1139 files changed, 0 insertions, 527531 deletions

diff --git a/common/recipes-kernel/linux/files/0001-drm-Remove-unused-fbdev_list-members.patch b/common/recipes-kernel/linux/files/0001-drm-Remove-unused-fbdev_list-members.patch
deleted file mode 100644
index ac621aaf..00000000
--- a/common/recipes-kernel/linux/files/0001-drm-Remove-unused-fbdev_list-members.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 327138e09ccd825e24563b7fa787a3c50bb2c39f Mon Sep 17 00:00:00 2001
-From: Lukas Wunner <lukas@wunner.de>
-Date: Sun, 1 Nov 2015 14:22:00 +0100
-Subject: [PATCH 0001/1110] drm: Remove unused fbdev_list members
-
-I noticed that intel_fbdev->our_mode is unused. Introduced by
-79e539453b34 ("DRM: i915: add mode setting support").
-
-Then I noticed that intel_fbdev->fbdev_list is unused as well.
-Introduced by 386516744ba4 ("drm/fb: fix fbdev object model +
-cleanup properly.") in i915, nouveau and radeon.
-
-Subsequently cargo culted to amdgpu, ast, cirrus, qxl, udl,
-virtio and mgag200.
-
-Already removed from the latter with cc59487a05b1 ("drm/mgag200:
-'fbdev_list' in 'struct mga_fbdev' is not used").
-
-Remove it from the others.
-
-Signed-off-by: Lukas Wunner <lukas@wunner.de>
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-index 093a8c6..6fcbbcc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-@@ -45,7 +45,6 @@
- struct amdgpu_fbdev {
- 	struct drm_fb_helper helper;
- 	struct amdgpu_framebuffer rfb;
--	struct list_head fbdev_list;
- 	struct amdgpu_device *adev;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch b/common/recipes-kernel/linux/files/0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch
deleted file mode 100644
index a1094e76..00000000
--- a/common/recipes-kernel/linux/files/0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch
+++ /dev/null
@@ -1,801 +0,0 @@
-From 82abea15da5d7483c84071c43ad223d14f0a6cdd Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 22 Nov 2016 17:54:08 +0500
-Subject: [PATCH] random: replace non-blocking pool with a Chacha20-based CRNG
-
-The CRNG is faster, and we don't pretend to track entropy usage in the
-CRNG any more.
-
-Signed-off-by: Theodore Ts'o <tytso@mit.edu>
-Backport-by: Awais Belal <awais_belal@mentor.com>
----
- crypto/chacha20_generic.c |  61 --------
- drivers/char/random.c     | 378 +++++++++++++++++++++++++++++++++-------------
- include/crypto/chacha20.h |   1 +
- lib/Makefile              |   2 +-
- lib/chacha20.c            |  79 ++++++++++
- 5 files changed, 357 insertions(+), 164 deletions(-)
- create mode 100644 lib/chacha20.c
-
-diff --git a/crypto/chacha20_generic.c b/crypto/chacha20_generic.c
-index da9c899..1cab831 100644
---- a/crypto/chacha20_generic.c
-+++ b/crypto/chacha20_generic.c
-@@ -15,72 +15,11 @@
- #include <linux/module.h>
- #include <crypto/chacha20.h>
- 
--static inline u32 rotl32(u32 v, u8 n)
--{
--	return (v << n) | (v >> (sizeof(v) * 8 - n));
--}
--
- static inline u32 le32_to_cpuvp(const void *p)
- {
- 	return le32_to_cpup(p);
- }
- 
--static void chacha20_block(u32 *state, void *stream)
--{
--	u32 x[16], *out = stream;
--	int i;
--
--	for (i = 0; i < ARRAY_SIZE(x); i++)
--		x[i] = state[i];
--
--	for (i = 0; i < 20; i += 2) {
--		x[0]  += x[4];    x[12] = rotl32(x[12] ^ x[0],  16);
--		x[1]  += x[5];    x[13] = rotl32(x[13] ^ x[1],  16);
--		x[2]  += x[6];    x[14] = rotl32(x[14] ^ x[2],  16);
--		x[3]  += x[7];    x[15] = rotl32(x[15] ^ x[3],  16);
--
--		x[8]  += x[12];   x[4]  = rotl32(x[4]  ^ x[8],  12);
--		x[9]  += x[13];   x[5]  = rotl32(x[5]  ^ x[9],  12);
--		x[10] += x[14];   x[6]  = rotl32(x[6]  ^ x[10], 12);
--		x[11] += x[15];   x[7]  = rotl32(x[7]  ^ x[11], 12);
--
--		x[0]  += x[4];    x[12] = rotl32(x[12] ^ x[0],   8);
--		x[1]  += x[5];    x[13] = rotl32(x[13] ^ x[1],   8);
--		x[2]  += x[6];    x[14] = rotl32(x[14] ^ x[2],   8);
--		x[3]  += x[7];    x[15] = rotl32(x[15] ^ x[3],   8);
--
--		x[8]  += x[12];   x[4]  = rotl32(x[4]  ^ x[8],   7);
--		x[9]  += x[13];   x[5]  = rotl32(x[5]  ^ x[9],   7);
--		x[10] += x[14];   x[6]  = rotl32(x[6]  ^ x[10],  7);
--		x[11] += x[15];   x[7]  = rotl32(x[7]  ^ x[11],  7);
--
--		x[0]  += x[5];    x[15] = rotl32(x[15] ^ x[0],  16);
--		x[1]  += x[6];    x[12] = rotl32(x[12] ^ x[1],  16);
--		x[2]  += x[7];    x[13] = rotl32(x[13] ^ x[2],  16);
--		x[3]  += x[4];    x[14] = rotl32(x[14] ^ x[3],  16);
--
--		x[10] += x[15];   x[5]  = rotl32(x[5]  ^ x[10], 12);
--		x[11] += x[12];   x[6]  = rotl32(x[6]  ^ x[11], 12);
--		x[8]  += x[13];   x[7]  = rotl32(x[7]  ^ x[8],  12);
--		x[9]  += x[14];   x[4]  = rotl32(x[4]  ^ x[9],  12);
--
--		x[0]  += x[5];    x[15] = rotl32(x[15] ^ x[0],   8);
--		x[1]  += x[6];    x[12] = rotl32(x[12] ^ x[1],   8);
--		x[2]  += x[7];    x[13] = rotl32(x[13] ^ x[2],   8);
--		x[3]  += x[4];    x[14] = rotl32(x[14] ^ x[3],   8);
--
--		x[10] += x[15];   x[5]  = rotl32(x[5]  ^ x[10],  7);
--		x[11] += x[12];   x[6]  = rotl32(x[6]  ^ x[11],  7);
--		x[8]  += x[13];   x[7]  = rotl32(x[7]  ^ x[8],   7);
--		x[9]  += x[14];   x[4]  = rotl32(x[4]  ^ x[9],   7);
--	}
--
--	for (i = 0; i < ARRAY_SIZE(x); i++)
--		out[i] = cpu_to_le32(x[i] + state[i]);
--
--	state[12]++;
--}
--
- static void chacha20_docrypt(u32 *state, u8 *dst, const u8 *src,
- 			     unsigned int bytes)
- {
-diff --git a/drivers/char/random.c b/drivers/char/random.c
-index 491a4dc..9088000 100644
---- a/drivers/char/random.c
-+++ b/drivers/char/random.c
-@@ -260,6 +260,7 @@
- #include <linux/irq.h>
- #include <linux/syscalls.h>
- #include <linux/completion.h>
-+#include <crypto/chacha20.h>
- 
- #include <asm/processor.h>
- #include <asm/uaccess.h>
-@@ -412,6 +413,31 @@ static struct fasync_struct *fasync;
- static DEFINE_SPINLOCK(random_ready_list_lock);
- static LIST_HEAD(random_ready_list);
- 
-+struct crng_state {
-+	__u32		state[16];
-+	unsigned long	init_time;
-+	spinlock_t	lock;
-+};
-+
-+struct crng_state primary_crng = {
-+	.lock = __SPIN_LOCK_UNLOCKED(primary_crng.lock),
-+};
-+
-+/*
-+ * crng_init =  0 --> Uninitialized
-+ *		1 --> Initialized
-+ *		2 --> Initialized from input_pool
-+ *
-+ * crng_init is protected by primary_crng->lock, and only increases
-+ * its value (from 0->1->2).
-+ */
-+static int crng_init = 0;
-+#define crng_ready() (likely(crng_init > 0))
-+static int crng_init_cnt = 0;
-+#define CRNG_INIT_CNT_THRESH (2*CHACHA20_KEY_SIZE)
-+static void extract_crng(__u8 out[CHACHA20_BLOCK_SIZE]);
-+static void process_random_ready_list(void);
-+
- /**********************************************************************
-  *
-  * OS independent entropy store.   Here are the functions which handle
-@@ -441,10 +467,15 @@ struct entropy_store {
- 	__u8 last_data[EXTRACT_SIZE];
- };
- 
-+static ssize_t extract_entropy(struct entropy_store *r, void *buf,
-+			       size_t nbytes, int min, int rsvd);
-+static ssize_t _extract_entropy(struct entropy_store *r, void *buf,
-+				size_t nbytes, int fips);
-+
-+static void crng_reseed(struct crng_state *crng, struct entropy_store *r);
- static void push_to_pool(struct work_struct *work);
- static __u32 input_pool_data[INPUT_POOL_WORDS];
- static __u32 blocking_pool_data[OUTPUT_POOL_WORDS];
--static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS];
- 
- static struct entropy_store input_pool = {
- 	.poolinfo = &poolinfo_table[0],
-@@ -465,16 +496,6 @@ static struct entropy_store blocking_pool = {
- 					push_to_pool),
- };
- 
--static struct entropy_store nonblocking_pool = {
--	.poolinfo = &poolinfo_table[1],
--	.name = "nonblocking",
--	.pull = &input_pool,
--	.lock = __SPIN_LOCK_UNLOCKED(nonblocking_pool.lock),
--	.pool = nonblocking_pool_data,
--	.push_work = __WORK_INITIALIZER(nonblocking_pool.push_work,
--					push_to_pool),
--};
--
- static __u32 const twist_table[8] = {
- 	0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158,
- 	0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 };
-@@ -677,12 +698,6 @@ retry:
- 	if (!r->initialized && r->entropy_total > 128) {
- 		r->initialized = 1;
- 		r->entropy_total = 0;
--		if (r == &nonblocking_pool) {
--			prandom_reseed_late();
--			process_random_ready_list();
--			wake_up_all(&urandom_init_wait);
--			pr_notice("random: %s pool is initialized\n", r->name);
--		}
- 	}
- 
- 	trace_credit_entropy_bits(r->name, nbits,
-@@ -692,30 +707,27 @@ retry:
- 	if (r == &input_pool) {
- 		int entropy_bits = entropy_count >> ENTROPY_SHIFT;
- 
-+		if (crng_init < 2 && entropy_bits >= 128) {
-+			crng_reseed(&primary_crng, r);
-+			entropy_bits = r->entropy_count >> ENTROPY_SHIFT;
-+		}
-+
- 		/* should we wake readers? */
- 		if (entropy_bits >= random_read_wakeup_bits) {
- 			wake_up_interruptible(&random_read_wait);
- 			kill_fasync(&fasync, SIGIO, POLL_IN);
- 		}
- 		/* If the input pool is getting full, send some
--		 * entropy to the two output pools, flipping back and
--		 * forth between them, until the output pools are 75%
--		 * full.
-+		 * entropy to the blocking pool until it is 75% full.
- 		 */
- 		if (entropy_bits > random_write_wakeup_bits &&
- 		    r->initialized &&
- 		    r->entropy_total >= 2*random_read_wakeup_bits) {
--			static struct entropy_store *last = &blocking_pool;
- 			struct entropy_store *other = &blocking_pool;
- 
--			if (last == &blocking_pool)
--				other = &nonblocking_pool;
- 			if (other->entropy_count <=
--			    3 * other->poolinfo->poolfracbits / 4)
--				last = other;
--			if (last->entropy_count <=
--			    3 * last->poolinfo->poolfracbits / 4) {
--				schedule_work(&last->push_work);
-+			    3 * other->poolinfo->poolfracbits / 4) {
-+				schedule_work(&other->push_work);
- 				r->entropy_total = 0;
- 			}
- 		}
-@@ -738,6 +750,152 @@ static int credit_entropy_bits_safe(struct entropy_store *r, int nbits)
- 
- /*********************************************************************
-  *
-+ * CRNG using CHACHA20
-+ *
-+ *********************************************************************/
-+
-+#define CRNG_RESEED_INTERVAL (300*HZ)
-+
-+static DECLARE_WAIT_QUEUE_HEAD(crng_init_wait);
-+
-+static void crng_initialize(struct crng_state *crng)
-+{
-+	int		i;
-+	unsigned long	rv;
-+
-+	memcpy(&crng->state[0], "expand 32-byte k", 16);
-+	if (crng == &primary_crng)
-+		_extract_entropy(&input_pool, &crng->state[4],
-+				 sizeof(__u32) * 12, 0);
-+	else
-+		get_random_bytes(&crng->state[4], sizeof(__u32) * 12);
-+	for (i = 4; i < 16; i++) {
-+		if (!arch_get_random_seed_long(&rv) &&
-+		    !arch_get_random_long(&rv))
-+			rv = random_get_entropy();
-+		crng->state[i] ^= rv;
-+	}
-+	crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
-+}
-+
-+static int crng_fast_load(const char *cp, size_t len)
-+{
-+	unsigned long flags;
-+	char *p;
-+
-+	if (!spin_trylock_irqsave(&primary_crng.lock, flags))
-+		return 0;
-+	if (crng_ready()) {
-+		spin_unlock_irqrestore(&primary_crng.lock, flags);
-+		return 0;
-+	}
-+	p = (unsigned char *) &primary_crng.state[4];
-+	while (len > 0 && crng_init_cnt < CRNG_INIT_CNT_THRESH) {
-+		p[crng_init_cnt % CHACHA20_KEY_SIZE] ^= *cp;
-+		cp++; crng_init_cnt++; len--;
-+	}
-+	if (crng_init_cnt >= CRNG_INIT_CNT_THRESH) {
-+		crng_init = 1;
-+		wake_up_interruptible(&crng_init_wait);
-+		pr_notice("random: fast init done\n");
-+	}
-+	spin_unlock_irqrestore(&primary_crng.lock, flags);
-+	return 1;
-+}
-+
-+static void crng_reseed(struct crng_state *crng, struct entropy_store *r)
-+{
-+	unsigned long	flags;
-+	int		i, num;
-+	union {
-+		__u8	block[CHACHA20_BLOCK_SIZE];
-+		__u32	key[8];
-+	} buf;
-+
-+	if (r) {
-+		num = extract_entropy(r, &buf, 32, 16, 0);
-+		if (num == 0)
-+			return;
-+	} else
-+		extract_crng(buf.block);
-+	spin_lock_irqsave(&primary_crng.lock, flags);
-+	for (i = 0; i < 8; i++) {
-+		unsigned long	rv;
-+		if (!arch_get_random_seed_long(&rv) &&
-+		    !arch_get_random_long(&rv))
-+			rv = random_get_entropy();
-+		crng->state[i+4] ^= buf.key[i] ^ rv;
-+	}
-+	memzero_explicit(&buf, sizeof(buf));
-+	crng->init_time = jiffies;
-+	if (crng == &primary_crng && crng_init < 2) {
-+		crng_init = 2;
-+		process_random_ready_list();
-+		wake_up_interruptible(&crng_init_wait);
-+		pr_notice("random: crng init done\n");
-+	}
-+	spin_unlock_irqrestore(&primary_crng.lock, flags);
-+}
-+
-+static inline void crng_wait_ready(void)
-+{
-+	wait_event_interruptible(crng_init_wait, crng_ready());
-+}
-+
-+static void extract_crng(__u8 out[CHACHA20_BLOCK_SIZE])
-+{
-+	unsigned long v, flags;
-+	struct crng_state *crng = &primary_crng;
-+
-+	if (crng_init > 1 &&
-+	    time_after(jiffies, crng->init_time + CRNG_RESEED_INTERVAL))
-+		crng_reseed(crng, &input_pool);
-+	spin_lock_irqsave(&crng->lock, flags);
-+	if (arch_get_random_long(&v))
-+		crng->state[14] ^= v;
-+	chacha20_block(&crng->state[0], out);
-+	if (crng->state[12] == 0)
-+		crng->state[13]++;
-+	spin_unlock_irqrestore(&crng->lock, flags);
-+}
-+
-+static ssize_t extract_crng_user(void __user *buf, size_t nbytes)
-+{
-+	ssize_t ret = 0, i;
-+	__u8 tmp[CHACHA20_BLOCK_SIZE];
-+	int large_request = (nbytes > 256);
-+
-+	while (nbytes) {
-+		if (large_request && need_resched()) {
-+			if (signal_pending(current)) {
-+				if (ret == 0)
-+					ret = -ERESTARTSYS;
-+				break;
-+			}
-+			schedule();
-+		}
-+
-+		extract_crng(tmp);
-+		i = min_t(int, nbytes, CHACHA20_BLOCK_SIZE);
-+		if (copy_to_user(buf, tmp, i)) {
-+			ret = -EFAULT;
-+			break;
-+		}
-+
-+		nbytes -= i;
-+		buf += i;
-+		ret += i;
-+	}
-+
-+	/* Wipe data just written to memory */
-+	memzero_explicit(tmp, sizeof(tmp));
-+
-+	return ret;
-+}
-+
-+
-+/*********************************************************************
-+ *
-  * Entropy input management
-  *
-  *********************************************************************/
-@@ -752,12 +910,12 @@ struct timer_rand_state {
- #define INIT_TIMER_RAND_STATE { INITIAL_JIFFIES, };
- 
- /*
-- * Add device- or boot-specific data to the input and nonblocking
-- * pools to help initialize them to unique values.
-+ * Add device- or boot-specific data to the input pool to help
-+ * initialize it.
-  *
-- * None of this adds any entropy, it is meant to avoid the
-- * problem of the nonblocking pool having similar initial state
-- * across largely identical devices.
-+ * None of this adds any entropy; it is meant to avoid the problem of
-+ * the entropy pool having similar initial state across largely
-+ * identical devices.
-  */
- void add_device_randomness(const void *buf, unsigned int size)
- {
-@@ -769,11 +927,6 @@ void add_device_randomness(const void *buf, unsigned int size)
- 	_mix_pool_bytes(&input_pool, buf, size);
- 	_mix_pool_bytes(&input_pool, &time, sizeof(time));
- 	spin_unlock_irqrestore(&input_pool.lock, flags);
--
--	spin_lock_irqsave(&nonblocking_pool.lock, flags);
--	_mix_pool_bytes(&nonblocking_pool, buf, size);
--	_mix_pool_bytes(&nonblocking_pool, &time, sizeof(time));
--	spin_unlock_irqrestore(&nonblocking_pool.lock, flags);
- }
- EXPORT_SYMBOL(add_device_randomness);
- 
-@@ -804,7 +957,7 @@ static void add_timer_randomness(struct timer_rand_state *state, unsigned num)
- 	sample.jiffies = jiffies;
- 	sample.cycles = random_get_entropy();
- 	sample.num = num;
--	r = nonblocking_pool.initialized ? &input_pool : &nonblocking_pool;
-+	r = &input_pool;
- 	mix_pool_bytes(r, &sample, sizeof(sample));
- 
- 	/*
-@@ -920,11 +1073,21 @@ void add_interrupt_randomness(int irq, int irq_flags)
- 	fast_mix(fast_pool);
- 	add_interrupt_bench(cycles);
- 
-+	if (!crng_ready()) {
-+		if ((fast_pool->count >= 64) &&
-+		    crng_fast_load((char *) fast_pool->pool,
-+				   sizeof(fast_pool->pool))) {
-+			fast_pool->count = 0;
-+			fast_pool->last = now;
-+		}
-+		return;
-+	}
-+
- 	if ((fast_pool->count < 64) &&
- 	    !time_after(now, fast_pool->last + HZ))
- 		return;
- 
--	r = nonblocking_pool.initialized ? &input_pool : &nonblocking_pool;
-+	r = &input_pool;
- 	if (!spin_trylock(&r->lock))
- 		return;
- 
-@@ -968,9 +1131,6 @@ EXPORT_SYMBOL_GPL(add_disk_randomness);
-  *
-  *********************************************************************/
- 
--static ssize_t extract_entropy(struct entropy_store *r, void *buf,
--			       size_t nbytes, int min, int rsvd);
--
- /*
-  * This utility inline function is responsible for transferring entropy
-  * from the primary pool to the secondary extraction pool. We make
-@@ -1145,6 +1305,36 @@ static void extract_buf(struct entropy_store *r, __u8 *out)
- 	memzero_explicit(&hash, sizeof(hash));
- }
- 
-+static ssize_t _extract_entropy(struct entropy_store *r, void *buf,
-+				size_t nbytes, int fips)
-+{
-+	ssize_t ret = 0, i;
-+	__u8 tmp[EXTRACT_SIZE];
-+	unsigned long flags;
-+
-+	while (nbytes) {
-+		extract_buf(r, tmp);
-+
-+		if (fips) {
-+			spin_lock_irqsave(&r->lock, flags);
-+			if (!memcmp(tmp, r->last_data, EXTRACT_SIZE))
-+				panic("Hardware RNG duplicated output!\n");
-+			memcpy(r->last_data, tmp, EXTRACT_SIZE);
-+			spin_unlock_irqrestore(&r->lock, flags);
-+		}
-+		i = min_t(int, nbytes, EXTRACT_SIZE);
-+		memcpy(buf, tmp, i);
-+		nbytes -= i;
-+		buf += i;
-+		ret += i;
-+	}
-+
-+	/* Wipe data just returned from memory */
-+	memzero_explicit(tmp, sizeof(tmp));
-+
-+	return ret;
-+}
-+
- /*
-  * This function extracts randomness from the "entropy pool", and
-  * returns it in a buffer.
-@@ -1157,7 +1347,6 @@ static void extract_buf(struct entropy_store *r, __u8 *out)
- static ssize_t extract_entropy(struct entropy_store *r, void *buf,
- 				 size_t nbytes, int min, int reserved)
- {
--	ssize_t ret = 0, i;
- 	__u8 tmp[EXTRACT_SIZE];
- 	unsigned long flags;
- 
-@@ -1181,27 +1370,7 @@ static ssize_t extract_entropy(struct entropy_store *r, void *buf,
- 	xfer_secondary_pool(r, nbytes);
- 	nbytes = account(r, nbytes, min, reserved);
- 
--	while (nbytes) {
--		extract_buf(r, tmp);
--
--		if (fips_enabled) {
--			spin_lock_irqsave(&r->lock, flags);
--			if (!memcmp(tmp, r->last_data, EXTRACT_SIZE))
--				panic("Hardware RNG duplicated output!\n");
--			memcpy(r->last_data, tmp, EXTRACT_SIZE);
--			spin_unlock_irqrestore(&r->lock, flags);
--		}
--		i = min_t(int, nbytes, EXTRACT_SIZE);
--		memcpy(buf, tmp, i);
--		nbytes -= i;
--		buf += i;
--		ret += i;
--	}
--
--	/* Wipe data just returned from memory */
--	memzero_explicit(tmp, sizeof(tmp));
--
--	return ret;
-+	return _extract_entropy(r, buf, nbytes, fips_enabled);
- }
- 
- /*
-@@ -1256,15 +1425,26 @@ static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf,
-  */
- void get_random_bytes(void *buf, int nbytes)
- {
-+	__u8 tmp[CHACHA20_BLOCK_SIZE];
-+
- #if DEBUG_RANDOM_BOOT > 0
--	if (unlikely(nonblocking_pool.initialized == 0))
-+	if (!crng_ready())
- 		printk(KERN_NOTICE "random: %pF get_random_bytes called "
--		       "with %d bits of entropy available\n",
--		       (void *) _RET_IP_,
--		       nonblocking_pool.entropy_total);
-+		       "with crng_init = %d\n", (void *) _RET_IP_, crng_init);
- #endif
- 	trace_get_random_bytes(nbytes, _RET_IP_);
--	extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0);
-+
-+	while (nbytes >= CHACHA20_BLOCK_SIZE) {
-+		extract_crng(buf);
-+		buf += CHACHA20_BLOCK_SIZE;
-+		nbytes -= CHACHA20_BLOCK_SIZE;
-+	}
-+
-+	if (nbytes > 0) {
-+		extract_crng(tmp);
-+		memcpy(buf, tmp, nbytes);
-+		memzero_explicit(tmp, nbytes);
-+	}
- }
- EXPORT_SYMBOL(get_random_bytes);
- 
-@@ -1282,7 +1462,7 @@ int add_random_ready_callback(struct random_ready_callback *rdy)
- 	unsigned long flags;
- 	int err = -EALREADY;
- 
--	if (likely(nonblocking_pool.initialized))
-+	if (crng_ready())
- 		return err;
- 
- 	owner = rdy->owner;
-@@ -1290,7 +1470,7 @@ int add_random_ready_callback(struct random_ready_callback *rdy)
- 		return -ENOENT;
- 
- 	spin_lock_irqsave(&random_ready_list_lock, flags);
--	if (nonblocking_pool.initialized)
-+	if (crng_ready())
- 		goto out;
- 
- 	owner = NULL;
-@@ -1354,7 +1534,7 @@ void get_random_bytes_arch(void *buf, int nbytes)
- 	}
- 
- 	if (nbytes)
--		extract_entropy(&nonblocking_pool, p, nbytes, 0, 0);
-+		get_random_bytes(p, nbytes);
- }
- EXPORT_SYMBOL(get_random_bytes_arch);
- 
-@@ -1399,7 +1579,7 @@ static int rand_initialize(void)
- {
- 	init_std_data(&input_pool);
- 	init_std_data(&blocking_pool);
--	init_std_data(&nonblocking_pool);
-+	crng_initialize(&primary_crng);
- 	return 0;
- }
- early_initcall(rand_initialize);
-@@ -1461,22 +1641,22 @@ random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
- static ssize_t
- urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
- {
-+	unsigned long flags;
- 	static int maxwarn = 10;
- 	int ret;
- 
--	if (unlikely(nonblocking_pool.initialized == 0) &&
--	    maxwarn > 0) {
-+	if (!crng_ready() && maxwarn > 0) {
- 		maxwarn--;
- 		printk(KERN_NOTICE "random: %s: uninitialized urandom read "
--		       "(%zd bytes read, %d bits of entropy available)\n",
--		       current->comm, nbytes, nonblocking_pool.entropy_total);
-+		       "(%zd bytes read)\n",
-+		       current->comm, nbytes);
-+		spin_lock_irqsave(&primary_crng.lock, flags);
-+		crng_init_cnt = 0;
-+		spin_unlock_irqrestore(&primary_crng.lock, flags);
- 	}
--
- 	nbytes = min_t(size_t, nbytes, INT_MAX >> (ENTROPY_SHIFT + 3));
--	ret = extract_entropy_user(&nonblocking_pool, buf, nbytes);
--
--	trace_urandom_read(8 * nbytes, ENTROPY_BITS(&nonblocking_pool),
--			   ENTROPY_BITS(&input_pool));
-+	ret = extract_crng_user(buf, nbytes);
-+	trace_urandom_read(8 * nbytes, 0, ENTROPY_BITS(&input_pool));
- 	return ret;
- }
- 
-@@ -1522,10 +1702,7 @@ static ssize_t random_write(struct file *file, const char __user *buffer,
- {
- 	size_t ret;
- 
--	ret = write_pool(&blocking_pool, buffer, count);
--	if (ret)
--		return ret;
--	ret = write_pool(&nonblocking_pool, buffer, count);
-+	ret = write_pool(&input_pool, buffer, count);
- 	if (ret)
- 		return ret;
- 
-@@ -1574,7 +1751,6 @@ static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
- 		if (!capable(CAP_SYS_ADMIN))
- 			return -EPERM;
- 		input_pool.entropy_count = 0;
--		nonblocking_pool.entropy_count = 0;
- 		blocking_pool.entropy_count = 0;
- 		return 0;
- 	default:
-@@ -1616,11 +1792,10 @@ SYSCALL_DEFINE3(getrandom, char __user *, buf, size_t, count,
- 	if (flags & GRND_RANDOM)
- 		return _random_read(flags & GRND_NONBLOCK, buf, count);
- 
--	if (unlikely(nonblocking_pool.initialized == 0)) {
-+	if (!crng_ready()) {
- 		if (flags & GRND_NONBLOCK)
- 			return -EAGAIN;
--		wait_event_interruptible(urandom_init_wait,
--					 nonblocking_pool.initialized);
-+		crng_wait_ready();
- 		if (signal_pending(current))
- 			return -ERESTARTSYS;
- 	}
-@@ -1852,18 +2027,17 @@ void add_hwgenerator_randomness(const char *buffer, size_t count,
- {
- 	struct entropy_store *poolp = &input_pool;
- 
--	if (unlikely(nonblocking_pool.initialized == 0))
--		poolp = &nonblocking_pool;
--	else {
--		/* Suspend writing if we're above the trickle
--		 * threshold.  We'll be woken up again once below
--		 * random_write_wakeup_thresh, or when the calling
--		 * thread is about to terminate.
--		 */
--		wait_event_interruptible(random_write_wait,
--					 kthread_should_stop() ||
--			ENTROPY_BITS(&input_pool) <= random_write_wakeup_bits);
-+	if (!crng_ready()) {
-+		crng_fast_load(buffer, count);
-+		return;
- 	}
-+
-+	/* Suspend writing if we're above the trickle threshold.
-+	 * We'll be woken up again once below random_write_wakeup_thresh,
-+	 * or when the calling thread is about to terminate.
-+	 */
-+	wait_event_interruptible(random_write_wait, kthread_should_stop() ||
-+			ENTROPY_BITS(&input_pool) <= random_write_wakeup_bits);
- 	mix_pool_bytes(poolp, buffer, count);
- 	credit_entropy_bits(poolp, entropy);
- }
-diff --git a/include/crypto/chacha20.h b/include/crypto/chacha20.h
-index 274bbae..20d20f6 100644
---- a/include/crypto/chacha20.h
-+++ b/include/crypto/chacha20.h
-@@ -16,6 +16,7 @@ struct chacha20_ctx {
- 	u32 key[8];
- };
- 
-+void chacha20_block(u32 *state, void *stream);
- void crypto_chacha20_init(u32 *state, struct chacha20_ctx *ctx, u8 *iv);
- int crypto_chacha20_setkey(struct crypto_tfm *tfm, const u8 *key,
- 			   unsigned int keysize);
-diff --git a/lib/Makefile b/lib/Makefile
-index 7f1de26..0f465dc 100644
---- a/lib/Makefile
-+++ b/lib/Makefile
-@@ -10,7 +10,7 @@ endif
- lib-y := ctype.o string.o vsprintf.o cmdline.o \
- 	 rbtree.o radix-tree.o dump_stack.o timerqueue.o\
- 	 idr.o int_sqrt.o extable.o \
--	 sha1.o md5.o irq_regs.o argv_split.o \
-+	 sha1.o chacha20.o md5.o irq_regs.o argv_split.o \
- 	 proportions.o flex_proportions.o ratelimit.o show_mem.o \
- 	 is_single_threaded.o plist.o decompress.o kobject_uevent.o \
- 	 earlycpio.o seq_buf.o nmi_backtrace.o
-diff --git a/lib/chacha20.c b/lib/chacha20.c
-new file mode 100644
-index 0000000..250ceed
---- /dev/null
-+++ b/lib/chacha20.c
-@@ -0,0 +1,79 @@
-+/*
-+ * ChaCha20 256-bit cipher algorithm, RFC7539
-+ *
-+ * Copyright (C) 2015 Martin Willi
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/export.h>
-+#include <linux/bitops.h>
-+#include <linux/cryptohash.h>
-+#include <asm/unaligned.h>
-+#include <crypto/chacha20.h>
-+
-+static inline u32 rotl32(u32 v, u8 n)
-+{
-+	return (v << n) | (v >> (sizeof(v) * 8 - n));
-+}
-+
-+extern void chacha20_block(u32 *state, void *stream)
-+{
-+	u32 x[16], *out = stream;
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(x); i++)
-+		x[i] = state[i];
-+
-+	for (i = 0; i < 20; i += 2) {
-+		x[0]  += x[4];    x[12] = rotl32(x[12] ^ x[0],  16);
-+		x[1]  += x[5];    x[13] = rotl32(x[13] ^ x[1],  16);
-+		x[2]  += x[6];    x[14] = rotl32(x[14] ^ x[2],  16);
-+		x[3]  += x[7];    x[15] = rotl32(x[15] ^ x[3],  16);
-+
-+		x[8]  += x[12];   x[4]  = rotl32(x[4]  ^ x[8],  12);
-+		x[9]  += x[13];   x[5]  = rotl32(x[5]  ^ x[9],  12);
-+		x[10] += x[14];   x[6]  = rotl32(x[6]  ^ x[10], 12);
-+		x[11] += x[15];   x[7]  = rotl32(x[7]  ^ x[11], 12);
-+
-+		x[0]  += x[4];    x[12] = rotl32(x[12] ^ x[0],   8);
-+		x[1]  += x[5];    x[13] = rotl32(x[13] ^ x[1],   8);
-+		x[2]  += x[6];    x[14] = rotl32(x[14] ^ x[2],   8);
-+		x[3]  += x[7];    x[15] = rotl32(x[15] ^ x[3],   8);
-+
-+		x[8]  += x[12];   x[4]  = rotl32(x[4]  ^ x[8],   7);
-+		x[9]  += x[13];   x[5]  = rotl32(x[5]  ^ x[9],   7);
-+		x[10] += x[14];   x[6]  = rotl32(x[6]  ^ x[10],  7);
-+		x[11] += x[15];   x[7]  = rotl32(x[7]  ^ x[11],  7);
-+
-+		x[0]  += x[5];    x[15] = rotl32(x[15] ^ x[0],  16);
-+		x[1]  += x[6];    x[12] = rotl32(x[12] ^ x[1],  16);
-+		x[2]  += x[7];    x[13] = rotl32(x[13] ^ x[2],  16);
-+		x[3]  += x[4];    x[14] = rotl32(x[14] ^ x[3],  16);
-+
-+		x[10] += x[15];   x[5]  = rotl32(x[5]  ^ x[10], 12);
-+		x[11] += x[12];   x[6]  = rotl32(x[6]  ^ x[11], 12);
-+		x[8]  += x[13];   x[7]  = rotl32(x[7]  ^ x[8],  12);
-+		x[9]  += x[14];   x[4]  = rotl32(x[4]  ^ x[9],  12);
-+
-+		x[0]  += x[5];    x[15] = rotl32(x[15] ^ x[0],   8);
-+		x[1]  += x[6];    x[12] = rotl32(x[12] ^ x[1],   8);
-+		x[2]  += x[7];    x[13] = rotl32(x[13] ^ x[2],   8);
-+		x[3]  += x[4];    x[14] = rotl32(x[14] ^ x[3],   8);
-+
-+		x[10] += x[15];   x[5]  = rotl32(x[5]  ^ x[10],  7);
-+		x[11] += x[12];   x[6]  = rotl32(x[6]  ^ x[11],  7);
-+		x[8]  += x[13];   x[7]  = rotl32(x[7]  ^ x[8],   7);
-+		x[9]  += x[14];   x[4]  = rotl32(x[4]  ^ x[9],   7);
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(x); i++)
-+		out[i] = cpu_to_le32(x[i] + state[i]);
-+
-+	state[12]++;
-+}
-+EXPORT_SYMBOL(chacha20_block);
--- 
-1.9.1
-
diff --git a/common/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch b/common/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch
deleted file mode 100644
index 570e7b85..00000000
--- a/common/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch
+++ /dev/null
@@ -1,432 +0,0 @@
-From 31f1e845c0d5d9fd243a6cf8d07fec822c335f88 Mon Sep 17 00:00:00 2001
-From: Sanjay R Mehta <sanju.mehta@amd.com>
-Date: Tue, 27 Sep 2016 16:13:05 +0530
-Subject: [PATCH 1/2] yocto amd staging add support to enable and disable IMC
- to fetch BIOS code
-
-Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
----
- drivers/staging/Kconfig           |   2 +
- drivers/staging/Makefile          |   1 +
- drivers/staging/amd_imc/Kconfig   |   9 ++
- drivers/staging/amd_imc/Makefile  |   1 +
- drivers/staging/amd_imc/amd_imc.c | 286 ++++++++++++++++++++++++++++++++++++++
- include/linux/amd_imc.h           |  69 +++++++++
- 6 files changed, 368 insertions(+)
- create mode 100644 drivers/staging/amd_imc/Kconfig
- create mode 100644 drivers/staging/amd_imc/Makefile
- create mode 100644 drivers/staging/amd_imc/amd_imc.c
- create mode 100644 include/linux/amd_imc.h
-
-diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
-index 5d3b86a..a6ee082 100644
---- a/drivers/staging/Kconfig
-+++ b/drivers/staging/Kconfig
-@@ -110,4 +110,6 @@ source "drivers/staging/wilc1000/Kconfig"
- 
- source "drivers/staging/most/Kconfig"
- 
-+source "drivers/staging/amd_imc/Kconfig"
-+
- endif # STAGING
-diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
-index 30918ed..4f31852 100644
---- a/drivers/staging/Makefile
-+++ b/drivers/staging/Makefile
-@@ -47,3 +47,4 @@ obj-$(CONFIG_FB_TFT)		+= fbtft/
- obj-$(CONFIG_FSL_MC_BUS)	+= fsl-mc/
- obj-$(CONFIG_WILC1000)		+= wilc1000/
- obj-$(CONFIG_MOST)		+= most/
-+obj-$(CONFIG_AMD_IMC)		+= amd_imc/
-diff --git a/drivers/staging/amd_imc/Kconfig b/drivers/staging/amd_imc/Kconfig
-new file mode 100644
-index 0000000..abfb724
---- /dev/null
-+++ b/drivers/staging/amd_imc/Kconfig
-@@ -0,0 +1,9 @@
-+config AMD_IMC
-+	bool "AMD Intergrated Micro Controller support"
-+	depends on PCI && X86_64
-+	default y
-+	---help---
-+	  This driver supports AMD Intergrated Micro Controller.
-+
-+	  To compile this driver as a module, choose M here. The module
-+	  will be called amd_imc.
-diff --git a/drivers/staging/amd_imc/Makefile b/drivers/staging/amd_imc/Makefile
-new file mode 100644
-index 0000000..c4837f8
---- /dev/null
-+++ b/drivers/staging/amd_imc/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_AMD_IMC) += amd_imc.o
-diff --git a/drivers/staging/amd_imc/amd_imc.c b/drivers/staging/amd_imc/amd_imc.c
-new file mode 100644
-index 0000000..1551bdb
---- /dev/null
-+++ b/drivers/staging/amd_imc/amd_imc.c
-@@ -0,0 +1,286 @@
-+/*****************************************************************************
-+*
-+* Copyright (c) 2014, Advanced Micro Devices, Inc.
-+* All rights reserved.
-+*
-+* Redistribution and use in source and binary forms, with or without
-+* modification, are permitted provided that the following conditions are met:
-+*     * Redistributions of source code must retain the above copyright
-+*       notice, this list of conditions and the following disclaimer.
-+*     * Redistributions in binary form must reproduce the above copyright
-+*       notice, this list of conditions and the following disclaimer in the
-+*       documentation and/or other materials provided with the distribution.
-+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-+*       its contributors may be used to endorse or promote products derived
-+*       from this software without specific prior written permission.
-+*
-+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*
-+*
-+***************************************************************************/
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/pci.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+#include <linux/io.h>
-+#include <linux/delay.h>
-+#include <linux/amd_imc.h>
-+
-+static int imc_enabled;
-+static u16 imc_port_addr;
-+static u8 msg_reg_base_hi;
-+static u8 msg_reg_base_lo;
-+static u16 msg_reg_base;
-+
-+static struct pci_dev *amd_imc_pci;
-+static struct platform_device *amd_imc_platform_device;
-+
-+static DEFINE_PCI_DEVICE_TABLE(amd_lpc_pci_tbl) = {
-+	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE, PCI_ANY_ID,
-+	 PCI_ANY_ID,},
-+	{}
-+};
-+
-+void amd_imc_enter_scratch_ram(void)
-+{
-+	u8 byte;
-+
-+	if (!imc_enabled)
-+		return;
-+
-+	/* Instruct IMC to enter scratch RAM */
-+	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	outb(0, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+	outb(AMD_MSG_REG1, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	outb(AMD_IMC_ENTER_SCRATCH_RAM, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+	outb(AMD_MSG_SYS_TO_IMC, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	outb(AMD_IMC_ROM_OWNERSHIP_SEM, msg_reg_base +
-+	     AMD_MSG_DATA_REG_OFFSET);
-+
-+	/* As per the spec, the firmware may take up to 50ms */
-+	msleep(50);
-+
-+	/* read message registger 0 to confirm function completion */
-+	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	byte = inb(msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+	if (byte == AMD_IMC_FUNC_NOT_SUPP)
-+		pr_info("amd_imc: %s not supported\n", __func__);
-+	else if (byte == AMD_IMC_FUNC_COMPLETED)
-+		pr_info("amd_imc: %s completed\n", __func__);
-+}
-+EXPORT_SYMBOL_GPL(amd_imc_enter_scratch_ram);
-+
-+void amd_imc_exit_scratch_ram(void)
-+{
-+	u8 byte;
-+
-+	if (!imc_enabled)
-+		return;
-+
-+	/* Instruct IMC to exit scratch RAM */
-+	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	outb(0, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+	outb(AMD_MSG_REG1, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	outb(AMD_IMC_ENTER_SCRATCH_RAM, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+	outb(AMD_MSG_SYS_TO_IMC, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	outb(AMD_IMC_ROM_OWNERSHIP_SEM, msg_reg_base +
-+	     AMD_MSG_DATA_REG_OFFSET);
-+
-+	/* As per the spec, the firmware may take up to 50ms */
-+	msleep(50);
-+
-+	/* read message registger 0 to confirm function completion */
-+	outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+	byte = inb(msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+	if (byte == AMD_IMC_FUNC_NOT_SUPP)
-+		pr_info("amd_imc: %s not supported\n", __func__);
-+	else if (byte == AMD_IMC_FUNC_COMPLETED)
-+		pr_info("amd_imc: %s completed\n", __func__);
-+}
-+EXPORT_SYMBOL_GPL(amd_imc_exit_scratch_ram);
-+
-+/*
-+* The PCI Device ID table below is used to identify the platform
-+* the driver is supposed to work for. Since this is a platform
-+* driver, we need a way for us to be able to find the correct
-+* platform when the driver gets loaded, otherwise we should
-+* bail out.
-+*/
-+static DEFINE_PCI_DEVICE_TABLE(amd_imc_pci_tbl) = {
-+	{ PCI_VENDOR_ID_AMD, 0x790B, PCI_ANY_ID,
-+	  PCI_ANY_ID, },
-+	{ 0, },
-+};
-+
-+static int amd_imc_init(struct platform_device *pdev)
-+{
-+	struct pci_dev *dev = NULL;
-+	static u32 imc_strap_status_phys;
-+	void __iomem *imcstrapstatus;
-+	u32 val;
-+
-+	/* Match the PCI device */
-+	for_each_pci_dev(dev) {
-+		if (pci_match_id(amd_imc_pci_tbl, dev) != NULL) {
-+			amd_imc_pci = dev;
-+			break;
-+		}
-+	}
-+
-+	if (!amd_imc_pci)
-+		return -ENODEV;
-+
-+
-+	/* ACPI MMIO Base Address */
-+	val = AMD_GPIO_ACPIMMIO_BASE;
-+
-+	/* IMCStrapStatus is located at ACPI MMIO Base Address + 0xE80 */
-+	if (!request_mem_region_exclusive(val + AMD_IMC_STRAP_STATUS_OFFSET,
-+	    AMD_IMC_STRAP_STATUS_SIZE, "IMC Strap Status")) {
-+		pr_err("amd_imc: MMIO address 0x%04x already in use\n",
-+			val + AMD_IMC_STRAP_STATUS_OFFSET);
-+		goto exit;
-+	}
-+
-+	imc_strap_status_phys = val + AMD_IMC_STRAP_STATUS_OFFSET;
-+
-+	imcstrapstatus = ioremap(imc_strap_status_phys,
-+				 AMD_IMC_STRAP_STATUS_SIZE);
-+	if (!imcstrapstatus) {
-+		pr_err("amd_imc: failed to get IMC Strap Status address\n");
-+		goto unreg_imc_region;
-+	}
-+
-+	/* Check if IMC is enabled */
-+	val = ioread32(imcstrapstatus);
-+	if ((val & AMD_IMC_ENABLED) == AMD_IMC_ENABLED) {
-+		struct pci_dev *pdev = NULL;
-+
-+		pr_info("amd_imc: IMC is enabled\n");
-+		imc_enabled = 1;
-+
-+		/*
-+		 * In case IMC is enabled, we need to find the IMC port address
-+		 * which will be used to send messages to the IMC. The IMC port
-+		 * address is stored in bits 1:15 of PCI device 20, function 3,
-+		 * offset 0xA4. PCI device 20, function 3 is actually the LPC
-+		 * ISA bridge.
-+		 */
-+		for_each_pci_dev(pdev) {
-+			if (pci_match_id(amd_lpc_pci_tbl, pdev) != NULL)
-+				break;
-+		}
-+
-+		/* Match found. Get the IMC port address */
-+		if (pdev) {
-+			pci_read_config_word(pdev, AMD_PCI_IMC_PORT_ADDR_REG,
-+					     &imc_port_addr);
-+
-+			/* The actual IMC port address has bit 0 masked out */
-+			imc_port_addr &= ~AMD_IMC_PORT_ACTIVE;
-+		}
-+
-+		/* Put device into configuration state */
-+		outb(AMD_DEVICE_ENTER_CONFIG_STATE, imc_port_addr +
-+		     AMD_IMC_INDEX_REG_OFFSET);
-+
-+		/* Select logical device number 9 */
-+		outb(AMD_SET_LOGICAL_DEVICE, imc_port_addr +
-+		     AMD_IMC_INDEX_REG_OFFSET);
-+		outb(AMD_SET_DEVICE_9, imc_port_addr +
-+		     AMD_IMC_DATA_REG_OFFSET);
-+
-+		/* read high byte of message register base address */
-+		outb(AMD_MSG_REG_HIGH, imc_port_addr +
-+		     AMD_IMC_INDEX_REG_OFFSET);
-+		msg_reg_base_hi = inb(imc_port_addr + AMD_IMC_DATA_REG_OFFSET);
-+
-+		/* read low byte of message register base address */
-+		outb(AMD_MSG_REG_LOW, imc_port_addr +
-+		     AMD_IMC_INDEX_REG_OFFSET);
-+		msg_reg_base_lo = inb(imc_port_addr + AMD_IMC_DATA_REG_OFFSET);
-+
-+		msg_reg_base = msg_reg_base_lo | (msg_reg_base_hi << 8);
-+
-+		/* Get device out of configuration state */
-+		outb(AMD_DEVICE_EXIT_CONFIG_STATE, imc_port_addr +
-+		     AMD_IMC_INDEX_REG_OFFSET);
-+	} else {
-+		pr_info("amd_imc: IMC is disabled\n");
-+		imc_enabled = 0;
-+	}
-+
-+	/* Release the region occupied by IMC Strap Status register */
-+	iounmap(imcstrapstatus);
-+	release_mem_region(imc_strap_status_phys, AMD_IMC_STRAP_STATUS_SIZE);
-+
-+	return 0;
-+
-+unreg_imc_region:
-+	release_mem_region(imc_strap_status_phys, AMD_IMC_STRAP_STATUS_SIZE);
-+exit:
-+	return -ENODEV;
-+}
-+
-+static struct platform_driver amd_imc_driver = {
-+	.probe		= amd_imc_init,
-+	.driver		= {
-+		.owner	= THIS_MODULE,
-+		.name	= IMC_MODULE_NAME,
-+	},
-+};
-+
-+static int __init amd_imc_init_module(void)
-+{
-+	int err;
-+
-+	pr_info("AMD IMC Driver v%s\n", IMC_VERSION);
-+
-+	err = platform_driver_register(&amd_imc_driver);
-+	if (err)
-+		return err;
-+
-+	amd_imc_platform_device = platform_device_register_simple(
-+					IMC_MODULE_NAME, -1, NULL, 0);
-+	if (IS_ERR(amd_imc_platform_device)) {
-+		err = PTR_ERR(amd_imc_platform_device);
-+		goto unreg_platform_driver;
-+	}
-+
-+	return 0;
-+
-+unreg_platform_driver:
-+	platform_driver_unregister(&amd_imc_driver);
-+	return err;
-+}
-+
-+static void __exit amd_imc_cleanup_module(void)
-+{
-+	platform_device_unregister(amd_imc_platform_device);
-+	platform_driver_unregister(&amd_imc_driver);
-+	pr_info("AMD IMC Module Unloaded\n");
-+}
-+
-+module_init(amd_imc_init_module);
-+module_exit(amd_imc_cleanup_module);
-+
-+MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
-+MODULE_DESCRIPTION("AMD IMC driver");
-+MODULE_LICENSE("Dual BSD/GPL");
-diff --git a/include/linux/amd_imc.h b/include/linux/amd_imc.h
-new file mode 100644
-index 0000000..b1c03bf
---- /dev/null
-+++ b/include/linux/amd_imc.h
-@@ -0,0 +1,69 @@
-+#ifndef _AMD_IMC_H_
-+#define _AMD_IMC_H_
-+
-+/* Module and version information */
-+#define IMC_VERSION "0.1"
-+#define IMC_MODULE_NAME "AMD IMC"
-+#define IMC_DRIVER_NAME   IMC_MODULE_NAME ", v" IMC_VERSION
-+
-+#define DRV_NAME "amd_imc"
-+
-+/* IO port address for indirect access using the ACPI PM registers */
-+#define AMD_IO_PM_INDEX_REG		0xCD6
-+#define AMD_IO_PM_DATA_REG		0xCD7
-+
-+#define AMD_GPIO_ACPIMMIO_BASE		0xFED80000
-+#define AMD_PM_ACPI_MMIO_BASE0		0x24
-+#define AMD_PM_ACPI_MMIO_BASE1		0x25
-+#define AMD_PM_ACPI_MMIO_BASE2		0x26
-+#define AMD_PM_ACPI_MMIO_BASE3		0x27
-+
-+#define AMD_ACPI_MMIO_ADDR_MASK		~0x1FFF
-+
-+/* Offset of IMC Strap Status register in the ACPI MMIO region */
-+#define AMD_IMC_STRAP_STATUS_OFFSET	0xE80
-+ #define AMD_IMC_ENABLED		0x4
-+#define AMD_IMC_STRAP_STATUS_SIZE	4
-+
-+#define PCI_DEVICE_ID_AMD_LPC_BRIDGE	0x790E
-+ #define AMD_PCI_IMC_PORT_ADDR_REG	0xA4
-+  #define AMD_IMC_PORT_ACTIVE		0x0001
-+
-+/* Device configuration state fields */
-+#define AMD_DEVICE_ENTER_CONFIG_STATE	0x5A
-+#define AMD_DEVICE_EXIT_CONFIG_STATE	0xA5
-+
-+/* Global configuration registers */
-+#define AMD_SET_LOGICAL_DEVICE		0x07
-+ #define AMD_SET_DEVICE_9		0x09
-+#define AMD_MSG_REG_HIGH		0x60
-+#define AMD_MSG_REG_LOW			0x61
-+
-+/* IMC index and data port offsets for indirect access */
-+#define AMD_IMC_INDEX_REG_OFFSET	0x00
-+#define AMD_IMC_DATA_REG_OFFSET		0x01
-+
-+/* Message register index and data port offsets for indirect access */
-+#define AMD_MSG_INDEX_REG_OFFSET	0x00
-+#define AMD_MSG_DATA_REG_OFFSET		0x01
-+
-+/* IMC message registers */
-+#define AMD_MSG_SYS_TO_IMC		0x80
-+ #define AMD_IMC_ROM_OWNERSHIP_SEM	0x96
-+#define AMD_MSG_REG0			0x82
-+ #define AMD_IMC_FUNC_NOT_SUPP		0x00
-+ #define AMD_IMC_FUNC_COMPLETED		0xFA
-+#define AMD_MSG_REG1			0x83
-+ #define AMD_IMC_ENTER_SCRATCH_RAM	0xB4
-+ #define AMD_IMC_EXIT_SCRATCH_RAM	0xB5
-+
-+/* Extern functions */
-+#ifdef CONFIG_AMD_IMC
-+extern void amd_imc_enter_scratch_ram(void);
-+extern void amd_imc_exit_scratch_ram(void);
-+#else
-+void amd_imc_enter_scratch_ram(void) {}
-+void amd_imc_exit_scratch_ram(void) {}
-+#endif
-+
-+#endif /* _AMD_IMC_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch b/common/recipes-kernel/linux/files/0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch
deleted file mode 100644
index 609e2d0f..00000000
--- a/common/recipes-kernel/linux/files/0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From e915ae9d87955964538402e0c5510d0161d0072f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
-Date: Wed, 11 Nov 2015 19:11:29 +0200
-Subject: [PATCH 0002/1110] drm: Pass the user drm_mode_fb_cmd2 as const to
- .fb_create()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Drivers shouldn't clobber the passed in addfb ioctl parameters.
-i915 was doing just that. To prevent it from happening again,
-pass the struct around as const, starting all the way from
-internal_framebuffer_create().
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h    | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index 82903ca..1846d65 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -530,7 +530,7 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
- int
- amdgpu_framebuffer_init(struct drm_device *dev,
- 			struct amdgpu_framebuffer *rfb,
--			struct drm_mode_fb_cmd2 *mode_cmd,
-+			const struct drm_mode_fb_cmd2 *mode_cmd,
- 			struct drm_gem_object *obj)
- {
- 	int ret;
-@@ -547,7 +547,7 @@ amdgpu_framebuffer_init(struct drm_device *dev,
- static struct drm_framebuffer *
- amdgpu_user_framebuffer_create(struct drm_device *dev,
- 			       struct drm_file *file_priv,
--			       struct drm_mode_fb_cmd2 *mode_cmd)
-+			       const struct drm_mode_fb_cmd2 *mode_cmd)
- {
- 	struct drm_gem_object *obj;
- 	struct amdgpu_framebuffer *amdgpu_fb;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 89df787..cfb48e3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -556,7 +556,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
- 
- int amdgpu_framebuffer_init(struct drm_device *dev,
- 			     struct amdgpu_framebuffer *rfb,
--			     struct drm_mode_fb_cmd2 *mode_cmd,
-+			     const struct drm_mode_fb_cmd2 *mode_cmd,
- 			     struct drm_gem_object *obj);
- 
- int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch b/common/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch
deleted file mode 100644
index c4aa7915..00000000
--- a/common/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 6d365974c73b25976a5c5b7572af2dab13ad39d0 Mon Sep 17 00:00:00 2001
-From: Sanjay R Mehta <sanju.mehta@amd.com>
-Date: Tue, 27 Sep 2016 16:14:53 +0530
-Subject: [PATCH 2/2] yocto amd i2c dev add calls to enable and disable IMC
- from fetching BIOS code
-
----
- drivers/i2c/i2c-dev.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
-index 2413ec9..6a3419d 100644
---- a/drivers/i2c/i2c-dev.c
-+++ b/drivers/i2c/i2c-dev.c
-@@ -34,6 +34,7 @@
- #include <linux/i2c-dev.h>
- #include <linux/jiffies.h>
- #include <linux/uaccess.h>
-+#include <linux/amd_imc.h>
- 
- /*
-  * An i2c_dev represents an i2c_adapter ... an I2C or SMBus master, not a
-@@ -510,6 +511,8 @@ static int i2cdev_open(struct inode *inode, struct file *file)
- 	client->adapter = adap;
- 	file->private_data = client;
- 
-+	amd_imc_enter_scratch_ram();
-+
- 	return 0;
- }
- 
-@@ -521,6 +524,8 @@ static int i2cdev_release(struct inode *inode, struct file *file)
- 	kfree(client);
- 	file->private_data = NULL;
- 
-+	amd_imc_exit_scratch_ram();
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0003-drm-amdgpu-use-src-in-Makefile-v2.patch b/common/recipes-kernel/linux/files/0003-drm-amdgpu-use-src-in-Makefile-v2.patch
deleted file mode 100644
index 57182375..00000000
--- a/common/recipes-kernel/linux/files/0003-drm-amdgpu-use-src-in-Makefile-v2.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 5275bdcecdd42926a65d16ad29b48414af476b46 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Tue, 24 Nov 2015 16:55:20 +0800
-Subject: [PATCH 0003/1110] drm/amdgpu: use $(src) in Makefile (v2)
-
-This can solve the path problem when compile amdgpu with DKMS.
-
-v2: agd: rebase on current drm-next
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile | 10 ++++++----
- 1 file changed, 6 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index ca06601..178fa15 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -2,10 +2,12 @@
- # Makefile for the drm device driver.  This driver provides support for the
- # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
- 
--ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg \
--	-Idrivers/gpu/drm/amd/include \
--	-Idrivers/gpu/drm/amd/amdgpu \
--	-Idrivers/gpu/drm/amd/scheduler
-+FULL_AMD_PATH=$(src)/..
-+
-+ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
-+	-I$(FULL_AMD_PATH)/include \
-+	-I$(FULL_AMD_PATH)/amdgpu \
-+	-I$(FULL_AMD_PATH)/scheduler
- 
- amdgpu-y := amdgpu_drv.o
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch b/common/recipes-kernel/linux/files/0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch
deleted file mode 100644
index 141a0235..00000000
--- a/common/recipes-kernel/linux/files/0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From a0a9b0026f51444eaf05073bc0b1c223adbb07bd Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 10:14:28 -0500
-Subject: [PATCH 0004/1110] drm/amdgpu: add a callback for reading the bios
- from the rom directly
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is necessary when the vbios image is not directly accessible via
-the rom BAR or legacy vga location.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 053fc2f..d313225 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1829,6 +1829,8 @@ struct amdgpu_cu_info {
-  */
- struct amdgpu_asic_funcs {
- 	bool (*read_disabled_bios)(struct amdgpu_device *adev);
-+	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
-+				   u8 *bios, u32 length_bytes);
- 	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
- 			     u32 sh_num, u32 reg_offset, u32 *value);
- 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
-@@ -2235,6 +2237,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
- #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
- #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
-+#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
- #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
- #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
- #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch b/common/recipes-kernel/linux/files/0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch
deleted file mode 100644
index f6e6f934..00000000
--- a/common/recipes-kernel/linux/files/0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From b24e766a5d73da9f5a4b51b31171a445298d6b1f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 10:34:45 -0500
-Subject: [PATCH 0005/1110] drm/amdgpu: add read_bios_from_rom callback for CI
- parts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read the vbios image directly from the rom.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik.c | 32 ++++++++++++++++++++++++++++++++
- 1 file changed, 32 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 484710c..61689f0 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -929,6 +929,37 @@ static bool cik_read_disabled_bios(struct amdgpu_device *adev)
- 	return r;
- }
- 
-+static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
-+				   u8 *bios, u32 length_bytes)
-+{
-+	u32 *dw_ptr;
-+	unsigned long flags;
-+	u32 i, length_dw;
-+
-+	if (bios == NULL)
-+		return false;
-+	if (length_bytes == 0)
-+		return false;
-+	/* APU vbios image is part of sbios image */
-+	if (adev->flags & AMD_IS_APU)
-+		return false;
-+
-+	dw_ptr = (u32 *)bios;
-+	length_dw = ALIGN(length_bytes, 4) / 4;
-+	/* take the smc lock since we are using the smc index */
-+	spin_lock_irqsave(&adev->smc_idx_lock, flags);
-+	/* set rom index to 0 */
-+	WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
-+	WREG32(mmSMC_IND_DATA_0, 0);
-+	/* set index to data for continous read */
-+	WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
-+	for (i = 0; i < length_dw; i++)
-+		dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
-+	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-+
-+	return true;
-+}
-+
- static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
- 	{mmGRBM_STATUS, false},
- 	{mmGB_ADDR_CONFIG, false},
-@@ -2267,6 +2298,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
- static const struct amdgpu_asic_funcs cik_asic_funcs =
- {
- 	.read_disabled_bios = &cik_read_disabled_bios,
-+	.read_bios_from_rom = &cik_read_bios_from_rom,
- 	.read_register = &cik_read_register,
- 	.reset = &cik_asic_reset,
- 	.set_vga_state = &cik_vga_set_state,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch b/common/recipes-kernel/linux/files/0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch
deleted file mode 100644
index 9d6a83de..00000000
--- a/common/recipes-kernel/linux/files/0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From b526555fa7a53776ff1925bd0bf9cef664134750 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 10:37:54 -0500
-Subject: [PATCH 0006/1110] drm/amdgpu: add read_bios_from_rom callback for VI
- parts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read the vbios image directly from the rom.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 3e9cbe3..0cb6f31 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -377,6 +377,38 @@ static bool vi_read_disabled_bios(struct amdgpu_device *adev)
- 	WREG32_SMC(ixROM_CNTL, rom_cntl);
- 	return r;
- }
-+
-+static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
-+				  u8 *bios, u32 length_bytes)
-+{
-+	u32 *dw_ptr;
-+	unsigned long flags;
-+	u32 i, length_dw;
-+
-+	if (bios == NULL)
-+		return false;
-+	if (length_bytes == 0)
-+		return false;
-+	/* APU vbios image is part of sbios image */
-+	if (adev->flags & AMD_IS_APU)
-+		return false;
-+
-+	dw_ptr = (u32 *)bios;
-+	length_dw = ALIGN(length_bytes, 4) / 4;
-+	/* take the smc lock since we are using the smc index */
-+	spin_lock_irqsave(&adev->smc_idx_lock, flags);
-+	/* set rom index to 0 */
-+	WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
-+	WREG32(mmSMC_IND_DATA_0, 0);
-+	/* set index to data for continous read */
-+	WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
-+	for (i = 0; i < length_dw; i++)
-+		dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
-+	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-+
-+	return true;
-+}
-+
- static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
- 	{mmGB_MACROTILE_MODE7, true},
- };
-@@ -1369,6 +1401,7 @@ static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
- static const struct amdgpu_asic_funcs vi_asic_funcs =
- {
- 	.read_disabled_bios = &vi_read_disabled_bios,
-+	.read_bios_from_rom = &vi_read_bios_from_rom,
- 	.read_register = &vi_read_register,
- 	.reset = &vi_asic_reset,
- 	.set_vga_state = &vi_vga_set_state,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch b/common/recipes-kernel/linux/files/0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch
deleted file mode 100644
index 43ed61bb..00000000
--- a/common/recipes-kernel/linux/files/0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch
+++ /dev/null
@@ -1,153 +0,0 @@
-From 4886ec68e93f0151fc681cf6f792fe1acba03814 Mon Sep 17 00:00:00 2001
-From: "monk.liu" <Monk.Liu@amd.com>
-Date: Thu, 29 Oct 2015 15:33:06 +0800
-Subject: [PATCH 0007/1110] drm/amdgpu: Use new read bios from rom callback
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read the vbios directly from the rom.  In some cases,
-e.g., virtualization, the rom is not available via
-the BAR or other means.  Access it directly.
-
-This is an updated version of Monks original patch which
-uses family specific callbacks and unifies some of the
-validation checking.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 58 +++++++++++++++++++++++++++-----
- 1 file changed, 50 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-index c44c0c6..80add22 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-@@ -35,6 +35,13 @@
-  * BIOS.
-  */
- 
-+#define AMD_VBIOS_SIGNATURE " 761295520"
-+#define AMD_VBIOS_SIGNATURE_OFFSET 0x30
-+#define AMD_VBIOS_SIGNATURE_SIZE sizeof(AMD_VBIOS_SIGNATURE)
-+#define AMD_VBIOS_SIGNATURE_END (AMD_VBIOS_SIGNATURE_OFFSET + AMD_VBIOS_SIGNATURE_SIZE)
-+#define AMD_IS_VALID_VBIOS(p) ((p)[0] == 0x55 && (p)[1] == 0xAA)
-+#define AMD_VBIOS_LENGTH(p) ((p)[2] << 9)
-+
- /* If you boot an IGP board with a discrete card as the primary,
-  * the IGP rom is not accessible via the rom bar as the IGP rom is
-  * part of the system bios.  On boot, the system bios puts a
-@@ -58,7 +65,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
- 		return false;
- 	}
- 
--	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
-+	if (size == 0 || !AMD_IS_VALID_VBIOS(bios)) {
- 		iounmap(bios);
- 		return false;
- 	}
-@@ -74,7 +81,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
- 
- bool amdgpu_read_bios(struct amdgpu_device *adev)
- {
--	uint8_t __iomem *bios, val1, val2;
-+	uint8_t __iomem *bios, val[2];
- 	size_t size;
- 
- 	adev->bios = NULL;
-@@ -84,10 +91,10 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
- 		return false;
- 	}
- 
--	val1 = readb(&bios[0]);
--	val2 = readb(&bios[1]);
-+	val[0] = readb(&bios[0]);
-+	val[1] = readb(&bios[1]);
- 
--	if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
-+	if (size == 0 || !AMD_IS_VALID_VBIOS(val)) {
- 		pci_unmap_rom(adev->pdev, bios);
- 		return false;
- 	}
-@@ -101,6 +108,38 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
- 	return true;
- }
- 
-+static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
-+{
-+	u8 header[AMD_VBIOS_SIGNATURE_END+1] = {0};
-+	int len;
-+
-+	if (!adev->asic_funcs->read_bios_from_rom)
-+		return false;
-+
-+	/* validate VBIOS signature */
-+	if (amdgpu_asic_read_bios_from_rom(adev, &header[0], sizeof(header)) == false)
-+		return false;
-+	header[AMD_VBIOS_SIGNATURE_END] = 0;
-+
-+	if ((!AMD_IS_VALID_VBIOS(header)) ||
-+	    0 != memcmp((char *)&header[AMD_VBIOS_SIGNATURE_OFFSET],
-+			AMD_VBIOS_SIGNATURE,
-+			strlen(AMD_VBIOS_SIGNATURE)))
-+		return false;
-+
-+	/* valid vbios, go on */
-+	len = AMD_VBIOS_LENGTH(header);
-+	len = ALIGN(len, 4);
-+	adev->bios = kmalloc(len, GFP_KERNEL);
-+	if (!adev->bios) {
-+		DRM_ERROR("no memory to allocate for BIOS\n");
-+		return false;
-+	}
-+
-+	/* read complete BIOS */
-+	return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);
-+}
-+
- static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
- {
- 	uint8_t __iomem *bios;
-@@ -113,7 +152,7 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
- 		return false;
- 	}
- 
--	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
-+	if (size == 0 || !AMD_IS_VALID_VBIOS(bios)) {
- 		return false;
- 	}
- 	adev->bios = kmemdup(bios, size, GFP_KERNEL);
-@@ -230,7 +269,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
- 			break;
- 	}
- 
--	if (i == 0 || adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) {
-+	if (i == 0 || !AMD_IS_VALID_VBIOS(adev->bios)) {
- 		kfree(adev->bios);
- 		return false;
- 	}
-@@ -320,6 +359,9 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
- 	if (r == false)
- 		r = amdgpu_read_bios(adev);
- 	if (r == false) {
-+		r = amdgpu_read_bios_from_rom(adev);
-+	}
-+	if (r == false) {
- 		r = amdgpu_read_disabled_bios(adev);
- 	}
- 	if (r == false) {
-@@ -330,7 +372,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
- 		adev->bios = NULL;
- 		return false;
- 	}
--	if (adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) {
-+	if (!AMD_IS_VALID_VBIOS(adev->bios)) {
- 		printk("BIOS signature incorrect %x %x\n", adev->bios[0], adev->bios[1]);
- 		goto free_bios;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch b/common/recipes-kernel/linux/files/0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch
deleted file mode 100644
index b576ea36..00000000
--- a/common/recipes-kernel/linux/files/0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From e898d15a84f811ba9b0947af65fb57696c100fbc Mon Sep 17 00:00:00 2001
-From: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date: Mon, 23 Nov 2015 10:32:37 +0100
-Subject: [PATCH 0008/1110] drm/amdgpu: Use unlocked gem unreferencing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-For drm_gem_object_unreference callers are required to hold
-dev->struct_mutex, which these paths don't. Enforcing this requirement
-has become a bit more strict with
-
-commit ef4c6270bf2867e2f8032e9614d1a8cfc6c71663
-Author: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date:   Thu Oct 15 09:36:25 2015 +0200
-
-    drm/gem: Check locking in drm_gem_object_unreference
-
-Cc: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-index 6fcbbcc..cfb6caa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-@@ -263,7 +263,7 @@ out_unref:
- 
- 	}
- 	if (fb && ret) {
--		drm_gem_object_unreference(gobj);
-+		drm_gem_object_unreference_unlocked(gobj);
- 		drm_framebuffer_unregister_private(fb);
- 		drm_framebuffer_cleanup(fb);
- 		kfree(fb);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0009-drm-amdgpu-add-err-check-for-pin-userptr.patch b/common/recipes-kernel/linux/files/0009-drm-amdgpu-add-err-check-for-pin-userptr.patch
deleted file mode 100644
index f7f77fc5..00000000
--- a/common/recipes-kernel/linux/files/0009-drm-amdgpu-add-err-check-for-pin-userptr.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From de1d487e1722791013ba3b384fc679a16d6070c5 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 26 Nov 2015 16:33:58 +0800
-Subject: [PATCH 0009/1110] drm/amdgpu: add err check for pin userptr
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Missing error check if the operation failed.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 1cbb16e..e8fe0b7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -587,13 +587,13 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
- 	uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
- 	int r;
- 
--	if (gtt->userptr) {
--		r = amdgpu_ttm_tt_pin_userptr(ttm);
--		if (r) {
--			DRM_ERROR("failed to pin userptr\n");
--			return r;
--		}
--	}
-+        if (gtt->userptr) {
-+                r = amdgpu_ttm_tt_pin_userptr(ttm);
-+                if (r) {
-+                        DRM_ERROR("failed to pin userptr\n");
-+                        return r;
-+                }
-+        }
- 	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
- 	if (!ttm->num_pages) {
- 		WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch b/common/recipes-kernel/linux/files/0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch
deleted file mode 100644
index 08e1c034..00000000
--- a/common/recipes-kernel/linux/files/0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From c8fb90402ca0bec0886137b3bbd0d4b646d9f00b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 17:42:02 -0500
-Subject: [PATCH 0010/1110] drm/amd: add new gfx8 register definitions for EDC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-EDC is a RAS feature for on chip memory.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-index daf763b..a9b6923 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-@@ -2807,5 +2807,18 @@
- #define ixDIDT_DBR_WEIGHT0_3                                                    0x90
- #define ixDIDT_DBR_WEIGHT4_7                                                    0x91
- #define ixDIDT_DBR_WEIGHT8_11                                                   0x92
-+#define mmTD_EDC_CNT                                                            0x252e
-+#define mmCPF_EDC_TAG_CNT                                                       0x3188
-+#define mmCPF_EDC_ROQ_CNT                                                       0x3189
-+#define mmCPF_EDC_ATC_CNT                                                       0x318a
-+#define mmCPG_EDC_TAG_CNT                                                       0x318b
-+#define mmCPG_EDC_ATC_CNT                                                       0x318c
-+#define mmCPG_EDC_DMA_CNT                                                       0x318d
-+#define mmCPC_EDC_SCRATCH_CNT                                                   0x318e
-+#define mmCPC_EDC_UCODE_CNT                                                     0x318f
-+#define mmCPC_EDC_ATC_CNT                                                       0x3190
-+#define mmDC_EDC_STATE_CNT                                                      0x3191
-+#define mmDC_EDC_CSINVOC_CNT                                                    0x3192
-+#define mmDC_EDC_RESTORE_CNT                                                    0x3193
- 
- #endif /* GFX_8_0_D_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch b/common/recipes-kernel/linux/files/0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch
deleted file mode 100644
index 1f5b247a..00000000
--- a/common/recipes-kernel/linux/files/0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch
+++ /dev/null
@@ -1,384 +0,0 @@
-From 2096458a304a38ca3f983174fba7a82946c0e5dd Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 17:43:42 -0500
-Subject: [PATCH 0011/1110] drm/amdgpu: add EDC support for CZ (v3)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This adds EDC support for CZ.
-EDC = Error Correction and Detection
-This code properly initializes the EDC hardware and
-resets the error counts.  This is done in late_init
-since it requires the IB pool which is not initialized
-during hw_init.
-
-v2: fix the IB size as noted by Felix, fix shader pgm
-register programming
-v3: use the IB for the shaders as suggested by Christian
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 331 +++++++++++++++++++++++++++++++++-
- 1 file changed, 330 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d105403..bc72883 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -964,6 +964,322 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
- 	return 0;
- }
- 
-+static const u32 vgpr_init_compute_shader[] =
-+{
-+	0x7e000209, 0x7e020208,
-+	0x7e040207, 0x7e060206,
-+	0x7e080205, 0x7e0a0204,
-+	0x7e0c0203, 0x7e0e0202,
-+	0x7e100201, 0x7e120200,
-+	0x7e140209, 0x7e160208,
-+	0x7e180207, 0x7e1a0206,
-+	0x7e1c0205, 0x7e1e0204,
-+	0x7e200203, 0x7e220202,
-+	0x7e240201, 0x7e260200,
-+	0x7e280209, 0x7e2a0208,
-+	0x7e2c0207, 0x7e2e0206,
-+	0x7e300205, 0x7e320204,
-+	0x7e340203, 0x7e360202,
-+	0x7e380201, 0x7e3a0200,
-+	0x7e3c0209, 0x7e3e0208,
-+	0x7e400207, 0x7e420206,
-+	0x7e440205, 0x7e460204,
-+	0x7e480203, 0x7e4a0202,
-+	0x7e4c0201, 0x7e4e0200,
-+	0x7e500209, 0x7e520208,
-+	0x7e540207, 0x7e560206,
-+	0x7e580205, 0x7e5a0204,
-+	0x7e5c0203, 0x7e5e0202,
-+	0x7e600201, 0x7e620200,
-+	0x7e640209, 0x7e660208,
-+	0x7e680207, 0x7e6a0206,
-+	0x7e6c0205, 0x7e6e0204,
-+	0x7e700203, 0x7e720202,
-+	0x7e740201, 0x7e760200,
-+	0x7e780209, 0x7e7a0208,
-+	0x7e7c0207, 0x7e7e0206,
-+	0xbf8a0000, 0xbf810000,
-+};
-+
-+static const u32 sgpr_init_compute_shader[] =
-+{
-+	0xbe8a0100, 0xbe8c0102,
-+	0xbe8e0104, 0xbe900106,
-+	0xbe920108, 0xbe940100,
-+	0xbe960102, 0xbe980104,
-+	0xbe9a0106, 0xbe9c0108,
-+	0xbe9e0100, 0xbea00102,
-+	0xbea20104, 0xbea40106,
-+	0xbea60108, 0xbea80100,
-+	0xbeaa0102, 0xbeac0104,
-+	0xbeae0106, 0xbeb00108,
-+	0xbeb20100, 0xbeb40102,
-+	0xbeb60104, 0xbeb80106,
-+	0xbeba0108, 0xbebc0100,
-+	0xbebe0102, 0xbec00104,
-+	0xbec20106, 0xbec40108,
-+	0xbec60100, 0xbec80102,
-+	0xbee60004, 0xbee70005,
-+	0xbeea0006, 0xbeeb0007,
-+	0xbee80008, 0xbee90009,
-+	0xbefc0000, 0xbf8a0000,
-+	0xbf810000, 0x00000000,
-+};
-+
-+static const u32 vgpr_init_regs[] =
-+{
-+	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
-+	mmCOMPUTE_RESOURCE_LIMITS, 0,
-+	mmCOMPUTE_NUM_THREAD_X, 256*4,
-+	mmCOMPUTE_NUM_THREAD_Y, 1,
-+	mmCOMPUTE_NUM_THREAD_Z, 1,
-+	mmCOMPUTE_PGM_RSRC2, 20,
-+	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
-+	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
-+	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
-+	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
-+	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
-+	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
-+	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
-+	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
-+	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
-+	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
-+};
-+
-+static const u32 sgpr1_init_regs[] =
-+{
-+	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
-+	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
-+	mmCOMPUTE_NUM_THREAD_X, 256*5,
-+	mmCOMPUTE_NUM_THREAD_Y, 1,
-+	mmCOMPUTE_NUM_THREAD_Z, 1,
-+	mmCOMPUTE_PGM_RSRC2, 20,
-+	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
-+	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
-+	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
-+	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
-+	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
-+	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
-+	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
-+	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
-+	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
-+	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
-+};
-+
-+static const u32 sgpr2_init_regs[] =
-+{
-+	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
-+	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
-+	mmCOMPUTE_NUM_THREAD_X, 256*5,
-+	mmCOMPUTE_NUM_THREAD_Y, 1,
-+	mmCOMPUTE_NUM_THREAD_Z, 1,
-+	mmCOMPUTE_PGM_RSRC2, 20,
-+	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
-+	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
-+	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
-+	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
-+	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
-+	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
-+	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
-+	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
-+	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
-+	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
-+};
-+
-+static const u32 sec_ded_counter_registers[] =
-+{
-+	mmCPC_EDC_ATC_CNT,
-+	mmCPC_EDC_SCRATCH_CNT,
-+	mmCPC_EDC_UCODE_CNT,
-+	mmCPF_EDC_ATC_CNT,
-+	mmCPF_EDC_ROQ_CNT,
-+	mmCPF_EDC_TAG_CNT,
-+	mmCPG_EDC_ATC_CNT,
-+	mmCPG_EDC_DMA_CNT,
-+	mmCPG_EDC_TAG_CNT,
-+	mmDC_EDC_CSINVOC_CNT,
-+	mmDC_EDC_RESTORE_CNT,
-+	mmDC_EDC_STATE_CNT,
-+	mmGDS_EDC_CNT,
-+	mmGDS_EDC_GRBM_CNT,
-+	mmGDS_EDC_OA_DED,
-+	mmSPI_EDC_CNT,
-+	mmSQC_ATC_EDC_GATCL1_CNT,
-+	mmSQC_EDC_CNT,
-+	mmSQ_EDC_DED_CNT,
-+	mmSQ_EDC_INFO,
-+	mmSQ_EDC_SEC_CNT,
-+	mmTCC_EDC_CNT,
-+	mmTCP_ATC_EDC_GATCL1_CNT,
-+	mmTCP_EDC_CNT,
-+	mmTD_EDC_CNT
-+};
-+
-+static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
-+{
-+	struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
-+	struct amdgpu_ib ib;
-+	struct fence *f = NULL;
-+	int r, i;
-+	u32 tmp;
-+	unsigned total_size, vgpr_offset, sgpr_offset;
-+	u64 gpu_addr;
-+
-+	/* only supported on CZ */
-+	if (adev->asic_type != CHIP_CARRIZO)
-+		return 0;
-+
-+	/* bail if the compute ring is not ready */
-+	if (!ring->ready)
-+		return 0;
-+
-+	tmp = RREG32(mmGB_EDC_MODE);
-+	WREG32(mmGB_EDC_MODE, 0);
-+
-+	total_size =
-+		(((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
-+	total_size +=
-+		(((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
-+	total_size +=
-+		(((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
-+	total_size = ALIGN(total_size, 256);
-+	vgpr_offset = total_size;
-+	total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
-+	sgpr_offset = total_size;
-+	total_size += sizeof(sgpr_init_compute_shader);
-+
-+	/* allocate an indirect buffer to put the commands in */
-+	memset(&ib, 0, sizeof(ib));
-+	r = amdgpu_ib_get(ring, NULL, total_size, &ib);
-+	if (r) {
-+		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
-+		return r;
-+	}
-+
-+	/* load the compute shaders */
-+	for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
-+		ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
-+
-+	for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
-+		ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
-+
-+	/* init the ib length to 0 */
-+	ib.length_dw = 0;
-+
-+	/* VGPR */
-+	/* write the register state for the compute dispatch */
-+	for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
-+		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
-+		ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
-+		ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
-+	}
-+	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
-+	gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
-+	ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
-+	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
-+	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
-+
-+	/* write dispatch packet */
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-+	ib.ptr[ib.length_dw++] = 8; /* x */
-+	ib.ptr[ib.length_dw++] = 1; /* y */
-+	ib.ptr[ib.length_dw++] = 1; /* z */
-+	ib.ptr[ib.length_dw++] =
-+		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
-+
-+	/* write CS partial flush packet */
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
-+	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
-+
-+	/* SGPR1 */
-+	/* write the register state for the compute dispatch */
-+	for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
-+		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
-+		ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
-+		ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
-+	}
-+	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
-+	gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
-+	ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
-+	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
-+	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
-+
-+	/* write dispatch packet */
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-+	ib.ptr[ib.length_dw++] = 8; /* x */
-+	ib.ptr[ib.length_dw++] = 1; /* y */
-+	ib.ptr[ib.length_dw++] = 1; /* z */
-+	ib.ptr[ib.length_dw++] =
-+		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
-+
-+	/* write CS partial flush packet */
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
-+	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
-+
-+	/* SGPR2 */
-+	/* write the register state for the compute dispatch */
-+	for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
-+		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
-+		ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
-+		ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
-+	}
-+	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
-+	gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
-+	ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
-+	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
-+	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
-+
-+	/* write dispatch packet */
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-+	ib.ptr[ib.length_dw++] = 8; /* x */
-+	ib.ptr[ib.length_dw++] = 1; /* y */
-+	ib.ptr[ib.length_dw++] = 1; /* z */
-+	ib.ptr[ib.length_dw++] =
-+		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
-+
-+	/* write CS partial flush packet */
-+	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
-+	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
-+
-+	/* shedule the ib on the ring */
-+	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
-+						 AMDGPU_FENCE_OWNER_UNDEFINED,
-+						 &f);
-+	if (r) {
-+		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
-+		goto fail;
-+	}
-+
-+	/* wait for the GPU to finish processing the IB */
-+	r = fence_wait(f, false);
-+	if (r) {
-+		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
-+		goto fail;
-+	}
-+
-+	tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
-+	tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
-+	WREG32(mmGB_EDC_MODE, tmp);
-+
-+	tmp = RREG32(mmCC_GC_EDC_CONFIG);
-+	tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
-+	WREG32(mmCC_GC_EDC_CONFIG, tmp);
-+
-+
-+	/* read back registers to clear the counters */
-+	for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
-+		RREG32(sec_ded_counter_registers[i]);
-+
-+fail:
-+	fence_put(f);
-+	amdgpu_ib_free(adev, &ib);
-+
-+	return r;
-+}
-+
- static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- {
- 	u32 gb_addr_config;
-@@ -4458,6 +4774,19 @@ static int gfx_v8_0_early_init(void *handle)
- 	return 0;
- }
- 
-+static int gfx_v8_0_late_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int r;
-+
-+	/* requires IBs so do in late init after IB pool is initialized */
-+	r = gfx_v8_0_do_edc_gpr_workarounds(adev);
-+	if (r)
-+		return r;
-+
-+	return 0;
-+}
-+
- static int gfx_v8_0_set_powergating_state(void *handle,
- 					  enum amd_powergating_state state)
- {
-@@ -4996,7 +5325,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
- 
- const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
- 	.early_init = gfx_v8_0_early_init,
--	.late_init = NULL,
-+	.late_init = gfx_v8_0_late_init,
- 	.sw_init = gfx_v8_0_sw_init,
- 	.sw_fini = gfx_v8_0_sw_fini,
- 	.hw_init = gfx_v8_0_hw_init,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch b/common/recipes-kernel/linux/files/0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch
deleted file mode 100644
index 2366e803..00000000
--- a/common/recipes-kernel/linux/files/0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From b0d5d1dd7c190c9a20369c4ef0880a1ffdfa95f9 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 5 Nov 2015 15:23:09 +0800
-Subject: [PATCH 0012/1110] drm/amd: abstract kernel rq and normal rq to
- priority of run queue
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Allows us to set priorities in the scheduler.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c       | 11 +++++------
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  2 +-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 14 +++++++++-----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  9 +++++++--
- 5 files changed, 23 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index d313225..e85ed1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1045,7 +1045,7 @@ struct amdgpu_ctx_mgr {
- 	struct idr		ctx_handles;
- };
- 
--int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
-+int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 		    struct amdgpu_ctx *ctx);
- void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index fec65f0..c1f2308 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -25,7 +25,7 @@
- #include <drm/drmP.h>
- #include "amdgpu.h"
- 
--int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
-+int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 		    struct amdgpu_ctx *ctx)
- {
- 	unsigned i, j;
-@@ -42,10 +42,9 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
- 		/* create context entity for each ring */
- 		for (i = 0; i < adev->num_rings; i++) {
- 			struct amd_sched_rq *rq;
--			if (kernel)
--				rq = &adev->rings[i]->sched.kernel_rq;
--			else
--				rq = &adev->rings[i]->sched.sched_rq;
-+			if (pri >= AMD_SCHED_MAX_PRIORITY)
-+				return -EINVAL;
-+			rq = &adev->rings[i]->sched.sched_rq[pri];
- 			r = amd_sched_entity_init(&adev->rings[i]->sched,
- 						  &ctx->rings[i].entity,
- 						  rq, amdgpu_sched_jobs);
-@@ -103,7 +102,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
- 		return r;
- 	}
- 	*id = (uint32_t)r;
--	r = amdgpu_ctx_init(adev, false, ctx);
-+	r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_NORMAL, ctx);
- 	mutex_unlock(&mgr->lock);
- 
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index c961fe0..c5206fd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1528,7 +1528,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 		return r;
- 	}
- 
--	r = amdgpu_ctx_init(adev, true, &adev->kernel_ctx);
-+	r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_KERNEL, &adev->kernel_ctx);
- 	if (r) {
- 		dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
- 		return r;
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 3a4820e..5ace1a7 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -349,14 +349,17 @@ static struct amd_sched_entity *
- amd_sched_select_entity(struct amd_gpu_scheduler *sched)
- {
- 	struct amd_sched_entity *entity;
-+	int i;
- 
- 	if (!amd_sched_ready(sched))
- 		return NULL;
- 
- 	/* Kernel run queue has higher priority than normal run queue*/
--	entity = amd_sched_rq_select_entity(&sched->kernel_rq);
--	if (entity == NULL)
--		entity = amd_sched_rq_select_entity(&sched->sched_rq);
-+	for (i = 0; i < AMD_SCHED_MAX_PRIORITY; i++) {
-+		entity = amd_sched_rq_select_entity(&sched->sched_rq[i]);
-+		if (entity)
-+			break;
-+	}
- 
- 	return entity;
- }
-@@ -478,12 +481,13 @@ int amd_sched_init(struct amd_gpu_scheduler *sched,
- 		   struct amd_sched_backend_ops *ops,
- 		   unsigned hw_submission, long timeout, const char *name)
- {
-+	int i;
- 	sched->ops = ops;
- 	sched->hw_submission_limit = hw_submission;
- 	sched->name = name;
- 	sched->timeout = timeout;
--	amd_sched_rq_init(&sched->sched_rq);
--	amd_sched_rq_init(&sched->kernel_rq);
-+	for (i = 0; i < AMD_SCHED_MAX_PRIORITY; i++)
-+		amd_sched_rq_init(&sched->sched_rq[i]);
- 
- 	init_waitqueue_head(&sched->wake_up_worker);
- 	init_waitqueue_head(&sched->job_scheduled);
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index a0f0ae5..9403145 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -104,6 +104,12 @@ struct amd_sched_backend_ops {
- 	struct fence *(*run_job)(struct amd_sched_job *sched_job);
- };
- 
-+enum amd_sched_priority {
-+	AMD_SCHED_PRIORITY_KERNEL = 0,
-+	AMD_SCHED_PRIORITY_NORMAL,
-+	AMD_SCHED_MAX_PRIORITY
-+};
-+
- /**
-  * One scheduler is implemented for each hardware ring
- */
-@@ -112,8 +118,7 @@ struct amd_gpu_scheduler {
- 	uint32_t			hw_submission_limit;
- 	long				timeout;
- 	const char			*name;
--	struct amd_sched_rq		sched_rq;
--	struct amd_sched_rq		kernel_rq;
-+	struct amd_sched_rq		sched_rq[AMD_SCHED_MAX_PRIORITY];
- 	wait_queue_head_t		wake_up_worker;
- 	wait_queue_head_t		job_scheduled;
- 	atomic_t			hw_rq_count;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch b/common/recipes-kernel/linux/files/0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch
deleted file mode 100644
index 5ecc4989..00000000
--- a/common/recipes-kernel/linux/files/0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 4a99da7413e28c0a9ffe7e258981e57ba0b6dfeb Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 30 Nov 2015 14:13:11 -0500
-Subject: [PATCH 0013/1110] amdgpu/gfxv8: Add missing break to switch statement
- from states init code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index bc72883..2dd0583 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1923,6 +1923,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
- 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
- 		}
-+		break;
- 	case CHIP_FIJI:
- 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- 			switch (reg_offset) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch b/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
deleted file mode 100644
index 84fa3f14..00000000
--- a/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
+++ /dev/null
@@ -1,2338 +0,0 @@
-From a420ce17e2154d83fa3c3f6c8ad91393cc49cdd6 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 1 Dec 2015 11:47:21 -0500
-Subject: [PATCH 0014/1110] amdgpu/gfxv8: Cleanup of
- gfx_v8_0_tiling_mode_table_init() (v2)
-
-Simplification and LOC reduction of function gfx_v8_0_tiling_mode_table_init()
-
-v2: remove spurious break
-bug: https://bugs.freedesktop.org/show_bug.cgi?id=93236
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2286 +++++++++++++--------------------
- 1 file changed, 898 insertions(+), 1388 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 2dd0583..f85de15 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1639,1407 +1639,917 @@ static int gfx_v8_0_sw_fini(void *handle)
- 
- static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- {
-+	uint32_t *modearray, *mod2array;
- 	const u32 num_tile_mode_states = 32;
- 	const u32 num_secondary_tile_mode_states = 16;
--	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
-+	u32 reg_offset;
- 
--	switch (adev->gfx.config.mem_row_size_in_kb) {
--	case 1:
--		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
--		break;
--	case 2:
--	default:
--		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
--		break;
--	case 4:
--		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
--		break;
--	}
-+	modearray = adev->gfx.config.tile_mode_array;
-+	mod2array = adev->gfx.config.macrotile_mode_array;
-+
-+	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+		modearray[reg_offset] = 0;
-+
-+	for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)
-+		mod2array[reg_offset] = 0;
- 
- 	switch (adev->asic_type) {
- 	case CHIP_TOPAZ:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P2));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 7:
--			case 12:
--			case 17:
--			case 23:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 7:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P2));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
-+			    reg_offset != 23)
-+				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- 		break;
- 	case CHIP_FIJI:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 7:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 12:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 17:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 23:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 30:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			case 7:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				 NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- 		break;
- 	case CHIP_TONGA:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 7:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 12:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 17:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 23:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 30:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			case 7:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				 NUM_BANKS(ADDR_SURF_4_BANK));
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				 NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- 		break;
- 	case CHIP_STONEY:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P2));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 7:
--			case 12:
--			case 17:
--			case 23:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 7:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P2));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
-+			    reg_offset != 23)
-+				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- 		break;
--	case CHIP_CARRIZO:
- 	default:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P2));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 7:
--			case 12:
--			case 17:
--			case 23:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 7:
--				/* unused idx */
--				continue;
--			default:
--				gb_tile_moden = 0;
--				break;
--			};
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		dev_warn(adev->dev,
-+			 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
-+			 adev->asic_type);
-+
-+	case CHIP_CARRIZO:
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P2));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P2) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				 PIPE_CONFIG(ADDR_SURF_P2) |
-+				 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				 NUM_BANKS(ADDR_SURF_16_BANK));
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				 NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
-+			    reg_offset != 23)
-+				WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
-+		break;
- 	}
- }
- 
-@@ -4957,7 +4467,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
- 				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
- 				 EVENT_INDEX(5)));
- 	amdgpu_ring_write(ring, addr & 0xfffffffc);
--	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 
-+	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
- 			  DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
- 	amdgpu_ring_write(ring, lower_32_bits(seq));
- 	amdgpu_ring_write(ring, upper_32_bits(seq));
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch b/common/recipes-kernel/linux/files/0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch
deleted file mode 100644
index 8efc17c3..00000000
--- a/common/recipes-kernel/linux/files/0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 1e6e1ab728900b26bec4de25fc5d851133137c0b Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 1 Dec 2015 11:48:32 -0500
-Subject: [PATCH 0015/1110] amdgpu/gfxv8: Simplification of
- gfx_v8_0_create_bitmask()
-
-Simplification of the function gfx_v8_0_create_bitmask().
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +-------
- 1 file changed, 1 insertion(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index f85de15..38f960c 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2555,13 +2555,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 
- static u32 gfx_v8_0_create_bitmask(u32 bit_width)
- {
--	u32 i, mask = 0;
--
--	for (i = 0; i < bit_width; i++) {
--		mask <<= 1;
--		mask |= 1;
--	}
--	return mask;
-+	return (u32)((1ULL << bit_width) - 1);
- }
- 
- void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch b/common/recipes-kernel/linux/files/0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch
deleted file mode 100644
index b6e77ef4..00000000
--- a/common/recipes-kernel/linux/files/0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 8b58a7e84ac160e687c8a184833c4d6210125dd2 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 1 Dec 2015 10:42:28 -0500
-Subject: [PATCH 0016/1110] amdgpu/gfxv8: Simplification in
- gfx_v8_0_enable_gui_idle_interrupt()
-
-Simplified the function by folding the two paths into one.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 16 +++++-----------
- 1 file changed, 5 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 38f960c..0446565 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2818,17 +2818,11 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
- {
- 	u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
- 
--	if (enable) {
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
--	} else {
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
--		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
--	}
-+	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
-+	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
-+	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
-+	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
-+
- 	WREG32(mmCP_INT_CNTL_RING0, tmp);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch b/common/recipes-kernel/linux/files/0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch
deleted file mode 100644
index 8b3a2684..00000000
--- a/common/recipes-kernel/linux/files/0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From a238e5cbb433f5a0df5ca1c4125f20fa61bc4914 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Dec 2015 12:23:28 -0500
-Subject: [PATCH 0017/1110] amdgpu/gfxv8: Remove magic numbers from function
- gfx_v8_0_tiling_mode_table_init()
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 0446565..15db401 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1640,8 +1640,8 @@ static int gfx_v8_0_sw_fini(void *handle)
- static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- {
- 	uint32_t *modearray, *mod2array;
--	const u32 num_tile_mode_states = 32;
--	const u32 num_secondary_tile_mode_states = 16;
-+	const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-+	const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
- 	u32 reg_offset;
- 
- 	modearray = adev->gfx.config.tile_mode_array;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch b/common/recipes-kernel/linux/files/0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch
deleted file mode 100644
index f8d04042..00000000
--- a/common/recipes-kernel/linux/files/0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 0dd3eb7611d2cb97a1ad7c02ea7d504bf0e5a086 Mon Sep 17 00:00:00 2001
-From: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date: Fri, 4 Dec 2015 09:45:43 +0100
-Subject: [PATCH 0018/1110] drm: Move LEAVE/ENTER_ATOMIC_MODESET to fbdev
- helpers
-
-This is only used for kgdb (and previously panic) handlers in
-the fbdev emulation, so belongs there.
-
-Note that this means we'll leave behind a forward declaration, but
-once all the helper vtables are consolidated (in the next patch) that
-will make more sense.
-
-v2: fixup radone/amdgpu.
-
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Link: http://patchwork.freedesktop.org/patch/msgid/1449218769-16577-3-git-send-email-daniel.vetter@ffwll.ch
-Reviewed-by: Thierry Reding <treding@nvidia.com> (v2)
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index cfb48e3..3b2d75d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -35,6 +35,7 @@
- #include <drm/drm_dp_helper.h>
- #include <drm/drm_fixed.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_fb_helper.h>
- #include <drm/drm_plane_helper.h>
- #include <linux/i2c.h>
- #include <linux/i2c-algo-bit.h>
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0019-drm-Pass-name-to-drm_encoder_init.patch b/common/recipes-kernel/linux/files/0019-drm-Pass-name-to-drm_encoder_init.patch
deleted file mode 100644
index b687b44e..00000000
--- a/common/recipes-kernel/linux/files/0019-drm-Pass-name-to-drm_encoder_init.patch
+++ /dev/null
@@ -1,202 +0,0 @@
-From 374964ea1da0a7d2a78d715cb6cf886b751ce16c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
-Date: Wed, 9 Dec 2015 16:20:18 +0200
-Subject: [PATCH 0019/1110] drm: Pass 'name' to drm_encoder_init()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Done with coccinelle for the most part. However, it thinks '...' is
-part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder
-in its place and got rid of it with sed afterwards.
-
-@@
-identifier dev, encoder, funcs;
-@@
- int drm_encoder_init(struct drm_device *dev,
-                      struct drm_encoder *encoder,
-                      const struct drm_encoder_funcs *funcs,
-                      int encoder_type
-+                     ,const char *name, int DOTDOTDOT
-                      )
-{ ... }
-
-@@
-identifier dev, encoder, funcs;
-@@
- int drm_encoder_init(struct drm_device *dev,
-                      struct drm_encoder *encoder,
-                      const struct drm_encoder_funcs *funcs,
-                      int encoder_type
-+                     ,const char *name, int DOTDOTDOT
-                      );
-
-@@
-expression E1, E2, E3, E4;
-@@
- drm_encoder_init(E1, E2, E3, E4
-+                 ,NULL
-                  )
-
-v2: Add ', or NULL...' to @name kernel doc (Jani)
-    Annotate the function with __printf() attribute (Jani)
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Link: http://patchwork.freedesktop.org/patch/msgid/1449670818-2966-1-git-send-email-ville.syrjala@linux.intel.com
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 14 +++++++-------
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 14 +++++++-------
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  | 14 +++++++-------
- 3 files changed, 21 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 4dcc8fb..093599a 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -3729,7 +3729,7 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- 		drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--				 DRM_MODE_ENCODER_DAC);
-+				 DRM_MODE_ENCODER_DAC, NULL);
- 		drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3740,15 +3740,15 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- 			amdgpu_encoder->rmx_type = RMX_FULL;
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS);
-+					 DRM_MODE_ENCODER_LVDS, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC);
-+					 DRM_MODE_ENCODER_DAC, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		} else {
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS);
-+					 DRM_MODE_ENCODER_TMDS, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		}
- 		drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
-@@ -3766,13 +3766,13 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- 		amdgpu_encoder->is_ext_encoder = true;
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS);
-+					 DRM_MODE_ENCODER_LVDS, NULL);
- 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC);
-+					 DRM_MODE_ENCODER_DAC, NULL);
- 		else
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS);
-+					 DRM_MODE_ENCODER_TMDS, NULL);
- 		drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 8f1e511..8701661 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -3722,7 +3722,7 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- 		drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--				 DRM_MODE_ENCODER_DAC);
-+				 DRM_MODE_ENCODER_DAC, NULL);
- 		drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3733,15 +3733,15 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- 			amdgpu_encoder->rmx_type = RMX_FULL;
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS);
-+					 DRM_MODE_ENCODER_LVDS, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC);
-+					 DRM_MODE_ENCODER_DAC, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		} else {
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS);
-+					 DRM_MODE_ENCODER_TMDS, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		}
- 		drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
-@@ -3759,13 +3759,13 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- 		amdgpu_encoder->is_ext_encoder = true;
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS);
-+					 DRM_MODE_ENCODER_LVDS, NULL);
- 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC);
-+					 DRM_MODE_ENCODER_DAC, NULL);
- 		else
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS);
-+					 DRM_MODE_ENCODER_TMDS, NULL);
- 		drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 42d954d..d0e128c 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -3659,7 +3659,7 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- 		drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--				 DRM_MODE_ENCODER_DAC);
-+				 DRM_MODE_ENCODER_DAC, NULL);
- 		drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3670,15 +3670,15 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- 			amdgpu_encoder->rmx_type = RMX_FULL;
- 			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS);
-+					 DRM_MODE_ENCODER_LVDS, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- 			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC);
-+					 DRM_MODE_ENCODER_DAC, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		} else {
- 			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS);
-+					 DRM_MODE_ENCODER_TMDS, NULL);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		}
- 		drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
-@@ -3696,13 +3696,13 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- 		amdgpu_encoder->is_ext_encoder = true;
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS);
-+					 DRM_MODE_ENCODER_LVDS, NULL);
- 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC);
-+					 DRM_MODE_ENCODER_DAC, NULL);
- 		else
- 			drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS);
-+					 DRM_MODE_ENCODER_TMDS, NULL);
- 		drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
- 		break;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch b/common/recipes-kernel/linux/files/0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch
deleted file mode 100644
index 18eb9f33..00000000
--- a/common/recipes-kernel/linux/files/0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 1d6c3c343ad0b1162aae90758b2de30d8aab64a1 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Wed, 2 Dec 2015 09:56:06 +0800
-Subject: [PATCH 0020/1110] drm/amdgpu/gfx8: Enable interrupt on ME1_PIPE3
-
-Otherwise FW cannot see the RLC ACK for the memory clean request
-It's for Stoney.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 15db401..5a6bb34 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3756,6 +3756,11 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- 		tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
- 		WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
- 		mqd->cp_hqd_persistent_state = tmp;
-+		if (adev->asic_type == CHIP_STONEY) {
-+			tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
-+			tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
-+			WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
-+		}
- 
- 		/* activate the queue */
- 		mqd->cp_hqd_active = 1;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch b/common/recipes-kernel/linux/files/0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch
deleted file mode 100644
index eff58cd1..00000000
--- a/common/recipes-kernel/linux/files/0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f933ed7d6bfd0ba56541536b54648e8ed80f959f Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Tue, 8 Dec 2015 11:23:29 +0800
-Subject: [PATCH 0021/1110] drm/amdgpu/gfx8: update PA_SC_RASTER_CONFIG:PKR_MAP
- only
-
-Use default value as a base.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 5a6bb34..16420b9 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2630,7 +2630,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
- 	mutex_lock(&adev->grbm_idx_mutex);
- 	for (i = 0; i < se_num; i++) {
- 		gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
--		data = 0;
-+		data = RREG32(mmPA_SC_RASTER_CONFIG);
- 		for (j = 0; j < sh_per_se; j++) {
- 			switch (enabled_rbs & 3) {
- 			case 0:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0022-drm-amdgpu-update-rev-id-register-for-VI.patch b/common/recipes-kernel/linux/files/0022-drm-amdgpu-update-rev-id-register-for-VI.patch
deleted file mode 100644
index 8056f349..00000000
--- a/common/recipes-kernel/linux/files/0022-drm-amdgpu-update-rev-id-register-for-VI.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 05158425917db24bd4310339d1433895135c5ae8 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Fri, 20 Nov 2015 11:40:53 +0800
-Subject: [PATCH 0022/1110] drm/amdgpu: update rev id register for VI
-
-Change-Id: I2ae9bb4a929f7c0c8783e0be563ae04be77596e2
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 0cb6f31..2f1c118 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1387,15 +1387,12 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 
- static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
- {
--	if (adev->asic_type == CHIP_TOPAZ)
--		return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
--			>> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
--	else if (adev->flags & AMD_IS_APU)
-+	if (adev->flags & AMD_IS_APU)
- 		return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
- 			>> ATI_REV_ID_FUSE_MACRO__SHIFT;
- 	else
--		return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
--			>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
-+		return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
-+			>> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
- }
- 
- static const struct amdgpu_asic_funcs vi_asic_funcs =
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch b/common/recipes-kernel/linux/files/0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch
deleted file mode 100644
index 50c39836..00000000
--- a/common/recipes-kernel/linux/files/0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch
+++ /dev/null
@@ -1,211 +0,0 @@
-From 0273b5fac28b3b13111b978c7c27c908ba9d28c2 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 7 Dec 2015 17:02:53 -0500
-Subject: [PATCH 0023/1110] drm/amdgpu: add more debugging output for driver
- failures
-
-Add more fine grained debugging output for init/fini/suspend/
-resume failures.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +++++++++++++++++++++++-------
- 1 file changed, 57 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index c5206fd..991884a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1214,12 +1214,14 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
- 		} else {
- 			if (adev->ip_blocks[i].funcs->early_init) {
- 				r = adev->ip_blocks[i].funcs->early_init((void *)adev);
--				if (r == -ENOENT)
-+				if (r == -ENOENT) {
- 					adev->ip_block_status[i].valid = false;
--				else if (r)
-+				} else if (r) {
-+					DRM_ERROR("early_init %d failed %d\n", i, r);
- 					return r;
--				else
-+				} else {
- 					adev->ip_block_status[i].valid = true;
-+				}
- 			} else {
- 				adev->ip_block_status[i].valid = true;
- 			}
-@@ -1237,20 +1239,28 @@ static int amdgpu_init(struct amdgpu_device *adev)
- 		if (!adev->ip_block_status[i].valid)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
--		if (r)
-+		if (r) {
-+			DRM_ERROR("sw_init %d failed %d\n", i, r);
- 			return r;
-+		}
- 		adev->ip_block_status[i].sw = true;
- 		/* need to do gmc hw init early so we can allocate gpu mem */
- 		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
- 			r = amdgpu_vram_scratch_init(adev);
--			if (r)
-+			if (r) {
-+				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
- 				return r;
-+			}
- 			r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
--			if (r)
-+			if (r) {
-+				DRM_ERROR("hw_init %d failed %d\n", i, r);
- 				return r;
-+			}
- 			r = amdgpu_wb_init(adev);
--			if (r)
-+			if (r) {
-+				DRM_ERROR("amdgpu_wb_init failed %d\n", r);
- 				return r;
-+			}
- 			adev->ip_block_status[i].hw = true;
- 		}
- 	}
-@@ -1262,8 +1272,10 @@ static int amdgpu_init(struct amdgpu_device *adev)
- 		if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
--		if (r)
-+		if (r) {
-+			DRM_ERROR("hw_init %d failed %d\n", i, r);
- 			return r;
-+		}
- 		adev->ip_block_status[i].hw = true;
- 	}
- 
-@@ -1280,12 +1292,16 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
- 		/* enable clockgating to save power */
- 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- 								    AMD_CG_STATE_GATE);
--		if (r)
-+		if (r) {
-+			DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
- 			return r;
-+		}
- 		if (adev->ip_blocks[i].funcs->late_init) {
- 			r = adev->ip_blocks[i].funcs->late_init((void *)adev);
--			if (r)
-+			if (r) {
-+				DRM_ERROR("late_init %d failed %d\n", i, r);
- 				return r;
-+			}
- 		}
- 	}
- 
-@@ -1306,10 +1322,15 @@ static int amdgpu_fini(struct amdgpu_device *adev)
- 		/* ungate blocks before hw fini so that we can shutdown the blocks safely */
- 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- 								    AMD_CG_STATE_UNGATE);
--		if (r)
-+		if (r) {
-+			DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
- 			return r;
-+		}
- 		r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
- 		/* XXX handle errors */
-+		if (r) {
-+			DRM_DEBUG("hw_fini %d failed %d\n", i, r);
-+		}
- 		adev->ip_block_status[i].hw = false;
- 	}
- 
-@@ -1318,6 +1339,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
- 		/* XXX handle errors */
-+		if (r) {
-+			DRM_DEBUG("sw_fini %d failed %d\n", i, r);
-+		}
- 		adev->ip_block_status[i].sw = false;
- 		adev->ip_block_status[i].valid = false;
- 	}
-@@ -1335,9 +1359,15 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
- 		/* ungate blocks so that suspend can properly shut them down */
- 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- 								    AMD_CG_STATE_UNGATE);
-+		if (r) {
-+			DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
-+		}
- 		/* XXX handle errors */
- 		r = adev->ip_blocks[i].funcs->suspend(adev);
- 		/* XXX handle errors */
-+		if (r) {
-+			DRM_ERROR("suspend %d failed %d\n", i, r);
-+		}
- 	}
- 
- 	return 0;
-@@ -1351,8 +1381,10 @@ static int amdgpu_resume(struct amdgpu_device *adev)
- 		if (!adev->ip_block_status[i].valid)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->resume(adev);
--		if (r)
-+		if (r) {
-+			DRM_ERROR("resume %d failed %d\n", i, r);
- 			return r;
-+		}
- 	}
- 
- 	return 0;
-@@ -1484,8 +1516,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 		return -EINVAL;
- 	}
- 	r = amdgpu_atombios_init(adev);
--	if (r)
-+	if (r) {
-+		dev_err(adev->dev, "amdgpu_atombios_init failed\n");
- 		return r;
-+	}
- 
- 	/* Post card if necessary */
- 	if (!amdgpu_card_posted(adev)) {
-@@ -1499,21 +1533,26 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 
- 	/* Initialize clocks */
- 	r = amdgpu_atombios_get_clock_info(adev);
--	if (r)
-+	if (r) {
-+		dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
- 		return r;
-+	}
- 	/* init i2c buses */
- 	amdgpu_atombios_i2c_init(adev);
- 
- 	/* Fence driver */
- 	r = amdgpu_fence_driver_init(adev);
--	if (r)
-+	if (r) {
-+		dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
- 		return r;
-+	}
- 
- 	/* init the mode config */
- 	drm_mode_config_init(adev->ddev);
- 
- 	r = amdgpu_init(adev);
- 	if (r) {
-+		dev_err(adev->dev, "amdgpu_init failed\n");
- 		amdgpu_fini(adev);
- 		return r;
- 	}
-@@ -1570,8 +1609,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	 * explicit gating rather than handling it automatically.
- 	 */
- 	r = amdgpu_late_init(adev);
--	if (r)
-+	if (r) {
-+		dev_err(adev->dev, "amdgpu_late_init failed\n");
- 		return r;
-+	}
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0024-drm-amdgpu-add-entity-only-when-first-job-come.patch b/common/recipes-kernel/linux/files/0024-drm-amdgpu-add-entity-only-when-first-job-come.patch
deleted file mode 100644
index 659bbaf0..00000000
--- a/common/recipes-kernel/linux/files/0024-drm-amdgpu-add-entity-only-when-first-job-come.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 090a50215bda6e62ddd9514d6f1ab0ba972b87bd Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 11 Dec 2015 18:22:52 +0800
-Subject: [PATCH 0024/1110] drm/amdgpu: add entity only when first job come
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-umd somtimes will create a context for every ring,
-that means some entities wouldn't be used at all.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 5ace1a7..8b2becd 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -47,6 +47,8 @@ static void amd_sched_rq_init(struct amd_sched_rq *rq)
- static void amd_sched_rq_add_entity(struct amd_sched_rq *rq,
- 				    struct amd_sched_entity *entity)
- {
-+	if (!list_empty(&entity->list))
-+		return;
- 	spin_lock(&rq->lock);
- 	list_add_tail(&entity->list, &rq->entities);
- 	spin_unlock(&rq->lock);
-@@ -55,6 +57,8 @@ static void amd_sched_rq_add_entity(struct amd_sched_rq *rq,
- static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq,
- 				       struct amd_sched_entity *entity)
- {
-+	if (list_empty(&entity->list))
-+		return;
- 	spin_lock(&rq->lock);
- 	list_del_init(&entity->list);
- 	if (rq->current_entity == entity)
-@@ -138,9 +142,6 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
- 	atomic_set(&entity->fence_seq, 0);
- 	entity->fence_context = fence_context_alloc(1);
- 
--	/* Add the entity to the run queue */
--	amd_sched_rq_add_entity(rq, entity);
--
- 	return 0;
- }
- 
-@@ -302,9 +303,11 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
- 	spin_unlock(&entity->queue_lock);
- 
- 	/* first job wakes up scheduler */
--	if (first)
-+	if (first) {
-+		/* Add the entity to the run queue */
-+		amd_sched_rq_add_entity(entity->rq, entity);
- 		amd_sched_wakeup(sched);
--
-+	}
- 	return added;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0025-drm-amdgpu-handle-error-case-for-ctx.patch b/common/recipes-kernel/linux/files/0025-drm-amdgpu-handle-error-case-for-ctx.patch
deleted file mode 100644
index 55da8d0f..00000000
--- a/common/recipes-kernel/linux/files/0025-drm-amdgpu-handle-error-case-for-ctx.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From b94cbc431148d3dc4b5bf20303412ed3b6e60f53 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 15:50:02 +0800
-Subject: [PATCH 0025/1110] drm/amdgpu: handle error case for ctx
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Properly handle ctx init failure.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index c1f2308..15e3416 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -56,7 +56,6 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 			for (j = 0; j < i; j++)
- 				amd_sched_entity_fini(&adev->rings[j]->sched,
- 						      &ctx->rings[j].entity);
--			kfree(ctx);
- 			return r;
- 		}
- 	}
-@@ -103,8 +102,12 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
- 	}
- 	*id = (uint32_t)r;
- 	r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_NORMAL, ctx);
-+	if (r) {
-+		idr_remove(&mgr->ctx_handles, *id);
-+		*id = 0;
-+		kfree(ctx);
-+	}
- 	mutex_unlock(&mgr->lock);
--
- 	return r;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch b/common/recipes-kernel/linux/files/0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch
deleted file mode 100644
index da130896..00000000
--- a/common/recipes-kernel/linux/files/0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 12db7286ff75575c9cac9afc5309c26e8ae21527 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 15:45:11 +0800
-Subject: [PATCH 0026/1110] drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and
- amdgpu_sched_jobs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  5 ++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 25 ++++++++++++++++++-------
- 2 files changed, 20 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e85ed1b..f6563fa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1022,11 +1022,9 @@ int amdgpu_vm_free_job(struct amdgpu_job *job);
-  * context related structures
-  */
- 
--#define AMDGPU_CTX_MAX_CS_PENDING	16
--
- struct amdgpu_ctx_ring {
- 	uint64_t		sequence;
--	struct fence		*fences[AMDGPU_CTX_MAX_CS_PENDING];
-+	struct fence		**fences;
- 	struct amd_sched_entity	entity;
- };
- 
-@@ -1035,6 +1033,7 @@ struct amdgpu_ctx {
- 	struct amdgpu_device    *adev;
- 	unsigned		reset_counter;
- 	spinlock_t		ring_lock;
-+	struct fence            **fences;
- 	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];
- };
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index 15e3416..ee121ec 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -35,15 +35,24 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 	ctx->adev = adev;
- 	kref_init(&ctx->refcount);
- 	spin_lock_init(&ctx->ring_lock);
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
--		ctx->rings[i].sequence = 1;
-+	ctx->fences = kzalloc(sizeof(struct fence *) * amdgpu_sched_jobs *
-+			 AMDGPU_MAX_RINGS, GFP_KERNEL);
-+	if (!ctx->fences)
-+		return -ENOMEM;
- 
-+	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-+		ctx->rings[i].sequence = 1;
-+		ctx->rings[i].fences = (void *)ctx->fences + sizeof(struct fence *) *
-+			amdgpu_sched_jobs * i;
-+	}
- 	if (amdgpu_enable_scheduler) {
- 		/* create context entity for each ring */
- 		for (i = 0; i < adev->num_rings; i++) {
- 			struct amd_sched_rq *rq;
--			if (pri >= AMD_SCHED_MAX_PRIORITY)
-+			if (pri >= AMD_SCHED_MAX_PRIORITY) {
-+				kfree(ctx->fences);
- 				return -EINVAL;
-+			}
- 			rq = &adev->rings[i]->sched.sched_rq[pri];
- 			r = amd_sched_entity_init(&adev->rings[i]->sched,
- 						  &ctx->rings[i].entity,
-@@ -56,6 +65,7 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 			for (j = 0; j < i; j++)
- 				amd_sched_entity_fini(&adev->rings[j]->sched,
- 						      &ctx->rings[j].entity);
-+			kfree(ctx->fences);
- 			return r;
- 		}
- 	}
-@@ -71,8 +81,9 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
- 		return;
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
--		for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
-+		for (j = 0; j < amdgpu_sched_jobs; ++j)
- 			fence_put(ctx->rings[i].fences[j]);
-+	kfree(ctx->fences);
- 
- 	if (amdgpu_enable_scheduler) {
- 		for (i = 0; i < adev->num_rings; i++)
-@@ -241,7 +252,7 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
- 	unsigned idx = 0;
- 	struct fence *other = NULL;
- 
--	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
-+	idx = seq % amdgpu_sched_jobs;
- 	other = cring->fences[idx];
- 	if (other) {
- 		signed long r;
-@@ -276,12 +287,12 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
- 	}
- 
- 
--	if (seq + AMDGPU_CTX_MAX_CS_PENDING < cring->sequence) {
-+	if (seq + amdgpu_sched_jobs < cring->sequence) {
- 		spin_unlock(&ctx->ring_lock);
- 		return NULL;
- 	}
- 
--	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
-+	fence = fence_get(cring->fences[seq % amdgpu_sched_jobs]);
- 	spin_unlock(&ctx->ring_lock);
- 
- 	return fence;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0027-drm-amdgpu-change-default-sched-jobs-to-32.patch b/common/recipes-kernel/linux/files/0027-drm-amdgpu-change-default-sched-jobs-to-32.patch
deleted file mode 100644
index c1bedd3f..00000000
--- a/common/recipes-kernel/linux/files/0027-drm-amdgpu-change-default-sched-jobs-to-32.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From df7c1b76f73d1969ff8b8001e351b9b2d1454595 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 15:46:50 +0800
-Subject: [PATCH 0027/1110] drm/amdgpu: change default sched jobs to 32
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Change the default scheduler queue size from 16 to 32.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 8d6668c..659300c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -79,7 +79,7 @@ int amdgpu_vm_fault_stop = 0;
- int amdgpu_vm_debug = 0;
- int amdgpu_exp_hw_support = 0;
- int amdgpu_enable_scheduler = 1;
--int amdgpu_sched_jobs = 16;
-+int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_enable_semaphores = 0;
- 
-@@ -155,7 +155,7 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
- MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)");
- module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
- 
--MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)");
-+MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
- module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
- 
- MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch b/common/recipes-kernel/linux/files/0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch
deleted file mode 100644
index 3f09b488..00000000
--- a/common/recipes-kernel/linux/files/0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 59751bbb53fb875b45a1f6a389e70a62923a58e3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 9 Dec 2015 15:36:40 -0500
-Subject: [PATCH 0028/1110] drm/amdgpu: limit visible vram if it's smaller than
- the BAR
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In some cases the amount of vram may be less than the BAR size,
-if so, limit visible vram to the amount of actual vram, not the
-BAR size.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++++
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++++
- 2 files changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index ea87033..538af44 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -407,6 +407,10 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
- 	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 	adev->mc.visible_vram_size = adev->mc.aper_size;
- 
-+	/* In case the PCI BAR is larger than the actual amount of vram */
-+	if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
-+		adev->mc.visible_vram_size = adev->mc.real_vram_size;
-+
- 	/* unless the user had overridden it, set the gart
- 	 * size equal to the 1024 or vram, whichever is larger.
- 	 */
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 0842308..3d4a923 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -448,6 +448,10 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
- 	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 	adev->mc.visible_vram_size = adev->mc.aper_size;
- 
-+	/* In case the PCI BAR is larger than the actual amount of vram */
-+	if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
-+		adev->mc.visible_vram_size = adev->mc.real_vram_size;
-+
- 	/* unless the user had overridden it, set the gart
- 	 * size equal to the 1024 or vram, whichever is larger.
- 	 */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch b/common/recipes-kernel/linux/files/0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch
deleted file mode 100644
index 889b82a1..00000000
--- a/common/recipes-kernel/linux/files/0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 0cb97db6c8809cf2127421383a668cbf912660e3 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 17:34:33 +0800
-Subject: [PATCH 0029/1110] drm/amdgpu: restrict the sched jobs number to power
- of two
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-CC: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c    | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +++++++++
- 2 files changed, 11 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index ee121ec..17d1fb1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -252,7 +252,7 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
- 	unsigned idx = 0;
- 	struct fence *other = NULL;
- 
--	idx = seq % amdgpu_sched_jobs;
-+	idx = seq & (amdgpu_sched_jobs - 1);
- 	other = cring->fences[idx];
- 	if (other) {
- 		signed long r;
-@@ -292,7 +292,7 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
- 		return NULL;
- 	}
- 
--	fence = fence_get(cring->fences[seq % amdgpu_sched_jobs]);
-+	fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
- 	spin_unlock(&ctx->ring_lock);
- 
- 	return fence;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 991884a..a138f69 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -949,6 +949,15 @@ static bool amdgpu_check_pot_argument(int arg)
-  */
- static void amdgpu_check_arguments(struct amdgpu_device *adev)
- {
-+	if (amdgpu_sched_jobs < 4) {
-+		dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
-+			 amdgpu_sched_jobs);
-+		amdgpu_sched_jobs = 4;
-+	} else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
-+		dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
-+			 amdgpu_sched_jobs);
-+		amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
-+	}
- 	/* vramlimit must be a power of two */
- 	if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
- 		dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch b/common/recipes-kernel/linux/files/0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch
deleted file mode 100644
index 39072112..00000000
--- a/common/recipes-kernel/linux/files/0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch
+++ /dev/null
@@ -1,119 +0,0 @@
-From 78fe04e337d615028fcbee472d8a3dc30a4177ea Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Dec 2015 14:39:05 +0100
-Subject: [PATCH 0030/1110] drm/amdgpu: put VM page tables directly into
- duplicates list
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-They share the reservation object with the page directory anyway.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  4 ++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 13 ++++++++-----
- 4 files changed, 15 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index f6563fa..1447a5e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -982,6 +982,10 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- 					       struct amdgpu_vm *vm,
- 					       struct list_head *head);
-+struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
-+                                               struct amdgpu_vm *vm,
-+                                               struct list_head *validated,
-+                                               struct list_head *duplicates);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		      struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 25a3e24..1d52144 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -406,8 +406,9 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 		amdgpu_cs_buckets_get_list(&buckets, &p->validated);
- 	}
- 
-+        INIT_LIST_HEAD(&duplicates);
- 	p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
--				      &p->validated);
-+                                      &p->validated, &duplicates);
- 
- 	if (p->uf.bo)
- 		list_add(&p->uf_entry.tv.head, &p->validated);
-@@ -415,7 +416,6 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 	if (need_mmap_lock)
- 		down_read(&current->mm->mmap_sem);
- 
--	INIT_LIST_HEAD(&duplicates);
- 	r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
- 	if (unlikely(r != 0))
- 		goto error_reserve;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 9c253c5..df0444f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -461,7 +461,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 	tv.shared = true;
- 	list_add(&tv.head, &list);
- 
--	vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
-+        vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list, &duplicates);
- 	if (!vm_bos)
- 		return;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8c5ec15..3c3404f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -78,14 +78,17 @@ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
-  * amdgpu_vm_get_bos - add the vm BOs to a validation list
-  *
-  * @vm: vm providing the BOs
-- * @head: head of validation list
-+ * @validated: head of validation list
-+ * @duplicates: head of duplicates list
-+
-  *
-  * Add the page directory to the list of BOs to
-  * validate for command submission (cayman+).
-  */
- struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
--					  struct amdgpu_vm *vm,
--					  struct list_head *head)
-+                                               struct amdgpu_vm *vm,
-+                                               struct list_head *validated,
-+                                               struct list_head *duplicates)
- {
- 	struct amdgpu_bo_list_entry *list;
- 	unsigned i, idx;
-@@ -103,7 +106,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- 	list[0].priority = 0;
- 	list[0].tv.bo = &vm->page_directory->tbo;
- 	list[0].tv.shared = true;
--	list_add(&list[0].tv.head, head);
-+        list_add(&list[0].tv.head, validated);
- 
- 	for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
- 		if (!vm->page_tables[i].bo)
-@@ -115,7 +118,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- 		list[idx].priority = 0;
- 		list[idx].tv.bo = &list[idx].robj->tbo;
- 		list[idx].tv.shared = true;
--		list_add(&list[idx++].tv.head, head);
-+                list_add(&list[idx++].tv.head, duplicates);
- 	}
- 
- 	return list;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch b/common/recipes-kernel/linux/files/0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch
deleted file mode 100644
index 4f646fee..00000000
--- a/common/recipes-kernel/linux/files/0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch
+++ /dev/null
@@ -1,190 +0,0 @@
-From e80b9ea2005233764ff7bac3ed1ef49732bdaa05 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Dec 2015 15:16:32 +0100
-Subject: [PATCH 0031/1110] drm/amdgpu: split VM PD and PT handling during CS
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This way we avoid the extra allocation for the page directory entry.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  6 +++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  9 ++++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 16 +++++++++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 39 ++++++++++++++++++++++++---------
- 4 files changed, 52 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1447a5e..638b089 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -986,6 +986,11 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
-                                                struct amdgpu_vm *vm,
-                                                struct list_head *validated,
-                                                struct list_head *duplicates);
-+void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-+                         struct list_head *validated,
-+                         struct amdgpu_bo_list_entry *entry);
-+struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
-+                                                  struct list_head *duplicates);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		      struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-@@ -1255,6 +1260,7 @@ struct amdgpu_cs_parser {
- 	unsigned		nchunks;
- 	struct amdgpu_cs_chunk	*chunks;
- 	/* relocations */
-+        struct amdgpu_bo_list_entry     vm_pd;
- 	struct amdgpu_bo_list_entry	*vm_bos;
- 	struct list_head	validated;
- 	struct fence		*fence;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 1d52144..1ff138e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -407,8 +407,7 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 	}
- 
-         INIT_LIST_HEAD(&duplicates);
--	p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
--                                      &p->validated, &duplicates);
-+        amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
- 
- 	if (p->uf.bo)
- 		list_add(&p->uf_entry.tv.head, &p->validated);
-@@ -420,6 +419,12 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 	if (unlikely(r != 0))
- 		goto error_reserve;
- 
-+        p->vm_bos = amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
-+        if (!p->vm_bos) {
-+                r = -ENOMEM;
-+                goto error_validate;
-+        }
-+
- 	r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
- 	if (r)
- 		goto error_validate;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index df0444f..b1d44ce 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -449,6 +449,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- {
- 	struct ttm_validate_buffer tv, *entry;
- 	struct amdgpu_bo_list_entry *vm_bos;
-+        struct amdgpu_bo_list_entry vm_pd;
- 	struct ww_acquire_ctx ticket;
- 	struct list_head list, duplicates;
- 	unsigned domain;
-@@ -461,14 +462,18 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 	tv.shared = true;
- 	list_add(&tv.head, &list);
- 
--        vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list, &duplicates);
--	if (!vm_bos)
--		return;
-+        amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
- 
- 	/* Provide duplicates to avoid -EALREADY */
- 	r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
- 	if (r)
--		goto error_free;
-+                goto error_print;
-+ 
-+        vm_bos = amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
-+        if (!vm_bos) {
-+                r = -ENOMEM;
-+                goto error_unreserve;
-+        }
- 
- 	list_for_each_entry(entry, &list, head) {
- 		domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
-@@ -498,10 +503,9 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 
- error_unreserve:
- 	ttm_eu_backoff_reservation(&ticket, &list);
--
--error_free:
- 	drm_free_large(vm_bos);
- 
-+error_print:
- 	if (r && r != -ERESTARTSYS)
- 		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 3c3404f..396ab85 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -75,27 +75,46 @@ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
- }
- 
- /**
-- * amdgpu_vm_get_bos - add the vm BOs to a validation list
-- *
-+ * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
-  * @vm: vm providing the BOs
-  * @validated: head of validation list
-+ * @entry: entry to add
-+ *
-+ * Add the page directory to the list of BOs to
-+ * validate for command submission.
-+ */
-+void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-+                        struct list_head *validated,
-+                        struct amdgpu_bo_list_entry *entry)
-+{
-+        entry->robj = vm->page_directory;
-+        entry->prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
-+        entry->allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
-+        entry->priority = 0;
-+        entry->tv.bo = &vm->page_directory->tbo;
-+        entry->tv.shared = true;
-+        list_add(&entry->tv.head, validated);
-+}
-+
-+/**
-++ * amdgpu_vm_get_bos - add the vm BOs to a validation list
-++ *
-++ * @vm: vm providing the BOs
-  * @duplicates: head of duplicates list
- 
-- *
-  * Add the page directory to the list of BOs to
-  * validate for command submission (cayman+).
-  */
--struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
--                                               struct amdgpu_vm *vm,
--                                               struct list_head *validated,
--                                               struct list_head *duplicates)
-+struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
-+                                                  struct list_head *duplicates)
-+
- {
- 	struct amdgpu_bo_list_entry *list;
- 	unsigned i, idx;
- 
--	list = drm_malloc_ab(vm->max_pde_used + 2,
-+        list = drm_malloc_ab(vm->max_pde_used + 1,
- 			     sizeof(struct amdgpu_bo_list_entry));
--	if (!list) {
-+        if (!list)
- 		return NULL;
- 	}
- 
-@@ -108,7 +127,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- 	list[0].tv.shared = true;
-         list_add(&list[0].tv.head, validated);
- 
--	for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
-+        for (i = 0, idx = 0; i <= vm->max_pde_used; i++) {
- 		if (!vm->page_tables[i].bo)
- 			continue;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch b/common/recipes-kernel/linux/files/0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch
deleted file mode 100644
index e7f774f3..00000000
--- a/common/recipes-kernel/linux/files/0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From 7e593951bf930179ca0d28269536c58361f5fa34 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Dec 2015 21:01:23 +0100
-Subject: [PATCH 0032/1110] drm/amdgpu: keep the PTs validation list in the VM
- v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This avoids allocating it on the fly.
-
-v2: fix grammar in comment
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  9 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  7 +---
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  9 +-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 57 +++++++++++++++------------------
- 4 files changed, 31 insertions(+), 51 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 638b089..41bee9e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -916,8 +916,9 @@ struct amdgpu_ring {
- #define AMDGPU_VM_FAULT_STOP_ALWAYS	2
- 
- struct amdgpu_vm_pt {
--	struct amdgpu_bo	*bo;
--	uint64_t		addr;
-+        struct amdgpu_bo_list_entry     entry;
-+        uint64_t                        addr;
-+
- };
- 
- struct amdgpu_vm_id {
-@@ -989,8 +990,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-                          struct list_head *validated,
-                          struct amdgpu_bo_list_entry *entry);
--struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
--                                                  struct list_head *duplicates);
-+void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		      struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-@@ -1261,7 +1261,6 @@ struct amdgpu_cs_parser {
- 	struct amdgpu_cs_chunk	*chunks;
- 	/* relocations */
-         struct amdgpu_bo_list_entry     vm_pd;
--	struct amdgpu_bo_list_entry	*vm_bos;
- 	struct list_head	validated;
- 	struct fence		*fence;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 1ff138e..850f2ab 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -419,11 +419,7 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 	if (unlikely(r != 0))
- 		goto error_reserve;
- 
--        p->vm_bos = amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
--        if (!p->vm_bos) {
--                r = -ENOMEM;
--                goto error_validate;
--        }
-+        amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
- 
- 	r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
- 	if (r)
-@@ -506,7 +502,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
- 	if (parser->bo_list)
- 		amdgpu_bo_list_put(parser->bo_list);
- 
--	drm_free_large(parser->vm_bos);
- 	for (i = 0; i < parser->nchunks; i++)
- 		drm_free_large(parser->chunks[i].kdata);
- 	kfree(parser->chunks);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index b1d44ce..8eb4b68 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -448,7 +448,6 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 				    struct amdgpu_bo_va *bo_va, uint32_t operation)
- {
- 	struct ttm_validate_buffer tv, *entry;
--	struct amdgpu_bo_list_entry *vm_bos;
-         struct amdgpu_bo_list_entry vm_pd;
- 	struct ww_acquire_ctx ticket;
- 	struct list_head list, duplicates;
-@@ -469,12 +468,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 	if (r)
-                 goto error_print;
-  
--        vm_bos = amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
--        if (!vm_bos) {
--                r = -ENOMEM;
--                goto error_unreserve;
--        }
--
-+        amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
- 	list_for_each_entry(entry, &list, head) {
- 		domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
- 		/* if anything is swapped out don't swap it in here,
-@@ -503,7 +497,6 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 
- error_unreserve:
- 	ttm_eu_backoff_reservation(&ticket, &list);
--	drm_free_large(vm_bos);
- 
- error_print:
- 	if (r && r != -ERESTARTSYS)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 396ab85..e83d4f1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -97,26 +97,18 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
- }
- 
- /**
--+ * amdgpu_vm_get_bos - add the vm BOs to a validation list
--+ *
--+ * @vm: vm providing the BOs
-+ * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
-+ *
-+ * @vm: vm providing the BOs
-  * @duplicates: head of duplicates list
- 
-- * Add the page directory to the list of BOs to
-- * validate for command submission (cayman+).
-- */
--struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
--                                                  struct list_head *duplicates)
-+ * Add the page directory to the BO duplicates list
-+ * for command submission.
- 
-+ */
-+void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
- {
--	struct amdgpu_bo_list_entry *list;
--	unsigned i, idx;
--
--        list = drm_malloc_ab(vm->max_pde_used + 1,
--			     sizeof(struct amdgpu_bo_list_entry));
--        if (!list)
--		return NULL;
--	}
-+        unsigned i;
- 
- 	/* add the vm page table to the list */
- 	list[0].robj = vm->page_directory;
-@@ -127,20 +119,14 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
- 	list[0].tv.shared = true;
-         list_add(&list[0].tv.head, validated);
- 
--        for (i = 0, idx = 0; i <= vm->max_pde_used; i++) {
--		if (!vm->page_tables[i].bo)
-+        for (i = 0; i <= vm->max_pde_used; ++i) {
-+                struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-+ 
-+                if (!entry->robj)
- 			continue;
- 
--		list[idx].robj = vm->page_tables[i].bo;
--		list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
--		list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
--		list[idx].priority = 0;
--		list[idx].tv.bo = &list[idx].robj->tbo;
--		list[idx].tv.shared = true;
--                list_add(&list[idx++].tv.head, duplicates);
-+                list_add(&entry->tv.head, duplicates);
- 	}
--
--	return list;
- }
- 
- /**
-@@ -483,7 +469,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 
- 	/* walk over the address space and update the page directory */
- 	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
--		struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
-+                struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
- 		uint64_t pde, pt;
- 
- 		if (bo == NULL)
-@@ -660,7 +646,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 	/* walk over the address space and update the page tables */
- 	for (addr = start; addr < end; ) {
- 		uint64_t pt_idx = addr >> amdgpu_vm_block_size;
--		struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
-+                struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
- 		unsigned nptes;
- 		uint64_t pte;
- 		int r;
-@@ -1092,9 +1078,11 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 	/* walk over the address space and allocate the page tables */
- 	for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
- 		struct reservation_object *resv = vm->page_directory->tbo.resv;
-+                struct amdgpu_bo_list_entry *entry;
- 		struct amdgpu_bo *pt;
- 
--		if (vm->page_tables[pt_idx].bo)
-+                entry = &vm->page_tables[pt_idx].entry;
-+                if (entry->robj)
- 			continue;
- 
- 		r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
-@@ -1116,8 +1104,13 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 			goto error_free;
- 		}
- 
-+                entry->robj = pt;
-+                entry->prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
-+                entry->allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
-+                entry->priority = 0;
-+                entry->tv.bo = &entry->robj->tbo;
-+                entry->tv.shared = true;
- 		vm->page_tables[pt_idx].addr = 0;
--		vm->page_tables[pt_idx].bo = pt;
- 	}
- 
- 	return 0;
-@@ -1347,7 +1340,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	}
- 
- 	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
--		amdgpu_bo_unref(&vm->page_tables[i].bo);
-+                amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
- 	drm_free_large(vm->page_tables);
- 
- 	amdgpu_bo_unref(&vm->page_directory);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0033-drm-amdgpu-fix-dp-link-rate-selection-v2.patch b/common/recipes-kernel/linux/files/0033-drm-amdgpu-fix-dp-link-rate-selection-v2.patch
deleted file mode 100644
index 585ce1a5..00000000
--- a/common/recipes-kernel/linux/files/0033-drm-amdgpu-fix-dp-link-rate-selection-v2.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 9057e8ec3a72b7ffcd95ed553843265f4ef966d3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 17 Dec 2015 09:57:49 -0500
-Subject: [PATCH 0033/1110] drm/amdgpu: fix dp link rate selection (v2)
-
-Need to properly handle the max link rate in the dpcd.
-This prevents some cases where 5.4 Ghz is selected when
-it shouldn't be.
-
-v2: simplify logic, add array bounds check
-
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 96 ++++++++++++--------------------
- 1 file changed, 36 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
-index 92b6aca..21aacc1 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
-@@ -243,7 +243,7 @@ static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STA
- 
- /* convert bits per color to bits per pixel */
- /* get bpc from the EDID */
--static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
-+static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
- {
- 	if (bpc == 0)
- 		return 24;
-@@ -251,64 +251,32 @@ static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
- 		return bpc * 3;
- }
- 
--/* get the max pix clock supported by the link rate and lane num */
--static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate,
--					    int lane_num,
--					    int bpp)
--{
--	return (link_rate * lane_num * 8) / bpp;
--}
--
- /***** amdgpu specific DP functions *****/
- 
--/* First get the min lane# when low rate is used according to pixel clock
-- * (prefer low rate), second check max lane# supported by DP panel,
-- * if the max lane# < low rate lane# then use max lane# instead.
-- */
--static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector,
-+static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
- 						 const u8 dpcd[DP_DPCD_SIZE],
--						 int pix_clock)
--{
--	int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
--	int max_link_rate = drm_dp_max_link_rate(dpcd);
--	int max_lane_num = drm_dp_max_lane_count(dpcd);
--	int lane_num;
--	int max_dp_pix_clock;
--
--	for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
--		max_dp_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
--		if (pix_clock <= max_dp_pix_clock)
--			break;
--	}
--
--	return lane_num;
--}
--
--static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector,
--						const u8 dpcd[DP_DPCD_SIZE],
--						int pix_clock)
-+						 unsigned pix_clock,
-+						 unsigned *dp_lanes, unsigned *dp_rate)
- {
--	int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
--	int lane_num, max_pix_clock;
--
--	if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
--	    ENCODER_OBJECT_ID_NUTMEG)
--		return 270000;
--
--	lane_num = amdgpu_atombios_dp_get_dp_lane_number(connector, dpcd, pix_clock);
--	max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(162000, lane_num, bpp);
--	if (pix_clock <= max_pix_clock)
--		return 162000;
--	max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(270000, lane_num, bpp);
--	if (pix_clock <= max_pix_clock)
--		return 270000;
--	if (amdgpu_connector_is_dp12_capable(connector)) {
--		max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(540000, lane_num, bpp);
--		if (pix_clock <= max_pix_clock)
--			return 540000;
-+	unsigned bpp =
-+		amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
-+	static const unsigned link_rates[3] = { 162000, 270000, 540000 };
-+	unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
-+	unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
-+	unsigned lane_num, i, max_pix_clock;
-+
-+	for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
-+		for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
-+			max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
-+			if (max_pix_clock >= pix_clock) {
-+				*dp_lanes = lane_num;
-+				*dp_rate = link_rates[i];
-+				return 0;
-+			}
-+		}
- 	}
- 
--	return drm_dp_max_link_rate(dpcd);
-+	return -EINVAL;
- }
- 
- static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
-@@ -422,6 +390,7 @@ void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
- {
- 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
- 	struct amdgpu_connector_atom_dig *dig_connector;
-+	int ret;
- 
- 	if (!amdgpu_connector->con_priv)
- 		return;
-@@ -429,10 +398,14 @@ void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
- 
- 	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
- 	    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
--		dig_connector->dp_clock =
--			amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
--		dig_connector->dp_lane_count =
--			amdgpu_atombios_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
-+		ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
-+							    mode->clock,
-+							    &dig_connector->dp_lane_count,
-+							    &dig_connector->dp_clock);
-+		if (ret) {
-+			dig_connector->dp_clock = 0;
-+			dig_connector->dp_lane_count = 0;
-+		}
- 	}
- }
- 
-@@ -441,14 +414,17 @@ int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
- {
- 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
- 	struct amdgpu_connector_atom_dig *dig_connector;
--	int dp_clock;
-+	unsigned dp_lanes, dp_clock;
-+	int ret;
- 
- 	if (!amdgpu_connector->con_priv)
- 		return MODE_CLOCK_HIGH;
- 	dig_connector = amdgpu_connector->con_priv;
- 
--	dp_clock =
--		amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
-+	ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
-+						    mode->clock, &dp_lanes, &dp_clock);
-+	if (ret)
-+		return MODE_CLOCK_HIGH;
- 
- 	if ((dp_clock == 540000) &&
- 	    (!amdgpu_connector_is_dp12_capable(connector)))
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0034-drm-amdgpu-share-struct-amdgpu_pm_state_type-with-po.patch b/common/recipes-kernel/linux/files/0034-drm-amdgpu-share-struct-amdgpu_pm_state_type-with-po.patch
deleted file mode 100644
index aa2849ca..00000000
--- a/common/recipes-kernel/linux/files/0034-drm-amdgpu-share-struct-amdgpu_pm_state_type-with-po.patch
+++ /dev/null
@@ -1,139 +0,0 @@
-From 18fb4fa3bf16be2c4482ba3f82df55c36d6c669b Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 25 Aug 2015 15:57:43 +0800
-Subject: [PATCH 0034/1110] drm/amdgpu: share struct amdgpu_pm_state_type with
- powerplay module
-
-rename amdgpu_pm_state_type to amd_pm_state_type
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 28 ++--------------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c   |  8 ++++----
- drivers/gpu/drm/amd/include/amd_shared.h | 21 +++++++++++++++++++++
- 3 files changed, 27 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 41bee9e..a10f421 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1307,31 +1307,7 @@ struct amdgpu_wb {
- int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
- void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
- 
--/**
-- * struct amdgpu_pm - power management datas
-- * It keeps track of various data needed to take powermanagement decision.
-- */
- 
--enum amdgpu_pm_state_type {
--	/* not used for dpm */
--	POWER_STATE_TYPE_DEFAULT,
--	POWER_STATE_TYPE_POWERSAVE,
--	/* user selectable states */
--	POWER_STATE_TYPE_BATTERY,
--	POWER_STATE_TYPE_BALANCED,
--	POWER_STATE_TYPE_PERFORMANCE,
--	/* internal states */
--	POWER_STATE_TYPE_INTERNAL_UVD,
--	POWER_STATE_TYPE_INTERNAL_UVD_SD,
--	POWER_STATE_TYPE_INTERNAL_UVD_HD,
--	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
--	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
--	POWER_STATE_TYPE_INTERNAL_BOOT,
--	POWER_STATE_TYPE_INTERNAL_THERMAL,
--	POWER_STATE_TYPE_INTERNAL_ACPI,
--	POWER_STATE_TYPE_INTERNAL_ULV,
--	POWER_STATE_TYPE_INTERNAL_3DPERF,
--};
- 
- enum amdgpu_int_thermal_type {
- 	THERMAL_TYPE_NONE,
-@@ -1613,8 +1589,8 @@ struct amdgpu_dpm {
- 	/* vce requirements */
- 	struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
- 	enum amdgpu_vce_level vce_level;
--	enum amdgpu_pm_state_type state;
--	enum amdgpu_pm_state_type user_state;
-+	enum amd_pm_state_type state;
-+	enum amd_pm_state_type user_state;
- 	u32                     platform_caps;
- 	u32                     voltage_response_time;
- 	u32                     backbias_response_time;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 7ae15fa..feb247d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -52,7 +52,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	enum amdgpu_pm_state_type pm = adev->pm.dpm.user_state;
-+	enum amd_pm_state_type pm = adev->pm.dpm.user_state;
- 
- 	return snprintf(buf, PAGE_SIZE, "%s\n",
- 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
-@@ -351,7 +351,7 @@ void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
- 		container_of(work, struct amdgpu_device,
- 			     pm.dpm.thermal.work);
- 	/* switch to the thermal state */
--	enum amdgpu_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
-+	enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
- 
- 	if (!adev->pm.dpm_enabled)
- 		return;
-@@ -379,7 +379,7 @@ void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
- }
- 
- static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
--						     enum amdgpu_pm_state_type dpm_state)
-+						     enum amd_pm_state_type dpm_state)
- {
- 	int i;
- 	struct amdgpu_ps *ps;
-@@ -516,7 +516,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
- {
- 	int i;
- 	struct amdgpu_ps *ps;
--	enum amdgpu_pm_state_type dpm_state;
-+	enum amd_pm_state_type dpm_state;
- 	int ret;
- 
- 	/* if dpm init failed */
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index fe28fb3..1195d06 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -85,6 +85,27 @@ enum amd_powergating_state {
- 	AMD_PG_STATE_UNGATE,
- };
- 
-+enum amd_pm_state_type {
-+	/* not used for dpm */
-+	POWER_STATE_TYPE_DEFAULT,
-+	POWER_STATE_TYPE_POWERSAVE,
-+	/* user selectable states */
-+	POWER_STATE_TYPE_BATTERY,
-+	POWER_STATE_TYPE_BALANCED,
-+	POWER_STATE_TYPE_PERFORMANCE,
-+	/* internal states */
-+	POWER_STATE_TYPE_INTERNAL_UVD,
-+	POWER_STATE_TYPE_INTERNAL_UVD_SD,
-+	POWER_STATE_TYPE_INTERNAL_UVD_HD,
-+	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
-+	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
-+	POWER_STATE_TYPE_INTERNAL_BOOT,
-+	POWER_STATE_TYPE_INTERNAL_THERMAL,
-+	POWER_STATE_TYPE_INTERNAL_ACPI,
-+	POWER_STATE_TYPE_INTERNAL_ULV,
-+	POWER_STATE_TYPE_INTERNAL_3DPERF,
-+};
-+
- struct amd_ip_funcs {
- 	/* sets up early driver state (pre sw_init), does not configure hw - Optional */
- 	int (*early_init)(void *handle);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0035-drm-amdgpu-mv-some-definition-from-amdgpu_acpi.c-to-.patch b/common/recipes-kernel/linux/files/0035-drm-amdgpu-mv-some-definition-from-amdgpu_acpi.c-to-.patch
deleted file mode 100644
index c3b90722..00000000
--- a/common/recipes-kernel/linux/files/0035-drm-amdgpu-mv-some-definition-from-amdgpu_acpi.c-to-.patch
+++ /dev/null
@@ -1,156 +0,0 @@
-From e6d674b817372a28ed00bf9b8bd8444ae86e49c5 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 21 Sep 2015 14:29:10 +0800
-Subject: [PATCH 0035/1110] drm/amdgpu: mv some definition from amdgpu_acpi.c
- to amdgpu_acpi.h
-
-These will be shared with the new powerplay module.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 56 -------------------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h | 57 +++++++++++++++++++++++++++++---
- 2 files changed, 53 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
-index a142d5a..5df5b83 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
-@@ -32,63 +32,7 @@
- #include "amdgpu_acpi.h"
- #include "atom.h"
- 
--#define ACPI_AC_CLASS           "ac_adapter"
--
- extern void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
--
--struct atif_verify_interface {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u16 version;		/* version */
--	u32 notification_mask;	/* supported notifications mask */
--	u32 function_bits;	/* supported functions bit vector */
--} __packed;
--
--struct atif_system_params {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u32 valid_mask;		/* valid flags mask */
--	u32 flags;		/* flags */
--	u8 command_code;	/* notify command code */
--} __packed;
--
--struct atif_sbios_requests {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u32 pending;		/* pending sbios requests */
--	u8 panel_exp_mode;	/* panel expansion mode */
--	u8 thermal_gfx;		/* thermal state: target gfx controller */
--	u8 thermal_state;	/* thermal state: state id (0: exit state, non-0: state) */
--	u8 forced_power_gfx;	/* forced power state: target gfx controller */
--	u8 forced_power_state;	/* forced power state: state id */
--	u8 system_power_src;	/* system power source */
--	u8 backlight_level;	/* panel backlight level (0-255) */
--} __packed;
--
--#define ATIF_NOTIFY_MASK	0x3
--#define ATIF_NOTIFY_NONE	0
--#define ATIF_NOTIFY_81		1
--#define ATIF_NOTIFY_N		2
--
--struct atcs_verify_interface {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u16 version;		/* version */
--	u32 function_bits;	/* supported functions bit vector */
--} __packed;
--
--#define ATCS_VALID_FLAGS_MASK	0x3
--
--struct atcs_pref_req_input {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u16 client_id;		/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
--	u16 valid_flags_mask;	/* valid flags mask */
--	u16 flags;		/* flags */
--	u8 req_type;		/* request type */
--	u8 perf_req;		/* performance request */
--} __packed;
--
--struct atcs_pref_req_output {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u8 ret_val;		/* return value */
--} __packed;
--
- /* Call the ATIF method
-  */
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
-index 01a29c3..51ce3e3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
-@@ -24,11 +24,60 @@
- #ifndef AMDGPU_ACPI_H
- #define AMDGPU_ACPI_H
- 
--struct amdgpu_device;
--struct acpi_bus_event;
-+#define ACPI_AC_CLASS           "ac_adapter"
- 
--int amdgpu_atif_handler(struct amdgpu_device *adev,
--		struct acpi_bus_event *event);
-+struct atif_verify_interface {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u16 version;		/* version */
-+	u32 notification_mask;	/* supported notifications mask */
-+	u32 function_bits;	/* supported functions bit vector */
-+} __packed;
-+
-+struct atif_system_params {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u32 valid_mask;		/* valid flags mask */
-+	u32 flags;		/* flags */
-+	u8 command_code;	/* notify command code */
-+} __packed;
-+
-+struct atif_sbios_requests {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u32 pending;		/* pending sbios requests */
-+	u8 panel_exp_mode;	/* panel expansion mode */
-+	u8 thermal_gfx;		/* thermal state: target gfx controller */
-+	u8 thermal_state;	/* thermal state: state id (0: exit state, non-0: state) */
-+	u8 forced_power_gfx;	/* forced power state: target gfx controller */
-+	u8 forced_power_state;	/* forced power state: state id */
-+	u8 system_power_src;	/* system power source */
-+	u8 backlight_level;	/* panel backlight level (0-255) */
-+} __packed;
-+
-+#define ATIF_NOTIFY_MASK	0x3
-+#define ATIF_NOTIFY_NONE	0
-+#define ATIF_NOTIFY_81		1
-+#define ATIF_NOTIFY_N		2
-+
-+struct atcs_verify_interface {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u16 version;		/* version */
-+	u32 function_bits;	/* supported functions bit vector */
-+} __packed;
-+
-+#define ATCS_VALID_FLAGS_MASK	0x3
-+
-+struct atcs_pref_req_input {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u16 client_id;		/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
-+	u16 valid_flags_mask;	/* valid flags mask */
-+	u16 flags;		/* flags */
-+	u8 req_type;		/* request type */
-+	u8 perf_req;		/* performance request */
-+} __packed;
-+
-+struct atcs_pref_req_output {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u8 ret_val;		/* return value */
-+} __packed;
- 
- /* AMD hw uses four ACPI control methods:
-  * 1. ATIF
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0036-drm-amdgpu-mv-amdgpu_acpi.h-to-amd-include-amd_acpi..patch b/common/recipes-kernel/linux/files/0036-drm-amdgpu-mv-amdgpu_acpi.h-to-amd-include-amd_acpi..patch
deleted file mode 100644
index fa15df41..00000000
--- a/common/recipes-kernel/linux/files/0036-drm-amdgpu-mv-amdgpu_acpi.h-to-amd-include-amd_acpi..patch
+++ /dev/null
@@ -1,1049 +0,0 @@
-From cf4cf15eac940a77b70da8e9b4e4fe114c281fd0 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 18 Sep 2015 16:35:17 +0800
-Subject: [PATCH 0036/1110] drm/amdgpu: mv amdgpu_acpi.h to
- amd/include/amd_acpi.h
-
-This will be shared with the new powerplay module.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c         |   2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h         | 494 -----------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c |   2 +-
- drivers/gpu/drm/amd/include/amd_acpi.h           | 494 +++++++++++++++++++++++
- 4 files changed, 496 insertions(+), 496 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
- create mode 100644 drivers/gpu/drm/amd/include/amd_acpi.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
-index 5df5b83..5cd7b73 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
-@@ -29,7 +29,7 @@
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include "amdgpu.h"
--#include "amdgpu_acpi.h"
-+#include "amd_acpi.h"
- #include "atom.h"
- 
- extern void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
-deleted file mode 100644
-index 51ce3e3..0000000
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
-+++ /dev/null
-@@ -1,494 +0,0 @@
--/*
-- * Copyright 2012 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef AMDGPU_ACPI_H
--#define AMDGPU_ACPI_H
--
--#define ACPI_AC_CLASS           "ac_adapter"
--
--struct atif_verify_interface {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u16 version;		/* version */
--	u32 notification_mask;	/* supported notifications mask */
--	u32 function_bits;	/* supported functions bit vector */
--} __packed;
--
--struct atif_system_params {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u32 valid_mask;		/* valid flags mask */
--	u32 flags;		/* flags */
--	u8 command_code;	/* notify command code */
--} __packed;
--
--struct atif_sbios_requests {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u32 pending;		/* pending sbios requests */
--	u8 panel_exp_mode;	/* panel expansion mode */
--	u8 thermal_gfx;		/* thermal state: target gfx controller */
--	u8 thermal_state;	/* thermal state: state id (0: exit state, non-0: state) */
--	u8 forced_power_gfx;	/* forced power state: target gfx controller */
--	u8 forced_power_state;	/* forced power state: state id */
--	u8 system_power_src;	/* system power source */
--	u8 backlight_level;	/* panel backlight level (0-255) */
--} __packed;
--
--#define ATIF_NOTIFY_MASK	0x3
--#define ATIF_NOTIFY_NONE	0
--#define ATIF_NOTIFY_81		1
--#define ATIF_NOTIFY_N		2
--
--struct atcs_verify_interface {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u16 version;		/* version */
--	u32 function_bits;	/* supported functions bit vector */
--} __packed;
--
--#define ATCS_VALID_FLAGS_MASK	0x3
--
--struct atcs_pref_req_input {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u16 client_id;		/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
--	u16 valid_flags_mask;	/* valid flags mask */
--	u16 flags;		/* flags */
--	u8 req_type;		/* request type */
--	u8 perf_req;		/* performance request */
--} __packed;
--
--struct atcs_pref_req_output {
--	u16 size;		/* structure size in bytes (includes size field) */
--	u8 ret_val;		/* return value */
--} __packed;
--
--/* AMD hw uses four ACPI control methods:
-- * 1. ATIF
-- * ARG0: (ACPI_INTEGER) function code
-- * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
-- * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
-- * ATIF provides an entry point for the gfx driver to interact with the sbios.
-- * The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom
-- * notification. Which notification is used as indicated by the ATIF Control
-- * Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or
-- * a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS
-- * to identify pending System BIOS requests and associated parameters. For
-- * example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver
-- * will perform display device detection and invoke ATIF Control Method
-- * SELECT_ACTIVE_DISPLAYS.
-- *
-- * 2. ATPX
-- * ARG0: (ACPI_INTEGER) function code
-- * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
-- * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
-- * ATPX methods are used on PowerXpress systems to handle mux switching and
-- * discrete GPU power control.
-- *
-- * 3. ATRM
-- * ARG0: (ACPI_INTEGER) offset of vbios rom data
-- * ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K).
-- * OUTPUT: (ACPI_BUFFER) output buffer
-- * ATRM provides an interfacess to access the discrete GPU vbios image on
-- * PowerXpress systems with multiple GPUs.
-- *
-- * 4. ATCS
-- * ARG0: (ACPI_INTEGER) function code
-- * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
-- * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
-- * ATCS provides an interface to AMD chipset specific functionality.
-- *
-- */
--/* ATIF */
--#define ATIF_FUNCTION_VERIFY_INTERFACE                             0x0
--/* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - version
-- * DWORD - supported notifications mask
-- * DWORD - supported functions bit vector
-- */
--/* Notifications mask */
--#       define ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED               (1 << 0)
--#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED        (1 << 1)
--#       define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED         (1 << 2)
--#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED    (1 << 3)
--#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED   (1 << 4)
--#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED          (1 << 5)
--#       define ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED                (1 << 6)
--#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED      (1 << 7)
--#       define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED                   (1 << 8)
--/* supported functions vector */
--#       define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED               (1 << 0)
--#       define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED            (1 << 1)
--#       define ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED              (1 << 2)
--#       define ATIF_GET_LID_STATE_SUPPORTED                       (1 << 3)
--#       define ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED           (1 << 4)
--#       define ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED             (1 << 5)
--#       define ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED  (1 << 6)
--#       define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED    (1 << 7)
--#       define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED     (1 << 12)
--#       define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED           (1 << 14)
--#define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS                        0x1
--/* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * DWORD - valid flags mask
-- * DWORD - flags
-- *
-- * OR
-- *
-- * WORD  - structure size in bytes (includes size field)
-- * DWORD - valid flags mask
-- * DWORD - flags
-- * BYTE  - notify command code
-- *
-- * flags
-- * bits 1:0:
-- * 0 - Notify(VGA, 0x81) is not used for notification
-- * 1 - Notify(VGA, 0x81) is used for notification
-- * 2 - Notify(VGA, n) is used for notification where
-- * n (0xd0-0xd9) is specified in notify command code.
-- * bit 2:
-- * 1 - lid changes not reported though int10
-- */
--#define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS                     0x2
--/* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * DWORD - pending sbios requests
-- * BYTE  - panel expansion mode
-- * BYTE  - thermal state: target gfx controller
-- * BYTE  - thermal state: state id (0: exit state, non-0: state)
-- * BYTE  - forced power state: target gfx controller
-- * BYTE  - forced power state: state id
-- * BYTE  - system power source
-- * BYTE  - panel backlight level (0-255)
-- */
--/* pending sbios requests */
--#       define ATIF_DISPLAY_SWITCH_REQUEST                         (1 << 0)
--#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST                  (1 << 1)
--#       define ATIF_THERMAL_STATE_CHANGE_REQUEST                   (1 << 2)
--#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST              (1 << 3)
--#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST             (1 << 4)
--#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST                    (1 << 5)
--#       define ATIF_PX_GFX_SWITCH_REQUEST                          (1 << 6)
--#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST                (1 << 7)
--#       define ATIF_DGPU_DISPLAY_EVENT                             (1 << 8)
--/* panel expansion mode */
--#       define ATIF_PANEL_EXPANSION_DISABLE                        0
--#       define ATIF_PANEL_EXPANSION_FULL                           1
--#       define ATIF_PANEL_EXPANSION_ASPECT                         2
--/* target gfx controller */
--#       define ATIF_TARGET_GFX_SINGLE                              0
--#       define ATIF_TARGET_GFX_PX_IGPU                             1
--#       define ATIF_TARGET_GFX_PX_DGPU                             2
--/* system power source */
--#       define ATIF_POWER_SOURCE_AC                                1
--#       define ATIF_POWER_SOURCE_DC                                2
--#       define ATIF_POWER_SOURCE_RESTRICTED_AC_1                   3
--#       define ATIF_POWER_SOURCE_RESTRICTED_AC_2                   4
--#define ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS                       0x3
--/* ARG0: ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - selected displays
-- * WORD  - connected displays
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - selected displays
-- */
--#       define ATIF_LCD1                                           (1 << 0)
--#       define ATIF_CRT1                                           (1 << 1)
--#       define ATIF_TV                                             (1 << 2)
--#       define ATIF_DFP1                                           (1 << 3)
--#       define ATIF_CRT2                                           (1 << 4)
--#       define ATIF_LCD2                                           (1 << 5)
--#       define ATIF_DFP2                                           (1 << 7)
--#       define ATIF_CV                                             (1 << 8)
--#       define ATIF_DFP3                                           (1 << 9)
--#       define ATIF_DFP4                                           (1 << 10)
--#       define ATIF_DFP5                                           (1 << 11)
--#       define ATIF_DFP6                                           (1 << 12)
--#define ATIF_FUNCTION_GET_LID_STATE                                0x4
--/* ARG0: ATIF_FUNCTION_GET_LID_STATE
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - lid state (0: open, 1: closed)
-- *
-- * GET_LID_STATE only works at boot and resume, for general lid
-- * status, use the kernel provided status
-- */
--#define ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS                    0x5
--/* ARG0: ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - 0
-- * BYTE  - TV standard
-- */
--#       define ATIF_TV_STD_NTSC                                    0
--#       define ATIF_TV_STD_PAL                                     1
--#       define ATIF_TV_STD_PALM                                    2
--#       define ATIF_TV_STD_PAL60                                   3
--#       define ATIF_TV_STD_NTSCJ                                   4
--#       define ATIF_TV_STD_PALCN                                   5
--#       define ATIF_TV_STD_PALN                                    6
--#       define ATIF_TV_STD_SCART_RGB                               9
--#define ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS                      0x6
--/* ARG0: ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - 0
-- * BYTE  - TV standard
-- * OUTPUT: none
-- */
--#define ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS           0x7
--/* ARG0: ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - panel expansion mode
-- */
--#define ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS             0x8
--/* ARG0: ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - panel expansion mode
-- * OUTPUT: none
-- */
--#define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION              0xD
--/* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - gfx controller id
-- * BYTE  - current temperature (degress Celsius)
-- * OUTPUT: none
-- */
--#define ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES                    0xF
--/* ARG0: ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - number of gfx devices
-- * WORD  - device structure size in bytes (excludes device size field)
-- * DWORD - flags         \
-- * WORD  - bus number     } repeated structure
-- * WORD  - device number /
-- */
--/* flags */
--#       define ATIF_PX_REMOVABLE_GRAPHICS_DEVICE                   (1 << 0)
--#       define ATIF_XGP_PORT                                       (1 << 1)
--#       define ATIF_VGA_ENABLED_GRAPHICS_DEVICE                    (1 << 2)
--#       define ATIF_XGP_PORT_IN_DOCK                               (1 << 3)
--
--/* ATPX */
--#define ATPX_FUNCTION_VERIFY_INTERFACE                             0x0
--/* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - version
-- * DWORD - supported functions bit vector
-- */
--/* supported functions vector */
--#       define ATPX_GET_PX_PARAMETERS_SUPPORTED                    (1 << 0)
--#       define ATPX_POWER_CONTROL_SUPPORTED                        (1 << 1)
--#       define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED                  (1 << 2)
--#       define ATPX_I2C_MUX_CONTROL_SUPPORTED                      (1 << 3)
--#       define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4)
--#       define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED   (1 << 5)
--#       define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED       (1 << 7)
--#       define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED          (1 << 8)
--#define ATPX_FUNCTION_GET_PX_PARAMETERS                            0x1
--/* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * DWORD - valid flags mask
-- * DWORD - flags
-- */
--/* flags */
--#       define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 0)
--#       define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 1)
--#       define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 2)
--#       define ATPX_CRT1_RGB_SIGNAL_MUXED                          (1 << 3)
--#       define ATPX_TV_SIGNAL_MUXED                                (1 << 4)
--#       define ATPX_DFP_SIGNAL_MUXED                               (1 << 5)
--#       define ATPX_SEPARATE_MUX_FOR_I2C                           (1 << 6)
--#       define ATPX_DYNAMIC_PX_SUPPORTED                           (1 << 7)
--#       define ATPX_ACF_NOT_SUPPORTED                              (1 << 8)
--#       define ATPX_FIXED_NOT_SUPPORTED                            (1 << 9)
--#       define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED               (1 << 10)
--#       define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS                    (1 << 11)
--#define ATPX_FUNCTION_POWER_CONTROL                                0x2
--/* ARG0: ATPX_FUNCTION_POWER_CONTROL
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - dGPU power state (0: power off, 1: power on)
-- * OUTPUT: none
-- */
--#define ATPX_FUNCTION_DISPLAY_MUX_CONTROL                          0x3
--/* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - display mux control (0: iGPU, 1: dGPU)
-- * OUTPUT: none
-- */
--#       define ATPX_INTEGRATED_GPU                                 0
--#       define ATPX_DISCRETE_GPU                                   1
--#define ATPX_FUNCTION_I2C_MUX_CONTROL                              0x4
--/* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - i2c/aux/hpd mux control (0: iGPU, 1: dGPU)
-- * OUTPUT: none
-- */
--#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION    0x5
--/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - target gpu (0: iGPU, 1: dGPU)
-- * OUTPUT: none
-- */
--#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION      0x6
--/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - target gpu (0: iGPU, 1: dGPU)
-- * OUTPUT: none
-- */
--#define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING               0x8
--/* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - number of display connectors
-- * WORD  - connector structure size in bytes (excludes connector size field)
-- * BYTE  - flags                                                     \
-- * BYTE  - ATIF display vector bit position                           } repeated
-- * BYTE  - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure
-- * WORD  - connector ACPI id                                         /
-- */
--/* flags */
--#       define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE  (1 << 0)
--#       define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 1)
--#       define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 2)
--#define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS                  0x9
--/* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - number of HPD/DDC ports
-- * WORD  - port structure size in bytes (excludes port size field)
-- * BYTE  - ATIF display vector bit position \
-- * BYTE  - hpd id                            } reapeated structure
-- * BYTE  - ddc id                           /
-- *
-- * available on A+A systems only
-- */
--/* hpd id */
--#       define ATPX_HPD_NONE                                       0
--#       define ATPX_HPD1                                           1
--#       define ATPX_HPD2                                           2
--#       define ATPX_HPD3                                           3
--#       define ATPX_HPD4                                           4
--#       define ATPX_HPD5                                           5
--#       define ATPX_HPD6                                           6
--/* ddc id */
--#       define ATPX_DDC_NONE                                       0
--#       define ATPX_DDC1                                           1
--#       define ATPX_DDC2                                           2
--#       define ATPX_DDC3                                           3
--#       define ATPX_DDC4                                           4
--#       define ATPX_DDC5                                           5
--#       define ATPX_DDC6                                           6
--#       define ATPX_DDC7                                           7
--#       define ATPX_DDC8                                           8
--
--/* ATCS */
--#define ATCS_FUNCTION_VERIFY_INTERFACE                             0x0
--/* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - version
-- * DWORD - supported functions bit vector
-- */
--/* supported functions vector */
--#       define ATCS_GET_EXTERNAL_STATE_SUPPORTED                   (1 << 0)
--#       define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED             (1 << 1)
--#       define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED       (1 << 2)
--#       define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED                   (1 << 3)
--#define ATCS_FUNCTION_GET_EXTERNAL_STATE                           0x1
--/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
-- * ARG1: none
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * DWORD - valid flags mask
-- * DWORD - flags (0: undocked, 1: docked)
-- */
--/* flags */
--#       define ATCS_DOCKED                                         (1 << 0)
--#define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST                     0x2
--/* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
-- * WORD  - valid flags mask
-- * WORD  - flags
-- * BYTE  - request type
-- * BYTE  - performance request
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - return value
-- */
--/* flags */
--#       define ATCS_ADVERTISE_CAPS                                 (1 << 0)
--#       define ATCS_WAIT_FOR_COMPLETION                            (1 << 1)
--/* request type */
--#       define ATCS_PCIE_LINK_SPEED                                1
--/* performance request */
--#       define ATCS_REMOVE                                         0
--#       define ATCS_FORCE_LOW_POWER                                1
--#       define ATCS_PERF_LEVEL_1                                   2 /* PCIE Gen 1 */
--#       define ATCS_PERF_LEVEL_2                                   3 /* PCIE Gen 2 */
--#       define ATCS_PERF_LEVEL_3                                   4 /* PCIE Gen 3 */
--/* return value */
--#       define ATCS_REQUEST_REFUSED                                1
--#       define ATCS_REQUEST_COMPLETE                               2
--#       define ATCS_REQUEST_IN_PROGRESS                            3
--#define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION               0x3
--/* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION
-- * ARG1: none
-- * OUTPUT: none
-- */
--#define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH                           0x4
--/* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH
-- * ARG1:
-- * WORD  - structure size in bytes (includes size field)
-- * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
-- * BYTE  - number of active lanes
-- * OUTPUT:
-- * WORD  - structure size in bytes (includes size field)
-- * BYTE  - number of active lanes
-- */
--
--#endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-index 5a8fbad..3c89586 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-@@ -11,7 +11,7 @@
- #include <linux/acpi.h>
- #include <linux/pci.h>
- 
--#include "amdgpu_acpi.h"
-+#include "amd_acpi.h"
- 
- struct amdgpu_atpx_functions {
- 	bool px_params;
-diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h
-new file mode 100644
-index 0000000..496360e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/amd_acpi.h
-@@ -0,0 +1,494 @@
-+/*
-+ * Copyright 2012 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef AMD_ACPI_H
-+#define AMD_ACPI_H
-+
-+#define ACPI_AC_CLASS           "ac_adapter"
-+
-+struct atif_verify_interface {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u16 version;		/* version */
-+	u32 notification_mask;	/* supported notifications mask */
-+	u32 function_bits;	/* supported functions bit vector */
-+} __packed;
-+
-+struct atif_system_params {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u32 valid_mask;		/* valid flags mask */
-+	u32 flags;		/* flags */
-+	u8 command_code;	/* notify command code */
-+} __packed;
-+
-+struct atif_sbios_requests {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u32 pending;		/* pending sbios requests */
-+	u8 panel_exp_mode;	/* panel expansion mode */
-+	u8 thermal_gfx;		/* thermal state: target gfx controller */
-+	u8 thermal_state;	/* thermal state: state id (0: exit state, non-0: state) */
-+	u8 forced_power_gfx;	/* forced power state: target gfx controller */
-+	u8 forced_power_state;	/* forced power state: state id */
-+	u8 system_power_src;	/* system power source */
-+	u8 backlight_level;	/* panel backlight level (0-255) */
-+} __packed;
-+
-+#define ATIF_NOTIFY_MASK	0x3
-+#define ATIF_NOTIFY_NONE	0
-+#define ATIF_NOTIFY_81		1
-+#define ATIF_NOTIFY_N		2
-+
-+struct atcs_verify_interface {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u16 version;		/* version */
-+	u32 function_bits;	/* supported functions bit vector */
-+} __packed;
-+
-+#define ATCS_VALID_FLAGS_MASK	0x3
-+
-+struct atcs_pref_req_input {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u16 client_id;		/* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
-+	u16 valid_flags_mask;	/* valid flags mask */
-+	u16 flags;		/* flags */
-+	u8 req_type;		/* request type */
-+	u8 perf_req;		/* performance request */
-+} __packed;
-+
-+struct atcs_pref_req_output {
-+	u16 size;		/* structure size in bytes (includes size field) */
-+	u8 ret_val;		/* return value */
-+} __packed;
-+
-+/* AMD hw uses four ACPI control methods:
-+ * 1. ATIF
-+ * ARG0: (ACPI_INTEGER) function code
-+ * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
-+ * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
-+ * ATIF provides an entry point for the gfx driver to interact with the sbios.
-+ * The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom
-+ * notification. Which notification is used as indicated by the ATIF Control
-+ * Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or
-+ * a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS
-+ * to identify pending System BIOS requests and associated parameters. For
-+ * example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver
-+ * will perform display device detection and invoke ATIF Control Method
-+ * SELECT_ACTIVE_DISPLAYS.
-+ *
-+ * 2. ATPX
-+ * ARG0: (ACPI_INTEGER) function code
-+ * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
-+ * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
-+ * ATPX methods are used on PowerXpress systems to handle mux switching and
-+ * discrete GPU power control.
-+ *
-+ * 3. ATRM
-+ * ARG0: (ACPI_INTEGER) offset of vbios rom data
-+ * ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K).
-+ * OUTPUT: (ACPI_BUFFER) output buffer
-+ * ATRM provides an interfacess to access the discrete GPU vbios image on
-+ * PowerXpress systems with multiple GPUs.
-+ *
-+ * 4. ATCS
-+ * ARG0: (ACPI_INTEGER) function code
-+ * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes
-+ * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes
-+ * ATCS provides an interface to AMD chipset specific functionality.
-+ *
-+ */
-+/* ATIF */
-+#define ATIF_FUNCTION_VERIFY_INTERFACE                             0x0
-+/* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - version
-+ * DWORD - supported notifications mask
-+ * DWORD - supported functions bit vector
-+ */
-+/* Notifications mask */
-+#       define ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED               (1 << 0)
-+#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED        (1 << 1)
-+#       define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED         (1 << 2)
-+#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED    (1 << 3)
-+#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED   (1 << 4)
-+#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED          (1 << 5)
-+#       define ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED                (1 << 6)
-+#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED      (1 << 7)
-+#       define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED                   (1 << 8)
-+/* supported functions vector */
-+#       define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED               (1 << 0)
-+#       define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED            (1 << 1)
-+#       define ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED              (1 << 2)
-+#       define ATIF_GET_LID_STATE_SUPPORTED                       (1 << 3)
-+#       define ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED           (1 << 4)
-+#       define ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED             (1 << 5)
-+#       define ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED  (1 << 6)
-+#       define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED    (1 << 7)
-+#       define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED     (1 << 12)
-+#       define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED           (1 << 14)
-+#define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS                        0x1
-+/* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * DWORD - valid flags mask
-+ * DWORD - flags
-+ *
-+ * OR
-+ *
-+ * WORD  - structure size in bytes (includes size field)
-+ * DWORD - valid flags mask
-+ * DWORD - flags
-+ * BYTE  - notify command code
-+ *
-+ * flags
-+ * bits 1:0:
-+ * 0 - Notify(VGA, 0x81) is not used for notification
-+ * 1 - Notify(VGA, 0x81) is used for notification
-+ * 2 - Notify(VGA, n) is used for notification where
-+ * n (0xd0-0xd9) is specified in notify command code.
-+ * bit 2:
-+ * 1 - lid changes not reported though int10
-+ */
-+#define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS                     0x2
-+/* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * DWORD - pending sbios requests
-+ * BYTE  - panel expansion mode
-+ * BYTE  - thermal state: target gfx controller
-+ * BYTE  - thermal state: state id (0: exit state, non-0: state)
-+ * BYTE  - forced power state: target gfx controller
-+ * BYTE  - forced power state: state id
-+ * BYTE  - system power source
-+ * BYTE  - panel backlight level (0-255)
-+ */
-+/* pending sbios requests */
-+#       define ATIF_DISPLAY_SWITCH_REQUEST                         (1 << 0)
-+#       define ATIF_EXPANSION_MODE_CHANGE_REQUEST                  (1 << 1)
-+#       define ATIF_THERMAL_STATE_CHANGE_REQUEST                   (1 << 2)
-+#       define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST              (1 << 3)
-+#       define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST             (1 << 4)
-+#       define ATIF_DISPLAY_CONF_CHANGE_REQUEST                    (1 << 5)
-+#       define ATIF_PX_GFX_SWITCH_REQUEST                          (1 << 6)
-+#       define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST                (1 << 7)
-+#       define ATIF_DGPU_DISPLAY_EVENT                             (1 << 8)
-+/* panel expansion mode */
-+#       define ATIF_PANEL_EXPANSION_DISABLE                        0
-+#       define ATIF_PANEL_EXPANSION_FULL                           1
-+#       define ATIF_PANEL_EXPANSION_ASPECT                         2
-+/* target gfx controller */
-+#       define ATIF_TARGET_GFX_SINGLE                              0
-+#       define ATIF_TARGET_GFX_PX_IGPU                             1
-+#       define ATIF_TARGET_GFX_PX_DGPU                             2
-+/* system power source */
-+#       define ATIF_POWER_SOURCE_AC                                1
-+#       define ATIF_POWER_SOURCE_DC                                2
-+#       define ATIF_POWER_SOURCE_RESTRICTED_AC_1                   3
-+#       define ATIF_POWER_SOURCE_RESTRICTED_AC_2                   4
-+#define ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS                       0x3
-+/* ARG0: ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - selected displays
-+ * WORD  - connected displays
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - selected displays
-+ */
-+#       define ATIF_LCD1                                           (1 << 0)
-+#       define ATIF_CRT1                                           (1 << 1)
-+#       define ATIF_TV                                             (1 << 2)
-+#       define ATIF_DFP1                                           (1 << 3)
-+#       define ATIF_CRT2                                           (1 << 4)
-+#       define ATIF_LCD2                                           (1 << 5)
-+#       define ATIF_DFP2                                           (1 << 7)
-+#       define ATIF_CV                                             (1 << 8)
-+#       define ATIF_DFP3                                           (1 << 9)
-+#       define ATIF_DFP4                                           (1 << 10)
-+#       define ATIF_DFP5                                           (1 << 11)
-+#       define ATIF_DFP6                                           (1 << 12)
-+#define ATIF_FUNCTION_GET_LID_STATE                                0x4
-+/* ARG0: ATIF_FUNCTION_GET_LID_STATE
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - lid state (0: open, 1: closed)
-+ *
-+ * GET_LID_STATE only works at boot and resume, for general lid
-+ * status, use the kernel provided status
-+ */
-+#define ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS                    0x5
-+/* ARG0: ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - 0
-+ * BYTE  - TV standard
-+ */
-+#       define ATIF_TV_STD_NTSC                                    0
-+#       define ATIF_TV_STD_PAL                                     1
-+#       define ATIF_TV_STD_PALM                                    2
-+#       define ATIF_TV_STD_PAL60                                   3
-+#       define ATIF_TV_STD_NTSCJ                                   4
-+#       define ATIF_TV_STD_PALCN                                   5
-+#       define ATIF_TV_STD_PALN                                    6
-+#       define ATIF_TV_STD_SCART_RGB                               9
-+#define ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS                      0x6
-+/* ARG0: ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - 0
-+ * BYTE  - TV standard
-+ * OUTPUT: none
-+ */
-+#define ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS           0x7
-+/* ARG0: ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - panel expansion mode
-+ */
-+#define ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS             0x8
-+/* ARG0: ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - panel expansion mode
-+ * OUTPUT: none
-+ */
-+#define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION              0xD
-+/* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - gfx controller id
-+ * BYTE  - current temperature (degress Celsius)
-+ * OUTPUT: none
-+ */
-+#define ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES                    0xF
-+/* ARG0: ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - number of gfx devices
-+ * WORD  - device structure size in bytes (excludes device size field)
-+ * DWORD - flags         \
-+ * WORD  - bus number     } repeated structure
-+ * WORD  - device number /
-+ */
-+/* flags */
-+#       define ATIF_PX_REMOVABLE_GRAPHICS_DEVICE                   (1 << 0)
-+#       define ATIF_XGP_PORT                                       (1 << 1)
-+#       define ATIF_VGA_ENABLED_GRAPHICS_DEVICE                    (1 << 2)
-+#       define ATIF_XGP_PORT_IN_DOCK                               (1 << 3)
-+
-+/* ATPX */
-+#define ATPX_FUNCTION_VERIFY_INTERFACE                             0x0
-+/* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - version
-+ * DWORD - supported functions bit vector
-+ */
-+/* supported functions vector */
-+#       define ATPX_GET_PX_PARAMETERS_SUPPORTED                    (1 << 0)
-+#       define ATPX_POWER_CONTROL_SUPPORTED                        (1 << 1)
-+#       define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED                  (1 << 2)
-+#       define ATPX_I2C_MUX_CONTROL_SUPPORTED                      (1 << 3)
-+#       define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4)
-+#       define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED   (1 << 5)
-+#       define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED       (1 << 7)
-+#       define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED          (1 << 8)
-+#define ATPX_FUNCTION_GET_PX_PARAMETERS                            0x1
-+/* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * DWORD - valid flags mask
-+ * DWORD - flags
-+ */
-+/* flags */
-+#       define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 0)
-+#       define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 1)
-+#       define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS                (1 << 2)
-+#       define ATPX_CRT1_RGB_SIGNAL_MUXED                          (1 << 3)
-+#       define ATPX_TV_SIGNAL_MUXED                                (1 << 4)
-+#       define ATPX_DFP_SIGNAL_MUXED                               (1 << 5)
-+#       define ATPX_SEPARATE_MUX_FOR_I2C                           (1 << 6)
-+#       define ATPX_DYNAMIC_PX_SUPPORTED                           (1 << 7)
-+#       define ATPX_ACF_NOT_SUPPORTED                              (1 << 8)
-+#       define ATPX_FIXED_NOT_SUPPORTED                            (1 << 9)
-+#       define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED               (1 << 10)
-+#       define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS                    (1 << 11)
-+#define ATPX_FUNCTION_POWER_CONTROL                                0x2
-+/* ARG0: ATPX_FUNCTION_POWER_CONTROL
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - dGPU power state (0: power off, 1: power on)
-+ * OUTPUT: none
-+ */
-+#define ATPX_FUNCTION_DISPLAY_MUX_CONTROL                          0x3
-+/* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - display mux control (0: iGPU, 1: dGPU)
-+ * OUTPUT: none
-+ */
-+#       define ATPX_INTEGRATED_GPU                                 0
-+#       define ATPX_DISCRETE_GPU                                   1
-+#define ATPX_FUNCTION_I2C_MUX_CONTROL                              0x4
-+/* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - i2c/aux/hpd mux control (0: iGPU, 1: dGPU)
-+ * OUTPUT: none
-+ */
-+#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION    0x5
-+/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - target gpu (0: iGPU, 1: dGPU)
-+ * OUTPUT: none
-+ */
-+#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION      0x6
-+/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - target gpu (0: iGPU, 1: dGPU)
-+ * OUTPUT: none
-+ */
-+#define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING               0x8
-+/* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - number of display connectors
-+ * WORD  - connector structure size in bytes (excludes connector size field)
-+ * BYTE  - flags                                                     \
-+ * BYTE  - ATIF display vector bit position                           } repeated
-+ * BYTE  - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure
-+ * WORD  - connector ACPI id                                         /
-+ */
-+/* flags */
-+#       define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE  (1 << 0)
-+#       define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 1)
-+#       define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE     (1 << 2)
-+#define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS                  0x9
-+/* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - number of HPD/DDC ports
-+ * WORD  - port structure size in bytes (excludes port size field)
-+ * BYTE  - ATIF display vector bit position \
-+ * BYTE  - hpd id                            } reapeated structure
-+ * BYTE  - ddc id                           /
-+ *
-+ * available on A+A systems only
-+ */
-+/* hpd id */
-+#       define ATPX_HPD_NONE                                       0
-+#       define ATPX_HPD1                                           1
-+#       define ATPX_HPD2                                           2
-+#       define ATPX_HPD3                                           3
-+#       define ATPX_HPD4                                           4
-+#       define ATPX_HPD5                                           5
-+#       define ATPX_HPD6                                           6
-+/* ddc id */
-+#       define ATPX_DDC_NONE                                       0
-+#       define ATPX_DDC1                                           1
-+#       define ATPX_DDC2                                           2
-+#       define ATPX_DDC3                                           3
-+#       define ATPX_DDC4                                           4
-+#       define ATPX_DDC5                                           5
-+#       define ATPX_DDC6                                           6
-+#       define ATPX_DDC7                                           7
-+#       define ATPX_DDC8                                           8
-+
-+/* ATCS */
-+#define ATCS_FUNCTION_VERIFY_INTERFACE                             0x0
-+/* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - version
-+ * DWORD - supported functions bit vector
-+ */
-+/* supported functions vector */
-+#       define ATCS_GET_EXTERNAL_STATE_SUPPORTED                   (1 << 0)
-+#       define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED             (1 << 1)
-+#       define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED       (1 << 2)
-+#       define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED                   (1 << 3)
-+#define ATCS_FUNCTION_GET_EXTERNAL_STATE                           0x1
-+/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
-+ * ARG1: none
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * DWORD - valid flags mask
-+ * DWORD - flags (0: undocked, 1: docked)
-+ */
-+/* flags */
-+#       define ATCS_DOCKED                                         (1 << 0)
-+#define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST                     0x2
-+/* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
-+ * WORD  - valid flags mask
-+ * WORD  - flags
-+ * BYTE  - request type
-+ * BYTE  - performance request
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - return value
-+ */
-+/* flags */
-+#       define ATCS_ADVERTISE_CAPS                                 (1 << 0)
-+#       define ATCS_WAIT_FOR_COMPLETION                            (1 << 1)
-+/* request type */
-+#       define ATCS_PCIE_LINK_SPEED                                1
-+/* performance request */
-+#       define ATCS_REMOVE                                         0
-+#       define ATCS_FORCE_LOW_POWER                                1
-+#       define ATCS_PERF_LEVEL_1                                   2 /* PCIE Gen 1 */
-+#       define ATCS_PERF_LEVEL_2                                   3 /* PCIE Gen 2 */
-+#       define ATCS_PERF_LEVEL_3                                   4 /* PCIE Gen 3 */
-+/* return value */
-+#       define ATCS_REQUEST_REFUSED                                1
-+#       define ATCS_REQUEST_COMPLETE                               2
-+#       define ATCS_REQUEST_IN_PROGRESS                            3
-+#define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION               0x3
-+/* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION
-+ * ARG1: none
-+ * OUTPUT: none
-+ */
-+#define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH                           0x4
-+/* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH
-+ * ARG1:
-+ * WORD  - structure size in bytes (includes size field)
-+ * WORD  - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
-+ * BYTE  - number of active lanes
-+ * OUTPUT:
-+ * WORD  - structure size in bytes (includes size field)
-+ * BYTE  - number of active lanes
-+ */
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0037-drm-amdgpu-implement-new-cgs-interface-for-acpi-func.patch b/common/recipes-kernel/linux/files/0037-drm-amdgpu-implement-new-cgs-interface-for-acpi-func.patch
deleted file mode 100644
index f71e744e..00000000
--- a/common/recipes-kernel/linux/files/0037-drm-amdgpu-implement-new-cgs-interface-for-acpi-func.patch
+++ /dev/null
@@ -1,349 +0,0 @@
-From 80cec685ee980cb171f2f73d1df702afbbc0bbb8 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 15 Sep 2015 14:44:44 +0800
-Subject: [PATCH 0037/1110] drm/amdgpu: implement new cgs interface for acpi
- function
-
-Add a new driver internal interface for accessing ACPI
-methods.  These will be used by various new components
-including powerplay.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 220 ++++++++++++++++++++++++++++++-
- drivers/gpu/drm/amd/include/cgs_common.h |  45 ++++++-
- 2 files changed, 262 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 8e99514..f901cdc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -24,6 +24,7 @@
- #include <linux/list.h>
- #include <linux/slab.h>
- #include <linux/pci.h>
-+#include <linux/acpi.h>
- #include <drm/drmP.h>
- #include <linux/firmware.h>
- #include <drm/amdgpu_drm.h>
-@@ -32,7 +33,6 @@
- #include "atom.h"
- #include "amdgpu_ucode.h"
- 
--
- struct amdgpu_cgs_device {
- 	struct cgs_device base;
- 	struct amdgpu_device *adev;
-@@ -736,6 +736,221 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
- 	return 0;
- }
- 
-+/** \brief evaluate acpi namespace object, handle or pathname must be valid
-+ *  \param cgs_device
-+ *  \param info input/output arguments for the control method
-+ *  \return status
-+ */
-+
-+#if defined(CONFIG_ACPI)
-+static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
-+				    struct cgs_acpi_method_info *info)
-+{
-+	CGS_FUNC_ADEV;
-+	acpi_handle handle;
-+	struct acpi_object_list input;
-+	struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
-+	union acpi_object *params = NULL;
-+	union acpi_object *obj = NULL;
-+	uint8_t name[5] = {'\0'};
-+	struct cgs_acpi_method_argument *argument = NULL;
-+	uint32_t i, count;
-+	acpi_status status;
-+	int result;
-+	uint32_t func_no = 0xFFFFFFFF;
-+
-+	handle = ACPI_HANDLE(&adev->pdev->dev);
-+	if (!handle)
-+		return -ENODEV;
-+
-+	memset(&input, 0, sizeof(struct acpi_object_list));
-+
-+	/* validate input info */
-+	if (info->size != sizeof(struct cgs_acpi_method_info))
-+		return -EINVAL;
-+
-+	input.count = info->input_count;
-+	if (info->input_count > 0) {
-+		if (info->pinput_argument == NULL)
-+			return -EINVAL;
-+			argument = info->pinput_argument;
-+			func_no = argument->value;
-+			for (i = 0; i < info->input_count; i++) {
-+				if (((argument->type == ACPI_TYPE_STRING) ||
-+					(argument->type == ACPI_TYPE_BUFFER))
-+					&& (argument->pointer == NULL))
-+					return -EINVAL;
-+				argument++;
-+			}
-+	}
-+
-+	if (info->output_count > 0) {
-+		if (info->poutput_argument == NULL)
-+			return -EINVAL;
-+		argument = info->poutput_argument;
-+		for (i = 0; i < info->output_count; i++) {
-+			if (((argument->type == ACPI_TYPE_STRING) ||
-+				(argument->type == ACPI_TYPE_BUFFER))
-+				&& (argument->pointer == NULL))
-+				return -EINVAL;
-+			argument++;
-+		}
-+	}
-+
-+	/* The path name passed to acpi_evaluate_object should be null terminated */
-+	if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
-+		strncpy(name, (char *)&(info->name), sizeof(uint32_t));
-+		name[4] = '\0';
-+	}
-+
-+	/* parse input parameters */
-+	if (input.count > 0) {
-+		input.pointer = params =
-+				kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
-+		if (params == NULL)
-+			return -EINVAL;
-+
-+		argument = info->pinput_argument;
-+
-+		for (i = 0; i < input.count; i++) {
-+			params->type = argument->type;
-+			switch (params->type) {
-+			case ACPI_TYPE_INTEGER:
-+				params->integer.value = argument->value;
-+				break;
-+			case ACPI_TYPE_STRING:
-+				params->string.length = argument->method_length;
-+				params->string.pointer = argument->pointer;
-+				break;
-+			case ACPI_TYPE_BUFFER:
-+				params->buffer.length = argument->method_length;
-+				params->buffer.pointer = argument->pointer;
-+				break;
-+			default:
-+				break;
-+			}
-+			params++;
-+			argument++;
-+		}
-+	}
-+
-+	/* parse output info */
-+	count = info->output_count;
-+	argument = info->poutput_argument;
-+
-+	/* evaluate the acpi method */
-+	status = acpi_evaluate_object(handle, name, &input, &output);
-+
-+	if (ACPI_FAILURE(status)) {
-+		result = -EIO;
-+		goto error;
-+	}
-+
-+	/* return the output info */
-+	obj = output.pointer;
-+
-+	if (count > 1) {
-+		if ((obj->type != ACPI_TYPE_PACKAGE) ||
-+			(obj->package.count != count)) {
-+			result = -EIO;
-+			goto error;
-+		}
-+		params = obj->package.elements;
-+	} else
-+		params = obj;
-+
-+	if (params == NULL) {
-+		result = -EIO;
-+		goto error;
-+	}
-+
-+	for (i = 0; i < count; i++) {
-+		if (argument->type != params->type) {
-+			result = -EIO;
-+			goto error;
-+		}
-+		switch (params->type) {
-+		case ACPI_TYPE_INTEGER:
-+			argument->value = params->integer.value;
-+			break;
-+		case ACPI_TYPE_STRING:
-+			if ((params->string.length != argument->data_length) ||
-+				(params->string.pointer == NULL)) {
-+				result = -EIO;
-+				goto error;
-+			}
-+			strncpy(argument->pointer,
-+				params->string.pointer,
-+				params->string.length);
-+			break;
-+		case ACPI_TYPE_BUFFER:
-+			if (params->buffer.pointer == NULL) {
-+				result = -EIO;
-+				goto error;
-+			}
-+			memcpy(argument->pointer,
-+				params->buffer.pointer,
-+				argument->data_length);
-+			break;
-+		default:
-+			break;
-+		}
-+		argument++;
-+		params++;
-+	}
-+
-+error:
-+	if (obj != NULL)
-+		kfree(obj);
-+	kfree((void *)input.pointer);
-+	return result;
-+}
-+#else
-+static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
-+				struct cgs_acpi_method_info *info)
-+{
-+	return -EIO;
-+}
-+#endif
-+
-+int amdgpu_cgs_call_acpi_method(void *cgs_device,
-+					uint32_t acpi_method,
-+					uint32_t acpi_function,
-+					void *pinput, void *poutput,
-+					uint32_t output_count,
-+					uint32_t input_size,
-+					uint32_t output_size)
-+{
-+	struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
-+	struct cgs_acpi_method_argument acpi_output = {0};
-+	struct cgs_acpi_method_info info = {0};
-+
-+	acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
-+	acpi_input[0].method_length = sizeof(uint32_t);
-+	acpi_input[0].data_length = sizeof(uint32_t);
-+	acpi_input[0].value = acpi_function;
-+
-+	acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
-+	acpi_input[1].method_length = CGS_ACPI_MAX_BUFFER_SIZE;
-+	acpi_input[1].data_length = input_size;
-+	acpi_input[1].pointer = pinput;
-+
-+	acpi_output.type = CGS_ACPI_TYPE_BUFFER;
-+	acpi_output.method_length = CGS_ACPI_MAX_BUFFER_SIZE;
-+	acpi_output.data_length = output_size;
-+	acpi_output.pointer = poutput;
-+
-+	info.size = sizeof(struct cgs_acpi_method_info);
-+	info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
-+	info.input_count = 2;
-+	info.name = acpi_method;
-+	info.pinput_argument = acpi_input;
-+	info.output_count = output_count;
-+	info.poutput_argument = &acpi_output;
-+
-+	return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
-+}
-+
- static const struct cgs_ops amdgpu_cgs_ops = {
- 	amdgpu_cgs_gpu_mem_info,
- 	amdgpu_cgs_gmap_kmem,
-@@ -768,7 +983,8 @@ static const struct cgs_ops amdgpu_cgs_ops = {
- 	amdgpu_cgs_set_camera_voltages,
- 	amdgpu_cgs_get_firmware_info,
- 	amdgpu_cgs_set_powergating_state,
--	amdgpu_cgs_set_clockgating_state
-+	amdgpu_cgs_set_clockgating_state,
-+	amdgpu_cgs_call_acpi_method,
- };
- 
- static const struct cgs_os_ops amdgpu_cgs_os_ops = {
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 992dcd8..8bf6ee5 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -129,6 +129,39 @@ struct cgs_firmware_info {
- 
- typedef unsigned long cgs_handle_t;
- 
-+#define CGS_ACPI_METHOD_ATCS          0x53435441
-+#define CGS_ACPI_METHOD_ATIF          0x46495441
-+#define CGS_ACPI_METHOD_ATPX          0x58505441
-+#define CGS_ACPI_FIELD_METHOD_NAME                      0x00000001
-+#define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT             0x00000002
-+#define CGS_ACPI_MAX_BUFFER_SIZE     256
-+#define CGS_ACPI_TYPE_ANY                      0x00
-+#define CGS_ACPI_TYPE_INTEGER               0x01
-+#define CGS_ACPI_TYPE_STRING                0x02
-+#define CGS_ACPI_TYPE_BUFFER                0x03
-+#define CGS_ACPI_TYPE_PACKAGE               0x04
-+
-+struct cgs_acpi_method_argument {
-+	uint32_t type;
-+	uint32_t method_length;
-+	uint32_t data_length;
-+	union{
-+		uint32_t value;
-+		void *pointer;
-+	};
-+};
-+
-+struct cgs_acpi_method_info {
-+	uint32_t size;
-+	uint32_t field;
-+	uint32_t input_count;
-+	uint32_t name;
-+	struct cgs_acpi_method_argument *pinput_argument;
-+	uint32_t output_count;
-+	struct cgs_acpi_method_argument *poutput_argument;
-+	uint32_t padding[9];
-+};
-+
- /**
-  * cgs_gpu_mem_info() - Return information about memory heaps
-  * @cgs_device: opaque device handle
-@@ -493,6 +526,13 @@ typedef int(*cgs_set_clockgating_state)(void *cgs_device,
- 				  enum amd_ip_block_type block_type,
- 				  enum amd_clockgating_state state);
- 
-+typedef int (*cgs_call_acpi_method)(void *cgs_device,
-+					uint32_t acpi_method,
-+					uint32_t acpi_function,
-+					void *pinput, void *poutput,
-+					uint32_t output_count,
-+					uint32_t input_size,
-+					uint32_t output_size);
- struct cgs_ops {
- 	/* memory management calls (similar to KFD interface) */
- 	cgs_gpu_mem_info_t gpu_mem_info;
-@@ -533,7 +573,8 @@ struct cgs_ops {
- 	/* cg pg interface*/
- 	cgs_set_powergating_state set_powergating_state;
- 	cgs_set_clockgating_state set_clockgating_state;
--	/* ACPI (TODO) */
-+	/* ACPI */
-+	cgs_call_acpi_method call_acpi_method;
- };
- 
- struct cgs_os_ops; /* To be define in OS-specific CGS header */
-@@ -620,5 +661,7 @@ struct cgs_device
- 	CGS_CALL(set_powergating_state, dev, block_type, state)
- #define cgs_set_clockgating_state(dev, block_type, state)	\
- 	CGS_CALL(set_clockgating_state, dev, block_type, state)
-+#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)	\
-+	CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
- 
- #endif /* _CGS_COMMON_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0038-drm-amdgpu-implement-cgs-interface-to-query-system-i.patch b/common/recipes-kernel/linux/files/0038-drm-amdgpu-implement-cgs-interface-to-query-system-i.patch
deleted file mode 100644
index 555a7398..00000000
--- a/common/recipes-kernel/linux/files/0038-drm-amdgpu-implement-cgs-interface-to-query-system-i.patch
+++ /dev/null
@@ -1,114 +0,0 @@
-From 2ba0b9d24785f41d0ab71d3d58c8cc14df71e24c Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Sep 2015 20:11:54 +0800
-Subject: [PATCH 0038/1110] drm/amdgpu: implement cgs interface to query system
- info
-
-Add a query to get the bus number and function of the
-device.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 23 +++++++++++++++++++++++
- drivers/gpu/drm/amd/include/cgs_common.h | 23 +++++++++++++++++++++++
- 2 files changed, 46 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index f901cdc..19f46d0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -736,6 +736,28 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
- 	return 0;
- }
- 
-+static int amdgpu_cgs_query_system_info(void *cgs_device,
-+				struct cgs_system_info *sys_info)
-+{
-+	CGS_FUNC_ADEV;
-+
-+	if (NULL == sys_info)
-+		return -ENODEV;
-+
-+	if (sizeof(struct cgs_system_info) != sys_info->size)
-+		return -ENODEV;
-+
-+	switch (sys_info->info_id) {
-+	case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
-+		sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
-+		break;
-+	default:
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
- /** \brief evaluate acpi namespace object, handle or pathname must be valid
-  *  \param cgs_device
-  *  \param info input/output arguments for the control method
-@@ -985,6 +1007,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
- 	amdgpu_cgs_set_powergating_state,
- 	amdgpu_cgs_set_clockgating_state,
- 	amdgpu_cgs_call_acpi_method,
-+	amdgpu_cgs_query_system_info,
- };
- 
- static const struct cgs_os_ops amdgpu_cgs_os_ops = {
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 8bf6ee5..5ea8db0 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -105,6 +105,21 @@ enum cgs_ucode_id {
- 	CGS_UCODE_ID_MAXIMUM,
- };
- 
-+enum cgs_system_info_id {
-+	CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
-+	CGS_SYSTEM_INFO_ID_MAXIMUM,
-+};
-+
-+struct cgs_system_info {
-+	uint64_t       size;
-+	uint64_t       info_id;
-+	union {
-+		void           *ptr;
-+		uint64_t        value;
-+	};
-+	uint64_t               padding[13];
-+};
-+
- /**
-  * struct cgs_clock_limits - Clock limits
-  *
-@@ -533,6 +548,10 @@ typedef int (*cgs_call_acpi_method)(void *cgs_device,
- 					uint32_t output_count,
- 					uint32_t input_size,
- 					uint32_t output_size);
-+
-+typedef int (*cgs_query_system_info)(void *cgs_device,
-+				struct cgs_system_info *sys_info);
-+
- struct cgs_ops {
- 	/* memory management calls (similar to KFD interface) */
- 	cgs_gpu_mem_info_t gpu_mem_info;
-@@ -575,6 +594,8 @@ struct cgs_ops {
- 	cgs_set_clockgating_state set_clockgating_state;
- 	/* ACPI */
- 	cgs_call_acpi_method call_acpi_method;
-+	/* get system info */
-+	cgs_query_system_info query_system_info;
- };
- 
- struct cgs_os_ops; /* To be define in OS-specific CGS header */
-@@ -663,5 +684,7 @@ struct cgs_device
- 	CGS_CALL(set_clockgating_state, dev, block_type, state)
- #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)	\
- 	CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
-+#define cgs_query_system_info(dev, sys_info)	\
-+	CGS_CALL(query_system_info, dev, sys_info)
- 
- #endif /* _CGS_COMMON_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0039-drm-amdgpu-add-new-cgs-interface-to-get-display-info.patch b/common/recipes-kernel/linux/files/0039-drm-amdgpu-add-new-cgs-interface-to-get-display-info.patch
deleted file mode 100644
index 5420409a..00000000
--- a/common/recipes-kernel/linux/files/0039-drm-amdgpu-add-new-cgs-interface-to-get-display-info.patch
+++ /dev/null
@@ -1,133 +0,0 @@
-From 364446ff0da9a0a35b44e193f54f88f34431dcc8 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 17 Sep 2015 16:34:14 +0800
-Subject: [PATCH 0039/1110] drm/amdgpu: add new cgs interface to get display
- info (v2)
-
-Add new CGS interfaces to query display info across modules.
-This is nedded by the powerplay module for synchronizing with
-the display module.
-
-v2: (agd): fold in refresh rate fix, rebase
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 40 ++++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/include/cgs_common.h | 20 ++++++++++++++++
- 2 files changed, 60 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 19f46d0..8f758ea 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -758,6 +758,45 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
- 	return 0;
- }
- 
-+static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
-+					  struct cgs_display_info *info)
-+{
-+	CGS_FUNC_ADEV;
-+	struct amdgpu_crtc *amdgpu_crtc;
-+	struct drm_device *ddev = adev->ddev;
-+	struct drm_crtc *crtc;
-+	uint32_t line_time_us, vblank_lines;
-+
-+	if (info == NULL)
-+		return -EINVAL;
-+
-+	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
-+		list_for_each_entry(crtc,
-+				&ddev->mode_config.crtc_list, head) {
-+			amdgpu_crtc = to_amdgpu_crtc(crtc);
-+			if (crtc->enabled) {
-+				info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
-+				info->display_count++;
-+			}
-+			if (info->mode_info != NULL &&
-+				crtc->enabled && amdgpu_crtc->enabled &&
-+				amdgpu_crtc->hw_mode.clock) {
-+				line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
-+							amdgpu_crtc->hw_mode.clock;
-+				vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
-+							amdgpu_crtc->hw_mode.crtc_vdisplay +
-+							(amdgpu_crtc->v_border * 2);
-+				info->mode_info->vblank_time_us = vblank_lines * line_time_us;
-+				info->mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
-+				info->mode_info->ref_clock = adev->clock.spll.reference_freq;
-+				info->mode_info++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
- /** \brief evaluate acpi namespace object, handle or pathname must be valid
-  *  \param cgs_device
-  *  \param info input/output arguments for the control method
-@@ -1006,6 +1045,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
- 	amdgpu_cgs_get_firmware_info,
- 	amdgpu_cgs_set_powergating_state,
- 	amdgpu_cgs_set_clockgating_state,
-+	amdgpu_cgs_get_active_displays_info,
- 	amdgpu_cgs_call_acpi_method,
- 	amdgpu_cgs_query_system_info,
- };
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 5ea8db0..2bbffd1 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -142,6 +142,18 @@ struct cgs_firmware_info {
- 	void			*kptr;
- };
- 
-+struct cgs_mode_info {
-+	uint32_t		refresh_rate;
-+	uint32_t		ref_clock;
-+	uint32_t		vblank_time_us;
-+};
-+
-+struct cgs_display_info {
-+	uint32_t		display_count;
-+	uint32_t		active_display_mask;
-+	struct cgs_mode_info *mode_info;
-+};
-+
- typedef unsigned long cgs_handle_t;
- 
- #define CGS_ACPI_METHOD_ATCS          0x53435441
-@@ -541,6 +553,10 @@ typedef int(*cgs_set_clockgating_state)(void *cgs_device,
- 				  enum amd_ip_block_type block_type,
- 				  enum amd_clockgating_state state);
- 
-+typedef int(*cgs_get_active_displays_info)(
-+					void *cgs_device,
-+					struct cgs_display_info *info);
-+
- typedef int (*cgs_call_acpi_method)(void *cgs_device,
- 					uint32_t acpi_method,
- 					uint32_t acpi_function,
-@@ -592,6 +608,8 @@ struct cgs_ops {
- 	/* cg pg interface*/
- 	cgs_set_powergating_state set_powergating_state;
- 	cgs_set_clockgating_state set_clockgating_state;
-+	/* display manager */
-+	cgs_get_active_displays_info get_active_displays_info;
- 	/* ACPI */
- 	cgs_call_acpi_method call_acpi_method;
- 	/* get system info */
-@@ -682,6 +700,8 @@ struct cgs_device
- 	CGS_CALL(set_powergating_state, dev, block_type, state)
- #define cgs_set_clockgating_state(dev, block_type, state)	\
- 	CGS_CALL(set_clockgating_state, dev, block_type, state)
-+#define cgs_get_active_displays_info(dev, info)	\
-+	CGS_CALL(get_active_displays_info, dev, info)
- #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)	\
- 	CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
- #define cgs_query_system_info(dev, sys_info)	\
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0040-drm-amd-powerplay-add-basic-powerplay-framework.patch b/common/recipes-kernel/linux/files/0040-drm-amd-powerplay-add-basic-powerplay-framework.patch
deleted file mode 100644
index 405f8018..00000000
--- a/common/recipes-kernel/linux/files/0040-drm-amd-powerplay-add-basic-powerplay-framework.patch
+++ /dev/null
@@ -1,942 +0,0 @@
-From eb6791939b3a50d7c764e43951da40cb5f8ead11 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 2 Dec 2015 17:46:21 -0500
-Subject: [PATCH 0040/1110] drm/amd/powerplay: add basic powerplay framework
-
-amdgpu_pp_ip_funcs is introduced to handle the two code paths,
-the legacy one and the new powerplay implementation.
-
-CONFIG_DRM_AMD_POWERPLAY kernel configuration option is
-introduced for the powerplay component.
-
-v4: squash in fixes
-v3: register debugfs file when powerplay module enable
-v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile               |  12 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu.h               |   5 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c           |   1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c     | 280 ++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h     |  33 +++
- drivers/gpu/drm/amd/amdgpu/cik.c                  |  11 +-
- drivers/gpu/drm/amd/amdgpu/vi.c                   |   7 +-
- drivers/gpu/drm/amd/powerplay/Kconfig             |   6 +
- drivers/gpu/drm/amd/powerplay/Makefile            |  15 ++
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 194 +++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 162 +++++++++++++
- 11 files changed, 717 insertions(+), 9 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
- create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/Kconfig
- create mode 100644 drivers/gpu/drm/amd/powerplay/Makefile
- create mode 100644 drivers/gpu/drm/amd/powerplay/amd_powerplay.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index 178fa15..4c856fe 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -7,7 +7,8 @@ FULL_AMD_PATH=$(src)/..
- ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
- 	-I$(FULL_AMD_PATH)/include \
- 	-I$(FULL_AMD_PATH)/amdgpu \
--	-I$(FULL_AMD_PATH)/scheduler
-+	-I$(FULL_AMD_PATH)/scheduler \
-+	-I$(FULL_AMD_PATH)/powerplay/inc
- 
- amdgpu-y := amdgpu_drv.o
- 
-@@ -47,6 +48,7 @@ amdgpu-y += \
- # add SMC block
- amdgpu-y += \
- 	amdgpu_dpm.o \
-+	amdgpu_powerplay.o \
- 	cz_smc.o cz_dpm.o \
- 	tonga_smc.o tonga_dpm.o \
- 	fiji_smc.o fiji_dpm.o \
-@@ -97,6 +99,14 @@ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
- amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
- amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
- 
-+ifneq ($(CONFIG_DRM_AMD_POWERPLAY),)
-+
-+include drivers/gpu/drm/amd/powerplay/Makefile
-+
-+amdgpu-y += $(AMD_POWERPLAY_FILES)
-+
-+endif
-+
- obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
- 
- CFLAGS_amdgpu_trace_points.o := -I$(src)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a10f421..9387cce 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -52,6 +52,7 @@
- #include "amdgpu_irq.h"
- #include "amdgpu_ucode.h"
- #include "amdgpu_gds.h"
-+#include "amd_powerplay.h"
- 
- #include "gpu_scheduler.h"
- 
-@@ -85,6 +86,7 @@ extern int amdgpu_enable_scheduler;
- extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
- extern int amdgpu_enable_semaphores;
-+extern int amdgpu_powerplay;
- 
- #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
- #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
-@@ -2045,6 +2047,9 @@ struct amdgpu_device {
- 	/* interrupts */
- 	struct amdgpu_irq		irq;
- 
-+	/* powerplay */
-+	struct amd_powerplay		powerplay;
-+
- 	/* dpm */
- 	struct amdgpu_pm		pm;
- 	u32				cg_flags;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 659300c..a318356 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -82,6 +82,7 @@ int amdgpu_enable_scheduler = 1;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_enable_semaphores = 0;
-+int amdgpu_powerplay = 0;
- 
- MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
- module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-new file mode 100644
-index 0000000..5dd2a4c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -0,0 +1,280 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "atom.h"
-+#include "amdgpu.h"
-+#include "amd_shared.h"
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include "amdgpu_pm.h"
-+#include <drm/amdgpu_drm.h>
-+#include "amdgpu_powerplay.h"
-+#include "cik_dpm.h"
-+#include "vi_dpm.h"
-+
-+static int amdgpu_powerplay_init(struct amdgpu_device *adev)
-+{
-+	int ret = 0;
-+	struct amd_powerplay *amd_pp;
-+
-+	amd_pp = &(adev->powerplay);
-+
-+	if (amdgpu_powerplay) {
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+		struct amd_pp_init *pp_init;
-+
-+		pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
-+
-+		if (pp_init == NULL)
-+			return -ENOMEM;
-+
-+		pp_init->chip_family = adev->family;
-+		pp_init->chip_id = adev->asic_type;
-+		pp_init->device = amdgpu_cgs_create_device(adev);
-+
-+		ret = amd_powerplay_init(pp_init, amd_pp);
-+		kfree(pp_init);
-+#endif
-+	} else {
-+		amd_pp->pp_handle = (void *)adev;
-+
-+		switch (adev->asic_type) {
-+#ifdef CONFIG_DRM_AMDGPU_CIK
-+		case CHIP_BONAIRE:
-+		case CHIP_HAWAII:
-+			amd_pp->ip_funcs = &ci_dpm_ip_funcs;
-+			break;
-+		case CHIP_KABINI:
-+		case CHIP_MULLINS:
-+		case CHIP_KAVERI:
-+			amd_pp->ip_funcs = &kv_dpm_ip_funcs;
-+			break;
-+#endif
-+		case CHIP_TOPAZ:
-+			amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
-+			break;
-+		case CHIP_TONGA:
-+			amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
-+			break;
-+		case CHIP_CARRIZO:
-+			amd_pp->ip_funcs = &cz_dpm_ip_funcs;
-+			break;
-+		default:
-+			ret = -EINVAL;
-+			break;
-+		}
-+	}
-+	return ret;
-+}
-+
-+static int amdgpu_pp_early_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int ret = 0;
-+
-+	ret = amdgpu_powerplay_init(adev);
-+	if (ret)
-+		return ret;
-+
-+	if (adev->powerplay.ip_funcs->early_init)
-+		ret = adev->powerplay.ip_funcs->early_init(
-+					adev->powerplay.pp_handle);
-+	return ret;
-+}
-+
-+static int amdgpu_pp_sw_init(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->sw_init)
-+		ret = adev->powerplay.ip_funcs->sw_init(
-+					adev->powerplay.pp_handle);
-+
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (amdgpu_powerplay) {
-+		adev->pm.dpm_enabled = true;
-+		amdgpu_pm_sysfs_init(adev);
-+	}
-+#endif
-+
-+	return ret;
-+}
-+
-+static int amdgpu_pp_sw_fini(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->sw_fini)
-+		ret = adev->powerplay.ip_funcs->sw_fini(
-+					adev->powerplay.pp_handle);
-+	if (ret)
-+		return ret;
-+
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (amdgpu_powerplay) {
-+		amdgpu_pm_sysfs_fini(adev);
-+		amd_powerplay_fini(adev->powerplay.pp_handle);
-+	}
-+#endif
-+
-+	return ret;
-+}
-+
-+static int amdgpu_pp_hw_init(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (amdgpu_powerplay && adev->firmware.smu_load)
-+		amdgpu_ucode_init_bo(adev);
-+
-+	if (adev->powerplay.ip_funcs->hw_init)
-+		ret = adev->powerplay.ip_funcs->hw_init(
-+					adev->powerplay.pp_handle);
-+
-+	return ret;
-+}
-+
-+static int amdgpu_pp_hw_fini(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->hw_fini)
-+		ret = adev->powerplay.ip_funcs->hw_fini(
-+					adev->powerplay.pp_handle);
-+
-+	if (amdgpu_powerplay && adev->firmware.smu_load)
-+		amdgpu_ucode_fini_bo(adev);
-+
-+	return ret;
-+}
-+
-+static int amdgpu_pp_suspend(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->suspend)
-+		ret = adev->powerplay.ip_funcs->suspend(
-+					 adev->powerplay.pp_handle);
-+	return ret;
-+}
-+
-+static int amdgpu_pp_resume(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->resume)
-+		ret = adev->powerplay.ip_funcs->resume(
-+					adev->powerplay.pp_handle);
-+	return ret;
-+}
-+
-+static int amdgpu_pp_set_clockgating_state(void *handle,
-+					enum amd_clockgating_state state)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->set_clockgating_state)
-+		ret = adev->powerplay.ip_funcs->set_clockgating_state(
-+				adev->powerplay.pp_handle, state);
-+	return ret;
-+}
-+
-+static int amdgpu_pp_set_powergating_state(void *handle,
-+					enum amd_powergating_state state)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->set_powergating_state)
-+		ret = adev->powerplay.ip_funcs->set_powergating_state(
-+				 adev->powerplay.pp_handle, state);
-+	return ret;
-+}
-+
-+
-+static bool amdgpu_pp_is_idle(void *handle)
-+{
-+	bool ret = true;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->is_idle)
-+		ret = adev->powerplay.ip_funcs->is_idle(
-+					adev->powerplay.pp_handle);
-+	return ret;
-+}
-+
-+static int amdgpu_pp_wait_for_idle(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->wait_for_idle)
-+		ret = adev->powerplay.ip_funcs->wait_for_idle(
-+					adev->powerplay.pp_handle);
-+	return ret;
-+}
-+
-+static int amdgpu_pp_soft_reset(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->soft_reset)
-+		ret = adev->powerplay.ip_funcs->soft_reset(
-+					adev->powerplay.pp_handle);
-+	return ret;
-+}
-+
-+static void amdgpu_pp_print_status(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->print_status)
-+		adev->powerplay.ip_funcs->print_status(
-+					adev->powerplay.pp_handle);
-+}
-+
-+const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
-+	.early_init = amdgpu_pp_early_init,
-+	.late_init = NULL,
-+	.sw_init = amdgpu_pp_sw_init,
-+	.sw_fini = amdgpu_pp_sw_fini,
-+	.hw_init = amdgpu_pp_hw_init,
-+	.hw_fini = amdgpu_pp_hw_fini,
-+	.suspend = amdgpu_pp_suspend,
-+	.resume = amdgpu_pp_resume,
-+	.is_idle = amdgpu_pp_is_idle,
-+	.wait_for_idle = amdgpu_pp_wait_for_idle,
-+	.soft_reset = amdgpu_pp_soft_reset,
-+	.print_status = amdgpu_pp_print_status,
-+	.set_clockgating_state = amdgpu_pp_set_clockgating_state,
-+	.set_powergating_state = amdgpu_pp_set_powergating_state,
-+};
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
-new file mode 100644
-index 0000000..da5cf47
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h
-@@ -0,0 +1,33 @@
-+/*
-+ *  Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __AMDGPU_POPWERPLAY_H__
-+#define __AMDGPU_POPWERPLAY_H__
-+
-+#include "amd_shared.h"
-+
-+extern const struct amd_ip_funcs amdgpu_pp_ip_funcs;
-+
-+#endif /* __AMDSOC_DM_H__ */
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 61689f0..c7c298b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -65,6 +65,7 @@
- #include "oss/oss_2_0_sh_mask.h"
- 
- #include "amdgpu_amdkfd.h"
-+#include "amdgpu_powerplay.h"
- 
- /*
-  * Indirect registers accessor
-@@ -1953,7 +1954,7 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
- 		.major = 7,
- 		.minor = 0,
- 		.rev = 0,
--		.funcs = &ci_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-@@ -2021,7 +2022,7 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
- 		.major = 7,
- 		.minor = 0,
- 		.rev = 0,
--		.funcs = &ci_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-@@ -2089,7 +2090,7 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
- 		.major = 7,
- 		.minor = 0,
- 		.rev = 0,
--		.funcs = &kv_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-@@ -2157,7 +2158,7 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
- 		.major = 7,
- 		.minor = 0,
- 		.rev = 0,
--		.funcs = &kv_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-@@ -2225,7 +2226,7 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
- 		.major = 7,
- 		.minor = 0,
- 		.rev = 0,
--		.funcs = &kv_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 2f1c118..9e8a220 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -72,6 +72,7 @@
- #include "uvd_v5_0.h"
- #include "uvd_v6_0.h"
- #include "vce_v3_0.h"
-+#include "amdgpu_powerplay.h"
- 
- /*
-  * Indirect registers accessor
-@@ -1131,7 +1132,7 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
- 		.major = 7,
- 		.minor = 1,
- 		.rev = 0,
--		.funcs = &iceland_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_GFX,
-@@ -1178,7 +1179,7 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
- 		.major = 7,
- 		.minor = 1,
- 		.rev = 0,
--		.funcs = &tonga_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-@@ -1314,7 +1315,7 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] =
- 		.major = 8,
- 		.minor = 0,
- 		.rev = 0,
--		.funcs = &cz_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
-diff --git a/drivers/gpu/drm/amd/powerplay/Kconfig b/drivers/gpu/drm/amd/powerplay/Kconfig
-new file mode 100644
-index 0000000..af38033
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/Kconfig
-@@ -0,0 +1,6 @@
-+config DRM_AMD_POWERPLAY
-+	bool  "Enable AMD powerplay component"
-+	depends on DRM_AMDGPU
-+	default n
-+	help
-+	  select this option will enable AMD powerplay component.
-diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
-new file mode 100644
-index 0000000..e7428a1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/Makefile
-@@ -0,0 +1,15 @@
-+
-+subdir-ccflags-y += -Iinclude/drm  \
-+		-Idrivers/gpu/drm/amd/powerplay/inc/  \
-+		-Idrivers/gpu/drm/amd/include/asic_reg  \
-+		-Idrivers/gpu/drm/amd/include
-+
-+AMD_PP_PATH = ../powerplay
-+
-+include $(AMD_POWERPLAY)
-+
-+POWER_MGR = amd_powerplay.o
-+
-+AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
-+
-+AMD_POWERPLAY_FILES += $(AMD_PP_POWER)
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-new file mode 100644
-index 0000000..39ffc5d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -0,0 +1,194 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/gfp.h>
-+#include "amd_shared.h"
-+#include "amd_powerplay.h"
-+
-+static int pp_early_init(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_sw_init(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_sw_fini(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_hw_init(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_hw_fini(void *handle)
-+{
-+	return 0;
-+}
-+
-+static bool pp_is_idle(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_wait_for_idle(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_sw_reset(void *handle)
-+{
-+	return 0;
-+}
-+
-+static void pp_print_status(void *handle)
-+{
-+
-+}
-+
-+static int pp_set_clockgating_state(void *handle,
-+				    enum amd_clockgating_state state)
-+{
-+	return 0;
-+}
-+
-+static int pp_set_powergating_state(void *handle,
-+				    enum amd_powergating_state state)
-+{
-+	return 0;
-+}
-+
-+static int pp_suspend(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_resume(void *handle)
-+{
-+	return 0;
-+}
-+
-+const struct amd_ip_funcs pp_ip_funcs = {
-+	.early_init = pp_early_init,
-+	.late_init = NULL,
-+	.sw_init = pp_sw_init,
-+	.sw_fini = pp_sw_fini,
-+	.hw_init = pp_hw_init,
-+	.hw_fini = pp_hw_fini,
-+	.suspend = pp_suspend,
-+	.resume = pp_resume,
-+	.is_idle = pp_is_idle,
-+	.wait_for_idle = pp_wait_for_idle,
-+	.soft_reset = pp_sw_reset,
-+	.print_status = pp_print_status,
-+	.set_clockgating_state = pp_set_clockgating_state,
-+	.set_powergating_state = pp_set_powergating_state,
-+};
-+
-+static int pp_dpm_load_fw(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_dpm_fw_loading_complete(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int pp_dpm_force_performance_level(void *handle,
-+					enum amd_dpm_forced_level level)
-+{
-+	return 0;
-+}
-+static enum amd_dpm_forced_level pp_dpm_get_performance_level(
-+								void *handle)
-+{
-+	return 0;
-+}
-+static int pp_dpm_get_sclk(void *handle, bool low)
-+{
-+	return 0;
-+}
-+static int pp_dpm_get_mclk(void *handle, bool low)
-+{
-+	return 0;
-+}
-+static int pp_dpm_powergate_vce(void *handle, bool gate)
-+{
-+	return 0;
-+}
-+static int pp_dpm_powergate_uvd(void *handle, bool gate)
-+{
-+	return 0;
-+}
-+
-+int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
-+{
-+	return 0;
-+}
-+enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
-+{
-+	return 0;
-+}
-+static void
-+pp_debugfs_print_current_performance_level(void *handle,
-+					       struct seq_file *m)
-+{
-+	return;
-+}
-+const struct amd_powerplay_funcs pp_dpm_funcs = {
-+	.get_temperature = NULL,
-+	.load_firmware = pp_dpm_load_fw,
-+	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
-+	.force_performance_level = pp_dpm_force_performance_level,
-+	.get_performance_level = pp_dpm_get_performance_level,
-+	.get_current_power_state = pp_dpm_get_current_power_state,
-+	.get_sclk = pp_dpm_get_sclk,
-+	.get_mclk = pp_dpm_get_mclk,
-+	.powergate_vce = pp_dpm_powergate_vce,
-+	.powergate_uvd = pp_dpm_powergate_uvd,
-+	.dispatch_tasks = pp_dpm_dispatch_tasks,
-+	.print_current_performance_level = pp_debugfs_print_current_performance_level,
-+};
-+
-+int amd_powerplay_init(struct amd_pp_init *pp_init,
-+		       struct amd_powerplay *amd_pp)
-+{
-+	if (pp_init == NULL || amd_pp == NULL)
-+		return -EINVAL;
-+
-+	amd_pp->ip_funcs = &pp_ip_funcs;
-+	amd_pp->pp_funcs = &pp_dpm_funcs;
-+
-+	return 0;
-+}
-+
-+int amd_powerplay_fini(void *handle)
-+{
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-new file mode 100644
-index 0000000..09d9d5a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -0,0 +1,162 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _AMD_POWERPLAY_H_
-+#define _AMD_POWERPLAY_H_
-+
-+#include <linux/seq_file.h>
-+#include <linux/types.h>
-+#include "amd_shared.h"
-+#include "cgs_common.h"
-+
-+
-+enum amd_pp_event {
-+	AMD_PP_EVENT_INITIALIZE = 0,
-+	AMD_PP_EVENT_UNINITIALIZE,
-+	AMD_PP_EVENT_POWER_SOURCE_CHANGE,
-+	AMD_PP_EVENT_SUSPEND,
-+	AMD_PP_EVENT_RESUME,
-+	AMD_PP_EVENT_ENTER_REST_STATE,
-+	AMD_PP_EVENT_EXIT_REST_STATE,
-+	AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
-+	AMD_PP_EVENT_THERMAL_NOTIFICATION,
-+	AMD_PP_EVENT_VBIOS_NOTIFICATION,
-+	AMD_PP_EVENT_ENTER_THERMAL_STATE,
-+	AMD_PP_EVENT_EXIT_THERMAL_STATE,
-+	AMD_PP_EVENT_ENTER_FORCED_STATE,
-+	AMD_PP_EVENT_EXIT_FORCED_STATE,
-+	AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
-+	AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
-+	AMD_PP_EVENT_ENTER_SCREEN_SAVER,
-+	AMD_PP_EVENT_EXIT_SCREEN_SAVER,
-+	AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
-+	AMD_PP_EVENT_VPU_RECOVERY_END,
-+	AMD_PP_EVENT_ENABLE_POWER_PLAY,
-+	AMD_PP_EVENT_DISABLE_POWER_PLAY,
-+	AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
-+	AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
-+	AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
-+	AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
-+	AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
-+	AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
-+	AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
-+	AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
-+	AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
-+	AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
-+	AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
-+	AMD_PP_EVENT_ENABLE_CGPG,
-+	AMD_PP_EVENT_DISABLE_CGPG,
-+	AMD_PP_EVENT_ENTER_TEXT_MODE,
-+	AMD_PP_EVENT_EXIT_TEXT_MODE,
-+	AMD_PP_EVENT_VIDEO_START,
-+	AMD_PP_EVENT_VIDEO_STOP,
-+	AMD_PP_EVENT_ENABLE_USER_STATE,
-+	AMD_PP_EVENT_DISABLE_USER_STATE,
-+	AMD_PP_EVENT_READJUST_POWER_STATE,
-+	AMD_PP_EVENT_START_INACTIVITY,
-+	AMD_PP_EVENT_STOP_INACTIVITY,
-+	AMD_PP_EVENT_LINKED_ADAPTERS_READY,
-+	AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
-+	AMD_PP_EVENT_COMPLETE_INIT,
-+	AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
-+	AMD_PP_EVENT_BACKLIGHT_CHANGED,
-+	AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
-+	AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
-+	AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
-+	AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
-+	AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
-+	AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
-+	AMD_PP_EVENT_SCREEN_ON,
-+	AMD_PP_EVENT_SCREEN_OFF,
-+	AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
-+	AMD_PP_EVENT_ENTER_ULP_STATE,
-+	AMD_PP_EVENT_EXIT_ULP_STATE,
-+	AMD_PP_EVENT_REGISTER_IP_STATE,
-+	AMD_PP_EVENT_UNREGISTER_IP_STATE,
-+	AMD_PP_EVENT_ENTER_MGPU_MODE,
-+	AMD_PP_EVENT_EXIT_MGPU_MODE,
-+	AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
-+	AMD_PP_EVENT_PRE_SUSPEND,
-+	AMD_PP_EVENT_PRE_RESUME,
-+	AMD_PP_EVENT_ENTER_BACOS,
-+	AMD_PP_EVENT_EXIT_BACOS,
-+	AMD_PP_EVENT_RESUME_BACO,
-+	AMD_PP_EVENT_RESET_BACO,
-+	AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
-+	AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
-+	AMD_PP_EVENT_START_COMPUTE_APPLICATION,
-+	AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
-+	AMD_PP_EVENT_REDUCE_POWER_LIMIT,
-+	AMD_PP_EVENT_ENTER_FRAME_LOCK,
-+	AMD_PP_EVENT_EXIT_FRAME_LOOCK,
-+	AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
-+	AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
-+	AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
-+	AMD_PP_EVENT_HIBERNATE,
-+	AMD_PP_EVENT_CONNECTED_STANDBY,
-+	AMD_PP_EVENT_ENTER_SELF_REFRESH,
-+	AMD_PP_EVENT_EXIT_SELF_REFRESH,
-+	AMD_PP_EVENT_START_AVFS_BTC,
-+	AMD_PP_EVENT_MAX
-+};
-+
-+enum amd_dpm_forced_level {
-+	AMD_DPM_FORCED_LEVEL_AUTO = 0,
-+	AMD_DPM_FORCED_LEVEL_LOW = 1,
-+	AMD_DPM_FORCED_LEVEL_HIGH = 2,
-+};
-+
-+struct amd_pp_init {
-+	struct cgs_device *device;
-+	uint32_t chip_family;
-+	uint32_t chip_id;
-+	uint32_t rev_id;
-+};
-+
-+struct amd_powerplay_funcs {
-+	int (*get_temperature)(void *handle);
-+	int (*load_firmware)(void *handle);
-+	int (*wait_for_fw_loading_complete)(void *handle);
-+	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
-+	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
-+	enum amd_pm_state_type (*get_current_power_state)(void *handle);
-+	int (*get_sclk)(void *handle, bool low);
-+	int (*get_mclk)(void *handle, bool low);
-+	int (*powergate_vce)(void *handle, bool gate);
-+	int (*powergate_uvd)(void *handle, bool gate);
-+	int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
-+				   void *input, void *output);
-+	void (*print_current_performance_level)(void *handle,
-+						      struct seq_file *m);
-+};
-+
-+struct amd_powerplay {
-+	void *pp_handle;
-+	const struct amd_ip_funcs *ip_funcs;
-+	const struct amd_powerplay_funcs *pp_funcs;
-+};
-+
-+int amd_powerplay_init(struct amd_pp_init *pp_init,
-+		       struct amd_powerplay *amd_pp);
-+int amd_powerplay_fini(void *handle);
-+
-+#endif /* _AMD_POWERPLAY_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0041-drm-amdgpu-disable-legacy-path-of-firmware-check-if-.patch b/common/recipes-kernel/linux/files/0041-drm-amdgpu-disable-legacy-path-of-firmware-check-if-.patch
deleted file mode 100644
index 4c962f69..00000000
--- a/common/recipes-kernel/linux/files/0041-drm-amdgpu-disable-legacy-path-of-firmware-check-if-.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From 172846d2dea4553830034376b03aa72fea667415 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 6 Nov 2015 20:33:24 -0500
-Subject: [PATCH 0041/1110] drm/amdgpu: disable legacy path of firmware check
- if powerplay is enabled
-
-Powerplay will use a different interface once it's integrated.  These
-legacy pathes will be removed once powerplay is enabled by default.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 80 ++++++++++++++++++----------------
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 24 +++++-----
- 2 files changed, 55 insertions(+), 49 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 16420b9..23fde5b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2902,16 +2902,18 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
- 
- 	gfx_v8_0_rlc_reset(adev);
- 
--	if (!adev->firmware.smu_load) {
--		/* legacy rlc firmware loading */
--		r = gfx_v8_0_rlc_load_microcode(adev);
--		if (r)
--			return r;
--	} else {
--		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--						AMDGPU_UCODE_ID_RLC_G);
--		if (r)
--			return -EINVAL;
-+	if (!amdgpu_powerplay) {
-+		if (!adev->firmware.smu_load) {
-+			/* legacy rlc firmware loading */
-+			r = gfx_v8_0_rlc_load_microcode(adev);
-+			if (r)
-+				return r;
-+		} else {
-+			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+							AMDGPU_UCODE_ID_RLC_G);
-+			if (r)
-+				return -EINVAL;
-+		}
- 	}
- 
- 	gfx_v8_0_rlc_start(adev);
-@@ -3802,35 +3804,37 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
- 	if (!(adev->flags & AMD_IS_APU))
- 		gfx_v8_0_enable_gui_idle_interrupt(adev, false);
- 
--	if (!adev->firmware.smu_load) {
--		/* legacy firmware loading */
--		r = gfx_v8_0_cp_gfx_load_microcode(adev);
--		if (r)
--			return r;
--
--		r = gfx_v8_0_cp_compute_load_microcode(adev);
--		if (r)
--			return r;
--	} else {
--		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--						AMDGPU_UCODE_ID_CP_CE);
--		if (r)
--			return -EINVAL;
--
--		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--						AMDGPU_UCODE_ID_CP_PFP);
--		if (r)
--			return -EINVAL;
--
--		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--						AMDGPU_UCODE_ID_CP_ME);
--		if (r)
--			return -EINVAL;
-+	if (!amdgpu_powerplay) {
-+		if (!adev->firmware.smu_load) {
-+			/* legacy firmware loading */
-+			r = gfx_v8_0_cp_gfx_load_microcode(adev);
-+			if (r)
-+				return r;
- 
--		r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--						AMDGPU_UCODE_ID_CP_MEC1);
--		if (r)
--			return -EINVAL;
-+			r = gfx_v8_0_cp_compute_load_microcode(adev);
-+			if (r)
-+				return r;
-+		} else {
-+			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+							AMDGPU_UCODE_ID_CP_CE);
-+			if (r)
-+				return -EINVAL;
-+
-+			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+							AMDGPU_UCODE_ID_CP_PFP);
-+			if (r)
-+				return -EINVAL;
-+
-+			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+							AMDGPU_UCODE_ID_CP_ME);
-+			if (r)
-+				return -EINVAL;
-+
-+			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+							AMDGPU_UCODE_ID_CP_MEC1);
-+			if (r)
-+				return -EINVAL;
-+		}
- 	}
- 
- 	r = gfx_v8_0_cp_gfx_resume(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 7253132..8091c1c 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -727,18 +727,20 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
- {
- 	int r, i;
- 
--	if (!adev->firmware.smu_load) {
--		r = sdma_v3_0_load_microcode(adev);
--		if (r)
--			return r;
--	} else {
--		for (i = 0; i < adev->sdma.num_instances; i++) {
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--									 (i == 0) ?
--									 AMDGPU_UCODE_ID_SDMA0 :
--									 AMDGPU_UCODE_ID_SDMA1);
-+	if (!amdgpu_powerplay) {
-+		if (!adev->firmware.smu_load) {
-+			r = sdma_v3_0_load_microcode(adev);
- 			if (r)
--				return -EINVAL;
-+				return r;
-+		} else {
-+			for (i = 0; i < adev->sdma.num_instances; i++) {
-+				r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+										 (i == 0) ?
-+										 AMDGPU_UCODE_ID_SDMA0 :
-+										 AMDGPU_UCODE_ID_SDMA1);
-+				if (r)
-+					return -EINVAL;
-+			}
- 		}
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0042-drm-amdgpu-export-amd_powerplay_func-to-amdgpu-and-o.patch b/common/recipes-kernel/linux/files/0042-drm-amdgpu-export-amd_powerplay_func-to-amdgpu-and-o.patch
deleted file mode 100644
index c8b8c2a5..00000000
--- a/common/recipes-kernel/linux/files/0042-drm-amdgpu-export-amd_powerplay_func-to-amdgpu-and-o.patch
+++ /dev/null
@@ -1,441 +0,0 @@
-From d7545b2f834039696946552cb68ed0bcd08a6918 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 10 Nov 2015 18:25:24 -0500
-Subject: [PATCH 0042/1110] drm/amdgpu: export amd_powerplay_func to amdgpu and
- other ip block
-
-Update amdgpu to deal with the new powerplay module properly.
-
-v2: squash in fixes
-v3: squash in Rex's power state reporting fix
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  46 ++++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 215 +++++++++++++++++++++------------
- 2 files changed, 180 insertions(+), 81 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 9387cce..9e12df3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2273,20 +2273,54 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
- #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
- #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
--#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
--#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
- #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
--#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
--#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
- #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
--#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
--#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
- #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
- #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
- #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
- #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
- #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
- 
-+#define amdgpu_dpm_get_sclk(adev, l) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
-+		(adev)->pm.funcs->get_sclk((adev), (l))
-+
-+#define amdgpu_dpm_get_mclk(adev, l)  \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
-+		(adev)->pm.funcs->get_mclk((adev), (l))
-+
-+
-+#define amdgpu_dpm_force_performance_level(adev, l) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
-+		(adev)->pm.funcs->force_performance_level((adev), (l))
-+
-+#define amdgpu_dpm_powergate_uvd(adev, g) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
-+		(adev)->pm.funcs->powergate_uvd((adev), (g))
-+
-+#define amdgpu_dpm_powergate_vce(adev, g) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
-+		(adev)->pm.funcs->powergate_vce((adev), (g))
-+
-+#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
-+		(adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
-+
-+#define amdgpu_dpm_get_current_power_state(adev) \
-+		(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
-+
-+#define amdgpu_dpm_get_performance_level(adev) \
-+		(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
-+
-+#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
-+	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
-+
- #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
- 
- /* Common functions */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index feb247d..534bfac 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -30,10 +30,16 @@
- #include <linux/hwmon.h>
- #include <linux/hwmon-sysfs.h>
- 
-+#include "amd_powerplay.h"
-+
- static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
- 
- void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
- {
-+	if (amdgpu_powerplay)
-+		/* TODO */
-+		return;
-+
- 	if (adev->pm.dpm_enabled) {
- 		mutex_lock(&adev->pm.mutex);
- 		if (power_supply_is_system_supplied() > 0)
-@@ -52,7 +58,12 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	enum amd_pm_state_type pm = adev->pm.dpm.user_state;
-+	enum amd_pm_state_type pm;
-+
-+	if (amdgpu_powerplay) {
-+		pm = amdgpu_dpm_get_current_power_state(adev);
-+	} else
-+		pm = adev->pm.dpm.user_state;
- 
- 	return snprintf(buf, PAGE_SIZE, "%s\n",
- 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
-@@ -66,40 +77,57 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
-+	enum amd_pm_state_type  state;
- 
--	mutex_lock(&adev->pm.mutex);
- 	if (strncmp("battery", buf, strlen("battery")) == 0)
--		adev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
-+		state = POWER_STATE_TYPE_BATTERY;
- 	else if (strncmp("balanced", buf, strlen("balanced")) == 0)
--		adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
-+		state = POWER_STATE_TYPE_BALANCED;
- 	else if (strncmp("performance", buf, strlen("performance")) == 0)
--		adev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
-+		state = POWER_STATE_TYPE_PERFORMANCE;
- 	else {
--		mutex_unlock(&adev->pm.mutex);
- 		count = -EINVAL;
- 		goto fail;
- 	}
--	mutex_unlock(&adev->pm.mutex);
- 
--	/* Can't set dpm state when the card is off */
--	if (!(adev->flags & AMD_IS_PX) ||
--	    (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
--		amdgpu_pm_compute_clocks(adev);
-+	if (amdgpu_powerplay) {
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
-+	} else {
-+		mutex_lock(&adev->pm.mutex);
-+		adev->pm.dpm.user_state = state;
-+		mutex_unlock(&adev->pm.mutex);
-+
-+		/* Can't set dpm state when the card is off */
-+		if (!(adev->flags & AMD_IS_PX) ||
-+		    (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
-+			amdgpu_pm_compute_clocks(adev);
-+	}
- fail:
- 	return count;
- }
- 
- static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
--						       struct device_attribute *attr,
--						       char *buf)
-+						struct device_attribute *attr,
-+								char *buf)
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
- 
--	return snprintf(buf, PAGE_SIZE, "%s\n",
--			(level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
--			(level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
-+	if (amdgpu_powerplay) {
-+		enum amd_dpm_forced_level level;
-+
-+		level = amdgpu_dpm_get_performance_level(adev);
-+		return snprintf(buf, PAGE_SIZE, "%s\n",
-+				(level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
-+				(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
-+	} else {
-+		enum amdgpu_dpm_forced_level level;
-+
-+		level = adev->pm.dpm.forced_level;
-+		return snprintf(buf, PAGE_SIZE, "%s\n",
-+				(level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
-+				(level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
-+	}
- }
- 
- static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
-@@ -112,7 +140,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 	enum amdgpu_dpm_forced_level level;
- 	int ret = 0;
- 
--	mutex_lock(&adev->pm.mutex);
- 	if (strncmp("low", buf, strlen("low")) == 0) {
- 		level = AMDGPU_DPM_FORCED_LEVEL_LOW;
- 	} else if (strncmp("high", buf, strlen("high")) == 0) {
-@@ -123,7 +150,11 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 		count = -EINVAL;
- 		goto fail;
- 	}
--	if (adev->pm.funcs->force_performance_level) {
-+
-+	if (amdgpu_powerplay)
-+		amdgpu_dpm_force_performance_level(adev, level);
-+	else {
-+		mutex_lock(&adev->pm.mutex);
- 		if (adev->pm.dpm.thermal_active) {
- 			count = -EINVAL;
- 			goto fail;
-@@ -131,6 +162,9 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 		ret = amdgpu_dpm_force_performance_level(adev, level);
- 		if (ret)
- 			count = -EINVAL;
-+		else
-+			adev->pm.dpm.forced_level = level;
-+		mutex_unlock(&adev->pm.mutex);
- 	}
- fail:
- 	mutex_unlock(&adev->pm.mutex);
-@@ -197,7 +231,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
- 	int err;
- 	int value;
- 
--	if(!adev->pm.funcs->set_fan_control_mode)
-+	if (!adev->pm.funcs->set_fan_control_mode)
- 		return -EINVAL;
- 
- 	err = kstrtoint(buf, 10, &value);
-@@ -294,7 +328,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	umode_t effective_mode = attr->mode;
- 
--	/* Skip attributes if DPM is not enabled */
-+	if (amdgpu_powerplay)
-+		return 0;  /* to do */
-+
-+	/* Skip limit attributes if DPM is not enabled */
- 	if (!adev->pm.dpm_enabled &&
- 	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
- 	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
-@@ -636,49 +673,54 @@ done:
- 
- void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
- {
--	if (adev->pm.funcs->powergate_uvd) {
--		mutex_lock(&adev->pm.mutex);
--		/* enable/disable UVD */
-+	if (amdgpu_powerplay)
- 		amdgpu_dpm_powergate_uvd(adev, !enable);
--		mutex_unlock(&adev->pm.mutex);
--	} else {
--		if (enable) {
-+	else {
-+		if (adev->pm.funcs->powergate_uvd) {
- 			mutex_lock(&adev->pm.mutex);
--			adev->pm.dpm.uvd_active = true;
--			adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
-+			/* enable/disable UVD */
-+			amdgpu_dpm_powergate_uvd(adev, !enable);
- 			mutex_unlock(&adev->pm.mutex);
- 		} else {
--			mutex_lock(&adev->pm.mutex);
--			adev->pm.dpm.uvd_active = false;
--			mutex_unlock(&adev->pm.mutex);
-+			if (enable) {
-+				mutex_lock(&adev->pm.mutex);
-+				adev->pm.dpm.uvd_active = true;
-+				adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
-+				mutex_unlock(&adev->pm.mutex);
-+			} else {
-+				mutex_lock(&adev->pm.mutex);
-+				adev->pm.dpm.uvd_active = false;
-+				mutex_unlock(&adev->pm.mutex);
-+			}
-+			amdgpu_pm_compute_clocks(adev);
- 		}
- 
--		amdgpu_pm_compute_clocks(adev);
- 	}
- }
- 
- void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
- {
--	if (adev->pm.funcs->powergate_vce) {
--		mutex_lock(&adev->pm.mutex);
--		/* enable/disable VCE */
-+	if (amdgpu_powerplay)
- 		amdgpu_dpm_powergate_vce(adev, !enable);
--
--		mutex_unlock(&adev->pm.mutex);
--	} else {
--		if (enable) {
-+	else {
-+		if (adev->pm.funcs->powergate_vce) {
- 			mutex_lock(&adev->pm.mutex);
--			adev->pm.dpm.vce_active = true;
--			/* XXX select vce level based on ring/task */
--			adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
-+			amdgpu_dpm_powergate_vce(adev, !enable);
- 			mutex_unlock(&adev->pm.mutex);
- 		} else {
--			mutex_lock(&adev->pm.mutex);
--			adev->pm.dpm.vce_active = false;
--			mutex_unlock(&adev->pm.mutex);
-+			if (enable) {
-+				mutex_lock(&adev->pm.mutex);
-+				adev->pm.dpm.vce_active = true;
-+				/* XXX select vce level based on ring/task */
-+				adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
-+				mutex_unlock(&adev->pm.mutex);
-+			} else {
-+				mutex_lock(&adev->pm.mutex);
-+				adev->pm.dpm.vce_active = false;
-+				mutex_unlock(&adev->pm.mutex);
-+			}
-+			amdgpu_pm_compute_clocks(adev);
- 		}
--
--		amdgpu_pm_compute_clocks(adev);
- 	}
- }
- 
-@@ -686,10 +728,13 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
- {
- 	int i;
- 
--	for (i = 0; i < adev->pm.dpm.num_ps; i++) {
--		printk("== power state %d ==\n", i);
-+	if (amdgpu_powerplay)
-+		/* TO DO */
-+		return;
-+
-+	for (i = 0; i < adev->pm.dpm.num_ps; i++)
- 		amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
--	}
-+
- }
- 
- int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
-@@ -699,8 +744,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
- 	if (adev->pm.sysfs_initialized)
- 		return 0;
- 
--	if (adev->pm.funcs->get_temperature == NULL)
--		return 0;
-+	if (!amdgpu_powerplay) {
-+		if (adev->pm.funcs->get_temperature == NULL)
-+			return 0;
-+	}
-+
- 	adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
- 								   DRIVER_NAME, adev,
- 								   hwmon_groups);
-@@ -749,32 +797,43 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
- 	if (!adev->pm.dpm_enabled)
- 		return;
- 
--	mutex_lock(&adev->pm.mutex);
-+	if (amdgpu_powerplay) {
-+		int i = 0;
-+
-+		amdgpu_display_bandwidth_update(adev);
-+		mutex_lock(&adev->ring_lock);
-+			for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
-+				struct amdgpu_ring *ring = adev->rings[i];
-+				if (ring && ring->ready)
-+					amdgpu_fence_wait_empty(ring);
-+				}
-+		mutex_unlock(&adev->ring_lock);
- 
--	/* update active crtc counts */
--	adev->pm.dpm.new_active_crtcs = 0;
--	adev->pm.dpm.new_active_crtc_count = 0;
--	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
--		list_for_each_entry(crtc,
--				    &ddev->mode_config.crtc_list, head) {
--			amdgpu_crtc = to_amdgpu_crtc(crtc);
--			if (crtc->enabled) {
--				adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
--				adev->pm.dpm.new_active_crtc_count++;
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
-+	} else {
-+		mutex_lock(&adev->pm.mutex);
-+		adev->pm.dpm.new_active_crtcs = 0;
-+		adev->pm.dpm.new_active_crtc_count = 0;
-+		if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
-+			list_for_each_entry(crtc,
-+					    &ddev->mode_config.crtc_list, head) {
-+				amdgpu_crtc = to_amdgpu_crtc(crtc);
-+				if (crtc->enabled) {
-+					adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
-+					adev->pm.dpm.new_active_crtc_count++;
-+				}
- 			}
- 		}
--	}
--
--	/* update battery/ac status */
--	if (power_supply_is_system_supplied() > 0)
--		adev->pm.dpm.ac_power = true;
--	else
--		adev->pm.dpm.ac_power = false;
--
--	amdgpu_dpm_change_power_state_locked(adev);
-+		/* update battery/ac status */
-+		if (power_supply_is_system_supplied() > 0)
-+			adev->pm.dpm.ac_power = true;
-+		else
-+			adev->pm.dpm.ac_power = false;
- 
--	mutex_unlock(&adev->pm.mutex);
-+		amdgpu_dpm_change_power_state_locked(adev);
- 
-+		mutex_unlock(&adev->pm.mutex);
-+	}
- }
- 
- /*
-@@ -788,7 +847,13 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
- 	struct drm_device *dev = node->minor->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
- 
--	if (adev->pm.dpm_enabled) {
-+	if (!adev->pm.dpm_enabled) {
-+		seq_printf(m, "dpm not enabled\n");
-+		return 0;
-+	}
-+	if (amdgpu_powerplay) {
-+		amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
-+	} else {
- 		mutex_lock(&adev->pm.mutex);
- 		if (adev->pm.funcs->debugfs_print_current_performance_level)
- 			amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0043-drm-amd-powerplay-add-SMU-manager-sub-component.patch b/common/recipes-kernel/linux/files/0043-drm-amd-powerplay-add-SMU-manager-sub-component.patch
deleted file mode 100644
index 65900e57..00000000
--- a/common/recipes-kernel/linux/files/0043-drm-amd-powerplay-add-SMU-manager-sub-component.patch
+++ /dev/null
@@ -1,670 +0,0 @@
-From a84259401d5f43c9a4ad5ad62619c5c6341b7fd6 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Tue, 21 Jul 2015 17:43:02 +0800
-Subject: [PATCH 0043/1110] drm/amd/powerplay: add SMU manager sub-component
-
-The SMUMGR is one sub-component of powerplay for SMU firmware support.
-The SMU handles firmware loading for other IP blocks (GFX, SDMA, etc.)
-on VI parts.  The adds the core powerplay infrastructure to handle that.
-
-v3: direct use printk in powerplay module.
-v2: direct use cgs_read/write_register functions in smu-modules
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/Makefile          |   4 +
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c   |  81 ++++++++
- drivers/gpu/drm/amd/powerplay/inc/pp_instance.h |  33 ++++
- drivers/gpu/drm/amd/powerplay/inc/smumgr.h      | 182 +++++++++++++++++
- drivers/gpu/drm/amd/powerplay/smumgr/Makefile   |   9 +
- drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c   | 251 ++++++++++++++++++++++++
- 6 files changed, 560 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smumgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/Makefile
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-
-diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
-index e7428a1..60c6654 100644
---- a/drivers/gpu/drm/amd/powerplay/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/Makefile
-@@ -6,6 +6,10 @@ subdir-ccflags-y += -Iinclude/drm  \
- 
- AMD_PP_PATH = ../powerplay
- 
-+PP_LIBS = smumgr
-+
-+AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix drivers/gpu/drm/amd/powerplay/,$(PP_LIBS)))
-+
- include $(AMD_POWERPLAY)
- 
- POWER_MGR = amd_powerplay.o
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 39ffc5d..ea78525 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -23,8 +23,10 @@
- #include <linux/types.h>
- #include <linux/kernel.h>
- #include <linux/gfp.h>
-+#include <linux/slab.h>
- #include "amd_shared.h"
- #include "amd_powerplay.h"
-+#include "pp_instance.h"
- 
- static int pp_early_init(void *handle)
- {
-@@ -43,11 +45,51 @@ static int pp_sw_fini(void *handle)
- 
- static int pp_hw_init(void *handle)
- {
-+	struct pp_instance *pp_handle;
-+	struct pp_smumgr *smumgr;
-+	int ret = 0;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+	smumgr = pp_handle->smu_mgr;
-+
-+	if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
-+		smumgr->smumgr_funcs->smu_init == NULL ||
-+		smumgr->smumgr_funcs->start_smu == NULL)
-+		return -EINVAL;
-+
-+	ret = smumgr->smumgr_funcs->smu_init(smumgr);
-+	if (ret) {
-+		printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
-+		return ret;
-+	}
-+
-+	ret = smumgr->smumgr_funcs->start_smu(smumgr);
-+	if (ret) {
-+		printk(KERN_ERR "[ powerplay ] smc start failed\n");
-+		smumgr->smumgr_funcs->smu_fini(smumgr);
-+		return ret;
-+	}
- 	return 0;
- }
- 
- static int pp_hw_fini(void *handle)
- {
-+	struct pp_instance *pp_handle;
-+	struct pp_smumgr *smumgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+	smumgr = pp_handle->smu_mgr;
-+
-+	if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
-+		smumgr->smumgr_funcs->smu_fini != NULL)
-+		smumgr->smumgr_funcs->smu_fini(smumgr);
-+
- 	return 0;
- }
- 
-@@ -176,12 +218,49 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
- 	.print_current_performance_level = pp_debugfs_print_current_performance_level,
- };
- 
-+static int amd_pp_instance_init(struct amd_pp_init *pp_init,
-+				struct amd_powerplay *amd_pp)
-+{
-+	int ret;
-+	struct pp_instance *handle;
-+
-+	handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
-+	if (handle == NULL)
-+		return -ENOMEM;
-+
-+	ret = smum_init(pp_init, handle);
-+	if (ret)
-+		return ret;
-+
-+	amd_pp->pp_handle = handle;
-+	return 0;
-+}
-+
-+static int amd_pp_instance_fini(void *handle)
-+{
-+	struct pp_instance *instance = (struct pp_instance *)handle;
-+	if (instance == NULL)
-+		return -EINVAL;
-+
-+	smum_fini(instance->smu_mgr);
-+
-+	kfree(handle);
-+	return 0;
-+}
-+
- int amd_powerplay_init(struct amd_pp_init *pp_init,
- 		       struct amd_powerplay *amd_pp)
- {
-+	int ret;
-+
- 	if (pp_init == NULL || amd_pp == NULL)
- 		return -EINVAL;
- 
-+	ret = amd_pp_instance_init(pp_init, amd_pp);
-+
-+	if (ret)
-+		return ret;
-+
- 	amd_pp->ip_funcs = &pp_ip_funcs;
- 	amd_pp->pp_funcs = &pp_dpm_funcs;
- 
-@@ -190,5 +269,7 @@ int amd_powerplay_init(struct amd_pp_init *pp_init,
- 
- int amd_powerplay_fini(void *handle)
- {
-+	amd_pp_instance_fini(handle);
-+
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-new file mode 100644
-index 0000000..318f827
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _PP_INSTANCE_H_
-+#define _PP_INSTANCE_H_
-+
-+#include "smumgr.h"
-+
-+
-+struct pp_instance {
-+	struct pp_smumgr *smu_mgr;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
-new file mode 100644
-index 0000000..504f035
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
-@@ -0,0 +1,182 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _SMUMGR_H_
-+#define _SMUMGR_H_
-+#include <linux/types.h>
-+#include "pp_instance.h"
-+#include "amd_powerplay.h"
-+
-+struct pp_smumgr;
-+struct pp_instance;
-+
-+#define smu_lower_32_bits(n) ((uint32_t)(n))
-+#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
-+
-+struct pp_smumgr_func {
-+	int (*smu_init)(struct pp_smumgr *smumgr);
-+	int (*smu_fini)(struct pp_smumgr *smumgr);
-+	int (*start_smu)(struct pp_smumgr *smumgr);
-+	int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
-+				    uint32_t firmware);
-+	int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
-+	int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
-+					    uint32_t firmware);
-+	int (*get_argument)(struct pp_smumgr *smumgr);
-+	int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
-+	int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
-+					  uint16_t msg, uint32_t parameter);
-+	int (*download_pptable_settings)(struct pp_smumgr *smumgr,
-+					 void **table);
-+	int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
-+};
-+
-+struct pp_smumgr {
-+	uint32_t chip_family;
-+	uint32_t chip_id;
-+	uint32_t hw_revision;
-+	void *device;
-+	void *backend;
-+	uint32_t usec_timeout;
-+	bool reload_fw;
-+	const struct pp_smumgr_func *smumgr_funcs;
-+};
-+
-+
-+extern int smum_init(struct amd_pp_init *pp_init,
-+		     struct pp_instance *handle);
-+
-+extern int smum_fini(struct pp_smumgr *smumgr);
-+
-+extern int smum_get_argument(struct pp_smumgr *smumgr);
-+
-+extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);
-+
-+extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
-+
-+extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
-+
-+extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+					uint16_t msg, uint32_t parameter);
-+
-+extern int smum_wait_on_register(struct pp_smumgr *smumgr,
-+				uint32_t index, uint32_t value, uint32_t mask);
-+
-+extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
-+				uint32_t index, uint32_t value, uint32_t mask);
-+
-+extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
-+				uint32_t indirect_port, uint32_t index,
-+				uint32_t value, uint32_t mask);
-+
-+
-+extern void smum_wait_for_indirect_register_unequal(
-+				struct pp_smumgr *smumgr,
-+				uint32_t indirect_port, uint32_t index,
-+				uint32_t value, uint32_t mask);
-+
-+extern int smu_allocate_memory(void *device, uint32_t size,
-+			 enum cgs_gpu_mem_type type,
-+			 uint32_t byte_align, uint64_t *mc_addr,
-+			 void **kptr, void *handle);
-+
-+extern int smu_free_memory(void *device, void *handle);
-+
-+#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-+
-+#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
-+
-+#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr,			\
-+					port, index, value, mask)	\
-+	smum_wait_on_indirect_register(smumgr,				\
-+				mm##port##_INDEX, index, value, mask)
-+
-+
-+#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,         \
-+							index, value, mask) \
-+		smum_wait_for_register_unequal(smumgr,            \
-+					index, value, mask)
-+
-+#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask)		\
-+	SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,			\
-+				mm##reg, value, mask)
-+
-+#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval)		\
-+	SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg,				\
-+		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
-+		SMUM_FIELD_MASK(reg, field))
-+
-+#define SMUM_GET_FIELD(value, reg, field)				\
-+		(((value) & SMUM_FIELD_MASK(reg, field))		\
-+		>> SMUM_FIELD_SHIFT(reg, field))
-+
-+#define SMUM_READ_FIELD(device, reg, field)                           \
-+		SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
-+
-+#define SMUM_SET_FIELD(value, reg, field, field_val)                  \
-+		(((value) & ~SMUM_FIELD_MASK(reg, field)) |                    \
-+		(SMUM_FIELD_MASK(reg, field) & ((field_val) <<                 \
-+			SMUM_FIELD_SHIFT(reg, field))))
-+
-+#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr,		\
-+				port, index, value, mask)		\
-+	smum_wait_on_indirect_register(smumgr,				\
-+		mm##port##_INDEX_0, index, value, mask)
-+
-+#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,	\
-+				port, index, value, mask)		\
-+	smum_wait_for_indirect_register_unequal(smumgr,			\
-+		mm##port##_INDEX_0, index, value, mask)
-+
-+
-+#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
-+	SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-+
-+#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask)     \
-+		SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-+
-+
-+/*Operations on named fields.*/
-+
-+#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
-+		SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
-+			reg, field)
-+
-+#define SMUM_WRITE_FIELD(device, reg, field, fieldval)            \
-+		cgs_write_register(device, mm##reg, \
-+		SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))
-+
-+#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
-+		cgs_write_ind_register(device, port, ix##reg, \
-+			SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
-+			reg, field, fieldval))
-+
-+#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
-+	SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg,		\
-+		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
-+		SMUM_FIELD_MASK(reg, field))
-+
-+#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
-+	SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg,	\
-+		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
-+		SMUM_FIELD_MASK(reg, field))
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-new file mode 100644
-index 0000000..61bfb2a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-@@ -0,0 +1,9 @@
-+#
-+# Makefile for the 'smu manager' sub-component of powerplay.
-+# It provides the smu management services for the driver.
-+
-+SMU_MGR = smumgr.o
-+
-+AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
-+
-+AMD_POWERPLAY_FILES += $(AMD_PP_SMUMGR)
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-new file mode 100644
-index 0000000..1a11714
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-@@ -0,0 +1,251 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include "pp_instance.h"
-+#include "smumgr.h"
-+#include "cgs_common.h"
-+#include "linux/delay.h"
-+
-+int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
-+{
-+	struct pp_smumgr *smumgr;
-+
-+	if ((handle == NULL) || (pp_init == NULL))
-+		return -EINVAL;
-+
-+	smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
-+	if (smumgr == NULL)
-+		return -ENOMEM;
-+
-+	smumgr->device = pp_init->device;
-+	smumgr->chip_family = pp_init->chip_family;
-+	smumgr->chip_id = pp_init->chip_id;
-+	smumgr->hw_revision = pp_init->rev_id;
-+	smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
-+	smumgr->reload_fw = 1;
-+	handle->smu_mgr = smumgr;
-+
-+	switch (smumgr->chip_family) {
-+	case AMD_FAMILY_CZ:
-+		/* TODO */
-+		break;
-+	case AMD_FAMILY_VI:
-+		/* TODO */
-+		break;
-+	default:
-+		kfree(smumgr);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+int smum_fini(struct pp_smumgr *smumgr)
-+{
-+	kfree(smumgr);
-+	return 0;
-+}
-+
-+int smum_get_argument(struct pp_smumgr *smumgr)
-+{
-+	if (NULL != smumgr->smumgr_funcs->get_argument)
-+		return smumgr->smumgr_funcs->get_argument(smumgr);
-+
-+	return 0;
-+}
-+
-+int smum_download_powerplay_table(struct pp_smumgr *smumgr,
-+								void **table)
-+{
-+	if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
-+		return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
-+									table);
-+
-+	return 0;
-+}
-+
-+int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
-+{
-+	if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
-+		return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
-+
-+	return 0;
-+}
-+
-+int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
-+		return -EINVAL;
-+
-+	return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
-+}
-+
-+int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+					uint16_t msg, uint32_t parameter)
-+{
-+	if (smumgr == NULL ||
-+		smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
-+		return -EINVAL;
-+	return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
-+						smumgr, msg, parameter);
-+}
-+
-+/*
-+ * Returns once the part of the register indicated by the mask has
-+ * reached the given value.
-+ */
-+int smum_wait_on_register(struct pp_smumgr *smumgr,
-+				uint32_t index,
-+				uint32_t value, uint32_t mask)
-+{
-+	uint32_t i;
-+	uint32_t cur_value;
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	for (i = 0; i < smumgr->usec_timeout; i++) {
-+		cur_value = cgs_read_register(smumgr->device, index);
-+		if ((cur_value & mask) == (value & mask))
-+			break;
-+		udelay(1);
-+	}
-+
-+	/* timeout means wrong logic*/
-+	if (i == smumgr->usec_timeout)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
-+					uint32_t index,
-+					uint32_t value, uint32_t mask)
-+{
-+	uint32_t i;
-+	uint32_t cur_value;
-+
-+	if (smumgr == NULL)
-+		return -EINVAL;
-+
-+	for (i = 0; i < smumgr->usec_timeout; i++) {
-+		cur_value = cgs_read_register(smumgr->device,
-+									index);
-+		if ((cur_value & mask) != (value & mask))
-+			break;
-+		udelay(1);
-+	}
-+
-+	/* timeout means wrong logic */
-+	if (i == smumgr->usec_timeout)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+
-+/*
-+ * Returns once the part of the register indicated by the mask
-+ * has reached the given value.The indirect space is described by
-+ * giving the memory-mapped index of the indirect index register.
-+ */
-+int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
-+					uint32_t indirect_port,
-+					uint32_t index,
-+					uint32_t value,
-+					uint32_t mask)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	cgs_write_register(smumgr->device, indirect_port, index);
-+	return smum_wait_on_register(smumgr, indirect_port + 1,
-+						mask, value);
-+}
-+
-+void smum_wait_for_indirect_register_unequal(
-+						struct pp_smumgr *smumgr,
-+						uint32_t indirect_port,
-+						uint32_t index,
-+						uint32_t value,
-+						uint32_t mask)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return;
-+	cgs_write_register(smumgr->device, indirect_port, index);
-+	smum_wait_for_register_unequal(smumgr, indirect_port + 1,
-+						value, mask);
-+}
-+
-+int smu_allocate_memory(void *device, uint32_t size,
-+			 enum cgs_gpu_mem_type type,
-+			 uint32_t byte_align, uint64_t *mc_addr,
-+			 void **kptr, void *handle)
-+{
-+	int ret = 0;
-+	cgs_handle_t cgs_handle;
-+
-+	if (device == NULL || handle == NULL ||
-+	    mc_addr == NULL || kptr == NULL)
-+		return -EINVAL;
-+
-+	ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
-+				0, 0, (cgs_handle_t *)handle);
-+	if (ret)
-+		return -ENOMEM;
-+
-+	cgs_handle = *(cgs_handle_t *)handle;
-+
-+	ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
-+	if (ret)
-+		goto error_gmap;
-+
-+	ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
-+	if (ret)
-+		goto error_kmap;
-+
-+	return 0;
-+
-+error_kmap:
-+	cgs_gunmap_gpu_mem(device, cgs_handle);
-+
-+error_gmap:
-+	cgs_free_gpu_mem(device, cgs_handle);
-+	return ret;
-+}
-+
-+int smu_free_memory(void *device, void *handle)
-+{
-+	cgs_handle_t cgs_handle = (cgs_handle_t)handle;
-+
-+	if (device == NULL || handle == NULL)
-+		return -EINVAL;
-+
-+	cgs_kunmap_gpu_mem(device, cgs_handle);
-+	cgs_gunmap_gpu_mem(device, cgs_handle);
-+	cgs_free_gpu_mem(device, cgs_handle);
-+
-+	return 0;
-+}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0044-drm-amd-powerplay-add-hardware-manager-sub-component.patch b/common/recipes-kernel/linux/files/0044-drm-amd-powerplay-add-hardware-manager-sub-component.patch
deleted file mode 100644
index 3b97bd6e..00000000
--- a/common/recipes-kernel/linux/files/0044-drm-amd-powerplay-add-hardware-manager-sub-component.patch
+++ /dev/null
@@ -1,3650 +0,0 @@
-From f6229149c93236443805deed2ec2ef92d672c2d1 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Tue, 21 Jul 2015 21:18:15 +0800
-Subject: [PATCH 0044/1110] drm/amd/powerplay: add hardware manager
- sub-component
-
-The hwmgr handles all hardware related calls, including clock/power
-gating control, DPM, read and parse PPTable, etc.
-
-v5: squash in fixes
-v4: implement acpi's atcs function use cgs interface
-v3: fix code style error and add big-endian mode support.
-v2: use cgs interface directly in hwmgr sub-module
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/Makefile             |    2 +-
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |   55 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   10 +
- .../gpu/drm/amd/powerplay/hwmgr/functiontables.c   |  154 ++
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |   84 +
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |  201 +++
- drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c      |   76 +
- .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  | 1661 ++++++++++++++++++++
- .../gpu/drm/amd/powerplay/hwmgr/processpptables.h  |   47 +
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |    1 -
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    |  280 ++++
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  607 +++++++
- drivers/gpu/drm/amd/powerplay/inc/power_state.h    |  200 +++
- drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h        |   28 +
- drivers/gpu/drm/amd/powerplay/inc/pp_instance.h    |    3 +-
- .../gpu/drm/amd/powerplay/inc/pp_power_source.h    |   36 +
- 16 files changed, 3439 insertions(+), 6 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/power_state.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
-index 60c6654..6359c67 100644
---- a/drivers/gpu/drm/amd/powerplay/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/Makefile
-@@ -6,7 +6,7 @@ subdir-ccflags-y += -Iinclude/drm  \
- 
- AMD_PP_PATH = ../powerplay
- 
--PP_LIBS = smumgr
-+PP_LIBS = smumgr hwmgr
- 
- AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix drivers/gpu/drm/amd/powerplay/,$(PP_LIBS)))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index ea78525..88fdb04 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -35,12 +35,46 @@ static int pp_early_init(void *handle)
- 
- static int pp_sw_init(void *handle)
- {
--	return 0;
-+	struct pp_instance *pp_handle;
-+	struct pp_hwmgr  *hwmgr;
-+	int ret = 0;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+	hwmgr = pp_handle->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->pptable_func == NULL ||
-+	    hwmgr->hwmgr_func == NULL ||
-+	    hwmgr->pptable_func->pptable_init == NULL ||
-+	    hwmgr->hwmgr_func->backend_init == NULL)
-+		return -EINVAL;
-+
-+	ret = hwmgr->pptable_func->pptable_init(hwmgr);
-+	if (ret == 0)
-+		ret = hwmgr->hwmgr_func->backend_init(hwmgr);
-+
-+	return ret;
- }
- 
- static int pp_sw_fini(void *handle)
- {
--	return 0;
-+	struct pp_instance *pp_handle;
-+	struct pp_hwmgr  *hwmgr;
-+	int ret = 0;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+	hwmgr = pp_handle->hwmgr;
-+
-+	if (hwmgr != NULL || hwmgr->hwmgr_func != NULL ||
-+	    hwmgr->hwmgr_func->backend_fini != NULL)
-+		ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
-+
-+	return ret;
- }
- 
- static int pp_hw_init(void *handle)
-@@ -72,6 +106,8 @@ static int pp_hw_init(void *handle)
- 		smumgr->smumgr_funcs->smu_fini(smumgr);
- 		return ret;
- 	}
-+	hw_init_power_state_table(pp_handle->hwmgr);
-+
- 	return 0;
- }
- 
-@@ -203,6 +239,7 @@ pp_debugfs_print_current_performance_level(void *handle,
- {
- 	return;
- }
-+
- const struct amd_powerplay_funcs pp_dpm_funcs = {
- 	.get_temperature = NULL,
- 	.load_firmware = pp_dpm_load_fw,
-@@ -230,10 +267,20 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init,
- 
- 	ret = smum_init(pp_init, handle);
- 	if (ret)
--		return ret;
-+		goto fail_smum;
-+
-+	ret = hwmgr_init(pp_init, handle);
-+	if (ret)
-+		goto fail_hwmgr;
- 
- 	amd_pp->pp_handle = handle;
- 	return 0;
-+
-+fail_hwmgr:
-+	smum_fini(handle->smu_mgr);
-+fail_smum:
-+	kfree(handle);
-+	return ret;
- }
- 
- static int amd_pp_instance_fini(void *handle)
-@@ -242,6 +289,8 @@ static int amd_pp_instance_fini(void *handle)
- 	if (instance == NULL)
- 		return -EINVAL;
- 
-+	hwmgr_fini(instance->hwmgr);
-+
- 	smum_fini(instance->smu_mgr);
- 
- 	kfree(handle);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-new file mode 100644
-index 0000000..ef529e0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'hw manager' sub-component of powerplay.
-+# It provides the hardware management services for the driver.
-+
-+HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-+	       hardwaremanager.o pp_acpi.o
-+
-+AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
-+
-+AMD_POWERPLAY_FILES += $(AMD_PP_HWMGR)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-new file mode 100644
-index 0000000..5abde8f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-@@ -0,0 +1,154 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include "hwmgr.h"
-+
-+static int phm_run_table(struct pp_hwmgr *hwmgr,
-+			 struct phm_runtime_table_header *rt_table,
-+			 void *input,
-+			 void *output,
-+			 void *temp_storage)
-+{
-+	int result = 0;
-+	phm_table_function *function;
-+
-+	for (function = rt_table->function_list; NULL != *function; function++) {
-+		int tmp = (*function)(hwmgr, input, output, temp_storage, result);
-+
-+		if (tmp == PP_Result_TableImmediateExit)
-+			break;
-+		if (tmp) {
-+			if (0 == result)
-+				result = tmp;
-+			if (rt_table->exit_error)
-+				break;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+int phm_dispatch_table(struct pp_hwmgr *hwmgr,
-+		       struct phm_runtime_table_header *rt_table,
-+		       void *input, void *output)
-+{
-+	int result = 0;
-+	void *temp_storage = NULL;
-+
-+	if (hwmgr == NULL || rt_table == NULL || rt_table->function_list == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n");
-+		return 0; /*temp return ture because some function not implement on some asic */
-+	}
-+
-+	if (0 != rt_table->storage_size) {
-+		temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
-+		if (temp_storage == NULL) {
-+			printk(KERN_ERR "[ powerplay ] Could not allocate table temporary storage\n");
-+			return -1;
-+		}
-+	}
-+
-+	result = phm_run_table(hwmgr, rt_table, input, output, temp_storage);
-+
-+	if (NULL != temp_storage)
-+		kfree(temp_storage);
-+
-+	return result;
-+}
-+
-+int phm_construct_table(struct pp_hwmgr *hwmgr,
-+			struct phm_master_table_header *master_table,
-+			struct phm_runtime_table_header *rt_table)
-+{
-+	uint32_t function_count = 0;
-+	const struct phm_master_table_item *table_item;
-+	uint32_t size;
-+	phm_table_function *run_time_list;
-+	phm_table_function *rtf;
-+
-+	if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n");
-+		return -1;
-+	}
-+
-+	for (table_item = master_table->master_list;
-+		NULL != table_item->tableFunction; table_item++) {
-+		if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
-+		    (table_item->isFunctionNeededInRuntimeTable(hwmgr)))
-+			function_count++;
-+	}
-+
-+	size = (function_count + 1) * sizeof(phm_table_function);
-+	run_time_list = kzalloc(size, GFP_KERNEL);
-+	if (NULL == run_time_list)
-+		return -1;
-+
-+	rtf = run_time_list;
-+	for (table_item = master_table->master_list;
-+		NULL != table_item->tableFunction; table_item++) {
-+		if ((rtf - run_time_list) > function_count) {
-+			printk(KERN_ERR "[ powerplay ] Check function results have changed\n");
-+			kfree(run_time_list);
-+			return -1;
-+		}
-+
-+		if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
-+		     (table_item->isFunctionNeededInRuntimeTable(hwmgr))) {
-+			*(rtf++) = table_item->tableFunction;
-+		}
-+	}
-+
-+	if ((rtf - run_time_list) > function_count) {
-+		printk(KERN_ERR "[ powerplay ] Check function results have changed\n");
-+		kfree(run_time_list);
-+		return -1;
-+	}
-+
-+	*rtf = NULL;
-+	rt_table->function_list = run_time_list;
-+	rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError));
-+	rt_table->storage_size = master_table->storage_size;
-+	return 0;
-+}
-+
-+int phm_destroy_table(struct pp_hwmgr *hwmgr,
-+		      struct phm_runtime_table_header *rt_table)
-+{
-+	if (hwmgr == NULL || rt_table == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Parameter\n");
-+		return -1;
-+	}
-+
-+	if (NULL == rt_table->function_list)
-+		return 0;
-+
-+	kfree(rt_table->function_list);
-+
-+	rt_table->function_list = NULL;
-+	rt_table->storage_size = 0;
-+	rt_table->exit_error = false;
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-new file mode 100644
-index 0000000..7317e43
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -0,0 +1,84 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/errno.h>
-+#include "hwmgr.h"
-+#include "hardwaremanager.h"
-+#include "pp_acpi.h"
-+#include "amd_acpi.h"
-+
-+void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
-+{
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
-+
-+	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
-+		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
-+}
-+
-+int phm_setup_asic(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_TablelessHardwareInterface)) {
-+		if (NULL != hwmgr->hwmgr_func->asic_setup)
-+			return hwmgr->hwmgr_func->asic_setup(hwmgr);
-+	} else {
-+		return phm_dispatch_table (hwmgr, &(hwmgr->setup_asic),
-+					  NULL, NULL);
-+	}
-+
-+	return 0;
-+}
-+
-+int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_TablelessHardwareInterface)) {
-+		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
-+			return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
-+	} else {
-+		return phm_dispatch_table (hwmgr,
-+				&(hwmgr->enable_dynamic_state_management),
-+				NULL, NULL);
-+	}
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-new file mode 100644
-index 0000000..f6b1153
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -0,0 +1,201 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include "linux/delay.h"
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include "cgs_common.h"
-+#include "power_state.h"
-+#include "hwmgr.h"
-+
-+
-+
-+int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
-+{
-+	struct pp_hwmgr *hwmgr;
-+
-+	if ((handle == NULL) || (pp_init == NULL))
-+		return -EINVAL;
-+
-+	hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
-+	if (hwmgr == NULL)
-+		return -ENOMEM;
-+
-+	handle->hwmgr = hwmgr;
-+	hwmgr->smumgr = handle->smu_mgr;
-+	hwmgr->device = pp_init->device;
-+	hwmgr->chip_family = pp_init->chip_family;
-+	hwmgr->chip_id = pp_init->chip_id;
-+	hwmgr->hw_revision = pp_init->rev_id;
-+	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
-+	hwmgr->power_source = PP_PowerSource_AC;
-+
-+	switch (hwmgr->chip_family) {
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	phm_init_dynamic_caps(hwmgr);
-+
-+	return 0;
-+}
-+
-+int hwmgr_fini(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr == NULL || hwmgr->ps == NULL)
-+		return -EINVAL;
-+
-+	kfree(hwmgr->ps);
-+	kfree(hwmgr);
-+	return 0;
-+}
-+
-+int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	unsigned int i;
-+	unsigned int table_entries;
-+	struct pp_power_state *state;
-+	int size;
-+
-+	if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
-+		return -EINVAL;
-+
-+	if (hwmgr->hwmgr_func->get_power_state_size == NULL)
-+		return -EINVAL;
-+
-+	hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
-+
-+	hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
-+					  sizeof(struct pp_power_state);
-+
-+	hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
-+
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
-+		if (state->classification.flags & PP_StateClassificationFlag_Boot) {
-+			hwmgr->boot_ps = state;
-+			hwmgr->current_ps = hwmgr->request_ps = state;
-+		}
-+
-+		state->id = i + 1; /* assigned unique num for every power state id */
-+
-+		if (state->classification.flags & PP_StateClassificationFlag_Uvd)
-+			hwmgr->uvd_ps = state;
-+		state = (struct pp_power_state *)((uint64_t)state + size);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/**
-+ * Returns once the part of the register indicated by the mask has
-+ * reached the given value.
-+ */
-+int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
-+			 uint32_t value, uint32_t mask)
-+{
-+	uint32_t i;
-+	uint32_t cur_value;
-+
-+	if (hwmgr == NULL || hwmgr->device == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
-+		return -EINVAL;
-+	}
-+
-+	for (i = 0; i < hwmgr->usec_timeout; i++) {
-+		cur_value = cgs_read_register(hwmgr->device, index);
-+		if ((cur_value & mask) == (value & mask))
-+			break;
-+		udelay(1);
-+	}
-+
-+	/* timeout means wrong logic*/
-+	if (i == hwmgr->usec_timeout)
-+		return -1;
-+	return 0;
-+}
-+
-+int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
-+				uint32_t index, uint32_t value, uint32_t mask)
-+{
-+	uint32_t i;
-+	uint32_t cur_value;
-+
-+	if (hwmgr == NULL || hwmgr->device == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
-+		return -EINVAL;
-+	}
-+
-+	for (i = 0; i < hwmgr->usec_timeout; i++) {
-+		cur_value = cgs_read_register(hwmgr->device, index);
-+		if ((cur_value & mask) != (value & mask))
-+			break;
-+		udelay(1);
-+	}
-+
-+	/* timeout means wrong logic*/
-+	if (i == hwmgr->usec_timeout)
-+		return -1;
-+	return 0;
-+}
-+
-+
-+/**
-+ * Returns once the part of the register indicated by the mask has
-+ * reached the given value.The indirect space is described by giving
-+ * the memory-mapped index of the indirect index register.
-+ */
-+void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
-+				uint32_t indirect_port,
-+				uint32_t index,
-+				uint32_t value,
-+				uint32_t mask)
-+{
-+	if (hwmgr == NULL || hwmgr->device == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
-+		return;
-+	}
-+
-+	cgs_write_register(hwmgr->device, indirect_port, index);
-+	phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
-+}
-+
-+void phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
-+					uint32_t indirect_port,
-+					uint32_t index,
-+					uint32_t value,
-+					uint32_t mask)
-+{
-+	if (hwmgr == NULL || hwmgr->device == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
-+		return;
-+	}
-+
-+	cgs_write_register(hwmgr->device, indirect_port, index);
-+	phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
-+				      value, mask);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
-new file mode 100644
-index 0000000..7b2d500
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
-@@ -0,0 +1,76 @@
-+#include <linux/errno.h>
-+#include "linux/delay.h"
-+#include "hwmgr.h"
-+#include "amd_acpi.h"
-+
-+bool acpi_atcs_functions_supported(void *device, uint32_t index)
-+{
-+	int32_t result;
-+	struct atcs_verify_interface output_buf = {0};
-+
-+	int32_t temp_buffer = 1;
-+
-+	result = cgs_call_acpi_method(device, CGS_ACPI_METHOD_ATCS,
-+						ATCS_FUNCTION_VERIFY_INTERFACE,
-+						&temp_buffer,
-+						&output_buf,
-+						1,
-+						sizeof(temp_buffer),
-+						sizeof(output_buf));
-+
-+	return result == 0 ? (output_buf.function_bits & (1 << (index - 1))) != 0 : false;
-+}
-+
-+int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
-+{
-+	struct atcs_pref_req_input atcs_input;
-+	struct atcs_pref_req_output atcs_output;
-+	u32 retry = 3;
-+	int result;
-+	struct cgs_system_info info = {0};
-+
-+	if (!acpi_atcs_functions_supported(device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST))
-+		return -EINVAL;
-+
-+	info.size = sizeof(struct cgs_system_info);
-+	info.info_id = CGS_SYSTEM_INFO_ADAPTER_BDF_ID;
-+	result = cgs_query_system_info(device, &info);
-+	if (result != 0)
-+		return -EINVAL;
-+	atcs_input.client_id = (uint16_t)info.value;
-+	atcs_input.size = sizeof(struct atcs_pref_req_input);
-+	atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK;
-+	atcs_input.flags = ATCS_WAIT_FOR_COMPLETION;
-+	if (advertise)
-+		atcs_input.flags |= ATCS_ADVERTISE_CAPS;
-+	atcs_input.req_type = ATCS_PCIE_LINK_SPEED;
-+	atcs_input.perf_req = perf_req;
-+
-+	atcs_output.size = sizeof(struct atcs_pref_req_input);
-+
-+	while (retry--) {
-+		result = cgs_call_acpi_method(device,
-+						CGS_ACPI_METHOD_ATCS,
-+						ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST,
-+						&atcs_input,
-+						&atcs_output,
-+						0,
-+						sizeof(atcs_input),
-+						sizeof(atcs_output));
-+		if (result != 0)
-+			return -EIO;
-+
-+		switch (atcs_output.ret_val) {
-+		case ATCS_REQUEST_REFUSED:
-+		default:
-+			return -EINVAL;
-+		case ATCS_REQUEST_COMPLETE:
-+			return 0;
-+		case ATCS_REQUEST_IN_PROGRESS:
-+			udelay(10);
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-new file mode 100644
-index 0000000..dc1d3d2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-@@ -0,0 +1,1661 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+
-+#include "processpptables.h"
-+#include <atom-types.h>
-+#include <atombios.h>
-+#include "pptable.h"
-+#include "power_state.h"
-+#include "hwmgr.h"
-+#include "hardwaremanager.h"
-+
-+
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8 24
-+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V9 26
-+
-+#define NUM_BITS_CLOCK_INFO_ARRAY_INDEX 6
-+
-+static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t vce_table_offset = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	   sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
-+			(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+
-+		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
-+			const ATOM_PPLIB_EXTENDEDHEADER  *extended_header =
-+						(const ATOM_PPLIB_EXTENDEDHEADER *)
-+						(((unsigned long)powerplay_table3) +
-+						le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+			if (le16_to_cpu(extended_header->usSize) >=
-+			   SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2)
-+				vce_table_offset = le16_to_cpu(extended_header->usVCETableOffset);
-+		}
-+	}
-+
-+	return vce_table_offset;
-+}
-+
-+static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_vce_table_offset(hwmgr,
-+						powerplay_table);
-+
-+	if (table_offset > 0)
-+		return table_offset + 1;
-+
-+	return 0;
-+}
-+
-+static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
-+							powerplay_table);
-+	uint16_t table_size = 0;
-+
-+	if (table_offset > 0) {
-+		const VCEClockInfoArray *p = (const VCEClockInfoArray *)
-+			(((unsigned long) powerplay_table) + table_offset);
-+		table_size = sizeof(uint8_t) + p->ucNumEntries * sizeof(VCEClockInfo);
-+	}
-+
-+	return table_size;
-+}
-+
-+static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr,
-+				const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
-+							powerplay_table);
-+
-+	if (table_offset > 0)
-+		return table_offset + get_vce_clock_info_array_size(hwmgr,
-+							powerplay_table);
-+
-+	return 0;
-+}
-+
-+static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr,
-+							const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
-+	uint16_t table_size = 0;
-+
-+	if (table_offset > 0) {
-+		const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *ptable =
-+			(const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)(((unsigned long) powerplay_table) + table_offset);
-+
-+		table_size = sizeof(uint8_t) + ptable->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record);
-+	}
-+	return table_size;
-+}
-+
-+static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
-+
-+	if (table_offset > 0)
-+		return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);
-+
-+	return 0;
-+}
-+
-+static const ATOM_PPLIB_VCE_State_Table *get_vce_state_table(
-+						struct pp_hwmgr *hwmgr,
-+						const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);
-+
-+	if (table_offset > 0)
-+		return (const ATOM_PPLIB_VCE_State_Table *)(((unsigned long) powerplay_table) + table_offset);
-+
-+	return NULL;
-+}
-+
-+static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t uvd_table_offset = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
-+			(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
-+			const ATOM_PPLIB_EXTENDEDHEADER  *extended_header =
-+					(const ATOM_PPLIB_EXTENDEDHEADER *)
-+					(((unsigned long)powerplay_table3) +
-+				le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+			if (le16_to_cpu(extended_header->usSize) >=
-+			    SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3)
-+				uvd_table_offset = le16_to_cpu(extended_header->usUVDTableOffset);
-+		}
-+	}
-+	return uvd_table_offset;
-+}
-+
-+static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr,
-+			 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_uvd_table_offset(hwmgr,
-+						    powerplay_table);
-+
-+	if (table_offset > 0)
-+		return table_offset + 1;
-+	return 0;
-+}
-+
-+static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
-+						    powerplay_table);
-+	uint16_t table_size = 0;
-+
-+	if (table_offset > 0) {
-+		const UVDClockInfoArray *p = (const UVDClockInfoArray *)
-+					(((unsigned long) powerplay_table)
-+					+ table_offset);
-+		table_size = sizeof(UCHAR) +
-+			     p->ucNumEntries * sizeof(UVDClockInfo);
-+	}
-+
-+	return table_size;
-+}
-+
-+static uint16_t get_uvd_clock_voltage_limit_table_offset(
-+			struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
-+						     powerplay_table);
-+
-+	if (table_offset > 0)
-+		return table_offset +
-+			get_uvd_clock_info_array_size(hwmgr, powerplay_table);
-+
-+	return 0;
-+}
-+
-+static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t samu_table_offset = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
-+			(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
-+			const ATOM_PPLIB_EXTENDEDHEADER  *extended_header =
-+				(const ATOM_PPLIB_EXTENDEDHEADER *)
-+				(((unsigned long)powerplay_table3) +
-+				le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+			if (le16_to_cpu(extended_header->usSize) >=
-+			    SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4)
-+				samu_table_offset = le16_to_cpu(extended_header->usSAMUTableOffset);
-+		}
-+	}
-+
-+	return samu_table_offset;
-+}
-+
-+static uint16_t get_samu_clock_voltage_limit_table_offset(
-+			struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t table_offset = get_samu_table_offset(hwmgr,
-+					    powerplay_table);
-+
-+	if (table_offset > 0)
-+		return table_offset + 1;
-+
-+	return 0;
-+}
-+
-+static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr,
-+				const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t acp_table_offset = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
-+			(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
-+			const ATOM_PPLIB_EXTENDEDHEADER  *pExtendedHeader =
-+				(const ATOM_PPLIB_EXTENDEDHEADER *)
-+				(((unsigned long)powerplay_table3) +
-+				le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+			if (le16_to_cpu(pExtendedHeader->usSize) >=
-+			    SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6)
-+				acp_table_offset = le16_to_cpu(pExtendedHeader->usACPTableOffset);
-+		}
-+	}
-+
-+	return acp_table_offset;
-+}
-+
-+static uint16_t get_acp_clock_voltage_limit_table_offset(
-+				struct pp_hwmgr *hwmgr,
-+				const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table);
-+
-+	if (tableOffset > 0)
-+		return tableOffset + 1;
-+
-+	return 0;
-+}
-+
-+static uint16_t get_cacp_tdp_table_offset(
-+				struct pp_hwmgr *hwmgr,
-+				const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t cacTdpTableOffset = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
-+			const ATOM_PPLIB_EXTENDEDHEADER  *pExtendedHeader =
-+					(const ATOM_PPLIB_EXTENDEDHEADER *)
-+					(((unsigned long)powerplay_table3) +
-+				le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+			if (le16_to_cpu(pExtendedHeader->usSize) >=
-+			    SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7)
-+				cacTdpTableOffset = le16_to_cpu(pExtendedHeader->usPowerTuneTableOffset);
-+		}
-+	}
-+
-+	return cacTdpTableOffset;
-+}
-+
-+static int get_cac_tdp_table(struct pp_hwmgr *hwmgr,
-+				struct phm_cac_tdp_table **ptable,
-+				const ATOM_PowerTune_Table *table,
-+				uint16_t us_maximum_power_delivery_limit)
-+{
-+	unsigned long table_size;
-+	struct phm_cac_tdp_table *tdp_table;
-+
-+	table_size = sizeof(unsigned long) + sizeof(struct phm_cac_tdp_table);
-+
-+	tdp_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == tdp_table)
-+		return -ENOMEM;
-+
-+	tdp_table->usTDP = le16_to_cpu(table->usTDP);
-+	tdp_table->usConfigurableTDP = le16_to_cpu(table->usConfigurableTDP);
-+	tdp_table->usTDC = le16_to_cpu(table->usTDC);
-+	tdp_table->usBatteryPowerLimit = le16_to_cpu(table->usBatteryPowerLimit);
-+	tdp_table->usSmallPowerLimit = le16_to_cpu(table->usSmallPowerLimit);
-+	tdp_table->usLowCACLeakage = le16_to_cpu(table->usLowCACLeakage);
-+	tdp_table->usHighCACLeakage = le16_to_cpu(table->usHighCACLeakage);
-+	tdp_table->usMaximumPowerDeliveryLimit = us_maximum_power_delivery_limit;
-+
-+	*ptable = tdp_table;
-+
-+	return 0;
-+}
-+
-+static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t sclk_vdd_gfx_table_offset = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
-+			const ATOM_PPLIB_EXTENDEDHEADER  *pExtendedHeader =
-+				(const ATOM_PPLIB_EXTENDEDHEADER *)
-+				(((unsigned long)powerplay_table3) +
-+				le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+			if (le16_to_cpu(pExtendedHeader->usSize) >=
-+			    SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8)
-+				sclk_vdd_gfx_table_offset =
-+					le16_to_cpu(pExtendedHeader->usSclkVddgfxTableOffset);
-+		}
-+	}
-+
-+	return sclk_vdd_gfx_table_offset;
-+}
-+
-+static uint16_t get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(
-+			struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table);
-+
-+	if (tableOffset > 0)
-+		return tableOffset;
-+
-+	return 0;
-+}
-+
-+
-+static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
-+		struct phm_clock_voltage_dependency_table **ptable,
-+		const ATOM_PPLIB_Clock_Voltage_Dependency_Table *table)
-+{
-+
-+	unsigned long table_size, i;
-+	struct phm_clock_voltage_dependency_table *dep_table;
-+
-+	table_size = sizeof(unsigned long) +
-+		sizeof(struct phm_clock_voltage_dependency_table)
-+		* table->ucNumEntries;
-+
-+	dep_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == dep_table)
-+		return -ENOMEM;
-+
-+	dep_table->count = (unsigned long)table->ucNumEntries;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		dep_table->entries[i].clk =
-+			((unsigned long)table->entries[i].ucClockHigh << 16) |
-+			le16_to_cpu(table->entries[i].usClockLow);
-+			dep_table->entries[i].v =
-+				(unsigned long)le16_to_cpu(table->entries[i].usVoltage);
-+	}
-+
-+	*ptable = dep_table;
-+
-+	return 0;
-+}
-+
-+static int get_valid_clk(struct pp_hwmgr *hwmgr,
-+			struct phm_clock_array **ptable,
-+			const struct phm_clock_voltage_dependency_table *table)
-+{
-+	unsigned long table_size, i;
-+	struct phm_clock_array *clock_table;
-+
-+	table_size = sizeof(unsigned long) + sizeof(unsigned long) * table->count;
-+	clock_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == clock_table)
-+		return -ENOMEM;
-+
-+	clock_table->count = (unsigned long)table->count;
-+
-+	for (i = 0; i < clock_table->count; i++)
-+		clock_table->values[i] = (unsigned long)table->entries[i].clk;
-+
-+	*ptable = clock_table;
-+
-+	return 0;
-+}
-+
-+static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr,
-+			struct phm_clock_and_voltage_limits *limits,
-+			const ATOM_PPLIB_Clock_Voltage_Limit_Table *table)
-+{
-+	limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) |
-+			le16_to_cpu(table->entries[0].usSclkLow);
-+	limits->mclk = ((unsigned long)table->entries[0].ucMclkHigh << 16) |
-+			le16_to_cpu(table->entries[0].usMclkLow);
-+	limits->vddc = (unsigned long)le16_to_cpu(table->entries[0].usVddc);
-+	limits->vddci = (unsigned long)le16_to_cpu(table->entries[0].usVddci);
-+
-+	return 0;
-+}
-+
-+
-+static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
-+		       enum phm_platform_caps cap)
-+{
-+	if (enable)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
-+	else
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
-+}
-+
-+static int set_platform_caps(struct pp_hwmgr *hwmgr,
-+			unsigned long powerplay_caps)
-+{
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_POWERPLAY),
-+		PHM_PlatformCaps_PowerPlaySupport
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
-+		PHM_PlatformCaps_BiosPowerSourceControl
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s),
-+		PHM_PlatformCaps_EnableASPML0s
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1),
-+		PHM_PlatformCaps_EnableASPML1
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS),
-+		PHM_PlatformCaps_EnableBackbias
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC),
-+		PHM_PlatformCaps_AutomaticDCTransition
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY),
-+		PHM_PlatformCaps_GeminiPrimary
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC),
-+		PHM_PlatformCaps_StepVddc
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL),
-+		PHM_PlatformCaps_EnableVoltageControl
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL),
-+		PHM_PlatformCaps_EnableSideportControl
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1),
-+		PHM_PlatformCaps_TurnOffPll_ASPML1
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_HTLINKCONTROL),
-+		PHM_PlatformCaps_EnableHTLinkControl
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL),
-+		PHM_PlatformCaps_EnableMVDDControl
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL),
-+		PHM_PlatformCaps_ControlVDDCI
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT),
-+		PHM_PlatformCaps_RegulatorHot
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT),
-+		PHM_PlatformCaps_BootStateOnAlert
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT),
-+		PHM_PlatformCaps_DontWaitForVBlankOnAlert
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_BACO),
-+		PHM_PlatformCaps_BACO
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE),
-+		PHM_PlatformCaps_NewCACVoltage
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY),
-+		PHM_PlatformCaps_RevertGPIO5Polarity
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17),
-+		PHM_PlatformCaps_Thermal2GPIO17
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE),
-+		PHM_PlatformCaps_VRHotGPIOConfigurable
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_TEMP_INVERSION),
-+		PHM_PlatformCaps_TempInversion
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_EVV),
-+		PHM_PlatformCaps_EVV
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
-+		PHM_PlatformCaps_CombinePCCWithThermalSignal
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE),
-+		PHM_PlatformCaps_LoadPostProductionFirmware
-+	);
-+
-+	set_hw_cap(
-+		hwmgr,
-+		0 != (powerplay_caps & ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC),
-+		PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc
-+	);
-+
-+	return 0;
-+}
-+
-+static PP_StateClassificationFlags make_classification_flags(
-+						   struct pp_hwmgr *hwmgr,
-+						    USHORT classification,
-+						   USHORT classification2)
-+{
-+	PP_StateClassificationFlags result = 0;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
-+		result |= PP_StateClassificationFlag_Boot;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
-+		result |= PP_StateClassificationFlag_Thermal;
-+
-+	if (classification &
-+			ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
-+		result |= PP_StateClassificationFlag_LimitedPowerSource;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
-+		result |= PP_StateClassificationFlag_Rest;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
-+		result |= PP_StateClassificationFlag_Forced;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
-+		result |= PP_StateClassificationFlag_3DPerformance;
-+
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
-+		result |= PP_StateClassificationFlag_ACOverdriveTemplate;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
-+		result |= PP_StateClassificationFlag_Uvd;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
-+		result |= PP_StateClassificationFlag_UvdHD;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
-+		result |= PP_StateClassificationFlag_UvdSD;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
-+		result |= PP_StateClassificationFlag_HD2;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
-+		result |= PP_StateClassificationFlag_ACPI;
-+
-+	if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
-+		result |= PP_StateClassificationFlag_LimitedPowerSource_2;
-+
-+
-+	if (classification2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
-+		result |= PP_StateClassificationFlag_ULV;
-+
-+	if (classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
-+		result |= PP_StateClassificationFlag_UvdMVC;
-+
-+	return result;
-+}
-+
-+static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
-+						struct pp_power_state *ps,
-+							    uint8_t version,
-+			 const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info) {
-+	unsigned long rrr_index;
-+	unsigned long tmp;
-+
-+	ps->classification.ui_label = (le16_to_cpu(pnon_clock_info->usClassification) &
-+					ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
-+	ps->classification.flags = make_classification_flags(hwmgr,
-+				le16_to_cpu(pnon_clock_info->usClassification),
-+				le16_to_cpu(pnon_clock_info->usClassification2));
-+
-+	ps->classification.temporary_state = false;
-+	ps->classification.to_be_deleted = false;
-+	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+		ATOM_PPLIB_SINGLE_DISPLAY_ONLY;
-+
-+	ps->validation.singleDisplayOnly = (0 != tmp);
-+
-+	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+		ATOM_PPLIB_DISALLOW_ON_DC;
-+
-+	ps->validation.disallowOnDC = (0 != tmp);
-+
-+	ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+				ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
-+				ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
-+
-+	ps->pcie.lanes = 0;
-+
-+	ps->display.disableFrameModulation = false;
-+
-+	rrr_index = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+			ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK) >>
-+			ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT;
-+
-+	if (rrr_index != ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED) {
-+		static const uint8_t look_up[(ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK >> ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT) + 1] = \
-+								{ 0, 50, 0 };
-+
-+		ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;
-+		ps->display.explicitRefreshrate = look_up[rrr_index];
-+		ps->display.limitRefreshrate = true;
-+
-+		if (ps->display.explicitRefreshrate == 0)
-+			ps->display.limitRefreshrate = false;
-+	} else
-+		ps->display.limitRefreshrate = false;
-+
-+	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+		ATOM_PPLIB_ENABLE_VARIBRIGHT;
-+
-+	ps->display.enableVariBright = (0 != tmp);
-+
-+	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+		ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF;
-+
-+	ps->memory.dllOff = (0 != tmp);
-+
-+	ps->memory.m3arb = (uint8_t)(le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+						ATOM_PPLIB_M3ARB_MASK) >> ATOM_PPLIB_M3ARB_SHIFT;
-+
-+	ps->temperatures.min = PP_TEMPERATURE_UNITS_PER_CENTIGRADES *
-+				     pnon_clock_info->ucMinTemperature;
-+
-+	ps->temperatures.max = PP_TEMPERATURE_UNITS_PER_CENTIGRADES *
-+				     pnon_clock_info->ucMaxTemperature;
-+
-+	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+		ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING;
-+
-+	ps->software.disableLoadBalancing = tmp;
-+
-+	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+		ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS;
-+
-+	ps->software.enableSleepForTimestamps = (0 != tmp);
-+
-+	ps->validation.supportedPowerLevels = pnon_clock_info->ucRequiredPower;
-+
-+	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < version) {
-+		ps->uvd_clocks.VCLK = pnon_clock_info->ulVCLK;
-+		ps->uvd_clocks.DCLK = pnon_clock_info->ulDCLK;
-+	} else {
-+		ps->uvd_clocks.VCLK = 0;
-+		ps->uvd_clocks.DCLK = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static ULONG size_of_entry_v2(ULONG num_dpm_levels)
-+{
-+	return (sizeof(UCHAR) + sizeof(UCHAR) +
-+			(num_dpm_levels * sizeof(UCHAR)));
-+}
-+
-+static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
-+					const StateArray * pstate_arrays,
-+							 ULONG entry_index)
-+{
-+	ULONG i;
-+	const ATOM_PPLIB_STATE_V2 *pstate;
-+
-+	pstate = pstate_arrays->states;
-+	if (entry_index <= pstate_arrays->ucNumEntries) {
-+		for (i = 0; i < entry_index; i++)
-+			pstate = (ATOM_PPLIB_STATE_V2 *)(
-+						  (unsigned long)pstate +
-+			     size_of_entry_v2(pstate->ucNumDPMLevels));
-+	}
-+	return pstate;
-+}
-+
-+
-+static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
-+				     struct pp_hwmgr *hwmgr)
-+{
-+	const void *table_addr = NULL;
-+	uint8_t frev, crev;
-+	uint16_t size;
-+
-+	table_addr = cgs_atom_get_data_table(hwmgr->device,
-+			GetIndexIntoMasterTable(DATA, PowerPlayInfo),
-+			&size, &frev, &crev);
-+
-+	hwmgr->soft_pp_table = table_addr;
-+
-+	return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr;
-+}
-+
-+
-+int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
-+				     unsigned long *num_of_entries)
-+{
-+	const StateArray *pstate_arrays;
-+	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
-+
-+	if (powerplay_table == NULL)
-+		return -1;
-+
-+	if (powerplay_table->sHeader.ucTableFormatRevision >= 6) {
-+		pstate_arrays = (StateArray *)(((unsigned long)powerplay_table) +
-+					le16_to_cpu(powerplay_table->usStateArrayOffset));
-+
-+		*num_of_entries = (unsigned long)(pstate_arrays->ucNumEntries);
-+	} else
-+		*num_of_entries = (unsigned long)(powerplay_table->ucNumStates);
-+
-+	return 0;
-+}
-+
-+int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
-+				unsigned long entry_index,
-+				struct pp_power_state *ps,
-+			 pp_tables_hw_clock_info_callback func)
-+{
-+	int i;
-+	const StateArray *pstate_arrays;
-+	const ATOM_PPLIB_STATE_V2 *pstate_entry_v2;
-+	const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info;
-+	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
-+	int result = 0;
-+	int res = 0;
-+
-+	const ClockInfoArray *pclock_arrays;
-+
-+	const NonClockInfoArray *pnon_clock_arrays;
-+
-+	const ATOM_PPLIB_STATE *pstate_entry;
-+
-+	if (powerplay_table == NULL)
-+		return -1;
-+
-+	ps->classification.bios_index = entry_index;
-+
-+	if (powerplay_table->sHeader.ucTableFormatRevision >= 6) {
-+		pstate_arrays = (StateArray *)(((unsigned long)powerplay_table) +
-+					le16_to_cpu(powerplay_table->usStateArrayOffset));
-+
-+		if (entry_index > pstate_arrays->ucNumEntries)
-+			return -1;
-+
-+		pstate_entry_v2 = get_state_entry_v2(pstate_arrays, entry_index);
-+		pclock_arrays = (ClockInfoArray *)(((unsigned long)powerplay_table) +
-+					le16_to_cpu(powerplay_table->usClockInfoArrayOffset));
-+
-+		pnon_clock_arrays = (NonClockInfoArray *)(((unsigned long)powerplay_table) +
-+						le16_to_cpu(powerplay_table->usNonClockInfoArrayOffset));
-+
-+		pnon_clock_info = (ATOM_PPLIB_NONCLOCK_INFO *)((unsigned long)(pnon_clock_arrays->nonClockInfo) +
-+					(pstate_entry_v2->nonClockInfoIndex * pnon_clock_arrays->ucEntrySize));
-+
-+		result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info);
-+
-+		for (i = 0; i < pstate_entry_v2->ucNumDPMLevels; i++) {
-+			const void *pclock_info = (const void *)(
-+							(unsigned long)(pclock_arrays->clockInfo) +
-+							(pstate_entry_v2->clockInfoIndex[i] * pclock_arrays->ucEntrySize));
-+			res = func(hwmgr, &ps->hardware, i, pclock_info);
-+			if ((0 == result) && (0 != res))
-+				result = res;
-+		}
-+	} else {
-+		if (entry_index > powerplay_table->ucNumStates)
-+			return -1;
-+
-+		pstate_entry = (ATOM_PPLIB_STATE *)((unsigned long)powerplay_table + powerplay_table->usStateArrayOffset +
-+				entry_index * powerplay_table->ucStateEntrySize);
-+
-+		pnon_clock_info = (ATOM_PPLIB_NONCLOCK_INFO *)((unsigned long)powerplay_table +
-+						le16_to_cpu(powerplay_table->usNonClockInfoArrayOffset) +
-+						pstate_entry->ucNonClockStateIndex *
-+						powerplay_table->ucNonClockSize);
-+
-+		result = init_non_clock_fields(hwmgr, ps,
-+							powerplay_table->ucNonClockSize,
-+							pnon_clock_info);
-+
-+		for (i = 0; i < powerplay_table->ucStateEntrySize-1; i++) {
-+			const void *pclock_info = (const void *)((unsigned long)powerplay_table +
-+						le16_to_cpu(powerplay_table->usClockInfoArrayOffset) +
-+						pstate_entry->ucClockStateIndices[i] *
-+						powerplay_table->ucClockInfoSize);
-+
-+			int res = func(hwmgr, &ps->hardware, i, pclock_info);
-+
-+			if ((0 == result) && (0 != res))
-+					result = res;
-+		}
-+	}
-+
-+	if ((0 == result) &&
-+		(0 != (ps->classification.flags & PP_StateClassificationFlag_Boot)))
-+		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
-+
-+	return result;
-+}
-+
-+
-+
-+static int init_powerplay_tables(
-+			struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table
-+)
-+{
-+	return 0;
-+}
-+
-+
-+static int init_thermal_controller(
-+			struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	return 0;
-+}
-+
-+static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table,
-+			const ATOM_FIRMWARE_INFO_V1_4 *fw_info)
-+{
-+	hwmgr->platform_descriptor.overdriveLimit.engineClock =
-+				le32_to_cpu(fw_info->ulASICMaxEngineClock);
-+
-+	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
-+				le32_to_cpu(fw_info->ulASICMaxMemoryClock);
-+
-+	hwmgr->platform_descriptor.maxOverdriveVDDC =
-+		le32_to_cpu(fw_info->ul3DAccelerationEngineClock) & 0x7FF;
-+
-+	hwmgr->platform_descriptor.minOverdriveVDDC =
-+			   le16_to_cpu(fw_info->usBootUpVDDCVoltage);
-+
-+	hwmgr->platform_descriptor.maxOverdriveVDDC =
-+			   le16_to_cpu(fw_info->usBootUpVDDCVoltage);
-+
-+	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
-+	return 0;
-+}
-+
-+static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table,
-+			const ATOM_FIRMWARE_INFO_V2_1 *fw_info)
-+{
-+	const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3;
-+	const ATOM_PPLIB_EXTENDEDHEADER *header;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) <
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE3))
-+		return 0;
-+
-+	powerplay_table3 = (const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
-+
-+	if (0 == powerplay_table3->usExtendendedHeaderOffset)
-+		return 0;
-+
-+	header = (ATOM_PPLIB_EXTENDEDHEADER *)(((unsigned long) powerplay_table) +
-+			le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
-+
-+	hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock);
-+	hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock);
-+
-+
-+	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
-+	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
-+	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
-+
-+	return 0;
-+}
-+
-+static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	int result;
-+	uint8_t frev, crev;
-+	uint16_t size;
-+
-+	const ATOM_COMMON_TABLE_HEADER *fw_info = NULL;
-+
-+	hwmgr->platform_descriptor.overdriveLimit.engineClock = 0;
-+	hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0;
-+	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
-+	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
-+
-+	/* We assume here that fw_info is unchanged if this call fails.*/
-+	fw_info = cgs_atom_get_data_table(hwmgr->device,
-+			 GetIndexIntoMasterTable(DATA, FirmwareInfo),
-+			 &size, &frev, &crev);
-+
-+	if ((fw_info->ucTableFormatRevision == 1)
-+		&& (fw_info->usStructureSize >= sizeof(ATOM_FIRMWARE_INFO_V1_4)))
-+		result = init_overdrive_limits_V1_4(hwmgr,
-+				powerplay_table,
-+				(const ATOM_FIRMWARE_INFO_V1_4 *)fw_info);
-+
-+	else if ((fw_info->ucTableFormatRevision == 2)
-+		&& (fw_info->usStructureSize >= sizeof(ATOM_FIRMWARE_INFO_V2_1)))
-+		result = init_overdrive_limits_V2_1(hwmgr,
-+				powerplay_table,
-+				(const ATOM_FIRMWARE_INFO_V2_1 *)fw_info);
-+
-+	if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
-+		&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0
-+		&& !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_OverdriveDisabledByPowerBudget))
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ACOverdriveSupport);
-+
-+	return result;
-+}
-+
-+static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
-+		struct phm_uvd_clock_voltage_dependency_table **ptable,
-+		const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *table,
-+		const UVDClockInfoArray *array)
-+{
-+	unsigned long table_size, i;
-+	struct phm_uvd_clock_voltage_dependency_table *uvd_table;
-+
-+	table_size = sizeof(unsigned long) +
-+		 sizeof(struct phm_uvd_clock_voltage_dependency_table) *
-+		 table->numEntries;
-+
-+	uvd_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == uvd_table)
-+		return -ENOMEM;
-+
-+	uvd_table->count = table->numEntries;
-+
-+	for (i = 0; i < table->numEntries; i++) {
-+		const UVDClockInfo *entry =
-+			&array->entries[table->entries[i].ucUVDClockInfoIndex];
-+		uvd_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
-+		uvd_table->entries[i].vclk = ((unsigned long)entry->ucVClkHigh << 16)
-+					 | le16_to_cpu(entry->usVClkLow);
-+		uvd_table->entries[i].dclk = ((unsigned long)entry->ucDClkHigh << 16)
-+					 | le16_to_cpu(entry->usDClkLow);
-+	}
-+
-+	*ptable = uvd_table;
-+
-+	return 0;
-+}
-+
-+static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
-+		struct phm_vce_clock_voltage_dependency_table **ptable,
-+		const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table,
-+		const VCEClockInfoArray    *array)
-+{
-+	unsigned long table_size, i;
-+	struct phm_vce_clock_voltage_dependency_table *vce_table = NULL;
-+
-+	table_size = sizeof(unsigned long) +
-+			sizeof(struct phm_vce_clock_voltage_dependency_table)
-+			* table->numEntries;
-+
-+	vce_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == vce_table)
-+		return -ENOMEM;
-+
-+	vce_table->count = table->numEntries;
-+	for (i = 0; i < table->numEntries; i++) {
-+		const VCEClockInfo *entry = &array->entries[table->entries[i].ucVCEClockInfoIndex];
-+
-+		vce_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
-+		vce_table->entries[i].evclk = ((unsigned long)entry->ucEVClkHigh << 16)
-+					| le16_to_cpu(entry->usEVClkLow);
-+		vce_table->entries[i].ecclk = ((unsigned long)entry->ucECClkHigh << 16)
-+					| le16_to_cpu(entry->usECClkLow);
-+	}
-+
-+	*ptable = vce_table;
-+
-+	return 0;
-+}
-+
-+static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
-+		 struct phm_samu_clock_voltage_dependency_table **ptable,
-+		 const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *table)
-+{
-+	unsigned long table_size, i;
-+	struct phm_samu_clock_voltage_dependency_table *samu_table;
-+
-+	table_size = sizeof(unsigned long) +
-+		sizeof(struct phm_samu_clock_voltage_dependency_table) *
-+		table->numEntries;
-+
-+	samu_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == samu_table)
-+		return -ENOMEM;
-+
-+	samu_table->count = table->numEntries;
-+
-+	for (i = 0; i < table->numEntries; i++) {
-+		samu_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
-+		samu_table->entries[i].samclk = ((unsigned long)table->entries[i].ucSAMClockHigh << 16)
-+					 | le16_to_cpu(table->entries[i].usSAMClockLow);
-+	}
-+
-+	*ptable = samu_table;
-+
-+	return 0;
-+}
-+
-+static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
-+		struct phm_acp_clock_voltage_dependency_table **ptable,
-+		const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *table)
-+{
-+	unsigned table_size, i;
-+	struct phm_acp_clock_voltage_dependency_table *acp_table;
-+
-+	table_size = sizeof(unsigned long) +
-+		sizeof(struct phm_acp_clock_voltage_dependency_table) *
-+		table->numEntries;
-+
-+	acp_table = kzalloc(table_size, GFP_KERNEL);
-+	if (NULL == acp_table)
-+		return -ENOMEM;
-+
-+	acp_table->count = (unsigned long)table->numEntries;
-+
-+	for (i = 0; i < table->numEntries; i++) {
-+		acp_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
-+		acp_table->entries[i].acpclk = ((unsigned long)table->entries[i].ucACPClockHigh << 16)
-+					 | le16_to_cpu(table->entries[i].usACPClockLow);
-+	}
-+
-+	*ptable = acp_table;
-+
-+	return 0;
-+}
-+
-+static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	ATOM_PPLIB_Clock_Voltage_Dependency_Table *table;
-+	ATOM_PPLIB_Clock_Voltage_Limit_Table *limit_table;
-+	int result = 0;
-+
-+	uint16_t vce_clock_info_array_offset;
-+	uint16_t uvd_clock_info_array_offset;
-+	uint16_t table_offset;
-+
-+	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
-+	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
-+	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
-+	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-+	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
-+	hwmgr->dyn_state.vce_clocl_voltage_dependency_table = NULL;
-+	hwmgr->dyn_state.uvd_clocl_voltage_dependency_table = NULL;
-+	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
-+	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
-+	hwmgr->dyn_state.ppm_parameter_table = NULL;
-+	hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
-+
-+	vce_clock_info_array_offset = get_vce_clock_info_array_offset(
-+						hwmgr, powerplay_table);
-+	table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr,
-+						powerplay_table);
-+	if (vce_clock_info_array_offset > 0 && table_offset > 0) {
-+		const VCEClockInfoArray *array = (const VCEClockInfoArray *)
-+				(((unsigned long) powerplay_table) +
-+				vce_clock_info_array_offset);
-+		const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table =
-+				(const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
-+				(((unsigned long) powerplay_table) + table_offset);
-+		result = get_vce_clock_voltage_limit_table(hwmgr,
-+				&hwmgr->dyn_state.vce_clocl_voltage_dependency_table,
-+				table, array);
-+	}
-+
-+	uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table);
-+	table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
-+
-+	if (uvd_clock_info_array_offset > 0 && table_offset > 0) {
-+		const UVDClockInfoArray *array = (const UVDClockInfoArray *)
-+				(((unsigned long) powerplay_table) +
-+				uvd_clock_info_array_offset);
-+		const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *ptable =
-+				(const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
-+				(((unsigned long) powerplay_table) + table_offset);
-+		result = get_uvd_clock_voltage_limit_table(hwmgr,
-+				&hwmgr->dyn_state.uvd_clocl_voltage_dependency_table, ptable, array);
-+	}
-+
-+	table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,
-+							    powerplay_table);
-+
-+	if (table_offset > 0) {
-+		const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *ptable =
-+				(const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *)
-+				(((unsigned long) powerplay_table) + table_offset);
-+		result = get_samu_clock_voltage_limit_table(hwmgr,
-+				&hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable);
-+	}
-+
-+	table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr,
-+							     powerplay_table);
-+
-+	if (table_offset > 0) {
-+		const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *ptable =
-+				(const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *)
-+				(((unsigned long) powerplay_table) + table_offset);
-+		result = get_acp_clock_voltage_limit_table(hwmgr,
-+				&hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable);
-+	}
-+
-+	table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table);
-+	if (table_offset > 0) {
-+		UCHAR rev_id = *(UCHAR *)(((unsigned long)powerplay_table) + table_offset);
-+
-+		if (rev_id > 0) {
-+			const ATOM_PPLIB_POWERTUNE_Table_V1 *tune_table =
-+				(const ATOM_PPLIB_POWERTUNE_Table_V1 *)
-+				(((unsigned long) powerplay_table) + table_offset);
-+			result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table,
-+				&tune_table->power_tune_table,
-+				le16_to_cpu(tune_table->usMaximumPowerDeliveryLimit));
-+			hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
-+				le16_to_cpu(tune_table->usTjMax);
-+		} else {
-+			const ATOM_PPLIB_POWERTUNE_Table *tune_table =
-+				(const ATOM_PPLIB_POWERTUNE_Table *)
-+				(((unsigned long) powerplay_table) + table_offset);
-+			result = get_cac_tdp_table(hwmgr,
-+				&hwmgr->dyn_state.cac_dtp_table,
-+				&tune_table->power_tune_table, 255);
-+		}
-+	}
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+		sizeof(ATOM_PPLIB_POWERPLAYTABLE4)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE4 *)powerplay_table;
-+		if (0 != powerplay_table4->usVddcDependencyOnSCLKOffset) {
-+			table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
-+				(((unsigned long) powerplay_table4) +
-+				powerplay_table4->usVddcDependencyOnSCLKOffset);
-+			result = get_clock_voltage_dependency_table(hwmgr,
-+				&hwmgr->dyn_state.vddc_dependency_on_sclk, table);
-+		}
-+
-+		if (result == 0 && (0 != powerplay_table4->usVddciDependencyOnMCLKOffset)) {
-+			table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
-+				(((unsigned long) powerplay_table4) +
-+				powerplay_table4->usVddciDependencyOnMCLKOffset);
-+			result = get_clock_voltage_dependency_table(hwmgr,
-+				&hwmgr->dyn_state.vddci_dependency_on_mclk, table);
-+		}
-+
-+		if (result == 0 && (0 != powerplay_table4->usVddcDependencyOnMCLKOffset)) {
-+			table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
-+				(((unsigned long) powerplay_table4) +
-+				powerplay_table4->usVddcDependencyOnMCLKOffset);
-+			result = get_clock_voltage_dependency_table(hwmgr,
-+				&hwmgr->dyn_state.vddc_dependency_on_mclk, table);
-+		}
-+
-+		if (result == 0 && (0 != powerplay_table4->usMaxClockVoltageOnDCOffset)) {
-+			limit_table = (ATOM_PPLIB_Clock_Voltage_Limit_Table *)
-+				(((unsigned long) powerplay_table4) +
-+				powerplay_table4->usMaxClockVoltageOnDCOffset);
-+			result = get_clock_voltage_limit(hwmgr,
-+				&hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table);
-+		}
-+
-+		if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) &&
-+			(0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count))
-+			result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values,
-+					hwmgr->dyn_state.vddc_dependency_on_mclk);
-+
-+		if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) &&
-+			(0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count))
-+			result = get_valid_clk(hwmgr,
-+				&hwmgr->dyn_state.valid_sclk_values,
-+				hwmgr->dyn_state.vddc_dependency_on_sclk);
-+
-+		if (result == 0 && (0 != powerplay_table4->usMvddDependencyOnMCLKOffset)) {
-+			table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
-+				(((unsigned long) powerplay_table4) +
-+				powerplay_table4->usMvddDependencyOnMCLKOffset);
-+			result = get_clock_voltage_dependency_table(hwmgr,
-+				&hwmgr->dyn_state.mvdd_dependency_on_mclk, table);
-+		}
-+	}
-+
-+	table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr,
-+								powerplay_table);
-+
-+	if (table_offset > 0) {
-+		table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
-+			(((unsigned long) powerplay_table) + table_offset);
-+		result = get_clock_voltage_dependency_table(hwmgr,
-+			&hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table);
-+	}
-+
-+	return result;
-+}
-+
-+static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
-+				 struct phm_cac_leakage_table **ptable,
-+				const ATOM_PPLIB_CAC_Leakage_Table *table)
-+{
-+	struct phm_cac_leakage_table  *cac_leakage_table;
-+	unsigned long            table_size, i;
-+
-+	table_size = sizeof(ULONG) +
-+		(sizeof(struct phm_cac_leakage_table) * table->ucNumEntries);
-+
-+	cac_leakage_table = kzalloc(table_size, GFP_KERNEL);
-+
-+	cac_leakage_table->count = (ULONG)table->ucNumEntries;
-+
-+	for (i = 0; i < cac_leakage_table->count; i++) {
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EVV)) {
-+			cac_leakage_table->entries[i].Vddc1 = le16_to_cpu(table->entries[i].usVddc1);
-+			cac_leakage_table->entries[i].Vddc2 = le16_to_cpu(table->entries[i].usVddc2);
-+			cac_leakage_table->entries[i].Vddc3 = le16_to_cpu(table->entries[i].usVddc3);
-+		} else {
-+			cac_leakage_table->entries[i].Vddc    = le16_to_cpu(table->entries[i].usVddc);
-+			cac_leakage_table->entries[i].Leakage = le32_to_cpu(table->entries[i].ulLeakageValue);
-+		}
-+	}
-+
-+	*ptable = cac_leakage_table;
-+
-+	return 0;
-+}
-+
-+static int get_platform_power_management_table(struct pp_hwmgr *hwmgr,
-+			ATOM_PPLIB_PPM_Table *atom_ppm_table)
-+{
-+	struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_PPLIB_PPM_Table), GFP_KERNEL);
-+
-+	if (NULL == ptr)
-+		return -ENOMEM;
-+
-+	ptr->ppm_design            = atom_ppm_table->ucPpmDesign;
-+	ptr->cpu_core_number        = le16_to_cpu(atom_ppm_table->usCpuCoreNumber);
-+	ptr->platform_tdp          = le32_to_cpu(atom_ppm_table->ulPlatformTDP);
-+	ptr->small_ac_platform_tdp   = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP);
-+	ptr->platform_tdc          = le32_to_cpu(atom_ppm_table->ulPlatformTDC);
-+	ptr->small_ac_platform_tdc   = le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC);
-+	ptr->apu_tdp               = le32_to_cpu(atom_ppm_table->ulApuTDP);
-+	ptr->dgpu_tdp              = le32_to_cpu(atom_ppm_table->ulDGpuTDP);
-+	ptr->dgpu_ulv_power         = le32_to_cpu(atom_ppm_table->ulDGpuUlvPower);
-+	ptr->tj_max                = le32_to_cpu(atom_ppm_table->ulTjmax);
-+	hwmgr->dyn_state.ppm_parameter_table = ptr;
-+
-+	return 0;
-+}
-+
-+static int init_dpm2_parameters(struct pp_hwmgr *hwmgr,
-+			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	int result = 0;
-+
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE5)) {
-+		const  ATOM_PPLIB_POWERPLAYTABLE5 *ptable5 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE5 *)powerplay_table;
-+		const  ATOM_PPLIB_POWERPLAYTABLE4 *ptable4 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE4 *)
-+				(&ptable5->basicTable4);
-+		const  ATOM_PPLIB_POWERPLAYTABLE3 *ptable3 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE3 *)
-+				(&ptable4->basicTable3);
-+		const  ATOM_PPLIB_EXTENDEDHEADER  *extended_header;
-+		uint16_t table_offset;
-+		ATOM_PPLIB_PPM_Table *atom_ppm_table;
-+
-+		hwmgr->platform_descriptor.TDPLimit     = le32_to_cpu(ptable5->ulTDPLimit);
-+		hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit);
-+
-+		hwmgr->platform_descriptor.TDPODLimit   = le16_to_cpu(ptable5->usTDPODLimit);
-+		hwmgr->platform_descriptor.TDPAdjustment = 0;
-+
-+		hwmgr->platform_descriptor.VidAdjustment = 0;
-+		hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
-+		hwmgr->platform_descriptor.VidMinLimit     = 0;
-+		hwmgr->platform_descriptor.VidMaxLimit     = 1500000;
-+		hwmgr->platform_descriptor.VidStep         = 6250;
-+
-+		hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit);
-+
-+		if (hwmgr->platform_descriptor.TDPODLimit != 0)
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_PowerControl);
-+
-+		hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold);
-+
-+		hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage);
-+
-+		hwmgr->dyn_state.cac_leakage_table = NULL;
-+
-+		if (0 != ptable5->usCACLeakageTableOffset) {
-+			const ATOM_PPLIB_CAC_Leakage_Table *pCAC_leakage_table =
-+				(ATOM_PPLIB_CAC_Leakage_Table *)(((unsigned long)ptable5) +
-+				le16_to_cpu(ptable5->usCACLeakageTableOffset));
-+			result = get_cac_leakage_table(hwmgr,
-+				&hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table);
-+		}
-+
-+		hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope);
-+
-+		hwmgr->dyn_state.ppm_parameter_table = NULL;
-+
-+		if (0 != ptable3->usExtendendedHeaderOffset) {
-+			extended_header = (const ATOM_PPLIB_EXTENDEDHEADER *)
-+					(((unsigned long)powerplay_table) +
-+					le16_to_cpu(ptable3->usExtendendedHeaderOffset));
-+			if ((extended_header->usPPMTableOffset > 0) &&
-+				le16_to_cpu(extended_header->usSize) >=
-+				    SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) {
-+				table_offset = le16_to_cpu(extended_header->usPPMTableOffset);
-+				atom_ppm_table = (ATOM_PPLIB_PPM_Table *)
-+					(((unsigned long)powerplay_table) + table_offset);
-+				if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table))
-+					phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_EnablePlatformPowerManagement);
-+			}
-+		}
-+	}
-+	return result;
-+}
-+
-+static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
-+		const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
-+{
-+	if (le16_to_cpu(powerplay_table->usTableSize) >=
-+	    sizeof(ATOM_PPLIB_POWERPLAYTABLE4)) {
-+		const ATOM_PPLIB_POWERPLAYTABLE4 *powerplay_table4 =
-+				(const ATOM_PPLIB_POWERPLAYTABLE4 *)powerplay_table;
-+
-+		if (0 != powerplay_table4->usVddcPhaseShedLimitsTableOffset) {
-+			const ATOM_PPLIB_PhaseSheddingLimits_Table *ptable =
-+				(ATOM_PPLIB_PhaseSheddingLimits_Table *)
-+				(((unsigned long)powerplay_table4) +
-+				le16_to_cpu(powerplay_table4->usVddcPhaseShedLimitsTableOffset));
-+			struct phm_phase_shedding_limits_table *table;
-+			unsigned long size, i;
-+
-+
-+			size = sizeof(unsigned long) +
-+				(sizeof(struct phm_phase_shedding_limits_table) *
-+				ptable->ucNumEntries);
-+
-+			table = kzalloc(size, GFP_KERNEL);
-+
-+			table->count = (unsigned long)ptable->ucNumEntries;
-+
-+			for (i = 0; i < table->count; i++) {
-+				table->entries[i].Voltage = (unsigned long)le16_to_cpu(ptable->entries[i].usVoltage);
-+				table->entries[i].Sclk    = ((unsigned long)ptable->entries[i].ucSclkHigh << 16)
-+							| le16_to_cpu(ptable->entries[i].usSclkLow);
-+				table->entries[i].Mclk    = ((unsigned long)ptable->entries[i].ucMclkHigh << 16)
-+							| le16_to_cpu(ptable->entries[i].usMclkLow);
-+			}
-+			hwmgr->dyn_state.vddc_phase_shed_limits_table = table;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int get_number_of_vce_state_table_entries(
-+						  struct pp_hwmgr *hwmgr)
-+{
-+	const ATOM_PPLIB_POWERPLAYTABLE *table =
-+					     get_powerplay_table(hwmgr);
-+	const ATOM_PPLIB_VCE_State_Table *vce_table =
-+				    get_vce_state_table(hwmgr, table);
-+
-+	if (vce_table > 0)
-+		return vce_table->numEntries;
-+
-+	return 0;
-+}
-+
-+int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
-+							unsigned long i,
-+							struct PP_VCEState *vce_state,
-+							void **clock_info,
-+							unsigned long *flag)
-+{
-+	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
-+
-+	const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table);
-+
-+	unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_table);
-+
-+	const VCEClockInfoArray *vce_clock_info_array = (const VCEClockInfoArray *)(((unsigned long) powerplay_table) + vce_clock_info_array_offset);
-+
-+	const ClockInfoArray *clock_arrays = (ClockInfoArray *)(((unsigned long)powerplay_table) + powerplay_table->usClockInfoArrayOffset);
-+
-+	const ATOM_PPLIB_VCE_State_Record *record = &vce_state_table->entries[i];
-+
-+	const VCEClockInfo *vce_clock_info = &vce_clock_info_array->entries[record->ucVCEClockInfoIndex];
-+
-+	unsigned long clockInfoIndex = record->ucClockInfoIndex & 0x3F;
-+
-+	*flag = (record->ucClockInfoIndex >> NUM_BITS_CLOCK_INFO_ARRAY_INDEX);
-+
-+	vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | vce_clock_info->usEVClkLow;
-+	vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | vce_clock_info->usECClkLow;
-+
-+	*clock_info = (void *)((unsigned long)(clock_arrays->clockInfo) + (clockInfoIndex * clock_arrays->ucEntrySize));
-+
-+	return 0;
-+}
-+
-+
-+static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table;
-+
-+	powerplay_table = get_powerplay_table(hwmgr);
-+
-+	result = init_powerplay_tables(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = set_platform_caps(hwmgr,
-+				le32_to_cpu(powerplay_table->ulPlatformCaps));
-+
-+	if (0 == result)
-+		result = init_thermal_controller(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = init_overdrive_limits(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = init_clock_voltage_dependency(hwmgr,
-+						powerplay_table);
-+
-+	if (0 == result)
-+		result = init_dpm2_parameters(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = init_phase_shedding_table(hwmgr, powerplay_table);
-+
-+	return result;
-+}
-+
-+static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
-+{
-+	if (NULL != hwmgr->soft_pp_table) {
-+		kfree(hwmgr->soft_pp_table);
-+		hwmgr->soft_pp_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) {
-+		kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
-+		hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
-+		kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
-+		hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) {
-+		kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
-+		hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
-+		kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
-+		hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.valid_mclk_values) {
-+		kfree(hwmgr->dyn_state.valid_mclk_values);
-+		hwmgr->dyn_state.valid_mclk_values = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.valid_sclk_values) {
-+		kfree(hwmgr->dyn_state.valid_sclk_values);
-+		hwmgr->dyn_state.valid_sclk_values = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.cac_leakage_table) {
-+		kfree(hwmgr->dyn_state.cac_leakage_table);
-+		hwmgr->dyn_state.cac_leakage_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) {
-+		kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
-+		hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vce_clocl_voltage_dependency_table) {
-+		kfree(hwmgr->dyn_state.vce_clocl_voltage_dependency_table);
-+		hwmgr->dyn_state.vce_clocl_voltage_dependency_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.uvd_clocl_voltage_dependency_table) {
-+		kfree(hwmgr->dyn_state.uvd_clocl_voltage_dependency_table);
-+		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) {
-+		kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
-+		hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) {
-+		kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
-+		hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.cac_dtp_table) {
-+		kfree(hwmgr->dyn_state.cac_dtp_table);
-+		hwmgr->dyn_state.cac_dtp_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.ppm_parameter_table) {
-+		kfree(hwmgr->dyn_state.ppm_parameter_table);
-+		hwmgr->dyn_state.ppm_parameter_table = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) {
-+		kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
-+		hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
-+		kfree(hwmgr->dyn_state.vq_budgeting_table);
-+		hwmgr->dyn_state.vq_budgeting_table = NULL;
-+	}
-+
-+	return 0;
-+}
-+
-+const struct pp_table_func pptable_funcs = {
-+	.pptable_init = pp_tables_initialize,
-+	.pptable_fini = pp_tables_uninitialize,
-+	.pptable_get_number_of_vce_state_table_entries =
-+				get_number_of_vce_state_table_entries,
-+	.pptable_get_vce_state_table_entry =
-+						get_vce_state_table_entry,
-+};
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h
-new file mode 100644
-index 0000000..3043480
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ * Interface Functions related to the BIOS PowerPlay Tables.
-+ *
-+ */
-+
-+#ifndef PROCESSPPTABLES_H
-+#define PROCESSPPTABLES_H
-+
-+struct pp_hwmgr;
-+struct pp_power_state;
-+struct pp_hw_power_state;
-+
-+extern const struct pp_table_func pptable_funcs;
-+
-+typedef int (*pp_tables_hw_clock_info_callback)(struct pp_hwmgr *hwmgr,
-+					struct pp_hw_power_state *hw_ps,
-+							unsigned int index,
-+						 const void *clock_info);
-+
-+int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
-+				     unsigned long *num_of_entries);
-+
-+int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
-+						unsigned long entry_index,
-+						struct pp_power_state *ps,
-+				pp_tables_hw_clock_info_callback func);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 09d9d5a..2281d88 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -28,7 +28,6 @@
- #include "amd_shared.h"
- #include "cgs_common.h"
- 
--
- enum amd_pp_event {
- 	AMD_PP_EVENT_INITIALIZE = 0,
- 	AMD_PP_EVENT_UNINITIALIZE,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-new file mode 100644
-index 0000000..26e1256
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -0,0 +1,280 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _HARDWARE_MANAGER_H_
-+#define _HARDWARE_MANAGER_H_
-+
-+struct pp_hwmgr;
-+
-+/* Automatic Power State Throttling */
-+enum PHM_AutoThrottleSource
-+{
-+    PHM_AutoThrottleSource_Thermal,
-+    PHM_AutoThrottleSource_External
-+};
-+
-+typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
-+
-+enum phm_platform_caps {
-+	PHM_PlatformCaps_AtomBiosPpV1 = 0,
-+	PHM_PlatformCaps_PowerPlaySupport,
-+	PHM_PlatformCaps_ACOverdriveSupport,
-+	PHM_PlatformCaps_BacklightSupport,
-+	PHM_PlatformCaps_ThermalController,
-+	PHM_PlatformCaps_BiosPowerSourceControl,
-+	PHM_PlatformCaps_DisableVoltageTransition,
-+	PHM_PlatformCaps_DisableEngineTransition,
-+	PHM_PlatformCaps_DisableMemoryTransition,
-+	PHM_PlatformCaps_DynamicPowerManagement,
-+	PHM_PlatformCaps_EnableASPML0s,
-+	PHM_PlatformCaps_EnableASPML1,
-+	PHM_PlatformCaps_OD5inACSupport,
-+	PHM_PlatformCaps_OD5inDCSupport,
-+	PHM_PlatformCaps_SoftStateOD5,
-+	PHM_PlatformCaps_NoOD5Support,
-+	PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
-+	PHM_PlatformCaps_ActivityReporting,
-+	PHM_PlatformCaps_EnableBackbias,
-+	PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
-+	PHM_PlatformCaps_ShowPowerBudgetWarning,
-+	PHM_PlatformCaps_PowerBudgetWaiverAvailable,
-+	PHM_PlatformCaps_GFXClockGatingSupport,
-+	PHM_PlatformCaps_MMClockGatingSupport,
-+	PHM_PlatformCaps_AutomaticDCTransition,
-+	PHM_PlatformCaps_GeminiPrimary,
-+	PHM_PlatformCaps_MemorySpreadSpectrumSupport,
-+	PHM_PlatformCaps_EngineSpreadSpectrumSupport,
-+	PHM_PlatformCaps_StepVddc,
-+	PHM_PlatformCaps_DynamicPCIEGen2Support,
-+	PHM_PlatformCaps_SMC,
-+	PHM_PlatformCaps_FaultyInternalThermalReading,          /* Internal thermal controller reports faulty temperature value when DAC2 is active */
-+	PHM_PlatformCaps_EnableVoltageControl,                  /* indicates voltage can be controlled */
-+	PHM_PlatformCaps_EnableSideportControl,                 /* indicates Sideport can be controlled */
-+	PHM_PlatformCaps_VideoPlaybackEEUNotification,          /* indicates EEU notification of video start/stop is required */
-+	PHM_PlatformCaps_TurnOffPll_ASPML1,                     /* PCIE Turn Off PLL in ASPM L1 */
-+	PHM_PlatformCaps_EnableHTLinkControl,                   /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */
-+	PHM_PlatformCaps_PerformanceStateOnly,                  /* indicates only performance power state to be used on current system. */
-+	PHM_PlatformCaps_ExclusiveModeAlwaysHigh,               /* In Exclusive (3D) mode always stay in High state. */
-+	PHM_PlatformCaps_DisableMGClockGating,                  /* to disable Medium Grain Clock Gating or not */
-+	PHM_PlatformCaps_DisableMGCGTSSM,                       /* TO disable Medium Grain Clock Gating Shader Complex control */
-+	PHM_PlatformCaps_UVDAlwaysHigh,                         /* In UVD mode always stay in High state */
-+	PHM_PlatformCaps_DisablePowerGating,                    /* to disable power gating */
-+	PHM_PlatformCaps_CustomThermalPolicy,                   /* indicates only performance power state to be used on current system. */
-+	PHM_PlatformCaps_StayInBootState,                       /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
-+	PHM_PlatformCaps_SMCAllowSeparateSWThermalState,        /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
-+	PHM_PlatformCaps_MultiUVDStateSupport,                  /* Powerplay state table supports multi UVD states. */
-+	PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,             /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
-+	PHM_PlatformCaps_EnableMCUHTLinkControl,                /* Enable HT link control by MCU */
-+	PHM_PlatformCaps_ABM,                                   /* ABM support.*/
-+	PHM_PlatformCaps_KongThermalPolicy,                     /* A thermal policy specific for Kong */
-+	PHM_PlatformCaps_SwitchVDDNB,                           /* if the users want to switch VDDNB */
-+	PHM_PlatformCaps_ULPS,                                  /* support ULPS mode either through ACPI state or ULPS state */
-+	PHM_PlatformCaps_NativeULPS,                            /* hardware capable of ULPS state (other than through the ACPI state) */
-+	PHM_PlatformCaps_EnableMVDDControl,                     /* indicates that memory voltage can be controlled */
-+	PHM_PlatformCaps_ControlVDDCI,                          /* Control VDDCI separately from VDDC. */
-+	PHM_PlatformCaps_DisableDCODT,                          /* indicates if DC ODT apply or not */
-+	PHM_PlatformCaps_DynamicACTiming,                       /* if the SMC dynamically re-programs MC SEQ register values */
-+	PHM_PlatformCaps_EnableThermalIntByGPIO,                /* enable throttle control through GPIO */
-+	PHM_PlatformCaps_BootStateOnAlert,                      /* Go to boot state on alerts, e.g. on an AC->DC transition. */
-+	PHM_PlatformCaps_DontWaitForVBlankOnAlert,              /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
-+	PHM_PlatformCaps_Force3DClockSupport,                   /* indicates if the platform supports force 3D clock. */
-+	PHM_PlatformCaps_MicrocodeFanControl,                   /* Fan is controlled by the SMC microcode. */
-+	PHM_PlatformCaps_AdjustUVDPriorityForSP,
-+	PHM_PlatformCaps_DisableLightSleep,                     /* Light sleep for evergreen family. */
-+	PHM_PlatformCaps_DisableMCLS,                           /* MC Light sleep */
-+	PHM_PlatformCaps_RegulatorHot,                          /* Enable throttling on 'regulator hot' events. */
-+	PHM_PlatformCaps_BACO,                                  /* Support Bus Alive Chip Off mode */
-+	PHM_PlatformCaps_DisableDPM,                            /* Disable DPM, supported from Llano */
-+	PHM_PlatformCaps_DynamicM3Arbiter,                      /* support dynamically change m3 arbitor parameters */
-+	PHM_PlatformCaps_SclkDeepSleep,                         /* support sclk deep sleep */
-+	PHM_PlatformCaps_DynamicPatchPowerState,                /* this ASIC supports to patch power state dynamically */
-+	PHM_PlatformCaps_ThermalAutoThrottling,                 /* enabling auto thermal throttling, */
-+	PHM_PlatformCaps_SumoThermalPolicy,                     /* A thermal policy specific for Sumo */
-+	PHM_PlatformCaps_PCIEPerformanceRequest,                /* support to change RC voltage */
-+	PHM_PlatformCaps_BLControlledByGPU,                     /* support varibright */
-+	PHM_PlatformCaps_PowerContainment,                      /* support DPM2 power containment (AKA TDP clamping) */
-+	PHM_PlatformCaps_SQRamping,                             /* support DPM2 SQ power throttle */
-+	PHM_PlatformCaps_CAC,                                   /* support Capacitance * Activity power estimation */
-+	PHM_PlatformCaps_NIChipsets,                            /* Northern Island and beyond chipsets */
-+	PHM_PlatformCaps_TrinityChipsets,                       /* Trinity chipset */
-+	PHM_PlatformCaps_EvergreenChipsets,                     /* Evergreen family chipset */
-+	PHM_PlatformCaps_PowerControl,                          /* Cayman and beyond chipsets */
-+	PHM_PlatformCaps_DisableLSClockGating,                  /* to disable Light Sleep control for HDP memories */
-+	PHM_PlatformCaps_BoostState,                            /* this ASIC supports boost state */
-+	PHM_PlatformCaps_UserMaxClockForMultiDisplays,          /* indicates if max memory clock is used for all status when multiple displays are connected */
-+	PHM_PlatformCaps_RegWriteDelay,                         /* indicates if back to back reg write delay is required */
-+	PHM_PlatformCaps_NonABMSupportInPPLib,                  /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
-+	PHM_PlatformCaps_GFXDynamicMGPowerGating,               /* Enable Dynamic MG PowerGating on Trinity */
-+	PHM_PlatformCaps_DisableSMUUVDHandshake,                /* Disable SMU UVD Handshake */
-+	PHM_PlatformCaps_DTE,                                   /* Support Digital Temperature Estimation */
-+	PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,            /* This is for the feature requested by David B., and Tonny W.*/
-+	PHM_PlatformCaps_UVDPowerGating,                        /* enable UVD power gating, supported from Llano */
-+	PHM_PlatformCaps_UVDDynamicPowerGating,                 /* enable UVD Dynamic power gating, supported from UVD5 */
-+	PHM_PlatformCaps_VCEPowerGating,                        /* Enable VCE power gating, supported for TN and later ASICs */
-+	PHM_PlatformCaps_SamuPowerGating,                       /* Enable SAMU power gating, supported for KV and later ASICs */
-+	PHM_PlatformCaps_UVDDPM,                                /* UVD clock DPM */
-+	PHM_PlatformCaps_VCEDPM,                                /* VCE clock DPM */
-+	PHM_PlatformCaps_SamuDPM,                               /* SAMU clock DPM */
-+	PHM_PlatformCaps_AcpDPM,                                /* ACP clock DPM */
-+	PHM_PlatformCaps_SclkDeepSleepAboveLow,                 /* Enable SCLK Deep Sleep on all DPM states */
-+	PHM_PlatformCaps_DynamicUVDState,                       /* Dynamic UVD State */
-+	PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
-+	PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,            /* Set UVD Clk With Dummy Back End */
-+	PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,            /* Set VCE Clk With Dummy Back End */
-+	PHM_PlatformCaps_WantACPClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
-+	PHM_PlatformCaps_OD6inACSupport,                        /* indicates that the ASIC/back end supports OD6 */
-+	PHM_PlatformCaps_OD6inDCSupport,                        /* indicates that the ASIC/back end supports OD6 in DC */
-+	PHM_PlatformCaps_EnablePlatformPowerManagement,         /* indicates that Platform Power Management feature is supported */
-+	PHM_PlatformCaps_SurpriseRemoval,                       /* indicates that surprise removal feature is requested */
-+	PHM_PlatformCaps_NewCACVoltage,                         /* indicates new CAC voltage table support */
-+	PHM_PlatformCaps_DBRamping,                             /* for dI/dT feature */
-+	PHM_PlatformCaps_TDRamping,                             /* for dI/dT feature */
-+	PHM_PlatformCaps_TCPRamping,                            /* for dI/dT feature */
-+	PHM_PlatformCaps_EnableSMU7ThermalManagement,           /* SMC will manage thermal events */
-+	PHM_PlatformCaps_FPS,                                   /* FPS support */
-+	PHM_PlatformCaps_ACP,                                   /* ACP support */
-+	PHM_PlatformCaps_SclkThrottleLowNotification,           /* SCLK Throttle Low Notification */
-+	PHM_PlatformCaps_XDMAEnabled,                           /* XDMA engine is enabled */
-+	PHM_PlatformCaps_UseDummyBackEnd,                       /* use dummy back end */
-+	PHM_PlatformCaps_EnableDFSBypass,                       /* Enable DFS bypass */
-+	PHM_PlatformCaps_VddNBDirectRequest,
-+	PHM_PlatformCaps_PauseMMSessions,
-+	PHM_PlatformCaps_UnTabledHardwareInterface,             /* Tableless/direct call hardware interface for CI and newer ASICs */
-+	PHM_PlatformCaps_SMU7,                                  /* indicates that vpuRecoveryBegin without SMU shutdown */
-+	PHM_PlatformCaps_RevertGPIO5Polarity,                   /* indicates revert GPIO5 plarity table support */
-+	PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
-+	PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
-+	PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
-+	PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
-+	PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
-+	PHM_PlatformCaps_IOIC3,
-+	PHM_PlatformCaps_ConnectedStandby,
-+	PHM_PlatformCaps_EVV,
-+	PHM_PlatformCaps_EnableLongIdleBACOSupport,
-+	PHM_PlatformCaps_CombinePCCWithThermalSignal,
-+	PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
-+	PHM_PlatformCaps_StablePState,
-+	PHM_PlatformCaps_OD6PlusinACSupport,
-+	PHM_PlatformCaps_OD6PlusinDCSupport,
-+	PHM_PlatformCaps_ODThermalLimitUnlock,
-+	PHM_PlatformCaps_ReducePowerLimit,
-+	PHM_PlatformCaps_ODFuzzyFanControlSupport,
-+	PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
-+	PHM_PlatformCaps_ControlVDDGFX,
-+	PHM_PlatformCaps_BBBSupported,
-+	PHM_PlatformCaps_DisableVoltageIsland,
-+	PHM_PlatformCaps_FanSpeedInTableIsRPM,
-+	PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
-+	PHM_PlatformCaps_IcelandULPSSWWorkAround,
-+	PHM_PlatformCaps_FPSEnhancement,
-+	PHM_PlatformCaps_LoadPostProductionFirmware,
-+	PHM_PlatformCaps_VpuRecoveryInProgress,
-+	PHM_PlatformCaps_Falcon_QuickTransition,
-+	PHM_PlatformCaps_AVFS,
-+	PHM_PlatformCaps_ClockStretcher,
-+	PHM_PlatformCaps_TablelessHardwareInterface,
-+	PHM_PlatformCaps_EnableDriverEVV,
-+	PHM_PlatformCaps_Max
-+};
-+
-+#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
-+
-+/* Number of uint32_t entries used by CAPS table */
-+#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
-+	((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
-+
-+struct pp_hw_descriptor {
-+	uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
-+};
-+
-+/* Function for setting a platform cap */
-+static inline void phm_cap_set(uint32_t *caps,
-+			enum phm_platform_caps c)
-+{
-+	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
-+			     (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
-+}
-+
-+static inline void phm_cap_unset(uint32_t *caps,
-+			enum phm_platform_caps c)
-+{
-+	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
-+}
-+
-+static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
-+{
-+	return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
-+		  (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
-+}
-+
-+enum phm_clock_Type {
-+	PHM_DispClock = 1,
-+	PHM_SClock,
-+	PHM_MemClock
-+};
-+
-+#define MAX_NUM_CLOCKS 16
-+
-+struct PP_Clocks {
-+	uint32_t engineClock;
-+	uint32_t memoryClock;
-+	uint32_t BusBandwidth;
-+	uint32_t engineClockInSR;
-+};
-+
-+struct phm_platform_descriptor {
-+	uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
-+	uint32_t vbiosInterruptId;
-+	struct PP_Clocks overdriveLimit;
-+	struct PP_Clocks clockStep;
-+	uint32_t hardwareActivityPerformanceLevels;
-+	uint32_t minimumClocksReductionPercentage;
-+	uint32_t minOverdriveVDDC;
-+	uint32_t maxOverdriveVDDC;
-+	uint32_t overdriveVDDCStep;
-+	uint32_t hardwarePerformanceLevels;
-+	uint16_t powerBudget;
-+	uint32_t TDPLimit;
-+	uint32_t nearTDPLimit;
-+	uint32_t nearTDPLimitAdjusted;
-+	uint32_t SQRampingThreshold;
-+	uint32_t CACLeakage;
-+	uint16_t TDPODLimit;
-+	uint32_t TDPAdjustment;
-+	bool TDPAdjustmentPolarity;
-+	uint16_t LoadLineSlope;
-+	uint32_t  VidMinLimit;
-+	uint32_t  VidMaxLimit;
-+	uint32_t  VidStep;
-+	uint32_t  VidAdjustment;
-+	bool VidAdjustmentPolarity;
-+};
-+
-+struct phm_clocks {
-+	uint32_t num_of_entries;
-+	uint32_t clock[MAX_NUM_CLOCKS];
-+};
-+
-+extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
-+extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
-+extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
-+#endif /* _HARDWARE_MANAGER_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-new file mode 100644
-index 0000000..07fba41
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -0,0 +1,607 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _HWMGR_H_
-+#define _HWMGR_H_
-+
-+#include "amd_powerplay.h"
-+#include "pp_instance.h"
-+#include "hardwaremanager.h"
-+#include "pp_power_source.h"
-+
-+struct pp_instance;
-+struct pp_hwmgr;
-+struct pp_hw_power_state;
-+struct pp_power_state;
-+struct PP_VCEState;
-+
-+enum PP_Result {
-+	PP_Result_TableImmediateExit = 0x13,
-+};
-+
-+#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
-+#define PCIE_PERF_REQ_FORCE_LOWPOWER    1
-+#define PCIE_PERF_REQ_GEN1         2
-+#define PCIE_PERF_REQ_GEN2         3
-+#define PCIE_PERF_REQ_GEN3         4
-+
-+enum PHM_BackEnd_Magic {
-+	PHM_Dummy_Magic       = 0xAA5555AA,
-+	PHM_RV770_Magic       = 0xDCBAABCD,
-+	PHM_Kong_Magic        = 0x239478DF,
-+	PHM_NIslands_Magic    = 0x736C494E,
-+	PHM_Sumo_Magic        = 0x8339FA11,
-+	PHM_SIslands_Magic    = 0x369431AC,
-+	PHM_Trinity_Magic     = 0x96751873,
-+	PHM_CIslands_Magic    = 0x38AC78B0,
-+	PHM_Kv_Magic          = 0xDCBBABC0,
-+	PHM_VIslands_Magic    = 0x20130307,
-+	PHM_Cz_Magic          = 0x67DCBA25
-+};
-+
-+enum PP_DAL_POWERLEVEL {
-+	PP_DAL_POWERLEVEL_INVALID = 0,
-+	PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_PERFORMANCE,
-+
-+	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
-+	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
-+	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
-+	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
-+	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-+};
-+
-+#define PHM_PCIE_POWERGATING_TARGET_GFX            0
-+#define PHM_PCIE_POWERGATING_TARGET_DDI            1
-+#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
-+#define PHM_PCIE_POWERGATING_TARGET_PHY            3
-+
-+typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
-+				  void *output, void *storage, int result);
-+
-+typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
-+
-+struct phm_acp_arbiter {
-+	uint32_t acpclk;
-+};
-+
-+struct phm_uvd_arbiter {
-+	uint32_t vclk;
-+	uint32_t dclk;
-+	uint32_t vclk_ceiling;
-+	uint32_t dclk_ceiling;
-+};
-+
-+struct phm_vce_arbiter {
-+	uint32_t   evclk;
-+	uint32_t   ecclk;
-+};
-+
-+struct phm_gfx_arbiter {
-+	uint32_t sclk;
-+	uint32_t mclk;
-+	uint32_t sclk_over_drive;
-+	uint32_t mclk_over_drive;
-+	uint32_t sclk_threshold;
-+	uint32_t num_cus;
-+};
-+
-+/* Entries in the master tables */
-+struct phm_master_table_item {
-+	phm_check_function isFunctionNeededInRuntimeTable;
-+	phm_table_function tableFunction;
-+};
-+
-+enum phm_master_table_flag {
-+	PHM_MasterTableFlag_None         = 0,
-+	PHM_MasterTableFlag_ExitOnError  = 1,
-+};
-+
-+/* The header of the master tables */
-+struct phm_master_table_header {
-+	uint32_t storage_size;
-+	uint32_t flags;
-+	struct phm_master_table_item *master_list;
-+};
-+
-+struct phm_runtime_table_header {
-+	uint32_t storage_size;
-+	bool exit_error;
-+	phm_table_function *function_list;
-+};
-+
-+struct phm_clock_array {
-+	uint32_t count;
-+	uint32_t values[1];
-+};
-+
-+struct phm_clock_voltage_dependency_record {
-+	uint32_t clk;
-+	uint32_t v;
-+};
-+
-+struct phm_vceclock_voltage_dependency_record {
-+	uint32_t ecclk;
-+	uint32_t evclk;
-+	uint32_t v;
-+};
-+
-+struct phm_uvdclock_voltage_dependency_record {
-+	uint32_t vclk;
-+	uint32_t dclk;
-+	uint32_t v;
-+};
-+
-+struct phm_samuclock_voltage_dependency_record {
-+	uint32_t samclk;
-+	uint32_t v;
-+};
-+
-+struct phm_acpclock_voltage_dependency_record {
-+	uint32_t acpclk;
-+	uint32_t v;
-+};
-+
-+struct phm_clock_voltage_dependency_table {
-+	uint32_t count;										/* Number of entries. */
-+	struct phm_clock_voltage_dependency_record entries[1];		/* Dynamically allocate count entries. */
-+};
-+
-+struct phm_phase_shedding_limits_record {
-+	uint32_t  Voltage;
-+	uint32_t    Sclk;
-+	uint32_t    Mclk;
-+};
-+
-+
-+extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
-+			      struct phm_runtime_table_header *rt_table,
-+			      void *input, void *output);
-+
-+extern int phm_construct_table(struct pp_hwmgr *hwmgr,
-+			       struct phm_master_table_header *master_table,
-+			       struct phm_runtime_table_header *rt_table);
-+
-+extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
-+			     struct phm_runtime_table_header *rt_table);
-+
-+
-+struct phm_uvd_clock_voltage_dependency_record {
-+	uint32_t vclk;
-+	uint32_t dclk;
-+	uint32_t v;
-+};
-+
-+struct phm_uvd_clock_voltage_dependency_table {
-+	uint8_t count;
-+	struct phm_uvd_clock_voltage_dependency_record entries[1];
-+};
-+
-+struct phm_acp_clock_voltage_dependency_record {
-+	uint32_t acpclk;
-+	uint32_t v;
-+};
-+
-+struct phm_acp_clock_voltage_dependency_table {
-+	uint32_t count;
-+	struct phm_acp_clock_voltage_dependency_record entries[1];
-+};
-+
-+struct phm_vce_clock_voltage_dependency_record {
-+	uint32_t ecclk;
-+	uint32_t evclk;
-+	uint32_t v;
-+};
-+
-+struct phm_phase_shedding_limits_table {
-+	uint32_t                           count;
-+	struct phm_phase_shedding_limits_record  entries[1];
-+};
-+
-+struct phm_vceclock_voltage_dependency_table {
-+	uint8_t count;                                    /* Number of entries. */
-+	struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
-+};
-+
-+struct phm_uvdclock_voltage_dependency_table {
-+	uint8_t count;                                    /* Number of entries. */
-+	struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
-+};
-+
-+struct phm_samuclock_voltage_dependency_table {
-+	uint8_t count;                                    /* Number of entries. */
-+	struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
-+};
-+
-+struct phm_acpclock_voltage_dependency_table {
-+	uint32_t count;                                    /* Number of entries. */
-+	struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
-+};
-+
-+struct phm_vce_clock_voltage_dependency_table {
-+	uint8_t count;
-+	struct phm_vce_clock_voltage_dependency_record entries[1];
-+};
-+
-+struct pp_hwmgr_func {
-+	int (*backend_init)(struct pp_hwmgr *hw_mgr);
-+	int (*backend_fini)(struct pp_hwmgr *hw_mgr);
-+	int (*asic_setup)(struct pp_hwmgr *hw_mgr);
-+	int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
-+	int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, enum amd_dpm_forced_level level);
-+	int (*dynamic_state_management_enable)(struct pp_hwmgr *hw_mgr);
-+	int (*patch_boot_state)(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps);
-+	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, unsigned long, struct pp_power_state *);
-+	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
-+};
-+
-+struct pp_table_func {
-+	int (*pptable_init)(struct pp_hwmgr *hw_mgr);
-+	int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
-+	int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
-+	int (*pptable_get_vce_state_table_entry)(
-+						struct pp_hwmgr *hwmgr,
-+						unsigned long i,
-+						struct PP_VCEState *vce_state,
-+						void **clock_info,
-+						unsigned long *flag);
-+};
-+
-+union phm_cac_leakage_record {
-+	struct {
-+		uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
-+		uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
-+	};
-+	struct {
-+		uint16_t Vddc1;
-+		uint16_t Vddc2;
-+		uint16_t Vddc3;
-+	};
-+};
-+
-+struct phm_cac_leakage_table {
-+	uint32_t count;
-+	union phm_cac_leakage_record entries[1];
-+};
-+
-+struct phm_samu_clock_voltage_dependency_record {
-+	uint32_t samclk;
-+	uint32_t v;
-+};
-+
-+
-+struct phm_samu_clock_voltage_dependency_table {
-+	uint8_t count;
-+	struct phm_samu_clock_voltage_dependency_record entries[1];
-+};
-+
-+struct phm_cac_tdp_table {
-+	uint16_t usTDP;
-+	uint16_t usConfigurableTDP;
-+	uint16_t usTDC;
-+	uint16_t usBatteryPowerLimit;
-+	uint16_t usSmallPowerLimit;
-+	uint16_t usLowCACLeakage;
-+	uint16_t usHighCACLeakage;
-+	uint16_t usMaximumPowerDeliveryLimit;
-+	uint16_t usOperatingTempMinLimit;
-+	uint16_t usOperatingTempMaxLimit;
-+	uint16_t usOperatingTempStep;
-+	uint16_t usOperatingTempHyst;
-+	uint16_t usDefaultTargetOperatingTemp;
-+	uint16_t usTargetOperatingTemp;
-+	uint16_t usPowerTuneDataSetID;
-+	uint16_t usSoftwareShutdownTemp;
-+	uint16_t usClockStretchAmount;
-+	uint16_t usTemperatureLimitHotspot;
-+	uint16_t usTemperatureLimitLiquid1;
-+	uint16_t usTemperatureLimitLiquid2;
-+	uint16_t usTemperatureLimitVrVddc;
-+	uint16_t usTemperatureLimitVrMvdd;
-+	uint16_t usTemperatureLimitPlx;
-+	uint8_t  ucLiquid1_I2C_address;
-+	uint8_t  ucLiquid2_I2C_address;
-+	uint8_t  ucLiquid_I2C_Line;
-+	uint8_t  ucVr_I2C_address;
-+	uint8_t  ucVr_I2C_Line;
-+	uint8_t  ucPlx_I2C_address;
-+	uint8_t  ucPlx_I2C_Line;
-+};
-+
-+struct phm_ppm_table {
-+	uint8_t   ppm_design;
-+	uint16_t  cpu_core_number;
-+	uint32_t  platform_tdp;
-+	uint32_t  small_ac_platform_tdp;
-+	uint32_t  platform_tdc;
-+	uint32_t  small_ac_platform_tdc;
-+	uint32_t  apu_tdp;
-+	uint32_t  dgpu_tdp;
-+	uint32_t  dgpu_ulv_power;
-+	uint32_t  tj_max;
-+};
-+
-+struct phm_vq_budgeting_record {
-+	uint32_t ulCUs;
-+	uint32_t ulSustainableSOCPowerLimitLow;
-+	uint32_t ulSustainableSOCPowerLimitHigh;
-+	uint32_t ulMinSclkLow;
-+	uint32_t ulMinSclkHigh;
-+	uint8_t  ucDispConfig;
-+	uint32_t ulDClk;
-+	uint32_t ulEClk;
-+	uint32_t ulSustainableSclk;
-+	uint32_t ulSustainableCUs;
-+};
-+
-+struct phm_vq_budgeting_table {
-+	uint8_t numEntries;
-+	struct phm_vq_budgeting_record entries[1];
-+};
-+
-+struct phm_clock_and_voltage_limits {
-+	uint32_t sclk;
-+	uint32_t mclk;
-+	uint16_t vddc;
-+	uint16_t vddci;
-+	uint16_t vddgfx;
-+};
-+
-+
-+
-+struct phm_dynamic_state_info {
-+	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
-+	struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
-+	struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
-+	struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
-+	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
-+	struct phm_clock_array                    *valid_sclk_values;
-+	struct phm_clock_array                    *valid_mclk_values;
-+	struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
-+	struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
-+	uint32_t                                  mclk_sclk_ratio;
-+	uint32_t                                  sclk_mclk_delta;
-+	uint32_t                                  vddc_vddci_delta;
-+	uint32_t                                  min_vddc_for_pcie_gen2;
-+	struct phm_cac_leakage_table              *cac_leakage_table;
-+	struct phm_phase_shedding_limits_table	  *vddc_phase_shed_limits_table;
-+
-+	struct phm_vce_clock_voltage_dependency_table
-+					    *vce_clocl_voltage_dependency_table;
-+	struct phm_uvd_clock_voltage_dependency_table
-+					    *uvd_clocl_voltage_dependency_table;
-+	struct phm_acp_clock_voltage_dependency_table
-+					    *acp_clock_voltage_dependency_table;
-+	struct phm_samu_clock_voltage_dependency_table
-+					   *samu_clock_voltage_dependency_table;
-+
-+	struct phm_ppm_table                          *ppm_parameter_table;
-+	struct phm_cac_tdp_table                      *cac_dtp_table;
-+	struct phm_clock_voltage_dependency_table	  *vdd_gfx_dependency_on_sclk;
-+	struct phm_vq_budgeting_table		  		  *vq_budgeting_table;
-+};
-+
-+struct pp_hwmgr {
-+	uint32_t chip_family;
-+	uint32_t chip_id;
-+	uint32_t hw_revision;
-+	uint32_t sub_sys_id;
-+	uint32_t sub_vendor_id;
-+
-+	void *device;
-+	struct pp_smumgr *smumgr;
-+	const void *soft_pp_table;
-+	enum amd_dpm_forced_level dpm_level;
-+
-+	struct phm_gfx_arbiter gfx_arbiter;
-+	struct phm_acp_arbiter acp_arbiter;
-+	struct phm_uvd_arbiter uvd_arbiter;
-+	struct phm_vce_arbiter vce_arbiter;
-+	uint32_t usec_timeout;
-+	void *pptable;
-+	struct phm_platform_descriptor platform_descriptor;
-+	void *backend;
-+	enum PP_DAL_POWERLEVEL	dal_power_level;
-+	struct phm_dynamic_state_info dyn_state;
-+	struct phm_runtime_table_header setup_asic;
-+	struct phm_runtime_table_header disable_dynamic_state_management;
-+	struct phm_runtime_table_header enable_dynamic_state_management;
-+	const struct pp_hwmgr_func *hwmgr_func;
-+	const struct pp_table_func *pptable_func;
-+	struct pp_power_state    *ps;
-+        enum pp_power_source  power_source;
-+	uint32_t num_ps;
-+	uint32_t ps_size;
-+	struct pp_power_state    *current_ps;
-+	struct pp_power_state    *request_ps;
-+	struct pp_power_state    *boot_ps;
-+	struct pp_power_state    *uvd_ps;
-+};
-+
-+
-+extern int hwmgr_init(struct amd_pp_init *pp_init,
-+		      struct pp_instance *handle);
-+
-+extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
-+
-+extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
-+
-+extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
-+				uint32_t value, uint32_t mask);
-+
-+extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
-+				uint32_t index, uint32_t value, uint32_t mask);
-+
-+
-+
-+extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
-+				uint32_t indirect_port,
-+				uint32_t index,
-+				uint32_t value,
-+				uint32_t mask);
-+
-+extern void phm_wait_for_indirect_register_unequal(
-+				struct pp_hwmgr *hwmgr,
-+				uint32_t indirect_port,
-+				uint32_t index,
-+				uint32_t value,
-+				uint32_t mask);
-+
-+#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-+#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
-+
-+#define PHM_SET_FIELD(origval, reg, field, fieldval)	\
-+	(((origval) & ~PHM_FIELD_MASK(reg, field)) |	\
-+	 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
-+
-+#define PHM_GET_FIELD(value, reg, field)	\
-+	(((value) & PHM_FIELD_MASK(reg, field)) >>	\
-+	 PHM_FIELD_SHIFT(reg, field))
-+
-+
-+#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask)	\
-+	phm_wait_on_register(hwmgr, index, value, mask)
-+
-+#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask)	\
-+	phm_wait_for_register_unequal(hwmgr, index, value, mask)
-+
-+#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
-+	phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
-+
-+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
-+	phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
-+	phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)	\
-+	phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
-+
-+/* Operations on named registers. */
-+
-+#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask)	\
-+	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
-+
-+#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)	\
-+	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
-+
-+#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)	\
-+	PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)	\
-+	PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)	\
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)	\
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+/* Operations on named fields. */
-+
-+#define PHM_READ_FIELD(device, reg, field)	\
-+	PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
-+
-+#define PHM_READ_INDIRECT_FIELD(device, port, reg, field)	\
-+	PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
-+			reg, field)
-+
-+#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)	\
-+	PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
-+			reg, field)
-+
-+#define PHM_WRITE_FIELD(device, reg, field, fieldval)	\
-+	cgs_write_register(device, mm##reg, PHM_SET_FIELD(	\
-+				cgs_read_register(device, mm##reg), reg, field, fieldval))
-+
-+#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)	\
-+	cgs_write_ind_register(device, port, ix##reg,	\
-+			PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
-+				reg, field, fieldval))
-+
-+#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)	\
-+	cgs_write_ind_register(device, port, ix##reg,	\
-+			PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),	\
-+				reg, field, fieldval))
-+
-+#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval)	\
-+	PHM_WAIT_REGISTER(hwmgr, reg, (fieldval)	\
-+			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)	\
-+	PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\
-+			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)	\
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\
-+			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)	\
-+	PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval)	\
-+			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)	\
-+	PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)	\
-+			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)	\
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)	\
-+			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
-+
-+/* Operations on arrays of registers & fields. */
-+
-+#define PHM_READ_ARRAY_REGISTER(device, reg, offset)	\
-+	cgs_read_register(device, mm##reg + (offset))
-+
-+#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value)	\
-+	cgs_write_register(device, mm##reg + (offset), value)
-+
-+#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask)	\
-+	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
-+
-+#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask)	\
-+	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
-+
-+#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
-+	PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
-+
-+#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)	\
-+	PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset,	\
-+			PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset),	\
-+				reg, field, fieldvalue))
-+
-+#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)	\
-+	PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset),	\
-+			(fieldvalue) << PHM_FIELD_SHIFT(reg, field),	\
-+			PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue)	\
-+	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset),	\
-+			(fieldvalue) << PHM_FIELD_SHIFT(reg, field),	\
-+			PHM_FIELD_MASK(reg, field))
-+
-+#endif /* _HWMGR_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
-new file mode 100644
-index 0000000..c63bcc7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
-@@ -0,0 +1,200 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef PP_POWERSTATE_H
-+#define PP_POWERSTATE_H
-+
-+struct pp_hw_power_state {
-+	unsigned int magic;
-+};
-+
-+struct pp_power_state;
-+
-+
-+#define PP_INVALID_POWER_STATE_ID (0)
-+
-+
-+/*
-+ * An item of a list containing Power States.
-+ */
-+
-+struct PP_StateLinkedList {
-+	struct pp_power_state *next;
-+	struct pp_power_state *prev;
-+};
-+
-+
-+enum PP_StateUILabel {
-+	PP_StateUILabel_None,
-+	PP_StateUILabel_Battery,
-+	PP_StateUILabel_MiddleLow,
-+	PP_StateUILabel_Balanced,
-+	PP_StateUILabel_MiddleHigh,
-+	PP_StateUILabel_Performance,
-+	PP_StateUILabel_BACO
-+};
-+
-+enum PP_StateClassificationFlag {
-+	PP_StateClassificationFlag_Boot                = 0x0001,
-+	PP_StateClassificationFlag_Thermal             = 0x0002,
-+	PP_StateClassificationFlag_LimitedPowerSource  = 0x0004,
-+	PP_StateClassificationFlag_Rest                = 0x0008,
-+	PP_StateClassificationFlag_Forced              = 0x0010,
-+	PP_StateClassificationFlag_User3DPerformance   = 0x0020,
-+	PP_StateClassificationFlag_User2DPerformance   = 0x0040,
-+	PP_StateClassificationFlag_3DPerformance       = 0x0080,
-+	PP_StateClassificationFlag_ACOverdriveTemplate   = 0x0100,
-+	PP_StateClassificationFlag_Uvd                 = 0x0200,
-+	PP_StateClassificationFlag_3DPerformanceLow    = 0x0400,
-+	PP_StateClassificationFlag_ACPI                = 0x0800,
-+	PP_StateClassificationFlag_HD2                 = 0x1000,
-+	PP_StateClassificationFlag_UvdHD               = 0x2000,
-+	PP_StateClassificationFlag_UvdSD               = 0x4000,
-+	PP_StateClassificationFlag_UserDCPerformance    = 0x8000,
-+	PP_StateClassificationFlag_DCOverdriveTemplate   = 0x10000,
-+	PP_StateClassificationFlag_BACO                  = 0x20000,
-+	PP_StateClassificationFlag_LimitedPowerSource_2  = 0x40000,
-+	PP_StateClassificationFlag_ULV                   = 0x80000,
-+	PP_StateClassificationFlag_UvdMVC               = 0x100000,
-+};
-+
-+typedef unsigned int PP_StateClassificationFlags;
-+
-+struct PP_StateClassificationBlock {
-+	enum PP_StateUILabel         ui_label;
-+	enum PP_StateClassificationFlag  flags;
-+	int                          bios_index;
-+	bool                      temporary_state;
-+	bool                      to_be_deleted;
-+};
-+
-+struct PP_StatePcieBlock {
-+	unsigned int lanes;
-+};
-+
-+enum PP_RefreshrateSource {
-+	PP_RefreshrateSource_EDID,
-+	PP_RefreshrateSource_Explicit
-+};
-+
-+struct PP_StateDisplayBlock {
-+	bool              disableFrameModulation;
-+	bool              limitRefreshrate;
-+	enum PP_RefreshrateSource refreshrateSource;
-+	int                  explicitRefreshrate;
-+	int                  edidRefreshrateIndex;
-+	bool              enableVariBright;
-+};
-+
-+struct PP_StateMemroyBlock {
-+	bool              dllOff;
-+	uint8_t                 m3arb;
-+	uint8_t                 unused[3];
-+};
-+
-+struct PP_StateSoftwareAlgorithmBlock {
-+	bool disableLoadBalancing;
-+	bool enableSleepForTimestamps;
-+};
-+
-+#define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
-+
-+/**
-+ * Type to hold a temperature range.
-+ */
-+struct PP_TemperatureRange {
-+	uint16_t min;
-+	uint16_t max;
-+};
-+
-+struct PP_StateValidationBlock {
-+	bool singleDisplayOnly;
-+	bool disallowOnDC;
-+	uint8_t supportedPowerLevels;
-+};
-+
-+struct PP_UVD_CLOCKS {
-+	uint32_t VCLK;
-+	uint32_t DCLK;
-+};
-+
-+/**
-+* Structure to hold a PowerPlay Power State.
-+*/
-+struct pp_power_state {
-+	uint32_t                            id;
-+	struct PP_StateLinkedList                  orderedList;
-+	struct PP_StateLinkedList                  allStatesList;
-+
-+	struct PP_StateClassificationBlock         classification;
-+	struct PP_StateValidationBlock             validation;
-+	struct PP_StatePcieBlock                   pcie;
-+	struct PP_StateDisplayBlock                display;
-+	struct PP_StateMemroyBlock                 memory;
-+	struct PP_TemperatureRange                 temperatures;
-+	struct PP_StateSoftwareAlgorithmBlock      software;
-+	struct PP_UVD_CLOCKS                       uvd_clocks;
-+	struct pp_hw_power_state  hardware;
-+};
-+
-+
-+/*Structure to hold a VCE state entry*/
-+struct PP_VCEState {
-+	uint32_t evclk;
-+	uint32_t ecclk;
-+	uint32_t sclk;
-+	uint32_t mclk;
-+};
-+
-+enum PP_MMProfilingState {
-+	PP_MMProfilingState_NA = 0,
-+	PP_MMProfilingState_Started,
-+	PP_MMProfilingState_Stopped
-+};
-+
-+struct PP_Clock_Engine_Request {
-+	unsigned long clientType;
-+	unsigned long ctxid;
-+	uint64_t  context_handle;
-+	unsigned long sclk;
-+	unsigned long sclkHardMin;
-+	unsigned long mclk;
-+	unsigned long iclk;
-+	unsigned long evclk;
-+	unsigned long ecclk;
-+	unsigned long ecclkHardMin;
-+	unsigned long vclk;
-+	unsigned long dclk;
-+	unsigned long samclk;
-+	unsigned long acpclk;
-+	unsigned long sclkOverdrive;
-+	unsigned long mclkOverdrive;
-+	unsigned long sclk_threshold;
-+	unsigned long flag;
-+	unsigned long vclk_ceiling;
-+	unsigned long dclk_ceiling;
-+	unsigned long num_cus;
-+	unsigned long pmflag;
-+	enum PP_MMProfilingState MMProfilingState;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
-new file mode 100644
-index 0000000..3bd5e69
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h
-@@ -0,0 +1,28 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+extern bool acpi_atcs_functions_supported(void *device,
-+							uint32_t index);
-+extern int acpi_pcie_perf_request(void *device,
-+						uint8_t perf_req,
-+						bool advertise);
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-index 318f827..35dfcd9 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-@@ -24,10 +24,11 @@
- #define _PP_INSTANCE_H_
- 
- #include "smumgr.h"
--
-+#include "hwmgr.h"
- 
- struct pp_instance {
- 	struct pp_smumgr *smu_mgr;
-+	struct pp_hwmgr *hwmgr;
- };
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h b/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h
-new file mode 100644
-index 0000000..b43315c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef PP_POWERSOURCE_H
-+#define PP_POWERSOURCE_H
-+
-+enum pp_power_source {
-+	PP_PowerSource_AC = 0,
-+	PP_PowerSource_DC,
-+	PP_PowerSource_LimitedPower,
-+	PP_PowerSource_LimitedPower_2,
-+	PP_PowerSource_Max
-+};
-+
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0045-drm-amd-powerplay-add-Carrizo-smu-support.patch b/common/recipes-kernel/linux/files/0045-drm-amd-powerplay-add-Carrizo-smu-support.patch
deleted file mode 100644
index a73f3163..00000000
--- a/common/recipes-kernel/linux/files/0045-drm-amd-powerplay-add-Carrizo-smu-support.patch
+++ /dev/null
@@ -1,2159 +0,0 @@
-From 7e947a91bd0ea6cecf185060d03f2dfd9756673f Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Wed, 22 Jul 2015 09:54:16 +0800
-Subject: [PATCH 0045/1110] drm/amd/powerplay: add Carrizo smu support
-
-This implements the SMU firmware manager interface for CZ.
-Some header files are moved from amdgpu folder to powerplay as well.
-
-v3: delete peci sub-module.
-v2: use cgs interface directly
-    add load_mec_firmware function
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h              | 185 -----
- drivers/gpu/drm/amd/amdgpu/smu8.h                  |  72 --
- drivers/gpu/drm/amd/amdgpu/smu8_fusion.h           | 127 ---
- drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h     | 147 ----
- drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h       | 185 +++++
- drivers/gpu/drm/amd/powerplay/inc/smu8.h           |  72 ++
- drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h    | 127 +++
- .../gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h  | 147 ++++
- drivers/gpu/drm/amd/powerplay/smumgr/Makefile      |   2 +-
- drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 858 +++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h   | 102 +++
- drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |   3 +-
- 12 files changed, 1494 insertions(+), 533 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/smu8.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/smu8_fusion.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu8.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h
-deleted file mode 100644
-index 273616a..0000000
---- a/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h
-+++ /dev/null
-@@ -1,185 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef CZ_PP_SMC_H
--#define CZ_PP_SMC_H
--
--#pragma pack(push, 1)
--
--/* Fan control algorithm:*/
--#define FDO_MODE_HARDWARE 0
--#define FDO_MODE_PIECE_WISE_LINEAR 1
--
--enum FAN_CONTROL {
--    FAN_CONTROL_FUZZY,
--    FAN_CONTROL_TABLE
--};
--
--enum DPM_ARRAY {
--    DPM_ARRAY_HARD_MAX,
--    DPM_ARRAY_HARD_MIN,
--    DPM_ARRAY_SOFT_MAX,
--    DPM_ARRAY_SOFT_MIN
--};
--
--/*
-- * Return codes for driver to SMC communication.
-- * Leave these #define-s, enums might not be exactly 8-bits on the microcontroller.
-- */
--#define PPSMC_Result_OK             ((uint16_t)0x01)
--#define PPSMC_Result_NoMore         ((uint16_t)0x02)
--#define PPSMC_Result_NotNow         ((uint16_t)0x03)
--#define PPSMC_Result_Failed         ((uint16_t)0xFF)
--#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
--#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
--
--#define PPSMC_isERROR(x)            ((uint16_t)0x80 & (x))
--
--/*
-- * Supported driver messages
-- */
--#define PPSMC_MSG_Test                        ((uint16_t) 0x1)
--#define PPSMC_MSG_GetFeatureStatus            ((uint16_t) 0x2)
--#define PPSMC_MSG_EnableAllSmuFeatures        ((uint16_t) 0x3)
--#define PPSMC_MSG_DisableAllSmuFeatures       ((uint16_t) 0x4)
--#define PPSMC_MSG_OptimizeBattery             ((uint16_t) 0x5)
--#define PPSMC_MSG_MaximizePerf                ((uint16_t) 0x6)
--#define PPSMC_MSG_UVDPowerOFF                 ((uint16_t) 0x7)
--#define PPSMC_MSG_UVDPowerON                  ((uint16_t) 0x8)
--#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x9)
--#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0xA)
--#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0xB)
--#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0xC)
--#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0xD)
--#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0xE)
--#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0xF)
--#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x10)
--#define PPSMC_MSG_SetMinDeepSleepSclk         ((uint16_t) 0x11)
--#define PPSMC_MSG_SetSclkSoftMin              ((uint16_t) 0x12)
--#define PPSMC_MSG_SetSclkSoftMax              ((uint16_t) 0x13)
--#define PPSMC_MSG_SetSclkHardMin              ((uint16_t) 0x14)
--#define PPSMC_MSG_SetSclkHardMax              ((uint16_t) 0x15)
--#define PPSMC_MSG_SetLclkSoftMin              ((uint16_t) 0x16)
--#define PPSMC_MSG_SetLclkSoftMax              ((uint16_t) 0x17)
--#define PPSMC_MSG_SetLclkHardMin              ((uint16_t) 0x18)
--#define PPSMC_MSG_SetLclkHardMax              ((uint16_t) 0x19)
--#define PPSMC_MSG_SetUvdSoftMin               ((uint16_t) 0x1A)
--#define PPSMC_MSG_SetUvdSoftMax               ((uint16_t) 0x1B)
--#define PPSMC_MSG_SetUvdHardMin               ((uint16_t) 0x1C)
--#define PPSMC_MSG_SetUvdHardMax               ((uint16_t) 0x1D)
--#define PPSMC_MSG_SetEclkSoftMin              ((uint16_t) 0x1E)
--#define PPSMC_MSG_SetEclkSoftMax              ((uint16_t) 0x1F)
--#define PPSMC_MSG_SetEclkHardMin              ((uint16_t) 0x20)
--#define PPSMC_MSG_SetEclkHardMax              ((uint16_t) 0x21)
--#define PPSMC_MSG_SetAclkSoftMin              ((uint16_t) 0x22)
--#define PPSMC_MSG_SetAclkSoftMax              ((uint16_t) 0x23)
--#define PPSMC_MSG_SetAclkHardMin              ((uint16_t) 0x24)
--#define PPSMC_MSG_SetAclkHardMax              ((uint16_t) 0x25)
--#define PPSMC_MSG_SetNclkSoftMin              ((uint16_t) 0x26)
--#define PPSMC_MSG_SetNclkSoftMax              ((uint16_t) 0x27)
--#define PPSMC_MSG_SetNclkHardMin              ((uint16_t) 0x28)
--#define PPSMC_MSG_SetNclkHardMax              ((uint16_t) 0x29)
--#define PPSMC_MSG_SetPstateSoftMin            ((uint16_t) 0x2A)
--#define PPSMC_MSG_SetPstateSoftMax            ((uint16_t) 0x2B)
--#define PPSMC_MSG_SetPstateHardMin            ((uint16_t) 0x2C)
--#define PPSMC_MSG_SetPstateHardMax            ((uint16_t) 0x2D)
--#define PPSMC_MSG_DisableLowMemoryPstate      ((uint16_t) 0x2E)
--#define PPSMC_MSG_EnableLowMemoryPstate       ((uint16_t) 0x2F)
--#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x30)
--#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x31)
--#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x32)
--#define PPSMC_MSG_DriverDramAddrHi            ((uint16_t) 0x33)
--#define PPSMC_MSG_DriverDramAddrLo            ((uint16_t) 0x34)
--#define PPSMC_MSG_CondExecDramAddrHi          ((uint16_t) 0x35)
--#define PPSMC_MSG_CondExecDramAddrLo          ((uint16_t) 0x36)
--#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x37)
--#define PPSMC_MSG_DriverResetMode             ((uint16_t) 0x38)
--#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x39)
--#define PPSMC_MSG_SetDisplayPhyConfig         ((uint16_t) 0x3A)
--#define PPSMC_MSG_GetMaxSclkLevel             ((uint16_t) 0x3B)
--#define PPSMC_MSG_GetMaxLclkLevel             ((uint16_t) 0x3C)
--#define PPSMC_MSG_GetMaxUvdLevel              ((uint16_t) 0x3D)
--#define PPSMC_MSG_GetMaxEclkLevel             ((uint16_t) 0x3E)
--#define PPSMC_MSG_GetMaxAclkLevel             ((uint16_t) 0x3F)
--#define PPSMC_MSG_GetMaxNclkLevel             ((uint16_t) 0x40)
--#define PPSMC_MSG_GetMaxPstate                ((uint16_t) 0x41)
--#define PPSMC_MSG_DramAddrHiVirtual           ((uint16_t) 0x42)
--#define PPSMC_MSG_DramAddrLoVirtual           ((uint16_t) 0x43)
--#define PPSMC_MSG_DramAddrHiPhysical          ((uint16_t) 0x44)
--#define PPSMC_MSG_DramAddrLoPhysical          ((uint16_t) 0x45)
--#define PPSMC_MSG_DramBufferSize              ((uint16_t) 0x46)
--#define PPSMC_MSG_SetMmPwrLogDramAddrHi       ((uint16_t) 0x47)
--#define PPSMC_MSG_SetMmPwrLogDramAddrLo       ((uint16_t) 0x48)
--#define PPSMC_MSG_SetClkTableAddrHi           ((uint16_t) 0x49)
--#define PPSMC_MSG_SetClkTableAddrLo           ((uint16_t) 0x4A)
--#define PPSMC_MSG_GetConservativePowerLimit   ((uint16_t) 0x4B)
--
--#define PPSMC_MSG_InitJobs                    ((uint16_t) 0x252)
--#define PPSMC_MSG_ExecuteJob                  ((uint16_t) 0x254)
--
--#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
--#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
--
--#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
--#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
--
--#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
--#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
--
--#define PPSMC_MSG_AllowLowSclkInterrupt       ((uint16_t) 0x184)
--#define PPSMC_MSG_MmPowerMonitorStart         ((uint16_t) 0x18F)
--#define PPSMC_MSG_MmPowerMonitorStop          ((uint16_t) 0x190)
--#define PPSMC_MSG_MmPowerMonitorRestart       ((uint16_t) 0x191)
--
--#define PPSMC_MSG_SetClockGateMask            ((uint16_t) 0x260)
--#define PPSMC_MSG_SetFpsThresholdLo           ((uint16_t) 0x264)
--#define PPSMC_MSG_SetFpsThresholdHi           ((uint16_t) 0x265)
--#define PPSMC_MSG_SetLowSclkIntrThreshold     ((uint16_t) 0x266)
--
--#define PPSMC_MSG_ClkTableXferToDram          ((uint16_t) 0x267)
--#define PPSMC_MSG_ClkTableXferToSmu           ((uint16_t) 0x268)
--#define PPSMC_MSG_GetAverageGraphicsActivity  ((uint16_t) 0x269)
--#define PPSMC_MSG_GetAverageGioActivity       ((uint16_t) 0x26A)
--#define PPSMC_MSG_SetLoggerBufferSize         ((uint16_t) 0x26B)
--#define PPSMC_MSG_SetLoggerAddressHigh        ((uint16_t) 0x26C)
--#define PPSMC_MSG_SetLoggerAddressLow         ((uint16_t) 0x26D)
--#define PPSMC_MSG_SetWatermarkFrequency       ((uint16_t) 0x26E)
--
--/* REMOVE LATER*/
--#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
--
--/* Feature Enable Masks*/
--#define NB_DPM_MASK             0x00000800
--#define VDDGFX_MASK             0x00800000
--#define VCE_DPM_MASK            0x00400000
--#define ACP_DPM_MASK            0x00040000
--#define UVD_DPM_MASK            0x00010000
--#define GFX_CU_PG_MASK          0x00004000
--#define SCLK_DPM_MASK           0x00080000
--
--#if !defined(SMC_MICROCODE)
--#pragma pack(pop)
--
--#endif
--
--#endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu8.h b/drivers/gpu/drm/amd/amdgpu/smu8.h
-deleted file mode 100644
-index d758d07..0000000
---- a/drivers/gpu/drm/amd/amdgpu/smu8.h
-+++ /dev/null
-@@ -1,72 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef SMU8_H
--#define SMU8_H
--
--#pragma pack(push, 1)
--
--#define ENABLE_DEBUG_FEATURES
--
--struct SMU8_Firmware_Header {
--	uint32_t Version;
--	uint32_t ImageSize;
--	uint32_t CodeSize;
--	uint32_t HeaderSize;
--	uint32_t EntryPoint;
--	uint32_t Rtos;
--	uint32_t UcodeLoadStatus;
--	uint32_t DpmTable;
--	uint32_t FanTable;
--	uint32_t PmFuseTable;
--	uint32_t Globals;
--	uint32_t Reserved[20];
--	uint32_t Signature;
--};
--
--struct SMU8_MultimediaPowerLogData {
--	uint32_t avgTotalPower;
--	uint32_t avgGpuPower;
--	uint32_t avgUvdPower;
--	uint32_t avgVcePower;
--
--	uint32_t avgSclk;
--	uint32_t avgDclk;
--	uint32_t avgVclk;
--	uint32_t avgEclk;
--
--	uint32_t startTimeHi;
--	uint32_t startTimeLo;
--
--	uint32_t endTimeHi;
--	uint32_t endTimeLo;
--};
--
--#define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
--#define SMU8_UNBCSR_START_ADDR 0xC0100000
--
--#define SMN_MP1_SRAM_START_ADDR 0x10000000
--
--#pragma pack(pop)
--
--#endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h b/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h
-deleted file mode 100644
-index 5c9cc3c..0000000
---- a/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h
-+++ /dev/null
-@@ -1,127 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef SMU8_FUSION_H
--#define SMU8_FUSION_H
--
--#include "smu8.h"
--
--#pragma pack(push, 1)
--
--#define SMU8_MAX_CUS 2
--#define SMU8_PSMS_PER_CU 4
--#define SMU8_CACS_PER_CU 4
--
--struct SMU8_GfxCuPgScoreboard {
--    uint8_t Enabled;
--    uint8_t spare[3];
--};
--
--struct SMU8_Port80MonitorTable {
--	uint32_t MmioAddress;
--	uint32_t MemoryBaseHi;
--	uint32_t MemoryBaseLo;
--	uint16_t MemoryBufferSize;
--	uint16_t MemoryPosition;
--	uint16_t PollingInterval;
--	uint8_t  EnableCsrShadow;
--	uint8_t  EnableDramShadow;
--};
--
--/* Clock Table Definitions */
--#define NUM_SCLK_LEVELS     8
--#define NUM_LCLK_LEVELS     8
--#define NUM_UVD_LEVELS      8
--#define NUM_ECLK_LEVELS     8
--#define NUM_ACLK_LEVELS     8
--
--struct SMU8_Fusion_ClkLevel {
--	uint8_t		GnbVid;
--	uint8_t		GfxVid;
--	uint8_t		DfsDid;
--	uint8_t		DeepSleepDid;
--	uint32_t	DfsBypass;
--	uint32_t	Frequency;
--};
--
--struct SMU8_Fusion_SclkBreakdownTable {
--	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
--	struct SMU8_Fusion_ClkLevel DpmOffLevel;
--	/* SMU8_Fusion_ClkLevel PwrOffLevel; */
--	uint32_t    SclkValidMask;
--	uint32_t    MaxSclkIndex;
--};
--
--struct SMU8_Fusion_LclkBreakdownTable {
--	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
--	struct SMU8_Fusion_ClkLevel DpmOffLevel;
--    /* SMU8_Fusion_ClkLevel PwrOffLevel; */
--	uint32_t    LclkValidMask;
--	uint32_t    MaxLclkIndex;
--};
--
--struct SMU8_Fusion_EclkBreakdownTable {
--	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
--	struct SMU8_Fusion_ClkLevel DpmOffLevel;
--	struct SMU8_Fusion_ClkLevel PwrOffLevel;
--	uint32_t    EclkValidMask;
--	uint32_t    MaxEclkIndex;
--};
--
--struct SMU8_Fusion_VclkBreakdownTable {
--	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
--	struct SMU8_Fusion_ClkLevel DpmOffLevel;
--	struct SMU8_Fusion_ClkLevel PwrOffLevel;
--	uint32_t    VclkValidMask;
--	uint32_t    MaxVclkIndex;
--};
--
--struct SMU8_Fusion_DclkBreakdownTable {
--	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
--	struct SMU8_Fusion_ClkLevel DpmOffLevel;
--	struct SMU8_Fusion_ClkLevel PwrOffLevel;
--	uint32_t    DclkValidMask;
--	uint32_t    MaxDclkIndex;
--};
--
--struct SMU8_Fusion_AclkBreakdownTable {
--	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
--	struct SMU8_Fusion_ClkLevel DpmOffLevel;
--	struct SMU8_Fusion_ClkLevel PwrOffLevel;
--	uint32_t    AclkValidMask;
--	uint32_t    MaxAclkIndex;
--};
--
--
--struct SMU8_Fusion_ClkTable {
--	struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
--	struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
--	struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
--	struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
--	struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
--	struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
--};
--
--#pragma pack(pop)
--
--#endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h
-deleted file mode 100644
-index f8ba071..0000000
---- a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h
-+++ /dev/null
-@@ -1,147 +0,0 @@
--// CZ Ucode Loading Definitions
--#ifndef SMU_UCODE_XFER_CZ_H
--#define SMU_UCODE_XFER_CZ_H
--
--#define NUM_JOBLIST_ENTRIES      32
--
--#define TASK_TYPE_NO_ACTION      0
--#define TASK_TYPE_UCODE_LOAD     1
--#define TASK_TYPE_UCODE_SAVE     2
--#define TASK_TYPE_REG_LOAD       3
--#define TASK_TYPE_REG_SAVE       4
--#define TASK_TYPE_INITIALIZE     5
--
--#define TASK_ARG_REG_SMCIND      0
--#define TASK_ARG_REG_MMIO        1
--#define TASK_ARG_REG_FCH         2
--#define TASK_ARG_REG_UNB         3
--
--#define TASK_ARG_INIT_MM_PWR_LOG 0
--#define TASK_ARG_INIT_CLK_TABLE  1
--
--#define JOB_GFX_SAVE             0
--#define JOB_GFX_RESTORE          1
--#define JOB_FCH_SAVE             2
--#define JOB_FCH_RESTORE          3
--#define JOB_UNB_SAVE             4
--#define JOB_UNB_RESTORE          5
--#define JOB_GMC_SAVE             6
--#define JOB_GMC_RESTORE          7
--#define JOB_GNB_SAVE             8
--#define JOB_GNB_RESTORE          9
--
--#define IGNORE_JOB               0xff
--#define END_OF_TASK_LIST     (uint16_t)0xffff
--
--// Size of DRAM regions (in bytes) requested by SMU:
--#define SMU_DRAM_REQ_MM_PWR_LOG 48 
--
--#define UCODE_ID_SDMA0           0
--#define UCODE_ID_SDMA1           1
--#define UCODE_ID_CP_CE           2
--#define UCODE_ID_CP_PFP          3
--#define UCODE_ID_CP_ME           4
--#define UCODE_ID_CP_MEC_JT1      5
--#define UCODE_ID_CP_MEC_JT2      6
--#define UCODE_ID_GMCON_RENG      7
--#define UCODE_ID_RLC_G           8
--#define UCODE_ID_RLC_SCRATCH     9
--#define UCODE_ID_RLC_SRM_ARAM    10
--#define UCODE_ID_RLC_SRM_DRAM    11
--#define UCODE_ID_DMCU_ERAM       12
--#define UCODE_ID_DMCU_IRAM       13
--
--#define UCODE_ID_SDMA0_MASK           0x00000001       
--#define UCODE_ID_SDMA1_MASK           0x00000002        
--#define UCODE_ID_CP_CE_MASK           0x00000004      
--#define UCODE_ID_CP_PFP_MASK          0x00000008         
--#define UCODE_ID_CP_ME_MASK           0x00000010          
--#define UCODE_ID_CP_MEC_JT1_MASK      0x00000020             
--#define UCODE_ID_CP_MEC_JT2_MASK      0x00000040          
--#define UCODE_ID_GMCON_RENG_MASK      0x00000080            
--#define UCODE_ID_RLC_G_MASK           0x00000100           
--#define UCODE_ID_RLC_SCRATCH_MASK     0x00000200         
--#define UCODE_ID_RLC_SRM_ARAM_MASK    0x00000400                
--#define UCODE_ID_RLC_SRM_DRAM_MASK    0x00000800                 
--#define UCODE_ID_DMCU_ERAM_MASK       0x00001000             
--#define UCODE_ID_DMCU_IRAM_MASK       0x00002000              
--
--#define UCODE_ID_SDMA0_SIZE_BYTE           10368        
--#define UCODE_ID_SDMA1_SIZE_BYTE           10368          
--#define UCODE_ID_CP_CE_SIZE_BYTE           8576        
--#define UCODE_ID_CP_PFP_SIZE_BYTE          16768           
--#define UCODE_ID_CP_ME_SIZE_BYTE           16768            
--#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE      384               
--#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE      384            
--#define UCODE_ID_GMCON_RENG_SIZE_BYTE      4096              
--#define UCODE_ID_RLC_G_SIZE_BYTE           2048             
--#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE     132           
--#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE    8192                  
--#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE    4096                   
--#define UCODE_ID_DMCU_ERAM_SIZE_BYTE       24576               
--#define UCODE_ID_DMCU_IRAM_SIZE_BYTE       1024                 
--
--#define NUM_UCODES               14
--
--typedef struct {
--	uint32_t high;
--	uint32_t low;
--} data_64_t;
--
--struct SMU_Task {
--    uint8_t type;
--    uint8_t arg;
--    uint16_t next;
--    data_64_t addr;
--    uint32_t size_bytes;
--};
--typedef struct SMU_Task SMU_Task;
--
--struct TOC {
--    uint8_t JobList[NUM_JOBLIST_ENTRIES];
--    SMU_Task tasks[1];
--};
--
--// META DATA COMMAND Definitions
--#define METADATA_CMD_MODE0         0x00000103 
--#define METADATA_CMD_MODE1         0x00000113 
--#define METADATA_CMD_MODE2         0x00000123 
--#define METADATA_CMD_MODE3         0x00000133
--#define METADATA_CMD_DELAY         0x00000203
--#define METADATA_CMD_CHNG_REGSPACE 0x00000303
--#define METADATA_PERFORM_ON_SAVE   0x00001000
--#define METADATA_PERFORM_ON_LOAD   0x00002000
--#define METADATA_CMD_ARG_MASK      0xFFFF0000
--#define METADATA_CMD_ARG_SHIFT     16
--
--// Simple register addr/data fields
--struct SMU_MetaData_Mode0 {
--    uint32_t register_address;
--    uint32_t register_data;
--};
--typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0;
--
--// Register addr/data with mask
--struct SMU_MetaData_Mode1 {
--    uint32_t register_address;
--    uint32_t register_mask;
--    uint32_t register_data;
--};
--typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1;
--
--struct SMU_MetaData_Mode2 {
--    uint32_t register_address;
--    uint32_t register_mask;
--    uint32_t target_value;
--};
--typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2;
--
--// Always write data (even on a save operation)
--struct SMU_MetaData_Mode3 {
--    uint32_t register_address;
--    uint32_t register_mask;
--    uint32_t register_data;
--};
--typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3;
--
--#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h
-new file mode 100644
-index 0000000..273616a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h
-@@ -0,0 +1,185 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef CZ_PP_SMC_H
-+#define CZ_PP_SMC_H
-+
-+#pragma pack(push, 1)
-+
-+/* Fan control algorithm:*/
-+#define FDO_MODE_HARDWARE 0
-+#define FDO_MODE_PIECE_WISE_LINEAR 1
-+
-+enum FAN_CONTROL {
-+    FAN_CONTROL_FUZZY,
-+    FAN_CONTROL_TABLE
-+};
-+
-+enum DPM_ARRAY {
-+    DPM_ARRAY_HARD_MAX,
-+    DPM_ARRAY_HARD_MIN,
-+    DPM_ARRAY_SOFT_MAX,
-+    DPM_ARRAY_SOFT_MIN
-+};
-+
-+/*
-+ * Return codes for driver to SMC communication.
-+ * Leave these #define-s, enums might not be exactly 8-bits on the microcontroller.
-+ */
-+#define PPSMC_Result_OK             ((uint16_t)0x01)
-+#define PPSMC_Result_NoMore         ((uint16_t)0x02)
-+#define PPSMC_Result_NotNow         ((uint16_t)0x03)
-+#define PPSMC_Result_Failed         ((uint16_t)0xFF)
-+#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
-+#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
-+
-+#define PPSMC_isERROR(x)            ((uint16_t)0x80 & (x))
-+
-+/*
-+ * Supported driver messages
-+ */
-+#define PPSMC_MSG_Test                        ((uint16_t) 0x1)
-+#define PPSMC_MSG_GetFeatureStatus            ((uint16_t) 0x2)
-+#define PPSMC_MSG_EnableAllSmuFeatures        ((uint16_t) 0x3)
-+#define PPSMC_MSG_DisableAllSmuFeatures       ((uint16_t) 0x4)
-+#define PPSMC_MSG_OptimizeBattery             ((uint16_t) 0x5)
-+#define PPSMC_MSG_MaximizePerf                ((uint16_t) 0x6)
-+#define PPSMC_MSG_UVDPowerOFF                 ((uint16_t) 0x7)
-+#define PPSMC_MSG_UVDPowerON                  ((uint16_t) 0x8)
-+#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x9)
-+#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0xA)
-+#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0xB)
-+#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0xC)
-+#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0xD)
-+#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0xE)
-+#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0xF)
-+#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x10)
-+#define PPSMC_MSG_SetMinDeepSleepSclk         ((uint16_t) 0x11)
-+#define PPSMC_MSG_SetSclkSoftMin              ((uint16_t) 0x12)
-+#define PPSMC_MSG_SetSclkSoftMax              ((uint16_t) 0x13)
-+#define PPSMC_MSG_SetSclkHardMin              ((uint16_t) 0x14)
-+#define PPSMC_MSG_SetSclkHardMax              ((uint16_t) 0x15)
-+#define PPSMC_MSG_SetLclkSoftMin              ((uint16_t) 0x16)
-+#define PPSMC_MSG_SetLclkSoftMax              ((uint16_t) 0x17)
-+#define PPSMC_MSG_SetLclkHardMin              ((uint16_t) 0x18)
-+#define PPSMC_MSG_SetLclkHardMax              ((uint16_t) 0x19)
-+#define PPSMC_MSG_SetUvdSoftMin               ((uint16_t) 0x1A)
-+#define PPSMC_MSG_SetUvdSoftMax               ((uint16_t) 0x1B)
-+#define PPSMC_MSG_SetUvdHardMin               ((uint16_t) 0x1C)
-+#define PPSMC_MSG_SetUvdHardMax               ((uint16_t) 0x1D)
-+#define PPSMC_MSG_SetEclkSoftMin              ((uint16_t) 0x1E)
-+#define PPSMC_MSG_SetEclkSoftMax              ((uint16_t) 0x1F)
-+#define PPSMC_MSG_SetEclkHardMin              ((uint16_t) 0x20)
-+#define PPSMC_MSG_SetEclkHardMax              ((uint16_t) 0x21)
-+#define PPSMC_MSG_SetAclkSoftMin              ((uint16_t) 0x22)
-+#define PPSMC_MSG_SetAclkSoftMax              ((uint16_t) 0x23)
-+#define PPSMC_MSG_SetAclkHardMin              ((uint16_t) 0x24)
-+#define PPSMC_MSG_SetAclkHardMax              ((uint16_t) 0x25)
-+#define PPSMC_MSG_SetNclkSoftMin              ((uint16_t) 0x26)
-+#define PPSMC_MSG_SetNclkSoftMax              ((uint16_t) 0x27)
-+#define PPSMC_MSG_SetNclkHardMin              ((uint16_t) 0x28)
-+#define PPSMC_MSG_SetNclkHardMax              ((uint16_t) 0x29)
-+#define PPSMC_MSG_SetPstateSoftMin            ((uint16_t) 0x2A)
-+#define PPSMC_MSG_SetPstateSoftMax            ((uint16_t) 0x2B)
-+#define PPSMC_MSG_SetPstateHardMin            ((uint16_t) 0x2C)
-+#define PPSMC_MSG_SetPstateHardMax            ((uint16_t) 0x2D)
-+#define PPSMC_MSG_DisableLowMemoryPstate      ((uint16_t) 0x2E)
-+#define PPSMC_MSG_EnableLowMemoryPstate       ((uint16_t) 0x2F)
-+#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x30)
-+#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x31)
-+#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x32)
-+#define PPSMC_MSG_DriverDramAddrHi            ((uint16_t) 0x33)
-+#define PPSMC_MSG_DriverDramAddrLo            ((uint16_t) 0x34)
-+#define PPSMC_MSG_CondExecDramAddrHi          ((uint16_t) 0x35)
-+#define PPSMC_MSG_CondExecDramAddrLo          ((uint16_t) 0x36)
-+#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x37)
-+#define PPSMC_MSG_DriverResetMode             ((uint16_t) 0x38)
-+#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x39)
-+#define PPSMC_MSG_SetDisplayPhyConfig         ((uint16_t) 0x3A)
-+#define PPSMC_MSG_GetMaxSclkLevel             ((uint16_t) 0x3B)
-+#define PPSMC_MSG_GetMaxLclkLevel             ((uint16_t) 0x3C)
-+#define PPSMC_MSG_GetMaxUvdLevel              ((uint16_t) 0x3D)
-+#define PPSMC_MSG_GetMaxEclkLevel             ((uint16_t) 0x3E)
-+#define PPSMC_MSG_GetMaxAclkLevel             ((uint16_t) 0x3F)
-+#define PPSMC_MSG_GetMaxNclkLevel             ((uint16_t) 0x40)
-+#define PPSMC_MSG_GetMaxPstate                ((uint16_t) 0x41)
-+#define PPSMC_MSG_DramAddrHiVirtual           ((uint16_t) 0x42)
-+#define PPSMC_MSG_DramAddrLoVirtual           ((uint16_t) 0x43)
-+#define PPSMC_MSG_DramAddrHiPhysical          ((uint16_t) 0x44)
-+#define PPSMC_MSG_DramAddrLoPhysical          ((uint16_t) 0x45)
-+#define PPSMC_MSG_DramBufferSize              ((uint16_t) 0x46)
-+#define PPSMC_MSG_SetMmPwrLogDramAddrHi       ((uint16_t) 0x47)
-+#define PPSMC_MSG_SetMmPwrLogDramAddrLo       ((uint16_t) 0x48)
-+#define PPSMC_MSG_SetClkTableAddrHi           ((uint16_t) 0x49)
-+#define PPSMC_MSG_SetClkTableAddrLo           ((uint16_t) 0x4A)
-+#define PPSMC_MSG_GetConservativePowerLimit   ((uint16_t) 0x4B)
-+
-+#define PPSMC_MSG_InitJobs                    ((uint16_t) 0x252)
-+#define PPSMC_MSG_ExecuteJob                  ((uint16_t) 0x254)
-+
-+#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
-+#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
-+
-+#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
-+#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
-+
-+#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
-+#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
-+
-+#define PPSMC_MSG_AllowLowSclkInterrupt       ((uint16_t) 0x184)
-+#define PPSMC_MSG_MmPowerMonitorStart         ((uint16_t) 0x18F)
-+#define PPSMC_MSG_MmPowerMonitorStop          ((uint16_t) 0x190)
-+#define PPSMC_MSG_MmPowerMonitorRestart       ((uint16_t) 0x191)
-+
-+#define PPSMC_MSG_SetClockGateMask            ((uint16_t) 0x260)
-+#define PPSMC_MSG_SetFpsThresholdLo           ((uint16_t) 0x264)
-+#define PPSMC_MSG_SetFpsThresholdHi           ((uint16_t) 0x265)
-+#define PPSMC_MSG_SetLowSclkIntrThreshold     ((uint16_t) 0x266)
-+
-+#define PPSMC_MSG_ClkTableXferToDram          ((uint16_t) 0x267)
-+#define PPSMC_MSG_ClkTableXferToSmu           ((uint16_t) 0x268)
-+#define PPSMC_MSG_GetAverageGraphicsActivity  ((uint16_t) 0x269)
-+#define PPSMC_MSG_GetAverageGioActivity       ((uint16_t) 0x26A)
-+#define PPSMC_MSG_SetLoggerBufferSize         ((uint16_t) 0x26B)
-+#define PPSMC_MSG_SetLoggerAddressHigh        ((uint16_t) 0x26C)
-+#define PPSMC_MSG_SetLoggerAddressLow         ((uint16_t) 0x26D)
-+#define PPSMC_MSG_SetWatermarkFrequency       ((uint16_t) 0x26E)
-+
-+/* REMOVE LATER*/
-+#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
-+
-+/* Feature Enable Masks*/
-+#define NB_DPM_MASK             0x00000800
-+#define VDDGFX_MASK             0x00800000
-+#define VCE_DPM_MASK            0x00400000
-+#define ACP_DPM_MASK            0x00040000
-+#define UVD_DPM_MASK            0x00010000
-+#define GFX_CU_PG_MASK          0x00004000
-+#define SCLK_DPM_MASK           0x00080000
-+
-+#if !defined(SMC_MICROCODE)
-+#pragma pack(pop)
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu8.h b/drivers/gpu/drm/amd/powerplay/inc/smu8.h
-new file mode 100644
-index 0000000..d758d07
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu8.h
-@@ -0,0 +1,72 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU8_H
-+#define SMU8_H
-+
-+#pragma pack(push, 1)
-+
-+#define ENABLE_DEBUG_FEATURES
-+
-+struct SMU8_Firmware_Header {
-+	uint32_t Version;
-+	uint32_t ImageSize;
-+	uint32_t CodeSize;
-+	uint32_t HeaderSize;
-+	uint32_t EntryPoint;
-+	uint32_t Rtos;
-+	uint32_t UcodeLoadStatus;
-+	uint32_t DpmTable;
-+	uint32_t FanTable;
-+	uint32_t PmFuseTable;
-+	uint32_t Globals;
-+	uint32_t Reserved[20];
-+	uint32_t Signature;
-+};
-+
-+struct SMU8_MultimediaPowerLogData {
-+	uint32_t avgTotalPower;
-+	uint32_t avgGpuPower;
-+	uint32_t avgUvdPower;
-+	uint32_t avgVcePower;
-+
-+	uint32_t avgSclk;
-+	uint32_t avgDclk;
-+	uint32_t avgVclk;
-+	uint32_t avgEclk;
-+
-+	uint32_t startTimeHi;
-+	uint32_t startTimeLo;
-+
-+	uint32_t endTimeHi;
-+	uint32_t endTimeLo;
-+};
-+
-+#define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
-+#define SMU8_UNBCSR_START_ADDR 0xC0100000
-+
-+#define SMN_MP1_SRAM_START_ADDR 0x10000000
-+
-+#pragma pack(pop)
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h
-new file mode 100644
-index 0000000..5c9cc3c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h
-@@ -0,0 +1,127 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU8_FUSION_H
-+#define SMU8_FUSION_H
-+
-+#include "smu8.h"
-+
-+#pragma pack(push, 1)
-+
-+#define SMU8_MAX_CUS 2
-+#define SMU8_PSMS_PER_CU 4
-+#define SMU8_CACS_PER_CU 4
-+
-+struct SMU8_GfxCuPgScoreboard {
-+    uint8_t Enabled;
-+    uint8_t spare[3];
-+};
-+
-+struct SMU8_Port80MonitorTable {
-+	uint32_t MmioAddress;
-+	uint32_t MemoryBaseHi;
-+	uint32_t MemoryBaseLo;
-+	uint16_t MemoryBufferSize;
-+	uint16_t MemoryPosition;
-+	uint16_t PollingInterval;
-+	uint8_t  EnableCsrShadow;
-+	uint8_t  EnableDramShadow;
-+};
-+
-+/* Clock Table Definitions */
-+#define NUM_SCLK_LEVELS     8
-+#define NUM_LCLK_LEVELS     8
-+#define NUM_UVD_LEVELS      8
-+#define NUM_ECLK_LEVELS     8
-+#define NUM_ACLK_LEVELS     8
-+
-+struct SMU8_Fusion_ClkLevel {
-+	uint8_t		GnbVid;
-+	uint8_t		GfxVid;
-+	uint8_t		DfsDid;
-+	uint8_t		DeepSleepDid;
-+	uint32_t	DfsBypass;
-+	uint32_t	Frequency;
-+};
-+
-+struct SMU8_Fusion_SclkBreakdownTable {
-+	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
-+	struct SMU8_Fusion_ClkLevel DpmOffLevel;
-+	/* SMU8_Fusion_ClkLevel PwrOffLevel; */
-+	uint32_t    SclkValidMask;
-+	uint32_t    MaxSclkIndex;
-+};
-+
-+struct SMU8_Fusion_LclkBreakdownTable {
-+	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
-+	struct SMU8_Fusion_ClkLevel DpmOffLevel;
-+    /* SMU8_Fusion_ClkLevel PwrOffLevel; */
-+	uint32_t    LclkValidMask;
-+	uint32_t    MaxLclkIndex;
-+};
-+
-+struct SMU8_Fusion_EclkBreakdownTable {
-+	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
-+	struct SMU8_Fusion_ClkLevel DpmOffLevel;
-+	struct SMU8_Fusion_ClkLevel PwrOffLevel;
-+	uint32_t    EclkValidMask;
-+	uint32_t    MaxEclkIndex;
-+};
-+
-+struct SMU8_Fusion_VclkBreakdownTable {
-+	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
-+	struct SMU8_Fusion_ClkLevel DpmOffLevel;
-+	struct SMU8_Fusion_ClkLevel PwrOffLevel;
-+	uint32_t    VclkValidMask;
-+	uint32_t    MaxVclkIndex;
-+};
-+
-+struct SMU8_Fusion_DclkBreakdownTable {
-+	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
-+	struct SMU8_Fusion_ClkLevel DpmOffLevel;
-+	struct SMU8_Fusion_ClkLevel PwrOffLevel;
-+	uint32_t    DclkValidMask;
-+	uint32_t    MaxDclkIndex;
-+};
-+
-+struct SMU8_Fusion_AclkBreakdownTable {
-+	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
-+	struct SMU8_Fusion_ClkLevel DpmOffLevel;
-+	struct SMU8_Fusion_ClkLevel PwrOffLevel;
-+	uint32_t    AclkValidMask;
-+	uint32_t    MaxAclkIndex;
-+};
-+
-+
-+struct SMU8_Fusion_ClkTable {
-+	struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
-+	struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
-+	struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
-+	struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
-+	struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
-+	struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
-+};
-+
-+#pragma pack(pop)
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h
-new file mode 100644
-index 0000000..f8ba071
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_cz.h
-@@ -0,0 +1,147 @@
-+// CZ Ucode Loading Definitions
-+#ifndef SMU_UCODE_XFER_CZ_H
-+#define SMU_UCODE_XFER_CZ_H
-+
-+#define NUM_JOBLIST_ENTRIES      32
-+
-+#define TASK_TYPE_NO_ACTION      0
-+#define TASK_TYPE_UCODE_LOAD     1
-+#define TASK_TYPE_UCODE_SAVE     2
-+#define TASK_TYPE_REG_LOAD       3
-+#define TASK_TYPE_REG_SAVE       4
-+#define TASK_TYPE_INITIALIZE     5
-+
-+#define TASK_ARG_REG_SMCIND      0
-+#define TASK_ARG_REG_MMIO        1
-+#define TASK_ARG_REG_FCH         2
-+#define TASK_ARG_REG_UNB         3
-+
-+#define TASK_ARG_INIT_MM_PWR_LOG 0
-+#define TASK_ARG_INIT_CLK_TABLE  1
-+
-+#define JOB_GFX_SAVE             0
-+#define JOB_GFX_RESTORE          1
-+#define JOB_FCH_SAVE             2
-+#define JOB_FCH_RESTORE          3
-+#define JOB_UNB_SAVE             4
-+#define JOB_UNB_RESTORE          5
-+#define JOB_GMC_SAVE             6
-+#define JOB_GMC_RESTORE          7
-+#define JOB_GNB_SAVE             8
-+#define JOB_GNB_RESTORE          9
-+
-+#define IGNORE_JOB               0xff
-+#define END_OF_TASK_LIST     (uint16_t)0xffff
-+
-+// Size of DRAM regions (in bytes) requested by SMU:
-+#define SMU_DRAM_REQ_MM_PWR_LOG 48 
-+
-+#define UCODE_ID_SDMA0           0
-+#define UCODE_ID_SDMA1           1
-+#define UCODE_ID_CP_CE           2
-+#define UCODE_ID_CP_PFP          3
-+#define UCODE_ID_CP_ME           4
-+#define UCODE_ID_CP_MEC_JT1      5
-+#define UCODE_ID_CP_MEC_JT2      6
-+#define UCODE_ID_GMCON_RENG      7
-+#define UCODE_ID_RLC_G           8
-+#define UCODE_ID_RLC_SCRATCH     9
-+#define UCODE_ID_RLC_SRM_ARAM    10
-+#define UCODE_ID_RLC_SRM_DRAM    11
-+#define UCODE_ID_DMCU_ERAM       12
-+#define UCODE_ID_DMCU_IRAM       13
-+
-+#define UCODE_ID_SDMA0_MASK           0x00000001       
-+#define UCODE_ID_SDMA1_MASK           0x00000002        
-+#define UCODE_ID_CP_CE_MASK           0x00000004      
-+#define UCODE_ID_CP_PFP_MASK          0x00000008         
-+#define UCODE_ID_CP_ME_MASK           0x00000010          
-+#define UCODE_ID_CP_MEC_JT1_MASK      0x00000020             
-+#define UCODE_ID_CP_MEC_JT2_MASK      0x00000040          
-+#define UCODE_ID_GMCON_RENG_MASK      0x00000080            
-+#define UCODE_ID_RLC_G_MASK           0x00000100           
-+#define UCODE_ID_RLC_SCRATCH_MASK     0x00000200         
-+#define UCODE_ID_RLC_SRM_ARAM_MASK    0x00000400                
-+#define UCODE_ID_RLC_SRM_DRAM_MASK    0x00000800                 
-+#define UCODE_ID_DMCU_ERAM_MASK       0x00001000             
-+#define UCODE_ID_DMCU_IRAM_MASK       0x00002000              
-+
-+#define UCODE_ID_SDMA0_SIZE_BYTE           10368        
-+#define UCODE_ID_SDMA1_SIZE_BYTE           10368          
-+#define UCODE_ID_CP_CE_SIZE_BYTE           8576        
-+#define UCODE_ID_CP_PFP_SIZE_BYTE          16768           
-+#define UCODE_ID_CP_ME_SIZE_BYTE           16768            
-+#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE      384               
-+#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE      384            
-+#define UCODE_ID_GMCON_RENG_SIZE_BYTE      4096              
-+#define UCODE_ID_RLC_G_SIZE_BYTE           2048             
-+#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE     132           
-+#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE    8192                  
-+#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE    4096                   
-+#define UCODE_ID_DMCU_ERAM_SIZE_BYTE       24576               
-+#define UCODE_ID_DMCU_IRAM_SIZE_BYTE       1024                 
-+
-+#define NUM_UCODES               14
-+
-+typedef struct {
-+	uint32_t high;
-+	uint32_t low;
-+} data_64_t;
-+
-+struct SMU_Task {
-+    uint8_t type;
-+    uint8_t arg;
-+    uint16_t next;
-+    data_64_t addr;
-+    uint32_t size_bytes;
-+};
-+typedef struct SMU_Task SMU_Task;
-+
-+struct TOC {
-+    uint8_t JobList[NUM_JOBLIST_ENTRIES];
-+    SMU_Task tasks[1];
-+};
-+
-+// META DATA COMMAND Definitions
-+#define METADATA_CMD_MODE0         0x00000103 
-+#define METADATA_CMD_MODE1         0x00000113 
-+#define METADATA_CMD_MODE2         0x00000123 
-+#define METADATA_CMD_MODE3         0x00000133
-+#define METADATA_CMD_DELAY         0x00000203
-+#define METADATA_CMD_CHNG_REGSPACE 0x00000303
-+#define METADATA_PERFORM_ON_SAVE   0x00001000
-+#define METADATA_PERFORM_ON_LOAD   0x00002000
-+#define METADATA_CMD_ARG_MASK      0xFFFF0000
-+#define METADATA_CMD_ARG_SHIFT     16
-+
-+// Simple register addr/data fields
-+struct SMU_MetaData_Mode0 {
-+    uint32_t register_address;
-+    uint32_t register_data;
-+};
-+typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0;
-+
-+// Register addr/data with mask
-+struct SMU_MetaData_Mode1 {
-+    uint32_t register_address;
-+    uint32_t register_mask;
-+    uint32_t register_data;
-+};
-+typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1;
-+
-+struct SMU_MetaData_Mode2 {
-+    uint32_t register_address;
-+    uint32_t register_mask;
-+    uint32_t target_value;
-+};
-+typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2;
-+
-+// Always write data (even on a save operation)
-+struct SMU_MetaData_Mode3 {
-+    uint32_t register_address;
-+    uint32_t register_mask;
-+    uint32_t register_data;
-+};
-+typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3;
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-index 61bfb2a..9219940 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'smu manager' sub-component of powerplay.
- # It provides the smu management services for the driver.
- 
--SMU_MGR = smumgr.o
-+SMU_MGR = smumgr.o cz_smumgr.o
- 
- AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-new file mode 100644
-index 0000000..e74023b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-@@ -0,0 +1,858 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/gfp.h>
-+#include "linux/delay.h"
-+#include "cgs_common.h"
-+#include "smu/smu_8_0_d.h"
-+#include "smu/smu_8_0_sh_mask.h"
-+#include "smu8.h"
-+#include "smu8_fusion.h"
-+#include "cz_smumgr.h"
-+#include "cz_ppsmc.h"
-+#include "smu_ucode_xfer_cz.h"
-+#include "gca/gfx_8_0_d.h"
-+#include "gca/gfx_8_0_sh_mask.h"
-+#include "smumgr.h"
-+
-+#define SIZE_ALIGN_32(x)    (((x) + 31) / 32 * 32)
-+
-+static enum cz_scratch_entry firmware_list[] = {
-+	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
-+};
-+
-+static int cz_smum_get_argument(struct pp_smumgr *smumgr)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	return cgs_read_register(smumgr->device,
-+					mmSMU_MP1_SRBM2P_ARG_0);
-+}
-+
-+static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
-+								uint16_t msg)
-+{
-+	int result = 0;
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
-+					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] cz_send_msg_to_smc_async failed\n");
-+		return result;
-+	}
-+
-+	cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
-+	cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
-+
-+	return 0;
-+}
-+
-+/* Send a message to the SMC, and wait for its response.*/
-+static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	int result = 0;
-+
-+	result = cz_send_msg_to_smc_async(smumgr, msg);
-+	if (result != 0)
-+		return result;
-+
-+	result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
-+					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
-+
-+	if (result != 0)
-+		return result;
-+
-+	return 0;
-+}
-+
-+static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
-+				     uint32_t smc_address, uint32_t limit)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	if (0 != (3 & smc_address)) {
-+		printk(KERN_ERR "[ powerplay ] SMC address must be 4 byte aligned\n");
-+		return -1;
-+	}
-+
-+	if (limit <= (smc_address + 3)) {
-+		printk(KERN_ERR "[ powerplay ] SMC address beyond the SMC RAM area\n");
-+		return -1;
-+	}
-+
-+	cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0,
-+				SMN_MP1_SRAM_START_ADDR + smc_address);
-+
-+	return 0;
-+}
-+
-+static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr,
-+		uint32_t smc_address, uint32_t value, uint32_t limit)
-+{
-+	int result;
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	result = cz_set_smc_sram_address(smumgr, smc_address, limit);
-+	cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value);
-+
-+	return 0;
-+}
-+
-+static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+					  uint16_t msg, uint32_t parameter)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
-+
-+	return cz_send_msg_to_smc(smumgr, msg);
-+}
-+
-+static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend);
-+	int result = 0;
-+	uint32_t smc_address;
-+
-+	if (!smumgr->reload_fw) {
-+		printk(KERN_INFO "[ powerplay ] skip reloading...\n");
-+		return 0;
-+	}
-+
-+	smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
-+		offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
-+
-+	cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+					PPSMC_MSG_DriverDramAddrHi,
-+					cz_smu->toc_buffer.mc_addr_high);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+					PPSMC_MSG_DriverDramAddrLo,
-+					cz_smu->toc_buffer.mc_addr_low);
-+
-+	cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+					PPSMC_MSG_ExecuteJob,
-+					cz_smu->toc_entry_aram);
-+	cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
-+				cz_smu->toc_entry_power_profiling_index);
-+
-+	result = cz_send_msg_to_smc_with_parameter(smumgr,
-+					PPSMC_MSG_ExecuteJob,
-+					cz_smu->toc_entry_initialize_index);
-+
-+	return result;
-+}
-+
-+static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
-+				   uint32_t firmware)
-+{
-+	int i;
-+	uint32_t index = SMN_MP1_SRAM_START_ADDR +
-+			 SMU8_FIRMWARE_HEADER_LOCATION +
-+			 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	return cgs_read_register(smumgr->device,
-+					mmSMU_MP1_SRBM2P_ARG_0);
-+
-+	cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index);
-+
-+	for (i = 0; i < smumgr->usec_timeout; i++) {
-+		if (firmware ==
-+			(cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware))
-+			break;
-+		udelay(1);
-+	}
-+
-+	if (i >= smumgr->usec_timeout) {
-+		printk(KERN_ERR "[ powerplay ] SMU check loaded firmware failed.\n");
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
-+{
-+	uint32_t reg_data;
-+	uint32_t tmp;
-+	int ret = 0;
-+	struct cgs_firmware_info info = {0};
-+	struct cz_smumgr *cz_smu;
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	ret = cgs_get_firmware_info(smumgr->device,
-+						CGS_UCODE_ID_CP_MEC, &info);
-+
-+	if (ret)
-+		return -EINVAL;
-+
-+	/* Disable MEC parsing/prefetching */
-+	tmp = cgs_read_register(smumgr->device,
-+					mmCP_MEC_CNTL);
-+	tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
-+	tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
-+	cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp);
-+
-+	tmp = cgs_read_register(smumgr->device,
-+					mmCP_CPC_IC_BASE_CNTL);
-+
-+	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
-+	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
-+	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
-+	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
-+	cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
-+
-+	reg_data = smu_lower_32_bits(info.mc_addr) &
-+			SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
-+	cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
-+
-+	reg_data = smu_upper_32_bits(info.mc_addr) &
-+			SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
-+	cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
-+
-+	return 0;
-+}
-+
-+static int cz_start_smu(struct pp_smumgr *smumgr)
-+{
-+	int ret = 0;
-+	uint32_t fw_to_check = UCODE_ID_RLC_G_MASK |
-+				UCODE_ID_SDMA0_MASK |
-+				UCODE_ID_SDMA1_MASK |
-+				UCODE_ID_CP_CE_MASK |
-+				UCODE_ID_CP_ME_MASK |
-+				UCODE_ID_CP_PFP_MASK |
-+				UCODE_ID_CP_MEC_JT1_MASK |
-+				UCODE_ID_CP_MEC_JT2_MASK;
-+
-+	cz_request_smu_load_fw(smumgr);
-+	cz_check_fw_load_finish(smumgr, fw_to_check);
-+
-+	ret = cz_load_mec_firmware(smumgr);
-+	if (ret)
-+		printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n");
-+
-+	return ret;
-+}
-+
-+static uint8_t cz_translate_firmware_enum_to_arg(
-+			enum cz_scratch_entry firmware_enum)
-+{
-+	uint8_t ret = 0;
-+
-+	switch (firmware_enum) {
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0:
-+		ret = UCODE_ID_SDMA0;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
-+		ret = UCODE_ID_SDMA1;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
-+		ret = UCODE_ID_CP_CE;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
-+		ret = UCODE_ID_CP_PFP;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME:
-+		ret = UCODE_ID_CP_ME;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
-+		ret = UCODE_ID_CP_MEC_JT1;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
-+		ret = UCODE_ID_CP_MEC_JT2;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
-+		ret = UCODE_ID_GMCON_RENG;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G:
-+		ret = UCODE_ID_RLC_G;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
-+		ret = UCODE_ID_RLC_SCRATCH;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
-+		ret = UCODE_ID_RLC_SRM_ARAM;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
-+		ret = UCODE_ID_RLC_SRM_DRAM;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
-+		ret = UCODE_ID_DMCU_ERAM;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
-+		ret = UCODE_ID_DMCU_IRAM;
-+		break;
-+	case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
-+		ret = TASK_ARG_INIT_MM_PWR_LOG;
-+		break;
-+	case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
-+	case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
-+	case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
-+	case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
-+	case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START:
-+	case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
-+		ret = TASK_ARG_REG_MMIO;
-+		break;
-+	case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
-+		ret = TASK_ARG_INIT_CLK_TABLE;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
-+{
-+	enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SDMA0:
-+		result = CGS_UCODE_ID_SDMA0;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = CGS_UCODE_ID_SDMA1;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = CGS_UCODE_ID_CP_CE;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = CGS_UCODE_ID_CP_PFP;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = CGS_UCODE_ID_CP_ME;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+		result = CGS_UCODE_ID_CP_MEC_JT1;
-+		break;
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = CGS_UCODE_ID_CP_MEC_JT2;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = CGS_UCODE_ID_RLC_G;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+static int cz_smu_populate_single_scratch_task(
-+			struct pp_smumgr *smumgr,
-+			enum cz_scratch_entry fw_enum,
-+			uint8_t type, bool is_last)
-+{
-+	uint8_t i;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
-+	struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
-+
-+	task->type = type;
-+	task->arg = cz_translate_firmware_enum_to_arg(fw_enum);
-+	task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
-+
-+	for (i = 0; i < cz_smu->scratch_buffer_length; i++)
-+		if (cz_smu->scratch_buffer[i].firmware_ID == fw_enum)
-+			break;
-+
-+	if (i >= cz_smu->scratch_buffer_length) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n");
-+		return -EINVAL;
-+	}
-+
-+	task->addr.low = cz_smu->scratch_buffer[i].mc_addr_low;
-+	task->addr.high = cz_smu->scratch_buffer[i].mc_addr_high;
-+	task->size_bytes = cz_smu->scratch_buffer[i].data_size;
-+
-+	if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
-+		struct cz_ih_meta_data *pIHReg_restore =
-+		     (struct cz_ih_meta_data *)cz_smu->scratch_buffer[i].kaddr;
-+		pIHReg_restore->command =
-+			METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_smu_populate_single_ucode_load_task(
-+					struct pp_smumgr *smumgr,
-+					enum cz_scratch_entry fw_enum,
-+					bool is_last)
-+{
-+	uint8_t i;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
-+	struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
-+
-+	task->type = TASK_TYPE_UCODE_LOAD;
-+	task->arg = cz_translate_firmware_enum_to_arg(fw_enum);
-+	task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
-+
-+	for (i = 0; i < cz_smu->driver_buffer_length; i++)
-+		if (cz_smu->driver_buffer[i].firmware_ID == fw_enum)
-+			break;
-+
-+	if (i >= cz_smu->driver_buffer_length) {
-+		printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n");
-+		return -EINVAL;
-+	}
-+
-+	task->addr.low = cz_smu->driver_buffer[i].mc_addr_low;
-+	task->addr.high = cz_smu->driver_buffer[i].mc_addr_high;
-+	task->size_bytes = cz_smu->driver_buffer[i].data_size;
-+
-+	return 0;
-+}
-+
-+static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+
-+	cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
-+				TASK_TYPE_UCODE_SAVE, true);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
-+{
-+	int i;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
-+
-+	for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
-+		toc->JobList[i] = (uint8_t)IGNORE_JOB;
-+
-+	return 0;
-+}
-+
-+static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
-+
-+	toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				    CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
-+				    TASK_TYPE_UCODE_SAVE, false);
-+
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				    CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
-+				    TASK_TYPE_UCODE_SAVE, true);
-+
-+	return 0;
-+}
-+
-+
-+static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
-+
-+	toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
-+
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
-+
-+	/* populate scratch */
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
-+				TASK_TYPE_UCODE_LOAD, false);
-+
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
-+				TASK_TYPE_UCODE_LOAD, false);
-+
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
-+				TASK_TYPE_UCODE_LOAD, true);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_construct_toc_for_power_profiling(
-+						 struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+
-+	cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
-+
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
-+				TASK_TYPE_INITIALIZE, true);
-+	return 0;
-+}
-+
-+static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+
-+	cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
-+
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
-+	cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+
-+	cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
-+
-+	cz_smu_populate_single_scratch_task(smumgr,
-+				CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
-+				TASK_TYPE_INITIALIZE, true);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_construct_toc(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+
-+	cz_smu->toc_entry_used_count = 0;
-+
-+	cz_smu_initialize_toc_empty_job_list(smumgr);
-+
-+	cz_smu_construct_toc_for_rlc_aram_save(smumgr);
-+
-+	cz_smu_construct_toc_for_vddgfx_enter(smumgr);
-+
-+	cz_smu_construct_toc_for_vddgfx_exit(smumgr);
-+
-+	cz_smu_construct_toc_for_power_profiling(smumgr);
-+
-+	cz_smu_construct_toc_for_bootup(smumgr);
-+
-+	cz_smu_construct_toc_for_clock_table(smumgr);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	uint32_t firmware_type;
-+	uint32_t i;
-+	int ret;
-+	enum cgs_ucode_id ucode_id;
-+	struct cgs_firmware_info info = {0};
-+
-+	cz_smu->driver_buffer_length = 0;
-+
-+	for (i = 0; i < sizeof(firmware_list)/sizeof(*firmware_list); i++) {
-+
-+		firmware_type = cz_translate_firmware_enum_to_arg(
-+					firmware_list[i]);
-+
-+		ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
-+
-+		ret = cgs_get_firmware_info(smumgr->device,
-+							ucode_id, &info);
-+
-+		if (ret == 0) {
-+			cz_smu->driver_buffer[i].mc_addr_high =
-+					smu_upper_32_bits(info.mc_addr);
-+
-+			cz_smu->driver_buffer[i].mc_addr_low =
-+					smu_lower_32_bits(info.mc_addr);
-+
-+			cz_smu->driver_buffer[i].data_size = info.image_size;
-+
-+			cz_smu->driver_buffer[i].firmware_ID = firmware_list[i];
-+			cz_smu->driver_buffer_length++;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_smu_populate_single_scratch_entry(
-+				struct pp_smumgr *smumgr,
-+				enum cz_scratch_entry scratch_type,
-+				uint32_t ulsize_byte,
-+				struct cz_buffer_entry *entry)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	long long mc_addr =
-+			((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
-+			| cz_smu->smu_buffer.mc_addr_low;
-+
-+	uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);
-+
-+	mc_addr += cz_smu->smu_buffer_used_bytes;
-+
-+	entry->data_size = ulsize_byte;
-+	entry->kaddr = (char *) cz_smu->smu_buffer.kaddr +
-+				cz_smu->smu_buffer_used_bytes;
-+	entry->mc_addr_low = smu_lower_32_bits(mc_addr);
-+	entry->mc_addr_high = smu_upper_32_bits(mc_addr);
-+	entry->firmware_ID = scratch_type;
-+
-+	cz_smu->smu_buffer_used_bytes += ulsize_aligned;
-+
-+	return 0;
-+}
-+
-+static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	unsigned long i;
-+
-+	for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
-+		if (cz_smu->scratch_buffer[i].firmware_ID
-+			== CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
-+			break;
-+	}
-+
-+	*table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+				PPSMC_MSG_SetClkTableAddrHi,
-+				cz_smu->scratch_buffer[i].mc_addr_high);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+				PPSMC_MSG_SetClkTableAddrLo,
-+				cz_smu->scratch_buffer[i].mc_addr_low);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
-+				cz_smu->toc_entry_clock_table);
-+
-+	cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram);
-+
-+	return 0;
-+}
-+
-+static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	unsigned long i;
-+
-+	for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
-+		if (cz_smu->scratch_buffer[i].firmware_ID
-+				== CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
-+			break;
-+	}
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+				PPSMC_MSG_SetClkTableAddrHi,
-+				cz_smu->scratch_buffer[i].mc_addr_high);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr,
-+				PPSMC_MSG_SetClkTableAddrLo,
-+				cz_smu->scratch_buffer[i].mc_addr_low);
-+
-+	cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
-+				cz_smu->toc_entry_clock_table);
-+
-+	cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_init(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	uint64_t mc_addr = 0;
-+	int ret = 0;
-+
-+	cz_smu->toc_buffer.data_size = 4096;
-+	cz_smu->smu_buffer.data_size =
-+		ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
-+		ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) +
-+		ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) +
-+		ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
-+		ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
-+
-+	ret = smu_allocate_memory(smumgr->device,
-+				cz_smu->toc_buffer.data_size,
-+				CGS_GPU_MEM_TYPE__GART_CACHEABLE,
-+				PAGE_SIZE,
-+				&mc_addr,
-+				&cz_smu->toc_buffer.kaddr,
-+				&cz_smu->toc_buffer.handle);
-+	if (ret != 0)
-+		return -1;
-+
-+	cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	ret = smu_allocate_memory(smumgr->device,
-+				cz_smu->smu_buffer.data_size,
-+				CGS_GPU_MEM_TYPE__GART_CACHEABLE,
-+				PAGE_SIZE,
-+				&mc_addr,
-+				&cz_smu->smu_buffer.kaddr,
-+				&cz_smu->smu_buffer.handle);
-+	if (ret != 0)
-+		return -1;
-+
-+	cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	cz_smu_populate_firmware_entries(smumgr);
-+	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
-+		UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
-+		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-+		printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
-+		return -1;
-+	}
-+
-+	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
-+		UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
-+		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-+		printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
-+		return -1;
-+	}
-+	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
-+		UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
-+		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-+		printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
-+		return -1;
-+	}
-+
-+	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+		CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
-+		sizeof(struct SMU8_MultimediaPowerLogData),
-+		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-+		printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
-+		return -1;
-+	}
-+
-+	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+		CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
-+		sizeof(struct SMU8_Fusion_ClkTable),
-+		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-+		printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
-+		return -1;
-+	}
-+	cz_smu_construct_toc(smumgr);
-+
-+	return 0;
-+}
-+
-+static int cz_smu_fini(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu;
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	if (!cz_smu) {
-+		cgs_free_gpu_mem(smumgr->device,
-+				cz_smu->toc_buffer.handle);
-+		cgs_free_gpu_mem(smumgr->device,
-+				cz_smu->smu_buffer.handle);
-+		kfree(cz_smu);
-+		kfree(smumgr);
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct pp_smumgr_func cz_smu_funcs = {
-+	.smu_init = cz_smu_init,
-+	.smu_fini = cz_smu_fini,
-+	.start_smu = cz_start_smu,
-+	.check_fw_load_finish = cz_check_fw_load_finish,
-+	.request_smu_load_fw = NULL,
-+	.request_smu_load_specific_fw = NULL,
-+	.get_argument = cz_smum_get_argument,
-+	.send_msg_to_smc = cz_send_msg_to_smc,
-+	.send_msg_to_smc_with_parameter = cz_send_msg_to_smc_with_parameter,
-+	.download_pptable_settings = cz_download_pptable_settings,
-+	.upload_pptable_settings = cz_upload_pptable_settings,
-+};
-+
-+int cz_smum_init(struct pp_smumgr *smumgr)
-+{
-+	struct cz_smumgr *cz_smu;
-+
-+	cz_smu = kzalloc(sizeof(struct cz_smumgr), GFP_KERNEL);
-+	if (cz_smu == NULL)
-+		return -ENOMEM;
-+
-+	smumgr->backend = cz_smu;
-+	smumgr->smumgr_funcs = &cz_smu_funcs;
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h
-new file mode 100644
-index 0000000..8838180
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _CZ_SMUMGR_H_
-+#define _CZ_SMUMGR_H_
-+
-+
-+#define MAX_NUM_FIRMWARE                        8
-+#define MAX_NUM_SCRATCH                         11
-+#define CZ_SCRATCH_SIZE_NONGFX_CLOCKGATING      1024
-+#define CZ_SCRATCH_SIZE_NONGFX_GOLDENSETTING    2048
-+#define CZ_SCRATCH_SIZE_SDMA_METADATA           1024
-+#define CZ_SCRATCH_SIZE_IH                      ((2*256+1)*4)
-+
-+enum cz_scratch_entry {
-+	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
-+	CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
-+	CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
-+	CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
-+	CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
-+	CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
-+	CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START,
-+	CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
-+	CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
-+};
-+
-+struct cz_buffer_entry {
-+	uint32_t data_size;
-+	uint32_t mc_addr_low;
-+	uint32_t mc_addr_high;
-+	void *kaddr;
-+	enum cz_scratch_entry firmware_ID;
-+	unsigned long handle; /* as bo handle used when release bo */
-+};
-+
-+struct cz_register_index_data_pair {
-+	uint32_t offset;
-+	uint32_t value;
-+};
-+
-+struct cz_ih_meta_data {
-+	uint32_t command;
-+	struct cz_register_index_data_pair register_index_value_pair[1];
-+};
-+
-+struct cz_smumgr {
-+	uint8_t driver_buffer_length;
-+	uint8_t scratch_buffer_length;
-+	uint16_t toc_entry_used_count;
-+	uint16_t toc_entry_initialize_index;
-+	uint16_t toc_entry_power_profiling_index;
-+	uint16_t toc_entry_aram;
-+	uint16_t toc_entry_ih_register_restore_task_index;
-+	uint16_t toc_entry_clock_table;
-+	uint16_t ih_register_restore_task_size;
-+	uint16_t smu_buffer_used_bytes;
-+
-+	struct cz_buffer_entry toc_buffer;
-+	struct cz_buffer_entry smu_buffer;
-+	struct cz_buffer_entry firmware_buffer;
-+	struct cz_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
-+	struct cz_buffer_entry meta_data_buffer[MAX_NUM_FIRMWARE];
-+	struct cz_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
-+};
-+
-+struct pp_smumgr;
-+
-+extern int cz_smum_init(struct pp_smumgr *smumgr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-index 1a11714..9ff5d33 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-@@ -27,6 +27,7 @@
- #include "smumgr.h"
- #include "cgs_common.h"
- #include "linux/delay.h"
-+#include "cz_smumgr.h"
- 
- int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -49,7 +50,7 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 
- 	switch (smumgr->chip_family) {
- 	case AMD_FAMILY_CZ:
--		/* TODO */
-+		cz_smum_init(smumgr);
- 		break;
- 	case AMD_FAMILY_VI:
- 		/* TODO */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch b/common/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch
deleted file mode 100644
index 317c6730..00000000
--- a/common/recipes-kernel/linux/files/0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch
+++ /dev/null
@@ -1,1283 +0,0 @@
-From bab619f2322c11d323bd5dd451cff5c7d7db49fc Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Wed, 22 Jul 2015 10:41:30 +0800
-Subject: [PATCH 0046/1110] drm/amd/powerplay: add Carrizo dpm support
-
-This patch enables basic DPM support for Carrizo.
-DPM handles dynamic clock and voltage scaling.
-
-v3: delete peci sub-module
-v2: use cgs interface directly
-    correct define SMU_EnabledFeatureScoreboard_SclkDpmOn
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |   2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 898 +++++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h | 309 +++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c    |   6 +-
- 4 files changed, 1212 insertions(+), 3 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index ef529e0..22d383e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -3,7 +3,7 @@
- # It provides the hardware management services for the driver.
- 
- HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
--	       hardwaremanager.o pp_acpi.o
-+	       hardwaremanager.o pp_acpi.o cz_hwmgr.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-new file mode 100644
-index 0000000..0c49505
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -0,0 +1,898 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include "atom-types.h"
-+#include "atombios.h"
-+#include "processpptables.h"
-+#include "cgs_common.h"
-+#include "smu/smu_8_0_d.h"
-+#include "smumgr.h"
-+#include "hwmgr.h"
-+#include "hardwaremanager.h"
-+#include "cz_ppsmc.h"
-+#include "cz_hwmgr.h"
-+#include "power_state.h"
-+
-+static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
-+
-+static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
-+{
-+	if (PhwCz_Magic != hw_ps->magic)
-+		return NULL;
-+
-+	return (struct cz_power_state *)hw_ps;
-+}
-+
-+static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
-+				uint32_t clock, uint32_t msg)
-+{
-+	int i = 0;
-+	struct phm_clock_voltage_dependency_table *table =
-+				hwmgr->dyn_state.vddc_dependency_on_sclk;
-+
-+	switch (msg) {
-+	case PPSMC_MSG_SetSclkSoftMin:
-+	case PPSMC_MSG_SetSclkHardMin:
-+		for (i = 0; i < (int)table->count; i++) {
-+			if (clock <= table->entries[i].clk)
-+				break;
-+		}
-+		break;
-+
-+	case PPSMC_MSG_SetSclkSoftMax:
-+	case PPSMC_MSG_SetSclkHardMax:
-+		for (i = table->count - 1; i >= 0; i--) {
-+			if (clock >= table->entries[i].clk)
-+				break;
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+	return i;
-+}
-+
-+static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (cz_hwmgr->max_sclk_level == 0) {
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
-+		cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
-+	}
-+
-+	return cz_hwmgr->max_sclk_level;
-+}
-+
-+static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	uint32_t i;
-+
-+	cz_hwmgr->gfx_ramp_step = 256*25/100;
-+
-+	cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
-+
-+	for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
-+		cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
-+
-+	cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
-+	cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
-+
-+	cz_hwmgr->clock_slow_down_freq = 25000;
-+
-+	cz_hwmgr->skip_clock_slow_down = 1;
-+
-+	cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
-+
-+	cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
-+
-+	cz_hwmgr->voting_rights_clients = 0x00C00033;
-+
-+	cz_hwmgr->static_screen_threshold = 8;
-+
-+	cz_hwmgr->ddi_power_gating_disabled = 0;
-+
-+	cz_hwmgr->bapm_enabled = 1;
-+
-+	cz_hwmgr->voltage_drop_threshold = 0;
-+
-+	cz_hwmgr->gfx_power_gating_threshold = 500;
-+
-+	cz_hwmgr->vce_slow_sclk_threshold = 20000;
-+
-+	cz_hwmgr->dce_slow_sclk_threshold = 30000;
-+
-+	cz_hwmgr->disable_driver_thermal_policy = 1;
-+
-+	cz_hwmgr->disable_nb_ps3_in_battery = 0;
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+							PHM_PlatformCaps_ABM);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_NonABMSupportInPPLib);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					   PHM_PlatformCaps_SclkDeepSleep);
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_DynamicM3Arbiter);
-+
-+	cz_hwmgr->override_dynamic_mgpg = 1;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				  PHM_PlatformCaps_DynamicPatchPowerState);
-+
-+	cz_hwmgr->thermal_auto_throttling_treshold = 0;
-+
-+	cz_hwmgr->tdr_clock = 0;
-+
-+	cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_DynamicUVDState);
-+
-+	cz_hwmgr->is_nb_dpm_enabled_by_driver = 1;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				   PHM_PlatformCaps_DisableVoltageIsland);
-+
-+	return 0;
-+}
-+
-+static uint32_t cz_convert_8Bit_index_to_voltage(
-+			struct pp_hwmgr *hwmgr, uint16_t voltage)
-+{
-+	return 6200 - (voltage * 25);
-+}
-+
-+static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
-+			struct phm_clock_and_voltage_limits *table)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
-+	struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
-+	struct phm_clock_voltage_dependency_table *dep_table =
-+				hwmgr->dyn_state.vddc_dependency_on_sclk;
-+
-+	if (dep_table->count > 0) {
-+		table->sclk = dep_table->entries[dep_table->count-1].clk;
-+		table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
-+		   (uint16_t)dep_table->entries[dep_table->count-1].v);
-+	}
-+	table->mclk = sys_info->nbp_memory_clock[0];
-+	return 0;
-+}
-+
-+static int cz_init_dynamic_state_adjustment_rule_settings(
-+			struct pp_hwmgr *hwmgr,
-+			ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
-+{
-+	uint32_t table_size =
-+		sizeof(struct phm_clock_voltage_dependency_table) +
-+		(7 * sizeof(struct phm_clock_voltage_dependency_record));
-+
-+	struct phm_clock_voltage_dependency_table *table_clk_vlt =
-+					kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == table_clk_vlt) {
-+		printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
-+		return -ENOMEM;
-+	}
-+
-+	table_clk_vlt->count = 8;
-+	table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
-+	table_clk_vlt->entries[0].v = 0;
-+	table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
-+	table_clk_vlt->entries[1].v = 1;
-+	table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
-+	table_clk_vlt->entries[2].v = 2;
-+	table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
-+	table_clk_vlt->entries[3].v = 3;
-+	table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
-+	table_clk_vlt->entries[4].v = 4;
-+	table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
-+	table_clk_vlt->entries[5].v = 5;
-+	table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
-+	table_clk_vlt->entries[6].v = 6;
-+	table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
-+	table_clk_vlt->entries[7].v = 7;
-+	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-+
-+	return 0;
-+}
-+
-+static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
-+	ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
-+	uint32_t i;
-+	int result = 0;
-+	uint8_t frev, crev;
-+	uint16_t size;
-+
-+	info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
-+			hwmgr->device,
-+			GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
-+			&size, &frev, &crev);
-+
-+	if (crev != 9) {
-+		printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
-+		return -EINVAL;
-+	}
-+
-+	if (info == NULL) {
-+		printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
-+		return -EINVAL;
-+	}
-+
-+	cz_hwmgr->sys_info.bootup_uma_clock =
-+				   le32_to_cpu(info->ulBootUpUMAClock);
-+
-+	cz_hwmgr->sys_info.bootup_engine_clock =
-+				le32_to_cpu(info->ulBootUpEngineClock);
-+
-+	cz_hwmgr->sys_info.dentist_vco_freq =
-+				   le32_to_cpu(info->ulDentistVCOFreq);
-+
-+	cz_hwmgr->sys_info.system_config =
-+				     le32_to_cpu(info->ulSystemConfig);
-+
-+	cz_hwmgr->sys_info.bootup_nb_voltage_index =
-+				  le16_to_cpu(info->usBootUpNBVoltage);
-+
-+	cz_hwmgr->sys_info.htc_hyst_lmt =
-+			(info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
-+
-+	cz_hwmgr->sys_info.htc_tmp_lmt =
-+			(info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
-+
-+	if (cz_hwmgr->sys_info.htc_tmp_lmt <=
-+			cz_hwmgr->sys_info.htc_hyst_lmt) {
-+		printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
-+		return -EINVAL;
-+	}
-+
-+	cz_hwmgr->sys_info.nb_dpm_enable =
-+				cz_hwmgr->enable_nb_ps_policy &&
-+				(le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
-+
-+	for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
-+		if (i < CZ_NUM_NBPMEMORYCLOCK) {
-+			cz_hwmgr->sys_info.nbp_memory_clock[i] =
-+			  le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
-+		}
-+		cz_hwmgr->sys_info.nbp_n_clock[i] =
-+			    le32_to_cpu(info->ulNbpStateNClkFreq[i]);
-+	}
-+
-+	for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
-+		cz_hwmgr->sys_info.display_clock[i] =
-+					le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
-+	}
-+
-+	/* Here use 4 levels, make sure not exceed */
-+	for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
-+		cz_hwmgr->sys_info.nbp_voltage_index[i] =
-+			     le16_to_cpu(info->usNBPStateVoltage[i]);
-+	}
-+
-+	if (!cz_hwmgr->sys_info.nb_dpm_enable) {
-+		for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
-+			if (i < CZ_NUM_NBPMEMORYCLOCK) {
-+				cz_hwmgr->sys_info.nbp_memory_clock[i] =
-+				    cz_hwmgr->sys_info.nbp_memory_clock[0];
-+			}
-+			cz_hwmgr->sys_info.nbp_n_clock[i] =
-+				    cz_hwmgr->sys_info.nbp_n_clock[0];
-+			cz_hwmgr->sys_info.nbp_voltage_index[i] =
-+				    cz_hwmgr->sys_info.nbp_voltage_index[0];
-+		}
-+	}
-+
-+	if (le32_to_cpu(info->ulGPUCapInfo) &
-+		SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_EnableDFSBypass);
-+	}
-+
-+	cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
-+
-+	cz_construct_max_power_limits_table (hwmgr,
-+				    &hwmgr->dyn_state.max_clock_voltage_on_ac);
-+
-+	cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
-+				    &info->sDISPCLK_Voltage[0]);
-+
-+	return result;
-+}
-+
-+static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	cz_hwmgr->boot_power_level.engineClock =
-+				cz_hwmgr->sys_info.bootup_engine_clock;
-+
-+	cz_hwmgr->boot_power_level.vddcIndex =
-+			(uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
-+
-+	cz_hwmgr->boot_power_level.dsDividerIndex = 0;
-+
-+	cz_hwmgr->boot_power_level.ssDividerIndex = 0;
-+
-+	cz_hwmgr->boot_power_level.allowGnbSlow = 1;
-+
-+	cz_hwmgr->boot_power_level.forceNBPstate = 0;
-+
-+	cz_hwmgr->boot_power_level.hysteresis_up = 0;
-+
-+	cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
-+
-+	cz_hwmgr->boot_power_level.display_wm = 0;
-+
-+	cz_hwmgr->boot_power_level.vce_wm = 0;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
-+					void *output, void *storage, int result)
-+{
-+	return 0;
-+}
-+
-+static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
-+					void *output, void *storage, int result)
-+{
-+	return 0;
-+}
-+
-+static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
-+				 void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_clock_voltage_dependency_table *table =
-+					hwmgr->dyn_state.vddc_dependency_on_sclk;
-+	unsigned long clock = 0, level;
-+
-+	if (NULL == table && table->count <= 0)
-+		return -EINVAL;
-+
-+	cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
-+	cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
-+
-+	level = cz_get_max_sclk_level(hwmgr) - 1;
-+
-+	if (level < table->count)
-+		clock = table->entries[level].clk;
-+	else
-+		clock = table->entries[table->count - 1].clk;
-+
-+	cz_hwmgr->sclk_dpm.soft_max_clk = clock;
-+	cz_hwmgr->sclk_dpm.hard_max_clk = clock;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_uvd_clock_voltage_dependency_table *table =
-+				hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+	unsigned long clock = 0, level;
-+
-+	if (NULL == table && table->count <= 0)
-+		return -EINVAL;
-+
-+	cz_hwmgr->uvd_dpm.soft_min_clk = 0;
-+	cz_hwmgr->uvd_dpm.hard_min_clk = 0;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
-+	level = smum_get_argument(hwmgr->smumgr);
-+
-+	if (level < table->count)
-+		clock = table->entries[level].vclk;
-+	else
-+		clock = table->entries[table->count - 1].vclk;
-+
-+	cz_hwmgr->uvd_dpm.soft_max_clk = clock;
-+	cz_hwmgr->uvd_dpm.hard_max_clk = clock;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_vce_clock_voltage_dependency_table *table =
-+				hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+	unsigned long clock = 0, level;
-+
-+	if (NULL == table && table->count <= 0)
-+		return -EINVAL;
-+
-+	cz_hwmgr->vce_dpm.soft_min_clk = 0;
-+	cz_hwmgr->vce_dpm.hard_min_clk = 0;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
-+	level = smum_get_argument(hwmgr->smumgr);
-+
-+	if (level < table->count)
-+		clock = table->entries[level].ecclk;
-+	else
-+		clock = table->entries[table->count - 1].ecclk;
-+
-+	cz_hwmgr->vce_dpm.soft_max_clk = clock;
-+	cz_hwmgr->vce_dpm.hard_max_clk = clock;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_acp_clock_voltage_dependency_table *table =
-+				hwmgr->dyn_state.acp_clock_voltage_dependency_table;
-+	unsigned long clock = 0, level;
-+
-+	if (NULL == table && table->count <= 0)
-+		return -EINVAL;
-+
-+	cz_hwmgr->acp_dpm.soft_min_clk = 0;
-+	cz_hwmgr->acp_dpm.hard_min_clk = 0;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
-+	level = smum_get_argument(hwmgr->smumgr);
-+
-+	if (level < table->count)
-+		clock = table->entries[level].acpclk;
-+	else
-+		clock = table->entries[table->count - 1].acpclk;
-+
-+	cz_hwmgr->acp_dpm.soft_max_clk = clock;
-+	cz_hwmgr->acp_dpm.hard_max_clk = clock;
-+	return 0;
-+}
-+
-+static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	cz_hwmgr->uvd_power_gated = false;
-+	cz_hwmgr->vce_power_gated = false;
-+	cz_hwmgr->samu_power_gated = false;
-+	cz_hwmgr->acp_power_gated = false;
-+	cz_hwmgr->pgacpinit = true;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	cz_hwmgr->low_sclk_interrupt_threshold = 0;
-+
-+	return 0;
-+}
-+
-+static struct phm_master_table_item cz_setup_asic_list[] = {
-+	{NULL, cz_tf_reset_active_process_mask},
-+	{NULL, cz_tf_upload_pptable_to_smu},
-+	{NULL, cz_tf_init_sclk_limit},
-+	{NULL, cz_tf_init_uvd_limit},
-+	{NULL, cz_tf_init_vce_limit},
-+	{NULL, cz_tf_init_acp_limit},
-+	{NULL, cz_tf_init_power_gate_state},
-+	{NULL, cz_tf_init_sclk_threshold},
-+	{NULL, NULL}
-+};
-+
-+static struct phm_master_table_header cz_setup_asic_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	cz_setup_asic_list
-+};
-+
-+static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
-+				PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
-+	return 0;
-+}
-+
-+static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
-+			   void *storage, int result)
-+{
-+	int res = 0xff;
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	unsigned long dpm_features = 0;
-+
-+	cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
-+	dpm_features |= SCLK_DPM_MASK;
-+
-+	res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_EnableAllSmuFeatures,
-+				dpm_features);
-+
-+	return res;
-+}
-+
-+static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
-+	cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMin,
-+				cz_get_sclk_level(hwmgr,
-+				cz_hwmgr->sclk_dpm.soft_min_clk,
-+				PPSMC_MSG_SetSclkSoftMin));
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMax,
-+				cz_get_sclk_level(hwmgr,
-+				cz_hwmgr->sclk_dpm.soft_max_clk,
-+				PPSMC_MSG_SetSclkSoftMax));
-+
-+	return 0;
-+}
-+
-+int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	cz_hwmgr->acp_boot_level = 0xff;
-+	return 0;
-+}
-+
-+static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
-+				unsigned long check_feature)
-+{
-+	int result;
-+	unsigned long features;
-+
-+	result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
-+	if (result == 0) {
-+		features = smum_get_argument(hwmgr->smumgr);
-+		if (features & check_feature)
-+			return true;
-+	}
-+
-+	return result;
-+}
-+
-+static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
-+		return PP_Result_TableImmediateExit;
-+	return 0;
-+}
-+
-+static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
-+				void *output, void *storage, int result)
-+{
-+	/* TO DO */
-+	return 0;
-+}
-+
-+static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
-+						void *input, void *output,
-+						void *storage, int result)
-+{
-+	if (!cz_dpm_check_smu_features(hwmgr,
-+			     SMU_EnabledFeatureScoreboard_SclkDpmOn))
-+		return PP_Result_TableImmediateExit;
-+	return 0;
-+}
-+
-+static struct phm_master_table_item cz_disable_dpm_list[] = {
-+	{ NULL, cz_tf_check_for_dpm_enabled},
-+	{NULL, NULL},
-+};
-+
-+
-+static struct phm_master_table_header cz_disable_dpm_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	cz_disable_dpm_list
-+};
-+
-+static struct phm_master_table_item cz_enable_dpm_list[] = {
-+	{ NULL, cz_tf_check_for_dpm_disabled },
-+	{ NULL, cz_tf_program_voting_clients },
-+	{ NULL, cz_tf_start_dpm},
-+	{ NULL, cz_tf_program_bootup_state},
-+	{ NULL, cz_tf_enable_didt },
-+	{ NULL, cz_tf_reset_acp_boot_level },
-+	{NULL, NULL},
-+};
-+
-+static struct phm_master_table_header cz_enable_dpm_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	cz_enable_dpm_list
-+};
-+
-+static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+
-+	result = cz_initialize_dpm_defaults(hwmgr);
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
-+		return result;
-+	}
-+
-+	result = cz_get_system_info_data(hwmgr);
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
-+		return result;
-+	}
-+
-+	cz_construct_boot_state(hwmgr);
-+
-+	result = phm_construct_table(hwmgr, &cz_setup_asic_master,
-+				&(hwmgr->setup_asic));
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
-+		return result;
-+	}
-+
-+	result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
-+				&(hwmgr->disable_dynamic_state_management));
-+
-+	result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
-+				&(hwmgr->enable_dynamic_state_management));
-+
-+	return result;
-+}
-+
-+static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr != NULL || hwmgr->backend != NULL) {
-+		kfree(hwmgr->backend);
-+		kfree(hwmgr);
-+	}
-+	return 0;
-+}
-+
-+int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (cz_hwmgr->sclk_dpm.soft_min_clk !=
-+				cz_hwmgr->sclk_dpm.soft_max_clk)
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SetSclkSoftMin,
-+						cz_get_sclk_level(hwmgr,
-+						cz_hwmgr->sclk_dpm.soft_max_clk,
-+						PPSMC_MSG_SetSclkSoftMin));
-+	return 0;
-+}
-+
-+int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_clock_voltage_dependency_table *table =
-+				hwmgr->dyn_state.vddc_dependency_on_sclk;
-+	unsigned long clock = 0, level;
-+
-+	if (NULL == table && table->count <= 0)
-+		return -EINVAL;
-+
-+	cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
-+	cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
-+
-+	level = cz_get_max_sclk_level(hwmgr) - 1;
-+
-+	if (level < table->count)
-+		clock = table->entries[level].clk;
-+	else
-+		clock = table->entries[table->count - 1].clk;
-+
-+	cz_hwmgr->sclk_dpm.soft_max_clk = clock;
-+	cz_hwmgr->sclk_dpm.hard_max_clk = clock;
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMin,
-+				cz_get_sclk_level(hwmgr,
-+				cz_hwmgr->sclk_dpm.soft_min_clk,
-+				PPSMC_MSG_SetSclkSoftMin));
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMax,
-+				cz_get_sclk_level(hwmgr,
-+				cz_hwmgr->sclk_dpm.soft_max_clk,
-+				PPSMC_MSG_SetSclkSoftMax));
-+
-+	return 0;
-+}
-+
-+int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (cz_hwmgr->sclk_dpm.soft_min_clk !=
-+				cz_hwmgr->sclk_dpm.soft_max_clk) {
-+		cz_hwmgr->sclk_dpm.soft_max_clk =
-+			cz_hwmgr->sclk_dpm.soft_min_clk;
-+
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMax,
-+				cz_get_sclk_level(hwmgr,
-+				cz_hwmgr->sclk_dpm.soft_max_clk,
-+				PPSMC_MSG_SetSclkSoftMax));
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
-+				enum amd_dpm_forced_level level)
-+{
-+	int ret = 0;
-+
-+	switch (level) {
-+	case AMD_DPM_FORCED_LEVEL_HIGH:
-+		ret = cz_phm_force_dpm_highest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_LOW:
-+		ret = cz_phm_force_dpm_lowest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_AUTO:
-+		ret = cz_phm_unforce_dpm_levels(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	hwmgr->dpm_level = level;
-+
-+	return ret;
-+}
-+
-+static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
-+					struct pp_hw_power_state *hw_ps)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
-+
-+	cz_ps->level = 1;
-+	cz_ps->nbps_flags = 0;
-+	cz_ps->bapm_flags = 0;
-+	cz_ps->levels[0] = cz_hwmgr->boot_power_level;
-+
-+	return 0;
-+}
-+
-+static int cz_dpm_get_pp_table_entry_callback(
-+						     struct pp_hwmgr *hwmgr,
-+					   struct pp_hw_power_state *hw_ps,
-+							  unsigned int index,
-+						     const void *clock_info)
-+{
-+	struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
-+
-+	const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
-+
-+	struct phm_clock_voltage_dependency_table *table =
-+				    hwmgr->dyn_state.vddc_dependency_on_sclk;
-+	uint8_t clock_info_index = cz_clock_info->index;
-+
-+	if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
-+		clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
-+
-+	cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
-+	cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
-+
-+	cz_ps->level = index + 1;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+		cz_ps->levels[index].dsDividerIndex = 5;
-+		cz_ps->levels[index].ssDividerIndex = 5;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	unsigned long ret = 0;
-+
-+	result = pp_tables_get_num_of_entries(hwmgr, &ret);
-+
-+	return result ? 0 : ret;
-+}
-+
-+static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
-+		    unsigned long entry, struct pp_power_state *ps)
-+{
-+	int result;
-+	struct cz_power_state *cz_ps;
-+
-+	ps->hardware.magic = PhwCz_Magic;
-+
-+	cz_ps = cast_PhwCzPowerState(&(ps->hardware));
-+
-+	result = pp_tables_get_entry(hwmgr, entry, ps,
-+			cz_dpm_get_pp_table_entry_callback);
-+
-+	cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
-+	cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
-+
-+	return result;
-+}
-+
-+int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
-+{
-+	return sizeof(struct cz_power_state);
-+}
-+
-+static const struct pp_hwmgr_func cz_hwmgr_funcs = {
-+	.backend_init = cz_hwmgr_backend_init,
-+	.backend_fini = cz_hwmgr_backend_fini,
-+	.asic_setup = NULL,
-+	.force_dpm_level = cz_dpm_force_dpm_level,
-+	.get_power_state_size = cz_get_power_state_size,
-+	.patch_boot_state = cz_dpm_patch_boot_state,
-+	.get_pp_table_entry = cz_dpm_get_pp_table_entry,
-+	.get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
-+};
-+
-+int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr;
-+	int ret = 0;
-+
-+	cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
-+	if (cz_hwmgr == NULL)
-+		return -ENOMEM;
-+
-+	hwmgr->backend = cz_hwmgr;
-+	hwmgr->hwmgr_func = &cz_hwmgr_funcs;
-+	hwmgr->pptable_func = &pptable_funcs;
-+	return ret;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-new file mode 100644
-index 0000000..05849fd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-@@ -0,0 +1,309 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _CZ_HWMGR_H_
-+#define _CZ_HWMGR_H_
-+
-+#include "cgs_common.h"
-+
-+#define CZ_NUM_NBPSTATES               4
-+#define CZ_NUM_NBPMEMORYCLOCK          2
-+#define MAX_DISPLAY_CLOCK_LEVEL        8
-+#define CZ_AT_DFLT                     30
-+#define CZ_MAX_HARDWARE_POWERLEVELS    8
-+#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0   0x3FFFC102
-+
-+/* Carrizo device IDs */
-+#define DEVICE_ID_CZ_9870             0x9870
-+#define DEVICE_ID_CZ_9874             0x9874
-+#define DEVICE_ID_CZ_9875             0x9875
-+#define DEVICE_ID_CZ_9876             0x9876
-+#define DEVICE_ID_CZ_9877             0x9877
-+
-+#define PHMCZ_WRITE_SMC_REGISTER(device, reg, value)                            \
-+		cgs_write_ind_register(device, CGS_IND_REG__SMC, ix##reg, value)
-+
-+struct cz_dpm_entry {
-+	uint32_t soft_min_clk;
-+	uint32_t hard_min_clk;
-+	uint32_t soft_max_clk;
-+	uint32_t hard_max_clk;
-+};
-+
-+struct cz_sys_info {
-+	uint32_t bootup_uma_clock;
-+	uint32_t bootup_engine_clock;
-+	uint32_t dentist_vco_freq;
-+	uint32_t nb_dpm_enable;
-+	uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK];
-+	uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
-+	uint16_t nbp_voltage_index[CZ_NUM_NBPSTATES];
-+	uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
-+	uint16_t bootup_nb_voltage_index;
-+	uint8_t htc_tmp_lmt;
-+	uint8_t htc_hyst_lmt;
-+	uint32_t system_config;
-+	uint32_t uma_channel_number;
-+};
-+
-+#define MAX_DISPLAYPHY_IDS			0x8
-+#define DISPLAYPHY_LANEMASK			0xF
-+#define UNKNOWN_TRANSMITTER_PHY_ID		(-1)
-+
-+#define DISPLAYPHY_PHYID_SHIFT			24
-+#define DISPLAYPHY_LANESELECT_SHIFT		16
-+
-+#define DISPLAYPHY_RX_SELECT			0x1
-+#define DISPLAYPHY_TX_SELECT			0x2
-+#define DISPLAYPHY_CORE_SELECT			0x4
-+
-+#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
-+		(((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \
-+		((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \
-+		((rx) ? DISPLAYPHY_RX_SELECT : 0) | \
-+		((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
-+		((core) ? DISPLAYPHY_CORE_SELECT : 0))
-+
-+struct cz_display_phy_info_entry {
-+	uint8_t phy_present;
-+	uint8_t active_lane_mapping;
-+	uint8_t display_config_type;
-+	uint8_t active_number_of_lanes;
-+};
-+
-+#define CZ_MAX_DISPLAYPHY_IDS			10
-+
-+struct cz_display_phy_info {
-+	bool display_phy_access_initialized;
-+	struct cz_display_phy_info_entry entries[CZ_MAX_DISPLAYPHY_IDS];
-+};
-+
-+struct cz_power_level {
-+	uint32_t engineClock;
-+	uint8_t vddcIndex;
-+	uint8_t dsDividerIndex;
-+	uint8_t ssDividerIndex;
-+	uint8_t allowGnbSlow;
-+	uint8_t forceNBPstate;
-+	uint8_t display_wm;
-+	uint8_t vce_wm;
-+	uint8_t numSIMDToPowerDown;
-+	uint8_t hysteresis_up;
-+	uint8_t rsv[3];
-+};
-+
-+struct cz_uvd_clocks {
-+	uint32_t vclk;
-+	uint32_t dclk;
-+	uint32_t vclk_low_divider;
-+	uint32_t vclk_high_divider;
-+	uint32_t dclk_low_divider;
-+	uint32_t dclk_high_divider;
-+};
-+
-+enum cz_pstate_previous_action {
-+	DO_NOTHING = 1,
-+	FORCE_HIGH,
-+	CANCEL_FORCE_HIGH
-+};
-+
-+struct pp_disable_nb_ps_flags {
-+	union {
-+		struct {
-+			uint32_t entry : 1;
-+			uint32_t display : 1;
-+			uint32_t driver: 1;
-+			uint32_t vce : 1;
-+			uint32_t uvd : 1;
-+			uint32_t acp : 1;
-+			uint32_t reserved: 26;
-+		} bits;
-+		uint32_t u32All;
-+	};
-+};
-+
-+struct cz_power_state {
-+	unsigned int magic;
-+	uint32_t level;
-+	struct cz_uvd_clocks uvd_clocks;
-+	uint32_t evclk;
-+	uint32_t ecclk;
-+	uint32_t samclk;
-+	uint32_t acpclk;
-+	bool need_dfs_bypass;
-+	uint32_t nbps_flags;
-+	uint32_t bapm_flags;
-+	uint8_t dpm_0_pg_nb_ps_low;
-+	uint8_t dpm_0_pg_nb_ps_high;
-+	uint8_t dpm_x_nb_ps_low;
-+	uint8_t dpm_x_nb_ps_high;
-+	enum cz_pstate_previous_action action;
-+	struct cz_power_level levels[CZ_MAX_HARDWARE_POWERLEVELS];
-+	struct pp_disable_nb_ps_flags disable_nb_ps_flag;
-+};
-+
-+#define DPMFlags_SCLK_Enabled			0x00000001
-+#define DPMFlags_UVD_Enabled			0x00000002
-+#define DPMFlags_VCE_Enabled			0x00000004
-+#define DPMFlags_ACP_Enabled			0x00000008
-+#define DPMFlags_ForceHighestValid		0x40000000
-+#define DPMFlags_Debug				0x80000000
-+
-+#define SMU_EnabledFeatureScoreboard_AcpDpmOn   0x00000001 /* bit 0 */
-+#define SMU_EnabledFeatureScoreboard_SclkDpmOn    0x00200000
-+#define SMU_EnabledFeatureScoreboard_UvdDpmOn   0x00800000 /* bit 23 */
-+#define SMU_EnabledFeatureScoreboard_VceDpmOn   0x01000000 /* bit 24 */
-+
-+struct cz_hwmgr {
-+	uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
-+	uint32_t dpm_interval;
-+
-+	uint32_t voltage_drop_threshold;
-+
-+	uint32_t voting_rights_clients;
-+
-+	uint32_t disable_driver_thermal_policy;
-+
-+	uint32_t static_screen_threshold;
-+
-+	uint32_t gfx_power_gating_threshold;
-+
-+	uint32_t activity_hysteresis;
-+	uint32_t bootup_sclk_divider;
-+	uint32_t gfx_ramp_step;
-+	uint32_t gfx_ramp_delay; /* in micro-seconds */
-+
-+	uint32_t thermal_auto_throttling_treshold;
-+
-+	struct cz_sys_info sys_info;
-+
-+	struct cz_power_level boot_power_level;
-+	uint32_t mgcg_cgtt_local0;
-+	uint32_t mgcg_cgtt_local1;
-+
-+	uint32_t tdr_clock; /* in 10khz unit */
-+
-+	uint32_t ddi_power_gating_disabled;
-+	uint32_t disable_gfx_power_gating_in_uvd;
-+	uint32_t disable_nb_ps3_in_battery;
-+
-+	uint32_t lock_nb_ps_in_uvd_play_back;
-+
-+	struct cz_display_phy_info display_phy_info;
-+	uint32_t vce_slow_sclk_threshold; /* default 200mhz */
-+	uint32_t dce_slow_sclk_threshold; /* default 300mhz */
-+	uint32_t min_sclk_did;  /* minimum sclk divider */
-+
-+	bool disp_clk_bypass;
-+	bool disp_clk_bypass_pending;
-+	uint32_t bapm_enabled;
-+	uint32_t clock_slow_down_freq;
-+	uint32_t skip_clock_slow_down;
-+	uint32_t enable_nb_ps_policy;
-+	uint32_t voltage_drop_in_dce_power_gating;
-+	uint32_t uvd_dpm_interval;
-+	uint32_t override_dynamic_mgpg;
-+	uint32_t lclk_deep_enabled;
-+
-+	uint32_t uvd_performance;
-+
-+	bool video_start;
-+	bool battery_state;
-+	uint32_t lowest_valid;
-+	uint32_t highest_valid;
-+	uint32_t high_voltage_threshold;
-+	uint32_t is_nb_dpm_enabled;
-+	uint32_t is_nb_dpm_enabled_by_driver;
-+	uint32_t is_voltage_island_enabled;
-+
-+	bool pgacpinit;
-+
-+	uint8_t disp_config;
-+
-+	/* PowerTune */
-+	uint32_t power_containment_features;
-+	bool cac_enabled;
-+	bool disable_uvd_power_tune_feature;
-+	bool enable_ba_pm_feature;
-+	bool enable_tdc_limit_feature;
-+
-+	uint32_t sram_end;
-+	uint32_t dpm_table_start;
-+	uint32_t soft_regs_start;
-+
-+	uint8_t uvd_level_count;
-+	uint8_t vce_level_count;
-+
-+	uint8_t acp_level_count;
-+	uint8_t samu_level_count;
-+	uint32_t fps_high_threshold;
-+	uint32_t fps_low_threshold;
-+
-+	uint32_t dpm_flags;
-+	struct cz_dpm_entry sclk_dpm;
-+	struct cz_dpm_entry uvd_dpm;
-+	struct cz_dpm_entry vce_dpm;
-+	struct cz_dpm_entry acp_dpm;
-+
-+	uint8_t uvd_boot_level;
-+	uint8_t vce_boot_level;
-+	uint8_t acp_boot_level;
-+	uint8_t samu_boot_level;
-+	uint8_t uvd_interval;
-+	uint8_t vce_interval;
-+	uint8_t acp_interval;
-+	uint8_t samu_interval;
-+
-+	uint8_t graphics_interval;
-+	uint8_t graphics_therm_throttle_enable;
-+	uint8_t graphics_voltage_change_enable;
-+
-+	uint8_t graphics_clk_slow_enable;
-+	uint8_t graphics_clk_slow_divider;
-+
-+	uint32_t display_cac;
-+	uint32_t low_sclk_interrupt_threshold;
-+
-+	uint32_t dram_log_addr_h;
-+	uint32_t dram_log_addr_l;
-+	uint32_t dram_log_phy_addr_h;
-+	uint32_t dram_log_phy_addr_l;
-+	uint32_t dram_log_buff_size;
-+
-+	bool uvd_power_gated;
-+	bool vce_power_gated;
-+	bool samu_power_gated;
-+	bool acp_power_gated;
-+	bool acp_power_up_no_dsp;
-+	uint32_t active_process_mask;
-+
-+	uint32_t max_sclk_level;
-+	uint32_t num_of_clk_entries;
-+	struct cz_power_state *cz_ps;
-+};
-+
-+struct pp_hwmgr;
-+
-+int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
-+
-+#endif /* _CZ_HWMGR_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index f6b1153..e26df90 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -27,8 +27,7 @@
- #include "cgs_common.h"
- #include "power_state.h"
- #include "hwmgr.h"
--
--
-+#include "cz_hwmgr.h"
- 
- int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -51,6 +50,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 	hwmgr->power_source = PP_PowerSource_AC;
- 
- 	switch (hwmgr->chip_family) {
-+	case AMD_FAMILY_CZ:
-+		cz_hwmgr_init(hwmgr);
-+		break;
- 	default:
- 		return -EINVAL;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0047-drm-amd-powerplay-add-CG-and-PG-support-for-carrizo.patch b/common/recipes-kernel/linux/files/0047-drm-amd-powerplay-add-CG-and-PG-support-for-carrizo.patch
deleted file mode 100644
index bac07469..00000000
--- a/common/recipes-kernel/linux/files/0047-drm-amd-powerplay-add-CG-and-PG-support-for-carrizo.patch
+++ /dev/null
@@ -1,1366 +0,0 @@
-From 728e3862515c8d99fecf457ca874e04b1892df75 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Sep 2015 15:14:38 +0800
-Subject: [PATCH 0047/1110] drm/amd/powerplay: add CG and PG support for
- carrizo
-
-This adds clock and powergating support for CZ.
-
-v2: squash in fixes
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   3 +-
- .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c  | 252 ++++++++++
- .../drm/amd/powerplay/hwmgr/cz_clockpowergating.h  |  37 ++
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 521 ++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h     |  12 +-
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  89 +++-
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |  10 +
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    |  53 ++-
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  46 +-
- drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h  |  47 ++
- 10 files changed, 1058 insertions(+), 12 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index 22d383e..46cc494 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -3,7 +3,8 @@
- # It provides the hardware management services for the driver.
- 
- HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
--	       hardwaremanager.o pp_acpi.o cz_hwmgr.o
-+	       hardwaremanager.o pp_acpi.o cz_hwmgr.o \
-+               cz_clockpowergating.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-new file mode 100644
-index 0000000..ad77008
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-@@ -0,0 +1,252 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "hwmgr.h"
-+#include "cz_clockpowergating.h"
-+#include "cz_ppsmc.h"
-+
-+/* PhyID -> Status Mapping in DDI_PHY_GEN_STATUS
-+    0    GFX0L (3:0),                  (27:24),
-+    1    GFX0H (7:4),                  (31:28),
-+    2    GFX1L (3:0),                  (19:16),
-+    3    GFX1H (7:4),                  (23:20),
-+    4    DDIL   (3:0),                   (11: 8),
-+    5    DDIH  (7:4),                   (15:12),
-+    6    DDI2L (3:0),                   ( 3: 0),
-+    7    DDI2H (7:4),                   ( 7: 4),
-+*/
-+#define DDI_PHY_GEN_STATUS_VAL(phyID)   (1 << ((3 - ((phyID & 0x07)/2))*8 + (phyID & 0x01)*4))
-+#define IS_PHY_ID_USED_BY_PLL(PhyID)    (((0xF3 & (1 << PhyID)) & 0xFF) ? true : false)
-+
-+
-+int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating)
-+{
-+	int ret = 0;
-+
-+	switch (block) {
-+	case PHM_AsicBlock_UVD_MVC:
-+	case PHM_AsicBlock_UVD:
-+	case PHM_AsicBlock_UVD_HD:
-+	case PHM_AsicBlock_UVD_SD:
-+		if (gating == PHM_ClockGateSetting_StaticOff)
-+			ret = cz_dpm_powerdown_uvd(hwmgr);
-+		else
-+			ret = cz_dpm_powerup_uvd(hwmgr);
-+		break;
-+	case PHM_AsicBlock_GFX:
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+
-+bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block)
-+{
-+	return true;
-+}
-+
-+
-+int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return 0;
-+}
-+
-+int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
-+{
-+	return 0;
-+}
-+
-+static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
-+{
-+	return 0;
-+}
-+
-+int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	uint32_t dpm_features = 0;
-+
-+	if (enable &&
-+		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				  PHM_PlatformCaps_UVDDPM)) {
-+		cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
-+		dpm_features |= UVD_DPM_MASK;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			    PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
-+	} else {
-+		dpm_features |= UVD_DPM_MASK;
-+		cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			   PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
-+	}
-+	return 0;
-+}
-+
-+int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	uint32_t dpm_features = 0;
-+
-+	if (enable && phm_cap_enabled(
-+				hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_VCEDPM)) {
-+		cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
-+		dpm_features |= VCE_DPM_MASK;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			    PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
-+	} else {
-+		dpm_features |= VCE_DPM_MASK;
-+		cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			   PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (cz_hwmgr->uvd_power_gated == bgate)
-+		return 0;
-+
-+	cz_hwmgr->uvd_power_gated = bgate;
-+
-+	if (bgate) {
-+		cgs_set_clockgating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_CG_STATE_UNGATE);
-+		cgs_set_powergating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_PG_STATE_GATE);
-+		cz_dpm_update_uvd_dpm(hwmgr, true);
-+		cz_dpm_powerdown_uvd(hwmgr);
-+	} else {
-+		cz_dpm_powerup_uvd(hwmgr);
-+		cgs_set_clockgating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_PG_STATE_GATE);
-+		cgs_set_powergating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_CG_STATE_UNGATE);
-+		cz_dpm_update_uvd_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_VCEPowerGating)) {
-+		if (cz_hwmgr->vce_power_gated != bgate) {
-+			if (bgate) {
-+				cgs_set_clockgating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_CG_STATE_UNGATE);
-+				cgs_set_powergating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_PG_STATE_GATE);
-+				cz_enable_disable_vce_dpm(hwmgr, false);
-+			/* TODO: to figure out why vce can't be poweroff*/
-+				cz_hwmgr->vce_power_gated = true;
-+			} else {
-+				cz_dpm_powerup_vce(hwmgr);
-+				cz_hwmgr->vce_power_gated = false;
-+				cgs_set_clockgating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_PG_STATE_GATE);
-+				cgs_set_powergating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_CG_STATE_UNGATE);
-+				cz_dpm_update_vce_dpm(hwmgr);
-+				cz_enable_disable_vce_dpm(hwmgr, true);
-+				return 0;
-+			}
-+		}
-+	} else {
-+		cz_dpm_update_vce_dpm(hwmgr);
-+		cz_enable_disable_vce_dpm(hwmgr, true);
-+		return 0;
-+	}
-+
-+	if (!cz_hwmgr->vce_power_gated)
-+		cz_dpm_update_vce_dpm(hwmgr);
-+
-+	return 0;
-+}
-+
-+
-+static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
-+	/*we don't need an exit table here, because there is only D3 cold on Kv*/
-+	{ phm_cf_want_uvd_power_gating, cz_tf_uvd_power_gating_initialize },
-+	{ phm_cf_want_vce_power_gating, cz_tf_vce_power_gating_initialize },
-+	/* to do { NULL, cz_tf_xdma_power_gating_enable }, */
-+	{ NULL, NULL }
-+};
-+
-+struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	cz_enable_clock_power_gatings_list
-+};
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-new file mode 100644
-index 0000000..bbbc057
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _CZ_CLOCK_POWER_GATING_H_
-+#define _CZ_CLOCK_POWER_GATING_H_
-+
-+#include "cz_hwmgr.h"
-+#include "pp_asicblocks.h"
-+
-+extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
-+extern struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
-+extern struct phm_master_table_header cz_phm_disable_clock_power_gatings_master;
-+extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
-+extern int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
-+#endif /* _CZ_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 0c49505..e187b3f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -28,12 +28,23 @@
- #include "processpptables.h"
- #include "cgs_common.h"
- #include "smu/smu_8_0_d.h"
-+#include "smu8_fusion.h"
-+#include "smu/smu_8_0_sh_mask.h"
- #include "smumgr.h"
- #include "hwmgr.h"
- #include "hardwaremanager.h"
- #include "cz_ppsmc.h"
- #include "cz_hwmgr.h"
- #include "power_state.h"
-+#include "cz_clockpowergating.h"
-+
-+
-+#define ixSMUSVI_NB_CURRENTVID 0xD8230044
-+#define CURRENT_NB_VID_MASK 0xff000000
-+#define CURRENT_NB_VID__SHIFT 24
-+#define ixSMUSVI_GFX_CURRENTVID  0xD8230048
-+#define CURRENT_GFX_VID_MASK 0xff000000
-+#define CURRENT_GFX_VID__SHIFT 24
- 
- static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
- 
-@@ -45,6 +56,46 @@ static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_
- 	return (struct cz_power_state *)hw_ps;
- }
- 
-+static const struct cz_power_state *cast_const_PhwCzPowerState(
-+				const struct pp_hw_power_state *hw_ps)
-+{
-+	if (PhwCz_Magic != hw_ps->magic)
-+		return NULL;
-+
-+	return (struct cz_power_state *)hw_ps;
-+}
-+
-+uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
-+					uint32_t clock, uint32_t msg)
-+{
-+	int i = 0;
-+	struct phm_vce_clock_voltage_dependency_table *ptable =
-+		hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+
-+	switch (msg) {
-+	case PPSMC_MSG_SetEclkSoftMin:
-+	case PPSMC_MSG_SetEclkHardMin:
-+		for (i = 0; i < (int)ptable->count; i++) {
-+			if (clock <= ptable->entries[i].ecclk)
-+				break;
-+		}
-+		break;
-+
-+	case PPSMC_MSG_SetEclkSoftMax:
-+	case PPSMC_MSG_SetEclkHardMax:
-+		for (i = ptable->count - 1; i >= 0; i--) {
-+			if (clock >= ptable->entries[i].ecclk)
-+				break;
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return i;
-+}
-+
- static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
- 				uint32_t clock, uint32_t msg)
- {
-@@ -75,6 +126,37 @@ static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
- 	return i;
- }
- 
-+static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
-+					uint32_t clock, uint32_t msg)
-+{
-+	int i = 0;
-+	struct phm_uvd_clock_voltage_dependency_table *ptable =
-+		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+
-+	switch (msg) {
-+	case PPSMC_MSG_SetUvdSoftMin:
-+	case PPSMC_MSG_SetUvdHardMin:
-+		for (i = 0; i < (int)ptable->count; i++) {
-+			if (clock <= ptable->entries[i].vclk)
-+				break;
-+		}
-+		break;
-+
-+	case PPSMC_MSG_SetUvdSoftMax:
-+	case PPSMC_MSG_SetUvdHardMax:
-+		for (i = ptable->count - 1; i >= 0; i--) {
-+			if (clock >= ptable->entries[i].vclk)
-+				break;
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return i;
-+}
-+
- static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-@@ -504,6 +586,175 @@ static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
- 
- 	return 0;
- }
-+static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_clock_voltage_dependency_table *table =
-+					hwmgr->dyn_state.vddc_dependency_on_sclk;
-+
-+	unsigned long clock = 0;
-+	unsigned long level;
-+	unsigned long stable_pstate_sclk;
-+	struct PP_Clocks clocks;
-+	unsigned long percentage;
-+
-+	cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
-+	level = cz_get_max_sclk_level(hwmgr) - 1;
-+
-+	if (level < table->count)
-+		cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
-+	else
-+		cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
-+
-+	/*PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks);*/
-+	clock = clocks.engineClock;
-+
-+	if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
-+		cz_hwmgr->sclk_dpm.hard_min_clk = clock;
-+
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SetSclkHardMin,
-+						 cz_get_sclk_level(hwmgr,
-+					cz_hwmgr->sclk_dpm.hard_min_clk,
-+					     PPSMC_MSG_SetSclkHardMin));
-+	}
-+
-+	clock = cz_hwmgr->sclk_dpm.soft_min_clk;
-+
-+	/* update minimum clocks for Stable P-State feature */
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				     PHM_PlatformCaps_StablePState)) {
-+		percentage = 75;
-+		/*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
-+		stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
-+					percentage) / 100;
-+
-+		if (clock < stable_pstate_sclk)
-+			clock = stable_pstate_sclk;
-+	} else {
-+		if (clock < hwmgr->gfx_arbiter.sclk)
-+			clock = hwmgr->gfx_arbiter.sclk;
-+	}
-+
-+	if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
-+		cz_hwmgr->sclk_dpm.soft_min_clk = clock;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SetSclkSoftMin,
-+						cz_get_sclk_level(hwmgr,
-+					cz_hwmgr->sclk_dpm.soft_min_clk,
-+					     PPSMC_MSG_SetSclkSoftMin));
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_StablePState) &&
-+			 cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
-+		cz_hwmgr->sclk_dpm.soft_max_clk = clock;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SetSclkSoftMax,
-+						cz_get_sclk_level(hwmgr,
-+					cz_hwmgr->sclk_dpm.soft_max_clk,
-+					PPSMC_MSG_SetSclkSoftMax));
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_SclkDeepSleep)) {
-+		/* TO DO get from dal PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					  PPSMC_MSG_SetMinDeepSleepSclk,
-+						CZ_MIN_DEEP_SLEEP_SCLK);
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	struct cz_hwmgr *cz_hwmgr =
-+				  (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SetWatermarkFrequency,
-+				      cz_hwmgr->sclk_dpm.soft_max_clk);
-+
-+	return 0;
-+}
-+
-+static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	return 0;
-+}
-+
-+static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	int ret = 0;
-+	struct cz_hwmgr *cz_hwmgr =
-+				  (struct cz_hwmgr *)(hwmgr->backend);
-+	unsigned long dpm_features = 0;
-+
-+	if (!cz_hwmgr->is_nb_dpm_enabled &&
-+		cz_hwmgr->is_nb_dpm_enabled_by_driver) {		/* also depend on dal NBPStateDisableRequired */
-+		dpm_features |= NB_DPM_MASK;
-+		ret = smum_send_msg_to_smc_with_parameter(
-+							     hwmgr->smumgr,
-+					 PPSMC_MSG_EnableAllSmuFeatures,
-+							     dpm_features);
-+		if (ret == 0)
-+			cz_hwmgr->is_nb_dpm_enabled = true;
-+	}
-+	return ret;
-+}
-+
-+static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+
-+	struct cz_hwmgr *cz_hwmgr =
-+				  (struct cz_hwmgr *)(hwmgr->backend);
-+	const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
-+	const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
-+
-+	if (cz_hwmgr->sys_info.nb_dpm_enable) {
-+		if (pnew_state->action == FORCE_HIGH)
-+			smum_send_msg_to_smc(hwmgr->smumgr,
-+				    PPSMC_MSG_DisableLowMemoryPstate);
-+		else
-+			smum_send_msg_to_smc(hwmgr->smumgr,
-+				     PPSMC_MSG_EnableLowMemoryPstate);
-+	}
-+	return 0;
-+}
-+
-+static struct phm_master_table_item cz_set_power_state_list[] = {
-+	{NULL, cz_tf_update_sclk_limit},
-+	{NULL, cz_tf_set_deep_sleep_sclk_threshold},
-+	{NULL, cz_tf_set_watermark_threshold},
-+	{NULL, cz_tf_set_enabled_levels},
-+	{NULL, cz_tf_enable_nb_dpm},
-+	{NULL, cz_tf_update_low_mem_pstate},
-+	{NULL, NULL}
-+};
-+
-+static struct phm_master_table_header cz_set_power_state_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	cz_set_power_state_list
-+};
- 
- static struct phm_master_table_item cz_setup_asic_list[] = {
- 	{NULL, cz_tf_reset_active_process_mask},
-@@ -649,6 +900,56 @@ static struct phm_master_table_header cz_enable_dpm_master = {
- 	cz_enable_dpm_list
- };
- 
-+static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				struct pp_power_state  *prequest_ps,
-+			const struct pp_power_state *pcurrent_ps)
-+{
-+	struct cz_power_state *cz_ps =
-+				cast_PhwCzPowerState(&prequest_ps->hardware);
-+
-+	const struct cz_power_state *cz_current_ps =
-+				cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
-+
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct PP_Clocks clocks;
-+	bool force_high;
-+	unsigned long  num_of_active_displays = 4;
-+
-+	cz_ps->evclk = hwmgr->vce_arbiter.evclk;
-+	cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
-+
-+	cz_ps->need_dfs_bypass = true;
-+
-+	cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
-+				hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
-+
-+	cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
-+
-+	/* to do PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
-+	/* PECI_GetNumberOfActiveDisplays(pHwMgr->pPECI, &numOfActiveDisplays); */
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
-+		clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
-+	else
-+		clocks.memoryClock = 0;
-+
-+	if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
-+		clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-+
-+	force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
-+			|| (num_of_active_displays >= 3);
-+
-+	cz_ps->action = cz_current_ps->action;
-+
-+	if ((force_high == false) && (cz_ps->action == FORCE_HIGH))
-+		cz_ps->action = CANCEL_FORCE_HIGH;
-+	else if ((force_high == true) && (cz_ps->action != FORCE_HIGH))
-+		cz_ps->action = FORCE_HIGH;
-+	else
-+		cz_ps->action = DO_NOTHING;
-+
-+	return 0;
-+}
-+
- static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
-@@ -676,10 +977,28 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
- 				&(hwmgr->disable_dynamic_state_management));
--
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
-+		return result;
-+	}
- 	result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
- 				&(hwmgr->enable_dynamic_state_management));
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
-+		return result;
-+	}
-+	result = phm_construct_table(hwmgr, &cz_set_power_state_master,
-+				&(hwmgr->set_power_state));
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
-+		return result;
-+	}
- 
-+	result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
-+		return result;
-+	}
- 	return result;
- }
- 
-@@ -793,6 +1112,138 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
- 	return ret;
- }
- 
-+int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					 PHM_PlatformCaps_UVDPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+						     PPSMC_MSG_UVDPowerOFF);
-+	return 0;
-+}
-+
-+int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					 PHM_PlatformCaps_UVDPowerGating)) {
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
-+			return smum_send_msg_to_smc_with_parameter(
-+								hwmgr->smumgr,
-+						   PPSMC_MSG_UVDPowerON, 1);
-+		} else {
-+			return smum_send_msg_to_smc_with_parameter(
-+								hwmgr->smumgr,
-+						   PPSMC_MSG_UVDPowerON, 0);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_uvd_clock_voltage_dependency_table *ptable =
-+		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+
-+	if (!bgate) {
-+		/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					 PHM_PlatformCaps_StablePState)) {
-+			cz_hwmgr->uvd_dpm.hard_min_clk =
-+				   ptable->entries[ptable->count - 1].vclk;
-+
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						     PPSMC_MSG_SetUvdHardMin,
-+						      cz_get_uvd_level(hwmgr,
-+					     cz_hwmgr->uvd_dpm.hard_min_clk,
-+						   PPSMC_MSG_SetUvdHardMin));
-+
-+			cz_enable_disable_uvd_dpm(hwmgr, true);
-+		} else
-+			cz_enable_disable_uvd_dpm(hwmgr, true);
-+	} else
-+		cz_enable_disable_uvd_dpm(hwmgr, false);
-+
-+	return 0;
-+}
-+
-+int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	struct phm_vce_clock_voltage_dependency_table *ptable =
-+		hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+
-+	/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					 PHM_PlatformCaps_StablePState)) {
-+		cz_hwmgr->vce_dpm.hard_min_clk =
-+				  ptable->entries[ptable->count - 1].ecclk;
-+
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SetEclkHardMin,
-+					cz_get_eclk_level(hwmgr,
-+					     cz_hwmgr->vce_dpm.hard_min_clk,
-+						PPSMC_MSG_SetEclkHardMin));
-+	} else {
-+		/*EPR# 419220 -HW limitation to to */
-+		cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					    PPSMC_MSG_SetEclkHardMin,
-+					    cz_get_eclk_level(hwmgr,
-+				     cz_hwmgr->vce_dpm.hard_min_clk,
-+					  PPSMC_MSG_SetEclkHardMin));
-+
-+	}
-+	return 0;
-+}
-+
-+int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					 PHM_PlatformCaps_VCEPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+						     PPSMC_MSG_VCEPowerOFF);
-+	return 0;
-+}
-+
-+int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					 PHM_PlatformCaps_VCEPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+						     PPSMC_MSG_VCEPowerON);
-+	return 0;
-+}
-+
-+static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	return cz_hwmgr->sys_info.bootup_uma_clock;
-+}
-+
-+static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct cz_power_state  *cz_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	cz_ps = cast_PhwCzPowerState(&ps->hardware);
-+
-+	if (low)
-+		return cz_ps->levels[0].engineClock;
-+	else
-+		return cz_ps->levels[cz_ps->level-1].engineClock;
-+}
-+
- static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
- 					struct pp_hw_power_state *hw_ps)
- {
-@@ -871,15 +1322,83 @@ int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
- 	return sizeof(struct cz_power_state);
- }
- 
-+static void
-+cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
-+{
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	struct phm_clock_voltage_dependency_table *table =
-+				hwmgr->dyn_state.vddc_dependency_on_sclk;
-+
-+	struct phm_vce_clock_voltage_dependency_table *vce_table =
-+		hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+
-+	struct phm_uvd_clock_voltage_dependency_table *uvd_table =
-+		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+
-+	uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
-+					TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
-+	uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
-+					TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
-+	uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
-+					TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
-+
-+	uint32_t sclk, vclk, dclk, ecclk, tmp;
-+	uint16_t vddnb, vddgfx;
-+
-+	if (sclk_index >= NUM_SCLK_LEVELS) {
-+		seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
-+	} else {
-+		sclk = table->entries[sclk_index].clk;
-+		seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
-+	}
-+
-+	tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
-+		CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
-+	vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
-+	tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
-+		CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
-+	vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
-+	seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
-+
-+	seq_printf(m, "\n uvd    %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
-+	if (!cz_hwmgr->uvd_power_gated) {
-+		if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
-+			seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
-+		} else {
-+			vclk = uvd_table->entries[uvd_index].vclk;
-+			dclk = uvd_table->entries[uvd_index].dclk;
-+			seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
-+		}
-+	}
-+
-+	seq_printf(m, "\n vce    %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
-+	if (!cz_hwmgr->vce_power_gated) {
-+		if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
-+			seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
-+		} else {
-+			ecclk = vce_table->entries[vce_index].ecclk;
-+			seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
-+		}
-+	}
-+}
-+
- static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.backend_init = cz_hwmgr_backend_init,
- 	.backend_fini = cz_hwmgr_backend_fini,
- 	.asic_setup = NULL,
-+	.apply_state_adjust_rules = cz_apply_state_adjust_rules,
- 	.force_dpm_level = cz_dpm_force_dpm_level,
- 	.get_power_state_size = cz_get_power_state_size,
-+	.powerdown_uvd = cz_dpm_powerdown_uvd,
-+	.powergate_uvd = cz_dpm_powergate_uvd,
-+	.powergate_vce = cz_dpm_powergate_vce,
-+	.get_mclk = cz_dpm_get_mclk,
-+	.get_sclk = cz_dpm_get_sclk,
- 	.patch_boot_state = cz_dpm_patch_boot_state,
- 	.get_pp_table_entry = cz_dpm_get_pp_table_entry,
- 	.get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
-+	.print_current_perforce_level = cz_print_current_perforce_level,
- };
- 
- int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-index 05849fd..70b0e51 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-@@ -32,6 +32,7 @@
- #define CZ_AT_DFLT                     30
- #define CZ_MAX_HARDWARE_POWERLEVELS    8
- #define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0   0x3FFFC102
-+#define CZ_MIN_DEEP_SLEEP_SCLK         800
- 
- /* Carrizo device IDs */
- #define DEVICE_ID_CZ_9870             0x9870
-@@ -198,6 +199,9 @@ struct cz_hwmgr {
- 	struct cz_sys_info sys_info;
- 
- 	struct cz_power_level boot_power_level;
-+	struct cz_power_state *cz_current_ps;
-+	struct cz_power_state *cz_requested_ps;
-+
- 	uint32_t mgcg_cgtt_local0;
- 	uint32_t mgcg_cgtt_local1;
- 
-@@ -299,11 +303,15 @@ struct cz_hwmgr {
- 
- 	uint32_t max_sclk_level;
- 	uint32_t num_of_clk_entries;
--	struct cz_power_state *cz_ps;
- };
- 
- struct pp_hwmgr;
- 
- int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
--
-+int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr);
-+int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr);
-+int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr);
-+int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr);
-+int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr);
- #endif /* _CZ_HWMGR_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 7317e43..aec9f6d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -23,6 +23,7 @@
- #include <linux/errno.h>
- #include "hwmgr.h"
- #include "hardwaremanager.h"
-+#include "power_state.h"
- #include "pp_acpi.h"
- #include "amd_acpi.h"
- 
-@@ -55,6 +56,17 @@ void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
- 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
- }
- 
-+bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
-+{
-+	return hwmgr->block_hw_access;
-+}
-+
-+int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
-+{
-+	hwmgr->block_hw_access = block;
-+	return 0;
-+}
-+
- int phm_setup_asic(struct pp_hwmgr *hwmgr)
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-@@ -62,13 +74,33 @@ int phm_setup_asic(struct pp_hwmgr *hwmgr)
- 		if (NULL != hwmgr->hwmgr_func->asic_setup)
- 			return hwmgr->hwmgr_func->asic_setup(hwmgr);
- 	} else {
--		return phm_dispatch_table (hwmgr, &(hwmgr->setup_asic),
-+		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
- 					  NULL, NULL);
- 	}
- 
- 	return 0;
- }
- 
-+int phm_set_power_state(struct pp_hwmgr *hwmgr,
-+		    const struct pp_hw_power_state *pcurrent_state,
-+		    const struct pp_hw_power_state *pnew_power_state)
-+{
-+	struct phm_set_power_state_input states;
-+
-+	states.pcurrent_state = pcurrent_state;
-+	states.pnew_state = pnew_power_state;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_TablelessHardwareInterface)) {
-+		if (NULL != hwmgr->hwmgr_func->power_state_set)
-+			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
-+	} else {
-+		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
-+	}
-+
-+	return 0;
-+}
-+
- int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-@@ -76,9 +108,62 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
- 		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
- 			return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
- 	} else {
--		return phm_dispatch_table (hwmgr,
-+		return phm_dispatch_table(hwmgr,
- 				&(hwmgr->enable_dynamic_state_management),
- 				NULL, NULL);
- 	}
- 	return 0;
- }
-+
-+int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
-+{
-+	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
-+		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-+
-+	return 0;
-+}
-+
-+int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				   struct pp_power_state *adjusted_ps,
-+			     const struct pp_power_state *current_ps)
-+{
-+	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
-+		return hwmgr->hwmgr_func->apply_state_adjust_rules(
-+									hwmgr,
-+								 adjusted_ps,
-+								 current_ps);
-+	return 0;
-+}
-+
-+int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
-+		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
-+	return 0;
-+}
-+
-+int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
-+{
-+	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
-+		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
-+	return 0;
-+}
-+
-+int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
-+{
-+	if (hwmgr->hwmgr_func->powergate_vce != NULL)
-+		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
-+	return 0;
-+}
-+
-+int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_TablelessHardwareInterface)) {
-+		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
-+			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
-+	} else {
-+		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
-+	}
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index e26df90..5d1ba90 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -201,3 +201,13 @@ void phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
- 	phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
- 				      value, mask);
- }
-+
-+bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
-+{
-+	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
-+}
-+
-+bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
-+{
-+	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 26e1256..a69b379 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -23,7 +23,12 @@
- #ifndef _HARDWARE_MANAGER_H_
- #define _HARDWARE_MANAGER_H_
- 
-+
-+
- struct pp_hwmgr;
-+struct pp_hw_power_state;
-+struct pp_power_state;
-+enum amd_dpm_forced_level;
- 
- /* Automatic Power State Throttling */
- enum PHM_AutoThrottleSource
-@@ -206,6 +211,24 @@ struct pp_hw_descriptor {
- 	uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
- };
- 
-+enum PHM_PerformanceLevelDesignation {
-+	PHM_PerformanceLevelDesignation_Activity,
-+	PHM_PerformanceLevelDesignation_PowerContainment
-+};
-+
-+typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
-+
-+struct PHM_PerformanceLevel {
-+	uint32_t    coreClock;
-+	uint32_t    memory_clock;
-+	uint32_t  vddc;
-+	uint32_t  vddci;
-+	uint32_t    nonLocalMemoryFreq;
-+	uint32_t nonLocalMemoryWidth;
-+};
-+
-+typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
-+
- /* Function for setting a platform cap */
- static inline void phm_cap_set(uint32_t *caps,
- 			enum phm_platform_caps c)
-@@ -226,6 +249,20 @@ static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps
- 		  (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
- }
- 
-+#define PP_PCIEGenInvalid  0xffff
-+enum PP_PCIEGen {
-+	PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
-+	PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
-+	PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
-+};
-+
-+typedef enum PP_PCIEGen PP_PCIEGen;
-+
-+#define PP_Min_PCIEGen     PP_PCIEGen1
-+#define PP_Max_PCIEGen     PP_PCIEGen3
-+#define PP_Min_PCIELane    1
-+#define PP_Max_PCIELane    32
-+
- enum phm_clock_Type {
- 	PHM_DispClock = 1,
- 	PHM_SClock,
-@@ -273,8 +310,22 @@ struct phm_clocks {
- 	uint32_t num_of_entries;
- 	uint32_t clock[MAX_NUM_CLOCKS];
- };
--
-+extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
-+extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
-+extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
-+extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
- extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
- extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
- extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
-+extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
-+extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
-+extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
-+		    const struct pp_hw_power_state *pcurrent_state,
-+		 const struct pp_hw_power_state *pnew_power_state);
-+
-+extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				   struct pp_power_state *adjusted_ps,
-+			     const struct pp_power_state *current_ps);
-+
-+extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
- #endif /* _HARDWARE_MANAGER_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 07fba41..18b5ab1 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -23,6 +23,7 @@
- #ifndef _HWMGR_H_
- #define _HWMGR_H_
- 
-+#include <linux/seq_file.h>
- #include "amd_powerplay.h"
- #include "pp_instance.h"
- #include "hardwaremanager.h"
-@@ -85,6 +86,11 @@ typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
- 
- typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
- 
-+struct phm_set_power_state_input {
-+	const struct pp_hw_power_state *pcurrent_state;
-+	const struct pp_hw_power_state *pnew_state;
-+};
-+
- struct phm_acp_arbiter {
- 	uint32_t acpclk;
- };
-@@ -252,11 +258,34 @@ struct pp_hwmgr_func {
- 	int (*backend_fini)(struct pp_hwmgr *hw_mgr);
- 	int (*asic_setup)(struct pp_hwmgr *hw_mgr);
- 	int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
--	int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, enum amd_dpm_forced_level level);
--	int (*dynamic_state_management_enable)(struct pp_hwmgr *hw_mgr);
--	int (*patch_boot_state)(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps);
--	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, unsigned long, struct pp_power_state *);
-+
-+	int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
-+				struct pp_power_state  *prequest_ps,
-+			const struct pp_power_state *pcurrent_ps);
-+
-+	int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
-+					enum amd_dpm_forced_level level);
-+
-+	int (*dynamic_state_management_enable)(
-+						struct pp_hwmgr *hw_mgr);
-+
-+	int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
-+				     struct pp_hw_power_state *hw_ps);
-+
-+	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
-+			    unsigned long, struct pp_power_state *);
-+
- 	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
-+	int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
-+	int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
-+	int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
-+	int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
-+	int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
-+	int (*power_state_set)(struct pp_hwmgr *hwmgr,
-+						const void *state);
-+	void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
-+							struct seq_file *m);
-+	int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
- };
- 
- struct pp_table_func {
-@@ -416,7 +445,7 @@ struct pp_hwmgr {
- 	struct pp_smumgr *smumgr;
- 	const void *soft_pp_table;
- 	enum amd_dpm_forced_level dpm_level;
--
-+	bool block_hw_access;
- 	struct phm_gfx_arbiter gfx_arbiter;
- 	struct phm_acp_arbiter acp_arbiter;
- 	struct phm_uvd_arbiter uvd_arbiter;
-@@ -430,6 +459,8 @@ struct pp_hwmgr {
- 	struct phm_runtime_table_header setup_asic;
- 	struct phm_runtime_table_header disable_dynamic_state_management;
- 	struct phm_runtime_table_header enable_dynamic_state_management;
-+	struct phm_runtime_table_header set_power_state;
-+	struct phm_runtime_table_header enable_clock_power_gatings;
- 	const struct pp_hwmgr_func *hwmgr_func;
- 	const struct pp_table_func *pptable_func;
- 	struct pp_power_state    *ps;
-@@ -471,6 +502,11 @@ extern void phm_wait_for_indirect_register_unequal(
- 				uint32_t value,
- 				uint32_t mask);
- 
-+bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
-+bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
-+
-+#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
-+
- #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
- #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h b/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h
-new file mode 100644
-index 0000000..0c1593e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_asicblocks.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef PP_ASICBLOCKS_H
-+#define PP_ASICBLOCKS_H
-+
-+
-+enum PHM_AsicBlock {
-+	PHM_AsicBlock_GFX,
-+	PHM_AsicBlock_UVD_MVC,
-+	PHM_AsicBlock_UVD,
-+	PHM_AsicBlock_UVD_HD,
-+	PHM_AsicBlock_UVD_SD,
-+	PHM_AsicBlock_Count
-+};
-+
-+enum PHM_ClockGateSetting {
-+	PHM_ClockGateSetting_StaticOn,
-+	PHM_ClockGateSetting_StaticOff,
-+	PHM_ClockGateSetting_Dynamic
-+};
-+
-+struct phm_asic_blocks {
-+	bool gfx : 1;
-+	bool uvd : 1;
-+};
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0048-drm-amd-powerplay-add-event-manager-sub-component.patch b/common/recipes-kernel/linux/files/0048-drm-amd-powerplay-add-event-manager-sub-component.patch
deleted file mode 100644
index 482edcb3..00000000
--- a/common/recipes-kernel/linux/files/0048-drm-amd-powerplay-add-event-manager-sub-component.patch
+++ /dev/null
@@ -1,2664 +0,0 @@
-From 38aada7e86d4605b3edc269dfaa48637a16426b0 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Sep 2015 15:14:54 +0800
-Subject: [PATCH 0048/1110] drm/amd/powerplay: add event manager sub-component
-
-The event manager handles power related driver events.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/Makefile             |   2 +-
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  23 ++
- drivers/gpu/drm/amd/powerplay/eventmgr/Makefile    |  11 +
- .../drm/amd/powerplay/eventmgr/eventactionchains.c | 287 +++++++++++++++
- .../drm/amd/powerplay/eventmgr/eventactionchains.h |  62 ++++
- drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c | 180 +++++++++
- drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h |  34 ++
- .../drm/amd/powerplay/eventmgr/eventmanagement.c   | 215 +++++++++++
- .../drm/amd/powerplay/eventmgr/eventmanagement.h   |  59 +++
- drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c  | 114 ++++++
- .../drm/amd/powerplay/eventmgr/eventsubchains.c    | 395 ++++++++++++++++++++
- .../drm/amd/powerplay/eventmgr/eventsubchains.h    |  98 +++++
- .../gpu/drm/amd/powerplay/eventmgr/eventtasks.c    | 408 +++++++++++++++++++++
- .../gpu/drm/amd/powerplay/eventmgr/eventtasks.h    |  85 +++++
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.c       | 111 ++++++
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.h       |  37 ++
- drivers/gpu/drm/amd/powerplay/inc/eventmanager.h   | 109 ++++++
- drivers/gpu/drm/amd/powerplay/inc/eventmgr.h       | 125 +++++++
- drivers/gpu/drm/amd/powerplay/inc/pp_feature.h     |  67 ++++
- drivers/gpu/drm/amd/powerplay/inc/pp_instance.h    |   2 +
- 20 files changed, 2423 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/Makefile
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/eventmanager.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_feature.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
-index 6359c67..0231021 100644
---- a/drivers/gpu/drm/amd/powerplay/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/Makefile
-@@ -6,7 +6,7 @@ subdir-ccflags-y += -Iinclude/drm  \
- 
- AMD_PP_PATH = ../powerplay
- 
--PP_LIBS = smumgr hwmgr
-+PP_LIBS = smumgr hwmgr eventmgr
- 
- AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix drivers/gpu/drm/amd/powerplay/,$(PP_LIBS)))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 88fdb04..1964a2a 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -52,6 +52,7 @@ static int pp_sw_init(void *handle)
- 		return -EINVAL;
- 
- 	ret = hwmgr->pptable_func->pptable_init(hwmgr);
-+
- 	if (ret == 0)
- 		ret = hwmgr->hwmgr_func->backend_init(hwmgr);
- 
-@@ -81,6 +82,7 @@ static int pp_hw_init(void *handle)
- {
- 	struct pp_instance *pp_handle;
- 	struct pp_smumgr *smumgr;
-+	struct pp_eventmgr *eventmgr;
- 	int ret = 0;
- 
- 	if (handle == NULL)
-@@ -106,8 +108,14 @@ static int pp_hw_init(void *handle)
- 		smumgr->smumgr_funcs->smu_fini(smumgr);
- 		return ret;
- 	}
-+
- 	hw_init_power_state_table(pp_handle->hwmgr);
-+	eventmgr = pp_handle->eventmgr;
- 
-+	if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
-+		return -EINVAL;
-+
-+	ret = eventmgr->pp_eventmgr_init(eventmgr);
- 	return 0;
- }
- 
-@@ -115,11 +123,17 @@ static int pp_hw_fini(void *handle)
- {
- 	struct pp_instance *pp_handle;
- 	struct pp_smumgr *smumgr;
-+	struct pp_eventmgr *eventmgr;
- 
- 	if (handle == NULL)
- 		return -EINVAL;
- 
- 	pp_handle = (struct pp_instance *)handle;
-+	eventmgr = pp_handle->eventmgr;
-+
-+	if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL)
-+		eventmgr->pp_eventmgr_fini(eventmgr);
-+
- 	smumgr = pp_handle->smu_mgr;
- 
- 	if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
-@@ -273,9 +287,15 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init,
- 	if (ret)
- 		goto fail_hwmgr;
- 
-+	ret = eventmgr_init(handle);
-+	if (ret)
-+		goto fail_eventmgr;
-+
- 	amd_pp->pp_handle = handle;
- 	return 0;
- 
-+fail_eventmgr:
-+	hwmgr_fini(handle->hwmgr);
- fail_hwmgr:
- 	smum_fini(handle->smu_mgr);
- fail_smum:
-@@ -286,9 +306,12 @@ fail_smum:
- static int amd_pp_instance_fini(void *handle)
- {
- 	struct pp_instance *instance = (struct pp_instance *)handle;
-+
- 	if (instance == NULL)
- 		return -EINVAL;
- 
-+	eventmgr_fini(instance->eventmgr);
-+
- 	hwmgr_fini(instance->hwmgr);
- 
- 	smum_fini(instance->smu_mgr);
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile b/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile
-new file mode 100644
-index 0000000..7509e38
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/Makefile
-@@ -0,0 +1,11 @@
-+#
-+# Makefile for the 'event manager' sub-component of powerplay.
-+# It provides the event management services for the driver.
-+
-+EVENT_MGR = eventmgr.o eventinit.o eventmanagement.o  \
-+		eventactionchains.o eventsubchains.o eventtasks.o psm.o
-+
-+AMD_PP_EVENT = $(addprefix $(AMD_PP_PATH)/eventmgr/,$(EVENT_MGR))
-+
-+AMD_POWERPLAY_FILES += $(AMD_PP_EVENT)
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-new file mode 100644
-index 0000000..e9fe85f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -0,0 +1,287 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include "eventmgr.h"
-+#include "eventactionchains.h"
-+#include "eventsubchains.h"
-+
-+static const pem_event_action *initialize_event[] = {
-+	block_adjust_power_state_tasks,
-+	power_budget_tasks,
-+	system_config_tasks,
-+	setup_asic_tasks,
-+	enable_dynamic_state_management_tasks,
-+	enable_clock_power_gatings_tasks,
-+	get_2d_performance_state_tasks,
-+	set_performance_state_tasks,
-+	conditionally_force_3d_performance_state_tasks,
-+	process_vbios_eventinfo_tasks,
-+	broadcast_power_policy_tasks,
-+	NULL
-+};
-+
-+const struct action_chain initialize_action_chain = {
-+	"Initialize",
-+	initialize_event
-+};
-+
-+static const pem_event_action *uninitialize_event[] = {
-+	ungate_all_display_phys_tasks,
-+	uninitialize_display_phy_access_tasks,
-+	disable_gfx_voltage_island_power_gating_tasks,
-+	disable_gfx_clock_gating_tasks,
-+	set_boot_state_tasks,
-+	adjust_power_state_tasks,
-+	disable_dynamic_state_management_tasks,
-+	disable_clock_power_gatings_tasks,
-+	cleanup_asic_tasks,
-+	prepare_for_pnp_stop_tasks,
-+	NULL
-+};
-+
-+const struct action_chain uninitialize_action_chain = {
-+	"Uninitialize",
-+	uninitialize_event
-+};
-+
-+static const pem_event_action *power_source_change_event_pp_enabled[] = {
-+	set_power_source_tasks,
-+	set_power_saving_state_tasks,
-+	adjust_power_state_tasks,
-+	enable_disable_fps_tasks,
-+	set_nbmcu_state_tasks,
-+	broadcast_power_policy_tasks,
-+	NULL
-+};
-+
-+const struct action_chain power_source_change_action_chain_pp_enabled = {
-+	"Power source change - PowerPlay enabled",
-+	power_source_change_event_pp_enabled
-+};
-+
-+static const pem_event_action *power_source_change_event_pp_disabled[] = {
-+	set_power_source_tasks,
-+	set_nbmcu_state_tasks,
-+	NULL
-+};
-+
-+const struct action_chain power_source_changes_action_chain_pp_disabled = {
-+	"Power source change - PowerPlay disabled",
-+	power_source_change_event_pp_disabled
-+};
-+
-+static const pem_event_action *power_source_change_event_hardware_dc[] = {
-+	set_power_source_tasks,
-+	set_power_saving_state_tasks,
-+	adjust_power_state_tasks,
-+	enable_disable_fps_tasks,
-+	reset_hardware_dc_notification_tasks,
-+	set_nbmcu_state_tasks,
-+	broadcast_power_policy_tasks,
-+	NULL
-+};
-+
-+const struct action_chain power_source_change_action_chain_hardware_dc = {
-+	"Power source change - with Hardware DC switching",
-+	power_source_change_event_hardware_dc
-+};
-+
-+static const pem_event_action *suspend_event[] = {
-+	reset_display_phy_access_tasks,
-+	unregister_interrupt_tasks,
-+	disable_gfx_voltage_island_power_gating_tasks,
-+	disable_gfx_clock_gating_tasks,
-+	notify_smu_suspend_tasks,
-+	disable_smc_firmware_ctf_tasks,
-+	set_boot_state_tasks,
-+	adjust_power_state_tasks,
-+	disable_fps_tasks,
-+	vari_bright_suspend_tasks,
-+	reset_fan_speed_to_default_tasks,
-+	power_down_asic_tasks,
-+	disable_stutter_mode_tasks,
-+	set_connected_standby_tasks,
-+	block_hw_access_tasks,
-+	NULL
-+};
-+
-+const struct action_chain suspend_action_chain = {
-+	"Suspend",
-+	suspend_event
-+};
-+
-+static const pem_event_action *resume_event[] = {
-+	unblock_hw_access_tasks,
-+	resume_connected_standby_tasks,
-+	notify_smu_resume_tasks,
-+	reset_display_configCounter_tasks,
-+	update_dal_configuration_tasks,
-+	vari_bright_resume_tasks,
-+	block_adjust_power_state_tasks,
-+	setup_asic_tasks,
-+	enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
-+	enable_dynamic_state_management_tasks,
-+	enable_clock_power_gatings_tasks,
-+	enable_disable_bapm_tasks,
-+	reset_boot_state_tasks,
-+	adjust_power_state_tasks,
-+	enable_disable_fps_tasks,
-+	notify_hw_power_source_tasks,
-+	process_vbios_event_info_tasks,
-+	enable_gfx_clock_gating_tasks,
-+	enable_gfx_voltage_island_power_gating_tasks,
-+	reset_clock_gating_tasks,
-+	notify_smu_vpu_recovery_end_tasks,
-+	disable_vpu_cap_tasks,
-+	execute_escape_sequence_tasks,
-+	NULL
-+};
-+
-+
-+const struct action_chain resume_action_chain = {
-+	"resume",
-+	resume_event
-+};
-+
-+static const pem_event_action *complete_init_event[] = {
-+	adjust_power_state_tasks,
-+	enable_gfx_clock_gating_tasks,
-+	enable_gfx_voltage_island_power_gating_tasks,
-+	notify_power_state_change_tasks,
-+	NULL
-+};
-+
-+const struct action_chain complete_init_action_chain = {
-+	"complete init",
-+	complete_init_event
-+};
-+
-+static const pem_event_action *enable_gfx_clock_gating_event[] = {
-+	enable_gfx_clock_gating_tasks,
-+	NULL
-+};
-+
-+const struct action_chain enable_gfx_clock_gating_action_chain = {
-+	"enable gfx clock gate",
-+	enable_gfx_clock_gating_event
-+};
-+
-+static const pem_event_action *disable_gfx_clock_gating_event[] = {
-+	disable_gfx_clock_gating_tasks,
-+	NULL
-+};
-+
-+const struct action_chain disable_gfx_clock_gating_action_chain = {
-+	"disable gfx clock gate",
-+	disable_gfx_clock_gating_event
-+};
-+
-+static const pem_event_action *enable_cgpg_event[] = {
-+	enable_cgpg_tasks,
-+	NULL
-+};
-+
-+const struct action_chain enable_cgpg_action_chain = {
-+	"eable cg pg",
-+	enable_cgpg_event
-+};
-+
-+static const pem_event_action *disable_cgpg_event[] = {
-+	disable_cgpg_tasks,
-+	NULL
-+};
-+
-+const struct action_chain disable_cgpg_action_chain = {
-+	"disable cg pg",
-+	disable_cgpg_event
-+};
-+
-+
-+/* Enable user _2d performance and activate */
-+
-+static const pem_event_action *enable_user_state_event[] = {
-+	create_new_user_performance_state_tasks,
-+	adjust_power_state_tasks,
-+	NULL
-+};
-+
-+const struct action_chain enable_user_state_action_chain = {
-+	"Enable user state",
-+	enable_user_state_event
-+};
-+
-+static const pem_event_action *enable_user_2d_performance_event[] = {
-+	enable_user_2d_performance_tasks,
-+	add_user_2d_performance_state_tasks,
-+	set_performance_state_tasks,
-+	adjust_power_state_tasks,
-+	delete_user_2d_performance_state_tasks,
-+	NULL
-+};
-+
-+const struct action_chain enable_user_2d_performance_action_chain = {
-+	"enable_user_2d_performance_event_activate",
-+	enable_user_2d_performance_event
-+};
-+
-+
-+static const pem_event_action *disable_user_2d_performance_event[] = {
-+	disable_user_2d_performance_tasks,
-+	delete_user_2d_performance_state_tasks,
-+	NULL
-+};
-+
-+const struct action_chain disable_user_2d_performance_action_chain = {
-+	"disable_user_2d_performance_event",
-+	disable_user_2d_performance_event
-+};
-+
-+
-+static const pem_event_action *display_config_change_event[] = {
-+	/* countDisplayConfigurationChangeEventTasks, */
-+	unblock_adjust_power_state_tasks,
-+	/* setCPUPowerState,*/
-+	notify_hw_power_source_tasks,
-+	/* updateDALConfigurationTasks,
-+	variBrightDisplayConfigurationChangeTasks, */
-+	adjust_power_state_tasks,
-+	/*enableDisableFPSTasks,
-+	setNBMCUStateTasks,
-+	notifyPCIEDeviceReadyTasks,*/
-+	NULL
-+};
-+
-+const struct action_chain display_config_change_action_chain = {
-+	"Display configuration change",
-+	display_config_change_event
-+};
-+
-+static const pem_event_action *readjust_power_state_event[] = {
-+	adjust_power_state_tasks,
-+	NULL
-+};
-+
-+const struct action_chain readjust_power_state_action_chain = {
-+	"re-adjust power state",
-+	readjust_power_state_event
-+};
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h
-new file mode 100644
-index 0000000..f181e53
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _EVENT_ACTION_CHAINS_H_
-+#define _EVENT_ACTION_CHAINS_H_
-+#include "eventmgr.h"
-+
-+extern const struct action_chain initialize_action_chain;
-+
-+extern const struct action_chain uninitialize_action_chain;
-+
-+extern const struct action_chain power_source_change_action_chain_pp_enabled;
-+
-+extern const struct action_chain power_source_changes_action_chain_pp_disabled;
-+
-+extern const struct action_chain power_source_change_action_chain_hardware_dc;
-+
-+extern const struct action_chain suspend_action_chain;
-+
-+extern const struct action_chain resume_action_chain;
-+
-+extern const struct action_chain complete_init_action_chain;
-+
-+extern const struct action_chain enable_gfx_clock_gating_action_chain;
-+
-+extern const struct action_chain disable_gfx_clock_gating_action_chain;
-+
-+extern const struct action_chain enable_cgpg_action_chain;
-+
-+extern const struct action_chain disable_cgpg_action_chain;
-+
-+extern const struct action_chain enable_user_2d_performance_action_chain;
-+
-+extern const struct action_chain disable_user_2d_performance_action_chain;
-+
-+extern const struct action_chain enable_user_state_action_chain;
-+
-+extern const struct action_chain readjust_power_state_action_chain;
-+
-+extern const struct action_chain display_config_change_action_chain;
-+
-+#endif /*_EVENT_ACTION_CHAINS_H_*/
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
-new file mode 100644
-index 0000000..0438442
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
-@@ -0,0 +1,180 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include "eventmgr.h"
-+#include "eventinit.h"
-+
-+void pem_init_feature_info(struct pp_eventmgr *eventmgr)
-+{
-+
-+	/* PowerPlay info */
-+	eventmgr->ui_state_info[PP_PowerSource_AC].default_ui_lable =
-+					    PP_StateUILabel_Performance;
-+
-+	eventmgr->ui_state_info[PP_PowerSource_AC].current_ui_label =
-+					    PP_StateUILabel_Performance;
-+
-+	eventmgr->ui_state_info[PP_PowerSource_DC].default_ui_lable =
-+						  PP_StateUILabel_Battery;
-+
-+	eventmgr->ui_state_info[PP_PowerSource_DC].current_ui_label =
-+						  PP_StateUILabel_Battery;
-+
-+	if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_PowerPlaySupport)) {
-+		eventmgr->features[PP_Feature_PowerPlay].supported = true;
-+		eventmgr->features[PP_Feature_PowerPlay].version = PEM_CURRENT_POWERPLAY_FEATURE_VERSION;
-+		eventmgr->features[PP_Feature_PowerPlay].enabled_default = true;
-+		eventmgr->features[PP_Feature_PowerPlay].enabled = true;
-+	} else {
-+		eventmgr->features[PP_Feature_PowerPlay].supported = false;
-+		eventmgr->features[PP_Feature_PowerPlay].enabled = false;
-+		eventmgr->features[PP_Feature_PowerPlay].enabled_default = false;
-+	}
-+
-+	eventmgr->features[PP_Feature_Force3DClock].supported = true;
-+	eventmgr->features[PP_Feature_Force3DClock].enabled = false;
-+	eventmgr->features[PP_Feature_Force3DClock].enabled_default = false;
-+	eventmgr->features[PP_Feature_Force3DClock].version = 1;
-+
-+	/* over drive*/
-+	eventmgr->features[PP_Feature_User2DPerformance].version = 4;
-+	eventmgr->features[PP_Feature_User3DPerformance].version = 4;
-+	eventmgr->features[PP_Feature_OverdriveTest].version = 4;
-+
-+	eventmgr->features[PP_Feature_OverDrive].version = 4;
-+	eventmgr->features[PP_Feature_OverDrive].enabled = false;
-+	eventmgr->features[PP_Feature_OverDrive].enabled_default = false;
-+
-+	eventmgr->features[PP_Feature_User2DPerformance].supported = false;
-+	eventmgr->features[PP_Feature_User2DPerformance].enabled = false;
-+	eventmgr->features[PP_Feature_User2DPerformance].enabled_default = false;
-+
-+	eventmgr->features[PP_Feature_User3DPerformance].supported = false;
-+	eventmgr->features[PP_Feature_User3DPerformance].enabled = false;
-+	eventmgr->features[PP_Feature_User3DPerformance].enabled_default = false;
-+
-+	eventmgr->features[PP_Feature_OverdriveTest].supported = false;
-+	eventmgr->features[PP_Feature_OverdriveTest].enabled = false;
-+	eventmgr->features[PP_Feature_OverdriveTest].enabled_default = false;
-+
-+	eventmgr->features[PP_Feature_OverDrive].supported = false;
-+
-+	eventmgr->features[PP_Feature_PowerBudgetWaiver].enabled_default = false;
-+	eventmgr->features[PP_Feature_PowerBudgetWaiver].version = 1;
-+	eventmgr->features[PP_Feature_PowerBudgetWaiver].supported = false;
-+	eventmgr->features[PP_Feature_PowerBudgetWaiver].enabled = false;
-+
-+	/* Multi UVD States support */
-+	eventmgr->features[PP_Feature_MultiUVDState].supported = false;
-+	eventmgr->features[PP_Feature_MultiUVDState].enabled = false;
-+	eventmgr->features[PP_Feature_MultiUVDState].enabled_default = false;
-+
-+	/* Dynamic UVD States support */
-+	eventmgr->features[PP_Feature_DynamicUVDState].supported = false;
-+	eventmgr->features[PP_Feature_DynamicUVDState].enabled = false;
-+	eventmgr->features[PP_Feature_DynamicUVDState].enabled_default = false;
-+
-+	/* VCE DPM support */
-+	eventmgr->features[PP_Feature_VCEDPM].supported = false;
-+	eventmgr->features[PP_Feature_VCEDPM].enabled = false;
-+	eventmgr->features[PP_Feature_VCEDPM].enabled_default = false;
-+
-+	/* ACP PowerGating support */
-+	eventmgr->features[PP_Feature_ACP_POWERGATING].supported = false;
-+	eventmgr->features[PP_Feature_ACP_POWERGATING].enabled = false;
-+	eventmgr->features[PP_Feature_ACP_POWERGATING].enabled_default = false;
-+
-+	/* PPM support */
-+	eventmgr->features[PP_Feature_PPM].version = 1;
-+	eventmgr->features[PP_Feature_PPM].supported = false;
-+	eventmgr->features[PP_Feature_PPM].enabled = false;
-+
-+	/* FFC support (enables fan and temp settings, Gemini needs temp settings) */
-+	if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_ODFuzzyFanControlSupport) ||
-+	    phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_GeminiRegulatorFanControlSupport)) {
-+		eventmgr->features[PP_Feature_FFC].version = 1;
-+		eventmgr->features[PP_Feature_FFC].supported = true;
-+		eventmgr->features[PP_Feature_FFC].enabled = true;
-+		eventmgr->features[PP_Feature_FFC].enabled_default = true;
-+	} else {
-+		eventmgr->features[PP_Feature_FFC].supported = false;
-+		eventmgr->features[PP_Feature_FFC].enabled = false;
-+		eventmgr->features[PP_Feature_FFC].enabled_default = false;
-+	}
-+
-+	eventmgr->features[PP_Feature_VariBright].supported = false;
-+	eventmgr->features[PP_Feature_VariBright].enabled = false;
-+	eventmgr->features[PP_Feature_VariBright].enabled_default = false;
-+
-+	eventmgr->features[PP_Feature_BACO].supported = false;
-+	eventmgr->features[PP_Feature_BACO].supported = false;
-+	eventmgr->features[PP_Feature_BACO].enabled_default = false;
-+
-+	/* PowerDown feature support */
-+	eventmgr->features[PP_Feature_PowerDown].supported = false;
-+	eventmgr->features[PP_Feature_PowerDown].enabled = false;
-+	eventmgr->features[PP_Feature_PowerDown].enabled_default = false;
-+
-+	eventmgr->features[PP_Feature_FPS].version = 1;
-+	eventmgr->features[PP_Feature_FPS].supported = false;
-+	eventmgr->features[PP_Feature_FPS].enabled_default = false;
-+	eventmgr->features[PP_Feature_FPS].enabled = false;
-+
-+	eventmgr->features[PP_Feature_ViPG].version = 1;
-+	eventmgr->features[PP_Feature_ViPG].supported = false;
-+	eventmgr->features[PP_Feature_ViPG].enabled_default = false;
-+	eventmgr->features[PP_Feature_ViPG].enabled = false;
-+}
-+
-+int pem_register_interrupts(struct pp_eventmgr *eventmgr)
-+{
-+	int result = 0;
-+
-+	/* TODO:
-+	 * 1. Register thermal events interrupt
-+	 * 2. Register CTF event interrupt
-+	 * 3. Register for vbios events interrupt
-+	 * 4. Register External Throttle Interrupt
-+	 * 5. Register Smc To Host Interrupt
-+	 * */
-+	return result;
-+}
-+
-+
-+int pem_unregister_interrupts(struct pp_eventmgr *eventmgr)
-+{
-+	return 0;
-+}
-+
-+
-+void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr)
-+{
-+	eventmgr->features[PP_Feature_MultiUVDState].supported = false;
-+	eventmgr->features[PP_Feature_VariBright].supported = false;
-+	eventmgr->features[PP_Feature_PowerBudgetWaiver].supported = false;
-+	eventmgr->features[PP_Feature_OverDrive].supported = false;
-+	eventmgr->features[PP_Feature_OverdriveTest].supported = false;
-+	eventmgr->features[PP_Feature_User3DPerformance].supported = false;
-+	eventmgr->features[PP_Feature_User2DPerformance].supported = false;
-+	eventmgr->features[PP_Feature_PowerPlay].supported = false;
-+	eventmgr->features[PP_Feature_Force3DClock].supported = false;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
-new file mode 100644
-index 0000000..9ef96aa
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _EVENTINIT_H_
-+#define _EVENTINIT_H_
-+
-+#define PEM_CURRENT_POWERPLAY_FEATURE_VERSION 4
-+
-+void pem_init_feature_info(struct pp_eventmgr *eventmgr);
-+void pem_uninit_featureInfo(struct pp_eventmgr *eventmgr);
-+int pem_register_interrupts(struct pp_eventmgr *eventmgr);
-+int pem_unregister_interrupts(struct pp_eventmgr *eventmgr);
-+
-+#endif /* _EVENTINIT_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
-new file mode 100644
-index 0000000..1e2ad56
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
-@@ -0,0 +1,215 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include "eventmanagement.h"
-+#include "eventmgr.h"
-+#include "eventactionchains.h"
-+
-+int pem_init_event_action_chains(struct pp_eventmgr *eventmgr)
-+{
-+	int i;
-+
-+	for (i = 0; i < AMD_PP_EVENT_MAX; i++)
-+		eventmgr->event_chain[i] = NULL;
-+
-+	eventmgr->event_chain[AMD_PP_EVENT_SUSPEND] = pem_get_suspend_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_INITIALIZE] = pem_get_initialize_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_UNINITIALIZE] = pem_get_uninitialize_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_POWER_SOURCE_CHANGE] = pem_get_power_source_change_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_HIBERNATE] = pem_get_hibernate_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_RESUME] = pem_get_resume_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_THERMAL_NOTIFICATION] = pem_get_thermal_notification_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_VBIOS_NOTIFICATION] = pem_get_vbios_notification_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_ENTER_THERMAL_STATE] = pem_get_enter_thermal_state_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_EXIT_THERMAL_STATE] = pem_get_exit_thermal_state_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_ENABLE_POWER_PLAY] = pem_get_enable_powerplay_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_DISABLE_POWER_PLAY] = pem_get_disable_powerplay_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST] = pem_get_enable_overdrive_test_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST] = pem_get_disable_overdrive_test_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING] = pem_get_enable_gfx_clock_gating_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING] = pem_get_disable_gfx_clock_gating_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_ENABLE_CGPG] = pem_get_enable_cgpg_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_DISABLE_CGPG] = pem_get_disable_cgpg_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_COMPLETE_INIT] = pem_get_complete_init_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_SCREEN_ON] = pem_get_screen_on_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_SCREEN_OFF] = pem_get_screen_off_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_PRE_SUSPEND] = pem_get_pre_suspend_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_PRE_RESUME] = pem_get_pre_resume_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_ENABLE_USER_STATE] = pem_enable_user_state_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_READJUST_POWER_STATE] = pem_readjust_power_state_action_chain(eventmgr);
-+	eventmgr->event_chain[AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE] = pem_display_config_change_action_chain(eventmgr);
-+	return 0;
-+}
-+
-+int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data)
-+{
-+	const pem_event_action **paction_chain;
-+	const pem_event_action *psub_chain;
-+	int tmp_result = 0;
-+	int result = 0;
-+
-+	if (eventmgr == NULL || event_chain == NULL || event_data == NULL)
-+		return -EINVAL;
-+
-+	for (paction_chain = event_chain->action_chain; NULL != *paction_chain; paction_chain++) {
-+		if (0 != result)
-+			return result;
-+
-+		for (psub_chain = *paction_chain; NULL != *psub_chain; psub_chain++) {
-+			tmp_result = (*psub_chain)(eventmgr, event_data);
-+			if (0 == result)
-+				result = tmp_result;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+const struct action_chain *pem_get_suspend_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &suspend_action_chain;
-+}
-+
-+const struct action_chain *pem_get_initialize_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &initialize_action_chain;
-+}
-+
-+const struct action_chain *pem_get_uninitialize_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &uninitialize_action_chain;
-+}
-+
-+const struct action_chain *pem_get_power_source_change_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &power_source_change_action_chain_pp_enabled;  /* other case base on feature info*/
-+}
-+
-+const struct action_chain *pem_get_resume_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &resume_action_chain;
-+}
-+
-+const struct action_chain *pem_get_hibernate_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_thermal_notification_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_vbios_notification_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_enter_thermal_state_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_exit_thermal_state_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_enable_powerplay_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_disable_powerplay_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_enable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_disable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_enable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &enable_gfx_clock_gating_action_chain;
-+}
-+
-+const struct action_chain *pem_get_disable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &disable_gfx_clock_gating_action_chain;
-+}
-+
-+const struct action_chain *pem_get_enable_cgpg_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &enable_cgpg_action_chain;
-+}
-+
-+const struct action_chain *pem_get_disable_cgpg_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &disable_cgpg_action_chain;
-+}
-+
-+const struct action_chain *pem_get_complete_init_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &complete_init_action_chain;
-+}
-+
-+const struct action_chain *pem_get_screen_on_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_screen_off_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_pre_suspend_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_get_pre_resume_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return NULL;
-+}
-+
-+const struct action_chain *pem_enable_user_state_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &enable_user_state_action_chain;
-+}
-+
-+const struct action_chain *pem_readjust_power_state_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &readjust_power_state_action_chain;
-+}
-+
-+const struct action_chain *pem_display_config_change_action_chain(struct pp_eventmgr *eventmgr)
-+{
-+	return &display_config_change_action_chain;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h
-new file mode 100644
-index 0000000..383d4b2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.h
-@@ -0,0 +1,59 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _EVENT_MANAGEMENT_H_
-+#define _EVENT_MANAGEMENT_H_
-+
-+#include "eventmgr.h"
-+
-+int pem_init_event_action_chains(struct pp_eventmgr *eventmgr);
-+int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data);
-+const struct action_chain *pem_get_suspend_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_initialize_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_uninitialize_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_power_source_change_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_resume_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_hibernate_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_thermal_notification_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_vbios_notification_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_enter_thermal_state_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_exit_thermal_state_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_enable_powerplay_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_disable_powerplay_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_enable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_disable_overdrive_test_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_enable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_disable_gfx_clock_gating_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_enable_cgpg_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_disable_cgpg_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_complete_init_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_screen_on_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_screen_off_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_pre_suspend_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_get_pre_resume_action_chain(struct pp_eventmgr *eventmgr);
-+
-+extern const struct action_chain *pem_enable_user_state_action_chain(struct pp_eventmgr *eventmgr);
-+extern const struct action_chain *pem_readjust_power_state_action_chain(struct pp_eventmgr *eventmgr);
-+const struct action_chain *pem_display_config_change_action_chain(struct pp_eventmgr *eventmgr);
-+
-+
-+#endif /* _EVENT_MANAGEMENT_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
-new file mode 100644
-index 0000000..52a3efc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
-@@ -0,0 +1,114 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include "eventmgr.h"
-+#include "hwmgr.h"
-+#include "eventinit.h"
-+#include "eventmanagement.h"
-+
-+static int pem_init(struct pp_eventmgr *eventmgr)
-+{
-+	int result = 0;
-+	struct pem_event_data event_data;
-+
-+	/* Initialize PowerPlay feature info */
-+	pem_init_feature_info(eventmgr);
-+
-+	/* Initialize event action chains */
-+	pem_init_event_action_chains(eventmgr);
-+
-+	/* Call initialization event */
-+	result = pem_handle_event(eventmgr, AMD_PP_EVENT_INITIALIZE, &event_data);
-+
-+	if (0 != result)
-+		return result;
-+
-+	/* Register interrupt callback functions */
-+	result = pem_register_interrupts(eventmgr);
-+	return 0;
-+}
-+
-+static void pem_fini(struct pp_eventmgr *eventmgr)
-+{
-+	struct pem_event_data event_data;
-+
-+	pem_uninit_featureInfo(eventmgr);
-+	pem_unregister_interrupts(eventmgr);
-+
-+	pem_handle_event(eventmgr, AMD_PP_EVENT_UNINITIALIZE, &event_data);
-+
-+	if (eventmgr != NULL)
-+		kfree(eventmgr);
-+}
-+
-+int eventmgr_init(struct pp_instance *handle)
-+{
-+	int result = 0;
-+	struct pp_eventmgr *eventmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	eventmgr = kzalloc(sizeof(struct pp_eventmgr), GFP_KERNEL);
-+	if (eventmgr == NULL)
-+		return -ENOMEM;
-+
-+	eventmgr->hwmgr = handle->hwmgr;
-+	handle->eventmgr = eventmgr;
-+
-+	eventmgr->platform_descriptor = &(eventmgr->hwmgr->platform_descriptor);
-+	eventmgr->pp_eventmgr_init = pem_init;
-+	eventmgr->pp_eventmgr_fini = pem_fini;
-+
-+	return result;
-+}
-+
-+int eventmgr_fini(struct pp_eventmgr *eventmgr)
-+{
-+	kfree(eventmgr);
-+	return 0;
-+}
-+
-+static int pem_handle_event_unlocked(struct pp_eventmgr *eventmgr, enum amd_pp_event event, struct pem_event_data *data)
-+{
-+	if (eventmgr == NULL || event >= AMD_PP_EVENT_MAX || data == NULL)
-+		return -EINVAL;
-+
-+	return pem_excute_event_chain(eventmgr, eventmgr->event_chain[event], data);
-+}
-+
-+int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event, struct pem_event_data *event_data)
-+{
-+	int r = 0;
-+
-+	r = pem_handle_event_unlocked(eventmgr, event, event_data);
-+
-+	return r;
-+}
-+
-+bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr)
-+{
-+	return (eventmgr->block_adjust_power_state || phm_is_hw_access_blocked(eventmgr->hwmgr));
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-new file mode 100644
-index 0000000..49d8a29
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-@@ -0,0 +1,395 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "eventmgr.h"
-+#include "eventsubchains.h"
-+#include "eventtasks.h"
-+#include "hardwaremanager.h"
-+
-+const pem_event_action reset_display_phy_access_tasks[] = {
-+	pem_task_reset_display_phys_access,
-+	NULL
-+};
-+
-+const pem_event_action broadcast_power_policy_tasks[] = {
-+	/* PEM_Task_BroadcastPowerPolicyChange, */
-+	NULL
-+};
-+
-+const pem_event_action unregister_interrupt_tasks[] = {
-+	pem_task_unregister_interrupts,
-+	NULL
-+};
-+
-+/* Disable GFX Voltage Islands Power Gating */
-+const pem_event_action disable_gfx_voltage_island_powergating_tasks[] = {
-+	pem_task_disable_voltage_island_power_gating,
-+	NULL
-+};
-+
-+const pem_event_action disable_gfx_clockgating_tasks[] = {
-+	pem_task_disable_gfx_clock_gating,
-+	NULL
-+};
-+
-+const pem_event_action block_adjust_power_state_tasks[] = {
-+	pem_task_block_adjust_power_state,
-+	NULL
-+};
-+
-+
-+const pem_event_action unblock_adjust_power_state_tasks[] = {
-+	pem_task_unblock_adjust_power_state,
-+	NULL
-+};
-+
-+const pem_event_action set_performance_state_tasks[] = {
-+	pem_task_set_performance_state,
-+	NULL
-+};
-+
-+const pem_event_action get_2d_performance_state_tasks[] = {
-+	pem_task_get_2D_performance_state_id,
-+	NULL
-+};
-+
-+const pem_event_action conditionally_force3D_performance_state_tasks[] = {
-+	pem_task_conditionally_force_3d_performance_state,
-+	NULL
-+};
-+
-+const pem_event_action process_vbios_eventinfo_tasks[] = {
-+	/* PEM_Task_ProcessVbiosEventInfo,*/
-+	NULL
-+};
-+
-+const pem_event_action enable_dynamic_state_management_tasks[] = {
-+	/* PEM_Task_ResetBAPMPolicyChangedFlag,*/
-+	pem_task_get_boot_state_id,
-+	pem_task_enable_dynamic_state_management,
-+	pem_task_register_interrupts,
-+	NULL
-+};
-+
-+const pem_event_action enable_clock_power_gatings_tasks[] = {
-+	pem_task_enable_clock_power_gatings_tasks,
-+	pem_task_powerdown_uvd_tasks,
-+	pem_task_powerdown_vce_tasks,
-+	NULL
-+};
-+
-+const pem_event_action setup_asic_tasks[] = {
-+	pem_task_setup_asic,
-+	NULL
-+};
-+
-+const pem_event_action power_budget_tasks[] = {
-+	/* TODO
-+	 * PEM_Task_PowerBudgetWaiverAvailable,
-+	 * PEM_Task_PowerBudgetWarningMessage,
-+	 * PEM_Task_PruneStatesBasedOnPowerBudget,
-+	*/
-+	NULL
-+};
-+
-+const pem_event_action system_config_tasks[] = {
-+	/* PEM_Task_PruneStatesBasedOnSystemConfig,*/
-+	NULL
-+};
-+
-+
-+const pem_event_action conditionally_force_3d_performance_state_tasks[] = {
-+	pem_task_conditionally_force_3d_performance_state,
-+	NULL
-+};
-+
-+const pem_event_action ungate_all_display_phys_tasks[] = {
-+	/* PEM_Task_GetDisplayPhyAccessInfo */
-+	NULL
-+};
-+
-+const pem_event_action uninitialize_display_phy_access_tasks[] = {
-+	/* PEM_Task_UninitializeDisplayPhysAccess, */
-+	NULL
-+};
-+
-+const pem_event_action disable_gfx_voltage_island_power_gating_tasks[] = {
-+	/* PEM_Task_DisableVoltageIslandPowerGating, */
-+	NULL
-+};
-+
-+const pem_event_action disable_gfx_clock_gating_tasks[] = {
-+	pem_task_disable_gfx_clock_gating,
-+	NULL
-+};
-+
-+const pem_event_action set_boot_state_tasks[] = {
-+	pem_task_get_boot_state_id,
-+	pem_task_set_boot_state,
-+	NULL
-+};
-+
-+const pem_event_action adjust_power_state_tasks[] = {
-+	pem_task_notify_hw_mgr_display_configuration_change,
-+	pem_task_adjust_power_state,
-+	/*pem_task_notify_smc_display_config_after_power_state_adjustment,*/
-+	pem_task_update_allowed_performance_levels,
-+	/* to do pem_task_Enable_disable_bapm, */
-+	NULL
-+};
-+
-+const pem_event_action disable_dynamic_state_management_tasks[] = {
-+	pem_task_unregister_interrupts,
-+	pem_task_get_boot_state_id,
-+	pem_task_disable_dynamic_state_management,
-+	NULL
-+};
-+
-+const pem_event_action disable_clock_power_gatings_tasks[] = {
-+	pem_task_disable_clock_power_gatings_tasks,
-+	NULL
-+};
-+
-+const pem_event_action cleanup_asic_tasks[] = {
-+	/* PEM_Task_DisableFPS,*/
-+	pem_task_cleanup_asic,
-+	NULL
-+};
-+
-+const pem_event_action prepare_for_pnp_stop_tasks[] = {
-+	/* PEM_Task_PrepareForPnpStop,*/
-+	NULL
-+};
-+
-+const pem_event_action set_power_source_tasks[] = {
-+	pem_task_set_power_source,
-+	pem_task_notify_hw_of_power_source,
-+	NULL
-+};
-+
-+const pem_event_action set_power_saving_state_tasks[] = {
-+	pem_task_reset_power_saving_state,
-+	pem_task_get_power_saving_state,
-+	pem_task_set_power_saving_state,
-+	/* PEM_Task_ResetODDCState,
-+	 * PEM_Task_GetODDCState,
-+	 * PEM_Task_SetODDCState,*/
-+	NULL
-+};
-+
-+const pem_event_action enable_disable_fps_tasks[] = {
-+	/* PEM_Task_EnableDisableFPS,*/
-+	NULL
-+};
-+
-+const pem_event_action set_nbmcu_state_tasks[] = {
-+	/* PEM_Task_NBMCUStateChange,*/
-+	NULL
-+};
-+
-+const pem_event_action reset_hardware_dc_notification_tasks[] = {
-+	/* PEM_Task_ResetHardwareDCNotification,*/
-+	NULL
-+};
-+
-+
-+const pem_event_action notify_smu_suspend_tasks[] = {
-+	/* PEM_Task_NotifySMUSuspend,*/
-+	NULL
-+};
-+
-+const pem_event_action disable_smc_firmware_ctf_tasks[] = {
-+	/* PEM_Task_DisableSMCFirmwareCTF,*/
-+	NULL
-+};
-+
-+const pem_event_action disable_fps_tasks[] = {
-+	/* PEM_Task_DisableFPS,*/
-+	NULL
-+};
-+
-+const pem_event_action vari_bright_suspend_tasks[] = {
-+	/* PEM_Task_VariBright_Suspend,*/
-+	NULL
-+};
-+
-+const pem_event_action reset_fan_speed_to_default_tasks[] = {
-+	/* PEM_Task_ResetFanSpeedToDefault,*/
-+	NULL
-+};
-+
-+const pem_event_action power_down_asic_tasks[] = {
-+	/* PEM_Task_DisableFPS,*/
-+	pem_task_power_down_asic,
-+	NULL
-+};
-+
-+const pem_event_action disable_stutter_mode_tasks[] = {
-+	/* PEM_Task_DisableStutterMode,*/
-+	NULL
-+};
-+
-+const pem_event_action set_connected_standby_tasks[] = {
-+	/* PEM_Task_SetConnectedStandby,*/
-+	NULL
-+};
-+
-+const pem_event_action block_hw_access_tasks[] = {
-+	pem_task_block_hw_access,
-+	NULL
-+};
-+
-+const pem_event_action unblock_hw_access_tasks[] = {
-+	pem_task_un_block_hw_access,
-+	NULL
-+};
-+
-+const pem_event_action resume_connected_standby_tasks[] = {
-+	/* PEM_Task_ResumeConnectedStandby,*/
-+	NULL
-+};
-+
-+const pem_event_action notify_smu_resume_tasks[] = {
-+	/* PEM_Task_NotifySMUResume,*/
-+	NULL
-+};
-+
-+const pem_event_action reset_display_configCounter_tasks[] = {
-+	pem_task_reset_display_phys_access,
-+	NULL
-+};
-+
-+const pem_event_action update_dal_configuration_tasks[] = {
-+	/* PEM_Task_CheckVBlankTime,*/
-+	NULL
-+};
-+
-+const pem_event_action vari_bright_resume_tasks[] = {
-+	/* PEM_Task_VariBright_Resume,*/
-+	NULL
-+};
-+
-+const pem_event_action notify_hw_power_source_tasks[] = {
-+	pem_task_notify_hw_of_power_source,
-+	NULL
-+};
-+
-+const pem_event_action process_vbios_event_info_tasks[] = {
-+	/* PEM_Task_ProcessVbiosEventInfo,*/
-+	NULL
-+};
-+
-+const pem_event_action enable_gfx_clock_gating_tasks[] = {
-+	pem_task_enable_gfx_clock_gating,
-+	NULL
-+};
-+
-+const pem_event_action enable_gfx_voltage_island_power_gating_tasks[] = {
-+	pem_task_enable_voltage_island_power_gating,
-+	NULL
-+};
-+
-+const pem_event_action reset_clock_gating_tasks[] = {
-+	/* PEM_Task_ResetClockGating*/
-+	NULL
-+};
-+
-+const pem_event_action notify_smu_vpu_recovery_end_tasks[] = {
-+	/* PEM_Task_NotifySmuVPURecoveryEnd,*/
-+	NULL
-+};
-+
-+const pem_event_action disable_vpu_cap_tasks[] = {
-+	/* PEM_Task_DisableVPUCap,*/
-+	NULL
-+};
-+
-+const pem_event_action execute_escape_sequence_tasks[] = {
-+	/* PEM_Task_ExecuteEscapesequence,*/
-+	NULL
-+};
-+
-+const pem_event_action notify_power_state_change_tasks[] = {
-+	pem_task_notify_power_state_change,
-+	NULL
-+};
-+
-+const pem_event_action enable_cgpg_tasks[] = {
-+	pem_task_enable_cgpg,
-+	NULL
-+};
-+
-+const pem_event_action disable_cgpg_tasks[] = {
-+	pem_task_disable_cgpg,
-+	NULL
-+};
-+
-+const pem_event_action enable_user_2d_performance_tasks[] = {
-+	/* PEM_Task_SetUser2DPerformanceFlag,*/
-+	/* PEM_Task_UpdateUser2DPerformanceEnableEvents,*/
-+	NULL
-+};
-+
-+const pem_event_action add_user_2d_performance_state_tasks[] = {
-+	/* PEM_Task_Get2DPerformanceTemplate,*/
-+	/* PEM_Task_AllocateNewPowerStateMemory,*/
-+	/* PEM_Task_CopyNewPowerStateInfo,*/
-+	/* PEM_Task_UpdateNewPowerStateClocks,*/
-+	/* PEM_Task_UpdateNewPowerStateUser2DPerformanceFlag,*/
-+	/* PEM_Task_AddPowerState,*/
-+	/* PEM_Task_ReleaseNewPowerStateMemory,*/
-+	NULL
-+};
-+
-+const pem_event_action delete_user_2d_performance_state_tasks[] = {
-+	/* PEM_Task_GetCurrentUser2DPerformanceStateID,*/
-+	/* PEM_Task_DeletePowerState,*/
-+	/* PEM_Task_SetCurrentUser2DPerformanceStateID,*/
-+	NULL
-+};
-+
-+const pem_event_action disable_user_2d_performance_tasks[] = {
-+	/* PEM_Task_ResetUser2DPerformanceFlag,*/
-+	/* PEM_Task_UpdateUser2DPerformanceDisableEvents,*/
-+	NULL
-+};
-+
-+const pem_event_action enable_stutter_mode_tasks[] = {
-+	pem_task_enable_stutter_mode,
-+	NULL
-+};
-+
-+const pem_event_action enable_disable_bapm_tasks[] = {
-+	/*PEM_Task_EnableDisableBAPM,*/
-+	NULL
-+};
-+
-+const pem_event_action reset_boot_state_tasks[] = {
-+	pem_task_reset_boot_state,
-+	NULL
-+};
-+
-+const pem_event_action create_new_user_performance_state_tasks[] = {
-+	pem_task_create_user_performance_state,
-+	NULL
-+};
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-new file mode 100644
-index 0000000..27e0e61
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _EVENT_SUB_CHAINS_H_
-+#define _EVENT_SUB_CHAINS_H_
-+
-+#include "eventmgr.h"
-+
-+extern const pem_event_action reset_display_phy_access_tasks[];
-+extern const pem_event_action broadcast_power_policy_tasks[];
-+extern const pem_event_action unregister_interrupt_tasks[];
-+extern const pem_event_action disable_GFX_voltage_island_powergating_tasks[];
-+extern const pem_event_action disable_GFX_clockgating_tasks[];
-+extern const pem_event_action block_adjust_power_state_tasks[];
-+extern const pem_event_action unblock_adjust_power_state_tasks[];
-+extern const pem_event_action set_performance_state_tasks[];
-+extern const pem_event_action get_2D_performance_state_tasks[];
-+extern const pem_event_action conditionally_force3D_performance_state_tasks[];
-+extern const pem_event_action process_vbios_eventinfo_tasks[];
-+extern const pem_event_action enable_dynamic_state_management_tasks[];
-+extern const pem_event_action enable_clock_power_gatings_tasks[];
-+extern const pem_event_action conditionally_force3D_performance_state_tasks[];
-+extern const pem_event_action setup_asic_tasks[];
-+extern const pem_event_action power_budget_tasks[];
-+extern const pem_event_action system_config_tasks[];
-+extern const pem_event_action get_2d_performance_state_tasks[];
-+extern const pem_event_action conditionally_force_3d_performance_state_tasks[];
-+extern const pem_event_action ungate_all_display_phys_tasks[];
-+extern const pem_event_action uninitialize_display_phy_access_tasks[];
-+extern const pem_event_action disable_gfx_voltage_island_power_gating_tasks[];
-+extern const pem_event_action disable_gfx_clock_gating_tasks[];
-+extern const pem_event_action set_boot_state_tasks[];
-+extern const pem_event_action adjust_power_state_tasks[];
-+extern const pem_event_action disable_dynamic_state_management_tasks[];
-+extern const pem_event_action disable_clock_power_gatings_tasks[];
-+extern const pem_event_action cleanup_asic_tasks[];
-+extern const pem_event_action prepare_for_pnp_stop_tasks[];
-+extern const pem_event_action set_power_source_tasks[];
-+extern const pem_event_action set_power_saving_state_tasks[];
-+extern const pem_event_action enable_disable_fps_tasks[];
-+extern const pem_event_action set_nbmcu_state_tasks[];
-+extern const pem_event_action reset_hardware_dc_notification_tasks[];
-+extern const pem_event_action notify_smu_suspend_tasks[];
-+extern const pem_event_action disable_smc_firmware_ctf_tasks[];
-+extern const pem_event_action disable_fps_tasks[];
-+extern const pem_event_action vari_bright_suspend_tasks[];
-+extern const pem_event_action reset_fan_speed_to_default_tasks[];
-+extern const pem_event_action power_down_asic_tasks[];
-+extern const pem_event_action disable_stutter_mode_tasks[];
-+extern const pem_event_action set_connected_standby_tasks[];
-+extern const pem_event_action block_hw_access_tasks[];
-+extern const pem_event_action unblock_hw_access_tasks[];
-+extern const pem_event_action resume_connected_standby_tasks[];
-+extern const pem_event_action notify_smu_resume_tasks[];
-+extern const pem_event_action reset_display_configCounter_tasks[];
-+extern const pem_event_action update_dal_configuration_tasks[];
-+extern const pem_event_action vari_bright_resume_tasks[];
-+extern const pem_event_action notify_hw_power_source_tasks[];
-+extern const pem_event_action process_vbios_event_info_tasks[];
-+extern const pem_event_action enable_gfx_clock_gating_tasks[];
-+extern const pem_event_action enable_gfx_voltage_island_power_gating_tasks[];
-+extern const pem_event_action reset_clock_gating_tasks[];
-+extern const pem_event_action notify_smu_vpu_recovery_end_tasks[];
-+extern const pem_event_action disable_vpu_cap_tasks[];
-+extern const pem_event_action execute_escape_sequence_tasks[];
-+extern const pem_event_action notify_power_state_change_tasks[];
-+extern const pem_event_action enable_cgpg_tasks[];
-+extern const pem_event_action disable_cgpg_tasks[];
-+extern const pem_event_action enable_user_2d_performance_tasks[];
-+extern const pem_event_action add_user_2d_performance_state_tasks[];
-+extern const pem_event_action delete_user_2d_performance_state_tasks[];
-+extern const pem_event_action disable_user_2d_performance_tasks[];
-+extern const pem_event_action enable_stutter_mode_tasks[];
-+extern const pem_event_action enable_disable_bapm_tasks[];
-+extern const pem_event_action reset_boot_state_tasks[];
-+extern const pem_event_action create_new_user_performance_state_tasks[];
-+
-+#endif /* _EVENT_SUB_CHAINS_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-new file mode 100644
-index 0000000..55d5490
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -0,0 +1,408 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "eventmgr.h"
-+#include "eventinit.h"
-+#include "eventmanagement.h"
-+#include "eventmanager.h"
-+#include "hardwaremanager.h"
-+#include "eventtasks.h"
-+#include "power_state.h"
-+#include "hwmgr.h"
-+#include "amd_powerplay.h"
-+#include "psm.h"
-+
-+int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+
-+	if (pem_is_hw_access_blocked(eventmgr))
-+		return 0;
-+
-+	phm_force_dpm_levels(eventmgr->hwmgr, AMD_DPM_FORCED_LEVEL_AUTO);
-+
-+	return 0;
-+}
-+
-+/* eventtasks_generic.c */
-+int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (pem_is_hw_access_blocked(eventmgr))
-+		return 0;
-+
-+	hwmgr = eventmgr->hwmgr;
-+	if (event_data->pnew_power_state != NULL)
-+		hwmgr->request_ps = event_data->pnew_power_state;
-+
-+	if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
-+		psm_adjust_power_state_dynamic(eventmgr, event_data->skip_state_adjust_rules);
-+	else
-+		psm_adjust_power_state_static(eventmgr, event_data->skip_state_adjust_rules);
-+
-+	return 0;
-+}
-+
-+int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_reset_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_update_new_power_state_clocks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_system_shutdown(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_register_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	return pem_unregister_interrupts(eventmgr);
-+}
-+
-+
-+
-+int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	int result;
-+
-+	result = psm_get_state_by_classification(eventmgr,
-+		PP_StateClassificationFlag_Boot,
-+		&(event_data->requested_state_id)
-+	);
-+
-+	if (0 == result)
-+		pem_set_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
-+	else
-+		pem_unset_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
-+
-+	return result;
-+}
-+
-+int pem_task_enable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	return phm_enable_dynamic_state_management(eventmgr->hwmgr);
-+}
-+
-+int pem_task_disable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_enable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	return phm_enable_clock_power_gatings(eventmgr->hwmgr);
-+}
-+
-+int pem_task_powerdown_uvd_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	return phm_powerdown_uvd(eventmgr->hwmgr);
-+}
-+
-+int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	phm_powergate_uvd(eventmgr->hwmgr, true);
-+	phm_powergate_vce(eventmgr->hwmgr, true);
-+	return 0;
-+}
-+
-+int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_start_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_stop_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_setup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	return phm_setup_asic(eventmgr->hwmgr);
-+}
-+
-+int pem_task_cleanup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_store_dal_configuration(struct pp_eventmgr *eventmgr, const struct amd_display_configuration *display_config)
-+{
-+	/* TODO */
-+	return 0;
-+	/*phm_store_dal_configuration_data(eventmgr->hwmgr, display_config) */
-+}
-+
-+int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	eventmgr->block_adjust_power_state = true;
-+	/* to do PHM_ResetIPSCounter(pEventMgr->pHwMgr);*/
-+	return 0;
-+}
-+
-+int pem_task_unblock_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	eventmgr->block_adjust_power_state = false;
-+	return 0;
-+}
-+
-+int pem_task_notify_power_state_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+/*powersaving*/
-+
-+int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_notify_hw_of_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_get_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_reset_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_set_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_set_screen_state_on(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_set_screen_state_off(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_enable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_disable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_enable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_enable_clock_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+
-+int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+
-+/* performance */
-+int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID))
-+		return psm_set_performance_states(eventmgr, &(event_data->requested_state_id));
-+
-+	return 0;
-+}
-+
-+int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_enable_stutter_mode(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	/* TODO */
-+	return 0;
-+}
-+
-+int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	int result;
-+
-+	if (eventmgr->features[PP_Feature_PowerPlay].supported &&
-+		!(eventmgr->features[PP_Feature_PowerPlay].enabled))
-+			result = psm_get_state_by_classification(eventmgr,
-+					PP_StateClassificationFlag_Boot,
-+					&(event_data->requested_state_id));
-+	else if (eventmgr->features[PP_Feature_User2DPerformance].enabled)
-+			result = psm_get_state_by_classification(eventmgr,
-+				   PP_StateClassificationFlag_User2DPerformance,
-+					&(event_data->requested_state_id));
-+	else
-+		result = psm_get_ui_state(eventmgr, PP_StateUILabel_Performance,
-+					&(event_data->requested_state_id));
-+
-+	if (0 == result)
-+		pem_set_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
-+	else
-+		pem_unset_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID);
-+
-+	return result;
-+}
-+
-+int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	state = hwmgr->ps;
-+
-+restart_search:
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->classification.ui_label & event_data->requested_ui_label) {
-+			event_data->pnew_power_state = state;
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+	}
-+
-+	switch (event_data->requested_ui_label) {
-+	case PP_StateUILabel_Battery:
-+	case PP_StateUILabel_Balanced:
-+		event_data->requested_ui_label = PP_StateUILabel_Performance;
-+		goto restart_search;
-+	default:
-+		break;
-+	}
-+	return -1;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-new file mode 100644
-index 0000000..37d3cf1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _EVENT_TASKS_H_
-+#define _EVENT_TASKS_H_
-+#include "eventmgr.h"
-+
-+struct amd_display_configuration;
-+
-+/* eventtasks_generic.c */
-+int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_reset_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_update_new_power_state_clocks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_system_shutdown(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_register_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_enable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_disable_dynamic_state_management(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_enable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_powerdown_uvd_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_start_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_stop_asic_block_usage(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_setup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_cleanup_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_store_dal_configuration (struct pp_eventmgr *eventmgr, const struct amd_display_configuration *display_config);
-+int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_unblock_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_notify_power_state_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+
-+/*powersaving*/
-+
-+int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_notify_hw_of_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_get_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_reset_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_set_power_saving_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_set_screen_state_on(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_set_screen_state_off(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_enable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_disable_voltage_island_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_enable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_enable_stutter_mode(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+
-+/* performance */
-+int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+
-+#endif /* _EVENT_TASKS_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-new file mode 100644
-index 0000000..7469c4c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-@@ -0,0 +1,111 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include "psm.h"
-+
-+int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->classification.ui_label & ui_label) {
-+			*state_id = state->id;
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+	}
-+	return -1;
-+}
-+
-+int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->classification.flags & flag) {
-+			*state_id = state->id;
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+	}
-+	return -1;
-+}
-+
-+int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *state_id)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	struct pp_hwmgr *hwmgr = eventmgr->hwmgr;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->id == *state_id) {
-+			hwmgr->request_ps = state;
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+	}
-+	return -1;
-+}
-+
-+
-+int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
-+{
-+
-+	const struct pp_power_state  *pcurrent;
-+	struct pp_power_state  *requested;
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (skip)
-+		return 0;
-+
-+	hwmgr = eventmgr->hwmgr;
-+	pcurrent = hwmgr->current_ps;
-+	requested = hwmgr->request_ps;
-+
-+	if (pcurrent != NULL || requested != NULL) {
-+		phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
-+		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
-+		hwmgr->current_ps = requested;
-+	}
-+	return 0;
-+}
-+
-+int psm_adjust_power_state_static(struct pp_eventmgr *eventmgr, bool skip)
-+{
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-new file mode 100644
-index 0000000..15abfac
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include "eventmgr.h"
-+#include "eventinit.h"
-+#include "eventmanagement.h"
-+#include "eventmanager.h"
-+#include "power_state.h"
-+
-+int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id);
-+
-+int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id);
-+
-+int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *state_id);
-+
-+int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip);
-+
-+int psm_adjust_power_state_static(struct pp_eventmgr *eventmgr, bool skip);
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h b/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h
-new file mode 100644
-index 0000000..b9d84de
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/eventmanager.h
-@@ -0,0 +1,109 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _EVENT_MANAGER_H_
-+#define _EVENT_MANAGER_H_
-+
-+#include "power_state.h"
-+#include "pp_power_source.h"
-+#include "hardwaremanager.h"
-+#include "pp_asicblocks.h"
-+
-+struct pp_eventmgr;
-+enum amd_pp_event;
-+
-+enum PEM_EventDataValid {
-+	PEM_EventDataValid_RequestedStateID = 0,
-+	PEM_EventDataValid_RequestedUILabel,
-+	PEM_EventDataValid_NewPowerState,
-+	PEM_EventDataValid_RequestedPowerSource,
-+	PEM_EventDataValid_RequestedClocks,
-+	PEM_EventDataValid_CurrentTemperature,
-+	PEM_EventDataValid_AsicBlocks,
-+	PEM_EventDataValid_ODParameters,
-+	PEM_EventDataValid_PXAdapterPrefs,
-+	PEM_EventDataValid_PXUserPrefs,
-+	PEM_EventDataValid_PXSwitchReason,
-+	PEM_EventDataValid_PXSwitchPhase,
-+	PEM_EventDataValid_HdVideo,
-+	PEM_EventDataValid_BacklightLevel,
-+	PEM_EventDatavalid_VariBrightParams,
-+	PEM_EventDataValid_VariBrightLevel,
-+	PEM_EventDataValid_VariBrightImmediateChange,
-+	PEM_EventDataValid_PercentWhite,
-+	PEM_EventDataValid_SdVideo,
-+	PEM_EventDataValid_HTLinkChangeReason,
-+	PEM_EventDataValid_HWBlocks,
-+	PEM_EventDataValid_RequestedThermalState,
-+	PEM_EventDataValid_MvcVideo,
-+	PEM_EventDataValid_Max
-+};
-+
-+typedef enum PEM_EventDataValid PEM_EventDataValid;
-+
-+/* Number of bits in ULONG variable */
-+#define PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD (sizeof(unsigned long)*8)
-+
-+/* Number of ULONG entries used by event data valid bits */
-+#define PEM_MAX_NUM_EVENTDATAVALID_ULONG_ENTRIES                                 \
-+		((PEM_EventDataValid_Max + PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD - 1) /  \
-+		PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD)
-+
-+static inline void pem_set_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field)
-+{
-+	fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] |=
-+		(1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD));
-+}
-+
-+static inline void pem_unset_event_data_valid(unsigned long *fields, PEM_EventDataValid valid_field)
-+{
-+	fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] &=
-+		~(1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD));
-+}
-+
-+static inline unsigned long pem_is_event_data_valid(const unsigned long *fields, PEM_EventDataValid valid_field)
-+{
-+	return fields[valid_field / PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD] &
-+		(1UL << (valid_field % PEM_MAX_NUM_EVENTDATAVALID_BITS_PER_FIELD));
-+}
-+
-+struct pem_event_data {
-+	unsigned long	valid_fields[100];
-+	unsigned long   requested_state_id;
-+	enum PP_StateUILabel requested_ui_label;
-+	struct pp_power_state  *pnew_power_state;
-+	enum pp_power_source  requested_power_source;
-+	struct PP_Clocks       requested_clocks;
-+	bool         skip_state_adjust_rules;
-+	struct phm_asic_blocks  asic_blocks;
-+	/* to doPP_ThermalState requestedThermalState;
-+	enum ThermalStateRequestSrc requestThermalStateSrc;
-+	PP_Temperature  currentTemperature;*/
-+
-+};
-+
-+int pem_handle_event(struct pp_eventmgr *eventmgr, enum amd_pp_event event,
-+		     struct pem_event_data *event_data);
-+
-+bool pem_is_hw_access_blocked(struct pp_eventmgr *eventmgr);
-+
-+#endif /* _EVENT_MANAGER_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
-new file mode 100644
-index 0000000..10437dc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
-@@ -0,0 +1,125 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _EVENTMGR_H_
-+#define _EVENTMGR_H_
-+
-+#include <linux/mutex.h>
-+#include "pp_instance.h"
-+#include "hardwaremanager.h"
-+#include "eventmanager.h"
-+#include "pp_feature.h"
-+#include "pp_power_source.h"
-+#include "power_state.h"
-+
-+typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr,
-+				struct pem_event_data *event_data);
-+
-+struct action_chain {
-+	const char *description;  /* action chain description for debugging purpose */
-+	const pem_event_action **action_chain; /* pointer to chain of event actions */
-+};
-+
-+struct pem_power_source_ui_state_info {
-+	enum PP_StateUILabel current_ui_label;
-+	enum PP_StateUILabel default_ui_lable;
-+	unsigned long    configurable_ui_mapping;
-+};
-+
-+struct pp_clock_range {
-+	uint32_t min_sclk_khz;
-+	uint32_t max_sclk_khz;
-+
-+	uint32_t min_mclk_khz;
-+	uint32_t max_mclk_khz;
-+
-+	uint32_t min_vclk_khz;
-+	uint32_t max_vclk_khz;
-+
-+	uint32_t min_dclk_khz;
-+	uint32_t max_dclk_khz;
-+
-+	uint32_t min_aclk_khz;
-+	uint32_t max_aclk_khz;
-+
-+	uint32_t min_eclk_khz;
-+	uint32_t max_eclk_khz;
-+};
-+
-+enum pp_state {
-+	UNINITIALIZED,
-+	INACTIVE,
-+	ACTIVE
-+};
-+
-+enum pp_ring_index {
-+	PP_RING_TYPE_GFX_INDEX = 0,
-+	PP_RING_TYPE_DMA_INDEX,
-+	PP_RING_TYPE_DMA1_INDEX,
-+	PP_RING_TYPE_UVD_INDEX,
-+	PP_RING_TYPE_VCE0_INDEX,
-+	PP_RING_TYPE_VCE1_INDEX,
-+	PP_RING_TYPE_CP1_INDEX,
-+	PP_RING_TYPE_CP2_INDEX,
-+	PP_NUM_RINGS,
-+};
-+
-+struct pp_request {
-+	uint32_t flags;
-+	uint32_t sclk;
-+	uint32_t sclk_throttle;
-+	uint32_t mclk;
-+	uint32_t vclk;
-+	uint32_t dclk;
-+	uint32_t eclk;
-+	uint32_t aclk;
-+	uint32_t iclk;
-+	uint32_t vp8clk;
-+	uint32_t rsv[32];
-+};
-+
-+struct pp_eventmgr {
-+	struct pp_hwmgr	*hwmgr;
-+	struct pp_smumgr *smumgr;
-+
-+	struct pp_feature_info features[PP_Feature_Max];
-+	const struct action_chain *event_chain[AMD_PP_EVENT_MAX];
-+	struct phm_platform_descriptor   *platform_descriptor;
-+	struct pp_clock_range clock_range;
-+	enum pp_power_source  current_power_source;
-+	struct pem_power_source_ui_state_info  ui_state_info[PP_PowerSource_Max];
-+	enum pp_state states[PP_NUM_RINGS];
-+	struct pp_request hi_req;
-+	struct list_head context_list;
-+	struct mutex lock;
-+	bool  block_adjust_power_state;
-+	bool enable_cg;
-+	bool enable_gfx_cgpg;
-+	int (*pp_eventmgr_init)(struct pp_eventmgr *eventmgr);
-+	void (*pp_eventmgr_fini)(struct pp_eventmgr *eventmgr);
-+};
-+
-+int eventmgr_init(struct pp_instance *handle);
-+int eventmgr_fini(struct pp_eventmgr *eventmgr);
-+
-+#endif /* _EVENTMGR_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h b/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h
-new file mode 100644
-index 0000000..0faf6a2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_feature.h
-@@ -0,0 +1,67 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _PP_FEATURE_H_
-+#define _PP_FEATURE_H_
-+
-+/**
-+ * PowerPlay feature ids.
-+ */
-+enum pp_feature {
-+	PP_Feature_PowerPlay = 0,
-+	PP_Feature_User2DPerformance,
-+	PP_Feature_User3DPerformance,
-+	PP_Feature_VariBright,
-+	PP_Feature_VariBrightOnPowerXpress,
-+	PP_Feature_ReducedRefreshRate,
-+	PP_Feature_GFXClockGating,
-+	PP_Feature_OverdriveTest,
-+	PP_Feature_OverDrive,
-+	PP_Feature_PowerBudgetWaiver,
-+	PP_Feature_PowerControl,
-+	PP_Feature_PowerControl_2,
-+	PP_Feature_MultiUVDState,
-+	PP_Feature_Force3DClock,
-+	PP_Feature_BACO,
-+	PP_Feature_PowerDown,
-+	PP_Feature_DynamicUVDState,
-+	PP_Feature_VCEDPM,
-+	PP_Feature_PPM,
-+	PP_Feature_ACP_POWERGATING,
-+	PP_Feature_FFC,
-+	PP_Feature_FPS,
-+	PP_Feature_ViPG,
-+	PP_Feature_Max
-+};
-+
-+/**
-+ * Struct for PowerPlay feature info.
-+ */
-+struct pp_feature_info {
-+	bool supported;               /* feature supported by PowerPlay */
-+	bool enabled;                 /* feature enabled in PowerPlay */
-+	bool enabled_default;        /* default enable status of the feature */
-+	uint32_t version;             /* feature version */
-+};
-+
-+#endif /* _PP_FEATURE_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-index 35dfcd9..7b60b61 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-@@ -25,10 +25,12 @@
- 
- #include "smumgr.h"
- #include "hwmgr.h"
-+#include "eventmgr.h"
- 
- struct pp_instance {
- 	struct pp_smumgr *smu_mgr;
- 	struct pp_hwmgr *hwmgr;
-+	struct pp_eventmgr *eventmgr;
- };
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0049-drm-amd-powerplay-implement-functions-of-amd_powerpl.patch b/common/recipes-kernel/linux/files/0049-drm-amd-powerplay-implement-functions-of-amd_powerpl.patch
deleted file mode 100644
index 9cd50e81..00000000
--- a/common/recipes-kernel/linux/files/0049-drm-amd-powerplay-implement-functions-of-amd_powerpl.patch
+++ /dev/null
@@ -1,273 +0,0 @@
-From 67e2f17bd49366a1695ac77aebc2594825533848 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 28 Aug 2015 12:56:43 +0800
-Subject: [PATCH 0049/1110] drm/amd/powerplay: implement functions of
- amd_powerplay_func
-
-This is the common interface for interacting with the powerplay
-module.
-
-v2: squash in fixes
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 191 ++++++++++++++++++++++++--
- 1 file changed, 183 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 1964a2a..66ccfc0 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -27,6 +27,8 @@
- #include "amd_shared.h"
- #include "amd_powerplay.h"
- #include "pp_instance.h"
-+#include "power_state.h"
-+#include "eventmanager.h"
- 
- static int pp_early_init(void *handle)
- {
-@@ -177,11 +179,31 @@ static int pp_set_powergating_state(void *handle,
- 
- static int pp_suspend(void *handle)
- {
-+	struct pp_instance *pp_handle;
-+	struct pp_eventmgr *eventmgr;
-+	struct pem_event_data event_data = { {0} };
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+	eventmgr = pp_handle->eventmgr;
-+	pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
- 	return 0;
- }
- 
- static int pp_resume(void *handle)
- {
-+	struct pp_instance *pp_handle;
-+	struct pp_eventmgr *eventmgr;
-+	struct pem_event_data event_data = { {0} };
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+	eventmgr = pp_handle->eventmgr;
-+	pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
- 	return 0;
- }
- 
-@@ -215,45 +237,198 @@ static int pp_dpm_fw_loading_complete(void *handle)
- static int pp_dpm_force_performance_level(void *handle,
- 					enum amd_dpm_forced_level level)
- {
-+	struct pp_instance *pp_handle;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	pp_handle = (struct pp_instance *)handle;
-+
-+	hwmgr = pp_handle->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	    hwmgr->hwmgr_func->force_dpm_level == NULL)
-+		return -EINVAL;
-+
-+	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-+
- 	return 0;
- }
-+
- static enum amd_dpm_forced_level pp_dpm_get_performance_level(
- 								void *handle)
- {
--	return 0;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	return (((struct pp_instance *)handle)->hwmgr->dpm_level);
- }
-+
- static int pp_dpm_get_sclk(void *handle, bool low)
- {
--	return 0;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	    hwmgr->hwmgr_func->get_sclk == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
- }
-+
- static int pp_dpm_get_mclk(void *handle, bool low)
- {
--	return 0;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	    hwmgr->hwmgr_func->get_mclk == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
- }
-+
- static int pp_dpm_powergate_vce(void *handle, bool gate)
- {
--	return 0;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	    hwmgr->hwmgr_func->powergate_vce == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- }
-+
- static int pp_dpm_powergate_uvd(void *handle, bool gate)
- {
--	return 0;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	    hwmgr->hwmgr_func->powergate_uvd == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
-+}
-+
-+static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
-+{
-+	switch (state) {
-+	case POWER_STATE_TYPE_BATTERY:
-+		return PP_StateUILabel_Battery;
-+	case POWER_STATE_TYPE_BALANCED:
-+		return PP_StateUILabel_Balanced;
-+	case POWER_STATE_TYPE_PERFORMANCE:
-+		return PP_StateUILabel_Performance;
-+	default:
-+		return PP_StateUILabel_None;
-+	}
- }
- 
- int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
- {
--	return 0;
-+	int ret = 0;
-+	struct pp_instance *pp_handle;
-+	struct pem_event_data data = { {0} };
-+
-+	pp_handle = (struct pp_instance *)handle;
-+
-+	if (pp_handle == NULL)
-+		return -EINVAL;
-+
-+	switch (event_id) {
-+	case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
-+		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
-+		break;
-+	case AMD_PP_EVENT_ENABLE_USER_STATE:
-+	{
-+		enum amd_pm_state_type  ps;
-+
-+		if (input == NULL)
-+			return -EINVAL;
-+		ps = *(unsigned long *)input;
-+
-+		data.requested_ui_label = power_state_convert(ps);
-+		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
-+	}
-+	break;
-+	default:
-+		break;
-+	}
-+	return ret;
- }
-+
- enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
- {
--	return 0;
-+	struct pp_hwmgr *hwmgr;
-+	struct pp_power_state *state;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->current_ps == NULL)
-+		return -EINVAL;
-+
-+	state = hwmgr->current_ps;
-+
-+	switch (state->classification.ui_label) {
-+	case PP_StateUILabel_Battery:
-+		return POWER_STATE_TYPE_BATTERY;
-+	case PP_StateUILabel_Balanced:
-+		return POWER_STATE_TYPE_BALANCED;
-+	case PP_StateUILabel_Performance:
-+		return POWER_STATE_TYPE_PERFORMANCE;
-+	default:
-+		return POWER_STATE_TYPE_DEFAULT;
-+	}
- }
-+
- static void
- pp_debugfs_print_current_performance_level(void *handle,
- 					       struct seq_file *m)
- {
--	return;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	  hwmgr->hwmgr_func->print_current_perforce_level == NULL)
-+		return;
-+
-+	hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
- }
- 
-+
- const struct amd_powerplay_funcs pp_dpm_funcs = {
- 	.get_temperature = NULL,
- 	.load_firmware = pp_dpm_load_fw,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0050-drm-amd-powerplay-Add-ixSWRST_COMMAND_1-in-bif_5_0_d.patch b/common/recipes-kernel/linux/files/0050-drm-amd-powerplay-Add-ixSWRST_COMMAND_1-in-bif_5_0_d.patch
deleted file mode 100644
index f238ce8f..00000000
--- a/common/recipes-kernel/linux/files/0050-drm-amd-powerplay-Add-ixSWRST_COMMAND_1-in-bif_5_0_d.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e56de1778cc2be9477f0e02e347fd1c9303fd475 Mon Sep 17 00:00:00 2001
-From: yanyang1 <young.yang@amd.com>
-Date: Mon, 17 Aug 2015 14:15:20 +0800
-Subject: [PATCH 0050/1110] drm/amd/powerplay: Add ixSWRST_COMMAND_1 in
- bif_5_0_d.h
-
-Add ixSWRST_COMMAND_1 in bif_5_0_d.h.  Required by
-new powerplay code for tonga and fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: yanyang1 <young.yang@amd.com>
----
- drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
-index 92b6ba0..2933297 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
-@@ -596,6 +596,7 @@
- #define mmSWRST_EP_CONTROL_0                                                    0x14ac
- #define mmCPM_CONTROL                                                           0x14b8
- #define mmGSKT_CONTROL                                                          0x14bf
-+#define ixSWRST_COMMAND_1                                                       0x1400103
- #define ixLM_CONTROL                                                            0x1400120
- #define ixLM_PCIETXMUX0                                                         0x1400121
- #define ixLM_PCIETXMUX1                                                         0x1400122
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0051-drm-amd-powerplay-Move-smu7-.h-from-amdgpu-to-powerp.patch b/common/recipes-kernel/linux/files/0051-drm-amd-powerplay-Move-smu7-.h-from-amdgpu-to-powerp.patch
deleted file mode 100644
index 0093b50c..00000000
--- a/common/recipes-kernel/linux/files/0051-drm-amd-powerplay-Move-smu7-.h-from-amdgpu-to-powerp.patch
+++ /dev/null
@@ -1,2032 +0,0 @@
-From 50e39063e1b2f2e35a42ef1a7e509aca83003f0a Mon Sep 17 00:00:00 2001
-From: yanyang1 <young.yang@amd.com>
-Date: Wed, 19 Aug 2015 12:22:34 +0800
-Subject: [PATCH 0051/1110] drm/amd/powerplay: Move smu7*.h from amdgpu to
- powerplay.
-
-Move smu7.h, smu7_discrete.h and smu7_fusion.h from amdgpu to powerplay.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: yanyang1 <young.yang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/smu7.h                 | 170 -------
- drivers/gpu/drm/amd/amdgpu/smu7_discrete.h        | 514 ----------------------
- drivers/gpu/drm/amd/amdgpu/smu7_fusion.h          | 300 -------------
- drivers/gpu/drm/amd/powerplay/inc/smu7.h          | 170 +++++++
- drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h | 514 ++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h   | 300 +++++++++++++
- 6 files changed, 984 insertions(+), 984 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/smu7.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/smu7_discrete.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/smu7_fusion.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu7.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu7.h b/drivers/gpu/drm/amd/amdgpu/smu7.h
-deleted file mode 100644
-index 75a380a..0000000
---- a/drivers/gpu/drm/amd/amdgpu/smu7.h
-+++ /dev/null
-@@ -1,170 +0,0 @@
--/*
-- * Copyright 2013 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef SMU7_H
--#define SMU7_H
--
--#pragma pack(push, 1)
--
--#define SMU7_CONTEXT_ID_SMC        1
--#define SMU7_CONTEXT_ID_VBIOS      2
--
--
--#define SMU7_CONTEXT_ID_SMC        1
--#define SMU7_CONTEXT_ID_VBIOS      2
--
--#define SMU7_MAX_LEVELS_VDDC            8
--#define SMU7_MAX_LEVELS_VDDCI           4
--#define SMU7_MAX_LEVELS_MVDD            4
--#define SMU7_MAX_LEVELS_VDDNB           8
--
--#define SMU7_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
--#define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
--#define SMU7_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
--#define SMU7_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
--#define SMU7_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
--#define SMU7_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
--#define SMU7_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
--#define SMU7_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
--#define SMU7_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
--
--#define DPM_NO_LIMIT 0
--#define DPM_NO_UP 1
--#define DPM_GO_DOWN 2
--#define DPM_GO_UP 3
--
--#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
--#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
--
--#define GPIO_CLAMP_MODE_VRHOT      1
--#define GPIO_CLAMP_MODE_THERM      2
--#define GPIO_CLAMP_MODE_DC         4
--
--#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
--#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
--#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
--#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
--#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
--#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
--#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
--#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
--#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
--#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
--#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
--#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
--#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
--#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
--#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
--#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
--#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
--#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
--#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
--#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
--
--
--struct SMU7_PIDController
--{
--    uint32_t Ki;
--    int32_t LFWindupUL;
--    int32_t LFWindupLL;
--    uint32_t StatePrecision;
--    uint32_t LfPrecision;
--    uint32_t LfOffset;
--    uint32_t MaxState;
--    uint32_t MaxLfFraction;
--    uint32_t StateShift;
--};
--
--typedef struct SMU7_PIDController SMU7_PIDController;
--
--// -------------------------------------------------------------------------------------------------------------------------
--#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
--
--#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
--#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
--#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
--#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
--#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
--#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
--#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
--#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
--#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
--
--#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
--#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
--#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
--#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
--#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
--#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
--
--struct SMU7_Firmware_Header
--{
--    uint32_t Digest[5];
--    uint32_t Version;
--    uint32_t HeaderSize;
--    uint32_t Flags;
--    uint32_t EntryPoint;
--    uint32_t CodeSize;
--    uint32_t ImageSize;
--
--    uint32_t Rtos;
--    uint32_t SoftRegisters;
--    uint32_t DpmTable;
--    uint32_t FanTable;
--    uint32_t CacConfigTable;
--    uint32_t CacStatusTable;
--
--    uint32_t mcRegisterTable;
--
--    uint32_t mcArbDramTimingTable;
--
--    uint32_t PmFuseTable;
--    uint32_t Globals;
--    uint32_t Reserved[42];
--    uint32_t Signature;
--};
--
--typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
--
--#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
--
--enum  DisplayConfig {
--    PowerDown = 1,
--    DP54x4,
--    DP54x2,
--    DP54x1,
--    DP27x4,
--    DP27x2,
--    DP27x1,
--    HDMI297,
--    HDMI162,
--    LVDS,
--    DP324x4,
--    DP324x2,
--    DP324x1
--};
--
--#pragma pack(pop)
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu7_discrete.h b/drivers/gpu/drm/amd/amdgpu/smu7_discrete.h
-deleted file mode 100644
-index 0b0b404..0000000
---- a/drivers/gpu/drm/amd/amdgpu/smu7_discrete.h
-+++ /dev/null
-@@ -1,514 +0,0 @@
--/*
-- * Copyright 2013 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef SMU7_DISCRETE_H
--#define SMU7_DISCRETE_H
--
--#include "smu7.h"
--
--#pragma pack(push, 1)
--
--#define SMU7_DTE_ITERATIONS 5
--#define SMU7_DTE_SOURCES 3
--#define SMU7_DTE_SINKS 1
--#define SMU7_NUM_CPU_TES 0
--#define SMU7_NUM_GPU_TES 1
--#define SMU7_NUM_NON_TES 2
--
--struct SMU7_SoftRegisters
--{
--    uint32_t        RefClockFrequency;
--    uint32_t        PmTimerP;
--    uint32_t        FeatureEnables;
--    uint32_t        PreVBlankGap;
--    uint32_t        VBlankTimeout;
--    uint32_t        TrainTimeGap;
--
--    uint32_t        MvddSwitchTime;
--    uint32_t        LongestAcpiTrainTime;
--    uint32_t        AcpiDelay;
--    uint32_t        G5TrainTime;
--    uint32_t        DelayMpllPwron;
--    uint32_t        VoltageChangeTimeout;
--    uint32_t        HandshakeDisables;
--
--    uint8_t         DisplayPhy1Config;
--    uint8_t         DisplayPhy2Config;
--    uint8_t         DisplayPhy3Config;
--    uint8_t         DisplayPhy4Config;
--
--    uint8_t         DisplayPhy5Config;
--    uint8_t         DisplayPhy6Config;
--    uint8_t         DisplayPhy7Config;
--    uint8_t         DisplayPhy8Config;
--
--    uint32_t        AverageGraphicsA;
--    uint32_t        AverageMemoryA;
--    uint32_t        AverageGioA;
--
--    uint8_t         SClkDpmEnabledLevels;
--    uint8_t         MClkDpmEnabledLevels;
--    uint8_t         LClkDpmEnabledLevels;
--    uint8_t         PCIeDpmEnabledLevels;
--
--    uint8_t         UVDDpmEnabledLevels;
--    uint8_t         SAMUDpmEnabledLevels;
--    uint8_t         ACPDpmEnabledLevels;
--    uint8_t         VCEDpmEnabledLevels;
--
--    uint32_t        DRAM_LOG_ADDR_H;
--    uint32_t        DRAM_LOG_ADDR_L;
--    uint32_t        DRAM_LOG_PHY_ADDR_H;
--    uint32_t        DRAM_LOG_PHY_ADDR_L;
--    uint32_t        DRAM_LOG_BUFF_SIZE;
--    uint32_t        UlvEnterC;
--    uint32_t        UlvTime;
--    uint32_t        Reserved[3];
--
--};
--
--typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
--
--struct SMU7_Discrete_VoltageLevel
--{
--    uint16_t    Voltage;
--    uint16_t    StdVoltageHiSidd;
--    uint16_t    StdVoltageLoSidd;
--    uint8_t     Smio;
--    uint8_t     padding;
--};
--
--typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
--
--struct SMU7_Discrete_GraphicsLevel
--{
--    uint32_t    Flags;
--    uint32_t    MinVddc;
--    uint32_t    MinVddcPhases;
--
--    uint32_t    SclkFrequency;
--
--    uint8_t     padding1[2];
--    uint16_t    ActivityLevel;
--
--    uint32_t    CgSpllFuncCntl3;
--    uint32_t    CgSpllFuncCntl4;
--    uint32_t    SpllSpreadSpectrum;
--    uint32_t    SpllSpreadSpectrum2;
--    uint32_t    CcPwrDynRm;
--    uint32_t    CcPwrDynRm1;
--    uint8_t     SclkDid;
--    uint8_t     DisplayWatermark;
--    uint8_t     EnabledForActivity;
--    uint8_t     EnabledForThrottle;
--    uint8_t     UpH;
--    uint8_t     DownH;
--    uint8_t     VoltageDownH;
--    uint8_t     PowerThrottle;
--    uint8_t     DeepSleepDivId;
--    uint8_t     padding[3];
--};
--
--typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
--
--struct SMU7_Discrete_ACPILevel
--{
--    uint32_t    Flags;
--    uint32_t    MinVddc;
--    uint32_t    MinVddcPhases;
--    uint32_t    SclkFrequency;
--    uint8_t     SclkDid;
--    uint8_t     DisplayWatermark;
--    uint8_t     DeepSleepDivId;
--    uint8_t     padding;
--    uint32_t    CgSpllFuncCntl;
--    uint32_t    CgSpllFuncCntl2;
--    uint32_t    CgSpllFuncCntl3;
--    uint32_t    CgSpllFuncCntl4;
--    uint32_t    SpllSpreadSpectrum;
--    uint32_t    SpllSpreadSpectrum2;
--    uint32_t    CcPwrDynRm;
--    uint32_t    CcPwrDynRm1;
--};
--
--typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
--
--struct SMU7_Discrete_Ulv
--{
--    uint32_t    CcPwrDynRm;
--    uint32_t    CcPwrDynRm1;
--    uint16_t    VddcOffset;
--    uint8_t     VddcOffsetVid;
--    uint8_t     VddcPhase;
--    uint32_t    Reserved;
--};
--
--typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
--
--struct SMU7_Discrete_MemoryLevel
--{
--    uint32_t    MinVddc;
--    uint32_t    MinVddcPhases;
--    uint32_t    MinVddci;
--    uint32_t    MinMvdd;
--
--    uint32_t    MclkFrequency;
--
--    uint8_t     EdcReadEnable;
--    uint8_t     EdcWriteEnable;
--    uint8_t     RttEnable;
--    uint8_t     StutterEnable;
--
--    uint8_t     StrobeEnable;
--    uint8_t     StrobeRatio;
--    uint8_t     EnabledForThrottle;
--    uint8_t     EnabledForActivity;
--
--    uint8_t     UpH;
--    uint8_t     DownH;
--    uint8_t     VoltageDownH;
--    uint8_t     padding;
--
--    uint16_t    ActivityLevel;
--    uint8_t     DisplayWatermark;
--    uint8_t     padding1;
--
--    uint32_t    MpllFuncCntl;
--    uint32_t    MpllFuncCntl_1;
--    uint32_t    MpllFuncCntl_2;
--    uint32_t    MpllAdFuncCntl;
--    uint32_t    MpllDqFuncCntl;
--    uint32_t    MclkPwrmgtCntl;
--    uint32_t    DllCntl;
--    uint32_t    MpllSs1;
--    uint32_t    MpllSs2;
--};
--
--typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
--
--struct SMU7_Discrete_LinkLevel
--{
--    uint8_t     PcieGenSpeed;
--    uint8_t     PcieLaneCount;
--    uint8_t     EnabledForActivity;
--    uint8_t     Padding;
--    uint32_t    DownT;
--    uint32_t    UpT;
--    uint32_t    Reserved;
--};
--
--typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
--
--
--struct SMU7_Discrete_MCArbDramTimingTableEntry
--{
--    uint32_t McArbDramTiming;
--    uint32_t McArbDramTiming2;
--    uint8_t  McArbBurstTime;
--    uint8_t  padding[3];
--};
--
--typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
--
--struct SMU7_Discrete_MCArbDramTimingTable
--{
--    SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
--};
--
--typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
--
--struct SMU7_Discrete_UvdLevel
--{
--    uint32_t VclkFrequency;
--    uint32_t DclkFrequency;
--    uint16_t MinVddc;
--    uint8_t  MinVddcPhases;
--    uint8_t  VclkDivider;
--    uint8_t  DclkDivider;
--    uint8_t  padding[3];
--};
--
--typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
--
--struct SMU7_Discrete_ExtClkLevel
--{
--    uint32_t Frequency;
--    uint16_t MinVoltage;
--    uint8_t  MinPhases;
--    uint8_t  Divider;
--};
--
--typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
--
--struct SMU7_Discrete_StateInfo
--{
--    uint32_t SclkFrequency;
--    uint32_t MclkFrequency;
--    uint32_t VclkFrequency;
--    uint32_t DclkFrequency;
--    uint32_t SamclkFrequency;
--    uint32_t AclkFrequency;
--    uint32_t EclkFrequency;
--    uint16_t MvddVoltage;
--    uint16_t padding16;
--    uint8_t  DisplayWatermark;
--    uint8_t  McArbIndex;
--    uint8_t  McRegIndex;
--    uint8_t  SeqIndex;
--    uint8_t  SclkDid;
--    int8_t   SclkIndex;
--    int8_t   MclkIndex;
--    uint8_t  PCIeGen;
--
--};
--
--typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
--
--
--struct SMU7_Discrete_DpmTable
--{
--    SMU7_PIDController                  GraphicsPIDController;
--    SMU7_PIDController                  MemoryPIDController;
--    SMU7_PIDController                  LinkPIDController;
--
--    uint32_t                            SystemFlags;
--
--
--    uint32_t                            SmioMaskVddcVid;
--    uint32_t                            SmioMaskVddcPhase;
--    uint32_t                            SmioMaskVddciVid;
--    uint32_t                            SmioMaskMvddVid;
--
--    uint32_t                            VddcLevelCount;
--    uint32_t                            VddciLevelCount;
--    uint32_t                            MvddLevelCount;
--
--    SMU7_Discrete_VoltageLevel          VddcLevel               [SMU7_MAX_LEVELS_VDDC];
--//    SMU7_Discrete_VoltageLevel          VddcStandardReference   [SMU7_MAX_LEVELS_VDDC];
--    SMU7_Discrete_VoltageLevel          VddciLevel              [SMU7_MAX_LEVELS_VDDCI];
--    SMU7_Discrete_VoltageLevel          MvddLevel               [SMU7_MAX_LEVELS_MVDD];
--
--    uint8_t                             GraphicsDpmLevelCount;
--    uint8_t                             MemoryDpmLevelCount;
--    uint8_t                             LinkLevelCount;
--    uint8_t                             UvdLevelCount;
--    uint8_t                             VceLevelCount;
--    uint8_t                             AcpLevelCount;
--    uint8_t                             SamuLevelCount;
--    uint8_t                             MasterDeepSleepControl;
--    uint32_t                            Reserved[5];
--//    uint32_t                            SamuDefaultLevel;
--
--    SMU7_Discrete_GraphicsLevel         GraphicsLevel           [SMU7_MAX_LEVELS_GRAPHICS];
--    SMU7_Discrete_MemoryLevel           MemoryACPILevel;
--    SMU7_Discrete_MemoryLevel           MemoryLevel             [SMU7_MAX_LEVELS_MEMORY];
--    SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
--    SMU7_Discrete_ACPILevel             ACPILevel;
--    SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
--    SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
--    SMU7_Discrete_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
--    SMU7_Discrete_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
--    SMU7_Discrete_Ulv                   Ulv;
--
--    uint32_t                            SclkStepSize;
--    uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
--
--    uint8_t                             UvdBootLevel;
--    uint8_t                             VceBootLevel;
--    uint8_t                             AcpBootLevel;
--    uint8_t                             SamuBootLevel;
--
--    uint8_t                             UVDInterval;
--    uint8_t                             VCEInterval;
--    uint8_t                             ACPInterval;
--    uint8_t                             SAMUInterval;
--
--    uint8_t                             GraphicsBootLevel;
--    uint8_t                             GraphicsVoltageChangeEnable;
--    uint8_t                             GraphicsThermThrottleEnable;
--    uint8_t                             GraphicsInterval;
--
--    uint8_t                             VoltageInterval;
--    uint8_t                             ThermalInterval;
--    uint16_t                            TemperatureLimitHigh;
--
--    uint16_t                            TemperatureLimitLow;
--    uint8_t                             MemoryBootLevel;
--    uint8_t                             MemoryVoltageChangeEnable;
--
--    uint8_t                             MemoryInterval;
--    uint8_t                             MemoryThermThrottleEnable;
--    uint16_t                            VddcVddciDelta;
--
--    uint16_t                            VoltageResponseTime;
--    uint16_t                            PhaseResponseTime;
--
--    uint8_t                             PCIeBootLinkLevel;
--    uint8_t                             PCIeGenInterval;
--    uint8_t                             DTEInterval;
--    uint8_t                             DTEMode;
--
--    uint8_t                             SVI2Enable;
--    uint8_t                             VRHotGpio;
--    uint8_t                             AcDcGpio;
--    uint8_t                             ThermGpio;
--
--    uint16_t                            PPM_PkgPwrLimit;
--    uint16_t                            PPM_TemperatureLimit;
--
--    uint16_t                            DefaultTdp;
--    uint16_t                            TargetTdp;
--
--    uint16_t                            FpsHighT;
--    uint16_t                            FpsLowT;
--
--    uint16_t                            BAPMTI_R  [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
--    uint16_t                            BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
--
--    uint8_t                             DTEAmbientTempBase;
--    uint8_t                             DTETjOffset;
--    uint8_t                             GpuTjMax;
--    uint8_t                             GpuTjHyst;
--
--    uint16_t                            BootVddc;
--    uint16_t                            BootVddci;
--
--    uint16_t                            BootMVdd;
--    uint16_t                            padding;
--
--    uint32_t                            BAPM_TEMP_GRADIENT;
--
--    uint32_t                            LowSclkInterruptT;
--};
--
--typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
--
--#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
--#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
--
--struct SMU7_Discrete_MCRegisterAddress
--{
--    uint16_t s0;
--    uint16_t s1;
--};
--
--typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
--
--struct SMU7_Discrete_MCRegisterSet
--{
--    uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
--};
--
--typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
--
--struct SMU7_Discrete_MCRegisters
--{
--    uint8_t                             last;
--    uint8_t                             reserved[3];
--    SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
--    SMU7_Discrete_MCRegisterSet         data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
--};
--
--typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
--
--struct SMU7_Discrete_FanTable
--{
--	uint16_t FdoMode;
--	int16_t  TempMin;
--	int16_t  TempMed;
--	int16_t  TempMax;
--	int16_t  Slope1;
--	int16_t  Slope2;
--	int16_t  FdoMin;
--	int16_t  HystUp;
--	int16_t  HystDown;
--	int16_t  HystSlope;
--	int16_t  TempRespLim;
--	int16_t  TempCurr;
--	int16_t  SlopeCurr;
--	int16_t  PwmCurr;
--	uint32_t RefreshPeriod;
--	int16_t  FdoMax;
--	uint8_t  TempSrc;
--	int8_t   Padding;
--};
--
--typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
--
--
--struct SMU7_Discrete_PmFuses {
--  // dw0-dw1
--  uint8_t BapmVddCVidHiSidd[8];
--
--  // dw2-dw3
--  uint8_t BapmVddCVidLoSidd[8];
--
--  // dw4-dw5
--  uint8_t VddCVid[8];
--
--  // dw6
--  uint8_t SviLoadLineEn;
--  uint8_t SviLoadLineVddC;
--  uint8_t SviLoadLineTrimVddC;
--  uint8_t SviLoadLineOffsetVddC;
--
--  // dw7
--  uint16_t TDC_VDDC_PkgLimit;
--  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
--  uint8_t TDC_MAWt;
--
--  // dw8
--  uint8_t TdcWaterfallCtl;
--  uint8_t LPMLTemperatureMin;
--  uint8_t LPMLTemperatureMax;
--  uint8_t Reserved;
--
--  // dw9-dw10
--  uint8_t BapmVddCVidHiSidd2[8];
--
--  // dw11-dw12
--  int16_t FuzzyFan_ErrorSetDelta;
--  int16_t FuzzyFan_ErrorRateSetDelta;
--  int16_t FuzzyFan_PwmSetDelta;
--  uint16_t CalcMeasPowerBlend;
--
--  // dw13-dw16
--  uint8_t GnbLPML[16];
--
--  // dw17
--  uint8_t GnbLPMLMaxVid;
--  uint8_t GnbLPMLMinVid;
--  uint8_t Reserved1[2];
--
--  // dw18
--  uint16_t BapmVddCBaseLeakageHiSidd;
--  uint16_t BapmVddCBaseLeakageLoSidd;
--};
--
--typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
--
--
--#pragma pack(pop)
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu7_fusion.h b/drivers/gpu/drm/amd/amdgpu/smu7_fusion.h
-deleted file mode 100644
-index 78ada9f..0000000
---- a/drivers/gpu/drm/amd/amdgpu/smu7_fusion.h
-+++ /dev/null
-@@ -1,300 +0,0 @@
--/*
-- * Copyright 2013 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef SMU7_FUSION_H
--#define SMU7_FUSION_H
--
--#include "smu7.h"
--
--#pragma pack(push, 1)
--
--#define SMU7_DTE_ITERATIONS 5
--#define SMU7_DTE_SOURCES 5
--#define SMU7_DTE_SINKS 3
--#define SMU7_NUM_CPU_TES 2
--#define SMU7_NUM_GPU_TES 1
--#define SMU7_NUM_NON_TES 2
--
--// All 'soft registers' should be uint32_t.
--struct SMU7_SoftRegisters
--{
--    uint32_t        RefClockFrequency;
--    uint32_t        PmTimerP;
--    uint32_t        FeatureEnables;
--    uint32_t        HandshakeDisables;
--
--    uint8_t         DisplayPhy1Config;
--    uint8_t         DisplayPhy2Config;
--    uint8_t         DisplayPhy3Config;
--    uint8_t         DisplayPhy4Config;
--
--    uint8_t         DisplayPhy5Config;
--    uint8_t         DisplayPhy6Config;
--    uint8_t         DisplayPhy7Config;
--    uint8_t         DisplayPhy8Config;
--
--    uint32_t        AverageGraphicsA;
--    uint32_t        AverageMemoryA;
--    uint32_t        AverageGioA;
--
--    uint8_t         SClkDpmEnabledLevels;
--    uint8_t         MClkDpmEnabledLevels;
--    uint8_t         LClkDpmEnabledLevels;
--    uint8_t         PCIeDpmEnabledLevels;
--
--    uint8_t         UVDDpmEnabledLevels;
--    uint8_t         SAMUDpmEnabledLevels;
--    uint8_t         ACPDpmEnabledLevels;
--    uint8_t         VCEDpmEnabledLevels;
--
--    uint32_t        DRAM_LOG_ADDR_H;
--    uint32_t        DRAM_LOG_ADDR_L;
--    uint32_t        DRAM_LOG_PHY_ADDR_H;
--    uint32_t        DRAM_LOG_PHY_ADDR_L;
--    uint32_t        DRAM_LOG_BUFF_SIZE;
--    uint32_t        UlvEnterC;
--    uint32_t        UlvTime;
--    uint32_t        Reserved[3];
--
--};
--
--typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
--
--struct SMU7_Fusion_GraphicsLevel
--{
--    uint32_t    MinVddNb;
--
--    uint32_t    SclkFrequency;
--
--    uint8_t     Vid;
--    uint8_t     VidOffset;
--    uint16_t    AT;
--
--    uint8_t     PowerThrottle;
--    uint8_t     GnbSlow;
--    uint8_t     ForceNbPs1;
--    uint8_t     SclkDid;
--
--    uint8_t     DisplayWatermark;
--    uint8_t     EnabledForActivity;
--    uint8_t     EnabledForThrottle;
--    uint8_t     UpH;
--
--    uint8_t     DownH;
--    uint8_t     VoltageDownH;
--    uint8_t     DeepSleepDivId;
--
--    uint8_t     ClkBypassCntl;
--
--    uint32_t    reserved;
--};
--
--typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
--
--struct SMU7_Fusion_GIOLevel
--{
--    uint8_t     EnabledForActivity;
--    uint8_t     LclkDid;
--    uint8_t     Vid;
--    uint8_t     VoltageDownH;
--
--    uint32_t    MinVddNb;
--
--    uint16_t    ResidencyCounter;
--    uint8_t     UpH;
--    uint8_t     DownH;
--
--    uint32_t    LclkFrequency;
--
--    uint8_t     ActivityLevel;
--    uint8_t     EnabledForThrottle;
--
--    uint8_t     ClkBypassCntl;
--
--    uint8_t     padding;
--};
--
--typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
--
--// UVD VCLK/DCLK state (level) definition.
--struct SMU7_Fusion_UvdLevel
--{
--    uint32_t VclkFrequency;
--    uint32_t DclkFrequency;
--    uint16_t MinVddNb;
--    uint8_t  VclkDivider;
--    uint8_t  DclkDivider;
--
--    uint8_t     VClkBypassCntl;
--    uint8_t     DClkBypassCntl;
--
--    uint8_t     padding[2];
--
--};
--
--typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
--
--// Clocks for other external blocks (VCE, ACP, SAMU).
--struct SMU7_Fusion_ExtClkLevel
--{
--    uint32_t Frequency;
--    uint16_t MinVoltage;
--    uint8_t  Divider;
--    uint8_t  ClkBypassCntl;
--
--    uint32_t Reserved;
--};
--typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
--
--struct SMU7_Fusion_ACPILevel
--{
--    uint32_t    Flags;
--    uint32_t    MinVddNb;
--    uint32_t    SclkFrequency;
--    uint8_t     SclkDid;
--    uint8_t     GnbSlow;
--    uint8_t     ForceNbPs1;
--    uint8_t     DisplayWatermark;
--    uint8_t     DeepSleepDivId;
--    uint8_t     padding[3];
--};
--
--typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
--
--struct SMU7_Fusion_NbDpm
--{
--    uint8_t DpmXNbPsHi;
--    uint8_t DpmXNbPsLo;
--    uint8_t Dpm0PgNbPsHi;
--    uint8_t Dpm0PgNbPsLo;
--    uint8_t EnablePsi1;
--    uint8_t SkipDPM0;
--    uint8_t SkipPG;
--    uint8_t Hysteresis;
--    uint8_t EnableDpmPstatePoll;
--    uint8_t padding[3];
--};
--
--typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
--
--struct SMU7_Fusion_StateInfo
--{
--    uint32_t SclkFrequency;
--    uint32_t LclkFrequency;
--    uint32_t VclkFrequency;
--    uint32_t DclkFrequency;
--    uint32_t SamclkFrequency;
--    uint32_t AclkFrequency;
--    uint32_t EclkFrequency;
--    uint8_t  DisplayWatermark;
--    uint8_t  McArbIndex;
--    int8_t   SclkIndex;
--    int8_t   MclkIndex;
--};
--
--typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
--
--struct SMU7_Fusion_DpmTable
--{
--    uint32_t                            SystemFlags;
--
--    SMU7_PIDController                  GraphicsPIDController;
--    SMU7_PIDController                  GioPIDController;
--
--    uint8_t                            GraphicsDpmLevelCount;
--    uint8_t                            GIOLevelCount;
--    uint8_t                            UvdLevelCount;
--    uint8_t                            VceLevelCount;
--
--    uint8_t                            AcpLevelCount;
--    uint8_t                            SamuLevelCount;
--    uint16_t                           FpsHighT;
--
--    SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
--    SMU7_Fusion_ACPILevel             ACPILevel;
--    SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
--    SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
--    SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
--    SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
--
--    uint8_t                           UvdBootLevel;
--    uint8_t                           VceBootLevel;
--    uint8_t                           AcpBootLevel;
--    uint8_t                           SamuBootLevel;
--    uint8_t                           UVDInterval;
--    uint8_t                           VCEInterval;
--    uint8_t                           ACPInterval;
--    uint8_t                           SAMUInterval;
--
--    uint8_t                           GraphicsBootLevel;
--    uint8_t                           GraphicsInterval;
--    uint8_t                           GraphicsThermThrottleEnable;
--    uint8_t                           GraphicsVoltageChangeEnable;
--
--    uint8_t                           GraphicsClkSlowEnable;
--    uint8_t                           GraphicsClkSlowDivider;
--    uint16_t                          FpsLowT;
--
--    uint32_t                          DisplayCac;
--    uint32_t                          LowSclkInterruptT;
--
--    uint32_t                          DRAM_LOG_ADDR_H;
--    uint32_t                          DRAM_LOG_ADDR_L;
--    uint32_t                          DRAM_LOG_PHY_ADDR_H;
--    uint32_t                          DRAM_LOG_PHY_ADDR_L;
--    uint32_t                          DRAM_LOG_BUFF_SIZE;
--
--};
--
--struct SMU7_Fusion_GIODpmTable
--{
--
--    SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];
--
--    SMU7_PIDController                GioPIDController;
--
--    uint32_t                          GIOLevelCount;
--
--    uint8_t                           Enable;
--    uint8_t                           GIOVoltageChangeEnable;
--    uint8_t                           GIOBootLevel;
--    uint8_t                           padding;
--    uint8_t                           padding1[2];
--    uint8_t                           TargetState;
--    uint8_t                           CurrenttState;
--    uint8_t                           ThrottleOnHtc;
--    uint8_t                           ThermThrottleStatus;
--    uint8_t                           ThermThrottleTempSelect;
--    uint8_t                           ThermThrottleEnable;
--    uint16_t                          TemperatureLimitHigh;
--    uint16_t                          TemperatureLimitLow;
--
--};
--
--typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
--typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
--
--#pragma pack(pop)
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7.h b/drivers/gpu/drm/amd/powerplay/inc/smu7.h
-new file mode 100644
-index 0000000..75a380a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7.h
-@@ -0,0 +1,170 @@
-+/*
-+ * Copyright 2013 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU7_H
-+#define SMU7_H
-+
-+#pragma pack(push, 1)
-+
-+#define SMU7_CONTEXT_ID_SMC        1
-+#define SMU7_CONTEXT_ID_VBIOS      2
-+
-+
-+#define SMU7_CONTEXT_ID_SMC        1
-+#define SMU7_CONTEXT_ID_VBIOS      2
-+
-+#define SMU7_MAX_LEVELS_VDDC            8
-+#define SMU7_MAX_LEVELS_VDDCI           4
-+#define SMU7_MAX_LEVELS_MVDD            4
-+#define SMU7_MAX_LEVELS_VDDNB           8
-+
-+#define SMU7_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
-+#define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
-+#define SMU7_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
-+#define SMU7_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
-+#define SMU7_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
-+#define SMU7_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
-+#define SMU7_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
-+#define SMU7_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
-+#define SMU7_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
-+
-+#define DPM_NO_LIMIT 0
-+#define DPM_NO_UP 1
-+#define DPM_GO_DOWN 2
-+#define DPM_GO_UP 3
-+
-+#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
-+#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
-+
-+#define GPIO_CLAMP_MODE_VRHOT      1
-+#define GPIO_CLAMP_MODE_THERM      2
-+#define GPIO_CLAMP_MODE_DC         4
-+
-+#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
-+#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
-+#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
-+#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
-+#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
-+#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
-+#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
-+#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
-+#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
-+#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
-+#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
-+
-+
-+struct SMU7_PIDController
-+{
-+    uint32_t Ki;
-+    int32_t LFWindupUL;
-+    int32_t LFWindupLL;
-+    uint32_t StatePrecision;
-+    uint32_t LfPrecision;
-+    uint32_t LfOffset;
-+    uint32_t MaxState;
-+    uint32_t MaxLfFraction;
-+    uint32_t StateShift;
-+};
-+
-+typedef struct SMU7_PIDController SMU7_PIDController;
-+
-+// -------------------------------------------------------------------------------------------------------------------------
-+#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
-+
-+#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
-+#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
-+#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
-+#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
-+#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
-+#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
-+#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
-+#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
-+#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
-+
-+#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
-+#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
-+#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
-+#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
-+#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
-+#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
-+
-+struct SMU7_Firmware_Header
-+{
-+    uint32_t Digest[5];
-+    uint32_t Version;
-+    uint32_t HeaderSize;
-+    uint32_t Flags;
-+    uint32_t EntryPoint;
-+    uint32_t CodeSize;
-+    uint32_t ImageSize;
-+
-+    uint32_t Rtos;
-+    uint32_t SoftRegisters;
-+    uint32_t DpmTable;
-+    uint32_t FanTable;
-+    uint32_t CacConfigTable;
-+    uint32_t CacStatusTable;
-+
-+    uint32_t mcRegisterTable;
-+
-+    uint32_t mcArbDramTimingTable;
-+
-+    uint32_t PmFuseTable;
-+    uint32_t Globals;
-+    uint32_t Reserved[42];
-+    uint32_t Signature;
-+};
-+
-+typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
-+
-+#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
-+
-+enum  DisplayConfig {
-+    PowerDown = 1,
-+    DP54x4,
-+    DP54x2,
-+    DP54x1,
-+    DP27x4,
-+    DP27x2,
-+    DP27x1,
-+    HDMI297,
-+    HDMI162,
-+    LVDS,
-+    DP324x4,
-+    DP324x2,
-+    DP324x1
-+};
-+
-+#pragma pack(pop)
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h
-new file mode 100644
-index 0000000..0b0b404
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h
-@@ -0,0 +1,514 @@
-+/*
-+ * Copyright 2013 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU7_DISCRETE_H
-+#define SMU7_DISCRETE_H
-+
-+#include "smu7.h"
-+
-+#pragma pack(push, 1)
-+
-+#define SMU7_DTE_ITERATIONS 5
-+#define SMU7_DTE_SOURCES 3
-+#define SMU7_DTE_SINKS 1
-+#define SMU7_NUM_CPU_TES 0
-+#define SMU7_NUM_GPU_TES 1
-+#define SMU7_NUM_NON_TES 2
-+
-+struct SMU7_SoftRegisters
-+{
-+    uint32_t        RefClockFrequency;
-+    uint32_t        PmTimerP;
-+    uint32_t        FeatureEnables;
-+    uint32_t        PreVBlankGap;
-+    uint32_t        VBlankTimeout;
-+    uint32_t        TrainTimeGap;
-+
-+    uint32_t        MvddSwitchTime;
-+    uint32_t        LongestAcpiTrainTime;
-+    uint32_t        AcpiDelay;
-+    uint32_t        G5TrainTime;
-+    uint32_t        DelayMpllPwron;
-+    uint32_t        VoltageChangeTimeout;
-+    uint32_t        HandshakeDisables;
-+
-+    uint8_t         DisplayPhy1Config;
-+    uint8_t         DisplayPhy2Config;
-+    uint8_t         DisplayPhy3Config;
-+    uint8_t         DisplayPhy4Config;
-+
-+    uint8_t         DisplayPhy5Config;
-+    uint8_t         DisplayPhy6Config;
-+    uint8_t         DisplayPhy7Config;
-+    uint8_t         DisplayPhy8Config;
-+
-+    uint32_t        AverageGraphicsA;
-+    uint32_t        AverageMemoryA;
-+    uint32_t        AverageGioA;
-+
-+    uint8_t         SClkDpmEnabledLevels;
-+    uint8_t         MClkDpmEnabledLevels;
-+    uint8_t         LClkDpmEnabledLevels;
-+    uint8_t         PCIeDpmEnabledLevels;
-+
-+    uint8_t         UVDDpmEnabledLevels;
-+    uint8_t         SAMUDpmEnabledLevels;
-+    uint8_t         ACPDpmEnabledLevels;
-+    uint8_t         VCEDpmEnabledLevels;
-+
-+    uint32_t        DRAM_LOG_ADDR_H;
-+    uint32_t        DRAM_LOG_ADDR_L;
-+    uint32_t        DRAM_LOG_PHY_ADDR_H;
-+    uint32_t        DRAM_LOG_PHY_ADDR_L;
-+    uint32_t        DRAM_LOG_BUFF_SIZE;
-+    uint32_t        UlvEnterC;
-+    uint32_t        UlvTime;
-+    uint32_t        Reserved[3];
-+
-+};
-+
-+typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
-+
-+struct SMU7_Discrete_VoltageLevel
-+{
-+    uint16_t    Voltage;
-+    uint16_t    StdVoltageHiSidd;
-+    uint16_t    StdVoltageLoSidd;
-+    uint8_t     Smio;
-+    uint8_t     padding;
-+};
-+
-+typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
-+
-+struct SMU7_Discrete_GraphicsLevel
-+{
-+    uint32_t    Flags;
-+    uint32_t    MinVddc;
-+    uint32_t    MinVddcPhases;
-+
-+    uint32_t    SclkFrequency;
-+
-+    uint8_t     padding1[2];
-+    uint16_t    ActivityLevel;
-+
-+    uint32_t    CgSpllFuncCntl3;
-+    uint32_t    CgSpllFuncCntl4;
-+    uint32_t    SpllSpreadSpectrum;
-+    uint32_t    SpllSpreadSpectrum2;
-+    uint32_t    CcPwrDynRm;
-+    uint32_t    CcPwrDynRm1;
-+    uint8_t     SclkDid;
-+    uint8_t     DisplayWatermark;
-+    uint8_t     EnabledForActivity;
-+    uint8_t     EnabledForThrottle;
-+    uint8_t     UpH;
-+    uint8_t     DownH;
-+    uint8_t     VoltageDownH;
-+    uint8_t     PowerThrottle;
-+    uint8_t     DeepSleepDivId;
-+    uint8_t     padding[3];
-+};
-+
-+typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
-+
-+struct SMU7_Discrete_ACPILevel
-+{
-+    uint32_t    Flags;
-+    uint32_t    MinVddc;
-+    uint32_t    MinVddcPhases;
-+    uint32_t    SclkFrequency;
-+    uint8_t     SclkDid;
-+    uint8_t     DisplayWatermark;
-+    uint8_t     DeepSleepDivId;
-+    uint8_t     padding;
-+    uint32_t    CgSpllFuncCntl;
-+    uint32_t    CgSpllFuncCntl2;
-+    uint32_t    CgSpllFuncCntl3;
-+    uint32_t    CgSpllFuncCntl4;
-+    uint32_t    SpllSpreadSpectrum;
-+    uint32_t    SpllSpreadSpectrum2;
-+    uint32_t    CcPwrDynRm;
-+    uint32_t    CcPwrDynRm1;
-+};
-+
-+typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
-+
-+struct SMU7_Discrete_Ulv
-+{
-+    uint32_t    CcPwrDynRm;
-+    uint32_t    CcPwrDynRm1;
-+    uint16_t    VddcOffset;
-+    uint8_t     VddcOffsetVid;
-+    uint8_t     VddcPhase;
-+    uint32_t    Reserved;
-+};
-+
-+typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
-+
-+struct SMU7_Discrete_MemoryLevel
-+{
-+    uint32_t    MinVddc;
-+    uint32_t    MinVddcPhases;
-+    uint32_t    MinVddci;
-+    uint32_t    MinMvdd;
-+
-+    uint32_t    MclkFrequency;
-+
-+    uint8_t     EdcReadEnable;
-+    uint8_t     EdcWriteEnable;
-+    uint8_t     RttEnable;
-+    uint8_t     StutterEnable;
-+
-+    uint8_t     StrobeEnable;
-+    uint8_t     StrobeRatio;
-+    uint8_t     EnabledForThrottle;
-+    uint8_t     EnabledForActivity;
-+
-+    uint8_t     UpH;
-+    uint8_t     DownH;
-+    uint8_t     VoltageDownH;
-+    uint8_t     padding;
-+
-+    uint16_t    ActivityLevel;
-+    uint8_t     DisplayWatermark;
-+    uint8_t     padding1;
-+
-+    uint32_t    MpllFuncCntl;
-+    uint32_t    MpllFuncCntl_1;
-+    uint32_t    MpllFuncCntl_2;
-+    uint32_t    MpllAdFuncCntl;
-+    uint32_t    MpllDqFuncCntl;
-+    uint32_t    MclkPwrmgtCntl;
-+    uint32_t    DllCntl;
-+    uint32_t    MpllSs1;
-+    uint32_t    MpllSs2;
-+};
-+
-+typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
-+
-+struct SMU7_Discrete_LinkLevel
-+{
-+    uint8_t     PcieGenSpeed;
-+    uint8_t     PcieLaneCount;
-+    uint8_t     EnabledForActivity;
-+    uint8_t     Padding;
-+    uint32_t    DownT;
-+    uint32_t    UpT;
-+    uint32_t    Reserved;
-+};
-+
-+typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
-+
-+
-+struct SMU7_Discrete_MCArbDramTimingTableEntry
-+{
-+    uint32_t McArbDramTiming;
-+    uint32_t McArbDramTiming2;
-+    uint8_t  McArbBurstTime;
-+    uint8_t  padding[3];
-+};
-+
-+typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
-+
-+struct SMU7_Discrete_MCArbDramTimingTable
-+{
-+    SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
-+};
-+
-+typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
-+
-+struct SMU7_Discrete_UvdLevel
-+{
-+    uint32_t VclkFrequency;
-+    uint32_t DclkFrequency;
-+    uint16_t MinVddc;
-+    uint8_t  MinVddcPhases;
-+    uint8_t  VclkDivider;
-+    uint8_t  DclkDivider;
-+    uint8_t  padding[3];
-+};
-+
-+typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
-+
-+struct SMU7_Discrete_ExtClkLevel
-+{
-+    uint32_t Frequency;
-+    uint16_t MinVoltage;
-+    uint8_t  MinPhases;
-+    uint8_t  Divider;
-+};
-+
-+typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
-+
-+struct SMU7_Discrete_StateInfo
-+{
-+    uint32_t SclkFrequency;
-+    uint32_t MclkFrequency;
-+    uint32_t VclkFrequency;
-+    uint32_t DclkFrequency;
-+    uint32_t SamclkFrequency;
-+    uint32_t AclkFrequency;
-+    uint32_t EclkFrequency;
-+    uint16_t MvddVoltage;
-+    uint16_t padding16;
-+    uint8_t  DisplayWatermark;
-+    uint8_t  McArbIndex;
-+    uint8_t  McRegIndex;
-+    uint8_t  SeqIndex;
-+    uint8_t  SclkDid;
-+    int8_t   SclkIndex;
-+    int8_t   MclkIndex;
-+    uint8_t  PCIeGen;
-+
-+};
-+
-+typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
-+
-+
-+struct SMU7_Discrete_DpmTable
-+{
-+    SMU7_PIDController                  GraphicsPIDController;
-+    SMU7_PIDController                  MemoryPIDController;
-+    SMU7_PIDController                  LinkPIDController;
-+
-+    uint32_t                            SystemFlags;
-+
-+
-+    uint32_t                            SmioMaskVddcVid;
-+    uint32_t                            SmioMaskVddcPhase;
-+    uint32_t                            SmioMaskVddciVid;
-+    uint32_t                            SmioMaskMvddVid;
-+
-+    uint32_t                            VddcLevelCount;
-+    uint32_t                            VddciLevelCount;
-+    uint32_t                            MvddLevelCount;
-+
-+    SMU7_Discrete_VoltageLevel          VddcLevel               [SMU7_MAX_LEVELS_VDDC];
-+//    SMU7_Discrete_VoltageLevel          VddcStandardReference   [SMU7_MAX_LEVELS_VDDC];
-+    SMU7_Discrete_VoltageLevel          VddciLevel              [SMU7_MAX_LEVELS_VDDCI];
-+    SMU7_Discrete_VoltageLevel          MvddLevel               [SMU7_MAX_LEVELS_MVDD];
-+
-+    uint8_t                             GraphicsDpmLevelCount;
-+    uint8_t                             MemoryDpmLevelCount;
-+    uint8_t                             LinkLevelCount;
-+    uint8_t                             UvdLevelCount;
-+    uint8_t                             VceLevelCount;
-+    uint8_t                             AcpLevelCount;
-+    uint8_t                             SamuLevelCount;
-+    uint8_t                             MasterDeepSleepControl;
-+    uint32_t                            Reserved[5];
-+//    uint32_t                            SamuDefaultLevel;
-+
-+    SMU7_Discrete_GraphicsLevel         GraphicsLevel           [SMU7_MAX_LEVELS_GRAPHICS];
-+    SMU7_Discrete_MemoryLevel           MemoryACPILevel;
-+    SMU7_Discrete_MemoryLevel           MemoryLevel             [SMU7_MAX_LEVELS_MEMORY];
-+    SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
-+    SMU7_Discrete_ACPILevel             ACPILevel;
-+    SMU7_Discrete_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
-+    SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
-+    SMU7_Discrete_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
-+    SMU7_Discrete_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
-+    SMU7_Discrete_Ulv                   Ulv;
-+
-+    uint32_t                            SclkStepSize;
-+    uint32_t                            Smio                    [SMU7_MAX_ENTRIES_SMIO];
-+
-+    uint8_t                             UvdBootLevel;
-+    uint8_t                             VceBootLevel;
-+    uint8_t                             AcpBootLevel;
-+    uint8_t                             SamuBootLevel;
-+
-+    uint8_t                             UVDInterval;
-+    uint8_t                             VCEInterval;
-+    uint8_t                             ACPInterval;
-+    uint8_t                             SAMUInterval;
-+
-+    uint8_t                             GraphicsBootLevel;
-+    uint8_t                             GraphicsVoltageChangeEnable;
-+    uint8_t                             GraphicsThermThrottleEnable;
-+    uint8_t                             GraphicsInterval;
-+
-+    uint8_t                             VoltageInterval;
-+    uint8_t                             ThermalInterval;
-+    uint16_t                            TemperatureLimitHigh;
-+
-+    uint16_t                            TemperatureLimitLow;
-+    uint8_t                             MemoryBootLevel;
-+    uint8_t                             MemoryVoltageChangeEnable;
-+
-+    uint8_t                             MemoryInterval;
-+    uint8_t                             MemoryThermThrottleEnable;
-+    uint16_t                            VddcVddciDelta;
-+
-+    uint16_t                            VoltageResponseTime;
-+    uint16_t                            PhaseResponseTime;
-+
-+    uint8_t                             PCIeBootLinkLevel;
-+    uint8_t                             PCIeGenInterval;
-+    uint8_t                             DTEInterval;
-+    uint8_t                             DTEMode;
-+
-+    uint8_t                             SVI2Enable;
-+    uint8_t                             VRHotGpio;
-+    uint8_t                             AcDcGpio;
-+    uint8_t                             ThermGpio;
-+
-+    uint16_t                            PPM_PkgPwrLimit;
-+    uint16_t                            PPM_TemperatureLimit;
-+
-+    uint16_t                            DefaultTdp;
-+    uint16_t                            TargetTdp;
-+
-+    uint16_t                            FpsHighT;
-+    uint16_t                            FpsLowT;
-+
-+    uint16_t                            BAPMTI_R  [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
-+    uint16_t                            BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
-+
-+    uint8_t                             DTEAmbientTempBase;
-+    uint8_t                             DTETjOffset;
-+    uint8_t                             GpuTjMax;
-+    uint8_t                             GpuTjHyst;
-+
-+    uint16_t                            BootVddc;
-+    uint16_t                            BootVddci;
-+
-+    uint16_t                            BootMVdd;
-+    uint16_t                            padding;
-+
-+    uint32_t                            BAPM_TEMP_GRADIENT;
-+
-+    uint32_t                            LowSclkInterruptT;
-+};
-+
-+typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
-+
-+#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
-+#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
-+
-+struct SMU7_Discrete_MCRegisterAddress
-+{
-+    uint16_t s0;
-+    uint16_t s1;
-+};
-+
-+typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
-+
-+struct SMU7_Discrete_MCRegisterSet
-+{
-+    uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+};
-+
-+typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
-+
-+struct SMU7_Discrete_MCRegisters
-+{
-+    uint8_t                             last;
-+    uint8_t                             reserved[3];
-+    SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+    SMU7_Discrete_MCRegisterSet         data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
-+};
-+
-+typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
-+
-+struct SMU7_Discrete_FanTable
-+{
-+	uint16_t FdoMode;
-+	int16_t  TempMin;
-+	int16_t  TempMed;
-+	int16_t  TempMax;
-+	int16_t  Slope1;
-+	int16_t  Slope2;
-+	int16_t  FdoMin;
-+	int16_t  HystUp;
-+	int16_t  HystDown;
-+	int16_t  HystSlope;
-+	int16_t  TempRespLim;
-+	int16_t  TempCurr;
-+	int16_t  SlopeCurr;
-+	int16_t  PwmCurr;
-+	uint32_t RefreshPeriod;
-+	int16_t  FdoMax;
-+	uint8_t  TempSrc;
-+	int8_t   Padding;
-+};
-+
-+typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
-+
-+
-+struct SMU7_Discrete_PmFuses {
-+  // dw0-dw1
-+  uint8_t BapmVddCVidHiSidd[8];
-+
-+  // dw2-dw3
-+  uint8_t BapmVddCVidLoSidd[8];
-+
-+  // dw4-dw5
-+  uint8_t VddCVid[8];
-+
-+  // dw6
-+  uint8_t SviLoadLineEn;
-+  uint8_t SviLoadLineVddC;
-+  uint8_t SviLoadLineTrimVddC;
-+  uint8_t SviLoadLineOffsetVddC;
-+
-+  // dw7
-+  uint16_t TDC_VDDC_PkgLimit;
-+  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
-+  uint8_t TDC_MAWt;
-+
-+  // dw8
-+  uint8_t TdcWaterfallCtl;
-+  uint8_t LPMLTemperatureMin;
-+  uint8_t LPMLTemperatureMax;
-+  uint8_t Reserved;
-+
-+  // dw9-dw10
-+  uint8_t BapmVddCVidHiSidd2[8];
-+
-+  // dw11-dw12
-+  int16_t FuzzyFan_ErrorSetDelta;
-+  int16_t FuzzyFan_ErrorRateSetDelta;
-+  int16_t FuzzyFan_PwmSetDelta;
-+  uint16_t CalcMeasPowerBlend;
-+
-+  // dw13-dw16
-+  uint8_t GnbLPML[16];
-+
-+  // dw17
-+  uint8_t GnbLPMLMaxVid;
-+  uint8_t GnbLPMLMinVid;
-+  uint8_t Reserved1[2];
-+
-+  // dw18
-+  uint16_t BapmVddCBaseLeakageHiSidd;
-+  uint16_t BapmVddCBaseLeakageLoSidd;
-+};
-+
-+typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
-+
-+
-+#pragma pack(pop)
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h b/drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h
-new file mode 100644
-index 0000000..78ada9f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h
-@@ -0,0 +1,300 @@
-+/*
-+ * Copyright 2013 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU7_FUSION_H
-+#define SMU7_FUSION_H
-+
-+#include "smu7.h"
-+
-+#pragma pack(push, 1)
-+
-+#define SMU7_DTE_ITERATIONS 5
-+#define SMU7_DTE_SOURCES 5
-+#define SMU7_DTE_SINKS 3
-+#define SMU7_NUM_CPU_TES 2
-+#define SMU7_NUM_GPU_TES 1
-+#define SMU7_NUM_NON_TES 2
-+
-+// All 'soft registers' should be uint32_t.
-+struct SMU7_SoftRegisters
-+{
-+    uint32_t        RefClockFrequency;
-+    uint32_t        PmTimerP;
-+    uint32_t        FeatureEnables;
-+    uint32_t        HandshakeDisables;
-+
-+    uint8_t         DisplayPhy1Config;
-+    uint8_t         DisplayPhy2Config;
-+    uint8_t         DisplayPhy3Config;
-+    uint8_t         DisplayPhy4Config;
-+
-+    uint8_t         DisplayPhy5Config;
-+    uint8_t         DisplayPhy6Config;
-+    uint8_t         DisplayPhy7Config;
-+    uint8_t         DisplayPhy8Config;
-+
-+    uint32_t        AverageGraphicsA;
-+    uint32_t        AverageMemoryA;
-+    uint32_t        AverageGioA;
-+
-+    uint8_t         SClkDpmEnabledLevels;
-+    uint8_t         MClkDpmEnabledLevels;
-+    uint8_t         LClkDpmEnabledLevels;
-+    uint8_t         PCIeDpmEnabledLevels;
-+
-+    uint8_t         UVDDpmEnabledLevels;
-+    uint8_t         SAMUDpmEnabledLevels;
-+    uint8_t         ACPDpmEnabledLevels;
-+    uint8_t         VCEDpmEnabledLevels;
-+
-+    uint32_t        DRAM_LOG_ADDR_H;
-+    uint32_t        DRAM_LOG_ADDR_L;
-+    uint32_t        DRAM_LOG_PHY_ADDR_H;
-+    uint32_t        DRAM_LOG_PHY_ADDR_L;
-+    uint32_t        DRAM_LOG_BUFF_SIZE;
-+    uint32_t        UlvEnterC;
-+    uint32_t        UlvTime;
-+    uint32_t        Reserved[3];
-+
-+};
-+
-+typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
-+
-+struct SMU7_Fusion_GraphicsLevel
-+{
-+    uint32_t    MinVddNb;
-+
-+    uint32_t    SclkFrequency;
-+
-+    uint8_t     Vid;
-+    uint8_t     VidOffset;
-+    uint16_t    AT;
-+
-+    uint8_t     PowerThrottle;
-+    uint8_t     GnbSlow;
-+    uint8_t     ForceNbPs1;
-+    uint8_t     SclkDid;
-+
-+    uint8_t     DisplayWatermark;
-+    uint8_t     EnabledForActivity;
-+    uint8_t     EnabledForThrottle;
-+    uint8_t     UpH;
-+
-+    uint8_t     DownH;
-+    uint8_t     VoltageDownH;
-+    uint8_t     DeepSleepDivId;
-+
-+    uint8_t     ClkBypassCntl;
-+
-+    uint32_t    reserved;
-+};
-+
-+typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
-+
-+struct SMU7_Fusion_GIOLevel
-+{
-+    uint8_t     EnabledForActivity;
-+    uint8_t     LclkDid;
-+    uint8_t     Vid;
-+    uint8_t     VoltageDownH;
-+
-+    uint32_t    MinVddNb;
-+
-+    uint16_t    ResidencyCounter;
-+    uint8_t     UpH;
-+    uint8_t     DownH;
-+
-+    uint32_t    LclkFrequency;
-+
-+    uint8_t     ActivityLevel;
-+    uint8_t     EnabledForThrottle;
-+
-+    uint8_t     ClkBypassCntl;
-+
-+    uint8_t     padding;
-+};
-+
-+typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
-+
-+// UVD VCLK/DCLK state (level) definition.
-+struct SMU7_Fusion_UvdLevel
-+{
-+    uint32_t VclkFrequency;
-+    uint32_t DclkFrequency;
-+    uint16_t MinVddNb;
-+    uint8_t  VclkDivider;
-+    uint8_t  DclkDivider;
-+
-+    uint8_t     VClkBypassCntl;
-+    uint8_t     DClkBypassCntl;
-+
-+    uint8_t     padding[2];
-+
-+};
-+
-+typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
-+
-+// Clocks for other external blocks (VCE, ACP, SAMU).
-+struct SMU7_Fusion_ExtClkLevel
-+{
-+    uint32_t Frequency;
-+    uint16_t MinVoltage;
-+    uint8_t  Divider;
-+    uint8_t  ClkBypassCntl;
-+
-+    uint32_t Reserved;
-+};
-+typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
-+
-+struct SMU7_Fusion_ACPILevel
-+{
-+    uint32_t    Flags;
-+    uint32_t    MinVddNb;
-+    uint32_t    SclkFrequency;
-+    uint8_t     SclkDid;
-+    uint8_t     GnbSlow;
-+    uint8_t     ForceNbPs1;
-+    uint8_t     DisplayWatermark;
-+    uint8_t     DeepSleepDivId;
-+    uint8_t     padding[3];
-+};
-+
-+typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
-+
-+struct SMU7_Fusion_NbDpm
-+{
-+    uint8_t DpmXNbPsHi;
-+    uint8_t DpmXNbPsLo;
-+    uint8_t Dpm0PgNbPsHi;
-+    uint8_t Dpm0PgNbPsLo;
-+    uint8_t EnablePsi1;
-+    uint8_t SkipDPM0;
-+    uint8_t SkipPG;
-+    uint8_t Hysteresis;
-+    uint8_t EnableDpmPstatePoll;
-+    uint8_t padding[3];
-+};
-+
-+typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
-+
-+struct SMU7_Fusion_StateInfo
-+{
-+    uint32_t SclkFrequency;
-+    uint32_t LclkFrequency;
-+    uint32_t VclkFrequency;
-+    uint32_t DclkFrequency;
-+    uint32_t SamclkFrequency;
-+    uint32_t AclkFrequency;
-+    uint32_t EclkFrequency;
-+    uint8_t  DisplayWatermark;
-+    uint8_t  McArbIndex;
-+    int8_t   SclkIndex;
-+    int8_t   MclkIndex;
-+};
-+
-+typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
-+
-+struct SMU7_Fusion_DpmTable
-+{
-+    uint32_t                            SystemFlags;
-+
-+    SMU7_PIDController                  GraphicsPIDController;
-+    SMU7_PIDController                  GioPIDController;
-+
-+    uint8_t                            GraphicsDpmLevelCount;
-+    uint8_t                            GIOLevelCount;
-+    uint8_t                            UvdLevelCount;
-+    uint8_t                            VceLevelCount;
-+
-+    uint8_t                            AcpLevelCount;
-+    uint8_t                            SamuLevelCount;
-+    uint16_t                           FpsHighT;
-+
-+    SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
-+    SMU7_Fusion_ACPILevel             ACPILevel;
-+    SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
-+    SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
-+    SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
-+    SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
-+
-+    uint8_t                           UvdBootLevel;
-+    uint8_t                           VceBootLevel;
-+    uint8_t                           AcpBootLevel;
-+    uint8_t                           SamuBootLevel;
-+    uint8_t                           UVDInterval;
-+    uint8_t                           VCEInterval;
-+    uint8_t                           ACPInterval;
-+    uint8_t                           SAMUInterval;
-+
-+    uint8_t                           GraphicsBootLevel;
-+    uint8_t                           GraphicsInterval;
-+    uint8_t                           GraphicsThermThrottleEnable;
-+    uint8_t                           GraphicsVoltageChangeEnable;
-+
-+    uint8_t                           GraphicsClkSlowEnable;
-+    uint8_t                           GraphicsClkSlowDivider;
-+    uint16_t                          FpsLowT;
-+
-+    uint32_t                          DisplayCac;
-+    uint32_t                          LowSclkInterruptT;
-+
-+    uint32_t                          DRAM_LOG_ADDR_H;
-+    uint32_t                          DRAM_LOG_ADDR_L;
-+    uint32_t                          DRAM_LOG_PHY_ADDR_H;
-+    uint32_t                          DRAM_LOG_PHY_ADDR_L;
-+    uint32_t                          DRAM_LOG_BUFF_SIZE;
-+
-+};
-+
-+struct SMU7_Fusion_GIODpmTable
-+{
-+
-+    SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];
-+
-+    SMU7_PIDController                GioPIDController;
-+
-+    uint32_t                          GIOLevelCount;
-+
-+    uint8_t                           Enable;
-+    uint8_t                           GIOVoltageChangeEnable;
-+    uint8_t                           GIOBootLevel;
-+    uint8_t                           padding;
-+    uint8_t                           padding1[2];
-+    uint8_t                           TargetState;
-+    uint8_t                           CurrenttState;
-+    uint8_t                           ThrottleOnHtc;
-+    uint8_t                           ThermThrottleStatus;
-+    uint8_t                           ThermThrottleTempSelect;
-+    uint8_t                           ThermThrottleEnable;
-+    uint16_t                          TemperatureLimitHigh;
-+    uint16_t                          TemperatureLimitLow;
-+
-+};
-+
-+typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
-+typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
-+
-+#pragma pack(pop)
-+
-+#endif
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0052-drm-amd-powerplay-add-header-file-for-tonga-smu-and-.patch b/common/recipes-kernel/linux/files/0052-drm-amd-powerplay-add-header-file-for-tonga-smu-and-.patch
deleted file mode 100644
index f7783242..00000000
--- a/common/recipes-kernel/linux/files/0052-drm-amd-powerplay-add-header-file-for-tonga-smu-and-.patch
+++ /dev/null
@@ -1,2090 +0,0 @@
-From 7832a47e2c0cf2529e28f6e3117f19fca35b9e6f Mon Sep 17 00:00:00 2001
-From: yanyang1 <young.yang@amd.com>
-Date: Mon, 17 Aug 2015 14:15:20 +0800
-Subject: [PATCH 0052/1110] drm/amd/powerplay: add header file for tonga smu
- and dpm
-
-These headers provide the SMU interface used by the driver.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: yanyang1 <young.yang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h           | 198 ------
- drivers/gpu/drm/amd/powerplay/inc/smu72.h          | 664 ++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h | 760 +++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h    | 420 ++++++++++++
- 4 files changed, 1844 insertions(+), 198 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu72.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
-deleted file mode 100644
-index 811781f..0000000
---- a/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
-+++ /dev/null
-@@ -1,198 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef TONGA_PP_SMC_H
--#define TONGA_PP_SMC_H
--
--#pragma pack(push, 1)
--
--#define PPSMC_SWSTATE_FLAG_DC                           0x01
--#define PPSMC_SWSTATE_FLAG_UVD                          0x02
--#define PPSMC_SWSTATE_FLAG_VCE                          0x04
--#define PPSMC_SWSTATE_FLAG_PCIE_X1                      0x08
--
--#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
--#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
--#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff 
--
--#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01 
--#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02 
--#define PPSMC_SYSTEMFLAG_GDDR5                          0x04 
--
--#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08 
--
--#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10 
--#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20 
--#define PPSMC_SYSTEMFLAG_12CHANNEL                      0x40
--
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
--#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
--
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
--
--#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH      0x10
--#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17               0x20
--#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17                  0x40
--
--#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01 
--#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02 
--#define PPSMC_DPM2FLAGS_OCP                             0x04 
--
--#define PPSMC_DISPLAY_WATERMARK_LOW                     0
--#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
--
--#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    		0x01
--#define PPSMC_STATEFLAG_POWERBOOST         		0x02
--#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 		0x04
--#define PPSMC_STATEFLAG_POWERSHIFT         		0x08
--#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   		0x10
--#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 		0x20
--#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   		0x40
--
--#define FDO_MODE_HARDWARE 0
--#define FDO_MODE_PIECE_WISE_LINEAR 1
--
--enum FAN_CONTROL {
--	FAN_CONTROL_FUZZY,
--	FAN_CONTROL_TABLE
--};
--
--#define PPSMC_Result_OK             			((uint16_t)0x01)
--#define PPSMC_Result_NoMore         			((uint16_t)0x02)
--#define PPSMC_Result_NotNow         			((uint16_t)0x03)
--#define PPSMC_Result_Failed         			((uint16_t)0xFF) 
--#define PPSMC_Result_UnknownCmd     			((uint16_t)0xFE) 
--#define PPSMC_Result_UnknownVT      			((uint16_t)0xFD) 
--
--typedef uint16_t PPSMC_Result;
--
--#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
--
--#define PPSMC_MSG_Halt                      		((uint16_t)0x10)
--#define PPSMC_MSG_Resume                    		((uint16_t)0x11)
--#define PPSMC_MSG_EnableDPMLevel            		((uint16_t)0x12)
--#define PPSMC_MSG_ZeroLevelsDisabled        		((uint16_t)0x13)
--#define PPSMC_MSG_OneLevelsDisabled         		((uint16_t)0x14)
--#define PPSMC_MSG_TwoLevelsDisabled         		((uint16_t)0x15)
--#define PPSMC_MSG_EnableThermalInterrupt    		((uint16_t)0x16)
--#define PPSMC_MSG_RunningOnAC               		((uint16_t)0x17)
--#define PPSMC_MSG_LevelUp                   		((uint16_t)0x18)
--#define PPSMC_MSG_LevelDown                 		((uint16_t)0x19)
--#define PPSMC_MSG_ResetDPMCounters          		((uint16_t)0x1a)
--#define PPSMC_MSG_SwitchToSwState           		((uint16_t)0x20)
--#define PPSMC_MSG_SwitchToSwStateLast       		((uint16_t)0x3f)
--#define PPSMC_MSG_SwitchToInitialState      		((uint16_t)0x40)
--#define PPSMC_MSG_NoForcedLevel             		((uint16_t)0x41)
--#define PPSMC_MSG_ForceHigh                 		((uint16_t)0x42)
--#define PPSMC_MSG_ForceMediumOrHigh         		((uint16_t)0x43)
--#define PPSMC_MSG_SwitchToMinimumPower      		((uint16_t)0x51)
--#define PPSMC_MSG_ResumeFromMinimumPower    		((uint16_t)0x52)
--#define PPSMC_MSG_EnableCac                 		((uint16_t)0x53)
--#define PPSMC_MSG_DisableCac                		((uint16_t)0x54)
--#define PPSMC_DPMStateHistoryStart          		((uint16_t)0x55)
--#define PPSMC_DPMStateHistoryStop           		((uint16_t)0x56)
--#define PPSMC_CACHistoryStart               		((uint16_t)0x57)
--#define PPSMC_CACHistoryStop                		((uint16_t)0x58)
--#define PPSMC_TDPClampingActive             		((uint16_t)0x59)
--#define PPSMC_TDPClampingInactive           		((uint16_t)0x5A)
--#define PPSMC_StartFanControl               		((uint16_t)0x5B)
--#define PPSMC_StopFanControl                		((uint16_t)0x5C)
--#define PPSMC_NoDisplay                     		((uint16_t)0x5D)
--#define PPSMC_HasDisplay                    		((uint16_t)0x5E)
--#define PPSMC_MSG_UVDPowerOFF               		((uint16_t)0x60)
--#define PPSMC_MSG_UVDPowerON                		((uint16_t)0x61)
--#define PPSMC_MSG_EnableULV                 		((uint16_t)0x62)
--#define PPSMC_MSG_DisableULV                		((uint16_t)0x63)
--#define PPSMC_MSG_EnterULV                  		((uint16_t)0x64)
--#define PPSMC_MSG_ExitULV                   		((uint16_t)0x65)
--#define PPSMC_PowerShiftActive              		((uint16_t)0x6A)
--#define PPSMC_PowerShiftInactive            		((uint16_t)0x6B)
--#define PPSMC_OCPActive                     		((uint16_t)0x6C)
--#define PPSMC_OCPInactive                   		((uint16_t)0x6D)
--#define PPSMC_CACLongTermAvgEnable          		((uint16_t)0x6E)
--#define PPSMC_CACLongTermAvgDisable         		((uint16_t)0x6F)
--#define PPSMC_MSG_InferredStateSweep_Start  		((uint16_t)0x70)
--#define PPSMC_MSG_InferredStateSweep_Stop   		((uint16_t)0x71)
--#define PPSMC_MSG_SwitchToLowestInfState    		((uint16_t)0x72)
--#define PPSMC_MSG_SwitchToNonInfState       		((uint16_t)0x73)
--#define PPSMC_MSG_AllStateSweep_Start       		((uint16_t)0x74)
--#define PPSMC_MSG_AllStateSweep_Stop        		((uint16_t)0x75)
--#define PPSMC_MSG_SwitchNextLowerInfState   		((uint16_t)0x76)
--#define PPSMC_MSG_SwitchNextHigherInfState  		((uint16_t)0x77)
--#define PPSMC_MSG_MclkRetrainingTest        		((uint16_t)0x78)
--#define PPSMC_MSG_ForceTDPClamping          		((uint16_t)0x79)
--#define PPSMC_MSG_CollectCAC_PowerCorreln   		((uint16_t)0x7A)
--#define PPSMC_MSG_CollectCAC_WeightCalib    		((uint16_t)0x7B)
--#define PPSMC_MSG_CollectCAC_SQonly         		((uint16_t)0x7C)
--#define PPSMC_MSG_CollectCAC_TemperaturePwr 		((uint16_t)0x7D)
--#define PPSMC_MSG_ExtremitiesTest_Start     		((uint16_t)0x7E)
--#define PPSMC_MSG_ExtremitiesTest_Stop      		((uint16_t)0x7F)
--#define PPSMC_FlushDataCache                		((uint16_t)0x80)
--#define PPSMC_FlushInstrCache               		((uint16_t)0x81)
--#define PPSMC_MSG_SetEnabledLevels          		((uint16_t)0x82)
--#define PPSMC_MSG_SetForcedLevels           		((uint16_t)0x83)
--#define PPSMC_MSG_ResetToDefaults           		((uint16_t)0x84)
--#define PPSMC_MSG_SetForcedLevelsAndJump    		((uint16_t)0x85)
--#define PPSMC_MSG_SetCACHistoryMode         		((uint16_t)0x86)
--#define PPSMC_MSG_EnableDTE                 		((uint16_t)0x87)
--#define PPSMC_MSG_DisableDTE                		((uint16_t)0x88)
--#define PPSMC_MSG_SmcSpaceSetAddress        		((uint16_t)0x89)
--#define PPSMC_MSG_SmcSpaceWriteDWordInc     		((uint16_t)0x8A)
--#define PPSMC_MSG_SmcSpaceWriteWordInc      		((uint16_t)0x8B)
--#define PPSMC_MSG_SmcSpaceWriteByteInc      		((uint16_t)0x8C)
--#define PPSMC_MSG_ChangeNearTDPLimit        		((uint16_t)0x90)
--#define PPSMC_MSG_ChangeSafePowerLimit      		((uint16_t)0x91)
--#define PPSMC_MSG_DPMStateSweepStart        		((uint16_t)0x92)
--#define PPSMC_MSG_DPMStateSweepStop         		((uint16_t)0x93)
--#define PPSMC_MSG_OVRDDisableSCLKDS         		((uint16_t)0x94)
--#define PPSMC_MSG_CancelDisableOVRDSCLKDS   		((uint16_t)0x95)
--#define PPSMC_MSG_ThrottleOVRDSCLKDS        		((uint16_t)0x96)
--#define PPSMC_MSG_CancelThrottleOVRDSCLKDS  		((uint16_t)0x97)
--#define PPSMC_MSG_GPIO17                    		((uint16_t)0x98)
--#define PPSMC_MSG_API_SetSvi2Volt_Vddc      		((uint16_t)0x99)
--#define PPSMC_MSG_API_SetSvi2Volt_Vddci     		((uint16_t)0x9A)
--#define PPSMC_MSG_API_SetSvi2Volt_Mvdd      		((uint16_t)0x9B)
--#define PPSMC_MSG_API_GetSvi2Volt_Vddc      		((uint16_t)0x9C)
--#define PPSMC_MSG_API_GetSvi2Volt_Vddci     		((uint16_t)0x9D)
--#define PPSMC_MSG_API_GetSvi2Volt_Mvdd      		((uint16_t)0x9E)
--
--#define PPSMC_MSG_BREAK                     		((uint16_t)0xF8)
--
--#define PPSMC_MSG_Test                      		((uint16_t)0x100)
--#define PPSMC_MSG_DRV_DRAM_ADDR_HI            		((uint16_t)0x250)
--#define PPSMC_MSG_DRV_DRAM_ADDR_LO            		((uint16_t)0x251)
--#define PPSMC_MSG_SMU_DRAM_ADDR_HI            		((uint16_t)0x252)
--#define PPSMC_MSG_SMU_DRAM_ADDR_LO            		((uint16_t)0x253)
--#define PPSMC_MSG_LoadUcodes                  		((uint16_t)0x254)
--
--typedef uint16_t PPSMC_Msg;
--
--#define PPSMC_EVENT_STATUS_THERMAL          		0x00000001
--#define PPSMC_EVENT_STATUS_REGULATORHOT     		0x00000002
--#define PPSMC_EVENT_STATUS_DC               		0x00000004
--#define PPSMC_EVENT_STATUS_GPIO17           		0x00000008
--
--#pragma pack(pop)
--
--#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72.h b/drivers/gpu/drm/amd/powerplay/inc/smu72.h
-new file mode 100644
-index 0000000..b73d6b5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu72.h
-@@ -0,0 +1,664 @@
-+#ifndef SMU72_H
-+#define SMU72_H
-+
-+#if !defined(SMC_MICROCODE)
-+#pragma pack(push, 1)
-+#endif
-+
-+#define SMU__NUM_SCLK_DPM_STATE  8
-+#define SMU__NUM_MCLK_DPM_LEVELS 4
-+#define SMU__NUM_LCLK_DPM_LEVELS 8
-+#define SMU__NUM_PCIE_DPM_LEVELS 8
-+
-+enum SID_OPTION {
-+	SID_OPTION_HI,
-+	SID_OPTION_LO,
-+	SID_OPTION_COUNT
-+};
-+
-+enum Poly3rdOrderCoeff {
-+	LEAKAGE_TEMPERATURE_SCALAR,
-+	LEAKAGE_VOLTAGE_SCALAR,
-+	DYNAMIC_VOLTAGE_SCALAR,
-+	POLY_3RD_ORDER_COUNT
-+};
-+
-+struct SMU7_Poly3rdOrder_Data {
-+	int32_t a;
-+	int32_t b;
-+	int32_t c;
-+	int32_t d;
-+	uint8_t a_shift;
-+	uint8_t b_shift;
-+	uint8_t c_shift;
-+	uint8_t x_shift;
-+};
-+
-+typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
-+
-+struct Power_Calculator_Data {
-+	uint16_t NoLoadVoltage;
-+	uint16_t LoadVoltage;
-+	uint16_t Resistance;
-+	uint16_t Temperature;
-+	uint16_t BaseLeakage;
-+	uint16_t LkgTempScalar;
-+	uint16_t LkgVoltScalar;
-+	uint16_t LkgAreaScalar;
-+	uint16_t LkgPower;
-+	uint16_t DynVoltScalar;
-+	uint32_t Cac;
-+	uint32_t DynPower;
-+	uint32_t TotalCurrent;
-+	uint32_t TotalPower;
-+};
-+
-+typedef struct Power_Calculator_Data PowerCalculatorData_t;
-+
-+struct Gc_Cac_Weight_Data {
-+	uint8_t index;
-+	uint32_t value;
-+};
-+
-+typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
-+
-+
-+typedef struct {
-+	uint32_t high;
-+	uint32_t low;
-+} data_64_t;
-+
-+typedef struct {
-+	data_64_t high;
-+	data_64_t low;
-+} data_128_t;
-+
-+#define SMU7_CONTEXT_ID_SMC        1
-+#define SMU7_CONTEXT_ID_VBIOS      2
-+
-+#define SMU72_MAX_LEVELS_VDDC            16
-+#define SMU72_MAX_LEVELS_VDDGFX          16
-+#define SMU72_MAX_LEVELS_VDDCI           8
-+#define SMU72_MAX_LEVELS_MVDD            4
-+
-+#define SMU_MAX_SMIO_LEVELS              4
-+
-+#define SMU72_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   /* SCLK + SQ DPM + ULV */
-+#define SMU72_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
-+#define SMU72_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  /* LCLK Levels */
-+#define SMU72_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  /* PCIe speed and number of lanes. */
-+#define SMU72_MAX_LEVELS_UVD             8   /* VCLK/DCLK levels for UVD. */
-+#define SMU72_MAX_LEVELS_VCE             8   /* ECLK levels for VCE. */
-+#define SMU72_MAX_LEVELS_ACP             8   /* ACLK levels for ACP. */
-+#define SMU72_MAX_LEVELS_SAMU            8   /* SAMCLK levels for SAMU. */
-+#define SMU72_MAX_ENTRIES_SMIO           32  /* Number of entries in SMIO table. */
-+
-+#define DPM_NO_LIMIT 0
-+#define DPM_NO_UP 1
-+#define DPM_GO_DOWN 2
-+#define DPM_GO_UP 3
-+
-+#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
-+#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
-+
-+#define GPIO_CLAMP_MODE_VRHOT      1
-+#define GPIO_CLAMP_MODE_THERM      2
-+#define GPIO_CLAMP_MODE_DC         4
-+
-+#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
-+#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
-+#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
-+#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
-+#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
-+#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
-+#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
-+#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
-+#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
-+#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
-+#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
-+
-+/* Virtualization Defines */
-+#define CG_XDMA_MASK  0x1
-+#define CG_XDMA_SHIFT 0
-+#define CG_UVD_MASK   0x2
-+#define CG_UVD_SHIFT  1
-+#define CG_VCE_MASK   0x4
-+#define CG_VCE_SHIFT  2
-+#define CG_SAMU_MASK  0x8
-+#define CG_SAMU_SHIFT 3
-+#define CG_GFX_MASK   0x10
-+#define CG_GFX_SHIFT  4
-+#define CG_SDMA_MASK  0x20
-+#define CG_SDMA_SHIFT 5
-+#define CG_HDP_MASK   0x40
-+#define CG_HDP_SHIFT  6
-+#define CG_MC_MASK    0x80
-+#define CG_MC_SHIFT   7
-+#define CG_DRM_MASK   0x100
-+#define CG_DRM_SHIFT  8
-+#define CG_ROM_MASK   0x200
-+#define CG_ROM_SHIFT  9
-+#define CG_BIF_MASK   0x400
-+#define CG_BIF_SHIFT  10
-+
-+#define SMU72_DTE_ITERATIONS 5
-+#define SMU72_DTE_SOURCES 3
-+#define SMU72_DTE_SINKS 1
-+#define SMU72_NUM_CPU_TES 0
-+#define SMU72_NUM_GPU_TES 1
-+#define SMU72_NUM_NON_TES 2
-+#define SMU72_DTE_FAN_SCALAR_MIN 0x100
-+#define SMU72_DTE_FAN_SCALAR_MAX 0x166
-+#define SMU72_DTE_FAN_TEMP_MAX 93
-+#define SMU72_DTE_FAN_TEMP_MIN 83
-+
-+#if defined SMU__FUSION_ONLY
-+#define SMU7_DTE_ITERATIONS 5
-+#define SMU7_DTE_SOURCES 5
-+#define SMU7_DTE_SINKS 3
-+#define SMU7_NUM_CPU_TES 2
-+#define SMU7_NUM_GPU_TES 1
-+#define SMU7_NUM_NON_TES 2
-+#endif
-+
-+struct SMU7_HystController_Data {
-+	uint8_t waterfall_up;
-+	uint8_t waterfall_down;
-+	uint8_t waterfall_limit;
-+	uint8_t spare;
-+	uint16_t release_cnt;
-+	uint16_t release_limit;
-+};
-+
-+typedef struct SMU7_HystController_Data SMU7_HystController_Data;
-+
-+struct SMU72_PIDController {
-+	uint32_t Ki;
-+	int32_t LFWindupUpperLim;
-+	int32_t LFWindupLowerLim;
-+	uint32_t StatePrecision;
-+	uint32_t LfPrecision;
-+	uint32_t LfOffset;
-+	uint32_t MaxState;
-+	uint32_t MaxLfFraction;
-+	uint32_t StateShift;
-+};
-+
-+typedef struct SMU72_PIDController SMU72_PIDController;
-+
-+struct SMU7_LocalDpmScoreboard {
-+	uint32_t PercentageBusy;
-+
-+	int32_t  PIDError;
-+	int32_t  PIDIntegral;
-+	int32_t  PIDOutput;
-+
-+	uint32_t SigmaDeltaAccum;
-+	uint32_t SigmaDeltaOutput;
-+	uint32_t SigmaDeltaLevel;
-+
-+	uint32_t UtilizationSetpoint;
-+
-+	uint8_t  TdpClampMode;
-+	uint8_t  TdcClampMode;
-+	uint8_t  ThermClampMode;
-+	uint8_t  VoltageBusy;
-+
-+	int8_t   CurrLevel;
-+	int8_t   TargLevel;
-+	uint8_t  LevelChangeInProgress;
-+	uint8_t  UpHyst;
-+
-+	uint8_t  DownHyst;
-+	uint8_t  VoltageDownHyst;
-+	uint8_t  DpmEnable;
-+	uint8_t  DpmRunning;
-+
-+	uint8_t  DpmForce;
-+	uint8_t  DpmForceLevel;
-+	uint8_t  DisplayWatermark;
-+	uint8_t  McArbIndex;
-+
-+	uint32_t MinimumPerfSclk;
-+
-+	uint8_t  AcpiReq;
-+	uint8_t  AcpiAck;
-+	uint8_t  GfxClkSlow;
-+	uint8_t  GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
-+
-+	uint8_t  FpsFilterWeight;
-+	uint8_t  EnabledLevelsChange;
-+	uint8_t  DteClampMode;
-+	uint8_t  FpsClampMode;
-+
-+	uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
-+	uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
-+
-+	void     (*TargetStateCalculator)(uint8_t);
-+	void     (*SavedTargetStateCalculator)(uint8_t);
-+
-+	uint16_t AutoDpmInterval;
-+	uint16_t AutoDpmRange;
-+
-+	uint8_t  FpsEnabled;
-+	uint8_t  MaxPerfLevel;
-+	uint8_t  AllowLowClkInterruptToHost;
-+	uint8_t  FpsRunning;
-+
-+	uint32_t MaxAllowedFrequency;
-+
-+	uint32_t FilteredSclkFrequency;
-+	uint32_t LastSclkFrequency;
-+	uint32_t FilteredSclkFrequencyCnt;
-+};
-+
-+typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
-+
-+#define SMU7_MAX_VOLTAGE_CLIENTS 12
-+
-+typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
-+
-+struct SMU_VoltageLevel {
-+	uint8_t Vddc;
-+	uint8_t Vddci;
-+	uint8_t VddGfx;
-+	uint8_t Phases;
-+};
-+
-+typedef struct SMU_VoltageLevel SMU_VoltageLevel;
-+
-+struct SMU7_VoltageScoreboard {
-+	SMU_VoltageLevel CurrentVoltage;
-+	SMU_VoltageLevel TargetVoltage;
-+	uint16_t MaxVid;
-+	uint8_t  HighestVidOffset;
-+	uint8_t  CurrentVidOffset;
-+
-+	uint8_t  ControllerBusy;
-+	uint8_t  CurrentVid;
-+	uint8_t  CurrentVddciVid;
-+	uint8_t  VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
-+
-+	SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
-+	uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
-+
-+	uint8_t  TargetIndex;
-+	uint8_t  Delay;
-+	uint8_t  ControllerEnable;
-+	uint8_t  ControllerRunning;
-+	uint16_t CurrentStdVoltageHiSidd;
-+	uint16_t CurrentStdVoltageLoSidd;
-+	uint8_t  OverrideVoltage;
-+	uint8_t  VddcUseUlvOffset;
-+	uint8_t  VddGfxUseUlvOffset;
-+	uint8_t  padding;
-+
-+	VoltageChangeHandler_t ChangeVddc;
-+	VoltageChangeHandler_t ChangeVddGfx;
-+	VoltageChangeHandler_t ChangeVddci;
-+	VoltageChangeHandler_t ChangePhase;
-+	VoltageChangeHandler_t ChangeMvdd;
-+
-+	VoltageChangeHandler_t functionLinks[6];
-+
-+	uint8_t *VddcFollower1;
-+	uint8_t *VddcFollower2;
-+	int16_t  Driver_OD_RequestedVidOffset1;
-+	int16_t  Driver_OD_RequestedVidOffset2;
-+
-+};
-+
-+typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
-+
-+#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
-+
-+struct SMU7_PCIeLinkSpeedScoreboard {
-+	uint8_t     DpmEnable;
-+	uint8_t     DpmRunning;
-+	uint8_t     DpmForce;
-+	uint8_t     DpmForceLevel;
-+
-+	uint8_t     CurrentLinkSpeed;
-+	uint8_t     EnabledLevelsChange;
-+	uint16_t    AutoDpmInterval;
-+
-+	uint16_t    AutoDpmRange;
-+	uint16_t    AutoDpmCount;
-+
-+	uint8_t     DpmMode;
-+	uint8_t     AcpiReq;
-+	uint8_t     AcpiAck;
-+	uint8_t     CurrentLinkLevel;
-+
-+};
-+
-+typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
-+
-+/* -------------------------------------------------------- CAC table ------------------------------------------------------ */
-+#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
-+#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
-+#define SMU7_SCALE_I  7
-+#define SMU7_SCALE_R 12
-+
-+struct SMU7_PowerScoreboard {
-+	PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
-+	PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
-+
-+	uint32_t TotalGpuPower;
-+	uint32_t TdcCurrent;
-+
-+	uint16_t   VddciTotalPower;
-+	uint16_t   sparesasfsdfd;
-+	uint16_t   Vddr1Power;
-+	uint16_t   RocPower;
-+
-+	uint16_t   CalcMeasPowerBlend;
-+	uint8_t    SidOptionPower;
-+	uint8_t    SidOptionCurrent;
-+
-+	uint32_t   WinTime;
-+
-+	uint16_t Telemetry_1_slope;
-+	uint16_t Telemetry_2_slope;
-+	int32_t Telemetry_1_offset;
-+	int32_t Telemetry_2_offset;
-+
-+	uint32_t VddcCurrentTelemetry;
-+	uint32_t VddGfxCurrentTelemetry;
-+	uint32_t VddcPowerTelemetry;
-+	uint32_t VddGfxPowerTelemetry;
-+	uint32_t VddciPowerTelemetry;
-+
-+	uint32_t VddcPower;
-+	uint32_t VddGfxPower;
-+	uint32_t VddciPower;
-+
-+	uint32_t TelemetryCurrent[2];
-+	uint32_t TelemetryVoltage[2];
-+	uint32_t TelemetryPower[2];
-+};
-+
-+typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
-+
-+struct SMU7_ThermalScoreboard {
-+	int16_t  GpuLimit;
-+	int16_t  GpuHyst;
-+	uint16_t CurrGnbTemp;
-+	uint16_t FilteredGnbTemp;
-+
-+	uint8_t  ControllerEnable;
-+	uint8_t  ControllerRunning;
-+	uint8_t  AutoTmonCalInterval;
-+	uint8_t  AutoTmonCalEnable;
-+
-+	uint8_t  ThermalDpmEnabled;
-+	uint8_t  SclkEnabledMask;
-+	uint8_t  spare[2];
-+	int32_t  temperature_gradient;
-+
-+	SMU7_HystController_Data HystControllerData;
-+	int32_t  WeightedSensorTemperature;
-+	uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
-+	uint32_t Alpha;
-+};
-+
-+typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
-+
-+/* For FeatureEnables: */
-+#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
-+#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
-+#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
-+#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
-+#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
-+#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
-+#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
-+#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
-+#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
-+
-+#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
-+#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
-+#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
-+#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
-+#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
-+#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
-+
-+/* All 'soft registers' should be uint32_t. */
-+struct SMU72_SoftRegisters {
-+	uint32_t        RefClockFrequency;
-+	uint32_t        PmTimerPeriod;
-+	uint32_t        FeatureEnables;
-+
-+	uint32_t        PreVBlankGap;
-+	uint32_t        VBlankTimeout;
-+	uint32_t        TrainTimeGap;
-+
-+	uint32_t        MvddSwitchTime;
-+	uint32_t        LongestAcpiTrainTime;
-+	uint32_t        AcpiDelay;
-+	uint32_t        G5TrainTime;
-+	uint32_t        DelayMpllPwron;
-+	uint32_t        VoltageChangeTimeout;
-+
-+	uint32_t        HandshakeDisables;
-+
-+	uint8_t         DisplayPhy1Config;
-+	uint8_t         DisplayPhy2Config;
-+	uint8_t         DisplayPhy3Config;
-+	uint8_t         DisplayPhy4Config;
-+
-+	uint8_t         DisplayPhy5Config;
-+	uint8_t         DisplayPhy6Config;
-+	uint8_t         DisplayPhy7Config;
-+	uint8_t         DisplayPhy8Config;
-+
-+	uint32_t        AverageGraphicsActivity;
-+	uint32_t        AverageMemoryActivity;
-+	uint32_t        AverageGioActivity;
-+
-+	uint8_t         SClkDpmEnabledLevels;
-+	uint8_t         MClkDpmEnabledLevels;
-+	uint8_t         LClkDpmEnabledLevels;
-+	uint8_t         PCIeDpmEnabledLevels;
-+
-+	uint8_t         UVDDpmEnabledLevels;
-+	uint8_t         SAMUDpmEnabledLevels;
-+	uint8_t         ACPDpmEnabledLevels;
-+	uint8_t         VCEDpmEnabledLevels;
-+
-+	uint32_t        DRAM_LOG_ADDR_H;
-+	uint32_t        DRAM_LOG_ADDR_L;
-+	uint32_t        DRAM_LOG_PHY_ADDR_H;
-+	uint32_t        DRAM_LOG_PHY_ADDR_L;
-+	uint32_t        DRAM_LOG_BUFF_SIZE;
-+	uint32_t        UlvEnterCount;
-+	uint32_t        UlvTime;
-+	uint32_t        UcodeLoadStatus;
-+	uint32_t        Reserved[2];
-+
-+};
-+
-+typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
-+
-+struct SMU72_Firmware_Header {
-+	uint32_t Digest[5];
-+	uint32_t Version;
-+	uint32_t HeaderSize;
-+	uint32_t Flags;
-+	uint32_t EntryPoint;
-+	uint32_t CodeSize;
-+	uint32_t ImageSize;
-+
-+	uint32_t Rtos;
-+	uint32_t SoftRegisters;
-+	uint32_t DpmTable;
-+	uint32_t FanTable;
-+	uint32_t CacConfigTable;
-+	uint32_t CacStatusTable;
-+	uint32_t mcRegisterTable;
-+	uint32_t mcArbDramTimingTable;
-+	uint32_t PmFuseTable;
-+	uint32_t Globals;
-+	uint32_t ClockStretcherTable;
-+	uint32_t Reserved[41];
-+	uint32_t Signature;
-+};
-+
-+typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
-+
-+#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
-+
-+enum  DisplayConfig {
-+	PowerDown = 1,
-+	DP54x4,
-+	DP54x2,
-+	DP54x1,
-+	DP27x4,
-+	DP27x2,
-+	DP27x1,
-+	HDMI297,
-+	HDMI162,
-+	LVDS,
-+	DP324x4,
-+	DP324x2,
-+	DP324x1
-+};
-+
-+#define MC_BLOCK_COUNT 1
-+#define CPL_BLOCK_COUNT 5
-+#define SE_BLOCK_COUNT 15
-+#define GC_BLOCK_COUNT 24
-+
-+struct SMU7_Local_Cac {
-+	uint8_t BlockId;
-+	uint8_t SignalId;
-+	uint8_t Threshold;
-+	uint8_t Padding;
-+};
-+
-+typedef struct SMU7_Local_Cac SMU7_Local_Cac;
-+
-+struct SMU7_Local_Cac_Table {
-+	SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
-+	SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
-+	SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
-+	SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
-+};
-+
-+typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
-+
-+#if !defined(SMC_MICROCODE)
-+#pragma pack(pop)
-+#endif
-+
-+/* Description of Clock Gating bitmask for Tonga: */
-+/* System Clock Gating */
-+#define CG_SYS_BITMASK_FIRST_BIT      0  /* First bit of Sys CG bitmask */
-+#define CG_SYS_BITMASK_LAST_BIT       9  /* Last bit of Sys CG bitmask */
-+#define CG_SYS_BIF_MGLS_SHIFT         0
-+#define CG_SYS_ROM_SHIFT              1
-+#define CG_SYS_MC_MGCG_SHIFT          2
-+#define CG_SYS_MC_MGLS_SHIFT          3
-+#define CG_SYS_SDMA_MGCG_SHIFT        4
-+#define CG_SYS_SDMA_MGLS_SHIFT        5
-+#define CG_SYS_DRM_MGCG_SHIFT         6
-+#define CG_SYS_HDP_MGCG_SHIFT         7
-+#define CG_SYS_HDP_MGLS_SHIFT         8
-+#define CG_SYS_DRM_MGLS_SHIFT         9
-+
-+#define CG_SYS_BIF_MGLS_MASK          0x1
-+#define CG_SYS_ROM_MASK               0x2
-+#define CG_SYS_MC_MGCG_MASK           0x4
-+#define CG_SYS_MC_MGLS_MASK           0x8
-+#define CG_SYS_SDMA_MGCG_MASK         0x10
-+#define CG_SYS_SDMA_MGLS_MASK         0x20
-+#define CG_SYS_DRM_MGCG_MASK          0x40
-+#define CG_SYS_HDP_MGCG_MASK          0x80
-+#define CG_SYS_HDP_MGLS_MASK          0x100
-+#define CG_SYS_DRM_MGLS_MASK          0x200
-+
-+/* Graphics Clock Gating */
-+#define CG_GFX_BITMASK_FIRST_BIT      16 /* First bit of Gfx CG bitmask */
-+#define CG_GFX_BITMASK_LAST_BIT       20 /* Last bit of Gfx CG bitmask */
-+#define CG_GFX_CGCG_SHIFT             16
-+#define CG_GFX_CGLS_SHIFT             17
-+#define CG_CPF_MGCG_SHIFT             18
-+#define CG_RLC_MGCG_SHIFT             19
-+#define CG_GFX_OTHERS_MGCG_SHIFT      20
-+
-+#define CG_GFX_CGCG_MASK              0x00010000
-+#define CG_GFX_CGLS_MASK              0x00020000
-+#define CG_CPF_MGCG_MASK              0x00040000
-+#define CG_RLC_MGCG_MASK              0x00080000
-+#define CG_GFX_OTHERS_MGCG_MASK       0x00100000
-+
-+/* Voltage Regulator Configuration */
-+/* VR Config info is contained in dpmTable.VRConfig */
-+
-+#define VRCONF_VDDC_MASK         0x000000FF
-+#define VRCONF_VDDC_SHIFT        0
-+#define VRCONF_VDDGFX_MASK       0x0000FF00
-+#define VRCONF_VDDGFX_SHIFT      8
-+#define VRCONF_VDDCI_MASK        0x00FF0000
-+#define VRCONF_VDDCI_SHIFT       16
-+#define VRCONF_MVDD_MASK         0xFF000000
-+#define VRCONF_MVDD_SHIFT        24
-+
-+#define VR_MERGED_WITH_VDDC      0
-+#define VR_SVI2_PLANE_1          1
-+#define VR_SVI2_PLANE_2          2
-+#define VR_SMIO_PATTERN_1        3
-+#define VR_SMIO_PATTERN_2        4
-+#define VR_STATIC_VOLTAGE        5
-+
-+/* Clock Stretcher Configuration */
-+
-+#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
-+#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
-+
-+/* The 'settings' field is subdivided in the following way: */
-+#define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
-+#define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
-+#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
-+#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
-+#define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
-+#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
-+
-+struct SMU_ClockStretcherDataTableEntry {
-+	uint8_t minVID;
-+	uint8_t maxVID;
-+
-+	uint16_t setting;
-+};
-+typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
-+
-+struct SMU_ClockStretcherDataTable {
-+	SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
-+};
-+typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
-+
-+struct SMU_CKS_LOOKUPTableEntry {
-+	uint16_t minFreq;
-+	uint16_t maxFreq;
-+
-+	uint8_t setting;
-+	uint8_t padding[3];
-+};
-+typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
-+
-+struct SMU_CKS_LOOKUPTable {
-+	SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
-+};
-+typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
-+
-+#endif
-+
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h
-new file mode 100644
-index 0000000..98f76e9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h
-@@ -0,0 +1,760 @@
-+#ifndef SMU72_DISCRETE_H
-+#define SMU72_DISCRETE_H
-+
-+#include "smu72.h"
-+
-+#if !defined(SMC_MICROCODE)
-+#pragma pack(push, 1)
-+#endif
-+
-+struct SMIO_Pattern {
-+	uint16_t Voltage;
-+	uint8_t  Smio;
-+	uint8_t  padding;
-+};
-+
-+typedef struct SMIO_Pattern SMIO_Pattern;
-+
-+struct SMIO_Table {
-+	SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
-+};
-+
-+typedef struct SMIO_Table SMIO_Table;
-+
-+struct SMU72_Discrete_GraphicsLevel {
-+	SMU_VoltageLevel MinVoltage;
-+
-+	uint32_t    SclkFrequency;
-+
-+	uint8_t     pcieDpmLevel;
-+	uint8_t     DeepSleepDivId;
-+	uint16_t    ActivityLevel;
-+
-+	uint32_t    CgSpllFuncCntl3;
-+	uint32_t    CgSpllFuncCntl4;
-+	uint32_t    SpllSpreadSpectrum;
-+	uint32_t    SpllSpreadSpectrum2;
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+	uint8_t     SclkDid;
-+	uint8_t     DisplayWatermark;
-+	uint8_t     EnabledForActivity;
-+	uint8_t     EnabledForThrottle;
-+	uint8_t     UpHyst;
-+	uint8_t     DownHyst;
-+	uint8_t     VoltageDownHyst;
-+	uint8_t     PowerThrottle;
-+};
-+
-+typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
-+
-+struct SMU72_Discrete_ACPILevel {
-+	uint32_t    Flags;
-+	SMU_VoltageLevel MinVoltage;
-+	uint32_t    SclkFrequency;
-+	uint8_t     SclkDid;
-+	uint8_t     DisplayWatermark;
-+	uint8_t     DeepSleepDivId;
-+	uint8_t     padding;
-+	uint32_t    CgSpllFuncCntl;
-+	uint32_t    CgSpllFuncCntl2;
-+	uint32_t    CgSpllFuncCntl3;
-+	uint32_t    CgSpllFuncCntl4;
-+	uint32_t    SpllSpreadSpectrum;
-+	uint32_t    SpllSpreadSpectrum2;
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+};
-+
-+typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
-+
-+struct SMU72_Discrete_Ulv {
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+	uint16_t    VddcOffset;
-+	uint8_t     VddcOffsetVid;
-+	uint8_t     VddcPhase;
-+	uint32_t    Reserved;
-+};
-+
-+typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
-+
-+struct SMU72_Discrete_MemoryLevel {
-+	SMU_VoltageLevel MinVoltage;
-+	uint32_t    MinMvdd;
-+
-+	uint32_t    MclkFrequency;
-+
-+	uint8_t     EdcReadEnable;
-+	uint8_t     EdcWriteEnable;
-+	uint8_t     RttEnable;
-+	uint8_t     StutterEnable;
-+
-+	uint8_t     StrobeEnable;
-+	uint8_t     StrobeRatio;
-+	uint8_t     EnabledForThrottle;
-+	uint8_t     EnabledForActivity;
-+
-+	uint8_t     UpHyst;
-+	uint8_t     DownHyst;
-+	uint8_t     VoltageDownHyst;
-+	uint8_t     padding;
-+
-+	uint16_t    ActivityLevel;
-+	uint8_t     DisplayWatermark;
-+	uint8_t     padding1;
-+
-+	uint32_t    MpllFuncCntl;
-+	uint32_t    MpllFuncCntl_1;
-+	uint32_t    MpllFuncCntl_2;
-+	uint32_t    MpllAdFuncCntl;
-+	uint32_t    MpllDqFuncCntl;
-+	uint32_t    MclkPwrmgtCntl;
-+	uint32_t    DllCntl;
-+	uint32_t    MpllSs1;
-+	uint32_t    MpllSs2;
-+};
-+
-+typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
-+
-+struct SMU72_Discrete_LinkLevel {
-+	uint8_t     PcieGenSpeed;           /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
-+	uint8_t     PcieLaneCount;          /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
-+	uint8_t     EnabledForActivity;
-+	uint8_t     SPC;
-+	uint32_t    DownThreshold;
-+	uint32_t    UpThreshold;
-+	uint32_t    Reserved;
-+};
-+
-+typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
-+
-+/* MC ARB DRAM Timing registers. */
-+struct SMU72_Discrete_MCArbDramTimingTableEntry {
-+	uint32_t McArbDramTiming;
-+	uint32_t McArbDramTiming2;
-+	uint8_t  McArbBurstTime;
-+	uint8_t  padding[3];
-+};
-+
-+typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
-+
-+struct SMU72_Discrete_MCArbDramTimingTable {
-+	SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
-+};
-+
-+typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
-+
-+/* UVD VCLK/DCLK state (level) definition. */
-+struct SMU72_Discrete_UvdLevel {
-+	uint32_t VclkFrequency;
-+	uint32_t DclkFrequency;
-+	SMU_VoltageLevel MinVoltage;
-+	uint8_t  VclkDivider;
-+	uint8_t  DclkDivider;
-+	uint8_t  padding[2];
-+};
-+
-+typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
-+
-+/* Clocks for other external blocks (VCE, ACP, SAMU). */
-+struct SMU72_Discrete_ExtClkLevel {
-+	uint32_t Frequency;
-+	SMU_VoltageLevel MinVoltage;
-+	uint8_t  Divider;
-+	uint8_t  padding[3];
-+};
-+
-+typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
-+
-+struct SMU72_Discrete_StateInfo {
-+	uint32_t SclkFrequency;
-+	uint32_t MclkFrequency;
-+	uint32_t VclkFrequency;
-+	uint32_t DclkFrequency;
-+	uint32_t SamclkFrequency;
-+	uint32_t AclkFrequency;
-+	uint32_t EclkFrequency;
-+	uint16_t MvddVoltage;
-+	uint16_t padding16;
-+	uint8_t  DisplayWatermark;
-+	uint8_t  McArbIndex;
-+	uint8_t  McRegIndex;
-+	uint8_t  SeqIndex;
-+	uint8_t  SclkDid;
-+	int8_t   SclkIndex;
-+	int8_t   MclkIndex;
-+	uint8_t  PCIeGen;
-+
-+};
-+
-+typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
-+
-+struct SMU72_Discrete_DpmTable {
-+	/* Multi-DPM controller settings */
-+	SMU72_PIDController                  GraphicsPIDController;
-+	SMU72_PIDController                  MemoryPIDController;
-+	SMU72_PIDController                  LinkPIDController;
-+
-+	uint32_t                            SystemFlags;
-+
-+	/* SMIO masks for voltage and phase controls */
-+	uint32_t                            VRConfig;
-+	uint32_t                            SmioMask1;
-+	uint32_t                            SmioMask2;
-+	SMIO_Table                          SmioTable1;
-+	SMIO_Table                          SmioTable2;
-+
-+	uint32_t                            VddcLevelCount;
-+	uint32_t                            VddciLevelCount;
-+	uint32_t                            VddGfxLevelCount;
-+	uint32_t                            MvddLevelCount;
-+
-+	uint16_t                            VddcTable[SMU72_MAX_LEVELS_VDDC];
-+	uint16_t                            VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
-+	uint16_t                            VddciTable[SMU72_MAX_LEVELS_VDDCI];
-+
-+	uint8_t                             BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
-+	uint8_t                             BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
-+	uint8_t                             BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
-+
-+	uint8_t                             BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
-+	uint8_t                             BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
-+	uint8_t                             BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
-+
-+	uint8_t                             GraphicsDpmLevelCount;
-+	uint8_t                             MemoryDpmLevelCount;
-+	uint8_t                             LinkLevelCount;
-+	uint8_t                             MasterDeepSleepControl;
-+
-+	uint8_t                             UvdLevelCount;
-+	uint8_t                             VceLevelCount;
-+	uint8_t                             AcpLevelCount;
-+	uint8_t                             SamuLevelCount;
-+
-+	uint8_t                             ThermOutGpio;
-+	uint8_t                             ThermOutPolarity;
-+	uint8_t                             ThermOutMode;
-+	uint8_t                             DPMFreezeAndForced;
-+	uint32_t                            Reserved[4];
-+
-+	/* State table entries for each DPM state */
-+	SMU72_Discrete_GraphicsLevel        GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
-+	SMU72_Discrete_MemoryLevel          MemoryACPILevel;
-+	SMU72_Discrete_MemoryLevel          MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
-+	SMU72_Discrete_LinkLevel            LinkLevel[SMU72_MAX_LEVELS_LINK];
-+	SMU72_Discrete_ACPILevel            ACPILevel;
-+	SMU72_Discrete_UvdLevel             UvdLevel[SMU72_MAX_LEVELS_UVD];
-+	SMU72_Discrete_ExtClkLevel          VceLevel[SMU72_MAX_LEVELS_VCE];
-+	SMU72_Discrete_ExtClkLevel          AcpLevel[SMU72_MAX_LEVELS_ACP];
-+	SMU72_Discrete_ExtClkLevel          SamuLevel[SMU72_MAX_LEVELS_SAMU];
-+	SMU72_Discrete_Ulv                  Ulv;
-+
-+	uint32_t                            SclkStepSize;
-+	uint32_t                            Smio[SMU72_MAX_ENTRIES_SMIO];
-+
-+	uint8_t                             UvdBootLevel;
-+	uint8_t                             VceBootLevel;
-+	uint8_t                             AcpBootLevel;
-+	uint8_t                             SamuBootLevel;
-+
-+	uint8_t                             GraphicsBootLevel;
-+	uint8_t                             GraphicsVoltageChangeEnable;
-+	uint8_t                             GraphicsThermThrottleEnable;
-+	uint8_t                             GraphicsInterval;
-+
-+	uint8_t                             VoltageInterval;
-+	uint8_t                             ThermalInterval;
-+	uint16_t                            TemperatureLimitHigh;
-+
-+	uint16_t                            TemperatureLimitLow;
-+	uint8_t                             MemoryBootLevel;
-+	uint8_t                             MemoryVoltageChangeEnable;
-+
-+	uint16_t                            BootMVdd;
-+	uint8_t                             MemoryInterval;
-+	uint8_t                             MemoryThermThrottleEnable;
-+
-+	uint16_t                            VoltageResponseTime;
-+	uint16_t                            PhaseResponseTime;
-+
-+	uint8_t                             PCIeBootLinkLevel;
-+	uint8_t                             PCIeGenInterval;
-+	uint8_t                             DTEInterval;
-+	uint8_t                             DTEMode;
-+
-+	uint8_t                             SVI2Enable;
-+	uint8_t                             VRHotGpio;
-+	uint8_t                             AcDcGpio;
-+	uint8_t                             ThermGpio;
-+
-+	uint16_t                            PPM_PkgPwrLimit;
-+	uint16_t                            PPM_TemperatureLimit;
-+
-+	uint16_t                            DefaultTdp;
-+	uint16_t                            TargetTdp;
-+
-+	uint16_t                            FpsHighThreshold;
-+	uint16_t                            FpsLowThreshold;
-+
-+	uint16_t                            BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
-+	uint16_t                            BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
-+
-+	uint8_t                             DTEAmbientTempBase;
-+	uint8_t                             DTETjOffset;
-+	uint8_t                             GpuTjMax;
-+	uint8_t                             GpuTjHyst;
-+
-+	SMU_VoltageLevel                    BootVoltage;
-+
-+	uint32_t                            BAPM_TEMP_GRADIENT;
-+
-+	uint32_t                            LowSclkInterruptThreshold;
-+	uint32_t                            VddGfxReChkWait;
-+
-+	uint8_t                             ClockStretcherAmount;
-+
-+	uint8_t                             Sclk_CKS_masterEn0_7;
-+	uint8_t                             Sclk_CKS_masterEn8_15;
-+	uint8_t                             padding[1];
-+
-+	uint8_t                             Sclk_voltageOffset[8];
-+
-+	SMU_ClockStretcherDataTable         ClockStretcherDataTable;
-+	SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
-+};
-+
-+typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
-+
-+/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
-+#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
-+#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
-+
-+struct SMU72_Discrete_MCRegisterAddress {
-+	uint16_t s0;
-+	uint16_t s1;
-+};
-+
-+typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
-+
-+struct SMU72_Discrete_MCRegisterSet {
-+	uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+};
-+
-+typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
-+
-+struct SMU72_Discrete_MCRegisters {
-+	uint8_t                             last;
-+	uint8_t                             reserved[3];
-+	SMU72_Discrete_MCRegisterAddress     address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+	SMU72_Discrete_MCRegisterSet         data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
-+};
-+
-+typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
-+
-+
-+/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
-+
-+struct SMU72_Discrete_FanTable {
-+	uint16_t FdoMode;
-+	int16_t  TempMin;
-+	int16_t  TempMed;
-+	int16_t  TempMax;
-+	int16_t  Slope1;
-+	int16_t  Slope2;
-+	int16_t  FdoMin;
-+	int16_t  HystUp;
-+	int16_t  HystDown;
-+	int16_t  HystSlope;
-+	int16_t  TempRespLim;
-+	int16_t  TempCurr;
-+	int16_t  SlopeCurr;
-+	int16_t  PwmCurr;
-+	uint32_t RefreshPeriod;
-+	int16_t  FdoMax;
-+	uint8_t  TempSrc;
-+	int8_t   FanControl_GL_Flag;
-+};
-+
-+typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
-+
-+#define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
-+#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
-+
-+struct SMU7_MclkDpmScoreboard {
-+
-+	uint32_t PercentageBusy;
-+
-+	int32_t  PIDError;
-+	int32_t  PIDIntegral;
-+	int32_t  PIDOutput;
-+
-+	uint32_t SigmaDeltaAccum;
-+	uint32_t SigmaDeltaOutput;
-+	uint32_t SigmaDeltaLevel;
-+
-+	uint32_t UtilizationSetpoint;
-+
-+	uint8_t  TdpClampMode;
-+	uint8_t  TdcClampMode;
-+	uint8_t  ThermClampMode;
-+	uint8_t  VoltageBusy;
-+
-+	int8_t   CurrLevel;
-+	int8_t   TargLevel;
-+	uint8_t  LevelChangeInProgress;
-+	uint8_t  UpHyst;
-+
-+	uint8_t  DownHyst;
-+	uint8_t  VoltageDownHyst;
-+	uint8_t  DpmEnable;
-+	uint8_t  DpmRunning;
-+
-+	uint8_t  DpmForce;
-+	uint8_t  DpmForceLevel;
-+	uint8_t  DisplayWatermark;
-+	uint8_t  McArbIndex;
-+
-+	uint32_t MinimumPerfMclk;
-+
-+	uint8_t  AcpiReq;
-+	uint8_t  AcpiAck;
-+	uint8_t  MclkSwitchInProgress;
-+	uint8_t  MclkSwitchCritical;
-+
-+	uint8_t  IgnoreVBlank;
-+	uint8_t  TargetMclkIndex;
-+	uint8_t  TargetMvddIndex;
-+	uint8_t  MclkSwitchResult;
-+
-+	uint16_t VbiFailureCount;
-+	uint8_t  VbiWaitCounter;
-+	uint8_t  EnabledLevelsChange;
-+
-+	uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
-+	uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
-+
-+	void     (*TargetStateCalculator)(uint8_t);
-+	void     (*SavedTargetStateCalculator)(uint8_t);
-+
-+	uint16_t AutoDpmInterval;
-+	uint16_t AutoDpmRange;
-+
-+	uint16_t VbiTimeoutCount;
-+	uint16_t MclkSwitchingTime;
-+
-+	uint8_t  fastSwitch;
-+	uint8_t  Save_PIC_VDDGFX_EXIT;
-+	uint8_t  Save_PIC_VDDGFX_ENTER;
-+	uint8_t  padding;
-+
-+};
-+
-+typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
-+
-+struct SMU7_UlvScoreboard {
-+	uint8_t     EnterUlv;
-+	uint8_t     ExitUlv;
-+	uint8_t     UlvActive;
-+	uint8_t     WaitingForUlv;
-+	uint8_t     UlvEnable;
-+	uint8_t     UlvRunning;
-+	uint8_t     UlvMasterEnable;
-+	uint8_t     padding;
-+	uint32_t    UlvAbortedCount;
-+	uint32_t    UlvTimeStamp;
-+};
-+
-+typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
-+
-+struct VddgfxSavedRegisters {
-+	uint32_t GPU_DBG[3];
-+	uint32_t MEC_BaseAddress_Hi;
-+	uint32_t MEC_BaseAddress_Lo;
-+	uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
-+	uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
-+	uint32_t CP_INT_CNTL;
-+};
-+
-+typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
-+
-+struct SMU7_VddGfxScoreboard {
-+	uint8_t     VddGfxEnable;
-+	uint8_t     VddGfxActive;
-+	uint8_t     VPUResetOccured;
-+	uint8_t     padding;
-+
-+	uint32_t    VddGfxEnteredCount;
-+	uint32_t    VddGfxAbortedCount;
-+
-+	uint32_t    VddGfxVid;
-+
-+	VddgfxSavedRegisters SavedRegisters;
-+};
-+
-+typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
-+
-+struct SMU7_TdcLimitScoreboard {
-+	uint8_t  Enable;
-+	uint8_t  Running;
-+	uint16_t Alpha;
-+	uint32_t FilteredIddc;
-+	uint32_t IddcLimit;
-+	uint32_t IddcHyst;
-+	SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
-+
-+struct SMU7_PkgPwrLimitScoreboard {
-+	uint8_t  Enable;
-+	uint8_t  Running;
-+	uint16_t Alpha;
-+	uint32_t FilteredPkgPwr;
-+	uint32_t Limit;
-+	uint32_t Hyst;
-+	uint32_t LimitFromDriver;
-+	SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
-+
-+struct SMU7_BapmScoreboard {
-+	uint32_t source_powers[SMU72_DTE_SOURCES];
-+	uint32_t source_powers_last[SMU72_DTE_SOURCES];
-+	int32_t entity_temperatures[SMU72_NUM_GPU_TES];
-+	int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
-+	int32_t Limit;
-+	int32_t Hyst;
-+	int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
-+	int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
-+	uint16_t ConfigTDPPowerScalar;
-+	uint16_t FanSpeedPowerScalar;
-+	uint16_t OverDrivePowerScalar;
-+	uint16_t OverDriveLimitScalar;
-+	uint16_t FinalPowerScalar;
-+	uint8_t VariantID;
-+	uint8_t spare997;
-+
-+	SMU7_HystController_Data HystControllerData;
-+
-+	int32_t temperature_gradient_slope;
-+	int32_t temperature_gradient;
-+	uint32_t measured_temperature;
-+};
-+
-+
-+typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
-+
-+struct SMU7_AcpiScoreboard {
-+	uint32_t SavedInterruptMask[2];
-+	uint8_t LastACPIRequest;
-+	uint8_t CgBifResp;
-+	uint8_t RequestType;
-+	uint8_t Padding;
-+	SMU72_Discrete_ACPILevel D0Level;
-+};
-+
-+typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
-+
-+struct SMU72_Discrete_PmFuses {
-+	/* dw1  */
-+	uint8_t SviLoadLineEn;
-+	uint8_t SviLoadLineVddC;
-+	uint8_t SviLoadLineTrimVddC;
-+	uint8_t SviLoadLineOffsetVddC;
-+
-+	/* dw2 */
-+	uint16_t TDC_VDDC_PkgLimit;
-+	uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
-+	uint8_t TDC_MAWt;
-+
-+	/* dw3 */
-+	uint8_t TdcWaterfallCtl;
-+	uint8_t LPMLTemperatureMin;
-+	uint8_t LPMLTemperatureMax;
-+	uint8_t Reserved;
-+
-+	/* dw4-dw7  */
-+	uint8_t LPMLTemperatureScaler[16];
-+
-+	/* dw8-dw9  */
-+	int16_t FuzzyFan_ErrorSetDelta;
-+	int16_t FuzzyFan_ErrorRateSetDelta;
-+	int16_t FuzzyFan_PwmSetDelta;
-+	uint16_t Reserved6;
-+
-+	/* dw10-dw14  */
-+	uint8_t GnbLPML[16];
-+
-+	/* dw15 */
-+	uint8_t GnbLPMLMaxVid;
-+	uint8_t GnbLPMLMinVid;
-+	uint8_t Reserved1[2];
-+
-+	/* dw16 */
-+	uint16_t BapmVddCBaseLeakageHiSidd;
-+	uint16_t BapmVddCBaseLeakageLoSidd;
-+};
-+
-+typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
-+
-+struct SMU7_Discrete_Log_Header_Table {
-+	uint32_t    version;
-+	uint32_t    asic_id;
-+	uint16_t    flags;
-+	uint16_t    entry_size;
-+	uint32_t    total_size;
-+	uint32_t    num_of_entries;
-+	uint8_t     type;
-+	uint8_t     mode;
-+	uint8_t     filler_0[2];
-+	uint32_t    filler_1[2];
-+};
-+
-+typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
-+
-+struct SMU7_Discrete_Log_Cntl {
-+	uint8_t             Enabled;
-+	uint8_t             Type;
-+	uint8_t             padding[2];
-+	uint32_t            BufferSize;
-+	uint32_t            SamplesLogged;
-+	uint32_t            SampleSize;
-+	uint32_t            AddrL;
-+	uint32_t            AddrH;
-+};
-+
-+typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
-+
-+#define CAC_ACC_NW_NUM_OF_SIGNALS 87
-+
-+struct SMU7_Discrete_Cac_Collection_Table {
-+	uint32_t temperature;
-+	uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
-+};
-+
-+typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
-+
-+struct SMU7_Discrete_Cac_Verification_Table {
-+	uint32_t VddcTotalPower;
-+	uint32_t VddcLeakagePower;
-+	uint32_t VddcConstantPower;
-+	uint32_t VddcGfxDynamicPower;
-+	uint32_t VddcUvdDynamicPower;
-+	uint32_t VddcVceDynamicPower;
-+	uint32_t VddcAcpDynamicPower;
-+	uint32_t VddcPcieDynamicPower;
-+	uint32_t VddcDceDynamicPower;
-+	uint32_t VddcCurrent;
-+	uint32_t VddcVoltage;
-+	uint32_t VddciTotalPower;
-+	uint32_t VddciLeakagePower;
-+	uint32_t VddciConstantPower;
-+	uint32_t VddciDynamicPower;
-+	uint32_t Vddr1TotalPower;
-+	uint32_t Vddr1LeakagePower;
-+	uint32_t Vddr1ConstantPower;
-+	uint32_t Vddr1DynamicPower;
-+	uint32_t spare[4];
-+	uint32_t temperature;
-+};
-+
-+typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
-+
-+struct SMU7_Discrete_Pm_Status_Table {
-+	/* Thermal entities */
-+	int32_t T_meas_max;
-+	int32_t T_meas_acc;
-+	int32_t T_calc_max;
-+	int32_t T_calc_acc;
-+	uint32_t P_scalar_acc;
-+	uint32_t P_calc_max;
-+	uint32_t P_calc_acc;
-+
-+	/*Voltage domains */
-+	uint32_t I_calc_max;
-+	uint32_t I_calc_acc;
-+	uint32_t I_calc_acc_vddci;
-+	uint32_t V_calc_noload_acc;
-+	uint32_t V_calc_load_acc;
-+	uint32_t V_calc_noload_acc_vddci;
-+	uint32_t P_meas_acc;
-+	uint32_t V_meas_noload_acc;
-+	uint32_t V_meas_load_acc;
-+	uint32_t I_meas_acc;
-+	uint32_t P_meas_acc_vddci;
-+	uint32_t V_meas_noload_acc_vddci;
-+	uint32_t V_meas_load_acc_vddci;
-+	uint32_t I_meas_acc_vddci;
-+
-+	/*Frequency */
-+	uint16_t Sclk_dpm_residency[8];
-+	uint16_t Uvd_dpm_residency[8];
-+	uint16_t Vce_dpm_residency[8];
-+	uint16_t Mclk_dpm_residency[4];
-+
-+	/*Chip */
-+	uint32_t P_vddci_acc;
-+	uint32_t P_vddr1_acc;
-+	uint32_t P_nte1_acc;
-+	uint32_t PkgPwr_max;
-+	uint32_t PkgPwr_acc;
-+	uint32_t MclkSwitchingTime_max;
-+	uint32_t MclkSwitchingTime_acc;
-+	uint32_t FanPwm_acc;
-+	uint32_t FanRpm_acc;
-+
-+	uint32_t AccCnt;
-+};
-+
-+typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
-+
-+/*FIXME THESE NEED TO BE UPDATED */
-+#define SMU7_SCLK_CAC 0x561
-+#define SMU7_MCLK_CAC 0xF9
-+#define SMU7_VCLK_CAC 0x2DE
-+#define SMU7_DCLK_CAC 0x2DE
-+#define SMU7_ECLK_CAC 0x25E
-+#define SMU7_ACLK_CAC 0x25E
-+#define SMU7_SAMCLK_CAC 0x25E
-+#define SMU7_DISPCLK_CAC 0x100
-+#define SMU7_CAC_CONSTANT 0x2EE3430
-+#define SMU7_CAC_CONSTANT_SHIFT 18
-+
-+#define SMU7_VDDCI_MCLK_CONST        1765
-+#define SMU7_VDDCI_MCLK_CONST_SHIFT  16
-+#define SMU7_VDDCI_VDDCI_CONST       50958
-+#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
-+#define SMU7_VDDCI_CONST             11781
-+
-+#define SMU7_12C_VDDCI_MCLK_CONST        1623
-+#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT  15
-+#define SMU7_12C_VDDCI_VDDCI_CONST       40088
-+#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
-+#define SMU7_12C_VDDCI_CONST             20856
-+
-+#define SMU7_VDDCI_STROBE_PWR        1331
-+
-+#define SMU7_VDDR1_CONST            693
-+#define SMU7_VDDR1_CAC_WEIGHT       20
-+#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
-+#define SMU7_VDDR1_STROBE_PWR       512
-+
-+#define SMU7_AREA_COEFF_UVD 0xA78
-+#define SMU7_AREA_COEFF_VCE 0x190A
-+#define SMU7_AREA_COEFF_ACP 0x22D1
-+#define SMU7_AREA_COEFF_SAMU 0x534
-+
-+/*ThermOutMode values */
-+#define SMU7_THERM_OUT_MODE_DISABLE       0x0
-+#define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
-+#define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
-+
-+#if !defined(SMC_MICROCODE)
-+#pragma pack(pop)
-+#endif
-+
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h
-new file mode 100644
-index 0000000..6363129
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h
-@@ -0,0 +1,420 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef TONGA_PP_SMC_H
-+#define TONGA_PP_SMC_H
-+
-+#pragma pack(push, 1)
-+
-+#define PPSMC_SWSTATE_FLAG_DC				0x01
-+#define PPSMC_SWSTATE_FLAG_UVD				0x02
-+#define PPSMC_SWSTATE_FLAG_VCE				0x04
-+#define PPSMC_SWSTATE_FLAG_PCIE_X1			0x08
-+
-+#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
-+#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
-+#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
-+
-+#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
-+#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
-+#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
-+
-+#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
-+
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
-+#define PPSMC_SYSTEMFLAG_12CHANNEL                      0x40
-+
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
-+#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH      0x10
-+#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17               0x20
-+#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17                  0x40
-+
-+/* Defines for DPM 2.0 */
-+#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
-+#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
-+#define PPSMC_DPM2FLAGS_OCP                             0x04
-+
-+/* Defines for display watermark level */
-+
-+#define PPSMC_DISPLAY_WATERMARK_LOW                     0
-+#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
-+
-+/* In the HW performance level's state flags:*/
-+#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
-+#define PPSMC_STATEFLAG_POWERBOOST         0x02
-+#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
-+#define PPSMC_STATEFLAG_POWERSHIFT         0x08
-+#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
-+#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
-+#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
-+
-+/* Fan control algorithm:*/
-+#define FDO_MODE_HARDWARE 0
-+#define FDO_MODE_PIECE_WISE_LINEAR 1
-+
-+enum FAN_CONTROL {
-+	FAN_CONTROL_FUZZY,
-+	FAN_CONTROL_TABLE
-+};
-+
-+/* Return codes for driver to SMC communication.*/
-+
-+#define PPSMC_Result_OK             ((uint16_t)0x01)
-+#define PPSMC_Result_NoMore         ((uint16_t)0x02)
-+#define PPSMC_Result_NotNow         ((uint16_t)0x03)
-+
-+#define PPSMC_Result_Failed         ((uint16_t)0xFF)
-+#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
-+#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
-+
-+typedef uint16_t PPSMC_Result;
-+
-+#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
-+
-+
-+#define PPSMC_MSG_Halt                      ((uint16_t)0x10)
-+#define PPSMC_MSG_Resume                    ((uint16_t)0x11)
-+#define PPSMC_MSG_EnableDPMLevel            ((uint16_t)0x12)
-+#define PPSMC_MSG_ZeroLevelsDisabled        ((uint16_t)0x13)
-+#define PPSMC_MSG_OneLevelsDisabled         ((uint16_t)0x14)
-+#define PPSMC_MSG_TwoLevelsDisabled         ((uint16_t)0x15)
-+#define PPSMC_MSG_EnableThermalInterrupt    ((uint16_t)0x16)
-+#define PPSMC_MSG_RunningOnAC               ((uint16_t)0x17)
-+#define PPSMC_MSG_LevelUp                   ((uint16_t)0x18)
-+#define PPSMC_MSG_LevelDown                 ((uint16_t)0x19)
-+#define PPSMC_MSG_ResetDPMCounters          ((uint16_t)0x1a)
-+#define PPSMC_MSG_SwitchToSwState           ((uint16_t)0x20)
-+
-+#define PPSMC_MSG_SwitchToSwStateLast       ((uint16_t)0x3f)
-+#define PPSMC_MSG_SwitchToInitialState      ((uint16_t)0x40)
-+#define PPSMC_MSG_NoForcedLevel             ((uint16_t)0x41)
-+#define PPSMC_MSG_ForceHigh                 ((uint16_t)0x42)
-+#define PPSMC_MSG_ForceMediumOrHigh         ((uint16_t)0x43)
-+
-+#define PPSMC_MSG_SwitchToMinimumPower      ((uint16_t)0x51)
-+#define PPSMC_MSG_ResumeFromMinimumPower    ((uint16_t)0x52)
-+#define PPSMC_MSG_EnableCac                 ((uint16_t)0x53)
-+#define PPSMC_MSG_DisableCac                ((uint16_t)0x54)
-+#define PPSMC_DPMStateHistoryStart          ((uint16_t)0x55)
-+#define PPSMC_DPMStateHistoryStop           ((uint16_t)0x56)
-+#define PPSMC_CACHistoryStart               ((uint16_t)0x57)
-+#define PPSMC_CACHistoryStop                ((uint16_t)0x58)
-+#define PPSMC_TDPClampingActive             ((uint16_t)0x59)
-+#define PPSMC_TDPClampingInactive           ((uint16_t)0x5A)
-+#define PPSMC_StartFanControl               ((uint16_t)0x5B)
-+#define PPSMC_StopFanControl                ((uint16_t)0x5C)
-+#define PPSMC_NoDisplay                     ((uint16_t)0x5D)
-+#define PPSMC_HasDisplay                    ((uint16_t)0x5E)
-+#define PPSMC_MSG_UVDPowerOFF               ((uint16_t)0x60)
-+#define PPSMC_MSG_UVDPowerON                ((uint16_t)0x61)
-+#define PPSMC_MSG_EnableULV                 ((uint16_t)0x62)
-+#define PPSMC_MSG_DisableULV                ((uint16_t)0x63)
-+#define PPSMC_MSG_EnterULV                  ((uint16_t)0x64)
-+#define PPSMC_MSG_ExitULV                   ((uint16_t)0x65)
-+#define PPSMC_PowerShiftActive              ((uint16_t)0x6A)
-+#define PPSMC_PowerShiftInactive            ((uint16_t)0x6B)
-+#define PPSMC_OCPActive                     ((uint16_t)0x6C)
-+#define PPSMC_OCPInactive                   ((uint16_t)0x6D)
-+#define PPSMC_CACLongTermAvgEnable          ((uint16_t)0x6E)
-+#define PPSMC_CACLongTermAvgDisable         ((uint16_t)0x6F)
-+#define PPSMC_MSG_InferredStateSweep_Start  ((uint16_t)0x70)
-+#define PPSMC_MSG_InferredStateSweep_Stop   ((uint16_t)0x71)
-+#define PPSMC_MSG_SwitchToLowestInfState    ((uint16_t)0x72)
-+#define PPSMC_MSG_SwitchToNonInfState       ((uint16_t)0x73)
-+#define PPSMC_MSG_AllStateSweep_Start       ((uint16_t)0x74)
-+#define PPSMC_MSG_AllStateSweep_Stop        ((uint16_t)0x75)
-+#define PPSMC_MSG_SwitchNextLowerInfState   ((uint16_t)0x76)
-+#define PPSMC_MSG_SwitchNextHigherInfState  ((uint16_t)0x77)
-+#define PPSMC_MSG_MclkRetrainingTest        ((uint16_t)0x78)
-+#define PPSMC_MSG_ForceTDPClamping          ((uint16_t)0x79)
-+#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint16_t)0x7A)
-+#define PPSMC_MSG_CollectCAC_WeightCalib    ((uint16_t)0x7B)
-+#define PPSMC_MSG_CollectCAC_SQonly         ((uint16_t)0x7C)
-+#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
-+
-+#define PPSMC_MSG_ExtremitiesTest_Start     ((uint16_t)0x7E)
-+#define PPSMC_MSG_ExtremitiesTest_Stop      ((uint16_t)0x7F)
-+#define PPSMC_FlushDataCache                ((uint16_t)0x80)
-+#define PPSMC_FlushInstrCache               ((uint16_t)0x81)
-+
-+#define PPSMC_MSG_SetEnabledLevels          ((uint16_t)0x82)
-+#define PPSMC_MSG_SetForcedLevels           ((uint16_t)0x83)
-+
-+#define PPSMC_MSG_ResetToDefaults           ((uint16_t)0x84)
-+
-+#define PPSMC_MSG_SetForcedLevelsAndJump    ((uint16_t)0x85)
-+#define PPSMC_MSG_SetCACHistoryMode         ((uint16_t)0x86)
-+#define PPSMC_MSG_EnableDTE                 ((uint16_t)0x87)
-+#define PPSMC_MSG_DisableDTE                ((uint16_t)0x88)
-+
-+#define PPSMC_MSG_SmcSpaceSetAddress        ((uint16_t)0x89)
-+#define PPSMC_MSG_ChangeNearTDPLimit        ((uint16_t)0x90)
-+#define PPSMC_MSG_ChangeSafePowerLimit      ((uint16_t)0x91)
-+
-+#define PPSMC_MSG_DPMStateSweepStart        ((uint16_t)0x92)
-+#define PPSMC_MSG_DPMStateSweepStop         ((uint16_t)0x93)
-+
-+#define PPSMC_MSG_OVRDDisableSCLKDS         ((uint16_t)0x94)
-+#define PPSMC_MSG_CancelDisableOVRDSCLKDS   ((uint16_t)0x95)
-+#define PPSMC_MSG_ThrottleOVRDSCLKDS        ((uint16_t)0x96)
-+#define PPSMC_MSG_CancelThrottleOVRDSCLKDS  ((uint16_t)0x97)
-+#define PPSMC_MSG_GPIO17					((uint16_t)0x98)
-+
-+#define PPSMC_MSG_API_SetSvi2Volt_Vddc      ((uint16_t)0x99)
-+#define PPSMC_MSG_API_SetSvi2Volt_Vddci     ((uint16_t)0x9A)
-+#define PPSMC_MSG_API_SetSvi2Volt_Mvdd      ((uint16_t)0x9B)
-+#define PPSMC_MSG_API_GetSvi2Volt_Vddc      ((uint16_t)0x9C)
-+#define PPSMC_MSG_API_GetSvi2Volt_Vddci     ((uint16_t)0x9D)
-+#define PPSMC_MSG_API_GetSvi2Volt_Mvdd      ((uint16_t)0x9E)
-+
-+#define PPSMC_MSG_BREAK                     ((uint16_t)0xF8)
-+
-+/* Trinity Specific Messages*/
-+#define PPSMC_MSG_Test                      ((uint16_t) 0x100)
-+#define PPSMC_MSG_DPM_Voltage_Pwrmgt        ((uint16_t) 0x101)
-+#define PPSMC_MSG_DPM_Config                ((uint16_t) 0x102)
-+#define PPSMC_MSG_PM_Controller_Start       ((uint16_t) 0x103)
-+#define PPSMC_MSG_DPM_ForceState            ((uint16_t) 0x104)
-+#define PPSMC_MSG_PG_PowerDownSIMD          ((uint16_t) 0x105)
-+#define PPSMC_MSG_PG_PowerUpSIMD            ((uint16_t) 0x106)
-+#define PPSMC_MSG_PM_Controller_Stop        ((uint16_t) 0x107)
-+#define PPSMC_MSG_PG_SIMD_Config            ((uint16_t) 0x108)
-+#define PPSMC_MSG_Voltage_Cntl_Enable       ((uint16_t) 0x109)
-+#define PPSMC_MSG_Thermal_Cntl_Enable       ((uint16_t) 0x10a)
-+#define PPSMC_MSG_Reset_Service             ((uint16_t) 0x10b)
-+#define PPSMC_MSG_VCEPowerOFF               ((uint16_t) 0x10e)
-+#define PPSMC_MSG_VCEPowerON                ((uint16_t) 0x10f)
-+#define PPSMC_MSG_DPM_Disable_VCE_HS        ((uint16_t) 0x110)
-+#define PPSMC_MSG_DPM_Enable_VCE_HS         ((uint16_t) 0x111)
-+#define PPSMC_MSG_DPM_N_LevelsDisabled      ((uint16_t) 0x112)
-+#define PPSMC_MSG_DCEPowerOFF               ((uint16_t) 0x113)
-+#define PPSMC_MSG_DCEPowerON                ((uint16_t) 0x114)
-+#define PPSMC_MSG_PCIE_DDIPowerDown         ((uint16_t) 0x117)
-+#define PPSMC_MSG_PCIE_DDIPowerUp           ((uint16_t) 0x118)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerDown  ((uint16_t) 0x119)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerUp    ((uint16_t) 0x11a)
-+#define PPSMC_MSG_SYSPLLPowerOff            ((uint16_t) 0x11b)
-+#define PPSMC_MSG_SYSPLLPowerOn             ((uint16_t) 0x11c)
-+#define PPSMC_MSG_DCE_RemoveVoltageAdjustment   ((uint16_t) 0x11d)
-+#define PPSMC_MSG_DCE_AllowVoltageAdjustment    ((uint16_t) 0x11e)
-+#define PPSMC_MSG_DISPLAYPHYStatusNotify    ((uint16_t) 0x11f)
-+#define PPSMC_MSG_EnableBAPM                ((uint16_t) 0x120)
-+#define PPSMC_MSG_DisableBAPM               ((uint16_t) 0x121)
-+#define PPSMC_MSG_PCIE_PHYPowerDown         ((uint16_t) 0x122)
-+#define PPSMC_MSG_PCIE_PHYPowerUp           ((uint16_t) 0x123)
-+#define PPSMC_MSG_UVD_DPM_Config            ((uint16_t) 0x124)
-+#define PPSMC_MSG_Spmi_Enable               ((uint16_t) 0x122)
-+#define PPSMC_MSG_Spmi_Timer                ((uint16_t) 0x123)
-+#define PPSMC_MSG_LCLK_DPM_Config           ((uint16_t) 0x124)
-+#define PPSMC_MSG_NBDPM_Config             ((uint16_t) 0x125)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerDown           ((uint16_t) 0x126)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerUp             ((uint16_t) 0x127)
-+#define PPSMC_MSG_MCLKDPM_Config                ((uint16_t) 0x128)
-+
-+#define PPSMC_MSG_UVDDPM_Config               ((uint16_t) 0x129)
-+#define PPSMC_MSG_VCEDPM_Config               ((uint16_t) 0x12A)
-+#define PPSMC_MSG_ACPDPM_Config               ((uint16_t) 0x12B)
-+#define PPSMC_MSG_SAMUDPM_Config              ((uint16_t) 0x12C)
-+#define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
-+#define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
-+#define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
-+#define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
-+#define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
-+#define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
-+#define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
-+#define PPSMC_MSG_SetTDPLimit                 ((uint16_t) 0x134)
-+#define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
-+#define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
-+#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
-+#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
-+#define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
-+#define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
-+#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0x13b)
-+#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0x13c)
-+#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
-+#define PPSMC_MSG_IOMMUPowerOFF               ((uint16_t) 0x13e)
-+#define PPSMC_MSG_IOMMUPowerON                ((uint16_t) 0x13f)
-+#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
-+#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
-+#define PPSMC_MSG_NBDPM_ForceNominal          ((uint16_t) 0x142)
-+#define PPSMC_MSG_NBDPM_ForcePerformance      ((uint16_t) 0x143)
-+#define PPSMC_MSG_NBDPM_UnForce               ((uint16_t) 0x144)
-+#define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
-+#define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
-+#define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
-+#define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
-+#define PPSMC_MSG_EnableACDCGPIOInterrupt     ((uint16_t) 0x149)
-+#define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
-+#define PPSMC_MSG_SwitchToAC                  ((uint16_t) 0x14b)
-+
-+#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0x14c)
-+#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x14d)
-+
-+#define PPSMC_MSG_DPM_Enable                  ((uint16_t)0x14e)
-+#define PPSMC_MSG_DPM_Disable                 ((uint16_t)0x14f)
-+#define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t)0x150)
-+#define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t)0x151)
-+#define PPSMC_MSG_LCLKDPM_Enable              ((uint16_t)0x152)
-+#define PPSMC_MSG_LCLKDPM_Disable             ((uint16_t)0x153)
-+#define PPSMC_MSG_UVDDPM_Enable               ((uint16_t)0x154)
-+#define PPSMC_MSG_UVDDPM_Disable              ((uint16_t)0x155)
-+#define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t)0x156)
-+#define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t)0x157)
-+#define PPSMC_MSG_ACPDPM_Enable               ((uint16_t)0x158)
-+#define PPSMC_MSG_ACPDPM_Disable              ((uint16_t)0x159)
-+#define PPSMC_MSG_VCEDPM_Enable               ((uint16_t)0x15a)
-+#define PPSMC_MSG_VCEDPM_Disable              ((uint16_t)0x15b)
-+#define PPSMC_MSG_LCLKDPM_SetEnabledMask      ((uint16_t)0x15c)
-+
-+#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
-+#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
-+#define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
-+#define PPSMC_MSG_MCLKDPM_GetEnabledMask      ((uint16_t) 0x160)
-+#define PPSMC_MSG_LCLKDPM_GetEnabledMask      ((uint16_t) 0x161)
-+#define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
-+#define PPSMC_MSG_UVDDPM_GetEnabledMask       ((uint16_t) 0x163)
-+#define PPSMC_MSG_SAMUDPM_GetEnabledMask      ((uint16_t) 0x164)
-+#define PPSMC_MSG_ACPDPM_GetEnabledMask       ((uint16_t) 0x165)
-+#define PPSMC_MSG_VCEDPM_GetEnabledMask       ((uint16_t) 0x166)
-+#define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
-+#define PPSMC_MSG_PCIeDPM_GetEnabledMask      ((uint16_t) 0x168)
-+#define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
-+#define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
-+#define PPSMC_MSG_DPM_AutoRotate_Mode         ((uint16_t) 0x16b)
-+#define PPSMC_MSG_DISPCLK_FROM_FCH            ((uint16_t)0x16c)
-+#define PPSMC_MSG_DISPCLK_FROM_DFS            ((uint16_t)0x16d)
-+#define PPSMC_MSG_DPREFCLK_FROM_FCH           ((uint16_t)0x16e)
-+#define PPSMC_MSG_DPREFCLK_FROM_DFS           ((uint16_t)0x16f)
-+#define PPSMC_MSG_PmStatusLogStart            ((uint16_t)0x170)
-+#define PPSMC_MSG_PmStatusLogSample           ((uint16_t)0x171)
-+#define PPSMC_MSG_SCLK_AutoDPM_ON             ((uint16_t) 0x172)
-+#define PPSMC_MSG_MCLK_AutoDPM_ON             ((uint16_t) 0x173)
-+#define PPSMC_MSG_LCLK_AutoDPM_ON             ((uint16_t) 0x174)
-+#define PPSMC_MSG_UVD_AutoDPM_ON              ((uint16_t) 0x175)
-+#define PPSMC_MSG_SAMU_AutoDPM_ON             ((uint16_t) 0x176)
-+#define PPSMC_MSG_ACP_AutoDPM_ON              ((uint16_t) 0x177)
-+#define PPSMC_MSG_VCE_AutoDPM_ON              ((uint16_t) 0x178)
-+#define PPSMC_MSG_PCIe_AutoDPM_ON             ((uint16_t) 0x179)
-+#define PPSMC_MSG_MASTER_AutoDPM_ON           ((uint16_t) 0x17a)
-+#define PPSMC_MSG_MASTER_AutoDPM_OFF          ((uint16_t) 0x17b)
-+#define PPSMC_MSG_DYNAMICDISPPHYPOWER         ((uint16_t) 0x17c)
-+#define PPSMC_MSG_CAC_COLLECTION_ON           ((uint16_t) 0x17d)
-+#define PPSMC_MSG_CAC_COLLECTION_OFF          ((uint16_t) 0x17e)
-+#define PPSMC_MSG_CAC_CORRELATION_ON          ((uint16_t) 0x17f)
-+#define PPSMC_MSG_CAC_CORRELATION_OFF         ((uint16_t) 0x180)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON        ((uint16_t) 0x181)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF       ((uint16_t) 0x182)
-+#define PPSMC_MSG_UVD_HANDSHAKE_OFF           ((uint16_t) 0x183)
-+#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT     ((uint16_t) 0x184)
-+#define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
-+#define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
-+#define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
-+#define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
-+#define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
-+#define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
-+#define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
-+#define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
-+#define PPSMC_MSG_START_DRAM_LOGGING          ((uint16_t) 0x18D)
-+#define PPSMC_MSG_STOP_DRAM_LOGGING           ((uint16_t) 0x18E)
-+#define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
-+#define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
-+#define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
-+#define PPSMC_MSG_DisableACDCGPIOInterrupt    ((uint16_t) 0x192)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddc       ((uint16_t) 0x193)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddci      ((uint16_t) 0x194)
-+#define PPSMC_MSG_SetVidOffset_1              ((uint16_t) 0x195)
-+#define PPSMC_MSG_SetVidOffset_2              ((uint16_t) 0x207)
-+#define PPSMC_MSG_GetVidOffset_1              ((uint16_t) 0x196)
-+#define PPSMC_MSG_GetVidOffset_2              ((uint16_t) 0x208)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable    ((uint16_t) 0x197)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable	  ((uint16_t) 0x198)
-+#define PPSMC_MSG_SetTjMax                    ((uint16_t) 0x199)
-+#define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
-+
-+#define PPSMC_MSG_WaitForMclkSwitchFinish	  ((uint16_t) 0x19B)
-+#define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
-+#define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
-+#define PPSMC_MSG_Enable_PCC                  ((uint16_t) 0x19E)
-+#define PPSMC_MSG_Disable_PCC                 ((uint16_t) 0x19F)
-+
-+#define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
-+#define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
-+#define PPSMC_MSG_API_GetSclkBusy             ((uint16_t) 0x202)
-+#define PPSMC_MSG_API_GetMclkBusy             ((uint16_t) 0x203)
-+#define PPSMC_MSG_API_GetAsicPower            ((uint16_t) 0x204)
-+#define PPSMC_MSG_SetFanRpmMax                ((uint16_t) 0x205)
-+#define PPSMC_MSG_SetFanSclkTarget            ((uint16_t) 0x206)
-+#define PPSMC_MSG_SetFanMinPwm                ((uint16_t) 0x209)
-+#define PPSMC_MSG_SetFanTemperatureTarget     ((uint16_t) 0x20A)
-+
-+#define PPSMC_MSG_BACO_StartMonitor           ((uint16_t) 0x240)
-+#define PPSMC_MSG_BACO_Cancel                 ((uint16_t) 0x241)
-+#define PPSMC_MSG_EnableVddGfx                ((uint16_t) 0x242)
-+#define PPSMC_MSG_DisableVddGfx               ((uint16_t) 0x243)
-+#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x244)
-+#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x245)
-+#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x246)
-+
-+#define PPSMC_MSG_DRV_DRAM_ADDR_HI			  ((uint16_t) 0x250)
-+#define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
-+#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
-+#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x255)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI      ((uint16_t) 0x256)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO      ((uint16_t) 0x257)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI          ((uint16_t) 0x258)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO          ((uint16_t) 0x259)
-+#define PPSMC_MSG_LoadVBios                   ((uint16_t) 0x25A)
-+#define PPSMC_MSG_GetUcodeVersion             ((uint16_t) 0x25B)
-+#define DMCUSMC_MSG_PSREntry                  ((uint16_t) 0x25C)
-+#define DMCUSMC_MSG_PSRExit                   ((uint16_t) 0x25D)
-+#define PPSMC_MSG_EnableClockGatingFeature    ((uint16_t) 0x260)
-+#define PPSMC_MSG_DisableClockGatingFeature   ((uint16_t) 0x261)
-+#define PPSMC_MSG_IsDeviceRunning             ((uint16_t) 0x262)
-+#define PPSMC_MSG_LoadMetaData                ((uint16_t) 0x263)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Enable  ((uint16_t) 0x264)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
-+#define PPSMC_MSG_GetTelemetry1Slope          ((uint16_t) 0x266)
-+#define PPSMC_MSG_GetTelemetry1Offset         ((uint16_t) 0x267)
-+#define PPSMC_MSG_GetTelemetry2Slope          ((uint16_t) 0x268)
-+#define PPSMC_MSG_GetTelemetry2Offset         ((uint16_t) 0x269)
-+
-+typedef uint16_t PPSMC_Msg;
-+
-+/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
-+#define PPSMC_EVENT_STATUS_THERMAL          0x00000001
-+#define PPSMC_EVENT_STATUS_REGULATORHOT     0x00000002
-+#define PPSMC_EVENT_STATUS_DC               0x00000004
-+#define PPSMC_EVENT_STATUS_GPIO17           0x00000008
-+
-+
-+#pragma pack(pop)
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0053-drm-amd-powerplay-Add-Tonga-SMU-support.patch b/common/recipes-kernel/linux/files/0053-drm-amd-powerplay-Add-Tonga-SMU-support.patch
deleted file mode 100644
index 08050bd3..00000000
--- a/common/recipes-kernel/linux/files/0053-drm-amd-powerplay-Add-Tonga-SMU-support.patch
+++ /dev/null
@@ -1,998 +0,0 @@
-From 00027dc4d190bcae17c67d8b476f22926fb2591a Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Wed, 22 Jul 2015 11:29:58 +0800
-Subject: [PATCH 0053/1110] drm/amd/powerplay: Add Tonga SMU support
-
-The SMU manager handles firmware loading for other IP
-blocks (GFX, SDMA, etc.).  This implements it for Tonga.
-
-v3: delete peci sub-module
-v2: use cgs interface directly
-
-Signed-off-by: Young Yang <Young.Yang@amd.com>
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/pp_debug.h       |  40 +
- drivers/gpu/drm/amd/powerplay/smumgr/Makefile      |   2 +-
- drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |   9 +-
- .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    | 819 +++++++++++++++++++++
- .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h    |  53 ++
- 5 files changed, 921 insertions(+), 2 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-new file mode 100644
-index 0000000..65ef547
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-@@ -0,0 +1,40 @@
-+
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef PP_DEBUG_H
-+#define PP_DEBUG_H
-+
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+
-+#define PP_ASSERT_WITH_CODE(cond, msg, code)	\
-+	do {					\
-+		if (!(cond)) {			\
-+			printk(msg);	\
-+			code;			\
-+		}				\
-+	} while (0)
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-index 9219940..0e3348d 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'smu manager' sub-component of powerplay.
- # It provides the smu management services for the driver.
- 
--SMU_MGR = smumgr.o cz_smumgr.o
-+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o
- 
- AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-index 9ff5d33..a386ca8 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-@@ -28,6 +28,7 @@
- #include "cgs_common.h"
- #include "linux/delay.h"
- #include "cz_smumgr.h"
-+#include "tonga_smumgr.h"
- 
- int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -53,7 +54,13 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		cz_smum_init(smumgr);
- 		break;
- 	case AMD_FAMILY_VI:
--		/* TODO */
-+		switch (smumgr->chip_id) {
-+		case CHIP_TONGA:
-+			tonga_smum_init(smumgr);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
- 		break;
- 	default:
- 		kfree(smumgr);
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-new file mode 100644
-index 0000000..62ff760
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-@@ -0,0 +1,819 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/gfp.h>
-+
-+#include "smumgr.h"
-+#include "tonga_smumgr.h"
-+#include "pp_debug.h"
-+#include "smu_ucode_xfer_vi.h"
-+#include "tonga_ppsmc.h"
-+#include "smu/smu_7_1_2_d.h"
-+#include "smu/smu_7_1_2_sh_mask.h"
-+#include "cgs_common.h"
-+
-+#define TONGA_SMC_SIZE			0x20000
-+#define BUFFER_SIZE			80000
-+#define MAX_STRING_SIZE			15
-+#define BUFFER_SIZETWO              131072 /*128 *1024*/
-+
-+/**
-+* Set the address for reading/writing the SMC SRAM space.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smcAddress the address in the SMC RAM to access.
-+*/
-+static int tonga_set_smc_sram_address(struct pp_smumgr *smumgr,
-+				uint32_t smcAddress, uint32_t limit)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+	PP_ASSERT_WITH_CODE((0 == (3 & smcAddress)),
-+		"SMC address must be 4 byte aligned.",
-+		return -1;);
-+
-+	PP_ASSERT_WITH_CODE((limit > (smcAddress + 3)),
-+		"SMC address is beyond the SMC RAM area.",
-+		return -1;);
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smcAddress);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
-+
-+	return 0;
-+}
-+
-+/**
-+* Copy bytes from an array into the SMC RAM space.
-+*
-+* @param    smumgr  the address of the powerplay SMU manager.
-+* @param    smcStartAddress the start address in the SMC RAM to copy bytes to.
-+* @param    src the byte array to copy the bytes from.
-+* @param    byteCount the number of bytes to copy.
-+*/
-+int tonga_copy_bytes_to_smc(struct pp_smumgr *smumgr,
-+		uint32_t smcStartAddress, const uint8_t *src,
-+		uint32_t byteCount, uint32_t limit)
-+{
-+	uint32_t addr;
-+	uint32_t data, orig_data;
-+	int result = 0;
-+	uint32_t extra_shift;
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+	PP_ASSERT_WITH_CODE((0 == (3 & smcStartAddress)),
-+		"SMC address must be 4 byte aligned.",
-+		return 0;);
-+
-+	PP_ASSERT_WITH_CODE((limit > (smcStartAddress + byteCount)),
-+		"SMC address is beyond the SMC RAM area.",
-+		return 0;);
-+
-+	addr = smcStartAddress;
-+
-+	while (byteCount >= 4) {
-+		/*
-+		 * Bytes are written into the
-+		 * SMC address space with the MSB first
-+		 */
-+		data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
-+
-+		result = tonga_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (result)
-+			goto out;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-+
-+		src += 4;
-+		byteCount -= 4;
-+		addr += 4;
-+	}
-+
-+	if (0 != byteCount) {
-+		/* Now write odd bytes left, do a read modify write cycle */
-+		data = 0;
-+
-+		result = tonga_set_smc_sram_address(smumgr, addr, limit);
-+		if (result)
-+			goto out;
-+
-+		orig_data = cgs_read_register(smumgr->device,
-+							mmSMC_IND_DATA_0);
-+		extra_shift = 8 * (4 - byteCount);
-+
-+		while (byteCount > 0) {
-+			data = (data << 8) + *src++;
-+			byteCount--;
-+		}
-+
-+		data <<= extra_shift;
-+		data |= (orig_data & ~((~0UL) << extra_shift));
-+
-+		result = tonga_set_smc_sram_address(smumgr, addr, limit);
-+		if (result)
-+			goto out;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-+	}
-+
-+out:
-+	return result;
-+}
-+
-+
-+int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
-+{
-+	static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
-+
-+	tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Return if the SMC is currently running.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+*/
-+static int tonga_is_smc_ram_running(struct pp_smumgr *smumgr)
-+{
-+	return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-+			&& (0x20100 <= cgs_read_ind_register(smumgr->device,
-+					CGS_IND_REG__SMC, ixSMC_PC_C)));
-+}
-+
-+static int tonga_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	return 0;
-+}
-+
-+/**
-+* Send a message to the SMC, and wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	if (!tonga_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PP_ASSERT_WITH_CODE(
-+		1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
-+		"Failed to send Previous Message.",
-+		return 1);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PP_ASSERT_WITH_CODE(
-+		1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
-+		"Failed to send Message.",
-+		return 1);
-+
-+	return 0;
-+}
-+
-+/*
-+* Send a message to the SMC, and do not wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+static int tonga_send_msg_to_smc_without_waiting
-+				(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PP_ASSERT_WITH_CODE(
-+		1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
-+		"Failed to send Previous Message.",
-+		return 0);
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	return 0;
-+}
-+
-+/*
-+* Send a message to the SMC with parameter
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+static int tonga_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+				uint16_t msg, uint32_t parameter)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	if (!tonga_is_smc_ram_running(smumgr))
-+		return PPSMC_Result_Failed;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+
-+	return tonga_send_msg_to_smc(smumgr, msg);
-+}
-+
-+/*
-+* Send a message to the SMC with parameter, do not wait for response
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+static int tonga_send_msg_to_smc_with_parameter_without_waiting(
-+			struct pp_smumgr *smumgr,
-+			uint16_t msg, uint32_t parameter)
-+{
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+
-+	return tonga_send_msg_to_smc_without_waiting(smumgr, msg);
-+}
-+
-+/*
-+ * Read a 32bit value from the SMC SRAM space.
-+ * ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+ * @param    smumgr  the address of the powerplay hardware manager.
-+ * @param    smcAddress the address in the SMC RAM to access.
-+ * @param    value and output parameter for the data read from the SMC SRAM.
-+ */
-+int tonga_read_smc_sram_dword(struct pp_smumgr *smumgr,
-+					uint32_t smcAddress, uint32_t *value,
-+					uint32_t limit)
-+{
-+	int result;
-+
-+	result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
-+
-+	if (0 != result)
-+		return result;
-+
-+	*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Write a 32bit value to the SMC SRAM space.
-+ * ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+ * @param    smumgr  the address of the powerplay hardware manager.
-+ * @param    smcAddress the address in the SMC RAM to access.
-+ * @param    value to write to the SMC SRAM.
-+ */
-+int tonga_write_smc_sram_dword(struct pp_smumgr *smumgr,
-+					uint32_t smcAddress, uint32_t value,
-+					uint32_t limit)
-+{
-+	int result;
-+
-+	result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
-+
-+	if (0 != result)
-+		return result;
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, value);
-+
-+	return 0;
-+}
-+
-+static int tonga_smu_fini(struct pp_smumgr *smumgr)
-+{
-+	if (smumgr->backend != NULL) {
-+		kfree(smumgr->backend);
-+		smumgr->backend = NULL;
-+	}
-+	return 0;
-+}
-+
-+static enum cgs_ucode_id tonga_convert_fw_type_to_cgs(uint32_t fw_type)
-+{
-+	enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SMU:
-+		result = CGS_UCODE_ID_SMU;
-+		break;
-+	case UCODE_ID_SDMA0:
-+		result = CGS_UCODE_ID_SDMA0;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = CGS_UCODE_ID_SDMA1;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = CGS_UCODE_ID_CP_CE;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = CGS_UCODE_ID_CP_PFP;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = CGS_UCODE_ID_CP_ME;
-+		break;
-+	case UCODE_ID_CP_MEC:
-+		result = CGS_UCODE_ID_CP_MEC;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+		result = CGS_UCODE_ID_CP_MEC_JT1;
-+		break;
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = CGS_UCODE_ID_CP_MEC_JT2;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = CGS_UCODE_ID_RLC_G;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Convert the PPIRI firmware type to SMU type mask.
-+ * For MEC, we need to check all MEC related type
-+*/
-+static uint16_t tonga_get_mask_for_firmware_type(uint16_t firmwareType)
-+{
-+	uint16_t result = 0;
-+
-+	switch (firmwareType) {
-+	case UCODE_ID_SDMA0:
-+		result = UCODE_ID_SDMA0_MASK;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = UCODE_ID_SDMA1_MASK;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = UCODE_ID_CP_CE_MASK;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = UCODE_ID_CP_PFP_MASK;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = UCODE_ID_CP_ME_MASK;
-+		break;
-+	case UCODE_ID_CP_MEC:
-+	case UCODE_ID_CP_MEC_JT1:
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = UCODE_ID_CP_MEC_MASK;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = UCODE_ID_RLC_G_MASK;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Check if the FW has been loaded,
-+ * SMU will not return if loading has not finished.
-+*/
-+static int tonga_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fwType)
-+{
-+	uint16_t fwMask = tonga_get_mask_for_firmware_type(fwType);
-+
-+	if (0 != SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
-+				SOFT_REGISTERS_TABLE_28, fwMask, fwMask)) {
-+		printk(KERN_ERR "[ powerplay ] check firmware loading failed\n");
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Populate one firmware image to the data structure */
-+static int tonga_populate_single_firmware_entry(struct pp_smumgr *smumgr,
-+				uint16_t firmware_type,
-+				struct SMU_Entry *pentry)
-+{
-+	int result;
-+	struct cgs_firmware_info info = {0};
-+
-+	result = cgs_get_firmware_info(
-+				smumgr->device,
-+				tonga_convert_fw_type_to_cgs(firmware_type),
-+				&info);
-+
-+	if (result == 0) {
-+		pentry->version = 0;
-+		pentry->id = (uint16_t)firmware_type;
-+		pentry->image_addr_high = smu_upper_32_bits(info.mc_addr);
-+		pentry->image_addr_low = smu_lower_32_bits(info.mc_addr);
-+		pentry->meta_data_addr_high = 0;
-+		pentry->meta_data_addr_low = 0;
-+		pentry->data_size_byte = info.image_size;
-+		pentry->num_register_entries = 0;
-+
-+		if (firmware_type == UCODE_ID_RLC_G)
-+			pentry->flags = 1;
-+		else
-+			pentry->flags = 0;
-+	} else {
-+		return result;
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_request_smu_reload_fw(struct pp_smumgr *smumgr)
-+{
-+	struct tonga_smumgr *tonga_smu =
-+		(struct tonga_smumgr *)(smumgr->backend);
-+	uint16_t fw_to_load;
-+	int result = 0;
-+	struct SMU_DRAMData_TOC *toc;
-+	/**
-+	 * First time this gets called during SmuMgr init,
-+	 * we haven't processed SMU header file yet,
-+	 * so Soft Register Start offset is unknown.
-+	 * However, for this case, UcodeLoadStatus is already 0,
-+	 * so we can skip this if the Soft Registers Start offset is 0.
-+	 */
-+	cgs_write_ind_register(smumgr->device,
-+		CGS_IND_REG__SMC, ixSOFT_REGISTERS_TABLE_28, 0);
-+
-+	tonga_send_msg_to_smc_with_parameter(smumgr,
-+		PPSMC_MSG_SMU_DRAM_ADDR_HI,
-+		tonga_smu->smu_buffer.mc_addr_high);
-+	tonga_send_msg_to_smc_with_parameter(smumgr,
-+		PPSMC_MSG_SMU_DRAM_ADDR_LO,
-+		tonga_smu->smu_buffer.mc_addr_low);
-+
-+	toc = (struct SMU_DRAMData_TOC *)tonga_smu->pHeader;
-+	toc->num_entries = 0;
-+	toc->structure_version = 1;
-+
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry(smumgr,
-+		UCODE_ID_RLC_G,
-+		&toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n",
-+		return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry(smumgr,
-+		UCODE_ID_CP_CE,
-+		&toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n",
-+		return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_populate_single_firmware_entry
-+		(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
-+		"Failed to Get Firmware Entry.\n", return -1);
-+
-+	tonga_send_msg_to_smc_with_parameter(smumgr,
-+		PPSMC_MSG_DRV_DRAM_ADDR_HI,
-+		tonga_smu->header_buffer.mc_addr_high);
-+	tonga_send_msg_to_smc_with_parameter(smumgr,
-+		PPSMC_MSG_DRV_DRAM_ADDR_LO,
-+		tonga_smu->header_buffer.mc_addr_low);
-+
-+	fw_to_load = UCODE_ID_RLC_G_MASK
-+			+ UCODE_ID_SDMA0_MASK
-+			+ UCODE_ID_SDMA1_MASK
-+			+ UCODE_ID_CP_CE_MASK
-+			+ UCODE_ID_CP_ME_MASK
-+			+ UCODE_ID_CP_PFP_MASK
-+			+ UCODE_ID_CP_MEC_MASK;
-+
-+	PP_ASSERT_WITH_CODE(
-+		0 == tonga_send_msg_to_smc_with_parameter_without_waiting(
-+		smumgr, PPSMC_MSG_LoadUcodes, fw_to_load),
-+		"Fail to Request SMU Load uCode", return 0);
-+
-+	return result;
-+}
-+
-+static int tonga_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
-+				uint32_t firmwareType)
-+{
-+	return 0;
-+}
-+
-+/**
-+ * Upload the SMC firmware to the SMC microcontroller.
-+ *
-+ * @param    smumgr  the address of the powerplay hardware manager.
-+ * @param    pFirmware the data structure containing the various sections of the firmware.
-+ */
-+static int tonga_smu_upload_firmware_image(struct pp_smumgr *smumgr)
-+{
-+	const uint8_t *src;
-+	uint32_t byte_count;
-+	uint32_t *data;
-+	struct cgs_firmware_info info = {0};
-+
-+	if (smumgr == NULL || smumgr->device == NULL)
-+		return -EINVAL;
-+
-+	cgs_get_firmware_info(smumgr->device,
-+		tonga_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
-+
-+	if (info.image_size & 3) {
-+		printk(KERN_ERR "[ powerplay ] SMC ucode is not 4 bytes aligned\n");
-+		return -EINVAL;
-+	}
-+
-+	if (info.image_size > TONGA_SMC_SIZE) {
-+		printk(KERN_ERR "[ powerplay ] SMC address is beyond the SMC RAM area\n");
-+		return -EINVAL;
-+	}
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, 0x20000);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
-+
-+	byte_count = info.image_size;
-+	src = (const uint8_t *)info.kptr;
-+
-+	data = (uint32_t *)src;
-+	for (; byte_count >= 4; data++, byte_count -= 4)
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data[0]);
-+
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-+
-+	return 0;
-+}
-+
-+static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result;
-+
-+	/* Assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	result = tonga_smu_upload_firmware_image(smumgr);
-+	if (result)
-+		return result;
-+
-+	/* Clear status */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+		ixSMU_STATUS, 0);
-+
-+	/* Enable clock */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	/* De-assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Set SMU Auto Start */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMU_INPUT_DATA, AUTO_START, 1);
-+
-+	/* Clear firmware interrupt enable flag */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+		ixFIRMWARE_FLAGS, 0);
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+		RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
-+
-+	/**
-+	 * Call Test SMU message with 0x20000 offset to trigger SMU start
-+	 */
-+	tonga_send_msg_to_smc_offset(smumgr);
-+
-+	/* Wait for done bit to be set */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+		SMU_STATUS, SMU_DONE, 0);
-+
-+	/* Check pass/failed indicator */
-+	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
-+				CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
-+		printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
-+		return -EINVAL;
-+	}
-+
-+	/* Wait for firmware to initialize */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+		FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return 0;
-+}
-+
-+
-+static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* wait for smc boot up */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+		RCU_UC_EVENTS, boot_seq_done, 0);
-+
-+	/*Clear firmware interrupt enable flag*/
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+		ixFIRMWARE_FLAGS, 0);
-+
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	result = tonga_smu_upload_firmware_image(smumgr);
-+
-+	if (result != 0)
-+		return result;
-+
-+	/* Set smc instruct start point at 0x0 */
-+	tonga_program_jump_on_start(smumgr);
-+
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	/*De-assert reset*/
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for firmware to initialize */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+		FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+static int tonga_start_smu(struct pp_smumgr *smumgr)
-+{
-+	int result;
-+
-+	/* Only start SMC if SMC RAM is not running */
-+	if (!tonga_is_smc_ram_running(smumgr)) {
-+		/*Check if SMU is running in protected mode*/
-+		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMU_FIRMWARE, SMU_MODE)) {
-+			result = tonga_start_in_non_protection_mode(smumgr);
-+			if (result)
-+				return result;
-+		} else {
-+			result = tonga_start_in_protection_mode(smumgr);
-+			if (result)
-+				return result;
-+		}
-+	}
-+
-+	result = tonga_request_smu_reload_fw(smumgr);
-+
-+	return result;
-+}
-+
-+/**
-+ * Write a 32bit value to the SMC SRAM space.
-+ * ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+ * @param    smumgr  the address of the powerplay hardware manager.
-+ * @param    smcAddress the address in the SMC RAM to access.
-+ * @param    value to write to the SMC SRAM.
-+ */
-+static int tonga_smu_init(struct pp_smumgr *smumgr)
-+{
-+	struct tonga_smumgr *tonga_smu;
-+	uint8_t *internal_buf;
-+	uint64_t mc_addr = 0;
-+	/* Allocate memory for backend private data */
-+	tonga_smu = (struct tonga_smumgr *)(smumgr->backend);
-+	tonga_smu->header_buffer.data_size =
-+		((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
-+	tonga_smu->smu_buffer.data_size = 200*4096;
-+
-+	smu_allocate_memory(smumgr->device,
-+		tonga_smu->header_buffer.data_size,
-+		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+		PAGE_SIZE,
-+		&mc_addr,
-+		&tonga_smu->header_buffer.kaddr,
-+		&tonga_smu->header_buffer.handle);
-+
-+	tonga_smu->pHeader = tonga_smu->header_buffer.kaddr;
-+	tonga_smu->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	tonga_smu->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != tonga_smu->pHeader),
-+		"Out of memory.",
-+		kfree(smumgr->backend);
-+		cgs_free_gpu_mem(smumgr->device,
-+		(cgs_handle_t)tonga_smu->header_buffer.handle);
-+		return -1);
-+
-+	smu_allocate_memory(smumgr->device,
-+		tonga_smu->smu_buffer.data_size,
-+		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+		PAGE_SIZE,
-+		&mc_addr,
-+		&tonga_smu->smu_buffer.kaddr,
-+		&tonga_smu->smu_buffer.handle);
-+
-+	internal_buf = tonga_smu->smu_buffer.kaddr;
-+	tonga_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	tonga_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != internal_buf),
-+		"Out of memory.",
-+		kfree(smumgr->backend);
-+		cgs_free_gpu_mem(smumgr->device,
-+		(cgs_handle_t)tonga_smu->smu_buffer.handle);
-+		return -1;);
-+
-+	return 0;
-+}
-+
-+static const struct pp_smumgr_func tonga_smu_funcs = {
-+	.smu_init = &tonga_smu_init,
-+	.smu_fini = &tonga_smu_fini,
-+	.start_smu = &tonga_start_smu,
-+	.check_fw_load_finish = &tonga_check_fw_load_finish,
-+	.request_smu_load_fw = &tonga_request_smu_reload_fw,
-+	.request_smu_load_specific_fw = &tonga_request_smu_load_specific_fw,
-+	.send_msg_to_smc = &tonga_send_msg_to_smc,
-+	.send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter,
-+	.download_pptable_settings = NULL,
-+	.upload_pptable_settings = NULL,
-+};
-+
-+int tonga_smum_init(struct pp_smumgr *smumgr)
-+{
-+	struct tonga_smumgr *tonga_smu = NULL;
-+
-+	tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
-+
-+	if (tonga_smu == NULL)
-+		return -1;
-+
-+	smumgr->backend = tonga_smu;
-+	smumgr->smumgr_funcs = &tonga_smu_funcs;
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
-new file mode 100644
-index 0000000..33c788d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _TONGA_SMUMGR_H_
-+#define _TONGA_SMUMGR_H_
-+
-+struct tonga_buffer_entry {
-+	uint32_t data_size;
-+	uint32_t mc_addr_low;
-+	uint32_t mc_addr_high;
-+	void *kaddr;
-+	unsigned long  handle;
-+};
-+
-+struct tonga_smumgr {
-+	uint8_t *pHeader;
-+	uint8_t *pMecImage;
-+	uint32_t ulSoftRegsStart;
-+
-+	struct tonga_buffer_entry header_buffer;
-+	struct tonga_buffer_entry smu_buffer;
-+};
-+
-+extern int tonga_smum_init(struct pp_smumgr *smumgr);
-+extern int tonga_copy_bytes_to_smc(struct pp_smumgr *smumgr,
-+		uint32_t smcStartAddress, const uint8_t *src,
-+		uint32_t byteCount, uint32_t limit);
-+extern int tonga_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smcAddress,
-+		uint32_t *value, uint32_t limit);
-+extern int tonga_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smcAddress,
-+		uint32_t value, uint32_t limit);
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0054-drm-amd-powerplay-add-Tonga-dpm-support-v3.patch b/common/recipes-kernel/linux/files/0054-drm-amd-powerplay-add-Tonga-dpm-support-v3.patch
deleted file mode 100644
index bce50d08..00000000
--- a/common/recipes-kernel/linux/files/0054-drm-amd-powerplay-add-Tonga-dpm-support-v3.patch
+++ /dev/null
@@ -1,9546 +0,0 @@
-From c01e1ac0d1a1fdd320f91d8f367867f77bddeec6 Mon Sep 17 00:00:00 2001
-From: yanyang1 <young.yang@amd.com>
-Date: Tue, 18 Aug 2015 15:28:32 +0800
-Subject: [PATCH 0054/1110] drm/amd/powerplay: add Tonga dpm support (v3)
-
-This implements DPM for tonga.  DPM handles dynamic
-clock and voltage scaling.
-
-v2: merge all the patches related with tonga dpm
-v3: merge dpm force level fix, cgs display fix, spelling fix
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: yanyang1 <young.yang@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/Makefile             |    5 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |    4 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |   10 +
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h    |  105 +
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c   |  704 +++
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h   |  237 +
- drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h  |   42 +
- drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c  |   64 +
- drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h  |   31 +
- .../drm/amd/powerplay/hwmgr/tonga_dyn_defaults.h   |  107 +
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  | 5714 ++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h  |  427 ++
- .../gpu/drm/amd/powerplay/hwmgr/tonga_powertune.h  |   66 +
- .../gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h    |  406 ++
- .../amd/powerplay/hwmgr/tonga_processpptables.c    | 1129 ++++
- .../amd/powerplay/hwmgr/tonga_processpptables.h    |   35 +
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    |   18 +-
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   90 +
- drivers/gpu/drm/amd/powerplay/inc/pp_debug.h       |    2 +-
- .../gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h  |  100 +
- 20 files changed, 9284 insertions(+), 12 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_dyn_defaults.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
-index 0231021..e195bf5 100644
---- a/drivers/gpu/drm/amd/powerplay/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/Makefile
-@@ -2,7 +2,10 @@
- subdir-ccflags-y += -Iinclude/drm  \
- 		-Idrivers/gpu/drm/amd/powerplay/inc/  \
- 		-Idrivers/gpu/drm/amd/include/asic_reg  \
--		-Idrivers/gpu/drm/amd/include
-+		-Idrivers/gpu/drm/amd/include  \
-+		-Idrivers/gpu/drm/amd/powerplay/smumgr\
-+		-Idrivers/gpu/drm/amd/powerplay/hwmgr \
-+		-Idrivers/gpu/drm/amd/powerplay/eventmgr
- 
- AMD_PP_PATH = ../powerplay
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index 46cc494..fd73d3c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -4,7 +4,9 @@
- 
- HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
- 	       hardwaremanager.o pp_acpi.o cz_hwmgr.o \
--               cz_clockpowergating.o
-+               cz_clockpowergating.o \
-+	       tonga_processpptables.o ppatomctrl.o \
-+               tonga_hwmgr.o 	pppcielanes.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index 5d1ba90..407b2e3 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -28,6 +28,7 @@
- #include "power_state.h"
- #include "hwmgr.h"
- #include "cz_hwmgr.h"
-+#include "tonga_hwmgr.h"
- 
- int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -53,6 +54,15 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 	case AMD_FAMILY_CZ:
- 		cz_hwmgr_init(hwmgr);
- 		break;
-+	case AMD_FAMILY_VI:
-+		switch (hwmgr->chip_id) {
-+		case CHIP_TONGA:
-+			tonga_hwmgr_init(hwmgr);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		break;
- 	default:
- 		return -EINVAL;
- 	}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
-new file mode 100644
-index 0000000..c9e6c2d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef PP_HWMGR_PPT_H
-+#define PP_HWMGR_PPT_H
-+
-+#include "hardwaremanager.h"
-+#include "smumgr.h"
-+#include "atom-types.h"
-+
-+struct phm_ppt_v1_clock_voltage_dependency_record {
-+	uint32_t clk;
-+	uint8_t vddInd;
-+	uint16_t vdd_offset;
-+	uint16_t vddc;
-+	uint16_t vddgfx;
-+	uint16_t vddci;
-+	uint16_t mvdd;
-+	uint8_t phases;
-+	uint8_t cks_enable;
-+	uint8_t cks_voffset;
-+};
-+
-+typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_voltage_dependency_record;
-+
-+struct phm_ppt_v1_clock_voltage_dependency_table {
-+	uint32_t count;                                            /* Number of entries. */
-+	phm_ppt_v1_clock_voltage_dependency_record entries[1];     /* Dynamically allocate count entries. */
-+};
-+
-+typedef struct phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_clock_voltage_dependency_table;
-+
-+
-+/* Multimedia Clock Voltage Dependency records and table */
-+struct phm_ppt_v1_mm_clock_voltage_dependency_record {
-+	uint32_t  dclk;                                              /* UVD D-clock */
-+	uint32_t  vclk;                                              /* UVD V-clock */
-+	uint32_t  eclk;                                              /* VCE clock */
-+	uint32_t  aclk;                                              /* ACP clock */
-+	uint32_t  samclock;                                          /* SAMU clock */
-+	uint8_t	vddcInd;
-+	uint16_t vddgfx_offset;
-+	uint16_t vddc;
-+	uint16_t vddgfx;
-+	uint8_t phases;
-+};
-+typedef struct phm_ppt_v1_mm_clock_voltage_dependency_record phm_ppt_v1_mm_clock_voltage_dependency_record;
-+
-+struct phm_ppt_v1_mm_clock_voltage_dependency_table {
-+	uint32_t count;													/* Number of entries. */
-+	phm_ppt_v1_mm_clock_voltage_dependency_record entries[1];		/* Dynamically allocate count entries. */
-+};
-+typedef struct phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_mm_clock_voltage_dependency_table;
-+
-+struct phm_ppt_v1_voltage_lookup_record {
-+	uint16_t us_calculated;
-+	uint16_t us_vdd;												/* Base voltage */
-+	uint16_t us_cac_low;
-+	uint16_t us_cac_mid;
-+	uint16_t us_cac_high;
-+};
-+typedef struct phm_ppt_v1_voltage_lookup_record phm_ppt_v1_voltage_lookup_record;
-+
-+struct phm_ppt_v1_voltage_lookup_table {
-+	uint32_t count;
-+	phm_ppt_v1_voltage_lookup_record entries[1];    /* Dynamically allocate count entries. */
-+};
-+typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table;
-+
-+/* PCIE records and Table */
-+
-+struct phm_ppt_v1_pcie_record {
-+	uint8_t gen_speed;
-+	uint8_t lane_width;
-+};
-+typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
-+
-+struct phm_ppt_v1_pcie_table {
-+	uint32_t count;                                            /* Number of entries. */
-+	phm_ppt_v1_pcie_record entries[1];                         /* Dynamically allocate count entries. */
-+};
-+typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table;
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-new file mode 100644
-index 0000000..9af2f59
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-@@ -0,0 +1,704 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "cgs_common.h"
-+#include "pp_debug.h"
-+#define MEM_ID_MASK           0xff000000
-+#define MEM_ID_SHIFT          24
-+#define CLOCK_RANGE_MASK      0x00ffffff
-+#define CLOCK_RANGE_SHIFT     0
-+#define LOW_NIBBLE_MASK       0xf
-+#define DATA_EQU_PREV         0
-+#define DATA_FROM_TABLE       4
-+
-+union voltage_object_info {
-+	struct _ATOM_VOLTAGE_OBJECT_INFO v1;
-+	struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
-+	struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
-+};
-+
-+static int atomctrl_retrieve_ac_timing(
-+		uint8_t index,
-+		ATOM_INIT_REG_BLOCK *reg_block,
-+		pp_atomctrl_mc_reg_table *table)
-+{
-+	uint32_t i, j;
-+	uint8_t tmem_id;
-+	ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
-+		((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize));
-+
-+	uint8_t num_ranges = 0;
-+
-+	while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK &&
-+			num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES) {
-+		tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
-+
-+		if (index == tmem_id) {
-+			table->mc_reg_table_entry[num_ranges].mclk_max =
-+				(uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >>
-+						CLOCK_RANGE_SHIFT);
-+
-+			for (i = 0, j = 1; i < table->last; i++) {
-+				if ((table->mc_reg_address[i].uc_pre_reg_data &
-+							LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
-+					table->mc_reg_table_entry[num_ranges].mc_data[i] =
-+						(uint32_t)*((uint32_t *)reg_data + j);
-+					j++;
-+				} else if ((table->mc_reg_address[i].uc_pre_reg_data &
-+							LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
-+					table->mc_reg_table_entry[num_ranges].mc_data[i] =
-+						table->mc_reg_table_entry[num_ranges].mc_data[i-1];
-+				}
-+			}
-+			num_ranges++;
-+		}
-+
-+		reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
-+			((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ;
-+	}
-+
-+	PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),
-+			"Invalid VramInfo table.", return -1);
-+	table->num_entries = num_ranges;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Get memory clock AC timing registers index from VBIOS table
-+ * VBIOS set end of memory clock AC timing registers by ucPreRegDataLength bit6 = 1
-+ * @param    reg_block the address ATOM_INIT_REG_BLOCK
-+ * @param    table the address of MCRegTable
-+ * @return   PP_Result_OK
-+ */
-+static int atomctrl_set_mc_reg_address_table(
-+		ATOM_INIT_REG_BLOCK *reg_block,
-+		pp_atomctrl_mc_reg_table *table)
-+{
-+	uint8_t i = 0;
-+	uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize))
-+			/ sizeof(ATOM_INIT_REG_INDEX_FORMAT));
-+	ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
-+
-+	num_entries--;        /* subtract 1 data end mark entry */
-+
-+	PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE),
-+			"Invalid VramInfo table.", return -1);
-+
-+	/* ucPreRegDataLength bit6 = 1 is the end of memory clock AC timing registers */
-+	while ((!(format->ucPreRegDataLength & ACCESS_PLACEHOLDER)) &&
-+			(i < num_entries)) {
-+		table->mc_reg_address[i].s1 =
-+			(uint16_t)(le16_to_cpu(format->usRegIndex));
-+		table->mc_reg_address[i].uc_pre_reg_data =
-+			format->ucPreRegDataLength;
-+
-+		i++;
-+		format = (ATOM_INIT_REG_INDEX_FORMAT *)
-+			((uint8_t *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
-+	}
-+
-+	table->last = i;
-+	return 0;
-+}
-+
-+
-+int atomctrl_initialize_mc_reg_table(
-+		struct pp_hwmgr *hwmgr,
-+		uint8_t module_index,
-+		pp_atomctrl_mc_reg_table *table)
-+{
-+	ATOM_VRAM_INFO_HEADER_V2_1 *vram_info;
-+	ATOM_INIT_REG_BLOCK *reg_block;
-+	int result = 0;
-+	u8 frev, crev;
-+	u16 size;
-+
-+	vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)
-+		cgs_atom_get_data_table(hwmgr->device,
-+				GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
-+
-+	if (module_index >= vram_info->ucNumOfVRAMModule) {
-+		printk(KERN_ERR "[ powerplay ] Invalid VramInfo table.");
-+		result = -1;
-+	} else if (vram_info->sHeader.ucTableFormatRevision < 2) {
-+		printk(KERN_ERR "[ powerplay ] Invalid VramInfo table.");
-+		result = -1;
-+	}
-+
-+	if (0 == result) {
-+		reg_block = (ATOM_INIT_REG_BLOCK *)
-+			((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset));
-+		result = atomctrl_set_mc_reg_address_table(reg_block, table);
-+	}
-+
-+	if (0 == result) {
-+		result = atomctrl_retrieve_ac_timing(module_index,
-+					reg_block, table);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Set DRAM timings based on engine clock and memory clock.
-+ */
-+int atomctrl_set_engine_dram_timings_rv770(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock,
-+		uint32_t memory_clock)
-+{
-+	SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;
-+
-+	/* They are both in 10KHz Units. */
-+	engine_clock_parameters.ulTargetEngineClock =
-+		(uint32_t) engine_clock & SET_CLOCK_FREQ_MASK;
-+	engine_clock_parameters.ulTargetEngineClock |=
-+		(COMPUTE_ENGINE_PLL_PARAM << 24);
-+
-+	/* in 10 khz units.*/
-+	engine_clock_parameters.sReserved.ulClock =
-+		(uint32_t) memory_clock & SET_CLOCK_FREQ_MASK;
-+	return cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
-+			&engine_clock_parameters);
-+}
-+
-+/**
-+ * Private Function to get the PowerPlay Table Address.
-+ * WARNING: The tabled returned by this function is in
-+ * dynamically allocated memory.
-+ * The caller has to release if by calling kfree.
-+ */
-+static ATOM_VOLTAGE_OBJECT_INFO *get_voltage_info_table(void *device)
-+{
-+	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
-+	u8 frev, crev;
-+	u16 size;
-+	union voltage_object_info *voltage_info;
-+
-+	voltage_info = (union voltage_object_info *)
-+		cgs_atom_get_data_table(device, index,
-+			&size, &frev, &crev);
-+
-+	if (voltage_info != NULL)
-+		return (ATOM_VOLTAGE_OBJECT_INFO *) &(voltage_info->v3);
-+	else
-+		return NULL;
-+}
-+
-+static const ATOM_VOLTAGE_OBJECT_V3 *atomctrl_lookup_voltage_type_v3(
-+		const ATOM_VOLTAGE_OBJECT_INFO_V3_1 * voltage_object_info_table,
-+		uint8_t voltage_type, uint8_t voltage_mode)
-+{
-+	unsigned int size = le16_to_cpu(voltage_object_info_table->sHeader.usStructureSize);
-+	unsigned int offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
-+	uint8_t *start = (uint8_t *)voltage_object_info_table;
-+
-+	while (offset < size) {
-+		const ATOM_VOLTAGE_OBJECT_V3 *voltage_object =
-+			(const ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
-+
-+		if (voltage_type == voltage_object->asGpioVoltageObj.sHeader.ucVoltageType &&
-+			voltage_mode == voltage_object->asGpioVoltageObj.sHeader.ucVoltageMode)
-+			return voltage_object;
-+
-+		offset += le16_to_cpu(voltage_object->asGpioVoltageObj.sHeader.usSize);
-+	}
-+
-+	return NULL;
-+}
-+
-+/** atomctrl_get_memory_pll_dividers_si().
-+ *
-+ * @param hwmgr                 input parameter: pointer to HwMgr
-+ * @param clock_value             input parameter: memory clock
-+ * @param dividers                 output parameter: memory PLL dividers
-+ * @param strobe_mode            input parameter: 1 for strobe mode,  0 for performance mode
-+ */
-+int atomctrl_get_memory_pll_dividers_si(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t clock_value,
-+		pp_atomctrl_memory_clock_param *mpll_param,
-+		bool strobe_mode)
-+{
-+	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
-+	int result;
-+
-+	mpll_parameters.ulClock = (uint32_t) clock_value;
-+	mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);
-+
-+	result = cgs_atom_exec_cmd_table
-+		(hwmgr->device,
-+		 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
-+		 &mpll_parameters);
-+
-+	if (0 == result) {
-+		mpll_param->mpll_fb_divider.clk_frac =
-+			mpll_parameters.ulFbDiv.usFbDivFrac;
-+		mpll_param->mpll_fb_divider.cl_kf =
-+			mpll_parameters.ulFbDiv.usFbDiv;
-+		mpll_param->mpll_post_divider =
-+			(uint32_t)mpll_parameters.ucPostDiv;
-+		mpll_param->vco_mode =
-+			(uint32_t)(mpll_parameters.ucPllCntlFlag &
-+					MPLL_CNTL_FLAG_VCO_MODE_MASK);
-+		mpll_param->yclk_sel =
-+			(uint32_t)((mpll_parameters.ucPllCntlFlag &
-+						MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0);
-+		mpll_param->qdr =
-+			(uint32_t)((mpll_parameters.ucPllCntlFlag &
-+						MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0);
-+		mpll_param->half_rate =
-+			(uint32_t)((mpll_parameters.ucPllCntlFlag &
-+						MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0);
-+		mpll_param->dll_speed =
-+			(uint32_t)(mpll_parameters.ucDllSpeed);
-+		mpll_param->bw_ctrl =
-+			(uint32_t)(mpll_parameters.ucBWCntl);
-+	}
-+
-+	return result;
-+}
-+
-+int atomctrl_get_engine_pll_dividers_vi(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t clock_value,
-+		pp_atomctrl_clock_dividers_vi *dividers)
-+{
-+	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
-+	int result;
-+
-+	pll_patameters.ulClock.ulClock = clock_value;
-+	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
-+
-+	result = cgs_atom_exec_cmd_table
-+		(hwmgr->device,
-+		 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
-+		 &pll_patameters);
-+
-+	if (0 == result) {
-+		dividers->pll_post_divider =
-+			pll_patameters.ulClock.ucPostDiv;
-+		dividers->real_clock =
-+			pll_patameters.ulClock.ulClock;
-+
-+		dividers->ul_fb_div.ul_fb_div_frac =
-+			pll_patameters.ulFbDiv.usFbDivFrac;
-+		dividers->ul_fb_div.ul_fb_div =
-+			pll_patameters.ulFbDiv.usFbDiv;
-+
-+		dividers->uc_pll_ref_div =
-+			pll_patameters.ucPllRefDiv;
-+		dividers->uc_pll_post_div =
-+			pll_patameters.ucPllPostDiv;
-+		dividers->uc_pll_cntl_flag =
-+			pll_patameters.ucPllCntlFlag;
-+	}
-+
-+	return result;
-+}
-+
-+int atomctrl_get_dfs_pll_dividers_vi(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t clock_value,
-+		pp_atomctrl_clock_dividers_vi *dividers)
-+{
-+	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
-+	int result;
-+
-+	pll_patameters.ulClock.ulClock = clock_value;
-+	pll_patameters.ulClock.ucPostDiv =
-+		COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
-+
-+	result = cgs_atom_exec_cmd_table
-+		(hwmgr->device,
-+		 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
-+		 &pll_patameters);
-+
-+	if (0 == result) {
-+		dividers->pll_post_divider =
-+			pll_patameters.ulClock.ucPostDiv;
-+		dividers->real_clock =
-+			pll_patameters.ulClock.ulClock;
-+
-+		dividers->ul_fb_div.ul_fb_div_frac =
-+			pll_patameters.ulFbDiv.usFbDivFrac;
-+		dividers->ul_fb_div.ul_fb_div =
-+			pll_patameters.ulFbDiv.usFbDiv;
-+
-+		dividers->uc_pll_ref_div =
-+			pll_patameters.ucPllRefDiv;
-+		dividers->uc_pll_post_div =
-+			pll_patameters.ucPllPostDiv;
-+		dividers->uc_pll_cntl_flag =
-+			pll_patameters.ucPllCntlFlag;
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Get the reference clock in 10KHz
-+ */
-+uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
-+{
-+	ATOM_FIRMWARE_INFO *fw_info;
-+	u8 frev, crev;
-+	u16 size;
-+	uint32_t clock;
-+
-+	fw_info = (ATOM_FIRMWARE_INFO *)
-+		cgs_atom_get_data_table(hwmgr->device,
-+			GetIndexIntoMasterTable(DATA, FirmwareInfo),
-+			&size, &frev, &crev);
-+
-+	if (fw_info == NULL)
-+		clock = 2700;
-+	else
-+		clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock));
-+
-+	return clock;
-+}
-+
-+/**
-+ * Returns 0 if the given voltage type is controlled by GPIO pins.
-+ * voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC,
-+ * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
-+ * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
-+ */
-+bool atomctrl_is_voltage_controled_by_gpio_v3(
-+		struct pp_hwmgr *hwmgr,
-+		uint8_t voltage_type,
-+		uint8_t voltage_mode)
-+{
-+	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
-+		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
-+	bool ret;
-+
-+	PP_ASSERT_WITH_CODE((NULL != voltage_info),
-+			"Could not find Voltage Table in BIOS.", return -1;);
-+
-+	ret = (NULL != atomctrl_lookup_voltage_type_v3
-+			(voltage_info, voltage_type, voltage_mode)) ? 0 : 1;
-+
-+	return ret;
-+}
-+
-+int atomctrl_get_voltage_table_v3(
-+		struct pp_hwmgr *hwmgr,
-+		uint8_t voltage_type,
-+		uint8_t voltage_mode,
-+		pp_atomctrl_voltage_table *voltage_table)
-+{
-+	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
-+		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
-+	const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
-+	unsigned int i;
-+
-+	PP_ASSERT_WITH_CODE((NULL != voltage_info),
-+			"Could not find Voltage Table in BIOS.", return -1;);
-+
-+	voltage_object = atomctrl_lookup_voltage_type_v3
-+		(voltage_info, voltage_type, voltage_mode);
-+
-+	if (voltage_object == NULL)
-+		return -1;
-+
-+	PP_ASSERT_WITH_CODE(
-+			(voltage_object->asGpioVoltageObj.ucGpioEntryNum <=
-+			PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES),
-+			"Too many voltage entries!",
-+			return -1;
-+			);
-+
-+	for (i = 0; i < voltage_object->asGpioVoltageObj.ucGpioEntryNum; i++) {
-+		voltage_table->entries[i].value =
-+			voltage_object->asGpioVoltageObj.asVolGpioLut[i].usVoltageValue;
-+		voltage_table->entries[i].smio_low =
-+			voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId;
-+	}
-+
-+	voltage_table->mask_low    =
-+		voltage_object->asGpioVoltageObj.ulGpioMaskVal;
-+	voltage_table->count      =
-+		voltage_object->asGpioVoltageObj.ucGpioEntryNum;
-+	voltage_table->phase_delay =
-+		voltage_object->asGpioVoltageObj.ucPhaseDelay;
-+
-+	return 0;
-+}
-+
-+static bool atomctrl_lookup_gpio_pin(
-+		ATOM_GPIO_PIN_LUT * gpio_lookup_table,
-+		const uint32_t pinId,
-+		pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
-+{
-+	unsigned int size = le16_to_cpu(gpio_lookup_table->sHeader.usStructureSize);
-+	unsigned int offset = offsetof(ATOM_GPIO_PIN_LUT, asGPIO_Pin[0]);
-+	uint8_t *start = (uint8_t *)gpio_lookup_table;
-+
-+	while (offset < size) {
-+		const ATOM_GPIO_PIN_ASSIGNMENT *pin_assignment =
-+			(const ATOM_GPIO_PIN_ASSIGNMENT *)(start + offset);
-+
-+		if (pinId == pin_assignment->ucGPIO_ID) {
-+			gpio_pin_assignment->uc_gpio_pin_bit_shift =
-+				pin_assignment->ucGpioPinBitShift;
-+			gpio_pin_assignment->us_gpio_pin_aindex =
-+				le16_to_cpu(pin_assignment->usGpioPin_AIndex);
-+			return 0;
-+		}
-+
-+		offset += offsetof(ATOM_GPIO_PIN_ASSIGNMENT, ucGPIO_ID) + 1;
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * Private Function to get the PowerPlay Table Address.
-+ * WARNING: The tabled returned by this function is in
-+ * dynamically allocated memory.
-+ * The caller has to release if by calling kfree.
-+ */
-+static ATOM_GPIO_PIN_LUT *get_gpio_lookup_table(void *device)
-+{
-+	u8 frev, crev;
-+	u16 size;
-+	void *table_address;
-+
-+	table_address = (ATOM_GPIO_PIN_LUT *)
-+		cgs_atom_get_data_table(device,
-+				GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT),
-+				&size, &frev, &crev);
-+
-+	PP_ASSERT_WITH_CODE((NULL != table_address),
-+			"Error retrieving BIOS Table Address!", return NULL;);
-+
-+	return (ATOM_GPIO_PIN_LUT *)table_address;
-+}
-+
-+/**
-+ * Returns 1 if the given pin id find in lookup table.
-+ */
-+bool atomctrl_get_pp_assign_pin(
-+		struct pp_hwmgr *hwmgr,
-+		const uint32_t pinId,
-+		pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
-+{
-+	bool bRet = 0;
-+	ATOM_GPIO_PIN_LUT *gpio_lookup_table =
-+		get_gpio_lookup_table(hwmgr->device);
-+
-+	PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
-+			"Could not find GPIO lookup Table in BIOS.", return -1);
-+
-+	bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId,
-+		gpio_pin_assignment);
-+
-+	return bRet;
-+}
-+
-+/** atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table.
-+ * @param hwmgr               	input: pointer to hwManager
-+ * @param voltage_type            input: type of EVV voltage VDDC or VDDGFX
-+ * @param sclk                        input: in 10Khz unit. DPM state SCLK frequency
-+ *                                   		which is define in PPTable SCLK/VDDC dependence
-+ *				table associated with this virtual_voltage_Id
-+ * @param virtual_voltage_Id      input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
-+ * @param voltage		       output: real voltage level in unit of mv
-+ */
-+int atomctrl_get_voltage_evv_on_sclk(
-+		struct pp_hwmgr *hwmgr,
-+		uint8_t voltage_type,
-+		uint32_t sclk, uint16_t virtual_voltage_Id,
-+		uint16_t *voltage)
-+{
-+	int result;
-+	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
-+
-+	get_voltage_info_param_space.ucVoltageType   =
-+		voltage_type;
-+	get_voltage_info_param_space.ucVoltageMode   =
-+		ATOM_GET_VOLTAGE_EVV_VOLTAGE;
-+	get_voltage_info_param_space.usVoltageLevel  =
-+		virtual_voltage_Id;
-+	get_voltage_info_param_space.ulSCLKFreq      =
-+		sclk;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
-+			&get_voltage_info_param_space);
-+
-+	if (0 != result)
-+		return result;
-+
-+	*voltage = ((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
-+			(&get_voltage_info_param_space))->usVoltageLevel;
-+
-+	return result;
-+}
-+
-+/**
-+ * Get the mpll reference clock in 10KHz
-+ */
-+uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)
-+{
-+	ATOM_COMMON_TABLE_HEADER *fw_info;
-+	uint32_t clock;
-+	u8 frev, crev;
-+	u16 size;
-+
-+	fw_info = (ATOM_COMMON_TABLE_HEADER *)
-+		cgs_atom_get_data_table(hwmgr->device,
-+				GetIndexIntoMasterTable(DATA, FirmwareInfo),
-+				&size, &frev, &crev);
-+
-+	if (fw_info == NULL)
-+		clock = 2700;
-+	else {
-+		if ((fw_info->ucTableFormatRevision == 2) &&
-+			(le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V2_1))) {
-+			ATOM_FIRMWARE_INFO_V2_1 *fwInfo_2_1 =
-+				(ATOM_FIRMWARE_INFO_V2_1 *)fw_info;
-+			clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock));
-+		} else {
-+			ATOM_FIRMWARE_INFO *fwInfo_0_0 =
-+				(ATOM_FIRMWARE_INFO *)fw_info;
-+			clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock));
-+		}
-+	}
-+
-+	return clock;
-+}
-+
-+/**
-+ * Get the asic internal spread spectrum table
-+ */
-+static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
-+{
-+	ATOM_ASIC_INTERNAL_SS_INFO *table = NULL;
-+	u8 frev, crev;
-+	u16 size;
-+
-+	table = (ATOM_ASIC_INTERNAL_SS_INFO *)
-+		cgs_atom_get_data_table(device,
-+			GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info),
-+			&size, &frev, &crev);
-+
-+	return table;
-+}
-+
-+/**
-+ * Get the asic internal spread spectrum assignment
-+ */
-+static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr,
-+		const uint8_t clockSource,
-+		const uint32_t clockSpeed,
-+		pp_atomctrl_internal_ss_info *ssEntry)
-+{
-+	ATOM_ASIC_INTERNAL_SS_INFO *table;
-+	ATOM_ASIC_SS_ASSIGNMENT *ssInfo;
-+	int entry_found = 0;
-+
-+	memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info));
-+
-+	table = asic_internal_ss_get_ss_table(hwmgr->device);
-+
-+	if (NULL == table)
-+		return -1;
-+
-+	ssInfo = &table->asSpreadSpectrum[0];
-+
-+	while (((uint8_t *)ssInfo - (uint8_t *)table) <
-+		le16_to_cpu(table->sHeader.usStructureSize)) {
-+		if ((clockSource == ssInfo->ucClockIndication) &&
-+			((uint32_t)clockSpeed <= le32_to_cpu(ssInfo->ulTargetClockRange))) {
-+			entry_found = 1;
-+			break;
-+		}
-+
-+		ssInfo = (ATOM_ASIC_SS_ASSIGNMENT *)((uint8_t *)ssInfo +
-+				sizeof(ATOM_ASIC_SS_ASSIGNMENT));
-+	}
-+
-+	if (entry_found) {
-+		ssEntry->speed_spectrum_percentage =
-+			ssInfo->usSpreadSpectrumPercentage;
-+		ssEntry->speed_spectrum_rate = ssInfo->usSpreadRateInKhz;
-+
-+		if (((GET_DATA_TABLE_MAJOR_REVISION(table) == 2) &&
-+			(GET_DATA_TABLE_MINOR_REVISION(table) >= 2)) ||
-+			(GET_DATA_TABLE_MAJOR_REVISION(table) == 3)) {
-+			ssEntry->speed_spectrum_rate /= 100;
-+		}
-+
-+		switch (ssInfo->ucSpreadSpectrumMode) {
-+		case 0:
-+			ssEntry->speed_spectrum_mode =
-+				pp_atomctrl_spread_spectrum_mode_down;
-+			break;
-+		case 1:
-+			ssEntry->speed_spectrum_mode =
-+				pp_atomctrl_spread_spectrum_mode_center;
-+			break;
-+		default:
-+			ssEntry->speed_spectrum_mode =
-+				pp_atomctrl_spread_spectrum_mode_down;
-+			break;
-+		}
-+	}
-+
-+	return entry_found ? 0 : 1;
-+}
-+
-+/**
-+ * Get the memory clock spread spectrum info
-+ */
-+int atomctrl_get_memory_clock_spread_spectrum(
-+		struct pp_hwmgr *hwmgr,
-+		const uint32_t memory_clock,
-+		pp_atomctrl_internal_ss_info *ssInfo)
-+{
-+	return asic_internal_ss_get_ss_asignment(hwmgr,
-+			ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo);
-+}
-+/**
-+ * Get the engine clock spread spectrum info
-+ */
-+int atomctrl_get_engine_clock_spread_spectrum(
-+		struct pp_hwmgr *hwmgr,
-+		const uint32_t engine_clock,
-+		pp_atomctrl_internal_ss_info *ssInfo)
-+{
-+	return asic_internal_ss_get_ss_asignment(hwmgr,
-+			ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
-+}
-+
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-new file mode 100644
-index 0000000..23da436
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-@@ -0,0 +1,237 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef PP_ATOMVOLTAGECTRL_H
-+#define PP_ATOMVOLTAGECTRL_H
-+
-+#include "hwmgr.h"
-+
-+#define MEM_TYPE_GDDR5  0x50
-+#define MEM_TYPE_GDDR4  0x40
-+#define MEM_TYPE_GDDR3  0x30
-+#define MEM_TYPE_DDR2   0x20
-+#define MEM_TYPE_GDDR1  0x10
-+#define MEM_TYPE_DDR3   0xb0
-+#define MEM_TYPE_MASK   0xF0
-+
-+
-+/* As returned from PowerConnectorDetectionTable. */
-+#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE  0x80
-+#define PP_ATOM_POWER_BUDGET_SHOW_WARNING       0x40
-+#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER        0x20
-+#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR    0x0F
-+
-+/* New functions for Evergreen and beyond. */
-+#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
-+
-+struct pp_atomctrl_clock_dividers {
-+	uint32_t pll_post_divider;
-+	uint32_t pll_feedback_divider;
-+	uint32_t pll_ref_divider;
-+	bool  enable_post_divider;
-+};
-+
-+typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
-+
-+union pp_atomctrl_tcipll_fb_divider {
-+	struct {
-+		uint32_t ul_fb_div_frac : 14;
-+		uint32_t ul_fb_div : 12;
-+		uint32_t un_used : 6;
-+	};
-+	uint32_t ul_fb_divider;
-+};
-+
-+typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
-+
-+struct pp_atomctrl_clock_dividers_rv730 {
-+	uint32_t pll_post_divider;
-+	pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
-+	uint32_t pll_ref_divider;
-+	bool  enable_post_divider;
-+	bool  enable_dithen;
-+	uint32_t vco_mode;
-+};
-+typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
-+
-+
-+struct pp_atomctrl_clock_dividers_kong {
-+	uint32_t    pll_post_divider;
-+	uint32_t    real_clock;
-+};
-+typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
-+
-+struct pp_atomctrl_clock_dividers_ci {
-+	uint32_t    pll_post_divider;               /* post divider value */
-+	uint32_t    real_clock;
-+	pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /* Output Parameter: PLL FB divider */
-+	uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
-+	uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
-+	uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
-+};
-+typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
-+
-+struct pp_atomctrl_clock_dividers_vi {
-+	uint32_t    pll_post_divider;               /* post divider value */
-+	uint32_t    real_clock;
-+	pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /*Output Parameter: PLL FB divider */
-+	uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
-+	uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
-+	uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
-+};
-+typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
-+
-+union pp_atomctrl_s_mpll_fb_divider {
-+	struct {
-+		uint32_t cl_kf : 12;
-+		uint32_t clk_frac : 12;
-+		uint32_t un_used : 8;
-+	};
-+	uint32_t ul_fb_divider;
-+};
-+typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
-+
-+enum pp_atomctrl_spread_spectrum_mode {
-+	pp_atomctrl_spread_spectrum_mode_down = 0,
-+	pp_atomctrl_spread_spectrum_mode_center
-+};
-+typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
-+
-+struct pp_atomctrl_memory_clock_param {
-+	pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
-+	uint32_t mpll_post_divider;
-+	uint32_t bw_ctrl;
-+	uint32_t dll_speed;
-+	uint32_t vco_mode;
-+	uint32_t yclk_sel;
-+	uint32_t qdr;
-+	uint32_t half_rate;
-+};
-+typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
-+
-+struct pp_atomctrl_internal_ss_info {
-+	uint32_t speed_spectrum_percentage;                      /* in 1/100 percentage */
-+	uint32_t speed_spectrum_rate;                            /* in KHz */
-+	pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
-+};
-+typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
-+
-+#ifndef NUMBER_OF_M3ARB_PARAMS
-+#define NUMBER_OF_M3ARB_PARAMS 3
-+#endif
-+
-+#ifndef NUMBER_OF_M3ARB_PARAM_SETS
-+#define NUMBER_OF_M3ARB_PARAM_SETS 10
-+#endif
-+
-+struct pp_atomctrl_kong_system_info {
-+	uint32_t			ul_bootup_uma_clock;          /* in 10kHz unit */
-+	uint16_t			us_max_nb_voltage;            /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
-+	uint16_t			us_min_nb_voltage;            /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
-+	uint16_t			us_bootup_nb_voltage;         /* boot up NB voltage */
-+	uint8_t			uc_htc_tmp_lmt;               /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
-+	uint8_t			uc_tj_offset;                /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
-+	/* 0: default 1: uvd 2: fs-3d */
-+	uint32_t          ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
-+};
-+typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
-+
-+struct pp_atomctrl_memory_info {
-+	uint8_t memory_vendor;
-+	uint8_t memory_type;
-+};
-+typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
-+
-+#define MAX_AC_TIMING_ENTRIES 16
-+
-+struct pp_atomctrl_memory_clock_range_table {
-+	uint8_t   num_entries;
-+	uint8_t   rsv[3];
-+
-+	uint32_t mclk[MAX_AC_TIMING_ENTRIES];
-+};
-+typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
-+
-+struct pp_atomctrl_voltage_table_entry {
-+	uint16_t value;
-+	uint32_t smio_low;
-+};
-+
-+typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
-+
-+struct pp_atomctrl_voltage_table {
-+	uint32_t count;
-+	uint32_t mask_low;
-+	uint32_t phase_delay;   /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
-+	pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
-+};
-+
-+typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
-+
-+#define VBIOS_MC_REGISTER_ARRAY_SIZE           32
-+#define VBIOS_MAX_AC_TIMING_ENTRIES            20
-+
-+struct pp_atomctrl_mc_reg_entry {
-+	uint32_t           mclk_max;
-+	uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
-+};
-+typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
-+
-+struct pp_atomctrl_mc_register_address {
-+	uint16_t s1;
-+	uint8_t  uc_pre_reg_data;
-+};
-+
-+typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
-+
-+struct pp_atomctrl_mc_reg_table {
-+	uint8_t                         last;                    /* number of registers */
-+	uint8_t                         num_entries;             /* number of AC timing entries */
-+	pp_atomctrl_mc_reg_entry        mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
-+	pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
-+};
-+typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
-+
-+struct pp_atomctrl_gpio_pin_assignment {
-+	uint16_t                   us_gpio_pin_aindex;
-+	uint8_t                    uc_gpio_pin_bit_shift;
-+};
-+typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
-+
-+extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
-+extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
-+extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
-+extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
-+extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
-+extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
-+extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
-+extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
-+extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
-+extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
-+extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
-+extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
-+extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
-+
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h
-new file mode 100644
-index 0000000..7269ac1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef PP_INTERRUPT_H
-+#define PP_INTERRUPT_H
-+
-+/**
-+ * The type of the interrupt callback functions in PowerPlay
-+ */
-+typedef void (*pp_interrupt_callback) (void *context, uint32_t ul_context_data);
-+
-+/**
-+ * Event Manager action chain list information
-+ */
-+struct pp_interrupt_registration_info {
-+	pp_interrupt_callback callback;  /* Pointer to callback function */
-+	void *context;                  /* Pointer to callback function context */
-+	uint32_t *interrupt_enable_id;    /* Registered interrupt id */
-+};
-+
-+typedef struct pp_interrupt_registration_info pp_interrupt_registration_info;
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c
-new file mode 100644
-index 0000000..186496a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.c
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/types.h>
-+#include "atom-types.h"
-+#include "atombios.h"
-+#include "pppcielanes.h"
-+
-+/** \file
-+ * Functions related to PCIe lane changes.
-+ */
-+
-+/* For converting from number of lanes to lane bits.  */
-+static const unsigned char pp_r600_encode_lanes[] = {
-+	0,          /*  0 Not Supported  */
-+	1,          /*  1 Lane  */
-+	2,          /*  2 Lanes  */
-+	0,          /*  3 Not Supported  */
-+	3,          /*  4 Lanes  */
-+	0,          /*  5 Not Supported  */
-+	0,          /*  6 Not Supported  */
-+	0,          /*  7 Not Supported  */
-+	4,          /*  8 Lanes  */
-+	0,          /*  9 Not Supported  */
-+	0,          /* 10 Not Supported  */
-+	0,          /* 11 Not Supported  */
-+	5,          /* 12 Lanes (Not actually supported)  */
-+	0,          /* 13 Not Supported  */
-+	0,          /* 14 Not Supported  */
-+	0,          /* 15 Not Supported  */
-+	6           /* 16 Lanes  */
-+};
-+
-+static const unsigned char pp_r600_decoded_lanes[8] = { 16, 1, 2, 4, 8, 12, 16, };
-+
-+uint8_t encode_pcie_lane_width(uint32_t num_lanes)
-+{
-+	return pp_r600_encode_lanes[num_lanes];
-+}
-+
-+uint8_t decode_pcie_lane_width(uint32_t num_lanes)
-+{
-+	return pp_r600_decoded_lanes[num_lanes];
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h
-new file mode 100644
-index 0000000..70b163b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pppcielanes.h
-@@ -0,0 +1,31 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef PP_PCIELANES_H
-+#define PP_PCIELANES_H
-+
-+extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
-+extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_dyn_defaults.h
-new file mode 100644
-index 0000000..080d69d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_dyn_defaults.h
-@@ -0,0 +1,107 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef TONGA_DYN_DEFAULTS_H
-+#define TONGA_DYN_DEFAULTS_H
-+
-+
-+/** \file
-+ * Volcanic Islands Dynamic default parameters.
-+ */
-+
-+enum TONGAdpm_TrendDetection {
-+	TONGAdpm_TrendDetection_AUTO,
-+	TONGAdpm_TrendDetection_UP,
-+	TONGAdpm_TrendDetection_DOWN
-+};
-+typedef enum TONGAdpm_TrendDetection TONGAdpm_TrendDetection;
-+
-+/* Bit vector representing same fields as hardware register. */
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102  /* CP_Gfx_busy */
-+/* HDP_busy */
-+/* IH_busy */
-+/* DRM_busy */
-+/* DRMDMA_busy */
-+/* UVD_busy */
-+/* VCE_busy */
-+/* ACP_busy */
-+/* SAMU_busy */
-+/* AVP_busy  */
-+/* SDMA enabled */
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1              0x000400  /* FE_Gfx_busy  - Intended for primary usage.   Rest are for flexibility. */
-+/* SH_Gfx_busy */
-+/* RB_Gfx_busy */
-+/* VCE_busy */
-+
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080  /* SH_Gfx_busy - Intended for primary usage.   Rest are for flexibility. */
-+/* FE_Gfx_busy */
-+/* RB_Gfx_busy */
-+/* ACP_busy */
-+
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200  /* RB_Gfx_busy - Intended for primary usage.   Rest are for flexibility. */
-+/* FE_Gfx_busy */
-+/* SH_Gfx_busy */
-+/* UVD_busy */
-+
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680  /* UVD_busy */
-+/* VCE_busy */
-+/* ACP_busy */
-+/* SAMU_busy */
-+
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033  /* GFX, HDP, DRMDMA */
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033  /* GFX, HDP, DRMDMA */
-+#define PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000  /* GFX, HDP, DRMDMA */
-+
-+
-+/* thermal protection counter (units).*/
-+#define PPTONGA_THERMALPROTECTCOUNTER_DFLT            0x200 /* ~19us */
-+
-+/* static screen threshold unit */
-+#define PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT        0
-+
-+/* static screen threshold */
-+#define PPTONGA_STATICSCREENTHRESHOLD_DFLT            0x00C8
-+
-+/* gfx idle clock stop threshold */
-+#define PPTONGA_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200 /* ~19us with static screen threshold unit of 0 */
-+
-+/* Fixed reference divider to use when building baby stepping tables. */
-+#define PPTONGA_REFERENCEDIVIDER_DFLT                  4
-+
-+/*
-+ * ULV voltage change delay time
-+ * Used to be delay_vreg in N.I. split for S.I.
-+ * Using N.I. delay_vreg value as default
-+ * ReferenceClock = 2700
-+ * VoltageResponseTime = 1000
-+ * VDDCDelayTime = (VoltageResponseTime * ReferenceClock) / 1600 = 1687
-+ */
-+
-+#define PPTONGA_ULVVOLTAGECHANGEDELAY_DFLT             1687
-+
-+#define PPTONGA_CGULVPARAMETER_DFLT                    0x00040035
-+#define PPTONGA_CGULVCONTROL_DFLT                      0x00007450
-+#define PPTONGA_TARGETACTIVITY_DFLT                     30  /*30%  */
-+#define PPTONGA_MCLK_TARGETACTIVITY_DFLT                10  /*10%  */
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-new file mode 100644
-index 0000000..0feb1a8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -0,0 +1,5714 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+#include "linux/delay.h"
-+#include "pp_acpi.h"
-+#include "hwmgr.h"
-+#include <atombios.h>
-+#include "tonga_hwmgr.h"
-+#include "pptable.h"
-+#include "processpptables.h"
-+#include "tonga_processpptables.h"
-+#include "tonga_pptable.h"
-+#include "pp_debug.h"
-+#include "tonga_ppsmc.h"
-+#include "cgs_common.h"
-+#include "pppcielanes.h"
-+#include "tonga_dyn_defaults.h"
-+#include "smumgr.h"
-+#include "tonga_smumgr.h"
-+
-+#include "smu/smu_7_1_2_d.h"
-+#include "smu/smu_7_1_2_sh_mask.h"
-+
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+
-+#define MC_CG_ARB_FREQ_F0           0x0a
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define MC_CG_ARB_FREQ_F2           0x0c
-+#define MC_CG_ARB_FREQ_F3           0x0d
-+
-+#define MC_CG_SEQ_DRAMCONF_S0       0x05
-+#define MC_CG_SEQ_DRAMCONF_S1       0x06
-+#define MC_CG_SEQ_YCLK_SUSPEND      0x04
-+#define MC_CG_SEQ_YCLK_RESUME       0x0a
-+
-+#define PCIE_BUS_CLK                10000
-+#define TCLK                        (PCIE_BUS_CLK / 10)
-+
-+#define SMC_RAM_END 0x40000
-+#define SMC_CG_IND_START            0xc0030000
-+#define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND*/
-+
-+#define VOLTAGE_SCALE               4
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+
-+#define VDDC_VDDCI_DELTA            200
-+#define VDDC_VDDGFX_DELTA           300
-+
-+#define MC_SEQ_MISC0_GDDR5_SHIFT 28
-+#define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
-+#define MC_SEQ_MISC0_GDDR5_VALUE 5
-+
-+typedef uint32_t PECI_RegistryValue;
-+
-+/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
-+uint16_t PP_ClockStretcherLookupTable[2][4] = {
-+	{600, 1050, 3, 0},
-+	{600, 1050, 6, 1} };
-+
-+/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
-+uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
-+	{ {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+	{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-+
-+/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
-+uint8_t PP_ClockStretchAmountConversion[2][6] = {
-+	{0, 1, 3, 2, 4, 5},
-+	{0, 2, 4, 5, 6, 5} };
-+
-+/* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
-+enum DPM_EVENT_SRC {
-+	DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
-+	DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
-+	DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
-+	DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
-+	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
-+};
-+typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
-+
-+enum DISPLAY_GAP {
-+	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
-+	DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
-+	DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
-+	DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
-+};
-+typedef enum DISPLAY_GAP DISPLAY_GAP;
-+
-+const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
-+
-+struct tonga_power_state *cast_phw_tonga_power_state(
-+				  struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL;);
-+
-+	return (struct tonga_power_state *)hw_ps;
-+}
-+
-+const struct tonga_power_state *cast_const_phw_tonga_power_state(
-+				 const struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL;);
-+
-+	return (const struct tonga_power_state *)hw_ps;
-+}
-+
-+int tonga_add_voltage(struct pp_hwmgr *hwmgr,
-+	phm_ppt_v1_voltage_lookup_table *look_up_table,
-+	phm_ppt_v1_voltage_lookup_record *record)
-+{
-+	uint32_t i;
-+	PP_ASSERT_WITH_CODE((NULL != look_up_table),
-+		"Lookup Table empty.", return -1;);
-+	PP_ASSERT_WITH_CODE((0 != look_up_table->count),
-+		"Lookup Table empty.", return -1;);
-+	PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
-+		"Lookup Table is full.", return -1;);
-+
-+	/* This is to avoid entering duplicate calculated records. */
-+	for (i = 0; i < look_up_table->count; i++) {
-+		if (look_up_table->entries[i].us_vdd == record->us_vdd) {
-+			if (look_up_table->entries[i].us_calculated == 1)
-+				return 0;
-+			else
-+				break;
-+		}
-+	}
-+
-+	look_up_table->entries[i].us_calculated = 1;
-+	look_up_table->entries[i].us_vdd = record->us_vdd;
-+	look_up_table->entries[i].us_cac_low = record->us_cac_low;
-+	look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
-+	look_up_table->entries[i].us_cac_high = record->us_cac_high;
-+	/* Only increment the count when we're appending, not replacing duplicate entry. */
-+	if (i == look_up_table->count)
-+		look_up_table->count++;
-+
-+	return 0;
-+}
-+
-+uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
-+		uint32_t voltage)
-+{
-+	uint8_t count = (uint8_t) (voltage_table->count);
-+	uint8_t i = 0;
-+
-+	PP_ASSERT_WITH_CODE((NULL != voltage_table),
-+		"Voltage Table empty.", return 0;);
-+	PP_ASSERT_WITH_CODE((0 != count),
-+		"Voltage Table empty.", return 0;);
-+
-+	for (i = 0; i < count; i++) {
-+		/* find first voltage bigger than requested */
-+		if (voltage_table->entries[i].value >= voltage)
-+			return i;
-+	}
-+
-+	/* voltage is bigger than max voltage in the table */
-+	return i - 1;
-+}
-+
-+/**
-+ * @brief PhwTonga_GetVoltageOrder
-+ *  Returns index of requested voltage record in lookup(table)
-+ * @param hwmgr - pointer to hardware manager
-+ * @param lookupTable - lookup list to search in
-+ * @param voltage - voltage to look for
-+ * @return 0 on success
-+ */
-+uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
-+		uint16_t voltage)
-+{
-+	uint8_t count = (uint8_t) (look_up_table->count);
-+	uint8_t i;
-+
-+	PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
-+	PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
-+
-+	for (i = 0; i < count; i++) {
-+		/* find first voltage equal or bigger than requested */
-+		if (look_up_table->entries[i].us_vdd >= voltage)
-+			return i;
-+	}
-+
-+	/* voltage is bigger than max voltage in the table */
-+	return i-1;
-+}
-+
-+bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	/*
-+	 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
-+	 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
-+	 * whereas voltage control is a fundemental change that will not be disabled
-+	 */
-+
-+	return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+					FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
-+}
-+
-+/**
-+ * Re-generate the DPM level mask value
-+ * @param    hwmgr      the address of the hardware manager
-+ */
-+static uint32_t tonga_get_dpm_level_enable_mask_value(
-+			struct tonga_single_dpm_table * dpm_table)
-+{
-+	uint32_t i;
-+	uint32_t mask_value = 0;
-+
-+	for (i = dpm_table->count; i > 0; i--) {
-+		mask_value = mask_value << 1;
-+
-+		if (dpm_table->dpm_levels[i-1].enabled)
-+			mask_value |= 0x1;
-+		else
-+			mask_value &= 0xFFFFFFFE;
-+	}
-+	return mask_value;
-+}
-+
-+/**
-+ * Retrieve DPM default values from registry (if available)
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ */
-+void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	phw_tonga_ulv_parm *ulv = &(data->ulv);
-+	uint32_t tmp;
-+
-+	ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
-+	data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
-+	data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
-+	data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
-+	data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
-+	data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
-+	data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
-+	data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
-+	data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
-+
-+	data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
-+	data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_ABM);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_NonABMSupportInPPLib);
-+
-+	tmp = 0;
-+	if (tmp == 0)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DynamicACTiming);
-+
-+	tmp = 0;
-+	if (0 != tmp)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DisableMemoryTransition);
-+
-+	data->mclk_strobe_mode_threshold = 40000;
-+	data->mclk_stutter_mode_threshold = 30000;
-+	data->mclk_edc_enable_threshold = 40000;
-+	data->mclk_edc_wr_enable_threshold = 40000;
-+
-+	tmp = 0;
-+	if (tmp != 0)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DisableMCLS);
-+
-+	data->pcie_gen_performance.max = PP_PCIEGen1;
-+	data->pcie_gen_performance.min = PP_PCIEGen3;
-+	data->pcie_gen_power_saving.max = PP_PCIEGen1;
-+	data->pcie_gen_power_saving.min = PP_PCIEGen3;
-+
-+	data->pcie_lane_performance.max = 0;
-+	data->pcie_lane_performance.min = 16;
-+	data->pcie_lane_power_saving.max = 0;
-+	data->pcie_lane_power_saving.min = 16;
-+
-+	tmp = 0;
-+
-+	if (tmp)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_DynamicUVDState);
-+
-+}
-+
-+int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = tonga_copy_bytes_to_smc(
-+				hwmgr->smumgr,
-+				data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
-+				LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				data->sram_end
-+				);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Find SCLK value that is associated with specified virtual_voltage_Id.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @param    virtual_voltage_Id  voltageId to look for.
-+ * @param    sclk output value .
-+ * @return   always 0 if success and 2 if association not found
-+ */
-+static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
-+	phm_ppt_v1_voltage_lookup_table *lookup_table,
-+	uint16_t virtual_voltage_id, uint32_t *sclk)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	struct phm_ppt_v1_information *pptable_info =
-+					(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
-+	for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
-+		voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
-+		if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
-+			break;
-+	}
-+
-+	PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
-+			"Can't find requested voltage id in vdd_dep_on_sclk table!",
-+			return -1;
-+			);
-+
-+	*sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Get Leakage VDDC based on leakage ID.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   2 if vddgfx returned is greater than 2V or if BIOS
-+ */
-+int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
-+	uint16_t    virtual_voltage_id;
-+	uint16_t    vddc = 0;
-+	uint16_t    vddgfx = 0;
-+	uint16_t    i, j;
-+	uint32_t  sclk = 0;
-+
-+	/* retrieve voltage for leakage ID (0xff01 + i) */
-+	for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
-+		virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-+
-+		/* in split mode we should have only vddgfx EVV leakages */
-+		if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
-+			if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
-+						pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
-+				if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+							PHM_PlatformCaps_ClockStretcher)) {
-+					for (j = 1; j < sclk_table->count; j++) {
-+						if (sclk_table->entries[j].clk == sclk &&
-+								sclk_table->entries[j].cks_enable == 0) {
-+							sclk += 5000;
-+							break;
-+						}
-+					}
-+				}
-+				PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
-+						(hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
-+						 virtual_voltage_id, &vddgfx),
-+						"Error retrieving EVV voltage value!", continue);
-+
-+				/* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
-+				PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
-+
-+				/* the voltage should not be zero nor equal to leakage ID */
-+				if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
-+					data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
-+					data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
-+					data->vddcgfx_leakage.count++;
-+				}
-+			}
-+		} else {
-+			/*  in merged mode we have only vddc EVV leakages */
-+			if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
-+						pptable_info->vddc_lookup_table,
-+						virtual_voltage_id, &sclk)) {
-+				PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
-+						(hwmgr, VOLTAGE_TYPE_VDDC, sclk,
-+						 virtual_voltage_id, &vddc),
-+						"Error retrieving EVV voltage value!", continue);
-+
-+				/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
-+				if (vddc > 2000)
-+					printk(KERN_ERR "[ powerplay ] Invalid VDDC value! \n");
-+
-+				/* the voltage should not be zero nor equal to leakage ID */
-+				if (vddc != 0 && vddc != virtual_voltage_id) {
-+					data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
-+					data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
-+					data->vddc_leakage.count++;
-+				}
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* enable SCLK dpm */
-+	if (0 == data->sclk_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						   PPSMC_MSG_DPM_Enable)),
-+				"Failed to enable SCLK DPM during DPM Start Function!",
-+				return -1);
-+	}
-+
-+	/* enable MCLK dpm */
-+	if (0 == data->mclk_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					     PPSMC_MSG_MCLKDPM_Enable)),
-+				"Failed to enable MCLK DPM during DPM Start Function!",
-+				return -1);
-+
-+		PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixLCAC_CPL_CNTL, 0x100005);/*Read */
-+
-+		udelay(10);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixLCAC_CPL_CNTL, 0x500005);/* write */
-+
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_start_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* enable general power management */
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
-+	/* enable sclk deep sleep */
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
-+
-+	/* prepare for PCIE DPM */
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
-+			offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_Voltage_Cntl_Enable)),
-+			"Failed to enable voltage DPM during DPM Start Function!",
-+			return -1);
-+
-+	if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
-+		PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
-+	}
-+
-+	/* enable PCIE dpm */
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_Enable)),
-+				"Failed to enable pcie DPM during DPM Start Function!",
-+				return -1
-+				);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_Falcon_QuickTransition)) {
-+				   smum_send_msg_to_smc(hwmgr->smumgr,
-+				    PPSMC_MSG_EnableACDCGPIOInterrupt);
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* disable SCLK dpm */
-+	if (0 == data->sclk_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
-+		PP_ASSERT_WITH_CODE(
-+				(0 == tonga_is_dpm_running(hwmgr)),
-+				"Trying to Disable SCLK DPM when DPM is disabled",
-+				return -1
-+				);
-+
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						  PPSMC_MSG_DPM_Disable)),
-+				"Failed to disable SCLK DPM during DPM stop Function!",
-+				return -1);
-+	}
-+
-+	/* disable MCLK dpm */
-+	if (0 == data->mclk_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
-+		PP_ASSERT_WITH_CODE(
-+				(0 == tonga_is_dpm_running(hwmgr)),
-+				"Trying to Disable MCLK DPM when DPM is disabled",
-+				return -1
-+				);
-+
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					    PPSMC_MSG_MCLKDPM_Disable)),
-+				"Failed to Disable MCLK DPM during DPM stop Function!",
-+				return -1);
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
-+	/* disable sclk deep sleep*/
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
-+
-+	/* disable PCIE dpm */
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
-+		PP_ASSERT_WITH_CODE(
-+				(0 == tonga_is_dpm_running(hwmgr)),
-+				"Trying to Disable PCIE DPM when DPM is disabled",
-+				return -1
-+				);
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_Disable)),
-+				"Failed to disable pcie DPM during DPM stop Function!",
-+				return -1);
-+	}
-+
-+	if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
-+		PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
-+
-+	/* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
-+	PP_ASSERT_WITH_CODE(
-+			(0 == tonga_is_dpm_running(hwmgr)),
-+			"Trying to Disable Voltage CNTL when DPM is disabled",
-+			return -1
-+			);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_Voltage_Cntl_Disable)),
-+			"Failed to disable voltage DPM during DPM stop Function!",
-+			return -1);
-+
-+	return 0;
-+}
-+
-+int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Send a message to the SMC and return a parameter
-+ *
-+ * @param    hwmgr:  the address of the powerplay hardware manager.
-+ * @param    msg: the message to send.
-+ * @param    parameter: pointer to the received parameter
-+ * @return   The response that came from the SMC.
-+ */
-+PPSMC_Result tonga_send_msg_to_smc_return_parameter(
-+		struct pp_hwmgr *hwmgr,
-+		PPSMC_Msg msg,
-+		uint32_t *parameter)
-+{
-+	int result;
-+
-+	result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
-+
-+	if ((0 == result) && parameter) {
-+		*parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * force DPM power State
-+ *
-+ * @param    hwmgr:  the address of the powerplay hardware manager.
-+ * @param    n     :  DPM level
-+ * @return   The response that came from the SMC.
-+ */
-+int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t level_mask = 1 << n;
-+
-+	/* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
-+	PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
-+			"Trying to force SCLK when DPM is disabled", return -1;);
-+	if (0 == data->sclk_dpm_key_disabled)
-+		return (0 == smum_send_msg_to_smc_with_parameter(
-+							     hwmgr->smumgr,
-+		     (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
-+						    level_mask) ? 0 : 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * force DPM power State
-+ *
-+ * @param    hwmgr:  the address of the powerplay hardware manager.
-+ * @param    n     :  DPM level
-+ * @return   The response that came from the SMC.
-+ */
-+int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t level_mask = 1 << n;
-+
-+	/* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
-+	PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
-+			"Trying to Force MCLK when DPM is disabled", return -1;);
-+	if (0 == data->mclk_dpm_key_disabled)
-+		return (0 == smum_send_msg_to_smc_with_parameter(
-+								hwmgr->smumgr,
-+								(PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
-+								level_mask) ? 0 : 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * force DPM power State
-+ *
-+ * @param    hwmgr:  the address of the powerplay hardware manager.
-+ * @param    n     :  DPM level
-+ * @return   The response that came from the SMC.
-+ */
-+int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
-+	PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
-+			"Trying to Force PCIE level when DPM is disabled", return -1;);
-+	if (0 == data->pcie_dpm_key_disabled)
-+		return (0 == smum_send_msg_to_smc_with_parameter(
-+							     hwmgr->smumgr,
-+			   (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
-+								n) ? 0 : 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Set the initial state by calling SMC to switch to this state directly
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
-+{
-+	/*
-+	* SMC only stores one state that SW will ask to switch too,
-+	* so we switch the the just uploaded one
-+	*/
-+	return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
-+}
-+
-+/**
-+ * Get the location of various tables inside the FW image.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
-+
-+	uint32_t tmp;
-+	int result;
-+	bool error = 0;
-+
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, DpmTable),
-+				&tmp, data->sram_end);
-+
-+	if (0 == result) {
-+		data->dpm_table_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, SoftRegisters),
-+				&tmp, data->sram_end);
-+
-+	if (0 == result) {
-+		data->soft_regs_start = tmp;
-+		tonga_smu->ulSoftRegsStart = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, mcRegisterTable),
-+				&tmp, data->sram_end);
-+
-+	if (0 == result) {
-+		data->mc_reg_table_start = tmp;
-+	}
-+
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, FanTable),
-+				&tmp, data->sram_end);
-+
-+	if (0 == result) {
-+		data->fan_table_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
-+				&tmp, data->sram_end);
-+
-+	if (0 == result) {
-+		data->arb_table_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, Version),
-+				&tmp, data->sram_end);
-+
-+	if (0 == result) {
-+		hwmgr->microcode_version_info.SMC = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	return error ? 1 : 0;
-+}
-+
-+/**
-+ * Read clock related registers.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL         =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
-+	data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
-+	data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
-+	data->clock_registers.vDLL_CNTL                  =
-+		cgs_read_register(hwmgr->device, mmDLL_CNTL);
-+	data->clock_registers.vMCLK_PWRMGT_CNTL          =
-+		cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
-+	data->clock_registers.vMPLL_AD_FUNC_CNTL         =
-+		cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
-+	data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
-+		cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
-+	data->clock_registers.vMPLL_FUNC_CNTL            =
-+		cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
-+	data->clock_registers.vMPLL_FUNC_CNTL_1          =
-+		cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
-+	data->clock_registers.vMPLL_FUNC_CNTL_2          =
-+		cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
-+	data->clock_registers.vMPLL_SS1                  =
-+		cgs_read_register(hwmgr->device, mmMPLL_SS1);
-+	data->clock_registers.vMPLL_SS2                  =
-+		cgs_read_register(hwmgr->device, mmMPLL_SS2);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Find out if memory is GDDR5.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t temp;
-+
-+	temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
-+
-+	data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
-+			((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
-+			 MC_SEQ_MISC0_GDDR5_SHIFT));
-+
-+	return 0;
-+}
-+
-+/**
-+ * Enables Dynamic Power Management by SMC
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initialize PowerGating States for different engines
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = 0;
-+	data->vce_power_gated = 0;
-+	data->samu_power_gated = 0;
-+	data->acp_power_gated = 0;
-+	data->pg_acp_init = 1;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Checks if DPM is enabled
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	/*
-+	 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
-+	 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
-+	 * whereas voltage control is a fundemental change that will not be disabled
-+	 */
-+	return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
-+}
-+
-+/**
-+ * Checks if DPM is stopped
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (0 != tonga_is_dpm_running(hwmgr)) {
-+		/* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
-+		if (!data->dpm_table_start) {
-+			return 1;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Remove repeated voltage values and create table with unique values.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @param    voltage_table  the pointer to changing voltage table
-+ * @return    1 in success
-+ */
-+
-+static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
-+			pp_atomctrl_voltage_table *voltage_table)
-+{
-+	uint32_t table_size, i, j;
-+	uint16_t vvalue;
-+	bool bVoltageFound = 0;
-+	pp_atomctrl_voltage_table *table;
-+
-+	PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
-+	table_size = sizeof(pp_atomctrl_voltage_table);
-+	table = kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -ENOMEM;
-+
-+	memset(table, 0x00, table_size);
-+	table->mask_low = voltage_table->mask_low;
-+	table->phase_delay = voltage_table->phase_delay;
-+
-+	for (i = 0; i < voltage_table->count; i++) {
-+		vvalue = voltage_table->entries[i].value;
-+		bVoltageFound = 0;
-+
-+		for (j = 0; j < table->count; j++) {
-+			if (vvalue == table->entries[j].value) {
-+				bVoltageFound = 1;
-+				break;
-+			}
-+		}
-+
-+		if (!bVoltageFound) {
-+			table->entries[table->count].value = vvalue;
-+			table->entries[table->count].smio_low =
-+				voltage_table->entries[i].smio_low;
-+			table->count++;
-+		}
-+	}
-+
-+	memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
-+
-+	kfree(table);
-+
-+	return 0;
-+}
-+
-+static int tonga_get_svi2_vdd_ci_voltage_table(
-+		struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
-+{
-+	uint32_t i;
-+	int result;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
-+
-+	PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
-+			"Voltage Dependency Table empty.", return -1;);
-+
-+	vddci_voltage_table->mask_low = 0;
-+	vddci_voltage_table->phase_delay = 0;
-+	vddci_voltage_table->count = voltage_dependency_table->count;
-+
-+	for (i = 0; i < voltage_dependency_table->count; i++) {
-+		vddci_voltage_table->entries[i].value =
-+			voltage_dependency_table->entries[i].vddci;
-+		vddci_voltage_table->entries[i].smio_low = 0;
-+	}
-+
-+	result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to trim VDDCI table.", return result;);
-+
-+	return 0;
-+}
-+
-+
-+
-+static int tonga_get_svi2_vdd_voltage_table(
-+		struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *look_up_table,
-+		pp_atomctrl_voltage_table *voltage_table)
-+{
-+	uint8_t i = 0;
-+
-+	PP_ASSERT_WITH_CODE((0 != look_up_table->count),
-+			"Voltage Lookup Table empty.", return -1;);
-+
-+	voltage_table->mask_low = 0;
-+	voltage_table->phase_delay = 0;
-+
-+	voltage_table->count = look_up_table->count;
-+
-+	for (i = 0; i < voltage_table->count; i++) {
-+		voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
-+		voltage_table->entries[i].smio_low = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
-+ * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
-+ */
-+
-+static void tonga_trim_voltage_table_to_fit_state_table(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t max_voltage_steps,
-+		pp_atomctrl_voltage_table *voltage_table)
-+{
-+	unsigned int i, diff;
-+
-+	if (voltage_table->count <= max_voltage_steps) {
-+		return;
-+	}
-+
-+	diff = voltage_table->count - max_voltage_steps;
-+
-+	for (i = 0; i < max_voltage_steps; i++) {
-+		voltage_table->entries[i] = voltage_table->entries[i + diff];
-+	}
-+
-+	voltage_table->count = max_voltage_steps;
-+
-+	return;
-+}
-+
-+/**
-+ * Create Voltage Tables.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result;
-+
-+	/* MVDD has only GPIO voltage control */
-+	if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+					VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to retrieve MVDD table.", return result;);
-+	}
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
-+		/* GPIO voltage */
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+					VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to retrieve VDDCI table.", return result;);
-+	} else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
-+		/* SVI2 voltage */
-+		result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
-+					pptable_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
-+	}
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
-+		/* VDDGFX has only SVI2 voltage control */
-+		result = tonga_get_svi2_vdd_voltage_table(hwmgr,
-+					pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
-+	}
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		/* VDDC has only SVI2 voltage control */
-+		result = tonga_get_svi2_vdd_voltage_table(hwmgr,
-+					pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
-+	}
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
-+			"Too many voltage values for VDDC. Trimming to fit state table.",
-+			tonga_trim_voltage_table_to_fit_state_table(hwmgr,
-+			SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
-+			);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
-+			"Too many voltage values for VDDGFX. Trimming to fit state table.",
-+			tonga_trim_voltage_table_to_fit_state_table(hwmgr,
-+			SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
-+			);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
-+			"Too many voltage values for VDDCI. Trimming to fit state table.",
-+			tonga_trim_voltage_table_to_fit_state_table(hwmgr,
-+			SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
-+			);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
-+			"Too many voltage values for MVDD. Trimming to fit state table.",
-+			tonga_trim_voltage_table_to_fit_state_table(hwmgr,
-+			SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
-+			);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Vddc table preparation for SMC.
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    table     the SMC DPM table structure to be populated
-+ * @return   always 0
-+ */
-+static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	unsigned int count;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		table->VddcLevelCount = data->vddc_voltage_table.count;
-+		for (count = 0; count < table->VddcLevelCount; count++) {
-+			table->VddcTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * VddGfx table preparation for SMC.
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    table     the SMC DPM table structure to be populated
-+ * @return   always 0
-+ */
-+static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	unsigned int count;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
-+		table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
-+		for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
-+			table->VddGfxTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * Vddci table preparation for SMC.
-+ *
-+ * @param    *hwmgr The address of the hardware manager.
-+ * @param    *table The SMC DPM table structure to be populated.
-+ * @return   0
-+ */
-+static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+
-+	table->VddciLevelCount = data->vddci_voltage_table.count;
-+	for (count = 0; count < table->VddciLevelCount; count++) {
-+		if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
-+			table->VddciTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		} else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
-+			table->SmioTable1.Pattern[count].Voltage =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
-+			table->SmioTable1.Pattern[count].Smio =
-+				(uint8_t) count;
-+			table->Smio[count] |=
-+				data->vddci_voltage_table.entries[count].smio_low;
-+			table->VddciTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		}
-+	}
-+
-+	table->SmioMask1 = data->vddci_voltage_table.mask_low;
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Mvdd table preparation for SMC.
-+ *
-+ * @param    *hwmgr The address of the hardware manager.
-+ * @param    *table The SMC DPM table structure to be populated.
-+ * @return   0
-+ */
-+static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		table->MvddLevelCount = data->mvdd_voltage_table.count;
-+		for (count = 0; count < table->MvddLevelCount; count++) {
-+			table->SmioTable2.Pattern[count].Voltage =
-+				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
-+			table->SmioTable2.Pattern[count].Smio =
-+				(uint8_t) count;
-+			table->Smio[count] |=
-+				data->mvdd_voltage_table.entries[count].smio_low;
-+		}
-+		table->SmioMask2 = data->vddci_voltage_table.mask_low;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Convert a voltage value in mv unit to VID number required by SMU firmware
-+ */
-+static uint8_t convert_to_vid(uint16_t vddc)
-+{
-+	return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-+}
-+
-+
-+/**
-+ * Preparation of vddc and vddgfx CAC tables for SMC.
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    table     the SMC DPM table structure to be populated
-+ * @return   always 0
-+ */
-+static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index;
-+	int result = 0;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
-+	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
-+
-+	/* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
-+	uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
-+	uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
-+
-+	for (count = 0; count < vddcLevelCount; count++) {
-+		/* We are populating vddc CAC data to BapmVddc table in split and merged mode */
-+		index = tonga_get_voltage_index(vddc_lookup_table,
-+			data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] =
-+			convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
-+		table->BapmVddcVidHiSidd[count] =
-+			convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
-+		table->BapmVddcVidHiSidd2[count] =
-+			convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
-+	}
-+
-+	if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
-+		/* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
-+		for (count = 0; count < vddgfxLevelCount; count++) {
-+			index = tonga_get_voltage_index(vddgfx_lookup_table,
-+				data->vddgfx_voltage_table.entries[count].value);
-+			table->BapmVddGfxVidLoSidd[count] =
-+				convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
-+			table->BapmVddGfxVidHiSidd[count] =
-+				convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
-+			table->BapmVddGfxVidHiSidd2[count] =
-+				convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
-+		}
-+	} else {
-+		for (count = 0; count < vddcLevelCount; count++) {
-+			index = tonga_get_voltage_index(vddc_lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+			table->BapmVddGfxVidLoSidd[count] =
-+				convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
-+			table->BapmVddGfxVidHiSidd[count] =
-+				convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
-+			table->BapmVddGfxVidHiSidd2[count] =
-+				convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+
-+/**
-+ * Preparation of voltage tables for SMC.
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    table     the SMC DPM table structure to be populated
-+ * @return   always 0
-+ */
-+
-+int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+	SMU72_Discrete_DpmTable *table)
-+{
-+	int result;
-+
-+	result = tonga_populate_smc_vddc_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDC voltage table to SMC", return -1);
-+
-+	result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDCI voltage table to SMC", return -1);
-+
-+	result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDGFX voltage table to SMC", return -1);
-+
-+	result = tonga_populate_smc_mvdd_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate MVDD voltage table to SMC", return -1);
-+
-+	result = tonga_populate_cac_tables(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate CAC voltage tables to SMC", return -1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Populates the SMC VRConfig field in DPM table.
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    table     the SMC DPM table structure to be populated
-+ * @return   always 0
-+ */
-+static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint16_t config;
-+
-+	if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
-+		/*  Splitted mode */
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
-+
-+		if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+			config = VR_SVI2_PLANE_2;
-+			table->VRConfig |= config;
-+		} else {
-+			printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
-+		}
-+	} else {
-+		/* Merged mode  */
-+		config = VR_MERGED_WITH_VDDC;
-+		table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
-+
-+		/* Set Vddc Voltage Controller  */
-+		if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+			config = VR_SVI2_PLANE_1;
-+			table->VRConfig |= config;
-+		} else {
-+			printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
-+		}
-+	}
-+
-+	/* Set Vddci Voltage Controller  */
-+	if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
-+	} else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
-+	}
-+
-+	/* Set Mvdd Voltage Controller */
-+	if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		config = VR_SMIO_PATTERN_2;
-+		table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
-+	phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
-+	uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i = 0;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (allowed_clock_voltage_table->count == 0)
-+		return -1;
-+
-+	for (i = 0; i < allowed_clock_voltage_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (allowed_clock_voltage_table->entries[i].clk >= clock) {
-+			voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+								allowed_clock_voltage_table->entries[i].vddgfx);
-+
-+			voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
-+								allowed_clock_voltage_table->entries[i].vddc);
-+
-+			if (allowed_clock_voltage_table->entries[i].vddci) {
-+				voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
-+									allowed_clock_voltage_table->entries[i].vddci);
-+			} else {
-+				voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
-+									allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
-+			}
-+
-+			if (allowed_clock_voltage_table->entries[i].mvdd) {
-+				*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
-+			}
-+
-+			voltage->Phases = 1;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+		allowed_clock_voltage_table->entries[i-1].vddgfx);
-+	voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
-+		allowed_clock_voltage_table->entries[i-1].vddc);
-+
-+	if (allowed_clock_voltage_table->entries[i-1].vddci) {
-+		voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
-+			allowed_clock_voltage_table->entries[i-1].vddci);
-+	}
-+	if (allowed_clock_voltage_table->entries[i-1].mvdd) {
-+		*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
-+{
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
-+}
-+
-+int tonga_populate_memory_timing_parameters(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock,
-+		uint32_t memory_clock,
-+		struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
-+		)
-+{
-+	uint32_t dramTiming;
-+	uint32_t dramTiming2;
-+	uint32_t burstTime;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+				engine_clock, memory_clock);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
-+	arb_regs->McArbBurstTime = (uint8_t)burstTime;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Setup parameters for the MC ARB.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ * This function is to be called from the SetPowerState table.
-+ */
-+int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	int result = 0;
-+	SMU72_Discrete_MCArbDramTimingTable  arb_regs;
-+	uint32_t i, j;
-+
-+	memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = tonga_populate_memory_timing_parameters
-+				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
-+				 data->dpm_table.mclk_table.dpm_levels[j].value,
-+				 &arb_regs.entries[i][j]);
-+
-+			if (0 != result) {
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (0 == result) {
-+		result = tonga_copy_bytes_to_smc(
-+				hwmgr->smumgr,
-+				data->arb_table_start,
-+				(uint8_t *)&arb_regs,
-+				sizeof(SMU72_Discrete_MCArbDramTimingTable),
-+				data->sram_end
-+				);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_dpm_table *dpm_table = &data->dpm_table;
-+	uint32_t i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount =
-+			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity =
-+			1;
-+		table->LinkLevel[i].SPC =
-+			(uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold =
-+			PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold =
-+			PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	data->smc_state_table.LinkLevelCount =
-+		(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+		tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+
-+static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
-+
-+	table->VceLevelCount = (uint8_t) (mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency =
-+			mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage.Vddc =
-+			tonga_get_voltage_index(pptable_info->vddc_lookup_table,
-+				mm_table->entries[count].vddc);
-+		table->VceLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
-+			tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+				mm_table->entries[count].vddgfx) : 0;
-+		table->VceLevel[count].MinVoltage.Vddci =
-+			tonga_get_voltage_id(&data->vddci_voltage_table,
-+				mm_table->entries[count].vddc - data->vddc_vddci_delta);
-+		table->VceLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+					table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock", return result);
-+
-+		table->VceLevel[count].Divider    = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
-+
-+	table->AcpLevelCount = (uint8_t) (mm_table->count);
-+	table->AcpBootLevel = 0;
-+
-+	for (count = 0; count < table->AcpLevelCount; count++) {
-+		table->AcpLevel[count].Frequency =
-+			pptable_info->mm_dep_table->entries[count].aclk;
-+		table->AcpLevel[count].MinVoltage.Vddc =
-+			tonga_get_voltage_index(pptable_info->vddc_lookup_table,
-+			mm_table->entries[count].vddc);
-+		table->AcpLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
-+			tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+				mm_table->entries[count].vddgfx) : 0;
-+		table->AcpLevel[count].MinVoltage.Vddci =
-+			tonga_get_voltage_id(&data->vddci_voltage_table,
-+				mm_table->entries[count].vddc - data->vddc_vddci_delta);
-+		table->AcpLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+			table->AcpLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find divide id for engine clock", return result);
-+
-+		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+	SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t) (mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].Frequency =
-+			pptable_info->mm_dep_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage.Vddc =
-+			tonga_get_voltage_index(pptable_info->vddc_lookup_table,
-+				mm_table->entries[count].vddc);
-+		table->SamuLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
-+			tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+				mm_table->entries[count].vddgfx) : 0;
-+		table->SamuLevel[count].MinVoltage.Vddci =
-+			tonga_get_voltage_id(&data->vddci_voltage_table,
-+				mm_table->entries[count].vddc - data->vddc_vddci_delta);
-+		table->SamuLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+					table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider     = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Populates the SMC MCLK structure using the provided memory clock
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    memory_clock the memory clock to use to populate the structure
-+ * @param    sclk        the SMC SCLK structure to be populated
-+ */
-+static int tonga_calculate_mclk_params(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU72_Discrete_MemoryLevel *mclk,
-+		bool strobe_mode,
-+		bool dllStateOn
-+		)
-+{
-+	const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
-+	uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+	uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
-+	uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
-+	uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
-+	uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
-+	uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
-+	uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
-+
-+	pp_atomctrl_memory_clock_param mpll_param;
-+	int result;
-+
-+	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
-+				memory_clock, &mpll_param, strobe_mode);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Error retrieving Memory Clock Parameters from VBIOS.", return result);
-+
-+	/* MPLL_FUNC_CNTL setup*/
-+	mpll_func_cntl    = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
-+
-+	/* MPLL_FUNC_CNTL_1 setup*/
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
-+
-+	/* MPLL_AD_FUNC_CNTL setup*/
-+	mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
-+							MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-+
-+	if (data->is_memory_GDDR5) {
-+		/* MPLL_DQ_FUNC_CNTL setup*/
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+								MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+								MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
-+		/*
-+		 ************************************
-+		 Fref = Reference Frequency
-+		 NF = Feedback divider ratio
-+		 NR = Reference divider ratio
-+		 Fnom = Nominal VCO output frequency = Fref * NF / NR
-+		 Fs = Spreading Rate
-+		 D = Percentage down-spread / 2
-+		 Fint = Reference input frequency to PFD = Fref / NR
-+		 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
-+		 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
-+		 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
-+		 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
-+		 *************************************
-+		 */
-+		pp_atomctrl_internal_ss_info ss_info;
-+		uint32_t freq_nom;
-+		uint32_t tmp;
-+		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
-+
-+		/* for GDDR5 for all modes and DDR3 */
-+		if (1 == mpll_param.qdr)
-+			freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
-+		else
-+			freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
-+
-+		/* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
-+		tmp = (freq_nom / reference_clock);
-+		tmp = tmp * tmp;
-+
-+		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
-+			/* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
-+			/* ss.Info.speed_spectrum_rate -- in unit of khz */
-+			/* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
-+			/*     = reference_clock * 5 / speed_spectrum_rate */
-+			uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
-+
-+			/* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
-+			/*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
-+			uint32_t clkv =
-+				(uint32_t)((((131 * ss_info.speed_spectrum_percentage *
-+							ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
-+
-+			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
-+			mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
-+		}
-+	}
-+
-+	/* MCLK_PWRMGT_CNTL setup */
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
-+
-+
-+	/* Save the result data to outpupt memory level structure */
-+	mclk->MclkFrequency   = memory_clock;
-+	mclk->MpllFuncCntl    = mpll_func_cntl;
-+	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
-+	mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
-+	mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
-+	mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
-+	mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
-+	mclk->DllCntl         = dll_cntl;
-+	mclk->MpllSs1         = mpll_ss1;
-+	mclk->MpllSs2         = mpll_ss2;
-+
-+	return 0;
-+}
-+
-+static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
-+		bool strobe_mode)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (strobe_mode) {
-+		if (memory_clock < 12500) {
-+			mc_para_index = 0x00;
-+		} else if (memory_clock > 47500) {
-+			mc_para_index = 0x0f;
-+		} else {
-+			mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
-+		}
-+	} else {
-+		if (memory_clock < 65000) {
-+			mc_para_index = 0x00;
-+		} else if (memory_clock > 135000) {
-+			mc_para_index = 0x0f;
-+		} else {
-+			mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
-+		}
-+	}
-+
-+	return mc_para_index;
-+}
-+
-+static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (memory_clock < 10000) {
-+		mc_para_index = 0;
-+	} else if (memory_clock >= 80000) {
-+		mc_para_index = 0x0f;
-+	} else {
-+		mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
-+	}
-+
-+	return mc_para_index;
-+}
-+
-+static int tonga_populate_single_memory_level(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU72_Discrete_MemoryLevel *memory_level
-+		)
-+{
-+	uint32_t minMvdd = 0;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+	bool dllStateOn;
-+	struct cgs_display_info info = {0};
-+
-+
-+	if (NULL != pptable_info->vdd_dep_on_mclk) {
-+		result = tonga_get_dependecy_volt_by_clk(hwmgr,
-+			pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
-+	}
-+
-+	if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
-+		memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	} else {
-+		memory_level->MinMvdd = minMvdd;
-+	}
-+	memory_level->EnabledForThrottle = 1;
-+	memory_level->EnabledForActivity = 0;
-+	memory_level->UpHyst = 0;
-+	memory_level->DownHyst = 100;
-+	memory_level->VoltageDownHyst = 0;
-+
-+	/* Indicates maximum activity level for this performance level.*/
-+	memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	memory_level->StutterEnable = 0;
-+	memory_level->StrobeEnable = 0;
-+	memory_level->EdcReadEnable = 0;
-+	memory_level->EdcWriteEnable = 0;
-+	memory_level->RttEnable = 0;
-+
-+	/* default set to low watermark. Highest level will be set to high later.*/
-+	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	if ((data->mclk_stutter_mode_threshold != 0) &&
-+			(memory_clock <= data->mclk_stutter_mode_threshold) &&
-+			(data->is_uvd_enabled == 0)
-+#if defined(LINUX)
-+			&& (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
-+			&& (data->display_timing.num_existing_displays <= 2)
-+			&& (data->display_timing.num_existing_displays != 0)
-+#endif
-+	)
-+		memory_level->StutterEnable = 1;
-+
-+	/* decide strobe mode*/
-+	memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
-+		(memory_clock <= data->mclk_strobe_mode_threshold);
-+
-+	/* decide EDC mode and memory clock ratio*/
-+	if (data->is_memory_GDDR5) {
-+		memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
-+					memory_level->StrobeEnable);
-+
-+		if ((data->mclk_edc_enable_threshold != 0) &&
-+				(memory_clock > data->mclk_edc_enable_threshold)) {
-+			memory_level->EdcReadEnable = 1;
-+		}
-+
-+		if ((data->mclk_edc_wr_enable_threshold != 0) &&
-+				(memory_clock > data->mclk_edc_wr_enable_threshold)) {
-+			memory_level->EdcWriteEnable = 1;
-+		}
-+
-+		if (memory_level->StrobeEnable) {
-+			if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
-+					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
-+				dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+			} else {
-+				dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
-+			}
-+
-+		} else {
-+			dllStateOn = data->dll_defaule_on;
-+		}
-+	} else {
-+		memory_level->StrobeRatio =
-+			tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
-+		dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+	}
-+
-+	result = tonga_calculate_mclk_params(hwmgr,
-+		memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
-+
-+	if (0 == result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
-+		/* MCLK frequency in units of 10KHz*/
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
-+		/* Indicates maximum activity level for this performance level.*/
-+		CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Populates the SMC MVDD structure using the provided memory clock.
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
-+ * @param    voltage     the SMC VOLTAGE structure to be populated
-+ */
-+int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
-+{
-+	const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
-+				/* Always round to higher voltage. */
-+				smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+
-+		PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
-+			"MVDD Voltage is outside the supported range.", return -1);
-+
-+	} else {
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
-+	SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	SMIO_Pattern voltage_level;
-+	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
-+	uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+
-+	/* The ACPI state should not do DPM on DC (or ever).*/
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
-+
-+	/* assign zero for now*/
-+	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
-+		table->ACPILevel.SclkFrequency,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	/* divider ID for required SCLK*/
-+	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
-+	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+	table->ACPILevel.DeepSleepDivId = 0;
-+
-+	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
-+							CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
-+	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
-+							CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
-+	spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
-+							CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
-+
-+	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-+	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-+	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+
-+	/* For various features to be enabled/disabled while this level is active.*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	/* SCLK frequency in units of 10KHz*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	/* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
-+	table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
-+
-+	/*  CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
-+
-+	if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
-+		table->MemoryACPILevel.MinMvdd =
-+			PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	/* Force reset on DLL*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
-+
-+	/* Disable DLL in ACPIState*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
-+
-+	/* Enable DLL bypass signal*/
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK0_BYPASS, 0);
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK1_BYPASS, 0);
-+
-+	table->MemoryACPILevel.DllCntl            =
-+		PP_HOST_TO_SMC_UL(dll_cntl);
-+	table->MemoryACPILevel.MclkPwrmgtCntl     =
-+		PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
-+	table->MemoryACPILevel.MpllAdFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllDqFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl       =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl_1     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
-+	table->MemoryACPILevel.MpllFuncCntl_2     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
-+	table->MemoryACPILevel.MpllSs1            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
-+	table->MemoryACPILevel.MpllSs2            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	/* Indicates maximum activity level for this performance level.*/
-+	table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	table->MemoryACPILevel.StutterEnable = 0;
-+	table->MemoryACPILevel.StrobeEnable = 0;
-+	table->MemoryACPILevel.EdcReadEnable = 0;
-+	table->MemoryACPILevel.EdcWriteEnable = 0;
-+	table->MemoryACPILevel.RttEnable = 0;
-+
-+	return result;
-+}
-+
-+static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
-+{
-+	int result = 0;
-+	uint32_t i;
-+
-+	for (i = 0; i < table->count; i++) {
-+		if (value == table->dpm_levels[i].value) {
-+			*boot_level = i;
-+			result = 0;
-+		}
-+	}
-+	return result;
-+}
-+
-+static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	table->GraphicsBootLevel  = 0;        /* 0 == DPM[0] (low), etc. */
-+	table->MemoryBootLevel    = 0;        /* 0 == DPM[0] (low), etc. */
-+
-+	/* find boot level from dpm table*/
-+	result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
-+	data->vbios_boot_state.sclk_bootup_value,
-+	(uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
-+
-+	if (0 != result) {
-+		data->smc_state_table.GraphicsBootLevel = 0;
-+		printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
-+			in dependency table. Using Graphics DPM level 0!");
-+		result = 0;
-+	}
-+
-+	result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
-+		data->vbios_boot_state.mclk_bootup_value,
-+		(uint32_t *)&(data->smc_state_table.MemoryBootLevel));
-+
-+	if (0 != result) {
-+		data->smc_state_table.MemoryBootLevel = 0;
-+		printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
-+			in dependency table. Using Memory DPM level 0!");
-+		result = 0;
-+	}
-+
-+	table->BootVoltage.Vddc =
-+		tonga_get_voltage_id(&(data->vddc_voltage_table),
-+			data->vbios_boot_state.vddc_bootup_value);
-+	table->BootVoltage.VddGfx =
-+		tonga_get_voltage_id(&(data->vddgfx_voltage_table),
-+			data->vbios_boot_state.vddgfx_bootup_value);
-+	table->BootVoltage.Vddci =
-+		tonga_get_voltage_id(&(data->vddci_voltage_table),
-+			data->vbios_boot_state.vddci_bootup_value);
-+	table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return result;
-+}
-+
-+
-+/**
-+ * Calculates the SCLK dividers using the provided engine clock
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    engine_clock the engine clock to use to populate the structure
-+ * @param    sclk        the SMC SCLK structure to be populated
-+ */
-+int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
-+{
-+	const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t    reference_clock;
-+	uint32_t reference_divider;
-+	uint32_t fbdiv;
-+	int result;
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
-+	reference_clock = atomctrl_get_reference_clock(hwmgr);
-+
-+	reference_divider = 1 + dividers.uc_pll_ref_div;
-+
-+	/* low 14 bits is fraction and high 12 bits is divider*/
-+	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-+
-+	/* SPLL_FUNC_CNTL setup*/
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
-+		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
-+		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
-+
-+	/* SPLL_FUNC_CNTL_3 setup*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
-+		CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
-+
-+	/* set to use fractional accumulation*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
-+		CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
-+		pp_atomctrl_internal_ss_info ss_info;
-+
-+		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
-+		if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
-+			/*
-+			* ss_info.speed_spectrum_percentage -- in unit of 0.01%
-+			* ss_info.speed_spectrum_rate -- in unit of khz
-+			*/
-+			/* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
-+			uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
-+
-+			/* clkv = 2 * D * fbdiv / NS */
-+			uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
-+
-+			cg_spll_spread_spectrum =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
-+			cg_spll_spread_spectrum =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
-+			cg_spll_spread_spectrum_2 =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
-+		}
-+	}
-+
-+	sclk->SclkFrequency        = engine_clock;
-+	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
-+	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
-+	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
-+	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-+	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Populates single SMC SCLK structure using the provided engine clock
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ * @param    engine_clock the engine clock to use to populate the structure
-+ * @param    sclk        the SMC SCLK structure to be populated
-+ */
-+static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
-+{
-+	int result;
-+	uint32_t threshold;
-+	uint32_t mvdd;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
-+
-+
-+	/* populate graphics levels*/
-+	result = tonga_get_dependecy_volt_by_clk(hwmgr,
-+		pptable_info->vdd_dep_on_sclk, engine_clock,
-+		&graphic_level->MinVoltage, &mvdd);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+		"can not find VDDC voltage value for VDDC	\
-+		engine clock dependency table", return result);
-+
-+	/* SCLK frequency in units of 10KHz*/
-+	graphic_level->SclkFrequency = engine_clock;
-+
-+	/* Indicates maximum activity level for this performance level. 50% for now*/
-+	graphic_level->ActivityLevel = sclk_activity_level_threshold;
-+
-+	graphic_level->CcPwrDynRm = 0;
-+	graphic_level->CcPwrDynRm1 = 0;
-+	/* this level can be used if activity is high enough.*/
-+	graphic_level->EnabledForActivity = 0;
-+	/* this level can be used for throttling.*/
-+	graphic_level->EnabledForThrottle = 1;
-+	graphic_level->UpHyst = 0;
-+	graphic_level->DownHyst = 0;
-+	graphic_level->VoltageDownHyst = 0;
-+	graphic_level->PowerThrottle = 0;
-+
-+	threshold = engine_clock * data->fast_watemark_threshold / 100;
-+/*
-+	*get the DAL clock. do it in funture.
-+	PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
-+	data->display_timing.min_clock_insr = minClocks.engineClockInSR;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+	{
-+		graphic_level->DeepSleepDivId = PhwTonga_GetSleepDividerIdFromClock(hwmgr, engine_clock, minClocks.engineClockInSR);
-+	}
-+*/
-+
-+	/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
-+	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	if (0 == result) {
-+		/* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
-+		/* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ */
-+static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct tonga_dpm_table *dpm_table = &data->dpm_table;
-+	phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
-+	uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
-+	int result = 0;
-+	uint32_t level_array_adress = data->dpm_table_start +
-+		offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
-+		SMU72_MAX_LEVELS_GRAPHICS;   /* 64 -> long; 32 -> int*/
-+	SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
-+	uint32_t i, maxEntry;
-+	uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
-+	PECI_RegistryValue reg_value;
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		result = tonga_populate_single_graphic_level(hwmgr,
-+					dpm_table->sclk_table.dpm_levels[i].value,
-+					(uint16_t)data->activity_target[i],
-+					&(data->smc_state_table.GraphicsLevel[i]));
-+
-+		if (0 != result)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
-+
-+		if (0 == i) {
-+			reg_value = 0;
-+			if (reg_value != 0)
-+				data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
-+		}
-+
-+		if (1 == i) {
-+			reg_value = 0;
-+			if (reg_value != 0)
-+				data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
-+		}
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+
-+	/* set highest level watermark to high */
-+	if (dpm_table->sclk_table.count > 1)
-+		data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	data->smc_state_table.GraphicsDpmLevelCount =
-+		(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+		tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
-+			"There must be 1 or more PCIE levels defined in PPTable.", return -1);
-+		maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
-+		for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+			data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
-+				(uint8_t) ((i < maxEntry) ? i : maxEntry);
-+		}
-+	} else {
-+		if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
-+			printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+					(1<<(highest_pcie_level_enabled+1))) != 0)) {
-+			highest_pcie_level_enabled++;
-+		}
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+					(1<<lowest_pcie_level_enabled)) == 0)) {
-+			lowest_pcie_level_enabled++;
-+		}
-+
-+		while ((count < highest_pcie_level_enabled) &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+					(1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
-+			count++;
-+		}
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
-+			(lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
-+
-+
-+		/* set pcieDpmLevel to highest_pcie_level_enabled*/
-+		for (i = 2; i < dpm_table->sclk_table.count; i++) {
-+			data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
-+		}
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled*/
-+		data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled*/
-+		data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change*/
-+	result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
-+
-+	if (0 != result)
-+		return result;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
-+ *
-+ * @param    hwmgr      the address of the hardware manager
-+ */
-+
-+static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
-+	uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
-+	SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+			"can not populate memory level as memory clock is zero", return -1);
-+		result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
-+			&(data->smc_state_table.MemoryLevel[i]));
-+		if (0 != result) {
-+			return result;
-+		}
-+	}
-+
-+	/* Only enable level 0 for now.*/
-+	data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-+
-+	/*
-+	* in order to prevent MC activity from stutter mode to push DPM up.
-+	* the UVD change complements this by putting the MCLK in a higher state
-+	* by default such that we are not effected by up threshold or and MCLK DPM latency.
-+	*/
-+	data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
-+
-+	data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high*/
-+	data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change*/
-+	result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
-+		level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
-+
-+	if (0 != result) {
-+		return result;
-+	}
-+
-+	return 0;
-+}
-+
-+struct TONGA_DLL_SPEED_SETTING {
-+	uint16_t            Min;                          /* Minimum Data Rate*/
-+	uint16_t            Max;                          /* Maximum Data Rate*/
-+	uint32_t 			dll_speed;                     /* The desired DLL_SPEED setting*/
-+};
-+
-+static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	return 0;
-+}
-+
-+/* ---------------------------------------- ULV related functions ----------------------------------------------------*/
-+
-+
-+static int tonga_reset_single_dpm_table(
-+	struct pp_hwmgr *hwmgr,
-+	struct tonga_single_dpm_table *dpm_table,
-+	uint32_t count)
-+{
-+	uint32_t i;
-+	if (!(count <= MAX_REGULAR_DPM_NUMBER))
-+		printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
-+			table entries to exceed max number! \n");
-+
-+	dpm_table->count = count;
-+	for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
-+		dpm_table->dpm_levels[i].enabled = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static void tonga_setup_pcie_table_entry(
-+	struct tonga_single_dpm_table *dpm_table,
-+	uint32_t index, uint32_t pcie_gen,
-+	uint32_t pcie_lanes)
-+{
-+	dpm_table->dpm_levels[index].value = pcie_gen;
-+	dpm_table->dpm_levels[index].param1 = pcie_lanes;
-+	dpm_table->dpm_levels[index].enabled = 1;
-+}
-+
-+bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
-+{
-+	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
-+{
-+	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
-+uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen)
-+{
-+	uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
-+		CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
-+	uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
-+		CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
-+
-+	switch (asic_pcie_link_speed_cap) {
-+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
-+		return PP_PCIEGen1;
-+
-+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
-+		return PP_PCIEGen2;
-+
-+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
-+		return PP_PCIEGen3;
-+
-+	default:
-+		if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
-+			(ns_pcie_gen == PP_PCIEGen3)) {
-+			return PP_PCIEGen3;
-+		} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
-+			((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
-+			return PP_PCIEGen2;
-+		}
-+	}
-+
-+	return PP_PCIEGen1;
-+}
-+
-+uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes)
-+{
-+	int i, j;
-+	uint16_t new_pcie_lanes = ns_pcie_lanes;
-+	uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
-+
-+	switch (pcie_lane_width_cap) {
-+	case 0:
-+		printk(KERN_ERR "[ powerplay ] No valid PCIE lane width reported by CAIL!");
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
-+		new_pcie_lanes = 1;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
-+		new_pcie_lanes = 2;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
-+		new_pcie_lanes = 4;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
-+		new_pcie_lanes = 8;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
-+		new_pcie_lanes = 12;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
-+		new_pcie_lanes = 16;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
-+		new_pcie_lanes = 32;
-+		break;
-+	default:
-+		for (i = 0; i < 7; i++) {
-+			if (ns_pcie_lanes == pcie_lanes[i]) {
-+				if (pcie_lane_width_cap & (0x10000 << i)) {
-+					break;
-+				} else {
-+					for (j = i - 1; j >= 0; j--) {
-+						if (pcie_lane_width_cap & (0x10000 << j)) {
-+							new_pcie_lanes = pcie_lanes[j];
-+							break;
-+						}
-+					}
-+
-+					if (j < 0) {
-+						for (j = i + 1; j < 7; j++) {
-+							if (pcie_lane_width_cap & (0x10000 << j)) {
-+								new_pcie_lanes = pcie_lanes[j];
-+								break;
-+							}
-+						}
-+						if (j > 7)
-+							printk(KERN_ERR "[ powerplay ] Cannot find a valid PCIE lane width!");
-+					}
-+				}
-+				break;
-+			}
-+		}
-+		break;
-+	}
-+
-+	return new_pcie_lanes;
-+}
-+
-+static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
-+	uint32_t i, maxEntry;
-+
-+	if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_power_saving = data->pcie_gen_performance;
-+		data->pcie_lane_power_saving = data->pcie_lane_performance;
-+	} else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_performance = data->pcie_gen_power_saving;
-+		data->pcie_lane_performance = data->pcie_lane_power_saving;
-+	}
-+
-+	tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
-+
-+	if (pcie_table != NULL) {
-+		/*
-+		* maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
-+		* If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
-+		*/
-+		maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
-+						SMU72_MAX_LEVELS_LINK : pcie_table->count;
-+		for (i = 1; i < maxEntry; i++) {
-+			tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
-+				get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
-+				get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		}
-+		data->dpm_table.pcie_speed_table.count = maxEntry - 1;
-+	} else {
-+		/* Hardcode Pcie Table */
-+		tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
-+			get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
-+			get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
-+			get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
-+			get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
-+			get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
-+			get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+		data->dpm_table.pcie_speed_table.count = 6;
-+	}
-+	/* Populate last level for boot PCIE level, but do not increment count. */
-+	tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
-+		data->dpm_table.pcie_speed_table.count,
-+		get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
-+		get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
-+
-+	return 0;
-+
-+}
-+
-+/*
-+ * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
-+ * Dynamic state patching function will then trim these state tables to the allowed range based
-+ * on the power policy or external client requests, such as UVD request, etc.
-+ */
-+static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i;
-+
-+	phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
-+		pptable_info->vdd_dep_on_sclk;
-+	phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
-+		pptable_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
-+		"SCLK dependency table is missing. This table is mandatory", return -1);
-+	PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
-+		"SCLK dependency table has to have is missing. This table is mandatory", return -1);
-+
-+	PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
-+		"MCLK dependency table is missing. This table is mandatory", return -1);
-+	PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
-+		"VMCLK dependency table has to have is missing. This table is mandatory", return -1);
-+
-+	/* clear the state table to reset everything to default */
-+	memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
-+	tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
-+	tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
-+	/* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
-+	/* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
-+	/* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
-+	/* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
-+
-+	PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
-+		"SCLK dependency table is missing. This table is mandatory", return -1);
-+	/* Initialize Sclk DPM table based on allow Sclk values*/
-+	data->dpm_table.sclk_table.count = 0;
-+
-+	for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
-+				allowed_vdd_sclk_table->entries[i].clk) {
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
-+				allowed_vdd_sclk_table->entries[i].clk;
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
-+			data->dpm_table.sclk_table.count++;
-+		}
-+	}
-+
-+	PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
-+		"MCLK dependency table is missing. This table is mandatory", return -1);
-+	/* Initialize Mclk DPM table based on allow Mclk values */
-+	data->dpm_table.mclk_table.count = 0;
-+	for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
-+			allowed_vdd_mclk_table->entries[i].clk) {
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
-+				allowed_vdd_mclk_table->entries[i].clk;
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
-+			data->dpm_table.mclk_table.count++;
-+		}
-+	}
-+
-+	/* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
-+	for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
-+		data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
-+		/* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
-+		/* param1 is for corresponding std voltage */
-+		data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
-+	}
-+	data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
-+
-+	if (NULL != allowed_vdd_mclk_table) {
-+		/* Initialize Vddci DPM table based on allow Mclk values */
-+		for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
-+			data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
-+			data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
-+			data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
-+			data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
-+		}
-+		data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
-+		data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
-+	}
-+
-+	/* setup PCIE gen speed levels*/
-+	tonga_setup_default_pcie_tables(hwmgr);
-+
-+	/* save a copy of the default DPM table*/
-+	memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
-+
-+	return 0;
-+}
-+
-+int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
-+		const struct tonga_power_state *bootState)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint8_t count, level;
-+
-+	count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
-+			bootState->performance_levels[0].engine_clock) {
-+			data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
-+			bootState->performance_levels[0].memory_clock) {
-+			data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initializes the SMC table and uploads it
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @param    pInput  the pointer to input data (PowerState)
-+ * @return   always 0
-+ */
-+int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMU72_Discrete_DpmTable  *table = &(data->smc_state_table);
-+	const phw_tonga_ulv_parm *ulv = &(data->ulv);
-+	uint8_t i;
-+	PECI_RegistryValue reg_value;
-+	pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
-+
-+	result = tonga_setup_default_dpm_tables(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to setup default DPM tables!", return result;);
-+	memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
-+	if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
-+		tonga_populate_smc_voltage_tables(hwmgr, table);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition)) {
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc)) {
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+	}
-+
-+	if (data->is_memory_GDDR5) {
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+	}
-+
-+	i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
-+
-+	if (i == 1 || i == 0) {
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
-+	}
-+
-+	if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
-+		PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ULV state!", return result;);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
-+	}
-+
-+	result = tonga_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Link Level!", return result;);
-+
-+	result = tonga_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Graphics Level!", return result;);
-+
-+	result = tonga_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Memory Level!", return result;);
-+
-+	result = tonga_populate_smv_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize ACPI Level!", return result;);
-+
-+	result = tonga_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize VCE Level!", return result;);
-+
-+	result = tonga_populate_smc_acp_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize ACP Level!", return result;);
-+
-+	result = tonga_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize SAMU Level!", return result;);
-+
-+	/* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
-+	/* need to populate the  ARB settings for the initial state. */
-+	result = tonga_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to Write ARB settings for the initial state.", return result;);
-+
-+	result = tonga_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Boot Level!", return result;);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = tonga_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate Clock Stretcher Data Table!", return result;);
-+	}
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+		pptable_info->cac_dtp_table->usTargetOperatingTemp *
-+		TONGA_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow =
-+		(pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+		TONGA_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable  = 1;
-+	table->MemoryInterval  = 1;
-+	table->VoltageResponseTime  = 0;
-+	table->PhaseResponseTime  = 0;
-+	table->MemoryThermThrottleEnable  = 1;
-+
-+	/*
-+	* Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
-+	* SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
-+	* but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
-+	* To avoid it, we set PCIeBootLinkLevel to highest dpm level
-+	*/
-+	PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
-+			"There must be 1 or more PCIE levels defined in PPTable.",
-+			return -1);
-+
-+	table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
-+
-+	table->PCIeGenInterval  = 1;
-+
-+	result = tonga_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to populate VRConfig setting!", return result);
-+
-+	table->ThermGpio  = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	reg_value = 0;
-+	if ((0 == reg_value) &&
-+		(0 == atomctrl_get_pp_assign_pin(hwmgr,
-+			VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
-+		table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot);
-+	} else {
-+		table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	/* ACDC Switch GPIO */
-+	reg_value = 0;
-+	if ((0 == reg_value) &&
-+		(0 == atomctrl_get_pp_assign_pin(hwmgr,
-+			PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
-+		table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_Falcon_QuickTransition);
-+
-+	reg_value = 0;
-+	if (1 == reg_value) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition);
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_Falcon_QuickTransition);
-+	}
-+
-+	reg_value = 0;
-+	if ((0 == reg_value) &&
-+		(0 == atomctrl_get_pp_assign_pin(hwmgr,
-+			THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-+
-+		table->ThermOutPolarity =
-+			(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
-+			(1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
-+
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO*/
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot) &&
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_CombinePCCWithThermalSignal)){
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+		}
-+	} else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+	}
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
-+										offsetof(SMU72_Discrete_DpmTable, SystemFlags),
-+										(uint8_t *)&(table->SystemFlags),
-+										sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
-+										data->sram_end);
-+
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to upload dpm data to SMC memory!", return result;);
-+
-+	return result;
-+}
-+
-+/* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
-+static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
-+{
-+	return;
-+}
-+
-+int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
-+{
-+	PPSMC_Result result;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* Apply minimum voltage based on DAL's request level */
-+	tonga_apply_dal_minimum_voltage_request(hwmgr);
-+
-+	if (0 == data->sclk_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
-+		if (0 != tonga_is_dpm_running(hwmgr))
-+			printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
-+
-+		if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			result = smum_send_msg_to_smc_with_parameter(
-+								hwmgr->smumgr,
-+				(PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+				data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+			PP_ASSERT_WITH_CODE((0 == result),
-+				"Set Sclk Dpm enable Mask failed", return -1);
-+		}
-+	}
-+
-+	if (0 == data->mclk_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
-+		if (0 != tonga_is_dpm_running(hwmgr))
-+			printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
-+
-+		if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			result = smum_send_msg_to_smc_with_parameter(
-+								hwmgr->smumgr,
-+				(PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+				data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+			PP_ASSERT_WITH_CODE((0 == result),
-+				"Set Mclk Dpm enable Mask failed", return -1);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+
-+int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t level, tmp;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		/* PCIE */
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++ ;
-+
-+			if (0 != level) {
-+				PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
-+					"force highest pcie dpm state failed!", return -1);
-+			}
-+		}
-+	}
-+
-+	if (0 == data->sclk_dpm_key_disabled) {
-+		/* SCLK */
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++ ;
-+
-+			if (0 != level) {
-+				PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
-+					"force highest sclk dpm state failed!", return -1);
-+				if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-+					CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
-+					printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
-+						Curr_Sclk_Index does not match the level \n");
-+
-+			}
-+		}
-+	}
-+
-+	if (0 == data->mclk_dpm_key_disabled) {
-+		/* MCLK */
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++ ;
-+
-+			if (0 != level) {
-+				PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
-+					"force highest mclk dpm state failed!", return -1);
-+				if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+					TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
-+					printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
-+						Curr_Sclk_Index does not match the level \n");
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Find the MC microcode version and store it in the HwMgr struct
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
-+{
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
-+
-+	hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initialize Dynamic State Adjustment Rule Settings
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ */
-+int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t table_size;
-+	struct phm_clock_voltage_dependency_table *table_clk_vlt;
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	hwmgr->dyn_state.mclk_sclk_ratio = 4;
-+	hwmgr->dyn_state.sclk_mclk_delta = 15000;      /* 150 MHz */
-+	hwmgr->dyn_state.vddc_vddci_delta = 200;       /* 200mV */
-+
-+	/* initialize vddc_dep_on_dal_pwrl table */
-+	table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
-+	table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == table_clk_vlt) {
-+		printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
-+		return -ENOMEM;
-+	} else {
-+		table_clk_vlt->count = 4;
-+		table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
-+		table_clk_vlt->entries[0].v = 0;
-+		table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
-+		table_clk_vlt->entries[1].v = 720;
-+		table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
-+		table_clk_vlt->entries[2].v = 810;
-+		table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
-+		table_clk_vlt->entries[3].v = 900;
-+		pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
-+		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
-+		pptable_info->vdd_dep_on_sclk;
-+	phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
-+		pptable_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-+		"VDD dependency on SCLK table is missing. 	\
-+		This table is mandatory", return -1);
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-+		"VDD dependency on SCLK table has to have is missing. 	\
-+		This table is mandatory", return -1);
-+
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-+		"VDD dependency on MCLK table is missing. 	\
-+		This table is mandatory", return -1);
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
-+		"VDD dependency on MCLK table has to have is missing.	 \
-+		This table is mandatory", return -1);
-+
-+	data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
-+	data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
-+
-+	pptable_info->max_clock_voltage_on_ac.sclk =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
-+	pptable_info->max_clock_voltage_on_ac.mclk =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
-+	pptable_info->max_clock_voltage_on_ac.vddc =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
-+	pptable_info->max_clock_voltage_on_ac.vddci =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
-+
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
-+		pptable_info->max_clock_voltage_on_ac.sclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
-+		pptable_info->max_clock_voltage_on_ac.mclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
-+		pptable_info->max_clock_voltage_on_ac.vddc;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
-+		pptable_info->max_clock_voltage_on_ac.vddci;
-+
-+	return 0;
-+}
-+
-+int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	int result = 1;
-+
-+	PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
-+		"Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
-+							return result);
-+
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
-+							     hwmgr->smumgr,
-+					PPSMC_MSG_PCIeDPM_UnForceLevel)),
-+					   "unforce pcie level failed!",
-+								return -1);
-+	}
-+
-+	result = tonga_upload_dpm_level_enable_mask(hwmgr);
-+
-+	return result;
-+}
-+
-+static uint32_t tonga_get_lowest_enable_level(
-+				struct pp_hwmgr *hwmgr, uint32_t level_mask)
-+{
-+	uint32_t level = 0;
-+
-+	while (0 == (level_mask & (1 << level)))
-+		level++;
-+
-+	return level;
-+}
-+
-+static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t level = 0;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* for now force only sclk */
-+	if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+		level = tonga_get_lowest_enable_level(hwmgr,
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+
-+		PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
-+			"force sclk dpm state failed!", return -1);
-+
-+		if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
-+			printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index.	\
-+				Curr_Sclk_Index does not match the level \n");
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
-+	phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
-+
-+	if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
-+		for (entryId = 0; entryId < sclk_table->count; ++entryId) {
-+			voltageId = sclk_table->entries[entryId].vddInd;
-+			sclk_table->entries[entryId].vddgfx =
-+				pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
-+		}
-+	} else {
-+		for (entryId = 0; entryId < sclk_table->count; ++entryId) {
-+			voltageId = sclk_table->entries[entryId].vddInd;
-+			sclk_table->entries[entryId].vddc =
-+				pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+		}
-+	}
-+
-+	for (entryId = 0; entryId < mclk_table->count; ++entryId) {
-+		voltageId = mclk_table->entries[entryId].vddInd;
-+		mclk_table->entries[entryId].vddc =
-+			pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mm_table->count; ++entryId) {
-+		voltageId = mm_table->entries[entryId].vddcInd;
-+		mm_table->entries[entryId].vddc =
-+			pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	return 0;
-+
-+}
-+
-+static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	uint8_t entryId;
-+	phm_ppt_v1_voltage_lookup_record v_record;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
-+	phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
-+
-+	if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
-+		for (entryId = 0; entryId < sclk_table->count; ++entryId) {
-+			if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
-+				v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
-+					sclk_table->entries[entryId].vdd_offset - 0xFFFF;
-+			else
-+				v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
-+					sclk_table->entries[entryId].vdd_offset;
-+
-+			sclk_table->entries[entryId].vddc =
-+				v_record.us_cac_low = v_record.us_cac_mid =
-+				v_record.us_cac_high = v_record.us_vdd;
-+
-+			tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
-+		}
-+
-+		for (entryId = 0; entryId < mclk_table->count; ++entryId) {
-+			if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
-+				v_record.us_vdd = mclk_table->entries[entryId].vddc +
-+					mclk_table->entries[entryId].vdd_offset - 0xFFFF;
-+			else
-+				v_record.us_vdd = mclk_table->entries[entryId].vddc +
-+					mclk_table->entries[entryId].vdd_offset;
-+
-+			mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
-+				v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
-+			tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
-+		}
-+	}
-+
-+	return 0;
-+
-+}
-+
-+static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t entryId;
-+	phm_ppt_v1_voltage_lookup_record v_record;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
-+
-+	if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
-+		for (entryId = 0; entryId < mm_table->count; entryId++) {
-+			if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
-+				v_record.us_vdd = mm_table->entries[entryId].vddc +
-+					mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
-+			else
-+				v_record.us_vdd = mm_table->entries[entryId].vddc +
-+					mm_table->entries[entryId].vddgfx_offset;
-+
-+			/* Add the calculated VDDGFX to the VDDGFX lookup table */
-+			mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
-+				v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
-+			tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
-+		}
-+	}
-+	return 0;
-+}
-+
-+
-+/**
-+ * Change virtual leakage voltage to actual value.
-+ *
-+ * @param     hwmgr  the address of the powerplay hardware manager.
-+ * @param     pointer to changing voltage
-+ * @param     pointer to leakage table
-+ */
-+static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
-+		uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
-+{
-+	uint32_t leakage_index;
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 */
-+	for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
-+		/* if this voltage matches a leakage voltage ID */
-+		/* patch with actual leakage voltage */
-+		if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
-+			*voltage = pLeakageTable->actual_voltage[leakage_index];
-+			break;
-+		}
-+	}
-+
-+	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
-+		printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
-+}
-+
-+/**
-+ * Patch voltage lookup table by EVV leakages.
-+ *
-+ * @param     hwmgr  the address of the powerplay hardware manager.
-+ * @param     pointer to voltage lookup table
-+ * @param     pointer to leakage table
-+ * @return     always 0
-+ */
-+static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table,
-+		phw_tonga_leakage_voltage *pLeakageTable)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < lookup_table->count; i++) {
-+		tonga_patch_with_vdd_leakage(hwmgr,
-+			&lookup_table->entries[i].us_vdd, pLeakageTable);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
-+		phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
-+{
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
-+		pptable_info->max_clock_voltage_on_dc.vddc;
-+
-+	return 0;
-+}
-+
-+static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
-+		struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
-+		uint16_t *Vddgfx)
-+{
-+	tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
-+	return 0;
-+}
-+
-+int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table)
-+{
-+	uint32_t table_size, i, j;
-+	phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
-+	table_size = lookup_table->count;
-+
-+	PP_ASSERT_WITH_CODE(0 != lookup_table->count,
-+		"Lookup table is empty", return -1);
-+
-+	/* Sorting voltages */
-+	for (i = 0; i < table_size - 1; i++) {
-+		for (j = i + 1; j > 0; j--) {
-+			if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
-+				tmp_voltage_lookup_record = lookup_table->entries[j-1];
-+				lookup_table->entries[j-1] = lookup_table->entries[j];
-+				lookup_table->entries[j] = tmp_voltage_lookup_record;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	int tmp_result;
-+	tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
-+		tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
-+			pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
-+		if (tmp_result != 0)
-+			result = tmp_result;
-+
-+		tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
-+			&(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
-+		if (tmp_result != 0)
-+			result = tmp_result;
-+	} else {
-+		tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
-+			pptable_info->vddc_lookup_table, &(data->vddc_leakage));
-+		if (tmp_result != 0)
-+			result = tmp_result;
-+
-+		tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
-+			&(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
-+		if (tmp_result != 0)
-+			result = tmp_result;
-+	}
-+
-+	tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
-+	if (tmp_result != 0)
-+		result = tmp_result;
-+
-+	tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
-+	if (tmp_result != 0)
-+		result = tmp_result;
-+
-+	tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
-+	if (tmp_result != 0)
-+		result = tmp_result;
-+
-+	tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
-+	if (tmp_result != 0)
-+		result = tmp_result;
-+
-+	tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
-+	if (tmp_result != 0)
-+		result = tmp_result;
-+
-+	return result;
-+}
-+
-+int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	data->low_sclk_interrupt_threshold = 0;
-+
-+	return 0;
-+}
-+
-+int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = tonga_read_clock_registers(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to read clock registers!", result = tmp_result);
-+
-+	tmp_result = tonga_get_memory_type(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to get memory type!", result = tmp_result);
-+
-+	tmp_result = tonga_enable_acpi_power_management(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to enable ACPI power management!", result = tmp_result);
-+
-+	tmp_result = tonga_init_power_gate_state(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to init power gate state!", result = tmp_result);
-+
-+	tmp_result = tonga_get_mc_microcode_version(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to get MC microcode version!", result = tmp_result);
-+
-+	tmp_result = tonga_init_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to init sclk threshold!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+/**
-+ * Enable voltage control
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
-+{
-+	/* enable voltage control */
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Checks if we want to support voltage control
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ */
-+bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
-+{
-+	const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
-+}
-+
-+/*---------------------------MC----------------------------*/
-+
-+uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
-+{
-+	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
-+}
-+
-+bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
-+{
-+	bool result = 1;
-+
-+	switch (inReg) {
-+	case  mmMC_SEQ_RAS_TIMING:
-+		*outReg = mmMC_SEQ_RAS_TIMING_LP;
-+		break;
-+
-+	case  mmMC_SEQ_DLL_STBY:
-+		*outReg = mmMC_SEQ_DLL_STBY_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD0:
-+		*outReg = mmMC_SEQ_G5PDX_CMD0_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD1:
-+		*outReg = mmMC_SEQ_G5PDX_CMD1_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CTRL:
-+		*outReg = mmMC_SEQ_G5PDX_CTRL_LP;
-+		break;
-+
-+	case mmMC_SEQ_CAS_TIMING:
-+		*outReg = mmMC_SEQ_CAS_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING:
-+		*outReg = mmMC_SEQ_MISC_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING2:
-+		*outReg = mmMC_SEQ_MISC_TIMING2_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CMD:
-+		*outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CTL:
-+		*outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D0:
-+		*outReg = mmMC_SEQ_RD_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D1:
-+		*outReg = mmMC_SEQ_RD_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D0:
-+		*outReg = mmMC_SEQ_WR_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D1:
-+		*outReg = mmMC_SEQ_WR_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_EMRS:
-+		*outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS:
-+		*outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS1:
-+		*outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_TIMING:
-+		*outReg = mmMC_SEQ_PMG_TIMING_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS2:
-+		*outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_2:
-+		*outReg = mmMC_SEQ_WR_CTL_2_LP;
-+		break;
-+
-+	default:
-+		result = 0;
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
-+{
-+	uint32_t i;
-+	uint16_t address;
-+
-+	for (i = 0; i < table->last; i++) {
-+		table->mc_reg_address[i].s0 =
-+			tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
-+			? address : table->mc_reg_address[i].s1;
-+	}
-+	return 0;
-+}
-+
-+int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
-+{
-+	uint8_t i, j;
-+
-+	PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+		"Invalid VramInfo table.", return -1);
-+	PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
-+		"Invalid VramInfo table.", return -1);
-+
-+	for (i = 0; i < table->last; i++) {
-+		ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
-+	}
-+	ni_table->last = table->last;
-+
-+	for (i = 0; i < table->num_entries; i++) {
-+		ni_table->mc_reg_table_entry[i].mclk_max =
-+			table->mc_reg_table_entry[i].mclk_max;
-+		for (j = 0; j < table->last; j++) {
-+			ni_table->mc_reg_table_entry[i].mc_data[j] =
-+				table->mc_reg_table_entry[i].mc_data[j];
-+		}
-+	}
-+	ni_table->num_entries = table->num_entries;
-+
-+	return 0;
-+}
-+
-+/**
-+ * VBIOS omits some information to reduce size, we need to recover them here.
-+ * 1.   when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
-+ *      Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
-+ * 2.   when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
-+ * 3.   need to set these data for each clock range
-+ *
-+ * @param    hwmgr the address of the powerplay hardware manager.
-+ * @param    table the address of MCRegTable
-+ * @return   always 0
-+ */
-+int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
-+{
-+	uint8_t i, j, k;
-+	uint32_t temp_reg;
-+	const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	for (i = 0, j = table->last; i < table->last; i++) {
-+		PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+			"Invalid VramInfo table.", return -1);
-+		switch (table->mc_reg_address[i].s1) {
-+		/*
-+		* mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
-+		* Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
-+		*/
-+		case mmMC_SEQ_MISC1:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					((temp_reg & 0xffff0000)) |
-+					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -1);
-+
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+
-+				if (!data->is_memory_GDDR5) {
-+					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
-+				}
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -1);
-+
-+			if (!data->is_memory_GDDR5) {
-+				table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
-+				table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
-+				for (k = 0; k < table->num_entries; k++) {
-+					table->mc_reg_table_entry[k].mc_data[j] =
-+						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
-+				}
-+				j++;
-+				PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+					"Invalid VramInfo table.", return -1);
-+			}
-+
-+			break;
-+
-+		case mmMC_SEQ_RESERVE_M:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -1);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+	}
-+
-+	table->last = j;
-+
-+	return 0;
-+}
-+
-+int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
-+{
-+	uint8_t i, j;
-+	for (i = 0; i < table->last; i++) {
-+		for (j = 1; j < table->num_entries; j++) {
-+			if (table->mc_reg_table_entry[j-1].mc_data[i] !=
-+				table->mc_reg_table_entry[j].mc_data[i]) {
-+				table->validflag |= (1<<i);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_mc_reg_table *table;
-+	phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
-+	uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
-+
-+	table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -1;
-+
-+	/* Program additional LP registers that are no longer programmed by VBIOS */
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
-+
-+	memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-+
-+	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
-+
-+	if (0 == result)
-+		result = tonga_copy_vbios_smc_reg_table(table, ni_table);
-+
-+	if (0 == result) {
-+		tonga_set_s0_mc_reg_index(ni_table);
-+		result = tonga_set_mc_special_registers(hwmgr, ni_table);
-+	}
-+
-+	if (0 == result)
-+		tonga_set_valid_flag(ni_table);
-+
-+	kfree(table);
-+	return result;
-+}
-+
-+/*
-+* Copy one arb setting to another and then switch the active set.
-+* arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
-+*/
-+int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
-+		uint32_t arbFreqSrc, uint32_t arbFreqDest)
-+{
-+	uint32_t mc_arb_dram_timing;
-+	uint32_t mc_arb_dram_timing2;
-+	uint32_t burst_time;
-+	uint32_t mc_cg_config;
-+
-+	switch (arbFreqSrc) {
-+	case MC_CG_ARB_FREQ_F0:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+		break;
-+
-+	case MC_CG_ARB_FREQ_F1:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
-+		break;
-+
-+	default:
-+		return -1;
-+	}
-+
-+	switch (arbFreqDest) {
-+	case MC_CG_ARB_FREQ_F0:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
-+		break;
-+
-+	case MC_CG_ARB_FREQ_F1:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
-+		break;
-+
-+	default:
-+		return -1;
-+	}
-+
-+	mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
-+	mc_cg_config |= 0x0000000F;
-+	cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
-+	PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initial switch from ARB F0->F1
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ * This function is to be called from the SetPowerState table.
-+ */
-+int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
-+{
-+	return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
-+}
-+
-+/**
-+ * Initialize the ARB DRAM timing table's index field.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/*
-+	* This is a read-modify-write on the first byte of the ARB table.
-+	* The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
-+	* This solution is ugly, but we never write the whole table only individual fields in it.
-+	* In reality this field should not be in that structure but in a soft register.
-+	*/
-+	result = tonga_read_smc_sram_dword(hwmgr->smumgr,
-+				data->arb_table_start, &tmp, data->sram_end);
-+
-+	if (0 != result)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return tonga_write_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start,  tmp, data->sram_end);
-+}
-+
-+int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
-+{
-+	const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
-+		if (data->tonga_mc_reg_table.validflag & 1<<j) {
-+			PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
-+				"Index of mc_reg_table->address[] array out of boundary", return -1);
-+			mc_reg_table->address[i].s0 =
-+				PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
-+			mc_reg_table->address[i].s1 =
-+				PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
-+			i++;
-+		}
-+	}
-+
-+	mc_reg_table->last = (uint8_t)i;
-+
-+	return 0;
-+}
-+
-+/*convert register values from driver to SMC format */
-+void tonga_convert_mc_registers(
-+	const phw_tonga_mc_reg_entry * pEntry,
-+	SMU72_Discrete_MCRegisterSet *pData,
-+	uint32_t numEntries, uint32_t validflag)
-+{
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < numEntries; j++) {
-+		if (validflag & 1<<j) {
-+			pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
-+			i++;
-+		}
-+	}
-+}
-+
-+/* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
-+int tonga_convert_mc_reg_table_entry_to_smc(
-+		struct pp_hwmgr *hwmgr,
-+		const uint32_t memory_clock,
-+		SMU72_Discrete_MCRegisterSet *mc_reg_table_data
-+		)
-+{
-+	const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t i = 0;
-+
-+	for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
-+		if (memory_clock <=
-+			data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
-+			break;
-+		}
-+	}
-+
-+	if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
-+		--i;
-+
-+	tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
-+		mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
-+
-+	return 0;
-+}
-+
-+int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_MCRegisters *mc_reg_table)
-+{
-+	int result = 0;
-+	tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	int res;
-+	uint32_t i;
-+
-+	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
-+		res = tonga_convert_mc_reg_table_entry_to_smc(
-+				hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[i].value,
-+				&mc_reg_table->data[i]
-+				);
-+
-+		if (0 != res)
-+			result = res;
-+	}
-+
-+	return result;
-+}
-+
-+int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
-+	result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize MCRegTable for the MC register addresses!", return result;);
-+
-+	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize MCRegTable for driver state!", return result;);
-+
-+	return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
-+			(uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
-+}
-+
-+/**
-+ * Programs static screed detection parameters
-+ *
-+ * @param   hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* Set static screen threshold unit*/
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
-+		CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
-+		data->static_screen_threshold_unit);
-+	/* Set static screen threshold*/
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
-+		CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
-+		data->static_screen_threshold);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Setup display gap for glitch free memory clock switching.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
-+							CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
-+
-+	display_gap = PHM_SET_FIELD(display_gap,
-+					CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
-+
-+	display_gap = PHM_SET_FIELD(display_gap,
-+					CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Programs activity state transition voting clients
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+
-+	/* Clear reset for voting clients before enabling DPM */
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+		SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+		SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+		ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
-+
-+	return 0;
-+}
-+
-+
-+int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = tonga_check_for_dpm_stopped(hwmgr);
-+
-+	if (cf_tonga_voltage_control(hwmgr)) {
-+		tmp_result = tonga_enable_voltage_control(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable voltage control!", result = tmp_result);
-+
-+		tmp_result = tonga_construct_voltage_tables(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to contruct voltage tables!", result = tmp_result);
-+	}
-+
-+	tmp_result = tonga_initialize_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to initialize MC reg table!", result = tmp_result);
-+
-+	tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to program static screen threshold parameters!", result = tmp_result);
-+
-+	tmp_result = tonga_enable_display_gap(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to enable display gap!", result = tmp_result);
-+
-+	tmp_result = tonga_program_voting_clients(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to program voting clients!", result = tmp_result);
-+
-+	tmp_result = tonga_process_firmware_header(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to process firmware header!", result = tmp_result);
-+
-+	tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
-+
-+	tmp_result = tonga_init_smc_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to initialize SMC table!", result = tmp_result);
-+
-+	tmp_result = tonga_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to initialize ARB table index!", result = tmp_result);
-+
-+	tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to populate initialize MC Reg table!", result = tmp_result);
-+
-+	/* enable SCLK control */
-+	tmp_result = tonga_enable_sclk_control(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to enable SCLK control!", result = tmp_result);
-+
-+	/* enable DPM */
-+	tmp_result = tonga_start_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to start DPM!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = tonga_check_for_dpm_running(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"SMC is still running!", return 0);
-+
-+	tmp_result = tonga_stop_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to stop DPM!", result = tmp_result);
-+
-+	tmp_result = tonga_reset_to_default(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to reset to default!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	result = tonga_set_boot_state(hwmgr);
-+	if (0 != result)
-+		printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
-+
-+	return result;
-+}
-+
-+int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
-+{
-+	if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
-+		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-+		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-+	}
-+
-+	if (NULL != hwmgr->backend) {
-+		kfree(hwmgr->backend);
-+		hwmgr->backend = NULL;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initializes the Volcanic Islands Hardware Manager
-+ *
-+ * @param   hwmgr the address of the powerplay hardware manager.
-+ * @return   1 if success; otherwise appropriate error code.
-+ */
-+int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	SMU72_Discrete_DpmTable  *table = NULL;
-+	tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phw_tonga_ulv_parm *ulv;
-+
-+	PP_ASSERT_WITH_CODE((NULL != hwmgr),
-+		"Invalid Parameter!", return -1;);
-+
-+	data->dll_defaule_on = 0;
-+	data->sram_end = SMC_RAM_END;
-+
-+	data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
-+	data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
-+
-+	data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
-+	data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
-+	data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_DisableVoltageIsland);
-+
-+	data->sclk_dpm_key_disabled = 0;
-+	data->mclk_dpm_key_disabled = 0;
-+	data->pcie_dpm_key_disabled = 0;
-+	data->pcc_monitor_enabled = 0;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_UnTabledHardwareInterface);
-+
-+	data->gpio_debug = 0;
-+	data->engine_clock_data = 0;
-+	data->memory_clock_data = 0;
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_DynamicPatchPowerState);
-+
-+	/* need to set voltage control types before EVV patching*/
-+	data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
-+	data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
-+	data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
-+	data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
-+
-+	if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
-+		data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ControlVDDGFX)) {
-+		if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+			VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
-+			data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
-+		}
-+	}
-+
-+	if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ControlVDDGFX);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableMVDDControl)) {
-+		if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+					VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
-+			data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
-+		}
-+	}
-+
-+	if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableMVDDControl);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ControlVDDCI)) {
-+		if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+					VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
-+			data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
-+		else if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+						VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
-+			data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_ControlVDDCI);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_TablelessHardwareInterface);
-+
-+	if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher);
-+
-+	/* Initializes DPM default values*/
-+	tonga_initialize_dpm_defaults(hwmgr);
-+
-+	/* Get leakage voltage based on leakage ID.*/
-+	PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
-+		"Get EVV Voltage Failed.  Abort Driver loading!", return -1);
-+
-+	tonga_complete_dependency_tables(hwmgr);
-+
-+	/* Parse pptable data read from VBIOS*/
-+	tonga_set_private_var_based_on_pptale(hwmgr);
-+
-+	/* ULV Support*/
-+	ulv = &(data->ulv);
-+	ulv->ulv_supported = 0;
-+
-+	/* Initalize Dynamic State Adjustment Rule Settings*/
-+	result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
-+	data->uvd_enabled = 0;
-+
-+	table = &(data->smc_state_table);
-+
-+	/*
-+	* if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
-+	* Peak Current Control feature is enabled and we should program PCC HW register
-+	*/
-+	if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
-+		uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
-+										CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
-+
-+		switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
-+		case 0:
-+			temp_reg = PHM_SET_FIELD(temp_reg,
-+				CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
-+			break;
-+		case 1:
-+			temp_reg = PHM_SET_FIELD(temp_reg,
-+				CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
-+			break;
-+		case 2:
-+			temp_reg = PHM_SET_FIELD(temp_reg,
-+				CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
-+			break;
-+		case 3:
-+			temp_reg = PHM_SET_FIELD(temp_reg,
-+				CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
-+			break;
-+		case 4:
-+			temp_reg = PHM_SET_FIELD(temp_reg,
-+				CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
-+			break;
-+		default:
-+			printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register!	\
-+				Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
-+			break;
-+		}
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCNB_PWRMGT_CNTL, temp_reg);
-+	}
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_EnableSMU7ThermalManagement);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_SMU7);
-+
-+	data->vddc_phase_shed_control = 0;
-+
-+	if (0 == result) {
-+		data->is_tlu_enabled = 0;
-+		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
-+			TONGA_MAX_HARDWARE_POWERLEVELS;
-+		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
-+		hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
-+
-+		data->pcie_gen_cap = 0x30007;
-+		data->pcie_lane_cap = 0x2f0000;
-+	} else {
-+		/* Ignore return value in here, we are cleaning up a mess. */
-+		tonga_hwmgr_backend_fini(hwmgr);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
-+		enum amd_dpm_forced_level level)
-+{
-+	int ret = 0;
-+
-+	switch (level) {
-+	case AMD_DPM_FORCED_LEVEL_HIGH:
-+		ret = tonga_force_dpm_highest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_LOW:
-+		ret = tonga_force_dpm_lowest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_AUTO:
-+		ret = tonga_unforce_dpm_levels(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	hwmgr->dpm_level = level;
-+	return ret;
-+}
-+
-+static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				struct pp_power_state  *prequest_ps,
-+			const struct pp_power_state *pcurrent_ps)
-+{
-+	struct tonga_power_state *tonga_ps =
-+				cast_phw_tonga_power_state(&prequest_ps->hardware);
-+
-+	uint32_t sclk;
-+	uint32_t mclk;
-+	struct PP_Clocks minimum_clocks = {0};
-+	bool disable_mclk_switching;
-+	bool disable_mclk_switching_for_frame_lock;
-+	struct cgs_display_info info = {0};
-+	const struct phm_clock_and_voltage_limits *max_limits;
-+	uint32_t i;
-+	tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	int32_t count;
-+	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
-+
-+	data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
-+
-+	PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
-+				 "VI should always have 2 performance levels",
-+				 );
-+
-+	max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
-+			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
-+			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
-+
-+	if (PP_PowerSource_DC == hwmgr->power_source) {
-+		for (i = 0; i < tonga_ps->performance_level_count; i++) {
-+			if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
-+				tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
-+			if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
-+				tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
-+		}
-+	}
-+
-+	tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
-+	tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
-+
-+	tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-+
-+	/* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
-+
-+		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
-+		stable_pstate_sclk = (max_limits->sclk * 75) / 100;
-+
-+		for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
-+			if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
-+				stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
-+				break;
-+			}
-+		}
-+
-+		if (count < 0)
-+			stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
-+
-+		stable_pstate_mclk = max_limits->mclk;
-+
-+		minimum_clocks.engineClock = stable_pstate_sclk;
-+		minimum_clocks.memoryClock = stable_pstate_mclk;
-+	}
-+
-+	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
-+		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
-+
-+	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
-+		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-+
-+	tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-+
-+	if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
-+					"Overdrive sclk exceeds limit",
-+					hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
-+
-+		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
-+			tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
-+	}
-+
-+	if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
-+			"Overdrive mclk exceeds limit",
-+			hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
-+
-+		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
-+			tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
-+	}
-+
-+	disable_mclk_switching_for_frame_lock = phm_cap_enabled(
-+				    hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
-+
-+	disable_mclk_switching = (1 < info.display_count) ||
-+				    disable_mclk_switching_for_frame_lock;
-+
-+	sclk  = tonga_ps->performance_levels[0].engine_clock;
-+	mclk  = tonga_ps->performance_levels[0].memory_clock;
-+
-+	if (disable_mclk_switching)
-+		mclk  = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
-+
-+	if (sclk < minimum_clocks.engineClock)
-+		sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
-+
-+	if (mclk < minimum_clocks.memoryClock)
-+		mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
-+
-+	tonga_ps->performance_levels[0].engine_clock = sclk;
-+	tonga_ps->performance_levels[0].memory_clock = mclk;
-+
-+	tonga_ps->performance_levels[1].engine_clock =
-+		(tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
-+			      tonga_ps->performance_levels[1].engine_clock :
-+			      tonga_ps->performance_levels[0].engine_clock;
-+
-+	if (disable_mclk_switching) {
-+		if (mclk < tonga_ps->performance_levels[1].memory_clock)
-+			mclk = tonga_ps->performance_levels[1].memory_clock;
-+
-+		tonga_ps->performance_levels[0].memory_clock = mclk;
-+		tonga_ps->performance_levels[1].memory_clock = mclk;
-+	} else {
-+		if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
-+			tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
-+		for (i=0; i < tonga_ps->performance_level_count; i++) {
-+			tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
-+			tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
-+			tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
-+			tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
-+{
-+	return sizeof(struct tonga_power_state);
-+}
-+
-+static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct tonga_power_state  *tonga_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
-+
-+	if (low)
-+		return tonga_ps->performance_levels[0].memory_clock;
-+	else
-+		return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
-+}
-+
-+static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct tonga_power_state  *tonga_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
-+
-+	if (low)
-+		return tonga_ps->performance_levels[0].engine_clock;
-+	else
-+		return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
-+}
-+
-+static uint16_t tonga_get_current_pcie_speed(
-+						   struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t speed_cntl = 0;
-+
-+	speed_cntl = cgs_read_ind_register(hwmgr->device,
-+						   CGS_IND_REG__PCIE,
-+						   ixPCIE_LC_SPEED_CNTL);
-+	return((uint16_t)PHM_GET_FIELD(speed_cntl,
-+			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
-+}
-+
-+static int tonga_get_current_pcie_lane_number(
-+						   struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t link_width;
-+
-+	link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+							CGS_IND_REG__PCIE,
-+						  PCIE_LC_LINK_WIDTH_CNTL,
-+							LC_LINK_WIDTH_RD);
-+
-+	PP_ASSERT_WITH_CODE((7 >= link_width),
-+			"Invalid PCIe lane width!", return 0);
-+
-+	return decode_pcie_lane_width(link_width);
-+}
-+
-+static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
-+					struct pp_hw_power_state *hw_ps)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
-+	ATOM_FIRMWARE_INFO_V2_2 *fw_info;
-+	uint16_t size;
-+	uint8_t frev, crev;
-+	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-+
-+	/* First retrieve the Boot clocks and VDDC from the firmware info table.
-+	 * We assume here that fw_info is unchanged if this call fails.
-+	 */
-+	fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
-+			hwmgr->device, index,
-+			&size, &frev, &crev);
-+	if (!fw_info)
-+		/* During a test, there is no firmware info table. */
-+		return 0;
-+
-+	/* Patch the state. */
-+	data->vbios_boot_state.sclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultEngineClock);
-+	data->vbios_boot_state.mclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultMemoryClock);
-+	data->vbios_boot_state.mvdd_bootup_value  = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
-+	data->vbios_boot_state.vddc_bootup_value  = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
-+	data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
-+	data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
-+	data->vbios_boot_state.pcie_lane_bootup_value =
-+			(uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
-+
-+	/* set boot power state */
-+	ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
-+	ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
-+	ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
-+	ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
-+
-+	return 0;
-+}
-+
-+static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
-+		void *state, struct pp_power_state *power_state,
-+		void *pp_table, uint32_t classification_flag)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	struct tonga_power_state  *tonga_ps =
-+			(struct tonga_power_state *)(&(power_state->hardware));
-+
-+	struct tonga_performance_level *performance_level;
-+
-+	ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
-+
-+	ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
-+			(ATOM_Tonga_POWERPLAYTABLE *)pp_table;
-+
-+	ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-+			(ATOM_Tonga_SCLK_Dependency_Table *)
-+			(((uint64_t)powerplay_table) +
-+			le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
-+
-+	ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
-+			(ATOM_Tonga_MCLK_Dependency_Table *)
-+			(((uint64_t)powerplay_table) +
-+			le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
-+
-+	/* The following fields are not initialized here: id orderedList allStatesList */
-+	power_state->classification.ui_label =
-+			(le16_to_cpu(state_entry->usClassification) &
-+			ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
-+			ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
-+	power_state->classification.flags = classification_flag;
-+	/* NOTE: There is a classification2 flag in BIOS that is not being used right now */
-+
-+	power_state->classification.temporary_state = false;
-+	power_state->classification.to_be_deleted = false;
-+
-+	power_state->validation.disallowOnDC =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
-+
-+	power_state->pcie.lanes = 0;
-+
-+	power_state->display.disableFrameModulation = false;
-+	power_state->display.limitRefreshrate = false;
-+	power_state->display.enableVariBright =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
-+
-+	power_state->validation.supportedPowerLevels = 0;
-+	power_state->uvd_clocks.VCLK = 0;
-+	power_state->uvd_clocks.DCLK = 0;
-+	power_state->temperatures.min = 0;
-+	power_state->temperatures.max = 0;
-+
-+	performance_level = &(tonga_ps->performance_levels
-+			[tonga_ps->performance_level_count++]);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
-+			"Performance levels exceeds SMC limit!",
-+			return -1);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(tonga_ps->performance_level_count <=
-+					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
-+			"Performance levels exceeds Driver limit!",
-+			return -1);
-+
-+	/* Performance levels are arranged from low to high. */
-+	performance_level->memory_clock =
-+				le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
-+
-+	performance_level->engine_clock =
-+				le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
-+
-+	performance_level->pcie_gen = get_pcie_gen_support(
-+							data->pcie_gen_cap,
-+					     state_entry->ucPCIEGenLow);
-+
-+	performance_level->pcie_lane = get_pcie_lane_support(
-+						    data->pcie_lane_cap,
-+					   state_entry->ucPCIELaneHigh);
-+
-+	performance_level =
-+			&(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
-+
-+	performance_level->memory_clock =
-+				le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
-+
-+	performance_level->engine_clock =
-+				le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
-+
-+	performance_level->pcie_gen = get_pcie_gen_support(
-+							data->pcie_gen_cap,
-+					    state_entry->ucPCIEGenHigh);
-+
-+	performance_level->pcie_lane = get_pcie_lane_support(
-+						    data->pcie_lane_cap,
-+					   state_entry->ucPCIELaneHigh);
-+
-+	return 0;
-+}
-+
-+static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
-+		    unsigned long entry_index, struct pp_power_state *ps)
-+{
-+	int result;
-+	struct tonga_power_state *tonga_ps;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+					   table_info->vdd_dep_on_mclk;
-+
-+	ps->hardware.magic = PhwTonga_Magic;
-+
-+	tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
-+
-+	result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
-+			tonga_get_pp_table_entry_callback_func);
-+
-+	/* This is the earliest time we have all the dependency table and the VBIOS boot state
-+	 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
-+	 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
-+	 */
-+	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
-+		if (dep_mclk_table->entries[0].clk !=
-+				data->vbios_boot_state.mclk_bootup_value)
-+			printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot MCLK level");
-+		if (dep_mclk_table->entries[0].vddci !=
-+				data->vbios_boot_state.vddci_bootup_value)
-+			printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot VDDCI level");
-+	}
-+
-+	/* set DC compatible flag if this state supports DC */
-+	if (!ps->validation.disallowOnDC)
-+		tonga_ps->dc_compatible = true;
-+
-+	if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
-+		data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
-+	else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
-+		if (data->bacos.best_match == 0xffff) {
-+			/* For V.I. use boot state as base BACO state */
-+			data->bacos.best_match = PP_StateClassificationFlag_Boot;
-+			data->bacos.performance_level = tonga_ps->performance_levels[0];
-+		}
-+	}
-+
-+	tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
-+	tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
-+
-+	if (!result) {
-+		uint32_t i;
-+
-+		switch (ps->classification.ui_label) {
-+		case PP_StateUILabel_Performance:
-+			data->use_pcie_performance_levels = true;
-+
-+			for (i = 0; i < tonga_ps->performance_level_count; i++) {
-+				if (data->pcie_gen_performance.max <
-+						tonga_ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.max =
-+							tonga_ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_performance.min >
-+						tonga_ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.min =
-+							tonga_ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_performance.max <
-+						tonga_ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.max =
-+							tonga_ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_performance.min >
-+						tonga_ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.min =
-+							tonga_ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		case PP_StateUILabel_Battery:
-+			data->use_pcie_power_saving_levels = true;
-+
-+			for (i = 0; i < tonga_ps->performance_level_count; i++) {
-+				if (data->pcie_gen_power_saving.max <
-+						tonga_ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.max =
-+							tonga_ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_power_saving.min >
-+						tonga_ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.min =
-+							tonga_ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_power_saving.max <
-+						tonga_ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.max =
-+							tonga_ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_power_saving.min >
-+						tonga_ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.min =
-+							tonga_ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static void
-+tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
-+{
-+	uint32_t sclk, mclk;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
-+
-+	sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
-+
-+	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n", mclk/100, sclk/100);
-+}
-+
-+static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
-+	const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
-+	uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
-+	struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
-+	uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
-+	struct PP_Clocks min_clocks = {0};
-+	uint32_t i;
-+	struct cgs_display_info info = {0};
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	for (i = 0; i < psclk_table->count; i++) {
-+		if (sclk == psclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= psclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-+	else {
-+	/* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
-+		if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
-+			data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
-+	}
-+
-+	for (i=0; i < pmclk_table->count; i++) {
-+		if (mclk == pmclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= pmclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
-+
-+	return 0;
-+}
-+
-+static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
-+{
-+	uint32_t i;
-+	uint32_t sclk, max_sclk = 0;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_dpm_table *pdpm_table = &data->dpm_table;
-+
-+	for (i = 0; i < hw_ps->performance_level_count; i++) {
-+		sclk = hw_ps->performance_levels[i].engine_clock;
-+		if (max_sclk < sclk)
-+			max_sclk = sclk;
-+	}
-+
-+	for (i = 0; i < pdpm_table->sclk_table.count; i++) {
-+		if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
-+			return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
-+					pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
-+					pdpm_table->pcie_speed_table.dpm_levels[i].value);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
-+	const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
-+
-+	uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
-+	uint16_t current_link_speed;
-+
-+	if (data->force_pcie_gen == PP_PCIEGenInvalid)
-+		current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
-+	else
-+		current_link_speed = data->force_pcie_gen;
-+
-+	data->force_pcie_gen = PP_PCIEGenInvalid;
-+	data->pspp_notify_required = false;
-+	if (target_link_speed > current_link_speed) {
-+		switch(target_link_speed) {
-+		case PP_PCIEGen3:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
-+				break;
-+			data->force_pcie_gen = PP_PCIEGen2;
-+			if (current_link_speed == PP_PCIEGen2)
-+				break;
-+		case PP_PCIEGen2:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
-+				break;
-+		default:
-+			data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
-+			break;
-+		}
-+	} else {
-+		if (target_link_speed < current_link_speed)
-+			data->pspp_notify_required = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+		PP_ASSERT_WITH_CODE(
-+			true == tonga_is_dpm_running(hwmgr),
-+			"Trying to freeze SCLK DPM when DPM is disabled",
-+			);
-+		PP_ASSERT_WITH_CODE(
-+			0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					  PPSMC_MSG_SCLKDPM_FreezeLevel),
-+			"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
-+			return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		 DPMTABLE_OD_UPDATE_MCLK)) {
-+		PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
-+			"Trying to freeze MCLK DPM when DPM is disabled",
-+			);
-+		PP_ASSERT_WITH_CODE(
-+			0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+							PPSMC_MSG_MCLKDPM_FreezeLevel),
-+			"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
-+			return -1);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result = 0;
-+
-+	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
-+	const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
-+	uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
-+	struct tonga_dpm_table *pdpm_table = &data->dpm_table;
-+
-+	struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
-+	uint32_t dpm_count, clock_percent;
-+	uint32_t i;
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
-+		pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-+		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+		/* Need to do calculation based on the golden DPM table
-+		 * as the Heatmap GPU Clock axis is also based on the default values
-+		 */
-+			PP_ASSERT_WITH_CODE(
-+				(pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
-+				"Divide by 0!",
-+				return -1);
-+			dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
-+			for (i = dpm_count; i > 1; i--) {
-+				if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
-+					clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
-+							pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
-+
-+					pdpm_table->sclk_table.dpm_levels[i].value =
-+							pgolden_dpm_table->sclk_table.dpm_levels[i].value +
-+							(pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
-+
-+				} else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
-+					clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
-+								pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
-+
-+					pdpm_table->sclk_table.dpm_levels[i].value =
-+							pgolden_dpm_table->sclk_table.dpm_levels[i].value -
-+							(pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
-+				} else
-+					pdpm_table->sclk_table.dpm_levels[i].value =
-+							pgolden_dpm_table->sclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
-+		pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+
-+			PP_ASSERT_WITH_CODE(
-+					(pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
-+					"Divide by 0!",
-+					return -1);
-+			dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
-+			for (i = dpm_count; i > 1; i--) {
-+				if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
-+						clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
-+								    pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
-+
-+						pdpm_table->mclk_table.dpm_levels[i].value =
-+										pgolden_dpm_table->mclk_table.dpm_levels[i].value +
-+										(pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
-+
-+				} else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
-+						clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
-+								    pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
-+
-+						pdpm_table->mclk_table.dpm_levels[i].value =
-+									pgolden_dpm_table->mclk_table.dpm_levels[i].value -
-+									(pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
-+				} else
-+					pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
-+		result = tonga_populate_all_memory_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
-+			return result);
-+	}
-+
-+	if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
-+		/*populate MCLK dpm table to SMU7 */
-+		result = tonga_populate_all_memory_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	return result;
-+}
-+
-+static	int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
-+			  struct tonga_single_dpm_table * pdpm_table,
-+			     uint32_t low_limit, uint32_t high_limit)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < pdpm_table->count; i++) {
-+		if ((pdpm_table->dpm_levels[i].value < low_limit) ||
-+		    (pdpm_table->dpm_levels[i].value > high_limit))
-+			pdpm_table->dpm_levels[i].enabled = false;
-+		else
-+			pdpm_table->dpm_levels[i].enabled = true;
-+	}
-+	return 0;
-+}
-+
-+static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
-+{
-+	int result = 0;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t high_limit_count;
-+
-+	PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
-+				"power state did not have any performance level",
-+				 return -1);
-+
-+	high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
-+
-+	tonga_trim_single_dpm_states(hwmgr,
-+					&(data->dpm_table.sclk_table),
-+					hw_state->performance_levels[0].engine_clock,
-+					hw_state->performance_levels[high_limit_count].engine_clock);
-+
-+	tonga_trim_single_dpm_states(hwmgr,
-+						&(data->dpm_table.mclk_table),
-+						hw_state->performance_levels[0].memory_clock,
-+						hw_state->performance_levels[high_limit_count].memory_clock);
-+
-+	return result;
-+}
-+
-+static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result;
-+	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
-+
-+
-+	result = tonga_trim_dpm_states(hwmgr, tonga_ps);
-+	if (0 != result)
-+		return result;
-+
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
-+	data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
-+	if (data->uvd_enabled)
-+		data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
-+
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+				  (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
-+				  (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
-+}
-+
-+static int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
-+	const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
-+
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if(tonga_nps->vce_clocks.EVCLK >0 &&
-+	(tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
-+		data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
-+
-+		mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFF00FFFF;
-+		mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
-+				smum_send_msg_to_smc_with_parameter(
-+							   hwmgr->smumgr,
-+			(PPSMC_Msg)(PPSMC_MSG_VCEDPM_SetEnabledMask),
-+			(uint32_t)1 << data->smc_state_table.VceBootLevel);
-+
-+			tonga_enable_disable_vce_dpm(hwmgr, true);
-+		} else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
-+			tonga_enable_disable_vce_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t address;
-+	int32_t result;
-+
-+	if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
-+		return 0;
-+
-+
-+	memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
-+
-+	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
-+
-+	if(result != 0)
-+		return result;
-+
-+
-+	address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
-+
-+	return  tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
-+				 (uint8_t *)&data->mc_reg_table.data[0],
-+				sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
-+				data->sram_end);
-+}
-+
-+static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return tonga_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+
-+		PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
-+			"Trying to Unfreeze SCLK DPM when DPM is disabled",
-+			);
-+		PP_ASSERT_WITH_CODE(
-+			 0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+			"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
-+			return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
-+
-+		PP_ASSERT_WITH_CODE(
-+				true == tonga_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze MCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(
-+			 0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+		    "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
-+		    return -1);
-+	}
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	return 0;
-+}
-+
-+static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
-+	uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
-+	uint8_t  request;
-+
-+	if (data->pspp_notify_required  ||
-+	    data->pcie_performance_request) {
-+		if (target_link_speed == PP_PCIEGen3)
-+			request = PCIE_PERF_REQ_GEN3;
-+		else if (target_link_speed == PP_PCIEGen2)
-+			request = PCIE_PERF_REQ_GEN2;
-+		else
-+			request = PCIE_PERF_REQ_GEN1;
-+
-+		if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
-+			data->pcie_performance_request = false;
-+			return 0;
-+		}
-+
-+		if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
-+			if (PP_PCIEGen2 == target_link_speed)
-+				printk("PSPP request to switch to Gen2 from Gen3 Failed!");
-+			else
-+				printk("PSPP request to switch to Gen1 from Gen2 Failed!");
-+		}
-+	}
-+
-+	data->pcie_performance_request = false;
-+	return 0;
-+}
-+
-+static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
-+	}
-+
-+	tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
-+
-+	tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
-+
-+	tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
-+
-+	tmp_result = tonga_update_vce_dpm(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
-+
-+	tmp_result = tonga_update_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
-+
-+	tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
-+
-+	tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
-+
-+	tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
-+
-+	tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
-+	}
-+
-+	return result;
-+}
-+
-+static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
-+	.backend_init = &tonga_hwmgr_backend_init,
-+	.backend_fini = &tonga_hwmgr_backend_fini,
-+	.asic_setup = &tonga_setup_asic_task,
-+	.dynamic_state_management_enable = &tonga_enable_dpm_tasks,
-+	.apply_state_adjust_rules = tonga_apply_state_adjust_rules,
-+	.force_dpm_level = &tonga_force_dpm_level,
-+	.power_state_set = tonga_set_power_state_tasks,
-+	.get_power_state_size = tonga_get_power_state_size,
-+	.get_mclk = tonga_dpm_get_mclk,
-+	.get_sclk = tonga_dpm_get_sclk,
-+	.patch_boot_state = tonga_dpm_patch_boot_state,
-+	.get_pp_table_entry = tonga_get_pp_table_entry,
-+	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
-+	.print_current_perforce_level = tonga_print_current_perforce_level,
-+};
-+
-+int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
-+{
-+	tonga_hwmgr  *data;
-+
-+	data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
-+	if (data == NULL)
-+		return -ENOMEM;
-+	memset(data, 0x00, sizeof(tonga_hwmgr));
-+
-+	hwmgr->backend = data;
-+	hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
-+	hwmgr->pptable_func = &tonga_pptable_funcs;
-+
-+	return 0;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-new file mode 100644
-index 0000000..d007706
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -0,0 +1,427 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef TONGA_HWMGR_H
-+#define TONGA_HWMGR_H
-+
-+#include "hwmgr.h"
-+#include "smu72_discrete.h"
-+#include "ppatomctrl.h"
-+#include "ppinterrupt.h"
-+#include "tonga_powertune.h"
-+
-+#define TONGA_MAX_HARDWARE_POWERLEVELS 2
-+#define TONGA_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
-+
-+struct tonga_performance_level {
-+	uint32_t	memory_clock;
-+	uint32_t	engine_clock;
-+	uint16_t    pcie_gen;
-+	uint16_t    pcie_lane;
-+};
-+
-+struct _phw_tonga_bacos {
-+	uint32_t                          best_match;
-+	uint32_t                          baco_flags;
-+	struct tonga_performance_level		  performance_level;
-+};
-+typedef struct _phw_tonga_bacos phw_tonga_bacos;
-+
-+struct _phw_tonga_uvd_clocks {
-+	uint32_t   VCLK;
-+	uint32_t   DCLK;
-+};
-+
-+typedef struct _phw_tonga_uvd_clocks phw_tonga_uvd_clocks;
-+
-+struct _phw_tonga_vce_clocks {
-+	uint32_t   EVCLK;
-+	uint32_t   ECCLK;
-+};
-+
-+typedef struct _phw_tonga_vce_clocks phw_tonga_vce_clocks;
-+
-+struct tonga_power_state {
-+	uint32_t                    magic;
-+	phw_tonga_uvd_clocks        uvd_clocks;
-+	phw_tonga_vce_clocks        vce_clocks;
-+	uint32_t                    sam_clk;
-+	uint32_t                    acp_clk;
-+	uint16_t                    performance_level_count;
-+	bool                        dc_compatible;
-+	uint32_t                    sclk_threshold;
-+	struct tonga_performance_level performance_levels[TONGA_MAX_HARDWARE_POWERLEVELS];
-+};
-+
-+struct _phw_tonga_dpm_level {
-+	bool  		enabled;
-+	uint32_t    value;
-+	uint32_t    param1;
-+};
-+typedef struct _phw_tonga_dpm_level phw_tonga_dpm_level;
-+
-+#define TONGA_MAX_DEEPSLEEP_DIVIDER_ID 5
-+#define MAX_REGULAR_DPM_NUMBER 8
-+#define TONGA_MINIMUM_ENGINE_CLOCK 2500
-+
-+struct tonga_single_dpm_table {
-+	uint32_t count;
-+	phw_tonga_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
-+};
-+
-+struct tonga_dpm_table {
-+	struct tonga_single_dpm_table  sclk_table;
-+	struct tonga_single_dpm_table  mclk_table;
-+	struct tonga_single_dpm_table  pcie_speed_table;
-+	struct tonga_single_dpm_table  vddc_table;
-+	struct tonga_single_dpm_table  vdd_gfx_table;
-+	struct tonga_single_dpm_table  vdd_ci_table;
-+	struct tonga_single_dpm_table  mvdd_table;
-+};
-+typedef struct _phw_tonga_dpm_table phw_tonga_dpm_table;
-+
-+
-+struct _phw_tonga_clock_regisiters {
-+	uint32_t  vCG_SPLL_FUNC_CNTL;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t  vDLL_CNTL;
-+	uint32_t  vMCLK_PWRMGT_CNTL;
-+	uint32_t  vMPLL_AD_FUNC_CNTL;
-+	uint32_t  vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL_1;
-+	uint32_t  vMPLL_FUNC_CNTL_2;
-+	uint32_t  vMPLL_SS1;
-+	uint32_t  vMPLL_SS2;
-+};
-+typedef struct _phw_tonga_clock_regisiters phw_tonga_clock_registers;
-+
-+struct _phw_tonga_voltage_smio_registers {
-+	uint32_t vs0_vid_lower_smio_cntl;
-+};
-+typedef struct _phw_tonga_voltage_smio_registers phw_tonga_voltage_smio_registers;
-+
-+
-+struct _phw_tonga_mc_reg_entry {
-+	uint32_t mclk_max;
-+	uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+};
-+typedef struct _phw_tonga_mc_reg_entry phw_tonga_mc_reg_entry;
-+
-+struct _phw_tonga_mc_reg_table {
-+	uint8_t   last;               /* number of registers*/
-+	uint8_t   num_entries;        /* number of entries in mc_reg_table_entry used*/
-+	uint16_t  validflag;          /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
-+	phw_tonga_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
-+	SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+};
-+typedef struct _phw_tonga_mc_reg_table phw_tonga_mc_reg_table;
-+
-+#define DISABLE_MC_LOADMICROCODE   1
-+#define DISABLE_MC_CFGPROGRAMMING  2
-+
-+/*Ultra Low Voltage parameter structure */
-+struct _phw_tonga_ulv_parm{
-+	bool	ulv_supported;
-+	uint32_t   ch_ulv_parameter;
-+	uint32_t   ulv_volt_change_delay;
-+	struct tonga_performance_level   ulv_power_level;
-+};
-+typedef struct _phw_tonga_ulv_parm phw_tonga_ulv_parm;
-+
-+#define TONGA_MAX_LEAKAGE_COUNT  8
-+
-+struct _phw_tonga_leakage_voltage {
-+	uint16_t  count;
-+	uint16_t  leakage_id[TONGA_MAX_LEAKAGE_COUNT];
-+	uint16_t  actual_voltage[TONGA_MAX_LEAKAGE_COUNT];
-+};
-+typedef struct _phw_tonga_leakage_voltage phw_tonga_leakage_voltage;
-+
-+struct _phw_tonga_display_timing {
-+	uint32_t min_clock_insr;
-+	uint32_t num_existing_displays;
-+};
-+typedef struct _phw_tonga_display_timing phw_tonga_display_timing;
-+
-+struct _phw_tonga_dpmlevel_enable_mask {
-+	uint32_t uvd_dpm_enable_mask;
-+	uint32_t vce_dpm_enable_mask;
-+	uint32_t acp_dpm_enable_mask;
-+	uint32_t samu_dpm_enable_mask;
-+	uint32_t sclk_dpm_enable_mask;
-+	uint32_t mclk_dpm_enable_mask;
-+	uint32_t pcie_dpm_enable_mask;
-+};
-+typedef struct _phw_tonga_dpmlevel_enable_mask phw_tonga_dpmlevel_enable_mask;
-+
-+struct _phw_tonga_pcie_perf_range {
-+	uint16_t max;
-+	uint16_t min;
-+};
-+typedef struct _phw_tonga_pcie_perf_range phw_tonga_pcie_perf_range;
-+
-+struct _phw_tonga_vbios_boot_state {
-+	uint16_t					mvdd_bootup_value;
-+	uint16_t					vddc_bootup_value;
-+	uint16_t					vddci_bootup_value;
-+	uint16_t					vddgfx_bootup_value;
-+	uint32_t					sclk_bootup_value;
-+	uint32_t					mclk_bootup_value;
-+	uint16_t					pcie_gen_bootup_value;
-+	uint16_t					pcie_lane_bootup_value;
-+};
-+typedef struct _phw_tonga_vbios_boot_state phw_tonga_vbios_boot_state;
-+
-+#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-+#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
-+#define DPMTABLE_UPDATE_SCLK        0x00000004
-+#define DPMTABLE_UPDATE_MCLK        0x00000008
-+
-+/* We need to review which fields are needed. */
-+/* This is mostly a copy of the RV7xx/Evergreen structure which is close, but not identical to the N.Islands one. */
-+struct tonga_hwmgr {
-+	struct tonga_dpm_table               dpm_table;
-+	struct tonga_dpm_table               golden_dpm_table;
-+
-+	uint32_t                           voting_rights_clients0;
-+	uint32_t                           voting_rights_clients1;
-+	uint32_t                           voting_rights_clients2;
-+	uint32_t                           voting_rights_clients3;
-+	uint32_t                           voting_rights_clients4;
-+	uint32_t                           voting_rights_clients5;
-+	uint32_t                           voting_rights_clients6;
-+	uint32_t                           voting_rights_clients7;
-+	uint32_t                           static_screen_threshold_unit;
-+	uint32_t                           static_screen_threshold;
-+	uint32_t                           voltage_control;
-+	uint32_t                           vdd_gfx_control;
-+
-+	uint32_t                           vddc_vddci_delta;
-+	uint32_t                           vddc_vddgfx_delta;
-+
-+	pp_interrupt_registration_info    internal_high_thermal_interrupt_info;
-+	pp_interrupt_registration_info    internal_low_thermal_interrupt_info;
-+	pp_interrupt_registration_info    smc_to_host_interrupt_info;
-+	uint32_t                          active_auto_throttle_sources;
-+
-+	pp_interrupt_registration_info    external_throttle_interrupt;
-+	pp_interrupt_callback             external_throttle_callback;
-+	void                             *external_throttle_context;
-+
-+	pp_interrupt_registration_info    ctf_interrupt_info;
-+	pp_interrupt_callback             ctf_callback;
-+	void                             *ctf_context;
-+
-+	phw_tonga_clock_registers      	  clock_registers;
-+	phw_tonga_voltage_smio_registers  voltage_smio_registers;
-+
-+	bool                         	is_memory_GDDR5;
-+	uint16_t                          acpi_vddc;
-+	bool                         	pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
-+	uint16_t                          force_pcie_gen;            /* The forced PCI-E speed if not 0xffff */
-+	uint16_t                          acpi_pcie_gen;             /* The PCI-E speed at ACPI time */
-+	uint32_t                           pcie_gen_cap;             /* The PCI-E speed capabilities bitmap from CAIL */
-+	uint32_t                           pcie_lane_cap;            /* The PCI-E lane capabilities bitmap from CAIL */
-+	uint32_t                           pcie_spc_cap;             /* Symbol Per Clock Capabilities from registry */
-+	phw_tonga_leakage_voltage       	vddc_leakage;            /* The Leakage VDDC supported (based on leakage ID).*/
-+	phw_tonga_leakage_voltage       	vddcgfx_leakage;         /* The Leakage VDDC supported (based on leakage ID). */
-+	phw_tonga_leakage_voltage       	vddci_leakage;           /* The Leakage VDDCI supported (based on leakage ID). */
-+
-+	uint32_t                           mvdd_control;
-+	uint32_t                           vddc_mask_low;
-+	uint32_t                           mvdd_mask_low;
-+	uint16_t                          max_vddc_in_pp_table;        /* the maximum VDDC value in the powerplay table*/
-+	uint16_t                          min_vddc_in_pp_table;
-+	uint16_t                          max_vddci_in_pp_table;       /* the maximum VDDCI value in the powerplay table */
-+	uint16_t                          min_vddci_in_pp_table;
-+	uint32_t                           mclk_strobe_mode_threshold;
-+	uint32_t                           mclk_stutter_mode_threshold;
-+	uint32_t                           mclk_edc_enable_threshold;
-+	uint32_t                           mclk_edc_wr_enable_threshold;
-+	bool                         	is_uvd_enabled;
-+	bool                         	is_xdma_enabled;
-+	phw_tonga_vbios_boot_state      vbios_boot_state;
-+
-+	bool                         battery_state;
-+	bool                         is_tlu_enabled;
-+	bool                         pcie_performance_request;
-+
-+	/* -------------- SMC SRAM Address of firmware header tables ----------------*/
-+	uint32_t                           sram_end;                 /* The first address after the SMC SRAM. */
-+	uint32_t                           dpm_table_start;          /* The start of the dpm table in the SMC SRAM. */
-+	uint32_t                           soft_regs_start;          /* The start of the soft registers in the SMC SRAM. */
-+	uint32_t                           mc_reg_table_start;       /* The start of the mc register table in the SMC SRAM. */
-+	uint32_t                           fan_table_start;          /* The start of the fan table in the SMC SRAM. */
-+	uint32_t                           arb_table_start;          /* The start of the ARB setting table in the SMC SRAM. */
-+	SMU72_Discrete_DpmTable         smc_state_table;             /* The carbon copy of the SMC state table. */
-+	SMU72_Discrete_MCRegisters      mc_reg_table;
-+	SMU72_Discrete_Ulv              ulv_setting;                 /* The carbon copy of ULV setting. */
-+	/* -------------- Stuff originally coming from Evergreen --------------------*/
-+	phw_tonga_mc_reg_table			tonga_mc_reg_table;
-+	uint32_t                         vdd_ci_control;
-+	pp_atomctrl_voltage_table        vddc_voltage_table;
-+	pp_atomctrl_voltage_table        vddci_voltage_table;
-+	pp_atomctrl_voltage_table        vddgfx_voltage_table;
-+	pp_atomctrl_voltage_table        mvdd_voltage_table;
-+
-+	uint32_t                           mgcg_cgtt_local2;
-+	uint32_t                           mgcg_cgtt_local3;
-+	uint32_t                           gpio_debug;
-+	uint32_t							mc_micro_code_feature;
-+	uint32_t							highest_mclk;
-+	uint16_t                          acpi_vdd_ci;
-+	uint8_t                           mvdd_high_index;
-+	uint8_t                           mvdd_low_index;
-+	bool                         dll_defaule_on;
-+	bool                         performance_request_registered;
-+
-+	/* ----------------- Low Power Features ---------------------*/
-+	phw_tonga_bacos					bacos;
-+	phw_tonga_ulv_parm              ulv;
-+	/* ----------------- CAC Stuff ---------------------*/
-+	uint32_t					cac_table_start;
-+	bool                         cac_configuration_required;    /* TRUE if PP_CACConfigurationRequired == 1 */
-+	bool                         driver_calculate_cac_leakage;  /* TRUE if PP_DriverCalculateCACLeakage == 1 */
-+	bool                         cac_enabled;
-+	/* ----------------- DPM2 Parameters ---------------------*/
-+	uint32_t					power_containment_features;
-+	bool                         enable_bapm_feature;
-+	bool                         enable_tdc_limit_feature;
-+	bool                         enable_pkg_pwr_tracking_feature;
-+	bool                         disable_uvd_power_tune_feature;
-+	phw_tonga_pt_defaults           *power_tune_defaults;
-+	SMU72_Discrete_PmFuses           power_tune_table;
-+	uint32_t                           ul_dte_tj_offset;             /* Fudge factor in DPM table to correct HW DTE errors */
-+	uint32_t                           fast_watemark_threshold;      /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
-+
-+	/* ----------------- Phase Shedding ---------------------*/
-+	bool                         vddc_phase_shed_control;
-+	/* --------------------- DI/DT --------------------------*/
-+	phw_tonga_display_timing       display_timing;
-+	/* --------- ReadRegistry data for memory and engine clock margins ---- */
-+	uint32_t                           engine_clock_data;
-+	uint32_t                           memory_clock_data;
-+	/* -------- Thermal Temperature Setting --------------*/
-+	phw_tonga_dpmlevel_enable_mask     dpm_level_enable_mask;
-+	uint32_t                           need_update_smu7_dpm_table;
-+	uint32_t                           sclk_dpm_key_disabled;
-+	uint32_t                           mclk_dpm_key_disabled;
-+	uint32_t                           pcie_dpm_key_disabled;
-+	uint32_t                           min_engine_clocks; /* used to store the previous dal min sclock */
-+	phw_tonga_pcie_perf_range       pcie_gen_performance;
-+	phw_tonga_pcie_perf_range       pcie_lane_performance;
-+	phw_tonga_pcie_perf_range       pcie_gen_power_saving;
-+	phw_tonga_pcie_perf_range       pcie_lane_power_saving;
-+	bool                            use_pcie_performance_levels;
-+	bool                            use_pcie_power_saving_levels;
-+	uint32_t                           activity_target[SMU72_MAX_LEVELS_GRAPHICS]; /* percentage value from 0-100, default 50 */
-+	uint32_t                           mclk_activity_target;
-+	uint32_t                           low_sclk_interrupt_threshold;
-+	uint32_t                           last_mclk_dpm_enable_mask;
-+	bool								uvd_enabled;
-+	uint32_t                           pcc_monitor_enabled;
-+
-+	/* --------- Power Gating States ------------*/
-+	bool                           uvd_power_gated;  /* 1: gated, 0:not gated */
-+	bool                           vce_power_gated;  /* 1: gated, 0:not gated */
-+	bool                           samu_power_gated; /* 1: gated, 0:not gated */
-+	bool                           acp_power_gated;  /* 1: gated, 0:not gated */
-+	bool                           pg_acp_init;
-+
-+};
-+
-+typedef struct tonga_hwmgr tonga_hwmgr;
-+
-+#define TONGA_DPM2_NEAR_TDP_DEC          10
-+#define TONGA_DPM2_ABOVE_SAFE_INC        5
-+#define TONGA_DPM2_BELOW_SAFE_INC        20
-+
-+#define TONGA_DPM2_LTA_WINDOW_SIZE       7  /* Log2 of the LTA window size (l2numWin_TDP). Eg. If LTA windows size is 128, then this value should be Log2(128) = 7. */
-+
-+#define TONGA_DPM2_LTS_TRUNCATE          0
-+
-+#define TONGA_DPM2_TDP_SAFE_LIMIT_PERCENT            80  /* Maximum 100 */
-+
-+#define TONGA_DPM2_MAXPS_PERCENT_H                   90  /* Maximum 0xFF */
-+#define TONGA_DPM2_MAXPS_PERCENT_M                   90  /* Maximum 0xFF */
-+
-+#define TONGA_DPM2_PWREFFICIENCYRATIO_MARGIN         50
-+
-+#define TONGA_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
-+#define TONGA_DPM2_SQ_RAMP_MIN_POWER                 0x12
-+#define TONGA_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
-+#define TONGA_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
-+#define TONGA_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
-+
-+#define TONGA_VOLTAGE_CONTROL_NONE                   0x0
-+#define TONGA_VOLTAGE_CONTROL_BY_GPIO                0x1
-+#define TONGA_VOLTAGE_CONTROL_BY_SVID2               0x2
-+#define TONGA_VOLTAGE_CONTROL_MERGED                 0x3
-+
-+#define TONGA_Q88_FORMAT_CONVERSION_UNIT             256 /*To convert to Q8.8 format for firmware */
-+
-+#define TONGA_UNUSED_GPIO_PIN                        0x7F
-+
-+/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
-+
-+/* Following flags shows PCIe link speed supported by ASIC H/W.*/
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
-+
-+/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
-+
-+#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
-+#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
-+
-+#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
-+#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
-+
-+#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
-+#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
-+
-+#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
-+
-+int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.h
-new file mode 100644
-index 0000000..8e6670b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.h
-@@ -0,0 +1,66 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef TONGA_POWERTUNE_H
-+#define TONGA_POWERTUNE_H
-+
-+enum _phw_tonga_ptc_config_reg_type {
-+	TONGA_CONFIGREG_MMR = 0,
-+	TONGA_CONFIGREG_SMC_IND,
-+	TONGA_CONFIGREG_DIDT_IND,
-+	TONGA_CONFIGREG_CACHE,
-+
-+	TONGA_CONFIGREG_MAX
-+};
-+typedef enum _phw_tonga_ptc_config_reg_type phw_tonga_ptc_config_reg_type;
-+
-+/* PowerContainment Features */
-+#define POWERCONTAINMENT_FEATURE_BAPM            0x00000001
-+#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
-+#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
-+
-+struct _phw_tonga_pt_config_reg {
-+	uint32_t                           Offset;
-+	uint32_t                           Mask;
-+	uint32_t                           Shift;
-+	uint32_t                           Value;
-+	phw_tonga_ptc_config_reg_type     Type;
-+};
-+typedef struct _phw_tonga_pt_config_reg phw_tonga_pt_config_reg;
-+
-+struct _phw_tonga_pt_defaults {
-+	uint8_t   svi_load_line_en;
-+	uint8_t   svi_load_line_vddC;
-+	uint8_t   tdc_vddc_throttle_release_limit_perc;
-+	uint8_t   tdc_mawt;
-+	uint8_t   tdc_waterfall_ctl;
-+	uint8_t   dte_ambient_temp_base;
-+	uint32_t  display_cac;
-+	uint32_t  bamp_temp_gradient;
-+	uint16_t  bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
-+	uint16_t  bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
-+};
-+typedef struct _phw_tonga_pt_defaults phw_tonga_pt_defaults;
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-new file mode 100644
-index 0000000..9a4456e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-@@ -0,0 +1,406 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef TONGA_PPTABLE_H
-+#define TONGA_PPTABLE_H
-+
-+/** \file
-+ * This is a PowerPlay table header file
-+ */
-+#pragma pack(push, 1)
-+
-+#include "hwmgr.h"
-+
-+#define ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
-+#define ATOM_TONGA_PP_FANPARAMETERS_NOFAN                                 0x80    /* No fan is connected to this controller. */
-+
-+#define ATOM_TONGA_PP_THERMALCONTROLLER_NONE      0
-+#define ATOM_TONGA_PP_THERMALCONTROLLER_LM96163   17
-+#define ATOM_TONGA_PP_THERMALCONTROLLER_TONGA     21
-+#define ATOM_TONGA_PP_THERMALCONTROLLER_FIJI      22
-+
-+/*
-+ * Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
-+ * We probably should reserve the bit 0x80 for this use.
-+ * To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
-+ * The driver can pick the correct internal controller based on the ASIC.
-+ */
-+
-+#define ATOM_TONGA_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL   0x89    /* ADT7473 Fan Control + Internal Thermal Controller */
-+#define ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL   0x8D    /* EMC2103 Fan Control + Internal Thermal Controller */
-+
-+/*/* ATOM_TONGA_POWERPLAYTABLE::ulPlatformCaps */
-+#define ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL              0x1            /* This cap indicates whether vddgfx will be a separated power rail. */
-+#define ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY                   0x2            /* This cap indicates whether this is a mobile part and CCC need to show Powerplay page. */
-+#define ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE            0x4            /* This cap indicates whether power source notificaiton is done by SBIOS directly. */
-+#define ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND      0x8            /* Enable the option to overwrite voltage island feature to be disabled, regardless of VddGfx power rail support. */
-+#define ____RETIRE16____                                0x10
-+#define ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC                 0x20            /* This cap indicates whether power source notificaiton is done by GPIO directly. */
-+#define ____RETIRE64____                                0x40
-+#define ____RETIRE128____                               0x80
-+#define ____RETIRE256____                              0x100
-+#define ____RETIRE512____                              0x200
-+#define ____RETIRE1024____                             0x400
-+#define ____RETIRE2048____                             0x800
-+#define ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL             0x1000            /* This cap indicates dynamic MVDD is required. Uncheck to disable it. */
-+#define ____RETIRE2000____                            0x2000
-+#define ____RETIRE4000____                            0x4000
-+#define ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL            0x8000            /* This cap indicates dynamic VDDCI is required. Uncheck to disable it. */
-+#define ____RETIRE10000____                          0x10000
-+#define ATOM_TONGA_PP_PLATFORM_CAP_BACO                    0x20000            /* Enable to indicate the driver supports BACO state. */
-+
-+#define ATOM_TONGA_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17         0x100000     /* Enable to indicate the driver supports thermal2GPIO17. */
-+#define ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL  0x1000000     /* Enable to indicate if thermal and PCC are sharing the same GPIO */
-+#define ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE       0x2000000
-+
-+/* ATOM_PPLIB_NONCLOCK_INFO::usClassification */
-+#define ATOM_PPLIB_CLASSIFICATION_UI_MASK               0x0007
-+#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT              0
-+#define ATOM_PPLIB_CLASSIFICATION_UI_NONE               0
-+#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY            1
-+#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED           3
-+#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE        5
-+/* 2, 4, 6, 7 are reserved */
-+
-+#define ATOM_PPLIB_CLASSIFICATION_BOOT                  0x0008
-+#define ATOM_PPLIB_CLASSIFICATION_THERMAL               0x0010
-+#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE    0x0020
-+#define ATOM_PPLIB_CLASSIFICATION_REST                  0x0040
-+#define ATOM_PPLIB_CLASSIFICATION_FORCED                0x0080
-+#define ATOM_PPLIB_CLASSIFICATION_ACPI                  0x1000
-+
-+/* ATOM_PPLIB_NONCLOCK_INFO::usClassification2 */
-+#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
-+
-+#define ATOM_Tonga_DISALLOW_ON_DC                       0x00004000
-+#define ATOM_Tonga_ENABLE_VARIBRIGHT                    0x00008000
-+
-+#define ATOM_Tonga_TABLE_REVISION_TONGA                 7
-+
-+typedef struct _ATOM_Tonga_POWERPLAYTABLE {
-+	ATOM_COMMON_TABLE_HEADER sHeader;
-+
-+	UCHAR  ucTableRevision;
-+	USHORT usTableSize;						/*the size of header structure */
-+
-+	ULONG	ulGoldenPPID;
-+	ULONG	ulGoldenRevision;
-+	USHORT	usFormatID;
-+
-+	USHORT	usVoltageTime;					 /*in microseconds */
-+	ULONG	ulPlatformCaps;					  /*See ATOM_Tonga_CAPS_* */
-+
-+	ULONG	ulMaxODEngineClock; 			   /*For Overdrive.  */
-+	ULONG	ulMaxODMemoryClock; 			   /*For Overdrive. */
-+
-+	USHORT	usPowerControlLimit;
-+	USHORT	usUlvVoltageOffset;				  /*in mv units */
-+
-+	USHORT	usStateArrayOffset;				  /*points to ATOM_Tonga_State_Array */
-+	USHORT	usFanTableOffset;				  /*points to ATOM_Tonga_Fan_Table */
-+	USHORT	usThermalControllerOffset;		   /*points to ATOM_Tonga_Thermal_Controller */
-+	USHORT	usReserv;						   /*CustomThermalPolicy removed for Tonga. Keep this filed as reserved. */
-+
-+	USHORT	usMclkDependencyTableOffset;	   /*points to ATOM_Tonga_MCLK_Dependency_Table */
-+	USHORT	usSclkDependencyTableOffset;	   /*points to ATOM_Tonga_SCLK_Dependency_Table */
-+	USHORT	usVddcLookupTableOffset;		   /*points to ATOM_Tonga_Voltage_Lookup_Table */
-+	USHORT	usVddgfxLookupTableOffset; 		/*points to ATOM_Tonga_Voltage_Lookup_Table */
-+
-+	USHORT	usMMDependencyTableOffset;		  /*points to ATOM_Tonga_MM_Dependency_Table */
-+
-+	USHORT	usVCEStateTableOffset;			   /*points to ATOM_Tonga_VCE_State_Table; */
-+
-+	USHORT	usPPMTableOffset;				  /*points to ATOM_Tonga_PPM_Table */
-+	USHORT	usPowerTuneTableOffset;			  /*points to ATOM_PowerTune_Table */
-+
-+	USHORT	usHardLimitTableOffset; 		   /*points to ATOM_Tonga_Hard_Limit_Table */
-+
-+	USHORT	usPCIETableOffset;				  /*points to ATOM_Tonga_PCIE_Table */
-+
-+	USHORT	usGPIOTableOffset;				  /*points to ATOM_Tonga_GPIO_Table */
-+
-+	USHORT	usReserved[6];					   /*TODO: modify reserved size to fit structure aligning */
-+} ATOM_Tonga_POWERPLAYTABLE;
-+
-+typedef struct _ATOM_Tonga_State {
-+	UCHAR  ucEngineClockIndexHigh;
-+	UCHAR  ucEngineClockIndexLow;
-+
-+	UCHAR  ucMemoryClockIndexHigh;
-+	UCHAR  ucMemoryClockIndexLow;
-+
-+	UCHAR  ucPCIEGenLow;
-+	UCHAR  ucPCIEGenHigh;
-+
-+	UCHAR  ucPCIELaneLow;
-+	UCHAR  ucPCIELaneHigh;
-+
-+	USHORT usClassification;
-+	ULONG ulCapsAndSettings;
-+	USHORT usClassification2;
-+	UCHAR  ucUnused[4];
-+} ATOM_Tonga_State;
-+
-+typedef struct _ATOM_Tonga_State_Array {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries;		/* Number of entries. */
-+	ATOM_Tonga_State states[1];	/* Dynamically allocate entries. */
-+} ATOM_Tonga_State_Array;
-+
-+typedef struct _ATOM_Tonga_MCLK_Dependency_Record {
-+	UCHAR  ucVddcInd;	/* Vddc voltage */
-+	USHORT usVddci;
-+	USHORT usVddgfxOffset;	/* Offset relative to Vddc voltage */
-+	USHORT usMvdd;
-+	ULONG ulMclk;
-+	USHORT usReserved;
-+} ATOM_Tonga_MCLK_Dependency_Record;
-+
-+typedef struct _ATOM_Tonga_MCLK_Dependency_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries; 										/* Number of entries. */
-+	ATOM_Tonga_MCLK_Dependency_Record entries[1];				/* Dynamically allocate entries. */
-+} ATOM_Tonga_MCLK_Dependency_Table;
-+
-+typedef struct _ATOM_Tonga_SCLK_Dependency_Record {
-+	UCHAR  ucVddInd;											/* Base voltage */
-+	USHORT usVddcOffset;										/* Offset relative to base voltage */
-+	ULONG ulSclk;
-+	USHORT usEdcCurrent;
-+	UCHAR  ucReliabilityTemperature;
-+	UCHAR  ucCKSVOffsetandDisable;							  /* Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level. */
-+} ATOM_Tonga_SCLK_Dependency_Record;
-+
-+typedef struct _ATOM_Tonga_SCLK_Dependency_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries; 										/* Number of entries. */
-+	ATOM_Tonga_SCLK_Dependency_Record entries[1];				 /* Dynamically allocate entries. */
-+} ATOM_Tonga_SCLK_Dependency_Table;
-+
-+typedef struct _ATOM_Tonga_PCIE_Record {
-+	UCHAR ucPCIEGenSpeed;
-+	UCHAR usPCIELaneWidth;
-+	UCHAR ucReserved[2];
-+} ATOM_Tonga_PCIE_Record;
-+
-+typedef struct _ATOM_Tonga_PCIE_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries; 										/* Number of entries. */
-+	ATOM_Tonga_PCIE_Record entries[1];							/* Dynamically allocate entries. */
-+} ATOM_Tonga_PCIE_Table;
-+
-+typedef struct _ATOM_Tonga_MM_Dependency_Record {
-+	UCHAR   ucVddcInd;											 /* VDDC voltage */
-+	USHORT  usVddgfxOffset;									  /* Offset relative to VDDC voltage */
-+	ULONG  ulDClk;												/* UVD D-clock */
-+	ULONG  ulVClk;												/* UVD V-clock */
-+	ULONG  ulEClk;												/* VCE clock */
-+	ULONG  ulAClk;												/* ACP clock */
-+	ULONG  ulSAMUClk;											/* SAMU clock */
-+} ATOM_Tonga_MM_Dependency_Record;
-+
-+typedef struct _ATOM_Tonga_MM_Dependency_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries; 										/* Number of entries. */
-+	ATOM_Tonga_MM_Dependency_Record entries[1]; 			   /* Dynamically allocate entries. */
-+} ATOM_Tonga_MM_Dependency_Table;
-+
-+typedef struct _ATOM_Tonga_Voltage_Lookup_Record {
-+	USHORT usVdd;											   /* Base voltage */
-+	USHORT usCACLow;
-+	USHORT usCACMid;
-+	USHORT usCACHigh;
-+} ATOM_Tonga_Voltage_Lookup_Record;
-+
-+typedef struct _ATOM_Tonga_Voltage_Lookup_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries; 										/* Number of entries. */
-+	ATOM_Tonga_Voltage_Lookup_Record entries[1];				/* Dynamically allocate entries. */
-+} ATOM_Tonga_Voltage_Lookup_Table;
-+
-+typedef struct _ATOM_Tonga_Fan_Table {
-+	UCHAR   ucRevId;						 /* Change this if the table format changes or version changes so that the other fields are not the same. */
-+	UCHAR   ucTHyst;						 /* Temperature hysteresis. Integer. */
-+	USHORT  usTMin; 						 /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
-+	USHORT  usTMed; 						 /* The middle temperature where we change slopes. */
-+	USHORT  usTHigh;						 /* The high point above TMed for adjusting the second slope. */
-+	USHORT  usPWMMin;						 /* The minimum PWM value in percent (0.01% increments). */
-+	USHORT  usPWMMed;						 /* The PWM value (in percent) at TMed. */
-+	USHORT  usPWMHigh;						 /* The PWM value at THigh. */
-+	USHORT  usTMax; 						 /* The max temperature */
-+	UCHAR   ucFanControlMode;				  /* Legacy or Fuzzy Fan mode */
-+	USHORT  usFanPWMMax;					  /* Maximum allowed fan power in percent */
-+	USHORT  usFanOutputSensitivity;		  /* Sensitivity of fan reaction to temepature changes */
-+	USHORT  usFanRPMMax;					  /* The default value in RPM */
-+	ULONG  ulMinFanSCLKAcousticLimit;	   /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
-+	UCHAR   ucTargetTemperature;			 /* Advanced fan controller target temperature. */
-+	UCHAR   ucMinimumPWMLimit; 			  /* The minimum PWM that the advanced fan controller can set.	This should be set to the highest PWM that will run the fan at its lowest RPM. */
-+	USHORT  usReserved;
-+} ATOM_Tonga_Fan_Table;
-+
-+typedef struct _ATOM_Fiji_Fan_Table {
-+	UCHAR   ucRevId;						 /* Change this if the table format changes or version changes so that the other fields are not the same. */
-+	UCHAR   ucTHyst;						 /* Temperature hysteresis. Integer. */
-+	USHORT  usTMin; 						 /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
-+	USHORT  usTMed; 						 /* The middle temperature where we change slopes. */
-+	USHORT  usTHigh;						 /* The high point above TMed for adjusting the second slope. */
-+	USHORT  usPWMMin;						 /* The minimum PWM value in percent (0.01% increments). */
-+	USHORT  usPWMMed;						 /* The PWM value (in percent) at TMed. */
-+	USHORT  usPWMHigh;						 /* The PWM value at THigh. */
-+	USHORT  usTMax; 						 /* The max temperature */
-+	UCHAR   ucFanControlMode;				  /* Legacy or Fuzzy Fan mode */
-+	USHORT  usFanPWMMax;					  /* Maximum allowed fan power in percent */
-+	USHORT  usFanOutputSensitivity;		  /* Sensitivity of fan reaction to temepature changes */
-+	USHORT  usFanRPMMax;					  /* The default value in RPM */
-+	ULONG  ulMinFanSCLKAcousticLimit;		/* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
-+	UCHAR   ucTargetTemperature;			 /* Advanced fan controller target temperature. */
-+	UCHAR   ucMinimumPWMLimit; 			  /* The minimum PWM that the advanced fan controller can set.	This should be set to the highest PWM that will run the fan at its lowest RPM. */
-+	USHORT  usFanGainEdge;
-+	USHORT  usFanGainHotspot;
-+	USHORT  usFanGainLiquid;
-+	USHORT  usFanGainVrVddc;
-+	USHORT  usFanGainVrMvdd;
-+	USHORT  usFanGainPlx;
-+	USHORT  usFanGainHbm;
-+	USHORT  usReserved;
-+} ATOM_Fiji_Fan_Table;
-+
-+typedef struct _ATOM_Tonga_Thermal_Controller {
-+	UCHAR ucRevId;
-+	UCHAR ucType;		   /* one of ATOM_TONGA_PP_THERMALCONTROLLER_* */
-+	UCHAR ucI2cLine;		/* as interpreted by DAL I2C */
-+	UCHAR ucI2cAddress;
-+	UCHAR ucFanParameters;	/* Fan Control Parameters. */
-+	UCHAR ucFanMinRPM; 	 /* Fan Minimum RPM (hundreds) -- for display purposes only. */
-+	UCHAR ucFanMaxRPM; 	 /* Fan Maximum RPM (hundreds) -- for display purposes only. */
-+	UCHAR ucReserved;
-+	UCHAR ucFlags;		   /* to be defined */
-+} ATOM_Tonga_Thermal_Controller;
-+
-+typedef struct _ATOM_Tonga_VCE_State_Record {
-+	UCHAR  ucVCEClockIndex;	/*index into usVCEDependencyTableOffset of 'ATOM_Tonga_MM_Dependency_Table' type */
-+	UCHAR  ucFlag;		/* 2 bits indicates memory p-states */
-+	UCHAR  ucSCLKIndex;		/*index into ATOM_Tonga_SCLK_Dependency_Table */
-+	UCHAR  ucMCLKIndex;		/*index into ATOM_Tonga_MCLK_Dependency_Table */
-+} ATOM_Tonga_VCE_State_Record;
-+
-+typedef struct _ATOM_Tonga_VCE_State_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries;
-+	ATOM_Tonga_VCE_State_Record entries[1];
-+} ATOM_Tonga_VCE_State_Table;
-+
-+typedef struct _ATOM_Tonga_PowerTune_Table {
-+	UCHAR  ucRevId;
-+	USHORT usTDP;
-+	USHORT usConfigurableTDP;
-+	USHORT usTDC;
-+	USHORT usBatteryPowerLimit;
-+	USHORT usSmallPowerLimit;
-+	USHORT usLowCACLeakage;
-+	USHORT usHighCACLeakage;
-+	USHORT usMaximumPowerDeliveryLimit;
-+	USHORT usTjMax;
-+	USHORT usPowerTuneDataSetID;
-+	USHORT usEDCLimit;
-+	USHORT usSoftwareShutdownTemp;
-+	USHORT usClockStretchAmount;
-+	USHORT usReserve[2];
-+} ATOM_Tonga_PowerTune_Table;
-+
-+typedef struct _ATOM_Fiji_PowerTune_Table {
-+	UCHAR  ucRevId;
-+	USHORT usTDP;
-+	USHORT usConfigurableTDP;
-+	USHORT usTDC;
-+	USHORT usBatteryPowerLimit;
-+	USHORT usSmallPowerLimit;
-+	USHORT usLowCACLeakage;
-+	USHORT usHighCACLeakage;
-+	USHORT usMaximumPowerDeliveryLimit;
-+	USHORT usTjMax;  /* For Fiji, this is also usTemperatureLimitEdge; */
-+	USHORT usPowerTuneDataSetID;
-+	USHORT usEDCLimit;
-+	USHORT usSoftwareShutdownTemp;
-+	USHORT usClockStretchAmount;
-+	USHORT usTemperatureLimitHotspot;  /*The following are added for Fiji */
-+	USHORT usTemperatureLimitLiquid1;
-+	USHORT usTemperatureLimitLiquid2;
-+	USHORT usTemperatureLimitVrVddc;
-+	USHORT usTemperatureLimitVrMvdd;
-+	USHORT usTemperatureLimitPlx;
-+	UCHAR  ucLiquid1_I2C_address;  /*Liquid */
-+	UCHAR  ucLiquid2_I2C_address;
-+	UCHAR  ucLiquid_I2C_Line;
-+	UCHAR  ucVr_I2C_address;	/*VR */
-+	UCHAR  ucVr_I2C_Line;
-+	UCHAR  ucPlx_I2C_address;  /*PLX */
-+	UCHAR  ucPlx_I2C_Line;
-+	USHORT usReserved;
-+} ATOM_Fiji_PowerTune_Table;
-+
-+#define ATOM_PPM_A_A    1
-+#define ATOM_PPM_A_I    2
-+typedef struct _ATOM_Tonga_PPM_Table {
-+	UCHAR   ucRevId;
-+	UCHAR   ucPpmDesign;		  /*A+I or A+A */
-+	USHORT  usCpuCoreNumber;
-+	ULONG  ulPlatformTDP;
-+	ULONG  ulSmallACPlatformTDP;
-+	ULONG  ulPlatformTDC;
-+	ULONG  ulSmallACPlatformTDC;
-+	ULONG  ulApuTDP;
-+	ULONG  ulDGpuTDP;
-+	ULONG  ulDGpuUlvPower;
-+	ULONG  ulTjmax;
-+} ATOM_Tonga_PPM_Table;
-+
-+typedef struct _ATOM_Tonga_Hard_Limit_Record {
-+	ULONG  ulSCLKLimit;
-+	ULONG  ulMCLKLimit;
-+	USHORT  usVddcLimit;
-+	USHORT  usVddciLimit;
-+	USHORT  usVddgfxLimit;
-+} ATOM_Tonga_Hard_Limit_Record;
-+
-+typedef struct _ATOM_Tonga_Hard_Limit_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries;
-+	ATOM_Tonga_Hard_Limit_Record entries[1];
-+} ATOM_Tonga_Hard_Limit_Table;
-+
-+typedef struct _ATOM_Tonga_GPIO_Table {
-+	UCHAR  ucRevId;
-+	UCHAR  ucVRHotTriggeredSclkDpmIndex;		/* If VRHot signal is triggered SCLK will be limited to this DPM level */
-+	UCHAR  ucReserve[5];
-+} ATOM_Tonga_GPIO_Table;
-+
-+typedef struct _PPTable_Generic_SubTable_Header {
-+	UCHAR  ucRevId;
-+} PPTable_Generic_SubTable_Header;
-+
-+
-+#pragma pack(pop)
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-new file mode 100644
-index 0000000..ddb03a0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -0,0 +1,1129 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+
-+#include "tonga_processpptables.h"
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "pp_debug.h"
-+#include "hwmgr.h"
-+#include "cgs_common.h"
-+#include "tonga_pptable.h"
-+
-+/**
-+ * Private Function used during initialization.
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param setIt A flag indication if the capability should be set (TRUE) or reset (FALSE).
-+ * @param cap Which capability to set/reset.
-+ */
-+static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap)
-+{
-+	if (setIt)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
-+	else
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
-+}
-+
-+
-+/**
-+ * Private Function used during initialization.
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param powerplay_caps the bit array (from BIOS) of capability bits.
-+ * @exception the current implementation always returns 1.
-+ */
-+static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
-+{
-+	PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),
-+		"ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!", continue);
-+	PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),
-+		"ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!", continue);
-+	PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),
-+		"ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!", continue);
-+	PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),
-+		"ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!", continue);
-+	PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),
-+		"ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!", continue);
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY),
-+			PHM_PlatformCaps_PowerPlaySupport
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
-+			PHM_PlatformCaps_BiosPowerSourceControl
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC),
-+			PHM_PlatformCaps_AutomaticDCTransition
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL),
-+			PHM_PlatformCaps_EnableMVDDControl
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL),
-+			PHM_PlatformCaps_ControlVDDCI
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL),
-+			PHM_PlatformCaps_ControlVDDGFX
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_BACO),
-+			PHM_PlatformCaps_BACO
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND),
-+			PHM_PlatformCaps_DisableVoltageIsland
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
-+			PHM_PlatformCaps_CombinePCCWithThermalSignal
-+		  );
-+
-+	set_hw_cap(
-+			hwmgr,
-+			0 != (powerplay_caps & ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE),
-+			PHM_PlatformCaps_LoadPostProductionFirmware
-+		  );
-+
-+	return 0;
-+}
-+
-+/**
-+ * Private Function to get the PowerPlay Table Address.
-+ */
-+const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
-+{
-+	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
-+
-+	u16 size;
-+	u8 frev, crev;
-+	void *table_address;
-+
-+	table_address = (ATOM_Tonga_POWERPLAYTABLE *)
-+		cgs_atom_get_data_table(hwmgr->device, index, &size, &frev, &crev);
-+
-+	hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
-+
-+	return table_address;
-+}
-+
-+static int get_vddc_lookup_table(
-+		struct pp_hwmgr	*hwmgr,
-+		phm_ppt_v1_voltage_lookup_table	**lookup_table,
-+		const ATOM_Tonga_Voltage_Lookup_Table	*vddc_lookup_pp_tables,
-+		uint32_t	max_levels
-+		)
-+{
-+	uint32_t table_size, i;
-+	phm_ppt_v1_voltage_lookup_table *table;
-+
-+	PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),
-+		"Invalid CAC Leakage PowerPlay Table!", return 1);
-+
-+	table_size = sizeof(uint32_t) +
-+		sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
-+
-+	table = (phm_ppt_v1_voltage_lookup_table *)
-+		kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -1;
-+
-+	memset(table, 0x00, table_size);
-+
-+	table->count = vddc_lookup_pp_tables->ucNumEntries;
-+
-+	for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) {
-+		table->entries[i].us_calculated = 0;
-+		table->entries[i].us_vdd =
-+			vddc_lookup_pp_tables->entries[i].usVdd;
-+		table->entries[i].us_cac_low =
-+			vddc_lookup_pp_tables->entries[i].usCACLow;
-+		table->entries[i].us_cac_mid =
-+			vddc_lookup_pp_tables->entries[i].usCACMid;
-+		table->entries[i].us_cac_high =
-+			vddc_lookup_pp_tables->entries[i].usCACHigh;
-+	}
-+
-+	*lookup_table = table;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Private Function used during initialization.
-+ * Initialize Platform Power Management Parameter table
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param atom_ppm_table Pointer to PPM table in VBIOS
-+ */
-+static int get_platform_power_management_table(
-+		struct pp_hwmgr *hwmgr,
-+		ATOM_Tonga_PPM_Table *atom_ppm_table)
-+{
-+	struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_Tonga_PPM_Table), GFP_KERNEL);
-+	struct phm_ppt_v1_information *pp_table_information =
-+		(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (NULL == ptr)
-+		return -1;
-+
-+	ptr->ppm_design
-+		= atom_ppm_table->ucPpmDesign;
-+	ptr->cpu_core_number
-+		= atom_ppm_table->usCpuCoreNumber;
-+	ptr->platform_tdp
-+		= atom_ppm_table->ulPlatformTDP;
-+	ptr->small_ac_platform_tdp
-+		= atom_ppm_table->ulSmallACPlatformTDP;
-+	ptr->platform_tdc
-+		= atom_ppm_table->ulPlatformTDC;
-+	ptr->small_ac_platform_tdc
-+		= atom_ppm_table->ulSmallACPlatformTDC;
-+	ptr->apu_tdp
-+		= atom_ppm_table->ulApuTDP;
-+	ptr->dgpu_tdp
-+		= atom_ppm_table->ulDGpuTDP;
-+	ptr->dgpu_ulv_power
-+		= atom_ppm_table->ulDGpuUlvPower;
-+	ptr->tj_max
-+		= atom_ppm_table->ulTjmax;
-+
-+	pp_table_information->ppm_parameter_table = ptr;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Private Function used during initialization.
-+ * Initialize TDP limits for DPM2
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param powerplay_table Pointer to the PowerPlay Table.
-+ */
-+static int init_dpm_2_parameters(
-+		struct pp_hwmgr *hwmgr,
-+		const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
-+		)
-+{
-+	int result = 0;
-+	struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	ATOM_Tonga_PPM_Table *atom_ppm_table;
-+	uint32_t disable_ppm = 0;
-+	uint32_t disable_power_control = 0;
-+
-+	pp_table_information->us_ulv_voltage_offset =
-+		le16_to_cpu(powerplay_table->usUlvVoltageOffset);
-+
-+	pp_table_information->ppm_parameter_table = NULL;
-+	pp_table_information->vddc_lookup_table = NULL;
-+	pp_table_information->vddgfx_lookup_table = NULL;
-+	/* TDP limits */
-+	hwmgr->platform_descriptor.TDPODLimit =
-+		le16_to_cpu(powerplay_table->usPowerControlLimit);
-+	hwmgr->platform_descriptor.TDPAdjustment = 0;
-+	hwmgr->platform_descriptor.VidAdjustment = 0;
-+	hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
-+	hwmgr->platform_descriptor.VidMinLimit = 0;
-+	hwmgr->platform_descriptor.VidMaxLimit = 1500000;
-+	hwmgr->platform_descriptor.VidStep = 6250;
-+
-+	disable_power_control = 0;
-+	if (0 == disable_power_control) {
-+		/* enable TDP overdrive (PowerControl) feature as well if supported */
-+		if (hwmgr->platform_descriptor.TDPODLimit != 0)
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerControl);
-+	}
-+
-+	if (0 != powerplay_table->usVddcLookupTableOffset) {
-+		const ATOM_Tonga_Voltage_Lookup_Table *pVddcCACTable =
-+			(ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
-+			le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
-+
-+		result = get_vddc_lookup_table(hwmgr,
-+			&pp_table_information->vddc_lookup_table, pVddcCACTable, 16);
-+	}
-+
-+	if (0 != powerplay_table->usVddgfxLookupTableOffset) {
-+		const ATOM_Tonga_Voltage_Lookup_Table *pVddgfxCACTable =
-+			(ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
-+			le16_to_cpu(powerplay_table->usVddgfxLookupTableOffset));
-+
-+		result = get_vddc_lookup_table(hwmgr,
-+			&pp_table_information->vddgfx_lookup_table, pVddgfxCACTable, 16);
-+	}
-+
-+	disable_ppm = 0;
-+	if (0 == disable_ppm) {
-+		atom_ppm_table = (ATOM_Tonga_PPM_Table *)
-+			(((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset));
-+
-+		if (0 != powerplay_table->usPPMTableOffset) {
-+			if (1 == get_platform_power_management_table(hwmgr, atom_ppm_table)) {
-+				phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_EnablePlatformPowerManagement);
-+			}
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+static int get_valid_clk(
-+		struct pp_hwmgr *hwmgr,
-+		struct phm_clock_array **clk_table,
-+		const phm_ppt_v1_clock_voltage_dependency_table  * clk_volt_pp_table
-+		)
-+{
-+	uint32_t table_size, i;
-+	struct phm_clock_array *table;
-+
-+	PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),
-+		"Invalid PowerPlay Table!", return -1);
-+
-+	table_size = sizeof(uint32_t) +
-+		sizeof(uint32_t) * clk_volt_pp_table->count;
-+
-+	table = (struct phm_clock_array *)kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -1;
-+
-+	memset(table, 0x00, table_size);
-+
-+	table->count = (uint32_t)clk_volt_pp_table->count;
-+
-+	for (i = 0; i < table->count; i++)
-+		table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
-+
-+	*clk_table = table;
-+
-+	return 0;
-+}
-+
-+static int get_hard_limits(
-+		struct pp_hwmgr *hwmgr,
-+		struct phm_clock_and_voltage_limits *limits,
-+		const ATOM_Tonga_Hard_Limit_Table * limitable
-+		)
-+{
-+	PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1);
-+
-+	/* currently we always take entries[0] parameters */
-+	limits->sclk = (uint32_t)limitable->entries[0].ulSCLKLimit;
-+	limits->mclk = (uint32_t)limitable->entries[0].ulMCLKLimit;
-+	limits->vddc = (uint16_t)limitable->entries[0].usVddcLimit;
-+	limits->vddci = (uint16_t)limitable->entries[0].usVddciLimit;
-+	limits->vddgfx = (uint16_t)limitable->entries[0].usVddgfxLimit;
-+
-+	return 0;
-+}
-+
-+static int get_mclk_voltage_dependency_table(
-+		struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table,
-+		const ATOM_Tonga_MCLK_Dependency_Table * mclk_dep_table
-+		)
-+{
-+	uint32_t table_size, i;
-+	phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
-+
-+	PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),
-+		"Invalid PowerPlay Table!", return -1);
-+
-+	table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
-+		* mclk_dep_table->ucNumEntries;
-+
-+	mclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
-+		kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == mclk_table)
-+		return -1;
-+
-+	memset(mclk_table, 0x00, table_size);
-+
-+	mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
-+
-+	for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
-+		mclk_table->entries[i].vddInd =
-+			mclk_dep_table->entries[i].ucVddcInd;
-+		mclk_table->entries[i].vdd_offset =
-+			mclk_dep_table->entries[i].usVddgfxOffset;
-+		mclk_table->entries[i].vddci =
-+			mclk_dep_table->entries[i].usVddci;
-+		mclk_table->entries[i].mvdd =
-+			mclk_dep_table->entries[i].usMvdd;
-+		mclk_table->entries[i].clk =
-+			mclk_dep_table->entries[i].ulMclk;
-+	}
-+
-+	*pp_tonga_mclk_dep_table = mclk_table;
-+
-+	return 0;
-+}
-+
-+static int get_sclk_voltage_dependency_table(
-+		struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table,
-+		const ATOM_Tonga_SCLK_Dependency_Table * sclk_dep_table
-+		)
-+{
-+	uint32_t table_size, i;
-+	phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
-+
-+	PP_ASSERT_WITH_CODE((0 != sclk_dep_table->ucNumEntries),
-+		"Invalid PowerPlay Table!", return -1);
-+
-+	table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
-+		* sclk_dep_table->ucNumEntries;
-+
-+	sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
-+		kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == sclk_table)
-+		return -1;
-+
-+	memset(sclk_table, 0x00, table_size);
-+
-+	sclk_table->count = (uint32_t)sclk_dep_table->ucNumEntries;
-+
-+	for (i = 0; i < sclk_dep_table->ucNumEntries; i++) {
-+		sclk_table->entries[i].vddInd =
-+			sclk_dep_table->entries[i].ucVddInd;
-+		sclk_table->entries[i].vdd_offset =
-+			sclk_dep_table->entries[i].usVddcOffset;
-+		sclk_table->entries[i].clk =
-+			sclk_dep_table->entries[i].ulSclk;
-+		sclk_table->entries[i].cks_enable =
-+			(((sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
-+		sclk_table->entries[i].cks_voffset =
-+			(sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
-+	}
-+
-+	*pp_tonga_sclk_dep_table = sclk_table;
-+
-+	return 0;
-+}
-+
-+static int get_pcie_table(
-+		struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_pcie_table **pp_tonga_pcie_table,
-+		const ATOM_Tonga_PCIE_Table * atom_pcie_table
-+		)
-+{
-+	uint32_t table_size, i, pcie_count;
-+	phm_ppt_v1_pcie_table *pcie_table;
-+	struct phm_ppt_v1_information *pp_table_information =
-+		(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	PP_ASSERT_WITH_CODE((0 != atom_pcie_table->ucNumEntries),
-+		"Invalid PowerPlay Table!", return -1);
-+
-+	table_size = sizeof(uint32_t) +
-+		sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
-+
-+	pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == pcie_table)
-+		return -1;
-+
-+	memset(pcie_table, 0x00, table_size);
-+
-+	/*
-+	* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
-+	* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
-+	*/
-+	pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
-+	if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
-+		pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
-+	else
-+		printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
-+		Disregarding the excess entries... \n");
-+
-+	pcie_table->count = pcie_count;
-+
-+	for (i = 0; i < pcie_count; i++) {
-+		pcie_table->entries[i].gen_speed =
-+			atom_pcie_table->entries[i].ucPCIEGenSpeed;
-+		pcie_table->entries[i].lane_width =
-+			atom_pcie_table->entries[i].usPCIELaneWidth;
-+	}
-+
-+	*pp_tonga_pcie_table = pcie_table;
-+
-+	return 0;
-+}
-+
-+static int get_cac_tdp_table(
-+		struct pp_hwmgr *hwmgr,
-+		struct phm_cac_tdp_table **cac_tdp_table,
-+		const PPTable_Generic_SubTable_Header * table
-+		)
-+{
-+	uint32_t table_size;
-+	struct phm_cac_tdp_table *tdp_table;
-+
-+	table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table);
-+	tdp_table = kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == tdp_table)
-+		return -1;
-+
-+	memset(tdp_table, 0x00, table_size);
-+
-+	hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == hwmgr->dyn_state.cac_dtp_table)
-+		return -1;
-+
-+	memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
-+
-+	if (table->ucRevId < 3) {
-+		const ATOM_Tonga_PowerTune_Table *tonga_table =
-+			(ATOM_Tonga_PowerTune_Table *)table;
-+		tdp_table->usTDP = tonga_table->usTDP;
-+		tdp_table->usConfigurableTDP =
-+			tonga_table->usConfigurableTDP;
-+		tdp_table->usTDC = tonga_table->usTDC;
-+		tdp_table->usBatteryPowerLimit =
-+			tonga_table->usBatteryPowerLimit;
-+		tdp_table->usSmallPowerLimit =
-+			tonga_table->usSmallPowerLimit;
-+		tdp_table->usLowCACLeakage =
-+			tonga_table->usLowCACLeakage;
-+		tdp_table->usHighCACLeakage =
-+			tonga_table->usHighCACLeakage;
-+		tdp_table->usMaximumPowerDeliveryLimit =
-+			tonga_table->usMaximumPowerDeliveryLimit;
-+		tdp_table->usDefaultTargetOperatingTemp =
-+			tonga_table->usTjMax;
-+		tdp_table->usTargetOperatingTemp =
-+			tonga_table->usTjMax; /*Set the initial temp to the same as default */
-+		tdp_table->usPowerTuneDataSetID =
-+			tonga_table->usPowerTuneDataSetID;
-+		tdp_table->usSoftwareShutdownTemp =
-+			tonga_table->usSoftwareShutdownTemp;
-+		tdp_table->usClockStretchAmount =
-+			tonga_table->usClockStretchAmount;
-+	} else {   /* Fiji and newer */
-+		const ATOM_Fiji_PowerTune_Table *fijitable =
-+			(ATOM_Fiji_PowerTune_Table *)table;
-+		tdp_table->usTDP = fijitable->usTDP;
-+		tdp_table->usConfigurableTDP = fijitable->usConfigurableTDP;
-+		tdp_table->usTDC = fijitable->usTDC;
-+		tdp_table->usBatteryPowerLimit = fijitable->usBatteryPowerLimit;
-+		tdp_table->usSmallPowerLimit = fijitable->usSmallPowerLimit;
-+		tdp_table->usLowCACLeakage = fijitable->usLowCACLeakage;
-+		tdp_table->usHighCACLeakage = fijitable->usHighCACLeakage;
-+		tdp_table->usMaximumPowerDeliveryLimit =
-+			fijitable->usMaximumPowerDeliveryLimit;
-+		tdp_table->usDefaultTargetOperatingTemp =
-+			fijitable->usTjMax;
-+		tdp_table->usTargetOperatingTemp =
-+			fijitable->usTjMax; /*Set the initial temp to the same as default */
-+		tdp_table->usPowerTuneDataSetID =
-+			fijitable->usPowerTuneDataSetID;
-+		tdp_table->usSoftwareShutdownTemp =
-+			fijitable->usSoftwareShutdownTemp;
-+		tdp_table->usClockStretchAmount =
-+			fijitable->usClockStretchAmount;
-+		tdp_table->usTemperatureLimitHotspot =
-+			fijitable->usTemperatureLimitHotspot;
-+		tdp_table->usTemperatureLimitLiquid1 =
-+			fijitable->usTemperatureLimitLiquid1;
-+		tdp_table->usTemperatureLimitLiquid2 =
-+			fijitable->usTemperatureLimitLiquid2;
-+		tdp_table->usTemperatureLimitVrVddc =
-+			fijitable->usTemperatureLimitVrVddc;
-+		tdp_table->usTemperatureLimitVrMvdd =
-+			fijitable->usTemperatureLimitVrMvdd;
-+		tdp_table->usTemperatureLimitPlx =
-+			fijitable->usTemperatureLimitPlx;
-+		tdp_table->ucLiquid1_I2C_address =
-+			fijitable->ucLiquid1_I2C_address;
-+		tdp_table->ucLiquid2_I2C_address =
-+			fijitable->ucLiquid2_I2C_address;
-+		tdp_table->ucLiquid_I2C_Line =
-+			fijitable->ucLiquid_I2C_Line;
-+		tdp_table->ucVr_I2C_address = fijitable->ucVr_I2C_address;
-+		tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line;
-+		tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address;
-+		tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line;
-+	}
-+
-+	*cac_tdp_table = tdp_table;
-+
-+	return 0;
-+}
-+
-+static int get_mm_clock_voltage_table(
-+		struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_mm_clock_voltage_dependency_table **tonga_mm_table,
-+		const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table
-+		)
-+{
-+	uint32_t table_size, i;
-+	const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record;
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
-+
-+	PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),
-+		"Invalid PowerPlay Table!", return -1);
-+	table_size = sizeof(uint32_t) +
-+		sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record)
-+		* mm_dependency_table->ucNumEntries;
-+	mm_table = (phm_ppt_v1_mm_clock_voltage_dependency_table *)
-+		kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == mm_table)
-+		return -1;
-+
-+	memset(mm_table, 0x00, table_size);
-+
-+	mm_table->count = mm_dependency_table->ucNumEntries;
-+
-+	for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
-+		mm_dependency_record = &mm_dependency_table->entries[i];
-+		mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
-+		mm_table->entries[i].vddgfx_offset = mm_dependency_record->usVddgfxOffset;
-+		mm_table->entries[i].aclk = mm_dependency_record->ulAClk;
-+		mm_table->entries[i].samclock = mm_dependency_record->ulSAMUClk;
-+		mm_table->entries[i].eclk = mm_dependency_record->ulEClk;
-+		mm_table->entries[i].vclk = mm_dependency_record->ulVClk;
-+		mm_table->entries[i].dclk = mm_dependency_record->ulDClk;
-+	}
-+
-+	*tonga_mm_table = mm_table;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Private Function used during initialization.
-+ * Initialize clock voltage dependency
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param powerplay_table Pointer to the PowerPlay Table.
-+ */
-+static int init_clock_voltage_dependency(
-+		struct pp_hwmgr *hwmgr,
-+		const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
-+		)
-+{
-+	int result = 0;
-+	struct phm_ppt_v1_information *pp_table_information =
-+		(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	const ATOM_Tonga_MM_Dependency_Table *mm_dependency_table =
-+		(const ATOM_Tonga_MM_Dependency_Table *)(((unsigned long) powerplay_table) +
-+		le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
-+	const PPTable_Generic_SubTable_Header *pPowerTuneTable =
-+		(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
-+		le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
-+	const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
-+		(const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
-+		le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
-+	const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-+		(const ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
-+		le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
-+	const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
-+		(const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
-+		le16_to_cpu(powerplay_table->usHardLimitTableOffset));
-+	const ATOM_Tonga_PCIE_Table *pcie_table =
-+		(const ATOM_Tonga_PCIE_Table *)(((unsigned long) powerplay_table) +
-+		le16_to_cpu(powerplay_table->usPCIETableOffset));
-+
-+	pp_table_information->vdd_dep_on_sclk = NULL;
-+	pp_table_information->vdd_dep_on_mclk = NULL;
-+	pp_table_information->mm_dep_table = NULL;
-+	pp_table_information->pcie_table = NULL;
-+
-+	if (powerplay_table->usMMDependencyTableOffset != 0)
-+		result = get_mm_clock_voltage_table(hwmgr,
-+		&pp_table_information->mm_dep_table, mm_dependency_table);
-+
-+	if (result == 0 && powerplay_table->usPowerTuneTableOffset != 0)
-+		result = get_cac_tdp_table(hwmgr,
-+		&pp_table_information->cac_dtp_table, pPowerTuneTable);
-+
-+	if (result == 0 && powerplay_table->usSclkDependencyTableOffset != 0)
-+		result = get_sclk_voltage_dependency_table(hwmgr,
-+		&pp_table_information->vdd_dep_on_sclk, sclk_dep_table);
-+
-+	if (result == 0 && powerplay_table->usMclkDependencyTableOffset != 0)
-+		result = get_mclk_voltage_dependency_table(hwmgr,
-+		&pp_table_information->vdd_dep_on_mclk, mclk_dep_table);
-+
-+	if (result == 0 && powerplay_table->usPCIETableOffset != 0)
-+		result = get_pcie_table(hwmgr,
-+		&pp_table_information->pcie_table, pcie_table);
-+
-+	if (result == 0 && powerplay_table->usHardLimitTableOffset != 0)
-+		result = get_hard_limits(hwmgr,
-+		&pp_table_information->max_clock_voltage_on_dc, pHardLimits);
-+
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
-+		pp_table_information->max_clock_voltage_on_dc.sclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
-+		pp_table_information->max_clock_voltage_on_dc.mclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
-+		pp_table_information->max_clock_voltage_on_dc.vddc;
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
-+		pp_table_information->max_clock_voltage_on_dc.vddci;
-+
-+	if (result == 0 && (NULL != pp_table_information->vdd_dep_on_mclk)
-+		&& (0 != pp_table_information->vdd_dep_on_mclk->count))
-+		result = get_valid_clk(hwmgr, &pp_table_information->valid_mclk_values,
-+		pp_table_information->vdd_dep_on_mclk);
-+
-+	if (result == 0 && (NULL != pp_table_information->vdd_dep_on_sclk)
-+		&& (0 != pp_table_information->vdd_dep_on_sclk->count))
-+		result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
-+		pp_table_information->vdd_dep_on_sclk);
-+
-+	return result;
-+}
-+
-+/** Retrieves the (signed) Overdrive limits from VBIOS.
-+ * The max engine clock, memory clock and max temperature come from the firmware info table.
-+ *
-+ * The information is placed into the platform descriptor.
-+ *
-+ * @param hwmgr source of the VBIOS table and owner of the platform descriptor to be updated.
-+ * @param powerplay_table the address of the PowerPlay table.
-+ *
-+ * @return 1 as long as the firmware info table was present and of a supported version.
-+ */
-+static int init_over_drive_limits(
-+		struct pp_hwmgr *hwmgr,
-+		const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
-+{
-+	hwmgr->platform_descriptor.overdriveLimit.engineClock =
-+		le16_to_cpu(powerplay_table->ulMaxODEngineClock);
-+	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
-+		le16_to_cpu(powerplay_table->ulMaxODMemoryClock);
-+
-+	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
-+	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
-+	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
-+
-+	if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 \
-+		&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ACOverdriveSupport);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Private Function used during initialization.
-+ * Inspect the PowerPlay table for obvious signs of corruption.
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param powerplay_table Pointer to the PowerPlay Table.
-+ * @exception This implementation always returns 1.
-+ */
-+static int init_thermal_controller(
-+		struct pp_hwmgr *hwmgr,
-+		const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
-+		)
-+{
-+	const PPTable_Generic_SubTable_Header *fan_table;
-+	ATOM_Tonga_Thermal_Controller *thermal_controller;
-+
-+	thermal_controller = (ATOM_Tonga_Thermal_Controller *)
-+		(((unsigned long)powerplay_table) +
-+		le16_to_cpu(powerplay_table->usThermalControllerOffset));
-+	PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset),
-+		"Thermal controller table not set!", return -1);
-+
-+	hwmgr->thermal_controller.ucType = thermal_controller->ucType;
-+	hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
-+	hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
-+
-+	hwmgr->thermal_controller.fanInfo.bNoFan =
-+		(0 != (thermal_controller->ucFanParameters & ATOM_TONGA_PP_FANPARAMETERS_NOFAN));
-+
-+	hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
-+		thermal_controller->ucFanParameters &
-+		ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
-+
-+	hwmgr->thermal_controller.fanInfo.ulMinRPM
-+		= thermal_controller->ucFanMinRPM * 100UL;
-+	hwmgr->thermal_controller.fanInfo.ulMaxRPM
-+		= thermal_controller->ucFanMaxRPM * 100UL;
-+
-+	set_hw_cap(
-+			hwmgr,
-+			ATOM_TONGA_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
-+			PHM_PlatformCaps_ThermalController
-+		  );
-+
-+	if (0 == powerplay_table->usFanTableOffset)
-+		return -1;
-+
-+	fan_table = (const PPTable_Generic_SubTable_Header *)
-+		(((unsigned long)powerplay_table) +
-+		le16_to_cpu(powerplay_table->usFanTableOffset));
-+
-+	PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset),
-+		"Fan table not set!", return -1);
-+	PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId),
-+		"Unsupported fan table format!", return -1);
-+
-+	hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
-+		= 100000;
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_MicrocodeFanControl);
-+
-+	if (fan_table->ucRevId < 8) {
-+		const ATOM_Tonga_Fan_Table *tonga_fan_table =
-+			(ATOM_Tonga_Fan_Table *)fan_table;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
-+			= tonga_fan_table->ucTHyst;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
-+			= tonga_fan_table->usTMin;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
-+			= tonga_fan_table->usTMed;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
-+			= tonga_fan_table->usTHigh;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
-+			= tonga_fan_table->usPWMMin;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
-+			= tonga_fan_table->usPWMMed;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
-+			= tonga_fan_table->usPWMHigh;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
-+			= 10900;                  /* hard coded */
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
-+			= tonga_fan_table->usTMax;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
-+			= tonga_fan_table->ucFanControlMode;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
-+			= tonga_fan_table->usFanPWMMax;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
-+			= 4836;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
-+			= tonga_fan_table->usFanOutputSensitivity;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
-+			= tonga_fan_table->usFanRPMMax;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
-+			= (tonga_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
-+			= tonga_fan_table->ucTargetTemperature;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
-+			= tonga_fan_table->ucMinimumPWMLimit;
-+	} else {
-+		const ATOM_Fiji_Fan_Table *fiji_fan_table =
-+			(ATOM_Fiji_Fan_Table *)fan_table;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
-+			= fiji_fan_table->ucTHyst;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
-+			= fiji_fan_table->usTMin;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
-+			= fiji_fan_table->usTMed;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
-+			= fiji_fan_table->usTHigh;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
-+			= fiji_fan_table->usPWMMin;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
-+			= fiji_fan_table->usPWMMed;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
-+			= fiji_fan_table->usPWMHigh;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
-+			= fiji_fan_table->usTMax;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
-+			= fiji_fan_table->ucFanControlMode;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
-+			= fiji_fan_table->usFanPWMMax;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
-+			= 4836;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
-+			= fiji_fan_table->usFanOutputSensitivity;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
-+			= fiji_fan_table->usFanRPMMax;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
-+			= (fiji_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
-+			= fiji_fan_table->ucTargetTemperature;
-+		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
-+			= fiji_fan_table->ucMinimumPWMLimit;
-+
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
-+			= fiji_fan_table->usFanGainEdge;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
-+			= fiji_fan_table->usFanGainHotspot;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
-+			= fiji_fan_table->usFanGainLiquid;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
-+			= fiji_fan_table->usFanGainVrVddc;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
-+			= fiji_fan_table->usFanGainVrMvdd;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
-+			= fiji_fan_table->usFanGainPlx;
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
-+			= fiji_fan_table->usFanGainHbm;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Private Function used during initialization.
-+ * Inspect the PowerPlay table for obvious signs of corruption.
-+ * @param hwmgr Pointer to the hardware manager.
-+ * @param powerplay_table Pointer to the PowerPlay Table.
-+ * @exception 2 if the powerplay table is incorrect.
-+ */
-+static int check_powerplay_tables(
-+		struct pp_hwmgr *hwmgr,
-+		const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
-+		)
-+{
-+	const ATOM_Tonga_State_Array *state_arrays;
-+
-+	state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)powerplay_table) +
-+		le16_to_cpu(powerplay_table->usStateArrayOffset));
-+
-+	PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <=
-+		powerplay_table->sHeader.ucTableFormatRevision),
-+		"Unsupported PPTable format!", return -1);
-+	PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset),
-+		"State table is not set!", return -1);
-+	PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize),
-+		"Invalid PowerPlay Table!", return -1);
-+	PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
-+		"Invalid PowerPlay Table!", return -1);
-+
-+	return 0;
-+}
-+
-+int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
-+
-+	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
-+
-+	if (NULL == hwmgr->pptable)
-+		return -1;
-+
-+	memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
-+
-+	powerplay_table = get_powerplay_table(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != powerplay_table),
-+		"Missing PowerPlay Table!", return -1);
-+
-+	result = check_powerplay_tables(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = set_platform_caps(hwmgr,
-+			le32_to_cpu(powerplay_table->ulPlatformCaps));
-+
-+	if (0 == result)
-+		result = init_thermal_controller(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = init_over_drive_limits(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = init_clock_voltage_dependency(hwmgr, powerplay_table);
-+
-+	if (0 == result)
-+		result = init_dpm_2_parameters(hwmgr, powerplay_table);
-+
-+	return result;
-+}
-+
-+int tonga_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	struct phm_ppt_v1_information *pp_table_information =
-+		(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (NULL != hwmgr->soft_pp_table) {
-+		kfree(hwmgr->soft_pp_table);
-+		hwmgr->soft_pp_table = NULL;
-+	}
-+
-+	if (NULL != pp_table_information->vdd_dep_on_sclk)
-+		pp_table_information->vdd_dep_on_sclk = NULL;
-+
-+	if (NULL != pp_table_information->vdd_dep_on_mclk)
-+		pp_table_information->vdd_dep_on_mclk = NULL;
-+
-+	if (NULL != pp_table_information->valid_mclk_values)
-+		pp_table_information->valid_mclk_values = NULL;
-+
-+	if (NULL != pp_table_information->valid_sclk_values)
-+		pp_table_information->valid_sclk_values = NULL;
-+
-+	if (NULL != pp_table_information->vddc_lookup_table)
-+		pp_table_information->vddc_lookup_table = NULL;
-+
-+	if (NULL != pp_table_information->vddgfx_lookup_table)
-+		pp_table_information->vddgfx_lookup_table = NULL;
-+
-+	if (NULL != pp_table_information->mm_dep_table)
-+		pp_table_information->mm_dep_table = NULL;
-+
-+	if (NULL != pp_table_information->cac_dtp_table)
-+		pp_table_information->cac_dtp_table = NULL;
-+
-+	if (NULL != hwmgr->dyn_state.cac_dtp_table)
-+		hwmgr->dyn_state.cac_dtp_table = NULL;
-+
-+	if (NULL != pp_table_information->ppm_parameter_table)
-+		pp_table_information->ppm_parameter_table = NULL;
-+
-+	if (NULL != pp_table_information->pcie_table)
-+		pp_table_information->pcie_table = NULL;
-+
-+	if (NULL != hwmgr->pptable) {
-+		kfree(hwmgr->pptable);
-+		hwmgr->pptable = NULL;
-+	}
-+
-+	return result;
-+}
-+
-+const struct pp_table_func tonga_pptable_funcs = {
-+	.pptable_init = tonga_pp_tables_initialize,
-+	.pptable_fini = tonga_pp_tables_uninitialize,
-+};
-+
-+int tonga_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
-+{
-+	const ATOM_Tonga_State_Array * state_arrays;
-+	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != pp_table),
-+			"Missing PowerPlay Table!", return -1);
-+	PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >=
-+			ATOM_Tonga_TABLE_REVISION_TONGA),
-+			"Incorrect PowerPlay table revision!", return -1);
-+
-+	state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
-+			le16_to_cpu(pp_table->usStateArrayOffset));
-+
-+	return (uint32_t)(state_arrays->ucNumEntries);
-+}
-+
-+/**
-+* Private function to convert flags stored in the BIOS to software flags in PowerPlay.
-+*/
-+static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
-+		uint16_t classification, uint16_t classification2)
-+{
-+	uint32_t result = 0;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
-+		result |= PP_StateClassificationFlag_Boot;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
-+		result |= PP_StateClassificationFlag_Thermal;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
-+		result |= PP_StateClassificationFlag_LimitedPowerSource;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
-+		result |= PP_StateClassificationFlag_Rest;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
-+		result |= PP_StateClassificationFlag_Forced;
-+
-+	if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
-+		result |= PP_StateClassificationFlag_ACPI;
-+
-+	if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
-+		result |= PP_StateClassificationFlag_LimitedPowerSource_2;
-+
-+	return result;
-+}
-+
-+/**
-+* Create a Power State out of an entry in the PowerPlay table.
-+* This function is called by the hardware back-end.
-+* @param hwmgr Pointer to the hardware manager.
-+* @param entry_index The index of the entry to be extracted from the table.
-+* @param power_state The address of the PowerState instance being created.
-+* @return -1 if the entry cannot be retrieved.
-+*/
-+int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
-+		uint32_t entry_index, struct pp_power_state *power_state,
-+		int (*call_back_func)(struct pp_hwmgr *, void *,
-+				struct pp_power_state *, void *, uint32_t))
-+{
-+	int result = 0;
-+	const ATOM_Tonga_State_Array * state_arrays;
-+	const ATOM_Tonga_State *state_entry;
-+	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);
-+	power_state->classification.bios_index = entry_index;
-+
-+	if (pp_table->sHeader.ucTableFormatRevision >=
-+			ATOM_Tonga_TABLE_REVISION_TONGA) {
-+		state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
-+				le16_to_cpu(pp_table->usStateArrayOffset));
-+
-+		PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset),
-+				"Invalid PowerPlay Table State Array Offset.", return -1);
-+		PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
-+				"Invalid PowerPlay Table State Array.", return -1);
-+		PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
-+				"Invalid PowerPlay Table State Array Entry.", return -1);
-+
-+		state_entry = &(state_arrays->states[entry_index]);
-+
-+		result = call_back_func(hwmgr, (void *)state_entry, power_state,
-+				(void *)pp_table,
-+				make_classification_flags(hwmgr,
-+					le16_to_cpu(state_entry->usClassification),
-+					le16_to_cpu(state_entry->usClassification2)));
-+	}
-+
-+	if (!result && (power_state->classification.flags &
-+			PP_StateClassificationFlag_Boot))
-+		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.h
-new file mode 100644
-index 0000000..d24b888
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef TONGA_PROCESSPPTABLES_H
-+#define TONGA_PROCESSPPTABLES_H
-+
-+#include "hwmgr.h"
-+
-+extern const struct pp_table_func tonga_pptable_funcs;
-+extern int tonga_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr);
-+extern int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index,
-+		struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
-+				struct pp_power_state *, void *, uint32_t));
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index a69b379..9795b9a 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -219,12 +219,12 @@ enum PHM_PerformanceLevelDesignation {
- typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
- 
- struct PHM_PerformanceLevel {
--	uint32_t    coreClock;
--	uint32_t    memory_clock;
--	uint32_t  vddc;
--	uint32_t  vddci;
--	uint32_t    nonLocalMemoryFreq;
--	uint32_t nonLocalMemoryWidth;
-+    uint32_t    coreClock;
-+    uint32_t    memory_clock;
-+    uint32_t  vddc;
-+    uint32_t  vddci;
-+    uint32_t    nonLocalMemoryFreq;
-+    uint32_t nonLocalMemoryWidth;
- };
- 
- typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
-@@ -251,9 +251,9 @@ static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps
- 
- #define PP_PCIEGenInvalid  0xffff
- enum PP_PCIEGen {
--	PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
--	PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
--	PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
-+    PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
-+    PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
-+    PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
- };
- 
- typedef enum PP_PCIEGen PP_PCIEGen;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 18b5ab1..ca513a1 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -28,6 +28,7 @@
- #include "pp_instance.h"
- #include "hardwaremanager.h"
- #include "pp_power_source.h"
-+#include "hwmgr_ppt.h"
- 
- struct pp_instance;
- struct pp_hwmgr;
-@@ -400,7 +401,24 @@ struct phm_clock_and_voltage_limits {
- 	uint16_t vddgfx;
- };
- 
-+/* Structure to hold PPTable information */
- 
-+struct phm_ppt_v1_information {
-+	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
-+	struct phm_clock_array *valid_sclk_values;
-+	struct phm_clock_array *valid_mclk_values;
-+	struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
-+	struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
-+	struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
-+	struct phm_ppm_table *ppm_parameter_table;
-+	struct phm_cac_tdp_table *cac_dtp_table;
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
-+	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
-+	struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
-+	struct phm_ppt_v1_pcie_table *pcie_table;
-+	uint16_t us_ulv_voltage_offset;
-+};
- 
- struct phm_dynamic_state_info {
- 	struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
-@@ -434,6 +452,70 @@ struct phm_dynamic_state_info {
- 	struct phm_vq_budgeting_table		  		  *vq_budgeting_table;
- };
- 
-+struct pp_fan_info {
-+	bool bNoFan;
-+	uint8_t   ucTachometerPulsesPerRevolution;
-+	uint32_t   ulMinRPM;
-+	uint32_t   ulMaxRPM;
-+};
-+
-+struct pp_advance_fan_control_parameters {
-+	uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
-+	uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
-+	uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
-+	uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
-+	uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
-+	uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
-+	uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
-+	uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
-+	uint16_t  usTMax;                          /* The max temperature */
-+	uint8_t   ucFanControlMode;
-+	uint16_t  usFanPWMMinLimit;
-+	uint16_t  usFanPWMMaxLimit;
-+	uint16_t  usFanPWMStep;
-+	uint16_t  usDefaultMaxFanPWM;
-+	uint16_t  usFanOutputSensitivity;
-+	uint16_t  usDefaultFanOutputSensitivity;
-+	uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
-+	uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
-+	uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
-+	uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
-+	uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
-+	uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
-+	uint16_t  usFanCurrentLow;                 /* Low current */
-+	uint16_t  usFanCurrentHigh;                /* High current */
-+	uint16_t  usFanRPMLow;                     /* Low RPM */
-+	uint16_t  usFanRPMHigh;                    /* High RPM */
-+	uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
-+	uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
-+	uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
-+	uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
-+	uint16_t  usFanGainHotspot;
-+	uint16_t  usFanGainLiquid;
-+	uint16_t  usFanGainVrVddc;
-+	uint16_t  usFanGainVrMvdd;
-+	uint16_t  usFanGainPlx;
-+	uint16_t  usFanGainHbm;
-+};
-+
-+struct pp_thermal_controller_info {
-+	uint8_t ucType;
-+	uint8_t ucI2cLine;
-+	uint8_t ucI2cAddress;
-+	struct pp_fan_info fanInfo;
-+	struct pp_advance_fan_control_parameters advanceFanControlParameters;
-+};
-+
-+struct phm_microcode_version_info {
-+	uint32_t SMC;
-+	uint32_t DMCU;
-+	uint32_t MC;
-+	uint32_t NB;
-+};
-+
-+/**
-+ * The main hardware manager structure.
-+ */
- struct pp_hwmgr {
- 	uint32_t chip_family;
- 	uint32_t chip_id;
-@@ -466,6 +548,8 @@ struct pp_hwmgr {
- 	struct pp_power_state    *ps;
-         enum pp_power_source  power_source;
- 	uint32_t num_ps;
-+	struct pp_thermal_controller_info thermal_controller;
-+	struct phm_microcode_version_info microcode_version_info;
- 	uint32_t ps_size;
- 	struct pp_power_state    *current_ps;
- 	struct pp_power_state    *request_ps;
-@@ -487,7 +571,13 @@ extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
- extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
- 				uint32_t index, uint32_t value, uint32_t mask);
- 
-+extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr,
-+		uint32_t indirect_port, uint32_t index);
- 
-+extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr,
-+		uint32_t indirect_port,
-+		uint32_t index,
-+		uint32_t value);
- 
- extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- 				uint32_t indirect_port,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-index 65ef547..3df3ded 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-@@ -31,7 +31,7 @@
- #define PP_ASSERT_WITH_CODE(cond, msg, code)	\
- 	do {					\
- 		if (!(cond)) {			\
--			printk(msg);	\
-+			printk("%s\n", msg);	\
- 			code;			\
- 		}				\
- 	} while (0)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
-new file mode 100644
-index 0000000..c24a81e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
-@@ -0,0 +1,100 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU_UCODE_XFER_VI_H
-+#define SMU_UCODE_XFER_VI_H
-+
-+#define SMU_DRAMData_TOC_VERSION  1
-+#define MAX_IH_REGISTER_COUNT     65535
-+#define SMU_DIGEST_SIZE_BYTES     20
-+#define SMU_FB_SIZE_BYTES         1048576
-+#define SMU_MAX_ENTRIES           12
-+
-+#define UCODE_ID_SMU              0
-+#define UCODE_ID_SDMA0            1
-+#define UCODE_ID_SDMA1            2
-+#define UCODE_ID_CP_CE            3
-+#define UCODE_ID_CP_PFP           4
-+#define UCODE_ID_CP_ME            5
-+#define UCODE_ID_CP_MEC           6
-+#define UCODE_ID_CP_MEC_JT1       7
-+#define UCODE_ID_CP_MEC_JT2       8
-+#define UCODE_ID_GMCON_RENG       9
-+#define UCODE_ID_RLC_G            10
-+#define UCODE_ID_IH_REG_RESTORE   11
-+#define UCODE_ID_VBIOS            12
-+#define UCODE_ID_MISC_METADATA    13
-+#define UCODE_ID_RLC_SCRATCH      32
-+#define UCODE_ID_RLC_SRM_ARAM     33
-+#define UCODE_ID_RLC_SRM_DRAM     34
-+#define UCODE_ID_MEC_STORAGE      35
-+#define UCODE_ID_VBIOS_PARAMETERS 36
-+#define UCODE_META_DATA           0xFF
-+
-+#define UCODE_ID_SMU_MASK             0x00000001
-+#define UCODE_ID_SDMA0_MASK           0x00000002
-+#define UCODE_ID_SDMA1_MASK           0x00000004
-+#define UCODE_ID_CP_CE_MASK           0x00000008
-+#define UCODE_ID_CP_PFP_MASK          0x00000010
-+#define UCODE_ID_CP_ME_MASK           0x00000020
-+#define UCODE_ID_CP_MEC_MASK          0x00000040
-+#define UCODE_ID_CP_MEC_JT1_MASK      0x00000080
-+#define UCODE_ID_CP_MEC_JT2_MASK      0x00000100
-+#define UCODE_ID_GMCON_RENG_MASK      0x00000200
-+#define UCODE_ID_RLC_G_MASK           0x00000400
-+#define UCODE_ID_IH_REG_RESTORE_MASK  0x00000800
-+#define UCODE_ID_VBIOS_MASK           0x00001000
-+
-+#define UCODE_FLAG_UNHALT_MASK   0x1
-+
-+struct SMU_Entry {
-+#ifndef __BIG_ENDIAN
-+	uint16_t id;
-+	uint16_t version;
-+	uint32_t image_addr_high;
-+	uint32_t image_addr_low;
-+	uint32_t meta_data_addr_high;
-+	uint32_t meta_data_addr_low;
-+	uint32_t data_size_byte;
-+	uint16_t flags;
-+	uint16_t num_register_entries;
-+#else
-+	uint16_t version;
-+	uint16_t id;
-+	uint32_t image_addr_high;
-+	uint32_t image_addr_low;
-+	uint32_t meta_data_addr_high;
-+	uint32_t meta_data_addr_low;
-+	uint32_t data_size_byte;
-+	uint16_t num_register_entries;
-+	uint16_t flags;
-+#endif
-+};
-+
-+struct SMU_DRAMData_TOC {
-+	uint32_t structure_version;
-+	uint32_t num_entries;
-+	struct SMU_Entry entry[SMU_MAX_ENTRIES];
-+};
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0055-drm-amd-powerplay-add-update-headers-for-Fiji-SMU-an.patch b/common/recipes-kernel/linux/files/0055-drm-amd-powerplay-add-update-headers-for-Fiji-SMU-an.patch
deleted file mode 100644
index a18d4292..00000000
--- a/common/recipes-kernel/linux/files/0055-drm-amd-powerplay-add-update-headers-for-Fiji-SMU-an.patch
+++ /dev/null
@@ -1,13191 +0,0 @@
-From 5253c237c31f31c768e59d911540c2484ea0139d Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 9 Nov 2015 17:34:31 -0500
-Subject: [PATCH 0055/1110] drm/amd/powerplay: add/update headers for Fiji SMU
- and DPM
-
-New headers for Fiji.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/fiji_ppsmc.h            |   182 -
- drivers/gpu/drm/amd/include/atombios.h             |    79 +
- drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h    |   617 ++
- drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h     |   412 +
- drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h  | 10299 +++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/smu73.h          |   720 ++
- drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h |   799 ++
- 7 files changed, 12926 insertions(+), 182 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/fiji_ppsmc.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu73.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/fiji_ppsmc.h
-deleted file mode 100644
-index 3c48240..0000000
---- a/drivers/gpu/drm/amd/amdgpu/fiji_ppsmc.h
-+++ /dev/null
-@@ -1,182 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef FIJI_PP_SMC_H
--#define FIJI_PP_SMC_H
--
--#pragma pack(push, 1)
--
--#define PPSMC_SWSTATE_FLAG_DC                           0x01
--#define PPSMC_SWSTATE_FLAG_UVD                          0x02
--#define PPSMC_SWSTATE_FLAG_VCE                          0x04
--
--#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
--#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
--#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
--
--#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
--#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
--#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
--
--#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
--
--#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
--#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
--
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
--#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
--
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
--
--#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
--#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
--#define PPSMC_DPM2FLAGS_OCP                             0x04
--
--#define PPSMC_DISPLAY_WATERMARK_LOW                     0
--#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
--
--#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    		0x01
--#define PPSMC_STATEFLAG_POWERBOOST         		0x02
--#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 		0x04
--#define PPSMC_STATEFLAG_POWERSHIFT         		0x08
--#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   		0x10
--#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 		0x20
--#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   		0x40
--
--#define FDO_MODE_HARDWARE 0
--#define FDO_MODE_PIECE_WISE_LINEAR 1
--
--enum FAN_CONTROL {
--	FAN_CONTROL_FUZZY,
--	FAN_CONTROL_TABLE
--};
--
--//Gemini Modes
--#define PPSMC_GeminiModeNone   0  //Single GPU board
--#define PPSMC_GeminiModeMaster 1  //Master GPU on a Gemini board
--#define PPSMC_GeminiModeSlave  2  //Slave GPU on a Gemini board
--
--#define PPSMC_Result_OK             			((uint16_t)0x01)
--#define PPSMC_Result_NoMore         			((uint16_t)0x02)
--#define PPSMC_Result_NotNow         			((uint16_t)0x03)
--#define PPSMC_Result_Failed         			((uint16_t)0xFF)
--#define PPSMC_Result_UnknownCmd     			((uint16_t)0xFE)
--#define PPSMC_Result_UnknownVT      			((uint16_t)0xFD)
--
--typedef uint16_t PPSMC_Result;
--
--#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
--
--#define PPSMC_MSG_Halt                      		((uint16_t)0x10)
--#define PPSMC_MSG_Resume                    		((uint16_t)0x11)
--#define PPSMC_MSG_EnableDPMLevel            		((uint16_t)0x12)
--#define PPSMC_MSG_ZeroLevelsDisabled        		((uint16_t)0x13)
--#define PPSMC_MSG_OneLevelsDisabled         		((uint16_t)0x14)
--#define PPSMC_MSG_TwoLevelsDisabled         		((uint16_t)0x15)
--#define PPSMC_MSG_EnableThermalInterrupt    		((uint16_t)0x16)
--#define PPSMC_MSG_RunningOnAC               		((uint16_t)0x17)
--#define PPSMC_MSG_LevelUp                   		((uint16_t)0x18)
--#define PPSMC_MSG_LevelDown                 		((uint16_t)0x19)
--#define PPSMC_MSG_ResetDPMCounters          		((uint16_t)0x1a)
--#define PPSMC_MSG_SwitchToSwState           		((uint16_t)0x20)
--#define PPSMC_MSG_SwitchToSwStateLast       		((uint16_t)0x3f)
--#define PPSMC_MSG_SwitchToInitialState      		((uint16_t)0x40)
--#define PPSMC_MSG_NoForcedLevel             		((uint16_t)0x41)
--#define PPSMC_MSG_ForceHigh                 		((uint16_t)0x42)
--#define PPSMC_MSG_ForceMediumOrHigh         		((uint16_t)0x43)
--#define PPSMC_MSG_SwitchToMinimumPower      		((uint16_t)0x51)
--#define PPSMC_MSG_ResumeFromMinimumPower    		((uint16_t)0x52)
--#define PPSMC_MSG_EnableCac                 		((uint16_t)0x53)
--#define PPSMC_MSG_DisableCac                		((uint16_t)0x54)
--#define PPSMC_DPMStateHistoryStart          		((uint16_t)0x55)
--#define PPSMC_DPMStateHistoryStop           		((uint16_t)0x56)
--#define PPSMC_CACHistoryStart               		((uint16_t)0x57)
--#define PPSMC_CACHistoryStop                		((uint16_t)0x58)
--#define PPSMC_TDPClampingActive             		((uint16_t)0x59)
--#define PPSMC_TDPClampingInactive           		((uint16_t)0x5A)
--#define PPSMC_StartFanControl               		((uint16_t)0x5B)
--#define PPSMC_StopFanControl                		((uint16_t)0x5C)
--#define PPSMC_NoDisplay                     		((uint16_t)0x5D)
--#define PPSMC_HasDisplay                    		((uint16_t)0x5E)
--#define PPSMC_MSG_UVDPowerOFF               		((uint16_t)0x60)
--#define PPSMC_MSG_UVDPowerON                		((uint16_t)0x61)
--#define PPSMC_MSG_EnableULV                 		((uint16_t)0x62)
--#define PPSMC_MSG_DisableULV                		((uint16_t)0x63)
--#define PPSMC_MSG_EnterULV                  		((uint16_t)0x64)
--#define PPSMC_MSG_ExitULV                   		((uint16_t)0x65)
--#define PPSMC_PowerShiftActive              		((uint16_t)0x6A)
--#define PPSMC_PowerShiftInactive            		((uint16_t)0x6B)
--#define PPSMC_OCPActive                     		((uint16_t)0x6C)
--#define PPSMC_OCPInactive                   		((uint16_t)0x6D)
--#define PPSMC_CACLongTermAvgEnable          		((uint16_t)0x6E)
--#define PPSMC_CACLongTermAvgDisable         		((uint16_t)0x6F)
--#define PPSMC_MSG_InferredStateSweep_Start  		((uint16_t)0x70)
--#define PPSMC_MSG_InferredStateSweep_Stop   		((uint16_t)0x71)
--#define PPSMC_MSG_SwitchToLowestInfState    		((uint16_t)0x72)
--#define PPSMC_MSG_SwitchToNonInfState       		((uint16_t)0x73)
--#define PPSMC_MSG_AllStateSweep_Start       		((uint16_t)0x74)
--#define PPSMC_MSG_AllStateSweep_Stop        		((uint16_t)0x75)
--#define PPSMC_MSG_SwitchNextLowerInfState   		((uint16_t)0x76)
--#define PPSMC_MSG_SwitchNextHigherInfState  		((uint16_t)0x77)
--#define PPSMC_MSG_MclkRetrainingTest        		((uint16_t)0x78)
--#define PPSMC_MSG_ForceTDPClamping          		((uint16_t)0x79)
--#define PPSMC_MSG_CollectCAC_PowerCorreln   		((uint16_t)0x7A)
--#define PPSMC_MSG_CollectCAC_WeightCalib    		((uint16_t)0x7B)
--#define PPSMC_MSG_CollectCAC_SQonly         		((uint16_t)0x7C)
--#define PPSMC_MSG_CollectCAC_TemperaturePwr 		((uint16_t)0x7D)
--#define PPSMC_MSG_ExtremitiesTest_Start     		((uint16_t)0x7E)
--#define PPSMC_MSG_ExtremitiesTest_Stop      		((uint16_t)0x7F)
--#define PPSMC_FlushDataCache                		((uint16_t)0x80)
--#define PPSMC_FlushInstrCache               		((uint16_t)0x81)
--#define PPSMC_MSG_SetEnabledLevels          		((uint16_t)0x82)
--#define PPSMC_MSG_SetForcedLevels           		((uint16_t)0x83)
--#define PPSMC_MSG_ResetToDefaults           		((uint16_t)0x84)
--#define PPSMC_MSG_SetForcedLevelsAndJump    		((uint16_t)0x85)
--#define PPSMC_MSG_SetCACHistoryMode         		((uint16_t)0x86)
--#define PPSMC_MSG_EnableDTE                 		((uint16_t)0x87)
--#define PPSMC_MSG_DisableDTE                		((uint16_t)0x88)
--#define PPSMC_MSG_SmcSpaceSetAddress        		((uint16_t)0x89)
--#define PPSMC_MSG_SmcSpaceWriteDWordInc     		((uint16_t)0x8A)
--#define PPSMC_MSG_SmcSpaceWriteWordInc      		((uint16_t)0x8B)
--#define PPSMC_MSG_SmcSpaceWriteByteInc      		((uint16_t)0x8C)
--
--#define PPSMC_MSG_BREAK                     		((uint16_t)0xF8)
--
--#define PPSMC_MSG_Test                      		((uint16_t)0x100)
--#define PPSMC_MSG_DRV_DRAM_ADDR_HI            		((uint16_t)0x250)
--#define PPSMC_MSG_DRV_DRAM_ADDR_LO            		((uint16_t)0x251)
--#define PPSMC_MSG_SMU_DRAM_ADDR_HI            		((uint16_t)0x252)
--#define PPSMC_MSG_SMU_DRAM_ADDR_LO            		((uint16_t)0x253)
--#define PPSMC_MSG_LoadUcodes                  		((uint16_t)0x254)
--
--typedef uint16_t PPSMC_Msg;
--
--#define PPSMC_EVENT_STATUS_THERMAL          		0x00000001
--#define PPSMC_EVENT_STATUS_REGULATORHOT     		0x00000002
--#define PPSMC_EVENT_STATUS_DC               		0x00000004
--#define PPSMC_EVENT_STATUS_GPIO17           		0x00000008
--
--#pragma pack(pop)
--
--#endif
-diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
-index 5526226..eaf451e 100644
---- a/drivers/gpu/drm/amd/include/atombios.h
-+++ b/drivers/gpu/drm/amd/include/atombios.h
-@@ -550,6 +550,13 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
- //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
- #define MPLL_CNTL_FLAG_BYPASS_AD_PLL            0x04
- 
-+// use for ComputeMemoryClockParamTable
-+typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2
-+{
-+  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;
-+  ULONG ulReserved;
-+}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
-+
- typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
- {
-   ATOM_COMPUTE_CLOCK_FREQ ulClock;
-@@ -4988,6 +4995,78 @@ typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_3
-   ULONG  ulSDCMargine;
- }ATOM_ASIC_PROFILING_INFO_V3_3;
- 
-+// for Fiji speed EVV algorithm
-+typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_4
-+{
-+  ATOM_COMMON_TABLE_HEADER         asHeader;
-+  ULONG  ulEvvLkgFactor;
-+  ULONG  ulBoardCoreTemp;
-+  ULONG  ulMaxVddc;
-+  ULONG  ulMinVddc;
-+  ULONG  ulLoadLineSlop;
-+  ULONG  ulLeakageTemp;
-+  ULONG  ulLeakageVoltage;
-+  EFUSE_LINEAR_FUNC_PARAM sCACm;
-+  EFUSE_LINEAR_FUNC_PARAM sCACb;
-+  EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
-+  EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
-+  EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
-+  USHORT usLkgEuseIndex;
-+  UCHAR  ucLkgEfuseBitLSB;
-+  UCHAR  ucLkgEfuseLength;
-+  ULONG  ulLkgEncodeLn_MaxDivMin;
-+  ULONG  ulLkgEncodeMax;
-+  ULONG  ulLkgEncodeMin;
-+  ULONG  ulEfuseLogisticAlpha;
-+  USHORT usPowerDpm0;
-+  USHORT usPowerDpm1;
-+  USHORT usPowerDpm2;
-+  USHORT usPowerDpm3;
-+  USHORT usPowerDpm4;
-+  USHORT usPowerDpm5;
-+  USHORT usPowerDpm6;
-+  USHORT usPowerDpm7;
-+  ULONG  ulTdpDerateDPM0;
-+  ULONG  ulTdpDerateDPM1;
-+  ULONG  ulTdpDerateDPM2;
-+  ULONG  ulTdpDerateDPM3;
-+  ULONG  ulTdpDerateDPM4;
-+  ULONG  ulTdpDerateDPM5;
-+  ULONG  ulTdpDerateDPM6;
-+  ULONG  ulTdpDerateDPM7;
-+  EFUSE_LINEAR_FUNC_PARAM sRoFuse;
-+  ULONG  ulEvvDefaultVddc;
-+  ULONG  ulEvvNoCalcVddc;
-+  USHORT usParamNegFlag;
-+  USHORT usSpeed_Model;
-+  ULONG  ulSM_A0;
-+  ULONG  ulSM_A1;
-+  ULONG  ulSM_A2;
-+  ULONG  ulSM_A3;
-+  ULONG  ulSM_A4;
-+  ULONG  ulSM_A5;
-+  ULONG  ulSM_A6;
-+  ULONG  ulSM_A7;
-+  UCHAR  ucSM_A0_sign;
-+  UCHAR  ucSM_A1_sign;
-+  UCHAR  ucSM_A2_sign;
-+  UCHAR  ucSM_A3_sign;
-+  UCHAR  ucSM_A4_sign;
-+  UCHAR  ucSM_A5_sign;
-+  UCHAR  ucSM_A6_sign;
-+  UCHAR  ucSM_A7_sign;
-+  ULONG ulMargin_RO_a;
-+  ULONG ulMargin_RO_b;
-+  ULONG ulMargin_RO_c;
-+  ULONG ulMargin_fixed;
-+  ULONG ulMargin_Fmax_mean;
-+  ULONG ulMargin_plat_mean;
-+  ULONG ulMargin_Fmax_sigma;
-+  ULONG ulMargin_plat_sigma;
-+  ULONG ulMargin_DC_sigma;
-+  ULONG ulReserved[8];            // Reserved for future ASIC
-+}ATOM_ASIC_PROFILING_INFO_V3_4;
-+
- typedef struct _ATOM_POWER_SOURCE_OBJECT
- {
-    UCHAR  ucPwrSrcId;                                   // Power source
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-new file mode 100644
-index 0000000..42f2423
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-@@ -0,0 +1,617 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <asm/div64.h>
-+
-+#define SHIFT_AMOUNT 16 /* We multiply all original integers with 2^SHIFT_AMOUNT to get the fInt representation */
-+
-+#define PRECISION 5 /* Change this value to change the number of decimal places in the final output - 5 is a good default */
-+
-+#define SHIFTED_2 (2 << SHIFT_AMOUNT)
-+#define MAX (1 << (SHIFT_AMOUNT - 1)) - 1 /* 32767 - Might change in the future */
-+
-+/* -------------------------------------------------------------------------------
-+ * NEW TYPE - fINT
-+ * -------------------------------------------------------------------------------
-+ * A variable of type fInt can be accessed in 3 ways using the dot (.) operator
-+ * fInt A;
-+ * A.full => The full number as it is. Generally not easy to read
-+ * A.partial.real => Only the integer portion
-+ * A.partial.decimal => Only the fractional portion
-+ */
-+typedef union _fInt {
-+    int full;
-+    struct _partial {
-+        unsigned int decimal: SHIFT_AMOUNT; /*Needs to always be unsigned*/
-+        int real: 32 - SHIFT_AMOUNT;
-+    } partial;
-+} fInt;
-+
-+/* -------------------------------------------------------------------------------
-+ * Function Declarations
-+ *  -------------------------------------------------------------------------------
-+ */
-+fInt ConvertToFraction(int);                       /* Use this to convert an INT to a FINT */
-+fInt Convert_ULONG_ToFraction(uint32_t);              /* Use this to convert an uint32_t to a FINT */
-+fInt GetScaledFraction(int, int);                  /* Use this to convert an INT to a FINT after scaling it by a factor */
-+int ConvertBackToInteger(fInt);                    /* Convert a FINT back to an INT that is scaled by 1000 (i.e. last 3 digits are the decimal digits) */
-+
-+fInt fNegate(fInt);                                /* Returns -1 * input fInt value */
-+fInt fAdd (fInt, fInt);                            /* Returns the sum of two fInt numbers */
-+fInt fSubtract (fInt A, fInt B);                   /* Returns A-B - Sometimes easier than Adding negative numbers */
-+fInt fMultiply (fInt, fInt);                       /* Returns the product of two fInt numbers */
-+fInt fDivide (fInt A, fInt B);                     /* Returns A/B */
-+fInt fGetSquare(fInt);                             /* Returns the square of a fInt number */
-+fInt fSqrt(fInt);                                  /* Returns the Square Root of a fInt number */
-+
-+int uAbs(int);                                     /* Returns the Absolute value of the Int */
-+fInt fAbs(fInt);                                   /* Returns the Absolute value of the fInt */
-+int uPow(int base, int exponent);                  /* Returns base^exponent an INT */
-+
-+void SolveQuadracticEqn(fInt, fInt, fInt, fInt[]); /* Returns the 2 roots via the array */
-+bool Equal(fInt, fInt);                         /* Returns true if two fInts are equal to each other */
-+bool GreaterThan(fInt A, fInt B);               /* Returns true if A > B */
-+
-+fInt fExponential(fInt exponent);                  /* Can be used to calculate e^exponent */
-+fInt fNaturalLog(fInt value);                      /* Can be used to calculate ln(value) */
-+
-+/* Fuse decoding functions
-+ * -------------------------------------------------------------------------------------
-+ */
-+fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength);
-+fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength);
-+fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength);
-+
-+/* Internal Support Functions - Use these ONLY for testing or adding to internal functions
-+ * -------------------------------------------------------------------------------------
-+ * Some of the following functions take two INTs as their input - This is unsafe for a variety of reasons.
-+ */
-+fInt Add (int, int);                               /* Add two INTs and return Sum as FINT */
-+fInt Multiply (int, int);                          /* Multiply two INTs and return Product as FINT */
-+fInt Divide (int, int);                            /* You get the idea... */
-+fInt fNegate(fInt);
-+
-+int uGetScaledDecimal (fInt);                      /* Internal function */
-+int GetReal (fInt A);                              /* Internal function */
-+
-+/* Future Additions and Incomplete Functions
-+ * -------------------------------------------------------------------------------------
-+ */
-+int GetRoundedValue(fInt);                         /* Incomplete function - Useful only when Precision is lacking */
-+                                                   /* Let us say we have 2.126 but can only handle 2 decimal points. We could */
-+                                                   /* either chop of 6 and keep 2.12 or use this function to get 2.13, which is more accurate */
-+
-+/* -------------------------------------------------------------------------------------
-+ * TROUBLESHOOTING INFORMATION
-+ * -------------------------------------------------------------------------------------
-+ * 1) ConvertToFraction - InputOutOfRangeException: Only accepts numbers smaller than MAX (default: 32767)
-+ * 2) fAdd - OutputOutOfRangeException: Output bigger than MAX (default: 32767)
-+ * 3) fMultiply - OutputOutOfRangeException:
-+ * 4) fGetSquare - OutputOutOfRangeException:
-+ * 5) fDivide - DivideByZeroException
-+ * 6) fSqrt - NegativeSquareRootException: Input cannot be a negative number
-+ */
-+
-+/* -------------------------------------------------------------------------------------
-+ * START OF CODE
-+ * -------------------------------------------------------------------------------------
-+ */
-+fInt fExponential(fInt exponent)        /*Can be used to calculate e^exponent*/
-+{
-+    uint32_t i;
-+    bool bNegated = false;
-+
-+    fInt fPositiveOne = ConvertToFraction(1);
-+    fInt fZERO = ConvertToFraction(0);
-+
-+    fInt lower_bound = Divide(78, 10000);
-+    fInt solution = fPositiveOne; /*Starting off with baseline of 1 */
-+    fInt error_term;
-+
-+    uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
-+    uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
-+
-+    if (GreaterThan(fZERO, exponent)) {
-+        exponent = fNegate(exponent);
-+        bNegated = true;
-+    }
-+
-+    while (GreaterThan(exponent, lower_bound)) {
-+        for (i = 0; i < 11; i++) {
-+            if (GreaterThan(exponent, GetScaledFraction(k_array[i], 10000))) {
-+                exponent = fSubtract(exponent, GetScaledFraction(k_array[i], 10000));
-+                solution = fMultiply(solution, GetScaledFraction(expk_array[i], 10000));
-+            }
-+        }
-+    }
-+
-+    error_term = fAdd(fPositiveOne, exponent);
-+
-+    solution = fMultiply(solution, error_term);
-+
-+    if (bNegated)
-+        solution = fDivide(fPositiveOne, solution);
-+
-+    return solution;
-+}
-+
-+fInt fNaturalLog(fInt value)
-+{
-+    uint32_t i;
-+    fInt upper_bound = Divide(8, 1000);
-+    fInt fNegativeOne = ConvertToFraction(-1);
-+    fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */
-+    fInt error_term;
-+
-+    uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
-+    uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
-+
-+    while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) {
-+        for (i = 0; i < 10; i++) {
-+            if (GreaterThan(value, GetScaledFraction(k_array[i], 10000))) {
-+                value = fDivide(value, GetScaledFraction(k_array[i], 10000));
-+                solution = fAdd(solution, GetScaledFraction(logk_array[i], 10000));
-+            }
-+        }
-+    }
-+
-+    error_term = fAdd(fNegativeOne, value);
-+
-+    return (fAdd(solution, error_term));
-+}
-+
-+fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength)
-+{
-+    fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
-+    fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
-+
-+    fInt f_decoded_value;
-+
-+    f_decoded_value = fDivide(f_fuse_value, f_bit_max_value);
-+    f_decoded_value = fMultiply(f_decoded_value, f_range);
-+    f_decoded_value = fAdd(f_decoded_value, f_min);
-+
-+    return f_decoded_value;
-+}
-+
-+
-+fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength)
-+{
-+    fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
-+    fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
-+
-+    fInt f_CONSTANT_NEG13 = ConvertToFraction(-13);
-+    fInt f_CONSTANT1 = ConvertToFraction(1);
-+
-+    fInt f_decoded_value;
-+
-+    f_decoded_value = fSubtract(fDivide(f_bit_max_value, f_fuse_value), f_CONSTANT1);
-+    f_decoded_value = fNaturalLog(f_decoded_value);
-+    f_decoded_value = fMultiply(f_decoded_value, fDivide(f_range, f_CONSTANT_NEG13));
-+    f_decoded_value = fAdd(f_decoded_value, f_average);
-+
-+    return f_decoded_value;
-+}
-+
-+fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength)
-+{
-+    fInt fLeakage;
-+    fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
-+
-+    fLeakage = fMultiply(ln_max_div_min, Convert_ULONG_ToFraction(leakageID_fuse));
-+    fLeakage = fDivide(fLeakage, f_bit_max_value);
-+    fLeakage = fExponential(fLeakage);
-+    fLeakage = fMultiply(fLeakage, f_min);
-+
-+    return fLeakage;
-+}
-+
-+fInt ConvertToFraction(int X) /*Add all range checking here. Is it possible to make fInt a private declaration? */
-+{
-+    fInt temp;
-+
-+    if (X <= MAX)
-+        temp.full = (X << SHIFT_AMOUNT);
-+    else
-+        temp.full = 0;
-+
-+    return temp;
-+}
-+
-+fInt fNegate(fInt X)
-+{
-+    fInt CONSTANT_NEGONE = ConvertToFraction(-1);
-+    return (fMultiply(X, CONSTANT_NEGONE));
-+}
-+
-+fInt Convert_ULONG_ToFraction(uint32_t X)
-+{
-+    fInt temp;
-+
-+    if (X <= MAX)
-+        temp.full = (X << SHIFT_AMOUNT);
-+    else
-+        temp.full = 0;
-+
-+    return temp;
-+}
-+
-+fInt GetScaledFraction(int X, int factor)
-+{
-+    int times_shifted, factor_shifted;
-+    bool bNEGATED;
-+    fInt fValue;
-+
-+    times_shifted = 0;
-+    factor_shifted = 0;
-+    bNEGATED = false;
-+
-+    if (X < 0) {
-+        X = -1*X;
-+        bNEGATED = true;
-+    }
-+
-+    if (factor < 0) {
-+        factor = -1*factor;
-+
-+        bNEGATED = !bNEGATED; /*If bNEGATED = true due to X < 0, this will cover the case of negative cancelling negative */
-+    }
-+
-+    if ((X > MAX) || factor > MAX) {
-+        if ((X/factor) <= MAX) {
-+            while (X > MAX) {
-+                X = X >> 1;
-+                times_shifted++;
-+            }
-+
-+            while (factor > MAX) {
-+                factor = factor >> 1;
-+                factor_shifted++;
-+            }
-+        } else {
-+            fValue.full = 0;
-+            return fValue;
-+        }
-+    }
-+
-+    if (factor == 1)
-+        return (ConvertToFraction(X));
-+
-+    fValue = fDivide(ConvertToFraction(X * uPow(-1, bNEGATED)), ConvertToFraction(factor));
-+
-+    fValue.full = fValue.full << times_shifted;
-+    fValue.full = fValue.full >> factor_shifted;
-+
-+    return fValue;
-+}
-+
-+/* Addition using two fInts */
-+fInt fAdd (fInt X, fInt Y)
-+{
-+    fInt Sum;
-+
-+    Sum.full = X.full + Y.full;
-+
-+    return Sum;
-+}
-+
-+/* Addition using two fInts */
-+fInt fSubtract (fInt X, fInt Y)
-+{
-+    fInt Difference;
-+
-+    Difference.full = X.full - Y.full;
-+
-+    return Difference;
-+}
-+
-+bool Equal(fInt A, fInt B)
-+{
-+    if (A.full == B.full)
-+        return true;
-+    else
-+        return false;
-+}
-+
-+bool GreaterThan(fInt A, fInt B)
-+{
-+    if (A.full > B.full)
-+        return true;
-+    else
-+        return false;
-+}
-+
-+fInt fMultiply (fInt X, fInt Y) /* Uses 64-bit integers (int64_t) */
-+{
-+    fInt Product;
-+    int64_t tempProduct;
-+    bool X_LessThanOne, Y_LessThanOne;
-+
-+    X_LessThanOne = (X.partial.real == 0 && X.partial.decimal != 0 && X.full >= 0);
-+    Y_LessThanOne = (Y.partial.real == 0 && Y.partial.decimal != 0 && Y.full >= 0);
-+
-+    /*The following is for a very specific common case: Non-zero number with ONLY fractional portion*/
-+    /* TEMPORARILY DISABLED - CAN BE USED TO IMPROVE PRECISION
-+
-+    if (X_LessThanOne && Y_LessThanOne) {
-+        Product.full = X.full * Y.full;
-+        return Product
-+    }*/
-+
-+    tempProduct = ((int64_t)X.full) * ((int64_t)Y.full); /*Q(16,16)*Q(16,16) = Q(32, 32) - Might become a negative number! */
-+    tempProduct = tempProduct >> 16; /*Remove lagging 16 bits - Will lose some precision from decimal; */
-+    Product.full = (int)tempProduct; /*The int64_t will lose the leading 16 bits that were part of the integer portion */
-+
-+    return Product;
-+}
-+
-+fInt fDivide (fInt X, fInt Y)
-+{
-+    fInt fZERO, fQuotient;
-+    int64_t longlongX, longlongY;
-+
-+    fZERO = ConvertToFraction(0);
-+
-+    if (Equal(Y, fZERO))
-+        return fZERO;
-+
-+    longlongX = (int64_t)X.full;
-+    longlongY = (int64_t)Y.full;
-+
-+    longlongX = longlongX << 16; /*Q(16,16) -> Q(32,32) */
-+
-+    do_div(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */
-+
-+    fQuotient.full = (int)longlongX;
-+    return fQuotient;
-+}
-+
-+int ConvertBackToInteger (fInt A) /*THIS is the function that will be used to check with the Golden settings table*/
-+{
-+    fInt fullNumber, scaledDecimal, scaledReal;
-+
-+    scaledReal.full = GetReal(A) * uPow(10, PRECISION-1); /* DOUBLE CHECK THISSSS!!! */
-+
-+    scaledDecimal.full = uGetScaledDecimal(A);
-+
-+    fullNumber = fAdd(scaledDecimal,scaledReal);
-+
-+    return fullNumber.full;
-+}
-+
-+fInt fGetSquare(fInt A)
-+{
-+    return fMultiply(A,A);
-+}
-+
-+/* x_new = x_old - (x_old^2 - C) / (2 * x_old) */
-+fInt fSqrt(fInt num)
-+{
-+    fInt F_divide_Fprime, Fprime;
-+    fInt test;
-+    fInt twoShifted;
-+    int seed, counter, error;
-+    fInt x_new, x_old, C, y;
-+
-+    fInt fZERO = ConvertToFraction(0);
-+    /* (0 > num) is the same as (num < 0), i.e., num is negative */
-+    if (GreaterThan(fZERO, num) || Equal(fZERO, num))
-+        return fZERO;
-+
-+    C = num;
-+
-+    if (num.partial.real > 3000)
-+        seed = 60;
-+    else if (num.partial.real > 1000)
-+        seed = 30;
-+    else if (num.partial.real > 100)
-+        seed = 10;
-+    else
-+        seed = 2;
-+
-+    counter = 0;
-+
-+    if (Equal(num, fZERO)) /*Square Root of Zero is zero */
-+        return fZERO;
-+
-+    twoShifted = ConvertToFraction(2);
-+    x_new = ConvertToFraction(seed);
-+
-+    do {
-+        counter++;
-+
-+        x_old.full = x_new.full;
-+
-+        test = fGetSquare(x_old); /*1.75*1.75 is reverting back to 1 when shifted down */
-+        y = fSubtract(test, C); /*y = f(x) = x^2 - C; */
-+
-+        Fprime = fMultiply(twoShifted, x_old);
-+        F_divide_Fprime = fDivide(y, Fprime);
-+
-+        x_new = fSubtract(x_old, F_divide_Fprime);
-+
-+        error = ConvertBackToInteger(x_new) - ConvertBackToInteger(x_old);
-+
-+        if (counter > 20) /*20 is already way too many iterations. If we dont have an answer by then, we never will*/
-+            return x_new;
-+
-+    } while (uAbs(error) > 0);
-+
-+    return (x_new);
-+}
-+
-+void SolveQuadracticEqn(fInt A, fInt B, fInt C, fInt Roots[])
-+{
-+    fInt* pRoots = &Roots[0];
-+    fInt temp, root_first, root_second;
-+    fInt f_CONSTANT10, f_CONSTANT100;
-+
-+    f_CONSTANT100 = ConvertToFraction(100);
-+    f_CONSTANT10 = ConvertToFraction(10);
-+
-+    while(GreaterThan(A, f_CONSTANT100) || GreaterThan(B, f_CONSTANT100) || GreaterThan(C, f_CONSTANT100)) {
-+        A = fDivide(A, f_CONSTANT10);
-+        B = fDivide(B, f_CONSTANT10);
-+        C = fDivide(C, f_CONSTANT10);
-+    }
-+
-+    temp = fMultiply(ConvertToFraction(4), A); /* root = 4*A */
-+    temp = fMultiply(temp, C); /* root = 4*A*C */
-+    temp = fSubtract(fGetSquare(B), temp); /* root = b^2 - 4AC */
-+    temp = fSqrt(temp); /*root = Sqrt (b^2 - 4AC); */
-+
-+    root_first = fSubtract(fNegate(B), temp); /* b - Sqrt(b^2 - 4AC) */
-+    root_second = fAdd(fNegate(B), temp); /* b + Sqrt(b^2 - 4AC) */
-+
-+    root_first = fDivide(root_first, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
-+    root_first = fDivide(root_first, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */
-+
-+    root_second = fDivide(root_second, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
-+    root_second = fDivide(root_second, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */
-+
-+    *(pRoots + 0) = root_first;
-+    *(pRoots + 1) = root_second;
-+}
-+
-+/* -----------------------------------------------------------------------------
-+ * SUPPORT FUNCTIONS
-+ * -----------------------------------------------------------------------------
-+ */
-+
-+/* Addition using two normal ints - Temporary - Use only for testing purposes?. */
-+fInt Add (int X, int Y)
-+{
-+    fInt A, B, Sum;
-+
-+    A.full = (X << SHIFT_AMOUNT);
-+    B.full = (Y << SHIFT_AMOUNT);
-+
-+    Sum.full = A.full + B.full;
-+
-+    return Sum;
-+}
-+
-+/* Conversion Functions */
-+int GetReal (fInt A)
-+{
-+    return (A.full >> SHIFT_AMOUNT);
-+}
-+
-+/* Temporarily Disabled */
-+int GetRoundedValue(fInt A) /*For now, round the 3rd decimal place */
-+{
-+    /* ROUNDING TEMPORARLY DISABLED
-+    int temp = A.full;
-+
-+    int decimal_cutoff, decimal_mask = 0x000001FF;
-+
-+    decimal_cutoff = temp & decimal_mask;
-+
-+
-+    if (decimal_cutoff > 0x147) {
-+        temp += 673;
-+    }*/
-+
-+    return ConvertBackToInteger(A)/10000; /*Temporary - in case this was used somewhere else */
-+}
-+
-+fInt Multiply (int X, int Y)
-+{
-+    fInt A, B, Product;
-+
-+    A.full = X << SHIFT_AMOUNT;
-+    B.full = Y << SHIFT_AMOUNT;
-+
-+    Product = fMultiply(A, B);
-+
-+    return Product;
-+}
-+fInt Divide (int X, int Y)
-+{
-+    fInt A, B, Quotient;
-+
-+    A.full = X << SHIFT_AMOUNT;
-+    B.full = Y << SHIFT_AMOUNT;
-+
-+    Quotient = fDivide(A, B);
-+
-+    return Quotient;
-+}
-+
-+int uGetScaledDecimal (fInt A) /*Converts the fractional portion to whole integers - Costly function */
-+{
-+	int dec[PRECISION];
-+	int i, scaledDecimal = 0, tmp = A.partial.decimal;
-+
-+	for (i = 0; i < PRECISION; i++) {
-+        dec[i] = tmp / (1 << SHIFT_AMOUNT);
-+
-+        tmp = tmp - ((1 << SHIFT_AMOUNT)*dec[i]);
-+
-+        tmp *= 10;
-+
-+        scaledDecimal = scaledDecimal + dec[i]*uPow(10, PRECISION - 1 -i);
-+    }
-+
-+    return scaledDecimal;
-+}
-+
-+int uPow(int base, int power)
-+{
-+	if (power == 0)
-+		return 1;
-+	else
-+		return (base)*uPow(base, power - 1);
-+}
-+
-+fInt fAbs(fInt A)
-+{
-+	if (A.partial.real < 0)
-+		return (fMultiply(A, ConvertToFraction(-1)));
-+	else
-+		return A;
-+}
-+
-+int uAbs(int X)
-+{
-+	if (X < 0)
-+		return (X * -1);
-+	else
-+		return X;
-+}
-+
-+fInt fRoundUpByStepSize(fInt A, fInt fStepSize, bool error_term)
-+{
-+    fInt solution;
-+
-+    solution = fDivide(A, fStepSize);
-+    solution.partial.decimal = 0; /*All fractional digits changes to 0 */
-+
-+    if (error_term)
-+        solution.partial.real += 1; /*Error term of 1 added */
-+
-+    solution = fMultiply(solution, fStepSize);
-+    solution = fAdd(solution, fStepSize);
-+
-+    return solution;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h
-new file mode 100644
-index 0000000..7ae4945
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_ppsmc.h
-@@ -0,0 +1,412 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+
-+#ifndef _FIJI_PP_SMC_H_
-+#define _FIJI_PP_SMC_H_
-+
-+#pragma pack(push, 1)
-+
-+#define PPSMC_SWSTATE_FLAG_DC                           0x01
-+#define PPSMC_SWSTATE_FLAG_UVD                          0x02
-+#define PPSMC_SWSTATE_FLAG_VCE                          0x04
-+
-+#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
-+#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
-+#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
-+
-+#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
-+#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
-+#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
-+
-+#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
-+
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
-+#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
-+
-+/* Defines for DPM 2.0 */
-+#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
-+#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
-+#define PPSMC_DPM2FLAGS_OCP                             0x04
-+
-+/* Defines for display watermark level */
-+#define PPSMC_DISPLAY_WATERMARK_LOW                     0
-+#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
-+
-+/* In the HW performance level's state flags: */
-+#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
-+#define PPSMC_STATEFLAG_POWERBOOST         0x02
-+#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
-+#define PPSMC_STATEFLAG_POWERSHIFT         0x08
-+#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
-+#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
-+#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
-+
-+/* Fan control algorithm: */
-+#define FDO_MODE_HARDWARE 0
-+#define FDO_MODE_PIECE_WISE_LINEAR 1
-+
-+enum FAN_CONTROL {
-+  FAN_CONTROL_FUZZY,
-+  FAN_CONTROL_TABLE
-+};
-+
-+/* Gemini Modes*/
-+#define PPSMC_GeminiModeNone   0  /*Single GPU board*/
-+#define PPSMC_GeminiModeMaster 1  /*Master GPU on a Gemini board*/
-+#define PPSMC_GeminiModeSlave  2  /*Slave GPU on a Gemini board*/
-+
-+
-+/* Return codes for driver to SMC communication. */
-+#define PPSMC_Result_OK             ((uint16_t)0x01)
-+#define PPSMC_Result_NoMore         ((uint16_t)0x02)
-+
-+#define PPSMC_Result_NotNow         ((uint16_t)0x03)
-+
-+#define PPSMC_Result_Failed         ((uint16_t)0xFF)
-+#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
-+#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
-+
-+#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
-+
-+
-+#define PPSMC_MSG_Halt                      ((uint16_t)0x10)
-+#define PPSMC_MSG_Resume                    ((uint16_t)0x11)
-+#define PPSMC_MSG_EnableDPMLevel            ((uint16_t)0x12)
-+#define PPSMC_MSG_ZeroLevelsDisabled        ((uint16_t)0x13)
-+#define PPSMC_MSG_OneLevelsDisabled         ((uint16_t)0x14)
-+#define PPSMC_MSG_TwoLevelsDisabled         ((uint16_t)0x15)
-+#define PPSMC_MSG_EnableThermalInterrupt    ((uint16_t)0x16)
-+#define PPSMC_MSG_RunningOnAC               ((uint16_t)0x17)
-+#define PPSMC_MSG_LevelUp                   ((uint16_t)0x18)
-+#define PPSMC_MSG_LevelDown                 ((uint16_t)0x19)
-+#define PPSMC_MSG_ResetDPMCounters          ((uint16_t)0x1a)
-+#define PPSMC_MSG_SwitchToSwState           ((uint16_t)0x20)
-+
-+#define PPSMC_MSG_SwitchToSwStateLast       ((uint16_t)0x3f)
-+#define PPSMC_MSG_SwitchToInitialState      ((uint16_t)0x40)
-+#define PPSMC_MSG_NoForcedLevel             ((uint16_t)0x41)
-+#define PPSMC_MSG_ForceHigh                 ((uint16_t)0x42)
-+#define PPSMC_MSG_ForceMediumOrHigh         ((uint16_t)0x43)
-+
-+#define PPSMC_MSG_SwitchToMinimumPower      ((uint16_t)0x51)
-+#define PPSMC_MSG_ResumeFromMinimumPower    ((uint16_t)0x52)
-+#define PPSMC_MSG_EnableCac                 ((uint16_t)0x53)
-+#define PPSMC_MSG_DisableCac                ((uint16_t)0x54)
-+#define PPSMC_DPMStateHistoryStart          ((uint16_t)0x55)
-+#define PPSMC_DPMStateHistoryStop           ((uint16_t)0x56)
-+#define PPSMC_CACHistoryStart               ((uint16_t)0x57)
-+#define PPSMC_CACHistoryStop                ((uint16_t)0x58)
-+#define PPSMC_TDPClampingActive             ((uint16_t)0x59)
-+#define PPSMC_TDPClampingInactive           ((uint16_t)0x5A)
-+#define PPSMC_StartFanControl               ((uint16_t)0x5B)
-+#define PPSMC_StopFanControl                ((uint16_t)0x5C)
-+#define PPSMC_NoDisplay                     ((uint16_t)0x5D)
-+#define PPSMC_HasDisplay                    ((uint16_t)0x5E)
-+#define PPSMC_MSG_UVDPowerOFF               ((uint16_t)0x60)
-+#define PPSMC_MSG_UVDPowerON                ((uint16_t)0x61)
-+#define PPSMC_MSG_EnableULV                 ((uint16_t)0x62)
-+#define PPSMC_MSG_DisableULV                ((uint16_t)0x63)
-+#define PPSMC_MSG_EnterULV                  ((uint16_t)0x64)
-+#define PPSMC_MSG_ExitULV                   ((uint16_t)0x65)
-+#define PPSMC_PowerShiftActive              ((uint16_t)0x6A)
-+#define PPSMC_PowerShiftInactive            ((uint16_t)0x6B)
-+#define PPSMC_OCPActive                     ((uint16_t)0x6C)
-+#define PPSMC_OCPInactive                   ((uint16_t)0x6D)
-+#define PPSMC_CACLongTermAvgEnable          ((uint16_t)0x6E)
-+#define PPSMC_CACLongTermAvgDisable         ((uint16_t)0x6F)
-+#define PPSMC_MSG_InferredStateSweep_Start  ((uint16_t)0x70)
-+#define PPSMC_MSG_InferredStateSweep_Stop   ((uint16_t)0x71)
-+#define PPSMC_MSG_SwitchToLowestInfState    ((uint16_t)0x72)
-+#define PPSMC_MSG_SwitchToNonInfState       ((uint16_t)0x73)
-+#define PPSMC_MSG_AllStateSweep_Start       ((uint16_t)0x74)
-+#define PPSMC_MSG_AllStateSweep_Stop        ((uint16_t)0x75)
-+#define PPSMC_MSG_SwitchNextLowerInfState   ((uint16_t)0x76)
-+#define PPSMC_MSG_SwitchNextHigherInfState  ((uint16_t)0x77)
-+#define PPSMC_MSG_MclkRetrainingTest        ((uint16_t)0x78)
-+#define PPSMC_MSG_ForceTDPClamping          ((uint16_t)0x79)
-+#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint16_t)0x7A)
-+#define PPSMC_MSG_CollectCAC_WeightCalib    ((uint16_t)0x7B)
-+#define PPSMC_MSG_CollectCAC_SQonly         ((uint16_t)0x7C)
-+#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
-+
-+#define PPSMC_MSG_ExtremitiesTest_Start     ((uint16_t)0x7E)
-+#define PPSMC_MSG_ExtremitiesTest_Stop      ((uint16_t)0x7F)
-+#define PPSMC_FlushDataCache                ((uint16_t)0x80)
-+#define PPSMC_FlushInstrCache               ((uint16_t)0x81)
-+
-+#define PPSMC_MSG_SetEnabledLevels          ((uint16_t)0x82)
-+#define PPSMC_MSG_SetForcedLevels           ((uint16_t)0x83)
-+
-+#define PPSMC_MSG_ResetToDefaults           ((uint16_t)0x84)
-+
-+#define PPSMC_MSG_SetForcedLevelsAndJump      ((uint16_t)0x85)
-+#define PPSMC_MSG_SetCACHistoryMode           ((uint16_t)0x86)
-+#define PPSMC_MSG_EnableDTE                   ((uint16_t)0x87)
-+#define PPSMC_MSG_DisableDTE                  ((uint16_t)0x88)
-+
-+#define PPSMC_MSG_SmcSpaceSetAddress          ((uint16_t)0x89)
-+
-+#define PPSMC_MSG_BREAK                       ((uint16_t)0xF8)
-+
-+/* Trinity Specific Messages*/
-+#define PPSMC_MSG_Test                        ((uint16_t) 0x100)
-+#define PPSMC_MSG_DPM_Voltage_Pwrmgt          ((uint16_t) 0x101)
-+#define PPSMC_MSG_DPM_Config                  ((uint16_t) 0x102)
-+#define PPSMC_MSG_PM_Controller_Start         ((uint16_t) 0x103)
-+#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
-+#define PPSMC_MSG_PG_PowerDownSIMD            ((uint16_t) 0x105)
-+#define PPSMC_MSG_PG_PowerUpSIMD              ((uint16_t) 0x106)
-+#define PPSMC_MSG_PM_Controller_Stop          ((uint16_t) 0x107)
-+#define PPSMC_MSG_PG_SIMD_Config              ((uint16_t) 0x108)
-+#define PPSMC_MSG_Voltage_Cntl_Enable         ((uint16_t) 0x109)
-+#define PPSMC_MSG_Thermal_Cntl_Enable         ((uint16_t) 0x10a)
-+#define PPSMC_MSG_Reset_Service               ((uint16_t) 0x10b)
-+#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x10e)
-+#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0x10f)
-+#define PPSMC_MSG_DPM_Disable_VCE_HS          ((uint16_t) 0x110)
-+#define PPSMC_MSG_DPM_Enable_VCE_HS           ((uint16_t) 0x111)
-+#define PPSMC_MSG_DPM_N_LevelsDisabled        ((uint16_t) 0x112)
-+#define PPSMC_MSG_DCEPowerOFF                 ((uint16_t) 0x113)
-+#define PPSMC_MSG_DCEPowerON                  ((uint16_t) 0x114)
-+#define PPSMC_MSG_PCIE_DDIPowerDown           ((uint16_t) 0x117)
-+#define PPSMC_MSG_PCIE_DDIPowerUp             ((uint16_t) 0x118)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerDown    ((uint16_t) 0x119)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerUp      ((uint16_t) 0x11a)
-+#define PPSMC_MSG_SYSPLLPowerOff              ((uint16_t) 0x11b)
-+#define PPSMC_MSG_SYSPLLPowerOn               ((uint16_t) 0x11c)
-+#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
-+#define PPSMC_MSG_DCE_AllowVoltageAdjustment  ((uint16_t) 0x11e)
-+#define PPSMC_MSG_DISPLAYPHYStatusNotify      ((uint16_t) 0x11f)
-+#define PPSMC_MSG_EnableBAPM                  ((uint16_t) 0x120)
-+#define PPSMC_MSG_DisableBAPM                 ((uint16_t) 0x121)
-+#define PPSMC_MSG_Spmi_Enable                 ((uint16_t) 0x122)
-+#define PPSMC_MSG_Spmi_Timer                  ((uint16_t) 0x123)
-+#define PPSMC_MSG_LCLK_DPM_Config             ((uint16_t) 0x124)
-+#define PPSMC_MSG_VddNB_Request               ((uint16_t) 0x125)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerDown        ((uint32_t) 0x126)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerUp          ((uint32_t) 0x127)
-+#define PPSMC_MSG_MCLKDPM_Config              ((uint16_t) 0x128)
-+
-+#define PPSMC_MSG_UVDDPM_Config               ((uint16_t) 0x129)
-+#define PPSMC_MSG_VCEDPM_Config               ((uint16_t) 0x12A)
-+#define PPSMC_MSG_ACPDPM_Config               ((uint16_t) 0x12B)
-+#define PPSMC_MSG_SAMUDPM_Config              ((uint16_t) 0x12C)
-+#define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
-+#define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
-+#define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
-+#define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
-+#define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
-+#define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
-+#define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
-+#define PPSMC_MSG_SetTDPLimit                 ((uint16_t) 0x134)
-+#define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
-+#define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
-+#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
-+#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
-+#define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
-+#define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
-+#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0x13b)
-+#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0x13c)
-+#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
-+#define PPSMC_MSG_IOMMUPowerOFF               ((uint16_t) 0x13e)
-+#define PPSMC_MSG_IOMMUPowerON                ((uint16_t) 0x13f)
-+#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
-+#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
-+#define PPSMC_MSG_NBDPM_ForceNominal          ((uint16_t) 0x142)
-+#define PPSMC_MSG_NBDPM_ForcePerformance      ((uint16_t) 0x143)
-+#define PPSMC_MSG_NBDPM_UnForce               ((uint16_t) 0x144)
-+#define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
-+#define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
-+#define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
-+#define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
-+#define PPSMC_MSG_EnableACDCGPIOInterrupt     ((uint16_t) 0x149)
-+#define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
-+#define PPSMC_MSG_SwitchToAC                  ((uint16_t) 0x14b)
-+
-+#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0x14c)
-+#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x14d)
-+
-+#define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
-+#define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
-+#define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
-+#define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
-+#define PPSMC_MSG_LCLKDPM_Enable              ((uint16_t) 0x152)
-+#define PPSMC_MSG_LCLKDPM_Disable             ((uint16_t) 0x153)
-+#define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
-+#define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
-+#define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
-+#define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
-+#define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
-+#define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
-+#define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
-+#define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
-+#define PPSMC_MSG_LCLKDPM_SetEnabledMask      ((uint16_t) 0x15c)
-+#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
-+#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
-+#define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
-+#define PPSMC_MSG_MCLKDPM_GetEnabledMask      ((uint16_t) 0x160)
-+#define PPSMC_MSG_LCLKDPM_GetEnabledMask      ((uint16_t) 0x161)
-+#define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
-+#define PPSMC_MSG_UVDDPM_GetEnabledMask       ((uint16_t) 0x163)
-+#define PPSMC_MSG_SAMUDPM_GetEnabledMask      ((uint16_t) 0x164)
-+#define PPSMC_MSG_ACPDPM_GetEnabledMask       ((uint16_t) 0x165)
-+#define PPSMC_MSG_VCEDPM_GetEnabledMask       ((uint16_t) 0x166)
-+#define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
-+#define PPSMC_MSG_PCIeDPM_GetEnabledMask      ((uint16_t) 0x168)
-+#define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
-+#define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
-+#define PPSMC_MSG_DPM_AutoRotate_Mode         ((uint16_t) 0x16b)
-+#define PPSMC_MSG_DISPCLK_FROM_FCH            ((uint16_t) 0x16c)
-+#define PPSMC_MSG_DISPCLK_FROM_DFS            ((uint16_t) 0x16d)
-+#define PPSMC_MSG_DPREFCLK_FROM_FCH           ((uint16_t) 0x16e)
-+#define PPSMC_MSG_DPREFCLK_FROM_DFS           ((uint16_t) 0x16f)
-+#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
-+#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
-+#define PPSMC_MSG_SCLK_AutoDPM_ON             ((uint16_t) 0x172)
-+#define PPSMC_MSG_MCLK_AutoDPM_ON             ((uint16_t) 0x173)
-+#define PPSMC_MSG_LCLK_AutoDPM_ON             ((uint16_t) 0x174)
-+#define PPSMC_MSG_UVD_AutoDPM_ON              ((uint16_t) 0x175)
-+#define PPSMC_MSG_SAMU_AutoDPM_ON             ((uint16_t) 0x176)
-+#define PPSMC_MSG_ACP_AutoDPM_ON              ((uint16_t) 0x177)
-+#define PPSMC_MSG_VCE_AutoDPM_ON              ((uint16_t) 0x178)
-+#define PPSMC_MSG_PCIe_AutoDPM_ON             ((uint16_t) 0x179)
-+#define PPSMC_MSG_MASTER_AutoDPM_ON           ((uint16_t) 0x17a)
-+#define PPSMC_MSG_MASTER_AutoDPM_OFF          ((uint16_t) 0x17b)
-+#define PPSMC_MSG_DYNAMICDISPPHYPOWER         ((uint16_t) 0x17c)
-+#define PPSMC_MSG_CAC_COLLECTION_ON           ((uint16_t) 0x17d)
-+#define PPSMC_MSG_CAC_COLLECTION_OFF          ((uint16_t) 0x17e)
-+#define PPSMC_MSG_CAC_CORRELATION_ON          ((uint16_t) 0x17f)
-+#define PPSMC_MSG_CAC_CORRELATION_OFF         ((uint16_t) 0x180)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON        ((uint16_t) 0x181)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF       ((uint16_t) 0x182)
-+#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT     ((uint16_t) 0x184)
-+#define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
-+#define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
-+#define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
-+#define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
-+#define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
-+#define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
-+#define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
-+#define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
-+#define PPSMC_MSG_START_DRAM_LOGGING          ((uint16_t) 0x18D)
-+#define PPSMC_MSG_STOP_DRAM_LOGGING           ((uint16_t) 0x18E)
-+#define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
-+#define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
-+#define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
-+#define PPSMC_MSG_DisableACDCGPIOInterrupt    ((uint16_t) 0x192)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddc       ((uint16_t) 0x193)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddci      ((uint16_t) 0x194)
-+#define PPSMC_MSG_SetVidOffset_1              ((uint16_t) 0x195)
-+#define PPSMC_MSG_SetVidOffset_2              ((uint16_t) 0x207)
-+#define PPSMC_MSG_GetVidOffset_1              ((uint16_t) 0x196)
-+#define PPSMC_MSG_GetVidOffset_2              ((uint16_t) 0x208)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable    ((uint16_t) 0x197)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable   ((uint16_t) 0x198)
-+#define PPSMC_MSG_SetTjMax                    ((uint16_t) 0x199)
-+#define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
-+#define PPSMC_MSG_WaitForMclkSwitchFinish     ((uint16_t) 0x19B)
-+#define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
-+#define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
-+
-+#define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
-+#define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
-+#define PPSMC_MSG_API_GetSclkBusy             ((uint16_t) 0x202)
-+#define PPSMC_MSG_API_GetMclkBusy             ((uint16_t) 0x203)
-+#define PPSMC_MSG_API_GetAsicPower            ((uint16_t) 0x204)
-+#define PPSMC_MSG_SetFanRpmMax                ((uint16_t) 0x205)
-+#define PPSMC_MSG_SetFanSclkTarget            ((uint16_t) 0x206)
-+#define PPSMC_MSG_SetFanMinPwm                ((uint16_t) 0x209)
-+#define PPSMC_MSG_SetFanTemperatureTarget     ((uint16_t) 0x20A)
-+
-+#define PPSMC_MSG_BACO_StartMonitor           ((uint16_t) 0x240)
-+#define PPSMC_MSG_BACO_Cancel                 ((uint16_t) 0x241)
-+#define PPSMC_MSG_EnableVddGfx                ((uint16_t) 0x242)
-+#define PPSMC_MSG_DisableVddGfx               ((uint16_t) 0x243)
-+#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x244)
-+#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x245)
-+#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x246)
-+
-+#define PPSMC_MSG_DRV_DRAM_ADDR_HI            ((uint16_t) 0x250)
-+#define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
-+#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
-+#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x255)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI      ((uint16_t) 0x256)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO      ((uint16_t) 0x257)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI          ((uint16_t) 0x258)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO          ((uint16_t) 0x259)
-+#define PPSMC_MSG_LoadVBios                   ((uint16_t) 0x25A)
-+#define PPSMC_MSG_GetUcodeVersion             ((uint16_t) 0x25B)
-+#define DMCUSMC_MSG_PSREntry                  ((uint16_t) 0x25C)
-+#define DMCUSMC_MSG_PSRExit                   ((uint16_t) 0x25D)
-+#define PPSMC_MSG_EnableClockGatingFeature    ((uint16_t) 0x260)
-+#define PPSMC_MSG_DisableClockGatingFeature   ((uint16_t) 0x261)
-+#define PPSMC_MSG_IsDeviceRunning             ((uint16_t) 0x262)
-+#define PPSMC_MSG_LoadMetaData                ((uint16_t) 0x263)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Enable  ((uint16_t) 0x264)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
-+#define PPSMC_MSG_GetTelemetry1Slope          ((uint16_t) 0x266)
-+#define PPSMC_MSG_GetTelemetry1Offset         ((uint16_t) 0x267)
-+#define PPSMC_MSG_GetTelemetry2Slope          ((uint16_t) 0x268)
-+#define PPSMC_MSG_GetTelemetry2Offset         ((uint16_t) 0x269)
-+#define PPSMC_MSG_EnableAvfs                  ((uint16_t) 0x26A)
-+#define PPSMC_MSG_DisableAvfs                 ((uint16_t) 0x26B)
-+#define PPSMC_MSG_PerformBtc                  ((uint16_t) 0x26C)
-+#define PPSMC_MSG_GetHbmCode                  ((uint16_t) 0x26D)
-+#define PPSMC_MSG_GetVrVddcTemperature        ((uint16_t) 0x26E)
-+#define PPSMC_MSG_GetVrMvddTemperature        ((uint16_t) 0x26F)
-+#define PPSMC_MSG_GetLiquidTemperature        ((uint16_t) 0x270)
-+#define PPSMC_MSG_GetPlxTemperature           ((uint16_t) 0x271)
-+#define PPSMC_MSG_RequestI2CControl           ((uint16_t) 0x272)
-+#define PPSMC_MSG_ReleaseI2CControl           ((uint16_t) 0x273)
-+#define PPSMC_MSG_LedConfig                   ((uint16_t) 0x274)
-+#define PPSMC_MSG_SetHbmFanCode               ((uint16_t) 0x275)
-+#define PPSMC_MSG_SetHbmThrottleCode          ((uint16_t) 0x276)
-+
-+#define PPSMC_MSG_GetEnabledPsm               ((uint16_t) 0x400)
-+#define PPSMC_MSG_AgmStartPsm                 ((uint16_t) 0x401)
-+#define PPSMC_MSG_AgmReadPsm                  ((uint16_t) 0x402)
-+#define PPSMC_MSG_AgmResetPsm                 ((uint16_t) 0x403)
-+#define PPSMC_MSG_ReadVftCell                 ((uint16_t) 0x404)
-+
-+/* AVFS Only - Remove Later */
-+#define PPSMC_MSG_VftTableIsValid             ((uint16_t) 0x666)
-+
-+/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
-+#define PPSMC_EVENT_STATUS_THERMAL          0x00000001
-+#define PPSMC_EVENT_STATUS_REGULATORHOT     0x00000002
-+#define PPSMC_EVENT_STATUS_DC               0x00000004
-+
-+typedef uint16_t PPSMC_Msg;
-+
-+#pragma pack(pop)
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
-new file mode 100644
-index 0000000..0262ad3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
-@@ -0,0 +1,10299 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _FIJI_PWRVIRUS_H_
-+#define _FIJI_PWRVIRUS_H_
-+
-+#define mmCP_HYP_MEC1_UCODE_ADDR	0xf81a
-+#define mmCP_HYP_MEC1_UCODE_DATA	0xf81b
-+#define mmCP_HYP_MEC2_UCODE_ADDR	0xf81c
-+#define mmCP_HYP_MEC2_UCODE_DATA	0xf81d
-+
-+enum PWR_Command
-+{
-+   PwrCmdNull = 0,
-+   PwrCmdWrite,
-+   PwrCmdEnd,
-+   PwrCmdMax
-+};
-+typedef enum PWR_Command PWR_Command;
-+
-+struct PWR_Command_Table
-+{
-+   PWR_Command        command;
-+   ULONG              data;
-+   ULONG              reg;
-+};
-+typedef struct PWR_Command_Table PWR_Command_Table;
-+
-+#define PWR_VIRUS_TABLE_SIZE  10243
-+static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
-+{
-+    { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX                               },
-+    { PwrCmdWrite, 0x00000000, mmPCIE_DATA                                },
-+    { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX                               },
-+    { PwrCmdWrite, 0x0300078c, mmPCIE_DATA                                },
-+    { PwrCmdWrite, 0x00000000, mmBIF_CLK_CTRL                             },
-+    { PwrCmdWrite, 0x00000001, mmBIF_CLK_CTRL                             },
-+    { PwrCmdWrite, 0x00000000, mmBIF_CLK_CTRL                             },
-+    { PwrCmdWrite, 0x00000003, mmBIF_FB_EN                                },
-+    { PwrCmdWrite, 0x00000000, mmBIF_FB_EN                                },
-+    { PwrCmdWrite, 0x00000001, mmBIF_DOORBELL_APER_EN                     },
-+    { PwrCmdWrite, 0x00000000, mmBIF_DOORBELL_APER_EN                     },
-+    { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX                               },
-+    { PwrCmdWrite, 0x00000000, mmPCIE_DATA                                },
-+    { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX                               },
-+    { PwrCmdWrite, 0x22000000, mmPCIE_DATA                                },
-+    { PwrCmdWrite, 0x014000c0, mmPCIE_INDEX                               },
-+    { PwrCmdWrite, 0x00000000, mmPCIE_DATA                                },
-+    /*
-+    { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION                        },
-+    { PwrCmdWrite, 0x00000000, mmMC_CITF_CNTL                             },
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION                        },
-+    { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION                        },
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION                        },
-+    { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION                        },
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_FB_OFFSET                          },*/
-+    { PwrCmdWrite, 0x00000000, mmRLC_CSIB_ADDR_LO                         },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CSIB_ADDR_HI                         },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CSIB_LENGTH                          },
-+    /*
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_MX_L1_TLB_CNTL                     },
-+    { PwrCmdWrite, 0x00000001, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR           },
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR          },
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_FB_LOCATION                        },
-+    { PwrCmdWrite, 0x009f0090, mmMC_VM_FB_LOCATION                        },*/
-+    { PwrCmdWrite, 0x00000000, mmVM_CONTEXT0_CNTL                         },
-+    { PwrCmdWrite, 0x00000000, mmVM_CONTEXT1_CNTL                         },
-+    /*
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_AGP_BASE                           },
-+    { PwrCmdWrite, 0x00000002, mmMC_VM_AGP_BOT                            },
-+    { PwrCmdWrite, 0x00000000, mmMC_VM_AGP_TOP                            },*/
-+    { PwrCmdWrite, 0x04000000, mmATC_VM_APERTURE0_LOW_ADDR                },
-+    { PwrCmdWrite, 0x0400ff20, mmATC_VM_APERTURE0_HIGH_ADDR               },
-+    { PwrCmdWrite, 0x00000002, mmATC_VM_APERTURE0_CNTL                    },
-+    { PwrCmdWrite, 0x0000ffff, mmATC_VM_APERTURE0_CNTL2                   },
-+    { PwrCmdWrite, 0x00000001, mmATC_VM_APERTURE1_LOW_ADDR                },
-+    { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_HIGH_ADDR               },
-+    { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_CNTL                    },
-+    { PwrCmdWrite, 0x00000000, mmATC_VM_APERTURE1_CNTL2                   },
-+    //{ PwrCmdWrite, 0x00000000, mmMC_ARB_RAMCFG                            },
-+    { PwrCmdWrite, 0x12011003, mmGB_ADDR_CONFIG                           },
-+    { PwrCmdWrite, 0x00800010, mmGB_TILE_MODE0                            },
-+    { PwrCmdWrite, 0x00800810, mmGB_TILE_MODE1                            },
-+    { PwrCmdWrite, 0x00801010, mmGB_TILE_MODE2                            },
-+    { PwrCmdWrite, 0x00801810, mmGB_TILE_MODE3                            },
-+    { PwrCmdWrite, 0x00802810, mmGB_TILE_MODE4                            },
-+    { PwrCmdWrite, 0x00802808, mmGB_TILE_MODE5                            },
-+    { PwrCmdWrite, 0x00802814, mmGB_TILE_MODE6                            },
-+    { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE7                            },
-+    { PwrCmdWrite, 0x00000004, mmGB_TILE_MODE8                            },
-+    { PwrCmdWrite, 0x02000008, mmGB_TILE_MODE9                            },
-+    { PwrCmdWrite, 0x02000010, mmGB_TILE_MODE10                           },
-+    { PwrCmdWrite, 0x06000014, mmGB_TILE_MODE11                           },
-+    { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE12                           },
-+    { PwrCmdWrite, 0x02400008, mmGB_TILE_MODE13                           },
-+    { PwrCmdWrite, 0x02400010, mmGB_TILE_MODE14                           },
-+    { PwrCmdWrite, 0x02400030, mmGB_TILE_MODE15                           },
-+    { PwrCmdWrite, 0x06400014, mmGB_TILE_MODE16                           },
-+    { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE17                           },
-+    { PwrCmdWrite, 0x0040000c, mmGB_TILE_MODE18                           },
-+    { PwrCmdWrite, 0x0100000c, mmGB_TILE_MODE19                           },
-+    { PwrCmdWrite, 0x0100001c, mmGB_TILE_MODE20                           },
-+    { PwrCmdWrite, 0x01000034, mmGB_TILE_MODE21                           },
-+    { PwrCmdWrite, 0x01000024, mmGB_TILE_MODE22                           },
-+    { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE23                           },
-+    { PwrCmdWrite, 0x0040001c, mmGB_TILE_MODE24                           },
-+    { PwrCmdWrite, 0x01000020, mmGB_TILE_MODE25                           },
-+    { PwrCmdWrite, 0x01000038, mmGB_TILE_MODE26                           },
-+    { PwrCmdWrite, 0x02c00008, mmGB_TILE_MODE27                           },
-+    { PwrCmdWrite, 0x02c00010, mmGB_TILE_MODE28                           },
-+    { PwrCmdWrite, 0x06c00014, mmGB_TILE_MODE29                           },
-+    { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE30                           },
-+    { PwrCmdWrite, 0x00000000, mmGB_TILE_MODE31                           },
-+    { PwrCmdWrite, 0x000000a8, mmGB_MACROTILE_MODE0                       },
-+    { PwrCmdWrite, 0x000000a4, mmGB_MACROTILE_MODE1                       },
-+    { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE2                       },
-+    { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE3                       },
-+    { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE4                       },
-+    { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE5                       },
-+    { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE6                       },
-+    { PwrCmdWrite, 0x00000000, mmGB_MACROTILE_MODE7                       },
-+    { PwrCmdWrite, 0x000000ee, mmGB_MACROTILE_MODE8                       },
-+    { PwrCmdWrite, 0x000000ea, mmGB_MACROTILE_MODE9                       },
-+    { PwrCmdWrite, 0x000000e9, mmGB_MACROTILE_MODE10                      },
-+    { PwrCmdWrite, 0x000000e5, mmGB_MACROTILE_MODE11                      },
-+    { PwrCmdWrite, 0x000000e4, mmGB_MACROTILE_MODE12                      },
-+    { PwrCmdWrite, 0x000000e0, mmGB_MACROTILE_MODE13                      },
-+    { PwrCmdWrite, 0x00000090, mmGB_MACROTILE_MODE14                      },
-+    { PwrCmdWrite, 0x00000000, mmGB_MACROTILE_MODE15                      },
-+    { PwrCmdWrite, 0x00900000, mmHDP_NONSURFACE_BASE                      },
-+    { PwrCmdWrite, 0x00008000, mmHDP_NONSURFACE_INFO                      },
-+    { PwrCmdWrite, 0x3fffffff, mmHDP_NONSURFACE_SIZE                      },
-+    { PwrCmdWrite, 0x00000003, mmBIF_FB_EN                                },
-+    //{ PwrCmdWrite, 0x00000000, mmMC_VM_FB_OFFSET                          },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_CNTL                                },
-+    { PwrCmdWrite, 0x00020000, mmSRBM_CNTL                                },
-+    { PwrCmdWrite, 0x80000000, mmATC_VMID0_PASID_MAPPING                  },
-+    { PwrCmdWrite, 0x00000000, mmATC_VMID_PASID_MAPPING_UPDATE_STATUS     },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+    { PwrCmdWrite, 0xe0000000, mmGRBM_GFX_INDEX                           },
-+    { PwrCmdWrite, 0x00000000, mmCGTS_TCC_DISABLE                         },
-+    { PwrCmdWrite, 0x00000000, mmTCP_ADDR_CONFIG                          },
-+    { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG                          },
-+    { PwrCmdWrite, 0x76543210, mmTCP_CHAN_STEER_LO                        },
-+    { PwrCmdWrite, 0xfedcba98, mmTCP_CHAN_STEER_HI                        },
-+    { PwrCmdWrite, 0x00000000, mmDB_DEBUG2                                },
-+    { PwrCmdWrite, 0x00000000, mmDB_DEBUG                                 },
-+    { PwrCmdWrite, 0x00002b16, mmCP_QUEUE_THRESHOLDS                      },
-+    { PwrCmdWrite, 0x00006030, mmCP_MEQ_THRESHOLDS                        },
-+    { PwrCmdWrite, 0x01000104, mmSPI_CONFIG_CNTL_1                        },
-+    { PwrCmdWrite, 0x98184020, mmPA_SC_FIFO_SIZE                          },
-+    { PwrCmdWrite, 0x00000001, mmVGT_NUM_INSTANCES                        },
-+    { PwrCmdWrite, 0x00000000, mmCP_PERFMON_CNTL                          },
-+    { PwrCmdWrite, 0x01180000, mmSQ_CONFIG                                },
-+    { PwrCmdWrite, 0x00000000, mmVGT_CACHE_INVALIDATION                   },
-+    { PwrCmdWrite, 0x00000000, mmSQ_THREAD_TRACE_BASE                     },
-+    { PwrCmdWrite, 0x0000df80, mmSQ_THREAD_TRACE_MASK                     },
-+    { PwrCmdWrite, 0x02249249, mmSQ_THREAD_TRACE_MODE                     },
-+    { PwrCmdWrite, 0x00000000, mmPA_SC_LINE_STIPPLE_STATE                 },
-+    { PwrCmdWrite, 0x00000000, mmCB_PERFCOUNTER0_SELECT1                  },
-+    { PwrCmdWrite, 0x06000100, mmCGTT_VGT_CLK_CTRL                        },
-+    { PwrCmdWrite, 0x00000007, mmPA_CL_ENHANCE                            },
-+    { PwrCmdWrite, 0x00000001, mmPA_SC_ENHANCE                            },
-+    { PwrCmdWrite, 0x00ffffff, mmPA_SC_FORCE_EOV_MAX_CNTS                 },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000010, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000020, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000030, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000040, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000050, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000060, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000070, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000080, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000090, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x000000a0, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x000000b0, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x000000c0, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x000000d0, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x000000e0, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x000000f0, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmRLC_PG_CNTL                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS2                             },
-+    { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
-+    { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL                              },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x0000000e, mmSH_MEM_APE1_BASE                         },
-+    { PwrCmdWrite, 0x0000020d, mmSH_MEM_APE1_LIMIT                        },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000320, mmSH_MEM_CONFIG                            },
-+    { PwrCmdWrite, 0x00000000, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_RB_VMID                               },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+    { PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+    { PwrCmdWrite, 0x00000000, mmRLC_SRM_CNTL                             },
-+    { PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
-+    { PwrCmdWrite, 0x00000000, mmCP_ME_CNTL                               },
-+    { PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
-+    { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+    { PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL                              },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL                              },
-+    { PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL                                 },
-+    { PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE                          },
-+    { PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG                          },
-+    { PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
-+    { PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
-+    { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
-+    { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR                   },
-+    { PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+    { PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO                           },
-+    { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+    { PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO                           },
-+    { PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+    { PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO                           },
-+    { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+    { PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO                           },
-+    { PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+    { PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO                           },
-+    { PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+    { PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO                           },
-+    { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+    { PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+    { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR                         },
-+    { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+    { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+    { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+    { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+    { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+    { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+    { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR                         },
-+    { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+    { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+    { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+    { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+    { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+    { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+    { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR                         },
-+    { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+    { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+    { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+    { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+    { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+    { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+    { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR                         },
-+    { PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+    { PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+    { PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+    { PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+    { PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+    { PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+    { PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+    { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+    { PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+    { PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+    { PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+    { PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1                    },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+    { PwrCmdEnd,   0x00000000, 0x00000000                                 },
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu73.h b/drivers/gpu/drm/amd/powerplay/inc/smu73.h
-new file mode 100644
-index 0000000..c6b12a4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu73.h
-@@ -0,0 +1,720 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _SMU73_H_
-+#define _SMU73_H_
-+
-+#pragma pack(push, 1)
-+enum SID_OPTION {
-+  SID_OPTION_HI,
-+  SID_OPTION_LO,
-+  SID_OPTION_COUNT
-+};
-+
-+enum Poly3rdOrderCoeff {
-+    LEAKAGE_TEMPERATURE_SCALAR,
-+    LEAKAGE_VOLTAGE_SCALAR,
-+    DYNAMIC_VOLTAGE_SCALAR,
-+    POLY_3RD_ORDER_COUNT
-+};
-+
-+struct SMU7_Poly3rdOrder_Data
-+{
-+    int32_t a;
-+    int32_t b;
-+    int32_t c;
-+    int32_t d;
-+    uint8_t a_shift;
-+    uint8_t b_shift;
-+    uint8_t c_shift;
-+    uint8_t x_shift;
-+};
-+
-+typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
-+
-+struct Power_Calculator_Data
-+{
-+  uint16_t NoLoadVoltage;
-+  uint16_t LoadVoltage;
-+  uint16_t Resistance;
-+  uint16_t Temperature;
-+  uint16_t BaseLeakage;
-+  uint16_t LkgTempScalar;
-+  uint16_t LkgVoltScalar;
-+  uint16_t LkgAreaScalar;
-+  uint16_t LkgPower;
-+  uint16_t DynVoltScalar;
-+  uint32_t Cac;
-+  uint32_t DynPower;
-+  uint32_t TotalCurrent;
-+  uint32_t TotalPower;
-+};
-+
-+typedef struct Power_Calculator_Data PowerCalculatorData_t;
-+
-+struct Gc_Cac_Weight_Data
-+{
-+  uint8_t index;
-+  uint32_t value;
-+};
-+
-+typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
-+
-+
-+typedef struct {
-+  uint32_t high;
-+  uint32_t low;
-+} data_64_t;
-+
-+typedef struct {
-+  data_64_t high;
-+  data_64_t low;
-+} data_128_t;
-+
-+#define SMU__NUM_SCLK_DPM_STATE  8
-+#define SMU__NUM_MCLK_DPM_LEVELS 4
-+#define SMU__NUM_LCLK_DPM_LEVELS 8
-+#define SMU__NUM_PCIE_DPM_LEVELS 8
-+
-+#define SMU7_CONTEXT_ID_SMC        1
-+#define SMU7_CONTEXT_ID_VBIOS      2
-+
-+#define SMU73_MAX_LEVELS_VDDC            16
-+#define SMU73_MAX_LEVELS_VDDGFX          16
-+#define SMU73_MAX_LEVELS_VDDCI           8
-+#define SMU73_MAX_LEVELS_MVDD            4
-+
-+#define SMU_MAX_SMIO_LEVELS              4
-+
-+#define SMU73_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
-+#define SMU73_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
-+#define SMU73_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
-+#define SMU73_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
-+#define SMU73_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
-+#define SMU73_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
-+#define SMU73_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
-+#define SMU73_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
-+#define SMU73_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
-+
-+#define DPM_NO_LIMIT 0
-+#define DPM_NO_UP 1
-+#define DPM_GO_DOWN 2
-+#define DPM_GO_UP 3
-+
-+#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
-+#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
-+
-+#define GPIO_CLAMP_MODE_VRHOT      1
-+#define GPIO_CLAMP_MODE_THERM      2
-+#define GPIO_CLAMP_MODE_DC         4
-+
-+#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
-+#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
-+#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
-+#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
-+#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
-+#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
-+#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
-+#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
-+#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
-+#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
-+#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
-+
-+// Virtualization Defines
-+#define CG_XDMA_MASK  0x1
-+#define CG_XDMA_SHIFT 0
-+#define CG_UVD_MASK   0x2
-+#define CG_UVD_SHIFT  1
-+#define CG_VCE_MASK   0x4
-+#define CG_VCE_SHIFT  2
-+#define CG_SAMU_MASK  0x8
-+#define CG_SAMU_SHIFT 3
-+#define CG_GFX_MASK   0x10
-+#define CG_GFX_SHIFT  4
-+#define CG_SDMA_MASK  0x20
-+#define CG_SDMA_SHIFT 5
-+#define CG_HDP_MASK   0x40
-+#define CG_HDP_SHIFT  6
-+#define CG_MC_MASK    0x80
-+#define CG_MC_SHIFT   7
-+#define CG_DRM_MASK   0x100
-+#define CG_DRM_SHIFT  8
-+#define CG_ROM_MASK   0x200
-+#define CG_ROM_SHIFT  9
-+#define CG_BIF_MASK   0x400
-+#define CG_BIF_SHIFT  10
-+
-+#define SMU73_DTE_ITERATIONS 5
-+#define SMU73_DTE_SOURCES 3
-+#define SMU73_DTE_SINKS 1
-+#define SMU73_NUM_CPU_TES 0
-+#define SMU73_NUM_GPU_TES 1
-+#define SMU73_NUM_NON_TES 2
-+#define SMU73_DTE_FAN_SCALAR_MIN 0x100
-+#define SMU73_DTE_FAN_SCALAR_MAX 0x166
-+#define SMU73_DTE_FAN_TEMP_MAX 93
-+#define SMU73_DTE_FAN_TEMP_MIN 83
-+
-+#define SMU73_THERMAL_INPUT_LOOP_COUNT 6
-+#define SMU73_THERMAL_CLAMP_MODE_COUNT 8
-+
-+
-+struct SMU7_HystController_Data
-+{
-+    uint16_t waterfall_up;
-+    uint16_t waterfall_down;
-+    uint16_t waterfall_limit;
-+    uint16_t release_cnt;
-+    uint16_t release_limit;
-+    uint16_t spare;
-+};
-+
-+typedef struct SMU7_HystController_Data SMU7_HystController_Data;
-+
-+struct SMU73_PIDController
-+{
-+    uint32_t Ki;
-+    int32_t LFWindupUpperLim;
-+    int32_t LFWindupLowerLim;
-+    uint32_t StatePrecision;
-+
-+    uint32_t LfPrecision;
-+    uint32_t LfOffset;
-+    uint32_t MaxState;
-+    uint32_t MaxLfFraction;
-+    uint32_t StateShift;
-+};
-+
-+typedef struct SMU73_PIDController SMU73_PIDController;
-+
-+struct SMU7_LocalDpmScoreboard
-+{
-+    uint32_t PercentageBusy;
-+
-+    int32_t  PIDError;
-+    int32_t  PIDIntegral;
-+    int32_t  PIDOutput;
-+
-+    uint32_t SigmaDeltaAccum;
-+    uint32_t SigmaDeltaOutput;
-+    uint32_t SigmaDeltaLevel;
-+
-+    uint32_t UtilizationSetpoint;
-+
-+    uint8_t  TdpClampMode;
-+    uint8_t  TdcClampMode;
-+    uint8_t  ThermClampMode;
-+    uint8_t  VoltageBusy;
-+
-+    int8_t   CurrLevel;
-+    int8_t   TargLevel;
-+    uint8_t  LevelChangeInProgress;
-+    uint8_t  UpHyst;
-+
-+    uint8_t  DownHyst;
-+    uint8_t  VoltageDownHyst;
-+    uint8_t  DpmEnable;
-+    uint8_t  DpmRunning;
-+
-+    uint8_t  DpmForce;
-+    uint8_t  DpmForceLevel;
-+    uint8_t  DisplayWatermark;
-+    uint8_t  McArbIndex;
-+
-+    uint32_t MinimumPerfSclk;
-+
-+    uint8_t  AcpiReq;
-+    uint8_t  AcpiAck;
-+    uint8_t  GfxClkSlow;
-+    uint8_t  GpioClampMode;
-+
-+    uint8_t  spare2;
-+    uint8_t  EnabledLevelsChange;
-+    uint8_t  DteClampMode;
-+    uint8_t  FpsClampMode;
-+
-+    uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_GRAPHICS];
-+    uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_GRAPHICS];
-+
-+    void     (*TargetStateCalculator)(uint8_t);
-+    void     (*SavedTargetStateCalculator)(uint8_t);
-+
-+    uint16_t AutoDpmInterval;
-+    uint16_t AutoDpmRange;
-+
-+    uint8_t  FpsEnabled;
-+    uint8_t  MaxPerfLevel;
-+    uint8_t  AllowLowClkInterruptToHost;
-+    uint8_t  FpsRunning;
-+
-+    uint32_t MaxAllowedFrequency;
-+
-+    uint32_t FilteredSclkFrequency;
-+    uint32_t LastSclkFrequency;
-+    uint32_t FilteredSclkFrequencyCnt;
-+
-+    uint8_t  LedEnable;
-+    uint8_t  LedPin0;
-+    uint8_t  LedPin1;
-+    uint8_t  LedPin2;
-+    uint32_t LedAndMask;
-+
-+    uint16_t FpsAlpha;
-+    uint16_t DeltaTime;
-+    uint32_t CurrentFps;
-+    uint32_t FilteredFps;
-+    uint32_t FrameCount;
-+    uint32_t FrameCountLast;
-+    uint16_t FpsTargetScalar;
-+    uint16_t FpsWaterfallLimitScalar;
-+    uint16_t FpsAlphaScalar;
-+    uint16_t spare8;
-+    SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
-+
-+#define SMU7_MAX_VOLTAGE_CLIENTS 12
-+
-+typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
-+
-+#define VDDC_MASK    0x00007FFF
-+#define VDDC_SHIFT   0
-+#define VDDCI_MASK   0x3FFF8000
-+#define VDDCI_SHIFT  15
-+#define PHASES_MASK  0xC0000000
-+#define PHASES_SHIFT 30
-+
-+typedef uint32_t SMU_VoltageLevel;
-+
-+struct SMU7_VoltageScoreboard
-+{
-+    SMU_VoltageLevel TargetVoltage;
-+    uint16_t MaxVid;
-+    uint8_t  HighestVidOffset;
-+    uint8_t  CurrentVidOffset;
-+
-+    uint16_t CurrentVddc;
-+    uint16_t CurrentVddci;
-+
-+
-+    uint8_t  ControllerBusy;
-+    uint8_t  CurrentVid;
-+    uint8_t  CurrentVddciVid;
-+    uint8_t  padding;
-+
-+    SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
-+    SMU_VoltageLevel TargetVoltageState;
-+    uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
-+
-+    uint8_t  padding2;
-+    uint8_t  padding3;
-+    uint8_t  ControllerEnable;
-+    uint8_t  ControllerRunning;
-+    uint16_t CurrentStdVoltageHiSidd;
-+    uint16_t CurrentStdVoltageLoSidd;
-+    uint8_t  OverrideVoltage;
-+    uint8_t  padding4;
-+    uint8_t  padding5;
-+    uint8_t  CurrentPhases;
-+
-+    VoltageChangeHandler_t ChangeVddc;
-+
-+    VoltageChangeHandler_t ChangeVddci;
-+    VoltageChangeHandler_t ChangePhase;
-+    VoltageChangeHandler_t ChangeMvdd;
-+
-+    VoltageChangeHandler_t functionLinks[6];
-+
-+    uint16_t * VddcFollower1;
-+
-+    int16_t  Driver_OD_RequestedVidOffset1;
-+    int16_t  Driver_OD_RequestedVidOffset2;
-+
-+};
-+
-+typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
-+
-+// -------------------------------------------------------------------------------------------------------------------------
-+#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
-+
-+struct SMU7_PCIeLinkSpeedScoreboard
-+{
-+    uint8_t     DpmEnable;
-+    uint8_t     DpmRunning;
-+    uint8_t     DpmForce;
-+    uint8_t     DpmForceLevel;
-+
-+    uint8_t     CurrentLinkSpeed;
-+    uint8_t     EnabledLevelsChange;
-+    uint16_t    AutoDpmInterval;
-+
-+    uint16_t    AutoDpmRange;
-+    uint16_t    AutoDpmCount;
-+
-+    uint8_t     DpmMode;
-+    uint8_t     AcpiReq;
-+    uint8_t     AcpiAck;
-+    uint8_t     CurrentLinkLevel;
-+
-+};
-+
-+typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
-+
-+// -------------------------------------------------------- CAC table ------------------------------------------------------
-+#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
-+#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
-+
-+#define SMU7_SCALE_I  7
-+#define SMU7_SCALE_R 12
-+
-+struct SMU7_PowerScoreboard
-+{
-+    uint32_t GpuPower;
-+
-+    uint32_t VddcPower;
-+    uint32_t VddcVoltage;
-+    uint32_t VddcCurrent;
-+
-+    uint32_t MvddPower;
-+    uint32_t MvddVoltage;
-+    uint32_t MvddCurrent;
-+
-+    uint32_t RocPower;
-+
-+    uint16_t Telemetry_1_slope;
-+    uint16_t Telemetry_2_slope;
-+    int32_t  Telemetry_1_offset;
-+    int32_t  Telemetry_2_offset;
-+};
-+typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
-+
-+// For FeatureEnables:
-+#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
-+#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
-+#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
-+#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
-+#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
-+#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
-+#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
-+#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
-+#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
-+
-+#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
-+#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
-+#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
-+#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
-+#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
-+#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
-+
-+// All 'soft registers' should be uint32_t.
-+struct SMU73_SoftRegisters
-+{
-+    uint32_t        RefClockFrequency;
-+    uint32_t        PmTimerPeriod;
-+    uint32_t        FeatureEnables;
-+
-+    uint32_t        PreVBlankGap;
-+    uint32_t        VBlankTimeout;
-+    uint32_t        TrainTimeGap;
-+
-+    uint32_t        MvddSwitchTime;
-+    uint32_t        LongestAcpiTrainTime;
-+    uint32_t        AcpiDelay;
-+    uint32_t        G5TrainTime;
-+    uint32_t        DelayMpllPwron;
-+    uint32_t        VoltageChangeTimeout;
-+
-+    uint32_t        HandshakeDisables;
-+
-+    uint8_t         DisplayPhy1Config;
-+    uint8_t         DisplayPhy2Config;
-+    uint8_t         DisplayPhy3Config;
-+    uint8_t         DisplayPhy4Config;
-+
-+    uint8_t         DisplayPhy5Config;
-+    uint8_t         DisplayPhy6Config;
-+    uint8_t         DisplayPhy7Config;
-+    uint8_t         DisplayPhy8Config;
-+
-+    uint32_t        AverageGraphicsActivity;
-+    uint32_t        AverageMemoryActivity;
-+    uint32_t        AverageGioActivity;
-+
-+    uint8_t         SClkDpmEnabledLevels;
-+    uint8_t         MClkDpmEnabledLevels;
-+    uint8_t         LClkDpmEnabledLevels;
-+    uint8_t         PCIeDpmEnabledLevels;
-+
-+    uint8_t         UVDDpmEnabledLevels;
-+    uint8_t         SAMUDpmEnabledLevels;
-+    uint8_t         ACPDpmEnabledLevels;
-+    uint8_t         VCEDpmEnabledLevels;
-+
-+    uint32_t        DRAM_LOG_ADDR_H;
-+    uint32_t        DRAM_LOG_ADDR_L;
-+    uint32_t        DRAM_LOG_PHY_ADDR_H;
-+    uint32_t        DRAM_LOG_PHY_ADDR_L;
-+    uint32_t        DRAM_LOG_BUFF_SIZE;
-+    uint32_t        UlvEnterCount;
-+    uint32_t        UlvTime;
-+    uint32_t        UcodeLoadStatus;
-+    uint32_t        Reserved[2];
-+
-+};
-+
-+typedef struct SMU73_SoftRegisters SMU73_SoftRegisters;
-+
-+struct SMU73_Firmware_Header
-+{
-+    uint32_t Digest[5];
-+    uint32_t Version;
-+    uint32_t HeaderSize;
-+    uint32_t Flags;
-+    uint32_t EntryPoint;
-+    uint32_t CodeSize;
-+    uint32_t ImageSize;
-+
-+    uint32_t Rtos;
-+    uint32_t SoftRegisters;
-+    uint32_t DpmTable;
-+    uint32_t FanTable;
-+    uint32_t CacConfigTable;
-+    uint32_t CacStatusTable;
-+
-+
-+    uint32_t mcRegisterTable;
-+
-+
-+    uint32_t mcArbDramTimingTable;
-+
-+
-+
-+
-+    uint32_t PmFuseTable;
-+    uint32_t Globals;
-+    uint32_t ClockStretcherTable;
-+    uint32_t Reserved[41];
-+    uint32_t Signature;
-+};
-+
-+typedef struct SMU73_Firmware_Header SMU73_Firmware_Header;
-+
-+#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
-+
-+enum  DisplayConfig {
-+    PowerDown = 1,
-+    DP54x4,
-+    DP54x2,
-+    DP54x1,
-+    DP27x4,
-+    DP27x2,
-+    DP27x1,
-+    HDMI297,
-+    HDMI162,
-+    LVDS,
-+    DP324x4,
-+    DP324x2,
-+    DP324x1
-+};
-+
-+
-+#define MC_BLOCK_COUNT 1
-+#define CPL_BLOCK_COUNT 5
-+#define SE_BLOCK_COUNT 15
-+#define GC_BLOCK_COUNT 24
-+
-+struct SMU7_Local_Cac {
-+  uint8_t BlockId;
-+  uint8_t SignalId;
-+  uint8_t Threshold;
-+  uint8_t Padding;
-+};
-+
-+typedef struct SMU7_Local_Cac SMU7_Local_Cac;
-+
-+struct SMU7_Local_Cac_Table {
-+
-+  SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
-+  SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
-+  SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
-+  SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
-+};
-+
-+typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
-+
-+#if !defined(SMC_MICROCODE)
-+#pragma pack(pop)
-+#endif
-+
-+// Description of Clock Gating bitmask for Tonga:
-+// System Clock Gating
-+#define CG_SYS_BITMASK_FIRST_BIT      0  // First bit of Sys CG bitmask
-+#define CG_SYS_BITMASK_LAST_BIT       9  // Last bit of Sys CG bitmask
-+#define CG_SYS_BIF_MGLS_SHIFT         0
-+#define CG_SYS_ROM_SHIFT              1
-+#define CG_SYS_MC_MGCG_SHIFT          2
-+#define CG_SYS_MC_MGLS_SHIFT          3
-+#define CG_SYS_SDMA_MGCG_SHIFT        4
-+#define CG_SYS_SDMA_MGLS_SHIFT        5
-+#define CG_SYS_DRM_MGCG_SHIFT         6
-+#define CG_SYS_HDP_MGCG_SHIFT         7
-+#define CG_SYS_HDP_MGLS_SHIFT         8
-+#define CG_SYS_DRM_MGLS_SHIFT         9
-+
-+#define CG_SYS_BIF_MGLS_MASK          0x1
-+#define CG_SYS_ROM_MASK               0x2
-+#define CG_SYS_MC_MGCG_MASK           0x4
-+#define CG_SYS_MC_MGLS_MASK           0x8
-+#define CG_SYS_SDMA_MGCG_MASK         0x10
-+#define CG_SYS_SDMA_MGLS_MASK         0x20
-+#define CG_SYS_DRM_MGCG_MASK          0x40
-+#define CG_SYS_HDP_MGCG_MASK          0x80
-+#define CG_SYS_HDP_MGLS_MASK          0x100
-+#define CG_SYS_DRM_MGLS_MASK          0x200
-+
-+// Graphics Clock Gating
-+#define CG_GFX_BITMASK_FIRST_BIT      16 // First bit of Gfx CG bitmask
-+#define CG_GFX_BITMASK_LAST_BIT       20 // Last bit of Gfx CG bitmask
-+#define CG_GFX_CGCG_SHIFT             16
-+#define CG_GFX_CGLS_SHIFT             17
-+#define CG_CPF_MGCG_SHIFT             18
-+#define CG_RLC_MGCG_SHIFT             19
-+#define CG_GFX_OTHERS_MGCG_SHIFT      20
-+
-+#define CG_GFX_CGCG_MASK              0x00010000
-+#define CG_GFX_CGLS_MASK              0x00020000
-+#define CG_CPF_MGCG_MASK              0x00040000
-+#define CG_RLC_MGCG_MASK              0x00080000
-+#define CG_GFX_OTHERS_MGCG_MASK       0x00100000
-+
-+
-+
-+// Voltage Regulator Configuration
-+// VR Config info is contained in dpmTable.VRConfig
-+
-+#define VRCONF_VDDC_MASK         0x000000FF
-+#define VRCONF_VDDC_SHIFT        0
-+#define VRCONF_VDDGFX_MASK       0x0000FF00
-+#define VRCONF_VDDGFX_SHIFT      8
-+#define VRCONF_VDDCI_MASK        0x00FF0000
-+#define VRCONF_VDDCI_SHIFT       16
-+#define VRCONF_MVDD_MASK         0xFF000000
-+#define VRCONF_MVDD_SHIFT        24
-+
-+#define VR_MERGED_WITH_VDDC      0
-+#define VR_SVI2_PLANE_1          1
-+#define VR_SVI2_PLANE_2          2
-+#define VR_SMIO_PATTERN_1        3
-+#define VR_SMIO_PATTERN_2        4
-+#define VR_STATIC_VOLTAGE        5
-+
-+// Clock Stretcher Configuration
-+
-+#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
-+#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
-+
-+// The 'settings' field is subdivided in the following way:
-+#define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
-+#define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
-+#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
-+#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
-+#define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
-+#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
-+
-+struct SMU_ClockStretcherDataTableEntry {
-+  uint8_t minVID;
-+  uint8_t maxVID;
-+
-+
-+  uint16_t setting;
-+};
-+typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
-+
-+struct SMU_ClockStretcherDataTable {
-+  SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
-+};
-+typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
-+
-+struct SMU_CKS_LOOKUPTableEntry {
-+  uint16_t minFreq;
-+  uint16_t maxFreq;
-+
-+  uint8_t setting;
-+  uint8_t padding[3];
-+};
-+typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
-+
-+struct SMU_CKS_LOOKUPTable {
-+  SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
-+};
-+typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
-+
-+struct AgmAvfsData_t {
-+  uint16_t avgPsmCount[28];
-+  uint16_t minPsmCount[28];
-+};
-+typedef struct AgmAvfsData_t AgmAvfsData_t;
-+
-+// AVFS DEFINES
-+
-+enum VFT_COLUMNS {
-+  SCLK0,
-+  SCLK1,
-+  SCLK2,
-+  SCLK3,
-+  SCLK4,
-+  SCLK5,
-+  SCLK6,
-+  SCLK7,
-+
-+  NUM_VFT_COLUMNS
-+};
-+
-+#define TEMP_RANGE_MAXSTEPS 12
-+struct VFT_CELL_t {
-+  uint16_t Voltage;
-+};
-+
-+typedef struct VFT_CELL_t VFT_CELL_t;
-+
-+struct VFT_TABLE_t {
-+  VFT_CELL_t    Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
-+  uint16_t      AvfsGbv [NUM_VFT_COLUMNS];
-+  uint16_t      BtcGbv  [NUM_VFT_COLUMNS];
-+  uint16_t      Temperature [TEMP_RANGE_MAXSTEPS];
-+
-+  uint8_t       NumTemperatureSteps;
-+  uint8_t       padding[3];
-+};
-+typedef struct VFT_TABLE_t VFT_TABLE_t;
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h
-new file mode 100644
-index 0000000..5916be0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h
-@@ -0,0 +1,799 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _SMU73_DISCRETE_H_
-+#define _SMU73_DISCRETE_H_
-+
-+#include "smu73.h"
-+
-+#pragma pack(push, 1)
-+
-+struct SMIO_Pattern
-+{
-+  uint16_t Voltage;
-+  uint8_t  Smio;
-+  uint8_t  padding;
-+};
-+
-+typedef struct SMIO_Pattern SMIO_Pattern;
-+
-+struct SMIO_Table
-+{
-+  SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
-+};
-+
-+typedef struct SMIO_Table SMIO_Table;
-+
-+struct SMU73_Discrete_GraphicsLevel {
-+	uint32_t    MinVoltage;
-+
-+	uint32_t    SclkFrequency;
-+
-+	uint8_t     pcieDpmLevel;
-+	uint8_t     DeepSleepDivId;
-+	uint16_t    ActivityLevel;
-+	uint32_t    CgSpllFuncCntl3;
-+	uint32_t    CgSpllFuncCntl4;
-+	uint32_t    SpllSpreadSpectrum;
-+	uint32_t    SpllSpreadSpectrum2;
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+	uint8_t     SclkDid;
-+	uint8_t     DisplayWatermark;
-+	uint8_t     EnabledForActivity;
-+	uint8_t     EnabledForThrottle;
-+	uint8_t     UpHyst;
-+	uint8_t     DownHyst;
-+	uint8_t     VoltageDownHyst;
-+	uint8_t     PowerThrottle;
-+};
-+
-+typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel;
-+
-+struct SMU73_Discrete_ACPILevel {
-+    uint32_t    Flags;
-+    uint32_t MinVoltage;
-+    uint32_t    SclkFrequency;
-+    uint8_t     SclkDid;
-+    uint8_t     DisplayWatermark;
-+    uint8_t     DeepSleepDivId;
-+    uint8_t     padding;
-+    uint32_t    CgSpllFuncCntl;
-+    uint32_t    CgSpllFuncCntl2;
-+    uint32_t    CgSpllFuncCntl3;
-+    uint32_t    CgSpllFuncCntl4;
-+    uint32_t    SpllSpreadSpectrum;
-+    uint32_t    SpllSpreadSpectrum2;
-+    uint32_t    CcPwrDynRm;
-+    uint32_t    CcPwrDynRm1;
-+};
-+
-+typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel;
-+
-+struct SMU73_Discrete_Ulv {
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+	uint16_t    VddcOffset;
-+	uint8_t     VddcOffsetVid;
-+	uint8_t     VddcPhase;
-+	uint32_t    Reserved;
-+};
-+
-+typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv;
-+
-+struct SMU73_Discrete_MemoryLevel
-+{
-+    uint32_t MinVoltage;
-+    uint32_t    MinMvdd;
-+
-+    uint32_t    MclkFrequency;
-+
-+    uint8_t     StutterEnable;
-+    uint8_t     FreqRange;
-+    uint8_t     EnabledForThrottle;
-+    uint8_t     EnabledForActivity;
-+
-+    uint8_t     UpHyst;
-+    uint8_t     DownHyst;
-+    uint8_t     VoltageDownHyst;
-+    uint8_t     padding;
-+
-+    uint16_t    ActivityLevel;
-+    uint8_t     DisplayWatermark;
-+    uint8_t     MclkDivider;
-+};
-+
-+typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel;
-+
-+struct SMU73_Discrete_LinkLevel
-+{
-+    uint8_t     PcieGenSpeed;           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
-+    uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 
-+    uint8_t     EnabledForActivity;
-+    uint8_t     SPC;
-+    uint32_t    DownThreshold;
-+    uint32_t    UpThreshold;
-+    uint32_t    Reserved;
-+};
-+
-+typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel;
-+
-+
-+// MC ARB DRAM Timing registers.
-+struct SMU73_Discrete_MCArbDramTimingTableEntry
-+{
-+    uint32_t McArbDramTiming;
-+    uint32_t McArbDramTiming2;
-+    uint8_t  McArbBurstTime;
-+    uint8_t  TRRDS;
-+    uint8_t  TRRDL;
-+    uint8_t  padding;
-+};
-+
-+typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry;
-+
-+struct SMU73_Discrete_MCArbDramTimingTable
-+{
-+    SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
-+};
-+
-+typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable;
-+
-+// UVD VCLK/DCLK state (level) definition.
-+struct SMU73_Discrete_UvdLevel
-+{
-+    uint32_t VclkFrequency;
-+    uint32_t DclkFrequency;
-+    uint32_t MinVoltage;
-+    uint8_t  VclkDivider;
-+    uint8_t  DclkDivider;
-+    uint8_t  padding[2];
-+};
-+
-+typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel;
-+
-+// Clocks for other external blocks (VCE, ACP, SAMU).
-+struct SMU73_Discrete_ExtClkLevel
-+{
-+    uint32_t Frequency;
-+    uint32_t MinVoltage;
-+    uint8_t  Divider;
-+    uint8_t  padding[3];
-+};
-+
-+typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel;
-+
-+struct SMU73_Discrete_StateInfo
-+{
-+    uint32_t SclkFrequency;
-+    uint32_t MclkFrequency;
-+    uint32_t VclkFrequency;
-+    uint32_t DclkFrequency;
-+    uint32_t SamclkFrequency;
-+    uint32_t AclkFrequency;
-+    uint32_t EclkFrequency;
-+    uint16_t MvddVoltage;
-+    uint16_t padding16;
-+    uint8_t  DisplayWatermark;
-+    uint8_t  McArbIndex;
-+    uint8_t  McRegIndex;
-+    uint8_t  SeqIndex;
-+    uint8_t  SclkDid;
-+    int8_t   SclkIndex;
-+    int8_t   MclkIndex;
-+    uint8_t  PCIeGen;
-+
-+};
-+
-+typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo;
-+
-+struct SMU73_Discrete_DpmTable
-+{
-+    // Multi-DPM controller settings
-+    SMU73_PIDController                  GraphicsPIDController;
-+    SMU73_PIDController                  MemoryPIDController;
-+    SMU73_PIDController                  LinkPIDController;
-+
-+    uint32_t                            SystemFlags;
-+
-+    // SMIO masks for voltage and phase controls
-+    uint32_t                            VRConfig;
-+    uint32_t                            SmioMask1;
-+    uint32_t                            SmioMask2;
-+    SMIO_Table                          SmioTable1;
-+    SMIO_Table                          SmioTable2;
-+
-+    uint32_t                            MvddLevelCount;
-+
-+
-+    uint8_t                             BapmVddcVidHiSidd        [SMU73_MAX_LEVELS_VDDC];
-+    uint8_t                             BapmVddcVidLoSidd        [SMU73_MAX_LEVELS_VDDC];
-+    uint8_t                             BapmVddcVidHiSidd2       [SMU73_MAX_LEVELS_VDDC];
-+
-+    uint8_t                             GraphicsDpmLevelCount;
-+    uint8_t                             MemoryDpmLevelCount;
-+    uint8_t                             LinkLevelCount;
-+    uint8_t                             MasterDeepSleepControl;
-+
-+    uint8_t                             UvdLevelCount;
-+    uint8_t                             VceLevelCount;
-+    uint8_t                             AcpLevelCount;
-+    uint8_t                             SamuLevelCount;
-+
-+    uint8_t                             ThermOutGpio;
-+    uint8_t                             ThermOutPolarity;
-+    uint8_t                             ThermOutMode;
-+    uint8_t                             BootPhases;
-+    uint32_t                            Reserved[4];
-+
-+    // State table entries for each DPM state
-+    SMU73_Discrete_GraphicsLevel        GraphicsLevel           [SMU73_MAX_LEVELS_GRAPHICS];
-+    SMU73_Discrete_MemoryLevel          MemoryACPILevel;
-+    SMU73_Discrete_MemoryLevel          MemoryLevel             [SMU73_MAX_LEVELS_MEMORY];
-+    SMU73_Discrete_LinkLevel            LinkLevel               [SMU73_MAX_LEVELS_LINK];
-+    SMU73_Discrete_ACPILevel            ACPILevel;
-+    SMU73_Discrete_UvdLevel             UvdLevel                [SMU73_MAX_LEVELS_UVD];
-+    SMU73_Discrete_ExtClkLevel          VceLevel                [SMU73_MAX_LEVELS_VCE];
-+    SMU73_Discrete_ExtClkLevel          AcpLevel                [SMU73_MAX_LEVELS_ACP];
-+    SMU73_Discrete_ExtClkLevel          SamuLevel               [SMU73_MAX_LEVELS_SAMU];
-+    SMU73_Discrete_Ulv                  Ulv;
-+
-+    uint32_t                            SclkStepSize;
-+    uint32_t                            Smio                    [SMU73_MAX_ENTRIES_SMIO];
-+
-+    uint8_t                             UvdBootLevel;
-+    uint8_t                             VceBootLevel;
-+    uint8_t                             AcpBootLevel;
-+    uint8_t                             SamuBootLevel;
-+
-+    uint8_t                             GraphicsBootLevel;
-+    uint8_t                             GraphicsVoltageChangeEnable;
-+    uint8_t                             GraphicsThermThrottleEnable;
-+    uint8_t                             GraphicsInterval;
-+
-+    uint8_t                             VoltageInterval;
-+    uint8_t                             ThermalInterval;
-+    uint16_t                            TemperatureLimitHigh;
-+
-+    uint16_t                            TemperatureLimitLow;
-+    uint8_t                             MemoryBootLevel;
-+    uint8_t                             MemoryVoltageChangeEnable;
-+
-+    uint16_t                            BootMVdd;
-+    uint8_t                             MemoryInterval;
-+    uint8_t                             MemoryThermThrottleEnable;
-+
-+    uint16_t                            VoltageResponseTime;
-+    uint16_t                            PhaseResponseTime;
-+
-+    uint8_t                             PCIeBootLinkLevel;
-+    uint8_t                             PCIeGenInterval;
-+    uint8_t                             DTEInterval;
-+    uint8_t                             DTEMode;
-+
-+    uint8_t                             SVI2Enable;
-+    uint8_t                             VRHotGpio;
-+    uint8_t                             AcDcGpio;
-+    uint8_t                             ThermGpio;
-+
-+    uint16_t                            PPM_PkgPwrLimit;
-+    uint16_t                            PPM_TemperatureLimit;
-+
-+    uint16_t                            DefaultTdp;
-+    uint16_t                            TargetTdp;
-+
-+    uint16_t                            FpsHighThreshold;
-+    uint16_t                            FpsLowThreshold;
-+
-+    uint16_t                            TemperatureLimitEdge;
-+    uint16_t                            TemperatureLimitHotspot;
-+    uint16_t                            TemperatureLimitLiquid1;
-+    uint16_t                            TemperatureLimitLiquid2;
-+    uint16_t                            TemperatureLimitVrVddc;
-+    uint16_t                            TemperatureLimitVrMvdd;
-+    uint16_t                            TemperatureLimitPlx;
-+
-+    uint16_t                            FanGainEdge;
-+    uint16_t                            FanGainHotspot;
-+    uint16_t                            FanGainLiquid;
-+    uint16_t                            FanGainVrVddc;
-+    uint16_t                            FanGainVrMvdd;
-+    uint16_t                            FanGainPlx;
-+    uint16_t                            FanGainHbm;
-+
-+    uint8_t                             Liquid1_I2C_address;
-+    uint8_t                             Liquid2_I2C_address;
-+    uint8_t                             Vr_I2C_address;
-+    uint8_t                             Plx_I2C_address;
-+
-+    uint8_t                             GeminiMode;
-+    uint8_t                             spare17[3];
-+    uint32_t                            GeminiApertureHigh;
-+    uint32_t                            GeminiApertureLow;
-+
-+    uint8_t                             Liquid_I2C_LineSCL;
-+    uint8_t                             Liquid_I2C_LineSDA;
-+    uint8_t                             Vr_I2C_LineSCL;
-+    uint8_t                             Vr_I2C_LineSDA;
-+    uint8_t                             Plx_I2C_LineSCL;
-+    uint8_t                             Plx_I2C_LineSDA;
-+
-+    uint8_t                             spare1253[2];
-+    uint32_t                            spare123[2];
-+
-+    uint8_t                             DTEAmbientTempBase;
-+    uint8_t                             DTETjOffset;
-+    uint8_t                             GpuTjMax;
-+    uint8_t                             GpuTjHyst;
-+
-+    uint16_t                            BootVddc;
-+    uint16_t                            BootVddci;
-+
-+    uint32_t                            BAPM_TEMP_GRADIENT;
-+
-+    uint32_t                            LowSclkInterruptThreshold;
-+    uint32_t                            VddGfxReChkWait;
-+
-+    uint8_t                             ClockStretcherAmount;
-+    uint8_t                             Sclk_CKS_masterEn0_7;
-+    uint8_t                             Sclk_CKS_masterEn8_15;
-+    uint8_t                             DPMFreezeAndForced;
-+
-+    uint8_t                             Sclk_voltageOffset[8];
-+
-+    SMU_ClockStretcherDataTable         ClockStretcherDataTable;
-+    SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
-+};
-+
-+typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;
-+
-+
-+// --------------------------------------------------- Fan Table -----------------------------------------------------------
-+struct SMU73_Discrete_FanTable
-+{
-+    uint16_t FdoMode;
-+    int16_t  TempMin;
-+    int16_t  TempMed;
-+    int16_t  TempMax;
-+    int16_t  Slope1;
-+    int16_t  Slope2;
-+    int16_t  FdoMin;
-+    int16_t  HystUp;
-+    int16_t  HystDown;
-+    int16_t  HystSlope;
-+    int16_t  TempRespLim;
-+    int16_t  TempCurr;
-+    int16_t  SlopeCurr;
-+    int16_t  PwmCurr;
-+    uint32_t RefreshPeriod;
-+    int16_t  FdoMax;
-+    uint8_t  TempSrc;
-+    int8_t   Padding;
-+};
-+
-+typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable;
-+
-+#define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
-+#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
-+
-+
-+
-+struct SMU7_MclkDpmScoreboard
-+{
-+
-+    uint32_t PercentageBusy;
-+
-+    int32_t  PIDError;
-+    int32_t  PIDIntegral;
-+    int32_t  PIDOutput;
-+
-+    uint32_t SigmaDeltaAccum;
-+    uint32_t SigmaDeltaOutput;
-+    uint32_t SigmaDeltaLevel;
-+
-+    uint32_t UtilizationSetpoint;
-+
-+    uint8_t  TdpClampMode;
-+    uint8_t  TdcClampMode;
-+    uint8_t  ThermClampMode;
-+    uint8_t  VoltageBusy;
-+
-+    int8_t   CurrLevel;
-+    int8_t   TargLevel;
-+    uint8_t  LevelChangeInProgress;
-+    uint8_t  UpHyst;
-+
-+    uint8_t  DownHyst;
-+    uint8_t  VoltageDownHyst;
-+    uint8_t  DpmEnable;
-+    uint8_t  DpmRunning;
-+
-+    uint8_t  DpmForce;
-+    uint8_t  DpmForceLevel;
-+    uint8_t  DisplayWatermark;
-+    uint8_t  McArbIndex;
-+
-+    uint32_t MinimumPerfMclk;
-+
-+    uint8_t  AcpiReq;
-+    uint8_t  AcpiAck;
-+    uint8_t  MclkSwitchInProgress;
-+    uint8_t  MclkSwitchCritical;
-+
-+    uint8_t  IgnoreVBlank;
-+    uint8_t  TargetMclkIndex;
-+    uint8_t  TargetMvddIndex;
-+    uint8_t  MclkSwitchResult;
-+
-+    uint16_t VbiFailureCount;
-+    uint8_t  VbiWaitCounter;
-+    uint8_t  EnabledLevelsChange;
-+
-+    uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY];
-+    uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY];
-+
-+    void     (*TargetStateCalculator)(uint8_t);
-+    void     (*SavedTargetStateCalculator)(uint8_t);
-+
-+    uint16_t AutoDpmInterval;
-+    uint16_t AutoDpmRange;
-+
-+    uint16_t VbiTimeoutCount;
-+    uint16_t MclkSwitchingTime;
-+
-+    uint8_t  fastSwitch;
-+    uint8_t  Save_PIC_VDDGFX_EXIT;
-+    uint8_t  Save_PIC_VDDGFX_ENTER;
-+    uint8_t  padding;
-+
-+};
-+
-+typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
-+
-+struct SMU7_UlvScoreboard
-+{
-+    uint8_t     EnterUlv;
-+    uint8_t     ExitUlv;
-+    uint8_t     UlvActive;
-+    uint8_t     WaitingForUlv;
-+    uint8_t     UlvEnable;
-+    uint8_t     UlvRunning;
-+    uint8_t     UlvMasterEnable;
-+    uint8_t     padding;
-+    uint32_t    UlvAbortedCount;
-+    uint32_t    UlvTimeStamp;
-+};
-+
-+typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
-+
-+struct VddgfxSavedRegisters
-+{
-+  uint32_t GPU_DBG[3];
-+  uint32_t MEC_BaseAddress_Hi;
-+  uint32_t MEC_BaseAddress_Lo;
-+  uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
-+  uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
-+  uint32_t CP_INT_CNTL;
-+};
-+
-+typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
-+
-+struct SMU7_VddGfxScoreboard
-+{
-+    uint8_t     VddGfxEnable;
-+    uint8_t     VddGfxActive;
-+    uint8_t     VPUResetOccured;
-+    uint8_t     padding;
-+
-+    uint32_t    VddGfxEnteredCount;
-+    uint32_t    VddGfxAbortedCount;
-+
-+    uint32_t    VddGfxVid;
-+
-+    VddgfxSavedRegisters SavedRegisters;
-+};
-+
-+typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
-+
-+struct SMU7_TdcLimitScoreboard {
-+  uint8_t  Enable;
-+  uint8_t  Running;
-+  uint16_t Alpha;
-+  uint32_t FilteredIddc;
-+  uint32_t IddcLimit;
-+  uint32_t IddcHyst;
-+  SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
-+
-+struct SMU7_PkgPwrLimitScoreboard {
-+  uint8_t  Enable;
-+  uint8_t  Running;
-+  uint16_t Alpha;
-+  uint32_t FilteredPkgPwr;
-+  uint32_t Limit;
-+  uint32_t Hyst;
-+  uint32_t LimitFromDriver;
-+  SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
-+
-+struct SMU7_BapmScoreboard {
-+  uint32_t source_powers[SMU73_DTE_SOURCES];
-+  uint32_t source_powers_last[SMU73_DTE_SOURCES];
-+  int32_t entity_temperatures[SMU73_NUM_GPU_TES];
-+  int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES];
-+  int32_t Limit;
-+  int32_t Hyst;
-+  int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2];
-+  int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS];
-+  uint16_t ConfigTDPPowerScalar;
-+  uint16_t FanSpeedPowerScalar;
-+  uint16_t OverDrivePowerScalar;
-+  uint16_t OverDriveLimitScalar;
-+  uint16_t FinalPowerScalar;
-+  uint8_t VariantID;
-+  uint8_t spare997;
-+
-+  SMU7_HystController_Data HystControllerData;
-+
-+  int32_t temperature_gradient_slope;
-+  int32_t temperature_gradient;
-+  uint32_t measured_temperature;
-+};
-+
-+
-+typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
-+
-+struct SMU7_AcpiScoreboard {
-+  uint32_t SavedInterruptMask[2];
-+  uint8_t LastACPIRequest;
-+  uint8_t CgBifResp;
-+  uint8_t RequestType;
-+  uint8_t Padding;
-+  SMU73_Discrete_ACPILevel D0Level;
-+};
-+
-+typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
-+
-+struct SMU_QuadraticCoeffs {
-+  int32_t m1;
-+  uint32_t b;
-+
-+  int16_t m2;
-+  uint8_t m1_shift;
-+  uint8_t m2_shift;
-+};
-+
-+typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
-+
-+struct SMU73_Discrete_PmFuses {
-+  /* dw0-dw1 */
-+  uint8_t BapmVddCVidHiSidd[8];
-+
-+  /* dw2-dw3 */
-+  uint8_t BapmVddCVidLoSidd[8];
-+
-+  /* dw4-dw5 */
-+  uint8_t VddCVid[8];
-+
-+  /* dw1*/
-+  uint8_t SviLoadLineEn;
-+  uint8_t SviLoadLineVddC;
-+  uint8_t SviLoadLineTrimVddC;
-+  uint8_t SviLoadLineOffsetVddC;
-+
-+  /* dw2 */
-+  uint16_t TDC_VDDC_PkgLimit;
-+  uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
-+  uint8_t TDC_MAWt;
-+
-+  /* dw3 */
-+  uint8_t TdcWaterfallCtl;
-+  uint8_t LPMLTemperatureMin;
-+  uint8_t LPMLTemperatureMax;
-+  uint8_t Reserved;
-+
-+  /* dw4-dw7 */
-+  uint8_t LPMLTemperatureScaler[16];
-+
-+  /* dw8-dw9 */
-+  int16_t FuzzyFan_ErrorSetDelta;
-+  int16_t FuzzyFan_ErrorRateSetDelta;
-+  int16_t FuzzyFan_PwmSetDelta;
-+  uint16_t Reserved6;
-+
-+  /* dw10-dw14 */
-+  uint8_t GnbLPML[16];
-+
-+  /* dw15 */
-+  uint8_t GnbLPMLMaxVid;
-+  uint8_t GnbLPMLMinVid;
-+  uint8_t Reserved1[2];
-+
-+  /* dw16 */
-+  uint16_t BapmVddCBaseLeakageHiSidd;
-+  uint16_t BapmVddCBaseLeakageLoSidd;
-+
-+  /* AVFS */
-+  uint16_t  VFT_Temp[3];
-+  uint16_t  padding;
-+
-+  SMU_QuadraticCoeffs VFT_ATE[3];
-+
-+  SMU_QuadraticCoeffs AVFS_GB;
-+  SMU_QuadraticCoeffs ATE_ACBTC_GB;
-+
-+  SMU_QuadraticCoeffs P2V;
-+
-+  uint32_t PsmCharzFreq;
-+
-+  uint16_t InversionVoltage;
-+  uint16_t PsmCharzTemp;
-+
-+  uint32_t EnabledAvfsModules;
-+};
-+
-+typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses;
-+
-+struct SMU7_Discrete_Log_Header_Table {
-+  uint32_t    version;
-+  uint32_t    asic_id;
-+  uint16_t    flags;
-+  uint16_t    entry_size;
-+  uint32_t    total_size;
-+  uint32_t    num_of_entries;
-+  uint8_t     type;
-+  uint8_t     mode;
-+  uint8_t     filler_0[2];
-+  uint32_t    filler_1[2];
-+};
-+
-+typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
-+
-+struct SMU7_Discrete_Log_Cntl {
-+    uint8_t             Enabled;
-+    uint8_t             Type;
-+    uint8_t             padding[2];
-+    uint32_t            BufferSize;
-+    uint32_t            SamplesLogged;
-+    uint32_t            SampleSize;
-+    uint32_t            AddrL;
-+    uint32_t            AddrH;
-+};
-+
-+typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
-+
-+#define CAC_ACC_NW_NUM_OF_SIGNALS 87
-+
-+struct SMU7_Discrete_Cac_Collection_Table {
-+  uint32_t temperature;
-+  uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
-+};
-+
-+typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
-+
-+struct SMU7_Discrete_Cac_Verification_Table {
-+  uint32_t VddcTotalPower;
-+  uint32_t VddcLeakagePower;
-+  uint32_t VddcConstantPower;
-+  uint32_t VddcGfxDynamicPower;
-+  uint32_t VddcUvdDynamicPower;
-+  uint32_t VddcVceDynamicPower;
-+  uint32_t VddcAcpDynamicPower;
-+  uint32_t VddcPcieDynamicPower;
-+  uint32_t VddcDceDynamicPower;
-+  uint32_t VddcCurrent;
-+  uint32_t VddcVoltage;
-+  uint32_t VddciTotalPower;
-+  uint32_t VddciLeakagePower;
-+  uint32_t VddciConstantPower;
-+  uint32_t VddciDynamicPower;
-+  uint32_t Vddr1TotalPower;
-+  uint32_t Vddr1LeakagePower;
-+  uint32_t Vddr1ConstantPower;
-+  uint32_t Vddr1DynamicPower;
-+  uint32_t spare[4];
-+  uint32_t temperature;
-+};
-+
-+typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
-+
-+struct SMU7_Discrete_Pm_Status_Table {
-+  //Thermal entities
-+  int32_t  T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT];
-+  int32_t  T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT];
-+  int32_t  T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT];
-+  uint32_t T_hbm_acc;
-+
-+  //Voltage domains
-+  uint32_t I_calc_max;
-+  uint32_t I_calc_acc;
-+  uint32_t P_meas_acc;
-+  uint32_t V_meas_load_acc;
-+  uint32_t I_meas_acc;
-+  uint32_t P_meas_acc_vddci;
-+  uint32_t V_meas_load_acc_vddci;
-+  uint32_t I_meas_acc_vddci;
-+
-+  //Frequency
-+  uint16_t Sclk_dpm_residency[8];
-+  uint16_t Uvd_dpm_residency[8];
-+  uint16_t Vce_dpm_residency[8];
-+
-+  //Chip
-+  uint32_t P_roc_acc;
-+  uint32_t PkgPwr_max;
-+  uint32_t PkgPwr_acc;
-+  uint32_t MclkSwitchingTime_max;
-+  uint32_t MclkSwitchingTime_acc;
-+  uint32_t FanPwm_acc;
-+  uint32_t FanRpm_acc;
-+  uint32_t Gfx_busy_acc;
-+  uint32_t Mc_busy_acc;
-+  uint32_t Fps_acc;
-+
-+  uint32_t AccCnt;
-+};
-+
-+typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
-+
-+//FIXME THESE NEED TO BE UPDATED
-+#define SMU7_SCLK_CAC 0x561
-+#define SMU7_MCLK_CAC 0xF9
-+#define SMU7_VCLK_CAC 0x2DE
-+#define SMU7_DCLK_CAC 0x2DE
-+#define SMU7_ECLK_CAC 0x25E
-+#define SMU7_ACLK_CAC 0x25E
-+#define SMU7_SAMCLK_CAC 0x25E
-+#define SMU7_DISPCLK_CAC 0x100
-+#define SMU7_CAC_CONSTANT 0x2EE3430
-+#define SMU7_CAC_CONSTANT_SHIFT 18
-+
-+#define SMU7_VDDCI_MCLK_CONST        1765
-+#define SMU7_VDDCI_MCLK_CONST_SHIFT  16
-+#define SMU7_VDDCI_VDDCI_CONST       50958
-+#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
-+#define SMU7_VDDCI_CONST             11781
-+#define SMU7_VDDCI_STROBE_PWR        1331
-+
-+#define SMU7_VDDR1_CONST            693
-+#define SMU7_VDDR1_CAC_WEIGHT       20
-+#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
-+#define SMU7_VDDR1_STROBE_PWR       512
-+
-+#define SMU7_AREA_COEFF_UVD 0xA78
-+#define SMU7_AREA_COEFF_VCE 0x190A
-+#define SMU7_AREA_COEFF_ACP 0x22D1
-+#define SMU7_AREA_COEFF_SAMU 0x534
-+
-+//ThermOutMode values
-+#define SMU7_THERM_OUT_MODE_DISABLE       0x0
-+#define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
-+#define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
-+
-+#pragma pack(pop)
-+
-+#endif
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0056-drm-amd-powerplay-update-atomctrl-for-fiji.patch b/common/recipes-kernel/linux/files/0056-drm-amd-powerplay-update-atomctrl-for-fiji.patch
deleted file mode 100644
index 49111cc2..00000000
--- a/common/recipes-kernel/linux/files/0056-drm-amd-powerplay-update-atomctrl-for-fiji.patch
+++ /dev/null
@@ -1,621 +0,0 @@
-From 5f8eb56f0aacf11a3701dcb226657cea26c44dad Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 9 Nov 2015 17:35:45 -0500
-Subject: [PATCH 0056/1110] drm/amd/powerplay: update atomctrl for fiji
-
-Add some new functions to support Fiji.  Split out
-from the previous patch.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c  | 489 +++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h  |   6 +
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c |  10 +-
- 3 files changed, 496 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-index 9af2f59..8b47ea0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-@@ -28,6 +28,8 @@
- #include "atombios.h"
- #include "cgs_common.h"
- #include "pp_debug.h"
-+#include "ppevvmath.h"
-+
- #define MEM_ID_MASK           0xff000000
- #define MEM_ID_SHIFT          24
- #define CLOCK_RANGE_MASK      0x00ffffff
-@@ -94,7 +96,7 @@ static int atomctrl_retrieve_ac_timing(
-  * VBIOS set end of memory clock AC timing registers by ucPreRegDataLength bit6 = 1
-  * @param    reg_block the address ATOM_INIT_REG_BLOCK
-  * @param    table the address of MCRegTable
-- * @return   PP_Result_OK
-+ * @return   0
-  */
- static int atomctrl_set_mc_reg_address_table(
- 		ATOM_INIT_REG_BLOCK *reg_block,
-@@ -286,6 +288,31 @@ int atomctrl_get_memory_pll_dividers_si(
- 	return result;
- }
- 
-+/** atomctrl_get_memory_pll_dividers_vi().
-+ *
-+ * @param hwmgr                 input parameter: pointer to HwMgr
-+ * @param clock_value             input parameter: memory clock
-+ * @param dividers               output parameter: memory PLL dividers
-+ */
-+int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
-+		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)
-+{
-+	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
-+	int result;
-+
-+	mpll_parameters.ulClock.ulClock = (uint32_t)clock_value;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
-+			&mpll_parameters);
-+
-+	if (!result)
-+		mpll_param->mpll_post_divider =
-+				(uint32_t)mpll_parameters.ulClock.ucPostDiv;
-+
-+	return result;
-+}
-+
- int atomctrl_get_engine_pll_dividers_vi(
- 		struct pp_hwmgr *hwmgr,
- 		uint32_t clock_value,
-@@ -387,7 +414,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
- }
- 
- /**
-- * Returns 0 if the given voltage type is controlled by GPIO pins.
-+ * Returns true if the given voltage type is controlled by GPIO pins.
-  * voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC,
-  * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
-  * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
-@@ -402,10 +429,10 @@ bool atomctrl_is_voltage_controled_by_gpio_v3(
- 	bool ret;
- 
- 	PP_ASSERT_WITH_CODE((NULL != voltage_info),
--			"Could not find Voltage Table in BIOS.", return -1;);
-+			"Could not find Voltage Table in BIOS.", return false;);
- 
- 	ret = (NULL != atomctrl_lookup_voltage_type_v3
--			(voltage_info, voltage_type, voltage_mode)) ? 0 : 1;
-+			(voltage_info, voltage_type, voltage_mode)) ? true : false;
- 
- 	return ret;
- }
-@@ -525,6 +552,441 @@ bool atomctrl_get_pp_assign_pin(
- 	return bRet;
- }
- 
-+int atomctrl_calculate_voltage_evv_on_sclk(
-+		struct pp_hwmgr *hwmgr,
-+		uint8_t voltage_type,
-+		uint32_t sclk,
-+		uint16_t virtual_voltage_Id,
-+		uint16_t *voltage,
-+		uint16_t dpm_level,
-+		bool debug)
-+{
-+	ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;
-+
-+	EFUSE_LINEAR_FUNC_PARAM sRO_fuse;
-+	EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;
-+	EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;
-+	EFUSE_LOGISTIC_FUNC_PARAM sKt_Beta_fuse;
-+	EFUSE_LOGISTIC_FUNC_PARAM sKv_m_fuse;
-+	EFUSE_LOGISTIC_FUNC_PARAM sKv_b_fuse;
-+	EFUSE_INPUT_PARAMETER sInput_FuseValues;
-+	READ_EFUSE_VALUE_PARAMETER sOutput_FuseValues;
-+
-+	uint32_t ul_RO_fused, ul_CACb_fused, ul_CACm_fused, ul_Kt_Beta_fused, ul_Kv_m_fused, ul_Kv_b_fused;
-+	fInt fSM_A0, fSM_A1, fSM_A2, fSM_A3, fSM_A4, fSM_A5, fSM_A6, fSM_A7;
-+	fInt fMargin_RO_a, fMargin_RO_b, fMargin_RO_c, fMargin_fixed, fMargin_FMAX_mean, fMargin_Plat_mean, fMargin_FMAX_sigma, fMargin_Plat_sigma, fMargin_DC_sigma;
-+	fInt fLkg_FT, repeat;
-+	fInt fMicro_FMAX, fMicro_CR, fSigma_FMAX, fSigma_CR, fSigma_DC, fDC_SCLK, fSquared_Sigma_DC, fSquared_Sigma_CR, fSquared_Sigma_FMAX;
-+	fInt fRLL_LoadLine, fPowerDPMx, fDerateTDP, fVDDC_base, fA_Term, fC_Term, fB_Term, fRO_DC_margin;
-+	fInt fRO_fused, fCACm_fused, fCACb_fused, fKv_m_fused, fKv_b_fused, fKt_Beta_fused, fFT_Lkg_V0NORM;
-+	fInt fSclk_margin, fSclk, fEVV_V;
-+	fInt fV_min, fV_max, fT_prod, fLKG_Factor, fT_FT, fV_FT, fV_x, fTDP_Power, fTDP_Power_right, fTDP_Power_left, fTDP_Current, fV_NL;
-+	uint32_t ul_FT_Lkg_V0NORM;
-+	fInt fLn_MaxDivMin, fMin, fAverage, fRange;
-+	fInt fRoots[2];
-+	fInt fStepSize = GetScaledFraction(625, 100000);
-+
-+	int result;
-+
-+	getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)
-+			cgs_atom_get_data_table(hwmgr->device,
-+					GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
-+					NULL, NULL, NULL);
-+
-+	if (!getASICProfilingInfo)
-+		return -1;
-+
-+	if(getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 ||
-+			(getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 &&
-+			getASICProfilingInfo->asHeader.ucTableContentRevision < 4))
-+		return -1;
-+
-+	/*-----------------------------------------------------------
-+	 *GETTING MULTI-STEP PARAMETERS RELATED TO CURRENT DPM LEVEL
-+	 *-----------------------------------------------------------
-+	 */
-+	fRLL_LoadLine = Divide(getASICProfilingInfo->ulLoadLineSlop, 1000);
-+
-+	switch (dpm_level) {
-+	case 1:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm1);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM1, 1000);
-+		break;
-+	case 2:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm2);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM2, 1000);
-+		break;
-+	case 3:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm3);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM3, 1000);
-+		break;
-+	case 4:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm4);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM4, 1000);
-+		break;
-+	case 5:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm5);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM5, 1000);
-+		break;
-+	case 6:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm6);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM6, 1000);
-+		break;
-+	case 7:
-+		fPowerDPMx = Convert_ULONG_ToFraction(getASICProfilingInfo->usPowerDpm7);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM7, 1000);
-+		break;
-+	default:
-+		printk(KERN_ERR "DPM Level not supported\n");
-+		fPowerDPMx = Convert_ULONG_ToFraction(1);
-+		fDerateTDP = GetScaledFraction(getASICProfilingInfo->ulTdpDerateDPM0, 1000);
-+	}
-+
-+	/*-------------------------
-+	 * DECODING FUSE VALUES
-+	 * ------------------------
-+	 */
-+	/*Decode RO_Fused*/
-+	sRO_fuse = getASICProfilingInfo->sRoFuse;
-+
-+	sInput_FuseValues.usEfuseIndex = sRO_fuse.usEfuseIndex;
-+	sInput_FuseValues.ucBitShift = sRO_fuse.ucEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = sRO_fuse.ucEfuseLength;
-+
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+
-+	if (result)
-+		return result;
-+
-+	/* Finally, the actual fuse value */
-+	ul_RO_fused = sOutput_FuseValues.ulEfuseValue;
-+	fMin = GetScaledFraction(sRO_fuse.ulEfuseMin, 1);
-+	fRange = GetScaledFraction(sRO_fuse.ulEfuseEncodeRange, 1);
-+	fRO_fused = fDecodeLinearFuse(ul_RO_fused, fMin, fRange, sRO_fuse.ucEfuseLength);
-+
-+	sCACm_fuse = getASICProfilingInfo->sCACm;
-+
-+	sInput_FuseValues.usEfuseIndex = sCACm_fuse.usEfuseIndex;
-+	sInput_FuseValues.ucBitShift = sCACm_fuse.ucEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = sCACm_fuse.ucEfuseLength;
-+
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+
-+	if (result)
-+		return result;
-+
-+	ul_CACm_fused = sOutput_FuseValues.ulEfuseValue;
-+	fMin = GetScaledFraction(sCACm_fuse.ulEfuseMin, 1000);
-+	fRange = GetScaledFraction(sCACm_fuse.ulEfuseEncodeRange, 1000);
-+
-+	fCACm_fused = fDecodeLinearFuse(ul_CACm_fused, fMin, fRange, sCACm_fuse.ucEfuseLength);
-+
-+	sCACb_fuse = getASICProfilingInfo->sCACb;
-+
-+	sInput_FuseValues.usEfuseIndex = sCACb_fuse.usEfuseIndex;
-+	sInput_FuseValues.ucBitShift = sCACb_fuse.ucEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+
-+	if (result)
-+		return result;
-+
-+	ul_CACb_fused = sOutput_FuseValues.ulEfuseValue;
-+	fMin = GetScaledFraction(sCACb_fuse.ulEfuseMin, 1000);
-+	fRange = GetScaledFraction(sCACb_fuse.ulEfuseEncodeRange, 1000);
-+
-+	fCACb_fused = fDecodeLinearFuse(ul_CACb_fused, fMin, fRange, sCACb_fuse.ucEfuseLength);
-+
-+	sKt_Beta_fuse = getASICProfilingInfo->sKt_b;
-+
-+	sInput_FuseValues.usEfuseIndex = sKt_Beta_fuse.usEfuseIndex;
-+	sInput_FuseValues.ucBitShift = sKt_Beta_fuse.ucEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = sKt_Beta_fuse.ucEfuseLength;
-+
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+
-+	if (result)
-+		return result;
-+
-+	ul_Kt_Beta_fused = sOutput_FuseValues.ulEfuseValue;
-+	fAverage = GetScaledFraction(sKt_Beta_fuse.ulEfuseEncodeAverage, 1000);
-+	fRange = GetScaledFraction(sKt_Beta_fuse.ulEfuseEncodeRange, 1000);
-+
-+	fKt_Beta_fused = fDecodeLogisticFuse(ul_Kt_Beta_fused,
-+			fAverage, fRange, sKt_Beta_fuse.ucEfuseLength);
-+
-+	sKv_m_fuse = getASICProfilingInfo->sKv_m;
-+
-+	sInput_FuseValues.usEfuseIndex = sKv_m_fuse.usEfuseIndex;
-+	sInput_FuseValues.ucBitShift = sKv_m_fuse.ucEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = sKv_m_fuse.ucEfuseLength;
-+
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+	if (result)
-+		return result;
-+
-+	ul_Kv_m_fused = sOutput_FuseValues.ulEfuseValue;
-+	fAverage = GetScaledFraction(sKv_m_fuse.ulEfuseEncodeAverage, 1000);
-+	fRange = GetScaledFraction((sKv_m_fuse.ulEfuseEncodeRange & 0x7fffffff), 1000);
-+	fRange = fMultiply(fRange, ConvertToFraction(-1));
-+
-+	fKv_m_fused = fDecodeLogisticFuse(ul_Kv_m_fused,
-+			fAverage, fRange, sKv_m_fuse.ucEfuseLength);
-+
-+	sKv_b_fuse = getASICProfilingInfo->sKv_b;
-+
-+	sInput_FuseValues.usEfuseIndex = sKv_b_fuse.usEfuseIndex;
-+	sInput_FuseValues.ucBitShift = sKv_b_fuse.ucEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+
-+	if (result)
-+		return result;
-+
-+	ul_Kv_b_fused = sOutput_FuseValues.ulEfuseValue;
-+	fAverage = GetScaledFraction(sKv_b_fuse.ulEfuseEncodeAverage, 1000);
-+	fRange = GetScaledFraction(sKv_b_fuse.ulEfuseEncodeRange, 1000);
-+
-+	fKv_b_fused = fDecodeLogisticFuse(ul_Kv_b_fused,
-+			fAverage, fRange, sKv_b_fuse.ucEfuseLength);
-+
-+	/* Decoding the Leakage - No special struct container */
-+	/*
-+	 * usLkgEuseIndex=56
-+	 * ucLkgEfuseBitLSB=6
-+	 * ucLkgEfuseLength=10
-+	 * ulLkgEncodeLn_MaxDivMin=69077
-+	 * ulLkgEncodeMax=1000000
-+	 * ulLkgEncodeMin=1000
-+	 * ulEfuseLogisticAlpha=13
-+	 */
-+
-+	sInput_FuseValues.usEfuseIndex = getASICProfilingInfo->usLkgEuseIndex;
-+	sInput_FuseValues.ucBitShift = getASICProfilingInfo->ucLkgEfuseBitLSB;
-+	sInput_FuseValues.ucBitLength = getASICProfilingInfo->ucLkgEfuseLength;
-+
-+	sOutput_FuseValues.sEfuse = sInput_FuseValues;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&sOutput_FuseValues);
-+
-+	if (result)
-+		return result;
-+
-+	ul_FT_Lkg_V0NORM = sOutput_FuseValues.ulEfuseValue;
-+	fLn_MaxDivMin = GetScaledFraction(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin, 10000);
-+	fMin = GetScaledFraction(getASICProfilingInfo->ulLkgEncodeMin, 10000);
-+
-+	fFT_Lkg_V0NORM = fDecodeLeakageID(ul_FT_Lkg_V0NORM,
-+			fLn_MaxDivMin, fMin, getASICProfilingInfo->ucLkgEfuseLength);
-+	fLkg_FT = fFT_Lkg_V0NORM;
-+
-+	/*-------------------------------------------
-+	 * PART 2 - Grabbing all required values
-+	 *-------------------------------------------
-+	 */
-+	fSM_A0 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A0, 1000000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A0_sign)));
-+	fSM_A1 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A1, 1000000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A1_sign)));
-+	fSM_A2 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A2, 100000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A2_sign)));
-+	fSM_A3 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A3, 1000000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A3_sign)));
-+	fSM_A4 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A4, 1000000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A4_sign)));
-+	fSM_A5 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A5, 1000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A5_sign)));
-+	fSM_A6 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A6, 1000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A6_sign)));
-+	fSM_A7 = fMultiply(GetScaledFraction(getASICProfilingInfo->ulSM_A7, 1000),
-+			ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A7_sign)));
-+
-+	fMargin_RO_a = ConvertToFraction(getASICProfilingInfo->ulMargin_RO_a);
-+	fMargin_RO_b = ConvertToFraction(getASICProfilingInfo->ulMargin_RO_b);
-+	fMargin_RO_c = ConvertToFraction(getASICProfilingInfo->ulMargin_RO_c);
-+
-+	fMargin_fixed = ConvertToFraction(getASICProfilingInfo->ulMargin_fixed);
-+
-+	fMargin_FMAX_mean = GetScaledFraction(
-+			getASICProfilingInfo->ulMargin_Fmax_mean, 10000);
-+	fMargin_Plat_mean = GetScaledFraction(
-+			getASICProfilingInfo->ulMargin_plat_mean, 10000);
-+	fMargin_FMAX_sigma = GetScaledFraction(
-+			getASICProfilingInfo->ulMargin_Fmax_sigma, 10000);
-+	fMargin_Plat_sigma = GetScaledFraction(
-+			getASICProfilingInfo->ulMargin_plat_sigma, 10000);
-+
-+	fMargin_DC_sigma = GetScaledFraction(
-+			getASICProfilingInfo->ulMargin_DC_sigma, 100);
-+	fMargin_DC_sigma = fDivide(fMargin_DC_sigma, ConvertToFraction(1000));
-+
-+	fCACm_fused = fDivide(fCACm_fused, ConvertToFraction(100));
-+	fCACb_fused = fDivide(fCACb_fused, ConvertToFraction(100));
-+	fKt_Beta_fused = fDivide(fKt_Beta_fused, ConvertToFraction(100));
-+	fKv_m_fused =  fNegate(fDivide(fKv_m_fused, ConvertToFraction(100)));
-+	fKv_b_fused = fDivide(fKv_b_fused, ConvertToFraction(10));
-+
-+	fSclk = GetScaledFraction(sclk, 100);
-+
-+	fV_max = fDivide(GetScaledFraction(
-+			getASICProfilingInfo->ulMaxVddc, 1000), ConvertToFraction(4));
-+	fT_prod = GetScaledFraction(getASICProfilingInfo->ulBoardCoreTemp, 10);
-+	fLKG_Factor = GetScaledFraction(getASICProfilingInfo->ulEvvLkgFactor, 100);
-+	fT_FT = GetScaledFraction(getASICProfilingInfo->ulLeakageTemp, 10);
-+	fV_FT = fDivide(GetScaledFraction(
-+			getASICProfilingInfo->ulLeakageVoltage, 1000), ConvertToFraction(4));
-+	fV_min = fDivide(GetScaledFraction(
-+			getASICProfilingInfo->ulMinVddc, 1000), ConvertToFraction(4));
-+
-+	/*-----------------------
-+	 * PART 3
-+	 *-----------------------
-+	 */
-+
-+	fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4,fSclk), fSM_A5));
-+	fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b);
-+	fC_Term = fAdd(fMargin_RO_c,
-+			fAdd(fMultiply(fSM_A0,fLkg_FT),
-+			fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT,fSclk)),
-+			fAdd(fMultiply(fSM_A3, fSclk),
-+			fSubtract(fSM_A7,fRO_fused)))));
-+
-+	fVDDC_base = fSubtract(fRO_fused,
-+			fSubtract(fMargin_RO_c,
-+					fSubtract(fSM_A3, fMultiply(fSM_A1, fSclk))));
-+	fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0,fSclk), fSM_A2));
-+
-+	repeat = fSubtract(fVDDC_base,
-+			fDivide(fMargin_DC_sigma, ConvertToFraction(1000)));
-+
-+	fRO_DC_margin = fAdd(fMultiply(fMargin_RO_a,
-+			fGetSquare(repeat)),
-+			fAdd(fMultiply(fMargin_RO_b, repeat),
-+			fMargin_RO_c));
-+
-+	fDC_SCLK = fSubtract(fRO_fused,
-+			fSubtract(fRO_DC_margin,
-+			fSubtract(fSM_A3,
-+			fMultiply(fSM_A2, repeat))));
-+	fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0,repeat), fSM_A1));
-+
-+	fSigma_DC = fSubtract(fSclk, fDC_SCLK);
-+
-+	fMicro_FMAX = fMultiply(fSclk, fMargin_FMAX_mean);
-+	fMicro_CR = fMultiply(fSclk, fMargin_Plat_mean);
-+	fSigma_FMAX = fMultiply(fSclk, fMargin_FMAX_sigma);
-+	fSigma_CR = fMultiply(fSclk, fMargin_Plat_sigma);
-+
-+	fSquared_Sigma_DC = fGetSquare(fSigma_DC);
-+	fSquared_Sigma_CR = fGetSquare(fSigma_CR);
-+	fSquared_Sigma_FMAX = fGetSquare(fSigma_FMAX);
-+
-+	fSclk_margin = fAdd(fMicro_FMAX,
-+			fAdd(fMicro_CR,
-+			fAdd(fMargin_fixed,
-+			fSqrt(fAdd(fSquared_Sigma_FMAX,
-+			fAdd(fSquared_Sigma_DC, fSquared_Sigma_CR))))));
-+	/*
-+	 fA_Term = fSM_A4 * (fSclk + fSclk_margin) + fSM_A5;
-+	 fB_Term = fSM_A2 * (fSclk + fSclk_margin) + fSM_A6;
-+	 fC_Term = fRO_DC_margin + fSM_A0 * fLkg_FT + fSM_A1 * fLkg_FT * (fSclk + fSclk_margin) + fSM_A3 * (fSclk + fSclk_margin) + fSM_A7 - fRO_fused;
-+	 */
-+
-+	fA_Term = fAdd(fMultiply(fSM_A4, fAdd(fSclk, fSclk_margin)), fSM_A5);
-+	fB_Term = fAdd(fMultiply(fSM_A2, fAdd(fSclk, fSclk_margin)), fSM_A6);
-+	fC_Term = fAdd(fRO_DC_margin,
-+			fAdd(fMultiply(fSM_A0, fLkg_FT),
-+			fAdd(fMultiply(fMultiply(fSM_A1, fLkg_FT),
-+			fAdd(fSclk, fSclk_margin)),
-+			fAdd(fMultiply(fSM_A3,
-+			fAdd(fSclk, fSclk_margin)),
-+			fSubtract(fSM_A7, fRO_fused)))));
-+
-+	SolveQuadracticEqn(fA_Term, fB_Term, fC_Term, fRoots);
-+
-+	if (GreaterThan(fRoots[0], fRoots[1]))
-+		fEVV_V = fRoots[1];
-+	else
-+		fEVV_V = fRoots[0];
-+
-+	if (GreaterThan(fV_min, fEVV_V))
-+		fEVV_V = fV_min;
-+	else if (GreaterThan(fEVV_V, fV_max))
-+		fEVV_V = fSubtract(fV_max, fStepSize);
-+
-+	fEVV_V = fRoundUpByStepSize(fEVV_V, fStepSize, 0);
-+
-+	/*-----------------
-+	 * PART 4
-+	 *-----------------
-+	 */
-+
-+	fV_x = fV_min;
-+
-+	while (GreaterThan(fAdd(fV_max, fStepSize), fV_x)) {
-+		fTDP_Power_left = fMultiply(fMultiply(fMultiply(fAdd(
-+				fMultiply(fCACm_fused, fV_x), fCACb_fused), fSclk),
-+				fGetSquare(fV_x)), fDerateTDP);
-+
-+		fTDP_Power_right = fMultiply(fFT_Lkg_V0NORM, fMultiply(fLKG_Factor,
-+				fMultiply(fExponential(fMultiply(fAdd(fMultiply(fKv_m_fused,
-+				fT_prod), fKv_b_fused), fV_x)), fV_x)));
-+		fTDP_Power_right = fMultiply(fTDP_Power_right, fExponential(fMultiply(
-+				fKt_Beta_fused, fT_prod)));
-+		fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply(
-+				fAdd(fMultiply(fKv_m_fused, fT_prod), fKv_b_fused), fV_FT)));
-+		fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply(
-+				fKt_Beta_fused, fT_FT)));
-+
-+		fTDP_Power = fAdd(fTDP_Power_left, fTDP_Power_right);
-+
-+		fTDP_Current = fDivide(fTDP_Power, fV_x);
-+
-+		fV_NL = fAdd(fV_x, fDivide(fMultiply(fTDP_Current, fRLL_LoadLine),
-+				ConvertToFraction(10)));
-+
-+		fV_NL = fRoundUpByStepSize(fV_NL, fStepSize, 0);
-+
-+		if (GreaterThan(fV_max, fV_NL) &&
-+			(GreaterThan(fV_NL,fEVV_V) ||
-+			Equal(fV_NL, fEVV_V))) {
-+			fV_NL = fMultiply(fV_NL, ConvertToFraction(1000));
-+
-+			*voltage = (uint16_t)fV_NL.partial.real;
-+			break;
-+		} else
-+			fV_x = fAdd(fV_x, fStepSize);
-+	}
-+
-+	return result;
-+}
-+
- /** atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table.
-  * @param hwmgr               	input: pointer to hwManager
-  * @param voltage_type            input: type of EVV voltage VDDC or VDDGFX
-@@ -701,4 +1163,23 @@ int atomctrl_get_engine_clock_spread_spectrum(
- 			ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
- }
- 
-+int atomctrl_read_efuse(void *device, uint16_t start_index,
-+		uint16_t end_index, uint32_t mask, uint32_t *efuse)
-+{
-+	int result;
-+	READ_EFUSE_VALUE_PARAMETER efuse_param;
-+
-+	efuse_param.sEfuse.usEfuseIndex = (start_index / 32) * 4;
-+	efuse_param.sEfuse.ucBitShift = (uint8_t)
-+			(start_index - ((start_index / 32) * 32));
-+	efuse_param.sEfuse.ucBitLength  = (uint8_t)
-+			((end_index - start_index) + 1);
- 
-+	result = cgs_atom_exec_cmd_table(device,
-+			GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
-+			&efuse_param);
-+	if (!result)
-+		*efuse = efuse_param.ulEfuseValue & mask;
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-index 23da436..b5ba371 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-@@ -231,6 +231,12 @@ extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t
- extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
- extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
- extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
-+extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
-+		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
-+extern int atomctrl_read_efuse(void *device, uint16_t start_index,
-+		uint16_t end_index, uint32_t mask, uint32_t *efuse);
-+extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
-+		uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
- 
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 0feb1a8..1a02c7d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4507,14 +4507,14 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 	data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
- 	data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
- 
--	if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
- 				VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
- 		data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
- 	}
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_ControlVDDGFX)) {
--		if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
- 			VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
- 			data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
- 		}
-@@ -4527,7 +4527,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_EnableMVDDControl)) {
--		if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
- 					VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
- 			data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
- 		}
-@@ -4540,10 +4540,10 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_ControlVDDCI)) {
--		if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
- 					VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
- 			data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
--		else if (0 == atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
- 						VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
- 			data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0057-drm-amd-powerplay-add-Fiji-SMU-support.patch b/common/recipes-kernel/linux/files/0057-drm-amd-powerplay-add-Fiji-SMU-support.patch
deleted file mode 100644
index 5424fe2f..00000000
--- a/common/recipes-kernel/linux/files/0057-drm-amd-powerplay-add-Fiji-SMU-support.patch
+++ /dev/null
@@ -1,1181 +0,0 @@
-From 760992afb86e2e1baa3654e6327e5ed8fe1d04fe Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Wed, 26 Aug 2015 16:50:59 -0400
-Subject: [PATCH 0057/1110] drm/amd/powerplay: add Fiji SMU support.
-
-Add support for the SMU manager for Fiji. This handles the
-firmware loading for other IP blocks (GFX, SDMA, etc.).
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/smumgr/Makefile      |    2 +-
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 1035 ++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h |   77 ++
- drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |    4 +
- 4 files changed, 1117 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-index 0e3348d..6c4ef13 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'smu manager' sub-component of powerplay.
- # It provides the smu management services for the driver.
- 
--SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o
-+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o
- 
- AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-new file mode 100644
-index 0000000..c96b458
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-@@ -0,0 +1,1035 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "smumgr.h"
-+#include "smu73.h"
-+#include "smu_ucode_xfer_vi.h"
-+#include "fiji_smumgr.h"
-+#include "fiji_ppsmc.h"
-+#include "smu73_discrete.h"
-+#include "ppatomctrl.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "oss/oss_3_0_d.h"
-+#include "gca/gfx_8_0_d.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "pp_debug.h"
-+#include "fiji_pwrvirus.h"
-+
-+#define AVFS_EN_MSB                                        1568
-+#define AVFS_EN_LSB                                        1568
-+
-+#define FIJI_SMC_SIZE 0x20000
-+
-+struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
-+		/*  Min        Sclk       pcie     DeepSleep Activity  CgSpll      CgSpll    spllSpread  SpllSpread   CcPwr  CcPwr  Sclk   Display     Enabled     Enabled                       Voltage    Power */
-+		/* Voltage,  Frequency,  DpmLevel,  DivId,    Level,  FuncCntl3,  FuncCntl4,  Spectrum,   Spectrum2,  DynRm, DynRm1  Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
-+		{ 0x3c0fd047, 0x30750000,   0x00,     0x03,   0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0xa00fd047, 0x409c0000,   0x01,     0x04,   0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0x0410d047, 0x50c30000,   0x01,     0x00,   0x1e00, 0x00600410, 0x87020000, 0x21680000, 0x0d000000,   0,      0,   0x0e,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0x6810d047, 0x60ea0000,   0x01,     0x00,   0x1e00, 0x00800410, 0x87020000, 0x21680000, 0x0e000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0xcc10d047, 0xe8fd0000,   0x01,     0x00,   0x1e00, 0x00e00410, 0x87020000, 0x21680000, 0x0f000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0x3011d047, 0x70110100,   0x01,     0x00,   0x1e00, 0x00400510, 0x87020000, 0x21680000, 0x10000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0x9411d047, 0xf8240100,   0x01,     0x00,   0x1e00, 0x00a00510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-+		{ 0xf811d047, 0x80380100,   0x01,     0x00,   0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000,   0,      0,   0x0c,   0x01,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 }
-+};
-+
-+static enum cgs_ucode_id fiji_convert_fw_type_to_cgs(uint32_t fw_type)
-+{
-+	enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SMU:
-+		result = CGS_UCODE_ID_SMU;
-+		break;
-+	case UCODE_ID_SDMA0:
-+		result = CGS_UCODE_ID_SDMA0;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = CGS_UCODE_ID_SDMA1;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = CGS_UCODE_ID_CP_CE;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = CGS_UCODE_ID_CP_PFP;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = CGS_UCODE_ID_CP_ME;
-+		break;
-+	case UCODE_ID_CP_MEC:
-+		result = CGS_UCODE_ID_CP_MEC;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+		result = CGS_UCODE_ID_CP_MEC_JT1;
-+		break;
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = CGS_UCODE_ID_CP_MEC_JT2;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = CGS_UCODE_ID_RLC_G;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+/**
-+* Set the address for reading/writing the SMC SRAM space.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smc_addr the address in the SMC RAM to access.
-+*/
-+static int fiji_set_smc_sram_address(struct pp_smumgr *smumgr,
-+		uint32_t smc_addr, uint32_t limit)
-+{
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)),
-+			"SMC address must be 4 byte aligned.", return -EINVAL;);
-+	PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)),
-+			"SMC address is beyond the SMC RAM area.", return -EINVAL;);
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smc_addr);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-+
-+	return 0;
-+}
-+
-+/**
-+* Copy bytes from an array into the SMC RAM space.
-+*
-+* @param    smumgr  the address of the powerplay SMU manager.
-+* @param    smcStartAddress the start address in the SMC RAM to copy bytes to.
-+* @param    src the byte array to copy the bytes from.
-+* @param    byteCount the number of bytes to copy.
-+*/
-+int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
-+		uint32_t smcStartAddress, const uint8_t *src,
-+		uint32_t byteCount, uint32_t limit)
-+{
-+	int result;
-+	uint32_t data, originalData;
-+	uint32_t addr, extraShift;
-+
-+	PP_ASSERT_WITH_CODE((0 == (3 & smcStartAddress)),
-+			"SMC address must be 4 byte aligned.", return -EINVAL;);
-+	PP_ASSERT_WITH_CODE((limit > (smcStartAddress + byteCount)),
-+			"SMC address is beyond the SMC RAM area.", return -EINVAL;);
-+
-+	addr = smcStartAddress;
-+
-+	while (byteCount >= 4) {
-+		/* Bytes are written into the SMC addres space with the MSB first. */
-+		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
-+
-+		result = fiji_set_smc_sram_address(smumgr, addr, limit);
-+		if (result)
-+			return result;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-+
-+		src += 4;
-+		byteCount -= 4;
-+		addr += 4;
-+	}
-+
-+	if (byteCount) {
-+		/* Now write the odd bytes left.
-+		 * Do a read modify write cycle.
-+		 */
-+		data = 0;
-+
-+		result = fiji_set_smc_sram_address(smumgr, addr, limit);
-+		if (result)
-+			return result;
-+
-+		originalData = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
-+		extraShift = 8 * (4 - byteCount);
-+
-+		while (byteCount > 0) {
-+			/* Bytes are written into the SMC addres
-+			 * space with the MSB first.
-+			 */
-+			data = (0x100 * data) + *src++;
-+			byteCount--;
-+		}
-+		data <<= extraShift;
-+		data |= (originalData & ~((~0UL) << extraShift));
-+
-+		result = fiji_set_smc_sram_address(smumgr, addr, limit);
-+		if (!result)
-+			return result;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-+	}
-+	return 0;
-+}
-+
-+int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
-+{
-+	static unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
-+
-+	fiji_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data) + 1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Return if the SMC is currently running.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+*/
-+bool fiji_is_smc_ram_running(struct pp_smumgr *smumgr)
-+{
-+	return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
-+			CGS_IND_REG__SMC,
-+			SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-+			&& (0x20100 <= cgs_read_ind_register(smumgr->device,
-+					CGS_IND_REG__SMC, ixSMC_PC_C)));
-+}
-+
-+/**
-+* Send a message to the SMC, and wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+int fiji_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	if (!fiji_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) {
-+		printk(KERN_ERR "Failed to send Previous Message.");
-+		SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	}
-+
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+    SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+    return 0;
-+}
-+
-+/**
-+ * Send a message to the SMC with parameter
-+ * @param    smumgr:  the address of the powerplay hardware manager.
-+ * @param    msg: the message to send.
-+ * @param    parameter: the parameter to send
-+ * @return   The response that came from the SMC.
-+ */
-+int fiji_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+		uint16_t msg, uint32_t parameter)
-+{
-+	if (!fiji_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) {
-+		printk(KERN_ERR "Failed to send Previous Message.");
-+		SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	}
-+
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	return 0;
-+}
-+
-+
-+/**
-+* Send a message to the SMC with parameter, do not wait for response
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+int fiji_send_msg_to_smc_with_parameter_without_waiting(
-+		struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+{
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) {
-+		printk(KERN_ERR "Failed to send Previous Message.");
-+		SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	}
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	return 0;
-+}
-+
-+/**
-+* Uploads the SMU firmware from .hex file
-+*
-+* @param    smumgr  the address of the powerplay SMU manager.
-+* @return   0 or -1.
-+*/
-+
-+static int fiji_upload_smu_firmware_image(struct pp_smumgr *smumgr)
-+{
-+	const uint8_t *src;
-+	uint32_t byte_count;
-+	uint32_t *data;
-+	struct cgs_firmware_info info = {0};
-+
-+	cgs_get_firmware_info(smumgr->device,
-+			fiji_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
-+
-+	if (info.image_size & 3) {
-+		printk(KERN_ERR "SMC ucode is not 4 bytes aligned\n");
-+		return -EINVAL;
-+	}
-+
-+	if (info.image_size > FIJI_SMC_SIZE) {
-+		printk(KERN_ERR "SMC address is beyond the SMC RAM area\n");
-+		return -EINVAL;
-+	}
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, 0x20000);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
-+
-+	byte_count = info.image_size;
-+	src = (const uint8_t *)info.kptr;
-+
-+	data = (uint32_t *)src;
-+	for (; byte_count >= 4; data++, byte_count -= 4)
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data[0]);
-+
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-+	return 0;
-+}
-+
-+/**
-+* Read a 32bit value from the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smc_addr the address in the SMC RAM to access.
-+* @param    value and output parameter for the data read from the SMC SRAM.
-+*/
-+int fiji_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-+		uint32_t *value, uint32_t limit)
-+{
-+	int	result = fiji_set_smc_sram_address(smumgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
-+	return 0;
-+}
-+
-+/**
-+* Write a 32bit value to the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smc_addr the address in the SMC RAM to access.
-+* @param    value to write to the SMC SRAM.
-+*/
-+int fiji_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-+		uint32_t value, uint32_t limit)
-+{
-+	int result;
-+
-+	result = fiji_set_smc_sram_address(smumgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, value);
-+	return 0;
-+}
-+
-+static uint32_t fiji_get_mask_for_firmware_type(uint32_t fw_type)
-+{
-+	uint32_t result = 0;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SDMA0:
-+		result = UCODE_ID_SDMA0_MASK;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = UCODE_ID_SDMA1_MASK;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = UCODE_ID_CP_CE_MASK;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = UCODE_ID_CP_PFP_MASK;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = UCODE_ID_CP_ME_MASK;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+		result = UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
-+		break;
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT2_MASK;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = UCODE_ID_RLC_G_MASK;
-+		break;
-+	default:
-+		printk(KERN_ERR "UCode type is out of range!");
-+		result = 0;
-+	}
-+
-+	return result;
-+}
-+
-+/* Populate one firmware image to the data structure */
-+static int fiji_populate_single_firmware_entry(struct pp_smumgr *smumgr,
-+		uint32_t fw_type, struct SMU_Entry *entry)
-+{
-+	int result;
-+	struct cgs_firmware_info info = {0};
-+
-+	result = cgs_get_firmware_info(
-+			smumgr->device,
-+			fiji_convert_fw_type_to_cgs(fw_type),
-+			&info);
-+
-+	if (!result) {
-+		entry->version = 0;
-+		entry->id = (uint16_t)fw_type;
-+		entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
-+		entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
-+		entry->meta_data_addr_high = 0;
-+		entry->meta_data_addr_low = 0;
-+		entry->data_size_byte = info.image_size;
-+		entry->num_register_entries = 0;
-+
-+		if (fw_type == UCODE_ID_RLC_G)
-+			entry->flags = 1;
-+		else
-+			entry->flags = 0;
-+	}
-+
-+	return result;
-+}
-+
-+static int fiji_request_smu_load_fw(struct pp_smumgr *smumgr)
-+{
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+	uint32_t fw_to_load;
-+	struct SMU_DRAMData_TOC *toc;
-+
-+	if (priv->soft_regs_start)
-+		cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+				priv->soft_regs_start +
-+				offsetof(SMU73_SoftRegisters, UcodeLoadStatus),
-+				0x0);
-+
-+	toc = (struct SMU_DRAMData_TOC *)priv->header;
-+	toc->num_entries = 0;
-+	toc->structure_version = 1;
-+
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
-+			"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
-+			"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
-+			"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
-+			"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
-+			"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
-+					"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
-+					"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
-+					"Failed to Get Firmware Entry.\n" , return -1 );
-+	PP_ASSERT_WITH_CODE(
-+			0 == fiji_populate_single_firmware_entry(smumgr,
-+					UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
-+					"Failed to Get Firmware Entry.\n" , return -1 );
-+
-+	fiji_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI,
-+			priv->header_buffer.mc_addr_high);
-+	fiji_send_msg_to_smc_with_parameter(smumgr,PPSMC_MSG_DRV_DRAM_ADDR_LO,
-+			priv->header_buffer.mc_addr_low);
-+
-+	fw_to_load = UCODE_ID_RLC_G_MASK
-+			+ UCODE_ID_SDMA0_MASK
-+			+ UCODE_ID_SDMA1_MASK
-+			+ UCODE_ID_CP_CE_MASK
-+			+ UCODE_ID_CP_ME_MASK
-+			+ UCODE_ID_CP_PFP_MASK
-+			+ UCODE_ID_CP_MEC_MASK
-+			+ UCODE_ID_CP_MEC_JT1_MASK
-+			+ UCODE_ID_CP_MEC_JT2_MASK;
-+
-+	if (fiji_send_msg_to_smc_with_parameter(smumgr,
-+			PPSMC_MSG_LoadUcodes, fw_to_load))
-+		printk(KERN_ERR "Fail to Request SMU Load uCode");
-+
-+	return 0;
-+}
-+
-+
-+/* Check if the FW has been loaded, SMU will not return
-+ * if loading has not finished.
-+ */
-+static int fiji_check_fw_load_finish(struct pp_smumgr *smumgr,
-+		uint32_t fw_type)
-+{
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+	uint32_t mask = fiji_get_mask_for_firmware_type(fw_type);
-+
-+	/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
-+	if (smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX,
-+			priv->soft_regs_start +
-+			offsetof(SMU73_SoftRegisters, UcodeLoadStatus),
-+			mask, mask)) {
-+		printk(KERN_ERR "check firmware loading failed\n");
-+		return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+
-+static int fiji_reload_firmware(struct pp_smumgr *smumgr)
-+{
-+	return smumgr->smumgr_funcs->start_smu(smumgr);
-+}
-+
-+static bool fiji_is_hw_virtualization_enabled(struct pp_smumgr *smumgr)
-+{
-+	uint32_t value;
-+
-+	value = cgs_read_register(smumgr->device, mmBIF_IOV_FUNC_IDENTIFIER);
-+	if (value & BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK) {
-+		/* driver reads on SR-IOV enabled PF: 0x80000000
-+		 * driver reads on SR-IOV enabled VF: 0x80000001
-+		 * driver reads on SR-IOV disabled:   0x00000000
-+		 */
-+		return true;
-+	}
-+	return false;
-+}
-+
-+static int fiji_request_smu_specific_fw_load(struct pp_smumgr *smumgr, uint32_t fw_type)
-+{
-+	if (fiji_is_hw_virtualization_enabled(smumgr)) {
-+		uint32_t masks = fiji_get_mask_for_firmware_type(fw_type);
-+		if (fiji_send_msg_to_smc_with_parameter_without_waiting(smumgr,
-+				PPSMC_MSG_LoadUcodes, masks))
-+			printk(KERN_ERR "Fail to Request SMU Load uCode");
-+	}
-+	/* For non-virtualization cases,
-+	 * SMU loads all FWs at once in fiji_request_smu_load_fw.
-+	 */
-+    return 0;
-+}
-+
-+static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* Wait for smc boot up */
-+	/* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+		RCU_UC_EVENTS, boot_seq_done, 0); */
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	result = fiji_upload_smu_firmware_image(smumgr);
-+	if (result)
-+		return result;
-+
-+	/* Clear status */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+			ixSMU_STATUS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	/* De-assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for ROM firmware to initialize interrupt hendler */
-+	/*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
-+			SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
-+
-+	/* Set SMU Auto Start */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMU_INPUT_DATA, AUTO_START, 1);
-+
-+	/* Clear firmware interrupt enable flag */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+			ixFIRMWARE_FLAGS, 0);
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS,
-+			INTERRUPTS_ENABLED, 1);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	/* Wait for done bit to be set */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+			SMU_STATUS, SMU_DONE, 0);
-+
-+	/* Check pass/failed indicator */
-+	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMU_STATUS, SMU_PASS)) {
-+		PP_ASSERT_WITH_CODE(false,
-+				"SMU Firmware start failed!", return -1);
-+	}
-+
-+	/* Wait for firmware to initialize */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+			FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* wait for smc boot up */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+			RCU_UC_EVENTS, boot_seq_done, 0);
-+
-+	/* Clear firmware interrupt enable flag */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+			ixFIRMWARE_FLAGS, 0);
-+
-+	/* Assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	result = fiji_upload_smu_firmware_image(smumgr);
-+	if (result)
-+		return result;
-+
-+	/* Set smc instruct start point at 0x0 */
-+	fiji_program_jump_on_start(smumgr);
-+
-+	/* Enable clock */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	/* De-assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+			SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for firmware to initialize */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+			FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
-+{
-+	int i, result = -1;
-+	uint32_t reg, data;
-+	PWR_Command_Table *virus = PwrVirusTable;
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+
-+	priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS;
-+	for (i = 0; (i < PWR_VIRUS_TABLE_SIZE); i++) {
-+		switch (virus->command) {
-+		case PwrCmdWrite:
-+			reg  = virus->reg;
-+			data = virus->data;
-+			cgs_write_register(smumgr->device, reg, data);
-+			break;
-+		case PwrCmdEnd:
-+			priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_LOADED;
-+			result = 0;
-+			break;
-+		default:
-+			printk(KERN_ERR "Table Exit with Invalid Command!");
-+			priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL;
-+			result = -1;
-+			break;
-+		}
-+		virus++;
-+	}
-+	return result;
-+}
-+
-+static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+
-+	priv->avfs.AvfsBtcStatus = AVFS_BTC_STARTED;
-+	if (priv->avfs.AvfsBtcParam) {
-+		if (!fiji_send_msg_to_smc_with_parameter(smumgr,
-+				PPSMC_MSG_PerformBtc, priv->avfs.AvfsBtcParam)) {
-+			if (!fiji_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs)) {
-+				priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_UNSAVED;
-+				result = 0;
-+			} else {
-+				printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] Attempt"
-+						" to Enable AVFS Failed!");
-+				fiji_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs);
-+				result = -1;
-+			}
-+		} else {
-+			printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] "
-+					"PerformBTC SMU msg failed");
-+			result = -1;
-+		}
-+	}
-+	/* Soft-Reset to reset the engine before loading uCode */
-+	 /* halt */
-+	cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
-+	/* reset everything */
-+	cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
-+	/* clear reset */
-+	cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
-+
-+    return result;
-+}
-+
-+int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	uint32_t table_start;
-+	uint32_t charz_freq_addr, inversion_voltage_addr, charz_freq;
-+	uint16_t inversion_voltage;
-+
-+	charz_freq = 0x30750000; /* In 10KHz units 0x00007530 Actual value */
-+	inversion_voltage = 0x1A04; /* mV Q14.2 0x41A Actual value */
-+
-+	PP_ASSERT_WITH_CODE(0 == fiji_read_smc_sram_dword(smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header,
-+					PmFuseTable), &table_start, 0x40000),
-+			"[AVFS][Fiji_SetupGfxLvlStruct] SMU could not communicate "
-+			"starting address of PmFuse structure",
-+			return -1;);
-+
-+	charz_freq_addr = table_start +
-+			offsetof(struct SMU73_Discrete_PmFuses, PsmCharzFreq);
-+	inversion_voltage_addr = table_start +
-+			offsetof(struct SMU73_Discrete_PmFuses, InversionVoltage);
-+
-+	result = fiji_copy_bytes_to_smc(smumgr, charz_freq_addr,
-+			(uint8_t *)(&charz_freq), sizeof(charz_freq), 0x40000);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"[AVFS][fiji_setup_pm_fuse_for_avfs] charz_freq could not "
-+			"be populated.", return -1;);
-+
-+	result = fiji_copy_bytes_to_smc(smumgr, inversion_voltage_addr,
-+			(uint8_t *)(&inversion_voltage), sizeof(inversion_voltage), 0x40000);
-+	PP_ASSERT_WITH_CODE(0 == result, "[AVFS][fiji_setup_pm_fuse_for_avfs] "
-+			"charz_freq could not be populated.", return -1;);
-+
-+	return result;
-+}
-+
-+int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
-+{
-+	int32_t vr_config;
-+	uint32_t table_start;
-+	uint32_t level_addr, vr_config_addr;
-+	uint32_t level_size = sizeof(avfs_graphics_level);
-+
-+	PP_ASSERT_WITH_CODE(0 == fiji_read_smc_sram_dword(smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, DpmTable),
-+			&table_start, 0x40000),
-+			"[AVFS][Fiji_SetupGfxLvlStruct] SMU could not "
-+			"communicate starting address of DPM table",
-+			return -1;);
-+
-+	/* Default value for vr_config =
-+	 * VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
-+	vr_config = 0x01000500;   /* Real value:0x50001 */
-+
-+	vr_config_addr = table_start +
-+			offsetof(SMU73_Discrete_DpmTable, VRConfig);
-+
-+	PP_ASSERT_WITH_CODE(0 == fiji_copy_bytes_to_smc(smumgr, vr_config_addr,
-+			(uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
-+			"[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
-+			"vr_config value over to SMC",
-+			return -1;);
-+
-+	level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
-+
-+	PP_ASSERT_WITH_CODE(0 == fiji_copy_bytes_to_smc(smumgr, level_addr,
-+			(uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
-+			"[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
-+			return -1;);
-+
-+	return 0;
-+}
-+
-+/* Work in Progress */
-+int fiji_restore_vft_table(struct pp_smumgr *smumgr)
-+{
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+
-+	if (AVFS_BTC_COMPLETED_SAVED == priv->avfs.AvfsBtcStatus) {
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_RESTORED;
-+		return 0;
-+	} else
-+		return -EINVAL;
-+}
-+
-+/* Work in Progress */
-+int fiji_save_vft_table(struct pp_smumgr *smumgr)
-+{
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+
-+	if (AVFS_BTC_COMPLETED_SAVED == priv->avfs.AvfsBtcStatus) {
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_RESTORED;
-+		return 0;
-+	} else
-+		return -EINVAL;
-+}
-+
-+int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
-+{
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+
-+	switch (priv->avfs.AvfsBtcStatus) {
-+	case AVFS_BTC_COMPLETED_SAVED: /*S3 State - Pre SMU Start */
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_RESTOREVFT_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == fiji_restore_vft_table(smumgr),
-+				"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics "
-+				"Level table over to SMU",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_RESTORED;
-+		break;
-+	case AVFS_BTC_COMPLETED_RESTORED: /*S3 State - Post SMU Start*/
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_SMUMSG_ERROR;
-+		PP_ASSERT_WITH_CODE(0 == fiji_send_msg_to_smc(smumgr,
-+				PPSMC_MSG_VftTableIsValid),
-+				"[AVFS][fiji_avfs_event_mgr] SMU did not respond "
-+				"correctly to VftTableIsValid Msg",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_SMUMSG_ERROR;
-+		PP_ASSERT_WITH_CODE(0 == fiji_send_msg_to_smc(smumgr,
-+				PPSMC_MSG_EnableAvfs),
-+				"[AVFS][fiji_avfs_event_mgr] SMU did not respond "
-+				"correctly to EnableAvfs Message Msg",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_SAVED;
-+		break;
-+	case AVFS_BTC_BOOT: /*Cold Boot State - Post SMU Start*/
-+		if (!smu_started)
-+			break;
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == fiji_setup_pm_fuse_for_avfs(smumgr),
-+				"[AVFS][fiji_avfs_event_mgr] Failure at "
-+				"fiji_setup_pm_fuse_for_avfs",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_DPMTABLESETUP_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr),
-+				"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
-+				" table over to SMU",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL;
-+		PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr),
-+				"[AVFS][fiji_avfs_event_mgr] Could not setup "
-+				"Pwr Virus for AVFS ",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr),
-+				"[AVFS][fiji_avfs_event_mgr] Failure at "
-+				"fiji_start_avfs_btc. AVFS Disabled",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_SAVEVFT_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == fiji_save_vft_table(smumgr),
-+				"[AVFS][fiji_avfs_event_mgr] Could not save VFT Table",
-+				return -1;);
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_SAVED;
-+		break;
-+	case AVFS_BTC_DISABLED: /* Do nothing */
-+		break;
-+	case AVFS_BTC_NOTSUPPORTED: /* Do nothing */
-+		break;
-+	default:
-+		printk(KERN_ERR "[AVFS] Something is broken. See log!");
-+		break;
-+	}
-+	return 0;
-+}
-+
-+static int fiji_start_smu(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+
-+	/* Only start SMC if SMC RAM is not running */
-+	if (!fiji_is_smc_ram_running(smumgr)) {
-+		fiji_avfs_event_mgr(smumgr, false);
-+
-+		/* Check if SMU is running in protected mode */
-+		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
-+				CGS_IND_REG__SMC,
-+				SMU_FIRMWARE, SMU_MODE)) {
-+			result = fiji_start_smu_in_non_protection_mode(smumgr);
-+			if (result)
-+				return result;
-+		} else {
-+			result = fiji_start_smu_in_protection_mode(smumgr);
-+			if (result)
-+				return result;
-+		}
-+		fiji_avfs_event_mgr(smumgr, true);
-+	}
-+
-+	/* To initialize all clock gating before RLC loaded and running.*/
-+	/*PECI_InitClockGating(peci);*/
-+
-+	/* Setup SoftRegsStart here for register lookup in case
-+	 * DummyBackEnd is used and ProcessFirmwareHeader is not executed
-+	 */
-+	fiji_read_smc_sram_dword(smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, SoftRegisters),
-+			&(priv->soft_regs_start), 0x40000);
-+
-+	result = fiji_request_smu_load_fw(smumgr);
-+
-+	return result;
-+}
-+
-+static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
-+{
-+
-+	uint32_t efuse = 0;
-+	uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
-+
-+	if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
-+			mask, &efuse)) {
-+		if (efuse)
-+			return true;
-+	}
-+	return false;
-+}
-+
-+/**
-+* Write a 32bit value to the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smc_addr the address in the SMC RAM to access.
-+* @param    value to write to the SMC SRAM.
-+*/
-+static int fiji_smu_init(struct pp_smumgr *smumgr)
-+{
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+	uint64_t mc_addr;
-+
-+	priv->header_buffer.data_size =
-+			((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
-+	smu_allocate_memory(smumgr->device,
-+			priv->header_buffer.data_size,
-+			CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+			PAGE_SIZE,
-+			&mc_addr,
-+			&priv->header_buffer.kaddr,
-+			&priv->header_buffer.handle);
-+
-+	priv->header = priv->header_buffer.kaddr;
-+	priv->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	priv->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != priv->header),
-+			"Out of memory.",
-+			kfree(smumgr->backend);
-+			cgs_free_gpu_mem(smumgr->device,
-+			(cgs_handle_t)priv->header_buffer.handle);
-+			return -1);
-+
-+	priv->avfs.AvfsBtcStatus = AVFS_BTC_BOOT;
-+	if (fiji_is_hw_avfs_present(smumgr))
-+		/* AVFS Parameter
-+		 * 0 - BTC DC disabled, BTC AC disabled
-+		 * 1 - BTC DC enabled,  BTC AC disabled
-+		 * 2 - BTC DC disabled, BTC AC enabled
-+		 * 3 - BTC DC enabled,  BTC AC enabled
-+		 * Default is 0 - BTC DC disabled, BTC AC disabled
-+		 */
-+		priv->avfs.AvfsBtcParam = 0;
-+	else
-+		priv->avfs.AvfsBtcStatus = AVFS_BTC_NOTSUPPORTED;
-+
-+	priv->acpi_optimization = 1;
-+
-+	return 0;
-+}
-+
-+static int fiji_smu_fini(struct pp_smumgr *smumgr)
-+{
-+	if (smumgr->backend) {
-+		kfree(smumgr->backend);
-+		smumgr->backend = NULL;
-+	}
-+	return 0;
-+}
-+
-+static const struct pp_smumgr_func fiji_smu_funcs = {
-+	.smu_init = &fiji_smu_init,
-+	.smu_fini = &fiji_smu_fini,
-+	.start_smu = &fiji_start_smu,
-+	.check_fw_load_finish = &fiji_check_fw_load_finish,
-+	.request_smu_load_fw = &fiji_reload_firmware,
-+	.request_smu_load_specific_fw = &fiji_request_smu_specific_fw_load,
-+	.send_msg_to_smc = &fiji_send_msg_to_smc,
-+	.send_msg_to_smc_with_parameter = &fiji_send_msg_to_smc_with_parameter,
-+	.download_pptable_settings = NULL,
-+	.upload_pptable_settings = NULL,
-+};
-+
-+int fiji_smum_init(struct pp_smumgr *smumgr)
-+{
-+	struct fiji_smumgr *fiji_smu = NULL;
-+
-+	fiji_smu = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
-+
-+	if (fiji_smu == NULL)
-+		return -1;
-+
-+	smumgr->backend = fiji_smu;
-+	smumgr->smumgr_funcs = &fiji_smu_funcs;
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
-new file mode 100644
-index 0000000..8cd22d9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
-@@ -0,0 +1,77 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _FIJI_SMUMANAGER_H_
-+#define _FIJI_SMUMANAGER_H_
-+
-+enum AVFS_BTC_STATUS {
-+	AVFS_BTC_BOOT = 0,
-+	AVFS_BTC_BOOT_STARTEDSMU,
-+	AVFS_LOAD_VIRUS,
-+	AVFS_BTC_VIRUS_LOADED,
-+	AVFS_BTC_VIRUS_FAIL,
-+	AVFS_BTC_STARTED,
-+	AVFS_BTC_FAILED,
-+	AVFS_BTC_RESTOREVFT_FAILED,
-+	AVFS_BTC_SAVEVFT_FAILED,
-+	AVFS_BTC_DPMTABLESETUP_FAILED,
-+	AVFS_BTC_COMPLETED_UNSAVED,
-+	AVFS_BTC_COMPLETED_SAVED,
-+	AVFS_BTC_COMPLETED_RESTORED,
-+	AVFS_BTC_DISABLED,
-+	AVFS_BTC_NOTSUPPORTED,
-+	AVFS_BTC_SMUMSG_ERROR
-+};
-+
-+struct fiji_smu_avfs {
-+	enum AVFS_BTC_STATUS AvfsBtcStatus;
-+	uint32_t           AvfsBtcParam;
-+};
-+
-+struct fiji_buffer_entry {
-+	uint32_t data_size;
-+	uint32_t mc_addr_low;
-+	uint32_t mc_addr_high;
-+	void *kaddr;
-+	unsigned long  handle;
-+};
-+
-+struct fiji_smumgr {
-+	uint8_t        *header;
-+	uint8_t        *mec_image;
-+	uint32_t        soft_regs_start;
-+	struct fiji_smu_avfs avfs;
-+	uint32_t        acpi_optimization;
-+
-+	struct fiji_buffer_entry header_buffer;
-+};
-+
-+int fiji_smum_init(struct pp_smumgr *smumgr);
-+int fiji_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smcAddress,
-+		uint32_t *value, uint32_t limit);
-+int fiji_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-+		uint32_t value, uint32_t limit);
-+int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smcStartAddress,
-+		const uint8_t *src,	uint32_t byteCount, uint32_t limit);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-index a386ca8..063ae71 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-@@ -29,6 +29,7 @@
- #include "linux/delay.h"
- #include "cz_smumgr.h"
- #include "tonga_smumgr.h"
-+#include "fiji_smumgr.h"
- 
- int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -58,6 +59,9 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		case CHIP_TONGA:
- 			tonga_smum_init(smumgr);
- 			break;
-+		case CHIP_FIJI:
-+			fiji_smum_init(smumgr);
-+			break;
- 		default:
- 			return -EINVAL;
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0058-drm-amd-powerplay-add-Fiji-DPM-support.patch b/common/recipes-kernel/linux/files/0058-drm-amd-powerplay-add-Fiji-DPM-support.patch
deleted file mode 100644
index e9336534..00000000
--- a/common/recipes-kernel/linux/files/0058-drm-amd-powerplay-add-Fiji-DPM-support.patch
+++ /dev/null
@@ -1,5906 +0,0 @@
-From 9c74c84bd1448613a5f18b23d7ef0221110fe52b Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Wed, 26 Aug 2015 16:52:28 -0400
-Subject: [PATCH 0058/1110] drm/amd/powerplay: add Fiji DPM support.
-
-This enabled DPM support for Fiji.  DPM is dynamic
-clock and voltage scaling.
-
-v2: rename fiji_hwmgr_early_init to fiji_hwmgr_init
-v3: (agd) fold in endian fix, additional function addition
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |    3 +-
- .../drm/amd/powerplay/hwmgr/fiji_dyn_defaults.h    |  105 +
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   | 4728 ++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h   |  356 ++
- .../gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c   |  553 +++
- .../gpu/drm/amd/powerplay/hwmgr/fiji_powertune.h   |   66 +
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |    5 +
- 7 files changed, 5815 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_dyn_defaults.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index fd73d3c..c78e38c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -6,7 +6,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
- 	       hardwaremanager.o pp_acpi.o cz_hwmgr.o \
-                cz_clockpowergating.o \
- 	       tonga_processpptables.o ppatomctrl.o \
--               tonga_hwmgr.o 	pppcielanes.o
-+               tonga_hwmgr.o 	pppcielanes.o \
-+               fiji_powertune.o fiji_hwmgr.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_dyn_defaults.h
-new file mode 100644
-index 0000000..32d43e8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_dyn_defaults.h
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef FIJI_DYN_DEFAULTS_H
-+#define FIJI_DYN_DEFAULTS_H
-+
-+/** \file
-+* Volcanic Islands Dynamic default parameters.
-+*/
-+
-+enum FIJIdpm_TrendDetection
-+{
-+    FIJIAdpm_TrendDetection_AUTO,
-+    FIJIAdpm_TrendDetection_UP,
-+    FIJIAdpm_TrendDetection_DOWN
-+};
-+typedef enum FIJIdpm_TrendDetection FIJIdpm_TrendDetection;
-+
-+/* We need to fill in the default values!!!!!!!!!!!!!!!!!!!!!!! */
-+
-+/* Bit vector representing same fields as hardware register. */
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0    0x3FFFC102  /* CP_Gfx_busy ????
-+                                                         * HDP_busy
-+                                                         * IH_busy
-+                                                         * UVD_busy
-+                                                         * VCE_busy
-+                                                         * ACP_busy
-+                                                         * SAMU_busy
-+                                                         * SDMA enabled */
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1    0x000400  /* FE_Gfx_busy  - Intended for primary usage.   Rest are for flexibility. ????
-+                                                       * SH_Gfx_busy
-+                                                       * RB_Gfx_busy
-+                                                       * VCE_busy */
-+
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2    0xC00080  /* SH_Gfx_busy - Intended for primary usage.   Rest are for flexibility.
-+                                                       * FE_Gfx_busy
-+                                                       * RB_Gfx_busy
-+                                                       * ACP_busy */
-+
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3    0xC00200  /* RB_Gfx_busy - Intended for primary usage.   Rest are for flexibility.
-+                                                       * FE_Gfx_busy
-+                                                       * SH_Gfx_busy
-+                                                       * UVD_busy */
-+
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4    0xC01680  /* UVD_busy
-+                                                       * VCE_busy
-+                                                       * ACP_busy
-+                                                       * SAMU_busy */
-+
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5    0xC00033  /* GFX, HDP */
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6    0xC00033  /* GFX, HDP */
-+#define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7    0x3FFFC000  /* GFX, HDP */
-+
-+
-+/* thermal protection counter (units). */
-+#define PPFIJI_THERMALPROTECTCOUNTER_DFLT            0x200 /* ~19us */
-+
-+/* static screen threshold unit */
-+#define PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT    0
-+
-+/* static screen threshold */
-+#define PPFIJI_STATICSCREENTHRESHOLD_DFLT        0x00C8
-+
-+/* gfx idle clock stop threshold */
-+#define PPFIJI_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200 /* ~19us with static screen threshold unit of 0 */
-+
-+/* Fixed reference divider to use when building baby stepping tables. */
-+#define PPFIJI_REFERENCEDIVIDER_DFLT                  4
-+
-+/* ULV voltage change delay time
-+ * Used to be delay_vreg in N.I. split for S.I.
-+ * Using N.I. delay_vreg value as default
-+ * ReferenceClock = 2700
-+ * VoltageResponseTime = 1000
-+ * VDDCDelayTime = (VoltageResponseTime * ReferenceClock) / 1600 = 1687
-+ */
-+#define PPFIJI_ULVVOLTAGECHANGEDELAY_DFLT             1687
-+
-+#define PPFIJI_CGULVPARAMETER_DFLT			0x00040035
-+#define PPFIJI_CGULVCONTROL_DFLT			0x00007450
-+#define PPFIJI_TARGETACTIVITY_DFLT			30 /* 30%*/
-+#define PPFIJI_MCLK_TARGETACTIVITY_DFLT		10 /* 10% */
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-new file mode 100644
-index 0000000..4457878
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -0,0 +1,4728 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+#include "linux/delay.h"
-+
-+#include "hwmgr.h"
-+#include "fiji_smumgr.h"
-+#include "atombios.h"
-+#include "hardwaremanager.h"
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "cgs_common.h"
-+#include "fiji_dyn_defaults.h"
-+#include "fiji_powertune.h"
-+#include "smu73.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+#include "pppcielanes.h"
-+#include "fiji_hwmgr.h"
-+#include "tonga_processpptables.h"
-+#include "tonga_pptable.h"
-+#include "pp_debug.h"
-+#include "pp_acpi.h"
-+
-+#define VOLTAGE_SCALE	4
-+#define SMC_RAM_END		0x40000
-+#define VDDC_VDDCI_DELTA	300
-+
-+#define MC_SEQ_MISC0_GDDR5_SHIFT 28
-+#define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
-+#define MC_SEQ_MISC0_GDDR5_VALUE 5
-+
-+#define MC_CG_ARB_FREQ_F0           0x0a /* boot-up default */
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define MC_CG_ARB_FREQ_F2           0x0c
-+#define MC_CG_ARB_FREQ_F3           0x0d
-+
-+/* From smc_reg.h */
-+#define SMC_CG_IND_START            0xc0030000
-+#define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND */
-+
-+#define VOLTAGE_SCALE               4
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+
-+#define VDDC_VDDCI_DELTA            300
-+
-+#define ixSWRST_COMMAND_1           0x1400103
-+#define MC_SEQ_CNTL__CAC_EN_MASK    0x40000000
-+
-+/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
-+enum DPM_EVENT_SRC {
-+    DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
-+    DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
-+    DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
-+    DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
-+    DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
-+};
-+
-+enum DISPLAY_GAP {
-+	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
-+	DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
-+	DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. */
-+	DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
-+};
-+
-+/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
-+ * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
-+ */
-+uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
-+                                                {600, 1050, 6, 1} };
-+
-+/* [FF, SS] type, [] 4 voltage ranges, and
-+ * [Floor Freq, Boundary Freq, VID min , VID max]
-+ */
-+uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
-+{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+  { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-+
-+/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
-+ * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
-+ */
-+uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
-+                                                  {0, 2, 4, 5, 6, 5} };
-+
-+const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
-+
-+struct fiji_power_state *cast_phw_fiji_power_state(
-+				  struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL;);
-+
-+	return (struct fiji_power_state *)hw_ps;
-+}
-+
-+const struct fiji_power_state *cast_const_phw_fiji_power_state(
-+				 const struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL;);
-+
-+	return (const struct fiji_power_state *)hw_ps;
-+}
-+
-+static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
-+static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_ulv_parm *ulv = &data->ulv;
-+
-+	ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
-+	data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
-+	data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
-+	data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
-+	data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
-+	data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
-+	data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
-+	data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
-+	data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
-+
-+	data->static_screen_threshold_unit =
-+			PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
-+	data->static_screen_threshold =
-+			PPFIJI_STATICSCREENTHRESHOLD_DFLT;
-+
-+	/* Unset ABM cap as it moved to DAL.
-+	 * Add PHM_PlatformCaps_NonABMSupportInPPLib
-+	 * for re-direct ABM related request to DAL
-+	 */
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ABM);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_NonABMSupportInPPLib);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DynamicACTiming);
-+
-+	fiji_initialize_power_tune_defaults(hwmgr);
-+
-+	data->mclk_stutter_mode_threshold = 60000;
-+	data->pcie_gen_performance.max = PP_PCIEGen1;
-+	data->pcie_gen_performance.min = PP_PCIEGen3;
-+	data->pcie_gen_power_saving.max = PP_PCIEGen1;
-+	data->pcie_gen_power_saving.min = PP_PCIEGen3;
-+	data->pcie_lane_performance.max = 0;
-+	data->pcie_lane_performance.min = 16;
-+	data->pcie_lane_power_saving.max = 0;
-+	data->pcie_lane_power_saving.min = 16;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DynamicUVDState);
-+}
-+
-+static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
-+	phm_ppt_v1_voltage_lookup_table *lookup_table,
-+	uint16_t virtual_voltage_id, int32_t *sclk)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
-+	for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
-+		voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
-+		if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
-+			break;
-+	}
-+
-+	PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
-+			"Can't find requested voltage id in vdd_dep_on_sclk table!",
-+			return -EINVAL;
-+			);
-+
-+	*sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
-+
-+	return 0;
-+}
-+
-+/**
-+* Get Leakage VDDC based on leakage ID.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint16_t    vv_id;
-+	uint16_t    vddc = 0;
-+	uint16_t    evv_default = 1150;
-+	uint16_t    i, j;
-+	uint32_t  sclk = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	int result;
-+
-+	for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
-+		vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-+		if (!fiji_get_sclk_for_voltage_evv(hwmgr,
-+				table_info->vddc_lookup_table, vv_id, &sclk)) {
-+			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_ClockStretcher)) {
-+				for (j = 1; j < sclk_table->count; j++) {
-+					if (sclk_table->entries[j].clk == sclk &&
-+							sclk_table->entries[j].cks_enable == 0) {
-+						sclk += 5000;
-+						break;
-+					}
-+				}
-+			}
-+
-+			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_EnableDriverEVV))
-+				result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
-+						VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
-+			else
-+				result = -EINVAL;
-+
-+			if (result)
-+				result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
-+						VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
-+
-+			/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
-+			PP_ASSERT_WITH_CODE((vddc < 2000),
-+					"Invalid VDDC value, greater than 2v!", result = -EINVAL;);
-+
-+			if (result)
-+				/* 1.15V is the default safe value for Fiji */
-+				vddc = evv_default;
-+
-+			/* the voltage should not be zero nor equal to leakage ID */
-+			if (vddc != 0 && vddc != vv_id) {
-+				data->vddc_leakage.actual_voltage
-+				[data->vddc_leakage.count] = vddc;
-+				data->vddc_leakage.leakage_id
-+				[data->vddc_leakage.count] = vv_id;
-+				data->vddc_leakage.count++;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * Change virtual leakage voltage to actual value.
-+ *
-+ * @param     hwmgr  the address of the powerplay hardware manager.
-+ * @param     pointer to changing voltage
-+ * @param     pointer to leakage table
-+ */
-+static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
-+		uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
-+{
-+	uint32_t index;
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 */
-+	for (index = 0; index < leakage_table->count; index++) {
-+		/* if this voltage matches a leakage voltage ID */
-+		/* patch with actual leakage voltage */
-+		if (leakage_table->leakage_id[index] == *voltage) {
-+			*voltage = leakage_table->actual_voltage[index];
-+			break;
-+		}
-+	}
-+
-+	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
-+		printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
-+}
-+
-+/**
-+* Patch voltage lookup table by EVV leakages.
-+*
-+* @param     hwmgr  the address of the powerplay hardware manager.
-+* @param     pointer to voltage lookup table
-+* @param     pointer to leakage table
-+* @return     always 0
-+*/
-+static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table,
-+		struct fiji_leakage_voltage *leakage_table)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < lookup_table->count; i++)
-+		fiji_patch_with_vdd_leakage(hwmgr,
-+				&lookup_table->entries[i].us_vdd, leakage_table);
-+
-+	return 0;
-+}
-+
-+static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
-+		struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
-+		uint16_t *vddc)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
-+			table_info->max_clock_voltage_on_dc.vddc;
-+	return 0;
-+}
-+
-+static int fiji_patch_voltage_dependency_tables_with_lookup_table(
-+		struct pp_hwmgr *hwmgr)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	for (entryId = 0; entryId < sclk_table->count; ++entryId) {
-+		voltageId = sclk_table->entries[entryId].vddInd;
-+		sclk_table->entries[entryId].vddc =
-+				table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mclk_table->count; ++entryId) {
-+		voltageId = mclk_table->entries[entryId].vddInd;
-+		mclk_table->entries[entryId].vddc =
-+			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mm_table->count; ++entryId) {
-+		voltageId = mm_table->entries[entryId].vddcInd;
-+		mm_table->entries[entryId].vddc =
-+			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	return 0;
-+
-+}
-+
-+static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	/* Need to determine if we need calculated voltage. */
-+	return 0;
-+}
-+
-+static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
-+{
-+	/* Need to determine if we need calculated voltage from mm table. */
-+	return 0;
-+}
-+
-+static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
-+{
-+	uint32_t table_size, i, j;
-+	struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
-+	table_size = lookup_table->count;
-+
-+	PP_ASSERT_WITH_CODE(0 != lookup_table->count,
-+		"Lookup table is empty", return -EINVAL);
-+
-+	/* Sorting voltages */
-+	for (i = 0; i < table_size - 1; i++) {
-+		for (j = i + 1; j > 0; j--) {
-+			if (lookup_table->entries[j].us_vdd <
-+					lookup_table->entries[j - 1].us_vdd) {
-+				tmp_voltage_lookup_record = lookup_table->entries[j - 1];
-+				lookup_table->entries[j - 1] = lookup_table->entries[j];
-+				lookup_table->entries[j] = tmp_voltage_lookup_record;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	int tmp_result;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
-+			table_info->vddc_lookup_table, &(data->vddc_leakage));
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
-+			&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
-+	if(tmp_result)
-+		result = tmp_result;
-+
-+	return result;
-+}
-+
-+static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-+		"VDD dependency on SCLK table is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-+		"VDD dependency on SCLK table has to have is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-+		"VDD dependency on MCLK table is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
-+		"VDD dependency on MCLK table has to have is missing.	 \
-+		This table is mandatory", return -EINVAL);
-+
-+	data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
-+	data->max_vddc_in_pptable =	(uint16_t)allowed_sclk_vdd_table->
-+			entries[allowed_sclk_vdd_table->count - 1].vddc;
-+
-+	table_info->max_clock_voltage_on_ac.sclk =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
-+	table_info->max_clock_voltage_on_ac.mclk =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
-+	table_info->max_clock_voltage_on_ac.vddc =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
-+	table_info->max_clock_voltage_on_ac.vddci =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
-+
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
-+		table_info->max_clock_voltage_on_ac.sclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
-+		table_info->max_clock_voltage_on_ac.mclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
-+		table_info->max_clock_voltage_on_ac.vddc;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
-+		table_info->max_clock_voltage_on_ac.vddci;
-+
-+	return 0;
-+}
-+
-+static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t speedCntl = 0;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
-+			ixPCIE_LC_SPEED_CNTL);
-+	return((uint16_t)PHM_GET_FIELD(speedCntl,
-+			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
-+}
-+
-+static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t link_width;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
-+			PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
-+
-+	PP_ASSERT_WITH_CODE((7 >= link_width),
-+			"Invalid PCIe lane width!", return 0);
-+
-+	return decode_pcie_lane_width(link_width);
-+}
-+
-+/** Patch the Boot State to match VBIOS boot clocks and voltage.
-+*
-+* @param hwmgr Pointer to the hardware manager.
-+* @param pPowerState The address of the PowerState instance being created.
-+*
-+*/
-+static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
-+		struct pp_hw_power_state *hw_ps)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
-+	ATOM_FIRMWARE_INFO_V2_2 *fw_info;
-+	uint16_t size;
-+	uint8_t frev, crev;
-+	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-+
-+	/* First retrieve the Boot clocks and VDDC from the firmware info table.
-+	 * We assume here that fw_info is unchanged if this call fails.
-+	 */
-+	fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
-+			hwmgr->device, index,
-+			&size, &frev, &crev);
-+	if (!fw_info)
-+		/* During a test, there is no firmware info table. */
-+		return 0;
-+
-+	/* Patch the state. */
-+	data->vbios_boot_state.sclk_bootup_value =
-+			le32_to_cpu(fw_info->ulDefaultEngineClock);
-+	data->vbios_boot_state.mclk_bootup_value =
-+			le32_to_cpu(fw_info->ulDefaultMemoryClock);
-+	data->vbios_boot_state.mvdd_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
-+	data->vbios_boot_state.vddc_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpVDDCVoltage);
-+	data->vbios_boot_state.vddci_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
-+	data->vbios_boot_state.pcie_gen_bootup_value =
-+			fiji_get_current_pcie_speed(hwmgr);
-+	data->vbios_boot_state.pcie_lane_bootup_value =
-+			(uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
-+
-+	/* set boot power state */
-+	ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
-+	ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
-+	ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
-+	ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
-+
-+	return 0;
-+}
-+
-+static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t i;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	bool stay_in_boot;
-+	int result;
-+
-+	data->dll_default_on = false;
-+	data->sram_end = SMC_RAM_END;
-+
-+	for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
-+		data->activity_target[i] = FIJI_AT_DFLT;
-+
-+	data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
-+
-+	data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
-+	data->mclk_dpm0_activity_target = 0xa;
-+
-+	data->sclk_dpm_key_disabled = 0;
-+	data->mclk_dpm_key_disabled = 0;
-+	data->pcie_dpm_key_disabled = 0;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_UnTabledHardwareInterface);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TablelessHardwareInterface);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep);
-+
-+	data->gpio_debug = 0;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DynamicPatchPowerState);
-+
-+	/* need to set voltage control types before EVV patching */
-+	data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
-+	data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
-+	data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
-+
-+	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
-+		data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableMVDDControl))
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
-+			data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
-+
-+	if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableMVDDControl);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ControlVDDCI)) {
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
-+			data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
-+		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
-+			data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ControlVDDCI);
-+
-+	if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+
-+	fiji_init_dpm_defaults(hwmgr);
-+
-+	/* Get leakage voltage based on leakage ID. */
-+	fiji_get_evv_voltages(hwmgr);
-+
-+	/* Patch our voltage dependency table with actual leakage voltage
-+	 * We need to perform leakage translation before it's used by other functions
-+	 */
-+	fiji_complete_dependency_tables(hwmgr);
-+
-+	/* Parse pptable data read from VBIOS */
-+	fiji_set_private_data_based_on_pptable(hwmgr);
-+
-+	/* ULV Support */
-+	data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
-+
-+	/* Initalize Dynamic State Adjustment Rule Settings */
-+	result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
-+
-+	if (!result) {
-+		data->uvd_enabled = false;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EnableSMU7ThermalManagement);
-+		data->vddc_phase_shed_control = false;
-+	}
-+
-+	stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StayInBootState);
-+
-+	if (0 == result) {
-+		data->is_tlu_enabled = 0;
-+		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
-+				FIJI_MAX_HARDWARE_POWERLEVELS;
-+		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
-+		hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
-+
-+		data->pcie_gen_cap = 0x30007;
-+		data->pcie_lane_cap = 0x2f0000;
-+	} else {
-+		/* Ignore return value in here, we are cleaning up a mess. */
-+		tonga_hwmgr_backend_fini(hwmgr);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Read clock related registers.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_SPLL_FUNC_CNTL);
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_SPLL_FUNC_CNTL_2);
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_SPLL_FUNC_CNTL_3);
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_SPLL_FUNC_CNTL_4);
-+	data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_SPLL_SPREAD_SPECTRUM);
-+	data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
-+		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_SPLL_SPREAD_SPECTRUM_2);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Find out if memory is GDDR5.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t temp;
-+
-+	temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
-+
-+	data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
-+			((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
-+			 MC_SEQ_MISC0_GDDR5_SHIFT));
-+
-+	return 0;
-+}
-+
-+/**
-+ * Enables Dynamic Power Management by SMC
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			GENERAL_PWRMGT, STATIC_PM_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initialize PowerGating States for different engines
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+	data->samu_power_gated = false;
-+	data->acp_power_gated = false;
-+	data->pg_acp_init = true;
-+
-+	return 0;
-+}
-+
-+static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	data->low_sclk_interrupt_threshold = 0;
-+
-+	return 0;
-+}
-+
-+static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = fiji_read_clock_registers(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to read clock registers!", result = tmp_result);
-+
-+	tmp_result = fiji_get_memory_type(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to get memory type!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_acpi_power_management(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable ACPI power management!", result = tmp_result);
-+
-+	tmp_result = fiji_init_power_gate_state(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to init power gate state!", result = tmp_result);
-+
-+	tmp_result = tonga_get_mc_microcode_version(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to get MC microcode version!", result = tmp_result);
-+
-+	tmp_result = fiji_init_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to init sclk threshold!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+/**
-+* Checks if we want to support voltage control
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*/
-+static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
-+{
-+	const struct fiji_hwmgr *data =
-+			(const struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
-+}
-+
-+/**
-+* Enable voltage control
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
-+{
-+	/* enable voltage control */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Remove repeated voltage values and create table with unique values.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    vol_table  the pointer to changing voltage table
-+* @return    0 in success
-+*/
-+
-+static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
-+		struct pp_atomctrl_voltage_table *vol_table)
-+{
-+	uint32_t i, j;
-+	uint16_t vvalue;
-+	bool found = false;
-+	struct pp_atomctrl_voltage_table *table;
-+
-+	PP_ASSERT_WITH_CODE((NULL != vol_table),
-+			"Voltage Table empty.", return -EINVAL);
-+	table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
-+			GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -EINVAL;
-+
-+	table->mask_low = vol_table->mask_low;
-+	table->phase_delay = vol_table->phase_delay;
-+
-+	for (i = 0; i < vol_table->count; i++) {
-+		vvalue = vol_table->entries[i].value;
-+		found = false;
-+
-+		for (j = 0; j < table->count; j++) {
-+			if (vvalue == table->entries[j].value) {
-+				found = true;
-+				break;
-+			}
-+		}
-+
-+		if (!found) {
-+			table->entries[table->count].value = vvalue;
-+			table->entries[table->count].smio_low =
-+					vol_table->entries[i].smio_low;
-+			table->count++;
-+		}
-+	}
-+
-+	memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
-+	kfree(table);
-+
-+    return 0;
-+}
-+static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-+{
-+	uint32_t i;
-+	int result;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
-+
-+	PP_ASSERT_WITH_CODE((0 != dep_table->count),
-+			"Voltage Dependency Table empty.", return -EINVAL);
-+
-+	vol_table->mask_low = 0;
-+	vol_table->phase_delay = 0;
-+	vol_table->count = dep_table->count;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		vol_table->entries[i].value = dep_table->entries[i].mvdd;
-+		vol_table->entries[i].smio_low = 0;
-+	}
-+
-+	result = fiji_trim_voltage_table(hwmgr, vol_table);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to trim MVDD table.", return result);
-+
-+	return 0;
-+}
-+
-+static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-+{
-+	uint32_t i;
-+	int result;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
-+
-+	PP_ASSERT_WITH_CODE((0 != dep_table->count),
-+			"Voltage Dependency Table empty.", return -EINVAL);
-+
-+	vol_table->mask_low = 0;
-+	vol_table->phase_delay = 0;
-+	vol_table->count = dep_table->count;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		vol_table->entries[i].value = dep_table->entries[i].vddci;
-+		vol_table->entries[i].smio_low = 0;
-+	}
-+
-+	result = fiji_trim_voltage_table(hwmgr, vol_table);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to trim VDDCI table.", return result);
-+
-+	return 0;
-+}
-+
-+static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table)
-+{
-+	int i = 0;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
-+
-+	PP_ASSERT_WITH_CODE((0 != lookup_table->count),
-+			"Voltage Lookup Table empty.", return -EINVAL);
-+
-+	vol_table->mask_low = 0;
-+	vol_table->phase_delay = 0;
-+
-+	vol_table->count = lookup_table->count;
-+
-+	for (i = 0; i < vol_table->count; i++) {
-+		vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
-+		vol_table->entries[i].smio_low = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+/* ---- Voltage Tables ----
-+ * If the voltage table would be bigger than
-+ * what will fit into the state table on
-+ * the SMC keep only the higher entries.
-+ */
-+static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
-+		uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
-+{
-+	unsigned int i, diff;
-+
-+	if (vol_table->count <= max_vol_steps)
-+		return;
-+
-+	diff = vol_table->count - max_vol_steps;
-+
-+	for (i = 0; i < max_vol_steps; i++)
-+		vol_table->entries[i] = vol_table->entries[i + diff];
-+
-+	vol_table->count = max_vol_steps;
-+
-+	return;
-+}
-+
-+/**
-+* Create Voltage Tables.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	int result;
-+
-+	if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC,	VOLTAGE_OBJ_GPIO_LUT,
-+				&(data->mvdd_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve MVDD table.",
-+				return result);
-+	} else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
-+				table_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 MVDD table from dependancy table.",
-+				return result;);
-+	}
-+
-+	if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
-+				&(data->vddci_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve VDDCI table.",
-+				return result);
-+	} else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		result = fiji_get_svi2_vddci_voltage_table(hwmgr,
-+				table_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 VDDCI table from dependancy table.",
-+				return result);
-+	}
-+
-+	if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		result = fiji_get_svi2_vdd_voltage_table(hwmgr,
-+				table_info->vddc_lookup_table);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 VDDC table from lookup table.",
-+				return result);
-+	}
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
-+			"Too many voltage values for VDDC. Trimming to fit state table.",
-+			fiji_trim_voltage_table_to_fit_state_table(hwmgr,
-+					SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
-+			"Too many voltage values for VDDCI. Trimming to fit state table.",
-+			fiji_trim_voltage_table_to_fit_state_table(hwmgr,
-+					SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
-+			"Too many voltage values for MVDD. Trimming to fit state table.",
-+			fiji_trim_voltage_table_to_fit_state_table(hwmgr,
-+					SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
-+
-+    return 0;
-+}
-+
-+static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	/* Program additional LP registers
-+	 * that are no longer programmed by VBIOS
-+	 */
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs static screed detection parameters
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int fiji_program_static_screen_threshold_parameters(
-+		struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	/* Set static screen threshold unit */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
-+			data->static_screen_threshold_unit);
-+	/* Set static screen threshold */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
-+			data->static_screen_threshold);
-+
-+    return 0;
-+}
-+
-+/**
-+* Setup display gap for glitch free memory clock switching.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t displayGap =
-+			cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixCG_DISPLAY_GAP_CNTL);
-+
-+	displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP, DISPLAY_GAP_IGNORE);
-+
-+	displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_DISPLAY_GAP_CNTL, displayGap);
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs activity state transition voting clients
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	/* Clear reset for voting clients before enabling DPM */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
-+
-+	return 0;
-+}
-+
-+/**
-+* Get the location of various tables inside the FW image.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, DpmTable),
-+			&tmp, data->sram_end);
-+
-+	if (0 == result)
-+		data->dpm_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, SoftRegisters),
-+			&tmp, data->sram_end);
-+
-+	if (!result) {
-+		data->soft_regs_start = tmp;
-+		smu_data->soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, mcRegisterTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->mc_reg_table_start = tmp;
-+
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, FanTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->fan_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->arb_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, Version),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (0 != result);
-+
-+    return error ? -1 : 0;
-+}
-+
-+/* Copy one arb setting to another and then switch the active set.
-+ * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
-+ */
-+static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
-+		uint32_t arb_src, uint32_t arb_dest)
-+{
-+	uint32_t mc_arb_dram_timing;
-+	uint32_t mc_arb_dram_timing2;
-+	uint32_t burst_time;
-+	uint32_t mc_cg_config;
-+
-+	switch (arb_src) {
-+	case MC_CG_ARB_FREQ_F0:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+		break;
-+	case MC_CG_ARB_FREQ_F1:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (arb_dest) {
-+	case MC_CG_ARB_FREQ_F0:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
-+		break;
-+	case MC_CG_ARB_FREQ_F1:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+    mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
-+    mc_cg_config |= 0x0000000F;
-+    cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
-+    PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
-+
-+    return 0;
-+}
-+
-+/**
-+* Initial switch from ARB F0->F1
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+* This function is to be called from the SetPowerState table.
-+*/
-+static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
-+{
-+	return fiji_copy_and_switch_arb_sets(hwmgr,
-+			MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
-+}
-+
-+static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
-+		struct fiji_single_dpm_table *dpm_table, uint32_t count)
-+{
-+	int i;
-+	PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
-+			"Fatal error, can not set up single DPM table entries "
-+			"to exceed max number!",);
-+
-+	dpm_table->count = count;
-+	for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
-+		dpm_table->dpm_levels[i].enabled = false;
-+
-+	return 0;
-+}
-+
-+static void fiji_setup_pcie_table_entry(
-+	struct fiji_single_dpm_table *dpm_table,
-+	uint32_t index, uint32_t pcie_gen,
-+	uint32_t pcie_lanes)
-+{
-+	dpm_table->dpm_levels[index].value = pcie_gen;
-+	dpm_table->dpm_levels[index].param1 = pcie_lanes;
-+	dpm_table->dpm_levels[index].enabled = 1;
-+}
-+
-+static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint32_t i, max_entry;
-+
-+	PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
-+			data->use_pcie_power_saving_levels), "No pcie performance levels!",
-+			return -EINVAL);
-+
-+	if (data->use_pcie_performance_levels &&
-+			!data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_power_saving = data->pcie_gen_performance;
-+		data->pcie_lane_power_saving = data->pcie_lane_performance;
-+	} else if (!data->use_pcie_performance_levels &&
-+			data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_performance = data->pcie_gen_power_saving;
-+		data->pcie_lane_performance = data->pcie_lane_power_saving;
-+	}
-+
-+	fiji_reset_single_dpm_table(hwmgr,
-+			&data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
-+
-+	if (pcie_table != NULL) {
-+		/* max_entry is used to make sure we reserve one PCIE level
-+		 * for boot level (fix for A+A PSPP issue).
-+		 * If PCIE table from PPTable have ULV entry + 8 entries,
-+		 * then ignore the last entry.*/
-+		max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
-+				SMU73_MAX_LEVELS_LINK : pcie_table->count;
-+		for (i = 1; i < max_entry; i++) {
-+			fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
-+					get_pcie_gen_support(data->pcie_gen_cap,
-+							pcie_table->entries[i].gen_speed),
-+					get_pcie_lane_support(data->pcie_lane_cap,
-+							pcie_table->entries[i].lane_width));
-+		}
-+		data->dpm_table.pcie_speed_table.count = max_entry - 1;
-+	} else {
-+		/* Hardcode Pcie Table */
-+		fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Min_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Min_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+
-+		data->dpm_table.pcie_speed_table.count = 6;
-+	}
-+	/* Populate last level for boot PCIE level, but do not increment count. */
-+	fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
-+			data->dpm_table.pcie_speed_table.count,
-+			get_pcie_gen_support(data->pcie_gen_cap,
-+					PP_Min_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap,
-+					PP_Max_PCIELane));
-+
-+	return 0;
-+}
-+
-+/*
-+ * This function is to initalize all DPM state tables
-+ * for SMU7 based on the dependency table.
-+ * Dynamic state patching function will then trim these
-+ * state tables to the allowed range based
-+ * on the power policy or external client requests,
-+ * such as UVD request, etc.
-+ */
-+static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i;
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
-+			"SCLK dependency table is missing. This table is mandatory",
-+			return -EINVAL);
-+	PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
-+			"SCLK dependency table has to have is missing. "
-+			"This table is mandatory",
-+			return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
-+			"MCLK dependency table is missing. This table is mandatory",
-+			return -EINVAL);
-+	PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
-+			"MCLK dependency table has to have is missing. "
-+			"This table is mandatory",
-+			return -EINVAL);
-+
-+	/* clear the state table to reset everything to default */
-+	fiji_reset_single_dpm_table(hwmgr,
-+			&data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
-+	fiji_reset_single_dpm_table(hwmgr,
-+			&data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
-+
-+	/* Initialize Sclk DPM table based on allow Sclk values */
-+	data->dpm_table.sclk_table.count = 0;
-+	for (i = 0; i < dep_sclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.sclk_table.dpm_levels
-+				[data->dpm_table.sclk_table.count - 1].value !=
-+						dep_sclk_table->entries[i].clk) {
-+			data->dpm_table.sclk_table.dpm_levels
-+			[data->dpm_table.sclk_table.count].value =
-+					dep_sclk_table->entries[i].clk;
-+			data->dpm_table.sclk_table.dpm_levels
-+			[data->dpm_table.sclk_table.count].enabled =
-+					(i == 0) ? true : false;
-+			data->dpm_table.sclk_table.count++;
-+		}
-+	}
-+
-+	/* Initialize Mclk DPM table based on allow Mclk values */
-+	data->dpm_table.mclk_table.count = 0;
-+	for (i=0; i<dep_mclk_table->count; i++) {
-+		if ( i==0 || data->dpm_table.mclk_table.dpm_levels
-+				[data->dpm_table.mclk_table.count - 1].value !=
-+						dep_mclk_table->entries[i].clk) {
-+			data->dpm_table.mclk_table.dpm_levels
-+			[data->dpm_table.mclk_table.count].value =
-+					dep_mclk_table->entries[i].clk;
-+			data->dpm_table.mclk_table.dpm_levels
-+			[data->dpm_table.mclk_table.count].enabled =
-+					(i == 0) ? true : false;
-+			data->dpm_table.mclk_table.count++;
-+		}
-+	}
-+
-+	/* setup PCIE gen speed levels */
-+	fiji_setup_default_pcie_table(hwmgr);
-+
-+	/* save a copy of the default DPM table */
-+	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
-+			sizeof(struct fiji_dpm_table));
-+
-+	return 0;
-+}
-+
-+/**
-+ * @brief PhwFiji_GetVoltageOrder
-+ *  Returns index of requested voltage record in lookup(table)
-+ * @param lookup_table - lookup list to search in
-+ * @param voltage - voltage to look for
-+ * @return 0 on success
-+ */
-+uint8_t fiji_get_voltage_index(
-+		struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
-+{
-+	uint8_t count = (uint8_t) (lookup_table->count);
-+	uint8_t i;
-+
-+	PP_ASSERT_WITH_CODE((NULL != lookup_table),
-+			"Lookup Table empty.", return 0);
-+	PP_ASSERT_WITH_CODE((0 != count),
-+			"Lookup Table empty.", return 0);
-+
-+	for (i = 0; i < lookup_table->count; i++) {
-+		/* find first voltage equal or bigger than requested */
-+		if (lookup_table->entries[i].us_vdd >= voltage)
-+			return i;
-+	}
-+	/* voltage is bigger than max voltage in the table */
-+	return i - 1;
-+}
-+
-+/**
-+* Preparation of vddc and vddgfx CAC tables for SMC.
-+*
-+* @param    hwmgr  the address of the hardware manager
-+* @param    table  the SMC DPM table structure to be populated
-+* @return   always 0
-+*/
-+static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index;
-+	int result = 0;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
-+			table_info->vddc_lookup_table;
-+	/* tables is already swapped, so in order to use the value from it,
-+	 * we need to swap it back.
-+	 * We are populating vddc CAC data to BapmVddc table
-+	 * in split and merged mode
-+	 */
-+	for( count = 0; count<lookup_table->count; count++) {
-+		index = fiji_get_voltage_index(lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
-+				(lookup_table->entries[index].us_cac_low *
-+						VOLTAGE_SCALE)) / 25);
-+		table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
-+				(lookup_table->entries[index].us_cac_high *
-+						VOLTAGE_SCALE)) / 25);
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+* Preparation of voltage tables for SMC.
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    table   the SMC DPM table structure to be populated
-+* @return   always  0
-+*/
-+
-+int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	int result;
-+
-+	result = fiji_populate_cac_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate CAC voltage tables to SMC",
-+			return -EINVAL);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_Ulv *state)
-+{
-+	int result = 0;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
-+	state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
-+			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
-+
-+	state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
-+
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+		CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+		CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	return fiji_populate_ulv_level(hwmgr, &table->Ulv);
-+}
-+
-+static int32_t fiji_get_dpm_level_enable_mask_value(
-+		struct fiji_single_dpm_table* dpm_table)
-+{
-+	int32_t i;
-+	int32_t mask = 0;
-+
-+	for (i = dpm_table->count; i > 0; i--) {
-+		mask = mask << 1;
-+		if (dpm_table->dpm_levels[i - 1].enabled)
-+			mask |= 0x1;
-+		else
-+			mask &= 0xFFFFFFFE;
-+	}
-+	return mask;
-+}
-+
-+static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_dpm_table *dpm_table = &data->dpm_table;
-+	int i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count)
-+	 * is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
-+				dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity = 1;
-+		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	data->smc_state_table.LinkLevelCount =
-+			(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+/**
-+* Calculates the SCLK dividers using the provided engine clock
-+*
-+* @param    hwmgr  the address of the hardware manager
-+* @param    clock  the engine clock to use to populate the structure
-+* @param    sclk   the SMC SCLK structure to be populated
-+*/
-+static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
-+{
-+	const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t ref_clock;
-+	uint32_t ref_divider;
-+	uint32_t fbdiv;
-+	int result;
-+
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error retrieving Engine Clock dividers from VBIOS.",
-+			return result);
-+
-+	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
-+	ref_clock = atomctrl_get_reference_clock(hwmgr);
-+	ref_divider = 1 + dividers.uc_pll_ref_div;
-+
-+	/* low 14 bits is fraction and high 12 bits is divider */
-+	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-+
-+	/* SPLL_FUNC_CNTL setup */
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_REF_DIV, dividers.uc_pll_ref_div);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_PDIV_A,  dividers.uc_pll_post_div);
-+
-+	/* SPLL_FUNC_CNTL_3 setup*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
-+			SPLL_FB_DIV, fbdiv);
-+
-+	/* set to use fractional accumulation*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
-+			SPLL_DITHEN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
-+		struct pp_atomctrl_internal_ss_info ssInfo;
-+
-+		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
-+		if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
-+				vco_freq, &ssInfo)) {
-+			/*
-+			 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
-+			 * ss_info.speed_spectrum_rate -- in unit of khz
-+			 *
-+			 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
-+			 */
-+			uint32_t clk_s = ref_clock * 5 /
-+					(ref_divider * ssInfo.speed_spectrum_rate);
-+			/* clkv = 2 * D * fbdiv / NS */
-+			uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
-+					fbdiv / (clk_s * 10000);
-+
-+			cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
-+					CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
-+			cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
-+					CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
-+			cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
-+					CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
-+		}
-+	}
-+
-+	sclk->SclkFrequency        = clock;
-+	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
-+	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
-+	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
-+	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-+	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
-+
-+	return 0;
-+}
-+
-+static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
-+{
-+	uint32_t  i;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_voltage_table *vddci_table =
-+			&(data->vddci_voltage_table);
-+
-+	for (i = 0; i < vddci_table->count; i++) {
-+		if (vddci_table->entries[i].value >= vddci)
-+			return vddci_table->entries[i].value;
-+	}
-+
-+	PP_ASSERT_WITH_CODE(false,
-+			"VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
-+			return vddci_table->entries[i].value);
-+}
-+
-+static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
-+		uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i;
-+	uint16_t vddci;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	*voltage = *mvdd = 0;
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (dep_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (dep_table->entries[i].clk >= clock) {
-+			*voltage |= (dep_table->entries[i].vddc *
-+					VOLTAGE_SCALE) << VDDC_SHIFT;
-+			if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else if (dep_table->entries[i].vddci)
-+				*voltage |= (dep_table->entries[i].vddci *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else {
-+				vddci = fiji_find_closest_vddci(hwmgr,
-+						(dep_table->entries[i].vddc -
-+								(uint16_t)data->vddc_vddci_delta));
-+				*voltage |= (vddci * VOLTAGE_SCALE) <<	VDDCI_SHIFT;
-+			}
-+
-+			if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
-+					VOLTAGE_SCALE;
-+			else if (dep_table->entries[i].mvdd)
-+				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
-+					VOLTAGE_SCALE;
-+
-+			*voltage |= 1 << PHASES_SHIFT;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+	if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+				VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	else if (dep_table->entries[i-1].vddci) {
-+		vddci = fiji_find_closest_vddci(hwmgr,
-+				(dep_table->entries[i].vddc -
-+						(uint16_t)data->vddc_vddci_delta));
-+		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	}
-+
-+	if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
-+	else if (dep_table->entries[i].mvdd)
-+		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-+
-+	return 0;
-+}
-+/**
-+* Populates single SMC SCLK structure using the provided engine clock
-+*
-+* @param    hwmgr      the address of the hardware manager
-+* @param    clock the engine clock to use to populate the structure
-+* @param    sclk        the SMC SCLK structure to be populated
-+*/
-+
-+static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, uint16_t sclk_al_threshold,
-+		struct SMU73_Discrete_GraphicsLevel *level)
-+{
-+	int result;
-+	/* PP_Clocks minClocks; */
-+	uint32_t threshold, mvdd;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	result = fiji_calculate_sclk_params(hwmgr, clock, level);
-+
-+	/* populate graphics levels */
-+	result = fiji_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_sclk, clock,
-+			&level->MinVoltage, &mvdd);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find VDDC voltage value for "
-+			"VDDC engine clock dependency table",
-+			return result);
-+
-+	level->SclkFrequency = clock;
-+	level->ActivityLevel = sclk_al_threshold;
-+	level->CcPwrDynRm = 0;
-+	level->CcPwrDynRm1 = 0;
-+	level->EnabledForActivity = 0;
-+	level->EnabledForThrottle = 1;
-+	level->UpHyst = 10;
-+	level->DownHyst = 0;
-+	level->VoltageDownHyst = 0;
-+	level->PowerThrottle = 0;
-+
-+	threshold = clock * data->fast_watermark_threshold / 100;
-+
-+    /*
-+     * TODO: get minimum clocks from dal configaration
-+     * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
-+     */
-+    /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
-+
-+    /* get level->DeepSleepDivId
-+    if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+    {
-+        level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
-+    } */
-+
-+	/* Default to slow, highest DPM level will be
-+	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-+	 */
-+	level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-+
-+	return 0;
-+}
-+/**
-+* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
-+*
-+* @param    hwmgr      the address of the hardware manager
-+*/
-+static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_dpm_table *dpm_table = &data->dpm_table;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
-+	int result = 0;
-+	uint32_t array = data->dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
-+			SMU73_MAX_LEVELS_GRAPHICS;
-+	struct SMU73_Discrete_GraphicsLevel *levels =
-+			data->smc_state_table.GraphicsLevel;
-+	uint32_t i, max_entry;
-+	uint8_t hightest_pcie_level_enabled = 0,
-+			lowest_pcie_level_enabled = 0,
-+			mid_pcie_level_enabled = 0,
-+			count = 0;
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		result = fiji_populate_single_graphic_level(hwmgr,
-+				dpm_table->sclk_table.dpm_levels[i].value,
-+				(uint16_t)data->activity_target[i],
-+				&levels[i]);
-+		if (result)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			levels[i].DeepSleepDivId = 0;
-+	}
-+
-+	/* Only enable level 0 for now.*/
-+	levels[0].EnabledForActivity = 1;
-+
-+	/* set highest level watermark to high */
-+	levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	data->smc_state_table.GraphicsDpmLevelCount =
-+			(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
-+				"There must be 1 or more PCIE levels defined in PPTable.",
-+				return -EINVAL);
-+		max_entry = pcie_entry_cnt - 1;
-+		for (i = 0; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel =
-+					(uint8_t) ((i < max_entry)? i : max_entry);
-+	} else {
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (hightest_pcie_level_enabled + 1))) != 0 ))
-+			hightest_pcie_level_enabled++;
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << lowest_pcie_level_enabled)) == 0 ))
-+			lowest_pcie_level_enabled++;
-+
-+		while ((count < hightest_pcie_level_enabled) &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
-+			count++;
-+
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
-+				hightest_pcie_level_enabled?
-+						(lowest_pcie_level_enabled + 1 + count) :
-+						hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to hightest_pcie_level_enabled */
-+		for(i = 2; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled */
-+		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled */
-+		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change */
-+	result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, data->sram_end);
-+
-+	return result;
-+}
-+
-+/**
-+ * MCLK Frequency Ratio
-+ * SEQ_CG_RESP  Bit[31:24] - 0x0
-+ * Bit[27:24] \96 DDR3 Frequency ratio
-+ * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
-+ * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
-+ * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
-+ * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
-+ * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
-+ * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
-+ * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
-+ * 400 < 0x7 <= 450MHz,       800 < 0xF
-+ */
-+static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
-+{
-+	if (mem_clock <= 10000) return 0x0;
-+	if (mem_clock <= 15000) return 0x1;
-+	if (mem_clock <= 20000) return 0x2;
-+	if (mem_clock <= 25000) return 0x3;
-+	if (mem_clock <= 30000) return 0x4;
-+	if (mem_clock <= 35000) return 0x5;
-+	if (mem_clock <= 40000) return 0x6;
-+	if (mem_clock <= 45000) return 0x7;
-+	if (mem_clock <= 50000) return 0x8;
-+	if (mem_clock <= 55000) return 0x9;
-+	if (mem_clock <= 60000) return 0xa;
-+	if (mem_clock <= 65000) return 0xb;
-+	if (mem_clock <= 70000) return 0xc;
-+	if (mem_clock <= 75000) return 0xd;
-+	if (mem_clock <= 80000) return 0xe;
-+	/* mem_clock > 800MHz */
-+	return 0xf;
-+}
-+
-+/**
-+* Populates the SMC MCLK structure using the provided memory clock
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    clock   the memory clock to use to populate the structure
-+* @param    sclk    the SMC SCLK structure to be populated
-+*/
-+static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
-+    uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
-+{
-+	struct pp_atomctrl_memory_clock_param mem_param;
-+	int result;
-+
-+	result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to get Memory PLL Dividers.",);
-+
-+	/* Save the result data to outpupt memory level structure */
-+	mclk->MclkFrequency   = clock;
-+	mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
-+	mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
-+
-+	return result;
-+}
-+
-+static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+
-+	if (table_info->vdd_dep_on_mclk) {
-+		result = fiji_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk, clock,
-+				&mem_level->MinVoltage, &mem_level->MinMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find MinVddc voltage value from memory "
-+				"VDDC voltage dependency table", return result);
-+	}
-+
-+	mem_level->EnabledForThrottle = 1;
-+	mem_level->EnabledForActivity = 0;
-+	mem_level->UpHyst = 0;
-+	mem_level->DownHyst = 100;
-+	mem_level->VoltageDownHyst = 0;
-+	mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	mem_level->StutterEnable = false;
-+
-+	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	/* enable stutter mode if all the follow condition applied
-+	 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
-+	 * &(data->DisplayTiming.numExistingDisplays));
-+	 */
-+	data->display_timing.num_existing_displays = 1;
-+
-+	if ((data->mclk_stutter_mode_threshold) &&
-+		(clock <= data->mclk_stutter_mode_threshold) &&
-+		(!data->is_uvd_enabled) &&
-+		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
-+				STUTTER_ENABLE) & 0x1))
-+		mem_level->StutterEnable = true;
-+
-+	result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
-+	}
-+	return result;
-+}
-+
-+/**
-+* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
-+*
-+* @param    hwmgr      the address of the hardware manager
-+*/
-+static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t array = data->dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
-+	uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
-+			SMU73_MAX_LEVELS_MEMORY;
-+	struct SMU73_Discrete_MemoryLevel *levels =
-+			data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+				"can not populate memory level as memory clock is zero",
-+				return -EINVAL);
-+		result = fiji_populate_single_memory_level(hwmgr,
-+				dpm_table->mclk_table.dpm_levels[i].value,
-+				&levels[i]);
-+		if (result)
-+			return result;
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	levels[0].EnabledForActivity = 1;
-+
-+	/* in order to prevent MC activity from stutter mode to push DPM up.
-+	 * the UVD change complements this by putting the MCLK in
-+	 * a higher state by default such that we are not effected by
-+	 * up threshold or and MCLK DPM latency.
-+	 */
-+	levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
-+	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-+
-+	data->smc_state_table.MemoryDpmLevelCount =
-+			(uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high */
-+	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change */
-+	result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, data->sram_end);
-+
-+	return result;
-+}
-+
-+/**
-+* Populates the SMC MVDD structure using the provided memory clock.
-+*
-+* @param    hwmgr      the address of the hardware manager
-+* @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
-+* @param    voltage     the SMC VOLTAGE structure to be populated
-+*/
-+int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
-+		uint32_t mclk, SMIO_Pattern *smio_pat)
-+{
-+	const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
-+				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
-+				"MVDD Voltage is outside the supported range.",
-+				return -EINVAL);
-+	} else
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	SMIO_Pattern vol_level;
-+	uint32_t mvdd;
-+	uint16_t us_mvdd;
-+	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-+
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0,
-+		 * already converted to SMC_UL */
-+		table->ACPILevel.SclkFrequency =
-+				data->dpm_table.sclk_table.dpm_levels[0].value;
-+		result = fiji_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_sclk,
-+				table->ACPILevel.SclkFrequency,
-+				&table->ACPILevel.MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDC voltage value "
-+				"in Clock Dependency Table",);
-+	} else {
-+		table->ACPILevel.SclkFrequency =
-+				data->vbios_boot_state.sclk_bootup_value;
-+		table->ACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
-+			table->ACPILevel.SclkFrequency,  &dividers);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error retrieving Engine Clock dividers from VBIOS.",
-+			return result);
-+
-+	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
-+	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+	table->ACPILevel.DeepSleepDivId = 0;
-+
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_PWRON, 0);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_RESET, 1);
-+	spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
-+			SCLK_MUX_SEL, 4);
-+
-+	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-+	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-+	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->dpm_table.mclk_table.dpm_levels[0].value;
-+		result = fiji_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk,
-+				table->MemoryACPILevel.MclkFrequency,
-+				&table->MemoryACPILevel.MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDCI voltage value "
-+				"in Clock Dependency Table",);
-+	} else {
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->vbios_boot_state.mclk_bootup_value;
-+		table->MemoryACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	us_mvdd = 0;
-+	if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
-+			(data->mclk_dpm_key_disabled))
-+		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	else {
-+		if (!fiji_populate_mvdd_value(hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[0].value,
-+				&vol_level))
-+			us_mvdd = vol_level.Voltage;
-+	}
-+
-+	table->MemoryACPILevel.MinMvdd =
-+			PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	table->MemoryACPILevel.ActivityLevel =
-+			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	table->MemoryACPILevel.StutterEnable = false;
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-+
-+	return result;
-+}
-+
-+static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	table->VceLevelCount = (uint8_t)(mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for(count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage |=
-+				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->VceLevel[count].MinVoltage |=
-+				((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/*retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	table->AcpLevelCount = (uint8_t)(mm_table->count);
-+	table->AcpBootLevel = 0;
-+
-+	for (count = 0; count < table->AcpLevelCount; count++) {
-+		table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
-+		table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->AcpLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for engine clock", return result);
-+
-+		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t)(mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
-+		int32_t eng_clock, int32_t mem_clock,
-+		struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
-+{
-+	uint32_t dram_timing;
-+	uint32_t dram_timing2;
-+	uint32_t burstTime;
-+	ULONG state, trrds, trrdl;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+			eng_clock, mem_clock);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
-+
-+	state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
-+	trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
-+	trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
-+	arb_regs->McArbBurstTime   = (uint8_t)burstTime;
-+	arb_regs->TRRDS            = (uint8_t)trrds;
-+	arb_regs->TRRDL            = (uint8_t)trrdl;
-+
-+	return 0;
-+}
-+
-+static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
-+	uint32_t i, j;
-+	int result = 0;
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = fiji_populate_memory_timing_parameters(hwmgr,
-+					data->dpm_table.sclk_table.dpm_levels[i].value,
-+					data->dpm_table.mclk_table.dpm_levels[j].value,
-+					&arb_regs.entries[i][j]);
-+			if (result)
-+				break;
-+		}
-+	}
-+
-+	if (!result)
-+		result = fiji_copy_bytes_to_smc(
-+				hwmgr->smumgr,
-+				data->arb_table_start,
-+				(uint8_t *)&arb_regs,
-+				sizeof(SMU73_Discrete_MCArbDramTimingTable),
-+				data->sram_end);
-+	return result;
-+}
-+
-+static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	table->UvdLevelCount = (uint8_t)(mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
-+
-+	}
-+	return result;
-+}
-+
-+static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
-+		uint32_t value, uint32_t *boot_level)
-+{
-+	int result = -EINVAL;
-+	uint32_t i;
-+
-+	for (i = 0; i < table->count; i++) {
-+		if (value == table->dpm_levels[i].value) {
-+			*boot_level = i;
-+			result = 0;
-+		}
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table */
-+	result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(table->GraphicsBootLevel));
-+
-+	result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
-+			data->vbios_boot_state.mclk_bootup_value,
-+			(uint32_t *)&(table->MemoryBootLevel));
-+
-+	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
-+			VOLTAGE_SCALE;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
-+	for (level = 0; level < count; level++) {
-+		if(table_info->vdd_dep_on_sclk->entries[level].clk >=
-+				data->vbios_boot_state.sclk_bootup_value) {
-+			data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
-+	for (level = 0; level < count; level++) {
-+		if(table_info->vdd_dep_on_mclk->entries[level].clk >=
-+				data->vbios_boot_state.mclk_bootup_value) {
-+			data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-+			volt_with_cks, value;
-+	uint16_t clock_freq_u16;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-+			volt_offset = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+
-+	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-+
-+	/* Read SMU_Eefuse to read and calculate RO and determine
-+	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
-+	 */
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (146 * 4));
-+	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (148 * 4));
-+	efuse &= 0xFF000000;
-+	efuse = efuse >> 24;
-+	efuse2 &= 0xF;
-+
-+	if (efuse2 == 1)
-+		ro = (2300 - 1350) * efuse / 255 + 1350;
-+	else
-+		ro = (2500 - 1000) * efuse / 255 + 1000;
-+
-+	if (ro >= 1660)
-+		type = 0;
-+	else
-+		type = 1;
-+
-+	/* Populate Stretch amount */
-+	data->smc_state_table.ClockStretcherAmount = stretch_amount;
-+
-+	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
-+	for (i = 0; i < sclk_table->count; i++) {
-+		data->smc_state_table.Sclk_CKS_masterEn0_7 |=
-+				sclk_table->entries[i].cks_enable << i;
-+		volt_without_cks = (uint32_t)((14041 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-+			(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-+		volt_with_cks = (uint32_t)((13946 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-+			(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
-+		if (volt_without_cks >= volt_with_cks)
-+			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
-+					sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
-+		data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
-+	}
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			STRETCH_ENABLE, 0x0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			staticEnable, 0x1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x0);
-+
-+	/* Populate CKS Lookup Table */
-+	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
-+		stretch_amount2 = 0;
-+	else if (stretch_amount == 3 || stretch_amount == 4)
-+		stretch_amount2 = 1;
-+	else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+		PP_ASSERT_WITH_CODE(false,
-+				"Stretch Amount in PPTable not supported\n",
-+				return -EINVAL);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL);
-+	value &= 0xFFC2FF87;
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-+			fiji_clock_stretcher_lookup_table[stretch_amount2][0];
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-+			fiji_clock_stretcher_lookup_table[stretch_amount2][1];
-+	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
-+			GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
-+			SclkFrequency) / 100);
-+	if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
-+			clock_freq_u16 &&
-+        fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
-+			clock_freq_u16) {
-+		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-+		value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-+		/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-+		value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-+		/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-+		value |= (fiji_clock_stretch_amount_conversion
-+				[fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
-+				 [stretch_amount]) << 3;
-+	}
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
-+			CKS_LOOKUPTableEntry[0].minFreq);
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
-+			CKS_LOOKUPTableEntry[0].maxFreq);
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-+			fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-+			(fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL, value);
-+
-+	/* Populate DDT Lookup Table */
-+	for (i = 0; i < 4; i++) {
-+		/* Assign the minimum and maximum VID stored
-+		 * in the last row of Clock Stretcher Voltage Table.
-+		 */
-+		data->smc_state_table.ClockStretcherDataTable.
-+		ClockStretcherDataTableEntry[i].minVID =
-+				(uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
-+		data->smc_state_table.ClockStretcherDataTable.
-+		ClockStretcherDataTableEntry[i].maxVID =
-+				(uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
-+		/* Loop through each SCLK and check the frequency
-+		 * to see if it lies within the frequency for clock stretcher.
-+		 */
-+		for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
-+			cks_setting = 0;
-+			clock_freq = PP_SMC_TO_HOST_UL(
-+					data->smc_state_table.GraphicsLevel[j].SclkFrequency);
-+			/* Check the allowed frequency against the sclk level[j].
-+			 *  Sclk's endianness has already been converted,
-+			 *  and it's in 10Khz unit,
-+			 *  as opposed to Data table, which is in Mhz unit.
-+			 */
-+			if (clock_freq >=
-+					(fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
-+				cks_setting |= 0x2;
-+				if (clock_freq <
-+						(fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
-+					cks_setting |= 0x1;
-+			}
-+			data->smc_state_table.ClockStretcherDataTable.
-+			ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
-+				ClockStretcherDataTable.
-+				ClockStretcherDataTableEntry[i].setting);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
-+	value &= 0xFFFFFFFE;
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-+
-+	return 0;
-+}
-+
-+/**
-+* Populates the SMC VRConfig field in DPM table.
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    table   the SMC DPM table structure to be populated
-+* @return   always 0
-+*/
-+static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint16_t config;
-+
-+	config = VR_MERGED_WITH_VDDC;
-+	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-+
-+	/* Set Vddc Voltage Controller */
-+	if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= config;
-+	} else {
-+		PP_ASSERT_WITH_CODE(false,
-+				"VDDC should be on SVI2 control in merged mode!",);
-+	}
-+	/* Set Vddci Voltage Controller */
-+	if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	}
-+	/* Set Mvdd Voltage Controller */
-+	if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		config = VR_SVI2_PLANE_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		config = VR_SMIO_PATTERN_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Initializes the SMC table and uploads it
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput  the pointer to input data (PowerState)
-+* @return   always 0
-+*/
-+static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
-+	const struct fiji_ulv_parm *ulv = &(data->ulv);
-+	uint8_t i;
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+
-+	result = fiji_setup_default_dpm_tables(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to setup default DPM tables!", return result);
-+
-+	if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
-+		fiji_populate_smc_voltage_tables(hwmgr, table);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
-+		result = fiji_populate_ulv_state(hwmgr, table);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to initialize ULV state!", return result);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
-+	}
-+
-+	result = fiji_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Link Level!", return result);
-+
-+	result = fiji_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Graphics Level!", return result);
-+
-+	result = fiji_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Memory Level!", return result);
-+
-+	result = fiji_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACPI Level!", return result);
-+
-+	result = fiji_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize VCE Level!", return result);
-+
-+	result = fiji_populate_smc_acp_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACP Level!", return result);
-+
-+	result = fiji_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize SAMU Level!", return result);
-+
-+	/* Since only the initial state is completely set up at this point
-+	 * (the other states are just copies of the boot state) we only
-+	 * need to populate the  ARB settings for the initial state.
-+	 */
-+	result = fiji_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to Write ARB settings for the initial state.", return result);
-+
-+	result = fiji_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize UVD Level!", return result);
-+
-+	result = fiji_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot Level!", return result);
-+
-+	result = fiji_populate_smc_initailial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot State!", return result);
-+
-+	result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate BAPM Parameters!", return result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = fiji_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to populate Clock Stretcher Data Table!",
-+				return result);
-+	}
-+
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+			table_info->cac_dtp_table->usTargetOperatingTemp *
-+			FIJI_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow  =
-+			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+			FIJI_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable = 1;
-+	table->MemoryInterval = 1;
-+	table->VoltageResponseTime = 0;
-+	table->PhaseResponseTime = 0;
-+	table->MemoryThermThrottleEnable = 1;
-+	table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
-+	table->PCIeGenInterval = 1;
-+
-+	result = fiji_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate VRConfig setting!", return result);
-+
-+	table->ThermGpio = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
-+		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	} else {
-+		table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
-+			&gpio_pin)) {
-+		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	/* Thermal Output GPIO */
-+	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
-+			&gpio_pin)) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+
-+		/* For porlarity read GPIOPAD_A with assigned Gpio pin
-+		 * since VBIOS will program this register to set 'inactive state',
-+		 * driver can then determine 'active state' from this and
-+		 * program SMU with correct polarity
-+		 */
-+		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
-+				(1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO */
-+		if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot) &&
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_CombinePCCWithThermalSignal))
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+	} else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
-+			data->dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, SystemFlags),
-+			(uint8_t *)&(table->SystemFlags),
-+			sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
-+			data->sram_end);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload dpm data to SMC memory!", return result);
-+
-+	return 0;
-+}
-+
-+/**
-+* Initialize the ARB DRAM timing table's index field.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/* This is a read-modify-write on the first byte of the ARB table.
-+	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
-+	 * is the field 'current'.
-+	 * This solution is ugly, but we never write the whole table only
-+	 * individual fields in it.
-+	 * In reality this field should not be in that structure
-+	 * but in a soft register.
-+	 */
-+	result = fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start, &tmp, data->sram_end);
-+
-+	if (result)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return fiji_write_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start,  tmp, data->sram_end);
-+}
-+
-+static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
-+{
-+	if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_EnableVRHotGPIOInterrupt);
-+
-+	return 0;
-+}
-+
-+static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-+			SCLK_PWRMGT_OFF, 0);
-+	return 0;
-+}
-+
-+static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_ulv_parm *ulv = &(data->ulv);
-+
-+	if (ulv->ulv_supported)
-+		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
-+
-+	return 0;
-+}
-+
-+static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep)) {
-+		if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to enable Master Deep Sleep switch failed!",
-+					return -1);
-+	} else {
-+		if (smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to disable Master Deep Sleep switch failed!",
-+					return -1);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t   val, val0, val2;
-+	uint32_t   i, cpl_cntl, cpl_threshold, mc_threshold;
-+
-+	/* enable SCLK dpm */
-+	if(!data->sclk_dpm_key_disabled)
-+		PP_ASSERT_WITH_CODE(
-+            (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
-+            "Failed to enable SCLK DPM during DPM Start Function!",
-+            return -1);
-+
-+	/* enable MCLK dpm */
-+	if(0 == data->mclk_dpm_key_disabled) {
-+		cpl_threshold = 0;
-+		mc_threshold = 0;
-+
-+		/* Read per MCD tile (0 - 7) */
-+		for (i = 0; i < 8; i++) {
-+			PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
-+			val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
-+			if (0xf0000000 != val) {
-+				/* count number of MCQ that has channel(s) enabled */
-+				cpl_threshold++;
-+				/* only harvest 3 or full 4 supported */
-+				mc_threshold = val ? 3 : 4;
-+			}
-+		}
-+		PP_ASSERT_WITH_CODE(0 != cpl_threshold,
-+				"Number of MCQ is zero!", return -EINVAL;);
-+
-+		mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
-+				LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
-+						LCAC_MC0_CNTL__MC0_ENABLE_MASK;
-+		cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
-+				LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
-+						LCAC_CPL_CNTL__CPL_ENABLE_MASK;
-+		cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixLCAC_MC0_CNTL, mc_threshold);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixLCAC_MC1_CNTL, mc_threshold);
-+		if (8 == cpl_threshold) {
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC2_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC3_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC4_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC5_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC6_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC7_CNTL, mc_threshold);
-+		}
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixLCAC_CPL_CNTL, cpl_cntl);
-+
-+		udelay(5);
-+
-+		mc_threshold = mc_threshold |
-+				(1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
-+		cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixLCAC_MC0_CNTL, mc_threshold);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixLCAC_MC1_CNTL, mc_threshold);
-+		if (8 == cpl_threshold) {
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC2_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC3_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC4_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC5_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC6_CNTL, mc_threshold);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixLCAC_MC7_CNTL, mc_threshold);
-+		}
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixLCAC_CPL_CNTL, cpl_cntl);
-+
-+		/* Program CAC_EN per MCD (0-7) Tile */
-+		val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
-+		val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
-+				MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
-+
-+		for (i = 0; i < 8; i++) {
-+			/* Enable MCD i Tile read & write */
-+			val2  = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
-+					(1 << i));
-+			cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
-+			/* Enbale CAC_ON MCD i Tile */
-+			val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
-+			val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
-+			cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
-+		}
-+		/* Set MC_CONFIG_MCD back to its default setting val0 */
-+		cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
-+
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_MCLKDPM_Enable)),
-+				"Failed to enable MCLK DPM during DPM Start Function!",
-+				return -1);
-+	}
-+	return 0;
-+}
-+
-+static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	/*enable general power management */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+			GLOBAL_PWRMGT_EN, 1);
-+	/* enable sclk deep sleep */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-+			DYNAMIC_PM_EN, 1);
-+	/* prepare for PCIE DPM */
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			data->soft_regs_start + offsetof(SMU73_SoftRegisters,
-+					VoltageChangeTimeout), 0x1000);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
-+			SWRST_COMMAND_1, RESETLC, 0x0);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_Voltage_Cntl_Enable)),
-+			"Failed to enable voltage DPM during DPM Start Function!",
-+			return -1);
-+
-+	if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
-+		printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
-+		return -1;
-+	}
-+
-+	/* enable PCIE dpm */
-+	if(!data->pcie_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_Enable)),
-+				"Failed to enable pcie DPM during DPM Start Function!",
-+				return -1);
-+	}
-+
-+    return 0;
-+}
-+
-+static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
-+		uint32_t sources)
-+{
-+	bool protection;
-+	enum DPM_EVENT_SRC src;
-+
-+	switch (sources) {
-+	default:
-+		printk(KERN_ERR "Unknown throttling event sources.");
-+		/* fall through */
-+	case 0:
-+		protection = false;
-+		/* src is unused */
-+		break;
-+	case (1 << PHM_AutoThrottleSource_Thermal):
-+		protection = true;
-+		src = DPM_EVENT_SRC_DIGITAL;
-+		break;
-+	case (1 << PHM_AutoThrottleSource_External):
-+		protection = true;
-+		src = DPM_EVENT_SRC_EXTERNAL;
-+		break;
-+	case (1 << PHM_AutoThrottleSource_External) |
-+			(1 << PHM_AutoThrottleSource_Thermal):
-+		protection = true;
-+		src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
-+		break;
-+	}
-+	/* Order matters - don't enable thermal protection for the wrong source. */
-+	if (protection) {
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
-+				DPM_EVENT_SRC, src);
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+				THERMAL_PROTECTION_DIS,
-+				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_ThermalController));
-+	} else
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+				THERMAL_PROTECTION_DIS, 1);
-+}
-+
-+static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
-+		PHM_AutoThrottleSource source)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (!(data->active_auto_throttle_sources & (1 << source))) {
-+		data->active_auto_throttle_sources |= 1 << source;
-+		fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
-+	}
-+	return 0;
-+}
-+
-+static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
-+{
-+    return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
-+}
-+
-+static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"DPM is already running right now, no need to enable DPM!",
-+			return 0);
-+
-+	if (fiji_voltage_control(hwmgr)) {
-+		tmp_result = fiji_enable_voltage_control(hwmgr);
-+		PP_ASSERT_WITH_CODE(tmp_result == 0,
-+				"Failed to enable voltage control!",
-+				result = tmp_result);
-+	}
-+
-+	if (fiji_voltage_control(hwmgr)) {
-+		tmp_result = fiji_construct_voltage_tables(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to contruct voltage tables!",
-+				result = tmp_result);
-+	}
-+
-+	tmp_result = fiji_initialize_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize MC reg table!", result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport))
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalController))
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
-+
-+	tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program static screen threshold parameters!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_enable_display_gap(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable display gap!", result = tmp_result);
-+
-+	tmp_result = fiji_program_voting_clients(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program voting clients!", result = tmp_result);
-+
-+	tmp_result = fiji_process_firmware_header(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to process firmware header!", result = tmp_result);
-+
-+	tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize switch from ArbF0 to F1!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_init_smc_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize SMC table!", result = tmp_result);
-+
-+	tmp_result = fiji_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize ARB table index!", result = tmp_result);
-+
-+	tmp_result = fiji_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to populate PM fuses!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_sclk_control(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable SCLK control!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_ulv(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable ULV!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable deep sleep master switch!", result = tmp_result);
-+
-+	tmp_result = fiji_start_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to start DPM!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_smc_cac(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable SMC CAC!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_power_containment(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable power containment!", result = tmp_result);
-+
-+	tmp_result = fiji_power_control_set_level(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to power control set level!", result = tmp_result);
-+
-+	tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable thermal auto throttle!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t level, tmp;
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+						(1 << level));
-+		}
-+	}
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+						(1 << level));
-+		}
-+	}
-+
-+	if (!data->pcie_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_ForceLevel,
-+						(1 << level));
-+		}
-+	}
-+	return 0;
-+}
-+
-+static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_clock_voltage_dependency_table *table =
-+				table_info->vddc_dep_on_dal_pwrl;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-+	enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-+	uint32_t req_vddc = 0, req_volt, i;
-+
-+	if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
-+			dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
-+		return;
-+
-+	for (i= 0; i < table->count; i++) {
-+		if (dal_power_level == table->entries[i].clk) {
-+			req_vddc = table->entries[i].v;
-+			break;
-+		}
-+	}
-+
-+	vddc_table = table_info->vdd_dep_on_sclk;
-+	for (i= 0; i < vddc_table->count; i++) {
-+		if (req_vddc <= vddc_table->entries[i].vddc) {
-+			req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-+					<< VDDC_SHIFT;
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VddC_Request, req_volt);
-+			return;
-+		}
-+	}
-+	printk(KERN_ERR "DAL requested level can not"
-+			" found a available voltage in VDDC DPM Table \n");
-+}
-+
-+static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	fiji_apply_dal_min_voltage_request(hwmgr);
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+	}
-+	return 0;
-+}
-+
-+static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (!fiji_is_dpm_running(hwmgr))
-+		return -EINVAL;
-+
-+	if (!data->pcie_dpm_key_disabled) {
-+		smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_PCIeDPM_UnForceLevel);
-+	}
-+
-+	return fiji_upload_dpmlevel_enable_mask(hwmgr);
-+}
-+
-+static uint32_t fiji_get_lowest_enabled_level(
-+		struct pp_hwmgr *hwmgr, uint32_t mask)
-+{
-+	uint32_t level = 0;
-+
-+	while(0 == (mask & (1 << level)))
-+		level++;
-+
-+	return level;
-+}
-+
-+static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data =
-+			(struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t level = 0;
-+
-+	/* Only force sclk for now */
-+	if (!data->sclk_dpm_key_disabled)
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = fiji_get_lowest_enabled_level(hwmgr,
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					(1 << level));
-+
-+	}
-+	return 0;
-+
-+}
-+static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
-+				enum amd_dpm_forced_level level)
-+{
-+	int ret = 0;
-+
-+	switch (level) {
-+	case AMD_DPM_FORCED_LEVEL_HIGH:
-+		ret = fiji_force_dpm_highest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_LOW:
-+		ret = fiji_force_dpm_lowest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_AUTO:
-+		ret = fiji_unforce_dpm_levels(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	hwmgr->dpm_level = level;
-+
-+	return ret;
-+}
-+
-+static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
-+{
-+	return sizeof(struct fiji_power_state);
-+}
-+
-+static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
-+		void *state, struct pp_power_state *power_state,
-+		void *pp_table, uint32_t classification_flag)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_power_state  *fiji_power_state =
-+			(struct fiji_power_state *)(&(power_state->hardware));
-+	struct fiji_performance_level *performance_level;
-+	ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
-+	ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
-+			(ATOM_Tonga_POWERPLAYTABLE *)pp_table;
-+	ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-+			(ATOM_Tonga_SCLK_Dependency_Table *)
-+			(((unsigned long)powerplay_table) +
-+				le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
-+	ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
-+			(ATOM_Tonga_MCLK_Dependency_Table *)
-+			(((unsigned long)powerplay_table) +
-+				le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
-+
-+	/* The following fields are not initialized here: id orderedList allStatesList */
-+	power_state->classification.ui_label =
-+			(le16_to_cpu(state_entry->usClassification) &
-+			ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
-+			ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
-+	power_state->classification.flags = classification_flag;
-+	/* NOTE: There is a classification2 flag in BIOS that is not being used right now */
-+
-+	power_state->classification.temporary_state = false;
-+	power_state->classification.to_be_deleted = false;
-+
-+	power_state->validation.disallowOnDC =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
-+					ATOM_Tonga_DISALLOW_ON_DC));
-+
-+	power_state->pcie.lanes = 0;
-+
-+	power_state->display.disableFrameModulation = false;
-+	power_state->display.limitRefreshrate = false;
-+	power_state->display.enableVariBright =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
-+					ATOM_Tonga_ENABLE_VARIBRIGHT));
-+
-+	power_state->validation.supportedPowerLevels = 0;
-+	power_state->uvd_clocks.VCLK = 0;
-+	power_state->uvd_clocks.DCLK = 0;
-+	power_state->temperatures.min = 0;
-+	power_state->temperatures.max = 0;
-+
-+	performance_level = &(fiji_power_state->performance_levels
-+			[fiji_power_state->performance_level_count++]);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
-+			"Performance levels exceeds SMC limit!",
-+			return -1);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(fiji_power_state->performance_level_count <=
-+					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
-+			"Performance levels exceeds Driver limit!",
-+			return -1);
-+
-+	/* Performance levels are arranged from low to high. */
-+	performance_level->memory_clock = mclk_dep_table->entries
-+			[state_entry->ucMemoryClockIndexLow].ulMclk;
-+	performance_level->engine_clock = sclk_dep_table->entries
-+			[state_entry->ucEngineClockIndexLow].ulSclk;
-+	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
-+			state_entry->ucPCIEGenLow);
-+	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-+			state_entry->ucPCIELaneHigh);
-+
-+	performance_level = &(fiji_power_state->performance_levels
-+			[fiji_power_state->performance_level_count++]);
-+	performance_level->memory_clock = mclk_dep_table->entries
-+			[state_entry->ucMemoryClockIndexHigh].ulMclk;
-+	performance_level->engine_clock = sclk_dep_table->entries
-+			[state_entry->ucEngineClockIndexHigh].ulSclk;
-+	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
-+			state_entry->ucPCIEGenHigh);
-+	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-+			state_entry->ucPCIELaneHigh);
-+
-+	return 0;
-+}
-+
-+static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
-+		unsigned long entry_index, struct pp_power_state *state)
-+{
-+	int result;
-+	struct fiji_power_state *ps;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	state->hardware.magic = PHM_VIslands_Magic;
-+
-+	ps = (struct fiji_power_state *)(&state->hardware);
-+
-+	result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
-+			fiji_get_pp_table_entry_callback_func);
-+
-+	/* This is the earliest time we have all the dependency table and the VBIOS boot state
-+	 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
-+	 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
-+	 */
-+	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
-+		if (dep_mclk_table->entries[0].clk !=
-+				data->vbios_boot_state.mclk_bootup_value)
-+			printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot MCLK level");
-+		if (dep_mclk_table->entries[0].vddci !=
-+				data->vbios_boot_state.vddci_bootup_value)
-+			printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot VDDCI level");
-+	}
-+
-+	/* set DC compatible flag if this state supports DC */
-+	if (!state->validation.disallowOnDC)
-+		ps->dc_compatible = true;
-+
-+	if (state->classification.flags & PP_StateClassificationFlag_ACPI)
-+		data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
-+
-+	ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
-+	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
-+
-+	if (!result) {
-+		uint32_t i;
-+
-+		switch (state->classification.ui_label) {
-+		case PP_StateUILabel_Performance:
-+			data->use_pcie_performance_levels = true;
-+
-+			for (i = 0; i < ps->performance_level_count; i++) {
-+				if (data->pcie_gen_performance.max <
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.max =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_performance.min >
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.min =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_performance.max <
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.max =
-+							ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_performance.min >
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.min =
-+							ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		case PP_StateUILabel_Battery:
-+			data->use_pcie_power_saving_levels = true;
-+
-+			for (i = 0; i < ps->performance_level_count; i++) {
-+				if (data->pcie_gen_power_saving.max <
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.max =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_power_saving.min >
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.min =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_power_saving.max <
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.max =
-+							ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_power_saving.min >
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.min =
-+							ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				struct pp_power_state  *request_ps,
-+			const struct pp_power_state *current_ps)
-+{
-+	struct fiji_power_state *fiji_ps =
-+				cast_phw_fiji_power_state(&request_ps->hardware);
-+	uint32_t sclk;
-+	uint32_t mclk;
-+	struct PP_Clocks minimum_clocks = {0};
-+	bool disable_mclk_switching;
-+	bool disable_mclk_switching_for_frame_lock;
-+	struct cgs_display_info info = {0};
-+	const struct phm_clock_and_voltage_limits *max_limits;
-+	uint32_t i;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int32_t count;
-+	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
-+
-+	data->battery_state = (PP_StateUILabel_Battery ==
-+			request_ps->classification.ui_label);
-+
-+	PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
-+				 "VI should always have 2 performance levels",);
-+
-+	max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
-+			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
-+			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
-+
-+	/* Cap clock DPM tables at DC MAX if it is in DC. */
-+	if (PP_PowerSource_DC == hwmgr->power_source) {
-+		for (i = 0; i < fiji_ps->performance_level_count; i++) {
-+			if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
-+				fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
-+			if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
-+				fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
-+		}
-+	}
-+
-+	fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
-+	fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
-+
-+	fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-+
-+	/* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState)) {
-+		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
-+		stable_pstate_sclk = (max_limits->sclk * 75) / 100;
-+
-+		for (count = table_info->vdd_dep_on_sclk->count - 1;
-+				count >= 0; count--) {
-+			if (stable_pstate_sclk >=
-+					table_info->vdd_dep_on_sclk->entries[count].clk) {
-+				stable_pstate_sclk =
-+						table_info->vdd_dep_on_sclk->entries[count].clk;
-+				break;
-+			}
-+		}
-+
-+		if (count < 0)
-+			stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
-+
-+		stable_pstate_mclk = max_limits->mclk;
-+
-+		minimum_clocks.engineClock = stable_pstate_sclk;
-+		minimum_clocks.memoryClock = stable_pstate_mclk;
-+	}
-+
-+	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
-+		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
-+
-+	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
-+		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-+
-+	fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-+
-+	if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
-+				hwmgr->platform_descriptor.overdriveLimit.engineClock),
-+				"Overdrive sclk exceeds limit",
-+				hwmgr->gfx_arbiter.sclk_over_drive =
-+						hwmgr->platform_descriptor.overdriveLimit.engineClock);
-+
-+		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
-+			fiji_ps->performance_levels[1].engine_clock =
-+					hwmgr->gfx_arbiter.sclk_over_drive;
-+	}
-+
-+	if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
-+				hwmgr->platform_descriptor.overdriveLimit.memoryClock),
-+				"Overdrive mclk exceeds limit",
-+				hwmgr->gfx_arbiter.mclk_over_drive =
-+						hwmgr->platform_descriptor.overdriveLimit.memoryClock);
-+
-+		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
-+			fiji_ps->performance_levels[1].memory_clock =
-+					hwmgr->gfx_arbiter.mclk_over_drive;
-+	}
-+
-+	disable_mclk_switching_for_frame_lock = phm_cap_enabled(
-+				    hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
-+
-+	disable_mclk_switching = (1 < info.display_count) ||
-+				    disable_mclk_switching_for_frame_lock;
-+
-+	sclk = fiji_ps->performance_levels[0].engine_clock;
-+	mclk = fiji_ps->performance_levels[0].memory_clock;
-+
-+	if (disable_mclk_switching)
-+		mclk = fiji_ps->performance_levels
-+		[fiji_ps->performance_level_count - 1].memory_clock;
-+
-+	if (sclk < minimum_clocks.engineClock)
-+		sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
-+				max_limits->sclk : minimum_clocks.engineClock;
-+
-+	if (mclk < minimum_clocks.memoryClock)
-+		mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
-+				max_limits->mclk : minimum_clocks.memoryClock;
-+
-+	fiji_ps->performance_levels[0].engine_clock = sclk;
-+	fiji_ps->performance_levels[0].memory_clock = mclk;
-+
-+	fiji_ps->performance_levels[1].engine_clock =
-+		(fiji_ps->performance_levels[1].engine_clock >=
-+				fiji_ps->performance_levels[0].engine_clock) ?
-+						fiji_ps->performance_levels[1].engine_clock :
-+						fiji_ps->performance_levels[0].engine_clock;
-+
-+	if (disable_mclk_switching) {
-+		if (mclk < fiji_ps->performance_levels[1].memory_clock)
-+			mclk = fiji_ps->performance_levels[1].memory_clock;
-+
-+		fiji_ps->performance_levels[0].memory_clock = mclk;
-+		fiji_ps->performance_levels[1].memory_clock = mclk;
-+	} else {
-+		if (fiji_ps->performance_levels[1].memory_clock <
-+				fiji_ps->performance_levels[0].memory_clock)
-+			fiji_ps->performance_levels[1].memory_clock =
-+					fiji_ps->performance_levels[0].memory_clock;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState)) {
-+		for (i = 0; i < fiji_ps->performance_level_count; i++) {
-+			fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
-+			fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
-+			fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
-+			fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	const struct fiji_power_state *fiji_ps =
-+			cast_const_phw_fiji_power_state(states->pnew_state);
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
-+	uint32_t sclk = fiji_ps->performance_levels
-+			[fiji_ps->performance_level_count - 1].engine_clock;
-+	struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
-+	uint32_t mclk = fiji_ps->performance_levels
-+			[fiji_ps->performance_level_count - 1].memory_clock;
-+	struct PP_Clocks min_clocks = {0};
-+	uint32_t i;
-+	struct cgs_display_info info = {0};
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	for (i = 0; i < sclk_table->count; i++) {
-+		if (sclk == sclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= sclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-+	else {
-+	/* TODO: Check SCLK in DAL's minimum clocks
-+	 * in case DeepSleep divider update is required.
-+	 */
-+		if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
-+			data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
-+	}
-+
-+	for (i = 0; i < mclk_table->count; i++) {
-+		if (mclk == mclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= mclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
-+
-+	return 0;
-+}
-+
-+static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
-+		const struct fiji_power_state *fiji_ps)
-+{
-+	uint32_t i;
-+	uint32_t sclk, max_sclk = 0;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_dpm_table *dpm_table = &data->dpm_table;
-+
-+	for (i = 0; i < fiji_ps->performance_level_count; i++) {
-+		sclk = fiji_ps->performance_levels[i].engine_clock;
-+		if (max_sclk < sclk)
-+			max_sclk = sclk;
-+	}
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
-+			return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
-+					dpm_table->pcie_speed_table.dpm_levels
-+					[dpm_table->pcie_speed_table.count - 1].value :
-+					dpm_table->pcie_speed_table.dpm_levels[i].value);
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_request_link_speed_change_before_state_change(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	const struct fiji_power_state *fiji_nps =
-+			cast_const_phw_fiji_power_state(states->pnew_state);
-+	const struct fiji_power_state *fiji_cps =
-+			cast_const_phw_fiji_power_state(states->pcurrent_state);
-+
-+	uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
-+	uint16_t current_link_speed;
-+
-+	if (data->force_pcie_gen == PP_PCIEGenInvalid)
-+		current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
-+	else
-+		current_link_speed = data->force_pcie_gen;
-+
-+	data->force_pcie_gen = PP_PCIEGenInvalid;
-+	data->pspp_notify_required = false;
-+	if (target_link_speed > current_link_speed) {
-+		switch(target_link_speed) {
-+		case PP_PCIEGen3:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
-+				break;
-+			data->force_pcie_gen = PP_PCIEGen2;
-+			if (current_link_speed == PP_PCIEGen2)
-+				break;
-+		case PP_PCIEGen2:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
-+				break;
-+		default:
-+			data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
-+			break;
-+		}
-+	} else {
-+		if (target_link_speed < current_link_speed)
-+			data->pspp_notify_required = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+		PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
-+				"Trying to freeze SCLK DPM when DPM is disabled",);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_FreezeLevel),
-+				"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
-+				return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		 DPMTABLE_OD_UPDATE_MCLK)) {
-+		PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
-+				"Trying to freeze MCLK DPM when DPM is disabled",);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_MCLKDPM_FreezeLevel),
-+				"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
-+				return -1);
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result = 0;
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	const struct fiji_power_state *fiji_ps =
-+			cast_const_phw_fiji_power_state(states->pnew_state);
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t sclk = fiji_ps->performance_levels
-+			[fiji_ps->performance_level_count - 1].engine_clock;
-+	uint32_t mclk = fiji_ps->performance_levels
-+			[fiji_ps->performance_level_count - 1].memory_clock;
-+	struct fiji_dpm_table *dpm_table = &data->dpm_table;
-+
-+	struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
-+	uint32_t dpm_count, clock_percent;
-+	uint32_t i;
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
-+		dpm_table->sclk_table.dpm_levels
-+		[dpm_table->sclk_table.count - 1].value = sclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_OD6PlusinACSupport) ||
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+		/* Need to do calculation based on the golden DPM table
-+		 * as the Heatmap GPU Clock axis is also based on the default values
-+		 */
-+			PP_ASSERT_WITH_CODE(
-+				(golden_dpm_table->sclk_table.dpm_levels
-+						[golden_dpm_table->sclk_table.count - 1].value != 0),
-+				"Divide by 0!",
-+				return -1);
-+			dpm_count = dpm_table->sclk_table.count < 2 ?
-+					0 : dpm_table->sclk_table.count - 2;
-+			for (i = dpm_count; i > 1; i--) {
-+				if (sclk > golden_dpm_table->sclk_table.dpm_levels
-+						[golden_dpm_table->sclk_table.count-1].value) {
-+					clock_percent =
-+						((sclk - golden_dpm_table->sclk_table.dpm_levels
-+							[golden_dpm_table->sclk_table.count-1].value) * 100) /
-+						golden_dpm_table->sclk_table.dpm_levels
-+							[golden_dpm_table->sclk_table.count-1].value;
-+
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value +
-+							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-+								clock_percent)/100;
-+
-+				} else if (golden_dpm_table->sclk_table.dpm_levels
-+						[dpm_table->sclk_table.count-1].value > sclk) {
-+					clock_percent =
-+						((golden_dpm_table->sclk_table.dpm_levels
-+						[golden_dpm_table->sclk_table.count - 1].value - sclk) *
-+								100) /
-+						golden_dpm_table->sclk_table.dpm_levels
-+							[golden_dpm_table->sclk_table.count-1].value;
-+
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value -
-+							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+				} else
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
-+		dpm_table->mclk_table.dpm_levels
-+			[dpm_table->mclk_table.count - 1].value = mclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_OD6PlusinACSupport) ||
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+
-+			PP_ASSERT_WITH_CODE(
-+					(golden_dpm_table->mclk_table.dpm_levels
-+						[golden_dpm_table->mclk_table.count-1].value != 0),
-+					"Divide by 0!",
-+					return -1);
-+			dpm_count = dpm_table->mclk_table.count < 2 ?
-+					0 : dpm_table->mclk_table.count - 2;
-+			for (i = dpm_count; i > 1; i--) {
-+				if (mclk > golden_dpm_table->mclk_table.dpm_levels
-+						[golden_dpm_table->mclk_table.count-1].value) {
-+					clock_percent = ((mclk -
-+							golden_dpm_table->mclk_table.dpm_levels
-+							[golden_dpm_table->mclk_table.count-1].value) * 100) /
-+							golden_dpm_table->mclk_table.dpm_levels
-+							[golden_dpm_table->mclk_table.count-1].value;
-+
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value +
-+							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+
-+				} else if (golden_dpm_table->mclk_table.dpm_levels
-+						[dpm_table->mclk_table.count-1].value > mclk) {
-+					clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
-+							[golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
-+									golden_dpm_table->mclk_table.dpm_levels
-+									[golden_dpm_table->mclk_table.count-1].value;
-+
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value -
-+							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+				} else
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
-+		result = fiji_populate_all_memory_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
-+		/*populate MCLK dpm table to SMU7 */
-+		result = fiji_populate_all_memory_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	return result;
-+}
-+
-+static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
-+			  struct fiji_single_dpm_table * dpm_table,
-+			     uint32_t low_limit, uint32_t high_limit)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->count; i++) {
-+		if ((dpm_table->dpm_levels[i].value < low_limit) ||
-+		    (dpm_table->dpm_levels[i].value > high_limit))
-+			dpm_table->dpm_levels[i].enabled = false;
-+		else
-+			dpm_table->dpm_levels[i].enabled = true;
-+	}
-+	return 0;
-+}
-+
-+static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
-+		const struct fiji_power_state *fiji_ps)
-+{
-+	int result = 0;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t high_limit_count;
-+
-+	PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
-+			"power state did not have any performance level",
-+			return -1);
-+
-+	high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
-+
-+	fiji_trim_single_dpm_states(hwmgr,
-+			&(data->dpm_table.sclk_table),
-+			fiji_ps->performance_levels[0].engine_clock,
-+			fiji_ps->performance_levels[high_limit_count].engine_clock);
-+
-+	fiji_trim_single_dpm_states(hwmgr,
-+			&(data->dpm_table.mclk_table),
-+			fiji_ps->performance_levels[0].memory_clock,
-+			fiji_ps->performance_levels[high_limit_count].memory_clock);
-+
-+	return result;
-+}
-+
-+static int fiji_generate_dpm_level_enable_mask(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result;
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	const struct fiji_power_state *fiji_ps =
-+			cast_const_phw_fiji_power_state(states->pnew_state);
-+
-+	result = fiji_trim_dpm_states(hwmgr, fiji_ps);
-+	if (result)
-+		return result;
-+
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
-+	data->last_mclk_dpm_enable_mask =
-+			data->dpm_level_enable_mask.mclk_dpm_enable_mask;
-+
-+	if (data->uvd_enabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
-+			data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
-+	}
-+
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+			PPSMC_MSG_VCEDPM_Enable :
-+			PPSMC_MSG_VCEDPM_Disable);
-+}
-+
-+static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	const struct fiji_power_state *fiji_nps =
-+			cast_const_phw_fiji_power_state(states->pnew_state);
-+	const struct fiji_power_state *fiji_cps =
-+			cast_const_phw_fiji_power_state(states->pcurrent_state);
-+
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (fiji_nps->vce_clks.evclk >0 &&
-+	(fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
-+		data->smc_state_table.VceBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFF00FFFF;
-+		mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState)) {
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VCEDPM_SetEnabledMask,
-+					(uint32_t)1 << data->smc_state_table.VceBootLevel);
-+
-+			fiji_enable_disable_vce_dpm(hwmgr, true);
-+		} else if (fiji_nps->vce_clks.evclk == 0 &&
-+				fiji_cps != NULL &&
-+				fiji_cps->vce_clks.evclk > 0)
-+			fiji_enable_disable_vce_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = fiji_copy_bytes_to_smc(
-+				hwmgr->smumgr,
-+				data->dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				data->sram_end);
-+	}
-+
-+	return result;
-+}
-+
-+static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return fiji_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+
-+		PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze SCLK DPM when DPM is disabled",);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+			"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
-+			return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
-+
-+		PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze MCLK DPM when DPM is disabled",);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+		    "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
-+		    return -1);
-+	}
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	return 0;
-+}
-+
-+/* Look up the voltaged based on DAL's requested level.
-+ * and then send the requested VDDC voltage to SMC
-+ */
-+static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
-+{
-+	return;
-+}
-+
-+int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	/* Apply minimum voltage based on DAL's request level */
-+	fiji_apply_dal_minimum_voltage_request(hwmgr);
-+
-+	if (0 == data->sclk_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this,
-+		 *  we should skip this message.
-+		 */
-+		if (!fiji_is_dpm_running(hwmgr))
-+			printk(KERN_ERR "[ powerplay ] "
-+					"Trying to set Enable Mask when DPM is disabled \n");
-+
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+			PP_ASSERT_WITH_CODE((0 == result),
-+				"Set Sclk Dpm enable Mask failed", return -1);
-+		}
-+	}
-+
-+	if (0 == data->mclk_dpm_key_disabled) {
-+		/* Checking if DPM is running.  If we discover hang because of this,
-+		 *  we should skip this message.
-+		 */
-+		if (!fiji_is_dpm_running(hwmgr))
-+			printk(KERN_ERR "[ powerplay ]"
-+					" Trying to set Enable Mask when DPM is disabled \n");
-+
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+			PP_ASSERT_WITH_CODE((0 == result),
-+				"Set Mclk Dpm enable Mask failed", return -1);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_notify_link_speed_change_after_state_change(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	const struct fiji_power_state *fiji_ps =
-+			cast_const_phw_fiji_power_state(states->pnew_state);
-+	uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
-+	uint8_t  request;
-+
-+	if (data->pspp_notify_required) {
-+		if (target_link_speed == PP_PCIEGen3)
-+			request = PCIE_PERF_REQ_GEN3;
-+		else if (target_link_speed == PP_PCIEGen2)
-+			request = PCIE_PERF_REQ_GEN2;
-+		else
-+			request = PCIE_PERF_REQ_GEN1;
-+
-+		if(request == PCIE_PERF_REQ_GEN1 &&
-+				fiji_get_current_pcie_speed(hwmgr) > 0)
-+			return 0;
-+
-+		if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
-+			if (PP_PCIEGen2 == target_link_speed)
-+				printk("PSPP request to switch to Gen2 from Gen3 Failed!");
-+			else
-+				printk("PSPP request to switch to Gen1 from Gen2 Failed!");
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
-+		const void *input)
-+{
-+	int tmp_result, result = 0;
-+
-+	tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to find DPM states clocks in DPM table!",
-+			result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result =
-+			fiji_request_link_speed_change_before_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to request link speed change before state change!",
-+				result = tmp_result);
-+	}
-+
-+	tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to freeze SCLK MCLK DPM!", result = tmp_result);
-+
-+	tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to populate and upload SCLK MCLK DPM levels!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to generate DPM level enabled mask!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_update_vce_dpm(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to update VCE DPM!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_update_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to update SCLK threshold!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program memory timing parameters!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to unfreeze SCLK MCLK DPM!",
-+			result = tmp_result);
-+
-+	tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to upload DPM level enabled mask!",
-+			result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result =
-+			fiji_notify_link_speed_change_after_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to notify link speed change after state change!",
-+				result = tmp_result);
-+	}
-+
-+	return result;
-+}
-+
-+static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct fiji_power_state  *fiji_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
-+
-+	if (low)
-+		return fiji_ps->performance_levels[0].engine_clock;
-+	else
-+		return fiji_ps->performance_levels
-+				[fiji_ps->performance_level_count-1].engine_clock;
-+}
-+
-+static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct fiji_power_state  *fiji_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
-+
-+	if (low)
-+		return fiji_ps->performance_levels[0].memory_clock;
-+	else
-+		return fiji_ps->performance_levels
-+				[fiji_ps->performance_level_count-1].memory_clock;
-+}
-+
-+static void fiji_print_current_perforce_level(
-+		struct pp_hwmgr *hwmgr, struct seq_file *m)
-+{
-+	uint32_t sclk, mclk;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+
-+	sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+
-+	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
-+			mclk / 100, sclk / 100);
-+}
-+
-+static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
-+	.backend_init = &fiji_hwmgr_backend_init,
-+	.backend_fini = &tonga_hwmgr_backend_fini,
-+	.asic_setup = &fiji_setup_asic_task,
-+	.dynamic_state_management_enable = &fiji_enable_dpm_tasks,
-+	.force_dpm_level = &fiji_dpm_force_dpm_level,
-+	.get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
-+	.get_power_state_size = &fiji_get_power_state_size,
-+	.get_pp_table_entry = &fiji_get_pp_table_entry,
-+	.patch_boot_state = &fiji_patch_boot_state,
-+	.apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
-+	.power_state_set = &fiji_set_power_state_tasks,
-+	.get_sclk = &fiji_dpm_get_sclk,
-+	.get_mclk = &fiji_dpm_get_mclk,
-+	.print_current_perforce_level = &fiji_print_current_perforce_level,
-+};
-+
-+int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr  *data;
-+	int ret = 0;
-+
-+	data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
-+	if (data == NULL)
-+		return -ENOMEM;
-+
-+	hwmgr->backend = data;
-+	hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
-+	hwmgr->pptable_func = &tonga_pptable_funcs;
-+	return ret;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-new file mode 100644
-index 0000000..38dbe49
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -0,0 +1,356 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _FIJI_HWMGR_H_
-+#define _FIJI_HWMGR_H_
-+
-+#include "hwmgr.h"
-+#include "smu73.h"
-+#include "smu73_discrete.h"
-+#include "ppatomctrl.h"
-+#include "fiji_ppsmc.h"
-+
-+#define FIJI_MAX_HARDWARE_POWERLEVELS	2
-+#define FIJI_AT_DFLT	30
-+
-+#define FIJI_VOLTAGE_CONTROL_NONE                   0x0
-+#define FIJI_VOLTAGE_CONTROL_BY_GPIO                0x1
-+#define FIJI_VOLTAGE_CONTROL_BY_SVID2               0x2
-+#define FIJI_VOLTAGE_CONTROL_MERGED                 0x3
-+
-+#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-+#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
-+#define DPMTABLE_UPDATE_SCLK        0x00000004
-+#define DPMTABLE_UPDATE_MCLK        0x00000008
-+
-+struct fiji_performance_level {
-+	uint32_t  memory_clock;
-+	uint32_t  engine_clock;
-+	uint16_t  pcie_gen;
-+	uint16_t  pcie_lane;
-+};
-+
-+struct fiji_uvd_clocks {
-+	uint32_t  vclk;
-+	uint32_t  dclk;
-+};
-+
-+struct fiji_vce_clocks {
-+	uint32_t  evclk;
-+	uint32_t  ecclk;
-+};
-+
-+struct fiji_power_state {
-+    uint32_t                  magic;
-+    struct fiji_uvd_clocks    uvd_clks;
-+    struct fiji_vce_clocks    vce_clks;
-+    uint32_t                  sam_clk;
-+    uint32_t                  acp_clk;
-+    uint16_t                  performance_level_count;
-+    bool                      dc_compatible;
-+    uint32_t                  sclk_threshold;
-+    struct fiji_performance_level  performance_levels[FIJI_MAX_HARDWARE_POWERLEVELS];
-+};
-+
-+struct fiji_dpm_level {
-+	bool	enabled;
-+    uint32_t	value;
-+    uint32_t	param1;
-+};
-+
-+#define FIJI_MAX_DEEPSLEEP_DIVIDER_ID 5
-+#define MAX_REGULAR_DPM_NUMBER 8
-+#define FIJI_MINIMUM_ENGINE_CLOCK 2500
-+
-+struct fiji_single_dpm_table {
-+	uint32_t		count;
-+	struct fiji_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
-+};
-+
-+struct fiji_dpm_table {
-+	struct fiji_single_dpm_table  sclk_table;
-+	struct fiji_single_dpm_table  mclk_table;
-+	struct fiji_single_dpm_table  pcie_speed_table;
-+	struct fiji_single_dpm_table  vddc_table;
-+	struct fiji_single_dpm_table  vddci_table;
-+	struct fiji_single_dpm_table  mvdd_table;
-+};
-+
-+struct fiji_clock_registers {
-+	uint32_t  vCG_SPLL_FUNC_CNTL;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t  vDLL_CNTL;
-+	uint32_t  vMCLK_PWRMGT_CNTL;
-+	uint32_t  vMPLL_AD_FUNC_CNTL;
-+	uint32_t  vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL_1;
-+	uint32_t  vMPLL_FUNC_CNTL_2;
-+	uint32_t  vMPLL_SS1;
-+	uint32_t  vMPLL_SS2;
-+};
-+
-+struct fiji_voltage_smio_registers {
-+	uint32_t vS0_VID_LOWER_SMIO_CNTL;
-+};
-+
-+#define FIJI_MAX_LEAKAGE_COUNT  8
-+struct fiji_leakage_voltage {
-+	uint16_t  count;
-+	uint16_t  leakage_id[FIJI_MAX_LEAKAGE_COUNT];
-+	uint16_t  actual_voltage[FIJI_MAX_LEAKAGE_COUNT];
-+};
-+
-+struct fiji_vbios_boot_state {
-+	uint16_t    mvdd_bootup_value;
-+	uint16_t    vddc_bootup_value;
-+	uint16_t    vddci_bootup_value;
-+	uint32_t    sclk_bootup_value;
-+	uint32_t    mclk_bootup_value;
-+	uint16_t    pcie_gen_bootup_value;
-+	uint16_t    pcie_lane_bootup_value;
-+};
-+
-+struct fiji_bacos {
-+	uint32_t                       best_match;
-+	uint32_t                       baco_flags;
-+	struct fiji_performance_level  performance_level;
-+};
-+
-+/* Ultra Low Voltage parameter structure */
-+struct fiji_ulv_parm {
-+	bool                           ulv_supported;
-+	uint32_t                       cg_ulv_parameter;
-+	uint32_t                       ulv_volt_change_delay;
-+	struct fiji_performance_level  ulv_power_level;
-+};
-+
-+struct fiji_display_timing {
-+	uint32_t  min_clock_in_sr;
-+	uint32_t  num_existing_displays;
-+};
-+
-+struct fiji_dpmlevel_enable_mask {
-+	uint32_t  uvd_dpm_enable_mask;
-+	uint32_t  vce_dpm_enable_mask;
-+	uint32_t  acp_dpm_enable_mask;
-+	uint32_t  samu_dpm_enable_mask;
-+	uint32_t  sclk_dpm_enable_mask;
-+	uint32_t  mclk_dpm_enable_mask;
-+	uint32_t  pcie_dpm_enable_mask;
-+};
-+
-+struct fiji_pcie_perf_range {
-+	uint16_t  max;
-+	uint16_t  min;
-+};
-+
-+struct fiji_hwmgr {
-+	struct fiji_dpm_table			dpm_table;
-+	struct fiji_dpm_table			golden_dpm_table;
-+
-+	uint32_t						voting_rights_clients0;
-+	uint32_t						voting_rights_clients1;
-+	uint32_t						voting_rights_clients2;
-+	uint32_t						voting_rights_clients3;
-+	uint32_t						voting_rights_clients4;
-+	uint32_t						voting_rights_clients5;
-+	uint32_t						voting_rights_clients6;
-+	uint32_t						voting_rights_clients7;
-+	uint32_t						static_screen_threshold_unit;
-+	uint32_t						static_screen_threshold;
-+	uint32_t						voltage_control;
-+	uint32_t						vddc_vddci_delta;
-+
-+	uint32_t						active_auto_throttle_sources;
-+
-+	struct fiji_clock_registers            clock_registers;
-+	struct fiji_voltage_smio_registers      voltage_smio_registers;
-+
-+	bool                           is_memory_gddr5;
-+	uint16_t                       acpi_vddc;
-+	bool                           pspp_notify_required;
-+	uint16_t                       force_pcie_gen;
-+	uint16_t                       acpi_pcie_gen;
-+	uint32_t                       pcie_gen_cap;
-+	uint32_t                       pcie_lane_cap;
-+	uint32_t                       pcie_spc_cap;
-+	struct fiji_leakage_voltage          vddc_leakage;
-+	struct fiji_leakage_voltage          Vddci_leakage;
-+
-+	uint32_t                             mvdd_control;
-+	uint32_t                             vddc_mask_low;
-+	uint32_t                             mvdd_mask_low;
-+	uint16_t                            max_vddc_in_pptable;
-+	uint16_t                            min_vddc_in_pptable;
-+	uint16_t                            max_vddci_in_pptable;
-+	uint16_t                            min_vddci_in_pptable;
-+	uint32_t                             mclk_strobe_mode_threshold;
-+	uint32_t                             mclk_stutter_mode_threshold;
-+	uint32_t                             mclk_edc_enable_threshold;
-+	uint32_t                             mclk_edcwr_enable_threshold;
-+	bool                                is_uvd_enabled;
-+	struct fiji_vbios_boot_state        vbios_boot_state;
-+
-+	bool                           battery_state;
-+	bool                           is_tlu_enabled;
-+
-+	/* ---- SMC SRAM Address of firmware header tables ---- */
-+	uint32_t                             sram_end;
-+	uint32_t                             dpm_table_start;
-+	uint32_t                             soft_regs_start;
-+	uint32_t                             mc_reg_table_start;
-+	uint32_t                             fan_table_start;
-+	uint32_t                             arb_table_start;
-+	struct SMU73_Discrete_DpmTable       smc_state_table;
-+	struct SMU73_Discrete_Ulv            ulv_setting;
-+
-+	/* ---- Stuff originally coming from Evergreen ---- */
-+	uint32_t                             vddci_control;
-+	struct pp_atomctrl_voltage_table     vddc_voltage_table;
-+	struct pp_atomctrl_voltage_table     vddci_voltage_table;
-+	struct pp_atomctrl_voltage_table     mvdd_voltage_table;
-+
-+	uint32_t                             mgcg_cgtt_local2;
-+	uint32_t                             mgcg_cgtt_local3;
-+	uint32_t                             gpio_debug;
-+	uint32_t                             mc_micro_code_feature;
-+	uint32_t                             highest_mclk;
-+	uint16_t                             acpi_vddci;
-+	uint8_t                              mvdd_high_index;
-+	uint8_t                              mvdd_low_index;
-+	bool                                 dll_default_on;
-+	bool                                 performance_request_registered;
-+
-+	/* ---- Low Power Features ---- */
-+	struct fiji_bacos                    bacos;
-+	struct fiji_ulv_parm                 ulv;
-+
-+	/* ---- CAC Stuff ---- */
-+	uint32_t                       cac_table_start;
-+	bool                           cac_configuration_required;
-+	bool                           driver_calculate_cac_leakage;
-+	bool                           cac_enabled;
-+
-+	/* ---- DPM2 Parameters ---- */
-+	uint32_t                       power_containment_features;
-+	bool                           enable_dte_feature;
-+	bool                           enable_tdc_limit_feature;
-+	bool                           enable_pkg_pwr_tracking_feature;
-+	bool                           disable_uvd_power_tune_feature;
-+	struct fiji_pt_defaults       *power_tune_defaults;
-+	struct SMU73_Discrete_PmFuses  power_tune_table;
-+	uint32_t                       dte_tj_offset;
-+	uint32_t                       fast_watermark_threshold;
-+
-+	/* ---- Phase Shedding ---- */
-+	bool                           vddc_phase_shed_control;
-+
-+	/* ---- DI/DT ---- */
-+	struct fiji_display_timing        display_timing;
-+
-+	/* ---- Thermal Temperature Setting ---- */
-+	struct fiji_dpmlevel_enable_mask     dpm_level_enable_mask;
-+	uint32_t                             need_update_smu7_dpm_table;
-+	uint32_t                             sclk_dpm_key_disabled;
-+	uint32_t                             mclk_dpm_key_disabled;
-+	uint32_t                             pcie_dpm_key_disabled;
-+	uint32_t                             min_engine_clocks;
-+	struct fiji_pcie_perf_range          pcie_gen_performance;
-+	struct fiji_pcie_perf_range          pcie_lane_performance;
-+	struct fiji_pcie_perf_range          pcie_gen_power_saving;
-+	struct fiji_pcie_perf_range          pcie_lane_power_saving;
-+	bool                                 use_pcie_performance_levels;
-+	bool                                 use_pcie_power_saving_levels;
-+	uint32_t                             activity_target[SMU73_MAX_LEVELS_GRAPHICS];
-+	uint32_t                             mclk_activity_target;
-+	uint32_t                             mclk_dpm0_activity_target;
-+	uint32_t                             low_sclk_interrupt_threshold;
-+	uint32_t                             last_mclk_dpm_enable_mask;
-+	bool                                 uvd_enabled;
-+
-+	/* ---- Power Gating States ---- */
-+	bool                           uvd_power_gated;
-+	bool                           vce_power_gated;
-+	bool                           samu_power_gated;
-+	bool                           acp_power_gated;
-+	bool                           pg_acp_init;
-+	bool                           frtc_enabled;
-+	bool                           frtc_status_changed;
-+};
-+
-+/* To convert to Q8.8 format for firmware */
-+#define FIJI_Q88_FORMAT_CONVERSION_UNIT             256
-+
-+enum Fiji_I2CLineID {
-+    Fiji_I2CLineID_DDC1 = 0x90,
-+    Fiji_I2CLineID_DDC2 = 0x91,
-+    Fiji_I2CLineID_DDC3 = 0x92,
-+    Fiji_I2CLineID_DDC4 = 0x93,
-+    Fiji_I2CLineID_DDC5 = 0x94,
-+    Fiji_I2CLineID_DDC6 = 0x95,
-+    Fiji_I2CLineID_SCLSDA = 0x96,
-+    Fiji_I2CLineID_DDCVGA = 0x97
-+};
-+
-+#define Fiji_I2C_DDC1DATA          0
-+#define Fiji_I2C_DDC1CLK           1
-+#define Fiji_I2C_DDC2DATA          2
-+#define Fiji_I2C_DDC2CLK           3
-+#define Fiji_I2C_DDC3DATA          4
-+#define Fiji_I2C_DDC3CLK           5
-+#define Fiji_I2C_SDA               40
-+#define Fiji_I2C_SCL               41
-+#define Fiji_I2C_DDC4DATA          65
-+#define Fiji_I2C_DDC4CLK           66
-+#define Fiji_I2C_DDC5DATA          0x48
-+#define Fiji_I2C_DDC5CLK           0x49
-+#define Fiji_I2C_DDC6DATA          0x4a
-+#define Fiji_I2C_DDC6CLK           0x4b
-+#define Fiji_I2C_DDCVGADATA        0x4c
-+#define Fiji_I2C_DDCVGACLK         0x4d
-+
-+#define FIJI_UNUSED_GPIO_PIN       0x7F
-+
-+extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
-+extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
-+extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
-+extern uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen);
-+extern uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes);
-+
-+#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
-+#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
-+
-+#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
-+#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
-+
-+#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
-+#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
-+
-+#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
-+
-+#endif /* _FIJI_HWMGR_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-new file mode 100644
-index 0000000..f89c98f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-@@ -0,0 +1,553 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "hwmgr.h"
-+#include "smumgr.h"
-+#include "fiji_hwmgr.h"
-+#include "fiji_powertune.h"
-+#include "fiji_smumgr.h"
-+#include "smu73_discrete.h"
-+#include "pp_debug.h"
-+
-+#define VOLTAGE_SCALE  4
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+
-+struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+		/*sviLoadLIneEn,  SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
-+		{1,               0xF,             0xFD,
-+		/* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
-+		0x19,        5,               45}
-+};
-+
-+void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *fiji_hwmgr = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct  phm_ppt_v1_information *table_info =
-+			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t tmp = 0;
-+
-+	if(table_info &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID)
-+		fiji_hwmgr->power_tune_defaults =
-+				&fiji_power_tune_data_set_array
-+				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
-+	else
-+		fiji_hwmgr->power_tune_defaults = &fiji_power_tune_data_set_array[0];
-+
-+	/* Assume disabled */
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_CAC);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SQRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DBRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TDRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TCPRamping);
-+
-+	fiji_hwmgr->dte_tj_offset = tmp;
-+
-+	if (!tmp) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_PowerContainment);
-+
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_CAC);
-+
-+		fiji_hwmgr->fast_watermark_threshold = 100;
-+
-+		tmp = 1;
-+		fiji_hwmgr->enable_dte_feature = tmp ? false : true;
-+		fiji_hwmgr->enable_tdc_limit_feature = tmp ? true : false;
-+		fiji_hwmgr->enable_pkg_pwr_tracking_feature = tmp ? true : false;
-+	}
-+}
-+
-+/* PPGen has the gain setting generated in x * 100 unit
-+ * This function is to convert the unit to x * 4096(0x1000) unit.
-+ *  This is the unit expected by SMC firmware
-+ */
-+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
-+{
-+    uint32_t tmp;
-+    tmp = raw_setting * 4096 / 100;
-+    return (uint16_t)tmp;
-+}
-+
-+static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
-+{
-+	switch (line) {
-+	case Fiji_I2CLineID_DDC1 :
-+		*scl = Fiji_I2C_DDC1CLK;
-+		*sda = Fiji_I2C_DDC1DATA;
-+		break;
-+	case Fiji_I2CLineID_DDC2 :
-+		*scl = Fiji_I2C_DDC2CLK;
-+		*sda = Fiji_I2C_DDC2DATA;
-+		break;
-+	case Fiji_I2CLineID_DDC3 :
-+		*scl = Fiji_I2C_DDC3CLK;
-+		*sda = Fiji_I2C_DDC3DATA;
-+		break;
-+	case Fiji_I2CLineID_DDC4 :
-+		*scl = Fiji_I2C_DDC4CLK;
-+		*sda = Fiji_I2C_DDC4DATA;
-+		break;
-+	case Fiji_I2CLineID_DDC5 :
-+		*scl = Fiji_I2C_DDC5CLK;
-+		*sda = Fiji_I2C_DDC5DATA;
-+		break;
-+	case Fiji_I2CLineID_DDC6 :
-+		*scl = Fiji_I2C_DDC6CLK;
-+		*sda = Fiji_I2C_DDC6DATA;
-+		break;
-+	case Fiji_I2CLineID_SCLSDA :
-+		*scl = Fiji_I2C_SCL;
-+		*sda = Fiji_I2C_SDA;
-+		break;
-+	case Fiji_I2CLineID_DDCVGA :
-+		*scl = Fiji_I2C_DDCVGACLK;
-+		*sda = Fiji_I2C_DDCVGADATA;
-+		break;
-+	default:
-+		*scl = 0;
-+		*sda = 0;
-+		break;
-+	}
-+}
-+
-+int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_pt_defaults *defaults = data->power_tune_defaults;
-+	SMU73_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	struct pp_advance_fan_control_parameters *fan_table=
-+			&hwmgr->thermal_controller.advanceFanControlParameters;
-+	uint8_t uc_scl, uc_sda;
-+
-+	/* TDP number of fraction bits are changed from 8 to 7 for Fiji
-+	 * as requested by SMC team
-+	 */
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
-+			(uint16_t)(cac_dtp_table->usTDP * 128));
-+	dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
-+			(uint16_t)(cac_dtp_table->usTDP * 128));
-+
-+	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
-+			"Target Operating Temp is out of Range!",);
-+
-+	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
-+
-+	/* The following are for new Fiji Multi-input fan/thermal control */
-+	dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTargetOperatingTemp * 256);
-+	dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitHotspot * 256);
-+	dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitLiquid1 * 256);
-+	dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitLiquid2 * 256);
-+	dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitVrVddc * 256);
-+	dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitVrMvdd * 256);
-+	dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitPlx * 256);
-+
-+	dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainEdge));
-+	dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainHotspot));
-+	dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainLiquid));
-+	dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainVrVddc));
-+	dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
-+	dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainPlx));
-+	dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainHbm));
-+
-+	dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
-+	dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
-+	dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
-+	dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
-+
-+	get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
-+	dpm_table->Liquid_I2C_LineSCL = uc_scl;
-+	dpm_table->Liquid_I2C_LineSDA = uc_sda;
-+
-+	get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
-+	dpm_table->Vr_I2C_LineSCL = uc_scl;
-+	dpm_table->Vr_I2C_LineSDA = uc_sda;
-+
-+	get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
-+	dpm_table->Plx_I2C_LineSCL = uc_scl;
-+	dpm_table->Plx_I2C_LineSDA = uc_sda;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+    struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+    struct fiji_pt_defaults *defaults = data->power_tune_defaults;
-+
-+    data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
-+    data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-+    data->power_tune_table.SviLoadLineTrimVddC = 3;
-+    data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+    return 0;
-+}
-+
-+static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct  fiji_pt_defaults *defaults = data->power_tune_defaults;
-+
-+	/* TDC number of fraction bits are changed from 8 to 7
-+	 * for Fiji as requested by SMC team
-+	 */
-+	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
-+	data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
-+	data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct  fiji_pt_defaults *defaults = data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (fiji_read_smc_sram_dword(hwmgr->smumgr,
-+			fuse_table_offset +
-+			offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, data->sram_end))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else {
-+		data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
-+		data->power_tune_table.LPMLTemperatureMin =
-+				(uint8_t)((temp >> 16) & 0xff);
-+		data->power_tune_table.LPMLTemperatureMax =
-+				(uint8_t)((temp >> 8) & 0xff);
-+		data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
-+	}
-+	return 0;
-+}
-+
-+static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if( (hwmgr->thermal_controller.advanceFanControlParameters.
-+			usFanOutputSensitivity & (1 << 15)) ||
-+			0 == hwmgr->thermal_controller.advanceFanControlParameters.
-+			usFanOutputSensitivity )
-+		hwmgr->thermal_controller.advanceFanControlParameters.
-+		usFanOutputSensitivity = hwmgr->thermal_controller.
-+			advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	data->power_tune_table.FuzzyFan_PwmSetDelta =
-+			PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
-+					advanceFanControlParameters.usFanOutputSensitivity);
-+	return 0;
-+}
-+
-+static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int fiji_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-+{
-+ /*   int  i, min, max;
-+    struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+    uint8_t * pHiVID = data->power_tune_table.BapmVddCVidHiSidd;
-+    uint8_t * pLoVID = data->power_tune_table.BapmVddCVidLoSidd;
-+
-+    min = max = pHiVID[0];
-+    for (i = 0; i < 8; i++) {
-+        if (0 != pHiVID[i]) {
-+            if (min > pHiVID[i])
-+                min = pHiVID[i];
-+            if (max < pHiVID[i])
-+                max = pHiVID[i];
-+        }
-+
-+        if (0 != pLoVID[i]) {
-+            if (min > pLoVID[i])
-+                min = pLoVID[i];
-+            if (max < pLoVID[i])
-+                max = pLoVID[i];
-+        }
-+    }
-+
-+    PP_ASSERT_WITH_CODE((0 != min) && (0 != max), "BapmVddcVidSidd table does not exist!", return int_Failed);
-+    data->power_tune_table.GnbLPMLMaxVid = (uint8_t)max;
-+    data->power_tune_table.GnbLPMLMinVid = (uint8_t)min;
-+*/
-+    return 0;
-+}
-+
-+static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint16_t HiSidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t LoSidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+
-+	HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
-+	data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
-+
-+	return 0;
-+}
-+
-+int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t pm_fuse_table_offset;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (fiji_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU73_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, data->sram_end))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to get pm_fuse_table_offset Failed!",
-+					return -EINVAL);
-+
-+		/* DW6 */
-+		if (fiji_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate SviLoadLine Failed!",
-+					return -EINVAL);
-+		/* DW7 */
-+		if (fiji_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed!", return -EINVAL);
-+		/* DW8 */
-+		if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TdcWaterfallCtl, "
-+					"LPMLTemperature Min and Max Failed!",
-+					return -EINVAL);
-+
-+		/* DW9-DW12 */
-+		if (0 != fiji_populate_temperature_scaler(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate LPMLTemperatureScaler Failed!",
-+					return -EINVAL);
-+
-+		/* DW13-DW14 */
-+		if(fiji_populate_fuzzy_fan(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate Fuzzy Fan Control parameters Failed!",
-+					return -EINVAL);
-+
-+		/* DW15-DW18 */
-+		if (fiji_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Failed!",
-+					return -EINVAL);
-+
-+		/* DW19 */
-+		if (fiji_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Min and Max Vid Failed!",
-+					return -EINVAL);
-+
-+		/* DW20 */
-+		if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
-+					"Sidd Failed!", return -EINVAL);
-+
-+		if (fiji_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
-+				(uint8_t *)&data->power_tune_table,
-+				sizeof(struct SMU73_Discrete_PmFuses), data->sram_end))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed!",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	int result = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_CAC)) {
-+		int smc_result;
-+		smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+				(uint16_t)(PPSMC_MSG_EnableCac));
-+		PP_ASSERT_WITH_CODE((0 == smc_result),
-+				"Failed to enable CAC in SMC.", result = -1);
-+
-+        data->cac_enabled = (0 == smc_result) ? true : false;
-+	}
-+	return result;
-+}
-+
-+int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if(data->power_containment_features &
-+			POWERCONTAINMENT_FEATURE_PkgPwrLimit)
-+		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_PkgPwrSetLimit, n);
-+	return 0;
-+}
-+
-+static int fiji_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
-+{
-+	return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
-+			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
-+}
-+
-+int fiji_enable_power_containment(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int smc_result;
-+	int result = 0;
-+
-+	data->power_containment_features = 0;
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (data->enable_dte_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_EnableDTE));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable DTE in SMC.", result = -1;);
-+			if (0 == smc_result)
-+				data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
-+		}
-+
-+		if (data->enable_tdc_limit_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_TDCLimitEnable));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable TDCLimit in SMC.", result = -1;);
-+			if (0 == smc_result)
-+				data->power_containment_features |=
-+						POWERCONTAINMENT_FEATURE_TDCLimit;
-+		}
-+
-+		if (data->enable_pkg_pwr_tracking_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable PkgPwrTracking in SMC.", result = -1;);
-+			if (0 == smc_result) {
-+				struct phm_cac_tdp_table *cac_table =
-+						table_info->cac_dtp_table;
-+				uint32_t default_limit =
-+					(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
-+
-+				data->power_containment_features |=
-+						POWERCONTAINMENT_FEATURE_PkgPwrLimit;
-+
-+				if (fiji_set_power_limit(hwmgr, default_limit))
-+					printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
-+			}
-+		}
-+	}
-+	return result;
-+}
-+
-+int fiji_power_control_set_level(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+	int adjust_percent, target_tdp;
-+	int result = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		/* adjustment percentage has already been validated */
-+		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
-+				hwmgr->platform_descriptor.TDPAdjustment :
-+				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
-+		/* SMC requested that target_tdp to be 7 bit fraction in DPM table
-+		 * but message to be 8 bit fraction for messages
-+		 */
-+		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
-+        result = fiji_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
-+    }
-+
-+    return result;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.h
-new file mode 100644
-index 0000000..55e5820
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.h
-@@ -0,0 +1,66 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef FIJI_POWERTUNE_H
-+#define FIJI_POWERTUNE_H
-+
-+enum fiji_pt_config_reg_type {
-+	FIJI_CONFIGREG_MMR = 0,
-+	FIJI_CONFIGREG_SMC_IND,
-+	FIJI_CONFIGREG_DIDT_IND,
-+	FIJI_CONFIGREG_CACHE,
-+	FIJI_CONFIGREG_MAX
-+};
-+
-+/* PowerContainment Features */
-+#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
-+#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
-+#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
-+
-+struct fiji_pt_config_reg {
-+	uint32_t                           offset;
-+	uint32_t                           mask;
-+	uint32_t                           shift;
-+	uint32_t                           value;
-+	enum fiji_pt_config_reg_type       type;
-+};
-+
-+struct fiji_pt_defaults
-+{
-+    uint8_t   SviLoadLineEn;
-+    uint8_t   SviLoadLineVddC;
-+    uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
-+    uint8_t   TDC_MAWt;
-+    uint8_t   TdcWaterfallCtl;
-+    uint8_t   DTEAmbientTempBase;
-+};
-+
-+void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
-+int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
-+int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr);
-+int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr);
-+int fiji_enable_power_containment(struct pp_hwmgr *hwmgr);
-+int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
-+int fiji_power_control_set_level(struct pp_hwmgr *hwmgr);
-+
-+#endif  /* FIJI_POWERTUNE_H */
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index 407b2e3..f243e40 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -30,6 +30,8 @@
- #include "cz_hwmgr.h"
- #include "tonga_hwmgr.h"
- 
-+extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
-+
- int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
- 	struct pp_hwmgr *hwmgr;
-@@ -59,6 +61,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		case CHIP_TONGA:
- 			tonga_hwmgr_init(hwmgr);
- 			break;
-+		case CHIP_FIJI:
-+			fiji_hwmgr_init(hwmgr);
-+			break;
- 		default:
- 			return -EINVAL;
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0059-drm-amdgpu-add-amdgpu.powerplay-module-option.patch b/common/recipes-kernel/linux/files/0059-drm-amdgpu-add-amdgpu.powerplay-module-option.patch
deleted file mode 100644
index 05fd5535..00000000
--- a/common/recipes-kernel/linux/files/0059-drm-amdgpu-add-amdgpu.powerplay-module-option.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From d6ab2efcf5034edeb6dff8bbf99ee174c3271152 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Tue, 21 Jul 2015 14:01:50 +0800
-Subject: [PATCH 0059/1110] drm/amdgpu: add amdgpu.powerplay module option
-
-This option can be used to enable the new powerplay implementation,
-and it is disabled by default.
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index a318356..8aedfa6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -165,6 +165,11 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
- MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))");
- module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
- 
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable (default))");
-+module_param_named(powerplay, amdgpu_powerplay, int, 0444);
-+#endif
-+
- static struct pci_device_id pciidlist[] = {
- #ifdef CONFIG_DRM_AMDGPU_CIK
- 	/* Kaveri */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0060-drm-amd-amdgpu-enable-powerplay-and-smc-firmware-loa.patch b/common/recipes-kernel/linux/files/0060-drm-amd-amdgpu-enable-powerplay-and-smc-firmware-loa.patch
deleted file mode 100644
index 241cd1b4..00000000
--- a/common/recipes-kernel/linux/files/0060-drm-amd-amdgpu-enable-powerplay-and-smc-firmware-loa.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From c815958f01589ac4bf7a14c08b45c453db56bd65 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 29 Sep 2015 14:58:53 -0400
-Subject: [PATCH 0060/1110] drm/amd/amdgpu: enable powerplay and smc firmware
- loading for Fiji.
-
-Switch over to handling in the powerplay module.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c       | 3 +++
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 3 +++
- drivers/gpu/drm/amd/amdgpu/vi.c               | 2 +-
- 3 files changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 8f758ea..a611401 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -703,6 +703,9 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
- 		case CHIP_TONGA:
- 			strcpy(fw_name, "amdgpu/tonga_smc.bin");
- 			break;
-+		case CHIP_FIJI:
-+			strcpy(fw_name, "amdgpu/fiji_smc.bin");
-+			break;
- 		default:
- 			DRM_ERROR("SMC firmware not supported\n");
- 			return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 5dd2a4c..1a824f0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -77,6 +77,9 @@ static int amdgpu_powerplay_init(struct amdgpu_device *adev)
- 		case CHIP_TONGA:
- 			amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
- 			break;
-+		case CHIP_FIJI:
-+			amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
-+			break;
- 		case CHIP_CARRIZO:
- 			amd_pp->ip_funcs = &cz_dpm_ip_funcs;
- 			break;
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 9e8a220..28f07df 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1247,7 +1247,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
- 		.major = 7,
- 		.minor = 1,
- 		.rev = 0,
--		.funcs = &fiji_dpm_ip_funcs,
-+		.funcs = &amdgpu_pp_ip_funcs,
- 	},
- 	{
- 		.type = AMD_IP_BLOCK_TYPE_DCE,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0061-drm-amdgpu-powerplay-add-function-point-in-hwmgr_fun.patch b/common/recipes-kernel/linux/files/0061-drm-amdgpu-powerplay-add-function-point-in-hwmgr_fun.patch
deleted file mode 100644
index 3897cd86..00000000
--- a/common/recipes-kernel/linux/files/0061-drm-amdgpu-powerplay-add-function-point-in-hwmgr_fun.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From b7c7eca5fc11b57bbf3fad4710d60332daaf5232 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 14:51:09 +0800
-Subject: [PATCH 0061/1110] drm/amdgpu/powerplay: add function point in
- hwmgr_funcs for program display gap
-
-Displaygap support is required for proper mclk switching.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index ca513a1..2370a72 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -275,7 +275,6 @@ struct pp_hwmgr_func {
- 
- 	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
- 			    unsigned long, struct pp_power_state *);
--
- 	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
- 	int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
- 	int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
-@@ -287,6 +286,8 @@ struct pp_hwmgr_func {
- 	void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
- 							struct seq_file *m);
- 	int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
-+	int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
-+	int (*display_config_changed)(struct pp_hwmgr *hwmgr);
- };
- 
- struct pp_table_func {
-@@ -543,6 +544,7 @@ struct pp_hwmgr {
- 	struct phm_runtime_table_header enable_dynamic_state_management;
- 	struct phm_runtime_table_header set_power_state;
- 	struct phm_runtime_table_header enable_clock_power_gatings;
-+	struct phm_runtime_table_header display_configuration_changed;
- 	const struct pp_hwmgr_func *hwmgr_func;
- 	const struct pp_table_func *pptable_func;
- 	struct pp_power_state    *ps;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0062-drm-amdgpu-poweprlay-export-program-display-gap-func.patch b/common/recipes-kernel/linux/files/0062-drm-amdgpu-poweprlay-export-program-display-gap-func.patch
deleted file mode 100644
index 7f90bd26..00000000
--- a/common/recipes-kernel/linux/files/0062-drm-amdgpu-poweprlay-export-program-display-gap-func.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From e8804f55632a7d6f58ce5d769bd6767359823c31 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 14:55:03 +0800
-Subject: [PATCH 0062/1110] drm/amdgpu/poweprlay: export program display gap
- function to eventmgr
-
-This allows the eventmgr to properly update the displaygap on
-certain power events.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 27 ++++++++++++++++++++++
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    |  2 ++
- 2 files changed, 29 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index aec9f6d..620119f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -167,3 +167,30 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
- 	}
- 	return 0;
- }
-+
-+int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				 PHM_PlatformCaps_TablelessHardwareInterface)) {
-+		if (NULL != hwmgr->hwmgr_func->display_config_changed)
-+			hwmgr->hwmgr_func->display_config_changed(hwmgr);
-+	} else
-+		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
-+    return 0;
-+}
-+
-+int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				 PHM_PlatformCaps_TablelessHardwareInterface))
-+		if (NULL != hwmgr->hwmgr_func->display_config_changed)
-+			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
-+
-+    return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 9795b9a..1d29760 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -328,4 +328,6 @@ extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 			     const struct pp_power_state *current_ps);
- 
- extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
-+extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
-+extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
- #endif /* _HARDWARE_MANAGER_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0063-drm-amdgpu-powerplay-implement-pem_task-for-display_.patch b/common/recipes-kernel/linux/files/0063-drm-amdgpu-powerplay-implement-pem_task-for-display_.patch
deleted file mode 100644
index 4421d29c..00000000
--- a/common/recipes-kernel/linux/files/0063-drm-amdgpu-powerplay-implement-pem_task-for-display_.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From cd9e695b43b69fbd758530dc8b2fc6694901aecb Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 14:59:17 +0800
-Subject: [PATCH 0063/1110] drm/amdgpu/powerplay: implement pem_task for
- display_configuration_change
-
-Add support for display configuration changes to the event manager.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c |  2 +-
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c     | 15 ++++++++++++---
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h     |  2 +-
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.c            |  2 +-
- 4 files changed, 15 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-index 49d8a29..e5dd86d 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-@@ -152,7 +152,7 @@ const pem_event_action set_boot_state_tasks[] = {
- const pem_event_action adjust_power_state_tasks[] = {
- 	pem_task_notify_hw_mgr_display_configuration_change,
- 	pem_task_adjust_power_state,
--	/*pem_task_notify_smc_display_config_after_power_state_adjustment,*/
-+	pem_task_notify_smc_display_config_after_power_state_adjustment,
- 	pem_task_update_allowed_performance_levels,
- 	/* to do pem_task_Enable_disable_bapm, */
- 	NULL
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index 55d5490..8ca3280 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -189,16 +189,25 @@ int pem_task_store_dal_configuration(struct pp_eventmgr *eventmgr, const struct
- 
- int pem_task_notify_hw_mgr_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
--	/* TODO */
--	return 0;
-+	if (pem_is_hw_access_blocked(eventmgr))
-+		return 0;
-+
-+	return phm_display_configuration_changed(eventmgr->hwmgr);
- }
- 
- int pem_task_notify_hw_mgr_pre_display_configuration_change(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
--	/* TODO */
- 	return 0;
- }
- 
-+int pem_task_notify_smc_display_config_after_power_state_adjustment(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	if (pem_is_hw_access_blocked(eventmgr))
-+		return 0;
-+
-+	return phm_notify_smc_display_config_after_ps_adjustment(eventmgr->hwmgr);
-+}
-+
- int pem_task_block_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
- 	eventmgr->block_adjust_power_state = true;
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-index 37d3cf1..287c87c 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-@@ -57,7 +57,7 @@ int pem_task_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data
- int pem_task_un_block_hw_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
- int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
- int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
--
-+int pem_task_notify_smc_display_config_after_power_state_adjustment(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
- /*powersaving*/
- 
- int pem_task_set_power_source(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-index 7469c4c..08b75bd 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-@@ -97,7 +97,7 @@ int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
- 	pcurrent = hwmgr->current_ps;
- 	requested = hwmgr->request_ps;
- 
--	if (pcurrent != NULL || requested != NULL) {
-+	if ((pcurrent != NULL || requested != NULL) && (pcurrent != requested)) {
- 		phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
- 		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
- 		hwmgr->current_ps = requested;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0064-drm-amdgpu-powerplay-program-display-gap-for-tonga.patch b/common/recipes-kernel/linux/files/0064-drm-amdgpu-powerplay-program-display-gap-for-tonga.patch
deleted file mode 100644
index 27b6be2b..00000000
--- a/common/recipes-kernel/linux/files/0064-drm-amdgpu-powerplay-program-display-gap-for-tonga.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From b98ec74987101cbd193e534047c3da6e86f0448d Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 15:02:04 +0800
-Subject: [PATCH 0064/1110] drm/amdgpu/powerplay: program display gap for
- tonga.
-
-Implement displaygap programming for tonga.  This is
-required for properly mclk switching.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 91 +++++++++++++++++++++++
- 1 file changed, 91 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 1a02c7d..fe8b315 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -168,6 +168,13 @@ int tonga_add_voltage(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
-+int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
-+{
-+	PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
-+
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
-+}
-+
- uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
- 		uint32_t voltage)
- {
-@@ -4392,6 +4399,10 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
- 		"Failed to populate initialize MC Reg table!", result = tmp_result);
- 
-+	tmp_result = tonga_notify_smc_display_change(hwmgr, false);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+		"Failed to notify no display!", result = tmp_result);
-+
- 	/* enable SCLK control */
- 	tmp_result = tonga_enable_sclk_control(hwmgr);
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
-@@ -5679,6 +5690,84 @@ static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input
- 	return result;
- }
- 
-+
-+int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t num_active_displays = 0;
-+	struct cgs_display_info info = {0};
-+	info.mode_info = NULL;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	num_active_displays = info.display_count;
-+
-+	if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
-+		tonga_notify_smc_display_change(hwmgr, false);
-+	else
-+		tonga_notify_smc_display_change(hwmgr, true);
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs the display gap
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always OK
-+*/
-+int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t num_active_displays = 0;
-+	uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
-+	uint32_t display_gap2;
-+	uint32_t pre_vbi_time_in_us;
-+	uint32_t frame_time_in_us;
-+	uint32_t ref_clock;
-+	uint32_t refresh_rate = 0;
-+	struct cgs_display_info info = {0};
-+	struct cgs_mode_info mode_info;
-+
-+	info.mode_info = &mode_info;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	num_active_displays = info.display_count;
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	ref_clock = mode_info.ref_clock;
-+	refresh_rate = mode_info.refresh_rate;
-+
-+	if(0 == refresh_rate)
-+		refresh_rate = 60;
-+
-+	frame_time_in_us = 1000000 / refresh_rate;
-+
-+	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
-+	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
-+
-+	if (num_active_displays == 1)
-+		tonga_notify_smc_display_change(hwmgr, true);
-+
-+	return 0;
-+}
-+
-+int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
-+{
-+
-+	tonga_program_display_gap(hwmgr);
-+
-+	/* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.backend_init = &tonga_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -5694,6 +5783,8 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.get_pp_table_entry = tonga_get_pp_table_entry,
- 	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
- 	.print_current_perforce_level = tonga_print_current_perforce_level,
-+	.notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
-+	.display_config_changed = tonga_display_configuration_changed_task,
- };
- 
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0065-drm-amdgpu-enable-powerplay-module-by-default-for-to.patch b/common/recipes-kernel/linux/files/0065-drm-amdgpu-enable-powerplay-module-by-default-for-to.patch
deleted file mode 100644
index 97126033..00000000
--- a/common/recipes-kernel/linux/files/0065-drm-amdgpu-enable-powerplay-module-by-default-for-to.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From b18cc36a16c393854c4cea0eb2e752fe78b540fa Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Sat, 17 Oct 2015 17:57:58 +0800
-Subject: [PATCH 0065/1110] drm/amdgpu: enable powerplay module by default for
- tonga.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 1a824f0..cbb00e2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -96,6 +96,14 @@ static int amdgpu_pp_early_init(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	int ret = 0;
- 
-+	switch (adev->asic_type) {
-+		case CHIP_TONGA:
-+			amdgpu_powerplay = 1;
-+			break;
-+		default:
-+			break;
-+	}
-+
- 	ret = amdgpu_powerplay_init(adev);
- 	if (ret)
- 		return ret;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0066-drm-amdgpu-enable-powerplay-module-by-default-for-fi.patch b/common/recipes-kernel/linux/files/0066-drm-amdgpu-enable-powerplay-module-by-default-for-fi.patch
deleted file mode 100644
index 803fe947..00000000
--- a/common/recipes-kernel/linux/files/0066-drm-amdgpu-enable-powerplay-module-by-default-for-fi.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 78c5ba369b8995d8c03493f2e405f7a5bb64e7f8 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 20 Oct 2015 11:05:45 +0800
-Subject: [PATCH 0066/1110] drm/amdgpu: enable powerplay module by default for
- fiji.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index cbb00e2..1ff6fd5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -96,13 +96,16 @@ static int amdgpu_pp_early_init(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	int ret = 0;
- 
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
- 	switch (adev->asic_type) {
- 		case CHIP_TONGA:
-+		case CHIP_FIJI:
- 			amdgpu_powerplay = 1;
- 			break;
- 		default:
- 			break;
- 	}
-+#endif
- 
- 	ret = amdgpu_powerplay_init(adev);
- 	if (ret)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0067-drm-amdgpu-powerplay-add-some-definition-for-other-i.patch b/common/recipes-kernel/linux/files/0067-drm-amdgpu-powerplay-add-some-definition-for-other-i.patch
deleted file mode 100644
index f416db4f..00000000
--- a/common/recipes-kernel/linux/files/0067-drm-amdgpu-powerplay-add-some-definition-for-other-i.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 474eca7871cf0e94ad49d59087b7f68c78c68bcc Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 9 Oct 2015 18:43:28 +0800
-Subject: [PATCH 0067/1110] drm/amdgpu/powerplay: add some definition for other
- ip block to update cg pg.
-
-Interface for clock and power gating handling.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 41 +++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 2281d88..d81b239 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -131,6 +131,47 @@ struct amd_pp_init {
- 	uint32_t rev_id;
- };
- 
-+enum {
-+	PP_GROUP_UNKNOWN = 0,
-+	PP_GROUP_GFX = 1,
-+	PP_GROUP_SYS,
-+	PP_GROUP_MAX
-+};
-+
-+#define PP_GROUP_MASK        0xF0000000
-+#define PP_GROUP_SHIFT       28
-+
-+#define PP_BLOCK_MASK        0x0FFFFF00
-+#define PP_BLOCK_SHIFT       8
-+
-+#define PP_BLOCK_GFX_CG         0x01
-+#define PP_BLOCK_GFX_MG         0x02
-+#define PP_BLOCK_SYS_BIF        0x01
-+#define PP_BLOCK_SYS_MC         0x02
-+#define PP_BLOCK_SYS_ROM        0x04
-+#define PP_BLOCK_SYS_DRM        0x08
-+#define PP_BLOCK_SYS_HDP        0x10
-+#define PP_BLOCK_SYS_SDMA       0x20
-+
-+#define PP_STATE_MASK           0x0000000F
-+#define PP_STATE_SHIFT          0
-+#define PP_STATE_SUPPORT_MASK   0x000000F0
-+#define PP_STATE_SUPPORT_SHIFT  0
-+
-+#define PP_STATE_CG             0x01
-+#define PP_STATE_LS             0x02
-+#define PP_STATE_DS             0x04
-+#define PP_STATE_SD             0x08
-+#define PP_STATE_SUPPORT_CG     0x10
-+#define PP_STATE_SUPPORT_LS     0x20
-+#define PP_STATE_SUPPORT_DS     0x40
-+#define PP_STATE_SUPPORT_SD     0x80
-+
-+#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
-+								block << PP_BLOCK_SHIFT |\
-+								support << PP_STATE_SUPPORT_SHIFT |\
-+								state << PP_STATE_SHIFT)
-+
- struct amd_powerplay_funcs {
- 	int (*get_temperature)(void *handle);
- 	int (*load_firmware)(void *handle);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0068-drm-amd-powerplay-add-new-function-point-in-hwmgr_fu.patch b/common/recipes-kernel/linux/files/0068-drm-amd-powerplay-add-new-function-point-in-hwmgr_fu.patch
deleted file mode 100644
index 8089c10a..00000000
--- a/common/recipes-kernel/linux/files/0068-drm-amd-powerplay-add-new-function-point-in-hwmgr_fu.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 37cce1a8266a1ab827d2173772fee084ede9f6d6 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 30 Sep 2015 13:28:49 +0800
-Subject: [PATCH 0068/1110] drm/amd/powerplay: add new function point in
- hwmgr_func for CG/PG.
-
-Add callbacks interface for clock and powergating.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 2370a72..f90a8b6 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -288,6 +288,9 @@ struct pp_hwmgr_func {
- 	int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
- 	int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
- 	int (*display_config_changed)(struct pp_hwmgr *hwmgr);
-+	int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
-+	int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
-+						const uint32_t *msg_id);
- };
- 
- struct pp_table_func {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0069-drm-amd-powerplay-Add-CG-and-PG-support-for-tonga.patch b/common/recipes-kernel/linux/files/0069-drm-amd-powerplay-Add-CG-and-PG-support-for-tonga.patch
deleted file mode 100644
index 09dba042..00000000
--- a/common/recipes-kernel/linux/files/0069-drm-amd-powerplay-Add-CG-and-PG-support-for-tonga.patch
+++ /dev/null
@@ -1,559 +0,0 @@
-From 6662b1e637efc24bfc592d234e9398c42ba30726 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 15 Oct 2015 21:12:58 +0800
-Subject: [PATCH 0069/1110] drm/amd/powerplay: Add CG and PG support for tonga
-
-Implement clock and power gating support for tonga.  On Tonga
-this is handles by the SMU rather than direct register settings
-in the driver.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   2 +-
- .../amd/powerplay/hwmgr/tonga_clockpowergating.c   | 350 +++++++++++++++++++++
- .../amd/powerplay/hwmgr/tonga_clockpowergating.h   |  36 +++
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  63 +++-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h  |   4 +
- 5 files changed, 440 insertions(+), 15 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index c78e38c..6f38811 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -7,7 +7,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-                cz_clockpowergating.o \
- 	       tonga_processpptables.o ppatomctrl.o \
-                tonga_hwmgr.o 	pppcielanes.o \
--               fiji_powertune.o fiji_hwmgr.o
-+               fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
-new file mode 100644
-index 0000000..e58d038
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
-@@ -0,0 +1,350 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "hwmgr.h"
-+#include "tonga_clockpowergating.h"
-+#include "tonga_ppsmc.h"
-+#include "tonga_hwmgr.h"
-+
-+int tonga_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_uvd_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+						     PPSMC_MSG_UVDPowerOFF);
-+	return 0;
-+}
-+
-+int tonga_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_uvd_power_gating(hwmgr)) {
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+								PPSMC_MSG_UVDPowerON, 1);
-+		} else {
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+								PPSMC_MSG_UVDPowerON, 0);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_vce_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+						  PPSMC_MSG_VCEPowerOFF);
-+	return 0;
-+}
-+
-+int tonga_phm_powerup_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_vce_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+						  PPSMC_MSG_VCEPowerON);
-+	return 0;
-+}
-+
-+int tonga_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating)
-+{
-+	int ret = 0;
-+
-+	switch (block) {
-+	case PHM_AsicBlock_UVD_MVC:
-+	case PHM_AsicBlock_UVD:
-+	case PHM_AsicBlock_UVD_HD:
-+	case PHM_AsicBlock_UVD_SD:
-+		if (gating == PHM_ClockGateSetting_StaticOff)
-+			ret = tonga_phm_powerdown_uvd(hwmgr);
-+		else
-+			ret = tonga_phm_powerup_uvd(hwmgr);
-+		break;
-+	case PHM_AsicBlock_GFX:
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+int tonga_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+
-+	tonga_phm_powerup_uvd(hwmgr);
-+	tonga_phm_powerup_vce(hwmgr);
-+
-+	return 0;
-+}
-+
-+int tonga_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (data->uvd_power_gated == bgate)
-+		return 0;
-+
-+	data->uvd_power_gated = bgate;
-+
-+	if (bgate) {
-+		cgs_set_clockgating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_CG_STATE_UNGATE);
-+		cgs_set_powergating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_PG_STATE_GATE);
-+		tonga_update_uvd_dpm(hwmgr, true);
-+		tonga_phm_powerdown_uvd(hwmgr);
-+	} else {
-+		tonga_phm_powerup_uvd(hwmgr);
-+		cgs_set_powergating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_PG_STATE_UNGATE);
-+		cgs_set_clockgating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_UVD,
-+						AMD_PG_STATE_GATE);
-+
-+		tonga_update_uvd_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_set_power_state_input states;
-+	const struct pp_power_state  *pcurrent;
-+	struct pp_power_state  *requested;
-+
-+	pcurrent = hwmgr->current_ps;
-+	requested = hwmgr->request_ps;
-+
-+	states.pcurrent_state = &(pcurrent->hardware);
-+	states.pnew_state = &(requested->hardware);
-+
-+	if (phm_cf_want_vce_power_gating(hwmgr)) {
-+		if (data->vce_power_gated != bgate) {
-+			if (bgate) {
-+				cgs_set_clockgating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_CG_STATE_UNGATE);
-+				cgs_set_powergating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_PG_STATE_GATE);
-+				tonga_enable_disable_vce_dpm(hwmgr, false);
-+				data->vce_power_gated = true;
-+			} else {
-+				tonga_phm_powerup_vce(hwmgr);
-+				data->vce_power_gated = false;
-+				cgs_set_powergating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_PG_STATE_UNGATE);
-+				cgs_set_clockgating_state(
-+							hwmgr->device,
-+							AMD_IP_BLOCK_TYPE_VCE,
-+							AMD_PG_STATE_GATE);
-+
-+				tonga_update_vce_dpm(hwmgr, &states);
-+				tonga_enable_disable_vce_dpm(hwmgr, true);
-+				return 0;
-+			}
-+		}
-+	} else {
-+		tonga_update_vce_dpm(hwmgr, &states);
-+		tonga_enable_disable_vce_dpm(hwmgr, true);
-+		return 0;
-+	}
-+
-+	if (!data->vce_power_gated)
-+		tonga_update_vce_dpm(hwmgr, &states);
-+
-+	return 0;
-+}
-+
-+int tonga_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
-+					const uint32_t *msg_id)
-+{
-+	PPSMC_Msg msg;
-+	uint32_t value;
-+
-+	switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
-+	case PP_GROUP_GFX:
-+		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
-+		case PP_BLOCK_GFX_CG:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
-+				  ? PPSMC_MSG_EnableClockGatingFeature
-+				  : PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CGCG_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+					? PPSMC_MSG_EnableClockGatingFeature
-+					: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CGLS_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_MG:
-+			/* For GFX MGCG, there are three different ones;
-+			 * CPF, RLC, and all others.  CPF MGCG will not be used for Tonga.
-+			 * For GFX MGLS, Tonga will not support it.
-+			 * */
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+				value = (CG_RLC_MGCG_MASK | CG_GFX_OTHERS_MGCG_MASK);
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		default:
-+			return -1;
-+		}
-+		break;
-+
-+	case PP_GROUP_SYS:
-+		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
-+		case PP_BLOCK_SYS_BIF:
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_BIF_MGLS_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_MC:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_MC_MGCG_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_MC_MGLS_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_HDP:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
-+					? PPSMC_MSG_EnableClockGatingFeature
-+					: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_HDP_MGCG_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+					? PPSMC_MSG_EnableClockGatingFeature
-+					: PPSMC_MSG_DisableClockGatingFeature;
-+
-+				value = CG_SYS_HDP_MGLS_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_SDMA:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_SDMA_MGCG_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+
-+				value = CG_SYS_SDMA_MGLS_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_ROM:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
-+				? PPSMC_MSG_EnableClockGatingFeature
-+				: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_ROM_MASK;
-+
-+				if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		default:
-+			return -1;
-+
-+		}
-+		break;
-+
-+	default:
-+		return -1;
-+
-+	}
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.h
-new file mode 100644
-index 0000000..8bc38cb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.h
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _TONGA_CLOCK_POWER_GATING_H_
-+#define _TONGA_CLOCK_POWER_GATING_H_
-+
-+#include "tonga_hwmgr.h"
-+#include "pp_asicblocks.h"
-+
-+extern int tonga_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
-+extern int tonga_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int tonga_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int tonga_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
-+extern int tonga_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
-+extern int tonga_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, const uint32_t *msg_id);
-+#endif /* _TONGA_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index fe8b315..9a7de1f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -39,6 +39,7 @@
- #include "tonga_dyn_defaults.h"
- #include "smumgr.h"
- #include "tonga_smumgr.h"
-+#include "tonga_clockpowergating.h"
- 
- #include "smu/smu_7_1_2_d.h"
- #include "smu/smu_7_1_2_sh_mask.h"
-@@ -5488,14 +5489,47 @@ static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const vo
- 	return 0;
- }
- 
--static int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
- 				  (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
- 				  (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
- }
- 
--static int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
-+int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+				  (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
-+				  (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
-+}
-+
-+int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0x00FFFFFF;
-+		mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
-+		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_UVDDPM_SetEnabledMask,
-+						(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
-+	}
-+
-+	return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
-+}
-+
-+int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- {
- 	const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
- 	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-@@ -5505,8 +5539,7 @@ static int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- 	uint32_t mm_boot_level_offset, mm_boot_level_value;
- 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
- 
--	if(tonga_nps->vce_clocks.EVCLK >0 &&
--	(tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
-+	if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
- 		data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
- 
- 		mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
-@@ -5517,16 +5550,14 @@ static int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- 		mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
- 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
--				smum_send_msg_to_smc_with_parameter(
--							   hwmgr->smumgr,
--			(PPSMC_Msg)(PPSMC_MSG_VCEDPM_SetEnabledMask),
--			(uint32_t)1 << data->smc_state_table.VceBootLevel);
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VCEDPM_SetEnabledMask,
-+				(uint32_t)(1 << data->smc_state_table.VceBootLevel));
- 
--			tonga_enable_disable_vce_dpm(hwmgr, true);
--		} else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
--			tonga_enable_disable_vce_dpm(hwmgr, false);
--	}
-+		tonga_enable_disable_vce_dpm(hwmgr, true);
-+	} else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
-+		tonga_enable_disable_vce_dpm(hwmgr, false);
- 
- 	return 0;
- }
-@@ -5783,6 +5814,10 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.get_pp_table_entry = tonga_get_pp_table_entry,
- 	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
- 	.print_current_perforce_level = tonga_print_current_perforce_level,
-+	.powerdown_uvd = tonga_phm_powerdown_uvd,
-+	.powergate_uvd = tonga_phm_powergate_uvd,
-+	.powergate_vce = tonga_phm_powergate_vce,
-+	.disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
- 	.notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
- 	.display_config_changed = tonga_display_configuration_changed_task,
- };
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index d007706..c3ac966 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -422,6 +422,10 @@ typedef struct tonga_hwmgr tonga_hwmgr;
- #define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
- 
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
-+int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
-+int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
-+int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
- 
- #endif
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0070-drm-amdgpu-powerplay-add-new-function-point-in-hwmgr.patch b/common/recipes-kernel/linux/files/0070-drm-amdgpu-powerplay-add-new-function-point-in-hwmgr.patch
deleted file mode 100644
index 654d7227..00000000
--- a/common/recipes-kernel/linux/files/0070-drm-amdgpu-powerplay-add-new-function-point-in-hwmgr.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 16b151977998b9cf5f4dd4420d8886ed0ded76cf Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 11:46:51 +0800
-Subject: [PATCH 0070/1110] drm/amdgpu/powerplay: add new function point in
- hwmgr_funcs for thermal control
-
-Add the interface for fan and thermal control.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index f90a8b6..aedb1e4 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -35,6 +35,7 @@ struct pp_hwmgr;
- struct pp_hw_power_state;
- struct pp_power_state;
- struct PP_VCEState;
-+struct phm_fan_speed_info;
- 
- enum PP_Result {
- 	PP_Result_TableImmediateExit = 0x13,
-@@ -291,6 +292,21 @@ struct pp_hwmgr_func {
- 	int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
- 	int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
- 						const uint32_t *msg_id);
-+	int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
-+	int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
-+	int (*get_temperature)(struct pp_hwmgr *hwmgr);
-+	int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
-+	int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
-+	int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
-+	int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
-+	int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
-+	int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+	int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
-+	int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+	int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
-+	int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
-+	int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
-+					const void *thermal_interrupt_info);
- };
- 
- struct pp_table_func {
-@@ -548,12 +564,17 @@ struct pp_hwmgr {
- 	struct phm_runtime_table_header set_power_state;
- 	struct phm_runtime_table_header enable_clock_power_gatings;
- 	struct phm_runtime_table_header display_configuration_changed;
-+	struct phm_runtime_table_header start_thermal_controller;
-+	struct phm_runtime_table_header set_temperature_range;
- 	const struct pp_hwmgr_func *hwmgr_func;
- 	const struct pp_table_func *pptable_func;
- 	struct pp_power_state    *ps;
-         enum pp_power_source  power_source;
- 	uint32_t num_ps;
- 	struct pp_thermal_controller_info thermal_controller;
-+	bool fan_ctrl_is_in_default_mode;
-+	uint32_t fan_ctrl_default_mode;
-+	uint32_t tmin;
- 	struct phm_microcode_version_info microcode_version_info;
- 	uint32_t ps_size;
- 	struct pp_power_state    *current_ps;
-@@ -599,6 +620,7 @@ extern void phm_wait_for_indirect_register_unequal(
- 
- bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
- bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
-+bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
- 
- #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0071-drm-amdgpu-powerplay-mv-ppinterrupt.h-to-inc-folder-.patch b/common/recipes-kernel/linux/files/0071-drm-amdgpu-powerplay-mv-ppinterrupt.h-to-inc-folder-.patch
deleted file mode 100644
index 967ec963..00000000
--- a/common/recipes-kernel/linux/files/0071-drm-amdgpu-powerplay-mv-ppinterrupt.h-to-inc-folder-.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From c0f9855c24dfe901e87db8cf6e53c16f3a95a460 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 21 Oct 2015 10:30:02 +0800
-Subject: [PATCH 0071/1110] drm/amdgpu/powerplay: mv ppinterrupt.h to inc
- folder to share with other submodule.
-
-Redefine interrupt callback function in accordance with cgs.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h | 42 ---------------------
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h | 14 +++----
- drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h   | 46 +++++++++++++++++++++++
- 3 files changed, 53 insertions(+), 49 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h
-deleted file mode 100644
-index 7269ac1..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppinterrupt.h
-+++ /dev/null
-@@ -1,42 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--#ifndef PP_INTERRUPT_H
--#define PP_INTERRUPT_H
--
--/**
-- * The type of the interrupt callback functions in PowerPlay
-- */
--typedef void (*pp_interrupt_callback) (void *context, uint32_t ul_context_data);
--
--/**
-- * Event Manager action chain list information
-- */
--struct pp_interrupt_registration_info {
--	pp_interrupt_callback callback;  /* Pointer to callback function */
--	void *context;                  /* Pointer to callback function context */
--	uint32_t *interrupt_enable_id;    /* Registered interrupt id */
--};
--
--typedef struct pp_interrupt_registration_info pp_interrupt_registration_info;
--
--#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index c3ac966..d773d12 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -223,17 +223,17 @@ struct tonga_hwmgr {
- 	uint32_t                           vddc_vddci_delta;
- 	uint32_t                           vddc_vddgfx_delta;
- 
--	pp_interrupt_registration_info    internal_high_thermal_interrupt_info;
--	pp_interrupt_registration_info    internal_low_thermal_interrupt_info;
--	pp_interrupt_registration_info    smc_to_host_interrupt_info;
-+	struct pp_interrupt_registration_info    internal_high_thermal_interrupt_info;
-+	struct pp_interrupt_registration_info    internal_low_thermal_interrupt_info;
-+	struct pp_interrupt_registration_info    smc_to_host_interrupt_info;
- 	uint32_t                          active_auto_throttle_sources;
- 
--	pp_interrupt_registration_info    external_throttle_interrupt;
--	pp_interrupt_callback             external_throttle_callback;
-+	struct pp_interrupt_registration_info    external_throttle_interrupt;
-+	irq_handler_func_t             external_throttle_callback;
- 	void                             *external_throttle_context;
- 
--	pp_interrupt_registration_info    ctf_interrupt_info;
--	pp_interrupt_callback             ctf_callback;
-+	struct pp_interrupt_registration_info    ctf_interrupt_info;
-+	irq_handler_func_t             ctf_callback;
- 	void                             *ctf_context;
- 
- 	phw_tonga_clock_registers      	  clock_registers;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h b/drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h
-new file mode 100644
-index 0000000..c067e09
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/ppinterrupt.h
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _PP_INTERRUPT_H_
-+#define _PP_INTERRUPT_H_
-+
-+enum amd_thermal_irq {
-+	AMD_THERMAL_IRQ_LOW_TO_HIGH = 0,
-+	AMD_THERMAL_IRQ_HIGH_TO_LOW,
-+
-+	AMD_THERMAL_IRQ_LAST
-+};
-+
-+/* The type of the interrupt callback functions in PowerPlay */
-+typedef int (*irq_handler_func_t)(void *private_data,
-+				unsigned src_id, const uint32_t *iv_entry);
-+
-+/* Event Manager action chain list information */
-+struct pp_interrupt_registration_info {
-+	irq_handler_func_t call_back; /* Pointer to callback function */
-+	void *context;                   /* Pointer to callback function context */
-+	uint32_t src_id;               /* Registered interrupt id */
-+	const uint32_t *iv_entry;
-+};
-+
-+#endif /* _PP_INTERRUPT_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0072-drm-amdgpu-powerplay-add-thermal-control-interface-i.patch b/common/recipes-kernel/linux/files/0072-drm-amdgpu-powerplay-add-thermal-control-interface-i.patch
deleted file mode 100644
index b27a6966..00000000
--- a/common/recipes-kernel/linux/files/0072-drm-amdgpu-powerplay-add-thermal-control-interface-i.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 2a58c1170bd4bc0fe78b01b525baac8739e373ea Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 21 Oct 2015 10:34:22 +0800
-Subject: [PATCH 0072/1110] drm/amdgpu/powerplay: add thermal control interface
- in hwmgr.
-
-Thermal controller interface.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 29 ++++++++++++++++++++++
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    | 16 ++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/power_state.h    |  4 +--
- 3 files changed, 47 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 620119f..9d910f3 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -194,3 +194,32 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
- 
-     return 0;
- }
-+
-+int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr == NULL || hwmgr->hwmgr_func->stop_thermal_controller == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
-+}
-+
-+int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
-+{
-+	if (hwmgr == NULL || hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
-+}
-+
-+/**
-+* Initializes the thermal controller subsystem.
-+*
-+* @param    pHwMgr  the address of the powerplay hardware manager.
-+* @param    pTemperatureRange the address of the structure holding the temperature range.
-+* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
-+*/
-+int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
-+{
-+
-+	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 1d29760..a868110 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -29,6 +29,18 @@ struct pp_hwmgr;
- struct pp_hw_power_state;
- struct pp_power_state;
- enum amd_dpm_forced_level;
-+struct PP_TemperatureRange;
-+
-+struct phm_fan_speed_info {
-+	uint32_t min_percent;
-+	uint32_t max_percent;
-+	uint32_t min_rpm;
-+	uint32_t max_rpm;
-+	bool supports_percent_read;
-+	bool supports_percent_write;
-+	bool supports_rpm_read;
-+	bool supports_rpm_write;
-+};
- 
- /* Automatic Power State Throttling */
- enum PHM_AutoThrottleSource
-@@ -330,4 +342,8 @@ extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
- extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
- extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
-+extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
-+extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
-+extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
- #endif /* _HARDWARE_MANAGER_H_ */
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
-index c63bcc7..a3f0ce4 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
-@@ -122,8 +122,8 @@ struct PP_StateSoftwareAlgorithmBlock {
-  * Type to hold a temperature range.
-  */
- struct PP_TemperatureRange {
--	uint16_t min;
--	uint16_t max;
-+	uint32_t min;
-+	uint32_t max;
- };
- 
- struct PP_StateValidationBlock {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0073-drm-amdgpu-powerplay-enable-thermal-interrupt-task-i.patch b/common/recipes-kernel/linux/files/0073-drm-amdgpu-powerplay-enable-thermal-interrupt-task-i.patch
deleted file mode 100644
index 7b476416..00000000
--- a/common/recipes-kernel/linux/files/0073-drm-amdgpu-powerplay-enable-thermal-interrupt-task-i.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From 7ebe355fcd71a1cf5c2108a286dd4d043acd3ae4 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 20:32:36 +0800
-Subject: [PATCH 0073/1110] drm/amdgpu/powerplay: enable thermal interrupt task
- in eventmgr.
-
-Add thermal handling to the event manager.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/eventmgr/eventactionchains.c |  1 +
- drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c     | 17 ++++++++++++++++-
- .../gpu/drm/amd/powerplay/eventmgr/eventsubchains.c    | 10 ++++++++++
- .../gpu/drm/amd/powerplay/eventmgr/eventsubchains.h    |  3 ++-
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c    | 18 ++++++++++++++++--
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h    |  3 +++
- 6 files changed, 48 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-index e9fe85f..bbbb76c 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -33,6 +33,7 @@ static const pem_event_action *initialize_event[] = {
- 	enable_clock_power_gatings_tasks,
- 	get_2d_performance_state_tasks,
- 	set_performance_state_tasks,
-+	initialize_thermal_controller_tasks,
- 	conditionally_force_3d_performance_state_tasks,
- 	process_vbios_eventinfo_tasks,
- 	broadcast_power_policy_tasks,
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
-index 0438442..d5ec8cc 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventinit.c
-@@ -22,6 +22,8 @@
-  */
- #include "eventmgr.h"
- #include "eventinit.h"
-+#include "ppinterrupt.h"
-+#include "hardwaremanager.h"
- 
- void pem_init_feature_info(struct pp_eventmgr *eventmgr)
- {
-@@ -145,12 +147,25 @@ void pem_init_feature_info(struct pp_eventmgr *eventmgr)
- 	eventmgr->features[PP_Feature_ViPG].enabled = false;
- }
- 
-+static int thermal_interrupt_callback(void *private_data,
-+				      unsigned src_id, const uint32_t *iv_entry)
-+{
-+	/* TO DO hanle PEM_Event_ThermalNotification (struct pp_eventmgr *)private_data*/
-+	printk("current thermal is out of range \n");
-+	return 0;
-+}
-+
- int pem_register_interrupts(struct pp_eventmgr *eventmgr)
- {
- 	int result = 0;
-+	struct pp_interrupt_registration_info info;
-+
-+	info.call_back = thermal_interrupt_callback;
-+	info.context = eventmgr;
-+
-+	result = phm_register_thermal_interrupt(eventmgr->hwmgr, &info);
- 
- 	/* TODO:
--	 * 1. Register thermal events interrupt
- 	 * 2. Register CTF event interrupt
- 	 * 3. Register for vbios events interrupt
- 	 * 4. Register External Throttle Interrupt
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-index e5dd86d..3dd671e 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-@@ -393,3 +393,13 @@ const pem_event_action create_new_user_performance_state_tasks[] = {
- 	pem_task_create_user_performance_state,
- 	NULL
- };
-+
-+const pem_event_action initialize_thermal_controller_tasks[] = {
-+	pem_task_initialize_thermal_controller,
-+	NULL
-+};
-+
-+const pem_event_action uninitialize_thermal_controller_tasks[] = {
-+	pem_task_uninitialize_thermal_controller,
-+	NULL
-+};
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-index 27e0e61..741ebfc 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-@@ -94,5 +94,6 @@ extern const pem_event_action enable_stutter_mode_tasks[];
- extern const pem_event_action enable_disable_bapm_tasks[];
- extern const pem_event_action reset_boot_state_tasks[];
- extern const pem_event_action create_new_user_performance_state_tasks[];
--
-+extern const pem_event_action initialize_thermal_controller_tasks[];
-+extern const pem_event_action uninitialize_thermal_controller_tasks[];
- #endif /* _EVENT_SUB_CHAINS_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index 8ca3280..fdd67c6 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -32,6 +32,9 @@
- #include "amd_powerplay.h"
- #include "psm.h"
- 
-+#define TEMP_RANGE_MIN (90 * 1000)
-+#define TEMP_RANGE_MAX (120 * 1000)
-+
- int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
- 
-@@ -104,8 +107,6 @@ int pem_task_unregister_interrupts(struct pp_eventmgr *eventmgr, struct pem_even
- 	return pem_unregister_interrupts(eventmgr);
- }
- 
--
--
- int pem_task_get_boot_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
- 	int result;
-@@ -415,3 +416,16 @@ restart_search:
- 	return -1;
- }
- 
-+int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	struct PP_TemperatureRange range;
-+	range.max = TEMP_RANGE_MAX;
-+	range.min = TEMP_RANGE_MIN;
-+
-+	return phm_start_thermal_controller(eventmgr->hwmgr, &range);
-+}
-+
-+int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-+{
-+	return phm_stop_thermal_controller(eventmgr->hwmgr);
-+}
-\ No newline at end of file
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-index 287c87c..6c6297e 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.h
-@@ -81,5 +81,8 @@ int pem_task_conditionally_force_3d_performance_state(struct pp_eventmgr *eventm
- int pem_task_get_2D_performance_state_id(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
- int pem_task_create_user_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
- int pem_task_update_allowed_performance_levels(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+/*thermal */
-+int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
-+int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data);
- 
- #endif /* _EVENT_TASKS_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0074-drm-amdgpu-powerplay-implement-thermal-control-for-t.patch b/common/recipes-kernel/linux/files/0074-drm-amdgpu-powerplay-implement-thermal-control-for-t.patch
deleted file mode 100644
index da32eabd..00000000
--- a/common/recipes-kernel/linux/files/0074-drm-amdgpu-powerplay-implement-thermal-control-for-t.patch
+++ /dev/null
@@ -1,904 +0,0 @@
-From 6b510abe48de659a306ac314d102b11aa2c336c2 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 20 Oct 2015 18:06:23 +0800
-Subject: [PATCH 0074/1110] drm/amdgpu/powerplay: implement thermal control for
- tonga.
-
-Implement thermal and fan control for tonga.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  | 150 +++++-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h  |   1 +
- .../gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c    | 587 +++++++++++++++++++++
- .../gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h    |  60 +++
- 5 files changed, 798 insertions(+), 2 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index 6f38811..cea032c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -6,7 +6,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
- 	       hardwaremanager.o pp_acpi.o cz_hwmgr.o \
-                cz_clockpowergating.o \
- 	       tonga_processpptables.o ppatomctrl.o \
--               tonga_hwmgr.o 	pppcielanes.o \
-+               tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
-                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 9a7de1f..088b5bf 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -40,6 +40,7 @@
- #include "smumgr.h"
- #include "tonga_smumgr.h"
- #include "tonga_clockpowergating.h"
-+#include "tonga_thermal.h"
- 
- #include "smu/smu_7_1_2_d.h"
- #include "smu/smu_7_1_2_sh_mask.h"
-@@ -50,6 +51,9 @@
- #include "bif/bif_5_0_d.h"
- #include "bif/bif_5_0_sh_mask.h"
- 
-+#include "cgs_linux.h"
-+#include "eventmgr.h"
-+
- #define MC_CG_ARB_FREQ_F0           0x0a
- #define MC_CG_ARB_FREQ_F1           0x0b
- #define MC_CG_ARB_FREQ_F2           0x0c
-@@ -5721,6 +5725,22 @@ static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input
- 	return result;
- }
- 
-+/**
-+*  Set maximum target operating fan output PWM
-+*
-+* @param    pHwMgr:  the address of the powerplay hardware manager.
-+* @param    usMaxFanPwm:  max operating fan PWM in percents
-+* @return   The response that came from the SMC.
-+*/
-+static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
-+{
-+	hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+    return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -EINVAL);
-+}
- 
- int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
- {
-@@ -5799,6 +5819,122 @@ int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
- 	return 0;
- }
- 
-+/**
-+*  Set maximum target operating fan output RPM
-+*
-+* @param    pHwMgr:  the address of the powerplay hardware manager.
-+* @param    usMaxFanRpm:  max operating fan RPM value.
-+* @return   The response that came from the SMC.
-+*/
-+static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
-+{
-+	hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+	return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -EINVAL);
-+}
-+
-+uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t reference_clock;
-+	uint32_t tc;
-+	uint32_t divide;
-+
-+	ATOM_FIRMWARE_INFO *fw_info;
-+	uint16_t size;
-+	uint8_t frev, crev;
-+	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-+
-+	tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
-+
-+	if (tc)
-+		return TCLK;
-+
-+	fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
-+						  &size, &frev, &crev);
-+
-+	if (!fw_info)
-+		return 0;
-+
-+	reference_clock = le16_to_cpu(fw_info->usMinPixelClockPLL_Output);
-+
-+	divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
-+
-+	if (0 != divide)
-+		return reference_clock / 4;
-+
-+	return reference_clock;
-+}
-+
-+int tonga_dpm_set_interrupt_state(void *private_data,
-+					 unsigned src_id, unsigned type,
-+					 int enabled)
-+{
-+	uint32_t cg_thermal_int;
-+	struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	switch (type) {
-+	case AMD_THERMAL_IRQ_LOW_TO_HIGH:
-+		if (enabled) {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		} else {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		}
-+		break;
-+
-+	case AMD_THERMAL_IRQ_HIGH_TO_LOW:
-+		if (enabled) {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		} else {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	return 0;
-+}
-+
-+int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
-+					const void *thermal_interrupt_info)
-+{
-+	int result;
-+	const struct pp_interrupt_registration_info *info =
-+			(const struct pp_interrupt_registration_info *)thermal_interrupt_info;
-+
-+	if (info == NULL)
-+		return -EINVAL;
-+
-+	result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
-+				tonga_dpm_set_interrupt_state,
-+				info->call_back, info->context);
-+
-+	if (result)
-+		return -EINVAL;
-+
-+	result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
-+				tonga_dpm_set_interrupt_state,
-+				info->call_back, info->context);
-+
-+	if (result)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.backend_init = &tonga_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -5820,6 +5956,18 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
- 	.notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
- 	.display_config_changed = tonga_display_configuration_changed_task,
-+	.set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
-+	.set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
-+	.get_temperature = tonga_thermal_get_temperature,
-+	.stop_thermal_controller = tonga_thermal_stop_thermal_controller,
-+	.get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
-+	.get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
-+	.set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
-+	.reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
-+	.get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
-+	.set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
-+	.uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
-+	.register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
- };
- 
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
-@@ -5834,7 +5982,7 @@ int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
- 	hwmgr->backend = data;
- 	hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
- 	hwmgr->pptable_func = &tonga_pptable_funcs;
--
-+	pp_tonga_thermal_initialize(hwmgr);
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index d773d12..44b985a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -426,6 +426,7 @@ int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
- int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
- int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
- int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
-+uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
- 
- #endif
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-new file mode 100644
-index 0000000..a315507
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-@@ -0,0 +1,587 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "tonga_thermal.h"
-+#include "tonga_hwmgr.h"
-+#include "tonga_smumgr.h"
-+#include "tonga_ppsmc.h"
-+#include "smu/smu_7_1_2_d.h"
-+#include "smu/smu_7_1_2_sh_mask.h"
-+
-+/**
-+* Get Fan Speed Control Parameters.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pSpeed is the address of the structure where the result is to be placed.
-+* @exception Always succeeds except if we cannot zero out the output structure.
-+*/
-+int tonga_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info)
-+{
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	fan_speed_info->supports_percent_read = true;
-+	fan_speed_info->supports_percent_write = true;
-+	fan_speed_info->min_percent = 0;
-+	fan_speed_info->max_percent = 100;
-+
-+	if (0 != hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
-+		fan_speed_info->supports_rpm_read = true;
-+		fan_speed_info->supports_rpm_write = true;
-+		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
-+		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
-+	} else {
-+		fan_speed_info->min_rpm = 0;
-+		fan_speed_info->max_rpm = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Get Fan Speed in percent.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pSpeed is the address of the structure where the result is to be placed.
-+* @exception Fails is the 100% setting appears to be 0.
-+*/
-+int tonga_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
-+	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_STATUS, FDO_PWM_DUTY);
-+
-+	if (0 == duty100)
-+		return -EINVAL;
-+
-+
-+	tmp64 = (uint64_t)duty * 100;
-+	do_div(tmp64, duty100);
-+	*speed = (uint32_t)tmp64;
-+
-+	if (*speed > 100)
-+		*speed = 100;
-+
-+	return 0;
-+}
-+
-+/**
-+* Get Fan Speed in RPM.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the address of the structure where the result is to be placed.
-+* @exception Returns not supported if no fan is found or if pulses per revolution are not set
-+*/
-+int tonga_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
-+{
-+	return 0;
-+}
-+
-+/**
-+* Set Fan Speed Control to static mode, so that the user can decide what speed to use.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*           mode    the fan control mode, 0 default, 1 by percent, 5, by RPM
-+* @exception Should always succeed.
-+*/
-+int tonga_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+
-+	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+		hwmgr->fan_ctrl_default_mode = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE);
-+		hwmgr->tmin = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN);
-+		hwmgr->fan_ctrl_is_in_default_mode = false;
-+	}
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN, 0);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE, mode);
-+
-+	return 0;
-+}
-+
-+/**
-+* Reset Fan Speed Control to default mode.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Should always succeed.
-+*/
-+int tonga_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN, hwmgr->tmin);
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	}
-+
-+	return 0;
-+}
-+
-+int tonga_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
-+		result = (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl) == 0) ?  0 : -EINVAL;
-+/*
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_FanSpeedInTableIsRPM))
-+			hwmgr->set_max_fan_rpm_output(hwmgr, hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM);
-+		else
-+			hwmgr->set_max_fan_pwm_output(hwmgr, hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM);
-+*/
-+	} else {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
-+		result = (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl) == 0) ?  0 : -EINVAL;
-+	}
-+/* TO DO FOR SOME DEVICE ID 0X692b, send this msg return invalid command.
-+	if (result == 0 && hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature != 0)
-+		result = (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanTemperatureTarget, \
-+								hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature) ? 0 : -EINVAL);
-+*/
-+	return result;
-+}
-+
-+
-+int tonga_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl) == 0) ?  0 : -EINVAL;
-+}
-+
-+/**
-+* Set Fan Speed in percent.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (0% - 100%) to be set.
-+* @exception Fails is the 100% setting appears to be 0.
-+*/
-+int tonga_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return -EINVAL;
-+
-+	if (speed > 100)
-+		speed = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
-+		tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (0 == duty100)
-+		return -EINVAL;
-+
-+	tmp64 = (uint64_t)speed * 100;
-+	do_div(tmp64, duty100);
-+	duty = (uint32_t)tmp64;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
-+
-+	return tonga_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reset Fan Speed to default.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Always succeeds.
-+*/
-+int tonga_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) {
-+		result = tonga_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+		if (0 == result)
-+			result = tonga_fan_ctrl_start_smc_fan_control(hwmgr);
-+	} else
-+		result = tonga_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set Fan Speed in RPM.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (min - max) to be set.
-+* @exception Fails is the speed not lie between min and max.
-+*/
-+int tonga_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
-+{
-+	return 0;
-+}
-+
-+/**
-+* Reads the remote temperature from the SIslands thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int tonga_thermal_get_temperature(struct pp_hwmgr *hwmgr)
-+{
-+	int temp;
-+
-+	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_STATUS, CTF_TEMP);
-+
-+/* Bit 9 means the reading is lower than the lowest usable value. */
-+	if (0 != (0x200 & temp))
-+		temp = TONGA_THERMAL_MAXIMUM_TEMP_READING;
-+	else
-+		temp = (temp & 0x1ff);
-+
-+	temp = temp * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	return temp;
-+}
-+
-+/**
-+* Set the requested temperature range for high and low alert signals
-+*
-+* @param    hwmgr The address of the hardware manager.
-+* @param    range Temperature range to be programmed for high and low alert signals
-+* @exception PP_Result_BadInput if the input data is not valid.
-+*/
-+static int tonga_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, uint32_t low_temp, uint32_t high_temp)
-+{
-+	uint32_t low = TONGA_THERMAL_MINIMUM_ALERT_TEMP * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+	uint32_t high = TONGA_THERMAL_MAXIMUM_ALERT_TEMP * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	if (low < low_temp)
-+		low = low_temp;
-+	if (high > high_temp)
-+		high = high_temp;
-+
-+	if (low > high)
-+		return -EINVAL;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, DIG_THERM_DPM, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs thermal controller one-time setting registers
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int tonga_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	if (0 != hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+						CG_TACH_CTRL, EDGE_PER_REV,
-+						hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
-+
-+	return 0;
-+}
-+
-+/**
-+* Enable thermal alerts on the RV770 thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int tonga_thermal_enable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK);
-+	alert &= ~(TONGA_THERMAL_HIGH_ALERT_MASK | TONGA_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to enable internal thermal interrupts */
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable) == 0) ? 0 : -1;
-+}
-+
-+/**
-+* Disable thermal alerts on the RV770 thermal controller.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int tonga_thermal_disable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK);
-+	alert |= (TONGA_THERMAL_HIGH_ALERT_MASK | TONGA_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to disable internal thermal interrupts */
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable) == 0) ? 0 : -1;
-+}
-+
-+/**
-+* Uninitialize the thermal controller.
-+* Currently just disables alerts.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int tonga_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	int result = tonga_thermal_disable_alert(hwmgr);
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		tonga_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set up the fan table to control the fan using the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (0 == data->fan_table_start) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (0 == duty100) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = tonga_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	fan_table.FanControl_GL_Flag = 1;
-+
-+	res = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), data->sram_end);
-+/* TO DO FOR SOME DEVICE ID 0X692b, send this msg return invalid command.
-+	if (res == 0 && hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit != 0)
-+		res = (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanMinPwm, \
-+						hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit) ? 0 : -1);
-+
-+	if (res == 0 && hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit != 0)
-+		res = (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanSclkTarget, \
-+					hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit) ? 0 : -1);
-+
-+	if (0 != res)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+*/
-+	return 0;
-+}
-+
-+/**
-+* Start the fan control on the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_tonga_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
-+{
-+/* If the fantable setup has failed we could have disabled PHM_PlatformCaps_MicrocodeFanControl even after this function was included in the table.
-+ * Make sure that we still think controlling the fan is OK.
-+*/
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) {
-+		tonga_fan_ctrl_start_smc_fan_control(hwmgr);
-+		tonga_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Set temperature range for high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_tonga_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
-+{
-+	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
-+
-+	if (range == NULL)
-+		return -EINVAL;
-+
-+	return tonga_thermal_set_temperature_range(hwmgr, range->min, range->max);
-+}
-+
-+/**
-+* Programs one-time setting registers
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from initialize thermal controller routine
-+*/
-+int tf_tonga_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
-+{
-+    return tonga_thermal_initialize(hwmgr);
-+}
-+
-+/**
-+* Enable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from enable alert routine
-+*/
-+int tf_tonga_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
-+{
-+	return tonga_thermal_enable_alert(hwmgr);
-+}
-+
-+/**
-+* Disable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from disable alert routine
-+*/
-+static int tf_tonga_thermal_disable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result)
-+{
-+	return tonga_thermal_disable_alert(hwmgr);
-+}
-+
-+static struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = {
-+	{ NULL, tf_tonga_thermal_initialize },
-+	{ NULL, tf_tonga_thermal_set_temperature_range },
-+	{ NULL, tf_tonga_thermal_enable_alert },
-+/* We should restrict performance levels to low before we halt the SMC.
-+ * On the other hand we are still in boot state when we do this so it would be pointless.
-+ * If this assumption changes we have to revisit this table.
-+ */
-+	{ NULL, tf_tonga_thermal_setup_fan_table},
-+	{ NULL, tf_tonga_thermal_start_smc_fan_control},
-+	{ NULL, NULL }
-+};
-+
-+static struct phm_master_table_header tonga_thermal_start_thermal_controller_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	tonga_thermal_start_thermal_controller_master_list
-+};
-+
-+static struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = {
-+	{ NULL, tf_tonga_thermal_disable_alert},
-+	{ NULL, tf_tonga_thermal_set_temperature_range},
-+	{ NULL, tf_tonga_thermal_enable_alert},
-+	{ NULL, NULL }
-+};
-+
-+struct phm_master_table_header tonga_thermal_set_temperature_range_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	tonga_thermal_set_temperature_range_master_list
-+};
-+
-+int tonga_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
-+		tonga_fan_ctrl_set_default_mode(hwmgr);
-+	return 0;
-+}
-+
-+/**
-+* Initializes the thermal controller related functions in the Hardware Manager structure.
-+* @param    hwmgr The address of the hardware manager.
-+* @exception Any error code from the low-level communication.
-+*/
-+int pp_tonga_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	result = phm_construct_table(hwmgr, &tonga_thermal_set_temperature_range_master, &(hwmgr->set_temperature_range));
-+
-+	if (0 == result) {
-+		result = phm_construct_table(hwmgr,
-+						&tonga_thermal_start_thermal_controller_master,
-+						&(hwmgr->start_thermal_controller));
-+		if (0 != result)
-+			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
-+	}
-+
-+	if (0 == result)
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	return result;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h
-new file mode 100644
-index 0000000..07680a7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h
-@@ -0,0 +1,60 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef TONGA_THERMAL_H
-+#define TONGA_THERMAL_H
-+
-+#include "hwmgr.h"
-+
-+#define TONGA_THERMAL_HIGH_ALERT_MASK         0x1
-+#define TONGA_THERMAL_LOW_ALERT_MASK          0x2
-+
-+#define TONGA_THERMAL_MINIMUM_TEMP_READING    -256
-+#define TONGA_THERMAL_MAXIMUM_TEMP_READING    255
-+
-+#define TONGA_THERMAL_MINIMUM_ALERT_TEMP      0
-+#define TONGA_THERMAL_MAXIMUM_ALERT_TEMP      255
-+
-+#define FDO_PWM_MODE_STATIC  1
-+#define FDO_PWM_MODE_STATIC_RPM 5
-+
-+
-+extern int tf_tonga_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_tonga_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_tonga_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+
-+extern int tonga_thermal_get_temperature(struct pp_hwmgr *hwmgr);
-+extern int tonga_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int tonga_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
-+extern int tonga_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int tonga_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
-+extern int tonga_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
-+extern int tonga_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int tonga_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-+extern int pp_tonga_thermal_initialize(struct pp_hwmgr *hwmgr);
-+extern int tonga_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int tonga_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int tonga_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+
-+#endif
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0075-drm-amdgpu-powerplay-implement-fan-control-interface.patch b/common/recipes-kernel/linux/files/0075-drm-amdgpu-powerplay-implement-fan-control-interface.patch
deleted file mode 100644
index 199fc4f6..00000000
--- a/common/recipes-kernel/linux/files/0075-drm-amdgpu-powerplay-implement-fan-control-interface.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From 28a7159e3bba73b4fc12f70f3a5f0d5d1e8b1d3b Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 16 Oct 2015 11:48:21 +0800
-Subject: [PATCH 0075/1110] drm/amdgpu/powerplay: implement fan control
- interface in amd_powerplay_funcs
-
-This adds the interface needed to expose powerplay fan control to sysfs
-via hwmon.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 85 ++++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  4 ++
- 2 files changed, 88 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 66ccfc0..10385c0 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -428,9 +428,88 @@ pp_debugfs_print_current_performance_level(void *handle,
- 	hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
- }
- 
-+static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	  hwmgr->hwmgr_func->set_fan_control_mode == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
-+}
-+
-+static int pp_dpm_get_fan_control_mode(void *handle)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	  hwmgr->hwmgr_func->get_fan_control_mode == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
-+}
-+
-+static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	  hwmgr->hwmgr_func->set_fan_speed_percent == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
-+}
-+
-+static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	  hwmgr->hwmgr_func->get_fan_speed_percent == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
-+}
-+
-+static int pp_dpm_get_temperature(void *handle)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+	  hwmgr->hwmgr_func->get_temperature == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_temperature(hwmgr);
-+}
- 
- const struct amd_powerplay_funcs pp_dpm_funcs = {
--	.get_temperature = NULL,
-+	.get_temperature = pp_dpm_get_temperature,
- 	.load_firmware = pp_dpm_load_fw,
- 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
- 	.force_performance_level = pp_dpm_force_performance_level,
-@@ -442,6 +521,10 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
- 	.powergate_uvd = pp_dpm_powergate_uvd,
- 	.dispatch_tasks = pp_dpm_dispatch_tasks,
- 	.print_current_performance_level = pp_debugfs_print_current_performance_level,
-+	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
-+	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
-+	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
-+	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
- };
- 
- static int amd_pp_instance_init(struct amd_pp_init *pp_init,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index d81b239..40ded67 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -187,6 +187,10 @@ struct amd_powerplay_funcs {
- 				   void *input, void *output);
- 	void (*print_current_performance_level)(void *handle,
- 						      struct seq_file *m);
-+	int (*set_fan_control_mode)(void *handle, uint32_t mode);
-+	int (*get_fan_control_mode)(void *handle);
-+	int (*set_fan_speed_percent)(void *handle, uint32_t percent);
-+	int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
- };
- 
- struct amd_powerplay {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0076-drm-amdgpu-export-fan-control-functions-to-amdgpu.patch b/common/recipes-kernel/linux/files/0076-drm-amdgpu-export-fan-control-functions-to-amdgpu.patch
deleted file mode 100644
index 51411f2f..00000000
--- a/common/recipes-kernel/linux/files/0076-drm-amdgpu-export-fan-control-functions-to-amdgpu.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From fe7fbe019ccec55c37df39d9ab9b16d3fea62a2a Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 15 Oct 2015 17:23:43 +0800
-Subject: [PATCH 0076/1110] drm/amdgpu: export fan control functions to amdgpu
-
-Hook up the amdgpu thermal control callbacks for powerplay.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 30 +++++++++++++++++++++++++-----
- 1 file changed, 25 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 9e12df3..0c66b15 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2268,7 +2268,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
- #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
- #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
--#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
- #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
- #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
- #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
-@@ -2276,10 +2275,31 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
- #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
- #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
--#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
--#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
--#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
--#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
-+
-+#define amdgpu_dpm_get_temperature(adev) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
-+		(adev)->pm.funcs->get_temperature((adev))
-+
-+#define amdgpu_dpm_set_fan_control_mode(adev, m) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
-+		(adev)->pm.funcs->set_fan_control_mode((adev), (m))
-+
-+#define amdgpu_dpm_get_fan_control_mode(adev) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
-+		(adev)->pm.funcs->get_fan_control_mode((adev))
-+
-+#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
-+		(adev)->pm.funcs->set_fan_speed_percent((adev), (s))
-+
-+#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
-+		amdgpu_powerplay ? \
-+		(adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
-+		(adev)->pm.funcs->get_fan_speed_percent((adev), (s))
- 
- #define amdgpu_dpm_get_sclk(adev, l) \
- 		amdgpu_powerplay ? \
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0077-drm-amdgpu-enable-sysfs-interface-for-powerplay.patch b/common/recipes-kernel/linux/files/0077-drm-amdgpu-enable-sysfs-interface-for-powerplay.patch
deleted file mode 100644
index a5b3bef8..00000000
--- a/common/recipes-kernel/linux/files/0077-drm-amdgpu-enable-sysfs-interface-for-powerplay.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From cba61490ee35e59fac852328417517535715f572 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 10 Nov 2015 18:29:11 -0500
-Subject: [PATCH 0077/1110] drm/amdgpu: enable sysfs interface for powerplay
-
-Same interface exposed in pre-powerplay dpm code.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 20 +++++++++++---------
- 1 file changed, 11 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 534bfac..754c169 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -184,10 +184,10 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	int temp;
- 
--	if (adev->pm.funcs->get_temperature)
--		temp = amdgpu_dpm_get_temperature(adev);
--	else
-+	if (!amdgpu_powerplay && !adev->pm.funcs->get_temperature)
- 		temp = 0;
-+	else
-+		temp = amdgpu_dpm_get_temperature(adev);
- 
- 	return snprintf(buf, PAGE_SIZE, "%d\n", temp);
- }
-@@ -215,8 +215,10 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	u32 pwm_mode = 0;
- 
--	if (adev->pm.funcs->get_fan_control_mode)
--		pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
-+	if (!amdgpu_powerplay && !adev->pm.funcs->get_fan_control_mode)
-+		return -EINVAL;
-+
-+	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
- 
- 	/* never 0 (full-speed), fuse or smc-controlled always */
- 	return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
-@@ -231,7 +233,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
- 	int err;
- 	int value;
- 
--	if (!adev->pm.funcs->set_fan_control_mode)
-+	if (!amdgpu_powerplay && !adev->pm.funcs->set_fan_control_mode)
- 		return -EINVAL;
- 
- 	err = kstrtoint(buf, 10, &value);
-@@ -328,9 +330,6 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	umode_t effective_mode = attr->mode;
- 
--	if (amdgpu_powerplay)
--		return 0;  /* to do */
--
- 	/* Skip limit attributes if DPM is not enabled */
- 	if (!adev->pm.dpm_enabled &&
- 	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
-@@ -341,6 +340,9 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
- 	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
- 		return 0;
- 
-+	if (amdgpu_powerplay)
-+		return effective_mode;
-+
- 	/* Skip fan attributes if fan is not present */
- 	if (adev->pm.no_fan &&
- 	    (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0078-drm-amdgpu-support-per-device-powerplay-enablement-v.patch b/common/recipes-kernel/linux/files/0078-drm-amdgpu-support-per-device-powerplay-enablement-v.patch
deleted file mode 100644
index 9b184872..00000000
--- a/common/recipes-kernel/linux/files/0078-drm-amdgpu-support-per-device-powerplay-enablement-v.patch
+++ /dev/null
@@ -1,406 +0,0 @@
-From e3d67c2f684799961df46e685a7808b7f4deb7d3 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Tue, 10 Nov 2015 18:31:08 -0500
-Subject: [PATCH 0078/1110] drm/amdgpu: support per device powerplay enablement
- (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The amdgu_powerplay variable is global for multiple GPU instances.
-
-v2: fold in Flora's module option change, protect adev reference in
-macros
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           | 71 ++++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  4 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        | 30 +++++------
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 15 +++---
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         |  4 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c        |  2 +-
- 6 files changed, 65 insertions(+), 61 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0c66b15..ea4a467 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2049,6 +2049,7 @@ struct amdgpu_device {
- 
- 	/* powerplay */
- 	struct amd_powerplay		powerplay;
-+	bool				pp_enabled;
- 
- 	/* dpm */
- 	struct amdgpu_pm		pm;
-@@ -2277,68 +2278,68 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
- 
- #define amdgpu_dpm_get_temperature(adev) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
--		(adev)->pm.funcs->get_temperature((adev))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
-+	      (adev)->pm.funcs->get_temperature((adev))
- 
- #define amdgpu_dpm_set_fan_control_mode(adev, m) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
--		(adev)->pm.funcs->set_fan_control_mode((adev), (m))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
-+	      (adev)->pm.funcs->set_fan_control_mode((adev), (m))
- 
- #define amdgpu_dpm_get_fan_control_mode(adev) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
--		(adev)->pm.funcs->get_fan_control_mode((adev))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
-+	      (adev)->pm.funcs->get_fan_control_mode((adev))
- 
- #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
--		(adev)->pm.funcs->set_fan_speed_percent((adev), (s))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
-+	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
- 
- #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
--		(adev)->pm.funcs->get_fan_speed_percent((adev), (s))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
-+	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
- 
- #define amdgpu_dpm_get_sclk(adev, l) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
- 		(adev)->pm.funcs->get_sclk((adev), (l))
- 
- #define amdgpu_dpm_get_mclk(adev, l)  \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
--		(adev)->pm.funcs->get_mclk((adev), (l))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
-+	      (adev)->pm.funcs->get_mclk((adev), (l))
- 
- 
- #define amdgpu_dpm_force_performance_level(adev, l) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
--		(adev)->pm.funcs->force_performance_level((adev), (l))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
-+	      (adev)->pm.funcs->force_performance_level((adev), (l))
- 
- #define amdgpu_dpm_powergate_uvd(adev, g) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
--		(adev)->pm.funcs->powergate_uvd((adev), (g))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
-+	      (adev)->pm.funcs->powergate_uvd((adev), (g))
- 
- #define amdgpu_dpm_powergate_vce(adev, g) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
--		(adev)->pm.funcs->powergate_vce((adev), (g))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
-+	      (adev)->pm.funcs->powergate_vce((adev), (g))
- 
- #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
--		amdgpu_powerplay ? \
--		(adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
--		(adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
-+	(adev)->pp_enabled ?						\
-+	      (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
-+	      (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
- 
- #define amdgpu_dpm_get_current_power_state(adev) \
--		(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
-+	(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
- 
- #define amdgpu_dpm_get_performance_level(adev) \
--		(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
-+	(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
- 
--#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
-+#define amdgpu_dpm_dispatch_task(adev, event_id, input, output)		\
- 	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
- 
- #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 8aedfa6..9c1af89 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -82,7 +82,7 @@ int amdgpu_enable_scheduler = 1;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_enable_semaphores = 0;
--int amdgpu_powerplay = 0;
-+int amdgpu_powerplay = -1;
- 
- MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
- module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
-@@ -166,7 +166,7 @@ MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable
- module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable (default))");
-+MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
- module_param_named(powerplay, amdgpu_powerplay, int, 0444);
- #endif
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 754c169..e05ae17 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -36,7 +36,7 @@ static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
- 
- void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
- {
--	if (amdgpu_powerplay)
-+	if (adev->pp_enabled)
- 		/* TODO */
- 		return;
- 
-@@ -60,7 +60,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	enum amd_pm_state_type pm;
- 
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		pm = amdgpu_dpm_get_current_power_state(adev);
- 	} else
- 		pm = adev->pm.dpm.user_state;
-@@ -90,7 +90,7 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
- 		goto fail;
- 	}
- 
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
- 	} else {
- 		mutex_lock(&adev->pm.mutex);
-@@ -113,7 +113,7 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
- 
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		enum amd_dpm_forced_level level;
- 
- 		level = amdgpu_dpm_get_performance_level(adev);
-@@ -151,7 +151,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 		goto fail;
- 	}
- 
--	if (amdgpu_powerplay)
-+	if (adev->pp_enabled)
- 		amdgpu_dpm_force_performance_level(adev, level);
- 	else {
- 		mutex_lock(&adev->pm.mutex);
-@@ -184,7 +184,7 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	int temp;
- 
--	if (!amdgpu_powerplay && !adev->pm.funcs->get_temperature)
-+	if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
- 		temp = 0;
- 	else
- 		temp = amdgpu_dpm_get_temperature(adev);
-@@ -215,7 +215,7 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	u32 pwm_mode = 0;
- 
--	if (!amdgpu_powerplay && !adev->pm.funcs->get_fan_control_mode)
-+	if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
- 		return -EINVAL;
- 
- 	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
-@@ -233,7 +233,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
- 	int err;
- 	int value;
- 
--	if (!amdgpu_powerplay && !adev->pm.funcs->set_fan_control_mode)
-+	if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
- 		return -EINVAL;
- 
- 	err = kstrtoint(buf, 10, &value);
-@@ -340,7 +340,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
- 	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
- 		return 0;
- 
--	if (amdgpu_powerplay)
-+	if (adev->pp_enabled)
- 		return effective_mode;
- 
- 	/* Skip fan attributes if fan is not present */
-@@ -675,7 +675,7 @@ done:
- 
- void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
- {
--	if (amdgpu_powerplay)
-+	if (adev->pp_enabled)
- 		amdgpu_dpm_powergate_uvd(adev, !enable);
- 	else {
- 		if (adev->pm.funcs->powergate_uvd) {
-@@ -702,7 +702,7 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
- 
- void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
- {
--	if (amdgpu_powerplay)
-+	if (adev->pp_enabled)
- 		amdgpu_dpm_powergate_vce(adev, !enable);
- 	else {
- 		if (adev->pm.funcs->powergate_vce) {
-@@ -730,7 +730,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
- {
- 	int i;
- 
--	if (amdgpu_powerplay)
-+	if (adev->pp_enabled)
- 		/* TO DO */
- 		return;
- 
-@@ -746,7 +746,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
- 	if (adev->pm.sysfs_initialized)
- 		return 0;
- 
--	if (!amdgpu_powerplay) {
-+	if (!adev->pp_enabled) {
- 		if (adev->pm.funcs->get_temperature == NULL)
- 			return 0;
- 	}
-@@ -799,7 +799,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
- 	if (!adev->pm.dpm_enabled)
- 		return;
- 
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		int i = 0;
- 
- 		amdgpu_display_bandwidth_update(adev);
-@@ -853,7 +853,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
- 		seq_printf(m, "dpm not enabled\n");
- 		return 0;
- 	}
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
- 	} else {
- 		mutex_lock(&adev->pm.mutex);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 1ff6fd5..6b46fbf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -40,7 +40,7 @@ static int amdgpu_powerplay_init(struct amdgpu_device *adev)
- 
- 	amd_pp = &(adev->powerplay);
- 
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 		struct amd_pp_init *pp_init;
- 
-@@ -100,11 +100,14 @@ static int amdgpu_pp_early_init(void *handle)
- 	switch (adev->asic_type) {
- 		case CHIP_TONGA:
- 		case CHIP_FIJI:
--			amdgpu_powerplay = 1;
-+			adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
- 			break;
- 		default:
-+			adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
- 			break;
- 	}
-+#else
-+	adev->pp_enabled = false;
- #endif
- 
- 	ret = amdgpu_powerplay_init(adev);
-@@ -127,7 +130,7 @@ static int amdgpu_pp_sw_init(void *handle)
- 					adev->powerplay.pp_handle);
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		adev->pm.dpm_enabled = true;
- 		amdgpu_pm_sysfs_init(adev);
- 	}
-@@ -148,7 +151,7 @@ static int amdgpu_pp_sw_fini(void *handle)
- 		return ret;
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (amdgpu_powerplay) {
-+	if (adev->pp_enabled) {
- 		amdgpu_pm_sysfs_fini(adev);
- 		amd_powerplay_fini(adev->powerplay.pp_handle);
- 	}
-@@ -162,7 +165,7 @@ static int amdgpu_pp_hw_init(void *handle)
- 	int ret = 0;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (amdgpu_powerplay && adev->firmware.smu_load)
-+	if (adev->pp_enabled && adev->firmware.smu_load)
- 		amdgpu_ucode_init_bo(adev);
- 
- 	if (adev->powerplay.ip_funcs->hw_init)
-@@ -181,7 +184,7 @@ static int amdgpu_pp_hw_fini(void *handle)
- 		ret = adev->powerplay.ip_funcs->hw_fini(
- 					adev->powerplay.pp_handle);
- 
--	if (amdgpu_powerplay && adev->firmware.smu_load)
-+	if (adev->pp_enabled && adev->firmware.smu_load)
- 		amdgpu_ucode_fini_bo(adev);
- 
- 	return ret;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 23fde5b..2fda19c 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2902,7 +2902,7 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
- 
- 	gfx_v8_0_rlc_reset(adev);
- 
--	if (!amdgpu_powerplay) {
-+	if (!adev->pp_enabled) {
- 		if (!adev->firmware.smu_load) {
- 			/* legacy rlc firmware loading */
- 			r = gfx_v8_0_rlc_load_microcode(adev);
-@@ -3804,7 +3804,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
- 	if (!(adev->flags & AMD_IS_APU))
- 		gfx_v8_0_enable_gui_idle_interrupt(adev, false);
- 
--	if (!amdgpu_powerplay) {
-+	if (!adev->pp_enabled) {
- 		if (!adev->firmware.smu_load) {
- 			/* legacy firmware loading */
- 			r = gfx_v8_0_cp_gfx_load_microcode(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 8091c1c..c741c09 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -727,7 +727,7 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
- {
- 	int r, i;
- 
--	if (!amdgpu_powerplay) {
-+	if (!adev->pp_enabled) {
- 		if (!adev->firmware.smu_load) {
- 			r = sdma_v3_0_load_microcode(adev);
- 			if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0079-drm-amd-powerplay-add-and-export-hwmgr-interface-to-.patch b/common/recipes-kernel/linux/files/0079-drm-amd-powerplay-add-and-export-hwmgr-interface-to-.patch
deleted file mode 100644
index 157a7c10..00000000
--- a/common/recipes-kernel/linux/files/0079-drm-amd-powerplay-add-and-export-hwmgr-interface-to-.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 962df00d7b3b3ff73130c618228f0e4ffe98d3b3 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 4 Nov 2015 11:07:34 +0800
-Subject: [PATCH 0079/1110] drm/amd/powerplay: add and export hwmgr interface
- to eventmgr to check hw states.
-
-Interface between hwmgr and eventmgr.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c   | 21 +++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h |  8 ++++++++
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h           |  5 +++++
- 3 files changed, 34 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 9d910f3..f2d603c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -223,3 +223,24 @@ int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRa
- 
- 	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
- }
-+
-+
-+bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr == NULL || hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
-+}
-+
-+
-+int phm_check_states_equal(struct pp_hwmgr *hwmgr,
-+				 const struct pp_hw_power_state *pstate1,
-+				 const struct pp_hw_power_state *pstate2,
-+				 bool *equal)
-+{
-+	if (hwmgr == NULL || hwmgr->hwmgr_func->check_states_equal == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index a868110..a3f7bd2 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -322,6 +322,7 @@ struct phm_clocks {
- 	uint32_t num_of_entries;
- 	uint32_t clock[MAX_NUM_CLOCKS];
- };
-+
- extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
- extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
- extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
-@@ -345,5 +346,12 @@ extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hw
- extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
- extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
- extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
-+
-+extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
-+				 const struct pp_hw_power_state *pstate1,
-+				 const struct pp_hw_power_state *pstate2,
-+				 bool *equal);
-+
- #endif /* _HARDWARE_MANAGER_H_ */
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index aedb1e4..5b5c94d 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -307,6 +307,11 @@ struct pp_hwmgr_func {
- 	int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
- 	int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
- 					const void *thermal_interrupt_info);
-+	bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
-+	int (*check_states_equal)(struct pp_hwmgr *hwmgr,
-+					const struct pp_hw_power_state *pstate1,
-+					const struct pp_hw_power_state *pstate2,
-+					bool *equal);
- };
- 
- struct pp_table_func {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0080-drm-amd-powerplay-implement-new-funcs-to-check-curre.patch b/common/recipes-kernel/linux/files/0080-drm-amd-powerplay-implement-new-funcs-to-check-curre.patch
deleted file mode 100644
index 91b44f36..00000000
--- a/common/recipes-kernel/linux/files/0080-drm-amd-powerplay-implement-new-funcs-to-check-curre.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 8136f4f187c29addca5cbc3dda253ecda976bdc3 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 4 Nov 2015 11:21:35 +0800
-Subject: [PATCH 0080/1110] drm/amd/powerplay: implement new funcs to check
- current states for tonga.
-
-Implement the new callbacks for tonga.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 62 +++++++++++++++++++++++
- 1 file changed, 62 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 088b5bf..9a1e8bf 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -5935,6 +5935,66 @@ int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
-+bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	bool is_update_required = false;
-+	struct cgs_display_info info = {0,0,NULL};
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		is_update_required = true;
-+/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
-+	if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+		cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
-+		if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
-+			is_update_required = true;
-+*/
-+	return is_update_required;
-+}
-+
-+static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
-+							   const struct tonga_performance_level *pl2)
-+{
-+	return ((pl1->memory_clock == pl2->memory_clock) &&
-+		  (pl1->engine_clock == pl2->engine_clock) &&
-+		  (pl1->pcie_gen == pl2->pcie_gen) &&
-+		  (pl1->pcie_lane == pl2->pcie_lane));
-+}
-+
-+int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
-+{
-+	const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
-+	const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
-+	int i;
-+
-+	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
-+		return -EINVAL;
-+
-+	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
-+	if (psa->performance_level_count != psb->performance_level_count) {
-+		*equal = false;
-+		return 0;
-+	}
-+
-+	for (i = 0; i < psa->performance_level_count; i++) {
-+		if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
-+			/* If we have found even one performance level pair that is different the states are different. */
-+			*equal = false;
-+			return 0;
-+		}
-+	}
-+
-+	/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
-+	*equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
-+	*equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
-+	*equal &= (psa->sclk_threshold == psb->sclk_threshold);
-+	*equal &= (psa->acp_clk == psb->acp_clk);
-+
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.backend_init = &tonga_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -5968,6 +6028,8 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
- 	.uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
- 	.register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
-+	.check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
-+	.check_states_equal = tonga_check_states_equal,
- };
- 
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0081-drm-amd-powerplay-refine-the-logic-of-whether-need-t.patch b/common/recipes-kernel/linux/files/0081-drm-amd-powerplay-refine-the-logic-of-whether-need-t.patch
deleted file mode 100644
index 08dbb486..00000000
--- a/common/recipes-kernel/linux/files/0081-drm-amd-powerplay-refine-the-logic-of-whether-need-t.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 5b1f18ef440591637603496b299e942278ca17b3 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 4 Nov 2015 14:56:56 +0800
-Subject: [PATCH 0081/1110] drm/amd/powerplay: refine the logic of whether need
- to update power state.
-
-Better handle power state changes.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.c | 13 ++++++++++---
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.h |  1 +
- 2 files changed, 11 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-index 08b75bd..82774ac 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-@@ -86,9 +86,10 @@ int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *stat
- int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
- {
- 
--	const struct pp_power_state  *pcurrent;
--	struct pp_power_state  *requested;
-+	struct pp_power_state *pcurrent;
-+	struct pp_power_state *requested;
- 	struct pp_hwmgr *hwmgr;
-+	bool equal;
- 
- 	if (skip)
- 		return 0;
-@@ -97,7 +98,13 @@ int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
- 	pcurrent = hwmgr->current_ps;
- 	requested = hwmgr->request_ps;
- 
--	if ((pcurrent != NULL || requested != NULL) && (pcurrent != requested)) {
-+	if (requested == NULL)
-+		return 0;
-+
-+	if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr, &pcurrent->hardware, &requested->hardware, &equal)))
-+		equal = false;
-+
-+	if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
- 		phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
- 		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
- 		hwmgr->current_ps = requested;
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-index 15abfac..1380470 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-@@ -25,6 +25,7 @@
- #include "eventmanagement.h"
- #include "eventmanager.h"
- #include "power_state.h"
-+#include "hardwaremanager.h"
- 
- int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label, unsigned long *state_id);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0082-drm-amd-powerplay-tonga-enable-pcie-and-mclk-forcing.patch b/common/recipes-kernel/linux/files/0082-drm-amd-powerplay-tonga-enable-pcie-and-mclk-forcing.patch
deleted file mode 100644
index 36970174..00000000
--- a/common/recipes-kernel/linux/files/0082-drm-amd-powerplay-tonga-enable-pcie-and-mclk-forcing.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 2e347265e9c5799e88d1b6ec8656073fe2ff9a17 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 00:23:57 -0500
-Subject: [PATCH 0082/1110] drm/amd/powerplay/tonga: enable pcie and mclk
- forcing for low
-
-When forcing the lowest state also force mclk and pcie.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 48 +++++++++++++++++------
- 1 file changed, 37 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 9a1e8bf..a9cc786 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -3279,7 +3279,7 @@ int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
- 				if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
- 					printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
--						Curr_Sclk_Index does not match the level \n");
-+						Curr_Mclk_Index does not match the level \n");
- 			}
- 		}
- 	}
-@@ -3424,21 +3424,47 @@ static uint32_t tonga_get_lowest_enable_level(
- 
- static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
- {
--	uint32_t level = 0;
-+	uint32_t level;
- 	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
- 
--	/* for now force only sclk */
--	if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
--		level = tonga_get_lowest_enable_level(hwmgr,
--					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		/* PCIE */
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
-+			level = tonga_get_lowest_enable_level(hwmgr,
-+							      data->dpm_level_enable_mask.pcie_dpm_enable_mask);
-+			PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
-+					    "force lowest pcie dpm state failed!", return -1);
-+		}
-+	}
-+
-+	if (0 == data->sclk_dpm_key_disabled) {
-+		/* SCLK */
-+		if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = tonga_get_lowest_enable_level(hwmgr,
-+							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
- 
--		PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
--			"force sclk dpm state failed!", return -1);
-+			PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
-+					    "force sclk dpm state failed!", return -1);
- 
--		if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
--			CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
--			printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index.	\
-+			if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-+							 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
-+				printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index.	\
- 				Curr_Sclk_Index does not match the level \n");
-+		}
-+	}
-+
-+	if (0 == data->mclk_dpm_key_disabled) {
-+		/* MCLK */
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
-+			level = tonga_get_lowest_enable_level(hwmgr,
-+							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+			PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
-+					    "force lowest mclk dpm state failed!", return -1);
-+			if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+							 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
-+				printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
-+						Curr_Mclk_Index does not match the level \n");
-+		}
- 	}
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch b/common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch
deleted file mode 100644
index 1ec5c7d2..00000000
--- a/common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From b0d91d2c1134404fb066c8ad0bd781e9fea591f4 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 00:31:00 -0500
-Subject: [PATCH 0083/1110] drm/amd/powerplay/fiji: enable pcie and mclk
- forcing for low
-
-When forcing the lowest state also force mclk and pcie.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 30 ++++++++++++++++++++----
- 1 file changed, 25 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 4457878..adcc2f0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -3576,18 +3576,38 @@ static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
- {
- 	struct fiji_hwmgr *data =
- 			(struct fiji_hwmgr *)(hwmgr->backend);
--	uint32_t level = 0;
-+	uint32_t level;
- 
--	/* Only force sclk for now */
- 	if (!data->sclk_dpm_key_disabled)
- 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
- 			level = fiji_get_lowest_enabled_level(hwmgr,
--					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					(1 << level));
-+							    PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+							    (1 << level));
-+
-+	}
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			level = fiji_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+							    (1 << level));
-+		}
-+	}
- 
-+	if (!data->pcie_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-+			level = fiji_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.pcie_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_PCIeDPM_ForceLevel,
-+							    (1 << level));
-+		}
- 	}
-+
- 	return 0;
- 
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0084-drm-amdgpu-extract-pcie-helpers-to-common-header.patch b/common/recipes-kernel/linux/files/0084-drm-amdgpu-extract-pcie-helpers-to-common-header.patch
deleted file mode 100644
index cd04d00d..00000000
--- a/common/recipes-kernel/linux/files/0084-drm-amdgpu-extract-pcie-helpers-to-common-header.patch
+++ /dev/null
@@ -1,417 +0,0 @@
-From 986a3342190c5e0526a88ec408d1b23682171fc2 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 20:18:52 -0500
-Subject: [PATCH 0084/1110] drm/amdgpu: extract pcie helpers to common header
-
-These will be used by multiple powerplay drivers and
-other IP modules.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/amd_pcie.h            |  50 ++++++++
- drivers/gpu/drm/amd/include/amd_pcie_helpers.h    | 141 ++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c  |   1 +
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h  |   2 -
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 112 +----------------
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h |  24 ----
- 6 files changed, 193 insertions(+), 137 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/include/amd_pcie.h
- create mode 100644 drivers/gpu/drm/amd/include/amd_pcie_helpers.h
-
-diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
-new file mode 100644
-index 0000000..7c2a916
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/amd_pcie.h
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef __AMD_PCIE_H__
-+#define __AMD_PCIE_H__
-+
-+/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
-+#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
-+
-+/* Following flags shows PCIe link speed supported by ASIC H/W.*/
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
-+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
-+
-+/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
-+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
-new file mode 100644
-index 0000000..2cfdf05
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
-@@ -0,0 +1,141 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef __AMD_PCIE_HELPERS_H__
-+#define __AMD_PCIE_HELPERS_H__
-+
-+#include "amd_pcie.h"
-+
-+static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
-+{
-+	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
-+{
-+	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
-+static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
-+					    uint16_t ns_pcie_gen)
-+{
-+	uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
-+		CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
-+	uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
-+		CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
-+
-+	switch (asic_pcie_link_speed_cap) {
-+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
-+		return PP_PCIEGen1;
-+
-+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
-+		return PP_PCIEGen2;
-+
-+	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
-+		return PP_PCIEGen3;
-+
-+	default:
-+		if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
-+			(ns_pcie_gen == PP_PCIEGen3)) {
-+			return PP_PCIEGen3;
-+		} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
-+			((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
-+			return PP_PCIEGen2;
-+		}
-+	}
-+
-+	return PP_PCIEGen1;
-+}
-+
-+static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
-+					     uint16_t ns_pcie_lanes)
-+{
-+	int i, j;
-+	uint16_t new_pcie_lanes = ns_pcie_lanes;
-+	uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
-+
-+	switch (pcie_lane_width_cap) {
-+	case 0:
-+		printk(KERN_ERR "No valid PCIE lane width reported");
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
-+		new_pcie_lanes = 1;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
-+		new_pcie_lanes = 2;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
-+		new_pcie_lanes = 4;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
-+		new_pcie_lanes = 8;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
-+		new_pcie_lanes = 12;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
-+		new_pcie_lanes = 16;
-+		break;
-+	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
-+		new_pcie_lanes = 32;
-+		break;
-+	default:
-+		for (i = 0; i < 7; i++) {
-+			if (ns_pcie_lanes == pcie_lanes[i]) {
-+				if (pcie_lane_width_cap & (0x10000 << i)) {
-+					break;
-+				} else {
-+					for (j = i - 1; j >= 0; j--) {
-+						if (pcie_lane_width_cap & (0x10000 << j)) {
-+							new_pcie_lanes = pcie_lanes[j];
-+							break;
-+						}
-+					}
-+
-+					if (j < 0) {
-+						for (j = i + 1; j < 7; j++) {
-+							if (pcie_lane_width_cap & (0x10000 << j)) {
-+								new_pcie_lanes = pcie_lanes[j];
-+								break;
-+							}
-+						}
-+						if (j > 7)
-+							printk(KERN_ERR "Cannot find a valid PCIE lane width!");
-+					}
-+				}
-+				break;
-+			}
-+		}
-+		break;
-+	}
-+
-+	return new_pcie_lanes;
-+}
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index adcc2f0..ccbdbef 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -49,6 +49,7 @@
- #include "tonga_pptable.h"
- #include "pp_debug.h"
- #include "pp_acpi.h"
-+#include "amd_pcie_helpers.h"
- 
- #define VOLTAGE_SCALE	4
- #define SMC_RAM_END		0x40000
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-index 38dbe49..22d985e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -339,8 +339,6 @@ enum Fiji_I2CLineID {
- extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
- extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
- extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
--extern uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen);
--extern uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes);
- 
- #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
- #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index a9cc786..9442313 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -53,6 +53,7 @@
- 
- #include "cgs_linux.h"
- #include "eventmgr.h"
-+#include "amd_pcie_helpers.h"
- 
- #define MC_CG_ARB_FREQ_F0           0x0a
- #define MC_CG_ARB_FREQ_F1           0x0b
-@@ -2651,117 +2652,6 @@ static void tonga_setup_pcie_table_entry(
- 	dpm_table->dpm_levels[index].enabled = 1;
- }
- 
--bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
--{
--	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
--		return 1;
--
--	return 0;
--}
--
--bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
--{
--	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
--		return 1;
--
--	return 0;
--}
--
--/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
--uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap, uint16_t ns_pcie_gen)
--{
--	uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
--		CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
--	uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
--		CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
--
--	switch (asic_pcie_link_speed_cap) {
--	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
--		return PP_PCIEGen1;
--
--	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
--		return PP_PCIEGen2;
--
--	case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
--		return PP_PCIEGen3;
--
--	default:
--		if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
--			(ns_pcie_gen == PP_PCIEGen3)) {
--			return PP_PCIEGen3;
--		} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
--			((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
--			return PP_PCIEGen2;
--		}
--	}
--
--	return PP_PCIEGen1;
--}
--
--uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, uint16_t ns_pcie_lanes)
--{
--	int i, j;
--	uint16_t new_pcie_lanes = ns_pcie_lanes;
--	uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
--
--	switch (pcie_lane_width_cap) {
--	case 0:
--		printk(KERN_ERR "[ powerplay ] No valid PCIE lane width reported by CAIL!");
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
--		new_pcie_lanes = 1;
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
--		new_pcie_lanes = 2;
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
--		new_pcie_lanes = 4;
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
--		new_pcie_lanes = 8;
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
--		new_pcie_lanes = 12;
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
--		new_pcie_lanes = 16;
--		break;
--	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
--		new_pcie_lanes = 32;
--		break;
--	default:
--		for (i = 0; i < 7; i++) {
--			if (ns_pcie_lanes == pcie_lanes[i]) {
--				if (pcie_lane_width_cap & (0x10000 << i)) {
--					break;
--				} else {
--					for (j = i - 1; j >= 0; j--) {
--						if (pcie_lane_width_cap & (0x10000 << j)) {
--							new_pcie_lanes = pcie_lanes[j];
--							break;
--						}
--					}
--
--					if (j < 0) {
--						for (j = i + 1; j < 7; j++) {
--							if (pcie_lane_width_cap & (0x10000 << j)) {
--								new_pcie_lanes = pcie_lanes[j];
--								break;
--							}
--						}
--						if (j > 7)
--							printk(KERN_ERR "[ powerplay ] Cannot find a valid PCIE lane width!");
--					}
--				}
--				break;
--			}
--		}
--		break;
--	}
--
--	return new_pcie_lanes;
--}
--
- static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
- {
- 	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index 44b985a..49168d2 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -386,30 +386,6 @@ typedef struct tonga_hwmgr tonga_hwmgr;
- 
- #define TONGA_UNUSED_GPIO_PIN                        0x7F
- 
--/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
--#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
--#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
--#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
--#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
--#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
--
--/* Following flags shows PCIe link speed supported by ASIC H/W.*/
--#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
--#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
--#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
--#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
--#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
--
--/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
--#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
--
- #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
- #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0085-drm-amdgpu-store-pcie-gen-mask-and-link-width.patch b/common/recipes-kernel/linux/files/0085-drm-amdgpu-store-pcie-gen-mask-and-link-width.patch
deleted file mode 100644
index a98697e5..00000000
--- a/common/recipes-kernel/linux/files/0085-drm-amdgpu-store-pcie-gen-mask-and-link-width.patch
+++ /dev/null
@@ -1,258 +0,0 @@
-From 762e824be90ff30e6329bfb0ad0b98e628a22f1b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 19:45:06 -0500
-Subject: [PATCH 0085/1110] drm/amdgpu: store pcie gen mask and link width
-
-We'll need this later for pcie dpm.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 78 ++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/cik.c           | 24 ++++-----
- drivers/gpu/drm/amd/amdgpu/vi.c            | 13 ++---
- 4 files changed, 99 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index ea4a467..4a4ddb6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1645,8 +1645,12 @@ struct amdgpu_pm {
- 	const struct firmware	*fw;	/* SMC firmware */
- 	uint32_t                fw_version;
- 	const struct amdgpu_dpm_funcs *funcs;
-+	uint32_t                pcie_gen_mask;
-+	uint32_t                pcie_mlw_mask;
- };
- 
-+void amdgpu_get_pcie_info(struct amdgpu_device *adev);
-+
- /*
-  * UVD
-  */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index a138f69..e8905be 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -38,6 +38,7 @@
- #include "amdgpu_i2c.h"
- #include "atom.h"
- #include "amdgpu_atombios.h"
-+#include "amd_pcie.h"
- #ifdef CONFIG_DRM_AMDGPU_CIK
- #include "cik.h"
- #endif
-@@ -1937,6 +1938,83 @@ retry:
- 	return r;
- }
- 
-+void amdgpu_get_pcie_info(struct amdgpu_device *adev)
-+{
-+	u32 mask;
-+	int ret;
-+
-+	if (pci_is_root_bus(adev->pdev->bus))
-+		return;
-+
-+	if (amdgpu_pcie_gen2 == 0)
-+		return;
-+
-+	if (adev->flags & AMD_IS_APU)
-+		return;
-+
-+	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-+	if (!ret) {
-+		adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
-+					  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-+					  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
-+
-+		if (mask & DRM_PCIE_SPEED_25)
-+			adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
-+		if (mask & DRM_PCIE_SPEED_50)
-+			adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
-+		if (mask & DRM_PCIE_SPEED_80)
-+			adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
-+	}
-+	ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
-+	if (!ret) {
-+		switch (mask) {
-+		case 32:
-+			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+			break;
-+		case 16:
-+			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+			break;
-+		case 12:
-+			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+			break;
-+		case 8:
-+			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+			break;
-+		case 4:
-+			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+			break;
-+		case 2:
-+			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+			break;
-+		case 1:
-+			adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+}
- 
- /*
-  * Debugfs
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index c7c298b..fd9c958 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -32,6 +32,7 @@
- #include "amdgpu_vce.h"
- #include "cikd.h"
- #include "atom.h"
-+#include "amd_pcie.h"
- 
- #include "cik.h"
- #include "gmc_v7_0.h"
-@@ -1595,8 +1596,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
- {
- 	struct pci_dev *root = adev->pdev->bus->self;
- 	int bridge_pos, gpu_pos;
--	u32 speed_cntl, mask, current_data_rate;
--	int ret, i;
-+	u32 speed_cntl, current_data_rate;
-+	int i;
- 	u16 tmp16;
- 
- 	if (pci_is_root_bus(adev->pdev->bus))
-@@ -1608,23 +1609,20 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
- 	if (adev->flags & AMD_IS_APU)
- 		return;
- 
--	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
--	if (ret != 0)
--		return;
--
--	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
-+	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-+					CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
- 		return;
- 
- 	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
- 	current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
- 		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
--	if (mask & DRM_PCIE_SPEED_80) {
-+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
- 		if (current_data_rate == 2) {
- 			DRM_INFO("PCIE gen 3 link speeds already enabled\n");
- 			return;
- 		}
- 		DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
--	} else if (mask & DRM_PCIE_SPEED_50) {
-+	} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
- 		if (current_data_rate == 1) {
- 			DRM_INFO("PCIE gen 2 link speeds already enabled\n");
- 			return;
-@@ -1640,7 +1638,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
- 	if (!gpu_pos)
- 		return;
- 
--	if (mask & DRM_PCIE_SPEED_80) {
-+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
- 		/* re-try equalization if gen3 is not already enabled */
- 		if (current_data_rate != 2) {
- 			u16 bridge_cfg, gpu_cfg;
-@@ -1735,9 +1733,9 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
- 
- 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
- 	tmp16 &= ~0xf;
--	if (mask & DRM_PCIE_SPEED_80)
-+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
- 		tmp16 |= 3; /* gen3 */
--	else if (mask & DRM_PCIE_SPEED_50)
-+	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
- 		tmp16 |= 2; /* gen2 */
- 	else
- 		tmp16 |= 1; /* gen1 */
-@@ -2450,6 +2448,8 @@ static int cik_common_early_init(void *handle)
- 		return -EINVAL;
- 	}
- 
-+	amdgpu_get_pcie_info(adev);
-+
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 28f07df..8f2c5c9 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -31,6 +31,7 @@
- #include "amdgpu_vce.h"
- #include "amdgpu_ucode.h"
- #include "atom.h"
-+#include "amd_pcie.h"
- 
- #include "gmc/gmc_8_1_d.h"
- #include "gmc/gmc_8_1_sh_mask.h"
-@@ -1053,9 +1054,6 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
- 
- static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
- {
--	u32 mask;
--	int ret;
--
- 	if (pci_is_root_bus(adev->pdev->bus))
- 		return;
- 
-@@ -1065,11 +1063,8 @@ static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
- 	if (adev->flags & AMD_IS_APU)
- 		return;
- 
--	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
--	if (ret != 0)
--		return;
--
--	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
-+	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-+					CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
- 		return;
- 
- 	/* todo */
-@@ -1474,6 +1469,8 @@ static int vi_common_early_init(void *handle)
- 	if (amdgpu_smc_load_fw && smc_enabled)
- 		adev->firmware.smu_load = true;
- 
-+	amdgpu_get_pcie_info(adev);
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0086-drm-amdgpu-cgs-add-sys-info-query-for-pcie-gen-and-l.patch b/common/recipes-kernel/linux/files/0086-drm-amdgpu-cgs-add-sys-info-query-for-pcie-gen-and-l.patch
deleted file mode 100644
index 0296d7a8..00000000
--- a/common/recipes-kernel/linux/files/0086-drm-amdgpu-cgs-add-sys-info-query-for-pcie-gen-and-l.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 95c5ee13242afde54e85f3042bab85204a1da248 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 20:35:32 -0500
-Subject: [PATCH 0086/1110] drm/amdgpu/cgs: add sys info query for pcie gen and
- link width
-
-Needed by powerplay to properly handle pcie dpm switching.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 6 ++++++
- drivers/gpu/drm/amd/include/cgs_common.h | 2 ++
- 2 files changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index a611401..6fa0fea 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -754,6 +754,12 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
- 	case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
- 		sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
- 		break;
-+	case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
-+		sys_info->value = adev->pm.pcie_gen_mask;
-+		break;
-+	case CGS_SYSTEM_INFO_PCIE_MLW:
-+		sys_info->value = adev->pm.pcie_mlw_mask;
-+		break;
- 	default:
- 		return -ENODEV;
- 	}
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 2bbffd1..03affb3 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -107,6 +107,8 @@ enum cgs_ucode_id {
- 
- enum cgs_system_info_id {
- 	CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
-+	CGS_SYSTEM_INFO_PCIE_GEN_INFO,
-+	CGS_SYSTEM_INFO_PCIE_MLW,
- 	CGS_SYSTEM_INFO_ID_MAXIMUM,
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0087-drm-amdgpu-powerplay-tonga-query-supported-pcie-info.patch b/common/recipes-kernel/linux/files/0087-drm-amdgpu-powerplay-tonga-query-supported-pcie-info.patch
deleted file mode 100644
index 886792ae..00000000
--- a/common/recipes-kernel/linux/files/0087-drm-amdgpu-powerplay-tonga-query-supported-pcie-info.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 3816b22b724e0b9b1238c1fd0b9be32736e88839 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 20:58:55 -0500
-Subject: [PATCH 0087/1110] drm/amdgpu/powerplay/tonga: query supported pcie
- info from cgs (v2)
-
-Rather than hardcode it.
-
-v2: integrate spc fix from Rex
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 20 ++++++++++++++++++--
- 1 file changed, 18 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 9442313..bed50e6 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4559,14 +4559,30 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 	data->vddc_phase_shed_control = 0;
- 
- 	if (0 == result) {
-+		struct cgs_system_info sys_info = {0};
-+
- 		data->is_tlu_enabled = 0;
- 		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
- 			TONGA_MAX_HARDWARE_POWERLEVELS;
- 		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
- 		hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
- 
--		data->pcie_gen_cap = 0x30007;
--		data->pcie_lane_cap = 0x2f0000;
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_gen_cap = 0x30007;
-+		else
-+			data->pcie_gen_cap = (uint32_t)sys_info.value;
-+		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-+			data->pcie_spc_cap = 20;
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_lane_cap = 0x2f0000;
-+		else
-+			data->pcie_lane_cap = (uint32_t)sys_info.value;
- 	} else {
- 		/* Ignore return value in here, we are cleaning up a mess. */
- 		tonga_hwmgr_backend_fini(hwmgr);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch b/common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch
deleted file mode 100644
index 3ffc4236..00000000
--- a/common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From b6a83b14bdfdc66d6d25cfc4fe89d61de0560686 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 11 Nov 2015 21:02:16 -0500
-Subject: [PATCH 0088/1110] drm/amdgpu/powerplay/fiji: query supported pcie
- info from cgs (v2)
-
-Rather than hardcode it.
-
-v2: integrate spc fix from Rex
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 20 ++++++++++++++++++--
- 1 file changed, 18 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index ccbdbef..5ef92e1 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -684,14 +684,30 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 			PHM_PlatformCaps_StayInBootState);
- 
- 	if (0 == result) {
-+		struct cgs_system_info sys_info = {0};
-+
- 		data->is_tlu_enabled = 0;
- 		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
- 				FIJI_MAX_HARDWARE_POWERLEVELS;
- 		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
- 		hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
- 
--		data->pcie_gen_cap = 0x30007;
--		data->pcie_lane_cap = 0x2f0000;
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_gen_cap = 0x30007;
-+		else
-+			data->pcie_gen_cap = (uint32_t)sys_info.value;
-+		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-+			data->pcie_spc_cap = 20;
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_lane_cap = 0x2f0000;
-+		else
-+			data->pcie_lane_cap = (uint32_t)sys_info.value;
- 	} else {
- 		/* Ignore return value in here, we are cleaning up a mess. */
- 		tonga_hwmgr_backend_fini(hwmgr);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch b/common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch
deleted file mode 100644
index 073ce483..00000000
--- a/common/recipes-kernel/linux/files/0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From dca6548892286633a1e156079f1043a620ab0ce9 Mon Sep 17 00:00:00 2001
-From: kbuild test robot <fengguang.wu@intel.com>
-Date: Thu, 12 Nov 2015 12:58:34 -0500
-Subject: [PATCH 0089/1110] drm/amd/powerplay: fix boolreturn.cocci warnings
-
-drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_hwmgr.c:2653:9-10: WARNING: return of 0/1 in function 'is_pcie_gen2_supported' with return type bool
-drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/tonga_hwmgr.c:2645:9-10: WARNING: return of 0/1 in function 'is_pcie_gen3_supported' with return type bool
-
- Return statements in functions returning bool should use
- true/false instead of 1/0.
-Generated by: scripts/coccinelle/misc/boolreturn.cocci
-
-CC: yanyang1 <young.yang@amd.com>
-Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/amd_pcie_helpers.h | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
-index 2cfdf05..5725bf8 100644
---- a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
-+++ b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h
-@@ -28,17 +28,17 @@
- static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
- {
- 	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
--		return 1;
-+		return true;
- 
--	return 0;
-+	return false;
- }
- 
- static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
- {
- 	if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
--		return 1;
-+		return true;
- 
--	return 0;
-+	return false;
- }
- 
- /* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0090-drm-amd-powerplay-tonga-Add-UVD-DPM-init.patch b/common/recipes-kernel/linux/files/0090-drm-amd-powerplay-tonga-Add-UVD-DPM-init.patch
deleted file mode 100644
index 45ea0dfd..00000000
--- a/common/recipes-kernel/linux/files/0090-drm-amd-powerplay-tonga-Add-UVD-DPM-init.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 4999dcd121f8ab7b5b2e7702f67ff1c33e50a0df Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 13 Nov 2015 10:46:30 -0500
-Subject: [PATCH 0090/1110] drm/amd/powerplay/tonga: Add UVD DPM init
-
-Load the UVD DPM state into the SMC.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 56 +++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index bed50e6..2348d8c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -1639,6 +1639,58 @@ static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_
- 	return 0;
- }
- 
-+static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+					SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
-+
-+	table->UvdLevelCount = (uint8_t) (mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage.Vddc =
-+			tonga_get_voltage_index(pptable_info->vddc_lookup_table,
-+						mm_table->entries[count].vddc);
-+		table->UvdLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
-+			tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+						mm_table->entries[count].vddgfx) : 0;
-+		table->UvdLevel[count].MinVoltage.Vddci =
-+			tonga_get_voltage_id(&data->vddci_voltage_table,
-+					     mm_table->entries[count].vddc - data->vddc_vddci_delta);
-+		table->UvdLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+							  table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				    "can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+							  table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				    "can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		//CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
-+    }
-+
-+    return result;
-+
-+}
- 
- static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- 		SMU72_Discrete_DpmTable *table)
-@@ -2924,6 +2976,10 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
- 	PP_ASSERT_WITH_CODE(0 == result,
- 		"Failed to Write ARB settings for the initial state.", return result;);
- 
-+	result = tonga_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize UVD Level!", return result;);
-+
- 	result = tonga_populate_smc_boot_level(hwmgr, table);
- 	PP_ASSERT_WITH_CODE(0 == result,
- 		"Failed to initialize Boot Level!", return result;);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0091-drm-amd-amdgpu-add-gfx-clock-gating-support-for-Fiji.patch b/common/recipes-kernel/linux/files/0091-drm-amd-amdgpu-add-gfx-clock-gating-support-for-Fiji.patch
deleted file mode 100644
index 844fa50a..00000000
--- a/common/recipes-kernel/linux/files/0091-drm-amd-amdgpu-add-gfx-clock-gating-support-for-Fiji.patch
+++ /dev/null
@@ -1,291 +0,0 @@
-From f97b219400c277b9e1a397212b6203120e525ef6 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 10 Nov 2015 10:50:25 -0500
-Subject: [PATCH 0091/1110] drm/amd/amdgpu: add gfx clock gating support for
- Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 254 ++++++++++++++++++++++++++++++++++
- 1 file changed, 254 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 2fda19c..42b4203 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -66,6 +66,27 @@
- #define MACRO_TILE_ASPECT(x)				((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
- #define NUM_BANKS(x)					((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
- 
-+#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
-+#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
-+#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
-+#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
-+#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
-+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
-+
-+/* BPM SERDES CMD */
-+#define SET_BPM_SERDES_CMD    1
-+#define CLE_BPM_SERDES_CMD    0
-+
-+/* BPM Register Address*/
-+enum {
-+	BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
-+	BPM_REG_CGLS_ON,            /* ON/OFF CGLS: shall be controlled by RLC FW */
-+	BPM_REG_CGCG_OVERRIDE,      /* Set/Clear CGCG Override */
-+	BPM_REG_MGCG_OVERRIDE,      /* Set/Clear MGCG Override */
-+	BPM_REG_FGCG_OVERRIDE,      /* Set/Clear FGCG Override */
-+	BPM_REG_FGCG_MAX
-+};
-+
- MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
- MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
- MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
-@@ -4301,9 +4322,242 @@ static int gfx_v8_0_set_powergating_state(void *handle,
- 	return 0;
- }
- 
-+static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
-+		uint32_t reg_addr, uint32_t cmd)
-+{
-+	uint32_t data;
-+
-+	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-+
-+	WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
-+	WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
-+
-+	data = RREG32(mmRLC_SERDES_WR_CTRL);
-+	data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
-+			RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
-+			RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
-+			RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
-+			RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
-+			RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
-+			RLC_SERDES_WR_CTRL__POWER_UP_MASK |
-+			RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
-+			RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
-+			RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
-+			RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
-+	data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
-+			(cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
-+			(reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
-+			(0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
-+
-+	WREG32(mmRLC_SERDES_WR_CTRL, data);
-+}
-+
-+static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	/* It is disabled by HW by default */
-+	if (enable) {
-+		/* 1 - RLC memory Light sleep */
-+		temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
-+		data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
-+		if (temp != data)
-+			WREG32(mmRLC_MEM_SLP_CNTL, data);
-+
-+		/* 2 - CP memory Light sleep */
-+		temp = data = RREG32(mmCP_MEM_SLP_CNTL);
-+		data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
-+		if (temp != data)
-+			WREG32(mmCP_MEM_SLP_CNTL, data);
-+
-+		/* 3 - RLC_CGTT_MGCG_OVERRIDE */
-+		temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-+		data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
-+
-+		if (temp != data)
-+			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
-+
-+		/* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+
-+		/* 5 - clear mgcg override */
-+		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
-+
-+		/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
-+		temp = data = RREG32(mmCGTS_SM_CTRL_REG);
-+		data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
-+		data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
-+		data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
-+		data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
-+		data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
-+		data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
-+		data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
-+		if (temp != data)
-+			WREG32(mmCGTS_SM_CTRL_REG, data);
-+		udelay(50);
-+
-+		/* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+	} else {
-+		/* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
-+		temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-+		data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
-+		if (temp != data)
-+			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
-+
-+		/* 2 - disable MGLS in RLC */
-+		data = RREG32(mmRLC_MEM_SLP_CNTL);
-+		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
-+			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
-+			WREG32(mmRLC_MEM_SLP_CNTL, data);
-+		}
-+
-+		/* 3 - disable MGLS in CP */
-+		data = RREG32(mmCP_MEM_SLP_CNTL);
-+		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
-+			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
-+			WREG32(mmCP_MEM_SLP_CNTL, data);
-+		}
-+
-+		/* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
-+		temp = data = RREG32(mmCGTS_SM_CTRL_REG);
-+		data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
-+				CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
-+		if (temp != data)
-+			WREG32(mmCGTS_SM_CTRL_REG, data);
-+
-+		/* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+
-+		/* 6 - set mgcg override */
-+		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
-+
-+		udelay(50);
-+
-+		/* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+	}
-+}
-+
-+static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, temp1, data, data1;
-+
-+	temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
-+
-+	if (enable) {
-+		/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
-+		 * Cmp_busy/GFX_Idle interrupts
-+		 */
-+		gfx_v8_0_enable_gui_idle_interrupt(adev, true);
-+
-+		temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-+		data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
-+		if (temp1 != data1)
-+			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
-+
-+		/* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+
-+		/* 3 - clear cgcg override */
-+		fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
-+
-+		/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+
-+		/* 4 - write cmd to set CGLS */
-+		fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
-+
-+		/* 5 - enable cgcg */
-+		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
-+
-+		/* enable cgls*/
-+		data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
-+
-+		temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-+		data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
-+
-+		if (temp1 != data1)
-+			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
-+
-+		if (temp != data)
-+			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
-+	} else {
-+		/* disable cntx_empty_int_enable & GFX Idle interrupt */
-+		gfx_v8_0_enable_gui_idle_interrupt(adev, false);
-+
-+		/* TEST CGCG */
-+		temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-+		data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
-+				RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
-+		if (temp1 != data1)
-+			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
-+
-+		/* read gfx register to wake up cgcg */
-+		RREG32(mmCB_CGTT_SCLK_CTRL);
-+		RREG32(mmCB_CGTT_SCLK_CTRL);
-+		RREG32(mmCB_CGTT_SCLK_CTRL);
-+		RREG32(mmCB_CGTT_SCLK_CTRL);
-+
-+		/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+
-+		/* write cmd to Set CGCG Overrride */
-+		fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
-+
-+		/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-+		gfx_v8_0_wait_for_rlc_serdes(adev);
-+
-+		/* write cmd to Clear CGLS */
-+		fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
-+
-+		/* disable cgcg, cgls should be disabled too. */
-+		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
-+				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
-+		if (temp != data)
-+			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
-+	}
-+}
-+static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	if (enable) {
-+		/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
-+		 * ===  MGCG + MGLS + TS(CG/LS) ===
-+		 */
-+		fiji_update_medium_grain_clock_gating(adev, enable);
-+		fiji_update_coarse_grain_clock_gating(adev, enable);
-+	} else {
-+		/* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
-+		 * ===  CGCG + CGLS ===
-+		 */
-+		fiji_update_coarse_grain_clock_gating(adev, enable);
-+		fiji_update_medium_grain_clock_gating(adev, enable);
-+	}
-+	return 0;
-+}
-+
- static int gfx_v8_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_FIJI:
-+		fiji_update_gfx_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		break;
-+	default:
-+		break;
-+	}
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch b/common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch
deleted file mode 100644
index 1b327cb8..00000000
--- a/common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch
+++ /dev/null
@@ -1,202 +0,0 @@
-From 0690f9c20ec6f732f6f19249bcaef94c12e3b55a Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 10 Nov 2015 11:27:39 -0500
-Subject: [PATCH 0092/1110] drm/amd/amdgpu: add gmc clock gating support for
- Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 172 ++++++++++++++++++++++++++++++++++
- 1 file changed, 172 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 3d4a923..2fcfa97 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -1307,9 +1307,181 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
- 	return 0;
- }
- 
-+static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t data;
-+
-+	if (enable) {
-+		data = RREG32(mmMC_HUB_MISC_HUB_CG);
-+		data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_HUB_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_SIP_CG);
-+		data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_SIP_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_VM_CG);
-+		data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_VM_CG, data);
-+
-+		data = RREG32(mmMC_XPB_CLK_GAT);
-+		data |= MC_XPB_CLK_GAT__ENABLE_MASK;
-+		WREG32(mmMC_XPB_CLK_GAT, data);
-+
-+		data = RREG32(mmATC_MISC_CG);
-+		data |= ATC_MISC_CG__ENABLE_MASK;
-+		WREG32(mmATC_MISC_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_WR_CG);
-+		data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_WR_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_RD_CG);
-+		data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_RD_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_VM_CG);
-+		data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_VM_CG, data);
-+
-+		data = RREG32(mmVM_L2_CG);
-+		data |= VM_L2_CG__ENABLE_MASK;
-+		WREG32(mmVM_L2_CG, data);
-+	} else {
-+		data = RREG32(mmMC_HUB_MISC_HUB_CG);
-+		data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_HUB_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_SIP_CG);
-+		data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_SIP_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_VM_CG);
-+		data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_VM_CG, data);
-+
-+		data = RREG32(mmMC_XPB_CLK_GAT);
-+		data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
-+		WREG32(mmMC_XPB_CLK_GAT, data);
-+
-+		data = RREG32(mmATC_MISC_CG);
-+		data &= ~ATC_MISC_CG__ENABLE_MASK;
-+		WREG32(mmATC_MISC_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_WR_CG);
-+		data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_WR_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_RD_CG);
-+		data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_RD_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_VM_CG);
-+		data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_VM_CG, data);
-+
-+		data = RREG32(mmVM_L2_CG);
-+		data &= ~VM_L2_CG__ENABLE_MASK;
-+		WREG32(mmVM_L2_CG, data);
-+	}
-+}
-+
-+static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t data;
-+
-+	if (enable) {
-+		data = RREG32(mmMC_HUB_MISC_HUB_CG);
-+		data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_HUB_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_SIP_CG);
-+		data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_SIP_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_VM_CG);
-+		data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_VM_CG, data);
-+
-+		data = RREG32(mmMC_XPB_CLK_GAT);
-+		data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_XPB_CLK_GAT, data);
-+
-+		data = RREG32(mmATC_MISC_CG);
-+		data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmATC_MISC_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_WR_CG);
-+		data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_WR_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_RD_CG);
-+		data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_RD_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_VM_CG);
-+		data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_VM_CG, data);
-+
-+		data = RREG32(mmVM_L2_CG);
-+		data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmVM_L2_CG, data);
-+	} else {
-+		data = RREG32(mmMC_HUB_MISC_HUB_CG);
-+		data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_HUB_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_SIP_CG);
-+		data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_SIP_CG, data);
-+
-+		data = RREG32(mmMC_HUB_MISC_VM_CG);
-+		data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_HUB_MISC_VM_CG, data);
-+
-+		data = RREG32(mmMC_XPB_CLK_GAT);
-+		data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_XPB_CLK_GAT, data);
-+
-+		data = RREG32(mmATC_MISC_CG);
-+		data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmATC_MISC_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_WR_CG);
-+		data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_WR_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_RD_CG);
-+		data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_RD_CG, data);
-+
-+		data = RREG32(mmMC_CITF_MISC_VM_CG);
-+		data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmMC_CITF_MISC_VM_CG, data);
-+
-+		data = RREG32(mmVM_L2_CG);
-+		data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
-+		WREG32(mmVM_L2_CG, data);
-+	}
-+}
-+
- static int gmc_v8_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_FIJI:
-+		fiji_update_mc_medium_grain_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		fiji_update_mc_light_sleep(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		break;
-+	default:
-+		break;
-+	}
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0093-drm-amdgpu-add-sdma-clock-gating-support-for-Fiji.patch b/common/recipes-kernel/linux/files/0093-drm-amdgpu-add-sdma-clock-gating-support-for-Fiji.patch
deleted file mode 100644
index 28b52b94..00000000
--- a/common/recipes-kernel/linux/files/0093-drm-amdgpu-add-sdma-clock-gating-support-for-Fiji.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From 855ffa6dbabe4cd79a9c5d90a819c0039e948016 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Wed, 11 Nov 2015 11:49:11 -0500
-Subject: [PATCH 0093/1110] drm/amdgpu: add sdma clock gating support for Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 105 +++++++++++++++++++++++++++++++++
- 1 file changed, 105 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index c741c09..ad54c46 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1429,9 +1429,114 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
- 	return 0;
- }
- 
-+static void fiji_update_sdma_medium_grain_clock_gating(
-+		struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	if (enable) {
-+		temp = data = RREG32(mmSDMA0_CLK_CTRL);
-+		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
-+		if (data != temp)
-+			WREG32(mmSDMA0_CLK_CTRL, data);
-+
-+		temp = data = RREG32(mmSDMA1_CLK_CTRL);
-+		data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
-+
-+		if (data != temp)
-+			WREG32(mmSDMA1_CLK_CTRL, data);
-+	} else {
-+		temp = data = RREG32(mmSDMA0_CLK_CTRL);
-+		data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-+				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
-+
-+		if (data != temp)
-+			WREG32(mmSDMA0_CLK_CTRL, data);
-+
-+		temp = data = RREG32(mmSDMA1_CLK_CTRL);
-+		data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-+				SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK;
-+
-+		if (data != temp)
-+			WREG32(mmSDMA1_CLK_CTRL, data);
-+	}
-+}
-+
-+static void fiji_update_sdma_medium_grain_light_sleep(
-+		struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	if (enable) {
-+		temp = data = RREG32(mmSDMA0_POWER_CNTL);
-+		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmSDMA0_POWER_CNTL, data);
-+
-+		temp = data = RREG32(mmSDMA1_POWER_CNTL);
-+		data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmSDMA1_POWER_CNTL, data);
-+	} else {
-+		temp = data = RREG32(mmSDMA0_POWER_CNTL);
-+		data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmSDMA0_POWER_CNTL, data);
-+
-+		temp = data = RREG32(mmSDMA1_POWER_CNTL);
-+		data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmSDMA1_POWER_CNTL, data);
-+	}
-+}
-+
- static int sdma_v3_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_FIJI:
-+		fiji_update_sdma_medium_grain_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		fiji_update_sdma_medium_grain_light_sleep(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		break;
-+	default:
-+		break;
-+	}
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch b/common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch
deleted file mode 100644
index 2f9c4a8e..00000000
--- a/common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 50771694e54dc5c1441506707ea3aedf02979c2d Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 12 Nov 2015 16:59:47 -0500
-Subject: [PATCH 0094/1110] drm/amd/powerplay: add parts of system clock gating
- support for Fiji. (v2)
-
-Removed fiji_mgcg_cgcg_init that is affected and redundant for new implementation.
-
-v2: re-add mgcg_cgcg init
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 86 +++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 86 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 8f2c5c9..89f5a1f 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1544,9 +1544,95 @@ static int vi_common_soft_reset(void *handle)
- 	return 0;
- }
- 
-+static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	temp = data = RREG32_PCIE(ixPCIE_CNTL2);
-+
-+	if (enable)
-+		data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
-+				PCIE_CNTL2__MST_MEM_LS_EN_MASK |
-+				PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
-+	else
-+		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
-+				PCIE_CNTL2__MST_MEM_LS_EN_MASK |
-+				PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
-+
-+	if (temp != data)
-+		WREG32_PCIE(ixPCIE_CNTL2, data);
-+}
-+
-+static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
-+
-+	if (enable)
-+		data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
-+	else
-+		data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
-+
-+	if (temp != data)
-+		WREG32(mmHDP_HOST_PATH_CNTL, data);
-+}
-+
-+static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	temp = data = RREG32(mmHDP_MEM_POWER_LS);
-+
-+	if (enable)
-+		data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
-+	else
-+		data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
-+
-+	if (temp != data)
-+		WREG32(mmHDP_MEM_POWER_LS, data);
-+}
-+
-+static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t temp, data;
-+
-+	temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
-+
-+	if (enable)
-+		data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
-+				CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
-+	else
-+		data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
-+				CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
-+
-+	if (temp != data)
-+		WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
-+}
-+
- static int vi_common_set_clockgating_state(void *handle,
- 					    enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_FIJI:
-+		fiji_update_bif_medium_grain_light_sleep(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		fiji_update_hdp_medium_grain_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		fiji_update_hdp_light_sleep(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		fiji_update_rom_medium_grain_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		break;
-+	default:
-+		break;
-+	}
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0095-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch b/common/recipes-kernel/linux/files/0095-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch
deleted file mode 100644
index f1eadcdd..00000000
--- a/common/recipes-kernel/linux/files/0095-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 306e22971ffd9d11efda77f6a188e205ca0ac8ad Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 12 Nov 2015 17:30:52 -0500
-Subject: [PATCH 0095/1110] drm/amd/powerplay: enable clock gating for Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-index c96b458..45997e6 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-@@ -917,7 +917,14 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
- 	}
- 
- 	/* To initialize all clock gating before RLC loaded and running.*/
--	/*PECI_InitClockGating(peci);*/
-+	cgs_set_clockgating_state(smumgr->device,
-+			AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
-+	cgs_set_clockgating_state(smumgr->device,
-+			AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
-+	cgs_set_clockgating_state(smumgr->device,
-+			AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
-+	cgs_set_clockgating_state(smumgr->device,
-+			AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
- 
- 	/* Setup SoftRegsStart here for register lookup in case
- 	 * DummyBackEnd is used and ProcessFirmwareHeader is not executed
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0096-drm-amd-powerplay-add-atomctrl-function-to-calculate.patch b/common/recipes-kernel/linux/files/0096-drm-amd-powerplay-add-atomctrl-function-to-calculate.patch
deleted file mode 100644
index 3e86599a..00000000
--- a/common/recipes-kernel/linux/files/0096-drm-amd-powerplay-add-atomctrl-function-to-calculate.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 37c74865dbe1f7606bcb7c4152410c814dce89d7 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 13 Nov 2015 22:00:01 -0500
-Subject: [PATCH 0096/1110] drm/amd/powerplay: add atomctrl function to
- calculate CZ sclk dividers
-
-Use atombios to calculate the values.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 22 ++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h |  3 +++
- 2 files changed, 25 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-index 8b47ea0..ea87c90 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-@@ -313,6 +313,28 @@ int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
- 	return result;
- }
- 
-+int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
-+					  uint32_t clock_value,
-+					  pp_atomctrl_clock_dividers_kong *dividers)
-+{
-+	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
-+	int result;
-+
-+	pll_parameters.ulClock = clock_value;
-+
-+	result = cgs_atom_exec_cmd_table
-+		(hwmgr->device,
-+		 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
-+		 &pll_parameters);
-+
-+	if (0 == result) {
-+		dividers->pll_post_divider = pll_parameters.ucPostDiv;
-+		dividers->real_clock = pll_parameters.ulClock;
-+	}
-+
-+	return result;
-+}
-+
- int atomctrl_get_engine_pll_dividers_vi(
- 		struct pp_hwmgr *hwmgr,
- 		uint32_t clock_value,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-index b5ba371..627420b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-@@ -233,6 +233,9 @@ extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uin
- extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
- extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
- 		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
-+extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
-+						 uint32_t clock_value,
-+						 pp_atomctrl_clock_dividers_kong *dividers);
- extern int atomctrl_read_efuse(void *device, uint16_t start_index,
- 		uint16_t end_index, uint32_t mask, uint32_t *efuse);
- extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0097-drm-amd-powerplay-implement-smc-state-upload-for-CZ.patch b/common/recipes-kernel/linux/files/0097-drm-amd-powerplay-implement-smc-state-upload-for-CZ.patch
deleted file mode 100644
index bf18d96c..00000000
--- a/common/recipes-kernel/linux/files/0097-drm-amd-powerplay-implement-smc-state-upload-for-CZ.patch
+++ /dev/null
@@ -1,321 +0,0 @@
-From b5c2312c162dbd04bf84ac286ece6f327a0cfb57 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 13 Nov 2015 23:51:40 -0500
-Subject: [PATCH 0097/1110] drm/amd/powerplay: implement smc state upload for
- CZ
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 135 +++++++++++++++++++--
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h     |   1 +
- .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  22 ++--
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   5 +-
- 4 files changed, 141 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index e187b3f..fc567ca 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -26,6 +26,7 @@
- #include "atom-types.h"
- #include "atombios.h"
- #include "processpptables.h"
-+#include "pp_debug.h"
- #include "cgs_common.h"
- #include "smu/smu_8_0_d.h"
- #include "smu8_fusion.h"
-@@ -70,7 +71,7 @@ uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
- {
- 	int i = 0;
- 	struct phm_vce_clock_voltage_dependency_table *ptable =
--		hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
- 
- 	switch (msg) {
- 	case PPSMC_MSG_SetEclkSoftMin:
-@@ -131,7 +132,7 @@ static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
- {
- 	int i = 0;
- 	struct phm_uvd_clock_voltage_dependency_table *ptable =
--		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
- 
- 	switch (msg) {
- 	case PPSMC_MSG_SetUvdSoftMin:
-@@ -448,9 +449,123 @@ static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
- }
- 
- static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
--					void *output, void *storage, int result)
-+				       void *output, void *storage, int result)
- {
--	return 0;
-+	struct SMU8_Fusion_ClkTable *clock_table;
-+	int ret;
-+	uint32_t i;
-+	void *table = NULL;
-+	pp_atomctrl_clock_dividers_kong dividers;
-+
-+	struct phm_clock_voltage_dependency_table *vddc_table =
-+		hwmgr->dyn_state.vddc_dependency_on_sclk;
-+	struct phm_clock_voltage_dependency_table *vdd_gfx_table =
-+		hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
-+	struct phm_acp_clock_voltage_dependency_table *acp_table =
-+		hwmgr->dyn_state.acp_clock_voltage_dependency_table;
-+	struct phm_uvd_clock_voltage_dependency_table *uvd_table =
-+		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
-+	struct phm_vce_clock_voltage_dependency_table *vce_table =
-+		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
-+
-+	if (!hwmgr->need_pp_table_upload)
-+		return 0;
-+
-+	ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
-+
-+	PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
-+			    "Fail to get clock table from SMU!", return -EINVAL;);
-+
-+	clock_table = (struct SMU8_Fusion_ClkTable *)table;
-+
-+	/* patch clock table */
-+	PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
-+			    "Dependency table entry exceeds max limit!", return -EINVAL;);
-+	PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
-+			    "Dependency table entry exceeds max limit!", return -EINVAL;);
-+	PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
-+			    "Dependency table entry exceeds max limit!", return -EINVAL;);
-+	PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
-+			    "Dependency table entry exceeds max limit!", return -EINVAL;);
-+	PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
-+			    "Dependency table entry exceeds max limit!", return -EINVAL;);
-+
-+	for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
-+
-+		/* vddc_sclk */
-+		clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
-+			(i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
-+		clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
-+			(i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
-+
-+		atomctrl_get_engine_pll_dividers_kong(hwmgr,
-+						      clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
-+						      &dividers);
-+
-+		clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
-+			(uint8_t)dividers.pll_post_divider;
-+
-+		/* vddgfx_sclk */
-+		clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
-+			(i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
-+
-+		/* acp breakdown */
-+		clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
-+			(i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
-+		clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
-+			(i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
-+
-+		atomctrl_get_engine_pll_dividers_kong(hwmgr,
-+						      clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
-+						      &dividers);
-+
-+		clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
-+			(uint8_t)dividers.pll_post_divider;
-+
-+
-+		/* uvd breakdown */
-+		clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
-+			(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
-+		clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
-+			(i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
-+
-+		atomctrl_get_engine_pll_dividers_kong(hwmgr,
-+						      clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
-+						      &dividers);
-+
-+		clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
-+			(uint8_t)dividers.pll_post_divider;
-+
-+		clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
-+			(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
-+		clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
-+			(i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
-+
-+		atomctrl_get_engine_pll_dividers_kong(hwmgr,
-+						      clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
-+						      &dividers);
-+
-+		clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
-+			(uint8_t)dividers.pll_post_divider;
-+
-+		/* vce breakdown */
-+		clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
-+			(i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
-+		clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
-+			(i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
-+
-+
-+		atomctrl_get_engine_pll_dividers_kong(hwmgr,
-+						      clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
-+						      &dividers);
-+
-+		clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
-+			(uint8_t)dividers.pll_post_divider;
-+
-+	}
-+	ret = smum_upload_powerplay_table(hwmgr->smumgr);
-+
-+	return ret;
- }
- 
- static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
-@@ -485,7 +600,7 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_uvd_clock_voltage_dependency_table *table =
--				hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+				hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
- 	unsigned long clock = 0, level;
- 
- 	if (NULL == table && table->count <= 0)
-@@ -513,7 +628,7 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_vce_clock_voltage_dependency_table *table =
--				hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+				hwmgr->dyn_state.vce_clock_voltage_dependency_table;
- 	unsigned long clock = 0, level;
- 
- 	if (NULL == table && table->count <= 0)
-@@ -1144,7 +1259,7 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_uvd_clock_voltage_dependency_table *ptable =
--		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
- 
- 	if (!bgate) {
- 		/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
-@@ -1172,7 +1287,7 @@ int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_vce_clock_voltage_dependency_table *ptable =
--		hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
- 
- 	/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-@@ -1331,10 +1446,10 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 				hwmgr->dyn_state.vddc_dependency_on_sclk;
- 
- 	struct phm_vce_clock_voltage_dependency_table *vce_table =
--		hwmgr->dyn_state.vce_clocl_voltage_dependency_table;
-+		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
- 
- 	struct phm_uvd_clock_voltage_dependency_table *uvd_table =
--		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table;
-+		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
- 
- 	uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
- 					TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-index 70b0e51..1765d0e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-@@ -25,6 +25,7 @@
- #define _CZ_HWMGR_H_
- 
- #include "cgs_common.h"
-+#include "ppatomctrl.h"
- 
- #define CZ_NUM_NBPSTATES               4
- #define CZ_NUM_NBPMEMORYCLOCK          2
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-index dc1d3d2..fdda6b4 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-@@ -1163,8 +1163,8 @@ static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
- 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
- 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
--	hwmgr->dyn_state.vce_clocl_voltage_dependency_table = NULL;
--	hwmgr->dyn_state.uvd_clocl_voltage_dependency_table = NULL;
-+	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
-+	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
- 	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
- 	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
- 	hwmgr->dyn_state.ppm_parameter_table = NULL;
-@@ -1182,7 +1182,7 @@ static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
- 				(const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
- 				(((unsigned long) powerplay_table) + table_offset);
- 		result = get_vce_clock_voltage_limit_table(hwmgr,
--				&hwmgr->dyn_state.vce_clocl_voltage_dependency_table,
-+				&hwmgr->dyn_state.vce_clock_voltage_dependency_table,
- 				table, array);
- 	}
- 
-@@ -1197,7 +1197,7 @@ static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
- 				(const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
- 				(((unsigned long) powerplay_table) + table_offset);
- 		result = get_uvd_clock_voltage_limit_table(hwmgr,
--				&hwmgr->dyn_state.uvd_clocl_voltage_dependency_table, ptable, array);
-+				&hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array);
- 	}
- 
- 	table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,
-@@ -1533,6 +1533,8 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
- 	int result;
- 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table;
- 
-+	hwmgr->need_pp_table_upload = true;
-+
- 	powerplay_table = get_powerplay_table(hwmgr);
- 
- 	result = init_powerplay_tables(hwmgr, powerplay_table);
-@@ -1607,14 +1609,14 @@ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
- 		hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
- 	}
- 
--	if (NULL != hwmgr->dyn_state.vce_clocl_voltage_dependency_table) {
--		kfree(hwmgr->dyn_state.vce_clocl_voltage_dependency_table);
--		hwmgr->dyn_state.vce_clocl_voltage_dependency_table = NULL;
-+	if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) {
-+		kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
-+		hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
- 	}
- 
--	if (NULL != hwmgr->dyn_state.uvd_clocl_voltage_dependency_table) {
--		kfree(hwmgr->dyn_state.uvd_clocl_voltage_dependency_table);
--		hwmgr->dyn_state.uvd_clocl_voltage_dependency_table = NULL;
-+	if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) {
-+		kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
-+		hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
- 	}
- 
- 	if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) {
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 5b5c94d..e115a07 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -463,9 +463,9 @@ struct phm_dynamic_state_info {
- 	struct phm_phase_shedding_limits_table	  *vddc_phase_shed_limits_table;
- 
- 	struct phm_vce_clock_voltage_dependency_table
--					    *vce_clocl_voltage_dependency_table;
-+					    *vce_clock_voltage_dependency_table;
- 	struct phm_uvd_clock_voltage_dependency_table
--					    *uvd_clocl_voltage_dependency_table;
-+					    *uvd_clock_voltage_dependency_table;
- 	struct phm_acp_clock_voltage_dependency_table
- 					    *acp_clock_voltage_dependency_table;
- 	struct phm_samu_clock_voltage_dependency_table
-@@ -551,6 +551,7 @@ struct pp_hwmgr {
- 	void *device;
- 	struct pp_smumgr *smumgr;
- 	const void *soft_pp_table;
-+	bool need_pp_table_upload;
- 	enum amd_dpm_forced_level dpm_level;
- 	bool block_hw_access;
- 	struct phm_gfx_arbiter gfx_arbiter;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0098-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch b/common/recipes-kernel/linux/files/0098-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch
deleted file mode 100644
index 289c0f40..00000000
--- a/common/recipes-kernel/linux/files/0098-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From a9867e8f3ef0737dc691370ef31adf2041848ddc Mon Sep 17 00:00:00 2001
-From: rezhu <Rex.Zhu@amd.com>
-Date: Thu, 12 Nov 2015 16:40:50 +0800
-Subject: [PATCH 0098/1110] drm/amd/powerplay: fix warning of cast to pointer
- from integer of different size.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c | 4 ++--
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.c        | 6 +++---
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c         | 2 +-
- 3 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index fdd67c6..618aadf 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -402,7 +402,7 @@ restart_search:
- 			event_data->pnew_power_state = state;
- 			return 0;
- 		}
--		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- 	}
- 
- 	switch (event_data->requested_ui_label) {
-@@ -428,4 +428,4 @@ int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct
- int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
- 	return phm_stop_thermal_controller(eventmgr->hwmgr);
--}
-\ No newline at end of file
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-index 82774ac..5740fbf 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-@@ -37,7 +37,7 @@ int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label
- 			*state_id = state->id;
- 			return 0;
- 		}
--		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- 	}
- 	return -1;
- }
-@@ -57,7 +57,7 @@ int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateC
- 			*state_id = state->id;
- 			return 0;
- 		}
--		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- 	}
- 	return -1;
- }
-@@ -77,7 +77,7 @@ int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *stat
- 			hwmgr->request_ps = state;
- 			return 0;
- 		}
--		state = (struct pp_power_state *)((uint64_t)state + hwmgr->ps_size);
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
- 	}
- 	return -1;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index f243e40..618cc4d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -121,7 +121,7 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
- 
- 		if (state->classification.flags & PP_StateClassificationFlag_Uvd)
- 			hwmgr->uvd_ps = state;
--		state = (struct pp_power_state *)((uint64_t)state + size);
-+		state = (struct pp_power_state *)((unsigned long)state + size);
- 	}
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0099-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch b/common/recipes-kernel/linux/files/0099-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch
deleted file mode 100644
index 7e54b411..00000000
--- a/common/recipes-kernel/linux/files/0099-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 1fbd822e6fde44d660d372680657763a5e5b5c25 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 16 Nov 2015 11:24:35 +0800
-Subject: [PATCH 0099/1110] drm/amd/powerplay: fix warning of cast to pointer
- from integer of different size.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 2348d8c..fd32be2 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4956,12 +4956,12 @@ static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
- 
- 	ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
- 			(ATOM_Tonga_SCLK_Dependency_Table *)
--			(((uint64_t)powerplay_table) +
-+			(((unsigned long)powerplay_table) +
- 			le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
- 
- 	ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
- 			(ATOM_Tonga_MCLK_Dependency_Table *)
--			(((uint64_t)powerplay_table) +
-+			(((unsigned long)powerplay_table) +
- 			le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
- 
- 	/* The following fields are not initialized here: id orderedList allStatesList */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0100-amdgpu-powerplay-Add-Stoney-to-list-of-early-init-ca.patch b/common/recipes-kernel/linux/files/0100-amdgpu-powerplay-Add-Stoney-to-list-of-early-init-ca.patch
deleted file mode 100644
index 057506bc..00000000
--- a/common/recipes-kernel/linux/files/0100-amdgpu-powerplay-Add-Stoney-to-list-of-early-init-ca.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 3c1cf495010da12291784e610fd93775052f1ecb Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Fri, 20 Nov 2015 13:33:44 -0500
-Subject: [PATCH 0100/1110] amdgpu/powerplay: Add Stoney to list of early init
- cases
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 6b46fbf..4f6740c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -81,6 +81,7 @@ static int amdgpu_powerplay_init(struct amdgpu_device *adev)
- 			amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
- 			break;
- 		case CHIP_CARRIZO:
-+		case CHIP_STONEY:
- 			amd_pp->ip_funcs = &cz_dpm_ip_funcs;
- 			break;
- 		default:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0101-drm-amd-powerplay-add-new-function-point-in-hwmgr.patch b/common/recipes-kernel/linux/files/0101-drm-amd-powerplay-add-new-function-point-in-hwmgr.patch
deleted file mode 100644
index f7d22adf..00000000
--- a/common/recipes-kernel/linux/files/0101-drm-amd-powerplay-add-new-function-point-in-hwmgr.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 7fb3678df3f66577d48daa317bfab55c696a69a4 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 19 Nov 2015 13:46:01 +0800
-Subject: [PATCH 0101/1110] drm/amd/powerplay: add new function point in hwmgr.
-
-1. for set_cpu_power_state
-2. restore display configuration
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index e115a07..238d162 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -312,6 +312,10 @@ struct pp_hwmgr_func {
- 					const struct pp_hw_power_state *pstate1,
- 					const struct pp_hw_power_state *pstate2,
- 					bool *equal);
-+	int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
-+	int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
-+				bool cc6_disable, bool pstate_disable,
-+				bool pstate_switch_disable);
- };
- 
- struct pp_table_func {
-@@ -575,7 +579,7 @@ struct pp_hwmgr {
- 	const struct pp_hwmgr_func *hwmgr_func;
- 	const struct pp_table_func *pptable_func;
- 	struct pp_power_state    *ps;
--        enum pp_power_source  power_source;
-+	enum pp_power_source  power_source;
- 	uint32_t num_ps;
- 	struct pp_thermal_controller_info thermal_controller;
- 	bool fan_ctrl_is_in_default_mode;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0102-drm-amd-powerplay-add-smc-msg-for-NB-P-State-switch.patch b/common/recipes-kernel/linux/files/0102-drm-amd-powerplay-add-smc-msg-for-NB-P-State-switch.patch
deleted file mode 100644
index 4dcafcdc..00000000
--- a/common/recipes-kernel/linux/files/0102-drm-amd-powerplay-add-smc-msg-for-NB-P-State-switch.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From a5026378fefdc88b1a06c4cc5b1eb50dd44c8fe9 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 19 Nov 2015 13:47:36 +0800
-Subject: [PATCH 0102/1110] drm/amd/powerplay: add smc msg for NB P-State
- switch
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h    | 1 +
- drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h | 8 ++++++++
- 2 files changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h
-index 273616a..9b69878 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h
-@@ -164,6 +164,7 @@ enum DPM_ARRAY {
- #define PPSMC_MSG_SetLoggerAddressHigh        ((uint16_t) 0x26C)
- #define PPSMC_MSG_SetLoggerAddressLow         ((uint16_t) 0x26D)
- #define PPSMC_MSG_SetWatermarkFrequency       ((uint16_t) 0x26E)
-+#define PPSMC_MSG_SetDisplaySizePowerParams   ((uint16_t) 0x26F)
- 
- /* REMOVE LATER*/
- #define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h
-index 5c9cc3c..0c37c94 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h
-@@ -48,6 +48,14 @@ struct SMU8_Port80MonitorTable {
- 	uint8_t  EnableDramShadow;
- };
- 
-+/*  Display specific power management parameters */
-+#define PWRMGT_SEPARATION_TIME_SHIFT            0
-+#define PWRMGT_SEPARATION_TIME_MASK             0xFFFF
-+#define PWRMGT_DISABLE_CPU_CSTATES_SHIFT        16
-+#define PWRMGT_DISABLE_CPU_CSTATES_MASK         0x1
-+#define PWRMGT_DISABLE_CPU_PSTATES_SHIFT        24
-+#define PWRMGT_DISABLE_CPU_PSTATES_MASK         0x1
-+
- /* Clock Table Definitions */
- #define NUM_SCLK_LEVELS     8
- #define NUM_LCLK_LEVELS     8
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0103-drm-amd-powerplay-export-interface-to-DAL-to-init-ch.patch b/common/recipes-kernel/linux/files/0103-drm-amd-powerplay-export-interface-to-DAL-to-init-ch.patch
deleted file mode 100644
index 4e430c18..00000000
--- a/common/recipes-kernel/linux/files/0103-drm-amd-powerplay-export-interface-to-DAL-to-init-ch.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From 3e6b314855a8e00aafadac9d3ff828e5de0fe713 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 19 Nov 2015 13:35:30 +0800
-Subject: [PATCH 0103/1110] drm/amd/powerplay: export interface to DAL to
- init/change display configuration.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h                   |  1 +
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c         | 16 ++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 16 ++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h     |  9 +++++++++
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   |  3 +++
- 5 files changed, 45 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 4a4ddb6..4084669 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1647,6 +1647,7 @@ struct amdgpu_pm {
- 	const struct amdgpu_dpm_funcs *funcs;
- 	uint32_t                pcie_gen_mask;
- 	uint32_t                pcie_mlw_mask;
-+	struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
- };
- 
- void amdgpu_get_pcie_info(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 10385c0..215757e 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -603,3 +603,19 @@ int amd_powerplay_fini(void *handle)
- 
- 	return 0;
- }
-+
-+/* export this function to DAL */
-+
-+int amd_powerplay_display_configuration_change(void *handle, const void *input)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+	const struct amd_pp_display_configuration *display_config = input;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	phm_store_dal_configuration_data(hwmgr, display_config);
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index f2d603c..d6d2849 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -26,6 +26,7 @@
- #include "power_state.h"
- #include "pp_acpi.h"
- #include "amd_acpi.h"
-+#include "amd_powerplay.h"
- 
- void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
- {
-@@ -244,3 +245,18 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- 
- 	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
- }
-+
-+int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
-+		    const struct amd_pp_display_configuration *display_config)
-+{
-+	if (hwmgr == NULL || hwmgr->hwmgr_func->store_cc6_data == NULL)
-+		return -EINVAL;
-+
-+	/* to do pass other display configuration in furture */
-+	return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
-+					display_config->cpu_pstate_separation_time,
-+					display_config->cpu_cc6_disable,
-+					display_config->cpu_pstate_disable,
-+					display_config->nb_pstate_switch_disable);
-+
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 40ded67..efa23c1 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -131,6 +131,13 @@ struct amd_pp_init {
- 	uint32_t rev_id;
- };
- 
-+struct amd_pp_display_configuration {
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+};
-+
- enum {
- 	PP_GROUP_UNKNOWN = 0,
- 	PP_GROUP_GFX = 1,
-@@ -203,4 +210,6 @@ int amd_powerplay_init(struct amd_pp_init *pp_init,
- 		       struct amd_powerplay *amd_pp);
- int amd_powerplay_fini(void *handle);
- 
-+int amd_powerplay_display_configuration_change(void *handle, const void *input);
-+
- #endif /* _AMD_POWERPLAY_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index a3f7bd2..7b721e8 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -353,5 +353,8 @@ extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- 				 const struct pp_hw_power_state *pstate2,
- 				 bool *equal);
- 
-+extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
-+		    const struct amd_pp_display_configuration *display_config);
-+
- #endif /* _HARDWARE_MANAGER_H_ */
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0104-drm-amd-powerplay-enable-set_cpu_power_state-task.-v.patch b/common/recipes-kernel/linux/files/0104-drm-amd-powerplay-enable-set_cpu_power_state-task.-v.patch
deleted file mode 100644
index 9177bbfe..00000000
--- a/common/recipes-kernel/linux/files/0104-drm-amd-powerplay-enable-set_cpu_power_state-task.-v.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From bfab153233ce2f5069eee8c776387411ac8a50df Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 19 Nov 2015 13:47:02 +0800
-Subject: [PATCH 0104/1110] drm/amd/powerplay: enable set_cpu_power_state task.
- (v2)
-
-v2: integrate Jammy's crash fix
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c |  2 +-
- drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c    |  5 +++++
- drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h    |  1 +
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c        |  3 +--
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c      | 13 +++++++++++--
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h        |  2 ++
- 6 files changed, 21 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-index bbbb76c..9458394 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -260,7 +260,7 @@ const struct action_chain disable_user_2d_performance_action_chain = {
- static const pem_event_action *display_config_change_event[] = {
- 	/* countDisplayConfigurationChangeEventTasks, */
- 	unblock_adjust_power_state_tasks,
--	/* setCPUPowerState,*/
-+	set_cpu_power_state,
- 	notify_hw_power_source_tasks,
- 	/* updateDALConfigurationTasks,
- 	variBrightDisplayConfigurationChangeTasks, */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-index 3dd671e..9ef2d90 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.c
-@@ -403,3 +403,8 @@ const pem_event_action uninitialize_thermal_controller_tasks[] = {
- 	pem_task_uninitialize_thermal_controller,
- 	NULL
- };
-+
-+const pem_event_action set_cpu_power_state[] = {
-+	pem_task_set_cpu_power_state,
-+	NULL
-+};
-\ No newline at end of file
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-index 741ebfc..7714cb9 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventsubchains.h
-@@ -96,4 +96,5 @@ extern const pem_event_action reset_boot_state_tasks[];
- extern const pem_event_action create_new_user_performance_state_tasks[];
- extern const pem_event_action initialize_thermal_controller_tasks[];
- extern const pem_event_action uninitialize_thermal_controller_tasks[];
-+extern const pem_event_action set_cpu_power_state[];
- #endif /* _EVENT_SUB_CHAINS_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index 618aadf..0a03f79 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -248,8 +248,7 @@ int pem_task_reset_display_phys_access(struct pp_eventmgr *eventmgr, struct pem_
- 
- int pem_task_set_cpu_power_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
--	/* TODO */
--	return 0;
-+	return phm_set_cpu_power_state(eventmgr->hwmgr);
- }
- 
- /*powersaving*/
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index d6d2849..31b0dc3 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -180,7 +180,7 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
- 			hwmgr->hwmgr_func->display_config_changed(hwmgr);
- 	} else
- 		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
--    return 0;
-+	return 0;
- }
- 
- int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
-@@ -193,7 +193,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
- 		if (NULL != hwmgr->hwmgr_func->display_config_changed)
- 			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
- 
--    return 0;
-+	return 0;
- }
- 
- int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
-@@ -260,3 +260,12 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 					display_config->nb_pstate_switch_disable);
- 
- }
-+
-+int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)
-+		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
-+
-+	return 0;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 7b721e8..820622d 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -356,5 +356,7 @@ extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 		    const struct amd_pp_display_configuration *display_config);
- 
-+extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
-+
- #endif /* _HARDWARE_MANAGER_H_ */
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0105-drm-amd-powerplay-enable-disable-NB-pstate-feature-f.patch b/common/recipes-kernel/linux/files/0105-drm-amd-powerplay-enable-disable-NB-pstate-feature-f.patch
deleted file mode 100644
index bdcf6277..00000000
--- a/common/recipes-kernel/linux/files/0105-drm-amd-powerplay-enable-disable-NB-pstate-feature-f.patch
+++ /dev/null
@@ -1,195 +0,0 @@
-From 4f41c6d334546d413367d63b90412fc83521e6d6 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 19 Nov 2015 13:48:14 +0800
-Subject: [PATCH 0105/1110] drm/amd/powerplay: enable/disable NB pstate feature
- for Carrizo.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 99 ++++++++++++++++++++++----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h |  3 +-
- 2 files changed, 87 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index fc567ca..c7116ae 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -239,7 +239,10 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_DynamicUVDState);
- 
--	cz_hwmgr->is_nb_dpm_enabled_by_driver = 1;
-+	cz_hwmgr->display_cfg.cpu_cc6_disable = false;
-+	cz_hwmgr->display_cfg.cpu_pstate_disable = false;
-+	cz_hwmgr->display_cfg.nb_pstate_switch_disable = false;
-+	cz_hwmgr->display_cfg.cpu_pstate_separation_time = 0;
- 
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 				   PHM_PlatformCaps_DisableVoltageIsland);
-@@ -812,17 +815,16 @@ static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
-+
- static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
- 					void *input, void *output,
- 					void *storage, int result)
- {
- 	int ret = 0;
--	struct cz_hwmgr *cz_hwmgr =
--				  (struct cz_hwmgr *)(hwmgr->backend);
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	unsigned long dpm_features = 0;
- 
--	if (!cz_hwmgr->is_nb_dpm_enabled &&
--		cz_hwmgr->is_nb_dpm_enabled_by_driver) {		/* also depend on dal NBPStateDisableRequired */
-+	if (!cz_hwmgr->is_nb_dpm_enabled) {
- 		dpm_features |= NB_DPM_MASK;
- 		ret = smum_send_msg_to_smc_with_parameter(
- 							     hwmgr->smumgr,
-@@ -831,26 +833,48 @@ static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
- 		if (ret == 0)
- 			cz_hwmgr->is_nb_dpm_enabled = true;
- 	}
-+
- 	return ret;
- }
- 
-+static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
-+{
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (hw_data->is_nb_dpm_enabled) {
-+		if (enable)
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_EnableLowMemoryPstate,
-+						(lock ? 1 : 0));
-+		else
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_DisableLowMemoryPstate,
-+						(lock ? 1 : 0));
-+	}
-+
-+	return 0;
-+}
-+
- static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
- 					void *input, void *output,
- 					void *storage, int result)
- {
--
--	struct cz_hwmgr *cz_hwmgr =
--				  (struct cz_hwmgr *)(hwmgr->backend);
-+	bool disable_switch;
-+	bool enable_low_mem_state;
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 	const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
- 	const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
- 
--	if (cz_hwmgr->sys_info.nb_dpm_enable) {
-+	if (hw_data->sys_info.nb_dpm_enable) {
-+		disable_switch = hw_data->display_cfg.nb_pstate_switch_disable ? true : false;
-+		enable_low_mem_state = hw_data->display_cfg.nb_pstate_switch_disable ? false : true;
-+
- 		if (pnew_state->action == FORCE_HIGH)
--			smum_send_msg_to_smc(hwmgr->smumgr,
--				    PPSMC_MSG_DisableLowMemoryPstate);
--		else
--			smum_send_msg_to_smc(hwmgr->smumgr,
--				     PPSMC_MSG_EnableLowMemoryPstate);
-+			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
-+		else if(pnew_state->action == CANCEL_FORCE_HIGH)
-+			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
-+		else 
-+			cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
- 	}
- 	return 0;
- }
-@@ -1498,6 +1522,51 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 	}
- }
- 
-+int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+	uint32_t data = 0;
-+	if (hw_data->cc6_setting_changed == true) {
-+		data |= (hw_data->display_cfg.cpu_pstate_separation_time
-+			& PWRMGT_SEPARATION_TIME_MASK)
-+			<< PWRMGT_SEPARATION_TIME_SHIFT;
-+
-+		data|= (hw_data->display_cfg.cpu_cc6_disable ? 0x1 : 0x0)
-+			<< PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
-+
-+		data|= (hw_data->display_cfg.cpu_pstate_disable ? 0x1 : 0x0)
-+			<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
-+
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SetDisplaySizePowerParams,
-+						data);
-+
-+		hw_data->cc6_setting_changed = false;
-+	}
-+
-+	return 0;
-+}
-+
-+int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
-+			bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
-+{
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (separation_time != hw_data->display_cfg.cpu_pstate_separation_time
-+	|| cc6_disable != hw_data->display_cfg.cpu_cc6_disable
-+	|| pstate_disable != hw_data->display_cfg.cpu_pstate_disable
-+	|| pstate_switch_disable != hw_data->display_cfg.nb_pstate_switch_disable) {
-+
-+		hw_data->display_cfg.cpu_pstate_separation_time = separation_time;
-+		hw_data->display_cfg.cpu_cc6_disable = cc6_disable;
-+		hw_data->display_cfg.cpu_pstate_disable = pstate_disable;
-+		hw_data->display_cfg.nb_pstate_switch_disable = pstate_switch_disable;
-+		hw_data->cc6_setting_changed = true;
-+
-+	}
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.backend_init = cz_hwmgr_backend_init,
- 	.backend_fini = cz_hwmgr_backend_fini,
-@@ -1514,6 +1583,8 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.get_pp_table_entry = cz_dpm_get_pp_table_entry,
- 	.get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
- 	.print_current_perforce_level = cz_print_current_perforce_level,
-+	.set_cpu_power_state = cz_set_cpu_power_state,
-+	.store_cc6_data = cz_store_cc6_data,
- };
- 
- int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-index 1765d0e..54a6c34 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-@@ -238,7 +238,7 @@ struct cz_hwmgr {
- 	uint32_t highest_valid;
- 	uint32_t high_voltage_threshold;
- 	uint32_t is_nb_dpm_enabled;
--	uint32_t is_nb_dpm_enabled_by_driver;
-+	struct amd_pp_display_configuration display_cfg; /* set by DAL */
- 	uint32_t is_voltage_island_enabled;
- 
- 	bool pgacpinit;
-@@ -304,6 +304,7 @@ struct cz_hwmgr {
- 
- 	uint32_t max_sclk_level;
- 	uint32_t num_of_clk_entries;
-+	bool cc6_setting_changed;
- };
- 
- struct pp_hwmgr;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0106-drm-amd-powerplay-Add-PPLib-debug-print-macro.patch b/common/recipes-kernel/linux/files/0106-drm-amd-powerplay-Add-PPLib-debug-print-macro.patch
deleted file mode 100644
index ca2e0519..00000000
--- a/common/recipes-kernel/linux/files/0106-drm-amd-powerplay-Add-PPLib-debug-print-macro.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From e05e02d7509d4079d4d6f2f721bd7c165332940d Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 19 Nov 2015 14:45:39 -0500
-Subject: [PATCH 0106/1110] drm/amd/powerplay: Add PPLib debug print macro.
-
-- The macro is silent by default.
-- Use the macro to print Display Configuration - related changes.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 35 +++++++++++++++++++++++---
- drivers/gpu/drm/amd/powerplay/inc/pp_debug.h   |  9 ++++++-
- 2 files changed, 40 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index c7116ae..13b5bef 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -38,7 +38,7 @@
- #include "cz_hwmgr.h"
- #include "power_state.h"
- #include "cz_clockpowergating.h"
--
-+#include "pp_debug.h"
- 
- #define ixSMUSVI_NB_CURRENTVID 0xD8230044
- #define CURRENT_NB_VID_MASK 0xff000000
-@@ -821,10 +821,12 @@ static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
- 					void *storage, int result)
- {
- 	int ret = 0;
-+
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	unsigned long dpm_features = 0;
- 
- 	if (!cz_hwmgr->is_nb_dpm_enabled) {
-+		PP_DBG_LOG("enabling ALL SMU features.\n");
- 		dpm_features |= NB_DPM_MASK;
- 		ret = smum_send_msg_to_smc_with_parameter(
- 							     hwmgr->smumgr,
-@@ -842,14 +844,19 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	if (hw_data->is_nb_dpm_enabled) {
--		if (enable)
-+		if (enable) {
-+			PP_DBG_LOG("enable Low Memory PState.\n");
-+
- 			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 						PPSMC_MSG_EnableLowMemoryPstate,
- 						(lock ? 1 : 0));
--		else
-+		} else {
-+			PP_DBG_LOG("disable Low Memory PState.\n");
-+
- 			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 						PPSMC_MSG_DisableLowMemoryPstate,
- 						(lock ? 1 : 0));
-+		}
- 	}
- 
- 	return 0;
-@@ -1522,11 +1529,30 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 	}
- }
- 
-+static void cz_hw_print_display_cfg(
-+	const struct amd_pp_display_configuration *display_cfg)
-+{
-+	PP_DBG_LOG("New Display Configuration:\n");
-+
-+	PP_DBG_LOG("   cpu_cc6_disable: %d\n",
-+			display_cfg->cpu_cc6_disable);
-+	PP_DBG_LOG("   cpu_pstate_disable: %d\n",
-+			display_cfg->cpu_pstate_disable);
-+	PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
-+			display_cfg->nb_pstate_switch_disable);
-+	PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
-+			display_cfg->cpu_pstate_separation_time);
-+}
-+
- int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 	uint32_t data = 0;
-+
- 	if (hw_data->cc6_setting_changed == true) {
-+
-+		cz_hw_print_display_cfg(&hw_data->display_cfg);
-+
- 		data |= (hw_data->display_cfg.cpu_pstate_separation_time
- 			& PWRMGT_SEPARATION_TIME_MASK)
- 			<< PWRMGT_SEPARATION_TIME_SHIFT;
-@@ -1537,6 +1563,9 @@ int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- 		data|= (hw_data->display_cfg.cpu_pstate_disable ? 0x1 : 0x0)
- 			<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
- 
-+		PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
-+			data);
-+
- 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 						PPSMC_MSG_SetDisplaySizePowerParams,
- 						data);
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-index 3df3ded..d7d83b7 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
-@@ -36,5 +36,12 @@
- 		}				\
- 	} while (0)
- 
--#endif
-+
-+#define PP_DBG_LOG(fmt, ...) \
-+	do { \
-+		if(0)printk(KERN_INFO "[ pp_dbg ] " fmt, ##__VA_ARGS__); \
-+	} while (0)
-+
-+
-+#endif /* PP_DEBUG_H */
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0107-drm-amdgpu-rename-tonga_smumgr.h-to-tonga_smum.h.patch b/common/recipes-kernel/linux/files/0107-drm-amdgpu-rename-tonga_smumgr.h-to-tonga_smum.h.patch
deleted file mode 100644
index 20b54988..00000000
--- a/common/recipes-kernel/linux/files/0107-drm-amdgpu-rename-tonga_smumgr.h-to-tonga_smum.h.patch
+++ /dev/null
@@ -1,145 +0,0 @@
-From cd97ada156b65615125f8b8ba3cb0b7e46036a3b Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Wed, 21 Oct 2015 17:15:45 +0800
-Subject: [PATCH 0107/1110] drm/amdgpu: rename tonga_smumgr.h to tonga_smum.h
-
-This conflicts with the tonga_smumgr.h from powerplay
-in DKMS environement
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/tonga_dpm.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/tonga_smc.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/tonga_smum.h   | 42 +++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h | 42 -------------------------------
- 4 files changed, 44 insertions(+), 44 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_smum.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-index 63d6cb3..0497784 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-@@ -24,7 +24,7 @@
- #include <linux/firmware.h>
- #include "drmP.h"
- #include "amdgpu.h"
--#include "tonga_smumgr.h"
-+#include "tonga_smum.h"
- 
- MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smc.c b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
-index 5421309..361c49a 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
-@@ -25,7 +25,7 @@
- #include "drmP.h"
- #include "amdgpu.h"
- #include "tonga_ppsmc.h"
--#include "tonga_smumgr.h"
-+#include "tonga_smum.h"
- #include "smu_ucode_xfer_vi.h"
- #include "amdgpu_ucode.h"
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smum.h b/drivers/gpu/drm/amd/amdgpu/tonga_smum.h
-new file mode 100644
-index 0000000..c031ff9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_smum.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef TONGA_SMUMGR_H
-+#define TONGA_SMUMGR_H
-+
-+#include "tonga_ppsmc.h"
-+
-+int tonga_smu_init(struct amdgpu_device *adev);
-+int tonga_smu_fini(struct amdgpu_device *adev);
-+int tonga_smu_start(struct amdgpu_device *adev);
-+
-+struct tonga_smu_private_data
-+{
-+	uint8_t *header;
-+	uint32_t smu_buffer_addr_high;
-+	uint32_t smu_buffer_addr_low;
-+	uint32_t header_addr_high;
-+	uint32_t header_addr_low;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h b/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h
-deleted file mode 100644
-index c031ff9..0000000
---- a/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h
-+++ /dev/null
-@@ -1,42 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef TONGA_SMUMGR_H
--#define TONGA_SMUMGR_H
--
--#include "tonga_ppsmc.h"
--
--int tonga_smu_init(struct amdgpu_device *adev);
--int tonga_smu_fini(struct amdgpu_device *adev);
--int tonga_smu_start(struct amdgpu_device *adev);
--
--struct tonga_smu_private_data
--{
--	uint8_t *header;
--	uint32_t smu_buffer_addr_high;
--	uint32_t smu_buffer_addr_low;
--	uint32_t header_addr_high;
--	uint32_t header_addr_low;
--};
--
--#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0108-drm-amdgpu-rename-fiji_smumgr.h-to-fiji_smum.h.patch b/common/recipes-kernel/linux/files/0108-drm-amdgpu-rename-fiji_smumgr.h-to-fiji_smum.h.patch
deleted file mode 100644
index b302713e..00000000
--- a/common/recipes-kernel/linux/files/0108-drm-amdgpu-rename-fiji_smumgr.h-to-fiji_smum.h.patch
+++ /dev/null
@@ -1,145 +0,0 @@
-From 83ba8f33769d81ed8790936bd8fb55b23742eb92 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Wed, 21 Oct 2015 17:18:10 +0800
-Subject: [PATCH 0108/1110] drm/amdgpu: rename fiji_smumgr.h to fiji_smum.h
-
-This conflicts with fiji_smumgr.h from powerplay
-in DKMS environment
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/fiji_dpm.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/fiji_smc.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/fiji_smum.h   | 42 ++++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/fiji_smumgr.h | 42 --------------------------------
- 4 files changed, 44 insertions(+), 44 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/amdgpu/fiji_smum.h
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/fiji_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-index 8f9845d..4b0e45a 100644
---- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-@@ -24,7 +24,7 @@
- #include <linux/firmware.h>
- #include "drmP.h"
- #include "amdgpu.h"
--#include "fiji_smumgr.h"
-+#include "fiji_smum.h"
- 
- MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_smc.c b/drivers/gpu/drm/amd/amdgpu/fiji_smc.c
-index bda1249..e35340a 100644
---- a/drivers/gpu/drm/amd/amdgpu/fiji_smc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/fiji_smc.c
-@@ -25,7 +25,7 @@
- #include "drmP.h"
- #include "amdgpu.h"
- #include "fiji_ppsmc.h"
--#include "fiji_smumgr.h"
-+#include "fiji_smum.h"
- #include "smu_ucode_xfer_vi.h"
- #include "amdgpu_ucode.h"
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_smum.h b/drivers/gpu/drm/amd/amdgpu/fiji_smum.h
-new file mode 100644
-index 0000000..1cef03d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/fiji_smum.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef FIJI_SMUMGR_H
-+#define FIJI_SMUMGR_H
-+
-+#include "fiji_ppsmc.h"
-+
-+int fiji_smu_init(struct amdgpu_device *adev);
-+int fiji_smu_fini(struct amdgpu_device *adev);
-+int fiji_smu_start(struct amdgpu_device *adev);
-+
-+struct fiji_smu_private_data
-+{
-+	uint8_t *header;
-+	uint32_t smu_buffer_addr_high;
-+	uint32_t smu_buffer_addr_low;
-+	uint32_t header_addr_high;
-+	uint32_t header_addr_low;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_smumgr.h b/drivers/gpu/drm/amd/amdgpu/fiji_smumgr.h
-deleted file mode 100644
-index 1cef03d..0000000
---- a/drivers/gpu/drm/amd/amdgpu/fiji_smumgr.h
-+++ /dev/null
-@@ -1,42 +0,0 @@
--/*
-- * Copyright 2014 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef FIJI_SMUMGR_H
--#define FIJI_SMUMGR_H
--
--#include "fiji_ppsmc.h"
--
--int fiji_smu_init(struct amdgpu_device *adev);
--int fiji_smu_fini(struct amdgpu_device *adev);
--int fiji_smu_start(struct amdgpu_device *adev);
--
--struct fiji_smu_private_data
--{
--	uint8_t *header;
--	uint32_t smu_buffer_addr_high;
--	uint32_t smu_buffer_addr_low;
--	uint32_t header_addr_high;
--	uint32_t header_addr_low;
--};
--
--#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0109-drm-amd-powerplay-add-multimedia-power-gating-suppor.patch b/common/recipes-kernel/linux/files/0109-drm-amd-powerplay-add-multimedia-power-gating-suppor.patch
deleted file mode 100644
index 7640c2e6..00000000
--- a/common/recipes-kernel/linux/files/0109-drm-amd-powerplay-add-multimedia-power-gating-suppor.patch
+++ /dev/null
@@ -1,382 +0,0 @@
-From 8394b210923b4ee9757b3505c6a3e59d41613266 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 20 Nov 2015 15:58:11 -0500
-Subject: [PATCH 0109/1110] drm/amd/powerplay: add multimedia power gating
- support for Fiji.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   3 +-
- .../amd/powerplay/hwmgr/fiji_clockpowergating.c    | 114 ++++++++++++++++++
- .../amd/powerplay/hwmgr/fiji_clockpowergating.h    |  35 ++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   | 127 ++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h   |   5 +
- 5 files changed, 281 insertions(+), 3 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index cea032c..269fd82 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -7,7 +7,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-                cz_clockpowergating.o \
- 	       tonga_processpptables.o ppatomctrl.o \
-                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
--               fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o
-+               fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
-+               fiji_clockpowergating.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
-new file mode 100644
-index 0000000..e68edf0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
-@@ -0,0 +1,114 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "hwmgr.h"
-+#include "fiji_clockpowergating.h"
-+#include "fiji_ppsmc.h"
-+#include "fiji_hwmgr.h"
-+
-+int fiji_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+	data->samu_power_gated = false;
-+	data->acp_power_gated = false;
-+
-+	return 0;
-+}
-+
-+int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (data->uvd_power_gated == bgate)
-+		return 0;
-+
-+	data->uvd_power_gated = bgate;
-+
-+	if (bgate)
-+		fiji_update_uvd_dpm(hwmgr, true);
-+	else
-+		fiji_update_uvd_dpm(hwmgr, false);
-+
-+	return 0;
-+}
-+
-+int fiji_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct phm_set_power_state_input states;
-+	const struct pp_power_state  *pcurrent;
-+	struct pp_power_state  *requested;
-+
-+	if (data->vce_power_gated == bgate)
-+		return 0;
-+
-+	data->vce_power_gated = bgate;
-+
-+	pcurrent = hwmgr->current_ps;
-+	requested = hwmgr->request_ps;
-+
-+	states.pcurrent_state = &(pcurrent->hardware);
-+	states.pnew_state = &(requested->hardware);
-+
-+	fiji_update_vce_dpm(hwmgr, &states);
-+	fiji_enable_disable_vce_dpm(hwmgr, !bgate);
-+
-+	return 0;
-+}
-+
-+int fiji_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (data->samu_power_gated == bgate)
-+		return 0;
-+
-+	data->samu_power_gated = bgate;
-+
-+	if (bgate)
-+		fiji_update_samu_dpm(hwmgr, true);
-+	else
-+		fiji_update_samu_dpm(hwmgr, false);
-+
-+	return 0;
-+}
-+
-+int fiji_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (data->acp_power_gated == bgate)
-+		return 0;
-+
-+	data->acp_power_gated = bgate;
-+
-+	if (bgate)
-+		fiji_update_acp_dpm(hwmgr, true);
-+	else
-+		fiji_update_acp_dpm(hwmgr, false);
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.h
-new file mode 100644
-index 0000000..33af5f5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _FIJI_CLOCK_POWER_GATING_H_
-+#define _FIJI_CLOCK_POWER_GATING_H_
-+
-+#include "fiji_hwmgr.h"
-+#include "pp_asicblocks.h"
-+
-+extern int fiji_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int fiji_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int fiji_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
-+extern int fiji_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
-+#endif /* _TONGA_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 5ef92e1..b616e16 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -51,6 +51,8 @@
- #include "pp_acpi.h"
- #include "amd_pcie_helpers.h"
- 
-+#include "fiji_clockpowergating.h"
-+
- #define VOLTAGE_SCALE	4
- #define SMC_RAM_END		0x40000
- #define VDDC_VDDCI_DELTA	300
-@@ -4385,14 +4387,70 @@ static int fiji_generate_dpm_level_enable_mask(
- 	return 0;
- }
- 
--static int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+				  (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
-+				  (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
-+}
-+
-+int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
- 	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
- 			PPSMC_MSG_VCEDPM_Enable :
- 			PPSMC_MSG_VCEDPM_Disable);
- }
- 
--static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
-+int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+			PPSMC_MSG_SAMUDPM_Enable :
-+			PPSMC_MSG_SAMUDPM_Disable);
-+}
-+
-+int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+			PPSMC_MSG_ACPDPM_Enable :
-+			PPSMC_MSG_ACPDPM_Disable);
-+}
-+
-+int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.UvdBootLevel = 0;
-+		if (table_info->mm_dep_table->count > 0)
-+			data->smc_state_table.UvdBootLevel =
-+					(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0x00FFFFFF;
-+		mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_UVDDPM) ||
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDDPM_SetEnabledMask,
-+					(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
-+	}
-+
-+	return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
-+}
-+
-+int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- {
- 	const struct phm_set_power_state_input *states =
- 			(const struct phm_set_power_state_input *)input;
-@@ -4438,6 +4496,68 @@ static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- 	return 0;
- }
- 
-+int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.SamuBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFFFFFF00;
-+		mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SAMUDPM_SetEnabledMask,
-+					(uint32_t)(1 << data->smc_state_table.SamuBootLevel));
-+	}
-+
-+	return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
-+}
-+
-+int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.AcpBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFFFF00FF;
-+		mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_ACPDPM_SetEnabledMask,
-+						(uint32_t)(1 << data->smc_state_table.AcpBootLevel));
-+	}
-+
-+	return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
-+}
-+
- static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-@@ -4747,6 +4867,9 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.get_sclk = &fiji_dpm_get_sclk,
- 	.get_mclk = &fiji_dpm_get_mclk,
- 	.print_current_perforce_level = &fiji_print_current_perforce_level,
-+	.powergate_uvd = &fiji_phm_powergate_uvd,
-+	.powergate_vce = &fiji_phm_powergate_vce,
-+	.disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
- };
- 
- int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-index 22d985e..cd1e88a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -339,6 +339,11 @@ enum Fiji_I2CLineID {
- extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
- extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
- extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
-+int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
-+int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
- 
- #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
- #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0110-drm-amd-amdgpu-add-uvd6.0-clock-gating-support.-v2.patch b/common/recipes-kernel/linux/files/0110-drm-amd-amdgpu-add-uvd6.0-clock-gating-support.-v2.patch
deleted file mode 100644
index d17c4a2d..00000000
--- a/common/recipes-kernel/linux/files/0110-drm-amd-amdgpu-add-uvd6.0-clock-gating-support.-v2.patch
+++ /dev/null
@@ -1,308 +0,0 @@
-From f477863caba3cf22909f1dbce174f82d3859fb74 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 23 Nov 2015 11:20:36 -0500
-Subject: [PATCH 0110/1110] drm/amd/amdgpu: add uvd6.0 clock gating support.
- (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-v2: fix bug in register mask setting.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 261 +++++++++++++++++++++++++++++++++-
- 1 file changed, 259 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 121915b..3d59139 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -279,6 +279,234 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
- 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
- }
- 
-+static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	u32 data, data1;
-+
-+	data = RREG32(mmUVD_CGC_GATE);
-+	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
-+	if (enable) {
-+		data |= UVD_CGC_GATE__SYS_MASK |
-+				UVD_CGC_GATE__UDEC_MASK |
-+				UVD_CGC_GATE__MPEG2_MASK |
-+				UVD_CGC_GATE__RBC_MASK |
-+				UVD_CGC_GATE__LMI_MC_MASK |
-+				UVD_CGC_GATE__IDCT_MASK |
-+				UVD_CGC_GATE__MPRD_MASK |
-+				UVD_CGC_GATE__MPC_MASK |
-+				UVD_CGC_GATE__LBSI_MASK |
-+				UVD_CGC_GATE__LRBBM_MASK |
-+				UVD_CGC_GATE__UDEC_RE_MASK |
-+				UVD_CGC_GATE__UDEC_CM_MASK |
-+				UVD_CGC_GATE__UDEC_IT_MASK |
-+				UVD_CGC_GATE__UDEC_DB_MASK |
-+				UVD_CGC_GATE__UDEC_MP_MASK |
-+				UVD_CGC_GATE__WCB_MASK |
-+				UVD_CGC_GATE__VCPU_MASK |
-+				UVD_CGC_GATE__SCPU_MASK;
-+		data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_MASK |
-+				UVD_SUVD_CGC_GATE__SMP_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_MASK |
-+				UVD_SUVD_CGC_GATE__SRE_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
-+	} else {
-+		data &= ~(UVD_CGC_GATE__SYS_MASK |
-+				UVD_CGC_GATE__UDEC_MASK |
-+				UVD_CGC_GATE__MPEG2_MASK |
-+				UVD_CGC_GATE__RBC_MASK |
-+				UVD_CGC_GATE__LMI_MC_MASK |
-+				UVD_CGC_GATE__LMI_UMC_MASK |
-+				UVD_CGC_GATE__IDCT_MASK |
-+				UVD_CGC_GATE__MPRD_MASK |
-+				UVD_CGC_GATE__MPC_MASK |
-+				UVD_CGC_GATE__LBSI_MASK |
-+				UVD_CGC_GATE__LRBBM_MASK |
-+				UVD_CGC_GATE__UDEC_RE_MASK |
-+				UVD_CGC_GATE__UDEC_CM_MASK |
-+				UVD_CGC_GATE__UDEC_IT_MASK |
-+				UVD_CGC_GATE__UDEC_DB_MASK |
-+				UVD_CGC_GATE__UDEC_MP_MASK |
-+				UVD_CGC_GATE__WCB_MASK |
-+				UVD_CGC_GATE__VCPU_MASK |
-+				UVD_CGC_GATE__SCPU_MASK);
-+		data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_MASK |
-+				UVD_SUVD_CGC_GATE__SMP_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_MASK |
-+				UVD_SUVD_CGC_GATE__SRE_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_H264_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
-+	}
-+	WREG32(mmUVD_CGC_GATE, data);
-+	WREG32(mmUVD_SUVD_CGC_GATE, data1);
-+}
-+
-+static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	u32 data, data1;
-+
-+	data = RREG32(mmUVD_CGC_GATE);
-+	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
-+	if (enable) {
-+		data |= UVD_CGC_GATE__SYS_MASK |
-+				UVD_CGC_GATE__UDEC_MASK |
-+				UVD_CGC_GATE__MPEG2_MASK |
-+				UVD_CGC_GATE__RBC_MASK |
-+				UVD_CGC_GATE__LMI_MC_MASK |
-+				UVD_CGC_GATE__IDCT_MASK |
-+				UVD_CGC_GATE__MPRD_MASK |
-+				UVD_CGC_GATE__MPC_MASK |
-+				UVD_CGC_GATE__LBSI_MASK |
-+				UVD_CGC_GATE__LRBBM_MASK |
-+				UVD_CGC_GATE__UDEC_RE_MASK |
-+				UVD_CGC_GATE__UDEC_CM_MASK |
-+				UVD_CGC_GATE__UDEC_IT_MASK |
-+				UVD_CGC_GATE__UDEC_DB_MASK |
-+				UVD_CGC_GATE__UDEC_MP_MASK |
-+				UVD_CGC_GATE__WCB_MASK |
-+				UVD_CGC_GATE__VCPU_MASK |
-+				UVD_CGC_GATE__SCPU_MASK;
-+		data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_MASK |
-+				UVD_SUVD_CGC_GATE__SMP_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_MASK;
-+	} else {
-+		data &= ~(UVD_CGC_GATE__SYS_MASK |
-+				UVD_CGC_GATE__UDEC_MASK |
-+				UVD_CGC_GATE__MPEG2_MASK |
-+				UVD_CGC_GATE__RBC_MASK |
-+				UVD_CGC_GATE__LMI_MC_MASK |
-+				UVD_CGC_GATE__LMI_UMC_MASK |
-+				UVD_CGC_GATE__IDCT_MASK |
-+				UVD_CGC_GATE__MPRD_MASK |
-+				UVD_CGC_GATE__MPC_MASK |
-+				UVD_CGC_GATE__LBSI_MASK |
-+				UVD_CGC_GATE__LRBBM_MASK |
-+				UVD_CGC_GATE__UDEC_RE_MASK |
-+				UVD_CGC_GATE__UDEC_CM_MASK |
-+				UVD_CGC_GATE__UDEC_IT_MASK |
-+				UVD_CGC_GATE__UDEC_DB_MASK |
-+				UVD_CGC_GATE__UDEC_MP_MASK |
-+				UVD_CGC_GATE__WCB_MASK |
-+				UVD_CGC_GATE__VCPU_MASK |
-+				UVD_CGC_GATE__SCPU_MASK);
-+		data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_MASK |
-+				UVD_SUVD_CGC_GATE__SMP_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_MASK);
-+	}
-+	WREG32(mmUVD_CGC_GATE, data);
-+	WREG32(mmUVD_SUVD_CGC_GATE, data1);
-+}
-+
-+static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev,
-+		bool swmode)
-+{
-+	u32 data, data1 = 0, data2;
-+
-+	/* Always un-gate UVD REGS bit */
-+	data = RREG32(mmUVD_CGC_GATE);
-+	data &= ~(UVD_CGC_GATE__REGS_MASK);
-+	WREG32(mmUVD_CGC_GATE, data);
-+
-+	data = RREG32(mmUVD_CGC_CTRL);
-+	data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
-+			UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
-+	data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
-+			1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) |
-+			4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY);
-+
-+	data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
-+	if (swmode) {
-+		data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
-+				UVD_CGC_CTRL__SYS_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_MODE_MASK |
-+				UVD_CGC_CTRL__MPEG2_MODE_MASK |
-+				UVD_CGC_CTRL__REGS_MODE_MASK |
-+				UVD_CGC_CTRL__RBC_MODE_MASK |
-+				UVD_CGC_CTRL__LMI_MC_MODE_MASK |
-+				UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
-+				UVD_CGC_CTRL__IDCT_MODE_MASK |
-+				UVD_CGC_CTRL__MPRD_MODE_MASK |
-+				UVD_CGC_CTRL__MPC_MODE_MASK |
-+				UVD_CGC_CTRL__LBSI_MODE_MASK |
-+				UVD_CGC_CTRL__LRBBM_MODE_MASK |
-+				UVD_CGC_CTRL__WCB_MODE_MASK |
-+				UVD_CGC_CTRL__VCPU_MODE_MASK |
-+				UVD_CGC_CTRL__JPEG_MODE_MASK |
-+				UVD_CGC_CTRL__SCPU_MODE_MASK);
-+		data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
-+				UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK;
-+		data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK;
-+		data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID);
-+		data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
-+	} else {
-+		data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
-+				UVD_CGC_CTRL__SYS_MODE_MASK |
-+				UVD_CGC_CTRL__UDEC_MODE_MASK |
-+				UVD_CGC_CTRL__MPEG2_MODE_MASK |
-+				UVD_CGC_CTRL__REGS_MODE_MASK |
-+				UVD_CGC_CTRL__RBC_MODE_MASK |
-+				UVD_CGC_CTRL__LMI_MC_MODE_MASK |
-+				UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
-+				UVD_CGC_CTRL__IDCT_MODE_MASK |
-+				UVD_CGC_CTRL__MPRD_MODE_MASK |
-+				UVD_CGC_CTRL__MPC_MODE_MASK |
-+				UVD_CGC_CTRL__LBSI_MODE_MASK |
-+				UVD_CGC_CTRL__LRBBM_MODE_MASK |
-+				UVD_CGC_CTRL__WCB_MODE_MASK |
-+				UVD_CGC_CTRL__VCPU_MODE_MASK |
-+				UVD_CGC_CTRL__SCPU_MODE_MASK;
-+		data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
-+				UVD_SUVD_CGC_CTRL__SDB_MODE_MASK;
-+	}
-+	WREG32(mmUVD_CGC_CTRL, data);
-+	WREG32(mmUVD_SUVD_CGC_CTRL, data2);
-+
-+	data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2);
-+	data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
-+			REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
-+			REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
-+	data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
-+			REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
-+			REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
-+	data |= data1;
-+	WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data);
-+}
-+
- /**
-  * uvd_v6_0_start - start UVD block
-  *
-@@ -303,8 +531,19 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
- 
- 	uvd_v6_0_mc_resume(adev);
- 
--	/* disable clock gating */
--	WREG32(mmUVD_CGC_GATE, 0);
-+	/* Set dynamic clock gating in S/W control mode */
-+	if (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG) {
-+		if (adev->flags & AMD_IS_APU)
-+			cz_set_uvd_clock_gating_branches(adev, false);
-+		else
-+			tonga_set_uvd_clock_gating_branches(adev, false);
-+		uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
-+	} else {
-+		/* disable clock gating */
-+		uint32_t data = RREG32(mmUVD_CGC_CTRL);
-+		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
-+		WREG32(mmUVD_CGC_CTRL, data);
-+	}
- 
- 	/* disable interupt */
- 	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
-@@ -758,6 +997,24 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
- static int uvd_v6_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
-+
-+	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG))
-+		return 0;
-+
-+	if (enable) {
-+		if (adev->flags & AMD_IS_APU)
-+			cz_set_uvd_clock_gating_branches(adev, enable);
-+		else
-+			tonga_set_uvd_clock_gating_branches(adev, enable);
-+		uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
-+	} else {
-+		uint32_t data = RREG32(mmUVD_CGC_CTRL);
-+		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
-+		WREG32(mmUVD_CGC_CTRL, data);
-+	}
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0111-drm-amd-amdgpu-add-vce3.0-clock-gating-support.-v2.patch b/common/recipes-kernel/linux/files/0111-drm-amd-amdgpu-add-vce3.0-clock-gating-support.-v2.patch
deleted file mode 100644
index f85778d8..00000000
--- a/common/recipes-kernel/linux/files/0111-drm-amd-amdgpu-add-vce3.0-clock-gating-support.-v2.patch
+++ /dev/null
@@ -1,203 +0,0 @@
-From a6349c62e77d42be9211527c4acafb803431ef2b Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 23 Nov 2015 16:57:53 -0500
-Subject: [PATCH 0111/1110] drm/amd/amdgpu: add vce3.0 clock gating support.
- (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-v2: fix grbm locking
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 149 +++++++++++++++++++++++++++++++++-
- 1 file changed, 148 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index 370c6c9..35f48ad 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -103,6 +103,108 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
- 		WREG32(mmVCE_RB_WPTR2, ring->wptr);
- }
- 
-+static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
-+{
-+	u32 tmp, data;
-+
-+	tmp = data = RREG32(mmVCE_RB_ARB_CTRL);
-+	if (override)
-+		data |= VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK;
-+	else
-+		data &= ~VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK;
-+
-+	if (tmp != data)
-+		WREG32(mmVCE_RB_ARB_CTRL, data);
-+}
-+
-+static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
-+					     bool gated)
-+{
-+	u32 tmp, data;
-+	/* Set Override to disable Clock Gating */
-+	vce_v3_0_override_vce_clock_gating(adev, true);
-+
-+	if (!gated) {
-+		/* Force CLOCK ON for VCE_CLOCK_GATING_B,
-+		 * {*_FORCE_ON, *_FORCE_OFF} = {1, 0}
-+		 * VREG can be FORCE ON or set to Dynamic, but can't be OFF
-+		 */
-+		tmp = data = RREG32(mmVCE_CLOCK_GATING_B);
-+		data |= 0x1ff;
-+		data &= ~0xef0000;
-+		if (tmp != data)
-+			WREG32(mmVCE_CLOCK_GATING_B, data);
-+
-+		/* Force CLOCK ON for VCE_UENC_CLOCK_GATING,
-+		 * {*_FORCE_ON, *_FORCE_OFF} = {1, 0}
-+		 */
-+		tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING);
-+		data |= 0x3ff000;
-+		data &= ~0xffc00000;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_CLOCK_GATING, data);
-+
-+		/* set VCE_UENC_CLOCK_GATING_2 */
-+		tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
-+		data |= 0x2;
-+		data &= ~0x2;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
-+
-+		/* Force CLOCK ON for VCE_UENC_REG_CLOCK_GATING */
-+		tmp = data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
-+		data |= 0x37f;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
-+
-+		/* Force VCE_UENC_DMA_DCLK_CTRL Clock ON */
-+		tmp = data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
-+		data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
-+				VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
-+				VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
-+				0x8;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
-+	} else {
-+		/* Force CLOCK OFF for VCE_CLOCK_GATING_B,
-+		 * {*, *_FORCE_OFF} = {*, 1}
-+		 * set VREG to Dynamic, as it can't be OFF
-+		 */
-+		tmp = data = RREG32(mmVCE_CLOCK_GATING_B);
-+		data &= ~0x80010;
-+		data |= 0xe70008;
-+		if (tmp != data)
-+			WREG32(mmVCE_CLOCK_GATING_B, data);
-+		/* Force CLOCK OFF for VCE_UENC_CLOCK_GATING,
-+		 * Force ClOCK OFF takes precedent over Force CLOCK ON setting.
-+		 * {*_FORCE_ON, *_FORCE_OFF} = {*, 1}
-+		 */
-+		tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING);
-+		data |= 0xffc00000;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_CLOCK_GATING, data);
-+		/* Set VCE_UENC_CLOCK_GATING_2 */
-+		tmp = data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
-+		data |= 0x10000;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
-+		/* Set VCE_UENC_REG_CLOCK_GATING to dynamic */
-+		tmp = data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
-+		data &= ~0xffc00000;
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
-+		/* Set VCE_UENC_DMA_DCLK_CTRL CG always in dynamic mode */
-+		tmp = data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
-+		data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
-+				VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
-+				VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
-+				0x8);
-+		if (tmp != data)
-+			WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
-+	}
-+	vce_v3_0_override_vce_clock_gating(adev, false);
-+}
-+
- /**
-  * vce_v3_0_start - start VCE block
-  *
-@@ -121,7 +223,7 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
- 		if (adev->vce.harvest_config & (1 << idx))
- 			continue;
- 
--		if(idx == 0)
-+		if (idx == 0)
- 			WREG32_P(mmGRBM_GFX_INDEX, 0,
- 				~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
- 		else
-@@ -174,6 +276,10 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
- 		/* clear BUSY flag */
- 		WREG32_P(mmVCE_STATUS, 0, ~1);
- 
-+		/* Set Clock-Gating off */
-+		if (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)
-+			vce_v3_0_set_vce_sw_clock_gating(adev, false);
-+
- 		if (r) {
- 			DRM_ERROR("VCE not responding, giving up!!!\n");
- 			mutex_unlock(&adev->grbm_idx_mutex);
-@@ -609,6 +715,47 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
- static int vce_v3_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
-+	int i;
-+
-+	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG))
-+		return 0;
-+
-+	mutex_lock(&adev->grbm_idx_mutex);
-+	for (i = 0; i < 2; i++) {
-+		/* Program VCE Instance 0 or 1 if not harvested */
-+		if (adev->vce.harvest_config & (1 << i))
-+			continue;
-+
-+		if (i == 0)
-+			WREG32_P(mmGRBM_GFX_INDEX, 0,
-+					~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
-+		else
-+			WREG32_P(mmGRBM_GFX_INDEX,
-+					GRBM_GFX_INDEX__VCE_INSTANCE_MASK,
-+					~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
-+
-+		if (enable) {
-+			/* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
-+			uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
-+			data &= ~(0xf | 0xff0);
-+			data |= ((0x0 << 0) | (0x04 << 4));
-+			WREG32(mmVCE_CLOCK_GATING_A, data);
-+
-+			/* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */
-+			data = RREG32(mmVCE_UENC_CLOCK_GATING);
-+			data &= ~(0xf | 0xff0);
-+			data |= ((0x0 << 0) | (0x04 << 4));
-+			WREG32(mmVCE_UENC_CLOCK_GATING, data);
-+		}
-+
-+		vce_v3_0_set_vce_sw_clock_gating(adev, enable);
-+	}
-+
-+	WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
-+	mutex_unlock(&adev->grbm_idx_mutex);
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0112-drm-amd-amdgpu-enable-uvd-vce-clock-gating-for-Fiji.patch b/common/recipes-kernel/linux/files/0112-drm-amd-amdgpu-enable-uvd-vce-clock-gating-for-Fiji.patch
deleted file mode 100644
index bd9c1d24..00000000
--- a/common/recipes-kernel/linux/files/0112-drm-amd-amdgpu-enable-uvd-vce-clock-gating-for-Fiji.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c66d5f9b8236a782c7810ada7245e9857def1ed8 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 24 Nov 2015 10:53:27 -0500
-Subject: [PATCH 0112/1110] drm/amd/amdgpu: enable uvd&vce clock gating for
- Fiji.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 89f5a1f..d94c625 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1443,7 +1443,8 @@ static int vi_common_early_init(void *handle)
- 		break;
- 	case CHIP_FIJI:
- 		adev->has_uvd = true;
--		adev->cg_flags = 0;
-+		adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
-+				AMDGPU_CG_SUPPORT_VCE_MGCG;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0113-drm-amdgpu-Prepare-DKMS-build-for-powerplay-module.patch b/common/recipes-kernel/linux/files/0113-drm-amdgpu-Prepare-DKMS-build-for-powerplay-module.patch
deleted file mode 100644
index 8c040b23..00000000
--- a/common/recipes-kernel/linux/files/0113-drm-amdgpu-Prepare-DKMS-build-for-powerplay-module.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From c38b364e83c27c8e2d5697ff048956d208a72913 Mon Sep 17 00:00:00 2001
-From: Qiang Yu <Qiang.Yu@amd.com>
-Date: Wed, 2 Dec 2015 10:56:57 +0800
-Subject: [PATCH 0113/1110] drm/amdgpu: Prepare DKMS build for powerplay
- module.
-
-Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index 4c856fe..20c9539 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -101,7 +101,7 @@ amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
- 
- ifneq ($(CONFIG_DRM_AMD_POWERPLAY),)
- 
--include drivers/gpu/drm/amd/powerplay/Makefile
-+include $(FULL_AMD_PATH)/powerplay/Makefile
- 
- amdgpu-y += $(AMD_POWERPLAY_FILES)
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0114-drm-amd-powerplay-add-display-configeration-changed-.patch b/common/recipes-kernel/linux/files/0114-drm-amd-powerplay-add-display-configeration-changed-.patch
deleted file mode 100644
index 077acb42..00000000
--- a/common/recipes-kernel/linux/files/0114-drm-amd-powerplay-add-display-configeration-changed-.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 139780b3c235ec7f94b5cc22d65f7340b85027e4 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 24 Nov 2015 17:00:56 -0500
-Subject: [PATCH 0114/1110] drm/amd/powerplay: add display configeration
- changed function in hwmgr for Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 66 ++++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h |  2 +
- 2 files changed, 68 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index b616e16..00d2e17 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -3434,6 +3434,10 @@ static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
- 			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
- 
-+	tmp_result = tonga_notify_smc_display_change(hwmgr, false);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to notify no display!", result = tmp_result);
-+
- 	tmp_result = fiji_enable_sclk_control(hwmgr);
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
- 			"Failed to enable SCLK control!", result = tmp_result);
-@@ -4852,6 +4856,65 @@ static void fiji_print_current_perforce_level(
- 			mclk / 100, sclk / 100);
- }
- 
-+static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	uint32_t num_active_displays = 0;
-+	uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
-+	uint32_t display_gap2;
-+	uint32_t pre_vbi_time_in_us;
-+	uint32_t frame_time_in_us;
-+	uint32_t ref_clock;
-+	uint32_t refresh_rate = 0;
-+	struct cgs_display_info info = {0};
-+	struct cgs_mode_info mode_info;
-+
-+	info.mode_info = &mode_info;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	num_active_displays = info.display_count;
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP, (num_active_displays > 0)?
-+			DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	ref_clock = mode_info.ref_clock;
-+	refresh_rate = mode_info.refresh_rate;
-+
-+	if (refresh_rate == 0)
-+		refresh_rate = 60;
-+
-+	frame_time_in_us = 1000000 / refresh_rate;
-+
-+	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
-+	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			data->soft_regs_start +
-+			offsetof(SMU73_SoftRegisters, PreVBlankGap), 0x64);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			data->soft_regs_start +
-+			offsetof(SMU73_SoftRegisters, VBlankTimeout),
-+			(frame_time_in_us - pre_vbi_time_in_us));
-+
-+	if (num_active_displays == 1)
-+		tonga_notify_smc_display_change(hwmgr, true);
-+
-+	return 0;
-+}
-+
-+int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
-+{
-+	return fiji_program_display_gap(hwmgr);
-+}
-+
- static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.backend_init = &fiji_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -4870,6 +4933,9 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.powergate_uvd = &fiji_phm_powergate_uvd,
- 	.powergate_vce = &fiji_phm_powergate_vce,
- 	.disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
-+	.notify_smc_display_config_after_ps_adjustment =
-+			&tonga_notify_smc_display_config_after_ps_adjustment,
-+	.display_config_changed = &fiji_display_configuration_changed_task,
- };
- 
- int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-index cd1e88a..22e273b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -339,6 +339,8 @@ enum Fiji_I2CLineID {
- extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
- extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
- extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
-+extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
-+extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
- int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
- int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
- int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0115-drm-amd-powerplay-Add-thermal-protection-support-for.patch b/common/recipes-kernel/linux/files/0115-drm-amd-powerplay-Add-thermal-protection-support-for.patch
deleted file mode 100644
index dc93cef2..00000000
--- a/common/recipes-kernel/linux/files/0115-drm-amd-powerplay-Add-thermal-protection-support-for.patch
+++ /dev/null
@@ -1,976 +0,0 @@
-From c990b28981e5da2687a8e720393c4daaab36980f Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 27 Nov 2015 14:09:53 -0500
-Subject: [PATCH 0115/1110] drm/amd/powerplay: Add thermal protection support
- for Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   | 143 +++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c | 687 +++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h |  61 ++
- 4 files changed, 892 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index 269fd82..b664e34 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -8,7 +8,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
- 	       tonga_processpptables.o ppatomctrl.o \
-                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
-                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
--               fiji_clockpowergating.o
-+               fiji_clockpowergating.o fiji_thermal.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 00d2e17..8de045f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -50,8 +50,11 @@
- #include "pp_debug.h"
- #include "pp_acpi.h"
- #include "amd_pcie_helpers.h"
-+#include "cgs_linux.h"
-+#include "ppinterrupt.h"
- 
- #include "fiji_clockpowergating.h"
-+#include "fiji_thermal.h"
- 
- #define VOLTAGE_SCALE	4
- #define SMC_RAM_END		0x40000
-@@ -694,6 +697,31 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
- 		hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
- 
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_FanSpeedInTableIsRPM);
-+
-+		if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucFanControlMode) {
-+			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
-+					hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
-+			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
-+					hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
-+			hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
-+					table_info->cac_dtp_table->usOperatingTempMinLimit;
-+			hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
-+					table_info->cac_dtp_table->usOperatingTempMaxLimit;
-+			hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
-+					table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
-+			hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
-+					table_info->cac_dtp_table->usOperatingTempStep;
-+			hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
-+					table_info->cac_dtp_table->usTargetOperatingTemp;
-+
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_ODFuzzyFanControlSupport);
-+		}
-+
- 		sys_info.size = sizeof(struct cgs_system_info);
- 		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
- 		result = cgs_query_system_info(hwmgr->device, &sys_info);
-@@ -4915,6 +4943,108 @@ int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
- 	return fiji_program_display_gap(hwmgr);
- }
- 
-+static int fiji_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr,
-+		uint16_t us_max_fan_pwm)
-+{
-+	hwmgr->thermal_controller.
-+	advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
-+}
-+
-+static int fiji_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr,
-+		uint16_t us_max_fan_rpm)
-+{
-+	hwmgr->thermal_controller.
-+	advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
-+}
-+
-+int fiji_dpm_set_interrupt_state(void *private_data,
-+					 unsigned src_id, unsigned type,
-+					 int enabled)
-+{
-+	uint32_t cg_thermal_int;
-+	struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	switch (type) {
-+	case AMD_THERMAL_IRQ_LOW_TO_HIGH:
-+		if (enabled) {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		} else {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		}
-+		break;
-+
-+	case AMD_THERMAL_IRQ_HIGH_TO_LOW:
-+		if (enabled) {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		} else {
-+			cg_thermal_int = cgs_read_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT);
-+			cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-+			cgs_write_ind_register(hwmgr->device,
-+					CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	return 0;
-+}
-+
-+int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
-+					const void *thermal_interrupt_info)
-+{
-+	int result;
-+	const struct pp_interrupt_registration_info *info =
-+			(const struct pp_interrupt_registration_info *)
-+			thermal_interrupt_info;
-+
-+	if (info == NULL)
-+		return -EINVAL;
-+
-+	result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
-+				fiji_dpm_set_interrupt_state,
-+				info->call_back, info->context);
-+
-+	if (result)
-+		return -EINVAL;
-+
-+	result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
-+				fiji_dpm_set_interrupt_state,
-+				info->call_back, info->context);
-+
-+	if (result)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.backend_init = &fiji_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -4936,6 +5066,18 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.notify_smc_display_config_after_ps_adjustment =
- 			&tonga_notify_smc_display_config_after_ps_adjustment,
- 	.display_config_changed = &fiji_display_configuration_changed_task,
-+	.set_max_fan_pwm_output = fiji_set_max_fan_pwm_output,
-+	.set_max_fan_rpm_output = fiji_set_max_fan_rpm_output,
-+	.get_temperature = fiji_thermal_get_temperature,
-+	.stop_thermal_controller = fiji_thermal_stop_thermal_controller,
-+	.get_fan_speed_info = fiji_fan_ctrl_get_fan_speed_info,
-+	.get_fan_speed_percent = fiji_fan_ctrl_get_fan_speed_percent,
-+	.set_fan_speed_percent = fiji_fan_ctrl_set_fan_speed_percent,
-+	.reset_fan_speed_to_default = fiji_fan_ctrl_reset_fan_speed_to_default,
-+	.get_fan_speed_rpm = fiji_fan_ctrl_get_fan_speed_rpm,
-+	.set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
-+	.uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
-+	.register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
- };
- 
- int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
-@@ -4950,5 +5092,6 @@ int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
- 	hwmgr->backend = data;
- 	hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
- 	hwmgr->pptable_func = &tonga_pptable_funcs;
-+	pp_fiji_thermal_initialize(hwmgr);
- 	return ret;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-new file mode 100644
-index 0000000..1b2eaa9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-@@ -0,0 +1,687 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "fiji_thermal.h"
-+#include "fiji_hwmgr.h"
-+#include "fiji_smumgr.h"
-+#include "fiji_ppsmc.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+
-+int fiji_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
-+		struct phm_fan_speed_info *fan_speed_info)
-+{
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	fan_speed_info->supports_percent_read = true;
-+	fan_speed_info->supports_percent_write = true;
-+	fan_speed_info->min_percent = 0;
-+	fan_speed_info->max_percent = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
-+		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
-+		fan_speed_info->supports_rpm_read = true;
-+		fan_speed_info->supports_rpm_write = true;
-+		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
-+		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
-+	} else {
-+		fan_speed_info->min_rpm = 0;
-+		fan_speed_info->max_rpm = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+int fiji_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
-+		uint32_t *speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_STATUS, FDO_PWM_DUTY);
-+
-+	if (duty100 == 0)
-+		return -EINVAL;
-+
-+
-+	tmp64 = (uint64_t)duty * 100;
-+	do_div(tmp64, duty100);
-+	*speed = (uint32_t)tmp64;
-+
-+	if (*speed > 100)
-+		*speed = 100;
-+
-+	return 0;
-+}
-+
-+int fiji_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
-+{
-+	uint32_t tach_period;
-+	uint32_t crystal_clock_freq;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
-+			(hwmgr->thermal_controller.fanInfo.
-+				ucTachometerPulsesPerRevolution == 0))
-+		return 0;
-+
-+	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_TACH_STATUS, TACH_PERIOD);
-+
-+	if (tach_period == 0)
-+		return -EINVAL;
-+
-+	crystal_clock_freq = tonga_get_xclk(hwmgr);
-+
-+	*speed = 60 * crystal_clock_freq * 10000/ tach_period;
-+
-+	return 0;
-+}
-+
-+/**
-+* Set Fan Speed Control to static mode, so that the user can decide what speed to use.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*           mode    the fan control mode, 0 default, 1 by percent, 5, by RPM
-+* @exception Should always succeed.
-+*/
-+int fiji_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+
-+	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+		hwmgr->fan_ctrl_default_mode =
-+				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,	CGS_IND_REG__SMC,
-+						CG_FDO_CTRL2, FDO_PWM_MODE);
-+		hwmgr->tmin =
-+				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+						CG_FDO_CTRL2, TMIN);
-+		hwmgr->fan_ctrl_is_in_default_mode = false;
-+	}
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, TMIN, 0);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, FDO_PWM_MODE, mode);
-+
-+	return 0;
-+}
-+
-+/**
-+* Reset Fan Speed Control to default mode.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Should always succeed.
-+*/
-+int fiji_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, TMIN, hwmgr->tmin);
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	}
-+
-+	return 0;
-+}
-+
-+int fiji_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
-+		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_FanSpeedInTableIsRPM))
-+			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
-+					hwmgr->thermal_controller.
-+					advanceFanControlParameters.usMaxFanRPM);
-+		else
-+			hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
-+					hwmgr->thermal_controller.
-+					advanceFanControlParameters.usMaxFanPWM);
-+
-+	} else {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
-+		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+	}
-+
-+	if (!result && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucTargetTemperature)
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanTemperatureTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucTargetTemperature);
-+
-+	return result;
-+}
-+
-+
-+int fiji_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
-+}
-+
-+/**
-+* Set Fan Speed in percent.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (0% - 100%) to be set.
-+* @exception Fails is the 100% setting appears to be 0.
-+*/
-+int fiji_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
-+		uint32_t speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (speed > 100)
-+		speed = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl))
-+		fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0)
-+		return -EINVAL;
-+
-+	tmp64 = (uint64_t)speed * 100;
-+	do_div(tmp64, duty100);
-+	duty = (uint32_t)tmp64;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
-+
-+	return fiji_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reset Fan Speed to default.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Always succeeds.
-+*/
-+int fiji_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl)) {
-+		result = fiji_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+		if (!result)
-+			result = fiji_fan_ctrl_start_smc_fan_control(hwmgr);
-+	} else
-+		result = fiji_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set Fan Speed in RPM.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (min - max) to be set.
-+* @exception Fails is the speed not lie between min and max.
-+*/
-+int fiji_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
-+{
-+	uint32_t tach_period;
-+	uint32_t crystal_clock_freq;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
-+			(hwmgr->thermal_controller.fanInfo.
-+			ucTachometerPulsesPerRevolution == 0) ||
-+			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
-+			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
-+		return 0;
-+
-+	crystal_clock_freq = tonga_get_xclk(hwmgr);
-+
-+	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_TACH_STATUS, TACH_PERIOD, tach_period);
-+
-+	return fiji_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reads the remote temperature from the SIslands thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int fiji_thermal_get_temperature(struct pp_hwmgr *hwmgr)
-+{
-+	int temp;
-+
-+	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_STATUS, CTF_TEMP);
-+
-+	/* Bit 9 means the reading is lower than the lowest usable value. */
-+	if (temp & 0x200)
-+		temp = FIJI_THERMAL_MAXIMUM_TEMP_READING;
-+	else
-+		temp = temp & 0x1ff;
-+
-+	temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	return temp;
-+}
-+
-+/**
-+* Set the requested temperature range for high and low alert signals
-+*
-+* @param    hwmgr The address of the hardware manager.
-+* @param    range Temperature range to be programmed for high and low alert signals
-+* @exception PP_Result_BadInput if the input data is not valid.
-+*/
-+static int fiji_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-+		uint32_t low_temp, uint32_t high_temp)
-+{
-+	uint32_t low = FIJI_THERMAL_MINIMUM_ALERT_TEMP *
-+			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+	uint32_t high = FIJI_THERMAL_MAXIMUM_ALERT_TEMP *
-+			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	if (low < low_temp)
-+		low = low_temp;
-+	if (high > high_temp)
-+		high = high_temp;
-+
-+	if (low > high)
-+		return -EINVAL;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, DIG_THERM_INTH,
-+			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, DIG_THERM_INTL,
-+			(low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_CTRL, DIG_THERM_DPM,
-+			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs thermal controller one-time setting registers
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int fiji_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_TACH_CTRL, EDGE_PER_REV,
-+				hwmgr->thermal_controller.fanInfo.
-+				ucTachometerPulsesPerRevolution - 1);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
-+
-+	return 0;
-+}
-+
-+/**
-+* Enable thermal alerts on the RV770 thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int fiji_thermal_enable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK);
-+	alert &= ~(FIJI_THERMAL_HIGH_ALERT_MASK | FIJI_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to enable internal thermal interrupts */
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
-+}
-+
-+/**
-+* Disable thermal alerts on the RV770 thermal controller.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int fiji_thermal_disable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK);
-+	alert |= (FIJI_THERMAL_HIGH_ALERT_MASK | FIJI_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to disable internal thermal interrupts */
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
-+}
-+
-+/**
-+* Uninitialize the thermal controller.
-+* Currently just disables alerts.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int fiji_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	int result = fiji_thermal_disable_alert(hwmgr);
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		fiji_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set up the fan table to control the fan using the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (data->fan_table_start == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
-+			usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->
-+			thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = tonga_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
-+			thermal_controller.advanceFanControlParameters.ulCycleDelay *
-+			reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
-+			hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	res = fiji_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start,
-+			(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
-+			data->sram_end);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucMinimumPWMLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanMinPwm,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucMinimumPWMLimit);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanSclkTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-+
-+	if (res)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+
-+	return 0;
-+}
-+
-+/**
-+* Start the fan control on the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_fiji_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+/* If the fantable setup has failed we could have disabled
-+ * PHM_PlatformCaps_MicrocodeFanControl even after
-+ * this function was included in the table.
-+ * Make sure that we still think controlling the fan is OK.
-+*/
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl)) {
-+		fiji_fan_ctrl_start_smc_fan_control(hwmgr);
-+		fiji_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Set temperature range for high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_fiji_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
-+
-+	if (range == NULL)
-+		return -EINVAL;
-+
-+	return fiji_thermal_set_temperature_range(hwmgr, range->min, range->max);
-+}
-+
-+/**
-+* Programs one-time setting registers
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from initialize thermal controller routine
-+*/
-+int tf_fiji_thermal_initialize(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+    return fiji_thermal_initialize(hwmgr);
-+}
-+
-+/**
-+* Enable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from enable alert routine
-+*/
-+int tf_fiji_thermal_enable_alert(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	return fiji_thermal_enable_alert(hwmgr);
-+}
-+
-+/**
-+* Disable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from disable alert routine
-+*/
-+static int tf_fiji_thermal_disable_alert(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	return fiji_thermal_disable_alert(hwmgr);
-+}
-+
-+static struct phm_master_table_item
-+fiji_thermal_start_thermal_controller_master_list[] = {
-+	{NULL, tf_fiji_thermal_initialize},
-+	{NULL, tf_fiji_thermal_set_temperature_range},
-+	{NULL, tf_fiji_thermal_enable_alert},
-+/* We should restrict performance levels to low before we halt the SMC.
-+ * On the other hand we are still in boot state when we do this
-+ * so it would be pointless.
-+ * If this assumption changes we have to revisit this table.
-+ */
-+	{NULL, tf_fiji_thermal_setup_fan_table},
-+	{NULL, tf_fiji_thermal_start_smc_fan_control},
-+	{NULL, NULL}
-+};
-+
-+static struct phm_master_table_header
-+fiji_thermal_start_thermal_controller_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	fiji_thermal_start_thermal_controller_master_list
-+};
-+
-+static struct phm_master_table_item
-+fiji_thermal_set_temperature_range_master_list[] = {
-+	{NULL, tf_fiji_thermal_disable_alert},
-+	{NULL, tf_fiji_thermal_set_temperature_range},
-+	{NULL, tf_fiji_thermal_enable_alert},
-+	{NULL, NULL}
-+};
-+
-+struct phm_master_table_header
-+fiji_thermal_set_temperature_range_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	fiji_thermal_set_temperature_range_master_list
-+};
-+
-+int fiji_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
-+		fiji_fan_ctrl_set_default_mode(hwmgr);
-+	return 0;
-+}
-+
-+/**
-+* Initializes the thermal controller related functions in the Hardware Manager structure.
-+* @param    hwmgr The address of the hardware manager.
-+* @exception Any error code from the low-level communication.
-+*/
-+int pp_fiji_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	result = phm_construct_table(hwmgr,
-+			&fiji_thermal_set_temperature_range_master,
-+			&(hwmgr->set_temperature_range));
-+
-+	if (!result) {
-+		result = phm_construct_table(hwmgr,
-+				&fiji_thermal_start_thermal_controller_master,
-+				&(hwmgr->start_thermal_controller));
-+		if (result)
-+			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
-+	}
-+
-+	if (!result)
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	return result;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h
-new file mode 100644
-index 0000000..c3ee552
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h
-@@ -0,0 +1,61 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef FIJI_THERMAL_H
-+#define FIJI_THERMAL_H
-+
-+#include "hwmgr.h"
-+
-+#define FIJI_THERMAL_HIGH_ALERT_MASK         0x1
-+#define FIJI_THERMAL_LOW_ALERT_MASK          0x2
-+
-+#define FIJI_THERMAL_MINIMUM_TEMP_READING    -256
-+#define FIJI_THERMAL_MAXIMUM_TEMP_READING    255
-+
-+#define FIJI_THERMAL_MINIMUM_ALERT_TEMP      0
-+#define FIJI_THERMAL_MAXIMUM_ALERT_TEMP      255
-+
-+#define FDO_PWM_MODE_STATIC  1
-+#define FDO_PWM_MODE_STATIC_RPM 5
-+
-+
-+extern int tf_fiji_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_fiji_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_fiji_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+
-+extern int fiji_thermal_get_temperature(struct pp_hwmgr *hwmgr);
-+extern int fiji_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int fiji_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
-+extern int fiji_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int fiji_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
-+extern int fiji_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
-+extern int fiji_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int fiji_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-+extern int pp_fiji_thermal_initialize(struct pp_hwmgr *hwmgr);
-+extern int fiji_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int fiji_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int fiji_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
-+
-+#endif
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0116-drm-amd-powerplay-Fix-a-bug-in-fan-control-setting-d.patch b/common/recipes-kernel/linux/files/0116-drm-amd-powerplay-Fix-a-bug-in-fan-control-setting-d.patch
deleted file mode 100644
index 7face117..00000000
--- a/common/recipes-kernel/linux/files/0116-drm-amd-powerplay-Fix-a-bug-in-fan-control-setting-d.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From de1acf4abcfe4f6b462671de21f72eccd72d592f Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 3 Dec 2015 15:13:46 -0500
-Subject: [PATCH 0116/1110] drm/amd/powerplay: Fix a bug in fan control setting
- default mode for Tonga and Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c  | 2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-index 1b2eaa9..def57d0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-@@ -141,7 +141,7 @@ int fiji_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
- */
- int fiji_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+	if (!hwmgr->fan_ctrl_is_in_default_mode) {
- 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
- 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-index a315507..5da7586 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-@@ -129,7 +129,7 @@ int tonga_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
- */
- int tonga_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+	if (!hwmgr->fan_ctrl_is_in_default_mode) {
- 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
- 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL2, TMIN, hwmgr->tmin);
- 		hwmgr->fan_ctrl_is_in_default_mode = true;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0117-drm-amd-powerplay-add-functions-set-get_fan_control_.patch b/common/recipes-kernel/linux/files/0117-drm-amd-powerplay-add-functions-set-get_fan_control_.patch
deleted file mode 100644
index b14f7cb8..00000000
--- a/common/recipes-kernel/linux/files/0117-drm-amd-powerplay-add-functions-set-get_fan_control_.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 60aa09ae95c3e8b3a62f1f92974158a15b1bb62c Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 4 Dec 2015 10:57:22 -0500
-Subject: [PATCH 0117/1110] drm/amd/powerplay: add functions
- set/get_fan_control_mode in hwmgr for Tonga.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  | 26 ++++++++++++++++++++++
- .../gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h    |  1 +
- 2 files changed, 27 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index fd32be2..4ef06ec 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -5983,6 +5983,30 @@ int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_st
- 	return 0;
- }
- 
-+static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+	if (mode) {
-+		/* stop auto-manage */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl))
-+			tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
-+		tonga_fan_ctrl_set_static_mode(hwmgr, mode);
-+	} else
-+		/* restart auto-manage */
-+		tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->fan_ctrl_is_in_default_mode)
-+		return hwmgr->fan_ctrl_default_mode;
-+	else
-+		return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, FDO_PWM_MODE);
-+}
-+
- static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.backend_init = &tonga_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -6018,6 +6042,8 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
- 	.check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
- 	.check_states_equal = tonga_check_states_equal,
-+	.set_fan_control_mode = tonga_set_fan_control_mode,
-+	.get_fan_control_mode = tonga_get_fan_control_mode,
- };
- 
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h
-index 07680a7..aa335f2 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.h
-@@ -55,6 +55,7 @@ extern int pp_tonga_thermal_initialize(struct pp_hwmgr *hwmgr);
- extern int tonga_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
- extern int tonga_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
- extern int tonga_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int tonga_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
- 
- #endif
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0118-drm-amd-powerplay-add-functions-set-get_fan_control_.patch b/common/recipes-kernel/linux/files/0118-drm-amd-powerplay-add-functions-set-get_fan_control_.patch
deleted file mode 100644
index e2c2856a..00000000
--- a/common/recipes-kernel/linux/files/0118-drm-amd-powerplay-add-functions-set-get_fan_control_.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 8d12f79a32fa0185db53a072bd11bc80268a82e6 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 4 Dec 2015 15:49:02 -0500
-Subject: [PATCH 0118/1110] drm/amd/powerplay: add functions
- set/get_fan_control_mode in hwmgr for Fiji.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   | 26 ++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h |  1 +
- 2 files changed, 27 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 8de045f..fec0789 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -5045,6 +5045,30 @@ int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
-+static int fiji_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+	if (mode) {
-+		/* stop auto-manage */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl))
-+			fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
-+		fiji_fan_ctrl_set_static_mode(hwmgr, mode);
-+	} else
-+		/* restart auto-manage */
-+		fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->fan_ctrl_is_in_default_mode)
-+		return hwmgr->fan_ctrl_default_mode;
-+	else
-+		return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, FDO_PWM_MODE);
-+}
-+
- static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.backend_init = &fiji_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -5078,6 +5102,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
- 	.uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
- 	.register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
-+	.set_fan_control_mode = fiji_set_fan_control_mode,
-+	.get_fan_control_mode = fiji_get_fan_control_mode,
- };
- 
- int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h
-index c3ee552..8621493 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.h
-@@ -55,6 +55,7 @@ extern int pp_fiji_thermal_initialize(struct pp_hwmgr *hwmgr);
- extern int fiji_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
- extern int fiji_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
- extern int fiji_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int fiji_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
- extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0119-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch b/common/recipes-kernel/linux/files/0119-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch
deleted file mode 100644
index 10db476b..00000000
--- a/common/recipes-kernel/linux/files/0119-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 1e30465fa34c7c003f906aed4dd4efd8722de611 Mon Sep 17 00:00:00 2001
-From: kbuild test robot <fengguang.wu@intel.com>
-Date: Fri, 4 Dec 2015 19:13:27 -0500
-Subject: [PATCH 0119/1110] drm/amd/powerplay: fix boolreturn.cocci warnings
-
-drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomctrl.c:475:10-11: WARNING: return of 0/1 in function 'atomctrl_lookup_gpio_pin' with return type bool
-
- Return statements in functions returning bool should use
- true/false instead of 1/0.
-Generated by: scripts/coccinelle/misc/boolreturn.cocci
-
-CC: yanyang1 <young.yang@amd.com>
-Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-index ea87c90..2a83a4a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-@@ -521,13 +521,13 @@ static bool atomctrl_lookup_gpio_pin(
- 				pin_assignment->ucGpioPinBitShift;
- 			gpio_pin_assignment->us_gpio_pin_aindex =
- 				le16_to_cpu(pin_assignment->usGpioPin_AIndex);
--			return 0;
-+			return false;
- 		}
- 
- 		offset += offsetof(ATOM_GPIO_PIN_ASSIGNMENT, ucGPIO_ID) + 1;
- 	}
- 
--	return 1;
-+	return true;
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0120-drm-amd-powerplay-fix-bug-that-dpm-funcs-in-debugfs-.patch b/common/recipes-kernel/linux/files/0120-drm-amd-powerplay-fix-bug-that-dpm-funcs-in-debugfs-.patch
deleted file mode 100644
index 9d6c0a5d..00000000
--- a/common/recipes-kernel/linux/files/0120-drm-amd-powerplay-fix-bug-that-dpm-funcs-in-debugfs-.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 3ad4f595b8d3a74d5d280bee9b6e7b8c4c3146f6 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 7 Dec 2015 16:42:35 +0800
-Subject: [PATCH 0120/1110] drm/amd/powerplay: fix bug that dpm funcs in
- debugfs/sysfs missing.
-
-in dpm module, sysfs init func move to late_init from sw_init.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-
-Change-Id: Ice4a73212d8e3106d05f04a27043820ffd32929e
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 15 ++++++++++++++-
- 1 file changed, 14 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 4f6740c..6cbbae7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -121,6 +121,19 @@ static int amdgpu_pp_early_init(void *handle)
- 	return ret;
- }
- 
-+
-+static int amdgpu_pp_late_init(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->powerplay.ip_funcs->late_init)
-+		ret = adev->powerplay.ip_funcs->late_init(
-+					adev->powerplay.pp_handle);
-+
-+	return ret;
-+}
-+
- static int amdgpu_pp_sw_init(void *handle)
- {
- 	int ret = 0;
-@@ -282,7 +295,7 @@ static void amdgpu_pp_print_status(void *handle)
- 
- const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
- 	.early_init = amdgpu_pp_early_init,
--	.late_init = NULL,
-+	.late_init = amdgpu_pp_late_init,
- 	.sw_init = amdgpu_pp_sw_init,
- 	.sw_fini = amdgpu_pp_sw_fini,
- 	.hw_init = amdgpu_pp_hw_init,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0121-drm-amd-powerplay-check-whether-enable-dpm-in-powerp.patch b/common/recipes-kernel/linux/files/0121-drm-amd-powerplay-check-whether-enable-dpm-in-powerp.patch
deleted file mode 100644
index d0f8b99e..00000000
--- a/common/recipes-kernel/linux/files/0121-drm-amd-powerplay-check-whether-enable-dpm-in-powerp.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 27b8581febea0979f10a7a3d1e34e961eb70ad0f Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 23 Nov 2015 14:50:10 +0800
-Subject: [PATCH 0121/1110] drm/amd/powerplay: check whether enable dpm in
- powerplay.
-
-Change-Id: I0a2dbf8ef7d4a3e9788fe211fc5964dd2487c519
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 6cbbae7..b8b4a47 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -145,8 +145,11 @@ static int amdgpu_pp_sw_init(void *handle)
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	if (adev->pp_enabled) {
--		adev->pm.dpm_enabled = true;
- 		amdgpu_pm_sysfs_init(adev);
-+		if (amdgpu_dpm == 0)
-+			adev->pm.dpm_enabled = false;
-+		else
-+			adev->pm.dpm_enabled = true;
- 	}
- #endif
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0122-drm-amd-powerplay-move-shared-function-of-vi-to-hwmg.patch b/common/recipes-kernel/linux/files/0122-drm-amd-powerplay-move-shared-function-of-vi-to-hwmg.patch
deleted file mode 100644
index eaabdeba..00000000
--- a/common/recipes-kernel/linux/files/0122-drm-amd-powerplay-move-shared-function-of-vi-to-hwmg.patch
+++ /dev/null
@@ -1,488 +0,0 @@
-From e3a99cfd915c79a5e5026310d39fa37104a66b11 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 3 Dec 2015 14:16:01 +0800
-Subject: [PATCH 0122/1110] drm/amd/powerplay: move shared function of vi to
- hwmgr. (v2)
-
-v2: agd: rebase on upstream
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c  |   6 -
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c       | 336 +++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c |   8 -
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  48 +++-
- 4 files changed, 379 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index fec0789..94f404c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -91,12 +91,6 @@ enum DPM_EVENT_SRC {
-     DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
- };
- 
--enum DISPLAY_GAP {
--	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
--	DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
--	DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. */
--	DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
--};
- 
- /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
-  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index 618cc4d..ca4554b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -27,9 +27,12 @@
- #include "cgs_common.h"
- #include "power_state.h"
- #include "hwmgr.h"
--#include "cz_hwmgr.h"
--#include "tonga_hwmgr.h"
-+#include "pppcielanes.h"
-+#include "pp_debug.h"
-+#include "ppatomctrl.h"
- 
-+extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
-+extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
- extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
- 
- int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
-@@ -112,6 +115,7 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
- 
- 	for (i = 0; i < table_entries; i++) {
- 		result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
-+
- 		if (state->classification.flags & PP_StateClassificationFlag_Boot) {
- 			hwmgr->boot_ps = state;
- 			hwmgr->current_ps = hwmgr->request_ps = state;
-@@ -226,3 +230,331 @@ bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
- {
- 	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
- }
-+
-+
-+int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
-+{
-+	uint32_t i, j;
-+	uint16_t vvalue;
-+	bool found = false;
-+	struct pp_atomctrl_voltage_table *table;
-+
-+	PP_ASSERT_WITH_CODE((NULL != vol_table),
-+			"Voltage Table empty.", return -EINVAL);
-+
-+	table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
-+			GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -EINVAL;
-+
-+	table->mask_low = vol_table->mask_low;
-+	table->phase_delay = vol_table->phase_delay;
-+
-+	for (i = 0; i < vol_table->count; i++) {
-+		vvalue = vol_table->entries[i].value;
-+		found = false;
-+
-+		for (j = 0; j < table->count; j++) {
-+			if (vvalue == table->entries[j].value) {
-+				found = true;
-+				break;
-+			}
-+		}
-+
-+		if (!found) {
-+			table->entries[table->count].value = vvalue;
-+			table->entries[table->count].smio_low =
-+					vol_table->entries[i].smio_low;
-+			table->count++;
-+		}
-+	}
-+
-+	memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
-+	kfree(table);
-+
-+	return 0;
-+}
-+
-+int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
-+		phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-+{
-+	uint32_t i;
-+	int result;
-+
-+	PP_ASSERT_WITH_CODE((0 != dep_table->count),
-+			"Voltage Dependency Table empty.", return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE((NULL != vol_table),
-+			"vol_table empty.", return -EINVAL);
-+
-+	vol_table->mask_low = 0;
-+	vol_table->phase_delay = 0;
-+	vol_table->count = dep_table->count;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		vol_table->entries[i].value = dep_table->entries[i].mvdd;
-+		vol_table->entries[i].smio_low = 0;
-+	}
-+
-+	result = phm_trim_voltage_table(vol_table);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to trim MVDD table.", return result);
-+
-+	return 0;
-+}
-+
-+int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
-+		phm_ppt_v1_clock_voltage_dependency_table *dep_table)
-+{
-+	uint32_t i;
-+	int result;
-+
-+	PP_ASSERT_WITH_CODE((0 != dep_table->count),
-+			"Voltage Dependency Table empty.", return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE((NULL != vol_table),
-+			"vol_table empty.", return -EINVAL);
-+
-+	vol_table->mask_low = 0;
-+	vol_table->phase_delay = 0;
-+	vol_table->count = dep_table->count;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		vol_table->entries[i].value = dep_table->entries[i].vddci;
-+		vol_table->entries[i].smio_low = 0;
-+	}
-+
-+	result = phm_trim_voltage_table(vol_table);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to trim VDDCI table.", return result);
-+
-+	return 0;
-+}
-+
-+int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table)
-+{
-+	int i = 0;
-+
-+	PP_ASSERT_WITH_CODE((0 != lookup_table->count),
-+			"Voltage Lookup Table empty.", return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE((NULL != vol_table),
-+			"vol_table empty.", return -EINVAL);
-+
-+	vol_table->mask_low = 0;
-+	vol_table->phase_delay = 0;
-+
-+	vol_table->count = lookup_table->count;
-+
-+	for (i = 0; i < vol_table->count; i++) {
-+		vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
-+		vol_table->entries[i].smio_low = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
-+				struct pp_atomctrl_voltage_table *vol_table)
-+{
-+	unsigned int i, diff;
-+
-+	if (vol_table->count <= max_vol_steps)
-+		return;
-+
-+	diff = vol_table->count - max_vol_steps;
-+
-+	for (i = 0; i < max_vol_steps; i++)
-+		vol_table->entries[i] = vol_table->entries[i + diff];
-+
-+	vol_table->count = max_vol_steps;
-+
-+	return;
-+}
-+
-+int phm_reset_single_dpm_table(void *table,
-+				uint32_t count, int max)
-+{
-+	int i;
-+
-+	struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-+
-+	PP_ASSERT_WITH_CODE(count <= max,
-+			"Fatal error, can not set up single DPM table entries to exceed max number!",
-+			   );
-+
-+	dpm_table->count = count;
-+	for (i = 0; i < max; i++)
-+		dpm_table->dpm_level[i].enabled = false;
-+
-+	return 0;
-+}
-+
-+void phm_setup_pcie_table_entry(
-+	void *table,
-+	uint32_t index, uint32_t pcie_gen,
-+	uint32_t pcie_lanes)
-+{
-+	struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-+	dpm_table->dpm_level[index].value = pcie_gen;
-+	dpm_table->dpm_level[index].param1 = pcie_lanes;
-+	dpm_table->dpm_level[index].enabled = 1;
-+}
-+
-+int32_t phm_get_dpm_level_enable_mask_value(void *table)
-+{
-+	int32_t i;
-+	int32_t mask = 0;
-+	struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-+
-+	for (i = dpm_table->count; i > 0; i--) {
-+		mask = mask << 1;
-+		if (dpm_table->dpm_level[i - 1].enabled)
-+			mask |= 0x1;
-+		else
-+			mask &= 0xFFFFFFFE;
-+	}
-+
-+	return mask;
-+}
-+
-+uint8_t phm_get_voltage_index(
-+		struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
-+{
-+	uint8_t count = (uint8_t) (lookup_table->count);
-+	uint8_t i;
-+
-+	PP_ASSERT_WITH_CODE((NULL != lookup_table),
-+			"Lookup Table empty.", return 0);
-+	PP_ASSERT_WITH_CODE((0 != count),
-+			"Lookup Table empty.", return 0);
-+
-+	for (i = 0; i < lookup_table->count; i++) {
-+		/* find first voltage equal or bigger than requested */
-+		if (lookup_table->entries[i].us_vdd >= voltage)
-+			return i;
-+	}
-+	/* voltage is bigger than max voltage in the table */
-+	return i - 1;
-+}
-+
-+uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
-+{
-+	uint32_t  i;
-+
-+	for (i = 0; i < vddci_table->count; i++) {
-+		if (vddci_table->entries[i].value >= vddci)
-+			return vddci_table->entries[i].value;
-+	}
-+
-+	PP_ASSERT_WITH_CODE(false,
-+			"VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
-+			return vddci_table->entries[i].value);
-+}
-+
-+int phm_find_boot_level(void *table,
-+		uint32_t value, uint32_t *boot_level)
-+{
-+	int result = -EINVAL;
-+	uint32_t i;
-+	struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
-+
-+	for (i = 0; i < dpm_table->count; i++) {
-+		if (value == dpm_table->dpm_level[i].value) {
-+			*boot_level = i;
-+			result = 0;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
-+	phm_ppt_v1_voltage_lookup_table *lookup_table,
-+	uint16_t virtual_voltage_id, int32_t *sclk)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
-+	for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
-+		voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
-+		if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
-+			break;
-+	}
-+
-+	PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
-+			"Can't find requested voltage id in vdd_dep_on_sclk table!",
-+			return -EINVAL;
-+			);
-+
-+	*sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initialize Dynamic State Adjustment Rule Settings
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ */
-+int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t table_size;
-+	struct phm_clock_voltage_dependency_table *table_clk_vlt;
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	/* initialize vddc_dep_on_dal_pwrl table */
-+	table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
-+	table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
-+
-+	if (NULL == table_clk_vlt) {
-+		printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
-+		return -ENOMEM;
-+	} else {
-+		table_clk_vlt->count = 4;
-+		table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
-+		table_clk_vlt->entries[0].v = 0;
-+		table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
-+		table_clk_vlt->entries[1].v = 720;
-+		table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
-+		table_clk_vlt->entries[2].v = 810;
-+		table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
-+		table_clk_vlt->entries[3].v = 900;
-+		pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
-+		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-+	}
-+
-+	return 0;
-+}
-+
-+int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
-+{
-+	if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
-+		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-+		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-+	}
-+
-+	if (NULL != hwmgr->backend) {
-+		kfree(hwmgr->backend);
-+		hwmgr->backend = NULL;
-+	}
-+
-+	return 0;
-+}
-+
-+uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
-+{
-+	uint32_t level = 0;
-+
-+	while (0 == (mask & (1 << level)))
-+		level++;
-+
-+	return level;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 4ef06ec..a9fb42a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -110,14 +110,6 @@ enum DPM_EVENT_SRC {
- };
- typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
- 
--enum DISPLAY_GAP {
--	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
--	DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
--	DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
--	DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
--};
--typedef enum DISPLAY_GAP DISPLAY_GAP;
--
- const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
- 
- struct tonga_power_state *cast_phw_tonga_power_state(
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 238d162..ec871eb 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -29,6 +29,8 @@
- #include "hardwaremanager.h"
- #include "pp_power_source.h"
- #include "hwmgr_ppt.h"
-+#include "ppatomctrl.h"
-+#include "hwmgr_ppt.h"
- 
- struct pp_instance;
- struct pp_hwmgr;
-@@ -36,6 +38,28 @@ struct pp_hw_power_state;
- struct pp_power_state;
- struct PP_VCEState;
- struct phm_fan_speed_info;
-+struct pp_atomctrl_voltage_table;
-+
-+
-+enum DISPLAY_GAP {
-+	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
-+	DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
-+	DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
-+	DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
-+};
-+typedef enum DISPLAY_GAP DISPLAY_GAP;
-+
-+
-+struct vi_dpm_level {
-+	bool enabled;
-+	uint32_t value;
-+	uint32_t param1;
-+};
-+
-+struct vi_dpm_table {
-+	uint32_t count;
-+	struct vi_dpm_level dpm_level[1];
-+};
- 
- enum PP_Result {
- 	PP_Result_TableImmediateExit = 0x13,
-@@ -628,9 +652,27 @@ extern void phm_wait_for_indirect_register_unequal(
- 				uint32_t value,
- 				uint32_t mask);
- 
--bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
--bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
--bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
-+extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
-+extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
-+extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
-+
-+extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
-+extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
-+extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
-+extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
-+extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
-+extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
-+extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
-+extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
-+extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
-+extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
-+extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
-+extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
-+								uint16_t virtual_voltage_id, int32_t *sclk);
-+extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
-+extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
-+extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
-+
- 
- #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0123-drm-amdgpu-powerplay-enable-sysfs-and-debugfs-interf.patch b/common/recipes-kernel/linux/files/0123-drm-amdgpu-powerplay-enable-sysfs-and-debugfs-interf.patch
deleted file mode 100644
index ddec541b..00000000
--- a/common/recipes-kernel/linux/files/0123-drm-amdgpu-powerplay-enable-sysfs-and-debugfs-interf.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 186655ff574d3c179471619315bf10dcc0604e02 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 8 Dec 2015 17:28:28 -0500
-Subject: [PATCH 0123/1110] drm/amdgpu/powerplay: enable sysfs and debugfs
- interfaces late
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-To avoid users accessing them before the module has finished
-initializing them and make sure they are only created if
-dpm has properly initialized.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index b8b4a47..ddb90eb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -131,6 +131,10 @@ static int amdgpu_pp_late_init(void *handle)
- 		ret = adev->powerplay.ip_funcs->late_init(
- 					adev->powerplay.pp_handle);
- 
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (adev->pp_enabled)
-+		amdgpu_pm_sysfs_init(adev);
-+#endif
- 	return ret;
- }
- 
-@@ -145,7 +149,6 @@ static int amdgpu_pp_sw_init(void *handle)
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	if (adev->pp_enabled) {
--		amdgpu_pm_sysfs_init(adev);
- 		if (amdgpu_dpm == 0)
- 			adev->pm.dpm_enabled = false;
- 		else
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0124-drm-amd-powerplay-display-gpu-load-when-print-perfor.patch b/common/recipes-kernel/linux/files/0124-drm-amd-powerplay-display-gpu-load-when-print-perfor.patch
deleted file mode 100644
index d619618f..00000000
--- a/common/recipes-kernel/linux/files/0124-drm-amd-powerplay-display-gpu-load-when-print-perfor.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 5c0f0fb00e7145d4b720cf7a68c902137254e4e0 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 8 Dec 2015 14:31:13 +0800
-Subject: [PATCH 0124/1110] drm/amd/powerplay: display gpu load when print
- performance for tonga.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index a9fb42a..49f8af5 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -5148,7 +5148,9 @@ static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
- static void
- tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- {
--	uint32_t sclk, mclk;
-+	uint32_t sclk, mclk, active_percent;
-+	uint32_t offset;
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 
- 	smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
- 
-@@ -5158,6 +5160,15 @@ tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 
- 	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n", mclk/100, sclk/100);
-+
-+
-+	offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
-+	active_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
-+	active_percent += 80;
-+	active_percent >>= 8;
-+
-+	seq_printf(m, "\n [GPU load]: %u%%\n\n", active_percent > 100 ? 100 : active_percent);
-+
- }
- 
- static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0125-amd-powerplay-Implement-get-dal-power-level.patch b/common/recipes-kernel/linux/files/0125-amd-powerplay-Implement-get-dal-power-level.patch
deleted file mode 100644
index b9544ccf..00000000
--- a/common/recipes-kernel/linux/files/0125-amd-powerplay-Implement-get-dal-power-level.patch
+++ /dev/null
@@ -1,227 +0,0 @@
-From 6b321cb0239569a83db377a9abe9f4e7307c2693 Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Mon, 30 Nov 2015 16:39:53 -0500
-Subject: [PATCH 0125/1110] amd\powerplay Implement get dal power level
-
-Implement get dal power level and simple clock info
-
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c      | 13 ++++++++++
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 27 +++++++++++++++++++--
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  9 +++++++
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |  9 +++++++
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    | 28 +++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          | 18 ++------------
- 6 files changed, 85 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 215757e..0b9876d 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -619,3 +619,16 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input)
- 	phm_store_dal_configuration_data(hwmgr, display_config);
- 	return 0;
- }
-+
-+int amd_powerplay_get_display_power_level(void *handle,  void *output)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL || output == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	return phm_get_dal_power_level(hwmgr,
-+			(struct pp_dal_clock_info *)output);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 13b5bef..a745acf 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1544,7 +1544,7 @@ static void cz_hw_print_display_cfg(
- 			display_cfg->cpu_pstate_separation_time);
- }
- 
--int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
-+ static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 	uint32_t data = 0;
-@@ -1576,7 +1576,7 @@ int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- 	return 0;
- }
- 
--int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
-+ static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
- 			bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-@@ -1596,6 +1596,28 @@ int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
- 	return 0;
- }
- 
-+ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
-+		struct pp_dal_clock_info*info)
-+{
-+	uint32_t i;
-+	const struct phm_clock_voltage_dependency_table * table =
-+			hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
-+	const struct phm_clock_and_voltage_limits* limits =
-+			&hwmgr->dyn_state.max_clock_voltage_on_ac;
-+
-+	info->engine_max_clock = limits->sclk;
-+	info->memory_max_clock = limits->mclk;
-+
-+	for (i = table->count - 1; i > 0; i--) {
-+
-+		if (limits->vddc >= table->entries[i].v) {
-+			info->level = table->entries[i].clk;
-+			return 0;
-+		}
-+	}
-+	return -EINVAL;
-+}
-+
- static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.backend_init = cz_hwmgr_backend_init,
- 	.backend_fini = cz_hwmgr_backend_fini,
-@@ -1614,6 +1636,7 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.print_current_perforce_level = cz_print_current_perforce_level,
- 	.set_cpu_power_state = cz_set_cpu_power_state,
- 	.store_cc6_data = cz_store_cc6_data,
-+	.get_dal_power_level= cz_get_dal_power_level,
- };
- 
- int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 31b0dc3..d24a419 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -261,6 +261,15 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 
- }
- 
-+int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-+		struct pp_dal_clock_info*info)
-+{
-+	if (hwmgr == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr,info);
-+}
-+
- int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- {
- 	if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index efa23c1..2ec8c22 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -138,6 +138,12 @@ struct amd_pp_display_configuration {
- 	uint32_t cpu_pstate_separation_time;
- };
- 
-+struct amd_pp_dal_clock_info {
-+	uint32_t	engine_max_clock;
-+	uint32_t	memory_max_clock;
-+	uint32_t	level;
-+};
-+
- enum {
- 	PP_GROUP_UNKNOWN = 0,
- 	PP_GROUP_GFX = 1,
-@@ -212,4 +218,7 @@ int amd_powerplay_fini(void *handle);
- 
- int amd_powerplay_display_configuration_change(void *handle, const void *input);
- 
-+int amd_powerplay_get_display_power_level(void *handle,  void *output);
-+
-+
- #endif /* _AMD_POWERPLAY_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 820622d..a3b93cd 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -323,6 +323,29 @@ struct phm_clocks {
- 	uint32_t clock[MAX_NUM_CLOCKS];
- };
- 
-+enum PP_DAL_POWERLEVEL {
-+	PP_DAL_POWERLEVEL_INVALID = 0,
-+	PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_PERFORMANCE,
-+
-+	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
-+	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
-+	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
-+	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
-+	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-+};
-+
-+struct pp_dal_clock_info {
-+	uint32_t		engine_max_clock;/*dal validation clock on AC*/
-+	uint32_t		memory_max_clock;/*dal validation clock on AC*/
-+	enum PP_DAL_POWERLEVEL	level;	/*number of levels for the given clocks*/
-+};
-+
- extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
- extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
- extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
-@@ -354,7 +377,10 @@ extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- 				 bool *equal);
- 
- extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
--		    const struct amd_pp_display_configuration *display_config);
-+		const struct amd_pp_display_configuration *display_config);
-+
-+extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-+		struct pp_dal_clock_info*info);
- 
- extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index ec871eb..c9fcc0c 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -85,22 +85,6 @@ enum PHM_BackEnd_Magic {
- 	PHM_Cz_Magic          = 0x67DCBA25
- };
- 
--enum PP_DAL_POWERLEVEL {
--	PP_DAL_POWERLEVEL_INVALID = 0,
--	PP_DAL_POWERLEVEL_ULTRALOW,
--	PP_DAL_POWERLEVEL_LOW,
--	PP_DAL_POWERLEVEL_NOMINAL,
--	PP_DAL_POWERLEVEL_PERFORMANCE,
--
--	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
--	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
--	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
--	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
--	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
--	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
--	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
--	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
--};
- 
- #define PHM_PCIE_POWERGATING_TARGET_GFX            0
- #define PHM_PCIE_POWERGATING_TARGET_DDI            1
-@@ -340,6 +324,8 @@ struct pp_hwmgr_func {
- 	int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
- 				bool cc6_disable, bool pstate_disable,
- 				bool pstate_switch_disable);
-+	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
-+			struct pp_dal_clock_info*info);
- };
- 
- struct pp_table_func {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0126-amd-powerplay-Fix-get-dal-power-level.patch b/common/recipes-kernel/linux/files/0126-amd-powerplay-Fix-get-dal-power-level.patch
deleted file mode 100644
index 758dc79a..00000000
--- a/common/recipes-kernel/linux/files/0126-amd-powerplay-Fix-get-dal-power-level.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From 72ddab517936e77fb0428a8f11f6a79f58cec0af Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Thu, 3 Dec 2015 10:27:57 -0500
-Subject: [PATCH 0126/1110] amd/powerplay: Fix get dal power level
-
-Simplify data struct for get dal power level
-
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c         | 6 +++---
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c        | 2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 7 ++++---
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h     | 3 ++-
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 7 +------
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h             | 2 +-
- 6 files changed, 12 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 0b9876d..db0370b 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -620,7 +620,8 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input)
- 	return 0;
- }
- 
--int amd_powerplay_get_display_power_level(void *handle,  void *output)
-+int amd_powerplay_get_display_power_level(void *handle,
-+		struct amd_pp_dal_clock_info *output)
- {
- 	struct pp_hwmgr  *hwmgr;
- 
-@@ -629,6 +630,5 @@ int amd_powerplay_get_display_power_level(void *handle,  void *output)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	return phm_get_dal_power_level(hwmgr,
--			(struct pp_dal_clock_info *)output);
-+	return phm_get_dal_power_level(hwmgr, output);
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index a745acf..bd30b56 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1597,7 +1597,7 @@ static void cz_hw_print_display_cfg(
- }
- 
-  static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct pp_dal_clock_info*info)
-+		struct amd_pp_dal_clock_info*info)
- {
- 	uint32_t i;
- 	const struct phm_clock_voltage_dependency_table * table =
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index d24a419..881feb8 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -262,12 +262,13 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- }
- 
- int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct pp_dal_clock_info*info)
-+		struct amd_pp_dal_clock_info*info)
- {
--	if (hwmgr == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
-+	if (info == NULL || hwmgr == NULL ||
-+			hwmgr->hwmgr_func->get_dal_power_level == NULL)
- 		return -EINVAL;
- 
--	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr,info);
-+	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
- }
- 
- int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 2ec8c22..3d0058c 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -218,7 +218,8 @@ int amd_powerplay_fini(void *handle);
- 
- int amd_powerplay_display_configuration_change(void *handle, const void *input);
- 
--int amd_powerplay_get_display_power_level(void *handle,  void *output);
-+int amd_powerplay_get_display_power_level(void *handle,
-+		struct amd_pp_dal_clock_info *output);
- 
- 
- #endif /* _AMD_POWERPLAY_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index a3b93cd..a503306 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -340,11 +340,6 @@ enum PP_DAL_POWERLEVEL {
- 	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
- };
- 
--struct pp_dal_clock_info {
--	uint32_t		engine_max_clock;/*dal validation clock on AC*/
--	uint32_t		memory_max_clock;/*dal validation clock on AC*/
--	enum PP_DAL_POWERLEVEL	level;	/*number of levels for the given clocks*/
--};
- 
- extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
- extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
-@@ -380,7 +375,7 @@ extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 		const struct amd_pp_display_configuration *display_config);
- 
- extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct pp_dal_clock_info*info);
-+		struct amd_pp_dal_clock_info*info);
- 
- extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index c9fcc0c..0c58969 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -325,7 +325,7 @@ struct pp_hwmgr_func {
- 				bool cc6_disable, bool pstate_disable,
- 				bool pstate_switch_disable);
- 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
--			struct pp_dal_clock_info*info);
-+			struct amd_pp_dal_clock_info*info);
- };
- 
- struct pp_table_func {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0127-amd-powerplay-Add-structures-required-to-report-conf.patch b/common/recipes-kernel/linux/files/0127-amd-powerplay-Add-structures-required-to-report-conf.patch
deleted file mode 100644
index 5301fbd9..00000000
--- a/common/recipes-kernel/linux/files/0127-amd-powerplay-Add-structures-required-to-report-conf.patch
+++ /dev/null
@@ -1,337 +0,0 @@
-From 3e36e312d28058cf9647d7429027da0068a24e7b Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 1 Dec 2015 13:23:07 -0500
-Subject: [PATCH 0127/1110] amd/powerplay: Add structures required to report
- configuration change
-
-Add required structures for amd_powerplay_display_configuration_change
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 76 +++++++++++++---------
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h     | 11 +++-
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 17 +++--
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 73 +++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  1 +
- 5 files changed, 139 insertions(+), 39 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index bd30b56..4641095 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -239,10 +239,10 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_DynamicUVDState);
- 
--	cz_hwmgr->display_cfg.cpu_cc6_disable = false;
--	cz_hwmgr->display_cfg.cpu_pstate_disable = false;
--	cz_hwmgr->display_cfg.nb_pstate_switch_disable = false;
--	cz_hwmgr->display_cfg.cpu_pstate_separation_time = 0;
-+	cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
-+	cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
-+	cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
-+	cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
- 
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 				   PHM_PlatformCaps_DisableVoltageIsland);
-@@ -784,8 +784,11 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
- 					void *storage, int result)
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				    PHM_PlatformCaps_SclkDeepSleep)) {
--		/* TO DO get from dal PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
-+				PHM_PlatformCaps_SclkDeepSleep)) {
-+		uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
-+		if (clks == 0)
-+			clks = CZ_MIN_DEEP_SLEEP_SCLK;
-+
- 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					  PPSMC_MSG_SetMinDeepSleepSclk,
- 						CZ_MIN_DEEP_SLEEP_SCLK);
-@@ -873,8 +876,8 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
- 	const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
- 
- 	if (hw_data->sys_info.nb_dpm_enable) {
--		disable_switch = hw_data->display_cfg.nb_pstate_switch_disable ? true : false;
--		enable_low_mem_state = hw_data->display_cfg.nb_pstate_switch_disable ? false : true;
-+		disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
-+		enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
- 
- 		if (pnew_state->action == FORCE_HIGH)
- 			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
-@@ -1530,18 +1533,18 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- }
- 
- static void cz_hw_print_display_cfg(
--	const struct amd_pp_display_configuration *display_cfg)
-+	const struct cc6_settings *cc6_settings)
- {
- 	PP_DBG_LOG("New Display Configuration:\n");
- 
- 	PP_DBG_LOG("   cpu_cc6_disable: %d\n",
--			display_cfg->cpu_cc6_disable);
-+			cc6_settings->cpu_cc6_disable);
- 	PP_DBG_LOG("   cpu_pstate_disable: %d\n",
--			display_cfg->cpu_pstate_disable);
-+			cc6_settings->cpu_pstate_disable);
- 	PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
--			display_cfg->nb_pstate_switch_disable);
-+			cc6_settings->nb_pstate_switch_disable);
- 	PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
--			display_cfg->cpu_pstate_separation_time);
-+			cc6_settings->cpu_pstate_separation_time);
- }
- 
-  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
-@@ -1549,18 +1552,20 @@ static void cz_hw_print_display_cfg(
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 	uint32_t data = 0;
- 
--	if (hw_data->cc6_setting_changed == true) {
-+	if (hw_data->cc6_settings.cc6_setting_changed == true) {
-+
-+		hw_data->cc6_settings.cc6_setting_changed = false;
- 
--		cz_hw_print_display_cfg(&hw_data->display_cfg);
-+		cz_hw_print_display_cfg(&hw_data->cc6_settings);
- 
--		data |= (hw_data->display_cfg.cpu_pstate_separation_time
-+		data |= (hw_data->cc6_settings.cpu_pstate_separation_time
- 			& PWRMGT_SEPARATION_TIME_MASK)
- 			<< PWRMGT_SEPARATION_TIME_SHIFT;
- 
--		data|= (hw_data->display_cfg.cpu_cc6_disable ? 0x1 : 0x0)
-+		data|= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
- 			<< PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
- 
--		data|= (hw_data->display_cfg.cpu_pstate_disable ? 0x1 : 0x0)
-+		data|= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
- 			<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
- 
- 		PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
-@@ -1569,30 +1574,39 @@ static void cz_hw_print_display_cfg(
- 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 						PPSMC_MSG_SetDisplaySizePowerParams,
- 						data);
--
--		hw_data->cc6_setting_changed = false;
- 	}
- 
- 	return 0;
- }
- 
-+
-  static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
- 			bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
--{
-+ {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 
--	if (separation_time != hw_data->display_cfg.cpu_pstate_separation_time
--	|| cc6_disable != hw_data->display_cfg.cpu_cc6_disable
--	|| pstate_disable != hw_data->display_cfg.cpu_pstate_disable
--	|| pstate_switch_disable != hw_data->display_cfg.nb_pstate_switch_disable) {
--
--		hw_data->display_cfg.cpu_pstate_separation_time = separation_time;
--		hw_data->display_cfg.cpu_cc6_disable = cc6_disable;
--		hw_data->display_cfg.cpu_pstate_disable = pstate_disable;
--		hw_data->display_cfg.nb_pstate_switch_disable = pstate_switch_disable;
--		hw_data->cc6_setting_changed = true;
-+	if (separation_time !=
-+		hw_data->cc6_settings.cpu_pstate_separation_time
-+		|| cc6_disable !=
-+		hw_data->cc6_settings.cpu_cc6_disable
-+		|| pstate_disable !=
-+		hw_data->cc6_settings.cpu_pstate_disable
-+		|| pstate_switch_disable !=
-+		hw_data->cc6_settings.nb_pstate_switch_disable) {
-+
-+		hw_data->cc6_settings.cc6_setting_changed = true;
-+
-+		hw_data->cc6_settings.cpu_pstate_separation_time =
-+			separation_time;
-+		hw_data->cc6_settings.cpu_cc6_disable =
-+			cc6_disable;
-+		hw_data->cc6_settings.cpu_pstate_disable =
-+			pstate_disable;
-+		hw_data->cc6_settings.nb_pstate_switch_disable =
-+			pstate_switch_disable;
- 
- 	}
-+
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-index 54a6c34..c477f1c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h
-@@ -176,6 +176,14 @@ struct cz_power_state {
- #define SMU_EnabledFeatureScoreboard_UvdDpmOn   0x00800000 /* bit 23 */
- #define SMU_EnabledFeatureScoreboard_VceDpmOn   0x01000000 /* bit 24 */
- 
-+struct cc6_settings {
-+	bool cc6_setting_changed;
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+};
-+
- struct cz_hwmgr {
- 	uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
- 	uint32_t dpm_interval;
-@@ -238,7 +246,7 @@ struct cz_hwmgr {
- 	uint32_t highest_valid;
- 	uint32_t high_voltage_threshold;
- 	uint32_t is_nb_dpm_enabled;
--	struct amd_pp_display_configuration display_cfg; /* set by DAL */
-+	struct cc6_settings cc6_settings;
- 	uint32_t is_voltage_island_enabled;
- 
- 	bool pgacpinit;
-@@ -304,7 +312,6 @@ struct cz_hwmgr {
- 
- 	uint32_t max_sclk_level;
- 	uint32_t num_of_clk_entries;
--	bool cc6_setting_changed;
- };
- 
- struct pp_hwmgr;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 881feb8..df8937b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -249,16 +249,21 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 		    const struct amd_pp_display_configuration *display_config)
- {
--	if (hwmgr == NULL || hwmgr->hwmgr_func->store_cc6_data == NULL)
-+
-+	if (hwmgr == NULL)
- 		return -EINVAL;
- 
-+	hwmgr->display_config = *display_config;
- 	/* to do pass other display configuration in furture */
--	return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
--					display_config->cpu_pstate_separation_time,
--					display_config->cpu_cc6_disable,
--					display_config->cpu_pstate_disable,
--					display_config->nb_pstate_switch_disable);
- 
-+	if (hwmgr->hwmgr_func->store_cc6_data)
-+		hwmgr->hwmgr_func->store_cc6_data(hwmgr,
-+				display_config->cpu_pstate_separation_time,
-+				display_config->cpu_cc6_disable,
-+				display_config->cpu_pstate_disable,
-+				display_config->nb_pstate_switch_disable);
-+
-+	return 0;
- }
- 
- int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 3d0058c..d9b8d3f 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -130,12 +130,85 @@ struct amd_pp_init {
- 	uint32_t chip_id;
- 	uint32_t rev_id;
- };
-+enum amd_pp_display_config_type{
-+	AMD_PP_DisplayConfigType_None = 0,
-+	AMD_PP_DisplayConfigType_DP54 ,
-+	AMD_PP_DisplayConfigType_DP432 ,
-+	AMD_PP_DisplayConfigType_DP324 ,
-+	AMD_PP_DisplayConfigType_DP27,
-+	AMD_PP_DisplayConfigType_DP243,
-+	AMD_PP_DisplayConfigType_DP216,
-+	AMD_PP_DisplayConfigType_DP162,
-+	AMD_PP_DisplayConfigType_HDMI6G ,
-+	AMD_PP_DisplayConfigType_HDMI297 ,
-+	AMD_PP_DisplayConfigType_HDMI162,
-+	AMD_PP_DisplayConfigType_LVDS,
-+	AMD_PP_DisplayConfigType_DVI,
-+	AMD_PP_DisplayConfigType_WIRELESS,
-+	AMD_PP_DisplayConfigType_VGA
-+};
-+
-+struct single_display_configuration
-+{
-+	uint32_t controller_index;
-+	uint32_t controller_id;
-+	uint32_t signal_type;
-+	uint32_t display_state;
-+	/* phy id for the primary internal transmitter */
-+	uint8_t primary_transmitter_phyi_d;
-+	/* bitmap with the active lanes */
-+	uint8_t primary_transmitter_active_lanemap;
-+	/* phy id for the secondary internal transmitter (for dual-link dvi) */
-+	uint8_t secondary_transmitter_phy_id;
-+	/* bitmap with the active lanes */
-+	uint8_t secondary_transmitter_active_lanemap;
-+	/* misc phy settings for SMU. */
-+	uint32_t config_flags;
-+	uint32_t display_type;
-+	uint32_t view_resolution_cx;
-+	uint32_t view_resolution_cy;
-+	enum amd_pp_display_config_type displayconfigtype;
-+	uint32_t vertical_refresh; /* for active display */
-+};
-+
-+#define MAX_NUM_DISPLAY 32
- 
- struct amd_pp_display_configuration {
- 	bool nb_pstate_switch_disable;/* controls NB PState switch */
- 	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
- 	bool cpu_pstate_disable;
- 	uint32_t cpu_pstate_separation_time;
-+
-+	uint32_t num_display;  /* total number of display*/
-+	uint32_t num_path_including_non_display;
-+	uint32_t crossfire_display_index;
-+	uint32_t min_mem_set_clock;
-+	uint32_t min_core_set_clock;
-+	/* unit 10KHz x bit*/
-+	uint32_t min_bus_bandwidth;
-+	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
-+	uint32_t min_core_set_clock_in_sr;
-+
-+	struct single_display_configuration displays[MAX_NUM_DISPLAY];
-+
-+	uint32_t vrefresh; /* for active display*/
-+
-+	uint32_t min_vblank_time; /* for active display*/
-+	bool multi_monitor_in_sync;
-+	/* Controller Index of primary display - used in MCLK SMC switching hang
-+	 * SW Workaround*/
-+	uint32_t crtc_index;
-+	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+	uint32_t line_time_in_us;
-+	bool invalid_vblank_time;
-+
-+	uint32_t display_clk;
-+	/*
-+	 * for given display configuration if multimonitormnsync == false then
-+	 * Memory clock DPMS with this latency or below is allowed, DPMS with
-+	 * higher latency not allowed.
-+	 */
-+	uint32_t dce_tolerable_mclk_in_active_latency;
- };
- 
- struct amd_pp_dal_clock_info {
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 0c58969..eb0f1b2 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -601,6 +601,7 @@ struct pp_hwmgr {
- 	struct pp_power_state    *request_ps;
- 	struct pp_power_state    *boot_ps;
- 	struct pp_power_state    *uvd_ps;
-+	struct amd_pp_display_configuration display_config;
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0128-drm-powerplay-add-debugging-output-to-tonga_processp.patch b/common/recipes-kernel/linux/files/0128-drm-powerplay-add-debugging-output-to-tonga_processp.patch
deleted file mode 100644
index a8fbbdf6..00000000
--- a/common/recipes-kernel/linux/files/0128-drm-powerplay-add-debugging-output-to-tonga_processp.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 8ba17c733ffb662a95b9fe0594e79d2cca827507 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 11 Dec 2015 12:12:32 -0500
-Subject: [PATCH 0128/1110] drm/powerplay: add debugging output to
- tonga_processpptables.c
-
-To help track down init errors.
-
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../amd/powerplay/hwmgr/tonga_processpptables.c    | 39 ++++++++++++++--------
- 1 file changed, 26 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index ddb03a0..2f09bb3 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -942,8 +942,8 @@ int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr)
- 
- 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
- 
--	if (NULL == hwmgr->pptable)
--		return -1;
-+	PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
-+			    "Failed to allocate hwmgr->pptable!", return -1);
- 
- 	memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
- 
-@@ -954,21 +954,34 @@ int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr)
- 
- 	result = check_powerplay_tables(hwmgr, powerplay_table);
- 
--	if (0 == result)
--		result = set_platform_caps(hwmgr,
--			le32_to_cpu(powerplay_table->ulPlatformCaps));
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "check_powerplay_tables failed", return result);
-+
-+	result = set_platform_caps(hwmgr,
-+				   le32_to_cpu(powerplay_table->ulPlatformCaps));
-+
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "set_platform_caps failed", return result);
-+
-+	result = init_thermal_controller(hwmgr, powerplay_table);
-+
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_thermal_controller failed", return result);
-+
-+	result = init_over_drive_limits(hwmgr, powerplay_table);
-+
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_over_drive_limits failed", return result);
- 
--	if (0 == result)
--		result = init_thermal_controller(hwmgr, powerplay_table);
-+	result = init_clock_voltage_dependency(hwmgr, powerplay_table);
- 
--	if (0 == result)
--		result = init_over_drive_limits(hwmgr, powerplay_table);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_clock_voltage_dependency failed", return result);
- 
--	if (0 == result)
--		result = init_clock_voltage_dependency(hwmgr, powerplay_table);
-+	result = init_dpm_2_parameters(hwmgr, powerplay_table);
- 
--	if (0 == result)
--		result = init_dpm_2_parameters(hwmgr, powerplay_table);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_dpm_2_parameters failed", return result);
- 
- 	return result;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0129-drm-powerplay-add-debugging-output-to-processpptable.patch b/common/recipes-kernel/linux/files/0129-drm-powerplay-add-debugging-output-to-processpptable.patch
deleted file mode 100644
index 60cedcfd..00000000
--- a/common/recipes-kernel/linux/files/0129-drm-powerplay-add-debugging-output-to-processpptable.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From bb4da830a4501d0a4af27db7fa11ed3d763d19bc Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 11 Dec 2015 12:32:55 -0500
-Subject: [PATCH 0129/1110] drm/powerplay: add debugging output to
- processpptables.c
-
-To help track down init errors.
-
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  | 42 +++++++++++++++-------
- 1 file changed, 29 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-index fdda6b4..1d385f4 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-@@ -27,6 +27,7 @@
- #include "processpptables.h"
- #include <atom-types.h>
- #include <atombios.h>
-+#include "pp_debug.h"
- #include "pptable.h"
- #include "power_state.h"
- #include "hwmgr.h"
-@@ -1539,25 +1540,40 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
- 
- 	result = init_powerplay_tables(hwmgr, powerplay_table);
- 
--	if (0 == result)
--		result = set_platform_caps(hwmgr,
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_powerplay_tables failed", return result);
-+
-+	result = set_platform_caps(hwmgr,
- 				le32_to_cpu(powerplay_table->ulPlatformCaps));
- 
--	if (0 == result)
--		result = init_thermal_controller(hwmgr, powerplay_table);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "set_platform_caps failed", return result);
- 
--	if (0 == result)
--		result = init_overdrive_limits(hwmgr, powerplay_table);
-+	result = init_thermal_controller(hwmgr, powerplay_table);
- 
--	if (0 == result)
--		result = init_clock_voltage_dependency(hwmgr,
--						powerplay_table);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_thermal_controller failed", return result);
-+
-+	result = init_overdrive_limits(hwmgr, powerplay_table);
-+
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_overdrive_limits failed", return result);
-+
-+	result = init_clock_voltage_dependency(hwmgr,
-+					       powerplay_table);
-+
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_clock_voltage_dependency failed", return result);
-+
-+	result = init_dpm2_parameters(hwmgr, powerplay_table);
-+
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_dpm2_parameters failed", return result);
- 
--	if (0 == result)
--		result = init_dpm2_parameters(hwmgr, powerplay_table);
-+	result = init_phase_shedding_table(hwmgr, powerplay_table);
- 
--	if (0 == result)
--		result = init_phase_shedding_table(hwmgr, powerplay_table);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			    "init_phase_shedding_table failed", return result);
- 
- 	return result;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0130-drm-powerplay-hwmgr-log-errors-in-tonga_hwmgr_backen.patch b/common/recipes-kernel/linux/files/0130-drm-powerplay-hwmgr-log-errors-in-tonga_hwmgr_backen.patch
deleted file mode 100644
index 2fd2ecd3..00000000
--- a/common/recipes-kernel/linux/files/0130-drm-powerplay-hwmgr-log-errors-in-tonga_hwmgr_backen.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 80a3b333dba48c9ce466d4a641e802a91d129efc Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 11 Dec 2015 12:39:01 -0500
-Subject: [PATCH 0130/1110] drm/powerplay/hwmgr: log errors in
- tonga_hwmgr_backend_init
-
-Helpful in debugging init issues.
-
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 49f8af5..3cb5d04 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4557,6 +4557,8 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	/* Initalize Dynamic State Adjustment Rule Settings*/
- 	result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
-+	if (result)
-+		printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
- 	data->uvd_enabled = 0;
- 
- 	table = &(data->smc_state_table);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0131-drm-amd-powerplay-Don-t-return-an-error-if-fan-table.patch b/common/recipes-kernel/linux/files/0131-drm-amd-powerplay-Don-t-return-an-error-if-fan-table.patch
deleted file mode 100644
index d193f0bf..00000000
--- a/common/recipes-kernel/linux/files/0131-drm-amd-powerplay-Don-t-return-an-error-if-fan-table.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 7296a5dd0966310f0f2dbb06b09f353d4861187e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 14 Dec 2015 10:46:52 -0500
-Subject: [PATCH 0131/1110] drm/amd/powerplay: Don't return an error if fan
- table is missing
-
-It's a valid configuration on some laptops.
-
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index 2f09bb3..ae216fe 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -797,7 +797,7 @@ static int init_thermal_controller(
- 		  );
- 
- 	if (0 == powerplay_table->usFanTableOffset)
--		return -1;
-+		return 0;
- 
- 	fan_table = (const PPTable_Generic_SubTable_Header *)
- 		(((unsigned long)powerplay_table) +
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0132-drm-amdgpu-powerplay-Program-a-calculated-value-as-D.patch b/common/recipes-kernel/linux/files/0132-drm-amdgpu-powerplay-Program-a-calculated-value-as-D.patch
deleted file mode 100644
index 731d6956..00000000
--- a/common/recipes-kernel/linux/files/0132-drm-amdgpu-powerplay-Program-a-calculated-value-as-D.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 3805fc85c45ff9620df53013182205d30d7e12e6 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Fri, 11 Dec 2015 12:06:25 -0500
-Subject: [PATCH 0132/1110] drm/amdgpu/powerplay: Program a calculated value as
- Deep Sleep clock.
-
-This replaces programming of a hardcoded value.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 4641095..3448065 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -789,9 +789,11 @@ static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
- 		if (clks == 0)
- 			clks = CZ_MIN_DEEP_SLEEP_SCLK;
- 
-+		PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
-+
- 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					  PPSMC_MSG_SetMinDeepSleepSclk,
--						CZ_MIN_DEEP_SLEEP_SCLK);
-+				PPSMC_MSG_SetMinDeepSleepSclk,
-+				clks);
- 	}
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0133-drm-amd-powerplay-add-point-check-to-avoid-NULL-poin.patch b/common/recipes-kernel/linux/files/0133-drm-amd-powerplay-add-point-check-to-avoid-NULL-poin.patch
deleted file mode 100644
index c9a5ce9f..00000000
--- a/common/recipes-kernel/linux/files/0133-drm-amd-powerplay-add-point-check-to-avoid-NULL-poin.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From 13414ce9034c987ccafaed88a5e86229ebaac810 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 11 Dec 2015 15:21:33 +0800
-Subject: [PATCH 0133/1110] drm/amd/powerplay: add point check to avoid NULL
- point hang.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 60 +++++++++++++++++-----
- 1 file changed, 47 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index df8937b..0fddac9 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -28,6 +28,12 @@
- #include "amd_acpi.h"
- #include "amd_powerplay.h"
- 
-+#define PHM_FUNC_CHECK(hw) \
-+	do {							\
-+		if ((hw) == NULL || (hw)->hwmgr_func == NULL)	\
-+			return -EINVAL;				\
-+	} while (0)
-+
- void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
- {
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
-@@ -70,6 +76,8 @@ int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
- 
- int phm_setup_asic(struct pp_hwmgr *hwmgr)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 		PHM_PlatformCaps_TablelessHardwareInterface)) {
- 		if (NULL != hwmgr->hwmgr_func->asic_setup)
-@@ -88,6 +96,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
- {
- 	struct phm_set_power_state_input states;
- 
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	states.pcurrent_state = pcurrent_state;
- 	states.pnew_state = pnew_power_state;
- 
-@@ -104,6 +114,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
- 
- int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 		PHM_PlatformCaps_TablelessHardwareInterface)) {
- 		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
-@@ -118,6 +130,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
- 
- int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
- 		return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
- 
-@@ -128,6 +142,8 @@ int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 				   struct pp_power_state *adjusted_ps,
- 			     const struct pp_power_state *current_ps)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
- 		return hwmgr->hwmgr_func->apply_state_adjust_rules(
- 									hwmgr,
-@@ -138,6 +154,8 @@ int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 
- int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
- 		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
- 	return 0;
-@@ -145,6 +163,8 @@ int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
- 
- int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
- 		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- 	return 0;
-@@ -152,6 +172,8 @@ int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
- 
- int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (hwmgr->hwmgr_func->powergate_vce != NULL)
- 		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- 	return 0;
-@@ -159,6 +181,8 @@ int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
- 
- int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
- {
-+	PHM_FUNC_CHECK(hwmgr);
-+
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 		PHM_PlatformCaps_TablelessHardwareInterface)) {
- 		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
-@@ -171,8 +195,7 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
- 
- int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr == NULL)
--		return -EINVAL;
-+	PHM_FUNC_CHECK(hwmgr);
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				 PHM_PlatformCaps_TablelessHardwareInterface)) {
-@@ -185,8 +208,7 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
- 
- int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr == NULL)
--		return -EINVAL;
-+	PHM_FUNC_CHECK(hwmgr);
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				 PHM_PlatformCaps_TablelessHardwareInterface))
-@@ -198,7 +220,9 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
- 
- int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr == NULL || hwmgr->hwmgr_func->stop_thermal_controller == NULL)
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
- 		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
-@@ -206,7 +230,9 @@ int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
- 
- int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
- {
--	if (hwmgr == NULL || hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
- 		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
-@@ -228,7 +254,9 @@ int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRa
- 
- bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr == NULL || hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
- 		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
-@@ -240,7 +268,9 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- 				 const struct pp_hw_power_state *pstate2,
- 				 bool *equal)
- {
--	if (hwmgr == NULL || hwmgr->hwmgr_func->check_states_equal == NULL)
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->check_states_equal == NULL)
- 		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
-@@ -249,8 +279,9 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
- int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 		    const struct amd_pp_display_configuration *display_config)
- {
-+	PHM_FUNC_CHECK(hwmgr);
- 
--	if (hwmgr == NULL)
-+	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
- 		return -EINVAL;
- 
- 	hwmgr->display_config = *display_config;
-@@ -267,10 +298,11 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- }
- 
- int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct amd_pp_dal_clock_info*info)
-+		struct amd_pp_dal_clock_info *info)
- {
--	if (info == NULL || hwmgr == NULL ||
--			hwmgr->hwmgr_func->get_dal_power_level == NULL)
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
- 		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
-@@ -278,7 +310,9 @@ int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
- 
- int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- {
--	if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
- 		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0134-drm-amd-powerplay-check-whether-need-to-enable-therm.patch b/common/recipes-kernel/linux/files/0134-drm-amd-powerplay-check-whether-need-to-enable-therm.patch
deleted file mode 100644
index cbb9e3ea..00000000
--- a/common/recipes-kernel/linux/files/0134-drm-amd-powerplay-check-whether-need-to-enable-therm.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 6c152c0ae63512ee7eda1a08bdc4c640a17ba194 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 17 Dec 2015 14:20:06 +0800
-Subject: [PATCH 0134/1110] drm/amd/powerplay: check whether need to enable
- thermal control. (v2)
-
-In I+A platform(skylake), it is controlled by intel.
-
-v2: integrate Tom's fix
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index 0a03f79..f0700d0 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -418,10 +418,17 @@ restart_search:
- int pem_task_initialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
- 	struct PP_TemperatureRange range;
-+
- 	range.max = TEMP_RANGE_MAX;
- 	range.min = TEMP_RANGE_MIN;
- 
--	return phm_start_thermal_controller(eventmgr->hwmgr, &range);
-+	if (eventmgr == NULL || eventmgr->platform_descriptor == NULL)
-+		return -EINVAL;
-+
-+	if (phm_cap_enabled(eventmgr->platform_descriptor->platformCaps, PHM_PlatformCaps_ThermalController))
-+		return phm_start_thermal_controller(eventmgr->hwmgr, &range);
-+
-+	return 0;
- }
- 
- int pem_task_uninitialize_thermal_controller(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0135-drm-amd-powerplay-show-gpu-load-when-print-gpu-perfo.patch b/common/recipes-kernel/linux/files/0135-drm-amd-powerplay-show-gpu-load-when-print-gpu-perfo.patch
deleted file mode 100644
index a832bac2..00000000
--- a/common/recipes-kernel/linux/files/0135-drm-amd-powerplay-show-gpu-load-when-print-gpu-perfo.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 731293237e12e750a3425e34b721d12ffe870b89 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 17 Dec 2015 17:20:04 +0800
-Subject: [PATCH 0135/1110] drm/amd/powerplay: show gpu load when print gpu
- performance for Cz. (v2)
-
-Show GPU load in in the debugfs output.
-
-v2: integrate Tom's optimization
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 3448065..5bac36b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1494,8 +1494,9 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 	uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
- 					TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
- 
--	uint32_t sclk, vclk, dclk, ecclk, tmp;
-+	uint32_t sclk, vclk, dclk, ecclk, tmp, active_percent;
- 	uint16_t vddnb, vddgfx;
-+	int result;
- 
- 	if (sclk_index >= NUM_SCLK_LEVELS) {
- 		seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
-@@ -1532,6 +1533,16 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 			seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
- 		}
- 	}
-+
-+	result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
-+	if (0 == result) {
-+		active_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
-+		active_percent = active_percent > 100 ? 100 : active_percent;
-+	} else {
-+		active_percent = 50;
-+	}
-+
-+	seq_printf(m, "\n [GPU load]: %u %%\n\n", active_percent);
- }
- 
- static void cz_hw_print_display_cfg(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0136-amd-powerplay-don-t-enable-ucode-fan-control-if-vbio.patch b/common/recipes-kernel/linux/files/0136-amd-powerplay-don-t-enable-ucode-fan-control-if-vbio.patch
deleted file mode 100644
index 3b456461..00000000
--- a/common/recipes-kernel/linux/files/0136-amd-powerplay-don-t-enable-ucode-fan-control-if-vbio.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 8c518450c658851d39ad5b24a4d4952b39825e9a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Sat, 19 Dec 2015 18:26:55 -0500
-Subject: [PATCH 0136/1110] amd/powerplay: don't enable ucode fan control if
- vbios has no fan table
-
-Some systems have a single fan controlled by ACPI or some other
-method.
-
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-index 5da7586..2e159b0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-@@ -371,6 +371,9 @@ int tf_tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *
- 	int res;
- 	uint64_t tmp64;
- 
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
-+		return 0;
-+
- 	if (0 == data->fan_table_start) {
- 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
- 		return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0137-amd-powerplay-disable-powerplay-by-default-initially.patch b/common/recipes-kernel/linux/files/0137-amd-powerplay-disable-powerplay-by-default-initially.patch
deleted file mode 100644
index 31bc5796..00000000
--- a/common/recipes-kernel/linux/files/0137-amd-powerplay-disable-powerplay-by-default-initially.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c079a58edec7b8ef45361bd641f45612012b4035 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 21 Dec 2015 17:07:40 -0500
-Subject: [PATCH 0137/1110] amd/powerplay: disable powerplay by default
- initially
-
-Hopefully we can enable this by default once we get more
-upstream feedback on stability, etc.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index ddb90eb..5ee9a06 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -101,7 +101,7 @@ static int amdgpu_pp_early_init(void *handle)
- 	switch (adev->asic_type) {
- 		case CHIP_TONGA:
- 		case CHIP_FIJI:
--			adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
-+			adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
- 			break;
- 		default:
- 			adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0138-amd-powerplay-fix-copy-paste-typo-in-hardwaremanager.patch b/common/recipes-kernel/linux/files/0138-amd-powerplay-fix-copy-paste-typo-in-hardwaremanager.patch
deleted file mode 100644
index 206c741f..00000000
--- a/common/recipes-kernel/linux/files/0138-amd-powerplay-fix-copy-paste-typo-in-hardwaremanager.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From f38711069a960509dfe972a9179b91c1e079356d Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 21 Dec 2015 17:13:05 -0500
-Subject: [PATCH 0138/1110] amd/powerplay: fix copy paste typo in
- hardwaremanager.c
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 0fddac9..001b8bb 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -212,7 +212,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				 PHM_PlatformCaps_TablelessHardwareInterface))
--		if (NULL != hwmgr->hwmgr_func->display_config_changed)
-+		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
- 			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0139-drm-powerplay-use-div64_s64-instead-of-do_div.patch b/common/recipes-kernel/linux/files/0139-drm-powerplay-use-div64_s64-instead-of-do_div.patch
deleted file mode 100644
index e9c927c5..00000000
--- a/common/recipes-kernel/linux/files/0139-drm-powerplay-use-div64_s64-instead-of-do_div.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From d7bc091149f65703b5175e3e4cf5d3b72817a48b Mon Sep 17 00:00:00 2001
-From: Arnd Bergmann <arnd@arndb.de>
-Date: Fri, 1 Jan 2016 14:07:41 +0100
-Subject: [PATCH 0139/1110] drm: powerplay: use div64_s64 instead of do_div
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The newly added code for Fiji creates a correct compiler warning
-about invalid use of the do_div macro:
-
-In file included from powerplay/hwmgr/ppatomctrl.c:31:0:
-drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppevvmath.h: In function 'fDivide':
-drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppevvmath.h:382:89: warning: comparison of distinct pointer types lacks a cast
-     do_div(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */
-
-do_div() divides an unsigned 64-bit number by an unsigned 32-bit number.
-The code instead wants to divide two signed 64-bit numbers, which is done
-using the div64_s64 function.
-
-Reviewed-by: Thierry Reding <treding@nvidia.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Fixes: 770911a3cfbb ("drm/amd/powerplay: add/update headers for Fiji SMU and DPM")
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-index 42f2423..411cb0f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-@@ -379,7 +379,7 @@ fInt fDivide (fInt X, fInt Y)
- 
-     longlongX = longlongX << 16; /*Q(16,16) -> Q(32,32) */
- 
--    do_div(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */
-+    div64_s64(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */
- 
-     fQuotient.full = (int)longlongX;
-     return fQuotient;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0140-drm-amd-powerplay-fix-a-reversed-condition.patch b/common/recipes-kernel/linux/files/0140-drm-amd-powerplay-fix-a-reversed-condition.patch
deleted file mode 100644
index eeeeab1e..00000000
--- a/common/recipes-kernel/linux/files/0140-drm-amd-powerplay-fix-a-reversed-condition.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From cf517f048b1f4e035b131eddaa42914872503380 Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Mon, 4 Jan 2016 23:42:55 +0300
-Subject: [PATCH 0140/1110] drm/amd/powerplay: fix a reversed condition
-
-This test was reversed so it would end up leading to a NULL dereference.
-
-Fixes: 4630f0faae80 ('drm/amd/powerplay: add Carrizo smu support')
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-index e74023b..873a8d2 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-@@ -818,7 +818,7 @@ static int cz_smu_fini(struct pp_smumgr *smumgr)
- 		return -EINVAL;
- 
- 	cz_smu = (struct cz_smumgr *)smumgr->backend;
--	if (!cz_smu) {
-+	if (cz_smu) {
- 		cgs_free_gpu_mem(smumgr->device,
- 				cz_smu->toc_buffer.handle);
- 		cgs_free_gpu_mem(smumgr->device,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0141-drm-amdgpu-cgs-cleanup-some-indenting.patch b/common/recipes-kernel/linux/files/0141-drm-amdgpu-cgs-cleanup-some-indenting.patch
deleted file mode 100644
index 00f8314c..00000000
--- a/common/recipes-kernel/linux/files/0141-drm-amdgpu-cgs-cleanup-some-indenting.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From c472d7ed03c510d5b7ae17a5f6abc54594215d51 Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Mon, 4 Jan 2016 23:43:47 +0300
-Subject: [PATCH 0141/1110] drm/amdgpu/cgs: cleanup some indenting
-
-This code is indented too far.  Also we normally use spaces to align if
-statement conditions.
-
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 18 +++++++++---------
- 1 file changed, 9 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 6fa0fea..59485d0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -843,15 +843,15 @@ static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
- 	if (info->input_count > 0) {
- 		if (info->pinput_argument == NULL)
- 			return -EINVAL;
--			argument = info->pinput_argument;
--			func_no = argument->value;
--			for (i = 0; i < info->input_count; i++) {
--				if (((argument->type == ACPI_TYPE_STRING) ||
--					(argument->type == ACPI_TYPE_BUFFER))
--					&& (argument->pointer == NULL))
--					return -EINVAL;
--				argument++;
--			}
-+		argument = info->pinput_argument;
-+		func_no = argument->value;
-+		for (i = 0; i < info->input_count; i++) {
-+			if (((argument->type == ACPI_TYPE_STRING) ||
-+			     (argument->type == ACPI_TYPE_BUFFER)) &&
-+			    (argument->pointer == NULL))
-+				return -EINVAL;
-+			argument++;
-+		}
- 	}
- 
- 	if (info->output_count > 0) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0142-drm-amd-powerplay-precedence-bug-in-init_non_clock_f.patch b/common/recipes-kernel/linux/files/0142-drm-amd-powerplay-precedence-bug-in-init_non_clock_f.patch
deleted file mode 100644
index 460cba32..00000000
--- a/common/recipes-kernel/linux/files/0142-drm-amd-powerplay-precedence-bug-in-init_non_clock_f.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 6a20fdd606d7401aa6c7740af0927d56f15680ff Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Mon, 4 Jan 2016 23:44:24 +0300
-Subject: [PATCH 0142/1110] drm/amd/powerplay: precedence bug in
- init_non_clock_fields()
-
-The cast to uint8_t happens before the right shift so this always sets
-.m3arb to zero.  The cast is actually a no-op so we can remove it.
-
-Fixes: 3bace3591493 ('drm/amd/powerplay: add hardware manager sub-component')
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-index 1d385f4..8f9d705 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-@@ -735,8 +735,8 @@ static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
- 
- 	ps->memory.dllOff = (0 != tmp);
- 
--	ps->memory.m3arb = (uint8_t)(le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
--						ATOM_PPLIB_M3ARB_MASK) >> ATOM_PPLIB_M3ARB_SHIFT;
-+	ps->memory.m3arb = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-+			    ATOM_PPLIB_M3ARB_MASK) >> ATOM_PPLIB_M3ARB_SHIFT;
- 
- 	ps->temperatures.min = PP_TEMPERATURE_UNITS_PER_CENTIGRADES *
- 				     pnon_clock_info->ucMinTemperature;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0143-drm-amdgpu-fix-NULL-in-vm_grab_id-while-S3-back.patch b/common/recipes-kernel/linux/files/0143-drm-amdgpu-fix-NULL-in-vm_grab_id-while-S3-back.patch
deleted file mode 100644
index edc57e6e..00000000
--- a/common/recipes-kernel/linux/files/0143-drm-amdgpu-fix-NULL-in-vm_grab_id-while-S3-back.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 5883cd766f09e213a64acadcbeceb8c389113375 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Tue, 29 Dec 2015 11:57:38 +0800
-Subject: [PATCH 0143/1110] drm/amdgpu: fix NULL in vm_grab_id while S3 back
-
-vm_manager_fini shouldn't be in suspend phase.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 -
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 -
- 2 files changed, 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index 538af44..c1a4ec8 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -1005,7 +1005,6 @@ static int gmc_v7_0_sw_fini(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev->vm_manager.enabled) {
--		amdgpu_vm_manager_fini(adev);
- 		gmc_v7_0_vm_fini(adev);
- 		adev->vm_manager.enabled = false;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 2fcfa97..e59251f 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -1016,7 +1016,6 @@ static int gmc_v8_0_suspend(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev->vm_manager.enabled) {
--		amdgpu_vm_manager_fini(adev);
- 		gmc_v8_0_vm_fini(adev);
- 		adev->vm_manager.enabled = false;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0144-amdgpu-vce3-Cleanup-harvest-config-function.patch b/common/recipes-kernel/linux/files/0144-amdgpu-vce3-Cleanup-harvest-config-function.patch
deleted file mode 100644
index b82b3708..00000000
--- a/common/recipes-kernel/linux/files/0144-amdgpu-vce3-Cleanup-harvest-config-function.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From dacb4ef059137b8966f06ea457ae1bfacb45f098 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 10:21:46 -0500
-Subject: [PATCH 0144/1110] amdgpu/vce3: Cleanup harvest config function.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Basic LOC reduction.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 20 ++++++--------------
- 1 file changed, 6 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index 35f48ad..0de86de 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -314,14 +314,11 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
- static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
- {
- 	u32 tmp;
--	unsigned ret;
- 
- 	/* Fiji, Stoney are single pipe */
- 	if ((adev->asic_type == CHIP_FIJI) ||
--	    (adev->asic_type == CHIP_STONEY)){
--		ret = AMDGPU_VCE_HARVEST_VCE1;
--		return ret;
--	}
-+	    (adev->asic_type == CHIP_STONEY))
-+		return AMDGPU_VCE_HARVEST_VCE1;
- 
- 	/* Tonga and CZ are dual or single pipe */
- 	if (adev->flags & AMD_IS_APU)
-@@ -335,19 +332,14 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
- 
- 	switch (tmp) {
- 	case 1:
--		ret = AMDGPU_VCE_HARVEST_VCE0;
--		break;
-+		return AMDGPU_VCE_HARVEST_VCE0;
- 	case 2:
--		ret = AMDGPU_VCE_HARVEST_VCE1;
--		break;
-+		return AMDGPU_VCE_HARVEST_VCE1;
- 	case 3:
--		ret = AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
--		break;
-+		return AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
- 	default:
--		ret = 0;
-+		return 0;
- 	}
--
--	return ret;
- }
- 
- static int vce_v3_0_early_init(void *handle)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0145-amdgpu-vce3-Simplify-idle-and-wait-for-idle-code.patch b/common/recipes-kernel/linux/files/0145-amdgpu-vce3-Simplify-idle-and-wait-for-idle-code.patch
deleted file mode 100644
index a035054f..00000000
--- a/common/recipes-kernel/linux/files/0145-amdgpu-vce3-Simplify-idle-and-wait-for-idle-code.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 8ba6c8ff3550f5ff51e323f03d07d481b64f50cf Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 10:35:56 -0500
-Subject: [PATCH 0145/1110] amdgpu/vce3: Simplify idle and wait for idle code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-More LOC reductions in VCE3 code.  This patch simplifies the is_idle and
-wait_for_idle logic.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 30 +++++-------------------------
- 1 file changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index 0de86de..f20529d 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -535,17 +535,9 @@ static bool vce_v3_0_is_idle(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	u32 mask = 0;
--	int idx;
--
--	for (idx = 0; idx < 2; ++idx) {
--		if (adev->vce.harvest_config & (1 << idx))
--			continue;
- 
--		if (idx == 0)
--			mask |= SRBM_STATUS2__VCE0_BUSY_MASK;
--		else
--			mask |= SRBM_STATUS2__VCE1_BUSY_MASK;
--	}
-+	mask |= (adev->vce.harvest_config & (1<<0)) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
-+	mask |= (adev->vce.harvest_config & (1<<1)) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
- 
- 	return !(RREG32(mmSRBM_STATUS2) & mask);
- }
-@@ -554,23 +546,11 @@ static int vce_v3_0_wait_for_idle(void *handle)
- {
- 	unsigned i;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	u32 mask = 0;
--	int idx;
- 
--	for (idx = 0; idx < 2; ++idx) {
--		if (adev->vce.harvest_config & (1 << idx))
--			continue;
--
--		if (idx == 0)
--			mask |= SRBM_STATUS2__VCE0_BUSY_MASK;
--		else
--			mask |= SRBM_STATUS2__VCE1_BUSY_MASK;
--	}
--
--	for (i = 0; i < adev->usec_timeout; i++) {
--		if (!(RREG32(mmSRBM_STATUS2) & mask))
-+	for (i = 0; i < adev->usec_timeout; i++)
-+		if (vce_v3_0_is_idle(handle))
- 			return 0;
--	}
-+
- 	return -ETIMEDOUT;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0146-amdgpu-vce3-Simplify-vce_v3_0_soft_reset.patch b/common/recipes-kernel/linux/files/0146-amdgpu-vce3-Simplify-vce_v3_0_soft_reset.patch
deleted file mode 100644
index 2c884546..00000000
--- a/common/recipes-kernel/linux/files/0146-amdgpu-vce3-Simplify-vce_v3_0_soft_reset.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d9782da56ad40bdc7754395c90dbac618ad58bba Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 10:40:16 -0500
-Subject: [PATCH 0146/1110] amdgpu/vce3: Simplify vce_v3_0_soft_reset()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-LOC reduction and simplification.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 11 ++---------
- 1 file changed, 2 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index f20529d..d50db76 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -558,17 +558,10 @@ static int vce_v3_0_soft_reset(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	u32 mask = 0;
--	int idx;
- 
--	for (idx = 0; idx < 2; ++idx) {
--		if (adev->vce.harvest_config & (1 << idx))
--			continue;
-+	mask |= (adev->vce.harvest_config & (1<<0)) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
-+	mask |= (adev->vce.harvest_config & (1<<1)) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
- 
--		if (idx == 0)
--			mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
--		else
--			mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
--	}
- 	WREG32_P(mmSRBM_SOFT_RESET, mask,
- 		 ~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK |
- 		   SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK));
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0147-amdgpu-vce3-Simplify-vce_v3_0_process_interrupt.patch b/common/recipes-kernel/linux/files/0147-amdgpu-vce3-Simplify-vce_v3_0_process_interrupt.patch
deleted file mode 100644
index b22b13f6..00000000
--- a/common/recipes-kernel/linux/files/0147-amdgpu-vce3-Simplify-vce_v3_0_process_interrupt.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 283f037b56e596bbd8221e73de9cf7d0ebe4d92b Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 10:42:39 -0500
-Subject: [PATCH 0147/1110] amdgpu/vce3: Simplify vce_v3_0_process_interrupt()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Fold two cases into one for a LOC reduction.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index d50db76..d3e7ba6 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -663,10 +663,8 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
- 
- 	switch (entry->src_data) {
- 	case 0:
--		amdgpu_fence_process(&adev->vce.ring[0]);
--		break;
- 	case 1:
--		amdgpu_fence_process(&adev->vce.ring[1]);
-+		amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
- 		break;
- 	default:
- 		DRM_ERROR("Unhandled interrupt: %d %d\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0148-amdgpu-vce3-Remove-magic-constants-from-harvest-regi.patch b/common/recipes-kernel/linux/files/0148-amdgpu-vce3-Remove-magic-constants-from-harvest-regi.patch
deleted file mode 100644
index c6344f28..00000000
--- a/common/recipes-kernel/linux/files/0148-amdgpu-vce3-Remove-magic-constants-from-harvest-regi.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 8d0a67ee2c61056f67a7118be3fd55f591c31929 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 4 Jan 2016 10:46:41 -0500
-Subject: [PATCH 0148/1110] amdgpu/vce3: Remove magic constants from harvest
- register masks.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index d3e7ba6..ad56b1f 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -536,8 +536,8 @@ static bool vce_v3_0_is_idle(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	u32 mask = 0;
- 
--	mask |= (adev->vce.harvest_config & (1<<0)) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
--	mask |= (adev->vce.harvest_config & (1<<1)) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
-+	mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
-+	mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
- 
- 	return !(RREG32(mmSRBM_STATUS2) & mask);
- }
-@@ -559,8 +559,8 @@ static int vce_v3_0_soft_reset(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	u32 mask = 0;
- 
--	mask |= (adev->vce.harvest_config & (1<<0)) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
--	mask |= (adev->vce.harvest_config & (1<<1)) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
-+	mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
-+	mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
- 
- 	WREG32_P(mmSRBM_SOFT_RESET, mask,
- 		 ~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK |
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0149-amdgpu-vce3-Simplify-vce_v3_0_hw_init-and-ensure-bot.patch b/common/recipes-kernel/linux/files/0149-amdgpu-vce3-Simplify-vce_v3_0_hw_init-and-ensure-bot.patch
deleted file mode 100644
index b06f802f..00000000
--- a/common/recipes-kernel/linux/files/0149-amdgpu-vce3-Simplify-vce_v3_0_hw_init-and-ensure-bot.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From b22c8cdefe4b97e402c9387cb063fc3aaf7c2e1b Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 10:55:34 -0500
-Subject: [PATCH 0149/1110] amdgpu/vce3: Simplify vce_v3_0_hw_init and ensure
- both rings default to not ready.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Simplified the ring test and added logic to ensure rings are marked not ready
-by default.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 24 +++++++++---------------
- 1 file changed, 9 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index ad56b1f..e99af81 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -414,28 +414,22 @@ static int vce_v3_0_sw_fini(void *handle)
- 
- static int vce_v3_0_hw_init(void *handle)
- {
--	struct amdgpu_ring *ring;
--	int r;
-+	int r, i;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	r = vce_v3_0_start(adev);
- 	if (r)
- 		return r;
- 
--	ring = &adev->vce.ring[0];
--	ring->ready = true;
--	r = amdgpu_ring_test_ring(ring);
--	if (r) {
--		ring->ready = false;
--		return r;
--	}
-+	adev->vce.ring[0].ready = false;
-+	adev->vce.ring[1].ready = false;
- 
--	ring = &adev->vce.ring[1];
--	ring->ready = true;
--	r = amdgpu_ring_test_ring(ring);
--	if (r) {
--		ring->ready = false;
--		return r;
-+	for (i = 0; i < 2; i++) {
-+		r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
-+		if (r)
-+			return r;
-+		else
-+			adev->vce.ring[i].ready = true;
- 	}
- 
- 	DRM_INFO("VCE initialized successfully.\n");
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0150-amdgpu-dce11-Remove-division-from-dce_v11_0_vblank_w.patch b/common/recipes-kernel/linux/files/0150-amdgpu-dce11-Remove-division-from-dce_v11_0_vblank_w.patch
deleted file mode 100644
index 22e759f0..00000000
--- a/common/recipes-kernel/linux/files/0150-amdgpu-dce11-Remove-division-from-dce_v11_0_vblank_w.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From f53cc5d2a8d79ee93befd170a94a385ae700d35a Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 13:01:49 -0500
-Subject: [PATCH 0150/1110] amdgpu/dce11: Remove division from
- dce_v11_0_vblank_wait()
-
-Mimics odd behaviour where (i++ % 100 == 0) is true in the first iteration of each loop...
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 8701661..80be62a 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -211,7 +211,7 @@ static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
-  */
- static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
- {
--	unsigned i = 0;
-+	unsigned i = 100;
- 
- 	if (crtc >= adev->mode_info.num_crtc)
- 		return;
-@@ -223,14 +223,16 @@ static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
- 	 * wait for another frame.
- 	 */
- 	while (dce_v11_0_is_in_vblank(adev, crtc)) {
--		if (i++ % 100 == 0) {
-+		if (i++ == 100) {
-+			i = 0;
- 			if (!dce_v11_0_is_counter_moving(adev, crtc))
- 				break;
- 		}
- 	}
- 
- 	while (!dce_v11_0_is_in_vblank(adev, crtc)) {
--		if (i++ % 100 == 0) {
-+		if (i++ == 100) {
-+			i = 0;
- 			if (!dce_v11_0_is_counter_moving(adev, crtc))
- 				break;
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0151-amdgpu-dce11-Add-test-for-crtc-0-to-various-DCEv11-f.patch b/common/recipes-kernel/linux/files/0151-amdgpu-dce11-Add-test-for-crtc-0-to-various-DCEv11-f.patch
deleted file mode 100644
index 29c8ce54..00000000
--- a/common/recipes-kernel/linux/files/0151-amdgpu-dce11-Add-test-for-crtc-0-to-various-DCEv11-f.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 6f0803b38e7683b4fd2ac427bba91a99d1557f18 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 15 Dec 2015 13:03:43 -0500
-Subject: [PATCH 0151/1110] amdgpu/dce11: Add test for crtc < 0 to various
- DCEv11 functions
-
-To be consistent with other DCE11 functions test for crtc < 0.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 80be62a..8e67249 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -213,7 +213,7 @@ static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
- {
- 	unsigned i = 100;
- 
--	if (crtc >= adev->mode_info.num_crtc)
-+	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
- 		return;
- 
- 	if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
-@@ -241,7 +241,7 @@ static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
- 
- static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
- {
--	if (crtc >= adev->mode_info.num_crtc)
-+	if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
- 		return 0;
- 	else
- 		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
-@@ -3386,7 +3386,7 @@ static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
- {
- 	u32 tmp;
- 
--	if (crtc >= adev->mode_info.num_crtc) {
-+	if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
- 		DRM_DEBUG("invalid crtc %d\n", crtc);
- 		return;
- 	}
-@@ -3401,7 +3401,7 @@ static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
- {
- 	u32 tmp;
- 
--	if (crtc >= adev->mode_info.num_crtc) {
-+	if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
- 		DRM_DEBUG("invalid crtc %d\n", crtc);
- 		return;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0152-drm-amd-powerplay-fix-bug-that-NULL-checks-are-rever.patch b/common/recipes-kernel/linux/files/0152-drm-amd-powerplay-fix-bug-that-NULL-checks-are-rever.patch
deleted file mode 100644
index 397da594..00000000
--- a/common/recipes-kernel/linux/files/0152-drm-amd-powerplay-fix-bug-that-NULL-checks-are-rever.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 7e79b0a0025c11fc8dc23253eb13accc264abf4e Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 6 Jan 2016 16:22:07 +0800
-Subject: [PATCH 0152/1110] drm/amd/powerplay: fix bug that NULL checks are
- reversed.
-
-&& was used instead of ||.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 5bac36b..c0e6aae 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -579,7 +579,7 @@ static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
- 					hwmgr->dyn_state.vddc_dependency_on_sclk;
- 	unsigned long clock = 0, level;
- 
--	if (NULL == table && table->count <= 0)
-+	if (NULL == table || table->count <= 0)
- 		return -EINVAL;
- 
- 	cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
-@@ -606,7 +606,7 @@ static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
- 				hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
- 	unsigned long clock = 0, level;
- 
--	if (NULL == table && table->count <= 0)
-+	if (NULL == table || table->count <= 0)
- 		return -EINVAL;
- 
- 	cz_hwmgr->uvd_dpm.soft_min_clk = 0;
-@@ -634,7 +634,7 @@ static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
- 				hwmgr->dyn_state.vce_clock_voltage_dependency_table;
- 	unsigned long clock = 0, level;
- 
--	if (NULL == table && table->count <= 0)
-+	if (NULL == table || table->count <= 0)
- 		return -EINVAL;
- 
- 	cz_hwmgr->vce_dpm.soft_min_clk = 0;
-@@ -662,7 +662,7 @@ static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
- 				hwmgr->dyn_state.acp_clock_voltage_dependency_table;
- 	unsigned long clock = 0, level;
- 
--	if (NULL == table && table->count <= 0)
-+	if (NULL == table || table->count <= 0)
- 		return -EINVAL;
- 
- 	cz_hwmgr->acp_dpm.soft_min_clk = 0;
-@@ -1183,7 +1183,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
- 				hwmgr->dyn_state.vddc_dependency_on_sclk;
- 	unsigned long clock = 0, level;
- 
--	if (NULL == table && table->count <= 0)
-+	if (NULL == table || table->count <= 0)
- 		return -EINVAL;
- 
- 	cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0153-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch b/common/recipes-kernel/linux/files/0153-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch
deleted file mode 100644
index b1f4b6f3..00000000
--- a/common/recipes-kernel/linux/files/0153-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch
+++ /dev/null
@@ -1,993 +0,0 @@
-From ad143b8bf42dfb169b345c19d099d3e2146e33fd Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 6 Jan 2016 16:38:48 +0800
-Subject: [PATCH 0153/1110] drm/amd/powerplay: fix Smatch static checker
- warnings with indenting (v2)
-
-v2: AGD: rebase on upstream
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c             |   2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  51 +-
- .../gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c   |  12 +-
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |   1 -
- drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h    | 555 ++++++++++-----------
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |   8 +-
- 6 files changed, 312 insertions(+), 317 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index e05ae17..398c197 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -808,7 +808,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
- 				struct amdgpu_ring *ring = adev->rings[i];
- 				if (ring && ring->ready)
- 					amdgpu_fence_wait_empty(ring);
--				}
-+			}
- 		mutex_unlock(&adev->ring_lock);
- 
- 		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 94f404c..6dba5bf 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -941,8 +941,9 @@ static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
- 	memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
- 	kfree(table);
- 
--    return 0;
-+	return 0;
- }
-+
- static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
- 		phm_ppt_v1_clock_voltage_dependency_table *dep_table)
- {
-@@ -1112,7 +1113,7 @@ static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
- 			fiji_trim_voltage_table_to_fit_state_table(hwmgr,
- 					SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
- 
--    return 0;
-+	return 0;
- }
- 
- static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-@@ -1158,7 +1159,7 @@ static int fiji_program_static_screen_threshold_parameters(
- 			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
- 			data->static_screen_threshold);
- 
--    return 0;
-+	return 0;
- }
- 
- /**
-@@ -1295,7 +1296,7 @@ static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
- 
- 	error |= (0 != result);
- 
--    return error ? -1 : 0;
-+	return error ? -1 : 0;
- }
- 
- /* Copy one arb setting to another and then switch the active set.
-@@ -1339,12 +1340,12 @@ static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
- 		return -EINVAL;
- 	}
- 
--    mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
--    mc_cg_config |= 0x0000000F;
--    cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
--    PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
-+	mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
-+	mc_cg_config |= 0x0000000F;
-+	cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
-+	PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
- 
--    return 0;
-+	return 0;
- }
- 
- /**
-@@ -1927,17 +1928,17 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- 
- 	threshold = clock * data->fast_watermark_threshold / 100;
- 
--    /*
--     * TODO: get minimum clocks from dal configaration
--     * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
--     */
--    /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
-+	/*
-+	* TODO: get minimum clocks from dal configaration
-+	* PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
-+	*/
-+	/* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
- 
--    /* get level->DeepSleepDivId
--    if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
--    {
--        level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
--    } */
-+	/* get level->DeepSleepDivId
-+	if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+	{
-+	level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
-+	} */
- 
- 	/* Default to slow, highest DPM level will be
- 	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-@@ -2756,7 +2757,7 @@ static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
- 			SclkFrequency) / 100);
- 	if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
- 			clock_freq_u16 &&
--        fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
-+	    fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
- 			clock_freq_u16) {
- 		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
- 		value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-@@ -3172,9 +3173,9 @@ static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
- 	/* enable SCLK dpm */
- 	if(!data->sclk_dpm_key_disabled)
- 		PP_ASSERT_WITH_CODE(
--            (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
--            "Failed to enable SCLK DPM during DPM Start Function!",
--            return -1);
-+		(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
-+		"Failed to enable SCLK DPM during DPM Start Function!",
-+		return -1);
- 
- 	/* enable MCLK dpm */
- 	if(0 == data->mclk_dpm_key_disabled) {
-@@ -3320,7 +3321,7 @@ static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
- 				return -1);
- 	}
- 
--    return 0;
-+	return 0;
- }
- 
- static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
-@@ -3378,7 +3379,7 @@ static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
- 
- static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
- {
--    return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
-+	return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
- }
- 
- static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-index f89c98f..6efcb2b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-@@ -93,9 +93,9 @@ void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-  */
- static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
- {
--    uint32_t tmp;
--    tmp = raw_setting * 4096 / 100;
--    return (uint16_t)tmp;
-+	uint32_t tmp;
-+	tmp = raw_setting * 4096 / 100;
-+	return (uint16_t)tmp;
- }
- 
- static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
-@@ -546,8 +546,8 @@ int fiji_power_control_set_level(struct pp_hwmgr *hwmgr)
- 		 * but message to be 8 bit fraction for messages
- 		 */
- 		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
--        result = fiji_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
--    }
-+		result = fiji_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
-+	}
- 
--    return result;
-+	return result;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 001b8bb..f9bf4fc 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -317,4 +317,3 @@ int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- 
- 	return 0;
- }
--
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-index 411cb0f..b7429a5 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-@@ -117,379 +117,380 @@ int GetRoundedValue(fInt);                         /* Incomplete function - Usef
-  */
- fInt fExponential(fInt exponent)        /*Can be used to calculate e^exponent*/
- {
--    uint32_t i;
--    bool bNegated = false;
-+	uint32_t i;
-+	bool bNegated = false;
- 
--    fInt fPositiveOne = ConvertToFraction(1);
--    fInt fZERO = ConvertToFraction(0);
-+	fInt fPositiveOne = ConvertToFraction(1);
-+	fInt fZERO = ConvertToFraction(0);
- 
--    fInt lower_bound = Divide(78, 10000);
--    fInt solution = fPositiveOne; /*Starting off with baseline of 1 */
--    fInt error_term;
-+	fInt lower_bound = Divide(78, 10000);
-+	fInt solution = fPositiveOne; /*Starting off with baseline of 1 */
-+	fInt error_term;
- 
--    uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
--    uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
-+	uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
-+	uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
- 
--    if (GreaterThan(fZERO, exponent)) {
--        exponent = fNegate(exponent);
--        bNegated = true;
--    }
-+	if (GreaterThan(fZERO, exponent)) {
-+		exponent = fNegate(exponent);
-+		bNegated = true;
-+	}
- 
--    while (GreaterThan(exponent, lower_bound)) {
--        for (i = 0; i < 11; i++) {
--            if (GreaterThan(exponent, GetScaledFraction(k_array[i], 10000))) {
--                exponent = fSubtract(exponent, GetScaledFraction(k_array[i], 10000));
--                solution = fMultiply(solution, GetScaledFraction(expk_array[i], 10000));
--            }
--        }
--    }
-+	while (GreaterThan(exponent, lower_bound)) {
-+		for (i = 0; i < 11; i++) {
-+			if (GreaterThan(exponent, GetScaledFraction(k_array[i], 10000))) {
-+				exponent = fSubtract(exponent, GetScaledFraction(k_array[i], 10000));
-+				solution = fMultiply(solution, GetScaledFraction(expk_array[i], 10000));
-+			}
-+		}
-+	}
- 
--    error_term = fAdd(fPositiveOne, exponent);
-+	error_term = fAdd(fPositiveOne, exponent);
- 
--    solution = fMultiply(solution, error_term);
-+	solution = fMultiply(solution, error_term);
- 
--    if (bNegated)
--        solution = fDivide(fPositiveOne, solution);
-+	if (bNegated)
-+		solution = fDivide(fPositiveOne, solution);
- 
--    return solution;
-+	return solution;
- }
- 
- fInt fNaturalLog(fInt value)
- {
--    uint32_t i;
--    fInt upper_bound = Divide(8, 1000);
--    fInt fNegativeOne = ConvertToFraction(-1);
--    fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */
--    fInt error_term;
--
--    uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
--    uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
--
--    while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) {
--        for (i = 0; i < 10; i++) {
--            if (GreaterThan(value, GetScaledFraction(k_array[i], 10000))) {
--                value = fDivide(value, GetScaledFraction(k_array[i], 10000));
--                solution = fAdd(solution, GetScaledFraction(logk_array[i], 10000));
--            }
--        }
--    }
--
--    error_term = fAdd(fNegativeOne, value);
--
--    return (fAdd(solution, error_term));
-+	uint32_t i;
-+	fInt upper_bound = Divide(8, 1000);
-+	fInt fNegativeOne = ConvertToFraction(-1);
-+	fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */
-+	fInt error_term;
-+
-+	uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
-+	uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
-+
-+	while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) {
-+		for (i = 0; i < 10; i++) {
-+			if (GreaterThan(value, GetScaledFraction(k_array[i], 10000))) {
-+				value = fDivide(value, GetScaledFraction(k_array[i], 10000));
-+				solution = fAdd(solution, GetScaledFraction(logk_array[i], 10000));
-+			}
-+		}
-+	}
-+
-+	error_term = fAdd(fNegativeOne, value);
-+
-+	return (fAdd(solution, error_term));
- }
- 
- fInt fDecodeLinearFuse(uint32_t fuse_value, fInt f_min, fInt f_range, uint32_t bitlength)
- {
--    fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
--    fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
-+	fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
-+	fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
- 
--    fInt f_decoded_value;
-+	fInt f_decoded_value;
- 
--    f_decoded_value = fDivide(f_fuse_value, f_bit_max_value);
--    f_decoded_value = fMultiply(f_decoded_value, f_range);
--    f_decoded_value = fAdd(f_decoded_value, f_min);
-+	f_decoded_value = fDivide(f_fuse_value, f_bit_max_value);
-+	f_decoded_value = fMultiply(f_decoded_value, f_range);
-+	f_decoded_value = fAdd(f_decoded_value, f_min);
- 
--    return f_decoded_value;
-+	return f_decoded_value;
- }
- 
- 
- fInt fDecodeLogisticFuse(uint32_t fuse_value, fInt f_average, fInt f_range, uint32_t bitlength)
- {
--    fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
--    fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
-+	fInt f_fuse_value = Convert_ULONG_ToFraction(fuse_value);
-+	fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
- 
--    fInt f_CONSTANT_NEG13 = ConvertToFraction(-13);
--    fInt f_CONSTANT1 = ConvertToFraction(1);
-+	fInt f_CONSTANT_NEG13 = ConvertToFraction(-13);
-+	fInt f_CONSTANT1 = ConvertToFraction(1);
- 
--    fInt f_decoded_value;
-+	fInt f_decoded_value;
- 
--    f_decoded_value = fSubtract(fDivide(f_bit_max_value, f_fuse_value), f_CONSTANT1);
--    f_decoded_value = fNaturalLog(f_decoded_value);
--    f_decoded_value = fMultiply(f_decoded_value, fDivide(f_range, f_CONSTANT_NEG13));
--    f_decoded_value = fAdd(f_decoded_value, f_average);
-+	f_decoded_value = fSubtract(fDivide(f_bit_max_value, f_fuse_value), f_CONSTANT1);
-+	f_decoded_value = fNaturalLog(f_decoded_value);
-+	f_decoded_value = fMultiply(f_decoded_value, fDivide(f_range, f_CONSTANT_NEG13));
-+	f_decoded_value = fAdd(f_decoded_value, f_average);
- 
--    return f_decoded_value;
-+	return f_decoded_value;
- }
- 
- fInt fDecodeLeakageID (uint32_t leakageID_fuse, fInt ln_max_div_min, fInt f_min, uint32_t bitlength)
- {
--    fInt fLeakage;
--    fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
-+	fInt fLeakage;
-+	fInt f_bit_max_value = Convert_ULONG_ToFraction((uPow(2, bitlength)) - 1);
- 
--    fLeakage = fMultiply(ln_max_div_min, Convert_ULONG_ToFraction(leakageID_fuse));
--    fLeakage = fDivide(fLeakage, f_bit_max_value);
--    fLeakage = fExponential(fLeakage);
--    fLeakage = fMultiply(fLeakage, f_min);
-+	fLeakage = fMultiply(ln_max_div_min, Convert_ULONG_ToFraction(leakageID_fuse));
-+	fLeakage = fDivide(fLeakage, f_bit_max_value);
-+	fLeakage = fExponential(fLeakage);
-+	fLeakage = fMultiply(fLeakage, f_min);
- 
--    return fLeakage;
-+	return fLeakage;
- }
- 
- fInt ConvertToFraction(int X) /*Add all range checking here. Is it possible to make fInt a private declaration? */
- {
--    fInt temp;
-+	fInt temp;
- 
--    if (X <= MAX)
--        temp.full = (X << SHIFT_AMOUNT);
--    else
--        temp.full = 0;
-+	if (X <= MAX)
-+		temp.full = (X << SHIFT_AMOUNT);
-+	else
-+		temp.full = 0;
- 
--    return temp;
-+	return temp;
- }
- 
- fInt fNegate(fInt X)
- {
--    fInt CONSTANT_NEGONE = ConvertToFraction(-1);
--    return (fMultiply(X, CONSTANT_NEGONE));
-+	fInt CONSTANT_NEGONE = ConvertToFraction(-1);
-+	return (fMultiply(X, CONSTANT_NEGONE));
- }
- 
- fInt Convert_ULONG_ToFraction(uint32_t X)
- {
--    fInt temp;
-+	fInt temp;
- 
--    if (X <= MAX)
--        temp.full = (X << SHIFT_AMOUNT);
--    else
--        temp.full = 0;
-+	if (X <= MAX)
-+		temp.full = (X << SHIFT_AMOUNT);
-+	else
-+		temp.full = 0;
- 
--    return temp;
-+	return temp;
- }
- 
- fInt GetScaledFraction(int X, int factor)
- {
--    int times_shifted, factor_shifted;
--    bool bNEGATED;
--    fInt fValue;
--
--    times_shifted = 0;
--    factor_shifted = 0;
--    bNEGATED = false;
--
--    if (X < 0) {
--        X = -1*X;
--        bNEGATED = true;
--    }
--
--    if (factor < 0) {
--        factor = -1*factor;
--
--        bNEGATED = !bNEGATED; /*If bNEGATED = true due to X < 0, this will cover the case of negative cancelling negative */
--    }
--
--    if ((X > MAX) || factor > MAX) {
--        if ((X/factor) <= MAX) {
--            while (X > MAX) {
--                X = X >> 1;
--                times_shifted++;
--            }
--
--            while (factor > MAX) {
--                factor = factor >> 1;
--                factor_shifted++;
--            }
--        } else {
--            fValue.full = 0;
--            return fValue;
--        }
--    }
--
--    if (factor == 1)
--        return (ConvertToFraction(X));
--
--    fValue = fDivide(ConvertToFraction(X * uPow(-1, bNEGATED)), ConvertToFraction(factor));
--
--    fValue.full = fValue.full << times_shifted;
--    fValue.full = fValue.full >> factor_shifted;
--
--    return fValue;
-+	int times_shifted, factor_shifted;
-+	bool bNEGATED;
-+	fInt fValue;
-+
-+	times_shifted = 0;
-+	factor_shifted = 0;
-+	bNEGATED = false;
-+
-+	if (X < 0) {
-+		X = -1*X;
-+		bNEGATED = true;
-+	}
-+
-+	if (factor < 0) {
-+		factor = -1*factor;
-+		bNEGATED = !bNEGATED; /*If bNEGATED = true due to X < 0, this will cover the case of negative cancelling negative */
-+	}
-+
-+	if ((X > MAX) || factor > MAX) {
-+		if ((X/factor) <= MAX) {
-+			while (X > MAX) {
-+				X = X >> 1;
-+				times_shifted++;
-+			}
-+
-+			while (factor > MAX) {
-+				factor = factor >> 1;
-+				factor_shifted++;
-+			}
-+		} else {
-+			fValue.full = 0;
-+			return fValue;
-+		}
-+	}
-+
-+	if (factor == 1)
-+	return (ConvertToFraction(X));
-+
-+	fValue = fDivide(ConvertToFraction(X * uPow(-1, bNEGATED)), ConvertToFraction(factor));
-+
-+	fValue.full = fValue.full << times_shifted;
-+	fValue.full = fValue.full >> factor_shifted;
-+
-+	return fValue;
- }
- 
- /* Addition using two fInts */
- fInt fAdd (fInt X, fInt Y)
- {
--    fInt Sum;
-+	fInt Sum;
- 
--    Sum.full = X.full + Y.full;
-+	Sum.full = X.full + Y.full;
- 
--    return Sum;
-+	return Sum;
- }
- 
- /* Addition using two fInts */
- fInt fSubtract (fInt X, fInt Y)
- {
--    fInt Difference;
-+	fInt Difference;
- 
--    Difference.full = X.full - Y.full;
-+	Difference.full = X.full - Y.full;
- 
--    return Difference;
-+	return Difference;
- }
- 
- bool Equal(fInt A, fInt B)
- {
--    if (A.full == B.full)
--        return true;
--    else
--        return false;
-+	if (A.full == B.full)
-+		return true;
-+	else
-+		return false;
- }
- 
- bool GreaterThan(fInt A, fInt B)
- {
--    if (A.full > B.full)
--        return true;
--    else
--        return false;
-+	if (A.full > B.full)
-+		return true;
-+	else
-+		return false;
- }
- 
- fInt fMultiply (fInt X, fInt Y) /* Uses 64-bit integers (int64_t) */
- {
--    fInt Product;
--    int64_t tempProduct;
--    bool X_LessThanOne, Y_LessThanOne;
-+	fInt Product;
-+	int64_t tempProduct;
-+	bool X_LessThanOne, Y_LessThanOne;
- 
--    X_LessThanOne = (X.partial.real == 0 && X.partial.decimal != 0 && X.full >= 0);
--    Y_LessThanOne = (Y.partial.real == 0 && Y.partial.decimal != 0 && Y.full >= 0);
-+	X_LessThanOne = (X.partial.real == 0 && X.partial.decimal != 0 && X.full >= 0);
-+	Y_LessThanOne = (Y.partial.real == 0 && Y.partial.decimal != 0 && Y.full >= 0);
- 
--    /*The following is for a very specific common case: Non-zero number with ONLY fractional portion*/
--    /* TEMPORARILY DISABLED - CAN BE USED TO IMPROVE PRECISION
-+	/*The following is for a very specific common case: Non-zero number with ONLY fractional portion*/
-+	/* TEMPORARILY DISABLED - CAN BE USED TO IMPROVE PRECISION
- 
--    if (X_LessThanOne && Y_LessThanOne) {
--        Product.full = X.full * Y.full;
--        return Product
--    }*/
-+	if (X_LessThanOne && Y_LessThanOne) {
-+		Product.full = X.full * Y.full;
-+		return Product
-+	}*/
- 
--    tempProduct = ((int64_t)X.full) * ((int64_t)Y.full); /*Q(16,16)*Q(16,16) = Q(32, 32) - Might become a negative number! */
--    tempProduct = tempProduct >> 16; /*Remove lagging 16 bits - Will lose some precision from decimal; */
--    Product.full = (int)tempProduct; /*The int64_t will lose the leading 16 bits that were part of the integer portion */
-+	tempProduct = ((int64_t)X.full) * ((int64_t)Y.full); /*Q(16,16)*Q(16,16) = Q(32, 32) - Might become a negative number! */
-+	tempProduct = tempProduct >> 16; /*Remove lagging 16 bits - Will lose some precision from decimal; */
-+	Product.full = (int)tempProduct; /*The int64_t will lose the leading 16 bits that were part of the integer portion */
- 
--    return Product;
-+	return Product;
- }
- 
- fInt fDivide (fInt X, fInt Y)
- {
--    fInt fZERO, fQuotient;
--    int64_t longlongX, longlongY;
-+	fInt fZERO, fQuotient;
-+	int64_t longlongX, longlongY;
- 
--    fZERO = ConvertToFraction(0);
-+	fZERO = ConvertToFraction(0);
- 
--    if (Equal(Y, fZERO))
--        return fZERO;
-+	if (Equal(Y, fZERO))
-+	return fZERO;
- 
--    longlongX = (int64_t)X.full;
--    longlongY = (int64_t)Y.full;
-+	longlongX = (int64_t)X.full;
-+	longlongY = (int64_t)Y.full;
- 
--    longlongX = longlongX << 16; /*Q(16,16) -> Q(32,32) */
-+	longlongX = longlongX << 16; /*Q(16,16) -> Q(32,32) */
- 
--    div64_s64(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */
-+	div64_s64(longlongX, longlongY); /*Q(32,32) divided by Q(16,16) = Q(16,16) Back to original format */
- 
--    fQuotient.full = (int)longlongX;
--    return fQuotient;
-+	fQuotient.full = (int)longlongX;
-+	return fQuotient;
- }
- 
- int ConvertBackToInteger (fInt A) /*THIS is the function that will be used to check with the Golden settings table*/
- {
--    fInt fullNumber, scaledDecimal, scaledReal;
-+	fInt fullNumber, scaledDecimal, scaledReal;
- 
--    scaledReal.full = GetReal(A) * uPow(10, PRECISION-1); /* DOUBLE CHECK THISSSS!!! */
-+	scaledReal.full = GetReal(A) * uPow(10, PRECISION-1); /* DOUBLE CHECK THISSSS!!! */
- 
--    scaledDecimal.full = uGetScaledDecimal(A);
-+	scaledDecimal.full = uGetScaledDecimal(A);
- 
--    fullNumber = fAdd(scaledDecimal,scaledReal);
-+	fullNumber = fAdd(scaledDecimal,scaledReal);
- 
--    return fullNumber.full;
-+	return fullNumber.full;
- }
- 
- fInt fGetSquare(fInt A)
- {
--    return fMultiply(A,A);
-+	return fMultiply(A,A);
- }
- 
- /* x_new = x_old - (x_old^2 - C) / (2 * x_old) */
- fInt fSqrt(fInt num)
- {
--    fInt F_divide_Fprime, Fprime;
--    fInt test;
--    fInt twoShifted;
--    int seed, counter, error;
--    fInt x_new, x_old, C, y;
-+	fInt F_divide_Fprime, Fprime;
-+	fInt test;
-+	fInt twoShifted;
-+	int seed, counter, error;
-+	fInt x_new, x_old, C, y;
- 
--    fInt fZERO = ConvertToFraction(0);
--    /* (0 > num) is the same as (num < 0), i.e., num is negative */
--    if (GreaterThan(fZERO, num) || Equal(fZERO, num))
--        return fZERO;
-+	fInt fZERO = ConvertToFraction(0);
- 
--    C = num;
-+	/* (0 > num) is the same as (num < 0), i.e., num is negative */
- 
--    if (num.partial.real > 3000)
--        seed = 60;
--    else if (num.partial.real > 1000)
--        seed = 30;
--    else if (num.partial.real > 100)
--        seed = 10;
--    else
--        seed = 2;
-+	if (GreaterThan(fZERO, num) || Equal(fZERO, num))
-+		return fZERO;
- 
--    counter = 0;
-+	C = num;
- 
--    if (Equal(num, fZERO)) /*Square Root of Zero is zero */
--        return fZERO;
-+	if (num.partial.real > 3000)
-+		seed = 60;
-+	else if (num.partial.real > 1000)
-+		seed = 30;
-+	else if (num.partial.real > 100)
-+		seed = 10;
-+	else
-+		seed = 2;
-+
-+	counter = 0;
- 
--    twoShifted = ConvertToFraction(2);
--    x_new = ConvertToFraction(seed);
-+	if (Equal(num, fZERO)) /*Square Root of Zero is zero */
-+		return fZERO;
- 
--    do {
--        counter++;
-+	twoShifted = ConvertToFraction(2);
-+	x_new = ConvertToFraction(seed);
- 
--        x_old.full = x_new.full;
-+	do {
-+		counter++;
- 
--        test = fGetSquare(x_old); /*1.75*1.75 is reverting back to 1 when shifted down */
--        y = fSubtract(test, C); /*y = f(x) = x^2 - C; */
-+		x_old.full = x_new.full;
- 
--        Fprime = fMultiply(twoShifted, x_old);
--        F_divide_Fprime = fDivide(y, Fprime);
-+		test = fGetSquare(x_old); /*1.75*1.75 is reverting back to 1 when shifted down */
-+		y = fSubtract(test, C); /*y = f(x) = x^2 - C; */
- 
--        x_new = fSubtract(x_old, F_divide_Fprime);
-+		Fprime = fMultiply(twoShifted, x_old);
-+		F_divide_Fprime = fDivide(y, Fprime);
- 
--        error = ConvertBackToInteger(x_new) - ConvertBackToInteger(x_old);
-+		x_new = fSubtract(x_old, F_divide_Fprime);
- 
--        if (counter > 20) /*20 is already way too many iterations. If we dont have an answer by then, we never will*/
--            return x_new;
-+		error = ConvertBackToInteger(x_new) - ConvertBackToInteger(x_old);
- 
--    } while (uAbs(error) > 0);
-+		if (counter > 20) /*20 is already way too many iterations. If we dont have an answer by then, we never will*/
-+			return x_new;
- 
--    return (x_new);
-+	} while (uAbs(error) > 0);
-+
-+	return (x_new);
- }
- 
- void SolveQuadracticEqn(fInt A, fInt B, fInt C, fInt Roots[])
- {
--    fInt* pRoots = &Roots[0];
--    fInt temp, root_first, root_second;
--    fInt f_CONSTANT10, f_CONSTANT100;
-+	fInt *pRoots = &Roots[0];
-+	fInt temp, root_first, root_second;
-+	fInt f_CONSTANT10, f_CONSTANT100;
- 
--    f_CONSTANT100 = ConvertToFraction(100);
--    f_CONSTANT10 = ConvertToFraction(10);
-+	f_CONSTANT100 = ConvertToFraction(100);
-+	f_CONSTANT10 = ConvertToFraction(10);
- 
--    while(GreaterThan(A, f_CONSTANT100) || GreaterThan(B, f_CONSTANT100) || GreaterThan(C, f_CONSTANT100)) {
--        A = fDivide(A, f_CONSTANT10);
--        B = fDivide(B, f_CONSTANT10);
--        C = fDivide(C, f_CONSTANT10);
--    }
-+	while(GreaterThan(A, f_CONSTANT100) || GreaterThan(B, f_CONSTANT100) || GreaterThan(C, f_CONSTANT100)) {
-+		A = fDivide(A, f_CONSTANT10);
-+		B = fDivide(B, f_CONSTANT10);
-+		C = fDivide(C, f_CONSTANT10);
-+	}
- 
--    temp = fMultiply(ConvertToFraction(4), A); /* root = 4*A */
--    temp = fMultiply(temp, C); /* root = 4*A*C */
--    temp = fSubtract(fGetSquare(B), temp); /* root = b^2 - 4AC */
--    temp = fSqrt(temp); /*root = Sqrt (b^2 - 4AC); */
-+	temp = fMultiply(ConvertToFraction(4), A); /* root = 4*A */
-+	temp = fMultiply(temp, C); /* root = 4*A*C */
-+	temp = fSubtract(fGetSquare(B), temp); /* root = b^2 - 4AC */
-+	temp = fSqrt(temp); /*root = Sqrt (b^2 - 4AC); */
- 
--    root_first = fSubtract(fNegate(B), temp); /* b - Sqrt(b^2 - 4AC) */
--    root_second = fAdd(fNegate(B), temp); /* b + Sqrt(b^2 - 4AC) */
-+	root_first = fSubtract(fNegate(B), temp); /* b - Sqrt(b^2 - 4AC) */
-+	root_second = fAdd(fNegate(B), temp); /* b + Sqrt(b^2 - 4AC) */
- 
--    root_first = fDivide(root_first, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
--    root_first = fDivide(root_first, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */
-+	root_first = fDivide(root_first, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
-+	root_first = fDivide(root_first, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */
- 
--    root_second = fDivide(root_second, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
--    root_second = fDivide(root_second, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */
-+	root_second = fDivide(root_second, ConvertToFraction(2)); /* [b +- Sqrt(b^2 - 4AC)]/[2] */
-+	root_second = fDivide(root_second, A); /*[b +- Sqrt(b^2 - 4AC)]/[2*A] */
- 
--    *(pRoots + 0) = root_first;
--    *(pRoots + 1) = root_second;
-+	*(pRoots + 0) = root_first;
-+	*(pRoots + 1) = root_second;
- }
- 
- /* -----------------------------------------------------------------------------
-@@ -500,61 +501,58 @@ void SolveQuadracticEqn(fInt A, fInt B, fInt C, fInt Roots[])
- /* Addition using two normal ints - Temporary - Use only for testing purposes?. */
- fInt Add (int X, int Y)
- {
--    fInt A, B, Sum;
-+	fInt A, B, Sum;
- 
--    A.full = (X << SHIFT_AMOUNT);
--    B.full = (Y << SHIFT_AMOUNT);
-+	A.full = (X << SHIFT_AMOUNT);
-+	B.full = (Y << SHIFT_AMOUNT);
- 
--    Sum.full = A.full + B.full;
-+	Sum.full = A.full + B.full;
- 
--    return Sum;
-+	return Sum;
- }
- 
- /* Conversion Functions */
- int GetReal (fInt A)
- {
--    return (A.full >> SHIFT_AMOUNT);
-+	return (A.full >> SHIFT_AMOUNT);
- }
- 
- /* Temporarily Disabled */
- int GetRoundedValue(fInt A) /*For now, round the 3rd decimal place */
- {
--    /* ROUNDING TEMPORARLY DISABLED
--    int temp = A.full;
--
--    int decimal_cutoff, decimal_mask = 0x000001FF;
--
--    decimal_cutoff = temp & decimal_mask;
--
--
--    if (decimal_cutoff > 0x147) {
--        temp += 673;
--    }*/
--
--    return ConvertBackToInteger(A)/10000; /*Temporary - in case this was used somewhere else */
-+	/* ROUNDING TEMPORARLY DISABLED
-+	int temp = A.full;
-+	int decimal_cutoff, decimal_mask = 0x000001FF;
-+	decimal_cutoff = temp & decimal_mask;
-+	if (decimal_cutoff > 0x147) {
-+		temp += 673;
-+	}*/
-+
-+	return ConvertBackToInteger(A)/10000; /*Temporary - in case this was used somewhere else */
- }
- 
- fInt Multiply (int X, int Y)
- {
--    fInt A, B, Product;
-+	fInt A, B, Product;
- 
--    A.full = X << SHIFT_AMOUNT;
--    B.full = Y << SHIFT_AMOUNT;
-+	A.full = X << SHIFT_AMOUNT;
-+	B.full = Y << SHIFT_AMOUNT;
- 
--    Product = fMultiply(A, B);
-+	Product = fMultiply(A, B);
- 
--    return Product;
-+	return Product;
- }
-+
- fInt Divide (int X, int Y)
- {
--    fInt A, B, Quotient;
-+	fInt A, B, Quotient;
- 
--    A.full = X << SHIFT_AMOUNT;
--    B.full = Y << SHIFT_AMOUNT;
-+	A.full = X << SHIFT_AMOUNT;
-+	B.full = Y << SHIFT_AMOUNT;
- 
--    Quotient = fDivide(A, B);
-+	Quotient = fDivide(A, B);
- 
--    return Quotient;
-+	return Quotient;
- }
- 
- int uGetScaledDecimal (fInt A) /*Converts the fractional portion to whole integers - Costly function */
-@@ -563,16 +561,13 @@ int uGetScaledDecimal (fInt A) /*Converts the fractional portion to whole intege
- 	int i, scaledDecimal = 0, tmp = A.partial.decimal;
- 
- 	for (i = 0; i < PRECISION; i++) {
--        dec[i] = tmp / (1 << SHIFT_AMOUNT);
--
--        tmp = tmp - ((1 << SHIFT_AMOUNT)*dec[i]);
--
--        tmp *= 10;
--
--        scaledDecimal = scaledDecimal + dec[i]*uPow(10, PRECISION - 1 -i);
--    }
-+		dec[i] = tmp / (1 << SHIFT_AMOUNT);
-+		tmp = tmp - ((1 << SHIFT_AMOUNT)*dec[i]);
-+		tmp *= 10;
-+		scaledDecimal = scaledDecimal + dec[i]*uPow(10, PRECISION - 1 -i);
-+	}
- 
--    return scaledDecimal;
-+	return scaledDecimal;
- }
- 
- int uPow(int base, int power)
-@@ -601,17 +596,17 @@ int uAbs(int X)
- 
- fInt fRoundUpByStepSize(fInt A, fInt fStepSize, bool error_term)
- {
--    fInt solution;
-+	fInt solution;
- 
--    solution = fDivide(A, fStepSize);
--    solution.partial.decimal = 0; /*All fractional digits changes to 0 */
-+	solution = fDivide(A, fStepSize);
-+	solution.partial.decimal = 0; /*All fractional digits changes to 0 */
- 
--    if (error_term)
--        solution.partial.real += 1; /*Error term of 1 added */
-+	if (error_term)
-+		solution.partial.real += 1; /*Error term of 1 added */
- 
--    solution = fMultiply(solution, fStepSize);
--    solution = fAdd(solution, fStepSize);
-+	solution = fMultiply(solution, fStepSize);
-+	solution = fAdd(solution, fStepSize);
- 
--    return solution;
-+	return solution;
- }
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-index 45997e6..21c31db 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-@@ -228,9 +228,9 @@ int fiji_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
- 	}
- 
- 	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
--    SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
- 
--    return 0;
-+	return 0;
- }
- 
- /**
-@@ -557,7 +557,7 @@ static int fiji_request_smu_specific_fw_load(struct pp_smumgr *smumgr, uint32_t
- 	/* For non-virtualization cases,
- 	 * SMU loads all FWs at once in fiji_request_smu_load_fw.
- 	 */
--    return 0;
-+	return 0;
- }
- 
- static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
-@@ -723,7 +723,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
- 	/* clear reset */
- 	cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
- 
--    return result;
-+	return result;
- }
- 
- int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0154-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch b/common/recipes-kernel/linux/files/0154-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch
deleted file mode 100644
index f81d2a38..00000000
--- a/common/recipes-kernel/linux/files/0154-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch
+++ /dev/null
@@ -1,397 +0,0 @@
-From 2ab364254ca34fc25e5c8523c5f1835aa30e92a9 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 6 Jan 2016 16:48:38 +0800
-Subject: [PATCH 0154/1110] drm/amd/powerplay: fix Smatch static checker
- warnings
-
-1. return -1 instead of -ENOMEM
-2. The struct type mismatch warnings.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  2 +-
- .../gpu/drm/amd/powerplay/hwmgr/functiontables.c   | 13 +++++-----
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |  3 +++
- .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  | 11 +++++++-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  | 30 +++++++++++++---------
- .../amd/powerplay/hwmgr/tonga_processpptables.c    | 20 +++++++--------
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  2 +-
- .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    |  2 +-
- 8 files changed, 51 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 6dba5bf..3f3009d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -914,7 +914,7 @@ static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
- 			GFP_KERNEL);
- 
- 	if (NULL == table)
--		return -EINVAL;
-+		return -ENOMEM;
- 
- 	table->mask_low = vol_table->mask_low;
- 	table->phase_delay = vol_table->phase_delay;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-index 5abde8f..9deadab 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-@@ -66,7 +66,7 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr,
- 		temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
- 		if (temp_storage == NULL) {
- 			printk(KERN_ERR "[ powerplay ] Could not allocate table temporary storage\n");
--			return -1;
-+			return -ENOMEM;
- 		}
- 	}
- 
-@@ -90,7 +90,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
- 
- 	if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
- 		printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n");
--		return -1;
-+		return -EINVAL;
- 	}
- 
- 	for (table_item = master_table->master_list;
-@@ -102,8 +102,9 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
- 
- 	size = (function_count + 1) * sizeof(phm_table_function);
- 	run_time_list = kzalloc(size, GFP_KERNEL);
-+
- 	if (NULL == run_time_list)
--		return -1;
-+		return -ENOMEM;
- 
- 	rtf = run_time_list;
- 	for (table_item = master_table->master_list;
-@@ -111,7 +112,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
- 		if ((rtf - run_time_list) > function_count) {
- 			printk(KERN_ERR "[ powerplay ] Check function results have changed\n");
- 			kfree(run_time_list);
--			return -1;
-+			return -EINVAL;
- 		}
- 
- 		if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
-@@ -123,7 +124,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
- 	if ((rtf - run_time_list) > function_count) {
- 		printk(KERN_ERR "[ powerplay ] Check function results have changed\n");
- 		kfree(run_time_list);
--		return -1;
-+		return -EINVAL;
- 	}
- 
- 	*rtf = NULL;
-@@ -138,7 +139,7 @@ int phm_destroy_table(struct pp_hwmgr *hwmgr,
- {
- 	if (hwmgr == NULL || rt_table == NULL) {
- 		printk(KERN_ERR "[ powerplay ] Invalid Parameter\n");
--		return -1;
-+		return -EINVAL;
- 	}
- 
- 	if (NULL == rt_table->function_list)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index ca4554b..5fb98aa 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -111,6 +111,9 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
- 
- 	hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
- 
-+	if (hwmgr->ps == NULL)
-+		return -ENOMEM;
-+
- 	state = hwmgr->ps;
- 
- 	for (i = 0; i < table_entries; i++) {
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-index 8f9d705..2f1a14f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
-@@ -1322,11 +1322,17 @@ static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
- 	struct phm_cac_leakage_table  *cac_leakage_table;
- 	unsigned long            table_size, i;
- 
-+	if (hwmgr == NULL || table == NULL || ptable == NULL)
-+		return -EINVAL;
-+
- 	table_size = sizeof(ULONG) +
- 		(sizeof(struct phm_cac_leakage_table) * table->ucNumEntries);
- 
- 	cac_leakage_table = kzalloc(table_size, GFP_KERNEL);
- 
-+	if (cac_leakage_table == NULL)
-+		return -ENOMEM;
-+
- 	cac_leakage_table->count = (ULONG)table->ucNumEntries;
- 
- 	for (i = 0; i < cac_leakage_table->count; i++) {
-@@ -1349,7 +1355,7 @@ static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
- static int get_platform_power_management_table(struct pp_hwmgr *hwmgr,
- 			ATOM_PPLIB_PPM_Table *atom_ppm_table)
- {
--	struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_PPLIB_PPM_Table), GFP_KERNEL);
-+	struct phm_ppm_table *ptr = kzalloc(sizeof(struct phm_ppm_table), GFP_KERNEL);
- 
- 	if (NULL == ptr)
- 		return -ENOMEM;
-@@ -1466,6 +1472,9 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
- 
- 			table = kzalloc(size, GFP_KERNEL);
- 
-+			if (table == NULL)
-+				return -ENOMEM;
-+
- 			table->count = (unsigned long)ptable->ucNumEntries;
- 
- 			for (i = 0; i < table->count; i++) {
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 3cb5d04..0b188d1 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -115,9 +115,12 @@ const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
- struct tonga_power_state *cast_phw_tonga_power_state(
- 				  struct pp_hw_power_state *hw_ps)
- {
-+	if (hw_ps == NULL)
-+		return NULL;
-+
- 	PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
- 				"Invalid Powerstate Type!",
--				 return NULL;);
-+				 return NULL);
- 
- 	return (struct tonga_power_state *)hw_ps;
- }
-@@ -125,9 +128,12 @@ struct tonga_power_state *cast_phw_tonga_power_state(
- const struct tonga_power_state *cast_const_phw_tonga_power_state(
- 				 const struct pp_hw_power_state *hw_ps)
- {
-+	if (hw_ps == NULL)
-+		return NULL;
-+
- 	PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
- 				"Invalid Powerstate Type!",
--				 return NULL;);
-+				 return NULL);
- 
- 	return (const struct tonga_power_state *)hw_ps;
- }
-@@ -1678,9 +1684,9 @@ static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
- 		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
- 		//CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
--    }
-+	}
- 
--    return result;
-+	return result;
- 
- }
- 
-@@ -1719,7 +1725,7 @@ static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- 		PP_ASSERT_WITH_CODE((0 == result),
- 				"can not find divide id for VCE engine clock", return result);
- 
--		table->VceLevel[count].Divider    = (uint8_t)dividers.pll_post_divider;
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
- 
- 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
- 	}
-@@ -1804,7 +1810,7 @@ static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- 		PP_ASSERT_WITH_CODE((0 == result),
- 			"can not find divide id for samu clock", return result);
- 
--		table->SamuLevel[count].Divider     = (uint8_t)dividers.pll_post_divider;
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
- 
- 		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
- 	}
-@@ -1847,7 +1853,7 @@ static int tonga_calculate_mclk_params(
- 		"Error retrieving Memory Clock Parameters from VBIOS.", return result);
- 
- 	/* MPLL_FUNC_CNTL setup*/
--	mpll_func_cntl    = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
-+	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
- 
- 	/* MPLL_FUNC_CNTL_1 setup*/
- 	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-@@ -3864,6 +3870,7 @@ int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_to
- 				table->mc_reg_table_entry[i].mc_data[j];
- 		}
- 	}
-+
- 	ni_table->num_entries = table->num_entries;
- 
- 	return 0;
-@@ -3989,7 +3996,7 @@ int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
- 	table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
- 
- 	if (NULL == table)
--		return -1;
-+		return -ENOMEM;
- 
- 	/* Program additional LP registers that are no longer programmed by VBIOS */
- 	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-@@ -5470,7 +5477,6 @@ static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const vo
- 	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 	const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
- 
--
- 	result = tonga_trim_dpm_states(hwmgr, tonga_ps);
- 	if (0 != result)
- 		return result;
-@@ -5732,7 +5738,7 @@ static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_
- 	if (phm_is_hw_access_blocked(hwmgr))
- 		return 0;
- 
--    return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -EINVAL);
-+	return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
- }
- 
- int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
-@@ -5826,7 +5832,7 @@ static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_
- 	if (phm_is_hw_access_blocked(hwmgr))
- 		return 0;
- 
--	return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -EINVAL);
-+	return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
- }
- 
- uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
-@@ -5962,7 +5968,7 @@ int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_st
- 	const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
- 	int i;
- 
--	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
-+	if (equal == NULL || psa == NULL || psb == NULL)
- 		return -EINVAL;
- 
- 	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index ae216fe..34f4bef 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -168,7 +168,7 @@ static int get_vddc_lookup_table(
- 		kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(table, 0x00, table_size);
- 
-@@ -206,7 +206,7 @@ static int get_platform_power_management_table(
- 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
- 
- 	if (NULL == ptr)
--		return -1;
-+		return -ENOMEM;
- 
- 	ptr->ppm_design
- 		= atom_ppm_table->ucPpmDesign;
-@@ -327,7 +327,7 @@ static int get_valid_clk(
- 	table = (struct phm_clock_array *)kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(table, 0x00, table_size);
- 
-@@ -378,7 +378,7 @@ static int get_mclk_voltage_dependency_table(
- 		kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == mclk_table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(mclk_table, 0x00, table_size);
- 
-@@ -421,7 +421,7 @@ static int get_sclk_voltage_dependency_table(
- 		kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == sclk_table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(sclk_table, 0x00, table_size);
- 
-@@ -464,7 +464,7 @@ static int get_pcie_table(
- 	pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == pcie_table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(pcie_table, 0x00, table_size);
- 
-@@ -506,14 +506,14 @@ static int get_cac_tdp_table(
- 	tdp_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == tdp_table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(tdp_table, 0x00, table_size);
- 
- 	hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == hwmgr->dyn_state.cac_dtp_table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
- 
-@@ -614,7 +614,7 @@ static int get_mm_clock_voltage_table(
- 		kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == mm_table)
--		return -1;
-+		return -ENOMEM;
- 
- 	memset(mm_table, 0x00, table_size);
- 
-@@ -943,7 +943,7 @@ int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr)
- 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
- 
- 	PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
--			    "Failed to allocate hwmgr->pptable!", return -1);
-+			    "Failed to allocate hwmgr->pptable!", return -ENOMEM);
- 
- 	memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-index 21c31db..cdbb9f8 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-@@ -1033,7 +1033,7 @@ int fiji_smum_init(struct pp_smumgr *smumgr)
- 	fiji_smu = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
- 
- 	if (fiji_smu == NULL)
--		return -1;
-+		return -ENOMEM;
- 
- 	smumgr->backend = fiji_smu;
- 	smumgr->smumgr_funcs = &fiji_smu_funcs;
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-index 62ff760..d166fd9 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-@@ -810,7 +810,7 @@ int tonga_smum_init(struct pp_smumgr *smumgr)
- 	tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
- 
- 	if (tonga_smu == NULL)
--		return -1;
-+		return -ENOMEM;
- 
- 	smumgr->backend = tonga_smu;
- 	smumgr->smumgr_funcs = &tonga_smu_funcs;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0155-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch b/common/recipes-kernel/linux/files/0155-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch
deleted file mode 100644
index c941f6e1..00000000
--- a/common/recipes-kernel/linux/files/0155-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 7995b11e4c858d71cc003bfb61abf4341138100c Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 13:56:03 +0800
-Subject: [PATCH 0155/1110] drm/amd/powerplay: add powerplay valid check to
- avoid null point. (v2)
-
-In case CONFIG_DRM_AMD_POWERPLAY is defined and amdgpu.powerplay=0.
-some functions in powrplay can also be called by DAL. and the input parameter is *adev.
-if just check point not NULL was not enough and will lead to NULL point error.
-
-V2: AGD: rebase on upstream
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c   | 15 ++++++++++++---
- drivers/gpu/drm/amd/powerplay/inc/pp_instance.h |  3 +++
- 2 files changed, 15 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index db0370b..2764bd3 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -30,6 +30,12 @@
- #include "power_state.h"
- #include "eventmanager.h"
- 
-+#define PP_CHECK(handle)						\
-+	do {								\
-+		if ((handle) == NULL || (handle)->pp_valid != PP_VALID)	\
-+			return -EINVAL;					\
-+	} while (0)
-+
- static int pp_early_init(void *handle)
- {
- 	return 0;
-@@ -537,6 +543,8 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init,
- 	if (handle == NULL)
- 		return -ENOMEM;
- 
-+	handle->pp_valid = PP_VALID;
-+
- 	ret = smum_init(pp_init, handle);
- 	if (ret)
- 		goto fail_smum;
-@@ -611,8 +619,7 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input)
- 	struct pp_hwmgr  *hwmgr;
- 	const struct amd_pp_display_configuration *display_config = input;
- 
--	if (handle == NULL)
--		return -EINVAL;
-+	PP_CHECK((struct pp_instance *)handle);
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
-@@ -625,7 +632,9 @@ int amd_powerplay_get_display_power_level(void *handle,
- {
- 	struct pp_hwmgr  *hwmgr;
- 
--	if (handle == NULL || output == NULL)
-+	PP_CHECK((struct pp_instance *)handle);
-+
-+	if (output == NULL)
- 		return -EINVAL;
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-index 7b60b61..4d8ed1f 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
-@@ -27,7 +27,10 @@
- #include "hwmgr.h"
- #include "eventmgr.h"
- 
-+#define PP_VALID  0x1F1F1F1F
-+
- struct pp_instance {
-+	uint32_t pp_valid;
- 	struct pp_smumgr *smu_mgr;
- 	struct pp_hwmgr *hwmgr;
- 	struct pp_eventmgr *eventmgr;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0156-drm-amd-powerplay-Reload-and-initialize-the-smc-firm.patch b/common/recipes-kernel/linux/files/0156-drm-amd-powerplay-Reload-and-initialize-the-smc-firm.patch
deleted file mode 100644
index 9957fc28..00000000
--- a/common/recipes-kernel/linux/files/0156-drm-amd-powerplay-Reload-and-initialize-the-smc-firm.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From b4d418567a702f0b0eaee9a9fe1cc4d232eb020a Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 10:25:19 +0800
-Subject: [PATCH 0156/1110] drm/amd/powerplay: Reload and initialize the smc
- firmware on powerplay resume.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 2764bd3..8f5d5ed 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -203,13 +203,29 @@ static int pp_resume(void *handle)
- 	struct pp_instance *pp_handle;
- 	struct pp_eventmgr *eventmgr;
- 	struct pem_event_data event_data = { {0} };
-+	struct pp_smumgr *smumgr;
-+	int ret;
- 
- 	if (handle == NULL)
- 		return -EINVAL;
- 
- 	pp_handle = (struct pp_instance *)handle;
-+	smumgr = pp_handle->smu_mgr;
-+
-+	if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
-+		smumgr->smumgr_funcs->start_smu == NULL)
-+		return -EINVAL;
-+
-+	ret = smumgr->smumgr_funcs->start_smu(smumgr);
-+	if (ret) {
-+		printk(KERN_ERR "[ powerplay ] smc start failed\n");
-+		smumgr->smumgr_funcs->smu_fini(smumgr);
-+		return ret;
-+	}
-+
- 	eventmgr = pp_handle->eventmgr;
- 	pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
-+
- 	return 0;
- }
- 
-@@ -624,6 +640,7 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input)
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
- 	phm_store_dal_configuration_data(hwmgr, display_config);
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0157-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch b/common/recipes-kernel/linux/files/0157-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch
deleted file mode 100644
index 1c8a1bc4..00000000
--- a/common/recipes-kernel/linux/files/0157-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From c86985f31f1598cee0b6ab9aa299b3ccee22bcfd Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 6 Jan 2016 17:08:46 +0800
-Subject: [PATCH 0157/1110] drm/amdgpu: Show gpu load when display gpu
- performance for Ci.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 57a2e34..8b4731d 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -1395,7 +1395,6 @@ static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
- 		ci_fan_ctrl_set_default_mode(adev);
- }
- 
--#if 0
- static int ci_read_smc_soft_register(struct amdgpu_device *adev,
- 				     u16 reg_offset, u32 *value)
- {
-@@ -1405,7 +1404,6 @@ static int ci_read_smc_soft_register(struct amdgpu_device *adev,
- 				      pi->soft_regs_start + reg_offset,
- 				      value, pi->sram_end);
- }
--#endif
- 
- static int ci_write_smc_soft_register(struct amdgpu_device *adev,
- 				      u16 reg_offset, u32 value)
-@@ -6084,11 +6082,23 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
- 	struct amdgpu_ps *rps = &pi->current_rps;
- 	u32 sclk = ci_get_average_sclk_freq(adev);
- 	u32 mclk = ci_get_average_mclk_freq(adev);
-+	u32 activity_percent = 50;
-+	int ret;
-+
-+	ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
-+					&activity_percent);
-+
-+	if (ret == 0) {
-+		activity_percent += 0x80;
-+		activity_percent >>= 8;
-+		activity_percent = activity_percent > 100 ? 100 : activity_percent;
-+	}
- 
- 	seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
- 	seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
- 	seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
- 		   sclk, mclk);
-+	seq_printf(m, "GPU load: %u %%\n", activity_percent);
- }
- 
- static void ci_dpm_print_power_state(struct amdgpu_device *adev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0158-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch b/common/recipes-kernel/linux/files/0158-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch
deleted file mode 100644
index 7bf43b1c..00000000
--- a/common/recipes-kernel/linux/files/0158-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 512194a7d7c12f2cf0988ccfb6b423087c4420ff Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 6 Jan 2016 17:15:59 +0800
-Subject: [PATCH 0158/1110] drm/amdgpu: Show gpu load when display gpu
- performance for Fiji of VI.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 3f3009d..28031a7 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -4866,7 +4866,9 @@ static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
- static void fiji_print_current_perforce_level(
- 		struct pp_hwmgr *hwmgr, struct seq_file *m)
- {
--	uint32_t sclk, mclk;
-+	uint32_t sclk, mclk, activity_percent = 0;
-+	uint32_t offset;
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- 
- 	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
- 
-@@ -4877,6 +4879,13 @@ static void fiji_print_current_perforce_level(
- 	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
- 			mclk / 100, sclk / 100);
-+
-+	offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
-+	activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
-+	activity_percent += 0x80;
-+	activity_percent >>= 8;
-+
-+	seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
- }
- 
- static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0159-drm-amdgpu-fix-hex-decimal-bug-when-show-gpu-load.patch b/common/recipes-kernel/linux/files/0159-drm-amdgpu-fix-hex-decimal-bug-when-show-gpu-load.patch
deleted file mode 100644
index c429dc93..00000000
--- a/common/recipes-kernel/linux/files/0159-drm-amdgpu-fix-hex-decimal-bug-when-show-gpu-load.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From cd3b78731694227e708756b3765367284f685184 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 6 Jan 2016 17:17:53 +0800
-Subject: [PATCH 0159/1110] drm/amdgpu: fix hex/decimal bug when show gpu load.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c    | 10 +++++-----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 10 +++++-----
- 2 files changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index c0e6aae..65ad24a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1494,7 +1494,7 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 	uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
- 					TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
- 
--	uint32_t sclk, vclk, dclk, ecclk, tmp, active_percent;
-+	uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
- 	uint16_t vddnb, vddgfx;
- 	int result;
- 
-@@ -1536,13 +1536,13 @@ cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 
- 	result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
- 	if (0 == result) {
--		active_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
--		active_percent = active_percent > 100 ? 100 : active_percent;
-+		activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
-+		activity_percent = activity_percent > 100 ? 100 : activity_percent;
- 	} else {
--		active_percent = 50;
-+		activity_percent = 50;
- 	}
- 
--	seq_printf(m, "\n [GPU load]: %u %%\n\n", active_percent);
-+	seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
- }
- 
- static void cz_hw_print_display_cfg(
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 0b188d1..44a9250 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -5157,7 +5157,7 @@ static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
- static void
- tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- {
--	uint32_t sclk, mclk, active_percent;
-+	uint32_t sclk, mclk, activity_percent;
- 	uint32_t offset;
- 	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 
-@@ -5172,11 +5172,11 @@ tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 
- 
- 	offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
--	active_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
--	active_percent += 80;
--	active_percent >>= 8;
-+	activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
-+	activity_percent += 0x80;
-+	activity_percent >>= 8;
- 
--	seq_printf(m, "\n [GPU load]: %u%%\n\n", active_percent > 100 ? 100 : active_percent);
-+	seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
- 
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0160-drm-amd-powerplay-add-thermal-control-task-when-resu.patch b/common/recipes-kernel/linux/files/0160-drm-amd-powerplay-add-thermal-control-task-when-resu.patch
deleted file mode 100644
index b350679e..00000000
--- a/common/recipes-kernel/linux/files/0160-drm-amd-powerplay-add-thermal-control-task-when-resu.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 71f606b03d98b2d1668759711b1128b8b3093a1f Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 11:23:57 +0800
-Subject: [PATCH 0160/1110] drm/amd/powerplay: add thermal control task when
- resume.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-index 9458394..83be3cf 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -143,6 +143,7 @@ static const pem_event_action *resume_event[] = {
- 	enable_dynamic_state_management_tasks,
- 	enable_clock_power_gatings_tasks,
- 	enable_disable_bapm_tasks,
-+	initialize_thermal_controller_tasks,
- 	reset_boot_state_tasks,
- 	adjust_power_state_tasks,
- 	enable_disable_fps_tasks,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0161-drm-amd-powerplay-enable-set-boot-state-task.patch b/common/recipes-kernel/linux/files/0161-drm-amd-powerplay-enable-set-boot-state-task.patch
deleted file mode 100644
index de4c3c5b..00000000
--- a/common/recipes-kernel/linux/files/0161-drm-amd-powerplay-enable-set-boot-state-task.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From ed9a7b03d59b9953acb0843c9cb06279d086f12b Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 11:19:14 +0800
-Subject: [PATCH 0161/1110] drm/amd/powerplay: enable set boot state task
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c | 6 ++++--
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.c        | 3 +--
- drivers/gpu/drm/amd/powerplay/eventmgr/psm.h        | 2 +-
- 3 files changed, 6 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index f0700d0..f0b4491 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -74,7 +74,9 @@ int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data
- 
- int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
--	/* TODO */
-+	if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID))
-+		return psm_set_states(eventmgr, &(event_data->requested_state_id));
-+
- 	return 0;
- }
- 
-@@ -343,7 +345,7 @@ int pem_task_disable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_e
- int pem_task_set_performance_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
- 	if (pem_is_event_data_valid(event_data->valid_fields, PEM_EventDataValid_RequestedStateID))
--		return psm_set_performance_states(eventmgr, &(event_data->requested_state_id));
-+		return psm_set_states(eventmgr, &(event_data->requested_state_id));
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-index 5740fbf..a46225c 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
-@@ -62,7 +62,7 @@ int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateC
- 	return -1;
- }
- 
--int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *state_id)
-+int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id)
- {
- 	struct pp_power_state *state;
- 	int table_entries;
-@@ -82,7 +82,6 @@ int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *stat
- 	return -1;
- }
- 
--
- int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
- {
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-index 1380470..fbdff3e 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.h
-@@ -31,7 +31,7 @@ int psm_get_ui_state(struct pp_eventmgr *eventmgr, enum PP_StateUILabel ui_label
- 
- int psm_get_state_by_classification(struct pp_eventmgr *eventmgr, enum PP_StateClassificationFlag flag, unsigned long *state_id);
- 
--int psm_set_performance_states(struct pp_eventmgr *eventmgr, unsigned long *state_id);
-+int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id);
- 
- int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0162-drm-amd-powerplay-enable-power-down-asic-task.-v2.patch b/common/recipes-kernel/linux/files/0162-drm-amd-powerplay-enable-power-down-asic-task.-v2.patch
deleted file mode 100644
index 728abd22..00000000
--- a/common/recipes-kernel/linux/files/0162-drm-amd-powerplay-enable-power-down-asic-task.-v2.patch
+++ /dev/null
@@ -1,108 +0,0 @@
-From 34d7662a9fa8167b7375ad0d58e43b48ad182b75 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 11:22:34 +0800
-Subject: [PATCH 0162/1110] drm/amd/powerplay: enable power down asic task.
- (v2)
-
-v2: AGD: rebase on upstream
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c   |  3 +--
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 17 ++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   |  2 ++
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h             |  6 ++++--
- 4 files changed, 23 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-index f0b4491..5cd1234 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
-@@ -68,8 +68,7 @@ int pem_task_adjust_power_state(struct pp_eventmgr *eventmgr, struct pem_event_d
- 
- int pem_task_power_down_asic(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
- {
--	/* TODO */
--	return 0;
-+	return phm_power_down_asic(eventmgr->hwmgr);
- }
- 
- int pem_task_set_boot_state(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index f9bf4fc..0f2d5e4 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -90,6 +90,22 @@ int phm_setup_asic(struct pp_hwmgr *hwmgr)
- 	return 0;
- }
- 
-+int phm_power_down_asic(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_TablelessHardwareInterface)) {
-+		if (NULL != hwmgr->hwmgr_func->power_off_asic)
-+			return hwmgr->hwmgr_func->power_off_asic(hwmgr);
-+	} else {
-+		return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
-+					  NULL, NULL);
-+	}
-+
-+	return 0;
-+}
-+
- int phm_set_power_state(struct pp_hwmgr *hwmgr,
- 		    const struct pp_hw_power_state *pcurrent_state,
- 		    const struct pp_hw_power_state *pnew_power_state)
-@@ -247,7 +263,6 @@ int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
- */
- int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
- {
--
- 	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
- }
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index a503306..91795ef 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -379,5 +379,7 @@ extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
- 
- extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
- 
-+extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
-+
- #endif /* _HARDWARE_MANAGER_H_ */
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index eb0f1b2..aeaa3db 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -325,7 +325,8 @@ struct pp_hwmgr_func {
- 				bool cc6_disable, bool pstate_disable,
- 				bool pstate_switch_disable);
- 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
--			struct amd_pp_dal_clock_info*info);
-+				   struct amd_pp_dal_clock_info *info);
-+	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
- };
- 
- struct pp_table_func {
-@@ -576,9 +577,10 @@ struct pp_hwmgr {
- 	void *pptable;
- 	struct phm_platform_descriptor platform_descriptor;
- 	void *backend;
--	enum PP_DAL_POWERLEVEL	dal_power_level;
-+	enum PP_DAL_POWERLEVEL dal_power_level;
- 	struct phm_dynamic_state_info dyn_state;
- 	struct phm_runtime_table_header setup_asic;
-+	struct phm_runtime_table_header power_down_asic;
- 	struct phm_runtime_table_header disable_dynamic_state_management;
- 	struct phm_runtime_table_header enable_dynamic_state_management;
- 	struct phm_runtime_table_header set_power_state;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0163-drm-amd-powerplay-implement-power-down-asic-task-for.patch b/common/recipes-kernel/linux/files/0163-drm-amd-powerplay-implement-power-down-asic-task-for.patch
deleted file mode 100644
index 376ff2c3..00000000
--- a/common/recipes-kernel/linux/files/0163-drm-amd-powerplay-implement-power-down-asic-task-for.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 132c681a86fa6085110da5ad62ec973c1d2fd07e Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 11:23:16 +0800
-Subject: [PATCH 0163/1110] drm/amd/powerplay: implement power down asic task
- for CZ
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 55 ++++++++++++++++++++++++++
- 1 file changed, 55 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 65ad24a..0874ab4 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -925,6 +925,54 @@ static struct phm_master_table_header cz_setup_asic_master = {
- 	cz_setup_asic_list
- };
- 
-+static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+	hw_data->disp_clk_bypass_pending = false;
-+	hw_data->disp_clk_bypass = false;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+	hw_data->is_nb_dpm_enabled = false;
-+
-+	return 0;
-+}
-+
-+static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
-+					void *input, void *output,
-+					void *storage, int result)
-+{
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	hw_data->cc6_settings.cc6_setting_changed = false;
-+	hw_data->cc6_settings.cpu_pstate_separation_time = 0;
-+	hw_data->cc6_settings.cpu_cc6_disable = false;
-+	hw_data->cc6_settings.cpu_pstate_disable = false;
-+
-+	return 0;
-+}
-+
-+static struct phm_master_table_item cz_power_down_asic_list[] = {
-+	{NULL, cz_tf_power_up_display_clock_sys_pll},
-+	{NULL, cz_tf_clear_nb_dpm_flag},
-+	{NULL, cz_tf_reset_cc6_data},
-+	{NULL, NULL}
-+};
-+
-+static struct phm_master_table_header cz_power_down_asic_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	cz_power_down_asic_list
-+};
-+
- static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
- 				void *output, void *storage, int result)
- {
-@@ -1126,6 +1174,13 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 		return result;
- 	}
- 
-+	result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
-+				&(hwmgr->power_down_asic));
-+	if (result != 0) {
-+		printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
-+		return result;
-+	}
-+
- 	result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
- 				&(hwmgr->disable_dynamic_state_management));
- 	if (result != 0) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0164-drm-amdgpu-add-warning-to-amdgpu_bo_gpu_offset-v2.patch b/common/recipes-kernel/linux/files/0164-drm-amdgpu-add-warning-to-amdgpu_bo_gpu_offset-v2.patch
deleted file mode 100644
index 9d1d0487..00000000
--- a/common/recipes-kernel/linux/files/0164-drm-amdgpu-add-warning-to-amdgpu_bo_gpu_offset-v2.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From c9fe183d1d8401a3ded4952eda78d058241224b4 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 15 Dec 2015 11:10:30 +0100
-Subject: [PATCH 0164/1110] drm/amdgpu: add warning to amdgpu_bo_gpu_offset()
- v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Check if there really is a valid offset for the BO.
-
-v2: user WARN_ON_ONCE
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-index ea756e7..5107fb2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-@@ -96,6 +96,7 @@ static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
-  */
- static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
- {
-+	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
- 	return bo->tbo.offset;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0165-drm-amdgpu-cgs-add-an-interface-to-access-PCI-resour.patch b/common/recipes-kernel/linux/files/0165-drm-amdgpu-cgs-add-an-interface-to-access-PCI-resour.patch
deleted file mode 100644
index 22cdb803..00000000
--- a/common/recipes-kernel/linux/files/0165-drm-amdgpu-cgs-add-an-interface-to-access-PCI-resour.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From 93e9aeba60043dc107c2a58e6b2d8a9a59cb603e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 23 Dec 2015 11:25:43 -0500
-Subject: [PATCH 0165/1110] drm/amdgpu/cgs: add an interface to access PCI
- resources
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This provides an interface to get access to the base address
-of PCI resources (MMIO, DOORBELL, etc.).  Only MMIO and
-DOORBELL are implemented right now.  This is necessary to
-properly utilize shared drivers on platform devices.  IP
-modules can use this interface to get the base address
-of the resource and add any additional offset and set the
-size when setting up the platform driver(s).
-
-Acked-by: Dave Airlie <airlied@redhat.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 36 ++++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/include/cgs_common.h | 34 ++++++++++++++++++++++++++++++
- 2 files changed, 70 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 59485d0..a081dda 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -398,6 +398,41 @@ static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
- 	WARN(ret, "pci_write_config_dword error");
- }
- 
-+
-+static int amdgpu_cgs_get_pci_resource(void *cgs_device,
-+				       enum cgs_resource_type resource_type,
-+				       uint64_t size,
-+				       uint64_t offset,
-+				       uint64_t *resource_base)
-+{
-+	CGS_FUNC_ADEV;
-+
-+	if (resource_base == NULL)
-+		return -EINVAL;
-+
-+	switch (resource_type) {
-+	case CGS_RESOURCE_TYPE_MMIO:
-+		if (adev->rmmio_size == 0)
-+			return -ENOENT;
-+		if ((offset + size) > adev->rmmio_size)
-+			return -EINVAL;
-+		*resource_base = adev->rmmio_base;
-+		return 0;
-+	case CGS_RESOURCE_TYPE_DOORBELL:
-+		if (adev->doorbell.size == 0)
-+			return -ENOENT;
-+		if ((offset + size) > adev->doorbell.size)
-+			return -EINVAL;
-+		*resource_base = adev->doorbell.base;
-+		return 0;
-+	case CGS_RESOURCE_TYPE_FB:
-+	case CGS_RESOURCE_TYPE_IO:
-+	case CGS_RESOURCE_TYPE_ROM:
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
- static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
- 						  unsigned table, uint16_t *size,
- 						  uint8_t *frev, uint8_t *crev)
-@@ -1041,6 +1076,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
- 	amdgpu_cgs_write_pci_config_byte,
- 	amdgpu_cgs_write_pci_config_word,
- 	amdgpu_cgs_write_pci_config_dword,
-+	amdgpu_cgs_get_pci_resource,
- 	amdgpu_cgs_atom_get_data_table,
- 	amdgpu_cgs_atom_get_cmd_table_revs,
- 	amdgpu_cgs_atom_exec_cmd_table,
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 03affb3..713aec9 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -122,6 +122,17 @@ struct cgs_system_info {
- 	uint64_t               padding[13];
- };
- 
-+/*
-+ * enum cgs_resource_type - GPU resource type
-+ */
-+enum cgs_resource_type {
-+	CGS_RESOURCE_TYPE_MMIO = 0,
-+	CGS_RESOURCE_TYPE_FB,
-+	CGS_RESOURCE_TYPE_IO,
-+	CGS_RESOURCE_TYPE_DOORBELL,
-+	CGS_RESOURCE_TYPE_ROM,
-+};
-+
- /**
-  * struct cgs_clock_limits - Clock limits
-  *
-@@ -417,6 +428,23 @@ typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
- typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
- 					     uint32_t value);
- 
-+
-+/**
-+ * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
-+ * @cgs_device:	opaque device handle
-+ * @resource_type:	Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
-+ * @size:	size of the region
-+ * @offset:	offset from the start of the region
-+ * @resource_base:	base address (not including offset) returned
-+ *
-+ * Return: 0 on success, -errno otherwise
-+ */
-+typedef int (*cgs_get_pci_resource_t)(void *cgs_device,
-+				      enum cgs_resource_type resource_type,
-+				      uint64_t size,
-+				      uint64_t offset,
-+				      uint64_t *resource_base);
-+
- /**
-  * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
-  * @cgs_device:	opaque device handle
-@@ -593,6 +621,8 @@ struct cgs_ops {
- 	cgs_write_pci_config_byte_t write_pci_config_byte;
- 	cgs_write_pci_config_word_t write_pci_config_word;
- 	cgs_write_pci_config_dword_t write_pci_config_dword;
-+	/* PCI resources */
-+	cgs_get_pci_resource_t get_pci_resource;
- 	/* ATOM BIOS */
- 	cgs_atom_get_data_table_t atom_get_data_table;
- 	cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
-@@ -708,5 +738,9 @@ struct cgs_device
- 	CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
- #define cgs_query_system_info(dev, sys_info)	\
- 	CGS_CALL(query_system_info, dev, sys_info)
-+#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
-+	resource_base) \
-+	CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
-+	resource_base)
- 
- #endif /* _CGS_COMMON_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0166-drm-amdgpu-add-irq-domain-support.patch b/common/recipes-kernel/linux/files/0166-drm-amdgpu-add-irq-domain-support.patch
deleted file mode 100644
index f4567662..00000000
--- a/common/recipes-kernel/linux/files/0166-drm-amdgpu-add-irq-domain-support.patch
+++ /dev/null
@@ -1,296 +0,0 @@
-From 217188dcdf9dd0d228954f3b7379a1172d0cf0ff Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 6 Nov 2015 01:29:08 -0500
-Subject: [PATCH 0166/1110] drm/amdgpu: add irq domain support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Hardware blocks on the GPU like ACP generate interrupts in
-the GPU interrupt controller, but are driven by a separate
-driver.  Add an irq domain to the GPU driver so that
-blocks like ACP can register a Linux interrupt.
-
-Acked-by: Dave Airlie <airlied@redhat.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 108 +++++++++++++++++++++++++++++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h |   9 +++
- drivers/gpu/drm/amd/amdgpu/cik_ih.c     |   6 ++
- drivers/gpu/drm/amd/amdgpu/cz_ih.c      |   7 +++
- drivers/gpu/drm/amd/amdgpu/iceland_ih.c |   7 +++
- drivers/gpu/drm/amd/amdgpu/tonga_ih.c   |   7 +++
- 6 files changed, 136 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 7c42ff6..3006182 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -312,6 +312,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
- 	}
- 
- 	adev->irq.sources[src_id] = source;
-+
- 	return 0;
- }
- 
-@@ -335,15 +336,19 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
- 		return;
- 	}
- 
--	src = adev->irq.sources[src_id];
--	if (!src) {
--		DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
--		return;
--	}
-+	if (adev->irq.virq[src_id]) {
-+		generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
-+	} else {
-+		src = adev->irq.sources[src_id];
-+		if (!src) {
-+			DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
-+			return;
-+		}
- 
--	r = src->funcs->process(adev, src, entry);
--	if (r)
--		DRM_ERROR("error processing interrupt (%d)\n", r);
-+		r = src->funcs->process(adev, src, entry);
-+		if (r)
-+			DRM_ERROR("error processing interrupt (%d)\n", r);
-+	}
- }
- 
- /**
-@@ -461,3 +466,90 @@ bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- 
- 	return !!atomic_read(&src->enabled_types[type]);
- }
-+
-+/* gen irq */
-+static void amdgpu_irq_mask(struct irq_data *irqd)
-+{
-+	/* XXX */
-+}
-+
-+static void amdgpu_irq_unmask(struct irq_data *irqd)
-+{
-+	/* XXX */
-+}
-+
-+static struct irq_chip amdgpu_irq_chip = {
-+	.name = "amdgpu-ih",
-+	.irq_mask = amdgpu_irq_mask,
-+	.irq_unmask = amdgpu_irq_unmask,
-+};
-+
-+static int amdgpu_irqdomain_map(struct irq_domain *d,
-+				unsigned int irq, irq_hw_number_t hwirq)
-+{
-+	if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
-+		return -EPERM;
-+
-+	irq_set_chip_and_handler(irq,
-+				 &amdgpu_irq_chip, handle_simple_irq);
-+	return 0;
-+}
-+
-+static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
-+	.map = amdgpu_irqdomain_map,
-+};
-+
-+/**
-+ * amdgpu_irq_add_domain - create a linear irq domain
-+ *
-+ * @adev: amdgpu device pointer
-+ *
-+ * Create an irq domain for GPU interrupt sources
-+ * that may be driven by another driver (e.g., ACP).
-+ */
-+int amdgpu_irq_add_domain(struct amdgpu_device *adev)
-+{
-+	adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
-+						 &amdgpu_hw_irqdomain_ops, adev);
-+	if (!adev->irq.domain) {
-+		DRM_ERROR("GPU irq add domain failed\n");
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * amdgpu_irq_remove_domain - remove the irq domain
-+ *
-+ * @adev: amdgpu device pointer
-+ *
-+ * Remove the irq domain for GPU interrupt sources
-+ * that may be driven by another driver (e.g., ACP).
-+ */
-+void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
-+{
-+	if (adev->irq.domain) {
-+		irq_domain_remove(adev->irq.domain);
-+		adev->irq.domain = NULL;
-+	}
-+}
-+
-+/**
-+ * amdgpu_irq_create_mapping - create a mapping between a domain irq and a
-+ *                             Linux irq
-+ *
-+ * @adev: amdgpu device pointer
-+ * @src_id: IH source id
-+ *
-+ * Create a mapping between a domain irq (GPU IH src id) and a Linux irq
-+ * Use this for components that generate a GPU interrupt, but are driven
-+ * by a different driver (e.g., ACP).
-+ * Returns the Linux irq.
-+ */
-+unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
-+{
-+	adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
-+
-+	return adev->irq.virq[src_id];
-+}
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
-index 17b01ae..e124b59 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
-@@ -24,6 +24,7 @@
- #ifndef __AMDGPU_IRQ_H__
- #define __AMDGPU_IRQ_H__
- 
-+#include <linux/irqdomain.h>
- #include "amdgpu_ih.h"
- 
- #define AMDGPU_MAX_IRQ_SRC_ID	0x100
-@@ -65,6 +66,10 @@ struct amdgpu_irq {
- 	/* interrupt ring */
- 	struct amdgpu_ih_ring		ih;
- 	const struct amdgpu_ih_funcs	*ih_funcs;
-+
-+	/* gen irq stuff */
-+	struct irq_domain		*domain; /* GPU irq controller domain */
-+	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
- };
- 
- void amdgpu_irq_preinstall(struct drm_device *dev);
-@@ -90,4 +95,8 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- 			unsigned type);
- 
-+int amdgpu_irq_add_domain(struct amdgpu_device *adev);
-+void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
-+unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-index 8993c50..30c9b3b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-@@ -274,6 +274,11 @@ static void cik_ih_set_rptr(struct amdgpu_device *adev)
- static int cik_ih_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int ret;
-+
-+	ret = amdgpu_irq_add_domain(adev);
-+	if (ret)
-+		return ret;
- 
- 	cik_ih_set_interrupt_funcs(adev);
- 
-@@ -300,6 +305,7 @@ static int cik_ih_sw_fini(void *handle)
- 
- 	amdgpu_irq_fini(adev);
- 	amdgpu_ih_ring_fini(adev);
-+	amdgpu_irq_remove_domain(adev);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-index bc751bf..c79638f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-@@ -253,8 +253,14 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev)
- static int cz_ih_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int ret;
-+
-+	ret = amdgpu_irq_add_domain(adev);
-+	if (ret)
-+		return ret;
- 
- 	cz_ih_set_interrupt_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -278,6 +284,7 @@ static int cz_ih_sw_fini(void *handle)
- 
- 	amdgpu_irq_fini(adev);
- 	amdgpu_ih_ring_fini(adev);
-+	amdgpu_irq_remove_domain(adev);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-index 779532d..679e739 100644
---- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-@@ -253,8 +253,14 @@ static void iceland_ih_set_rptr(struct amdgpu_device *adev)
- static int iceland_ih_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int ret;
-+
-+	ret = amdgpu_irq_add_domain(adev);
-+	if (ret)
-+		return ret;
- 
- 	iceland_ih_set_interrupt_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -278,6 +284,7 @@ static int iceland_ih_sw_fini(void *handle)
- 
- 	amdgpu_irq_fini(adev);
- 	amdgpu_ih_ring_fini(adev);
-+	amdgpu_irq_remove_domain(adev);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-index 743c372..b6f7d7b 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-@@ -273,8 +273,14 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev)
- static int tonga_ih_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int ret;
-+
-+	ret = amdgpu_irq_add_domain(adev);
-+	if (ret)
-+		return ret;
- 
- 	tonga_ih_set_interrupt_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -301,6 +307,7 @@ static int tonga_ih_sw_fini(void *handle)
- 
- 	amdgpu_irq_fini(adev);
- 	amdgpu_ih_ring_fini(adev);
-+	amdgpu_irq_add_domain(adev);
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0167-drm-amdgpu-powerplay-include-asm-div64.h-for-do_div.patch b/common/recipes-kernel/linux/files/0167-drm-amdgpu-powerplay-include-asm-div64.h-for-do_div.patch
deleted file mode 100644
index 6e27ebc8..00000000
--- a/common/recipes-kernel/linux/files/0167-drm-amdgpu-powerplay-include-asm-div64.h-for-do_div.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d48d44b0fa43f11e6a7d5dc54fd044d9151eade9 Mon Sep 17 00:00:00 2001
-From: Stephen Rothwell <sfr@canb.auug.org.au>
-Date: Thu, 31 Dec 2015 21:20:20 +1100
-Subject: [PATCH 0167/1110] drm/amdgpu/powerplay: include asm/div64.h for
- do_div()
-
-Fixes: 1e4854e96c35 ("drm/amdgpu/powerplay: implement thermal control for tonga.")
-Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
-Signed-off-by: Dave Airlie <airlied@redhat.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c  | 2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-index def57d0..e76a7de 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-@@ -20,7 +20,7 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
--
-+#include <asm/div64.h>
- #include "fiji_thermal.h"
- #include "fiji_hwmgr.h"
- #include "fiji_smumgr.h"
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-index 2e159b0..a188174 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-@@ -20,7 +20,7 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
--
-+#include <asm/div64.h>
- #include "tonga_thermal.h"
- #include "tonga_hwmgr.h"
- #include "tonga_smumgr.h"
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0168-drm-amd-powerplay-fix-static-checker-warning-for-ret.patch b/common/recipes-kernel/linux/files/0168-drm-amd-powerplay-fix-static-checker-warning-for-ret.patch
deleted file mode 100644
index fa4d2e38..00000000
--- a/common/recipes-kernel/linux/files/0168-drm-amd-powerplay-fix-static-checker-warning-for-ret.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From ca258fb603fb40548abf29dfdeced6b472da24c2 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 11 Jan 2016 11:25:18 +0800
-Subject: [PATCH 0168/1110] drm/amd/powerplay: fix static checker warning for
- return meaningless value.
-
-The return value should be either negative or zero, no positive.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-index d166fd9..ebdb43a 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-@@ -199,7 +199,7 @@ static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
- 	PP_ASSERT_WITH_CODE(
- 		1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
- 		"Failed to send Previous Message.",
--		return 1);
-+		);
- 
- 	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
- 
-@@ -207,7 +207,7 @@ static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
- 	PP_ASSERT_WITH_CODE(
- 		1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
- 		"Failed to send Message.",
--		return 1);
-+		);
- 
- 	return 0;
- }
-@@ -229,7 +229,7 @@ static int tonga_send_msg_to_smc_without_waiting
- 	PP_ASSERT_WITH_CODE(
- 		1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
- 		"Failed to send Previous Message.",
--		return 0);
-+		);
- 	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0169-drm-amdgpu-cz-add-code-to-enable-forcing-UVD-clocks.patch b/common/recipes-kernel/linux/files/0169-drm-amdgpu-cz-add-code-to-enable-forcing-UVD-clocks.patch
deleted file mode 100644
index dcc67b68..00000000
--- a/common/recipes-kernel/linux/files/0169-drm-amdgpu-cz-add-code-to-enable-forcing-UVD-clocks.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From 459ab71fa30c122605416991c383b2f801834456 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 18 Dec 2015 11:06:42 -0500
-Subject: [PATCH 0169/1110] drm/amdgpu/cz: add code to enable forcing UVD
- clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-UVD DPM works similarly to SCLK DPM.  Add a similar interface
-for UVD for forcing the UVD clocks.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 129 ++++++++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/cz_dpm.h |   1 +
- 2 files changed, 130 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index 8035d4d..5ccea9f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -1078,6 +1078,37 @@ static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
- 	return i;
- }
- 
-+static uint32_t cz_get_uvd_level(struct amdgpu_device *adev,
-+				 uint32_t clock, uint16_t msg)
-+{
-+	int i = 0;
-+	struct amdgpu_uvd_clock_voltage_dependency_table *table =
-+		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
-+
-+	switch (msg) {
-+	case PPSMC_MSG_SetUvdSoftMin:
-+	case PPSMC_MSG_SetUvdHardMin:
-+		for (i = 0; i < table->count; i++)
-+			if (clock <= table->entries[i].vclk)
-+				break;
-+		if (i == table->count)
-+			i = table->count - 1;
-+		break;
-+	case PPSMC_MSG_SetUvdSoftMax:
-+	case PPSMC_MSG_SetUvdHardMax:
-+		for (i = table->count - 1; i >= 0; i--)
-+			if (clock >= table->entries[i].vclk)
-+				break;
-+		if (i < 0)
-+			i = 0;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return i;
-+}
-+
- static int cz_program_bootup_state(struct amdgpu_device *adev)
- {
- 	struct cz_power_info *pi = cz_get_pi(adev);
-@@ -1739,6 +1770,104 @@ static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
- 	return 0;
- }
- 
-+
-+static int cz_dpm_uvd_force_highest(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+	int ret = 0;
-+
-+	if (pi->uvd_dpm.soft_min_clk != pi->uvd_dpm.soft_max_clk) {
-+		pi->uvd_dpm.soft_min_clk =
-+			pi->uvd_dpm.soft_max_clk;
-+		ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetUvdSoftMin,
-+				cz_get_uvd_level(adev,
-+					pi->uvd_dpm.soft_min_clk,
-+					PPSMC_MSG_SetUvdSoftMin));
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static int cz_dpm_uvd_force_lowest(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+	int ret = 0;
-+
-+	if (pi->uvd_dpm.soft_max_clk != pi->uvd_dpm.soft_min_clk) {
-+		pi->uvd_dpm.soft_max_clk = pi->uvd_dpm.soft_min_clk;
-+		ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetUvdSoftMax,
-+				cz_get_uvd_level(adev,
-+					pi->uvd_dpm.soft_max_clk,
-+					PPSMC_MSG_SetUvdSoftMax));
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static uint32_t cz_dpm_get_max_uvd_level(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+
-+	if (!pi->max_uvd_level) {
-+		cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
-+		pi->max_uvd_level = cz_get_argument(adev) + 1;
-+	}
-+
-+	if (pi->max_uvd_level > CZ_MAX_HARDWARE_POWERLEVELS) {
-+		DRM_ERROR("Invalid max uvd level!\n");
-+		return -EINVAL;
-+	}
-+
-+	return pi->max_uvd_level;
-+}
-+
-+static int cz_dpm_unforce_uvd_dpm_levels(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+	struct amdgpu_uvd_clock_voltage_dependency_table *dep_table =
-+		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
-+	uint32_t level = 0;
-+	int ret = 0;
-+
-+	pi->uvd_dpm.soft_min_clk = dep_table->entries[0].vclk;
-+	level = cz_dpm_get_max_uvd_level(adev) - 1;
-+	if (level < dep_table->count)
-+		pi->uvd_dpm.soft_max_clk = dep_table->entries[level].vclk;
-+	else
-+		pi->uvd_dpm.soft_max_clk =
-+			dep_table->entries[dep_table->count - 1].vclk;
-+
-+	/* get min/max sclk soft value
-+	 * notify SMU to execute */
-+	ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetUvdSoftMin,
-+				cz_get_uvd_level(adev,
-+					pi->uvd_dpm.soft_min_clk,
-+					PPSMC_MSG_SetUvdSoftMin));
-+	if (ret)
-+		return ret;
-+
-+	ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetUvdSoftMax,
-+				cz_get_uvd_level(adev,
-+					pi->uvd_dpm.soft_max_clk,
-+					PPSMC_MSG_SetUvdSoftMax));
-+	if (ret)
-+		return ret;
-+
-+	DRM_DEBUG("DPM uvd unforce state min=%d, max=%d.\n",
-+		  pi->uvd_dpm.soft_min_clk,
-+		  pi->uvd_dpm.soft_max_clk);
-+
-+	return 0;
-+}
-+
- static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
- 				  enum amdgpu_dpm_forced_level level)
- {
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
-index 99e1afc..6a6a6fe 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
-@@ -183,6 +183,7 @@ struct cz_power_info {
- 	uint32_t voltage_drop_threshold;
- 	uint32_t gfx_pg_threshold;
- 	uint32_t max_sclk_level;
-+	uint32_t max_uvd_level;
- 	/* flags */
- 	bool didt_enabled;
- 	bool video_start;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0170-drm-amdgpu-cz-add-code-to-enable-forcing-VCE-clocks.patch b/common/recipes-kernel/linux/files/0170-drm-amdgpu-cz-add-code-to-enable-forcing-VCE-clocks.patch
deleted file mode 100644
index adb6994e..00000000
--- a/common/recipes-kernel/linux/files/0170-drm-amdgpu-cz-add-code-to-enable-forcing-VCE-clocks.patch
+++ /dev/null
@@ -1,150 +0,0 @@
-From 08a5aab8c32a3234d0487f9348170e6eda821287 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 18 Dec 2015 11:25:16 -0500
-Subject: [PATCH 0170/1110] drm/amdgpu/cz: add code to enable forcing VCE
- clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-VCE DPM works similarly to SCLK DPM.  Add a similar interface
-for VCE for forcing the VCE clocks.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 98 ++++++++++++++++++++++++++++++++++++-
- drivers/gpu/drm/amd/amdgpu/cz_dpm.h |  1 +
- 2 files changed, 98 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index 5ccea9f..02cba49 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -1770,7 +1770,6 @@ static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
- 	return 0;
- }
- 
--
- static int cz_dpm_uvd_force_highest(struct amdgpu_device *adev)
- {
- 	struct cz_power_info *pi = cz_get_pi(adev);
-@@ -1868,6 +1867,103 @@ static int cz_dpm_unforce_uvd_dpm_levels(struct amdgpu_device *adev)
- 	return 0;
- }
- 
-+static int cz_dpm_vce_force_highest(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+	int ret = 0;
-+
-+	if (pi->vce_dpm.soft_min_clk != pi->vce_dpm.soft_max_clk) {
-+		pi->vce_dpm.soft_min_clk =
-+			pi->vce_dpm.soft_max_clk;
-+		ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetEclkSoftMin,
-+				cz_get_eclk_level(adev,
-+					pi->vce_dpm.soft_min_clk,
-+					PPSMC_MSG_SetEclkSoftMin));
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static int cz_dpm_vce_force_lowest(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+	int ret = 0;
-+
-+	if (pi->vce_dpm.soft_max_clk != pi->vce_dpm.soft_min_clk) {
-+		pi->vce_dpm.soft_max_clk = pi->vce_dpm.soft_min_clk;
-+		ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetEclkSoftMax,
-+				cz_get_uvd_level(adev,
-+					pi->vce_dpm.soft_max_clk,
-+					PPSMC_MSG_SetEclkSoftMax));
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static uint32_t cz_dpm_get_max_vce_level(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+
-+	if (!pi->max_vce_level) {
-+		cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
-+		pi->max_vce_level = cz_get_argument(adev) + 1;
-+	}
-+
-+	if (pi->max_vce_level > CZ_MAX_HARDWARE_POWERLEVELS) {
-+		DRM_ERROR("Invalid max vce level!\n");
-+		return -EINVAL;
-+	}
-+
-+	return pi->max_vce_level;
-+}
-+
-+static int cz_dpm_unforce_vce_dpm_levels(struct amdgpu_device *adev)
-+{
-+	struct cz_power_info *pi = cz_get_pi(adev);
-+	struct amdgpu_vce_clock_voltage_dependency_table *dep_table =
-+		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
-+	uint32_t level = 0;
-+	int ret = 0;
-+
-+	pi->vce_dpm.soft_min_clk = dep_table->entries[0].ecclk;
-+	level = cz_dpm_get_max_vce_level(adev) - 1;
-+	if (level < dep_table->count)
-+		pi->vce_dpm.soft_max_clk = dep_table->entries[level].ecclk;
-+	else
-+		pi->vce_dpm.soft_max_clk =
-+			dep_table->entries[dep_table->count - 1].ecclk;
-+
-+	/* get min/max sclk soft value
-+	 * notify SMU to execute */
-+	ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetEclkSoftMin,
-+				cz_get_eclk_level(adev,
-+					pi->vce_dpm.soft_min_clk,
-+					PPSMC_MSG_SetEclkSoftMin));
-+	if (ret)
-+		return ret;
-+
-+	ret = cz_send_msg_to_smc_with_parameter(adev,
-+				PPSMC_MSG_SetEclkSoftMax,
-+				cz_get_eclk_level(adev,
-+					pi->vce_dpm.soft_max_clk,
-+					PPSMC_MSG_SetEclkSoftMax));
-+	if (ret)
-+		return ret;
-+
-+	DRM_DEBUG("DPM vce unforce state min=%d, max=%d.\n",
-+		  pi->vce_dpm.soft_min_clk,
-+		  pi->vce_dpm.soft_max_clk);
-+
-+	return 0;
-+}
-+
- static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
- 				  enum amdgpu_dpm_forced_level level)
- {
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
-index 6a6a6fe..5df8c1f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
-@@ -184,6 +184,7 @@ struct cz_power_info {
- 	uint32_t gfx_pg_threshold;
- 	uint32_t max_sclk_level;
- 	uint32_t max_uvd_level;
-+	uint32_t max_vce_level;
- 	/* flags */
- 	bool didt_enabled;
- 	bool video_start;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0171-drm-amdgpu-cz-force-uvd-clocks-when-sclks-are-forced.patch b/common/recipes-kernel/linux/files/0171-drm-amdgpu-cz-force-uvd-clocks-when-sclks-are-forced.patch
deleted file mode 100644
index 35cd1af1..00000000
--- a/common/recipes-kernel/linux/files/0171-drm-amdgpu-cz-force-uvd-clocks-when-sclks-are-forced.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 3620a28cbd3739c6445a4a76680620a1041fddd5 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 18 Dec 2015 11:28:49 -0500
-Subject: [PATCH 0171/1110] drm/amdgpu/cz: force uvd clocks when sclks are
- forced
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index 02cba49..bdf5a22 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -1971,25 +1971,49 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
- 
- 	switch (level) {
- 	case AMDGPU_DPM_FORCED_LEVEL_HIGH:
-+		/* sclk */
- 		ret = cz_dpm_unforce_dpm_levels(adev);
- 		if (ret)
- 			return ret;
- 		ret = cz_dpm_force_highest(adev);
- 		if (ret)
- 			return ret;
-+
-+		/* uvd */
-+		ret = cz_dpm_unforce_uvd_dpm_levels(adev);
-+		if (ret)
-+			return ret;
-+		ret = cz_dpm_uvd_force_highest(adev);
-+		if (ret)
-+			return ret;
- 		break;
- 	case AMDGPU_DPM_FORCED_LEVEL_LOW:
-+		/* sclk */
- 		ret = cz_dpm_unforce_dpm_levels(adev);
- 		if (ret)
- 			return ret;
- 		ret = cz_dpm_force_lowest(adev);
- 		if (ret)
- 			return ret;
-+
-+		/* uvd */
-+		ret = cz_dpm_unforce_uvd_dpm_levels(adev);
-+		if (ret)
-+			return ret;
-+		ret = cz_dpm_uvd_force_lowest(adev);
-+		if (ret)
-+			return ret;
- 		break;
- 	case AMDGPU_DPM_FORCED_LEVEL_AUTO:
-+		/* sclk */
- 		ret = cz_dpm_unforce_dpm_levels(adev);
- 		if (ret)
- 			return ret;
-+
-+		/* uvd */
-+		ret = cz_dpm_unforce_uvd_dpm_levels(adev);
-+		if (ret)
-+			return ret;
- 		break;
- 	default:
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0172-drm-amdgpu-cz-force-vce-clocks-when-sclks-are-forced.patch b/common/recipes-kernel/linux/files/0172-drm-amdgpu-cz-force-vce-clocks-when-sclks-are-forced.patch
deleted file mode 100644
index 59784b80..00000000
--- a/common/recipes-kernel/linux/files/0172-drm-amdgpu-cz-force-vce-clocks-when-sclks-are-forced.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From c93f76093ff3bc1e92e2c56cb23ee96b2b304d6f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 18 Dec 2015 11:33:30 -0500
-Subject: [PATCH 0172/1110] drm/amdgpu/cz: force vce clocks when sclks are
- forced
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 24 +++++++++++++++++++++++-
- 1 file changed, 23 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index bdf5a22..4dd17f2 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -1986,6 +1986,14 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
- 		ret = cz_dpm_uvd_force_highest(adev);
- 		if (ret)
- 			return ret;
-+
-+		/* vce */
-+		ret = cz_dpm_unforce_vce_dpm_levels(adev);
-+		if (ret)
-+			return ret;
-+		ret = cz_dpm_vce_force_highest(adev);
-+		if (ret)
-+			return ret;
- 		break;
- 	case AMDGPU_DPM_FORCED_LEVEL_LOW:
- 		/* sclk */
-@@ -2003,6 +2011,14 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
- 		ret = cz_dpm_uvd_force_lowest(adev);
- 		if (ret)
- 			return ret;
-+
-+		/* vce */
-+		ret = cz_dpm_unforce_vce_dpm_levels(adev);
-+		if (ret)
-+			return ret;
-+		ret = cz_dpm_vce_force_lowest(adev);
-+		if (ret)
-+			return ret;
- 		break;
- 	case AMDGPU_DPM_FORCED_LEVEL_AUTO:
- 		/* sclk */
-@@ -2014,6 +2030,11 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
- 		ret = cz_dpm_unforce_uvd_dpm_levels(adev);
- 		if (ret)
- 			return ret;
-+
-+		/* vce */
-+		ret = cz_dpm_unforce_vce_dpm_levels(adev);
-+		if (ret)
-+			return ret;
- 		break;
- 	default:
- 		break;
-@@ -2154,7 +2175,8 @@ static int cz_update_vce_dpm(struct amdgpu_device *adev)
- 		pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
- 
- 	} else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
--		pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
-+		/* leave it as set by user */
-+		/*pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;*/
- 	}
- 
- 	cz_send_msg_to_smc_with_parameter(adev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0173-drm-amdgpu-use-kobj_to_dev.patch b/common/recipes-kernel/linux/files/0173-drm-amdgpu-use-kobj_to_dev.patch
deleted file mode 100644
index 046b092b..00000000
--- a/common/recipes-kernel/linux/files/0173-drm-amdgpu-use-kobj_to_dev.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 76088f00f64497474ec1c85243f29109e4cfc058 Mon Sep 17 00:00:00 2001
-From: Geliang Tang <geliangtang@163.com>
-Date: Wed, 13 Jan 2016 22:48:42 +0800
-Subject: [PATCH 0173/1110] drm/amdgpu: use kobj_to_dev()
-
-Use kobj_to_dev() instead of open-coding it.
-
-Signed-off-by: Geliang Tang <geliangtang@163.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 398c197..8edcdd7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -326,7 +326,7 @@ static struct attribute *hwmon_attributes[] = {
- static umode_t hwmon_attributes_visible(struct kobject *kobj,
- 					struct attribute *attr, int index)
- {
--	struct device *dev = container_of(kobj, struct device, kobj);
-+	struct device *dev = kobj_to_dev(kobj);
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	umode_t effective_mode = attr->mode;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0174-drm-amdgpu-move-VM-page-tables-to-the-LRU-end-on-CS-.patch b/common/recipes-kernel/linux/files/0174-drm-amdgpu-move-VM-page-tables-to-the-LRU-end-on-CS-.patch
deleted file mode 100644
index 545151cb..00000000
--- a/common/recipes-kernel/linux/files/0174-drm-amdgpu-move-VM-page-tables-to-the-LRU-end-on-CS-.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From e6460e3680517c987dd3a934c33324ff166f60bf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 10 Jun 2016 18:46:42 +0530
-Subject: [PATCH 0174/1110] drm/amdgpu: move VM page tables to the LRU end on
- CS v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This makes it less likely to run into an ENOMEM because
-VM page tables are evicted last.
-
-v2: move the BOs in the LRU tail after validation
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: kalyan alle <kalle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 ++++++++++++++++++++++++++
- 2 files changed, 28 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 4084669..6edeba2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -993,6 +993,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-                          struct list_head *validated,
-                          struct amdgpu_bo_list_entry *entry);
- void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
-+void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-+                                  struct amdgpu_vm *vm);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		      struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index e83d4f1..d495db3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -130,6 +130,32 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
- }
- 
- /**
-+ * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
-+ *
-+ * @adev: amdgpu device instance
-+ * @vm: vm providing the BOs
-+ *
-+ * Move the PT BOs to the tail of the LRU.
-+ */
-+void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-+                                  struct amdgpu_vm *vm)
-+{
-+        struct ttm_bo_global *glob = adev->mman.bdev.glob;
-+        unsigned i;
-+ 
-+        spin_lock(&glob->lru_lock);
-+        for (i = 0; i <= vm->max_pde_used; ++i) {
-+                struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-+ 
-+                if (!entry->robj)
-+                        continue;
-+ 
-+                ttm_bo_move_to_lru_tail(&entry->robj->tbo);
-+        }
-+        spin_unlock(&glob->lru_lock);
-+}
-+
-+/**
-  * amdgpu_vm_grab_id - allocate the next free VMID
-  *
-  * @vm: vm to allocate id for
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0175-drm-amdgpu-validate-duplicates-first.patch b/common/recipes-kernel/linux/files/0175-drm-amdgpu-validate-duplicates-first.patch
deleted file mode 100644
index 569bbca3..00000000
--- a/common/recipes-kernel/linux/files/0175-drm-amdgpu-validate-duplicates-first.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 1d360569ca9850df2864c1f7523fc14869d1d7b8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 10 Jun 2016 18:58:39 +0530
-Subject: [PATCH 0175/1110] drm/amdgpu: validate duplicates first
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Most VM BOs end up in the duplicates list, validate it
-first make -ENOMEM less likely.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <David1.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 850f2ab..b7d6438 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -421,11 +421,11 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 
-         amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
- 
--	r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
-+        r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
- 	if (r)
- 		goto error_validate;
- 
--	r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
-+        r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
- 
- error_validate:
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0176-drm-amdgpu-add-missing-irq.h-include.patch b/common/recipes-kernel/linux/files/0176-drm-amdgpu-add-missing-irq.h-include.patch
deleted file mode 100644
index ce38ef81..00000000
--- a/common/recipes-kernel/linux/files/0176-drm-amdgpu-add-missing-irq.h-include.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From a2f35ce40a9182aadca77af81fb38cb4f772f702 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Thu, 14 Jan 2016 08:07:55 +1000
-Subject: [PATCH 0176/1110] drm/amdgpu: add missing irq.h include
-
-this fixes the build on arm.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 3006182..f594cfa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -25,6 +25,7 @@
-  *          Alex Deucher
-  *          Jerome Glisse
-  */
-+#include <linux/irq.h>
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/amdgpu_drm.h>
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0177-drm-amdgpu-Add-some-tweaks-to-gfx-8-soft-reset.patch b/common/recipes-kernel/linux/files/0177-drm-amdgpu-Add-some-tweaks-to-gfx-8-soft-reset.patch
deleted file mode 100644
index d0769bc8..00000000
--- a/common/recipes-kernel/linux/files/0177-drm-amdgpu-Add-some-tweaks-to-gfx-8-soft-reset.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 376ba97a7dc4e999a24f0ef6843f1cd5c30a9e63 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 10:59:16 -0400
-Subject: [PATCH 0177/1110] drm/amdgpu: Add some tweaks to gfx 8 soft reset
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 42b4203..ba3d11a 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4186,7 +4186,18 @@ static int gfx_v8_0_soft_reset(void *handle)
- 		gfx_v8_0_cp_gfx_enable(adev, false);
- 
- 		/* Disable MEC parsing/prefetching */
--		/* XXX todo */
-+		gfx_v8_0_cp_compute_enable(adev, false);
-+
-+		if (grbm_soft_reset || srbm_soft_reset) {
-+			tmp = RREG32(mmGMCON_DEBUG);
-+			tmp = REG_SET_FIELD(tmp,
-+					    GMCON_DEBUG, GFX_STALL, 1);
-+			tmp = REG_SET_FIELD(tmp,
-+					    GMCON_DEBUG, GFX_CLEAR, 1);
-+			WREG32(mmGMCON_DEBUG, tmp);
-+
-+			udelay(50);
-+		}
- 
- 		if (grbm_soft_reset) {
- 			tmp = RREG32(mmGRBM_SOFT_RESET);
-@@ -4215,6 +4226,16 @@ static int gfx_v8_0_soft_reset(void *handle)
- 			WREG32(mmSRBM_SOFT_RESET, tmp);
- 			tmp = RREG32(mmSRBM_SOFT_RESET);
- 		}
-+
-+		if (grbm_soft_reset || srbm_soft_reset) {
-+			tmp = RREG32(mmGMCON_DEBUG);
-+			tmp = REG_SET_FIELD(tmp,
-+					    GMCON_DEBUG, GFX_STALL, 0);
-+			tmp = REG_SET_FIELD(tmp,
-+					    GMCON_DEBUG, GFX_CLEAR, 0);
-+			WREG32(mmGMCON_DEBUG, tmp);
-+		}
-+
- 		/* Wait a little for things to settle down */
- 		udelay(50);
- 		gfx_v8_0_print_status((void *)adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0178-drm-amdgpu-Allow-the-driver-to-load-if-amdgpu.powerp.patch b/common/recipes-kernel/linux/files/0178-drm-amdgpu-Allow-the-driver-to-load-if-amdgpu.powerp.patch
deleted file mode 100644
index 452f57a4..00000000
--- a/common/recipes-kernel/linux/files/0178-drm-amdgpu-Allow-the-driver-to-load-if-amdgpu.powerp.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 2589993a32dd6069b737681ed926e4209d5424a9 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 18 Jan 2016 17:00:03 -0500
-Subject: [PATCH 0178/1110] drm/amdgpu: Allow the driver to load if
- amdgpu.powerplay=1 on asics without powerplay support
-
-Avoid setting pp_enabled if there is no powerplay implementation.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 25 ++++++++++++++++++-------
- 1 file changed, 18 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 5ee9a06..b9d0d55 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -99,13 +99,24 @@ static int amdgpu_pp_early_init(void *handle)
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	switch (adev->asic_type) {
--		case CHIP_TONGA:
--		case CHIP_FIJI:
--			adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
--			break;
--		default:
--			adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
--			break;
-+	case CHIP_TONGA:
-+	case CHIP_FIJI:
-+		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
-+		break;
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+		adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
-+		break;
-+	/* These chips don't have powerplay implemenations */
-+	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
-+	case CHIP_KABINI:
-+	case CHIP_MULLINS:
-+	case CHIP_KAVERI:
-+	case CHIP_TOPAZ:
-+	default:
-+		adev->pp_enabled = false;
-+		break;
- 	}
- #else
- 	adev->pp_enabled = false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0179-drm-amd-amdgpu-Improve-amdgpu_dpm-macros-to-avoid-un.patch b/common/recipes-kernel/linux/files/0179-drm-amd-amdgpu-Improve-amdgpu_dpm-macros-to-avoid-un.patch
deleted file mode 100644
index 53038fde..00000000
--- a/common/recipes-kernel/linux/files/0179-drm-amd-amdgpu-Improve-amdgpu_dpm-macros-to-avoid-un.patch
+++ /dev/null
@@ -1,108 +0,0 @@
-From c5bdb2aca2d984ec540d7967ef22371f641357ca Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 19 Jan 2016 14:28:56 -0500
-Subject: [PATCH 0179/1110] drm/amd/amdgpu: Improve amdgpu_dpm* macros to avoid
- unexpected result (v2)
-
-The two macros returns are values which probably are used
-in the expression of calculation. Without the brackets
-the result of the expression may be wrong.
-
-v2: agd: squash both patches together
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 44 ++++++++++++++++++-------------------
- 1 file changed, 22 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 6edeba2..06a46f5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2285,60 +2285,60 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
- 
- #define amdgpu_dpm_get_temperature(adev) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
--	      (adev)->pm.funcs->get_temperature((adev))
-+	      (adev)->pm.funcs->get_temperature((adev)))
- 
- #define amdgpu_dpm_set_fan_control_mode(adev, m) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
--	      (adev)->pm.funcs->set_fan_control_mode((adev), (m))
-+	      (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
- 
- #define amdgpu_dpm_get_fan_control_mode(adev) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
--	      (adev)->pm.funcs->get_fan_control_mode((adev))
-+	      (adev)->pm.funcs->get_fan_control_mode((adev)))
- 
- #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
--	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
-+	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
- 
- #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
--	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
-+	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
- 
- #define amdgpu_dpm_get_sclk(adev, l) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
--		(adev)->pm.funcs->get_sclk((adev), (l))
-+		(adev)->pm.funcs->get_sclk((adev), (l)))
- 
- #define amdgpu_dpm_get_mclk(adev, l)  \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
--	      (adev)->pm.funcs->get_mclk((adev), (l))
-+	      (adev)->pm.funcs->get_mclk((adev), (l)))
- 
- 
- #define amdgpu_dpm_force_performance_level(adev, l) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
--	      (adev)->pm.funcs->force_performance_level((adev), (l))
-+	      (adev)->pm.funcs->force_performance_level((adev), (l)))
- 
- #define amdgpu_dpm_powergate_uvd(adev, g) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
--	      (adev)->pm.funcs->powergate_uvd((adev), (g))
-+	      (adev)->pm.funcs->powergate_uvd((adev), (g)))
- 
- #define amdgpu_dpm_powergate_vce(adev, g) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
--	      (adev)->pm.funcs->powergate_vce((adev), (g))
-+	      (adev)->pm.funcs->powergate_vce((adev), (g)))
- 
- #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
--	(adev)->pp_enabled ?						\
-+	((adev)->pp_enabled ?						\
- 	      (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
--	      (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
-+	      (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
- 
- #define amdgpu_dpm_get_current_power_state(adev) \
- 	(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0180-drm-amdgpu-add-a-message-to-indicate-when-powerplay-.patch b/common/recipes-kernel/linux/files/0180-drm-amdgpu-add-a-message-to-indicate-when-powerplay-.patch
deleted file mode 100644
index c2674645..00000000
--- a/common/recipes-kernel/linux/files/0180-drm-amdgpu-add-a-message-to-indicate-when-powerplay-.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From f5f134195c48e30a727e0cfc0a75dc157dabfcdb Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 20 Jan 2016 12:15:09 -0500
-Subject: [PATCH 0180/1110] drm/amdgpu: add a message to indicate when
- powerplay is enabled (v2)
-
-Makes it clear to the user which power management path is in
-use.
-
-v2: make consistent with dpm
-
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 8f5d5ed..aa67244 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -64,6 +64,11 @@ static int pp_sw_init(void *handle)
- 	if (ret == 0)
- 		ret = hwmgr->hwmgr_func->backend_init(hwmgr);
- 
-+	if (ret)
-+		printk("amdgpu: powerplay initialization failed\n");
-+	else
-+		printk("amdgpu: powerplay initialized\n");
-+
- 	return ret;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0181-drm-amdgpu-fix-next_rptr-handling-for-debugfs.patch b/common/recipes-kernel/linux/files/0181-drm-amdgpu-fix-next_rptr-handling-for-debugfs.patch
deleted file mode 100644
index 2b15e93e..00000000
--- a/common/recipes-kernel/linux/files/0181-drm-amdgpu-fix-next_rptr-handling-for-debugfs.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From fcd0db4290ef306be51ef9855481f6ca68e1535f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 21 Jan 2016 12:56:52 +0100
-Subject: [PATCH 0181/1110] drm/amdgpu: fix next_rptr handling for debugfs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-That somehow got lost.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 78e9b0f..d1f234d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -487,7 +487,7 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- 	seq_printf(m, "rptr: 0x%08x [%5d]\n",
- 		   rptr, rptr);
- 
--	rptr_next = ~0;
-+	rptr_next = le32_to_cpu(*ring->next_rptr_cpu_addr);
- 
- 	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
- 		   ring->wptr, ring->wptr);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0182-drm-amdgpu-don-t-init-fbdev-if-we-don-t-have-any-con.patch b/common/recipes-kernel/linux/files/0182-drm-amdgpu-don-t-init-fbdev-if-we-don-t-have-any-con.patch
deleted file mode 100644
index 111ba55b..00000000
--- a/common/recipes-kernel/linux/files/0182-drm-amdgpu-don-t-init-fbdev-if-we-don-t-have-any-con.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 97857de01f8e1bc9c4a4c5123e540ab997d6d3b8 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 26 Jan 2016 00:30:33 -0500
-Subject: [PATCH 0182/1110] drm/amdgpu: don't init fbdev if we don't have any
- connectors
-
-Don't init fbdev if we don't have connectors.  E.g., if you have
-a PX laptop with the displays attached to an IGP with no driver
-support, you may end up with a blank screen rather than falling
-back to vesa, etc.
-
-Based on a similar radeon patch from Rob Clark.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-index cfb6caa..9191467 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-@@ -333,6 +333,10 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
- 	if (!adev->mode_info.mode_config_initialized)
- 		return 0;
- 
-+	/* don't init fbdev if there are no connectors */
-+	if (list_empty(&adev->ddev->mode_config.connector_list))
-+		return 0;
-+
- 	/* select 8 bpp console on low vram cards */
- 	if (adev->mc.real_vram_size <= (32*1024*1024))
- 		bpp_sel = 8;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0183-drm-amd-powerplay-Update-SMU-firmware-loading-for-St.patch b/common/recipes-kernel/linux/files/0183-drm-amd-powerplay-Update-SMU-firmware-loading-for-St.patch
deleted file mode 100644
index ce7580b0..00000000
--- a/common/recipes-kernel/linux/files/0183-drm-amd-powerplay-Update-SMU-firmware-loading-for-St.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From 26241e142d4d65daa7c078538dd7ba93a8dd38ed Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 21 Jan 2016 19:24:44 +0800
-Subject: [PATCH 0183/1110] drm/amd/powerplay: Update SMU firmware loading for
- Stoney
-
-Fix firmware init on Stoney when powerplay is enabled.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 41 ++++++++++++++++++------
- 1 file changed, 32 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-index 873a8d2..ec222c6 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-@@ -272,6 +272,9 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
- 				UCODE_ID_CP_MEC_JT1_MASK |
- 				UCODE_ID_CP_MEC_JT2_MASK;
- 
-+	if (smumgr->chip_id == CHIP_STONEY)
-+		fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
-+
- 	cz_request_smu_load_fw(smumgr);
- 	cz_check_fw_load_finish(smumgr, fw_to_check);
- 
-@@ -282,7 +285,7 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
- 	return ret;
- }
- 
--static uint8_t cz_translate_firmware_enum_to_arg(
-+static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
- 			enum cz_scratch_entry firmware_enum)
- {
- 	uint8_t ret = 0;
-@@ -292,7 +295,10 @@ static uint8_t cz_translate_firmware_enum_to_arg(
- 		ret = UCODE_ID_SDMA0;
- 		break;
- 	case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
--		ret = UCODE_ID_SDMA1;
-+		if (smumgr->chip_id == CHIP_STONEY)
-+			ret = UCODE_ID_SDMA0;
-+		else
-+			ret = UCODE_ID_SDMA1;
- 		break;
- 	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
- 		ret = UCODE_ID_CP_CE;
-@@ -307,7 +313,10 @@ static uint8_t cz_translate_firmware_enum_to_arg(
- 		ret = UCODE_ID_CP_MEC_JT1;
- 		break;
- 	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
--		ret = UCODE_ID_CP_MEC_JT2;
-+		if (smumgr->chip_id == CHIP_STONEY)
-+			ret = UCODE_ID_CP_MEC_JT1;
-+		else
-+			ret = UCODE_ID_CP_MEC_JT2;
- 		break;
- 	case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
- 		ret = UCODE_ID_GMCON_RENG;
-@@ -396,7 +405,7 @@ static int cz_smu_populate_single_scratch_task(
- 	struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
- 
- 	task->type = type;
--	task->arg = cz_translate_firmware_enum_to_arg(fw_enum);
-+	task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
- 	task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
- 
- 	for (i = 0; i < cz_smu->scratch_buffer_length; i++)
-@@ -433,7 +442,7 @@ static int cz_smu_populate_single_ucode_load_task(
- 	struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
- 
- 	task->type = TASK_TYPE_UCODE_LOAD;
--	task->arg = cz_translate_firmware_enum_to_arg(fw_enum);
-+	task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
- 	task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
- 
- 	for (i = 0; i < cz_smu->driver_buffer_length; i++)
-@@ -509,8 +518,14 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr)
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
- 	cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+
-+	if (smumgr->chip_id == CHIP_STONEY)
-+		cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-+	else
-+		cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
-+
- 	cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
- 
-@@ -551,7 +566,11 @@ static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
- 
- 	cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	if (smumgr->chip_id == CHIP_STONEY)
-+		cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
-+	else
-+		cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
- 	cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
-@@ -561,7 +580,11 @@ static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
- 	cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	if (smumgr->chip_id == CHIP_STONEY)
-+		cz_smu_populate_single_ucode_load_task(smumgr,
-+				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-+	else
-+		cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
- 	cz_smu_populate_single_ucode_load_task(smumgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
-@@ -618,7 +641,7 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
- 
- 	for (i = 0; i < sizeof(firmware_list)/sizeof(*firmware_list); i++) {
- 
--		firmware_type = cz_translate_firmware_enum_to_arg(
-+		firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
- 					firmware_list[i]);
- 
- 		ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch b/common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch
deleted file mode 100644
index 96c94b43..00000000
--- a/common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 2cc9910bbf39e0c79338cfb57d0d575d57eddb14 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 2 Feb 2016 14:42:28 -0500
-Subject: [PATCH 0184/1110] drm/amdgpu/gfx8: enable cp inst/reg error
- interrupts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Enable CP register/instruction error interrupts. Useful
-for debugging command stream problems.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index ba3d11a..64a070e 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3901,6 +3901,8 @@ static int gfx_v8_0_hw_fini(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
-+	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
- 	gfx_v8_0_cp_enable(adev, false);
- 	gfx_v8_0_rlc_stop(adev);
- 	gfx_v8_0_cp_compute_fini(adev);
-@@ -4329,6 +4331,14 @@ static int gfx_v8_0_late_init(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	int r;
- 
-+	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
-+	if (r)
-+		return r;
-+
-+	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
-+	if (r)
-+		return r;
-+
- 	/* requires IBs so do in late init after IB pool is initialized */
- 	r = gfx_v8_0_do_edc_gpr_workarounds(adev);
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0185-drm-amdgpu-gfx7-enable-cp-inst-reg-error-interrupts.patch b/common/recipes-kernel/linux/files/0185-drm-amdgpu-gfx7-enable-cp-inst-reg-error-interrupts.patch
deleted file mode 100644
index 8f6ea3eb..00000000
--- a/common/recipes-kernel/linux/files/0185-drm-amdgpu-gfx7-enable-cp-inst-reg-error-interrupts.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 77d676c5a0592361bfda36993ecde349d1c816fc Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 2 Feb 2016 14:46:48 -0500
-Subject: [PATCH 0185/1110] drm/amdgpu/gfx7: enable cp inst/reg error
- interrupts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Enable CP register/instruction error interrupts. Useful
-for debugging command stream problems.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 20 +++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 9463007..96d2073 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4751,6 +4751,22 @@ static int gfx_v7_0_early_init(void *handle)
- 	return 0;
- }
- 
-+static int gfx_v7_0_late_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int r;
-+
-+	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
-+	if (r)
-+		return r;
-+
-+	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
-+	if (r)
-+		return r;
-+
-+	return 0;
-+}
-+
- static int gfx_v7_0_sw_init(void *handle)
- {
- 	struct amdgpu_ring *ring;
-@@ -4903,6 +4919,8 @@ static int gfx_v7_0_hw_fini(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
-+	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
- 	gfx_v7_0_cp_enable(adev, false);
- 	gfx_v7_0_rlc_stop(adev);
- 	gfx_v7_0_fini_pg(adev);
-@@ -5540,7 +5558,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
- 
- const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
- 	.early_init = gfx_v7_0_early_init,
--	.late_init = NULL,
-+	.late_init = gfx_v7_0_late_init,
- 	.sw_init = gfx_v7_0_sw_init,
- 	.sw_fini = gfx_v7_0_sw_fini,
- 	.hw_init = gfx_v7_0_hw_init,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0186-drm-amdgpu-load-MEC-ucode-manually-on-iceland.patch b/common/recipes-kernel/linux/files/0186-drm-amdgpu-load-MEC-ucode-manually-on-iceland.patch
deleted file mode 100644
index e0a5c61a..00000000
--- a/common/recipes-kernel/linux/files/0186-drm-amdgpu-load-MEC-ucode-manually-on-iceland.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From b834b8493dec3194a848f9b4656de2378ad7b4f8 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 2 Feb 2016 16:22:15 -0500
-Subject: [PATCH 0186/1110] drm/amdgpu: load MEC ucode manually on iceland
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The smc doesn't handle it.
-
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 64a070e..1cb5741 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3851,10 +3851,16 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
- 			if (r)
- 				return -EINVAL;
- 
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_CP_MEC1);
--			if (r)
--				return -EINVAL;
-+			if (adev->asic_type == CHIP_TOPAZ) {
-+				r = gfx_v8_0_cp_compute_load_microcode(adev);
-+				if (r)
-+					return r;
-+			} else {
-+				r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-+										 AMDGPU_UCODE_ID_CP_MEC1);
-+				if (r)
-+					return -EINVAL;
-+			}
- 		}
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0187-drm-amdgpu-disable-uvd-and-vce-clockgating-on-Fiji.patch b/common/recipes-kernel/linux/files/0187-drm-amdgpu-disable-uvd-and-vce-clockgating-on-Fiji.patch
deleted file mode 100644
index efabee8e..00000000
--- a/common/recipes-kernel/linux/files/0187-drm-amdgpu-disable-uvd-and-vce-clockgating-on-Fiji.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 295c411f3d9b5d71d166484cacba1e61518a4d59 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 2 Feb 2016 18:22:24 -0500
-Subject: [PATCH 0187/1110] drm/amdgpu: disable uvd and vce clockgating on Fiji
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Doesn't work properly yet.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index d94c625..89f5a1f 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1443,8 +1443,7 @@ static int vi_common_early_init(void *handle)
- 		break;
- 	case CHIP_FIJI:
- 		adev->has_uvd = true;
--		adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
--				AMDGPU_CG_SUPPORT_VCE_MGCG;
-+		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch b/common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch
deleted file mode 100644
index f859c7f0..00000000
--- a/common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch
+++ /dev/null
@@ -1,233 +0,0 @@
-From 0ce33e777dc9d6bee8b6d5039838966eab6bf4a3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 10:21:23 -0500
-Subject: [PATCH 0188/1110] drm/amdgpu: add pcie cap module parameters (v2)
-
-Allows the user to force the supported pcie gen and lane
-config on both the asic and the chipset.
-Useful for debugging pcie problems and for virtualization
-where we may not be able to query the pcie bridge caps.
-
-Default to:
-gen: chipset 1/2, asic 1/2/3
-lanes: 1/2/4/8/16
-
-v2: fix bare metal case
-
-Reviewed-by: monk liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   2 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 147 ++++++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    |   8 ++
- 3 files changed, 92 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 06a46f5..cb51310 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
- extern int amdgpu_enable_semaphores;
- extern int amdgpu_powerplay;
-+extern unsigned amdgpu_pcie_gen_cap;
-+extern unsigned amdgpu_pcie_lane_cap;
- 
- #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
- #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index e8905be..51bfc11 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1938,80 +1938,97 @@ retry:
- 	return r;
- }
- 
-+#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */
-+#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
-+
- void amdgpu_get_pcie_info(struct amdgpu_device *adev)
- {
- 	u32 mask;
- 	int ret;
- 
--	if (pci_is_root_bus(adev->pdev->bus))
--		return;
-+	if (amdgpu_pcie_gen_cap)
-+		adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
- 
--	if (amdgpu_pcie_gen2 == 0)
--		return;
-+	if (amdgpu_pcie_lane_cap)
-+		adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
- 
--	if (adev->flags & AMD_IS_APU)
-+	/* covers APUs as well */
-+	if (pci_is_root_bus(adev->pdev->bus)) {
-+		if (adev->pm.pcie_gen_mask == 0)
-+			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
-+		if (adev->pm.pcie_mlw_mask == 0)
-+			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
- 		return;
-+	}
- 
--	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
--	if (!ret) {
--		adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
--					  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
--					  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
--
--		if (mask & DRM_PCIE_SPEED_25)
--			adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
--		if (mask & DRM_PCIE_SPEED_50)
--			adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
--		if (mask & DRM_PCIE_SPEED_80)
--			adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
--	}
--	ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
--	if (!ret) {
--		switch (mask) {
--		case 32:
--			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
--			break;
--		case 16:
--			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
--			break;
--		case 12:
--			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
--			break;
--		case 8:
--			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
--			break;
--		case 4:
--			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
--			break;
--		case 2:
--			adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
--						  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
--			break;
--		case 1:
--			adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
--			break;
--		default:
--			break;
-+	if (adev->pm.pcie_gen_mask == 0) {
-+		ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-+		if (!ret) {
-+			adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
-+						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-+						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
-+
-+			if (mask & DRM_PCIE_SPEED_25)
-+				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
-+			if (mask & DRM_PCIE_SPEED_50)
-+				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
-+			if (mask & DRM_PCIE_SPEED_80)
-+				adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
-+		} else {
-+			adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
-+		}
-+	}
-+	if (adev->pm.pcie_mlw_mask == 0) {
-+		ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
-+		if (!ret) {
-+			switch (mask) {
-+			case 32:
-+				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+				break;
-+			case 16:
-+				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+				break;
-+			case 12:
-+				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+				break;
-+			case 8:
-+				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+				break;
-+			case 4:
-+				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+				break;
-+			case 2:
-+				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+				break;
-+			case 1:
-+				adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
-+				break;
-+			default:
-+				break;
-+			}
-+		} else {
-+			adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
- 		}
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 9c1af89..9ef1db8 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -83,6 +83,8 @@ int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_enable_semaphores = 0;
- int amdgpu_powerplay = -1;
-+unsigned amdgpu_pcie_gen_cap = 0;
-+unsigned amdgpu_pcie_lane_cap = 0;
- 
- MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
- module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
-@@ -170,6 +172,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 =
- module_param_named(powerplay, amdgpu_powerplay, int, 0444);
- #endif
- 
-+MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
-+module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
-+
-+MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
-+module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
-+
- static struct pci_device_id pciidlist[] = {
- #ifdef CONFIG_DRM_AMDGPU_CIK
- 	/* Kaveri */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0189-drm-amdgpu-cik-don-t-mess-with-aspm-if-gpu-is-root-b.patch b/common/recipes-kernel/linux/files/0189-drm-amdgpu-cik-don-t-mess-with-aspm-if-gpu-is-root-b.patch
deleted file mode 100644
index 01598394..00000000
--- a/common/recipes-kernel/linux/files/0189-drm-amdgpu-cik-don-t-mess-with-aspm-if-gpu-is-root-b.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 72d172fab54a89dab463cdab4decf3aa244cabb8 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 10:33:59 -0500
-Subject: [PATCH 0189/1110] drm/amdgpu/cik: don't mess with aspm if gpu is root
- bus
-
-Pcie registers may not be available in a virtualized
-environment.
-
-Reviewed-by: monk liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index fd9c958..5c978e0 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -1762,6 +1762,9 @@ static void cik_program_aspm(struct amdgpu_device *adev)
- 	if (amdgpu_aspm == 0)
- 		return;
- 
-+	if (pci_is_root_bus(adev->pdev->bus))
-+		return;
-+
- 	/* XXX double check APUs */
- 	if (adev->flags & AMD_IS_APU)
- 		return;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0190-drm-amdgpu-dpm-ci-switch-over-to-the-common-pcie-cap.patch b/common/recipes-kernel/linux/files/0190-drm-amdgpu-dpm-ci-switch-over-to-the-common-pcie-cap.patch
deleted file mode 100644
index d3fe1d24..00000000
--- a/common/recipes-kernel/linux/files/0190-drm-amdgpu-dpm-ci-switch-over-to-the-common-pcie-cap.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 43d93cc05437d218136f7a0f824c014d165c30ca Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 10:44:04 -0500
-Subject: [PATCH 0190/1110] drm/amdgpu/dpm/ci: switch over to the common pcie
- caps interface
-
-We already query this at driver init, so use that info.  Also
-handles virtualization cases.
-
-Reviewed-by: monk liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 11 +++++------
- 1 file changed, 5 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 8b4731d..474ca02 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -31,6 +31,7 @@
- #include "ci_dpm.h"
- #include "gfx_v7_0.h"
- #include "atom.h"
-+#include "amd_pcie.h"
- #include <linux/seq_file.h>
- 
- #include "smu/smu_7_0_1_d.h"
-@@ -5835,18 +5836,16 @@ static int ci_dpm_init(struct amdgpu_device *adev)
- 	u8 frev, crev;
- 	struct ci_power_info *pi;
- 	int ret;
--	u32 mask;
- 
- 	pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
- 	if (pi == NULL)
- 		return -ENOMEM;
- 	adev->pm.dpm.priv = pi;
- 
--	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
--	if (ret)
--		pi->sys_pcie_mask = 0;
--	else
--		pi->sys_pcie_mask = mask;
-+	pi->sys_pcie_mask =
-+		(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
-+		CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
-+
- 	pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
- 
- 	pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0191-drm-amdgpu-handle-uvd-pg-flags-properly.patch b/common/recipes-kernel/linux/files/0191-drm-amdgpu-handle-uvd-pg-flags-properly.patch
deleted file mode 100644
index 1ea6f8c4..00000000
--- a/common/recipes-kernel/linux/files/0191-drm-amdgpu-handle-uvd-pg-flags-properly.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 5555b7546ad656ee9e895d65a79adf963fe8c615 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:26:56 -0500
-Subject: [PATCH 0191/1110] drm/amdgpu: handle uvd pg flags properly
-
-Don't attempt to start/stop the uvd block if pg is disabled.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 ++++-
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 +++
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 +++
- 3 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index 5e9f73a..9cb5287 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -848,7 +848,10 @@ static int uvd_v4_2_set_powergating_state(void *handle,
- 	 * revisit this when there is a cleaner line between
- 	 * the smc and the hw blocks
- 	 */
--	 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_UVD))
-+		return 0;
- 
- 	if (state == AMD_PG_STATE_GATE) {
- 		uvd_v4_2_stop(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 38864f5..b4623de 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -789,6 +789,9 @@ static int uvd_v5_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_UVD))
-+		return 0;
-+
- 	if (state == AMD_PG_STATE_GATE) {
- 		uvd_v5_0_stop(adev);
- 		return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 3d59139..c41eda7 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -1030,6 +1030,9 @@ static int uvd_v6_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_UVD))
-+		return 0;
-+
- 	if (state == AMD_PG_STATE_GATE) {
- 		uvd_v6_0_stop(adev);
- 		return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0192-drm-amdgpu-handle-vce-pg-flags-properly.patch b/common/recipes-kernel/linux/files/0192-drm-amdgpu-handle-vce-pg-flags-properly.patch
deleted file mode 100644
index 98d54c67..00000000
--- a/common/recipes-kernel/linux/files/0192-drm-amdgpu-handle-vce-pg-flags-properly.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 93202d7b89cab4e2cdddf91b4f217786465fedd9 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:29:45 -0500
-Subject: [PATCH 0192/1110] drm/amdgpu: handle vce pg flags properly
-
-Don't attempt to start/stop the vce block if pg is disabled.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 3 +++
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +++
- 2 files changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index 52ac7a8..d3ce608 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -608,6 +608,9 @@ static int vce_v2_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_VCE))
-+		return 0;
-+
- 	if (state == AMD_PG_STATE_GATE)
- 		/* XXX do we need a vce_v2_0_stop()? */
- 		return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index e99af81..797d12c 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -728,6 +728,9 @@ static int vce_v3_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_VCE))
-+		return 0;
-+
- 	if (state == AMD_PG_STATE_GATE)
- 		/* XXX do we need a vce_v3_0_stop()? */
- 		return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0193-drm-amdgpu-clean-up-vce-pg-flags-for-cz-st.patch b/common/recipes-kernel/linux/files/0193-drm-amdgpu-clean-up-vce-pg-flags-for-cz-st.patch
deleted file mode 100644
index 33822626..00000000
--- a/common/recipes-kernel/linux/files/0193-drm-amdgpu-clean-up-vce-pg-flags-for-cz-st.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c26528c69f5c15b99568edd16b0a5d2bc7970cca Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:31:32 -0500
-Subject: [PATCH 0193/1110] drm/amdgpu: clean up vce pg flags for cz/st
-
-It was already disabled elsewhere, make it offical.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 89f5a1f..0d14d10 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1457,8 +1457,7 @@ static int vi_common_early_init(void *handle)
- 	case CHIP_STONEY:
- 		adev->has_uvd = true;
- 		adev->cg_flags = 0;
--		/* Disable UVD pg */
--		adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
-+		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
- 	default:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0194-drm-amdgpu-be-consistent-with-uvd-cg-flags.patch b/common/recipes-kernel/linux/files/0194-drm-amdgpu-be-consistent-with-uvd-cg-flags.patch
deleted file mode 100644
index a88f30db..00000000
--- a/common/recipes-kernel/linux/files/0194-drm-amdgpu-be-consistent-with-uvd-cg-flags.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 1ff27cd3c7cac0e653851ae0b2dc55fff822f816 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:33:56 -0500
-Subject: [PATCH 0194/1110] drm/amdgpu: be consistent with uvd cg flags
-
-Don't do anything if the uvd cg flags are not set.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +++
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++++
- 2 files changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index 9cb5287..c982524 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -830,6 +830,9 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
- 	bool gate = false;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG))
-+		return 0;
-+
- 	if (state == AMD_CG_STATE_GATE)
- 		gate = true;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index b4623de..aad1ab5 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -774,6 +774,11 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
- static int uvd_v5_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG))
-+		return 0;
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0195-drm-amd-powerplay-cz-disable-uvd-pg.patch b/common/recipes-kernel/linux/files/0195-drm-amd-powerplay-cz-disable-uvd-pg.patch
deleted file mode 100644
index 88a0cb9d..00000000
--- a/common/recipes-kernel/linux/files/0195-drm-amd-powerplay-cz-disable-uvd-pg.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From a2c12049cde2f2c0832415f18d00e06f80f01441 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:40:32 -0500
-Subject: [PATCH 0195/1110] drm/amd/powerplay/cz: disable uvd pg
-
-Not working reliably yet.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 0874ab4..8fc9e01 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -247,6 +247,8 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 				   PHM_PlatformCaps_DisableVoltageIsland);
- 
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		      PHM_PlatformCaps_UVDPowerGating);
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0196-drm-amd-powerplay-cz-disable-vce-pg.patch b/common/recipes-kernel/linux/files/0196-drm-amd-powerplay-cz-disable-vce-pg.patch
deleted file mode 100644
index e0df4709..00000000
--- a/common/recipes-kernel/linux/files/0196-drm-amd-powerplay-cz-disable-vce-pg.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f78039d1e8572b74304dc832389c02a8f4efb051 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:42:24 -0500
-Subject: [PATCH 0196/1110] drm/amd/powerplay/cz: disable vce pg
-
-Not working reliably yet.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 8fc9e01..80af87f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -249,6 +249,9 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- 
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 		      PHM_PlatformCaps_UVDPowerGating);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		      PHM_PlatformCaps_VCEPowerGating);
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0197-drm-amd-powerplay-tonga-disable-uvd-pg.patch b/common/recipes-kernel/linux/files/0197-drm-amd-powerplay-tonga-disable-uvd-pg.patch
deleted file mode 100644
index 150c14af..00000000
--- a/common/recipes-kernel/linux/files/0197-drm-amd-powerplay-tonga-disable-uvd-pg.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 1ff4f30e5e12f6ca0313edf2f7c8b118c4add05e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:47:38 -0500
-Subject: [PATCH 0197/1110] drm/amd/powerplay/tonga: disable uvd pg
-
-Not working reliably yet.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 44a9250..7518caa 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4615,6 +4615,9 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	data->vddc_phase_shed_control = 0;
- 
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		      PHM_PlatformCaps_UVDPowerGating);
-+
- 	if (0 == result) {
- 		struct cgs_system_info sys_info = {0};
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0198-drm-amd-powerplay-tonga-disable-vce-pg.patch b/common/recipes-kernel/linux/files/0198-drm-amd-powerplay-tonga-disable-vce-pg.patch
deleted file mode 100644
index 596f6bad..00000000
--- a/common/recipes-kernel/linux/files/0198-drm-amd-powerplay-tonga-disable-vce-pg.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From d7e964ff129e3993f212282fe59b1c8e8412e8f0 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 23:48:51 -0500
-Subject: [PATCH 0198/1110] drm/amd/powerplay/tonga: disable vce pg
-
-Not working reliably yet.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 7518caa..69c81c1 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4617,6 +4617,8 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 		      PHM_PlatformCaps_UVDPowerGating);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		      PHM_PlatformCaps_VCEPowerGating);
- 
- 	if (0 == result) {
- 		struct cgs_system_info sys_info = {0};
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0199-drm-amdgpu-add-a-cgs-interface-to-fetch-cg-and-pg-fl.patch b/common/recipes-kernel/linux/files/0199-drm-amdgpu-add-a-cgs-interface-to-fetch-cg-and-pg-fl.patch
deleted file mode 100644
index 3cf097ce..00000000
--- a/common/recipes-kernel/linux/files/0199-drm-amdgpu-add-a-cgs-interface-to-fetch-cg-and-pg-fl.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 0561bbe3a5e3dc6c7c99933dbd6f5e12781a2a1b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 5 Feb 2016 10:34:28 -0500
-Subject: [PATCH 0199/1110] drm/amdgpu: add a cgs interface to fetch cg and pg
- flags
-
-Needed to pass the cg and pg info to powerplay.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 6 ++++++
- drivers/gpu/drm/amd/include/cgs_common.h | 2 ++
- 2 files changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index a081dda..7a4b101 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -795,6 +795,12 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
- 	case CGS_SYSTEM_INFO_PCIE_MLW:
- 		sys_info->value = adev->pm.pcie_mlw_mask;
- 		break;
-+	case CGS_SYSTEM_INFO_CG_FLAGS:
-+		sys_info->value = adev->cg_flags;
-+		break;
-+	case CGS_SYSTEM_INFO_PG_FLAGS:
-+		sys_info->value = adev->pg_flags;
-+		break;
- 	default:
- 		return -ENODEV;
- 	}
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 713aec9..aec38fc 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -109,6 +109,8 @@ enum cgs_system_info_id {
- 	CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
- 	CGS_SYSTEM_INFO_PCIE_GEN_INFO,
- 	CGS_SYSTEM_INFO_PCIE_MLW,
-+	CGS_SYSTEM_INFO_CG_FLAGS,
-+	CGS_SYSTEM_INFO_PG_FLAGS,
- 	CGS_SYSTEM_INFO_ID_MAXIMUM,
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0200-drm-amdgpu-remove-unused-cg-defines.patch b/common/recipes-kernel/linux/files/0200-drm-amdgpu-remove-unused-cg-defines.patch
deleted file mode 100644
index 97dceaf3..00000000
--- a/common/recipes-kernel/linux/files/0200-drm-amdgpu-remove-unused-cg-defines.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 5548db570cf9b33dc0f176296c0916e8d330393a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 5 Feb 2016 10:37:29 -0500
-Subject: [PATCH 0200/1110] drm/amdgpu: remove unused cg defines
-
-Leftover from radeon.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 ---------
- 1 file changed, 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index cb51310..084f0df 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -134,15 +134,6 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define AMDGPU_RESET_VCE			(1 << 13)
- #define AMDGPU_RESET_VCE1			(1 << 14)
- 
--/* CG block flags */
--#define AMDGPU_CG_BLOCK_GFX			(1 << 0)
--#define AMDGPU_CG_BLOCK_MC			(1 << 1)
--#define AMDGPU_CG_BLOCK_SDMA			(1 << 2)
--#define AMDGPU_CG_BLOCK_UVD			(1 << 3)
--#define AMDGPU_CG_BLOCK_VCE			(1 << 4)
--#define AMDGPU_CG_BLOCK_HDP			(1 << 5)
--#define AMDGPU_CG_BLOCK_BIF			(1 << 6)
--
- /* CG flags */
- #define AMDGPU_CG_SUPPORT_GFX_MGCG		(1 << 0)
- #define AMDGPU_CG_SUPPORT_GFX_MGLS		(1 << 1)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0201-drma-dmgpu-move-cg-and-pg-flags-into-shared-headers.patch b/common/recipes-kernel/linux/files/0201-drma-dmgpu-move-cg-and-pg-flags-into-shared-headers.patch
deleted file mode 100644
index 19646633..00000000
--- a/common/recipes-kernel/linux/files/0201-drma-dmgpu-move-cg-and-pg-flags-into-shared-headers.patch
+++ /dev/null
@@ -1,722 +0,0 @@
-From ef576c8b7f73984116c416356abd7e80836a8b5c Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 5 Feb 2016 10:56:22 -0500
-Subject: [PATCH 0201/1110] drma/dmgpu: move cg and pg flags into shared
- headers
-
-So they can be used by powerplay.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  32 -------
- drivers/gpu/drm/amd/amdgpu/cik.c         | 154 +++++++++++++++----------------
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c    |   4 +-
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c      |   6 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    |  70 +++++++-------
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |  10 +-
- drivers/gpu/drm/amd/amdgpu/kv_dpm.c      |   8 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |   6 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |   4 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |   6 +-
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    |   4 +-
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    |   6 +-
- drivers/gpu/drm/amd/include/amd_shared.h |  32 +++++++
- 13 files changed, 171 insertions(+), 171 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 084f0df..a152e82 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -134,38 +134,6 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define AMDGPU_RESET_VCE			(1 << 13)
- #define AMDGPU_RESET_VCE1			(1 << 14)
- 
--/* CG flags */
--#define AMDGPU_CG_SUPPORT_GFX_MGCG		(1 << 0)
--#define AMDGPU_CG_SUPPORT_GFX_MGLS		(1 << 1)
--#define AMDGPU_CG_SUPPORT_GFX_CGCG		(1 << 2)
--#define AMDGPU_CG_SUPPORT_GFX_CGLS		(1 << 3)
--#define AMDGPU_CG_SUPPORT_GFX_CGTS		(1 << 4)
--#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
--#define AMDGPU_CG_SUPPORT_GFX_CP_LS		(1 << 6)
--#define AMDGPU_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
--#define AMDGPU_CG_SUPPORT_MC_LS			(1 << 8)
--#define AMDGPU_CG_SUPPORT_MC_MGCG		(1 << 9)
--#define AMDGPU_CG_SUPPORT_SDMA_LS		(1 << 10)
--#define AMDGPU_CG_SUPPORT_SDMA_MGCG		(1 << 11)
--#define AMDGPU_CG_SUPPORT_BIF_LS		(1 << 12)
--#define AMDGPU_CG_SUPPORT_UVD_MGCG		(1 << 13)
--#define AMDGPU_CG_SUPPORT_VCE_MGCG		(1 << 14)
--#define AMDGPU_CG_SUPPORT_HDP_LS		(1 << 15)
--#define AMDGPU_CG_SUPPORT_HDP_MGCG		(1 << 16)
--
--/* PG flags */
--#define AMDGPU_PG_SUPPORT_GFX_PG		(1 << 0)
--#define AMDGPU_PG_SUPPORT_GFX_SMG		(1 << 1)
--#define AMDGPU_PG_SUPPORT_GFX_DMG		(1 << 2)
--#define AMDGPU_PG_SUPPORT_UVD			(1 << 3)
--#define AMDGPU_PG_SUPPORT_VCE			(1 << 4)
--#define AMDGPU_PG_SUPPORT_CP			(1 << 5)
--#define AMDGPU_PG_SUPPORT_GDS			(1 << 6)
--#define AMDGPU_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
--#define AMDGPU_PG_SUPPORT_SDMA			(1 << 8)
--#define AMDGPU_PG_SUPPORT_ACP			(1 << 9)
--#define AMDGPU_PG_SUPPORT_SAMU			(1 << 10)
--
- /* GFX current status */
- #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
- #define AMDGPU_GFX_SAFE_MODE			0x00000001L
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 5c978e0..155965e 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -2335,72 +2335,72 @@ static int cik_common_early_init(void *handle)
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
- 		adev->cg_flags =
--			AMDGPU_CG_SUPPORT_GFX_MGCG |
--			AMDGPU_CG_SUPPORT_GFX_MGLS |
--			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
--			AMDGPU_CG_SUPPORT_GFX_CGLS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
--			AMDGPU_CG_SUPPORT_GFX_CP_LS |
--			AMDGPU_CG_SUPPORT_MC_LS |
--			AMDGPU_CG_SUPPORT_MC_MGCG |
--			AMDGPU_CG_SUPPORT_SDMA_MGCG |
--			AMDGPU_CG_SUPPORT_SDMA_LS |
--			AMDGPU_CG_SUPPORT_BIF_LS |
--			AMDGPU_CG_SUPPORT_VCE_MGCG |
--			AMDGPU_CG_SUPPORT_UVD_MGCG |
--			AMDGPU_CG_SUPPORT_HDP_LS |
--			AMDGPU_CG_SUPPORT_HDP_MGCG;
-+			AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			/*AMD_CG_SUPPORT_GFX_CGCG |*/
-+			AMD_CG_SUPPORT_GFX_CGLS |
-+			AMD_CG_SUPPORT_GFX_CGTS |
-+			AMD_CG_SUPPORT_GFX_CGTS_LS |
-+			AMD_CG_SUPPORT_GFX_CP_LS |
-+			AMD_CG_SUPPORT_MC_LS |
-+			AMD_CG_SUPPORT_MC_MGCG |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_VCE_MGCG |
-+			AMD_CG_SUPPORT_UVD_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
- 	case CHIP_HAWAII:
- 		adev->cg_flags =
--			AMDGPU_CG_SUPPORT_GFX_MGCG |
--			AMDGPU_CG_SUPPORT_GFX_MGLS |
--			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
--			AMDGPU_CG_SUPPORT_GFX_CGLS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS |
--			AMDGPU_CG_SUPPORT_GFX_CP_LS |
--			AMDGPU_CG_SUPPORT_MC_LS |
--			AMDGPU_CG_SUPPORT_MC_MGCG |
--			AMDGPU_CG_SUPPORT_SDMA_MGCG |
--			AMDGPU_CG_SUPPORT_SDMA_LS |
--			AMDGPU_CG_SUPPORT_BIF_LS |
--			AMDGPU_CG_SUPPORT_VCE_MGCG |
--			AMDGPU_CG_SUPPORT_UVD_MGCG |
--			AMDGPU_CG_SUPPORT_HDP_LS |
--			AMDGPU_CG_SUPPORT_HDP_MGCG;
-+			AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			/*AMD_CG_SUPPORT_GFX_CGCG |*/
-+			AMD_CG_SUPPORT_GFX_CGLS |
-+			AMD_CG_SUPPORT_GFX_CGTS |
-+			AMD_CG_SUPPORT_GFX_CP_LS |
-+			AMD_CG_SUPPORT_MC_LS |
-+			AMD_CG_SUPPORT_MC_MGCG |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_VCE_MGCG |
-+			AMD_CG_SUPPORT_UVD_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = 0x28;
- 		break;
- 	case CHIP_KAVERI:
- 		adev->cg_flags =
--			AMDGPU_CG_SUPPORT_GFX_MGCG |
--			AMDGPU_CG_SUPPORT_GFX_MGLS |
--			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
--			AMDGPU_CG_SUPPORT_GFX_CGLS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
--			AMDGPU_CG_SUPPORT_GFX_CP_LS |
--			AMDGPU_CG_SUPPORT_SDMA_MGCG |
--			AMDGPU_CG_SUPPORT_SDMA_LS |
--			AMDGPU_CG_SUPPORT_BIF_LS |
--			AMDGPU_CG_SUPPORT_VCE_MGCG |
--			AMDGPU_CG_SUPPORT_UVD_MGCG |
--			AMDGPU_CG_SUPPORT_HDP_LS |
--			AMDGPU_CG_SUPPORT_HDP_MGCG;
-+			AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			/*AMD_CG_SUPPORT_GFX_CGCG |*/
-+			AMD_CG_SUPPORT_GFX_CGLS |
-+			AMD_CG_SUPPORT_GFX_CGTS |
-+			AMD_CG_SUPPORT_GFX_CGTS_LS |
-+			AMD_CG_SUPPORT_GFX_CP_LS |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_VCE_MGCG |
-+			AMD_CG_SUPPORT_UVD_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG;
- 		adev->pg_flags =
--			/*AMDGPU_PG_SUPPORT_GFX_PG |
--			  AMDGPU_PG_SUPPORT_GFX_SMG |
--			  AMDGPU_PG_SUPPORT_GFX_DMG |*/
--			AMDGPU_PG_SUPPORT_UVD |
--			/*AMDGPU_PG_SUPPORT_VCE |
--			  AMDGPU_PG_SUPPORT_CP |
--			  AMDGPU_PG_SUPPORT_GDS |
--			  AMDGPU_PG_SUPPORT_RLC_SMU_HS |
--			  AMDGPU_PG_SUPPORT_ACP |
--			  AMDGPU_PG_SUPPORT_SAMU |*/
-+			/*AMD_PG_SUPPORT_GFX_PG |
-+			  AMD_PG_SUPPORT_GFX_SMG |
-+			  AMD_PG_SUPPORT_GFX_DMG |*/
-+			AMD_PG_SUPPORT_UVD |
-+			/*AMD_PG_SUPPORT_VCE |
-+			  AMD_PG_SUPPORT_CP |
-+			  AMD_PG_SUPPORT_GDS |
-+			  AMD_PG_SUPPORT_RLC_SMU_HS |
-+			  AMD_PG_SUPPORT_ACP |
-+			  AMD_PG_SUPPORT_SAMU |*/
- 			0;
- 		if (adev->pdev->device == 0x1312 ||
- 			adev->pdev->device == 0x1316 ||
-@@ -2412,29 +2412,29 @@ static int cik_common_early_init(void *handle)
- 	case CHIP_KABINI:
- 	case CHIP_MULLINS:
- 		adev->cg_flags =
--			AMDGPU_CG_SUPPORT_GFX_MGCG |
--			AMDGPU_CG_SUPPORT_GFX_MGLS |
--			/*AMDGPU_CG_SUPPORT_GFX_CGCG |*/
--			AMDGPU_CG_SUPPORT_GFX_CGLS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS |
--			AMDGPU_CG_SUPPORT_GFX_CGTS_LS |
--			AMDGPU_CG_SUPPORT_GFX_CP_LS |
--			AMDGPU_CG_SUPPORT_SDMA_MGCG |
--			AMDGPU_CG_SUPPORT_SDMA_LS |
--			AMDGPU_CG_SUPPORT_BIF_LS |
--			AMDGPU_CG_SUPPORT_VCE_MGCG |
--			AMDGPU_CG_SUPPORT_UVD_MGCG |
--			AMDGPU_CG_SUPPORT_HDP_LS |
--			AMDGPU_CG_SUPPORT_HDP_MGCG;
-+			AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			/*AMD_CG_SUPPORT_GFX_CGCG |*/
-+			AMD_CG_SUPPORT_GFX_CGLS |
-+			AMD_CG_SUPPORT_GFX_CGTS |
-+			AMD_CG_SUPPORT_GFX_CGTS_LS |
-+			AMD_CG_SUPPORT_GFX_CP_LS |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_VCE_MGCG |
-+			AMD_CG_SUPPORT_UVD_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG;
- 		adev->pg_flags =
--			/*AMDGPU_PG_SUPPORT_GFX_PG |
--			  AMDGPU_PG_SUPPORT_GFX_SMG | */
--			AMDGPU_PG_SUPPORT_UVD |
--			/*AMDGPU_PG_SUPPORT_VCE |
--			  AMDGPU_PG_SUPPORT_CP |
--			  AMDGPU_PG_SUPPORT_GDS |
--			  AMDGPU_PG_SUPPORT_RLC_SMU_HS |
--			  AMDGPU_PG_SUPPORT_SAMU |*/
-+			/*AMD_PG_SUPPORT_GFX_PG |
-+			  AMD_PG_SUPPORT_GFX_SMG | */
-+			AMD_PG_SUPPORT_UVD |
-+			/*AMD_PG_SUPPORT_VCE |
-+			  AMD_PG_SUPPORT_CP |
-+			  AMD_PG_SUPPORT_GDS |
-+			  AMD_PG_SUPPORT_RLC_SMU_HS |
-+			  AMD_PG_SUPPORT_SAMU |*/
- 			0;
- 		if (adev->asic_type == CHIP_KABINI) {
- 			if (adev->rev_id == 0)
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 5f712ce..c55ecf0 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -885,7 +885,7 @@ static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
- {
- 	u32 orig, data;
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
- 		WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
- 		WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
- 	} else {
-@@ -906,7 +906,7 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
- {
- 	u32 orig, data;
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
- 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
- 		data |= 0x100;
- 		if (orig != data)
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index 4dd17f2..9056355 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -445,13 +445,13 @@ static int cz_dpm_init(struct amdgpu_device *adev)
- 	pi->gfx_pg_threshold = 500;
- 	pi->caps_fps = true;
- 	/* uvd */
--	pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
-+	pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
- 	pi->caps_uvd_dpm = true;
- 	/* vce */
--	pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
-+	pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
- 	pi->caps_vce_dpm = true;
- 	/* acp */
--	pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
-+	pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
- 	pi->caps_acp_dpm = true;
- 
- 	pi->caps_stable_power_state = false;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 96d2073..9b1c430 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4122,7 +4122,7 @@ static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
- 
- 	orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
- 		gfx_v7_0_enable_gui_idle_interrupt(adev, true);
- 
- 		tmp = gfx_v7_0_halt_rlc(adev);
-@@ -4160,9 +4160,9 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
- {
- 	u32 data, orig, tmp = 0;
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
--		if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
--			if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
-+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
-+			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
- 				orig = data = RREG32(mmCP_MEM_SLP_CNTL);
- 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
- 				if (orig != data)
-@@ -4189,14 +4189,14 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
- 
- 		gfx_v7_0_update_rlc(adev, tmp);
- 
--		if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
-+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
- 			orig = data = RREG32(mmCGTS_SM_CTRL_REG);
- 			data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
- 			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
- 			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
- 			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
--			if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
--			    (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
-+			if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
-+			    (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
- 				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
- 			data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
- 			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
-@@ -4262,7 +4262,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
- 	u32 data, orig;
- 
- 	orig = data = RREG32(mmRLC_PG_CNTL);
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
- 		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
- 	else
- 		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
-@@ -4276,7 +4276,7 @@ static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
- 	u32 data, orig;
- 
- 	orig = data = RREG32(mmRLC_PG_CNTL);
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
- 		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
- 	else
- 		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-@@ -4289,7 +4289,7 @@ static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
- 	u32 data, orig;
- 
- 	orig = data = RREG32(mmRLC_PG_CNTL);
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
- 		data &= ~0x8000;
- 	else
- 		data |= 0x8000;
-@@ -4302,7 +4302,7 @@ static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
- 	u32 data, orig;
- 
- 	orig = data = RREG32(mmRLC_PG_CNTL);
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
- 		data &= ~0x2000;
- 	else
- 		data |= 0x2000;
-@@ -4383,7 +4383,7 @@ static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
- {
- 	u32 data, orig;
- 
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
- 		orig = data = RREG32(mmRLC_PG_CNTL);
- 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
- 		if (orig != data)
-@@ -4455,7 +4455,7 @@ static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
- 	u32 data, orig;
- 
- 	orig = data = RREG32(mmRLC_PG_CNTL);
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
- 		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
- 	else
- 		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-@@ -4469,7 +4469,7 @@ static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
- 	u32 data, orig;
- 
- 	orig = data = RREG32(mmRLC_PG_CNTL);
--	if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
-+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
- 		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
- 	else
- 		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-@@ -4636,15 +4636,15 @@ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
- 
- static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
- {
--	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
--			      AMDGPU_PG_SUPPORT_GFX_SMG |
--			      AMDGPU_PG_SUPPORT_GFX_DMG |
--			      AMDGPU_PG_SUPPORT_CP |
--			      AMDGPU_PG_SUPPORT_GDS |
--			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
-+	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-+			      AMD_PG_SUPPORT_GFX_SMG |
-+			      AMD_PG_SUPPORT_GFX_DMG |
-+			      AMD_PG_SUPPORT_CP |
-+			      AMD_PG_SUPPORT_GDS |
-+			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
- 		gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
- 		gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
--		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
-+		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
- 			gfx_v7_0_init_gfx_cgpg(adev);
- 			gfx_v7_0_enable_cp_pg(adev, true);
- 			gfx_v7_0_enable_gds_pg(adev, true);
-@@ -4656,14 +4656,14 @@ static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
- 
- static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
- {
--	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
--			      AMDGPU_PG_SUPPORT_GFX_SMG |
--			      AMDGPU_PG_SUPPORT_GFX_DMG |
--			      AMDGPU_PG_SUPPORT_CP |
--			      AMDGPU_PG_SUPPORT_GDS |
--			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
-+	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-+			      AMD_PG_SUPPORT_GFX_SMG |
-+			      AMD_PG_SUPPORT_GFX_DMG |
-+			      AMD_PG_SUPPORT_CP |
-+			      AMD_PG_SUPPORT_GDS |
-+			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
- 		gfx_v7_0_update_gfx_pg(adev, false);
--		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
-+		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
- 			gfx_v7_0_enable_cp_pg(adev, false);
- 			gfx_v7_0_enable_gds_pg(adev, false);
- 		}
-@@ -5540,14 +5540,14 @@ static int gfx_v7_0_set_powergating_state(void *handle,
- 	if (state == AMD_PG_STATE_GATE)
- 		gate = true;
- 
--	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
--			      AMDGPU_PG_SUPPORT_GFX_SMG |
--			      AMDGPU_PG_SUPPORT_GFX_DMG |
--			      AMDGPU_PG_SUPPORT_CP |
--			      AMDGPU_PG_SUPPORT_GDS |
--			      AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
-+	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-+			      AMD_PG_SUPPORT_GFX_SMG |
-+			      AMD_PG_SUPPORT_GFX_DMG |
-+			      AMD_PG_SUPPORT_CP |
-+			      AMD_PG_SUPPORT_GDS |
-+			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
- 		gfx_v7_0_update_gfx_pg(adev, gate);
--		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
-+		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
- 			gfx_v7_0_enable_cp_pg(adev, gate);
- 			gfx_v7_0_enable_gds_pg(adev, gate);
- 		}
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index c1a4ec8..c01b861 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -792,7 +792,7 @@ static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
- 
- 	for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
- 		orig = data = RREG32(mc_cg_registers[i]);
--		if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
-+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
- 			data |= mc_cg_ls_en[i];
- 		else
- 			data &= ~mc_cg_ls_en[i];
-@@ -809,7 +809,7 @@ static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
- 
- 	for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
- 		orig = data = RREG32(mc_cg_registers[i]);
--		if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
-+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
- 			data |= mc_cg_en[i];
- 		else
- 			data &= ~mc_cg_en[i];
-@@ -825,7 +825,7 @@ static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
- 
- 	orig = data = RREG32_PCIE(ixPCIE_CNTL2);
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
- 		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
- 		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
- 		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
-@@ -848,7 +848,7 @@ static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
- 
- 	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
- 		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
- 	else
- 		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
-@@ -864,7 +864,7 @@ static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
- 
- 	orig = data = RREG32(mmHDP_MEM_POWER_LS);
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
- 		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
- 	else
- 		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
-diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-index 7e9154c..654d767 100644
---- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-@@ -2859,11 +2859,11 @@ static int kv_dpm_init(struct amdgpu_device *adev)
- 	pi->voltage_drop_t = 0;
- 	pi->caps_sclk_throttle_low_notification = false;
- 	pi->caps_fps = false; /* true? */
--	pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
-+	pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
- 	pi->caps_uvd_dpm = true;
--	pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
--	pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false;
--	pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
-+	pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
-+	pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
-+	pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
- 	pi->caps_stable_p_state = false;
- 
- 	ret = kv_parse_sys_info_table(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index c982524..fbd3767 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -611,7 +611,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
- {
- 	u32 orig, data;
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
- 		data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
- 		data = 0xfff;
- 		WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
-@@ -830,7 +830,7 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
- 	bool gate = false;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG))
-+	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
- 		return 0;
- 
- 	if (state == AMD_CG_STATE_GATE)
-@@ -853,7 +853,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_UVD))
-+	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
- 		return 0;
- 
- 	if (state == AMD_PG_STATE_GATE) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index aad1ab5..57f1c5b 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -776,7 +776,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG))
-+	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
- 		return 0;
- 
- 	return 0;
-@@ -794,7 +794,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_UVD))
-+	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
- 		return 0;
- 
- 	if (state == AMD_PG_STATE_GATE) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index c41eda7..0b365b7 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -532,7 +532,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
- 	uvd_v6_0_mc_resume(adev);
- 
- 	/* Set dynamic clock gating in S/W control mode */
--	if (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG) {
-+	if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
- 		if (adev->flags & AMD_IS_APU)
- 			cz_set_uvd_clock_gating_branches(adev, false);
- 		else
-@@ -1000,7 +1000,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
- 
--	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG))
-+	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
- 		return 0;
- 
- 	if (enable) {
-@@ -1030,7 +1030,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_UVD))
-+	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
- 		return 0;
- 
- 	if (state == AMD_PG_STATE_GATE) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index d3ce608..a822eda 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -373,7 +373,7 @@ static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
- {
- 	bool sw_cg = false;
- 
--	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
- 		if (sw_cg)
- 			vce_v2_0_set_sw_cg(adev, true);
- 		else
-@@ -608,7 +608,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_VCE))
-+	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
- 		return 0;
- 
- 	if (state == AMD_PG_STATE_GATE)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index 797d12c..d662fa9 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -277,7 +277,7 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
- 		WREG32_P(mmVCE_STATUS, 0, ~1);
- 
- 		/* Set Clock-Gating off */
--		if (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)
-+		if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
- 			vce_v3_0_set_vce_sw_clock_gating(adev, false);
- 
- 		if (r) {
-@@ -676,7 +676,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
- 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
- 	int i;
- 
--	if (!(adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG))
-+	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
- 		return 0;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
-@@ -728,7 +728,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
- 	 */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_VCE))
-+	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
- 		return 0;
- 
- 	if (state == AMD_PG_STATE_GATE)
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index 1195d06..dbf7e64 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -85,6 +85,38 @@ enum amd_powergating_state {
- 	AMD_PG_STATE_UNGATE,
- };
- 
-+/* CG flags */
-+#define AMD_CG_SUPPORT_GFX_MGCG			(1 << 0)
-+#define AMD_CG_SUPPORT_GFX_MGLS			(1 << 1)
-+#define AMD_CG_SUPPORT_GFX_CGCG			(1 << 2)
-+#define AMD_CG_SUPPORT_GFX_CGLS			(1 << 3)
-+#define AMD_CG_SUPPORT_GFX_CGTS			(1 << 4)
-+#define AMD_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
-+#define AMD_CG_SUPPORT_GFX_CP_LS		(1 << 6)
-+#define AMD_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
-+#define AMD_CG_SUPPORT_MC_LS			(1 << 8)
-+#define AMD_CG_SUPPORT_MC_MGCG			(1 << 9)
-+#define AMD_CG_SUPPORT_SDMA_LS			(1 << 10)
-+#define AMD_CG_SUPPORT_SDMA_MGCG		(1 << 11)
-+#define AMD_CG_SUPPORT_BIF_LS			(1 << 12)
-+#define AMD_CG_SUPPORT_UVD_MGCG			(1 << 13)
-+#define AMD_CG_SUPPORT_VCE_MGCG			(1 << 14)
-+#define AMD_CG_SUPPORT_HDP_LS			(1 << 15)
-+#define AMD_CG_SUPPORT_HDP_MGCG			(1 << 16)
-+
-+/* PG flags */
-+#define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
-+#define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
-+#define AMD_PG_SUPPORT_GFX_DMG			(1 << 2)
-+#define AMD_PG_SUPPORT_UVD			(1 << 3)
-+#define AMD_PG_SUPPORT_VCE			(1 << 4)
-+#define AMD_PG_SUPPORT_CP			(1 << 5)
-+#define AMD_PG_SUPPORT_GDS			(1 << 6)
-+#define AMD_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
-+#define AMD_PG_SUPPORT_SDMA			(1 << 8)
-+#define AMD_PG_SUPPORT_ACP			(1 << 9)
-+#define AMD_PG_SUPPORT_SAMU			(1 << 10)
-+
- enum amd_pm_state_type {
- 	/* not used for dpm */
- 	POWER_STATE_TYPE_DEFAULT,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0202-drm-amdgpu-tonga-plumb-pg-flags-through-to-powerplay.patch b/common/recipes-kernel/linux/files/0202-drm-amdgpu-tonga-plumb-pg-flags-through-to-powerplay.patch
deleted file mode 100644
index b8d34dbe..00000000
--- a/common/recipes-kernel/linux/files/0202-drm-amdgpu-tonga-plumb-pg-flags-through-to-powerplay.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 22f6b2b04fa05f9d3334b03159056c185ec5b97c Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 5 Feb 2016 11:11:51 -0500
-Subject: [PATCH 0202/1110] drm/amdgpu/tonga: plumb pg flags through to
- powerplay
-
-Enable vce and uvd pg based on single set of pg flags.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 69c81c1..980d3bf 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4451,6 +4451,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 	pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
- 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
- 	phw_tonga_ulv_parm *ulv;
-+	struct cgs_system_info sys_info = {0};
- 
- 	PP_ASSERT_WITH_CODE((NULL != hwmgr),
- 		"Invalid Parameter!", return -1;);
-@@ -4619,10 +4620,19 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 		      PHM_PlatformCaps_UVDPowerGating);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 		      PHM_PlatformCaps_VCEPowerGating);
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
-+	result = cgs_query_system_info(hwmgr->device, &sys_info);
-+	if (!result) {
-+		if (sys_info.value & AMD_PG_SUPPORT_UVD)
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				      PHM_PlatformCaps_UVDPowerGating);
-+		if (sys_info.value & AMD_PG_SUPPORT_VCE)
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				      PHM_PlatformCaps_VCEPowerGating);
-+	}
- 
- 	if (0 == result) {
--		struct cgs_system_info sys_info = {0};
--
- 		data->is_tlu_enabled = 0;
- 		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
- 			TONGA_MAX_HARDWARE_POWERLEVELS;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0203-drm-amdgpu-cz-plumb-pg-flags-through-to-powerplay.patch b/common/recipes-kernel/linux/files/0203-drm-amdgpu-cz-plumb-pg-flags-through-to-powerplay.patch
deleted file mode 100644
index 1d5f771b..00000000
--- a/common/recipes-kernel/linux/files/0203-drm-amdgpu-cz-plumb-pg-flags-through-to-powerplay.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 4c4ba1ed5bccd255e238a718626f9a744dfbd70c Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 5 Feb 2016 11:23:28 -0500
-Subject: [PATCH 0203/1110] drm/amdgpu/cz: plumb pg flags through to powerplay
-
-Enable vce and uvd pg based on single set of pg flags.
-
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 80af87f..cf01177 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -174,6 +174,8 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	uint32_t i;
-+	struct cgs_system_info sys_info = {0};
-+	int result;
- 
- 	cz_hwmgr->gfx_ramp_step = 256*25/100;
- 
-@@ -251,6 +253,17 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- 		      PHM_PlatformCaps_UVDPowerGating);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 		      PHM_PlatformCaps_VCEPowerGating);
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
-+	result = cgs_query_system_info(hwmgr->device, &sys_info);
-+	if (!result) {
-+		if (sys_info.value & AMD_PG_SUPPORT_UVD)
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				      PHM_PlatformCaps_UVDPowerGating);
-+		if (sys_info.value & AMD_PG_SUPPORT_VCE)
-+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				      PHM_PlatformCaps_VCEPowerGating);
-+	}
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0204-drm-amdgpu-gfx8-fix-priv-reg-interrupt-enable.patch b/common/recipes-kernel/linux/files/0204-drm-amdgpu-gfx8-fix-priv-reg-interrupt-enable.patch
deleted file mode 100644
index c6c17fdb..00000000
--- a/common/recipes-kernel/linux/files/0204-drm-amdgpu-gfx8-fix-priv-reg-interrupt-enable.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 5505c9c273853949723c9ee37512fdcd312a6f9a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 18 Feb 2016 11:10:09 -0500
-Subject: [PATCH 0204/1110] drm/amdgpu/gfx8: fix priv reg interrupt enable
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Looks like a copy/paste typo.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Noticed-by: David Panariti <David.Panariti@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 1cb5741..7086ac1 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4996,7 +4996,7 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
- 	case AMDGPU_IRQ_STATE_ENABLE:
- 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
- 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
--					    PRIV_REG_INT_ENABLE, 0);
-+					    PRIV_REG_INT_ENABLE, 1);
- 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
- 		break;
- 	default:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0205-drm-amdgpu-fix-locking-in-force-performance-level.patch b/common/recipes-kernel/linux/files/0205-drm-amdgpu-fix-locking-in-force-performance-level.patch
deleted file mode 100644
index 3f444274..00000000
--- a/common/recipes-kernel/linux/files/0205-drm-amdgpu-fix-locking-in-force-performance-level.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 0388fd19426625532fed528f5702938345c2004a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 19 Feb 2016 15:18:45 -0500
-Subject: [PATCH 0205/1110] drm/amdgpu: fix locking in force performance level
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Looks like a copy paste typo when we added powerplay
-support.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 8edcdd7..e9ad9a5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -157,6 +157,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 		mutex_lock(&adev->pm.mutex);
- 		if (adev->pm.dpm.thermal_active) {
- 			count = -EINVAL;
-+			mutex_unlock(&adev->pm.mutex);
- 			goto fail;
- 		}
- 		ret = amdgpu_dpm_force_performance_level(adev, level);
-@@ -167,8 +168,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 		mutex_unlock(&adev->pm.mutex);
- 	}
- fail:
--	mutex_unlock(&adev->pm.mutex);
--
- 	return count;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0206-drm-amdgpu-pm-add-some-checks-for-PX.patch b/common/recipes-kernel/linux/files/0206-drm-amdgpu-pm-add-some-checks-for-PX.patch
deleted file mode 100644
index 1685b35c..00000000
--- a/common/recipes-kernel/linux/files/0206-drm-amdgpu-pm-add-some-checks-for-PX.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 8e7dc1e0ce2344e3d42e0ee1e2498c7bc753246b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 19 Feb 2016 15:30:15 -0500
-Subject: [PATCH 0206/1110] drm/amdgpu/pm: add some checks for PX
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-I.e., doesn't make sense to change power states or check the
-temperature when the asic is powered off.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index e9ad9a5..95a4a25 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -113,6 +113,10 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
- 
-+	if  ((adev->flags & AMD_IS_PX) &&
-+	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
-+		return snprintf(buf, PAGE_SIZE, "off\n");
-+
- 	if (adev->pp_enabled) {
- 		enum amd_dpm_forced_level level;
- 
-@@ -140,6 +144,11 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 	enum amdgpu_dpm_forced_level level;
- 	int ret = 0;
- 
-+	/* Can't force performance level when the card is off */
-+	if  ((adev->flags & AMD_IS_PX) &&
-+	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
-+		return -EINVAL;
-+
- 	if (strncmp("low", buf, strlen("low")) == 0) {
- 		level = AMDGPU_DPM_FORCED_LEVEL_LOW;
- 	} else if (strncmp("high", buf, strlen("high")) == 0) {
-@@ -181,8 +190,14 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
- 				      char *buf)
- {
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
-+	struct drm_device *ddev = adev->ddev;
- 	int temp;
- 
-+	/* Can't get temperature when the card is off */
-+	if  ((adev->flags & AMD_IS_PX) &&
-+	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
-+		return -EINVAL;
-+
- 	if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
- 		temp = 0;
- 	else
-@@ -847,12 +862,16 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
- 	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 	struct drm_device *dev = node->minor->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
-+	struct drm_device *ddev = adev->ddev;
- 
- 	if (!adev->pm.dpm_enabled) {
- 		seq_printf(m, "dpm not enabled\n");
- 		return 0;
- 	}
--	if (adev->pp_enabled) {
-+	if  ((adev->flags & AMD_IS_PX) &&
-+	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
-+		seq_printf(m, "PX asic powered off\n");
-+	} else if (adev->pp_enabled) {
- 		amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
- 	} else {
- 		mutex_lock(&adev->pm.mutex);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0207-amdgpu-fix-NULL-pointer-dereference-at-tonga_check_s.patch b/common/recipes-kernel/linux/files/0207-amdgpu-fix-NULL-pointer-dereference-at-tonga_check_s.patch
deleted file mode 100644
index 92fff479..00000000
--- a/common/recipes-kernel/linux/files/0207-amdgpu-fix-NULL-pointer-dereference-at-tonga_check_s.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 31a8dc088815792e81afc89eed55f48567bde4e9 Mon Sep 17 00:00:00 2001
-From: Bradley Pankow <btpankow@gmail.com>
-Date: Mon, 22 Feb 2016 20:11:47 -0500
-Subject: [PATCH 0207/1110] amdgpu: fix NULL pointer dereference at
- tonga_check_states_equal
-
-The event_data passed from pem_fini was not cleared upon initialization.
-This caused NULL checks to pass and cast_const_phw_tonga_power_state to
-attempt to dereference an invalid pointer. Clear the event_data in
-pem_init and pem_fini before calling pem_handle_event.
-
-Reviewed-by:  Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Bradley Pankow <btpankow@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
-index 52a3efc..46410e3 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
-@@ -31,7 +31,7 @@
- static int pem_init(struct pp_eventmgr *eventmgr)
- {
- 	int result = 0;
--	struct pem_event_data event_data;
-+	struct pem_event_data event_data = { {0} };
- 
- 	/* Initialize PowerPlay feature info */
- 	pem_init_feature_info(eventmgr);
-@@ -52,7 +52,7 @@ static int pem_init(struct pp_eventmgr *eventmgr)
- 
- static void pem_fini(struct pp_eventmgr *eventmgr)
- {
--	struct pem_event_data event_data;
-+	struct pem_event_data event_data = { {0} };
- 
- 	pem_uninit_featureInfo(eventmgr);
- 	pem_unregister_interrupts(eventmgr);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0208-drm-amdgpu-disable-direct-VM-updates-when-vm_debug-i.patch b/common/recipes-kernel/linux/files/0208-drm-amdgpu-disable-direct-VM-updates-when-vm_debug-i.patch
deleted file mode 100644
index 59c1787f..00000000
--- a/common/recipes-kernel/linux/files/0208-drm-amdgpu-disable-direct-VM-updates-when-vm_debug-i.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 1338d00055c756221e1d26d5e110f3712d037732 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 19 Feb 2016 10:03:03 +0100
-Subject: [PATCH 0208/1110] drm/amdgpu: disable direct VM updates when vm_debug
- is set
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-That should make user space bugs more obvious.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 8eb4b68..cb34ff6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -596,7 +596,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
- 		break;
- 	}
- 	ttm_eu_backoff_reservation(&ticket, &list);
--	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
-+	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
-+	    !amdgpu_vm_debug)
- 		amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
- 
- 	drm_gem_object_unreference_unlocked(gobj);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0209-drm-amd-powerplay-export-AMD_PP_EVENT_COMPLETE_INIT-.patch b/common/recipes-kernel/linux/files/0209-drm-amd-powerplay-export-AMD_PP_EVENT_COMPLETE_INIT-.patch
deleted file mode 100644
index 827fc734..00000000
--- a/common/recipes-kernel/linux/files/0209-drm-amd-powerplay-export-AMD_PP_EVENT_COMPLETE_INIT-.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From f4efc839b685590b3c8bb8dedd96ae3484a5d7c5 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 25 Feb 2016 17:16:52 +0800
-Subject: [PATCH 0209/1110] drm/amd/powerplay: export
- AMD_PP_EVENT_COMPLETE_INIT task to amdgpu.
-
-This is needed to init the dynamic states without a display.  To be
-used in the next commit.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c              | 5 ++++-
- drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c | 1 +
- 2 files changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index aa67244..589599f 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -402,8 +402,11 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
- 
- 		data.requested_ui_label = power_state_convert(ps);
- 		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
-+		break;
- 	}
--	break;
-+	case AMD_PP_EVENT_COMPLETE_INIT:
-+		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
-+		break;
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-index 83be3cf..6b52c78 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -165,6 +165,7 @@ const struct action_chain resume_action_chain = {
- };
- 
- static const pem_event_action *complete_init_event[] = {
-+	unblock_adjust_power_state_tasks,
- 	adjust_power_state_tasks,
- 	enable_gfx_clock_gating_tasks,
- 	enable_gfx_voltage_island_power_gating_tasks,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0210-drm-amd-powerplay-send-event-to-notify-powerplay-all.patch b/common/recipes-kernel/linux/files/0210-drm-amd-powerplay-send-event-to-notify-powerplay-all.patch
deleted file mode 100644
index ec603b4c..00000000
--- a/common/recipes-kernel/linux/files/0210-drm-amd-powerplay-send-event-to-notify-powerplay-all.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 42ade7639d6843929440e924008c0ce9d03802c4 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 25 Feb 2016 17:32:45 +0800
-Subject: [PATCH 0210/1110] drm/amd/powerplay: send event to notify powerplay
- all modules are initialized.
-
-with this event, powerplay can adjust current power state if needed.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index b9d0d55..3cb6d6c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -143,8 +143,10 @@ static int amdgpu_pp_late_init(void *handle)
- 					adev->powerplay.pp_handle);
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (adev->pp_enabled)
-+	if (adev->pp_enabled) {
- 		amdgpu_pm_sysfs_init(adev);
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
-+	}
- #endif
- 	return ret;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0211-drm-amdgpu-cz-enable-disable-vce-dpm-even-if-vce-pg-.patch b/common/recipes-kernel/linux/files/0211-drm-amdgpu-cz-enable-disable-vce-dpm-even-if-vce-pg-.patch
deleted file mode 100644
index 1f9a7382..00000000
--- a/common/recipes-kernel/linux/files/0211-drm-amdgpu-cz-enable-disable-vce-dpm-even-if-vce-pg-.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 1b7a34b147110b8044df2395d565f00df4df5312 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 25 Feb 2016 11:24:52 -0500
-Subject: [PATCH 0211/1110] drm/amdgpu/cz: enable/disable vce dpm even if vce
- pg is disabled
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-I missed this when cleaning up the vce pg handling.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index 9056355..208990a 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -2226,10 +2226,8 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
- 		}
- 	} else { /*pi->caps_vce_pg*/
- 		cz_update_vce_dpm(adev);
--		cz_enable_vce_dpm(adev, true);
-+		cz_enable_vce_dpm(adev, !gate);
- 	}
--
--	return;
- }
- 
- const struct amd_ip_funcs cz_dpm_ip_funcs = {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0212-drm-amdgpu-powerplay-cz-enable-disable-vce-dpm-indep.patch b/common/recipes-kernel/linux/files/0212-drm-amdgpu-powerplay-cz-enable-disable-vce-dpm-indep.patch
deleted file mode 100644
index ac737f5f..00000000
--- a/common/recipes-kernel/linux/files/0212-drm-amdgpu-powerplay-cz-enable-disable-vce-dpm-indep.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 7373c1413b1ae2a11b020db98d22add9adc8642d Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 29 Feb 2016 15:29:48 -0500
-Subject: [PATCH 0212/1110] drm/amdgpu/powerplay/cz: enable/disable vce dpm
- independent of vce pg
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If we don't disable it when vce is not in use, we use extra power
-if vce pg is disabled.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-index ad77008..ff08ce4 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-@@ -226,7 +226,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- 		}
- 	} else {
- 		cz_dpm_update_vce_dpm(hwmgr);
--		cz_enable_disable_vce_dpm(hwmgr, true);
-+		cz_enable_disable_vce_dpm(hwmgr, !bgate);
- 		return 0;
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0213-drm-amdgpu-cz-remove-commented-out-call-to-enable-vc.patch b/common/recipes-kernel/linux/files/0213-drm-amdgpu-cz-remove-commented-out-call-to-enable-vc.patch
deleted file mode 100644
index c75b8e91..00000000
--- a/common/recipes-kernel/linux/files/0213-drm-amdgpu-cz-remove-commented-out-call-to-enable-vc.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 798ac66ba4e59beb2f2e94a32969f0aee4abe171 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 29 Feb 2016 16:11:07 -0500
-Subject: [PATCH 0213/1110] drm/amdgpu/cz: remove commented out call to enable
- vce pg
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This code path is not currently enabled now that we properly
-respect the vce pg flags, so uncomment the actual pg calls
-so the code is as it should be we are eventually able to
-enable vce pg.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index 208990a..e7ef226 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -2202,8 +2202,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
- 							    AMD_PG_STATE_GATE);
- 
- 				cz_enable_vce_dpm(adev, false);
--				/* TODO: to figure out why vce can't be poweroff. */
--				/* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
-+				cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);
- 				pi->vce_power_gated = true;
- 			} else {
- 				cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0214-drm-amdgpu-dp-add-back-special-handling-for-NUTMEG.patch b/common/recipes-kernel/linux/files/0214-drm-amdgpu-dp-add-back-special-handling-for-NUTMEG.patch
deleted file mode 100644
index 6be0003a..00000000
--- a/common/recipes-kernel/linux/files/0214-drm-amdgpu-dp-add-back-special-handling-for-NUTMEG.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From c70815caa938048d1e78451bf2b90b1eb6f6b827 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 3 Mar 2016 19:34:28 -0500
-Subject: [PATCH 0214/1110] drm/amdgpu/dp: add back special handling for NUTMEG
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-When I fixed the dp rate selection in:
-3b73b168cffd9c392584d3f665021fa2190f8612
-drm/amdgpu: fix dp link rate selection (v2)
-I accidently dropped the special handling for NUTMEG
-DP bridge chips.  They require a fixed link rate.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
-index 21aacc1..bf731e9 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
-@@ -265,15 +265,27 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
- 	unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
- 	unsigned lane_num, i, max_pix_clock;
- 
--	for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
--		for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
--			max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
-+	if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
-+	    ENCODER_OBJECT_ID_NUTMEG) {
-+		for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
-+			max_pix_clock = (lane_num * 270000 * 8) / bpp;
- 			if (max_pix_clock >= pix_clock) {
- 				*dp_lanes = lane_num;
--				*dp_rate = link_rates[i];
-+				*dp_rate = 270000;
- 				return 0;
- 			}
- 		}
-+	} else {
-+		for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
-+			for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
-+				max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
-+				if (max_pix_clock >= pix_clock) {
-+					*dp_lanes = lane_num;
-+					*dp_rate = link_rates[i];
-+					return 0;
-+				}
-+			}
-+		}
- 	}
- 
- 	return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0215-drm-amd-powerplay-indent-a-couple-if-statements.patch b/common/recipes-kernel/linux/files/0215-drm-amd-powerplay-indent-a-couple-if-statements.patch
deleted file mode 100644
index 08f4668e..00000000
--- a/common/recipes-kernel/linux/files/0215-drm-amd-powerplay-indent-a-couple-if-statements.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 8b46404c2a790d4179b9a23741ad6d7d4cb71f3f Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Wed, 20 Jan 2016 13:17:48 +0300
-Subject: [PATCH 0215/1110] drm/amd/powerplay: indent a couple if statements
-
-We recently redid the indenting, but missed these two if statements.
-
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-index b7429a5..b10df32 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-@@ -293,7 +293,7 @@ fInt GetScaledFraction(int X, int factor)
- 	}
- 
- 	if (factor == 1)
--	return (ConvertToFraction(X));
-+		return ConvertToFraction(X);
- 
- 	fValue = fDivide(ConvertToFraction(X * uPow(-1, bNEGATED)), ConvertToFraction(factor));
- 
-@@ -371,7 +371,7 @@ fInt fDivide (fInt X, fInt Y)
- 	fZERO = ConvertToFraction(0);
- 
- 	if (Equal(Y, fZERO))
--	return fZERO;
-+		return fZERO;
- 
- 	longlongX = (int64_t)X.full;
- 	longlongY = (int64_t)Y.full;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0216-drm-amdgpu-fix-amdgpu_cs_get_threshold_for_moves-han.patch b/common/recipes-kernel/linux/files/0216-drm-amdgpu-fix-amdgpu_cs_get_threshold_for_moves-han.patch
deleted file mode 100644
index 92094287..00000000
--- a/common/recipes-kernel/linux/files/0216-drm-amdgpu-fix-amdgpu_cs_get_threshold_for_moves-han.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From 3a010d204e89688d424d44a82fa8f726eb6c1628 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 10 Jun 2016 19:27:25 +0530
-Subject: [PATCH 0216/1110] drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves
- handling
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The threshold should only be computed once.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 ++++++++++++---------
- 2 files changed, 14 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a152e82..501fd23 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1228,6 +1228,8 @@ struct amdgpu_cs_parser {
-         struct amdgpu_bo_list_entry     vm_pd;
- 	struct list_head	validated;
- 	struct fence		*fence;
-+        uint64_t                bytes_moved_threshold;
-+        uint64_t                bytes_moved;
- 
- 	struct amdgpu_ib	*ibs;
- 	uint32_t		num_ibs;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index b7d6438..9212787 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -336,14 +336,14 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
- 	return max(bytes_moved_threshold, 1024*1024ull);
- }
- 
--int amdgpu_cs_list_validate(struct amdgpu_device *adev,
--			    struct amdgpu_vm *vm,
-+int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 			    struct list_head *validated)
- {
-+        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-+        struct amdgpu_vm *vm = &fpriv->vm;
- 	struct amdgpu_bo_list_entry *lobj;
- 	struct amdgpu_bo *bo;
--	u64 bytes_moved = 0, initial_bytes_moved;
--	u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
-+        u64 initial_bytes_moved;
- 	int r;
- 
- 	list_for_each_entry(lobj, validated, tv.head) {
-@@ -363,16 +363,16 @@ int amdgpu_cs_list_validate(struct amdgpu_device *adev,
- 			 */
- 			if ((lobj->allowed_domains & current_domain) != 0 &&
- 			    (domain & current_domain) == 0 && /* will be moved */
--			    bytes_moved > bytes_moved_threshold) {
-+                            p->bytes_moved > p->bytes_moved_threshold) {
- 				/* don't move it */
- 				domain = current_domain;
- 			}
- 
- 		retry:
- 			amdgpu_ttm_placement_from_domain(bo, domain);
--			initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
-+                        initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
- 			r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
--			bytes_moved += atomic64_read(&adev->num_bytes_moved) -
-+                        p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
- 				       initial_bytes_moved;
- 
- 			if (unlikely(r)) {
-@@ -421,11 +421,14 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 
-         amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
- 
--        r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates);
-+        p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
-+        p->bytes_moved = 0;
-+ 
-+        r = amdgpu_cs_list_validate(p, &duplicates);
- 	if (r)
- 		goto error_validate;
- 
--        r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
-+        r = amdgpu_cs_list_validate(p, &p->validated);
- 
- error_validate:
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0217-drm-amdgpu-cleanup-amdgpu_cs_list_validate.patch b/common/recipes-kernel/linux/files/0217-drm-amdgpu-cleanup-amdgpu_cs_list_validate.patch
deleted file mode 100644
index a02a7c54..00000000
--- a/common/recipes-kernel/linux/files/0217-drm-amdgpu-cleanup-amdgpu_cs_list_validate.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From 15bb77b919b01ed6db2ed65e2da92a1c4df6b4a0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 10 Jun 2016 19:30:51 +0530
-Subject: [PATCH 0217/1110] drm/amdgpu: cleanup amdgpu_cs_list_validate
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to actually check the current placement. Just use the allowed domains
-when the threshold is reached.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 66 ++++++++++++++++------------------
- 1 file changed, 31 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 9212787..c4b4290 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -342,48 +342,44 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
-         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-         struct amdgpu_vm *vm = &fpriv->vm;
- 	struct amdgpu_bo_list_entry *lobj;
--	struct amdgpu_bo *bo;
-         u64 initial_bytes_moved;
- 	int r;
- 
- 	list_for_each_entry(lobj, validated, tv.head) {
--		bo = lobj->robj;
--		if (!bo->pin_count) {
--			u32 domain = lobj->prefered_domains;
--			u32 current_domain =
--				amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
--
--			/* Check if this buffer will be moved and don't move it
--			 * if we have moved too many buffers for this IB already.
--			 *
--			 * Note that this allows moving at least one buffer of
--			 * any size, because it doesn't take the current "bo"
--			 * into account. We don't want to disallow buffer moves
--			 * completely.
--			 */
--			if ((lobj->allowed_domains & current_domain) != 0 &&
--			    (domain & current_domain) == 0 && /* will be moved */
--                            p->bytes_moved > p->bytes_moved_threshold) {
--				/* don't move it */
--				domain = current_domain;
--			}
-+                struct amdgpu_bo *bo = lobj->robj;
-+                uint32_t domain;
-+
-+                lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
-+                if (bo->pin_count)
-+                        continue;
-+
-+               /* Avoid moving this one if we have moved too many buffers
-+                * for this IB already.
-+                *
-+                * Note that this allows moving at least one buffer of
-+                * any size, because it doesn't take the current "bo"
-+                * into account. We don't want to disallow buffer moves
-+                * completely.
-+                */
-+                if (p->bytes_moved <= p->bytes_moved_threshold)
-+                        domain = lobj->prefered_domains;
-+                else
-+                        domain = lobj->allowed_domains;
-+ 
-+        retry:
-+                amdgpu_ttm_placement_from_domain(bo, domain);
-+                initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
-+                r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
-+                p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
-+                               initial_bytes_moved;
-+ 
-+                if (unlikely(r)) {
-+                        if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
-+                                domain = lobj->allowed_domains;
-+                                goto retry;
- 
--		retry:
--			amdgpu_ttm_placement_from_domain(bo, domain);
--                        initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
--			r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
--                        p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
--				       initial_bytes_moved;
--
--			if (unlikely(r)) {
--				if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
--					domain = lobj->allowed_domains;
--					goto retry;
--				}
--				return r;
- 			}
- 		}
--		lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
- 	}
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0218-drm-amdgpu-group-VM-mapping-tree-with-its-lock-v2.patch b/common/recipes-kernel/linux/files/0218-drm-amdgpu-group-VM-mapping-tree-with-its-lock-v2.patch
deleted file mode 100644
index ac4909dc..00000000
--- a/common/recipes-kernel/linux/files/0218-drm-amdgpu-group-VM-mapping-tree-with-its-lock-v2.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 9d3616c9cb4ed48b4929f3d214997f97da1208b3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sat, 19 Dec 2015 19:42:05 +0100
-Subject: [PATCH 0218/1110] drm/amdgpu: group VM mapping tree with its lock
- (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-And also update the comment.
-
-v2: agd: rebase on usptream.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 501fd23..35d5221 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -892,6 +892,8 @@ struct amdgpu_vm_id {
- };
- 
- struct amdgpu_vm {
-+	/* tree of virtual addresses mapped */
-+	spinlock_t		it_lock;
- 	struct rb_root		va;
- 
- 	/* protecting invalidated */
-@@ -916,8 +918,7 @@ struct amdgpu_vm {
- 
- 	/* for id and flush management per ring */
- 	struct amdgpu_vm_id	ids[AMDGPU_MAX_RINGS];
--	/* for interval tree */
--	spinlock_t		it_lock;
-+
- 	/* protecting freed */
- 	spinlock_t		freed_lock;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0219-drm-amdgpu-cleanup-amdgpu_cs_parser-structure.patch b/common/recipes-kernel/linux/files/0219-drm-amdgpu-cleanup-amdgpu_cs_parser-structure.patch
deleted file mode 100644
index 791c2584..00000000
--- a/common/recipes-kernel/linux/files/0219-drm-amdgpu-cleanup-amdgpu_cs_parser-structure.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 72838599f8c5280d4540f4f85f55248a0c31b89f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 15 Dec 2015 14:41:33 +0100
-Subject: [PATCH 0219/1110] drm/amdgpu: cleanup amdgpu_cs_parser structure
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Remove unused user_ptr field, group fields by usage.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 24 ++++++++++++------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  1 -
- 2 files changed, 12 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 35d5221..8676505 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1214,28 +1214,28 @@ struct amdgpu_cs_chunk {
- 	uint32_t		chunk_id;
- 	uint32_t		length_dw;
- 	uint32_t		*kdata;
--	void __user		*user_ptr;
- };
- 
- struct amdgpu_cs_parser {
- 	struct amdgpu_device	*adev;
- 	struct drm_file		*filp;
- 	struct amdgpu_ctx	*ctx;
--	struct amdgpu_bo_list *bo_list;
-+	
- 	/* chunks */
- 	unsigned		nchunks;
- 	struct amdgpu_cs_chunk	*chunks;
--	/* relocations */
--        struct amdgpu_bo_list_entry     vm_pd;
--	struct list_head	validated;
--	struct fence		*fence;
--        uint64_t                bytes_moved_threshold;
--        uint64_t                bytes_moved;
--
--	struct amdgpu_ib	*ibs;
-+        /* indirect buffers */
- 	uint32_t		num_ibs;
--
--	struct ww_acquire_ctx	ticket;
-+	struct amdgpu_ib	*ibs;
-+ 
-+       /* buffer objects */
-+         struct ww_acquire_ctx           ticket;
-+         struct amdgpu_bo_list           *bo_list;
-+         struct amdgpu_bo_list_entry     vm_pd;
-+         struct list_head                validated;
-+         struct fence                    *fence;
-+         uint64_t                        bytes_moved_threshold;
-+         uint64_t                        bytes_moved;
- 
- 	/* user fence */
- 	struct amdgpu_user_fence	uf;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index c4b4290..f94469d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -217,7 +217,6 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 
- 		size = p->chunks[i].length_dw;
- 		cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
--		p->chunks[i].user_ptr = cdata;
- 
- 		p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
- 		if (p->chunks[i].kdata == NULL) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0220-drm-amdgpu-cleanup-amdgpu_cs_parser_relocs.patch b/common/recipes-kernel/linux/files/0220-drm-amdgpu-cleanup-amdgpu_cs_parser_relocs.patch
deleted file mode 100644
index d54cd8fd..00000000
--- a/common/recipes-kernel/linux/files/0220-drm-amdgpu-cleanup-amdgpu_cs_parser_relocs.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From f58575533de1b3e552a4e607186dd54a95df673b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 18 Dec 2015 20:33:52 +0100
-Subject: [PATCH 0220/1110] drm/amdgpu: cleanup amdgpu_cs_parser_relocs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Rename it to amdgpu_cs_parser_bos and move validation and bo list init there.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 ++++++++++-----------
- 1 file changed, 10 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index f94469d..e615aa0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -181,15 +181,12 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		goto free_chunk;
- 	}
- 
--	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
--
- 	/* get chunks */
--	INIT_LIST_HEAD(&p->validated);
- 	chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
- 	if (copy_from_user(chunk_array, chunk_array_user,
- 			   sizeof(uint64_t)*cs->in.num_chunks)) {
- 		ret = -EFAULT;
--		goto put_bo_list;
-+		goto put_ctx;
- 	}
- 
- 	p->nchunks = cs->in.num_chunks;
-@@ -197,7 +194,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 			    GFP_KERNEL);
- 	if (!p->chunks) {
- 		ret = -ENOMEM;
--		goto put_bo_list;
-+		goto put_ctx;
- 	}
- 
- 	for (i = 0; i < p->nchunks; i++) {
-@@ -273,9 +270,7 @@ free_partial_kdata:
- 	for (; i >= 0; i--)
- 		drm_free_large(p->chunks[i].kdata);
- 	kfree(p->chunks);
--put_bo_list:
--	if (p->bo_list)
--		amdgpu_bo_list_put(p->bo_list);
-+put_ctx:
- 	amdgpu_ctx_put(p->ctx);
- free_chunk:
- 	kfree(chunk_array);
-@@ -383,7 +378,8 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 	return 0;
- }
- 
--static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
-+static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
-+				union drm_amdgpu_cs *cs)
- {
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	struct amdgpu_cs_buckets buckets;
-@@ -391,12 +387,15 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 	bool need_mmap_lock = false;
- 	int i, r;
- 
-+	INIT_LIST_HEAD(&p->validated);
-+
-+	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
- 	if (p->bo_list) {
- 		need_mmap_lock = p->bo_list->has_userptr;
- 		amdgpu_cs_buckets_init(&buckets);
- 		for (i = 0; i < p->bo_list->num_entries; i++)
- 			amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
--								  p->bo_list->array[i].priority);
-+					      p->bo_list->array[i].priority);
- 
- 		amdgpu_cs_buckets_get_list(&buckets, &p->validated);
- 	}
-@@ -822,7 +821,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 		r = amdgpu_cs_handle_lockup(adev, r);
- 		return r;
- 	}
--	r = amdgpu_cs_parser_relocs(&parser);
-+	r = amdgpu_cs_parser_bos(&parser, data);
- 	if (r == -ENOMEM)
- 		DRM_ERROR("Not enough memory for command submission!\n");
- 	else if (r && r != -ERESTARTSYS)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0221-drm-amdgpu-cleanup-bo-list-bucket-handling.patch b/common/recipes-kernel/linux/files/0221-drm-amdgpu-cleanup-bo-list-bucket-handling.patch
deleted file mode 100644
index bdbc4a11..00000000
--- a/common/recipes-kernel/linux/files/0221-drm-amdgpu-cleanup-bo-list-bucket-handling.patch
+++ /dev/null
@@ -1,174 +0,0 @@
-From 401109ddd43b20b0bbf8965bac4c5d5ac68e8f5c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 18 Dec 2015 21:26:47 +0100
-Subject: [PATCH 0221/1110] drm/amdgpu: cleanup bo list bucket handling
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Move that into the BO list. No functional change.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h         |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 36 +++++++++++++++++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c      | 51 ++---------------------------
- 3 files changed, 39 insertions(+), 50 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 8676505..b7b5d2e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1064,6 +1064,8 @@ struct amdgpu_bo_list {
- 
- struct amdgpu_bo_list *
- amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
-+void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
-+			     struct list_head *validated);
- void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
- void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index f82a2dd..9da4bd0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -32,6 +32,9 @@
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
-+#define AMDGPU_BO_LIST_MAX_PRIORITY	32u
-+#define AMDGPU_BO_LIST_NUM_BUCKETS	(AMDGPU_BO_LIST_MAX_PRIORITY + 1)
-+
- static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv,
- 				 struct amdgpu_bo_list **result,
- 				 int *id)
-@@ -106,7 +109,8 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 
- 		entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
- 		drm_gem_object_unreference_unlocked(gobj);
--		entry->priority = info[i].bo_priority;
-+		entry->priority = min(info[i].bo_priority,
-+				      AMDGPU_BO_LIST_MAX_PRIORITY);
- 		entry->prefered_domains = entry->robj->initial_domain;
- 		entry->allowed_domains = entry->prefered_domains;
- 		if (entry->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
-@@ -161,6 +165,36 @@ amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id)
- 	return result;
- }
- 
-+void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
-+			     struct list_head *validated)
-+{
-+	/* This is based on the bucket sort with O(n) time complexity.
-+	 * An item with priority "i" is added to bucket[i]. The lists are then
-+	 * concatenated in descending order.
-+	 */
-+	struct list_head bucket[AMDGPU_BO_LIST_NUM_BUCKETS];
-+	unsigned i;
-+
-+	for (i = 0; i < AMDGPU_BO_LIST_NUM_BUCKETS; i++)
-+		INIT_LIST_HEAD(&bucket[i]);
-+
-+	/* Since buffers which appear sooner in the relocation list are
-+	 * likely to be used more often than buffers which appear later
-+	 * in the list, the sort mustn't change the ordering of buffers
-+	 * with the same priority, i.e. it must be stable.
-+	 */
-+	for (i = 0; i < list->num_entries; i++) {
-+		unsigned priority = list->array[i].priority;
-+
-+		list_add_tail(&list->array[i].tv.head,
-+			      &bucket[priority]);
-+	}
-+
-+	/* Connect the sorted buckets in the output list. */
-+	for (i = 0; i < AMDGPU_BO_LIST_NUM_BUCKETS; i++)
-+		list_splice(&bucket[i], validated);
-+}
-+
- void amdgpu_bo_list_put(struct amdgpu_bo_list *list)
- {
- 	mutex_unlock(&list->lock);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index e615aa0..76ec99d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -30,47 +30,6 @@
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
--#define AMDGPU_CS_MAX_PRIORITY		32u
--#define AMDGPU_CS_NUM_BUCKETS		(AMDGPU_CS_MAX_PRIORITY + 1)
--
--/* This is based on the bucket sort with O(n) time complexity.
-- * An item with priority "i" is added to bucket[i]. The lists are then
-- * concatenated in descending order.
-- */
--struct amdgpu_cs_buckets {
--	struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
--};
--
--static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
--{
--	unsigned i;
--
--	for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
--		INIT_LIST_HEAD(&b->bucket[i]);
--}
--
--static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
--				  struct list_head *item, unsigned priority)
--{
--	/* Since buffers which appear sooner in the relocation list are
--	 * likely to be used more often than buffers which appear later
--	 * in the list, the sort mustn't change the ordering of buffers
--	 * with the same priority, i.e. it must be stable.
--	 */
--	list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
--}
--
--static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
--				       struct list_head *out_list)
--{
--	unsigned i;
--
--	/* Connect the sorted buckets in the output list. */
--	for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
--		list_splice(&b->bucket[i], out_list);
--	}
--}
--
- int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
- 		       u32 ip_instance, u32 ring,
- 		       struct amdgpu_ring **out_ring)
-@@ -382,22 +341,16 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
- 				union drm_amdgpu_cs *cs)
- {
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
--	struct amdgpu_cs_buckets buckets;
- 	struct list_head duplicates;
- 	bool need_mmap_lock = false;
--	int i, r;
-+	int r;
- 
- 	INIT_LIST_HEAD(&p->validated);
- 
- 	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
- 	if (p->bo_list) {
- 		need_mmap_lock = p->bo_list->has_userptr;
--		amdgpu_cs_buckets_init(&buckets);
--		for (i = 0; i < p->bo_list->num_entries; i++)
--			amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
--					      p->bo_list->array[i].priority);
--
--		amdgpu_cs_buckets_get_list(&buckets, &p->validated);
-+                amdgpu_bo_list_get_list(p->bo_list, &p->validated);
- 	}
- 
-         INIT_LIST_HEAD(&duplicates);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0222-drm-amdgpu-keep-the-prefered-allowed-domains-in-the-.patch b/common/recipes-kernel/linux/files/0222-drm-amdgpu-keep-the-prefered-allowed-domains-in-the-.patch
deleted file mode 100644
index 39293ddb..00000000
--- a/common/recipes-kernel/linux/files/0222-drm-amdgpu-keep-the-prefered-allowed-domains-in-the-.patch
+++ /dev/null
@@ -1,348 +0,0 @@
-From 9e3086daf194226378bd489d9089328d3cf3cbc9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 18 Dec 2015 22:13:12 +0100
-Subject: [PATCH 0222/1110] drm/amdgpu: keep the prefered/allowed domains in
- the BO
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Stop copying that to the bo list entry, it doesn't change anyway.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h         |  6 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 14 ++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c      | 86 ++++++++++++++++++++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c     | 14 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 15 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c      |  4 --
- 6 files changed, 91 insertions(+), 48 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index b7b5d2e..d5e4503 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -445,8 +445,6 @@ struct amdgpu_bo_list_entry {
- 	struct amdgpu_bo		*robj;
- 	struct ttm_validate_buffer	tv;
- 	struct amdgpu_bo_va		*bo_va;
--	unsigned			prefered_domains;
--	unsigned			allowed_domains;
- 	uint32_t			priority;
- };
- 
-@@ -484,6 +482,8 @@ struct amdgpu_bo {
- 	struct list_head		list;
- 	/* Protected by tbo.reserved */
- 	u32				initial_domain;
-+        u32                             prefered_domains;
-+        u32                             allowed_domains;
- 	struct ttm_place		placements[AMDGPU_GEM_DOMAIN_MAX + 1];
- 	struct ttm_placement		placement;
- 	struct ttm_buffer_object	tbo;
-@@ -1064,8 +1064,6 @@ struct amdgpu_bo_list {
- 
- struct amdgpu_bo_list *
- amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
--void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
--			     struct list_head *validated);
- void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
- void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index 9da4bd0..1c6c0ac 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -111,23 +111,17 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 		drm_gem_object_unreference_unlocked(gobj);
- 		entry->priority = min(info[i].bo_priority,
- 				      AMDGPU_BO_LIST_MAX_PRIORITY);
--		entry->prefered_domains = entry->robj->initial_domain;
--		entry->allowed_domains = entry->prefered_domains;
--		if (entry->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
--			entry->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
--		if (amdgpu_ttm_tt_has_userptr(entry->robj->tbo.ttm)) {
-+                if (amdgpu_ttm_tt_has_userptr(entry->robj->tbo.ttm))
- 			has_userptr = true;
--			entry->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
--			entry->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
- 		}
- 		entry->tv.bo = &entry->robj->tbo;
- 		entry->tv.shared = true;
- 
--		if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
-+                if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
- 			gds_obj = entry->robj;
--		if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GWS)
-+                if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GWS)
- 			gws_obj = entry->robj;
--		if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_OA)
-+                if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_OA)
- 			oa_obj = entry->robj;
- 
- 		trace_amdgpu_bo_list_set(list, entry->robj);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 76ec99d..dba4bad 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -30,6 +30,47 @@
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
-+#define AMDGPU_CS_MAX_PRIORITY         32u
-+#define AMDGPU_CS_NUM_BUCKETS          (AMDGPU_CS_MAX_PRIORITY + 1)
-+
-+/* This is based on the bucket sort with O(n) time complexity.
-+ * An item with priority "i" is added to bucket[i]. The lists are then
-+ * concatenated in descending order.
-+ */
-+struct amdgpu_cs_buckets {
-+       struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
-+};
-+
-+static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
-+{
-+       unsigned i;
-+
-+       for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
-+               INIT_LIST_HEAD(&b->bucket[i]);
-+}
-+
-+static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
-+                                 struct list_head *item, unsigned priority)
-+{
-+       /* Since buffers which appear sooner in the relocation list are
-+        * likely to be used more often than buffers which appear later
-+        * in the list, the sort mustn't change the ordering of buffers
-+        * with the same priority, i.e. it must be stable.
-+        */
-+       list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
-+}
-+
-+static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
-+                                      struct list_head *out_list)
-+{
-+       unsigned i;
-+
-+       /* Connect the sorted buckets in the output list. */
-+       for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
-+               list_splice(&b->bucket[i], out_list);
-+       }
-+}
-+
- int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
- 		       u32 ip_instance, u32 ring,
- 		       struct amdgpu_ring **out_ring)
-@@ -107,8 +148,6 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 	}
- 
- 	p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo);
--	p->uf_entry.prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
--	p->uf_entry.allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
- 	p->uf_entry.priority = 0;
- 	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
- 	p->uf_entry.tv.shared = true;
-@@ -139,13 +178,16 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		ret = -EINVAL;
- 		goto free_chunk;
- 	}
-+ 
-+        p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
- 
- 	/* get chunks */
-+        INIT_LIST_HEAD(&p->validated);
- 	chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
- 	if (copy_from_user(chunk_array, chunk_array_user,
- 			   sizeof(uint64_t)*cs->in.num_chunks)) {
- 		ret = -EFAULT;
--		goto put_ctx;
-+                goto put_bo_list;
- 	}
- 
- 	p->nchunks = cs->in.num_chunks;
-@@ -153,7 +195,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 			    GFP_KERNEL);
- 	if (!p->chunks) {
- 		ret = -ENOMEM;
--		goto put_ctx;
-+                goto put_bo_list;
- 	}
- 
- 	for (i = 0; i < p->nchunks; i++) {
-@@ -229,7 +271,9 @@ free_partial_kdata:
- 	for (; i >= 0; i--)
- 		drm_free_large(p->chunks[i].kdata);
- 	kfree(p->chunks);
--put_ctx:
-+put_bo_list:
-+       if (p->bo_list)
-+               amdgpu_bo_list_put(p->bo_list);
- 	amdgpu_ctx_put(p->ctx);
- free_chunk:
- 	kfree(chunk_array);
-@@ -315,9 +359,9 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
-                 * completely.
-                 */
-                 if (p->bytes_moved <= p->bytes_moved_threshold)
--                        domain = lobj->prefered_domains;
-+                        domain = bo->prefered_domains;
-                 else
--                        domain = lobj->allowed_domains;
-+                        domain = bo->allowed_domains;
-  
-         retry:
-                 amdgpu_ttm_placement_from_domain(bo, domain);
-@@ -327,36 +371,38 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
-                                initial_bytes_moved;
-  
-                 if (unlikely(r)) {
--                        if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
--                                domain = lobj->allowed_domains;
--                                goto retry;
-+                        if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
-+                                domain = bo->allowed_domains;
- 
-+                                goto retry;
- 			}
-+			return r;
- 		}
- 	}
- 	return 0;
- }
- 
--static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
--				union drm_amdgpu_cs *cs)
-+static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- {
--	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-+        struct amdgpu_cs_buckets buckets;
- 	struct list_head duplicates;
- 	bool need_mmap_lock = false;
--	int r;
--
--	INIT_LIST_HEAD(&p->validated);
- 
--	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
-+	int i, r;
-+	
- 	if (p->bo_list) {
- 		need_mmap_lock = p->bo_list->has_userptr;
--                amdgpu_bo_list_get_list(p->bo_list, &p->validated);
-+                amdgpu_cs_buckets_init(&buckets);
-+                for (i = 0; i < p->bo_list->num_entries; i++)
-+                        amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
-+                                                                 p->bo_list->array[i].priority);
-+
-+               amdgpu_cs_buckets_get_list(&buckets, &p->validated);
- 	}
- 
-         INIT_LIST_HEAD(&duplicates);
-         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
- 
--	if (p->uf.bo)
- 		list_add(&p->uf_entry.tv.head, &p->validated);
- 
- 	if (need_mmap_lock)
-@@ -774,7 +820,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 		r = amdgpu_cs_handle_lockup(adev, r);
- 		return r;
- 	}
--	r = amdgpu_cs_parser_bos(&parser, data);
-+        r = amdgpu_cs_parser_relocs(&parser);
- 	if (r == -ENOMEM)
- 		DRM_ERROR("Not enough memory for command submission!\n");
- 	else if (r && r != -ERESTARTSYS)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index cb34ff6..95e12f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -252,6 +252,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
- 		goto handle_lockup;
- 
- 	bo = gem_to_amdgpu_bo(gobj);
-+        bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
-+        bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
- 	r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
- 	if (r)
- 		goto release_object;
-@@ -629,7 +631,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 
- 		info.bo_size = robj->gem_base.size;
- 		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
--		info.domains = robj->initial_domain;
-+                info.domains = robj->prefered_domains;
- 		info.domain_flags = robj->flags;
- 		amdgpu_bo_unreserve(robj);
- 		if (copy_to_user(out, &info, sizeof(info)))
-@@ -642,9 +644,13 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 			amdgpu_bo_unreserve(robj);
- 			break;
- 		}
--		robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
--						      AMDGPU_GEM_DOMAIN_GTT |
--						      AMDGPU_GEM_DOMAIN_CPU);
-+                robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
-+                                                        AMDGPU_GEM_DOMAIN_GTT |
-+                                                        AMDGPU_GEM_DOMAIN_CPU);
-+                robj->allowed_domains = robj->prefered_domains;
-+                if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
-+                        robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
-+ 
- 		amdgpu_bo_unreserve(robj);
- 		break;
- 	default:
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index 73628c7..b79a4f3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -254,12 +254,15 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- 	bo->adev = adev;
- 	INIT_LIST_HEAD(&bo->list);
- 	INIT_LIST_HEAD(&bo->va);
--	bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM |
--				       AMDGPU_GEM_DOMAIN_GTT |
--				       AMDGPU_GEM_DOMAIN_CPU |
--				       AMDGPU_GEM_DOMAIN_GDS |
--				       AMDGPU_GEM_DOMAIN_GWS |
--				       AMDGPU_GEM_DOMAIN_OA);
-+        bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
-+                                         AMDGPU_GEM_DOMAIN_GTT |
-+                                         AMDGPU_GEM_DOMAIN_CPU |
-+                                         AMDGPU_GEM_DOMAIN_GDS |
-+                                         AMDGPU_GEM_DOMAIN_GWS |
-+                                         AMDGPU_GEM_DOMAIN_OA);
-+        bo->allowed_domains = bo->prefered_domains;
-+        if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
-+                bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
- 
- 	bo->flags = flags;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index d495db3..8c729b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -88,8 +88,6 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-                         struct amdgpu_bo_list_entry *entry)
- {
-         entry->robj = vm->page_directory;
--        entry->prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
--        entry->allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
-         entry->priority = 0;
-         entry->tv.bo = &vm->page_directory->tbo;
-         entry->tv.shared = true;
-@@ -1131,8 +1129,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 		}
- 
-                 entry->robj = pt;
--                entry->prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
--                entry->allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
-                 entry->priority = 0;
-                 entry->tv.bo = &entry->robj->tbo;
-                 entry->tv.shared = true;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0223-drm-amdgpu-search-only-the-BO-list-for-VM-mappings.patch b/common/recipes-kernel/linux/files/0223-drm-amdgpu-search-only-the-BO-list-for-VM-mappings.patch
deleted file mode 100644
index 8fa44ee1..00000000
--- a/common/recipes-kernel/linux/files/0223-drm-amdgpu-search-only-the-BO-list-for-VM-mappings.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 5553613307a3a3b79f7972bb583d854c44101e58 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 22 Dec 2015 16:06:12 +0100
-Subject: [PATCH 0223/1110] drm/amdgpu: search only the BO list for VM mappings
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Make UVD/VCE VM emulation more efficient.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 20 +++++++++++++-------
- 1 file changed, 13 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index dba4bad..bb37911 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -971,30 +971,36 @@ struct amdgpu_bo_va_mapping *
- amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
- 		       uint64_t addr, struct amdgpu_bo **bo)
- {
--	struct amdgpu_bo_list_entry *reloc;
- 	struct amdgpu_bo_va_mapping *mapping;
-+	unsigned i;
-+
-+	if (!parser->bo_list)
-+		return NULL;
- 
- 	addr /= AMDGPU_GPU_PAGE_SIZE;
- 
--	list_for_each_entry(reloc, &parser->validated, tv.head) {
--		if (!reloc->bo_va)
-+	for (i = 0; i < parser->bo_list->num_entries; i++) {
-+		struct amdgpu_bo_list_entry *lobj;
-+
-+		lobj = &parser->bo_list->array[i];
-+		if (!lobj->bo_va)
- 			continue;
- 
--		list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
-+		list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
- 			if (mapping->it.start > addr ||
- 			    addr > mapping->it.last)
- 				continue;
- 
--			*bo = reloc->bo_va->bo;
-+			*bo = lobj->bo_va->bo;
- 			return mapping;
- 		}
- 
--		list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
-+		list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
- 			if (mapping->it.start > addr ||
- 			    addr > mapping->it.last)
- 				continue;
- 
--			*bo = reloc->bo_va->bo;
-+			*bo = lobj->bo_va->bo;
- 			return mapping;
- 		}
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0224-drm-amdgpu-try-to-find-BO-VAs-only-for-the-BOs-in-th.patch b/common/recipes-kernel/linux/files/0224-drm-amdgpu-try-to-find-BO-VAs-only-for-the-BOs-in-th.patch
deleted file mode 100644
index 57b3f700..00000000
--- a/common/recipes-kernel/linux/files/0224-drm-amdgpu-try-to-find-BO-VAs-only-for-the-BOs-in-th.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 09377bb6a04b3e24b6e1b393c0a9a223ad0f5a54 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 5 Jan 2016 16:03:39 +0100
-Subject: [PATCH 0224/1110] drm/amdgpu: try to find BO VAs only for the BOs in
- the list
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The other ones don't have any VAs assigned anyway or are uninteresting to us.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 +++++++++++++---
- 1 file changed, 13 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index bb37911..a07a525 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -336,8 +336,6 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
- int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 			    struct list_head *validated)
- {
--        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
--        struct amdgpu_vm *vm = &fpriv->vm;
- 	struct amdgpu_bo_list_entry *lobj;
-         u64 initial_bytes_moved;
- 	int r;
-@@ -346,7 +344,6 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
-                 struct amdgpu_bo *bo = lobj->robj;
-                 uint32_t domain;
- 
--                lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
-                 if (bo->pin_count)
-                         continue;
- 
-@@ -422,6 +419,19 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 		goto error_validate;
- 
-         r = amdgpu_cs_list_validate(p, &p->validated);
-+        if (r)
-+                goto error_validate;
-+
-+        if (p->bo_list) {
-+                struct amdgpu_vm *vm = &fpriv->vm;
-+                unsigned i;
-+ 
-+                for (i = 0; i < p->bo_list->num_entries; i++) {
-+                        struct amdgpu_bo *bo = p->bo_list->array[i].robj;
-+ 
-+                        p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
-+                }
-+        }
- 
- error_validate:
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0225-drm-amdgpu-clean-up-hw-semaphore-support-in-driver.patch b/common/recipes-kernel/linux/files/0225-drm-amdgpu-clean-up-hw-semaphore-support-in-driver.patch
deleted file mode 100644
index efd1e167..00000000
--- a/common/recipes-kernel/linux/files/0225-drm-amdgpu-clean-up-hw-semaphore-support-in-driver.patch
+++ /dev/null
@@ -1,1137 +0,0 @@
-From bcabc891096a6d65fa16c4819faa3ab1d0350587 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 15 Jan 2016 11:05:21 +0800
-Subject: [PATCH 0225/1110] drm/amdgpu: clean up hw semaphore support in driver
-
-No longer used.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile           |   2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  21 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |   4 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c | 102 -----------
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c      |  64 +------
- drivers/gpu/drm/amd/amdgpu/amdgpu_test.c      | 237 --------------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h     |  36 ----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c       |  24 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h       |   3 -
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c         |  26 +--
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         |  34 +---
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         |  42 +----
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c        |  27 +--
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c        |  28 +--
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c         |  29 +---
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c         |  29 +---
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c         |  29 +---
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c         |   2 +-
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c         |   2 +-
- 19 files changed, 17 insertions(+), 724 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index 20c9539..7e4568e 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -20,7 +20,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
- 	amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \
- 	amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \
- 	amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \
--	atombios_encoders.o amdgpu_semaphore.o amdgpu_sa.o atombios_i2c.o \
-+	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
- 	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
- 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index d5e4503..2d6e17d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -598,31 +598,10 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
- int amdgpu_mode_dumb_mmap(struct drm_file *filp,
- 			  struct drm_device *dev,
- 			  uint32_t handle, uint64_t *offset_p);
--
--/*
-- * Semaphores.
-- */
--struct amdgpu_semaphore {
--	struct amdgpu_sa_bo	*sa_bo;
--	signed			waiters;
--	uint64_t		gpu_addr;
--};
--
--int amdgpu_semaphore_create(struct amdgpu_device *adev,
--			    struct amdgpu_semaphore **semaphore);
--bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
--				  struct amdgpu_semaphore *semaphore);
--bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
--				struct amdgpu_semaphore *semaphore);
--void amdgpu_semaphore_free(struct amdgpu_device *adev,
--			   struct amdgpu_semaphore **semaphore,
--			   struct fence *fence);
--
- /*
-  * Synchronization
-  */
- struct amdgpu_sync {
--	struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
- 	struct fence		*sync_to[AMDGPU_MAX_RINGS];
- 	DECLARE_HASHTABLE(fences, 4);
- 	struct fence	        *last_vm_update;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 9ef1db8..78fac51 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -81,7 +81,6 @@ int amdgpu_exp_hw_support = 0;
- int amdgpu_enable_scheduler = 1;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
--int amdgpu_enable_semaphores = 0;
- int amdgpu_powerplay = -1;
- unsigned amdgpu_pcie_gen_cap = 0;
- unsigned amdgpu_pcie_lane_cap = 0;
-@@ -164,9 +163,6 @@ module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
- MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
- module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
- 
--MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))");
--module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
--
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
- module_param_named(powerplay, amdgpu_powerplay, int, 0444);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c
-deleted file mode 100644
-index 1caaf20..0000000
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c
-+++ /dev/null
-@@ -1,102 +0,0 @@
--/*
-- * Copyright 2011 Christian König.
-- * All Rights Reserved.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the
-- * "Software"), to deal in the Software without restriction, including
-- * without limitation the rights to use, copy, modify, merge, publish,
-- * distribute, sub license, and/or sell copies of the Software, and to
-- * permit persons to whom the Software is furnished to do so, subject to
-- * the following conditions:
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-- * USE OR OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * The above copyright notice and this permission notice (including the
-- * next paragraph) shall be included in all copies or substantial portions
-- * of the Software.
-- *
-- */
--/*
-- * Authors:
-- *    Christian König <deathsimple@vodafone.de>
-- */
--#include <drm/drmP.h>
--#include "amdgpu.h"
--#include "amdgpu_trace.h"
--
--int amdgpu_semaphore_create(struct amdgpu_device *adev,
--			    struct amdgpu_semaphore **semaphore)
--{
--	int r;
--
--	*semaphore = kmalloc(sizeof(struct amdgpu_semaphore), GFP_KERNEL);
--	if (*semaphore == NULL) {
--		return -ENOMEM;
--	}
--	r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
--			     &(*semaphore)->sa_bo, 8, 8);
--	if (r) {
--		kfree(*semaphore);
--		*semaphore = NULL;
--		return r;
--	}
--	(*semaphore)->waiters = 0;
--	(*semaphore)->gpu_addr = amdgpu_sa_bo_gpu_addr((*semaphore)->sa_bo);
--
--	*((uint64_t *)amdgpu_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0;
--
--	return 0;
--}
--
--bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
--				  struct amdgpu_semaphore *semaphore)
--{
--	trace_amdgpu_semaphore_signale(ring->idx, semaphore);
--
--	if (amdgpu_ring_emit_semaphore(ring, semaphore, false)) {
--		--semaphore->waiters;
--
--		/* for debugging lockup only, used by sysfs debug files */
--		ring->last_semaphore_signal_addr = semaphore->gpu_addr;
--		return true;
--	}
--	return false;
--}
--
--bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
--				struct amdgpu_semaphore *semaphore)
--{
--	trace_amdgpu_semaphore_wait(ring->idx, semaphore);
--
--	if (amdgpu_ring_emit_semaphore(ring, semaphore, true)) {
--		++semaphore->waiters;
--
--		/* for debugging lockup only, used by sysfs debug files */
--		ring->last_semaphore_wait_addr = semaphore->gpu_addr;
--		return true;
--	}
--	return false;
--}
--
--void amdgpu_semaphore_free(struct amdgpu_device *adev,
--			   struct amdgpu_semaphore **semaphore,
--			   struct fence *fence)
--{
--	if (semaphore == NULL || *semaphore == NULL) {
--		return;
--	}
--	if ((*semaphore)->waiters > 0) {
--		dev_err(adev->dev, "semaphore %p has more waiters than signalers,"
--			" hardware lockup imminent!\n", *semaphore);
--	}
--	amdgpu_sa_bo_free(adev, &(*semaphore)->sa_bo, fence);
--	kfree(*semaphore);
--	*semaphore = NULL;
--}
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index 181ce39..a6fee51 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -48,9 +48,6 @@ void amdgpu_sync_create(struct amdgpu_sync *sync)
- {
- 	unsigned i;
- 
--	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
--		sync->semaphores[i] = NULL;
--
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
- 		sync->sync_to[i] = NULL;
- 
-@@ -153,13 +150,13 @@ static void *amdgpu_sync_get_owner(struct fence *f)
- }
- 
- /**
-- * amdgpu_sync_resv - use the semaphores to sync to a reservation object
-+ * amdgpu_sync_resv - sync to a reservation object
-  *
-  * @sync: sync object to add fences from reservation object to
-  * @resv: reservation object with embedded fence
-  * @shared: true if we should only sync to the exclusive fence
-  *
-- * Sync to the fence using the semaphore objects
-+ * Sync to the fence
-  */
- int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     struct amdgpu_sync *sync,
-@@ -250,9 +247,6 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
- 		kfree(e);
- 	}
- 
--	if (amdgpu_enable_semaphores)
--		return 0;
--
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 		struct fence *fence = sync->sync_to[i];
- 		if (!fence)
-@@ -279,12 +273,10 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
- 		      struct amdgpu_ring *ring)
- {
- 	struct amdgpu_device *adev = ring->adev;
--	unsigned count = 0;
- 	int i, r;
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 		struct amdgpu_ring *other = adev->rings[i];
--		struct amdgpu_semaphore *semaphore;
- 		struct amdgpu_fence *fence;
- 
- 		if (!sync->sync_to[i])
-@@ -292,64 +284,19 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
- 
- 		fence = to_amdgpu_fence(sync->sync_to[i]);
- 
--		/* check if we really need to sync */
--		if (!amdgpu_enable_scheduler &&
--		    !amdgpu_fence_need_sync(fence, ring))
--			continue;
--
- 		/* prevent GPU deadlocks */
- 		if (!other->ready) {
- 			dev_err(adev->dev, "Syncing to a disabled ring!");
- 			return -EINVAL;
- 		}
- 
--		if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores) {
-+		if (amdgpu_enable_scheduler) {
- 			r = fence_wait(sync->sync_to[i], true);
- 			if (r)
- 				return r;
- 			continue;
- 		}
- 
--		if (count >= AMDGPU_NUM_SYNCS) {
--			/* not enough room, wait manually */
--			r = fence_wait(&fence->base, false);
--			if (r)
--				return r;
--			continue;
--		}
--		r = amdgpu_semaphore_create(adev, &semaphore);
--		if (r)
--			return r;
--
--		sync->semaphores[count++] = semaphore;
--
--		/* allocate enough space for sync command */
--		r = amdgpu_ring_alloc(other, 16);
--		if (r)
--			return r;
--
--		/* emit the signal semaphore */
--		if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
--			/* signaling wasn't successful wait manually */
--			amdgpu_ring_undo(other);
--			r = fence_wait(&fence->base, false);
--			if (r)
--				return r;
--			continue;
--		}
--
--		/* we assume caller has already allocated space on waiters ring */
--		if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
--			/* waiting wasn't successful wait manually */
--			amdgpu_ring_undo(other);
--			r = fence_wait(&fence->base, false);
--			if (r)
--				return r;
--			continue;
--		}
--
--		amdgpu_ring_commit(other);
--		amdgpu_fence_note_sync(fence, ring);
- 	}
- 
- 	return 0;
-@@ -362,7 +309,7 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
-  * @sync: sync object to use
-  * @fence: fence to use for the free
-  *
-- * Free the sync object by freeing all semaphores in it.
-+ * Free the sync object.
-  */
- void amdgpu_sync_free(struct amdgpu_device *adev,
- 		      struct amdgpu_sync *sync,
-@@ -378,9 +325,6 @@ void amdgpu_sync_free(struct amdgpu_device *adev,
- 		kfree(e);
- 	}
- 
--	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
--		amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
--
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
- 		fence_put(sync->sync_to[i]);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
-index 4865615..05a53f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
-@@ -238,144 +238,10 @@ void amdgpu_test_moves(struct amdgpu_device *adev)
- 		amdgpu_do_test_moves(adev);
- }
- 
--static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev,
--					     struct amdgpu_ring *ring,
--					     struct fence **fence)
--{
--	uint32_t handle = ring->idx ^ 0xdeafbeef;
--	int r;
--
--	if (ring == &adev->uvd.ring) {
--		r = amdgpu_uvd_get_create_msg(ring, handle, NULL);
--		if (r) {
--			DRM_ERROR("Failed to get dummy create msg\n");
--			return r;
--		}
--
--		r = amdgpu_uvd_get_destroy_msg(ring, handle, fence);
--		if (r) {
--			DRM_ERROR("Failed to get dummy destroy msg\n");
--			return r;
--		}
--
--	} else if (ring == &adev->vce.ring[0] ||
--		   ring == &adev->vce.ring[1]) {
--		r = amdgpu_vce_get_create_msg(ring, handle, NULL);
--		if (r) {
--			DRM_ERROR("Failed to get dummy create msg\n");
--			return r;
--		}
--
--		r = amdgpu_vce_get_destroy_msg(ring, handle, fence);
--		if (r) {
--			DRM_ERROR("Failed to get dummy destroy msg\n");
--			return r;
--		}
--	} else {
--		struct amdgpu_fence *a_fence = NULL;
--		r = amdgpu_ring_lock(ring, 64);
--		if (r) {
--			DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
--			return r;
--		}
--		amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, &a_fence);
--		amdgpu_ring_unlock_commit(ring);
--		*fence = &a_fence->base;
--	}
--	return 0;
--}
--
- void amdgpu_test_ring_sync(struct amdgpu_device *adev,
- 			   struct amdgpu_ring *ringA,
- 			   struct amdgpu_ring *ringB)
- {
--	struct fence *fence1 = NULL, *fence2 = NULL;
--	struct amdgpu_semaphore *semaphore = NULL;
--	int r;
--
--	r = amdgpu_semaphore_create(adev, &semaphore);
--	if (r) {
--		DRM_ERROR("Failed to create semaphore\n");
--		goto out_cleanup;
--	}
--
--	r = amdgpu_ring_lock(ringA, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_wait(ringA, semaphore);
--	amdgpu_ring_unlock_commit(ringA);
--
--	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1);
--	if (r)
--		goto out_cleanup;
--
--	r = amdgpu_ring_lock(ringA, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_wait(ringA, semaphore);
--	amdgpu_ring_unlock_commit(ringA);
--
--	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2);
--	if (r)
--		goto out_cleanup;
--
--	mdelay(1000);
--
--	if (fence_is_signaled(fence1)) {
--		DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
--		goto out_cleanup;
--	}
--
--	r = amdgpu_ring_lock(ringB, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring B %p\n", ringB);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_signal(ringB, semaphore);
--	amdgpu_ring_unlock_commit(ringB);
--
--	r = fence_wait(fence1, false);
--	if (r) {
--		DRM_ERROR("Failed to wait for sync fence 1\n");
--		goto out_cleanup;
--	}
--
--	mdelay(1000);
--
--	if (fence_is_signaled(fence2)) {
--		DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
--		goto out_cleanup;
--	}
--
--	r = amdgpu_ring_lock(ringB, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring B %p\n", ringB);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_signal(ringB, semaphore);
--	amdgpu_ring_unlock_commit(ringB);
--
--	r = fence_wait(fence2, false);
--	if (r) {
--		DRM_ERROR("Failed to wait for sync fence 1\n");
--		goto out_cleanup;
--	}
--
--out_cleanup:
--	amdgpu_semaphore_free(adev, &semaphore, NULL);
--
--	if (fence1)
--		fence_put(fence1);
--
--	if (fence2)
--		fence_put(fence2);
--
--	if (r)
--		printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
- }
- 
- static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
-@@ -383,109 +249,6 @@ static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
- 			    struct amdgpu_ring *ringB,
- 			    struct amdgpu_ring *ringC)
- {
--	struct fence *fenceA = NULL, *fenceB = NULL;
--	struct amdgpu_semaphore *semaphore = NULL;
--	bool sigA, sigB;
--	int i, r;
--
--	r = amdgpu_semaphore_create(adev, &semaphore);
--	if (r) {
--		DRM_ERROR("Failed to create semaphore\n");
--		goto out_cleanup;
--	}
--
--	r = amdgpu_ring_lock(ringA, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_wait(ringA, semaphore);
--	amdgpu_ring_unlock_commit(ringA);
--
--	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA);
--	if (r)
--		goto out_cleanup;
--
--	r = amdgpu_ring_lock(ringB, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_wait(ringB, semaphore);
--	amdgpu_ring_unlock_commit(ringB);
--	r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB);
--	if (r)
--		goto out_cleanup;
--
--	mdelay(1000);
--
--	if (fence_is_signaled(fenceA)) {
--		DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
--		goto out_cleanup;
--	}
--	if (fence_is_signaled(fenceB)) {
--		DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
--		goto out_cleanup;
--	}
--
--	r = amdgpu_ring_lock(ringC, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring B %p\n", ringC);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_signal(ringC, semaphore);
--	amdgpu_ring_unlock_commit(ringC);
--
--	for (i = 0; i < 30; ++i) {
--		mdelay(100);
--		sigA = fence_is_signaled(fenceA);
--		sigB = fence_is_signaled(fenceB);
--		if (sigA || sigB)
--			break;
--	}
--
--	if (!sigA && !sigB) {
--		DRM_ERROR("Neither fence A nor B has been signaled\n");
--		goto out_cleanup;
--	} else if (sigA && sigB) {
--		DRM_ERROR("Both fence A and B has been signaled\n");
--		goto out_cleanup;
--	}
--
--	DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
--
--	r = amdgpu_ring_lock(ringC, 64);
--	if (r) {
--		DRM_ERROR("Failed to lock ring B %p\n", ringC);
--		goto out_cleanup;
--	}
--	amdgpu_semaphore_emit_signal(ringC, semaphore);
--	amdgpu_ring_unlock_commit(ringC);
--
--	mdelay(1000);
--
--	r = fence_wait(fenceA, false);
--	if (r) {
--		DRM_ERROR("Failed to wait for sync fence A\n");
--		goto out_cleanup;
--	}
--	r = fence_wait(fenceB, false);
--	if (r) {
--		DRM_ERROR("Failed to wait for sync fence B\n");
--		goto out_cleanup;
--	}
--
--out_cleanup:
--	amdgpu_semaphore_free(adev, &semaphore, NULL);
--
--	if (fenceA)
--		fence_put(fenceA);
--
--	if (fenceB)
--		fence_put(fenceB);
--
--	if (r)
--		printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
- }
- 
- static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-index 8f9834a..2b94c63 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-@@ -247,42 +247,6 @@ TRACE_EVENT(amdgpu_bo_list_set,
- 	    TP_printk("list=%p, bo=%p", __entry->list, __entry->bo)
- );
- 
--DECLARE_EVENT_CLASS(amdgpu_semaphore_request,
--
--	    TP_PROTO(int ring, struct amdgpu_semaphore *sem),
--
--	    TP_ARGS(ring, sem),
--
--	    TP_STRUCT__entry(
--			     __field(int, ring)
--			     __field(signed, waiters)
--			     __field(uint64_t, gpu_addr)
--			     ),
--
--	    TP_fast_assign(
--			   __entry->ring = ring;
--			   __entry->waiters = sem->waiters;
--			   __entry->gpu_addr = sem->gpu_addr;
--			   ),
--
--	    TP_printk("ring=%u, waiters=%d, addr=%010Lx", __entry->ring,
--		      __entry->waiters, __entry->gpu_addr)
--);
--
--DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_signale,
--
--	    TP_PROTO(int ring, struct amdgpu_semaphore *sem),
--
--	    TP_ARGS(ring, sem)
--);
--
--DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_wait,
--
--	    TP_PROTO(int ring, struct amdgpu_semaphore *sem),
--
--	    TP_ARGS(ring, sem)
--);
--
- #endif
- 
- /* This part must be outside protection */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index bb0da76..9c3e271 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -744,30 +744,6 @@ out:
- }
- 
- /**
-- * amdgpu_vce_ring_emit_semaphore - emit a semaphore command
-- *
-- * @ring: engine to use
-- * @semaphore: address of semaphore
-- * @emit_wait: true=emit wait, false=emit signal
-- *
-- */
--bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
--				    struct amdgpu_semaphore *semaphore,
--				    bool emit_wait)
--{
--	uint64_t addr = semaphore->gpu_addr;
--
--	amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
--	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
--	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
--	amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
--	if (!emit_wait)
--		amdgpu_ring_write(ring, VCE_CMD_END);
--
--	return true;
--}
--
--/**
-  * amdgpu_vce_ring_emit_ib - execute indirect buffer
-  *
-  * @ring: engine to use
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-index ba2da8e..5538cf7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-@@ -34,9 +34,6 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 			       struct fence **fence);
- void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
- int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
--bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
--				    struct amdgpu_semaphore *semaphore,
--				    bool emit_wait);
- void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
- void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
- 				unsigned flags);
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index c55ecf0..dd2a0c1 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -295,30 +295,6 @@ static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
- }
- 
- /**
-- * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
-- *
-- * @ring: amdgpu_ring structure holding ring information
-- * @semaphore: amdgpu semaphore object
-- * @emit_wait: wait or signal semaphore
-- *
-- * Add a DMA semaphore packet to the ring wait on or signal
-- * other rings (CIK).
-- */
--static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
--					 struct amdgpu_semaphore *semaphore,
--					 bool emit_wait)
--{
--	u64 addr = semaphore->gpu_addr;
--	u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
--
--	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
--	amdgpu_ring_write(ring, addr & 0xfffffff8);
--	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
--
--	return true;
--}
--
--/**
-  * cik_sdma_gfx_stop - stop the gfx async dma engines
-  *
-  * @adev: amdgpu_device pointer
-@@ -1297,7 +1273,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = cik_sdma_ring_emit_ib,
- 	.emit_fence = cik_sdma_ring_emit_fence,
--	.emit_semaphore = cik_sdma_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
- 	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
- 	.test_ring = cik_sdma_ring_test_ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 9b1c430..52b3c2b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2516,36 +2516,6 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, upper_32_bits(seq));
- }
- 
--/**
-- * gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring
-- *
-- * @ring: amdgpu ring buffer object
-- * @semaphore: amdgpu semaphore object
-- * @emit_wait: Is this a sempahore wait?
-- *
-- * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
-- * from running ahead of semaphore waits.
-- */
--static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
--					 struct amdgpu_semaphore *semaphore,
--					 bool emit_wait)
--{
--	uint64_t addr = semaphore->gpu_addr;
--	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
--
--	amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
--	amdgpu_ring_write(ring, addr & 0xffffffff);
--	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
--
--	if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
--		/* Prevent the PFP from running ahead of the semaphore wait */
--		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
--		amdgpu_ring_write(ring, 0x0);
--	}
--
--	return true;
--}
--
- /*
-  * IB stuff
-  */
-@@ -5580,7 +5550,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
- 	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
--	.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-@@ -5596,7 +5566,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v7_0_ring_emit_ib_compute,
- 	.emit_fence = gfx_v7_0_ring_emit_fence_compute,
--	.emit_semaphore = gfx_v7_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 7086ac1..50e071a 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4762,44 +4762,6 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
- 
- }
- 
--/**
-- * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
-- *
-- * @ring: amdgpu ring buffer object
-- * @semaphore: amdgpu semaphore object
-- * @emit_wait: Is this a sempahore wait?
-- *
-- * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
-- * from running ahead of semaphore waits.
-- */
--static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
--					 struct amdgpu_semaphore *semaphore,
--					 bool emit_wait)
--{
--	uint64_t addr = semaphore->gpu_addr;
--	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
--
--	if (ring->adev->asic_type == CHIP_TOPAZ ||
--	    ring->adev->asic_type == CHIP_TONGA ||
--	    ring->adev->asic_type == CHIP_FIJI)
--		/* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
--		return false;
--	else {
--		amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
--		amdgpu_ring_write(ring, lower_32_bits(addr));
--		amdgpu_ring_write(ring, upper_32_bits(addr));
--		amdgpu_ring_write(ring, sel);
--	}
--
--	if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
--		/* Prevent the PFP from running ahead of the semaphore wait */
--		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
--		amdgpu_ring_write(ring, 0x0);
--	}
--
--	return true;
--}
--
- static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 					unsigned vm_id, uint64_t pd_addr)
- {
-@@ -5146,7 +5108,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
- 	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
--	.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-@@ -5162,7 +5124,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v8_0_ring_emit_ib_compute,
- 	.emit_fence = gfx_v8_0_ring_emit_fence_compute,
--	.emit_semaphore = gfx_v8_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index b1c7a9b..1eae05a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -335,31 +335,6 @@ static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
- }
- 
- /**
-- * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
-- *
-- * @ring: amdgpu_ring structure holding ring information
-- * @semaphore: amdgpu semaphore object
-- * @emit_wait: wait or signal semaphore
-- *
-- * Add a DMA semaphore packet to the ring wait on or signal
-- * other rings (VI).
-- */
--static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
--					  struct amdgpu_semaphore *semaphore,
--					  bool emit_wait)
--{
--	u64 addr = semaphore->gpu_addr;
--	u32 sig = emit_wait ? 0 : 1;
--
--	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
--			  SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
--	amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
--	amdgpu_ring_write(ring, upper_32_bits(addr));
--
--	return true;
--}
--
--/**
-  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
-  *
-  * @adev: amdgpu_device pointer
-@@ -1302,7 +1277,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = sdma_v2_4_ring_emit_ib,
- 	.emit_fence = sdma_v2_4_ring_emit_fence,
--	.emit_semaphore = sdma_v2_4_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
- 	.test_ring = sdma_v2_4_ring_test_ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index ad54c46..93930ae 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -444,32 +444,6 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
- 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
- }
- 
--
--/**
-- * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
-- *
-- * @ring: amdgpu_ring structure holding ring information
-- * @semaphore: amdgpu semaphore object
-- * @emit_wait: wait or signal semaphore
-- *
-- * Add a DMA semaphore packet to the ring wait on or signal
-- * other rings (VI).
-- */
--static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
--					  struct amdgpu_semaphore *semaphore,
--					  bool emit_wait)
--{
--	u64 addr = semaphore->gpu_addr;
--	u32 sig = emit_wait ? 0 : 1;
--
--	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
--			  SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
--	amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
--	amdgpu_ring_write(ring, upper_32_bits(addr));
--
--	return true;
--}
--
- /**
-  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
-  *
-@@ -1570,7 +1544,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = sdma_v3_0_ring_emit_ib,
- 	.emit_fence = sdma_v3_0_ring_emit_fence,
--	.emit_semaphore = sdma_v3_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
- 	.test_ring = sdma_v3_0_ring_test_ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index fbd3767..65961e4 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -439,33 +439,6 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
- }
- 
- /**
-- * uvd_v4_2_ring_emit_semaphore - emit semaphore command
-- *
-- * @ring: amdgpu_ring pointer
-- * @semaphore: semaphore to emit commands for
-- * @emit_wait: true if we should emit a wait command
-- *
-- * Emit a semaphore command (either wait or signal) to the UVD ring.
-- */
--static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring,
--					 struct amdgpu_semaphore *semaphore,
--					 bool emit_wait)
--{
--	uint64_t addr = semaphore->gpu_addr;
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
--	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
--	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
--	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
--
--	return true;
--}
--
--/**
-  * uvd_v4_2_ring_test_ring - register write test
-  *
-  * @ring: amdgpu_ring pointer
-@@ -888,7 +861,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
- 	.parse_cs = amdgpu_uvd_ring_parse_cs,
- 	.emit_ib = uvd_v4_2_ring_emit_ib,
- 	.emit_fence = uvd_v4_2_ring_emit_fence,
--	.emit_semaphore = uvd_v4_2_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.test_ring = uvd_v4_2_ring_test_ring,
- 	.test_ib = uvd_v4_2_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 57f1c5b..2a4a21a 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -483,33 +483,6 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
- }
- 
- /**
-- * uvd_v5_0_ring_emit_semaphore - emit semaphore command
-- *
-- * @ring: amdgpu_ring pointer
-- * @semaphore: semaphore to emit commands for
-- * @emit_wait: true if we should emit a wait command
-- *
-- * Emit a semaphore command (either wait or signal) to the UVD ring.
-- */
--static bool uvd_v5_0_ring_emit_semaphore(struct amdgpu_ring *ring,
--					 struct amdgpu_semaphore *semaphore,
--					 bool emit_wait)
--{
--	uint64_t addr = semaphore->gpu_addr;
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
--	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
--	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
--	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
--
--	return true;
--}
--
--/**
-  * uvd_v5_0_ring_test_ring - register write test
-  *
-  * @ring: amdgpu_ring pointer
-@@ -829,7 +802,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
- 	.parse_cs = amdgpu_uvd_ring_parse_cs,
- 	.emit_ib = uvd_v5_0_ring_emit_ib,
- 	.emit_fence = uvd_v5_0_ring_emit_fence,
--	.emit_semaphore = uvd_v5_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.test_ring = uvd_v5_0_ring_test_ring,
- 	.test_ib = uvd_v5_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 0b365b7..dc59a53 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -722,33 +722,6 @@ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
- }
- 
- /**
-- * uvd_v6_0_ring_emit_semaphore - emit semaphore command
-- *
-- * @ring: amdgpu_ring pointer
-- * @semaphore: semaphore to emit commands for
-- * @emit_wait: true if we should emit a wait command
-- *
-- * Emit a semaphore command (either wait or signal) to the UVD ring.
-- */
--static bool uvd_v6_0_ring_emit_semaphore(struct amdgpu_ring *ring,
--					 struct amdgpu_semaphore *semaphore,
--					 bool emit_wait)
--{
--	uint64_t addr = semaphore->gpu_addr;
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));
--	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));
--	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
--
--	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));
--	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
--
--	return true;
--}
--
--/**
-  * uvd_v6_0_ring_test_ring - register write test
-  *
-  * @ring: amdgpu_ring pointer
-@@ -1065,7 +1038,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
- 	.parse_cs = amdgpu_uvd_ring_parse_cs,
- 	.emit_ib = uvd_v6_0_ring_emit_ib,
- 	.emit_fence = uvd_v6_0_ring_emit_fence,
--	.emit_semaphore = uvd_v6_0_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.test_ring = uvd_v6_0_ring_test_ring,
- 	.test_ib = uvd_v6_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index a822eda..6e48cc6 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -642,7 +642,7 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
- 	.parse_cs = amdgpu_vce_ring_parse_cs,
- 	.emit_ib = amdgpu_vce_ring_emit_ib,
- 	.emit_fence = amdgpu_vce_ring_emit_fence,
--	.emit_semaphore = amdgpu_vce_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.test_ring = amdgpu_vce_ring_test_ring,
- 	.test_ib = amdgpu_vce_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index d662fa9..e3b47bc 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -762,7 +762,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
- 	.parse_cs = amdgpu_vce_ring_parse_cs,
- 	.emit_ib = amdgpu_vce_ring_emit_ib,
- 	.emit_fence = amdgpu_vce_ring_emit_fence,
--	.emit_semaphore = amdgpu_vce_ring_emit_semaphore,
-+	.emit_semaphore = NULL,
- 	.test_ring = amdgpu_vce_ring_test_ring,
- 	.test_ib = amdgpu_vce_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0226-drm-amdgpu-cleanup-amdgpu_sync_rings-V2.patch b/common/recipes-kernel/linux/files/0226-drm-amdgpu-cleanup-amdgpu_sync_rings-V2.patch
deleted file mode 100644
index 6e1ff374..00000000
--- a/common/recipes-kernel/linux/files/0226-drm-amdgpu-cleanup-amdgpu_sync_rings-V2.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From 65eeb8fd02011de3e023be0569a727c420ef2340 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 15 Jan 2016 11:12:42 +0800
-Subject: [PATCH 0226/1110] drm/amdgpu: cleanup amdgpu_sync_rings V2
-
-No longer needed now that semaphores are gone.
-
-V2: remove the first amdgpu_sync_wait in amdgpu_ib_schedule
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com> (V1)
-Reviewed-by: Monk Liu <monk.liu@amd.com> (V2)
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  2 --
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   | 10 +++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 42 --------------------------------
- 3 files changed, 3 insertions(+), 51 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 2d6e17d..1ab88b5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -614,8 +614,6 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     struct amdgpu_sync *sync,
- 		     struct reservation_object *resv,
- 		     void *owner);
--int amdgpu_sync_rings(struct amdgpu_sync *sync,
--		      struct amdgpu_ring *ring);
- struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
- int amdgpu_sync_wait(struct amdgpu_sync *sync);
- void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 9e25eda..3b58d70 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -141,11 +141,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 		dev_err(adev->dev, "couldn't schedule ib\n");
- 		return -EINVAL;
- 	}
--	r = amdgpu_sync_wait(&ibs->sync);
--	if (r) {
--		dev_err(adev->dev, "IB sync failed (%d).\n", r);
--		return r;
--	}
-+
- 	r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
- 	if (r) {
- 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
-@@ -161,10 +157,10 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 		}
- 	}
- 
--	r = amdgpu_sync_rings(&ibs->sync, ring);
-+	r = amdgpu_sync_wait(&ibs->sync);
- 	if (r) {
- 		amdgpu_ring_unlock_undo(ring);
--		dev_err(adev->dev, "failed to sync rings (%d)\n", r);
-+		dev_err(adev->dev, "failed to sync wait (%d)\n", r);
- 		return r;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index a6fee51..7f12a4d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -261,48 +261,6 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
- }
- 
- /**
-- * amdgpu_sync_rings - sync ring to all registered fences
-- *
-- * @sync: sync object to use
-- * @ring: ring that needs sync
-- *
-- * Ensure that all registered fences are signaled before letting
-- * the ring continue. The caller must hold the ring lock.
-- */
--int amdgpu_sync_rings(struct amdgpu_sync *sync,
--		      struct amdgpu_ring *ring)
--{
--	struct amdgpu_device *adev = ring->adev;
--	int i, r;
--
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		struct amdgpu_ring *other = adev->rings[i];
--		struct amdgpu_fence *fence;
--
--		if (!sync->sync_to[i])
--			continue;
--
--		fence = to_amdgpu_fence(sync->sync_to[i]);
--
--		/* prevent GPU deadlocks */
--		if (!other->ready) {
--			dev_err(adev->dev, "Syncing to a disabled ring!");
--			return -EINVAL;
--		}
--
--		if (amdgpu_enable_scheduler) {
--			r = fence_wait(sync->sync_to[i], true);
--			if (r)
--				return r;
--			continue;
--		}
--
--	}
--
--	return 0;
--}
--
--/**
-  * amdgpu_sync_free - free the sync object
-  *
-  * @adev: amdgpu_device pointer
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0227-drm-amdgpu-clean-up-non-scheduler-code-path-v2.patch b/common/recipes-kernel/linux/files/0227-drm-amdgpu-clean-up-non-scheduler-code-path-v2.patch
deleted file mode 100644
index 3303814c..00000000
--- a/common/recipes-kernel/linux/files/0227-drm-amdgpu-clean-up-non-scheduler-code-path-v2.patch
+++ /dev/null
@@ -1,378 +0,0 @@
-From 01607789c113795bf3b0c406c61246718290ff1d Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 15 Jan 2016 11:25:00 +0800
-Subject: [PATCH 0227/1110] drm/amdgpu: clean up non-scheduler code path (v2)
-
-Non-scheduler code is longer supported.
-
-v2: agd: rebased on upstream
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c    | 11 +------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c   | 48 ++++++++++++++-----------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  4 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 39 ++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c    |  4 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 44 ++++++++++++----------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  4 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |  4 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c   |  6 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  9 ++----
- 11 files changed, 64 insertions(+), 110 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1ab88b5..1e9452b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -82,7 +82,6 @@ extern int amdgpu_vm_size;
- extern int amdgpu_vm_block_size;
- extern int amdgpu_vm_fault_stop;
- extern int amdgpu_vm_debug;
--extern int amdgpu_enable_scheduler;
- extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
- extern int amdgpu_enable_semaphores;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index a07a525..ddc8339 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -856,7 +856,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 	if (r)
- 		goto out;
- 
--	if (amdgpu_enable_scheduler && parser.num_ibs) {
-+	if (parser.num_ibs) {
- 		struct amdgpu_ring * ring = parser.ibs->ring;
- 		struct amd_sched_fence *fence;
- 		struct amdgpu_job *job;
-@@ -901,15 +901,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 
- 		trace_amdgpu_cs_ioctl(job);
- 		amd_sched_entity_push_job(&job->base);
--
--	} else {
--		struct amdgpu_fence *fence;
--
--		r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs,
--				       parser.filp);
--		fence = parser.ibs[parser.num_ibs - 1].fence;
--		parser.fence = fence_get(&fence->base);
--		cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
- 	}
- 
- out:
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index 17d1fb1..f1f4b45 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -45,29 +45,27 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 		ctx->rings[i].fences = (void *)ctx->fences + sizeof(struct fence *) *
- 			amdgpu_sched_jobs * i;
- 	}
--	if (amdgpu_enable_scheduler) {
--		/* create context entity for each ring */
--		for (i = 0; i < adev->num_rings; i++) {
--			struct amd_sched_rq *rq;
--			if (pri >= AMD_SCHED_MAX_PRIORITY) {
--				kfree(ctx->fences);
--				return -EINVAL;
--			}
--			rq = &adev->rings[i]->sched.sched_rq[pri];
--			r = amd_sched_entity_init(&adev->rings[i]->sched,
--						  &ctx->rings[i].entity,
--						  rq, amdgpu_sched_jobs);
--			if (r)
--				break;
--		}
--
--		if (i < adev->num_rings) {
--			for (j = 0; j < i; j++)
--				amd_sched_entity_fini(&adev->rings[j]->sched,
--						      &ctx->rings[j].entity);
-+	/* create context entity for each ring */
-+	for (i = 0; i < adev->num_rings; i++) {
-+		struct amd_sched_rq *rq;
-+		if (pri >= AMD_SCHED_MAX_PRIORITY) {
- 			kfree(ctx->fences);
--			return r;
-+			return -EINVAL;
- 		}
-+		rq = &adev->rings[i]->sched.sched_rq[pri];
-+		r = amd_sched_entity_init(&adev->rings[i]->sched,
-+					  &ctx->rings[i].entity,
-+					  rq, amdgpu_sched_jobs);
-+		if (r)
-+			break;
-+	}
-+
-+	if (i < adev->num_rings) {
-+		for (j = 0; j < i; j++)
-+			amd_sched_entity_fini(&adev->rings[j]->sched,
-+					      &ctx->rings[j].entity);
-+		kfree(ctx->fences);
-+		return r;
- 	}
- 	return 0;
- }
-@@ -85,11 +83,9 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
- 			fence_put(ctx->rings[i].fences[j]);
- 	kfree(ctx->fences);
- 
--	if (amdgpu_enable_scheduler) {
--		for (i = 0; i < adev->num_rings; i++)
--			amd_sched_entity_fini(&adev->rings[i]->sched,
--					      &ctx->rings[i].entity);
--	}
-+	for (i = 0; i < adev->num_rings; i++)
-+		amd_sched_entity_fini(&adev->rings[i]->sched,
-+				      &ctx->rings[i].entity);
- }
- 
- static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 78fac51..58c81a4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -78,7 +78,6 @@ int amdgpu_vm_block_size = -1;
- int amdgpu_vm_fault_stop = 0;
- int amdgpu_vm_debug = 0;
- int amdgpu_exp_hw_support = 0;
--int amdgpu_enable_scheduler = 1;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_powerplay = -1;
-@@ -154,9 +153,6 @@ module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
- MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
- module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
- 
--MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)");
--module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
--
- MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
- module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 3671f9f..cac03e7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -472,6 +472,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
- int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
- {
- 	int i, r;
-+	long timeout;
- 
- 	ring->fence_drv.cpu_addr = NULL;
- 	ring->fence_drv.gpu_addr = 0;
-@@ -486,26 +487,24 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
- 
- 	init_waitqueue_head(&ring->fence_drv.fence_queue);
- 
--	if (amdgpu_enable_scheduler) {
--		long timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
--		if (timeout == 0) {
--			/*
--			 * FIXME:
--			 * Delayed workqueue cannot use it directly,
--			 * so the scheduler will not use delayed workqueue if
--			 * MAX_SCHEDULE_TIMEOUT is set.
--			 * Currently keep it simple and silly.
--			 */
--			timeout = MAX_SCHEDULE_TIMEOUT;
--		}
--		r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
--				   amdgpu_sched_hw_submission,
--				   timeout, ring->name);
--		if (r) {
--			DRM_ERROR("Failed to create scheduler on ring %s.\n",
--				  ring->name);
--			return r;
--		}
-+	timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
-+	if (timeout == 0) {
-+		/*
-+		 * FIXME:
-+		 * Delayed workqueue cannot use it directly,
-+		 * so the scheduler will not use delayed workqueue if
-+		 * MAX_SCHEDULE_TIMEOUT is set.
-+		 * Currently keep it simple and silly.
-+		 */
-+		timeout = MAX_SCHEDULE_TIMEOUT;
-+	}
-+	r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
-+			   amdgpu_sched_hw_submission,
-+			   timeout, ring->name);
-+	if (r) {
-+		DRM_ERROR("Failed to create scheduler on ring %s.\n",
-+			  ring->name);
-+		return r;
- 	}
- 
- 	return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 3b58d70..54cede3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -199,10 +199,6 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 		return r;
- 	}
- 
--	if (!amdgpu_enable_scheduler && ib->ctx)
--		ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
--						    &ib->fence->base);
--
- 	/* wrap the last IB with fence */
- 	if (ib->user) {
- 		uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index 438c052..dd9fac3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -76,33 +76,25 @@ int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
- 					 void *owner,
- 					 struct fence **f)
- {
--	int r = 0;
--	if (amdgpu_enable_scheduler) {
--		struct amdgpu_job *job =
--			kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
--		if (!job)
--			return -ENOMEM;
--		job->base.sched = &ring->sched;
--		job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
--		job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner);
--		if (!job->base.s_fence) {
--			kfree(job);
--			return -ENOMEM;
--		}
--		*f = fence_get(&job->base.s_fence->base);
--
--		job->adev = adev;
--		job->ibs = ibs;
--		job->num_ibs = num_ibs;
--		job->owner = owner;
--		job->free_job = free_job;
--		amd_sched_entity_push_job(&job->base);
--	} else {
--		r = amdgpu_ib_schedule(adev, num_ibs, ibs, owner);
--		if (r)
--			return r;
--		*f = fence_get(&ibs[num_ibs - 1].fence->base);
-+	struct amdgpu_job *job =
-+		kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
-+	if (!job)
-+		return -ENOMEM;
-+	job->base.sched = &ring->sched;
-+	job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
-+	job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner);
-+	if (!job->base.s_fence) {
-+		kfree(job);
-+		return -ENOMEM;
- 	}
-+	*f = fence_get(&job->base.s_fence->base);
-+
-+	job->adev = adev;
-+	job->ibs = ibs;
-+	job->num_ibs = num_ibs;
-+	job->owner = owner;
-+	job->free_job = free_job;
-+	amd_sched_entity_push_job(&job->base);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index e8fe0b7..f08d53f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -1070,10 +1070,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	if (r)
- 		goto error_free;
- 
--	if (!amdgpu_enable_scheduler) {
--		amdgpu_ib_free(adev, ib);
--		kfree(ib);
--	}
- 	return 0;
- error_free:
- 	amdgpu_ib_free(adev, ib);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 3b35ad8..b4e902c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -900,11 +900,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
- 		*fence = fence_get(f);
- 	amdgpu_bo_unref(&bo);
- 	fence_put(f);
--	if (amdgpu_enable_scheduler)
--		return 0;
- 
--	amdgpu_ib_free(ring->adev, ib);
--	kfree(ib);
- 	return 0;
- err2:
- 	amdgpu_ib_free(ring->adev, ib);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 9c3e271..d83efc7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -433,8 +433,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	if (fence)
- 		*fence = fence_get(f);
- 	fence_put(f);
--	if (amdgpu_enable_scheduler)
--		return 0;
-+	return 0;
- err:
- 	amdgpu_ib_free(adev, ib);
- 	kfree(ib);
-@@ -500,8 +499,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	if (fence)
- 		*fence = fence_get(f);
- 	fence_put(f);
--	if (amdgpu_enable_scheduler)
--		return 0;
-+	return 0;
- err:
- 	amdgpu_ib_free(adev, ib);
- 	kfree(ib);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8c729b1..870379a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -408,8 +408,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	if (!r)
- 		amdgpu_bo_fence(bo, fence, true);
- 	fence_put(fence);
--	if (amdgpu_enable_scheduler)
--		return 0;
-+	return 0;
- 
- error_free:
- 	amdgpu_ib_free(adev, ib);
-@@ -543,7 +542,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 		fence_put(fence);
- 	}
- 
--	if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
-+	if (ib->length_dw == 0) {
- 		amdgpu_ib_free(adev, ib);
- 		kfree(ib);
- 	}
-@@ -826,10 +825,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 		*fence = fence_get(f);
- 	}
- 	fence_put(f);
--	if (!amdgpu_enable_scheduler) {
--		amdgpu_ib_free(adev, ib);
--		kfree(ib);
--	}
- 	return 0;
- 
- error_free:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0228-drm-amdgpu-remove-some-more-semaphore-leftovers.patch b/common/recipes-kernel/linux/files/0228-drm-amdgpu-remove-some-more-semaphore-leftovers.patch
deleted file mode 100644
index f668de86..00000000
--- a/common/recipes-kernel/linux/files/0228-drm-amdgpu-remove-some-more-semaphore-leftovers.patch
+++ /dev/null
@@ -1,229 +0,0 @@
-From 701eab8ab9fd8fc081b5549b428163208bc01950 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 15 Jan 2016 14:33:08 -0500
-Subject: [PATCH 0228/1110] drm/amdgpu: remove some more semaphore leftovers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No longer needed since semaphores were removed.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <David1.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 8 --------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 1 -
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    | 2 --
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 2 --
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 1 -
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 1 -
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    | 1 -
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    | 1 -
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    | 1 -
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    | 1 -
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    | 1 -
- 12 files changed, 24 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1e9452b..f572cbc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -84,7 +84,6 @@ extern int amdgpu_vm_fault_stop;
- extern int amdgpu_vm_debug;
- extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
--extern int amdgpu_enable_semaphores;
- extern int amdgpu_powerplay;
- extern unsigned amdgpu_pcie_gen_cap;
- extern unsigned amdgpu_pcie_lane_cap;
-@@ -149,7 +148,6 @@ struct amdgpu_fence;
- struct amdgpu_ib;
- struct amdgpu_vm;
- struct amdgpu_ring;
--struct amdgpu_semaphore;
- struct amdgpu_cs_parser;
- struct amdgpu_job;
- struct amdgpu_irq_src;
-@@ -294,9 +292,6 @@ struct amdgpu_ring_funcs {
- 			struct amdgpu_ib *ib);
- 	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
- 			   uint64_t seq, unsigned flags);
--	bool (*emit_semaphore)(struct amdgpu_ring *ring,
--			       struct amdgpu_semaphore *semaphore,
--			       bool emit_wait);
- 	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
- 			      uint64_t pd_addr);
- 	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
-@@ -802,8 +797,6 @@ struct amdgpu_ring {
- 	bool			ready;
- 	u32			nop;
- 	u32			idx;
--	u64			last_semaphore_signal_addr;
--	u64			last_semaphore_wait_addr;
- 	u32			me;
- 	u32			pipe;
- 	u32			queue;
-@@ -2192,7 +2185,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
- #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
- #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
--#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
- #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
- #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
- #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index d1f234d..66c6bbd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -491,10 +491,6 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- 
- 	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
- 		   ring->wptr, ring->wptr);
--	seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
--		   ring->last_semaphore_signal_addr);
--	seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
--		   ring->last_semaphore_wait_addr);
- 	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
- 	seq_printf(m, "%u dwords in ring\n", count);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index dd2a0c1..2aede8f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -1273,7 +1273,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = cik_sdma_ring_emit_ib,
- 	.emit_fence = cik_sdma_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
- 	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
- 	.test_ring = cik_sdma_ring_test_ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 52b3c2b..82ede2f 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -5550,7 +5550,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
- 	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-@@ -5566,7 +5565,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v7_0_ring_emit_ib_compute,
- 	.emit_fence = gfx_v7_0_ring_emit_fence_compute,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 50e071a..95ca834 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -5108,7 +5108,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
- 	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-@@ -5124,7 +5123,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v8_0_ring_emit_ib_compute,
- 	.emit_fence = gfx_v8_0_ring_emit_fence_compute,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 1eae05a..77d5f29 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -1277,7 +1277,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = sdma_v2_4_ring_emit_ib,
- 	.emit_fence = sdma_v2_4_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
- 	.test_ring = sdma_v2_4_ring_test_ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 93930ae..d6170e6 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1544,7 +1544,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = sdma_v3_0_ring_emit_ib,
- 	.emit_fence = sdma_v3_0_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
- 	.test_ring = sdma_v3_0_ring_test_ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index 65961e4..fcc29c6 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -861,7 +861,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
- 	.parse_cs = amdgpu_uvd_ring_parse_cs,
- 	.emit_ib = uvd_v4_2_ring_emit_ib,
- 	.emit_fence = uvd_v4_2_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.test_ring = uvd_v4_2_ring_test_ring,
- 	.test_ib = uvd_v4_2_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 2a4a21a..67be97c 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -802,7 +802,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
- 	.parse_cs = amdgpu_uvd_ring_parse_cs,
- 	.emit_ib = uvd_v5_0_ring_emit_ib,
- 	.emit_fence = uvd_v5_0_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.test_ring = uvd_v5_0_ring_test_ring,
- 	.test_ib = uvd_v5_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index dc59a53..4d64769 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -1038,7 +1038,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
- 	.parse_cs = amdgpu_uvd_ring_parse_cs,
- 	.emit_ib = uvd_v6_0_ring_emit_ib,
- 	.emit_fence = uvd_v6_0_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.test_ring = uvd_v6_0_ring_test_ring,
- 	.test_ib = uvd_v6_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index 6e48cc6..a4bfee2 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -642,7 +642,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
- 	.parse_cs = amdgpu_vce_ring_parse_cs,
- 	.emit_ib = amdgpu_vce_ring_emit_ib,
- 	.emit_fence = amdgpu_vce_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.test_ring = amdgpu_vce_ring_test_ring,
- 	.test_ib = amdgpu_vce_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index e3b47bc..c438c7e 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -762,7 +762,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
- 	.parse_cs = amdgpu_vce_ring_parse_cs,
- 	.emit_ib = amdgpu_vce_ring_emit_ib,
- 	.emit_fence = amdgpu_vce_ring_emit_fence,
--	.emit_semaphore = NULL,
- 	.test_ring = amdgpu_vce_ring_test_ring,
- 	.test_ib = amdgpu_vce_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0229-drm-amdgpu-remove-sync_to-from-sync-obj-v2.patch b/common/recipes-kernel/linux/files/0229-drm-amdgpu-remove-sync_to-from-sync-obj-v2.patch
deleted file mode 100644
index 233a5378..00000000
--- a/common/recipes-kernel/linux/files/0229-drm-amdgpu-remove-sync_to-from-sync-obj-v2.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 413319377bf1a284d74666a77b69711514ac0940 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 18 Jan 2016 14:49:45 +0100
-Subject: [PATCH 0229/1110] drm/amdgpu: remove sync_to from sync obj v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not needed any more without semaphores.
-
-v2: remove unused variables as well
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 44 +++++++-------------------------
- 2 files changed, 9 insertions(+), 36 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index f572cbc..996b8f8 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -596,7 +596,6 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp,
-  * Synchronization
-  */
- struct amdgpu_sync {
--	struct fence		*sync_to[AMDGPU_MAX_RINGS];
- 	DECLARE_HASHTABLE(fences, 4);
- 	struct fence	        *last_vm_update;
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index 7f12a4d..1d348f8 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -46,11 +46,6 @@ struct amdgpu_sync_entry {
-  */
- void amdgpu_sync_create(struct amdgpu_sync *sync)
- {
--	unsigned i;
--
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
--		sync->sync_to[i] = NULL;
--
- 	hash_init(sync->fences);
- 	sync->last_vm_update = NULL;
- }
-@@ -104,7 +99,6 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- 		      struct fence *f)
- {
- 	struct amdgpu_sync_entry *e;
--	struct amdgpu_fence *fence;
- 
- 	if (!f)
- 		return 0;
-@@ -113,27 +107,20 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- 	    amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM))
- 		amdgpu_sync_keep_later(&sync->last_vm_update, f);
- 
--	fence = to_amdgpu_fence(f);
--	if (!fence || fence->ring->adev != adev) {
--		hash_for_each_possible(sync->fences, e, node, f->context) {
--			if (unlikely(e->fence->context != f->context))
--				continue;
--
--			amdgpu_sync_keep_later(&e->fence, f);
--			return 0;
--		}
--
--		e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
--		if (!e)
--			return -ENOMEM;
-+	hash_for_each_possible(sync->fences, e, node, f->context) {
-+		if (unlikely(e->fence->context != f->context))
-+			continue;
- 
--		hash_add(sync->fences, &e->node, f->context);
--		e->fence = fence_get(f);
-+		amdgpu_sync_keep_later(&e->fence, f);
- 		return 0;
- 	}
- 
--	amdgpu_sync_keep_later(&sync->sync_to[fence->ring->idx], f);
-+	e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
-+	if (!e)
-+		return -ENOMEM;
- 
-+	hash_add(sync->fences, &e->node, f->context);
-+	e->fence = fence_get(f);
- 	return 0;
- }
- 
-@@ -247,16 +234,6 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
- 		kfree(e);
- 	}
- 
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		struct fence *fence = sync->sync_to[i];
--		if (!fence)
--			continue;
--
--		r = fence_wait(fence, false);
--		if (r)
--			return r;
--	}
--
- 	return 0;
- }
- 
-@@ -283,8 +260,5 @@ void amdgpu_sync_free(struct amdgpu_device *adev,
- 		kfree(e);
- 	}
- 
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
--		fence_put(sync->sync_to[i]);
--
- 	fence_put(sync->last_vm_update);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0230-drm-amdgpu-cleanup-sync_seq-handling.patch b/common/recipes-kernel/linux/files/0230-drm-amdgpu-cleanup-sync_seq-handling.patch
deleted file mode 100644
index 85a02a3f..00000000
--- a/common/recipes-kernel/linux/files/0230-drm-amdgpu-cleanup-sync_seq-handling.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From 1ac7d01496f3be8d37f57400cc1947c31ad5f4d1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 18 Jan 2016 15:16:53 +0100
-Subject: [PATCH 0230/1110] drm/amdgpu: cleanup sync_seq handling
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used any more without semaphores
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  7 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 94 ++++---------------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c     |  2 +-
- 3 files changed, 13 insertions(+), 90 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 996b8f8..e3be9f5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -349,7 +349,7 @@ struct amdgpu_fence_driver {
- 	uint64_t			gpu_addr;
- 	volatile uint32_t		*cpu_addr;
- 	/* sync_seq is protected by ring emission lock */
--	uint64_t			sync_seq[AMDGPU_MAX_RINGS];
-+	uint64_t			sync_seq;
- 	atomic64_t			last_seq;
- 	bool				initialized;
- 	struct amdgpu_irq_src		*irq_src;
-@@ -402,11 +402,6 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
- unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
- 
--bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
--			    struct amdgpu_ring *ring);
--void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
--			    struct amdgpu_ring *ring);
--
- /*
-  * TTM.
-  */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index cac03e7..988a32d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -107,7 +107,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
- 	if ((*fence) == NULL) {
- 		return -ENOMEM;
- 	}
--	(*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
-+	(*fence)->seq = ++ring->fence_drv.sync_seq;
- 	(*fence)->ring = ring;
- 	(*fence)->owner = owner;
- 	fence_init(&(*fence)->base, &amdgpu_fence_ops,
-@@ -171,7 +171,7 @@ static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
- 	 */
- 	last_seq = atomic64_read(&ring->fence_drv.last_seq);
- 	do {
--		last_emitted = ring->fence_drv.sync_seq[ring->idx];
-+		last_emitted = ring->fence_drv.sync_seq;
- 		seq = amdgpu_fence_read(ring);
- 		seq |= last_seq & 0xffffffff00000000LL;
- 		if (seq < last_seq) {
-@@ -274,7 +274,7 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
- 	bool signaled = false;
- 
- 	BUG_ON(!ring);
--	if (seq > ring->fence_drv.sync_seq[ring->idx])
-+	if (seq > ring->fence_drv.sync_seq)
- 		return -EINVAL;
- 
- 	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
-@@ -304,7 +304,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
- {
- 	uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
- 
--	if (seq >= ring->fence_drv.sync_seq[ring->idx])
-+	if (seq >= ring->fence_drv.sync_seq)
- 		return -ENOENT;
- 
- 	return amdgpu_fence_ring_wait_seq(ring, seq);
-@@ -322,7 +322,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
-  */
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
- {
--	uint64_t seq = ring->fence_drv.sync_seq[ring->idx];
-+	uint64_t seq = ring->fence_drv.sync_seq;
- 
- 	if (!seq)
- 		return 0;
-@@ -347,7 +347,7 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
- 	 * but it's ok to report slightly wrong fence count here.
- 	 */
- 	amdgpu_fence_process(ring);
--	emitted = ring->fence_drv.sync_seq[ring->idx]
-+	emitted = ring->fence_drv.sync_seq
- 		- atomic64_read(&ring->fence_drv.last_seq);
- 	/* to avoid 32bits warp around */
- 	if (emitted > 0x10000000)
-@@ -357,68 +357,6 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
- }
- 
- /**
-- * amdgpu_fence_need_sync - do we need a semaphore
-- *
-- * @fence: amdgpu fence object
-- * @dst_ring: which ring to check against
-- *
-- * Check if the fence needs to be synced against another ring
-- * (all asics).  If so, we need to emit a semaphore.
-- * Returns true if we need to sync with another ring, false if
-- * not.
-- */
--bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
--			    struct amdgpu_ring *dst_ring)
--{
--	struct amdgpu_fence_driver *fdrv;
--
--	if (!fence)
--		return false;
--
--	if (fence->ring == dst_ring)
--		return false;
--
--	/* we are protected by the ring mutex */
--	fdrv = &dst_ring->fence_drv;
--	if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
--		return false;
--
--	return true;
--}
--
--/**
-- * amdgpu_fence_note_sync - record the sync point
-- *
-- * @fence: amdgpu fence object
-- * @dst_ring: which ring to check against
-- *
-- * Note the sequence number at which point the fence will
-- * be synced with the requested ring (all asics).
-- */
--void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
--			    struct amdgpu_ring *dst_ring)
--{
--	struct amdgpu_fence_driver *dst, *src;
--	unsigned i;
--
--	if (!fence)
--		return;
--
--	if (fence->ring == dst_ring)
--		return;
--
--	/* we are protected by the ring mutex */
--	src = &fence->ring->fence_drv;
--	dst = &dst_ring->fence_drv;
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		if (i == dst_ring->idx)
--			continue;
--
--		dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
--	}
--}
--
--/**
-  * amdgpu_fence_driver_start_ring - make the fence driver
-  * ready for use on the requested ring.
-  *
-@@ -471,14 +409,12 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
-  */
- int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
- {
--	int i, r;
- 	long timeout;
-+	int r;
- 
- 	ring->fence_drv.cpu_addr = NULL;
- 	ring->fence_drv.gpu_addr = 0;
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
--		ring->fence_drv.sync_seq[i] = 0;
--
-+	ring->fence_drv.sync_seq = 0;
- 	atomic64_set(&ring->fence_drv.last_seq, 0);
- 	ring->fence_drv.initialized = false;
- 
-@@ -650,7 +586,7 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
- 		if (!ring || !ring->fence_drv.initialized)
- 			continue;
- 
--		amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
-+		amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
- 	}
- }
- 
-@@ -780,7 +716,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
- 	struct drm_info_node *node = (struct drm_info_node *)m->private;
- 	struct drm_device *dev = node->minor->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
--	int i, j;
-+	int i;
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 		struct amdgpu_ring *ring = adev->rings[i];
-@@ -793,15 +729,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
- 		seq_printf(m, "Last signaled fence 0x%016llx\n",
- 			   (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
- 		seq_printf(m, "Last emitted        0x%016llx\n",
--			   ring->fence_drv.sync_seq[i]);
--
--		for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
--			struct amdgpu_ring *other = adev->rings[j];
--			if (i != j && other && other->fence_drv.initialized &&
--			    ring->fence_drv.sync_seq[j])
--				seq_printf(m, "Last sync to ring %d 0x%016llx\n",
--					   j, ring->fence_drv.sync_seq[j]);
--		}
-+			   ring->fence_drv.sync_seq);
- 	}
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 95ca834..73d8ac0 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4766,7 +4766,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 					unsigned vm_id, uint64_t pd_addr)
- {
- 	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
--	uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
-+	uint32_t seq = ring->fence_drv.sync_seq;
- 	uint64_t addr = ring->fence_drv.gpu_addr;
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0231-drm-amdgpu-clean-up-asic-level-reset-for-CI.patch b/common/recipes-kernel/linux/files/0231-drm-amdgpu-clean-up-asic-level-reset-for-CI.patch
deleted file mode 100644
index 665ee3d7..00000000
--- a/common/recipes-kernel/linux/files/0231-drm-amdgpu-clean-up-asic-level-reset-for-CI.patch
+++ /dev/null
@@ -1,360 +0,0 @@
-From dd7ed4a0c516cca77e9a058aa7825f5cdd9cdcc8 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 14 Oct 2015 09:43:58 -0400
-Subject: [PATCH 0231/1110] drm/amdgpu: clean up asic level reset for CI
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Drop soft reset, always use pci config reset.
-
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik.c | 308 +--------------------------------------
- 1 file changed, 4 insertions(+), 304 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 155965e..192ab13 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -1059,257 +1059,6 @@ static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
- 	return -EINVAL;
- }
- 
--static void cik_print_gpu_status_regs(struct amdgpu_device *adev)
--{
--	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
--		RREG32(mmGRBM_STATUS));
--	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
--		RREG32(mmGRBM_STATUS2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE0));
--	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE1));
--	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE3));
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--	dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
--		RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
--	dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
--		 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
--	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
--	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT2));
--	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT3));
--	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
--		 RREG32(mmCP_CPF_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPF_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
--	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPC_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
--}
--
--/**
-- * cik_gpu_check_soft_reset - check which blocks are busy
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Check which blocks are busy and return the relevant reset
-- * mask to be used by cik_gpu_soft_reset().
-- * Returns a mask of the blocks to be reset.
-- */
--u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev)
--{
--	u32 reset_mask = 0;
--	u32 tmp;
--
--	/* GRBM_STATUS */
--	tmp = RREG32(mmGRBM_STATUS);
--	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
--		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
--		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
--		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
--		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
--		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
--		reset_mask |= AMDGPU_RESET_GFX;
--
--	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
--		reset_mask |= AMDGPU_RESET_CP;
--
--	/* GRBM_STATUS2 */
--	tmp = RREG32(mmGRBM_STATUS2);
--	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_RLC;
--
--	/* SDMA0_STATUS_REG */
--	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
--	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
--		reset_mask |= AMDGPU_RESET_DMA;
--
--	/* SDMA1_STATUS_REG */
--	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
--	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
--		reset_mask |= AMDGPU_RESET_DMA1;
--
--	/* SRBM_STATUS2 */
--	tmp = RREG32(mmSRBM_STATUS2);
--	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_DMA;
--
--	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_DMA1;
--
--	/* SRBM_STATUS */
--	tmp = RREG32(mmSRBM_STATUS);
--
--	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_IH;
--
--	if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_SEM;
--
--	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
--		reset_mask |= AMDGPU_RESET_GRBM;
--
--	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_VMC;
--
--	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
--		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
--		reset_mask |= AMDGPU_RESET_MC;
--
--	if (amdgpu_display_is_display_hung(adev))
--		reset_mask |= AMDGPU_RESET_DISPLAY;
--
--	/* Skip MC reset as it's mostly likely not hung, just busy */
--	if (reset_mask & AMDGPU_RESET_MC) {
--		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
--		reset_mask &= ~AMDGPU_RESET_MC;
--	}
--
--	return reset_mask;
--}
--
--/**
-- * cik_gpu_soft_reset - soft reset GPU
-- *
-- * @adev: amdgpu_device pointer
-- * @reset_mask: mask of which blocks to reset
-- *
-- * Soft reset the blocks specified in @reset_mask.
-- */
--static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
--{
--	struct amdgpu_mode_mc_save save;
--	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
--	u32 tmp;
--
--	if (reset_mask == 0)
--		return;
--
--	dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
--
--	cik_print_gpu_status_regs(adev);
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
--
--	/* disable CG/PG */
--
--	/* stop the rlc */
--	gfx_v7_0_rlc_stop(adev);
--
--	/* Disable GFX parsing/prefetching */
--	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
--
--	/* Disable MEC parsing/prefetching */
--	WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
--
--	if (reset_mask & AMDGPU_RESET_DMA) {
--		/* sdma0 */
--		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
--		tmp |= SDMA0_F32_CNTL__HALT_MASK;
--		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
--	}
--	if (reset_mask & AMDGPU_RESET_DMA1) {
--		/* sdma1 */
--		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
--		tmp |= SDMA0_F32_CNTL__HALT_MASK;
--		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
--	}
--
--	gmc_v7_0_mc_stop(adev, &save);
--	if (amdgpu_asic_wait_for_mc_idle(adev)) {
--		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
--	}
--
--	if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP))
--		grbm_soft_reset = GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
--			GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
--
--	if (reset_mask & AMDGPU_RESET_CP) {
--		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
--
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
--	}
--
--	if (reset_mask & AMDGPU_RESET_DMA)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
--
--	if (reset_mask & AMDGPU_RESET_DMA1)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
--
--	if (reset_mask & AMDGPU_RESET_DISPLAY)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
--
--	if (reset_mask & AMDGPU_RESET_RLC)
--		grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
--
--	if (reset_mask & AMDGPU_RESET_SEM)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK;
--
--	if (reset_mask & AMDGPU_RESET_IH)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
--
--	if (reset_mask & AMDGPU_RESET_GRBM)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
--
--	if (reset_mask & AMDGPU_RESET_VMC)
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK;
--
--	if (!(adev->flags & AMD_IS_APU)) {
--		if (reset_mask & AMDGPU_RESET_MC)
--			srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK;
--	}
--
--	if (grbm_soft_reset) {
--		tmp = RREG32(mmGRBM_SOFT_RESET);
--		tmp |= grbm_soft_reset;
--		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
--		WREG32(mmGRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmGRBM_SOFT_RESET);
--
--		udelay(50);
--
--		tmp &= ~grbm_soft_reset;
--		WREG32(mmGRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmGRBM_SOFT_RESET);
--	}
--
--	if (srbm_soft_reset) {
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--		tmp |= srbm_soft_reset;
--		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
--		WREG32(mmSRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--
--		udelay(50);
--
--		tmp &= ~srbm_soft_reset;
--		WREG32(mmSRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--	}
--
--	/* Wait a little for things to settle down */
--	udelay(50);
--
--	gmc_v7_0_mc_resume(adev, &save);
--	udelay(50);
--
--	cik_print_gpu_status_regs(adev);
--}
--
- struct kv_reset_save_regs {
- 	u32 gmcon_reng_execute;
- 	u32 gmcon_misc;
-@@ -1405,45 +1154,11 @@ static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
- 
- static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
- {
--	struct amdgpu_mode_mc_save save;
- 	struct kv_reset_save_regs kv_save = { 0 };
--	u32 tmp, i;
-+	u32 i;
- 
- 	dev_info(adev->dev, "GPU pci config reset\n");
- 
--	/* disable dpm? */
--
--	/* disable cg/pg */
--
--	/* Disable GFX parsing/prefetching */
--	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
--		CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
--
--	/* Disable MEC parsing/prefetching */
--	WREG32(mmCP_MEC_CNTL,
--			CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
--
--	/* sdma0 */
--	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
--	tmp |= SDMA0_F32_CNTL__HALT_MASK;
--	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
--	/* sdma1 */
--	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
--	tmp |= SDMA0_F32_CNTL__HALT_MASK;
--	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
--	/* XXX other engines? */
--
--	/* halt the rlc, disable cp internal ints */
--	gfx_v7_0_rlc_stop(adev);
--
--	udelay(50);
--
--	/* disable mem access */
--	gmc_v7_0_mc_stop(adev, &save);
--	if (amdgpu_asic_wait_for_mc_idle(adev)) {
--		dev_warn(adev->dev, "Wait for MC idle timed out !\n");
--	}
--
- 	if (adev->flags & AMD_IS_APU)
- 		kv_save_regs_for_reset(adev, &kv_save);
- 
-@@ -1489,26 +1204,11 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu
-  */
- static int cik_asic_reset(struct amdgpu_device *adev)
- {
--	u32 reset_mask;
--
--	reset_mask = amdgpu_cik_gpu_check_soft_reset(adev);
--
--	if (reset_mask)
--		cik_set_bios_scratch_engine_hung(adev, true);
--
--	/* try soft reset */
--	cik_gpu_soft_reset(adev, reset_mask);
--
--	reset_mask = amdgpu_cik_gpu_check_soft_reset(adev);
--
--	/* try pci config reset */
--	if (reset_mask && amdgpu_hard_reset)
--		cik_gpu_pci_config_reset(adev);
-+	cik_set_bios_scratch_engine_hung(adev, true);
- 
--	reset_mask = amdgpu_cik_gpu_check_soft_reset(adev);
-+	cik_gpu_pci_config_reset(adev);
- 
--	if (!reset_mask)
--		cik_set_bios_scratch_engine_hung(adev, false);
-+	cik_set_bios_scratch_engine_hung(adev, false);
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0232-drm-amdgpu-clean-up-asic-level-reset-for-VI.patch b/common/recipes-kernel/linux/files/0232-drm-amdgpu-clean-up-asic-level-reset-for-VI.patch
deleted file mode 100644
index 4fa3d98c..00000000
--- a/common/recipes-kernel/linux/files/0232-drm-amdgpu-clean-up-asic-level-reset-for-VI.patch
+++ /dev/null
@@ -1,431 +0,0 @@
-From 3b7e1b3b85b74e7f42b2ac7942573a0a6bdfb132 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 14 Oct 2015 09:39:37 -0400
-Subject: [PATCH 0232/1110] drm/amdgpu: clean up asic level reset for VI
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Drop soft reset, always use pci config reset.
-
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 385 +---------------------------------------
- 1 file changed, 4 insertions(+), 381 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 0d14d10..4ccf415 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -571,374 +571,12 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
- 	return -EINVAL;
- }
- 
--static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
--{
--	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
--		RREG32(mmGRBM_STATUS));
--	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
--		RREG32(mmGRBM_STATUS2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE0));
--	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE1));
--	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE3));
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--	dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
--		RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
--	if (adev->sdma.num_instances > 1) {
--		dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
--			RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
--	}
--	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
--	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT2));
--	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT3));
--	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
--		 RREG32(mmCP_CPF_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPF_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
--	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPC_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
--}
--
--/**
-- * vi_gpu_check_soft_reset - check which blocks are busy
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Check which blocks are busy and return the relevant reset
-- * mask to be used by vi_gpu_soft_reset().
-- * Returns a mask of the blocks to be reset.
-- */
--u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
--{
--	u32 reset_mask = 0;
--	u32 tmp;
--
--	/* GRBM_STATUS */
--	tmp = RREG32(mmGRBM_STATUS);
--	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
--		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
--		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
--		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
--		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
--		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
--		reset_mask |= AMDGPU_RESET_GFX;
--
--	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
--		reset_mask |= AMDGPU_RESET_CP;
--
--	/* GRBM_STATUS2 */
--	tmp = RREG32(mmGRBM_STATUS2);
--	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_RLC;
--
--	if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
--		   GRBM_STATUS2__CPC_BUSY_MASK |
--		   GRBM_STATUS2__CPG_BUSY_MASK))
--		reset_mask |= AMDGPU_RESET_CP;
--
--	/* SRBM_STATUS2 */
--	tmp = RREG32(mmSRBM_STATUS2);
--	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_DMA;
--
--	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_DMA1;
--
--	/* SRBM_STATUS */
--	tmp = RREG32(mmSRBM_STATUS);
--
--	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_IH;
--
--	if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_SEM;
--
--	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
--		reset_mask |= AMDGPU_RESET_GRBM;
--
--	if (adev->asic_type != CHIP_TOPAZ) {
--		if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
--			   SRBM_STATUS__UVD_BUSY_MASK))
--			reset_mask |= AMDGPU_RESET_UVD;
--	}
--
--	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
--		reset_mask |= AMDGPU_RESET_VMC;
--
--	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
--		   SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
--		reset_mask |= AMDGPU_RESET_MC;
--
--	/* SDMA0_STATUS_REG */
--	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
--	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
--		reset_mask |= AMDGPU_RESET_DMA;
--
--	/* SDMA1_STATUS_REG */
--	if (adev->sdma.num_instances > 1) {
--		tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
--		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
--			reset_mask |= AMDGPU_RESET_DMA1;
--	}
--#if 0
--	/* VCE_STATUS */
--	if (adev->asic_type != CHIP_TOPAZ) {
--		tmp = RREG32(mmVCE_STATUS);
--		if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
--			reset_mask |= AMDGPU_RESET_VCE;
--		if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
--			reset_mask |= AMDGPU_RESET_VCE1;
--
--	}
--
--	if (adev->asic_type != CHIP_TOPAZ) {
--		if (amdgpu_display_is_display_hung(adev))
--			reset_mask |= AMDGPU_RESET_DISPLAY;
--	}
--#endif
--
--	/* Skip MC reset as it's mostly likely not hung, just busy */
--	if (reset_mask & AMDGPU_RESET_MC) {
--		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
--		reset_mask &= ~AMDGPU_RESET_MC;
--	}
--
--	return reset_mask;
--}
--
--/**
-- * vi_gpu_soft_reset - soft reset GPU
-- *
-- * @adev: amdgpu_device pointer
-- * @reset_mask: mask of which blocks to reset
-- *
-- * Soft reset the blocks specified in @reset_mask.
-- */
--static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
--{
--	struct amdgpu_mode_mc_save save;
--	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
--	u32 tmp;
--
--	if (reset_mask == 0)
--		return;
--
--	dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
--
--	vi_print_gpu_status_regs(adev);
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
--
--	/* disable CG/PG */
--
--	/* stop the rlc */
--	//XXX
--	//gfx_v8_0_rlc_stop(adev);
--
--	/* Disable GFX parsing/prefetching */
--	tmp = RREG32(mmCP_ME_CNTL);
--	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
--	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
--	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
--	WREG32(mmCP_ME_CNTL, tmp);
--
--	/* Disable MEC parsing/prefetching */
--	tmp = RREG32(mmCP_MEC_CNTL);
--	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
--	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
--	WREG32(mmCP_MEC_CNTL, tmp);
--
--	if (reset_mask & AMDGPU_RESET_DMA) {
--		/* sdma0 */
--		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
--		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
--		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
--	}
--	if (reset_mask & AMDGPU_RESET_DMA1) {
--		/* sdma1 */
--		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
--		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
--		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
--	}
--
--	gmc_v8_0_mc_stop(adev, &save);
--	if (amdgpu_asic_wait_for_mc_idle(adev)) {
--		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
--	}
--
--	if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
--		grbm_soft_reset =
--			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
--		grbm_soft_reset =
--			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
--	}
--
--	if (reset_mask & AMDGPU_RESET_CP) {
--		grbm_soft_reset =
--			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
--	}
--
--	if (reset_mask & AMDGPU_RESET_DMA)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
--
--	if (reset_mask & AMDGPU_RESET_DMA1)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
--
--	if (reset_mask & AMDGPU_RESET_DISPLAY)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
--
--	if (reset_mask & AMDGPU_RESET_RLC)
--		grbm_soft_reset =
--			REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
--
--	if (reset_mask & AMDGPU_RESET_SEM)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
--
--	if (reset_mask & AMDGPU_RESET_IH)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
--
--	if (reset_mask & AMDGPU_RESET_GRBM)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
--
--	if (reset_mask & AMDGPU_RESET_VMC)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
--
--	if (reset_mask & AMDGPU_RESET_UVD)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
--
--	if (reset_mask & AMDGPU_RESET_VCE)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
--
--	if (reset_mask & AMDGPU_RESET_VCE)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
--
--	if (!(adev->flags & AMD_IS_APU)) {
--		if (reset_mask & AMDGPU_RESET_MC)
--		srbm_soft_reset =
--			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
--	}
--
--	if (grbm_soft_reset) {
--		tmp = RREG32(mmGRBM_SOFT_RESET);
--		tmp |= grbm_soft_reset;
--		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
--		WREG32(mmGRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmGRBM_SOFT_RESET);
--
--		udelay(50);
--
--		tmp &= ~grbm_soft_reset;
--		WREG32(mmGRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmGRBM_SOFT_RESET);
--	}
--
--	if (srbm_soft_reset) {
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--		tmp |= srbm_soft_reset;
--		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
--		WREG32(mmSRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--
--		udelay(50);
--
--		tmp &= ~srbm_soft_reset;
--		WREG32(mmSRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--	}
--
--	/* Wait a little for things to settle down */
--	udelay(50);
--
--	gmc_v8_0_mc_resume(adev, &save);
--	udelay(50);
--
--	vi_print_gpu_status_regs(adev);
--}
--
- static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
- {
--	struct amdgpu_mode_mc_save save;
--	u32 tmp, i;
-+	u32 i;
- 
- 	dev_info(adev->dev, "GPU pci config reset\n");
- 
--	/* disable dpm? */
--
--	/* disable cg/pg */
--
--	/* Disable GFX parsing/prefetching */
--	tmp = RREG32(mmCP_ME_CNTL);
--	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
--	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
--	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
--	WREG32(mmCP_ME_CNTL, tmp);
--
--	/* Disable MEC parsing/prefetching */
--	tmp = RREG32(mmCP_MEC_CNTL);
--	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
--	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
--	WREG32(mmCP_MEC_CNTL, tmp);
--
--	/* Disable GFX parsing/prefetching */
--	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
--		CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
--
--	/* Disable MEC parsing/prefetching */
--	WREG32(mmCP_MEC_CNTL,
--			CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
--
--	/* sdma0 */
--	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
--	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
--	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
--
--	/* sdma1 */
--	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
--	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
--	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
--
--	/* XXX other engines? */
--
--	/* halt the rlc, disable cp internal ints */
--	//XXX
--	//gfx_v8_0_rlc_stop(adev);
--
--	udelay(50);
--
--	/* disable mem access */
--	gmc_v8_0_mc_stop(adev, &save);
--	if (amdgpu_asic_wait_for_mc_idle(adev)) {
--		dev_warn(adev->dev, "Wait for MC idle timed out !\n");
--	}
--
- 	/* disable BM */
- 	pci_clear_master(adev->pdev);
- 	/* reset */
-@@ -978,26 +616,11 @@ static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hun
-  */
- static int vi_asic_reset(struct amdgpu_device *adev)
- {
--	u32 reset_mask;
--
--	reset_mask = vi_gpu_check_soft_reset(adev);
--
--	if (reset_mask)
--		vi_set_bios_scratch_engine_hung(adev, true);
--
--	/* try soft reset */
--	vi_gpu_soft_reset(adev, reset_mask);
--
--	reset_mask = vi_gpu_check_soft_reset(adev);
--
--	/* try pci config reset */
--	if (reset_mask && amdgpu_hard_reset)
--		vi_gpu_pci_config_reset(adev);
-+	vi_set_bios_scratch_engine_hung(adev, true);
- 
--	reset_mask = vi_gpu_check_soft_reset(adev);
-+	vi_gpu_pci_config_reset(adev);
- 
--	if (!reset_mask)
--		vi_set_bios_scratch_engine_hung(adev, false);
-+	vi_set_bios_scratch_engine_hung(adev, false);
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0233-drm-amdgpu-post-card-after-hard-reset.patch b/common/recipes-kernel/linux/files/0233-drm-amdgpu-post-card-after-hard-reset.patch
deleted file mode 100644
index ab3fc37d..00000000
--- a/common/recipes-kernel/linux/files/0233-drm-amdgpu-post-card-after-hard-reset.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 7245823bde00811b8e4494bb4eed4dd50e5defdb Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 15 Jan 2016 11:59:48 -0500
-Subject: [PATCH 0233/1110] drm/amdgpu: post card after hard reset
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Posting is required after a pci config reset.
-
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 51bfc11..c96437c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1894,6 +1894,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
- 
- retry:
- 	r = amdgpu_asic_reset(adev);
-+	/* post card */
-+	amdgpu_atom_asic_init(adev->mode_info.atom_context);
-+
- 	if (!r) {
- 		dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
- 		r = amdgpu_resume(adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0234-drm-amdgpu-add-a-debugfs-property-to-trigger-a-GPU-r.patch b/common/recipes-kernel/linux/files/0234-drm-amdgpu-add-a-debugfs-property-to-trigger-a-GPU-r.patch
deleted file mode 100644
index 7842efe5..00000000
--- a/common/recipes-kernel/linux/files/0234-drm-amdgpu-add-a-debugfs-property-to-trigger-a-GPU-r.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From c1ba9e8a74d01791e480fcb4bd342ed8837ab73b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 14 Jan 2016 10:25:22 -0500
-Subject: [PATCH 0234/1110] drm/amdgpu: add a debugfs property to trigger a GPU
- reset
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Ported from similar code in radeon.
-
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 20 +++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 988a32d..08963fc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -734,15 +734,33 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
- 	return 0;
- }
- 
-+/**
-+ * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
-+ *
-+ * Manually trigger a gpu reset at the next fence wait.
-+ */
-+static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
-+{
-+	struct drm_info_node *node = (struct drm_info_node *) m->private;
-+	struct drm_device *dev = node->minor->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	seq_printf(m, "gpu reset\n");
-+	amdgpu_gpu_reset(adev);
-+
-+	return 0;
-+}
-+
- static struct drm_info_list amdgpu_debugfs_fence_list[] = {
- 	{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
-+	{"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
- };
- #endif
- 
- int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
- {
- #if defined(CONFIG_DEBUG_FS)
--	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1);
-+	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
- #else
- 	return 0;
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0235-drm-amdgpu-drop-hard_reset-module-parameter.patch b/common/recipes-kernel/linux/files/0235-drm-amdgpu-drop-hard_reset-module-parameter.patch
deleted file mode 100644
index 8c9f7ca8..00000000
--- a/common/recipes-kernel/linux/files/0235-drm-amdgpu-drop-hard_reset-module-parameter.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 2e2bc430d6c21e43c22161bbf0d0b494475e6f11 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 15 Jan 2016 13:18:12 -0500
-Subject: [PATCH 0235/1110] drm/amdgpu: drop hard_reset module parameter
-
-It doesn't currently do anything and there's no need for it
-going forward since pci config reset will be required as a
-fallback even when we have fine grained reset implemented.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ----
- 2 files changed, 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e3be9f5..a1da7e2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -74,7 +74,6 @@ extern int amdgpu_dpm;
- extern int amdgpu_smc_load_fw;
- extern int amdgpu_aspm;
- extern int amdgpu_runtime_pm;
--extern int amdgpu_hard_reset;
- extern unsigned amdgpu_ip_block_mask;
- extern int amdgpu_bapm;
- extern int amdgpu_deep_color;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 58c81a4..c1182ec 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -69,7 +69,6 @@ int amdgpu_dpm = -1;
- int amdgpu_smc_load_fw = 1;
- int amdgpu_aspm = -1;
- int amdgpu_runtime_pm = -1;
--int amdgpu_hard_reset = 0;
- unsigned amdgpu_ip_block_mask = 0xffffffff;
- int amdgpu_bapm = -1;
- int amdgpu_deep_color = 0;
-@@ -126,9 +125,6 @@ module_param_named(aspm, amdgpu_aspm, int, 0444);
- MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
- module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
- 
--MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
--module_param_named(hard_reset, amdgpu_hard_reset, int, 0444);
--
- MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
- module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0236-drm-amdgpu-add-VM-pointer-to-id-trace.patch b/common/recipes-kernel/linux/files/0236-drm-amdgpu-add-VM-pointer-to-id-trace.patch
deleted file mode 100644
index 034679de..00000000
--- a/common/recipes-kernel/linux/files/0236-drm-amdgpu-add-VM-pointer-to-id-trace.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From a5520f1d3b2a965e6d1177b412598edc8aa24930 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 7 Jan 2016 18:15:22 +0100
-Subject: [PATCH 0236/1110] drm/amdgpu: add VM pointer to id trace
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Because of the scheduler all traces come from the same thread now and
-can't be distincted otherwise.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 9 ++++++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    | 6 +++---
- 2 files changed, 9 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-index 2b94c63..e7d2676 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-@@ -100,18 +100,21 @@ TRACE_EVENT(amdgpu_sched_run_job,
- 
- 
- TRACE_EVENT(amdgpu_vm_grab_id,
--	    TP_PROTO(unsigned vmid, int ring),
--	    TP_ARGS(vmid, ring),
-+	    TP_PROTO(struct amdgpu_vm *vm, unsigned vmid, int ring),
-+	    TP_ARGS(vm, vmid, ring),
- 	    TP_STRUCT__entry(
-+			     __field(struct amdgpu_vm *, vm)
- 			     __field(u32, vmid)
- 			     __field(u32, ring)
- 			     ),
- 
- 	    TP_fast_assign(
-+			   __entry->vm = vm;
- 			   __entry->vmid = vmid;
- 			   __entry->ring = ring;
- 			   ),
--	    TP_printk("vmid=%u, ring=%u", __entry->vmid, __entry->ring)
-+	    TP_printk("vm=%p, id=%u, ring=%u", __entry->vm, __entry->vmid,
-+		      __entry->ring)
- );
- 
- TRACE_EVENT(amdgpu_vm_bo_map,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 870379a..e688fcf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -181,7 +181,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 
- 		owner = atomic_long_read(&adev->vm_manager.ids[id].owner);
- 		if (owner == (long)vm) {
--			trace_amdgpu_vm_grab_id(vm_id->id, ring->idx);
-+			trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx);
- 			return 0;
- 		}
- 	}
-@@ -197,7 +197,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		if (fence == NULL) {
- 			/* found a free one */
- 			vm_id->id = i;
--			trace_amdgpu_vm_grab_id(i, ring->idx);
-+			trace_amdgpu_vm_grab_id(vm, i, ring->idx);
- 			return 0;
- 		}
- 
-@@ -216,7 +216,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 			fence  = adev->vm_manager.ids[choices[i]].active;
- 			vm_id->id = choices[i];
- 
--			trace_amdgpu_vm_grab_id(choices[i], ring->idx);
-+			trace_amdgpu_vm_grab_id(vm, choices[i], ring->idx);
- 			return amdgpu_sync_fence(ring->adev, sync, fence);
- 		}
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0237-drm-amdgpu-grab-VMID-before-submitting-job-v5.patch b/common/recipes-kernel/linux/files/0237-drm-amdgpu-grab-VMID-before-submitting-job-v5.patch
deleted file mode 100644
index b36f151a..00000000
--- a/common/recipes-kernel/linux/files/0237-drm-amdgpu-grab-VMID-before-submitting-job-v5.patch
+++ /dev/null
@@ -1,141 +0,0 @@
-From 26605d32bf6727a47cda37191eeecaa7f92138ec Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 3 Nov 2015 20:58:50 +0100
-Subject: [PATCH 0237/1110] drm/amdgpu: grab VMID before submitting job v5
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows the scheduler to handle the dependencies on ID contention as well.
-
-v2: grab id only once
-v3: use a separate lock for the VMIDs
-v4: cleanup after semaphore removal
-v5: minor coding style change
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 ++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c     | 17 +++++------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c  | 26 +++++++++++++++++++++++++-
- 4 files changed, 35 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a1da7e2..f970afa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -737,6 +737,7 @@ struct amdgpu_ib {
- 	struct amdgpu_ring		*ring;
- 	struct amdgpu_fence		*fence;
- 	struct amdgpu_user_fence        *user;
-+	bool				grabbed_vmid;
- 	struct amdgpu_vm		*vm;
- 	struct amdgpu_ctx		*ctx;
- 	struct amdgpu_sync		sync;
-@@ -886,6 +887,9 @@ struct amdgpu_vm {
- };
- 
- struct amdgpu_vm_manager {
-+	/* protecting IDs */
-+	struct mutex				lock;
-+
- 	struct {
- 		struct fence	*active;
- 		atomic_long_t	owner;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index c96437c..9bab3dc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1456,6 +1456,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	/* mutex initialization are all done here so we
- 	 * can recall function without having locking issues */
- 	mutex_init(&adev->ring_lock);
-+	mutex_init(&adev->vm_manager.lock);
- 	atomic_set(&adev->irq.ih.lock, 0);
- 	mutex_init(&adev->gem.mutex);
- 	mutex_init(&adev->pm.mutex);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 54cede3..56ae9a5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -142,21 +142,17 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 		return -EINVAL;
- 	}
- 
-+	if (vm && !ibs->grabbed_vmid) {
-+		dev_err(adev->dev, "VM IB without ID\n");
-+		return -EINVAL;
-+	}
-+
- 	r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
- 	if (r) {
- 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
- 		return r;
- 	}
- 
--	if (vm) {
--		/* grab a vm id if necessary */
--		r = amdgpu_vm_grab_id(ibs->vm, ibs->ring, &ibs->sync);
--		if (r) {
--			amdgpu_ring_unlock_undo(ring);
--			return r;
--		}
--	}
--
- 	r = amdgpu_sync_wait(&ibs->sync);
- 	if (r) {
- 		amdgpu_ring_unlock_undo(ring);
-@@ -207,9 +203,6 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
- 
--	if (ib->vm)
--		amdgpu_vm_fence(adev, ib->vm, &ib->fence->base);
--
- 	amdgpu_ring_unlock_commit(ring);
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index dd9fac3..b22a95f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -31,7 +31,31 @@
- static struct fence *amdgpu_sched_dependency(struct amd_sched_job *sched_job)
- {
- 	struct amdgpu_job *job = to_amdgpu_job(sched_job);
--	return amdgpu_sync_get_fence(&job->ibs->sync);
-+	struct amdgpu_sync *sync = &job->ibs->sync;
-+	struct amdgpu_vm *vm = job->ibs->vm;
-+
-+	struct fence *fence = amdgpu_sync_get_fence(sync);
-+
-+	if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
-+		struct amdgpu_ring *ring = job->ibs->ring;
-+		struct amdgpu_device *adev = ring->adev;
-+		int r;
-+
-+		mutex_lock(&adev->vm_manager.lock);
-+		r = amdgpu_vm_grab_id(vm, ring, sync);
-+		if (r) {
-+			DRM_ERROR("Error getting VM ID (%d)\n", r);
-+		} else {
-+			fence = &job->base.s_fence->base;
-+			amdgpu_vm_fence(ring->adev, vm, fence);
-+			job->ibs->grabbed_vmid = true;
-+		}
-+		mutex_unlock(&adev->vm_manager.lock);
-+
-+		fence = amdgpu_sync_get_fence(sync);
-+	}
-+
-+	return fence;
- }
- 
- static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0238-drm-amdgpu-merge-vm_grab_id-and-vm_fence-v2.patch b/common/recipes-kernel/linux/files/0238-drm-amdgpu-merge-vm_grab_id-and-vm_fence-v2.patch
deleted file mode 100644
index ced1e96d..00000000
--- a/common/recipes-kernel/linux/files/0238-drm-amdgpu-merge-vm_grab_id-and-vm_fence-v2.patch
+++ /dev/null
@@ -1,188 +0,0 @@
-From 26ec1581529fbccb5bfbf5ec61d2711dd9c38622 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 18 Jan 2016 17:01:42 +0100
-Subject: [PATCH 0238/1110] drm/amdgpu: merge vm_grab_id and vm_fence v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need for an extra function any more.
-
-v2: comment cleanups
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  5 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 13 +++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    | 57 ++++++++++++++-----------------
- 3 files changed, 30 insertions(+), 45 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index f970afa..64784e4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -924,13 +924,10 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
- void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-                                   struct amdgpu_vm *vm);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
--		      struct amdgpu_sync *sync);
-+                      struct amdgpu_sync *sync, struct fence *fence);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 		     struct amdgpu_vm *vm,
- 		     struct fence *updates);
--void amdgpu_vm_fence(struct amdgpu_device *adev,
--		     struct amdgpu_vm *vm,
--		     struct fence *fence);
- uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index b22a95f..76a1f82 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -38,19 +38,14 @@ static struct fence *amdgpu_sched_dependency(struct amd_sched_job *sched_job)
- 
- 	if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
- 		struct amdgpu_ring *ring = job->ibs->ring;
--		struct amdgpu_device *adev = ring->adev;
- 		int r;
- 
--		mutex_lock(&adev->vm_manager.lock);
--		r = amdgpu_vm_grab_id(vm, ring, sync);
--		if (r) {
-+		r = amdgpu_vm_grab_id(vm, ring, sync,
-+				      &job->base.s_fence->base);
-+		if (r)
- 			DRM_ERROR("Error getting VM ID (%d)\n", r);
--		} else {
--			fence = &job->base.s_fence->base;
--			amdgpu_vm_fence(ring->adev, vm, fence);
-+		else
- 			job->ibs->grabbed_vmid = true;
--		}
--		mutex_unlock(&adev->vm_manager.lock);
- 
- 		fence = amdgpu_sync_get_fence(sync);
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index e688fcf..38ab4a5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -159,13 +159,14 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-  * @vm: vm to allocate id for
-  * @ring: ring we want to submit job to
-  * @sync: sync object where we add dependencies
-+ * @fence: fence protecting ID from reuse
-  *
-  * Allocate an id for the vm, adding fences to the sync obj as necessary.
-  *
-  * Global mutex must be locked!
-  */
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
--		      struct amdgpu_sync *sync)
-+		      struct amdgpu_sync *sync, struct fence *fence)
- {
- 	struct fence *best[AMDGPU_MAX_RINGS] = {};
- 	struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
-@@ -174,6 +175,8 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 	unsigned choices[2] = {};
- 	unsigned i;
- 
-+	mutex_lock(&adev->vm_manager.lock);
-+
- 	/* check if the id is still valid */
- 	if (vm_id->id) {
- 		unsigned id = vm_id->id;
-@@ -182,6 +185,9 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		owner = atomic_long_read(&adev->vm_manager.ids[id].owner);
- 		if (owner == (long)vm) {
- 			trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx);
-+			fence_put(adev->vm_manager.ids[id].active);
-+			adev->vm_manager.ids[id].active = fence_get(fence);
-+			mutex_unlock(&adev->vm_manager.lock);
- 			return 0;
- 		}
- 	}
-@@ -198,6 +204,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 			/* found a free one */
- 			vm_id->id = i;
- 			trace_amdgpu_vm_grab_id(vm, i, ring->idx);
-+			mutex_unlock(&adev->vm_manager.lock);
- 			return 0;
- 		}
- 
-@@ -210,19 +217,29 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 	}
- 
- 	for (i = 0; i < 2; ++i) {
--		if (choices[i]) {
--			struct fence *fence;
-+		struct fence *active;
-+		int r;
- 
--			fence  = adev->vm_manager.ids[choices[i]].active;
--			vm_id->id = choices[i];
-+		if (!choices[i])
-+			continue;
- 
--			trace_amdgpu_vm_grab_id(vm, choices[i], ring->idx);
--			return amdgpu_sync_fence(ring->adev, sync, fence);
--		}
-+		vm_id->id = choices[i];
-+		active  = adev->vm_manager.ids[vm_id->id].active;
-+		r = amdgpu_sync_fence(ring->adev, sync, active);
-+
-+		trace_amdgpu_vm_grab_id(vm, choices[i], ring->idx);
-+		atomic_long_set(&adev->vm_manager.ids[vm_id->id].owner, (long)vm);
-+
-+		fence_put(adev->vm_manager.ids[vm_id->id].active);
-+		adev->vm_manager.ids[vm_id->id].active = fence_get(fence);
-+
-+		mutex_unlock(&adev->vm_manager.lock);
-+		return r;
- 	}
- 
- 	/* should never happen */
- 	BUG();
-+	mutex_unlock(&adev->vm_manager.lock);
- 	return -EINVAL;
- }
- 
-@@ -265,30 +282,6 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- }
- 
- /**
-- * amdgpu_vm_fence - remember fence for vm
-- *
-- * @adev: amdgpu_device pointer
-- * @vm: vm we want to fence
-- * @fence: fence to remember
-- *
-- * Fence the vm (cayman+).
-- * Set the fence used to protect page table and id.
-- *
-- * Global and local mutex must be locked!
-- */
--void amdgpu_vm_fence(struct amdgpu_device *adev,
--		     struct amdgpu_vm *vm,
--		     struct fence *fence)
--{
--	struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence);
--	unsigned vm_id = vm->ids[ring->idx].id;
--
--	fence_put(adev->vm_manager.ids[vm_id].active);
--	adev->vm_manager.ids[vm_id].active = fence_get(fence);
--	atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm);
--}
--
--/**
-  * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
-  *
-  * @vm: requested vm
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0239-drm-amdgpu-use-a-global-LRU-list-for-VMIDs.patch b/common/recipes-kernel/linux/files/0239-drm-amdgpu-use-a-global-LRU-list-for-VMIDs.patch
deleted file mode 100644
index 4d9e2d63..00000000
--- a/common/recipes-kernel/linux/files/0239-drm-amdgpu-use-a-global-LRU-list-for-VMIDs.patch
+++ /dev/null
@@ -1,225 +0,0 @@
-From 733b067a8a1d587ff27072eb2ba55dc5c5e695f0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 21 Jan 2016 10:19:11 +0100
-Subject: [PATCH 0239/1110] drm/amdgpu: use a global LRU list for VMIDs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With the scheduler enabled managing per ring LRUs don't
-make much sense any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 19 ++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 88 ++++++++++++++++------------------
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  3 +-
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  3 +-
- 4 files changed, 55 insertions(+), 58 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 64784e4..5135635 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -886,18 +886,20 @@ struct amdgpu_vm {
- 	spinlock_t		freed_lock;
- };
- 
-+struct amdgpu_vm_manager_id {
-+	struct list_head	list;
-+	struct fence		*active;
-+	atomic_long_t		owner;
-+};
-+
- struct amdgpu_vm_manager {
--	/* protecting IDs */
-+	/* Handling of VMIDs */
- 	struct mutex				lock;
--
--	struct {
--		struct fence	*active;
--		atomic_long_t	owner;
--	} ids[AMDGPU_NUM_VM];
-+	unsigned				num_ids;
-+	struct list_head			ids_lru;
-+	struct amdgpu_vm_manager_id		ids[AMDGPU_NUM_VM];
- 
- 	uint32_t				max_pfn;
--	/* number of VMIDs */
--	unsigned				nvm;
- 	/* vram base address for page table entry  */
- 	u64					vram_base_offset;
- 	/* is vm enabled? */
-@@ -907,6 +909,7 @@ struct amdgpu_vm_manager {
- 	struct amdgpu_ring                      *vm_pte_funcs_ring;
- };
- 
-+void amdgpu_vm_manager_init(struct amdgpu_device *adev);
- void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 38ab4a5..796fe49 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -168,79 +168,52 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		      struct amdgpu_sync *sync, struct fence *fence)
- {
--	struct fence *best[AMDGPU_MAX_RINGS] = {};
- 	struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
- 	struct amdgpu_device *adev = ring->adev;
--
--	unsigned choices[2] = {};
--	unsigned i;
-+	struct amdgpu_vm_manager_id *id;
-+	int r;
- 
- 	mutex_lock(&adev->vm_manager.lock);
- 
- 	/* check if the id is still valid */
- 	if (vm_id->id) {
--		unsigned id = vm_id->id;
- 		long owner;
- 
--		owner = atomic_long_read(&adev->vm_manager.ids[id].owner);
-+		id = &adev->vm_manager.ids[vm_id->id];
-+		owner = atomic_long_read(&id->owner);
- 		if (owner == (long)vm) {
-+			list_move_tail(&id->list, &adev->vm_manager.ids_lru);
- 			trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx);
--			fence_put(adev->vm_manager.ids[id].active);
--			adev->vm_manager.ids[id].active = fence_get(fence);
--			mutex_unlock(&adev->vm_manager.lock);
--			return 0;
--		}
--	}
- 
--	/* we definately need to flush */
--	vm_id->pd_gpu_addr = ~0ll;
-+			fence_put(id->active);
-+			id->active = fence_get(fence);
- 
--	/* skip over VMID 0, since it is the system VM */
--	for (i = 1; i < adev->vm_manager.nvm; ++i) {
--		struct fence *fence = adev->vm_manager.ids[i].active;
--		struct amdgpu_ring *fring;
--
--		if (fence == NULL) {
--			/* found a free one */
--			vm_id->id = i;
--			trace_amdgpu_vm_grab_id(vm, i, ring->idx);
- 			mutex_unlock(&adev->vm_manager.lock);
- 			return 0;
- 		}
--
--		fring = amdgpu_ring_from_fence(fence);
--		if (best[fring->idx] == NULL ||
--		    fence_is_later(best[fring->idx], fence)) {
--			best[fring->idx] = fence;
--			choices[fring == ring ? 0 : 1] = i;
--		}
- 	}
- 
--	for (i = 0; i < 2; ++i) {
--		struct fence *active;
--		int r;
--
--		if (!choices[i])
--			continue;
-+	/* we definately need to flush */
-+	vm_id->pd_gpu_addr = ~0ll;
- 
--		vm_id->id = choices[i];
--		active  = adev->vm_manager.ids[vm_id->id].active;
--		r = amdgpu_sync_fence(ring->adev, sync, active);
-+	id = list_first_entry(&adev->vm_manager.ids_lru,
-+			      struct amdgpu_vm_manager_id,
-+			      list);
-+	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-+	atomic_long_set(&id->owner, (long)vm);
- 
--		trace_amdgpu_vm_grab_id(vm, choices[i], ring->idx);
--		atomic_long_set(&adev->vm_manager.ids[vm_id->id].owner, (long)vm);
-+	vm_id->id = id - adev->vm_manager.ids;
-+	trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx);
- 
--		fence_put(adev->vm_manager.ids[vm_id->id].active);
--		adev->vm_manager.ids[vm_id->id].active = fence_get(fence);
-+	r = amdgpu_sync_fence(ring->adev, sync, id->active);
- 
--		mutex_unlock(&adev->vm_manager.lock);
--		return r;
-+	if (!r) {
-+		fence_put(id->active);
-+		id->active = fence_get(fence);
- 	}
- 
--	/* should never happen */
--	BUG();
- 	mutex_unlock(&adev->vm_manager.lock);
--	return -EINVAL;
-+	return r;
- }
- 
- /**
-@@ -1366,6 +1339,25 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- }
- 
- /**
-+ * amdgpu_vm_manager_init - init the VM manager
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Initialize the VM manager structures
-+ */
-+void amdgpu_vm_manager_init(struct amdgpu_device *adev)
-+{
-+	unsigned i;
-+
-+	INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
-+
-+	/* skip over VMID 0, since it is the system VM */
-+	for (i = 1; i < adev->vm_manager.num_ids; ++i)
-+		list_add_tail(&adev->vm_manager.ids[i].list,
-+			      &adev->vm_manager.ids_lru);
-+}
-+
-+/**
-  * amdgpu_vm_manager_fini - cleanup VM manager
-  *
-  * @adev: amdgpu_device pointer
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index c01b861..7864318 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -694,7 +694,8 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
- 	 * amdgpu graphics/compute will use VMIDs 1-7
- 	 * amdkfd will use VMIDs 8-15
- 	 */
--	adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
-+	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
-+	amdgpu_vm_manager_init(adev);
- 
- 	/* base offset of vram pages */
- 	if (adev->flags & AMD_IS_APU) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index e59251f..009fe5f 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -774,7 +774,8 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
- 	 * amdgpu graphics/compute will use VMIDs 1-7
- 	 * amdkfd will use VMIDs 8-15
- 	 */
--	adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
-+	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
-+	amdgpu_vm_manager_init(adev);
- 
- 	/* base offset of vram pages */
- 	if (adev->flags & AMD_IS_APU) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0240-drm-amdgpu-remove-the-ring-lock-v2.patch b/common/recipes-kernel/linux/files/0240-drm-amdgpu-remove-the-ring-lock-v2.patch
deleted file mode 100644
index fa29b08c..00000000
--- a/common/recipes-kernel/linux/files/0240-drm-amdgpu-remove-the-ring-lock-v2.patch
+++ /dev/null
@@ -1,685 +0,0 @@
-From 1efdedaeccd078f50a532997bb0df5d5575e4a5b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 21 Jan 2016 11:28:53 +0100
-Subject: [PATCH 0240/1110] drm/amdgpu: remove the ring lock v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's not needed any more because all access goes through the scheduler now.
-
-v2: Update commit message.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  5 --
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |  6 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c     | 10 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 19 +++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 80 +++---------------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c    |  4 +-
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c      |  4 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c      |  8 +--
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      |  8 +--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c     |  4 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     |  4 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c      |  8 +--
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c      |  8 +--
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c      |  8 +--
- 15 files changed, 45 insertions(+), 132 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 5135635..e05c6f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -774,7 +774,6 @@ struct amdgpu_ring {
- 	struct amd_gpu_scheduler 	sched;
- 
- 	spinlock_t              fence_lock;
--	struct mutex		*ring_lock;
- 	struct amdgpu_bo	*ring_obj;
- 	volatile uint32_t	*ring;
- 	unsigned		rptr_offs;
-@@ -1156,12 +1155,9 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
- /* Ring access between begin & end cannot sleep */
- void amdgpu_ring_free_size(struct amdgpu_ring *ring);
- int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
--int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
- void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
- void amdgpu_ring_commit(struct amdgpu_ring *ring);
--void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
- void amdgpu_ring_undo(struct amdgpu_ring *ring);
--void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
- unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
- 			    uint32_t **data);
- int amdgpu_ring_restore(struct amdgpu_ring *ring,
-@@ -1975,7 +1971,6 @@ struct amdgpu_device {
- 
- 	/* rings */
- 	unsigned			fence_context;
--	struct mutex			ring_lock;
- 	unsigned			num_rings;
- 	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
- 	bool				ib_pool_ready;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 9bab3dc..f9c0393 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1455,7 +1455,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 
- 	/* mutex initialization are all done here so we
- 	 * can recall function without having locking issues */
--	mutex_init(&adev->ring_lock);
- 	mutex_init(&adev->vm_manager.lock);
- 	atomic_set(&adev->irq.ih.lock, 0);
- 	mutex_init(&adev->gem.mutex);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 08963fc..7210502 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -487,7 +487,6 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
- 
- 	if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
- 		kmem_cache_destroy(amdgpu_fence_slab);
--	mutex_lock(&adev->ring_lock);
- 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
- 		struct amdgpu_ring *ring = adev->rings[i];
- 
-@@ -505,7 +504,6 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
- 		del_timer_sync(&ring->fence_drv.fallback_timer);
- 		ring->fence_drv.initialized = false;
- 	}
--	mutex_unlock(&adev->ring_lock);
- }
- 
- /**
-@@ -520,7 +518,6 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
- {
- 	int i, r;
- 
--	mutex_lock(&adev->ring_lock);
- 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
- 		struct amdgpu_ring *ring = adev->rings[i];
- 		if (!ring || !ring->fence_drv.initialized)
-@@ -537,7 +534,6 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
- 		amdgpu_irq_put(adev, ring->fence_drv.irq_src,
- 			       ring->fence_drv.irq_type);
- 	}
--	mutex_unlock(&adev->ring_lock);
- }
- 
- /**
-@@ -556,7 +552,6 @@ void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
- {
- 	int i;
- 
--	mutex_lock(&adev->ring_lock);
- 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
- 		struct amdgpu_ring *ring = adev->rings[i];
- 		if (!ring || !ring->fence_drv.initialized)
-@@ -566,7 +561,6 @@ void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
- 		amdgpu_irq_get(adev, ring->fence_drv.irq_src,
- 			       ring->fence_drv.irq_type);
- 	}
--	mutex_unlock(&adev->ring_lock);
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 56ae9a5..40c9779 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -147,7 +147,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 		return -EINVAL;
- 	}
- 
--	r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
-+	r = amdgpu_ring_alloc(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
- 	if (r) {
- 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
- 		return r;
-@@ -155,7 +155,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 
- 	r = amdgpu_sync_wait(&ibs->sync);
- 	if (r) {
--		amdgpu_ring_unlock_undo(ring);
-+		amdgpu_ring_undo(ring);
- 		dev_err(adev->dev, "failed to sync wait (%d)\n", r);
- 		return r;
- 	}
-@@ -180,7 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 
- 		if (ib->ring != ring || ib->ctx != ctx || ib->vm != vm) {
- 			ring->current_ctx = old_ctx;
--			amdgpu_ring_unlock_undo(ring);
-+			amdgpu_ring_undo(ring);
- 			return -EINVAL;
- 		}
- 		amdgpu_ring_emit_ib(ring, ib);
-@@ -191,7 +191,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
- 		ring->current_ctx = old_ctx;
--		amdgpu_ring_unlock_undo(ring);
-+		amdgpu_ring_undo(ring);
- 		return r;
- 	}
- 
-@@ -203,7 +203,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 95a4a25..54e1cac 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -637,14 +637,12 @@ force:
- 		amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
- 	}
- 
--	mutex_lock(&adev->ring_lock);
--
- 	/* update whether vce is active */
- 	ps->vce_active = adev->pm.dpm.vce_active;
- 
- 	ret = amdgpu_dpm_pre_set_power_state(adev);
- 	if (ret)
--		goto done;
-+		return;
- 
- 	/* update display watermarks based on new power state */
- 	amdgpu_display_bandwidth_update(adev);
-@@ -682,9 +680,6 @@ force:
- 			amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
- 		}
- 	}
--
--done:
--	mutex_unlock(&adev->ring_lock);
- }
- 
- void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
-@@ -817,13 +812,11 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
- 		int i = 0;
- 
- 		amdgpu_display_bandwidth_update(adev);
--		mutex_lock(&adev->ring_lock);
--			for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
--				struct amdgpu_ring *ring = adev->rings[i];
--				if (ring && ring->ready)
--					amdgpu_fence_wait_empty(ring);
--			}
--		mutex_unlock(&adev->ring_lock);
-+		for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
-+			struct amdgpu_ring *ring = adev->rings[i];
-+			if (ring && ring->ready)
-+				amdgpu_fence_wait_empty(ring);
-+		}
- 
- 		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
- 	} else {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 66c6bbd..81d06d7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -105,30 +105,6 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
- 	return 0;
- }
- 
--/**
-- * amdgpu_ring_lock - lock the ring and allocate space on it
-- *
-- * @adev: amdgpu_device pointer
-- * @ring: amdgpu_ring structure holding ring information
-- * @ndw: number of dwords to allocate in the ring buffer
-- *
-- * Lock the ring and allocate @ndw dwords in the ring buffer
-- * (all asics).
-- * Returns 0 on success, error on failure.
-- */
--int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw)
--{
--	int r;
--
--	mutex_lock(ring->ring_lock);
--	r = amdgpu_ring_alloc(ring, ndw);
--	if (r) {
--		mutex_unlock(ring->ring_lock);
--		return r;
--	}
--	return 0;
--}
--
- /** amdgpu_ring_insert_nop - insert NOP packets
-  *
-  * @ring: amdgpu_ring structure holding ring information
-@@ -168,20 +144,6 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
- }
- 
- /**
-- * amdgpu_ring_unlock_commit - tell the GPU to execute the new
-- * commands on the ring buffer and unlock it
-- *
-- * @ring: amdgpu_ring structure holding ring information
-- *
-- * Call amdgpu_ring_commit() then unlock the ring (all asics).
-- */
--void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring)
--{
--	amdgpu_ring_commit(ring);
--	mutex_unlock(ring->ring_lock);
--}
--
--/**
-  * amdgpu_ring_undo - reset the wptr
-  *
-  * @ring: amdgpu_ring structure holding ring information
-@@ -194,19 +156,6 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring)
- }
- 
- /**
-- * amdgpu_ring_unlock_undo - reset the wptr and unlock the ring
-- *
-- * @ring: amdgpu_ring structure holding ring information
-- *
-- * Call amdgpu_ring_undo() then unlock the ring (all asics).
-- */
--void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring)
--{
--	amdgpu_ring_undo(ring);
--	mutex_unlock(ring->ring_lock);
--}
--
--/**
-  * amdgpu_ring_backup - Back up the content of a ring
-  *
-  * @ring: the ring we want to back up
-@@ -218,43 +167,32 @@ unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
- {
- 	unsigned size, ptr, i;
- 
--	/* just in case lock the ring */
--	mutex_lock(ring->ring_lock);
- 	*data = NULL;
- 
--	if (ring->ring_obj == NULL) {
--		mutex_unlock(ring->ring_lock);
-+	if (ring->ring_obj == NULL)
- 		return 0;
--	}
- 
- 	/* it doesn't make sense to save anything if all fences are signaled */
--	if (!amdgpu_fence_count_emitted(ring)) {
--		mutex_unlock(ring->ring_lock);
-+	if (!amdgpu_fence_count_emitted(ring))
- 		return 0;
--	}
- 
- 	ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
- 
- 	size = ring->wptr + (ring->ring_size / 4);
- 	size -= ptr;
- 	size &= ring->ptr_mask;
--	if (size == 0) {
--		mutex_unlock(ring->ring_lock);
-+	if (size == 0)
- 		return 0;
--	}
- 
- 	/* and then save the content of the ring */
- 	*data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
--	if (!*data) {
--		mutex_unlock(ring->ring_lock);
-+	if (!*data)
- 		return 0;
--	}
- 	for (i = 0; i < size; ++i) {
- 		(*data)[i] = ring->ring[ptr++];
- 		ptr &= ring->ptr_mask;
- 	}
- 
--	mutex_unlock(ring->ring_lock);
- 	return size;
- }
- 
-@@ -276,7 +214,7 @@ int amdgpu_ring_restore(struct amdgpu_ring *ring,
- 		return 0;
- 
- 	/* restore the saved ring content */
--	r = amdgpu_ring_lock(ring, size);
-+	r = amdgpu_ring_alloc(ring, size);
- 	if (r)
- 		return r;
- 
-@@ -284,7 +222,7 @@ int amdgpu_ring_restore(struct amdgpu_ring *ring,
- 		amdgpu_ring_write(ring, data[i]);
- 	}
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 	kfree(data);
- 	return 0;
- }
-@@ -352,7 +290,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		return r;
- 	}
- 
--	ring->ring_lock = &adev->ring_lock;
- 	/* Align ring size */
- 	rb_bufsz = order_base_2(ring_size / 8);
- 	ring_size = (1 << (rb_bufsz + 1)) * 4;
-@@ -410,15 +347,10 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
- 	int r;
- 	struct amdgpu_bo *ring_obj;
- 
--	if (ring->ring_lock == NULL)
--		return;
--
--	mutex_lock(ring->ring_lock);
- 	ring_obj = ring->ring_obj;
- 	ring->ready = false;
- 	ring->ring = NULL;
- 	ring->ring_obj = NULL;
--	mutex_unlock(ring->ring_lock);
- 
- 	amdgpu_wb_free(ring->adev, ring->fence_offs);
- 	amdgpu_wb_free(ring->adev, ring->rptr_offs);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index d83efc7..a96bfe1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -789,14 +789,14 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
- 	unsigned i;
- 	int r;
- 
--	r = amdgpu_ring_lock(ring, 16);
-+	r = amdgpu_ring_alloc(ring, 16);
- 	if (r) {
- 		DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
- 			  ring->idx, r);
- 		return r;
- 	}
- 	amdgpu_ring_write(ring, VCE_CMD_END);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		if (amdgpu_ring_get_rptr(ring) != rptr)
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 2aede8f..c70d7b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -560,7 +560,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 
--	r = amdgpu_ring_lock(ring, 5);
-+	r = amdgpu_ring_alloc(ring, 5);
- 	if (r) {
- 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
- 		amdgpu_wb_free(adev, index);
-@@ -571,7 +571,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
- 	amdgpu_ring_write(ring, 1); /* number of DWs to follow */
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = le32_to_cpu(adev->wb.wb[index]);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 82ede2f..bf0517d 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2379,7 +2379,7 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
- 		return r;
- 	}
- 	WREG32(scratch, 0xCAFEDEAD);
--	r = amdgpu_ring_lock(ring, 3);
-+	r = amdgpu_ring_alloc(ring, 3);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
- 		amdgpu_gfx_scratch_free(adev, scratch);
-@@ -2388,7 +2388,7 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
- 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = RREG32(scratch);
-@@ -2812,7 +2812,7 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
- 
- 	gfx_v7_0_cp_gfx_enable(adev, true);
- 
--	r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8);
-+	r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
- 		return r;
-@@ -2881,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
- 	amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
- 	amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 73d8ac0..3a2b060 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -652,7 +652,7 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
- 		return r;
- 	}
- 	WREG32(scratch, 0xCAFEDEAD);
--	r = amdgpu_ring_lock(ring, 3);
-+	r = amdgpu_ring_alloc(ring, 3);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
- 			  ring->idx, r);
-@@ -662,7 +662,7 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
- 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = RREG32(scratch);
-@@ -3062,7 +3062,7 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
- 
- 	gfx_v8_0_cp_gfx_enable(adev, true);
- 
--	r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
-+	r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
- 		return r;
-@@ -3126,7 +3126,7 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
- 	amdgpu_ring_write(ring, 0x8000);
- 	amdgpu_ring_write(ring, 0x8000);
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 77d5f29..e86f85f 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -611,7 +611,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 
--	r = amdgpu_ring_lock(ring, 5);
-+	r = amdgpu_ring_alloc(ring, 5);
- 	if (r) {
- 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
- 		amdgpu_wb_free(adev, index);
-@@ -624,7 +624,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
- 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = le32_to_cpu(adev->wb.wb[index]);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index d6170e6..b2fbf96 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -762,7 +762,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 
--	r = amdgpu_ring_lock(ring, 5);
-+	r = amdgpu_ring_alloc(ring, 5);
- 	if (r) {
- 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
- 		amdgpu_wb_free(adev, index);
-@@ -775,7 +775,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
- 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = le32_to_cpu(adev->wb.wb[index]);
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index fcc29c6..5ef96d6 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -164,7 +164,7 @@ static int uvd_v4_2_hw_init(void *handle)
- 		goto done;
- 	}
- 
--	r = amdgpu_ring_lock(ring, 10);
-+	r = amdgpu_ring_alloc(ring, 10);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
- 		goto done;
-@@ -189,7 +189,7 @@ static int uvd_v4_2_hw_init(void *handle)
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
- 	amdgpu_ring_write(ring, 3);
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- done:
- 	/* lower clocks again */
-@@ -453,7 +453,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
- 	int r;
- 
- 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
--	r = amdgpu_ring_lock(ring, 3);
-+	r = amdgpu_ring_alloc(ring, 3);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
- 			  ring->idx, r);
-@@ -461,7 +461,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
- 	}
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = RREG32(mmUVD_CONTEXT_ID);
- 		if (tmp == 0xDEADBEEF)
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 67be97c..7d67772 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -160,7 +160,7 @@ static int uvd_v5_0_hw_init(void *handle)
- 		goto done;
- 	}
- 
--	r = amdgpu_ring_lock(ring, 10);
-+	r = amdgpu_ring_alloc(ring, 10);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
- 		goto done;
-@@ -185,7 +185,7 @@ static int uvd_v5_0_hw_init(void *handle)
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
- 	amdgpu_ring_write(ring, 3);
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- done:
- 	/* lower clocks again */
-@@ -497,7 +497,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
- 	int r;
- 
- 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
--	r = amdgpu_ring_lock(ring, 3);
-+	r = amdgpu_ring_alloc(ring, 3);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
- 			  ring->idx, r);
-@@ -505,7 +505,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
- 	}
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = RREG32(mmUVD_CONTEXT_ID);
- 		if (tmp == 0xDEADBEEF)
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 4d64769..2ef8150 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -157,7 +157,7 @@ static int uvd_v6_0_hw_init(void *handle)
- 		goto done;
- 	}
- 
--	r = amdgpu_ring_lock(ring, 10);
-+	r = amdgpu_ring_alloc(ring, 10);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
- 		goto done;
-@@ -182,7 +182,7 @@ static int uvd_v6_0_hw_init(void *handle)
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
- 	amdgpu_ring_write(ring, 3);
- 
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 
- done:
- 	if (!r)
-@@ -736,7 +736,7 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
- 	int r;
- 
- 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
--	r = amdgpu_ring_lock(ring, 3);
-+	r = amdgpu_ring_alloc(ring, 3);
- 	if (r) {
- 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
- 			  ring->idx, r);
-@@ -744,7 +744,7 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
- 	}
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
- 	amdgpu_ring_write(ring, 0xDEADBEEF);
--	amdgpu_ring_unlock_commit(ring);
-+	amdgpu_ring_commit(ring);
- 	for (i = 0; i < adev->usec_timeout; i++) {
- 		tmp = RREG32(mmUVD_CONTEXT_ID);
- 		if (tmp == 0xDEADBEEF)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0241-drm-amdgpu-remove-rptr-checking.patch b/common/recipes-kernel/linux/files/0241-drm-amdgpu-remove-rptr-checking.patch
deleted file mode 100644
index 4f03c26e..00000000
--- a/common/recipes-kernel/linux/files/0241-drm-amdgpu-remove-rptr-checking.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From 35c5c7e91428453adf034b3644077eb813701521 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 21 Jan 2016 13:06:05 +0100
-Subject: [PATCH 0241/1110] drm/amdgpu: remove rptr checking
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With the scheduler enabled we don't need that any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  5 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 77 +++++++++++---------------------
- 2 files changed, 26 insertions(+), 56 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e05c6f4..de1e6ca 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -782,7 +782,7 @@ struct amdgpu_ring {
- 	unsigned		wptr;
- 	unsigned		wptr_old;
- 	unsigned		ring_size;
--	unsigned		ring_free_dw;
-+	unsigned		max_dw;
- 	int			count_dw;
- 	uint64_t		gpu_addr;
- 	uint32_t		align_mask;
-@@ -1152,8 +1152,6 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
- void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
- int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
--/* Ring access between begin & end cannot sleep */
--void amdgpu_ring_free_size(struct amdgpu_ring *ring);
- int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
- void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
- void amdgpu_ring_commit(struct amdgpu_ring *ring);
-@@ -2129,7 +2127,6 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
- 	ring->ring[ring->wptr++] = v;
- 	ring->wptr &= ring->ptr_mask;
- 	ring->count_dw--;
--	ring->ring_free_dw--;
- }
- 
- static inline struct amdgpu_sdma_instance *
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 81d06d7..1f0db99 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -49,28 +49,6 @@
- static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
- 
- /**
-- * amdgpu_ring_free_size - update the free size
-- *
-- * @adev: amdgpu_device pointer
-- * @ring: amdgpu_ring structure holding ring information
-- *
-- * Update the free dw slots in the ring buffer (all asics).
-- */
--void amdgpu_ring_free_size(struct amdgpu_ring *ring)
--{
--	uint32_t rptr = amdgpu_ring_get_rptr(ring);
--
--	/* This works because ring_size is a power of 2 */
--	ring->ring_free_dw = rptr + (ring->ring_size / 4);
--	ring->ring_free_dw -= ring->wptr;
--	ring->ring_free_dw &= ring->ptr_mask;
--	if (!ring->ring_free_dw) {
--		/* this is an empty ring */
--		ring->ring_free_dw = ring->ring_size / 4;
--	}
--}
--
--/**
-  * amdgpu_ring_alloc - allocate space on the ring buffer
-  *
-  * @adev: amdgpu_device pointer
-@@ -82,24 +60,16 @@ void amdgpu_ring_free_size(struct amdgpu_ring *ring)
-  */
- int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
- {
--	int r;
--
--	/* make sure we aren't trying to allocate more space than there is on the ring */
--	if (ndw > (ring->ring_size / 4))
--		return -ENOMEM;
- 	/* Align requested size with padding so unlock_commit can
- 	 * pad safely */
--	amdgpu_ring_free_size(ring);
- 	ndw = (ndw + ring->align_mask) & ~ring->align_mask;
--	while (ndw > (ring->ring_free_dw - 1)) {
--		amdgpu_ring_free_size(ring);
--		if (ndw < ring->ring_free_dw) {
--			break;
--		}
--		r = amdgpu_fence_wait_next(ring);
--		if (r)
--			return r;
--	}
-+
-+	/* Make sure we aren't trying to allocate more space
-+	 * than the maximum for one submission
-+	 */
-+	if (WARN_ON_ONCE(ndw > ring->max_dw))
-+		return -ENOMEM;
-+
- 	ring->count_dw = ndw;
- 	ring->wptr_old = ring->wptr;
- 	return 0;
-@@ -326,7 +296,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		}
- 	}
- 	ring->ptr_mask = (ring->ring_size / 4) - 1;
--	ring->ring_free_dw = ring->ring_size / 4;
-+	ring->max_dw = DIV_ROUND_UP(ring->ring_size / 4,
-+				    amdgpu_sched_hw_submission);
- 
- 	if (amdgpu_debugfs_ring_init(adev, ring)) {
- 		DRM_ERROR("Failed to register debugfs file for rings !\n");
-@@ -406,25 +377,18 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- 	struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset);
- 
- 	uint32_t rptr, wptr, rptr_next;
--	unsigned count, i, j;
--
--	amdgpu_ring_free_size(ring);
--	count = (ring->ring_size / 4) - ring->ring_free_dw;
-+	unsigned i;
- 
- 	wptr = amdgpu_ring_get_wptr(ring);
--	seq_printf(m, "wptr: 0x%08x [%5d]\n",
--		   wptr, wptr);
-+	seq_printf(m, "wptr: 0x%08x [%5d]\n", wptr, wptr);
- 
- 	rptr = amdgpu_ring_get_rptr(ring);
--	seq_printf(m, "rptr: 0x%08x [%5d]\n",
--		   rptr, rptr);
--
- 	rptr_next = le32_to_cpu(*ring->next_rptr_cpu_addr);
- 
-+	seq_printf(m, "rptr: 0x%08x [%5d]\n", rptr, rptr);
-+
- 	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
- 		   ring->wptr, ring->wptr);
--	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
--	seq_printf(m, "%u dwords in ring\n", count);
- 
- 	if (!ring->ready)
- 		return 0;
-@@ -433,11 +397,20 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- 	 * packet that is the root issue
- 	 */
- 	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
--	for (j = 0; j <= (count + 32); j++) {
-+	while (i != rptr) {
-+		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
-+		if (i == rptr)
-+			seq_puts(m, " *");
-+		if (i == rptr_next)
-+			seq_puts(m, " #");
-+		seq_puts(m, "\n");
-+		i = (i + 1) & ring->ptr_mask;
-+	}
-+	while (i != wptr) {
- 		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
--		if (rptr == i)
-+		if (i == rptr)
- 			seq_puts(m, " *");
--		if (rptr_next == i)
-+		if (i == rptr_next)
- 			seq_puts(m, " #");
- 		seq_puts(m, "\n");
- 		i = (i + 1) & ring->ptr_mask;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0242-drm-amd-powerplay-add-some-sysfs-interfaces-for-powe.patch b/common/recipes-kernel/linux/files/0242-drm-amd-powerplay-add-some-sysfs-interfaces-for-powe.patch
deleted file mode 100644
index f9455e9d..00000000
--- a/common/recipes-kernel/linux/files/0242-drm-amd-powerplay-add-some-sysfs-interfaces-for-powe.patch
+++ /dev/null
@@ -1,653 +0,0 @@
-From 86b96db7ca91553b3c87bad0206a6493257a74ea Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 11 Dec 2015 16:24:34 -0500
-Subject: [PATCH 0242/1110] drm/amd/powerplay: add some sysfs interfaces for
- powerplay.
-
-The new sysfs interfaces:
-pp_num_states: Read-only, return the number of all pp states, 0 if powerplay is not available.
-pp_cur_state: Read-only, return the index number of current pp state.
-pp_force_state: Read-write, to write a power state index will switch to selected state forcedly and
-		enable forced state mode, disable forced state mode. such as "echo >...".
-pp_table: Read-write, binary output, to be used to read or write the dpm table, the maximum
-		file size is 4KB of page size.
-pp_dpm_sclk: Read-write, reading will return a dpm levels list, to write an index number will force
-		powerplay to set the corresponding dpm level.
-pp_dpm_mclk: same as sclk.
-pp_dpm_pcie: same as sclk.
-
-And add new setting "manual" to the existing interface power_dpm_force_performance_level.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h               |  17 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c            | 336 +++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 116 +++++++-
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  17 ++
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |   4 +
- 5 files changed, 488 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index de1e6ca..0e65ffe 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1468,6 +1468,7 @@ enum amdgpu_dpm_forced_level {
- 	AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
- 	AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
- 	AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
-+	AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
- };
- 
- struct amdgpu_vce_state {
-@@ -1980,6 +1981,7 @@ struct amdgpu_device {
- 	/* powerplay */
- 	struct amd_powerplay		powerplay;
- 	bool				pp_enabled;
-+	bool				pp_force_state_enabled;
- 
- 	/* dpm */
- 	struct amdgpu_pm		pm;
-@@ -2267,6 +2269,21 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_dpm_get_performance_level(adev) \
- 	(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
- 
-+#define amdgpu_dpm_get_pp_num_states(adev, data) \
-+	(adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
-+
-+#define amdgpu_dpm_get_pp_table(adev, table) \
-+	(adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
-+
-+#define amdgpu_dpm_set_pp_table(adev, buf, size) \
-+	(adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
-+
-+#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
-+	(adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
-+
-+#define amdgpu_dpm_force_clock_level(adev, type, level) \
-+		(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
-+
- #define amdgpu_dpm_dispatch_task(adev, event_id, input, output)		\
- 	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 54e1cac..ff9597c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -123,7 +123,9 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
- 		level = amdgpu_dpm_get_performance_level(adev);
- 		return snprintf(buf, PAGE_SIZE, "%s\n",
- 				(level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
--				(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
-+				(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
-+				(level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
-+				(level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
- 	} else {
- 		enum amdgpu_dpm_forced_level level;
- 
-@@ -155,6 +157,8 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
- 		level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
- 	} else if (strncmp("auto", buf, strlen("auto")) == 0) {
- 		level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
-+	} else if (strncmp("manual", buf, strlen("manual")) == 0) {
-+		level = AMDGPU_DPM_FORCED_LEVEL_MANUAL;
- 	} else {
- 		count = -EINVAL;
- 		goto fail;
-@@ -180,10 +184,293 @@ fail:
- 	return count;
- }
- 
-+static ssize_t amdgpu_get_pp_num_states(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	struct pp_states_info data;
-+	int i, buf_len;
-+
-+	if (adev->pp_enabled)
-+		amdgpu_dpm_get_pp_num_states(adev, &data);
-+
-+	buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
-+	for (i = 0; i < data.nums; i++)
-+		buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
-+				(data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
-+				(data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
-+				(data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
-+				(data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
-+
-+	return buf_len;
-+}
-+
-+static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	struct pp_states_info data;
-+	enum amd_pm_state_type pm = 0;
-+	int i = 0;
-+
-+	if (adev->pp_enabled) {
-+
-+		pm = amdgpu_dpm_get_current_power_state(adev);
-+		amdgpu_dpm_get_pp_num_states(adev, &data);
-+
-+		for (i = 0; i < data.nums; i++) {
-+			if (pm == data.states[i])
-+				break;
-+		}
-+
-+		if (i == data.nums)
-+			i = -EINVAL;
-+	}
-+
-+	return snprintf(buf, PAGE_SIZE, "%d\n", i);
-+}
-+
-+static ssize_t amdgpu_get_pp_force_state(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	struct pp_states_info data;
-+	enum amd_pm_state_type pm = 0;
-+	int i;
-+
-+	if (adev->pp_force_state_enabled && adev->pp_enabled) {
-+		pm = amdgpu_dpm_get_current_power_state(adev);
-+		amdgpu_dpm_get_pp_num_states(adev, &data);
-+
-+		for (i = 0; i < data.nums; i++) {
-+			if (pm == data.states[i])
-+				break;
-+		}
-+
-+		if (i == data.nums)
-+			i = -EINVAL;
-+
-+		return snprintf(buf, PAGE_SIZE, "%d\n", i);
-+
-+	} else
-+		return snprintf(buf, PAGE_SIZE, "\n");
-+}
-+
-+static ssize_t amdgpu_set_pp_force_state(struct device *dev,
-+		struct device_attribute *attr,
-+		const char *buf,
-+		size_t count)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	enum amd_pm_state_type state = 0;
-+	long idx;
-+	int ret;
-+
-+	if (strlen(buf) == 1)
-+		adev->pp_force_state_enabled = false;
-+	else {
-+		ret = kstrtol(buf, 0, &idx);
-+
-+		if (ret) {
-+			count = -EINVAL;
-+			goto fail;
-+		}
-+
-+		if (adev->pp_enabled) {
-+			struct pp_states_info data;
-+			amdgpu_dpm_get_pp_num_states(adev, &data);
-+			state = data.states[idx];
-+			/* only set user selected power states */
-+			if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
-+				state != POWER_STATE_TYPE_DEFAULT) {
-+				amdgpu_dpm_dispatch_task(adev,
-+						AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
-+				adev->pp_force_state_enabled = true;
-+			}
-+		}
-+	}
-+fail:
-+	return count;
-+}
-+
-+static ssize_t amdgpu_get_pp_table(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	char *table = NULL;
-+	int size, i;
-+
-+	if (adev->pp_enabled)
-+		size = amdgpu_dpm_get_pp_table(adev, &table);
-+	else
-+		return 0;
-+
-+	if (size >= PAGE_SIZE)
-+		size = PAGE_SIZE - 1;
-+
-+	for (i = 0; i < size; i++) {
-+		sprintf(buf + i, "%02x", table[i]);
-+	}
-+	sprintf(buf + i, "\n");
-+
-+	return size;
-+}
-+
-+static ssize_t amdgpu_set_pp_table(struct device *dev,
-+		struct device_attribute *attr,
-+		const char *buf,
-+		size_t count)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+
-+	if (adev->pp_enabled)
-+		amdgpu_dpm_set_pp_table(adev, buf, count);
-+
-+	return count;
-+}
-+
-+static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	ssize_t size = 0;
-+
-+	if (adev->pp_enabled)
-+		size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
-+
-+	return size;
-+}
-+
-+static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
-+		struct device_attribute *attr,
-+		const char *buf,
-+		size_t count)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	int ret;
-+	long level;
-+
-+	ret = kstrtol(buf, 0, &level);
-+
-+	if (ret) {
-+		count = -EINVAL;
-+		goto fail;
-+	}
-+
-+	if (adev->pp_enabled)
-+		amdgpu_dpm_force_clock_level(adev, PP_SCLK, level);
-+fail:
-+	return count;
-+}
-+
-+static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	ssize_t size = 0;
-+
-+	if (adev->pp_enabled)
-+		size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
-+
-+	return size;
-+}
-+
-+static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
-+		struct device_attribute *attr,
-+		const char *buf,
-+		size_t count)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	int ret;
-+	long level;
-+
-+	ret = kstrtol(buf, 0, &level);
-+
-+	if (ret) {
-+		count = -EINVAL;
-+		goto fail;
-+	}
-+
-+	if (adev->pp_enabled)
-+		amdgpu_dpm_force_clock_level(adev, PP_MCLK, level);
-+fail:
-+	return count;
-+}
-+
-+static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
-+		struct device_attribute *attr,
-+		char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	ssize_t size = 0;
-+
-+	if (adev->pp_enabled)
-+		size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
-+
-+	return size;
-+}
-+
-+static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
-+		struct device_attribute *attr,
-+		const char *buf,
-+		size_t count)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	int ret;
-+	long level;
-+
-+	ret = kstrtol(buf, 0, &level);
-+
-+	if (ret) {
-+		count = -EINVAL;
-+		goto fail;
-+	}
-+
-+	if (adev->pp_enabled)
-+		amdgpu_dpm_force_clock_level(adev, PP_PCIE, level);
-+fail:
-+	return count;
-+}
-+
- static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
- static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
- 		   amdgpu_get_dpm_forced_performance_level,
- 		   amdgpu_set_dpm_forced_performance_level);
-+static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
-+static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
-+static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
-+		amdgpu_get_pp_force_state,
-+		amdgpu_set_pp_force_state);
-+static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
-+		amdgpu_get_pp_table,
-+		amdgpu_set_pp_table);
-+static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
-+		amdgpu_get_pp_dpm_sclk,
-+		amdgpu_set_pp_dpm_sclk);
-+static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
-+		amdgpu_get_pp_dpm_mclk,
-+		amdgpu_set_pp_dpm_mclk);
-+static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
-+		amdgpu_get_pp_dpm_pcie,
-+		amdgpu_set_pp_dpm_pcie);
- 
- static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
- 				      struct device_attribute *attr,
-@@ -780,6 +1067,44 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
- 		DRM_ERROR("failed to create device file for dpm state\n");
- 		return ret;
- 	}
-+
-+	if (adev->pp_enabled) {
-+		ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_num_states\n");
-+			return ret;
-+		}
-+		ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_cur_state\n");
-+			return ret;
-+		}
-+		ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_force_state\n");
-+			return ret;
-+		}
-+		ret = device_create_file(adev->dev, &dev_attr_pp_table);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_table\n");
-+			return ret;
-+		}
-+		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_dpm_sclk\n");
-+			return ret;
-+		}
-+		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_dpm_mclk\n");
-+			return ret;
-+		}
-+		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
-+		if (ret) {
-+			DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-+			return ret;
-+		}
-+	}
- 	ret = amdgpu_debugfs_pm_init(adev);
- 	if (ret) {
- 		DRM_ERROR("Failed to register debugfs file for dpm!\n");
-@@ -797,6 +1122,15 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
- 		hwmon_device_unregister(adev->pm.int_hwmon_dev);
- 	device_remove_file(adev->dev, &dev_attr_power_dpm_state);
- 	device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
-+	if (adev->pp_enabled) {
-+		device_remove_file(adev->dev, &dev_attr_pp_num_states);
-+		device_remove_file(adev->dev, &dev_attr_pp_cur_state);
-+		device_remove_file(adev->dev, &dev_attr_pp_force_state);
-+		device_remove_file(adev->dev, &dev_attr_pp_table);
-+		device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
-+		device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
-+		device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
-+	}
- }
- 
- void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 589599f..bbc6bda 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -436,7 +436,10 @@ enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
- 	case PP_StateUILabel_Performance:
- 		return POWER_STATE_TYPE_PERFORMANCE;
- 	default:
--		return POWER_STATE_TYPE_DEFAULT;
-+		if (state->classification.flags & PP_StateClassificationFlag_Boot)
-+			return  POWER_STATE_TYPE_INTERNAL_BOOT;
-+		else
-+			return POWER_STATE_TYPE_DEFAULT;
- 	}
- }
- 
-@@ -538,6 +541,112 @@ static int pp_dpm_get_temperature(void *handle)
- 	return hwmgr->hwmgr_func->get_temperature(hwmgr);
- }
- 
-+static int pp_dpm_get_pp_num_states(void *handle,
-+		struct pp_states_info *data)
-+{
-+	struct pp_hwmgr *hwmgr;
-+	int i;
-+
-+	if (!handle)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->ps == NULL)
-+		return -EINVAL;
-+
-+	data->nums = hwmgr->num_ps;
-+
-+	for (i = 0; i < hwmgr->num_ps; i++) {
-+		struct pp_power_state *state = (struct pp_power_state *)
-+				((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
-+		switch (state->classification.ui_label) {
-+		case PP_StateUILabel_Battery:
-+			data->states[i] = POWER_STATE_TYPE_BATTERY;
-+			break;
-+		case PP_StateUILabel_Balanced:
-+			data->states[i] = POWER_STATE_TYPE_BALANCED;
-+			break;
-+		case PP_StateUILabel_Performance:
-+			data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
-+			break;
-+		default:
-+			if (state->classification.flags & PP_StateClassificationFlag_Boot)
-+				data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
-+			else
-+				data->states[i] = POWER_STATE_TYPE_DEFAULT;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int pp_dpm_get_pp_table(void *handle, char **table)
-+{
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (!handle)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+		hwmgr->hwmgr_func->get_pp_table == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_pp_table(hwmgr, table);
-+}
-+
-+static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
-+{
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (!handle)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+		hwmgr->hwmgr_func->set_pp_table == NULL)
-+			return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
-+}
-+
-+static int pp_dpm_force_clock_level(void *handle,
-+		enum pp_clock_type type, int level)
-+{
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (!handle)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+			hwmgr->hwmgr_func->force_clock_level == NULL)
-+				return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
-+}
-+
-+static int pp_dpm_print_clock_levels(void *handle,
-+		enum pp_clock_type type, char *buf)
-+{
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (!handle)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+			hwmgr->hwmgr_func->print_clock_levels == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
-+}
-+
- const struct amd_powerplay_funcs pp_dpm_funcs = {
- 	.get_temperature = pp_dpm_get_temperature,
- 	.load_firmware = pp_dpm_load_fw,
-@@ -555,6 +664,11 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
- 	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
- 	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
- 	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
-+	.get_pp_num_states = pp_dpm_get_pp_num_states,
-+	.get_pp_table = pp_dpm_get_pp_table,
-+	.set_pp_table = pp_dpm_set_pp_table,
-+	.force_clock_level = pp_dpm_force_clock_level,
-+	.print_clock_levels = pp_dpm_print_clock_levels,
- };
- 
- static int amd_pp_instance_init(struct amd_pp_init *pp_init,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index d9b8d3f..ee23606 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -122,6 +122,7 @@ enum amd_dpm_forced_level {
- 	AMD_DPM_FORCED_LEVEL_AUTO = 0,
- 	AMD_DPM_FORCED_LEVEL_LOW = 1,
- 	AMD_DPM_FORCED_LEVEL_HIGH = 2,
-+	AMD_DPM_FORCED_LEVEL_MANUAL = 3,
- };
- 
- struct amd_pp_init {
-@@ -224,6 +225,17 @@ enum {
- 	PP_GROUP_MAX
- };
- 
-+enum pp_clock_type {
-+	PP_SCLK,
-+	PP_MCLK,
-+	PP_PCIE,
-+};
-+
-+struct pp_states_info {
-+	uint32_t nums;
-+	uint32_t states[16];
-+};
-+
- #define PP_GROUP_MASK        0xF0000000
- #define PP_GROUP_SHIFT       28
- 
-@@ -277,6 +289,11 @@ struct amd_powerplay_funcs {
- 	int (*get_fan_control_mode)(void *handle);
- 	int (*set_fan_speed_percent)(void *handle, uint32_t percent);
- 	int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
-+	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
-+	int (*get_pp_table)(void *handle, char **table);
-+	int (*set_pp_table)(void *handle, const char *buf, size_t size);
-+	int (*force_clock_level)(void *handle, enum pp_clock_type type, int level);
-+	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
- };
- 
- struct amd_powerplay {
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index aeaa3db..4094e81 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -327,6 +327,10 @@ struct pp_hwmgr_func {
- 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
- 				   struct amd_pp_dal_clock_info *info);
- 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
-+	int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table);
-+	int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
-+	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level);
-+	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
- };
- 
- struct pp_table_func {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0243-drm-amd-powerplay-add-hwmgr-s-functions-for-Fiji-sys.patch b/common/recipes-kernel/linux/files/0243-drm-amd-powerplay-add-hwmgr-s-functions-for-Fiji-sys.patch
deleted file mode 100644
index 8477970b..00000000
--- a/common/recipes-kernel/linux/files/0243-drm-amd-powerplay-add-hwmgr-s-functions-for-Fiji-sys.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From d9df71d3bf0c2a1d106d4f576d8c03d526e5c821 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 14 Dec 2015 13:49:37 -0500
-Subject: [PATCH 0243/1110] drm/amd/powerplay: add hwmgr's functions for Fiji
- sysfs interfaces.
-
-These add the interfaces for manual clock control.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 123 +++++++++++++++++++++++
- 1 file changed, 123 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 28031a7..5cca2ec 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -5073,6 +5073,125 @@ static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
- 				CG_FDO_CTRL2, FDO_PWM_MODE);
- }
- 
-+static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	*table = (char *)&data->smc_state_table;
-+
-+	return sizeof(struct SMU73_Discrete_DpmTable);
-+}
-+
-+static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	void *table = (void *)&data->smc_state_table;
-+
-+	memcpy(table, buf, size);
-+
-+	return 0;
-+}
-+
-+static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, int level)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-+		return -EINVAL;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		if (!data->sclk_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					(1 << level));
-+		break;
-+	case PP_MCLK:
-+		if (!data->mclk_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+					(1 << level));
-+		break;
-+	case PP_PCIE:
-+		if (!data->pcie_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_PCIeDPM_ForceLevel,
-+					(1 << level));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, char *buf)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
-+	struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
-+	struct fiji_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
-+	int i, now, size = 0;
-+	uint32_t clock, pcie_speed;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+		for (i = 0; i < sclk_table->count; i++) {
-+			if (clock > sclk_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < sclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, sclk_table->dpm_levels[i].value / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	case PP_MCLK:
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+		for (i = 0; i < mclk_table->count; i++) {
-+			if (clock > mclk_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < mclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, mclk_table->dpm_levels[i].value / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	case PP_PCIE:
-+		pcie_speed = fiji_get_current_pcie_speed(hwmgr);
-+		for (i = 0; i < pcie_table->count; i++) {
-+			if (pcie_speed != pcie_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < pcie_table->count; i++)
-+			size += sprintf(buf + size, "%d: %s %s\n", i,
-+					(pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
-+					(pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
-+					(pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
-+					(i == now) ? "*" : "");
-+		break;
-+	default:
-+		break;
-+	}
-+	return size;
-+}
-+
- static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.backend_init = &fiji_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -5108,6 +5227,10 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
- 	.set_fan_control_mode = fiji_set_fan_control_mode,
- 	.get_fan_control_mode = fiji_get_fan_control_mode,
-+	.get_pp_table = fiji_get_pp_table,
-+	.set_pp_table = fiji_set_pp_table,
-+	.force_clock_level = fiji_force_clock_level,
-+	.print_clock_levels = fiji_print_clock_levels,
- };
- 
- int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0244-drm-amd-powerplay-add-some-hwmgr-functions-for-sysfs.patch b/common/recipes-kernel/linux/files/0244-drm-amd-powerplay-add-some-hwmgr-functions-for-sysfs.patch
deleted file mode 100644
index 1c22f571..00000000
--- a/common/recipes-kernel/linux/files/0244-drm-amd-powerplay-add-some-hwmgr-functions-for-sysfs.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From a037838e547bdba915c705838fed8032d715a5d5 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 22 Jan 2016 12:17:41 -0500
-Subject: [PATCH 0244/1110] drm/amd/powerplay: add some hwmgr functions for
- sysfs interface on Carrizo
-
-These add the interfaces for manual clock control.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 51 ++++++++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index cf01177..1e90cbf 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1718,6 +1718,54 @@ static void cz_hw_print_display_cfg(
- 	return -EINVAL;
- }
- 
-+static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, int level)
-+{
-+	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-+		return -EINVAL;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMin,
-+				(1 << level));
-+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetSclkSoftMax,
-+				(1 << level));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, char *buf)
-+{
-+	struct phm_clock_voltage_dependency_table *sclk_table =
-+			hwmgr->dyn_state.vddc_dependency_on_sclk;
-+	int i, now, size = 0;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC,
-+				ixTARGET_AND_CURRENT_PROFILE_INDEX),
-+				TARGET_AND_CURRENT_PROFILE_INDEX,
-+				CURR_SCLK_INDEX);
-+
-+		for (i = 0; i < sclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, sclk_table->entries[i].clk / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	default:
-+		break;
-+	}
-+	return size;
-+}
-+
- static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.backend_init = cz_hwmgr_backend_init,
- 	.backend_fini = cz_hwmgr_backend_fini,
-@@ -1737,6 +1785,9 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.set_cpu_power_state = cz_set_cpu_power_state,
- 	.store_cc6_data = cz_store_cc6_data,
- 	.get_dal_power_level= cz_get_dal_power_level,
-+	.force_clock_level = cz_force_clock_level,
-+	.print_clock_levels = cz_print_clock_levels,
-+
- };
- 
- int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0245-drm-amd-powerplay-add-some-hwmgr-functions-for-sysfs.patch b/common/recipes-kernel/linux/files/0245-drm-amd-powerplay-add-some-hwmgr-functions-for-sysfs.patch
deleted file mode 100644
index 27496656..00000000
--- a/common/recipes-kernel/linux/files/0245-drm-amd-powerplay-add-some-hwmgr-functions-for-sysfs.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 881a832dca571e68140df46e16cbfe7b5869af8f Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 22 Jan 2016 14:32:41 -0500
-Subject: [PATCH 0245/1110] drm/amd/powerplay: add some hwmgr functions for
- sysfs interface on Tonga
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 123 ++++++++++++++++++++++
- 1 file changed, 123 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 980d3bf..aec4f83 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -6033,6 +6033,125 @@ static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
- 				CG_FDO_CTRL2, FDO_PWM_MODE);
- }
- 
-+static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	*table = (char *)&data->smc_state_table;
-+
-+	return sizeof(struct SMU72_Discrete_DpmTable);
-+}
-+
-+static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	void *table = (void *)&data->smc_state_table;
-+
-+	memcpy(table, buf, size);
-+
-+	return 0;
-+}
-+
-+static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, int level)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+
-+	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-+		return -EINVAL;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		if (!data->sclk_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					(1 << level));
-+		break;
-+	case PP_MCLK:
-+		if (!data->mclk_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+					(1 << level));
-+		break;
-+	case PP_PCIE:
-+		if (!data->pcie_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_PCIeDPM_ForceLevel,
-+					(1 << level));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, char *buf)
-+{
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
-+	struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
-+	struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
-+	struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
-+	int i, now, size = 0;
-+	uint32_t clock, pcie_speed;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+		for (i = 0; i < sclk_table->count; i++) {
-+			if (clock > sclk_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < sclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, sclk_table->dpm_levels[i].value / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	case PP_MCLK:
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+		for (i = 0; i < mclk_table->count; i++) {
-+			if (clock > mclk_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < mclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, mclk_table->dpm_levels[i].value / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	case PP_PCIE:
-+		pcie_speed = tonga_get_current_pcie_speed(hwmgr);
-+		for (i = 0; i < pcie_table->count; i++) {
-+			if (pcie_speed != pcie_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < pcie_table->count; i++)
-+			size += sprintf(buf + size, "%d: %s %s\n", i,
-+					(pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
-+					(pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
-+					(pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
-+					(i == now) ? "*" : "");
-+		break;
-+	default:
-+		break;
-+	}
-+	return size;
-+}
-+
- static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.backend_init = &tonga_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -6070,6 +6189,10 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.check_states_equal = tonga_check_states_equal,
- 	.set_fan_control_mode = tonga_set_fan_control_mode,
- 	.get_fan_control_mode = tonga_get_fan_control_mode,
-+	.get_pp_table = tonga_get_pp_table,
-+	.set_pp_table = tonga_set_pp_table,
-+	.force_clock_level = tonga_force_clock_level,
-+	.print_clock_levels = tonga_print_clock_levels,
- };
- 
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0246-drm-amd-add-dce8-enum-register-header.patch b/common/recipes-kernel/linux/files/0246-drm-amd-add-dce8-enum-register-header.patch
deleted file mode 100644
index 5e2668e3..00000000
--- a/common/recipes-kernel/linux/files/0246-drm-amd-add-dce8-enum-register-header.patch
+++ /dev/null
@@ -1,1144 +0,0 @@
-From bc9efa2a39fc9ec181b742fb0a374493d907349a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 27 Jan 2016 11:09:50 -0500
-Subject: [PATCH 0246/1110] drm/amd: add dce8 enum register header
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This adds the DCE8 enum header.
-
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/include/asic_reg/dce/dce_8_0_enum.h    | 1117 ++++++++++++++++++++
- 1 file changed, 1117 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
-new file mode 100644
-index 0000000..6bea30e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
-@@ -0,0 +1,1117 @@
-+/*
-+ * DCE_8_0 Register documentation
-+ *
-+ * Copyright (C) 2016  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef DCE_8_0_ENUM_H
-+#define DCE_8_0_ENUM_H
-+
-+typedef enum SurfaceEndian {
-+	ENDIAN_NONE                                      = 0x0,
-+	ENDIAN_8IN16                                     = 0x1,
-+	ENDIAN_8IN32                                     = 0x2,
-+	ENDIAN_8IN64                                     = 0x3,
-+} SurfaceEndian;
-+typedef enum ArrayMode {
-+	ARRAY_LINEAR_GENERAL                             = 0x0,
-+	ARRAY_LINEAR_ALIGNED                             = 0x1,
-+	ARRAY_1D_TILED_THIN1                             = 0x2,
-+	ARRAY_1D_TILED_THICK                             = 0x3,
-+	ARRAY_2D_TILED_THIN1                             = 0x4,
-+	ARRAY_PRT_TILED_THIN1                            = 0x5,
-+	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
-+	ARRAY_2D_TILED_THICK                             = 0x7,
-+	ARRAY_2D_TILED_XTHICK                            = 0x8,
-+	ARRAY_PRT_TILED_THICK                            = 0x9,
-+	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
-+	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
-+	ARRAY_3D_TILED_THIN1                             = 0xc,
-+	ARRAY_3D_TILED_THICK                             = 0xd,
-+	ARRAY_3D_TILED_XTHICK                            = 0xe,
-+	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
-+} ArrayMode;
-+typedef enum PipeTiling {
-+	CONFIG_1_PIPE                                    = 0x0,
-+	CONFIG_2_PIPE                                    = 0x1,
-+	CONFIG_4_PIPE                                    = 0x2,
-+	CONFIG_8_PIPE                                    = 0x3,
-+} PipeTiling;
-+typedef enum BankTiling {
-+	CONFIG_4_BANK                                    = 0x0,
-+	CONFIG_8_BANK                                    = 0x1,
-+} BankTiling;
-+typedef enum GroupInterleave {
-+	CONFIG_256B_GROUP                                = 0x0,
-+	CONFIG_512B_GROUP                                = 0x1,
-+} GroupInterleave;
-+typedef enum RowTiling {
-+	CONFIG_1KB_ROW                                   = 0x0,
-+	CONFIG_2KB_ROW                                   = 0x1,
-+	CONFIG_4KB_ROW                                   = 0x2,
-+	CONFIG_8KB_ROW                                   = 0x3,
-+	CONFIG_1KB_ROW_OPT                               = 0x4,
-+	CONFIG_2KB_ROW_OPT                               = 0x5,
-+	CONFIG_4KB_ROW_OPT                               = 0x6,
-+	CONFIG_8KB_ROW_OPT                               = 0x7,
-+} RowTiling;
-+typedef enum BankSwapBytes {
-+	CONFIG_128B_SWAPS                                = 0x0,
-+	CONFIG_256B_SWAPS                                = 0x1,
-+	CONFIG_512B_SWAPS                                = 0x2,
-+	CONFIG_1KB_SWAPS                                 = 0x3,
-+} BankSwapBytes;
-+typedef enum SampleSplitBytes {
-+	CONFIG_1KB_SPLIT                                 = 0x0,
-+	CONFIG_2KB_SPLIT                                 = 0x1,
-+	CONFIG_4KB_SPLIT                                 = 0x2,
-+	CONFIG_8KB_SPLIT                                 = 0x3,
-+} SampleSplitBytes;
-+typedef enum NumPipes {
-+	ADDR_CONFIG_1_PIPE                               = 0x0,
-+	ADDR_CONFIG_2_PIPE                               = 0x1,
-+	ADDR_CONFIG_4_PIPE                               = 0x2,
-+	ADDR_CONFIG_8_PIPE                               = 0x3,
-+} NumPipes;
-+typedef enum PipeInterleaveSize {
-+	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
-+	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
-+} PipeInterleaveSize;
-+typedef enum BankInterleaveSize {
-+	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
-+	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
-+	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
-+	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
-+} BankInterleaveSize;
-+typedef enum NumShaderEngines {
-+	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
-+	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
-+} NumShaderEngines;
-+typedef enum ShaderEngineTileSize {
-+	ADDR_CONFIG_SE_TILE_16                           = 0x0,
-+	ADDR_CONFIG_SE_TILE_32                           = 0x1,
-+} ShaderEngineTileSize;
-+typedef enum NumGPUs {
-+	ADDR_CONFIG_1_GPU                                = 0x0,
-+	ADDR_CONFIG_2_GPU                                = 0x1,
-+	ADDR_CONFIG_4_GPU                                = 0x2,
-+} NumGPUs;
-+typedef enum MultiGPUTileSize {
-+	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
-+	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
-+	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
-+	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
-+} MultiGPUTileSize;
-+typedef enum RowSize {
-+	ADDR_CONFIG_1KB_ROW                              = 0x0,
-+	ADDR_CONFIG_2KB_ROW                              = 0x1,
-+	ADDR_CONFIG_4KB_ROW                              = 0x2,
-+} RowSize;
-+typedef enum NumLowerPipes {
-+	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
-+	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
-+} NumLowerPipes;
-+typedef enum DebugBlockId {
-+	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
-+	DBG_CLIENT_BLKID_dbg                             = 0x1,
-+	DBG_CLIENT_BLKID_uvdu_0                          = 0x2,
-+	DBG_CLIENT_BLKID_uvdu_1                          = 0x3,
-+	DBG_CLIENT_BLKID_uvdu_2                          = 0x4,
-+	DBG_CLIENT_BLKID_uvdu_3                          = 0x5,
-+	DBG_CLIENT_BLKID_uvdu_4                          = 0x6,
-+	DBG_CLIENT_BLKID_uvdu_5                          = 0x7,
-+	DBG_CLIENT_BLKID_uvdu_6                          = 0x8,
-+	DBG_CLIENT_BLKID_uvdm_0                          = 0x9,
-+	DBG_CLIENT_BLKID_uvdm_1                          = 0xa,
-+	DBG_CLIENT_BLKID_uvdm_2                          = 0xb,
-+	DBG_CLIENT_BLKID_uvdm_3                          = 0xc,
-+	DBG_CLIENT_BLKID_vcea_0                          = 0xd,
-+	DBG_CLIENT_BLKID_vcea_1                          = 0xe,
-+	DBG_CLIENT_BLKID_vcea_2                          = 0xf,
-+	DBG_CLIENT_BLKID_vcea_3                          = 0x10,
-+	DBG_CLIENT_BLKID_vcea_4                          = 0x11,
-+	DBG_CLIENT_BLKID_vcea_5                          = 0x12,
-+	DBG_CLIENT_BLKID_vcea_6                          = 0x13,
-+	DBG_CLIENT_BLKID_vceb_0                          = 0x14,
-+	DBG_CLIENT_BLKID_vceb_1                          = 0x15,
-+	DBG_CLIENT_BLKID_vceb_2                          = 0x16,
-+	DBG_CLIENT_BLKID_dco                             = 0x17,
-+	DBG_CLIENT_BLKID_xdma                            = 0x18,
-+	DBG_CLIENT_BLKID_smu_0                           = 0x19,
-+	DBG_CLIENT_BLKID_smu_1                           = 0x1a,
-+	DBG_CLIENT_BLKID_smu_2                           = 0x1b,
-+	DBG_CLIENT_BLKID_gck                             = 0x1c,
-+	DBG_CLIENT_BLKID_tmonw0                          = 0x1d,
-+	DBG_CLIENT_BLKID_tmonw1                          = 0x1e,
-+	DBG_CLIENT_BLKID_grbm                            = 0x1f,
-+	DBG_CLIENT_BLKID_rlc                             = 0x20,
-+	DBG_CLIENT_BLKID_ds0                             = 0x21,
-+	DBG_CLIENT_BLKID_cpg_0                           = 0x22,
-+	DBG_CLIENT_BLKID_cpg_1                           = 0x23,
-+	DBG_CLIENT_BLKID_cpc_0                           = 0x24,
-+	DBG_CLIENT_BLKID_cpc_1                           = 0x25,
-+	DBG_CLIENT_BLKID_cpf                             = 0x26,
-+	DBG_CLIENT_BLKID_scf0                            = 0x27,
-+	DBG_CLIENT_BLKID_scf1                            = 0x28,
-+	DBG_CLIENT_BLKID_scf2                            = 0x29,
-+	DBG_CLIENT_BLKID_scf3                            = 0x2a,
-+	DBG_CLIENT_BLKID_pc0                             = 0x2b,
-+	DBG_CLIENT_BLKID_pc1                             = 0x2c,
-+	DBG_CLIENT_BLKID_pc2                             = 0x2d,
-+	DBG_CLIENT_BLKID_pc3                             = 0x2e,
-+	DBG_CLIENT_BLKID_vgt0                            = 0x2f,
-+	DBG_CLIENT_BLKID_vgt1                            = 0x30,
-+	DBG_CLIENT_BLKID_vgt2                            = 0x31,
-+	DBG_CLIENT_BLKID_vgt3                            = 0x32,
-+	DBG_CLIENT_BLKID_sx00                            = 0x33,
-+	DBG_CLIENT_BLKID_sx10                            = 0x34,
-+	DBG_CLIENT_BLKID_sx20                            = 0x35,
-+	DBG_CLIENT_BLKID_sx30                            = 0x36,
-+	DBG_CLIENT_BLKID_cb001                           = 0x37,
-+	DBG_CLIENT_BLKID_cb200                           = 0x38,
-+	DBG_CLIENT_BLKID_cb201                           = 0x39,
-+	DBG_CLIENT_BLKID_cbr0                            = 0x3a,
-+	DBG_CLIENT_BLKID_cb000                           = 0x3b,
-+	DBG_CLIENT_BLKID_cb101                           = 0x3c,
-+	DBG_CLIENT_BLKID_cb300                           = 0x3d,
-+	DBG_CLIENT_BLKID_cb301                           = 0x3e,
-+	DBG_CLIENT_BLKID_cbr1                            = 0x3f,
-+	DBG_CLIENT_BLKID_cb100                           = 0x40,
-+	DBG_CLIENT_BLKID_ia0                             = 0x41,
-+	DBG_CLIENT_BLKID_ia1                             = 0x42,
-+	DBG_CLIENT_BLKID_bci0                            = 0x43,
-+	DBG_CLIENT_BLKID_bci1                            = 0x44,
-+	DBG_CLIENT_BLKID_bci2                            = 0x45,
-+	DBG_CLIENT_BLKID_bci3                            = 0x46,
-+	DBG_CLIENT_BLKID_pa0                             = 0x47,
-+	DBG_CLIENT_BLKID_pa1                             = 0x48,
-+	DBG_CLIENT_BLKID_spim0                           = 0x49,
-+	DBG_CLIENT_BLKID_spim1                           = 0x4a,
-+	DBG_CLIENT_BLKID_spim2                           = 0x4b,
-+	DBG_CLIENT_BLKID_spim3                           = 0x4c,
-+	DBG_CLIENT_BLKID_sdma                            = 0x4d,
-+	DBG_CLIENT_BLKID_ih                              = 0x4e,
-+	DBG_CLIENT_BLKID_sem                             = 0x4f,
-+	DBG_CLIENT_BLKID_srbm                            = 0x50,
-+	DBG_CLIENT_BLKID_hdp                             = 0x51,
-+	DBG_CLIENT_BLKID_acp_0                           = 0x52,
-+	DBG_CLIENT_BLKID_acp_1                           = 0x53,
-+	DBG_CLIENT_BLKID_sam                             = 0x54,
-+	DBG_CLIENT_BLKID_mcc0                            = 0x55,
-+	DBG_CLIENT_BLKID_mcc1                            = 0x56,
-+	DBG_CLIENT_BLKID_mcc2                            = 0x57,
-+	DBG_CLIENT_BLKID_mcc3                            = 0x58,
-+	DBG_CLIENT_BLKID_mcd0                            = 0x59,
-+	DBG_CLIENT_BLKID_mcd1                            = 0x5a,
-+	DBG_CLIENT_BLKID_mcd2                            = 0x5b,
-+	DBG_CLIENT_BLKID_mcd3                            = 0x5c,
-+	DBG_CLIENT_BLKID_mcb                             = 0x5d,
-+	DBG_CLIENT_BLKID_vmc                             = 0x5e,
-+	DBG_CLIENT_BLKID_gmcon                           = 0x5f,
-+	DBG_CLIENT_BLKID_gdc_0                           = 0x60,
-+	DBG_CLIENT_BLKID_gdc_1                           = 0x61,
-+	DBG_CLIENT_BLKID_gdc_2                           = 0x62,
-+	DBG_CLIENT_BLKID_gdc_3                           = 0x63,
-+	DBG_CLIENT_BLKID_gdc_4                           = 0x64,
-+	DBG_CLIENT_BLKID_gdc_5                           = 0x65,
-+	DBG_CLIENT_BLKID_gdc_6                           = 0x66,
-+	DBG_CLIENT_BLKID_gdc_7                           = 0x67,
-+	DBG_CLIENT_BLKID_gdc_8                           = 0x68,
-+	DBG_CLIENT_BLKID_gdc_9                           = 0x69,
-+	DBG_CLIENT_BLKID_gdc_10                          = 0x6a,
-+	DBG_CLIENT_BLKID_gdc_11                          = 0x6b,
-+	DBG_CLIENT_BLKID_gdc_12                          = 0x6c,
-+	DBG_CLIENT_BLKID_gdc_13                          = 0x6d,
-+	DBG_CLIENT_BLKID_gdc_14                          = 0x6e,
-+	DBG_CLIENT_BLKID_gdc_15                          = 0x6f,
-+	DBG_CLIENT_BLKID_gdc_16                          = 0x70,
-+	DBG_CLIENT_BLKID_gdc_17                          = 0x71,
-+	DBG_CLIENT_BLKID_gdc_18                          = 0x72,
-+	DBG_CLIENT_BLKID_gdc_19                          = 0x73,
-+	DBG_CLIENT_BLKID_gdc_20                          = 0x74,
-+	DBG_CLIENT_BLKID_gdc_21                          = 0x75,
-+	DBG_CLIENT_BLKID_gdc_22                          = 0x76,
-+	DBG_CLIENT_BLKID_wd                              = 0x77,
-+	DBG_CLIENT_BLKID_sdma_0                          = 0x78,
-+	DBG_CLIENT_BLKID_sdma_1                          = 0x79,
-+} DebugBlockId;
-+typedef enum DebugBlockId_OLD {
-+	DBG_BLOCK_ID_RESERVED                            = 0x0,
-+	DBG_BLOCK_ID_DBG                                 = 0x1,
-+	DBG_BLOCK_ID_VMC                                 = 0x2,
-+	DBG_BLOCK_ID_PDMA                                = 0x3,
-+	DBG_BLOCK_ID_CG                                  = 0x4,
-+	DBG_BLOCK_ID_SRBM                                = 0x5,
-+	DBG_BLOCK_ID_GRBM                                = 0x6,
-+	DBG_BLOCK_ID_RLC                                 = 0x7,
-+	DBG_BLOCK_ID_CSC                                 = 0x8,
-+	DBG_BLOCK_ID_SEM                                 = 0x9,
-+	DBG_BLOCK_ID_IH                                  = 0xa,
-+	DBG_BLOCK_ID_SC                                  = 0xb,
-+	DBG_BLOCK_ID_SQ                                  = 0xc,
-+	DBG_BLOCK_ID_AVP                                 = 0xd,
-+	DBG_BLOCK_ID_GMCON                               = 0xe,
-+	DBG_BLOCK_ID_SMU                                 = 0xf,
-+	DBG_BLOCK_ID_DMA0                                = 0x10,
-+	DBG_BLOCK_ID_DMA1                                = 0x11,
-+	DBG_BLOCK_ID_SPIM                                = 0x12,
-+	DBG_BLOCK_ID_GDS                                 = 0x13,
-+	DBG_BLOCK_ID_SPIS                                = 0x14,
-+	DBG_BLOCK_ID_UNUSED0                             = 0x15,
-+	DBG_BLOCK_ID_PA0                                 = 0x16,
-+	DBG_BLOCK_ID_PA1                                 = 0x17,
-+	DBG_BLOCK_ID_CP0                                 = 0x18,
-+	DBG_BLOCK_ID_CP1                                 = 0x19,
-+	DBG_BLOCK_ID_CP2                                 = 0x1a,
-+	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
-+	DBG_BLOCK_ID_UVDU                                = 0x1c,
-+	DBG_BLOCK_ID_UVDM                                = 0x1d,
-+	DBG_BLOCK_ID_VCE                                 = 0x1e,
-+	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
-+	DBG_BLOCK_ID_VGT0                                = 0x20,
-+	DBG_BLOCK_ID_VGT1                                = 0x21,
-+	DBG_BLOCK_ID_IA                                  = 0x22,
-+	DBG_BLOCK_ID_UNUSED3                             = 0x23,
-+	DBG_BLOCK_ID_SCT0                                = 0x24,
-+	DBG_BLOCK_ID_SCT1                                = 0x25,
-+	DBG_BLOCK_ID_SPM0                                = 0x26,
-+	DBG_BLOCK_ID_SPM1                                = 0x27,
-+	DBG_BLOCK_ID_TCAA                                = 0x28,
-+	DBG_BLOCK_ID_TCAB                                = 0x29,
-+	DBG_BLOCK_ID_TCCA                                = 0x2a,
-+	DBG_BLOCK_ID_TCCB                                = 0x2b,
-+	DBG_BLOCK_ID_MCC0                                = 0x2c,
-+	DBG_BLOCK_ID_MCC1                                = 0x2d,
-+	DBG_BLOCK_ID_MCC2                                = 0x2e,
-+	DBG_BLOCK_ID_MCC3                                = 0x2f,
-+	DBG_BLOCK_ID_SX0                                 = 0x30,
-+	DBG_BLOCK_ID_SX1                                 = 0x31,
-+	DBG_BLOCK_ID_SX2                                 = 0x32,
-+	DBG_BLOCK_ID_SX3                                 = 0x33,
-+	DBG_BLOCK_ID_UNUSED4                             = 0x34,
-+	DBG_BLOCK_ID_UNUSED5                             = 0x35,
-+	DBG_BLOCK_ID_UNUSED6                             = 0x36,
-+	DBG_BLOCK_ID_UNUSED7                             = 0x37,
-+	DBG_BLOCK_ID_PC0                                 = 0x38,
-+	DBG_BLOCK_ID_PC1                                 = 0x39,
-+	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
-+	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
-+	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
-+	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
-+	DBG_BLOCK_ID_MCB                                 = 0x3e,
-+	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
-+	DBG_BLOCK_ID_SCB0                                = 0x40,
-+	DBG_BLOCK_ID_SCB1                                = 0x41,
-+	DBG_BLOCK_ID_UNUSED13                            = 0x42,
-+	DBG_BLOCK_ID_UNUSED14                            = 0x43,
-+	DBG_BLOCK_ID_SCF0                                = 0x44,
-+	DBG_BLOCK_ID_SCF1                                = 0x45,
-+	DBG_BLOCK_ID_UNUSED15                            = 0x46,
-+	DBG_BLOCK_ID_UNUSED16                            = 0x47,
-+	DBG_BLOCK_ID_BCI0                                = 0x48,
-+	DBG_BLOCK_ID_BCI1                                = 0x49,
-+	DBG_BLOCK_ID_BCI2                                = 0x4a,
-+	DBG_BLOCK_ID_BCI3                                = 0x4b,
-+	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
-+	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
-+	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
-+	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
-+	DBG_BLOCK_ID_CB00                                = 0x50,
-+	DBG_BLOCK_ID_CB01                                = 0x51,
-+	DBG_BLOCK_ID_CB02                                = 0x52,
-+	DBG_BLOCK_ID_CB03                                = 0x53,
-+	DBG_BLOCK_ID_CB04                                = 0x54,
-+	DBG_BLOCK_ID_UNUSED21                            = 0x55,
-+	DBG_BLOCK_ID_UNUSED22                            = 0x56,
-+	DBG_BLOCK_ID_UNUSED23                            = 0x57,
-+	DBG_BLOCK_ID_CB10                                = 0x58,
-+	DBG_BLOCK_ID_CB11                                = 0x59,
-+	DBG_BLOCK_ID_CB12                                = 0x5a,
-+	DBG_BLOCK_ID_CB13                                = 0x5b,
-+	DBG_BLOCK_ID_CB14                                = 0x5c,
-+	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
-+	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
-+	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
-+	DBG_BLOCK_ID_TCP0                                = 0x60,
-+	DBG_BLOCK_ID_TCP1                                = 0x61,
-+	DBG_BLOCK_ID_TCP2                                = 0x62,
-+	DBG_BLOCK_ID_TCP3                                = 0x63,
-+	DBG_BLOCK_ID_TCP4                                = 0x64,
-+	DBG_BLOCK_ID_TCP5                                = 0x65,
-+	DBG_BLOCK_ID_TCP6                                = 0x66,
-+	DBG_BLOCK_ID_TCP7                                = 0x67,
-+	DBG_BLOCK_ID_TCP8                                = 0x68,
-+	DBG_BLOCK_ID_TCP9                                = 0x69,
-+	DBG_BLOCK_ID_TCP10                               = 0x6a,
-+	DBG_BLOCK_ID_TCP11                               = 0x6b,
-+	DBG_BLOCK_ID_TCP12                               = 0x6c,
-+	DBG_BLOCK_ID_TCP13                               = 0x6d,
-+	DBG_BLOCK_ID_TCP14                               = 0x6e,
-+	DBG_BLOCK_ID_TCP15                               = 0x6f,
-+	DBG_BLOCK_ID_TCP16                               = 0x70,
-+	DBG_BLOCK_ID_TCP17                               = 0x71,
-+	DBG_BLOCK_ID_TCP18                               = 0x72,
-+	DBG_BLOCK_ID_TCP19                               = 0x73,
-+	DBG_BLOCK_ID_TCP20                               = 0x74,
-+	DBG_BLOCK_ID_TCP21                               = 0x75,
-+	DBG_BLOCK_ID_TCP22                               = 0x76,
-+	DBG_BLOCK_ID_TCP23                               = 0x77,
-+	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
-+	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
-+	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
-+	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
-+	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
-+	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
-+	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
-+	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
-+	DBG_BLOCK_ID_DB00                                = 0x80,
-+	DBG_BLOCK_ID_DB01                                = 0x81,
-+	DBG_BLOCK_ID_DB02                                = 0x82,
-+	DBG_BLOCK_ID_DB03                                = 0x83,
-+	DBG_BLOCK_ID_DB04                                = 0x84,
-+	DBG_BLOCK_ID_UNUSED27                            = 0x85,
-+	DBG_BLOCK_ID_UNUSED28                            = 0x86,
-+	DBG_BLOCK_ID_UNUSED29                            = 0x87,
-+	DBG_BLOCK_ID_DB10                                = 0x88,
-+	DBG_BLOCK_ID_DB11                                = 0x89,
-+	DBG_BLOCK_ID_DB12                                = 0x8a,
-+	DBG_BLOCK_ID_DB13                                = 0x8b,
-+	DBG_BLOCK_ID_DB14                                = 0x8c,
-+	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
-+	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
-+	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
-+	DBG_BLOCK_ID_TCC0                                = 0x90,
-+	DBG_BLOCK_ID_TCC1                                = 0x91,
-+	DBG_BLOCK_ID_TCC2                                = 0x92,
-+	DBG_BLOCK_ID_TCC3                                = 0x93,
-+	DBG_BLOCK_ID_TCC4                                = 0x94,
-+	DBG_BLOCK_ID_TCC5                                = 0x95,
-+	DBG_BLOCK_ID_TCC6                                = 0x96,
-+	DBG_BLOCK_ID_TCC7                                = 0x97,
-+	DBG_BLOCK_ID_SPS00                               = 0x98,
-+	DBG_BLOCK_ID_SPS01                               = 0x99,
-+	DBG_BLOCK_ID_SPS02                               = 0x9a,
-+	DBG_BLOCK_ID_SPS10                               = 0x9b,
-+	DBG_BLOCK_ID_SPS11                               = 0x9c,
-+	DBG_BLOCK_ID_SPS12                               = 0x9d,
-+	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
-+	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
-+	DBG_BLOCK_ID_TA00                                = 0xa0,
-+	DBG_BLOCK_ID_TA01                                = 0xa1,
-+	DBG_BLOCK_ID_TA02                                = 0xa2,
-+	DBG_BLOCK_ID_TA03                                = 0xa3,
-+	DBG_BLOCK_ID_TA04                                = 0xa4,
-+	DBG_BLOCK_ID_TA05                                = 0xa5,
-+	DBG_BLOCK_ID_TA06                                = 0xa6,
-+	DBG_BLOCK_ID_TA07                                = 0xa7,
-+	DBG_BLOCK_ID_TA08                                = 0xa8,
-+	DBG_BLOCK_ID_TA09                                = 0xa9,
-+	DBG_BLOCK_ID_TA0A                                = 0xaa,
-+	DBG_BLOCK_ID_TA0B                                = 0xab,
-+	DBG_BLOCK_ID_UNUSED35                            = 0xac,
-+	DBG_BLOCK_ID_UNUSED36                            = 0xad,
-+	DBG_BLOCK_ID_UNUSED37                            = 0xae,
-+	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
-+	DBG_BLOCK_ID_TA10                                = 0xb0,
-+	DBG_BLOCK_ID_TA11                                = 0xb1,
-+	DBG_BLOCK_ID_TA12                                = 0xb2,
-+	DBG_BLOCK_ID_TA13                                = 0xb3,
-+	DBG_BLOCK_ID_TA14                                = 0xb4,
-+	DBG_BLOCK_ID_TA15                                = 0xb5,
-+	DBG_BLOCK_ID_TA16                                = 0xb6,
-+	DBG_BLOCK_ID_TA17                                = 0xb7,
-+	DBG_BLOCK_ID_TA18                                = 0xb8,
-+	DBG_BLOCK_ID_TA19                                = 0xb9,
-+	DBG_BLOCK_ID_TA1A                                = 0xba,
-+	DBG_BLOCK_ID_TA1B                                = 0xbb,
-+	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
-+	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
-+	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
-+	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
-+	DBG_BLOCK_ID_TD00                                = 0xc0,
-+	DBG_BLOCK_ID_TD01                                = 0xc1,
-+	DBG_BLOCK_ID_TD02                                = 0xc2,
-+	DBG_BLOCK_ID_TD03                                = 0xc3,
-+	DBG_BLOCK_ID_TD04                                = 0xc4,
-+	DBG_BLOCK_ID_TD05                                = 0xc5,
-+	DBG_BLOCK_ID_TD06                                = 0xc6,
-+	DBG_BLOCK_ID_TD07                                = 0xc7,
-+	DBG_BLOCK_ID_TD08                                = 0xc8,
-+	DBG_BLOCK_ID_TD09                                = 0xc9,
-+	DBG_BLOCK_ID_TD0A                                = 0xca,
-+	DBG_BLOCK_ID_TD0B                                = 0xcb,
-+	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
-+	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
-+	DBG_BLOCK_ID_UNUSED45                            = 0xce,
-+	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
-+	DBG_BLOCK_ID_TD10                                = 0xd0,
-+	DBG_BLOCK_ID_TD11                                = 0xd1,
-+	DBG_BLOCK_ID_TD12                                = 0xd2,
-+	DBG_BLOCK_ID_TD13                                = 0xd3,
-+	DBG_BLOCK_ID_TD14                                = 0xd4,
-+	DBG_BLOCK_ID_TD15                                = 0xd5,
-+	DBG_BLOCK_ID_TD16                                = 0xd6,
-+	DBG_BLOCK_ID_TD17                                = 0xd7,
-+	DBG_BLOCK_ID_TD18                                = 0xd8,
-+	DBG_BLOCK_ID_TD19                                = 0xd9,
-+	DBG_BLOCK_ID_TD1A                                = 0xda,
-+	DBG_BLOCK_ID_TD1B                                = 0xdb,
-+	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
-+	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
-+	DBG_BLOCK_ID_UNUSED49                            = 0xde,
-+	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
-+	DBG_BLOCK_ID_MCD0                                = 0xe0,
-+	DBG_BLOCK_ID_MCD1                                = 0xe1,
-+	DBG_BLOCK_ID_MCD2                                = 0xe2,
-+	DBG_BLOCK_ID_MCD3                                = 0xe3,
-+	DBG_BLOCK_ID_MCD4                                = 0xe4,
-+	DBG_BLOCK_ID_MCD5                                = 0xe5,
-+	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
-+	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
-+} DebugBlockId_OLD;
-+typedef enum DebugBlockId_BY2 {
-+	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
-+	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
-+	DBG_BLOCK_ID_CG_BY2                              = 0x2,
-+	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
-+	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
-+	DBG_BLOCK_ID_IH_BY2                              = 0x5,
-+	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
-+	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
-+	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
-+	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
-+	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
-+	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
-+	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
-+	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
-+	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
-+	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
-+	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
-+	DBG_BLOCK_ID_IA_BY2                              = 0x11,
-+	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
-+	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
-+	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
-+	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
-+	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
-+	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
-+	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
-+	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
-+	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
-+	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
-+	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
-+	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
-+	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
-+	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
-+	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
-+	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
-+	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
-+	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
-+	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
-+	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
-+	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
-+	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
-+	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
-+	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
-+	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
-+	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
-+	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
-+	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
-+	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
-+	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
-+	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
-+	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
-+	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
-+	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
-+	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
-+	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
-+	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
-+	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
-+	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
-+	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
-+	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
-+	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
-+	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
-+	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
-+	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
-+	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
-+	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
-+	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
-+	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
-+	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
-+	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
-+	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
-+	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
-+	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
-+	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
-+	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
-+	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
-+	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
-+	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
-+	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
-+	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
-+	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
-+	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
-+	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
-+	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
-+	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
-+	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
-+	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
-+	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
-+	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
-+	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
-+	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
-+	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
-+	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
-+	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
-+	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
-+	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
-+	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
-+	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
-+	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
-+	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
-+	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
-+	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
-+	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
-+	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
-+	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
-+	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
-+	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
-+	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
-+	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
-+	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
-+	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
-+	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
-+	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
-+	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
-+	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
-+	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
-+	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
-+} DebugBlockId_BY2;
-+typedef enum DebugBlockId_BY4 {
-+	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
-+	DBG_BLOCK_ID_CG_BY4                              = 0x1,
-+	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
-+	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
-+	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
-+	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
-+	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
-+	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
-+	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
-+	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
-+	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
-+	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
-+	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
-+	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
-+	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
-+	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
-+	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
-+	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
-+	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
-+	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
-+	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
-+	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
-+	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
-+	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
-+	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
-+	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
-+	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
-+	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
-+	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
-+	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
-+	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
-+	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
-+	DBG_BLOCK_ID_DB_BY4                              = 0x20,
-+	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
-+	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
-+	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
-+	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
-+	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
-+	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
-+	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
-+	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
-+	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
-+	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
-+	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
-+	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
-+	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
-+	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
-+	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
-+	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
-+	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
-+	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
-+	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
-+	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
-+	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
-+	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
-+	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
-+	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
-+	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
-+} DebugBlockId_BY4;
-+typedef enum DebugBlockId_BY8 {
-+	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
-+	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
-+	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
-+	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
-+	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
-+	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
-+	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
-+	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
-+	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
-+	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
-+	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
-+	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
-+	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
-+	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
-+	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
-+	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
-+	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
-+	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
-+	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
-+	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
-+	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
-+	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
-+	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
-+	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
-+	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
-+	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
-+	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
-+	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
-+	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
-+} DebugBlockId_BY8;
-+typedef enum DebugBlockId_BY16 {
-+	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
-+	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
-+	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
-+	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
-+	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
-+	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
-+	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
-+	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
-+	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
-+	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
-+	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
-+	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
-+	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
-+	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
-+	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
-+} DebugBlockId_BY16;
-+typedef enum CompareRef {
-+	REF_NEVER                                        = 0x0,
-+	REF_LESS                                         = 0x1,
-+	REF_EQUAL                                        = 0x2,
-+	REF_LEQUAL                                       = 0x3,
-+	REF_GREATER                                      = 0x4,
-+	REF_NOTEQUAL                                     = 0x5,
-+	REF_GEQUAL                                       = 0x6,
-+	REF_ALWAYS                                       = 0x7,
-+} CompareRef;
-+typedef enum ReadSize {
-+	READ_256_BITS                                    = 0x0,
-+	READ_512_BITS                                    = 0x1,
-+} ReadSize;
-+typedef enum DepthFormat {
-+	DEPTH_INVALID                                    = 0x0,
-+	DEPTH_16                                         = 0x1,
-+	DEPTH_X8_24                                      = 0x2,
-+	DEPTH_8_24                                       = 0x3,
-+	DEPTH_X8_24_FLOAT                                = 0x4,
-+	DEPTH_8_24_FLOAT                                 = 0x5,
-+	DEPTH_32_FLOAT                                   = 0x6,
-+	DEPTH_X24_8_32_FLOAT                             = 0x7,
-+} DepthFormat;
-+typedef enum ZFormat {
-+	Z_INVALID                                        = 0x0,
-+	Z_16                                             = 0x1,
-+	Z_24                                             = 0x2,
-+	Z_32_FLOAT                                       = 0x3,
-+} ZFormat;
-+typedef enum StencilFormat {
-+	STENCIL_INVALID                                  = 0x0,
-+	STENCIL_8                                        = 0x1,
-+} StencilFormat;
-+typedef enum CmaskMode {
-+	CMASK_CLEAR_NONE                                 = 0x0,
-+	CMASK_CLEAR_ONE                                  = 0x1,
-+	CMASK_CLEAR_ALL                                  = 0x2,
-+	CMASK_ANY_EXPANDED                               = 0x3,
-+	CMASK_ALPHA0_FRAG1                               = 0x4,
-+	CMASK_ALPHA0_FRAG2                               = 0x5,
-+	CMASK_ALPHA0_FRAG4                               = 0x6,
-+	CMASK_ALPHA0_FRAGS                               = 0x7,
-+	CMASK_ALPHA1_FRAG1                               = 0x8,
-+	CMASK_ALPHA1_FRAG2                               = 0x9,
-+	CMASK_ALPHA1_FRAG4                               = 0xa,
-+	CMASK_ALPHA1_FRAGS                               = 0xb,
-+	CMASK_ALPHAX_FRAG1                               = 0xc,
-+	CMASK_ALPHAX_FRAG2                               = 0xd,
-+	CMASK_ALPHAX_FRAG4                               = 0xe,
-+	CMASK_ALPHAX_FRAGS                               = 0xf,
-+} CmaskMode;
-+typedef enum QuadExportFormat {
-+	EXPORT_UNUSED                                    = 0x0,
-+	EXPORT_32_R                                      = 0x1,
-+	EXPORT_32_GR                                     = 0x2,
-+	EXPORT_32_AR                                     = 0x3,
-+	EXPORT_FP16_ABGR                                 = 0x4,
-+	EXPORT_UNSIGNED16_ABGR                           = 0x5,
-+	EXPORT_SIGNED16_ABGR                             = 0x6,
-+	EXPORT_32_ABGR                                   = 0x7,
-+} QuadExportFormat;
-+typedef enum QuadExportFormatOld {
-+	EXPORT_4P_32BPC_ABGR                             = 0x0,
-+	EXPORT_4P_16BPC_ABGR                             = 0x1,
-+	EXPORT_4P_32BPC_GR                               = 0x2,
-+	EXPORT_4P_32BPC_AR                               = 0x3,
-+	EXPORT_2P_32BPC_ABGR                             = 0x4,
-+	EXPORT_8P_32BPC_R                                = 0x5,
-+} QuadExportFormatOld;
-+typedef enum ColorFormat {
-+	COLOR_INVALID                                    = 0x0,
-+	COLOR_8                                          = 0x1,
-+	COLOR_16                                         = 0x2,
-+	COLOR_8_8                                        = 0x3,
-+	COLOR_32                                         = 0x4,
-+	COLOR_16_16                                      = 0x5,
-+	COLOR_10_11_11                                   = 0x6,
-+	COLOR_11_11_10                                   = 0x7,
-+	COLOR_10_10_10_2                                 = 0x8,
-+	COLOR_2_10_10_10                                 = 0x9,
-+	COLOR_8_8_8_8                                    = 0xa,
-+	COLOR_32_32                                      = 0xb,
-+	COLOR_16_16_16_16                                = 0xc,
-+	COLOR_RESERVED_13                                = 0xd,
-+	COLOR_32_32_32_32                                = 0xe,
-+	COLOR_RESERVED_15                                = 0xf,
-+	COLOR_5_6_5                                      = 0x10,
-+	COLOR_1_5_5_5                                    = 0x11,
-+	COLOR_5_5_5_1                                    = 0x12,
-+	COLOR_4_4_4_4                                    = 0x13,
-+	COLOR_8_24                                       = 0x14,
-+	COLOR_24_8                                       = 0x15,
-+	COLOR_X24_8_32_FLOAT                             = 0x16,
-+	COLOR_RESERVED_23                                = 0x17,
-+} ColorFormat;
-+typedef enum SurfaceFormat {
-+	FMT_INVALID                                      = 0x0,
-+	FMT_8                                            = 0x1,
-+	FMT_16                                           = 0x2,
-+	FMT_8_8                                          = 0x3,
-+	FMT_32                                           = 0x4,
-+	FMT_16_16                                        = 0x5,
-+	FMT_10_11_11                                     = 0x6,
-+	FMT_11_11_10                                     = 0x7,
-+	FMT_10_10_10_2                                   = 0x8,
-+	FMT_2_10_10_10                                   = 0x9,
-+	FMT_8_8_8_8                                      = 0xa,
-+	FMT_32_32                                        = 0xb,
-+	FMT_16_16_16_16                                  = 0xc,
-+	FMT_32_32_32                                     = 0xd,
-+	FMT_32_32_32_32                                  = 0xe,
-+	FMT_RESERVED_4                                   = 0xf,
-+	FMT_5_6_5                                        = 0x10,
-+	FMT_1_5_5_5                                      = 0x11,
-+	FMT_5_5_5_1                                      = 0x12,
-+	FMT_4_4_4_4                                      = 0x13,
-+	FMT_8_24                                         = 0x14,
-+	FMT_24_8                                         = 0x15,
-+	FMT_X24_8_32_FLOAT                               = 0x16,
-+	FMT_RESERVED_33                                  = 0x17,
-+	FMT_11_11_10_FLOAT                               = 0x18,
-+	FMT_16_FLOAT                                     = 0x19,
-+	FMT_32_FLOAT                                     = 0x1a,
-+	FMT_16_16_FLOAT                                  = 0x1b,
-+	FMT_8_24_FLOAT                                   = 0x1c,
-+	FMT_24_8_FLOAT                                   = 0x1d,
-+	FMT_32_32_FLOAT                                  = 0x1e,
-+	FMT_10_11_11_FLOAT                               = 0x1f,
-+	FMT_16_16_16_16_FLOAT                            = 0x20,
-+	FMT_3_3_2                                        = 0x21,
-+	FMT_6_5_5                                        = 0x22,
-+	FMT_32_32_32_32_FLOAT                            = 0x23,
-+	FMT_RESERVED_36                                  = 0x24,
-+	FMT_1                                            = 0x25,
-+	FMT_1_REVERSED                                   = 0x26,
-+	FMT_GB_GR                                        = 0x27,
-+	FMT_BG_RG                                        = 0x28,
-+	FMT_32_AS_8                                      = 0x29,
-+	FMT_32_AS_8_8                                    = 0x2a,
-+	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
-+	FMT_8_8_8                                        = 0x2c,
-+	FMT_16_16_16                                     = 0x2d,
-+	FMT_16_16_16_FLOAT                               = 0x2e,
-+	FMT_4_4                                          = 0x2f,
-+	FMT_32_32_32_FLOAT                               = 0x30,
-+	FMT_BC1                                          = 0x31,
-+	FMT_BC2                                          = 0x32,
-+	FMT_BC3                                          = 0x33,
-+	FMT_BC4                                          = 0x34,
-+	FMT_BC5                                          = 0x35,
-+	FMT_BC6                                          = 0x36,
-+	FMT_BC7                                          = 0x37,
-+	FMT_32_AS_32_32_32_32                            = 0x38,
-+	FMT_APC3                                         = 0x39,
-+	FMT_APC4                                         = 0x3a,
-+	FMT_APC5                                         = 0x3b,
-+	FMT_APC6                                         = 0x3c,
-+	FMT_APC7                                         = 0x3d,
-+	FMT_CTX1                                         = 0x3e,
-+	FMT_RESERVED_63                                  = 0x3f,
-+} SurfaceFormat;
-+typedef enum BUF_DATA_FORMAT {
-+	BUF_DATA_FORMAT_INVALID                          = 0x0,
-+	BUF_DATA_FORMAT_8                                = 0x1,
-+	BUF_DATA_FORMAT_16                               = 0x2,
-+	BUF_DATA_FORMAT_8_8                              = 0x3,
-+	BUF_DATA_FORMAT_32                               = 0x4,
-+	BUF_DATA_FORMAT_16_16                            = 0x5,
-+	BUF_DATA_FORMAT_10_11_11                         = 0x6,
-+	BUF_DATA_FORMAT_11_11_10                         = 0x7,
-+	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
-+	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
-+	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
-+	BUF_DATA_FORMAT_32_32                            = 0xb,
-+	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
-+	BUF_DATA_FORMAT_32_32_32                         = 0xd,
-+	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
-+	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
-+} BUF_DATA_FORMAT;
-+typedef enum IMG_DATA_FORMAT {
-+	IMG_DATA_FORMAT_INVALID                          = 0x0,
-+	IMG_DATA_FORMAT_8                                = 0x1,
-+	IMG_DATA_FORMAT_16                               = 0x2,
-+	IMG_DATA_FORMAT_8_8                              = 0x3,
-+	IMG_DATA_FORMAT_32                               = 0x4,
-+	IMG_DATA_FORMAT_16_16                            = 0x5,
-+	IMG_DATA_FORMAT_10_11_11                         = 0x6,
-+	IMG_DATA_FORMAT_11_11_10                         = 0x7,
-+	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
-+	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
-+	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
-+	IMG_DATA_FORMAT_32_32                            = 0xb,
-+	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
-+	IMG_DATA_FORMAT_32_32_32                         = 0xd,
-+	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
-+	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
-+	IMG_DATA_FORMAT_5_6_5                            = 0x10,
-+	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
-+	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
-+	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
-+	IMG_DATA_FORMAT_8_24                             = 0x14,
-+	IMG_DATA_FORMAT_24_8                             = 0x15,
-+	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
-+	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
-+	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
-+	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
-+	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
-+	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
-+	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
-+	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
-+	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
-+	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
-+	IMG_DATA_FORMAT_GB_GR                            = 0x20,
-+	IMG_DATA_FORMAT_BG_RG                            = 0x21,
-+	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
-+	IMG_DATA_FORMAT_BC1                              = 0x23,
-+	IMG_DATA_FORMAT_BC2                              = 0x24,
-+	IMG_DATA_FORMAT_BC3                              = 0x25,
-+	IMG_DATA_FORMAT_BC4                              = 0x26,
-+	IMG_DATA_FORMAT_BC5                              = 0x27,
-+	IMG_DATA_FORMAT_BC6                              = 0x28,
-+	IMG_DATA_FORMAT_BC7                              = 0x29,
-+	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
-+	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
-+	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
-+	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
-+	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
-+	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
-+	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
-+	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
-+	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
-+	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
-+	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
-+	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
-+	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
-+	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
-+	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
-+	IMG_DATA_FORMAT_4_4                              = 0x39,
-+	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
-+	IMG_DATA_FORMAT_1                                = 0x3b,
-+	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
-+	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
-+	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
-+	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
-+} IMG_DATA_FORMAT;
-+typedef enum BUF_NUM_FORMAT {
-+	BUF_NUM_FORMAT_UNORM                             = 0x0,
-+	BUF_NUM_FORMAT_SNORM                             = 0x1,
-+	BUF_NUM_FORMAT_USCALED                           = 0x2,
-+	BUF_NUM_FORMAT_SSCALED                           = 0x3,
-+	BUF_NUM_FORMAT_UINT                              = 0x4,
-+	BUF_NUM_FORMAT_SINT                              = 0x5,
-+	BUF_NUM_FORMAT_SNORM_OGL                         = 0x6,
-+	BUF_NUM_FORMAT_FLOAT                             = 0x7,
-+} BUF_NUM_FORMAT;
-+typedef enum IMG_NUM_FORMAT {
-+	IMG_NUM_FORMAT_UNORM                             = 0x0,
-+	IMG_NUM_FORMAT_SNORM                             = 0x1,
-+	IMG_NUM_FORMAT_USCALED                           = 0x2,
-+	IMG_NUM_FORMAT_SSCALED                           = 0x3,
-+	IMG_NUM_FORMAT_UINT                              = 0x4,
-+	IMG_NUM_FORMAT_SINT                              = 0x5,
-+	IMG_NUM_FORMAT_SNORM_OGL                         = 0x6,
-+	IMG_NUM_FORMAT_FLOAT                             = 0x7,
-+	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
-+	IMG_NUM_FORMAT_SRGB                              = 0x9,
-+	IMG_NUM_FORMAT_UBNORM                            = 0xa,
-+	IMG_NUM_FORMAT_UBNORM_OGL                        = 0xb,
-+	IMG_NUM_FORMAT_UBINT                             = 0xc,
-+	IMG_NUM_FORMAT_UBSCALED                          = 0xd,
-+	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
-+	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
-+} IMG_NUM_FORMAT;
-+typedef enum TileType {
-+	ARRAY_COLOR_TILE                                 = 0x0,
-+	ARRAY_DEPTH_TILE                                 = 0x1,
-+} TileType;
-+typedef enum NonDispTilingOrder {
-+	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
-+	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
-+} NonDispTilingOrder;
-+typedef enum MicroTileMode {
-+	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
-+	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
-+	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
-+	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
-+	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
-+} MicroTileMode;
-+typedef enum TileSplit {
-+	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
-+	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
-+	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
-+	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
-+	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
-+	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
-+	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
-+} TileSplit;
-+typedef enum SampleSplit {
-+	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
-+	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
-+	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
-+	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
-+} SampleSplit;
-+typedef enum PipeConfig {
-+	ADDR_SURF_P2                                     = 0x0,
-+	ADDR_SURF_P2_RESERVED0                           = 0x1,
-+	ADDR_SURF_P2_RESERVED1                           = 0x2,
-+	ADDR_SURF_P2_RESERVED2                           = 0x3,
-+	ADDR_SURF_P4_8x16                                = 0x4,
-+	ADDR_SURF_P4_16x16                               = 0x5,
-+	ADDR_SURF_P4_16x32                               = 0x6,
-+	ADDR_SURF_P4_32x32                               = 0x7,
-+	ADDR_SURF_P8_16x16_8x16                          = 0x8,
-+	ADDR_SURF_P8_16x32_8x16                          = 0x9,
-+	ADDR_SURF_P8_32x32_8x16                          = 0xa,
-+	ADDR_SURF_P8_16x32_16x16                         = 0xb,
-+	ADDR_SURF_P8_32x32_16x16                         = 0xc,
-+	ADDR_SURF_P8_32x32_16x32                         = 0xd,
-+	ADDR_SURF_P8_32x64_32x32                         = 0xe,
-+} PipeConfig;
-+typedef enum NumBanks {
-+	ADDR_SURF_2_BANK                                 = 0x0,
-+	ADDR_SURF_4_BANK                                 = 0x1,
-+	ADDR_SURF_8_BANK                                 = 0x2,
-+	ADDR_SURF_16_BANK                                = 0x3,
-+} NumBanks;
-+typedef enum BankWidth {
-+	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
-+	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
-+	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
-+	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
-+} BankWidth;
-+typedef enum BankHeight {
-+	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
-+	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
-+	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
-+	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
-+} BankHeight;
-+typedef enum BankWidthHeight {
-+	ADDR_SURF_BANK_WH_1                              = 0x0,
-+	ADDR_SURF_BANK_WH_2                              = 0x1,
-+	ADDR_SURF_BANK_WH_4                              = 0x2,
-+	ADDR_SURF_BANK_WH_8                              = 0x3,
-+} BankWidthHeight;
-+typedef enum MacroTileAspect {
-+	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
-+	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
-+	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
-+	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
-+} MacroTileAspect;
-+typedef enum TCC_CACHE_POLICIES {
-+	TCC_CACHE_POLICY_LRU                             = 0x0,
-+	TCC_CACHE_POLICY_STREAM                          = 0x1,
-+	TCC_CACHE_POLICY_BYPASS                          = 0x2,
-+} TCC_CACHE_POLICIES;
-+typedef enum PERFMON_COUNTER_MODE {
-+	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
-+	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
-+	PERFMON_COUNTER_MODE_MAX                         = 0x2,
-+	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
-+	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
-+	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
-+	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
-+	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
-+	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
-+	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
-+	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
-+} PERFMON_COUNTER_MODE;
-+typedef enum PERFMON_SPM_MODE {
-+	PERFMON_SPM_MODE_OFF                             = 0x0,
-+	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
-+	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
-+	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
-+	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
-+	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
-+	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
-+	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
-+	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
-+	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
-+	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
-+} PERFMON_SPM_MODE;
-+typedef enum SurfaceTiling {
-+	ARRAY_LINEAR                                     = 0x0,
-+	ARRAY_TILED                                      = 0x1,
-+} SurfaceTiling;
-+typedef enum SurfaceArray {
-+	ARRAY_1D                                         = 0x0,
-+	ARRAY_2D                                         = 0x1,
-+	ARRAY_3D                                         = 0x2,
-+	ARRAY_3D_SLICE                                   = 0x3,
-+} SurfaceArray;
-+typedef enum ColorArray {
-+	ARRAY_2D_ALT_COLOR                               = 0x0,
-+	ARRAY_2D_COLOR                                   = 0x1,
-+	ARRAY_3D_SLICE_COLOR                             = 0x3,
-+} ColorArray;
-+typedef enum DepthArray {
-+	ARRAY_2D_ALT_DEPTH                               = 0x0,
-+	ARRAY_2D_DEPTH                                   = 0x1,
-+} DepthArray;
-+
-+#endif /* DCE_8_0_ENUM_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0247-drm-amdgpu-drop-a-dummy-wakeup-scheduler.patch b/common/recipes-kernel/linux/files/0247-drm-amdgpu-drop-a-dummy-wakeup-scheduler.patch
deleted file mode 100644
index 3d0a0a59..00000000
--- a/common/recipes-kernel/linux/files/0247-drm-amdgpu-drop-a-dummy-wakeup-scheduler.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From e3340ebb98eae7e066b7eea99edf8c8f9713faa8 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Tue, 26 Jan 2016 14:59:57 +0800
-Subject: [PATCH 0247/1110] drm/amdgpu: drop a dummy wakeup scheduler
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-since the dependency job is also scheduled by the same
-scheduler with the job depended on it, no need to
-call wake up scheduler when the dep is scheduled.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 8b2becd..a5ff945 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -229,6 +229,14 @@ static void amd_sched_entity_wakeup(struct fence *f, struct fence_cb *cb)
- 	amd_sched_wakeup(entity->sched);
- }
- 
-+static void amd_sched_entity_clear_dep(struct fence *f, struct fence_cb *cb)
-+{
-+	struct amd_sched_entity *entity =
-+		container_of(cb, struct amd_sched_entity, cb);
-+	entity->dependency = NULL;
-+	fence_put(f);
-+}
-+
- static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
- {
- 	struct amd_gpu_scheduler *sched = entity->sched;
-@@ -251,7 +259,7 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
- 		}
- 
- 		/* Wait for fence to be scheduled */
--		entity->cb.func = amd_sched_entity_wakeup;
-+		entity->cb.func = amd_sched_entity_clear_dep;
- 		list_add_tail(&entity->cb.node, &s_fence->scheduled_cb);
- 		return true;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0248-drm-amdgpu-use-WARN_ON_ONCE-instead-of-BUG_ON-in-the.patch b/common/recipes-kernel/linux/files/0248-drm-amdgpu-use-WARN_ON_ONCE-instead-of-BUG_ON-in-the.patch
deleted file mode 100644
index 8b28977e..00000000
--- a/common/recipes-kernel/linux/files/0248-drm-amdgpu-use-WARN_ON_ONCE-instead-of-BUG_ON-in-the.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 364fe90c8a3964ec2d7bc9f61eca4f9780cc71ce Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 25 Jan 2016 13:01:42 +0100
-Subject: [PATCH 0248/1110] drm/amdgpu: use WARN_ON_ONCE instead of BUG_ON in
- the SA
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Crashing the system doesn't helps at all. Also properly return
--EINVAL if size or alignment are outside valid ranges.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
-index ca72a2e..2faf03b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
-@@ -321,8 +321,11 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
- 	int i, r;
- 	signed long t;
- 
--	BUG_ON(align > sa_manager->align);
--	BUG_ON(size > sa_manager->size);
-+	if (WARN_ON_ONCE(align > sa_manager->align))
-+		return -EINVAL;
-+
-+	if (WARN_ON_ONCE(size > sa_manager->size))
-+		return -EINVAL;
- 
- 	*sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
- 	if ((*sa_bo) == NULL) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0249-drm-amdgpu-remove-nonsense-IB-size-checks.patch b/common/recipes-kernel/linux/files/0249-drm-amdgpu-remove-nonsense-IB-size-checks.patch
deleted file mode 100644
index 7ff90e52..00000000
--- a/common/recipes-kernel/linux/files/0249-drm-amdgpu-remove-nonsense-IB-size-checks.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 26d0a0a1552aa345de6c65e39d1033cf1de4bc5b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 25 Jan 2016 17:06:09 +0100
-Subject: [PATCH 0249/1110] drm/amdgpu: remove nonsense IB size checks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Those are just leftovers from the time we wrote the VM
-updates directly to the ring.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 --------
- 1 file changed, 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 796fe49..9f3a8d9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -441,10 +441,6 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 	/* assume the worst case */
- 	ndw += vm->max_pde_used * 6;
- 
--	/* update too big for an IB */
--	if (ndw > 0xfffff)
--		return -ENOMEM;
--
- 	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
- 	if (!ib)
- 		return -ENOMEM;
-@@ -750,10 +746,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 		ndw += 2 * 10;
- 	}
- 
--	/* update too big for an IB */
--	if (ndw > 0xfffff)
--		return -ENOMEM;
--
- 	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
- 	if (!ib)
- 		return -ENOMEM;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0250-drm-amdgpu-move-more-logic-into-amdgpu_vm_map_gart-v.patch b/common/recipes-kernel/linux/files/0250-drm-amdgpu-move-more-logic-into-amdgpu_vm_map_gart-v.patch
deleted file mode 100644
index a1cb64cb..00000000
--- a/common/recipes-kernel/linux/files/0250-drm-amdgpu-move-more-logic-into-amdgpu_vm_map_gart-v.patch
+++ /dev/null
@@ -1,210 +0,0 @@
-From fb8c81fd95e4e90a3d5054b30d3cf2eaab12115e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 30 Nov 2015 13:26:07 +0100
-Subject: [PATCH 0250/1110] drm/amdgpu: move more logic into amdgpu_vm_map_gart
- v3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to duplicate that code over and over again. Also stop using the
-flags to determine if we need to map the addresses.
-
-v2: constify the pages_addr
-v3: rebased, fix typo in commit message
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 36 ++++++++++++++++++++++------------
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 11 ++---------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 11 ++---------
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 11 ++---------
- 5 files changed, 33 insertions(+), 42 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0e65ffe..e182c9f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -244,7 +244,7 @@ struct amdgpu_vm_pte_funcs {
- 			 unsigned count);
- 	/* write pte one entry at a time with addr mapping */
- 	void (*write_pte)(struct amdgpu_ib *ib,
--			  uint64_t pe,
-+			  const dma_addr_t *pages_addr, uint64_t pe,
- 			  uint64_t addr, unsigned count,
- 			  uint32_t incr, uint32_t flags);
- 	/* for linear pte/pde updates without addr mapping */
-@@ -930,7 +930,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 		     struct amdgpu_vm *vm,
- 		     struct fence *updates);
--uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
-+uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm);
- int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
-@@ -2164,7 +2164,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
- #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
- #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
--#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
-+#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
- #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
- #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
- #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 9f3a8d9..47e1186 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -306,9 +306,14 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
- 		uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
- 		amdgpu_vm_copy_pte(adev, ib, pe, src, count);
- 
--	} else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
--		amdgpu_vm_write_pte(adev, ib, pe, addr,
--				      count, incr, flags);
-+	} else if (flags & AMDGPU_PTE_SYSTEM) {
-+		dma_addr_t *pages_addr = adev->gart.pages_addr;
-+		amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
-+				    count, incr, flags);
-+
-+	} else if (count < 3) {
-+		amdgpu_vm_write_pte(adev, ib, NULL, pe, addr,
-+				    count, incr, flags);
- 
- 	} else {
- 		amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
-@@ -385,24 +390,31 @@ error:
- }
- 
- /**
-- * amdgpu_vm_map_gart - get the physical address of a gart page
-+ * amdgpu_vm_map_gart - Resolve gart mapping of addr
-  *
-- * @adev: amdgpu_device pointer
-+ * @pages_addr: optional DMA address to use for lookup
-  * @addr: the unmapped addr
-  *
-  * Look up the physical address of the page that the pte resolves
-- * to (cayman+).
-- * Returns the physical address of the page.
-+ * to and return the pointer for the page table entry.
-  */
--uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
-+uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
- {
- 	uint64_t result;
- 
--	/* page table offset */
--	result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
-+	if (pages_addr) {
-+		/* page table offset */
-+		result = pages_addr[addr >> PAGE_SHIFT];
-+
-+		/* in case cpu page size != gpu page size*/
-+		result |= addr & (~PAGE_MASK);
-+
-+	} else {
-+		/* No mapping required */
-+		result = addr;
-+	}
- 
--	/* in case cpu page size != gpu page size*/
--	result |= addr & (~PAGE_MASK);
-+	result &= 0xFFFFFFFFFFFFF000ULL;
- 
- 	return result;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index c70d7b1..0602279 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -714,7 +714,7 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
-  * Update PTEs by writing them manually using sDMA (CIK).
-  */
- static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
--				  uint64_t pe,
-+				  const dma_addr_t *pages_addr, uint64_t pe,
- 				  uint64_t addr, unsigned count,
- 				  uint32_t incr, uint32_t flags)
- {
-@@ -733,14 +733,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
- 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
- 		ib->ptr[ib->length_dw++] = ndw;
- 		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
--			if (flags & AMDGPU_PTE_SYSTEM) {
--				value = amdgpu_vm_map_gart(ib->ring->adev, addr);
--				value &= 0xFFFFFFFFFFFFF000ULL;
--			} else if (flags & AMDGPU_PTE_VALID) {
--				value = addr;
--			} else {
--				value = 0;
--			}
-+			value = amdgpu_vm_map_gart(pages_addr, addr);
- 			addr += incr;
- 			value |= flags;
- 			ib->ptr[ib->length_dw++] = value;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index e86f85f..0843f81 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -772,7 +772,7 @@ static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
-  * Update PTEs by writing them manually using sDMA (CIK).
-  */
- static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
--				   uint64_t pe,
-+				   const dma_addr_t *pages_addr, uint64_t pe,
- 				   uint64_t addr, unsigned count,
- 				   uint32_t incr, uint32_t flags)
- {
-@@ -791,14 +791,7 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
- 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
- 		ib->ptr[ib->length_dw++] = ndw;
- 		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
--			if (flags & AMDGPU_PTE_SYSTEM) {
--				value = amdgpu_vm_map_gart(ib->ring->adev, addr);
--				value &= 0xFFFFFFFFFFFFF000ULL;
--			} else if (flags & AMDGPU_PTE_VALID) {
--				value = addr;
--			} else {
--				value = 0;
--			}
-+			value = amdgpu_vm_map_gart(pages_addr, addr);
- 			addr += incr;
- 			value |= flags;
- 			ib->ptr[ib->length_dw++] = value;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index b2fbf96..7af4b57 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -922,7 +922,7 @@ static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
-  * Update PTEs by writing them manually using sDMA (CIK).
-  */
- static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
--				   uint64_t pe,
-+				   const dma_addr_t *pages_addr, uint64_t pe,
- 				   uint64_t addr, unsigned count,
- 				   uint32_t incr, uint32_t flags)
- {
-@@ -941,14 +941,7 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
- 		ib->ptr[ib->length_dw++] = upper_32_bits(pe);
- 		ib->ptr[ib->length_dw++] = ndw;
- 		for (; ndw > 0; ndw -= 2, --count, pe += 8) {
--			if (flags & AMDGPU_PTE_SYSTEM) {
--				value = amdgpu_vm_map_gart(ib->ring->adev, addr);
--				value &= 0xFFFFFFFFFFFFF000ULL;
--			} else if (flags & AMDGPU_PTE_VALID) {
--				value = addr;
--			} else {
--				value = 0;
--			}
-+			value = amdgpu_vm_map_gart(pages_addr, addr);
- 			addr += incr;
- 			value |= flags;
- 			ib->ptr[ib->length_dw++] = value;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0251-drm-amdgpu-use-BOs-GART-instance-for-mapping-address.patch b/common/recipes-kernel/linux/files/0251-drm-amdgpu-use-BOs-GART-instance-for-mapping-address.patch
deleted file mode 100644
index e55b0abd..00000000
--- a/common/recipes-kernel/linux/files/0251-drm-amdgpu-use-BOs-GART-instance-for-mapping-address.patch
+++ /dev/null
@@ -1,325 +0,0 @@
-From 7d9951feab64741e37a4324e260edf08561c861c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 30 Nov 2015 14:19:26 +0100
-Subject: [PATCH 0251/1110] drm/amdgpu: use BOs GART instance for mapping
- addresses v4
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-That allows the VM code to use GART BOs from other driver instances.
-
-v2: don't use copy optimization for foreign GARTs, that won't work.
-v3: some more comment cleanups
-v4: agd: rebase on upstream
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 114 ++++++++++++++++++++-------------
- 1 file changed, 68 insertions(+), 46 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 47e1186..3469d11 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -283,31 +283,34 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
-  * amdgpu_vm_update_pages - helper to call the right asic function
-  *
-  * @adev: amdgpu_device pointer
-+ * @gtt: GART instance to use for mapping
-+ * @gtt_flags: GTT hw access flags
-  * @ib: indirect buffer to fill with commands
-  * @pe: addr of the page entry
-  * @addr: dst addr to write into pe
-  * @count: number of page entries to update
-  * @incr: increase next addr by incr bytes
-  * @flags: hw access flags
-- * @gtt_flags: GTT hw access flags
-  *
-  * Traces the parameters and calls the right asic functions
-  * to setup the page table using the DMA.
-  */
- static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
-+				   struct amdgpu_gart *gtt,
-+				   uint32_t gtt_flags,
- 				   struct amdgpu_ib *ib,
- 				   uint64_t pe, uint64_t addr,
- 				   unsigned count, uint32_t incr,
--				   uint32_t flags, uint32_t gtt_flags)
-+				   uint32_t flags)
- {
- 	trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
- 
--	if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
--		uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
-+	if ((gtt == &adev->gart) && (flags == gtt_flags)) {
-+		uint64_t src = gtt->table_addr + (addr >> 12) * 8;
- 		amdgpu_vm_copy_pte(adev, ib, pe, src, count);
- 
--	} else if (flags & AMDGPU_PTE_SYSTEM) {
--		dma_addr_t *pages_addr = adev->gart.pages_addr;
-+	} else if (gtt) {
-+		dma_addr_t *pages_addr = gtt->pages_addr;
- 		amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
- 				    count, incr, flags);
- 
-@@ -369,7 +372,8 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 
- 	ib->length_dw = 0;
- 
--	amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
-+	amdgpu_vm_update_pages(adev, NULL, 0, ib, addr, 0, entries, 0, 0);
-+
- 	amdgpu_vm_pad_ib(adev, ib);
- 	WARN_ON(ib->length_dw > 64);
- 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
-@@ -482,9 +486,10 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 		    ((last_pt + incr * count) != pt)) {
- 
- 			if (count) {
--				amdgpu_vm_update_pages(adev, ib, last_pde,
--						       last_pt, count, incr,
--						       AMDGPU_PTE_VALID, 0);
-+				amdgpu_vm_update_pages(adev, NULL, 0, ib,
-+						       last_pde, last_pt,
-+						       count, incr,
-+						       AMDGPU_PTE_VALID);
- 			}
- 
- 			count = 1;
-@@ -496,8 +501,8 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 	}
- 
- 	if (count)
--		amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count,
--				       incr, AMDGPU_PTE_VALID, 0);
-+		amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt,
-+				       count, incr, AMDGPU_PTE_VALID);
- 
- 	if (ib->length_dw != 0) {
- 		amdgpu_vm_pad_ib(adev, ib);
-@@ -533,20 +538,22 @@ error_free:
-  * amdgpu_vm_frag_ptes - add fragment information to PTEs
-  *
-  * @adev: amdgpu_device pointer
-+ * @gtt: GART instance to use for mapping
-+ * @gtt_flags: GTT hw mapping flags
-  * @ib: IB for the update
-  * @pe_start: first PTE to handle
-  * @pe_end: last PTE to handle
-  * @addr: addr those PTEs should point to
-  * @flags: hw mapping flags
-- * @gtt_flags: GTT hw mapping flags
-  *
-  * Global and local mutex must be locked!
-  */
- static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-+				struct amdgpu_gart *gtt,
-+				uint32_t gtt_flags,
- 				struct amdgpu_ib *ib,
- 				uint64_t pe_start, uint64_t pe_end,
--				uint64_t addr, uint32_t flags,
--				uint32_t gtt_flags)
-+				uint64_t addr, uint32_t flags)
- {
- 	/**
- 	 * The MC L1 TLB supports variable sized pages, based on a fragment
-@@ -577,35 +584,34 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
- 	unsigned count;
- 
- 	/* system pages are non continuously */
--	if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
--	    (frag_start >= frag_end)) {
-+	if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) {
- 
- 		count = (pe_end - pe_start) / 8;
--		amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
--				       AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
-+		amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start,
-+				       addr, count, AMDGPU_GPU_PAGE_SIZE,
-+				       flags);
- 		return;
- 	}
- 
- 	/* handle the 4K area at the beginning */
- 	if (pe_start != frag_start) {
- 		count = (frag_start - pe_start) / 8;
--		amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
--				       AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
-+		amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr,
-+				       count, AMDGPU_GPU_PAGE_SIZE, flags);
- 		addr += AMDGPU_GPU_PAGE_SIZE * count;
- 	}
- 
- 	/* handle the area in the middle */
- 	count = (frag_end - frag_start) / 8;
--	amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
--			       AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
--			       gtt_flags);
-+	amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count,
-+			       AMDGPU_GPU_PAGE_SIZE, flags | frag_flags);
- 
- 	/* handle the 4K area at the end */
- 	if (frag_end != pe_end) {
- 		addr += AMDGPU_GPU_PAGE_SIZE * count;
- 		count = (pe_end - frag_end) / 8;
--		amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
--				       AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
-+		amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr,
-+				       count, AMDGPU_GPU_PAGE_SIZE, flags);
- 	}
- }
- 
-@@ -613,6 +619,8 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  * amdgpu_vm_update_ptes - make sure that page tables are valid
-  *
-  * @adev: amdgpu_device pointer
-+ * @gtt: GART instance to use for mapping
-+ * @gtt_flags: GTT hw mapping flags
-  * @vm: requested vm
-  * @start: start of GPU address range
-  * @end: end of GPU address range
-@@ -624,11 +632,12 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  * Global and local mutex must be locked!
-  */
- static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-+				 struct amdgpu_gart *gtt,
-+				 uint32_t gtt_flags,
- 				 struct amdgpu_vm *vm,
- 				 struct amdgpu_ib *ib,
- 				 uint64_t start, uint64_t end,
--				 uint64_t dst, uint32_t flags,
--				 uint32_t gtt_flags)
-+				 uint64_t dst, uint32_t flags)
- {
- 	uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
- 	uint64_t last_pte = ~0, last_dst = ~0;
-@@ -664,10 +673,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 		if ((last_pte + 8 * count) != pte) {
- 
- 			if (count) {
--				amdgpu_vm_frag_ptes(adev, ib, last_pte,
--						    last_pte + 8 * count,
--						    last_dst, flags,
--						    gtt_flags);
-+				amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
-+						    last_pte, last_pte + 8 * count,
-+						    last_dst, flags);
- 			}
- 
- 			count = nptes;
-@@ -682,9 +690,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 	}
- 
- 	if (count) {
--		amdgpu_vm_frag_ptes(adev, ib, last_pte,
--				    last_pte + 8 * count,
--				    last_dst, flags, gtt_flags);
-+		amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
-+				    last_pte, last_pte + 8 * count,
-+				    last_dst, flags);
- 	}
- 
- 	return 0;
-@@ -694,6 +702,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
-  *
-  * @adev: amdgpu_device pointer
-+ * @gtt: GART instance to use for mapping
-  * @vm: requested vm
-  * @mapping: mapped range and flags to use for the update
-  * @addr: addr to set the area to
-@@ -706,10 +715,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-  * Object have to be reserved and mutex must be locked!
-  */
- static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
-+				       struct amdgpu_gart *gtt,
-+				       uint32_t gtt_flags,
- 				       struct amdgpu_vm *vm,
- 				       struct amdgpu_bo_va_mapping *mapping,
--				       uint64_t addr, uint32_t gtt_flags,
--				       struct fence **fence)
-+				       uint64_t addr, struct fence **fence)
- {
- 	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	unsigned nptes, ncmds, ndw;
-@@ -739,11 +749,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	/* padding, etc. */
- 	ndw = 64;
- 
--	if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
-+	if ((gtt == &adev->gart) && (flags == gtt_flags)) {
- 		/* only copy commands needed */
- 		ndw += ncmds * 7;
- 
--	} else if (flags & AMDGPU_PTE_SYSTEM) {
-+	} else if (gtt) {
- 		/* header for write data commands */
- 		ndw += ncmds * 4;
- 
-@@ -770,9 +780,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 
- 	ib->length_dw = 0;
- 
--	r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
--				  mapping->it.last + 1, addr + mapping->offset,
--				  flags, gtt_flags);
-+	r = amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib,
-+				  mapping->it.start, mapping->it.last + 1,
-+				  addr + mapping->offset, flags);
- 
- 	if (r) {
- 		amdgpu_ib_free(adev, ib);
-@@ -821,14 +831,25 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- {
- 	struct amdgpu_vm *vm = bo_va->vm;
- 	struct amdgpu_bo_va_mapping *mapping;
-+	struct amdgpu_gart *gtt = NULL;
- 	uint32_t flags;
- 	uint64_t addr;
- 	int r;
- 
- 	if (mem) {
- 		addr = (u64)mem->start << PAGE_SHIFT;
--		if (mem->mem_type != TTM_PL_TT)
-+		switch (mem->mem_type) {
-+		case TTM_PL_TT:
-+			gtt = &bo_va->bo->adev->gart;
-+			break;
-+
-+		case TTM_PL_VRAM:
- 			addr += adev->vm_manager.vram_base_offset;
-+			break;
-+
-+		default:
-+			break;
-+		}
- 	} else {
- 		addr = 0;
- 	}
-@@ -841,8 +862,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 	spin_unlock(&vm->status_lock);
- 
- 	list_for_each_entry(mapping, &bo_va->invalids, list) {
--		r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
--						flags, &bo_va->last_pt_update);
-+		r = amdgpu_vm_bo_update_mapping(adev, gtt, flags, vm, mapping, addr,
-+						&bo_va->last_pt_update);
- 		if (r)
- 			return r;
- 	}
-@@ -888,7 +909,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
- 			struct amdgpu_bo_va_mapping, list);
- 		list_del(&mapping->list);
- 		spin_unlock(&vm->freed_lock);
--		r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
-+		r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, vm, mapping,
-+						0, NULL);
- 		kfree(mapping);
- 		if (r)
- 			return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0252-drm-amdgpu-split-VM-mappings-into-smaller-operations.patch b/common/recipes-kernel/linux/files/0252-drm-amdgpu-split-VM-mappings-into-smaller-operations.patch
deleted file mode 100644
index 01445314..00000000
--- a/common/recipes-kernel/linux/files/0252-drm-amdgpu-split-VM-mappings-into-smaller-operations.patch
+++ /dev/null
@@ -1,185 +0,0 @@
-From a3e2b400ab91822ed1680131b319cd1ee6832cb0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 25 Jan 2016 14:27:31 +0100
-Subject: [PATCH 0252/1110] drm/amdgpu: split VM mappings into smaller
- operations (v3)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If we can't copy entries from the GTT or fill them with one command split
-up the mapping operation into multiple ones.
-
-v2: agd: rebase on upstream
-v3: squash in Christian's fix
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 104 ++++++++++++++++++++++++---------
- 1 file changed, 77 insertions(+), 27 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 3469d11..ae1d20a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -703,42 +703,32 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-  *
-  * @adev: amdgpu_device pointer
-  * @gtt: GART instance to use for mapping
-+ * @gtt_flags: flags as they are used for GTT
-  * @vm: requested vm
-- * @mapping: mapped range and flags to use for the update
-+ * @start: start of mapped range
-+ * @last: last mapped entry
-+ * @flags: flags for the entries
-  * @addr: addr to set the area to
-- * @gtt_flags: flags as they are used for GTT
-  * @fence: optional resulting fence
-  *
-- * Fill in the page table entries for @mapping.
-+ * Fill in the page table entries between @start and @last.
-  * Returns 0 for success, -EINVAL for failure.
-- *
-- * Object have to be reserved and mutex must be locked!
-  */
- static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 				       struct amdgpu_gart *gtt,
- 				       uint32_t gtt_flags,
- 				       struct amdgpu_vm *vm,
--				       struct amdgpu_bo_va_mapping *mapping,
--				       uint64_t addr, struct fence **fence)
-+				       uint64_t start, uint64_t last,
-+				       uint32_t flags, uint64_t addr,
-+				       struct fence **fence)
- {
- 	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	unsigned nptes, ncmds, ndw;
--	uint32_t flags = gtt_flags;
- 	struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
- 	int r;
- 
--	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
--	 * but in case of something, we filter the flags in first place
--	 */
--	if (!(mapping->flags & AMDGPU_PTE_READABLE))
--		flags &= ~AMDGPU_PTE_READABLE;
--	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
--		flags &= ~AMDGPU_PTE_WRITEABLE;
--
--	trace_amdgpu_vm_bo_update(mapping);
--
--	nptes = mapping->it.last - mapping->it.start + 1;
-+	nptes = last - start + 1;
- 
- 	/*
- 	 * reserve space for one command every (1 << BLOCK_SIZE)
-@@ -780,10 +770,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 
- 	ib->length_dw = 0;
- 
--	r = amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib,
--				  mapping->it.start, mapping->it.last + 1,
--				  addr + mapping->offset, flags);
--
-+	r = amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start,
-+				  last + 1, addr, flags);
- 	if (r) {
- 		amdgpu_ib_free(adev, ib);
- 		kfree(ib);
-@@ -814,6 +802,68 @@ error_free:
- }
- 
- /**
-+ * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @gtt: GART instance to use for mapping
-+ * @vm: requested vm
-+ * @mapping: mapped range and flags to use for the update
-+ * @addr: addr to set the area to
-+ * @gtt_flags: flags as they are used for GTT
-+ * @fence: optional resulting fence
-+ *
-+ * Split the mapping into smaller chunks so that each update fits
-+ * into a SDMA IB.
-+ * Returns 0 for success, -EINVAL for failure.
-+ */
-+static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
-+				      struct amdgpu_gart *gtt,
-+				      uint32_t gtt_flags,
-+				      struct amdgpu_vm *vm,
-+				      struct amdgpu_bo_va_mapping *mapping,
-+				      uint64_t addr, struct fence **fence)
-+{
-+	const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
-+
-+	uint64_t start = mapping->it.start;
-+	uint32_t flags = gtt_flags;
-+	int r;
-+
-+	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
-+	 * but in case of something, we filter the flags in first place
-+	 */
-+	if (!(mapping->flags & AMDGPU_PTE_READABLE))
-+		flags &= ~AMDGPU_PTE_READABLE;
-+	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
-+		flags &= ~AMDGPU_PTE_WRITEABLE;
-+
-+	trace_amdgpu_vm_bo_update(mapping);
-+
-+	addr += mapping->offset;
-+
-+	if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags)))
-+		return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm,
-+						   start, mapping->it.last,
-+						   flags, addr, fence);
-+
-+	while (start != mapping->it.last + 1) {
-+		uint64_t last;
-+
-+		last = min((uint64_t)mapping->it.last, start + max_size);
-+		r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm,
-+						start, last, flags, addr,
-+						fence);
-+		if (r)
-+			return r;
-+
-+		start = last + 1;
-+		addr += max_size;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-  * amdgpu_vm_bo_update - update all BO mappings in the vm page table
-  *
-  * @adev: amdgpu_device pointer
-@@ -862,8 +912,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 	spin_unlock(&vm->status_lock);
- 
- 	list_for_each_entry(mapping, &bo_va->invalids, list) {
--		r = amdgpu_vm_bo_update_mapping(adev, gtt, flags, vm, mapping, addr,
--						&bo_va->last_pt_update);
-+		r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr,
-+					       &bo_va->last_pt_update);
- 		if (r)
- 			return r;
- 	}
-@@ -909,8 +959,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
- 			struct amdgpu_bo_va_mapping, list);
- 		list_del(&mapping->list);
- 		spin_unlock(&vm->freed_lock);
--		r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, vm, mapping,
--						0, NULL);
-+		r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping,
-+					       0, NULL);
- 		kfree(mapping);
- 		if (r)
- 			return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0253-drm-amdgpu-optimize-VM-fencing.patch b/common/recipes-kernel/linux/files/0253-drm-amdgpu-optimize-VM-fencing.patch
deleted file mode 100644
index 43f392a6..00000000
--- a/common/recipes-kernel/linux/files/0253-drm-amdgpu-optimize-VM-fencing.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 99daa73a701cf97a5beed053619755447ded430b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 26 Jan 2016 11:40:46 +0100
-Subject: [PATCH 0253/1110] drm/amdgpu: optimize VM fencing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to fence every page table, just the page directory is enough.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 51 +++++++++++++++-------------------
- 1 file changed, 23 insertions(+), 28 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index ae1d20a..6bf839f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -631,36 +631,25 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  *
-  * Global and local mutex must be locked!
-  */
--static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
--				 struct amdgpu_gart *gtt,
--				 uint32_t gtt_flags,
--				 struct amdgpu_vm *vm,
--				 struct amdgpu_ib *ib,
--				 uint64_t start, uint64_t end,
--				 uint64_t dst, uint32_t flags)
-+static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-+                                  struct amdgpu_gart *gtt,
-+                                  uint32_t gtt_flags,
-+                                  struct amdgpu_vm *vm,
-+                                  struct amdgpu_ib *ib,
-+                                  uint64_t start, uint64_t end,
-+                                  uint64_t dst, uint32_t flags)
- {
- 	uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
- 	uint64_t last_pte = ~0, last_dst = ~0;
--	void *owner = AMDGPU_FENCE_OWNER_VM;
- 	unsigned count = 0;
- 	uint64_t addr;
- 
--	/* sync to everything on unmapping */
--	if (!(flags & AMDGPU_PTE_VALID))
--		owner = AMDGPU_FENCE_OWNER_UNDEFINED;
--
- 	/* walk over the address space and update the page tables */
- 	for (addr = start; addr < end; ) {
- 		uint64_t pt_idx = addr >> amdgpu_vm_block_size;
-                 struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
- 		unsigned nptes;
- 		uint64_t pte;
--		int r;
--
--		amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner);
--		r = reservation_object_reserve_shared(pt->tbo.resv);
--		if (r)
--			return r;
- 
- 		if ((addr & ~mask) == (end & ~mask))
- 			nptes = end - addr;
-@@ -694,8 +683,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 				    last_pte, last_pte + 8 * count,
- 				    last_dst, flags);
- 	}
--
--	return 0;
- }
- 
- /**
-@@ -723,11 +710,16 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 				       struct fence **fence)
- {
- 	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
-+        void *owner = AMDGPU_FENCE_OWNER_VM;
- 	unsigned nptes, ncmds, ndw;
- 	struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
- 	int r;
- 
-+        /* sync to everything on unmapping */
-+        if (!(flags & AMDGPU_PTE_VALID))
-+                owner = AMDGPU_FENCE_OWNER_UNDEFINED;
-+ 
- 	nptes = last - start + 1;
- 
- 	/*
-@@ -769,14 +761,17 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	}
- 
- 	ib->length_dw = 0;
--
--	r = amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start,
--				  last + 1, addr, flags);
--	if (r) {
--		amdgpu_ib_free(adev, ib);
--		kfree(ib);
--		return r;
--	}
-+        r = amdgpu_sync_resv(adev, &ib->sync, vm->page_directory->tbo.resv,
-+                             owner);
-+        if (r)
-+                goto error_free;
-+
-+        r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
-+        if (r)
-+                goto error_free;
-+ 
-+        amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1,
-+                              addr, flags);
- 
- 	amdgpu_vm_pad_ib(adev, ib);
- 	WARN_ON(ib->length_dw > ndw);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0254-drm-amdgpu-cleanup-comments-in-VM-code.patch b/common/recipes-kernel/linux/files/0254-drm-amdgpu-cleanup-comments-in-VM-code.patch
deleted file mode 100644
index b03b9650..00000000
--- a/common/recipes-kernel/linux/files/0254-drm-amdgpu-cleanup-comments-in-VM-code.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From 240f49a4476ee24585442d8c0ed2a5880be62acc Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 26 Jan 2016 12:17:11 +0100
-Subject: [PATCH 0254/1110] drm/amdgpu: cleanup comments in VM code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Neither the global nor the local mutex exists any more and
-amdgpu doesn't support cayman.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kayan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 30 +++++++++++-------------------
- 1 file changed, 11 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 6bf839f..21d918a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -55,7 +55,7 @@
-  *
-  * @adev: amdgpu_device pointer
-  *
-- * Calculate the number of page directory entries (cayman+).
-+ * Calculate the number of page directory entries.
-  */
- static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
- {
-@@ -67,7 +67,7 @@ static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
-  *
-  * @adev: amdgpu_device pointer
-  *
-- * Calculate the size of the page directory in bytes (cayman+).
-+ * Calculate the size of the page directory in bytes.
-  */
- static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
- {
-@@ -162,8 +162,6 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-  * @fence: fence protecting ID from reuse
-  *
-  * Allocate an id for the vm, adding fences to the sync obj as necessary.
-- *
-- * Global mutex must be locked!
-  */
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		      struct amdgpu_sync *sync, struct fence *fence)
-@@ -223,9 +221,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
-  * @vm: vm we want to flush
-  * @updates: last vm update that we waited for
-  *
-- * Flush the vm (cayman+).
-- *
-- * Global and local mutex must be locked!
-+ * Flush the vm.
-  */
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 		     struct amdgpu_vm *vm,
-@@ -260,7 +256,7 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
-  * @vm: requested vm
-  * @bo: requested buffer object
-  *
-- * Find @bo inside the requested vm (cayman+).
-+ * Find @bo inside the requested vm.
-  * Search inside the @bos vm list for the requested vm
-  * Returns the found bo_va or NULL if none is found
-  *
-@@ -432,10 +428,8 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
-  * @end: end of GPU address range
-  *
-  * Allocates new page tables if necessary
-- * and updates the page directory (cayman+).
-+ * and updates the page directory.
-  * Returns 0 for success, error for failure.
-- *
-- * Global and local mutex must be locked!
-  */
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm)
-@@ -627,9 +621,7 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  * @dst: destination address to map to
-  * @flags: mapping flags
-  *
-- * Update the page tables in the range @start - @end (cayman+).
-- *
-- * Global and local mutex must be locked!
-+ * Update the page tables in the range @start - @end.
-  */
- static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-                                   struct amdgpu_gart *gtt,
-@@ -1013,7 +1005,7 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
-  * @vm: requested vm
-  * @bo: amdgpu buffer object
-  *
-- * Add @bo into the requested vm (cayman+).
-+ * Add @bo into the requested vm.
-  * Add @bo to the list of bos associated with the vm
-  * Returns newly added bo_va or NULL for failure
-  *
-@@ -1245,7 +1237,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
-  * @adev: amdgpu_device pointer
-  * @bo_va: requested bo_va
-  *
-- * Remove @bo_va->bo from the requested vm (cayman+).
-+ * Remove @bo_va->bo from the requested vm.
-  *
-  * Object have to be reserved!
-  */
-@@ -1290,7 +1282,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
-  * @vm: requested vm
-  * @bo: amdgpu buffer object
-  *
-- * Mark @bo as invalid (cayman+).
-+ * Mark @bo as invalid.
-  */
- void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
- 			     struct amdgpu_bo *bo)
-@@ -1311,7 +1303,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
-  * @adev: amdgpu_device pointer
-  * @vm: requested vm
-  *
-- * Init @vm fields (cayman+).
-+ * Init @vm fields.
-  */
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
-@@ -1372,7 +1364,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
-  * @adev: amdgpu_device pointer
-  * @vm: requested vm
-  *
-- * Tear down @vm (cayman+).
-+ * Tear down @vm.
-  * Unbind the VM and remove all bos from the vm bo list
-  */
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0255-drm-amdgpu-optimize-amdgpu_vm_update_ptes-a-bit.patch b/common/recipes-kernel/linux/files/0255-drm-amdgpu-optimize-amdgpu_vm_update_ptes-a-bit.patch
deleted file mode 100644
index c674a1e2..00000000
--- a/common/recipes-kernel/linux/files/0255-drm-amdgpu-optimize-amdgpu_vm_update_ptes-a-bit.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 804871103c28d763b94a3488262169696452c0c6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 26 Jan 2016 12:37:49 +0100
-Subject: [PATCH 0255/1110] drm/amdgpu: optimize amdgpu_vm_update_ptes a bit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Don't calculate the end address multiple times.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 ++++++++++++++++++----------------
- 1 file changed, 21 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 21d918a..83bc8b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -577,6 +577,10 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
- 
- 	unsigned count;
- 
-+        /* Abort early if there isn't anything to do */
-+        if (pe_start == pe_end)
-+                return;
-+
- 	/* system pages are non continuously */
- 	if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) {
- 
-@@ -634,6 +638,9 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 	uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
- 	uint64_t last_pte = ~0, last_dst = ~0;
- 	unsigned count = 0;
-+        const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
-+ 
-+        uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0;
- 	uint64_t addr;
- 
- 	/* walk over the address space and update the page tables */
-@@ -641,40 +648,36 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 		uint64_t pt_idx = addr >> amdgpu_vm_block_size;
-                 struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
- 		unsigned nptes;
--		uint64_t pte;
-+                uint64_t pe_start;
- 
- 		if ((addr & ~mask) == (end & ~mask))
- 			nptes = end - addr;
- 		else
- 			nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
- 
--		pte = amdgpu_bo_gpu_offset(pt);
--		pte += (addr & mask) * 8;
-+                pe_start = amdgpu_bo_gpu_offset(pt);
-+                pe_start += (addr & mask) * 8;
- 
--		if ((last_pte + 8 * count) != pte) {
-+                if (last_pe_end != pe_start) {
- 
--			if (count) {
--				amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
--						    last_pte, last_pte + 8 * count,
--						    last_dst, flags);
--			}
--
--			count = nptes;
--			last_pte = pte;
-+                        amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
-+                                            last_pe_start, last_pe_end,
-+                                            last_dst, flags);
-+ 
-+                        last_pe_start = pe_start;
-+                        last_pe_end = pe_start + 8 * nptes;
- 			last_dst = dst;
- 		} else {
--			count += nptes;
-+                        last_pe_end += 8 * nptes;
- 		}
- 
- 		addr += nptes;
- 		dst += nptes * AMDGPU_GPU_PAGE_SIZE;
- 	}
- 
--	if (count) {
--		amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
--				    last_pte, last_pte + 8 * count,
--				    last_dst, flags);
--	}
-+        amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
-+                            last_pe_start, last_pe_end,
-+                            last_dst, flags);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0256-drm-amdgpu-remove-power-of-two-limit-for-vramlimit.patch b/common/recipes-kernel/linux/files/0256-drm-amdgpu-remove-power-of-two-limit-for-vramlimit.patch
deleted file mode 100644
index a787af97..00000000
--- a/common/recipes-kernel/linux/files/0256-drm-amdgpu-remove-power-of-two-limit-for-vramlimit.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 4d3f0e0b736ba38639a08d7188474dea9ec8817b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 7 Jan 2016 11:44:13 +0100
-Subject: [PATCH 0256/1110] drm/amdgpu: remove power of two limit for vramlimit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-That works with other values as well.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ------
- 1 file changed, 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index f9c0393..4978262 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -959,12 +959,6 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
- 			 amdgpu_sched_jobs);
- 		amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
- 	}
--	/* vramlimit must be a power of two */
--	if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
--		dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
--				amdgpu_vram_limit);
--		amdgpu_vram_limit = 0;
--	}
- 
- 	if (amdgpu_gart_size != -1) {
- 		/* gtt size must be power of two and greater or equal to 32M */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0257-drm-amd-add-ACP-driver-support.patch b/common/recipes-kernel/linux/files/0257-drm-amd-add-ACP-driver-support.patch
deleted file mode 100644
index 25c73e9b..00000000
--- a/common/recipes-kernel/linux/files/0257-drm-amd-add-ACP-driver-support.patch
+++ /dev/null
@@ -1,626 +0,0 @@
-From bf389abf92583b9e6185715cdea923ee26bdea06 Mon Sep 17 00:00:00 2001
-From: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
-Date: Tue, 22 Sep 2015 17:05:20 -0400
-Subject: [PATCH 0257/1110] drm/amd: add ACP driver support
-
-This adds the ACP (Audio CoProcessor) IP driver and wires
-it up to the amdgpu driver.  The ACP block provides the DMA
-engine for i2s based ALSA driver. This is required for audio
-on APUs that utilize an i2s codec.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Murali Krishna Vemuri <murali-krishna.vemuri@amd.com>
-Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
-Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/acp/Kconfig              |  10 +
- drivers/gpu/drm/amd/acp/Makefile             |   8 +
- drivers/gpu/drm/amd/acp/acp_hw.c             |  50 +++++
- drivers/gpu/drm/amd/acp/include/acp_gfx_if.h |  34 +++
- drivers/gpu/drm/amd/amdgpu/Makefile          |  13 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu.h          |  12 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c      | 298 +++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h      |  41 ++++
- drivers/gpu/drm/amd/amdgpu/vi.c              |  12 ++
- drivers/gpu/drm/amd/include/amd_shared.h     |   1 +
- 10 files changed, 478 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/acp/Kconfig
- create mode 100644 drivers/gpu/drm/amd/acp/Makefile
- create mode 100644 drivers/gpu/drm/amd/acp/acp_hw.c
- create mode 100644 drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
- create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
- create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-
-diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
-new file mode 100644
-index 0000000..28b5e70
---- /dev/null
-+++ b/drivers/gpu/drm/amd/acp/Kconfig
-@@ -0,0 +1,10 @@
-+menu "ACP Configuration"
-+
-+config DRM_AMD_ACP
-+       bool "Enable ACP IP support"
-+       default y
-+       select MFD_CORE
-+       help
-+	Choose this option to enable ACP IP support for AMD SOCs.
-+
-+endmenu
-diff --git a/drivers/gpu/drm/amd/acp/Makefile b/drivers/gpu/drm/amd/acp/Makefile
-new file mode 100644
-index 0000000..8363cb5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/acp/Makefile
-@@ -0,0 +1,8 @@
-+#
-+# Makefile for the ACP, which is a sub-component
-+# of AMDSOC/AMDGPU drm driver.
-+# It provides the HW control for ACP related functionalities.
-+
-+subdir-ccflags-y += -I$(AMDACPPATH)/ -I$(AMDACPPATH)/include
-+
-+AMD_ACP_FILES := $(AMDACPPATH)/acp_hw.o
-diff --git a/drivers/gpu/drm/amd/acp/acp_hw.c b/drivers/gpu/drm/amd/acp/acp_hw.c
-new file mode 100644
-index 0000000..7af83f1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/acp/acp_hw.c
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/device.h>
-+#include <linux/delay.h>
-+#include <linux/errno.h>
-+
-+#include "acp_gfx_if.h"
-+
-+#define ACP_MODE_I2S	0
-+#define ACP_MODE_AZ	1
-+
-+#define mmACP_AZALIA_I2S_SELECT 0x51d4
-+
-+int amd_acp_hw_init(void *cgs_device,
-+		    unsigned acp_version_major, unsigned acp_version_minor)
-+{
-+	unsigned int acp_mode = ACP_MODE_I2S;
-+
-+	if ((acp_version_major == 2) && (acp_version_minor == 2))
-+		acp_mode = cgs_read_register(cgs_device,
-+					mmACP_AZALIA_I2S_SELECT);
-+
-+	if (acp_mode != ACP_MODE_I2S)
-+		return -ENODEV;
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
-new file mode 100644
-index 0000000..bccf47b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+*/
-+
-+#ifndef _ACP_GFX_IF_H
-+#define _ACP_GFX_IF_H
-+
-+#include <linux/types.h>
-+#include "cgs_linux.h"
-+#include "cgs_common.h"
-+
-+int amd_acp_hw_init(void *cgs_device,
-+		    unsigned acp_version_major, unsigned acp_version_minor);
-+
-+#endif /* _ACP_GFX_IF_H */
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index 7e4568e..dceebbb 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -8,7 +8,8 @@ ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
- 	-I$(FULL_AMD_PATH)/include \
- 	-I$(FULL_AMD_PATH)/amdgpu \
- 	-I$(FULL_AMD_PATH)/scheduler \
--	-I$(FULL_AMD_PATH)/powerplay/inc
-+	-I$(FULL_AMD_PATH)/powerplay/inc \
-+	-I$(FULL_AMD_PATH)/acp/include
- 
- amdgpu-y := amdgpu_drv.o
- 
-@@ -94,6 +95,16 @@ amdgpu-y += \
- 	../scheduler/sched_fence.o \
- 	amdgpu_sched.o
- 
-+# ACP componet
-+ifneq ($(CONFIG_DRM_AMD_ACP),)
-+amdgpu-y += amdgpu_acp.o
-+
-+AMDACPPATH := ../acp
-+include $(FULL_AMD_PATH)/acp/Makefile
-+
-+amdgpu-y += $(AMD_ACP_FILES)
-+endif
-+
- amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
- amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
- amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e182c9f..e134cfe 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -53,6 +53,7 @@
- #include "amdgpu_ucode.h"
- #include "amdgpu_gds.h"
- #include "amd_powerplay.h"
-+#include "amdgpu_acp.h"
- 
- #include "gpu_scheduler.h"
- 
-@@ -1857,6 +1858,13 @@ void amdgpu_cgs_destroy_device(void *cgs_device);
- 
- 
- /*
-+ * CGS
-+ */
-+void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
-+void amdgpu_cgs_destroy_device(void *cgs_device);
-+
-+
-+/*
-  * Core structure, functions and helpers.
-  */
- typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
-@@ -1876,6 +1884,10 @@ struct amdgpu_device {
- 	struct drm_device		*ddev;
- 	struct pci_dev			*pdev;
- 
-+#ifdef CONFIG_DRM_AMD_ACP
-+	struct amdgpu_acp		acp;
-+#endif
-+
- 	/* ASIC */
- 	enum amd_asic_type		asic_type;
- 	uint32_t			family;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-new file mode 100644
-index 0000000..71f26e9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -0,0 +1,298 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/irqdomain.h>
-+#include <linux/platform_device.h>
-+#include <sound/designware_i2s.h>
-+#include <sound/pcm.h>
-+
-+#include "amdgpu.h"
-+#include "atom.h"
-+#include "amdgpu_acp.h"
-+
-+#include "acp_gfx_if.h"
-+
-+#define ACP_TILE_ON_MASK                0x03
-+#define ACP_TILE_OFF_MASK               0x02
-+#define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
-+#define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
-+
-+#define ACP_TILE_P1_MASK                0x3e
-+#define ACP_TILE_P2_MASK                0x3d
-+#define ACP_TILE_DSP0_MASK              0x3b
-+#define ACP_TILE_DSP1_MASK              0x37
-+
-+#define ACP_TILE_DSP2_MASK              0x2f
-+
-+#define ACP_DMA_REGS_END		0x146c0
-+#define ACP_I2S_PLAY_REGS_START		0x14840
-+#define ACP_I2S_PLAY_REGS_END		0x148b4
-+#define ACP_I2S_CAP_REGS_START		0x148b8
-+#define ACP_I2S_CAP_REGS_END		0x1496c
-+
-+#define ACP_I2S_COMP1_CAP_REG_OFFSET	0xac
-+#define ACP_I2S_COMP2_CAP_REG_OFFSET	0xa8
-+#define ACP_I2S_COMP1_PLAY_REG_OFFSET	0x6c
-+#define ACP_I2S_COMP2_PLAY_REG_OFFSET	0x68
-+
-+#define mmACP_PGFSM_RETAIN_REG		0x51c9
-+#define mmACP_PGFSM_CONFIG_REG		0x51ca
-+#define mmACP_PGFSM_READ_REG_0		0x51cc
-+
-+#define mmACP_MEM_SHUT_DOWN_REQ_LO	0x51f8
-+#define mmACP_MEM_SHUT_DOWN_REQ_HI	0x51f9
-+#define mmACP_MEM_SHUT_DOWN_STS_LO	0x51fa
-+#define mmACP_MEM_SHUT_DOWN_STS_HI	0x51fb
-+
-+#define ACP_TIMEOUT_LOOP		0x000000FF
-+#define ACP_DEVS			3
-+#define ACP_SRC_ID			162
-+
-+enum {
-+	ACP_TILE_P1 = 0,
-+	ACP_TILE_P2,
-+	ACP_TILE_DSP0,
-+	ACP_TILE_DSP1,
-+	ACP_TILE_DSP2,
-+};
-+
-+static int acp_sw_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	adev->acp.parent = adev->dev;
-+
-+	adev->acp.cgs_device =
-+		amdgpu_cgs_create_device(adev);
-+	if (!adev->acp.cgs_device)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int acp_sw_fini(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->acp.cgs_device)
-+		amdgpu_cgs_destroy_device(adev->acp.cgs_device);
-+
-+	return 0;
-+}
-+
-+/**
-+ * acp_hw_init - start and test ACP block
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ */
-+static int acp_hw_init(void *handle)
-+{
-+	int r;
-+	uint64_t acp_base;
-+	struct i2s_platform_data *i2s_pdata;
-+
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	const struct amdgpu_ip_block_version *ip_version =
-+		amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
-+
-+	if (!ip_version)
-+		return -EINVAL;
-+
-+	r = amd_acp_hw_init(adev->acp.cgs_device,
-+			    ip_version->major, ip_version->minor);
-+	/* -ENODEV means board uses AZ rather than ACP */
-+	if (r == -ENODEV)
-+		return 0;
-+	else if (r)
-+		return r;
-+
-+	r = cgs_get_pci_resource(adev->acp.cgs_device, CGS_RESOURCE_TYPE_MMIO,
-+			0x5289, 0, &acp_base);
-+	if (r == -ENODEV)
-+		return 0;
-+	else if (r)
-+		return r;
-+
-+	adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS,
-+							GFP_KERNEL);
-+
-+	if (adev->acp.acp_cell == NULL)
-+		return -ENOMEM;
-+
-+	adev->acp.acp_res = kzalloc(sizeof(struct resource) * 4, GFP_KERNEL);
-+
-+	if (adev->acp.acp_res == NULL) {
-+		kfree(adev->acp.acp_cell);
-+		return -ENOMEM;
-+	}
-+
-+	i2s_pdata = kzalloc(sizeof(struct i2s_platform_data) * 2, GFP_KERNEL);
-+	if (i2s_pdata == NULL) {
-+		kfree(adev->acp.acp_res);
-+		kfree(adev->acp.acp_cell);
-+		return -ENOMEM;
-+	}
-+
-+	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
-+	i2s_pdata[0].cap = DWC_I2S_PLAY;
-+	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
-+	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
-+	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
-+
-+	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-+				DW_I2S_QUIRK_COMP_PARAM1;
-+	i2s_pdata[1].cap = DWC_I2S_RECORD;
-+	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
-+	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
-+	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
-+
-+	adev->acp.acp_res[0].name = "acp2x_dma";
-+	adev->acp.acp_res[0].flags = IORESOURCE_MEM;
-+	adev->acp.acp_res[0].start = acp_base;
-+	adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
-+
-+	adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
-+	adev->acp.acp_res[1].flags = IORESOURCE_MEM;
-+	adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
-+	adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
-+
-+	adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
-+	adev->acp.acp_res[2].flags = IORESOURCE_MEM;
-+	adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
-+	adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
-+
-+	adev->acp.acp_res[3].name = "acp2x_dma_irq";
-+	adev->acp.acp_res[3].flags = IORESOURCE_IRQ;
-+	adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162);
-+	adev->acp.acp_res[3].end = adev->acp.acp_res[3].start;
-+
-+	adev->acp.acp_cell[0].name = "acp_audio_dma";
-+	adev->acp.acp_cell[0].num_resources = 4;
-+	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
-+
-+	adev->acp.acp_cell[1].name = "designware-i2s";
-+	adev->acp.acp_cell[1].num_resources = 1;
-+	adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
-+	adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
-+	adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
-+
-+	adev->acp.acp_cell[2].name = "designware-i2s";
-+	adev->acp.acp_cell[2].num_resources = 1;
-+	adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
-+	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
-+	adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
-+
-+	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
-+								ACP_DEVS);
-+	if (r)
-+		return r;
-+
-+	return 0;
-+}
-+
-+/**
-+ * acp_hw_fini - stop the hardware block
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ */
-+static int acp_hw_fini(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	mfd_remove_devices(adev->acp.parent);
-+	kfree(adev->acp.acp_res);
-+	kfree(adev->acp.acp_cell);
-+
-+	return 0;
-+}
-+
-+static int acp_suspend(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int acp_resume(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int acp_early_init(void *handle)
-+{
-+	return 0;
-+}
-+
-+static bool acp_is_idle(void *handle)
-+{
-+	return true;
-+}
-+
-+static int acp_wait_for_idle(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int acp_soft_reset(void *handle)
-+{
-+	return 0;
-+}
-+
-+static void acp_print_status(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	dev_info(adev->dev, "ACP STATUS\n");
-+}
-+
-+static int acp_set_clockgating_state(void *handle,
-+				     enum amd_clockgating_state state)
-+{
-+	return 0;
-+}
-+
-+static int acp_set_powergating_state(void *handle,
-+				     enum amd_powergating_state state)
-+{
-+	return 0;
-+}
-+
-+const struct amd_ip_funcs acp_ip_funcs = {
-+	.early_init = acp_early_init,
-+	.late_init = NULL,
-+	.sw_init = acp_sw_init,
-+	.sw_fini = acp_sw_fini,
-+	.hw_init = acp_hw_init,
-+	.hw_fini = acp_hw_fini,
-+	.suspend = acp_suspend,
-+	.resume = acp_resume,
-+	.is_idle = acp_is_idle,
-+	.wait_for_idle = acp_wait_for_idle,
-+	.soft_reset = acp_soft_reset,
-+	.print_status = acp_print_status,
-+	.set_clockgating_state = acp_set_clockgating_state,
-+	.set_powergating_state = acp_set_powergating_state,
-+};
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-new file mode 100644
-index 0000000..24952ed
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-@@ -0,0 +1,41 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __AMDGPU_ACP_H__
-+#define __AMDGPU_ACP_H__
-+
-+#include <linux/mfd/core.h>
-+
-+struct amdgpu_acp {
-+	struct device *parent;
-+	void *cgs_device;
-+	struct amd_acp_private *private;
-+	struct mfd_cell *acp_cell;
-+	struct resource *acp_res;
-+};
-+
-+extern const struct amd_ip_funcs acp_ip_funcs;
-+
-+#endif /* __AMDGPU_ACP_H__ */
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 4ccf415..b72cf06 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -74,6 +74,9 @@
- #include "uvd_v6_0.h"
- #include "vce_v3_0.h"
- #include "amdgpu_powerplay.h"
-+#if defined(CONFIG_DRM_AMD_ACP)
-+#include "amdgpu_acp.h"
-+#endif
- 
- /*
-  * Indirect registers accessor
-@@ -970,6 +973,15 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] =
- 		.rev = 0,
- 		.funcs = &vce_v3_0_ip_funcs,
- 	},
-+#if defined(CONFIG_DRM_AMD_ACP)
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_ACP,
-+		.major = 2,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &acp_ip_funcs,
-+	},
-+#endif
- };
- 
- int vi_set_ip_blocks(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index dbf7e64..04e4090 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -73,6 +73,7 @@ enum amd_ip_block_type {
- 	AMD_IP_BLOCK_TYPE_SDMA,
- 	AMD_IP_BLOCK_TYPE_UVD,
- 	AMD_IP_BLOCK_TYPE_VCE,
-+	AMD_IP_BLOCK_TYPE_ACP,
- };
- 
- enum amd_clockgating_state {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0258-drm-amd-add-pm-domain-for-ACP-IP-sub-blocks.patch b/common/recipes-kernel/linux/files/0258-drm-amd-add-pm-domain-for-ACP-IP-sub-blocks.patch
deleted file mode 100644
index 2c43d4be..00000000
--- a/common/recipes-kernel/linux/files/0258-drm-amd-add-pm-domain-for-ACP-IP-sub-blocks.patch
+++ /dev/null
@@ -1,311 +0,0 @@
-From c4179391cc0a3321b45cda7fcc0431d71421e58d Mon Sep 17 00:00:00 2001
-From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
-Date: Mon, 23 Nov 2015 21:07:30 +0530
-Subject: [PATCH 0258/1110] drm/amd: add pm domain for ACP IP sub blocks
-
-ACP IP have internal DMA controller, DW I2S controller and DSPs
-as separate power tiles. DMA and I2S devices are added to generic
-pm domain, so that entire IP can be powered off/on at appropriate
-times. Unused DSPs are made to be powered off though they are powered
-on during ACP pm domain power on sequence.
-
-Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/acp/Kconfig         |   1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 206 +++++++++++++++++++++++++++++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h |   1 +
- 3 files changed, 207 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
-index 28b5e70..2b07813 100644
---- a/drivers/gpu/drm/amd/acp/Kconfig
-+++ b/drivers/gpu/drm/amd/acp/Kconfig
-@@ -4,6 +4,7 @@ config DRM_AMD_ACP
-        bool "Enable ACP IP support"
-        default y
-        select MFD_CORE
-+       select PM_GENERIC_DOMAINS if PM
-        help
- 	Choose this option to enable ACP IP support for AMD SOCs.
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-index 71f26e9..9f8cfaa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -24,6 +24,7 @@
-  */
- 
- #include <linux/irqdomain.h>
-+#include <linux/pm_domain.h>
- #include <linux/platform_device.h>
- #include <sound/designware_i2s.h>
- #include <sound/pcm.h>
-@@ -102,6 +103,155 @@ static int acp_sw_fini(void *handle)
- 	return 0;
- }
- 
-+/* power off a tile/block within ACP */
-+static int acp_suspend_tile(void *cgs_dev, int tile)
-+{
-+	u32 val = 0;
-+	u32 count = 0;
-+
-+	if ((tile  < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
-+		pr_err("Invalid ACP tile : %d to suspend\n", tile);
-+		return -1;
-+	}
-+
-+	val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
-+	val &= ACP_TILE_ON_MASK;
-+
-+	if (val == 0x0) {
-+		val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
-+		val = val | (1 << tile);
-+		cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
-+		cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
-+					0x500 + tile);
-+
-+		count = ACP_TIMEOUT_LOOP;
-+		while (true) {
-+			val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
-+								+ tile);
-+			val = val & ACP_TILE_ON_MASK;
-+			if (val == ACP_TILE_OFF_MASK)
-+				break;
-+			if (--count == 0) {
-+				pr_err("Timeout reading ACP PGFSM status\n");
-+				return -ETIMEDOUT;
-+			}
-+			udelay(100);
-+		}
-+
-+		val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
-+
-+		val |= ACP_TILE_OFF_RETAIN_REG_MASK;
-+		cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
-+	}
-+	return 0;
-+}
-+
-+/* power on a tile/block within ACP */
-+static int acp_resume_tile(void *cgs_dev, int tile)
-+{
-+	u32 val = 0;
-+	u32 count = 0;
-+
-+	if ((tile  < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
-+		pr_err("Invalid ACP tile to resume\n");
-+		return -1;
-+	}
-+
-+	val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
-+	val = val & ACP_TILE_ON_MASK;
-+
-+	if (val != 0x0) {
-+		cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
-+					0x600 + tile);
-+		count = ACP_TIMEOUT_LOOP;
-+		while (true) {
-+			val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
-+							+ tile);
-+			val = val & ACP_TILE_ON_MASK;
-+			if (val == 0x0)
-+				break;
-+			if (--count == 0) {
-+				pr_err("Timeout reading ACP PGFSM status\n");
-+				return -ETIMEDOUT;
-+			}
-+			udelay(100);
-+		}
-+		val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
-+		if (tile == ACP_TILE_P1)
-+			val = val & (ACP_TILE_P1_MASK);
-+		else if (tile == ACP_TILE_P2)
-+			val = val & (ACP_TILE_P2_MASK);
-+
-+		cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
-+	}
-+	return 0;
-+}
-+
-+struct acp_pm_domain {
-+	void *cgs_dev;
-+	struct generic_pm_domain gpd;
-+};
-+
-+static int acp_poweroff(struct generic_pm_domain *genpd)
-+{
-+	int i, ret;
-+	struct acp_pm_domain *apd;
-+
-+	apd = container_of(genpd, struct acp_pm_domain, gpd);
-+	if (apd != NULL) {
-+		/* Donot return abruptly if any of power tile fails to suspend.
-+		 * Log it and continue powering off other tile
-+		 */
-+		for (i = 4; i >= 0 ; i--) {
-+			ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i);
-+			if (ret)
-+				pr_err("ACP tile %d tile suspend failed\n", i);
-+		}
-+	}
-+	return 0;
-+}
-+
-+static int acp_poweron(struct generic_pm_domain *genpd)
-+{
-+	int i, ret;
-+	struct acp_pm_domain *apd;
-+
-+	apd = container_of(genpd, struct acp_pm_domain, gpd);
-+	if (apd != NULL) {
-+		for (i = 0; i < 2; i++) {
-+			ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i);
-+			if (ret) {
-+				pr_err("ACP tile %d resume failed\n", i);
-+				break;
-+			}
-+		}
-+
-+		/* Disable DSPs which are not going to be used */
-+		for (i = 0; i < 3; i++) {
-+			ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i);
-+			/* Continue suspending other DSP, even if one fails */
-+			if (ret)
-+				pr_err("ACP DSP %d suspend failed\n", i);
-+		}
-+	}
-+	return 0;
-+}
-+
-+static struct device *get_mfd_cell_dev(const char *device_name, int r)
-+{
-+	char auto_dev_name[25];
-+	char buf[8];
-+	struct device *dev;
-+
-+	sprintf(buf, ".%d.auto", r);
-+	strcpy(auto_dev_name, device_name);
-+	strcat(auto_dev_name, buf);
-+	dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
-+	dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
-+
-+	return dev;
-+}
-+
- /**
-  * acp_hw_init - start and test ACP block
-  *
-@@ -110,8 +260,9 @@ static int acp_sw_fini(void *handle)
-  */
- static int acp_hw_init(void *handle)
- {
--	int r;
-+	int r, i;
- 	uint64_t acp_base;
-+	struct device *dev;
- 	struct i2s_platform_data *i2s_pdata;
- 
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -137,6 +288,19 @@ static int acp_hw_init(void *handle)
- 	else if (r)
- 		return r;
- 
-+	adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
-+	if (adev->acp.acp_genpd == NULL)
-+		return -ENOMEM;
-+
-+	adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
-+	adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
-+	adev->acp.acp_genpd->gpd.power_on = acp_poweron;
-+
-+
-+	adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
-+
-+	pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
-+
- 	adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS,
- 							GFP_KERNEL);
- 
-@@ -211,6 +375,15 @@ static int acp_hw_init(void *handle)
- 	if (r)
- 		return r;
- 
-+	for (i = 0; i < ACP_DEVS ; i++) {
-+		dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-+		r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
-+		if (r) {
-+			dev_err(dev, "Failed to add dev to genpd\n");
-+			return r;
-+		}
-+	}
-+
- 	return 0;
- }
- 
-@@ -222,10 +395,22 @@ static int acp_hw_init(void *handle)
-  */
- static int acp_hw_fini(void *handle)
- {
-+	int i, ret;
-+	struct device *dev;
-+
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	for (i = 0; i < ACP_DEVS ; i++) {
-+		dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-+		ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev);
-+		/* If removal fails, dont giveup and try rest */
-+		if (ret)
-+			dev_err(dev, "remove dev from genpd failed\n");
-+	}
-+
- 	mfd_remove_devices(adev->acp.parent);
- 	kfree(adev->acp.acp_res);
-+	kfree(adev->acp.acp_genpd);
- 	kfree(adev->acp.acp_cell);
- 
- 	return 0;
-@@ -238,6 +423,25 @@ static int acp_suspend(void *handle)
- 
- static int acp_resume(void *handle)
- {
-+	int i, ret;
-+	struct acp_pm_domain *apd;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	/* SMU block will power on ACP irrespective of ACP runtime status.
-+	 * Power off explicitly based on genpd ACP runtime status so that ACP
-+	 * hw and ACP-genpd status are in sync.
-+	 * 'suspend_power_off' represents "Power status before system suspend"
-+	*/
-+	if (adev->acp.acp_genpd->gpd.suspend_power_off == true) {
-+		apd = container_of(&adev->acp.acp_genpd->gpd,
-+					struct acp_pm_domain, gpd);
-+
-+		for (i = 4; i >= 0 ; i--) {
-+			ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i);
-+			if (ret)
-+				pr_err("ACP tile %d tile suspend failed\n", i);
-+		}
-+	}
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-index 24952ed..f6e32a6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-@@ -34,6 +34,7 @@ struct amdgpu_acp {
- 	struct amd_acp_private *private;
- 	struct mfd_cell *acp_cell;
- 	struct resource *acp_res;
-+	struct acp_pm_domain *acp_genpd;
- };
- 
- extern const struct amd_ip_funcs acp_ip_funcs;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0259-drm-amdgpu-remove-unused-function.patch b/common/recipes-kernel/linux/files/0259-drm-amdgpu-remove-unused-function.patch
deleted file mode 100644
index 0fe5f929..00000000
--- a/common/recipes-kernel/linux/files/0259-drm-amdgpu-remove-unused-function.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From cf997eaeedc31608efe81c8a1ee5af441bad0de1 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 1 Feb 2016 11:18:30 -0500
-Subject: [PATCH 0259/1110] drm/amdgpu: remove unused function
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-amdgpu_boot_test_post_card() is not used anywhere.  Probably
-a leftover from the original port from radeon.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 25 -------------------------
- 2 files changed, 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e134cfe..5d51ef2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2306,7 +2306,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev);
- void amdgpu_pci_config_reset(struct amdgpu_device *adev);
- bool amdgpu_card_posted(struct amdgpu_device *adev);
- void amdgpu_update_display_priority(struct amdgpu_device *adev);
--bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
- 
- int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
- int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 4978262..4ba9ae4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -636,31 +636,6 @@ bool amdgpu_card_posted(struct amdgpu_device *adev)
- }
- 
- /**
-- * amdgpu_boot_test_post_card - check and possibly initialize the hw
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Check if the asic is initialized and if not, attempt to initialize
-- * it (all asics).
-- * Returns true if initialized or false if not.
-- */
--bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
--{
--	if (amdgpu_card_posted(adev))
--		return true;
--
--	if (adev->bios) {
--		DRM_INFO("GPU not posted. posting now...\n");
--		if (adev->is_atom_bios)
--			amdgpu_atom_asic_init(adev->mode_info.atom_context);
--		return true;
--	} else {
--		dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
--		return false;
--	}
--}
--
--/**
-  * amdgpu_dummy_page_init - init dummy page used by the driver
-  *
-  * @adev: amdgpu_device pointer
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0260-drm-amdgpu-add-check-for-atombios-GPU-virtualization.patch b/common/recipes-kernel/linux/files/0260-drm-amdgpu-add-check-for-atombios-GPU-virtualization.patch
deleted file mode 100644
index 48f0ecc9..00000000
--- a/common/recipes-kernel/linux/files/0260-drm-amdgpu-add-check-for-atombios-GPU-virtualization.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From bebed259df3daca6fee960d5243b5df96879c684 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 1 Feb 2016 11:00:49 -0500
-Subject: [PATCH 0260/1110] drm/amdgpu: add check for atombios GPU
- virtualization table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This table is found on boards that support SR-IOV.  This will
-be used to determine if the board supports SR-IOV and allow
-the driver to take specific action in certain cases.
-
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 13 +++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |  2 ++
- 2 files changed, 15 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
-index 9416e0f..84b0ce3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
-@@ -1514,6 +1514,19 @@ int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
- 	return -EINVAL;
- }
- 
-+bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
-+{
-+	int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
-+	u8 frev, crev;
-+	u16 data_offset, size;
-+
-+	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
-+					  &frev, &crev, &data_offset))
-+		return true;
-+
-+	return false;
-+}
-+
- void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
- {
- 	uint32_t bios_6_scratch;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
-index 0ebb959..9e14420 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
-@@ -196,6 +196,8 @@ int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
- 				      u8 module_index,
- 				      struct atom_mc_reg_table *reg_table);
- 
-+bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
-+
- void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
- void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
- void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0261-drm-amdgpu-track-whether-the-asic-supports-SR-IOV.patch b/common/recipes-kernel/linux/files/0261-drm-amdgpu-track-whether-the-asic-supports-SR-IOV.patch
deleted file mode 100644
index 7b88995c..00000000
--- a/common/recipes-kernel/linux/files/0261-drm-amdgpu-track-whether-the-asic-supports-SR-IOV.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 13b2c75583f64d8579d9da073e68cbbcc8173d50 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 1 Feb 2016 11:13:04 -0500
-Subject: [PATCH 0261/1110] drm/amdgpu: track whether the asic supports SR-IOV
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Required to make desicions about certain code pathes.
-
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 7 +++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
- 2 files changed, 11 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 5d51ef2..27c530b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1864,6 +1864,11 @@ void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
- void amdgpu_cgs_destroy_device(void *cgs_device);
- 
- 
-+/* GPU virtualization */
-+struct amdgpu_virtualization {
-+	bool supports_sr_iov;
-+};
-+
- /*
-  * Core structure, functions and helpers.
-  */
-@@ -2037,6 +2042,8 @@ struct amdgpu_device {
- 
- 	/* kernel conext for IB submission */
- 	struct amdgpu_ctx	kernel_ctx;
-+
-+	struct amdgpu_virtualization virtualization;
- };
- 
- bool amdgpu_device_is_px(struct drm_device *dev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 4ba9ae4..970844d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1500,6 +1500,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 		return r;
- 	}
- 
-+	/* See if the asic supports SR-IOV */
-+	adev->virtualization.supports_sr_iov =
-+		amdgpu_atombios_has_gpu_virtualization_table(adev);
-+
- 	/* Post card if necessary */
- 	if (!amdgpu_card_posted(adev)) {
- 		if (!adev->bios) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0262-drm-amdgpu-always-repost-cards-that-support-SR-IOV.patch b/common/recipes-kernel/linux/files/0262-drm-amdgpu-always-repost-cards-that-support-SR-IOV.patch
deleted file mode 100644
index 748b62a1..00000000
--- a/common/recipes-kernel/linux/files/0262-drm-amdgpu-always-repost-cards-that-support-SR-IOV.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 7cb1f29018daa909fd4b64df67279b4bab1080c8 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 1 Feb 2016 11:23:15 -0500
-Subject: [PATCH 0262/1110] drm/amdgpu: always repost cards that support SR-IOV
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Generally a good idea between VM sessions.  We need a way to
-detect VM pass-through in general and always run asic_init in
-that case.
-
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 970844d..b8b132f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1505,7 +1505,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 		amdgpu_atombios_has_gpu_virtualization_table(adev);
- 
- 	/* Post card if necessary */
--	if (!amdgpu_card_posted(adev)) {
-+	if (!amdgpu_card_posted(adev) ||
-+	    adev->virtualization.supports_sr_iov) {
- 		if (!adev->bios) {
- 			dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
- 			return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0263-drm-amdgpu-gmc8-skip-MC-ucode-loading-on-SR-IOV-capa.patch b/common/recipes-kernel/linux/files/0263-drm-amdgpu-gmc8-skip-MC-ucode-loading-on-SR-IOV-capa.patch
deleted file mode 100644
index 41c1a856..00000000
--- a/common/recipes-kernel/linux/files/0263-drm-amdgpu-gmc8-skip-MC-ucode-loading-on-SR-IOV-capa.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 0e236101475d1cc881d0ed01a672906cba6af527 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 1 Feb 2016 11:29:54 -0500
-Subject: [PATCH 0263/1110] drm/amdgpu/gmc8: skip MC ucode loading on SR-IOV
- capable boards
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-VBIOS does this for us in asic_init.
-
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 009fe5f..b410c32 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -252,6 +252,12 @@ static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
- 	if (!adev->mc.fw)
- 		return -EINVAL;
- 
-+	/* Skip MC ucode loading on SR-IOV capable boards.
-+	 * vbios does this for us in asic_init in that case.
-+	 */
-+	if (adev->virtualization.supports_sr_iov)
-+		return 0;
-+
- 	hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
- 	amdgpu_ucode_print_mc_hdr(&hdr->header);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0264-drm-amdgpu-smu-skip-SMC-ucode-loading-on-SR-IOV-capa.patch b/common/recipes-kernel/linux/files/0264-drm-amdgpu-smu-skip-SMC-ucode-loading-on-SR-IOV-capa.patch
deleted file mode 100644
index 23ce2000..00000000
--- a/common/recipes-kernel/linux/files/0264-drm-amdgpu-smu-skip-SMC-ucode-loading-on-SR-IOV-capa.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 41f377189cfbb06787d975219c57053667c4abe3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 1 Feb 2016 11:43:28 -0500
-Subject: [PATCH 0264/1110] drm/amdgpu/smu: skip SMC ucode loading on SR-IOV
- capable boards (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-VBIOS does this for us in asic_init.
-
-v2: update iceland as well
-
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/fiji_smc.c    | 6 ++++++
- drivers/gpu/drm/amd/amdgpu/iceland_smc.c | 6 ++++++
- drivers/gpu/drm/amd/amdgpu/tonga_smc.c   | 6 ++++++
- 3 files changed, 18 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_smc.c b/drivers/gpu/drm/amd/amdgpu/fiji_smc.c
-index e35340a..b336c91 100644
---- a/drivers/gpu/drm/amd/amdgpu/fiji_smc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/fiji_smc.c
-@@ -272,6 +272,12 @@ static int fiji_smu_upload_firmware_image(struct amdgpu_device *adev)
- 	if (!adev->pm.fw)
- 		return -EINVAL;
- 
-+	/* Skip SMC ucode loading on SR-IOV capable boards.
-+	 * vbios does this for us in asic_init in that case.
-+	 */
-+	if (adev->virtualization.supports_sr_iov)
-+		return 0;
-+
- 	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
- 	amdgpu_ucode_print_smc_hdr(&hdr->header);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
-index 090486c..52ee081 100644
---- a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c
-@@ -279,6 +279,12 @@ static int iceland_smu_upload_firmware_image(struct amdgpu_device *adev)
- 	if (!adev->pm.fw)
- 		return -EINVAL;
- 
-+	/* Skip SMC ucode loading on SR-IOV capable boards.
-+	 * vbios does this for us in asic_init in that case.
-+	 */
-+	if (adev->virtualization.supports_sr_iov)
-+		return 0;
-+
- 	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
- 	amdgpu_ucode_print_smc_hdr(&hdr->header);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smc.c b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
-index 361c49a..083893d 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c
-@@ -272,6 +272,12 @@ static int tonga_smu_upload_firmware_image(struct amdgpu_device *adev)
- 	if (!adev->pm.fw)
- 		return -EINVAL;
- 
-+	/* Skip SMC ucode loading on SR-IOV capable boards.
-+	 * vbios does this for us in asic_init in that case.
-+	 */
-+	if (adev->virtualization.supports_sr_iov)
-+		return 0;
-+
- 	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
- 	amdgpu_ucode_print_smc_hdr(&hdr->header);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0265-drm-amdgpu-fix-size-estimation-for-clear-IB.patch b/common/recipes-kernel/linux/files/0265-drm-amdgpu-fix-size-estimation-for-clear-IB.patch
deleted file mode 100644
index 95ff9ab7..00000000
--- a/common/recipes-kernel/linux/files/0265-drm-amdgpu-fix-size-estimation-for-clear-IB.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 6f4f75e5e240c3eebdaaa6e00b2e228f7d782673 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 3 Feb 2016 22:39:01 +0100
-Subject: [PATCH 0265/1110] drm/amdgpu: fix size estimation for clear IB
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We only need a few dw here.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 83bc8b1..6512386 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -362,15 +362,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	if (!ib)
- 		goto error;
- 
--	r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib);
-+	r = amdgpu_ib_get(ring, NULL, 64, ib);
- 	if (r)
- 		goto error_free;
- 
- 	ib->length_dw = 0;
- 
- 	amdgpu_vm_update_pages(adev, NULL, 0, ib, addr, 0, entries, 0, 0);
--
- 	amdgpu_vm_pad_ib(adev, ib);
-+
- 	WARN_ON(ib->length_dw > 64);
- 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
- 						 &amdgpu_vm_free_job,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0266-drm-amdgpu-add-amdgpu_set_ib_value-helper-v2.patch b/common/recipes-kernel/linux/files/0266-drm-amdgpu-add-amdgpu_set_ib_value-helper-v2.patch
deleted file mode 100644
index f59f3458..00000000
--- a/common/recipes-kernel/linux/files/0266-drm-amdgpu-add-amdgpu_set_ib_value-helper-v2.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From fba087bf357fd8d9a02fef8819929b489523c2d6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 31 Jan 2016 11:00:41 +0100
-Subject: [PATCH 0266/1110] drm/amdgpu: add amdgpu_set_ib_value helper (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-And use it in UVD/VCE command patching.
-
-v2: squash in Christian's fix
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 10 +++++++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  8 ++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  5 ++---
- 3 files changed, 15 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 27c530b..a48dbe7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1215,11 +1215,19 @@ struct amdgpu_job {
- #define to_amdgpu_job(sched_job)		\
- 		container_of((sched_job), struct amdgpu_job, base)
- 
--static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
-+static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
-+				      uint32_t ib_idx, int idx)
- {
- 	return p->ibs[ib_idx].ptr[idx];
- }
- 
-+static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
-+				       uint32_t ib_idx, int idx,
-+				       uint32_t value)
-+{
-+	p->ibs[ib_idx].ptr[idx] = value;
-+}
-+
- /*
-  * Writeback
-  */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index b4e902c..2a20b66 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -621,7 +621,6 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
- {
- 	struct amdgpu_bo_va_mapping *mapping;
- 	struct amdgpu_bo *bo;
--	struct amdgpu_ib *ib;
- 	uint32_t cmd, lo, hi;
- 	uint64_t start, end;
- 	uint64_t addr;
-@@ -643,9 +642,10 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
- 	addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
- 	start += addr;
- 
--	ib = &ctx->parser->ibs[ctx->ib_idx];
--	ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
--	ib->ptr[ctx->data1] = start >> 32;
-+	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
-+			    lower_32_bits(start));
-+	amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
-+			    upper_32_bits(start));
- 
- 	cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
- 	if (cmd < 0x4) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index a96bfe1..d80e12c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -520,7 +520,6 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
- 			       int lo, int hi, unsigned size, uint32_t index)
- {
- 	struct amdgpu_bo_va_mapping *mapping;
--	struct amdgpu_ib *ib = &p->ibs[ib_idx];
- 	struct amdgpu_bo *bo;
- 	uint64_t addr;
- 
-@@ -549,8 +548,8 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
- 	addr += amdgpu_bo_gpu_offset(bo);
- 	addr -= ((uint64_t)size) * ((uint64_t)index);
- 
--	ib->ptr[lo] = addr & 0xFFFFFFFF;
--	ib->ptr[hi] = addr >> 32;
-+	amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
-+	amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0267-drm-amdgpu-separate-pushing-CS-to-scheduler.patch b/common/recipes-kernel/linux/files/0267-drm-amdgpu-separate-pushing-CS-to-scheduler.patch
deleted file mode 100644
index 74eca800..00000000
--- a/common/recipes-kernel/linux/files/0267-drm-amdgpu-separate-pushing-CS-to-scheduler.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From 1187d5c01ed4b93581713158f4c2aac0f8fc0611 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 31 Jan 2016 11:30:55 +0100
-Subject: [PATCH 0267/1110] drm/amdgpu: separate pushing CS to scheduler
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Move that out of the main IOCTL function.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 96 ++++++++++++++++++----------------
- 1 file changed, 50 insertions(+), 46 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index ddc8339..a344b16 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -809,6 +809,54 @@ static int amdgpu_cs_free_job(struct amdgpu_job *job)
- 	return 0;
- }
- 
-+static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
-+			    union drm_amdgpu_cs *cs)
-+{
-+	struct amdgpu_ring * ring = p->ibs->ring;
-+	struct amd_sched_fence *fence;
-+	struct amdgpu_job *job;
-+
-+	job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
-+	if (!job)
-+		return -ENOMEM;
-+
-+	job->base.sched = &ring->sched;
-+	job->base.s_entity = &p->ctx->rings[ring->idx].entity;
-+	job->adev = p->adev;
-+	job->owner = p->filp;
-+	job->free_job = amdgpu_cs_free_job;
-+
-+	job->ibs = p->ibs;
-+	job->num_ibs = p->num_ibs;
-+	p->ibs = NULL;
-+	p->num_ibs = 0;
-+
-+	if (job->ibs[job->num_ibs - 1].user) {
-+		job->uf = p->uf;
-+		job->ibs[job->num_ibs - 1].user = &job->uf;
-+		p->uf.bo = NULL;
-+	}
-+
-+	fence = amd_sched_fence_create(job->base.s_entity, p->filp);
-+	if (!fence) {
-+		amdgpu_cs_free_job(job);
-+		kfree(job);
-+		return -ENOMEM;
-+	}
-+
-+	job->base.s_fence = fence;
-+	p->fence = fence_get(&fence->base);
-+
-+	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring,
-+					      &fence->base);
-+	job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
-+
-+	trace_amdgpu_cs_ioctl(job);
-+	amd_sched_entity_push_job(&job->base);
-+
-+	return 0;
-+}
-+
- int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
-@@ -856,52 +904,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 	if (r)
- 		goto out;
- 
--	if (parser.num_ibs) {
--		struct amdgpu_ring * ring = parser.ibs->ring;
--		struct amd_sched_fence *fence;
--		struct amdgpu_job *job;
--
--		job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
--		if (!job) {
--			r = -ENOMEM;
--			goto out;
--		}
--
--		job->base.sched = &ring->sched;
--		job->base.s_entity = &parser.ctx->rings[ring->idx].entity;
--		job->adev = parser.adev;
--		job->owner = parser.filp;
--		job->free_job = amdgpu_cs_free_job;
--
--		job->ibs = parser.ibs;
--		job->num_ibs = parser.num_ibs;
--		parser.ibs = NULL;
--		parser.num_ibs = 0;
--
--		if (job->ibs[job->num_ibs - 1].user) {
--			job->uf = parser.uf;
--			job->ibs[job->num_ibs - 1].user = &job->uf;
--			parser.uf.bo = NULL;
--		}
--
--		fence = amd_sched_fence_create(job->base.s_entity,
--					       parser.filp);
--		if (!fence) {
--			r = -ENOMEM;
--			amdgpu_cs_free_job(job);
--			kfree(job);
--			goto out;
--		}
--		job->base.s_fence = fence;
--		parser.fence = fence_get(&fence->base);
--
--		cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring,
--						      &fence->base);
--		job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
--
--		trace_amdgpu_cs_ioctl(job);
--		amd_sched_entity_push_job(&job->base);
--	}
-+	if (parser.num_ibs)
-+		r = amdgpu_cs_submit(&parser, cs);
- 
- out:
- 	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0268-drm-amdgpu-gfx-minor-code-cleanup.patch b/common/recipes-kernel/linux/files/0268-drm-amdgpu-gfx-minor-code-cleanup.patch
deleted file mode 100644
index c713bace..00000000
--- a/common/recipes-kernel/linux/files/0268-drm-amdgpu-gfx-minor-code-cleanup.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From f7e14e1fbbcb72b09138da32ffe61b9b7d5f61a7 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 11:11:00 -0500
-Subject: [PATCH 0268/1110] drm/amdgpu/gfx: minor code cleanup
-
-Drop needless function wrapper.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 19 +------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +----------
- 2 files changed, 2 insertions(+), 28 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index bf0517d..e4a78ff 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -3096,21 +3096,6 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
- }
- 
- /**
-- * gfx_v7_0_cp_compute_start - start the compute queues
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Enable the compute queues.
-- * Returns 0 for success, error for failure.
-- */
--static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev)
--{
--	gfx_v7_0_cp_compute_enable(adev, true);
--
--	return 0;
--}
--
--/**
-  * gfx_v7_0_cp_compute_fini - stop the compute queues
-  *
-  * @adev: amdgpu_device pointer
-@@ -3300,9 +3285,7 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
- 	u32 *buf;
- 	struct bonaire_mqd *mqd;
- 
--	r = gfx_v7_0_cp_compute_start(adev);
--	if (r)
--		return r;
-+	gfx_v7_0_cp_compute_enable(adev, true);
- 
- 	/* fix up chicken bits */
- 	tmp = RREG32(mmCP_CPF_DEBUG);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 3a2b060..ab1159e 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3226,13 +3226,6 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
- 	udelay(50);
- }
- 
--static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
--{
--	gfx_v8_0_cp_compute_enable(adev, true);
--
--	return 0;
--}
--
- static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
- {
- 	const struct gfx_firmware_header_v1_0 *mec_hdr;
-@@ -3802,9 +3795,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- 		WREG32(mmCP_PQ_STATUS, tmp);
- 	}
- 
--	r = gfx_v8_0_cp_compute_start(adev);
--	if (r)
--		return r;
-+	gfx_v8_0_cp_compute_enable(adev, true);
- 
- 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
- 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0269-drm-amdgpu-check-userptrs-mm-earlier.patch b/common/recipes-kernel/linux/files/0269-drm-amdgpu-check-userptrs-mm-earlier.patch
deleted file mode 100644
index 41237a4f..00000000
--- a/common/recipes-kernel/linux/files/0269-drm-amdgpu-check-userptrs-mm-earlier.patch
+++ /dev/null
@@ -1,191 +0,0 @@
-From c0768582c76a463866bc22ac8768b04e6070ff2c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 8 Feb 2016 11:08:35 +0100
-Subject: [PATCH 0269/1110] drm/amdgpu: check userptrs mm earlier
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Instead of when we try to bind it check the usermm when
-we try to use it in the IOCTLs.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h         |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 17 +++++++++++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c      |  7 ++++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c     |  4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c     |  9 +++------
- 7 files changed, 27 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a48dbe7..473b447 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2330,7 +2330,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
- bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
- int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
- 				     uint32_t flags);
--bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
-+struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
- bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
- 				  unsigned long end);
- bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index 1c6c0ac..53b1ebf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -102,18 +102,27 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	for (i = 0; i < num_entries; ++i) {
- 		struct amdgpu_bo_list_entry *entry = &array[i];
- 		struct drm_gem_object *gobj;
-+                struct mm_struct *usermm;
- 
- 		gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
- 		if (!gobj)
-+                if (!gobj) {
-+                        r = -ENOENT;
- 			goto error_free;
-+                }
- 
- 		entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
- 		drm_gem_object_unreference_unlocked(gobj);
- 		entry->priority = min(info[i].bo_priority,
- 				      AMDGPU_BO_LIST_MAX_PRIORITY);
--                if (amdgpu_ttm_tt_has_userptr(entry->robj->tbo.ttm))
--			has_userptr = true;
--		}
-+                usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm);
-+                if (usermm) {
-+                        if (usermm != current->mm) {
-+                                r = -EPERM;
-+                                goto error_free;
-+                        }
-+                        has_userptr = true;
-+                }
- 		entry->tv.bo = &entry->robj->tbo;
- 		entry->tv.shared = true;
- 
-@@ -143,7 +152,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 
- error_free:
- 	drm_free_large(array);
--	return -ENOENT;
-+        return r;
- }
- 
- struct amdgpu_bo_list *
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index a344b16..bd9a0be 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -142,7 +142,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 	p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
- 	p->uf.offset = fence_data->offset;
- 
--	if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) {
-+        if (amdgpu_ttm_tt_get_usermm(p->uf.bo->tbo.ttm)) {
- 		drm_gem_object_unreference_unlocked(gobj);
- 		return -EINVAL;
- 	}
-@@ -342,8 +342,13 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 
- 	list_for_each_entry(lobj, validated, tv.head) {
-                 struct amdgpu_bo *bo = lobj->robj;
-+                struct mm_struct *usermm;
-                 uint32_t domain;
- 
-+                usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
-+                if (usermm && usermm != current->mm)
-+                        return -EPERM;
-+
-                 if (bo->pin_count)
-                         continue;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 95e12f4..2f56bc6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -310,7 +310,7 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp,
- 		return -ENOENT;
- 	}
- 	robj = gem_to_amdgpu_bo(gobj);
--	if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) ||
-+        if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
- 	    (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
- 		drm_gem_object_unreference_unlocked(gobj);
- 		return -EPERM;
-@@ -639,7 +639,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 		break;
- 	}
- 	case AMDGPU_GEM_OP_SET_PLACEMENT:
--		if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
-+                if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
- 			r = -EPERM;
- 			amdgpu_bo_unreserve(robj);
- 			break;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index b79a4f3..c884873 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -370,7 +370,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
- 	int r, i;
- 	unsigned fpfn, lpfn;
- 
--	if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm))
-+        if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
- 		return -EPERM;
- 
- 	if (WARN_ON_ONCE(min_offset > max_offset))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-index 59f735a..39db99a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-@@ -121,7 +121,7 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
- {
- 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
- 
--	if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm))
-+        if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
- 		return ERR_PTR(-EPERM);
- 
- 	return drm_gem_prime_export(dev, gobj, flags);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index f08d53f..a4f7182 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -499,9 +499,6 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
- 	enum dma_data_direction direction = write ?
- 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
- 
--	if (current->mm != gtt->usermm)
--		return -EPERM;
--
- 	if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
- 		/* check that we only pin down anonymous memory
- 		   to prevent problems with writeback */
-@@ -773,14 +770,14 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
- 	return 0;
- }
- 
--bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
-+struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
- {
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
- 
- 	if (gtt == NULL)
--		return false;
-+                return NULL;
- 
--	return !!gtt->userptr;
-+        return gtt->usermm;
- }
- 
- bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0270-drm-amdgpu-remove-adev-and-fence-from-amdgpu_sync_fr.patch b/common/recipes-kernel/linux/files/0270-drm-amdgpu-remove-adev-and-fence-from-amdgpu_sync_fr.patch
deleted file mode 100644
index 26732963..00000000
--- a/common/recipes-kernel/linux/files/0270-drm-amdgpu-remove-adev-and-fence-from-amdgpu_sync_fr.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From fc26c19008cd8d48631d3088ce310951fb529327 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 3 Feb 2016 15:11:39 +0100
-Subject: [PATCH 0270/1110] drm/amdgpu: remove adev and fence from
- amdgpu_sync_free
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just leftovers from the semaphores.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 3 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 6 +-----
- 3 files changed, 3 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 473b447..7be8689 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -604,8 +604,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     void *owner);
- struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
- int amdgpu_sync_wait(struct amdgpu_sync *sync);
--void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
--		      struct fence *fence);
-+void amdgpu_sync_free(struct amdgpu_sync *sync);
- 
- /*
-  * GART structures, functions & helpers
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 40c9779..d7cd408 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -93,7 +93,7 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
-  */
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
- {
--	amdgpu_sync_free(adev, &ib->sync, &ib->fence->base);
-+	amdgpu_sync_free(&ib->sync);
- 	amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base);
- 	if (ib->fence)
- 		fence_put(&ib->fence->base);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index 1d348f8..c15be00 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -240,15 +240,11 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
- /**
-  * amdgpu_sync_free - free the sync object
-  *
-- * @adev: amdgpu_device pointer
-  * @sync: sync object to use
-- * @fence: fence to use for the free
-  *
-  * Free the sync object.
-  */
--void amdgpu_sync_free(struct amdgpu_device *adev,
--		      struct amdgpu_sync *sync,
--		      struct fence *fence)
-+void amdgpu_sync_free(struct amdgpu_sync *sync)
- {
- 	struct amdgpu_sync_entry *e;
- 	struct hlist_node *tmp;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0271-drm-amdgpu-remove-AMDGPU_NUM_SYNCS.patch b/common/recipes-kernel/linux/files/0271-drm-amdgpu-remove-AMDGPU_NUM_SYNCS.patch
deleted file mode 100644
index 1ce614d5..00000000
--- a/common/recipes-kernel/linux/files/0271-drm-amdgpu-remove-AMDGPU_NUM_SYNCS.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From c7ae5f8fef765bd3b1f4c4b7b5316fd5643554f2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 3 Feb 2016 15:12:58 +0100
-Subject: [PATCH 0271/1110] drm/amdgpu: remove AMDGPU_NUM_SYNCS
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just a leftover from semaphores.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 3 ---
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
- 2 files changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 7be8689..e4f6069 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -106,9 +106,6 @@ extern unsigned amdgpu_pcie_lane_cap;
- /* max number of IP instances */
- #define AMDGPU_MAX_SDMA_INSTANCES		2
- 
--/* number of hw syncs before falling back on blocking */
--#define AMDGPU_NUM_SYNCS			4
--
- /* hardcode that limit for now */
- #define AMDGPU_VA_RESERVED_SIZE			(8 << 20)
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index d7cd408..b673770 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -147,7 +147,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 		return -EINVAL;
- 	}
- 
--	r = amdgpu_ring_alloc(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs);
-+	r = amdgpu_ring_alloc(ring, 256 * num_ibs);
- 	if (r) {
- 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
- 		return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0272-drm-amdgpu-fix-num_ibs-check.patch b/common/recipes-kernel/linux/files/0272-drm-amdgpu-fix-num_ibs-check.patch
deleted file mode 100644
index 85777ac6..00000000
--- a/common/recipes-kernel/linux/files/0272-drm-amdgpu-fix-num_ibs-check.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From cc71dc022223c5d6d06d75ff61f91a5a0958b5eb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 31 Jan 2016 11:32:04 +0100
-Subject: [PATCH 0272/1110] drm/amdgpu: fix num_ibs check
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Specifying no IBs on command submission is invalid, stop crashing
-badly when somebody tries it.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 +++++-----------
- 1 file changed, 5 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index bd9a0be..58e115a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -255,6 +255,10 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		}
- 	}
- 
-+        if (p->num_ibs == 0) {
-+                ret = -EINVAL;
-+                goto free_all_kdata;
-+        }
- 
- 	p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
- 	if (!p->ibs) {
-@@ -594,9 +598,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
- 	struct amdgpu_ring *ring;
- 	int i, r;
- 
--	if (parser->num_ibs == 0)
--		return 0;
--
- 	/* Only for UVD/VCE VM emulation */
- 	for (i = 0; i < parser->num_ibs; i++) {
- 		ring = parser->ibs[i].ring;
-@@ -703,9 +704,6 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		j++;
- 	}
- 
--	if (!parser->num_ibs)
--		return 0;
--
- 	/* add GDS resources to first IB */
- 	if (parser->bo_list) {
- 		struct amdgpu_bo *gds = parser->bo_list->gds_obj;
-@@ -748,9 +746,6 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 	struct amdgpu_ib *ib;
- 	int i, j, r;
- 
--	if (!p->num_ibs)
--		return 0;
--
- 	/* Add dependencies to first IB */
- 	ib = &p->ibs[0];
- 	for (i = 0; i < p->nchunks; ++i) {
-@@ -909,8 +904,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 	if (r)
- 		goto out;
- 
--	if (parser.num_ibs)
--		r = amdgpu_cs_submit(&parser, cs);
-+        r = amdgpu_cs_submit(&parser, cs);
- 
- out:
- 	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0273-drm-amdgpu-add-proper-job-alloc-free-functions.patch b/common/recipes-kernel/linux/files/0273-drm-amdgpu-add-proper-job-alloc-free-functions.patch
deleted file mode 100644
index fa77af5d..00000000
--- a/common/recipes-kernel/linux/files/0273-drm-amdgpu-add-proper-job-alloc-free-functions.patch
+++ /dev/null
@@ -1,362 +0,0 @@
-From 6a50fb95f903bb73e062477399a1170de608c35c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 3 Feb 2016 13:44:52 +0100
-Subject: [PATCH 0273/1110] drm/amdgpu: add proper job alloc/free functions
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-And use them in the CS instead of allocating IBs and jobs separately.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 14 ++++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c    | 63 +++++++++++--------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 33 ++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h |  4 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |  6 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c   |  2 +-
- 6 files changed, 69 insertions(+), 53 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e4f6069..1dbd2d7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -755,7 +755,9 @@ enum amdgpu_ring_type {
- };
- 
- extern struct amd_sched_backend_ops amdgpu_sched_ops;
--
-+int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-+                    struct amdgpu_job **job);
-+void amdgpu_job_free(struct amdgpu_job *job);
- int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
- 					 struct amdgpu_ring *ring,
- 					 struct amdgpu_ib *ibs,
-@@ -1181,9 +1183,9 @@ struct amdgpu_cs_parser {
- 	/* chunks */
- 	unsigned		nchunks;
- 	struct amdgpu_cs_chunk	*chunks;
--        /* indirect buffers */
--	uint32_t		num_ibs;
--	struct amdgpu_ib	*ibs;
-+
-+       /* scheduler job object */
-+        struct amdgpu_job       *job;
-  
-        /* buffer objects */
-          struct ww_acquire_ctx           ticket;
-@@ -1214,14 +1216,14 @@ struct amdgpu_job {
- static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
- 				      uint32_t ib_idx, int idx)
- {
--	return p->ibs[ib_idx].ptr[idx];
-+        return p->job->ibs[ib_idx].ptr[idx];
- }
- 
- static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
- 				       uint32_t ib_idx, int idx,
- 				       uint32_t value)
- {
--	p->ibs[ib_idx].ptr[idx] = value;
-+        p->job->ibs[ib_idx].ptr[idx] = value;
- }
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 58e115a..f1fd4ed 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -163,6 +163,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 	uint64_t *chunk_array;
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	unsigned size;
-+        unsigned size, num_ibs = 0;
- 	int i;
- 	int ret;
- 
-@@ -255,16 +256,9 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		}
- 	}
- 
--        if (p->num_ibs == 0) {
--                ret = -EINVAL;
-+        ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job);
-+        if (ret)
-                 goto free_all_kdata;
--        }
--
--	p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!p->ibs) {
--		ret = -ENOMEM;
--		goto free_all_kdata;
--	}
- 
- 	kfree(chunk_array);
- 	return 0;
-@@ -460,7 +454,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
- 
- 	list_for_each_entry(e, &p->validated, tv.head) {
- 		struct reservation_object *resv = e->robj->tbo.resv;
--		r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
-+                r = amdgpu_sync_resv(p->adev, &p->job->ibs[0].sync, resv, p->filp);
- 
- 		if (r)
- 			return r;
-@@ -520,10 +514,8 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
- 	for (i = 0; i < parser->nchunks; i++)
- 		drm_free_large(parser->chunks[i].kdata);
- 	kfree(parser->chunks);
--	if (parser->ibs)
--		for (i = 0; i < parser->num_ibs; i++)
--			amdgpu_ib_free(parser->adev, &parser->ibs[i]);
--	kfree(parser->ibs);
-+        if (parser->job)
-+                amdgpu_job_free(parser->job);
- 	amdgpu_bo_unref(&parser->uf.bo);
- 	amdgpu_bo_unref(&parser->uf_entry.robj);
- }
-@@ -540,7 +532,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- 	if (r)
- 		return r;
- 
--	r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
-+        r = amdgpu_sync_fence(adev, &p->job->ibs[0].sync, vm->page_directory_fence);
- 	if (r)
- 		return r;
- 
-@@ -566,14 +558,14 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- 				return r;
- 
- 			f = bo_va->last_pt_update;
--			r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
-+                        r = amdgpu_sync_fence(adev, &p->job->ibs[0].sync, f);
- 			if (r)
- 				return r;
- 		}
- 
- 	}
- 
--	r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
-+        r = amdgpu_vm_clear_invalids(adev, vm, &p->job->ibs[0].sync);
- 
- 	if (amdgpu_vm_debug && p->bo_list) {
- 		/* Invalidate all BOs to test for userspace bugs */
-@@ -599,8 +591,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
- 	int i, r;
- 
- 	/* Only for UVD/VCE VM emulation */
--	for (i = 0; i < parser->num_ibs; i++) {
--		ring = parser->ibs[i].ring;
-+        for (i = 0; i < parser->job->num_ibs; i++) {
-+                ring = parser->job->ibs[i].ring;
- 		if (ring->funcs->parse_cs) {
- 			r = amdgpu_ring_parse_cs(ring, parser, i);
- 			if (r)
-@@ -633,14 +625,14 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 	int i, j;
- 	int r;
- 
--	for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
-+        for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
- 		struct amdgpu_cs_chunk *chunk;
- 		struct amdgpu_ib *ib;
- 		struct drm_amdgpu_cs_chunk_ib *chunk_ib;
- 		struct amdgpu_ring *ring;
- 
- 		chunk = &parser->chunks[i];
--		ib = &parser->ibs[j];
-+                ib = &parser->job->ibs[j];
- 		chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
- 
- 		if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
-@@ -709,7 +701,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		struct amdgpu_bo *gds = parser->bo_list->gds_obj;
- 		struct amdgpu_bo *gws = parser->bo_list->gws_obj;
- 		struct amdgpu_bo *oa = parser->bo_list->oa_obj;
--		struct amdgpu_ib *ib = &parser->ibs[0];
-+                struct amdgpu_ib *ib = &parser->job->ibs[0];
- 
- 		if (gds) {
- 			ib->gds_base = amdgpu_bo_gpu_offset(gds);
-@@ -726,7 +718,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 	}
- 	/* wrap the last IB with user fence */
- 	if (parser->uf.bo) {
--		struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
-+                struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
- 
- 		/* UVD & VCE fw doesn't support user fences */
- 		if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
-@@ -747,7 +739,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 	int i, j, r;
- 
- 	/* Add dependencies to first IB */
--	ib = &p->ibs[0];
-+        ib = &p->job->ibs[0];
- 	for (i = 0; i < p->nchunks; ++i) {
- 		struct drm_amdgpu_cs_chunk_dep *deps;
- 		struct amdgpu_cs_chunk *chunk;
-@@ -799,26 +791,20 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 
- static int amdgpu_cs_free_job(struct amdgpu_job *job)
- {
--	int i;
--	if (job->ibs)
--		for (i = 0; i < job->num_ibs; i++)
--			amdgpu_ib_free(job->adev, &job->ibs[i]);
--	kfree(job->ibs);
--	if (job->uf.bo)
--		amdgpu_bo_unref(&job->uf.bo);
-+        amdgpu_job_free(job);
- 	return 0;
- }
- 
- static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 			    union drm_amdgpu_cs *cs)
- {
--	struct amdgpu_ring * ring = p->ibs->ring;
-+        struct amdgpu_ring * ring = p->job->ibs->ring;
- 	struct amd_sched_fence *fence;
- 	struct amdgpu_job *job;
- 
--	job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
--	if (!job)
--		return -ENOMEM;
-+        job = p->job;
-+        p->job = NULL;
-+
- 
- 	job->base.sched = &ring->sched;
- 	job->base.s_entity = &p->ctx->rings[ring->idx].entity;
-@@ -826,11 +812,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 	job->owner = p->filp;
- 	job->free_job = amdgpu_cs_free_job;
- 
--	job->ibs = p->ibs;
--	job->num_ibs = p->num_ibs;
--	p->ibs = NULL;
--	p->num_ibs = 0;
--
- 	if (job->ibs[job->num_ibs - 1].user) {
- 		job->uf = p->uf;
- 		job->ibs[job->num_ibs - 1].user = &job->uf;
-@@ -897,7 +878,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 	if (r)
- 		goto out;
- 
--	for (i = 0; i < parser.num_ibs; i++)
-+        for (i = 0; i < parser.job->num_ibs; i++)
- 		trace_amdgpu_cs(&parser, i);
- 
- 	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index 76a1f82..91b4862 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -28,6 +28,39 @@
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
-+int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-+                     struct amdgpu_job **job)
-+{
-+       size_t size = sizeof(struct amdgpu_job);
-+ 
-+        if (num_ibs == 0)
-+                return -EINVAL;
-+ 
-+        size += sizeof(struct amdgpu_ib) * num_ibs;
-+ 
-+        *job = kzalloc(size, GFP_KERNEL);
-+        if (!*job)
-+                return -ENOMEM;
-+ 
-+        (*job)->adev = adev;
-+        (*job)->ibs = (void *)&(*job)[1];
-+        (*job)->num_ibs = num_ibs;
-+        (*job)->free_job = NULL;
-+ 
-+        return 0;
-+}
-+
-+void amdgpu_job_free(struct amdgpu_job *job)
-+{
-+        unsigned i;
-+ 
-+        for (i = 0; i < job->num_ibs; ++i)
-+                amdgpu_ib_free(job->adev, &job->ibs[i]);
-+ 
-+        amdgpu_bo_unref(&job->uf.bo);
-+       /* TODO: Free the job structure here as well */
-+}
-+
- static struct fence *amdgpu_sched_dependency(struct amd_sched_job *sched_job)
- {
- 	struct amdgpu_job *job = to_amdgpu_job(sched_job);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-index e7d2676..9c15284 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-@@ -39,9 +39,9 @@ TRACE_EVENT(amdgpu_cs,
- 	    TP_fast_assign(
- 			   __entry->bo_list = p->bo_list;
- 			   __entry->ring = p->ibs[i].ring->idx;
--			   __entry->dw = p->ibs[i].length_dw;
-+                           __entry->dw = p->job->ibs[i].length_dw;
- 			   __entry->fences = amdgpu_fence_count_emitted(
--				p->ibs[i].ring);
-+                                p->job->ibs[i].ring);
- 			   ),
- 	    TP_printk("bo_list=%p, ring=%u, dw=%u, fences=%u",
- 		      __entry->bo_list, __entry->ring, __entry->dw,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 2a20b66..520ad02 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -707,7 +707,7 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
- static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
- 			     int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
- {
--	struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
-+        struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
- 	int i, r;
- 
- 	ctx->idx++;
-@@ -753,7 +753,7 @@ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
- static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
- 				 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
- {
--	struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
-+        struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
- 	int r;
- 
- 	for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
-@@ -795,7 +795,7 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
- 		[0x00000003]	=	2048,
- 		[0x00000004]	=	0xFFFFFFFF,
- 	};
--	struct amdgpu_ib *ib = &parser->ibs[ib_idx];
-+        struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
- 	int r;
- 
- 	if (ib->length_dw % 16) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index d80e12c..420b610 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -604,7 +604,7 @@ static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
-  */
- int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
- {
--	struct amdgpu_ib *ib = &p->ibs[ib_idx];
-+        struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
- 	unsigned fb_idx = 0, bs_idx = 0;
- 	int session_idx = -1;
- 	bool destroyed = false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0274-drm-amdgpu-cleanup-user-fence-handling-in-the-CS.patch b/common/recipes-kernel/linux/files/0274-drm-amdgpu-cleanup-user-fence-handling-in-the-CS.patch
deleted file mode 100644
index e67d7c58..00000000
--- a/common/recipes-kernel/linux/files/0274-drm-amdgpu-cleanup-user-fence-handling-in-the-CS.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From ff51765a186b834ac7459306ac2e8bede060dfeb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 1 Feb 2016 11:20:37 +0100
-Subject: [PATCH 0274/1110] drm/amdgpu: cleanup user fence handling in the CS
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Don't keep that around twice.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 28 +++++++++++++---------------
- 2 files changed, 13 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1dbd2d7..dba07d8 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1197,7 +1197,6 @@ struct amdgpu_cs_parser {
-          uint64_t                        bytes_moved;
- 
- 	/* user fence */
--	struct amdgpu_user_fence	uf;
- 	struct amdgpu_bo_list_entry	uf_entry;
- };
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index f1fd4ed..a4805aa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -128,6 +128,7 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
- }
- 
- static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
-+                                      struct amdgpu_user_fence *uf,
- 				      struct drm_amdgpu_cs_chunk_fence *fence_data)
- {
- 	struct drm_gem_object *gobj;
-@@ -139,15 +140,15 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 	if (gobj == NULL)
- 		return -EINVAL;
- 
--	p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
--	p->uf.offset = fence_data->offset;
-+        uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
-+        uf->offset = fence_data->offset;
- 
--        if (amdgpu_ttm_tt_get_usermm(p->uf.bo->tbo.ttm)) {
-+        if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) {
- 		drm_gem_object_unreference_unlocked(gobj);
- 		return -EINVAL;
- 	}
- 
--	p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo);
-+        p->uf_entry.robj = amdgpu_bo_ref(uf->bo);
- 	p->uf_entry.priority = 0;
- 	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
- 	p->uf_entry.tv.shared = true;
-@@ -158,10 +159,11 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 
- int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- {
-+        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	union drm_amdgpu_cs *cs = data;
- 	uint64_t *chunk_array_user;
- 	uint64_t *chunk_array;
--	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-+        struct amdgpu_user_fence uf = {};
- 	unsigned size;
-         unsigned size, num_ibs = 0;
- 	int i;
-@@ -241,7 +243,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 				goto free_partial_kdata;
- 			}
- 
--			ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata);
-+                        ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata);
- 			if (ret)
- 				goto free_partial_kdata;
- 
-@@ -260,6 +262,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
-         if (ret)
-                 goto free_all_kdata;
- 
-+        p->job->uf = uf;
-+
- 	kfree(chunk_array);
- 	return 0;
- 
-@@ -403,6 +407,7 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
-         INIT_LIST_HEAD(&duplicates);
-         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
- 
-+        if (p->job->uf.bo)
- 		list_add(&p->uf_entry.tv.head, &p->validated);
- 
- 	if (need_mmap_lock)
-@@ -516,7 +521,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
- 	kfree(parser->chunks);
-         if (parser->job)
-                 amdgpu_job_free(parser->job);
--	amdgpu_bo_unref(&parser->uf.bo);
- 	amdgpu_bo_unref(&parser->uf_entry.robj);
- }
- 
-@@ -717,7 +721,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		}
- 	}
- 	/* wrap the last IB with user fence */
--	if (parser->uf.bo) {
-+        if (parser->job->uf.bo) {
-                 struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
- 
- 		/* UVD & VCE fw doesn't support user fences */
-@@ -725,7 +729,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		    ib->ring->type == AMDGPU_RING_TYPE_VCE)
- 			return -EINVAL;
- 
--		ib->user = &parser->uf;
-+                ib->user = &parser->job->uf;
- 	}
- 
- 	return 0;
-@@ -812,12 +816,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 	job->owner = p->filp;
- 	job->free_job = amdgpu_cs_free_job;
- 
--	if (job->ibs[job->num_ibs - 1].user) {
--		job->uf = p->uf;
--		job->ibs[job->num_ibs - 1].user = &job->uf;
--		p->uf.bo = NULL;
--	}
--
- 	fence = amd_sched_fence_create(job->base.s_entity, p->filp);
- 	if (!fence) {
- 		amdgpu_cs_free_job(job);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0275-drm-amdgpu-make-pad_ib-a-ring-function-v3.patch b/common/recipes-kernel/linux/files/0275-drm-amdgpu-make-pad_ib-a-ring-function-v3.patch
deleted file mode 100644
index d5658c7d..00000000
--- a/common/recipes-kernel/linux/files/0275-drm-amdgpu-make-pad_ib-a-ring-function-v3.patch
+++ /dev/null
@@ -1,360 +0,0 @@
-From 8a1e15e2e173cbce8f95c6d0703856136493fc4f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 31 Jan 2016 12:20:55 +0100
-Subject: [PATCH 0275/1110] drm/amdgpu: make pad_ib a ring function v3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The padding depends on the firmware version and we need that for BO moves as
-well, not only for VM updates.
-
-v2: new approach of making pad_ib a ring function
-v3: fix typo in macro name
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  7 ++++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 13 +++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  6 +++---
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c    |  6 +++---
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    |  2 ++
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    |  2 ++
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   |  8 ++++----
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   |  8 ++++----
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |  1 +
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |  1 +
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |  1 +
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    |  1 +
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    |  1 +
- 14 files changed, 41 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index dba07d8..49d3c33 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -250,8 +250,6 @@ struct amdgpu_vm_pte_funcs {
- 			    uint64_t pe,
- 			    uint64_t addr, unsigned count,
- 			    uint32_t incr, uint32_t flags);
--	/* pad the indirect buffer to the necessary number of dw */
--	void (*pad_ib)(struct amdgpu_ib *ib);
- };
- 
- /* provided by the gmc block */
-@@ -301,6 +299,8 @@ struct amdgpu_ring_funcs {
- 	int (*test_ib)(struct amdgpu_ring *ring);
- 	/* insert NOP packets */
- 	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
-+	/* pad the indirect buffer to the necessary number of dw */
-+	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
- };
- 
- /*
-@@ -1153,6 +1153,7 @@ void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
- int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
- int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
- void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
-+void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
- void amdgpu_ring_commit(struct amdgpu_ring *ring);
- void amdgpu_ring_undo(struct amdgpu_ring *ring);
- unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
-@@ -2190,7 +2191,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
- #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
- #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
--#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
- #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
- #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
- #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
-@@ -2202,6 +2202,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
- #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
- #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
-+#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
- #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
- #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
- #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 1f0db99..56c07e3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -90,6 +90,19 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
- 		amdgpu_ring_write(ring, ring->nop);
- }
- 
-+/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
-+ *
-+ * @ring: amdgpu_ring structure holding ring information
-+ * @ib: IB to add NOP packets to
-+ *
-+ * This is the generic pad_ib function for rings except SDMA
-+ */
-+void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
-+{
-+	while (ib->length_dw & ring->align_mask)
-+		ib->ptr[ib->length_dw++] = ring->nop;
-+}
-+
- /**
-  * amdgpu_ring_commit - tell the GPU to execute the new
-  * commands on the ring buffer
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index a4f7182..4a32bdd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -1058,7 +1058,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 		byte_count -= cur_size_in_bytes;
- 	}
- 
--	amdgpu_vm_pad_ib(adev, ib);
-+	amdgpu_ring_pad_ib(ring, ib);
- 	WARN_ON(ib->length_dw > num_dw);
- 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
- 						 &amdgpu_vm_free_job,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 6512386..3487a11 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -369,7 +369,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	ib->length_dw = 0;
- 
- 	amdgpu_vm_update_pages(adev, NULL, 0, ib, addr, 0, entries, 0, 0);
--	amdgpu_vm_pad_ib(adev, ib);
-+        amdgpu_ring_pad_ib(ring, ib);
- 
- 	WARN_ON(ib->length_dw > 64);
- 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
-@@ -499,7 +499,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				       count, incr, AMDGPU_PTE_VALID);
- 
- 	if (ib->length_dw != 0) {
--		amdgpu_vm_pad_ib(adev, ib);
-+                amdgpu_ring_pad_ib(ring, ib);
- 		amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
- 		WARN_ON(ib->length_dw > ndw);
- 		r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
-@@ -768,7 +768,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
-         amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1,
-                               addr, flags);
- 
--	amdgpu_vm_pad_ib(adev, ib);
-+        amdgpu_ring_pad_ib(ring, ib);
- 	WARN_ON(ib->length_dw > ndw);
- 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
- 						 &amdgpu_vm_free_job,
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 0602279..0608326 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -796,9 +796,9 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
-  * @ib: indirect buffer to fill with padding
-  *
-  */
--static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
-+static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
- {
--	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
-+	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
- 	u32 pad_count;
- 	int i;
- 
-@@ -1271,6 +1271,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
- 	.test_ring = cik_sdma_ring_test_ring,
- 	.test_ib = cik_sdma_ring_test_ib,
- 	.insert_nop = cik_sdma_ring_insert_nop,
-+	.pad_ib = cik_sdma_ring_pad_ib,
- };
- 
- static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
-@@ -1367,7 +1368,6 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
- 	.copy_pte = cik_sdma_vm_copy_pte,
- 	.write_pte = cik_sdma_vm_write_pte,
- 	.set_pte_pde = cik_sdma_vm_set_pte_pde,
--	.pad_ib = cik_sdma_vm_pad_ib,
- };
- 
- static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index e4a78ff..148311e 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -5539,6 +5539,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
- 	.test_ring = gfx_v7_0_ring_test_ring,
- 	.test_ib = gfx_v7_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
-@@ -5554,6 +5555,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
- 	.test_ring = gfx_v7_0_ring_test_ring,
- 	.test_ib = gfx_v7_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index ab1159e..2b69a15 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -5105,6 +5105,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
- 	.test_ring = gfx_v8_0_ring_test_ring,
- 	.test_ib = gfx_v8_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
-@@ -5120,6 +5121,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
- 	.test_ring = gfx_v8_0_ring_test_ring,
- 	.test_ib = gfx_v8_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 0843f81..fc53db9 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -849,14 +849,14 @@ static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
- }
- 
- /**
-- * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
-+ * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
-  *
-  * @ib: indirect buffer to fill with padding
-  *
-  */
--static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
-+static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
- {
--	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
-+	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
- 	u32 pad_count;
- 	int i;
- 
-@@ -1275,6 +1275,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
- 	.test_ring = sdma_v2_4_ring_test_ring,
- 	.test_ib = sdma_v2_4_ring_test_ib,
- 	.insert_nop = sdma_v2_4_ring_insert_nop,
-+	.pad_ib = sdma_v2_4_ring_pad_ib,
- };
- 
- static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
-@@ -1372,7 +1373,6 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
- 	.copy_pte = sdma_v2_4_vm_copy_pte,
- 	.write_pte = sdma_v2_4_vm_write_pte,
- 	.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
--	.pad_ib = sdma_v2_4_vm_pad_ib,
- };
- 
- static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 7af4b57..999a169 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -999,14 +999,14 @@ static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
- }
- 
- /**
-- * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
-+ * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
-  *
-  * @ib: indirect buffer to fill with padding
-  *
-  */
--static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
-+static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
- {
--	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
-+	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
- 	u32 pad_count;
- 	int i;
- 
-@@ -1542,6 +1542,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
- 	.test_ring = sdma_v3_0_ring_test_ring,
- 	.test_ib = sdma_v3_0_ring_test_ib,
- 	.insert_nop = sdma_v3_0_ring_insert_nop,
-+	.pad_ib = sdma_v3_0_ring_pad_ib,
- };
- 
- static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
-@@ -1639,7 +1640,6 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
- 	.copy_pte = sdma_v3_0_vm_copy_pte,
- 	.write_pte = sdma_v3_0_vm_write_pte,
- 	.set_pte_pde = sdma_v3_0_vm_set_pte_pde,
--	.pad_ib = sdma_v3_0_vm_pad_ib,
- };
- 
- static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index 5ef96d6..91080a5 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -864,6 +864,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
- 	.test_ring = uvd_v4_2_ring_test_ring,
- 	.test_ib = uvd_v4_2_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 7d67772..1e8476a 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -805,6 +805,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
- 	.test_ring = uvd_v5_0_ring_test_ring,
- 	.test_ib = uvd_v5_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 2ef8150..e55b040 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -1041,6 +1041,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
- 	.test_ring = uvd_v6_0_ring_test_ring,
- 	.test_ib = uvd_v6_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index a4bfee2..c7e885b 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -645,6 +645,7 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
- 	.test_ring = amdgpu_vce_ring_test_ring,
- 	.test_ib = amdgpu_vce_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index c438c7e..ce468ee 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -765,6 +765,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
- 	.test_ring = amdgpu_vce_ring_test_ring,
- 	.test_ib = amdgpu_vce_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
- };
- 
- static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0276-drm-amdgpu-move-ring-from-IBs-into-job.patch b/common/recipes-kernel/linux/files/0276-drm-amdgpu-move-ring-from-IBs-into-job.patch
deleted file mode 100644
index a245857f..00000000
--- a/common/recipes-kernel/linux/files/0276-drm-amdgpu-move-ring-from-IBs-into-job.patch
+++ /dev/null
@@ -1,439 +0,0 @@
-From 7e425890bf4b71763f8603e26c8e94438804a4cf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 31 Jan 2016 12:29:04 +0100
-Subject: [PATCH 0276/1110] drm/amdgpu: move ring from IBs into job
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We can't submit to multiple rings at the same time anyway.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c    | 35 ++++++++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c    | 11 ++++------
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c |  5 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h |  8 +++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c   |  4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  6 +++---
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c     |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c     |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c     |  4 ++--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c    |  2 +-
- 14 files changed, 47 insertions(+), 44 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 49d3c33..ea4e3aa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -731,7 +731,6 @@ struct amdgpu_ib {
- 	uint32_t			length_dw;
- 	uint64_t			gpu_addr;
- 	uint32_t			*ptr;
--	struct amdgpu_ring		*ring;
- 	struct amdgpu_fence		*fence;
- 	struct amdgpu_user_fence        *user;
- 	bool				grabbed_vmid;
-@@ -1143,10 +1142,10 @@ struct amdgpu_gfx {
- 	unsigned ce_ram_size;
- };
- 
--int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
-+int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 		  unsigned size, struct amdgpu_ib *ib);
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
--int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
-+int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		       struct amdgpu_ib *ib, void *owner);
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
- void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
-@@ -1204,6 +1203,7 @@ struct amdgpu_cs_parser {
- struct amdgpu_job {
- 	struct amd_sched_job    base;
- 	struct amdgpu_device	*adev;
-+        struct amdgpu_ring      *ring;
- 	struct amdgpu_ib	*ibs;
- 	uint32_t		num_ibs;
- 	void			*owner;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index a4805aa..45ba532 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -587,26 +587,26 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- }
- 
- static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
--				 struct amdgpu_cs_parser *parser)
-+                                 struct amdgpu_cs_parser *p)
- {
--	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
-+        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	struct amdgpu_vm *vm = &fpriv->vm;
--	struct amdgpu_ring *ring;
-+        struct amdgpu_ring *ring = p->job->ring;
- 	int i, r;
- 
- 	/* Only for UVD/VCE VM emulation */
--        for (i = 0; i < parser->job->num_ibs; i++) {
--                ring = parser->job->ibs[i].ring;
--		if (ring->funcs->parse_cs) {
--			r = amdgpu_ring_parse_cs(ring, parser, i);
-+        if (ring->funcs->parse_cs) {
-+                for (i = 0; i < p->job->num_ibs; i++) {
-+                        r = amdgpu_ring_parse_cs(ring, p, i);
-+
- 			if (r)
- 				return r;
- 		}
- 	}
- 
--	r = amdgpu_bo_vm_update_pte(parser, vm);
-+        r = amdgpu_bo_vm_update_pte(p, vm);
- 	if (!r)
--		amdgpu_cs_sync_rings(parser);
-+                amdgpu_cs_sync_rings(p);
- 
- 	return r;
- }
-@@ -648,6 +648,11 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		if (r)
- 			return r;
- 
-+                if (parser->job->ring && parser->job->ring != ring)
-+                        return -EINVAL;
-+ 
-+                parser->job->ring = ring;
-+
- 		if (ring->funcs->parse_cs) {
- 			struct amdgpu_bo_va_mapping *m;
- 			struct amdgpu_bo *aobj = NULL;
-@@ -676,7 +681,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 			offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
- 			kptr += chunk_ib->va_start - offset;
- 
--			r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
-+                        r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
- 			if (r) {
- 				DRM_ERROR("Failed to get ib !\n");
- 				return r;
-@@ -685,7 +690,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
- 			amdgpu_bo_kunmap(aobj);
- 		} else {
--			r =  amdgpu_ib_get(ring, vm, 0, ib);
-+                        r =  amdgpu_ib_get(adev, vm, 0, ib);
- 			if (r) {
- 				DRM_ERROR("Failed to get ib !\n");
- 				return r;
-@@ -725,8 +730,9 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
-                 struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
- 
- 		/* UVD & VCE fw doesn't support user fences */
--		if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
--		    ib->ring->type == AMDGPU_RING_TYPE_VCE)
-+                if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
-+                    parser->job->ring->type == AMDGPU_RING_TYPE_VCE)
-+
- 			return -EINVAL;
- 
-                 ib->user = &parser->job->uf;
-@@ -802,7 +808,7 @@ static int amdgpu_cs_free_job(struct amdgpu_job *job)
- static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 			    union drm_amdgpu_cs *cs)
- {
--        struct amdgpu_ring * ring = p->job->ibs->ring;
-+        struct amdgpu_ring *ring = p->job->ring;
- 	struct amd_sched_fence *fence;
- 	struct amdgpu_job *job;
- 
-@@ -812,7 +818,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 
- 	job->base.sched = &ring->sched;
- 	job->base.s_entity = &p->ctx->rings[ring->idx].entity;
--	job->adev = p->adev;
- 	job->owner = p->filp;
- 	job->free_job = amdgpu_cs_free_job;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index b673770..640ff53 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -55,10 +55,9 @@ static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
-  * suballocator.
-  * Returns 0 on success, error on failure.
-  */
--int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
-+int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 		  unsigned size, struct amdgpu_ib *ib)
- {
--	struct amdgpu_device *adev = ring->adev;
- 	int r;
- 
- 	if (size) {
-@@ -77,7 +76,6 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
- 
- 	amdgpu_sync_create(&ib->sync);
- 
--	ib->ring = ring;
- 	ib->vm = vm;
- 
- 	return 0;
-@@ -120,11 +118,11 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
-  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
-  * to SI there was just a DE IB.
-  */
--int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
-+int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		       struct amdgpu_ib *ibs, void *owner)
- {
-+        struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_ib *ib = &ibs[0];
--	struct amdgpu_ring *ring;
- 	struct amdgpu_ctx *ctx, *old_ctx;
- 	struct amdgpu_vm *vm;
- 	unsigned i;
-@@ -133,7 +131,6 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 	if (num_ibs == 0)
- 		return -EINVAL;
- 
--	ring = ibs->ring;
- 	ctx = ibs->ctx;
- 	vm = ibs->vm;
- 
-@@ -178,7 +175,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
- 	for (i = 0; i < num_ibs; ++i) {
- 		ib = &ibs[i];
- 
--		if (ib->ring != ring || ib->ctx != ctx || ib->vm != vm) {
-+                if (ib->ctx != ctx || ib->vm != vm) {
- 			ring->current_ctx = old_ctx;
- 			amdgpu_ring_undo(ring);
- 			return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index 91b4862..7c03d4a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -70,7 +70,7 @@ static struct fence *amdgpu_sched_dependency(struct amd_sched_job *sched_job)
- 	struct fence *fence = amdgpu_sync_get_fence(sync);
- 
- 	if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
--		struct amdgpu_ring *ring = job->ibs->ring;
-+                struct amdgpu_ring *ring = job->ring;
- 		int r;
- 
- 		r = amdgpu_vm_grab_id(vm, ring, sync,
-@@ -98,7 +98,7 @@ static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job)
- 	}
- 	job = to_amdgpu_job(sched_job);
- 	trace_amdgpu_sched_run_job(job);
--	r = amdgpu_ib_schedule(job->adev, job->num_ibs, job->ibs, job->owner);
-+        r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job->owner);
- 	if (r) {
- 		DRM_ERROR("Error scheduling IBs (%d)\n", r);
- 		goto err;
-@@ -142,6 +142,7 @@ int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
- 	*f = fence_get(&job->base.s_fence->base);
- 
- 	job->adev = adev;
-+        job->ring = ring;
- 	job->ibs = ibs;
- 	job->num_ibs = num_ibs;
- 	job->owner = owner;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-index 9c15284..0254425 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-@@ -38,10 +38,10 @@ TRACE_EVENT(amdgpu_cs,
- 
- 	    TP_fast_assign(
- 			   __entry->bo_list = p->bo_list;
--			   __entry->ring = p->ibs[i].ring->idx;
-+                           __entry->ring = p->job->ring->idx;
-                            __entry->dw = p->job->ibs[i].length_dw;
- 			   __entry->fences = amdgpu_fence_count_emitted(
--                                p->job->ibs[i].ring);
-+                                p->job->ring);
- 			   ),
- 	    TP_printk("bo_list=%p, ring=%u, dw=%u, fences=%u",
- 		      __entry->bo_list, __entry->ring, __entry->dw,
-@@ -65,7 +65,7 @@ TRACE_EVENT(amdgpu_cs_ioctl,
- 			   __entry->sched_job = &job->base;
- 			   __entry->ib = job->ibs;
- 			   __entry->fence = &job->base.s_fence->base;
--			   __entry->ring_name = job->ibs[0].ring->name;
-+                           __entry->ring_name = job->ring->name;
- 			   __entry->num_ibs = job->num_ibs;
- 			   ),
- 	    TP_printk("adev=%p, sched_job=%p, first ib=%p, sched fence=%p, ring name:%s, num_ibs:%u",
-@@ -90,7 +90,7 @@ TRACE_EVENT(amdgpu_sched_run_job,
- 			   __entry->sched_job = &job->base;
- 			   __entry->ib = job->ibs;
- 			   __entry->fence = &job->base.s_fence->base;
--			   __entry->ring_name = job->ibs[0].ring->name;
-+                           __entry->ring_name = job->ring->name;
- 			   __entry->num_ibs = job->num_ibs;
- 			   ),
- 	    TP_printk("adev=%p, sched_job=%p, first ib=%p, sched fence=%p, ring name:%s, num_ibs:%u",
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 4a32bdd..df5ecc2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -1030,7 +1030,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	if (!ib)
- 		return -ENOMEM;
- 
--	r = amdgpu_ib_get(ring, NULL, num_dw * 4, ib);
-+        r = amdgpu_ib_get(adev, NULL, num_dw * 4, ib);
- 	if (r) {
- 		kfree(ib);
- 		return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 520ad02..35aa5a2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -872,7 +872,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
- 		r = -ENOMEM;
- 		goto err;
- 	}
--	r = amdgpu_ib_get(ring, NULL, 64, ib);
-+        r = amdgpu_ib_get(adev, NULL, 64, ib);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 420b610..26cc9e4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -378,7 +378,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
- 	if (!ib)
- 		return -ENOMEM;
--	r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
-+        r = amdgpu_ib_get(adev, NULL, ib_size_dw * 4, ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		kfree(ib);
-@@ -464,7 +464,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	if (!ib)
- 		return -ENOMEM;
- 
--	r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
-+        r = amdgpu_ib_get(adev, NULL, ib_size_dw * 4, ib);
- 	if (r) {
- 		kfree(ib);
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 3487a11..ec9c967 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -362,7 +362,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	if (!ib)
- 		goto error;
- 
--	r = amdgpu_ib_get(ring, NULL, 64, ib);
-+        r = amdgpu_ib_get(adev, NULL, 64, ib);
- 	if (r)
- 		goto error_free;
- 
-@@ -455,7 +455,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 	if (!ib)
- 		return -ENOMEM;
- 
--	r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
-+        r = amdgpu_ib_get(adev, NULL, ndw * 4, ib);
- 	if (r) {
- 		kfree(ib);
- 		return r;
-@@ -749,7 +749,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	if (!ib)
- 		return -ENOMEM;
- 
--	r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
-+        r = amdgpu_ib_get(adev, NULL, ndw * 4, ib);
- 	if (r) {
- 		kfree(ib);
- 		return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 0608326..1309d3e 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -621,7 +621,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 	memset(&ib, 0, sizeof(ib));
--	r = amdgpu_ib_get(ring, NULL, 256, &ib);
-+        r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 148311e..0a2fb19 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2631,7 +2631,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	}
- 	WREG32(scratch, 0xCAFEDEAD);
- 	memset(&ib, 0, sizeof(ib));
--	r = amdgpu_ib_get(ring, NULL, 256, &ib);
-+        r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err1;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 2b69a15..98d9186 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -699,7 +699,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	}
- 	WREG32(scratch, 0xCAFEDEAD);
- 	memset(&ib, 0, sizeof(ib));
--	r = amdgpu_ib_get(ring, NULL, 256, &ib);
-+        r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err1;
-@@ -1171,7 +1171,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 
- 	/* allocate an indirect buffer to put the commands in */
- 	memset(&ib, 0, sizeof(ib));
--	r = amdgpu_ib_get(ring, NULL, total_size, &ib);
-+        r = amdgpu_ib_get(adev, NULL, total_size, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index fc53db9..32bb31a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -674,7 +674,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 	memset(&ib, 0, sizeof(ib));
--	r = amdgpu_ib_get(ring, NULL, 256, &ib);
-+        r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 999a169..fe18e85 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -825,7 +825,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 	memset(&ib, 0, sizeof(ib));
--	r = amdgpu_ib_get(ring, NULL, 256, &ib);
-+        r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0277-drm-amdgpu-directly-return-fence-from-ib_schedule.patch b/common/recipes-kernel/linux/files/0277-drm-amdgpu-directly-return-fence-from-ib_schedule.patch
deleted file mode 100644
index 8bd70e75..00000000
--- a/common/recipes-kernel/linux/files/0277-drm-amdgpu-directly-return-fence-from-ib_schedule.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 3d4074df8e41c5e3abf277a778888bf99e20fec8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 1 Feb 2016 11:56:35 +0100
-Subject: [PATCH 0277/1110] drm/amdgpu: directly return fence from ib_schedule
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index 7c03d4a..e699b06 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -98,21 +98,19 @@ static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job)
- 	}
- 	job = to_amdgpu_job(sched_job);
- 	trace_amdgpu_sched_run_job(job);
--        r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job->owner);
-+        r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
-+                               job->owner, &fence);
- 	if (r) {
- 		DRM_ERROR("Error scheduling IBs (%d)\n", r);
- 		goto err;
- 	}
- 
--	fence = job->ibs[job->num_ibs - 1].fence;
--	fence_get(&fence->base);
--
- err:
- 	if (job->free_job)
- 		job->free_job(job);
- 
- 	kfree(job);
--	return fence ? &fence->base : NULL;
-+        return fence;
- }
- 
- struct amd_sched_backend_ops amdgpu_sched_ops = {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0278-drm-amdgpu-send-SDMA-GFX-IB-tests-directly-to-the-ri.patch b/common/recipes-kernel/linux/files/0278-drm-amdgpu-send-SDMA-GFX-IB-tests-directly-to-the-ri.patch
deleted file mode 100644
index 26c1ffb3..00000000
--- a/common/recipes-kernel/linux/files/0278-drm-amdgpu-send-SDMA-GFX-IB-tests-directly-to-the-ri.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-From 11dcdc2e90be14d479c7052182c81d26eb67df69 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 1 Feb 2016 12:02:08 +0100
-Subject: [PATCH 0278/1110] drm/amdgpu: send SDMA/GFX IB tests directly to the
- ring again
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There is no point in sending them through the scheduler.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 4 +---
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 4 +---
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 8 ++------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +---
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +---
- 5 files changed, 6 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 1309d3e..60c5d35 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -633,9 +633,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[3] = 1;
- 	ib.ptr[4] = 0xDEADBEEF;
- 	ib.length_dw = 5;
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 0a2fb19..90bff8c 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2641,9 +2641,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- 	if (r)
- 		goto err2;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 98d9186..ffc9b0a 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -709,9 +709,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- 	if (r)
- 		goto err2;
- 
-@@ -1266,9 +1264,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
- 
- 	/* shedule the ib on the ring */
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
- 		goto fail;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 32bb31a..9b29c2a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -691,9 +691,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index fe18e85..17f9acd 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -842,9 +842,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- 	if (r)
- 		goto err1;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0279-drm-amdgpu-cleanup-in-kernel-job-submission.patch b/common/recipes-kernel/linux/files/0279-drm-amdgpu-cleanup-in-kernel-job-submission.patch
deleted file mode 100644
index 2bdc99f3..00000000
--- a/common/recipes-kernel/linux/files/0279-drm-amdgpu-cleanup-in-kernel-job-submission.patch
+++ /dev/null
@@ -1,253 +0,0 @@
-From 1eb0d8b2eedbd3da3fd627010743cab953537ef1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 1 Feb 2016 12:20:25 +0100
-Subject: [PATCH 0279/1110] drm/amdgpu: cleanup in kernel job submission
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add a job_alloc_with_ib helper and proper job submission.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 16 ++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 90 ++++++++++------------------------
- 2 files changed, 30 insertions(+), 76 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index ea4e3aa..0e63bd3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -754,16 +754,12 @@ enum amdgpu_ring_type {
- };
- 
- extern struct amd_sched_backend_ops amdgpu_sched_ops;
--int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--                    struct amdgpu_job **job);
-+int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
-+                             struct amdgpu_job **job);
-+
- void amdgpu_job_free(struct amdgpu_job *job);
--int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
--					 struct amdgpu_ring *ring,
--					 struct amdgpu_ib *ibs,
--					 unsigned num_ibs,
--					 int (*free_job)(struct amdgpu_job *),
--					 void *owner,
--					 struct fence **fence);
-+int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-+                      void *owner, struct fence **f);
- 
- struct amdgpu_ring {
- 	struct amdgpu_device		*adev;
-@@ -954,7 +950,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
- 		       uint64_t addr);
- void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
- 		      struct amdgpu_bo_va *bo_va);
--int amdgpu_vm_free_job(struct amdgpu_job *job);
- 
- /*
-  * context related structures
-@@ -1208,7 +1203,6 @@ struct amdgpu_job {
- 	uint32_t		num_ibs;
- 	void			*owner;
- 	struct amdgpu_user_fence uf;
--	int (*free_job)(struct amdgpu_job *job);
- };
- #define to_amdgpu_job(sched_job)		\
- 		container_of((sched_job), struct amdgpu_job, base)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index ec9c967..e65f4a9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -320,15 +320,6 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
- 	}
- }
- 
--int amdgpu_vm_free_job(struct amdgpu_job *job)
--{
--	int i;
--	for (i = 0; i < job->num_ibs; i++)
--		amdgpu_ib_free(job->adev, &job->ibs[i]);
--	kfree(job->ibs);
--	return 0;
--}
--
- /**
-  * amdgpu_vm_clear_bo - initially clear the page dir/table
-  *
-@@ -342,7 +333,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- {
- 	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	struct fence *fence = NULL;
--	struct amdgpu_ib *ib;
-+        struct amdgpu_job *job;
- 	unsigned entries;
- 	uint64_t addr;
- 	int r;
-@@ -358,33 +349,24 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	addr = amdgpu_bo_gpu_offset(bo);
- 	entries = amdgpu_bo_size(bo) / 8;
- 
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib)
-+        r = amdgpu_job_alloc_with_ib(adev, 64, &job);
-+        if (r)
- 		goto error;
-+        amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries,
-+                                0, 0);
-+        amdgpu_ring_pad_ib(ring, &job->ibs[0]);
- 
--        r = amdgpu_ib_get(adev, NULL, 64, ib);
-+        WARN_ON(job->ibs[0].length_dw > 64);
-+        r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &fence);
- 	if (r)
- 		goto error_free;
- 
--	ib->length_dw = 0;
--
--	amdgpu_vm_update_pages(adev, NULL, 0, ib, addr, 0, entries, 0, 0);
--        amdgpu_ring_pad_ib(ring, ib);
--
--	WARN_ON(ib->length_dw > 64);
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--						 &amdgpu_vm_free_job,
--						 AMDGPU_FENCE_OWNER_VM,
--						 &fence);
--	if (!r)
--		amdgpu_bo_fence(bo, fence, true);
-+        amdgpu_bo_fence(bo, fence, true)
- 	fence_put(fence);
- 	return 0;
- 
- error_free:
--	amdgpu_ib_free(adev, ib);
--	kfree(ib);
--
-+        amdgpu_job_free(job);
- error:
- 	return r;
- }
-@@ -440,6 +422,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 	uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
- 	uint64_t last_pde = ~0, last_pt = ~0;
- 	unsigned count = 0, pt_idx, ndw;
-+        struct amdgpu_job *job;
- 	struct amdgpu_ib *ib;
- 	struct fence *fence = NULL;
- 
-@@ -450,18 +433,11 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 
- 	/* assume the worst case */
- 	ndw += vm->max_pde_used * 6;
--
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib)
--		return -ENOMEM;
--
--        r = amdgpu_ib_get(adev, NULL, ndw * 4, ib);
--	if (r) {
--		kfree(ib);
-+        r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
-+        if (r)
- 		return r;
--	}
--	ib->length_dw = 0;
- 
-+        ib = &job->ibs[0];
- 	/* walk over the address space and update the page directory */
- 	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
-                 struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
-@@ -502,10 +478,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-                 amdgpu_ring_pad_ib(ring, ib);
- 		amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
- 		WARN_ON(ib->length_dw > ndw);
--		r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--							 &amdgpu_vm_free_job,
--							 AMDGPU_FENCE_OWNER_VM,
--							 &fence);
-+                r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &fence);
- 		if (r)
- 			goto error_free;
- 
-@@ -513,18 +486,13 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 		fence_put(vm->page_directory_fence);
- 		vm->page_directory_fence = fence_get(fence);
- 		fence_put(fence);
--	}
--
--	if (ib->length_dw == 0) {
--		amdgpu_ib_free(adev, ib);
--		kfree(ib);
--	}
-+        } else {
-+                amdgpu_job_free(job);
- 
- 	return 0;
- 
- error_free:
--	amdgpu_ib_free(adev, ib);
--	kfree(ib);
-+        amdgpu_job_free(job);
- 	return r;
- }
- 
-@@ -707,6 +675,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
-         void *owner = AMDGPU_FENCE_OWNER_VM;
- 	unsigned nptes, ncmds, ndw;
-+        struct amdgpu_job *job;
- 	struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
- 	int r;
-@@ -744,18 +713,13 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 		/* two extra commands for begin/end of fragment */
- 		ndw += 2 * 10;
- 	}
-+        r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
-+        if (r)
- 
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib)
--		return -ENOMEM;
--
--        r = amdgpu_ib_get(adev, NULL, ndw * 4, ib);
--	if (r) {
--		kfree(ib);
- 		return r;
--	}
- 
--	ib->length_dw = 0;
-+        ib = &job->ibs[0];
-+
-         r = amdgpu_sync_resv(adev, &ib->sync, vm->page_directory->tbo.resv,
-                              owner);
-         if (r)
-@@ -770,10 +734,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 
-         amdgpu_ring_pad_ib(ring, ib);
- 	WARN_ON(ib->length_dw > ndw);
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--						 &amdgpu_vm_free_job,
--						 AMDGPU_FENCE_OWNER_VM,
--						 &f);
-+        r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &f);
- 	if (r)
- 		goto error_free;
- 
-@@ -786,8 +747,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	return 0;
- 
- error_free:
--	amdgpu_ib_free(adev, ib);
--	kfree(ib);
-+        amdgpu_job_free(job);
- 	return r;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0280-drm-amdgpu-rename-amdgpu_sched.c-to-amdgpu_job.c.patch b/common/recipes-kernel/linux/files/0280-drm-amdgpu-rename-amdgpu_sched.c-to-amdgpu_job.c.patch
deleted file mode 100644
index e76006c8..00000000
--- a/common/recipes-kernel/linux/files/0280-drm-amdgpu-rename-amdgpu_sched.c-to-amdgpu_job.c.patch
+++ /dev/null
@@ -1,338 +0,0 @@
-From 5d80a5c6d33cb16be4e609c6302c09a5db7200c8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 1 Feb 2016 12:31:01 +0100
-Subject: [PATCH 0280/1110] drm/amdgpu: rename amdgpu_sched.c to amdgpu_job.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-That's probably a better matching name.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   | 153 ++++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 151 -----------------------------
- 2 files changed, 153 insertions(+), 151 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-new file mode 100644
-index 0000000..fe4f6be
---- /dev/null
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -0,0 +1,153 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ *
-+ */
-+#include <linux/kthread.h>
-+#include <linux/wait.h>
-+#include <linux/sched.h>
-+#include <drm/drmP.h>
-+#include "amdgpu.h"
-+#include "amdgpu_trace.h"
-+
-+int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-+                    struct amdgpu_job **job)
-+{
-+       size_t size = sizeof(struct amdgpu_job);
-+
-+       if (num_ibs == 0)
-+               return -EINVAL;
-+
-+       size += sizeof(struct amdgpu_ib) * num_ibs;
-+
-+       *job = kzalloc(size, GFP_KERNEL);
-+       if (!*job)
-+               return -ENOMEM;
-+
-+       (*job)->adev = adev;
-+       (*job)->ibs = (void *)&(*job)[1];
-+       (*job)->num_ibs = num_ibs;
-+
-+       return 0;
-+}
-+
-+int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
-+                            struct amdgpu_job **job)
-+{
-+       int r;
-+
-+       r = amdgpu_job_alloc(adev, 1, job);
-+       if (r)
-+               return r;
-+
-+       r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
-+       if (r)
-+               kfree(*job);
-+
-+       return r;
-+}
-+
-+void amdgpu_job_free(struct amdgpu_job *job)
-+{
-+       unsigned i;
-+
-+       for (i = 0; i < job->num_ibs; ++i)
-+               amdgpu_ib_free(job->adev, &job->ibs[i]);
-+
-+       amdgpu_bo_unref(&job->uf.bo);
-+       kfree(job);
-+}
-+
-+int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-+                     void *owner, struct fence **f)
-+{
-+       struct amdgpu_device *adev = job->adev;
-+
-+       job->ring = ring;
-+       job->base.sched = &ring->sched;
-+       job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
-+       job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner);
-+       if (!job->base.s_fence)
-+               return -ENOMEM;
-+
-+       *f = fence_get(&job->base.s_fence->base);
-+
-+       job->owner = owner;
-+       amd_sched_entity_push_job(&job->base);
-+
-+       return 0;
-+}
-+
-+static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
-+{
-+       struct amdgpu_job *job = to_amdgpu_job(sched_job);
-+       struct amdgpu_sync *sync = &job->ibs->sync;
-+       struct amdgpu_vm *vm = job->ibs->vm;
-+
-+       struct fence *fence = amdgpu_sync_get_fence(sync);
-+
-+       if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
-+               struct amdgpu_ring *ring = job->ring;
-+               int r;
-+
-+               r = amdgpu_vm_grab_id(vm, ring, sync,
-+                                     &job->base.s_fence->base);
-+               if (r)
-+                       DRM_ERROR("Error getting VM ID (%d)\n", r);
-+               else
-+                       job->ibs->grabbed_vmid = true;
-+
-+               fence = amdgpu_sync_get_fence(sync);
-+       }
-+
-+       return fence;
-+}
-+
-+static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
-+{
-+       struct fence *fence = NULL;
-+       struct amdgpu_job *job;
-+       int r;
-+
-+       if (!sched_job) {
-+               DRM_ERROR("job is null\n");
-+               return NULL;
-+       }
-+       job = to_amdgpu_job(sched_job);
-+       trace_amdgpu_sched_run_job(job);
-+       r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
-+                              job->owner, &fence);
-+       if (r) {
-+               DRM_ERROR("Error scheduling IBs (%d)\n", r);
-+               goto err;
-+       }
-+
-+err:
-+       amdgpu_job_free(job);
-+       return fence;
-+}
-+
-+struct amd_sched_backend_ops amdgpu_sched_ops = {
-+       .dependency = amdgpu_job_dependency,
-+       .run_job = amdgpu_job_run,
-+};
-+
-+
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-index e699b06..e69de29 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
-@@ -1,151 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- *
-- */
--#include <linux/kthread.h>
--#include <linux/wait.h>
--#include <linux/sched.h>
--#include <drm/drmP.h>
--#include "amdgpu.h"
--#include "amdgpu_trace.h"
--
--int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--                     struct amdgpu_job **job)
--{
--       size_t size = sizeof(struct amdgpu_job);
-- 
--        if (num_ibs == 0)
--                return -EINVAL;
-- 
--        size += sizeof(struct amdgpu_ib) * num_ibs;
-- 
--        *job = kzalloc(size, GFP_KERNEL);
--        if (!*job)
--                return -ENOMEM;
-- 
--        (*job)->adev = adev;
--        (*job)->ibs = (void *)&(*job)[1];
--        (*job)->num_ibs = num_ibs;
--        (*job)->free_job = NULL;
-- 
--        return 0;
--}
--
--void amdgpu_job_free(struct amdgpu_job *job)
--{
--        unsigned i;
-- 
--        for (i = 0; i < job->num_ibs; ++i)
--                amdgpu_ib_free(job->adev, &job->ibs[i]);
-- 
--        amdgpu_bo_unref(&job->uf.bo);
--       /* TODO: Free the job structure here as well */
--}
--
--static struct fence *amdgpu_sched_dependency(struct amd_sched_job *sched_job)
--{
--	struct amdgpu_job *job = to_amdgpu_job(sched_job);
--	struct amdgpu_sync *sync = &job->ibs->sync;
--	struct amdgpu_vm *vm = job->ibs->vm;
--
--	struct fence *fence = amdgpu_sync_get_fence(sync);
--
--	if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
--                struct amdgpu_ring *ring = job->ring;
--		int r;
--
--		r = amdgpu_vm_grab_id(vm, ring, sync,
--				      &job->base.s_fence->base);
--		if (r)
--			DRM_ERROR("Error getting VM ID (%d)\n", r);
--		else
--			job->ibs->grabbed_vmid = true;
--
--		fence = amdgpu_sync_get_fence(sync);
--	}
--
--	return fence;
--}
--
--static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job)
--{
--	struct amdgpu_fence *fence = NULL;
--	struct amdgpu_job *job;
--	int r;
--
--	if (!sched_job) {
--		DRM_ERROR("job is null\n");
--		return NULL;
--	}
--	job = to_amdgpu_job(sched_job);
--	trace_amdgpu_sched_run_job(job);
--        r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
--                               job->owner, &fence);
--	if (r) {
--		DRM_ERROR("Error scheduling IBs (%d)\n", r);
--		goto err;
--	}
--
--err:
--	if (job->free_job)
--		job->free_job(job);
--
--	kfree(job);
--        return fence;
--}
--
--struct amd_sched_backend_ops amdgpu_sched_ops = {
--	.dependency = amdgpu_sched_dependency,
--	.run_job = amdgpu_sched_run_job,
--};
--
--int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
--					 struct amdgpu_ring *ring,
--					 struct amdgpu_ib *ibs,
--					 unsigned num_ibs,
--					 int (*free_job)(struct amdgpu_job *),
--					 void *owner,
--					 struct fence **f)
--{
--	struct amdgpu_job *job =
--		kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
--	if (!job)
--		return -ENOMEM;
--	job->base.sched = &ring->sched;
--	job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
--	job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner);
--	if (!job->base.s_fence) {
--		kfree(job);
--		return -ENOMEM;
--	}
--	*f = fence_get(&job->base.s_fence->base);
--
--	job->adev = adev;
--        job->ring = ring;
--	job->ibs = ibs;
--	job->num_ibs = num_ibs;
--	job->owner = owner;
--	job->free_job = free_job;
--	amd_sched_entity_push_job(&job->base);
--
--	return 0;
--}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0281-drm-amdgpu-send-UVD-IB-tests-directly-to-the-ring.patch b/common/recipes-kernel/linux/files/0281-drm-amdgpu-send-UVD-IB-tests-directly-to-the-ring.patch
deleted file mode 100644
index 29948aca..00000000
--- a/common/recipes-kernel/linux/files/0281-drm-amdgpu-send-UVD-IB-tests-directly-to-the-ring.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From 47c1854b8ffaa37712a637e4d1ba91d7eb7ab762 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 3 Feb 2016 16:01:06 +0100
-Subject: [PATCH 0281/1110] drm/amdgpu: send UVD IB tests directly to the ring
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We need the IB test for GPU resets as well and
-the scheduler should be stoped then.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 32 ++++++++++++++++++++++----------
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  2 +-
- 5 files changed, 26 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 35aa5a2..16284b9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -244,7 +244,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
- 
- 			amdgpu_uvd_note_usage(adev);
- 
--			r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
-+                        r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence);
- 			if (r) {
- 				DRM_ERROR("Error destroying UVD (%d)!\n", r);
- 				continue;
-@@ -300,7 +300,8 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
- 
- 			amdgpu_uvd_note_usage(adev);
- 
--			r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
-+                        r = amdgpu_uvd_get_destroy_msg(ring, handle,
-+                                                      false, &fence);
- 			if (r) {
- 				DRM_ERROR("Error destroying UVD (%d)!\n", r);
- 				continue;
-@@ -836,9 +837,9 @@ static int amdgpu_uvd_free_job(
- 	return 0;
- }
- 
--static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
--			       struct amdgpu_bo *bo,
--			       struct fence **fence)
-+static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
-+                              bool direct, struct fence **fence)
-+
- {
- 	struct ttm_validate_buffer tv;
- 	struct ww_acquire_ctx ticket;
-@@ -891,8 +892,19 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
- 						 &amdgpu_uvd_free_job,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
--	if (r)
--		goto err2;
-+        if (direct) {
-+                r = amdgpu_ib_schedule(ring, 1, ib,
-+                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+                if (r)
-+                        goto err_free;
-+
-+                amdgpu_job_free(job);
-+        } else {
-+                r = amdgpu_job_submit(job, ring,
-+                                      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+                if (r)
-+                        goto err_free;
-+        }
- 
- 	ttm_eu_fence_buffer_objects(&ticket, &head, f);
- 
-@@ -960,11 +972,11 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	amdgpu_bo_kunmap(bo);
- 	amdgpu_bo_unreserve(bo);
- 
--	return amdgpu_uvd_send_msg(ring, bo, fence);
-+        return amdgpu_uvd_send_msg(ring, bo, true, fence);
- }
- 
- int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
--			       struct fence **fence)
-+                              bool direct, struct fence **fence)
- {
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_bo *bo;
-@@ -1002,7 +1014,7 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	amdgpu_bo_kunmap(bo);
- 	amdgpu_bo_unreserve(bo);
- 
--	return amdgpu_uvd_send_msg(ring, bo, fence);
-+        return amdgpu_uvd_send_msg(ring, bo, direct, fence);
- }
- 
- static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
-index 1724c2c..9a3b449 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
-@@ -31,7 +31,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev);
- int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 			      struct fence **fence);
- int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
--			       struct fence **fence);
-+			       bool direct, struct fence **fence);
- void amdgpu_uvd_free_handles(struct amdgpu_device *adev,
- 			     struct drm_file *filp);
- int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx);
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index 91080a5..d2fc1ca 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -522,7 +522,7 @@ static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring)
- 		goto error;
- 	}
- 
--	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
-+	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
- 		goto error;
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 1e8476a..c5edb98 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -568,7 +568,7 @@ static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring)
- 		goto error;
- 	}
- 
--	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
-+	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
- 		goto error;
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index e55b040..0d5098e 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -800,7 +800,7 @@ static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring)
- 		goto error;
- 	}
- 
--	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);
-+	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
- 		goto error;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0282-drm-amdgpu-send-VCE-IB-tests-directly-to-the-ring-ag.patch b/common/recipes-kernel/linux/files/0282-drm-amdgpu-send-VCE-IB-tests-directly-to-the-ring-ag.patch
deleted file mode 100644
index 62a30479..00000000
--- a/common/recipes-kernel/linux/files/0282-drm-amdgpu-send-VCE-IB-tests-directly-to-the-ring-ag.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 5fe0e3fc256e398fd1de01345ee3783801e2fef8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 3 Feb 2016 16:50:56 +0100
-Subject: [PATCH 0282/1110] drm/amdgpu: send VCE IB tests directly to the ring
- again
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We need the IB test for GPU resets as well and
-the scheduler should be stoped then.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27 ++++++++++++++++++++++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h |  2 +-
- 2 files changed, 23 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 26cc9e4..2c055b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -338,7 +338,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
- 
- 		amdgpu_vce_note_usage(adev);
- 
--		r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
-+                r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
- 		if (r)
- 			DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
- 
-@@ -428,8 +428,12 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &amdgpu_vce_free_job,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
-+        r = amdgpu_ib_schedule(ring, 1, ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+
- 	if (r)
- 		goto err;
-+       
-+	 amdgpu_job_free(job);
- 	if (fence)
- 		*fence = fence_get(f);
- 	fence_put(f);
-@@ -451,7 +455,7 @@ err:
-  * Close up a stream for HW test or if userspace failed to do so
-  */
- int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
--			       struct fence **fence)
-+                               bool direct, struct fence **fence)
- {
- 	const unsigned ib_size_dw = 1024;
- 	struct amdgpu_ib *ib = NULL;
-@@ -494,8 +498,21 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &amdgpu_vce_free_job,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
--	if (r)
--		goto err;
-+
-+       if (direct) {
-+                r = amdgpu_ib_schedule(ring, 1, ib,
-+                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+                if (r)
-+                        goto err;
-+
-+                amdgpu_job_free(job);
-+        } else {
-+                r = amdgpu_job_submit(job, ring,
-+                                      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+                if (r)
-+                        goto err;
-+        }
-+
- 	if (fence)
- 		*fence = fence_get(f);
- 	fence_put(f);
-@@ -836,7 +853,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
- 		goto error;
- 	}
- 
--	r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
-+        r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
- 		goto error;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-index 5538cf7..ef99d23 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-@@ -31,7 +31,7 @@ int amdgpu_vce_resume(struct amdgpu_device *adev);
- int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 			      struct fence **fence);
- int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
--			       struct fence **fence);
-+			       bool direct, struct fence **fence);
- void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
- int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
- void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0283-drm-amdgpu-move-sync-into-job-object.patch b/common/recipes-kernel/linux/files/0283-drm-amdgpu-move-sync-into-job-object.patch
deleted file mode 100644
index 29c12bc0..00000000
--- a/common/recipes-kernel/linux/files/0283-drm-amdgpu-move-sync-into-job-object.patch
+++ /dev/null
@@ -1,384 +0,0 @@
-From 8831d24449a923ff2859966c653a57e9ef50bfa2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 8 Feb 2016 12:13:05 +0100
-Subject: [PATCH 0283/1110] drm/amdgpu: move sync into job object
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to keep that for every IB.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  3 ++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 12 +++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 16 ++++------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 21 +++++++++++++++------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  7 ++++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  5 +++--
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |  3 ++-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  3 ++-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  6 ++++--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  |  3 ++-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |  3 ++-
- 13 files changed, 47 insertions(+), 39 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0e63bd3..c882c7c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -736,7 +736,6 @@ struct amdgpu_ib {
- 	bool				grabbed_vmid;
- 	struct amdgpu_vm		*vm;
- 	struct amdgpu_ctx		*ctx;
--	struct amdgpu_sync		sync;
- 	uint32_t			gds_base, gds_size;
- 	uint32_t			gws_base, gws_size;
- 	uint32_t			oa_base, oa_size;
-@@ -1142,6 +1141,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		       struct amdgpu_ib *ib, void *owner);
-+                       struct fence *last_vm_update,
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
- void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
- int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
-@@ -1199,6 +1199,7 @@ struct amdgpu_job {
- 	struct amd_sched_job    base;
- 	struct amdgpu_device	*adev;
-         struct amdgpu_ring      *ring;
-+        struct amdgpu_sync      sync;
- 	struct amdgpu_ib	*ibs;
- 	uint32_t		num_ibs;
- 	void			*owner;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 45ba532..a92a30a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -459,7 +459,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
- 
- 	list_for_each_entry(e, &p->validated, tv.head) {
- 		struct reservation_object *resv = e->robj->tbo.resv;
--                r = amdgpu_sync_resv(p->adev, &p->job->ibs[0].sync, resv, p->filp);
-+                r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
- 
- 		if (r)
- 			return r;
-@@ -562,14 +562,14 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- 				return r;
- 
- 			f = bo_va->last_pt_update;
--                        r = amdgpu_sync_fence(adev, &p->job->ibs[0].sync, f);
-+                        r = amdgpu_sync_fence(adev, &p->job->sync, f);
- 			if (r)
- 				return r;
- 		}
- 
- 	}
- 
--        r = amdgpu_vm_clear_invalids(adev, vm, &p->job->ibs[0].sync);
-+        r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
- 
- 	if (amdgpu_vm_debug && p->bo_list) {
- 		/* Invalidate all BOs to test for userspace bugs */
-@@ -745,11 +745,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 				  struct amdgpu_cs_parser *p)
- {
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
--	struct amdgpu_ib *ib;
- 	int i, j, r;
- 
--	/* Add dependencies to first IB */
--        ib = &p->job->ibs[0];
- 	for (i = 0; i < p->nchunks; ++i) {
- 		struct drm_amdgpu_cs_chunk_dep *deps;
- 		struct amdgpu_cs_chunk *chunk;
-@@ -787,7 +784,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 				return r;
- 
- 			} else if (fence) {
--				r = amdgpu_sync_fence(adev, &ib->sync, fence);
-+                                r = amdgpu_sync_fence(adev, &p->job->sync,
-+                                                      fence);
- 				fence_put(fence);
- 				amdgpu_ctx_put(ctx);
- 				if (r)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 640ff53..9040b3e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -74,8 +74,6 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 			ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
- 	}
- 
--	amdgpu_sync_create(&ib->sync);
--
- 	ib->vm = vm;
- 
- 	return 0;
-@@ -91,7 +89,6 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-  */
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
- {
--	amdgpu_sync_free(&ib->sync);
- 	amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base);
- 	if (ib->fence)
- 		fence_put(&ib->fence->base);
-@@ -119,7 +116,9 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
-  * to SI there was just a DE IB.
-  */
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
--		       struct amdgpu_ib *ibs, void *owner)
-+		       struct amdgpu_ib *ibs, void *owner,
-+                       struct fence *last_vm_update,
-+		       struct fence **f)
- {
-         struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_ib *ib = &ibs[0];
-@@ -150,16 +149,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		return r;
- 	}
- 
--	r = amdgpu_sync_wait(&ibs->sync);
--	if (r) {
--		amdgpu_ring_undo(ring);
--		dev_err(adev->dev, "failed to sync wait (%d)\n", r);
--		return r;
--	}
--
- 	if (vm) {
- 		/* do context switch */
--		amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
-+                amdgpu_vm_flush(ring, vm, last_vm_update);
- 
- 		if (ring->funcs->emit_gds_switch)
- 			amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index fe4f6be..fda8ebc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -46,6 +46,8 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-        (*job)->ibs = (void *)&(*job)[1];
-        (*job)->num_ibs = num_ibs;
- 
-+       amdgpu_sync_create(&(*job)->sync);
-+
-        return 0;
- }
- 
-@@ -73,6 +75,7 @@ void amdgpu_job_free(struct amdgpu_job *job)
-                amdgpu_ib_free(job->adev, &job->ibs[i]);
- 
-        amdgpu_bo_unref(&job->uf.bo);
-+       amdgpu_sync_free(&job->sync);
-        kfree(job);
- }
- 
-@@ -99,23 +102,22 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
- static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
- {
-        struct amdgpu_job *job = to_amdgpu_job(sched_job);
--       struct amdgpu_sync *sync = &job->ibs->sync;
-        struct amdgpu_vm *vm = job->ibs->vm;
- 
--       struct fence *fence = amdgpu_sync_get_fence(sync);
-+       struct fence *fence = amdgpu_sync_get_fence(&job->sync);
- 
-        if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
-                struct amdgpu_ring *ring = job->ring;
-                int r;
- 
--               r = amdgpu_vm_grab_id(vm, ring, sync,
-+               r = amdgpu_vm_grab_id(vm, ring, &job->sync,
-                                      &job->base.s_fence->base);
-                if (r)
-                        DRM_ERROR("Error getting VM ID (%d)\n", r);
-                else
-                        job->ibs->grabbed_vmid = true;
- 
--               fence = amdgpu_sync_get_fence(sync);
-+               fence = amdgpu_sync_get_fence(&job->sync);
-        }
- 
-        return fence;
-@@ -132,9 +134,16 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
-                return NULL;
-        }
-        job = to_amdgpu_job(sched_job);
-+
-+       r = amdgpu_sync_wait(&job->sync);
-+       if (r) {
-+               DRM_ERROR("failed to sync wait (%d)\n", r);
-+               return NULL;
-+       }
-+
-        trace_amdgpu_sched_run_job(job);
--       r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
--                              job->owner, &fence);
-+       r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job->owner,
-+                              job->sync.last_vm_update, &fence);
-        if (r) {
-                DRM_ERROR("Error scheduling IBs (%d)\n", r);
-                goto err;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index df5ecc2..7355007 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -1039,7 +1039,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	ib->length_dw = 0;
- 
- 	if (resv) {
--		r = amdgpu_sync_resv(adev, &ib->sync, resv,
-+                r = amdgpu_sync_resv(adev, &job->sync, resv,
- 				     AMDGPU_FENCE_OWNER_UNDEFINED);
- 		if (r) {
- 			DRM_ERROR("sync failed (%d).\n", r);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 16284b9..8b11edc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -894,7 +894,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 						 &f);
-         if (direct) {
-                 r = amdgpu_ib_schedule(ring, 1, ib,
--                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+                                       AMDGPU_FENCE_OWNER_UNDEFINED, NULL, &f);
-                 if (r)
-                         goto err_free;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 2c055b1..5564a46 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -428,8 +428,8 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &amdgpu_vce_free_job,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
--        r = amdgpu_ib_schedule(ring, 1, ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
--
-+        r = amdgpu_ib_schedule(ring, 1, ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r)
- 		goto err;
-        
-@@ -501,7 +501,8 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 
-        if (direct) {
-                 r = amdgpu_ib_schedule(ring, 1, ib,
--                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+                                       AMDGPU_FENCE_OWNER_UNDEFINED,
-+                                       NULL, &f);
-                 if (r)
-                         goto err;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index e65f4a9..8877f15 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -476,7 +476,8 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 
- 	if (ib->length_dw != 0) {
-                 amdgpu_ring_pad_ib(ring, ib);
--		amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
-+                amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
-+                                 AMDGPU_FENCE_OWNER_VM);
- 		WARN_ON(ib->length_dw > ndw);
-                 r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &fence);
- 		if (r)
-@@ -720,7 +721,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 
-         ib = &job->ibs[0];
- 
--        r = amdgpu_sync_resv(adev, &ib->sync, vm->page_directory->tbo.resv,
-+        r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
-                              owner);
-         if (r)
-                 goto error_free;
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 60c5d35..2accc7c 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -633,7 +633,8 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[3] = 1;
- 	ib.ptr[4] = 0xDEADBEEF;
- 	ib.length_dw = 5;
--	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 90bff8c..99d85f6 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2641,7 +2641,8 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r)
- 		goto err2;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index ffc9b0a..1b5abdb 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -709,7 +709,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r)
- 		goto err2;
- 
-@@ -1264,7 +1265,8 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
- 
- 	/* shedule the ib on the ring */
--	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
- 		goto fail;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 9b29c2a..bf5c4f1 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -691,7 +691,8 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 17f9acd..cdb9a9f 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -842,7 +842,8 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--	r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
-+                               NULL, &f);
- 	if (r)
- 		goto err1;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0284-drm-amdgpu-Don-t-crash-system-if-we-can-t-get-crtc.patch b/common/recipes-kernel/linux/files/0284-drm-amdgpu-Don-t-crash-system-if-we-can-t-get-crtc.patch
deleted file mode 100644
index 542a3d6f..00000000
--- a/common/recipes-kernel/linux/files/0284-drm-amdgpu-Don-t-crash-system-if-we-can-t-get-crtc.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From db54921428ca7db9ad7586500ea0ef469bc6b88d Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 25 Nov 2015 15:42:09 -0500
-Subject: [PATCH 0284/1110] drm/amdgpu: Don't crash system if we can't get crtc
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index 4488e82..ab58187 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -727,6 +727,12 @@ int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
- 
- 	/* Get associated drm_crtc: */
- 	crtc = &adev->mode_info.crtcs[pipe]->base;
-+	if (!crtc) {
-+		/* This can occur on driver load if some component fails to
-+		 * initialize completely and driver is unloaded */
-+		DRM_ERROR("Uninitialized crtc %d\n", pipe);
-+		return -EINVAL;
-+	}
- 
- 	/* Helper routine in DRM core does all the work: */
- 	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch b/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch
deleted file mode 100644
index b2c91d3f..00000000
--- a/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From c580f8426eb04e18ed9373ab4f420b5e05e6b63e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 24 Nov 2015 10:51:51 -0500
-Subject: [PATCH 0285/1110] drm/amd: Adding IVSRC register headers
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/include/ivsrcid/ivsrcid_vislands30.h   | 102 +++++++++++++++++++++
- 1 file changed, 102 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
-
-diff --git a/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h b/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
-new file mode 100644
-index 0000000..d21c6b1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
-@@ -0,0 +1,102 @@
-+/*
-+ * Volcanic Islands IV SRC Register documentation
-+ *
-+ * Copyright (C) 2015  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef _IVSRCID_VISLANDS30_H_
-+#define _IVSRCID_VISLANDS30_H_
-+
-+
-+// IV Source IDs
-+
-+#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT		            7	    // 0x07	
-+#define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT                  0
-+
-+#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP		            8	    // 0x08	
-+#define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP                    0
-+
-+#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT		            9	    // 0x09	
-+#define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT                  0
-+
-+#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP  		            10	    // 0x0a	
-+#define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP                    0
-+
-+#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT		            11	    // 0x0b	
-+#define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT                  0
-+
-+#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP		            12	    // 0x0c	
-+#define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP                    0
-+
-+#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT		            13	    // 0x0d  	
-+#define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT                  0
-+
-+#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP		            14	    // 0x0e  	
-+#define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP                    0
-+
-+#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT		            15	    // 0x0f	
-+#define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT                  0
-+
-+#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP		            16	    // 0x10  	
-+#define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP                    0
-+
-+#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT		            17	    // 0x11      	
-+#define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT                  0
-+
-+#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP		            18	    // 0x12  	
-+#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP                    0
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A		            42	    // 0x2a	
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A                 0
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B   		        42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B                 1
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C   		        42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C                 2
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D	    	        42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D                 3
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E		            42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E                 4
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F		            42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F                 5
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_A		                    42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HPD_RX_A                         6
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_B		                    42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HPD_RX_B                         7
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_C		                    42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HPD_RX_C                         8
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_D		                    42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HPD_RX_D                         9
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_E		                    42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HPD_RX_E                         10
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_F		                    42	    // 0x2a		
-+#define VISLANDS30_IV_EXTID_HPD_RX_F                         11
-+
-+#endif // _IVSRCID_VISLANDS30_H_
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0286-drm-amd-powerplay-change-struct-name.patch b/common/recipes-kernel/linux/files/0286-drm-amd-powerplay-change-struct-name.patch
deleted file mode 100644
index 2044a466..00000000
--- a/common/recipes-kernel/linux/files/0286-drm-amd-powerplay-change-struct-name.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From 9a3e589e2ff9a665fc2d5f9b4ba111ef344bacd2 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 10 Dec 2015 16:49:50 +0800
-Subject: [PATCH 0286/1110] drm/amd/powerplay: change struct name.
-
-amd_pp_dal_clock_info to amd_pp_simple_clock_info.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c         | 2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c        | 4 ++--
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h     | 4 ++--
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 2 +-
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h             | 2 +-
- 6 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index bbc6bda..a5d7282 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -767,7 +767,7 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input)
- }
- 
- int amd_powerplay_get_display_power_level(void *handle,
--		struct amd_pp_dal_clock_info *output)
-+		struct amd_pp_simple_clock_info *output)
- {
- 	struct pp_hwmgr  *hwmgr;
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 1e90cbf..ab0242d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1697,10 +1697,10 @@ static void cz_hw_print_display_cfg(
- }
- 
-  static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct amd_pp_dal_clock_info*info)
-+		struct amd_pp_simple_clock_info *info)
- {
- 	uint32_t i;
--	const struct phm_clock_voltage_dependency_table * table =
-+	const struct phm_clock_voltage_dependency_table *table =
- 			hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
- 	const struct phm_clock_and_voltage_limits* limits =
- 			&hwmgr->dyn_state.max_clock_voltage_on_ac;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index 0f2d5e4..a53d4f2 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -313,7 +313,7 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- }
- 
- int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct amd_pp_dal_clock_info *info)
-+		struct amd_pp_simple_clock_info *info)
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index ee23606..3edc2d3 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -212,7 +212,7 @@ struct amd_pp_display_configuration {
- 	uint32_t dce_tolerable_mclk_in_active_latency;
- };
- 
--struct amd_pp_dal_clock_info {
-+struct amd_pp_simple_clock_info {
- 	uint32_t	engine_max_clock;
- 	uint32_t	memory_max_clock;
- 	uint32_t	level;
-@@ -309,7 +309,7 @@ int amd_powerplay_fini(void *handle);
- int amd_powerplay_display_configuration_change(void *handle, const void *input);
- 
- int amd_powerplay_get_display_power_level(void *handle,
--		struct amd_pp_dal_clock_info *output);
-+		struct amd_pp_simple_clock_info *output);
- 
- 
- #endif /* _AMD_POWERPLAY_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 91795ef..ce97bf2 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -375,7 +375,7 @@ extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 		const struct amd_pp_display_configuration *display_config);
- 
- extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
--		struct amd_pp_dal_clock_info*info);
-+		struct amd_pp_simple_clock_info *info);
- 
- extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 4094e81..e3214f1 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -325,7 +325,7 @@ struct pp_hwmgr_func {
- 				bool cc6_disable, bool pstate_disable,
- 				bool pstate_switch_disable);
- 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
--				   struct amd_pp_dal_clock_info *info);
-+				   struct amd_pp_simple_clock_info *info);
- 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
- 	int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table);
- 	int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0287-drm-amd-powerplay-export-interface-to-DAL.patch b/common/recipes-kernel/linux/files/0287-drm-amd-powerplay-export-interface-to-DAL.patch
deleted file mode 100644
index 77c6400f..00000000
--- a/common/recipes-kernel/linux/files/0287-drm-amd-powerplay-export-interface-to-DAL.patch
+++ /dev/null
@@ -1,394 +0,0 @@
-From 714ad0e4b4990ccafe9a3d54496b8ddb6c0a5ba4 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 7 Dec 2015 18:44:23 +0800
-Subject: [PATCH 0287/1110] drm/amd/powerplay: export interface to DAL.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c      | 81 +++++++++++++++++++
- .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 91 +++++++++++++++++++++-
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 50 ++++++++++++
- .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    | 42 +++++-----
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  8 +-
- 5 files changed, 251 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index a5d7282..7a5baeb 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -29,6 +29,7 @@
- #include "pp_instance.h"
- #include "power_state.h"
- #include "eventmanager.h"
-+#include "pp_debug.h"
- 
- #define PP_CHECK(handle)						\
- 	do {								\
-@@ -780,3 +781,83 @@ int amd_powerplay_get_display_power_level(void *handle,
- 
- 	return phm_get_dal_power_level(hwmgr, output);
- }
-+
-+int amd_powerplay_get_current_clocks(void *handle,
-+		void *output)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+	struct amd_pp_simple_clock_info simple_clocks;
-+	struct pp_clock_info hw_clocks;
-+	struct amd_pp_clock_info *clocks = (struct amd_pp_clock_info *)output;
-+
-+	if (handle == NULL || output == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	phm_get_dal_power_level(hwmgr, &simple_clocks);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
-+		if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
-+			PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
-+	} else {
-+		if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
-+			PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
-+	}
-+
-+	clocks->min_engine_clock = hw_clocks.min_eng_clk;
-+	clocks->max_engine_clock = hw_clocks.max_eng_clk;
-+	clocks->min_memory_clock = hw_clocks.min_mem_clk;
-+	clocks->max_memory_clock = hw_clocks.max_mem_clk;
-+	clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
-+	clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
-+
-+	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
-+	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
-+
-+	clocks->max_clocks_state = simple_clocks.level;
-+
-+	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
-+		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
-+		clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
-+	}
-+
-+	return 0;
-+
-+}
-+
-+int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
-+{
-+	int result = -1;
-+
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (handle == NULL || clocks == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	result = phm_get_clock_by_type(hwmgr, type, clocks);
-+
-+	return result;
-+}
-+
-+int amd_powerplay_get_display_mode_validation_clocks(void *handle, const void *input,
-+							void *output)
-+{
-+	int result = -1;
-+
-+	struct amd_pp_simple_clock_info *clocks = output;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL || clocks == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
-+		result = phm_get_max_high_clocks(hwmgr, clocks);
-+
-+	return result;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index a53d4f2..be31bed 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -26,7 +26,7 @@
- #include "power_state.h"
- #include "pp_acpi.h"
- #include "amd_acpi.h"
--#include "amd_powerplay.h"
-+#include "pp_debug.h"
- 
- #define PHM_FUNC_CHECK(hw) \
- 	do {							\
-@@ -319,7 +319,6 @@ int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
- 
- 	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
- 		return -EINVAL;
--
- 	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
- }
- 
-@@ -332,3 +331,91 @@ int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- 
- 	return 0;
- }
-+
-+
-+int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
-+				PHM_PerformanceLevelDesignation designation, uint32_t index,
-+				PHM_PerformanceLevel *level)
-+{
-+	PHM_FUNC_CHECK(hwmgr);
-+	if (hwmgr->hwmgr_func->get_performance_level == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
-+
-+
-+}
-+
-+
-+/**
-+* Gets Clock Info.
-+*
-+* @param    pHwMgr  the address of the powerplay hardware manager.
-+* @param    pPowerState the address of the Power State structure.
-+* @param    pClockInfo the address of PP_ClockInfo structure where the result will be returned.
-+* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
-+*/
-+int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
-+			PHM_PerformanceLevelDesignation designation)
-+{
-+	int result;
-+	PHM_PerformanceLevel performance_level;
-+
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
-+
-+	result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
-+
-+	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
-+
-+
-+	pclock_info->min_mem_clk = performance_level.memory_clock;
-+	pclock_info->min_eng_clk = performance_level.coreClock;
-+	pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
-+
-+
-+	result = phm_get_performance_level(hwmgr, state, designation,
-+					(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
-+
-+	PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
-+
-+	pclock_info->max_mem_clk = performance_level.memory_clock;
-+	pclock_info->max_eng_clk = performance_level.coreClock;
-+	pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
-+
-+	return 0;
-+}
-+
-+int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
-+{
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
-+
-+}
-+
-+int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
-+{
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
-+
-+}
-+
-+int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
-+{
-+	PHM_FUNC_CHECK(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
-+		return -EINVAL;
-+
-+	return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 3edc2d3..235f2fb 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -28,6 +28,7 @@
- #include "amd_shared.h"
- #include "cgs_common.h"
- 
-+
- enum amd_pp_event {
- 	AMD_PP_EVENT_INITIALIZE = 0,
- 	AMD_PP_EVENT_UNINITIALIZE,
-@@ -218,6 +219,49 @@ struct amd_pp_simple_clock_info {
- 	uint32_t	level;
- };
- 
-+enum PP_DAL_POWERLEVEL {
-+	PP_DAL_POWERLEVEL_INVALID = 0,
-+	PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_PERFORMANCE,
-+
-+	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
-+	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
-+	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
-+	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
-+	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-+};
-+
-+struct amd_pp_clock_info {
-+	uint32_t min_engine_clock;
-+	uint32_t max_engine_clock;
-+	uint32_t min_memory_clock;
-+	uint32_t max_memory_clock;
-+	uint32_t min_bus_bandwidth;
-+	uint32_t max_bus_bandwidth;
-+	uint32_t max_engine_clock_in_sr;
-+	uint32_t min_engine_clock_in_sr;
-+	enum PP_DAL_POWERLEVEL max_clocks_state;
-+};
-+
-+enum amd_pp_clock_type {
-+	amd_pp_disp_clock = 1,
-+	amd_pp_sys_clock,
-+	amd_pp_mem_clock
-+};
-+
-+#define MAX_NUM_CLOCKS 16
-+
-+struct amd_pp_clocks {
-+	uint32_t count;
-+	uint32_t clock[MAX_NUM_CLOCKS];
-+};
-+
-+
- enum {
- 	PP_GROUP_UNKNOWN = 0,
- 	PP_GROUP_GFX = 1,
-@@ -311,5 +355,11 @@ int amd_powerplay_display_configuration_change(void *handle, const void *input);
- int amd_powerplay_get_display_power_level(void *handle,
- 		struct amd_pp_simple_clock_info *output);
- 
-+int amd_powerplay_get_current_clocks(void *handle, void *output);
-+
-+int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
-+
-+int amd_powerplay_get_display_mode_validation_clocks(void *handle, const void *input,
-+							void *output);
- 
- #endif /* _AMD_POWERPLAY_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index ce97bf2..040d3f7 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -31,6 +31,7 @@ struct pp_power_state;
- enum amd_dpm_forced_level;
- struct PP_TemperatureRange;
- 
-+
- struct phm_fan_speed_info {
- 	uint32_t min_percent;
- 	uint32_t max_percent;
-@@ -290,6 +291,15 @@ struct PP_Clocks {
- 	uint32_t engineClockInSR;
- };
- 
-+struct pp_clock_info {
-+	uint32_t min_mem_clk;
-+	uint32_t max_mem_clk;
-+	uint32_t min_eng_clk;
-+	uint32_t max_eng_clk;
-+	uint32_t min_bus_bandwidth;
-+	uint32_t max_bus_bandwidth;
-+};
-+
- struct phm_platform_descriptor {
- 	uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
- 	uint32_t vbiosInterruptId;
-@@ -323,24 +333,6 @@ struct phm_clocks {
- 	uint32_t clock[MAX_NUM_CLOCKS];
- };
- 
--enum PP_DAL_POWERLEVEL {
--	PP_DAL_POWERLEVEL_INVALID = 0,
--	PP_DAL_POWERLEVEL_ULTRALOW,
--	PP_DAL_POWERLEVEL_LOW,
--	PP_DAL_POWERLEVEL_NOMINAL,
--	PP_DAL_POWERLEVEL_PERFORMANCE,
--
--	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
--	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
--	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
--	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
--	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
--	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
--	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
--	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
--};
--
--
- extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
- extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
- extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
-@@ -381,5 +373,19 @@ extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
- 
- extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
- 
-+extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
-+				PHM_PerformanceLevelDesignation designation, uint32_t index,
-+				PHM_PerformanceLevel *level);
-+
-+extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
-+			struct pp_clock_info *pclock_info,
-+			PHM_PerformanceLevelDesignation designation);
-+
-+extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
-+
-+extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
-+
-+extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
-+
- #endif /* _HARDWARE_MANAGER_H_ */
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index e3214f1..928f5a7 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -325,7 +325,13 @@ struct pp_hwmgr_func {
- 				bool cc6_disable, bool pstate_disable,
- 				bool pstate_switch_disable);
- 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
--				   struct amd_pp_simple_clock_info *info);
-+			struct amd_pp_simple_clock_info *info);
-+	int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
-+			PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
-+	int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
-+				const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
-+	int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
-+	int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
- 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
- 	int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table);
- 	int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0288-drm-amd-powerplay-implement-functions-in-carrizo-for.patch b/common/recipes-kernel/linux/files/0288-drm-amd-powerplay-implement-functions-in-carrizo-for.patch
deleted file mode 100644
index 62740ee6..00000000
--- a/common/recipes-kernel/linux/files/0288-drm-amd-powerplay-implement-functions-in-carrizo-for.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From 6fab3d6d22d39bd6c04281521d46f50095ddf494 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 7 Dec 2015 18:45:29 +0800
-Subject: [PATCH 0288/1110] drm/amd/powerplay: implement functions in carrizo
- for DAL.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 126 ++++++++++++++++++++++---
- 1 file changed, 115 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index ab0242d..c40fa40 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -901,9 +901,9 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
- 
- 		if (pnew_state->action == FORCE_HIGH)
- 			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
--		else if(pnew_state->action == CANCEL_FORCE_HIGH)
-+		else if (pnew_state->action == CANCEL_FORCE_HIGH)
- 			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
--		else 
-+		else
- 			cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
- 	}
- 	return 0;
-@@ -1648,10 +1648,10 @@ static void cz_hw_print_display_cfg(
- 			& PWRMGT_SEPARATION_TIME_MASK)
- 			<< PWRMGT_SEPARATION_TIME_SHIFT;
- 
--		data|= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
-+		data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
- 			<< PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
- 
--		data|= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
-+		data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
- 			<< PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
- 
- 		PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
-@@ -1666,9 +1666,9 @@ static void cz_hw_print_display_cfg(
- }
- 
- 
-- static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
-+static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
- 			bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
-- {
-+{
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	if (separation_time !=
-@@ -1696,20 +1696,19 @@ static void cz_hw_print_display_cfg(
- 	return 0;
- }
- 
-- static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
-+static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
- 		struct amd_pp_simple_clock_info *info)
- {
- 	uint32_t i;
- 	const struct phm_clock_voltage_dependency_table *table =
- 			hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
--	const struct phm_clock_and_voltage_limits* limits =
-+	const struct phm_clock_and_voltage_limits *limits =
- 			&hwmgr->dyn_state.max_clock_voltage_on_ac;
- 
- 	info->engine_max_clock = limits->sclk;
- 	info->memory_max_clock = limits->mclk;
- 
- 	for (i = table->count - 1; i > 0; i--) {
--
- 		if (limits->vddc >= table->entries[i].v) {
- 			info->level = table->entries[i].clk;
- 			return 0;
-@@ -1766,6 +1765,108 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	return size;
- }
- 
-+static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
-+				PHM_PerformanceLevelDesignation designation, uint32_t index,
-+				PHM_PerformanceLevel *level)
-+{
-+	const struct cz_power_state *ps;
-+	struct cz_hwmgr *data;
-+	uint32_t level_index;
-+	uint32_t i;
-+
-+	if (level == NULL || hwmgr == NULL || state == NULL)
-+		return -EINVAL;
-+
-+	data = (struct cz_hwmgr *)(hwmgr->backend);
-+	ps = cast_const_PhwCzPowerState(state);
-+	level->coreClock  = ps->levels[index].engineClock;
-+	level_index = index > ps->level - 1 ? ps->level - 1 : index;
-+
-+	if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
-+		for (i = 1; i < ps->level; i++) {
-+			if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
-+				level->coreClock = ps->levels[i].engineClock;
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (index == 0)
-+		level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
-+	else
-+		level->memory_clock = data->sys_info.nbp_memory_clock[0];
-+
-+	level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[index].vddcIndex) + 2) / 4;
-+	level->nonLocalMemoryFreq = 0;
-+	level->nonLocalMemoryWidth = 0;
-+
-+	return 0;
-+}
-+
-+static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
-+	const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
-+{
-+	const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
-+
-+	clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
-+	clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
-+
-+	return 0;
-+}
-+
-+static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
-+						struct amd_pp_clocks *clocks)
-+{
-+	struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
-+	int i;
-+	struct phm_clock_voltage_dependency_table *table;
-+
-+	clocks->count = cz_get_max_sclk_level(hwmgr);
-+	switch (type) {
-+	case amd_pp_disp_clock:
-+		for (i = 0; i < clocks->count; i++)
-+			clocks->clock[i] = data->sys_info.display_clock[i];
-+		break;
-+	case amd_pp_sys_clock:
-+		table = hwmgr->dyn_state.vddc_dependency_on_sclk;
-+		for (i = 0; i < clocks->count; i++)
-+			clocks->clock[i] = table->entries[i].clk;
-+		break;
-+	case amd_pp_mem_clock:
-+		clocks->count = CZ_NUM_NBPMEMORYCLOCK;
-+		for (i = 0; i < clocks->count; i++)
-+			clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
-+		break;
-+	default:
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
-+{
-+	struct phm_clock_voltage_dependency_table *table =
-+					hwmgr->dyn_state.vddc_dependency_on_sclk;
-+	unsigned long level;
-+	const struct phm_clock_and_voltage_limits *limits =
-+			&hwmgr->dyn_state.max_clock_voltage_on_ac;
-+
-+	if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
-+		return -EINVAL;
-+
-+	level = cz_get_max_sclk_level(hwmgr) - 1;
-+
-+	if (level < table->count)
-+		clocks->engine_max_clock = table->entries[level].clk;
-+	else
-+		clocks->engine_max_clock = table->entries[table->count - 1].clk;
-+
-+	clocks->memory_max_clock = limits->mclk;
-+
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.backend_init = cz_hwmgr_backend_init,
- 	.backend_fini = cz_hwmgr_backend_fini,
-@@ -1784,10 +1885,13 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.print_current_perforce_level = cz_print_current_perforce_level,
- 	.set_cpu_power_state = cz_set_cpu_power_state,
- 	.store_cc6_data = cz_store_cc6_data,
--	.get_dal_power_level= cz_get_dal_power_level,
- 	.force_clock_level = cz_force_clock_level,
- 	.print_clock_levels = cz_print_clock_levels,
--
-+	.get_dal_power_level = cz_get_dal_power_level,
-+	.get_performance_level = cz_get_performance_level,
-+	.get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
-+	.get_clock_by_type = cz_get_clock_by_type,
-+	.get_max_high_clocks = cz_get_max_high_clocks,
- };
- 
- int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0289-drm-amd-powerplay-Make-declarations-of-functions-exp.patch b/common/recipes-kernel/linux/files/0289-drm-amd-powerplay-Make-declarations-of-functions-exp.patch
deleted file mode 100644
index 53f89160..00000000
--- a/common/recipes-kernel/linux/files/0289-drm-amd-powerplay-Make-declarations-of-functions-exp.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-From 999b288e648da8e21d63bc4371c07d38ab3bcba0 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Mon, 14 Dec 2015 10:51:39 -0500
-Subject: [PATCH 0289/1110] drm/amd/powerplay: Make declarations of functions
- exposed to DAL type-safe.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 15 ++++++---------
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 15 ++++++++++-----
- 2 files changed, 16 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 7a5baeb..86e86e2 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -753,10 +753,10 @@ int amd_powerplay_fini(void *handle)
- 
- /* export this function to DAL */
- 
--int amd_powerplay_display_configuration_change(void *handle, const void *input)
-+int amd_powerplay_display_configuration_change(void *handle,
-+	const struct amd_pp_display_configuration *display_config)
- {
- 	struct pp_hwmgr  *hwmgr;
--	const struct amd_pp_display_configuration *display_config = input;
- 
- 	PP_CHECK((struct pp_instance *)handle);
- 
-@@ -783,14 +783,13 @@ int amd_powerplay_get_display_power_level(void *handle,
- }
- 
- int amd_powerplay_get_current_clocks(void *handle,
--		void *output)
-+		struct amd_pp_clock_info *clocks)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct amd_pp_simple_clock_info simple_clocks;
- 	struct pp_clock_info hw_clocks;
--	struct amd_pp_clock_info *clocks = (struct amd_pp_clock_info *)output;
- 
--	if (handle == NULL || output == NULL)
-+	if (handle == NULL || clocks == NULL)
- 		return -EINVAL;
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-@@ -842,12 +841,10 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
- 	return result;
- }
- 
--int amd_powerplay_get_display_mode_validation_clocks(void *handle, const void *input,
--							void *output)
-+int amd_powerplay_get_display_mode_validation_clocks(void *handle,
-+		struct amd_pp_simple_clock_info *clocks)
- {
- 	int result = -1;
--
--	struct amd_pp_simple_clock_info *clocks = output;
- 	struct pp_hwmgr  *hwmgr;
- 
- 	if (handle == NULL || clocks == NULL)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index 235f2fb..bbe02ec 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -348,18 +348,23 @@ struct amd_powerplay {
- 
- int amd_powerplay_init(struct amd_pp_init *pp_init,
- 		       struct amd_powerplay *amd_pp);
-+
- int amd_powerplay_fini(void *handle);
- 
--int amd_powerplay_display_configuration_change(void *handle, const void *input);
-+int amd_powerplay_display_configuration_change(void *handle,
-+		const struct amd_pp_display_configuration *input);
- 
- int amd_powerplay_get_display_power_level(void *handle,
- 		struct amd_pp_simple_clock_info *output);
- 
--int amd_powerplay_get_current_clocks(void *handle, void *output);
-+int amd_powerplay_get_current_clocks(void *handle,
-+		struct amd_pp_clock_info *output);
- 
--int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
-+int amd_powerplay_get_clock_by_type(void *handle,
-+		enum amd_pp_clock_type type,
-+		struct amd_pp_clocks *clocks);
- 
--int amd_powerplay_get_display_mode_validation_clocks(void *handle, const void *input,
--							void *output);
-+int amd_powerplay_get_display_mode_validation_clocks(void *handle,
-+		struct amd_pp_simple_clock_info *output);
- 
- #endif /* _AMD_POWERPLAY_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0290-drm-amd-powerplay-Use-engine-clock-limit-calculated-.patch b/common/recipes-kernel/linux/files/0290-drm-amd-powerplay-Use-engine-clock-limit-calculated-.patch
deleted file mode 100644
index b7c065c5..00000000
--- a/common/recipes-kernel/linux/files/0290-drm-amd-powerplay-Use-engine-clock-limit-calculated-.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From e8df16e7dc7910d54d0672c6fb3b4fc1f56ee121 Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Fri, 11 Dec 2015 13:38:58 -0500
-Subject: [PATCH 0290/1110] drm/amd/powerplay: Use engine clock limit
- calculated by dal
-
-Use min required system clock calculated by dal
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index c40fa40..fa85d8a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -733,7 +733,6 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
- 	unsigned long clock = 0;
- 	unsigned long level;
- 	unsigned long stable_pstate_sclk;
--	struct PP_Clocks clocks;
- 	unsigned long percentage;
- 
- 	cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
-@@ -744,8 +743,9 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
- 	else
- 		cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
- 
--	/*PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks);*/
--	clock = clocks.engineClock;
-+	clock = hwmgr->display_config.min_core_set_clock;
-+	if (clock == 0)
-+		printk(KERN_ERR "[ powerplay ] min_core_set_clock not set\n");
- 
- 	if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
- 		cz_hwmgr->sclk_dpm.hard_min_clk = clock;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0291-drm-amd-powerplay-get-real-display-device-num-by-cgs.patch b/common/recipes-kernel/linux/files/0291-drm-amd-powerplay-get-real-display-device-num-by-cgs.patch
deleted file mode 100644
index 5ec1e816..00000000
--- a/common/recipes-kernel/linux/files/0291-drm-amd-powerplay-get-real-display-device-num-by-cgs.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From c035e7e780257fc8093c38f8fe372aaffc729928 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 14 Dec 2015 18:14:57 +0800
-Subject: [PATCH 0291/1110] drm/amd/powerplay: get real display device num by
- cgs interface
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 25 ++++++++++++++++---------
- 1 file changed, 16 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index fa85d8a..1e79f84 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1128,9 +1128,10 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 				cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
- 
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
--	struct PP_Clocks clocks;
-+	struct PP_Clocks clocks = {0, 0, 0, 0};
- 	bool force_high;
--	unsigned long  num_of_active_displays = 4;
-+	uint32_t  num_of_active_displays = 0;
-+	struct cgs_display_info info = {0};
- 
- 	cz_ps->evclk = hwmgr->vce_arbiter.evclk;
- 	cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
-@@ -1142,12 +1143,15 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 
- 	cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
- 
--	/* to do PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
--	/* PECI_GetNumberOfActiveDisplays(pHwMgr->pPECI, &numOfActiveDisplays); */
-+	clocks.memoryClock = hwmgr->display_config.min_core_set_clock != 0 ?
-+				hwmgr->display_config.min_core_set_clock :
-+				cz_hwmgr->sys_info.nbp_memory_clock[1];
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	num_of_active_displays = info.display_count;
-+
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
- 		clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
--	else
--		clocks.memoryClock = 0;
- 
- 	if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
- 		clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-@@ -1217,6 +1221,7 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 		printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
- 		return result;
- 	}
-+	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
- 
- 	result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
- 	if (result != 0) {
-@@ -1779,9 +1784,11 @@ static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p
- 
- 	data = (struct cz_hwmgr *)(hwmgr->backend);
- 	ps = cast_const_PhwCzPowerState(state);
--	level->coreClock  = ps->levels[index].engineClock;
-+
- 	level_index = index > ps->level - 1 ? ps->level - 1 : index;
- 
-+	level->coreClock  = ps->levels[level_index].engineClock;
-+
- 	if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
- 		for (i = 1; i < ps->level; i++) {
- 			if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
-@@ -1791,12 +1798,12 @@ static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p
- 		}
- 	}
- 
--	if (index == 0)
-+	if (level_index == 0)
- 		level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
- 	else
- 		level->memory_clock = data->sys_info.nbp_memory_clock[0];
- 
--	level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[index].vddcIndex) + 2) / 4;
-+	level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
- 	level->nonLocalMemoryFreq = 0;
- 	level->nonLocalMemoryWidth = 0;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0292-drm-amd-powerplay-Use-correct-clock-in-cz_apply_stat.patch b/common/recipes-kernel/linux/files/0292-drm-amd-powerplay-Use-correct-clock-in-cz_apply_stat.patch
deleted file mode 100644
index 5afa5a47..00000000
--- a/common/recipes-kernel/linux/files/0292-drm-amd-powerplay-Use-correct-clock-in-cz_apply_stat.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 7878f3fb68fe6a4f54c12e61d91d0169e26d1a2e Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 15 Dec 2015 14:47:02 -0500
-Subject: [PATCH 0292/1110] drm/amd/powerplay: Use correct clock in
- cz_apply_state_adjust_rules
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Eagle Yeh <eagle.yeh@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 1e79f84..f5c79dd 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1143,8 +1143,8 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 
- 	cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
- 
--	clocks.memoryClock = hwmgr->display_config.min_core_set_clock != 0 ?
--				hwmgr->display_config.min_core_set_clock :
-+	clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
-+				hwmgr->display_config.min_mem_set_clock :
- 				cz_hwmgr->sys_info.nbp_memory_clock[1];
- 
- 	cgs_get_active_displays_info(hwmgr->device, &info);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0293-drm-amd-powerplay-Enable-low-mem-pstate-when-cancel_.patch b/common/recipes-kernel/linux/files/0293-drm-amd-powerplay-Enable-low-mem-pstate-when-cancel_.patch
deleted file mode 100644
index 304f57d8..00000000
--- a/common/recipes-kernel/linux/files/0293-drm-amd-powerplay-Enable-low-mem-pstate-when-cancel_.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From c0e331d4ac3d2834145a90175f453c9bd9080616 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 15 Dec 2015 19:00:59 -0500
-Subject: [PATCH 0293/1110] drm/amd/powerplay: Enable low mem pstate when
- cancel_high
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index f5c79dd..b8d6a82 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -902,7 +902,7 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
- 		if (pnew_state->action == FORCE_HIGH)
- 			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
- 		else if (pnew_state->action == CANCEL_FORCE_HIGH)
--			cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
-+			cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
- 		else
- 			cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0294-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch b/common/recipes-kernel/linux/files/0294-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch
deleted file mode 100644
index 1a2b8ff9..00000000
--- a/common/recipes-kernel/linux/files/0294-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 4b7da07fec96efab2edfc92f54af4ee9ef443a3b Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Dec 2015 13:56:03 +0800
-Subject: [PATCH 0294/1110] drm/amd/powerplay: add powerplay valid check to
- avoid null point.
-
-In case CONFIG_DRM_AMD_POWERPLAY is defined and amdgpu.powerplay=0.
-some functions in powrplay can also be called by DAL. and the input parameter is *adev.
-if just check point not NULL was not enough and will lead to NULL point error.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 12 +++++++++---
- 1 file changed, 9 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 86e86e2..351ebf2 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -789,7 +789,9 @@ int amd_powerplay_get_current_clocks(void *handle,
- 	struct amd_pp_simple_clock_info simple_clocks;
- 	struct pp_clock_info hw_clocks;
- 
--	if (handle == NULL || clocks == NULL)
-+	PP_CHECK((struct pp_instance *)handle);
-+
-+	if (clocks == NULL)
- 		return -EINVAL;
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-@@ -831,7 +833,9 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
- 
- 	struct pp_hwmgr *hwmgr;
- 
--	if (handle == NULL || clocks == NULL)
-+	PP_CHECK((struct pp_instance *)handle);
-+
-+	if (clocks == NULL)
- 		return -EINVAL;
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-@@ -847,7 +851,9 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle,
- 	int result = -1;
- 	struct pp_hwmgr  *hwmgr;
- 
--	if (handle == NULL || clocks == NULL)
-+	PP_CHECK((struct pp_instance *)handle);
-+
-+	if (clocks == NULL)
- 		return -EINVAL;
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch b/common/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch
deleted file mode 100644
index 6869eea3..00000000
--- a/common/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch
+++ /dev/null
@@ -1,1389 +0,0 @@
-From 7138ed10984deb0ccd7a2c78a0750fbd7f61257d Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 8 Feb 2016 09:55:13 -0500
-Subject: [PATCH 0295/1110] drm/amdgpu/gfx7: Reduce linecount in table init
-
-Replaces switch statements with direct assignments to
-reduce line count significantly.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1345 +++++++++++++--------------------
- 1 file changed, 525 insertions(+), 820 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 99d85f6..1543240 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1006,9 +1006,15 @@ out:
-  */
- static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
- {
--	const u32 num_tile_mode_states = 32;
--	const u32 num_secondary_tile_mode_states = 16;
--	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
-+	const u32 num_tile_mode_states =
-+			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-+	const u32 num_secondary_tile_mode_states =
-+			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-+	u32 reg_offset, split_equal_to_row_size;
-+	uint32_t *tile, *macrotile;
-+
-+	tile = adev->gfx.config.tile_mode_array;
-+	macrotile = adev->gfx.config.macrotile_mode_array;
- 
- 	switch (adev->gfx.config.mem_row_size_in_kb) {
- 	case 1:
-@@ -1023,832 +1029,531 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 		break;
- 	}
- 
-+	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+		tile[reg_offset] = 0;
-+	for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+		macrotile[reg_offset] = 0;
-+
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 7:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 12:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 17:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 23:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 30:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[7] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16));
-+		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
-+		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[12] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
-+		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[17] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
-+		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[23] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
-+		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[30] = (TILE_SPLIT(split_equal_to_row_size));
-+
-+		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
- 		break;
- 	case CHIP_HAWAII:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 7:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 12:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 17:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 23:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 30:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P4_16x16) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
--						NUM_BANKS(ADDR_SURF_4_BANK));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
-+		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
-+		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
-+		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
-+		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
-+		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
- 		break;
- 	case CHIP_KABINI:
- 	case CHIP_KAVERI:
- 	case CHIP_MULLINS:
- 	default:
--		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 1:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 2:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 3:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 4:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 5:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
--				break;
--			case 6:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
--						TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 7:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--
--			case 8:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
--						PIPE_CONFIG(ADDR_SURF_P2));
--				break;
--			case 9:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
--				break;
--			case 10:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 11:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 12:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 13:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
--				break;
--			case 14:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 15:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 16:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 17:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 18:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 19:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
--				break;
--			case 20:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 21:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 22:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 23:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			case 24:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 25:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 26:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
--				break;
--			case 27:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
--				break;
--			case 28:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
--				break;
--			case 29:
--				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
--						PIPE_CONFIG(ADDR_SURF_P2) |
--						MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
--						SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
--				break;
--			case 30:
--				gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
--		}
--		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
--			switch (reg_offset) {
--			case 0:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 1:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 2:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 3:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 4:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 5:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 6:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			case 8:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 9:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 10:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 11:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 12:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 13:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
--						NUM_BANKS(ADDR_SURF_16_BANK));
--				break;
--			case 14:
--				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
--						BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
--						MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
--						NUM_BANKS(ADDR_SURF_8_BANK));
--				break;
--			default:
--				gb_tile_moden = 0;
--				break;
--			}
--			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
--			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
--		}
-+		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-+			   TILE_SPLIT(split_equal_to_row_size));
-+		tile[7] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+			   PIPE_CONFIG(ADDR_SURF_P2));
-+		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			   PIPE_CONFIG(ADDR_SURF_P2) |
-+			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
-+		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[12] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
-+		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[17] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
-+		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[23] = (TILE_SPLIT(split_equal_to_row_size));
-+		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
-+		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+			    PIPE_CONFIG(ADDR_SURF_P2) |
-+			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		tile[30] = (TILE_SPLIT(split_equal_to_row_size));
-+
-+		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
- 		break;
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0296-drm-amdgpu-gfx7-Simplify-bitmask-creation.patch b/common/recipes-kernel/linux/files/0296-drm-amdgpu-gfx7-Simplify-bitmask-creation.patch
deleted file mode 100644
index 2f619677..00000000
--- a/common/recipes-kernel/linux/files/0296-drm-amdgpu-gfx7-Simplify-bitmask-creation.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 6849edf82b6aeafc89f4415108cc5ec8fe56773d Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 8 Feb 2016 08:48:15 -0500
-Subject: [PATCH 0296/1110] drm/amdgpu/gfx7: Simplify bitmask creation
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 +-------
- 1 file changed, 1 insertion(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 1543240..adaa3f8 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1598,13 +1598,7 @@ void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
-  */
- static u32 gfx_v7_0_create_bitmask(u32 bit_width)
- {
--	u32 i, mask = 0;
--
--	for (i = 0; i < bit_width; i++) {
--		mask <<= 1;
--		mask |= 1;
--	}
--	return mask;
-+	return (u32)((1ULL<<bit_width)-1);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0297-drm-amdgpu-gfx7-LOC-reduction-in-gfx_v7_0_setup_rb.patch b/common/recipes-kernel/linux/files/0297-drm-amdgpu-gfx7-LOC-reduction-in-gfx_v7_0_setup_rb.patch
deleted file mode 100644
index 31219bcd..00000000
--- a/common/recipes-kernel/linux/files/0297-drm-amdgpu-gfx7-LOC-reduction-in-gfx_v7_0_setup_rb.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 57ff151880cced48d72bcf4d5334864e6a4bc0a7 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 8 Feb 2016 12:34:19 -0500
-Subject: [PATCH 0297/1110] drm/amdgpu/gfx7: LOC reduction in gfx_v7_0_setup_rb
-
-Reduce for loop with bitmask to simple complement and mask
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 ++-------
- 1 file changed, 2 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index adaa3f8..940dc0b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1648,7 +1648,7 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
- 			      u32 max_rb_num_per_se)
- {
- 	int i, j;
--	u32 data, mask;
-+	u32 data;
- 	u32 disabled_rbs = 0;
- 	u32 enabled_rbs = 0;
- 
-@@ -1666,12 +1666,7 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
- 	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
- 	mutex_unlock(&adev->grbm_idx_mutex);
- 
--	mask = 1;
--	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
--		if (!(disabled_rbs & mask))
--			enabled_rbs |= mask;
--		mask <<= 1;
--	}
-+	enabled_rbs = (~disabled_rbs) & ((1UL<<(max_rb_num_per_se*se_num))-1);
- 
- 	adev->gfx.config.backend_enable_mask = enabled_rbs;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0298-drm-amdgpu-gfx7-Simplify-wptr-rptr-functions.patch b/common/recipes-kernel/linux/files/0298-drm-amdgpu-gfx7-Simplify-wptr-rptr-functions.patch
deleted file mode 100644
index 8af9cb30..00000000
--- a/common/recipes-kernel/linux/files/0298-drm-amdgpu-gfx7-Simplify-wptr-rptr-functions.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From d5c3076f344179387355e1efede457318c6a625a Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 8 Feb 2016 12:47:58 -0500
-Subject: [PATCH 0298/1110] drm/amdgpu/gfx7: Simplify wptr/rptr functions
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 23 ++++-------------------
- 1 file changed, 4 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 940dc0b..2cccd81 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2652,21 +2652,14 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
- 
- static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
- {
--	u32 rptr;
--
--	rptr = ring->adev->wb.wb[ring->rptr_offs];
--
--	return rptr;
-+	return ring->adev->wb.wb[ring->rptr_offs];
- }
- 
- static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
- {
- 	struct amdgpu_device *adev = ring->adev;
--	u32 wptr;
- 
--	wptr = RREG32(mmCP_RB0_WPTR);
--
--	return wptr;
-+	return RREG32(mmCP_RB0_WPTR);
- }
- 
- static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
-@@ -2679,21 +2672,13 @@ static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
- 
- static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
- {
--	u32 rptr;
--
--	rptr = ring->adev->wb.wb[ring->rptr_offs];
--
--	return rptr;
-+	return ring->adev->wb.wb[ring->rptr_offs];
- }
- 
- static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
- {
--	u32 wptr;
--
- 	/* XXX check if swapping is necessary on BE */
--	wptr = ring->adev->wb.wb[ring->wptr_offs];
--
--	return wptr;
-+	return ring->adev->wb.wb[ring->wptr_offs];
- }
- 
- static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0299-drm-amdgpu-gfx7-Fix-whitespace.patch b/common/recipes-kernel/linux/files/0299-drm-amdgpu-gfx7-Fix-whitespace.patch
deleted file mode 100644
index d6ac2385..00000000
--- a/common/recipes-kernel/linux/files/0299-drm-amdgpu-gfx7-Fix-whitespace.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 5458e539c310f9a8558ec51b6ab45fbec4da1cbc Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 8 Feb 2016 12:54:09 -0500
-Subject: [PATCH 0299/1110] drm/amdgpu/gfx7: Fix whitespace
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 2cccd81..409c6af 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -5303,7 +5303,7 @@ static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
- 
- 
- int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
--								   struct amdgpu_cu_info *cu_info)
-+			 struct amdgpu_cu_info *cu_info)
- {
- 	int i, j, k, counter, active_cu_number = 0;
- 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch b/common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch
deleted file mode 100644
index 0c09e7b2..00000000
--- a/common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 72968d3982b7af284da849909f4023432ba74a3f Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 10 Feb 2016 20:01:39 -0500
-Subject: [PATCH 0300/1110] drm/amd/include: Update dce 8 headers for dal
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h       |  1 +
- drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h | 12 ++++++++++++
- 2 files changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
-index dc52ea0..d3ccf5a 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
-@@ -1379,6 +1379,7 @@
- #define mmDC_GPIO_PAD_STRENGTH_1                                                0x1978
- #define mmDC_GPIO_PAD_STRENGTH_2                                                0x1979
- #define mmPHY_AUX_CNTL                                                          0x197f
-+#define mmDC_GPIO_I2CPAD_MASK                                                   0x1974
- #define mmDC_GPIO_I2CPAD_A                                                      0x1975
- #define mmDC_GPIO_I2CPAD_EN                                                     0x1976
- #define mmDC_GPIO_I2CPAD_Y                                                      0x1977
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
-index 8a29307..c331c9f 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
-@@ -4130,6 +4130,18 @@
- #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
- #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
- #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40
-+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6
- #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
- #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
- #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0301-drm-amdgpu-remove-the-userptr-rmn-lock.patch b/common/recipes-kernel/linux/files/0301-drm-amdgpu-remove-the-userptr-rmn-lock.patch
deleted file mode 100644
index 890f117e..00000000
--- a/common/recipes-kernel/linux/files/0301-drm-amdgpu-remove-the-userptr-rmn-lock.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 7dd3151852b73a79dc9ed8e3d4bb3a3c16ed927e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 9 Feb 2016 16:13:37 +0100
-Subject: [PATCH 0301/1110] drm/amdgpu: remove the userptr rmn->lock
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Avoid a lock inversion problem by just using the mmap_sem to
-protect the entries of the intervall tree.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 32 ++++++++++++--------------------
- 1 file changed, 12 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-index d4e2780..61f0e3c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-@@ -48,8 +48,7 @@ struct amdgpu_mn {
- 	/* protected by adev->mn_lock */
- 	struct hlist_node	node;
- 
--	/* objects protected by lock */
--	struct mutex		lock;
-+	/* objects protected by mm->mmap_sem */
- 	struct rb_root		objects;
- };
- 
-@@ -72,8 +71,8 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 	struct amdgpu_mn_node *node, *next_node;
- 	struct amdgpu_bo *bo, *next_bo;
- 
-+	down_write(&rmn->mm->mmap_sem);
- 	mutex_lock(&adev->mn_lock);
--	mutex_lock(&rmn->lock);
- 	hash_del(&rmn->node);
- 	rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects,
- 					     it.rb) {
-@@ -85,8 +84,8 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 		}
- 		kfree(node);
- 	}
--	mutex_unlock(&rmn->lock);
- 	mutex_unlock(&adev->mn_lock);
-+	up_write(&rmn->mm->mmap_sem);
- 	mmu_notifier_unregister(&rmn->mn, rmn->mm);
- 	kfree(rmn);
- }
-@@ -129,8 +128,6 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
- 	/* notification is exclusive, but interval is inclusive */
- 	end -= 1;
- 
--	mutex_lock(&rmn->lock);
--
- 	it = interval_tree_iter_first(&rmn->objects, start, end);
- 	while (it) {
- 		struct amdgpu_mn_node *node;
-@@ -165,8 +162,6 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
- 			amdgpu_bo_unreserve(bo);
- 		}
- 	}
--
--	mutex_unlock(&rmn->lock);
- }
- 
- static const struct mmu_notifier_ops amdgpu_mn_ops = {
-@@ -203,7 +198,6 @@ static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
- 	rmn->adev = adev;
- 	rmn->mm = mm;
- 	rmn->mn.ops = &amdgpu_mn_ops;
--	mutex_init(&rmn->lock);
- 	rmn->objects = RB_ROOT;
- 
- 	r = __mmu_notifier_register(&rmn->mn, mm);
-@@ -250,7 +244,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- 
- 	INIT_LIST_HEAD(&bos);
- 
--	mutex_lock(&rmn->lock);
-+	down_write(&rmn->mm->mmap_sem);
- 
- 	while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
- 		kfree(node);
-@@ -264,7 +258,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- 	if (!node) {
- 		node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
- 		if (!node) {
--			mutex_unlock(&rmn->lock);
-+			up_write(&rmn->mm->mmap_sem);
- 			return -ENOMEM;
- 		}
- 	}
-@@ -279,7 +273,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- 
- 	interval_tree_insert(&node->it, &rmn->objects);
- 
--	mutex_unlock(&rmn->lock);
-+	up_write(&rmn->mm->mmap_sem);
- 
- 	return 0;
- }
-@@ -294,17 +288,15 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- void amdgpu_mn_unregister(struct amdgpu_bo *bo)
- {
- 	struct amdgpu_device *adev = bo->adev;
--	struct amdgpu_mn *rmn;
-+	struct amdgpu_mn *rmn = bo->mn;
- 	struct list_head *head;
- 
--	mutex_lock(&adev->mn_lock);
--	rmn = bo->mn;
--	if (rmn == NULL) {
--		mutex_unlock(&adev->mn_lock);
-+	if (rmn == NULL)
- 		return;
--	}
- 
--	mutex_lock(&rmn->lock);
-+	down_write(&rmn->mm->mmap_sem);
-+	mutex_lock(&adev->mn_lock);
-+
- 	/* save the next list entry for later */
- 	head = bo->mn_list.next;
- 
-@@ -318,6 +310,6 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
- 		kfree(node);
- 	}
- 
--	mutex_unlock(&rmn->lock);
- 	mutex_unlock(&adev->mn_lock);
-+	up_write(&rmn->mm->mmap_sem);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0302-drm-amdgpu-use-per-VM-entity-for-page-table-updates-.patch b/common/recipes-kernel/linux/files/0302-drm-amdgpu-use-per-VM-entity-for-page-table-updates-.patch
deleted file mode 100644
index 6d64ac8d..00000000
--- a/common/recipes-kernel/linux/files/0302-drm-amdgpu-use-per-VM-entity-for-page-table-updates-.patch
+++ /dev/null
@@ -1,227 +0,0 @@
-From 5d7d7a1ff3f0f07db6cfc158a5896d321ce26776 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 1 Feb 2016 12:53:58 +0100
-Subject: [PATCH 0302/1110] drm/amdgpu: use per VM entity for page table
- updates (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Updates from different VMs can be processed independently.
-
-v2: agd: rebase on upstream
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  6 ++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 ++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 48 ++++++++++++++++++++++-----------
- 5 files changed, 46 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index c882c7c..08e771d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -758,7 +758,8 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
- 
- void amdgpu_job_free(struct amdgpu_job *job);
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
--                      void *owner, struct fence **f);
-+                      struct amd_sched_entity *entity, void *owner,
-+                      struct fence **f);
- 
- struct amdgpu_ring {
- 	struct amdgpu_device		*adev;
-@@ -876,6 +877,9 @@ struct amdgpu_vm {
- 
- 	/* protecting freed */
- 	spinlock_t		freed_lock;
-+
-+        /* Scheduler entity for page table updates */
-+        struct amd_sched_entity entity;
- };
- 
- struct amdgpu_vm_manager_id {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index fda8ebc..a16c43f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -80,13 +80,17 @@ void amdgpu_job_free(struct amdgpu_job *job)
- }
- 
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
--                     void *owner, struct fence **f)
-+                      struct amd_sched_entity *entity, void *owner,
-+                      struct fence **f)
- {
-        struct amdgpu_device *adev = job->adev;
-+       
-+	if (!entity)
-+               entity = &adev->kernel_ctx.rings[ring->idx].entity;
- 
-        job->ring = ring;
-        job->base.sched = &ring->sched;
--       job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
-+       job->base.s_entity = entity;
-        job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner);
-        if (!job->base.s_fence)
-                return -ENOMEM;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 8b11edc..4acfddf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -900,7 +900,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 
-                 amdgpu_job_free(job);
-         } else {
--                r = amdgpu_job_submit(job, ring,
-+                r = amdgpu_job_submit(job, ring, NULL,
-                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-                 if (r)
-                         goto err_free;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 5564a46..4239083 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -508,7 +508,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 
-                 amdgpu_job_free(job);
-         } else {
--                r = amdgpu_job_submit(job, ring,
-+                r = amdgpu_job_submit(job, ring, NULL,
-                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-                 if (r)
-                         goto err;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8877f15..b99afc3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -329,6 +329,7 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
-  * need to reserve bo first before calling it.
-  */
- static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
-+                              struct amdgpu_vm *vm,
- 			      struct amdgpu_bo *bo)
- {
- 	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
-@@ -357,7 +358,8 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
-         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
- 
-         WARN_ON(job->ibs[0].length_dw > 64);
--        r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &fence);
-+        r = amdgpu_job_submit(job, ring, &vm->entity,
-+                              AMDGPU_FENCE_OWNER_VM, &fence);
- 	if (r)
- 		goto error_free;
- 
-@@ -479,7 +481,8 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-                 amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
-                                  AMDGPU_FENCE_OWNER_VM);
- 		WARN_ON(ib->length_dw > ndw);
--                r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &fence);
-+                r = amdgpu_job_submit(job, ring, &vm->entity,
-+                                      AMDGPU_FENCE_OWNER_VM, &fence);
- 		if (r)
- 			goto error_free;
- 
-@@ -735,7 +738,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 
-         amdgpu_ring_pad_ib(ring, ib);
- 	WARN_ON(ib->length_dw > ndw);
--        r = amdgpu_job_submit(job, ring, AMDGPU_FENCE_OWNER_VM, &f);
-+        r = amdgpu_job_submit(job, ring, &vm->entity,
-+                              AMDGPU_FENCE_OWNER_VM, &f);
- 	if (r)
- 		goto error_free;
- 
-@@ -1110,7 +1114,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 		 */
- 		pt->parent = amdgpu_bo_ref(vm->page_directory);
- 
--		r = amdgpu_vm_clear_bo(adev, pt);
-+                r = amdgpu_vm_clear_bo(adev, vm, pt);
- 		if (r) {
- 			amdgpu_bo_unref(&pt);
- 			goto error_free;
-@@ -1271,9 +1275,11 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
-  */
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
-+        struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
- 		AMDGPU_VM_PTE_COUNT * 8);
- 	unsigned pd_size, pd_entries;
-+        struct amd_sched_rq *rq;
- 	int i, r;
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-@@ -1297,6 +1303,13 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 		return -ENOMEM;
- 	}
- 
-+        /* create scheduler entity for page table updates */
-+        rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
-+        r = amd_sched_entity_init(&ring->sched, &vm->entity,
-+                                  rq, amdgpu_sched_jobs);
-+        if (r)
-+                return r;
-+
- 	vm->page_directory_fence = NULL;
- 
- 	r = amdgpu_bo_create(adev, pd_size, align, true,
-@@ -1304,22 +1317,24 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 			     AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
- 			     NULL, NULL, &vm->page_directory);
- 	if (r)
--		return r;
-+                goto error_free_sched_entity;
-+
- 	r = amdgpu_bo_reserve(vm->page_directory, false);
--	if (r) {
--		amdgpu_bo_unref(&vm->page_directory);
--		vm->page_directory = NULL;
--		return r;
--	}
- 	r = amdgpu_vm_clear_bo(adev, vm->page_directory);
- 	amdgpu_bo_unreserve(vm->page_directory);
--	if (r) {
--		amdgpu_bo_unref(&vm->page_directory);
--		vm->page_directory = NULL;
--		return r;
--	}
-+        if (r)
-+                goto error_free_page_directory;
- 
- 	return 0;
-+
-+error_free_page_directory:
-+        amdgpu_bo_unref(&vm->page_directory);
-+        vm->page_directory = NULL;
-+
-+error_free_sched_entity:
-+        amd_sched_entity_fini(&ring->sched, &vm->entity);
-+
-+       return r;
- }
- 
- /**
-@@ -1333,9 +1348,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
-  */
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
-+        struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	struct amdgpu_bo_va_mapping *mapping, *tmp;
- 	int i;
- 
-+        amd_sched_entity_fini(&ring->sched, &vm->entity);
-+
- 	if (!RB_EMPTY_ROOT(&vm->va)) {
- 		dev_err(adev->dev, "still active bo inside vm\n");
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0303-drm-amdgpu-remove-is_pte_ring.patch b/common/recipes-kernel/linux/files/0303-drm-amdgpu-remove-is_pte_ring.patch
deleted file mode 100644
index 62f8c832..00000000
--- a/common/recipes-kernel/linux/files/0303-drm-amdgpu-remove-is_pte_ring.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 4da266aa5b79ee6c165c00bef756fb81c99f08e6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 8 Feb 2016 14:08:44 +0100
-Subject: [PATCH 0303/1110] drm/amdgpu: remove is_pte_ring
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used for anything.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 -
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 1 -
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 -
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 -
- 4 files changed, 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 08e771d..fa438c1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -796,7 +796,6 @@ struct amdgpu_ring {
- 	struct amdgpu_ctx	*current_ctx;
- 	enum amdgpu_ring_type	type;
- 	char			name[16];
--	bool                    is_pte_ring;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 2accc7c..923a340 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -1374,6 +1374,5 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
- 		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
--		adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index bf5c4f1..3607cb8 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -1379,6 +1379,5 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
- 		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
--		adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index cdb9a9f..2338a29 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1646,6 +1646,5 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
- 		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
--		adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0304-drm-amdgpu-use-SDMA-round-robin-for-VM-updates-v3.patch b/common/recipes-kernel/linux/files/0304-drm-amdgpu-use-SDMA-round-robin-for-VM-updates-v3.patch
deleted file mode 100644
index 0fa114d7..00000000
--- a/common/recipes-kernel/linux/files/0304-drm-amdgpu-use-SDMA-round-robin-for-VM-updates-v3.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From da2782438e2a41061e60a705ffd29ec9284c8f45 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 8 Feb 2016 17:37:38 +0100
-Subject: [PATCH 0304/1110] drm/amdgpu: use SDMA round robin for VM updates v3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Distribute the load on both rings.
-
-v2: use a loop for the initialization
-v3: agd: rebase on upstream
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 +++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 24 +++++++++++++++++++-----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c      |  8 +++++++-
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c     |  8 +++++++-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     |  8 +++++++-
- 6 files changed, 44 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index fa438c1..fd00d29 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -901,7 +901,9 @@ struct amdgpu_vm_manager {
- 	bool					enabled;
- 	/* vm pte handling */
- 	const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
--	struct amdgpu_ring                      *vm_pte_funcs_ring;
-+        struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
-+        unsigned                                vm_pte_num_rings;
-+        atomic_t                                vm_pte_next_ring;
- };
- 
- void amdgpu_vm_manager_init(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index b8b132f..e70c4e9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1402,7 +1402,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	adev->num_rings = 0;
- 	adev->mman.buffer_funcs = NULL;
- 	adev->mman.buffer_funcs_ring = NULL;
--	adev->vm_manager.vm_pte_funcs = NULL;
-+        adev->vm_manager.vm_pte_num_rings = 0;
- 	adev->vm_manager.vm_pte_funcs_ring = NULL;
- 	adev->gart.gart_funcs = NULL;
- 	adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index b99afc3..8e6786c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -332,13 +332,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
-                               struct amdgpu_vm *vm,
- 			      struct amdgpu_bo *bo)
- {
--	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
-+        struct amdgpu_ring *ring;
- 	struct fence *fence = NULL;
-         struct amdgpu_job *job;
- 	unsigned entries;
- 	uint64_t addr;
- 	int r;
- 
-+        ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-+
- 	r = reservation_object_reserve_shared(bo->tbo.resv);
- 	if (r)
- 		return r;
-@@ -418,7 +420,7 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm)
- {
--	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
-+        struct amdgpu_ring *ring;
- 	struct amdgpu_bo *pd = vm->page_directory;
- 	uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
- 	uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
-@@ -429,6 +431,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 	struct fence *fence = NULL;
- 
- 	int r;
-+        ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
- 
- 	/* padding, etc. */
- 	ndw = 64;
-@@ -676,7 +679,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 				       uint32_t flags, uint64_t addr,
- 				       struct fence **fence)
- {
--	struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
-+        struct amdgpu_ring *ring;
-         void *owner = AMDGPU_FENCE_OWNER_VM;
- 	unsigned nptes, ncmds, ndw;
-         struct amdgpu_job *job;
-@@ -684,6 +687,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	struct fence *f = NULL;
- 	int r;
- 
-+        ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-+
-         /* sync to everything on unmapping */
-         if (!(flags & AMDGPU_PTE_VALID))
-                 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
-@@ -1279,6 +1284,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
- 		AMDGPU_VM_PTE_COUNT * 8);
- 	unsigned pd_size, pd_entries;
-+        unsigned ring_instance;
-+        struct amdgpu_ring *ring;
-+
-         struct amd_sched_rq *rq;
- 	int i, r;
- 
-@@ -1304,6 +1312,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	}
- 
-         /* create scheduler entity for page table updates */
-+
-+        ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
-+        ring_instance %= adev->vm_manager.vm_pte_num_rings;
-+        ring = adev->vm_manager.vm_pte_rings[ring_instance];
-         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
-         r = amd_sched_entity_init(&ring->sched, &vm->entity,
-                                   rq, amdgpu_sched_jobs);
-@@ -1348,11 +1360,10 @@ error_free_sched_entity:
-  */
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
--        struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	struct amdgpu_bo_va_mapping *mapping, *tmp;
- 	int i;
- 
--        amd_sched_entity_fini(&ring->sched, &vm->entity);
-+        amd_sched_entity_fini(vm->entity.sched, &vm->entity);
- 
- 	if (!RB_EMPTY_ROOT(&vm->va)) {
- 		dev_err(adev->dev, "still active bo inside vm\n");
-@@ -1400,6 +1411,9 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 	for (i = 1; i < adev->vm_manager.num_ids; ++i)
- 		list_add_tail(&adev->vm_manager.ids[i].list,
- 			      &adev->vm_manager.ids_lru);
-+
-+        atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
-+
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 923a340..fefb365 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -1371,8 +1371,14 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
- 
- static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
- {
-+        unsigned i;
-+
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
--		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
-+                for (i = 0; i < adev->sdma.num_instances; i++)
-+                        adev->vm_manager.vm_pte_rings[i] =
-+                                &adev->sdma.instance[i].ring;
-+ 
-+                adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 3607cb8..1f9ba74 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -1376,8 +1376,14 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
- 
- static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
- {
-+        unsigned i;
-+
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
--		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
-+               for (i = 0; i < adev->sdma.num_instances; i++)
-+                       adev->vm_manager.vm_pte_rings[i] =
-+                               &adev->sdma.instance[i].ring;
-+ 
-+                adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 2338a29..f0943bb 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1643,8 +1643,14 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
- 
- static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
- {
-+        unsigned i;
-+
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
--		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
-+                for (i = 0; i < adev->sdma.num_instances; i++)
-+                        adev->vm_manager.vm_pte_rings[i] =
-+                                &adev->sdma.instance[i].ring;
-+
-+                adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0305-drm-amdgpu-use-separate-scheduler-entitiy-for-buffer.patch b/common/recipes-kernel/linux/files/0305-drm-amdgpu-use-separate-scheduler-entitiy-for-buffer.patch
deleted file mode 100644
index 9da1ab01..00000000
--- a/common/recipes-kernel/linux/files/0305-drm-amdgpu-use-separate-scheduler-entitiy-for-buffer.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 4daaf81885958741dd2b113f080f935bf13889de Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 10 Feb 2016 14:20:50 +0100
-Subject: [PATCH 0305/1110] drm/amdgpu: use separate scheduler entitiy for
- buffer moves
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows us to remove the global kernel context.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 ++++++++++++++++
- 2 files changed, 18 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index fd00d29..a6b4b03 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -417,6 +417,8 @@ struct amdgpu_mman {
- 	/* buffer handling */
- 	const struct amdgpu_buffer_funcs	*buffer_funcs;
- 	struct amdgpu_ring			*buffer_funcs_ring;
-+        /* Scheduler entity for buffer moves */
-+        struct amd_sched_entity                 entity;
- };
- 
- int amdgpu_copy_buffer(struct amdgpu_ring *ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 7355007..e5a684e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -77,6 +77,8 @@ static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
- static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
- {
- 	struct drm_global_reference *global_ref;
-+        struct amdgpu_ring *ring;
-+        struct amd_sched_rq *rq;
- 	int r;
- 
- 	adev->mman.mem_global_referenced = false;
-@@ -106,13 +108,27 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
- 		return r;
- 	}
- 
-+        ring = adev->mman.buffer_funcs_ring;
-+        rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
-+        r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
-+                                  rq, amdgpu_sched_jobs);
-+        if (r != 0) {
-+                DRM_ERROR("Failed setting up TTM BO move run queue.\n");
-+                drm_global_item_unref(&adev->mman.mem_global_ref);
-+                drm_global_item_unref(&adev->mman.bo_global_ref.ref);
-+                return r;
-+        }
-+
- 	adev->mman.mem_global_referenced = true;
-+
- 	return 0;
- }
- 
- static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
- {
- 	if (adev->mman.mem_global_referenced) {
-+                amd_sched_entity_fini(adev->mman.entity.sched,
-+                                      &adev->mman.entity);
- 		drm_global_item_unref(&adev->mman.bo_global_ref.ref);
- 		drm_global_item_unref(&adev->mman.mem_global_ref);
- 		adev->mman.mem_global_referenced = false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0306-drm-amdgpu-use-separate-scheduler-entity-for-UVD-sub.patch b/common/recipes-kernel/linux/files/0306-drm-amdgpu-use-separate-scheduler-entity-for-UVD-sub.patch
deleted file mode 100644
index 4275b1b6..00000000
--- a/common/recipes-kernel/linux/files/0306-drm-amdgpu-use-separate-scheduler-entity-for-UVD-sub.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 8fa4dfddd15bd915d66dae88aba8326df2189d32 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 10 Feb 2016 14:35:19 +0100
-Subject: [PATCH 0306/1110] drm/amdgpu: use separate scheduler entity for UVD
- submissions
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows us to remove the kernel context and use a better
-priority for the submissions.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 12 ++++++++++++
- 2 files changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a6b4b03..5db8e71 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1608,6 +1608,7 @@ struct amdgpu_uvd {
- 	struct amdgpu_ring	ring;
- 	struct amdgpu_irq_src	irq;
- 	bool			address_64_bit;
-+        struct amd_sched_entity entity;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 4acfddf..726f0cb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -91,6 +91,8 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
- 
- int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- {
-+        struct amdgpu_ring *ring;
-+        struct amd_sched_rq *rq;
- 	unsigned long bo_size;
- 	const char *fw_name;
- 	const struct common_firmware_header *hdr;
-@@ -193,6 +195,15 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- 	}
- 
- 	amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
-+ 
-+        ring = &adev->uvd.ring;
-+        rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+        r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
-+                                  rq, amdgpu_sched_jobs);
-+        if (r != 0) {
-+                DRM_ERROR("Failed setting up UVD run queue.\n");
-+                return r;
-+        }
- 
- 	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
- 		atomic_set(&adev->uvd.handles[i], 0);
-@@ -212,6 +223,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- 
- 	if (adev->uvd.vcpu_bo == NULL)
- 		return 0;
-+        amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
- 
- 	r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
- 	if (!r) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0307-drm-amdgpu-use-separate-scheduler-entity-for-VCE-sub.patch b/common/recipes-kernel/linux/files/0307-drm-amdgpu-use-separate-scheduler-entity-for-VCE-sub.patch
deleted file mode 100644
index 62def6ed..00000000
--- a/common/recipes-kernel/linux/files/0307-drm-amdgpu-use-separate-scheduler-entity-for-VCE-sub.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From b34557f0e92a2845169ae3bbda078d120e702722 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 10 Feb 2016 17:43:00 +0100
-Subject: [PATCH 0307/1110] drm/amdgpu: use separate scheduler entity for VCE
- submissions
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows us to remove the kernel context and use a better
-priority for the submissions.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 16 +++++++++++++++-
- 2 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 5db8e71..84ee4fe 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1633,6 +1633,7 @@ struct amdgpu_vce {
- 	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
- 	struct amdgpu_irq_src	irq;
- 	unsigned		harvest_config;
-+	struct amd_sched_entity	entity;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 4239083..547e084 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -74,6 +74,8 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work);
-  */
- int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
- {
-+        struct amdgpu_ring *ring;
-+        struct amd_sched_rq *rq;
- 	const char *fw_name;
- 	const struct common_firmware_header *hdr;
- 	unsigned ucode_version, version_major, version_minor, binary_id;
-@@ -170,6 +172,16 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
- 		return r;
- 	}
- 
-+
-+       ring = &adev->vce.ring[0];
-+       rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+       r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
-+                                 rq, amdgpu_sched_jobs);
-+       if (r != 0) {
-+               DRM_ERROR("Failed setting up VCE run queue.\n");
-+               return r;
-+       }
-+
- 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
- 		atomic_set(&adev->vce.handles[i], 0);
- 		adev->vce.filp[i] = NULL;
-@@ -190,6 +202,8 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
- 	if (adev->vce.vcpu_bo == NULL)
- 		return 0;
- 
-+        amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
-+
- 	amdgpu_bo_unref(&adev->vce.vcpu_bo);
- 
- 	amdgpu_ring_fini(&adev->vce.ring[0]);
-@@ -508,7 +522,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 
-                 amdgpu_job_free(job);
-         } else {
--                r = amdgpu_job_submit(job, ring, NULL,
-+                r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
-                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-                 if (r)
-                         goto err;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0308-drm-amdgpu-nuke-the-kernel-context.patch b/common/recipes-kernel/linux/files/0308-drm-amdgpu-nuke-the-kernel-context.patch
deleted file mode 100644
index 357de07e..00000000
--- a/common/recipes-kernel/linux/files/0308-drm-amdgpu-nuke-the-kernel-context.patch
+++ /dev/null
@@ -1,139 +0,0 @@
-From f966a597c252ae36b89a07d7b0460449bcb680c7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 11 Feb 2016 09:56:44 +0100
-Subject: [PATCH 0308/1110] drm/amdgpu: nuke the kernel context
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  7 -------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c    | 18 +++++++-----------
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  6 ------
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c    |  5 -----
- 4 files changed, 7 insertions(+), 29 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 84ee4fe..e33c5a6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -983,10 +983,6 @@ struct amdgpu_ctx_mgr {
- 	struct idr		ctx_handles;
- };
- 
--int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
--		    struct amdgpu_ctx *ctx);
--void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
--
- struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
- int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
- 
-@@ -2050,9 +2046,6 @@ struct amdgpu_device {
- 	/* amdkfd interface */
- 	struct kfd_dev          *kfd;
- 
--	/* kernel conext for IB submission */
--	struct amdgpu_ctx	kernel_ctx;
--
- 	struct amdgpu_virtualization virtualization;
- };
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index f1f4b45..3b99282 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -25,8 +25,7 @@
- #include <drm/drmP.h>
- #include "amdgpu.h"
- 
--int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
--		    struct amdgpu_ctx *ctx)
-+static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
- {
- 	unsigned i, j;
- 	int r;
-@@ -47,14 +46,11 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 	}
- 	/* create context entity for each ring */
- 	for (i = 0; i < adev->num_rings; i++) {
-+		struct amdgpu_ring *ring = adev->rings[i];
- 		struct amd_sched_rq *rq;
--		if (pri >= AMD_SCHED_MAX_PRIORITY) {
--			kfree(ctx->fences);
--			return -EINVAL;
--		}
--		rq = &adev->rings[i]->sched.sched_rq[pri];
--		r = amd_sched_entity_init(&adev->rings[i]->sched,
--					  &ctx->rings[i].entity,
-+
-+		rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+		r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
- 					  rq, amdgpu_sched_jobs);
- 		if (r)
- 			break;
-@@ -70,7 +66,7 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- 	return 0;
- }
- 
--void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
-+static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
- {
- 	struct amdgpu_device *adev = ctx->adev;
- 	unsigned i, j;
-@@ -108,7 +104,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
- 		return r;
- 	}
- 	*id = (uint32_t)r;
--	r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_NORMAL, ctx);
-+	r = amdgpu_ctx_init(adev, ctx);
- 	if (r) {
- 		idr_remove(&mgr->ctx_handles, *id);
- 		*id = 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index e70c4e9..736d560 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1551,11 +1551,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 		return r;
- 	}
- 
--	r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_KERNEL, &adev->kernel_ctx);
--	if (r) {
--		dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
--		return r;
--	}
- 	r = amdgpu_ib_ring_tests(adev);
- 	if (r)
- 		DRM_ERROR("ib ring test failed (%d).\n", r);
-@@ -1619,7 +1614,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
- 	adev->shutdown = true;
- 	/* evict vram memory */
- 	amdgpu_bo_evict_vram(adev);
--	amdgpu_ctx_fini(&adev->kernel_ctx);
- 	amdgpu_ib_pool_fini(adev);
- 	amdgpu_fence_driver_fini(adev);
- 	amdgpu_fbdev_fini(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index a16c43f..10ff227 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -83,11 +83,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-                       struct amd_sched_entity *entity, void *owner,
-                       struct fence **f)
- {
--       struct amdgpu_device *adev = job->adev;
--       
--	if (!entity)
--               entity = &adev->kernel_ctx.rings[ring->idx].entity;
--
-        job->ring = ring;
-        job->base.sched = &ring->sched;
-        job->base.s_entity = entity;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0309-drm-amdgpu-fix-coding-style-in-amdgpu_ctx.c.patch b/common/recipes-kernel/linux/files/0309-drm-amdgpu-fix-coding-style-in-amdgpu_ctx.c.patch
deleted file mode 100644
index c7466755..00000000
--- a/common/recipes-kernel/linux/files/0309-drm-amdgpu-fix-coding-style-in-amdgpu_ctx.c.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From b6cdba4bc3d2897462b23b85706beed535bdd602 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 11 Feb 2016 10:20:53 +0100
-Subject: [PATCH 0309/1110] drm/amdgpu: fix coding style in amdgpu_ctx.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Don't use pointer arithmetic and fix the indentation.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 31 +++++++++++++++----------------
- 1 file changed, 15 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index 3b99282..17e1362 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -34,15 +34,14 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
- 	ctx->adev = adev;
- 	kref_init(&ctx->refcount);
- 	spin_lock_init(&ctx->ring_lock);
--	ctx->fences = kzalloc(sizeof(struct fence *) * amdgpu_sched_jobs *
--			 AMDGPU_MAX_RINGS, GFP_KERNEL);
-+	ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
-+			      sizeof(struct fence*), GFP_KERNEL);
- 	if (!ctx->fences)
- 		return -ENOMEM;
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 		ctx->rings[i].sequence = 1;
--		ctx->rings[i].fences = (void *)ctx->fences + sizeof(struct fence *) *
--			amdgpu_sched_jobs * i;
-+		ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
- 	}
- 	/* create context entity for each ring */
- 	for (i = 0; i < adev->num_rings; i++) {
-@@ -192,18 +191,18 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
- 	id = args->in.ctx_id;
- 
- 	switch (args->in.op) {
--		case AMDGPU_CTX_OP_ALLOC_CTX:
--			r = amdgpu_ctx_alloc(adev, fpriv, &id);
--			args->out.alloc.ctx_id = id;
--			break;
--		case AMDGPU_CTX_OP_FREE_CTX:
--			r = amdgpu_ctx_free(fpriv, id);
--			break;
--		case AMDGPU_CTX_OP_QUERY_STATE:
--			r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
--			break;
--		default:
--			return -EINVAL;
-+	case AMDGPU_CTX_OP_ALLOC_CTX:
-+		r = amdgpu_ctx_alloc(adev, fpriv, &id);
-+		args->out.alloc.ctx_id = id;
-+		break;
-+	case AMDGPU_CTX_OP_FREE_CTX:
-+		r = amdgpu_ctx_free(fpriv, id);
-+		break;
-+	case AMDGPU_CTX_OP_QUERY_STATE:
-+		r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
-+		break;
-+	default:
-+		return -EINVAL;
- 	}
- 
- 	return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0310-drm-amdgpu-gfx-clean-up-harvest-configuration-v2.patch b/common/recipes-kernel/linux/files/0310-drm-amdgpu-gfx-clean-up-harvest-configuration-v2.patch
deleted file mode 100644
index d2751c5f..00000000
--- a/common/recipes-kernel/linux/files/0310-drm-amdgpu-gfx-clean-up-harvest-configuration-v2.patch
+++ /dev/null
@@ -1,476 +0,0 @@
-From 757050ee4e2166ab406163e584e61a85417231a0 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 12 Feb 2016 00:39:13 -0500
-Subject: [PATCH 0310/1110] drm/amdgpu/gfx: clean up harvest configuration (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read back harvest configuration from registers and simplify
-calculations.  No need to program the raster config registers.
-These are programmed as golden registers and the user mode
-drivers program them as well.
-
-v2: rebase on Tom's patches
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |   1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |   3 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 127 ++++++++++---------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 131 ++++++++++----------------------
- 4 files changed, 82 insertions(+), 180 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e33c5a6..d56dc9c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1097,6 +1097,7 @@ struct amdgpu_gca_config {
- 	unsigned multi_gpu_tile_size;
- 	unsigned mc_arb_ramcfg;
- 	unsigned gb_addr_config;
-+	unsigned num_rbs;
- 
- 	uint32_t tile_mode_array[32];
- 	uint32_t macrotile_mode_array[16];
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index ab58187..c825880 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -447,8 +447,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- 			dev_info.max_memory_clock = adev->pm.default_mclk * 10;
- 		}
- 		dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
--		dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
--					adev->gfx.config.max_shader_engines;
-+		dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
- 		dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
- 		dev_info._pad = 0;
- 		dev_info.ids_flags = 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 409c6af..55c38fb 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1598,39 +1598,31 @@ void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
-  */
- static u32 gfx_v7_0_create_bitmask(u32 bit_width)
- {
--	return (u32)((1ULL<<bit_width)-1);
-+	return (u32)((1ULL << bit_width) - 1);
- }
- 
- /**
-- * gfx_v7_0_get_rb_disabled - computes the mask of disabled RBs
-+ * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
-  *
-  * @adev: amdgpu_device pointer
-- * @max_rb_num: max RBs (render backends) for the asic
-- * @se_num: number of SEs (shader engines) for the asic
-- * @sh_per_se: number of SH blocks per SE for the asic
-  *
-- * Calculates the bitmask of disabled RBs (CIK).
-- * Returns the disabled RB bitmask.
-+ * Calculates the bitmask of enabled RBs (CIK).
-+ * Returns the enabled RB bitmask.
-  */
--static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev,
--				    u32 max_rb_num_per_se,
--				    u32 sh_per_se)
-+static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
- {
- 	u32 data, mask;
- 
- 	data = RREG32(mmCC_RB_BACKEND_DISABLE);
--	if (data & 1)
--		data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
--	else
--		data = 0;
--
- 	data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
- 
-+	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
- 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
- 
--	mask = gfx_v7_0_create_bitmask(max_rb_num_per_se / sh_per_se);
-+	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-+				       adev->gfx.config.max_sh_per_se);
- 
--	return data & mask;
-+	return (~data) & mask;
- }
- 
- /**
-@@ -1639,68 +1631,36 @@ static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev,
-  * @adev: amdgpu_device pointer
-  * @se_num: number of SEs (shader engines) for the asic
-  * @sh_per_se: number of SH blocks per SE for the asic
-- * @max_rb_num: max RBs (render backends) for the asic
-  *
-  * Configures per-SE/SH RB registers (CIK).
-  */
--static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
--			      u32 se_num, u32 sh_per_se,
--			      u32 max_rb_num_per_se)
-+static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
- {
- 	int i, j;
--	u32 data;
--	u32 disabled_rbs = 0;
--	u32 enabled_rbs = 0;
-+	u32 data, tmp, num_rbs = 0;
-+	u32 active_rbs = 0;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
--	for (i = 0; i < se_num; i++) {
--		for (j = 0; j < sh_per_se; j++) {
-+	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
-+		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
- 			gfx_v7_0_select_se_sh(adev, i, j);
--			data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
-+			data = gfx_v7_0_get_rb_active_bitmap(adev);
- 			if (adev->asic_type == CHIP_HAWAII)
--				disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
-+				active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
-+						       HAWAII_RB_BITMAP_WIDTH_PER_SH);
- 			else
--				disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
-+				active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
-+						       CIK_RB_BITMAP_WIDTH_PER_SH);
- 		}
- 	}
- 	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
- 	mutex_unlock(&adev->grbm_idx_mutex);
- 
--	enabled_rbs = (~disabled_rbs) & ((1UL<<(max_rb_num_per_se*se_num))-1);
--
--	adev->gfx.config.backend_enable_mask = enabled_rbs;
--
--	mutex_lock(&adev->grbm_idx_mutex);
--	for (i = 0; i < se_num; i++) {
--		gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
--		data = 0;
--		for (j = 0; j < sh_per_se; j++) {
--			switch (enabled_rbs & 3) {
--			case 0:
--				if (j == 0)
--					data |= (RASTER_CONFIG_RB_MAP_3 <<
--						PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
--				else
--					data |= (RASTER_CONFIG_RB_MAP_0 <<
--						PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
--				break;
--			case 1:
--				data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
--				break;
--			case 2:
--				data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
--				break;
--			case 3:
--			default:
--				data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
--				break;
--			}
--			enabled_rbs >>= 2;
--		}
--		WREG32(mmPA_SC_RASTER_CONFIG, data);
--	}
--	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
--	mutex_unlock(&adev->grbm_idx_mutex);
-+	adev->gfx.config.backend_enable_mask = active_rbs;
-+	tmp = active_rbs;
-+	while (tmp >>= 1)
-+		num_rbs++;
-+	adev->gfx.config.num_rbs = num_rbs;
- }
- 
- /**
-@@ -1931,9 +1891,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
- 
- 	gfx_v7_0_tiling_mode_table_init(adev);
- 
--	gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
--			  adev->gfx.config.max_sh_per_se,
--			  adev->gfx.config.max_backends_per_se);
-+	gfx_v7_0_setup_rb(adev);
- 
- 	/* set HW defaults for 3D engine */
- 	WREG32(mmCP_MEQ_THRESHOLDS,
-@@ -4039,28 +3997,20 @@ static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
- 	}
- }
- 
--static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev,
--					 u32 se, u32 sh)
-+static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
- {
--	u32 mask = 0, tmp, tmp1;
--	int i;
--
--	gfx_v7_0_select_se_sh(adev, se, sh);
--	tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
--	tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
--	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-+	u32 data, mask;
- 
--	tmp &= 0xffff0000;
-+	data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
-+	data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
- 
--	tmp |= tmp1;
--	tmp >>= 16;
-+	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
-+	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
- 
--	for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
--		mask <<= 1;
--		mask |= 1;
--	}
-+	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-+				       adev->gfx.config.max_sh_per_se);
- 
--	return (~tmp) & mask;
-+	return (~data) & mask;
- }
- 
- static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
-@@ -5317,10 +5267,11 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
- 			mask = 1;
- 			ao_bitmap = 0;
- 			counter = 0;
--			bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j);
-+			gfx_v7_0_select_se_sh(adev, i, j);
-+			bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
- 			cu_info->bitmap[i][j] = bitmap;
- 
--			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
-+			for (k = 0; k < 16; k ++) {
- 				if (bitmap & mask) {
- 					if (counter < 2)
- 						ao_bitmap |= mask;
-@@ -5332,9 +5283,11 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
- 			ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
- 		}
- 	}
-+	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-+	mutex_unlock(&adev->grbm_idx_mutex);
- 
- 	cu_info->number = active_cu_number;
- 	cu_info->ao_cu_mask = ao_cu_mask;
--	mutex_unlock(&adev->grbm_idx_mutex);
-+
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 1b5abdb..5e04140 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2572,11 +2572,6 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 	}
- }
- 
--static u32 gfx_v8_0_create_bitmask(u32 bit_width)
--{
--	return (u32)((1ULL << bit_width) - 1);
--}
--
- void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
- {
- 	u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
-@@ -2597,89 +2592,50 @@ void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
- 	WREG32(mmGRBM_GFX_INDEX, data);
- }
- 
--static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
--				    u32 max_rb_num_per_se,
--				    u32 sh_per_se)
-+static u32 gfx_v8_0_create_bitmask(u32 bit_width)
-+{
-+	return (u32)((1ULL << bit_width) - 1);
-+}
-+
-+static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
- {
- 	u32 data, mask;
- 
- 	data = RREG32(mmCC_RB_BACKEND_DISABLE);
--	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
--
- 	data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
- 
-+	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
- 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
- 
--	mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
-+	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-+				       adev->gfx.config.max_sh_per_se);
- 
--	return data & mask;
-+	return (~data) & mask;
- }
- 
--static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
--			      u32 se_num, u32 sh_per_se,
--			      u32 max_rb_num_per_se)
-+static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
- {
- 	int i, j;
--	u32 data, mask;
--	u32 disabled_rbs = 0;
--	u32 enabled_rbs = 0;
-+	u32 data, tmp, num_rbs = 0;
-+	u32 active_rbs = 0;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
--	for (i = 0; i < se_num; i++) {
--		for (j = 0; j < sh_per_se; j++) {
-+	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
-+		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
- 			gfx_v8_0_select_se_sh(adev, i, j);
--			data = gfx_v8_0_get_rb_disabled(adev,
--					      max_rb_num_per_se, sh_per_se);
--			disabled_rbs |= data << ((i * sh_per_se + j) *
--						 RB_BITMAP_WIDTH_PER_SH);
-+			data = gfx_v8_0_get_rb_active_bitmap(adev);
-+			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
-+					       RB_BITMAP_WIDTH_PER_SH);
- 		}
- 	}
- 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
- 	mutex_unlock(&adev->grbm_idx_mutex);
- 
--	mask = 1;
--	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
--		if (!(disabled_rbs & mask))
--			enabled_rbs |= mask;
--		mask <<= 1;
--	}
--
--	adev->gfx.config.backend_enable_mask = enabled_rbs;
--
--	mutex_lock(&adev->grbm_idx_mutex);
--	for (i = 0; i < se_num; i++) {
--		gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
--		data = RREG32(mmPA_SC_RASTER_CONFIG);
--		for (j = 0; j < sh_per_se; j++) {
--			switch (enabled_rbs & 3) {
--			case 0:
--				if (j == 0)
--					data |= (RASTER_CONFIG_RB_MAP_3 <<
--						 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
--				else
--					data |= (RASTER_CONFIG_RB_MAP_0 <<
--						 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
--				break;
--			case 1:
--				data |= (RASTER_CONFIG_RB_MAP_0 <<
--					 (i * sh_per_se + j) * 2);
--				break;
--			case 2:
--				data |= (RASTER_CONFIG_RB_MAP_3 <<
--					 (i * sh_per_se + j) * 2);
--				break;
--			case 3:
--			default:
--				data |= (RASTER_CONFIG_RB_MAP_2 <<
--					 (i * sh_per_se + j) * 2);
--				break;
--			}
--			enabled_rbs >>= 2;
--		}
--		WREG32(mmPA_SC_RASTER_CONFIG, data);
--	}
--	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
--	mutex_unlock(&adev->grbm_idx_mutex);
-+	adev->gfx.config.backend_enable_mask = active_rbs;
-+	tmp = active_rbs;
-+	while (tmp >>= 1)
-+		num_rbs++;
-+	adev->gfx.config.num_rbs = num_rbs;
- }
- 
- /**
-@@ -2749,9 +2705,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
- 
- 	gfx_v8_0_tiling_mode_table_init(adev);
- 
--	gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
--				 adev->gfx.config.max_sh_per_se,
--				 adev->gfx.config.max_backends_per_se);
-+	gfx_v8_0_setup_rb(adev);
- 
- 	/* XXX SH_MEM regs */
- 	/* where to put LDS, scratch, GPUVM in FSA64 space */
-@@ -5188,32 +5142,24 @@ static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
- 	}
- }
- 
--static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
--		u32 se, u32 sh)
-+static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
- {
--	u32 mask = 0, tmp, tmp1;
--	int i;
-+	u32 data, mask;
- 
--	gfx_v8_0_select_se_sh(adev, se, sh);
--	tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
--	tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
--	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-+	data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
-+	data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
- 
--	tmp &= 0xffff0000;
-+	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
-+	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
- 
--	tmp |= tmp1;
--	tmp >>= 16;
-+	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-+				       adev->gfx.config.max_sh_per_se);
- 
--	for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
--		mask <<= 1;
--		mask |= 1;
--	}
--
--	return (~tmp) & mask;
-+	return (~data) & mask;
- }
- 
- int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
--						 struct amdgpu_cu_info *cu_info)
-+			 struct amdgpu_cu_info *cu_info)
- {
- 	int i, j, k, counter, active_cu_number = 0;
- 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
-@@ -5227,10 +5173,11 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
- 			mask = 1;
- 			ao_bitmap = 0;
- 			counter = 0;
--			bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
-+			gfx_v8_0_select_se_sh(adev, i, j);
-+			bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
- 			cu_info->bitmap[i][j] = bitmap;
- 
--			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
-+			for (k = 0; k < 16; k ++) {
- 				if (bitmap & mask) {
- 					if (counter < 2)
- 						ao_bitmap |= mask;
-@@ -5242,9 +5189,11 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
- 			ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
- 		}
- 	}
-+	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-+	mutex_unlock(&adev->grbm_idx_mutex);
- 
- 	cu_info->number = active_cu_number;
- 	cu_info->ao_cu_mask = ao_cu_mask;
--	mutex_unlock(&adev->grbm_idx_mutex);
-+
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0311-drm-amdgpu-gfx7-rework-gpu_init.patch b/common/recipes-kernel/linux/files/0311-drm-amdgpu-gfx7-rework-gpu_init.patch
deleted file mode 100644
index 4b6a0d3a..00000000
--- a/common/recipes-kernel/linux/files/0311-drm-amdgpu-gfx7-rework-gpu_init.patch
+++ /dev/null
@@ -1,427 +0,0 @@
-From b891232f7037be905e52049089e86b60a465a194 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 12 Feb 2016 03:00:49 -0500
-Subject: [PATCH 0311/1110] drm/amdgpu/gfx7: rework gpu_init()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Split the sw and hw parts into separate functions.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 358 +++++++++++++++++-----------------
- 1 file changed, 182 insertions(+), 176 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 55c38fb..501f152 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1713,181 +1713,19 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
-  */
- static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
- {
--	u32 gb_addr_config;
--	u32 mc_shared_chmap, mc_arb_ramcfg;
--	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
--	u32 sh_mem_cfg;
--	u32 tmp;
-+	u32 tmp, sh_mem_cfg;
- 	int i;
- 
--	switch (adev->asic_type) {
--	case CHIP_BONAIRE:
--		adev->gfx.config.max_shader_engines = 2;
--		adev->gfx.config.max_tile_pipes = 4;
--		adev->gfx.config.max_cu_per_sh = 7;
--		adev->gfx.config.max_sh_per_se = 1;
--		adev->gfx.config.max_backends_per_se = 2;
--		adev->gfx.config.max_texture_channel_caches = 4;
--		adev->gfx.config.max_gprs = 256;
--		adev->gfx.config.max_gs_threads = 32;
--		adev->gfx.config.max_hw_contexts = 8;
--
--		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
--		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
--		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
--		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
--		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
--		break;
--	case CHIP_HAWAII:
--		adev->gfx.config.max_shader_engines = 4;
--		adev->gfx.config.max_tile_pipes = 16;
--		adev->gfx.config.max_cu_per_sh = 11;
--		adev->gfx.config.max_sh_per_se = 1;
--		adev->gfx.config.max_backends_per_se = 4;
--		adev->gfx.config.max_texture_channel_caches = 16;
--		adev->gfx.config.max_gprs = 256;
--		adev->gfx.config.max_gs_threads = 32;
--		adev->gfx.config.max_hw_contexts = 8;
--
--		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
--		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
--		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
--		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
--		gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
--		break;
--	case CHIP_KAVERI:
--		adev->gfx.config.max_shader_engines = 1;
--		adev->gfx.config.max_tile_pipes = 4;
--		if ((adev->pdev->device == 0x1304) ||
--		    (adev->pdev->device == 0x1305) ||
--		    (adev->pdev->device == 0x130C) ||
--		    (adev->pdev->device == 0x130F) ||
--		    (adev->pdev->device == 0x1310) ||
--		    (adev->pdev->device == 0x1311) ||
--		    (adev->pdev->device == 0x131C)) {
--			adev->gfx.config.max_cu_per_sh = 8;
--			adev->gfx.config.max_backends_per_se = 2;
--		} else if ((adev->pdev->device == 0x1309) ||
--			   (adev->pdev->device == 0x130A) ||
--			   (adev->pdev->device == 0x130D) ||
--			   (adev->pdev->device == 0x1313) ||
--			   (adev->pdev->device == 0x131D)) {
--			adev->gfx.config.max_cu_per_sh = 6;
--			adev->gfx.config.max_backends_per_se = 2;
--		} else if ((adev->pdev->device == 0x1306) ||
--			   (adev->pdev->device == 0x1307) ||
--			   (adev->pdev->device == 0x130B) ||
--			   (adev->pdev->device == 0x130E) ||
--			   (adev->pdev->device == 0x1315) ||
--			   (adev->pdev->device == 0x131B)) {
--			adev->gfx.config.max_cu_per_sh = 4;
--			adev->gfx.config.max_backends_per_se = 1;
--		} else {
--			adev->gfx.config.max_cu_per_sh = 3;
--			adev->gfx.config.max_backends_per_se = 1;
--		}
--		adev->gfx.config.max_sh_per_se = 1;
--		adev->gfx.config.max_texture_channel_caches = 4;
--		adev->gfx.config.max_gprs = 256;
--		adev->gfx.config.max_gs_threads = 16;
--		adev->gfx.config.max_hw_contexts = 8;
--
--		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
--		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
--		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
--		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
--		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
--		break;
--	case CHIP_KABINI:
--	case CHIP_MULLINS:
--	default:
--		adev->gfx.config.max_shader_engines = 1;
--		adev->gfx.config.max_tile_pipes = 2;
--		adev->gfx.config.max_cu_per_sh = 2;
--		adev->gfx.config.max_sh_per_se = 1;
--		adev->gfx.config.max_backends_per_se = 1;
--		adev->gfx.config.max_texture_channel_caches = 2;
--		adev->gfx.config.max_gprs = 256;
--		adev->gfx.config.max_gs_threads = 16;
--		adev->gfx.config.max_hw_contexts = 8;
--
--		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
--		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
--		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
--		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
--		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
--		break;
--	}
--
- 	WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
- 
--	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
--	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
--	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
--
--	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
--	adev->gfx.config.mem_max_burst_length_bytes = 256;
--	if (adev->flags & AMD_IS_APU) {
--		/* Get memory bank mapping mode. */
--		tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
--		dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
--		dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
--
--		tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
--		dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
--		dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
--
--		/* Validate settings in case only one DIMM installed. */
--		if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
--			dimm00_addr_map = 0;
--		if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
--			dimm01_addr_map = 0;
--		if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
--			dimm10_addr_map = 0;
--		if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
--			dimm11_addr_map = 0;
--
--		/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
--		/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
--		if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
--			adev->gfx.config.mem_row_size_in_kb = 2;
--		else
--			adev->gfx.config.mem_row_size_in_kb = 1;
--	} else {
--		tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
--		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
--		if (adev->gfx.config.mem_row_size_in_kb > 4)
--			adev->gfx.config.mem_row_size_in_kb = 4;
--	}
--	/* XXX use MC settings? */
--	adev->gfx.config.shader_engine_tile_size = 32;
--	adev->gfx.config.num_gpus = 1;
--	adev->gfx.config.multi_gpu_tile_size = 64;
--
--	/* fix up row size */
--	gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
--	switch (adev->gfx.config.mem_row_size_in_kb) {
--	case 1:
--	default:
--		gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
--		break;
--	case 2:
--		gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
--		break;
--	case 4:
--		gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
--		break;
--	}
--	adev->gfx.config.gb_addr_config = gb_addr_config;
--
--	WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
--	WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
--	WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
--	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
--	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
--	WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
--	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
--	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
-+	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
-+	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, adev->gfx.config.gb_addr_config & 0x70);
-+	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, adev->gfx.config.gb_addr_config & 0x70);
-+	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 
- 	gfx_v7_0_tiling_mode_table_init(adev);
- 
-@@ -1895,8 +1733,8 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
- 
- 	/* set HW defaults for 3D engine */
- 	WREG32(mmCP_MEQ_THRESHOLDS,
--			(0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
--			(0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
-+	       (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
-+	       (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
- 	/*
-@@ -1907,7 +1745,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
- 
- 	/* XXX SH_MEM regs */
- 	/* where to put LDS, scratch, GPUVM in FSA64 space */
--	sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 
-+	sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
- 				   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
- 
- 	mutex_lock(&adev->srbm_mutex);
-@@ -4348,6 +4186,172 @@ static int gfx_v7_0_late_init(void *handle)
- 	return 0;
- }
- 
-+static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
-+{
-+	u32 gb_addr_config;
-+	u32 mc_shared_chmap, mc_arb_ramcfg;
-+	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
-+	u32 tmp;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_BONAIRE:
-+		adev->gfx.config.max_shader_engines = 2;
-+		adev->gfx.config.max_tile_pipes = 4;
-+		adev->gfx.config.max_cu_per_sh = 7;
-+		adev->gfx.config.max_sh_per_se = 1;
-+		adev->gfx.config.max_backends_per_se = 2;
-+		adev->gfx.config.max_texture_channel_caches = 4;
-+		adev->gfx.config.max_gprs = 256;
-+		adev->gfx.config.max_gs_threads = 32;
-+		adev->gfx.config.max_hw_contexts = 8;
-+
-+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
-+		break;
-+	case CHIP_HAWAII:
-+		adev->gfx.config.max_shader_engines = 4;
-+		adev->gfx.config.max_tile_pipes = 16;
-+		adev->gfx.config.max_cu_per_sh = 11;
-+		adev->gfx.config.max_sh_per_se = 1;
-+		adev->gfx.config.max_backends_per_se = 4;
-+		adev->gfx.config.max_texture_channel_caches = 16;
-+		adev->gfx.config.max_gprs = 256;
-+		adev->gfx.config.max_gs_threads = 32;
-+		adev->gfx.config.max_hw_contexts = 8;
-+
-+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+		gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
-+		break;
-+	case CHIP_KAVERI:
-+		adev->gfx.config.max_shader_engines = 1;
-+		adev->gfx.config.max_tile_pipes = 4;
-+		if ((adev->pdev->device == 0x1304) ||
-+		    (adev->pdev->device == 0x1305) ||
-+		    (adev->pdev->device == 0x130C) ||
-+		    (adev->pdev->device == 0x130F) ||
-+		    (adev->pdev->device == 0x1310) ||
-+		    (adev->pdev->device == 0x1311) ||
-+		    (adev->pdev->device == 0x131C)) {
-+			adev->gfx.config.max_cu_per_sh = 8;
-+			adev->gfx.config.max_backends_per_se = 2;
-+		} else if ((adev->pdev->device == 0x1309) ||
-+			   (adev->pdev->device == 0x130A) ||
-+			   (adev->pdev->device == 0x130D) ||
-+			   (adev->pdev->device == 0x1313) ||
-+			   (adev->pdev->device == 0x131D)) {
-+			adev->gfx.config.max_cu_per_sh = 6;
-+			adev->gfx.config.max_backends_per_se = 2;
-+		} else if ((adev->pdev->device == 0x1306) ||
-+			   (adev->pdev->device == 0x1307) ||
-+			   (adev->pdev->device == 0x130B) ||
-+			   (adev->pdev->device == 0x130E) ||
-+			   (adev->pdev->device == 0x1315) ||
-+			   (adev->pdev->device == 0x131B)) {
-+			adev->gfx.config.max_cu_per_sh = 4;
-+			adev->gfx.config.max_backends_per_se = 1;
-+		} else {
-+			adev->gfx.config.max_cu_per_sh = 3;
-+			adev->gfx.config.max_backends_per_se = 1;
-+		}
-+		adev->gfx.config.max_sh_per_se = 1;
-+		adev->gfx.config.max_texture_channel_caches = 4;
-+		adev->gfx.config.max_gprs = 256;
-+		adev->gfx.config.max_gs_threads = 16;
-+		adev->gfx.config.max_hw_contexts = 8;
-+
-+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
-+		break;
-+	case CHIP_KABINI:
-+	case CHIP_MULLINS:
-+	default:
-+		adev->gfx.config.max_shader_engines = 1;
-+		adev->gfx.config.max_tile_pipes = 2;
-+		adev->gfx.config.max_cu_per_sh = 2;
-+		adev->gfx.config.max_sh_per_se = 1;
-+		adev->gfx.config.max_backends_per_se = 1;
-+		adev->gfx.config.max_texture_channel_caches = 2;
-+		adev->gfx.config.max_gprs = 256;
-+		adev->gfx.config.max_gs_threads = 16;
-+		adev->gfx.config.max_hw_contexts = 8;
-+
-+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+		gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
-+		break;
-+	}
-+
-+	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
-+	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
-+	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
-+
-+	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
-+	adev->gfx.config.mem_max_burst_length_bytes = 256;
-+	if (adev->flags & AMD_IS_APU) {
-+		/* Get memory bank mapping mode. */
-+		tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
-+		dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-+		dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
-+
-+		tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
-+		dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-+		dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
-+
-+		/* Validate settings in case only one DIMM installed. */
-+		if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
-+			dimm00_addr_map = 0;
-+		if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
-+			dimm01_addr_map = 0;
-+		if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
-+			dimm10_addr_map = 0;
-+		if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
-+			dimm11_addr_map = 0;
-+
-+		/* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
-+		/* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
-+		if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
-+			adev->gfx.config.mem_row_size_in_kb = 2;
-+		else
-+			adev->gfx.config.mem_row_size_in_kb = 1;
-+	} else {
-+		tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
-+		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
-+		if (adev->gfx.config.mem_row_size_in_kb > 4)
-+			adev->gfx.config.mem_row_size_in_kb = 4;
-+	}
-+	/* XXX use MC settings? */
-+	adev->gfx.config.shader_engine_tile_size = 32;
-+	adev->gfx.config.num_gpus = 1;
-+	adev->gfx.config.multi_gpu_tile_size = 64;
-+
-+	/* fix up row size */
-+	gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
-+	switch (adev->gfx.config.mem_row_size_in_kb) {
-+	case 1:
-+	default:
-+		gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
-+		break;
-+	case 2:
-+		gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
-+		break;
-+	case 4:
-+		gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
-+		break;
-+	}
-+	adev->gfx.config.gb_addr_config = gb_addr_config;
-+}
-+
- static int gfx_v7_0_sw_init(void *handle)
- {
- 	struct amdgpu_ring *ring;
-@@ -4451,6 +4455,10 @@ static int gfx_v7_0_sw_init(void *handle)
- 	if (r)
- 		return r;
- 
-+	adev->gfx.ce_ram_size = 0x8000;
-+
-+	gfx_v7_0_gpu_early_init(adev);
-+
- 	return r;
- }
- 
-@@ -4491,8 +4499,6 @@ static int gfx_v7_0_hw_init(void *handle)
- 	if (r)
- 		return r;
- 
--	adev->gfx.ce_ram_size = 0x8000;
--
- 	return r;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0312-drm-amdgpu-cik-move-sdma-tiling-config-setup-into-sd.patch b/common/recipes-kernel/linux/files/0312-drm-amdgpu-cik-move-sdma-tiling-config-setup-into-sd.patch
deleted file mode 100644
index 764140a3..00000000
--- a/common/recipes-kernel/linux/files/0312-drm-amdgpu-cik-move-sdma-tiling-config-setup-into-sd.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From a4c6993aca9f5a015f2423776484637586178196 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 12 Feb 2016 03:05:24 -0500
-Subject: [PATCH 0312/1110] drm/amdgpu/cik: move sdma tiling config setup into
- sdma code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Split sdma and gfx programming.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 +++++
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ------
- 2 files changed, 5 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index fefb365..2bf993c 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -393,6 +393,9 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
- 		cik_srbm_select(adev, 0, 0, 0, 0);
- 		mutex_unlock(&adev->srbm_mutex);
- 
-+		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
-+		       adev->gfx.config.gb_addr_config & 0x70);
-+
- 		WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
- 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
- 
-@@ -1065,6 +1068,8 @@ static void cik_sdma_print_status(void *handle)
- 			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
- 		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
- 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
-+		dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
-+			 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
- 		mutex_lock(&adev->srbm_mutex);
- 		for (j = 0; j < 16; j++) {
- 			cik_srbm_select(adev, 0, 0, 0, j);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 501f152..7761168 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1721,8 +1721,6 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
- 	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
--	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, adev->gfx.config.gb_addr_config & 0x70);
--	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, adev->gfx.config.gb_addr_config & 0x70);
- 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-@@ -4615,10 +4613,6 @@ static void gfx_v7_0_print_status(void *handle)
- 		 RREG32(mmHDP_ADDR_CONFIG));
- 	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
- 		 RREG32(mmDMIF_ADDR_CALC));
--	dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
--		 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
--	dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
--		 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
- 	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- 		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
- 	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0313-drm-amdgpu-cik-move-uvd-tiling-config-setup-into-uvd.patch b/common/recipes-kernel/linux/files/0313-drm-amdgpu-cik-move-uvd-tiling-config-setup-into-uvd.patch
deleted file mode 100644
index d748447c..00000000
--- a/common/recipes-kernel/linux/files/0313-drm-amdgpu-cik-move-uvd-tiling-config-setup-into-uvd.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 8a5525bb523ae9fdc29d169bc88d0b33c1a87030 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 12 Feb 2016 03:12:43 -0500
-Subject: [PATCH 0313/1110] drm/amdgpu/cik: move uvd tiling config setup into
- uvd code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Split uvd and gfx programming.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 11 -----------
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 11 +++++++++++
- 2 files changed, 11 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 7761168..4370daf 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -31,8 +31,6 @@
- #include "amdgpu_ucode.h"
- #include "clearstate_ci.h"
- 
--#include "uvd/uvd_4_2_d.h"
--
- #include "dce/dce_8_0_d.h"
- #include "dce/dce_8_0_sh_mask.h"
- 
-@@ -1721,9 +1719,6 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
- 	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
--	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
--	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
--	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 
- 	gfx_v7_0_tiling_mode_table_init(adev);
- 
-@@ -4613,12 +4608,6 @@ static void gfx_v7_0_print_status(void *handle)
- 		 RREG32(mmHDP_ADDR_CONFIG));
- 	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
- 		 RREG32(mmDMIF_ADDR_CALC));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- 
- 	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
- 		 RREG32(mmCP_MEQ_THRESHOLDS));
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index d2fc1ca..c606ccb 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -576,6 +576,10 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
- 	addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
- 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
- 
-+	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+
- 	uvd_v4_2_init_cg(adev);
- }
- 
-@@ -777,6 +781,13 @@ static void uvd_v4_2_print_status(void *handle)
- 		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
- 	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
- 		 RREG32(mmUVD_CONTEXT_ID));
-+	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
-+	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
-+	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
-+
- }
- 
- static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch b/common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch
deleted file mode 100644
index ac169bc4..00000000
--- a/common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 7b6b27de3068199ec3d9784c061c80e7e01b1f9e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 12 Feb 2016 03:19:14 -0500
-Subject: [PATCH 0314/1110] drm/amdgpu/vi: move sdma tiling config setup into
- sdma code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Split sdma and gfx programming.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 8 --------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 +++++
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++++
- 3 files changed, 10 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 5e04140..13eb40f 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2695,10 +2695,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
- 	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
--	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
--	       adev->gfx.config.gb_addr_config & 0x70);
--	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
--	       adev->gfx.config.gb_addr_config & 0x70);
- 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-@@ -3959,10 +3955,6 @@ static void gfx_v8_0_print_status(void *handle)
- 		 RREG32(mmHDP_ADDR_CONFIG));
- 	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
- 		 RREG32(mmDMIF_ADDR_CALC));
--	dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
--		 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
--	dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
--		 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
- 	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- 		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
- 	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 1f9ba74..1f70d83 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -434,6 +434,9 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
- 		vi_srbm_select(adev, 0, 0, 0, 0);
- 		mutex_unlock(&adev->srbm_mutex);
- 
-+		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
-+		       adev->gfx.config.gb_addr_config & 0x70);
-+
- 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
- 
- 		/* Set ring buffer size in dwords */
-@@ -1078,6 +1081,8 @@ static void sdma_v2_4_print_status(void *handle)
- 			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
- 		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
- 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
-+		dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
-+			 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
- 		mutex_lock(&adev->srbm_mutex);
- 		for (j = 0; j < 16; j++) {
- 			vi_srbm_select(adev, 0, 0, 0, j);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index f0943bb..2389bdb 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -570,6 +570,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
- 		vi_srbm_select(adev, 0, 0, 0, 0);
- 		mutex_unlock(&adev->srbm_mutex);
- 
-+		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
-+		       adev->gfx.config.gb_addr_config & 0x70);
-+
- 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
- 
- 		/* Set ring buffer size in dwords */
-@@ -1241,6 +1244,8 @@ static void sdma_v3_0_print_status(void *handle)
- 			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
- 		dev_info(adev->dev, "  SDMA%d_GFX_DOORBELL=0x%08X\n",
- 			 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
-+		dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
-+			 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
- 		mutex_lock(&adev->srbm_mutex);
- 		for (j = 0; j < 16; j++) {
- 			vi_srbm_select(adev, 0, 0, 0, j);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch b/common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch
deleted file mode 100644
index 576e7bfb..00000000
--- a/common/recipes-kernel/linux/files/0315-drm-amdgpu-vi-move-uvd-tiling-config-setup-into-uvd-.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From c3072891a30b09fe18f262f11ebef70913c232cc Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 12 Feb 2016 03:22:34 -0500
-Subject: [PATCH 0315/1110] drm/amdgpu/vi: move uvd tiling config setup into
- uvd code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Split uvd and gfx programming.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 ------------
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 10 ++++++++++
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 10 ++++++++++
- 3 files changed, 20 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 13eb40f..1744f67 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -43,9 +43,6 @@
- #include "gca/gfx_8_0_sh_mask.h"
- #include "gca/gfx_8_0_enum.h"
- 
--#include "uvd/uvd_5_0_d.h"
--#include "uvd/uvd_5_0_sh_mask.h"
--
- #include "dce/dce_10_0_d.h"
- #include "dce/dce_10_0_sh_mask.h"
- 
-@@ -2695,9 +2692,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
- 	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
--	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
--	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
--	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 
- 	gfx_v8_0_tiling_mode_table_init(adev);
- 
-@@ -3955,12 +3949,6 @@ static void gfx_v8_0_print_status(void *handle)
- 		 RREG32(mmHDP_ADDR_CONFIG));
- 	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
- 		 RREG32(mmDMIF_ADDR_CALC));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- 
- 	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
- 		 RREG32(mmCP_MEQ_THRESHOLDS));
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index c5edb98..e3c852d 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -279,6 +279,10 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
- 	size = AMDGPU_UVD_HEAP_SIZE;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
-+
-+	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- }
- 
- /**
-@@ -724,6 +728,12 @@ static void uvd_v5_0_print_status(void *handle)
- 		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
- 	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
- 		 RREG32(mmUVD_CONTEXT_ID));
-+	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
-+	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
-+	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- }
- 
- static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 0d5098e..3375e61 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -277,6 +277,10 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
- 	size = AMDGPU_UVD_HEAP_SIZE;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
-+
-+	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- }
- 
- static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
-@@ -947,6 +951,12 @@ static void uvd_v6_0_print_status(void *handle)
- 		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
- 	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
- 		 RREG32(mmUVD_CONTEXT_ID));
-+	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
-+	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
-+	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
-+		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- }
- 
- static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0316-drm-amdgpu-Fix-race-condition-in-MMU-notifier-releas.patch b/common/recipes-kernel/linux/files/0316-drm-amdgpu-Fix-race-condition-in-MMU-notifier-releas.patch
deleted file mode 100644
index 78cdd951..00000000
--- a/common/recipes-kernel/linux/files/0316-drm-amdgpu-Fix-race-condition-in-MMU-notifier-releas.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 0c670ebe392faae5c1ddf407d8b9631126bd1094 Mon Sep 17 00:00:00 2001
-From: Felix Kuehling <Felix.Kuehling@amd.com>
-Date: Thu, 14 Jan 2016 00:35:08 -0500
-Subject: [PATCH 0316/1110] drm/amdgpu: Fix race condition in MMU notifier
- release
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The release notifier can get called a second time from
-mmu_notifier_unregister depending on a race between
-__mmu_notifier_release and amdgpu_mn_destroy. Use
-mmu_notifier_unregister_no_release to avoid this.
-
-Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-index 61f0e3c..1b2105c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-@@ -86,7 +86,7 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 	}
- 	mutex_unlock(&adev->mn_lock);
- 	up_write(&rmn->mm->mmap_sem);
--	mmu_notifier_unregister(&rmn->mn, rmn->mm);
-+	mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
- 	kfree(rmn);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0317-drm-amdgpu-remove-fence-reset-detection-leftovers.patch b/common/recipes-kernel/linux/files/0317-drm-amdgpu-remove-fence-reset-detection-leftovers.patch
deleted file mode 100644
index 45481d0a..00000000
--- a/common/recipes-kernel/linux/files/0317-drm-amdgpu-remove-fence-reset-detection-leftovers.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 58c86b0b002bba8c6001ed49140c345b7e61c4e1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 11 Feb 2016 14:42:33 +0100
-Subject: [PATCH 0317/1110] drm/amdgpu: remove fence reset detection leftovers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-wait_event() never returns before the fence was signaled.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 14 ++++----------
- 1 file changed, 4 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 7210502..97db196 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -260,19 +260,16 @@ static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
- }
- 
- /*
-- * amdgpu_ring_wait_seq_timeout - wait for seq of the specific ring to signal
-+ * amdgpu_ring_wait_seq - wait for seq of the specific ring to signal
-  * @ring: ring to wait on for the seq number
-  * @seq: seq number wait for
-  *
-  * return value:
-  * 0: seq signaled, and gpu not hang
-- * -EDEADL: GPU hang detected
-  * -EINVAL: some paramter is not valid
-  */
- static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
- {
--	bool signaled = false;
--
- 	BUG_ON(!ring);
- 	if (seq > ring->fence_drv.sync_seq)
- 		return -EINVAL;
-@@ -281,13 +278,10 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
- 		return 0;
- 
- 	amdgpu_fence_schedule_fallback(ring);
--	wait_event(ring->fence_drv.fence_queue, (
--		   (signaled = amdgpu_fence_seq_signaled(ring, seq))));
-+	wait_event(ring->fence_drv.fence_queue,
-+		   amdgpu_fence_seq_signaled(ring, seq));
- 
--	if (signaled)
--		return 0;
--	else
--		return -EDEADLK;
-+	return 0;
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0318-drm-amdgpu-stop-calling-amdgpu_gpu_reset-from-the-fl.patch b/common/recipes-kernel/linux/files/0318-drm-amdgpu-stop-calling-amdgpu_gpu_reset-from-the-fl.patch
deleted file mode 100644
index 64523d89..00000000
--- a/common/recipes-kernel/linux/files/0318-drm-amdgpu-stop-calling-amdgpu_gpu_reset-from-the-fl.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 899ff480d5133c354ac517860294572af9c61c63 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 11 Feb 2016 14:51:47 +0100
-Subject: [PATCH 0318/1110] drm/amdgpu: stop calling amdgpu_gpu_reset from the
- flip code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We don't return -EDEADLK any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 +---------
- 1 file changed, 1 insertion(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index 1846d65..da49396 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -38,20 +38,12 @@
- static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
- 				   struct fence **f)
- {
--	struct amdgpu_fence *fence;
- 	long r;
- 
- 	if (*f == NULL)
- 		return;
- 
--	fence = to_amdgpu_fence(*f);
--	if (fence) {
--		r = fence_wait(&fence->base, false);
--		if (r == -EDEADLK)
--			r = amdgpu_gpu_reset(adev);
--	} else
--		r = fence_wait(*f, false);
--
-+	r = fence_wait(*f, false);
- 	if (r)
- 		DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0319-drm-amdgpu-stop-blocking-for-page-filp-fences.patch b/common/recipes-kernel/linux/files/0319-drm-amdgpu-stop-blocking-for-page-filp-fences.patch
deleted file mode 100644
index 00bbecfd..00000000
--- a/common/recipes-kernel/linux/files/0319-drm-amdgpu-stop-blocking-for-page-filp-fences.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From c13a496070571e8225a0574ff1d385e41dc9dfc8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 11 Feb 2016 15:48:30 +0100
-Subject: [PATCH 0319/1110] drm/amdgpu: stop blocking for page filp fences
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just register an callback and reschedule the work item if necessary.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h         |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 43 ++++++++++++++++++-----------
- 2 files changed, 28 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index d56dc9c..9a9673c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -721,6 +721,7 @@ struct amdgpu_flip_work {
- 	struct fence			*excl;
- 	unsigned			shared_count;
- 	struct fence			**shared;
-+	struct fence_cb			cb;
- };
- 
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index da49396..35756ad 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -35,24 +35,32 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_edid.h>
- 
--static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
--				   struct fence **f)
-+static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb)
- {
--	long r;
-+	struct amdgpu_flip_work *work =
-+		container_of(cb, struct amdgpu_flip_work, cb);
-+	struct amdgpu_device *adev = work->adev;
-+	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
- 
--	if (*f == NULL)
--		return;
-+	fence_put(f);
-+	queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
-+}
- 
--	r = fence_wait(*f, false);
--	if (r)
--		DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r);
-+static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
-+				     struct fence **f)
-+{
-+	struct fence *fence= *f;
-+
-+	if (fence == NULL)
-+		return false;
- 
--	/* We continue with the page flip even if we failed to wait on
--	 * the fence, otherwise the DRM core and userspace will be
--	 * confused about which BO the CRTC is scanning out
--	 */
--	fence_put(*f);
- 	*f = NULL;
-+
-+	if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
-+		return true;
-+
-+	fence_put(*f);
-+	return false;
- }
- 
- static void amdgpu_flip_work_func(struct work_struct *__work)
-@@ -68,9 +76,12 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
- 	int vpos, hpos, stat, min_udelay = 0;
- 	struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
- 
--	amdgpu_flip_wait_fence(adev, &work->excl);
-+	if (amdgpu_flip_handle_fence(work, &work->excl))
-+		return;
-+
- 	for (i = 0; i < work->shared_count; ++i)
--		amdgpu_flip_wait_fence(adev, &work->shared[i]);
-+		if (amdgpu_flip_handle_fence(work, &work->shared[i]))
-+			return;
- 
- 	/* We borrow the event spin lock for protecting flip_status */
- 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
-@@ -246,7 +257,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
- 	/* update crtc fb */
- 	crtc->primary->fb = fb;
- 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
--	queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
-+	amdgpu_flip_work_func(&work->flip_work);
- 	return 0;
- 
- vblank_cleanup:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0320-drm-amdgpu-remove-page-flip-work-queue-v3.patch b/common/recipes-kernel/linux/files/0320-drm-amdgpu-remove-page-flip-work-queue-v3.patch
deleted file mode 100644
index c56786ca..00000000
--- a/common/recipes-kernel/linux/files/0320-drm-amdgpu-remove-page-flip-work-queue-v3.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From 33dc2e651e561844b00f5fa8fa09aa42b03e3c7b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 11 Feb 2016 17:31:37 +0100
-Subject: [PATCH 0320/1110] drm/amdgpu: remove page flip work queue v3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just use the system queue now that we don't block any more.
-
-v2: handle DAL as well.
-v3: agd: split DAL changes out
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Mykola Lysenko <mykola.lysenko@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1)
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 +---
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h    | 1 -
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c      | 4 +---
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c      | 4 +---
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c       | 4 +---
- 5 files changed, 4 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index 35756ad..df65b11 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -39,11 +39,9 @@ static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb)
- {
- 	struct amdgpu_flip_work *work =
- 		container_of(cb, struct amdgpu_flip_work, cb);
--	struct amdgpu_device *adev = work->adev;
--	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
- 
- 	fence_put(f);
--	queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
-+	schedule_work(&work->flip_work);
- }
- 
- static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 3b2d75d..81bd964 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -390,7 +390,6 @@ struct amdgpu_crtc {
- 	struct drm_display_mode native_mode;
- 	u32 pll_id;
- 	/* page flipping */
--	struct workqueue_struct *pflip_queue;
- 	struct amdgpu_flip_work *pflip_works;
- 	enum amdgpu_flip_status pflip_status;
- 	int deferred_flip_completion;
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 093599a..a8ac8a3 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -2670,7 +2670,6 @@ static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
- 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
- 
- 	drm_crtc_cleanup(crtc);
--	destroy_workqueue(amdgpu_crtc->pflip_queue);
- 	kfree(amdgpu_crtc);
- }
- 
-@@ -2890,7 +2889,6 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
- 
- 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
- 	amdgpu_crtc->crtc_id = index;
--	amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
- 	adev->mode_info.crtcs[index] = amdgpu_crtc;
- 
- 	amdgpu_crtc->max_cursor_width = 128;
-@@ -3366,7 +3364,7 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
- 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 
- 	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
--	queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
-+	schedule_work(&works->unpin_work);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 8e67249..a7699be 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2661,7 +2661,6 @@ static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
- 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
- 
- 	drm_crtc_cleanup(crtc);
--	destroy_workqueue(amdgpu_crtc->pflip_queue);
- 	kfree(amdgpu_crtc);
- }
- 
-@@ -2881,7 +2880,6 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
- 
- 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
- 	amdgpu_crtc->crtc_id = index;
--	amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
- 	adev->mode_info.crtcs[index] = amdgpu_crtc;
- 
- 	amdgpu_crtc->max_cursor_width = 128;
-@@ -3361,7 +3359,7 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
- 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 
- 	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
--	queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
-+	schedule_work(&works->unpin_work);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index d0e128c..628d7b2 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -2582,7 +2582,6 @@ static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
- 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
- 
- 	drm_crtc_cleanup(crtc);
--	destroy_workqueue(amdgpu_crtc->pflip_queue);
- 	kfree(amdgpu_crtc);
- }
- 
-@@ -2809,7 +2808,6 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
- 
- 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
- 	amdgpu_crtc->crtc_id = index;
--	amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
- 	adev->mode_info.crtcs[index] = amdgpu_crtc;
- 
- 	amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
-@@ -3375,7 +3373,7 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
- 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 
- 	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
--	queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
-+	schedule_work(&works->unpin_work);
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0321-drm-amdgpu-print-pid-as-integer.patch b/common/recipes-kernel/linux/files/0321-drm-amdgpu-print-pid-as-integer.patch
deleted file mode 100644
index 22240f24..00000000
--- a/common/recipes-kernel/linux/files/0321-drm-amdgpu-print-pid-as-integer.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 3a50d919a012551ab858370c03f43489f51eb152 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 15:28:34 +0100
-Subject: [PATCH 0321/1110] drm/amdgpu: print pid as integer
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not sure why somebody thought that this is a long.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 2f56bc6..ea6b52b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -721,9 +721,9 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- 			placement = " CPU";
- 			break;
- 		}
--		seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
-+		seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8d\n",
- 			   i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
--			   placement, (unsigned long)rbo->pid);
-+			   placement, rbo->pid);
- 		i++;
- 	}
- 	mutex_unlock(&adev->gem.mutex);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0322-drm-amdgpu-print-the-BO-size-only-once-in-amdgpu_gem.patch b/common/recipes-kernel/linux/files/0322-drm-amdgpu-print-the-BO-size-only-once-in-amdgpu_gem.patch
deleted file mode 100644
index 0f7eaccd..00000000
--- a/common/recipes-kernel/linux/files/0322-drm-amdgpu-print-the-BO-size-only-once-in-amdgpu_gem.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 6a6fa16779715078fde4e45088c6fb3fd9439a93 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 13:01:23 +0100
-Subject: [PATCH 0322/1110] drm/amdgpu: print the BO size only once in
- amdgpu_gem_info
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Splitting it into KB/MB is just confusing.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index ea6b52b..901a44c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -721,9 +721,8 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- 			placement = " CPU";
- 			break;
- 		}
--		seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8d\n",
--			   i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
--			   placement, rbo->pid);
-+		seq_printf(m, "bo[0x%08x] %12ld %s pid %8d\n",
-+			   i, amdgpu_bo_size(rbo), placement, rbo->pid);
- 		i++;
- 	}
- 	mutex_unlock(&adev->gem.mutex);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0323-drm-amdgpu-optionally-print-the-pin-count-in-gem_inf.patch b/common/recipes-kernel/linux/files/0323-drm-amdgpu-optionally-print-the-pin-count-in-gem_inf.patch
deleted file mode 100644
index f8edcb5a..00000000
--- a/common/recipes-kernel/linux/files/0323-drm-amdgpu-optionally-print-the-pin-count-in-gem_inf.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 2fc1bbf233adc66b9d052487bb26e6627a625f1d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 12:41:37 +0100
-Subject: [PATCH 0323/1110] drm/amdgpu: optionally print the pin count in
- gem_info as well
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Usefull when debugging page flipping.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 901a44c..cb7806a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -705,6 +705,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- 
- 	mutex_lock(&adev->gem.mutex);
- 	list_for_each_entry(rbo, &adev->gem.objects, list) {
-+		unsigned pin_count;
- 		unsigned domain;
- 		const char *placement;
- 
-@@ -721,8 +722,13 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- 			placement = " CPU";
- 			break;
- 		}
--		seq_printf(m, "bo[0x%08x] %12ld %s pid %8d\n",
-+		seq_printf(m, "bo[0x%08x] %12ld %s pid %8d",
- 			   i, amdgpu_bo_size(rbo), placement, rbo->pid);
-+
-+		pin_count = ACCESS_ONCE(rbo->pin_count);
-+		if (pin_count)
-+			seq_printf(m, " pin count %d", pin_count);
-+		seq_printf(m, "\n");
- 		i++;
- 	}
- 	mutex_unlock(&adev->gem.mutex);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0324-drm-amdgpu-print-the-GPU-offset-as-well-in-gem_info.patch b/common/recipes-kernel/linux/files/0324-drm-amdgpu-print-the-GPU-offset-as-well-in-gem_info.patch
deleted file mode 100644
index 73edc466..00000000
--- a/common/recipes-kernel/linux/files/0324-drm-amdgpu-print-the-GPU-offset-as-well-in-gem_info.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From a00e59abda629c81c2581e09a5b55afef882248d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 17:36:22 +0100
-Subject: [PATCH 0324/1110] drm/amdgpu: print the GPU offset as well in
- gem_info
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-To easily find which memory is used.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index cb7806a..86ce4f3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -722,8 +722,9 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- 			placement = " CPU";
- 			break;
- 		}
--		seq_printf(m, "bo[0x%08x] %12ld %s pid %8d",
--			   i, amdgpu_bo_size(rbo), placement, rbo->pid);
-+		seq_printf(m, "bo[0x%08x] %12ld %s @ 0x%010Lx pid %8d",
-+			   i, amdgpu_bo_size(rbo), placement,
-+			   amdgpu_bo_gpu_offset(rbo), rbo->pid);
- 
- 		pin_count = ACCESS_ONCE(rbo->pin_count);
- 		if (pin_count)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0325-drm-amdgpu-rework-GEM-info-printing.patch b/common/recipes-kernel/linux/files/0325-drm-amdgpu-rework-GEM-info-printing.patch
deleted file mode 100644
index 059de0b6..00000000
--- a/common/recipes-kernel/linux/files/0325-drm-amdgpu-rework-GEM-info-printing.patch
+++ /dev/null
@@ -1,150 +0,0 @@
-From 8c97cc2e58f806aec91a47949daf5a57c041e188 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 15:23:00 +0100
-Subject: [PATCH 0325/1110] drm/amdgpu: rework GEM info printing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Print BOs grouped per client.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 94 +++++++++++++++++++++------------
- 2 files changed, 61 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 9a9673c..ba66640 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -493,7 +493,6 @@ struct amdgpu_bo {
- 	struct amdgpu_bo		*parent;
- 
- 	struct ttm_bo_kmap_obj		dma_buf_vmap;
--	pid_t				pid;
- 	struct amdgpu_mn		*mn;
- 	struct list_head		mn_list;
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 86ce4f3..c44905a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -83,7 +83,6 @@ retry:
- 		return r;
- 	}
- 	*obj = &robj->gem_base;
--	robj->pid = task_pid_nr(current);
- 
- 	mutex_lock(&adev->gem.mutex);
- 	list_add_tail(&robj->list, &adev->gem.objects);
-@@ -695,44 +694,73 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
- }
- 
- #if defined(CONFIG_DEBUG_FS)
-+static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
-+{
-+	struct drm_gem_object *gobj = ptr;
-+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
-+	struct seq_file *m = data;
-+
-+	unsigned domain;
-+	const char *placement;
-+	unsigned pin_count;
-+
-+	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
-+	switch (domain) {
-+	case AMDGPU_GEM_DOMAIN_VRAM:
-+		placement = "VRAM";
-+		break;
-+	case AMDGPU_GEM_DOMAIN_GTT:
-+		placement = " GTT";
-+		break;
-+	case AMDGPU_GEM_DOMAIN_CPU:
-+	default:
-+		placement = " CPU";
-+		break;
-+	}
-+	seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
-+		   id, amdgpu_bo_size(bo), placement,
-+		   amdgpu_bo_gpu_offset(bo));
-+
-+	pin_count = ACCESS_ONCE(bo->pin_count);
-+	if (pin_count)
-+		seq_printf(m, " pin count %d", pin_count);
-+	seq_printf(m, "\n");
-+
-+	return 0;
-+}
-+
- static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- {
- 	struct drm_info_node *node = (struct drm_info_node *)m->private;
- 	struct drm_device *dev = node->minor->dev;
--	struct amdgpu_device *adev = dev->dev_private;
--	struct amdgpu_bo *rbo;
--	unsigned i = 0;
-+	struct drm_file *file;
-+	int r;
- 
--	mutex_lock(&adev->gem.mutex);
--	list_for_each_entry(rbo, &adev->gem.objects, list) {
--		unsigned pin_count;
--		unsigned domain;
--		const char *placement;
--
--		domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
--		switch (domain) {
--		case AMDGPU_GEM_DOMAIN_VRAM:
--			placement = "VRAM";
--			break;
--		case AMDGPU_GEM_DOMAIN_GTT:
--			placement = " GTT";
--			break;
--		case AMDGPU_GEM_DOMAIN_CPU:
--		default:
--			placement = " CPU";
--			break;
--		}
--		seq_printf(m, "bo[0x%08x] %12ld %s @ 0x%010Lx pid %8d",
--			   i, amdgpu_bo_size(rbo), placement,
--			   amdgpu_bo_gpu_offset(rbo), rbo->pid);
--
--		pin_count = ACCESS_ONCE(rbo->pin_count);
--		if (pin_count)
--			seq_printf(m, " pin count %d", pin_count);
--		seq_printf(m, "\n");
--		i++;
-+	r = mutex_lock_interruptible(&dev->struct_mutex);
-+	if (r)
-+		return r;
-+
-+	list_for_each_entry(file, &dev->filelist, lhead) {
-+		struct task_struct *task;
-+
-+		/*
-+		 * Although we have a valid reference on file->pid, that does
-+		 * not guarantee that the task_struct who called get_pid() is
-+		 * still alive (e.g. get_pid(current) => fork() => exit()).
-+		 * Therefore, we need to protect this ->comm access using RCU.
-+		 */
-+		rcu_read_lock();
-+		task = pid_task(file->pid, PIDTYPE_PID);
-+		seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
-+			   task ? task->comm : "<unknown>");
-+		rcu_read_unlock();
-+
-+		spin_lock(&file->table_lock);
-+		idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
-+		spin_unlock(&file->table_lock);
- 	}
--	mutex_unlock(&adev->gem.mutex);
-+
-+	mutex_unlock(&dev->struct_mutex);
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0326-drm-amdgpu-cleanup-gem-init-finit.patch b/common/recipes-kernel/linux/files/0326-drm-amdgpu-cleanup-gem-init-finit.patch
deleted file mode 100644
index 6e47c43b..00000000
--- a/common/recipes-kernel/linux/files/0326-drm-amdgpu-cleanup-gem-init-finit.patch
+++ /dev/null
@@ -1,230 +0,0 @@
-From 9a0d113114485b5286a3af62b5f2b3a638a42c56 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 16:59:57 +0100
-Subject: [PATCH 0326/1110] drm/amdgpu: cleanup gem init/finit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Remove the double housekeeping and use something sane to
-forcefuly delete BOs on unload.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  9 +--------
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 31 +++++++++++++++++++-----------
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 23 ----------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  |  4 ----
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |  6 +-----
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |  6 +-----
- 8 files changed, 23 insertions(+), 58 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index ba66640..af4f128 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -567,13 +567,7 @@ struct amdgpu_sa_bo {
- /*
-  * GEM objects.
-  */
--struct amdgpu_gem {
--	struct mutex		mutex;
--	struct list_head	objects;
--};
--
--int amdgpu_gem_init(struct amdgpu_device *adev);
--void amdgpu_gem_fini(struct amdgpu_device *adev);
-+void amdgpu_gem_force_release(struct amdgpu_device *adev);
- int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
- 				int alignment, u32 initial_domain,
- 				u64 flags, bool kernel,
-@@ -1976,7 +1970,6 @@ struct amdgpu_device {
- 
- 	/* memory management */
- 	struct amdgpu_mman		mman;
--	struct amdgpu_gem		gem;
- 	struct amdgpu_vram_scratch	vram_scratch;
- 	struct amdgpu_wb		wb;
- 	atomic64_t			vram_usage;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 736d560..9663d17 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1426,7 +1426,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	 * can recall function without having locking issues */
- 	mutex_init(&adev->vm_manager.lock);
- 	atomic_set(&adev->irq.ih.lock, 0);
--	mutex_init(&adev->gem.mutex);
- 	mutex_init(&adev->pm.mutex);
- 	mutex_init(&adev->gfx.gpu_clock_mutex);
- 	mutex_init(&adev->srbm_mutex);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index c44905a..6270a20 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -84,22 +84,31 @@ retry:
- 	}
- 	*obj = &robj->gem_base;
- 
--	mutex_lock(&adev->gem.mutex);
--	list_add_tail(&robj->list, &adev->gem.objects);
--	mutex_unlock(&adev->gem.mutex);
--
- 	return 0;
- }
- 
--int amdgpu_gem_init(struct amdgpu_device *adev)
-+void amdgpu_gem_force_release(struct amdgpu_device *adev)
- {
--	INIT_LIST_HEAD(&adev->gem.objects);
--	return 0;
--}
-+	struct drm_device *ddev = adev->ddev;
-+	struct drm_file *file;
- 
--void amdgpu_gem_fini(struct amdgpu_device *adev)
--{
--	amdgpu_bo_force_delete(adev);
-+	mutex_lock(&ddev->struct_mutex);
-+
-+	list_for_each_entry(file, &ddev->filelist, lhead) {
-+		struct drm_gem_object *gobj;
-+		int handle;
-+
-+		WARN_ONCE(1, "Still active user space clients!\n");
-+		spin_lock(&file->table_lock);
-+		idr_for_each_entry(&file->object_idr, gobj, handle) {
-+			WARN_ONCE(1, "And also active allocations!\n");
-+			drm_gem_object_unreference(gobj);
-+		}
-+		idr_destroy(&file->object_idr);
-+		spin_unlock(&file->table_lock);
-+	}
-+
-+	mutex_unlock(&ddev->struct_mutex);
- }
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index c884873..c980cba 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -97,9 +97,6 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
- 
- 	amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
- 
--	mutex_lock(&bo->adev->gem.mutex);
--	list_del_init(&bo->list);
--	mutex_unlock(&bo->adev->gem.mutex);
- 	drm_gem_object_release(&bo->gem_base);
- 	amdgpu_bo_unref(&bo->parent);
- 	kfree(bo->metadata);
-@@ -473,26 +470,6 @@ int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
- 	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
- }
- 
--void amdgpu_bo_force_delete(struct amdgpu_device *adev)
--{
--	struct amdgpu_bo *bo, *n;
--
--	if (list_empty(&adev->gem.objects)) {
--		return;
--	}
--	dev_err(adev->dev, "Userspace still has active objects !\n");
--	list_for_each_entry_safe(bo, n, &adev->gem.objects, list) {
--		dev_err(adev->dev, "%p %p %lu %lu force free\n",
--			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
--			*((unsigned long *)&bo->gem_base.refcount));
--		mutex_lock(&bo->adev->gem.mutex);
--		list_del_init(&bo->list);
--		mutex_unlock(&bo->adev->gem.mutex);
--		/* this should unref the ttm bo */
--		drm_gem_object_unreference_unlocked(&bo->gem_base);
--	}
--}
--
- int amdgpu_bo_init(struct amdgpu_device *adev)
- {
- 	/* Add an MTRR for the VRAM */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-index 5107fb2..acc0801 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-@@ -149,7 +149,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
- 			     u64 *gpu_addr);
- int amdgpu_bo_unpin(struct amdgpu_bo *bo);
- int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
--void amdgpu_bo_force_delete(struct amdgpu_device *adev);
- int amdgpu_bo_init(struct amdgpu_device *adev);
- void amdgpu_bo_fini(struct amdgpu_device *adev);
- int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-index 39db99a..32b0247 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-@@ -73,10 +73,6 @@ struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
- 	if (ret)
- 		return ERR_PTR(ret);
- 
--	mutex_lock(&adev->gem.mutex);
--	list_add_tail(&bo->list, &adev->gem.objects);
--	mutex_unlock(&adev->gem.mutex);
--
- 	return &bo->gem_base;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index 7864318..3065184 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -919,10 +919,6 @@ static int gmc_v7_0_sw_init(void *handle)
- 	int dma_bits;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	r = amdgpu_gem_init(adev);
--	if (r)
--		return r;
--
- 	if (adev->flags & AMD_IS_APU) {
- 		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
- 	} else {
-@@ -1010,7 +1006,7 @@ static int gmc_v7_0_sw_fini(void *handle)
- 		adev->vm_manager.enabled = false;
- 	}
- 	gmc_v7_0_gart_fini(adev);
--	amdgpu_gem_fini(adev);
-+        amdgpu_gem_force_release(adev);
- 	amdgpu_bo_fini(adev);
- 
- 	return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index b410c32..f589e1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -881,10 +881,6 @@ static int gmc_v8_0_sw_init(void *handle)
- 	int dma_bits;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	r = amdgpu_gem_init(adev);
--	if (r)
--		return r;
--
- 	if (adev->flags & AMD_IS_APU) {
- 		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
- 	} else {
-@@ -978,7 +974,7 @@ static int gmc_v8_0_sw_fini(void *handle)
- 		adev->vm_manager.enabled = false;
- 	}
- 	gmc_v8_0_gart_fini(adev);
--	amdgpu_gem_fini(adev);
-+        amdgpu_gem_force_release(adev);
- 	amdgpu_bo_fini(adev);
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0327-drm-amdgpu-Fix-race-condition-in-amdgpu_mn_unregiste.patch b/common/recipes-kernel/linux/files/0327-drm-amdgpu-Fix-race-condition-in-amdgpu_mn_unregiste.patch
deleted file mode 100644
index 292458fa..00000000
--- a/common/recipes-kernel/linux/files/0327-drm-amdgpu-Fix-race-condition-in-amdgpu_mn_unregiste.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From 517f50c6dfe7fbc0671db2d7298ddaf97229c073 Mon Sep 17 00:00:00 2001
-From: Felix Kuehling <Felix.Kuehling@amd.com>
-Date: Tue, 16 Feb 2016 15:29:23 -0500
-Subject: [PATCH 0327/1110] drm/amdgpu: Fix race condition in
- amdgpu_mn_unregister
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Exchange locking order of adev->mn_lock and mm_sem, so that
-rmn->mm->mmap_sem can be taken safely, protected by adev->mn_lock,
-when amdgpu_mn_destroy runs concurrently.
-
-Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 23 +++++++++++++----------
- 1 file changed, 13 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-index 1b2105c..d12dff9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-@@ -71,12 +71,11 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 	struct amdgpu_mn_node *node, *next_node;
- 	struct amdgpu_bo *bo, *next_bo;
- 
--	down_write(&rmn->mm->mmap_sem);
- 	mutex_lock(&adev->mn_lock);
-+	down_write(&rmn->mm->mmap_sem);
- 	hash_del(&rmn->node);
- 	rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects,
- 					     it.rb) {
--
- 		interval_tree_remove(&node->it, &rmn->objects);
- 		list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
- 			bo->mn = NULL;
-@@ -84,8 +83,8 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 		}
- 		kfree(node);
- 	}
--	mutex_unlock(&adev->mn_lock);
- 	up_write(&rmn->mm->mmap_sem);
-+	mutex_unlock(&adev->mn_lock);
- 	mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
- 	kfree(rmn);
- }
-@@ -182,8 +181,8 @@ static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
- 	struct amdgpu_mn *rmn;
- 	int r;
- 
--	down_write(&mm->mmap_sem);
- 	mutex_lock(&adev->mn_lock);
-+	down_write(&mm->mmap_sem);
- 
- 	hash_for_each_possible(adev->mn_hash, rmn, node, (unsigned long)mm)
- 		if (rmn->mm == mm)
-@@ -207,14 +206,14 @@ static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
- 	hash_add(adev->mn_hash, &rmn->node, (unsigned long)mm);
- 
- release_locks:
--	mutex_unlock(&adev->mn_lock);
- 	up_write(&mm->mmap_sem);
-+	mutex_unlock(&adev->mn_lock);
- 
- 	return rmn;
- 
- free_rmn:
--	mutex_unlock(&adev->mn_lock);
- 	up_write(&mm->mmap_sem);
-+	mutex_unlock(&adev->mn_lock);
- 	kfree(rmn);
- 
- 	return ERR_PTR(r);
-@@ -288,14 +287,18 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- void amdgpu_mn_unregister(struct amdgpu_bo *bo)
- {
- 	struct amdgpu_device *adev = bo->adev;
--	struct amdgpu_mn *rmn = bo->mn;
-+	struct amdgpu_mn *rmn;
- 	struct list_head *head;
- 
--	if (rmn == NULL)
-+	mutex_lock(&adev->mn_lock);
-+
-+	rmn = bo->mn;
-+	if (rmn == NULL) {
-+		mutex_unlock(&adev->mn_lock);
- 		return;
-+	}
- 
- 	down_write(&rmn->mm->mmap_sem);
--	mutex_lock(&adev->mn_lock);
- 
- 	/* save the next list entry for later */
- 	head = bo->mn_list.next;
-@@ -310,6 +313,6 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
- 		kfree(node);
- 	}
- 
--	mutex_unlock(&adev->mn_lock);
- 	up_write(&rmn->mm->mmap_sem);
-+	mutex_unlock(&adev->mn_lock);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0328-drm-amdgpu-Don-t-call-interval_tree_remove-in-amdgpu.patch b/common/recipes-kernel/linux/files/0328-drm-amdgpu-Don-t-call-interval_tree_remove-in-amdgpu.patch
deleted file mode 100644
index 78350ec9..00000000
--- a/common/recipes-kernel/linux/files/0328-drm-amdgpu-Don-t-call-interval_tree_remove-in-amdgpu.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From b3f48dbf2654bf125ea1cfd53312a5533e8c0c95 Mon Sep 17 00:00:00 2001
-From: Felix Kuehling <Felix.Kuehling@amd.com>
-Date: Tue, 16 Feb 2016 15:31:30 -0500
-Subject: [PATCH 0328/1110] drm/amdgpu: Don't call interval_tree_remove in
- amdgpu_mn_destroy
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-rbtree_postorder_for_each_entry_safe can skip over some entries if
-the tree is rebalanced in interval_tree_remove. interval_tree_remove
-is also redundant when the tree is just about to be freed.
-
-Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-index d12dff9..d7ec9bd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-@@ -76,7 +76,6 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 	hash_del(&rmn->node);
- 	rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects,
- 					     it.rb) {
--		interval_tree_remove(&node->it, &rmn->objects);
- 		list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
- 			bo->mn = NULL;
- 			list_del_init(&bo->mn_list);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0329-drm-amdgpu-gfx-fix-off-by-one-in-rb-rework-v2.patch b/common/recipes-kernel/linux/files/0329-drm-amdgpu-gfx-fix-off-by-one-in-rb-rework-v2.patch
deleted file mode 100644
index 3bec60c9..00000000
--- a/common/recipes-kernel/linux/files/0329-drm-amdgpu-gfx-fix-off-by-one-in-rb-rework-v2.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From f8f5af1bcc6786bdf282e1116c6b7af76cf443f7 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 24 Feb 2016 10:06:06 -0500
-Subject: [PATCH 0329/1110] drm/amdgpu/gfx: fix off by one in rb rework (v2)
-
-When I reworked this code, I messed up num rb count.
-
-v2: use hweight32
-
-Reviewed-by: Ken Wang <Qingquing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 7 ++-----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 ++-----
- 2 files changed, 4 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 4370daf..c452048 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1635,7 +1635,7 @@ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
- static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
- {
- 	int i, j;
--	u32 data, tmp, num_rbs = 0;
-+	u32 data;
- 	u32 active_rbs = 0;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
-@@ -1655,10 +1655,7 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
- 	mutex_unlock(&adev->grbm_idx_mutex);
- 
- 	adev->gfx.config.backend_enable_mask = active_rbs;
--	tmp = active_rbs;
--	while (tmp >>= 1)
--		num_rbs++;
--	adev->gfx.config.num_rbs = num_rbs;
-+	adev->gfx.config.num_rbs = hweight32(active_rbs);
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 1744f67..48bc114 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2613,7 +2613,7 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
- static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
- {
- 	int i, j;
--	u32 data, tmp, num_rbs = 0;
-+	u32 data;
- 	u32 active_rbs = 0;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
-@@ -2629,10 +2629,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
- 	mutex_unlock(&adev->grbm_idx_mutex);
- 
- 	adev->gfx.config.backend_enable_mask = active_rbs;
--	tmp = active_rbs;
--	while (tmp >>= 1)
--		num_rbs++;
--	adev->gfx.config.num_rbs = num_rbs;
-+	adev->gfx.config.num_rbs = hweight32(active_rbs);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0330-drm-amd-Do-not-make-DRM_AMD_ACP-default-to-y.patch b/common/recipes-kernel/linux/files/0330-drm-amd-Do-not-make-DRM_AMD_ACP-default-to-y.patch
deleted file mode 100644
index 124c151f..00000000
--- a/common/recipes-kernel/linux/files/0330-drm-amd-Do-not-make-DRM_AMD_ACP-default-to-y.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 69a7a0ff90fdee4583328df0130dac3ae109bd67 Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert+renesas@glider.be>
-Date: Wed, 24 Feb 2016 09:13:45 +0100
-Subject: [PATCH 0330/1110] drm/amd: Do not make DRM_AMD_ACP default to y
-
-By default, not only this driver is enabled on all platforms, but also
-generic PM Domains and Multi-Function Devices.
-
-Drop the "default y" to fix this.
-
-Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/acp/Kconfig | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
-index 2b07813..0f734ee 100644
---- a/drivers/gpu/drm/amd/acp/Kconfig
-+++ b/drivers/gpu/drm/amd/acp/Kconfig
-@@ -2,7 +2,6 @@ menu "ACP Configuration"
- 
- config DRM_AMD_ACP
-        bool "Enable ACP IP support"
--       default y
-        select MFD_CORE
-        select PM_GENERIC_DOMAINS if PM
-        help
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0331-drm-amd-powerplay-fix-code-style-warning.patch b/common/recipes-kernel/linux/files/0331-drm-amd-powerplay-fix-code-style-warning.patch
deleted file mode 100644
index ec657522..00000000
--- a/common/recipes-kernel/linux/files/0331-drm-amd-powerplay-fix-code-style-warning.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From fd984da71a080aa8b06cef07bd62740686206c4f Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 25 Feb 2016 17:48:24 +0800
-Subject: [PATCH 0331/1110] drm/amd/powerplay: fix code style warning.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 351ebf2..9d22900 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -609,7 +609,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
- 
- 	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- 		hwmgr->hwmgr_func->set_pp_table == NULL)
--			return -EINVAL;
-+		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
- }
-@@ -626,7 +626,7 @@ static int pp_dpm_force_clock_level(void *handle,
- 
- 	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- 			hwmgr->hwmgr_func->force_clock_level == NULL)
--				return -EINVAL;
-+		return -EINVAL;
- 
- 	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0332-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_set.patch b/common/recipes-kernel/linux/files/0332-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_set.patch
deleted file mode 100644
index e1805e4f..00000000
--- a/common/recipes-kernel/linux/files/0332-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_set.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From a6279124b1e32280541b288b0b6bf34613378fea Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 22 Feb 2016 15:11:56 +0100
-Subject: [PATCH 0332/1110] drm/amdgpu: fix error handling in
- amdgpu_bo_list_set
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Don't leak BOs in case of some error.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index 53b1ebf..3406527 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -118,6 +118,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
-                 usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm);
-                 if (usermm) {
-                         if (usermm != current->mm) {
-+                                amdgpu_bo_unref(&entry->robj);
-                                 r = -EPERM;
-                                 goto error_free;
-                         }
-@@ -151,6 +152,8 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	return 0;
- 
- error_free:
-+        while (i--)
-+                amdgpu_bo_unref(&array[i].robj);
- 	drm_free_large(array);
-         return r;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0333-drm-amd-cleanup-get_mfd_cell_dev.patch b/common/recipes-kernel/linux/files/0333-drm-amd-cleanup-get_mfd_cell_dev.patch
deleted file mode 100644
index 3763bae2..00000000
--- a/common/recipes-kernel/linux/files/0333-drm-amd-cleanup-get_mfd_cell_dev.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 3727f6badafd345527ab81a871c3e7cd35febca1 Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Thu, 25 Feb 2016 10:47:10 +0300
-Subject: [PATCH 0333/1110] drm/amd: cleanup get_mfd_cell_dev()
-
-It's simpler to just use snprintf() to print this to one buffer instead
-of using strcpy() and strcat().  Also using snprintf() is slightly safer
-than using sprintf().
-
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-index 9f8cfaa..d6b0bff 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -240,12 +240,10 @@ static int acp_poweron(struct generic_pm_domain *genpd)
- static struct device *get_mfd_cell_dev(const char *device_name, int r)
- {
- 	char auto_dev_name[25];
--	char buf[8];
- 	struct device *dev;
- 
--	sprintf(buf, ".%d.auto", r);
--	strcpy(auto_dev_name, device_name);
--	strcat(auto_dev_name, buf);
-+	snprintf(auto_dev_name, sizeof(auto_dev_name),
-+		 "%s.%d.auto", device_name, r);
- 	dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
- 	dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0334-drm-amdgpu-update-radeon-acpi-header.patch b/common/recipes-kernel/linux/files/0334-drm-amdgpu-update-radeon-acpi-header.patch
deleted file mode 100644
index 792247df..00000000
--- a/common/recipes-kernel/linux/files/0334-drm-amdgpu-update-radeon-acpi-header.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 74957b0cee226a0abe3f4a9efe9a40d38b9d14b8 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 25 Feb 2016 01:47:53 -0500
-Subject: [PATCH 0334/1110] drm/amdgpu: update radeon acpi header
-
-Add some new defs for ATPX.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/amd_acpi.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h
-index 496360e..50e8933 100644
---- a/drivers/gpu/drm/amd/include/amd_acpi.h
-+++ b/drivers/gpu/drm/amd/include/amd_acpi.h
-@@ -340,6 +340,8 @@ struct atcs_pref_req_output {
- #       define ATPX_FIXED_NOT_SUPPORTED                            (1 << 9)
- #       define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED               (1 << 10)
- #       define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS                    (1 << 11)
-+#       define ATPX_DGPU_CAN_DRIVE_DISPLAYS                        (1 << 12)
-+#       define ATPX_MS_HYBRID_GFX_SUPPORTED                        (1 << 14)
- #define ATPX_FUNCTION_POWER_CONTROL                                0x2
- /* ARG0: ATPX_FUNCTION_POWER_CONTROL
-  * ARG1:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0335-drm-amdgpu-fix-VM-faults-caused-by-vm_grab_id-v4.patch b/common/recipes-kernel/linux/files/0335-drm-amdgpu-fix-VM-faults-caused-by-vm_grab_id-v4.patch
deleted file mode 100644
index 83902103..00000000
--- a/common/recipes-kernel/linux/files/0335-drm-amdgpu-fix-VM-faults-caused-by-vm_grab_id-v4.patch
+++ /dev/null
@@ -1,413 +0,0 @@
-From eaa21d10fdc0f6004c251edb39a17ac9dece6707 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 26 Feb 2016 16:18:26 +0100
-Subject: [PATCH 0335/1110] drm/amdgpu: fix VM faults caused by vm_grab_id() v4
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The owner must be per ring as long as we don't
-support sharing VMIDs per process. Also move the
-assigned VMID and page directory address into the
-IB structure.
-
-v3: assign the VMID to all IBs, not just the first one.
-v4: use correct pointer for owner
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  16 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  |   7 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  15 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 115 +++++++++++++++++---------------
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |   2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |   6 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |   6 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  |   2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |   2 +-
- 9 files changed, 91 insertions(+), 80 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index af4f128..ca1223f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -729,8 +729,9 @@ struct amdgpu_ib {
- 	uint32_t			*ptr;
- 	struct amdgpu_fence		*fence;
- 	struct amdgpu_user_fence        *user;
--	bool				grabbed_vmid;
- 	struct amdgpu_vm		*vm;
-+        unsigned                        vm_id;
-+        uint64_t                        vm_pd_addr;
- 	struct amdgpu_ctx		*ctx;
- 	uint32_t			gds_base, gds_size;
- 	uint32_t			gws_base, gws_size;
-@@ -836,10 +837,10 @@ struct amdgpu_vm_pt {
- };
- 
- struct amdgpu_vm_id {
--	unsigned		id;
--	uint64_t		pd_gpu_addr;
-+        struct amdgpu_vm_manager_id     *mgr_id;
-+        uint64_t                        pd_gpu_addr;
- 	/* last flushed PD/PT update */
--	struct fence	        *flushed_updates;
-+        struct fence                    *flushed_updates;
- };
- 
- struct amdgpu_vm {
-@@ -920,10 +921,11 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
- void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-                                   struct amdgpu_vm *vm);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
--                      struct amdgpu_sync *sync, struct fence *fence);
-+                      struct amdgpu_sync *sync, struct fence *fence,
-+                      unsigned *vm_id, uint64_t *vm_pd_addr);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
--		     struct amdgpu_vm *vm,
--		     struct fence *updates);
-+                     unsigned vmid,
-+                     uint64_t pd_addr);
- uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 9040b3e..6696fc1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -75,6 +75,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 	}
- 
- 	ib->vm = vm;
-+	ib->vm_id = 0;
- 
- 	return 0;
- }
-@@ -138,7 +139,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		return -EINVAL;
- 	}
- 
--	if (vm && !ibs->grabbed_vmid) {
-+	if (vm && !ibs->vm_id) {
- 		dev_err(adev->dev, "VM IB without ID\n");
- 		return -EINVAL;
- 	}
-@@ -151,10 +152,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 
- 	if (vm) {
- 		/* do context switch */
--                amdgpu_vm_flush(ring, vm, last_vm_update);
-+                amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr);
- 
- 		if (ring->funcs->emit_gds_switch)
--			amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
-+                        amdgpu_ring_emit_gds_switch(ring, ib->vm_id,
- 						    ib->gds_base, ib->gds_size,
- 						    ib->gws_base, ib->gws_size,
- 						    ib->oa_base, ib->oa_size);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index 10ff227..af9bae6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -105,16 +105,23 @@ static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
- 
-        struct fence *fence = amdgpu_sync_get_fence(&job->sync);
- 
--       if (fence == NULL && vm && !job->ibs->grabbed_vmid) {
-+       if (fence == NULL && vm && !job->ibs->vm_id) {
-                struct amdgpu_ring *ring = job->ring;
-+               unsigned i, vm_id;
-+               uint64_t vm_pd_addr;
-                int r;
- 
-                r = amdgpu_vm_grab_id(vm, ring, &job->sync,
--                                     &job->base.s_fence->base);
-+                                      &job->base.s_fence->base,
-+                                      &vm_id, &vm_pd_addr);
-                if (r)
-                        DRM_ERROR("Error getting VM ID (%d)\n", r);
--               else
--                       job->ibs->grabbed_vmid = true;
-+               else {
-+                       for (i = 0; i < job->num_ibs; ++i) {
-+                               job->ibs[i].vm_id = vm_id;
-+                               job->ibs[i].vm_pd_addr = vm_pd_addr;
-+                       }
-+               }
- 
-                fence = amdgpu_sync_get_fence(&job->sync);
-        }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8e6786c..d464bde 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -50,6 +50,9 @@
-  * SI supports 16.
-  */
- 
-+/* Special value that no flush is necessary */
-+#define AMDGPU_VM_NO_FLUSH (~0ll)
-+
- /**
-  * amdgpu_vm_num_pde - return the number of page directory entries
-  *
-@@ -164,50 +167,69 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-  * Allocate an id for the vm, adding fences to the sync obj as necessary.
-  */
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
--		      struct amdgpu_sync *sync, struct fence *fence)
-+		      struct amdgpu_sync *sync, struct fence *fence,
-+		      unsigned *vm_id, uint64_t *vm_pd_addr)
- {
--	struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
-+	uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
- 	struct amdgpu_device *adev = ring->adev;
--	struct amdgpu_vm_manager_id *id;
-+	struct amdgpu_vm_id *id = &vm->ids[ring->idx];
-+	struct fence *updates = sync->last_vm_update;
- 	int r;
- 
- 	mutex_lock(&adev->vm_manager.lock);
- 
- 	/* check if the id is still valid */
--	if (vm_id->id) {
-+	if (id->mgr_id) {
-+		struct fence *flushed = id->flushed_updates;
-+		bool is_later;
- 		long owner;
- 
--		id = &adev->vm_manager.ids[vm_id->id];
--		owner = atomic_long_read(&id->owner);
--		if (owner == (long)vm) {
--			list_move_tail(&id->list, &adev->vm_manager.ids_lru);
--			trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx);
-+		if (!flushed)
-+			is_later = true;
-+		else if (!updates)
-+			is_later = false;
-+		else
-+			is_later = fence_is_later(updates, flushed);
-+
-+		owner = atomic_long_read(&id->mgr_id->owner);
-+		if (!is_later && owner == (long)id &&
-+		    pd_addr == id->pd_gpu_addr) {
-+
-+			fence_put(id->mgr_id->active);
-+			id->mgr_id->active = fence_get(fence);
-+
-+			list_move_tail(&id->mgr_id->list,
-+				       &adev->vm_manager.ids_lru);
- 
--			fence_put(id->active);
--			id->active = fence_get(fence);
-+			*vm_id = id->mgr_id - adev->vm_manager.ids;
-+			*vm_pd_addr = AMDGPU_VM_NO_FLUSH;
-+			trace_amdgpu_vm_grab_id(vm, *vm_id, ring->idx);
- 
- 			mutex_unlock(&adev->vm_manager.lock);
- 			return 0;
- 		}
- 	}
- 
--	/* we definately need to flush */
--	vm_id->pd_gpu_addr = ~0ll;
-+	id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru,
-+				      struct amdgpu_vm_manager_id,
-+				      list);
- 
--	id = list_first_entry(&adev->vm_manager.ids_lru,
--			      struct amdgpu_vm_manager_id,
--			      list);
--	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
--	atomic_long_set(&id->owner, (long)vm);
-+	r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active);
-+	if (!r) {
-+		fence_put(id->mgr_id->active);
-+		id->mgr_id->active = fence_get(fence);
- 
--	vm_id->id = id - adev->vm_manager.ids;
--	trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx);
-+		fence_put(id->flushed_updates);
-+		id->flushed_updates = fence_get(updates);
- 
--	r = amdgpu_sync_fence(ring->adev, sync, id->active);
-+		id->pd_gpu_addr = pd_addr;
- 
--	if (!r) {
--		fence_put(id->active);
--		id->active = fence_get(fence);
-+		list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru);
-+		atomic_long_set(&id->mgr_id->owner, (long)id);
-+
-+		*vm_id = id->mgr_id - adev->vm_manager.ids;
-+		*vm_pd_addr = pd_addr;
-+		trace_amdgpu_vm_grab_id(vm, *vm_id, ring->idx);
- 	}
- 
- 	mutex_unlock(&adev->vm_manager.lock);
-@@ -218,35 +240,18 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
-  * amdgpu_vm_flush - hardware flush the vm
-  *
-  * @ring: ring to use for flush
-- * @vm: vm we want to flush
-- * @updates: last vm update that we waited for
-+ * @vmid: vmid number to use
-+ * @pd_addr: address of the page directory
-  *
-- * Flush the vm.
-+ * Emit a VM flush when it is necessary.
-  */
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
--		     struct amdgpu_vm *vm,
--		     struct fence *updates)
-+		     unsigned vmid,
-+		     uint64_t pd_addr)
- {
--	uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
--	struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
--	struct fence *flushed_updates = vm_id->flushed_updates;
--	bool is_later;
--
--	if (!flushed_updates)
--		is_later = true;
--	else if (!updates)
--		is_later = false;
--	else
--		is_later = fence_is_later(updates, flushed_updates);
--
--	if (pd_addr != vm_id->pd_gpu_addr || is_later) {
--		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
--		if (is_later) {
--			vm_id->flushed_updates = fence_get(updates);
--			fence_put(flushed_updates);
--		}
--		vm_id->pd_gpu_addr = pd_addr;
--		amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
-+	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
-+		trace_amdgpu_vm_flush(pd_addr, ring->idx, vmid);
-+		amdgpu_ring_emit_vm_flush(ring, vmid, pd_addr);
- 	}
- }
- 
-@@ -1291,7 +1296,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	int i, r;
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		vm->ids[i].id = 0;
-+		vm->ids[i].mgr_id = NULL;
- 		vm->ids[i].flushed_updates = NULL;
- 	}
- 	vm->va = RB_ROOT;
-@@ -1385,13 +1390,13 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	amdgpu_bo_unref(&vm->page_directory);
- 	fence_put(vm->page_directory_fence);
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		unsigned id = vm->ids[i].id;
-+		struct amdgpu_vm_id *id = &vm->ids[i];
- 
--		atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner,
--				    (long)vm, 0);
--		fence_put(vm->ids[i].flushed_updates);
-+		if (id->mgr_id)
-+			atomic_long_cmpxchg(&id->mgr_id->owner,
-+					    (long)id, 0);
-+		fence_put(id->flushed_updates);
- 	}
--
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 2bf993c..db10010 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -212,7 +212,7 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
- static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
- 			   struct amdgpu_ib *ib)
- {
--	u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
-+	u32 extra_bits = ib->vm_id & 0xf;
- 	u32 next_rptr = ring->wptr + 5;
- 
- 	while ((next_rptr & 7) != 4)
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index c452048..d0cb200 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2043,8 +2043,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- 	else
- 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- 
--	control |= ib->length_dw |
--		(ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
-+	control |= ib->length_dw | (ib->vm_id << 24);
- 
- 	amdgpu_ring_write(ring, header);
- 	amdgpu_ring_write(ring,
-@@ -2072,8 +2071,7 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
- 
- 	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- 
--	control |= ib->length_dw |
--			   (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
-+	control |= ib->length_dw | (ib->vm_id << 24);
- 
- 	amdgpu_ring_write(ring, header);
- 	amdgpu_ring_write(ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 48bc114..fadbfd8 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4619,8 +4619,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- 	else
- 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- 
--	control |= ib->length_dw |
--		(ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
-+	control |= ib->length_dw | (ib->vm_id << 24);
- 
- 	amdgpu_ring_write(ring, header);
- 	amdgpu_ring_write(ring,
-@@ -4649,8 +4648,7 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
- 
- 	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
- 
--	control |= ib->length_dw |
--			   (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
-+	control |= ib->length_dw | (ib->vm_id << 24);
- 
- 	amdgpu_ring_write(ring, header);
- 	amdgpu_ring_write(ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 1f70d83..1562291 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -244,7 +244,7 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
- static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
- 				   struct amdgpu_ib *ib)
- {
--	u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
-+	u32 vmid = ib->vm_id & 0xf;
- 	u32 next_rptr = ring->wptr + 5;
- 
- 	while ((next_rptr & 7) != 2)
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 2389bdb..d748a3a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -355,7 +355,7 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
- static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
- 				   struct amdgpu_ib *ib)
- {
--	u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
-+	u32 vmid = ib->vm_id & 0xf;
- 	u32 next_rptr = ring->wptr + 5;
- 
- 	while ((next_rptr & 7) != 2)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0336-drm-amdgpu-trace-the-pd_addr-in-vm_grab_id-as-well.patch b/common/recipes-kernel/linux/files/0336-drm-amdgpu-trace-the-pd_addr-in-vm_grab_id-as-well.patch
deleted file mode 100644
index 6aadb63d..00000000
--- a/common/recipes-kernel/linux/files/0336-drm-amdgpu-trace-the-pd_addr-in-vm_grab_id-as-well.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From fc314f63b963a4f72df4179ce8d95b6c3c3c1cbd Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 26 Feb 2016 16:18:36 +0100
-Subject: [PATCH 0336/1110] drm/amdgpu: trace the pd_addr in vm_grab_id as well
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Makes matching it to the flushes much easier.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 19 +++++++++++--------
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  5 +++--
- 2 files changed, 14 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-index 0254425..4bffcf6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
-@@ -100,21 +100,24 @@ TRACE_EVENT(amdgpu_sched_run_job,
- 
- 
- TRACE_EVENT(amdgpu_vm_grab_id,
--	    TP_PROTO(struct amdgpu_vm *vm, unsigned vmid, int ring),
--	    TP_ARGS(vm, vmid, ring),
-+	    TP_PROTO(struct amdgpu_vm *vm, int ring, unsigned vmid,
-+		     uint64_t pd_addr),
-+	    TP_ARGS(vm, ring, vmid, pd_addr),
- 	    TP_STRUCT__entry(
- 			     __field(struct amdgpu_vm *, vm)
--			     __field(u32, vmid)
- 			     __field(u32, ring)
-+			     __field(u32, vmid)
-+			     __field(u64, pd_addr)
- 			     ),
- 
- 	    TP_fast_assign(
- 			   __entry->vm = vm;
--			   __entry->vmid = vmid;
- 			   __entry->ring = ring;
-+			   __entry->vmid = vmid;
-+			   __entry->pd_addr = pd_addr;
- 			   ),
--	    TP_printk("vm=%p, id=%u, ring=%u", __entry->vm, __entry->vmid,
--		      __entry->ring)
-+	    TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx", __entry->vm,
-+		      __entry->ring, __entry->vmid, __entry->pd_addr)
- );
- 
- TRACE_EVENT(amdgpu_vm_bo_map,
-@@ -231,8 +234,8 @@ TRACE_EVENT(amdgpu_vm_flush,
- 			   __entry->ring = ring;
- 			   __entry->id = id;
- 			   ),
--	    TP_printk("pd_addr=%010Lx, ring=%u, id=%u",
--		      __entry->pd_addr, __entry->ring, __entry->id)
-+	    TP_printk("ring=%u, id=%u, pd_addr=%010Lx",
-+		      __entry->ring, __entry->id, __entry->pd_addr)
- );
- 
- TRACE_EVENT(amdgpu_bo_list_set,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index d464bde..5bea6da 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -203,7 +203,8 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 
- 			*vm_id = id->mgr_id - adev->vm_manager.ids;
- 			*vm_pd_addr = AMDGPU_VM_NO_FLUSH;
--			trace_amdgpu_vm_grab_id(vm, *vm_id, ring->idx);
-+			trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id,
-+						*vm_pd_addr);
- 
- 			mutex_unlock(&adev->vm_manager.lock);
- 			return 0;
-@@ -229,7 +230,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 
- 		*vm_id = id->mgr_id - adev->vm_manager.ids;
- 		*vm_pd_addr = pd_addr;
--		trace_amdgpu_vm_grab_id(vm, *vm_id, ring->idx);
-+		trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
- 	}
- 
- 	mutex_unlock(&adev->vm_manager.lock);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0337-drm-amdgpu-fix-rb-bitmap-cu-bitmap-calculation.patch b/common/recipes-kernel/linux/files/0337-drm-amdgpu-fix-rb-bitmap-cu-bitmap-calculation.patch
deleted file mode 100644
index be55999b..00000000
--- a/common/recipes-kernel/linux/files/0337-drm-amdgpu-fix-rb-bitmap-cu-bitmap-calculation.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From 009b73a51358b0ed72610b683f8fe866a8c45fc8 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Thu, 3 Mar 2016 12:59:49 +0800
-Subject: [PATCH 0337/1110] drm/amdgpu: fix rb bitmap & cu bitmap calculation
-
-Fix some copy paste typos.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cikd.h     |  3 ---
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 15 +++++++--------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |  9 ++++++---
- drivers/gpu/drm/amd/amdgpu/vid.h      |  2 --
- 4 files changed, 13 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
-index 7f6d457..60d4493 100644
---- a/drivers/gpu/drm/amd/amdgpu/cikd.h
-+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
-@@ -46,9 +46,6 @@
- #define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
- #define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003
- 
--#define CIK_RB_BITMAP_WIDTH_PER_SH     2
--#define HAWAII_RB_BITMAP_WIDTH_PER_SH  4
--
- #define AMDGPU_NUM_OF_VMIDS	8
- 
- #define		PIPEID(x)					((x) << 0)
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index d0cb200..361ce1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1637,18 +1637,16 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
- 	int i, j;
- 	u32 data;
- 	u32 active_rbs = 0;
-+	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
-+					adev->gfx.config.max_sh_per_se;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
- 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
- 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
- 			gfx_v7_0_select_se_sh(adev, i, j);
- 			data = gfx_v7_0_get_rb_active_bitmap(adev);
--			if (adev->asic_type == CHIP_HAWAII)
--				active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
--						       HAWAII_RB_BITMAP_WIDTH_PER_SH);
--			else
--				active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
--						       CIK_RB_BITMAP_WIDTH_PER_SH);
-+			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
-+					       rb_bitmap_width_per_sh);
- 		}
- 	}
- 	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-@@ -3833,8 +3831,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
- 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
- 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
- 
--	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
--				       adev->gfx.config.max_sh_per_se);
-+	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
- 
- 	return (~data) & mask;
- }
-@@ -5245,6 +5242,8 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
- 	if (!adev || !cu_info)
- 		return -EINVAL;
- 
-+	memset(cu_info, 0, sizeof(*cu_info));
-+
- 	mutex_lock(&adev->grbm_idx_mutex);
- 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
- 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index fadbfd8..1cda1af 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2615,6 +2615,8 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
- 	int i, j;
- 	u32 data;
- 	u32 active_rbs = 0;
-+	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
-+					adev->gfx.config.max_sh_per_se;
- 
- 	mutex_lock(&adev->grbm_idx_mutex);
- 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
-@@ -2622,7 +2624,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
- 			gfx_v8_0_select_se_sh(adev, i, j);
- 			data = gfx_v8_0_get_rb_active_bitmap(adev);
- 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
--					       RB_BITMAP_WIDTH_PER_SH);
-+					       rb_bitmap_width_per_sh);
- 		}
- 	}
- 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-@@ -5127,8 +5129,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
- 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
- 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
- 
--	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
--				       adev->gfx.config.max_sh_per_se);
-+	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
- 
- 	return (~data) & mask;
- }
-@@ -5142,6 +5143,8 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
- 	if (!adev || !cu_info)
- 		return -EINVAL;
- 
-+	memset(cu_info, 0, sizeof(*cu_info));
-+
- 	mutex_lock(&adev->grbm_idx_mutex);
- 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
- 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
-index d98aa9d..ace4997 100644
---- a/drivers/gpu/drm/amd/amdgpu/vid.h
-+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
-@@ -71,8 +71,6 @@
- #define		VMID(x)						((x) << 4)
- #define		QUEUEID(x)					((x) << 8)
- 
--#define RB_BITMAP_WIDTH_PER_SH     2
--
- #define MC_SEQ_MISC0__MT__MASK	0xf0000000
- #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
- #define MC_SEQ_MISC0__MT__DDR2   0x20000000
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0338-drm-amd-powerplay-refine-the-dmesg-info.patch b/common/recipes-kernel/linux/files/0338-drm-amd-powerplay-refine-the-dmesg-info.patch
deleted file mode 100644
index 1b24b793..00000000
--- a/common/recipes-kernel/linux/files/0338-drm-amd-powerplay-refine-the-dmesg-info.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From f8a63f77554bf4be64656763c42314e167a9eba0 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 21 Jan 2016 19:33:56 +0800
-Subject: [PATCH 0338/1110] drm/amd/powerplay: refine the dmesg info.
-
-this do not mean driver error.
-
-Change-Id: If2080eb4b79fc6389280b7c75cb7998d77090739
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c       | 3 ++-
- drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c | 9 +++++++--
- 2 files changed, 9 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index b8d6a82..727d5c9 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -744,8 +744,9 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
- 		cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
- 
- 	clock = hwmgr->display_config.min_core_set_clock;
-+;
- 	if (clock == 0)
--		printk(KERN_ERR "[ powerplay ] min_core_set_clock not set\n");
-+		printk(KERN_INFO "[ powerplay ] min_core_set_clock not set\n");
- 
- 	if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
- 		cz_hwmgr->sclk_dpm.hard_min_clk = clock;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-index 9deadab..72cfecc 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-@@ -34,6 +34,11 @@ static int phm_run_table(struct pp_hwmgr *hwmgr,
- 	int result = 0;
- 	phm_table_function *function;
- 
-+	if (rt_table->function_list == NULL) {
-+		printk(KERN_INFO "[ powerplay ] this function not implement!\n");
-+		return 0;
-+	}
-+
- 	for (function = rt_table->function_list; NULL != *function; function++) {
- 		int tmp = (*function)(hwmgr, input, output, temp_storage, result);
- 
-@@ -57,9 +62,9 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr,
- 	int result = 0;
- 	void *temp_storage = NULL;
- 
--	if (hwmgr == NULL || rt_table == NULL || rt_table->function_list == NULL) {
-+	if (hwmgr == NULL || rt_table == NULL) {
- 		printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n");
--		return 0; /*temp return ture because some function not implement on some asic */
-+		return -EINVAL;
- 	}
- 
- 	if (0 != rt_table->storage_size) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0339-drm-amdgpu-ci-drop-some-old-thermal-setup.patch b/common/recipes-kernel/linux/files/0339-drm-amdgpu-ci-drop-some-old-thermal-setup.patch
deleted file mode 100644
index 2156dd00..00000000
--- a/common/recipes-kernel/linux/files/0339-drm-amdgpu-ci-drop-some-old-thermal-setup.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From c0a902648aba37e2a68d7116a3b9101a05839f0a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 3 Mar 2016 11:28:24 -0500
-Subject: [PATCH 0339/1110] drm/amdgpu/ci: drop some old thermal setup
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This was leftover from a long time ago and is not longer needed
-since the thermal controller setup code was added.  Additional
-mucking with the thermal interrupts can cause spurious thermal
-events which can lead to unnecessary state changes.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 24 ------------------------
- 1 file changed, 24 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 474ca02..f66db20 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -5395,30 +5395,6 @@ static int ci_dpm_enable(struct amdgpu_device *adev)
- 
- 	ci_update_current_ps(adev, boot_ps);
- 
--	if (adev->irq.installed &&
--	    amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
--#if 0
--		PPSMC_Result result;
--#endif
--		ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
--						       CISLANDS_TEMP_RANGE_MAX);
--		if (ret) {
--			DRM_ERROR("ci_thermal_set_temperature_range failed\n");
--			return ret;
--		}
--		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
--			       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
--		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
--			       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
--
--#if 0
--		result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
--
--		if (result != PPSMC_Result_OK)
--			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
--#endif
--	}
--
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0340-drm-amdgpu-ci-remove-redundant-pcie-setup.patch b/common/recipes-kernel/linux/files/0340-drm-amdgpu-ci-remove-redundant-pcie-setup.patch
deleted file mode 100644
index b12db004..00000000
--- a/common/recipes-kernel/linux/files/0340-drm-amdgpu-ci-remove-redundant-pcie-setup.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 964dba44d2eed69d8273f46ff814ecc941ffb7d1 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 3 Mar 2016 12:28:37 -0500
-Subject: [PATCH 0340/1110] drm/amdgpu/ci: remove redundant pcie setup
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Looks like this got leftover by accident.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 20 --------------------
- 1 file changed, 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index f66db20..2a51bc7 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -4381,26 +4381,6 @@ static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
- 				}
- 			}
- 		}
--		if ((!pi->pcie_dpm_key_disabled) &&
--		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
--			levels = 0;
--			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
--			while (tmp >>= 1)
--				levels++;
--			if (levels) {
--				ret = ci_dpm_force_state_pcie(adev, level);
--				if (ret)
--					return ret;
--				for (i = 0; i < adev->usec_timeout; i++) {
--					tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
--					TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
--					TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
--					if (tmp == levels)
--						break;
--					udelay(1);
--				}
--			}
--		}
- 	} else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
- 		if ((!pi->sclk_dpm_key_disabled) &&
- 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch b/common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch
deleted file mode 100644
index 79bb0909..00000000
--- a/common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From dd69ad41ab1d50b183a110a9974faefc71a6fc52 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 3 Mar 2016 12:27:46 -0500
-Subject: [PATCH 0341/1110] drm/amdgpu/ci: sync up with dpm changes from radeon
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Looks like radeon commit:
-d3052b8ce8a308d2086519fa5f7c4966257ea184
-was missed.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 2a51bc7..1f9109d 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -3017,7 +3017,6 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev,
- 						      &memory_level->MinVddcPhases);
- 
- 	memory_level->EnabledForThrottle = 1;
--	memory_level->EnabledForActivity = 1;
- 	memory_level->UpH = 0;
- 	memory_level->DownH = 100;
- 	memory_level->VoltageDownH = 0;
-@@ -3376,7 +3375,6 @@ static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
- 	graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
- 	graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
- 	graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
--	graphic_level->EnabledForActivity = 1;
- 
- 	return 0;
- }
-@@ -3407,6 +3405,7 @@ static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
- 			pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
- 				PPSMC_DISPLAY_WATERMARK_HIGH;
- 	}
-+	pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
- 
- 	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
- 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
-@@ -3450,6 +3449,8 @@ static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
- 			return ret;
- 	}
- 
-+	pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-+
- 	if ((dpm_table->mclk_table.count >= 2) &&
- 	    ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
- 		pi->smc_state_table.MemoryLevel[1].MinVddc =
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0342-drm-amdgpu-delete-set-but-not-read-member-has_uvd-fr.patch b/common/recipes-kernel/linux/files/0342-drm-amdgpu-delete-set-but-not-read-member-has_uvd-fr.patch
deleted file mode 100644
index dffb851a..00000000
--- a/common/recipes-kernel/linux/files/0342-drm-amdgpu-delete-set-but-not-read-member-has_uvd-fr.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From ce7f3a3cb7c929fba8aec40d490cb7dcd62c812a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sat, 5 Mar 2016 06:59:51 +0100
-Subject: [PATCH 0342/1110] drm/amdgpu: delete set-but-not-read member has_uvd
- from amdgpu_device
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Clean up leftover from radeon code.
-
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
- drivers/gpu/drm/amd/amdgpu/cik.c    | 2 --
- drivers/gpu/drm/amd/amdgpu/vi.c     | 4 ----
- 3 files changed, 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index ca1223f..05d525d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2017,7 +2017,6 @@ struct amdgpu_device {
- 	struct amdgpu_sdma		sdma;
- 
- 	/* uvd */
--	bool				has_uvd;
- 	struct amdgpu_uvd		uvd;
- 
- 	/* vce */
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 192ab13..bddc9ba 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -2028,8 +2028,6 @@ static int cik_common_early_init(void *handle)
- 
- 	adev->asic_funcs = &cik_asic_funcs;
- 
--	adev->has_uvd = true;
--
- 	adev->rev_id = cik_get_rev_id(adev);
- 	adev->external_rev_id = 0xFF;
- 	switch (adev->asic_type) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index b72cf06..1c120ef 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1071,26 +1071,22 @@ static int vi_common_early_init(void *handle)
- 	adev->external_rev_id = 0xFF;
- 	switch (adev->asic_type) {
- 	case CHIP_TOPAZ:
--		adev->has_uvd = false;
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = 0x1;
- 		break;
- 	case CHIP_FIJI:
--		adev->has_uvd = true;
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
- 	case CHIP_TONGA:
--		adev->has_uvd = true;
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
--		adev->has_uvd = true;
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0343-drm-amdgpu-Switch-to-drm_vblank_on-off-v2.patch b/common/recipes-kernel/linux/files/0343-drm-amdgpu-Switch-to-drm_vblank_on-off-v2.patch
deleted file mode 100644
index 927417c9..00000000
--- a/common/recipes-kernel/linux/files/0343-drm-amdgpu-Switch-to-drm_vblank_on-off-v2.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 7736faea95570291857765c25646204a9c9a8fdd Mon Sep 17 00:00:00 2001
-From: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date: Thu, 21 Jan 2016 11:08:58 +0100
-Subject: [PATCH 0343/1110] drm/amdgpu: Switch to drm_vblank_on/off (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Equivalent change to the radeon driver.
-
-Note that with radeon this caught a bug in the dri3 DDX
-implementation, which asked for vblank interrupts when the pipe is
-off. That bug needs to be fixed before we can merge this patch (if
-amdgpu is affected too). Michel discovered this one.
-
-v2: agd: switch dce8 as well.
-
-Acked-by: Michel Dänzer <michel.daenzer@amd.com>
-Cc: Michel Dänzer <michel.daenzer@amd.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  | 4 ++--
- 3 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index a8ac8a3..25b4680 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -2700,13 +2700,13 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
- 		type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
- 		amdgpu_irq_update(adev, &adev->crtc_irq, type);
- 		amdgpu_irq_update(adev, &adev->pageflip_irq, type);
--		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
-+		drm_vblank_on(dev, amdgpu_crtc->crtc_id);
- 		dce_v10_0_crtc_load_lut(crtc);
- 		break;
- 	case DRM_MODE_DPMS_STANDBY:
- 	case DRM_MODE_DPMS_SUSPEND:
- 	case DRM_MODE_DPMS_OFF:
--		drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
-+		drm_vblank_off(dev, amdgpu_crtc->crtc_id);
- 		if (amdgpu_crtc->enabled) {
- 			dce_v10_0_vga_enable(crtc, true);
- 			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index a7699be..41e94d4 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2691,13 +2691,13 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
- 		type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
- 		amdgpu_irq_update(adev, &adev->crtc_irq, type);
- 		amdgpu_irq_update(adev, &adev->pageflip_irq, type);
--		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
-+		drm_vblank_on(dev, amdgpu_crtc->crtc_id);
- 		dce_v11_0_crtc_load_lut(crtc);
- 		break;
- 	case DRM_MODE_DPMS_STANDBY:
- 	case DRM_MODE_DPMS_SUSPEND:
- 	case DRM_MODE_DPMS_OFF:
--		drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
-+		drm_vblank_off(dev, amdgpu_crtc->crtc_id);
- 		if (amdgpu_crtc->enabled) {
- 			dce_v11_0_vga_enable(crtc, true);
- 			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 628d7b2..a220711 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -2612,13 +2612,13 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
- 		type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
- 		amdgpu_irq_update(adev, &adev->crtc_irq, type);
- 		amdgpu_irq_update(adev, &adev->pageflip_irq, type);
--		drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
-+		drm_vblank_on(dev, amdgpu_crtc->crtc_id);
- 		dce_v8_0_crtc_load_lut(crtc);
- 		break;
- 	case DRM_MODE_DPMS_STANDBY:
- 	case DRM_MODE_DPMS_SUSPEND:
- 	case DRM_MODE_DPMS_OFF:
--		drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
-+		drm_vblank_off(dev, amdgpu_crtc->crtc_id);
- 		if (amdgpu_crtc->enabled) {
- 			dce_v8_0_vga_enable(crtc, true);
- 			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0344-drm-amdgpu-wait-engine-idle-before-vm-flush-for-sdma.patch b/common/recipes-kernel/linux/files/0344-drm-amdgpu-wait-engine-idle-before-vm-flush-for-sdma.patch
deleted file mode 100644
index fd3c0095..00000000
--- a/common/recipes-kernel/linux/files/0344-drm-amdgpu-wait-engine-idle-before-vm-flush-for-sdma.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From dd56d4223732ee78c20fbcebbf86e82c354d3483 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Wed, 2 Mar 2016 11:30:31 +0800
-Subject: [PATCH 0344/1110] drm/amdgpu: wait engine idle before vm flush for
- sdma
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 14 ++++++++++++++
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 15 +++++++++++++++
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 15 +++++++++++++++
- 3 files changed, 44 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index db10010..f751dc3 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -829,6 +829,20 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
- {
- 	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
- 			  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
-+	uint32_t seq = ring->fence_drv.sync_seq;
-+	uint64_t addr = ring->fence_drv.gpu_addr;
-+
-+	/* wait for idle */
-+	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
-+					    SDMA_POLL_REG_MEM_EXTRA_OP(0) |
-+					    SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
-+					    SDMA_POLL_REG_MEM_EXTRA_M));
-+	amdgpu_ring_write(ring, addr & 0xfffffffc);
-+	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
-+	amdgpu_ring_write(ring, seq); /* reference */
-+	amdgpu_ring_write(ring, 0xfffffff); /* mask */
-+	amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
-+
- 
- 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
- 	if (vm_id < 8) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 1562291..60c2721 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -885,6 +885,21 @@ static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib
- static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 					 unsigned vm_id, uint64_t pd_addr)
- {
-+	uint32_t seq = ring->fence_drv.sync_seq;
-+	uint64_t addr = ring->fence_drv.gpu_addr;
-+
-+	/* wait for idle */
-+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
-+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
-+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
-+			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
-+	amdgpu_ring_write(ring, addr & 0xfffffffc);
-+	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
-+	amdgpu_ring_write(ring, seq); /* reference */
-+	amdgpu_ring_write(ring, 0xfffffff); /* mask */
-+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
-+
- 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- 	if (vm_id < 8) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index d748a3a..d585ce2 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1035,6 +1035,21 @@ static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib
- static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 					 unsigned vm_id, uint64_t pd_addr)
- {
-+	uint32_t seq = ring->fence_drv.sync_seq;
-+	uint64_t addr = ring->fence_drv.gpu_addr;
-+
-+	/* wait for idle */
-+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
-+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
-+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
-+			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
-+	amdgpu_ring_write(ring, addr & 0xfffffffc);
-+	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
-+	amdgpu_ring_write(ring, seq); /* reference */
-+	amdgpu_ring_write(ring, 0xfffffff); /* mask */
-+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
-+
- 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- 	if (vm_id < 8) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0345-drm-amdgpu-add-hdp_invalidate-function.patch b/common/recipes-kernel/linux/files/0345-drm-amdgpu-add-hdp_invalidate-function.patch
deleted file mode 100644
index 639d9875..00000000
--- a/common/recipes-kernel/linux/files/0345-drm-amdgpu-add-hdp_invalidate-function.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From b2fd47596ec489aecd9616151d870a2bf14e8560 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 11:38:48 +0800
-Subject: [PATCH 0345/1110] drm/amdgpu: add hdp_invalidate function
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's called after emitting ibs.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++++
- 2 files changed, 7 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 05d525d..1269e3e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -290,6 +290,7 @@ struct amdgpu_ring_funcs {
- 	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
- 			      uint64_t pd_addr);
- 	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
-+	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
- 	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
- 				uint32_t gds_base, uint32_t gds_size,
- 				uint32_t gws_base, uint32_t gws_size,
-@@ -2194,6 +2195,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
- #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
- #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
-+#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
- #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
- #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
- #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 6696fc1..1966d66 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -177,6 +177,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		ring->current_ctx = ctx;
- 	}
- 
-+	if (vm) {
-+		if (ring->funcs->emit_hdp_invalidate)
-+			amdgpu_ring_emit_hdp_invalidate(ring);
-+	}
-+
- 	r = amdgpu_fence_emit(ring, owner, &ib->fence);
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0346-drm-amdgpu-add-hdp-invalidation-for-gfx7.patch b/common/recipes-kernel/linux/files/0346-drm-amdgpu-add-hdp-invalidation-for-gfx7.patch
deleted file mode 100644
index 8db64cfe..00000000
--- a/common/recipes-kernel/linux/files/0346-drm-amdgpu-add-hdp-invalidation-for-gfx7.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 679ad153d12255e8029b3f4bc3bfb2ecd6279dd7 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 11:46:40 +0800
-Subject: [PATCH 0346/1110] drm/amdgpu: add hdp invalidation for gfx7
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 361ce1b..e1140a4 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1925,6 +1925,25 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- }
- 
- /**
-+ * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @ridx: amdgpu ring index
-+ *
-+ * Emits an hdp invalidate on the cp.
-+ */
-+static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-+{
-+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-+	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-+				 WRITE_DATA_DST_SEL(0) |
-+				 WR_CONFIRM));
-+	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-+	amdgpu_ring_write(ring, 0);
-+	amdgpu_ring_write(ring, 1);
-+}
-+
-+/**
-  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
-  *
-  * @adev: amdgpu_device pointer
-@@ -5145,6 +5164,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
- 	.test_ring = gfx_v7_0_ring_test_ring,
- 	.test_ib = gfx_v7_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-@@ -5161,6 +5181,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
- 	.test_ring = gfx_v7_0_ring_test_ring,
- 	.test_ib = gfx_v7_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0347-drm-amdgpu-add-hdp-invalidation-for-gfx8.patch b/common/recipes-kernel/linux/files/0347-drm-amdgpu-add-hdp-invalidation-for-gfx8.patch
deleted file mode 100644
index f8c6b50b..00000000
--- a/common/recipes-kernel/linux/files/0347-drm-amdgpu-add-hdp-invalidation-for-gfx8.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From de3ad4ceac667e19bcba2a1f3632bac8fabba2d8 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 11:55:13 +0800
-Subject: [PATCH 0347/1110] drm/amdgpu: add hdp invalidation for gfx8
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 1cda1af..fbe148d 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4589,6 +4589,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, 0x20); /* poll interval */
- }
- 
-+static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-+{
-+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-+	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-+				 WRITE_DATA_DST_SEL(0) |
-+				 WR_CONFIRM));
-+	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-+	amdgpu_ring_write(ring, 0);
-+	amdgpu_ring_write(ring, 1);
-+
-+}
-+
- static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- 				  struct amdgpu_ib *ib)
- {
-@@ -5031,6 +5043,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
- 	.test_ring = gfx_v8_0_ring_test_ring,
- 	.test_ib = gfx_v8_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
-@@ -5047,6 +5060,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
- 	.test_ring = gfx_v8_0_ring_test_ring,
- 	.test_ib = gfx_v8_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0348-drm-amdgpu-add-hdp-invalidation-for-cik-sdma.patch b/common/recipes-kernel/linux/files/0348-drm-amdgpu-add-hdp-invalidation-for-cik-sdma.patch
deleted file mode 100644
index e61bc624..00000000
--- a/common/recipes-kernel/linux/files/0348-drm-amdgpu-add-hdp-invalidation-for-cik-sdma.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 459ab370aa18ef8627ec39cae4012d3ab3dfa9e0 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 12:05:44 +0800
-Subject: [PATCH 0348/1110] drm/amdgpu: add hdp invalidation for cik sdma
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index f751dc3..f94d707 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -261,6 +261,13 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- 	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
- }
- 
-+static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-+{
-+	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-+	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-+	amdgpu_ring_write(ring, 1);
-+}
-+
- /**
-  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
-  *
-@@ -1286,6 +1293,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
- 	.emit_fence = cik_sdma_ring_emit_fence,
- 	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
- 	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
- 	.test_ring = cik_sdma_ring_test_ring,
- 	.test_ib = cik_sdma_ring_test_ib,
- 	.insert_nop = cik_sdma_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0349-drm-amdgpu-add-hdp-invalidation-for-sdma-v2_4.patch b/common/recipes-kernel/linux/files/0349-drm-amdgpu-add-hdp-invalidation-for-sdma-v2_4.patch
deleted file mode 100644
index 8427d919..00000000
--- a/common/recipes-kernel/linux/files/0349-drm-amdgpu-add-hdp-invalidation-for-sdma-v2_4.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 25230fa2b61a6c19e48ab80ab525783c1e4e8914 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 12:06:34 +0800
-Subject: [PATCH 0349/1110] drm/amdgpu: add hdp invalidation for sdma v2_4
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 60c2721..602a467 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -300,6 +300,13 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
- }
- 
-+static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-+{
-+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-+	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-+	amdgpu_ring_write(ring, 1);
-+}
- /**
-  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
-  *
-@@ -1291,6 +1298,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
- 	.emit_fence = sdma_v2_4_ring_emit_fence,
- 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
- 	.test_ring = sdma_v2_4_ring_test_ring,
- 	.test_ib = sdma_v2_4_ring_test_ib,
- 	.insert_nop = sdma_v2_4_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0350-drm-amdgpu-add-hdp-invalidation-for-sdma-v3_0.patch b/common/recipes-kernel/linux/files/0350-drm-amdgpu-add-hdp-invalidation-for-sdma-v3_0.patch
deleted file mode 100644
index 836526df..00000000
--- a/common/recipes-kernel/linux/files/0350-drm-amdgpu-add-hdp-invalidation-for-sdma-v3_0.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 7a6f44ca57279e49c1a7f0f2ccf0e5b98ffbf5ab Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 12:06:45 +0800
-Subject: [PATCH 0350/1110] drm/amdgpu: add hdp invalidation for sdma v3_0
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index d585ce2..e56020e 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -410,6 +410,14 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
- }
- 
-+static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-+{
-+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-+	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-+	amdgpu_ring_write(ring, 1);
-+}
-+
- /**
-  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
-  *
-@@ -1558,6 +1566,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
- 	.emit_fence = sdma_v3_0_ring_emit_fence,
- 	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
-+	.emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
- 	.test_ring = sdma_v3_0_ring_test_ring,
- 	.test_ib = sdma_v3_0_ring_test_ib,
- 	.insert_nop = sdma_v3_0_ring_insert_nop,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0351-drm-amdgpu-Clear-HDP_MISC_CNTL.HDP_FLUSH_INVALIDATE_.patch b/common/recipes-kernel/linux/files/0351-drm-amdgpu-Clear-HDP_MISC_CNTL.HDP_FLUSH_INVALIDATE_.patch
deleted file mode 100644
index dc34584a..00000000
--- a/common/recipes-kernel/linux/files/0351-drm-amdgpu-Clear-HDP_MISC_CNTL.HDP_FLUSH_INVALIDATE_.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 91549ea3878e482746ccc0033dd73e9d2050f096 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 3 Mar 2016 14:47:54 +0800
-Subject: [PATCH 0351/1110] drm/amdgpu: Clear
- HDP_MISC_CNTL.HDP_FLUSH_INVALIDATE_CACHE
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-So that we can invalidate and flush the HDP independently
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index 3065184..09829f1 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -339,7 +339,7 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
- 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
- 
- 	tmp = RREG32(mmHDP_MISC_CNTL);
--	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
-+	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
- 	WREG32(mmHDP_MISC_CNTL, tmp);
- 
- 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index f589e1b..bb254f1 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -386,7 +386,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
- 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
- 
- 	tmp = RREG32(mmHDP_MISC_CNTL);
--	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
-+	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
- 	WREG32(mmHDP_MISC_CNTL, tmp);
- 
- 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0352-drm-amdgpu-sync-to-the-active-user-on-reusing-a-VMID.patch b/common/recipes-kernel/linux/files/0352-drm-amdgpu-sync-to-the-active-user-on-reusing-a-VMID.patch
deleted file mode 100644
index 3094c72c..00000000
--- a/common/recipes-kernel/linux/files/0352-drm-amdgpu-sync-to-the-active-user-on-reusing-a-VMID.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 94f6825d010153b141f45831b76e26437470e81a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 3 Mar 2016 10:50:01 +0100
-Subject: [PATCH 0352/1110] drm/amdgpu: sync to the active user on reusing a
- VMID
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 5bea6da..6e23841 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -195,6 +195,13 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		if (!is_later && owner == (long)id &&
- 		    pd_addr == id->pd_gpu_addr) {
- 
-+			r = amdgpu_sync_fence(ring->adev, sync,
-+					      id->mgr_id->active);
-+			if (r) {
-+				mutex_unlock(&adev->vm_manager.lock);
-+				return r;
-+			}
-+
- 			fence_put(id->mgr_id->active);
- 			id->mgr_id->active = fence_get(fence);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0353-drm-amdgpu-group-userptr-in-the-BO-list-v2.patch b/common/recipes-kernel/linux/files/0353-drm-amdgpu-group-userptr-in-the-BO-list-v2.patch
deleted file mode 100644
index 2b26410b..00000000
--- a/common/recipes-kernel/linux/files/0353-drm-amdgpu-group-userptr-in-the-BO-list-v2.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From fff6698938982f36960e290820d12d49d52714a0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 22 Feb 2016 15:40:59 +0100
-Subject: [PATCH 0353/1110] drm/amdgpu: group userptr in the BO list v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We need them together with the next patch.
-
-v2: Don't take bo reference twice
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 23 +++++++++++++++--------
- 1 file changed, 15 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index 3406527..82f8caf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -91,7 +91,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo;
- 	struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo;
- 
--	bool has_userptr = false;
-+        unsigned last_entry = 0, first_userptr = num_entries;
- 	unsigned i;
- 
- 	array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry));
-@@ -100,8 +100,9 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));
- 
- 	for (i = 0; i < num_entries; ++i) {
--		struct amdgpu_bo_list_entry *entry = &array[i];
-+                struct amdgpu_bo_list_entry *entry;
- 		struct drm_gem_object *gobj;
-+                struct amdgpu_bo *bo;
-                 struct mm_struct *usermm;
- 
- 		gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
-@@ -111,19 +112,25 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 			goto error_free;
-                 }
- 
--		entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
-+                bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
- 		drm_gem_object_unreference_unlocked(gobj);
--		entry->priority = min(info[i].bo_priority,
--				      AMDGPU_BO_LIST_MAX_PRIORITY);
--                usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm);
-+
-+                usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
-                 if (usermm) {
-                         if (usermm != current->mm) {
--                                amdgpu_bo_unref(&entry->robj);
-+                                amdgpu_bo_unref(&bo);
-                                 r = -EPERM;
-                                 goto error_free;
-                         }
-                         has_userptr = true;
-+                        entry = &array[--first_userptr];
-+                } else {
-+                        entry = &array[last_entry++];
-                 }
-+                
-+		entry->robj = bo;
-+                entry->priority = min(info[i].bo_priority,
-+                                      AMDGPU_BO_LIST_MAX_PRIORITY);
- 		entry->tv.bo = &entry->robj->tbo;
- 		entry->tv.shared = true;
- 
-@@ -145,7 +152,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	list->gds_obj = gds_obj;
- 	list->gws_obj = gws_obj;
- 	list->oa_obj = oa_obj;
--	list->has_userptr = has_userptr;
-+        list->first_userptr = first_userptr;
- 	list->array = array;
- 	list->num_entries = num_entries;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0354-drm-amdgpu-prevent-get_user_pages-recursion.patch b/common/recipes-kernel/linux/files/0354-drm-amdgpu-prevent-get_user_pages-recursion.patch
deleted file mode 100644
index 954516b9..00000000
--- a/common/recipes-kernel/linux/files/0354-drm-amdgpu-prevent-get_user_pages-recursion.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From 497ffcd5b59f717af1147661efe74bb2dca17733 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 3 Mar 2016 14:24:57 +0100
-Subject: [PATCH 0354/1110] drm/amdgpu: prevent get_user_pages recursion
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Remember the tasks which are inside get_user_pages()
-and ignore MMU callbacks from there.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 48 ++++++++++++++++++++++++++-------
- 1 file changed, 38 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index e5a684e..051cd39 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -494,13 +494,20 @@ static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_re
- /*
-  * TTM backend functions.
-  */
-+struct amdgpu_ttm_gup_task_list {
-+	struct list_head	list;
-+	struct task_struct	*task;
-+};
-+
- struct amdgpu_ttm_tt {
--	struct ttm_dma_tt		ttm;
--	struct amdgpu_device		*adev;
--	u64				offset;
--	uint64_t			userptr;
--	struct mm_struct		*usermm;
--	uint32_t			userflags;
-+	struct ttm_dma_tt	ttm;
-+	struct amdgpu_device	*adev;
-+	u64			offset;
-+	uint64_t		userptr;
-+	struct mm_struct	*usermm;
-+	uint32_t		userflags;
-+	spinlock_t              guptasklock;
-+	struct list_head        guptasks;
- };
- 
- /* prepare the sg table with the user pages */
-@@ -530,9 +537,20 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
- 		unsigned num_pages = ttm->num_pages - pinned;
- 		uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
- 		struct page **pages = ttm->pages + pinned;
-+		struct amdgpu_ttm_gup_task_list guptask;
-+
-+		guptask.task = current;
-+		spin_lock(&gtt->guptasklock);
-+		list_add(&guptask.list, &gtt->guptasks);
-+		spin_unlock(&gtt->guptasklock);
- 
- 		r = get_user_pages(current, current->mm, userptr, num_pages,
- 				   write, 0, pages, NULL);
-+
-+		spin_lock(&gtt->guptasklock);
-+		list_del(&guptask.list);
-+		spin_unlock(&gtt->guptasklock);
-+
- 		if (r < 0)
- 			goto release_pages;
- 
-@@ -783,6 +801,9 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
- 	gtt->userptr = addr;
- 	gtt->usermm = current->mm;
- 	gtt->userflags = flags;
-+	spin_lock_init(&gtt->guptasklock);
-+	INIT_LIST_HEAD(&gtt->guptasks);
-+
- 	return 0;
- }
- 
-@@ -800,18 +821,25 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
- 				  unsigned long end)
- {
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
-+	struct amdgpu_ttm_gup_task_list *entry;
- 	unsigned long size;
- 
--	if (gtt == NULL)
--		return false;
--
--	if (gtt->ttm.ttm.state != tt_bound || !gtt->userptr)
-+	if (gtt == NULL || !gtt->userptr)
- 		return false;
- 
- 	size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
- 	if (gtt->userptr > end || gtt->userptr + size <= start)
- 		return false;
- 
-+	spin_lock(&gtt->guptasklock);
-+	list_for_each_entry(entry, &gtt->guptasks, list) {
-+		if (entry->task == current) {
-+			spin_unlock(&gtt->guptasklock);
-+			return false;
-+		}
-+	}
-+	spin_unlock(&gtt->guptasklock);
-+
- 	return true;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0355-drm-amdgpu-cleanup-the-sync-code.patch b/common/recipes-kernel/linux/files/0355-drm-amdgpu-cleanup-the-sync-code.patch
deleted file mode 100644
index 04ab79bd..00000000
--- a/common/recipes-kernel/linux/files/0355-drm-amdgpu-cleanup-the-sync-code.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From ff04e9638d871d6353ffc46c35d80b64b0b2dd15 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 16 Feb 2016 16:23:02 +0100
-Subject: [PATCH 0355/1110] drm/amdgpu: cleanup the sync code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need for two functions doing the same, remove one and
-add comments what those functions actually do.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 48 ++++++++++++++++++++------------
- 1 file changed, 30 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index c15be00..87690cc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -50,6 +50,14 @@ void amdgpu_sync_create(struct amdgpu_sync *sync)
- 	sync->last_vm_update = NULL;
- }
- 
-+/**
-+ * amdgpu_sync_same_dev - test if fence belong to us
-+ *
-+ * @adev: amdgpu device to use for the test
-+ * @f: fence to test
-+ *
-+ * Test if the fence was issued by us.
-+ */
- static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
- {
- 	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
-@@ -68,17 +76,33 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
- 	return false;
- }
- 
--static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
-+/**
-+ * amdgpu_sync_get_owner - extract the owner of a fence
-+ *
-+ * @fence: fence get the owner from
-+ *
-+ * Extract who originally created the fence.
-+ */
-+static void *amdgpu_sync_get_owner(struct fence *f)
- {
- 	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
- 	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
-+
- 	if (s_fence)
--		return s_fence->owner == owner;
--	if (a_fence)
--		return a_fence->owner == owner;
--	return false;
-+		return s_fence->owner;
-+	else if (a_fence)
-+		return a_fence->owner;
-+	return AMDGPU_FENCE_OWNER_UNDEFINED;
- }
- 
-+/**
-+ * amdgpu_sync_keep_later - Keep the later fence
-+ *
-+ * @keep: existing fence to test
-+ * @fence: new fence
-+ *
-+ * Either keep the existing fence or the new one, depending which one is later.
-+ */
- static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence)
- {
- 	if (*keep && fence_is_later(*keep, fence))
-@@ -104,7 +128,7 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- 		return 0;
- 
- 	if (amdgpu_sync_same_dev(adev, f) &&
--	    amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM))
-+	    amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
- 		amdgpu_sync_keep_later(&sync->last_vm_update, f);
- 
- 	hash_for_each_possible(sync->fences, e, node, f->context) {
-@@ -124,18 +148,6 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- 	return 0;
- }
- 
--static void *amdgpu_sync_get_owner(struct fence *f)
--{
--	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
--	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
--
--	if (s_fence)
--		return s_fence->owner;
--	else if (a_fence)
--		return a_fence->owner;
--	return AMDGPU_FENCE_OWNER_UNDEFINED;
--}
--
- /**
-  * amdgpu_sync_resv - sync to a reservation object
-  *
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch b/common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch
deleted file mode 100644
index 3328fe59..00000000
--- a/common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch
+++ /dev/null
@@ -1,292 +0,0 @@
-From b113c3ab8ac34ccfd88675b75bcc47ef412ed45d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 16 Feb 2016 10:57:10 +0100
-Subject: [PATCH 0356/1110] drm/amdgpu: remove HW fence owner
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used any more since we now always use the sheduler.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 9 ++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c    | 6 ++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c  | 8 +-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   | 3 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c   | 7 ++-----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c     | 3 +--
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c     | 3 +--
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c     | 6 ++----
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c    | 3 +--
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c    | 3 +--
- 12 files changed, 16 insertions(+), 43 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1269e3e..27b1dc3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -370,9 +370,6 @@ struct amdgpu_fence {
- 	struct amdgpu_ring		*ring;
- 	uint64_t			seq;
- 
--	/* filp or special value for fence creator */
--	void				*owner;
--
- 	wait_queue_t			fence_wake;
- };
- 
-@@ -393,8 +390,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
- 				   unsigned irq_type);
- void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
- void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
--int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
--		      struct amdgpu_fence **fence);
-+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence **fence);
- void amdgpu_fence_process(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
-@@ -1141,8 +1137,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 		  unsigned size, struct amdgpu_ib *ib);
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
--		       struct amdgpu_ib *ib, void *owner);
--                       struct fence *last_vm_update,
-+                       struct amdgpu_ib *ib, struct fence *last_vm_update,
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
- void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
- int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 97db196..d94b13a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -91,25 +91,21 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
-  * amdgpu_fence_emit - emit a fence on the requested ring
-  *
-  * @ring: ring the fence is associated with
-- * @owner: creator of the fence
-  * @fence: amdgpu fence object
-  *
-  * Emits a fence command on the requested ring (all asics).
-  * Returns 0 on success, -ENOMEM on failure.
-  */
--int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
--		      struct amdgpu_fence **fence)
-+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence **fence)
- {
- 	struct amdgpu_device *adev = ring->adev;
- 
--	/* we are protected by the ring emission mutex */
- 	*fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
- 	if ((*fence) == NULL) {
- 		return -ENOMEM;
- 	}
- 	(*fence)->seq = ++ring->fence_drv.sync_seq;
- 	(*fence)->ring = ring;
--	(*fence)->owner = owner;
- 	fence_init(&(*fence)->base, &amdgpu_fence_ops,
- 		&ring->fence_drv.fence_queue.lock,
- 		adev->fence_context + ring->idx,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 1966d66..dc5683c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -101,7 +101,6 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
-  * @adev: amdgpu_device pointer
-  * @num_ibs: number of IBs to schedule
-  * @ibs: IB objects to schedule
-- * @owner: owner for creating the fences
-  *
-  * Schedule an IB on the associated ring (all asics).
-  * Returns 0 on success, error on failure.
-@@ -117,8 +116,7 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
-  * to SI there was just a DE IB.
-  */
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
--		       struct amdgpu_ib *ibs, void *owner,
--                       struct fence *last_vm_update,
-+                       struct amdgpu_ib *ibs, struct fence *last_vm_update,
- 		       struct fence **f)
- {
-         struct amdgpu_device *adev = ring->adev;
-@@ -182,7 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 			amdgpu_ring_emit_hdp_invalidate(ring);
- 	}
- 
--	r = amdgpu_fence_emit(ring, owner, &ib->fence);
-+	r = amdgpu_fence_emit(ring, &ib->fence);
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
- 		ring->current_ctx = old_ctx;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index af9bae6..a3baec9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -148,7 +148,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
-        }
- 
-        trace_amdgpu_sched_run_job(job);
--       r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job->owner,
-+       r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
-                               job->sync.last_vm_update, &fence);
-        if (r) {
-                DRM_ERROR("Error scheduling IBs (%d)\n", r);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index 87690cc..e367342 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -60,12 +60,8 @@ void amdgpu_sync_create(struct amdgpu_sync *sync)
-  */
- static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
- {
--	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
- 	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
- 
--	if (a_fence)
--		return a_fence->ring->adev == adev;
--
- 	if (s_fence) {
- 		struct amdgpu_ring *ring;
- 
-@@ -85,13 +81,11 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
-  */
- static void *amdgpu_sync_get_owner(struct fence *f)
- {
--	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
- 	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
- 
- 	if (s_fence)
- 		return s_fence->owner;
--	else if (a_fence)
--		return a_fence->owner;
-+
- 	return AMDGPU_FENCE_OWNER_UNDEFINED;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 726f0cb..c00df2f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -905,8 +905,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
-         if (direct) {
--                r = amdgpu_ib_schedule(ring, 1, ib,
--                                       AMDGPU_FENCE_OWNER_UNDEFINED, NULL, &f);
-+                r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-                 if (r)
-                         goto err_free;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 547e084..125dba2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -442,8 +442,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &amdgpu_vce_free_job,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
--        r = amdgpu_ib_schedule(ring, 1, ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
- 	if (r)
- 		goto err;
-        
-@@ -514,9 +513,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &f);
- 
-        if (direct) {
--                r = amdgpu_ib_schedule(ring, 1, ib,
--                                       AMDGPU_FENCE_OWNER_UNDEFINED,
--                                       NULL, &f);
-+                r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-                 if (r)
-                         goto err;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index f94d707..481f22b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -643,8 +643,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[3] = 1;
- 	ib.ptr[4] = 0xDEADBEEF;
- 	ib.length_dw = 5;
--        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index e1140a4..5e9af0b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2136,8 +2136,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- 	if (r)
- 		goto err2;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index fbe148d..d6d2453 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -706,8 +706,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- 	if (r)
- 		goto err2;
- 
-@@ -1262,8 +1261,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
- 
- 	/* shedule the ib on the ring */
--        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
- 		goto fail;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 602a467..4abfd11 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -701,8 +701,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index e56020e..9a51233 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -853,8 +853,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
--                               NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- 	if (r)
- 		goto err1;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0357-drm-amdgpu-add-slap-cache-for-sync-objects-as-well.patch b/common/recipes-kernel/linux/files/0357-drm-amdgpu-add-slap-cache-for-sync-objects-as-well.patch
deleted file mode 100644
index 21cbb42c..00000000
--- a/common/recipes-kernel/linux/files/0357-drm-amdgpu-add-slap-cache-for-sync-objects-as-well.patch
+++ /dev/null
@@ -1,131 +0,0 @@
-From 1f797846d6a6f5734d9cb105fcd5a0b6cc4b3fc8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 16 Feb 2016 11:24:58 +0100
-Subject: [PATCH 0357/1110] drm/amdgpu: add slap cache for sync objects as well
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We need them all the time.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 36 ++++++++++++++++++++++++++++----
- 3 files changed, 36 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 27b1dc3..866e790 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -594,6 +594,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
- struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
- int amdgpu_sync_wait(struct amdgpu_sync *sync);
- void amdgpu_sync_free(struct amdgpu_sync *sync);
-+int amdgpu_sync_init(void);
-+void amdgpu_sync_fini(void);
- 
- /*
-  * GART structures, functions & helpers
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index c1182ec..82cab2e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -547,6 +547,7 @@ static struct pci_driver amdgpu_kms_pci_driver = {
- 
- static int __init amdgpu_init(void)
- {
-+	amdgpu_sync_init();
- #ifdef CONFIG_VGA_CONSOLE
- 	if (vgacon_text_force()) {
- 		DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
-@@ -571,6 +572,7 @@ static void __exit amdgpu_exit(void)
- 	amdgpu_amdkfd_fini();
- 	drm_pci_exit(driver, pdriver);
- 	amdgpu_unregister_atpx_handler();
-+	amdgpu_sync_fini();
- }
- 
- module_init(amdgpu_init);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index e367342..c48b4fc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -37,6 +37,8 @@ struct amdgpu_sync_entry {
- 	struct fence		*fence;
- };
- 
-+static struct kmem_cache *amdgpu_sync_slab;
-+
- /**
-  * amdgpu_sync_create - zero init sync object
-  *
-@@ -133,7 +135,7 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- 		return 0;
- 	}
- 
--	e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
-+	e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
- 	if (!e)
- 		return -ENOMEM;
- 
-@@ -214,7 +216,7 @@ struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
- 		f = e->fence;
- 
- 		hash_del(&e->node);
--		kfree(e);
-+		kmem_cache_free(amdgpu_sync_slab, e);
- 
- 		if (!fence_is_signaled(f))
- 			return f;
-@@ -237,7 +239,7 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
- 
- 		hash_del(&e->node);
- 		fence_put(e->fence);
--		kfree(e);
-+		kmem_cache_free(amdgpu_sync_slab, e);
- 	}
- 
- 	return 0;
-@@ -259,8 +261,34 @@ void amdgpu_sync_free(struct amdgpu_sync *sync)
- 	hash_for_each_safe(sync->fences, i, tmp, e, node) {
- 		hash_del(&e->node);
- 		fence_put(e->fence);
--		kfree(e);
-+		kmem_cache_free(amdgpu_sync_slab, e);
- 	}
- 
- 	fence_put(sync->last_vm_update);
- }
-+
-+/**
-+ * amdgpu_sync_init - init sync object subsystem
-+ *
-+ * Allocate the slab allocator.
-+ */
-+int amdgpu_sync_init(void)
-+{
-+	amdgpu_sync_slab = kmem_cache_create(
-+		"amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0,
-+		SLAB_HWCACHE_ALIGN, NULL);
-+	if (!amdgpu_sync_slab)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+/**
-+ * amdgpu_sync_fini - fini sync object subsystem
-+ *
-+ * Free the slab allocator.
-+ */
-+void amdgpu_sync_fini(void)
-+{
-+	kmem_cache_destroy(amdgpu_sync_slab);
-+}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0358-drm-amdgpu-return-the-common-fence-from-amdgpu_fence.patch b/common/recipes-kernel/linux/files/0358-drm-amdgpu-return-the-common-fence-from-amdgpu_fence.patch
deleted file mode 100644
index d5a0ad6b..00000000
--- a/common/recipes-kernel/linux/files/0358-drm-amdgpu-return-the-common-fence-from-amdgpu_fence.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From cee6a6cb58eba90c31ff50a76186c941085a164d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 16 Feb 2016 17:39:39 +0100
-Subject: [PATCH 0358/1110] drm/amdgpu: return the common fence from
- amdgpu_fence_emit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Try to avoid using the hardware specific fences even more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 27 ++++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c    |  7 ++++---
- 3 files changed, 20 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 866e790..b649a8f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -390,7 +390,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
- 				   unsigned irq_type);
- void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
- void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
--int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence **fence);
-+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
- void amdgpu_fence_process(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
-@@ -726,7 +726,7 @@ struct amdgpu_ib {
- 	uint32_t			length_dw;
- 	uint64_t			gpu_addr;
- 	uint32_t			*ptr;
--	struct amdgpu_fence		*fence;
-+        struct fence                    *fence;
- 	struct amdgpu_user_fence        *user;
- 	struct amdgpu_vm		*vm;
-         unsigned                        vm_id;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index d94b13a..83599f2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -91,28 +91,29 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
-  * amdgpu_fence_emit - emit a fence on the requested ring
-  *
-  * @ring: ring the fence is associated with
-- * @fence: amdgpu fence object
-+ * @f: resulting fence object
-  *
-  * Emits a fence command on the requested ring (all asics).
-  * Returns 0 on success, -ENOMEM on failure.
-  */
--int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence **fence)
-+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- {
- 	struct amdgpu_device *adev = ring->adev;
-+	struct amdgpu_fence *fence;
- 
--	*fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
--	if ((*fence) == NULL) {
-+	fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
-+	if (fence == NULL)
- 		return -ENOMEM;
--	}
--	(*fence)->seq = ++ring->fence_drv.sync_seq;
--	(*fence)->ring = ring;
--	fence_init(&(*fence)->base, &amdgpu_fence_ops,
--		&ring->fence_drv.fence_queue.lock,
--		adev->fence_context + ring->idx,
--		(*fence)->seq);
-+
-+	fence->seq = ++ring->fence_drv.sync_seq;
-+	fence->ring = ring;
-+	fence_init(&fence->base, &amdgpu_fence_ops,
-+		   &ring->fence_drv.fence_queue.lock,
-+		   adev->fence_context + ring->idx,
-+		   fence->seq);
- 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
--			       (*fence)->seq,
--			       AMDGPU_FENCE_FLAG_INT);
-+			       fence->seq, AMDGPU_FENCE_FLAG_INT);
-+	*f = &fence->base;
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index dc5683c..4d7b80b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -90,9 +90,8 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-  */
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
- {
--	amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base);
--	if (ib->fence)
--		fence_put(&ib->fence->base);
-+	amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence);
-+	fence_put(ib->fence);
- }
- 
- /**
-@@ -196,6 +195,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
- 
-+        *f = fence_get(ib->fence);	
-+
- 	amdgpu_ring_commit(ring);
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0359-drm-amdgpu-move-the-GDS-switch-into-vm-flush-as-well.patch b/common/recipes-kernel/linux/files/0359-drm-amdgpu-move-the-GDS-switch-into-vm-flush-as-well.patch
deleted file mode 100644
index d72ed0a0..00000000
--- a/common/recipes-kernel/linux/files/0359-drm-amdgpu-move-the-GDS-switch-into-vm-flush-as-well.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From c2c4bf56c642027f4ee4322eead0dd71739f826f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 1 Mar 2016 13:34:49 +0100
-Subject: [PATCH 0359/1110] drm/amdgpu: move the GDS switch into vm flush as
- well
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-After all it's an operation on the VMID.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  6 ++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 11 ++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +++++++++++++-----
- 3 files changed, 21 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index b649a8f..394122e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -923,8 +923,10 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
-                       struct amdgpu_sync *sync, struct fence *fence,
-                       unsigned *vm_id, uint64_t *vm_pd_addr);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
--                     unsigned vmid,
--                     uint64_t pd_addr);
-+                     unsigned vm_id, uint64_t pd_addr,
-+                     uint32_t gds_base, uint32_t gds_size,
-+                     uint32_t gws_base, uint32_t gws_size,
-+                     uint32_t oa_base, uint32_t oa_size);
- uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 4d7b80b..4aedfe4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -149,13 +149,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 
- 	if (vm) {
- 		/* do context switch */
--                amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr);
--
--		if (ring->funcs->emit_gds_switch)
--                        amdgpu_ring_emit_gds_switch(ring, ib->vm_id,
--						    ib->gds_base, ib->gds_size,
--						    ib->gws_base, ib->gws_size,
--						    ib->oa_base, ib->oa_size);
-+                amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
-+                                ib->gds_base, ib->gds_size,
-+                                ib->gws_base, ib->gws_size,
-+                                ib->oa_base, ib->oa_size);
- 
- 		if (ring->funcs->emit_hdp_flush)
- 			amdgpu_ring_emit_hdp_flush(ring);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 6e23841..3e1c8cf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -248,19 +248,27 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
-  * amdgpu_vm_flush - hardware flush the vm
-  *
-  * @ring: ring to use for flush
-- * @vmid: vmid number to use
-+ * @vm_id: vmid number to use
-  * @pd_addr: address of the page directory
-  *
-  * Emit a VM flush when it is necessary.
-  */
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
--		     unsigned vmid,
--		     uint64_t pd_addr)
-+		     unsigned vm_id, uint64_t pd_addr,
-+		     uint32_t gds_base, uint32_t gds_size,
-+		     uint32_t gws_base, uint32_t gws_size,
-+		     uint32_t oa_base, uint32_t oa_size)
- {
- 	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
--		trace_amdgpu_vm_flush(pd_addr, ring->idx, vmid);
--		amdgpu_ring_emit_vm_flush(ring, vmid, pd_addr);
-+		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
-+		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
- 	}
-+
-+	if (ring->funcs->emit_gds_switch)
-+		amdgpu_ring_emit_gds_switch(ring, vm_id,
-+					    gds_base, gds_size,
-+					    gws_base, gws_size,
-+					    oa_base, oa_size);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch b/common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch
deleted file mode 100644
index 38a34a1e..00000000
--- a/common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch
+++ /dev/null
@@ -1,148 +0,0 @@
-From dec35381ca2378fe439abde710d26a641683e63b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 1 Mar 2016 15:09:25 +0100
-Subject: [PATCH 0360/1110] drm/amdgpu: switch the GDS only on demand v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Switching the GDS space to often seems to be problematic.
-
-This patch together with the following can avoid VM faults on context switch.
-
-v2: extend commit message a bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  8 ++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c |  4 +++
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 +++++++++++++++++++++++++++++++---
- 3 files changed, 54 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 394122e..a1a10fa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -881,6 +881,13 @@ struct amdgpu_vm_manager_id {
- 	struct list_head	list;
- 	struct fence		*active;
- 	atomic_long_t		owner;
-+ 
-+        uint32_t                gds_base;
-+        uint32_t                gds_size;
-+        uint32_t                gws_base;
-+        uint32_t                gws_size;
-+        uint32_t                oa_base;
-+        uint32_t                oa_size;
- };
- 
- struct amdgpu_vm_manager {
-@@ -927,6 +934,7 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
-                      uint32_t gds_base, uint32_t gds_size,
-                      uint32_t gws_base, uint32_t gws_size,
-                      uint32_t oa_base, uint32_t oa_size);
-+void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
- uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 4aedfe4..ddaffa4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -164,6 +164,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 
-                 if (ib->ctx != ctx || ib->vm != vm) {
- 			ring->current_ctx = old_ctx;
-+			if (ib->vm_id)
-+				amdgpu_vm_reset_id(adev, ib->vm_id);
- 			amdgpu_ring_undo(ring);
- 			return -EINVAL;
- 		}
-@@ -180,6 +182,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
- 		ring->current_ctx = old_ctx;
-+		if (ib->vm_id)
-+			amdgpu_vm_reset_id(adev, ib->vm_id);
- 		amdgpu_ring_undo(ring);
- 		return r;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 3e1c8cf..abf0d44 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -259,16 +259,53 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 		     uint32_t gws_base, uint32_t gws_size,
- 		     uint32_t oa_base, uint32_t oa_size)
- {
-+        struct amdgpu_device *adev = ring->adev;
-+        struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id];
-+
- 	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
- 		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
- 	}
- 
--	if (ring->funcs->emit_gds_switch)
--		amdgpu_ring_emit_gds_switch(ring, vm_id,
-+        if (ring->funcs->emit_gds_switch && (
-+           mgr_id->gds_base != gds_base ||
-+           mgr_id->gds_size != gds_size ||
-+           mgr_id->gws_base != gws_base ||
-+           mgr_id->gws_size != gws_size ||
-+           mgr_id->oa_base != oa_base ||
-+           mgr_id->oa_size != oa_size)) {
-+
-+               mgr_id->gds_base = gds_base;
-+               mgr_id->gds_size = gds_size;
-+               mgr_id->gws_base = gws_base;
-+               mgr_id->gws_size = gws_size;
-+               mgr_id->oa_base = oa_base;
-+               mgr_id->oa_size = oa_size;
-+	       amdgpu_ring_emit_gds_switch(ring, vm_id,
- 					    gds_base, gds_size,
- 					    gws_base, gws_size,
- 					    oa_base, oa_size);
-+	}
-+}
-+
-+/**
-+ * amdgpu_vm_reset_id - reset VMID to zero
-+ *
-+ * @adev: amdgpu device structure
-+ * @vm_id: vmid number to use
-+ *
-+ * Reset saved GDW, GWS and OA to force switch on next flush.
-+ */
-+void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
-+{
-+       struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id];
-+
-+       mgr_id->gds_base = 0;
-+       mgr_id->gds_size = 0;
-+       mgr_id->gws_base = 0;
-+       mgr_id->gws_size = 0;
-+       mgr_id->oa_base = 0;
-+       mgr_id->oa_size = 0;
- }
- 
- /**
-@@ -1429,9 +1466,11 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 	INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
- 
- 	/* skip over VMID 0, since it is the system VM */
--	for (i = 1; i < adev->vm_manager.num_ids; ++i)
-+        for (i = 1; i < adev->vm_manager.num_ids; ++i) {
-+                 amdgpu_vm_reset_id(adev, i);
- 		list_add_tail(&adev->vm_manager.ids[i].list,
- 			      &adev->vm_manager.ids_lru);
-+        }
- 
-         atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch b/common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch
deleted file mode 100644
index b0c4797f..00000000
--- a/common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-From cf95fdb7c71fe682fe165553dc210d04889bcdc8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 15 Apr 2016 16:45:49 -0400
-Subject: [PATCH 0361/1110] drm/amdgpu: split pipeline sync and vm flush
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows us to use the pipeline sync for other tasks as well.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  2 ++
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 30 ++++++++++++++++++++++--------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 11 +++++++++--
- 4 files changed, 35 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a1a10fa..0bc033e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -287,6 +287,7 @@ struct amdgpu_ring_funcs {
- 			struct amdgpu_ib *ib);
- 	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
- 			   uint64_t seq, unsigned flags);
-+	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
- 	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
- 			      uint64_t pd_addr);
- 	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
-@@ -2198,6 +2199,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
- #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
- #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
-+#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
- #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
- #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
- #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index abf0d44..25469bf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -264,6 +264,8 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 
- 	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
-+		if (ring->funcs->emit_pipeline_sync)
-+			amdgpu_ring_emit_pipeline_sync(ring);
- 		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 5e9af0b..87d439a 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -3041,6 +3041,26 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
- 	return 0;
- }
- 
-+/**
-+ * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
-+ *
-+ * @ring: the ring to emmit the commands to
-+ *
-+ * Sync the command pipeline with the PFP. E.g. wait for everything
-+ * to be completed.
-+ */
-+static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
-+{
-+	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
-+	if (usepfp) {
-+		/* synce CE with ME to prevent CE fetch CEIB before context switch done */
-+		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
-+		amdgpu_ring_write(ring, 0);
-+		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
-+		amdgpu_ring_write(ring, 0);
-+	}
-+}
-+
- /*
-  * vm
-  * VMID 0 is the physical GPU addresses as used by the kernel.
-@@ -3072,14 +3092,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, 0xffffffff);
- 	amdgpu_ring_write(ring, 4); /* poll interval */
- 
--	if (usepfp) {
--		/* synce CE with ME to prevent CE fetch CEIB before context switch done */
--		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
--		amdgpu_ring_write(ring, 0);
--		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
--		amdgpu_ring_write(ring, 0);
--	}
--
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
- 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
- 				 WRITE_DATA_DST_SEL(0)));
-@@ -5160,6 +5172,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
- 	.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
-+	.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-@@ -5177,6 +5190,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v7_0_ring_emit_ib_compute,
- 	.emit_fence = gfx_v7_0_ring_emit_fence_compute,
-+	.emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
- 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d6d2453..56dd745 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4692,8 +4692,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
- 
- }
- 
--static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
--					unsigned vm_id, uint64_t pd_addr)
-+static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
- {
- 	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
- 	uint32_t seq = ring->fence_drv.sync_seq;
-@@ -4716,6 +4715,12 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
- 		amdgpu_ring_write(ring, 0);
- 	}
-+}
-+
-+static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-+					unsigned vm_id, uint64_t pd_addr)
-+{
-+	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
- 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-@@ -5038,6 +5043,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
- 	.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
-+	.emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-@@ -5055,6 +5061,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
- 	.parse_cs = NULL,
- 	.emit_ib = gfx_v8_0_ring_emit_ib_compute,
- 	.emit_fence = gfx_v8_0_ring_emit_fence_compute,
-+	.emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
- 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
- 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
- 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch b/common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch
deleted file mode 100644
index 27394a5e..00000000
--- a/common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From e4c5273b33bfe7303ea03aa50f9fad2b3ef32980 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 1 Mar 2016 15:51:53 +0100
-Subject: [PATCH 0362/1110] drm/amdgpu: if a GDS switch is needed emit a
- pipeline sync as well
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Otherwise we might change the GDS settings while they are still in use.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 ++++++++++++----------
- 1 file changed, 12 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 25469bf..f139cea 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -261,22 +261,24 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- {
-         struct amdgpu_device *adev = ring->adev;
-         struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id];
-+        bool gds_switch_needed = ring->funcs->emit_gds_switch && (
-+               mgr_id->gds_base != gds_base ||
-+               mgr_id->gds_size != gds_size ||
-+               mgr_id->gws_base != gws_base ||
-+               mgr_id->gws_size != gws_size ||
-+               mgr_id->oa_base != oa_base ||
-+               mgr_id->oa_size != oa_size);
-+
-+        if (ring->funcs->emit_pipeline_sync && (
-+           pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed))
-+               amdgpu_ring_emit_pipeline_sync(ring);
- 
- 	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
--		if (ring->funcs->emit_pipeline_sync)
--			amdgpu_ring_emit_pipeline_sync(ring);
- 		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
- 	}
- 
--        if (ring->funcs->emit_gds_switch && (
--           mgr_id->gds_base != gds_base ||
--           mgr_id->gds_size != gds_size ||
--           mgr_id->gws_base != gws_base ||
--           mgr_id->gws_size != gws_size ||
--           mgr_id->oa_base != oa_base ||
--           mgr_id->oa_size != oa_size)) {
--
-+        if (gds_switch_needed) {
-                mgr_id->gds_base = gds_base;
-                mgr_id->gds_size = gds_size;
-                mgr_id->gws_base = gws_base;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0363-drm-amdgpu-move-get_user_pages-out-of-amdgpu_ttm_tt_.patch b/common/recipes-kernel/linux/files/0363-drm-amdgpu-move-get_user_pages-out-of-amdgpu_ttm_tt_.patch
deleted file mode 100644
index 7e2976f9..00000000
--- a/common/recipes-kernel/linux/files/0363-drm-amdgpu-move-get_user_pages-out-of-amdgpu_ttm_tt_.patch
+++ /dev/null
@@ -1,447 +0,0 @@
-From 20b395a08bdc56f0bb9e34d3840718583159352b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 23 Feb 2016 12:36:59 +0100
-Subject: [PATCH 0363/1110] drm/amdgpu: move get_user_pages out of
- amdgpu_ttm_tt_pin_userptr v6
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-That avoids lock inversion between the BO reservation lock
-and the anon_vma lock.
-
-v2:
-* Changed amdgpu_bo_list_entry.user_pages to an array of pointers
-* Lock mmap_sem only for get_user_pages
-* Added invalidation of unbound userpointer BOs
-* Fixed memory leak and page reference leak
-
-v3 (chk):
-* Revert locking mmap_sem only for_get user_pages
-* Revert adding invalidation of unbound userpointer BOs
-* Sanitize and fix error handling
-
-v4 (chk):
-* Init userpages pointer everywhere.
-* Fix error handling when get_user_pages() fails.
-* Add invalidation of unbound userpointer BOs again.
-
-v5 (chk):
-* Add maximum number of tries.
-
-v6 (chk):
-* Fix error handling when we run out of tries.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v4)
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h         |   5 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c |   1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c      | 118 ++++++++++++++++++++++++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c     |  23 ++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c     |  53 +++++++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c      |   2 +
- 6 files changed, 176 insertions(+), 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0bc033e..66aef04 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -432,6 +432,8 @@ struct amdgpu_bo_list_entry {
- 	struct ttm_validate_buffer	tv;
- 	struct amdgpu_bo_va		*bo_va;
- 	uint32_t			priority;
-+	struct page			**user_pages;
-+	int				user_invalidated;
- };
- 
- struct amdgpu_bo_va_mapping {
-@@ -2329,11 +2331,14 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
- 		       struct amdgpu_ring **out_ring);
- void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
- bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
-+int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
- int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
- 				     uint32_t flags);
- struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
- bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
- 				  unsigned long end);
-+bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
-+				       int *last_invalidated);
- bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
- uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
- 				 struct ttm_mem_reg *mem);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index 82f8caf..17a2f83 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -201,6 +201,7 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
- 
- 		list_add_tail(&list->array[i].tv.head,
- 			      &bucket[priority]);
-+		list->array[i].user_pages = NULL;
- 	}
- 
- 	/* Connect the sorted buckets in the output list. */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index a92a30a..62027c6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -152,6 +152,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 	p->uf_entry.priority = 0;
- 	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
- 	p->uf_entry.tv.shared = true;
-+        p->uf_entry.user_pages = NULL;
- 
- 	drm_gem_object_unreference_unlocked(gobj);
- 	return 0;
-@@ -344,6 +345,7 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 
- 	list_for_each_entry(lobj, validated, tv.head) {
-                 struct amdgpu_bo *bo = lobj->robj;
-+                bool binding_userptr = false;
-                 struct mm_struct *usermm;
-                 uint32_t domain;
- 
-@@ -351,6 +353,15 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
-                 if (usermm && usermm != current->mm)
-                         return -EPERM;
- 
-+               /* Check if we have user pages and nobody bound the BO already */
-+                if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
-+                       size_t size = sizeof(struct page *);
-+
-+                       size *= bo->tbo.ttm->num_pages;
-+                       memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
-+                       binding_userptr = true;
-+               }
-+
-                 if (bo->pin_count)
-                         continue;
- 
-@@ -382,6 +393,11 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 			}
- 			return r;
- 		}
-+
-+               if (binding_userptr) {
-+                       drm_free_large(lobj->user_pages);
-+                       lobj->user_pages = NULL;
-+                }
- 	}
- 	return 0;
- }
-@@ -389,8 +405,10 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- {
-         struct amdgpu_cs_buckets buckets;
-+        struct amdgpu_bo_list_entry *e;
- 	struct list_head duplicates;
- 	bool need_mmap_lock = false;
-+        unsigned i, tries = 10;
- 
- 	int i, r;
- 	
-@@ -413,9 +431,81 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- 	if (need_mmap_lock)
- 		down_read(&current->mm->mmap_sem);
- 
--	r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
--	if (unlikely(r != 0))
--		goto error_reserve;
-+        while (1) {
-+                struct list_head need_pages;
-+                unsigned i;
-+
-+                r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
-+                                           &duplicates);
-+                if (unlikely(r != 0))
-+                        goto error_free_pages;
-+ 
-+                /* Without a BO list we don't have userptr BOs */
-+                if (!p->bo_list)
-+                        break;
-+ 
-+                INIT_LIST_HEAD(&need_pages);
-+                for (i = p->bo_list->first_userptr;
-+                     i < p->bo_list->num_entries; ++i) {
-+ 
-+                        e = &p->bo_list->array[i];
-+ 
-+                        if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
-+                                 &e->user_invalidated) && e->user_pages) {
-+ 
-+                                /* We acquired a page array, but somebody
-+                                * invalidated it. Free it an try again
-+                                */
-+                                release_pages(e->user_pages,
-+                                             e->robj->tbo.ttm->num_pages,
-+                                             false);
-+                               drm_free_large(e->user_pages);
-+                               e->user_pages = NULL;
-+                       }
-+
-+                       if (e->robj->tbo.ttm->state != tt_bound &&
-+                           !e->user_pages) {
-+                               list_del(&e->tv.head);
-+                               list_add(&e->tv.head, &need_pages);
-+
-+                               amdgpu_bo_unreserve(e->robj);
-+                       }
-+               }
-+
-+                if (list_empty(&need_pages))
-+                       break;
-+ 
-+               /* Unreserve everything again. */
-+                ttm_eu_backoff_reservation(&p->ticket, &p->validated);
-+
-+               /* We tried to often, just abort */
-+                if (!--tries) {
-+                       r = -EDEADLK;
-+                        goto error_free_pages;
-+                }
-+ 
-+                /* Fill the page arrays for all useptrs. */
-+                list_for_each_entry(e, &need_pages, tv.head) {
-+                        struct ttm_tt *ttm = e->robj->tbo.ttm;
-+ 
-+                        e->user_pages = drm_calloc_large(ttm->num_pages,
-+                                                         sizeof(struct page*));
-+                        if (!e->user_pages) {
-+                                r = -ENOMEM;
-+                                goto error_free_pages;
-+                        }
-+ 
-+                        r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
-+                        if (r) {
-+                                drm_free_large(e->user_pages);
-+                                e->user_pages = NULL;
-+                                goto error_free_pages;
-+                        }
-+                }
-+ 
-+                /* And try again. */
-+                list_splice(&need_pages, &p->validated);
-+        }
- 
-         amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
- 
-@@ -445,9 +535,25 @@ error_validate:
- 	if (r)
- 		ttm_eu_backoff_reservation(&p->ticket, &p->validated);
- 
--error_reserve:
--	if (need_mmap_lock)
--		up_read(&current->mm->mmap_sem);
-+error_free_pages:
-+
-+        if (need_mmap_lock)
-+                up_read(&current->mm->mmap_sem);
-+
-+       if (p->bo_list) {
-+                for (i = p->bo_list->first_userptr;
-+                     i < p->bo_list->num_entries; ++i) {
-+                        e = &p->bo_list->array[i];
-+ 
-+                        if (!e->user_pages)
-+                                continue;
-+ 
-+                        release_pages(e->user_pages,
-+                                      e->robj->tbo.ttm->num_pages,
-+                                      false);
-+                        drm_free_large(e->user_pages);
-+                }
-+        }
- 
- 	return r;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 6270a20..cbacf72 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -274,18 +274,23 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
- 
- 	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
- 		down_read(&current->mm->mmap_sem);
-+
-+		r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
-+						 bo->tbo.ttm->pages);
-+		if (r)
-+			goto unlock_mmap_sem;
-+
- 		r = amdgpu_bo_reserve(bo, true);
--		if (r) {
--			up_read(&current->mm->mmap_sem);
--			goto release_object;
--		}
-+		if (r)
-+			goto free_pages;
- 
- 		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
- 		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
- 		amdgpu_bo_unreserve(bo);
--		up_read(&current->mm->mmap_sem);
- 		if (r)
--			goto release_object;
-+			goto free_pages;
-+
-+		up_read(&current->mm->mmap_sem);
- 	}
- 
- 	r = drm_gem_handle_create(filp, gobj, &handle);
-@@ -297,6 +302,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
- 	args->handle = handle;
- 	return 0;
- 
-+free_pages:
-+	release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
-+
-+unlock_mmap_sem:
-+	up_read(&current->mm->mmap_sem);
-+
- release_object:
- 	drm_gem_object_unreference_unlocked(gobj);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 051cd39..6bbd395 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -508,22 +508,18 @@ struct amdgpu_ttm_tt {
- 	uint32_t		userflags;
- 	spinlock_t              guptasklock;
- 	struct list_head        guptasks;
-+	atomic_t		mmu_invalidations;
- };
- 
--/* prepare the sg table with the user pages */
--static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
-+int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
- {
--	struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
--	unsigned pinned = 0, nents;
--	int r;
--
- 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
--	enum dma_data_direction direction = write ?
--		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
-+	unsigned pinned = 0;
-+	int r;
- 
- 	if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
--		/* check that we only pin down anonymous memory
-+		/* check that we only use anonymous memory
- 		   to prevent problems with writeback */
- 		unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
- 		struct vm_area_struct *vma;
-@@ -536,7 +532,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
- 	do {
- 		unsigned num_pages = ttm->num_pages - pinned;
- 		uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
--		struct page **pages = ttm->pages + pinned;
-+		struct page **p = pages + pinned;
- 		struct amdgpu_ttm_gup_task_list guptask;
- 
- 		guptask.task = current;
-@@ -545,7 +541,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
- 		spin_unlock(&gtt->guptasklock);
- 
- 		r = get_user_pages(current, current->mm, userptr, num_pages,
--				   write, 0, pages, NULL);
-+				   write, 0, p, NULL);
- 
- 		spin_lock(&gtt->guptasklock);
- 		list_del(&guptask.list);
-@@ -558,6 +554,25 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
- 
- 	} while (pinned < ttm->num_pages);
- 
-+	return 0;
-+
-+release_pages:
-+	release_pages(pages, pinned, 0);
-+	return r;
-+}
-+
-+/* prepare the sg table with the user pages */
-+static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
-+{
-+	struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
-+	struct amdgpu_ttm_tt *gtt = (void *)ttm;
-+	unsigned nents;
-+	int r;
-+
-+	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
-+	enum dma_data_direction direction = write ?
-+		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
-+
- 	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
- 				      ttm->num_pages << PAGE_SHIFT,
- 				      GFP_KERNEL);
-@@ -576,9 +591,6 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
- 
- release_sg:
- 	kfree(ttm->sg);
--
--release_pages:
--	release_pages(ttm->pages, pinned, 0);
- 	return r;
- }
- 
-@@ -803,6 +815,7 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
- 	gtt->userflags = flags;
- 	spin_lock_init(&gtt->guptasklock);
- 	INIT_LIST_HEAD(&gtt->guptasks);
-+	atomic_set(&gtt->mmu_invalidations, 0);
- 
- 	return 0;
- }
-@@ -840,9 +853,21 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
- 	}
- 	spin_unlock(&gtt->guptasklock);
- 
-+	atomic_inc(&gtt->mmu_invalidations);
-+
- 	return true;
- }
- 
-+bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
-+				       int *last_invalidated)
-+{
-+	struct amdgpu_ttm_tt *gtt = (void *)ttm;
-+	int prev_invalidated = *last_invalidated;
-+
-+	*last_invalidated = atomic_read(&gtt->mmu_invalidations);
-+	return prev_invalidated != *last_invalidated;
-+}
-+
- bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
- {
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index f139cea..99afc64 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -94,6 +94,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-         entry->priority = 0;
-         entry->tv.bo = &vm->page_directory->tbo;
-         entry->tv.shared = true;
-+        entry->user_pages = NULL;
-         list_add(&entry->tv.head, validated);
- }
- 
-@@ -1191,6 +1192,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
-                 entry->priority = 0;
-                 entry->tv.bo = &entry->robj->tbo;
-                 entry->tv.shared = true;
-+                entry->user_pages = NULL;
- 		vm->page_tables[pt_idx].addr = 0;
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0364-drm-amd-amdgpu-Don-t-proceed-in-audio_fini-in-DCEv11.patch b/common/recipes-kernel/linux/files/0364-drm-amd-amdgpu-Don-t-proceed-in-audio_fini-in-DCEv11.patch
deleted file mode 100644
index 158a7494..00000000
--- a/common/recipes-kernel/linux/files/0364-drm-amd-amdgpu-Don-t-proceed-in-audio_fini-in-DCEv11.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From de73a4e5e473d93bbfe7ffe94af997e79035a800 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 2 Mar 2016 08:58:07 -0500
-Subject: [PATCH 0364/1110] drm/amd/amdgpu: Don't proceed in audio_fini in
- DCEv11 if disabled
-
-If amdgpu_audio is disabled then the audio structure is not initialized
-so we shouldn't read it in the fini function.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 41e94d4..9c1d120 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -1658,6 +1658,9 @@ static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
- {
- 	int i;
- 
-+	if (!amdgpu_audio)
-+		return;
-+
- 	if (!adev->mode_info.audio.enabled)
- 		return;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0365-drm-amd-amdgpu-Whitespace-typo-fix-in-sw_init-DCEv11.patch b/common/recipes-kernel/linux/files/0365-drm-amd-amdgpu-Whitespace-typo-fix-in-sw_init-DCEv11.patch
deleted file mode 100644
index ad3835b7..00000000
--- a/common/recipes-kernel/linux/files/0365-drm-amd-amdgpu-Whitespace-typo-fix-in-sw_init-DCEv11.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From f49534290a39ffc5188005854258d4808af903ff Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 2 Mar 2016 09:10:50 -0500
-Subject: [PATCH 0365/1110] drm/amd/amdgpu: Whitespace typo fix in sw_init
- (DCEv11)
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 9c1d120..1b8abaf 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2964,7 +2964,7 @@ static int dce_v11_0_sw_init(void *handle)
- 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
- 		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
- 		if (r)
--		return r;
-+			return r;
- 	}
- 
- 	for (i = 8; i < 20; i += 2) {
-@@ -2976,7 +2976,7 @@ static int dce_v11_0_sw_init(void *handle)
- 	/* HPD hotplug */
- 	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
- 	if (r)
--	return r;
-+		return r;
- 
- 	adev->mode_info.mode_config_initialized = true;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0366-drm-amd-amdgpu-Move-init-flag-to-after-init-in-sw_in.patch b/common/recipes-kernel/linux/files/0366-drm-amd-amdgpu-Move-init-flag-to-after-init-in-sw_in.patch
deleted file mode 100644
index 06d84a6f..00000000
--- a/common/recipes-kernel/linux/files/0366-drm-amd-amdgpu-Move-init-flag-to-after-init-in-sw_in.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 6ef6c6089087a13e22e1ec2c3bdaa539ec4e3dc2 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 2 Mar 2016 09:14:40 -0500
-Subject: [PATCH 0366/1110] drm/amd/amdgpu: Move init flag to after init in
- sw_init() (DCEv11)
-
-Don't set config_init to true until all config statements pass.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 1b8abaf..c510226 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2978,8 +2978,6 @@ static int dce_v11_0_sw_init(void *handle)
- 	if (r)
- 		return r;
- 
--	adev->mode_info.mode_config_initialized = true;
--
- 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
- 
- 	adev->ddev->mode_config.max_width = 16384;
-@@ -2997,6 +2995,7 @@ static int dce_v11_0_sw_init(void *handle)
- 	adev->ddev->mode_config.max_width = 16384;
- 	adev->ddev->mode_config.max_height = 16384;
- 
-+
- 	/* allocate crtcs */
- 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
- 		r = dce_v11_0_crtc_init(adev, i);
-@@ -3018,7 +3017,8 @@ static int dce_v11_0_sw_init(void *handle)
- 
- 	drm_kms_helper_poll_init(adev->ddev);
- 
--	return r;
-+	adev->mode_info.mode_config_initialized = true;
-+	return 0;
- }
- 
- static int dce_v11_0_sw_fini(void *handle)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0367-drm-amd-amdgpu-Make-afmt_init-cleanup-if-alloc-fails.patch b/common/recipes-kernel/linux/files/0367-drm-amd-amdgpu-Make-afmt_init-cleanup-if-alloc-fails.patch
deleted file mode 100644
index 43757c66..00000000
--- a/common/recipes-kernel/linux/files/0367-drm-amd-amdgpu-Make-afmt_init-cleanup-if-alloc-fails.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 2abc52d6d911ec52da9b7d50f7ef09ef63854a08 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 2 Mar 2016 09:19:57 -0500
-Subject: [PATCH 0367/1110] drm/amd/amdgpu: Make afmt_init() cleanup if alloc
- fails (DCEv11)
-
-Updated DCEv11 afmt_init to cleanup if any kzalloc
-fails and then return an error code.  Don't continue initializing
-the audio stack in that case.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index c510226..f078171 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -1966,7 +1966,7 @@ static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
- 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
- }
- 
--static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
-+static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
- {
- 	int i;
- 
-@@ -1979,8 +1979,16 @@ static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
- 		if (adev->mode_info.afmt[i]) {
- 			adev->mode_info.afmt[i]->offset = dig_offsets[i];
- 			adev->mode_info.afmt[i]->id = i;
-+		} else {
-+			int j;
-+			for (j = 0; j < i; j++) {
-+				kfree(adev->mode_info.afmt[j]);
-+				adev->mode_info.afmt[j] = NULL;
-+			}
-+			return -ENOMEM;
- 		}
- 	}
-+	return 0;
- }
- 
- static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
-@@ -3009,7 +3017,9 @@ static int dce_v11_0_sw_init(void *handle)
- 		return -EINVAL;
- 
- 	/* setup afmt */
--	dce_v11_0_afmt_init(adev);
-+	r = dce_v11_0_afmt_init(adev);
-+	if (r)
-+		return r;
- 
- 	r = dce_v11_0_audio_init(adev);
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0368-drm-amd-amdgpu-Fix-indentation-in-dce_v11_0_crtc_do_.patch b/common/recipes-kernel/linux/files/0368-drm-amd-amdgpu-Fix-indentation-in-dce_v11_0_crtc_do_.patch
deleted file mode 100644
index 51df5b45..00000000
--- a/common/recipes-kernel/linux/files/0368-drm-amd-amdgpu-Fix-indentation-in-dce_v11_0_crtc_do_.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 41544fcdd019a12b3177577a0b36227e5f74a88a Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 2 Mar 2016 12:07:02 -0500
-Subject: [PATCH 0368/1110] drm/amd/amdgpu: Fix indentation in
- dce_v11_0_crtc_do_set_base()
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index f078171..ad43347 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2065,8 +2065,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
- 	if (atomic) {
- 		amdgpu_fb = to_amdgpu_framebuffer(fb);
- 		target_fb = fb;
--	}
--	else {
-+	} else {
- 		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
- 		target_fb = crtc->primary->fb;
- 	}
-@@ -2080,9 +2079,9 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
- 	if (unlikely(r != 0))
- 		return r;
- 
--	if (atomic)
-+	if (atomic) {
- 		fb_location = amdgpu_bo_gpu_offset(rbo);
--	else {
-+	} else {
- 		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
- 		if (unlikely(r != 0)) {
- 			amdgpu_bo_unreserve(rbo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0369-drm-amd-amdgpu-Don-t-proceed-in-audio_fini-if-disabl.patch b/common/recipes-kernel/linux/files/0369-drm-amd-amdgpu-Don-t-proceed-in-audio_fini-if-disabl.patch
deleted file mode 100644
index 15174eba..00000000
--- a/common/recipes-kernel/linux/files/0369-drm-amd-amdgpu-Don-t-proceed-in-audio_fini-if-disabl.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 1c4adba6f374086b39b7ea50cc789004d7b45446 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:20:10 -0500
-Subject: [PATCH 0369/1110] drm/amd/amdgpu: Don't proceed in audio_fini if
- disabled (DCEv10)
-
-If audio is disabled we shouldn't proceed into the fini function.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 25b4680..8dd1029 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -1668,6 +1668,9 @@ static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
- {
- 	int i;
- 
-+	if (!amdgpu_audio)
-+		return;
-+
- 	if (!adev->mode_info.audio.enabled)
- 		return;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0370-drm-amd-amdgpu-Move-initialized-flag-to-bottom-of-sw.patch b/common/recipes-kernel/linux/files/0370-drm-amd-amdgpu-Move-initialized-flag-to-bottom-of-sw.patch
deleted file mode 100644
index 45f151df..00000000
--- a/common/recipes-kernel/linux/files/0370-drm-amd-amdgpu-Move-initialized-flag-to-bottom-of-sw.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From ec10f34455d3290c15666bc37f23f14cf39cf7f2 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:21:44 -0500
-Subject: [PATCH 0370/1110] drm/amd/amdgpu: Move initialized flag to bottom of
- sw_init (DCEv10)
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 8dd1029..7f091e2 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -2983,8 +2983,6 @@ static int dce_v10_0_sw_init(void *handle)
- 	if (r)
- 		return r;
- 
--	adev->mode_info.mode_config_initialized = true;
--
- 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
- 
- 	adev->ddev->mode_config.max_width = 16384;
-@@ -3023,7 +3021,8 @@ static int dce_v10_0_sw_init(void *handle)
- 
- 	drm_kms_helper_poll_init(adev->ddev);
- 
--	return r;
-+	adev->mode_info.mode_config_initialized = true;
-+	return 0;
- }
- 
- static int dce_v10_0_sw_fini(void *handle)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0371-drm-amd-amdgpu-Make-afmt_init-cleanup-if-alloc-fails.patch b/common/recipes-kernel/linux/files/0371-drm-amd-amdgpu-Make-afmt_init-cleanup-if-alloc-fails.patch
deleted file mode 100644
index b084557c..00000000
--- a/common/recipes-kernel/linux/files/0371-drm-amd-amdgpu-Make-afmt_init-cleanup-if-alloc-fails.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 0f73ef78c9d7a9a7f138fbaf61e5073124bc8f6d Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:23:48 -0500
-Subject: [PATCH 0371/1110] drm/amd/amdgpu: Make afmt_init cleanup if alloc
- fails (DCEv10)
-
-Make the function free memory and return an error code if the allocation
-fails.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 7f091e2..8f2367a 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -1976,7 +1976,7 @@ static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
- 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
- }
- 
--static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
-+static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
- {
- 	int i;
- 
-@@ -1989,8 +1989,16 @@ static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
- 		if (adev->mode_info.afmt[i]) {
- 			adev->mode_info.afmt[i]->offset = dig_offsets[i];
- 			adev->mode_info.afmt[i]->id = i;
-+		} else {
-+			int j;
-+			for (j = 0; j < i; j++) {
-+				kfree(adev->mode_info.afmt[j]);
-+				adev->mode_info.afmt[j] = NULL;
-+			}
-+			return -ENOMEM;
- 		}
- 	}
-+	return 0;
- }
- 
- static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
-@@ -3013,7 +3021,9 @@ static int dce_v10_0_sw_init(void *handle)
- 		return -EINVAL;
- 
- 	/* setup afmt */
--	dce_v10_0_afmt_init(adev);
-+	r = dce_v10_0_afmt_init(adev);
-+	if (r)
-+		return r;
- 
- 	r = dce_v10_0_audio_init(adev);
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0372-drm-amd-amdgpu-Fix-identation-in-do_set_base-DCEv10.patch b/common/recipes-kernel/linux/files/0372-drm-amd-amdgpu-Fix-identation-in-do_set_base-DCEv10.patch
deleted file mode 100644
index 677ff6a8..00000000
--- a/common/recipes-kernel/linux/files/0372-drm-amd-amdgpu-Fix-identation-in-do_set_base-DCEv10.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 25330f5acca5946192e88115f73de4be8a37fd9b Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:25:05 -0500
-Subject: [PATCH 0372/1110] drm/amd/amdgpu: Fix identation in do_set_base()
- (DCEv10)
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 8f2367a..80261bc 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -2075,8 +2075,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
- 	if (atomic) {
- 		amdgpu_fb = to_amdgpu_framebuffer(fb);
- 		target_fb = fb;
--	}
--	else {
-+	} else {
- 		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
- 		target_fb = crtc->primary->fb;
- 	}
-@@ -2090,9 +2089,9 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
- 	if (unlikely(r != 0))
- 		return r;
- 
--	if (atomic)
-+	if (atomic) {
- 		fb_location = amdgpu_bo_gpu_offset(rbo);
--	else {
-+	} else {
- 		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
- 		if (unlikely(r != 0)) {
- 			amdgpu_bo_unreserve(rbo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0373-drm-amd-amdgpu-Don-t-proceed-into-audio_fini-if-audi.patch b/common/recipes-kernel/linux/files/0373-drm-amd-amdgpu-Don-t-proceed-into-audio_fini-if-audi.patch
deleted file mode 100644
index c4deb613..00000000
--- a/common/recipes-kernel/linux/files/0373-drm-amd-amdgpu-Don-t-proceed-into-audio_fini-if-audi.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 9970daea15792f772e8339d703cd6713ced0e344 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:31:49 -0500
-Subject: [PATCH 0373/1110] drm/amd/amdgpu: Don't proceed into audio_fini if
- audio is disabled (DCEv8)
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index a220711..4ce5f94 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -1639,6 +1639,9 @@ static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
- {
- 	int i;
- 
-+	if (!amdgpu_audio)
-+		return;
-+
- 	if (!adev->mode_info.audio.enabled)
- 		return;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0374-drm-amd-amdgpu-Move-config-init-flag-to-bottom-of-sw.patch b/common/recipes-kernel/linux/files/0374-drm-amd-amdgpu-Move-config-init-flag-to-bottom-of-sw.patch
deleted file mode 100644
index e013ab54..00000000
--- a/common/recipes-kernel/linux/files/0374-drm-amd-amdgpu-Move-config-init-flag-to-bottom-of-sw.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 27a2d3d66ecf6d0cce655432a4ebff1381362a33 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:42:43 -0500
-Subject: [PATCH 0374/1110] drm/amd/amdgpu: Move config init flag to bottom of
- sw_init (DCEv8)
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 4ce5f94..1a79062 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -2893,8 +2893,6 @@ static int dce_v8_0_sw_init(void *handle)
- 	if (r)
- 		return r;
- 
--	adev->mode_info.mode_config_initialized = true;
--
- 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
- 
- 	adev->ddev->mode_config.max_width = 16384;
-@@ -2933,7 +2931,8 @@ static int dce_v8_0_sw_init(void *handle)
- 
- 	drm_kms_helper_poll_init(adev->ddev);
- 
--	return r;
-+	adev->mode_info.mode_config_initialized = true;
-+	return 0;
- }
- 
- static int dce_v8_0_sw_fini(void *handle)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0375-drm-amd-amdgpu-make-afmt_init-cleanup-if-alloc-fails.patch b/common/recipes-kernel/linux/files/0375-drm-amd-amdgpu-make-afmt_init-cleanup-if-alloc-fails.patch
deleted file mode 100644
index 23dbc790..00000000
--- a/common/recipes-kernel/linux/files/0375-drm-amd-amdgpu-make-afmt_init-cleanup-if-alloc-fails.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From d7e10515e0b4c0437336165326cb788ad89aaea7 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:45:29 -0500
-Subject: [PATCH 0375/1110] drm/amd/amdgpu: make afmt_init cleanup if alloc
- fails (DCEv8)
-
-If the allocation fails free memory and return error code.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 1a79062..8af3596 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -1913,7 +1913,7 @@ static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
- 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
- }
- 
--static void dce_v8_0_afmt_init(struct amdgpu_device *adev)
-+static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
- {
- 	int i;
- 
-@@ -1926,8 +1926,16 @@ static void dce_v8_0_afmt_init(struct amdgpu_device *adev)
- 		if (adev->mode_info.afmt[i]) {
- 			adev->mode_info.afmt[i]->offset = dig_offsets[i];
- 			adev->mode_info.afmt[i]->id = i;
-+		} else {
-+			int j;
-+			for (j = 0; j < i; j++) {
-+				kfree(adev->mode_info.afmt[j]);
-+				adev->mode_info.afmt[j] = NULL;
-+			}
-+			return -ENOMEM;
- 		}
- 	}
-+	return 0;
- }
- 
- static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
-@@ -2923,7 +2931,9 @@ static int dce_v8_0_sw_init(void *handle)
- 		return -EINVAL;
- 
- 	/* setup afmt */
--	dce_v8_0_afmt_init(adev);
-+	r = dce_v8_0_afmt_init(adev);
-+	if (r)
-+		return r;
- 
- 	r = dce_v8_0_audio_init(adev);
- 	if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0376-drm-amd-amdgpu-Fix-indentation-in-do_set_base-DCEv8.patch b/common/recipes-kernel/linux/files/0376-drm-amd-amdgpu-Fix-indentation-in-do_set_base-DCEv8.patch
deleted file mode 100644
index 6f187239..00000000
--- a/common/recipes-kernel/linux/files/0376-drm-amd-amdgpu-Fix-indentation-in-do_set_base-DCEv8.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From b8865aa0153679f12e317b53209967c76deb8cdf Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Mar 2016 09:46:41 -0500
-Subject: [PATCH 0376/1110] drm/amd/amdgpu: Fix indentation in do_set_base()
- (DCEv8)
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 8af3596..b351e76 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -2012,8 +2012,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
- 	if (atomic) {
- 		amdgpu_fb = to_amdgpu_framebuffer(fb);
- 		target_fb = fb;
--	}
--	else {
-+	} else {
- 		amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
- 		target_fb = crtc->primary->fb;
- 	}
-@@ -2027,9 +2026,9 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
- 	if (unlikely(r != 0))
- 		return r;
- 
--	if (atomic)
-+	if (atomic) {
- 		fb_location = amdgpu_bo_gpu_offset(rbo);
--	else {
-+	} else {
- 		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
- 		if (unlikely(r != 0)) {
- 			amdgpu_bo_unreserve(rbo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0377-drm-amdgpu-Fix-two-bugs-in-amdgpu_vm_bo_split_mappin.patch b/common/recipes-kernel/linux/files/0377-drm-amdgpu-Fix-two-bugs-in-amdgpu_vm_bo_split_mappin.patch
deleted file mode 100644
index 2c06d178..00000000
--- a/common/recipes-kernel/linux/files/0377-drm-amdgpu-Fix-two-bugs-in-amdgpu_vm_bo_split_mappin.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 97066c93d6552e25e9bbe4dd501d348820d68c19 Mon Sep 17 00:00:00 2001
-From: Felix Kuehling <Felix.Kuehling@amd.com>
-Date: Thu, 3 Mar 2016 19:13:20 -0500
-Subject: [PATCH 0377/1110] drm/amdgpu: Fix two bugs in
- amdgpu_vm_bo_split_mapping
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Off-by-one: last is inclusive, so the maximum is start + max_size - 1
-Wrong unit: addr is in bytes, max_size is in pages
-
-Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 99afc64..a80de65 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -872,7 +872,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 	while (start != mapping->it.last + 1) {
- 		uint64_t last;
- 
--		last = min((uint64_t)mapping->it.last, start + max_size);
-+		last = min((uint64_t)mapping->it.last, start + max_size - 1);
- 		r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm,
- 						start, last, flags, addr,
- 						fence);
-@@ -880,7 +880,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 			return r;
- 
- 		start = last + 1;
--		addr += max_size;
-+		addr += max_size * AMDGPU_GPU_PAGE_SIZE;
- 	}
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0378-drm-amdgpu-reserve-the-PD-during-unmap-and-remove.patch b/common/recipes-kernel/linux/files/0378-drm-amdgpu-reserve-the-PD-during-unmap-and-remove.patch
deleted file mode 100644
index 28096794..00000000
--- a/common/recipes-kernel/linux/files/0378-drm-amdgpu-reserve-the-PD-during-unmap-and-remove.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 3f2874ebc604baada1c76eba598e27b6ec797903 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 8 Mar 2016 17:47:46 +0100
-Subject: [PATCH 0378/1110] drm/amdgpu: reserve the PD during unmap and remove
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We not only need to protect the mapping tree and freed list itself,
-but also the items on those list.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 34 +++++++++++++++++++++++----------
- 1 file changed, 24 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index cbacf72..dcf6611 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -140,25 +140,40 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
- void amdgpu_gem_object_close(struct drm_gem_object *obj,
- 			     struct drm_file *file_priv)
- {
--	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
--	struct amdgpu_device *adev = rbo->adev;
-+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
-+	struct amdgpu_device *adev = bo->adev;
- 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
- 	struct amdgpu_vm *vm = &fpriv->vm;
-+
-+	struct amdgpu_bo_list_entry vm_pd;
-+	struct list_head list, duplicates;
-+	struct ttm_validate_buffer tv;
-+	struct ww_acquire_ctx ticket;
- 	struct amdgpu_bo_va *bo_va;
- 	int r;
--	r = amdgpu_bo_reserve(rbo, true);
-+
-+	INIT_LIST_HEAD(&list);
-+	INIT_LIST_HEAD(&duplicates);
-+
-+	tv.bo = &bo->tbo;
-+	tv.shared = true;
-+	list_add(&tv.head, &list);
-+
-+	amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
-+
-+	r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
- 	if (r) {
- 		dev_err(adev->dev, "leaking bo va because "
- 			"we fail to reserve bo (%d)\n", r);
- 		return;
- 	}
--	bo_va = amdgpu_vm_bo_find(vm, rbo);
-+	bo_va = amdgpu_vm_bo_find(vm, bo);
- 	if (bo_va) {
- 		if (--bo_va->ref_count == 0) {
- 			amdgpu_vm_bo_rmv(adev, bo_va);
- 		}
- 	}
--	amdgpu_bo_unreserve(rbo);
-+	ttm_eu_backoff_reservation(&ticket, &list);
- }
- 
- static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
-@@ -580,11 +595,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
- 	tv.shared = true;
- 	list_add(&tv.head, &list);
- 
--	if (args->operation == AMDGPU_VA_OP_MAP) {
--		tv_pd.bo = &fpriv->vm.page_directory->tbo;
--		tv_pd.shared = true;
--		list_add(&tv_pd.head, &list);
--	}
-+	tv_pd.bo = &fpriv->vm.page_directory->tbo;
-+	tv_pd.shared = true;
-+	list_add(&tv_pd.head, &list);
-+
- 	r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
- 	if (r) {
- 		drm_gem_object_unreference_unlocked(gobj);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0379-drm-amdgpu-Revert-add-spin-lock-to-protect-freed-lis.patch b/common/recipes-kernel/linux/files/0379-drm-amdgpu-Revert-add-spin-lock-to-protect-freed-lis.patch
deleted file mode 100644
index 3d52ed29..00000000
--- a/common/recipes-kernel/linux/files/0379-drm-amdgpu-Revert-add-spin-lock-to-protect-freed-lis.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 60869b7c5d7aaa900e7f965b3e6da3dc512463fc Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 8 Mar 2016 17:52:01 +0100
-Subject: [PATCH 0379/1110] drm/amdgpu: Revert "add spin lock to protect freed
- list in vm (v3)"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not needed any more because we need to protect the elements on the list anyway.
-
-This reverts commit dae6ecf9e6c9b677e577826c3ac665c6dd9c490b.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 +++-------------
- 1 file changed, 3 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index a80de65..c6b890c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -976,22 +976,18 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
- 	struct amdgpu_bo_va_mapping *mapping;
- 	int r;
- 
--	spin_lock(&vm->freed_lock);
- 	while (!list_empty(&vm->freed)) {
- 		mapping = list_first_entry(&vm->freed,
- 			struct amdgpu_bo_va_mapping, list);
- 		list_del(&mapping->list);
--		spin_unlock(&vm->freed_lock);
-+
- 		r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping,
- 					       0, NULL);
- 		kfree(mapping);
- 		if (r)
- 			return r;
- 
--		spin_lock(&vm->freed_lock);
- 	}
--	spin_unlock(&vm->freed_lock);
--
- 	return 0;
- 
- }
-@@ -1257,13 +1253,10 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
- 	spin_unlock(&vm->it_lock);
- 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
- 
--	if (valid) {
--		spin_lock(&vm->freed_lock);
-+	if (valid)
- 		list_add(&mapping->list, &vm->freed);
--		spin_unlock(&vm->freed_lock);
--	} else {
-+	else
- 		kfree(mapping);
--	}
- 
- 	return 0;
- }
-@@ -1296,9 +1289,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
- 		interval_tree_remove(&mapping->it, &vm->va);
- 		spin_unlock(&vm->it_lock);
- 		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
--		spin_lock(&vm->freed_lock);
- 		list_add(&mapping->list, &vm->freed);
--		spin_unlock(&vm->freed_lock);
- 	}
- 	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
- 		list_del(&mapping->list);
-@@ -1364,7 +1355,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	INIT_LIST_HEAD(&vm->cleared);
- 	INIT_LIST_HEAD(&vm->freed);
- 	spin_lock_init(&vm->it_lock);
--	spin_lock_init(&vm->freed_lock);
- 	pd_size = amdgpu_vm_directory_size(adev);
- 	pd_entries = amdgpu_vm_num_pdes(adev);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0380-drm-amdgpu-Revert-add-lock-for-interval-tree-in-vm.patch b/common/recipes-kernel/linux/files/0380-drm-amdgpu-Revert-add-lock-for-interval-tree-in-vm.patch
deleted file mode 100644
index 5ba2bbd4..00000000
--- a/common/recipes-kernel/linux/files/0380-drm-amdgpu-Revert-add-lock-for-interval-tree-in-vm.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 689e07f1db7dbd6d5bd7ba7a2e43a2c4245dd8b2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 8 Mar 2016 17:58:35 +0100
-Subject: [PATCH 0380/1110] drm/amdgpu: Revert "add lock for interval tree in
- vm"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not needed any more because we need to protect the elements on the list anyway.
-
-This reverts commit fe237ed7efec8ac147a4572fdf81173a7f8ddda7.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--------------
- 2 files changed, 2 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 66aef04..929bf7f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -847,7 +847,6 @@ struct amdgpu_vm_id {
- 
- struct amdgpu_vm {
- 	/* tree of virtual addresses mapped */
--	spinlock_t		it_lock;
- 	struct rb_root		va;
- 
- 	/* protecting invalidated */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index c6b890c..f6d7d3f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -1112,9 +1112,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 	saddr /= AMDGPU_GPU_PAGE_SIZE;
- 	eaddr /= AMDGPU_GPU_PAGE_SIZE;
- 
--	spin_lock(&vm->it_lock);
- 	it = interval_tree_iter_first(&vm->va, saddr, eaddr);
--	spin_unlock(&vm->it_lock);
- 	if (it) {
- 		struct amdgpu_bo_va_mapping *tmp;
- 		tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
-@@ -1141,10 +1139,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 	mutex_lock(&bo_va->mutex);
- 	list_add(&mapping->list, &bo_va->invalids);
- 	mutex_unlock(&bo_va->mutex);
--	spin_lock(&vm->it_lock);
- 	interval_tree_insert(&mapping->it, &vm->va);
--	spin_unlock(&vm->it_lock);
--	trace_amdgpu_vm_bo_map(bo_va, mapping);
- 
- 	/* Make sure the page tables are allocated */
- 	saddr >>= amdgpu_vm_block_size;
-@@ -1196,9 +1191,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 
- error_free:
- 	list_del(&mapping->list);
--	spin_lock(&vm->it_lock);
- 	interval_tree_remove(&mapping->it, &vm->va);
--	spin_unlock(&vm->it_lock);
- 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
- 	kfree(mapping);
- 
-@@ -1248,9 +1241,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
- 	}
- 	mutex_unlock(&bo_va->mutex);
- 	list_del(&mapping->list);
--	spin_lock(&vm->it_lock);
- 	interval_tree_remove(&mapping->it, &vm->va);
--	spin_unlock(&vm->it_lock);
- 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
- 
- 	if (valid)
-@@ -1285,17 +1276,13 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
- 
- 	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
- 		list_del(&mapping->list);
--		spin_lock(&vm->it_lock);
- 		interval_tree_remove(&mapping->it, &vm->va);
--		spin_unlock(&vm->it_lock);
- 		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
- 		list_add(&mapping->list, &vm->freed);
- 	}
- 	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
- 		list_del(&mapping->list);
--		spin_lock(&vm->it_lock);
- 		interval_tree_remove(&mapping->it, &vm->va);
--		spin_unlock(&vm->it_lock);
- 		kfree(mapping);
- 	}
- 	fence_put(bo_va->last_pt_update);
-@@ -1354,7 +1341,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	INIT_LIST_HEAD(&vm->invalidated);
- 	INIT_LIST_HEAD(&vm->cleared);
- 	INIT_LIST_HEAD(&vm->freed);
--	spin_lock_init(&vm->it_lock);
-+
- 	pd_size = amdgpu_vm_directory_size(adev);
- 	pd_entries = amdgpu_vm_num_pdes(adev);
- 
-@@ -1438,6 +1425,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 
- 	amdgpu_bo_unref(&vm->page_directory);
- 	fence_put(vm->page_directory_fence);
-+
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 		struct amdgpu_vm_id *id = &vm->ids[i];
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0381-drm-amdgpu-Revert-add-mutex-for-ba_va-valids-invalid.patch b/common/recipes-kernel/linux/files/0381-drm-amdgpu-Revert-add-mutex-for-ba_va-valids-invalid.patch
deleted file mode 100644
index edeef8a0..00000000
--- a/common/recipes-kernel/linux/files/0381-drm-amdgpu-Revert-add-mutex-for-ba_va-valids-invalid.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 7f3e7b0ea58ae3b4189b61dbf9c468929ef861d4 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 8 Mar 2016 18:03:27 +0100
-Subject: [PATCH 0381/1110] drm/amdgpu: Revert "add mutex for
- ba_va->valids/invalids"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not needed any more because we need to protect the elements on the list anyway.
-
-This reverts commit 38bf516c75b4ef0f5c716e05fa9baab7c52d6c39.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ++++++-----------
- 2 files changed, 6 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 929bf7f..7fc816a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -445,7 +445,6 @@ struct amdgpu_bo_va_mapping {
- 
- /* bo virtual addresses in a specific vm */
- struct amdgpu_bo_va {
--	struct mutex		        mutex;
- 	/* protected by bo being reserved */
- 	struct list_head		bo_list;
- 	struct fence		        *last_pt_update;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index f6d7d3f..e2effcf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -1014,9 +1014,8 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
- 		bo_va = list_first_entry(&vm->invalidated,
- 			struct amdgpu_bo_va, vm_status);
- 		spin_unlock(&vm->status_lock);
--		mutex_lock(&bo_va->mutex);
-+
- 		r = amdgpu_vm_bo_update(adev, bo_va, NULL);
--		mutex_unlock(&bo_va->mutex);
- 		if (r)
- 			return r;
- 
-@@ -1060,7 +1059,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
- 	INIT_LIST_HEAD(&bo_va->valids);
- 	INIT_LIST_HEAD(&bo_va->invalids);
- 	INIT_LIST_HEAD(&bo_va->vm_status);
--	mutex_init(&bo_va->mutex);
-+
- 	list_add_tail(&bo_va->bo_list, &bo->va);
- 
- 	return bo_va;
-@@ -1136,9 +1135,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 	mapping->offset = offset;
- 	mapping->flags = flags;
- 
--	mutex_lock(&bo_va->mutex);
- 	list_add(&mapping->list, &bo_va->invalids);
--	mutex_unlock(&bo_va->mutex);
- 	interval_tree_insert(&mapping->it, &vm->va);
- 
- 	/* Make sure the page tables are allocated */
-@@ -1220,7 +1217,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
- 	bool valid = true;
- 
- 	saddr /= AMDGPU_GPU_PAGE_SIZE;
--	mutex_lock(&bo_va->mutex);
-+
- 	list_for_each_entry(mapping, &bo_va->valids, list) {
- 		if (mapping->it.start == saddr)
- 			break;
-@@ -1234,12 +1231,10 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
- 				break;
- 		}
- 
--		if (&mapping->list == &bo_va->invalids) {
--			mutex_unlock(&bo_va->mutex);
-+		if (&mapping->list == &bo_va->invalids)
- 			return -ENOENT;
--		}
- 	}
--	mutex_unlock(&bo_va->mutex);
-+
- 	list_del(&mapping->list);
- 	interval_tree_remove(&mapping->it, &vm->va);
- 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
-@@ -1285,8 +1280,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
- 		interval_tree_remove(&mapping->it, &vm->va);
- 		kfree(mapping);
- 	}
-+
- 	fence_put(bo_va->last_pt_update);
--	mutex_destroy(&bo_va->mutex);
- 	kfree(bo_va);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch b/common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch
deleted file mode 100644
index 4d51f448..00000000
--- a/common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch
+++ /dev/null
@@ -1,187 +0,0 @@
-From 0303a1a0480622a5fc8496ff28e442b339c8fca5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 8 Mar 2016 14:11:00 +0100
-Subject: [PATCH 0382/1110] drm/amdgpu: split pipeline sync out of SDMA
- vm_flush() as well
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Code it similar to how we did it for the gfx and compute engines.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 27 +++++++++++++++++++--------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 23 +++++++++++++++++------
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 23 +++++++++++++++++------
- 3 files changed, 53 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 481f22b..363d4f6 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -822,19 +822,14 @@ static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
- }
- 
- /**
-- * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
-+ * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
-  *
-  * @ring: amdgpu_ring pointer
-- * @vm: amdgpu_vm pointer
-  *
-- * Update the page table base and flush the VM TLB
-- * using sDMA (CIK).
-+ * Make sure all previous operations are completed (CIK).
-  */
--static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
--					unsigned vm_id, uint64_t pd_addr)
-+static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
- {
--	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
--			  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
- 	uint32_t seq = ring->fence_drv.sync_seq;
- 	uint64_t addr = ring->fence_drv.gpu_addr;
- 
-@@ -848,7 +843,22 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, seq); /* reference */
- 	amdgpu_ring_write(ring, 0xfffffff); /* mask */
- 	amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
-+}
- 
-+/**
-+ * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
-+ *
-+ * @ring: amdgpu_ring pointer
-+ * @vm: amdgpu_vm pointer
-+ *
-+ * Update the page table base and flush the VM TLB
-+ * using sDMA (CIK).
-+ */
-+static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
-+					unsigned vm_id, uint64_t pd_addr)
-+{
-+	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
-+			  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
- 
- 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
- 	if (vm_id < 8) {
-@@ -1290,6 +1300,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = cik_sdma_ring_emit_ib,
- 	.emit_fence = cik_sdma_ring_emit_fence,
-+	.emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
- 	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
- 	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
- 	.emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 4abfd11..b96ec4e 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -880,16 +880,13 @@ static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib
- }
- 
- /**
-- * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
-+ * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
-  *
-  * @ring: amdgpu_ring pointer
-- * @vm: amdgpu_vm pointer
-  *
-- * Update the page table base and flush the VM TLB
-- * using sDMA (VI).
-+ * Make sure all previous operations are completed (CIK).
-  */
--static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
--					 unsigned vm_id, uint64_t pd_addr)
-+static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
- {
- 	uint32_t seq = ring->fence_drv.sync_seq;
- 	uint64_t addr = ring->fence_drv.gpu_addr;
-@@ -905,7 +902,20 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, 0xfffffff); /* mask */
- 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
- 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
-+}
- 
-+/**
-+ * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
-+ *
-+ * @ring: amdgpu_ring pointer
-+ * @vm: amdgpu_vm pointer
-+ *
-+ * Update the page table base and flush the VM TLB
-+ * using sDMA (VI).
-+ */
-+static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
-+					 unsigned vm_id, uint64_t pd_addr)
-+{
- 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- 	if (vm_id < 8) {
-@@ -1295,6 +1305,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = sdma_v2_4_ring_emit_ib,
- 	.emit_fence = sdma_v2_4_ring_emit_fence,
-+	.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
- 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
- 	.emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 9a51233..4d1c0a3 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1031,16 +1031,13 @@ static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib
- }
- 
- /**
-- * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
-+ * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
-  *
-  * @ring: amdgpu_ring pointer
-- * @vm: amdgpu_vm pointer
-  *
-- * Update the page table base and flush the VM TLB
-- * using sDMA (VI).
-+ * Make sure all previous operations are completed (CIK).
-  */
--static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
--					 unsigned vm_id, uint64_t pd_addr)
-+static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
- {
- 	uint32_t seq = ring->fence_drv.sync_seq;
- 	uint64_t addr = ring->fence_drv.gpu_addr;
-@@ -1056,7 +1053,20 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, 0xfffffff); /* mask */
- 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
- 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
-+}
- 
-+/**
-+ * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
-+ *
-+ * @ring: amdgpu_ring pointer
-+ * @vm: amdgpu_vm pointer
-+ *
-+ * Update the page table base and flush the VM TLB
-+ * using sDMA (VI).
-+ */
-+static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-+					 unsigned vm_id, uint64_t pd_addr)
-+{
- 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- 	if (vm_id < 8) {
-@@ -1563,6 +1573,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
- 	.parse_cs = NULL,
- 	.emit_ib = sdma_v3_0_ring_emit_ib,
- 	.emit_fence = sdma_v3_0_ring_emit_fence,
-+	.emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
- 	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
- 	.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
- 	.emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0383-drm-amd-powerplay-mv-avfs-status-to-smumgr.h.patch b/common/recipes-kernel/linux/files/0383-drm-amd-powerplay-mv-avfs-status-to-smumgr.h.patch
deleted file mode 100644
index 0430e8ac..00000000
--- a/common/recipes-kernel/linux/files/0383-drm-amd-powerplay-mv-avfs-status-to-smumgr.h.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 56df4dcc0902d6fa297917af35b96de430f853cf Mon Sep 17 00:00:00 2001
-From: rezhu <Rex.Zhu@amd.com>
-Date: Mon, 16 Nov 2015 10:24:17 +0800
-Subject: [PATCH 0383/1110] drm/amd/powerplay: mv avfs status to smumgr.h
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/smumgr.h         | 21 +++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h | 18 ------------------
- 2 files changed, 21 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
-index 504f035..fc9e3d1 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
-@@ -32,6 +32,27 @@ struct pp_instance;
- #define smu_lower_32_bits(n) ((uint32_t)(n))
- #define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
- 
-+enum AVFS_BTC_STATUS {
-+	AVFS_BTC_BOOT = 0,
-+	AVFS_BTC_BOOT_STARTEDSMU,
-+	AVFS_LOAD_VIRUS,
-+	AVFS_BTC_VIRUS_LOADED,
-+	AVFS_BTC_VIRUS_FAIL,
-+	AVFS_BTC_COMPLETED_PREVIOUSLY,
-+	AVFS_BTC_ENABLEAVFS,
-+	AVFS_BTC_STARTED,
-+	AVFS_BTC_FAILED,
-+	AVFS_BTC_RESTOREVFT_FAILED,
-+	AVFS_BTC_SAVEVFT_FAILED,
-+	AVFS_BTC_DPMTABLESETUP_FAILED,
-+	AVFS_BTC_COMPLETED_UNSAVED,
-+	AVFS_BTC_COMPLETED_SAVED,
-+	AVFS_BTC_COMPLETED_RESTORED,
-+	AVFS_BTC_DISABLED,
-+	AVFS_BTC_NOTSUPPORTED,
-+	AVFS_BTC_SMUMSG_ERROR
-+};
-+
- struct pp_smumgr_func {
- 	int (*smu_init)(struct pp_smumgr *smumgr);
- 	int (*smu_fini)(struct pp_smumgr *smumgr);
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
-index 8cd22d9..b4eb483 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h
-@@ -23,24 +23,6 @@
- #ifndef _FIJI_SMUMANAGER_H_
- #define _FIJI_SMUMANAGER_H_
- 
--enum AVFS_BTC_STATUS {
--	AVFS_BTC_BOOT = 0,
--	AVFS_BTC_BOOT_STARTEDSMU,
--	AVFS_LOAD_VIRUS,
--	AVFS_BTC_VIRUS_LOADED,
--	AVFS_BTC_VIRUS_FAIL,
--	AVFS_BTC_STARTED,
--	AVFS_BTC_FAILED,
--	AVFS_BTC_RESTOREVFT_FAILED,
--	AVFS_BTC_SAVEVFT_FAILED,
--	AVFS_BTC_DPMTABLESETUP_FAILED,
--	AVFS_BTC_COMPLETED_UNSAVED,
--	AVFS_BTC_COMPLETED_SAVED,
--	AVFS_BTC_COMPLETED_RESTORED,
--	AVFS_BTC_DISABLED,
--	AVFS_BTC_NOTSUPPORTED,
--	AVFS_BTC_SMUMSG_ERROR
--};
- 
- struct fiji_smu_avfs {
- 	enum AVFS_BTC_STATUS AvfsBtcStatus;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0384-drm-amd-powerplay-add-a-common-pp-endian-header.patch b/common/recipes-kernel/linux/files/0384-drm-amd-powerplay-add-a-common-pp-endian-header.patch
deleted file mode 100644
index a956b7d8..00000000
--- a/common/recipes-kernel/linux/files/0384-drm-amd-powerplay-add-a-common-pp-endian-header.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 71e40dc9782082e6d38bde1b5c758ba786527ce2 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 6 Jan 2016 12:58:19 -0500
-Subject: [PATCH 0384/1110] drm/amd/powerplay: add a common pp endian header
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-To replace the duplicated versions of this in all asic
-variants.
-
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/inc/pp_endian.h | 38 +++++++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_endian.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_endian.h b/drivers/gpu/drm/amd/powerplay/inc/pp_endian.h
-new file mode 100644
-index 0000000..f49d196
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_endian.h
-@@ -0,0 +1,38 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _PP_ENDIAN_H_
-+#define _PP_ENDIAN_H_
-+
-+#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
-+#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
-+
-+#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
-+#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
-+
-+#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
-+#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
-+
-+#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
-+
-+#endif /* _PP_ENDIAN_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0385-drm-amd-powerplay-use-pp_endian.h-for-Fiji.patch b/common/recipes-kernel/linux/files/0385-drm-amd-powerplay-use-pp_endian.h-for-Fiji.patch
deleted file mode 100644
index 6d807903..00000000
--- a/common/recipes-kernel/linux/files/0385-drm-amd-powerplay-use-pp_endian.h-for-Fiji.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 8f71fec1d8a3adab7c808e89b68fa3ca758e0272 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 6 Jan 2016 13:00:16 -0500
-Subject: [PATCH 0385/1110] drm/amd/powerplay: use pp_endian.h for Fiji
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Drop local versions of these macros.
-
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h | 12 +-----------
- 1 file changed, 1 insertion(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-index 22e273b..a16f7cd 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -29,6 +29,7 @@
- #include "smu73_discrete.h"
- #include "ppatomctrl.h"
- #include "fiji_ppsmc.h"
-+#include "pp_endian.h"
- 
- #define FIJI_MAX_HARDWARE_POWERLEVELS	2
- #define FIJI_AT_DFLT	30
-@@ -347,15 +348,4 @@ int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
- int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
- int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
- 
--#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
--#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
--
--#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
--#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
--
--#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
--#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
--
--#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
--
- #endif /* _FIJI_HWMGR_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0386-drm-amd-powerplay-use-pp_endian.h-for-Tonga.patch b/common/recipes-kernel/linux/files/0386-drm-amd-powerplay-use-pp_endian.h-for-Tonga.patch
deleted file mode 100644
index 5c47c4d2..00000000
--- a/common/recipes-kernel/linux/files/0386-drm-amd-powerplay-use-pp_endian.h-for-Tonga.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 28a97bd5b656923b1bf9959872620ae7a612908d Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 6 Jan 2016 13:02:10 -0500
-Subject: [PATCH 0386/1110] drm/amd/powerplay: use pp_endian.h for Tonga
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Drop local versions of these macros.
-
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h | 12 +-----------
- 1 file changed, 1 insertion(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index 49168d2..f88d3bb 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -28,6 +28,7 @@
- #include "ppatomctrl.h"
- #include "ppinterrupt.h"
- #include "tonga_powertune.h"
-+#include "pp_endian.h"
- 
- #define TONGA_MAX_HARDWARE_POWERLEVELS 2
- #define TONGA_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
-@@ -386,17 +387,6 @@ typedef struct tonga_hwmgr tonga_hwmgr;
- 
- #define TONGA_UNUSED_GPIO_PIN                        0x7F
- 
--#define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
--#define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
--
--#define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
--#define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
--
--#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
--#define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
--
--#define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
--
- int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
- int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
- int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0387-drm-amdgpu-allow-write-access-to-mapped-userptrs.patch b/common/recipes-kernel/linux/files/0387-drm-amdgpu-allow-write-access-to-mapped-userptrs.patch
deleted file mode 100644
index ef2669fc..00000000
--- a/common/recipes-kernel/linux/files/0387-drm-amdgpu-allow-write-access-to-mapped-userptrs.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From fe4dc2639d9edab456d6cc191a0ff9f8e3491fda Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 15:29:27 +0100
-Subject: [PATCH 0387/1110] drm/amdgpu: allow write access to mapped userptrs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With the updated MMU notifier we should also be able to
-handle the writeback case correctly.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index dcf6611..e9bf5a5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -258,12 +258,10 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
- 	    AMDGPU_GEM_USERPTR_REGISTER))
- 		return -EINVAL;
- 
--	if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && (
--	     !(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
--	     !(args->flags & AMDGPU_GEM_USERPTR_REGISTER))) {
-+	if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
-+	     !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
- 
--		/* if we want to write to it we must require anonymous
--		   memory and install a MMU notifier */
-+		/* if we want to write to it we must install a MMU notifier */
- 		return -EACCES;
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0388-drm-amdgpu-always-wait-before-kmap-a-BO.patch b/common/recipes-kernel/linux/files/0388-drm-amdgpu-always-wait-before-kmap-a-BO.patch
deleted file mode 100644
index b75d2cb6..00000000
--- a/common/recipes-kernel/linux/files/0388-drm-amdgpu-always-wait-before-kmap-a-BO.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 8d3e36dd379aa625ce65810010be8e42facb6e83 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 10 Mar 2016 16:21:04 +0100
-Subject: [PATCH 0388/1110] drm/amdgpu: always wait before kmap a BO
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-When a BO is currently moving we otherwise would blindly
-access the new location without checking.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 16 +++++++++++-----
- 1 file changed, 11 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index c980cba..7700867 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -308,7 +308,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
- int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
- {
- 	bool is_iomem;
--	int r;
-+	long r;
- 
- 	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
- 		return -EPERM;
-@@ -319,14 +319,20 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
- 		}
- 		return 0;
- 	}
-+
-+	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
-+						MAX_SCHEDULE_TIMEOUT);
-+	if (r < 0)
-+		return r;
-+
- 	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
--	if (r) {
-+	if (r)
- 		return r;
--	}
-+
- 	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
--	if (ptr) {
-+	if (ptr)
- 		*ptr = bo->kptr;
--	}
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0389-drm-amdgpu-stop-waiting-on-UVD-messages-before-mappi.patch b/common/recipes-kernel/linux/files/0389-drm-amdgpu-stop-waiting-on-UVD-messages-before-mappi.patch
deleted file mode 100644
index 42daf16b..00000000
--- a/common/recipes-kernel/linux/files/0389-drm-amdgpu-stop-waiting-on-UVD-messages-before-mappi.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From de275afd2e8b1ea9b985643743868e55ef11820a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 10 Mar 2016 16:23:29 +0100
-Subject: [PATCH 0389/1110] drm/amdgpu: stop waiting on UVD messages before
- mapping them
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-amdgpu_bo_kmap() now always waits for moves to finish.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 7 -------
- 1 file changed, 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index c00df2f..aa8bdd4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -543,13 +543,6 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 		return -EINVAL;
- 	}
- 
--	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
--						MAX_SCHEDULE_TIMEOUT);
--	if (r < 0) {
--		DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
--		return r;
--	}
--
- 	r = amdgpu_bo_kmap(bo, &ptr);
- 	if (r) {
- 		DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0390-drm-amdgpu-stop-using-the-ring-index-in-the-SA.patch b/common/recipes-kernel/linux/files/0390-drm-amdgpu-stop-using-the-ring-index-in-the-SA.patch
deleted file mode 100644
index 2300320a..00000000
--- a/common/recipes-kernel/linux/files/0390-drm-amdgpu-stop-using-the-ring-index-in-the-SA.patch
+++ /dev/null
@@ -1,177 +0,0 @@
-From b94cc62076223ff4af68772430e75e0d0ef6e3bc Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 14:50:08 +0100
-Subject: [PATCH 0390/1110] drm/amdgpu: stop using the ring index in the SA
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The ring index will always collide as hash into the fence list, so use
-the context number instead. That can still cause collisions, but they
-are less likely than using ring indices.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  5 +++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 53 ++++++++++++----------------------
- 2 files changed, 22 insertions(+), 36 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 7fc816a..3abc639 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -540,11 +540,14 @@ int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
-  * Assumption is that there won't be hole (all object on same
-  * alignment).
-  */
-+
-+#define AMDGPU_SA_NUM_FENCE_LISTS	32
-+
- struct amdgpu_sa_manager {
- 	wait_queue_head_t	wq;
- 	struct amdgpu_bo	*bo;
- 	struct list_head	*hole;
--	struct list_head	flist[AMDGPU_MAX_RINGS];
-+	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];
- 	struct list_head	olist;
- 	unsigned		size;
- 	uint64_t		gpu_addr;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
-index 2faf03b..8bf84ef 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
-@@ -60,9 +60,8 @@ int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
- 	sa_manager->align = align;
- 	sa_manager->hole = &sa_manager->olist;
- 	INIT_LIST_HEAD(&sa_manager->olist);
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-+	for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
- 		INIT_LIST_HEAD(&sa_manager->flist[i]);
--	}
- 
- 	r = amdgpu_bo_create(adev, size, align, true, domain,
- 			     0, NULL, NULL, &sa_manager->bo);
-@@ -228,11 +227,9 @@ static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
- 	unsigned soffset, eoffset, wasted;
- 	int i;
- 
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		if (!list_empty(&sa_manager->flist[i])) {
-+	for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
-+		if (!list_empty(&sa_manager->flist[i]))
- 			return true;
--		}
--	}
- 
- 	soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
- 	eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
-@@ -265,12 +262,11 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
- 	/* go over all fence list and try to find the closest sa_bo
- 	 * of the current last
- 	 */
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-+	for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
- 		struct amdgpu_sa_bo *sa_bo;
- 
--		if (list_empty(&sa_manager->flist[i])) {
-+		if (list_empty(&sa_manager->flist[i]))
- 			continue;
--		}
- 
- 		sa_bo = list_first_entry(&sa_manager->flist[i],
- 					 struct amdgpu_sa_bo, flist);
-@@ -299,7 +295,9 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
- 	}
- 
- 	if (best_bo) {
--		uint32_t idx = amdgpu_ring_from_fence(best_bo->fence)->idx;
-+		uint32_t idx = best_bo->fence->context;
-+
-+		idx %= AMDGPU_SA_NUM_FENCE_LISTS;
- 		++tries[idx];
- 		sa_manager->hole = best_bo->olist.prev;
- 
-@@ -315,8 +313,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
- 		     struct amdgpu_sa_bo **sa_bo,
- 		     unsigned size, unsigned align)
- {
--	struct fence *fences[AMDGPU_MAX_RINGS];
--	unsigned tries[AMDGPU_MAX_RINGS];
-+	struct fence *fences[AMDGPU_SA_NUM_FENCE_LISTS];
-+	unsigned tries[AMDGPU_SA_NUM_FENCE_LISTS];
- 	unsigned count;
- 	int i, r;
- 	signed long t;
-@@ -338,7 +336,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
- 
- 	spin_lock(&sa_manager->wq.lock);
- 	do {
--		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-+		for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
- 			fences[i] = NULL;
- 			tries[i] = 0;
- 		}
-@@ -355,7 +353,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
- 			/* see if we can skip over some allocations */
- 		} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
- 
--		for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)
-+		for (i = 0, count = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
- 			if (fences[i])
- 				fences[count++] = fence_get(fences[i]);
- 
-@@ -397,8 +395,9 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
- 	spin_lock(&sa_manager->wq.lock);
- 	if (fence && !fence_is_signaled(fence)) {
- 		uint32_t idx;
-+
- 		(*sa_bo)->fence = fence_get(fence);
--		idx = amdgpu_ring_from_fence(fence)->idx;
-+		idx = fence->context % AMDGPU_SA_NUM_FENCE_LISTS;
- 		list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);
- 	} else {
- 		amdgpu_sa_bo_remove_locked(*sa_bo);
-@@ -410,25 +409,6 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
- 
- #if defined(CONFIG_DEBUG_FS)
- 
--static void amdgpu_sa_bo_dump_fence(struct fence *fence, struct seq_file *m)
--{
--	struct amdgpu_fence *a_fence = to_amdgpu_fence(fence);
--	struct amd_sched_fence *s_fence = to_amd_sched_fence(fence);
--
--	if (a_fence)
--		seq_printf(m, " protected by 0x%016llx on ring %d",
--			   a_fence->seq, a_fence->ring->idx);
--
--	if (s_fence) {
--		struct amdgpu_ring *ring;
--
--
--		ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
--		seq_printf(m, " protected by 0x%016x on ring %d",
--			   s_fence->base.seqno, ring->idx);
--	}
--}
--
- void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
- 				  struct seq_file *m)
- {
-@@ -445,8 +425,11 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
- 		}
- 		seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
- 			   soffset, eoffset, eoffset - soffset);
-+
- 		if (i->fence)
--			amdgpu_sa_bo_dump_fence(i->fence, m);
-+			seq_printf(m, " protected by 0x%08x on context %d",
-+				   i->fence->seqno, i->fence->context);
-+
- 		seq_printf(m, "\n");
- 	}
- 	spin_unlock(&sa_manager->wq.lock);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0391-drm-amdgpu-remove-amdgpu_ring_from_fence.patch b/common/recipes-kernel/linux/files/0391-drm-amdgpu-remove-amdgpu_ring_from_fence.patch
deleted file mode 100644
index fc2b83d9..00000000
--- a/common/recipes-kernel/linux/files/0391-drm-amdgpu-remove-amdgpu_ring_from_fence.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From e66103524443d0940bbf60bd37f7111a8518ffbc Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 14:55:20 +0100
-Subject: [PATCH 0391/1110] drm/amdgpu: remove amdgpu_ring_from_fence
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 24 ------------------------
- 2 files changed, 25 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 3abc639..595133b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1171,7 +1171,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
- 		     enum amdgpu_ring_type ring_type);
- void amdgpu_ring_fini(struct amdgpu_ring *ring);
--struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
- 
- /*
-  * CS.
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 56c07e3..cc3c7ad 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -352,30 +352,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
- 	}
- }
- 
--/**
-- * amdgpu_ring_from_fence - get ring from fence
-- *
-- * @f: fence structure
-- *
-- * Extract the ring a fence belongs to. Handles both scheduler as
-- * well as hardware fences.
-- */
--struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f)
--{
--	struct amdgpu_fence *a_fence;
--	struct amd_sched_fence *s_fence;
--
--	s_fence = to_amd_sched_fence(f);
--	if (s_fence)
--		return container_of(s_fence->sched, struct amdgpu_ring, sched);
--
--	a_fence = to_amdgpu_fence(f);
--	if (a_fence)
--		return a_fence->ring;
--
--	return NULL;
--}
--
- /*
-  * Debugfs info
-  */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0392-drm-amdgpu-remove-amdgpu_fence_wait_next.patch b/common/recipes-kernel/linux/files/0392-drm-amdgpu-remove-amdgpu_fence_wait_next.patch
deleted file mode 100644
index 7aec724e..00000000
--- a/common/recipes-kernel/linux/files/0392-drm-amdgpu-remove-amdgpu_fence_wait_next.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From cb4d67f0d23ffb6637b22b2d8a0f8b44a9b4fbaf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 15:15:02 +0100
-Subject: [PATCH 0392/1110] drm/amdgpu: remove amdgpu_fence_wait_next
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 20 --------------------
- 2 files changed, 21 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 595133b..0f6ee5d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -393,7 +393,6 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
- void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
- int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
- void amdgpu_fence_process(struct amdgpu_ring *ring);
--int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
- unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 83599f2..fabb01e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -282,26 +282,6 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
- }
- 
- /**
-- * amdgpu_fence_wait_next - wait for the next fence to signal
-- *
-- * @adev: amdgpu device pointer
-- * @ring: ring index the fence is associated with
-- *
-- * Wait for the next fence on the requested ring to signal (all asics).
-- * Returns 0 if the next fence has passed, error for all other cases.
-- * Caller must hold ring lock.
-- */
--int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
--{
--	uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
--
--	if (seq >= ring->fence_drv.sync_seq)
--		return -ENOENT;
--
--	return amdgpu_fence_ring_wait_seq(ring, seq);
--}
--
--/**
-  * amdgpu_fence_wait_empty - wait for all fences to signal
-  *
-  * @adev: amdgpu device pointer
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0393-drm-amdgpu-move-fence-structure-into-amdgpu_fence.c.patch b/common/recipes-kernel/linux/files/0393-drm-amdgpu-move-fence-structure-into-amdgpu_fence.c.patch
deleted file mode 100644
index 8a6f42dc..00000000
--- a/common/recipes-kernel/linux/files/0393-drm-amdgpu-move-fence-structure-into-amdgpu_fence.c.patch
+++ /dev/null
@@ -1,119 +0,0 @@
-From 1bfbfdfdebe5ddde2ecdc0448ab3eff6ea8726e8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 15:12:53 +0100
-Subject: [PATCH 0393/1110] drm/amdgpu: move fence structure into
- amdgpu_fence.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to have that in the header file any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 25 -------------------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 26 +++++++++++++++++++++++++-
- 2 files changed, 25 insertions(+), 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0f6ee5d..19f8c46 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -141,7 +141,6 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define CIK_CURSOR_HEIGHT 128
- 
- struct amdgpu_device;
--struct amdgpu_fence;
- struct amdgpu_ib;
- struct amdgpu_vm;
- struct amdgpu_ring;
-@@ -364,16 +363,6 @@ struct amdgpu_fence_driver {
- #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
- #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
- 
--struct amdgpu_fence {
--	struct fence base;
--
--	/* RB, DMA, etc. */
--	struct amdgpu_ring		*ring;
--	uint64_t			seq;
--
--	wait_queue_t			fence_wake;
--};
--
- struct amdgpu_user_fence {
- 	/* write-back bo */
- 	struct amdgpu_bo 	*bo;
-@@ -2073,20 +2062,6 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
- void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
- 
- /*
-- * Cast helper
-- */
--extern const struct fence_ops amdgpu_fence_ops;
--static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
--{
--	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
--
--	if (__f->base.ops == &amdgpu_fence_ops)
--		return __f;
--
--	return NULL;
--}
--
--/*
-  * Registers read & write functions.
-  */
- #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index fabb01e..3db18f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -47,9 +47,33 @@
-  * that the the relevant GPU caches have been flushed.
-  */
- 
-+struct amdgpu_fence {
-+	struct fence base;
-+
-+	/* RB, DMA, etc. */
-+	struct amdgpu_ring		*ring;
-+	uint64_t			seq;
-+
-+	wait_queue_t			fence_wake;
-+};
-+
- static struct kmem_cache *amdgpu_fence_slab;
- static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);
- 
-+/*
-+ * Cast helper
-+ */
-+static const struct fence_ops amdgpu_fence_ops;
-+static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
-+{
-+	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
-+
-+	if (__f->base.ops == &amdgpu_fence_ops)
-+		return __f;
-+
-+	return NULL;
-+}
-+
- /**
-  * amdgpu_fence_write - write a fence value
-  *
-@@ -663,7 +687,7 @@ static void amdgpu_fence_release(struct fence *f)
- 	kmem_cache_free(amdgpu_fence_slab, fence);
- }
- 
--const struct fence_ops amdgpu_fence_ops = {
-+static const struct fence_ops amdgpu_fence_ops = {
- 	.get_driver_name = amdgpu_fence_get_driver_name,
- 	.get_timeline_name = amdgpu_fence_get_timeline_name,
- 	.enable_signaling = amdgpu_fence_enable_signaling,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0394-drm-amdgpu-cleanup-amdgpu_fence_activity.patch b/common/recipes-kernel/linux/files/0394-drm-amdgpu-cleanup-amdgpu_fence_activity.patch
deleted file mode 100644
index ac95a26c..00000000
--- a/common/recipes-kernel/linux/files/0394-drm-amdgpu-cleanup-amdgpu_fence_activity.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 149a30121e2a4169b331e317d8061f8e523f7afa Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 17:49:58 +0100
-Subject: [PATCH 0394/1110] drm/amdgpu: cleanup amdgpu_fence_activity
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The comment about the loop counter was never valid, even when you have
-multiple threads this loop only runs as long as the sequence increases.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 35 +++----------------------------
- 1 file changed, 3 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 3db18f4..35fbc88 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -166,30 +166,8 @@ static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
- static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
- {
- 	uint64_t seq, last_seq, last_emitted;
--	unsigned count_loop = 0;
- 	bool wake = false;
- 
--	/* Note there is a scenario here for an infinite loop but it's
--	 * very unlikely to happen. For it to happen, the current polling
--	 * process need to be interrupted by another process and another
--	 * process needs to update the last_seq btw the atomic read and
--	 * xchg of the current process.
--	 *
--	 * More over for this to go in infinite loop there need to be
--	 * continuously new fence signaled ie amdgpu_fence_read needs
--	 * to return a different value each time for both the currently
--	 * polling process and the other process that xchg the last_seq
--	 * btw atomic read and xchg of the current process. And the
--	 * value the other process set as last seq must be higher than
--	 * the seq value we just read. Which means that current process
--	 * need to be interrupted after amdgpu_fence_read and before
--	 * atomic xchg.
--	 *
--	 * To be even more safe we count the number of time we loop and
--	 * we bail after 10 loop just accepting the fact that we might
--	 * have temporarly set the last_seq not to the true real last
--	 * seq but to an older one.
--	 */
- 	last_seq = atomic64_read(&ring->fence_drv.last_seq);
- 	do {
- 		last_emitted = ring->fence_drv.sync_seq;
-@@ -200,23 +178,16 @@ static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
- 			seq |= last_emitted & 0xffffffff00000000LL;
- 		}
- 
--		if (seq <= last_seq || seq > last_emitted) {
-+		if (seq <= last_seq || seq > last_emitted)
- 			break;
--		}
-+
- 		/* If we loop over we don't want to return without
- 		 * checking if a fence is signaled as it means that the
- 		 * seq we just read is different from the previous on.
- 		 */
- 		wake = true;
- 		last_seq = seq;
--		if ((count_loop++) > 10) {
--			/* We looped over too many time leave with the
--			 * fact that we might have set an older fence
--			 * seq then the current real last seq as signaled
--			 * by the hw.
--			 */
--			break;
--		}
-+
- 	} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
- 
- 	if (seq < last_emitted)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0395-drm-amdgpu-merge-amdgpu_fence_process-and-_activity.patch b/common/recipes-kernel/linux/files/0395-drm-amdgpu-merge-amdgpu_fence_process-and-_activity.patch
deleted file mode 100644
index e8ade9f6..00000000
--- a/common/recipes-kernel/linux/files/0395-drm-amdgpu-merge-amdgpu_fence_process-and-_activity.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 2658022b2a789a112617ed1e68e8c6f94c4431d5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Mar 2016 17:57:56 +0100
-Subject: [PATCH 0395/1110] drm/amdgpu: merge amdgpu_fence_process and
- _activity
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to keep the two separate any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 24 +++++-------------------
- 1 file changed, 5 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 35fbc88..d8bbe85 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -155,15 +155,15 @@ static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
- }
- 
- /**
-- * amdgpu_fence_activity - check for fence activity
-+ * amdgpu_fence_process - check for fence activity
-  *
-  * @ring: pointer to struct amdgpu_ring
-  *
-  * Checks the current fence value and calculates the last
-- * signalled fence value. Returns true if activity occured
-- * on the ring, and the fence_queue should be waken up.
-+ * signalled fence value. Wakes the fence queue if the
-+ * sequence number has increased.
-  */
--static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
-+void amdgpu_fence_process(struct amdgpu_ring *ring)
- {
- 	uint64_t seq, last_seq, last_emitted;
- 	bool wake = false;
-@@ -193,21 +193,7 @@ static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
- 	if (seq < last_emitted)
- 		amdgpu_fence_schedule_fallback(ring);
- 
--	return wake;
--}
--
--/**
-- * amdgpu_fence_process - process a fence
-- *
-- * @adev: amdgpu_device pointer
-- * @ring: ring index the fence is associated with
-- *
-- * Checks the current fence value and wakes the fence queue
-- * if the sequence number has increased (all asics).
-- */
--void amdgpu_fence_process(struct amdgpu_ring *ring)
--{
--	if (amdgpu_fence_activity(ring))
-+	if (wake)
- 		wake_up_all(&ring->fence_drv.fence_queue);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0396-drm-amdgpu-RCU-protected-amdgpu_fence_release.patch b/common/recipes-kernel/linux/files/0396-drm-amdgpu-RCU-protected-amdgpu_fence_release.patch
deleted file mode 100644
index fc3e54aa..00000000
--- a/common/recipes-kernel/linux/files/0396-drm-amdgpu-RCU-protected-amdgpu_fence_release.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 352824dfbfbff5328210e72402abe1a934113ce0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 15 Mar 2016 13:40:17 +0100
-Subject: [PATCH 0396/1110] drm/amdgpu: RCU protected amdgpu_fence_release
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Fences must be freed RCU protected, otherwise the reservation_object_*_rcu()
-functions can run into problems.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index d8bbe85..ec73ab1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -638,12 +638,33 @@ static bool amdgpu_fence_enable_signaling(struct fence *f)
- 	return true;
- }
- 
--static void amdgpu_fence_release(struct fence *f)
-+/**
-+ * amdgpu_fence_free - free up the fence memory
-+ *
-+ * @rcu: RCU callback head
-+ *
-+ * Free up the fence memory after the RCU grace period.
-+ */
-+static void amdgpu_fence_free(struct rcu_head *rcu)
- {
-+	struct fence *f = container_of(rcu, struct fence, rcu);
- 	struct amdgpu_fence *fence = to_amdgpu_fence(f);
- 	kmem_cache_free(amdgpu_fence_slab, fence);
- }
- 
-+/**
-+ * amdgpu_fence_release - callback that fence can be freed
-+ *
-+ * @fence: fence
-+ *
-+ * This function is called when the reference count becomes zero.
-+ * It just RCU schedules freeing up the fence.
-+ */
-+static void amdgpu_fence_release(struct fence *f)
-+{
-+	call_rcu(&f->rcu, amdgpu_fence_free);
-+}
-+
- static const struct fence_ops amdgpu_fence_ops = {
- 	.get_driver_name = amdgpu_fence_get_driver_name,
- 	.get_timeline_name = amdgpu_fence_get_timeline_name,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0397-drm-amdgpu-RCU-protected-amd_sched_fence_release.patch b/common/recipes-kernel/linux/files/0397-drm-amdgpu-RCU-protected-amd_sched_fence_release.patch
deleted file mode 100644
index 38fe782e..00000000
--- a/common/recipes-kernel/linux/files/0397-drm-amdgpu-RCU-protected-amd_sched_fence_release.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From b21fc40ce5fbde04cca84b5a635e5ffbcae6ba80 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 15 Mar 2016 13:58:14 +0100
-Subject: [PATCH 0397/1110] drm/amdgpu: RCU protected amd_sched_fence_release
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Fences must be freed RCU protected, otherwise the reservation_object_*_rcu()
-functions can run into problems.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/scheduler/sched_fence.c | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c
-index 87c78ee..dc115ae 100644
---- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
-+++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c
-@@ -84,12 +84,33 @@ static bool amd_sched_fence_enable_signaling(struct fence *f)
- 	return true;
- }
- 
--static void amd_sched_fence_release(struct fence *f)
-+/**
-+ * amd_sched_fence_free - free up the fence memory
-+ *
-+ * @rcu: RCU callback head
-+ *
-+ * Free up the fence memory after the RCU grace period.
-+ */
-+static void amd_sched_fence_free(struct rcu_head *rcu)
- {
-+	struct fence *f = container_of(rcu, struct fence, rcu);
- 	struct amd_sched_fence *fence = to_amd_sched_fence(f);
- 	kmem_cache_free(sched_fence_slab, fence);
- }
- 
-+/**
-+ * amd_sched_fence_release - callback that fence can be freed
-+ *
-+ * @fence: fence
-+ *
-+ * This function is called when the reference count becomes zero.
-+ * It just RCU schedules freeing up the fence.
-+ */
-+static void amd_sched_fence_release(struct fence *f)
-+{
-+	call_rcu(&f->rcu, amd_sched_fence_free);
-+}
-+
- const struct fence_ops amd_sched_fence_ops = {
- 	.get_driver_name = amd_sched_fence_get_driver_name,
- 	.get_timeline_name = amd_sched_fence_get_timeline_name,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0398-drm-amdgpu-add-number-of-hardware-submissions-to-amd.patch b/common/recipes-kernel/linux/files/0398-drm-amdgpu-add-number-of-hardware-submissions-to-amd.patch
deleted file mode 100644
index d6fcba9c..00000000
--- a/common/recipes-kernel/linux/files/0398-drm-amdgpu-add-number-of-hardware-submissions-to-amd.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From abc34e0409c28dd32419f25329279ef320274ca3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 15 Mar 2016 14:52:26 +0100
-Subject: [PATCH 0398/1110] drm/amdgpu: add number of hardware submissions to
- amdgpu_fence_driver_init_ring
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Make this a parameter instead of using the global variable directly.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  3 ++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 10 ++++++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c  |  3 ++-
- 3 files changed, 12 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 19f8c46..bd556b4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -374,7 +374,8 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev);
- void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
- void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
- 
--int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
-+int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
-+				  unsigned num_hw_submission);
- int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
- 				   struct amdgpu_irq_src *irq_src,
- 				   unsigned irq_type);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index ec73ab1..4654113 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -355,15 +355,21 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
-  * for the requested ring.
-  *
-  * @ring: ring to init the fence driver on
-+ * @num_hw_submission: number of entries on the hardware queue
-  *
-  * Init the fence driver for the requested ring (all asics).
-  * Helper function for amdgpu_fence_driver_init().
-  */
--int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
-+int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
-+				  unsigned num_hw_submission)
- {
- 	long timeout;
- 	int r;
- 
-+	/* Check that num_hw_submission is a power of two */
-+	if ((num_hw_submission & (num_hw_submission - 1)) != 0)
-+		return -EINVAL;
-+
- 	ring->fence_drv.cpu_addr = NULL;
- 	ring->fence_drv.gpu_addr = 0;
- 	ring->fence_drv.sync_seq = 0;
-@@ -387,7 +393,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
- 		timeout = MAX_SCHEDULE_TIMEOUT;
- 	}
- 	r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
--			   amdgpu_sched_hw_submission,
-+			   num_hw_submission,
- 			   timeout, ring->name);
- 	if (r) {
- 		DRM_ERROR("Failed to create scheduler on ring %s.\n",
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index cc3c7ad..972eed2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -236,7 +236,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		ring->adev = adev;
- 		ring->idx = adev->num_rings++;
- 		adev->rings[ring->idx] = ring;
--		r = amdgpu_fence_driver_init_ring(ring);
-+		r = amdgpu_fence_driver_init_ring(ring,
-+			amdgpu_sched_hw_submission);
- 		if (r)
- 			return r;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0399-drm-amdgpu-keep-all-fences-in-an-RCU-protected-array.patch b/common/recipes-kernel/linux/files/0399-drm-amdgpu-keep-all-fences-in-an-RCU-protected-array.patch
deleted file mode 100644
index 2d5a9c49..00000000
--- a/common/recipes-kernel/linux/files/0399-drm-amdgpu-keep-all-fences-in-an-RCU-protected-array.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From 7d2083232b7c288ba4a6c440d5382c010d8a12e9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 13 Mar 2016 19:19:48 +0100
-Subject: [PATCH 0399/1110] drm/amdgpu: keep all fences in an RCU protected
- array v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just keep all HW fences in a RCU protected array as a
-first step to replace the wait queue.
-
-v2: update commit message, move fixes into separate patch.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 32 ++++++++++++++++++++++++++++---
- 2 files changed, 31 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index bd556b4..43c948d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -354,6 +354,8 @@ struct amdgpu_fence_driver {
- 	unsigned			irq_type;
- 	struct timer_list		fallback_timer;
- 	wait_queue_head_t		fence_queue;
-+	unsigned			num_fences_mask;
-+	struct fence			**fences;
- };
- 
- /* some special values for the owner field */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 4654113..44eac91 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -124,6 +124,8 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- {
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_fence *fence;
-+	struct fence *old, **ptr;
-+	unsigned idx;
- 
- 	fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
- 	if (fence == NULL)
-@@ -137,7 +139,21 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- 		   fence->seq);
- 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
- 			       fence->seq, AMDGPU_FENCE_FLAG_INT);
-+
-+	idx = fence->seq & ring->fence_drv.num_fences_mask;
-+	ptr = &ring->fence_drv.fences[idx];
-+	/* This function can't be called concurrently anyway, otherwise
-+	 * emitting the fence would mess up the hardware ring buffer.
-+	 */
-+	old = rcu_dereference_protected(*ptr, 1);
-+
-+	rcu_assign_pointer(*ptr, fence_get(&fence->base));
-+
-+	BUG_ON(old && !fence_is_signaled(old));
-+	fence_put(old);
-+
- 	*f = &fence->base;
-+
- 	return 0;
- }
- 
-@@ -380,6 +396,11 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
- 		    (unsigned long)ring);
- 
- 	init_waitqueue_head(&ring->fence_drv.fence_queue);
-+	ring->fence_drv.num_fences_mask = num_hw_submission - 1;
-+	ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *),
-+					 GFP_KERNEL);
-+	if (!ring->fence_drv.fences)
-+		return -ENOMEM;
- 
- 	timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
- 	if (timeout == 0) {
-@@ -441,10 +462,9 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev)
-  */
- void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
- {
--	int i, r;
-+	unsigned i, j;
-+	int r;
- 
--	if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
--		kmem_cache_destroy(amdgpu_fence_slab);
- 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
- 		struct amdgpu_ring *ring = adev->rings[i];
- 
-@@ -460,8 +480,14 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
- 			       ring->fence_drv.irq_type);
- 		amd_sched_fini(&ring->sched);
- 		del_timer_sync(&ring->fence_drv.fallback_timer);
-+		for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
-+			fence_put(ring->fence_drv.fences[i]);
-+		kfree(ring->fence_drv.fences);
- 		ring->fence_drv.initialized = false;
- 	}
-+
-+	if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
-+		kmem_cache_destroy(amdgpu_fence_slab);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0400-drm-amdgpu-cleanup-amdgpu_fence_wait_empty-v2.patch b/common/recipes-kernel/linux/files/0400-drm-amdgpu-cleanup-amdgpu_fence_wait_empty-v2.patch
deleted file mode 100644
index c3c0b37f..00000000
--- a/common/recipes-kernel/linux/files/0400-drm-amdgpu-cleanup-amdgpu_fence_wait_empty-v2.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From cbd78a92b38da79b03133fd3d965ea2816cdade1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Sun, 13 Mar 2016 19:37:01 +0100
-Subject: [PATCH 0400/1110] drm/amdgpu: cleanup amdgpu_fence_wait_empty v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just wait for last fence instead of waiting for the sequence manually.
-
-v2: don't use amdgpu_sched_jobs for the mask
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 69 +++++++------------------------
- 1 file changed, 15 insertions(+), 54 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 44eac91..d5bdd96 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -228,57 +228,6 @@ static void amdgpu_fence_fallback(unsigned long arg)
- }
- 
- /**
-- * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
-- *
-- * @ring: ring the fence is associated with
-- * @seq: sequence number
-- *
-- * Check if the last signaled fence sequnce number is >= the requested
-- * sequence number (all asics).
-- * Returns true if the fence has signaled (current fence value
-- * is >= requested value) or false if it has not (current fence
-- * value is < the requested value.  Helper function for
-- * amdgpu_fence_signaled().
-- */
--static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
--{
--	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
--		return true;
--
--	/* poll new last sequence at least once */
--	amdgpu_fence_process(ring);
--	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
--		return true;
--
--	return false;
--}
--
--/*
-- * amdgpu_ring_wait_seq - wait for seq of the specific ring to signal
-- * @ring: ring to wait on for the seq number
-- * @seq: seq number wait for
-- *
-- * return value:
-- * 0: seq signaled, and gpu not hang
-- * -EINVAL: some paramter is not valid
-- */
--static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
--{
--	BUG_ON(!ring);
--	if (seq > ring->fence_drv.sync_seq)
--		return -EINVAL;
--
--	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
--		return 0;
--
--	amdgpu_fence_schedule_fallback(ring);
--	wait_event(ring->fence_drv.fence_queue,
--		   amdgpu_fence_seq_signaled(ring, seq));
--
--	return 0;
--}
--
--/**
-  * amdgpu_fence_wait_empty - wait for all fences to signal
-  *
-  * @adev: amdgpu device pointer
-@@ -286,16 +235,28 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
-  *
-  * Wait for all fences on the requested ring to signal (all asics).
-  * Returns 0 if the fences have passed, error for all other cases.
-- * Caller must hold ring lock.
-  */
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
- {
--	uint64_t seq = ring->fence_drv.sync_seq;
-+	uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
-+	struct fence *fence, **ptr;
-+	int r;
- 
- 	if (!seq)
- 		return 0;
- 
--	return amdgpu_fence_ring_wait_seq(ring, seq);
-+	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
-+	rcu_read_lock();
-+	fence = rcu_dereference(*ptr);
-+	if (!fence || !fence_get_rcu(fence)) {
-+		rcu_read_unlock();
-+		return 0;
-+	}
-+	rcu_read_unlock();
-+
-+	r = fence_wait(fence, false);
-+	fence_put(fence);
-+	return r;
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0401-drm-amdgpu-signal-fences-directly-in-amdgpu_fence_pr.patch b/common/recipes-kernel/linux/files/0401-drm-amdgpu-signal-fences-directly-in-amdgpu_fence_pr.patch
deleted file mode 100644
index 1c7c1158..00000000
--- a/common/recipes-kernel/linux/files/0401-drm-amdgpu-signal-fences-directly-in-amdgpu_fence_pr.patch
+++ /dev/null
@@ -1,223 +0,0 @@
-From b7071d88be433418c213ae57acff2e3ee9fe93d2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 14 Mar 2016 14:29:46 +0100
-Subject: [PATCH 0401/1110] drm/amdgpu: signal fences directly in
- amdgpu_fence_process
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Because of the scheduler we need to signal all fences immediately
-anyway, so try to avoid the waitqueue overhead.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 97 ++++++++++---------------------
- 2 files changed, 31 insertions(+), 68 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 43c948d..05a0ffb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -353,8 +353,8 @@ struct amdgpu_fence_driver {
- 	struct amdgpu_irq_src		*irq_src;
- 	unsigned			irq_type;
- 	struct timer_list		fallback_timer;
--	wait_queue_head_t		fence_queue;
- 	unsigned			num_fences_mask;
-+	spinlock_t			lock;
- 	struct fence			**fences;
- };
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index d5bdd96..c5980c4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -53,8 +53,6 @@ struct amdgpu_fence {
- 	/* RB, DMA, etc. */
- 	struct amdgpu_ring		*ring;
- 	uint64_t			seq;
--
--	wait_queue_t			fence_wake;
- };
- 
- static struct kmem_cache *amdgpu_fence_slab;
-@@ -124,7 +122,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- {
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_fence *fence;
--	struct fence *old, **ptr;
-+	struct fence **ptr;
- 	unsigned idx;
- 
- 	fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
-@@ -134,7 +132,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- 	fence->seq = ++ring->fence_drv.sync_seq;
- 	fence->ring = ring;
- 	fence_init(&fence->base, &amdgpu_fence_ops,
--		   &ring->fence_drv.fence_queue.lock,
-+		   &ring->fence_drv.lock,
- 		   adev->fence_context + ring->idx,
- 		   fence->seq);
- 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
-@@ -145,13 +143,10 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- 	/* This function can't be called concurrently anyway, otherwise
- 	 * emitting the fence would mess up the hardware ring buffer.
- 	 */
--	old = rcu_dereference_protected(*ptr, 1);
-+	BUG_ON(rcu_dereference_protected(*ptr, 1));
- 
- 	rcu_assign_pointer(*ptr, fence_get(&fence->base));
- 
--	BUG_ON(old && !fence_is_signaled(old));
--	fence_put(old);
--
- 	*f = &fence->base;
- 
- 	return 0;
-@@ -181,11 +176,12 @@ static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
-  */
- void amdgpu_fence_process(struct amdgpu_ring *ring)
- {
-+	struct amdgpu_fence_driver *drv = &ring->fence_drv;
- 	uint64_t seq, last_seq, last_emitted;
--	bool wake = false;
-+	int r;
- 
--	last_seq = atomic64_read(&ring->fence_drv.last_seq);
- 	do {
-+		last_seq = atomic64_read(&ring->fence_drv.last_seq);
- 		last_emitted = ring->fence_drv.sync_seq;
- 		seq = amdgpu_fence_read(ring);
- 		seq |= last_seq & 0xffffffff00000000LL;
-@@ -195,22 +191,32 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
- 		}
- 
- 		if (seq <= last_seq || seq > last_emitted)
--			break;
-+			return;
- 
--		/* If we loop over we don't want to return without
--		 * checking if a fence is signaled as it means that the
--		 * seq we just read is different from the previous on.
--		 */
--		wake = true;
--		last_seq = seq;
--
--	} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
-+	} while (atomic64_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
- 
- 	if (seq < last_emitted)
- 		amdgpu_fence_schedule_fallback(ring);
- 
--	if (wake)
--		wake_up_all(&ring->fence_drv.fence_queue);
-+	while (last_seq != seq) {
-+		struct fence *fence, **ptr;
-+
-+		ptr = &drv->fences[++last_seq & drv->num_fences_mask];
-+
-+		/* There is always exactly one thread signaling this fence slot */
-+		fence = rcu_dereference_protected(*ptr, 1);
-+		rcu_assign_pointer(*ptr, NULL);
-+
-+		BUG_ON(!fence);
-+
-+		r = fence_signal(fence);
-+		if (!r)
-+			FENCE_TRACE(fence, "signaled from irq context\n");
-+		else
-+			BUG();
-+
-+		fence_put(fence);
-+	}
- }
- 
- /**
-@@ -356,8 +362,8 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
- 	setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
- 		    (unsigned long)ring);
- 
--	init_waitqueue_head(&ring->fence_drv.fence_queue);
- 	ring->fence_drv.num_fences_mask = num_hw_submission - 1;
-+	spin_lock_init(&ring->fence_drv.lock);
- 	ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *),
- 					 GFP_KERNEL);
- 	if (!ring->fence_drv.fences)
-@@ -436,7 +442,6 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
- 			/* no need to trigger GPU reset as we are unloading */
- 			amdgpu_fence_driver_force_completion(adev);
- 		}
--		wake_up_all(&ring->fence_drv.fence_queue);
- 		amdgpu_irq_put(adev, ring->fence_drv.irq_src,
- 			       ring->fence_drv.irq_type);
- 		amd_sched_fini(&ring->sched);
-@@ -569,42 +574,6 @@ static bool amdgpu_fence_is_signaled(struct fence *f)
- }
- 
- /**
-- * amdgpu_fence_check_signaled - callback from fence_queue
-- *
-- * this function is called with fence_queue lock held, which is also used
-- * for the fence locking itself, so unlocked variants are used for
-- * fence_signal, and remove_wait_queue.
-- */
--static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
--{
--	struct amdgpu_fence *fence;
--	struct amdgpu_device *adev;
--	u64 seq;
--	int ret;
--
--	fence = container_of(wait, struct amdgpu_fence, fence_wake);
--	adev = fence->ring->adev;
--
--	/*
--	 * We cannot use amdgpu_fence_process here because we're already
--	 * in the waitqueue, in a call from wake_up_all.
--	 */
--	seq = atomic64_read(&fence->ring->fence_drv.last_seq);
--	if (seq >= fence->seq) {
--		ret = fence_signal_locked(&fence->base);
--		if (!ret)
--			FENCE_TRACE(&fence->base, "signaled from irq context\n");
--		else
--			FENCE_TRACE(&fence->base, "was already signaled\n");
--
--		__remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake);
--		fence_put(&fence->base);
--	} else
--		FENCE_TRACE(&fence->base, "pending\n");
--	return 0;
--}
--
--/**
-  * amdgpu_fence_enable_signaling - enable signalling on fence
-  * @fence: fence
-  *
-@@ -617,17 +586,11 @@ static bool amdgpu_fence_enable_signaling(struct fence *f)
- 	struct amdgpu_fence *fence = to_amdgpu_fence(f);
- 	struct amdgpu_ring *ring = fence->ring;
- 
--	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
--		return false;
--
--	fence->fence_wake.flags = 0;
--	fence->fence_wake.private = NULL;
--	fence->fence_wake.func = amdgpu_fence_check_signaled;
--	__add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake);
--	fence_get(f);
- 	if (!timer_pending(&ring->fence_drv.fallback_timer))
- 		amdgpu_fence_schedule_fallback(ring);
-+
- 	FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
-+
- 	return true;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0402-drm-amdgpu-drop-the-extra-fence-range-check-v2.patch b/common/recipes-kernel/linux/files/0402-drm-amdgpu-drop-the-extra-fence-range-check-v2.patch
deleted file mode 100644
index 703409f6..00000000
--- a/common/recipes-kernel/linux/files/0402-drm-amdgpu-drop-the-extra-fence-range-check-v2.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 552c4f34713282ab51ecd042ae79926d94d7c1ea Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 14 Mar 2016 14:49:33 +0100
-Subject: [PATCH 0402/1110] drm/amdgpu: drop the extra fence range check v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Amdgpu doesn't support using scratch registers for fences any more.
-So we won't see values like 0xdeadbeef as fence value any more.
-
-v2: reschedule timer even if no change detected
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index c5980c4..fa4eabe 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -190,9 +190,6 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
- 			seq |= last_emitted & 0xffffffff00000000LL;
- 		}
- 
--		if (seq <= last_seq || seq > last_emitted)
--			return;
--
- 	} while (atomic64_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
- 
- 	if (seq < last_emitted)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0403-drm-amdgpu-remove-amdgpu_fence_is_signaled.patch b/common/recipes-kernel/linux/files/0403-drm-amdgpu-remove-amdgpu_fence_is_signaled.patch
deleted file mode 100644
index 38ed059c..00000000
--- a/common/recipes-kernel/linux/files/0403-drm-amdgpu-remove-amdgpu_fence_is_signaled.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From c26ad03b21c26443b153c564d4afbeb092341772 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 14 Mar 2016 15:23:11 +0100
-Subject: [PATCH 0403/1110] drm/amdgpu: remove amdgpu_fence_is_signaled
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's just overhead to check the fence value
-when we signal them directly anyway.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 25 -------------------------
- 1 file changed, 25 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index fa4eabe..da9a155 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -547,30 +547,6 @@ static const char *amdgpu_fence_get_timeline_name(struct fence *f)
- }
- 
- /**
-- * amdgpu_fence_is_signaled - test if fence is signaled
-- *
-- * @f: fence to test
-- *
-- * Test the fence sequence number if it is already signaled. If it isn't
-- * signaled start fence processing. Returns True if the fence is signaled.
-- */
--static bool amdgpu_fence_is_signaled(struct fence *f)
--{
--	struct amdgpu_fence *fence = to_amdgpu_fence(f);
--	struct amdgpu_ring *ring = fence->ring;
--
--	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
--		return true;
--
--	amdgpu_fence_process(ring);
--
--	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
--		return true;
--
--	return false;
--}
--
--/**
-  * amdgpu_fence_enable_signaling - enable signalling on fence
-  * @fence: fence
-  *
-@@ -622,7 +598,6 @@ static const struct fence_ops amdgpu_fence_ops = {
- 	.get_driver_name = amdgpu_fence_get_driver_name,
- 	.get_timeline_name = amdgpu_fence_get_timeline_name,
- 	.enable_signaling = amdgpu_fence_enable_signaling,
--	.signaled = amdgpu_fence_is_signaled,
- 	.wait = fence_default_wait,
- 	.release = amdgpu_fence_release,
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0404-drm-amdgpu-switch-back-to-32bit-hw-fences-v2.patch b/common/recipes-kernel/linux/files/0404-drm-amdgpu-switch-back-to-32bit-hw-fences-v2.patch
deleted file mode 100644
index 5dca9545..00000000
--- a/common/recipes-kernel/linux/files/0404-drm-amdgpu-switch-back-to-32bit-hw-fences-v2.patch
+++ /dev/null
@@ -1,164 +0,0 @@
-From 1ba674acd69d4537e78b893d2de7cd9f24c7b146 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 14 Mar 2016 15:46:06 +0100
-Subject: [PATCH 0404/1110] drm/amdgpu: switch back to 32bit hw fences v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We don't need to extend them to 64bits any more, so avoid the extra overhead.
-
-v2: update commit message.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  4 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 49 ++++++++++++-------------------
- 2 files changed, 21 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 05a0ffb..f1b23e5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -347,8 +347,8 @@ struct amdgpu_fence_driver {
- 	uint64_t			gpu_addr;
- 	volatile uint32_t		*cpu_addr;
- 	/* sync_seq is protected by ring emission lock */
--	uint64_t			sync_seq;
--	atomic64_t			last_seq;
-+	uint32_t			sync_seq;
-+	atomic_t			last_seq;
- 	bool				initialized;
- 	struct amdgpu_irq_src		*irq_src;
- 	unsigned			irq_type;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index da9a155..4303b44 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -52,7 +52,6 @@ struct amdgpu_fence {
- 
- 	/* RB, DMA, etc. */
- 	struct amdgpu_ring		*ring;
--	uint64_t			seq;
- };
- 
- static struct kmem_cache *amdgpu_fence_slab;
-@@ -104,7 +103,7 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
- 	if (drv->cpu_addr)
- 		seq = le32_to_cpu(*drv->cpu_addr);
- 	else
--		seq = lower_32_bits(atomic64_read(&drv->last_seq));
-+		seq = atomic_read(&drv->last_seq);
- 
- 	return seq;
- }
-@@ -123,23 +122,22 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_fence *fence;
- 	struct fence **ptr;
--	unsigned idx;
-+	uint32_t seq;
- 
- 	fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
- 	if (fence == NULL)
- 		return -ENOMEM;
- 
--	fence->seq = ++ring->fence_drv.sync_seq;
-+	seq = ++ring->fence_drv.sync_seq;
- 	fence->ring = ring;
- 	fence_init(&fence->base, &amdgpu_fence_ops,
- 		   &ring->fence_drv.lock,
- 		   adev->fence_context + ring->idx,
--		   fence->seq);
-+		   seq);
- 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
--			       fence->seq, AMDGPU_FENCE_FLAG_INT);
-+			       seq, AMDGPU_FENCE_FLAG_INT);
- 
--	idx = fence->seq & ring->fence_drv.num_fences_mask;
--	ptr = &ring->fence_drv.fences[idx];
-+	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
- 	/* This function can't be called concurrently anyway, otherwise
- 	 * emitting the fence would mess up the hardware ring buffer.
- 	 */
-@@ -177,22 +175,16 @@ static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
- void amdgpu_fence_process(struct amdgpu_ring *ring)
- {
- 	struct amdgpu_fence_driver *drv = &ring->fence_drv;
--	uint64_t seq, last_seq, last_emitted;
-+	uint32_t seq, last_seq;
- 	int r;
- 
- 	do {
--		last_seq = atomic64_read(&ring->fence_drv.last_seq);
--		last_emitted = ring->fence_drv.sync_seq;
-+		last_seq = atomic_read(&ring->fence_drv.last_seq);
- 		seq = amdgpu_fence_read(ring);
--		seq |= last_seq & 0xffffffff00000000LL;
--		if (seq < last_seq) {
--			seq &= 0xffffffff;
--			seq |= last_emitted & 0xffffffff00000000LL;
--		}
- 
--	} while (atomic64_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
-+	} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
- 
--	if (seq < last_emitted)
-+	if (seq != ring->fence_drv.sync_seq)
- 		amdgpu_fence_schedule_fallback(ring);
- 
- 	while (last_seq != seq) {
-@@ -279,13 +271,10 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
- 	 * but it's ok to report slightly wrong fence count here.
- 	 */
- 	amdgpu_fence_process(ring);
--	emitted = ring->fence_drv.sync_seq
--		- atomic64_read(&ring->fence_drv.last_seq);
--	/* to avoid 32bits warp around */
--	if (emitted > 0x10000000)
--		emitted = 0x10000000;
--
--	return (unsigned)emitted;
-+	emitted = 0x100000000ull;
-+	emitted -= atomic_read(&ring->fence_drv.last_seq);
-+	emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
-+	return lower_32_bits(emitted);
- }
- 
- /**
-@@ -317,7 +306,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
- 		ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
- 		ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
- 	}
--	amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
-+	amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
- 	amdgpu_irq_get(adev, irq_src, irq_type);
- 
- 	ring->fence_drv.irq_src = irq_src;
-@@ -353,7 +342,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
- 	ring->fence_drv.cpu_addr = NULL;
- 	ring->fence_drv.gpu_addr = 0;
- 	ring->fence_drv.sync_seq = 0;
--	atomic64_set(&ring->fence_drv.last_seq, 0);
-+	atomic_set(&ring->fence_drv.last_seq, 0);
- 	ring->fence_drv.initialized = false;
- 
- 	setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
-@@ -621,9 +610,9 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
- 		amdgpu_fence_process(ring);
- 
- 		seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
--		seq_printf(m, "Last signaled fence 0x%016llx\n",
--			   (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
--		seq_printf(m, "Last emitted        0x%016llx\n",
-+		seq_printf(m, "Last signaled fence 0x%08x\n",
-+			   atomic_read(&ring->fence_drv.last_seq));
-+		seq_printf(m, "Last emitted        0x%08x\n",
- 			   ring->fence_drv.sync_seq);
- 	}
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0405-drm-amd-powerplay-add-uvd-vce-dpm-enabling-flag-to-f.patch b/common/recipes-kernel/linux/files/0405-drm-amd-powerplay-add-uvd-vce-dpm-enabling-flag-to-f.patch
deleted file mode 100644
index 33a301f6..00000000
--- a/common/recipes-kernel/linux/files/0405-drm-amd-powerplay-add-uvd-vce-dpm-enabling-flag-to-f.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From a1e21ac5e35c037678c980c2b50c72e6bdec7a7b Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 15 Mar 2016 17:00:22 -0400
-Subject: [PATCH 0405/1110] drm/amd/powerplay: add uvd/vce dpm enabling flag to
- fix the performance issue for CZ
-
-Set the UVD and VCE DPM flags otherwise UVD and VCE DPM won't get enabled.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Cc: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 727d5c9..5682490 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -241,6 +241,11 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_DynamicUVDState);
- 
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_UVDDPM);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_VCEDPM);
-+
- 	cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
- 	cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
- 	cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0406-drm-amdgpu-give-a-fence-param-to-ib_free.patch b/common/recipes-kernel/linux/files/0406-drm-amdgpu-give-a-fence-param-to-ib_free.patch
deleted file mode 100644
index acee1e24..00000000
--- a/common/recipes-kernel/linux/files/0406-drm-amdgpu-give-a-fence-param-to-ib_free.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From 80293a2c74d271ec9109905e7426ef10630d9812 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 17 Mar 2016 10:47:07 +0800
-Subject: [PATCH 0406/1110] drm/amdgpu: give a fence param to ib_free
-
-thus amdgpu_ib_free() can hook sched fence to SA manager
-in later patches.
-
-BTW:
-for amdgpu_free_job(), it should only fence_put() the
-fence of the last ib once, so fix it as well in this patch.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 5 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 ++-
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c   | 2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 4 ++--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  | 2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  | 2 +-
- 8 files changed, 12 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index f1b23e5..940edb9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1142,7 +1142,7 @@ struct amdgpu_gfx {
- 
- int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 		  unsigned size, struct amdgpu_ib *ib);
--void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
-+void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
-                        struct amdgpu_ib *ib, struct fence *last_vm_update,
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index ddaffa4..5942daa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -85,12 +85,13 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-  *
-  * @adev: amdgpu_device pointer
-  * @ib: IB object to free
-+ * @f: the fence SA bo need wait on for the ib alloation
-  *
-  * Free an IB (all asics).
-  */
--void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
-+void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f)
- {
--	amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence);
-+	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
- 	fence_put(ib->fence);
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index a3baec9..66ccc7e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -72,7 +72,8 @@ void amdgpu_job_free(struct amdgpu_job *job)
-        unsigned i;
- 
-        for (i = 0; i < job->num_ibs; ++i)
--               amdgpu_ib_free(job->adev, &job->ibs[i]);
-+               amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, job->ibs[job->num_ibs - 1].fence);
-+       fence_put(job->ibs[job->num_ibs - 1].fence);
- 
-        amdgpu_bo_unref(&job->uf.bo);
-        amdgpu_sync_free(&job->sync);
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 363d4f6..08f509a 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -669,7 +669,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 
- err1:
- 	fence_put(f);
--	amdgpu_ib_free(adev, &ib);
-+	amdgpu_ib_free(adev, &ib, NULL);
- err0:
- 	amdgpu_wb_free(adev, index);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 87d439a..ef0e6b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2163,7 +2163,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 
- err2:
- 	fence_put(f);
--	amdgpu_ib_free(adev, &ib);
-+	amdgpu_ib_free(adev, &ib, NULL);
- err1:
- 	amdgpu_gfx_scratch_free(adev, scratch);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 56dd745..4d329e1 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -732,7 +732,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	}
- err2:
- 	fence_put(f);
--	amdgpu_ib_free(adev, &ib);
-+	amdgpu_ib_free(adev, &ib, NULL);
- err1:
- 	amdgpu_gfx_scratch_free(adev, scratch);
- 	return r;
-@@ -1289,7 +1289,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 
- fail:
- 	fence_put(f);
--	amdgpu_ib_free(adev, &ib);
-+	amdgpu_ib_free(adev, &ib, NULL);
- 
- 	return r;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index b96ec4e..242a363 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -727,7 +727,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 
- err1:
- 	fence_put(f);
--	amdgpu_ib_free(adev, &ib);
-+	amdgpu_ib_free(adev, &ib, NULL);
- err0:
- 	amdgpu_wb_free(adev, index);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 4d1c0a3..dde4125 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -878,7 +878,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	}
- err1:
- 	fence_put(f);
--	amdgpu_ib_free(adev, &ib);
-+	amdgpu_ib_free(adev, &ib, NULL);
- err0:
- 	amdgpu_wb_free(adev, index);
- 	return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0407-drm-amdgpu-move-ib.fence-to-job.fence.patch b/common/recipes-kernel/linux/files/0407-drm-amdgpu-move-ib.fence-to-job.fence.patch
deleted file mode 100644
index 16d3fa7f..00000000
--- a/common/recipes-kernel/linux/files/0407-drm-amdgpu-move-ib.fence-to-job.fence.patch
+++ /dev/null
@@ -1,198 +0,0 @@
-From e72596089d61f9338ebb182de4ffff8ebe829ebc Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 17 Mar 2016 13:48:13 +0800
-Subject: [PATCH 0407/1110] drm/amdgpu: move ib.fence to job.fence
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 +++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 1 +
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c   | 1 +
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   | 1 +
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 2 ++
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  | 1 +
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  | 1 +
- 10 files changed, 15 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 940edb9..3ff6b3e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -722,7 +722,6 @@ struct amdgpu_ib {
- 	uint32_t			length_dw;
- 	uint64_t			gpu_addr;
- 	uint32_t			*ptr;
--        struct fence                    *fence;
- 	struct amdgpu_user_fence        *user;
- 	struct amdgpu_vm		*vm;
-         unsigned                        vm_id;
-@@ -1203,6 +1202,7 @@ struct amdgpu_job {
-         struct amdgpu_ring      *ring;
-         struct amdgpu_sync      sync;
- 	struct amdgpu_ib	*ibs;
-+        struct fence            *fence; /* the hw fence */
- 	uint32_t		num_ibs;
- 	void			*owner;
- 	struct amdgpu_user_fence uf;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 5942daa..58b051c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -92,7 +92,6 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f)
- {
- 	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
--	fence_put(ib->fence);
- }
- 
- /**
-@@ -123,6 +122,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 	struct amdgpu_ib *ib = &ibs[0];
- 	struct amdgpu_ctx *ctx, *old_ctx;
- 	struct amdgpu_vm *vm;
-+	struct fence *hwf;
- 	unsigned i;
- 	int r = 0;
- 
-@@ -179,7 +179,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 			amdgpu_ring_emit_hdp_invalidate(ring);
- 	}
- 
--	r = amdgpu_fence_emit(ring, &ib->fence);
-+	r = amdgpu_fence_emit(ring, &hwf);
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
- 		ring->current_ctx = old_ctx;
-@@ -197,7 +197,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
- 
--        *f = fence_get(ib->fence);	
-+        *f = fence_get(hwf);
- 
- 	amdgpu_ring_commit(ring);
- 	return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index 66ccc7e..ddf1ed6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -72,8 +72,8 @@ void amdgpu_job_free(struct amdgpu_job *job)
-        unsigned i;
- 
-        for (i = 0; i < job->num_ibs; ++i)
--               amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, job->ibs[job->num_ibs - 1].fence);
--       fence_put(job->ibs[job->num_ibs - 1].fence);
-+               amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, job->fence);
-+       fence_put(job->fence);
- 
-        amdgpu_bo_unref(&job->uf.bo);
-        amdgpu_sync_free(&job->sync);
-@@ -157,6 +157,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
-        }
- 
- err:
-+       job->fence = fence;
-        amdgpu_job_free(job);
-        return fence;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index aa8bdd4..324bb32 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -899,6 +899,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 						 &f);
-         if (direct) {
-                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+                job->fence = f;
-                 if (r)
-                         goto err_free;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 125dba2..923ee5a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -443,6 +443,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
-         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+                 job->fence = f;
- 	if (r)
- 		goto err;
-        
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 08f509a..dd0cc1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -670,6 +670,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- err1:
- 	fence_put(f);
- 	amdgpu_ib_free(adev, &ib, NULL);
-+	fence_put(f);
- err0:
- 	amdgpu_wb_free(adev, index);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index ef0e6b1..177eb78 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2164,6 +2164,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- err2:
- 	fence_put(f);
- 	amdgpu_ib_free(adev, &ib, NULL);
-+	fence_put(f);
- err1:
- 	amdgpu_gfx_scratch_free(adev, scratch);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 4d329e1..066f349 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -733,6 +733,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- err2:
- 	fence_put(f);
- 	amdgpu_ib_free(adev, &ib, NULL);
-+	fence_put(f);
- err1:
- 	amdgpu_gfx_scratch_free(adev, scratch);
- 	return r;
-@@ -1290,6 +1291,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- fail:
- 	fence_put(f);
- 	amdgpu_ib_free(adev, &ib, NULL);
-+	fence_put(f);
- 
- 	return r;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 242a363..96b63d9 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -728,6 +728,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- err1:
- 	fence_put(f);
- 	amdgpu_ib_free(adev, &ib, NULL);
-+	fence_put(f);
- err0:
- 	amdgpu_wb_free(adev, index);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index dde4125..5845dde 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -879,6 +879,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- err1:
- 	fence_put(f);
- 	amdgpu_ib_free(adev, &ib, NULL);
-+	fence_put(f);
- err0:
- 	amdgpu_wb_free(adev, index);
- 	return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0408-drm-amdgpu-use-sched-fence-if-possible.patch b/common/recipes-kernel/linux/files/0408-drm-amdgpu-use-sched-fence-if-possible.patch
deleted file mode 100644
index 5a9abfec..00000000
--- a/common/recipes-kernel/linux/files/0408-drm-amdgpu-use-sched-fence-if-possible.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 2389be2b66ea81b9af93ba6c1b3652045c27b42e Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 17 Mar 2016 13:57:09 +0800
-Subject: [PATCH 0408/1110] drm/amdgpu: use sched fence if possible
-
-when preemption feature lands, the SA bo should rely on sched
-fence, because hw fence will be invalid after its job preempted
-or skipped.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index ddf1ed6..8a2d54a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -70,9 +70,12 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
- void amdgpu_job_free(struct amdgpu_job *job)
- {
-        unsigned i;
-+       struct fence *f;
-+       /* use sched fence if available */
-+       f = (job->base.s_fence)? &job->base.s_fence->base : job->fence;
- 
-        for (i = 0; i < job->num_ibs; ++i)
--               amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, job->fence);
-+               amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, f);
-        fence_put(job->fence);
- 
-        amdgpu_bo_unref(&job->uf.bo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0409-drm-amd-powerplay-show-uvd-vce-power-gate-info-for-f.patch b/common/recipes-kernel/linux/files/0409-drm-amd-powerplay-show-uvd-vce-power-gate-info-for-f.patch
deleted file mode 100644
index 0b0d8e64..00000000
--- a/common/recipes-kernel/linux/files/0409-drm-amd-powerplay-show-uvd-vce-power-gate-info-for-f.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 0808f1693925fb6c5719868c873d2f7c57927291 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 1 Mar 2016 17:02:51 +0800
-Subject: [PATCH 0409/1110] drm/amd/powerplay: show uvd/vce power gate info for
- fiji
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 5cca2ec..51dedf8 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -4275,7 +4275,6 @@ static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
- 	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
- 		dpm_table->mclk_table.dpm_levels
- 			[dpm_table->mclk_table.count - 1].value = mclk;
--
- 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				PHM_PlatformCaps_OD6PlusinACSupport) ||
- 			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-@@ -4886,6 +4885,10 @@ static void fiji_print_current_perforce_level(
- 	activity_percent >>= 8;
- 
- 	seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
-+
-+	seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
-+
-+	seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
- }
- 
- static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0410-drm-amd-powerplay-show-uvd-vce-power-gate-enablement.patch b/common/recipes-kernel/linux/files/0410-drm-amd-powerplay-show-uvd-vce-power-gate-enablement.patch
deleted file mode 100644
index e7939809..00000000
--- a/common/recipes-kernel/linux/files/0410-drm-amd-powerplay-show-uvd-vce-power-gate-enablement.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From c1c7bbc448bef6e5f198e66356148a52b078a7ac Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 1 Mar 2016 17:04:12 +0800
-Subject: [PATCH 0410/1110] drm/amd/powerplay: show uvd/vce power gate
- enablement for tonga.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index aec4f83..0d5d837 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -5185,7 +5185,6 @@ tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n", mclk/100, sclk/100);
- 
--
- 	offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
- 	activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
- 	activity_percent += 0x80;
-@@ -5193,6 +5192,9 @@ tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- 
- 	seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
- 
-+	seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
-+
-+	seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
- }
- 
- static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0411-drm-amdgpu-removing-BO_VAs-shouldn-t-be-interruptibl.patch b/common/recipes-kernel/linux/files/0411-drm-amdgpu-removing-BO_VAs-shouldn-t-be-interruptibl.patch
deleted file mode 100644
index 73a4953f..00000000
--- a/common/recipes-kernel/linux/files/0411-drm-amdgpu-removing-BO_VAs-shouldn-t-be-interruptibl.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 24c5ef3421e327723bf545d458821b758d3fd0fe Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 17 Mar 2016 17:14:10 +0100
-Subject: [PATCH 0411/1110] drm/amdgpu: removing BO_VAs shouldn't be
- interruptible
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index e9bf5a5..a095776 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -161,7 +161,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
- 
- 	amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
- 
--	r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
-+	r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
- 	if (r) {
- 		dev_err(adev->dev, "leaking bo va because "
- 			"we fail to reserve bo (%d)\n", r);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0412-drm-amdgpu-gfx7-add-MTYPE-definition.patch b/common/recipes-kernel/linux/files/0412-drm-amdgpu-gfx7-add-MTYPE-definition.patch
deleted file mode 100644
index ddb67942..00000000
--- a/common/recipes-kernel/linux/files/0412-drm-amdgpu-gfx7-add-MTYPE-definition.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From c40eaf1b92a5dbf10b5591e6095fc99989af28ca Mon Sep 17 00:00:00 2001
-From: Flora Cui <flora.cui@amd.com>
-Date: Mon, 12 Oct 2015 10:12:03 +0800
-Subject: [PATCH 0412/1110] drm/amdgpu/gfx7: add MTYPE definition
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
-index 9d4347d..dfe7879 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
-@@ -6225,6 +6225,12 @@ typedef enum TCC_CACHE_POLICIES {
- 	TCC_CACHE_POLICY_STREAM                          = 0x1,
- 	TCC_CACHE_POLICY_BYPASS                          = 0x2,
- } TCC_CACHE_POLICIES;
-+typedef enum MTYPE {
-+	MTYPE_NC_NV                                      = 0x0,
-+	MTYPE_NC                                         = 0x1,
-+	MTYPE_CC                                         = 0x2,
-+	MTYPE_UC                                         = 0x3,
-+} MTYPE;
- typedef enum PERFMON_COUNTER_MODE {
- 	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
- 	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0413-drm-amdgpu-release_pages-requires-linux-pagemap.h.patch b/common/recipes-kernel/linux/files/0413-drm-amdgpu-release_pages-requires-linux-pagemap.h.patch
deleted file mode 100644
index e6dd35b8..00000000
--- a/common/recipes-kernel/linux/files/0413-drm-amdgpu-release_pages-requires-linux-pagemap.h.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From b528dbee3e2fa87e5302d0279eda4ae161b0503b Mon Sep 17 00:00:00 2001
-From: Stephen Rothwell <sfr@canb.auug.org.au>
-Date: Thu, 17 Mar 2016 15:30:49 +1100
-Subject: [PATCH 0413/1110] drm/amdgpu: release_pages requires linux/pagemap.h
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
-Reviewed-by: Christian König <christian.koenig@amd.com.
-Signed-off-by: Dave Airlie <airlied@redhat.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 62027c6..170b8da 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -25,6 +25,7 @@
-  *    Jerome Glisse <glisse@freedesktop.org>
-  */
- #include <linux/list_sort.h>
-+#include <linux/pagemap.h>
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
- #include "amdgpu.h"
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index a095776..f5d53b3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -26,6 +26,7 @@
-  *          Jerome Glisse
-  */
- #include <linux/ktime.h>
-+#include <linux/pagemap.h>
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
- #include "amdgpu.h"
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0414-drm-amd-powerplay-fix-memory-leak-of-tdp_table.patch b/common/recipes-kernel/linux/files/0414-drm-amd-powerplay-fix-memory-leak-of-tdp_table.patch
deleted file mode 100644
index 04a00ea1..00000000
--- a/common/recipes-kernel/linux/files/0414-drm-amd-powerplay-fix-memory-leak-of-tdp_table.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 5f632a584a0918642dee7227c19e27fce2d95f9e Mon Sep 17 00:00:00 2001
-From: Colin Ian King <colin.king@canonical.com>
-Date: Fri, 18 Mar 2016 16:47:29 +0000
-Subject: [PATCH 0414/1110] drm/amd/powerplay: fix memory leak of tdp_table
-
-tdp_table is being leaked on failed allocations of
-hwmgr->dyn_state.cac_dtp_table. kfree tdp_table on the error
-return path to fix the leak.
-
-Signed-off-by: Colin Ian King <colin.king@canonical.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index 34f4bef..b156481 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -512,8 +512,10 @@ static int get_cac_tdp_table(
- 
- 	hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
- 
--	if (NULL == hwmgr->dyn_state.cac_dtp_table)
-+	if (NULL == hwmgr->dyn_state.cac_dtp_table) {
-+		kfree(tdp_table);
- 		return -ENOMEM;
-+	}
- 
- 	memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0415-drm-amdgpu-clean-up-path-handling-for-powerplay.patch b/common/recipes-kernel/linux/files/0415-drm-amdgpu-clean-up-path-handling-for-powerplay.patch
deleted file mode 100644
index afc565e0..00000000
--- a/common/recipes-kernel/linux/files/0415-drm-amdgpu-clean-up-path-handling-for-powerplay.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 3ce204ca3cdf19b1fc5c4b77b0ffdcbe6946fedb Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 15 Mar 2016 11:22:27 -0400
-Subject: [PATCH 0415/1110] drm/amdgpu: clean up path handling for powerplay
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Use $(FULL_AMD_PATH) like everything else.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/Makefile | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
-index e195bf5..043e6eb 100644
---- a/drivers/gpu/drm/amd/powerplay/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/Makefile
-@@ -1,17 +1,17 @@
- 
- subdir-ccflags-y += -Iinclude/drm  \
--		-Idrivers/gpu/drm/amd/powerplay/inc/  \
--		-Idrivers/gpu/drm/amd/include/asic_reg  \
--		-Idrivers/gpu/drm/amd/include  \
--		-Idrivers/gpu/drm/amd/powerplay/smumgr\
--		-Idrivers/gpu/drm/amd/powerplay/hwmgr \
--		-Idrivers/gpu/drm/amd/powerplay/eventmgr
-+		-I$(FULL_AMD_PATH)/powerplay/inc/  \
-+		-I$(FULL_AMD_PATH)/include/asic_reg  \
-+		-I$(FULL_AMD_PATH)/include  \
-+		-I$(FULL_AMD_PATH)/powerplay/smumgr\
-+		-I$(FULL_AMD_PATH)/powerplay/hwmgr \
-+		-I$(FULL_AMD_PATH)/powerplay/eventmgr
- 
- AMD_PP_PATH = ../powerplay
- 
- PP_LIBS = smumgr hwmgr eventmgr
- 
--AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix drivers/gpu/drm/amd/powerplay/,$(PP_LIBS)))
-+AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(PP_LIBS)))
- 
- include $(AMD_POWERPLAY)
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0416-drm-amdgpu-Revert-remove-the-userptr-rmn-lock.patch b/common/recipes-kernel/linux/files/0416-drm-amdgpu-Revert-remove-the-userptr-rmn-lock.patch
deleted file mode 100644
index bf7f3132..00000000
--- a/common/recipes-kernel/linux/files/0416-drm-amdgpu-Revert-remove-the-userptr-rmn-lock.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From 75943799af069bd6d8e1a603250a49089ee8d6ff Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 18 Mar 2016 19:29:51 +0100
-Subject: [PATCH 0416/1110] drm/amdgpu: Revert "remove the userptr rmn->lock"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This reverts commit c02196834456f2d5fad334088b70e98ce4967c34.
-
-In the meantime we moved get_user_pages() outside of the reservation lock,
-so that shouldn't be an issue any more
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 22 ++++++++++++++--------
- 1 file changed, 14 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-index d7ec9bd..c47f222 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-@@ -48,7 +48,8 @@ struct amdgpu_mn {
- 	/* protected by adev->mn_lock */
- 	struct hlist_node	node;
- 
--	/* objects protected by mm->mmap_sem */
-+	/* objects protected by lock */
-+	struct mutex		lock;
- 	struct rb_root		objects;
- };
- 
-@@ -72,7 +73,7 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 	struct amdgpu_bo *bo, *next_bo;
- 
- 	mutex_lock(&adev->mn_lock);
--	down_write(&rmn->mm->mmap_sem);
-+	mutex_lock(&rmn->lock);
- 	hash_del(&rmn->node);
- 	rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects,
- 					     it.rb) {
-@@ -82,7 +83,7 @@ static void amdgpu_mn_destroy(struct work_struct *work)
- 		}
- 		kfree(node);
- 	}
--	up_write(&rmn->mm->mmap_sem);
-+	mutex_unlock(&rmn->lock);
- 	mutex_unlock(&adev->mn_lock);
- 	mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
- 	kfree(rmn);
-@@ -126,6 +127,8 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
- 	/* notification is exclusive, but interval is inclusive */
- 	end -= 1;
- 
-+	mutex_lock(&rmn->lock);
-+
- 	it = interval_tree_iter_first(&rmn->objects, start, end);
- 	while (it) {
- 		struct amdgpu_mn_node *node;
-@@ -160,6 +163,8 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
- 			amdgpu_bo_unreserve(bo);
- 		}
- 	}
-+
-+	mutex_unlock(&rmn->lock);
- }
- 
- static const struct mmu_notifier_ops amdgpu_mn_ops = {
-@@ -196,6 +201,7 @@ static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
- 	rmn->adev = adev;
- 	rmn->mm = mm;
- 	rmn->mn.ops = &amdgpu_mn_ops;
-+	mutex_init(&rmn->lock);
- 	rmn->objects = RB_ROOT;
- 
- 	r = __mmu_notifier_register(&rmn->mn, mm);
-@@ -242,7 +248,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- 
- 	INIT_LIST_HEAD(&bos);
- 
--	down_write(&rmn->mm->mmap_sem);
-+	mutex_lock(&rmn->lock);
- 
- 	while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
- 		kfree(node);
-@@ -256,7 +262,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- 	if (!node) {
- 		node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
- 		if (!node) {
--			up_write(&rmn->mm->mmap_sem);
-+			mutex_unlock(&rmn->lock);
- 			return -ENOMEM;
- 		}
- 	}
-@@ -271,7 +277,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
- 
- 	interval_tree_insert(&node->it, &rmn->objects);
- 
--	up_write(&rmn->mm->mmap_sem);
-+	mutex_unlock(&rmn->lock);
- 
- 	return 0;
- }
-@@ -297,7 +303,7 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
- 		return;
- 	}
- 
--	down_write(&rmn->mm->mmap_sem);
-+	mutex_lock(&rmn->lock);
- 
- 	/* save the next list entry for later */
- 	head = bo->mn_list.next;
-@@ -312,6 +318,6 @@ void amdgpu_mn_unregister(struct amdgpu_bo *bo)
- 		kfree(node);
- 	}
- 
--	up_write(&rmn->mm->mmap_sem);
-+	mutex_unlock(&rmn->lock);
- 	mutex_unlock(&adev->mn_lock);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0417-drm-amdgpu-add-invalidate_page-callback-for-userptrs.patch b/common/recipes-kernel/linux/files/0417-drm-amdgpu-add-invalidate_page-callback-for-userptrs.patch
deleted file mode 100644
index c89b9592..00000000
--- a/common/recipes-kernel/linux/files/0417-drm-amdgpu-add-invalidate_page-callback-for-userptrs.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From e3eacee1dc6e60e7197872ccd0dd3d4468c417d6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 18 Mar 2016 19:29:52 +0100
-Subject: [PATCH 0417/1110] drm/amdgpu: add invalidate_page callback for
- userptrs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Otherwise we can run into problems with the writeback code.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 98 +++++++++++++++++++++++++---------
- 1 file changed, 72 insertions(+), 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-index c47f222..9f4a45c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
-@@ -106,6 +106,76 @@ static void amdgpu_mn_release(struct mmu_notifier *mn,
- }
- 
- /**
-+ * amdgpu_mn_invalidate_node - unmap all BOs of a node
-+ *
-+ * @node: the node with the BOs to unmap
-+ *
-+ * We block for all BOs and unmap them by move them
-+ * into system domain again.
-+ */
-+static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
-+				      unsigned long start,
-+				      unsigned long end)
-+{
-+	struct amdgpu_bo *bo;
-+	long r;
-+
-+	list_for_each_entry(bo, &node->bos, mn_list) {
-+
-+		if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
-+			continue;
-+
-+		r = amdgpu_bo_reserve(bo, true);
-+		if (r) {
-+			DRM_ERROR("(%ld) failed to reserve user bo\n", r);
-+			continue;
-+		}
-+
-+		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
-+			true, false, MAX_SCHEDULE_TIMEOUT);
-+		if (r <= 0)
-+			DRM_ERROR("(%ld) failed to wait for user bo\n", r);
-+
-+		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
-+		r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
-+		if (r)
-+			DRM_ERROR("(%ld) failed to validate user bo\n", r);
-+
-+		amdgpu_bo_unreserve(bo);
-+	}
-+}
-+
-+/**
-+ * amdgpu_mn_invalidate_page - callback to notify about mm change
-+ *
-+ * @mn: our notifier
-+ * @mn: the mm this callback is about
-+ * @address: address of invalidate page
-+ *
-+ * Invalidation of a single page. Blocks for all BOs mapping it
-+ * and unmap them by move them into system domain again.
-+ */
-+static void amdgpu_mn_invalidate_page(struct mmu_notifier *mn,
-+				      struct mm_struct *mm,
-+				      unsigned long address)
-+{
-+	struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
-+	struct interval_tree_node *it;
-+
-+	mutex_lock(&rmn->lock);
-+
-+	it = interval_tree_iter_first(&rmn->objects, address, address);
-+	if (it) {
-+		struct amdgpu_mn_node *node;
-+
-+		node = container_of(it, struct amdgpu_mn_node, it);
-+		amdgpu_mn_invalidate_node(node, address, address);
-+	}
-+
-+	mutex_unlock(&rmn->lock);
-+}
-+
-+/**
-  * amdgpu_mn_invalidate_range_start - callback to notify about mm change
-  *
-  * @mn: our notifier
-@@ -132,36 +202,11 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
- 	it = interval_tree_iter_first(&rmn->objects, start, end);
- 	while (it) {
- 		struct amdgpu_mn_node *node;
--		struct amdgpu_bo *bo;
--		long r;
- 
- 		node = container_of(it, struct amdgpu_mn_node, it);
- 		it = interval_tree_iter_next(it, start, end);
- 
--		list_for_each_entry(bo, &node->bos, mn_list) {
--
--			if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start,
--							  end))
--				continue;
--
--			r = amdgpu_bo_reserve(bo, true);
--			if (r) {
--				DRM_ERROR("(%ld) failed to reserve user bo\n", r);
--				continue;
--			}
--
--			r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
--				true, false, MAX_SCHEDULE_TIMEOUT);
--			if (r <= 0)
--				DRM_ERROR("(%ld) failed to wait for user bo\n", r);
--
--			amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
--			r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
--			if (r)
--				DRM_ERROR("(%ld) failed to validate user bo\n", r);
--
--			amdgpu_bo_unreserve(bo);
--		}
-+		amdgpu_mn_invalidate_node(node, start, end);
- 	}
- 
- 	mutex_unlock(&rmn->lock);
-@@ -169,6 +214,7 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
- 
- static const struct mmu_notifier_ops amdgpu_mn_ops = {
- 	.release = amdgpu_mn_release,
-+	.invalidate_page = amdgpu_mn_invalidate_page,
- 	.invalidate_range_start = amdgpu_mn_invalidate_range_start,
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0418-drm-amd-Beef-up-ACP-Kconfig-menu-text.patch b/common/recipes-kernel/linux/files/0418-drm-amd-Beef-up-ACP-Kconfig-menu-text.patch
deleted file mode 100644
index f27f8d80..00000000
--- a/common/recipes-kernel/linux/files/0418-drm-amd-Beef-up-ACP-Kconfig-menu-text.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 637b547bfd59c65c4953741989bf11201fbcab38 Mon Sep 17 00:00:00 2001
-From: Borislav Petkov <bp@suse.de>
-Date: Fri, 25 Mar 2016 12:27:42 +0100
-Subject: [PATCH 0418/1110] drm/amd: Beef up ACP Kconfig menu text
-
-The current "text" needs a user to use a crystal ball in order to find
-out what this ACP thing is.
-
-Use the text from
-
-  a8fe58cec351 ("drm/amd: add ACP driver support")
-
-to make it a bit more understandable to the rest of the world.
-
-Signed-off-by: Borislav Petkov <bp@suse.de>
-Cc: Alex Deucher <alexander.deucher@amd.com>
-Cc: Chunming Zhou <david1.zhou@amd.com>
-Cc: Jammy Zhou <Jammy.Zhou@amd.com>
-Cc: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
-Cc: Murali Krishna Vemuri <murali-krishna.vemuri@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/acp/Kconfig | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
-index 0f734ee..ca77ec1 100644
---- a/drivers/gpu/drm/amd/acp/Kconfig
-+++ b/drivers/gpu/drm/amd/acp/Kconfig
-@@ -1,10 +1,14 @@
--menu "ACP Configuration"
-+menu "ACP (Audio CoProcessor) Configuration"
- 
- config DRM_AMD_ACP
--       bool "Enable ACP IP support"
-+       bool "Enable AMD Audio CoProcessor IP support"
-        select MFD_CORE
-        select PM_GENERIC_DOMAINS if PM
-        help
- 	Choose this option to enable ACP IP support for AMD SOCs.
-+	This adds the ACP (Audio CoProcessor) IP driver and wires
-+	it up into the amdgpu driver.  The ACP block provides the DMA
-+	engine for the i2s-based ALSA driver. It is required for audio
-+	on APUs which utilize an i2s codec.
- 
- endmenu
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0419-drm-amdgpu-Don-t-move-pinned-BOs.patch b/common/recipes-kernel/linux/files/0419-drm-amdgpu-Don-t-move-pinned-BOs.patch
deleted file mode 100644
index f7c498de..00000000
--- a/common/recipes-kernel/linux/files/0419-drm-amdgpu-Don-t-move-pinned-BOs.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 0c0ee0cd5953041ae70900845bba5e601e5e4031 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com>
-Date: Mon, 28 Mar 2016 12:53:02 +0900
-Subject: [PATCH 0419/1110] drm/amdgpu: Don't move pinned BOs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The purpose of pinning is to prevent a buffer from moving.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Tested-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 6 ++++++
- 2 files changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index 7700867..95d35c2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -609,6 +609,10 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
- 	if ((offset + size) <= adev->mc.visible_vram_size)
- 		return 0;
- 
-+	/* Can't move a pinned BO to visible VRAM */
-+	if (abo->pin_count > 0)
-+		return -EINVAL;
-+
- 	/* hurrah the memory is not visible ! */
- 	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
- 	lpfn =	adev->mc.visible_vram_size >> PAGE_SHIFT;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 6bbd395..fbc3c2b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -384,9 +384,15 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo,
- 			struct ttm_mem_reg *new_mem)
- {
- 	struct amdgpu_device *adev;
-+	struct amdgpu_bo *abo;
- 	struct ttm_mem_reg *old_mem = &bo->mem;
- 	int r;
- 
-+	/* Can't move a pinned BO */
-+	abo = container_of(bo, struct amdgpu_bo, tbo);
-+	if (WARN_ON_ONCE(abo->pin_count > 0))
-+		return -EINVAL;
-+
- 	adev = amdgpu_get_adev(bo->bdev);
- 	if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
- 		amdgpu_move_null(bo, new_mem);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0420-drm-amd-powerplay-fix-segment-fault-issue-in-multi-d.patch b/common/recipes-kernel/linux/files/0420-drm-amd-powerplay-fix-segment-fault-issue-in-multi-d.patch
deleted file mode 100644
index 73dff28b..00000000
--- a/common/recipes-kernel/linux/files/0420-drm-amd-powerplay-fix-segment-fault-issue-in-multi-d.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 3aa26a86682b97b5fe9f1438f556650f864d6951 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 13:21:59 +0800
-Subject: [PATCH 0420/1110] drm/amd/powerplay: fix segment fault issue in
- multi-display case.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 7a4b101..75cb5b9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -816,10 +816,13 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
- 	struct drm_device *ddev = adev->ddev;
- 	struct drm_crtc *crtc;
- 	uint32_t line_time_us, vblank_lines;
-+	struct cgs_mode_info *mode_info;
- 
- 	if (info == NULL)
- 		return -EINVAL;
- 
-+	mode_info = info->mode_info;
-+
- 	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
- 		list_for_each_entry(crtc,
- 				&ddev->mode_config.crtc_list, head) {
-@@ -828,7 +831,7 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
- 				info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
- 				info->display_count++;
- 			}
--			if (info->mode_info != NULL &&
-+			if (mode_info != NULL &&
- 				crtc->enabled && amdgpu_crtc->enabled &&
- 				amdgpu_crtc->hw_mode.clock) {
- 				line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
-@@ -836,10 +839,10 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
- 				vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
- 							amdgpu_crtc->hw_mode.crtc_vdisplay +
- 							(amdgpu_crtc->v_border * 2);
--				info->mode_info->vblank_time_us = vblank_lines * line_time_us;
--				info->mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
--				info->mode_info->ref_clock = adev->clock.spll.reference_freq;
--				info->mode_info++;
-+				mode_info->vblank_time_us = vblank_lines * line_time_us;
-+				mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
-+				mode_info->ref_clock = adev->clock.spll.reference_freq;
-+				mode_info = NULL;
- 			}
- 		}
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0421-drm-amdgpu-add-an-cgs-interface-to-notify-amdgpu-the.patch b/common/recipes-kernel/linux/files/0421-drm-amdgpu-add-an-cgs-interface-to-notify-amdgpu-the.patch
deleted file mode 100644
index 18c7d95f..00000000
--- a/common/recipes-kernel/linux/files/0421-drm-amdgpu-add-an-cgs-interface-to-notify-amdgpu-the.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From ea79c3009a9c40bf50a7bfc31bd84912ff7c9399 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 14:20:37 +0800
-Subject: [PATCH 0421/1110] drm/amdgpu: add an cgs interface to notify amdgpu
- the dpm state.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 11 +++++++++++
- drivers/gpu/drm/amd/include/cgs_common.h |  8 ++++++++
- 2 files changed, 19 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 75cb5b9..6043dc7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -850,6 +850,16 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
- 	return 0;
- }
- 
-+
-+static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled)
-+{
-+	CGS_FUNC_ADEV;
-+
-+	adev->pm.dpm_enabled = enabled;
-+
-+	return 0;
-+}
-+
- /** \brief evaluate acpi namespace object, handle or pathname must be valid
-  *  \param cgs_device
-  *  \param info input/output arguments for the control method
-@@ -1100,6 +1110,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
- 	amdgpu_cgs_set_powergating_state,
- 	amdgpu_cgs_set_clockgating_state,
- 	amdgpu_cgs_get_active_displays_info,
-+	amdgpu_cgs_notify_dpm_enabled,
- 	amdgpu_cgs_call_acpi_method,
- 	amdgpu_cgs_query_system_info,
- };
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index aec38fc..ab84d49 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -589,6 +589,8 @@ typedef int(*cgs_get_active_displays_info)(
- 					void *cgs_device,
- 					struct cgs_display_info *info);
- 
-+typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled);
-+
- typedef int (*cgs_call_acpi_method)(void *cgs_device,
- 					uint32_t acpi_method,
- 					uint32_t acpi_function,
-@@ -644,6 +646,8 @@ struct cgs_ops {
- 	cgs_set_clockgating_state set_clockgating_state;
- 	/* display manager */
- 	cgs_get_active_displays_info get_active_displays_info;
-+	/* notify dpm enabled */
-+	cgs_notify_dpm_enabled notify_dpm_enabled;
- 	/* ACPI */
- 	cgs_call_acpi_method call_acpi_method;
- 	/* get system info */
-@@ -734,8 +738,12 @@ struct cgs_device
- 	CGS_CALL(set_powergating_state, dev, block_type, state)
- #define cgs_set_clockgating_state(dev, block_type, state)	\
- 	CGS_CALL(set_clockgating_state, dev, block_type, state)
-+#define cgs_notify_dpm_enabled(dev, enabled)	\
-+	CGS_CALL(notify_dpm_enabled, dev, enabled)
-+
- #define cgs_get_active_displays_info(dev, info)	\
- 	CGS_CALL(get_active_displays_info, dev, info)
-+
- #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)	\
- 	CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
- #define cgs_query_system_info(dev, sys_info)	\
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0422-drm-amdgpu-Not-support-disable-dpm-in-powerplay.patch b/common/recipes-kernel/linux/files/0422-drm-amdgpu-Not-support-disable-dpm-in-powerplay.patch
deleted file mode 100644
index c1d8fab7..00000000
--- a/common/recipes-kernel/linux/files/0422-drm-amdgpu-Not-support-disable-dpm-in-powerplay.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From b94ac88cca377036c325a8bd799b7b87e3b84243 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 14:21:50 +0800
-Subject: [PATCH 0422/1110] drm/amdgpu: Not support disable dpm in powerplay.
-
-We don't support the dpm parameter in powerplay.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 3cb6d6c..9430a7d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -161,12 +161,8 @@ static int amdgpu_pp_sw_init(void *handle)
- 					adev->powerplay.pp_handle);
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (adev->pp_enabled) {
--		if (amdgpu_dpm == 0)
--			adev->pm.dpm_enabled = false;
--		else
--			adev->pm.dpm_enabled = true;
--	}
-+	if (adev->pp_enabled)
-+		adev->pm.dpm_enabled = true;
- #endif
- 
- 	return ret;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0423-drm-amd-powerplay-notify-amdgpu-whether-dpm-is-enabl.patch b/common/recipes-kernel/linux/files/0423-drm-amd-powerplay-notify-amdgpu-whether-dpm-is-enabl.patch
deleted file mode 100644
index aa946dae..00000000
--- a/common/recipes-kernel/linux/files/0423-drm-amd-powerplay-notify-amdgpu-whether-dpm-is-enabl.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 7c850b2b0659cd76f80942c04ac19bbfc69b12ee Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 14:24:33 +0800
-Subject: [PATCH 0423/1110] drm/amd/powerplay: notify amdgpu whether dpm is
- enabled or not.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index be31bed..f8b1c44 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -130,18 +130,25 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
- 
- int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
- {
-+	int ret = 1;
-+	bool enabled;
- 	PHM_FUNC_CHECK(hwmgr);
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 		PHM_PlatformCaps_TablelessHardwareInterface)) {
- 		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
--			return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
-+			ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
- 	} else {
--		return phm_dispatch_table(hwmgr,
-+		ret = phm_dispatch_table(hwmgr,
- 				&(hwmgr->enable_dynamic_state_management),
- 				NULL, NULL);
- 	}
--	return 0;
-+
-+	enabled = ret == 0 ? true : false;
-+
-+	cgs_notify_dpm_enabled(hwmgr->device, enabled);
-+
-+	return ret;
- }
- 
- int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0424-drm-amdgpu-check-dpm-state-before-pm-system-fs-initi.patch b/common/recipes-kernel/linux/files/0424-drm-amdgpu-check-dpm-state-before-pm-system-fs-initi.patch
deleted file mode 100644
index 059cf163..00000000
--- a/common/recipes-kernel/linux/files/0424-drm-amdgpu-check-dpm-state-before-pm-system-fs-initi.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 28e55a323213bd61af9d2852573aeb6dbd1b45d7 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 14:34:51 +0800
-Subject: [PATCH 0424/1110] drm/amdgpu: check dpm state before pm system fs
- initialized.
-
-Make sure powerplay initialized properly before enabling
-debugfs pm files.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed- by: Alex Deucher <alexander.deucher@amd.com>
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 9430a7d..e9c6ae6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -143,7 +143,7 @@ static int amdgpu_pp_late_init(void *handle)
- 					adev->powerplay.pp_handle);
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (adev->pp_enabled) {
-+	if (adev->pp_enabled && adev->pm.dpm_enabled) {
- 		amdgpu_pm_sysfs_init(adev);
- 		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0425-drm-amd-powerplay-add-new-Fiji-function-for-not-sett.patch b/common/recipes-kernel/linux/files/0425-drm-amd-powerplay-add-new-Fiji-function-for-not-sett.patch
deleted file mode 100644
index b95ad541..00000000
--- a/common/recipes-kernel/linux/files/0425-drm-amd-powerplay-add-new-Fiji-function-for-not-sett.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 39079a6cc06efca3bf12a084a665b9fb4b9f5ba4 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 18:31:43 +0800
-Subject: [PATCH 0425/1110] drm/amd/powerplay: add new Fiji function for not
- setting same ps.
-
-Add comparison function used by powerplay to determine which
-power state to select.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 63 ++++++++++++++++++++++++
- 1 file changed, 63 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 51dedf8..a21f58e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -5195,6 +5195,67 @@ static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	return size;
- }
- 
-+static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
-+							   const struct fiji_performance_level *pl2)
-+{
-+	return ((pl1->memory_clock == pl2->memory_clock) &&
-+		  (pl1->engine_clock == pl2->engine_clock) &&
-+		  (pl1->pcie_gen == pl2->pcie_gen) &&
-+		  (pl1->pcie_lane == pl2->pcie_lane));
-+}
-+
-+int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
-+{
-+	const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
-+	const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
-+	int i;
-+
-+	if (equal == NULL || psa == NULL || psb == NULL)
-+		return -EINVAL;
-+
-+	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
-+	if (psa->performance_level_count != psb->performance_level_count) {
-+		*equal = false;
-+		return 0;
-+	}
-+
-+	for (i = 0; i < psa->performance_level_count; i++) {
-+		if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
-+			/* If we have found even one performance level pair that is different the states are different. */
-+			*equal = false;
-+			return 0;
-+		}
-+	}
-+
-+	/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
-+	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
-+	*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
-+	*equal &= (psa->sclk_threshold == psb->sclk_threshold);
-+	*equal &= (psa->acp_clk == psb->acp_clk);
-+
-+	return 0;
-+}
-+
-+bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+	bool is_update_required = false;
-+	struct cgs_display_info info = {0,0,NULL};
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		is_update_required = true;
-+/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
-+	if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+		cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
-+		if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
-+			is_update_required = true;
-+*/
-+	return is_update_required;
-+}
-+
-+
- static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.backend_init = &fiji_hwmgr_backend_init,
- 	.backend_fini = &tonga_hwmgr_backend_fini,
-@@ -5230,6 +5291,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
- 	.set_fan_control_mode = fiji_set_fan_control_mode,
- 	.get_fan_control_mode = fiji_get_fan_control_mode,
-+	.check_states_equal = fiji_check_states_equal,
-+	.check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
- 	.get_pp_table = fiji_get_pp_table,
- 	.set_pp_table = fiji_set_pp_table,
- 	.force_clock_level = fiji_force_clock_level,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0426-drm-amd-powerplay-Need-to-change-boot-to-performance.patch b/common/recipes-kernel/linux/files/0426-drm-amd-powerplay-Need-to-change-boot-to-performance.patch
deleted file mode 100644
index 52897550..00000000
--- a/common/recipes-kernel/linux/files/0426-drm-amd-powerplay-Need-to-change-boot-to-performance.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 2b14c1b6d6bfc7ce9087050f0ffc7386d1825b5f Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 18:45:59 +0800
-Subject: [PATCH 0426/1110] drm/amd/powerplay: Need to change boot to
- performance state in resume.
-
-Fixes slow performance on resume.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-index 6b52c78..56856a2 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -137,14 +137,14 @@ static const pem_event_action *resume_event[] = {
- 	reset_display_configCounter_tasks,
- 	update_dal_configuration_tasks,
- 	vari_bright_resume_tasks,
--	block_adjust_power_state_tasks,
- 	setup_asic_tasks,
- 	enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
- 	enable_dynamic_state_management_tasks,
- 	enable_clock_power_gatings_tasks,
- 	enable_disable_bapm_tasks,
- 	initialize_thermal_controller_tasks,
--	reset_boot_state_tasks,
-+	get_2d_performance_state_tasks,
-+	set_performance_state_tasks,
- 	adjust_power_state_tasks,
- 	enable_disable_fps_tasks,
- 	notify_hw_power_source_tasks,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0427-drm-amdgpu-Set-vblank_disable_allowed-true.patch b/common/recipes-kernel/linux/files/0427-drm-amdgpu-Set-vblank_disable_allowed-true.patch
deleted file mode 100644
index 8d42980e..00000000
--- a/common/recipes-kernel/linux/files/0427-drm-amdgpu-Set-vblank_disable_allowed-true.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 2db5fbd509cb7327031e8d45464ba426246456d7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com>
-Date: Thu, 31 Mar 2016 15:46:43 +0900
-Subject: [PATCH 0427/1110] drm/amdgpu: Set vblank_disable_allowed = true
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Without this, since the conversion from drm_vblank_pre/post_modeset to
-drm_vblank_on/off, the vblank interrupt could never be disabled after
-userspace triggered enabling it.
-
-Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index f594cfa..762cfdb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -219,6 +219,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
- 	if (r) {
- 		return r;
- 	}
-+	adev->ddev->vblank_disable_allowed = true;
-+
- 	/* enable msi */
- 	adev->irq.msi_enabled = false;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0428-drm-amdgpu-print-vram-type-rather-than-just-DDR.patch b/common/recipes-kernel/linux/files/0428-drm-amdgpu-print-vram-type-rather-than-just-DDR.patch
deleted file mode 100644
index 87daa193..00000000
--- a/common/recipes-kernel/linux/files/0428-drm-amdgpu-print-vram-type-rather-than-just-DDR.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 6fb8cb4190dca5106734e44b03ed3533d3ef18e1 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 31 Mar 2016 16:56:22 -0400
-Subject: [PATCH 0428/1110] drm/amdgpu: print vram type rather than just DDR
-
-We have the info, so use it rather than reporting just DDR.
-
-Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 15 +++++++++++++--
- 1 file changed, 13 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index 95d35c2..af5c32f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -476,6 +476,17 @@ int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
- 	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
- }
- 
-+static const char *amdgpu_vram_names[] = {
-+	"UNKNOWN",
-+	"GDDR1",
-+	"DDR2",
-+	"GDDR3",
-+	"GDDR4",
-+	"GDDR5",
-+	"HBM",
-+	"DDR3"
-+};
-+
- int amdgpu_bo_init(struct amdgpu_device *adev)
- {
- 	/* Add an MTRR for the VRAM */
-@@ -484,8 +495,8 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
- 	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
- 		adev->mc.mc_vram_size >> 20,
- 		(unsigned long long)adev->mc.aper_size >> 20);
--	DRM_INFO("RAM width %dbits DDR\n",
--			adev->mc.vram_width);
-+	DRM_INFO("RAM width %dbits %s\n",
-+		 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
- 	return amdgpu_ttm_init(adev);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0429-drm-amdgpu-fix-leaking-fence-in-the-pageflip-code.patch b/common/recipes-kernel/linux/files/0429-drm-amdgpu-fix-leaking-fence-in-the-pageflip-code.patch
deleted file mode 100644
index b4574ebc..00000000
--- a/common/recipes-kernel/linux/files/0429-drm-amdgpu-fix-leaking-fence-in-the-pageflip-code.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From b2a8f8bd510b25322019e5648e1bc0fb343b699c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 31 Mar 2016 13:05:51 +0200
-Subject: [PATCH 0429/1110] drm/amdgpu: fix leaking fence in the pageflip code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This fixes a memory leak when we can't register the callback on a fence.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index df65b11..7660f30 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -57,7 +57,7 @@ static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
- 	if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
- 		return true;
- 
--	fence_put(*f);
-+	fence_put(fence);
- 	return false;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0430-drm-amdgpu-fence-wait-old-rcu-slot.patch b/common/recipes-kernel/linux/files/0430-drm-amdgpu-fence-wait-old-rcu-slot.patch
deleted file mode 100644
index 732eb63a..00000000
--- a/common/recipes-kernel/linux/files/0430-drm-amdgpu-fence-wait-old-rcu-slot.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From f85e931c028faa6d279fa2d5741ec365a9ca4085 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 31 Mar 2016 11:07:14 +0800
-Subject: [PATCH 0430/1110] drm/amdgpu: fence wait old rcu slot
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-since the rcu slot was initialized to be num_hw_submission,
-if command submission doesn't use scheduler, this limitation
-will be invalid like uvd test.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 4303b44..d81f1f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -121,7 +121,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- {
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_fence *fence;
--	struct fence **ptr;
-+	struct fence *old, **ptr;
- 	uint32_t seq;
- 
- 	fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
-@@ -141,7 +141,11 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
- 	/* This function can't be called concurrently anyway, otherwise
- 	 * emitting the fence would mess up the hardware ring buffer.
- 	 */
--	BUG_ON(rcu_dereference_protected(*ptr, 1));
-+	old = rcu_dereference_protected(*ptr, 1);
-+	if (old && !fence_is_signaled(old)) {
-+		DRM_INFO("rcu slot is busy\n");
-+		fence_wait(old, false);
-+	}
- 
- 	rcu_assign_pointer(*ptr, fence_get(&fence->base));
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0431-drm-amdgpu-save-and-restore-UVD-context-with-suspend.patch b/common/recipes-kernel/linux/files/0431-drm-amdgpu-save-and-restore-UVD-context-with-suspend.patch
deleted file mode 100644
index ffbc8849..00000000
--- a/common/recipes-kernel/linux/files/0431-drm-amdgpu-save-and-restore-UVD-context-with-suspend.patch
+++ /dev/null
@@ -1,173 +0,0 @@
-From 880a8ad9990c8cb09e5f991eca25105164245e28 Mon Sep 17 00:00:00 2001
-From: Leo Liu <leo.liu@amd.com>
-Date: Fri, 1 Apr 2016 10:36:06 -0400
-Subject: [PATCH 0431/1110] drm/amdgpu: save and restore UVD context with
- suspend and resume
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-and revert fix following it accordingly
-
-Revert "drm/amdgpu: stop trying to suspend UVD sessions v2"
-Revert "drm/amdgpu: fix the UVD suspend sequence order"
-
-Signed-off-by: Leo Liu <leo.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 48 ++++++++++++++++++---------------
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c   |  4 +--
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c   |  4 +--
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  7 ++---
- 5 files changed, 36 insertions(+), 28 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 3ff6b3e..16cdddb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1595,6 +1595,7 @@ struct amdgpu_uvd {
- 	struct amdgpu_bo	*vcpu_bo;
- 	void			*cpu_addr;
- 	uint64_t		gpu_addr;
-+        void                    *saved_bo;
- 	unsigned		fw_version;
- 	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
- 	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 324bb32..69547c3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -243,32 +243,33 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- 
- int amdgpu_uvd_suspend(struct amdgpu_device *adev)
- {
--	struct amdgpu_ring *ring = &adev->uvd.ring;
--	int i, r;
-+        unsigned size;
-+        void *ptr;
-+        const struct common_firmware_header *hdr;
-+        int i;
- 
- 	if (adev->uvd.vcpu_bo == NULL)
- 		return 0;
- 
--	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
--		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
--		if (handle != 0) {
--			struct fence *fence;
--
--			amdgpu_uvd_note_usage(adev);
--
--                        r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence);
--			if (r) {
--				DRM_ERROR("Error destroying UVD (%d)!\n", r);
--				continue;
--			}
-+        for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
-+                if (atomic_read(&adev->uvd.handles[i]))
-+                        break;
-+ 
-+        if (i == AMDGPU_MAX_UVD_HANDLES)
-+                return 0;
-+        hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
- 
--			fence_wait(fence, false);
--			fence_put(fence);
-+        size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-+        size -= le32_to_cpu(hdr->ucode_size_bytes);
- 
--			adev->uvd.filp[i] = NULL;
--			atomic_set(&adev->uvd.handles[i], 0);
--		}
--	}
-+        ptr = adev->uvd.cpu_addr;
-+        ptr += le32_to_cpu(hdr->ucode_size_bytes);
-+ 
-+        adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
-+        if (!adev->uvd.saved_bo)
-+                return -ENOMEM;
-+ 
-+        memcpy(adev->uvd.saved_bo, ptr, size);
- 
- 	return 0;
- }
-@@ -295,7 +296,12 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
- 	ptr = adev->uvd.cpu_addr;
- 	ptr += le32_to_cpu(hdr->ucode_size_bytes);
- 
--	memset(ptr, 0, size);
-+	if (adev->uvd.saved_bo != NULL) {
-+		memcpy(ptr, adev->uvd.saved_bo, size);
-+		kfree(adev->uvd.saved_bo);
-+		adev->uvd.saved_bo = NULL;
-+	} else
-+		memset(ptr, 0, size);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index c606ccb..cb46375 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -224,11 +224,11 @@ static int uvd_v4_2_suspend(void *handle)
- 	int r;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	r = amdgpu_uvd_suspend(adev);
-+	r = uvd_v4_2_hw_fini(adev);
- 	if (r)
- 		return r;
- 
--	r = uvd_v4_2_hw_fini(adev);
-+	r = amdgpu_uvd_suspend(adev);
- 	if (r)
- 		return r;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index e3c852d..16476d8 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -220,11 +220,11 @@ static int uvd_v5_0_suspend(void *handle)
- 	int r;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	r = amdgpu_uvd_suspend(adev);
-+	r = uvd_v5_0_hw_fini(adev);
- 	if (r)
- 		return r;
- 
--	r = uvd_v5_0_hw_fini(adev);
-+	r = amdgpu_uvd_suspend(adev);
- 	if (r)
- 		return r;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 3375e61..d493791 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -214,15 +214,16 @@ static int uvd_v6_0_suspend(void *handle)
- 	int r;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	r = uvd_v6_0_hw_fini(adev);
-+	if (r)
-+		return r;
-+
- 	/* Skip this for APU for now */
- 	if (!(adev->flags & AMD_IS_APU)) {
- 		r = amdgpu_uvd_suspend(adev);
- 		if (r)
- 			return r;
- 	}
--	r = uvd_v6_0_hw_fini(adev);
--	if (r)
--		return r;
- 
- 	return r;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0432-drm-amdgpu-save-and-restore-the-firwmware-cache-part.patch b/common/recipes-kernel/linux/files/0432-drm-amdgpu-save-and-restore-the-firwmware-cache-part.patch
deleted file mode 100644
index 7fd7bab6..00000000
--- a/common/recipes-kernel/linux/files/0432-drm-amdgpu-save-and-restore-the-firwmware-cache-part.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From bda6d7754c62d614accae5a483b85dc6dfe7364f Mon Sep 17 00:00:00 2001
-From: Leo Liu <leo.liu@amd.com>
-Date: Mon, 4 Apr 2016 10:55:43 -0400
-Subject: [PATCH 0432/1110] drm/amdgpu: save and restore the firwmware cache
- part when suspend resume
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Leo Liu <leo.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 30 +++++++++++++-----------------
- 1 file changed, 13 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 69547c3..86dead7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -245,7 +245,6 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
- {
-         unsigned size;
-         void *ptr;
--        const struct common_firmware_header *hdr;
-         int i;
- 
- 	if (adev->uvd.vcpu_bo == NULL)
-@@ -257,15 +256,11 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
-  
-         if (i == AMDGPU_MAX_UVD_HANDLES)
-                 return 0;
--        hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
- 
-         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
--        size -= le32_to_cpu(hdr->ucode_size_bytes);
--
-         ptr = adev->uvd.cpu_addr;
--        ptr += le32_to_cpu(hdr->ucode_size_bytes);
-- 
--        adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
-+        
-+	adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
-         if (!adev->uvd.saved_bo)
-                 return -ENOMEM;
-  
-@@ -278,30 +273,31 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
- {
- 	unsigned size;
- 	void *ptr;
--	const struct common_firmware_header *hdr;
--	unsigned offset;
- 
- 	if (adev->uvd.vcpu_bo == NULL)
- 		return -EINVAL;
- 
--	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
--	offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
--	memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
--		(adev->uvd.fw->size) - offset);
--
- 	cancel_delayed_work_sync(&adev->uvd.idle_work);
- 
- 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
--	size -= le32_to_cpu(hdr->ucode_size_bytes);
- 	ptr = adev->uvd.cpu_addr;
--	ptr += le32_to_cpu(hdr->ucode_size_bytes);
- 
- 	if (adev->uvd.saved_bo != NULL) {
- 		memcpy(ptr, adev->uvd.saved_bo, size);
- 		kfree(adev->uvd.saved_bo);
- 		adev->uvd.saved_bo = NULL;
--	} else
-+        } else {
-+                const struct common_firmware_header *hdr;
-+                unsigned offset;
-+ 
-+                hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
-+                offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-+                memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
-+                        (adev->uvd.fw->size) - offset);
-+                size -= le32_to_cpu(hdr->ucode_size_bytes);
-+                ptr += le32_to_cpu(hdr->ucode_size_bytes);
- 		memset(ptr, 0, size);
-+        }
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0433-drm-amd-powerplay-fix-issue-that-resume-back-dpm-can.patch b/common/recipes-kernel/linux/files/0433-drm-amd-powerplay-fix-issue-that-resume-back-dpm-can.patch
deleted file mode 100644
index 44a4c02e..00000000
--- a/common/recipes-kernel/linux/files/0433-drm-amd-powerplay-fix-issue-that-resume-back-dpm-can.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From b1b7c0b52b5d8b1682a3934645e892b97c378979 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 4 Apr 2016 15:57:10 +0800
-Subject: [PATCH 0433/1110] drm/amd/powerplay: fix issue that resume back, dpm
- can't work on FIJI.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index a21f58e..89f31bc 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -2389,6 +2389,7 @@ static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- 
- 	for(count = 0; count < table->VceLevelCount; count++) {
- 		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage = 0;
- 		table->VceLevel[count].MinVoltage |=
- 				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
- 		table->VceLevel[count].MinVoltage |=
-@@ -2465,6 +2466,7 @@ static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- 
- 	for (count = 0; count < table->SamuLevelCount; count++) {
- 		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].MinVoltage = 0;
- 		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
- 		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- 				VOLTAGE_SCALE) << VDDC_SHIFT;
-@@ -2562,6 +2564,7 @@ static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- 	table->UvdBootLevel = 0;
- 
- 	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].MinVoltage = 0;
- 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
- 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
- 		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-@@ -2900,6 +2903,8 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
- 	if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
- 		fiji_populate_smc_voltage_tables(hwmgr, table);
- 
-+	table->SystemFlags = 0;
-+
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_AutomaticDCTransition))
- 		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-@@ -2997,6 +3002,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
- 	table->MemoryThermThrottleEnable = 1;
- 	table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
- 	table->PCIeGenInterval = 1;
-+	table->VRConfig = 0;
- 
- 	result = fiji_populate_vr_config(hwmgr, table);
- 	PP_ASSERT_WITH_CODE(0 == result,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0434-drm-amd-powerplay-add-uvd-vce-dpm-enabling-flag-defa.patch b/common/recipes-kernel/linux/files/0434-drm-amd-powerplay-add-uvd-vce-dpm-enabling-flag-defa.patch
deleted file mode 100644
index c65f75ab..00000000
--- a/common/recipes-kernel/linux/files/0434-drm-amd-powerplay-add-uvd-vce-dpm-enabling-flag-defa.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 9e78dec5ee50b911c85bd350f5c03c7bcbfe58f2 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Mon, 4 Apr 2016 16:38:55 +0800
-Subject: [PATCH 0434/1110] drm/amd/powerplay: add uvd/vce dpm enabling flag
- default.
-
-These should be set by default otherwise the UVD/VCE performance
-won't be optimal.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-index f8b1c44..fa208ad 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
-@@ -58,6 +58,9 @@ void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
- 
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
- 
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
-+
- 	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
- 		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
- 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0435-drm-amdgpu-total-vram-size-also-reduces-pin-size.patch b/common/recipes-kernel/linux/files/0435-drm-amdgpu-total-vram-size-also-reduces-pin-size.patch
deleted file mode 100644
index 0a1c46a7..00000000
--- a/common/recipes-kernel/linux/files/0435-drm-amdgpu-total-vram-size-also-reduces-pin-size.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 19b4a59ce20163bac0cf431ca82e19d0fc3cb39e Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 1 Apr 2016 17:05:30 +0800
-Subject: [PATCH 0435/1110] drm/amdgpu: total vram size also reduces pin size
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index c825880..8efe335 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -382,6 +382,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- 		struct drm_amdgpu_info_vram_gtt vram_gtt;
- 
- 		vram_gtt.vram_size = adev->mc.real_vram_size;
-+		vram_gtt.vram_size -= adev->vram_pin_size;
- 		vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
- 		vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
- 		vram_gtt.gtt_size  = adev->mc.gtt_size;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0436-drm-amdgpu-add-invisible-pin-size-statistic.patch b/common/recipes-kernel/linux/files/0436-drm-amdgpu-add-invisible-pin-size-statistic.patch
deleted file mode 100644
index 09ca6e44..00000000
--- a/common/recipes-kernel/linux/files/0436-drm-amdgpu-add-invisible-pin-size-statistic.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 4982b13ed49e522d56cd303c2910c7b76c15a491 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Tue, 5 Apr 2016 10:48:48 +0800
-Subject: [PATCH 0436/1110] drm/amdgpu: add invisible pin size statistic
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 ++++++++----
- 3 files changed, 10 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 16cdddb..47150ae 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2039,6 +2039,7 @@ struct amdgpu_device {
- 
- 	/* tracking pinned memory */
- 	u64 vram_pin_size;
-+	u64 invisible_pin_size;
- 	u64 gart_pin_size;
- 
- 	/* amdkfd interface */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index 8efe335..b04337d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- 		vram_gtt.vram_size = adev->mc.real_vram_size;
- 		vram_gtt.vram_size -= adev->vram_pin_size;
- 		vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
--		vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
-+		vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
- 		vram_gtt.gtt_size  = adev->mc.gtt_size;
- 		vram_gtt.gtt_size -= adev->gart_pin_size;
- 		return copy_to_user(out, &vram_gtt,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index af5c32f..b91ff33 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
- 		bo->pin_count = 1;
- 		if (gpu_addr != NULL)
- 			*gpu_addr = amdgpu_bo_gpu_offset(bo);
--		if (domain == AMDGPU_GEM_DOMAIN_VRAM)
-+		if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
- 			bo->adev->vram_pin_size += amdgpu_bo_size(bo);
--		else
-+			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
-+				bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
-+		} else
- 			bo->adev->gart_pin_size += amdgpu_bo_size(bo);
- 	} else {
- 		dev_err(bo->adev->dev, "%p pin failed\n", bo);
-@@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
- 	}
- 	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
- 	if (likely(r == 0)) {
--		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
-+		if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
- 			bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
--		else
-+			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
-+				bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
-+		} else
- 			bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
- 	} else {
- 		dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0437-drm-amd-amdgpu-fix-irq-domain-remove-for-tonga-ih.patch b/common/recipes-kernel/linux/files/0437-drm-amd-amdgpu-fix-irq-domain-remove-for-tonga-ih.patch
deleted file mode 100644
index 8a84b216..00000000
--- a/common/recipes-kernel/linux/files/0437-drm-amd-amdgpu-fix-irq-domain-remove-for-tonga-ih.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 7d9176eddf86c5c7cb652ceed278a2800332b36a Mon Sep 17 00:00:00 2001
-From: Junwei Zhang <Jerry.Zhang@amd.com>
-Date: Wed, 6 Apr 2016 16:01:19 +0800
-Subject: [PATCH 0437/1110] drm/amd/amdgpu: fix irq domain remove for tonga ih
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-index b6f7d7b..0f14199 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-@@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle)
- 
- 	amdgpu_irq_fini(adev);
- 	amdgpu_ih_ring_fini(adev);
--	amdgpu_irq_add_domain(adev);
-+	amdgpu_irq_remove_domain(adev);
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0438-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch b/common/recipes-kernel/linux/files/0438-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch
deleted file mode 100644
index 99c603ee..00000000
--- a/common/recipes-kernel/linux/files/0438-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From aa3baee444c65aa8fc6bd272677cfa80d4d099e7 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 13 Apr 2016 23:37:42 -0400
-Subject: [PATCH 0438/1110] drm/amdgpu/acp: fix resume on CZ systems with AZ
- audio
-
-Nothing to do on resume on systems with AZ audio.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-index d6b0bff..b7b583c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -425,6 +425,10 @@ static int acp_resume(void *handle)
- 	struct acp_pm_domain *apd;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	/* return early if no ACP */
-+	if (!adev->acp.acp_genpd)
-+		return 0;
-+
- 	/* SMU block will power on ACP irrespective of ACP runtime status.
- 	 * Power off explicitly based on genpd ACP runtime status so that ACP
- 	 * hw and ACP-genpd status are in sync.
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0439-drm-amdgpu-delete-unused-struct-member-suspend-from-.patch b/common/recipes-kernel/linux/files/0439-drm-amdgpu-delete-unused-struct-member-suspend-from-.patch
deleted file mode 100644
index 0c3cae52..00000000
--- a/common/recipes-kernel/linux/files/0439-drm-amdgpu-delete-unused-struct-member-suspend-from-.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e78ac9768193bf9e2406e37ffde6d4999489e32a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sat, 19 Mar 2016 16:12:11 +0100
-Subject: [PATCH 0439/1110] drm/amdgpu: delete unused struct member suspend
- from amdgpu_device
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 47150ae..829e124 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1908,7 +1908,6 @@ struct amdgpu_device {
- 	int				usec_timeout;
- 	const struct amdgpu_asic_funcs	*asic_funcs;
- 	bool				shutdown;
--	bool				suspend;
- 	bool				need_dma32;
- 	bool				accel_working;
- 	struct work_struct 		reset_work;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0440-drm-amdgpu-do-not-store-bios_header_start-in-amdgpu_.patch b/common/recipes-kernel/linux/files/0440-drm-amdgpu-do-not-store-bios_header_start-in-amdgpu_.patch
deleted file mode 100644
index a78f4a37..00000000
--- a/common/recipes-kernel/linux/files/0440-drm-amdgpu-do-not-store-bios_header_start-in-amdgpu_.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 318d244b7d2acce4b4e85b9f4cc97534c69e2a64 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sat, 19 Mar 2016 16:12:13 +0100
-Subject: [PATCH 0440/1110] drm/amdgpu: do not store bios_header_start in
- amdgpu_device
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It is only used locally in amdgpu_get_bios
-
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 8 ++++----
- 2 files changed, 4 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 829e124..ce1638c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1929,7 +1929,6 @@ struct amdgpu_device {
- 	/* BIOS */
- 	uint8_t				*bios;
- 	bool				is_atom_bios;
--	uint16_t			bios_header_start;
- 	struct amdgpu_bo		*stollen_vga_memory;
- 	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-index 80add22..99ca75b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-@@ -349,7 +349,7 @@ static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
- bool amdgpu_get_bios(struct amdgpu_device *adev)
- {
- 	bool r;
--	uint16_t tmp;
-+	uint16_t tmp, bios_header_start;
- 
- 	r = amdgpu_atrm_get_bios(adev);
- 	if (r == false)
-@@ -383,11 +383,11 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
- 		goto free_bios;
- 	}
- 
--	adev->bios_header_start = RBIOS16(0x48);
--	if (!adev->bios_header_start) {
-+	bios_header_start = RBIOS16(0x48);
-+	if (!bios_header_start) {
- 		goto free_bios;
- 	}
--	tmp = adev->bios_header_start + 4;
-+	tmp = bios_header_start + 4;
- 	if (!memcmp(adev->bios + tmp, "ATOM", 4) ||
- 	    !memcmp(adev->bios + tmp, "MOTA", 4)) {
- 		adev->is_atom_bios = true;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch b/common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch
deleted file mode 100644
index f4b70578..00000000
--- a/common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 245ca0d50e4ab1bca452b406249e09dd5f845cb7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sat, 19 Mar 2016 16:12:17 +0100
-Subject: [PATCH 0441/1110] drm/amdgpu: mark amdgpu_allowed_register_entry
- tables as 'const'
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/vi.c  | 10 +++++-----
- 2 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index bddc9ba..009598b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -962,7 +962,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
- 	return true;
- }
- 
--static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
-+static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
- 	{mmGRBM_STATUS, false},
- 	{mmGB_ADDR_CONFIG, false},
- 	{mmMC_ARB_RAMCFG, false},
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 1c120ef..a145556 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -414,11 +414,11 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
- 	return true;
- }
- 
--static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
-+static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
- 	{mmGB_MACROTILE_MODE7, true},
- };
- 
--static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
-+static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
- 	{mmGB_TILE_MODE7, true},
- 	{mmGB_TILE_MODE12, true},
- 	{mmGB_TILE_MODE17, true},
-@@ -426,7 +426,7 @@ static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
- 	{mmGB_MACROTILE_MODE7, true},
- };
- 
--static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
-+static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
- 	{mmGRBM_STATUS, false},
- 	{mmGRBM_STATUS2, false},
- 	{mmGRBM_STATUS_SE0, false},
-@@ -525,8 +525,8 @@ static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
- static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
- 			    u32 sh_num, u32 reg_offset, u32 *value)
- {
--	struct amdgpu_allowed_register_entry *asic_register_table = NULL;
--	struct amdgpu_allowed_register_entry *asic_register_entry;
-+	const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
-+	const struct amdgpu_allowed_register_entry *asic_register_entry;
- 	uint32_t size, i;
- 
- 	*value = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0442-drm-amdgpu-improve-vmid-assigment-V2.patch b/common/recipes-kernel/linux/files/0442-drm-amdgpu-improve-vmid-assigment-V2.patch
deleted file mode 100644
index eb82ef05..00000000
--- a/common/recipes-kernel/linux/files/0442-drm-amdgpu-improve-vmid-assigment-V2.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 6863e41d9fcd67a8b91775a459fb92d54b98089b Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 17 Mar 2016 11:41:37 +0800
-Subject: [PATCH 0442/1110] drm/amdgpu: improve vmid assigment V2
-
-V2: the signaled items on the LRU maintain their order
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index e2effcf..ac4e092 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -223,6 +223,20 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 				      struct amdgpu_vm_manager_id,
- 				      list);
- 
-+	if (id->mgr_id->active && !fence_is_signaled(id->mgr_id->active)) {
-+		struct amdgpu_vm_manager_id *mgr_id, *tmp;
-+		struct list_head *head = &adev->vm_manager.ids_lru;
-+		list_for_each_entry_safe(mgr_id, tmp, &adev->vm_manager.ids_lru, list) {
-+			if (mgr_id->active && fence_is_signaled(mgr_id->active)) {
-+				list_move(&mgr_id->list, head);
-+				head = &mgr_id->list;
-+			}
-+		}
-+		id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru,
-+					      struct amdgpu_vm_manager_id,
-+					      list);
-+	}
-+
- 	r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active);
- 	if (!r) {
- 		fence_put(id->mgr_id->active);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0443-drm-amdgpu-support-cond-exec.patch b/common/recipes-kernel/linux/files/0443-drm-amdgpu-support-cond-exec.patch
deleted file mode 100644
index 07341080..00000000
--- a/common/recipes-kernel/linux/files/0443-drm-amdgpu-support-cond-exec.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From f616a670bf0b24301261c88f8480f62be6a6c523 Mon Sep 17 00:00:00 2001
-From: Monk Liu <monk.liu@amd.com>
-Date: Thu, 14 Jan 2016 18:08:16 +0800
-Subject: [PATCH 0443/1110] drm/amdgpu: support cond exec
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 3 +++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   | 3 +++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 9 +++++++++
- 3 files changed, 15 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index ce1638c..c0b7731 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -787,6 +787,9 @@ struct amdgpu_ring {
- 	struct amdgpu_ctx	*current_ctx;
- 	enum amdgpu_ring_type	type;
- 	char			name[16];
-+	unsigned		cond_exe_offs;
-+	u64				cond_exe_gpu_addr;
-+	volatile u32	*cond_exe_cpu_addr;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 58b051c..52b63e3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -159,6 +159,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 			amdgpu_ring_emit_hdp_flush(ring);
- 	}
- 
-+	/* always set cond_exec_polling to CONTINUE */
-+	*ring->cond_exe_cpu_addr = 1;
-+
- 	old_ctx = ring->current_ctx;
- 	for (i = 0; i < num_ibs; ++i) {
- 		ib = &ibs[i];
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 972eed2..dd79243 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -267,6 +267,15 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 	}
- 	ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4);
- 	ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
-+
-+	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
-+	if (r) {
-+		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
-+		return r;
-+	}
-+	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
-+	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
-+
- 	spin_lock_init(&ring->fence_lock);
- 	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
- 	if (r) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0444-drm-amdgpu-patch-cond-exec-for-SDMA.patch b/common/recipes-kernel/linux/files/0444-drm-amdgpu-patch-cond-exec-for-SDMA.patch
deleted file mode 100644
index 8475a46c..00000000
--- a/common/recipes-kernel/linux/files/0444-drm-amdgpu-patch-cond-exec-for-SDMA.patch
+++ /dev/null
@@ -1,108 +0,0 @@
-From 8cd08f288a7b536c23bdd618506d223f3bbf35d7 Mon Sep 17 00:00:00 2001
-From: Monk Liu <monk.liu@amd.com>
-Date: Thu, 14 Jan 2016 19:07:38 +0800
-Subject: [PATCH 0444/1110] drm/amdgpu: patch cond exec for SDMA
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Monk Liu <monk.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  4 ++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c |  9 +++++++--
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 25 +++++++++++++++++++++++++
- 3 files changed, 36 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index c0b7731..ddcd836 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -302,6 +302,8 @@ struct amdgpu_ring_funcs {
- 	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
- 	/* pad the indirect buffer to the necessary number of dw */
- 	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
-+	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
-+	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
- };
- 
- /*
-@@ -2188,6 +2190,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
- #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
- #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
-+#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
-+#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
- #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
- #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
- #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 52b63e3..964914b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -123,7 +123,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 	struct amdgpu_ctx *ctx, *old_ctx;
- 	struct amdgpu_vm *vm;
- 	struct fence *hwf;
--	unsigned i;
-+        unsigned i, patch_offset = ~0;
-+
- 	int r = 0;
- 
- 	if (num_ibs == 0)
-@@ -199,9 +200,13 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		amdgpu_ring_emit_fence(ring, addr, ib->sequence,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
--
-+	
-+	if(f)
-         *f = fence_get(hwf);
- 
-+        if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
-+                amdgpu_ring_patch_cond_exec(ring, patch_offset);
-+
- 	amdgpu_ring_commit(ring);
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 5845dde..aebf4b7 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -452,6 +452,31 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
- 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
- }
- 
-+unsigned init_cond_exec(struct amdgpu_ring *ring)
-+{
-+	unsigned ret;
-+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
-+	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
-+	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
-+	amdgpu_ring_write(ring, 1);
-+	ret = ring->wptr;/* this is the offset we need patch later */
-+	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
-+	return ret;
-+}
-+
-+void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
-+{
-+	unsigned cur;
-+	BUG_ON(ring->ring[offset] != 0x55aa55aa);
-+
-+	cur = ring->wptr - 1;
-+	if (likely(cur > offset))
-+		ring->ring[offset] = cur - offset;
-+	else
-+		ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
-+}
-+
-+
- /**
-  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
-  *
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0445-drm-amdgpu-use-sched_job_init-to-initialize-sched_jo.patch b/common/recipes-kernel/linux/files/0445-drm-amdgpu-use-sched_job_init-to-initialize-sched_jo.patch
deleted file mode 100644
index 9cc2a2f8..00000000
--- a/common/recipes-kernel/linux/files/0445-drm-amdgpu-use-sched_job_init-to-initialize-sched_jo.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From 8bf3466e1b68d40f331f2a1b2987d5544ccd2e09 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Mon, 7 Mar 2016 12:49:55 +0800
-Subject: [PATCH 0445/1110] drm/amdgpu: use sched_job_init to initialize
- sched_job
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        | 31 +++++++++++----------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c       | 14 ++++++------
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 17 +++++++++++++++
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  5 ++++-
- 4 files changed, 42 insertions(+), 25 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 170b8da..ed6d8b3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -914,32 +914,27 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 			    union drm_amdgpu_cs *cs)
- {
-         struct amdgpu_ring *ring = p->job->ring;
--	struct amd_sched_fence *fence;
-+        struct fence *fence;
- 	struct amdgpu_job *job;
-+	int r;
- 
-         job = p->job;
-         p->job = NULL;
- 
--
--	job->base.sched = &ring->sched;
--	job->base.s_entity = &p->ctx->rings[ring->idx].entity;
--	job->owner = p->filp;
--	job->free_job = amdgpu_cs_free_job;
--
--	fence = amd_sched_fence_create(job->base.s_entity, p->filp);
--	if (!fence) {
--		amdgpu_cs_free_job(job);
--		kfree(job);
--		return -ENOMEM;
-+        r = amd_sched_job_init(&job->base, &ring->sched,
-+                                                &p->ctx->rings[ring->idx].entity,
-+                                                p->filp, &fence);
-+        if (r) {
-+	
-+ 	         amdgpu_cs_free_job(job);
-+		return r;
- 	}
- 
--	job->base.s_fence = fence;
--	p->fence = fence_get(&fence->base);
--
--	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring,
--					      &fence->base);
-+        job->owner = p->filp;
-+        p->fence = fence_get(fence);
-+        cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence);
- 	job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
--
-+	
- 	trace_amdgpu_cs_ioctl(job);
- 	amd_sched_entity_push_job(&job->base);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index 8a2d54a..b081671 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -87,16 +87,18 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-                       struct amd_sched_entity *entity, void *owner,
-                       struct fence **f)
- {
-+       struct fence *fence;
-+       int r;
-        job->ring = ring;
--       job->base.sched = &ring->sched;
--       job->base.s_entity = entity;
--       job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner);
--       if (!job->base.s_fence)
--               return -ENOMEM;
-+       if (!f)
-+               return -EINVAL;
- 
--       *f = fence_get(&job->base.s_fence->base);
-+       r = amd_sched_job_init(&job->base, &ring->sched, entity, owner, &fence);
-+       if (r)
-+               return r;
- 
-        job->owner = owner;
-+       *f = fence_get(fence);
-        amd_sched_entity_push_job(&job->base);
- 
-        return 0;
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index a5ff945..b9d5822 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -335,6 +335,23 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
- 		   amd_sched_entity_in(sched_job));
- }
- 
-+/* init a sched_job with basic field */
-+int amd_sched_job_init(struct amd_sched_job *job,
-+						struct amd_gpu_scheduler *sched,
-+						struct amd_sched_entity *entity,
-+						void *owner, struct fence **fence)
-+{
-+	job->sched = sched;
-+	job->s_entity = entity;
-+	job->s_fence = amd_sched_fence_create(entity, owner);
-+	if (!job->s_fence)
-+		return -ENOMEM;
-+
-+	if (fence)
-+		*fence = &job->s_fence->base;
-+	return 0;
-+}
-+
- /**
-  * Return ture if we can push more jobs to the hw.
-  */
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index 9403145..74bbec8 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -144,5 +144,8 @@ struct amd_sched_fence *amd_sched_fence_create(
- 	struct amd_sched_entity *s_entity, void *owner);
- void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
- void amd_sched_fence_signal(struct amd_sched_fence *fence);
--
-+int amd_sched_job_init(struct amd_sched_job *job,
-+					struct amd_gpu_scheduler *sched,
-+					struct amd_sched_entity *entity,
-+					void *owner, struct fence **fence);
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch b/common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch
deleted file mode 100644
index 3559e0a0..00000000
--- a/common/recipes-kernel/linux/files/0446-drm-amdgpu-dce11-fix-vertical-bars-appear-on-monitor.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 094b9b451f4889c854def2e9fc9343c5a40cc9da Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Fri, 18 Mar 2016 15:49:41 -0400
-Subject: [PATCH 0446/1110] drm/amdgpu/dce11: fix vertical bars appear on
- monitor
-
-Fixed mc stop and resume hardware programming sequence.
-
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 65 +++-------------------------------
- 1 file changed, 5 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index ad43347..fd74bce 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -565,35 +565,14 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
- 		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
- 					     CRTC_CONTROL, CRTC_MASTER_EN);
- 		if (crtc_enabled) {
--#if 0
--			u32 frame_count;
--			int j;
--
-+#if 1
- 			save->crtc_enabled[i] = true;
- 			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
- 			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
--				amdgpu_display_vblank_wait(adev, i);
--				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
-+				/*it is correct only for RGB ; black is 0*/
-+				WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
- 				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
- 				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
--				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			}
--			/* wait for the next frame */
--			frame_count = amdgpu_display_vblank_get_counter(adev, i);
--			for (j = 0; j < adev->usec_timeout; j++) {
--				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
--					break;
--				udelay(1);
--			}
--			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
--				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
--				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
--				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
--				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- 			}
- #else
- 			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
-@@ -614,54 +593,20 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
- static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
- 				       struct amdgpu_mode_mc_save *save)
- {
--	u32 tmp, frame_count;
--	int i, j;
-+	u32 tmp;
-+	int i;
- 
- 	/* update crtc base addresses */
- 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
- 		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
- 		       upper_32_bits(adev->mc.vram_start));
--		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
--		       upper_32_bits(adev->mc.vram_start));
- 		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
- 		       (u32)adev->mc.vram_start);
--		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
--		       (u32)adev->mc.vram_start);
- 
- 		if (save->crtc_enabled[i]) {
--			tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
--				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
--				WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
--				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
--				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
--				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
--				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
--			}
--			for (j = 0; j < adev->usec_timeout; j++) {
--				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
--					break;
--				udelay(1);
--			}
- 			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
- 			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- 			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			/* wait for the next frame */
--			frame_count = amdgpu_display_vblank_get_counter(adev, i);
--			for (j = 0; j < adev->usec_timeout; j++) {
--				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
--					break;
--				udelay(1);
--			}
- 		}
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0447-drm-amdgpu-delay-job-free-to-when-it-s-finished-v2.patch b/common/recipes-kernel/linux/files/0447-drm-amdgpu-delay-job-free-to-when-it-s-finished-v2.patch
deleted file mode 100644
index bf446a20..00000000
--- a/common/recipes-kernel/linux/files/0447-drm-amdgpu-delay-job-free-to-when-it-s-finished-v2.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From 1a4d5a6525af12d0c7a3f4c9a81379b02b4fa89b Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 3 Mar 2016 19:00:50 +0800
-Subject: [PATCH 0447/1110] drm/amdgpu: delay job free to when it's finished
- (v2)
-
-for those jobs submitted through scheduler, do not
-free it immediately after scheduled, instead free it
-in global workqueue by its sched fence signaling
-callback function.
-
-v2:
-call uf's bo_undef after job_run()
-call job's sync free after job_run()
-no static inline __amdgpu_job_free() anymore, just use
-kfree(job) to replace it.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c       | 11 ++++++++++-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  8 ++++++++
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  5 ++++-
- 4 files changed, 22 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index ddcd836..890844b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2406,5 +2406,4 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
- 		       uint64_t addr, struct amdgpu_bo **bo);
- 
- #include "amdgpu_object.h"
--
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index b081671..e593ed2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -28,6 +28,12 @@
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
-+static void amdgpu_job_free_handler(struct work_struct *ws)
-+{
-+	struct amdgpu_job *job = container_of(ws, struct amdgpu_job, base.work_free_job);
-+	kfree(job);
-+}
-+
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-                     struct amdgpu_job **job)
- {
-@@ -45,6 +51,7 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-        (*job)->adev = adev;
-        (*job)->ibs = (void *)&(*job)[1];
-        (*job)->num_ibs = num_ibs;
-+       INIT_WORK(&(*job)->base.work_free_job, amdgpu_job_free_handler);
- 
-        amdgpu_sync_create(&(*job)->sync);
- 
-@@ -80,7 +87,9 @@ void amdgpu_job_free(struct amdgpu_job *job)
- 
-        amdgpu_bo_unref(&job->uf.bo);
-        amdgpu_sync_free(&job->sync);
--       kfree(job);
-+
-+       if (!job->base.use_sched)
-+                kfree(job);
- }
- 
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index b9d5822..8d49ea2 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -319,6 +319,11 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
- 	return added;
- }
- 
-+static void amd_sched_free_job(struct fence *f, struct fence_cb *cb) {
-+	struct amd_sched_job *job = container_of(cb, struct amd_sched_job, cb_free_job);
-+	schedule_work(&job->work_free_job);
-+}
-+
- /**
-  * Submit a job to the job queue
-  *
-@@ -330,6 +335,9 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
- {
- 	struct amd_sched_entity *entity = sched_job->s_entity;
- 
-+	sched_job->use_sched = 1;
-+	fence_add_callback(&sched_job->s_fence->base,
-+					&sched_job->cb_free_job, amd_sched_free_job);
- 	trace_amd_sched_job(sched_job);
- 	wait_event(entity->sched->job_scheduled,
- 		   amd_sched_entity_in(sched_job));
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index 74bbec8..ee1e812 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -37,7 +37,7 @@ extern atomic_t sched_fence_slab_ref;
- 
- /**
-  * A scheduler entity is a wrapper around a job queue or a group
-- * of other entities. Entities take turns emitting jobs from their 
-+ * of other entities. Entities take turns emitting jobs from their
-  * job queues to corresponding hardware ring based on scheduling
-  * policy.
- */
-@@ -82,6 +82,9 @@ struct amd_sched_job {
- 	struct amd_gpu_scheduler        *sched;
- 	struct amd_sched_entity         *s_entity;
- 	struct amd_sched_fence          *s_fence;
-+	bool	use_sched;	/* true if the job goes to scheduler */
-+	struct fence_cb                cb_free_job;
-+	struct work_struct             work_free_job;
- };
- 
- extern const struct fence_ops amd_sched_fence_ops;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0448-drm-amdgpu-put-job-to-list-before-done.patch b/common/recipes-kernel/linux/files/0448-drm-amdgpu-put-job-to-list-before-done.patch
deleted file mode 100644
index 0de7f845..00000000
--- a/common/recipes-kernel/linux/files/0448-drm-amdgpu-put-job-to-list-before-done.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From dd722c4f3c4a31f7980aee3c738907d7fba184d7 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Fri, 4 Mar 2016 14:33:44 +0800
-Subject: [PATCH 0448/1110] drm/amdgpu:put job to list before done
-
-the mirror_list will be used for later time out detect
-feature.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 12 ++++++++++++
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  6 ++++++
- drivers/gpu/drm/amd/scheduler/sched_fence.c   |  9 +++++++++
- 3 files changed, 27 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 8d49ea2..af846f2 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -349,12 +349,15 @@ int amd_sched_job_init(struct amd_sched_job *job,
- 						struct amd_sched_entity *entity,
- 						void *owner, struct fence **fence)
- {
-+	INIT_LIST_HEAD(&job->node);
- 	job->sched = sched;
- 	job->s_entity = entity;
- 	job->s_fence = amd_sched_fence_create(entity, owner);
- 	if (!job->s_fence)
- 		return -ENOMEM;
- 
-+	job->s_fence->s_job = job;
-+
- 	if (fence)
- 		*fence = &job->s_fence->base;
- 	return 0;
-@@ -408,6 +411,12 @@ static void amd_sched_process_job(struct fence *f, struct fence_cb *cb)
- 	unsigned long flags;
- 
- 	atomic_dec(&sched->hw_rq_count);
-+
-+	/* remove job from ring_mirror_list */
-+	spin_lock_irqsave(&sched->job_list_lock, flags);
-+	list_del_init(&s_fence->s_job->node);
-+	spin_unlock_irqrestore(&sched->job_list_lock, flags);
-+
- 	amd_sched_fence_signal(s_fence);
- 	if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
- 		cancel_delayed_work(&s_fence->dwork);
-@@ -480,6 +489,7 @@ static int amd_sched_main(void *param)
- 		}
- 
- 		atomic_inc(&sched->hw_rq_count);
-+		amd_sched_job_pre_schedule(sched, sched_job);
- 		fence = sched->ops->run_job(sched_job);
- 		amd_sched_fence_scheduled(s_fence);
- 		if (fence) {
-@@ -527,6 +537,8 @@ int amd_sched_init(struct amd_gpu_scheduler *sched,
- 
- 	init_waitqueue_head(&sched->wake_up_worker);
- 	init_waitqueue_head(&sched->job_scheduled);
-+	INIT_LIST_HEAD(&sched->ring_mirror_list);
-+	spin_lock_init(&sched->job_list_lock);
- 	atomic_set(&sched->hw_rq_count, 0);
- 	if (atomic_inc_return(&sched_fence_slab_ref) == 1) {
- 		sched_fence_slab = kmem_cache_create(
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index ee1e812..2e3b830 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -76,6 +76,7 @@ struct amd_sched_fence {
- 	void                            *owner;
- 	struct delayed_work		dwork;
- 	struct list_head		list;
-+	struct amd_sched_job 	*s_job;
- };
- 
- struct amd_sched_job {
-@@ -85,6 +86,7 @@ struct amd_sched_job {
- 	bool	use_sched;	/* true if the job goes to scheduler */
- 	struct fence_cb                cb_free_job;
- 	struct work_struct             work_free_job;
-+	struct list_head			   node;
- };
- 
- extern const struct fence_ops amd_sched_fence_ops;
-@@ -128,6 +130,8 @@ struct amd_gpu_scheduler {
- 	struct list_head		fence_list;
- 	spinlock_t			fence_list_lock;
- 	struct task_struct		*thread;
-+	struct list_head	ring_mirror_list;
-+	spinlock_t			job_list_lock;
- };
- 
- int amd_sched_init(struct amd_gpu_scheduler *sched,
-@@ -151,4 +155,6 @@ int amd_sched_job_init(struct amd_sched_job *job,
- 					struct amd_gpu_scheduler *sched,
- 					struct amd_sched_entity *entity,
- 					void *owner, struct fence **fence);
-+void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched ,
-+								struct amd_sched_job *s_job);
- #endif
-diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c
-index dc115ae..33ddd38 100644
---- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
-+++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c
-@@ -57,6 +57,15 @@ void amd_sched_fence_signal(struct amd_sched_fence *fence)
- 		FENCE_TRACE(&fence->base, "was already signaled\n");
- }
- 
-+void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched ,
-+				struct amd_sched_job *s_job)
-+{
-+	unsigned long flags;
-+	spin_lock_irqsave(&sched->job_list_lock, flags);
-+	list_add_tail(&s_job->node, &sched->ring_mirror_list);
-+	spin_unlock_irqrestore(&sched->job_list_lock, flags);
-+}
-+
- void amd_sched_fence_scheduled(struct amd_sched_fence *s_fence)
- {
- 	struct fence_cb *cur, *tmp;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0449-drm-amdgpu-get-rid-of-incorrect-TDR.patch b/common/recipes-kernel/linux/files/0449-drm-amdgpu-get-rid-of-incorrect-TDR.patch
deleted file mode 100644
index 6d7ec197..00000000
--- a/common/recipes-kernel/linux/files/0449-drm-amdgpu-get-rid-of-incorrect-TDR.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 8ff407d79fae9ff8f93ab3e024697a24da1c893f Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Fri, 4 Mar 2016 14:42:26 +0800
-Subject: [PATCH 0449/1110] drm/amdgpu: get rid of incorrect TDR
-
-original time out detect routine is incorrect, cuz it measures
-the gap from job scheduled, but we should only measure the
-gap from processed by hw.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 39 +--------------------------
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  4 ---
- 2 files changed, 1 insertion(+), 42 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index af846f2..9a9fffd 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -418,46 +418,18 @@ static void amd_sched_process_job(struct fence *f, struct fence_cb *cb)
- 	spin_unlock_irqrestore(&sched->job_list_lock, flags);
- 
- 	amd_sched_fence_signal(s_fence);
--	if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
--		cancel_delayed_work(&s_fence->dwork);
--		spin_lock_irqsave(&sched->fence_list_lock, flags);
--		list_del_init(&s_fence->list);
--		spin_unlock_irqrestore(&sched->fence_list_lock, flags);
--	}
-+
- 	trace_amd_sched_process_job(s_fence);
- 	fence_put(&s_fence->base);
- 	wake_up_interruptible(&sched->wake_up_worker);
- }
- 
--static void amd_sched_fence_work_func(struct work_struct *work)
--{
--	struct amd_sched_fence *s_fence =
--		container_of(work, struct amd_sched_fence, dwork.work);
--	struct amd_gpu_scheduler *sched = s_fence->sched;
--	struct amd_sched_fence *entity, *tmp;
--	unsigned long flags;
--
--	DRM_ERROR("[%s] scheduler is timeout!\n", sched->name);
--
--	/* Clean all pending fences */
--	spin_lock_irqsave(&sched->fence_list_lock, flags);
--	list_for_each_entry_safe(entity, tmp, &sched->fence_list, list) {
--		DRM_ERROR("  fence no %d\n", entity->base.seqno);
--		cancel_delayed_work(&entity->dwork);
--		list_del_init(&entity->list);
--		fence_put(&entity->base);
--	}
--	spin_unlock_irqrestore(&sched->fence_list_lock, flags);
--}
--
- static int amd_sched_main(void *param)
- {
- 	struct sched_param sparam = {.sched_priority = 1};
- 	struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param;
- 	int r, count;
- 
--	spin_lock_init(&sched->fence_list_lock);
--	INIT_LIST_HEAD(&sched->fence_list);
- 	sched_setscheduler(current, SCHED_FIFO, &sparam);
- 
- 	while (!kthread_should_stop()) {
-@@ -465,7 +437,6 @@ static int amd_sched_main(void *param)
- 		struct amd_sched_fence *s_fence;
- 		struct amd_sched_job *sched_job;
- 		struct fence *fence;
--		unsigned long flags;
- 
- 		wait_event_interruptible(sched->wake_up_worker,
- 			(entity = amd_sched_select_entity(sched)) ||
-@@ -480,14 +451,6 @@ static int amd_sched_main(void *param)
- 
- 		s_fence = sched_job->s_fence;
- 
--		if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
--			INIT_DELAYED_WORK(&s_fence->dwork, amd_sched_fence_work_func);
--			schedule_delayed_work(&s_fence->dwork, sched->timeout);
--			spin_lock_irqsave(&sched->fence_list_lock, flags);
--			list_add_tail(&s_fence->list, &sched->fence_list);
--			spin_unlock_irqrestore(&sched->fence_list_lock, flags);
--		}
--
- 		atomic_inc(&sched->hw_rq_count);
- 		amd_sched_job_pre_schedule(sched, sched_job);
- 		fence = sched->ops->run_job(sched_job);
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index 2e3b830..b26148d 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -74,8 +74,6 @@ struct amd_sched_fence {
- 	struct amd_gpu_scheduler	*sched;
- 	spinlock_t			lock;
- 	void                            *owner;
--	struct delayed_work		dwork;
--	struct list_head		list;
- 	struct amd_sched_job 	*s_job;
- };
- 
-@@ -127,8 +125,6 @@ struct amd_gpu_scheduler {
- 	wait_queue_head_t		wake_up_worker;
- 	wait_queue_head_t		job_scheduled;
- 	atomic_t			hw_rq_count;
--	struct list_head		fence_list;
--	spinlock_t			fence_list_lock;
- 	struct task_struct		*thread;
- 	struct list_head	ring_mirror_list;
- 	spinlock_t			job_list_lock;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0450-drm-amdgpu-rework-TDR-in-scheduler-v2.patch b/common/recipes-kernel/linux/files/0450-drm-amdgpu-rework-TDR-in-scheduler-v2.patch
deleted file mode 100644
index fa8684e2..00000000
--- a/common/recipes-kernel/linux/files/0450-drm-amdgpu-rework-TDR-in-scheduler-v2.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From 03d207575c7c3c6dfe7bf00fcb9c2129a562d009 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Fri, 4 Mar 2016 18:51:02 +0800
-Subject: [PATCH 0450/1110] drm/amdgpu: rework TDR in scheduler (v2)
-
-Add two callbacks to scheduler to maintain jobs, and invoked for
-job timeout calculations. Now TDR measures time gap from
-job is processed by hw.
-
-v2:
-fix typo
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c       | 16 +++++++++++-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 37 +++++++++++++++++++++++++++
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h |  7 +++++
- drivers/gpu/drm/amd/scheduler/sched_fence.c   |  1 +
- 6 files changed, 62 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 890844b..2474405 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -753,6 +753,7 @@ void amdgpu_job_free(struct amdgpu_job *job);
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-                       struct amd_sched_entity *entity, void *owner,
-                       struct fence **f);
-+void amdgpu_job_timeout_func(struct work_struct *work);
- 
- struct amdgpu_ring {
- 	struct amdgpu_device		*adev;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index ed6d8b3..df923cf 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -923,6 +923,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 
-         r = amd_sched_job_init(&job->base, &ring->sched,
-                                                 &p->ctx->rings[ring->idx].entity,
-+                                                amdgpu_job_timeout_func,
-                                                 p->filp, &fence);
-         if (r) {
- 	
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index e593ed2..d00335a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -34,6 +34,15 @@ static void amdgpu_job_free_handler(struct work_struct *ws)
- 	kfree(job);
- }
- 
-+void amdgpu_job_timeout_func(struct work_struct *work)
-+{
-+	struct amdgpu_job *job = container_of(work, struct amdgpu_job, base.work_tdr.work);
-+	DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
-+				job->base.sched->name,
-+				(uint32_t)atomic_read(&job->ring->fence_drv.last_seq),
-+				job->ring->fence_drv.sync_seq);
-+}
-+
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-                     struct amdgpu_job **job)
- {
-@@ -102,7 +111,10 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-        if (!f)
-                return -EINVAL;
- 
--       r = amd_sched_job_init(&job->base, &ring->sched, entity, owner, &fence);
-+       r = amd_sched_job_init(&job->base, &ring->sched,
-+                                                       entity, owner,
-+                                                       amdgpu_job_timeout_func,
-+                                                       &fence);
-        if (r)
-                return r;
- 
-@@ -179,6 +191,8 @@ err:
- struct amd_sched_backend_ops amdgpu_sched_ops = {
-        .dependency = amdgpu_job_dependency,
-        .run_job = amdgpu_job_run,
-+       .begin_job = amd_sched_job_begin,
-+       .finish_job = amd_sched_job_finish,
- };
- 
- 
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 9a9fffd..b7e8071 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -324,6 +324,40 @@ static void amd_sched_free_job(struct fence *f, struct fence_cb *cb) {
- 	schedule_work(&job->work_free_job);
- }
- 
-+/* job_finish is called after hw fence signaled, and
-+ * the job had already been deleted from ring_mirror_list
-+ */
-+void amd_sched_job_finish(struct amd_sched_job *s_job)
-+{
-+	struct amd_sched_job *next;
-+	struct amd_gpu_scheduler *sched = s_job->sched;
-+
-+	if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
-+		cancel_delayed_work(&s_job->work_tdr); /*TODO: how to deal the case that tdr is running */
-+
-+		/* queue TDR for next job */
-+		next = list_first_entry_or_null(&sched->ring_mirror_list,
-+						struct amd_sched_job, node);
-+
-+		if (next) {
-+			INIT_DELAYED_WORK(&next->work_tdr, s_job->timeout_callback);
-+			schedule_delayed_work(&next->work_tdr, sched->timeout);
-+		}
-+	}
-+}
-+
-+void amd_sched_job_begin(struct amd_sched_job *s_job)
-+{
-+	struct amd_gpu_scheduler *sched = s_job->sched;
-+
-+	if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
-+		list_first_entry_or_null(&sched->ring_mirror_list, struct amd_sched_job, node) == s_job)
-+	{
-+		INIT_DELAYED_WORK(&s_job->work_tdr, s_job->timeout_callback);
-+		schedule_delayed_work(&s_job->work_tdr, sched->timeout);
-+	}
-+}
-+
- /**
-  * Submit a job to the job queue
-  *
-@@ -347,6 +381,7 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
- int amd_sched_job_init(struct amd_sched_job *job,
- 						struct amd_gpu_scheduler *sched,
- 						struct amd_sched_entity *entity,
-+						void (*timeout_cb)(struct work_struct *work),
- 						void *owner, struct fence **fence)
- {
- 	INIT_LIST_HEAD(&job->node);
-@@ -357,6 +392,7 @@ int amd_sched_job_init(struct amd_sched_job *job,
- 		return -ENOMEM;
- 
- 	job->s_fence->s_job = job;
-+	job->timeout_callback = timeout_cb;
- 
- 	if (fence)
- 		*fence = &job->s_fence->base;
-@@ -415,6 +451,7 @@ static void amd_sched_process_job(struct fence *f, struct fence_cb *cb)
- 	/* remove job from ring_mirror_list */
- 	spin_lock_irqsave(&sched->job_list_lock, flags);
- 	list_del_init(&s_fence->s_job->node);
-+	sched->ops->finish_job(s_fence->s_job);
- 	spin_unlock_irqrestore(&sched->job_list_lock, flags);
- 
- 	amd_sched_fence_signal(s_fence);
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index b26148d..a5700ad 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -85,6 +85,8 @@ struct amd_sched_job {
- 	struct fence_cb                cb_free_job;
- 	struct work_struct             work_free_job;
- 	struct list_head			   node;
-+	struct delayed_work work_tdr;
-+	void (*timeout_callback) (struct work_struct *work);
- };
- 
- extern const struct fence_ops amd_sched_fence_ops;
-@@ -105,6 +107,8 @@ static inline struct amd_sched_fence *to_amd_sched_fence(struct fence *f)
- struct amd_sched_backend_ops {
- 	struct fence *(*dependency)(struct amd_sched_job *sched_job);
- 	struct fence *(*run_job)(struct amd_sched_job *sched_job);
-+	void (*begin_job)(struct amd_sched_job *sched_job);
-+	void (*finish_job)(struct amd_sched_job *sched_job);
- };
- 
- enum amd_sched_priority {
-@@ -150,7 +154,10 @@ void amd_sched_fence_signal(struct amd_sched_fence *fence);
- int amd_sched_job_init(struct amd_sched_job *job,
- 					struct amd_gpu_scheduler *sched,
- 					struct amd_sched_entity *entity,
-+					void (*timeout_cb)(struct work_struct *work),
- 					void *owner, struct fence **fence);
- void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched ,
- 								struct amd_sched_job *s_job);
-+void amd_sched_job_finish(struct amd_sched_job *s_job);
-+void amd_sched_job_begin(struct amd_sched_job *s_job);
- #endif
-diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c
-index 33ddd38..2a732c4 100644
---- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
-+++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c
-@@ -63,6 +63,7 @@ void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched ,
- 	unsigned long flags;
- 	spin_lock_irqsave(&sched->job_list_lock, flags);
- 	list_add_tail(&s_job->node, &sched->ring_mirror_list);
-+	sched->ops->begin_job(s_job);
- 	spin_unlock_irqrestore(&sched->job_list_lock, flags);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0451-drm-amdgpu-use-ref-to-keep-job-alive.patch b/common/recipes-kernel/linux/files/0451-drm-amdgpu-use-ref-to-keep-job-alive.patch
deleted file mode 100644
index 2f0edfd2..00000000
--- a/common/recipes-kernel/linux/files/0451-drm-amdgpu-use-ref-to-keep-job-alive.patch
+++ /dev/null
@@ -1,189 +0,0 @@
-From 2f62816bd4ac61ca50b157d900fbd02cc94a92aa Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 10 Mar 2016 12:14:44 +0800
-Subject: [PATCH 0451/1110] drm/amdgpu: use ref to keep job alive
-
-this is to fix fatal page fault error that occured if:
-job is signaled/released after its timeout work is already
-put to the global queue (in this case the cancel_delayed_work
-will return false), which will lead to NX-protection error
-page fault during job_timeout_func.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c       | 15 ++++++++++++---
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  8 +++++++-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 13 +++++++++++++
- 5 files changed, 34 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 2474405..b0aeca5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -750,6 +750,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
-                              struct amdgpu_job **job);
- 
- void amdgpu_job_free(struct amdgpu_job *job);
-+void amdgpu_job_free_func(struct kref *refcount);
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-                       struct amd_sched_entity *entity, void *owner,
-                       struct fence **f);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index df923cf..807670c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -924,6 +924,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
-         r = amd_sched_job_init(&job->base, &ring->sched,
-                                                 &p->ctx->rings[ring->idx].entity,
-                                                 amdgpu_job_timeout_func,
-+                                                amdgpu_job_free_func,
-                                                 p->filp, &fence);
-         if (r) {
- 	
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index d00335a..7b4bbcc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -31,7 +31,7 @@
- static void amdgpu_job_free_handler(struct work_struct *ws)
- {
- 	struct amdgpu_job *job = container_of(ws, struct amdgpu_job, base.work_free_job);
--	kfree(job);
-+	amd_sched_job_put(&job->base);
- }
- 
- void amdgpu_job_timeout_func(struct work_struct *work)
-@@ -41,6 +41,8 @@ void amdgpu_job_timeout_func(struct work_struct *work)
- 				job->base.sched->name,
- 				(uint32_t)atomic_read(&job->ring->fence_drv.last_seq),
- 				job->ring->fence_drv.sync_seq);
-+
-+	amd_sched_job_put(&job->base);
- }
- 
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-@@ -101,6 +103,12 @@ void amdgpu_job_free(struct amdgpu_job *job)
-                 kfree(job);
- }
- 
-+void amdgpu_job_free_func(struct kref *refcount)
-+{
-+	struct amdgpu_job *job = container_of(refcount, struct amdgpu_job, base.refcount);
-+	kfree(job);
-+}
-+
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-                       struct amd_sched_entity *entity, void *owner,
-                       struct fence **f)
-@@ -112,9 +120,10 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-                return -EINVAL;
- 
-        r = amd_sched_job_init(&job->base, &ring->sched,
--                                                       entity, owner,
-+                                                       entity,
-                                                        amdgpu_job_timeout_func,
--                                                       &fence);
-+                                                       amdgpu_job_free_func,
-+                                                       owner, &fence);
-        if (r)
-                return r;
- 
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index b7e8071..639c70d 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -333,7 +333,8 @@ void amd_sched_job_finish(struct amd_sched_job *s_job)
- 	struct amd_gpu_scheduler *sched = s_job->sched;
- 
- 	if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
--		cancel_delayed_work(&s_job->work_tdr); /*TODO: how to deal the case that tdr is running */
-+		if (cancel_delayed_work(&s_job->work_tdr))
-+			amd_sched_job_put(s_job);
- 
- 		/* queue TDR for next job */
- 		next = list_first_entry_or_null(&sched->ring_mirror_list,
-@@ -341,6 +342,7 @@ void amd_sched_job_finish(struct amd_sched_job *s_job)
- 
- 		if (next) {
- 			INIT_DELAYED_WORK(&next->work_tdr, s_job->timeout_callback);
-+			amd_sched_job_get(next);
- 			schedule_delayed_work(&next->work_tdr, sched->timeout);
- 		}
- 	}
-@@ -354,6 +356,7 @@ void amd_sched_job_begin(struct amd_sched_job *s_job)
- 		list_first_entry_or_null(&sched->ring_mirror_list, struct amd_sched_job, node) == s_job)
- 	{
- 		INIT_DELAYED_WORK(&s_job->work_tdr, s_job->timeout_callback);
-+		amd_sched_job_get(s_job);
- 		schedule_delayed_work(&s_job->work_tdr, sched->timeout);
- 	}
- }
-@@ -382,9 +385,11 @@ int amd_sched_job_init(struct amd_sched_job *job,
- 						struct amd_gpu_scheduler *sched,
- 						struct amd_sched_entity *entity,
- 						void (*timeout_cb)(struct work_struct *work),
-+						void (*free_cb)(struct kref *refcount),
- 						void *owner, struct fence **fence)
- {
- 	INIT_LIST_HEAD(&job->node);
-+	kref_init(&job->refcount);
- 	job->sched = sched;
- 	job->s_entity = entity;
- 	job->s_fence = amd_sched_fence_create(entity, owner);
-@@ -393,6 +398,7 @@ int amd_sched_job_init(struct amd_sched_job *job,
- 
- 	job->s_fence->s_job = job;
- 	job->timeout_callback = timeout_cb;
-+	job->free_callback = free_cb;
- 
- 	if (fence)
- 		*fence = &job->s_fence->base;
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index a5700ad..95ebfd0 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -78,6 +78,7 @@ struct amd_sched_fence {
- };
- 
- struct amd_sched_job {
-+	struct kref refcount;
- 	struct amd_gpu_scheduler        *sched;
- 	struct amd_sched_entity         *s_entity;
- 	struct amd_sched_fence          *s_fence;
-@@ -87,6 +88,7 @@ struct amd_sched_job {
- 	struct list_head			   node;
- 	struct delayed_work work_tdr;
- 	void (*timeout_callback) (struct work_struct *work);
-+	void (*free_callback)(struct kref *refcount);
- };
- 
- extern const struct fence_ops amd_sched_fence_ops;
-@@ -155,9 +157,20 @@ int amd_sched_job_init(struct amd_sched_job *job,
- 					struct amd_gpu_scheduler *sched,
- 					struct amd_sched_entity *entity,
- 					void (*timeout_cb)(struct work_struct *work),
-+					void (*free_cb)(struct kref* refcount),
- 					void *owner, struct fence **fence);
- void amd_sched_job_pre_schedule(struct amd_gpu_scheduler *sched ,
- 								struct amd_sched_job *s_job);
- void amd_sched_job_finish(struct amd_sched_job *s_job);
- void amd_sched_job_begin(struct amd_sched_job *s_job);
-+static inline void amd_sched_job_get(struct amd_sched_job *job) {
-+	if (job)
-+		kref_get(&job->refcount);
-+}
-+
-+static inline void amd_sched_job_put(struct amd_sched_job *job) {
-+	if (job)
-+		kref_put(&job->refcount, job->free_callback);
-+}
-+
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0452-drm-amdgpu-fix-issue-that-can-t-set-vce-clock-gate.patch b/common/recipes-kernel/linux/files/0452-drm-amdgpu-fix-issue-that-can-t-set-vce-clock-gate.patch
deleted file mode 100644
index 07ae3a3e..00000000
--- a/common/recipes-kernel/linux/files/0452-drm-amdgpu-fix-issue-that-can-t-set-vce-clock-gate.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 8c7f27c3806f085ad54a2825f8cadbdca25d5330 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 16 Mar 2016 14:45:40 +0800
-Subject: [PATCH 0452/1110] drm/amdgpu: fix issue that can't set vce clock
- gate.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 18 +++++++++++++++++-
- 1 file changed, 17 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index c7e885b..fda89ec 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -44,7 +44,7 @@
- static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
- static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
- static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
--
-+static int vce_v2_0_wait_for_idle(void *handle);
- /**
-  * vce_v2_0_ring_get_rptr - get read pointer
-  *
-@@ -339,6 +339,21 @@ static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
- {
- 	u32 orig, tmp;
- 
-+	if (gated) {
-+		if (vce_v2_0_wait_for_idle(adev)) {
-+			DRM_INFO("VCE is busy, Can't set clock gateing");
-+			return;
-+		}
-+		WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
-+		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
-+		mdelay(100);
-+		WREG32(mmVCE_STATUS, 0);
-+	} else {
-+		WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
-+		WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
-+		mdelay(100);
-+	}
-+
- 	tmp = RREG32(mmVCE_CLOCK_GATING_B);
- 	tmp &= ~0x00060006;
- 	if (gated) {
-@@ -362,6 +377,7 @@ static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
- 
- 	if (gated)
- 		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
-+	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
- }
- 
- static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0453-drm-amdgpu-No-need-to-stop-hw-init-although-vce-s-st.patch b/common/recipes-kernel/linux/files/0453-drm-amdgpu-No-need-to-stop-hw-init-although-vce-s-st.patch
deleted file mode 100644
index 20a8b15a..00000000
--- a/common/recipes-kernel/linux/files/0453-drm-amdgpu-No-need-to-stop-hw-init-although-vce-s-st.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From ebeaf9918b6611e171b54faf18dd180f8abdfbf5 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 16 Mar 2016 14:48:18 +0800
-Subject: [PATCH 0453/1110] drm/amdgpu: No need to stop hw init although vce's
- state was not true.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-v2: add comment why ignore the error here.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index fda89ec..4440973 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -240,7 +240,8 @@ static int vce_v2_0_hw_init(void *handle)
- 
- 	r = vce_v2_0_start(adev);
- 	if (r)
--		return r;
-+/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
-+		return 0;
- 
- 	ring = &adev->vce.ring[0];
- 	ring->ready = true;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0454-drm-amdgpu-refine-code-for-code-style.patch b/common/recipes-kernel/linux/files/0454-drm-amdgpu-refine-code-for-code-style.patch
deleted file mode 100644
index aea02c32..00000000
--- a/common/recipes-kernel/linux/files/0454-drm-amdgpu-refine-code-for-code-style.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 63d9206bd8baa20754dff9ef61fe1e7abba5a28c Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 16 Mar 2016 15:17:18 +0800
-Subject: [PATCH 0454/1110] drm/amdgpu: refine code for code style.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index 4440973..c306cb9 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -319,7 +319,7 @@ static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
- 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
- 
- 		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
--    } else {
-+	} else {
- 		tmp = RREG32(mmVCE_CLOCK_GATING_B);
- 		tmp |= 0xe7;
- 		tmp &= ~0xe70000;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0455-drm-amd-amdgpu-Add-SW-clock-gating-support-to-UVD-5-.patch b/common/recipes-kernel/linux/files/0455-drm-amd-amdgpu-Add-SW-clock-gating-support-to-UVD-5-.patch
deleted file mode 100644
index 2702898d..00000000
--- a/common/recipes-kernel/linux/files/0455-drm-amd-amdgpu-Add-SW-clock-gating-support-to-UVD-5-.patch
+++ /dev/null
@@ -1,500 +0,0 @@
-From 9c8f86e4858d211006973b85726ac57e8c2c6a4e Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 23 Mar 2016 13:14:31 -0400
-Subject: [PATCH 0455/1110] drm/amd/amdgpu: Add SW clock gating support to UVD
- 5 and 6
-
-This patch adds support for software clock gating to UVD 5
-and UVD 6 blocks with a preliminary commented out hardware
-gating routine.
-
-Currently hardware gating does not work so it's not activated.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 115 ++++++++++++++
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 281 ++++++++++++++--------------------
- 2 files changed, 232 insertions(+), 164 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 16476d8..de459c8 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -31,6 +31,7 @@
- #include "uvd/uvd_5_0_sh_mask.h"
- #include "oss/oss_2_0_d.h"
- #include "oss/oss_2_0_sh_mask.h"
-+#include "vi.h"
- 
- static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
- static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
-@@ -754,14 +755,128 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
- 	return 0;
- }
- 
-+static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
-+{
-+	uint32_t data, data1, data2, suvd_flags;
-+
-+	data = RREG32(mmUVD_CGC_CTRL);
-+	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
-+	data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
-+
-+	data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
-+		  UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
-+
-+	suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
-+		     UVD_SUVD_CGC_GATE__SIT_MASK |
-+		     UVD_SUVD_CGC_GATE__SMP_MASK |
-+		     UVD_SUVD_CGC_GATE__SCM_MASK |
-+		     UVD_SUVD_CGC_GATE__SDB_MASK;
-+
-+	data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
-+		(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
-+		(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
-+
-+	data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
-+			UVD_CGC_CTRL__SYS_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_MODE_MASK |
-+			UVD_CGC_CTRL__MPEG2_MODE_MASK |
-+			UVD_CGC_CTRL__REGS_MODE_MASK |
-+			UVD_CGC_CTRL__RBC_MODE_MASK |
-+			UVD_CGC_CTRL__LMI_MC_MODE_MASK |
-+			UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
-+			UVD_CGC_CTRL__IDCT_MODE_MASK |
-+			UVD_CGC_CTRL__MPRD_MODE_MASK |
-+			UVD_CGC_CTRL__MPC_MODE_MASK |
-+			UVD_CGC_CTRL__LBSI_MODE_MASK |
-+			UVD_CGC_CTRL__LRBBM_MODE_MASK |
-+			UVD_CGC_CTRL__WCB_MODE_MASK |
-+			UVD_CGC_CTRL__VCPU_MODE_MASK |
-+			UVD_CGC_CTRL__JPEG_MODE_MASK |
-+			UVD_CGC_CTRL__SCPU_MODE_MASK);
-+	data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
-+	data1 |= suvd_flags;
-+
-+	WREG32(mmUVD_CGC_CTRL, data);
-+	WREG32(mmUVD_CGC_GATE, 0);
-+	WREG32(mmUVD_SUVD_CGC_GATE, data1);
-+	WREG32(mmUVD_SUVD_CGC_CTRL, data2);
-+}
-+
-+#if 0
-+static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
-+{
-+	uint32_t data, data1, cgc_flags, suvd_flags;
-+
-+	data = RREG32(mmUVD_CGC_GATE);
-+	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
-+
-+	cgc_flags = UVD_CGC_GATE__SYS_MASK |
-+				UVD_CGC_GATE__UDEC_MASK |
-+				UVD_CGC_GATE__MPEG2_MASK |
-+				UVD_CGC_GATE__RBC_MASK |
-+				UVD_CGC_GATE__LMI_MC_MASK |
-+				UVD_CGC_GATE__IDCT_MASK |
-+				UVD_CGC_GATE__MPRD_MASK |
-+				UVD_CGC_GATE__MPC_MASK |
-+				UVD_CGC_GATE__LBSI_MASK |
-+				UVD_CGC_GATE__LRBBM_MASK |
-+				UVD_CGC_GATE__UDEC_RE_MASK |
-+				UVD_CGC_GATE__UDEC_CM_MASK |
-+				UVD_CGC_GATE__UDEC_IT_MASK |
-+				UVD_CGC_GATE__UDEC_DB_MASK |
-+				UVD_CGC_GATE__UDEC_MP_MASK |
-+				UVD_CGC_GATE__WCB_MASK |
-+				UVD_CGC_GATE__VCPU_MASK |
-+				UVD_CGC_GATE__SCPU_MASK;
-+
-+	suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_MASK |
-+				UVD_SUVD_CGC_GATE__SMP_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_MASK;
-+
-+	data |= cgc_flags;
-+	data1 |= suvd_flags;
-+
-+	WREG32(mmUVD_CGC_GATE, data);
-+	WREG32(mmUVD_SUVD_CGC_GATE, data1);
-+}
-+#endif
-+
- static int uvd_v5_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
-+	static int curstate = -1;
- 
- 	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
- 		return 0;
- 
-+	if (curstate == state)
-+		return 0;
-+
-+	curstate = state;
-+	if (enable) {
-+		/* disable HW gating and enable Sw gating */
-+		uvd_v5_0_set_sw_clock_gating(adev);
-+	} else {
-+		/* wait for STATUS to clear */
-+		if (uvd_v5_0_wait_for_idle(handle))
-+			return -EBUSY;
-+
-+		/* enable HW gates because UVD is idle */
-+/*		uvd_v5_0_set_hw_clock_gating(adev); */
-+	}
-+
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index d493791..372d70a 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -31,11 +31,13 @@
- #include "uvd/uvd_6_0_sh_mask.h"
- #include "oss/oss_2_0_d.h"
- #include "oss/oss_2_0_sh_mask.h"
-+#include "vi.h"
- 
- static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
- static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
- static int uvd_v6_0_start(struct amdgpu_device *adev);
- static void uvd_v6_0_stop(struct amdgpu_device *adev);
-+static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
- 
- /**
-  * uvd_v6_0_ring_get_rptr - get read pointer
-@@ -284,6 +286,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
- 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- }
- 
-+#if 0
- static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
- 		bool enable)
- {
-@@ -360,157 +363,7 @@ static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
- 	WREG32(mmUVD_CGC_GATE, data);
- 	WREG32(mmUVD_SUVD_CGC_GATE, data1);
- }
--
--static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
--		bool enable)
--{
--	u32 data, data1;
--
--	data = RREG32(mmUVD_CGC_GATE);
--	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
--	if (enable) {
--		data |= UVD_CGC_GATE__SYS_MASK |
--				UVD_CGC_GATE__UDEC_MASK |
--				UVD_CGC_GATE__MPEG2_MASK |
--				UVD_CGC_GATE__RBC_MASK |
--				UVD_CGC_GATE__LMI_MC_MASK |
--				UVD_CGC_GATE__IDCT_MASK |
--				UVD_CGC_GATE__MPRD_MASK |
--				UVD_CGC_GATE__MPC_MASK |
--				UVD_CGC_GATE__LBSI_MASK |
--				UVD_CGC_GATE__LRBBM_MASK |
--				UVD_CGC_GATE__UDEC_RE_MASK |
--				UVD_CGC_GATE__UDEC_CM_MASK |
--				UVD_CGC_GATE__UDEC_IT_MASK |
--				UVD_CGC_GATE__UDEC_DB_MASK |
--				UVD_CGC_GATE__UDEC_MP_MASK |
--				UVD_CGC_GATE__WCB_MASK |
--				UVD_CGC_GATE__VCPU_MASK |
--				UVD_CGC_GATE__SCPU_MASK;
--		data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
--				UVD_SUVD_CGC_GATE__SIT_MASK |
--				UVD_SUVD_CGC_GATE__SMP_MASK |
--				UVD_SUVD_CGC_GATE__SCM_MASK |
--				UVD_SUVD_CGC_GATE__SDB_MASK;
--	} else {
--		data &= ~(UVD_CGC_GATE__SYS_MASK |
--				UVD_CGC_GATE__UDEC_MASK |
--				UVD_CGC_GATE__MPEG2_MASK |
--				UVD_CGC_GATE__RBC_MASK |
--				UVD_CGC_GATE__LMI_MC_MASK |
--				UVD_CGC_GATE__LMI_UMC_MASK |
--				UVD_CGC_GATE__IDCT_MASK |
--				UVD_CGC_GATE__MPRD_MASK |
--				UVD_CGC_GATE__MPC_MASK |
--				UVD_CGC_GATE__LBSI_MASK |
--				UVD_CGC_GATE__LRBBM_MASK |
--				UVD_CGC_GATE__UDEC_RE_MASK |
--				UVD_CGC_GATE__UDEC_CM_MASK |
--				UVD_CGC_GATE__UDEC_IT_MASK |
--				UVD_CGC_GATE__UDEC_DB_MASK |
--				UVD_CGC_GATE__UDEC_MP_MASK |
--				UVD_CGC_GATE__WCB_MASK |
--				UVD_CGC_GATE__VCPU_MASK |
--				UVD_CGC_GATE__SCPU_MASK);
--		data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
--				UVD_SUVD_CGC_GATE__SIT_MASK |
--				UVD_SUVD_CGC_GATE__SMP_MASK |
--				UVD_SUVD_CGC_GATE__SCM_MASK |
--				UVD_SUVD_CGC_GATE__SDB_MASK);
--	}
--	WREG32(mmUVD_CGC_GATE, data);
--	WREG32(mmUVD_SUVD_CGC_GATE, data1);
--}
--
--static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev,
--		bool swmode)
--{
--	u32 data, data1 = 0, data2;
--
--	/* Always un-gate UVD REGS bit */
--	data = RREG32(mmUVD_CGC_GATE);
--	data &= ~(UVD_CGC_GATE__REGS_MASK);
--	WREG32(mmUVD_CGC_GATE, data);
--
--	data = RREG32(mmUVD_CGC_CTRL);
--	data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
--			UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
--	data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
--			1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) |
--			4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY);
--
--	data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
--	if (swmode) {
--		data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
--				UVD_CGC_CTRL__SYS_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_MODE_MASK |
--				UVD_CGC_CTRL__MPEG2_MODE_MASK |
--				UVD_CGC_CTRL__REGS_MODE_MASK |
--				UVD_CGC_CTRL__RBC_MODE_MASK |
--				UVD_CGC_CTRL__LMI_MC_MODE_MASK |
--				UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
--				UVD_CGC_CTRL__IDCT_MODE_MASK |
--				UVD_CGC_CTRL__MPRD_MODE_MASK |
--				UVD_CGC_CTRL__MPC_MODE_MASK |
--				UVD_CGC_CTRL__LBSI_MODE_MASK |
--				UVD_CGC_CTRL__LRBBM_MODE_MASK |
--				UVD_CGC_CTRL__WCB_MODE_MASK |
--				UVD_CGC_CTRL__VCPU_MODE_MASK |
--				UVD_CGC_CTRL__JPEG_MODE_MASK |
--				UVD_CGC_CTRL__SCPU_MODE_MASK);
--		data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
--				UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK;
--		data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK;
--		data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID);
--		data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
--	} else {
--		data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
--				UVD_CGC_CTRL__SYS_MODE_MASK |
--				UVD_CGC_CTRL__UDEC_MODE_MASK |
--				UVD_CGC_CTRL__MPEG2_MODE_MASK |
--				UVD_CGC_CTRL__REGS_MODE_MASK |
--				UVD_CGC_CTRL__RBC_MODE_MASK |
--				UVD_CGC_CTRL__LMI_MC_MODE_MASK |
--				UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
--				UVD_CGC_CTRL__IDCT_MODE_MASK |
--				UVD_CGC_CTRL__MPRD_MODE_MASK |
--				UVD_CGC_CTRL__MPC_MODE_MASK |
--				UVD_CGC_CTRL__LBSI_MODE_MASK |
--				UVD_CGC_CTRL__LRBBM_MODE_MASK |
--				UVD_CGC_CTRL__WCB_MODE_MASK |
--				UVD_CGC_CTRL__VCPU_MODE_MASK |
--				UVD_CGC_CTRL__SCPU_MODE_MASK;
--		data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
--				UVD_SUVD_CGC_CTRL__SDB_MODE_MASK;
--	}
--	WREG32(mmUVD_CGC_CTRL, data);
--	WREG32(mmUVD_SUVD_CGC_CTRL, data2);
--
--	data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2);
--	data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
--			REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
--			REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
--	data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
--			REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
--			REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
--	data |= data1;
--	WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data);
--}
-+#endif
- 
- /**
-  * uvd_v6_0_start - start UVD block
-@@ -538,11 +391,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
- 
- 	/* Set dynamic clock gating in S/W control mode */
- 	if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
--		if (adev->flags & AMD_IS_APU)
--			cz_set_uvd_clock_gating_branches(adev, false);
--		else
--			tonga_set_uvd_clock_gating_branches(adev, false);
--		uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
-+		uvd_v6_0_set_sw_clock_gating(adev);
- 	} else {
- 		/* disable clock gating */
- 		uint32_t data = RREG32(mmUVD_CGC_CTRL);
-@@ -978,25 +827,129 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
- 	return 0;
- }
- 
-+static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
-+{
-+	uint32_t data, data1, data2, suvd_flags;
-+
-+	data = RREG32(mmUVD_CGC_CTRL);
-+	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
-+	data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
-+
-+	data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
-+		  UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
-+
-+	suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
-+		     UVD_SUVD_CGC_GATE__SIT_MASK |
-+		     UVD_SUVD_CGC_GATE__SMP_MASK |
-+		     UVD_SUVD_CGC_GATE__SCM_MASK |
-+		     UVD_SUVD_CGC_GATE__SDB_MASK;
-+
-+	data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
-+		(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
-+		(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
-+
-+	data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
-+			UVD_CGC_CTRL__SYS_MODE_MASK |
-+			UVD_CGC_CTRL__UDEC_MODE_MASK |
-+			UVD_CGC_CTRL__MPEG2_MODE_MASK |
-+			UVD_CGC_CTRL__REGS_MODE_MASK |
-+			UVD_CGC_CTRL__RBC_MODE_MASK |
-+			UVD_CGC_CTRL__LMI_MC_MODE_MASK |
-+			UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
-+			UVD_CGC_CTRL__IDCT_MODE_MASK |
-+			UVD_CGC_CTRL__MPRD_MODE_MASK |
-+			UVD_CGC_CTRL__MPC_MODE_MASK |
-+			UVD_CGC_CTRL__LBSI_MODE_MASK |
-+			UVD_CGC_CTRL__LRBBM_MODE_MASK |
-+			UVD_CGC_CTRL__WCB_MODE_MASK |
-+			UVD_CGC_CTRL__VCPU_MODE_MASK |
-+			UVD_CGC_CTRL__JPEG_MODE_MASK |
-+			UVD_CGC_CTRL__SCPU_MODE_MASK |
-+			UVD_CGC_CTRL__JPEG2_MODE_MASK);
-+	data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
-+			UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
-+	data1 |= suvd_flags;
-+
-+	WREG32(mmUVD_CGC_CTRL, data);
-+	WREG32(mmUVD_CGC_GATE, 0);
-+	WREG32(mmUVD_SUVD_CGC_GATE, data1);
-+	WREG32(mmUVD_SUVD_CGC_CTRL, data2);
-+}
-+
-+#if 0
-+static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
-+{
-+	uint32_t data, data1, cgc_flags, suvd_flags;
-+
-+	data = RREG32(mmUVD_CGC_GATE);
-+	data1 = RREG32(mmUVD_SUVD_CGC_GATE);
-+
-+	cgc_flags = UVD_CGC_GATE__SYS_MASK |
-+		UVD_CGC_GATE__UDEC_MASK |
-+		UVD_CGC_GATE__MPEG2_MASK |
-+		UVD_CGC_GATE__RBC_MASK |
-+		UVD_CGC_GATE__LMI_MC_MASK |
-+		UVD_CGC_GATE__IDCT_MASK |
-+		UVD_CGC_GATE__MPRD_MASK |
-+		UVD_CGC_GATE__MPC_MASK |
-+		UVD_CGC_GATE__LBSI_MASK |
-+		UVD_CGC_GATE__LRBBM_MASK |
-+		UVD_CGC_GATE__UDEC_RE_MASK |
-+		UVD_CGC_GATE__UDEC_CM_MASK |
-+		UVD_CGC_GATE__UDEC_IT_MASK |
-+		UVD_CGC_GATE__UDEC_DB_MASK |
-+		UVD_CGC_GATE__UDEC_MP_MASK |
-+		UVD_CGC_GATE__WCB_MASK |
-+		UVD_CGC_GATE__VCPU_MASK |
-+		UVD_CGC_GATE__SCPU_MASK |
-+		UVD_CGC_GATE__JPEG_MASK |
-+		UVD_CGC_GATE__JPEG2_MASK;
-+
-+	suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
-+				UVD_SUVD_CGC_GATE__SIT_MASK |
-+				UVD_SUVD_CGC_GATE__SMP_MASK |
-+				UVD_SUVD_CGC_GATE__SCM_MASK |
-+				UVD_SUVD_CGC_GATE__SDB_MASK;
-+
-+	data |= cgc_flags;
-+	data1 |= suvd_flags;
-+
-+	WREG32(mmUVD_CGC_GATE, data);
-+	WREG32(mmUVD_SUVD_CGC_GATE, data1);
-+}
-+#endif
-+
- static int uvd_v6_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
-+	static int curstate = -1;
- 
- 	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
- 		return 0;
- 
-+	if (curstate == state)
-+		return 0;
-+
-+	curstate = state;
- 	if (enable) {
--		if (adev->flags & AMD_IS_APU)
--			cz_set_uvd_clock_gating_branches(adev, enable);
--		else
--			tonga_set_uvd_clock_gating_branches(adev, enable);
--		uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
-+		/* disable HW gating and enable Sw gating */
-+		uvd_v6_0_set_sw_clock_gating(adev);
- 	} else {
--		uint32_t data = RREG32(mmUVD_CGC_CTRL);
--		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
--		WREG32(mmUVD_CGC_CTRL, data);
-+		/* wait for STATUS to clear */
-+		if (uvd_v6_0_wait_for_idle(handle))
-+			return -EBUSY;
-+
-+		/* enable HW gates because UVD is idle */
-+/*		uvd_v6_0_set_hw_clock_gating(adev); */
- 	}
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0456-drm-amd-amdgpu-Enable-clockgating-for-UVD5-on-Tonga.patch b/common/recipes-kernel/linux/files/0456-drm-amd-amdgpu-Enable-clockgating-for-UVD5-on-Tonga.patch
deleted file mode 100644
index 68a5edc8..00000000
--- a/common/recipes-kernel/linux/files/0456-drm-amd-amdgpu-Enable-clockgating-for-UVD5-on-Tonga.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From bdbf80d471e3752b2a725f52e81531a1ddddadf4 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 23 Mar 2016 13:16:13 -0400
-Subject: [PATCH 0456/1110] drm/amd/amdgpu: Enable clockgating for UVD5 on
- Tonga
-
-This patch enables clock gating for the UVD5 block with
-Tonga.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index a145556..5c39470 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1081,7 +1081,7 @@ static int vi_common_early_init(void *handle)
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
- 	case CHIP_TONGA:
--		adev->cg_flags = 0;
-+		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0457-drm-amd-amdgpu-Enable-clockgating-in-UVD6-for-Stoney.patch b/common/recipes-kernel/linux/files/0457-drm-amd-amdgpu-Enable-clockgating-in-UVD6-for-Stoney.patch
deleted file mode 100644
index cfcf5efb..00000000
--- a/common/recipes-kernel/linux/files/0457-drm-amd-amdgpu-Enable-clockgating-in-UVD6-for-Stoney.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 5d5fcf0a5b21571a4f9bc9179f465417deb132a8 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 23 Mar 2016 13:17:04 -0400
-Subject: [PATCH 0457/1110] drm/amd/amdgpu: Enable clockgating in UVD6 for
- Stoney
-
-This patch enables clockgating for the UVD6 block in Stoney.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 5c39470..3964790 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1086,11 +1086,15 @@ static int vi_common_early_init(void *handle)
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
- 	case CHIP_CARRIZO:
--	case CHIP_STONEY:
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
-+	case CHIP_STONEY:
-+		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
-+		adev->pg_flags = 0;
-+		adev->external_rev_id = adev->rev_id + 0x1;
-+		break;
- 	default:
- 		/* FIXME: not supported yet */
- 		return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0458-drm-amd-amdgpu-Enable-ability-to-print-register-stat.patch b/common/recipes-kernel/linux/files/0458-drm-amd-amdgpu-Enable-ability-to-print-register-stat.patch
deleted file mode 100644
index a2e6a8f1..00000000
--- a/common/recipes-kernel/linux/files/0458-drm-amd-amdgpu-Enable-ability-to-print-register-stat.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From 0f09539c772af43949b4358c6b45fe30a9b14861 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 28 Mar 2016 08:21:52 -0400
-Subject: [PATCH 0458/1110] drm/amd/amdgpu: Enable ability to print register
- status
-
-Added file "amdgpu_print_status" to debugfs and you can
-cat it to have the dmesg log populated with register values
-from various IP blocks.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 ++++++++++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 9663d17..f03fa47 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -47,6 +47,8 @@
- 
- static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
-+static int amdgpu_debugfs_status_init(struct amdgpu_device *adev);
-+
- 
- static const char *amdgpu_asic_name[] = {
- 	"BONAIRE",
-@@ -1110,6 +1112,15 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
- 	return NULL;
- }
- 
-+void amdgpu_print_status(struct amdgpu_device *adev)
-+{
-+	int i;
-+
-+	for (i = 0; i < adev->num_ip_blocks; i++)
-+		if (adev->ip_blocks[i].funcs->print_status)
-+			adev->ip_blocks[i].funcs->print_status(adev);
-+}
-+
- /**
-  * amdgpu_ip_block_version_cmp
-  *
-@@ -1258,6 +1269,8 @@ static int amdgpu_init(struct amdgpu_device *adev)
- 		adev->ip_block_status[i].hw = true;
- 	}
- 
-+	amdgpu_debugfs_status_init(adev);
-+
- 	return 0;
- }
- 
-@@ -2162,3 +2175,32 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
- }
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
- #endif
-+
-+/*
-+ * Status debugfs
-+ */
-+#if defined(CONFIG_DEBUG_FS)
-+static int amdgpu_debugfs_print_status(struct seq_file *m, void *data)
-+{
-+	struct drm_info_node *node = (struct drm_info_node *)m->private;
-+	struct drm_device *dev = node->minor->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	amdgpu_print_status(adev);
-+
-+	return 0;
-+}
-+
-+static struct drm_info_list amdgpu_debugfs_status_list[] = {
-+	{"amdgpu_print_status", &amdgpu_debugfs_print_status, 0, NULL},
-+};
-+#endif
-+
-+static int amdgpu_debugfs_status_init(struct amdgpu_device *adev)
-+{
-+#if defined(CONFIG_DEBUG_FS)
-+	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_status_list, 1);
-+#else
-+	return 0;
-+#endif
-+}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0459-drm-amd-powerplay-use-min_clock_in_sr-from-dal-for-d.patch b/common/recipes-kernel/linux/files/0459-drm-amd-powerplay-use-min_clock_in_sr-from-dal-for-d.patch
deleted file mode 100644
index 8ef2c974..00000000
--- a/common/recipes-kernel/linux/files/0459-drm-amd-powerplay-use-min_clock_in_sr-from-dal-for-d.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From d7c1d6682bea1c8adf97de23f7503b4ab848be3e Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 29 Mar 2016 19:32:37 +0800
-Subject: [PATCH 0459/1110] drm/amd/powerplay: use min_clock_in_sr from dal for
- deep sleep feature.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 50 ++++++++++++++----------
- 1 file changed, 30 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 89f31bc..025a3ed 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -1885,6 +1885,23 @@ static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
- 
- 	return 0;
- }
-+
-+static uint8_t fiji_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
-+						uint32_t clock, uint32_t clock_insr)
-+{
-+	uint8_t i;
-+	uint32_t temp;
-+	uint32_t min = clock_insr > 2500 ? clock_insr : 2500;
-+
-+	PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
-+	for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
-+		temp = clock / (1UL << i);
-+
-+		if (temp >= min || i == 0)
-+			break;
-+	}
-+	return i;
-+}
- /**
- * Populates single SMC SCLK structure using the provided engine clock
- *
-@@ -1928,17 +1945,13 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- 
- 	threshold = clock * data->fast_watermark_threshold / 100;
- 
--	/*
--	* TODO: get minimum clocks from dal configaration
--	* PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
--	*/
--	/* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
- 
--	/* get level->DeepSleepDivId
--	if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
--	{
--	level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
--	} */
-+	data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+		level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(hwmgr, clock,
-+								hwmgr->display_config.min_core_set_clock_in_sr);
-+
- 
- 	/* Default to slow, highest DPM level will be
- 	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-@@ -4066,7 +4079,6 @@ static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
- 	struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
- 	uint32_t mclk = fiji_ps->performance_levels
- 			[fiji_ps->performance_level_count - 1].memory_clock;
--	struct PP_Clocks min_clocks = {0};
- 	uint32_t i;
- 	struct cgs_display_info info = {0};
- 
-@@ -4080,10 +4092,8 @@ static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
- 	if (i >= sclk_table->count)
- 		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
- 	else {
--	/* TODO: Check SCLK in DAL's minimum clocks
--	 * in case DeepSleep divider update is required.
--	 */
--		if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
-+		if(data->display_timing.min_clock_in_sr !=
-+			hwmgr->display_config.min_core_set_clock_in_sr)
- 			data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
- 	}
- 
-@@ -5252,12 +5262,12 @@ bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h
- 
- 	if (data->display_timing.num_existing_displays != info.display_count)
- 		is_update_required = true;
--/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
--	if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
--		cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
--		if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+		if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr)
- 			is_update_required = true;
--*/
-+	}
-+
- 	return is_update_required;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0460-drm-amdgpu-drop-the-GTT-power-of-two-limit.patch b/common/recipes-kernel/linux/files/0460-drm-amdgpu-drop-the-GTT-power-of-two-limit.patch
deleted file mode 100644
index cba9e21a..00000000
--- a/common/recipes-kernel/linux/files/0460-drm-amdgpu-drop-the-GTT-power-of-two-limit.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 664866d235f148e39aab0e04bedbd243f54cc195 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Thu, 17 Mar 2016 16:25:15 +0100
-Subject: [PATCH 0460/1110] drm/amdgpu: drop the GTT power of two limit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-As far as I can see that isn't neccessary any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-----
- 1 file changed, 1 insertion(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index f03fa47..fd52a04 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -938,15 +938,11 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
- 	}
- 
- 	if (amdgpu_gart_size != -1) {
--		/* gtt size must be power of two and greater or equal to 32M */
-+		/* gtt size must be greater or equal to 32M */
- 		if (amdgpu_gart_size < 32) {
- 			dev_warn(adev->dev, "gart size (%d) too small\n",
- 				 amdgpu_gart_size);
- 			amdgpu_gart_size = -1;
--		} else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
--			dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
--				 amdgpu_gart_size);
--			amdgpu_gart_size = -1;
- 		}
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0461-drm-amdgpu-change-parameter-passing-in-the-VM-code.patch b/common/recipes-kernel/linux/files/0461-drm-amdgpu-change-parameter-passing-in-the-VM-code.patch
deleted file mode 100644
index 8d417e54..00000000
--- a/common/recipes-kernel/linux/files/0461-drm-amdgpu-change-parameter-passing-in-the-VM-code.patch
+++ /dev/null
@@ -1,324 +0,0 @@
-From 7d78c8e4a3fe6f5735c815db7d285a803c62d0df Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 18 Mar 2016 21:00:35 +0100
-Subject: [PATCH 0461/1110] drm/amdgpu: change parameter passing in the VM code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Make it more flexible by passing src and page addresses
-directly instead of the structures they contain.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 100 ++++++++++++++++++---------------
- 1 file changed, 54 insertions(+), 46 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index ac4e092..4db8a2b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -356,8 +356,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
-  * amdgpu_vm_update_pages - helper to call the right asic function
-  *
-  * @adev: amdgpu_device pointer
-- * @gtt: GART instance to use for mapping
-- * @gtt_flags: GTT hw access flags
-+ * @src: address where to copy page table entries from
-+ * @pages_addr: DMA addresses to use for mapping
-  * @ib: indirect buffer to fill with commands
-  * @pe: addr of the page entry
-  * @addr: dst addr to write into pe
-@@ -369,8 +369,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
-  * to setup the page table using the DMA.
-  */
- static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
--				   struct amdgpu_gart *gtt,
--				   uint32_t gtt_flags,
-+				   uint64_t src,
-+				   dma_addr_t *pages_addr,
- 				   struct amdgpu_ib *ib,
- 				   uint64_t pe, uint64_t addr,
- 				   unsigned count, uint32_t incr,
-@@ -378,12 +378,11 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
- {
- 	trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
- 
--	if ((gtt == &adev->gart) && (flags == gtt_flags)) {
--		uint64_t src = gtt->table_addr + (addr >> 12) * 8;
-+	if (src) {
-+		src += (addr >> 12) * 8;
- 		amdgpu_vm_copy_pte(adev, ib, pe, src, count);
- 
--	} else if (gtt) {
--		dma_addr_t *pages_addr = gtt->pages_addr;
-+	} else if (pages_addr) {
- 		amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
- 				    count, incr, flags);
- 
-@@ -432,7 +431,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
-         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
-         if (r)
- 		goto error;
--        amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries,
-+        amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries,
-                                 0, 0);
-         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
- 
-@@ -538,7 +537,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 		    ((last_pt + incr * count) != pt)) {
- 
- 			if (count) {
--				amdgpu_vm_update_pages(adev, NULL, 0, ib,
-+				amdgpu_vm_update_pages(adev, 0, NULL, ib,
- 						       last_pde, last_pt,
- 						       count, incr,
- 						       AMDGPU_PTE_VALID);
-@@ -553,7 +552,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 	}
- 
- 	if (count)
--		amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt,
-+		amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt,
- 				       count, incr, AMDGPU_PTE_VALID);
- 
- 	if (ib->length_dw != 0) {
-@@ -584,8 +583,8 @@ error_free:
-  * amdgpu_vm_frag_ptes - add fragment information to PTEs
-  *
-  * @adev: amdgpu_device pointer
-- * @gtt: GART instance to use for mapping
-- * @gtt_flags: GTT hw mapping flags
-+ * @src: address where to copy page table entries from
-+ * @pages_addr: DMA addresses to use for mapping
-  * @ib: IB for the update
-  * @pe_start: first PTE to handle
-  * @pe_end: last PTE to handle
-@@ -595,8 +594,8 @@ error_free:
-  * Global and local mutex must be locked!
-  */
- static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
--				struct amdgpu_gart *gtt,
--				uint32_t gtt_flags,
-+                                uint64_t src,
-+                                dma_addr_t *pages_addr,
- 				struct amdgpu_ib *ib,
- 				uint64_t pe_start, uint64_t pe_end,
- 				uint64_t addr, uint32_t flags)
-@@ -634,10 +633,11 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-                 return;
- 
- 	/* system pages are non continuously */
--	if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) {
-+        if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) ||
-+            (frag_start >= frag_end)) {
- 
- 		count = (pe_end - pe_start) / 8;
--		amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start,
-+                amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start,
- 				       addr, count, AMDGPU_GPU_PAGE_SIZE,
- 				       flags);
- 		return;
-@@ -646,21 +646,21 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
- 	/* handle the 4K area at the beginning */
- 	if (pe_start != frag_start) {
- 		count = (frag_start - pe_start) / 8;
--		amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr,
-+		amdgpu_vm_update_pages(adev, 0, NULL, ib, pe_start, addr,
- 				       count, AMDGPU_GPU_PAGE_SIZE, flags);
- 		addr += AMDGPU_GPU_PAGE_SIZE * count;
- 	}
- 
- 	/* handle the area in the middle */
- 	count = (frag_end - frag_start) / 8;
--	amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count,
-+	amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_start, addr, count,
- 			       AMDGPU_GPU_PAGE_SIZE, flags | frag_flags);
- 
- 	/* handle the 4K area at the end */
- 	if (frag_end != pe_end) {
- 		addr += AMDGPU_GPU_PAGE_SIZE * count;
- 		count = (pe_end - frag_end) / 8;
--		amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr,
-+		amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_end, addr,
- 				       count, AMDGPU_GPU_PAGE_SIZE, flags);
- 	}
- }
-@@ -669,8 +669,8 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  * amdgpu_vm_update_ptes - make sure that page tables are valid
-  *
-  * @adev: amdgpu_device pointer
-- * @gtt: GART instance to use for mapping
-- * @gtt_flags: GTT hw mapping flags
-+ * @src: address where to copy page table entries from
-+ * @pages_addr: DMA addresses to use for mapping
-  * @vm: requested vm
-  * @start: start of GPU address range
-  * @end: end of GPU address range
-@@ -680,8 +680,8 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  * Update the page tables in the range @start - @end.
-  */
- static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
--                                  struct amdgpu_gart *gtt,
--                                  uint32_t gtt_flags,
-+                                  uint64_t src,
-+                                  dma_addr_t *pages_addr,
-                                   struct amdgpu_vm *vm,
-                                   struct amdgpu_ib *ib,
-                                   uint64_t start, uint64_t end,
-@@ -712,7 +712,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 
-                 if (last_pe_end != pe_start) {
- 
--                        amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
-+                        amdgpu_vm_frag_ptes(adev, src, pages_addr, ib,
-                                             last_pe_start, last_pe_end,
-                                             last_dst, flags);
-  
-@@ -727,17 +727,16 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
- 		dst += nptes * AMDGPU_GPU_PAGE_SIZE;
- 	}
- 
--        amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib,
--                            last_pe_start, last_pe_end,
--                            last_dst, flags);
-+        amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start,
-+                           last_pe_end, last_dst, flags);
- }
- 
- /**
-  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
-  *
-  * @adev: amdgpu_device pointer
-- * @gtt: GART instance to use for mapping
-- * @gtt_flags: flags as they are used for GTT
-+ * @src: address where to copy page table entries from
-+ * @pages_addr: DMA addresses to use for mapping
-  * @vm: requested vm
-  * @start: start of mapped range
-  * @last: last mapped entry
-@@ -749,8 +748,8 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-  * Returns 0 for success, -EINVAL for failure.
-  */
- static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
--				       struct amdgpu_gart *gtt,
--				       uint32_t gtt_flags,
-+				       uint64_t src,
-+				       dma_addr_t *pages_addr,
- 				       struct amdgpu_vm *vm,
- 				       uint64_t start, uint64_t last,
- 				       uint32_t flags, uint64_t addr,
-@@ -781,11 +780,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	/* padding, etc. */
- 	ndw = 64;
- 
--	if ((gtt == &adev->gart) && (flags == gtt_flags)) {
-+	if (src) {
- 		/* only copy commands needed */
- 		ndw += ncmds * 7;
- 
--	} else if (gtt) {
-+	} else if (pages_addr) {
- 		/* header for write data commands */
- 		ndw += ncmds * 4;
- 
-@@ -815,8 +814,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
-         if (r)
-                 goto error_free;
-  
--        amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1,
--                              addr, flags);
-+        amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start,
-+                              last + 1, addr, flags);
- 
-         amdgpu_ring_pad_ib(ring, ib);
- 	WARN_ON(ib->length_dw > ndw);
-@@ -858,12 +857,13 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 				      uint32_t gtt_flags,
- 				      struct amdgpu_vm *vm,
- 				      struct amdgpu_bo_va_mapping *mapping,
--				      uint64_t addr, struct fence **fence)
-+				      uint32_t flags, uint64_t addr,
-+				      struct fence **fence)
- {
- 	const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
- 
--	uint64_t start = mapping->it.start;
--	uint32_t flags = gtt_flags;
-+	uint64_t src = 0, start = mapping->it.start;
-+	dma_addr_t *pages_addr = NULL;
- 	int r;
- 
- 	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
-@@ -876,10 +876,17 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 
- 	trace_amdgpu_vm_bo_update(mapping);
- 
-+	if (gtt) {
-+		if (flags == gtt_flags)
-+			src = adev->gart.table_addr + (addr >> 12) * 8;
-+		else
-+			pages_addr = &gtt->pages_addr[addr >> 12];
-+		addr = 0;
-+	}
- 	addr += mapping->offset;
- 
--	if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags)))
--		return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm,
-+	if (!gtt || src)
-+		return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm,
- 						   start, mapping->it.last,
- 						   flags, addr, fence);
- 
-@@ -887,7 +894,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 		uint64_t last;
- 
- 		last = min((uint64_t)mapping->it.last, start + max_size - 1);
--		r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm,
-+		r = amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm,
- 						start, last, flags, addr,
- 						fence);
- 		if (r)
-@@ -919,7 +926,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 	struct amdgpu_vm *vm = bo_va->vm;
- 	struct amdgpu_bo_va_mapping *mapping;
- 	struct amdgpu_gart *gtt = NULL;
--	uint32_t flags;
-+	uint32_t gtt_flags, flags;
- 	uint64_t addr;
- 	int r;
- 
-@@ -942,6 +949,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 	}
- 
- 	flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
-+	gtt_flags = (adev == bo_va->bo->adev) ? flags : 0;
- 
- 	spin_lock(&vm->status_lock);
- 	if (!list_empty(&bo_va->vm_status))
-@@ -949,8 +957,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 	spin_unlock(&vm->status_lock);
- 
- 	list_for_each_entry(mapping, &bo_va->invalids, list) {
--		r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr,
--					       &bo_va->last_pt_update);
-+		r = amdgpu_vm_bo_split_mapping(adev, gtt, gtt_flags, vm, mapping,
-+					       flags, addr, &bo_va->last_pt_update);
- 		if (r)
- 			return r;
- 	}
-@@ -996,7 +1004,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
- 		list_del(&mapping->list);
- 
- 		r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping,
--					       0, NULL);
-+					       0, 0, NULL);
- 		kfree(mapping);
- 		if (r)
- 			return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0462-drm-amdgpu-use-BO-pages-instead-of-GART-array.patch b/common/recipes-kernel/linux/files/0462-drm-amdgpu-use-BO-pages-instead-of-GART-array.patch
deleted file mode 100644
index 5da2dfa2..00000000
--- a/common/recipes-kernel/linux/files/0462-drm-amdgpu-use-BO-pages-instead-of-GART-array.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From 964ff8398005bfecd36c29bb6a25084a3054b286 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 30 Mar 2016 10:50:25 +0200
-Subject: [PATCH 0462/1110] drm/amdgpu: use BO pages instead of GART array
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 ++++++++++++++++-------------
- 1 file changed, 16 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 4db8a2b..0b9b03f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -841,11 +841,12 @@ error_free:
-  * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
-  *
-  * @adev: amdgpu_device pointer
-- * @gtt: GART instance to use for mapping
-+ * @gtt_flags: flags as they are used for GTT
-+ * @pages_addr: DMA addresses to use for mapping
-  * @vm: requested vm
-  * @mapping: mapped range and flags to use for the update
-  * @addr: addr to set the area to
-- * @gtt_flags: flags as they are used for GTT
-+ * @flags: HW flags for the mapping
-  * @fence: optional resulting fence
-  *
-  * Split the mapping into smaller chunks so that each update fits
-@@ -853,8 +854,8 @@ error_free:
-  * Returns 0 for success, -EINVAL for failure.
-  */
- static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
--				      struct amdgpu_gart *gtt,
- 				      uint32_t gtt_flags,
-+				      dma_addr_t *pages_addr,
- 				      struct amdgpu_vm *vm,
- 				      struct amdgpu_bo_va_mapping *mapping,
- 				      uint32_t flags, uint64_t addr,
-@@ -863,7 +864,6 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 	const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
- 
- 	uint64_t src = 0, start = mapping->it.start;
--	dma_addr_t *pages_addr = NULL;
- 	int r;
- 
- 	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
-@@ -876,16 +876,14 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
- 
- 	trace_amdgpu_vm_bo_update(mapping);
- 
--	if (gtt) {
-+	if (pages_addr) {
- 		if (flags == gtt_flags)
- 			src = adev->gart.table_addr + (addr >> 12) * 8;
--		else
--			pages_addr = &gtt->pages_addr[addr >> 12];
- 		addr = 0;
- 	}
- 	addr += mapping->offset;
- 
--	if (!gtt || src)
-+	if (!pages_addr || src)
- 		return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm,
- 						   start, mapping->it.last,
- 						   flags, addr, fence);
-@@ -925,16 +923,20 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- {
- 	struct amdgpu_vm *vm = bo_va->vm;
- 	struct amdgpu_bo_va_mapping *mapping;
--	struct amdgpu_gart *gtt = NULL;
-+	dma_addr_t *pages_addr = NULL;
- 	uint32_t gtt_flags, flags;
- 	uint64_t addr;
- 	int r;
- 
- 	if (mem) {
-+		struct ttm_dma_tt *ttm;
-+
- 		addr = (u64)mem->start << PAGE_SHIFT;
- 		switch (mem->mem_type) {
- 		case TTM_PL_TT:
--			gtt = &bo_va->bo->adev->gart;
-+			ttm = container_of(bo_va->bo->tbo.ttm, struct
-+					   ttm_dma_tt, ttm);
-+			pages_addr = ttm->dma_address;
- 			break;
- 
- 		case TTM_PL_VRAM:
-@@ -957,8 +959,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 	spin_unlock(&vm->status_lock);
- 
- 	list_for_each_entry(mapping, &bo_va->invalids, list) {
--		r = amdgpu_vm_bo_split_mapping(adev, gtt, gtt_flags, vm, mapping,
--					       flags, addr, &bo_va->last_pt_update);
-+		r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm,
-+					       mapping, flags, addr,
-+					       &bo_va->last_pt_update);
- 		if (r)
- 			return r;
- 	}
-@@ -1003,7 +1006,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
- 			struct amdgpu_bo_va_mapping, list);
- 		list_del(&mapping->list);
- 
--		r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping,
-+		r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping,
- 					       0, 0, NULL);
- 		kfree(mapping);
- 		if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0463-drm-amdgpu-remove-GART-page-addr-array.patch b/common/recipes-kernel/linux/files/0463-drm-amdgpu-remove-GART-page-addr-array.patch
deleted file mode 100644
index f94500ca..00000000
--- a/common/recipes-kernel/linux/files/0463-drm-amdgpu-remove-GART-page-addr-array.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From 20b0721a30fa5b190ffa239845f82eaca62163ee Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 30 Mar 2016 10:54:16 +0200
-Subject: [PATCH 0463/1110] drm/amdgpu: remove GART page addr array
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not needed any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  1 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 22 ++++------------------
- 2 files changed, 4 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index b0aeca5..35e07fb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -613,7 +613,6 @@ struct amdgpu_gart {
- 	unsigned			num_cpu_pages;
- 	unsigned			table_size;
- 	struct page			**pages;
--	dma_addr_t			*pages_addr;
- 	bool				ready;
- 	const struct amdgpu_gart_funcs *gart_funcs;
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
-index 7312d72..a13603a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
-@@ -240,8 +240,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
- 	for (i = 0; i < pages; i++, p++) {
- 		if (adev->gart.pages[p]) {
- 			adev->gart.pages[p] = NULL;
--			adev->gart.pages_addr[p] = adev->dummy_page.addr;
--			page_base = adev->gart.pages_addr[p];
-+			page_base = adev->dummy_page.addr;
- 			if (!adev->gart.ptr)
- 				continue;
- 
-@@ -287,10 +286,9 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
- 	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
- 
- 	for (i = 0; i < pages; i++, p++) {
--		adev->gart.pages_addr[p] = dma_addr[i];
- 		adev->gart.pages[p] = pagelist[i];
- 		if (adev->gart.ptr) {
--			page_base = adev->gart.pages_addr[p];
-+			page_base = dma_addr[i];
- 			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
- 				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
- 				page_base += AMDGPU_GPU_PAGE_SIZE;
-@@ -312,7 +310,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
-  */
- int amdgpu_gart_init(struct amdgpu_device *adev)
- {
--	int r, i;
-+	int r;
- 
- 	if (adev->gart.pages) {
- 		return 0;
-@@ -336,16 +334,6 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
- 		amdgpu_gart_fini(adev);
- 		return -ENOMEM;
- 	}
--	adev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
--					adev->gart.num_cpu_pages);
--	if (adev->gart.pages_addr == NULL) {
--		amdgpu_gart_fini(adev);
--		return -ENOMEM;
--	}
--	/* set GART entry to point to the dummy page by default */
--	for (i = 0; i < adev->gart.num_cpu_pages; i++) {
--		adev->gart.pages_addr[i] = adev->dummy_page.addr;
--	}
- 	return 0;
- }
- 
-@@ -358,15 +346,13 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
-  */
- void amdgpu_gart_fini(struct amdgpu_device *adev)
- {
--	if (adev->gart.pages && adev->gart.pages_addr && adev->gart.ready) {
-+	if (adev->gart.pages && adev->gart.ready) {
- 		/* unbind pages */
- 		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
- 	}
- 	adev->gart.ready = false;
- 	vfree(adev->gart.pages);
--	vfree(adev->gart.pages_addr);
- 	adev->gart.pages = NULL;
--	adev->gart.pages_addr = NULL;
- 
- 	amdgpu_dummy_page_fini(adev);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0464-drm-amdgpu-optionally-enable-GART-debugfs-file.patch b/common/recipes-kernel/linux/files/0464-drm-amdgpu-optionally-enable-GART-debugfs-file.patch
deleted file mode 100644
index e91b8105..00000000
--- a/common/recipes-kernel/linux/files/0464-drm-amdgpu-optionally-enable-GART-debugfs-file.patch
+++ /dev/null
@@ -1,193 +0,0 @@
-From 18510c1c4a1505f2e79edc206b997bee011913f6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 30 Mar 2016 14:42:57 +0200
-Subject: [PATCH 0464/1110] drm/amdgpu: optionally enable GART debugfs file
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Keeping the pages array around can use a lot of system memory
-when you want a large GART.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Kconfig       | 10 +++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  2 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 35 +++++++++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  9 ++++++++
- 4 files changed, 42 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig
-index b30fcfa..7335c04 100644
---- a/drivers/gpu/drm/amd/amdgpu/Kconfig
-+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
-@@ -15,3 +15,13 @@ config DRM_AMDGPU_USERPTR
- 	help
- 	  This option selects CONFIG_MMU_NOTIFIER if it isn't already
- 	  selected to enabled full userptr support.
-+
-+config DRM_AMDGPU_GART_DEBUGFS
-+	bool "Allow GART access through debugfs"
-+	depends on DRM_AMDGPU
-+	depends on DEBUG_FS
-+	default n
-+	help
-+	  Selecting this option creates a debugfs file to inspect the mapped
-+	  pages. Uses more memory for housekeeping, enable only for debugging.
-+
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 35e07fb..993b574 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -612,7 +612,9 @@ struct amdgpu_gart {
- 	unsigned			num_gpu_pages;
- 	unsigned			num_cpu_pages;
- 	unsigned			table_size;
-+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- 	struct page			**pages;
-+#endif
- 	bool				ready;
- 	const struct amdgpu_gart_funcs *gart_funcs;
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
-index a13603a..921bce2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
-@@ -238,17 +238,17 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
- 	t = offset / AMDGPU_GPU_PAGE_SIZE;
- 	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
- 	for (i = 0; i < pages; i++, p++) {
--		if (adev->gart.pages[p]) {
--			adev->gart.pages[p] = NULL;
--			page_base = adev->dummy_page.addr;
--			if (!adev->gart.ptr)
--				continue;
-+#ifdef CONFIG_AMDGPU_GART_DEBUGFS
-+		adev->gart.pages[p] = NULL;
-+#endif
-+		page_base = adev->dummy_page.addr;
-+		if (!adev->gart.ptr)
-+			continue;
- 
--			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
--				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
--							t, page_base, flags);
--				page_base += AMDGPU_GPU_PAGE_SIZE;
--			}
-+		for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
-+			amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
-+						t, page_base, flags);
-+			page_base += AMDGPU_GPU_PAGE_SIZE;
- 		}
- 	}
- 	mb();
-@@ -286,7 +286,9 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
- 	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
- 
- 	for (i = 0; i < pages; i++, p++) {
-+#ifdef CONFIG_AMDGPU_GART_DEBUGFS
- 		adev->gart.pages[p] = pagelist[i];
-+#endif
- 		if (adev->gart.ptr) {
- 			page_base = dma_addr[i];
- 			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
-@@ -312,9 +314,9 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
- {
- 	int r;
- 
--	if (adev->gart.pages) {
-+	if (adev->dummy_page.page)
- 		return 0;
--	}
-+
- 	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
- 	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
- 		DRM_ERROR("Page size is smaller than GPU page size!\n");
-@@ -328,12 +330,16 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
- 	adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
- 	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
- 		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
-+
-+#ifdef CONFIG_AMDGPU_GART_DEBUGFS
- 	/* Allocate pages table */
- 	adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
- 	if (adev->gart.pages == NULL) {
- 		amdgpu_gart_fini(adev);
- 		return -ENOMEM;
- 	}
-+#endif
-+
- 	return 0;
- }
- 
-@@ -346,13 +352,14 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
-  */
- void amdgpu_gart_fini(struct amdgpu_device *adev)
- {
--	if (adev->gart.pages && adev->gart.ready) {
-+	if (adev->gart.ready) {
- 		/* unbind pages */
- 		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
- 	}
- 	adev->gart.ready = false;
-+#ifdef CONFIG_AMDGPU_GART_DEBUGFS
- 	vfree(adev->gart.pages);
- 	adev->gart.pages = NULL;
--
-+#endif
- 	amdgpu_dummy_page_fini(adev);
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index fbc3c2b..228ccab 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -1226,6 +1226,8 @@ static const struct file_operations amdgpu_ttm_vram_fops = {
- 	.llseek = default_llseek
- };
- 
-+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
-+
- static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
- 				   size_t size, loff_t *pos)
- {
-@@ -1273,6 +1275,8 @@ static const struct file_operations amdgpu_ttm_gtt_fops = {
- 
- #endif
- 
-+#endif
-+
- static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
- {
- #if defined(CONFIG_DEBUG_FS)
-@@ -1288,6 +1292,7 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
- 	i_size_write(ent->d_inode, adev->mc.mc_vram_size);
- 	adev->mman.vram = ent;
- 
-+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- 	ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
- 				  adev, &amdgpu_ttm_gtt_fops);
- 	if (IS_ERR(ent))
-@@ -1295,6 +1300,7 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
- 	i_size_write(ent->d_inode, adev->mc.gtt_size);
- 	adev->mman.gtt = ent;
- 
-+#endif
- 	count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
- 
- #ifdef CONFIG_SWIOTLB
-@@ -1316,7 +1322,10 @@ static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
- 	debugfs_remove(adev->mman.vram);
- 	adev->mman.vram = NULL;
- 
-+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- 	debugfs_remove(adev->mman.gtt);
- 	adev->mman.gtt = NULL;
- #endif
-+
-+#endif
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch b/common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch
deleted file mode 100644
index 43fed0b3..00000000
--- a/common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 9fedb3f1bb29f2572495d469a6cc7500d91c9c81 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Wed, 30 Mar 2016 16:30:12 -0400
-Subject: [PATCH 0465/1110] drm/amd/powerplay: add deep sleep divider id into
- DPM table on Tonga
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 29 +++++++++++++++++++----
- 1 file changed, 24 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 0d5d837..fee7835 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -2415,6 +2415,25 @@ int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
-+static uint8_t tonga_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock, uint32_t min_engine_clock_in_sr)
-+{
-+	uint32_t i, temp;
-+	uint32_t min = (min_engine_clock_in_sr > TONGA_MINIMUM_ENGINE_CLOCK) ?
-+			min_engine_clock_in_sr : TONGA_MINIMUM_ENGINE_CLOCK;
-+
-+	PP_ASSERT_WITH_CODE((engine_clock >= min),
-+			"Engine clock can't satisfy stutter requirement!", return 0);
-+
-+	for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
-+		temp = engine_clock / (1 << i);
-+
-+		if(temp >= min || i == 0)
-+			break;
-+	}
-+	return (uint8_t)i;
-+}
-+
- /**
-  * Populates single SMC SCLK structure using the provided engine clock
-  *
-@@ -2463,12 +2482,12 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t
- 	*get the DAL clock. do it in funture.
- 	PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
- 	data->display_timing.min_clock_insr = minClocks.engineClockInSR;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
--	{
--		graphic_level->DeepSleepDivId = PhwTonga_GetSleepDividerIdFromClock(hwmgr, engine_clock, minClocks.engineClockInSR);
--	}
- */
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep))
-+		graphic_level->DeepSleepDivId =
-+				tonga_get_sleep_divider_id_from_clock(hwmgr, engine_clock,
-+						data->display_timing.min_clock_insr);
- 
- 	/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
- 	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0466-drm-amdgpu-merge-VM-manager-and-VM-context-ID-struct.patch b/common/recipes-kernel/linux/files/0466-drm-amdgpu-merge-VM-manager-and-VM-context-ID-struct.patch
deleted file mode 100644
index 0e1671c4..00000000
--- a/common/recipes-kernel/linux/files/0466-drm-amdgpu-merge-VM-manager-and-VM-context-ID-struct.patch
+++ /dev/null
@@ -1,309 +0,0 @@
-From ef36d09d3557e4d96cd928b8210801fef9c11fc7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 8 Mar 2016 15:40:11 +0100
-Subject: [PATCH 0466/1110] drm/amdgpu: merge VM manager and VM context ID
- structure
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No need to have two of them any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  18 ++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 139 +++++++++++++++++----------------
- 2 files changed, 78 insertions(+), 79 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 993b574..4b9fe35 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -838,13 +838,6 @@ struct amdgpu_vm_pt {
- 
- };
- 
--struct amdgpu_vm_id {
--        struct amdgpu_vm_manager_id     *mgr_id;
--        uint64_t                        pd_gpu_addr;
--	/* last flushed PD/PT update */
--        struct fence                    *flushed_updates;
--};
--
- struct amdgpu_vm {
- 	/* tree of virtual addresses mapped */
- 	struct rb_root		va;
-@@ -870,7 +863,7 @@ struct amdgpu_vm {
- 	struct amdgpu_vm_pt	*page_tables;
- 
- 	/* for id and flush management per ring */
--	struct amdgpu_vm_id	ids[AMDGPU_MAX_RINGS];
-+        struct amdgpu_vm_id     *ids[AMDGPU_MAX_RINGS];
- 
- 	/* protecting freed */
- 	spinlock_t		freed_lock;
-@@ -879,11 +872,14 @@ struct amdgpu_vm {
-         struct amd_sched_entity entity;
- };
- 
--struct amdgpu_vm_manager_id {
-+struct amdgpu_vm_id {
- 	struct list_head	list;
- 	struct fence		*active;
- 	atomic_long_t		owner;
-- 
-+        uint64_t                pd_gpu_addr;
-+        /* last flushed PD/PT update */
-+        struct fence            *flushed_updates;
-+
-         uint32_t                gds_base;
-         uint32_t                gds_size;
-         uint32_t                gws_base;
-@@ -897,7 +893,7 @@ struct amdgpu_vm_manager {
- 	struct mutex				lock;
- 	unsigned				num_ids;
- 	struct list_head			ids_lru;
--	struct amdgpu_vm_manager_id		ids[AMDGPU_NUM_VM];
-+        struct amdgpu_vm_id                     ids[AMDGPU_NUM_VM];
- 
- 	uint32_t				max_pfn;
- 	/* vram base address for page table entry  */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 0b9b03f..1c87193 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -173,43 +173,41 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- {
- 	uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
- 	struct amdgpu_device *adev = ring->adev;
--	struct amdgpu_vm_id *id = &vm->ids[ring->idx];
-+	struct amdgpu_vm_id *id = vm->ids[ring->idx];
- 	struct fence *updates = sync->last_vm_update;
- 	int r;
- 
- 	mutex_lock(&adev->vm_manager.lock);
- 
- 	/* check if the id is still valid */
--	if (id->mgr_id) {
-+	if (id) {
- 		struct fence *flushed = id->flushed_updates;
--		bool is_later;
--		long owner;
-+		long owner = atomic_long_read(&id->owner);
-+		bool usable = pd_addr == id->pd_gpu_addr;
- 
--		if (!flushed)
--			is_later = true;
-+		if (owner != (long)&vm->ids[ring->idx])
-+			usable = false;
-+		else if (!flushed)
-+			usable = false;
- 		else if (!updates)
--			is_later = false;
-+			usable = true;
- 		else
--			is_later = fence_is_later(updates, flushed);
-+			usable = !fence_is_later(updates, flushed);
- 
--		owner = atomic_long_read(&id->mgr_id->owner);
--		if (!is_later && owner == (long)id &&
--		    pd_addr == id->pd_gpu_addr) {
-+		if (usable) {
- 
--			r = amdgpu_sync_fence(ring->adev, sync,
--					      id->mgr_id->active);
-+			r = amdgpu_sync_fence(ring->adev, sync, id->active);
- 			if (r) {
- 				mutex_unlock(&adev->vm_manager.lock);
- 				return r;
- 			}
- 
--			fence_put(id->mgr_id->active);
--			id->mgr_id->active = fence_get(fence);
-+			fence_put(id->active);
-+			id->active = fence_get(fence);
- 
--			list_move_tail(&id->mgr_id->list,
--				       &adev->vm_manager.ids_lru);
-+			list_move_tail(&id->list, &adev->vm_manager.ids_lru);
- 
--			*vm_id = id->mgr_id - adev->vm_manager.ids;
-+			*vm_id = id - adev->vm_manager.ids;
- 			*vm_pd_addr = AMDGPU_VM_NO_FLUSH;
- 			trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id,
- 						*vm_pd_addr);
-@@ -219,38 +217,41 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		}
- 	}
- 
--	id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru,
--				      struct amdgpu_vm_manager_id,
--				      list);
-+	id = list_first_entry(&adev->vm_manager.ids_lru,
-+			      struct amdgpu_vm_id,
-+			      list);
- 
--	if (id->mgr_id->active && !fence_is_signaled(id->mgr_id->active)) {
--		struct amdgpu_vm_manager_id *mgr_id, *tmp;
-+	if (id->active && !fence_is_signaled(id->active)) {
-+		struct amdgpu_vm_id *tmp;
- 		struct list_head *head = &adev->vm_manager.ids_lru;
--		list_for_each_entry_safe(mgr_id, tmp, &adev->vm_manager.ids_lru, list) {
--			if (mgr_id->active && fence_is_signaled(mgr_id->active)) {
--				list_move(&mgr_id->list, head);
--				head = &mgr_id->list;
-+
-+		list_for_each_entry_safe(id, tmp, &adev->vm_manager.ids_lru,
-+					 list) {
-+			if (id->active && fence_is_signaled(id->active)) {
-+				list_move(&id->list, head);
-+				head = &id->list;
- 			}
- 		}
--		id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru,
--					      struct amdgpu_vm_manager_id,
--					      list);
-+		id = list_first_entry(&adev->vm_manager.ids_lru,
-+				      struct amdgpu_vm_id,
-+				      list);
- 	}
- 
--	r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active);
-+	r = amdgpu_sync_fence(ring->adev, sync, id->active);
- 	if (!r) {
--		fence_put(id->mgr_id->active);
--		id->mgr_id->active = fence_get(fence);
-+		fence_put(id->active);
-+		id->active = fence_get(fence);
- 
- 		fence_put(id->flushed_updates);
- 		id->flushed_updates = fence_get(updates);
- 
- 		id->pd_gpu_addr = pd_addr;
- 
--		list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru);
--		atomic_long_set(&id->mgr_id->owner, (long)id);
-+		list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-+		atomic_long_set(&id->owner, (long)&vm->ids[ring->idx]);
-+		vm->ids[ring->idx] = id;
- 
--		*vm_id = id->mgr_id - adev->vm_manager.ids;
-+		*vm_id = id - adev->vm_manager.ids;
- 		*vm_pd_addr = pd_addr;
- 		trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
- 	}
-@@ -275,14 +276,14 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 		     uint32_t oa_base, uint32_t oa_size)
- {
-         struct amdgpu_device *adev = ring->adev;
--        struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id];
-+        struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
-         bool gds_switch_needed = ring->funcs->emit_gds_switch && (
--               mgr_id->gds_base != gds_base ||
--               mgr_id->gds_size != gds_size ||
--               mgr_id->gws_base != gws_base ||
--               mgr_id->gws_size != gws_size ||
--               mgr_id->oa_base != oa_base ||
--               mgr_id->oa_size != oa_size);
-+                id->gds_base != gds_base ||
-+                id->gds_size != gds_size ||
-+                id->gws_base != gws_base ||
-+                id->gws_size != gws_size ||
-+                id->oa_base != oa_base ||
-+                id->oa_size != oa_size);
- 
-         if (ring->funcs->emit_pipeline_sync && (
-            pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed))
-@@ -294,12 +295,12 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 	}
- 
-         if (gds_switch_needed) {
--               mgr_id->gds_base = gds_base;
--               mgr_id->gds_size = gds_size;
--               mgr_id->gws_base = gws_base;
--               mgr_id->gws_size = gws_size;
--               mgr_id->oa_base = oa_base;
--               mgr_id->oa_size = oa_size;
-+                id->gds_base = gds_base;
-+                id->gds_size = gds_size;
-+                id->gws_base = gws_base;
-+                id->gws_size = gws_size;
-+                id->oa_base = oa_base;
-+                id->oa_size = oa_size;
- 	       amdgpu_ring_emit_gds_switch(ring, vm_id,
- 					    gds_base, gds_size,
- 					    gws_base, gws_size,
-@@ -317,14 +318,14 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
-  */
- void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
- {
--       struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id];
--
--       mgr_id->gds_base = 0;
--       mgr_id->gds_size = 0;
--       mgr_id->gws_base = 0;
--       mgr_id->gws_size = 0;
--       mgr_id->oa_base = 0;
--       mgr_id->oa_size = 0;
-+       struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
-+
-+       id->gds_base = 0;
-+       id->gds_size = 0;
-+       id->gws_base = 0;
-+       id->gws_size = 0;
-+       id->oa_base = 0;
-+       id->oa_size = 0;
- }
- 
- /**
-@@ -1352,10 +1353,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
-         struct amd_sched_rq *rq;
- 	int i, r;
- 
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		vm->ids[i].mgr_id = NULL;
--		vm->ids[i].flushed_updates = NULL;
--	}
-+        for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-+               vm->ids[i] = NULL;
- 	vm->va = RB_ROOT;
- 	spin_lock_init(&vm->status_lock);
- 	INIT_LIST_HEAD(&vm->invalidated);
-@@ -1447,12 +1446,12 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	fence_put(vm->page_directory_fence);
- 
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		struct amdgpu_vm_id *id = &vm->ids[i];
-+		struct amdgpu_vm_id *id = vm->ids[i];
- 
--		if (id->mgr_id)
--			atomic_long_cmpxchg(&id->mgr_id->owner,
--					    (long)id, 0);
--		fence_put(id->flushed_updates);
-+		if (!id)
-+			continue;
-+
-+		atomic_long_cmpxchg(&id->owner, (long)&vm->ids[i], 0);
- 	}
- }
- 
-@@ -1491,6 +1490,10 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
- {
- 	unsigned i;
- 
--	for (i = 0; i < AMDGPU_NUM_VM; ++i)
--		fence_put(adev->vm_manager.ids[i].active);
-+	for (i = 0; i < AMDGPU_NUM_VM; ++i) {
-+		struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
-+
-+		fence_put(id->active);
-+		fence_put(id->flushed_updates);
-+	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0467-drm-amdgpu-use-a-sync-object-for-VMID-fences-v2.patch b/common/recipes-kernel/linux/files/0467-drm-amdgpu-use-a-sync-object-for-VMID-fences-v2.patch
deleted file mode 100644
index 7edb7656..00000000
--- a/common/recipes-kernel/linux/files/0467-drm-amdgpu-use-a-sync-object-for-VMID-fences-v2.patch
+++ /dev/null
@@ -1,286 +0,0 @@
-From ce9a1734fbccf5fa7fb28a314f25e1f6f244f988 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Mon, 15 Feb 2016 12:33:02 +0100
-Subject: [PATCH 0467/1110] drm/amdgpu: use a sync object for VMID fences v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-v2: rebase & cleanup
-
-This way we can store more than one fence as user for each VMID.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1)
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h      |   7 ++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 105 +++++++++++++++++++++++++++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  54 ++++++++--------
- 3 files changed, 133 insertions(+), 33 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 4b9fe35..915c2e3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -589,6 +589,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     struct amdgpu_sync *sync,
- 		     struct reservation_object *resv,
- 		     void *owner);
-+bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);
-+int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
-+                            struct fence *fence);
- struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
- int amdgpu_sync_wait(struct amdgpu_sync *sync);
- void amdgpu_sync_free(struct amdgpu_sync *sync);
-@@ -874,8 +877,10 @@ struct amdgpu_vm {
- 
- struct amdgpu_vm_id {
- 	struct list_head	list;
--	struct fence		*active;
-+        struct fence            *first;
-+        struct amdgpu_sync      active;
- 	atomic_long_t		owner;
-+
-         uint64_t                pd_gpu_addr;
-         /* last flushed PD/PT update */
-         struct fence            *flushed_updates;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-index c48b4fc..34a9280 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
-@@ -109,6 +109,29 @@ static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence)
- }
- 
- /**
-+ * amdgpu_sync_add_later - add the fence to the hash
-+ *
-+ * @sync: sync object to add the fence to
-+ * @f: fence to add
-+ *
-+ * Tries to add the fence to an existing hash entry. Returns true when an entry
-+ * was found, false otherwise.
-+ */
-+static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct fence *f)
-+{
-+	struct amdgpu_sync_entry *e;
-+
-+	hash_for_each_possible(sync->fences, e, node, f->context) {
-+		if (unlikely(e->fence->context != f->context))
-+			continue;
-+
-+		amdgpu_sync_keep_later(&e->fence, f);
-+		return true;
-+	}
-+	return false;
-+}
-+
-+/**
-  * amdgpu_sync_fence - remember to sync to this fence
-  *
-  * @sync: sync object to add fence to
-@@ -127,13 +150,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
- 	    amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
- 		amdgpu_sync_keep_later(&sync->last_vm_update, f);
- 
--	hash_for_each_possible(sync->fences, e, node, f->context) {
--		if (unlikely(e->fence->context != f->context))
--			continue;
--
--		amdgpu_sync_keep_later(&e->fence, f);
-+	if (amdgpu_sync_add_later(sync, f))
- 		return 0;
--	}
- 
- 	e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
- 	if (!e)
-@@ -204,6 +222,81 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
- 	return r;
- }
- 
-+/**
-+ * amdgpu_sync_is_idle - test if all fences are signaled
-+ *
-+ * @sync: the sync object
-+ *
-+ * Returns true if all fences in the sync object are signaled.
-+ */
-+bool amdgpu_sync_is_idle(struct amdgpu_sync *sync)
-+{
-+	struct amdgpu_sync_entry *e;
-+	struct hlist_node *tmp;
-+	int i;
-+
-+	hash_for_each_safe(sync->fences, i, tmp, e, node) {
-+		struct fence *f = e->fence;
-+
-+		if (fence_is_signaled(f)) {
-+			hash_del(&e->node);
-+			fence_put(f);
-+			kmem_cache_free(amdgpu_sync_slab, e);
-+			continue;
-+		}
-+
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ * amdgpu_sync_cycle_fences - move fences from one sync object into another
-+ *
-+ * @dst: the destination sync object
-+ * @src: the source sync object
-+ * @fence: fence to add to source
-+ *
-+ * Remove all fences from source and put them into destination and add
-+ * fence as new one into source.
-+ */
-+int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
-+			     struct fence *fence)
-+{
-+	struct amdgpu_sync_entry *e, *newone;
-+	struct hlist_node *tmp;
-+	int i;
-+
-+	/* Allocate the new entry before moving the old ones */
-+	newone = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
-+	if (!newone)
-+		return -ENOMEM;
-+
-+	hash_for_each_safe(src->fences, i, tmp, e, node) {
-+		struct fence *f = e->fence;
-+
-+		hash_del(&e->node);
-+		if (fence_is_signaled(f)) {
-+			fence_put(f);
-+			kmem_cache_free(amdgpu_sync_slab, e);
-+			continue;
-+		}
-+
-+		if (amdgpu_sync_add_later(dst, f)) {
-+			kmem_cache_free(amdgpu_sync_slab, e);
-+			continue;
-+		}
-+
-+		hash_add(dst->fences, &e->node, f->context);
-+	}
-+
-+	hash_add(src->fences, &newone->node, fence->context);
-+	newone->fence = fence_get(fence);
-+
-+	return 0;
-+}
-+
- struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
- {
- 	struct amdgpu_sync_entry *e;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 1c87193..8382b7f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -196,14 +196,13 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 
- 		if (usable) {
- 
--			r = amdgpu_sync_fence(ring->adev, sync, id->active);
--			if (r) {
--				mutex_unlock(&adev->vm_manager.lock);
--				return r;
--			}
-+			r = amdgpu_sync_fence(ring->adev, sync, id->first);
-+			if (r)
-+				goto error;
- 
--			fence_put(id->active);
--			id->active = fence_get(fence);
-+			r = amdgpu_sync_fence(ring->adev, &id->active, fence);
-+			if (r)
-+				goto error;
- 
- 			list_move_tail(&id->list, &adev->vm_manager.ids_lru);
- 
-@@ -221,13 +220,13 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 			      struct amdgpu_vm_id,
- 			      list);
- 
--	if (id->active && !fence_is_signaled(id->active)) {
--		struct amdgpu_vm_id *tmp;
-+	if (!amdgpu_sync_is_idle(&id->active)) {
- 		struct list_head *head = &adev->vm_manager.ids_lru;
-+		struct amdgpu_vm_id *tmp;
- 
- 		list_for_each_entry_safe(id, tmp, &adev->vm_manager.ids_lru,
- 					 list) {
--			if (id->active && fence_is_signaled(id->active)) {
-+			if (amdgpu_sync_is_idle(&id->active)) {
- 				list_move(&id->list, head);
- 				head = &id->list;
- 			}
-@@ -237,25 +236,27 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 				      list);
- 	}
- 
--	r = amdgpu_sync_fence(ring->adev, sync, id->active);
--	if (!r) {
--		fence_put(id->active);
--		id->active = fence_get(fence);
-+	r = amdgpu_sync_cycle_fences(sync, &id->active, fence);
-+	if (r)
-+		goto error;
- 
--		fence_put(id->flushed_updates);
--		id->flushed_updates = fence_get(updates);
-+	fence_put(id->first);
-+	id->first = fence_get(fence);
- 
--		id->pd_gpu_addr = pd_addr;
-+	fence_put(id->flushed_updates);
-+	id->flushed_updates = fence_get(updates);
- 
--		list_move_tail(&id->list, &adev->vm_manager.ids_lru);
--		atomic_long_set(&id->owner, (long)&vm->ids[ring->idx]);
--		vm->ids[ring->idx] = id;
-+	id->pd_gpu_addr = pd_addr;
- 
--		*vm_id = id - adev->vm_manager.ids;
--		*vm_pd_addr = pd_addr;
--		trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
--	}
-+	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-+	atomic_long_set(&id->owner, (long)id);
-+	vm->ids[ring->idx] = id;
- 
-+	*vm_id = id - adev->vm_manager.ids;
-+	*vm_pd_addr = pd_addr;
-+	trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
-+
-+error:
- 	mutex_unlock(&adev->vm_manager.lock);
- 	return r;
- }
-@@ -1470,7 +1471,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 
- 	/* skip over VMID 0, since it is the system VM */
-         for (i = 1; i < adev->vm_manager.num_ids; ++i) {
--                 amdgpu_vm_reset_id(adev, i);
-+                 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
- 		list_add_tail(&adev->vm_manager.ids[i].list,
- 			      &adev->vm_manager.ids_lru);
-         }
-@@ -1493,7 +1494,8 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
- 	for (i = 0; i < AMDGPU_NUM_VM; ++i) {
- 		struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
- 
--		fence_put(id->active);
-+		fence_put(adev->vm_manager.ids[i].first);
-+		amdgpu_sync_free(&adev->vm_manager.ids[i].active);
- 		fence_put(id->flushed_updates);
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0468-drm-amdgpu-add-a-fence-after-the-VM-flush.patch b/common/recipes-kernel/linux/files/0468-drm-amdgpu-add-a-fence-after-the-VM-flush.patch
deleted file mode 100644
index b732ef27..00000000
--- a/common/recipes-kernel/linux/files/0468-drm-amdgpu-add-a-fence-after-the-VM-flush.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From e9f18e032cadfb8fe77b7d03b2688ae64b6d8d0e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 1 Mar 2016 16:46:18 +0100
-Subject: [PATCH 0468/1110] drm/amdgpu: add a fence after the VM flush
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This way we can track when the flush is done.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 11 ++++++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 12 ++++++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 +++++++++++++++++++++-----
- 3 files changed, 35 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 915c2e3..6d87e4c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -879,6 +879,7 @@ struct amdgpu_vm_id {
- 	struct list_head	list;
-         struct fence            *first;
-         struct amdgpu_sync      active;
-+        struct fence            *last_flush;
- 	atomic_long_t		owner;
- 
-         uint64_t                pd_gpu_addr;
-@@ -932,11 +933,11 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
-                       struct amdgpu_sync *sync, struct fence *fence,
-                       unsigned *vm_id, uint64_t *vm_pd_addr);
--void amdgpu_vm_flush(struct amdgpu_ring *ring,
--                     unsigned vm_id, uint64_t pd_addr,
--                     uint32_t gds_base, uint32_t gds_size,
--                     uint32_t gws_base, uint32_t gws_size,
--                     uint32_t oa_base, uint32_t oa_size);
-+int amdgpu_vm_flush(struct amdgpu_ring *ring,
-+                    unsigned vm_id, uint64_t pd_addr,
-+                    uint32_t gds_base, uint32_t gds_size,
-+                    uint32_t gws_base, uint32_t gws_size,
-+                    uint32_t oa_base, uint32_t oa_size);
- void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
- uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 964914b..209ab99 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -151,10 +151,14 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 
- 	if (vm) {
- 		/* do context switch */
--                amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
--                                ib->gds_base, ib->gds_size,
--                                ib->gws_base, ib->gws_size,
--                                ib->oa_base, ib->oa_size);
-+                r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
-+                                    ib->gds_base, ib->gds_size,
-+                                    ib->gws_base, ib->gws_size,
-+                                    ib->oa_base, ib->oa_size);
-+                if (r) {
-+                        amdgpu_ring_undo(ring);
-+                        return r;
-+                }
- 
- 		if (ring->funcs->emit_hdp_flush)
- 			amdgpu_ring_emit_hdp_flush(ring);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8382b7f..0da3fde 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -243,6 +243,9 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 	fence_put(id->first);
- 	id->first = fence_get(fence);
- 
-+	fence_put(id->last_flush);
-+	id->last_flush = NULL;
-+
- 	fence_put(id->flushed_updates);
- 	id->flushed_updates = fence_get(updates);
- 
-@@ -270,11 +273,11 @@ error:
-  *
-  * Emit a VM flush when it is necessary.
-  */
--void amdgpu_vm_flush(struct amdgpu_ring *ring,
--		     unsigned vm_id, uint64_t pd_addr,
--		     uint32_t gds_base, uint32_t gds_size,
--		     uint32_t gws_base, uint32_t gws_size,
--		     uint32_t oa_base, uint32_t oa_size)
-+int amdgpu_vm_flush(struct amdgpu_ring *ring,
-+                    unsigned vm_id, uint64_t pd_addr,
-+                    uint32_t gds_base, uint32_t gds_size,
-+                    uint32_t gws_base, uint32_t gws_size,
-+                    uint32_t oa_base, uint32_t oa_size)
- {
-         struct amdgpu_device *adev = ring->adev;
-         struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
-@@ -285,14 +288,25 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
-                 id->gws_size != gws_size ||
-                 id->oa_base != oa_base ||
-                 id->oa_size != oa_size);
-+        int r;
- 
-         if (ring->funcs->emit_pipeline_sync && (
-            pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed))
-                amdgpu_ring_emit_pipeline_sync(ring);
- 
- 	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
-+                struct fence *fence;
-+
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
- 		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
-+                r = amdgpu_fence_emit(ring, &fence);
-+                if (r)
-+                        return r;
-+ 
-+                mutex_lock(&adev->vm_manager.lock);
-+                fence_put(id->last_flush);
-+                id->last_flush = fence;
-+                mutex_unlock(&adev->vm_manager.lock);
- 	}
- 
-         if (gds_switch_needed) {
-@@ -307,6 +321,8 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
- 					    gws_base, gws_size,
- 					    oa_base, oa_size);
- 	}
-+
-+	return 0;
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0469-drm-amdgpu-reuse-VMIDs-already-assigned-to-a-process.patch b/common/recipes-kernel/linux/files/0469-drm-amdgpu-reuse-VMIDs-already-assigned-to-a-process.patch
deleted file mode 100644
index 4538e6fb..00000000
--- a/common/recipes-kernel/linux/files/0469-drm-amdgpu-reuse-VMIDs-already-assigned-to-a-process.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 9dd895105cf0da2b6d3cb8159b91e43ed420dd6a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 9 Mar 2016 22:11:53 +0100
-Subject: [PATCH 0469/1110] drm/amdgpu: reuse VMIDs already assigned to a
- process
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If we don't need to flush we can easily use another VMID
-already assigned to the process.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 77 ++++++++++++++++++++--------------
- 1 file changed, 46 insertions(+), 31 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 0da3fde..9444cbe 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -173,48 +173,63 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- {
- 	uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
- 	struct amdgpu_device *adev = ring->adev;
--	struct amdgpu_vm_id *id = vm->ids[ring->idx];
- 	struct fence *updates = sync->last_vm_update;
-+	struct amdgpu_vm_id *id;
-+	unsigned i = ring->idx;
- 	int r;
- 
- 	mutex_lock(&adev->vm_manager.lock);
- 
--	/* check if the id is still valid */
--	if (id) {
--		struct fence *flushed = id->flushed_updates;
--		long owner = atomic_long_read(&id->owner);
--		bool usable = pd_addr == id->pd_gpu_addr;
--
--		if (owner != (long)&vm->ids[ring->idx])
--			usable = false;
--		else if (!flushed)
--			usable = false;
--		else if (!updates)
--			usable = true;
--		else
--			usable = !fence_is_later(updates, flushed);
-+	/* Check if we can use a VMID already assigned to this VM */
-+	do {
-+		struct fence *flushed;
- 
--		if (usable) {
-+		id = vm->ids[i++];
-+		if (i == AMDGPU_MAX_RINGS)
-+			i = 0;
- 
--			r = amdgpu_sync_fence(ring->adev, sync, id->first);
--			if (r)
--				goto error;
-+		/* Check all the prerequisites to using this VMID */
-+		if (!id)
-+			continue;
- 
--			r = amdgpu_sync_fence(ring->adev, &id->active, fence);
-+		if (atomic_long_read(&id->owner) != (long)vm)
-+			continue;
-+
-+		if (pd_addr != id->pd_gpu_addr)
-+			continue;
-+
-+		if (id != vm->ids[ring->idx] &&
-+		    (!id->last_flush || !fence_is_signaled(id->last_flush)))
-+			continue;
-+
-+		flushed  = id->flushed_updates;
-+		if (updates && (!flushed || fence_is_later(updates, flushed)))
-+			continue;
-+
-+		/* Good we can use this VMID */
-+		if (id == vm->ids[ring->idx]) {
-+			r = amdgpu_sync_fence(ring->adev, sync,
-+					      id->first);
- 			if (r)
- 				goto error;
-+		}
- 
--			list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-+		/* And remember this submission as user of the VMID */
-+		r = amdgpu_sync_fence(ring->adev, &id->active, fence);
-+		if (r)
-+			goto error;
- 
--			*vm_id = id - adev->vm_manager.ids;
--			*vm_pd_addr = AMDGPU_VM_NO_FLUSH;
--			trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id,
--						*vm_pd_addr);
-+		list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-+		vm->ids[ring->idx] = id;
- 
--			mutex_unlock(&adev->vm_manager.lock);
--			return 0;
--		}
--	}
-+		*vm_id = id - adev->vm_manager.ids;
-+		*vm_pd_addr = AMDGPU_VM_NO_FLUSH;
-+		trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
-+
-+		mutex_unlock(&adev->vm_manager.lock);
-+		return 0;
-+
-+	} while (i != ring->idx);
- 
- 	id = list_first_entry(&adev->vm_manager.ids_lru,
- 			      struct amdgpu_vm_id,
-@@ -252,7 +267,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 	id->pd_gpu_addr = pd_addr;
- 
- 	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
--	atomic_long_set(&id->owner, (long)id);
-+	atomic_long_set(&id->owner, (long)vm);
- 	vm->ids[ring->idx] = id;
- 
- 	*vm_id = id - adev->vm_manager.ids;
-@@ -1468,7 +1483,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 		if (!id)
- 			continue;
- 
--		atomic_long_cmpxchg(&id->owner, (long)&vm->ids[i], 0);
-+		atomic_long_cmpxchg(&id->owner, (long)vm, 0);
- 	}
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0470-drm-amd-powerplay-fix-stutter-setup-in-mclk-level-in.patch b/common/recipes-kernel/linux/files/0470-drm-amd-powerplay-fix-stutter-setup-in-mclk-level-in.patch
deleted file mode 100644
index d7c8f96d..00000000
--- a/common/recipes-kernel/linux/files/0470-drm-amd-powerplay-fix-stutter-setup-in-mclk-level-in.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From a9e43289d72d0868435ae6e2cdbad42413a95f02 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 16:42:38 -0400
-Subject: [PATCH 0470/1110] drm/amd/powerplay: fix stutter setup in mclk level
- init
-
-Stale ifdef.
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index fee7835..b9a27c6 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -51,6 +51,9 @@
- #include "bif/bif_5_0_d.h"
- #include "bif/bif_5_0_sh_mask.h"
- 
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
- #include "cgs_linux.h"
- #include "eventmgr.h"
- #include "amd_pcie_helpers.h"
-@@ -2037,14 +2040,11 @@ static int tonga_populate_single_memory_level(
- 	data->display_timing.num_existing_displays = info.display_count;
- 
- 	if ((data->mclk_stutter_mode_threshold != 0) &&
--			(memory_clock <= data->mclk_stutter_mode_threshold) &&
--			(data->is_uvd_enabled == 0)
--#if defined(LINUX)
--			&& (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
--			&& (data->display_timing.num_existing_displays <= 2)
--			&& (data->display_timing.num_existing_displays != 0)
--#endif
--	)
-+	    (memory_clock <= data->mclk_stutter_mode_threshold) &&
-+	    (data->is_uvd_enabled == 0)
-+	    && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
-+	    && (data->display_timing.num_existing_displays <= 2)
-+	    && (data->display_timing.num_existing_displays != 0))
- 		memory_level->StutterEnable = 1;
- 
- 	/* decide strobe mode*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0471-drm-amd-Mark-some-tables-as-const.patch b/common/recipes-kernel/linux/files/0471-drm-amd-Mark-some-tables-as-const.patch
deleted file mode 100644
index 31febdde..00000000
--- a/common/recipes-kernel/linux/files/0471-drm-amd-Mark-some-tables-as-const.patch
+++ /dev/null
@@ -1,313 +0,0 @@
-From 913442622209799ceb511aa02581fd0f9aff353a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 10 Apr 2016 16:29:59 +0200
-Subject: [PATCH 0471/1110] drm/amd: Mark some tables as const
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This patch marks some compile-time constant tables 'const'.
-The tables marked in this patch are the low hanging fruit
-where little other changes were necesary to avoid casting
-away constness etc. Also mark some tables that are private
-to a file as static.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h                  |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c          |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c              |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c              |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c              |  2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c     | 12 ++++++------
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h     |  2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 10 +++++-----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c    |  8 ++++----
- drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h    |  2 +-
- drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c     |  2 +-
- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c   |  6 +++---
- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c  |  2 +-
- 13 files changed, 29 insertions(+), 29 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 6d87e4c..5c34b1e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2352,7 +2352,7 @@ static inline void amdgpu_unregister_atpx_handler(void) {}
-  * KMS
-  */
- extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
--extern int amdgpu_max_kms_ioctl;
-+extern const int amdgpu_max_kms_ioctl;
- 
- int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
- int amdgpu_driver_unload_kms(struct drm_device *dev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index 7660f30..58fd8aa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -588,20 +588,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs = {
- 	.output_poll_changed = amdgpu_output_poll_changed
- };
- 
--static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
-+static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
- {	{ UNDERSCAN_OFF, "off" },
- 	{ UNDERSCAN_ON, "on" },
- 	{ UNDERSCAN_AUTO, "auto" },
- };
- 
--static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
-+static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
- {	{ AMDGPU_AUDIO_DISABLE, "off" },
- 	{ AMDGPU_AUDIO_ENABLE, "on" },
- 	{ AMDGPU_AUDIO_AUTO, "auto" },
- };
- 
- /* XXX support different dither options? spatial, temporal, both, etc. */
--static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
-+static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
- {	{ AMDGPU_FMT_DITHER_DISABLE, "off" },
- 	{ AMDGPU_FMT_DITHER_ENABLE, "on" },
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 82cab2e..943cdfb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
- MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
- module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
- 
--static struct pci_device_id pciidlist[] = {
-+static const struct pci_device_id pciidlist[] = {
- #ifdef CONFIG_DRM_AMDGPU_CIK
- 	/* Kaveri */
- 	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 762cfdb..9266c7b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -498,7 +498,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d,
- 	return 0;
- }
- 
--static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
-+static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
- 	.map = amdgpu_irqdomain_map,
- };
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index b04337d..7db2712 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -755,4 +755,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- };
--int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
-+const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 025a3ed..55a006d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -95,23 +95,23 @@ enum DPM_EVENT_SRC {
- /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
-  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
-  */
--uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
--                                                {600, 1050, 6, 1} };
-+static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
-+{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
- 
- /* [FF, SS] type, [] 4 voltage ranges, and
-  * [Floor Freq, Boundary Freq, VID min , VID max]
-  */
--uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
-+static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
- { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
- 
- /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
-  * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
-  */
--uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
--                                                  {0, 2, 4, 5, 6, 5} };
-+static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
-+{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
- 
--const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
-+static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
- 
- struct fiji_power_state *cast_phw_fiji_power_state(
- 				  struct pp_hw_power_state *hw_ps)
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-index a16f7cd..4b29d9e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -263,7 +263,7 @@ struct fiji_hwmgr {
- 	bool                           enable_tdc_limit_feature;
- 	bool                           enable_pkg_pwr_tracking_feature;
- 	bool                           disable_uvd_power_tune_feature;
--	struct fiji_pt_defaults       *power_tune_defaults;
-+	const struct fiji_pt_defaults  *power_tune_defaults;
- 	struct SMU73_Discrete_PmFuses  power_tune_table;
- 	uint32_t                       dte_tj_offset;
- 	uint32_t                       fast_watermark_threshold;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-index 6efcb2b..db23a40 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
-@@ -32,7 +32,7 @@
- #define VOLTAGE_SCALE  4
- #define POWERTUNE_DEFAULT_SET_MAX    1
- 
--struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
- 		/*sviLoadLIneEn,  SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
- 		{1,               0xF,             0xFD,
- 		/* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
-@@ -143,7 +143,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
- int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
--	struct fiji_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
- 	SMU73_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
- 	struct phm_ppt_v1_information *table_info =
- 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-@@ -222,7 +222,7 @@ int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
- {
-     struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
--    struct fiji_pt_defaults *defaults = data->power_tune_defaults;
-+    const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
- 
-     data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
-     data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-@@ -238,7 +238,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- 	struct phm_ppt_v1_information *table_info =
- 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct  fiji_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
- 
- 	/* TDC number of fraction bits are changed from 8 to 7
- 	 * for Fiji as requested by SMC team
-@@ -256,7 +256,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
- static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
--	struct  fiji_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
- 	uint32_t temp;
- 
- 	if (fiji_read_smc_sram_dword(hwmgr->smumgr,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index b9a27c6..3bed991 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -89,17 +89,17 @@
- typedef uint32_t PECI_RegistryValue;
- 
- /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
--uint16_t PP_ClockStretcherLookupTable[2][4] = {
-+static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
- 	{600, 1050, 3, 0},
- 	{600, 1050, 6, 1} };
- 
- /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
--uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
-+static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
- 	{ {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
- 	{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
- 
- /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
--uint8_t PP_ClockStretchAmountConversion[2][6] = {
-+static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
- 	{0, 1, 3, 2, 4, 5},
- 	{0, 2, 4, 5, 6, 5} };
- 
-@@ -113,7 +113,7 @@ enum DPM_EVENT_SRC {
- };
- typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
- 
--const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
-+static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
- 
- struct tonga_power_state *cast_phw_tonga_power_state(
- 				  struct pp_hw_power_state *hw_ps)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
-index 0262ad3..8a31665 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
-@@ -46,7 +46,7 @@ struct PWR_Command_Table
- typedef struct PWR_Command_Table PWR_Command_Table;
- 
- #define PWR_VIRUS_TABLE_SIZE  10243
--static PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
-+static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
- {
-     { PwrCmdWrite, 0x100100b6, mmPCIE_INDEX                               },
-     { PwrCmdWrite, 0x00000000, mmPCIE_DATA                                },
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-index ec222c6..da18f44 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
-@@ -39,7 +39,7 @@
- 
- #define SIZE_ALIGN_32(x)    (((x) + 31) / 32 * 32)
- 
--static enum cz_scratch_entry firmware_list[] = {
-+static const enum cz_scratch_entry firmware_list[] = {
- 	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
- 	CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
- 	CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-index cdbb9f8..673a75c 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
-@@ -44,7 +44,7 @@
- 
- #define FIJI_SMC_SIZE 0x20000
- 
--struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
-+static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
- 		/*  Min        Sclk       pcie     DeepSleep Activity  CgSpll      CgSpll    spllSpread  SpllSpread   CcPwr  CcPwr  Sclk   Display     Enabled     Enabled                       Voltage    Power */
- 		/* Voltage,  Frequency,  DpmLevel,  DivId,    Level,  FuncCntl3,  FuncCntl4,  Spectrum,   Spectrum2,  DynRm, DynRm1  Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
- 		{ 0x3c0fd047, 0x30750000,   0x00,     0x03,   0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
-@@ -189,7 +189,7 @@ int fiji_copy_bytes_to_smc(struct pp_smumgr *smumgr,
- 
- int fiji_program_jump_on_start(struct pp_smumgr *smumgr)
- {
--	static unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
-+	static const unsigned char data[] = { 0xE0, 0x00, 0x80, 0x40 };
- 
- 	fiji_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data) + 1);
- 
-@@ -665,7 +665,7 @@ int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
- {
- 	int i, result = -1;
- 	uint32_t reg, data;
--	PWR_Command_Table *virus = PwrVirusTable;
-+	const PWR_Command_Table *virus = PwrVirusTable;
- 	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
- 
- 	priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS;
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-index ebdb43a..32820b6 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
-@@ -145,7 +145,7 @@ out:
- 
- int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
- {
--	static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
-+	static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
- 
- 	tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0472-drm-amd-scheduler-Mark-amdgpu_sched_ops-const.patch b/common/recipes-kernel/linux/files/0472-drm-amd-scheduler-Mark-amdgpu_sched_ops-const.patch
deleted file mode 100644
index aa1fc265..00000000
--- a/common/recipes-kernel/linux/files/0472-drm-amd-scheduler-Mark-amdgpu_sched_ops-const.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 82701fe9953eb4929c761263d0bf45f09ba123cb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 10 Apr 2016 16:30:00 +0200
-Subject: [PATCH 0472/1110] drm/amd/scheduler: Mark amdgpu_sched_ops const
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This marks the struct amdgpu_sched_ops const and
-adjusts amd_sched_init to take a const pointer
-for the ops param. The ops member of
-struct amd_gpu_scheduler is also changed to const.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c       | 2 +-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 2 +-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 4 ++--
- 4 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 5c34b1e..e7c1623 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -749,7 +749,7 @@ enum amdgpu_ring_type {
- 	AMDGPU_RING_TYPE_VCE
- };
- 
--extern struct amd_sched_backend_ops amdgpu_sched_ops;
-+extern const struct amd_sched_backend_ops amdgpu_sched_ops;
- int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
-                              struct amdgpu_job **job);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index 7b4bbcc..f9e7336 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -197,7 +197,7 @@ err:
-        return fence;
- }
- 
--struct amd_sched_backend_ops amdgpu_sched_ops = {
-+const struct amd_sched_backend_ops amdgpu_sched_ops = {
-        .dependency = amdgpu_job_dependency,
-        .run_job = amdgpu_job_run,
-        .begin_job = amd_sched_job_begin,
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 639c70d..c16248c 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -530,7 +530,7 @@ static int amd_sched_main(void *param)
-  * Return 0 on success, otherwise error code.
- */
- int amd_sched_init(struct amd_gpu_scheduler *sched,
--		   struct amd_sched_backend_ops *ops,
-+		   const struct amd_sched_backend_ops *ops,
- 		   unsigned hw_submission, long timeout, const char *name)
- {
- 	int i;
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index 95ebfd0..169f70f 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -123,7 +123,7 @@ enum amd_sched_priority {
-  * One scheduler is implemented for each hardware ring
- */
- struct amd_gpu_scheduler {
--	struct amd_sched_backend_ops	*ops;
-+	const struct amd_sched_backend_ops	*ops;
- 	uint32_t			hw_submission_limit;
- 	long				timeout;
- 	const char			*name;
-@@ -137,7 +137,7 @@ struct amd_gpu_scheduler {
- };
- 
- int amd_sched_init(struct amd_gpu_scheduler *sched,
--		   struct amd_sched_backend_ops *ops,
-+		   const struct amd_sched_backend_ops *ops,
- 		   uint32_t hw_submission, long timeout, const char *name);
- void amd_sched_fini(struct amd_gpu_scheduler *sched);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0473-drm-amdgpu-Mark-all-instances-of-struct-drm_info_lis.patch b/common/recipes-kernel/linux/files/0473-drm-amdgpu-Mark-all-instances-of-struct-drm_info_lis.patch
deleted file mode 100644
index da563741..00000000
--- a/common/recipes-kernel/linux/files/0473-drm-amdgpu-Mark-all-instances-of-struct-drm_info_lis.patch
+++ /dev/null
@@ -1,158 +0,0 @@
-From 6e4217012f969149642277260cf566d5267930ad Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 10 Apr 2016 16:30:01 +0200
-Subject: [PATCH 0473/1110] drm/amdgpu: Mark all instances of struct
- drm_info_list as const
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-All these are compile time constand and the
-drm_debugfs_create/remove_files functions take a const
-pointer argument.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c     | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 2 +-
- 8 files changed, 11 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e7c1623..7fe432d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1705,12 +1705,12 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
-  * Debugfs
-  */
- struct amdgpu_debugfs {
--	struct drm_info_list	*files;
-+	const struct drm_info_list	*files;
- 	unsigned		num_files;
- };
- 
- int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
--			     struct drm_info_list *files,
-+			     const struct drm_info_list *files,
- 			     unsigned nfiles);
- int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index fd52a04..8ff3286 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -2016,7 +2016,7 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev)
-  * Debugfs
-  */
- int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
--			     struct drm_info_list *files,
-+			     const struct drm_info_list *files,
- 			     unsigned nfiles)
- {
- 	unsigned i;
-@@ -2187,7 +2187,7 @@ static int amdgpu_debugfs_print_status(struct seq_file *m, void *data)
- 	return 0;
- }
- 
--static struct drm_info_list amdgpu_debugfs_status_list[] = {
-+static const struct drm_info_list amdgpu_debugfs_status_list[] = {
- 	{"amdgpu_print_status", &amdgpu_debugfs_print_status, 0, NULL},
- };
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index d81f1f4..100f4c6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -639,7 +639,7 @@ static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
- 	return 0;
- }
- 
--static struct drm_info_list amdgpu_debugfs_fence_list[] = {
-+static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
- 	{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
- 	{"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index f5d53b3..75edc9d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -797,7 +797,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
- 	return 0;
- }
- 
--static struct drm_info_list amdgpu_debugfs_gem_list[] = {
-+static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
- 	{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
- };
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 209ab99..146b55e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -325,7 +325,7 @@ static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
- 
- }
- 
--static struct drm_info_list amdgpu_debugfs_sa_list[] = {
-+static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
- 	{"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
- };
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index ff9597c..6d44d4a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -1212,7 +1212,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
- 	return 0;
- }
- 
--static struct drm_info_list amdgpu_pm_info_list[] = {
-+static const struct drm_info_list amdgpu_pm_info_list[] = {
- 	{"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
- };
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index dd79243..7bd31ae 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -427,7 +427,7 @@ static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
- static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
- static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
- 
--static struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
-+static const struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
- 	{"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index},
- 	{"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index},
- 	{"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index},
-@@ -445,7 +445,7 @@ static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ri
- #if defined(CONFIG_DEBUG_FS)
- 	unsigned i;
- 	for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
--		struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
-+		const struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
- 		int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data;
- 		struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset);
- 		unsigned r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 228ccab..07fb3b3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -1175,7 +1175,7 @@ static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
- static int ttm_pl_vram = TTM_PL_VRAM;
- static int ttm_pl_tt = TTM_PL_TT;
- 
--static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
-+static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
- 	{"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
- 	{"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
- 	{"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0474-drm-amd-powerplay-Mark-pem_event_action-chains-as-co.patch b/common/recipes-kernel/linux/files/0474-drm-amd-powerplay-Mark-pem_event_action-chains-as-co.patch
deleted file mode 100644
index 3fe5a9ed..00000000
--- a/common/recipes-kernel/linux/files/0474-drm-amd-powerplay-Mark-pem_event_action-chains-as-co.patch
+++ /dev/null
@@ -1,208 +0,0 @@
-From 9bf8959c2cac6f30ce7965c2e4aeb9cea245d95e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 10 Apr 2016 16:30:02 +0200
-Subject: [PATCH 0474/1110] drm/amd/powerplay: Mark pem_event_action chains as
- const
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-As these arrays were of pointer to pointer type, they were
-pointer to pointer to const. Make them pointer to const
-pointer to const.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/powerplay/eventmgr/eventactionchains.c | 34 +++++++++++-----------
- .../drm/amd/powerplay/eventmgr/eventmanagement.c   |  2 +-
- drivers/gpu/drm/amd/powerplay/inc/eventmgr.h       |  2 +-
- 3 files changed, 19 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-index 56856a2..d6635cc 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
-@@ -24,7 +24,7 @@
- #include "eventactionchains.h"
- #include "eventsubchains.h"
- 
--static const pem_event_action *initialize_event[] = {
-+static const pem_event_action * const initialize_event[] = {
- 	block_adjust_power_state_tasks,
- 	power_budget_tasks,
- 	system_config_tasks,
-@@ -45,7 +45,7 @@ const struct action_chain initialize_action_chain = {
- 	initialize_event
- };
- 
--static const pem_event_action *uninitialize_event[] = {
-+static const pem_event_action * const uninitialize_event[] = {
- 	ungate_all_display_phys_tasks,
- 	uninitialize_display_phy_access_tasks,
- 	disable_gfx_voltage_island_power_gating_tasks,
-@@ -64,7 +64,7 @@ const struct action_chain uninitialize_action_chain = {
- 	uninitialize_event
- };
- 
--static const pem_event_action *power_source_change_event_pp_enabled[] = {
-+static const pem_event_action * const power_source_change_event_pp_enabled[] = {
- 	set_power_source_tasks,
- 	set_power_saving_state_tasks,
- 	adjust_power_state_tasks,
-@@ -79,7 +79,7 @@ const struct action_chain power_source_change_action_chain_pp_enabled = {
- 	power_source_change_event_pp_enabled
- };
- 
--static const pem_event_action *power_source_change_event_pp_disabled[] = {
-+static const pem_event_action * const power_source_change_event_pp_disabled[] = {
- 	set_power_source_tasks,
- 	set_nbmcu_state_tasks,
- 	NULL
-@@ -90,7 +90,7 @@ const struct action_chain power_source_changes_action_chain_pp_disabled = {
- 	power_source_change_event_pp_disabled
- };
- 
--static const pem_event_action *power_source_change_event_hardware_dc[] = {
-+static const pem_event_action * const power_source_change_event_hardware_dc[] = {
- 	set_power_source_tasks,
- 	set_power_saving_state_tasks,
- 	adjust_power_state_tasks,
-@@ -106,7 +106,7 @@ const struct action_chain power_source_change_action_chain_hardware_dc = {
- 	power_source_change_event_hardware_dc
- };
- 
--static const pem_event_action *suspend_event[] = {
-+static const pem_event_action * const suspend_event[] = {
- 	reset_display_phy_access_tasks,
- 	unregister_interrupt_tasks,
- 	disable_gfx_voltage_island_power_gating_tasks,
-@@ -130,7 +130,7 @@ const struct action_chain suspend_action_chain = {
- 	suspend_event
- };
- 
--static const pem_event_action *resume_event[] = {
-+static const pem_event_action * const resume_event[] = {
- 	unblock_hw_access_tasks,
- 	resume_connected_standby_tasks,
- 	notify_smu_resume_tasks,
-@@ -164,7 +164,7 @@ const struct action_chain resume_action_chain = {
- 	resume_event
- };
- 
--static const pem_event_action *complete_init_event[] = {
-+static const pem_event_action * const complete_init_event[] = {
- 	unblock_adjust_power_state_tasks,
- 	adjust_power_state_tasks,
- 	enable_gfx_clock_gating_tasks,
-@@ -178,7 +178,7 @@ const struct action_chain complete_init_action_chain = {
- 	complete_init_event
- };
- 
--static const pem_event_action *enable_gfx_clock_gating_event[] = {
-+static const pem_event_action * const enable_gfx_clock_gating_event[] = {
- 	enable_gfx_clock_gating_tasks,
- 	NULL
- };
-@@ -188,7 +188,7 @@ const struct action_chain enable_gfx_clock_gating_action_chain = {
- 	enable_gfx_clock_gating_event
- };
- 
--static const pem_event_action *disable_gfx_clock_gating_event[] = {
-+static const pem_event_action * const disable_gfx_clock_gating_event[] = {
- 	disable_gfx_clock_gating_tasks,
- 	NULL
- };
-@@ -198,7 +198,7 @@ const struct action_chain disable_gfx_clock_gating_action_chain = {
- 	disable_gfx_clock_gating_event
- };
- 
--static const pem_event_action *enable_cgpg_event[] = {
-+static const pem_event_action * const enable_cgpg_event[] = {
- 	enable_cgpg_tasks,
- 	NULL
- };
-@@ -208,7 +208,7 @@ const struct action_chain enable_cgpg_action_chain = {
- 	enable_cgpg_event
- };
- 
--static const pem_event_action *disable_cgpg_event[] = {
-+static const pem_event_action * const disable_cgpg_event[] = {
- 	disable_cgpg_tasks,
- 	NULL
- };
-@@ -221,7 +221,7 @@ const struct action_chain disable_cgpg_action_chain = {
- 
- /* Enable user _2d performance and activate */
- 
--static const pem_event_action *enable_user_state_event[] = {
-+static const pem_event_action * const enable_user_state_event[] = {
- 	create_new_user_performance_state_tasks,
- 	adjust_power_state_tasks,
- 	NULL
-@@ -232,7 +232,7 @@ const struct action_chain enable_user_state_action_chain = {
- 	enable_user_state_event
- };
- 
--static const pem_event_action *enable_user_2d_performance_event[] = {
-+static const pem_event_action * const enable_user_2d_performance_event[] = {
- 	enable_user_2d_performance_tasks,
- 	add_user_2d_performance_state_tasks,
- 	set_performance_state_tasks,
-@@ -247,7 +247,7 @@ const struct action_chain enable_user_2d_performance_action_chain = {
- };
- 
- 
--static const pem_event_action *disable_user_2d_performance_event[] = {
-+static const pem_event_action * const disable_user_2d_performance_event[] = {
- 	disable_user_2d_performance_tasks,
- 	delete_user_2d_performance_state_tasks,
- 	NULL
-@@ -259,7 +259,7 @@ const struct action_chain disable_user_2d_performance_action_chain = {
- };
- 
- 
--static const pem_event_action *display_config_change_event[] = {
-+static const pem_event_action * const display_config_change_event[] = {
- 	/* countDisplayConfigurationChangeEventTasks, */
- 	unblock_adjust_power_state_tasks,
- 	set_cpu_power_state,
-@@ -278,7 +278,7 @@ const struct action_chain display_config_change_action_chain = {
- 	display_config_change_event
- };
- 
--static const pem_event_action *readjust_power_state_event[] = {
-+static const pem_event_action * const readjust_power_state_event[] = {
- 	adjust_power_state_tasks,
- 	NULL
- };
-diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
-index 1e2ad56..cd1ca07 100644
---- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
-+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmanagement.c
-@@ -62,7 +62,7 @@ int pem_init_event_action_chains(struct pp_eventmgr *eventmgr)
- 
- int pem_excute_event_chain(struct pp_eventmgr *eventmgr, const struct action_chain *event_chain, struct pem_event_data *event_data)
- {
--	const pem_event_action **paction_chain;
-+	const pem_event_action * const *paction_chain;
- 	const pem_event_action *psub_chain;
- 	int tmp_result = 0;
- 	int result = 0;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
-index 10437dc..d63ef83 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/eventmgr.h
-@@ -37,7 +37,7 @@ typedef int (*pem_event_action)(struct pp_eventmgr *eventmgr,
- 
- struct action_chain {
- 	const char *description;  /* action chain description for debugging purpose */
--	const pem_event_action **action_chain; /* pointer to chain of event actions */
-+	const pem_event_action * const *action_chain; /* pointer to chain of event actions */
- };
- 
- struct pem_power_source_ui_state_info {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0475-drm-amd-powerplay-mark-phm_master_table_-structs-as-.patch b/common/recipes-kernel/linux/files/0475-drm-amd-powerplay-mark-phm_master_table_-structs-as-.patch
deleted file mode 100644
index 11c70ec0..00000000
--- a/common/recipes-kernel/linux/files/0475-drm-amd-powerplay-mark-phm_master_table_-structs-as-.patch
+++ /dev/null
@@ -1,260 +0,0 @@
-From 9a89ad0b41464fb955182a7b4ab80f0d2fb52313 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 10 Apr 2016 16:30:03 +0200
-Subject: [PATCH 0475/1110] drm/amd/powerplay: mark phm_master_table_* structs
- as const
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Also adjust phm_construct_table to take a const pointer
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c    |  4 ++--
- .../drm/amd/powerplay/hwmgr/cz_clockpowergating.h    |  2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c       | 20 ++++++++++----------
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c   |  8 ++++----
- drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c |  2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c  |  8 ++++----
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h            |  4 ++--
- 7 files changed, 24 insertions(+), 24 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-index ff08ce4..436fc16 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-@@ -237,7 +237,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- }
- 
- 
--static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
-+static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
- 	/*we don't need an exit table here, because there is only D3 cold on Kv*/
- 	{ phm_cf_want_uvd_power_gating, cz_tf_uvd_power_gating_initialize },
- 	{ phm_cf_want_vce_power_gating, cz_tf_vce_power_gating_initialize },
-@@ -245,7 +245,7 @@ static struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
- 	{ NULL, NULL }
- };
- 
--struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
-+const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	cz_enable_clock_power_gatings_list
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-index bbbc057..35e1b36 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-@@ -28,7 +28,7 @@
- #include "pp_asicblocks.h"
- 
- extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
--extern struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
-+extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
- extern struct phm_master_table_header cz_phm_disable_clock_power_gatings_master;
- extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
- extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 5682490..648394f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -915,7 +915,7 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
--static struct phm_master_table_item cz_set_power_state_list[] = {
-+static const struct phm_master_table_item cz_set_power_state_list[] = {
- 	{NULL, cz_tf_update_sclk_limit},
- 	{NULL, cz_tf_set_deep_sleep_sclk_threshold},
- 	{NULL, cz_tf_set_watermark_threshold},
-@@ -925,13 +925,13 @@ static struct phm_master_table_item cz_set_power_state_list[] = {
- 	{NULL, NULL}
- };
- 
--static struct phm_master_table_header cz_set_power_state_master = {
-+static const struct phm_master_table_header cz_set_power_state_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	cz_set_power_state_list
- };
- 
--static struct phm_master_table_item cz_setup_asic_list[] = {
-+static const struct phm_master_table_item cz_setup_asic_list[] = {
- 	{NULL, cz_tf_reset_active_process_mask},
- 	{NULL, cz_tf_upload_pptable_to_smu},
- 	{NULL, cz_tf_init_sclk_limit},
-@@ -943,7 +943,7 @@ static struct phm_master_table_item cz_setup_asic_list[] = {
- 	{NULL, NULL}
- };
- 
--static struct phm_master_table_header cz_setup_asic_master = {
-+static const struct phm_master_table_header cz_setup_asic_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	cz_setup_asic_list
-@@ -984,14 +984,14 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
--static struct phm_master_table_item cz_power_down_asic_list[] = {
-+static const struct phm_master_table_item cz_power_down_asic_list[] = {
- 	{NULL, cz_tf_power_up_display_clock_sys_pll},
- 	{NULL, cz_tf_clear_nb_dpm_flag},
- 	{NULL, cz_tf_reset_cc6_data},
- 	{NULL, NULL}
- };
- 
--static struct phm_master_table_header cz_power_down_asic_master = {
-+static const struct phm_master_table_header cz_power_down_asic_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	cz_power_down_asic_list
-@@ -1095,19 +1095,19 @@ static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
--static struct phm_master_table_item cz_disable_dpm_list[] = {
-+static const struct phm_master_table_item cz_disable_dpm_list[] = {
- 	{ NULL, cz_tf_check_for_dpm_enabled},
- 	{NULL, NULL},
- };
- 
- 
--static struct phm_master_table_header cz_disable_dpm_master = {
-+static const struct phm_master_table_header cz_disable_dpm_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	cz_disable_dpm_list
- };
- 
--static struct phm_master_table_item cz_enable_dpm_list[] = {
-+static const struct phm_master_table_item cz_enable_dpm_list[] = {
- 	{ NULL, cz_tf_check_for_dpm_disabled },
- 	{ NULL, cz_tf_program_voting_clients },
- 	{ NULL, cz_tf_start_dpm},
-@@ -1117,7 +1117,7 @@ static struct phm_master_table_item cz_enable_dpm_list[] = {
- 	{NULL, NULL},
- };
- 
--static struct phm_master_table_header cz_enable_dpm_master = {
-+static const struct phm_master_table_header cz_enable_dpm_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	cz_enable_dpm_list
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-index e76a7de..e2b448f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-@@ -615,7 +615,7 @@ static int tf_fiji_thermal_disable_alert(struct pp_hwmgr *hwmgr,
- 	return fiji_thermal_disable_alert(hwmgr);
- }
- 
--static struct phm_master_table_item
-+static const struct phm_master_table_item
- fiji_thermal_start_thermal_controller_master_list[] = {
- 	{NULL, tf_fiji_thermal_initialize},
- 	{NULL, tf_fiji_thermal_set_temperature_range},
-@@ -630,14 +630,14 @@ fiji_thermal_start_thermal_controller_master_list[] = {
- 	{NULL, NULL}
- };
- 
--static struct phm_master_table_header
-+static const struct phm_master_table_header
- fiji_thermal_start_thermal_controller_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	fiji_thermal_start_thermal_controller_master_list
- };
- 
--static struct phm_master_table_item
-+static const struct phm_master_table_item
- fiji_thermal_set_temperature_range_master_list[] = {
- 	{NULL, tf_fiji_thermal_disable_alert},
- 	{NULL, tf_fiji_thermal_set_temperature_range},
-@@ -645,7 +645,7 @@ fiji_thermal_set_temperature_range_master_list[] = {
- 	{NULL, NULL}
- };
- 
--struct phm_master_table_header
-+static const struct phm_master_table_header
- fiji_thermal_set_temperature_range_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-index 72cfecc..7a705ce 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
-@@ -84,7 +84,7 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr,
- }
- 
- int phm_construct_table(struct pp_hwmgr *hwmgr,
--			struct phm_master_table_header *master_table,
-+			const struct phm_master_table_header *master_table,
- 			struct phm_runtime_table_header *rt_table)
- {
- 	uint32_t function_count = 0;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-index a188174..23f8463 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-@@ -525,7 +525,7 @@ static int tf_tonga_thermal_disable_alert(struct pp_hwmgr *hwmgr, void *input, v
- 	return tonga_thermal_disable_alert(hwmgr);
- }
- 
--static struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = {
-+static const struct phm_master_table_item tonga_thermal_start_thermal_controller_master_list[] = {
- 	{ NULL, tf_tonga_thermal_initialize },
- 	{ NULL, tf_tonga_thermal_set_temperature_range },
- 	{ NULL, tf_tonga_thermal_enable_alert },
-@@ -538,20 +538,20 @@ static struct phm_master_table_item tonga_thermal_start_thermal_controller_maste
- 	{ NULL, NULL }
- };
- 
--static struct phm_master_table_header tonga_thermal_start_thermal_controller_master = {
-+static const struct phm_master_table_header tonga_thermal_start_thermal_controller_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	tonga_thermal_start_thermal_controller_master_list
- };
- 
--static struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = {
-+static const struct phm_master_table_item tonga_thermal_set_temperature_range_master_list[] = {
- 	{ NULL, tf_tonga_thermal_disable_alert},
- 	{ NULL, tf_tonga_thermal_set_temperature_range},
- 	{ NULL, tf_tonga_thermal_enable_alert},
- 	{ NULL, NULL }
- };
- 
--struct phm_master_table_header tonga_thermal_set_temperature_range_master = {
-+static const struct phm_master_table_header tonga_thermal_set_temperature_range_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	tonga_thermal_set_temperature_range_master_list
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 928f5a7..e1ca36c 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -141,7 +141,7 @@ enum phm_master_table_flag {
- struct phm_master_table_header {
- 	uint32_t storage_size;
- 	uint32_t flags;
--	struct phm_master_table_item *master_list;
-+	const struct phm_master_table_item *master_list;
- };
- 
- struct phm_runtime_table_header {
-@@ -199,7 +199,7 @@ extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
- 			      void *input, void *output);
- 
- extern int phm_construct_table(struct pp_hwmgr *hwmgr,
--			       struct phm_master_table_header *master_table,
-+			       const struct phm_master_table_header *master_table,
- 			       struct phm_runtime_table_header *rt_table);
- 
- extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0476-drm-amd-make-some-function-local-tables-static-const.patch b/common/recipes-kernel/linux/files/0476-drm-amd-make-some-function-local-tables-static-const.patch
deleted file mode 100644
index c8ffd833..00000000
--- a/common/recipes-kernel/linux/files/0476-drm-amd-make-some-function-local-tables-static-const.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 56f49f8e2454f2b0b66f5dc2c24d29e49bbac0ae Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 10 Apr 2016 16:30:04 +0200
-Subject: [PATCH 0476/1110] drm/amd: make some function-local tables static
- const
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-These tables were initialized on stack on each call, avoid that
-and save a little bit of text size.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c   | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c  | 2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h | 8 ++++----
- 3 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
-index cd639c3..33e47a4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
-@@ -141,7 +141,7 @@ out_cleanup:
- void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)
- {
- 	int i;
--	int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = {
-+	static const int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = {
- 		640 * 480 * 4,
- 		720 * 480 * 4,
- 		800 * 600 * 4,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
-index 119cdc2..60a0c9a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
-@@ -439,7 +439,7 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
- 	struct drm_display_mode *mode = NULL;
- 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
- 	int i;
--	struct mode_size {
-+	static const struct mode_size {
- 		int w;
- 		int h;
- 	} common_modes[17] = {
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-index b10df32..009bd59 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
-@@ -127,8 +127,8 @@ fInt fExponential(fInt exponent)        /*Can be used to calculate e^exponent*/
- 	fInt solution = fPositiveOne; /*Starting off with baseline of 1 */
- 	fInt error_term;
- 
--	uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
--	uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
-+	static const uint32_t k_array[11] = {55452, 27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
-+	static const uint32_t expk_array[11] = {2560000, 160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
- 
- 	if (GreaterThan(fZERO, exponent)) {
- 		exponent = fNegate(exponent);
-@@ -162,8 +162,8 @@ fInt fNaturalLog(fInt value)
- 	fInt solution = ConvertToFraction(0); /*Starting off with baseline of 0 */
- 	fInt error_term;
- 
--	uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
--	uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
-+	static const uint32_t k_array[10] = {160000, 40000, 20000, 15000, 12500, 11250, 10625, 10313, 10156, 10078};
-+	static const uint32_t logk_array[10] = {27726, 13863, 6931, 4055, 2231, 1178, 606, 308, 155, 78};
- 
- 	while (GreaterThan(fAdd(value, fNegativeOne), upper_bound)) {
- 		for (i = 0; i < 10; i++) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0477-drm-amdgpu-handle-more-than-10-UVD-sessions-v2.patch b/common/recipes-kernel/linux/files/0477-drm-amdgpu-handle-more-than-10-UVD-sessions-v2.patch
deleted file mode 100644
index dc526e28..00000000
--- a/common/recipes-kernel/linux/files/0477-drm-amdgpu-handle-more-than-10-UVD-sessions-v2.patch
+++ /dev/null
@@ -1,243 +0,0 @@
-From bfdbc4f9e5d7bdaed2b60978d944c190cd729dee Mon Sep 17 00:00:00 2001
-From: Arindam Nath <arindam.nath@amd.com>
-Date: Tue, 12 Apr 2016 13:46:15 +0200
-Subject: [PATCH 0477/1110] drm/amdgpu: handle more than 10 UVD sessions (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Change History
---------------
-
-v2:
-- Make firmware version check correctly. Firmware
-  versions >= 1.80 should all support 40 UVD
-  instances.
-- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
-  variable.
-
-v1:
-- The firmware can handle upto 40 UVD sessions.
-
-Signed-off-by: Arindam Nath <arindam.nath@amd.com>
-Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h                | 11 +++++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c            | 30 ++++++++++++++++------
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c              |  5 ++--
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c              |  5 ++--
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c              |  7 +++--
- .../gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h   |  1 +
- 6 files changed, 41 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 7fe432d..bd80ea5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1596,16 +1596,19 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev);
- /*
-  * UVD
-  */
--#define AMDGPU_MAX_UVD_HANDLES	10
--#define AMDGPU_UVD_STACK_SIZE	(1024*1024)
--#define AMDGPU_UVD_HEAP_SIZE	(1024*1024)
--#define AMDGPU_UVD_FIRMWARE_OFFSET 256
-+#define AMDGPU_DEFAULT_UVD_HANDLES     10
-+#define AMDGPU_MAX_UVD_HANDLES         40
-+#define AMDGPU_UVD_STACK_SIZE          (200*1024)
-+#define AMDGPU_UVD_HEAP_SIZE           (256*1024)
-+#define AMDGPU_UVD_SESSION_SIZE                (50*1024)
-+#define AMDGPU_UVD_FIRMWARE_OFFSET     256
- 
- struct amdgpu_uvd {
- 	struct amdgpu_bo	*vcpu_bo;
- 	void			*cpu_addr;
- 	uint64_t		gpu_addr;
-         void                    *saved_bo;
-+        unsigned                max_handles;
- 	unsigned		fw_version;
- 	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
- 	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 86dead7..cb6990a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -151,6 +151,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- 		return r;
- 	}
- 
-+	/* Set the default UVD handles that the firmware can handle */
-+	adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
-+
- 	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
- 	family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
- 	version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
-@@ -161,8 +164,19 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- 	adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
- 				(family_id << 8));
- 
-+	/*
-+	 * Limit the number of UVD handles depending on microcode major
-+	 * and minor versions. The firmware version which has 40 UVD
-+	 * instances support is 1.80. So all subsequent versions should
-+	 * also have the same support.
-+	 */
-+	if ((version_major > 0x01) ||
-+	    ((version_major == 0x01) && (version_minor >= 0x50)))
-+		adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
-+
- 	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
--		 +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
-+		  +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
-+		  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
- 	r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
- 			     AMDGPU_GEM_DOMAIN_VRAM,
- 			     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
-@@ -205,7 +219,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
-                 return r;
-         }
- 
--	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
-+	for (i = 0; i < adev->uvd.max_handles; ++i) {
- 		atomic_set(&adev->uvd.handles[i], 0);
- 		adev->uvd.filp[i] = NULL;
- 	}
-@@ -250,7 +264,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
- 	if (adev->uvd.vcpu_bo == NULL)
- 		return 0;
- 
--        for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
-+        for (i = 0; i < adev->uvd.max_handles; ++i)
-                 if (atomic_read(&adev->uvd.handles[i]))
-                         break;
-  
-@@ -307,7 +321,7 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
- 	struct amdgpu_ring *ring = &adev->uvd.ring;
- 	int i, r;
- 
--	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
-+        for (i = 0; i < adev->uvd.max_handles; ++i) {
- 		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
- 		if (handle != 0 && adev->uvd.filp[i] == filp) {
- 			struct fence *fence;
-@@ -567,7 +581,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 		amdgpu_bo_kunmap(bo);
- 
- 		/* try to alloc a new handle */
--		for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
-+                for (i = 0; i < adev->uvd.max_handles; ++i) {
- 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
- 				DRM_ERROR("Handle 0x%x already in use!\n", handle);
- 				return -EINVAL;
-@@ -590,7 +604,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 			return r;
- 
- 		/* validate the handle */
--		for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
-+                for (i = 0; i < adev->uvd.max_handles; ++i) {
- 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
- 				if (adev->uvd.filp[i] != ctx->parser->filp) {
- 					DRM_ERROR("UVD handle collision detected!\n");
-@@ -605,7 +619,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 
- 	case 2:
- 		/* it's a destroy msg, free the handle */
--		for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
-+                for (i = 0; i < adev->uvd.max_handles; ++i)
- 			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
- 		amdgpu_bo_kunmap(bo);
- 		return 0;
-@@ -1032,7 +1046,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
- 
- 	fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
- 
--	for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
-+	for (i = 0; i < adev->uvd.max_handles; ++i)
- 		if (atomic_read(&adev->uvd.handles[i]))
- 			++handles;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index cb46375..0d6b9e2 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -559,12 +559,13 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
- 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
- 
- 	addr += size;
--	size = AMDGPU_UVD_STACK_SIZE >> 3;
-+	size = AMDGPU_UVD_HEAP_SIZE >> 3;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
- 
- 	addr += size;
--	size = AMDGPU_UVD_HEAP_SIZE >> 3;
-+	size = (AMDGPU_UVD_STACK_SIZE +
-+	       (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index de459c8..84abf89 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -272,12 +272,13 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
- 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
- 
- 	offset += size;
--	size = AMDGPU_UVD_STACK_SIZE;
-+	size = AMDGPU_UVD_HEAP_SIZE;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
- 
- 	offset += size;
--	size = AMDGPU_UVD_HEAP_SIZE;
-+	size = AMDGPU_UVD_STACK_SIZE +
-+	       (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 372d70a..c633b1a 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -272,18 +272,21 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
- 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
- 
- 	offset += size;
--	size = AMDGPU_UVD_STACK_SIZE;
-+	size = AMDGPU_UVD_HEAP_SIZE;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
- 
- 	offset += size;
--	size = AMDGPU_UVD_HEAP_SIZE;
-+	size = AMDGPU_UVD_STACK_SIZE +
-+	       (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
- 
- 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
- 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-+
-+	WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
- }
- 
- #if 0
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
-index b2d4aaf..6f6fb34 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
-@@ -111,5 +111,6 @@
- #define mmUVD_MIF_RECON1_ADDR_CONFIG                                            0x39c5
- #define ixUVD_MIF_SCLR_ADDR_CONFIG                                              0x4
- #define mmUVD_JPEG_ADDR_CONFIG                                                  0x3a1f
-+#define mmUVD_GP_SCRATCH4                                                       0x3d38
- 
- #endif /* UVD_6_0_D_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch b/common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch
deleted file mode 100644
index 09a41286..00000000
--- a/common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch
+++ /dev/null
@@ -1,840 +0,0 @@
-From 674cd6d2ced8478f7ed20d5f15c621cc649cf7b1 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Tue, 12 Apr 2016 13:25:48 +1000
-Subject: [PATCH 0478/1110] drm/amd: make a type-safe cgs_device struct. (v2)
-
-This is just a type-safety things to avoid everyone taking void *,
-it doesn't change anything.
-
-v2: agd5f: split out the dal changes into a separate patch.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/acp/acp_hw.c             |  2 +-
- drivers/gpu/drm/amd/acp/include/acp_gfx_if.h |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu.h          | 11 +---
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h      |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c      | 92 ++++++++++++++--------------
- drivers/gpu/drm/amd/include/cgs_common.h     | 76 ++++++++++++-----------
- drivers/gpu/drm/amd/include/cgs_linux.h      |  6 +-
- 7 files changed, 93 insertions(+), 98 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/acp/acp_hw.c b/drivers/gpu/drm/amd/acp/acp_hw.c
-index 7af83f1..c7d7205 100644
---- a/drivers/gpu/drm/amd/acp/acp_hw.c
-+++ b/drivers/gpu/drm/amd/acp/acp_hw.c
-@@ -34,7 +34,7 @@
- 
- #define mmACP_AZALIA_I2S_SELECT 0x51d4
- 
--int amd_acp_hw_init(void *cgs_device,
-+int amd_acp_hw_init(struct cgs_device *cgs_device,
- 		    unsigned acp_version_major, unsigned acp_version_minor)
- {
- 	unsigned int acp_mode = ACP_MODE_I2S;
-diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
-index bccf47b..a72ddb2 100644
---- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
-+++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h
-@@ -28,7 +28,7 @@
- #include "cgs_linux.h"
- #include "cgs_common.h"
- 
--int amd_acp_hw_init(void *cgs_device,
-+int amd_acp_hw_init(struct cgs_device *cgs_device,
- 		    unsigned acp_version_major, unsigned acp_version_minor);
- 
- #endif /* _ACP_GFX_IF_H */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index bd80ea5..47a3c8f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1872,15 +1872,8 @@ struct amdgpu_atcs {
- /*
-  * CGS
-  */
--void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
--void amdgpu_cgs_destroy_device(void *cgs_device);
--
--
--/*
-- * CGS
-- */
--void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
--void amdgpu_cgs_destroy_device(void *cgs_device);
-+struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
-+void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
- 
- 
- /* GPU virtualization */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-index f6e32a6..8a39631 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h
-@@ -30,7 +30,7 @@
- 
- struct amdgpu_acp {
- 	struct device *parent;
--	void *cgs_device;
-+	struct cgs_device *cgs_device;
- 	struct amd_acp_private *private;
- 	struct mfd_cell *acp_cell;
- 	struct resource *acp_res;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 6043dc7..8b653f2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -42,7 +42,7 @@ struct amdgpu_cgs_device {
- 	struct amdgpu_device *adev =					\
- 		((struct amdgpu_cgs_device *)cgs_device)->adev
- 
--static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
-+static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
- 				   uint64_t *mc_start, uint64_t *mc_size,
- 				   uint64_t *mem_size)
- {
-@@ -73,7 +73,7 @@ static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
- 	return 0;
- }
- 
--static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
-+static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
- 				uint64_t size,
- 				uint64_t min_offset, uint64_t max_offset,
- 				cgs_handle_t *kmem_handle, uint64_t *mcaddr)
-@@ -102,7 +102,7 @@ static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
- 	return ret;
- }
- 
--static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
-+static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
- {
- 	struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
- 
-@@ -118,7 +118,7 @@ static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
- 	return 0;
- }
- 
--static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
-+static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
- 				    enum cgs_gpu_mem_type type,
- 				    uint64_t size, uint64_t align,
- 				    uint64_t min_offset, uint64_t max_offset,
-@@ -208,7 +208,7 @@ static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
- 	return ret;
- }
- 
--static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
-+static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
- {
- 	struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
- 
-@@ -225,7 +225,7 @@ static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
- 	return 0;
- }
- 
--static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
-+static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
- 				   uint64_t *mcaddr)
- {
- 	int r;
-@@ -246,7 +246,7 @@ static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
- 	return r;
- }
- 
--static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
-+static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
- {
- 	int r;
- 	struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
-@@ -258,7 +258,7 @@ static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
- 	return r;
- }
- 
--static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
-+static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
- 				   void **map)
- {
- 	int r;
-@@ -271,7 +271,7 @@ static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
- 	return r;
- }
- 
--static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
-+static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
- {
- 	int r;
- 	struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
-@@ -283,20 +283,20 @@ static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
- 	return r;
- }
- 
--static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
-+static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
- {
- 	CGS_FUNC_ADEV;
- 	return RREG32(offset);
- }
- 
--static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
-+static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
- 				      uint32_t value)
- {
- 	CGS_FUNC_ADEV;
- 	WREG32(offset, value);
- }
- 
--static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
-+static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
- 					     enum cgs_ind_reg space,
- 					     unsigned index)
- {
-@@ -320,7 +320,7 @@ static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
- 	return 0;
- }
- 
--static void amdgpu_cgs_write_ind_register(void *cgs_device,
-+static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
- 					  enum cgs_ind_reg space,
- 					  unsigned index, uint32_t value)
- {
-@@ -343,7 +343,7 @@ static void amdgpu_cgs_write_ind_register(void *cgs_device,
- 	WARN(1, "Invalid indirect register space");
- }
- 
--static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
-+static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
- {
- 	CGS_FUNC_ADEV;
- 	uint8_t val;
-@@ -353,7 +353,7 @@ static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
- 	return val;
- }
- 
--static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
-+static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
- {
- 	CGS_FUNC_ADEV;
- 	uint16_t val;
-@@ -363,7 +363,7 @@ static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
- 	return val;
- }
- 
--static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
-+static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
- 						 unsigned addr)
- {
- 	CGS_FUNC_ADEV;
-@@ -374,7 +374,7 @@ static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
- 	return val;
- }
- 
--static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
-+static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
- 					     uint8_t value)
- {
- 	CGS_FUNC_ADEV;
-@@ -382,7 +382,7 @@ static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
- 	WARN(ret, "pci_write_config_byte error");
- }
- 
--static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
-+static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
- 					     uint16_t value)
- {
- 	CGS_FUNC_ADEV;
-@@ -390,7 +390,7 @@ static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
- 	WARN(ret, "pci_write_config_word error");
- }
- 
--static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
-+static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
- 					      uint32_t value)
- {
- 	CGS_FUNC_ADEV;
-@@ -399,7 +399,7 @@ static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
- }
- 
- 
--static int amdgpu_cgs_get_pci_resource(void *cgs_device,
-+static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
- 				       enum cgs_resource_type resource_type,
- 				       uint64_t size,
- 				       uint64_t offset,
-@@ -433,7 +433,7 @@ static int amdgpu_cgs_get_pci_resource(void *cgs_device,
- 	}
- }
- 
--static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
-+static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
- 						  unsigned table, uint16_t *size,
- 						  uint8_t *frev, uint8_t *crev)
- {
-@@ -449,7 +449,7 @@ static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
- 	return NULL;
- }
- 
--static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
-+static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
- 					      uint8_t *frev, uint8_t *crev)
- {
- 	CGS_FUNC_ADEV;
-@@ -462,7 +462,7 @@ static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
- 	return -EINVAL;
- }
- 
--static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
-+static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
- 					  void *args)
- {
- 	CGS_FUNC_ADEV;
-@@ -471,33 +471,33 @@ static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
- 		adev->mode_info.atom_context, table, args);
- }
- 
--static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
-+static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
- {
- 	/* TODO */
- 	return 0;
- }
- 
--static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
-+static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
- {
- 	/* TODO */
- 	return 0;
- }
- 
--static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
-+static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
- 				     int active)
- {
- 	/* TODO */
- 	return 0;
- }
- 
--static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
-+static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
- 				       enum cgs_clock clock, unsigned freq)
- {
- 	/* TODO */
- 	return 0;
- }
- 
--static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
-+static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
- 					enum cgs_engine engine, int powered)
- {
- 	/* TODO */
-@@ -506,7 +506,7 @@ static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
- 
- 
- 
--static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
-+static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
- 					    enum cgs_clock clock,
- 					    struct cgs_clock_limits *limits)
- {
-@@ -514,7 +514,7 @@ static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
- 	return 0;
- }
- 
--static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
-+static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
- 					  const uint32_t *voltages)
- {
- 	DRM_ERROR("not implemented");
-@@ -565,7 +565,7 @@ static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
- 	.process = cgs_process_irq,
- };
- 
--static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
-+static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id,
- 				     unsigned num_types,
- 				     cgs_irq_source_set_func_t set,
- 				     cgs_irq_handler_func_t handler,
-@@ -600,19 +600,19 @@ static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
- 	return ret;
- }
- 
--static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
-+static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
- {
- 	CGS_FUNC_ADEV;
- 	return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
- }
- 
--static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
-+static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
- {
- 	CGS_FUNC_ADEV;
- 	return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
- }
- 
--int amdgpu_cgs_set_clockgating_state(void *cgs_device,
-+int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
- 				  enum amd_ip_block_type block_type,
- 				  enum amd_clockgating_state state)
- {
-@@ -633,7 +633,7 @@ int amdgpu_cgs_set_clockgating_state(void *cgs_device,
- 	return r;
- }
- 
--int amdgpu_cgs_set_powergating_state(void *cgs_device,
-+int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
- 				  enum amd_ip_block_type block_type,
- 				  enum amd_powergating_state state)
- {
-@@ -655,7 +655,7 @@ int amdgpu_cgs_set_powergating_state(void *cgs_device,
- }
- 
- 
--static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type)
-+static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
- {
- 	CGS_FUNC_ADEV;
- 	enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
-@@ -695,7 +695,7 @@ static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type)
- 	return result;
- }
- 
--static int amdgpu_cgs_get_firmware_info(void *cgs_device,
-+static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
- 					enum cgs_ucode_id type,
- 					struct cgs_firmware_info *info)
- {
-@@ -774,7 +774,7 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device,
- 	return 0;
- }
- 
--static int amdgpu_cgs_query_system_info(void *cgs_device,
-+static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
- 				struct cgs_system_info *sys_info)
- {
- 	CGS_FUNC_ADEV;
-@@ -808,7 +808,7 @@ static int amdgpu_cgs_query_system_info(void *cgs_device,
- 	return 0;
- }
- 
--static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
-+static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
- 					  struct cgs_display_info *info)
- {
- 	CGS_FUNC_ADEV;
-@@ -851,7 +851,7 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
- }
- 
- 
--static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled)
-+static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
- {
- 	CGS_FUNC_ADEV;
- 
-@@ -867,7 +867,7 @@ static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled)
-  */
- 
- #if defined(CONFIG_ACPI)
--static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
-+static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
- 				    struct cgs_acpi_method_info *info)
- {
- 	CGS_FUNC_ADEV;
-@@ -1030,14 +1030,14 @@ error:
- 	return result;
- }
- #else
--static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
-+static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
- 				struct cgs_acpi_method_info *info)
- {
- 	return -EIO;
- }
- #endif
- 
--int amdgpu_cgs_call_acpi_method(void *cgs_device,
-+int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
- 					uint32_t acpi_method,
- 					uint32_t acpi_function,
- 					void *pinput, void *poutput,
-@@ -1121,7 +1121,7 @@ static const struct cgs_os_ops amdgpu_cgs_os_ops = {
- 	amdgpu_cgs_irq_put
- };
- 
--void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
-+struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
- {
- 	struct amdgpu_cgs_device *cgs_device =
- 		kmalloc(sizeof(*cgs_device), GFP_KERNEL);
-@@ -1135,10 +1135,10 @@ void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
- 	cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
- 	cgs_device->adev = adev;
- 
--	return cgs_device;
-+	return (struct cgs_device *)cgs_device;
- }
- 
--void amdgpu_cgs_destroy_device(void *cgs_device)
-+void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
- {
- 	kfree(cgs_device);
- }
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index ab84d49..ca1e229 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -26,6 +26,8 @@
- 
- #include "amd_shared.h"
- 
-+struct cgs_device;
-+
- /**
-  * enum cgs_gpu_mem_type - GPU memory types
-  */
-@@ -223,7 +225,7 @@ struct cgs_acpi_method_info {
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
-+typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
- 				  uint64_t *mc_start, uint64_t *mc_size,
- 				  uint64_t *mem_size);
- 
-@@ -239,7 +241,7 @@ typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
-+typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
- 			       uint64_t min_offset, uint64_t max_offset,
- 			       cgs_handle_t *kmem_handle, uint64_t *mcaddr);
- 
-@@ -250,7 +252,7 @@ typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
-+typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
- 
- /**
-  * cgs_alloc_gpu_mem() - Allocate GPU memory
-@@ -279,7 +281,7 @@ typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
-+typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
- 				   uint64_t size, uint64_t align,
- 				   uint64_t min_offset, uint64_t max_offset,
- 				   cgs_handle_t *handle);
-@@ -291,7 +293,7 @@ typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
-+typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
- 
- /**
-  * cgs_gmap_gpu_mem() - GPU-map GPU memory
-@@ -303,7 +305,7 @@ typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
-+typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
- 				  uint64_t *mcaddr);
- 
- /**
-@@ -315,7 +317,7 @@ typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
-+typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
- 
- /**
-  * cgs_kmap_gpu_mem() - Kernel-map GPU memory
-@@ -326,7 +328,7 @@ typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
-+typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
- 				  void **map);
- 
- /**
-@@ -336,7 +338,7 @@ typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
-+typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
- 
- /**
-  * cgs_read_register() - Read an MMIO register
-@@ -345,7 +347,7 @@ typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
-  *
-  * Return:  register value
-  */
--typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
-+typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
- 
- /**
-  * cgs_write_register() - Write an MMIO register
-@@ -353,7 +355,7 @@ typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
-  * @offset:	register offset
-  * @value:	register value
-  */
--typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
-+typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
- 				     uint32_t value);
- 
- /**
-@@ -363,7 +365,7 @@ typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
-  *
-  * Return:  register value
-  */
--typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
-+typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
- 					    unsigned index);
- 
- /**
-@@ -372,7 +374,7 @@ typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg s
-  * @offset:	register offset
-  * @value:	register value
-  */
--typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
-+typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
- 					 unsigned index, uint32_t value);
- 
- /**
-@@ -382,7 +384,7 @@ typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg spac
-  *
-  * Return:  Value read
-  */
--typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
-+typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
- 
- /**
-  * cgs_read_pci_config_word() - Read word from PCI configuration space
-@@ -391,7 +393,7 @@ typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
-  *
-  * Return:  Value read
-  */
--typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
-+typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
- 
- /**
-  * cgs_read_pci_config_dword() - Read dword from PCI configuration space
-@@ -400,7 +402,7 @@ typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
-  *
-  * Return:  Value read
-  */
--typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
-+typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
- 						unsigned addr);
- 
- /**
-@@ -409,7 +411,7 @@ typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
-  * @addr:	address
-  * @value:	value to write
-  */
--typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
-+typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
- 					    uint8_t value);
- 
- /**
-@@ -418,7 +420,7 @@ typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
-  * @addr:	address, must be word-aligned
-  * @value:	value to write
-  */
--typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
-+typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
- 					    uint16_t value);
- 
- /**
-@@ -427,7 +429,7 @@ typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
-  * @addr:	address, must be dword-aligned
-  * @value:	value to write
-  */
--typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
-+typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
- 					     uint32_t value);
- 
- 
-@@ -441,7 +443,7 @@ typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
-  *
-  * Return: 0 on success, -errno otherwise
-  */
--typedef int (*cgs_get_pci_resource_t)(void *cgs_device,
-+typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
- 				      enum cgs_resource_type resource_type,
- 				      uint64_t size,
- 				      uint64_t offset,
-@@ -458,7 +460,7 @@ typedef int (*cgs_get_pci_resource_t)(void *cgs_device,
-  * Return: Pointer to start of the table, or NULL on failure
-  */
- typedef const void *(*cgs_atom_get_data_table_t)(
--	void *cgs_device, unsigned table,
-+	struct cgs_device *cgs_device, unsigned table,
- 	uint16_t *size, uint8_t *frev, uint8_t *crev);
- 
- /**
-@@ -470,7 +472,7 @@ typedef const void *(*cgs_atom_get_data_table_t)(
-  *
-  * Return: 0 on success, -errno otherwise
-  */
--typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
-+typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
- 					     uint8_t *frev, uint8_t *crev);
- 
- /**
-@@ -481,7 +483,7 @@ typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
-  *
-  * Return: 0 on success, -errno otherwise
-  */
--typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
-+typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
- 					 unsigned table, void *args);
- 
- /**
-@@ -491,7 +493,7 @@ typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
-+typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
- 
- /**
-  * cgs_destroy_pm_request() - Destroy a power management request
-@@ -500,7 +502,7 @@ typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
-+typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
- 
- /**
-  * cgs_set_pm_request() - Activate or deactiveate a PM request
-@@ -516,7 +518,7 @@ typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
-+typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
- 				    int active);
- 
- /**
-@@ -528,7 +530,7 @@ typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
-+typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
- 				      enum cgs_clock clock, unsigned freq);
- 
- /**
-@@ -540,7 +542,7 @@ typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
-+typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
- 				       enum cgs_engine engine, int powered);
- 
- /**
-@@ -551,7 +553,7 @@ typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
-+typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
- 					   enum cgs_clock clock,
- 					   struct cgs_clock_limits *limits);
- 
-@@ -563,7 +565,7 @@ typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
-  *
-  * Return: 0 on success, -errno otherwise
-  */
--typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
-+typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
- 					 const uint32_t *voltages);
- /**
-  * cgs_get_firmware_info - Get the firmware information from core driver
-@@ -573,25 +575,25 @@ typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
-  *
-  * Return: 0 on success, -errno otherwise
-  */
--typedef int (*cgs_get_firmware_info)(void *cgs_device,
-+typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
- 				     enum cgs_ucode_id type,
- 				     struct cgs_firmware_info *info);
- 
--typedef int(*cgs_set_powergating_state)(void *cgs_device,
-+typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
- 				  enum amd_ip_block_type block_type,
- 				  enum amd_powergating_state state);
- 
--typedef int(*cgs_set_clockgating_state)(void *cgs_device,
-+typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
- 				  enum amd_ip_block_type block_type,
- 				  enum amd_clockgating_state state);
- 
- typedef int(*cgs_get_active_displays_info)(
--					void *cgs_device,
-+					struct cgs_device *cgs_device,
- 					struct cgs_display_info *info);
- 
--typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled);
-+typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
- 
--typedef int (*cgs_call_acpi_method)(void *cgs_device,
-+typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
- 					uint32_t acpi_method,
- 					uint32_t acpi_function,
- 					void *pinput, void *poutput,
-@@ -599,7 +601,7 @@ typedef int (*cgs_call_acpi_method)(void *cgs_device,
- 					uint32_t input_size,
- 					uint32_t output_size);
- 
--typedef int (*cgs_query_system_info)(void *cgs_device,
-+typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
- 				struct cgs_system_info *sys_info);
- 
- struct cgs_ops {
-diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h
-index 3b47ae3..ca4f600 100644
---- a/drivers/gpu/drm/amd/include/cgs_linux.h
-+++ b/drivers/gpu/drm/amd/include/cgs_linux.h
-@@ -66,7 +66,7 @@ typedef int (*cgs_irq_handler_func_t)(void *private_data,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id,
-+typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_id,
- 				    unsigned num_types,
- 				    cgs_irq_source_set_func_t set,
- 				    cgs_irq_handler_func_t handler,
-@@ -83,7 +83,7 @@ typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id,
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type);
-+typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type);
- 
- /**
-  * cgs_irq_put() - Indicate IRQ source is no longer needed
-@@ -98,7 +98,7 @@ typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type);
-  *
-  * Return:  0 on success, -errno otherwise
-  */
--typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned src_id, unsigned type);
-+typedef int (*cgs_irq_put_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type);
- 
- struct cgs_os_ops {
- 	/* IRQ handling */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0479-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch b/common/recipes-kernel/linux/files/0479-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch
deleted file mode 100644
index a414dcd4..00000000
--- a/common/recipes-kernel/linux/files/0479-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 1c8d1b39c9dc09a04add29781db119ed9a042744 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 11 Apr 2016 14:27:51 -0400
-Subject: [PATCH 0479/1110] drm/amd/powerplay: fix fan speed percent setting
- error on Tonga
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-index 23f8463..47ef1ca 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_thermal.c
-@@ -195,8 +195,8 @@ int tonga_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed)
- 	if (0 == duty100)
- 		return -EINVAL;
- 
--	tmp64 = (uint64_t)speed * 100;
--	do_div(tmp64, duty100);
-+	tmp64 = (uint64_t)speed * duty100;
-+	do_div(tmp64, 100);
- 	duty = (uint32_t)tmp64;
- 
- 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0480-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch b/common/recipes-kernel/linux/files/0480-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch
deleted file mode 100644
index 7b52f7fa..00000000
--- a/common/recipes-kernel/linux/files/0480-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From ec3f52436589a4b347443fec0181f4143cf2c52a Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 11 Apr 2016 14:28:55 -0400
-Subject: [PATCH 0480/1110] drm/amd/powerplay: fix fan speed percent setting
- error on Fiji
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-index e2b448f..92976b6 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_thermal.c
-@@ -221,8 +221,8 @@ int fiji_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
- 	if (duty100 == 0)
- 		return -EINVAL;
- 
--	tmp64 = (uint64_t)speed * 100;
--	do_div(tmp64, duty100);
-+	tmp64 = (uint64_t)speed * duty100;
-+	do_div(tmp64, 100);
- 	duty = (uint32_t)tmp64;
- 
- 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0481-drm-amdgpu-use-max_dw-in-ring_init.patch b/common/recipes-kernel/linux/files/0481-drm-amdgpu-use-max_dw-in-ring_init.patch
deleted file mode 100644
index 56c731e4..00000000
--- a/common/recipes-kernel/linux/files/0481-drm-amdgpu-use-max_dw-in-ring_init.patch
+++ /dev/null
@@ -1,231 +0,0 @@
-From 1e23c826e9bd76db7279a457a9a4051c9937baee Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 12 Apr 2016 16:26:34 +0200
-Subject: [PATCH 0481/1110] drm/amdgpu: use max_dw in ring_init
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Instead of specifying the total ring size calculate that from the maximum
-number of dw a submission can have and the number of concurrent submissions.
-
-This fixes UVD with 8 concurrent submissions or more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 +++++---------
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    |  4 ++--
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    |  4 ++--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    |  4 ++--
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    |  4 ++--
- 10 files changed, 18 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 7bd31ae..a91eca4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -215,18 +215,17 @@ int amdgpu_ring_restore(struct amdgpu_ring *ring,
-  *
-  * @adev: amdgpu_device pointer
-  * @ring: amdgpu_ring structure holding ring information
-- * @ring_size: size of the ring
-+ * @max_ndw: maximum number of dw for ring alloc
-  * @nop: nop packet for this ring
-  *
-  * Initialize the driver information for the selected ring (all asics).
-  * Returns 0 on success, error on failure.
-  */
- int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
--		     unsigned ring_size, u32 nop, u32 align_mask,
-+		     unsigned max_dw, u32 nop, u32 align_mask,
- 		     struct amdgpu_irq_src *irq_src, unsigned irq_type,
- 		     enum amdgpu_ring_type ring_type)
- {
--	u32 rb_bufsz;
- 	int r;
- 
- 	if (ring->adev == NULL) {
-@@ -283,10 +282,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		return r;
- 	}
- 
--	/* Align ring size */
--	rb_bufsz = order_base_2(ring_size / 8);
--	ring_size = (1 << (rb_bufsz + 1)) * 4;
--	ring->ring_size = ring_size;
-+	ring->ring_size = roundup_pow_of_two(max_dw * 4 *
-+					     amdgpu_sched_hw_submission);
- 	ring->align_mask = align_mask;
- 	ring->nop = nop;
- 	ring->type = ring_type;
-@@ -319,8 +316,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		}
- 	}
- 	ring->ptr_mask = (ring->ring_size / 4) - 1;
--	ring->max_dw = DIV_ROUND_UP(ring->ring_size / 4,
--				    amdgpu_sched_hw_submission);
-+	ring->max_dw = max_dw;
- 
- 	if (amdgpu_debugfs_ring_init(adev, ring)) {
- 		DRM_ERROR("Failed to register debugfs file for rings !\n");
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index dd0cc1b..2a1e83f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -976,7 +976,7 @@ static int cik_sdma_sw_init(void *handle)
- 		ring = &adev->sdma.instance[i].ring;
- 		ring->ring_obj = NULL;
- 		sprintf(ring->name, "sdma%d", i);
--		r = amdgpu_ring_init(adev, ring, 256 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 32 * 1024,
- 				     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
- 				     &adev->sdma.trap_irq,
- 				     (i == 0) ?
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 177eb78..967150c 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4414,7 +4414,7 @@ static int gfx_v7_0_sw_init(void *handle)
- 		ring = &adev->gfx.gfx_ring[i];
- 		ring->ring_obj = NULL;
- 		sprintf(ring->name, "gfx");
--		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 128 * 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
- 				     AMDGPU_RING_TYPE_GFX);
-@@ -4441,7 +4441,7 @@ static int gfx_v7_0_sw_init(void *handle)
- 		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
- 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
- 		/* type-2 packets are deprecated on MEC, use type-3 instead */
--		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 128 * 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, irq_type,
- 				     AMDGPU_RING_TYPE_COMPUTE);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 066f349..9839d4e 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1570,7 +1570,7 @@ static int gfx_v8_0_sw_init(void *handle)
- 			ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
- 		}
- 
--		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 128 * 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
- 				     AMDGPU_RING_TYPE_GFX);
-@@ -1597,7 +1597,7 @@ static int gfx_v8_0_sw_init(void *handle)
- 		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
- 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
- 		/* type-2 packets are deprecated on MEC, use type-3 instead */
--		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 128 * 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, irq_type,
- 				     AMDGPU_RING_TYPE_COMPUTE);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 96b63d9..82dc1e5 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -990,7 +990,7 @@ static int sdma_v2_4_sw_init(void *handle)
- 		ring->ring_obj = NULL;
- 		ring->use_doorbell = false;
- 		sprintf(ring->name, "sdma%d", i);
--		r = amdgpu_ring_init(adev, ring, 256 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 32 * 1024,
- 				     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
- 				     &adev->sdma.trap_irq,
- 				     (i == 0) ?
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index 0d6b9e2..c257cfa 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -114,7 +114,7 @@ static int uvd_v4_2_sw_init(void *handle)
- 
- 	ring = &adev->uvd.ring;
- 	sprintf(ring->name, "uvd");
--	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
- 			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
- 
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 84abf89..5f0d4f7 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -111,7 +111,7 @@ static int uvd_v5_0_sw_init(void *handle)
- 
- 	ring = &adev->uvd.ring;
- 	sprintf(ring->name, "uvd");
--	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
- 			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
- 
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index c633b1a..7e7c3da 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -112,7 +112,7 @@ static int uvd_v6_0_sw_init(void *handle)
- 
- 	ring = &adev->uvd.ring;
- 	sprintf(ring->name, "uvd");
--	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
- 			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
- 
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index c306cb9..ab9ee2a 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -201,14 +201,14 @@ static int vce_v2_0_sw_init(void *handle)
- 
- 	ring = &adev->vce.ring[0];
- 	sprintf(ring->name, "vce0");
--	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
- 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
- 	if (r)
- 		return r;
- 
- 	ring = &adev->vce.ring[1];
- 	sprintf(ring->name, "vce1");
--	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
- 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
- 	if (r)
- 		return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index ce468ee..bf7bc84 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -381,14 +381,14 @@ static int vce_v3_0_sw_init(void *handle)
- 
- 	ring = &adev->vce.ring[0];
- 	sprintf(ring->name, "vce0");
--	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
- 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
- 	if (r)
- 		return r;
- 
- 	ring = &adev->vce.ring[1];
- 	sprintf(ring->name, "vce1");
--	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
-+	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
- 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
- 	if (r)
- 		return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0482-drm-amdgpu-reduce-the-ring-size-for-GFX.patch b/common/recipes-kernel/linux/files/0482-drm-amdgpu-reduce-the-ring-size-for-GFX.patch
deleted file mode 100644
index e19770eb..00000000
--- a/common/recipes-kernel/linux/files/0482-drm-amdgpu-reduce-the-ring-size-for-GFX.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 98c76982a907e0d78d1f446cf1a869625e6079a7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 13 Apr 2016 10:27:35 +0200
-Subject: [PATCH 0482/1110] drm/amdgpu: reduce the ring size for GFX
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Those are way too large.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 967150c..35d2d4a 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4414,7 +4414,7 @@ static int gfx_v7_0_sw_init(void *handle)
- 		ring = &adev->gfx.gfx_ring[i];
- 		ring->ring_obj = NULL;
- 		sprintf(ring->name, "gfx");
--		r = amdgpu_ring_init(adev, ring, 128 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
- 				     AMDGPU_RING_TYPE_GFX);
-@@ -4441,7 +4441,7 @@ static int gfx_v7_0_sw_init(void *handle)
- 		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
- 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
- 		/* type-2 packets are deprecated on MEC, use type-3 instead */
--		r = amdgpu_ring_init(adev, ring, 128 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, irq_type,
- 				     AMDGPU_RING_TYPE_COMPUTE);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 9839d4e..d31fd9f 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1570,7 +1570,7 @@ static int gfx_v8_0_sw_init(void *handle)
- 			ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
- 		}
- 
--		r = amdgpu_ring_init(adev, ring, 128 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
- 				     AMDGPU_RING_TYPE_GFX);
-@@ -1597,7 +1597,7 @@ static int gfx_v8_0_sw_init(void *handle)
- 		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
- 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
- 		/* type-2 packets are deprecated on MEC, use type-3 instead */
--		r = amdgpu_ring_init(adev, ring, 128 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
- 				     &adev->gfx.eop_irq, irq_type,
- 				     AMDGPU_RING_TYPE_COMPUTE);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0483-drm-amdgpu-reduce-the-ring-size-for-SDMA.patch b/common/recipes-kernel/linux/files/0483-drm-amdgpu-reduce-the-ring-size-for-SDMA.patch
deleted file mode 100644
index aca1aeb5..00000000
--- a/common/recipes-kernel/linux/files/0483-drm-amdgpu-reduce-the-ring-size-for-SDMA.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 8973ac4fb3cef358c29cc26107c641863a39c3af Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 13 Apr 2016 10:30:13 +0200
-Subject: [PATCH 0483/1110] drm/amdgpu: reduce the ring size for SDMA
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Those are way too large.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  | 2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
- 3 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 2a1e83f..7e28b1c 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -976,7 +976,7 @@ static int cik_sdma_sw_init(void *handle)
- 		ring = &adev->sdma.instance[i].ring;
- 		ring->ring_obj = NULL;
- 		sprintf(ring->name, "sdma%d", i);
--		r = amdgpu_ring_init(adev, ring, 32 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
- 				     &adev->sdma.trap_irq,
- 				     (i == 0) ?
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 82dc1e5..9d8d3ef 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -990,7 +990,7 @@ static int sdma_v2_4_sw_init(void *handle)
- 		ring->ring_obj = NULL;
- 		ring->use_doorbell = false;
- 		sprintf(ring->name, "sdma%d", i);
--		r = amdgpu_ring_init(adev, ring, 32 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
- 				     &adev->sdma.trap_irq,
- 				     (i == 0) ?
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index aebf4b7..0122624 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1176,7 +1176,7 @@ static int sdma_v3_0_sw_init(void *handle)
- 			AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
- 
- 		sprintf(ring->name, "sdma%d", i);
--		r = amdgpu_ring_init(adev, ring, 256 * 1024,
-+		r = amdgpu_ring_init(adev, ring, 1024,
- 				     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
- 				     &adev->sdma.trap_irq,
- 				     (i == 0) ?
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0484-drm-amdgpu-use-the-ring-name-for-debugfs.patch b/common/recipes-kernel/linux/files/0484-drm-amdgpu-use-the-ring-name-for-debugfs.patch
deleted file mode 100644
index 1ef8fae6..00000000
--- a/common/recipes-kernel/linux/files/0484-drm-amdgpu-use-the-ring-name-for-debugfs.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 0e8b3339a04808bff246f83eebd3dfb7ab3204d0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 13 Apr 2016 11:34:44 +0200
-Subject: [PATCH 0484/1110] drm/amdgpu: use the ring name for debugfs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Instead of hard coding just another name in the ring code.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 49 ++++++++++++--------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    |  2 +-
- 3 files changed, 20 insertions(+), 33 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index a91eca4..0fd143d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -413,46 +413,33 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- 	return 0;
- }
- 
--/* TODO: clean this up !*/
--static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);
--static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);
--static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
--static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma.instance[0].ring);
--static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma.instance[1].ring);
--static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
--static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
--static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
--
--static const struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
--	{"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index},
--	{"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index},
--	{"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index},
--	{"amdgpu_ring_dma1", amdgpu_debugfs_ring_info, 0, &amdgpu_dma1_index},
--	{"amdgpu_ring_dma2", amdgpu_debugfs_ring_info, 0, &amdgpu_dma2_index},
--	{"amdgpu_ring_uvd", amdgpu_debugfs_ring_info, 0, &r600_uvd_index},
--	{"amdgpu_ring_vce1", amdgpu_debugfs_ring_info, 0, &si_vce1_index},
--	{"amdgpu_ring_vce2", amdgpu_debugfs_ring_info, 0, &si_vce2_index},
--};
-+static struct drm_info_list amdgpu_debugfs_ring_info_list[AMDGPU_MAX_RINGS];
-+static char amdgpu_debugs_ring_names[AMDGPU_MAX_RINGS][32];
- 
- #endif
- 
--static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)
-+static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
-+				    struct amdgpu_ring *ring)
- {
- #if defined(CONFIG_DEBUG_FS)
-+	unsigned offset = (uint8_t*)ring - (uint8_t*)adev;
- 	unsigned i;
--	for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
--		const struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
--		int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data;
--		struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset);
--		unsigned r;
- 
--		if (other != ring)
-+	for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
-+		struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
-+		char *name = amdgpu_debugs_ring_names[i];
-+
-+		if (!info->data) {
-+			sprintf(name, "amdgpu_ring_%s", ring->name);
-+			info->name = name;
-+			info->show = amdgpu_debugfs_ring_info;
-+			info->driver_features = 0;
-+			info->data = (void*)(uintptr_t)offset;
-+		} else if (info->data != (void*)(uintptr_t)offset)
- 			continue;
- 
--		r = amdgpu_debugfs_add_files(adev, info, 1);
--		if (r)
--			return r;
-+		return amdgpu_debugfs_add_files(adev, info, 1);
- 	}
- #endif
--	return 0;
-+	return -ENOSPC;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 35d2d4a..19b07a8 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4438,7 +4438,7 @@ static int gfx_v7_0_sw_init(void *handle)
- 		ring->me = 1; /* first MEC */
- 		ring->pipe = i / 8;
- 		ring->queue = i % 8;
--		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
-+		sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
- 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
- 		/* type-2 packets are deprecated on MEC, use type-3 instead */
- 		r = amdgpu_ring_init(adev, ring, 1024,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d31fd9f..6419aee 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1594,7 +1594,7 @@ static int gfx_v8_0_sw_init(void *handle)
- 		ring->me = 1; /* first MEC */
- 		ring->pipe = i / 8;
- 		ring->queue = i % 8;
--		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
-+		sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
- 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
- 		/* type-2 packets are deprecated on MEC, use type-3 instead */
- 		r = amdgpu_ring_init(adev, ring, 1024,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0485-drm-amdgpu-fix-the-coding-style-in-amdgpu_ring.c.patch b/common/recipes-kernel/linux/files/0485-drm-amdgpu-fix-the-coding-style-in-amdgpu_ring.c.patch
deleted file mode 100644
index 96176219..00000000
--- a/common/recipes-kernel/linux/files/0485-drm-amdgpu-fix-the-coding-style-in-amdgpu_ring.c.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 80fa1104a0784a2b30bfb15ce8807dd9f83bf3ce Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 13 Apr 2016 11:36:00 +0200
-Subject: [PATCH 0485/1110] drm/amdgpu: fix the coding style in amdgpu_ring.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-No functional change.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 0fd143d..bb4ec76 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -46,7 +46,8 @@
-  * wptr.  The GPU then starts fetching commands and executes
-  * them until the pointers are equal again.
-  */
--static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
-+static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
-+				    struct amdgpu_ring *ring);
- 
- /**
-  * amdgpu_ring_alloc - allocate space on the ring buffer
-@@ -264,7 +265,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r);
- 		return r;
- 	}
--	ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4);
-+	ring->next_rptr_gpu_addr = adev->wb.gpu_addr + ring->next_rptr_offs * 4;
- 	ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
- 
- 	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0486-drm-ttm-remove-use_ticket-parameter-from-ttm_bo_rese.patch b/common/recipes-kernel/linux/files/0486-drm-ttm-remove-use_ticket-parameter-from-ttm_bo_rese.patch
deleted file mode 100644
index b12ddb61..00000000
--- a/common/recipes-kernel/linux/files/0486-drm-ttm-remove-use_ticket-parameter-from-ttm_bo_rese.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 60c47d8b19d6620a21d9f3c442743896c35ae6b1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 6 Apr 2016 11:12:03 +0200
-Subject: [PATCH 0486/1110] drm/ttm: remove use_ticket parameter from
- ttm_bo_reserve
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not used any more.
-
-Reviewed-by: Sinclair Yeh <syeh@vmware.com>
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-index acc0801..bdb01d9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-@@ -71,7 +71,7 @@ static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
- {
- 	int r;
- 
--	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
-+	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
- 	if (unlikely(r != 0)) {
- 		if (r != -ERESTARTSYS)
- 			dev_err(bo->adev->dev, "%p reserve failed\n", bo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0487-drm-ttm-implement-LRU-add-callbacks-v2.patch b/common/recipes-kernel/linux/files/0487-drm-ttm-implement-LRU-add-callbacks-v2.patch
deleted file mode 100644
index 4a515009..00000000
--- a/common/recipes-kernel/linux/files/0487-drm-ttm-implement-LRU-add-callbacks-v2.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From c1fd9de7e6dce64e58b5a099c0a20c2ef0bf5dad Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 6 Apr 2016 11:12:07 +0200
-Subject: [PATCH 0487/1110] drm/ttm: implement LRU add callbacks v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows fine grained control for the driver where to add a BO into the LRU.
-
-v2: fix typo in comment
-
-Reviewed-by: Sinclair Yeh <syeh@vmware.com>
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 07fb3b3..1ec9491 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -923,6 +923,8 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
- 	.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
- 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
- 	.io_mem_free = &amdgpu_ttm_io_mem_free,
-+	.lru_tail = &ttm_bo_default_lru_tail,
-+	.swap_lru_tail = &ttm_bo_default_swap_lru_tail,
- };
- 
- int amdgpu_ttm_init(struct amdgpu_device *adev)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0488-drm-amdgpu-add-new-CG-flag-for-ROM-clockgating.patch b/common/recipes-kernel/linux/files/0488-drm-amdgpu-add-new-CG-flag-for-ROM-clockgating.patch
deleted file mode 100644
index 8247fc2c..00000000
--- a/common/recipes-kernel/linux/files/0488-drm-amdgpu-add-new-CG-flag-for-ROM-clockgating.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 92e827938dd5607545debf5500ef72b7a3f93859 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:52:24 -0400
-Subject: [PATCH 0488/1110] drm/amdgpu: add new CG flag for ROM clockgating
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/amd_shared.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index 04e4090..f8afe53 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -104,6 +104,7 @@ enum amd_powergating_state {
- #define AMD_CG_SUPPORT_VCE_MGCG			(1 << 14)
- #define AMD_CG_SUPPORT_HDP_LS			(1 << 15)
- #define AMD_CG_SUPPORT_HDP_MGCG			(1 << 16)
-+#define AMD_CG_SUPPORT_ROM_MGCG			(1 << 17)
- 
- /* PG flags */
- #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0489-drm-amdgpu-gfx-add-proper-CG-flags-for-fiji.patch b/common/recipes-kernel/linux/files/0489-drm-amdgpu-gfx-add-proper-CG-flags-for-fiji.patch
deleted file mode 100644
index cccb6269..00000000
--- a/common/recipes-kernel/linux/files/0489-drm-amdgpu-gfx-add-proper-CG-flags-for-fiji.patch
+++ /dev/null
@@ -1,183 +0,0 @@
-From af5ecee5dd91392608a90dad9908a9ccdd17286c Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 7 Apr 2016 18:38:00 -0400
-Subject: [PATCH 0489/1110] drm/amdgpu/gfx: add proper CG flags for fiji
-
-We were already enabling these CG features, this uses
-the standard interface for doing so.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 82 ++++++++++++++++++++---------------
- drivers/gpu/drm/amd/amdgpu/vi.c       |  9 +++-
- 2 files changed, 56 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 6419aee..48703cc 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4282,7 +4282,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
- }
- 
- static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
--		uint32_t reg_addr, uint32_t cmd)
-+				     uint32_t reg_addr, uint32_t cmd)
- {
- 	uint32_t data;
- 
-@@ -4312,23 +4312,29 @@ static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
- }
- 
- static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
--		bool enable)
-+						  bool enable)
- {
- 	uint32_t temp, data;
- 
- 	/* It is disabled by HW by default */
--	if (enable) {
--		/* 1 - RLC memory Light sleep */
--		temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
--		data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
--		if (temp != data)
--			WREG32(mmRLC_MEM_SLP_CNTL, data);
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
-+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
-+			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
-+				/* 1 - RLC memory Light sleep */
-+				temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
-+				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
-+				if (temp != data)
-+					WREG32(mmRLC_MEM_SLP_CNTL, data);
-+			}
- 
--		/* 2 - CP memory Light sleep */
--		temp = data = RREG32(mmCP_MEM_SLP_CNTL);
--		data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
--		if (temp != data)
--			WREG32(mmCP_MEM_SLP_CNTL, data);
-+			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
-+				/* 2 - CP memory Light sleep */
-+				temp = data = RREG32(mmCP_MEM_SLP_CNTL);
-+				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
-+				if (temp != data)
-+					WREG32(mmCP_MEM_SLP_CNTL, data);
-+			}
-+		}
- 
- 		/* 3 - RLC_CGTT_MGCG_OVERRIDE */
- 		temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-@@ -4346,17 +4352,21 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- 		/* 5 - clear mgcg override */
- 		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
- 
--		/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
--		temp = data = RREG32(mmCGTS_SM_CTRL_REG);
--		data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
--		data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
--		data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
--		data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
--		data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
--		data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
--		data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
--		if (temp != data)
--			WREG32(mmCGTS_SM_CTRL_REG, data);
-+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
-+			/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
-+			temp = data = RREG32(mmCGTS_SM_CTRL_REG);
-+			data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
-+			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
-+			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
-+			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
-+			if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
-+			    (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
-+				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
-+			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
-+			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
-+			if (temp != data)
-+				WREG32(mmCGTS_SM_CTRL_REG, data);
-+		}
- 		udelay(50);
- 
- 		/* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
-@@ -4406,13 +4416,13 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- }
- 
- static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
--		bool enable)
-+						  bool enable)
- {
- 	uint32_t temp, temp1, data, data1;
- 
- 	temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
- 
--	if (enable) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
- 		/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
- 		 * Cmp_busy/GFX_Idle interrupts
- 		 */
-@@ -4438,14 +4448,18 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- 		/* 5 - enable cgcg */
- 		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
- 
--		/* enable cgls*/
--		data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
-+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
-+			/* enable cgls*/
-+			data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
- 
--		temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
--		data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
-+			temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-+			data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
- 
--		if (temp1 != data1)
--			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
-+			if (temp1 != data1)
-+				WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
-+		} else {
-+			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
-+		}
- 
- 		if (temp != data)
- 			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
-@@ -4480,13 +4494,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- 
- 		/* disable cgcg, cgls should be disabled too. */
- 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
--				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
-+			  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
- 		if (temp != data)
- 			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
- 	}
- }
- static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
--		bool enable)
-+					bool enable)
- {
- 	if (enable) {
- 		/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 3964790..8d9b03f 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1076,7 +1076,14 @@ static int vi_common_early_init(void *handle)
- 		adev->external_rev_id = 0x1;
- 		break;
- 	case CHIP_FIJI:
--		adev->cg_flags = 0;
-+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			AMD_CG_SUPPORT_GFX_RLC_LS |
-+			AMD_CG_SUPPORT_GFX_CP_LS |
-+			AMD_CG_SUPPORT_GFX_CGTS |
-+			AMD_CG_SUPPORT_GFX_CGTS_LS |
-+			AMD_CG_SUPPORT_GFX_CGCG |
-+			AMD_CG_SUPPORT_GFX_CGLS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0490-drm-amdgpu-sdma-add-proper-CG-flags-for-fiji.patch b/common/recipes-kernel/linux/files/0490-drm-amdgpu-sdma-add-proper-CG-flags-for-fiji.patch
deleted file mode 100644
index c3b9abbe..00000000
--- a/common/recipes-kernel/linux/files/0490-drm-amdgpu-sdma-add-proper-CG-flags-for-fiji.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 051b94ccca43562f0ff3038f049906f3e5667060 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:42:51 -0400
-Subject: [PATCH 0490/1110] drm/amdgpu/sdma: add proper CG flags for fiji
-
-We were already enabling these CG features, this uses
-the standard interface for doing so.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/vi.c        | 4 +++-
- 2 files changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 0122624..8727f4a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1464,7 +1464,7 @@ static void fiji_update_sdma_medium_grain_clock_gating(
- {
- 	uint32_t temp, data;
- 
--	if (enable) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
- 		temp = data = RREG32(mmSDMA0_CLK_CTRL);
- 		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
- 				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-@@ -1524,7 +1524,7 @@ static void fiji_update_sdma_medium_grain_light_sleep(
- {
- 	uint32_t temp, data;
- 
--	if (enable) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
- 		temp = data = RREG32(mmSDMA0_POWER_CNTL);
- 		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 8d9b03f..5759504 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1083,7 +1083,9 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_GFX_CGTS |
- 			AMD_CG_SUPPORT_GFX_CGTS_LS |
- 			AMD_CG_SUPPORT_GFX_CGCG |
--			AMD_CG_SUPPORT_GFX_CGLS;
-+			AMD_CG_SUPPORT_GFX_CGLS |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch b/common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch
deleted file mode 100644
index e373d350..00000000
--- a/common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From bd0f234e6e86704d66c4719d7c1273a1feb01c6e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:52:58 -0400
-Subject: [PATCH 0491/1110] drm/amdgpu/common: add proper CG flags for fiji
-
-We were already enabling these CG features, this uses
-the standard interface for doing so.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 22 +++++++++++++---------
- 1 file changed, 13 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 5759504..ea9edf4 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1085,7 +1085,11 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_GFX_CGCG |
- 			AMD_CG_SUPPORT_GFX_CGLS |
- 			AMD_CG_SUPPORT_SDMA_MGCG |
--			AMD_CG_SUPPORT_SDMA_LS;
-+			AMD_CG_SUPPORT_SDMA_LS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_ROM_MGCG;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
-@@ -1188,13 +1192,13 @@ static int vi_common_soft_reset(void *handle)
- }
- 
- static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
--		bool enable)
-+						     bool enable)
- {
- 	uint32_t temp, data;
- 
- 	temp = data = RREG32_PCIE(ixPCIE_CNTL2);
- 
--	if (enable)
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
- 		data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
- 				PCIE_CNTL2__MST_MEM_LS_EN_MASK |
- 				PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
-@@ -1208,13 +1212,13 @@ static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
- }
- 
- static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
--		bool enable)
-+						      bool enable)
- {
- 	uint32_t temp, data;
- 
- 	temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
- 
--	if (enable)
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
- 		data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
- 	else
- 		data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
-@@ -1230,7 +1234,7 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
- 
- 	temp = data = RREG32(mmHDP_MEM_POWER_LS);
- 
--	if (enable)
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
- 		data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
- 	else
- 		data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
-@@ -1240,13 +1244,13 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
- }
- 
- static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
--		bool enable)
-+						      bool enable)
- {
- 	uint32_t temp, data;
- 
- 	temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
- 
--	if (enable)
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
- 		data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
- 				CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
- 	else
-@@ -1258,7 +1262,7 @@ static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev
- }
- 
- static int vi_common_set_clockgating_state(void *handle,
--					    enum amd_clockgating_state state)
-+					   enum amd_clockgating_state state)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0492-drm-amdgpu-gmc-add-proper-CG-flags-for-fiji.patch b/common/recipes-kernel/linux/files/0492-drm-amdgpu-gmc-add-proper-CG-flags-for-fiji.patch
deleted file mode 100644
index 520881d6..00000000
--- a/common/recipes-kernel/linux/files/0492-drm-amdgpu-gmc-add-proper-CG-flags-for-fiji.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 0d1a14aa1a603979cfa19b8e28822f53b5292133 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 01:01:18 -0400
-Subject: [PATCH 0492/1110] drm/amdgpu/gmc: add proper CG flags for fiji
-
-We were already enabling these CG features, this uses
-the standard interface for doing so.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ++++----
- drivers/gpu/drm/amd/amdgpu/vi.c       | 4 +++-
- 2 files changed, 7 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index bb254f1..9fbce45 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -1310,11 +1310,11 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
- }
- 
- static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
--		bool enable)
-+						     bool enable)
- {
- 	uint32_t data;
- 
--	if (enable) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
- 		data = RREG32(mmMC_HUB_MISC_HUB_CG);
- 		data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
- 		WREG32(mmMC_HUB_MISC_HUB_CG, data);
-@@ -1390,11 +1390,11 @@ static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
- }
- 
- static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
--		bool enable)
-+				       bool enable)
- {
- 	uint32_t data;
- 
--	if (enable) {
-+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
- 		data = RREG32(mmMC_HUB_MISC_HUB_CG);
- 		data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
- 		WREG32(mmMC_HUB_MISC_HUB_CG, data);
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index ea9edf4..16b2a29 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1089,7 +1089,9 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_BIF_LS |
- 			AMD_CG_SUPPORT_HDP_MGCG |
- 			AMD_CG_SUPPORT_HDP_LS |
--			AMD_CG_SUPPORT_ROM_MGCG;
-+			AMD_CG_SUPPORT_ROM_MGCG |
-+			AMD_CG_SUPPORT_MC_MGCG |
-+			AMD_CG_SUPPORT_MC_LS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x3c;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0493-drm-amdgpu-gfx8-rename-send_serdes_cmd.patch b/common/recipes-kernel/linux/files/0493-drm-amdgpu-gfx8-rename-send_serdes_cmd.patch
deleted file mode 100644
index 3cf8b4cb..00000000
--- a/common/recipes-kernel/linux/files/0493-drm-amdgpu-gfx8-rename-send_serdes_cmd.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 9507a7575899811848a36cde7ceb494c5af8f27d Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 01:12:20 -0400
-Subject: [PATCH 0493/1110] drm/amdgpu/gfx8: rename send_serdes_cmd
-
-So it can be shared with CZ/ST.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 48703cc..edd63e7 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4281,7 +4281,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
- 	return 0;
- }
- 
--static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
-+static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
- 				     uint32_t reg_addr, uint32_t cmd)
- {
- 	uint32_t data;
-@@ -4350,7 +4350,7 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 
- 		/* 5 - clear mgcg override */
--		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
-+		gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
- 
- 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
- 			/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
-@@ -4406,7 +4406,7 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 
- 		/* 6 - set mgcg override */
--		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
-+		gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
- 
- 		udelay(50);
- 
-@@ -4437,13 +4437,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 
- 		/* 3 - clear cgcg override */
--		fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
-+		gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
- 
- 		/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 
- 		/* 4 - write cmd to set CGLS */
--		fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
-+		gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
- 
- 		/* 5 - enable cgcg */
- 		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
-@@ -4484,13 +4484,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 
- 		/* write cmd to Set CGCG Overrride */
--		fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
-+		gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
- 
- 		/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 
- 		/* write cmd to Clear CGLS */
--		fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
-+		gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
- 
- 		/* disable cgcg, cgls should be disabled too. */
- 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch b/common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch
deleted file mode 100644
index 2e49f7d3..00000000
--- a/common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 136df7832570112848b7c6f406a7a95f85180d5b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 7 Apr 2016 23:16:00 -0400
-Subject: [PATCH 0494/1110] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for
- ST
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 +++++++++++++++++------
- 1 file changed, 17 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index edd63e7..14c75fe 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4292,7 +4292,8 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
- 	WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
- 
- 	data = RREG32(mmRLC_SERDES_WR_CTRL);
--	data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
-+	if (adev->asic_type == CHIP_STONEY)
-+			data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
- 			RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
- 			RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
- 			RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
-@@ -4300,13 +4301,23 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
- 			RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
- 			RLC_SERDES_WR_CTRL__POWER_UP_MASK |
- 			RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
--			RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
--			RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
- 			RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
-+	else
-+		data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
-+			  RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
-+			  RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
-+			  RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
-+			  RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
-+			  RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
-+			  RLC_SERDES_WR_CTRL__POWER_UP_MASK |
-+			  RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
-+			  RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
-+			  RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
-+			  RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
- 	data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
--			(cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
--			(reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
--			(0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
-+		 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
-+		 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
-+		 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
- 
- 	WREG32(mmRLC_SERDES_WR_CTRL, data);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0495-drm-amdgpu-add-a-new-set-of-rlc-function-pointers.patch b/common/recipes-kernel/linux/files/0495-drm-amdgpu-add-a-new-set-of-rlc-function-pointers.patch
deleted file mode 100644
index 0f802129..00000000
--- a/common/recipes-kernel/linux/files/0495-drm-amdgpu-add-a-new-set-of-rlc-function-pointers.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 5228644c5d40e413a13f3a471e4b5b1e3c382050 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 15:45:13 -0400
-Subject: [PATCH 0495/1110] drm/amdgpu: add a new set of rlc function pointers
-
-Different asics tend to have different ways to interact
-with the RLC.  This just covers enter/exit of safe mode
-for updating CG and PG state, but could be extended to
-cover other RLC operations in the future if necessary.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 47a3c8f..95ea8d7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1041,6 +1041,11 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
-  */
- #include "clearstate_defs.h"
- 
-+struct amdgpu_rlc_funcs {
-+	void (*enter_safe_mode)(struct amdgpu_device *adev);
-+	void (*exit_safe_mode)(struct amdgpu_device *adev);
-+};
-+
- struct amdgpu_rlc {
- 	/* for power gating */
- 	struct amdgpu_bo	*save_restore_obj;
-@@ -1059,6 +1064,10 @@ struct amdgpu_rlc {
- 	uint64_t		cp_table_gpu_addr;
- 	volatile uint32_t	*cp_table_ptr;
- 	u32                     cp_table_size;
-+
-+	/* safe mode for updating CG/PG state */
-+	bool in_safe_mode;
-+	const struct amdgpu_rlc_funcs *funcs;
- };
- 
- struct amdgpu_mec {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0496-drm-amdgpu-gfx-rework-fiji-cg-functions-so-they-can-.patch b/common/recipes-kernel/linux/files/0496-drm-amdgpu-gfx-rework-fiji-cg-functions-so-they-can-.patch
deleted file mode 100644
index 3405a01a..00000000
--- a/common/recipes-kernel/linux/files/0496-drm-amdgpu-gfx-rework-fiji-cg-functions-so-they-can-.patch
+++ /dev/null
@@ -1,315 +0,0 @@
-From 9a7ad545ad15335f2d61647cba82ec6bfe9fbcf4 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 7 Apr 2016 22:57:39 -0400
-Subject: [PATCH 0496/1110] drm/amdgpu/gfx: rework fiji cg functions so they
- can be shared
-
-They can be shared with other asics with minor modifications.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 218 +++++++++++++++++++++++++++++++---
- 1 file changed, 202 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 14c75fe..83ceafa 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -558,6 +558,7 @@ static const u32 stoney_mgcg_cgcg_init[] =
- static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
- static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
- static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
-+static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
- 
- static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
- {
-@@ -4250,6 +4251,7 @@ static int gfx_v8_0_early_init(void *handle)
- 	gfx_v8_0_set_ring_funcs(adev);
- 	gfx_v8_0_set_irq_funcs(adev);
- 	gfx_v8_0_set_gds_init(adev);
-+	gfx_v8_0_set_rlc_funcs(adev);
- 
- 	return 0;
- }
-@@ -4322,11 +4324,166 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
- 	WREG32(mmRLC_SERDES_WR_CTRL, data);
- }
- 
--static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
--						  bool enable)
-+#define MSG_ENTER_RLC_SAFE_MODE     1
-+#define MSG_EXIT_RLC_SAFE_MODE      0
-+
-+#define RLC_GPR_REG2__REQ_MASK           0x00000001
-+#define RLC_GPR_REG2__MESSAGE__SHIFT     0x00000001
-+#define RLC_GPR_REG2__MESSAGE_MASK       0x0000001e
-+
-+static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
-+{
-+	u32 data = 0;
-+	unsigned i;
-+
-+	data = RREG32(mmRLC_CNTL);
-+	if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
-+		return;
-+
-+	if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
-+	    (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
-+			       AMD_PG_SUPPORT_GFX_DMG))) {
-+		data |= RLC_GPR_REG2__REQ_MASK;
-+		data &= ~RLC_GPR_REG2__MESSAGE_MASK;
-+		data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
-+		WREG32(mmRLC_GPR_REG2, data);
-+
-+		for (i = 0; i < adev->usec_timeout; i++) {
-+			if ((RREG32(mmRLC_GPM_STAT) &
-+			     (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
-+			      RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
-+			    (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
-+			     RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
-+				break;
-+			udelay(1);
-+		}
-+
-+		for (i = 0; i < adev->usec_timeout; i++) {
-+			if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
-+				break;
-+			udelay(1);
-+		}
-+		adev->gfx.rlc.in_safe_mode = true;
-+	}
-+}
-+
-+static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)
-+{
-+	u32 data;
-+	unsigned i;
-+
-+	data = RREG32(mmRLC_CNTL);
-+	if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
-+		return;
-+
-+	if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
-+	    (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
-+			       AMD_PG_SUPPORT_GFX_DMG))) {
-+		data |= RLC_GPR_REG2__REQ_MASK;
-+		data &= ~RLC_GPR_REG2__MESSAGE_MASK;
-+		data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
-+		WREG32(mmRLC_GPR_REG2, data);
-+		adev->gfx.rlc.in_safe_mode = false;
-+	}
-+
-+	for (i = 0; i < adev->usec_timeout; i++) {
-+		if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
-+			break;
-+		udelay(1);
-+	}
-+}
-+
-+static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
-+{
-+	u32 data;
-+	unsigned i;
-+
-+	data = RREG32(mmRLC_CNTL);
-+	if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
-+		return;
-+
-+	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
-+		data |= RLC_SAFE_MODE__CMD_MASK;
-+		data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
-+		data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
-+		WREG32(mmRLC_SAFE_MODE, data);
-+
-+		for (i = 0; i < adev->usec_timeout; i++) {
-+			if ((RREG32(mmRLC_GPM_STAT) &
-+			     (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
-+			      RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
-+			    (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
-+			     RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
-+				break;
-+			udelay(1);
-+		}
-+
-+		for (i = 0; i < adev->usec_timeout; i++) {
-+			if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
-+				break;
-+			udelay(1);
-+		}
-+		adev->gfx.rlc.in_safe_mode = true;
-+	}
-+}
-+
-+static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
-+{
-+	u32 data = 0;
-+	unsigned i;
-+
-+	data = RREG32(mmRLC_CNTL);
-+	if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
-+		return;
-+
-+	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
-+		if (adev->gfx.rlc.in_safe_mode) {
-+			data |= RLC_SAFE_MODE__CMD_MASK;
-+			data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
-+			WREG32(mmRLC_SAFE_MODE, data);
-+			adev->gfx.rlc.in_safe_mode = false;
-+		}
-+	}
-+
-+	for (i = 0; i < adev->usec_timeout; i++) {
-+		if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
-+			break;
-+		udelay(1);
-+	}
-+}
-+
-+static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev)
-+{
-+	adev->gfx.rlc.in_safe_mode = true;
-+}
-+
-+static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev)
-+{
-+	adev->gfx.rlc.in_safe_mode = false;
-+}
-+
-+static const struct amdgpu_rlc_funcs cz_rlc_funcs = {
-+	.enter_safe_mode = cz_enter_rlc_safe_mode,
-+	.exit_safe_mode = cz_exit_rlc_safe_mode
-+};
-+
-+static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
-+	.enter_safe_mode = iceland_enter_rlc_safe_mode,
-+	.exit_safe_mode = iceland_exit_rlc_safe_mode
-+};
-+
-+static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = {
-+	.enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode,
-+	.exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode
-+};
-+
-+static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
-+						      bool enable)
- {
- 	uint32_t temp, data;
- 
-+	adev->gfx.rlc.funcs->enter_safe_mode(adev);
-+
- 	/* It is disabled by HW by default */
- 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
- 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
-@@ -4349,10 +4506,15 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- 
- 		/* 3 - RLC_CGTT_MGCG_OVERRIDE */
- 		temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
--		data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
--				RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
--				RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
--				RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
-+		if (adev->flags & AMD_IS_APU)
-+			data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
-+				  RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
-+				  RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
-+		else
-+			data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
-+				  RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
-+				  RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
-+				  RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
- 
- 		if (temp != data)
- 			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
-@@ -4424,15 +4586,19 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- 		/* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 	}
-+
-+	adev->gfx.rlc.funcs->exit_safe_mode(adev);
- }
- 
--static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
--						  bool enable)
-+static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
-+						      bool enable)
- {
- 	uint32_t temp, temp1, data, data1;
- 
- 	temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
- 
-+	adev->gfx.rlc.funcs->enter_safe_mode(adev);
-+
- 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
- 		/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
- 		 * Cmp_busy/GFX_Idle interrupts
-@@ -4509,22 +4675,24 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- 		if (temp != data)
- 			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
- 	}
-+
-+	adev->gfx.rlc.funcs->exit_safe_mode(adev);
- }
--static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
--					bool enable)
-+static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
-+					    bool enable)
- {
- 	if (enable) {
- 		/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
- 		 * ===  MGCG + MGLS + TS(CG/LS) ===
- 		 */
--		fiji_update_medium_grain_clock_gating(adev, enable);
--		fiji_update_coarse_grain_clock_gating(adev, enable);
-+		gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
-+		gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
- 	} else {
- 		/* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
- 		 * ===  CGCG + CGLS ===
- 		 */
--		fiji_update_coarse_grain_clock_gating(adev, enable);
--		fiji_update_medium_grain_clock_gating(adev, enable);
-+		gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
-+		gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
- 	}
- 	return 0;
- }
-@@ -4536,8 +4704,10 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
- 
- 	switch (adev->asic_type) {
- 	case CHIP_FIJI:
--		fiji_update_gfx_clock_gating(adev,
--				state == AMD_CG_STATE_GATE ? true : false);
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+		gfx_v8_0_update_gfx_clock_gating(adev,
-+						 state == AMD_CG_STATE_GATE ? true : false);
- 		break;
- 	default:
- 		break;
-@@ -5137,6 +5307,22 @@ static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
- 	adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
- }
- 
-+static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
-+{
-+	switch (adev->asic_type) {
-+	case CHIP_TOPAZ:
-+	case CHIP_STONEY:
-+		adev->gfx.rlc.funcs = &iceland_rlc_funcs;
-+		break;
-+	case CHIP_CARRIZO:
-+		adev->gfx.rlc.funcs = &cz_rlc_funcs;
-+		break;
-+	default:
-+		adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs;
-+		break;
-+	}
-+}
-+
- static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
- {
- 	/* init asci gds info */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0497-drm-amdgpu-enable-gfx-clockgating-for-CZ.patch b/common/recipes-kernel/linux/files/0497-drm-amdgpu-enable-gfx-clockgating-for-CZ.patch
deleted file mode 100644
index a223a934..00000000
--- a/common/recipes-kernel/linux/files/0497-drm-amdgpu-enable-gfx-clockgating-for-CZ.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From bfc952b49543ddf7f6875506bf521df8f4c882c5 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 7 Apr 2016 23:01:48 -0400
-Subject: [PATCH 0497/1110] drm/amdgpu: enable gfx clockgating for CZ
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 16b2a29..c9c88a5 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1101,7 +1101,15 @@ static int vi_common_early_init(void *handle)
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
- 	case CHIP_CARRIZO:
--		adev->cg_flags = 0;
-+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			AMD_CG_SUPPORT_GFX_RLC_LS |
-+			AMD_CG_SUPPORT_GFX_CP_LS |
-+			AMD_CG_SUPPORT_GFX_CGTS |
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			AMD_CG_SUPPORT_GFX_CGTS_LS |
-+			AMD_CG_SUPPORT_GFX_CGCG |
-+			AMD_CG_SUPPORT_GFX_CGLS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0498-drm-amdgpu-enable-gfx-clockgating-for-ST-v2.patch b/common/recipes-kernel/linux/files/0498-drm-amdgpu-enable-gfx-clockgating-for-ST-v2.patch
deleted file mode 100644
index 6525b541..00000000
--- a/common/recipes-kernel/linux/files/0498-drm-amdgpu-enable-gfx-clockgating-for-ST-v2.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 586e6c39b9086e335a7528dbff2ba314fdad7128 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 7 Apr 2016 23:17:15 -0400
-Subject: [PATCH 0498/1110] drm/amdgpu: enable gfx clockgating for ST (v2)
-
-v2: just enable MGCG for now since CGCG causes hangs
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index c9c88a5..2a7d37a 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1114,7 +1114,9 @@ static int vi_common_early_init(void *handle)
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
- 	case CHIP_STONEY:
--		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
-+		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGLS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0499-drm-amdgpu-vi-rename-fiji-cg-functions.patch b/common/recipes-kernel/linux/files/0499-drm-amdgpu-vi-rename-fiji-cg-functions.patch
deleted file mode 100644
index 72a647b1..00000000
--- a/common/recipes-kernel/linux/files/0499-drm-amdgpu-vi-rename-fiji-cg-functions.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From 4c3874fbf8eef34e046e38cbc7543c62d36197d9 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 01:37:44 -0400
-Subject: [PATCH 0499/1110] drm/amdgpu/vi: rename fiji cg functions
-
-They can be used for other VI parts.
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 33 +++++++++++++++++++++------------
- 1 file changed, 21 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 2a7d37a..7d03ea1 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1203,8 +1203,8 @@ static int vi_common_soft_reset(void *handle)
- 	return 0;
- }
- 
--static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
--						     bool enable)
-+static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
-+						   bool enable)
- {
- 	uint32_t temp, data;
- 
-@@ -1223,8 +1223,8 @@ static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
- 		WREG32_PCIE(ixPCIE_CNTL2, data);
- }
- 
--static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
--						      bool enable)
-+static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
-+						    bool enable)
- {
- 	uint32_t temp, data;
- 
-@@ -1239,8 +1239,8 @@ static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev
- 		WREG32(mmHDP_HOST_PATH_CNTL, data);
- }
- 
--static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
--		bool enable)
-+static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
-+				      bool enable)
- {
- 	uint32_t temp, data;
- 
-@@ -1255,8 +1255,8 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
- 		WREG32(mmHDP_MEM_POWER_LS, data);
- }
- 
--static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
--						      bool enable)
-+static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
-+						    bool enable)
- {
- 	uint32_t temp, data;
- 
-@@ -1280,13 +1280,22 @@ static int vi_common_set_clockgating_state(void *handle,
- 
- 	switch (adev->asic_type) {
- 	case CHIP_FIJI:
--		fiji_update_bif_medium_grain_light_sleep(adev,
-+		vi_update_bif_medium_grain_light_sleep(adev,
- 				state == AMD_CG_STATE_GATE ? true : false);
--		fiji_update_hdp_medium_grain_clock_gating(adev,
-+		vi_update_hdp_medium_grain_clock_gating(adev,
- 				state == AMD_CG_STATE_GATE ? true : false);
--		fiji_update_hdp_light_sleep(adev,
-+		vi_update_hdp_light_sleep(adev,
- 				state == AMD_CG_STATE_GATE ? true : false);
--		fiji_update_rom_medium_grain_clock_gating(adev,
-+		vi_update_rom_medium_grain_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		break;
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+		vi_update_bif_medium_grain_light_sleep(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		vi_update_hdp_medium_grain_clock_gating(adev,
-+				state == AMD_CG_STATE_GATE ? true : false);
-+		vi_update_hdp_light_sleep(adev,
- 				state == AMD_CG_STATE_GATE ? true : false);
- 		break;
- 	default:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0500-drm-amdgpu-enable-gmc-clockgating-for-CZ.patch b/common/recipes-kernel/linux/files/0500-drm-amdgpu-enable-gmc-clockgating-for-CZ.patch
deleted file mode 100644
index f93d2142..00000000
--- a/common/recipes-kernel/linux/files/0500-drm-amdgpu-enable-gmc-clockgating-for-CZ.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e89ef34b5d75a5000f5ad3b13251144c0eba8291 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:26:46 -0400
-Subject: [PATCH 0500/1110] drm/amdgpu: enable gmc clockgating for CZ
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 7d03ea1..0e9d382 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1109,7 +1109,10 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_GFX_MGLS |
- 			AMD_CG_SUPPORT_GFX_CGTS_LS |
- 			AMD_CG_SUPPORT_GFX_CGCG |
--			AMD_CG_SUPPORT_GFX_CGLS;
-+			AMD_CG_SUPPORT_GFX_CGLS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0501-drm-amdgpu-enable-gmc-clockgating-for-ST.patch b/common/recipes-kernel/linux/files/0501-drm-amdgpu-enable-gmc-clockgating-for-ST.patch
deleted file mode 100644
index e52624b9..00000000
--- a/common/recipes-kernel/linux/files/0501-drm-amdgpu-enable-gmc-clockgating-for-ST.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e5fca385bafbc0ece13c81cfedad156c30858d85 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 13 Apr 2016 12:41:50 -0400
-Subject: [PATCH 0501/1110] drm/amdgpu: enable gmc clockgating for ST
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 0e9d382..a330d70 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1119,7 +1119,10 @@ static int vi_common_early_init(void *handle)
- 	case CHIP_STONEY:
- 		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
- 			AMD_CG_SUPPORT_GFX_MGCG |
--			AMD_CG_SUPPORT_GFX_MGLS;
-+			AMD_CG_SUPPORT_GFX_MGLS |
-+			AMD_CG_SUPPORT_BIF_LS |
-+			AMD_CG_SUPPORT_HDP_MGCG |
-+			AMD_CG_SUPPORT_HDP_LS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0502-drm-amdgpu-sdma-rename-fiji-cg-functions.patch b/common/recipes-kernel/linux/files/0502-drm-amdgpu-sdma-rename-fiji-cg-functions.patch
deleted file mode 100644
index d3205d8c..00000000
--- a/common/recipes-kernel/linux/files/0502-drm-amdgpu-sdma-rename-fiji-cg-functions.patch
+++ /dev/null
@@ -1,165 +0,0 @@
-From a85230e4364ad6a1156ad5967b7ef1c68fe29326 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:19:39 -0400
-Subject: [PATCH 0502/1110] drm/amdgpu/sdma: rename fiji cg functions
-
-They care common for all sdma 3.0 parts
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 104 +++++++++++++--------------------
- 1 file changed, 39 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 8727f4a..368a46b 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1458,40 +1458,31 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
- 	return 0;
- }
- 
--static void fiji_update_sdma_medium_grain_clock_gating(
-+static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
- 		struct amdgpu_device *adev,
- 		bool enable)
- {
- 	uint32_t temp, data;
-+	int i;
- 
- 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
--		temp = data = RREG32(mmSDMA0_CLK_CTRL);
--		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
--				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
--		if (data != temp)
--			WREG32(mmSDMA0_CLK_CTRL, data);
--
--		temp = data = RREG32(mmSDMA1_CLK_CTRL);
--		data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
--
--		if (data != temp)
--			WREG32(mmSDMA1_CLK_CTRL, data);
-+		for (i = 0; i < adev->sdma.num_instances; i++) {
-+			temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
-+			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
-+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
-+			if (data != temp)
-+				WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
-+		}
- 	} else {
--		temp = data = RREG32(mmSDMA0_CLK_CTRL);
--		data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
-+		for (i = 0; i < adev->sdma.num_instances; i++) {
-+			temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
-+			data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
- 				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
- 				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
- 				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
-@@ -1500,54 +1491,35 @@ static void fiji_update_sdma_medium_grain_clock_gating(
- 				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
- 				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
- 
--		if (data != temp)
--			WREG32(mmSDMA0_CLK_CTRL, data);
--
--		temp = data = RREG32(mmSDMA1_CLK_CTRL);
--		data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
--				SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK;
--
--		if (data != temp)
--			WREG32(mmSDMA1_CLK_CTRL, data);
-+			if (data != temp)
-+				WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
-+		}
- 	}
- }
- 
--static void fiji_update_sdma_medium_grain_light_sleep(
-+static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
- 		struct amdgpu_device *adev,
- 		bool enable)
- {
- 	uint32_t temp, data;
-+	int i;
- 
- 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
--		temp = data = RREG32(mmSDMA0_POWER_CNTL);
--		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
--
--		if (temp != data)
--			WREG32(mmSDMA0_POWER_CNTL, data);
--
--		temp = data = RREG32(mmSDMA1_POWER_CNTL);
--		data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-+		for (i = 0; i < adev->sdma.num_instances; i++) {
-+			temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
-+			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
- 
--		if (temp != data)
--			WREG32(mmSDMA1_POWER_CNTL, data);
-+			if (temp != data)
-+				WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
-+		}
- 	} else {
--		temp = data = RREG32(mmSDMA0_POWER_CNTL);
--		data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
--
--		if (temp != data)
--			WREG32(mmSDMA0_POWER_CNTL, data);
--
--		temp = data = RREG32(mmSDMA1_POWER_CNTL);
--		data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-+		for (i = 0; i < adev->sdma.num_instances; i++) {
-+			temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
-+			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
- 
--		if (temp != data)
--			WREG32(mmSDMA1_POWER_CNTL, data);
-+			if (temp != data)
-+				WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
-+		}
- 	}
- }
- 
-@@ -1558,9 +1530,11 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
- 
- 	switch (adev->asic_type) {
- 	case CHIP_FIJI:
--		fiji_update_sdma_medium_grain_clock_gating(adev,
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+		sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
- 				state == AMD_CG_STATE_GATE ? true : false);
--		fiji_update_sdma_medium_grain_light_sleep(adev,
-+		sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
- 				state == AMD_CG_STATE_GATE ? true : false);
- 		break;
- 	default:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0503-drm-amdgpu-enable-sdma-clockgating-on-CZ.patch b/common/recipes-kernel/linux/files/0503-drm-amdgpu-enable-sdma-clockgating-on-CZ.patch
deleted file mode 100644
index 9f331381..00000000
--- a/common/recipes-kernel/linux/files/0503-drm-amdgpu-enable-sdma-clockgating-on-CZ.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From fb212b8332ea5cc710f384b31bdf62abbccb650f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:39:54 -0400
-Subject: [PATCH 0503/1110] drm/amdgpu: enable sdma clockgating on CZ
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index a330d70..83f890a 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1112,7 +1112,9 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_GFX_CGLS |
- 			AMD_CG_SUPPORT_BIF_LS |
- 			AMD_CG_SUPPORT_HDP_MGCG |
--			AMD_CG_SUPPORT_HDP_LS;
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0504-drm-amdgpu-enable-sdma-clockgating-on-ST.patch b/common/recipes-kernel/linux/files/0504-drm-amdgpu-enable-sdma-clockgating-on-ST.patch
deleted file mode 100644
index 4a3c49d0..00000000
--- a/common/recipes-kernel/linux/files/0504-drm-amdgpu-enable-sdma-clockgating-on-ST.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 7ad16afcb7b7f2c9884b37f27199437d842d66e3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Apr 2016 00:40:49 -0400
-Subject: [PATCH 0504/1110] drm/amdgpu: enable sdma clockgating on ST
-
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 83f890a..ddbb63a 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1124,7 +1124,9 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_GFX_MGLS |
- 			AMD_CG_SUPPORT_BIF_LS |
- 			AMD_CG_SUPPORT_HDP_MGCG |
--			AMD_CG_SUPPORT_HDP_LS;
-+			AMD_CG_SUPPORT_HDP_LS |
-+			AMD_CG_SUPPORT_SDMA_MGCG |
-+			AMD_CG_SUPPORT_SDMA_LS;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0505-drm-amdgpu-double-fence-slot.patch b/common/recipes-kernel/linux/files/0505-drm-amdgpu-double-fence-slot.patch
deleted file mode 100644
index 2b550c41..00000000
--- a/common/recipes-kernel/linux/files/0505-drm-amdgpu-double-fence-slot.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From b45931bb92fb4841a60e7bee9532df4c01d71c50 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 14 Apr 2016 10:27:28 +0800
-Subject: [PATCH 0505/1110] drm/amdgpu: double fence slot
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-we introduced vmid fence, so one hw submission could produce two fences.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 100f4c6..50e95ab 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -352,9 +352,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
- 	setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
- 		    (unsigned long)ring);
- 
--	ring->fence_drv.num_fences_mask = num_hw_submission - 1;
-+	ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
- 	spin_lock_init(&ring->fence_drv.lock);
--	ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *),
-+	ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
- 					 GFP_KERNEL);
- 	if (!ring->fence_drv.fences)
- 		return -ENOMEM;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0506-drm-amdgpu-only-update-last_flush-when-vmid-doesn-t-.patch b/common/recipes-kernel/linux/files/0506-drm-amdgpu-only-update-last_flush-when-vmid-doesn-t-.patch
deleted file mode 100644
index 00cb2f9c..00000000
--- a/common/recipes-kernel/linux/files/0506-drm-amdgpu-only-update-last_flush-when-vmid-doesn-t-.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 38cc13ce129ab201aa74dc39edf5f46d43635bf3 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 14 Apr 2016 13:42:32 +0800
-Subject: [PATCH 0506/1110] drm/amdgpu: only update last_flush when vmid
- doesn't have other new owner
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 ++++++++++-----
- 2 files changed, 11 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 95ea8d7..0214003 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -880,6 +880,7 @@ struct amdgpu_vm_id {
-         struct fence            *first;
-         struct amdgpu_sync      active;
-         struct fence            *last_flush;
-+        struct amdgpu_ring      *last_user;
- 	atomic_long_t		owner;
- 
-         uint64_t                pd_gpu_addr;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 9444cbe..4a896d7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -267,6 +267,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 	id->pd_gpu_addr = pd_addr;
- 
- 	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-+	id->last_user = ring;
- 	atomic_long_set(&id->owner, (long)vm);
- 	vm->ids[ring->idx] = id;
- 
-@@ -314,13 +315,17 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
- 
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
- 		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
--                r = amdgpu_fence_emit(ring, &fence);
--                if (r)
--                        return r;
-  
-                 mutex_lock(&adev->vm_manager.lock);
--                fence_put(id->last_flush);
--                id->last_flush = fence;
-+                if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) {
-+                        r = amdgpu_fence_emit(ring, &fence);
-+                        if (r) {
-+                                mutex_unlock(&adev->vm_manager.lock);
-+                                return r;
-+                        }
-+                        fence_put(id->last_flush);
-+                        id->last_flush = fence;
-+                }
-                 mutex_unlock(&adev->vm_manager.lock);
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0507-drm-amdgpu-fix-error-checking-when-reuse-vmid-on-sam.patch b/common/recipes-kernel/linux/files/0507-drm-amdgpu-fix-error-checking-when-reuse-vmid-on-sam.patch
deleted file mode 100644
index 2b4f3d49..00000000
--- a/common/recipes-kernel/linux/files/0507-drm-amdgpu-fix-error-checking-when-reuse-vmid-on-sam.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 1da67dcc1d2a4d088e525d01c6c1489d148b9539 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 14 Apr 2016 15:53:55 +0800
-Subject: [PATCH 0507/1110] drm/amdgpu: fix error checking when reuse vmid on
- same ring
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 4a896d7..4f16688 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -198,7 +198,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		if (pd_addr != id->pd_gpu_addr)
- 			continue;
- 
--		if (id != vm->ids[ring->idx] &&
-+		if (id->last_user != ring &&
- 		    (!id->last_flush || !fence_is_signaled(id->last_flush)))
- 			continue;
- 
-@@ -207,7 +207,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 			continue;
- 
- 		/* Good we can use this VMID */
--		if (id == vm->ids[ring->idx]) {
-+		if (id->last_user == ring) {
- 			r = amdgpu_sync_fence(ring->adev, sync,
- 					      id->first);
- 			if (r)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0508-drm-amdgpu-group-BOs-by-log2-of-the-size-on-the-LRU-.patch b/common/recipes-kernel/linux/files/0508-drm-amdgpu-group-BOs-by-log2-of-the-size-on-the-LRU-.patch
deleted file mode 100644
index 3ef61152..00000000
--- a/common/recipes-kernel/linux/files/0508-drm-amdgpu-group-BOs-by-log2-of-the-size-on-the-LRU-.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From 9cc9a4472afca6cc46f79dfafe53787a200c6121 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 15 Apr 2016 17:19:16 +0200
-Subject: [PATCH 0508/1110] drm/amdgpu: group BOs by log2 of the size on the
- LRU v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows us to have small BOs on the LRU before big ones.
-
-v2: fix of by one and list corruption bug
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 11 ++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 61 +++++++++++++++++++++++++++++++--
- 2 files changed, 70 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0214003..06cf1eb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -393,6 +393,14 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
- /*
-  * TTM.
-  */
-+
-+#define AMDGPU_TTM_LRU_SIZE	20
-+
-+struct amdgpu_mman_lru {
-+	struct list_head		*lru[TTM_NUM_MEM_TYPES];
-+	struct list_head		*swap_lru;
-+};
-+
- struct amdgpu_mman {
- 	struct ttm_bo_global_ref        bo_global_ref;
- 	struct drm_global_reference	mem_global_ref;
-@@ -410,6 +418,9 @@ struct amdgpu_mman {
- 	struct amdgpu_ring			*buffer_funcs_ring;
-         /* Scheduler entity for buffer moves */
-         struct amd_sched_entity                 entity;
-+
-+        /* custom LRU management */
-+        struct amdgpu_mman_lru                  log2_size[AMDGPU_TTM_LRU_SIZE];
- };
- 
- int amdgpu_copy_buffer(struct amdgpu_ring *ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 1ec9491..70f005d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -910,6 +910,52 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
- 	return flags;
- }
- 
-+static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
-+{
-+	struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
-+	unsigned i, j;
-+
-+	for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
-+		struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
-+
-+		for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
-+			if (&tbo->lru == lru->lru[j])
-+				lru->lru[j] = tbo->lru.prev;
-+
-+		if (&tbo->swap == lru->swap_lru)
-+			lru->swap_lru = tbo->swap.prev;
-+	}
-+}
-+
-+static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
-+{
-+	struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
-+	unsigned log2_size = min(ilog2(tbo->num_pages),
-+				 AMDGPU_TTM_LRU_SIZE - 1);
-+
-+	return &adev->mman.log2_size[log2_size];
-+}
-+
-+static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
-+{
-+	struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
-+	struct list_head *res = lru->lru[tbo->mem.mem_type];
-+
-+	lru->lru[tbo->mem.mem_type] = &tbo->lru;
-+
-+	return res;
-+}
-+
-+static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
-+{
-+	struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
-+	struct list_head *res = lru->swap_lru;
-+
-+	lru->swap_lru = &tbo->swap;
-+
-+	return res;
-+}
-+
- static struct ttm_bo_driver amdgpu_bo_driver = {
- 	.ttm_tt_create = &amdgpu_ttm_tt_create,
- 	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
-@@ -923,12 +969,14 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
- 	.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
- 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
- 	.io_mem_free = &amdgpu_ttm_io_mem_free,
--	.lru_tail = &ttm_bo_default_lru_tail,
--	.swap_lru_tail = &ttm_bo_default_swap_lru_tail,
-+	.lru_removal = &amdgpu_ttm_lru_removal,
-+	.lru_tail = &amdgpu_ttm_lru_tail,
-+	.swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
- };
- 
- int amdgpu_ttm_init(struct amdgpu_device *adev)
- {
-+	unsigned i, j;
- 	int r;
- 
- 	r = amdgpu_ttm_global_init(adev);
-@@ -946,6 +994,15 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
- 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
- 		return r;
- 	}
-+
-+	for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
-+		struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
-+
-+		for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
-+			lru->lru[j] = &adev->mman.bdev.man[j].lru;
-+		lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
-+	}
-+
- 	adev->mman.initialized = true;
- 	r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
- 				adev->mc.real_vram_size >> PAGE_SHIFT);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0509-drm-amdgpu-remove-sorting-of-CS-BOs.patch b/common/recipes-kernel/linux/files/0509-drm-amdgpu-remove-sorting-of-CS-BOs.patch
deleted file mode 100644
index d69aa04e..00000000
--- a/common/recipes-kernel/linux/files/0509-drm-amdgpu-remove-sorting-of-CS-BOs.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From cff6c9a7f64f13fbe5c6bfc09e9aaac3058e997a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 15 Apr 2016 17:19:17 +0200
-Subject: [PATCH 0509/1110] drm/amdgpu: remove sorting of CS BOs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Not needed any more.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 +----------------------
- 1 file changed, 1 insertion(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 807670c..55a5814 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -24,7 +24,6 @@
-  * Authors:
-  *    Jerome Glisse <glisse@freedesktop.org>
-  */
--#include <linux/list_sort.h>
- #include <linux/pagemap.h>
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
-@@ -574,16 +573,6 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
- 	return 0;
- }
- 
--static int cmp_size_smaller_first(void *priv, struct list_head *a,
--				  struct list_head *b)
--{
--	struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
--	struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
--
--	/* Sort A before B if A is smaller. */
--	return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
--}
--
- /**
-  * cs_parser_fini() - clean parser states
-  * @parser:	parser structure holding parsing context.
-@@ -597,17 +586,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
- 	unsigned i;
- 
- 	if (!error) {
--		/* Sort the buffer list from the smallest to largest buffer,
--		 * which affects the order of buffers in the LRU list.
--		 * This assures that the smallest buffers are added first
--		 * to the LRU list, so they are likely to be later evicted
--		 * first, instead of large buffers whose eviction is more
--		 * expensive.
--		 *
--		 * This slightly lowers the number of bytes moved by TTM
--		 * per frame under memory pressure.
--		 */
--		list_sort(NULL, &parser->validated, cmp_size_smaller_first);
-+		amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
- 
- 		ttm_eu_fence_buffer_objects(&parser->ticket,
- 					    &parser->validated,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch b/common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch
deleted file mode 100644
index 1606a1aa..00000000
--- a/common/recipes-kernel/linux/files/0510-drm-amd-dal-Add-dal-display-driver.patch
+++ /dev/null
@@ -1,90113 +0,0 @@
-From 35eea4f1b20ded08fc0d65891163d03238e3adf6 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 25 Nov 2015 14:45:50 -0500
-Subject: [PATCH 0510/1110] drm/amd/dal: Add dal display driver
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/Kconfig                    |   39 +
- drivers/gpu/drm/amd/dal/Makefile                   |   19 +
- .../gpu/drm/amd/dal/dal_power_interface_types.h    |   76 +
- drivers/gpu/drm/amd/dal/dal_services.h             |  266 ++
- drivers/gpu/drm/amd/dal/dal_services_types.h       |   62 +
- drivers/gpu/drm/amd/dal/dc/Makefile                |   24 +
- drivers/gpu/drm/amd/dal/dc/adapter/Makefile        |   18 +
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   | 2037 +++++++++
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h   |   67 +
- .../adapter/dce110/hw_ctx_adapter_service_dce110.c |  303 ++
- .../adapter/dce110/hw_ctx_adapter_service_dce110.h |   40 +
- .../amd/dal/dc/adapter/hw_ctx_adapter_service.c    |  164 +
- .../amd/dal/dc/adapter/hw_ctx_adapter_service.h    |   86 +
- .../drm/amd/dal/dc/adapter/wireless_data_source.c  |  209 +
- .../drm/amd/dal/dc/adapter/wireless_data_source.h  |   80 +
- .../gpu/drm/amd/dal/dc/asic_capability/Makefile    |   23 +
- .../amd/dal/dc/asic_capability/asic_capability.c   |  178 +
- .../dc/asic_capability/carrizo_asic_capability.c   |  146 +
- .../dc/asic_capability/carrizo_asic_capability.h   |   36 +
- drivers/gpu/drm/amd/dal/dc/audio/Makefile          |   22 +
- drivers/gpu/drm/amd/dal/dc/audio/audio.h           |  195 +
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |  463 ++
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c |  452 ++
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h |   42 +
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c  | 1929 ++++++++
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h  |   47 +
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c    |  771 ++++
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h    |  285 ++
- drivers/gpu/drm/amd/dal/dc/basics/Makefile         |   10 +
- drivers/gpu/drm/amd/dal/dc/basics/conversion.c     |  223 +
- drivers/gpu/drm/amd/dal/dc/basics/conversion.h     |   49 +
- drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c     |  692 +++
- drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c     |  223 +
- drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c |  135 +
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         |  947 ++++
- drivers/gpu/drm/amd/dal/dc/basics/logger.h         |   64 +
- .../gpu/drm/amd/dal/dc/basics/register_logger.c    |  197 +
- drivers/gpu/drm/amd/dal/dc/basics/signal_types.c   |  116 +
- drivers/gpu/drm/amd/dal/dc/basics/vector.c         |  309 ++
- drivers/gpu/drm/amd/dal/dc/bios/Makefile           |   27 +
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 4758 ++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h      |   78 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |  193 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |  108 +
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    | 2616 +++++++++++
- drivers/gpu/drm/amd/dal/dc/bios/command_table.h    |  117 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |  315 ++
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |   87 +
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c |  484 ++
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.h |   34 +
- .../dc/bios/dce110/command_table_helper_dce110.c   |  369 ++
- .../dc/bios/dce110/command_table_helper_dce110.h   |   34 +
- drivers/gpu/drm/amd/dal/dc/calcs/Makefile          |   10 +
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 3478 ++++++++++++++
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        |  278 ++
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c   | 1992 ++++++++
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h   |   74 +
- drivers/gpu/drm/amd/dal/dc/connector/Makefile      |   10 +
- drivers/gpu/drm/amd/dal/dc/connector/connector.h   |   39 +
- .../gpu/drm/amd/dal/dc/connector/connector_base.c  |  421 ++
- .../drm/amd/dal/dc/connector/connector_signals.c   |  204 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  849 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |   49 +
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 1081 +++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 1689 +++++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  188 +
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  378 ++
- drivers/gpu/drm/amd/dal/dc/core/dc_sink.c          |  118 +
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |  172 +
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |  124 +
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  473 ++
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  440 ++
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |   75 +
- drivers/gpu/drm/amd/dal/dc/dc_services.h           |  174 +
- drivers/gpu/drm/amd/dal/dc/dc_temp.h               |  508 +++
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  677 +++
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |   33 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c  |  886 ++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h  |   84 +
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 1825 ++++++++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h    |   36 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     |   85 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     |   90 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c  |  256 ++
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   |  877 ++++
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 2049 +++++++++
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |   91 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  969 ++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |   88 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  296 ++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |  140 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c |  904 ++++
- .../drm/amd/dal/dc/dce110/dce110_opp_formatter.c   |  610 +++
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 2473 ++++++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 1276 ++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.h    |   55 +
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 1168 +++++
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |   64 +
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 1878 ++++++++
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |  178 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   |  116 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |   91 +
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c |  840 ++++
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.h |   51 +
- .../drm/amd/dal/dc/dce110/dce110_transform_gamut.c |  297 ++
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c   |  818 ++++
- .../drm/amd/dal/dc/dce110/dce110_transform_sclv.c  |  531 +++
- drivers/gpu/drm/amd/dal/dc/dcs/Makefile            |   10 +
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c |  159 +
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h |   60 +
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c       | 1034 +++++
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h       |   38 +
- drivers/gpu/drm/amd/dal/dc/gpio/Makefile           |   24 +
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c |  883 ++++
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h |   46 +
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c |   84 +
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h |   32 +
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c |  367 ++
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h |   47 +
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c   |  440 ++
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.h   |   34 +
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.c              |  290 ++
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.h              |   45 +
- drivers/gpu/drm/amd/dal/dc/gpio/dvo.c              |  138 +
- drivers/gpu/drm/amd/dal/dc/gpio/dvo.h              |   42 +
- drivers/gpu/drm/amd/dal/dc/gpio/gpio.h             |   48 +
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c        |  279 ++
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     |  470 ++
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h     |   57 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c           |  105 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h           |   60 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c           |  318 ++
- drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h           |   89 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |   80 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h       |   74 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c          |  408 ++
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h          |  129 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c      |   93 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h      |   47 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c      |   86 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h      |   79 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c           |   88 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h           |   45 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |   67 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h     |   49 +
- drivers/gpu/drm/amd/dal/dc/gpio/irq.c              |  181 +
- drivers/gpu/drm/amd/dal/dc/gpio/irq.h              |   42 +
- drivers/gpu/drm/amd/dal/dc/gpu/Makefile            |   26 +
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c |  407 ++
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h |   79 +
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c      |  649 +++
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h      |  136 +
- .../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c    |   92 +
- .../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h    |   63 +
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c |   90 +
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h |   33 +
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |  958 ++++
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.h   |   53 +
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.c    |  383 ++
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.h    |   38 +
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.c    |  718 +++
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.h    |   55 +
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.c    |  193 +
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.h    |   32 +
- drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c     |  204 +
- drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h     |   82 +
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c     |  127 +
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h     |   63 +
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c  |  119 +
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h  |   47 +
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c  |  141 +
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h  |   52 +
- drivers/gpu/drm/amd/dal/dc/i2caux/Makefile         |   23 +
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c     |  568 +++
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h     |  119 +
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c   |  789 ++++
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.h   |   56 +
- .../i2caux/dce110/i2c_generic_hw_engine_dce110.h   |   25 +
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c    |  954 ++++
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h    |   58 +
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c    |  172 +
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h    |   43 +
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c   |  260 ++
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h   |   39 +
- drivers/gpu/drm/amd/dal/dc/i2caux/engine.h         |  129 +
- drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c    |   68 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c     |  122 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h     |  113 +
- .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c  |  287 ++
- .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h  |   77 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c  |  247 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h  |   80 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c  |  615 +++
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h  |   81 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |  519 +++
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h         |  123 +
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  463 ++
- drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h          |   60 +
- drivers/gpu/drm/amd/dal/dc/inc/compressor.h        |  140 +
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |   39 +
- drivers/gpu/drm/amd/dal/dc/inc/core_status.h       |   46 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  308 ++
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h        |   51 +
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  170 +
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |   66 +
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h         |   67 +
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |   55 +
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               |  206 +
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |   61 +
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |   81 +
- drivers/gpu/drm/amd/dal/dc/irq/Makefile            |   21 +
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c |  389 ++
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.h |   34 +
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |  173 +
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.h       |   85 +
- drivers/gpu/drm/amd/dal/dc/irq_types.h             |  199 +
- .../amd/dal/include/adapter_service_interface.h    |  628 +++
- .../drm/amd/dal/include/adapter_service_types.h    |   70 +
- .../gpu/drm/amd/dal/include/adjustment_interface.h |  230 +
- drivers/gpu/drm/amd/dal/include/adjustment_types.h |  420 ++
- .../amd/dal/include/asic_capability_interface.h    |   58 +
- .../drm/amd/dal/include/asic_capability_types.h    |  134 +
- drivers/gpu/drm/amd/dal/include/audio_interface.h  |  184 +
- drivers/gpu/drm/amd/dal/include/audio_types.h      |  275 ++
- .../drm/amd/dal/include/bios_parser_interface.h    |  294 ++
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |  305 ++
- drivers/gpu/drm/amd/dal/include/bit_set.h          |   61 +
- .../drm/amd/dal/include/clock_source_interface.h   |   89 +
- .../gpu/drm/amd/dal/include/clock_source_types.h   |  118 +
- .../gpu/drm/amd/dal/include/connector_interface.h  |   82 +
- drivers/gpu/drm/amd/dal/include/dal_asic_id.h      |  106 +
- .../gpu/drm/amd/dal/include/dal_register_logger.h  |   43 +
- drivers/gpu/drm/amd/dal/include/dal_types.h        |  292 ++
- .../amd/dal/include/dc_clock_generator_interface.h |   77 +
- drivers/gpu/drm/amd/dal/include/dcs_interface.h    |  351 ++
- drivers/gpu/drm/amd/dal/include/dcs_types.h        |  742 +++
- drivers/gpu/drm/amd/dal/include/ddc_interface.h    |   74 +
- .../drm/amd/dal/include/ddc_service_interface.h    |  100 +
- .../gpu/drm/amd/dal/include/ddc_service_types.h    |  220 +
- .../amd/dal/include/default_mode_list_interface.h  |   37 +
- .../drm/amd/dal/include/display_clock_interface.h  |  189 +
- .../drm/amd/dal/include/display_path_interface.h   |  436 ++
- .../gpu/drm/amd/dal/include/display_path_types.h   |  132 +
- .../amd/dal/include/display_service_interface.h    |  165 +
- .../drm/amd/dal/include/display_service_types.h    |  167 +
- drivers/gpu/drm/amd/dal/include/dmcu_interface.h   |   87 +
- drivers/gpu/drm/amd/dal/include/dmcu_types.h       |  199 +
- .../dal/include/dpcd_access_service_interface.h    |   65 +
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h        |  869 ++++
- drivers/gpu/drm/amd/dal/include/dvo_interface.h    |   48 +
- .../gpu/drm/amd/dal/include/encoder_interface.h    |  278 ++
- drivers/gpu/drm/amd/dal/include/encoder_types.h    |  216 +
- drivers/gpu/drm/amd/dal/include/fixed31_32.h       |  389 ++
- drivers/gpu/drm/amd/dal/include/fixed32_32.h       |   80 +
- drivers/gpu/drm/amd/dal/include/gpio_interface.h   |   93 +
- .../drm/amd/dal/include/gpio_service_interface.h   |   94 +
- drivers/gpu/drm/amd/dal/include/gpio_types.h       |  393 ++
- drivers/gpu/drm/amd/dal/include/gpu_clock_info.h   |   43 +
- drivers/gpu/drm/amd/dal/include/gpu_interface.h    |   91 +
- drivers/gpu/drm/amd/dal/include/grph_csc_types.h   |   98 +
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    |  598 +++
- drivers/gpu/drm/amd/dal/include/grph_object_defs.h |  328 ++
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   |  285 ++
- .../gpu/drm/amd/dal/include/hw_adjustment_set.h    |   50 +
- .../gpu/drm/amd/dal/include/hw_adjustment_types.h  |  205 +
- .../amd/dal/include/hw_path_mode_set_interface.h   |   48 +
- .../drm/amd/dal/include/hw_sequencer_interface.h   |  388 ++
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |  305 ++
- drivers/gpu/drm/amd/dal/include/i2caux_interface.h |  127 +
- drivers/gpu/drm/amd/dal/include/irq_interface.h    |   53 +
- .../drm/amd/dal/include/irq_service_interface.h    |   55 +
- drivers/gpu/drm/amd/dal/include/isr_config_types.h |  157 +
- .../gpu/drm/amd/dal/include/link_encoder_types.h   |   32 +
- .../drm/amd/dal/include/link_service_interface.h   |  202 +
- .../gpu/drm/amd/dal/include/link_service_types.h   |  428 ++
- drivers/gpu/drm/amd/dal/include/logger_interface.h |  153 +
- drivers/gpu/drm/amd/dal/include/logger_types.h     |  356 ++
- .../gpu/drm/amd/dal/include/mode_manager_types.h   |   71 +
- .../gpu/drm/amd/dal/include/mode_query_interface.h |   93 +
- .../amd/dal/include/mode_timing_list_interface.h   |   51 +
- .../gpu/drm/amd/dal/include/overlay_interface.h    |  137 +
- drivers/gpu/drm/amd/dal/include/overlay_types.h    |  164 +
- .../drm/amd/dal/include/path_mode_set_interface.h  |  107 +
- drivers/gpu/drm/amd/dal/include/plane_types.h      |  309 ++
- drivers/gpu/drm/amd/dal/include/scaler_types.h     |  196 +
- .../amd/dal/include/set_mode_params_interface.h    |  101 +
- drivers/gpu/drm/amd/dal/include/set_mode_types.h   |  285 ++
- drivers/gpu/drm/amd/dal/include/signal_types.h     |   58 +
- .../gpu/drm/amd/dal/include/stream_encoder_types.h |   16 +
- .../drm/amd/dal/include/timing_generator_types.h   |  150 +
- .../amd/dal/include/timing_list_query_interface.h  |   69 +
- drivers/gpu/drm/amd/dal/include/vector.h           |  150 +
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  |  135 +
- .../gpu/drm/amd/dal/include/video_gamma_types.h    |   56 +
- 294 files changed, 87748 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/dal/Kconfig
- create mode 100644 drivers/gpu/drm/amd/dal/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dal_power_interface_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dal_services.h
- create mode 100644 drivers/gpu/drm/amd/dal/dal_services_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/vector.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_target.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_helpers.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_services.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_temp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/irq.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/irq.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/compressor.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_status.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/ipp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/opp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/resource.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/transform.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/irq_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adapter_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adjustment_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/adjustment_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/asic_capability_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/audio_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/audio_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/bit_set.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/clock_source_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/clock_source_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/connector_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dal_asic_id.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dal_register_logger.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dal_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dcs_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dcs_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_clock_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_path_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_path_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/display_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_defs.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/dvo_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/encoder_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/encoder_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/fixed31_32.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/fixed32_32.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/gpu_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_csc_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_defs.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_id.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/i2caux_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/irq_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/irq_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/isr_config_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/link_encoder_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/logger_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/logger_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/mode_manager_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/mode_query_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/overlay_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/overlay_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/plane_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/scaler_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/signal_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/timing_generator_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/vector.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/video_csc_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
-new file mode 100644
-index 0000000..14df02e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/Kconfig
-@@ -0,0 +1,39 @@
-+menu "Display Engine Configuration"
-+	depends on DRM && (DRM_AMDSOC || DRM_AMDGPU)
-+
-+config DRM_AMD_DAL
-+        bool "AMD DAL - Enable new display engine (will be deprecated when the development is done)"
-+        help
-+          Choose this option if you want to use the new display engine
-+          support for AMD SOC.
-+
-+          Will be deprecated when the DAL component becomes stable and
-+          AMDSOC will fully switch to it.
-+
-+config DRM_AMD_DAL_VBIOS_PRESENT
-+        bool "Video Bios available on board"
-+        depends on DRM_AMD_DAL
-+        help
-+         This option is needed to allow a full range of feature
-+	 support when working on
-+	 x86 platforms and there is a VBIOS
-+	 present in the system
-+
-+config DRM_AMD_DAL_DCE11_0
-+        bool "Carrizo family"
-+        depends on DRM_AMD_DAL
-+        help
-+         Choose this option
-+	 if you want to have
-+	 CZ family
-+	 for display engine
-+
-+config DEBUG_KERNEL_DAL
-+        bool "Enable kgdb break in DAL"
-+        depends on DRM_AMD_DAL
-+        help
-+         Choose this option
-+         if you want to hit
-+         kdgb_break in assert.
-+
-+endmenu
-diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile
-new file mode 100644
-index 0000000..bdf5d18
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/Makefile
-@@ -0,0 +1,19 @@
-+#
-+# Makefile for the DAL (Display Abstract Layer), which is a  sub-component
-+# of the AMDGPU drm driver.
-+# It provides the HW control for display related functionalities.
-+
-+AMDDALPATH = $(RELATIVE_AMD_DAL_PATH)
-+
-+subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include -DDAL_CZ_BRINGUP
-+
-+subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/
-+
-+#TODO: remove when Timing Sync feature is complete
-+subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
-+
-+DAL_LIBS = amdgpu_dm dc
-+
-+AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/,$(DAL_LIBS)))
-+
-+include $(AMD_DAL)
-diff --git a/drivers/gpu/drm/amd/dal/dal_power_interface_types.h b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
-new file mode 100644
-index 0000000..82e8ca2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
-@@ -0,0 +1,76 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_POWER_INTERFACE_TYPES_H__
-+#define __DAL_POWER_INTERFACE_TYPES_H__
-+
-+enum dal_to_power_clocks_state {
-+	PP_CLOCKS_STATE_INVALID,
-+	PP_CLOCKS_STATE_ULTRA_LOW,
-+	PP_CLOCKS_STATE_LOW,
-+	PP_CLOCKS_STATE_NOMINAL,
-+	PP_CLOCKS_STATE_PERFORMANCE
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_info {
-+	enum dal_to_power_clocks_state required_clock;
-+	uint32_t min_sclk;
-+	uint32_t min_mclk;
-+	uint32_t min_deep_sleep_sclk;
-+};
-+
-+/* clocks in khz */
-+struct power_to_dal_info {
-+	uint32_t min_sclk;
-+	uint32_t max_sclk;
-+	uint32_t min_mclk;
-+	uint32_t max_mclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_system_clock_range {
-+	uint32_t min_sclk;
-+	uint32_t max_sclk;
-+
-+	uint32_t min_mclk;
-+	uint32_t max_mclk;
-+
-+	uint32_t min_dclk;
-+	uint32_t max_dclk;
-+
-+	/* Wireless Display */
-+	uint32_t min_eclk;
-+	uint32_t max_eclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_dclk {
-+	uint32_t optimal; /* input: best optimizes for stutter efficiency */
-+	uint32_t minimal; /* input: the lowest clk that DAL can support */
-+	uint32_t established; /* output: the actually set one */
-+};
-+
-+#endif /* __DAL_POWER_INTERFACE_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dal_services.h b/drivers/gpu/drm/amd/dal/dal_services.h
-new file mode 100644
-index 0000000..398e4e5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dal_services.h
-@@ -0,0 +1,266 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SERVICES_H__
-+#define __DAL_SERVICES_H__
-+
-+/* DC headers*/
-+#include "dc/dc_services.h"
-+
-+#include "dal_power_interface_types.h"
-+
-+#include "irq_types.h"
-+#include "include/dal_types.h"
-+
-+/* TODO: investigate if it can be removed. */
-+/* Undefine DEPRECATED because it conflicts with printk.h */
-+#undef DEPRECATED
-+
-+/*
-+ *
-+ * interrupt services to register and unregister handlers
-+ *
-+ */
-+
-+/* the timer "interrupt" current implementation supports only
-+'one-shot' type, and LOW level (asynchronous) context */
-+void dal_register_timer_interrupt(
-+	struct dc_context *ctx,
-+	struct dc_timer_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *handler_args);
-+
-+/*
-+ *
-+ * kernel memory manipulation
-+ *
-+ */
-+
-+/* Reallocate memory. The contents will remain unchanged.*/
-+void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
-+
-+void dc_service_memmove(void *dst, const void *src, uint32_t size);
-+
-+void dc_service_memset(void *p, int32_t c, uint32_t count);
-+
-+int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
-+
-+int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
-+
-+/*
-+ *
-+ * GPU registers access
-+ *
-+ */
-+static inline uint32_t dal_read_reg(
-+	const struct dc_context *ctx,
-+	uint32_t address)
-+{
-+	uint32_t value = cgs_read_register(ctx->cgs_device, address);
-+
-+#if defined(__DAL_REGISTER_LOGGER__)
-+	if (true == dal_reg_logger_should_dump_register()) {
-+		dal_reg_logger_rw_count_increment();
-+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+	}
-+#endif
-+	return value;
-+}
-+
-+static inline uint32_t get_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (mask & reg_value) >> shift;
-+}
-+
-+#define get_reg_field_value(reg_value, reg_name, reg_field)\
-+	get_reg_field_value_ex(\
-+		(reg_value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline uint32_t set_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (reg_value & ~mask) | (mask & (value << shift));
-+}
-+
-+#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
-+	(reg_value) = set_reg_field_value_ex(\
-+		(reg_value),\
-+		(value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline void dal_write_reg(
-+	const struct dc_context *ctx,
-+	uint32_t address,
-+	uint32_t value)
-+{
-+#if defined(__DAL_REGISTER_LOGGER__)
-+	if (true == dal_reg_logger_should_dump_register()) {
-+		dal_reg_logger_rw_count_increment();
-+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+	}
-+#endif
-+	cgs_write_register(ctx->cgs_device, address, value);
-+}
-+
-+static inline uint32_t dal_read_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index)
-+{
-+	return cgs_read_ind_register(ctx->cgs_device,addr_space,index);
-+}
-+
-+static inline void dal_write_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index,
-+	uint32_t value)
-+{
-+	cgs_write_ind_register(ctx->cgs_device,addr_space,index,value);
-+}
-+
-+enum platform_method {
-+	PM_GET_AVAILABLE_METHODS = 1 << 0,
-+	PM_GET_LID_STATE = 1 << 1,
-+	PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2
-+};
-+
-+struct platform_info_params {
-+	enum platform_method method;
-+	void *data;
-+};
-+
-+struct platform_info_brightness_caps {
-+	uint8_t ac_level_percentage;
-+	uint8_t dc_level_percentage;
-+};
-+
-+struct platform_info_ext_brightness_caps {
-+	struct platform_info_brightness_caps basic_caps;
-+	struct data_point {
-+		uint8_t luminance;
-+		uint8_t	signal_level;
-+	} data_points[99];
-+
-+	uint8_t	data_points_num;
-+	uint8_t	min_input_signal;
-+	uint8_t	max_input_signal;
-+};
-+
-+bool dal_get_platform_info(
-+	struct dc_context *ctx,
-+	struct platform_info_params *params);
-+
-+
-+static inline uint32_t dal_bios_cmd_table_para_revision(
-+	struct dc_context *ctx,
-+	uint32_t index)
-+{
-+	uint8_t frev;
-+	uint8_t crev;
-+
-+	if (cgs_atom_get_cmd_table_revs(
-+			ctx->cgs_device,
-+			index,
-+			&frev,
-+			&crev) != 0)
-+		return 0;
-+
-+	return crev;
-+}
-+
-+/* Calls to notification */
-+
-+/* Notify display manager for hotplug event */
-+void dal_notify_hotplug(
-+	struct dc_context *ctx,
-+	uint32_t display_index,
-+	bool is_connected);
-+
-+
-+void dal_notify_setmode_complete(
-+	struct dc_context *ctx,
-+	uint32_t h_total,
-+	uint32_t v_total,
-+	uint32_t h_active,
-+	uint32_t v_active,
-+	uint32_t pix_clk_in_khz);
-+
-+/* End of notification calls */
-+
-+/*
-+ *
-+ * Delay functions.
-+ *
-+ *
-+ */
-+
-+/* Following the guidance:
-+ * https://www.kernel.org/doc/Documentation/timers/timers-howto.txt
-+ *
-+ * This is a busy wait for nano seconds and should be used only for
-+ * extremely short ranges
-+ */
-+void dal_delay_in_nanoseconds(uint32_t nanoseconds);
-+
-+
-+/*
-+ *
-+ * atombios services
-+ *
-+ */
-+
-+bool dal_exec_bios_cmd_table(
-+	struct dc_context *ctx,
-+	uint32_t index,
-+	void *params);
-+
-+/*
-+ *
-+ * print-out services
-+ *
-+ */
-+#define dal_log_to_buffer(buffer, size, fmt, args)\
-+	vsnprintf(buffer, size, fmt, args)
-+
-+long dal_get_pid(void);
-+long dal_get_tgid(void);
-+
-+/*
-+ *
-+ * general debug capabilities
-+ *
-+ */
-+
-+#endif /* __DAL_SERVICES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dal_services_types.h b/drivers/gpu/drm/amd/dal/dal_services_types.h
-new file mode 100644
-index 0000000..89c73c6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dal_services_types.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SERVICES_TYPES_H__
-+#define __DAL_SERVICES_TYPES_H__
-+
-+#define INVALID_DISPLAY_INDEX 0xffffffff
-+
-+#if defined __KERNEL__
-+
-+#include <asm/byteorder.h>
-+#include <linux/types.h>
-+#include <drm/drmP.h>
-+
-+#include "cgs_linux.h"
-+
-+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
-+#define BIGENDIAN_CPU
-+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
-+#define LITTLEENDIAN_CPU
-+#endif
-+
-+#undef READ
-+#undef WRITE
-+#undef FRAME_SIZE
-+
-+#define dal_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
-+
-+#define dal_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-+
-+#define dal_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-+
-+#define dal_vlog(fmt, args) vprintk(fmt, args)
-+
-+#define dal_min(x, y) min(x, y)
-+#define dal_max(x, y) max(x, y)
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-new file mode 100644
-index 0000000..6926356
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -0,0 +1,24 @@
-+#
-+# Makefile for Display Core (dc) component.
-+#
-+
-+DC_LIBS = adapter asic_capability audio basics bios calcs connector \
-+dcs gpio gpu i2caux irq
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+DC_LIBS += dce110
-+endif
-+
-+AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS)))
-+
-+include $(AMD_DC)
-+
-+DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_target.o dc_sink.o dc_stream.o \
-+dc_hw_sequencer.o dc_surface.o dc_link_hwss.o dc_link_dp.o
-+
-+AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
-+
-+AMD_DAL_FILES += $(AMD_DISPLAY_CORE)
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-new file mode 100644
-index 0000000..8ede504
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-@@ -0,0 +1,18 @@
-+#
-+# Makefile for the 'adapter' sub-component of DAL.
-+# It provides the control and status of HW adapter.
-+
-+ADAPTER = adapter_service.o hw_ctx_adapter_service.o wireless_data_source.o
-+
-+AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ADAPTER)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce110/hw_ctx_adapter_service_dce110.o
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-new file mode 100644
-index 0000000..4f9a637
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -0,0 +1,2037 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#include "dal_services.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/asic_capability_types.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "include/asic_capability_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "adapter_service.h"
-+#include "hw_ctx_adapter_service.h"
-+#include "wireless_data_source.h"
-+
-+#include "atom.h"
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/hw_ctx_adapter_service_dce110.h"
-+#endif
-+
-+/*
-+ * Adapter service feature entry table.
-+ *
-+ * This is an array of features that is used to generate feature set. Each
-+ * entry consists three element:
-+ *
-+ * Feature name, default value, and if this feature is a boolean type. A
-+ * feature can only be a boolean or int type.
-+ *
-+ * Example 1: a boolean type feature
-+ * FEATURE_ENABLE_HW_EDID_POLLING, false, true
-+ *
-+ * First element is feature name: EATURE_ENABLE_HW_EDID_POLLING, it has a
-+ * default value 0, and it is a boolean feature.
-+ *
-+ * Example 2: an int type feature
-+ * FEATURE_DCP_PROGRAMMING_WA, 0x1FF7, false
-+ *
-+ * In this case, the default value is 0x1FF7 and not a boolean type, which
-+ * makes it an int type.
-+ */
-+
-+static
-+#if !defined(DAL_CZ_BRINGUP)
-+const
-+#endif
-+struct feature_source_entry feature_entry_table[] = {
-+	/* Feature name | default value | is boolean type */
-+	{FEATURE_ENABLE_HW_EDID_POLLING, false, true},
-+	{FEATURE_DP_SINK_DETECT_POLL_DATA_PIN, false, true},
-+	{FEATURE_UNDERFLOW_INTERRUPT, false, true},
-+	{FEATURE_ALLOW_WATERMARK_ADJUSTMENT, false, true},
-+	{FEATURE_LIGHT_SLEEP, false, true},
-+	{FEATURE_DCP_DITHER_FRAME_RANDOM_ENABLE, false, true},
-+	{FEATURE_DCP_DITHER_RGB_RANDOM_ENABLE, false, true},
-+	{FEATURE_DCP_DITHER_HIGH_PASS_RANDOM_ENABLE, false, true},
-+	{FEATURE_LINE_BUFFER_ENHANCED_PIXEL_DEPTH, false, true},
-+	{FEATURE_MAXIMIZE_URGENCY_WATERMARKS, false, true},
-+	{FEATURE_MAXIMIZE_STUTTER_MARKS, false, true},
-+	{FEATURE_MAXIMIZE_NBP_MARKS, false, true},
-+	/*
-+	 * We meet HW I2C issue when test S3 resume on KB.
-+	 * An EPR is created for debug the issue.
-+	 * Make Test has already been implemented
-+	 * with HW I2C. The work load for revert back to SW I2C in make test
-+	 * is big. Below is workaround for this issue.
-+	 * Driver uses SW I2C.
-+	 * Make Test uses HW I2C.
-+	 */
-+#if defined(DAL_CZ_BRINGUP)
-+	{FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, true, true},
-+#else
-+	{FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, false, true},
-+#endif
-+	{FEATURE_USE_MAX_DISPLAY_CLK, false, true},
-+	{FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
-+	{FEATURE_SUPPORT_DP_YUV, false, true},
-+	{FEATURE_SUPPORT_DP_Y_ONLY, false, true},
-+	{FEATURE_DISABLE_DP_GTC_SYNC, true, true},
-+	{FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
-+	{FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE, 0, false},
-+	{FEATURE_DCP_DITHER_MODE, 0, false},
-+	{FEATURE_DCP_PROGRAMMING_WA, 0, false},
-+	{FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
-+	{FEATURE_ENABLE_DFS_BYPASS, false, true},
-+	{FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
-+	{FEATURE_MAX_COFUNC_NON_DP_DISPLAYS, 2, false},
-+	{FEATURE_WIRELESS_LIMIT_720P, false, true},
-+	{FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
-+	{FEATURE_SUPPORTED_HDMI_CONNECTION_NUM, 0, false},
-+	{FEATURE_DETECT_REQUIRE_HPD_HIGH, false, true},
-+	{FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
-+	{FEATURE_LB_HIGH_RESOLUTION, false, true},
-+	{FEATURE_MAX_CONTROLLER_NUM, 0, false},
-+	{FEATURE_DRR_SUPPORT, AS_DRR_SUPPORT_ENABLED, false},
-+	{FEATURE_STUTTER_MODE, 15, false},
-+	{FEATURE_DP_DISPLAY_FORCE_SS_ENABLE, false, true},
-+	{FEATURE_REPORT_CE_MODE_ONLY, false, true},
-+	{FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT, false, true},
-+	{FEATURE_DDC_READ_FORCE_REPEATED_START, false, true},
-+	{FEATURE_FORCE_TIMING_RESYNC, false, true},
-+	{FEATURE_TMDS_DISABLE_DITHERING, false, true},
-+	{FEATURE_HDMI_DISABLE_DITHERING, false, true},
-+	{FEATURE_DP_DISABLE_DITHERING, false, true},
-+	{FEATURE_EMBEDDED_DISABLE_DITHERING, true, true},
-+	{FEATURE_ALLOW_SELF_REFRESH, false, true},
-+	{FEATURE_ALLOW_DYNAMIC_PIXEL_ENCODING_CHANGE, false, true},
-+	{FEATURE_ALLOW_HSYNC_VSYNC_ADJUSTMENT, false, true},
-+	{FEATURE_FORCE_PSR, false, true},
-+	{FEATURE_PSR_SETUP_TIME_TEST, 0, false},
-+	{FEATURE_POWER_GATING_PIPE_IN_TILE, true, true},
-+	{FEATURE_POWER_GATING_LB_PORTION, true, true},
-+	{FEATURE_PREFER_3D_TIMING, false, true},
-+	{FEATURE_VARI_BRIGHT_ENABLE, true, true},
-+	{FEATURE_PSR_ENABLE, false, true},
-+	{FEATURE_WIRELESS_ENABLE_COMPRESSED_AUDIO, false, true},
-+	{FEATURE_WIRELESS_INCLUDE_UNVERIFIED_TIMINGS, true, true},
-+	{FEATURE_EDID_STRESS_READ, false, true},
-+	{FEATURE_DP_FRAME_PACK_STEREO3D, false, true},
-+	{FEATURE_DISPLAY_PREFERRED_VIEW, 0, false},
-+	{FEATURE_ALLOW_HDMI_WITHOUT_AUDIO, false, true},
-+	{FEATURE_ABM_2_0, false, true},
-+	{FEATURE_SUPPORT_MIRABILIS, false, true},
-+	{FEATURE_OPTIMIZATION, 0xFFFF, false},
-+	{FEATURE_PERF_MEASURE, 0, false},
-+	{FEATURE_MIN_BACKLIGHT_LEVEL, 0, false},
-+	{FEATURE_MAX_BACKLIGHT_LEVEL, 255, false},
-+	{FEATURE_LOAD_DMCU_FIRMWARE, true, true},
-+	{FEATURE_DISABLE_AZ_CLOCK_GATING, false, true},
-+	{FEATURE_ENABLE_GPU_SCALING, false, true},
-+	{FEATURE_DONGLE_SINK_COUNT_CHECK, true, true},
-+	{FEATURE_INSTANT_UP_SCALE_DOWN_SCALE, false, true},
-+	{FEATURE_TILED_DISPLAY, false, true},
-+	{FEATURE_PREFERRED_ABM_CONFIG_SET, 0, false},
-+	{FEATURE_CHANGE_SW_I2C_SPEED, 50, false},
-+	{FEATURE_CHANGE_HW_I2C_SPEED, 50, false},
-+	{FEATURE_CHANGE_I2C_SPEED_CONTROL, false, true},
-+	{FEATURE_DEFAULT_PSR_LEVEL, 0, false},
-+	{FEATURE_MAX_CLOCK_SOURCE_NUM, 0, false},
-+	{FEATURE_REPORT_SINGLE_SELECTED_TIMING, false, true},
-+	{FEATURE_ALLOW_HDMI_HIGH_CLK_DP_DONGLE, true, true},
-+	{FEATURE_SUPPORT_EXTERNAL_PANEL_DRR, false, true},
-+	{FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE, 0, false},
-+	{FEATURE_ABM_CONFIG, 0, false},
-+	{FEATURE_WIRELESS_ENABLE, false, true},
-+	{FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, false, true},
-+	{FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS, 0, false},
-+	{FEATURE_USE_PPLIB, true, true},
-+	{FEATURE_DISABLE_LPT_SUPPORT, false, true},
-+	{FEATURE_DUMMY_FBC_BACKEND, false, true},
-+	{FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL, true, true},
-+	{FEATURE_DISABLE_FBC_COMP_CLK_GATE, false, true},
-+	{FEATURE_PIXEL_PERFECT_OUTPUT, false, true},
-+	{FEATURE_8BPP_SUPPORTED, false, true}
-+};
-+
-+
-+/* Stores entire ASIC features by sets */
-+uint32_t adapter_feature_set[FEATURE_MAXIMUM/32];
-+
-+enum {
-+	LEGACY_MAX_NUM_OF_CONTROLLERS = 2,
-+	DEFAULT_NUM_COFUNC_NON_DP_DISPLAYS = 2
-+};
-+
-+/*
-+ * get_feature_entries_num
-+ *
-+ * Get number of feature entries
-+ */
-+static inline uint32_t get_feature_entries_num(void)
-+{
-+	return ARRAY_SIZE(feature_entry_table);
-+}
-+
-+static void get_platform_info_methods(
-+		struct adapter_service *as)
-+{
-+	struct platform_info_params params;
-+	uint32_t mask = 0;
-+
-+	params.data = &mask;
-+	params.method = PM_GET_AVAILABLE_METHODS;
-+
-+	if (dal_get_platform_info(as->ctx, &params))
-+		as->platform_methods_mask = mask;
-+
-+
-+}
-+
-+static void initialize_backlight_caps(
-+		struct adapter_service *as)
-+{
-+	struct firmware_info fw_info;
-+	struct embedded_panel_info panel_info;
-+	struct platform_info_ext_brightness_caps caps;
-+	struct platform_info_params params;
-+	bool custom_curve_present = false;
-+	bool custom_min_max_present = false;
-+
-+	if (!(PM_GET_EXTENDED_BRIGHNESS_CAPS & as->platform_methods_mask)) {
-+			dal_logger_write(as->ctx->logger,
-+					LOG_MAJOR_BACKLIGHT,
-+					LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS,
-+					"This method is not supported\n");
-+			return;
-+	}
-+
-+	if (dal_bios_parser_get_firmware_info
-+			(as->bios_parser, &fw_info)	!= BP_RESULT_OK ||
-+		dal_bios_parser_get_embedded_panel_info
-+			(as->bios_parser, &panel_info) != BP_RESULT_OK)
-+		return;
-+
-+	params.data = &caps;
-+	params.method = PM_GET_EXTENDED_BRIGHNESS_CAPS;
-+
-+	if (dal_get_platform_info(as->ctx, &params)) {
-+		as->ac_level_percentage = caps.basic_caps.ac_level_percentage;
-+		as->dc_level_percentage = caps.basic_caps.dc_level_percentage;
-+		custom_curve_present = (caps.data_points_num > 0);
-+		custom_min_max_present = true;
-+	} else
-+		return;
-+	/* Choose minimum backlight level base on priority:
-+	 * extended caps,VBIOS,default */
-+	if (custom_min_max_present)
-+		as->backlight_8bit_lut[0] = caps.min_input_signal;
-+
-+	else if (fw_info.min_allowed_bl_level > 0)
-+		as->backlight_8bit_lut[0] = fw_info.min_allowed_bl_level;
-+
-+	else
-+		as->backlight_8bit_lut[0] = DEFAULT_MIN_BACKLIGHT;
-+
-+	/* Choose maximum backlight level base on priority:
-+	 * extended caps,default */
-+	if (custom_min_max_present)
-+		as->backlight_8bit_lut[100] = caps.max_input_signal;
-+
-+	else
-+		as->backlight_8bit_lut[100] = DEFAULT_MAX_BACKLIGHT;
-+
-+	if (as->backlight_8bit_lut[100] > ABSOLUTE_BACKLIGHT_MAX)
-+		as->backlight_8bit_lut[100] = ABSOLUTE_BACKLIGHT_MAX;
-+
-+	if (as->backlight_8bit_lut[0] > as->backlight_8bit_lut[100])
-+		as->backlight_8bit_lut[0] = as->backlight_8bit_lut[100];
-+
-+	if (custom_curve_present) {
-+		uint16_t index = 1;
-+		uint16_t i;
-+		uint16_t num_of_data_points = (caps.data_points_num <= 99 ?
-+				caps.data_points_num : 99);
-+		/* Filling translation table from data points -
-+		 * between every two provided data points we
-+		 * lineary interpolate missing values
-+		 */
-+		for (i = 0 ; i < num_of_data_points; i++) {
-+			uint16_t luminance = caps.data_points[i].luminance;
-+			uint16_t signal_level =
-+					caps.data_points[i].signal_level;
-+
-+			if (signal_level < as->backlight_8bit_lut[0])
-+				signal_level = as->backlight_8bit_lut[0];
-+
-+			if (signal_level > as->backlight_8bit_lut[100])
-+				signal_level = as->backlight_8bit_lut[100];
-+
-+			/* Lineary interpolate missing values */
-+			if (index < luminance) {
-+				uint16_t base_value =
-+						as->backlight_8bit_lut[index-1];
-+				uint16_t delta_signal =
-+						signal_level - base_value;
-+				uint16_t delta_luma = luminance - index + 1;
-+				uint16_t step = delta_signal;
-+
-+				for (; index < luminance ; index++) {
-+					as->backlight_8bit_lut[index] =
-+							base_value +
-+							(step / delta_luma);
-+					step += delta_signal;
-+				}
-+			}
-+			/* Now [index == luminance], so we can add
-+			 * data point to the translation table */
-+			as->backlight_8bit_lut[index++] = signal_level;
-+		}
-+		/* Complete the final segment of interpolation -
-+		 * between last datapoint and maximum value */
-+		if (index < 100) {
-+			uint16_t base_value = as->backlight_8bit_lut[index-1];
-+			uint16_t delta_signal =
-+					as->backlight_8bit_lut[100]-base_value;
-+			uint16_t delta_luma = 100 - index + 1;
-+			uint16_t step = delta_signal;
-+
-+			for (; index < 100 ; index++) {
-+				as->backlight_8bit_lut[index] = base_value +
-+						(step / delta_luma);
-+				step += delta_signal;
-+			}
-+		}
-+	}
-+	/* build backlight translation table based on default curve */
-+	else {
-+		/* Default backlight curve can be defined by
-+		 * polinomial F(x) = A(x*x) + Bx + C.
-+		 * Backlight curve should always  satisfy
-+		 * F(0) = min, F(100) = max, so polinomial coefficients are:
-+		 * A is 0.0255 - B/100 - min/10000 -
-+		 * (255-max)/10000 = (max - min)/10000 - B/100
-+		 * B is adjustable factor to modify the curve.
-+		 * Bigger B results in less concave curve.
-+		 * B range is [0..(max-min)/100]
-+		 * C is backlight minimum
-+		 */
-+		uint16_t delta = as->backlight_8bit_lut[100] -
-+				as->backlight_8bit_lut[0];
-+		uint16_t coeffc = as->backlight_8bit_lut[0];
-+		uint16_t coeffb = (BACKLIGHT_CURVE_COEFFB < delta ?
-+				BACKLIGHT_CURVE_COEFFB : delta);
-+		uint16_t coeffa = delta - coeffb;
-+		uint16_t i;
-+		uint32_t temp;
-+
-+		for (i = 1; i < 100 ; i++) {
-+			temp = (coeffa * i * i) / BACKLIGHT_CURVE_COEFFA_FACTOR;
-+			as->backlight_8bit_lut[i] = temp + (coeffb * i) /
-+					BACKLIGHT_CURVE_COEFFB_FACTOR + coeffc;
-+		}
-+	}
-+	as->backlight_caps_initialized = true;
-+}
-+
-+static void log_overriden_features(
-+	struct adapter_service *as,
-+	const char *feature_name,
-+	enum adapter_feature_id id,
-+	bool bool_feature,
-+	uint32_t value)
-+{
-+	if (bool_feature)
-+		dal_logger_write(as->ctx->logger,
-+			LOG_MAJOR_FEATURE_OVERRIDE,
-+			LOG_MINOR_FEATURE_OVERRIDE,
-+			"Overridden %s is %s now\n",
-+			feature_name,
-+			(value == 0) ? "disabled" : "enabled");
-+	else
-+		dal_logger_write(as->ctx->logger,
-+			LOG_MAJOR_FEATURE_OVERRIDE,
-+			LOG_MINOR_FEATURE_OVERRIDE,
-+			"Overridden %s new value: %d\n",
-+			feature_name,
-+			value);
-+}
-+
-+/*************************************
-+ * Local static functions definition *
-+ *************************************/
-+
-+#define check_bool_feature(feature) \
-+case FEATURE_ ## feature: \
-+	if (param->bool_param_enable_mask & \
-+		(1 << DAL_PARAM_ ## feature)) { \
-+		*data = param->bool_param_values & \
-+		(1 << DAL_PARAM_ ## feature); \
-+		ret = true; \
-+		feature_name = "FEATURE_" #feature; \
-+	} \
-+	break
-+
-+#define check_int_feature(feature) \
-+case FEATURE_ ## feature: \
-+	if (param->int_param_values[DAL_PARAM_ ## feature] != \
-+		DAL_PARAM_INVALID_INT) { \
-+		*data = param->int_param_values[DAL_PARAM_ ## feature];\
-+		ret = true;\
-+		bool_feature = false;\
-+		feature_name = "FEATURE_" #feature;\
-+	} \
-+	break
-+
-+/*
-+ * override_default_parameters
-+ *
-+ * Override features (from runtime parameter)
-+ * corresponding to Adapter Service Feature ID
-+ */
-+static bool override_default_parameters(
-+	struct adapter_service *as,
-+	const struct dal_override_parameters *param,
-+	const uint32_t idx,
-+	uint32_t *data)
-+{
-+	bool ret = false;
-+	bool bool_feature = true;
-+	char *feature_name;
-+
-+	if (idx >= get_feature_entries_num()) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	switch (feature_entry_table[idx].feature_id) {
-+	check_int_feature(MAX_COFUNC_NON_DP_DISPLAYS);
-+	check_int_feature(DRR_SUPPORT);
-+	check_bool_feature(LIGHT_SLEEP);
-+	check_bool_feature(MAXIMIZE_STUTTER_MARKS);
-+	check_bool_feature(MAXIMIZE_URGENCY_WATERMARKS);
-+	check_bool_feature(USE_MAX_DISPLAY_CLK);
-+	check_bool_feature(ENABLE_DFS_BYPASS);
-+	check_bool_feature(POWER_GATING_PIPE_IN_TILE);
-+	check_bool_feature(POWER_GATING_LB_PORTION);
-+	check_bool_feature(PSR_ENABLE);
-+	check_bool_feature(VARI_BRIGHT_ENABLE);
-+	check_bool_feature(USE_PPLIB);
-+	check_bool_feature(DISABLE_LPT_SUPPORT);
-+	check_bool_feature(DUMMY_FBC_BACKEND);
-+	check_bool_feature(ENABLE_GPU_SCALING);
-+	default:
-+		return false;
-+	}
-+	if (ret)
-+		log_overriden_features(
-+			as,
-+			feature_name,
-+			feature_entry_table[idx].feature_id,
-+			bool_feature,
-+			*data);
-+
-+	return ret;
-+}
-+
-+/*
-+ * get_feature_value_from_data_sources
-+ *
-+ * For a given feature, determine its value from ASIC cap and wireless
-+ * data source.
-+ * idx : index of feature_entry_table for the feature id.
-+ */
-+static bool get_feature_value_from_data_sources(
-+		const struct adapter_service *as,
-+		const uint32_t idx,
-+		uint32_t *data)
-+{
-+	if (idx >= get_feature_entries_num()) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	switch (feature_entry_table[idx].feature_id) {
-+	case FEATURE_MAX_COFUNC_NON_DP_DISPLAYS:
-+		*data = as->asic_cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS];
-+		break;
-+
-+	case FEATURE_WIRELESS_LIMIT_720P:
-+		*data = as->asic_cap->caps.WIRELESS_LIMIT_TO_720P;
-+		break;
-+
-+	case FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT:
-+		*data = as->asic_cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT;
-+		break;
-+
-+	case FEATURE_MODIFY_TIMINGS_FOR_WIRELESS:
-+		*data = as->asic_cap->caps.WIRELESS_TIMING_ADJUSTMENT;
-+		break;
-+
-+	case FEATURE_SUPPORTED_HDMI_CONNECTION_NUM:
-+		*data =
-+		as->asic_cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM];
-+		break;
-+
-+	case FEATURE_DETECT_REQUIRE_HPD_HIGH:
-+		*data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
-+		break;
-+
-+	case FEATURE_NO_HPD_LOW_POLLING_VCC_OFF:
-+		*data = as->asic_cap->caps.NO_VCC_OFF_HPD_POLLING;
-+		break;
-+
-+	case FEATURE_STUTTER_MODE:
-+		*data = as->asic_cap->data[ASIC_DATA_STUTTERMODE];
-+		break;
-+
-+	case FEATURE_WIRELESS_ENABLE:
-+		*data = as->wireless_data.wireless_enable;
-+		break;
-+
-+	case FEATURE_8BPP_SUPPORTED:
-+		*data = as->asic_cap->caps.SUPPORT_8BPP;
-+		break;
-+
-+	default:
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+/* get_bool_value
-+ *
-+ * Get the boolean value of a given feature
-+ */
-+static bool get_bool_value(
-+	const uint32_t set,
-+	const uint32_t idx)
-+{
-+	if (idx >= 32) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	return ((set & (1 << idx)) != 0);
-+}
-+
-+/*
-+ * get_hpd_info
-+ *
-+ * Get HPD information from BIOS
-+ */
-+static bool get_hpd_info(struct adapter_service *as,
-+	struct graphics_object_id id,
-+	struct graphics_object_hpd_info *info)
-+{
-+	return BP_RESULT_OK ==
-+		dal_bios_parser_get_hpd_info(as->bios_parser, id, info);
-+}
-+
-+/*
-+ * lookup_feature_entry
-+ *
-+ * Find the entry index of a given feature in feature table
-+ */
-+static uint32_t lookup_feature_entry(
-+	enum adapter_feature_id feature_id)
-+{
-+	uint32_t entries_num = get_feature_entries_num();
-+	uint32_t i = 0;
-+
-+	while (i != entries_num) {
-+		if (feature_entry_table[i].feature_id == feature_id)
-+			break;
-+
-+		++i;
-+	}
-+
-+	return i;
-+}
-+
-+/*
-+ * set_bool_value
-+ *
-+ * Set the boolean value of a given feature
-+ */
-+static void set_bool_value(
-+	uint32_t *set,
-+	const uint32_t idx,
-+	bool value)
-+{
-+	if (idx >= 32) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	if (value)
-+		*set |= (1 << idx);
-+	else
-+		*set &= ~(1 << idx);
-+}
-+
-+/*
-+ * generate_feature_set
-+ *
-+ * Generate the internal feature set from multiple data sources
-+ */
-+static bool generate_feature_set(
-+		struct adapter_service *as,
-+		const struct dal_override_parameters *param)
-+{
-+	uint32_t i = 0;
-+	uint32_t value = 0;
-+	uint32_t set_idx = 0;
-+	uint32_t internal_idx = 0;
-+	uint32_t entry_num = 0;
-+	const struct feature_source_entry *entry = NULL;
-+
-+	dc_service_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
-+	entry_num = get_feature_entries_num();
-+
-+
-+	while (i != entry_num) {
-+		entry = &feature_entry_table[i];
-+
-+		if (entry->feature_id <= FEATURE_UNKNOWN ||
-+				entry->feature_id >= FEATURE_MAXIMUM) {
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+
-+		set_idx = (uint32_t)((entry->feature_id - 1) / 32);
-+		internal_idx = (uint32_t)((entry->feature_id - 1) % 32);
-+
-+		/* TODO: wireless, runtime parameter, vbios */
-+		if (!override_default_parameters(as, param, i, &value)) {
-+			if (!get_feature_value_from_data_sources(
-+					as, i, &value)) {
-+				/*
-+				 * Can't find feature values from
-+				 * above data sources
-+				 * Assign default value
-+				 */
-+				value = entry->default_value;
-+			}
-+		}
-+
-+		if (entry->is_boolean_type)
-+			set_bool_value(&adapter_feature_set[set_idx],
-+					internal_idx,
-+					value != 0);
-+		else
-+			adapter_feature_set[set_idx] = value;
-+
-+		i++;
-+	}
-+
-+	return true;
-+}
-+
-+
-+/*
-+ * create_hw_ctx
-+ *
-+ * Create HW context for adapter service. This is DCE specific.
-+ */
-+static struct hw_ctx_adapter_service *create_hw_ctx(
-+	enum dce_version dce_version,
-+	struct dc_context *ctx)
-+{
-+	switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		return dal_adapter_service_create_hw_ctx_dce110(ctx);
-+#endif
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+}
-+
-+/*
-+ * adapter_service_destruct
-+ *
-+ * Release memory of objects in adapter service
-+ */
-+static void adapter_service_destruct(
-+	struct adapter_service *as)
-+{
-+	dal_adapter_service_destroy_hw_ctx(&as->hw_ctx);
-+	dal_i2caux_destroy(&as->i2caux);
-+	dal_bios_parser_destroy(&as->bios_parser);
-+	dal_gpio_service_destroy(&as->gpio_service);
-+	dal_asic_capability_destroy(&as->asic_cap);
-+	dal_bios_parser_destroy_integrated_info(as->ctx, &as->integrated_info);
-+}
-+
-+/*
-+ * adapter_service_construct
-+ *
-+ * Construct the derived type of adapter service
-+ */
-+static bool adapter_service_construct(
-+	struct adapter_service *as,
-+	struct as_init_data *init_data)
-+{
-+	if (!init_data)
-+		return false;
-+
-+	/* Create ASIC capability */
-+	as->ctx = init_data->ctx;
-+	as->asic_cap = dal_asic_capability_create(
-+			&init_data->hw_init_data, as->ctx);
-+
-+	if (!as->asic_cap) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+#if defined(DAL_CZ_BRINGUP)
-+	if (dal_adapter_service_get_dce_version(as) == DCE_VERSION_11_0) {
-+		uint32_t i;
-+
-+		for (i = 0; i < ARRAY_SIZE(feature_entry_table); i++) {
-+			enum adapter_feature_id id =
-+				feature_entry_table[i].feature_id;
-+			if (id == FEATURE_MAXIMIZE_URGENCY_WATERMARKS ||
-+				id == FEATURE_MAXIMIZE_STUTTER_MARKS ||
-+				id == FEATURE_MAXIMIZE_NBP_MARKS)
-+				feature_entry_table[i].default_value = true;
-+		}
-+	}
-+#endif
-+
-+	/* Generate feature set table */
-+	if (!generate_feature_set(as, init_data->display_param)) {
-+		ASSERT_CRITICAL(false);
-+		goto failed_to_generate_features;
-+	}
-+
-+	/* Create BIOS parser */
-+	init_data->bp_init_data.ctx = init_data->ctx;
-+	as->bios_parser =
-+		dal_bios_parser_create(&init_data->bp_init_data, as);
-+
-+	if (!as->bios_parser) {
-+		ASSERT_CRITICAL(false);
-+		goto failed_to_create_bios_parser;
-+	}
-+
-+	/* Create GPIO service */
-+	as->gpio_service =
-+		dal_gpio_service_create(
-+				dal_adapter_service_get_dce_version(as),
-+				as->ctx);
-+
-+	if (!as->gpio_service) {
-+		ASSERT_CRITICAL(false);
-+		goto failed_to_create_gpio_service;
-+	}
-+
-+	/* Create I2C AUX */
-+	as->i2caux = dal_i2caux_create(as, as->ctx);
-+
-+	if (!as->i2caux) {
-+		ASSERT_CRITICAL(false);
-+		goto failed_to_create_i2caux;
-+	}
-+
-+	/* Create Adapter Service HW Context*/
-+	as->hw_ctx = create_hw_ctx(
-+		dal_adapter_service_get_dce_version(as),
-+		as->ctx);
-+
-+	if (!as->hw_ctx) {
-+		ASSERT_CRITICAL(false);
-+		goto failed_to_create_hw_ctx;
-+	}
-+
-+	/* Avoid wireless encoder creation in upstream branch. */
-+
-+	/* Integrated info is not provided on discrete ASIC. NULL is allowed */
-+	as->integrated_info = dal_bios_parser_create_integrated_info(
-+			as->bios_parser);
-+
-+	dal_bios_parser_post_init(as->bios_parser);
-+
-+	/* Generate backlight translation table and initializes
-+			  other brightness properties */
-+	as->backlight_caps_initialized = false;
-+
-+	get_platform_info_methods(as);
-+
-+	initialize_backlight_caps(as);
-+
-+	return true;
-+
-+failed_to_generate_features:
-+	dal_adapter_service_destroy_hw_ctx(&as->hw_ctx);
-+
-+failed_to_create_hw_ctx:
-+	dal_i2caux_destroy(&as->i2caux);
-+
-+failed_to_create_i2caux:
-+	dal_gpio_service_destroy(&as->gpio_service);
-+
-+failed_to_create_gpio_service:
-+	dal_bios_parser_destroy(&as->bios_parser);
-+
-+failed_to_create_bios_parser:
-+	dal_asic_capability_destroy(&as->asic_cap);
-+
-+	return false;
-+}
-+
-+/*
-+ * Global function definition
-+ */
-+
-+/*
-+ * dal_adapter_service_create
-+ *
-+ * Create adapter service
-+ */
-+struct adapter_service *dal_adapter_service_create(
-+	struct as_init_data *init_data)
-+{
-+	struct adapter_service *as;
-+
-+	as = dc_service_alloc(init_data->ctx, sizeof(struct adapter_service));
-+
-+	if (!as) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (adapter_service_construct(as, init_data))
-+		return as;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(init_data->ctx, as);
-+
-+	return NULL;
-+}
-+
-+/*
-+ * dal_adapter_service_destroy
-+ *
-+ * Destroy adapter service and objects it contains
-+ */
-+void dal_adapter_service_destroy(
-+	struct adapter_service **as)
-+{
-+	if (!as) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	if (!*as) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	adapter_service_destruct(*as);
-+
-+	dc_service_free((*as)->ctx, *as);
-+
-+	*as = NULL;
-+}
-+
-+/*
-+ * dal_adapter_service_get_dce_version
-+ *
-+ * Get the DCE version of current ASIC
-+ */
-+enum dce_version dal_adapter_service_get_dce_version(
-+	const struct adapter_service *as)
-+{
-+	uint32_t version = as->asic_cap->data[ASIC_DATA_DCE_VERSION];
-+
-+	switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case 0x110:
-+		return DCE_VERSION_11_0;
-+#endif
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return DCE_VERSION_UNKNOWN;
-+	}
-+}
-+
-+/*
-+ * dal_adapter_service_get_controllers_num
-+ *
-+ * Get number of controllers
-+ */
-+uint8_t dal_adapter_service_get_controllers_num(
-+	struct adapter_service *as)
-+{
-+	uint32_t result = as->asic_cap->data[ASIC_DATA_CONTROLLERS_NUM];
-+
-+	/* Check the "max num of controllers" feature,
-+	 * use it for debugging purposes only */
-+	/* TODO implement
-+	 * dal_adapter_service_get_feature_value(as, ) */
-+
-+	return result;
-+}
-+
-+
-+/** Get total number of connectors.
-+ *
-+ * \param as	Adapter Service
-+ *
-+ * \return Total number of connectors. It is up-to-the caller to decide
-+ *	if the number is valid.
-+ */
-+uint8_t dal_adapter_service_get_connectors_num(
-+	struct adapter_service *as)
-+{
-+	uint8_t vbios_connectors_num = 0;
-+	uint8_t wireless_connectors_num = 0;
-+
-+	vbios_connectors_num = dal_bios_parser_get_connectors_number(
-+			as->bios_parser);
-+	wireless_connectors_num = wireless_get_connectors_num(as);
-+
-+	return vbios_connectors_num + wireless_connectors_num;
-+}
-+
-+static bool is_wireless_object(struct graphics_object_id id)
-+{
-+	if ((id.type == OBJECT_TYPE_ENCODER &&
-+		id.id == ENCODER_ID_INTERNAL_WIRELESS) ||
-+		(id.type == OBJECT_TYPE_CONNECTOR && id.id ==
-+			CONNECTOR_ID_WIRELESS) ||
-+		(id.type == OBJECT_TYPE_CONNECTOR && id.id ==
-+			CONNECTOR_ID_MIRACAST))
-+		return true;
-+	return false;
-+}
-+
-+/**
-+ * Get the number of source objects of an object
-+ *
-+ * \param [in] as: Adapter Service
-+ *
-+ * \param [in] id: The graphics object id
-+ *
-+ * \return
-+ *     The number of the source objects of an object
-+ */
-+uint32_t dal_adapter_service_get_src_num(
-+	struct adapter_service *as, struct graphics_object_id id)
-+{
-+	if (is_wireless_object(id))
-+		return wireless_get_srcs_num(as, id);
-+	else
-+		return dal_bios_parser_get_src_number(as->bios_parser, id);
-+}
-+
-+/**
-+ * Get the source objects of an object
-+ *
-+ * \param [in] id      The graphics object id
-+ * \param [in] index   Enumerating index which starts at 0
-+ *
-+ * \return If enumerating successfully, return the VALID source object id,
-+ *	otherwise, returns "zeroed out" object id.
-+ *	Client should call dal_graphics_object_id_is_valid() to check
-+ *	weather the id is valid.
-+ */
-+struct graphics_object_id dal_adapter_service_get_src_obj(
-+	struct adapter_service *as,
-+	struct graphics_object_id id,
-+	uint32_t index)
-+{
-+	struct graphics_object_id src_object_id;
-+
-+	if (is_wireless_object(id))
-+		src_object_id = wireless_get_src_obj_id(as, id, index);
-+	else {
-+		if (BP_RESULT_OK !=
-+			dal_bios_parser_get_src_obj(
-+				as->bios_parser, id, index, &src_object_id))
-+			src_object_id =
-+				dal_graphics_object_id_init(
-+					0,
-+					ENUM_ID_UNKNOWN,
-+					OBJECT_TYPE_UNKNOWN);
-+	}
-+
-+	return src_object_id;
-+}
-+
-+/** Get connector object id associated with a connector index.
-+ *
-+ * \param as	Adapter Service
-+ *
-+ * \param connector_index Index of connector between zero and total number
-+ *	returned by dal_adapter_service_get_connectors_num()
-+ *
-+ * \return graphics object id corresponding to the connector_index.
-+ */
-+struct graphics_object_id dal_adapter_service_get_connector_obj_id(
-+		struct adapter_service *as,
-+		uint8_t connector_index)
-+{
-+	uint8_t bios_connectors_num =
-+		dal_bios_parser_get_connectors_number(as->bios_parser);
-+
-+	if (connector_index >= bios_connectors_num)
-+		return wireless_get_connector_id(
-+				as,
-+				connector_index);
-+	else
-+		return dal_bios_parser_get_connector_id(
-+				as->bios_parser,
-+				connector_index);
-+}
-+
-+bool dal_adapter_service_get_device_tag(
-+		struct adapter_service *as,
-+		struct graphics_object_id connector_object_id,
-+		uint32_t device_tag_index,
-+		struct connector_device_tag_info *info)
-+{
-+	if (BP_RESULT_OK == dal_bios_parser_get_device_tag(as->bios_parser,
-+			connector_object_id, device_tag_index, info))
-+		return true;
-+	else
-+		return false;
-+}
-+
-+/* Check if DeviceId is supported by ATOM_OBJECT_HEADER support info */
-+bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
-+		struct device_id id)
-+{
-+	return dal_bios_parser_is_device_id_supported(as->bios_parser, id);
-+}
-+
-+bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as)
-+{
-+	struct firmware_info fw_info;
-+	enum bp_result bp_result = dal_adapter_service_get_firmware_info(
-+		as, &fw_info);
-+	uint32_t disp_clk_limit =
-+		as->asic_cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN];
-+	if (BP_RESULT_OK == bp_result) {
-+		dal_logger_write(as->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ADAPTER_SERVICE,
-+			"Read firmware is NULL");
-+		return false;
-+	}
-+	if (fw_info.default_display_engine_pll_frequency < disp_clk_limit)
-+		return false;
-+	return true;
-+}
-+
-+bool dal_adapter_service_underscan_for_hdmi_only(struct adapter_service *as)
-+{
-+	return as->asic_cap->caps.UNDERSCAN_FOR_HDMI_ONLY;
-+}
-+/*
-+ * dal_adapter_service_get_clock_sources_num
-+ *
-+ * Get number of clock sources
-+ */
-+uint8_t dal_adapter_service_get_clock_sources_num(
-+	struct adapter_service *as)
-+{
-+	struct firmware_info fw_info;
-+	uint32_t max_clk_src = 0;
-+	uint32_t num = as->asic_cap->data[ASIC_DATA_CLOCKSOURCES_NUM];
-+
-+	/*
-+	 * Check is system supports the use of the External clock source
-+	 * as a clock source for DP
-+	 */
-+	enum bp_result bp_result =
-+			dal_bios_parser_get_firmware_info(as->bios_parser,
-+					&fw_info);
-+
-+	if (BP_RESULT_OK == bp_result &&
-+			fw_info.external_clock_source_frequency_for_dp != 0)
-+		++num;
-+
-+	/*
-+	 * Add clock source for wireless if supported
-+	 */
-+	num += (uint32_t)wireless_get_clocks_num(as);
-+
-+	/* Check the "max number of clock sources" feature */
-+	if (dal_adapter_service_get_feature_value(
-+			FEATURE_MAX_CLOCK_SOURCE_NUM,
-+			&max_clk_src,
-+			sizeof(uint32_t)))
-+		if ((max_clk_src != 0) && (max_clk_src < num))
-+			num = max_clk_src;
-+
-+	return num;
-+}
-+
-+/*
-+ * dal_adapter_service_get_func_controllers_num
-+ *
-+ * Get number of controllers
-+ */
-+uint8_t dal_adapter_service_get_func_controllers_num(
-+	struct adapter_service *as)
-+{
-+	uint32_t result =
-+		as->asic_cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM];
-+
-+	/* Check the "max num of controllers" feature,
-+	 * use it for debugging purposes only */
-+
-+	/* Limit number of controllers by OS */
-+
-+	struct asic_feature_flags flags;
-+
-+	flags.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-+
-+	if (flags.bits.LEGACY_CLIENT &&
-+		(result > LEGACY_MAX_NUM_OF_CONTROLLERS))
-+		result = LEGACY_MAX_NUM_OF_CONTROLLERS;
-+
-+	return result;
-+}
-+
-+/*
-+ * dal_adapter_service_is_feature_supported
-+ *
-+ * Return if a given feature is supported by the ASIC. The feature has to be
-+ * a boolean type.
-+ */
-+bool dal_adapter_service_is_feature_supported(
-+	enum adapter_feature_id feature_id)
-+{
-+	bool data = 0;
-+
-+	dal_adapter_service_get_feature_value(feature_id, &data, sizeof(bool));
-+
-+	return data;
-+}
-+
-+/**
-+ * Reports maximum number of confunctional non-DP displays.
-+ * Value can be overriden if FEATURE_REPORT_SINGLE_SELECTED_TIMING feature is
-+ * enabled.
-+ *
-+ * \return
-+ *     Maximum number of confunctional non-DP displays
-+ */
-+uint32_t dal_adapter_service_get_max_cofunc_non_dp_displays(void)
-+{
-+	uint32_t non_dp_displays = DEFAULT_NUM_COFUNC_NON_DP_DISPLAYS;
-+
-+	if (true == dal_adapter_service_get_feature_value(
-+			FEATURE_MAX_COFUNC_NON_DP_DISPLAYS,
-+			&non_dp_displays,
-+			sizeof(non_dp_displays))) {
-+		/* the cached value exist */
-+		/* TODO: add more logic as per-DAL2 */
-+	}
-+
-+	return non_dp_displays;
-+}
-+
-+uint32_t dal_adapter_service_get_single_selected_timing_signals(void)
-+{
-+	uint32_t signals_bitmap = 0;
-+
-+	if (dal_adapter_service_is_feature_supported(
-+			FEATURE_REPORT_SINGLE_SELECTED_TIMING)) {
-+		/* the cached value exist */
-+		/* TODO: add more logic as per-DAL2 */
-+		signals_bitmap = 0;
-+	}
-+
-+	return signals_bitmap;
-+}
-+
-+/*
-+ * dal_adapter_service_get_i2c_info
-+ *
-+ * Get I2C information from BIOS
-+ */
-+bool dal_adapter_service_get_i2c_info(
-+	struct adapter_service *as,
-+	struct graphics_object_id id,
-+	struct graphics_object_i2c_info *i2c_info)
-+{
-+	if (!i2c_info) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	return BP_RESULT_OK ==
-+		dal_bios_parser_get_i2c_info(as->bios_parser, id, i2c_info);
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_ddc
-+ *
-+ * Obtain DDC
-+ */
-+struct ddc *dal_adapter_service_obtain_ddc(
-+	struct adapter_service *as,
-+	struct graphics_object_id id)
-+{
-+	struct graphics_object_i2c_info i2c_info;
-+	struct gpio_ddc_hw_info hw_info;
-+
-+
-+	if (!dal_adapter_service_get_i2c_info(as, id, &i2c_info))
-+		return NULL;
-+
-+	hw_info.ddc_channel = i2c_info.i2c_line;
-+	hw_info.hw_supported = i2c_info.i2c_hw_assist;
-+
-+	return dal_gpio_service_create_ddc(
-+		as->gpio_service,
-+		i2c_info.gpio_info.clk_a_register_index,
-+		1 << i2c_info.gpio_info.clk_a_shift,
-+		&hw_info);
-+}
-+
-+/*
-+ * dal_adapter_service_release_ddc
-+ *
-+ * Release DDC
-+ */
-+void dal_adapter_service_release_ddc(
-+	struct adapter_service *as,
-+	struct ddc *ddc)
-+{
-+	dal_gpio_service_destroy_ddc(&ddc);
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_hpd_irq
-+ *
-+ * Obtain HPD interrupt request
-+ */
-+struct irq *dal_adapter_service_obtain_hpd_irq(
-+	struct adapter_service *as,
-+	struct graphics_object_id id)
-+{
-+	enum bp_result bp_result;
-+
-+	struct graphics_object_hpd_info hpd_info;
-+	struct gpio_pin_info pin_info;
-+
-+	if (!get_hpd_info(as, id, &hpd_info))
-+		return NULL;
-+
-+	bp_result = dal_bios_parser_get_gpio_pin_info(as->bios_parser,
-+		hpd_info.hpd_int_gpio_uid, &pin_info);
-+
-+	if (bp_result != BP_RESULT_OK) {
-+		ASSERT(bp_result == BP_RESULT_NORECORD);
-+		return NULL;
-+	}
-+
-+	return dal_gpio_service_create_irq(
-+		as->gpio_service,
-+		pin_info.offset,
-+		pin_info.mask);
-+}
-+
-+/*
-+ * dal_adapter_service_release_irq
-+ *
-+ * Release interrupt request
-+ */
-+void dal_adapter_service_release_irq(
-+	struct adapter_service *as,
-+	struct irq *irq)
-+{
-+	dal_gpio_service_destroy_irq(&irq);
-+}
-+
-+/*
-+ * dal_adapter_service_get_ss_info_num
-+ *
-+ * Get number of spread spectrum entries from BIOS
-+ */
-+uint32_t dal_adapter_service_get_ss_info_num(
-+	struct adapter_service *as,
-+	enum as_signal_type signal)
-+{
-+	return dal_bios_parser_get_ss_entry_number(as->bios_parser, signal);
-+}
-+
-+/*
-+ * dal_adapter_service_get_ss_info
-+ *
-+ * Get spread spectrum info from BIOS
-+ */
-+bool dal_adapter_service_get_ss_info(
-+	struct adapter_service *as,
-+	enum as_signal_type signal,
-+	uint32_t idx,
-+	struct spread_spectrum_info *info)
-+{
-+	enum bp_result bp_result =
-+		dal_bios_parser_get_spread_spectrum_info(
-+			as->bios_parser, signal, idx, info);
-+
-+	return BP_RESULT_OK == bp_result;
-+}
-+
-+/*
-+ * dal_adapter_service_get_integrated_info
-+ *
-+ * Get integrated information on BIOS
-+ */
-+bool dal_adapter_service_get_integrated_info(
-+	struct adapter_service *as,
-+	struct integrated_info *info)
-+{
-+	if (info == NULL || as->integrated_info == NULL)
-+		return false;
-+
-+	dc_service_memmove(info, as->integrated_info, sizeof(struct integrated_info));
-+
-+	return true;
-+}
-+
-+/*
-+ * dal_adapter_service_is_dfs_bypass_enabled
-+ *
-+ * Check if DFS bypass is enabled
-+ */
-+bool dal_adapter_service_is_dfs_bypass_enabled(
-+	struct adapter_service *as)
-+{
-+	if (as->integrated_info == NULL)
-+		return false;
-+	if ((as->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) &&
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_ENABLE_DFS_BYPASS))
-+		return true;
-+	else
-+		return false;
-+}
-+
-+/*
-+ * dal_adapter_service_get_sw_i2c_speed
-+ *
-+ * Get SW I2C speed
-+ */
-+uint32_t dal_adapter_service_get_sw_i2c_speed(
-+	struct adapter_service *as)
-+{
-+	/* TODO: only from ASIC caps. Feature key is not implemented*/
-+	return as->asic_cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ];
-+}
-+
-+/*
-+ * dal_adapter_service_get_hw_i2c_speed
-+ *
-+ * Get HW I2C speed
-+ */
-+uint32_t dal_adapter_service_get_hw_i2c_speed(
-+	struct adapter_service *as)
-+{
-+	/* TODO: only from ASIC caps. Feature key is not implemented*/
-+	return as->asic_cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ];
-+}
-+
-+/*
-+ * dal_adapter_service_get_mc_latency
-+ *
-+ * Get memory controller latency
-+ */
-+uint32_t dal_adapter_service_get_mc_latency(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_MC_LATENCY];
-+}
-+
-+/*
-+ * dal_adapter_service_get_asic_vram_bit_width
-+ *
-+ * Get the video RAM bit width set on the ASIC
-+ */
-+uint32_t dal_adapter_service_get_asic_vram_bit_width(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_VRAM_BITWIDTH];
-+}
-+
-+/*
-+ * dal_adapter_service_get_asic_bugs
-+ *
-+ * Get the bug flags set on this ASIC
-+ */
-+struct asic_bugs dal_adapter_service_get_asic_bugs(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->bugs;
-+}
-+
-+
-+struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
-+		struct adapter_service *as)
-+{
-+	return as->asic_cap->runtime_flags;
-+}
-+
-+/*
-+ * dal_adapter_service_get_line_buffer_size
-+ *
-+ * Get line buffer size
-+ */
-+uint32_t dal_adapter_service_get_line_buffer_size(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_LINEBUFFER_SIZE];
-+}
-+
-+/*
-+ * dal_adapter_service_get_bandwidth_tuning_params
-+ *
-+ * Get parameters for bandwidth tuning
-+ */
-+bool dal_adapter_service_get_bandwidth_tuning_params(
-+	struct adapter_service *as,
-+	union bandwidth_tuning_params *params)
-+{
-+	/* TODO: add implementation */
-+	/* note: data comes from runtime parameters */
-+	return false;
-+}
-+
-+/*
-+ * dal_adapter_service_get_feature_flags
-+ *
-+ * Get a copy of ASIC feature flags
-+ */
-+struct asic_feature_flags dal_adapter_service_get_feature_flags(
-+	struct adapter_service *as)
-+{
-+	struct asic_feature_flags result = { { 0 } };
-+
-+	if (!as) {
-+		ASSERT_CRITICAL(false);
-+		return result;
-+	}
-+
-+	result.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-+
-+	return result;
-+}
-+
-+/*
-+ * dal_adapter_service_get_dram_bandwidth_efficiency
-+ *
-+ * Get efficiency of DRAM
-+ */
-+uint32_t dal_adapter_service_get_dram_bandwidth_efficiency(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY];
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_gpio
-+ *
-+ * Obtain GPIO
-+ */
-+struct gpio *dal_adapter_service_obtain_gpio(
-+	struct adapter_service *as,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	return dal_gpio_service_create_gpio_ex(
-+		as->gpio_service, id, en,
-+		GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+}
-+
-+/*
-+ * dal_adapter_service_obtain_stereo_gpio
-+ *
-+ * Obtain GPIO for stereo3D
-+ */
-+struct gpio *dal_adapter_service_obtain_stereo_gpio(
-+	struct adapter_service *as)
-+{
-+	const bool have_param_stereo_gpio = false;
-+
-+	struct asic_feature_flags result;
-+
-+	result.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-+
-+	/* Case 1 : Workstation stereo */
-+	if (result.bits.WORKSTATION_STEREO)
-+		/* "active low" <--> "default 3d right eye polarity" = false */
-+		return dal_gpio_service_create_gpio_ex(
-+			as->gpio_service, GPIO_ID_GENERIC, GPIO_GENERIC_A,
-+			GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW);
-+	/* Case 2 : runtime parameter override for sideband stereo */
-+	else if (have_param_stereo_gpio) {
-+		/* TODO implement */
-+		return NULL;
-+	/* Case 3 : VBIOS gives us GPIO for sideband stereo */
-+	} else {
-+		const struct graphics_object_id id =
-+			dal_graphics_object_id_init(
-+				GENERIC_ID_STEREO,
-+				ENUM_ID_1,
-+				OBJECT_TYPE_GENERIC);
-+
-+		struct bp_gpio_cntl_info cntl_info;
-+		struct gpio_pin_info pin_info;
-+
-+		/* Get GPIO record for this object.
-+		 * Stereo GPIO record should have exactly one entry
-+		 * where active state defines stereosync polarity */
-+		if (1 != dal_bios_parser_get_gpio_record(
-+			as->bios_parser, id, &cntl_info, 1)) {
-+			return NULL;
-+		} else if (BP_RESULT_OK != dal_bios_parser_get_gpio_pin_info(
-+			as->bios_parser, cntl_info.id, &pin_info)) {
-+			/*ASSERT_CRITICAL(false);*/
-+			return NULL;
-+		} else
-+			return dal_gpio_service_create_gpio_ex(
-+				as->gpio_service,
-+				pin_info.offset, pin_info.mask,
-+				cntl_info.state);
-+	}
-+}
-+
-+/*
-+ * dal_adapter_service_release_gpio
-+ *
-+ * Release GPIO
-+ */
-+void dal_adapter_service_release_gpio(
-+	struct adapter_service *as,
-+	struct gpio *gpio)
-+{
-+	dal_gpio_service_destroy_gpio(&gpio);
-+}
-+
-+/*
-+ * dal_adapter_service_get_firmware_info
-+ *
-+ * Get firmware information from BIOS
-+ */
-+bool dal_adapter_service_get_firmware_info(
-+	struct adapter_service *as,
-+	struct firmware_info *info)
-+{
-+	return dal_bios_parser_get_firmware_info(as->bios_parser, info) ==
-+		BP_RESULT_OK;
-+}
-+
-+/*
-+ * dal_adapter_service_get_audio_support
-+ *
-+ * Get information on audio support
-+ */
-+union audio_support dal_adapter_service_get_audio_support(
-+	struct adapter_service *as)
-+{
-+	return dal_adapter_service_hw_ctx_get_audio_support(as->hw_ctx);
-+}
-+
-+/*
-+ * dal_adapter_service_get_stream_engines_num
-+ *
-+ * Get number of stream engines
-+ */
-+uint8_t dal_adapter_service_get_stream_engines_num(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_DIGFE_NUM];
-+}
-+
-+/*
-+ * dal_adapter_service_get_feature_value
-+ *
-+ * Get the cached value of a given feature. This value can be a boolean, int,
-+ * or characters.
-+ */
-+bool dal_adapter_service_get_feature_value(
-+	const enum adapter_feature_id feature_id,
-+	void *data,
-+	uint32_t size)
-+{
-+	uint32_t entry_idx = 0;
-+	uint32_t set_idx = 0;
-+	uint32_t set_internal_idx = 0;
-+
-+	if (feature_id >= FEATURE_MAXIMUM || feature_id <= FEATURE_UNKNOWN) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if (data == NULL) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	entry_idx = lookup_feature_entry(feature_id);
-+	set_idx = (uint32_t)((feature_id - 1)/32);
-+	set_internal_idx = (uint32_t)((feature_id - 1) % 32);
-+
-+	if (entry_idx >= get_feature_entries_num()) {
-+		/* Cannot find this entry */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if (feature_entry_table[entry_idx].is_boolean_type) {
-+		if (size != sizeof(bool)) {
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+
-+		*(bool *)data = get_bool_value(adapter_feature_set[set_idx],
-+				set_internal_idx);
-+	} else {
-+		if (size != sizeof(uint32_t)) {
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+
-+		*(uint32_t *)data = adapter_feature_set[set_idx];
-+	}
-+
-+	return true;
-+}
-+
-+/*
-+ * dal_adapter_service_get_memory_type_multiplier
-+ *
-+ * Get multiplier for the memory type
-+ */
-+uint32_t dal_adapter_service_get_memory_type_multiplier(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER];
-+}
-+
-+/*
-+ * dal_adapter_service_get_bios_parser
-+ *
-+ * Get BIOS parser handler
-+ */
-+struct bios_parser *dal_adapter_service_get_bios_parser(
-+	struct adapter_service *as)
-+{
-+	return as->bios_parser;
-+}
-+
-+/*
-+ * dal_adapter_service_get_i2caux
-+ *
-+ * Get i2c aux handler
-+ */
-+struct i2caux *dal_adapter_service_get_i2caux(
-+	struct adapter_service *as)
-+{
-+	return as->i2caux;
-+}
-+
-+bool dal_adapter_service_initialize_hw_data(
-+	struct adapter_service *as)
-+{
-+	return as->hw_ctx->funcs->power_up(as->hw_ctx);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_fake_path_resource(
-+	struct adapter_service *as,
-+	uint32_t index)
-+{
-+	return as->hw_ctx->funcs->enum_fake_path_resource(as->hw_ctx, index);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_stereo_sync_object(
-+	struct adapter_service *as,
-+	uint32_t index)
-+{
-+	return as->hw_ctx->funcs->enum_stereo_sync_object(as->hw_ctx, index);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_sync_output_object(
-+	struct adapter_service *as,
-+	uint32_t index)
-+{
-+	return as->hw_ctx->funcs->enum_sync_output_object(as->hw_ctx, index);
-+}
-+
-+struct graphics_object_id dal_adapter_service_enum_audio_object(
-+	struct adapter_service *as,
-+	uint32_t index)
-+{
-+	return as->hw_ctx->funcs->enum_audio_object(as->hw_ctx, index);
-+}
-+
-+
-+void dal_adapter_service_update_audio_connectivity(
-+	struct adapter_service *as,
-+	uint32_t number_of_audio_capable_display_path)
-+{
-+	as->hw_ctx->funcs->update_audio_connectivity(
-+		as->hw_ctx,
-+		number_of_audio_capable_display_path,
-+		dal_adapter_service_get_controllers_num(as));
-+}
-+
-+bool dal_adapter_service_has_embedded_display_connector(
-+	struct adapter_service *as)
-+{
-+	uint8_t index;
-+	uint8_t num_connectors = dal_adapter_service_get_connectors_num(as);
-+
-+	if (num_connectors == 0 || num_connectors > ENUM_ID_COUNT)
-+		return false;
-+
-+	for (index = 0; index < num_connectors; index++) {
-+		struct graphics_object_id obj_id =
-+			dal_adapter_service_get_connector_obj_id(as, index);
-+		enum connector_id connector_id =
-+			dal_graphics_object_id_get_connector_id(obj_id);
-+
-+		if ((connector_id == CONNECTOR_ID_LVDS) ||
-+				(connector_id == CONNECTOR_ID_EDP))
-+			return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool dal_adapter_service_get_embedded_panel_info(
-+	struct adapter_service *as,
-+	struct embedded_panel_info *info)
-+{
-+	enum bp_result result;
-+
-+	if (info == NULL)
-+		/*TODO: add DALASSERT_MSG here*/
-+		return false;
-+
-+	result = dal_bios_parser_get_embedded_panel_info(
-+		as->bios_parser, info);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+bool dal_adapter_service_enum_embedded_panel_patch_mode(
-+	struct adapter_service *as,
-+	uint32_t index,
-+	struct embedded_panel_patch_mode *mode)
-+{
-+	enum bp_result result;
-+
-+	if (mode == NULL)
-+		/*TODO: add DALASSERT_MSG here*/
-+		return false;
-+
-+	result = dal_bios_parser_enum_embedded_panel_patch_mode(
-+		as->bios_parser, index, mode);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+bool dal_adapter_service_get_faked_edid_len(
-+	struct adapter_service *as,
-+	uint32_t *len)
-+{
-+	enum bp_result result;
-+
-+	result = dal_bios_parser_get_faked_edid_len(
-+		as->bios_parser,
-+		len);
-+	return result == BP_RESULT_OK;
-+}
-+
-+bool dal_adapter_service_get_faked_edid_buf(
-+	struct adapter_service *as,
-+	uint8_t *buf,
-+	uint32_t len)
-+{
-+	enum bp_result result;
-+
-+	result = dal_bios_parser_get_faked_edid_buf(
-+		as->bios_parser,
-+		buf,
-+		len);
-+	return result == BP_RESULT_OK;
-+
-+}
-+
-+/*
-+ * dal_adapter_service_is_fusion
-+ *
-+ * Is this Fusion ASIC
-+ */
-+bool dal_adapter_service_is_fusion(struct adapter_service *as)
-+{
-+	return as->asic_cap->caps.IS_FUSION;
-+}
-+
-+/*
-+ * dal_adapter_service_is_dfsbyass_dynamic
-+ *
-+ *
-+ **/
-+bool dal_adapter_service_is_dfsbyass_dynamic(struct adapter_service *as)
-+{
-+	return as->asic_cap->caps.DFSBYPASS_DYNAMIC_SUPPORT;
-+}
-+
-+/*
-+ * dal_adapter_service_should_optimize
-+ *
-+ * @brief Reports whether driver settings allow requested optimization
-+ *
-+ * @param
-+ * as: adapter service handler
-+ * feature: for which optimization is validated
-+ *
-+ * @return
-+ * true if requested feature can be optimized
-+ */
-+bool dal_adapter_service_should_optimize(
-+		struct adapter_service *as, enum optimization_feature feature)
-+{
-+	uint32_t supported_optimization = 0;
-+	struct dal_asic_runtime_flags flags;
-+
-+	if (!dal_adapter_service_get_feature_value(FEATURE_OPTIMIZATION,
-+			&supported_optimization, sizeof(uint32_t)))
-+		return false;
-+
-+	/* Retrieve ASIC runtime flags */
-+	flags = dal_adapter_service_get_asic_runtime_flags(as);
-+
-+	/* Check runtime flags against different optimization features */
-+	switch (feature) {
-+	case OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:
-+		if (!flags.flags.bits.OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT)
-+			return false;
-+		break;
-+
-+	case OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME:
-+		if (as->integrated_info == NULL ||
-+				!flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME)
-+			return false;
-+		break;
-+	case OF_SKIP_POWER_DOWN_INACTIVE_ENCODER:
-+		if (!dal_adapter_service_get_asic_runtime_flags(as).flags.bits.
-+			SKIP_POWER_DOWN_ON_RESUME)
-+			return false;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return (supported_optimization & feature) != 0;
-+}
-+
-+/*
-+ * dal_adapter_service_is_in_accelerated_mode
-+ *
-+ * @brief Determine if driver is in accelerated mode
-+ *
-+ * @param
-+ * as: Adapter Service handler
-+ *
-+ * @out
-+ * True if driver is in accelerated mode, false otherwise.
-+ */
-+bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as)
-+{
-+	return dal_bios_parser_is_accelerated_mode(as->bios_parser);
-+}
-+
-+struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
-+	struct adapter_service *as,
-+	struct graphics_object_i2c_info *info)
-+{
-+	struct gpio_ddc_hw_info hw_info = {
-+		info->i2c_hw_assist,
-+		info->i2c_line };
-+	return dal_gpio_service_create_ddc(as->gpio_service,
-+		info->gpio_info.clk_a_register_index,
-+		(1 << info->gpio_info.clk_a_shift), &hw_info);
-+}
-+
-+struct bdf_info dal_adapter_service_get_adapter_info(struct adapter_service *as)
-+{
-+	return as->bdf_info;
-+}
-+
-+/*
-+ * dal_adapter_service_should_psr_skip_wait_for_pll_lock
-+ *
-+ * @brief Determine if this ASIC needs to wait on PLL lock bit
-+ *
-+ * @param
-+ * as: Adapter Service handle
-+ *
-+ * @out
-+ * True if ASIC does not need to wait for PLL lock bit, i.e. skip the wait.
-+ */
-+bool dal_adapter_service_should_psr_skip_wait_for_pll_lock(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->caps.SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT;
-+}
-+
-+bool dal_adapter_service_is_lid_open(struct adapter_service *as)
-+{
-+	bool is_lid_open = false;
-+	struct platform_info_params params;
-+
-+	params.data = &is_lid_open;
-+	params.method = PM_GET_LID_STATE;
-+
-+	if ((PM_GET_LID_STATE & as->platform_methods_mask) &&
-+		dal_get_platform_info(as->ctx, &params))
-+		return is_lid_open;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	return dal_bios_parser_is_lid_open(as->bios_parser);
-+#else
-+	return false;
-+#endif
-+}
-+
-+bool dal_adapter_service_get_panel_backlight_default_levels(
-+	struct adapter_service *as,
-+	struct panel_backlight_levels *levels)
-+{
-+	if (!as->backlight_caps_initialized)
-+		return false;
-+
-+	levels->ac_level_percentage = as->ac_level_percentage;
-+	levels->dc_level_percentage = as->dc_level_percentage;
-+	return true;
-+}
-+
-+bool dal_adapter_service_get_panel_backlight_boundaries(
-+	struct adapter_service *as,
-+	struct panel_backlight_boundaries *boundaries)
-+{
-+	if (!as->backlight_caps_initialized)
-+		return false;
-+	if (boundaries != NULL) {
-+		boundaries->min_signal_level = as->backlight_8bit_lut[0];
-+		boundaries->max_signal_level =
-+			as->backlight_8bit_lut[SIZEOF_BACKLIGHT_LUT - 1];
-+		return true;
-+	}
-+	return false;
-+}
-+
-+
-+uint32_t dal_adapter_service_get_view_port_pixel_granularity(
-+	struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY];
-+}
-+
-+/**
-+ * Get number of paths per DP 1.2 connector from the runtime parameter if it
-+ * exists.
-+ * A check to see if MST is supported for the generation of ASIC is done
-+ *
-+ * \return
-+ *    Number of paths per DP 1.2 connector is exists in runtime parameters
-+ *    or ASIC cap
-+ */
-+uint32_t dal_adapter_service_get_num_of_path_per_dp_mst_connector(
-+		struct adapter_service *as)
-+{
-+	if (as->asic_cap->caps.DP_MST_SUPPORTED == 0) {
-+		/* ASIC doesn't support DP MST at all */
-+		return 0;
-+	}
-+
-+	return as->asic_cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR];
-+}
-+
-+uint32_t dal_adapter_service_get_num_of_underlays(
-+		struct adapter_service *as)
-+{
-+	return as->asic_cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES];
-+}
-+
-+bool dal_adapter_service_get_encoder_cap_info(
-+		struct adapter_service *as,
-+		struct graphics_object_id id,
-+		struct graphics_object_encoder_cap_info *info)
-+{
-+	struct bp_encoder_cap_info bp_cap_info = {0};
-+	enum bp_result result;
-+
-+	if (NULL == info) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	/*
-+	 * Retrieve Encoder Capability Information from VBIOS and store the
-+	 * call result (success or fail)
-+	 * Info from VBIOS about HBR2 has two fields:
-+	 *
-+	 * - dpHbr2Cap: indicates supported/not supported by HW Encoder
-+	 * - dpHbr2En : indicates DP spec compliant/not compliant
-+	 */
-+	result = dal_bios_parser_get_encoder_cap_info(
-+			as->bios_parser,
-+			id,
-+			&bp_cap_info);
-+
-+	/* Set dp_hbr2_validated flag (it's equal to Enable) */
-+	info->dp_hbr2_validated = bp_cap_info.DP_HBR2_EN;
-+
-+	if (result == BP_RESULT_OK) {
-+		info->dp_hbr2_cap = bp_cap_info.DP_HBR2_CAP;
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool dal_adapter_service_is_mc_tuning_req(struct adapter_service *as)
-+{
-+	return as->asic_cap->caps.NEED_MC_TUNING ? true : false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-new file mode 100644
-index 0000000..25ac648
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -0,0 +1,67 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ADAPTER_SERVICE_H__
-+#define __DAL_ADAPTER_SERVICE_H__
-+
-+/* Include */
-+#include "include/adapter_service_interface.h"
-+#include "wireless_data_source.h"
-+
-+/*
-+ * Forward declaration
-+ */
-+struct gpio_service;
-+struct asic_cap;
-+
-+/* Adapter service */
-+struct adapter_service {
-+	struct dc_context *ctx;
-+	struct asic_capability *asic_cap;
-+	struct bios_parser *bios_parser;
-+	struct gpio_service *gpio_service;
-+	struct i2caux *i2caux;
-+	struct wireless_data wireless_data;
-+	struct hw_ctx_adapter_service *hw_ctx;
-+	struct integrated_info *integrated_info;
-+	struct bdf_info bdf_info;
-+	uint32_t platform_methods_mask;
-+	uint32_t ac_level_percentage;
-+	uint32_t dc_level_percentage;
-+	uint32_t backlight_caps_initialized;
-+	uint32_t backlight_8bit_lut[SIZEOF_BACKLIGHT_LUT];
-+};
-+
-+/* Type of feature with its runtime parameter and default value */
-+struct feature_source_entry {
-+	enum adapter_feature_id feature_id;
-+	uint32_t default_value;
-+	bool is_boolean_type;
-+};
-+
-+/* Stores entire ASIC features by sets */
-+extern uint32_t adapter_feature_set[];
-+
-+#endif /* __DAL_ADAPTER_SERVICE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-new file mode 100644
-index 0000000..31c2aab
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-@@ -0,0 +1,303 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "../hw_ctx_adapter_service.h"
-+
-+#include "hw_ctx_adapter_service_dce110.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/grph_object_id.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x4819
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static const struct graphics_object_id invalid_go = {
-+	0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN, 0
-+};
-+
-+/* Macro */
-+#define AUDIO_STRAPS_HDMI_ENABLE 0x2
-+
-+#define FROM_HW_CTX(ptr) \
-+	container_of((ptr), struct hw_ctx_adapter_service_dce110, base)
-+
-+static const uint32_t audio_index_reg_offset[] = {
-+	/*CZ has 3 DIGs but 4 audio endpoints*/
-+	mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
-+};
-+
-+static const uint32_t audio_data_reg_offset[] = {
-+	mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+};
-+
-+enum {
-+	MAX_NUMBER_OF_AUDIO_PINS = 4
-+};
-+
-+static void destruct(
-+	struct hw_ctx_adapter_service_dce110 *hw_ctx)
-+{
-+	/* There is nothing to destruct at the moment */
-+	dal_adapter_service_destruct_hw_ctx(&hw_ctx->base);
-+}
-+
-+static void destroy(
-+	struct hw_ctx_adapter_service *ptr)
-+{
-+	struct hw_ctx_adapter_service_dce110 *hw_ctx =
-+		FROM_HW_CTX(ptr);
-+
-+	destruct(hw_ctx);
-+
-+	dc_service_free(ptr->ctx, hw_ctx);
-+}
-+
-+/*
-+ * enum_audio_object
-+ *
-+ * @brief enumerate audio object
-+ *
-+ * @param
-+ * const struct hw_ctx_adapter_service *hw_ctx - [in] provides num of endpoints
-+ * uint32_t index - [in] audio index
-+ *
-+ * @return
-+ * grphic object id
-+ */
-+static struct graphics_object_id enum_audio_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	uint32_t number_of_connected_audio_endpoints =
-+		FROM_HW_CTX(hw_ctx)->number_of_connected_audio_endpoints;
-+
-+	if (index >= number_of_connected_audio_endpoints ||
-+			number_of_connected_audio_endpoints == 0)
-+		return invalid_go;
-+	else
-+		return dal_graphics_object_id_init(
-+			AUDIO_ID_INTERNAL_AZALIA,
-+			(enum object_enum_id)(index + 1),
-+			OBJECT_TYPE_AUDIO);
-+}
-+
-+static uint32_t get_number_of_connected_audio_endpoints_multistream(
-+		struct dc_context *ctx)
-+{
-+	uint32_t num_connected_audio_endpoints = 0;
-+	uint32_t i;
-+	uint32_t default_config =
-+	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT;
-+
-+	/* find the total number of streams available via the
-+	 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
-+	 * registers (one for each pin) starting from pin 1
-+	 * up to the max number of audio pins.
-+	 * We stop on the first pin where
-+	 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
-+	 */
-+	for (i = 0; i < MAX_NUMBER_OF_AUDIO_PINS; i++) {
-+		uint32_t value = 0;
-+
-+		set_reg_field_value(value,
-+			default_config,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dal_write_reg(ctx, audio_index_reg_offset[i], value);
-+
-+		value = 0;
-+		value = dal_read_reg(ctx, audio_data_reg_offset[i]);
-+
-+		/* 1 means not supported*/
-+		if (get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
-+		PORT_CONNECTIVITY) == 1)
-+			break;
-+
-+		num_connected_audio_endpoints++;
-+	}
-+
-+	return num_connected_audio_endpoints;
-+
-+}
-+
-+/*
-+ * get_number_of_connected_audio_endpoints
-+ */
-+static uint32_t get_number_of_connected_audio_endpoints(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	uint32_t addr = mmCC_DC_HDMI_STRAPS;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	if (hw_ctx->cached_audio_straps == AUDIO_STRAPS_NOT_ALLOWED)
-+		/* audio straps indicate no audio supported */
-+		return 0;
-+
-+	value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+	field = get_reg_field_value(
-+			value, CC_DC_HDMI_STRAPS, AUDIO_STREAM_NUMBER);
-+	if (field == 1)
-+		/* multi streams not supported */
-+		return 1;
-+	else if (field == 0)
-+		/* multi streams supported */
-+		return get_number_of_connected_audio_endpoints_multistream(
-+				hw_ctx->ctx);
-+
-+	/* unexpected value */
-+	ASSERT_CRITICAL(false);
-+	return field;
-+}
-+
-+
-+/*
-+ * power_up
-+ *
-+ * @brief
-+ * Determine and cache audio support from register.
-+ *
-+ * @param
-+ * struct hw_ctx_adapter_service *hw_ctx - [in] adapter service hw context
-+ *
-+ * @return
-+ * true if succeed, false otherwise
-+ */
-+static bool power_up(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	struct hw_ctx_adapter_service_dce110 *hw_ctx_dce11 =
-+			FROM_HW_CTX(hw_ctx);
-+	/* Allow DP audio all the time
-+	 * without additional pinstrap check on Fusion */
-+
-+
-+	{
-+		uint32_t value = 0;
-+		uint32_t field = 0;
-+
-+		value = dal_read_reg(hw_ctx->ctx, mmCC_DC_HDMI_STRAPS);
-+		field = get_reg_field_value(
-+				value, CC_DC_HDMI_STRAPS, HDMI_DISABLE);
-+
-+		if (field == 0) {
-+			hw_ctx->cached_audio_straps = AUDIO_STRAPS_DP_HDMI_AUDIO;
-+		} else {
-+			value = dal_read_reg(
-+					hw_ctx->ctx, mmDC_PINSTRAPS);
-+			field = get_reg_field_value(
-+						value,
-+						DC_PINSTRAPS,
-+						DC_PINSTRAPS_AUDIO);
-+
-+			if (field & AUDIO_STRAPS_HDMI_ENABLE)
-+				hw_ctx->cached_audio_straps =
-+					AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE;
-+			else
-+				hw_ctx->cached_audio_straps =
-+						AUDIO_STRAPS_DP_AUDIO_ALLOWED;
-+		}
-+
-+	}
-+
-+	/* get the number of connected audio endpoints */
-+	hw_ctx_dce11->number_of_connected_audio_endpoints =
-+		get_number_of_connected_audio_endpoints(hw_ctx);
-+
-+	return true;
-+}
-+
-+static void update_audio_connectivity(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t number_of_audio_capable_display_path,
-+	uint32_t number_of_controllers)
-+{
-+	/* this one should be empty on DCE110 */
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+	.destroy = destroy,
-+	.power_up = power_up,
-+	.enum_fake_path_resource = NULL,
-+	.enum_stereo_sync_object = NULL,
-+	.enum_sync_output_object = NULL,
-+	.enum_audio_object = enum_audio_object,
-+	.update_audio_connectivity = update_audio_connectivity
-+};
-+
-+static bool construct(
-+	struct hw_ctx_adapter_service_dce110 *hw_ctx,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_adapter_service_construct_hw_ctx(&hw_ctx->base, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	hw_ctx->base.funcs = &funcs;
-+	hw_ctx->number_of_connected_audio_endpoints = 0;
-+
-+	return true;
-+}
-+
-+struct hw_ctx_adapter_service *
-+	dal_adapter_service_create_hw_ctx_dce110(
-+			struct dc_context *ctx)
-+{
-+	struct hw_ctx_adapter_service_dce110 *hw_ctx =
-+			dc_service_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce110));
-+
-+	if (!hw_ctx) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(hw_ctx, ctx))
-+		return &hw_ctx->base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, hw_ctx);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-new file mode 100644
-index 0000000..092b671
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__
-+
-+struct hw_ctx_adapter_service_dce110 {
-+	struct hw_ctx_adapter_service base;
-+	uint32_t number_of_connected_audio_endpoints;
-+};
-+
-+struct hw_ctx_adapter_service *
-+	dal_adapter_service_create_hw_ctx_dce110(
-+			struct dc_context *ctx);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__ */
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-new file mode 100644
-index 0000000..5fa886f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-@@ -0,0 +1,164 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/adapter_service_types.h"
-+#include "include/grph_object_id.h"
-+#include "hw_ctx_adapter_service.h"
-+
-+static const struct graphics_object_id invalid_go = {
-+	0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN
-+};
-+
-+static void destroy(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	/* Attention!
-+	 * You must override impl method in derived class */
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static bool power_up(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	/* Attention!
-+	 * You must override impl method in derived class */
-+	BREAK_TO_DEBUGGER();
-+
-+	return false;
-+}
-+
-+static struct graphics_object_id enum_fake_path_resource(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_stereo_sync_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_sync_output_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_audio_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	/* by default, we only allow one audio */
-+
-+	if (index > 0)
-+		return invalid_go;
-+	else if (hw_ctx->cached_audio_straps == AUDIO_STRAPS_NOT_ALLOWED)
-+		return invalid_go;
-+	else
-+		return dal_graphics_object_id_init(
-+			AUDIO_ID_INTERNAL_AZALIA,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_AUDIO);
-+}
-+
-+static void update_audio_connectivity(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t number_of_audio_capable_display_path,
-+	uint32_t number_of_controllers)
-+{
-+	/* Attention!
-+	 * You must override impl method in derived class */
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+	destroy,
-+	power_up,
-+	enum_fake_path_resource,
-+	enum_stereo_sync_object,
-+	enum_sync_output_object,
-+	enum_audio_object,
-+	update_audio_connectivity
-+};
-+
-+bool dal_adapter_service_construct_hw_ctx(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	struct dc_context *ctx)
-+{
-+
-+	hw_ctx->ctx = ctx;
-+	hw_ctx->funcs = &funcs;
-+	hw_ctx->cached_audio_straps = AUDIO_STRAPS_NOT_ALLOWED;
-+
-+	return true;
-+}
-+
-+union audio_support dal_adapter_service_hw_ctx_get_audio_support(
-+	const struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	union audio_support result;
-+
-+	result.raw = 0;
-+
-+	switch (hw_ctx->cached_audio_straps) {
-+	case AUDIO_STRAPS_DP_HDMI_AUDIO:
-+		result.bits.HDMI_AUDIO_NATIVE = true;
-+		/* do not break ! */
-+	case AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE:
-+		result.bits.HDMI_AUDIO_ON_DONGLE = true;
-+		/* do not break ! */
-+	case AUDIO_STRAPS_DP_AUDIO_ALLOWED:
-+		result.bits.DP_AUDIO = true;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+void dal_adapter_service_destruct_hw_ctx(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	/* There is nothing to destruct at the moment */
-+}
-+
-+void dal_adapter_service_destroy_hw_ctx(
-+	struct hw_ctx_adapter_service **ptr)
-+{
-+	if (!ptr || !*ptr) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	(*ptr)->funcs->destroy(*ptr);
-+
-+	*ptr = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h
-new file mode 100644
-index 0000000..f98c2d4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h
-@@ -0,0 +1,86 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_H__
-+
-+enum audio_straps {
-+	AUDIO_STRAPS_NOT_ALLOWED = 0,
-+	AUDIO_STRAPS_DP_AUDIO_ALLOWED,
-+	AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE,
-+	AUDIO_STRAPS_DP_HDMI_AUDIO
-+};
-+
-+struct hw_ctx_adapter_service;
-+
-+struct hw_ctx_adapter_service_funcs {
-+	void (*destroy)(
-+		struct hw_ctx_adapter_service *hw_ctx);
-+	/* Initializes relevant HW registers
-+	 * and caches relevant data from HW registers */
-+	bool (*power_up)(
-+		struct hw_ctx_adapter_service *hw_ctx);
-+	/* Enumerate fake path resources */
-+	struct graphics_object_id (*enum_fake_path_resource)(
-+		const struct hw_ctx_adapter_service *hw_ctx,
-+		uint32_t index);
-+	/* Enumerate stereo sync objects */
-+	struct graphics_object_id (*enum_stereo_sync_object)(
-+		const struct hw_ctx_adapter_service *hw_ctx,
-+		uint32_t index);
-+	/* Enumerate (H/V) sync output objects */
-+	struct graphics_object_id (*enum_sync_output_object)(
-+		const struct hw_ctx_adapter_service *hw_ctx,
-+		uint32_t index);
-+	/* Enumerate audio objects */
-+	struct graphics_object_id (*enum_audio_object)(
-+		const struct hw_ctx_adapter_service *hw_ctx,
-+		uint32_t index);
-+	void (*update_audio_connectivity)(
-+		struct hw_ctx_adapter_service *hw_ctx,
-+		uint32_t number_of_audio_capable_display_path,
-+		uint32_t number_of_controllers);
-+};
-+
-+struct hw_ctx_adapter_service {
-+	struct dc_context *ctx;
-+	const struct hw_ctx_adapter_service_funcs *funcs;
-+	enum audio_straps cached_audio_straps;
-+};
-+
-+bool dal_adapter_service_construct_hw_ctx(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	struct dc_context *ctx);
-+
-+union audio_support dal_adapter_service_hw_ctx_get_audio_support(
-+	const struct hw_ctx_adapter_service *hw_ctx);
-+
-+void dal_adapter_service_destruct_hw_ctx(
-+	struct hw_ctx_adapter_service *hw_ctx);
-+
-+void dal_adapter_service_destroy_hw_ctx(
-+	struct hw_ctx_adapter_service **ptr);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-new file mode 100644
-index 0000000..dcb885d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-@@ -0,0 +1,209 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#include "dal_services.h"
-+#include "adapter_service.h"
-+#include "wireless_data_source.h"
-+
-+#include "atom.h"
-+
-+/*construct wireless data*/
-+bool wireless_data_init(struct wireless_data *data,
-+		struct bios_parser *bp,
-+		struct wireless_init_data *init_data)
-+{
-+	struct firmware_info info;
-+
-+	if (data == NULL || bp == NULL || init_data == NULL) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	data->miracast_connector_enable = false;
-+	data->wireless_disp_path_enable = false;
-+	data->wireless_enable = false;
-+
-+	/* Wireless it not supported if VCE is not supported */
-+	if (!init_data->vce_supported)
-+		return true;
-+
-+	if (init_data->miracast_target_required)
-+		data->miracast_connector_enable = true;
-+
-+	/*
-+	 * If override is in place for platform support, we will both
-+	 * enable wireless display as a feature (i.e. CCC aspect) and
-+	 * enable the wireless display path without any further checks.
-+	 */
-+	if (init_data->platform_override) {
-+		data->wireless_enable = true;
-+		data->wireless_disp_path_enable = true;
-+	} else {
-+		/*
-+		 * Check if SBIOS sets remote display enable, exposed
-+		 * through VBIOS. This is only valid for APU, not dGPU
-+		 */
-+		dal_bios_parser_get_firmware_info(bp, &info);
-+
-+		if ((REMOTE_DISPLAY_ENABLE ==
-+			info.remote_display_config) &&
-+				init_data->fusion) {
-+			data->wireless_enable = true;
-+			data->wireless_disp_path_enable = true;
-+		}
-+	}
-+
-+	/*
-+	 * If remote display path override is enabled, we enable just the
-+	 * remote display path. This is mainly used for testing purposes
-+	 */
-+	if (init_data->remote_disp_path_override)
-+		data->wireless_disp_path_enable = true;
-+
-+	return true;
-+}
-+
-+uint8_t wireless_get_clocks_num(
-+	struct adapter_service *as)
-+{
-+	if (as->wireless_data.wireless_enable ||
-+		as->wireless_data.wireless_disp_path_enable)
-+		return 1;
-+	else
-+		return 0;
-+}
-+
-+static uint8_t wireless_get_encoders_num(
-+	struct adapter_service *as)
-+{
-+	if (as->wireless_data.wireless_enable ||
-+		as->wireless_data.wireless_disp_path_enable)
-+		return 1;
-+	else
-+		return 0;
-+}
-+
-+uint8_t wireless_get_connectors_num(
-+	struct adapter_service *as)
-+{
-+	uint8_t wireless_connectors_num = 0;
-+
-+	if (as->wireless_data.wireless_enable &&
-+		as->wireless_data.miracast_connector_enable)
-+		wireless_connectors_num++;
-+
-+	if (as->wireless_data.wireless_disp_path_enable)
-+		wireless_connectors_num++;
-+
-+	return wireless_connectors_num;
-+}
-+
-+struct graphics_object_id wireless_get_connector_id(
-+	struct adapter_service *as,
-+	uint8_t index)
-+{
-+	struct graphics_object_id unknown_object_id =
-+			dal_graphics_object_id_init(
-+				0,
-+				ENUM_ID_UNKNOWN,
-+				OBJECT_TYPE_UNKNOWN);
-+
-+	if (!as->wireless_data.wireless_enable &&
-+		!as->wireless_data.wireless_disp_path_enable)
-+		return unknown_object_id;
-+
-+	else if (!as->wireless_data.miracast_connector_enable)
-+		return dal_graphics_object_id_init(
-+			CONNECTOR_ID_WIRELESS,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_CONNECTOR);
-+
-+	switch (index) {
-+	case 0:
-+		return dal_graphics_object_id_init(
-+			CONNECTOR_ID_WIRELESS,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_CONNECTOR);
-+		break;
-+	case 1:
-+		return dal_graphics_object_id_init(
-+			CONNECTOR_ID_MIRACAST,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_CONNECTOR);
-+		break;
-+	default:
-+		return unknown_object_id;
-+	}
-+}
-+
-+uint8_t wireless_get_srcs_num(
-+	struct adapter_service *as,
-+	struct graphics_object_id id)
-+{
-+	switch (id.type) {
-+	case OBJECT_TYPE_CONNECTOR:
-+		return wireless_get_encoders_num(as);
-+	case OBJECT_TYPE_ENCODER:
-+		return 1;
-+
-+	default:
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+struct graphics_object_id wireless_get_src_obj_id(
-+	struct adapter_service *as,
-+	struct graphics_object_id id,
-+	uint8_t index)
-+{
-+	if (index < wireless_get_srcs_num(as, id)) {
-+		switch (id.type) {
-+		case OBJECT_TYPE_CONNECTOR:
-+			return dal_graphics_object_id_init(
-+					ENCODER_ID_INTERNAL_WIRELESS,
-+					ENUM_ID_1,
-+					OBJECT_TYPE_ENCODER);
-+			break;
-+		case OBJECT_TYPE_ENCODER:
-+			return dal_graphics_object_id_init(
-+					0,
-+					ENUM_ID_1,
-+					OBJECT_TYPE_GPU);
-+			break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			break;
-+		}
-+	}
-+
-+	return dal_graphics_object_id_init(
-+			0,
-+			ENUM_ID_UNKNOWN,
-+			OBJECT_TYPE_UNKNOWN);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-new file mode 100644
-index 0000000..54b140a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_WIRELESS_DATA_SOURCE_H__
-+#define __DAL_WIRELESS_DATA_SOURCE_H__
-+
-+/* Include */
-+#include "include/grph_object_id.h"
-+
-+/*
-+ * Forward declaration
-+ */
-+struct adapter_service;
-+struct bios_parser;
-+
-+/* Wireless data init structure */
-+struct wireless_init_data {
-+	bool fusion; /* Fusion flag */
-+	bool platform_override; /* Override for platform BIOS option */
-+	bool remote_disp_path_override; /* Override enabling wireless path */
-+	bool vce_supported; /* Existence of VCE block on this DCE */
-+	bool miracast_target_required; /* OS requires Miracast target */
-+};
-+
-+/* Wireless data */
-+struct wireless_data {
-+	bool wireless_enable;
-+	bool wireless_disp_path_enable;
-+	bool miracast_connector_enable;
-+};
-+
-+
-+/*construct wireless data*/
-+bool wireless_data_init(
-+	struct wireless_data *data,
-+	struct bios_parser *bp,
-+	struct wireless_init_data *init_data);
-+
-+uint8_t wireless_get_clocks_num(
-+	struct adapter_service *as);
-+
-+uint8_t wireless_get_connectors_num(
-+	struct adapter_service *as);
-+
-+struct graphics_object_id wireless_get_connector_id(
-+	struct adapter_service *as,
-+	uint8_t connector_index);
-+
-+uint8_t wireless_get_srcs_num(
-+	struct adapter_service *as,
-+	struct graphics_object_id id);
-+
-+struct graphics_object_id wireless_get_src_obj_id(
-+	struct adapter_service *as,
-+	struct graphics_object_id id,
-+	uint8_t index);
-+
-+#endif /* __DAL_WIRELESS_DATA_SOURCE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-new file mode 100644
-index 0000000..5e01a86
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-@@ -0,0 +1,23 @@
-+#
-+# Makefile for the 'asic_capability' sub-component of DAL.
-+#
-+
-+ASIC_CAPABILITY = asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY = \
-+	$(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+ASIC_CAPABILITY_DCE11 = carrizo_asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY_DCE11 = \
-+	$(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE11))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-new file mode 100644
-index 0000000..a532e2f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -0,0 +1,178 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+#include "include/dal_types.h"
-+#include "include/dal_asic_id.h"
-+
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "carrizo_asic_capability.h"
-+#endif
-+
-+/*
-+ * Initializes asic_capability instance.
-+ */
-+static bool construct(
-+	struct asic_capability *cap,
-+	struct hw_asic_id *init,
-+	struct dc_context *ctx)
-+{
-+	bool asic_supported = false;
-+
-+	cap->ctx = ctx;
-+	dc_service_memset(cap->data, 0, sizeof(cap->data));
-+
-+	/* ASIC data */
-+	cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
-+	cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
-+	cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
-+	cap->runtime_flags = init->runtime_flags;
-+	cap->data[ASIC_DATA_REVISION_ID] = init->hw_internal_rev;
-+	cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
-+	cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
-+	cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 1;
-+	cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
-+	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 25;
-+
-+	/* ASIC basic capability */
-+	cap->caps.UNDERSCAN_FOR_HDMI_ONLY = true;
-+	cap->caps.SUPPORT_CEA861E_FINAL = true;
-+	cap->caps.MIRABILIS_SUPPORTED = false;
-+	cap->caps.MIRABILIS_ENABLED_BY_DEFAULT = false;
-+	cap->caps.WIRELESS_LIMIT_TO_720P = false;
-+	cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT = false;
-+	cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+	cap->caps.WIRELESS_COMPRESSED_AUDIO = false;
-+	cap->caps.VCE_SUPPORTED = false;
-+	cap->caps.HPD_CHECK_FOR_EDID = false;
-+	cap->caps.NO_VCC_OFF_HPD_POLLING = false;
-+	cap->caps.NEED_MC_TUNING = false;
-+	cap->caps.SUPPORT_8BPP = true;
-+
-+	/* ASIC stereo 3D capability */
-+	cap->stereo_3d_caps.SUPPORTED = true;
-+
-+	switch (init->chip_family) {
-+	case FAMILY_CI:
-+		break;
-+
-+	case FAMILY_KV:
-+		if (ASIC_REV_IS_KALINDI(init->hw_internal_rev) ||
-+			ASIC_REV_IS_BHAVANI(init->hw_internal_rev)) {
-+		} else {
-+		}
-+		break;
-+
-+	case FAMILY_CZ:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+		carrizo_asic_capability_create(cap, init);
-+		asic_supported = true;
-+#endif
-+		break;
-+
-+	default:
-+		/* unsupported "chip_family" */
-+		break;
-+	}
-+
-+	if (false == asic_supported) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_MASK_ALL,
-+			"%s: ASIC not supported!\n", __func__);
-+	}
-+
-+	return asic_supported;
-+}
-+
-+static void destruct(
-+	struct asic_capability *cap)
-+{
-+	/* nothing to do (yet?) */
-+}
-+
-+/*
-+ * dal_asic_capability_create
-+ *
-+ * Creates asic capability based on DCE version.
-+ */
-+struct asic_capability *dal_asic_capability_create(
-+	struct hw_asic_id *init,
-+	struct dc_context *ctx)
-+{
-+	struct asic_capability *cap;
-+
-+	if (!init) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	cap = dc_service_alloc(ctx, sizeof(struct asic_capability));
-+
-+	if (!cap) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(cap, init, ctx))
-+		return cap;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dc_service_free(ctx, cap);
-+
-+	return NULL;
-+}
-+
-+/*
-+ * dal_asic_capability_destroy
-+ *
-+ * Destroy allocated memory.
-+ */
-+void dal_asic_capability_destroy(
-+	struct asic_capability **cap)
-+{
-+	if (!cap) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (!*cap) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	destruct(*cap);
-+
-+	dc_service_free((*cap)->ctx, *cap);
-+
-+	*cap = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-new file mode 100644
-index 0000000..f57d3f7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-@@ -0,0 +1,146 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+
-+#include "carrizo_asic_capability.h"
-+
-+#include "atom.h"
-+#include "dce/dce_11_0_d.h"
-+#include "smu/smu_8_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dal_asic_id.h"
-+
-+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS     0xC0014074
-+
-+/*
-+ * carrizo_asic_capability_create
-+ *
-+ * Create and initiate Carrizo capability.
-+ */
-+void carrizo_asic_capability_create(struct asic_capability *cap,
-+	struct hw_asic_id *init)
-+{
-+	uint32_t e_fuse_setting;
-+	/* ASIC data */
-+	cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
-+	cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
-+	cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
-+	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
-+	cap->data[ASIC_DATA_DCE_VERSION] = 0x110; /* DCE 11 */
-+	cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
-+	cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
-+	cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 2;
-+	cap->data[ASIC_DATA_MC_LATENCY] = 5000;
-+	cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
-+	cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-+	cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
-+	cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
-+	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
-+	cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
-+	cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
-+
-+	/* ASIC basic capability */
-+	cap->caps.IS_FUSION = true;
-+	cap->caps.DP_MST_SUPPORTED = true;
-+	cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
-+	cap->caps.MIRABILIS_SUPPORTED = true;
-+	cap->caps.NO_VCC_OFF_HPD_POLLING = true;
-+	cap->caps.VCE_SUPPORTED = true;
-+	cap->caps.HPD_CHECK_FOR_EDID = true;
-+	cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
-+	cap->caps.SUPPORT_8BPP = false;
-+
-+	/* ASIC stereo 3d capability */
-+	cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
-+	cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
-+	cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
-+	cap->stereo_3d_caps.INTERLEAVE = true;
-+
-+    e_fuse_setting = dal_read_index_reg(cap->ctx,CGS_IND_REG__SMC,ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-+
-+	/* Bits [28:27]*/
-+	switch ((e_fuse_setting >> 27) & 0x3) {
-+	case 0:
-+		/*both VCE engine are working*/
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
-+		/*TODO:
-+		cap->caps.wirelessLowVCEPerformance = false;
-+		m_AsicCaps.vceInstance0Enabled = true;
-+		m_AsicCaps.vceInstance1Enabled = true;*/
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 1:
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+		/*TODO:
-+		m_AsicCaps.wirelessLowVCEPerformance = false;
-+		m_AsicCaps.vceInstance1Enabled = true;*/
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 2:
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+		/*TODO:
-+		m_AsicCaps.wirelessLowVCEPerformance = false;
-+		m_AsicCaps.vceInstance0Enabled = true;*/
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 3:
-+		/* VCE_DISABLE = 0x3  - both VCE
-+		 * instances are in harvesting,
-+		 * no VCE supported any more.
-+		 */
-+		cap->caps.VCE_SUPPORTED = false;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	if (ASIC_REV_IS_STONEY(init->hw_internal_rev))
-+	{
-+		/* Stoney is the same DCE11, but only two pipes, three  digs.
-+		 * and HW added 64bit back for non SG */
-+		cap->data[ASIC_DATA_CONTROLLERS_NUM] = 2;
-+		cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 2;
-+		cap->data[ASIC_DATA_LINEBUFFER_NUM] = 2;
-+		/*3 DP MST per connector, limited by number of pipe and number
-+		 * of Dig.*/
-+		cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2;
-+
-+	}
-+
-+
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
-new file mode 100644
-index 0000000..d1e9b83
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CARRIZO_ASIC_CAPABILITY_H__
-+#define __DAL_CARRIZO_ASIC_CAPABILITY_H__
-+
-+/* Forward declaration */
-+struct asic_capability;
-+
-+/* Create and initialize Carrizo data */
-+void carrizo_asic_capability_create(struct asic_capability *cap,
-+	struct hw_asic_id *init);
-+
-+#endif /* __DAL_CARRIZO_ASIC_CAPABILITY_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-new file mode 100644
-index 0000000..0999372
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-@@ -0,0 +1,22 @@
-+#
-+# Makefile for the 'audio' sub-component of DAL.
-+# It provides the control and status of HW adapter resources,
-+# that are global for the ASIC and sharable between pipes.
-+
-+AUDIO = audio_base.o hw_ctx_audio.o
-+
-+AMD_DAL_AUDIO = $(addprefix $(AMDDALPATH)/dc/audio/,$(AUDIO))
-+
-+AMD_DAL_FILES += $(AMD_DAL_AUDIO)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+AUDIO_DCE11 = audio_dce110.o hw_ctx_audio_dce110.o
-+
-+AMD_DAL_AUDIO_DCE11 = $(addprefix $(AMDDALPATH)/dc/audio/dce110/,$(AUDIO_DCE11))
-+
-+AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE11)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio.h b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-new file mode 100644
-index 0000000..ad2dc18
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-@@ -0,0 +1,195 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUDIO_H__
-+#define __DAL_AUDIO_H__
-+
-+#include "include/audio_interface.h"
-+#include "hw_ctx_audio.h"
-+#include "include/link_service_types.h"
-+
-+/***** only for hook functions  *****/
-+/**
-+ *which will be overwritten by derived audio object.
-+ *audio hw context object is independent object
-+ */
-+
-+struct audio;
-+
-+struct audio_funcs {
-+	/*
-+	 *get_object_id
-+	 *get_object_type
-+	 *enumerate_input_signals
-+	 *enumerate_output_signals
-+	 *is_input_signal_supported
-+	 *is_output_signal_supported
-+	 *set_object_properties
-+	 *get_object_properties
-+	 */
-+
-+	void (*destroy)(struct audio **audio);
-+	/*power_up
-+	 *power_down
-+	 *release_hw_base
-+	 */
-+
-+	/* setup audio */
-+	enum audio_result (*setup)(
-+		struct audio *audio,
-+		struct audio_output *output,
-+		struct audio_info *info);
-+
-+	enum audio_result (*enable_output)(
-+		struct audio *audio,
-+		enum engine_id engine_id,
-+		enum signal_type signal);
-+
-+	enum audio_result (*disable_output)(
-+		struct audio *audio,
-+		enum engine_id engine_id,
-+		enum signal_type signal);
-+
-+	/*enable_azalia_audio_jack_presence
-+	 * disable_azalia_audio_jack_presence
-+	 */
-+
-+	enum audio_result (*unmute)(
-+		struct audio *audio,
-+		enum engine_id engine_id,
-+		enum signal_type signal);
-+
-+	enum audio_result (*mute)(
-+		struct audio *audio,
-+		enum engine_id engine_id,
-+		enum signal_type signal);
-+
-+	/* SW initialization that cannot be done in constructor. This will
-+	 * be done is audio_power_up but is not in audio_interface. It is only
-+	 * called by power_up
-+	 */
-+	enum audio_result (*initialize)(
-+		struct audio *audio);
-+
-+	/* enable channel splitting mapping */
-+	void (*enable_channel_splitting_mapping)(
-+		struct audio *audio,
-+		enum engine_id engine_id,
-+		enum signal_type signal,
-+		const struct audio_channel_associate_info *audio_mapping,
-+		bool enable);
-+
-+	/* get current multi channel split. */
-+	enum audio_result (*get_channel_splitting_mapping)(
-+		struct audio *audio,
-+		enum engine_id engine_id,
-+		struct audio_channel_associate_info *audio_mapping);
-+
-+	/* set payload value for the unsolicited response */
-+	void (*set_unsolicited_response_payload)(
-+		struct audio *audio,
-+		enum audio_payload payload);
-+
-+	/* Update audio wall clock source */
-+	void (*setup_audio_wall_dto)(
-+		struct audio *audio,
-+		enum signal_type signal,
-+		const struct audio_crtc_info *crtc_info,
-+		const struct audio_pll_info *pll_info);
-+
-+	/* options and features supported by Audio */
-+	struct audio_feature_support (*get_supported_features)(
-+		struct audio *audio);
-+
-+	/*
-+	 *check_audio_bandwidth
-+	 *write_reg
-+	 *read_reg
-+	 *enable_gtc_embedding_with_group
-+	 *disable_gtc_embedding
-+	 *register_interrupt
-+	 *unregister_interrupt
-+	 *process_interrupt
-+	 *create_hw_ctx
-+	 *getHwCtx
-+	 *setHwCtx
-+	 *handle_interrupt
-+	 */
-+};
-+
-+struct audio {
-+	/* hook functions. they will be overwritten by specific ASIC */
-+	const struct audio_funcs *funcs;
-+	/* TODO: static struct audio_funcs funcs;*/
-+
-+	/*external structures - get service from external*/
-+	struct graphics_object_id id;
-+	struct adapter_service *adapter_service;
-+	/* audio HW context */
-+	struct hw_ctx_audio *hw_ctx;
-+	struct dc_context *ctx;
-+	/* audio supports input and output signals */
-+	uint32_t input_signals;
-+	uint32_t output_signals;
-+};
-+
-+/* - functions defined by audio.h will be used by audio component only.
-+ *   but audio.c also implements some function defined by dal\include
-+ */
-+
-+/* graphics_object_base implemention
-+ * 1.input_signals and output_signals are moved
-+ * into audio object.
-+ *
-+ * 2.Get the Graphics Object ID
-+ *
-+ * Outside audio:
-+ * use dal_graphics_object_id_get_audio_id
-+ * Within audio:
-+ *	use audio->go_base.id
-+ *
-+ * 3. Get the Graphics Object Type
-+ *
-+ *  use object_id.type
-+ *  not function implemented.
-+ * 4. Common Graphics Object Properties
-+ * use object id ->go_properties.multi_path
-+ * not function implemented.
-+ */
-+
-+bool dal_audio_construct_base(
-+	struct audio *audio,
-+	const struct audio_init_data *init_data);
-+
-+void dal_audio_destruct_base(
-+	struct audio *audio);
-+
-+void dal_audio_release_hw_base(
-+	struct audio *audio);
-+
-+#endif  /* __DAL_AUDIO__ */
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-new file mode 100644
-index 0000000..6bac3ed
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -0,0 +1,463 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "audio.h"
-+#include "hw_ctx_audio.h"
-+
-+#include "dce110/audio_dce110.h"
-+
-+/***** static function : only used within audio.c *****/
-+
-+/* stub for hook functions */
-+static void destroy(
-+	struct audio **audio)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static enum audio_result setup(
-+	struct audio *audio,
-+	struct audio_output *output,
-+	struct audio_info *info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result enable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result disable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result unmute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result mute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+static enum audio_result initialize(
-+	struct audio *audio)
-+{
-+	/*DCE specific, must be implemented in derived. Implemeentaion of
-+	 *initialize will create audio hw context. create_hw_ctx
-+	 */
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+static void enable_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* get current multi channel split. */
-+static enum audio_result get_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* set payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+	struct audio *audio,
-+	enum audio_payload payload)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* update audio wall clock source */
-+static void setup_audio_wall_dto(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static struct audio_feature_support get_supported_features(struct audio *audio)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	struct audio_feature_support features;
-+
-+	dc_service_memset(&features, 0, sizeof(features));
-+
-+	features.ENGINE_DIGA = 1;
-+	features.ENGINE_DIGB = 1;
-+
-+	return features;
-+}
-+
-+static const struct audio_funcs audio_funcs = {
-+	.destroy = destroy,
-+	.setup = setup,
-+	.enable_output = enable_output,
-+	.disable_output = disable_output,
-+	.unmute = unmute,
-+	.mute = mute,
-+	.initialize = initialize,
-+	.enable_channel_splitting_mapping =
-+		enable_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.setup_audio_wall_dto = setup_audio_wall_dto,
-+	.get_supported_features = get_supported_features,
-+};
-+
-+/***** SCOPE : declare in audio.h. use within dal-audio. *****/
-+
-+bool dal_audio_construct_base(
-+	struct audio *audio,
-+	const struct audio_init_data *init_data)
-+{
-+	enum signal_type signals = SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+	ASSERT(init_data->as != NULL);
-+
-+	/* base hook functions */
-+	audio->funcs = &audio_funcs;
-+
-+	/*setup pointers to get service from dal service compoenents*/
-+	audio->adapter_service = init_data->as;
-+
-+	audio->ctx = init_data->ctx;
-+
-+	/* save audio endpoint number to identify object creating */
-+	audio->id = init_data->audio_stream_id;
-+
-+	/* Fill supported signals. !!! be aware that android definition is
-+	 * already shift to vector.
-+	 */
-+	signals |= SIGNAL_TYPE_DISPLAY_PORT;
-+	signals |= SIGNAL_TYPE_DISPLAY_PORT_MST;
-+	signals |= SIGNAL_TYPE_EDP;
-+	signals |= SIGNAL_TYPE_DISPLAY_PORT;
-+	signals |= SIGNAL_TYPE_WIRELESS;
-+
-+	/* Audio supports same set for input and output signals */
-+	audio->input_signals = signals;
-+	audio->output_signals = signals;
-+
-+	return true;
-+}
-+
-+/* except hw_ctx, no other hw need reset. so do nothing */
-+void dal_audio_destruct_base(
-+	struct audio *audio)
-+{
-+}
-+
-+/* Enumerate Graphics Object supported Input/Output Signal Types */
-+uint32_t dal_audio_enumerate_input_signals(
-+	struct audio *audio)
-+{
-+	return audio->input_signals;
-+}
-+
-+uint32_t dal_audio_enumerate_output_signals(
-+	struct audio *audio)
-+{
-+	return audio->output_signals;
-+}
-+
-+/*  Check if signal supported by GraphicsObject  */
-+bool dal_audio_is_input_signal_supported(
-+	struct audio *audio,
-+	enum signal_type signal)
-+{
-+	return (signal & audio->output_signals) != 0;
-+}
-+
-+bool dal_audio_is_output_signal_supported(
-+	struct audio *audio,
-+	enum signal_type signal)
-+{
-+	return (signal & audio->input_signals) != 0;
-+}
-+
-+/***** SCOPE : declare in dal\include  *****/
-+
-+/* audio object creator triage. memory allocate and release will be
-+ * done within dal_audio_create_dcexx
-+ */
-+struct audio *dal_audio_create(
-+	const struct audio_init_data *init_data)
-+{
-+	struct adapter_service *as;
-+
-+	if (init_data->as == NULL)
-+		return NULL;
-+
-+	as = init_data->as;
-+	switch (dal_adapter_service_get_dce_version(as)) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		return dal_audio_create_dce110(init_data);
-+#endif
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	return NULL;
-+}
-+
-+/* audio object creator triage.
-+ * memory for "struct audio   dal_audio_create_dce8x" allocate
-+ * will happens within dal_audio_dce8x. memory allocate is done
-+ * with dal_audio_create_dce8x. memory release is initiated by
-+ * dal_audio_destroy. It will call hook function which will finially
-+ * used destroy() of dal_audio_dce8x. therefore, no memroy allocate
-+ *and release happen physcially at audio base object.
-+ */
-+void dal_audio_destroy(
-+	struct audio **audio)
-+{
-+	if (!audio || !*audio) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	(*audio)->funcs->destroy(audio);
-+
-+	*audio = NULL;
-+}
-+
-+const struct graphics_object_id dal_audio_get_graphics_object_id(
-+	const struct audio *audio)
-+{
-+	return audio->id;
-+}
-+
-+/* enable azalia audio endpoint. This function call hw_ctx directly
-+ *not overwitten at audio level.
-+ */
-+enum audio_result dal_audio_enable_azalia_audio_jack_presence(
-+	struct audio *audio,
-+	enum engine_id engine_id)
-+{
-+	audio->hw_ctx->funcs->enable_azalia_audio(audio->hw_ctx, engine_id);
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* disable azalia audio endpoint. This function call hw_ctx directly
-+ *not overwitten at audio level.
-+ */
-+enum audio_result dal_audio_disable_azalia_audio_jack_presence(
-+	struct audio *audio,
-+	enum engine_id engine_id)
-+{
-+	audio->hw_ctx->funcs->disable_azalia_audio(audio->hw_ctx, engine_id);
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* get audio bandwidth information. This function call hw_ctx directly
-+ *not overwitten at audio level.
-+ */
-+void dal_audio_check_audio_bandwidth(
-+	struct audio *audio,
-+	const struct audio_crtc_info *info,
-+	uint32_t channel_count,
-+	enum signal_type signal,
-+	union audio_sample_rates *sample_rates)
-+{
-+	dal_hw_ctx_audio_check_audio_bandwidth(
-+		audio->hw_ctx, info, channel_count, signal, sample_rates);
-+}
-+
-+/* DP Audio register write access. This function call hw_ctx directly
-+ * not overwitten at audio level.
-+ */
-+
-+/*assign GTC group and enable GTC value embedding*/
-+void dal_audio_enable_gtc_embedding_with_group(
-+	struct audio *audio,
-+	uint32_t group_num,
-+	uint32_t audio_latency)
-+{
-+	audio->hw_ctx->funcs->enable_gtc_embedding_with_group(
-+		audio->hw_ctx, group_num, audio_latency);
-+}
-+
-+/* disable GTC value embedding */
-+void dal_audio_disable_gtc_embedding(
-+	struct audio *audio)
-+{
-+	audio->hw_ctx->funcs->disable_gtc_embedding(audio->hw_ctx);
-+}
-+
-+/* perform power up sequence (boot up, resume, recovery) */
-+enum audio_result dal_audio_power_up(
-+	struct audio *audio)
-+{
-+	return audio->funcs->initialize(audio);
-+}
-+
-+/* perform power down (shut down, stand by) */
-+enum audio_result dal_audio_power_down(
-+	struct audio *audio)
-+{
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* setup audio */
-+enum audio_result dal_audio_setup(
-+	struct audio *audio,
-+	struct audio_output *output,
-+	struct audio_info *info)
-+{
-+	return audio->funcs->setup(audio, output, info);
-+}
-+
-+/* enable audio */
-+enum audio_result dal_audio_enable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	return audio->funcs->enable_output(audio, engine_id, signal);
-+}
-+
-+/* disable audio */
-+enum audio_result dal_audio_disable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	return audio->funcs->disable_output(audio, engine_id, signal);
-+}
-+
-+/* unmute audio */
-+enum audio_result dal_audio_unmute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	return audio->funcs->unmute(audio, engine_id, signal);
-+}
-+
-+/* mute audio */
-+enum audio_result dal_audio_mute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	return audio->funcs->mute(audio, engine_id, signal);
-+}
-+
-+/* Enable multi channel split */
-+void dal_audio_enable_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	audio->funcs->enable_channel_splitting_mapping(
-+		audio, engine_id, signal, audio_mapping, enable);
-+}
-+
-+/* get current multi channel split. */
-+enum audio_result dal_audio_get_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	return audio->funcs->get_channel_splitting_mapping(
-+		audio, engine_id, audio_mapping);
-+}
-+
-+/* set payload value for the unsolicited response */
-+void dal_audio_set_unsolicited_response_payload(
-+	struct audio *audio,
-+	enum audio_payload payload)
-+{
-+	audio->funcs->set_unsolicited_response_payload(audio, payload);
-+}
-+
-+/* update audio wall clock source */
-+void dal_audio_setup_audio_wall_dto(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	audio->funcs->setup_audio_wall_dto(audio, signal, crtc_info, pll_info);
-+}
-+
-+struct audio_feature_support dal_audio_get_supported_features(
-+	struct audio *audio)
-+{
-+	return audio->funcs->get_supported_features(audio);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-new file mode 100644
-index 0000000..f284870
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-@@ -0,0 +1,452 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+
-+#include "audio_dce110.h"
-+
-+/***** static functions  *****/
-+
-+static void destruct(struct audio_dce110 *audio)
-+{
-+	/*release memory allocated for hw_ctx -- allocated is initiated
-+	 *by audio_dce110 power_up
-+	 *audio->base->hw_ctx = NULL is done within hw-ctx->destroy
-+	 */
-+	if (audio->base.hw_ctx)
-+		audio->base.hw_ctx->funcs->destroy(&(audio->base.hw_ctx));
-+
-+	/* reset base_audio_block */
-+	dal_audio_destruct_base(&audio->base);
-+}
-+
-+static void destroy(struct audio **ptr)
-+{
-+	struct audio_dce110 *audio = NULL;
-+
-+	audio = container_of(*ptr, struct audio_dce110, base);
-+
-+	destruct(audio);
-+
-+	/* release memory allocated for audio_dce110*/
-+	dc_service_free((*ptr)->ctx, audio);
-+	*ptr = NULL;
-+}
-+
-+
-+/* The inital call of hook function comes from audio object level.
-+ *The passing object handle "struct audio *audio" point to base object
-+ *already.There is not need to get base object from audio_dce110.
-+ */
-+
-+/**
-+* setup
-+*
-+* @brief
-+*  setup Audio HW block, to be called by dal_audio_setup
-+*
-+*/
-+static enum audio_result setup(
-+	struct audio *audio,
-+	struct audio_output *output,
-+	struct audio_info *info)
-+{
-+	switch (output->signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/*setup HDMI audio engine*/
-+		audio->hw_ctx->funcs->enable_afmt_clock(
-+			audio->hw_ctx,
-+			output->engine_id,
-+			true);
-+		audio->hw_ctx->funcs->setup_hdmi_audio(
-+			audio->hw_ctx, output->engine_id, &output->crtc_info);
-+
-+		audio->hw_ctx->funcs->setup_azalia(
-+			audio->hw_ctx,
-+			output->engine_id,
-+			output->signal,
-+			&output->crtc_info,
-+			&output->pll_info,
-+			info);
-+		break;
-+
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* setup Azalia block for Wireless Display - This
-+			is different than for wired
-+			displays because there is no
-+			DIG to program.*/
-+		/*TODO:
-+		audio->hw_ctx->funcs->setup_azalia_for_vce(
-+			audio->hw_ctx,
-+			audio->signal,
-+			audio->crtc_info,
-+			info);
-+		*/
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* setup DP audio engine will be done at enable output */
-+
-+		/* setup Azalia block*/
-+		audio->hw_ctx->funcs->setup_azalia(
-+			audio->hw_ctx,
-+			output->engine_id,
-+			output->signal,
-+			&output->crtc_info,
-+			&output->pll_info,
-+			info);
-+
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* enable_output
-+*
-+* @brief
-+*  enable Audio HW block, to be called by dal_audio_enable_output
-+*/
-+static enum audio_result enable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/* enable audio output */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP: {
-+			/* enable AFMT clock before enable audio*/
-+			audio->hw_ctx->funcs->enable_afmt_clock(
-+				audio->hw_ctx, engine_id, true);
-+			/* setup DP audio engine */
-+			audio->hw_ctx->funcs->setup_dp_audio(
-+				audio->hw_ctx, engine_id);
-+			/* enabl DP audio packets will be done at unblank */
-+			audio->hw_ctx->funcs->enable_dp_audio(
-+				audio->hw_ctx, engine_id);
-+		}
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* route audio to VCE block */
-+		audio->hw_ctx->funcs->setup_vce_audio(audio->hw_ctx);
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* disable_output
-+*
-+* @brief
-+*  disable Audio HW block, to be called by dal_audio_disable_output
-+*
-+*/
-+static enum audio_result disable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* disable HDMI audio */
-+		audio->hw_ctx->
-+			funcs->disable_azalia_audio(
-+					audio->hw_ctx, engine_id);
-+		audio->hw_ctx->
-+			funcs->enable_afmt_clock(
-+					audio->hw_ctx, engine_id,
-+					false);
-+
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP: {
-+			/* disable DP audio */
-+			audio->hw_ctx->funcs->disable_dp_audio(
-+				audio->hw_ctx, engine_id);
-+			audio->hw_ctx->funcs->disable_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+			audio->hw_ctx->funcs->enable_afmt_clock(
-+				audio->hw_ctx, engine_id, false);
-+		}
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* unmute
-+*
-+* @brief
-+*  unmute audio, to be called by dal_audio_unmute
-+*
-+*/
-+static enum audio_result unmute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* unmute Azalia audio */
-+		audio->hw_ctx->funcs->unmute_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/*Do nothing for wireless display*/
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* mute
-+*
-+* @brief
-+*  mute audio, to be called  by dal_audio_nmute
-+*
-+*/
-+static enum audio_result mute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* mute Azalia audio */
-+		audio->hw_ctx->funcs->mute_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/*Do nothing for wireless display*/
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* initialize
-+*
-+* @brief
-+*  Perform SW initialization - create audio hw context. Then do HW
-+*  initialization. this function is called at dal_audio_power_up.
-+*
-+*/
-+static enum audio_result initialize(
-+	struct audio *audio)
-+{
-+	uint8_t audio_endpoint_enum_id = 0;
-+
-+	audio_endpoint_enum_id = audio->id.enum_id;
-+
-+	/* HW CTX already create*/
-+	if (audio->hw_ctx != NULL)
-+		return AUDIO_RESULT_OK;
-+
-+	audio->hw_ctx = dal_hw_ctx_audio_dce110_create(
-+			audio->ctx,
-+			audio_endpoint_enum_id);
-+
-+	if (audio->hw_ctx == NULL)
-+		return AUDIO_RESULT_ERROR;
-+
-+	/* override HW default settings */
-+	audio->hw_ctx->funcs->hw_initialize(audio->hw_ctx);
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* enable multi channel split */
-+static void enable_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	audio->hw_ctx->funcs->setup_channel_splitting_mapping(
-+		audio->hw_ctx,
-+		engine_id,
-+		signal,
-+		audio_mapping, enable);
-+}
-+
-+/* get current multi channel split. */
-+static enum audio_result get_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	if (audio->hw_ctx->funcs->get_channel_splitting_mapping(
-+		audio->hw_ctx, engine_id, audio_mapping)) {
-+		return AUDIO_RESULT_OK;
-+	} else {
-+		return AUDIO_RESULT_ERROR;
-+	}
-+}
-+
-+/**
-+* set_unsolicited_response_payload
-+*
-+* @brief
-+*  Set payload value for the unsolicited response
-+*/
-+static void set_unsolicited_response_payload(
-+	struct audio *audio,
-+	enum audio_payload payload)
-+{
-+	audio->hw_ctx->funcs->set_unsolicited_response_payload(
-+			audio->hw_ctx, payload);
-+}
-+
-+/**
-+* setup_audio_wall_dto
-+*
-+* @brief
-+*  Update audio source clock from hardware context.
-+*
-+*/
-+static void setup_audio_wall_dto(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	audio->hw_ctx->funcs->setup_audio_wall_dto(
-+		audio->hw_ctx, signal, crtc_info, pll_info);
-+}
-+
-+/**
-+* get_supported_features
-+*
-+* @brief
-+*  options and features supported by Audio
-+*  returns supported engines, signals.
-+*  features are reported for HW audio/Azalia block rather then Audio object
-+*  itself the difference for DCE6.x is that MultiStream Audio is now supported
-+*
-+*/
-+static struct audio_feature_support get_supported_features(struct audio *audio)
-+{
-+	struct audio_feature_support afs = {0};
-+
-+	afs.ENGINE_DIGA = 1;
-+	afs.ENGINE_DIGB = 1;
-+	afs.ENGINE_DIGC = 1;
-+	afs.MULTISTREAM_AUDIO = 1;
-+
-+	return afs;
-+}
-+
-+static const struct audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup = setup,
-+	.enable_output = enable_output,
-+	.disable_output = disable_output,
-+	.unmute = unmute,
-+	.mute = mute,
-+	.initialize = initialize,
-+	.enable_channel_splitting_mapping =
-+		enable_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.setup_audio_wall_dto = setup_audio_wall_dto,
-+	.get_supported_features = get_supported_features,
-+};
-+
-+static bool construct(
-+	struct audio_dce110 *audio,
-+	const struct audio_init_data *init_data)
-+{
-+	struct audio *base = &audio->base;
-+
-+	/* base audio construct*/
-+	if (!dal_audio_construct_base(base, init_data))
-+		return false;
-+
-+	/*vtable methods*/
-+	base->funcs = &funcs;
-+	return true;
-+}
-+
-+
-+/* --- audio scope functions  --- */
-+
-+struct audio *dal_audio_create_dce110(
-+	const struct audio_init_data *init_data)
-+{
-+	/*allocate memory for audio_dce110 */
-+	struct audio_dce110 *audio = dc_service_alloc(init_data->ctx, sizeof(*audio));
-+
-+	if (audio == NULL) {
-+		ASSERT_CRITICAL(audio);
-+		return NULL;
-+	}
-+	/*pointer to base_audio_block of audio_dce110 ==> audio base object */
-+	if (construct(audio, init_data))
-+		return &audio->base;
-+
-+	dal_logger_write(
-+		init_data->ctx->logger,
-+		LOG_MAJOR_ERROR,
-+		LOG_MINOR_COMPONENT_AUDIO,
-+		"Failed to create audio object for DCE11\n");
-+
-+	 /*release memory allocated if fail */
-+	dc_service_free(init_data->ctx, audio);
-+	return NULL;
-+}
-+
-+/* Do not need expose construct_dce110 and destruct_dce110 becuase there is
-+ *derived object after dce110
-+ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-new file mode 100644
-index 0000000..e5ff823
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_AUDIO_DCE_110_H__
-+#define __DAL_AUDIO_DCE_110_H__
-+
-+#include "audio/audio.h"
-+#include "audio/hw_ctx_audio.h"
-+#include "audio/dce110/hw_ctx_audio_dce110.h"
-+
-+
-+
-+struct audio_dce110 {
-+	struct audio base;
-+	/* dce-specific members are following */
-+	/* none */
-+};
-+
-+struct audio *dal_audio_create_dce110(const struct audio_init_data *init_data);
-+
-+#endif   /*__DAL_AUDIO_DCE_110_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-new file mode 100644
-index 0000000..a13b2ab
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -0,0 +1,1929 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+#include "../hw_ctx_audio.h"
-+#include "hw_ctx_audio_dce110.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define FROM_BASE(ptr) \
-+	container_of((ptr), struct hw_ctx_audio_dce110, base)
-+
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
-+#define DP_AUDIO_DTO_MODULE_WITHOUT_SS 360
-+#define DP_AUDIO_DTO_PHASE_WITHOUT_SS 24
-+
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUDIO_FRONT_END 0
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__REGISTER_PROGRAMMABLE 2
-+
-+#define FIRST_AUDIO_STREAM_ID 1
-+
-+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_AUDIO, \
-+			"Audio:%s()\n", __func__)
-+
-+static const uint32_t engine_offset[] = {
-+	0,
-+	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG3_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
-+};
-+
-+static void destruct(
-+	struct hw_ctx_audio_dce110 *hw_ctx_dce110)
-+{
-+	dal_audio_destruct_hw_ctx_audio(&hw_ctx_dce110->base);
-+}
-+
-+static void destroy(
-+	struct hw_ctx_audio **ptr)
-+{
-+	struct hw_ctx_audio_dce110 *hw_ctx_dce110;
-+
-+	hw_ctx_dce110 = container_of(
-+		*ptr, struct hw_ctx_audio_dce110, base);
-+
-+	destruct(hw_ctx_dce110);
-+	/* release memory allocated for struct hw_ctx_audio_dce110 */
-+	dc_service_free((*ptr)->ctx, hw_ctx_dce110);
-+
-+	*ptr = NULL;
-+}
-+
-+/* ---  helpers --- */
-+static void write_indirect_azalia_reg(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t reg_index,
-+	uint32_t reg_data)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+		set_reg_field_value(value, reg_index,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+		value = 0;
-+		set_reg_field_value(value, reg_data,
-+			AZALIA_F0_CODEC_ENDPOINT_DATA,
-+			AZALIA_ENDPOINT_REG_DATA);
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	dal_logger_write(
-+		hw_ctx->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_AUDIO,
-+		"AUDIO:write_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, reg_data);
-+}
-+
-+static uint32_t read_indirect_azalia_reg(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t reg_index)
-+{
-+	uint32_t ret_val = 0;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+		set_reg_field_value(value, reg_index,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		ret_val = value;
-+	}
-+
-+	dal_logger_write(
-+		hw_ctx->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_AUDIO,
-+		"AUDIO:read_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, ret_val);
-+
-+	return ret_val;
-+}
-+
-+/* expose/not expose HBR capability to Audio driver */
-+static void set_high_bit_rate_capable(
-+	const struct hw_ctx_audio *hw_ctx,
-+	bool capable)
-+{
-+	uint32_t value = 0;
-+
-+	/* set high bit rate audio capable*/
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
-+
-+	set_reg_field_value(value, capable,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		HBR_CAPABLE);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		value);
-+}
-+
-+/* set HBR channnel count *
-+static void set_hbr_channel_count(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t hbr_channel_count)
-+{
-+	uint32_t value = 0;
-+
-+	if (hbr_channel_count > 7)
-+		return;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+
-+	set_reg_field_value(value, hbr_channel_count,
-+		AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+		HBR_CHANNEL_COUNT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL, value);
-+
-+}
-+
-+*set compressed audio channel count *
-+static void set_compressed_audio_channel_count(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t compressed_audio_ch_count)
-+{
-+	uint32_t value = 0;
-+	if (compressed_audio_ch_count > 7)
-+		return;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+
-+	set_reg_field_value(value, compressed_audio_ch_count,
-+		AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+		COMPRESSED_CHANNEL_COUNT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+		value);
-+
-+}
-+*/
-+/* set video latency in in ms/2+1 */
-+static void set_video_latency(
-+	const struct hw_ctx_audio *hw_ctx,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if ((latency_in_ms < 0) || (latency_in_ms > 255))
-+		return;
-+
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		VIDEO_LIPSYNC);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+
-+}
-+
-+/* set audio latency in in ms/2+1 */
-+static void set_audio_latency(
-+	const struct hw_ctx_audio *hw_ctx,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if (latency_in_ms < 0)
-+		latency_in_ms = 0;
-+
-+	if (latency_in_ms > 255)
-+		latency_in_ms = 255;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		AUDIO_LIPSYNC);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+
-+}
-+
-+/* enable HW/SW Sync */
-+/*static void enable_hw_sw_sync(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+		union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+	value = dal_read_reg(mmAZALIA_CYCLIC_BUFFER_SYNC);
-+	value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 1;
-+	dal_write_reg(mmAZALIA_CYCLIC_BUFFER_SYNC, value);
-+}*/
-+
-+/* disable HW/SW Sync */
-+/*static void disable_hw_sw_sync(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+	value = dal_read_reg(
-+		mmAZALIA_CYCLIC_BUFFER_SYNC);
-+	value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 0;
-+	dal_write_reg(
-+		mmAZALIA_CYCLIC_BUFFER_SYNC, value);
-+}*/
-+
-+/* update hardware with software's current position in cyclic buffer */
-+/*static void update_sw_write_ptr(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t offset)
-+{
-+		union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER value;
-+
-+	value = dal_read_reg(
-+		mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER);
-+	value.bits.APPLICATION_POSITION_IN_CYCLIC_BUFFER = offset;
-+	dal_write_reg(
-+		mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER,
-+		value);
-+}*/
-+
-+/* update Audio/Video association */
-+/*static void update_av_association(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	uint32_t displayId)
-+{
-+
-+}*/
-+
-+/* ---  hook functions --- */
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info);
-+
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info);
-+
-+static void setup_audio_wall_dto(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	struct azalia_clock_info clock_info = { 0 };
-+
-+	uint32_t value = dal_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
-+
-+	/* TODO: GraphicsObject\inc\GraphicsObjectDefs.hpp(131):
-+	 *inline bool isHdmiSignal(SignalType signal)
-+	 *if (Signals::isHdmiSignal(signal))
-+	 */
-+	if (dc_is_hdmi_signal(signal)) {
-+		/*DTO0 Programming goal:
-+		-generate 24MHz, 128*Fs from 24MHz
-+		-use DTO0 when an active HDMI port is connected
-+		(optionally a DP is connected) */
-+
-+		/* calculate DTO settings */
-+		get_azalia_clock_info_hdmi(
-+			hw_ctx,
-+			crtc_info->requested_pixel_clock,
-+			crtc_info->calculated_pixel_clock,
-+			&clock_info);
-+
-+		/* On TN/SI, Program DTO source select and DTO select before
-+		programming DTO modulo and DTO phase. These bits must be
-+		programmed first, otherwise there will be no HDMI audio at boot
-+		up. This is a HW sequence change (different from old ASICs).
-+		Caution when changing this programming sequence.
-+
-+		HDMI enabled, using DTO0
-+		program master CRTC for DTO0 */
-+		{
-+			set_reg_field_value(value,
-+				pll_info->dto_source - DTO_SOURCE_ID0,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO0_SOURCE_SEL);
-+
-+			set_reg_field_value(value,
-+				0,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL);
-+
-+			dal_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO_SOURCE, value);
-+		}
-+
-+		/* module */
-+		{
-+			value = dal_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_MODULE);
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_module,
-+				DCCG_AUDIO_DTO0_MODULE,
-+				DCCG_AUDIO_DTO0_MODULE);
-+			dal_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_MODULE, value);
-+		}
-+
-+		/* phase */
-+		{
-+			value = 0;
-+
-+			value = dal_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_PHASE);
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_phase,
-+				DCCG_AUDIO_DTO0_PHASE,
-+				DCCG_AUDIO_DTO0_PHASE);
-+
-+			dal_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_PHASE, value);
-+		}
-+
-+	} else {
-+		/*DTO1 Programming goal:
-+		-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-+		-default is to used DTO1, and switch to DTO0 when an audio
-+		master HDMI port is connected
-+		-use as default for DP
-+
-+		calculate DTO settings */
-+		get_azalia_clock_info_dp(
-+			hw_ctx,
-+			crtc_info->requested_pixel_clock,
-+			pll_info,
-+			&clock_info);
-+
-+		/* Program DTO select before programming DTO modulo and DTO
-+		phase. default to use DTO1 */
-+
-+		{
-+			set_reg_field_value(value, 1,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL);
-+			/*dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value)*/
-+
-+			/* Select 512fs for DP TODO: web register definition
-+			does not match register header file
-+			set_reg_field_value(value, 1,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO2_USE_512FBR_DTO);
-+			*/
-+
-+			dal_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO_SOURCE, value);
-+		}
-+
-+		/* module */
-+		{
-+			value = 0;
-+
-+			value = dal_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_MODULE);
-+
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_module,
-+				DCCG_AUDIO_DTO1_MODULE,
-+				DCCG_AUDIO_DTO1_MODULE);
-+
-+			dal_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_MODULE, value);
-+		}
-+
-+		/* phase */
-+		{
-+			value = 0;
-+
-+			value = dal_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_PHASE);
-+
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_phase,
-+				DCCG_AUDIO_DTO1_PHASE,
-+				DCCG_AUDIO_DTO1_PHASE);
-+
-+			dal_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_PHASE, value);
-+		}
-+
-+		/* DAL2 code separate DCCG_AUDIO_DTO_SEL and
-+		DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different
-+		location. merge together should not hurt */
-+		/*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1;
-+		dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/
-+	}
-+}
-+
-+/* setup HDMI audio */
-+static void setup_hdmi_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	struct audio_clock_info audio_clock_info = {0};
-+	uint32_t max_packets_per_line;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* For now still do calculation, although this field is ignored when
-+	above HDMI_PACKET_GEN_VERSION set to 1 */
-+	max_packets_per_line =
-+		dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+			hw_ctx,
-+			crtc_info);
-+
-+	/* HDMI_AUDIO_PACKET_CONTROL */
-+	{
-+		addr =
-+			mmHDMI_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, max_packets_per_line,
-+			HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_PACKETS_PER_LINE);
-+		/* still apply RS600's default setting which is 1. */
-+		set_reg_field_value(value, 1,
-+			HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_DELAY_EN);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+			AFMT_AUDIO_PACKET_CONTROL,
-+			AFMT_60958_CS_UPDATE);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 0,
-+				AFMT_AUDIO_PACKET_CONTROL2,
-+				AFMT_AUDIO_LAYOUT_OVRD);
-+
-+		/*Register field changed.*/
-+		set_reg_field_value(value, 0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_60958_OSF_OVRD);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* HDMI_ACR_PACKET_CONTROL */
-+	{
-+		addr = mmHDMI_ACR_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 1,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUTO_SEND);
-+
-+		/* Set HDMI_ACR_SOURCE to 0, to use hardwre
-+		 *  computed CTS values.*/
-+		set_reg_field_value(value, 0,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_SOURCE);
-+
-+		/* For now clear HDMI_ACR_AUDIO_PRIORITY =>ACR packet has
-+		higher priority over Audio Sample */
-+		set_reg_field_value(value, 0,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUDIO_PRIORITY);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Program audio clock sample/regeneration parameters */
-+	if (dal_audio_hw_ctx_get_audio_clock_info(
-+		hw_ctx,
-+		crtc_info->color_depth,
-+		crtc_info->requested_pixel_clock,
-+		crtc_info->calculated_pixel_clock,
-+		&audio_clock_info)) {
-+
-+		/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
-+		{
-+			addr = mmHDMI_ACR_32_0 + engine_offset[engine_id];
-+
-+			value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+			set_reg_field_value(value, audio_clock_info.cts_32khz,
-+				HDMI_ACR_32_0,
-+				HDMI_ACR_CTS_32);
-+
-+			dal_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
-+		{
-+			addr = mmHDMI_ACR_32_1 + engine_offset[engine_id];
-+
-+			value = dal_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_32khz,
-+				HDMI_ACR_32_1,
-+				HDMI_ACR_N_32);
-+
-+			dal_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
-+		{
-+			addr = mmHDMI_ACR_44_0 + engine_offset[engine_id];
-+
-+			value = dal_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.cts_44khz,
-+				HDMI_ACR_44_0,
-+				HDMI_ACR_CTS_44);
-+
-+			dal_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
-+		{
-+			addr = mmHDMI_ACR_44_1 + engine_offset[engine_id];
-+
-+			value = dal_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_44khz,
-+				HDMI_ACR_44_1,
-+				HDMI_ACR_N_44);
-+
-+			dal_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
-+		{
-+			addr = mmHDMI_ACR_48_0 + engine_offset[engine_id];
-+
-+			value = dal_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.cts_48khz,
-+				HDMI_ACR_48_0,
-+				HDMI_ACR_CTS_48);
-+
-+			dal_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
-+		{
-+			addr = mmHDMI_ACR_48_1 + engine_offset[engine_id];
-+
-+			value = dal_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_48khz,
-+				HDMI_ACR_48_1,
-+				HDMI_ACR_N_48);
-+
-+			dal_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* Video driver cannot know in advance which sample rate will
-+		be used by HD Audio driver
-+		HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
-+		programmed below in interruppt callback */
-+	} /* if */
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
-+	AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	{
-+		addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 1,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CHANNEL_NUMBER_L);
-+
-+		 /*HW default */
-+		set_reg_field_value(value, 0,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
-+	{
-+		addr = mmAFMT_60958_1 + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 2,
-+			AFMT_60958_1,
-+			AFMT_60958_CS_CHANNEL_NUMBER_R);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/*AFMT_60958_2 now keep this settings until
-+	 *  Programming guide comes out*/
-+	{
-+		addr = mmAFMT_60958_2 + engine_offset[engine_id];
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 3,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_2);
-+
-+		set_reg_field_value(value, 4,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_3);
-+
-+		set_reg_field_value(value, 5,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_4);
-+
-+		set_reg_field_value(value, 6,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_5);
-+
-+		set_reg_field_value(value, 7,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_6);
-+
-+		set_reg_field_value(value, 8,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_7);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+ /* setup DP audio */
-+static void setup_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/* --- DP Audio packet configurations --- */
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* ATP Configuration */
-+	{
-+		addr = mmDP_SEC_AUD_N + engine_offset[engine_id];
-+
-+		set_reg_field_value(value,
-+			DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT,
-+			DP_SEC_AUD_N,
-+			DP_SEC_AUD_N);
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Async/auto-calc timestamp mode */
-+	{
-+		addr = mmDP_SEC_TIMESTAMP +
-+			engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		set_reg_field_value(value,
-+			DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC,
-+			DP_SEC_TIMESTAMP,
-+			DP_SEC_TIMESTAMP_MODE);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* --- The following are the registers
-+	 *  copied from the SetupHDMI --- */
-+
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+			engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			1,
-+			AFMT_AUDIO_PACKET_CONTROL,
-+			AFMT_60958_CS_UPDATE);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	{
-+		addr =
-+			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_LAYOUT_OVRD);
-+
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_60958_OSF_OVRD);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_INFOFRAME_CONTROL0 */
-+	{
-+		addr =
-+			mmAFMT_INFOFRAME_CONTROL0 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value,
-+			1,
-+			AFMT_INFOFRAME_CONTROL0,
-+			AFMT_AUDIO_INFO_UPDATE);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	{
-+		addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+ /* setup VCE audio */
-+static void setup_vce_audio(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	struct dc_context *ctx = hw_ctx->ctx;
-+
-+	NOT_IMPLEMENTED();
-+
-+	/*TODO:
-+	const uint32_t addr = mmDOUT_DCE_VCE_CONTROL;
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+			addr);
-+
-+	set_reg_field_value(value,
-+		FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+		DOUT_DCE_VCE_CONTROL,
-+		DC_VCE_AUDIO_STREAM_SELECT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+			addr, value);*/
-+}
-+
-+static void enable_afmt_clock(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	bool enable_flag)
-+{
-+	uint32_t engine_offs = engine_offset[engine_id];
-+	uint32_t value;
-+	uint32_t count = 0;
-+	uint32_t enable = enable_flag ? 1:0;
-+
-+	/* Enable Audio packets*/
-+	value = dal_read_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs);
-+
-+	/*enable AFMT clock*/
-+	set_reg_field_value(value, enable,
-+		AFMT_CNTL, AFMT_AUDIO_CLOCK_EN);
-+	dal_write_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs, value);
-+
-+	/*wait for AFMT clock to turn on,
-+	 * the expectation is that this
-+	 * should complete in 1-2 reads)
-+	 */
-+	do {
-+		/* Wait for 1us between subsequent register reads.*/
-+		dc_service_delay_in_microseconds(hw_ctx->ctx, 1);
-+		value = dal_read_reg(hw_ctx->ctx,
-+				mmAFMT_CNTL + engine_offs);
-+	} while (get_reg_field_value(value,
-+				AFMT_CNTL, AFMT_AUDIO_CLOCK_ON) !=
-+						enable && count++ < 10);
-+}
-+
-+/* enable Azalia audio */
-+static void enable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	uint32_t value;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	if (get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED) != 1)
-+		set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		value);
-+}
-+
-+/* disable Azalia audio */
-+static void disable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	uint32_t value;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	set_reg_field_value(value, 0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		AUDIO_ENABLED);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		value);
-+}
-+
-+/* enable DP audio */
-+static void enable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+	uint32_t value;
-+
-+	/* Enable Audio packets */
-+	value = dal_read_reg(hw_ctx->ctx, addr);
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_ASP_ENABLE);
-+
-+	dal_write_reg(hw_ctx->ctx, addr, value);
-+
-+	/* Program the ATP and AIP next */
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_ATP_ENABLE);
-+
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_AIP_ENABLE);
-+
-+	dal_write_reg(hw_ctx->ctx, addr, value);
-+
-+	/* Program STREAM_ENABLE after all the other enables. */
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_STREAM_ENABLE);
-+
-+	dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* disable DP audio */
-+static void disable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+	uint32_t value;
-+
-+	/* Disable Audio packets */
-+	value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ASP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ATP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_AIP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ACM_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_STREAM_ENABLE);
-+
-+	/* This register shared with encoder info frame. Therefore we need to
-+	keep master enabled if at least on of the fields is not 0 */
-+	if (value != 0)
-+		set_reg_field_value(value, 1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+static void configure_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_info *audio_info)
-+{
-+	uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
-+	uint32_t value;
-+	uint32_t field = 0;
-+	enum audio_format_code audio_format_code;
-+	uint32_t format_index;
-+	uint32_t index;
-+	bool is_ac3_supported = false;
-+	bool is_audio_format_supported = false;
-+	union audio_sample_rates sample_rate;
-+	uint32_t strlen = 0;
-+
-+	/* Speaker Allocation */
-+	/*
-+	uint32_t value;
-+	uint32_t field = 0;*/
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
-+
-+	set_reg_field_value(value,
-+		speakers,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		SPEAKER_ALLOCATION);
-+
-+	/* LFE_PLAYBACK_LEVEL = LFEPBL
-+	 * LFEPBL = 0 : Unknown or refer to other information
-+	 * LFEPBL = 1 : 0dB playback
-+	 * LFEPBL = 2 : +10dB playback
-+	 * LFE_BL = 3 : Reserved
-+	 */
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		LFE_PLAYBACK_LEVEL);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		HDMI_CONNECTION);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		DP_CONNECTION);
-+
-+	field = get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+	field &= ~0x1;
-+
-+	set_reg_field_value(value,
-+		field,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+
-+	/* set audio for output signal */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		break;
-+	case SIGNAL_TYPE_WIRELESS: {
-+		/*LSB used for "is wireless" flag */
-+		field = 0;
-+		field = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+		field |= 0x1;
-+		set_reg_field_value(value,
-+			field,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		}
-+		break;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			DP_CONNECTION);
-+
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		value);
-+
-+	/* Wireless Display identification */
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION);
-+
-+	set_reg_field_value(value,
-+		signal == SIGNAL_TYPE_WIRELESS ? 1 : 0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION,
-+		WIRELESS_DISPLAY_IDENTIFICATION);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION,
-+		value);
-+
-+	/*  Audio Descriptors   */
-+	/* pass through all formats */
-+	for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
-+			format_index++) {
-+		audio_format_code =
-+			(AUDIO_FORMAT_CODE_FIRST + format_index);
-+
-+		/* those are unsupported, skip programming */
-+		if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
-+			audio_format_code == AUDIO_FORMAT_CODE_DST)
-+			continue;
-+
-+		value = 0;
-+
-+		/* check if supported */
-+		is_audio_format_supported =
-+			dal_audio_hw_ctx_is_audio_format_supported(
-+				hw_ctx,
-+				audio_info,
-+				audio_format_code, &index);
-+
-+		if (is_audio_format_supported) {
-+			const struct audio_mode *audio_mode =
-+					&audio_info->modes[index];
-+			union audio_sample_rates sample_rates =
-+					audio_mode->sample_rates;
-+			uint8_t byte2 = audio_mode->max_bit_rate;
-+
-+			/* adjust specific properties */
-+			switch (audio_format_code) {
-+			case AUDIO_FORMAT_CODE_LINEARPCM: {
-+				dal_hw_ctx_audio_check_audio_bandwidth(
-+					hw_ctx,
-+					crtc_info,
-+					audio_mode->channel_count,
-+					signal,
-+					&sample_rates);
-+
-+				byte2 = audio_mode->sample_size;
-+
-+				set_reg_field_value(value,
-+				sample_rates.all,
-+		AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+				SUPPORTED_FREQUENCIES_STEREO);
-+
-+				}
-+				break;
-+			case AUDIO_FORMAT_CODE_AC3:
-+				is_ac3_supported = true;
-+				break;
-+			case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
-+			case AUDIO_FORMAT_CODE_DTS_HD:
-+			case AUDIO_FORMAT_CODE_MAT_MLP:
-+			case AUDIO_FORMAT_CODE_DST:
-+			case AUDIO_FORMAT_CODE_WMAPRO:
-+				byte2 = audio_mode->vendor_specific;
-+				break;
-+			default:
-+				break;
-+			}
-+
-+			/* fill audio format data */
-+			set_reg_field_value(value,
-+			audio_mode->channel_count - 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			MAX_CHANNELS);
-+
-+			set_reg_field_value(value,
-+			sample_rates.all,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			SUPPORTED_FREQUENCIES);
-+
-+			set_reg_field_value(value,
-+			byte2,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			DESCRIPTOR_BYTE_2);
-+
-+		} /* if */
-+
-+		write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +
-+		format_index,
-+		value);
-+	} /* for */
-+
-+	if (is_ac3_supported)
-+		dal_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
-+		0x05);
-+
-+	/* check for 192khz/8-Ch support for HBR requirements */
-+	sample_rate.all = 0;
-+	sample_rate.rate.RATE_192 = 1;
-+	dal_hw_ctx_audio_check_audio_bandwidth(
-+		hw_ctx,
-+		crtc_info,
-+		8,
-+		signal,
-+		&sample_rate);
-+
-+	set_high_bit_rate_capable(hw_ctx, sample_rate.rate.RATE_192);
-+
-+	/* Audio and Video Lipsync */
-+	set_video_latency(hw_ctx, audio_info->video_latency);
-+	set_audio_latency(hw_ctx, audio_info->audio_latency);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->manufacture_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		MANUFACTURER_ID);
-+
-+	set_reg_field_value(value, audio_info->product_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		PRODUCT_ID);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		value);
-+
-+
-+	value = 0;
-+
-+	/*get display name string length */
-+	while (audio_info->display_name[strlen++] != '\0') {
-+		if (strlen >=
-+		MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
-+			break;
-+		}
-+	set_reg_field_value(value, strlen,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		SINK_DESCRIPTION_LEN);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		value);
-+
-+
-+	/*
-+	*write the port ID:
-+	*PORT_ID0 = display index
-+	*PORT_ID1 = 16bit BDF
-+	*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
-+	*/
-+
-+	value = 0;
-+
-+	set_reg_field_value(value, audio_info->port_id[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		PORT_ID0);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->port_id[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		PORT_ID1);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		value);
-+
-+	/*write the 18 char monitor string */
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION0);
-+
-+	set_reg_field_value(value, audio_info->display_name[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION1);
-+
-+	set_reg_field_value(value, audio_info->display_name[2],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION2);
-+
-+	set_reg_field_value(value, audio_info->display_name[3],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION3);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		value);
-+
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[4],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION4);
-+
-+	set_reg_field_value(value, audio_info->display_name[5],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION5);
-+
-+	set_reg_field_value(value, audio_info->display_name[6],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION6);
-+
-+	set_reg_field_value(value, audio_info->display_name[7],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION7);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[8],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION8);
-+
-+	set_reg_field_value(value, audio_info->display_name[9],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION9);
-+
-+	set_reg_field_value(value, audio_info->display_name[10],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION10);
-+
-+	set_reg_field_value(value, audio_info->display_name[11],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION11);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[12],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION12);
-+
-+	set_reg_field_value(value, audio_info->display_name[13],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION13);
-+
-+	set_reg_field_value(value, audio_info->display_name[14],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION14);
-+
-+	set_reg_field_value(value, audio_info->display_name[15],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION15);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		value);
-+
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[16],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION16);
-+
-+	set_reg_field_value(value, audio_info->display_name[17],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION17);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		value);
-+
-+}
-+
-+/* setup Azalia HW block */
-+static void setup_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info,
-+	const struct audio_info *audio_info)
-+{
-+	uint32_t speakers = 0;
-+	uint32_t channels = 0;
-+
-+	if (audio_info == NULL)
-+		/* This should not happen.it does so we don't get BSOD*/
-+		return;
-+
-+	speakers = audio_info->flags.info.ALLSPEAKERS;
-+	channels = dal_audio_hw_ctx_speakers_to_channels(
-+		hw_ctx,
-+		audio_info->flags.speaker_flags).all;
-+
-+	/* setup the audio stream source select (audio -> dig mapping) */
-+	{
-+		const uint32_t addr =
-+			mmAFMT_AUDIO_SRC_CONTROL + engine_offset[engine_id];
-+
-+		uint32_t value = 0;
-+		/*convert one-based index to zero-based */
-+		set_reg_field_value(value,
-+			FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+			AFMT_AUDIO_SRC_CONTROL,
-+			AFMT_AUDIO_SRC_SELECT);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Channel allocation */
-+	{
-+		const uint32_t addr =
-+			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+		uint32_t value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value,
-+			channels,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_CHANNEL_ENABLE);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	configure_azalia(hw_ctx, signal, crtc_info, audio_info);
-+}
-+
-+/* unmute audio */
-+static void unmute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+		engine_offset[engine_id];
-+
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 1,
-+		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+	dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* mute audio */
-+static void mute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+		engine_offset[engine_id];
-+
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+	dal_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* enable channel splitting mapping */
-+static void setup_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	uint32_t value = 0;
-+
-+	if ((audio_mapping == NULL || audio_mapping->u32all == 0) && enable)
-+		return;
-+
-+
-+	value = audio_mapping->u32all;
-+
-+	if (enable == false)
-+		/*0xFFFFFFFF;*/
-+		value = MULTI_CHANNEL_SPLIT_NO_ASSO_INFO;
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+		value);
-+}
-+
-+/* get current channel spliting */
-+static bool get_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	uint32_t value = 0;
-+
-+	if (audio_mapping == NULL)
-+		return false;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO);
-+
-+	/*0xFFFFFFFF*/
-+	if (get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+			ASSOCIATION_INFO) !=
-+			MULTI_CHANNEL_SPLIT_NO_ASSO_INFO) {
-+		uint32_t multi_channel01_enable = 0;
-+		uint32_t multi_channel23_enable = 0;
-+		uint32_t multi_channel45_enable = 0;
-+		uint32_t multi_channel67_enable = 0;
-+		/* get the one we set.*/
-+		audio_mapping->u32all = value;
-+
-+		/* check each enable status*/
-+		value = read_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE);
-+
-+		multi_channel01_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL01_ENABLE);
-+
-+		multi_channel23_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL23_ENABLE);
-+
-+		multi_channel45_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL45_ENABLE);
-+
-+		multi_channel67_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL67_ENABLE);
-+
-+		if (multi_channel01_enable == 0 &&
-+			multi_channel23_enable == 0 &&
-+			multi_channel45_enable == 0 &&
-+			multi_channel67_enable == 0)
-+			dal_logger_write(hw_ctx->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_COMPONENT_AUDIO,
-+				"Audio driver did not enable multi-channel\n");
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+/* set the payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum audio_payload payload)
-+{
-+	/* set the payload value for the unsolicited response
-+	 Jack presence is not required to be enabled */
-+	uint32_t value = 0;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE);
-+
-+	set_reg_field_value(value, payload,
-+		AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		UNSOLICITED_RESPONSE_PAYLOAD);
-+
-+	set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		UNSOLICITED_RESPONSE_FORCE);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		value);
-+}
-+
-+/* initialize HW state */
-+static void hw_initialize(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t stream_id = FROM_BASE(hw_ctx)->azalia_stream_id;
-+	uint32_t addr;
-+
-+	/* we only need to program the following registers once, so we only do
-+	it for the first audio stream.*/
-+	if (stream_id != FIRST_AUDIO_STREAM_ID)
-+		return;
-+
-+	/* Suport R5 - 32khz
-+	 * Suport R6 - 44.1khz
-+	 * Suport R7 - 48khz
-+	 */
-+	addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
-+	{
-+		uint32_t value;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 0x70,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
-+		AUDIO_RATE_CAPABILITIES);
-+
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/*Keep alive bit to verify HW block in BU. */
-+	addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
-+	{
-+		uint32_t value;
-+
-+		value = dal_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+		CLKSTOP);
-+
-+		set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+		EPSS);
-+		dal_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+/* Assign GTC group and enable GTC value embedding */
-+static void enable_gtc_embedding_with_group(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t group_num,
-+	uint32_t audio_latency)
-+{
-+	/*need to replace the static number with variable */
-+	if (group_num <= 6) {
-+		uint32_t value = read_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+		set_reg_field_value(
-+			value,
-+			group_num,
-+			AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+		write_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			value);
-+
-+		/*update audio latency to LIPSYNC*/
-+		set_audio_latency(hw_ctx, audio_latency);
-+	} else {
-+		dal_logger_write(
-+			hw_ctx->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_COMPONENT_AUDIO,
-+			"GTC group number %d is too big",
-+			group_num);
-+	}
-+}
-+
-+ /* Disable GTC value embedding */
-+static void disable_gtc_embedding(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t value = 0;
-+
-+	value = read_indirect_azalia_reg(
-+	hw_ctx,
-+	ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+	set_reg_field_value(value, 0,
-+	AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+	PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+	AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+	PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+		value);
-+}
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	if (azalia_clock_info == NULL)
-+		return false;
-+
-+	/* audio_dto_phase= 24 * 10,000;
-+	 *   24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase =
-+			24 * 10000;
-+
-+	/* audio_dto_module = PCLKFrequency * 10,000;
-+	 *  [khz] -> [100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+			actual_pixel_clock_in_khz * 10;
-+
-+	return true;
-+}
-+
-+/* search pixel clock value for Azalia DP Audio */
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	if (pll_info == NULL || azalia_clock_info == NULL)
-+		return false;
-+
-+	/* Reported dpDtoSourceClockInkhz value for
-+	 * DCE8 already adjusted for SS, do not need any
-+	 * adjustment here anymore
-+	 */
-+
-+	/*audio_dto_phase = 24 * 10,000;
-+	 * 24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase = 24 * 10000;
-+
-+	/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
-+	 *  [khz] ->[100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+		pll_info->dp_dto_source_clock_in_khz * 10;
-+
-+	return true;
-+}
-+
-+static const struct hw_ctx_audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup_audio_wall_dto =
-+		setup_audio_wall_dto,
-+	.setup_hdmi_audio =
-+		setup_hdmi_audio,
-+	.setup_dp_audio = setup_dp_audio,
-+	.setup_vce_audio = setup_vce_audio,
-+	.enable_azalia_audio =
-+		enable_azalia_audio,
-+	.disable_azalia_audio =
-+		disable_azalia_audio,
-+	.enable_dp_audio =
-+		enable_dp_audio,
-+	.disable_dp_audio =
-+		disable_dp_audio,
-+	.setup_azalia =
-+		setup_azalia,
-+	.disable_az_clock_gating = NULL,
-+	.unmute_azalia_audio =
-+		unmute_azalia_audio,
-+	.mute_azalia_audio =
-+		mute_azalia_audio,
-+	.setup_channel_splitting_mapping =
-+		setup_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.hw_initialize =
-+		hw_initialize,
-+	.enable_gtc_embedding_with_group =
-+		enable_gtc_embedding_with_group,
-+	.disable_gtc_embedding =
-+		disable_gtc_embedding,
-+	.get_azalia_clock_info_hdmi =
-+		get_azalia_clock_info_hdmi,
-+	.get_azalia_clock_info_dp =
-+		get_azalia_clock_info_dp,
-+	.enable_afmt_clock = enable_afmt_clock
-+};
-+
-+static bool construct(
-+	struct hw_ctx_audio_dce110 *hw_ctx,
-+	uint8_t azalia_stream_id,
-+	struct dc_context *ctx)
-+{
-+	struct hw_ctx_audio *base = &hw_ctx->base;
-+
-+	if (!dal_audio_construct_hw_ctx_audio(base))
-+		return false;
-+
-+	base->funcs = &funcs;
-+
-+	/* save audio endpoint or dig front for current dce110 audio object */
-+	hw_ctx->azalia_stream_id = azalia_stream_id;
-+	hw_ctx->base.ctx = ctx;
-+
-+	/* azalia audio endpoints register offsets. azalia is associated with
-+	DIG front. save AUDIO register offset */
-+	switch (azalia_stream_id) {
-+	case 1: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 2: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 3: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 4: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	default:
-+		dal_logger_write(
-+			hw_ctx->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_AUDIO,
-+			"Invalid Azalia stream ID!");
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+/* audio_dce110 is derived from audio directly, not via dce80  */
-+struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
-+	struct dc_context *ctx,
-+	uint32_t azalia_stream_id)
-+{
-+	/* allocate memory for struc hw_ctx_audio_dce110 */
-+	struct hw_ctx_audio_dce110 *hw_ctx_dce110 =
-+			dc_service_alloc(ctx, sizeof(struct hw_ctx_audio_dce110));
-+
-+	if (!hw_ctx_dce110) {
-+		ASSERT_CRITICAL(hw_ctx_dce110);
-+		return NULL;
-+	}
-+
-+	/*return pointer to hw_ctx_audio back to caller  -- audio object */
-+	if (construct(
-+			hw_ctx_dce110, azalia_stream_id, ctx))
-+		return &hw_ctx_dce110->base;
-+
-+	dal_logger_write(
-+		ctx->logger,
-+		LOG_MAJOR_ERROR,
-+		LOG_MINOR_COMPONENT_AUDIO,
-+		"Failed to create hw_ctx_audio for DCE11\n");
-+
-+
-+	dc_service_free(ctx, hw_ctx_dce110);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
-new file mode 100644
-index 0000000..1ad3826
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_AUDIO_DCE110_H__
-+#define __DAL_HW_CTX_AUDIO_DCE110_H__
-+
-+#include "audio/hw_ctx_audio.h"
-+
-+struct hw_ctx_audio_dce110 {
-+	struct hw_ctx_audio base;
-+
-+	/* azalia stream id 1 based indexing, corresponding to audio GO enumId*/
-+	uint32_t azalia_stream_id;
-+
-+	/* azalia stream endpoint register offsets */
-+	struct azalia_reg_offsets az_mm_reg_offsets;
-+
-+	/* audio encoder block MM register offset -- associate with DIG FRONT */
-+};
-+
-+struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
-+	struct dc_context *ctx,
-+	uint32_t azalia_stream_id);
-+
-+#endif  /* __DAL_HW_CTX_AUDIO_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-new file mode 100644
-index 0000000..f1f1298
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-@@ -0,0 +1,771 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "hw_ctx_audio.h"
-+
-+/* 25.2MHz/1.001*/
-+/* 25.2MHz/1.001*/
-+/* 25.2MHz*/
-+/* 27MHz */
-+/* 27MHz*1.001*/
-+/* 27MHz*1.001*/
-+/* 54MHz*/
-+/* 54MHz*1.001*/
-+/* 74.25MHz/1.001*/
-+/* 74.25MHz*/
-+/* 148.5MHz/1.001*/
-+/* 148.5MHz*/
-+
-+static const struct audio_clock_info audio_clock_info_table[12] = {
-+	{2517, 4576, 28125, 7007, 31250, 6864, 28125},
-+	{2518, 4576, 28125, 7007, 31250, 6864, 28125},
-+	{2520, 4096, 25200, 6272, 28000, 6144, 25200},
-+	{2700, 4096, 27000, 6272, 30000, 6144, 27000},
-+	{2702, 4096, 27027, 6272, 30030, 6144, 27027},
-+	{2703, 4096, 27027, 6272, 30030, 6144, 27027},
-+	{5400, 4096, 54000, 6272, 60000, 6144, 54000},
-+	{5405, 4096, 54054, 6272, 60060, 6144, 54054},
-+	{7417, 11648, 210937, 17836, 234375, 11648, 140625},
-+	{7425, 4096, 74250, 6272, 82500, 6144, 74250},
-+	{14835, 11648, 421875, 8918, 234375, 5824, 140625},
-+	{14850, 4096, 148500, 6272, 165000, 6144, 148500}
-+};
-+
-+static const struct audio_clock_info audio_clock_info_table_36bpc[12] = {
-+	{2517, 9152, 84375, 7007, 48875, 9152, 56250},
-+	{2518, 9152, 84375, 7007, 48875, 9152, 56250},
-+	{2520, 4096, 37800, 6272, 42000, 6144, 37800},
-+	{2700, 4096, 40500, 6272, 45000, 6144, 40500},
-+	{2702, 8192, 81081, 6272, 45045, 8192, 54054},
-+	{2703, 8192, 81081, 6272, 45045, 8192, 54054},
-+	{5400, 4096, 81000, 6272, 90000, 6144, 81000},
-+	{5405, 4096, 81081, 6272, 90090, 6144, 81081},
-+	{7417, 11648, 316406, 17836, 351562, 11648, 210937},
-+	{7425, 4096, 111375, 6272, 123750, 6144, 111375},
-+	{14835, 11648, 632812, 17836, 703125, 11648, 421875},
-+	{14850, 4096, 222750, 6272, 247500, 6144, 222750}
-+};
-+
-+static const struct audio_clock_info audio_clock_info_table_48bpc[12] = {
-+	{2517, 4576, 56250, 7007, 62500, 6864, 56250},
-+	{2518, 4576, 56250, 7007, 62500, 6864, 56250},
-+	{2520, 4096, 50400, 6272, 56000, 6144, 50400},
-+	{2700, 4096, 54000, 6272, 60000, 6144, 54000},
-+	{2702, 4096, 54054, 6267, 60060, 8192, 54054},
-+	{2703, 4096, 54054, 6272, 60060, 8192, 54054},
-+	{5400, 4096, 108000, 6272, 120000, 6144, 108000},
-+	{5405, 4096, 108108, 6272, 120120, 6144, 108108},
-+	{7417, 11648, 421875, 17836, 468750, 11648, 281250},
-+	{7425, 4096, 148500, 6272, 165000, 6144, 148500},
-+	{14835, 11648, 843750, 8918, 468750, 11648, 281250},
-+	{14850, 4096, 297000, 6272, 330000, 6144, 297000}
-+};
-+
-+
-+/***** static function *****/
-+
-+/*
-+ * except of HW context create function, caller will access other functions of
-+ * hw ctx via handle hw_ctx. Memory allocation for struct hw_ctx_audio_dce8x
-+ * will happen in hw_ctx_audio_dce8x. Memory allocation is done with
-+ * dal_audio_create_hw_ctx_audio_dce8x. Memory release is done by caller
-+ * via hw_ctx->functions.destroy(). It will finally use destroy() of
-+ * hw_ctx_audio_dce8x. Therefore, no memory allocate and release happen
-+ * physically at hw ctx base object.
-+ */
-+static void destroy(
-+	struct hw_ctx_audio **ptr)
-+{
-+	/* Attention!
-+	 * You must override this method in derived class */
-+}
-+
-+static void setup_audio_wall_dto(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* setup HDMI audio */
-+static void setup_hdmi_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+ /* setup DP audio */
-+static void setup_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+ /* setup VCE audio */
-+static void setup_vce_audio(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* enable Azalia audio */
-+static void enable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* disable Azalia audio */
-+static void disable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* enable DP audio */
-+static void enable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* disable DP audio */
-+static void disable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* setup Azalia HW block */
-+static void setup_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info,
-+	const struct audio_info *audio_info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* unmute audio */
-+static void unmute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* mute audio */
-+static void mute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* enable channel splitting mapping */
-+static void setup_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* get current channel spliting */
-+static bool get_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+/* set the payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum audio_payload payload)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* initialize HW state */
-+static void hw_initialize(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* Assign GTC group and enable GTC value embedding */
-+static void enable_gtc_embedding_with_group(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t groupNum,
-+	uint32_t audioLatency)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* Disable GTC value embedding */
-+static void disable_gtc_embedding(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* Disable Azalia Clock Gating Feature */
-+static void disable_az_clock_gating(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+/* search pixel clock value for Azalia DP Audio */
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	/*DCE specific, must be implemented in derived*/
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+/*****SCOPE : within audio hw context dal-audio-hw-ctx *****/
-+
-+
-+/* check whether specified sample rates can fit into a given timing */
-+void dal_hw_ctx_audio_check_audio_bandwidth(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	enum signal_type signal,
-+	union audio_sample_rates *sample_rates)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		dal_audio_hw_ctx_check_audio_bandwidth_hdmi(
-+			hw_ctx, crtc_info, channel_count, sample_rates);
-+		break;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		dal_audio_hw_ctx_check_audio_bandwidth_dpsst(
-+			hw_ctx, crtc_info, channel_count, sample_rates);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		dal_audio_hw_ctx_check_audio_bandwidth_dpmst(
-+			hw_ctx,  crtc_info, channel_count, sample_rates);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+/*For HDMI, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates)
-+{
-+	uint32_t samples;
-+	uint32_t  h_blank;
-+	bool limit_freq_to_48_khz = false;
-+	bool limit_freq_to_88_2_khz = false;
-+	bool limit_freq_to_96_khz = false;
-+	bool limit_freq_to_174_4_khz = false;
-+
-+	/* For two channels supported return whatever sink support,unmodified*/
-+	if (channel_count > 2) {
-+
-+		/* Based on HDMI spec 1.3 Table 7.5 */
-+		if ((crtc_info->requested_pixel_clock <= 27000) &&
-+		(crtc_info->v_active <= 576) &&
-+		!(crtc_info->interlaced) &&
-+		!(crtc_info->pixel_repetition == 2 ||
-+		crtc_info->pixel_repetition == 4)) {
-+			limit_freq_to_48_khz = true;
-+
-+		} else if ((crtc_info->requested_pixel_clock <= 27000) &&
-+				(crtc_info->v_active <= 576) &&
-+				(crtc_info->interlaced) &&
-+				(crtc_info->pixel_repetition == 2)) {
-+			limit_freq_to_88_2_khz = true;
-+
-+		} else if ((crtc_info->requested_pixel_clock <= 54000) &&
-+				(crtc_info->v_active <= 576) &&
-+				!(crtc_info->interlaced)) {
-+			limit_freq_to_174_4_khz = true;
-+		}
-+	}
-+
-+	/* Also do some calculation for the available Audio Bandwidth for the
-+	 * 8 ch (i.e. for the Layout 1 => ch > 2)
-+	 */
-+	h_blank = crtc_info->h_total - crtc_info->h_active;
-+
-+	if (crtc_info->pixel_repetition)
-+		h_blank *= crtc_info->pixel_repetition;
-+
-+	/*based on HDMI spec 1.3 Table 7.5 */
-+	h_blank -= 58;
-+	/*for Control Period */
-+	h_blank -= 16;
-+
-+	samples = h_blank * 10;
-+	/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
-+	 * of Audio samples per line multiplied by 10 - Layout 1)
-+	 */
-+	 samples /= 32;
-+	 samples *= crtc_info->v_active;
-+	 /*Number of samples multiplied by 10, per second */
-+	 samples *= crtc_info->refresh_rate;
-+	 /*Number of Audio samples per second */
-+	 samples /= 10;
-+
-+	 /* @todo do it after deep color is implemented
-+	  * 8xx - deep color bandwidth scaling
-+	  * Extra bandwidth is avaliable in deep color b/c link runs faster than
-+	  * pixel rate. This has the effect of allowing more tmds characters to
-+	  * be transmitted during blank
-+	  */
-+
-+	switch (crtc_info->color_depth) {
-+	case COLOR_DEPTH_888:
-+		samples *= 4;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		samples *= 5;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		samples *= 6;
-+		break;
-+	default:
-+		samples *= 4;
-+		break;
-+	}
-+
-+	samples /= 4;
-+
-+	/*check limitation*/
-+	if (samples < 88200)
-+		limit_freq_to_48_khz = true;
-+	else if (samples < 96000)
-+		limit_freq_to_88_2_khz = true;
-+	else if (samples < 176400)
-+		limit_freq_to_96_khz = true;
-+	else if (samples < 192000)
-+		limit_freq_to_174_4_khz = true;
-+
-+	if (sample_rates != NULL) {
-+		/* limit frequencies */
-+		if (limit_freq_to_174_4_khz)
-+			sample_rates->rate.RATE_192 = 0;
-+
-+		if (limit_freq_to_96_khz) {
-+			sample_rates->rate.RATE_192 = 0;
-+			sample_rates->rate.RATE_176_4 = 0;
-+		}
-+		if (limit_freq_to_88_2_khz) {
-+			sample_rates->rate.RATE_192 = 0;
-+			sample_rates->rate.RATE_176_4 = 0;
-+			sample_rates->rate.RATE_96 = 0;
-+		}
-+		if (limit_freq_to_48_khz) {
-+			sample_rates->rate.RATE_192 = 0;
-+			sample_rates->rate.RATE_176_4 = 0;
-+			sample_rates->rate.RATE_96 = 0;
-+			sample_rates->rate.RATE_88_2 = 0;
-+		}
-+	}
-+}
-+
-+/*For DP SST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpsst(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates)
-+{
-+	/* do nothing */
-+}
-+
-+/*For DP MST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpmst(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates)
-+{
-+	/* do nothing  */
-+}
-+
-+/* calculate max number of Audio packets per line */
-+uint32_t dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	uint32_t max_packets_per_line;
-+
-+	max_packets_per_line =
-+		crtc_info->h_total - crtc_info->h_active;
-+
-+	if (crtc_info->pixel_repetition)
-+		max_packets_per_line *= crtc_info->pixel_repetition;
-+
-+	/* for other hdmi features */
-+	max_packets_per_line -= 58;
-+	/* for Control Period */
-+	max_packets_per_line -= 16;
-+	/* Number of Audio Packets per Line */
-+	max_packets_per_line /= 32;
-+
-+	return max_packets_per_line;
-+}
-+
-+/**
-+* speakersToChannels
-+*
-+* @brief
-+*  translate speakers to channels
-+*
-+*  FL  - Front Left
-+*  FR  - Front Right
-+*  RL  - Rear Left
-+*  RR  - Rear Right
-+*  RC  - Rear Center
-+*  FC  - Front Center
-+*  FLC - Front Left Center
-+*  FRC - Front Right Center
-+*  RLC - Rear Left Center
-+*  RRC - Rear Right Center
-+*  LFE - Low Freq Effect
-+*
-+*               FC
-+*          FLC      FRC
-+*    FL                    FR
-+*
-+*                    LFE
-+*              ()
-+*
-+*
-+*    RL                    RR
-+*          RLC      RRC
-+*               RC
-+*
-+*             ch  8   7   6   5   4   3   2   1
-+* 0b00000011      -   -   -   -   -   -   FR  FL
-+* 0b00000111      -   -   -   -   -   LFE FR  FL
-+* 0b00001011      -   -   -   -   FC  -   FR  FL
-+* 0b00001111      -   -   -   -   FC  LFE FR  FL
-+* 0b00010011      -   -   -   RC  -   -   FR  FL
-+* 0b00010111      -   -   -   RC  -   LFE FR  FL
-+* 0b00011011      -   -   -   RC  FC  -   FR  FL
-+* 0b00011111      -   -   -   RC  FC  LFE FR  FL
-+* 0b00110011      -   -   RR  RL  -   -   FR  FL
-+* 0b00110111      -   -   RR  RL  -   LFE FR  FL
-+* 0b00111011      -   -   RR  RL  FC  -   FR  FL
-+* 0b00111111      -   -   RR  RL  FC  LFE FR  FL
-+* 0b01110011      -   RC  RR  RL  -   -   FR  FL
-+* 0b01110111      -   RC  RR  RL  -   LFE FR  FL
-+* 0b01111011      -   RC  RR  RL  FC  -   FR  FL
-+* 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
-+* 0b11110011      RRC RLC RR  RL  -   -   FR  FL
-+* 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
-+* 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
-+* 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
-+* 0b11000011      FRC FLC -   -   -   -   FR  FL
-+* 0b11000111      FRC FLC -   -   -   LFE FR  FL
-+* 0b11001011      FRC FLC -   -   FC  -   FR  FL
-+* 0b11001111      FRC FLC -   -   FC  LFE FR  FL
-+* 0b11010011      FRC FLC -   RC  -   -   FR  FL
-+* 0b11010111      FRC FLC -   RC  -   LFE FR  FL
-+* 0b11011011      FRC FLC -   RC  FC  -   FR  FL
-+* 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
-+* 0b11110011      FRC FLC RR  RL  -   -   FR  FL
-+* 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
-+* 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
-+* 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
-+*
-+* @param
-+*  speakers - speaker information as it comes from CEA audio block
-+*/
-+/* translate speakers to channels */
-+union audio_cea_channels dal_audio_hw_ctx_speakers_to_channels(
-+	const struct hw_ctx_audio *hw_ctx,
-+	struct audio_speaker_flags speaker_flags)
-+{
-+	union audio_cea_channels cea_channels = {0};
-+
-+	/* these are one to one */
-+	cea_channels.channels.FL = speaker_flags.FL_FR;
-+	cea_channels.channels.FR = speaker_flags.FL_FR;
-+	cea_channels.channels.LFE = speaker_flags.LFE;
-+	cea_channels.channels.FC = speaker_flags.FC;
-+
-+	/* if Rear Left and Right exist move RC speaker to channel 7
-+	 * otherwise to channel 5
-+	 */
-+	if (speaker_flags.RL_RR) {
-+		cea_channels.channels.RL_RC = speaker_flags.RL_RR;
-+		cea_channels.channels.RR = speaker_flags.RL_RR;
-+		cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
-+	} else {
-+		cea_channels.channels.RL_RC = speaker_flags.RC;
-+	}
-+
-+	/* FRONT Left Right Center and REAR Left Right Center are exclusive */
-+	if (speaker_flags.FLC_FRC) {
-+		cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
-+		cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
-+	} else {
-+		cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
-+		cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
-+	}
-+
-+	return cea_channels;
-+}
-+
-+/* check whether specified audio format supported */
-+bool dal_audio_hw_ctx_is_audio_format_supported(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_info *audio_info,
-+	enum audio_format_code audio_format_code,
-+	uint32_t *format_index)
-+{
-+	uint32_t index;
-+	uint32_t max_channe_index = 0;
-+	bool found = false;
-+
-+	if (audio_info == NULL)
-+		return found;
-+
-+	/* pass through whole array */
-+	for (index = 0; index < audio_info->mode_count; index++) {
-+		if (audio_info->modes[index].format_code == audio_format_code) {
-+			if (found) {
-+				/* format has multiply entries, choose one with
-+				 *  highst number of channels */
-+				if (audio_info->modes[index].channel_count >
-+		audio_info->modes[max_channe_index].channel_count) {
-+					max_channe_index = index;
-+				}
-+			} else {
-+				/* format found, save it's index */
-+				found = true;
-+				max_channe_index = index;
-+			}
-+		}
-+	}
-+
-+	/* return index */
-+	if (found && format_index != NULL)
-+		*format_index = max_channe_index;
-+
-+	return found;
-+}
-+
-+/* search pixel clock value for HDMI */
-+bool dal_audio_hw_ctx_get_audio_clock_info(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum dc_color_depth color_depth,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct audio_clock_info *audio_clock_info)
-+{
-+	const struct audio_clock_info *clock_info;
-+	uint32_t index;
-+	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
-+	uint32_t audio_array_size;
-+
-+	if (audio_clock_info == NULL)
-+		return false; /* should not happen */
-+
-+	switch (color_depth) {
-+	case COLOR_DEPTH_161616:
-+		clock_info = audio_clock_info_table_48bpc;
-+		audio_array_size = ARRAY_SIZE(
-+				audio_clock_info_table_48bpc);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		clock_info = audio_clock_info_table_36bpc;
-+		audio_array_size = ARRAY_SIZE(
-+				audio_clock_info_table_36bpc);
-+		break;
-+	default:
-+		clock_info = audio_clock_info_table;
-+		audio_array_size = ARRAY_SIZE(
-+				audio_clock_info_table);
-+		break;
-+	}
-+
-+	if (clock_info != NULL) {
-+		/* search for exact pixel clock in table */
-+		for (index = 0; index < audio_array_size; index++) {
-+			if (clock_info[index].pixel_clock_in_10khz >
-+				crtc_pixel_clock_in_10khz)
-+				break;  /* not match */
-+			else if (clock_info[index].pixel_clock_in_10khz ==
-+					crtc_pixel_clock_in_10khz) {
-+				/* match found */
-+				if (audio_clock_info != NULL) {
-+					*audio_clock_info = clock_info[index];
-+					return true;
-+				}
-+			}
-+		}
-+	}
-+
-+
-+	/* not found */
-+	if (actual_pixel_clock_in_khz == 0)
-+		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
-+
-+	/* See HDMI spec  the table entry under
-+	 *  pixel clock of "Other". */
-+	audio_clock_info->pixel_clock_in_10khz =
-+			actual_pixel_clock_in_khz / 10;
-+	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
-+	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
-+	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
-+
-+	audio_clock_info->n_32khz = 4096;
-+	audio_clock_info->n_44khz = 6272;
-+	audio_clock_info->n_48khz = 6144;
-+
-+	return true;
-+}
-+
-+static const struct hw_ctx_audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup_audio_wall_dto =
-+		setup_audio_wall_dto,
-+	.setup_hdmi_audio =
-+		setup_hdmi_audio,
-+	.setup_dp_audio = setup_dp_audio,
-+	.setup_vce_audio = setup_vce_audio,
-+	.enable_azalia_audio =
-+		enable_azalia_audio,
-+	.disable_azalia_audio =
-+		disable_azalia_audio,
-+	.enable_dp_audio =
-+		enable_dp_audio,
-+	.disable_dp_audio =
-+		disable_dp_audio,
-+	.setup_azalia =
-+		setup_azalia,
-+	.disable_az_clock_gating =
-+		disable_az_clock_gating,
-+	.unmute_azalia_audio =
-+		unmute_azalia_audio,
-+	.mute_azalia_audio =
-+		mute_azalia_audio,
-+	.setup_channel_splitting_mapping =
-+		setup_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.hw_initialize =
-+		hw_initialize,
-+	.enable_gtc_embedding_with_group =
-+		enable_gtc_embedding_with_group,
-+	.disable_gtc_embedding =
-+		disable_gtc_embedding,
-+	.get_azalia_clock_info_hdmi =
-+		get_azalia_clock_info_hdmi,
-+	.get_azalia_clock_info_dp =
-+		get_azalia_clock_info_dp,
-+};
-+/* --- object creator, destroy, construct, destruct --- */
-+
-+bool dal_audio_construct_hw_ctx_audio(
-+	struct hw_ctx_audio *ctx)
-+{
-+	ctx->funcs = &funcs;
-+
-+	/* internal variables */
-+
-+	return true;
-+}
-+
-+void dal_audio_destruct_hw_ctx_audio(
-+	struct hw_ctx_audio *ctx)
-+{
-+	/* nothing to do */
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-new file mode 100644
-index 0000000..8ab2e58
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-@@ -0,0 +1,285 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_AUDIO_H__
-+#define __DAL_HW_CTX_AUDIO_H__
-+
-+#include "include/audio_interface.h"
-+#include "include/link_service_types.h"
-+
-+struct hw_ctx_audio;
-+
-+
-+struct azalia_reg_offsets {
-+	uint32_t azf0endpointx_azalia_f0_codec_endpoint_index;
-+	uint32_t azf0endpointx_azalia_f0_codec_endpoint_data;
-+};
-+
-+/***** hook functions *****/
-+
-+struct hw_ctx_audio_funcs {
-+
-+	/* functions for hw_ctx creation */
-+	void (*destroy)(
-+		struct hw_ctx_audio **ptr);
-+
-+	/***** from dal2 hwcontextaudio.hpp *****/
-+
-+	void (*setup_audio_wall_dto)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum signal_type signal,
-+		const struct audio_crtc_info *crtc_info,
-+		const struct audio_pll_info *pll_info);
-+
-+	/* MM register access  read_register  write_register */
-+
-+	/***** from dal2 hwcontextaudio_hal.hpp *****/
-+
-+	/* setup HDMI audio */
-+	void (*setup_hdmi_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id,
-+		const struct audio_crtc_info *crtc_info);
-+
-+	/* setup DP audio */
-+	void (*setup_dp_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* setup VCE audio */
-+	void (*setup_vce_audio)(
-+		const struct hw_ctx_audio *hw_ctx);
-+
-+	/* enable Azalia audio */
-+	void (*enable_azalia_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* disable Azalia audio */
-+	void (*disable_azalia_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* enable DP audio */
-+	void (*enable_dp_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* disable DP audio */
-+	void (*disable_dp_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* setup Azalia HW block */
-+	void (*setup_azalia)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id,
-+		enum signal_type signal,
-+		const struct audio_crtc_info *crtc_info,
-+		const struct audio_pll_info *pll_info,
-+		const struct audio_info *audio_info);
-+
-+	/* unmute audio */
-+	void (*unmute_azalia_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* mute audio */
-+	void (*mute_azalia_audio)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id);
-+
-+	/* enable channel splitting mapping */
-+	void (*setup_channel_splitting_mapping)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id,
-+		enum signal_type signal,
-+		const struct audio_channel_associate_info *audio_mapping,
-+		bool enable);
-+
-+	/* get current channel spliting */
-+	bool (*get_channel_splitting_mapping)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id,
-+		struct audio_channel_associate_info *audio_mapping);
-+
-+	/* set the payload value for the unsolicited response */
-+	void (*set_unsolicited_response_payload)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum audio_payload payload);
-+
-+	/* initialize HW state */
-+	void (*hw_initialize)(
-+		const struct hw_ctx_audio *hw_ctx);
-+
-+	/* check_audio_bandwidth */
-+
-+	/* Assign GTC group and enable GTC value embedding */
-+	void (*enable_gtc_embedding_with_group)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		uint32_t groupNum,
-+		uint32_t audioLatency);
-+
-+	/* Disable GTC value embedding */
-+	void (*disable_gtc_embedding)(
-+		const struct hw_ctx_audio *hw_ctx);
-+
-+	/* Disable Azalia Clock Gating Feature */
-+	void (*disable_az_clock_gating)(
-+		const struct hw_ctx_audio *hw_ctx);
-+
-+	/* ~~~~  protected: ~~~~*/
-+
-+	/* calc_max_audio_packets_per_line */
-+	/* speakers_to_channels */
-+	/* is_audio_format_supported */
-+	/* get_audio_clock_info */
-+
-+	/* search pixel clock value for Azalia HDMI Audio */
-+	bool (*get_azalia_clock_info_hdmi)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		uint32_t crtc_pixel_clock_in_khz,
-+		uint32_t actual_pixel_clock_in_khz,
-+		struct azalia_clock_info *azalia_clock_info);
-+
-+	/* search pixel clock value for Azalia DP Audio */
-+	bool (*get_azalia_clock_info_dp)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		uint32_t requested_pixel_clock_in_khz,
-+		const struct audio_pll_info *pll_info,
-+		struct azalia_clock_info *azalia_clock_info);
-+
-+	void (*enable_afmt_clock)(
-+		const struct hw_ctx_audio *hw_ctx,
-+		enum engine_id engine_id,
-+		bool enable);
-+
-+	/* @@@@   private:  @@@@  */
-+
-+	/* check_audio_bandwidth_hdmi  */
-+	/* check_audio_bandwidth_dpsst */
-+	/* check_audio_bandwidth_dpmst */
-+
-+};
-+
-+
-+struct hw_ctx_audio {
-+	const struct hw_ctx_audio_funcs *funcs;
-+	struct dc_context *ctx;
-+
-+	/*audio_clock_infoTable[12];
-+	 *audio_clock_infoTable_36bpc[12];
-+	 *audio_clock_infoTable_48bpc[12];
-+	 *used by hw_ctx_audio.c file only. Will declare as static array
-+	 *azaliaclockinfoTable[12]  -- not used
-+	 *BusNumberMask;   BusNumberShift; DeviceNumberMask;
-+	 *not used by dce6 and after
-+	 */
-+};
-+
-+
-+
-+/* --- object construct, destruct --- */
-+
-+/*
-+ *called by derived audio object for specific ASIC. In case no derived object,
-+ *these two functions do not need exposed.
-+ */
-+bool dal_audio_construct_hw_ctx_audio(
-+	struct hw_ctx_audio *hw_ctx);
-+
-+void dal_audio_destruct_hw_ctx_audio(
-+	struct hw_ctx_audio *hw_ctx);
-+
-+/*
-+ *creator of audio HW context will be implemented by specific ASIC object only.
-+ *Top base or interface object does not have implementation of creator.
-+ */
-+
-+
-+/* --- functions called by audio hw context itself --- */
-+
-+/* MM register access */
-+/*read_register  - dal_read_reg */
-+/*write_register - dal_write_reg*/
-+
-+
-+/*check whether specified sample rates can fit into a given timing */
-+void dal_hw_ctx_audio_check_audio_bandwidth(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	enum signal_type signal,
-+	union audio_sample_rates *sample_rates);
-+
-+/*For HDMI, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates);
-+
-+/*For DPSST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpsst(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates);
-+
-+/*For DPMST, calculate if specified sample rates can fit into a given timing */
-+void dal_audio_hw_ctx_check_audio_bandwidth_dpmst(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates);
-+
-+/* calculate max number of Audio packets per line */
-+uint32_t dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_crtc_info *crtc_info);
-+
-+/* translate speakers to channels */
-+union audio_cea_channels dal_audio_hw_ctx_speakers_to_channels(
-+	const struct hw_ctx_audio *hw_ctx,
-+	struct audio_speaker_flags speaker_flags);
-+
-+/* check whether specified audio format supported */
-+bool dal_audio_hw_ctx_is_audio_format_supported(
-+	const struct hw_ctx_audio *hw_ctx,
-+	const struct audio_info *audio_info,
-+	enum audio_format_code audio_format_code,
-+	uint32_t *format_index);
-+
-+/* search pixel clock value for HDMI */
-+bool dal_audio_hw_ctx_get_audio_clock_info(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum dc_color_depth color_depth,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct audio_clock_info *audio_clock_info);
-+
-+
-+#endif  /* __DAL_HW_CTX_AUDIO_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
-new file mode 100644
-index 0000000..93e2371
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'utils' sub-component of DAL.
-+# It provides the general basic services required by other DAL
-+# subcomponents.
-+
-+BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o logger.o register_logger.o signal_types.o vector.o
-+
-+AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
-+
-+AMD_DAL_FILES += $(AMD_DAL_BASICS)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-new file mode 100644
-index 0000000..8c38206
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-@@ -0,0 +1,223 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#define DIVIDER 10000
-+
-+/* S2D13 value in [-3.00...0.9999] */
-+#define S2D13_MIN (-3 * DIVIDER)
-+#define S2D13_MAX (3 * DIVIDER)
-+
-+uint16_t fixed_point_to_int_frac(
-+	struct fixed31_32 arg,
-+	uint8_t integer_bits,
-+	uint8_t fractional_bits)
-+{
-+	int32_t numerator;
-+	int32_t divisor = 1 << fractional_bits;
-+
-+	uint16_t result;
-+
-+	uint16_t d = (uint16_t)dal_fixed31_32_floor(
-+		dal_fixed31_32_abs(
-+			arg));
-+
-+	if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-+		numerator = (uint16_t)dal_fixed31_32_floor(
-+			dal_fixed31_32_mul_int(
-+				arg,
-+				divisor));
-+	else {
-+		numerator = dal_fixed31_32_floor(
-+			dal_fixed31_32_sub(
-+				dal_fixed31_32_from_int(
-+					1LL << integer_bits),
-+				dal_fixed31_32_recip(
-+					dal_fixed31_32_from_int(
-+						divisor))));
-+	}
-+
-+	if (numerator >= 0)
-+		result = (uint16_t)numerator;
-+	else
-+		result = (uint16_t)(
-+		(1 << (integer_bits + fractional_bits + 1)) + numerator);
-+
-+	if ((result != 0) && dal_fixed31_32_lt(
-+		arg, dal_fixed31_32_zero))
-+		result |= 1 << (integer_bits + fractional_bits);
-+
-+	return result;
-+}
-+/**
-+* convert_float_matrix
-+* This converts a double into HW register spec defined format S2D13.
-+* @param :
-+* @return None
-+*/
-+void convert_float_matrix(
-+	uint16_t *matrix,
-+	struct fixed31_32 *flt,
-+	uint32_t buffer_size)
-+{
-+	const struct fixed31_32 min_2_13 =
-+		dal_fixed31_32_from_fraction(S2D13_MIN, DIVIDER);
-+	const struct fixed31_32 max_2_13 =
-+		dal_fixed31_32_from_fraction(S2D13_MAX, DIVIDER);
-+	uint32_t i;
-+
-+	for (i = 0; i < buffer_size; ++i) {
-+		uint32_t reg_value =
-+				fixed_point_to_int_frac(
-+					dal_fixed31_32_clamp(
-+						flt[i],
-+						min_2_13,
-+						max_2_13),
-+						2,
-+						13);
-+
-+		matrix[i] = (uint16_t)reg_value;
-+	}
-+}
-+
-+static void calculate_adjustments_common(
-+	const struct fixed31_32 *ideal_matrix,
-+	const struct dc_csc_adjustments *adjustments,
-+	struct fixed31_32 *matrix)
-+{
-+	const struct fixed31_32 sin_hue =
-+		dal_fixed31_32_sin(adjustments->hue);
-+	const struct fixed31_32 cos_hue =
-+		dal_fixed31_32_cos(adjustments->hue);
-+
-+	const struct fixed31_32 multiplier =
-+		dal_fixed31_32_mul(
-+			adjustments->contrast,
-+			adjustments->saturation);
-+
-+	matrix[0] = dal_fixed31_32_mul(
-+		ideal_matrix[0],
-+		adjustments->contrast);
-+
-+	matrix[1] = dal_fixed31_32_mul(
-+		ideal_matrix[1],
-+		adjustments->contrast);
-+
-+	matrix[2] = dal_fixed31_32_mul(
-+		ideal_matrix[2],
-+		adjustments->contrast);
-+
-+	matrix[4] = dal_fixed31_32_mul(
-+		multiplier,
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(
-+				ideal_matrix[8],
-+				sin_hue),
-+			dal_fixed31_32_mul(
-+				ideal_matrix[4],
-+				cos_hue)));
-+
-+	matrix[5] = dal_fixed31_32_mul(
-+		multiplier,
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(
-+				ideal_matrix[9],
-+				sin_hue),
-+			dal_fixed31_32_mul(
-+				ideal_matrix[5],
-+				cos_hue)));
-+
-+	matrix[6] = dal_fixed31_32_mul(
-+		multiplier,
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(
-+				ideal_matrix[10],
-+				sin_hue),
-+			dal_fixed31_32_mul(
-+				ideal_matrix[6],
-+				cos_hue)));
-+
-+	matrix[7] = ideal_matrix[7];
-+
-+	matrix[8] = dal_fixed31_32_mul(
-+		multiplier,
-+		dal_fixed31_32_sub(
-+			dal_fixed31_32_mul(
-+				ideal_matrix[8],
-+				cos_hue),
-+			dal_fixed31_32_mul(
-+				ideal_matrix[4],
-+				sin_hue)));
-+
-+	matrix[9] = dal_fixed31_32_mul(
-+		multiplier,
-+		dal_fixed31_32_sub(
-+			dal_fixed31_32_mul(
-+				ideal_matrix[9],
-+				cos_hue),
-+			dal_fixed31_32_mul(
-+				ideal_matrix[5],
-+				sin_hue)));
-+
-+	matrix[10] = dal_fixed31_32_mul(
-+		multiplier,
-+		dal_fixed31_32_sub(
-+			dal_fixed31_32_mul(
-+				ideal_matrix[10],
-+				cos_hue),
-+			dal_fixed31_32_mul(
-+				ideal_matrix[6],
-+				sin_hue)));
-+
-+	matrix[11] = ideal_matrix[11];
-+}
-+
-+void calculate_adjustments(
-+	const struct fixed31_32 *ideal_matrix,
-+	const struct dc_csc_adjustments *adjustments,
-+	struct fixed31_32 *matrix)
-+{
-+	calculate_adjustments_common(ideal_matrix, adjustments, matrix);
-+
-+	matrix[3] = dal_fixed31_32_add(
-+		ideal_matrix[3],
-+		dal_fixed31_32_mul(
-+			adjustments->brightness,
-+			dal_fixed31_32_from_fraction(86, 100)));
-+}
-+
-+void calculate_adjustments_y_only(
-+	const struct fixed31_32 *ideal_matrix,
-+	const struct dc_csc_adjustments *adjustments,
-+	struct fixed31_32 *matrix)
-+{
-+	calculate_adjustments_common(ideal_matrix, adjustments, matrix);
-+
-+	matrix[3] = dal_fixed31_32_add(
-+		ideal_matrix[3],
-+		adjustments->brightness);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.h b/drivers/gpu/drm/amd/dal/dc/basics/conversion.h
-new file mode 100644
-index 0000000..24ff473
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CONVERSION_H__
-+#define __DAL_CONVERSION_H__
-+
-+uint16_t fixed_point_to_int_frac(
-+	struct fixed31_32 arg,
-+	uint8_t integer_bits,
-+	uint8_t fractional_bits);
-+
-+void convert_float_matrix(
-+	uint16_t *matrix,
-+	struct fixed31_32 *flt,
-+	uint32_t buffer_size);
-+
-+void calculate_adjustments(
-+	const struct fixed31_32 *ideal_matrix,
-+	const struct dc_csc_adjustments *adjustments,
-+	struct fixed31_32 *matrix);
-+
-+void calculate_adjustments_y_only(
-+	const struct fixed31_32 *ideal_matrix,
-+	const struct dc_csc_adjustments *adjustments,
-+	struct fixed31_32 *matrix);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-new file mode 100644
-index 0000000..6ce75b3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-@@ -0,0 +1,692 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/fixed31_32.h"
-+
-+static inline uint64_t abs_i64(
-+	int64_t arg)
-+{
-+	if (arg > 0)
-+		return (uint64_t)arg;
-+	else
-+		return (uint64_t)(-arg);
-+}
-+
-+/*
-+ * @brief
-+ * result = dividend / divisor
-+ * *remainder = dividend % divisor
-+ */
-+static inline uint64_t complete_integer_division_u64(
-+	uint64_t dividend,
-+	uint64_t divisor,
-+	uint64_t *remainder)
-+{
-+	uint64_t result;
-+
-+	ASSERT(divisor);
-+
-+	result = div64_u64_rem(dividend, divisor, remainder);
-+
-+	return result;
-+}
-+
-+#define BITS_PER_FRACTIONAL_PART \
-+	32
-+
-+#define FRACTIONAL_PART_MASK \
-+	((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
-+
-+#define GET_INTEGER_PART(x) \
-+	((x) >> BITS_PER_FRACTIONAL_PART)
-+
-+#define GET_FRACTIONAL_PART(x) \
-+	(FRACTIONAL_PART_MASK & (x))
-+
-+struct fixed31_32 dal_fixed31_32_from_fraction(
-+	int64_t numerator,
-+	int64_t denominator)
-+{
-+	struct fixed31_32 res;
-+
-+	bool arg1_negative = numerator < 0;
-+	bool arg2_negative = denominator < 0;
-+
-+	uint64_t arg1_value = arg1_negative ? -numerator : numerator;
-+	uint64_t arg2_value = arg2_negative ? -denominator : denominator;
-+
-+	uint64_t remainder;
-+
-+	/* determine integer part */
-+
-+	uint64_t res_value = complete_integer_division_u64(
-+		arg1_value, arg2_value, &remainder);
-+
-+	ASSERT(res_value <= LONG_MAX);
-+
-+	/* determine fractional part */
-+	{
-+		uint32_t i = BITS_PER_FRACTIONAL_PART;
-+
-+		do {
-+			remainder <<= 1;
-+
-+			res_value <<= 1;
-+
-+			if (remainder >= arg2_value) {
-+				res_value |= 1;
-+				remainder -= arg2_value;
-+			}
-+		} while (--i != 0);
-+	}
-+
-+	/* round up LSB */
-+	{
-+		uint64_t summand = (remainder << 1) >= arg2_value;
-+
-+		ASSERT(res_value <= LLONG_MAX - summand);
-+
-+		res_value += summand;
-+	}
-+
-+	res.value = (int64_t)res_value;
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_from_int(
-+	int64_t arg)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
-+
-+	res.value = arg << BITS_PER_FRACTIONAL_PART;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_neg(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 res;
-+
-+	res.value = -arg.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_abs(
-+	struct fixed31_32 arg)
-+{
-+	if (arg.value < 0)
-+		return dal_fixed31_32_neg(arg);
-+	else
-+		return arg;
-+}
-+
-+bool dal_fixed31_32_lt(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	return arg1.value < arg2.value;
-+}
-+
-+bool dal_fixed31_32_le(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	return arg1.value <= arg2.value;
-+}
-+
-+bool dal_fixed31_32_eq(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	return arg1.value == arg2.value;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_min(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	if (arg1.value <= arg2.value)
-+		return arg1;
-+	else
-+		return arg2;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_max(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	if (arg1.value <= arg2.value)
-+		return arg2;
-+	else
-+		return arg1;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_clamp(
-+	struct fixed31_32 arg,
-+	struct fixed31_32 min_value,
-+	struct fixed31_32 max_value)
-+{
-+	if (dal_fixed31_32_le(arg, min_value))
-+		return min_value;
-+	else if (dal_fixed31_32_le(max_value, arg))
-+		return max_value;
-+	else
-+		return arg;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_shl(
-+	struct fixed31_32 arg,
-+	uint8_t shift)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-+		((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
-+
-+	res.value = arg.value << shift;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_shr(
-+	struct fixed31_32 arg,
-+	uint8_t shift)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(shift < 64);
-+
-+	res.value = arg.value >> shift;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_add(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
-+		((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
-+
-+	res.value = arg1.value + arg2.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sub_int(
-+	struct fixed31_32 arg1,
-+	int32_t arg2)
-+{
-+	return dal_fixed31_32_sub(
-+		arg1,
-+		dal_fixed31_32_from_int(arg2));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sub(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
-+		((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
-+
-+	res.value = arg1.value - arg2.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_mul_int(
-+	struct fixed31_32 arg1,
-+	int32_t arg2)
-+{
-+	return dal_fixed31_32_mul(
-+		arg1,
-+		dal_fixed31_32_from_int(arg2));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_mul(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	struct fixed31_32 res;
-+
-+	bool arg1_negative = arg1.value < 0;
-+	bool arg2_negative = arg2.value < 0;
-+
-+	uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
-+	uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
-+
-+	uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
-+	uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
-+
-+	uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
-+	uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
-+
-+	uint64_t tmp;
-+
-+	res.value = arg1_int * arg2_int;
-+
-+	ASSERT(res.value <= LONG_MAX);
-+
-+	res.value <<= BITS_PER_FRACTIONAL_PART;
-+
-+	tmp = arg1_int * arg2_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg2_int * arg1_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg1_fra * arg2_fra;
-+
-+	tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
-+		(tmp >= (uint64_t)dal_fixed31_32_half.value);
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sqr(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 res;
-+
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	uint64_t arg_int = GET_INTEGER_PART(arg_value);
-+
-+	uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
-+
-+	uint64_t tmp;
-+
-+	res.value = arg_int * arg_int;
-+
-+	ASSERT(res.value <= LONG_MAX);
-+
-+	res.value <<= BITS_PER_FRACTIONAL_PART;
-+
-+	tmp = arg_int * arg_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg_fra * arg_fra;
-+
-+	tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
-+		(tmp >= (uint64_t)dal_fixed31_32_half.value);
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_div_int(
-+	struct fixed31_32 arg1,
-+	int64_t arg2)
-+{
-+	return dal_fixed31_32_from_fraction(
-+		arg1.value,
-+		dal_fixed31_32_from_int(arg2).value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_div(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	return dal_fixed31_32_from_fraction(
-+		arg1.value,
-+		arg2.value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_recip(
-+	struct fixed31_32 arg)
-+{
-+	/*
-+	 * @note
-+	 * Good idea to use Newton's method
-+	 */
-+
-+	ASSERT(arg.value);
-+
-+	return dal_fixed31_32_from_fraction(
-+		dal_fixed31_32_one.value,
-+		arg.value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sinc(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 square;
-+
-+	struct fixed31_32 res = dal_fixed31_32_one;
-+
-+	int32_t n = 27;
-+
-+	struct fixed31_32 arg_norm = arg;
-+
-+	if (dal_fixed31_32_le(
-+		dal_fixed31_32_two_pi,
-+		dal_fixed31_32_abs(arg))) {
-+		arg_norm = dal_fixed31_32_sub(
-+			arg_norm,
-+			dal_fixed31_32_mul_int(
-+				dal_fixed31_32_two_pi,
-+				(int32_t)div64_s64(
-+					arg_norm.value,
-+					dal_fixed31_32_two_pi.value)));
-+	}
-+
-+	square = dal_fixed31_32_sqr(arg_norm);
-+
-+	do {
-+		res = dal_fixed31_32_sub(
-+			dal_fixed31_32_one,
-+			dal_fixed31_32_div_int(
-+				dal_fixed31_32_mul(
-+					square,
-+					res),
-+				n * (n - 1)));
-+
-+		n -= 2;
-+	} while (n > 2);
-+
-+	if (arg.value != arg_norm.value)
-+		res = dal_fixed31_32_div(
-+			dal_fixed31_32_mul(res, arg_norm),
-+			arg);
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sin(
-+	struct fixed31_32 arg)
-+{
-+	return dal_fixed31_32_mul(
-+		arg,
-+		dal_fixed31_32_sinc(arg));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_cos(
-+	struct fixed31_32 arg)
-+{
-+	/* TODO implement argument normalization */
-+
-+	const struct fixed31_32 square = dal_fixed31_32_sqr(arg);
-+
-+	struct fixed31_32 res = dal_fixed31_32_one;
-+
-+	int32_t n = 26;
-+
-+	do {
-+		res = dal_fixed31_32_sub(
-+			dal_fixed31_32_one,
-+			dal_fixed31_32_div_int(
-+				dal_fixed31_32_mul(
-+					square,
-+					res),
-+				n * (n - 1)));
-+
-+		n -= 2;
-+	} while (n != 0);
-+
-+	return res;
-+}
-+
-+/*
-+ * @brief
-+ * result = exp(arg),
-+ * where abs(arg) < 1
-+ *
-+ * Calculated as Taylor series.
-+ */
-+static struct fixed31_32 fixed31_32_exp_from_taylor_series(
-+	struct fixed31_32 arg)
-+{
-+	uint32_t n = 9;
-+
-+	struct fixed31_32 res = dal_fixed31_32_from_fraction(
-+		n + 2,
-+		n + 1);
-+	/* TODO find correct res */
-+
-+	ASSERT(dal_fixed31_32_lt(arg, dal_fixed31_32_one));
-+
-+	do
-+		res = dal_fixed31_32_add(
-+			dal_fixed31_32_one,
-+			dal_fixed31_32_div_int(
-+				dal_fixed31_32_mul(
-+					arg,
-+					res),
-+				n));
-+	while (--n != 1);
-+
-+	return dal_fixed31_32_add(
-+		dal_fixed31_32_one,
-+		dal_fixed31_32_mul(
-+			arg,
-+			res));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_exp(
-+	struct fixed31_32 arg)
-+{
-+	/*
-+	 * @brief
-+	 * Main equation is:
-+	 * exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r),
-+	 * where m = round(x / ln(2)), r = x - m * ln(2)
-+	 */
-+
-+	if (dal_fixed31_32_le(
-+		dal_fixed31_32_ln2_div_2,
-+		dal_fixed31_32_abs(arg))) {
-+		int32_t m = dal_fixed31_32_round(
-+			dal_fixed31_32_div(
-+				arg,
-+				dal_fixed31_32_ln2));
-+
-+		struct fixed31_32 r = dal_fixed31_32_sub(
-+			arg,
-+			dal_fixed31_32_mul_int(
-+				dal_fixed31_32_ln2,
-+				m));
-+
-+		ASSERT(m != 0);
-+
-+		ASSERT(dal_fixed31_32_lt(
-+			dal_fixed31_32_abs(r),
-+			dal_fixed31_32_one));
-+
-+		if (m > 0)
-+			return dal_fixed31_32_shl(
-+				fixed31_32_exp_from_taylor_series(r),
-+				(uint8_t)m);
-+		else
-+			return dal_fixed31_32_div_int(
-+				fixed31_32_exp_from_taylor_series(r),
-+				1LL << -m);
-+	} else if (arg.value != 0)
-+		return fixed31_32_exp_from_taylor_series(arg);
-+	else
-+		return dal_fixed31_32_one;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_log(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 res = dal_fixed31_32_neg(dal_fixed31_32_one);
-+	/* TODO improve 1st estimation */
-+
-+	struct fixed31_32 error;
-+
-+	ASSERT(arg.value > 0);
-+	/* TODO if arg is negative, return NaN */
-+	/* TODO if arg is zero, return -INF */
-+
-+	do {
-+		struct fixed31_32 res1 = dal_fixed31_32_add(
-+			dal_fixed31_32_sub(
-+				res,
-+				dal_fixed31_32_one),
-+			dal_fixed31_32_div(
-+				arg,
-+				dal_fixed31_32_exp(res)));
-+
-+		error = dal_fixed31_32_sub(
-+			res,
-+			res1);
-+
-+		res = res1;
-+		/* TODO determine max_allowed_error based on quality of exp() */
-+	} while (abs_i64(error.value) > 100ULL);
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_pow(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	return dal_fixed31_32_exp(
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_log(arg1),
-+			arg2));
-+}
-+
-+int32_t dal_fixed31_32_floor(
-+	struct fixed31_32 arg)
-+{
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	if (arg.value >= 0)
-+		return (int32_t)GET_INTEGER_PART(arg_value);
-+	else
-+		return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+int32_t dal_fixed31_32_round(
-+	struct fixed31_32 arg)
-+{
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	const int64_t summand = dal_fixed31_32_half.value;
-+
-+	ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
-+
-+	arg_value += summand;
-+
-+	if (arg.value >= 0)
-+		return (int32_t)GET_INTEGER_PART(arg_value);
-+	else
-+		return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+int32_t dal_fixed31_32_ceil(
-+	struct fixed31_32 arg)
-+{
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	const int64_t summand = dal_fixed31_32_one.value -
-+		dal_fixed31_32_epsilon.value;
-+
-+	ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
-+
-+	arg_value += summand;
-+
-+	if (arg.value >= 0)
-+		return (int32_t)GET_INTEGER_PART(arg_value);
-+	else
-+		return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+/* this function is a generic helper to translate fixed point value to
-+ * specified integer format that will consist of integer_bits integer part and
-+ * fractional_bits fractional part. For example it is used in
-+ * dal_fixed31_32_u2d19 to receive 2 bits integer part and 19 bits fractional
-+ * part in 32 bits. It is used in hw programming (scaler)
-+ */
-+
-+static inline uint32_t ux_dy(
-+	int64_t value,
-+	uint32_t integer_bits,
-+	uint32_t fractional_bits)
-+{
-+	/* 1. create mask of integer part */
-+	uint32_t result =
-+		(1 << integer_bits) - 1;
-+	/* 2. mask out fractional part */
-+	uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
-+	/* 3. shrink fixed point integer part to be of integer_bits width*/
-+	result &= GET_INTEGER_PART(value);
-+	/* 4. make space for fractional part to be filled in after integer */
-+	result <<= fractional_bits;
-+	/* 5. shrink fixed point fractional part to of fractional_bits width*/
-+	fractional_part >>= BITS_PER_FRACTIONAL_PART - fractional_bits;
-+	/* 6. merge the result */
-+	return result | fractional_part;
-+}
-+
-+uint32_t dal_fixed31_32_u2d19(
-+	struct fixed31_32 arg)
-+{
-+	return ux_dy(arg.value, 2, 19);
-+}
-+
-+uint32_t dal_fixed31_32_u0d19(
-+	struct fixed31_32 arg)
-+{
-+	return ux_dy(arg.value, 0, 19);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-new file mode 100644
-index 0000000..1140132
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-@@ -0,0 +1,223 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/fixed32_32.h"
-+
-+static uint64_t u64_div(uint64_t n, uint64_t d)
-+{
-+	uint32_t i = 0;
-+	uint64_t r;
-+	uint64_t q = div64_u64_rem(n, d, &r);
-+
-+	for (i = 0; i < 32; ++i) {
-+		uint64_t sbit = q & (1ULL<<63);
-+
-+		r <<= 1;
-+		r |= sbit ? 1 : 0;
-+		q <<= 1;
-+		if (r >= d) {
-+			r -= d;
-+			q |= 1;
-+		}
-+	}
-+
-+	if (2*r >= d)
-+		q += 1;
-+	return q;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = u64_div((uint64_t)n << 32, (uint64_t)d << 32);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_from_int(uint32_t value)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = (uint64_t)value<<32;
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx = {lhs.value + rhs.value};
-+
-+	ASSERT(fx.value >= rhs.value);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx = {lhs.value + ((uint64_t)rhs << 32)};
-+
-+	ASSERT(fx.value >= (uint64_t)rhs << 32);
-+	return fx;
-+
-+}
-+struct fixed32_32 dal_fixed32_32_sub(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	ASSERT(lhs.value >= rhs.value);
-+	fx.value = lhs.value - rhs.value;
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_sub_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	ASSERT(lhs.value >= ((uint64_t)rhs<<32));
-+	fx.value = lhs.value - ((uint64_t)rhs<<32);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_mul(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx;
-+	uint64_t lhs_int = lhs.value>>32;
-+	uint64_t lhs_frac = (uint32_t)lhs.value;
-+	uint64_t rhs_int = rhs.value>>32;
-+	uint64_t rhs_frac = (uint32_t)rhs.value;
-+	uint64_t ahbh = lhs_int * rhs_int;
-+	uint64_t ahbl = lhs_int * rhs_frac;
-+	uint64_t albh = lhs_frac * rhs_int;
-+	uint64_t albl = lhs_frac * rhs_frac;
-+
-+	ASSERT((ahbh>>32) == 0);
-+
-+	fx.value = (ahbh<<32) + ahbl + albh + (albl>>32);
-+	return fx;
-+
-+}
-+
-+struct fixed32_32 dal_fixed32_32_mul_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx;
-+	uint64_t lhsi = (lhs.value>>32) * (uint64_t)rhs;
-+	uint64_t lhsf;
-+
-+	ASSERT((lhsi>>32) == 0);
-+	lhsf = ((uint32_t)lhs.value) * (uint64_t)rhs;
-+	ASSERT((lhsi<<32) + lhsf >= lhsf);
-+	fx.value = (lhsi<<32) + lhsf;
-+	return fx;
-+}
-+
-+
-+
-+struct fixed32_32 dal_fixed32_32_div(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = u64_div(lhs.value, rhs.value);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_div_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = u64_div(lhs.value, (uint64_t)rhs << 32);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_min(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	return (lhs.value < rhs.value) ? lhs : rhs;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_max(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	return (lhs.value > rhs.value) ? lhs : rhs;
-+}
-+
-+bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value > rhs.value;
-+}
-+bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	return lhs.value > ((uint64_t)rhs<<32);
-+}
-+
-+bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value < rhs.value;
-+}
-+
-+bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value <= rhs.value;
-+}
-+
-+bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	return lhs.value < ((uint64_t)rhs<<32);
-+}
-+
-+bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	return lhs.value <= ((uint64_t)rhs<<32);
-+}
-+
-+uint32_t dal_fixed32_32_ceil(struct fixed32_32 v)
-+{
-+	ASSERT((uint32_t)v.value ? (v.value >> 32) + 1 >= 1 : true);
-+	return (v.value>>32) + ((uint32_t)v.value ? 1 : 0);
-+}
-+
-+uint32_t dal_fixed32_32_floor(struct fixed32_32 v)
-+{
-+	return v.value>>32;
-+}
-+
-+uint32_t dal_fixed32_32_round(struct fixed32_32 v)
-+{
-+	ASSERT(v.value + (1ULL<<31) >= (1ULL<<31));
-+	return (v.value + (1ULL<<31))>>32;
-+}
-+
-+bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value == rhs.value;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-new file mode 100644
-index 0000000..8276f9d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-@@ -0,0 +1,135 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/grph_object_id.h"
-+
-+bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
-+{
-+	bool rc = true;
-+
-+	switch (id.type) {
-+	case OBJECT_TYPE_UNKNOWN:
-+		rc = false;
-+		break;
-+	case OBJECT_TYPE_GPU:
-+	case OBJECT_TYPE_ENGINE:
-+		/* do NOT check for id.id == 0 */
-+		if (id.enum_id == ENUM_ID_UNKNOWN)
-+			rc = false;
-+		break;
-+	default:
-+		if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
-+			rc = false;
-+		break;
-+	}
-+
-+	return rc;
-+}
-+
-+bool dal_graphics_object_id_is_equal(
-+	struct graphics_object_id id1,
-+	struct graphics_object_id id2)
-+{
-+	if (false == dal_graphics_object_id_is_valid(id1)) {
-+		dal_output_to_console(
-+		"%s: Warning: comparing invalid object 'id1'!\n", __func__);
-+		return false;
-+	}
-+
-+	if (false == dal_graphics_object_id_is_valid(id2)) {
-+		dal_output_to_console(
-+		"%s: Warning: comparing invalid object 'id2'!\n", __func__);
-+		return false;
-+	}
-+
-+	if (id1.id == id2.id && id1.enum_id == id2.enum_id
-+		&& id1.type == id2.type)
-+		return true;
-+
-+	return false;
-+}
-+
-+/* Based on internal data members memory layout */
-+uint32_t dal_graphics_object_id_to_uint(struct graphics_object_id id)
-+{
-+	uint32_t object_id = 0;
-+
-+	object_id = id.id + (id.enum_id << 0x8) + (id.type << 0xc);
-+	return object_id;
-+}
-+
-+/*
-+ * ******* get specific ID - internal safe cast into specific type *******
-+ */
-+
-+enum controller_id dal_graphics_object_id_get_controller_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_CONTROLLER)
-+		return id.id;
-+	return CONTROLLER_ID_UNDEFINED;
-+}
-+
-+enum clock_source_id dal_graphics_object_id_get_clock_source_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
-+		return id.id;
-+	return CLOCK_SOURCE_ID_UNDEFINED;
-+}
-+
-+enum encoder_id dal_graphics_object_id_get_encoder_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_ENCODER)
-+		return id.id;
-+	return ENCODER_ID_UNKNOWN;
-+}
-+
-+enum connector_id dal_graphics_object_id_get_connector_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_CONNECTOR)
-+		return id.id;
-+	return CONNECTOR_ID_UNKNOWN;
-+}
-+
-+enum audio_id dal_graphics_object_id_get_audio_id(struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_AUDIO)
-+		return id.id;
-+	return AUDIO_ID_UNKNOWN;
-+}
-+
-+enum engine_id dal_graphics_object_id_get_engine_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_ENGINE)
-+		return id.id;
-+	return ENGINE_ID_UNKNOWN;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-new file mode 100644
-index 0000000..50db743
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -0,0 +1,947 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include <stdarg.h>
-+#include "dal_services.h"
-+#include "include/dal_types.h"
-+#include "include/logger_interface.h"
-+#include "logger.h"
-+
-+/* TODO: for now - empty, use DRM defines from dal services.
-+		Need to define appropriate levels of prints, and implement
-+		this component
-+void dal_log(const char *format, ...)
-+{
-+}
-+*/
-+
-+/* ----------- Logging Major/Minor names ------------ */
-+
-+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
-+
-+static const struct log_minor_info component_minor_info_tbl[] = {
-+	{LOG_MINOR_COMPONENT_LINK_SERVICE, "LS"},
-+	{LOG_MINOR_COMPONENT_DAL_INTERFACE, "DalIf"},
-+	{LOG_MINOR_COMPONENT_HWSS, "HWSS"},
-+	{LOG_MINOR_COMPONENT_ADAPTER_SERVICE, "AS"},
-+	{LOG_MINOR_COMPONENT_DISPLAY_SERVICE, "DS"},
-+	{LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER, "TM"},
-+	{LOG_MINOR_COMPONENT_ENCODER, "Encoder"},
-+	{LOG_MINOR_COMPONENT_I2C_AUX, "I2cAux"},
-+	{LOG_MINOR_COMPONENT_AUDIO, "Audio"},
-+	{LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE, "Dcs"},
-+	{LOG_MINOR_COMPONENT_DMCU, "Dmcu"},
-+	{LOG_MINOR_COMPONENT_GPU, "GPU"},
-+	{LOG_MINOR_COMPONENT_CONTROLLER, "Cntrlr"},
-+	{LOG_MINOR_COMPONENT_ISR, "ISR"},
-+	{LOG_MINOR_COMPONENT_BIOS, "BIOS"},
-+	{LOG_MINOR_COMPONENT_DC, "DC"},
-+	{LOG_MINOR_COMPONENT_IRQ_SERVICE, "IRQ SERVICE"},
-+
-+};
-+
-+static const struct log_minor_info hw_trace_minor_info_tbl[] = {
-+	{LOG_MINOR_HW_TRACE_MST, "Mst" },
-+	{LOG_MINOR_HW_TRACE_TRAVIS, "Travis" },
-+	{LOG_MINOR_HW_TRACE_HOTPLUG, "Hotplug" },
-+	{LOG_MINOR_HW_TRACE_LINK_TRAINING, "LinkTraining" },
-+	{LOG_MINOR_HW_TRACE_SET_MODE, "SetMode" },
-+	{LOG_MINOR_HW_TRACE_RESUME_S3, "ResumeS3" },
-+	{LOG_MINOR_HW_TRACE_RESUME_S4, "ResumeS4" },
-+	{LOG_MINOR_HW_TRACE_BOOTUP, "BootUp" },
-+	{LOG_MINOR_HW_TRACE_AUDIO, "Audio"},
-+	{LOG_MINOR_HW_TRACE_HPD_IRQ, "HpdIrq" },
-+	{LOG_MINOR_HW_TRACE_INTERRUPT, "Interrupt" },
-+	{LOG_MINOR_HW_TRACE_MPO, "Planes" },
-+};
-+
-+static const struct log_minor_info mst_minor_info_tbl[] = {
-+	{LOG_MINOR_MST_IRQ_HPD_RX, "IrqHpdRx"},
-+	{LOG_MINOR_MST_IRQ_TIMER, "IrqTimer"},
-+	{LOG_MINOR_MST_NATIVE_AUX, "NativeAux"},
-+	{LOG_MINOR_MST_SIDEBAND_MSG, "SB"},
-+	{LOG_MINOR_MST_MSG_TRANSACTION, "MT"},
-+	{LOG_MINOR_MST_SIDEBAND_MSG_PARSED, "SB Parsed"},
-+	{LOG_MINOR_MST_MSG_TRANSACTION_PARSED, "MT Parsed"},
-+	{LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS, "AuxMsgDpcdAccess"},
-+	{LOG_MINOR_MST_PROGRAMMING, "Programming"},
-+	{LOG_MINOR_MST_TOPOLOGY_DISCOVERY, "TopologyDiscovery"},
-+	{LOG_MINOR_MST_CONVERTER_CAPS, "ConverterCaps"},
-+};
-+
-+static const struct log_minor_info dcs_minor_info_tbl[] = {
-+	{LOG_MINOR_DCS_EDID_EMULATOR, "EdidEmul"},
-+	{LOG_MINOR_DCS_DONGLE_DETECTION, "DongleDetect"},
-+};
-+
-+static const struct log_minor_info dcp_minor_info_tbl[] = {
-+	{ LOG_MINOR_DCP_GAMMA_GRPH, "GammaGrph"},
-+	{ LOG_MINOR_DCP_GAMMA_OVL, "GammaOvl"},
-+	{ LOG_MINOR_DCP_CSC_GRPH, "CscGrph"},
-+	{ LOG_MINOR_DCP_CSC_OVL, "CscOvl"},
-+	{ LOG_MINOR_DCP_SCALER, "Scaler"},
-+	{ LOG_MINOR_DCP_SCALER_TABLES, "ScalerTables"},
-+};
-+
-+static const struct log_minor_info bios_minor_info_tbl[] = {
-+	{LOG_MINOR_BIOS_CMD_TABLE, "CmdTbl"},
-+};
-+
-+static const struct log_minor_info reg_minor_info_tbl[] = {
-+	{LOG_MINOR_REGISTER_INDEX, "Index"},
-+};
-+
-+static const struct log_minor_info info_packet_minor_info_tbl[] = {
-+	{LOG_MINOR_INFO_PACKETS_HDMI, "Hdmi"},
-+};
-+
-+
-+static const struct log_minor_info dsat_minor_info_tbl[] = {
-+	{LOG_MINOR_DSAT_LOGGER, "Logger"},
-+	{LOG_MINOR_DSAT_EDID_OVERRIDE, "EDID_Override"},
-+};
-+
-+static const struct log_minor_info ec_minor_info_tbl[] = {
-+	{LOG_MINOR_EC_PPLIB_NOTIFY, "PPLib_Notify" }, /* PPLib notifies DAL */
-+	{LOG_MINOR_EC_PPLIB_QUERY, "PPLib_Query" } /* DAL requested info from
-+							PPLib */
-+};
-+
-+static const struct log_minor_info bwm_minor_info_tbl[] = {
-+	{LOG_MINOR_BWM_MODE_VALIDATION, "ModeValidation"},
-+	{LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS, "Req_Bandw_Calcs"}
-+};
-+
-+static const struct log_minor_info mode_enum_minor_info_tbl[] = {
-+	{LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES, "BestviewCandidates"},
-+	{LOG_MINOR_MODE_ENUM_VIEW_SOLUTION, "ViewSolution"},
-+	{LOG_MINOR_MODE_ENUM_TS_LIST_BUILD, "TsListBuild"},
-+	{LOG_MINOR_MODE_ENUM_TS_LIST, "TsList"},
-+	{LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST, "MasterViewList"},
-+	{LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE, "MasterViewListUpdate"},
-+};
-+
-+static const struct log_minor_info i2caux_minor_info_tbl[] = {
-+	{LOG_MINOR_I2C_AUX_LOG, "Log"},
-+	{LOG_MINOR_I2C_AUX_AUX_TIMESTAMP, "Timestamp"},
-+	{LOG_MINOR_I2C_AUX_CFG, "Config"}
-+};
-+
-+static const struct log_minor_info line_buffer_minor_info_tbl[] = {
-+	{LOG_MINOR_LINE_BUFFER_POWERGATING, "PowerGating"}
-+};
-+
-+static const struct log_minor_info hwss_minor_info_tbl[] = {
-+	{LOG_MINOR_HWSS_TAPS_VALIDATION, "HWSS Taps"}
-+};
-+
-+static const struct log_minor_info optimization_minor_info_tbl[] = {
-+	{LOG_MINOR_OPTMZ_GENERAL, "General Optimizations"},
-+	{LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
-+		"Skip Vcc Off During Set Mode"}
-+};
-+
-+static const struct log_minor_info perf_measure_minor_info_tbl[] = {
-+	{LOG_MINOR_PERF_MEASURE_GENERAL, "General Performance Measurement"},
-+	{LOG_MINOR_PERF_MEASURE_HEAP_MEMORY, "Heap Memory Management"}
-+};
-+
-+static const struct log_minor_info sync_minor_info_tbl[] = {
-+	{LOG_MINOR_SYNC_HW_CLOCK_ADJUST, "Pixel Rate Tune-up"},
-+	{LOG_MINOR_SYNC_TIMING, "Timing"}
-+};
-+
-+static const struct log_minor_info backlight_minor_info_tbl[] = {
-+	{LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS, "Caps"},
-+	{LOG_MINOR_BACKLIGHT_DMCU_DELTALUT, "DMCU Delta LUT"},
-+	{LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT, "Build DMCU Delta LUT"},
-+	{LOG_MINOR_BACKLIGHT_INTERFACE, "Interface"},
-+	{LOG_MINOR_BACKLIGHT_LID, "Lid Status"}
-+};
-+
-+
-+static const struct log_minor_info override_feature_minor_info_tbl[] = {
-+	{LOG_MINOR_FEATURE_OVERRIDE, "overriden feature"},
-+};
-+
-+static const struct log_minor_info detection_minor_info_tbl[] = {
-+	{LOG_MINOR_DETECTION_EDID_PARSER, "EDID Parser"},
-+	{LOG_MINOR_DETECTION_DP_CAPS, "DP caps"},
-+};
-+
-+static const struct log_minor_info tm_minor_info_tbl[] = {
-+	{LOG_MINOR_TM_INFO, "INFO"},
-+	{LOG_MINOR_TM_IFACE_TRACE, "IFACE_TRACE"},
-+	{LOG_MINOR_TM_RESOURCES, "RESOURCES"},
-+	{LOG_MINOR_TM_ENCODER_CTL, "ENCODER_CTL"},
-+	{LOG_MINOR_TM_ENG_ASN, "ENG_ASN"},
-+	{LOG_MINOR_TM_CONTROLLER_ASN, "CONTROLLER_ASN"},
-+	{LOG_MINOR_TM_PWR_GATING, "PWR_GATING"},
-+	{LOG_MINOR_TM_BUILD_DSP_PATH, "BUILD_PATH"},
-+	{LOG_MINOR_TM_DISPLAY_DETECT, "DISPLAY_DETECT"},
-+	{LOG_MINOR_TM_LINK_SRV,	"LINK_SRV"},
-+	{LOG_MINOR_TM_NOT_IMPLEMENTED, "NOT_IMPL"},
-+	{LOG_MINOR_TM_COFUNC_PATH, "COFUNC_PATH"}
-+};
-+
-+static const struct log_minor_info ds_minor_info_tbl[] = {
-+	{LOG_MINOR_DS_MODE_SETTING, "Mode_Setting"},
-+};
-+
-+
-+struct log_major_mask_info {
-+	struct log_major_info major_info;
-+	uint32_t default_mask;
-+	const struct log_minor_info *minor_tbl;
-+	uint32_t tbl_element_cnt;
-+};
-+
-+/* A mask for each Major.
-+ * Use a mask or zero. */
-+#define LG_ERR_MSK 0xffffffff
-+#define LG_WRN_MSK 0xffffffff
-+#define LG_TM_MSK (1 << LOG_MINOR_TM_INFO)
-+#define LG_FO_MSK (1 << LOG_MINOR_FEATURE_OVERRIDE)
-+#define LG_EC_MSK ((1 << LOG_MINOR_EC_PPLIB_NOTIFY) | \
-+			(1 << LOG_MINOR_EC_PPLIB_QUERY))
-+#define LG_DSAT_MSK (1 << LOG_MINOR_DSAT_EDID_OVERRIDE)
-+#define LG_DT_MSK (1 << LOG_MINOR_DETECTION_EDID_PARSER)
-+
-+/* IFT - InterFaceTrace */
-+#define LG_IFT_MSK (1 << LOG_MINOR_COMPONENT_DC)
-+
-+
-+#define LG_HW_TR_AUD_MSK (1 << LOG_MINOR_HW_TRACE_AUDIO)
-+#define LG_HW_TR_INTERRUPT_MSK (1 << LOG_MINOR_HW_TRACE_INTERRUPT) | \
-+		(1 << LOG_MINOR_HW_TRACE_HPD_IRQ)
-+#define LG_HW_TR_PLANES_MSK (1 << LOG_MINOR_HW_TRACE_MPO)
-+#define LG_ALL_MSK 0xffffffff
-+
-+#define LG_SYNC_MSK (1 << LOG_MINOR_SYNC_TIMING)
-+
-+#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION)
-+
-+
-+static const struct log_major_mask_info log_major_mask_info_tbl[] = {
-+	/* LogMajor                  major name       default     MinorTble                    tblElementCnt */
-+	{{LOG_MAJOR_ERROR,           "Error"       }, LG_ALL_MSK, component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
-+	{{LOG_MAJOR_WARNING,         "Warning"     }, LG_ALL_MSK, component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
-+	{{LOG_MAJOR_INTERFACE_TRACE, "IfTrace"     }, LG_ALL_MSK, component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
-+	{{LOG_MAJOR_HW_TRACE,        "HwTrace"     }, (LG_ALL_MSK &
-+			~((1 << LOG_MINOR_HW_TRACE_LINK_TRAINING) |
-+			(1 << LOG_MINOR_HW_TRACE_AUDIO))),
-+								hw_trace_minor_info_tbl,     NUM_ELEMENTS(hw_trace_minor_info_tbl)},
-+	{{LOG_MAJOR_MST,             "MST"         }, LG_ALL_MSK, mst_minor_info_tbl,          NUM_ELEMENTS(mst_minor_info_tbl)},
-+	{{LOG_MAJOR_DCS,             "DCS"         }, LG_ALL_MSK, dcs_minor_info_tbl,          NUM_ELEMENTS(dcs_minor_info_tbl)},
-+	{{LOG_MAJOR_DCP,             "DCP"         }, LG_ALL_MSK, dcp_minor_info_tbl,          NUM_ELEMENTS(dcp_minor_info_tbl)},
-+	{{LOG_MAJOR_BIOS,            "Bios"        }, LG_ALL_MSK, bios_minor_info_tbl,         NUM_ELEMENTS(bios_minor_info_tbl)},
-+	{{LOG_MAJOR_REGISTER,        "Register"    }, LG_ALL_MSK, reg_minor_info_tbl,          NUM_ELEMENTS(reg_minor_info_tbl)},
-+	{{LOG_MAJOR_INFO_PACKETS,    "InfoPacket"  }, LG_ALL_MSK, info_packet_minor_info_tbl,  NUM_ELEMENTS(info_packet_minor_info_tbl)},
-+	{{LOG_MAJOR_DSAT,            "DSAT"        }, LG_ALL_MSK, dsat_minor_info_tbl,         NUM_ELEMENTS(dsat_minor_info_tbl)},
-+	{{LOG_MAJOR_EC,              "EC"          }, LG_ALL_MSK, ec_minor_info_tbl,           NUM_ELEMENTS(ec_minor_info_tbl)},
-+	{{LOG_MAJOR_BWM,             "BWM"         }, LG_BWM_MSK, bwm_minor_info_tbl,          NUM_ELEMENTS(bwm_minor_info_tbl)},
-+	{{LOG_MAJOR_MODE_ENUM,       "ModeEnum"    }, LG_ALL_MSK, mode_enum_minor_info_tbl,    NUM_ELEMENTS(mode_enum_minor_info_tbl)},
-+	{{LOG_MAJOR_I2C_AUX,         "I2cAux"      }, LG_ALL_MSK, i2caux_minor_info_tbl,       NUM_ELEMENTS(i2caux_minor_info_tbl)},
-+	{{LOG_MAJOR_LINE_BUFFER,     "LineBuffer"  }, LG_ALL_MSK, line_buffer_minor_info_tbl,  NUM_ELEMENTS(line_buffer_minor_info_tbl)},
-+	{{LOG_MAJOR_HWSS,            "HWSS"        }, LG_ALL_MSK, hwss_minor_info_tbl,         NUM_ELEMENTS(hwss_minor_info_tbl)},
-+	{{LOG_MAJOR_OPTIMIZATION,    "Optimization"}, LG_ALL_MSK, optimization_minor_info_tbl, NUM_ELEMENTS(optimization_minor_info_tbl)},
-+	{{LOG_MAJOR_PERF_MEASURE,    "PerfMeasure" }, LG_ALL_MSK, perf_measure_minor_info_tbl, NUM_ELEMENTS(perf_measure_minor_info_tbl)},
-+	{{LOG_MAJOR_SYNC,            "Sync"        }, LG_SYNC_MSK,sync_minor_info_tbl,         NUM_ELEMENTS(sync_minor_info_tbl)},
-+	{{LOG_MAJOR_BACKLIGHT,       "Backlight"   }, LG_ALL_MSK, backlight_minor_info_tbl,    NUM_ELEMENTS(backlight_minor_info_tbl)},
-+	{{LOG_MAJOR_INTERRUPTS,      "Interrupts"  }, LG_ALL_MSK, component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
-+	{{LOG_MAJOR_TM,              "TM"          }, 0,          tm_minor_info_tbl,           NUM_ELEMENTS(tm_minor_info_tbl)},
-+	{{LOG_MAJOR_DISPLAY_SERVICE, "DS"          }, LG_ALL_MSK, ds_minor_info_tbl,           NUM_ELEMENTS(ds_minor_info_tbl)},
-+	{{LOG_MAJOR_FEATURE_OVERRIDE, "FeatureOverride" }, LG_ALL_MSK, override_feature_minor_info_tbl, NUM_ELEMENTS(override_feature_minor_info_tbl)},
-+	{{LOG_MAJOR_DETECTION,       "Detection"   }, LG_ALL_MSK,  detection_minor_info_tbl,    NUM_ELEMENTS(detection_minor_info_tbl)},
-+};
-+
-+/* ----------- Object init and destruction ----------- */
-+static bool construct(struct dc_context *ctx, struct dal_logger *logger)
-+{
-+	uint32_t i;
-+	/* malloc buffer and init offsets */
-+
-+	logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
-+	logger->log_buffer = (char *)dc_service_alloc(ctx,
-+		logger->log_buffer_size *
-+		sizeof(char));
-+
-+	if (!logger->log_buffer)
-+		return false;
-+
-+	/* todo: Fill buffer with \0 if not done by dal_alloc */
-+
-+	/* Initialize both offsets to start of buffer (empty) */
-+	logger->buffer_read_offset = 0;
-+	logger->buffer_write_offset = 0;
-+
-+	logger->write_wrap_count = 0;
-+	logger->read_wrap_count = 0;
-+	logger->open_count = 0;
-+
-+	logger->flags.bits.ENABLE_CONSOLE = 1;
-+	logger->flags.bits.ENABLE_BUFFER = 0;
-+
-+	logger->ctx = ctx;
-+
-+	/* malloc and init minor mask array */
-+	logger->log_enable_mask_minors =
-+			(uint32_t *)dc_service_alloc(
-+				ctx,
-+				NUM_ELEMENTS(log_major_mask_info_tbl)
-+				* sizeof(uint32_t));
-+	if (!logger->log_enable_mask_minors)
-+		return false;
-+
-+
-+	/* Set default values for mask */
-+	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-+
-+		uint32_t dflt_mask = log_major_mask_info_tbl[i].default_mask;
-+
-+		logger->log_enable_mask_minors[i] = dflt_mask;
-+	}
-+
-+	return true;
-+}
-+
-+static void destruct(struct dal_logger *logger)
-+{
-+	if (logger->log_buffer) {
-+		dc_service_free(logger->ctx, logger->log_buffer);
-+		logger->log_buffer = NULL;
-+	}
-+
-+	if (logger->log_enable_mask_minors) {
-+		dc_service_free(logger->ctx, logger->log_enable_mask_minors);
-+		logger->log_enable_mask_minors = NULL;
-+	}
-+}
-+
-+struct dal_logger *dal_logger_create(struct dc_context *ctx)
-+{
-+	/* malloc struct */
-+	struct dal_logger *logger = dc_service_alloc(ctx, sizeof(struct dal_logger));
-+
-+	if (!logger)
-+		return NULL;
-+	if (!construct(ctx, logger)) {
-+		dc_service_free(ctx, logger);
-+		return NULL;
-+	}
-+
-+	return logger;
-+}
-+
-+uint32_t dal_logger_destroy(struct dal_logger **logger)
-+{
-+	if (logger == NULL || *logger == NULL)
-+		return 1;
-+	destruct(*logger);
-+	dc_service_free((*logger)->ctx, *logger);
-+	*logger = NULL;
-+
-+	return 0;
-+}
-+
-+/* ------------------------------------------------------------------------ */
-+
-+static void lock(struct dal_logger *logger)
-+{
-+	/* Todo: lock mutex? */
-+}
-+
-+static void unlock(struct dal_logger *logger)
-+{
-+	/* Todo: unlock mutex */
-+}
-+
-+bool dal_logger_should_log(
-+	struct dal_logger *logger,
-+	enum log_major major,
-+	enum log_minor minor)
-+{
-+	if (major < LOG_MAJOR_COUNT) {
-+
-+		uint32_t minor_mask = logger->log_enable_mask_minors[major];
-+
-+		if ((minor_mask & (1 << minor)) != 0)
-+			return true;
-+	}
-+
-+	return false;
-+}
-+
-+static void log_to_debug_console(struct log_entry *entry)
-+{
-+	struct dal_logger *logger = entry->logger;
-+
-+	if (logger->flags.bits.ENABLE_CONSOLE == 0)
-+		return;
-+
-+	switch (entry->major) {
-+	case LOG_MAJOR_ERROR:
-+		dal_error("%s", entry->buf);
-+		break;
-+	default:
-+		dal_output_to_console("%s", entry->buf);
-+		break;
-+	}
-+}
-+
-+/* Print everything unread existing in log_buffer to debug console*/
-+static void flush_to_debug_console(struct dal_logger *logger)
-+{
-+	int i = logger->buffer_read_offset;
-+	char *string_start = &logger->log_buffer[i];
-+
-+	dal_output_to_console(
-+		"---------------- FLUSHING LOG BUFFER ----------------\n");
-+	while (i < logger->buffer_write_offset)	{
-+
-+		if (logger->log_buffer[i] == '\0') {
-+			dal_output_to_console("%s", string_start);
-+			string_start = (char *)logger->log_buffer + i + 1;
-+		}
-+		i++;
-+	}
-+	dal_output_to_console(
-+		"-------------- END FLUSHING LOG BUFFER --------------\n\n");
-+}
-+
-+static void log_to_internal_buffer(struct log_entry *entry)
-+{
-+
-+	uint32_t size = entry->buf_offset;
-+	struct dal_logger *logger = entry->logger;
-+
-+	if (logger->flags.bits.ENABLE_BUFFER == 0)
-+		return;
-+
-+	if (logger->log_buffer == NULL)
-+		return;
-+
-+	if (size > 0 && size < logger->log_buffer_size) {
-+
-+		int total_free_space = 0;
-+		int space_before_wrap = 0;
-+
-+		if (logger->buffer_write_offset > logger->buffer_read_offset) {
-+			total_free_space = logger->log_buffer_size -
-+					logger->buffer_write_offset +
-+					logger->buffer_read_offset;
-+			space_before_wrap = logger->log_buffer_size -
-+					logger->buffer_write_offset;
-+		} else if (logger->buffer_write_offset <
-+				logger->buffer_read_offset) {
-+			total_free_space = logger->log_buffer_size -
-+					logger->buffer_read_offset +
-+					logger->buffer_write_offset;
-+			space_before_wrap = total_free_space;
-+		} else if (logger->write_wrap_count !=
-+				logger->read_wrap_count) {
-+			/* Buffer is completely full already */
-+			total_free_space = 0;
-+			space_before_wrap = 0;
-+		} else {
-+			/* Buffer is empty, start writing at beginning */
-+			total_free_space = logger->log_buffer_size;
-+			space_before_wrap = logger->log_buffer_size;
-+			logger->buffer_write_offset = 0;
-+			logger->buffer_read_offset = 0;
-+		}
-+
-+
-+
-+
-+		if (space_before_wrap > size) {
-+			/* No wrap around, copy 'size' bytes
-+			 * from 'entry->buf' to 'log_buffer'
-+			 */
-+			dc_service_memmove(logger->log_buffer +
-+					logger->buffer_write_offset,
-+					entry->buf, size);
-+			logger->buffer_write_offset += size;
-+
-+		} else if (total_free_space > size) {
-+			/* We have enough room without flushing,
-+			 * but need to wrap around */
-+
-+			int space_after_wrap = total_free_space -
-+					space_before_wrap;
-+
-+			dc_service_memmove(logger->log_buffer +
-+					logger->buffer_write_offset,
-+					entry->buf, space_before_wrap);
-+			dc_service_memmove(logger->log_buffer, entry->buf +
-+					space_before_wrap, space_after_wrap);
-+
-+			logger->buffer_write_offset = space_after_wrap;
-+			logger->write_wrap_count++;
-+
-+		} else {
-+			/* Not enough room remaining, we should flush
-+			 * existing logs */
-+
-+			/* Flush existing unread logs to console */
-+			flush_to_debug_console(logger);
-+
-+			/* Start writing to beginning of buffer */
-+			dc_service_memmove(logger->log_buffer, entry->buf, size);
-+			logger->buffer_write_offset = size;
-+			logger->buffer_read_offset = 0;
-+		}
-+
-+	}
-+
-+	unlock(logger);
-+}
-+
-+
-+static void log_timestamp(struct log_entry *entry)
-+{
-+	dal_logger_append(entry, "00:00:00 ");
-+}
-+
-+static void log_major_minor(struct log_entry *entry)
-+{
-+	uint32_t i;
-+	enum log_major major = entry->major;
-+	enum log_minor minor = entry->minor;
-+
-+	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-+
-+		const struct log_major_mask_info *maj_mask_info =
-+				&log_major_mask_info_tbl[i];
-+
-+		if (maj_mask_info->major_info.major == major) {
-+
-+			dal_logger_append(entry, "[%s_",
-+					maj_mask_info->major_info.major_name);
-+
-+			if (maj_mask_info->minor_tbl != NULL) {
-+				uint32_t j;
-+
-+				for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
-+
-+					const struct log_minor_info *min_info = &maj_mask_info->minor_tbl[j];
-+
-+					if (min_info->minor == minor)
-+						dal_logger_append(entry, "%s]\t", min_info->minor_name);
-+				}
-+			}
-+
-+			break;
-+		}
-+	}
-+}
-+
-+static void log_heading(struct log_entry *entry,
-+			enum log_major major,
-+			enum log_minor minor)
-+{
-+	log_timestamp(entry);
-+	log_major_minor(entry);
-+}
-+
-+
-+static void append_entry(
-+		struct log_entry *entry,
-+		char *buffer,
-+		uint32_t buf_size)
-+{
-+	if (!entry->buf ||
-+		entry->buf_offset + buf_size > entry->max_buf_bytes
-+	) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/* Todo: check if off by 1 byte due to \0 anywhere */
-+	dc_service_memmove(entry->buf + entry->buf_offset, buffer, buf_size);
-+	entry->buf_offset += buf_size;
-+}
-+
-+/* ------------------------------------------------------------------------ */
-+
-+/* Warning: Be careful that 'msg' is null terminated and the total size is
-+ * less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
-+ */
-+void dal_logger_write(
-+	struct dal_logger *logger,
-+	enum log_major major,
-+	enum log_minor minor,
-+	const char *msg,
-+	...)
-+{
-+
-+	if (logger && dal_logger_should_log(logger, major, minor)) {
-+
-+		uint32_t size;
-+		va_list args;
-+		char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
-+		struct log_entry entry;
-+
-+		va_start(args, msg);
-+		dal_logger_open(logger, &entry, major, minor);
-+
-+
-+		size = dal_log_to_buffer(
-+			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
-+
-+		if (size > 0 && size <
-+				DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE - 1) {
-+
-+			if (buffer[size] == '\0')
-+				size++; /* Add one for null terminator */
-+
-+			/* Concatenate onto end of entry buffer */
-+			append_entry(&entry, buffer, size);
-+		} else {
-+			append_entry(&entry, "LOG_ERROR\n", 12);
-+		}
-+
-+		dal_logger_close(&entry);
-+		va_end(args);
-+
-+	}
-+}
-+
-+
-+/* Same as dal_logger_write, except without open() and close(), which must
-+ * be done separately.
-+ */
-+void dal_logger_append(
-+	struct log_entry *entry,
-+	const char *msg,
-+	...)
-+{
-+	struct dal_logger *logger;
-+
-+	if (!entry) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	logger = entry->logger;
-+
-+	if (logger && logger->open_count > 0 &&
-+		dal_logger_should_log(logger, entry->major, entry->minor)) {
-+
-+		uint32_t size;
-+		va_list args;
-+		char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
-+
-+		va_start(args, msg);
-+
-+		size = dal_log_to_buffer(
-+			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
-+		append_entry(entry, buffer, size);
-+
-+		va_end(args);
-+	}
-+}
-+
-+
-+uint32_t dal_logger_read(
-+	struct dal_logger *logger, /* <[in] */
-+	uint32_t output_buffer_size, /* <[in] */
-+	char *output_buffer, /* >[out] */
-+	uint32_t *bytes_read, /* >[out] */
-+	bool single_line)
-+{
-+	uint32_t bytes_remaining = 0;
-+	uint32_t bytes_read_count = 0;
-+	bool keep_reading = true;
-+
-+	if (!logger || output_buffer == NULL || output_buffer_size == 0) {
-+		BREAK_TO_DEBUGGER();
-+		*bytes_read = 0;
-+		return 0;
-+	}
-+
-+	lock(logger);
-+
-+	/* Read until null terminator (if single_line==true,
-+	 *  max buffer size, or until we've read everything new
-+	 */
-+
-+	do {
-+		char cur;
-+
-+		/* Stop when we've read everything */
-+		if (logger->buffer_read_offset ==
-+			logger->buffer_write_offset) {
-+
-+			break;
-+		}
-+
-+		cur = logger->log_buffer[logger->buffer_read_offset];
-+		logger->buffer_read_offset++;
-+
-+		/* Wrap read pointer if at end */
-+		if (logger->buffer_read_offset == logger->log_buffer_size) {
-+
-+			logger->buffer_read_offset = 0;
-+			logger->read_wrap_count++;
-+		}
-+
-+		/* Don't send null terminators to buffer */
-+		if (cur != '\0') {
-+			output_buffer[bytes_read_count] = cur;
-+			bytes_read_count++;
-+		} else if (single_line) {
-+			keep_reading = false;
-+		}
-+
-+	} while (bytes_read_count <= output_buffer_size && keep_reading);
-+
-+	/* We assume that reading can never be ahead of writing */
-+	if (logger->write_wrap_count > logger->read_wrap_count) {
-+		bytes_remaining = logger->log_buffer_size -
-+			logger->buffer_read_offset +
-+			logger->buffer_write_offset;
-+	} else {
-+		bytes_remaining = logger->buffer_write_offset -
-+				logger->buffer_read_offset;
-+	}
-+
-+	/* reset write/read wrap count to 0 if we've read everything */
-+	if (bytes_remaining == 0) {
-+
-+		logger->write_wrap_count = 0;
-+		logger->read_wrap_count = 0;
-+	}
-+
-+	*bytes_read = bytes_read_count;
-+	unlock(logger);
-+
-+	return bytes_remaining;
-+}
-+
-+void dal_logger_open(
-+		struct dal_logger *logger,
-+		struct log_entry *entry, /* out */
-+		enum log_major major,
-+		enum log_minor minor)
-+{
-+	if (!entry) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	entry->major = LOG_MAJOR_COUNT;
-+	entry->minor = 0;
-+	entry->logger = logger;
-+
-+	entry->buf = dc_service_alloc(
-+		logger->ctx,
-+		DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char));
-+
-+	entry->buf_offset = 0;
-+	entry->max_buf_bytes =
-+			DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char);
-+
-+	logger->open_count++;
-+	entry->major = major;
-+	entry->minor = minor;
-+
-+	log_heading(entry, major, minor);
-+}
-+
-+void dal_logger_close(struct log_entry *entry)
-+{
-+	struct dal_logger *logger = entry->logger;
-+
-+
-+	if (logger && logger->open_count > 0) {
-+		logger->open_count--;
-+	} else {
-+		BREAK_TO_DEBUGGER();
-+		goto cleanup;
-+	}
-+
-+	/* --Flush log_entry buffer-- */
-+	/* print to kernel console */
-+	log_to_debug_console(entry);
-+	/* log internally for dsat */
-+	log_to_internal_buffer(entry);
-+
-+	/* TODO: Write end heading */
-+
-+cleanup:
-+	if (entry->buf) {
-+		dc_service_free(entry->logger->ctx, entry->buf);
-+		entry->buf = NULL;
-+		entry->buf_offset = 0;
-+		entry->max_buf_bytes = 0;
-+	}
-+}
-+
-+uint32_t dal_logger_get_mask(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major, enum log_minor lvl_minor)
-+{
-+	uint32_t log_mask = 0;
-+
-+	if (logger && lvl_major < LOG_MAJOR_COUNT)
-+		log_mask = logger->log_enable_mask_minors[lvl_major];
-+
-+	log_mask &= 1 << lvl_minor;
-+	return log_mask;
-+}
-+
-+uint32_t dal_logger_set_mask(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major, enum log_minor lvl_minor)
-+{
-+
-+	if (logger && lvl_major < LOG_MAJOR_COUNT) {
-+		if (lvl_minor == LOG_MINOR_MASK_ALL) {
-+			logger->log_enable_mask_minors[lvl_major] = 0xFFFFFFFF;
-+		} else {
-+			logger->log_enable_mask_minors[lvl_major] |=
-+				(1 << lvl_minor);
-+		}
-+		return 0;
-+	}
-+	return 1;
-+}
-+
-+uint32_t dal_logger_get_masks(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major)
-+{
-+	uint32_t log_mask = 0;
-+
-+	if (logger && lvl_major < LOG_MAJOR_COUNT)
-+		log_mask = logger->log_enable_mask_minors[lvl_major];
-+
-+	return log_mask;
-+}
-+
-+void dal_logger_set_masks(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major, uint32_t log_mask)
-+{
-+	if (logger && lvl_major < LOG_MAJOR_COUNT)
-+		logger->log_enable_mask_minors[lvl_major] = log_mask;
-+}
-+
-+uint32_t dal_logger_unset_mask(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major, enum log_minor lvl_minor)
-+{
-+
-+	if (lvl_major < LOG_MAJOR_COUNT) {
-+		if (lvl_minor == LOG_MINOR_MASK_ALL) {
-+			logger->log_enable_mask_minors[lvl_major] = 0;
-+		} else {
-+			logger->log_enable_mask_minors[lvl_major] &=
-+				~(1 << lvl_minor);
-+		}
-+		return 0;
-+	}
-+	return 1;
-+}
-+
-+uint32_t dal_logger_get_flags(
-+		struct dal_logger *logger)
-+{
-+
-+	return logger->flags.value;
-+}
-+
-+void dal_logger_set_flags(
-+		struct dal_logger *logger,
-+		union logger_flags flags)
-+{
-+
-+	logger->flags = flags;
-+}
-+
-+
-+uint32_t dal_logger_get_buffer_size(struct dal_logger *logger)
-+{
-+	return DAL_LOGGER_BUFFER_MAX_SIZE;
-+}
-+
-+uint32_t dal_logger_set_buffer_size(
-+		struct dal_logger *logger,
-+		uint32_t new_size)
-+{
-+	/* ToDo: implement dynamic size */
-+
-+	/* return new size */
-+	return DAL_LOGGER_BUFFER_MAX_SIZE;
-+}
-+
-+
-+const struct log_major_info *dal_logger_enum_log_major_info(
-+		struct dal_logger *logger,
-+		unsigned int enum_index)
-+{
-+	const struct log_major_info *major_info;
-+
-+	if (enum_index >= NUM_ELEMENTS(log_major_mask_info_tbl))
-+		return NULL;
-+
-+	major_info = &log_major_mask_info_tbl[enum_index].major_info;
-+	return major_info;
-+}
-+
-+const struct log_minor_info *dal_logger_enum_log_minor_info(
-+		struct dal_logger *logger,
-+		enum log_major major,
-+		unsigned int enum_index)
-+{
-+	const struct log_minor_info *minor_info = NULL;
-+	uint32_t i;
-+
-+	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-+
-+		const struct log_major_mask_info *maj_mask_info =
-+				&log_major_mask_info_tbl[i];
-+
-+		if (maj_mask_info->major_info.major == major) {
-+
-+			if (maj_mask_info->minor_tbl != NULL) {
-+				uint32_t j;
-+
-+				for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
-+
-+					minor_info = &maj_mask_info->minor_tbl[j];
-+
-+					if (minor_info->minor == enum_index)
-+						return minor_info;
-+				}
-+			}
-+
-+			break;
-+		}
-+	}
-+	return NULL;
-+
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.h b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-new file mode 100644
-index 0000000..fba5ec3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_H__
-+#define __DAL_LOGGER_H__
-+
-+/* Structure for keeping track of offsets, buffer, etc */
-+
-+#define DAL_LOGGER_BUFFER_MAX_SIZE 2048
-+#define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 256
-+
-+
-+#include "include/logger_types.h"
-+
-+struct dal_logger {
-+
-+	/* How far into the circular buffer has been read by dsat
-+	 * Read offset should never cross write offset. Write \0's to
-+	 * read data just to be sure?
-+	 */
-+	uint32_t buffer_read_offset;
-+
-+	/* How far into the circular buffer we have written
-+	 * Write offset should never cross read offset
-+	 */
-+	uint32_t buffer_write_offset;
-+
-+	uint32_t write_wrap_count;
-+	uint32_t read_wrap_count;
-+
-+	uint32_t open_count;
-+
-+	char *log_buffer;	/* Pointer to malloc'ed buffer */
-+	uint32_t log_buffer_size; /* Size of circular buffer */
-+
-+	uint32_t *log_enable_mask_minors; /*array of masks for major elements*/
-+
-+	union logger_flags flags;
-+	struct dc_context *ctx;
-+};
-+
-+#endif /* __DAL_LOGGER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-new file mode 100644
-index 0000000..a3086a0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-@@ -0,0 +1,197 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/dal_types.h"
-+#include "include/logger_interface.h"
-+#include "logger.h"
-+
-+/******************************************************************************
-+ * Register Logger.
-+ * A facility to create register R/W logs.
-+ * Currently used for DAL Test.
-+ *****************************************************************************/
-+
-+/******************************************************************************
-+ * Private structures
-+ *****************************************************************************/
-+struct dal_reg_dump_stack_location {
-+	const char *current_caller_func;
-+	long current_pid;
-+	long current_tgid;
-+	uint32_t rw_count;/* register access counter for current function. */
-+};
-+
-+/* This the maximum number of nested calls to the 'reg_dump' facility. */
-+#define DAL_REG_DUMP_STACK_MAX_SIZE 32
-+
-+struct dal_reg_dump_stack {
-+	int32_t stack_pointer;
-+	struct dal_reg_dump_stack_location
-+		stack_locations[DAL_REG_DUMP_STACK_MAX_SIZE];
-+	uint32_t total_rw_count; /* Total count for *all* functions. */
-+};
-+
-+static struct dal_reg_dump_stack reg_dump_stack = {0};
-+
-+/******************************************************************************
-+ * Private functions
-+ *****************************************************************************/
-+
-+/* Check if current process is the one which requested register dump.
-+ * The reason for the check:
-+ * mmCRTC_STATUS_FRAME_COUNT is accessed by dal_controller_get_vblank_counter().
-+ * Which runs all the time when at least one display is connected.
-+ * (Triggered by drm_mode_page_flip_ioctl()). */
-+static bool is_reg_dump_process(void)
-+{
-+	uint32_t i;
-+
-+	/* walk the list of our processes */
-+	for (i = 0; i < reg_dump_stack.stack_pointer; i++) {
-+		struct dal_reg_dump_stack_location *stack_location
-+					= &reg_dump_stack.stack_locations[i];
-+
-+		if (stack_location->current_pid == dal_get_pid()
-+			&& stack_location->current_tgid == dal_get_tgid())
-+			return true;
-+	}
-+
-+	return false;
-+}
-+
-+static bool dal_reg_dump_stack_is_empty(void)
-+{
-+	if (reg_dump_stack.stack_pointer <= 0)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static struct dal_reg_dump_stack_location *dal_reg_dump_stack_push(void)
-+{
-+	struct dal_reg_dump_stack_location *current_location = NULL;
-+
-+	if (reg_dump_stack.stack_pointer >= DAL_REG_DUMP_STACK_MAX_SIZE) {
-+		/* stack is full */
-+		dal_output_to_console("[REG_DUMP]: %s: stack is full!\n",
-+				__func__);
-+	} else {
-+		current_location =
-+		&reg_dump_stack.stack_locations[reg_dump_stack.stack_pointer];
-+		++reg_dump_stack.stack_pointer;
-+	}
-+
-+	return current_location;
-+}
-+
-+static struct dal_reg_dump_stack_location *dal_reg_dump_stack_pop(void)
-+{
-+	struct dal_reg_dump_stack_location *current_location = NULL;
-+
-+	if (dal_reg_dump_stack_is_empty()) {
-+		/* stack is empty */
-+		dal_output_to_console("[REG_DUMP]: %s: stack is empty!\n",
-+				__func__);
-+	} else {
-+		--reg_dump_stack.stack_pointer;
-+		current_location =
-+		&reg_dump_stack.stack_locations[reg_dump_stack.stack_pointer];
-+	}
-+
-+	return current_location;
-+}
-+
-+/******************************************************************************
-+ * Public functions
-+ *****************************************************************************/
-+
-+void dal_reg_logger_push(const char *caller_func)
-+{
-+	struct dal_reg_dump_stack_location *free_stack_location;
-+
-+	free_stack_location = dal_reg_dump_stack_push();
-+
-+	if (NULL == free_stack_location)
-+		return;
-+
-+	dc_service_memset(free_stack_location, 0, sizeof(*free_stack_location));
-+
-+	free_stack_location->current_caller_func = caller_func;
-+	free_stack_location->current_pid = dal_get_pid();
-+	free_stack_location->current_tgid = dal_get_tgid();
-+
-+	dal_output_to_console("[REG_DUMP]:%s - start (pid:%ld, tgid:%ld)\n",
-+		caller_func,
-+		free_stack_location->current_pid,
-+		free_stack_location->current_tgid);
-+}
-+
-+void dal_reg_logger_pop(void)
-+{
-+	struct dal_reg_dump_stack_location *top_stack_location;
-+
-+	top_stack_location = dal_reg_dump_stack_pop();
-+
-+	if (NULL == top_stack_location) {
-+		dal_output_to_console("[REG_DUMP]:%s - Stack is Empty!\n",
-+				__func__);
-+		return;
-+	}
-+
-+	dal_output_to_console(
-+	"[REG_DUMP]:%s - end."\
-+	" Reg R/W Count: Total=%d Function=%d. (pid:%ld, tgid:%ld)\n",
-+			top_stack_location->current_caller_func,
-+			reg_dump_stack.total_rw_count,
-+			top_stack_location->rw_count,
-+			dal_get_pid(),
-+			dal_get_tgid());
-+
-+	dc_service_memset(top_stack_location, 0, sizeof(*top_stack_location));
-+}
-+
-+void dal_reg_logger_rw_count_increment(void)
-+{
-+	++reg_dump_stack.total_rw_count;
-+
-+	++reg_dump_stack.stack_locations
-+		[reg_dump_stack.stack_pointer - 1].rw_count;
-+}
-+
-+bool dal_reg_logger_should_dump_register(void)
-+{
-+	if (true == dal_reg_dump_stack_is_empty())
-+		return false;
-+
-+	if (false == is_reg_dump_process())
-+		return false;
-+
-+	return true;
-+}
-+
-+/******************************************************************************
-+ * End of File.
-+ *****************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c b/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-new file mode 100644
-index 0000000..f589091
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+#include "include/signal_types.h"
-+
-+bool dc_is_hdmi_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
-+}
-+
-+bool dc_is_dp_sst_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_EDP);
-+}
-+
-+bool dc_is_dp_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_EDP ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-+}
-+
-+bool dc_is_dp_external_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-+}
-+
-+bool dc_is_analog_signal(enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_RGB:
-+		return true;
-+	break;
-+	default:
-+		return false;
-+	}
-+}
-+
-+bool dc_is_embedded_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
-+}
-+
-+bool dc_is_dvi_signal(enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		return true;
-+	break;
-+	default:
-+		return false;
-+	}
-+}
-+
-+bool dc_is_dvi_single_link_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
-+}
-+
-+bool dc_is_dual_link_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DVI_DUAL_LINK);
-+}
-+
-+bool dc_is_audio_capable_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-+		dc_is_hdmi_signal(signal) ||
-+		signal == SIGNAL_TYPE_WIRELESS);
-+}
-+
-+/*
-+ * @brief
-+ * Returns whether the signal is compatible
-+ * with other digital encoder signal types.
-+ * This is true for DVI, LVDS, and HDMI signal types.
-+ */
-+bool dc_is_digital_encoder_compatible_signal(enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_LVDS:
-+		return true;
-+	default:
-+		return false;
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/vector.c b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-new file mode 100644
-index 0000000..2f932c0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-@@ -0,0 +1,309 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/vector.h"
-+
-+bool dal_vector_construct(
-+	struct vector *vector,
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size)
-+{
-+	vector->container = NULL;
-+
-+	if (!struct_size || !capacity) {
-+		/* Container must be non-zero size*/
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	vector->container = dc_service_alloc(ctx, struct_size * capacity);
-+	if (vector->container == NULL)
-+		return false;
-+	vector->capacity = capacity;
-+	vector->struct_size = struct_size;
-+	vector->count = 0;
-+	vector->ctx = ctx;
-+	return true;
-+}
-+
-+bool dal_vector_presized_costruct(
-+	struct vector *vector,
-+	struct dc_context *ctx,
-+	uint32_t count,
-+	void *initial_value,
-+	uint32_t struct_size)
-+{
-+	uint32_t i;
-+
-+	vector->container = NULL;
-+
-+	if (!struct_size || !count) {
-+		/* Container must be non-zero size*/
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	vector->container = dc_service_alloc(ctx, struct_size * count);
-+
-+	if (vector->container == NULL)
-+		return false;
-+
-+	/* If caller didn't supply initial value then the default
-+	 * of all zeros is expected, which is exactly what dal_alloc()
-+	 * initialises the memory to. */
-+	if (NULL != initial_value) {
-+		for (i = 0; i < count; ++i)
-+			dc_service_memmove(
-+				vector->container + i * struct_size,
-+				initial_value,
-+				struct_size);
-+	}
-+
-+	vector->capacity = count;
-+	vector->struct_size = struct_size;
-+	vector->count = count;
-+	return true;
-+}
-+
-+struct vector *dal_vector_presized_create(
-+	struct dc_context *ctx,
-+	uint32_t size,
-+	void *initial_value,
-+	uint32_t struct_size)
-+{
-+	struct vector *vector = dc_service_alloc(ctx, sizeof(struct vector));
-+
-+	if (vector == NULL)
-+		return NULL;
-+
-+	if (dal_vector_presized_costruct(
-+		vector, ctx, size, initial_value, struct_size))
-+		return vector;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, vector);
-+	return NULL;
-+}
-+
-+struct vector *dal_vector_create(
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size)
-+{
-+	struct vector *vector = dc_service_alloc(ctx, sizeof(struct vector));
-+
-+	if (vector == NULL)
-+		return NULL;
-+
-+	if (dal_vector_construct(vector, ctx, capacity, struct_size))
-+		return vector;
-+
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, vector);
-+	return NULL;
-+}
-+
-+void dal_vector_destruct(
-+	struct vector *vector)
-+{
-+	if (vector->container != NULL)
-+		dc_service_free(vector->ctx, vector->container);
-+	vector->count = 0;
-+	vector->capacity = 0;
-+}
-+
-+void dal_vector_destroy(
-+	struct vector **vector)
-+{
-+	if (vector == NULL || *vector == NULL)
-+		return;
-+	dal_vector_destruct(*vector);
-+	dc_service_free((*vector)->ctx, *vector);
-+	*vector = NULL;
-+}
-+
-+uint32_t dal_vector_get_count(
-+	const struct vector *vector)
-+{
-+	return vector->count;
-+}
-+
-+void *dal_vector_at_index(
-+	const struct vector *vector,
-+	uint32_t index)
-+{
-+	if (vector->container == NULL || index >= vector->count)
-+		return NULL;
-+	return vector->container + (index * vector->struct_size);
-+}
-+
-+bool dal_vector_remove_at_index(
-+	struct vector *vector,
-+	uint32_t index)
-+{
-+	if (index >= vector->count)
-+		return false;
-+
-+	if (index != vector->count - 1)
-+		dc_service_memmove(
-+			vector->container + (index * vector->struct_size),
-+			vector->container + ((index + 1) * vector->struct_size),
-+			(vector->count - index - 1) * vector->struct_size);
-+	vector->count -= 1;
-+
-+	return true;
-+}
-+
-+void dal_vector_set_at_index(
-+	const struct vector *vector,
-+	const void *what,
-+	uint32_t index)
-+{
-+	void *where = dal_vector_at_index(vector, index);
-+
-+	if (!where) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+	dc_service_memmove(
-+		where,
-+		what,
-+		vector->struct_size);
-+}
-+
-+static inline uint32_t calc_increased_capacity(
-+	uint32_t old_capacity)
-+{
-+	return old_capacity * 2;
-+}
-+
-+bool dal_vector_insert_at(
-+	struct vector *vector,
-+	const void *what,
-+	uint32_t position)
-+{
-+	uint8_t *insert_address;
-+
-+	if (vector->count == vector->capacity) {
-+		if (!dal_vector_reserve(
-+			vector,
-+			calc_increased_capacity(vector->capacity)))
-+			return false;
-+	}
-+
-+	insert_address = vector->container + (vector->struct_size * position);
-+
-+	if (vector->count && position < vector->count)
-+		dc_service_memmove(
-+			insert_address + vector->struct_size,
-+			insert_address,
-+			vector->struct_size * (vector->count - position));
-+
-+	dc_service_memmove(
-+		insert_address,
-+		what,
-+		vector->struct_size);
-+
-+	vector->count++;
-+
-+	return true;
-+}
-+
-+bool dal_vector_append(
-+	struct vector *vector,
-+	const void *item)
-+{
-+	return dal_vector_insert_at(vector, item, vector->count);
-+}
-+
-+struct vector *dal_vector_clone(
-+	const struct vector *vector)
-+{
-+	struct vector *vec_cloned;
-+	uint32_t count;
-+
-+	/* create new vector */
-+	count = dal_vector_get_count(vector);
-+
-+	if (count == 0)
-+		/* when count is 0 we still want to create clone of the vector
-+		 */
-+		vec_cloned = dal_vector_create(
-+			vector->ctx,
-+			vector->capacity,
-+			vector->struct_size);
-+	else
-+		/* Call "presized create" version, independently of how the
-+		 * original vector was created.
-+		 * The owner of original vector must know how to treat the new
-+		 * vector - as "presized" or as "regular".
-+		 * But from vector point of view it doesn't matter. */
-+		vec_cloned = dal_vector_presized_create(vector->ctx, count,
-+			NULL,/* no initial value */
-+			vector->struct_size);
-+
-+	if (NULL == vec_cloned) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	/* copy vector's data */
-+	dc_service_memmove(vec_cloned->container, vector->container,
-+			vec_cloned->struct_size * vec_cloned->capacity);
-+
-+	return vec_cloned;
-+}
-+
-+uint32_t dal_vector_capacity(const struct vector *vector)
-+{
-+	return vector->capacity;
-+}
-+
-+bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
-+{
-+	void *new_container;
-+
-+	if (capacity <= vector->capacity)
-+		return true;
-+
-+	new_container = dc_service_realloc(vector->ctx, vector->container,
-+		capacity * vector->struct_size);
-+
-+	if (new_container) {
-+		vector->container = new_container;
-+		vector->capacity = capacity;
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+void dal_vector_clear(struct vector *vector)
-+{
-+	vector->count = 0;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-new file mode 100644
-index 0000000..75bb892
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-@@ -0,0 +1,27 @@
-+#
-+# Makefile for the 'bios' sub-component of DAL.
-+# It provides the parsing and executing controls for atom bios image.
-+
-+BIOS = bios_parser.o bios_parser_helper.o command_table.o command_table_helper.o
-+
-+AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
-+
-+AMD_DAL_FILES += $(AMD_DAL_BIOS)
-+
-+ifndef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+AMD_DAL_FILES := $(filter-out $(AMDDALPATH)/dc/bios/bios_parser_helper.o,$(AMD_DAL_FILES))
-+endif
-+$(warning AMD_DAL_FILES=$(AMD_DAL_FILES))
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+
-+ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/bios_parser_helper_dce110.o
-+endif
-+
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-new file mode 100644
-index 0000000..7a2b247
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -0,0 +1,4758 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "command_table.h"
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+#include "bios_parser_helper.h"
-+#endif
-+#include "command_table_helper.h"
-+#include "bios_parser.h"
-+
-+#define THREE_PERCENT_OF_10000 300
-+
-+#define LAST_RECORD_TYPE 0xff
-+
-+/* GUID to validate external display connection info table (aka OPM module) */
-+static const uint8_t ext_display_connection_guid[NUMBER_OF_UCHAR_FOR_GUID] = {
-+	0x91, 0x6E, 0x57, 0x09,
-+	0x3F, 0x6D, 0xD2, 0x11,
-+	0x39, 0x8E, 0x00, 0xA0,
-+	0xC9, 0x69, 0x72, 0x3B};
-+
-+#define GET_IMAGE(type, offset) ((type *) get_image(bp, offset, sizeof(type)))
-+#define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table)
-+
-+static uint8_t *get_image(struct bios_parser *bp, uint32_t offset,
-+	uint32_t size);
-+static uint32_t get_record_size(uint8_t *record);
-+static uint32_t get_edid_size(const ATOM_FAKE_EDID_PATCH_RECORD *edid);
-+static enum object_type object_type_from_bios_object_id(
-+	uint32_t bios_object_id);
-+static struct graphics_object_id object_id_from_bios_object_id(
-+	uint32_t bios_object_id);
-+static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id);
-+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id);
-+static enum connector_id connector_id_from_bios_object_id(
-+	uint32_t bios_object_id);
-+static uint32_t id_from_bios_object_id(enum object_type type,
-+	uint32_t bios_object_id);
-+static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id);
-+static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id);
-+static void get_atom_data_table_revision(
-+	ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
-+	struct atom_data_revision *tbl_revision);
-+static uint32_t get_dst_number_from_object(struct bios_parser *bp,
-+	ATOM_OBJECT *object);
-+static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
-+	uint16_t **id_list);
-+static uint32_t get_dest_obj_list(struct bios_parser *bp,
-+	ATOM_OBJECT *object, uint16_t **id_list);
-+static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
-+	struct graphics_object_id id);
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+	ATOM_I2C_RECORD *record,
-+	struct graphics_object_i2c_info *info);
-+static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
-+	ATOM_OBJECT *object);
-+static struct device_id device_type_from_device_id(uint16_t device_id);
-+static uint32_t signal_to_ss_id(enum as_signal_type signal);
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id);
-+static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object);
-+static void process_ext_display_connection_info(struct bios_parser *bp);
-+
-+#define BIOS_IMAGE_SIZE_OFFSET 2
-+#define BIOS_IMAGE_SIZE_UNIT 512
-+
-+static bool bios_parser_construct(
-+	struct bios_parser *bp,
-+	struct bp_init_data *init,
-+	struct adapter_service *as)
-+{
-+	uint16_t *rom_header_offset = NULL;
-+	ATOM_ROM_HEADER *rom_header = NULL;
-+	ATOM_OBJECT_HEADER *object_info_tbl;
-+	enum dce_version dce_version;
-+
-+	if (!as)
-+		return false;
-+
-+	if (!init)
-+		return false;
-+
-+	if (!init->bios)
-+		return false;
-+
-+	dce_version = dal_adapter_service_get_dce_version(as);
-+	bp->ctx = init->ctx;
-+	bp->as = as;
-+	bp->bios = init->bios;
-+	bp->bios_size = bp->bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT;
-+	bp->bios_local_image = NULL;
-+	bp->lcd_scale = LCD_SCALE_UNKNOWN;
-+
-+	rom_header_offset =
-+	GET_IMAGE(uint16_t, OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
-+
-+	if (!rom_header_offset)
-+		return false;
-+
-+	rom_header = GET_IMAGE(ATOM_ROM_HEADER, *rom_header_offset);
-+
-+	if (!rom_header)
-+		return false;
-+
-+	bp->master_data_tbl =
-+	GET_IMAGE(ATOM_MASTER_DATA_TABLE,
-+		rom_header->usMasterDataTableOffset);
-+
-+	if (!bp->master_data_tbl)
-+		return false;
-+
-+	bp->object_info_tbl_offset = DATA_TABLES(Object_Header);
-+
-+	if (!bp->object_info_tbl_offset)
-+		return false;
-+
-+	object_info_tbl =
-+	GET_IMAGE(ATOM_OBJECT_HEADER, bp->object_info_tbl_offset);
-+
-+	if (!object_info_tbl)
-+		return false;
-+
-+	get_atom_data_table_revision(&object_info_tbl->sHeader,
-+		&bp->object_info_tbl.revision);
-+
-+	if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 3) {
-+		ATOM_OBJECT_HEADER_V3 *tbl_v3;
-+
-+		tbl_v3 = GET_IMAGE(ATOM_OBJECT_HEADER_V3,
-+			bp->object_info_tbl_offset);
-+		if (!tbl_v3)
-+			return false;
-+
-+		bp->object_info_tbl.v1_3 = tbl_v3;
-+	} else if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 1)
-+		bp->object_info_tbl.v1_1 = object_info_tbl;
-+	else
-+		return false;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	bp->vbios_helper_data.active = 0;
-+	bp->vbios_helper_data.requested = 0;
-+	dal_bios_parser_init_bios_helper(bp, dce_version);
-+#endif
-+	dal_bios_parser_init_cmd_tbl(bp);
-+	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
-+
-+	return true;
-+}
-+
-+struct bios_parser *dal_bios_parser_create(
-+	struct bp_init_data *init, struct adapter_service *as)
-+{
-+	struct bios_parser *bp = NULL;
-+
-+	bp = dc_service_alloc(init->ctx, sizeof(struct bios_parser));
-+	if (!bp)
-+		return NULL;
-+
-+	if (bios_parser_construct(bp, init, as))
-+		return bp;
-+
-+	dc_service_free(init->ctx, bp);
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+static void destruct(struct bios_parser *bp)
-+{
-+	if (bp->bios_local_image)
-+		dc_service_free(bp->ctx, bp->bios_local_image);
-+}
-+
-+void dal_bios_parser_destroy(struct bios_parser **bp)
-+{
-+	if (!bp || !*bp) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	destruct(*bp);
-+
-+	dc_service_free((*bp)->ctx, *bp);
-+	*bp = NULL;
-+}
-+
-+void dal_bios_parser_power_down(struct bios_parser *bp)
-+{
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	dal_bios_parser_set_scratch_lcd_scale(bp, bp->lcd_scale);
-+#endif
-+}
-+
-+void dal_bios_parser_power_up(struct bios_parser *bp)
-+{
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	if (bp->lcd_scale == LCD_SCALE_UNKNOWN)
-+		bp->lcd_scale = dal_bios_parser_get_scratch_lcd_scale(bp);
-+#endif
-+}
-+
-+static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)
-+{
-+	ATOM_OBJECT_TABLE *table;
-+
-+	uint32_t object_table_offset = bp->object_info_tbl_offset + offset;
-+
-+	table = GET_IMAGE(ATOM_OBJECT_TABLE, object_table_offset);
-+
-+	if (!table)
-+		return 0;
-+	else
-+		return table->ucNumberOfObjects;
-+}
-+
-+uint8_t dal_bios_parser_get_encoders_number(struct bios_parser *bp)
-+{
-+	return get_number_of_objects(bp,
-+		le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset));
-+}
-+
-+uint8_t dal_bios_parser_get_connectors_number(struct bios_parser *bp)
-+{
-+	return get_number_of_objects(bp,
-+		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset));
-+}
-+
-+uint32_t dal_bios_parser_get_oem_ddc_lines_number(struct bios_parser *bp)
-+{
-+	uint32_t number = 0;
-+
-+	if (DATA_TABLES(OemInfo) != 0) {
-+		ATOM_OEM_INFO *info;
-+
-+		info = GET_IMAGE(ATOM_OEM_INFO,
-+			DATA_TABLES(OemInfo));
-+
-+		if (le16_to_cpu(info->sHeader.usStructureSize)
-+			> sizeof(ATOM_COMMON_TABLE_HEADER)) {
-+
-+			number = (le16_to_cpu(info->sHeader.usStructureSize)
-+				- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_I2C_ID_CONFIG_ACCESS);
-+
-+		}
-+	}
-+
-+	return number;
-+}
-+
-+struct graphics_object_id dal_bios_parser_get_encoder_id(struct bios_parser *bp,
-+	uint32_t i)
-+{
-+	struct graphics_object_id object_id = dal_graphics_object_id_init(
-+		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+	uint32_t encoder_table_offset = bp->object_info_tbl_offset
-+		+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+
-+	ATOM_OBJECT_TABLE *tbl =
-+		GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
-+
-+	if (tbl && tbl->ucNumberOfObjects > i) {
-+		const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-+
-+		object_id = object_id_from_bios_object_id(id);
-+	}
-+
-+	return object_id;
-+}
-+
-+struct graphics_object_id dal_bios_parser_get_connector_id(
-+	struct bios_parser *bp,
-+	uint8_t i)
-+{
-+	struct graphics_object_id object_id = dal_graphics_object_id_init(
-+		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+	uint32_t connector_table_offset = bp->object_info_tbl_offset
-+		+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+
-+	ATOM_OBJECT_TABLE *tbl =
-+		GET_IMAGE(ATOM_OBJECT_TABLE, connector_table_offset);
-+
-+	if (tbl && tbl->ucNumberOfObjects > i) {
-+		const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-+
-+		object_id = object_id_from_bios_object_id(id);
-+	}
-+
-+	return object_id;
-+}
-+
-+uint32_t dal_bios_parser_get_src_number(struct bios_parser *bp,
-+	struct graphics_object_id id)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+	ATOM_OBJECT *object;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+uint32_t dal_bios_parser_get_dst_number(struct bios_parser *bp,
-+	struct graphics_object_id id)
-+{
-+	ATOM_OBJECT *object = get_bios_object(bp, id);
-+
-+	return get_dst_number_from_object(bp, object);
-+}
-+
-+enum bp_result dal_bios_parser_get_src_obj(struct bios_parser *bp,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *src_object_id)
-+{
-+	uint32_t number;
-+	uint16_t *id;
-+	ATOM_OBJECT *object;
-+
-+	if (!src_object_id)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	number = get_src_obj_list(bp, object, &id);
-+
-+	if (number <= index)
-+		return BP_RESULT_BADINPUT;
-+
-+	*src_object_id = object_id_from_bios_object_id(id[index]);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+enum bp_result dal_bios_parser_get_dst_obj(struct bios_parser *bp,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *dest_object_id)
-+{
-+	uint32_t number;
-+	uint16_t *id;
-+	ATOM_OBJECT *object;
-+
-+	if (!dest_object_id)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	number = get_dest_obj_list(bp, object, &id);
-+
-+	if (number <= index)
-+		return BP_RESULT_BADINPUT;
-+
-+	*dest_object_id = object_id_from_bios_object_id(id[index]);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+enum bp_result dal_bios_parser_get_oem_ddc_info(struct bios_parser *bp,
-+	uint32_t index,
-+	struct graphics_object_i2c_info *info)
-+{
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (DATA_TABLES(OemInfo) != 0) {
-+		ATOM_OEM_INFO *tbl;
-+
-+		tbl = GET_IMAGE(ATOM_OEM_INFO, DATA_TABLES(OemInfo));
-+
-+		if (le16_to_cpu(tbl->sHeader.usStructureSize)
-+			> sizeof(ATOM_COMMON_TABLE_HEADER)) {
-+			ATOM_I2C_RECORD record;
-+			ATOM_I2C_ID_CONFIG_ACCESS *config;
-+
-+			dc_service_memset(&record, 0, sizeof(record));
-+
-+			config = &tbl->sucI2cId + index - 1;
-+
-+			record.sucI2cId.bfHW_Capable =
-+				config->sbfAccess.bfHW_Capable;
-+			record.sucI2cId.bfI2C_LineMux =
-+				config->sbfAccess.bfI2C_LineMux;
-+			record.sucI2cId.bfHW_EngineID =
-+				config->sbfAccess.bfHW_EngineID;
-+
-+			return get_gpio_i2c_info(bp, &record, info);
-+		}
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_get_i2c_info(struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	uint32_t offset;
-+	ATOM_OBJECT *object;
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	ATOM_I2C_RECORD *record;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_I2C_RECORD_TYPE == header->ucRecordType
-+			&& sizeof(ATOM_I2C_RECORD) <= header->ucRecordSize) {
-+			/* get the I2C info */
-+			record = (ATOM_I2C_RECORD *) header;
-+
-+			if (get_gpio_i2c_info(bp, record, info) == BP_RESULT_OK)
-+				return BP_RESULT_OK;
-+		}
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v1(uint8_t *i2c_line,
-+	ATOM_COMMON_TABLE_HEADER *header,
-+	uint8_t *address)
-+{
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	ATOM_VOLTAGE_OBJECT_INFO *info =
-+		(ATOM_VOLTAGE_OBJECT_INFO *) address;
-+
-+	uint8_t *voltage_current_object = (uint8_t *) &info->asVoltageObj[0];
-+
-+	while ((address + le16_to_cpu(header->usStructureSize)) > voltage_current_object) {
-+		ATOM_VOLTAGE_OBJECT *object =
-+			(ATOM_VOLTAGE_OBJECT *) voltage_current_object;
-+
-+		if ((object->ucVoltageType == SET_VOLTAGE_INIT_MODE) &&
-+			(object->ucVoltageType &
-+				VOLTAGE_CONTROLLED_BY_I2C_MASK)) {
-+
-+			*i2c_line = object->asControl.ucVoltageControlI2cLine
-+					^ 0x90;
-+			result = BP_RESULT_OK;
-+			break;
-+		}
-+
-+		voltage_current_object += object->ucSize;
-+	}
-+	return result;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v3(uint8_t *i2c_line,
-+	uint32_t index,
-+	ATOM_COMMON_TABLE_HEADER *header,
-+	uint8_t *address)
-+{
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *info =
-+		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *) address;
-+
-+	uint8_t *voltage_current_object =
-+		(uint8_t *) (&(info->asVoltageObj[0]));
-+
-+	while ((address + le16_to_cpu(header->usStructureSize)) > voltage_current_object) {
-+		ATOM_I2C_VOLTAGE_OBJECT_V3 *object =
-+			(ATOM_I2C_VOLTAGE_OBJECT_V3 *) voltage_current_object;
-+
-+		if (object->sHeader.ucVoltageMode ==
-+			ATOM_INIT_VOLTAGE_REGULATOR) {
-+			if (object->sHeader.ucVoltageType == index) {
-+				*i2c_line = object->ucVoltageControlI2cLine
-+						^ 0x90;
-+				result = BP_RESULT_OK;
-+				break;
-+			}
-+		}
-+
-+		voltage_current_object += le16_to_cpu(object->sHeader.usSize);
-+	}
-+	return result;
-+}
-+
-+enum bp_result dal_bios_parser_get_voltage_ddc_info(struct bios_parser *bp,
-+	uint32_t index,
-+	struct graphics_object_i2c_info *info)
-+{
-+	uint8_t i2c_line = 0;
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	uint8_t *voltage_info_address;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision = {0};
-+
-+	if (!DATA_TABLES(VoltageObjectInfo))
-+		return result;
-+
-+	voltage_info_address = get_image(bp,
-+		DATA_TABLES(VoltageObjectInfo),
-+		sizeof(ATOM_COMMON_TABLE_HEADER));
-+
-+	header = (ATOM_COMMON_TABLE_HEADER *) voltage_info_address;
-+
-+	get_atom_data_table_revision(header, &revision);
-+
-+	switch (revision.major) {
-+	case 1:
-+	case 2:
-+		result = get_voltage_ddc_info_v1(&i2c_line, header,
-+			voltage_info_address);
-+		break;
-+	case 3:
-+		if (revision.minor != 1)
-+			break;
-+		result = get_voltage_ddc_info_v3(&i2c_line, index, header,
-+			voltage_info_address);
-+		break;
-+	}
-+
-+	if (result == BP_RESULT_OK)
-+		result = dal_bios_parser_get_thermal_ddc_info(bp,
-+			i2c_line, info);
-+
-+
-+	return result;
-+}
-+
-+enum bp_result dal_bios_parser_get_thermal_ddc_info(
-+	struct bios_parser *bp,
-+	uint32_t i2c_channel_id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	ATOM_I2C_ID_CONFIG_ACCESS *config;
-+	ATOM_I2C_RECORD record;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	config = (ATOM_I2C_ID_CONFIG_ACCESS *) &i2c_channel_id;
-+
-+	record.sucI2cId.bfHW_Capable = config->sbfAccess.bfHW_Capable;
-+	record.sucI2cId.bfI2C_LineMux = config->sbfAccess.bfI2C_LineMux;
-+	record.sucI2cId.bfHW_EngineID = config->sbfAccess.bfHW_EngineID;
-+
-+	return get_gpio_i2c_info(bp, &record, info);
-+}
-+
-+enum bp_result dal_bios_parser_get_ddc_info_for_i2c_line(struct bios_parser *bp,
-+	uint8_t i2c_line, struct graphics_object_i2c_info *info)
-+{
-+	uint32_t offset;
-+	ATOM_OBJECT *object;
-+	ATOM_OBJECT_TABLE *table;
-+	uint32_t i;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+
-+	offset += bp->object_info_tbl_offset;
-+
-+	table = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
-+
-+	if (!table)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	for (i = 0; i < table->ucNumberOfObjects; i++) {
-+		object = &table->asObjects[i];
-+
-+		if (!object) {
-+			BREAK_TO_DEBUGGER(); /* Invalid object id */
-+			return BP_RESULT_BADINPUT;
-+		}
-+
-+		offset = le16_to_cpu(object->usRecordOffset)
-+				+ bp->object_info_tbl_offset;
-+
-+		for (;;) {
-+			ATOM_COMMON_RECORD_HEADER *header =
-+				GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+			if (!header)
-+				return BP_RESULT_BADBIOSTABLE;
-+
-+			offset += header->ucRecordSize;
-+
-+			if (LAST_RECORD_TYPE == header->ucRecordType ||
-+				!header->ucRecordSize)
-+				break;
-+
-+			if (ATOM_I2C_RECORD_TYPE == header->ucRecordType
-+				&& sizeof(ATOM_I2C_RECORD) <=
-+				header->ucRecordSize) {
-+				ATOM_I2C_RECORD *record =
-+					(ATOM_I2C_RECORD *) header;
-+
-+				if (i2c_line != record->sucI2cId.bfI2C_LineMux)
-+					continue;
-+
-+				/* get the I2C info */
-+				if (get_gpio_i2c_info(bp, record, info) ==
-+					BP_RESULT_OK)
-+					return BP_RESULT_OK;
-+			}
-+		}
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_get_hpd_info(struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct graphics_object_hpd_info *info)
-+{
-+	ATOM_OBJECT *object;
-+	ATOM_HPD_INT_RECORD *record = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	record = get_hpd_record(bp, object);
-+
-+	if (record != NULL) {
-+		info->hpd_int_gpio_uid = record->ucHPDIntGPIOID;
-+		info->hpd_active = record->ucPlugged_PinState;
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+uint32_t dal_bios_parser_get_gpio_record(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct bp_gpio_cntl_info *gpio_record,
-+	uint32_t record_size)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header = NULL;
-+	ATOM_OBJECT_GPIO_CNTL_RECORD *record = NULL;
-+	ATOM_OBJECT *object = get_bios_object(bp, id);
-+	uint32_t offset;
-+	uint32_t pins_number;
-+	uint32_t i;
-+
-+	if (!object)
-+		return 0;
-+
-+	/* Initialise offset */
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		/* Get record header */
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+		if (!header || header->ucRecordType == LAST_RECORD_TYPE ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		/* If this is gpio control record - stop. We found the record */
-+		if (header->ucRecordType == ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE
-+			&& header->ucRecordSize
-+				>= sizeof(ATOM_OBJECT_GPIO_CNTL_RECORD)) {
-+			record = (ATOM_OBJECT_GPIO_CNTL_RECORD *) header;
-+			break;
-+		}
-+
-+		/* Advance to next record */
-+		offset += header->ucRecordSize;
-+	}
-+
-+	/* If we did not find a record - return */
-+	if (!record)
-+		return 0;
-+
-+	/* Extract gpio IDs from bios record (make sure we do not exceed passed
-+	 *  array size) */
-+	pins_number = (record->ucNumberOfPins < record_size ?
-+			record->ucNumberOfPins : record_size);
-+	for (i = 0; i < pins_number; i++) {
-+		uint8_t output_state = ((record->asGpio[i].ucGPIO_PinState
-+			& GPIO_PIN_OUTPUT_STATE_MASK)
-+			>> GPIO_PIN_OUTPUT_STATE_SHIFT);
-+		gpio_record[i].id = record->asGpio[i].ucGPIOID;
-+
-+		switch (output_state) {
-+		case GPIO_PIN_STATE_ACTIVE_LOW:
-+			gpio_record[i].state =
-+				GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW;
-+			break;
-+
-+		case GPIO_PIN_STATE_ACTIVE_HIGH:
-+			gpio_record[i].state =
-+				GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH;
-+			break;
-+
-+		default:
-+			BREAK_TO_DEBUGGER(); /* Invalid Pin Output State */
-+			break;
-+		}
-+	}
-+
-+	return pins_number;
-+}
-+
-+enum bp_result dal_bios_parser_get_device_tag_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object,
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD **record)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	uint32_t offset;
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		offset += header->ucRecordSize;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE !=
-+			header->ucRecordType)
-+			continue;
-+
-+		if (sizeof(ATOM_CONNECTOR_DEVICE_TAG) > header->ucRecordSize)
-+			continue;
-+
-+		*record = (ATOM_CONNECTOR_DEVICE_TAG_RECORD *) header;
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_get_device_tag(
-+	struct bios_parser *bp,
-+	struct graphics_object_id connector_object_id,
-+	uint32_t device_tag_index,
-+	struct connector_device_tag_info *info)
-+{
-+	ATOM_OBJECT *object;
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD *record = NULL;
-+	ATOM_CONNECTOR_DEVICE_TAG *device_tag;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	/* getBiosObject will return MXM object */
-+	object = get_bios_object(bp, connector_object_id);
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	if (dal_bios_parser_get_device_tag_record(bp, object, &record)
-+		!= BP_RESULT_OK)
-+		return BP_RESULT_NORECORD;
-+
-+	if (device_tag_index >= record->ucNumberOfDevice)
-+		return BP_RESULT_NORECORD;
-+
-+	device_tag = &record->asDeviceTag[device_tag_index];
-+
-+	info->acpi_device = le32_to_cpu(device_tag->ulACPIDeviceEnum);
-+	info->dev_id =
-+		device_type_from_device_id(le16_to_cpu(device_tag->usDeviceID));
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_firmware_info_v1_4(
-+	struct bios_parser *bp,
-+	struct firmware_info *info);
-+static enum bp_result get_firmware_info_v2_1(
-+	struct bios_parser *bp,
-+	struct firmware_info *info);
-+static enum bp_result get_firmware_info_v2_2(
-+	struct bios_parser *bp,
-+	struct firmware_info *info);
-+
-+enum bp_result dal_bios_parser_get_firmware_info(
-+	struct bios_parser *bp,
-+	struct firmware_info *info)
-+{
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision;
-+
-+	if (info && DATA_TABLES(FirmwareInfo)) {
-+		header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+			DATA_TABLES(FirmwareInfo));
-+		get_atom_data_table_revision(header, &revision);
-+		switch (revision.major) {
-+		case 1:
-+			switch (revision.minor) {
-+			case 4:
-+				result = get_firmware_info_v1_4(bp, info);
-+				break;
-+			default:
-+				break;
-+			}
-+			break;
-+
-+		case 2:
-+			switch (revision.minor) {
-+			case 1:
-+				result = get_firmware_info_v2_1(bp, info);
-+				break;
-+			case 2:
-+				result = get_firmware_info_v2_2(bp, info);
-+				break;
-+			default:
-+				break;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result get_firmware_info_v1_4(
-+	struct bios_parser *bp,
-+	struct firmware_info *info)
-+{
-+	ATOM_FIRMWARE_INFO_V1_4 *firmware_info =
-+		GET_IMAGE(ATOM_FIRMWARE_INFO_V1_4,
-+			DATA_TABLES(FirmwareInfo));
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!firmware_info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	dc_service_memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. We need to convert from 10KHz units into
-+	 * KHz units */
-+	info->pll_info.crystal_frequency =
-+			le16_to_cpu(firmware_info->usReferenceClock) * 10;
-+	info->pll_info.min_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
-+	info->pll_info.max_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10;
-+	info->pll_info.min_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10;
-+	info->pll_info.max_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10;
-+
-+	if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+		/* Since there is no information on the SS, report conservative
-+		 * value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+
-+	if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+		/* Since there is no information on the SS,report conservative
-+		 * value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v3_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info);
-+
-+static enum bp_result get_firmware_info_v2_1(
-+	struct bios_parser *bp,
-+	struct firmware_info *info)
-+{
-+	ATOM_FIRMWARE_INFO_V2_1 *firmwareInfo =
-+		GET_IMAGE(ATOM_FIRMWARE_INFO_V2_1, DATA_TABLES(FirmwareInfo));
-+	struct spread_spectrum_info internalSS;
-+	uint32_t index;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!firmwareInfo)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	dc_service_memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. We need to convert from 10KHz units into
-+	 * KHz units */
-+	info->pll_info.crystal_frequency =
-+			le16_to_cpu(firmwareInfo->usCoreReferenceClock) * 10;
-+	info->pll_info.min_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmwareInfo->usMinPixelClockPLL_Input) * 10;
-+	info->pll_info.max_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmwareInfo->usMaxPixelClockPLL_Input) * 10;
-+	info->pll_info.min_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmwareInfo->ulMinPixelClockPLL_Output) * 10;
-+	info->pll_info.max_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmwareInfo->ulMaxPixelClockPLL_Output) * 10;
-+	info->default_display_engine_pll_frequency =
-+		le32_to_cpu(firmwareInfo->ulDefaultDispEngineClkFreq) * 10;
-+	info->external_clock_source_frequency_for_dp =
-+		le16_to_cpu(firmwareInfo->usUniphyDPModeExtClkFreq) * 10;
-+	info->min_allowed_bl_level = firmwareInfo->ucMinAllowedBL_Level;
-+
-+	/* There should be only one entry in the SS info table for Memory Clock
-+	 */
-+	index = 0;
-+	if (firmwareInfo->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 *  conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+		ASIC_INTERNAL_MEMORY_SS, index, &internalSS) == BP_RESULT_OK) {
-+		if (internalSS.spread_spectrum_percentage) {
-+			info->feature.memory_clk_ss_percentage =
-+				internalSS.spread_spectrum_percentage;
-+			if (internalSS.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.memory_clk_ss_percentage;
-+				info->feature.memory_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	/* There should be only one entry in the SS info table for Engine Clock
-+	 */
-+	index = 1;
-+	if (firmwareInfo->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 * conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+		ASIC_INTERNAL_ENGINE_SS, index, &internalSS) == BP_RESULT_OK) {
-+		if (internalSS.spread_spectrum_percentage) {
-+			info->feature.engine_clk_ss_percentage =
-+				internalSS.spread_spectrum_percentage;
-+			if (internalSS.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.engine_clk_ss_percentage;
-+				info->feature.engine_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_firmware_info_v2_2(
-+	struct bios_parser *bp,
-+	struct firmware_info *info)
-+{
-+	ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
-+	struct spread_spectrum_info internal_ss;
-+	uint32_t index;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	firmware_info = GET_IMAGE(ATOM_FIRMWARE_INFO_V2_2,
-+		DATA_TABLES(FirmwareInfo));
-+
-+	if (!firmware_info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	dc_service_memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. We need to convert from 10KHz units into
-+	 * KHz units */
-+	info->pll_info.crystal_frequency =
-+			le16_to_cpu(firmware_info->usCoreReferenceClock) * 10;
-+	info->pll_info.min_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
-+	info->pll_info.max_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10;
-+	info->pll_info.min_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10;
-+	info->pll_info.max_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10;
-+	info->default_display_engine_pll_frequency =
-+		le32_to_cpu(firmware_info->ulDefaultDispEngineClkFreq) * 10;
-+	info->external_clock_source_frequency_for_dp =
-+		le16_to_cpu(firmware_info->usUniphyDPModeExtClkFreq) * 10;
-+
-+	/* There should be only one entry in the SS info table for Memory Clock
-+	 */
-+	index = 0;
-+	if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 *  conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+		ASIC_INTERNAL_MEMORY_SS, index, &internal_ss) == BP_RESULT_OK) {
-+		if (internal_ss.spread_spectrum_percentage) {
-+			info->feature.memory_clk_ss_percentage =
-+				internal_ss.spread_spectrum_percentage;
-+			if (internal_ss.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.memory_clk_ss_percentage;
-+				info->feature.memory_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	/* There should be only one entry in the SS info table for Engine Clock
-+	 */
-+	index = 1;
-+	if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 * conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+		ASIC_INTERNAL_ENGINE_SS, index, &internal_ss) == BP_RESULT_OK) {
-+		if (internal_ss.spread_spectrum_percentage) {
-+			info->feature.engine_clk_ss_percentage =
-+				internal_ss.spread_spectrum_percentage;
-+			if (internal_ss.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.engine_clk_ss_percentage;
-+				info->feature.engine_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	/* Remote Display */
-+	info->remote_display_config = firmware_info->ucRemoteDisplayConfig;
-+
-+	/* Is allowed minimum BL level */
-+	info->min_allowed_bl_level = firmware_info->ucMinAllowedBL_Level;
-+	/* Used starting from CI */
-+	info->smu_gpu_pll_output_freq =
-+		(uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v3_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	ATOM_ASIC_INTERNAL_SS_INFO_V3 *ss_table_header_include;
-+	ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl;
-+	uint32_t table_size;
-+	uint32_t i;
-+	uint32_t table_index = 0;
-+
-+	if (!ss_info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	ss_table_header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+	table_size =
-+		(le16_to_cpu(ss_table_header_include->sHeader.usStructureSize)
-+		- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
-+		&ss_table_header_include->asSpreadSpectrum[0];
-+
-+	dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+	for (i = 0; i < table_size; i++) {
-+		if (tbl[i].ucClockIndication != (uint8_t) id)
-+			continue;
-+
-+		if (table_index != index) {
-+			table_index++;
-+			continue;
-+		}
-+		/* VBIOS introduced new defines for Version 3, same values as
-+		 *  before, so now use these new ones for Version 3.
-+		 * Shouldn't affect field VBIOS's V3 as define values are still
-+		 *  same.
-+		 * #define SS_MODE_V3_CENTRE_SPREAD_MASK                0x01
-+		 * #define SS_MODE_V3_EXTERNAL_SS_MASK                  0x02
-+
-+		 * Old VBIOS defines:
-+		 * #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
-+		 * #define ATOM_EXTERNAL_SS_MASK                  0x00000002
-+		 */
-+
-+		if (SS_MODE_V3_EXTERNAL_SS_MASK & tbl[i].ucSpreadSpectrumMode)
-+			ss_info->type.EXTERNAL = true;
-+
-+		if (SS_MODE_V3_CENTRE_SPREAD_MASK & tbl[i].ucSpreadSpectrumMode)
-+			ss_info->type.CENTER_MODE = true;
-+
-+		/* Older VBIOS (in field) always provides SS percentage in 0.01%
-+		 * units set Divider to 100 */
-+		ss_info->spread_percentage_divider = 100;
-+
-+		/* #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 */
-+		if (SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
-+			& tbl[i].ucSpreadSpectrumMode)
-+			ss_info->spread_percentage_divider = 1000;
-+
-+		ss_info->type.STEP_AND_DELAY_INFO = false;
-+		 /* convert [10KHz] into [KHz] */
-+		ss_info->target_clock_range =
-+			le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+		ss_info->spread_spectrum_percentage =
-+			(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+		ss_info->spread_spectrum_range =
-+			(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+
-+		return BP_RESULT_OK;
-+	}
-+	return BP_RESULT_NORECORD;
-+}
-+
-+enum bp_result dal_bios_parser_transmitter_control(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	if (!bp->cmd_tbl.transmitter_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.transmitter_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_encoder_control(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	if (!bp->cmd_tbl.dig_encoder_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_adjust_pixel_clock(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+	if (!bp->cmd_tbl.adjust_display_pll)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.adjust_display_pll(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_set_pixel_clock(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	if (!bp->cmd_tbl.set_pixel_clock)
-+		return BP_RESULT_FAILURE;
-+
-+		return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	if (!bp->cmd_tbl.enable_spread_spectrum_on_ppll)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_spread_spectrum_on_ppll(
-+			bp, bp_params, enable);
-+
-+}
-+
-+enum bp_result dal_bios_parser_program_crtc_timing(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	if (!bp->cmd_tbl.set_crtc_timing)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_program_display_engine_pll(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+
-+	if (!bp->cmd_tbl.program_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.program_clock(bp, bp_params);
-+
-+}
-+
-+enum signal_type dal_bios_parser_dac_load_detect(
-+	struct bios_parser *bp,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type display_signal)
-+{
-+	if (!bp->cmd_tbl.dac_load_detection)
-+		return SIGNAL_TYPE_NONE;
-+
-+	return bp->cmd_tbl.dac_load_detection(bp, encoder, connector,
-+		display_signal);
-+}
-+
-+enum bp_result dal_bios_parser_get_divider_for_target_display_clock(
-+	struct bios_parser *bp,
-+	struct bp_display_clock_parameters *bp_params)
-+{
-+	if (!bp->cmd_tbl.compute_memore_engine_pll)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.compute_memore_engine_pll(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_dvo_encoder_control(
-+	struct bios_parser *bp,
-+	struct bp_dvo_encoder_control *cntl)
-+{
-+	if (!bp->cmd_tbl.dvo_encoder_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.dvo_encoder_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_enable_crtc(
-+	struct bios_parser *bp,
-+	enum controller_id id,
-+	bool enable)
-+{
-+	if (!bp->cmd_tbl.enable_crtc)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_crtc(bp, id, enable);
-+}
-+
-+enum bp_result dal_bios_parser_blank_crtc(
-+	struct bios_parser *bp,
-+	struct bp_blank_crtc_parameters *bp_params,
-+	bool blank)
-+{
-+	if (!bp->cmd_tbl.blank_crtc)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.blank_crtc(bp, bp_params, blank);
-+}
-+
-+enum bp_result dal_bios_parser_crtc_source_select(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	if (!bp->cmd_tbl.select_crtc_source)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_set_overscan(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_overscan_parameters *bp_params)
-+{
-+
-+	if (!bp->cmd_tbl.set_crtc_overscan)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_crtc_overscan(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_enable_memory_requests(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable)
-+{
-+	if (!bp->cmd_tbl.enable_crtc_mem_req)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_crtc_mem_req(bp, controller_id, enable);
-+}
-+
-+enum bp_result dal_bios_parser_external_encoder_control(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl)
-+{
-+	if (!bp->cmd_tbl.external_encoder_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.external_encoder_control(bp, cntl);
-+}
-+
-+enum bp_result dal_bios_parser_enable_disp_power_gating(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	enum bp_pipe_control_action action)
-+{
-+	if (!bp->cmd_tbl.enable_disp_power_gating)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
-+		action);
-+}
-+
-+bool dal_bios_parser_is_device_id_supported(
-+	struct bios_parser *bp,
-+	struct device_id id)
-+{
-+	uint32_t mask = get_support_mask_for_device_id(id);
-+
-+	return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0;
-+}
-+
-+enum bp_result dal_bios_parser_crt_control(
-+	struct bios_parser *bp,
-+	enum engine_id engine_id,
-+	bool enable,
-+	uint32_t pixel_clock)
-+{
-+	uint8_t standard;
-+
-+	if (!bp->cmd_tbl.dac1_encoder_control &&
-+		engine_id == ENGINE_ID_DACA)
-+		return BP_RESULT_FAILURE;
-+	if (!bp->cmd_tbl.dac2_encoder_control &&
-+		engine_id == ENGINE_ID_DACB)
-+		return BP_RESULT_FAILURE;
-+	/* validate params */
-+	switch (engine_id) {
-+	case ENGINE_ID_DACA:
-+	case ENGINE_ID_DACB:
-+		break;
-+	default:
-+		/* unsupported engine */
-+		return BP_RESULT_FAILURE;
-+	}
-+
-+	standard = ATOM_DAC1_PS2; /* == ATOM_DAC2_PS2 */
-+
-+	if (enable) {
-+		if (engine_id == ENGINE_ID_DACA) {
-+			bp->cmd_tbl.dac1_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+			if (bp->cmd_tbl.dac1_output_control != NULL)
-+				bp->cmd_tbl.dac1_output_control(bp, enable);
-+		} else {
-+			bp->cmd_tbl.dac2_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+			if (bp->cmd_tbl.dac2_output_control != NULL)
-+				bp->cmd_tbl.dac2_output_control(bp, enable);
-+		}
-+	} else {
-+		if (engine_id == ENGINE_ID_DACA) {
-+			if (bp->cmd_tbl.dac1_output_control != NULL)
-+				bp->cmd_tbl.dac1_output_control(bp, enable);
-+			bp->cmd_tbl.dac1_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+		} else {
-+			if (bp->cmd_tbl.dac2_output_control != NULL)
-+				bp->cmd_tbl.dac2_output_control(bp, enable);
-+			bp->cmd_tbl.dac2_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+		}
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	uint32_t offset;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_HPD_INT_RECORD_TYPE == header->ucRecordType
-+			&& sizeof(ATOM_HPD_INT_RECORD) <= header->ucRecordSize)
-+			return (ATOM_HPD_INT_RECORD *) header;
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * Get I2C information of input object id
-+ *
-+ * search all records to find the ATOM_I2C_RECORD_TYPE record IR
-+ */
-+static ATOM_I2C_RECORD *get_i2c_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	ATOM_COMMON_RECORD_HEADER *record_header;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER();
-+		/* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		record_header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!record_header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == record_header->ucRecordType ||
-+			0 == record_header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_I2C_RECORD_TYPE == record_header->ucRecordType &&
-+			sizeof(ATOM_I2C_RECORD) <=
-+			record_header->ucRecordSize) {
-+			return (ATOM_I2C_RECORD *)record_header;
-+		}
-+
-+		offset += record_header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+
-+static enum bp_result get_ss_info_from_ss_info_table(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info);
-+static enum bp_result get_ss_info_from_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info);
-+/**
-+ * dal_bios_parser_get_spread_spectrum_info
-+ * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
-+ * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
-+ * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1,
-+ * there is only one entry for each signal /ss id.  However, there is
-+ * no planning of supporting multiple spread Sprectum entry for EverGreen
-+ * @param [in] this
-+ * @param [in] signal, ASSignalType to be converted to info index
-+ * @param [in] index, number of entries that match the converted info index
-+ * @param [out] ss_info, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+enum bp_result dal_bios_parser_get_spread_spectrum_info(
-+	struct bios_parser *bp,
-+	enum as_signal_type signal,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	uint32_t clk_id_ss = 0;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision tbl_revision;
-+
-+	if (!ss_info) /* check for bad input */
-+		return BP_RESULT_BADINPUT;
-+	/* signal translation */
-+	clk_id_ss = signal_to_ss_id(signal);
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		if (!index)
-+			return get_ss_info_from_ss_info_table(bp, clk_id_ss,
-+				ss_info);
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+	get_atom_data_table_revision(header, &tbl_revision);
-+
-+	switch (tbl_revision.major) {
-+	case 2:
-+		switch (tbl_revision.minor) {
-+		case 1:
-+			/* there can not be more then one entry for Internal
-+			 * SS Info table version 2.1 */
-+			if (!index)
-+				return get_ss_info_from_tbl(bp, clk_id_ss,
-+						ss_info);
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+
-+	case 3:
-+		switch (tbl_revision.minor) {
-+		case 1:
-+			return get_ss_info_v3_1(bp, clk_id_ss, index, ss_info);
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+		/* there can not be more then one entry for SS Info table */
-+	return result;
-+}
-+
-+static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *info);
-+
-+/**
-+ * get_ss_info_from_table
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info table from the VBIOS
-+ * There can not be more than 1 entry for  ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info.
-+ *
-+ * @param this
-+ * @param id, spread sprectrum info index
-+ * @param pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	if (!ss_info) /* check for bad input, if ss_info is not NULL */
-+		return BP_RESULT_BADINPUT;
-+	/* for SS_Info table only support DP and LVDS */
-+	if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS)
-+		return get_ss_info_from_ss_info_table(bp, id, ss_info);
-+	else
-+		return get_ss_info_from_internal_ss_info_tbl_V2_1(bp, id,
-+			ss_info);
-+}
-+
-+/**
-+ * get_ss_info_from_internal_ss_info_tbl_V2_1
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info table Ver 2.1
-+ * from the VBIOS
-+ * There will not be multiple entry for Ver 2.1
-+ *
-+ * @param id, spread sprectrum info index
-+ * @param pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *info)
-+{
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	ATOM_ASIC_INTERNAL_SS_INFO_V2 *header;
-+	ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl;
-+	uint32_t tbl_size, i;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return result;
-+
-+	header = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+
-+	dc_service_memset(info, 0, sizeof(struct spread_spectrum_info));
-+
-+	tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
-+		- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
-+				&(header->asSpreadSpectrum[0]);
-+	for (i = 0; i < tbl_size; i++) {
-+		result = BP_RESULT_NORECORD;
-+
-+		if (tbl[i].ucClockIndication != (uint8_t)id)
-+			continue;
-+
-+		if (ATOM_EXTERNAL_SS_MASK
-+			& tbl[i].ucSpreadSpectrumMode) {
-+			info->type.EXTERNAL = true;
-+		}
-+		if (ATOM_SS_CENTRE_SPREAD_MODE_MASK
-+			& tbl[i].ucSpreadSpectrumMode) {
-+			info->type.CENTER_MODE = true;
-+		}
-+		info->type.STEP_AND_DELAY_INFO = false;
-+		/* convert [10KHz] into [KHz] */
-+		info->target_clock_range =
-+			le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+		info->spread_spectrum_percentage =
-+			(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+		info->spread_spectrum_range =
-+			(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+		result = BP_RESULT_OK;
-+		break;
-+	}
-+
-+	return result;
-+
-+}
-+
-+/**
-+ * get_ss_info_from_ss_info_table
-+ * Get spread sprectrum information from the SS_Info table from the VBIOS
-+ * if the pointer to info is NULL, indicate the caller what to know the number
-+ * of entries that matches the id
-+ * for, the SS_Info table, there should not be more than 1 entry match.
-+ *
-+ * @param [in] id, spread sprectrum id
-+ * @param [out] pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_ss_info_table(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	ATOM_SPREAD_SPECTRUM_INFO *tbl;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	uint32_t table_size;
-+	uint32_t i;
-+	uint32_t id_local = SS_ID_UNKNOWN;
-+	struct atom_data_revision revision;
-+
-+	/* exist of the SS_Info table */
-+	/* check for bad input, pSSinfo can not be NULL */
-+	if (!DATA_TABLES(SS_Info) || !ss_info)
-+		return result;
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(SS_Info));
-+	get_atom_data_table_revision(header, &revision);
-+
-+	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info));
-+
-+	if (1 != revision.major || 2 > revision.minor)
-+		return result;
-+
-+	/* have to convert from Internal_SS format to SS_Info format */
-+	switch (id) {
-+	case ASIC_INTERNAL_SS_ON_DP:
-+		id_local = SS_ID_DP1;
-+		break;
-+	case ASIC_INTERNAL_SS_ON_LVDS:
-+	{
-+		struct embedded_panel_info panel_info;
-+
-+		if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
-+			== BP_RESULT_OK)
-+			id_local = panel_info.ss_id;
-+		break;
-+	}
-+	default:
-+		break;
-+	}
-+
-+	if (id_local == SS_ID_UNKNOWN)
-+		return result;
-+
-+	table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
-+		sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+			sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+
-+	for (i = 0; i < table_size; i++) {
-+		if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
-+			continue;
-+
-+		dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+		if (ATOM_EXTERNAL_SS_MASK &
-+			tbl->asSS_Info[i].ucSpreadSpectrumType)
-+			ss_info->type.EXTERNAL = true;
-+
-+		if (ATOM_SS_CENTRE_SPREAD_MODE_MASK &
-+			tbl->asSS_Info[i].ucSpreadSpectrumType)
-+			ss_info->type.CENTER_MODE = true;
-+
-+		ss_info->type.STEP_AND_DELAY_INFO = true;
-+		ss_info->spread_spectrum_percentage =
-+			(uint32_t)le16_to_cpu(tbl->asSS_Info[i].usSpreadSpectrumPercentage);
-+		ss_info->step_and_delay_info.step = tbl->asSS_Info[i].ucSS_Step;
-+		ss_info->step_and_delay_info.delay =
-+			tbl->asSS_Info[i].ucSS_Delay;
-+		ss_info->step_and_delay_info.recommended_ref_div =
-+			tbl->asSS_Info[i].ucRecommendedRef_Div;
-+		ss_info->spread_spectrum_range =
-+			(uint32_t)tbl->asSS_Info[i].ucSS_Range * 10000;
-+
-+		/* there will be only one entry for each display type in SS_info
-+		 * table */
-+		result = BP_RESULT_OK;
-+		break;
-+	}
-+
-+	return result;
-+}
-+static enum bp_result get_embedded_panel_info_v1_2(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info);
-+static enum bp_result get_embedded_panel_info_v1_3(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info);
-+
-+enum bp_result dal_bios_parser_get_embedded_panel_info(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info)
-+{
-+	ATOM_COMMON_TABLE_HEADER *hdr;
-+
-+	if (!DATA_TABLES(LCD_Info))
-+		return BP_RESULT_FAILURE;
-+
-+	hdr = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(LCD_Info));
-+
-+	if (!hdr)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	switch (hdr->ucTableFormatRevision) {
-+	case 1:
-+		switch (hdr->ucTableContentRevision) {
-+		case 0:
-+		case 1:
-+		case 2:
-+			return get_embedded_panel_info_v1_2(bp, info);
-+		case 3:
-+			return get_embedded_panel_info_v1_3(bp, info);
-+		default:
-+			break;
-+		}
-+	default:
-+			break;
-+	}
-+
-+	return BP_RESULT_FAILURE;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v1_2(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info)
-+{
-+	ATOM_LVDS_INFO_V12 *lvds;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(LVDS_Info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	lvds =
-+		GET_IMAGE(ATOM_LVDS_INFO_V12, DATA_TABLES(LVDS_Info));
-+
-+	if (!lvds)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != lvds->sHeader.ucTableFormatRevision
-+		|| 2 > lvds->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+	/* We need to convert from 10KHz units into KHz units*/
-+	info->lcd_timing.pixel_clk =
-+		le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+	/* usHActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.horizontal_addressable =
-+		le16_to_cpu(lvds->sLCDTiming.usHActive);
-+	/* usHBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now.  May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.horizontal_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+	/* usVActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.vertical_addressable =
-+			le16_to_cpu(lvds->sLCDTiming.usVActive);
-+	/* usVBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now. May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.vertical_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time);
-+	info->lcd_timing.horizontal_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncOffset);
-+	info->lcd_timing.horizontal_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncWidth);
-+	info->lcd_timing.vertical_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncOffset);
-+	info->lcd_timing.vertical_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncWidth);
-+	info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder;
-+	info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder;
-+	info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff;
-+	info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity;
-+	info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity;
-+	info->lcd_timing.misc_info.VERTICAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff;
-+	info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2;
-+	info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2;
-+	info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync;
-+	info->lcd_timing.misc_info.INTERLACE =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
-+	info->lcd_timing.misc_info.DOUBLE_CLOCK =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock;
-+	info->ss_id = lvds->ucSS_Id;
-+
-+	{
-+		uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
-+		/* Get minimum supported refresh rate*/
-+		if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
-+			info->supported_rr.REFRESH_RATE_30HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr)
-+			info->supported_rr.REFRESH_RATE_40HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr)
-+			info->supported_rr.REFRESH_RATE_48HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr)
-+			info->supported_rr.REFRESH_RATE_50HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr)
-+			info->supported_rr.REFRESH_RATE_60HZ = 1;
-+	}
-+
-+	/*Drr panel support can be reported by VBIOS*/
-+	if (LCDPANEL_CAP_DRR_SUPPORTED
-+		& lvds->ucLCDPanel_SpecialHandlingCap)
-+		info->drr_enabled = 1;
-+
-+	if (ATOM_PANEL_MISC_DUAL & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.DOUBLE_CLOCK = true;
-+
-+	if (ATOM_PANEL_MISC_888RGB & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.RGB888 = true;
-+
-+	info->lcd_timing.misc_info.GREY_LEVEL =
-+		(uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL &
-+		lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT;
-+
-+	if (ATOM_PANEL_MISC_SPATIAL & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.SPATIAL = true;
-+
-+	if (ATOM_PANEL_MISC_TEMPORAL & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.TEMPORAL = true;
-+
-+	if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.API_ENABLED = true;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v1_3(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info)
-+{
-+	ATOM_LCD_INFO_V13 *lvds;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(LCD_Info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	lvds = GET_IMAGE(ATOM_LCD_INFO_V13, DATA_TABLES(LCD_Info));
-+
-+	if (!lvds)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (!((1 == lvds->sHeader.ucTableFormatRevision)
-+		&& (3 <= lvds->sHeader.ucTableContentRevision)))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+	/* We need to convert from 10KHz units into KHz units */
-+	info->lcd_timing.pixel_clk =
-+		le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+	/* usHActive does not include borders, according to VBIOS team */
-+	info->lcd_timing.horizontal_addressable =
-+		le16_to_cpu(lvds->sLCDTiming.usHActive);
-+	/* usHBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now.  May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.horizontal_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+	/* usVActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.vertical_addressable =
-+		le16_to_cpu(lvds->sLCDTiming.usVActive);
-+	/* usVBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now. May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.vertical_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time);
-+	info->lcd_timing.horizontal_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncOffset);
-+	info->lcd_timing.horizontal_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncWidth);
-+	info->lcd_timing.vertical_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncOffset);
-+	info->lcd_timing.vertical_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncWidth);
-+	info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder;
-+	info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder;
-+	info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff;
-+	info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity;
-+	info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity;
-+	info->lcd_timing.misc_info.VERTICAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff;
-+	info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2;
-+	info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2;
-+	info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync;
-+	info->lcd_timing.misc_info.INTERLACE =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
-+	info->lcd_timing.misc_info.DOUBLE_CLOCK =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock;
-+	info->ss_id = lvds->ucSS_Id;
-+
-+	/* Drr panel support can be reported by VBIOS*/
-+	if (LCDPANEL_CAP_V13_DRR_SUPPORTED
-+		& lvds->ucLCDPanel_SpecialHandlingCap)
-+		info->drr_enabled = 1;
-+
-+	/* Get supported refresh rate*/
-+	if (info->drr_enabled == 1) {
-+		uint8_t min_rr =
-+			lvds->sRefreshRateSupport.ucMinRefreshRateForDRR;
-+		uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate;
-+
-+		if (min_rr != 0) {
-+			if (SUPPORTED_LCD_REFRESHRATE_30Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_30HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_40Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_40HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_48Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_48HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_50Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_50HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_60Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_60HZ = 1;
-+		} else {
-+			if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
-+				info->supported_rr.REFRESH_RATE_30HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr)
-+				info->supported_rr.REFRESH_RATE_40HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr)
-+				info->supported_rr.REFRESH_RATE_48HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr)
-+				info->supported_rr.REFRESH_RATE_50HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr)
-+				info->supported_rr.REFRESH_RATE_60HZ = 1;
-+		}
-+	}
-+
-+	if (ATOM_PANEL_MISC_V13_DUAL & lvds->ucLCD_Misc)
-+		info->lcd_timing.misc_info.DOUBLE_CLOCK = true;
-+
-+	if (ATOM_PANEL_MISC_V13_8BIT_PER_COLOR & lvds->ucLCD_Misc)
-+		info->lcd_timing.misc_info.RGB888 = true;
-+
-+	info->lcd_timing.misc_info.GREY_LEVEL =
-+		(uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL &
-+		lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/**
-+ * dal_bios_parser_get_encoder_cap_info
-+ *
-+ * @brief
-+ *  Get encoder capability information of input object id
-+ *
-+ * @param object_id, Object id
-+ * @param object_id, encoder cap information structure
-+ *
-+ * @return Bios parser result code
-+ *
-+ */
-+enum bp_result dal_bios_parser_get_encoder_cap_info(
-+	struct bios_parser *bp,
-+	struct graphics_object_id object_id,
-+	struct bp_encoder_cap_info *info)
-+{
-+	ATOM_OBJECT *object;
-+	ATOM_ENCODER_CAP_RECORD *record = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	record = get_encoder_cap_record(bp, object);
-+	if (!record)
-+		return BP_RESULT_NORECORD;
-+
-+	info->DP_HBR2_CAP = record->usHBR2Cap;
-+	info->DP_HBR2_EN = record->usHBR2En;
-+	return BP_RESULT_OK;
-+}
-+
-+/**
-+ * get_encoder_cap_record
-+ *
-+ * @brief
-+ *  Get encoder cap record for the object
-+ *
-+ * @param object, ATOM object
-+ *
-+ * @return atom encoder cap record
-+ *
-+ * @note
-+ *  search all records to find the ATOM_ENCODER_CAP_RECORD record
-+ */
-+static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	uint32_t offset;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		offset += header->ucRecordSize;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType)
-+			continue;
-+
-+		if (sizeof(ATOM_ENCODER_CAP_RECORD) <= header->ucRecordSize)
-+			return (ATOM_ENCODER_CAP_RECORD *)header;
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * dal_bios_parser_get_din_connector_info
-+ * @brief
-+ *   Get GPIO record for the DIN connector, this GPIO tells whether there is a
-+ *    CV dumb dongle
-+ *   attached to the DIN connector to perform load detection for the the
-+ *    appropriate signal
-+ *
-+ * @param id - DIN connector object id
-+ * @param info             - GPIO record infor
-+ * @return Bios parser result code
-+ */
-+enum bp_result dal_bios_parser_get_din_connector_info(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct din_connector_info *info)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *record = NULL;
-+	ATOM_OBJECT *object;
-+	uint32_t offset;
-+	enum bp_result result = BP_RESULT_NORECORD;
-+
-+	/* no output buffer provided */
-+	if (!info) {
-+		BREAK_TO_DEBUGGER(); /* Invalid output buffer */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	object = get_bios_object(bp, id);
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */;
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+				+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header) {
-+			result = BP_RESULT_BADBIOSTABLE;
-+			break;
-+		}
-+
-+		offset += header->ucRecordSize;
-+
-+		/* get out of the loop if no more records */
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE !=
-+			header->ucRecordType)
-+			continue;
-+
-+		if (sizeof(ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD)
-+			> header->ucRecordSize)
-+			continue;
-+
-+		record = (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *)header;
-+		result = BP_RESULT_OK;
-+		break;
-+	}
-+
-+	/* return if the record not found */
-+	if (result != BP_RESULT_OK)
-+		return result;
-+
-+	info->gpio_id = record->ucGPIOID;
-+	info->gpio_tv_active_state = (record->ucTVActiveState != 0);
-+
-+	return result;
-+}
-+
-+static uint32_t get_ss_entry_number(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+static uint32_t get_ss_entry_number_from_ss_info_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+
-+/**
-+ * BiosParserObject::GetNumberofSpreadSpectrumEntry
-+ * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from
-+ * the VBIOS that match the SSid (to be converted from signal)
-+ *
-+ * @param[in] signal, ASSignalType to be converted to SSid
-+ * @return number of SS Entry that match the signal
-+ */
-+uint32_t dal_bios_parser_get_ss_entry_number(
-+	struct bios_parser *bp,
-+	enum as_signal_type signal)
-+{
-+	uint32_t ss_id = 0;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision;
-+
-+	ss_id = signal_to_ss_id(signal);
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return get_ss_entry_number_from_ss_info_tbl(bp, ss_id);
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+	get_atom_data_table_revision(header, &revision);
-+
-+	switch (revision.major) {
-+	case 2:
-+		switch (revision.minor) {
-+		case 1:
-+			return get_ss_entry_number(bp, ss_id);
-+		default:
-+			break;
-+		}
-+		break;
-+	case 3:
-+		switch (revision.minor) {
-+		case 1:
-+			return
-+			get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+				bp, ss_id);
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/**
-+ * get_ss_entry_number_from_ss_info_tbl
-+ * Get Number of spread spectrum entry from the SS_Info table from the VBIOS.
-+ *
-+ * @note There can only be one entry for each id for SS_Info Table
-+ *
-+ * @param [in] id, spread spectrum id
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_ss_info_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id)
-+{
-+	ATOM_SPREAD_SPECTRUM_INFO *tbl;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	uint32_t table_size;
-+	uint32_t i;
-+	uint32_t number = 0;
-+	uint32_t id_local = SS_ID_UNKNOWN;
-+	struct atom_data_revision revision;
-+
-+	/* SS_Info table exist */
-+	if (!DATA_TABLES(SS_Info))
-+		return number;
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+		DATA_TABLES(SS_Info));
-+	get_atom_data_table_revision(header, &revision);
-+
-+	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO,
-+		DATA_TABLES(SS_Info));
-+
-+	if (1 != revision.major || 2 > revision.minor)
-+		return number;
-+
-+	/* have to convert from Internal_SS format to SS_Info format */
-+	switch (id) {
-+	case ASIC_INTERNAL_SS_ON_DP:
-+		id_local = SS_ID_DP1;
-+		break;
-+	case ASIC_INTERNAL_SS_ON_LVDS: {
-+		struct embedded_panel_info panel_info;
-+
-+		if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
-+			== BP_RESULT_OK)
-+			id_local = panel_info.ss_id;
-+		break;
-+	}
-+	default:
-+		break;
-+	}
-+
-+	if (id_local == SS_ID_UNKNOWN)
-+		return number;
-+
-+	table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
-+		sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+			sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+
-+	for (i = 0; i < table_size; i++)
-+		if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) {
-+			number = 1;
-+			break;
-+		}
-+
-+	return number;
-+}
-+
-+
-+/**
-+ * get_ss_entry_number
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info table from the VBIOS
-+ * There can not be more than 1 entry for  ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info.
-+ *
-+ * @param id, spread sprectrum info index
-+ * @return Bios parser result code
-+ */
-+static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id)
-+{
-+	if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS)
-+		return get_ss_entry_number_from_ss_info_tbl(bp, id);
-+
-+	return get_ss_entry_number_from_internal_ss_info_tbl_v2_1(bp, id);
-+}
-+
-+/**
-+ * get_ss_entry_number_from_internal_ss_info_tbl_v2_1
-+ * Get NUmber of spread sprectrum entry from the ASIC_InternalSS_Info table
-+ * Ver 2.1 from the VBIOS
-+ * There will not be multiple entry for Ver 2.1
-+ *
-+ * @param id, spread sprectrum info index
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
-+	struct bios_parser *bp,
-+	uint32_t id)
-+{
-+	ATOM_ASIC_INTERNAL_SS_INFO_V2 *header_include;
-+	ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl;
-+	uint32_t size;
-+	uint32_t i;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return 0;
-+
-+	header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+
-+	size = (le16_to_cpu(header_include->sHeader.usStructureSize)
-+		- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
-+		&header_include->asSpreadSpectrum[0];
-+	for (i = 0; i < size; i++)
-+		if (tbl[i].ucClockIndication == (uint8_t)id)
-+			return 1;
-+
-+	return 0;
-+}
-+/**
-+ * get_ss_entry_number_from_internal_ss_info_table_V3_1
-+ * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of
-+ * the VBIOS that matches id
-+ *
-+ * @param[in]  id, spread sprectrum id
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+	struct bios_parser *bp,
-+	uint32_t id)
-+{
-+	uint32_t number = 0;
-+	ATOM_ASIC_INTERNAL_SS_INFO_V3 *header_include;
-+	ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl;
-+	uint32_t size;
-+	uint32_t i;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return number;
-+
-+	header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+	size = (le16_to_cpu(header_include->sHeader.usStructureSize) -
-+		sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+			sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
-+		&header_include->asSpreadSpectrum[0];
-+
-+	for (i = 0; i < size; i++)
-+		if (tbl[i].ucClockIndication == (uint8_t)id)
-+			number++;
-+
-+	return number;
-+}
-+
-+static ATOM_FAKE_EDID_PATCH_RECORD *get_faked_edid_record(
-+	struct bios_parser *bp)
-+{
-+	uint32_t size;
-+	uint8_t *record;
-+	ATOM_LVDS_INFO_V12 *info;
-+
-+	if (!DATA_TABLES(LVDS_Info))
-+		return NULL;
-+
-+	info = GET_IMAGE(ATOM_LVDS_INFO_V12, DATA_TABLES(LVDS_Info));
-+
-+	if (!info)
-+		return NULL;
-+
-+	if (1 != info->sHeader.ucTableFormatRevision
-+		|| 2 > info->sHeader.ucTableContentRevision)
-+		return NULL;
-+
-+	if (!le16_to_cpu(info->usExtInfoTableOffset))
-+		return NULL;
-+
-+	record = GET_IMAGE(uint8_t, DATA_TABLES(LVDS_Info)
-+		+ le16_to_cpu(info->usExtInfoTableOffset));
-+
-+	if (!record)
-+		return NULL;
-+
-+	for (;;) {
-+		if (ATOM_RECORD_END_TYPE == *record)
-+			return NULL;
-+
-+		if (LCD_FAKE_EDID_PATCH_RECORD_TYPE == *record)
-+			break;
-+
-+		size = get_record_size(record);
-+
-+		if (!size)
-+			return NULL;
-+
-+		record += size;
-+	}
-+
-+	return (ATOM_FAKE_EDID_PATCH_RECORD *)record;
-+}
-+
-+enum bp_result dal_bios_parser_get_faked_edid_len(
-+	struct bios_parser *bp,
-+	uint32_t *len)
-+{
-+	ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
-+
-+	if (!edid_record)
-+		return BP_RESULT_NORECORD;
-+
-+	*len = get_edid_size(edid_record);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+enum bp_result dal_bios_parser_get_faked_edid_buf(
-+	struct bios_parser *bp,
-+	uint8_t *buff,
-+	uint32_t len)
-+{
-+	ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
-+	uint32_t edid_size;
-+
-+	if (!edid_record)
-+		return BP_RESULT_NORECORD;
-+
-+	edid_size = get_edid_size(edid_record);
-+
-+	if (len < edid_size)
-+		return BP_RESULT_BADINPUT; /* buffer not big enough to fill */
-+
-+	dc_service_memmove(buff, &edid_record->ucFakeEDIDString, edid_size);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/**
-+ * dal_bios_parser_get_gpio_pin_info
-+ * Get GpioPin information of input gpio id
-+ *
-+ * @param gpio_id, GPIO ID
-+ * @param info, GpioPin information structure
-+ * @return Bios parser result code
-+ * @note
-+ *  to get the GPIO PIN INFO, we need:
-+ *  1. get the GPIO_ID from other object table, see GetHPDInfo()
-+ *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA
-+ *  offset/mask
-+ */
-+enum bp_result dal_bios_parser_get_gpio_pin_info(
-+	struct bios_parser *bp,
-+	uint32_t gpio_id,
-+	struct gpio_pin_info *info)
-+{
-+	ATOM_GPIO_PIN_LUT *header;
-+	uint32_t count = 0;
-+	uint32_t i = 0;
-+
-+	if (!DATA_TABLES(GPIO_Pin_LUT))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	header = GET_IMAGE(ATOM_GPIO_PIN_LUT, DATA_TABLES(GPIO_Pin_LUT));
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_PIN_LUT)
-+		> le16_to_cpu(header->sHeader.usStructureSize))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != header->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	count = (le16_to_cpu(header->sHeader.usStructureSize)
-+		- sizeof(ATOM_COMMON_TABLE_HEADER))
-+		/ sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
-+	for (i = 0; i < count; ++i) {
-+		if (header->asGPIO_Pin[i].ucGPIO_ID != gpio_id)
-+			continue;
-+
-+		info->offset =
-+			(uint32_t) le16_to_cpu(header->asGPIO_Pin[i].usGpioPin_AIndex);
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask = (uint32_t) (1 <<
-+			header->asGPIO_Pin[i].ucGpioPinBitShift);
-+		info->mask_y = info->mask + 2;
-+		info->mask_en = info->mask + 1;
-+		info->mask_mask = info->mask - 1;
-+
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+/**
-+ * BiosParserObject::EnumEmbeddedPanelPatchMode
-+ * Get embedded panel patch mode
-+ *
-+ * @param index, mode index
-+ * @param info, embedded panel patch mode structure
-+ * @return Bios parser result code
-+ */
-+enum bp_result dal_bios_parser_enum_embedded_panel_patch_mode(
-+	struct bios_parser *bp,
-+	uint32_t index,
-+	struct embedded_panel_patch_mode *mode)
-+{
-+	uint32_t record_size;
-+	uint32_t record_index;
-+	uint8_t *record;
-+	ATOM_LVDS_INFO_V12 *info;
-+	ATOM_PATCH_RECORD_MODE *mode_record;
-+	ATOM_MASTER_LIST_OF_DATA_TABLES *list_of_tables;
-+
-+	if (!mode)
-+		return BP_RESULT_BADINPUT;
-+
-+	list_of_tables = &bp->master_data_tbl->ListOfDataTables;
-+	if (!list_of_tables->LVDS_Info)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	info = GET_IMAGE(ATOM_LVDS_INFO_V12, list_of_tables->LVDS_Info);
-+
-+	if (!info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != info->sHeader.ucTableFormatRevision
-+		|| 2 > info->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	if (!le16_to_cpu(info->usExtInfoTableOffset))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	record = GET_IMAGE(uint8_t, list_of_tables->LVDS_Info +
-+		le16_to_cpu(info->usExtInfoTableOffset));
-+
-+	if (!record)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	for (record_index = 0;;) {
-+		if (ATOM_RECORD_END_TYPE == *record)
-+			return BP_RESULT_NORECORD;
-+
-+		if (LCD_MODE_PATCH_RECORD_MODE_TYPE == *record) {
-+			if (record_index == index)
-+				break;
-+			record_index++;
-+		}
-+
-+		record_size = get_record_size(record);
-+
-+		if (!record_size)
-+			return BP_RESULT_NORECORD;
-+
-+		record += record_size;
-+	}
-+
-+	mode_record = (ATOM_PATCH_RECORD_MODE *) record;
-+
-+	mode->width = le16_to_cpu(mode_record->usHDisp);
-+	mode->height = le16_to_cpu(mode_record->usVDisp);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+	ATOM_I2C_RECORD *record,
-+	struct graphics_object_i2c_info *info)
-+{
-+	ATOM_GPIO_I2C_INFO *header;
-+	uint32_t count = 0;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	/* get the GPIO_I2C info */
-+	if (!DATA_TABLES(GPIO_I2C_Info))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	header = GET_IMAGE(ATOM_GPIO_I2C_INFO, DATA_TABLES(GPIO_I2C_Info));
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_I2C_ASSIGMENT)
-+		> le16_to_cpu(header->sHeader.usStructureSize))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != header->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	/* get data count */
-+	count = (le16_to_cpu(header->sHeader.usStructureSize)
-+		- sizeof(ATOM_COMMON_TABLE_HEADER))
-+		/ sizeof(ATOM_GPIO_I2C_ASSIGMENT);
-+	if (count < record->sucI2cId.bfI2C_LineMux)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	/* get the GPIO_I2C_INFO */
-+	info->i2c_hw_assist = record->sucI2cId.bfHW_Capable;
-+	info->i2c_line = record->sucI2cId.bfI2C_LineMux;
-+	info->i2c_engine_id = record->sucI2cId.bfHW_EngineID;
-+	info->i2c_slave_address = record->ucI2CAddr;
-+
-+	info->gpio_info.clk_mask_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkMaskRegisterIndex);
-+	info->gpio_info.clk_en_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkEnRegisterIndex);
-+	info->gpio_info.clk_y_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkY_RegisterIndex);
-+	info->gpio_info.clk_a_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkA_RegisterIndex);
-+	info->gpio_info.data_mask_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataMaskRegisterIndex);
-+	info->gpio_info.data_en_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataEnRegisterIndex);
-+	info->gpio_info.data_y_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataY_RegisterIndex);
-+	info->gpio_info.data_a_register_index =
-+		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataA_RegisterIndex);
-+
-+	info->gpio_info.clk_mask_shift =
-+		header->asGPIO_Info[info->i2c_line].ucClkMaskShift;
-+	info->gpio_info.clk_en_shift =
-+		header->asGPIO_Info[info->i2c_line].ucClkEnShift;
-+	info->gpio_info.clk_y_shift =
-+		header->asGPIO_Info[info->i2c_line].ucClkY_Shift;
-+	info->gpio_info.clk_a_shift =
-+		header->asGPIO_Info[info->i2c_line].ucClkA_Shift;
-+	info->gpio_info.data_mask_shift =
-+		header->asGPIO_Info[info->i2c_line].ucDataMaskShift;
-+	info->gpio_info.data_en_shift =
-+		header->asGPIO_Info[info->i2c_line].ucDataEnShift;
-+	info->gpio_info.data_y_shift =
-+		header->asGPIO_Info[info->i2c_line].ucDataY_Shift;
-+	info->gpio_info.data_a_shift =
-+		header->asGPIO_Info[info->i2c_line].ucDataA_Shift;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
-+	struct graphics_object_id id)
-+{
-+	uint32_t offset;
-+	ATOM_OBJECT_TABLE *tbl;
-+	uint32_t i;
-+
-+	switch (id.type) {
-+	case OBJECT_TYPE_ENCODER:
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+		break;
-+
-+	case OBJECT_TYPE_CONNECTOR:
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+		break;
-+
-+	case OBJECT_TYPE_ROUTER:
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_1->usRouterObjectTableOffset);
-+		break;
-+
-+	case OBJECT_TYPE_GENERIC:
-+		if (bp->object_info_tbl.revision.minor < 3)
-+			return NULL;
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_3->usMiscObjectTableOffset);
-+		break;
-+
-+	default:
-+		return NULL;
-+	}
-+
-+	offset += bp->object_info_tbl_offset;
-+
-+	tbl = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
-+	if (!tbl)
-+		return NULL;
-+
-+	for (i = 0; i < tbl->ucNumberOfObjects; i++)
-+		if (dal_graphics_object_id_is_equal(id,
-+			object_id_from_bios_object_id(
-+				le16_to_cpu(tbl->asObjects[i].usObjectID))))
-+			return &tbl->asObjects[i];
-+
-+	return NULL;
-+}
-+
-+static uint32_t get_dest_obj_list(struct bios_parser *bp,
-+	ATOM_OBJECT *object, uint16_t **id_list)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+				+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	offset += sizeof(uint16_t) * (*number);
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if ((!number) || (!*number))
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	*id_list = (uint16_t *)get_image(bp, offset,
-+		*number * sizeof(uint16_t));
-+
-+	if (!*id_list)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
-+	uint16_t **id_list)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	*id_list = (uint16_t *)get_image(bp, offset,
-+		*number * sizeof(uint16_t));
-+
-+	if (!*id_list)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+static uint32_t get_dst_number_from_object(struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid encoder object id*/
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	offset += sizeof(uint16_t) * (*number);
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+
-+	if (!number)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+static uint8_t *get_image(struct bios_parser *bp,
-+	uint32_t offset,
-+	uint32_t size)
-+{
-+	if (bp->bios && offset + size < bp->bios_size)
-+		return bp->bios + offset;
-+	else
-+		return NULL;
-+}
-+
-+static uint32_t get_record_size(uint8_t *record)
-+{
-+	switch (*record) {
-+	case LCD_MODE_PATCH_RECORD_MODE_TYPE:
-+		return sizeof(ATOM_PATCH_RECORD_MODE);
-+
-+	case LCD_RTS_RECORD_TYPE:
-+		return sizeof(ATOM_LCD_RTS_RECORD);
-+
-+	case LCD_CAP_RECORD_TYPE:
-+		return sizeof(ATOM_LCD_MODE_CONTROL_CAP);
-+
-+	case LCD_FAKE_EDID_PATCH_RECORD_TYPE: {
-+		ATOM_FAKE_EDID_PATCH_RECORD *fake_record =
-+			(ATOM_FAKE_EDID_PATCH_RECORD *) record;
-+		uint32_t edid_size = get_edid_size(fake_record);
-+
-+		return sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + edid_size
-+			- sizeof(fake_record->ucFakeEDIDString);
-+	}
-+
-+	case LCD_PANEL_RESOLUTION_RECORD_TYPE:
-+		return sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
-+
-+	default:
-+		return 0;
-+	}
-+}
-+
-+static uint32_t get_edid_size(const ATOM_FAKE_EDID_PATCH_RECORD *edid)
-+{
-+	uint32_t length = edid->ucFakeEDIDLength;
-+
-+	if (length < 128)
-+		length = length * 128;
-+
-+	return length;
-+}
-+
-+static struct graphics_object_id object_id_from_bios_object_id(
-+	uint32_t bios_object_id)
-+{
-+	enum object_type type;
-+	enum object_enum_id enum_id;
-+	struct graphics_object_id go_id = { 0 };
-+
-+	type = object_type_from_bios_object_id(bios_object_id);
-+
-+	if (OBJECT_TYPE_UNKNOWN == type)
-+		return go_id;
-+
-+	enum_id = enum_id_from_bios_object_id(bios_object_id);
-+
-+	if (ENUM_ID_UNKNOWN == enum_id)
-+		return go_id;
-+
-+	go_id = dal_graphics_object_id_init(
-+		id_from_bios_object_id(type, bios_object_id), enum_id, type);
-+
-+	return go_id;
-+}
-+
-+static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
-+		>> OBJECT_TYPE_SHIFT;
-+	enum object_type object_type;
-+
-+	switch (bios_object_type) {
-+	case GRAPH_OBJECT_TYPE_GPU:
-+		object_type = OBJECT_TYPE_GPU;
-+		break;
-+	case GRAPH_OBJECT_TYPE_ENCODER:
-+		object_type = OBJECT_TYPE_ENCODER;
-+		break;
-+	case GRAPH_OBJECT_TYPE_CONNECTOR:
-+		object_type = OBJECT_TYPE_CONNECTOR;
-+		break;
-+	case GRAPH_OBJECT_TYPE_ROUTER:
-+		object_type = OBJECT_TYPE_ROUTER;
-+		break;
-+	case GRAPH_OBJECT_TYPE_GENERIC:
-+		object_type = OBJECT_TYPE_GENERIC;
-+		break;
-+	default:
-+		object_type = OBJECT_TYPE_UNKNOWN;
-+		break;
-+	}
-+
-+	return object_type;
-+}
-+
-+static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_enum_id =
-+		(bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
-+	enum object_enum_id id;
-+
-+	switch (bios_enum_id) {
-+	case GRAPH_OBJECT_ENUM_ID1:
-+		id = ENUM_ID_1;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID2:
-+		id = ENUM_ID_2;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID3:
-+		id = ENUM_ID_3;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID4:
-+		id = ENUM_ID_4;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID5:
-+		id = ENUM_ID_5;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID6:
-+		id = ENUM_ID_6;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID7:
-+		id = ENUM_ID_7;
-+		break;
-+	default:
-+		id = ENUM_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static uint32_t id_from_bios_object_id(enum object_type type,
-+	uint32_t bios_object_id)
-+{
-+	switch (type) {
-+	case OBJECT_TYPE_GPU:
-+		return gpu_id_from_bios_object_id(bios_object_id);
-+	case OBJECT_TYPE_ENCODER:
-+		return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);
-+	case OBJECT_TYPE_CONNECTOR:
-+		return (uint32_t)connector_id_from_bios_object_id(
-+			bios_object_id);
-+	case OBJECT_TYPE_GENERIC:
-+		return generic_id_from_bios_object_id(bios_object_id);
-+	default:
-+		return 0;
-+	}
-+}
-+
-+static enum connector_id connector_id_from_bios_object_id(
-+	uint32_t bios_object_id)
-+{
-+	uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id);
-+
-+	enum connector_id id;
-+
-+	switch (bios_connector_id) {
-+	case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:
-+		id = CONNECTOR_ID_SINGLE_LINK_DVII;
-+		break;
-+	case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:
-+		id = CONNECTOR_ID_DUAL_LINK_DVII;
-+		break;
-+	case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:
-+		id = CONNECTOR_ID_SINGLE_LINK_DVID;
-+		break;
-+	case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:
-+		id = CONNECTOR_ID_DUAL_LINK_DVID;
-+		break;
-+	case CONNECTOR_OBJECT_ID_VGA:
-+		id = CONNECTOR_ID_VGA;
-+		break;
-+	case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:
-+		id = CONNECTOR_ID_HDMI_TYPE_A;
-+		break;
-+	case CONNECTOR_OBJECT_ID_LVDS:
-+		id = CONNECTOR_ID_LVDS;
-+		break;
-+	case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR:
-+		id = CONNECTOR_ID_PCIE;
-+		break;
-+	case CONNECTOR_OBJECT_ID_HARDCODE_DVI:
-+		id = CONNECTOR_ID_HARDCODE_DVI;
-+		break;
-+	case CONNECTOR_OBJECT_ID_DISPLAYPORT:
-+		id = CONNECTOR_ID_DISPLAY_PORT;
-+		break;
-+	case CONNECTOR_OBJECT_ID_eDP:
-+		id = CONNECTOR_ID_EDP;
-+		break;
-+	case CONNECTOR_OBJECT_ID_MXM:
-+		id = CONNECTOR_ID_MXM;
-+		break;
-+	default:
-+		id = CONNECTOR_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);
-+	enum encoder_id id;
-+
-+	switch (bios_encoder_id) {
-+	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
-+		id = ENCODER_ID_INTERNAL_LVDS;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
-+		id = ENCODER_ID_INTERNAL_TMDS1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
-+		id = ENCODER_ID_INTERNAL_TMDS2;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
-+		id = ENCODER_ID_INTERNAL_DAC1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
-+		id = ENCODER_ID_INTERNAL_DAC2;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_SDVOA:
-+		id = ENCODER_ID_INTERNAL_SDVOA;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_SDVOB:
-+		id = ENCODER_ID_INTERNAL_SDVOB;
-+		break;
-+	case ENCODER_OBJECT_ID_SI170B:
-+		id = ENCODER_ID_EXTERNAL_SI170B;
-+		break;
-+	case ENCODER_OBJECT_ID_CH7303:
-+		id = ENCODER_ID_EXTERNAL_CH7303;
-+		break;
-+	case ENCODER_OBJECT_ID_CH7301:
-+		id = ENCODER_ID_EXTERNAL_CH7301;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
-+		id = ENCODER_ID_INTERNAL_DVO1;
-+		break;
-+	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
-+		id = ENCODER_ID_EXTERNAL_SDVOA;
-+		break;
-+	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
-+		id = ENCODER_ID_EXTERNAL_SDVOB;
-+		break;
-+	case ENCODER_OBJECT_ID_TITFP513:
-+		id = ENCODER_ID_EXTERNAL_TITFP513;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-+		id = ENCODER_ID_INTERNAL_LVTM1;
-+		break;
-+	case ENCODER_OBJECT_ID_VT1623:
-+		id = ENCODER_ID_EXTERNAL_VT1623;
-+		break;
-+	case ENCODER_OBJECT_ID_HDMI_SI1930:
-+		id = ENCODER_ID_EXTERNAL_SI1930;
-+		break;
-+	case ENCODER_OBJECT_ID_HDMI_INTERNAL:
-+		id = ENCODER_ID_INTERNAL_HDMI;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_DVO1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
-+		break;
-+	case ENCODER_OBJECT_ID_SI178:
-+		id = ENCODER_ID_EXTERNAL_SI178;
-+		break;
-+	case ENCODER_OBJECT_ID_MVPU_FPGA:
-+		id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DDI:
-+		id = ENCODER_ID_INTERNAL_DDI;
-+		break;
-+	case ENCODER_OBJECT_ID_VT1625:
-+		id = ENCODER_ID_EXTERNAL_VT1625;
-+		break;
-+	case ENCODER_OBJECT_ID_HDMI_SI1932:
-+		id = ENCODER_ID_EXTERNAL_SI1932;
-+		break;
-+	case ENCODER_OBJECT_ID_DP_AN9801:
-+		id = ENCODER_ID_EXTERNAL_AN9801;
-+		break;
-+	case ENCODER_OBJECT_ID_DP_DP501:
-+		id = ENCODER_ID_EXTERNAL_DP501;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-+		id = ENCODER_ID_INTERNAL_UNIPHY;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-+		id = ENCODER_ID_INTERNAL_UNIPHY1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-+		id = ENCODER_ID_INTERNAL_UNIPHY2;
-+		break;
-+	case ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO:
-+		id = ENCODER_ID_EXTERNAL_GENERIC_DVO;
-+		break;
-+	case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
-+		id = ENCODER_ID_EXTERNAL_NUTMEG;
-+		break;
-+	case ENCODER_OBJECT_ID_TRAVIS:
-+		id = ENCODER_ID_EXTERNAL_TRAVIS;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
-+		id = ENCODER_ID_INTERNAL_UNIPHY3;
-+		break;
-+	default:
-+		id = ENCODER_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	return (bios_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
-+}
-+
-+enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id);
-+
-+	enum generic_id id;
-+
-+	switch (bios_generic_id) {
-+	case GENERIC_OBJECT_ID_MXM_OPM:
-+		id = GENERIC_ID_MXM_OPM;
-+		break;
-+	case GENERIC_OBJECT_ID_GLSYNC:
-+		id = GENERIC_ID_GLSYNC;
-+		break;
-+	case GENERIC_OBJECT_ID_STEREO_PIN:
-+		id = GENERIC_ID_STEREO;
-+		break;
-+	default:
-+		id = GENERIC_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static struct device_id device_type_from_device_id(uint16_t device_id)
-+{
-+
-+	struct device_id result_device_id;
-+
-+	switch (device_id) {
-+	case ATOM_DEVICE_LCD1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_LCD;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DEVICE_LCD2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_LCD;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DEVICE_CRT1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_CRT;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DEVICE_CRT2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_CRT;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DEVICE_DFP1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DEVICE_DFP2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DEVICE_DFP3_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 3;
-+		break;
-+
-+	case ATOM_DEVICE_DFP4_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 4;
-+		break;
-+
-+	case ATOM_DEVICE_DFP5_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 5;
-+		break;
-+
-+	case ATOM_DEVICE_DFP6_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 6;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Invalid device Id */
-+		result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
-+		result_device_id.enum_id = 0;
-+	}
-+	return result_device_id;
-+}
-+
-+static void get_atom_data_table_revision(
-+	ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
-+	struct atom_data_revision *tbl_revision)
-+{
-+	if (!tbl_revision)
-+		return;
-+
-+	/* initialize the revision to 0 which is invalid revision */
-+	tbl_revision->major = 0;
-+	tbl_revision->minor = 0;
-+
-+	if (!atom_data_tbl)
-+		return;
-+
-+	tbl_revision->major =
-+		(uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl);
-+	tbl_revision->minor =
-+		(uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl);
-+}
-+
-+static uint32_t signal_to_ss_id(enum as_signal_type signal)
-+{
-+	uint32_t clk_id_ss = 0;
-+
-+	switch (signal) {
-+	case AS_SIGNAL_TYPE_DVI:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_TMDS;
-+		break;
-+	case AS_SIGNAL_TYPE_HDMI:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_HDMI;
-+		break;
-+	case AS_SIGNAL_TYPE_LVDS:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_LVDS;
-+		break;
-+	case AS_SIGNAL_TYPE_DISPLAY_PORT:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_DP;
-+		break;
-+	case AS_SIGNAL_TYPE_GPU_PLL:
-+		clk_id_ss = ASIC_INTERNAL_GPUPLL_SS;
-+		break;
-+	default:
-+		break;
-+	}
-+	return clk_id_ss;
-+}
-+
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id)
-+{
-+	enum dal_device_type device_type = device_id.device_type;
-+	uint32_t enum_id = device_id.enum_id;
-+
-+	switch (device_type) {
-+	case DEVICE_TYPE_LCD:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_LCD1_SUPPORT;
-+		case 2:
-+			return ATOM_DEVICE_LCD2_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CRT:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_CRT1_SUPPORT;
-+		case 2:
-+			return ATOM_DEVICE_CRT2_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_DFP:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_DFP1_SUPPORT;
-+		case 2:
-+			return ATOM_DEVICE_DFP2_SUPPORT;
-+		case 3:
-+			return ATOM_DEVICE_DFP3_SUPPORT;
-+		case 4:
-+			return ATOM_DEVICE_DFP4_SUPPORT;
-+		case 5:
-+			return ATOM_DEVICE_DFP5_SUPPORT;
-+		case 6:
-+			return ATOM_DEVICE_DFP6_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CV:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_CV_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_TV:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_TV1_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	};
-+
-+	/* Unidentified device ID, return empty support mask. */
-+	return 0;
-+}
-+
-+/**
-+*  HwContext interface for writing MM registers
-+*/
-+
-+static bool i2c_read(
-+	struct bios_parser *bp,
-+	struct graphics_object_i2c_info *i2c_info,
-+	uint8_t *buffer,
-+	uint32_t length)
-+{
-+	struct ddc *ddc;
-+	uint8_t offset[2] = { 0, 0 };
-+	bool result = false;
-+	struct i2c_command cmd;
-+
-+	ddc = dal_adapter_service_obtain_ddc_from_i2c_info(bp->as, i2c_info);
-+
-+	if (!ddc)
-+		return result;
-+
-+	/*Using SW engine */
-+	cmd.engine = I2C_COMMAND_ENGINE_SW;
-+	cmd.speed = dal_adapter_service_get_sw_i2c_speed(bp->as);
-+
-+	{
-+		struct i2c_payload payloads[] = {
-+			{
-+				.address = i2c_info->i2c_slave_address >> 1,
-+				.data = offset,
-+				.length = sizeof(offset),
-+				.write = true
-+			},
-+			{
-+				.address = i2c_info->i2c_slave_address >> 1,
-+				.data = buffer,
-+				.length = length,
-+				.write = false
-+			}
-+		};
-+
-+		cmd.payloads = payloads;
-+		cmd.number_of_payloads = ARRAY_SIZE(payloads);
-+
-+		result = dal_i2caux_submit_i2c_command(
-+			dal_adapter_service_get_i2caux(bp->as),
-+			ddc,
-+			&cmd);
-+	}
-+
-+	dal_adapter_service_release_ddc(bp->as, ddc);
-+
-+	return result;
-+}
-+
-+/**
-+ * Read external display connection info table through i2c.
-+ * validate the GUID and checksum.
-+ *
-+ * @return enum bp_result whether all data was sucessfully read
-+ */
-+static enum bp_result get_ext_display_connection_info(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *opm_object,
-+	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *ext_display_connection_info_tbl)
-+{
-+	bool config_tbl_present = false;
-+	ATOM_I2C_RECORD *i2c_record = NULL;
-+	uint32_t i = 0;
-+
-+	if (opm_object == NULL)
-+		return BP_RESULT_BADINPUT;
-+
-+	i2c_record = get_i2c_record(bp, opm_object);
-+
-+	if (i2c_record != NULL) {
-+		ATOM_GPIO_I2C_INFO *gpio_i2c_header;
-+		struct graphics_object_i2c_info i2c_info;
-+
-+		gpio_i2c_header = GET_IMAGE(ATOM_GPIO_I2C_INFO,
-+			bp->master_data_tbl->ListOfDataTables.GPIO_I2C_Info);
-+
-+		if (NULL == gpio_i2c_header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (get_gpio_i2c_info(bp, i2c_record, &i2c_info) !=
-+			BP_RESULT_OK)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (i2c_read(
-+			bp,
-+			&i2c_info,
-+			(uint8_t *)ext_display_connection_info_tbl,
-+			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
-+			config_tbl_present = true;
-+		}
-+	}
-+
-+	/* Validate GUID */
-+	if (config_tbl_present)
-+		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; i++) {
-+			if (ext_display_connection_info_tbl->ucGuid[i]
-+				!= ext_display_connection_guid[i]) {
-+				config_tbl_present = false;
-+				break;
-+			}
-+		}
-+
-+	/* Validate checksum */
-+	if (config_tbl_present) {
-+		uint8_t check_sum = 0;
-+		uint8_t *buf =
-+			(uint8_t *)ext_display_connection_info_tbl;
-+
-+		for (i = 0; i < sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
-+			i++) {
-+			check_sum += buf[i];
-+		}
-+
-+		if (check_sum != 0)
-+			config_tbl_present = false;
-+	}
-+
-+	if (config_tbl_present)
-+		return BP_RESULT_OK;
-+	else
-+		return BP_RESULT_FAILURE;
-+}
-+
-+/*
-+ * Gets the first device ID in the same group as the given ID for enumerating.
-+ * For instance, if any DFP device ID is passed, returns the device ID for DFP1.
-+ *
-+ * The first device ID in the same group as the passed device ID, or 0 if no
-+ * matching device group found.
-+ */
-+static uint32_t enum_first_device_id(uint32_t dev_id)
-+{
-+	/* Return the first in the group that this ID belongs to. */
-+	if (dev_id & ATOM_DEVICE_CRT_SUPPORT)
-+		return ATOM_DEVICE_CRT1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_DFP_SUPPORT)
-+		return ATOM_DEVICE_DFP1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_LCD_SUPPORT)
-+		return ATOM_DEVICE_LCD1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_TV_SUPPORT)
-+		return ATOM_DEVICE_TV1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_CV_SUPPORT)
-+		return ATOM_DEVICE_CV_SUPPORT;
-+
-+	/* No group found for this device ID. */
-+
-+	dal_error("%s: incorrect input %d\n", __func__, dev_id);
-+	/* No matching support flag for given device ID */
-+	return 0;
-+}
-+
-+/*
-+ * Gets the next device ID in the group for a given device ID.
-+ *
-+ * The current device ID being enumerated on.
-+ *
-+ * The next device ID in the group, or 0 if no device exists.
-+ */
-+static uint32_t enum_next_dev_id(uint32_t dev_id)
-+{
-+	/* Get next device ID in the group. */
-+	switch (dev_id) {
-+	case ATOM_DEVICE_CRT1_SUPPORT:
-+		return ATOM_DEVICE_CRT2_SUPPORT;
-+	case ATOM_DEVICE_LCD1_SUPPORT:
-+		return ATOM_DEVICE_LCD2_SUPPORT;
-+	case ATOM_DEVICE_DFP1_SUPPORT:
-+		return ATOM_DEVICE_DFP2_SUPPORT;
-+	case ATOM_DEVICE_DFP2_SUPPORT:
-+		return ATOM_DEVICE_DFP3_SUPPORT;
-+	case ATOM_DEVICE_DFP3_SUPPORT:
-+		return ATOM_DEVICE_DFP4_SUPPORT;
-+	case ATOM_DEVICE_DFP4_SUPPORT:
-+		return ATOM_DEVICE_DFP5_SUPPORT;
-+	case ATOM_DEVICE_DFP5_SUPPORT:
-+		return ATOM_DEVICE_DFP6_SUPPORT;
-+	}
-+
-+	/* Done enumerating through devices. */
-+	return 0;
-+}
-+
-+/*
-+ * Returns the new device tag record for patched BIOS object.
-+ *
-+ * [IN] pExtDisplayPath - External display path to copy device tag from.
-+ * [IN] deviceSupport - Bit vector for device ID support flags.
-+ * [OUT] pDeviceTag - Device tag structure to fill with patched data.
-+ *
-+ * True if a compatible device ID was found, false otherwise.
-+ */
-+static bool get_patched_device_tag(
-+	struct bios_parser *bp,
-+	EXT_DISPLAY_PATH *ext_display_path,
-+	uint32_t device_support,
-+	ATOM_CONNECTOR_DEVICE_TAG *device_tag)
-+{
-+	uint32_t dev_id;
-+	/* Use fallback behaviour if not supported. */
-+	if (!bp->remap_device_tags) {
-+		device_tag->ulACPIDeviceEnum =
-+			cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+		device_tag->usDeviceID =
-+			cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceTag));
-+		return true;
-+	}
-+
-+	/* Find the first unused in the same group. */
-+	dev_id = enum_first_device_id(le16_to_cpu(ext_display_path->usDeviceTag));
-+	while (dev_id != 0) {
-+		/* Assign this device ID if supported. */
-+		if ((device_support & dev_id) != 0) {
-+			device_tag->ulACPIDeviceEnum =
-+				cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+			device_tag->usDeviceID = cpu_to_le16((USHORT) dev_id);
-+			return true;
-+		}
-+
-+		dev_id = enum_next_dev_id(dev_id);
-+	}
-+
-+	/* No compatible device ID found. */
-+	return false;
-+}
-+
-+/*
-+ * Adds a device tag to a BIOS object's device tag record if there is
-+ * matching device ID supported.
-+ *
-+ * pObject - Pointer to the BIOS object to add the device tag to.
-+ * pExtDisplayPath - Display path to retrieve base device ID from.
-+ * pDeviceSupport - Pointer to bit vector for supported device IDs.
-+ */
-+static void add_device_tag_from_ext_display_path(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object,
-+	EXT_DISPLAY_PATH *ext_display_path,
-+	uint32_t *device_support)
-+{
-+	/* Get device tag record for object. */
-+	ATOM_CONNECTOR_DEVICE_TAG *device_tag = NULL;
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD *device_tag_record = NULL;
-+	enum bp_result result =
-+		dal_bios_parser_get_device_tag_record(
-+			bp, object, &device_tag_record);
-+
-+	if ((le16_to_cpu(ext_display_path->usDeviceTag) != CONNECTOR_OBJECT_ID_NONE)
-+		&& (result == BP_RESULT_OK)) {
-+		uint8_t index;
-+
-+		if ((device_tag_record->ucNumberOfDevice == 1) &&
-+			(le16_to_cpu(device_tag_record->asDeviceTag[0].usDeviceID) == 0)) {
-+			/*Workaround bug in current VBIOS releases where
-+			 * ucNumberOfDevice = 1 but there is no actual device
-+			 * tag data. This w/a is temporary until the updated
-+			 * VBIOS is distributed. */
-+			device_tag_record->ucNumberOfDevice =
-+				device_tag_record->ucNumberOfDevice - 1;
-+		}
-+
-+		/* Attempt to find a matching device ID. */
-+		index = device_tag_record->ucNumberOfDevice;
-+		device_tag = &device_tag_record->asDeviceTag[index];
-+		if (get_patched_device_tag(
-+			bp,
-+			ext_display_path,
-+			*device_support,
-+			device_tag)) {
-+			/* Update cached device support to remove assigned ID.
-+			 */
-+			*device_support &= ~le16_to_cpu(device_tag->usDeviceID);
-+			device_tag_record->ucNumberOfDevice++;
-+		}
-+	}
-+}
-+
-+/*
-+ * Read out a single EXT_DISPLAY_PATH from the external display connection info
-+ * table. The specific entry in the table is determined by the enum_id passed
-+ * in.
-+ *
-+ * EXT_DISPLAY_PATH describing a single Configuration table entry
-+ */
-+
-+#define INVALID_CONNECTOR 0xffff
-+
-+static EXT_DISPLAY_PATH *get_ext_display_path_entry(
-+	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *config_table,
-+	uint32_t bios_object_id)
-+{
-+	EXT_DISPLAY_PATH *ext_display_path;
-+	uint32_t ext_display_path_index =
-+		((bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT) - 1;
-+
-+	if (ext_display_path_index >= MAX_NUMBER_OF_EXT_DISPLAY_PATH)
-+		return NULL;
-+
-+	ext_display_path = &config_table->sPath[ext_display_path_index];
-+
-+	if (le16_to_cpu(ext_display_path->usDeviceConnector) == INVALID_CONNECTOR)
-+		ext_display_path->usDeviceConnector = cpu_to_le16(0);
-+
-+	return ext_display_path;
-+}
-+
-+/*
-+ * Get AUX/DDC information of input object id
-+ *
-+ * search all records to find the ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE record
-+ * IR
-+ */
-+static ATOM_CONNECTOR_AUXDDC_LUT_RECORD *get_ext_connector_aux_ddc_lut_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	ATOM_COMMON_RECORD_HEADER *header;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER();
-+		/* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			0 == header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE ==
-+			header->ucRecordType &&
-+			sizeof(ATOM_CONNECTOR_AUXDDC_LUT_RECORD) <=
-+			header->ucRecordSize)
-+			return (ATOM_CONNECTOR_AUXDDC_LUT_RECORD *)(header);
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Get AUX/DDC information of input object id
-+ *
-+ * search all records to find the ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE record
-+ * IR
-+ */
-+static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	ATOM_COMMON_RECORD_HEADER *header;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER();
-+		/* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			0 == header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE ==
-+			header->ucRecordType &&
-+			sizeof(ATOM_CONNECTOR_HPDPIN_LUT_RECORD) <=
-+			header->ucRecordSize)
-+			return (ATOM_CONNECTOR_HPDPIN_LUT_RECORD *)header;
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Check whether we need to patch the VBIOS connector info table with
-+ * data from an external display connection info table.  This is
-+ * necessary to support MXM boards with an OPM (output personality
-+ * module).  With these designs, the VBIOS connector info table
-+ * specifies an MXM_CONNECTOR with a unique ID.  The driver retrieves
-+ * the external connection info table through i2c and then looks up the
-+ * connector ID to find the real connector type (e.g. DFP1).
-+ *
-+ */
-+static enum bp_result patch_bios_image_from_ext_display_connection_info(
-+	struct bios_parser *bp)
-+{
-+	ATOM_OBJECT_TABLE *connector_tbl;
-+	uint32_t connector_tbl_offset;
-+	struct graphics_object_id object_id;
-+	ATOM_OBJECT *object;
-+	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ext_display_connection_info_tbl;
-+	EXT_DISPLAY_PATH *ext_display_path;
-+	ATOM_CONNECTOR_AUXDDC_LUT_RECORD *aux_ddc_lut_record = NULL;
-+	ATOM_I2C_RECORD *i2c_record = NULL;
-+	ATOM_CONNECTOR_HPDPIN_LUT_RECORD *hpd_pin_lut_record = NULL;
-+	ATOM_HPD_INT_RECORD *hpd_record = NULL;
-+	ATOM_OBJECT_TABLE *encoder_table;
-+	uint32_t encoder_table_offset;
-+	ATOM_OBJECT *opm_object = NULL;
-+	uint32_t i = 0;
-+	struct graphics_object_id opm_object_id =
-+		dal_graphics_object_id_init(
-+			GENERIC_ID_MXM_OPM,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_GENERIC);
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD *dev_tag_record;
-+	uint32_t cached_device_support =
-+		le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport);
-+
-+	uint32_t dst_number;
-+	uint16_t *dst_object_id_list;
-+
-+	opm_object = get_bios_object(bp, opm_object_id);
-+	if (!opm_object)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	dc_service_memset(&ext_display_connection_info_tbl, 0,
-+		sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
-+
-+	connector_tbl_offset = bp->object_info_tbl_offset
-+		+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+	/* Read Connector info table from EEPROM through i2c */
-+	if (get_ext_display_connection_info(
-+		bp,
-+		opm_object,
-+		&ext_display_connection_info_tbl) != BP_RESULT_OK) {
-+		if (bp->headless_no_opm) {
-+			/* Failed to read OPM, remove all non-CF connectors. */
-+			for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
-+				object = &connector_tbl->asObjects[i];
-+				object_id = object_id_from_bios_object_id(
-+					le16_to_cpu(object->usObjectID));
-+				if (OBJECT_TYPE_CONNECTOR == object_id.type)
-+					object->usObjectID = cpu_to_le16(0);
-+			}
-+
-+			return BP_RESULT_OK;
-+		}
-+
-+		dal_logger_write(bp->ctx->logger,
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: Failed to read Connection Info Table", __func__);
-+		return BP_RESULT_UNSUPPORTED;
-+	}
-+
-+	/* Get pointer to AUX/DDC and HPD LUTs */
-+	aux_ddc_lut_record =
-+		get_ext_connector_aux_ddc_lut_record(bp, opm_object);
-+	hpd_pin_lut_record =
-+		get_ext_connector_hpd_pin_lut_record(bp, opm_object);
-+
-+	if ((aux_ddc_lut_record == NULL) || (hpd_pin_lut_record == NULL))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	/* Cache support bits for currently unmapped device types. */
-+	if (bp->remap_device_tags) {
-+		for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
-+			uint32_t j;
-+			/* Remove support for all non-MXM connectors. */
-+			object = &connector_tbl->asObjects[i];
-+			object_id = object_id_from_bios_object_id(
-+				le16_to_cpu(object->usObjectID));
-+			if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+				(CONNECTOR_ID_MXM == object_id.id))
-+				continue;
-+
-+			/* Remove support for all device tags. */
-+			if (dal_bios_parser_get_device_tag_record(
-+				bp, object, &dev_tag_record) != BP_RESULT_OK)
-+				continue;
-+
-+			for (j = 0; j < dev_tag_record->ucNumberOfDevice; ++j) {
-+				ATOM_CONNECTOR_DEVICE_TAG *device_tag =
-+					&dev_tag_record->asDeviceTag[j];
-+				cached_device_support &=
-+					~le16_to_cpu(device_tag->usDeviceID);
-+			}
-+		}
-+	}
-+
-+	/* Find all MXM connector objects and patch them with connector info
-+	 * from the external display connection info table. */
-+	for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+		uint32_t j;
-+
-+		object = &connector_tbl->asObjects[i];
-+		object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
-+		if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+			(CONNECTOR_ID_MXM != object_id.id))
-+			continue;
-+
-+		/* Get the correct connection info table entry based on the enum
-+		 * id. */
-+		ext_display_path = get_ext_display_path_entry(
-+			&ext_display_connection_info_tbl,
-+			le16_to_cpu(object->usObjectID));
-+		if (!ext_display_path)
-+			return BP_RESULT_FAILURE;
-+
-+		/* Patch device connector ID */
-+		object->usObjectID =
-+			cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceConnector));
-+
-+		/* Patch device tag, ulACPIDeviceEnum. */
-+		add_device_tag_from_ext_display_path(
-+			bp,
-+			object,
-+			ext_display_path,
-+			&cached_device_support);
-+
-+		/* Patch HPD info */
-+		if (ext_display_path->ucExtHPDPINLutIndex <
-+			MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES) {
-+			hpd_record = get_hpd_record(bp, object);
-+			if (hpd_record) {
-+				uint8_t index =
-+					ext_display_path->ucExtHPDPINLutIndex;
-+				hpd_record->ucHPDIntGPIOID =
-+					hpd_pin_lut_record->ucHPDPINMap[index];
-+			} else {
-+				BREAK_TO_DEBUGGER();
-+				/* Invalid hpd record */
-+				return BP_RESULT_FAILURE;
-+			}
-+		}
-+
-+		/* Patch I2C/AUX info */
-+		if (ext_display_path->ucExtHPDPINLutIndex <
-+			MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES) {
-+			i2c_record = get_i2c_record(bp, object);
-+			if (i2c_record) {
-+				uint8_t index =
-+					ext_display_path->ucExtAUXDDCLutIndex;
-+				i2c_record->sucI2cId =
-+					aux_ddc_lut_record->ucAUXDDCMap[index];
-+			} else {
-+				BREAK_TO_DEBUGGER();
-+				/* Invalid I2C record */
-+				return BP_RESULT_FAILURE;
-+			}
-+		}
-+
-+		/* Merge with other MXM connectors that map to the same physical
-+		 * connector. */
-+		for (j = i + 1;
-+			j < connector_tbl->ucNumberOfObjects; j++) {
-+			ATOM_OBJECT *next_object;
-+			struct graphics_object_id next_object_id;
-+			EXT_DISPLAY_PATH *next_ext_display_path;
-+
-+			next_object = &connector_tbl->asObjects[j];
-+			next_object_id = object_id_from_bios_object_id(
-+				le16_to_cpu(next_object->usObjectID));
-+
-+			if ((OBJECT_TYPE_CONNECTOR != next_object_id.type) &&
-+				(CONNECTOR_ID_MXM == next_object_id.id))
-+				continue;
-+
-+			next_ext_display_path = get_ext_display_path_entry(
-+				&ext_display_connection_info_tbl,
-+				le16_to_cpu(next_object->usObjectID));
-+
-+			if (next_ext_display_path == NULL)
-+				return BP_RESULT_FAILURE;
-+
-+			/* Merge if using same connector. */
-+			if ((le16_to_cpu(next_ext_display_path->usDeviceConnector) ==
-+				le16_to_cpu(ext_display_path->usDeviceConnector)) &&
-+				(le16_to_cpu(ext_display_path->usDeviceConnector) != 0)) {
-+				/* Clear duplicate connector from table. */
-+				next_object->usObjectID = cpu_to_le16(0);
-+				add_device_tag_from_ext_display_path(
-+					bp,
-+					object,
-+					ext_display_path,
-+					&cached_device_support);
-+			}
-+		}
-+	}
-+
-+	/* Find all encoders which have an MXM object as their destination.
-+	 *  Replace the MXM object with the real connector Id from the external
-+	 *  display connection info table */
-+
-+	encoder_table_offset = bp->object_info_tbl_offset
-+		+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+	encoder_table = GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
-+
-+	for (i = 0; i < encoder_table->ucNumberOfObjects; i++) {
-+		uint32_t j;
-+
-+		object = &encoder_table->asObjects[i];
-+
-+		dst_number = get_dest_obj_list(bp, object, &dst_object_id_list);
-+
-+		for (j = 0; j < dst_number; j++) {
-+			object_id = object_id_from_bios_object_id(
-+				dst_object_id_list[j]);
-+
-+			if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+				(CONNECTOR_ID_MXM != object_id.id))
-+				continue;
-+
-+			/* Get the correct connection info table entry based on
-+			 * the enum id. */
-+			ext_display_path =
-+				get_ext_display_path_entry(
-+					&ext_display_connection_info_tbl,
-+					dst_object_id_list[j]);
-+
-+			if (ext_display_path == NULL)
-+				return BP_RESULT_FAILURE;
-+
-+			dst_object_id_list[j] =
-+				le16_to_cpu(ext_display_path->usDeviceConnector);
-+		}
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/*
-+ * Check whether we need to patch the VBIOS connector info table with
-+ * data from an external display connection info table.  This is
-+ * necessary to support MXM boards with an OPM (output personality
-+ * module).  With these designs, the VBIOS connector info table
-+ * specifies an MXM_CONNECTOR with a unique ID.  The driver retrieves
-+ * the external connection info table through i2c and then looks up the
-+ * connector ID to find the real connector type (e.g. DFP1).
-+ *
-+ */
-+
-+static void process_ext_display_connection_info(struct bios_parser *bp)
-+{
-+	ATOM_OBJECT_TABLE *connector_tbl;
-+	uint32_t connector_tbl_offset;
-+	struct graphics_object_id object_id;
-+	ATOM_OBJECT *object;
-+	bool mxm_connector_found = false;
-+	bool null_entry_found = false;
-+	uint32_t i = 0;
-+
-+	connector_tbl_offset = bp->object_info_tbl_offset +
-+		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+	/* Look for MXM connectors to determine whether we need patch the VBIOS
-+	 * connector info table. Look for null entries to determine whether we
-+	 * need to compact connector table. */
-+	for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+		object = &connector_tbl->asObjects[i];
-+		object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
-+
-+		if ((OBJECT_TYPE_CONNECTOR == object_id.type) &&
-+			(CONNECTOR_ID_MXM == object_id.id)) {
-+			/* Once we found MXM connector - we can break */
-+			mxm_connector_found = true;
-+			break;
-+		} else if (OBJECT_TYPE_CONNECTOR != object_id.type) {
-+			/* We need to continue looping - to check if MXM
-+			 * connector present */
-+			null_entry_found = true;
-+		}
-+	}
-+
-+	/* Patch BIOS image */
-+	if (mxm_connector_found || null_entry_found) {
-+		uint32_t connectors_num = 0;
-+		uint8_t *original_bios;
-+		/* Step 1: Replace bios image with the new copy which will be
-+		 * patched */
-+		bp->bios_local_image = dc_service_alloc(bp->ctx, bp->bios_size);
-+		if (bp->bios_local_image == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			/* Failed to alloc bp->bios_local_image */
-+			return;
-+		}
-+
-+		dc_service_memmove(bp->bios_local_image, bp->bios, bp->bios_size);
-+		original_bios = bp->bios;
-+		bp->bios = bp->bios_local_image;
-+		connector_tbl =
-+			GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+		/* Step 2: (only if MXM connector found) Patch BIOS image with
-+		 * info from external module */
-+		if (mxm_connector_found &&
-+			patch_bios_image_from_ext_display_connection_info(bp) !=
-+				BP_RESULT_OK) {
-+			/* Patching the bios image has failed. We will copy
-+			 * again original image provided and afterwards
-+			 * only remove null entries */
-+			dc_service_memmove(
-+				bp->bios_local_image,
-+				original_bios,
-+				bp->bios_size);
-+		}
-+
-+		/* Step 3: Compact connector table (remove null entries, valid
-+		 * entries moved to beginning) */
-+		for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+			object = &connector_tbl->asObjects[i];
-+			object_id = object_id_from_bios_object_id(
-+				le16_to_cpu(object->usObjectID));
-+
-+			if (OBJECT_TYPE_CONNECTOR != object_id.type)
-+				continue;
-+
-+			if (i != connectors_num) {
-+				dc_service_memmove(
-+					&connector_tbl->
-+					asObjects[connectors_num],
-+					object,
-+					sizeof(ATOM_OBJECT));
-+			}
-+			++connectors_num;
-+		}
-+		connector_tbl->ucNumberOfObjects = (uint8_t)connectors_num;
-+	}
-+}
-+
-+void dal_bios_parser_post_init(struct bios_parser *bp)
-+{
-+	process_ext_display_connection_info(bp);
-+}
-+
-+bool dal_bios_parser_is_accelerated_mode(
-+	struct bios_parser *bp)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	return bp->bios_helper->is_accelerated_mode(
-+		bp->ctx);
-+#else
-+	dal_logger_write(bp->ctx->logger,
-+		LOG_MAJOR_BIOS,
-+		LOG_MINOR_BIOS_CMD_TABLE,
-+		"%s: VBIOS is not supported", __func__);
-+	return false;
-+#endif
-+}
-+
-+/**
-+* dal_bios_parser_set_scratch_connected
-+*
-+* @brief
-+*  update VBIOS scratch register about connected displays
-+*
-+* @param
-+*  bool - update scratch register or just prepare info to be updated
-+*  bool - connection state
-+*  const ConnectorDeviceTagInfo* - pointer to device type and enum ID
-+*/
-+void dal_bios_parser_set_scratch_connected(
-+	struct bios_parser *bp,
-+	struct graphics_object_id connector_id,
-+	bool connected,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	bp->bios_helper->set_scratch_connected(
-+		bp->ctx,
-+		connector_id, connected, device_tag);
-+#else
-+	dal_logger_write(bp->ctx->logger,
-+		LOG_MAJOR_BIOS,
-+		LOG_MINOR_BIOS_CMD_TABLE,
-+		"%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+/**
-+* dal_bios_parser_set_scratch_critical_state
-+*
-+* @brief
-+*  update critical state bit in VBIOS scratch register
-+*
-+* @param
-+*  bool - to set or reset state
-+*/
-+void dal_bios_parser_set_scratch_critical_state(
-+	struct bios_parser *bp,
-+	bool state)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	bp->bios_helper->set_scratch_critical_state(
-+			bp->ctx, state);
-+#else
-+	dal_logger_write(bp->ctx->logger,
-+		LOG_MAJOR_BIOS,
-+		LOG_MINOR_BIOS_CMD_TABLE,
-+		"%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+void dal_bios_parser_set_scratch_acc_mode_change(
-+	struct bios_parser *bp)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	bp->bios_helper->set_scratch_acc_mode_change(
-+		bp->ctx);
-+#else
-+	dal_logger_write(bp->ctx->logger,
-+		LOG_MAJOR_BIOS,
-+		LOG_MINOR_BIOS_CMD_TABLE,
-+		"%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+/**
-+* dal_bios_parser_prepare_scratch_active_and_requested
-+*
-+* @brief
-+*  update VBIOS scratch registers about active and requested displays
-+*
-+* @param
-+*  enum controller_id - controller Id
-+*  enum signal_type signal - signal type used on display
-+*  const struct connector_device_tag_info * - pointer to display type and
-+*  enum Id
-+*/
-+void dal_bios_parser_prepare_scratch_active_and_requested(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	enum signal_type signal,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	bp->bios_helper->prepare_scratch_active_and_requested(
-+			bp->ctx,
-+			&bp->vbios_helper_data,
-+			controller_id,
-+			signal,
-+			device_tag);
-+#else
-+	dal_logger_write(bp->ctx->logger,
-+		LOG_MAJOR_BIOS,
-+		LOG_MINOR_BIOS_CMD_TABLE,
-+		"%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+void dal_bios_parser_set_scratch_active_and_requested(
-+	struct bios_parser *bp)
-+{
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	bp->bios_helper->set_scratch_active_and_requested(
-+		bp->ctx,
-+		&bp->vbios_helper_data);
-+#else
-+	dal_logger_write(bp->ctx->logger,
-+		LOG_MAJOR_BIOS,
-+		LOG_MINOR_BIOS_CMD_TABLE,
-+		"%s: VBIOS is not supported", __func__);
-+#endif
-+}
-+
-+/*
-+ * get_integrated_info_v8
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v8(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+	ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *info_v8;
-+	uint32_t i;
-+
-+	info_v8 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_8,
-+		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+	if (info_v8 != NULL) {
-+		info->boot_up_engine_clock =
-+			le32_to_cpu(info_v8->ulBootUpEngineClock) * 10;
-+		info->dentist_vco_freq =
-+			le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
-+		info->boot_up_uma_clock =
-+			le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
-+
-+		for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+			/* Convert [10KHz] into [KHz] */
-+			info->disp_clk_voltage[i].max_supported_clk =
-+					le32_to_cpu(info_v8->sDISPCLK_Voltage[i].
-+					ulMaximumSupportedCLK) * 10;
-+			info->disp_clk_voltage[i].voltage_index =
-+				le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
-+		}
-+
-+		info->boot_up_req_display_vector =
-+			le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
-+		info->gpu_cap_info =
-+			le32_to_cpu(info_v8->ulGPUCapInfo);
-+
-+		/*
-+		 * system_config: Bit[0] = 0 : PCIE power gating disabled
-+		 *                       = 1 : PCIE power gating enabled
-+		 *                Bit[1] = 0 : DDR-PLL shut down disabled
-+		 *                       = 1 : DDR-PLL shut down enabled
-+		 *                Bit[2] = 0 : DDR-PLL power down disabled
-+		 *                       = 1 : DDR-PLL power down enabled
-+		 */
-+		info->system_config = le32_to_cpu(info_v8->ulSystemConfig);
-+		info->cpu_cap_info = le32_to_cpu(info_v8->ulCPUCapInfo);
-+		info->boot_up_nb_voltage =
-+				le16_to_cpu(info_v8->usBootUpNBVoltage);
-+		info->ext_disp_conn_info_offset =
-+				le16_to_cpu(info_v8->usExtDispConnInfoOffset);
-+		info->memory_type = info_v8->ucMemoryType;
-+		info->ma_channel_number = info_v8->ucUMAChannelNumber;
-+		info->gmc_restore_reset_time =
-+				le32_to_cpu(info_v8->ulGMCRestoreResetTime);
-+
-+		info->minimum_n_clk =
-+				le32_to_cpu(info_v8->ulNbpStateNClkFreq[0]);
-+		for (i = 1; i < 4; ++i)
-+			info->minimum_n_clk =
-+			info->minimum_n_clk < le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]) ?
-+			info->minimum_n_clk : le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]);
-+
-+		info->idle_n_clk = le32_to_cpu(info_v8->ulIdleNClk);
-+		info->ddr_dll_power_up_time =
-+				le32_to_cpu(info_v8->ulDDR_DLL_PowerUpTime);
-+		info->ddr_pll_power_up_time =
-+				le32_to_cpu(info_v8->ulDDR_PLL_PowerUpTime);
-+		info->pcie_clk_ss_type = le16_to_cpu(info_v8->usPCIEClkSSType);
-+		info->lvds_ss_percentage =
-+				le16_to_cpu(info_v8->usLvdsSSPercentage);
-+		info->lvds_sspread_rate_in_10hz =
-+				le16_to_cpu(info_v8->usLvdsSSpreadRateIn10Hz);
-+		info->hdmi_ss_percentage =
-+				le16_to_cpu(info_v8->usHDMISSPercentage);
-+		info->hdmi_sspread_rate_in_10hz =
-+				le16_to_cpu(info_v8->usHDMISSpreadRateIn10Hz);
-+		info->dvi_ss_percentage =
-+				le16_to_cpu(info_v8->usDVISSPercentage);
-+		info->dvi_sspread_rate_in_10_hz =
-+				le16_to_cpu(info_v8->usDVISSpreadRateIn10Hz);
-+
-+		info->max_lvds_pclk_freq_in_single_link =
-+				le16_to_cpu(info_v8->usMaxLVDSPclkFreqInSingleLink);
-+		info->lvds_misc = info_v8->ucLvdsMisc;
-+		info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+				info_v8->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+		info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+				info_v8->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+		info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+				info_v8->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+		info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+				info_v8->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+		info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+				info_v8->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+		info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+				info_v8->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+		info->lvds_off_to_on_delay_in_4ms =
-+				info_v8->ucLVDSOffToOnDelay_in4Ms;
-+		info->lvds_bit_depth_control_val =
-+				le32_to_cpu(info_v8->ulLCDBitDepthControlVal);
-+
-+		for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+			/* Convert [10KHz] into [KHz] */
-+			info->avail_s_clk[i].supported_s_clk =
-+				le32_to_cpu(info_v8->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+			info->avail_s_clk[i].voltage_index =
-+				le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageIndex);
-+			info->avail_s_clk[i].voltage_id =
-+				le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageID);
-+		}
-+
-+		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+			info->ext_disp_conn_info.gu_id[i] =
-+					info_v8->sExtDispConnInfo.ucGuid[i];
-+		}
-+
-+		for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+			info->ext_disp_conn_info.path[i].device_connector_id =
-+					object_id_from_bios_object_id(
-+			le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+
-+			info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+					object_id_from_bios_object_id(
-+			le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+
-+			info->ext_disp_conn_info.path[i].device_tag =
-+				le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceTag);
-+			info->ext_disp_conn_info.path[i].device_acpi_enum =
-+				le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+			info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+			info_v8->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+			info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+			info_v8->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+			info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+			info_v8->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+		}
-+		info->ext_disp_conn_info.checksum =
-+				info_v8->sExtDispConnInfo.ucChecksum;
-+
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*
-+ * get_integrated_info_v8
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v9(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+	ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info_v9;
-+	uint32_t i;
-+
-+	info_v9 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_9,
-+		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+	if (info_v9 != NULL) {
-+		info->boot_up_engine_clock =
-+				le32_to_cpu(info_v9->ulBootUpEngineClock) * 10;
-+		info->dentist_vco_freq =
-+				le32_to_cpu(info_v9->ulDentistVCOFreq) * 10;
-+		info->boot_up_uma_clock =
-+				le32_to_cpu(info_v9->ulBootUpUMAClock) * 10;
-+
-+		for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+			/* Convert [10KHz] into [KHz] */
-+			info->disp_clk_voltage[i].max_supported_clk =
-+				le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
-+			info->disp_clk_voltage[i].voltage_index =
-+				le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
-+		}
-+
-+		info->boot_up_req_display_vector =
-+				le32_to_cpu(info_v9->ulBootUpReqDisplayVector);
-+		info->gpu_cap_info = le32_to_cpu(info_v9->ulGPUCapInfo);
-+
-+		/*
-+		 * system_config: Bit[0] = 0 : PCIE power gating disabled
-+		 *                       = 1 : PCIE power gating enabled
-+		 *                Bit[1] = 0 : DDR-PLL shut down disabled
-+		 *                       = 1 : DDR-PLL shut down enabled
-+		 *                Bit[2] = 0 : DDR-PLL power down disabled
-+		 *                       = 1 : DDR-PLL power down enabled
-+		 */
-+		info->system_config = le32_to_cpu(info_v9->ulSystemConfig);
-+		info->cpu_cap_info = le32_to_cpu(info_v9->ulCPUCapInfo);
-+		info->boot_up_nb_voltage =
-+				le16_to_cpu(info_v9->usBootUpNBVoltage);
-+		info->ext_disp_conn_info_offset =
-+				le16_to_cpu(info_v9->usExtDispConnInfoOffset);
-+		info->memory_type = info_v9->ucMemoryType;
-+		info->ma_channel_number = info_v9->ucUMAChannelNumber;
-+		info->gmc_restore_reset_time =
-+				le32_to_cpu(info_v9->ulGMCRestoreResetTime);
-+
-+		info->minimum_n_clk =
-+				le32_to_cpu(info_v9->ulNbpStateNClkFreq[0]);
-+		for (i = 1; i < 4; ++i)
-+			info->minimum_n_clk =
-+			info->minimum_n_clk < le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]) ?
-+			info->minimum_n_clk : le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]);
-+
-+		info->idle_n_clk = le32_to_cpu(info_v9->ulIdleNClk);
-+		info->ddr_dll_power_up_time =
-+				le32_to_cpu(info_v9->ulDDR_DLL_PowerUpTime);
-+		info->ddr_pll_power_up_time =
-+				le32_to_cpu(info_v9->ulDDR_PLL_PowerUpTime);
-+		info->pcie_clk_ss_type = le16_to_cpu(info_v9->usPCIEClkSSType);
-+		info->lvds_ss_percentage =
-+				le16_to_cpu(info_v9->usLvdsSSPercentage);
-+		info->lvds_sspread_rate_in_10hz =
-+				le16_to_cpu(info_v9->usLvdsSSpreadRateIn10Hz);
-+		info->hdmi_ss_percentage =
-+				le16_to_cpu(info_v9->usHDMISSPercentage);
-+		info->hdmi_sspread_rate_in_10hz =
-+				le16_to_cpu(info_v9->usHDMISSpreadRateIn10Hz);
-+		info->dvi_ss_percentage =
-+				le16_to_cpu(info_v9->usDVISSPercentage);
-+		info->dvi_sspread_rate_in_10_hz =
-+				le16_to_cpu(info_v9->usDVISSpreadRateIn10Hz);
-+
-+		info->max_lvds_pclk_freq_in_single_link =
-+				le16_to_cpu(info_v9->usMaxLVDSPclkFreqInSingleLink);
-+		info->lvds_misc = info_v9->ucLvdsMisc;
-+		info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+				info_v9->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+		info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+				info_v9->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+		info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+				info_v9->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+		info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+				info_v9->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+		info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+				info_v9->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+		info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+				info_v9->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+		info->lvds_off_to_on_delay_in_4ms =
-+				info_v9->ucLVDSOffToOnDelay_in4Ms;
-+		info->lvds_bit_depth_control_val =
-+				le32_to_cpu(info_v9->ulLCDBitDepthControlVal);
-+
-+		for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+			/* Convert [10KHz] into [KHz] */
-+			info->avail_s_clk[i].supported_s_clk =
-+				le32_to_cpu(info_v9->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+			info->avail_s_clk[i].voltage_index =
-+				le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageIndex);
-+			info->avail_s_clk[i].voltage_id =
-+				le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageID);
-+		}
-+
-+		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+			info->ext_disp_conn_info.gu_id[i] =
-+					info_v9->sExtDispConnInfo.ucGuid[i];
-+		}
-+
-+		for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+			info->ext_disp_conn_info.path[i].device_connector_id =
-+					object_id_from_bios_object_id(
-+			le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+
-+			info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+					object_id_from_bios_object_id(
-+			le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+
-+			info->ext_disp_conn_info.path[i].device_tag =
-+				le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceTag);
-+			info->ext_disp_conn_info.path[i].device_acpi_enum =
-+				le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+			info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+			info_v9->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+			info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+			info_v9->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+			info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+			info_v9->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+		}
-+		info->ext_disp_conn_info.checksum =
-+				info_v9->sExtDispConnInfo.ucChecksum;
-+
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*
-+ * construct_integrated_info
-+ *
-+ * @brief
-+ * Get integrated BIOS information based on table revision
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result construct_integrated_info(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision;
-+
-+	if (info != NULL &&
-+		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo) {
-+		header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+		get_atom_data_table_revision(header, &revision);
-+
-+		/* Don't need to check major revision as they are all 1 */
-+		switch (revision.minor) {
-+		case 8:
-+			result = get_integrated_info_v8(bp, info);
-+			break;
-+		case 9:
-+			result = get_integrated_info_v9(bp, info);
-+			break;
-+		default:
-+			return result;
-+
-+		}
-+	}
-+
-+	/* Sort voltage table from low to high*/
-+	if (result == BP_RESULT_OK) {
-+		struct clock_voltage_caps temp = {0, 0};
-+		uint32_t i;
-+		uint32_t j;
-+
-+		for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+			for (j = i; j > 0; --j) {
-+				if (
-+				info->disp_clk_voltage[j].max_supported_clk <
-+				info->disp_clk_voltage[j-1].max_supported_clk) {
-+					/* swap j and j - 1*/
-+					temp = info->disp_clk_voltage[j-1];
-+					info->disp_clk_voltage[j-1] =
-+						info->disp_clk_voltage[j];
-+					info->disp_clk_voltage[j] = temp;
-+				}
-+			}
-+		}
-+
-+	}
-+
-+	return result;
-+}
-+
-+/*
-+ * dal_bios_parser_create_integrated_info
-+ *
-+ * @brief
-+ * Create integrated info
-+ *
-+ * @param
-+ * bios_parser *bp - [in] BIOS  parser handler
-+ *
-+ * @return
-+ * struct integrated_info * - pointer to the newly created integrated info
-+ */
-+struct integrated_info *dal_bios_parser_create_integrated_info(
-+	struct bios_parser *bp)
-+{
-+	struct integrated_info *info = NULL;
-+
-+	info = dc_service_alloc(bp->ctx, sizeof(struct integrated_info));
-+
-+	if (info == NULL) {
-+		ASSERT_CRITICAL(0);
-+		return NULL;
-+	}
-+
-+	if (construct_integrated_info(bp, info) == BP_RESULT_OK)
-+		return info;
-+
-+	dc_service_free(bp->ctx, info);
-+
-+	return NULL;
-+}
-+
-+/*
-+ * dal_bios_parser_destroy_integrated_info
-+ *
-+ * @brief
-+ * Destroy provided integrated info
-+ *
-+ * @param
-+ * struct integrated_info **info - [in] info to be destroied
-+ */
-+void dal_bios_parser_destroy_integrated_info(struct dc_context *ctx, struct integrated_info **info)
-+{
-+	if (info == NULL) {
-+		ASSERT_CRITICAL(0);
-+		return;
-+	}
-+
-+	if (*info != NULL) {
-+		dc_service_free(ctx, *info);
-+		*info = NULL;
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-new file mode 100644
-index 0000000..db169f1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-@@ -0,0 +1,78 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_H__
-+#define __DAL_BIOS_PARSER_H__
-+
-+#include "bios_parser_helper.h"
-+
-+struct atom_data_revision {
-+	uint32_t major;
-+	uint32_t minor;
-+};
-+
-+struct object_info_table {
-+	struct atom_data_revision revision;
-+	union {
-+		ATOM_OBJECT_HEADER *v1_1;
-+		ATOM_OBJECT_HEADER_V3 *v1_3;
-+	};
-+};
-+
-+enum spread_spectrum_id {
-+	SS_ID_UNKNOWN = 0,
-+	SS_ID_DP1 = 0xf1,
-+	SS_ID_DP2 = 0xf2,
-+	SS_ID_LVLINK_2700MHZ = 0xf3,
-+	SS_ID_LVLINK_1620MHZ = 0xf4
-+};
-+
-+struct bios_parser {
-+	struct dc_context *ctx;
-+	struct adapter_service *as;
-+
-+	struct object_info_table object_info_tbl;
-+	uint32_t object_info_tbl_offset;
-+	ATOM_MASTER_DATA_TABLE *master_data_tbl;
-+
-+	uint8_t *bios;
-+	uint32_t bios_size;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	const struct bios_parser_helper *bios_helper;
-+	struct vbios_helper_data vbios_helper_data;
-+#endif /* CONFIG_DRM_AMD_DAL_VBIOS_PRESENT */
-+
-+	const struct command_table_helper *cmd_helper;
-+	struct cmd_tbl cmd_tbl;
-+
-+	uint8_t *bios_local_image;
-+	enum lcd_scale lcd_scale;
-+
-+	bool remap_device_tags;
-+	bool headless_no_opm;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-new file mode 100644
-index 0000000..0089800
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -0,0 +1,193 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+#include "bios_parser_helper.h"
-+#include "command_table_helper.h"
-+#include "command_table.h"
-+#include "bios_parser.h"
-+
-+bool dal_bios_parser_init_bios_helper(
-+	struct bios_parser *bp,
-+	enum dce_version version)
-+{
-+	switch (version) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
-+		return true;
-+
-+#endif
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+bool dal_bios_parser_is_lid_open(
-+	struct bios_parser *bp)
-+{
-+	const struct graphics_object_id encoder = dal_graphics_object_id_init(
-+		ENCODER_ID_INTERNAL_UNIPHY,
-+		ENUM_ID_UNKNOWN,
-+		OBJECT_TYPE_UNKNOWN);
-+	const struct graphics_object_id connector = dal_graphics_object_id_init(
-+		CONNECTOR_ID_LVDS,
-+		ENUM_ID_UNKNOWN,
-+		OBJECT_TYPE_UNKNOWN);
-+
-+	enum signal_type signal;
-+
-+	/* check if VBIOS reported LCD as connected */
-+	signal = bp->bios_helper->detect_sink(bp->ctx,
-+		encoder, connector, SIGNAL_TYPE_LVDS);
-+
-+	if (signal == SIGNAL_TYPE_NONE)
-+		return false;
-+
-+	return bp->bios_helper->is_lid_open(bp->ctx);
-+}
-+
-+bool dal_bios_parser_is_lid_status_changed(
-+	struct bios_parser *bp)
-+{
-+	return bp->bios_helper->is_lid_status_changed(
-+			bp->ctx);
-+}
-+
-+bool dal_bios_parser_is_display_config_changed(
-+	struct bios_parser *bp)
-+{
-+	return bp->bios_helper->is_display_config_changed(
-+			bp->ctx);
-+}
-+
-+/**
-+* dal_bios_parser_set_scratch_lcd_scale
-+*
-+* @brief
-+*  update VBIOS scratch pad registers about LCD scale
-+*
-+* @param
-+*  bool - to set to full panel mode or aspect-ratio mode
-+*/
-+void dal_bios_parser_set_scratch_lcd_scale(
-+	struct bios_parser *bp,
-+	enum lcd_scale scale)
-+{
-+	bp->bios_helper->set_scratch_lcd_scale(
-+		bp->ctx, scale);
-+}
-+
-+/**
-+* dal_bios_parser_get_scratch_lcd_scale
-+*
-+* @brief
-+*  get LCD Scale Mode from VBIOS scratch register
-+*
-+* @param
-+*  NONE
-+*/
-+enum lcd_scale  dal_bios_parser_get_scratch_lcd_scale(
-+	struct bios_parser *bp)
-+{
-+	return bp->bios_helper->get_scratch_lcd_scale(
-+			bp->ctx);
-+}
-+
-+void dal_bios_parser_get_bios_event_info(
-+	struct bios_parser *bp,
-+	struct bios_event_info *info)
-+{
-+	bp->bios_helper->get_bios_event_info(
-+		bp->ctx, info);
-+}
-+
-+/* ABM related */
-+
-+void dal_bios_parser_update_requested_backlight_level(
-+	struct bios_parser *bp,
-+	uint32_t backlight_8bit)
-+{
-+	bp->bios_helper->update_requested_backlight_level(
-+		bp->ctx,
-+		backlight_8bit);
-+}
-+
-+uint32_t dal_bios_parser_get_requested_backlight_level(
-+	struct bios_parser *bp)
-+{
-+	return bp->bios_helper->get_requested_backlight_level(
-+			bp->ctx);
-+}
-+
-+void dal_bios_parser_take_backlight_control(
-+	struct bios_parser *bp,
-+	bool cntl)
-+{
-+	bp->bios_helper->take_backlight_control(
-+		bp->ctx, cntl);
-+}
-+
-+/**
-+ * dal_bios_parser_is_active_display
-+ *  Check video bios active display.
-+ */
-+bool dal_bios_parser_is_active_display(
-+	struct bios_parser *bp,
-+	enum signal_type signal,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+	return bp->bios_helper->is_active_display(
-+			bp->ctx, signal, device_tag);
-+}
-+
-+/**
-+ * dal_bios_parser_get_embedded_display_controller_id
-+ * Get controller ID for embedded display from scratch registers
-+ */
-+enum controller_id dal_bios_parser_get_embedded_display_controller_id(
-+	struct bios_parser *bp)
-+{
-+	return bp->bios_helper->get_embedded_display_controller_id(
-+			bp->ctx);
-+}
-+
-+/**
-+ * dal_bios_parser_get_embedded_display_refresh_rate
-+ * Get refresh rate for embedded display from scratch registers
-+ */
-+uint32_t dal_bios_parser_get_embedded_display_refresh_rate(
-+	struct bios_parser *bp)
-+{
-+	return bp->bios_helper->get_embedded_display_refresh_rate(
-+			bp->ctx);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-new file mode 100644
-index 0000000..d0e9de9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -0,0 +1,108 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_HELPER_H__
-+#define __DAL_BIOS_PARSER_HELPER_H__
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/bios_parser_helper_dce110.h"
-+#endif
-+
-+struct bios_parser;
-+
-+struct vbios_helper_data {
-+	uint32_t active;
-+	uint32_t requested;
-+};
-+
-+struct bios_parser_helper {
-+	enum signal_type (*detect_sink)(
-+		struct dc_context *ctx,
-+		struct graphics_object_id encoder,
-+		struct graphics_object_id connector,
-+		enum signal_type signal);
-+	bool (*is_lid_open)(
-+		struct dc_context *ctx);
-+	bool (*is_lid_status_changed)(
-+		struct dc_context *ctx);
-+	bool (*is_display_config_changed)(
-+		struct dc_context *ctx);
-+	void (*set_scratch_acc_mode_change)(
-+		struct dc_context *ctx);
-+	bool (*is_accelerated_mode)(
-+		struct dc_context *ctx);
-+	void (*set_scratch_critical_state)(
-+		struct dc_context *ctx,
-+		bool state);
-+	void (*prepare_scratch_active_and_requested)(
-+		struct dc_context *ctx,
-+		struct vbios_helper_data *data,
-+		enum controller_id id, enum signal_type s,
-+		const struct connector_device_tag_info *dev_tag);
-+	void (*set_scratch_active_and_requested)(
-+		struct dc_context *ctx,
-+		struct vbios_helper_data *d);
-+	void (*set_scratch_connected)(
-+		struct dc_context *ctx,
-+		struct graphics_object_id id,
-+		bool connected,
-+		const struct connector_device_tag_info *device_tag);
-+	void (*set_scratch_lcd_scale)(
-+		struct dc_context *ctx,
-+		enum lcd_scale lcd_scale_request);
-+	enum lcd_scale (*get_scratch_lcd_scale)(
-+		struct dc_context *ctx);
-+	uint32_t (*fmt_control)(
-+		struct dc_context *ctx,
-+		enum controller_id id, uint32_t *value);
-+	uint32_t (*fmt_bit_depth_control)(
-+		struct dc_context *ctx,
-+		enum controller_id id,
-+		uint32_t *value);
-+	void (*get_bios_event_info)(
-+		struct dc_context *ctx,
-+		struct bios_event_info *info);
-+	void (*take_backlight_control)(
-+		struct dc_context *ctx, bool control);
-+	uint32_t (*get_requested_backlight_level)(
-+		struct dc_context *ctx);
-+	void (*update_requested_backlight_level)(
-+		struct dc_context *ctx,
-+		uint32_t backlight_8bit);
-+	bool (*is_active_display)(
-+		struct dc_context *ctx,
-+		enum signal_type signal,
-+		const struct connector_device_tag_info *dev_tag);
-+	enum controller_id (*get_embedded_display_controller_id)(
-+		struct dc_context *ctx);
-+	uint32_t (*get_embedded_display_refresh_rate)(
-+		struct dc_context *ctx);
-+};
-+
-+bool dal_bios_parser_init_bios_helper(
-+	struct bios_parser *bp,
-+	enum dce_version ver);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-new file mode 100644
-index 0000000..a807ab6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -0,0 +1,2616 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_interface.h"
-+
-+#include "command_table.h"
-+#include "command_table_helper.h"
-+#include "bios_parser_helper.h"
-+#include "bios_parser.h"
-+
-+#define EXEC_BIOS_CMD_TABLE(command, params)\
-+	(cgs_atom_exec_cmd_table(bp->ctx->cgs_device, \
-+		GetIndexIntoMasterTable(COMMAND, command), \
-+		&params) == 0)
-+
-+#define BIOS_CMD_TABLE_REVISION(command, frev, crev)\
-+	cgs_atom_get_cmd_table_revs(bp->ctx->cgs_device, \
-+		GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
-+
-+#define BIOS_CMD_TABLE_PARA_REVISION(command)\
-+	dal_bios_cmd_table_para_revision(bp->ctx, \
-+		GetIndexIntoMasterTable(COMMAND, command))
-+
-+
-+static void init_dig_encoder_control(struct bios_parser *bp);
-+static void init_dvo_encoder_control(struct bios_parser *bp);
-+static void init_transmitter_control(struct bios_parser *bp);
-+static void init_set_pixel_clock(struct bios_parser *bp);
-+static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
-+static void init_adjust_display_pll(struct bios_parser *bp);
-+static void init_dac_encoder_control(struct bios_parser *bp);
-+static void init_dac_output_control(struct bios_parser *bp);
-+static void init_dac_load_detection(struct bios_parser *bp);
-+static void init_blank_crtc(struct bios_parser *bp);
-+static void init_set_crtc_timing(struct bios_parser *bp);
-+static void init_set_crtc_overscan(struct bios_parser *bp);
-+static void init_select_crtc_source(struct bios_parser *bp);
-+static void init_enable_crtc(struct bios_parser *bp);
-+static void init_enable_crtc_mem_req(struct bios_parser *bp);
-+static void init_compute_memore_engine_pll(struct bios_parser *bp);
-+static void init_external_encoder_control(struct bios_parser *bp);
-+static void init_enable_disp_power_gating(struct bios_parser *bp);
-+static void init_program_clock(struct bios_parser *bp);
-+
-+void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
-+{
-+	init_dig_encoder_control(bp);
-+	init_dvo_encoder_control(bp);
-+	init_transmitter_control(bp);
-+	init_set_pixel_clock(bp);
-+	init_enable_spread_spectrum_on_ppll(bp);
-+	init_adjust_display_pll(bp);
-+	init_dac_encoder_control(bp);
-+	init_dac_output_control(bp);
-+	init_dac_load_detection(bp);
-+	init_blank_crtc(bp);
-+	init_set_crtc_timing(bp);
-+	init_set_crtc_overscan(bp);
-+	init_select_crtc_source(bp);
-+	init_enable_crtc(bp);
-+	init_enable_crtc_mem_req(bp);
-+	init_program_clock(bp);
-+	init_compute_memore_engine_pll(bp);
-+	init_external_encoder_control(bp);
-+	init_enable_disp_power_gating(bp);
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  D I G E N C O D E R C O N T R O L
-+**
-+********************************************************************************
-+*******************************************************************************/
-+static enum bp_result encoder_control_digx_v3(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl);
-+
-+static enum bp_result encoder_control_digx_v4(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl);
-+static void init_encoder_control_dig_v1(struct bios_parser *bp);
-+
-+static void init_dig_encoder_control(struct bios_parser *bp)
-+{
-+	uint32_t version =
-+		BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl);
-+
-+	switch (version) {
-+	case 4:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4;
-+		break;
-+	case 2:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3;
-+		break;
-+	default:
-+		init_encoder_control_dig_v1(bp);
-+		break;
-+	}
-+}
-+
-+static enum bp_result encoder_control_dig_v1(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl);
-+static enum bp_result encoder_control_dig1_v1(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl);
-+static enum bp_result encoder_control_dig2_v1(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl);
-+
-+static void init_encoder_control_dig_v1(struct bios_parser *bp)
-+{
-+	struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-+
-+	if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG1EncoderControl))
-+		cmd_tbl->encoder_control_dig1 = encoder_control_dig1_v1;
-+	else
-+		cmd_tbl->encoder_control_dig1 = NULL;
-+
-+	if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG2EncoderControl))
-+		cmd_tbl->encoder_control_dig2 = encoder_control_dig2_v1;
-+	else
-+		cmd_tbl->encoder_control_dig2 = NULL;
-+
-+	cmd_tbl->dig_encoder_control = encoder_control_dig_v1;
-+}
-+
-+static enum bp_result encoder_control_dig_v1(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-+
-+	if (cntl != NULL)
-+		switch (cntl->engine_id) {
-+		case ENGINE_ID_DIGA:
-+			if (cmd_tbl->encoder_control_dig1 != NULL)
-+				result =
-+					cmd_tbl->encoder_control_dig1(bp, cntl);
-+			break;
-+		case ENGINE_ID_DIGB:
-+			if (cmd_tbl->encoder_control_dig2 != NULL)
-+				result =
-+					cmd_tbl->encoder_control_dig2(bp, cntl);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_dig1_v1(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-+
-+	bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIG1EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_dig2_v1(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-+
-+	bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIG2EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v3(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V3 params = {0};
-+
-+	if (LANE_COUNT_FOUR < cntl->lanes_number)
-+		params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */
-+	else
-+		params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
-+
-+	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+	params.ucEncoderMode =
-+		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+				cntl->signal,
-+				cntl->enable_dp_audio);
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.usPixelClock =
-+				cpu_to_le16((le32_to_cpu(params.usPixelClock) * 30) / 24);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.usPixelClock =
-+				cpu_to_le16((le32_to_cpu(params.usPixelClock) * 36) / 24);
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.usPixelClock =
-+				cpu_to_le16((le32_to_cpu(params.usPixelClock) * 48) / 24);
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v4(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V4 params = {0};
-+
-+	if (LANE_COUNT_FOUR < cntl->lanes_number)
-+		params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */
-+	else
-+		params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
-+
-+
-+	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+	params.ucEncoderMode =
-+		(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+				cntl->signal,
-+				cntl->enable_dp_audio));
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.usPixelClock =
-+				cpu_to_le16((le32_to_cpu(params.usPixelClock) * 30) / 24);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.usPixelClock =
-+				cpu_to_le16((le32_to_cpu(params.usPixelClock) * 36) / 24);
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.usPixelClock =
-+				cpu_to_le16((le32_to_cpu(params.usPixelClock) * 48) / 24);
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                 DVO ENCODER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result dvo_encoder_control_v3(
-+		struct bios_parser *bp,
-+		struct bp_dvo_encoder_control *cntl);
-+
-+static void init_dvo_encoder_control(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DVOEncoderControl)) {
-+	case 3:
-+		bp->cmd_tbl.dvo_encoder_control = dvo_encoder_control_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.dvo_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result dvo_encoder_control_v3(
-+		struct bios_parser *bp,
-+		struct bp_dvo_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DVO_ENCODER_CONTROL_PARAMETERS_V3 params;
-+	uint8_t config = 0;
-+
-+	if (cntl->memory_rate == DVO_ENCODER_MEMORY_RATE_SDR)
-+		config |= DVO_ENCODER_CONFIG_SDR_SPEED;
-+
-+	switch (cntl->interface_width) {
-+	case DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT:
-+		config |= DVO_ENCODER_CONFIG_24BIT;
-+		break;
-+	case DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT:
-+		config |= DVO_ENCODER_CONFIG_UPPER12BIT;
-+		break;
-+	default:
-+		config |= DVO_ENCODER_CONFIG_LOW12BIT;
-+		break;
-+	}
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	dc_service_memset(&params, 0, sizeof(params));
-+	params.ucAction = (uint8_t) cntl->action;
-+	params.usPixelClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
-+	params.ucDVOConfig = config;
-+
-+	if (EXEC_BIOS_CMD_TABLE(DVOEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  TRANSMITTER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result transmitter_control_v2(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v3(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v4(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v1_5(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+
-+static void init_transmitter_control(struct bios_parser *bp)
-+{
-+	uint8_t frev;
-+	uint8_t crev;
-+
-+	if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
-+			frev, crev) != 0)
-+		BREAK_TO_DEBUGGER();
-+	switch (crev) {
-+	case 2:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v3;
-+		break;
-+	case 4:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v4;
-+		break;
-+	case 5:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v1_5;
-+		break;
-+	default:
-+		bp->cmd_tbl.transmitter_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result transmitter_control_v2(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 params;
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	switch (cntl->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		break;
-+	default:
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	switch (cntl->action) {
-+	case TRANSMITTER_CONTROL_INIT:
-+		if ((CONNECTOR_ID_DUAL_LINK_DVII == connector_id) ||
-+				(CONNECTOR_ID_DUAL_LINK_DVID == connector_id))
-+			/* on INIT this bit should be set according to the
-+			 * phisycal connector
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* connector object id */
-+		params.usInitInfo =
-+			cpu_to_le16((uint8_t)cntl->connector_obj_id.id);
-+		break;
-+	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+		/* votage swing and pre-emphsis */
-+		params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
-+		params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
-+		break;
-+	default:
-+		/* if dual-link */
-+		if (LANE_COUNT_FOUR < cntl->lanes_number) {
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 20KHz units
-+			 */
-+			params.usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+		} else
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 10KHz units
-+			 */
-+			params.usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		break;
-+	}
-+
-+	/* 00 - coherent mode
-+	 * 01 - incoherent mode
-+	 */
-+
-+	params.acConfig.fCoherentMode = cntl->coherent;
-+
-+	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+			|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+			|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		/* Bit2: Transmitter Link selection
-+		 * =0 when bit0=0, single link A/C/E, when bit0=1,
-+		 * master link A/C/E
-+		 * =1 when bit0=0, single link B/D/F, when bit0=1,
-+		 * master link B/D/F
-+		 */
-+		params.acConfig.ucLinkSel = 1;
-+
-+	if (ENGINE_ID_DIGB == cntl->engine_id)
-+		/* Bit3: Transmitter data source selection
-+		 * =0 DIGA is data source.
-+		 * =1 DIGB is data source.
-+		 * This bit is only useful when ucAction= ATOM_ENABLE
-+		 */
-+		params.acConfig.ucEncoderSel = 1;
-+
-+	if (CONNECTOR_ID_DISPLAY_PORT == connector_id)
-+		/* Bit4: DP connector flag
-+		 * =0 connector is none-DP connector
-+		 * =1 connector is DP connector
-+		 */
-+		params.acConfig.fDPConnector = 1;
-+
-+	/* Bit[7:6]: Transmitter selection
-+	 * =0 UNIPHY_ENCODER: UNIPHYA/B
-+	 * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+	 * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+	 * =3 reserved
-+	 */
-+	params.acConfig.ucTransmitterSel =
-+		(uint8_t)bp->cmd_helper->transmitter_bp_to_atom(
-+			cntl->transmitter);
-+
-+	params.ucAction = (uint8_t)cntl->action;
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v3(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 params;
-+	uint32_t pll_id;
-+	enum connector_id conn_id =
-+		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
-+			|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	switch (cntl->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		break;
-+	default:
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	if (!cmd->clock_source_id_to_atom(cntl->pll_id, &pll_id))
-+		return BP_RESULT_BADINPUT;
-+
-+	/* fill information based on the action */
-+	switch (cntl->action) {
-+	case TRANSMITTER_CONTROL_INIT:
-+		if (dual_link_conn) {
-+			/* on INIT this bit should be set according to the
-+			 * phisycal connector
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+		}
-+
-+		/* connector object id */
-+		params.usInitInfo =
-+			cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+		break;
-+	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+		/* votage swing and pre-emphsis */
-+		params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
-+		params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
-+		break;
-+	default:
-+		if (dual_link_conn && cntl->multi_path)
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* if dual-link */
-+		if (LANE_COUNT_FOUR < cntl->lanes_number) {
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 20KHz units
-+			 */
-+			params.usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+		} else {
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 10KHz units
-+			 */
-+			params.usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+			if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+				switch (cntl->color_depth) {
-+				case COLOR_DEPTH_101010:
-+					params.usPixelClock =
-+						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
-+					break;
-+				case COLOR_DEPTH_121212:
-+					params.usPixelClock =
-+						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
-+					break;
-+				case COLOR_DEPTH_161616:
-+					params.usPixelClock =
-+						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
-+					break;
-+				default:
-+					break;
-+				}
-+		}
-+		break;
-+	}
-+
-+	/* 00 - coherent mode
-+	 * 01 - incoherent mode
-+	 */
-+
-+	params.acConfig.fCoherentMode = cntl->coherent;
-+
-+	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+			|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+			|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		/* Bit2: Transmitter Link selection
-+		 * =0 when bit0=0, single link A/C/E, when bit0=1,
-+		 * master link A/C/E
-+		 * =1 when bit0=0, single link B/D/F, when bit0=1,
-+		 * master link B/D/F
-+		 */
-+		params.acConfig.ucLinkSel = 1;
-+
-+	if (ENGINE_ID_DIGB == cntl->engine_id)
-+		/* Bit3: Transmitter data source selection
-+		 * =0 DIGA is data source.
-+		 * =1 DIGB is data source.
-+		 * This bit is only useful when ucAction= ATOM_ENABLE
-+		 */
-+		params.acConfig.ucEncoderSel = 1;
-+
-+	/* Bit[7:6]: Transmitter selection
-+	 * =0 UNIPHY_ENCODER: UNIPHYA/B
-+	 * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+	 * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+	 * =3 reserved
-+	 */
-+	params.acConfig.ucTransmitterSel =
-+		(uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);
-+
-+	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+
-+	params.acConfig.ucRefClkSource = (uint8_t)pll_id;
-+
-+	params.ucAction = (uint8_t)cntl->action;
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v4(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 params;
-+	uint32_t ref_clk_src_id;
-+	enum connector_id conn_id =
-+		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	switch (cntl->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		break;
-+	default:
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	if (!cmd->clock_source_id_to_ref_clk_src(cntl->pll_id, &ref_clk_src_id))
-+		return BP_RESULT_BADINPUT;
-+
-+	switch (cntl->action) {
-+	case TRANSMITTER_CONTROL_INIT:
-+	{
-+		if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
-+			(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+			/* on INIT this bit should be set according to the
-+			 * phisycal connector
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* connector object id */
-+		params.usInitInfo =
-+			cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+	}
-+	break;
-+	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+		/* votage swing and pre-emphsis */
-+		params.asMode.ucLaneSel = (uint8_t)(cntl->lane_select);
-+		params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings);
-+		break;
-+	default:
-+		if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
-+			(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* if dual-link */
-+		if (LANE_COUNT_FOUR < cntl->lanes_number)
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 20KHz units
-+			 */
-+			params.usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+		else {
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 10KHz units
-+			 */
-+			params.usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+
-+			if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+				switch (cntl->color_depth) {
-+				case COLOR_DEPTH_101010:
-+					params.usPixelClock =
-+						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
-+					break;
-+				case COLOR_DEPTH_121212:
-+					params.usPixelClock =
-+						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
-+					break;
-+				case COLOR_DEPTH_161616:
-+					params.usPixelClock =
-+						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
-+					break;
-+				default:
-+					break;
-+				}
-+		}
-+		break;
-+	}
-+
-+	/* 00 - coherent mode
-+	 * 01 - incoherent mode
-+	 */
-+
-+	params.acConfig.fCoherentMode = cntl->coherent;
-+
-+	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		/* Bit2: Transmitter Link selection
-+		 * =0 when bit0=0, single link A/C/E, when bit0=1,
-+		 * master link A/C/E
-+		 * =1 when bit0=0, single link B/D/F, when bit0=1,
-+		 * master link B/D/F
-+		 */
-+		params.acConfig.ucLinkSel = 1;
-+
-+	if (ENGINE_ID_DIGB == cntl->engine_id)
-+		/* Bit3: Transmitter data source selection
-+		 * =0 DIGA is data source.
-+		 * =1 DIGB is data source.
-+		 * This bit is only useful when ucAction= ATOM_ENABLE
-+		 */
-+		params.acConfig.ucEncoderSel = 1;
-+
-+	/* Bit[7:6]: Transmitter selection
-+	 * =0 UNIPHY_ENCODER: UNIPHYA/B
-+	 * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+	 * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+	 * =3 reserved
-+	 */
-+	params.acConfig.ucTransmitterSel =
-+		(uint8_t)(cmd->transmitter_bp_to_atom(cntl->transmitter));
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+	params.acConfig.ucRefClkSource = (uint8_t)(ref_clk_src_id);
-+	params.ucAction = (uint8_t)(cntl->action);
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v1_5(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 params;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
-+	params.ucAction = (uint8_t)cntl->action;
-+	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+	params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
-+
-+	params.ucDigMode =
-+		cmd->signal_type_to_atom_dig_mode(cntl->signal);
-+	params.asConfig.ucPhyClkSrcId =
-+		cmd->clock_source_id_to_atom_phy_clk_src_id(cntl->pll_id);
-+	/* 00 - coherent mode */
-+	params.asConfig.ucCoherentMode = cntl->coherent;
-+	params.asConfig.ucHPDSel =
-+		cmd->hpd_sel_to_atom(cntl->hpd_sel);
-+	params.ucDigEncoderSel =
-+		cmd->dig_encoder_sel_to_atom(cntl->engine_id);
-+	params.ucDPLaneSet = (uint8_t) cntl->lane_settings;
-+	params.usSymClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
-+	/*
-+	 * In SI/TN case, caller have to set usPixelClock as following:
-+	 * DP mode: usPixelClock = DP_LINK_CLOCK/10
-+	 * (DP_LINK_CLOCK = 1.62GHz, 2.7GHz, 5.4GHz)
-+	 * DVI single link mode: usPixelClock = pixel clock
-+	 * DVI dual link mode: usPixelClock = pixel clock
-+	 * HDMI mode: usPixelClock = pixel clock * deep_color_ratio
-+	 * (=1: 8bpp, =1.25: 10bpp, =1.5:12bpp, =2: 16bpp)
-+	 * LVDS mode: usPixelClock = pixel clock
-+	 */
-+	switch (cntl->signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.usSymClock =
-+				cpu_to_le16((le16_to_cpu(params.usSymClock) * 30) / 24);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.usSymClock =
-+				cpu_to_le16((le16_to_cpu(params.usSymClock) * 36) / 24);
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.usSymClock =
-+				cpu_to_le16((le16_to_cpu(params.usSymClock) * 48) / 24);
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  SET PIXEL CLOCK
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_pixel_clock_v3(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_set_pixel_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
-+	case 3:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v3;
-+		break;
-+	case 5:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v5;
-+		break;
-+	case 6:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v6;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_pixel_clock = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result set_pixel_clock_v3(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	PIXEL_CLOCK_PARAMETERS_V3 *params;
-+	SET_PIXEL_CLOCK_PS_ALLOCATION allocation;
-+
-+	dc_service_memset(&allocation, 0, sizeof(allocation));
-+
-+	if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
-+		allocation.sPCLKInput.ucPpll = ATOM_PPLL1;
-+	else if (CLOCK_SOURCE_ID_PLL2 == bp_params->pll_id)
-+		allocation.sPCLKInput.ucPpll = ATOM_PPLL2;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	allocation.sPCLKInput.usRefDiv =
-+		cpu_to_le16((uint16_t)bp_params->reference_divider);
-+	allocation.sPCLKInput.usFbDiv =
-+		cpu_to_le16((uint16_t)bp_params->feedback_divider);
-+	allocation.sPCLKInput.ucFracFbDiv =
-+		(uint8_t)bp_params->fractional_feedback_divider;
-+	allocation.sPCLKInput.ucPostDiv =
-+		(uint8_t)bp_params->pixel_clock_post_divider;
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	allocation.sPCLKInput.usPixelClock =
-+		cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+
-+	params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
-+	params->ucTransmitterId =
-+		bp->cmd_helper->encoder_id_to_atom(
-+			dal_graphics_object_id_get_encoder_id(
-+				bp_params->encoder_object_id));
-+	params->ucEncoderMode =
-+		(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+			bp_params->signal_type, false));
-+
-+	if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+		params->ucMiscInfo |= PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+
-+	if (bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK)
-+		params->ucMiscInfo |= PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK;
-+
-+	if (CONTROLLER_ID_D1 != bp_params->controller_id)
-+		params->ucMiscInfo |= PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetPixelClock, allocation))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+#ifndef SET_PIXEL_CLOCK_PS_ALLOCATION_V5
-+/* video bios did not define this: */
-+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION_V5 {
-+	PIXEL_CLOCK_PARAMETERS_V5 sPCLKInput;
-+	/* Caller doesn't need to init this portion */
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;
-+} SET_PIXEL_CLOCK_PS_ALLOCATION_V5;
-+#endif
-+
-+#ifndef SET_PIXEL_CLOCK_PS_ALLOCATION_V6
-+/* video bios did not define this: */
-+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION_V6 {
-+	PIXEL_CLOCK_PARAMETERS_V6 sPCLKInput;
-+	/* Caller doesn't need to init this portion */
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;
-+} SET_PIXEL_CLOCK_PS_ALLOCATION_V6;
-+#endif
-+
-+static enum bp_result set_pixel_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	dc_service_memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+		&& bp->cmd_helper->controller_id_to_atom(
-+			bp_params->controller_id, &controller_id)) {
-+		clk.sPCLKInput.ucCRTC = controller_id;
-+		clk.sPCLKInput.ucPpll = (uint8_t)pll_id;
-+		clk.sPCLKInput.ucRefDiv =
-+			(uint8_t)(bp_params->reference_divider);
-+		clk.sPCLKInput.usFbDiv =
-+			cpu_to_le16((uint16_t)(bp_params->feedback_divider));
-+		clk.sPCLKInput.ulFbDivDecFrac =
-+			cpu_to_le32(bp_params->fractional_feedback_divider);
-+		clk.sPCLKInput.ucPostDiv =
-+			(uint8_t)(bp_params->pixel_clock_post_divider);
-+		clk.sPCLKInput.ucTransmitterID =
-+			bp->cmd_helper->encoder_id_to_atom(
-+				dal_graphics_object_id_get_encoder_id(
-+					bp_params->encoder_object_id));
-+		clk.sPCLKInput.ucEncoderMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+				bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.sPCLKInput.usPixelClock =
-+			cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+			clk.sPCLKInput.ucMiscInfo |=
-+				PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+
-+		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+			clk.sPCLKInput.ucMiscInfo |=
-+				PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+		/* clkV5.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0: 24bpp
-+		 * =1:30bpp, =2:32bpp
-+		 * driver choose program it itself, i.e. here we program it
-+		 * to 888 by default.
-+		 */
-+
-+		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result set_pixel_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	dc_service_memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+		&& bp->cmd_helper->controller_id_to_atom(
-+			bp_params->controller_id, &controller_id)) {
-+		/* Note: VBIOS still wants to use ucCRTC name which is now
-+		 * 1 byte in ULONG
-+		 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-+		 *{
-+		 * target the pixel clock to drive the CRTC timing.
-+		 * ULONG ulPixelClock:24;
-+		 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
-+		 * previous version.
-+		 * ATOM_CRTC1~6, indicate the CRTC controller to
-+		 * ULONG ucCRTC:8;
-+		 * drive the pixel clock. not used for DCPLL case.
-+		 *}CRTC_PIXEL_CLOCK_FREQ;
-+		 *union
-+		 *{
-+		 * pixel clock and CRTC id frequency
-+		 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
-+		 * ULONG ulDispEngClkFreq; dispclk frequency
-+		 *};
-+		 */
-+		clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;
-+		clk.sPCLKInput.ucPpll = (uint8_t) pll_id;
-+		clk.sPCLKInput.ucRefDiv =
-+			(uint8_t) bp_params->reference_divider;
-+		clk.sPCLKInput.usFbDiv =
-+			cpu_to_le16((uint16_t) bp_params->feedback_divider);
-+		clk.sPCLKInput.ulFbDivDecFrac =
-+			cpu_to_le32(bp_params->fractional_feedback_divider);
-+		clk.sPCLKInput.ucPostDiv =
-+			(uint8_t) bp_params->pixel_clock_post_divider;
-+		clk.sPCLKInput.ucTransmitterID =
-+			bp->cmd_helper->encoder_id_to_atom(
-+				dal_graphics_object_id_get_encoder_id(
-+					bp_params->encoder_object_id));
-+		clk.sPCLKInput.ucEncoderMode =
-+			(uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
-+				bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
-+			cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
-+			clk.sPCLKInput.ucMiscInfo |=
-+				PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL;
-+		}
-+
-+		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) {
-+			clk.sPCLKInput.ucMiscInfo |=
-+				PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
-+		}
-+
-+		/* clkV6.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0:
-+		 * 24bpp =1:30bpp, =2:32bpp
-+		 * driver choose program it itself, i.e. here we pass required
-+		 * target rate that includes deep color.
-+		 */
-+
-+		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  ENABLE PIXEL CLOCK SS
-+**
-+********************************************************************************
-+*******************************************************************************/
-+static enum bp_result enable_spread_spectrum_on_ppll_v1(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+static enum bp_result enable_spread_spectrum_on_ppll_v2(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+static enum bp_result enable_spread_spectrum_on_ppll_v3(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+
-+static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) {
-+	case 1:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+			enable_spread_spectrum_on_ppll_v1;
-+		break;
-+	case 2:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+			enable_spread_spectrum_on_ppll_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+			enable_spread_spectrum_on_ppll_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v1(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL params;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	if ((enable == true) && (bp_params->percentage > 0))
-+		params.ucEnable = ATOM_ENABLE;
-+	else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	params.usSpreadSpectrumPercentage =
-+		cpu_to_le16((uint16_t)bp_params->percentage);
-+	params.ucSpreadSpectrumStep =
-+		(uint8_t)bp_params->ver1.step;
-+	params.ucSpreadSpectrumDelay =
-+		(uint8_t)bp_params->ver1.delay;
-+	/* convert back to unit of 10KHz */
-+	params.ucSpreadSpectrumRange =
-+		(uint8_t)(bp_params->ver1.range / 10000);
-+
-+	if (bp_params->flags.EXTERNAL_SS)
-+		params.ucSpreadSpectrumType |= ATOM_EXTERNAL_SS_MASK;
-+
-+	if (bp_params->flags.CENTER_SPREAD)
-+		params.ucSpreadSpectrumType |= ATOM_SS_CENTRE_SPREAD_MODE;
-+
-+	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
-+		params.ucPpll = ATOM_PPLL1;
-+	else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
-+		params.ucPpll = ATOM_PPLL2;
-+	else
-+		BREAK_TO_DEBUGGER(); /* Unexpected PLL value!! */
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v2(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 params;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P1PLL;
-+	else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P2PLL;
-+	else
-+		BREAK_TO_DEBUGGER(); /* Unexpected PLL value!! */
-+
-+	if ((enable == true) && (bp_params->percentage > 0)) {
-+		params.ucEnable = ATOM_ENABLE;
-+
-+		params.usSpreadSpectrumPercentage =
-+			cpu_to_le16((uint16_t)(bp_params->percentage));
-+		params.usSpreadSpectrumStep =
-+			cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+
-+		if (bp_params->flags.EXTERNAL_SS)
-+			params.ucSpreadSpectrumType |=
-+				ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD;
-+
-+		if (bp_params->flags.CENTER_SPREAD)
-+			params.ucSpreadSpectrumType |=
-+				ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD;
-+
-+		/* Both amounts need to be left shifted first before bit
-+		 * comparison. Otherwise, the result will always be zero here
-+		 */
-+		params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
-+			((bp_params->ds.feedback_amount <<
-+				ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT) &
-+				ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK) |
-+			((bp_params->ds.nfrac_amount <<
-+				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
-+				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK)));
-+	} else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v3(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 params;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	switch (bp_params->pll_id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		/* ATOM_PPLL_SS_TYPE_V3_P0PLL; this is pixel clock only,
-+		 * not for SI display clock.
-+		 */
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_DCPLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_P1PLL;
-+		break;
-+
-+	case CLOCK_SOURCE_ID_PLL2:
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_P2PLL;
-+		break;
-+
-+	case CLOCK_SOURCE_ID_DCPLL:
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_DCPLL;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		/* Unexpected PLL value!! */
-+		return result;
-+	}
-+
-+	if (enable == true) {
-+		params.ucEnable = ATOM_ENABLE;
-+
-+		params.usSpreadSpectrumAmountFrac =
-+			cpu_to_le16((uint16_t)(bp_params->ds_frac_amount));
-+		params.usSpreadSpectrumStep =
-+			cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+
-+		if (bp_params->flags.EXTERNAL_SS)
-+			params.ucSpreadSpectrumType |=
-+				ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD;
-+		if (bp_params->flags.CENTER_SPREAD)
-+			params.ucSpreadSpectrumType |=
-+				ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD;
-+
-+		/* Both amounts need to be left shifted first before bit
-+		 * comparison. Otherwise, the result will always be zero here
-+		 */
-+		params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
-+			((bp_params->ds.feedback_amount <<
-+				ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT) &
-+				ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK) |
-+			((bp_params->ds.nfrac_amount <<
-+				ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT) &
-+				ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK)));
-+	} else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  ADJUST DISPLAY PLL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result adjust_display_pll_v2(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params);
-+static enum bp_result adjust_display_pll_v3(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params);
-+
-+static void init_adjust_display_pll(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll)) {
-+	case 2:
-+		bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.adjust_display_pll = NULL;
-+		break;
-+	}
-+}
-+
-+static bool adjust_display_pll_bug_patch(ADJUST_DISPLAY_PLL_PARAMETERS *params)
-+{
-+	/* vbios bug: pixel clock should not be doubled for DVO with 24bit
-+	 * interface */
-+	if ((params->ucTransmitterID == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
-+		&& (params->ucDVOConfig == DVO_ENCODER_CONFIG_24BIT))
-+		/* the current pixel clock is good. no adjustment is required */
-+		return true;
-+	return false;
-+}
-+
-+static enum bp_result adjust_display_pll_v2(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ADJUST_DISPLAY_PLL_PS_ALLOCATION params = { 0 };
-+
-+	/* We need to convert from KHz units into 10KHz units and then convert
-+	 * output pixel clock back 10KHz-->KHz */
-+	uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
-+
-+	params.usPixelClock = cpu_to_le16((uint16_t)(pixel_clock_10KHz_in));
-+	params.ucTransmitterID =
-+		bp->cmd_helper->encoder_id_to_atom(
-+			dal_graphics_object_id_get_encoder_id(
-+				bp_params->encoder_object_id));
-+	params.ucEncodeMode =
-+		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+			bp_params->signal_type, false);
-+	params.ucDVOConfig = (uint8_t)(bp_params->dvo_config);
-+
-+	if (adjust_display_pll_bug_patch(&params)
-+		|| EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
-+		/* Convert output pixel clock back 10KHz-->KHz: multiply
-+		 * original pixel clock in KHz by ratio
-+		 * [output pxlClk/input pxlClk] */
-+		uint64_t pixel_clock_10KHz_out =
-+				le16_to_cpu((uint64_t)params.usPixelClock);
-+		uint64_t pixel_clock = (uint64_t)bp_params->pixel_clock;
-+
-+		bp_params->adjusted_pixel_clock =
-+			div_u64(pixel_clock * pixel_clock_10KHz_out,
-+				pixel_clock_10KHz_in);
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result adjust_display_pll_v3(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 params;
-+	uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	/* We need to convert from KHz units into 10KHz units and then convert
-+	 * output pixel clock back 10KHz-->KHz */
-+	params.sInput.usPixelClock = cpu_to_le16((uint16_t)pixel_clk_10_kHz_in);
-+	params.sInput.ucTransmitterID =
-+		bp->cmd_helper->encoder_id_to_atom(
-+			dal_graphics_object_id_get_encoder_id(
-+				bp_params->encoder_object_id));
-+	params.sInput.ucEncodeMode =
-+		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+			bp_params->signal_type, false);
-+
-+	if (DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT ==
-+		bp_params->display_pll_config)
-+		params.sInput.ucDispPllConfig =
-+			DISPPLL_CONFIG_DVO_DDR_SPEED |
-+			DISPPLL_CONFIG_DVO_LOW12BIT;
-+	else if (DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT ==
-+		bp_params->display_pll_config)
-+		params.sInput.ucDispPllConfig =
-+			DISPPLL_CONFIG_DVO_DDR_SPEED |
-+			DISPPLL_CONFIG_DVO_UPPER12BIT;
-+	else if (DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT ==
-+		bp_params->display_pll_config)
-+		params.sInput.ucDispPllConfig =
-+			DISPPLL_CONFIG_DVO_DDR_SPEED | DISPPLL_CONFIG_DVO_24BIT;
-+	else
-+		/* this does not mean anything here */
-+		params.sInput.ucDispPllConfig =
-+			(uint8_t)(bp_params->display_pll_config);
-+
-+	if (bp_params->ss_enable == true)
-+		params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
-+
-+	if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
-+		params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
-+
-+	if (EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
-+		/* Convert output pixel clock back 10KHz-->KHz: multiply
-+		 * original pixel clock in KHz by ratio
-+		 * [output pxlClk/input pxlClk] */
-+		uint64_t pixel_clk_10_khz_out =
-+			(uint64_t)le32_to_cpu(params.sOutput.ulDispPllFreq);
-+		uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
-+
-+		if (pixel_clk_10_kHz_in != 0) {
-+			bp_params->adjusted_pixel_clock =
-+				div_u64(pixel_clk * pixel_clk_10_khz_out,
-+					pixel_clk_10_kHz_in);
-+		} else {
-+			bp_params->adjusted_pixel_clock = 0;
-+			BREAK_TO_DEBUGGER();
-+		}
-+
-+		bp_params->reference_divider = params.sOutput.ucRefDiv;
-+		bp_params->pixel_clock_post_divider = params.sOutput.ucPostDiv;
-+
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  DAC ENCODER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result dac1_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard);
-+static enum bp_result dac2_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard);
-+
-+static void init_dac_encoder_control(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1EncoderControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac1_encoder_control = dac1_encoder_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac1_encoder_control = NULL;
-+		break;
-+	}
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2EncoderControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac2_encoder_control = dac2_encoder_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac2_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static void dac_encoder_control_prepare_params(
-+	DAC_ENCODER_CONTROL_PS_ALLOCATION *params,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard)
-+{
-+	params->ucDacStandard = dac_standard;
-+	if (enable)
-+		params->ucAction = ATOM_ENABLE;
-+	else
-+		params->ucAction = ATOM_DISABLE;
-+
-+	/* We need to convert from KHz units into 10KHz units
-+	 * it looks as if the TvControl do not care about pixel clock
-+	 */
-+	params->usPixelClock = cpu_to_le16((uint16_t)(pixel_clock / 10));
-+}
-+
-+static enum bp_result dac1_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DAC_ENCODER_CONTROL_PS_ALLOCATION params;
-+
-+	dac_encoder_control_prepare_params(
-+		&params,
-+		enable,
-+		pixel_clock,
-+		dac_standard);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC1EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result dac2_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DAC_ENCODER_CONTROL_PS_ALLOCATION params;
-+
-+	dac_encoder_control_prepare_params(
-+		&params,
-+		enable,
-+		pixel_clock,
-+		dac_standard);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC2EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  DAC OUTPUT CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+static enum bp_result dac1_output_control_v1(
-+	struct bios_parser *bp,
-+	bool enable);
-+static enum bp_result dac2_output_control_v1(
-+	struct bios_parser *bp,
-+	bool enable);
-+
-+static void init_dac_output_control(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1OutputControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac1_output_control = dac1_output_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac1_output_control = NULL;
-+		break;
-+	}
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2OutputControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac2_output_control = dac2_output_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac2_output_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result dac1_output_control_v1(
-+		struct bios_parser *bp, bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-+
-+	if (enable)
-+		params.ucAction = ATOM_ENABLE;
-+	else
-+		params.ucAction = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC1OutputControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result dac2_output_control_v1(
-+		struct bios_parser *bp, bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-+
-+	if (enable)
-+		params.ucAction = ATOM_ENABLE;
-+	else
-+		params.ucAction = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC2OutputControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  DAC LOAD DETECTION
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum signal_type dac_load_detection_v3(
-+	struct bios_parser *bp,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type display_signal);
-+
-+static void init_dac_load_detection(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC_LoadDetection)) {
-+	case 3:
-+		bp->cmd_tbl.dac_load_detection = dac_load_detection_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac_load_detection = NULL;
-+		break;
-+	}
-+}
-+
-+static enum signal_type dac_load_detection_v3(
-+	struct bios_parser *bp,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type display_signal)
-+{
-+	DAC_LOAD_DETECTION_PS_ALLOCATION params;
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	/* load detection is cupported for CRT, TV and CV */
-+	switch (display_signal) {
-+	case SIGNAL_TYPE_RGB:
-+		switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+		case ENCODER_ID_INTERNAL_DAC1:
-+		case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+			params.sDacload.usDeviceID =
-+				cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
-+			break;
-+		case ENCODER_ID_INTERNAL_DAC2:
-+		case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+			params.sDacload.usDeviceID =
-+				cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		return signal;
-+	}
-+
-+	/* set the encoder to detect on */
-+	switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+	case ENCODER_ID_INTERNAL_DAC1:
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+		params.sDacload.ucDacType = ATOM_DAC_A;
-+		break;
-+	case ENCODER_ID_INTERNAL_DAC2:
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+		params.sDacload.ucDacType = ATOM_DAC_B;
-+		break;
-+	case ENCODER_ID_EXTERNAL_CH7303:
-+		params.sDacload.ucDacType = ATOM_EXT_DAC;
-+		break;
-+	default:
-+		return signal;
-+	}
-+
-+	if (!EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params))
-+		return signal;
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	signal = bp->bios_helper->detect_sink(
-+		bp->ctx,
-+		encoder,
-+		connector,
-+		display_signal);
-+#else
-+	BREAK_TO_DEBUGGER(); /* VBios is needed */
-+#endif
-+
-+	return signal;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                 BLANK CRTC
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result blank_crtc_v1(
-+		struct bios_parser *bp,
-+		struct bp_blank_crtc_parameters *bp_params,
-+		bool blank);
-+
-+static void init_blank_crtc(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(BlankCRTC)) {
-+	case 1:
-+		bp->cmd_tbl.blank_crtc = blank_crtc_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.blank_crtc = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result blank_crtc_v1(
-+		struct bios_parser *bp,
-+		struct bp_blank_crtc_parameters *bp_params,
-+		bool blank)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	BLANK_CRTC_PARAMETERS params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-+			&atom_controller_id)) {
-+		params.ucCRTC = (uint8_t)atom_controller_id;
-+
-+		if (blank)
-+			params.ucBlanking = ATOM_BLANKING;
-+		else
-+			params.ucBlanking = ATOM_BLANKING_OFF;
-+		params.usBlackColorRCr =
-+			cpu_to_le16((uint16_t)bp_params->black_color_rcr);
-+		params.usBlackColorGY =
-+			cpu_to_le16((uint16_t)bp_params->black_color_gy);
-+		params.usBlackColorBCb =
-+			cpu_to_le16((uint16_t)bp_params->black_color_bcb);
-+
-+		if (EXEC_BIOS_CMD_TABLE(BlankCRTC, params))
-+			result = BP_RESULT_OK;
-+	} else
-+		/* Not support more than two CRTC as current ASIC, update this
-+		 * if needed.
-+		 */
-+		result = BP_RESULT_BADINPUT;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  SET CRTC TIMING
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+static enum bp_result set_crtc_timing_v1(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+
-+static void init_set_crtc_timing(struct bios_parser *bp)
-+{
-+	uint32_t dtd_version =
-+		BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_UsingDTDTiming);
-+	if (dtd_version > 2)
-+		switch (dtd_version) {
-+		case 3:
-+			bp->cmd_tbl.set_crtc_timing =
-+				set_crtc_using_dtd_timing_v3;
-+			break;
-+		default:
-+			bp->cmd_tbl.set_crtc_timing = NULL;
-+			break;
-+		}
-+	else
-+		switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_Timing)) {
-+		case 1:
-+			bp->cmd_tbl.set_crtc_timing = set_crtc_timing_v1;
-+			break;
-+		default:
-+			bp->cmd_tbl.set_crtc_timing = NULL;
-+			break;
-+		}
-+}
-+
-+static enum bp_result set_crtc_timing_v1(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(
-+		bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+
-+	params.usH_Total = cpu_to_le16((uint16_t)(bp_params->h_total));
-+	params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable));
-+	params.usH_SyncStart = cpu_to_le16((uint16_t)(bp_params->h_sync_start));
-+	params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width));
-+	params.usV_Total = cpu_to_le16((uint16_t)(bp_params->v_total));
-+	params.usV_Disp = cpu_to_le16((uint16_t)(bp_params->v_addressable));
-+	params.usV_SyncStart =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_start));
-+	params.usV_SyncWidth =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_width));
-+
-+
-+	/* VBIOS does not expect any value except zero into this call, for
-+	 * underscan use another entry ProgramOverscan call but when mode
-+	 * 1776x1000 with the overscan 72x44 .e.i. 1920x1080 @30 DAL2 is ok,
-+	 * but when same ,but 60 Hz there is corruption
-+	 * DAL1 does not allow the mode 1776x1000@60
-+	 */
-+	params.ucOverscanRight = (uint8_t)bp_params->h_overscan_right;
-+	params.ucOverscanLeft = (uint8_t)bp_params->h_overscan_left;
-+	params.ucOverscanBottom = (uint8_t)bp_params->v_overscan_bottom;
-+	params.ucOverscanTop = (uint8_t)bp_params->v_overscan_top;
-+
-+	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+
-+	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+
-+	if (bp_params->flags.INTERLACE) {
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+
-+		/* original DAL code has this condition to apply tis for
-+		 * non-TV/CV only due to complex MV testing for possible
-+		 * impact
-+		 * if (pACParameters->signal != SignalType_YPbPr &&
-+		 *  pACParameters->signal != SignalType_Composite &&
-+		 *  pACParameters->signal != SignalType_SVideo)
-+		 */
-+		/* HW will deduct 0.5 line from 2nd feild.
-+		 * i.e. for 1080i, it is 2 lines for 1st field, 2.5
-+		 * lines for the 2nd feild. we need input as 5 instead
-+		 * of 4, but it is 4 either from Edid data
-+		 * (spec CEA 861) or CEA timing table.
-+		 */
-+		params.usV_SyncStart =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_start + 1));
-+	}
-+
-+	if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetCRTC_Timing, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_CRTC_USING_DTD_TIMING_PARAMETERS params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(
-+		bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+
-+	/* bios usH_Size wants h addressable size */
-+	params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable);
-+	/* bios usH_Blanking_Time wants borders included in blanking */
-+	params.usH_Blanking_Time =
-+		cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
-+	/* bios usV_Size wants v addressable size */
-+	params.usV_Size = cpu_to_le16((uint16_t)bp_params->v_addressable);
-+	/* bios usV_Blanking_Time wants borders included in blanking */
-+	params.usV_Blanking_Time =
-+		cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
-+	/* bios usHSyncOffset is the offset from the end of h addressable,
-+	 * our horizontalSyncStart is the offset from the beginning
-+	 * of h addressable */
-+	params.usH_SyncOffset =
-+		cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
-+	params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
-+	/* bios usHSyncOffset is the offset from the end of v addressable,
-+	 * our verticalSyncStart is the offset from the beginning of
-+	 * v addressable */
-+	params.usV_SyncOffset =
-+		cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
-+	params.usV_SyncWidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
-+
-+	/* we assume that overscan from original timing does not get bigger
-+	 * than 255
-+	 * we will program all the borders in the Set CRTC Overscan call below
-+	 */
-+
-+	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+
-+	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+
-+
-+	if (bp_params->flags.INTERLACE)	{
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+
-+		/* original DAL code has this condition to apply this
-+		 * for non-TV/CV only
-+		 * due to complex MV testing for possible impact
-+		 * if ( pACParameters->signal != SignalType_YPbPr &&
-+		 *  pACParameters->signal != SignalType_Composite &&
-+		 *  pACParameters->signal != SignalType_SVideo)
-+		 */
-+		{
-+			/* HW will deduct 0.5 line from 2nd feild.
-+			 * i.e. for 1080i, it is 2 lines for 1st field,
-+			 * 2.5 lines for the 2nd feild. we need input as 5
-+			 * instead of 4.
-+			 * but it is 4 either from Edid data (spec CEA 861)
-+			 * or CEA timing table.
-+			 */
-+			params.usV_SyncOffset =
-+				cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1);
-+
-+		}
-+	}
-+
-+	if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+		params.susModeMiscInfo.usAccess =
-+			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetCRTC_UsingDTDTiming, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  SET CRTC OVERSCAN
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_crtc_overscan_v1(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_overscan_parameters *bp_params);
-+
-+static void init_set_crtc_overscan(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_OverScan))	{
-+	case 1:
-+		bp->cmd_tbl.set_crtc_overscan = set_crtc_overscan_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_crtc_overscan = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result set_crtc_overscan_v1(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_overscan_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_CRTC_OVERSCAN_PARAMETERS params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(
-+		bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	params.usOverscanRight =
-+			cpu_to_le16((uint16_t)bp_params->h_overscan_right);
-+	params.usOverscanLeft =
-+			cpu_to_le16((uint16_t)bp_params->h_overscan_left);
-+	params.usOverscanBottom =
-+			cpu_to_le16((uint16_t)bp_params->v_overscan_bottom);
-+	params.usOverscanTop =
-+			cpu_to_le16((uint16_t)bp_params->v_overscan_top);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetCRTC_OverScan, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  SELECT CRTC SOURCE
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result select_crtc_source_v2(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params);
-+static enum bp_result select_crtc_source_v3(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params);
-+
-+static void init_select_crtc_source(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {
-+	case 2:
-+		bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.select_crtc_source = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result select_crtc_source_v2(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SELECT_CRTC_SOURCE_PARAMETERS_V2 params;
-+	uint8_t atom_controller_id;
-+	uint32_t atom_engine_id;
-+	enum signal_type s = bp_params->signal;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	/* set controller id */
-+	if (bp->cmd_helper->controller_id_to_atom(
-+		bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+	else
-+		return BP_RESULT_FAILURE;
-+
-+	/* set encoder id */
-+	if (bp->cmd_helper->engine_bp_to_atom(
-+		bp_params->engine_id, &atom_engine_id))
-+		params.ucEncoderID = (uint8_t)atom_engine_id;
-+	else
-+		return BP_RESULT_FAILURE;
-+
-+	if (SIGNAL_TYPE_EDP == s ||
-+			(SIGNAL_TYPE_DISPLAY_PORT == s &&
-+				SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+		s = SIGNAL_TYPE_LVDS;
-+
-+	params.ucEncodeMode =
-+		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+			s, bp_params->enable_dp_audio);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result select_crtc_source_v3(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	bool result = BP_RESULT_FAILURE;
-+	SELECT_CRTC_SOURCE_PARAMETERS_V3 params;
-+	uint8_t atom_controller_id;
-+	uint32_t atom_engine_id;
-+	enum signal_type s = bp_params->signal;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-+			&atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+	else
-+		return result;
-+
-+	if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
-+			&atom_engine_id))
-+		params.ucEncoderID = (uint8_t)atom_engine_id;
-+	else
-+		return result;
-+
-+	if (SIGNAL_TYPE_EDP == s ||
-+			(SIGNAL_TYPE_DISPLAY_PORT == s &&
-+			SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+		s = SIGNAL_TYPE_LVDS;
-+
-+	params.ucEncodeMode =
-+		bp->cmd_helper->encoder_mode_bp_to_atom(
-+			s, bp_params->enable_dp_audio);
-+	/* Needed for VBIOS Random Spatial Dithering feature */
-+	params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  ENABLE CRTC
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result enable_crtc_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable);
-+
-+static void init_enable_crtc(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTC)) {
-+	case 1:
-+		bp->cmd_tbl.enable_crtc = enable_crtc_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_crtc = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_crtc_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable)
-+{
-+	bool result = BP_RESULT_FAILURE;
-+	ENABLE_CRTC_PARAMETERS params = {0};
-+	uint8_t id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
-+		params.ucCRTC = id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	if (enable)
-+		params.ucEnable = ATOM_ENABLE;
-+	else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableCRTC, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  ENABLE CRTC MEM REQ
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result enable_crtc_mem_req_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable);
-+
-+static void init_enable_crtc_mem_req(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTCMemReq)) {
-+	case 1:
-+		bp->cmd_tbl.enable_crtc_mem_req = enable_crtc_mem_req_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_crtc_mem_req = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_crtc_mem_req_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable)
-+{
-+	bool result = BP_RESULT_BADINPUT;
-+	ENABLE_CRTC_PARAMETERS params = {0};
-+	uint8_t id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) {
-+		params.ucCRTC = id;
-+
-+		if (enable)
-+			params.ucEnable = ATOM_ENABLE;
-+		else
-+			params.ucEnable = ATOM_DISABLE;
-+
-+		if (EXEC_BIOS_CMD_TABLE(EnableCRTCMemReq, params))
-+			result = BP_RESULT_OK;
-+		else
-+			result = BP_RESULT_FAILURE;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  DISPLAY PLL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result program_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result program_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_program_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
-+	case 5:
-+		bp->cmd_tbl.program_clock = program_clock_v5;
-+		break;
-+	case 6:
-+		bp->cmd_tbl.program_clock = program_clock_v6;
-+		break;
-+	default:
-+		bp->cmd_tbl.program_clock = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result program_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 params;
-+	uint32_t atom_pll_id;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+	if (!bp->cmd_helper->clock_source_id_to_atom(
-+		bp_params->pll_id, &atom_pll_id)) {
-+		BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
-+	params.sPCLKInput.usPixelClock =
-+		cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
-+	params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
-+
-+	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+		params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result program_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 params;
-+	uint32_t atom_pll_id;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	if (!bp->cmd_helper->clock_source_id_to_atom(
-+		bp_params->pll_id, &atom_pll_id)) {
-+		BREAK_TO_DEBUGGER(); /*Invalid Input!!*/
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
-+	params.sPCLKInput.ulDispEngClkFreq =
-+		cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+		params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) {
-+		/* True display clock is returned by VBIOS if DFS bypass
-+		 * is enabled. */
-+		bp_params->dfs_bypass_display_clock =
-+			(uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10);
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                 COMPUTE MEMORY ENGINE PLL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result compute_memore_engine_pll_v4(
-+	struct bios_parser *bp,
-+	struct bp_display_clock_parameters *bp_params);
-+
-+static void init_compute_memore_engine_pll(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(ComputeMemoryEnginePLL)) {
-+	case 4:
-+		bp->cmd_tbl.compute_memore_engine_pll =
-+			compute_memore_engine_pll_v4;
-+		break;
-+	default:
-+		bp->cmd_tbl.compute_memore_engine_pll = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result compute_memore_engine_pll_v4(
-+	struct bios_parser *bp,
-+	struct bp_display_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
-+
-+	/* Initialize this to the target clock in case this call fails */
-+	bp_params->actual_display_clock = bp_params->target_display_clock;
-+
-+	if (EXEC_BIOS_CMD_TABLE(ComputeMemoryEnginePLL, params)) {
-+		/* Convert from 10KHz units back to KHz */
-+		bp_params->actual_display_clock =
-+				le32_to_cpu(params.ulClock) * 10;
-+		bp_params->actual_post_divider_id = params.ucPostDiv;
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  EXTERNAL ENCODER CONTROL
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result external_encoder_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl);
-+
-+static void init_external_encoder_control(
-+	struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(ExternalEncoderControl)) {
-+	case 3:
-+		bp->cmd_tbl.external_encoder_control =
-+			external_encoder_control_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.external_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result external_encoder_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	/* we need use _PS_Alloc struct */
-+	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 params;
-+	EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 *cntl_params;
-+	struct graphics_object_id encoder;
-+	bool is_input_signal_dp = false;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	cntl_params = &params.sExtEncoder;
-+
-+	encoder = cntl->encoder_id;
-+
-+	/* check if encoder supports external encoder control table */
-+	switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		is_input_signal_dp = true;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	/* Fill information based on the action
-+	 *
-+	 * Bit[6:4]: indicate external encoder, applied to all functions.
-+	 * =0: external encoder1, mapped to external encoder enum id1
-+	 * =1: external encoder2, mapped to external encoder enum id2
-+	 *
-+	 * enum ObjectEnumId
-+	 * {
-+	 *  EnumId_Unknown = 0,
-+	 *  EnumId_1,
-+	 *  EnumId_2,
-+	 * };
-+	 */
-+	cntl_params->ucConfig = (uint8_t)((encoder.enum_id - 1) << 4);
-+
-+	switch (cntl->action) {
-+	case EXTERNAL_ENCODER_CONTROL_INIT:
-+		/* output display connector type. Only valid in encoder
-+		 * initialization */
-+		cntl_params->usConnectorId =
-+			cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
-+		break;
-+	case EXTERNAL_ENCODER_CONTROL_SETUP:
-+		/* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in
-+		 * 10KHz
-+		 * output display device pixel clock frequency in unit of 10KHz.
-+		 * Only valid in setup and enableoutput
-+		 */
-+		cntl_params->usPixelClock =
-+			cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		/* Indicate display output signal type drive by external
-+		 * encoder, only valid in setup and enableoutput */
-+		cntl_params->ucEncoderMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+				cntl->signal, false);
-+
-+		if (is_input_signal_dp) {
-+			/* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz,
-+			 * only valid in encoder setup with DP mode. */
-+			if (LINK_RATE_HIGH == cntl->link_rate)
-+				cntl_params->ucConfig |= 1;
-+			/* output color depth Indicate encoder data bpc format
-+			 * in DP mode, only valid in encoder setup in DP mode.
-+			 */
-+			cntl_params->ucBitPerColor =
-+				(uint8_t)(cntl->color_depth);
-+		}
-+		/* Indicate how many lanes used by external encoder, only valid
-+		 * in encoder setup and enableoutput. */
-+		cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number);
-+		break;
-+	case EXTERNAL_ENCODER_CONTROL_ENABLE:
-+		cntl_params->usPixelClock =
-+			cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		cntl_params->ucEncoderMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+				cntl->signal, false);
-+		cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	cntl_params->ucAction = (uint8_t)cntl->action;
-+
-+	if (EXEC_BIOS_CMD_TABLE(ExternalEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	if (EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT == cntl->action) {
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+		if (BP_RESULT_OK == result)
-+			/* get VBIOS result from scratch register.
-+			 * ExternalEncoderControl runs detection and save result
-+			 * in BIOS scratch registers. */
-+			cntl->signal = bp->bios_helper->detect_sink(
-+				bp->ctx,
-+				encoder,
-+				cntl->connector_obj_id,
-+				cntl->signal);
-+		else/* BIOS table does not work. */
-+#endif
-+		{
-+			BREAK_TO_DEBUGGER(); /* VBios is needed */
-+			cntl->signal = SIGNAL_TYPE_NONE;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+********************************************************************************
-+**
-+**                  ENABLE DISPLAY POWER GATING
-+**
-+********************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+	struct bios_parser *bp,
-+	enum controller_id crtc_id,
-+	enum bp_pipe_control_action action);
-+
-+static void init_enable_disp_power_gating(
-+	struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating)) {
-+	case 1:
-+		bp->cmd_tbl.enable_disp_power_gating =
-+			enable_disp_power_gating_v2_1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_disp_power_gating = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+	struct bios_parser *bp,
-+	enum controller_id crtc_id,
-+	enum bp_pipe_control_action action)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 params = {0};
-+	uint8_t atom_crtc_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
-+		params.ucDispPipeId = atom_crtc_id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	params.ucEnable =
-+		bp->cmd_helper->disp_power_gating_action_to_atom(action);
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableDispPowerGating, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-new file mode 100644
-index 0000000..814d31f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-@@ -0,0 +1,117 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_H__
-+#define __DAL_COMMAND_TABLE_H__
-+
-+struct bios_parser;
-+struct bp_encoder_control;
-+
-+struct cmd_tbl {
-+	enum bp_result (*dig_encoder_control)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*encoder_control_dig1)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*encoder_control_dig2)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*dvo_encoder_control)(
-+		struct bios_parser *bp,
-+		struct bp_dvo_encoder_control *cntl);
-+	enum bp_result (*transmitter_control)(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *control);
-+	enum bp_result (*set_pixel_clock)(
-+		struct bios_parser *bp,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*enable_spread_spectrum_on_ppll)(
-+		struct bios_parser *bp,
-+		struct bp_spread_spectrum_parameters *bp_params,
-+		bool enable);
-+	enum bp_result (*adjust_display_pll)(
-+		struct bios_parser *bp,
-+		struct bp_adjust_pixel_clock_parameters *bp_params);
-+	enum bp_result (*dac1_encoder_control)(
-+		struct bios_parser *bp,
-+		bool enable,
-+		uint32_t pixel_clock,
-+		uint8_t dac_standard);
-+	enum bp_result (*dac2_encoder_control)(
-+		struct bios_parser *bp,
-+		bool enable,
-+		uint32_t pixel_clock,
-+		uint8_t dac_standard);
-+	enum bp_result (*dac1_output_control)(
-+		struct bios_parser *bp,
-+		bool enable);
-+	enum bp_result (*dac2_output_control)(
-+		struct bios_parser *bp,
-+		bool enable);
-+	enum signal_type (*dac_load_detection)(
-+		struct bios_parser *bp,
-+		struct graphics_object_id encoder,
-+		struct graphics_object_id connector,
-+		enum signal_type display_signal);
-+	enum bp_result (*blank_crtc)(
-+		struct bios_parser *bp,
-+		struct bp_blank_crtc_parameters *bp_params,
-+		bool blank);
-+	enum bp_result (*set_crtc_timing)(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+	enum bp_result (*set_crtc_overscan)(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_overscan_parameters *bp_params);
-+	enum bp_result (*select_crtc_source)(
-+		struct bios_parser *bp,
-+		struct bp_crtc_source_select *bp_params);
-+	enum bp_result (*enable_crtc)(
-+		struct bios_parser *bp,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*enable_crtc_mem_req)(
-+		struct bios_parser *bp,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*program_clock)(
-+		struct bios_parser *bp,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*compute_memore_engine_pll)(
-+		struct bios_parser *bp,
-+		struct bp_display_clock_parameters *bp_params);
-+	enum bp_result (*external_encoder_control)(
-+			struct bios_parser *bp,
-+			struct bp_external_encoder_control *cntl);
-+	enum bp_result (*enable_disp_power_gating)(
-+		struct bios_parser *bp,
-+		enum controller_id crtc_id,
-+		enum bp_pipe_control_action action);
-+};
-+
-+void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-new file mode 100644
-index 0000000..dad1426
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -0,0 +1,315 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+
-+#include "command_table_helper.h"
-+
-+bool dal_bios_parser_init_cmd_tbl_helper(
-+	const struct command_table_helper **h,
-+	enum dce_version dce)
-+{
-+	switch (dce) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		*h = dal_cmd_tbl_helper_dce110_get_table();
-+		return true;
-+
-+#endif
-+	default:
-+		/* Unsupported DCE */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+/* real implementations */
-+
-+bool dal_cmd_table_helper_controller_id_to_atom(
-+	enum controller_id id,
-+	uint8_t *atom_id)
-+{
-+	if (atom_id == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (id) {
-+	case CONTROLLER_ID_D0:
-+		*atom_id = ATOM_CRTC1;
-+		return true;
-+	case CONTROLLER_ID_D1:
-+		*atom_id = ATOM_CRTC2;
-+		return true;
-+	case CONTROLLER_ID_D2:
-+		*atom_id = ATOM_CRTC3;
-+		return true;
-+	case CONTROLLER_ID_D3:
-+		*atom_id = ATOM_CRTC4;
-+		return true;
-+	case CONTROLLER_ID_D4:
-+		*atom_id = ATOM_CRTC5;
-+		return true;
-+	case CONTROLLER_ID_D5:
-+		*atom_id = ATOM_CRTC6;
-+		return true;
-+	case CONTROLLER_ID_UNDERLAY0:
-+		*atom_id = ATOM_UNDERLAY_PIPE0;
-+		return true;
-+	case CONTROLLER_ID_UNDEFINED:
-+		*atom_id = ATOM_CRTC_INVALID;
-+		return true;
-+	default:
-+		/* Wrong controller id */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+/**
-+* translate_transmitter_bp_to_atom
-+*
-+* @brief
-+*  Translate the Transmitter to the corresponding ATOM BIOS value
-+*
-+* @param
-+*   input transmitter
-+*   output digitalTransmitter
-+*    // =00: Digital Transmitter1 ( UNIPHY linkAB )
-+*    // =01: Digital Transmitter2 ( UNIPHY linkCD )
-+*    // =02: Digital Transmitter3 ( UNIPHY linkEF )
-+*/
-+uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
-+	enum transmitter t)
-+{
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		return 0;
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+		return 1;
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+		return 2;
-+	default:
-+		/* Invalid Transmitter Type! */
-+		BREAK_TO_DEBUGGER();
-+		return 0;
-+	}
-+}
-+
-+uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
-+	enum signal_type s,
-+	bool enable_dp_audio)
-+{
-+	switch (s) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		return ATOM_ENCODER_MODE_DVI;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		return ATOM_ENCODER_MODE_HDMI;
-+	case SIGNAL_TYPE_LVDS:
-+		return ATOM_ENCODER_MODE_LVDS;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		if (enable_dp_audio)
-+			return ATOM_ENCODER_MODE_DP_AUDIO;
-+		else
-+			return ATOM_ENCODER_MODE_DP;
-+	case SIGNAL_TYPE_RGB:
-+		return ATOM_ENCODER_MODE_CRT;
-+	default:
-+		return ATOM_ENCODER_MODE_CRT;
-+	}
-+}
-+
-+void dal_cmd_table_helper_assign_control_parameter(
-+	const struct command_table_helper *h,
-+	struct bp_encoder_control *control,
-+	DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param)
-+{
-+	/* there are three transmitter blocks, each one has two links 4-lanes
-+	 * each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in
-+	 * each transmitter block B, D and F as link 1, third transmitter block
-+	 * has non splitable links (UniphyE and UniphyF can not be configured
-+	 * separately to drive two different streams)
-+	 */
-+	if ((control->transmitter == TRANSMITTER_UNIPHY_B) ||
-+		(control->transmitter == TRANSMITTER_UNIPHY_D) ||
-+		(control->transmitter == TRANSMITTER_UNIPHY_F)) {
-+		/* Bit2: Link Select
-+		 * =0: PHY linkA/C/E
-+		 * =1: PHY linkB/D/F
-+		 */
-+		ctrl_param->acConfig.ucLinkSel = 1;
-+	}
-+
-+	/* Bit[4:3]: Transmitter Selection
-+	 * =00: Digital Transmitter1 ( UNIPHY linkAB )
-+	 * =01: Digital Transmitter2 ( UNIPHY linkCD )
-+	 * =02: Digital Transmitter3 ( UNIPHY linkEF )
-+	 * =03: Reserved
-+	 */
-+	ctrl_param->acConfig.ucTransmitterSel =
-+		(uint8_t)(h->transmitter_bp_to_atom(control->transmitter));
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	ctrl_param->ucAction = h->encoder_action_to_atom(control->action);
-+	ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10));
-+	ctrl_param->ucEncoderMode =
-+		(uint8_t)(h->encoder_mode_bp_to_atom(
-+			control->signal, control->enable_dp_audio));
-+	ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);
-+}
-+
-+bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
-+	enum clock_source_id id,
-+	uint32_t *ref_clk_src_id)
-+{
-+	if (ref_clk_src_id == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL1:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_DCPLL:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
-+		return true;
-+	case CLOCK_SOURCE_ID_UNDEFINED:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
-+		return true;
-+	default:
-+		/* Unsupported clock source id */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+uint8_t dal_cmd_table_helper_encoder_id_to_atom(
-+	enum encoder_id id)
-+{
-+	switch (id) {
-+	case ENCODER_ID_INTERNAL_LVDS:
-+		return ENCODER_OBJECT_ID_INTERNAL_LVDS;
-+	case ENCODER_ID_INTERNAL_TMDS1:
-+		return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
-+	case ENCODER_ID_INTERNAL_TMDS2:
-+		return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
-+	case ENCODER_ID_INTERNAL_DAC1:
-+		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
-+	case ENCODER_ID_INTERNAL_DAC2:
-+		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
-+	case ENCODER_ID_INTERNAL_SDVOA:
-+		return ENCODER_OBJECT_ID_INTERNAL_SDVOA;
-+	case ENCODER_ID_INTERNAL_SDVOB:
-+		return ENCODER_OBJECT_ID_INTERNAL_SDVOB;
-+	case ENCODER_ID_EXTERNAL_SI170B:
-+		return ENCODER_OBJECT_ID_SI170B;
-+	case ENCODER_ID_EXTERNAL_CH7303:
-+		return ENCODER_OBJECT_ID_CH7303;
-+	case ENCODER_ID_EXTERNAL_CH7301:
-+		return ENCODER_OBJECT_ID_CH7301;
-+	case ENCODER_ID_INTERNAL_DVO1:
-+		return ENCODER_OBJECT_ID_INTERNAL_DVO1;
-+	case ENCODER_ID_EXTERNAL_SDVOA:
-+		return ENCODER_OBJECT_ID_EXTERNAL_SDVOA;
-+	case ENCODER_ID_EXTERNAL_SDVOB:
-+		return ENCODER_OBJECT_ID_EXTERNAL_SDVOB;
-+	case ENCODER_ID_EXTERNAL_TITFP513:
-+		return ENCODER_OBJECT_ID_TITFP513;
-+	case ENCODER_ID_INTERNAL_LVTM1:
-+		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
-+	case ENCODER_ID_EXTERNAL_VT1623:
-+		return ENCODER_OBJECT_ID_VT1623;
-+	case ENCODER_ID_EXTERNAL_SI1930:
-+		return ENCODER_OBJECT_ID_HDMI_SI1930;
-+	case ENCODER_ID_INTERNAL_HDMI:
-+		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		return ENCODER_OBJECT_ID_TRAVIS;
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+		return ENCODER_OBJECT_ID_NUTMEG;
-+	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DVO1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
-+	case ENCODER_ID_EXTERNAL_SI178:
-+		return ENCODER_OBJECT_ID_SI178;
-+	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
-+		return ENCODER_OBJECT_ID_MVPU_FPGA;
-+	case ENCODER_ID_INTERNAL_DDI:
-+		return ENCODER_OBJECT_ID_INTERNAL_DDI;
-+	case ENCODER_ID_EXTERNAL_VT1625:
-+		return ENCODER_OBJECT_ID_VT1625;
-+	case ENCODER_ID_EXTERNAL_SI1932:
-+		return ENCODER_OBJECT_ID_HDMI_SI1932;
-+	case ENCODER_ID_EXTERNAL_AN9801:
-+		return ENCODER_OBJECT_ID_DP_AN9801;
-+	case ENCODER_ID_EXTERNAL_DP501:
-+		return ENCODER_OBJECT_ID_DP_DP501;
-+	case ENCODER_ID_INTERNAL_UNIPHY:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
-+	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
-+	case ENCODER_ID_INTERNAL_UNIPHY1:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
-+	case ENCODER_ID_INTERNAL_UNIPHY2:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
-+	case ENCODER_ID_INTERNAL_UNIPHY3:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
-+	case ENCODER_ID_INTERNAL_WIRELESS:
-+		return ENCODER_OBJECT_ID_INTERNAL_VCE;
-+	case ENCODER_ID_EXTERNAL_GENERIC_DVO:
-+		return ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO;
-+	case ENCODER_ID_UNKNOWN:
-+		return ENCODER_OBJECT_ID_NONE;
-+	default:
-+		/* Invalid encoder id */
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_OBJECT_ID_NONE;
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-new file mode 100644
-index 0000000..e5c00de
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-@@ -0,0 +1,87 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_H__
-+#define __DAL_COMMAND_TABLE_HELPER_H__
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/command_table_helper_dce110.h"
-+#endif
-+
-+struct command_table_helper {
-+	bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
-+	uint8_t (*encoder_action_to_atom)(
-+			enum bp_encoder_control_action action);
-+	uint32_t (*encoder_mode_bp_to_atom)(enum signal_type s,
-+			bool enable_dp_audio);
-+	bool (*engine_bp_to_atom)(enum engine_id engine_id,
-+			uint32_t *atom_engine_id);
-+	void (*assign_control_parameter)(
-+			const struct command_table_helper *h,
-+			struct bp_encoder_control *control,
-+			DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param);
-+	bool (*clock_source_id_to_atom)(enum clock_source_id id,
-+			uint32_t *atom_pll_id);
-+	bool (*clock_source_id_to_ref_clk_src)(
-+			enum clock_source_id id,
-+			uint32_t *ref_clk_src_id);
-+	uint8_t (*transmitter_bp_to_atom)(enum transmitter t);
-+	uint8_t (*encoder_id_to_atom)(enum encoder_id id);
-+	uint8_t (*clock_source_id_to_atom_phy_clk_src_id)(
-+			enum clock_source_id id);
-+	uint8_t (*signal_type_to_atom_dig_mode)(enum signal_type s);
-+	uint8_t (*hpd_sel_to_atom)(enum hpd_source_id id);
-+	uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
-+	uint8_t (*phy_id_to_atom)(enum transmitter t);
-+	uint8_t (*disp_power_gating_action_to_atom)(
-+			enum bp_pipe_control_action action);
-+};
-+
-+bool dal_bios_parser_init_cmd_tbl_helper(const struct command_table_helper **h,
-+	enum dce_version dce);
-+
-+bool dal_cmd_table_helper_controller_id_to_atom(
-+	enum controller_id id,
-+	uint8_t *atom_id);
-+
-+uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
-+	enum signal_type s,
-+	bool enable_dp_audio);
-+
-+void dal_cmd_table_helper_assign_control_parameter(
-+	const struct command_table_helper *h,
-+	struct bp_encoder_control *control,
-+DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param);
-+
-+bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
-+	enum clock_source_id id,
-+	uint32_t *ref_clk_src_id);
-+
-+uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
-+	enum transmitter t);
-+
-+uint8_t dal_cmd_table_helper_encoder_id_to_atom(
-+	enum encoder_id id);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-new file mode 100644
-index 0000000..2cc2d2d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -0,0 +1,484 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+#include "include/logger_interface.h"
-+
-+#include "../bios_parser_helper.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "bif/bif_5_1_d.h"
-+
-+/**
-+ * set_scratch_acc_mode_change
-+ *
-+ * @brief
-+ *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-+ *  VGA/non-Accelerated mode is set
-+ *
-+ * @param
-+ *  struct dc_context *ctx - [in] DAL context
-+ */
-+static void set_scratch_acc_mode_change(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	value |= ATOM_S6_ACC_MODE;
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+/*
-+ * set_scratch_active_and_requested
-+ *
-+ * @brief
-+ * Set VBIOS scratch pad registers about active and requested displays
-+ *
-+ * @param
-+ * struct dc_context *ctx - [in] DAL context for register accessing
-+ * struct vbios_helper_data *d - [in] values to write
-+ */
-+static void set_scratch_active_and_requested(
-+	struct dc_context *ctx,
-+	struct vbios_helper_data *d)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_3;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
-+	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_6;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S6_ACC_REQ_MASK;
-+	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_5;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
-+	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	d->active = 0;
-+	d->requested = 0;
-+}
-+
-+/**
-+ * get LCD Scale Mode from VBIOS scratch register
-+ */
-+static enum lcd_scale get_scratch_lcd_scale(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	if (value & ATOM_S6_REQ_LCD_EXPANSION_FULL)
-+		return LCD_SCALE_FULLPANEL;
-+	else if (value & ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO)
-+		return LCD_SCALE_ASPECTRATIO;
-+	else
-+		return LCD_SCALE_NONE;
-+}
-+
-+/**
-+ * prepare_scratch_active_and_requested
-+ *
-+ * @brief
-+ *  prepare and update VBIOS scratch pad registers about active and requested
-+ *  displays
-+ *
-+ * @param
-+ * data - helper's shared data
-+ * enum controller_ild - controller Id
-+ * enum signal_type - signal type used on display
-+ * const struct connector_device_tag_info* - pointer to display type and enum id
-+ */
-+static void prepare_scratch_active_and_requested(
-+	struct dc_context *ctx,
-+	struct vbios_helper_data *data,
-+	enum controller_id id,
-+	enum signal_type s,
-+	const struct connector_device_tag_info *dev_tag)
-+{
-+	switch (s) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_DFP)
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP1;
-+				data->active |= ATOM_S3_DFP1_ACTIVE;
-+				break;
-+			case 2:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP2;
-+				data->active |= ATOM_S3_DFP2_ACTIVE;
-+				break;
-+			case 3:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP3;
-+				data->active |= ATOM_S3_DFP3_ACTIVE;
-+				break;
-+			case 4:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP4;
-+				data->active |= ATOM_S3_DFP4_ACTIVE;
-+				break;
-+			case 5:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP5;
-+				data->active |= ATOM_S3_DFP5_ACTIVE;
-+				break;
-+			case 6:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP6;
-+				data->active |= ATOM_S3_DFP6_ACTIVE;
-+				break;
-+			default:
-+				break;
-+			}
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_EDP:
-+		data->requested |= ATOM_S6_ACC_REQ_LCD1;
-+		data->active |= ATOM_S3_LCD1_ACTIVE;
-+		break;
-+	case SIGNAL_TYPE_RGB:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_CRT)
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				data->requested |= ATOM_S6_ACC_REQ_CRT1;
-+				data->active |= ATOM_S3_CRT1_ACTIVE;
-+				break;
-+			case 2:
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_BIOS,
-+					LOG_MINOR_COMPONENT_BIOS,
-+					"%s: DAL does not support DAC2!\n",
-+					__func__);
-+				break;
-+			default:
-+				break;
-+			}
-+		break;
-+	default:
-+		dal_logger_write(ctx->logger,
-+				LOG_MAJOR_BIOS,
-+				LOG_MINOR_COMPONENT_BIOS,
-+				"%s: No such signal!\n",
-+				__func__);
-+		break;
-+	}
-+}
-+
-+/*
-+ * is_accelerated_mode
-+ *
-+ * @brief
-+ *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-+ *  VGA/non-Accelerated mode is set
-+ *
-+ * @param
-+ * struct dc_context *ctx
-+ *
-+ * @return
-+ * true if in acceleration mode, false otherwise.
-+ */
-+static bool is_accelerated_mode(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	return (value & ATOM_S6_ACC_MODE) ? true : false;
-+}
-+
-+#define BIOS_SCRATCH0_DAC_B_SHIFT 8
-+
-+/**
-+ * detect_sink
-+ *
-+ * @brief
-+ *  read VBIOS scratch register to determine whether display for the specified
-+ *  signal is present and return the actual sink signal type
-+ *  For analog signals VBIOS load detection has to be called prior reading the
-+ *  register
-+ *
-+ * @param
-+ *  encoder - encoder id (to specify DAC)
-+ *  connector - connector id (to check CV on DIN)
-+ *  signal - signal (as display type) to check
-+ *
-+ * @return
-+ *  signal_type - actual (on the sink) signal type detected
-+ */
-+static enum signal_type detect_sink(
-+	struct dc_context *ctx,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type signal)
-+{
-+	uint32_t bios_scratch0;
-+	uint32_t encoder_id = encoder.id;
-+	/* after DCE 10.x does not support DAC2, so assert and return
-+	 * SIGNAL_TYPE_NONE */
-+	if (encoder_id == ENCODER_ID_INTERNAL_DAC2
-+		|| encoder_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2) {
-+		ASSERT(false);
-+		return SIGNAL_TYPE_NONE;
-+	}
-+
-+	bios_scratch0 = dal_read_reg(ctx,
-+		mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF);
-+
-+	/* In further processing we use DACB masks. If we want detect load on
-+	 * DACA, we need to shift the register so DACA bits will be in place of
-+	 * DACB bits
-+	 */
-+	if (encoder_id == ENCODER_ID_INTERNAL_DAC1
-+		|| encoder_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1
-+		|| encoder_id == ENCODER_ID_EXTERNAL_NUTMEG
-+		|| encoder_id == ENCODER_ID_EXTERNAL_TRAVIS) {
-+		bios_scratch0 <<= BIOS_SCRATCH0_DAC_B_SHIFT;
-+	}
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_RGB: {
-+		if (bios_scratch0 & ATOM_S0_CRT2_MASK)
-+			return SIGNAL_TYPE_RGB;
-+		break;
-+	}
-+	case SIGNAL_TYPE_LVDS: {
-+		if (bios_scratch0 & ATOM_S0_LCD1)
-+			return SIGNAL_TYPE_LVDS;
-+		break;
-+	}
-+	case SIGNAL_TYPE_EDP: {
-+		if (bios_scratch0 & ATOM_S0_LCD1)
-+			return SIGNAL_TYPE_EDP;
-+		break;
-+	}
-+	default:
-+		break;
-+	}
-+
-+	return SIGNAL_TYPE_NONE;
-+}
-+
-+/**
-+ * set_scratch_connected
-+ *
-+ * @brief
-+ *    update BIOS_SCRATCH_0 register about connected displays
-+ *
-+ * @param
-+ * bool - update scratch register or just prepare info to be updated
-+ * bool - connection state
-+ * const struct connector_device_tag_info * - pointer to device type and enum ID
-+ */
-+static void set_scratch_connected(
-+	struct dc_context *ctx,
-+	struct graphics_object_id id,
-+	bool connected,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t update = 0;
-+
-+	switch (device_tag->dev_id.device_type) {
-+	case DEVICE_TYPE_LCD:
-+		/* For LCD VBIOS will update LCD Panel connected bit always and
-+		 * Lid state bit based on SBIOS info do not do anything here
-+		 * for LCD
-+		 */
-+		break;
-+	case DEVICE_TYPE_CRT:
-+		/*
-+		 * CRT is not supported in DCE11
-+		 */
-+		break;
-+	case DEVICE_TYPE_DFP:
-+		switch (device_tag->dev_id.enum_id) {
-+		case 1:
-+			update |= ATOM_S0_DFP1;
-+			break;
-+		case 2:
-+			update |= ATOM_S0_DFP2;
-+			break;
-+		case 3:
-+			update |= ATOM_S0_DFP3;
-+			break;
-+		case 4:
-+			update |= ATOM_S0_DFP4;
-+			break;
-+		case 5:
-+			update |= ATOM_S0_DFP5;
-+			break;
-+		case 6:
-+			update |= ATOM_S0_DFP6;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CV:
-+		/* DCE 8.0 does not support CV,
-+		 * so don't do anything */
-+		break;
-+
-+	case DEVICE_TYPE_TV:
-+		/* For TV VBIOS will update S-Video or
-+		 * Composite scratch bits on DAL_LoadDetect
-+		 * when called by driver, do not do anything
-+		 * here for TV
-+		 */
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+	/* update scratch register */
-+	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	if (connected)
-+		value |= update;
-+	else
-+		value &= ~update;
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void set_scratch_critical_state(
-+	struct dc_context *ctx,
-+	bool state)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	if (state)
-+		value |= ATOM_S6_CRITICAL_STATE;
-+	else
-+		value &= ~ATOM_S6_CRITICAL_STATE;
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void set_scratch_lcd_scale(
-+	struct dc_context *ctx,
-+	enum lcd_scale lcd_scale_request)
-+{
-+	DAL_LOGGER_NOT_IMPL(
-+		LOG_MINOR_COMPONENT_BIOS,
-+		"Bios Parser:%s\n",
-+		__func__);
-+}
-+
-+static bool is_lid_open(struct dc_context *ctx)
-+{
-+	uint32_t bios_scratch6;
-+
-+	bios_scratch6 =
-+		dal_read_reg(
-+			ctx,
-+			mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF);
-+
-+	/* lid is open if the bit is not set */
-+	if (!(bios_scratch6 & ATOM_S6_LID_STATE))
-+		return true;
-+
-+	return false;
-+}
-+
-+/* function table */
-+static const struct bios_parser_helper bios_parser_helper_funcs = {
-+	.detect_sink = detect_sink,
-+	.fmt_bit_depth_control = NULL,
-+	.fmt_control = NULL,
-+	.get_bios_event_info = NULL,
-+	.get_embedded_display_controller_id = NULL,
-+	.get_embedded_display_refresh_rate = NULL,
-+	.get_requested_backlight_level = NULL,
-+	.get_scratch_lcd_scale = get_scratch_lcd_scale,
-+	.is_accelerated_mode = is_accelerated_mode,
-+	.is_active_display = NULL,
-+	.is_display_config_changed = NULL,
-+	.is_lid_open = is_lid_open,
-+	.is_lid_status_changed = NULL,
-+	.prepare_scratch_active_and_requested =
-+			prepare_scratch_active_and_requested,
-+	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
-+	.set_scratch_active_and_requested = set_scratch_active_and_requested,
-+	.set_scratch_connected = set_scratch_connected,
-+	.set_scratch_critical_state = set_scratch_critical_state,
-+	.set_scratch_lcd_scale = set_scratch_lcd_scale,
-+	.take_backlight_control = NULL,
-+	.update_requested_backlight_level = NULL,
-+};
-+
-+/*
-+ * dal_bios_parser_dce110_init_bios_helper
-+ *
-+ * @brief
-+ * Initialize BIOS helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+
-+const struct bios_parser_helper *dal_bios_parser_helper_dce110_get_table()
-+{
-+	return &bios_parser_helper_funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
-new file mode 100644
-index 0000000..915f31a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_HELPER_DCE110_H__
-+#define __DAL_BIOS_PARSER_HELPER_DCE110_H__
-+
-+struct bios_parser_helper;
-+
-+/* Initialize BIOS helper functions */
-+const struct bios_parser_helper *dal_bios_parser_helper_dce110_get_table(void);
-+
-+#endif /* __DAL_BIOS_PARSER_HELPER_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-new file mode 100644
-index 0000000..e75b51b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-@@ -0,0 +1,369 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+
-+#include "../command_table_helper.h"
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel >> 4;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
-+		break;
-+	case ENGINE_ID_UNKNOWN:
-+		 /* No DIG_FRONT is associated to DIG_BACKEND */
-+		atom_dig_encoder_sel = 0;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	}
-+
-+	return atom_dig_encoder_sel;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_ID_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL1:
-+			*atom_pll_id = ATOM_PPLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL2:
-+			*atom_pll_id = ATOM_PPLL2;
-+			break;
-+		case CLOCK_SOURCE_ID_EXTERNAL:
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_EXT_PLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			/* for VCE encoding,
-+			 * we need to pass in ATOM_PPLL_INVALID
-+			 */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			/* When programming DP DTO PLL ID should be invalid */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			/* Should not happen */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DVO:
-+			*atom_engine_id = ASIC_EXT_DIG_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+/* function table */
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+			clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.assign_control_parameter = NULL,
-+	.clock_source_id_to_ref_clk_src = NULL,
-+	.transmitter_bp_to_atom = NULL,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
-+	.encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
-+};
-+
-+/*
-+ * dal_cmd_tbl_helper_dce110_get_table
-+ *
-+ * @brief
-+ * Initialize command table helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table()
-+{
-+	return &command_table_helper_funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h
-new file mode 100644
-index 0000000..eb60c2e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE110_H__
-+#define __DAL_COMMAND_TABLE_HELPER_DCE110_H__
-+
-+struct command_table_helper;
-+
-+/* Initialize command table helper functions */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void);
-+
-+#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/Makefile b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
-new file mode 100644
-index 0000000..7f1916b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'calcs' sub-component of DAL.
-+# It calculates Bandwidth and Watermarks values for HW programming
-+#
-+
-+BW_CALCS = bandwidth_calcs.o bw_fixed.o scaler_filter.o
-+
-+AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
-+
-+AMD_DAL_FILES += $(AMD_DAL_BW_CALCS)
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-new file mode 100644
-index 0000000..68618bb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -0,0 +1,3478 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+
-+#include "bandwidth_calcs.h"
-+
-+/*******************************************************************************
-+ * Private Functions
-+ ******************************************************************************/
-+
-+enum bw_defines {
-+	def_ok,
-+	def_na,
-+	def_notok,
-+	def_display_write_back420_chroma,
-+	def_display_write_back420_luma,
-+	def_graphics,
-+	def_xl_pattern_solid,
-+	def_xl_pattern_light_horizontal,
-+	def_xl_pattern_checker,
-+	def_notok_color,
-+	def_na_color,
-+	def_vb_black,
-+	def_vb_white,
-+	def_high_no_nbp_state_change_color,
-+	def_high_no_nbp_state_change,
-+	def_high_color,
-+	def_mid_color,
-+	def_low_color,
-+	def_high,
-+	def_mid,
-+	def_low,
-+	def_exceeded_allowed_maximum_sclk,
-+	def_exceeded_allowed_maximum_bw,
-+	def_exceeded_allowed_page_close_open,
-+	def_exceeded_allowed_outstanding_pte_req_queue_size,
-+	def_linear,
-+	def_underlay444,
-+	def_underlay422,
-+	def_underlay420_chroma,
-+	def_underlay420_luma,
-+	def_any_lines,
-+	def_auto,
-+	def_manual,
-+	def_portrait,
-+	def_invalid_linear_or_stereo_mode,
-+	def_invalid_rotation_or_bpp_or_stereo,
-+	def_vsr_more_than_vtaps,
-+	def_vsr_more_than_4,
-+	def_ceil_htaps_div_4_more_or_eq_hsr,
-+	def_hsr_more_than_htaps,
-+	def_hsr_more_than_4,
-+	def_none,
-+	def_blended,
-+	def_landscape
-+};
-+
-+static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
-+	const struct bw_calcs_input_vbios *vbios,
-+	const struct bw_calcs_input_mode_data_internal *mode_data,
-+	struct bw_results_internal *results)
-+{
-+	const struct bw_fixed pixels_per_chunk = int_to_fixed(512);
-+	const struct bw_fixed max_chunks_non_fbc_mode = int_to_fixed(16);
-+	const uint32_t high = 2;
-+	const uint32_t mid = 1;
-+	const uint32_t low = 0;
-+
-+	uint32_t i, j, k;
-+	struct bw_fixed yclk[3];
-+	struct bw_fixed sclk[3];
-+	bool d0_underlay_enable;
-+	bool d1_underlay_enable;
-+	enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
-+	enum bw_defines tiling_mode[maximum_number_of_surfaces];
-+	enum bw_stereo_mode stereo_mode[maximum_number_of_surfaces];
-+	enum bw_defines surface_type[maximum_number_of_surfaces];
-+	enum bw_defines voltage;
-+	enum bw_defines mode_background_color;
-+	enum bw_defines mode_font_color;
-+	enum bw_defines mode_pattern;
-+	enum bw_defines sclk_message;
-+	enum bw_defines yclk_message;
-+	enum bw_defines pipe_check;
-+	enum bw_defines hsr_check;
-+	enum bw_defines vsr_check;
-+	enum bw_defines lb_size_check;
-+	enum bw_defines fbc_check;
-+	enum bw_defines rotation_check;
-+	enum bw_defines mode_check;
-+	uint32_t y_clk_level;
-+	uint32_t sclk_level;
-+	yclk[high] = vbios->high_yclk;
-+	yclk[mid] = vbios->high_yclk;
-+	yclk[low] = vbios->low_yclk;
-+	sclk[high] = vbios->high_sclk;
-+	sclk[mid] = vbios->mid_sclk;
-+	sclk[low] = vbios->low_sclk;
-+	if (mode_data->d0_underlay_mode == ul_none) {
-+		d0_underlay_enable = false;
-+	} else {
-+		d0_underlay_enable = true;
-+	}
-+	if (mode_data->d1_underlay_mode == ul_none) {
-+		d1_underlay_enable = false;
-+	} else {
-+		d1_underlay_enable = true;
-+	}
-+	results->number_of_underlay_surfaces = int_to_fixed(
-+		d0_underlay_enable + d1_underlay_enable);
-+	if (mode_data->underlay_surface_type == yuv_420) {
-+		surface_type[0] = def_underlay420_luma;
-+		surface_type[2] = def_underlay420_luma;
-+		results->bytes_per_pixel[0] = int_to_fixed(1);
-+		results->bytes_per_pixel[2] = int_to_fixed(1);
-+		surface_type[1] = def_underlay420_chroma;
-+		surface_type[3] = def_underlay420_chroma;
-+		results->bytes_per_pixel[1] = int_to_fixed(2);
-+		results->bytes_per_pixel[3] = int_to_fixed(2);
-+		results->lb_size_per_component[0] =
-+			dceip->underlay420_luma_lb_size_per_component;
-+		results->lb_size_per_component[1] =
-+			dceip->underlay420_chroma_lb_size_per_component;
-+		results->lb_size_per_component[2] =
-+			dceip->underlay420_luma_lb_size_per_component;
-+		results->lb_size_per_component[3] =
-+			dceip->underlay420_chroma_lb_size_per_component;
-+	} else if (mode_data->underlay_surface_type == yuv_422) {
-+		surface_type[0] = def_underlay422;
-+		surface_type[2] = def_underlay422;
-+		results->bytes_per_pixel[0] = int_to_fixed(2);
-+		results->bytes_per_pixel[2] = int_to_fixed(2);
-+		results->lb_size_per_component[0] =
-+			dceip->underlay422_lb_size_per_component;
-+		results->lb_size_per_component[2] =
-+			dceip->underlay422_lb_size_per_component;
-+	} else {
-+		surface_type[0] = def_underlay444;
-+		surface_type[2] = def_underlay444;
-+		results->bytes_per_pixel[0] = int_to_fixed(4);
-+		results->bytes_per_pixel[2] = int_to_fixed(4);
-+		results->lb_size_per_component[0] =
-+			dceip->lb_size_per_component444;
-+		results->lb_size_per_component[2] =
-+			dceip->lb_size_per_component444;
-+	}
-+	if (d0_underlay_enable) {
-+		if (mode_data->underlay_surface_type == yuv_420) {
-+			results->enable[0] = true;
-+			results->enable[1] = true;
-+		} else {
-+			results->enable[0] = true;
-+			results->enable[1] = false;
-+		}
-+	} else {
-+		results->enable[0] = false;
-+		results->enable[1] = false;
-+	}
-+	if (d1_underlay_enable) {
-+		if (mode_data->underlay_surface_type == yuv_420) {
-+			results->enable[2] = true;
-+			results->enable[3] = true;
-+		} else {
-+			results->enable[2] = true;
-+			results->enable[3] = false;
-+		}
-+	} else {
-+		results->enable[2] = false;
-+		results->enable[3] = false;
-+	}
-+
-+	results->use_alpha[0] = false;
-+	results->use_alpha[1] = false;
-+	results->use_alpha[2] = false;
-+	results->use_alpha[3] = false;
-+	results->scatter_gather_enable_for_pipe[0] =
-+		vbios->scatter_gather_enable;
-+	results->scatter_gather_enable_for_pipe[1] =
-+		vbios->scatter_gather_enable;
-+	results->scatter_gather_enable_for_pipe[2] =
-+		vbios->scatter_gather_enable;
-+	results->scatter_gather_enable_for_pipe[3] =
-+		vbios->scatter_gather_enable;
-+	results->interlace_mode[0] = mode_data->graphics_interlace_mode;
-+	results->interlace_mode[1] = mode_data->graphics_interlace_mode;
-+	results->interlace_mode[2] = mode_data->graphics_interlace_mode;
-+	results->interlace_mode[3] = mode_data->graphics_interlace_mode;
-+	results->h_total[0] = mode_data->d0_htotal;
-+	results->h_total[1] = mode_data->d0_htotal;
-+	results->h_total[2] = mode_data->d1_htotal;
-+	results->h_total[3] = mode_data->d1_htotal;
-+	results->pixel_rate[0] = mode_data->d0_pixel_rate;
-+	results->pixel_rate[1] = mode_data->d0_pixel_rate;
-+	results->pixel_rate[2] = mode_data->d1_pixel_rate;
-+	results->pixel_rate[3] = mode_data->d1_pixel_rate;
-+	results->src_width[0] = mode_data->underlay_src_width;
-+	results->src_width[1] = mode_data->underlay_src_width;
-+	results->src_width[2] = mode_data->underlay_src_width;
-+	results->src_width[3] = mode_data->underlay_src_width;
-+	results->src_height[0] = mode_data->underlay_src_height;
-+	results->src_height[1] = mode_data->underlay_src_height;
-+	results->src_height[2] = mode_data->underlay_src_height;
-+	results->src_height[3] = mode_data->underlay_src_height;
-+	results->pitch_in_pixels[0] = mode_data->underlay_pitch_in_pixels;
-+	results->pitch_in_pixels[1] = mode_data->underlay_pitch_in_pixels;
-+	results->pitch_in_pixels[2] = mode_data->underlay_pitch_in_pixels;
-+	results->pitch_in_pixels[3] = mode_data->underlay_pitch_in_pixels;
-+	results->scale_ratio[0] = mode_data->d0_underlay_scale_ratio;
-+	results->scale_ratio[1] = mode_data->d0_underlay_scale_ratio;
-+	results->scale_ratio[2] = mode_data->d1_underlay_scale_ratio;
-+	results->scale_ratio[3] = mode_data->d1_underlay_scale_ratio;
-+	results->h_taps[0] = mode_data->underlay_htaps;
-+	results->h_taps[1] = mode_data->underlay_htaps;
-+	results->h_taps[2] = mode_data->underlay_htaps;
-+	results->h_taps[3] = mode_data->underlay_htaps;
-+	results->v_taps[0] = mode_data->underlay_vtaps;
-+	results->v_taps[1] = mode_data->underlay_vtaps;
-+	results->v_taps[2] = mode_data->underlay_vtaps;
-+	results->v_taps[3] = mode_data->underlay_vtaps;
-+	results->rotation_angle[0] = mode_data->underlay_rotation_angle;
-+	results->rotation_angle[1] = mode_data->underlay_rotation_angle;
-+	results->rotation_angle[2] = mode_data->underlay_rotation_angle;
-+	results->rotation_angle[3] = mode_data->underlay_rotation_angle;
-+	if (mode_data->underlay_tiling_mode == linear) {
-+		tiling_mode[0] = def_linear;
-+		tiling_mode[1] = def_linear;
-+		tiling_mode[2] = def_linear;
-+		tiling_mode[3] = def_linear;
-+	} else {
-+		tiling_mode[0] = def_landscape;
-+		tiling_mode[1] = def_landscape;
-+		tiling_mode[2] = def_landscape;
-+		tiling_mode[3] = def_landscape;
-+	}
-+	stereo_mode[0] = mode_data->underlay_stereo_mode;
-+	stereo_mode[1] = mode_data->underlay_stereo_mode;
-+	stereo_mode[2] = mode_data->underlay_stereo_mode;
-+	stereo_mode[3] = mode_data->underlay_stereo_mode;
-+	results->lb_bpc[0] = mode_data->underlay_lb_bpc;
-+	results->lb_bpc[1] = mode_data->underlay_lb_bpc;
-+	results->lb_bpc[2] = mode_data->underlay_lb_bpc;
-+	results->lb_bpc[3] = mode_data->underlay_lb_bpc;
-+	results->compression_rate[0] = int_to_fixed(1);
-+	results->compression_rate[1] = int_to_fixed(1);
-+	results->compression_rate[2] = int_to_fixed(1);
-+	results->compression_rate[3] = int_to_fixed(1);
-+	results->access_one_channel_only[0] = false;
-+	results->access_one_channel_only[1] = false;
-+	results->access_one_channel_only[2] = false;
-+	results->access_one_channel_only[3] = false;
-+	results->cursor_width_pixels[0] = int_to_fixed(0);
-+	results->cursor_width_pixels[1] = int_to_fixed(0);
-+	results->cursor_width_pixels[2] = int_to_fixed(0);
-+	results->cursor_width_pixels[3] = int_to_fixed(0);
-+	for (i = 4; i <= maximum_number_of_surfaces - 3; i += 1) {
-+		if (i < mode_data->number_of_displays + 4) {
-+			if (i == 4 && mode_data->d0_underlay_mode == ul_only) {
-+				results->enable[i] = false;
-+				results->use_alpha[i] = false;
-+			} else if (i == 4
-+				&& mode_data->d0_underlay_mode == ul_blend) {
-+				results->enable[i] = true;
-+				results->use_alpha[i] = true;
-+			} else if (i == 4) {
-+				results->enable[i] = true;
-+				results->use_alpha[i] = false;
-+			} else if (i == 5
-+				&& mode_data->d1_underlay_mode == ul_only) {
-+				results->enable[i] = false;
-+				results->use_alpha[i] = false;
-+			} else if (i == 5
-+				&& mode_data->d1_underlay_mode == ul_blend) {
-+				results->enable[i] = true;
-+				results->use_alpha[i] = true;
-+			} else {
-+				results->enable[i] = true;
-+				results->use_alpha[i] = false;
-+			}
-+		} else {
-+			results->enable[i] = false;
-+			results->use_alpha[i] = false;
-+		}
-+		results->scatter_gather_enable_for_pipe[i] =
-+			vbios->scatter_gather_enable;
-+		surface_type[i] = def_graphics;
-+		results->lb_size_per_component[i] =
-+			dceip->lb_size_per_component444;
-+		results->bytes_per_pixel[i] =
-+			mode_data->graphics_bytes_per_pixel;
-+		results->interlace_mode[i] = mode_data->graphics_interlace_mode;
-+		results->h_taps[i] = mode_data->graphics_htaps;
-+		results->v_taps[i] = mode_data->graphics_vtaps;
-+		results->rotation_angle[i] = mode_data->graphics_rotation_angle;
-+		if (mode_data->graphics_tiling_mode == linear) {
-+			tiling_mode[i] = def_linear;
-+		} else if (equ(mode_data->graphics_rotation_angle,
-+			int_to_fixed(0))
-+			|| equ(mode_data->graphics_rotation_angle,
-+				int_to_fixed(180))) {
-+			tiling_mode[i] = def_landscape;
-+		} else {
-+			tiling_mode[i] = def_portrait;
-+		}
-+		results->lb_bpc[i] = mode_data->graphics_lb_bpc;
-+		if (i == 4) {
-+			/* todo: check original d0_underlay_mode comparison, possible bug there*/
-+			if (mode_data->d0_fbc_enable
-+				&& (dceip->argb_compression_support
-+					|| mode_data->d0_underlay_mode
-+						!= ul_blend)) {
-+				results->compression_rate[i] =
-+					vbios->average_compression_rate;
-+				results->access_one_channel_only[i] =
-+					mode_data->d0_lpt_enable;
-+			} else {
-+				results->compression_rate[i] = int_to_fixed(1);
-+				results->access_one_channel_only[i] = false;
-+			}
-+			results->h_total[i] = mode_data->d0_htotal;
-+			results->pixel_rate[i] = mode_data->d0_pixel_rate;
-+			results->src_width[i] =
-+				mode_data->d0_graphics_src_width;
-+			results->src_height[i] =
-+				mode_data->d0_graphics_src_height;
-+			results->pitch_in_pixels[i] =
-+				mode_data->d0_graphics_src_width;
-+			results->scale_ratio[i] =
-+				mode_data->d0_graphics_scale_ratio;
-+			stereo_mode[i] = mode_data->d0_graphics_stereo_mode;
-+		} else if (i == 5) {
-+			results->compression_rate[i] = int_to_fixed(1);
-+			results->access_one_channel_only[i] = false;
-+			results->h_total[i] = mode_data->d1_htotal;
-+			results->pixel_rate[i] = mode_data->d1_pixel_rate;
-+			results->src_width[i] =
-+				mode_data->d1_graphics_src_width;
-+			results->src_height[i] =
-+				mode_data->d1_graphics_src_height;
-+			results->pitch_in_pixels[i] =
-+				mode_data->d1_graphics_src_width;
-+			results->scale_ratio[i] =
-+				mode_data->d1_graphics_scale_ratio;
-+			stereo_mode[i] = mode_data->d1_graphics_stereo_mode;
-+		} else {
-+			results->compression_rate[i] = int_to_fixed(1);
-+			results->access_one_channel_only[i] = false;
-+			results->h_total[i] = mode_data->d2_htotal;
-+			results->pixel_rate[i] = mode_data->d2_pixel_rate;
-+			results->src_width[i] =
-+				mode_data->d2_graphics_src_width;
-+			results->src_height[i] =
-+				mode_data->d2_graphics_src_height;
-+			results->pitch_in_pixels[i] =
-+				mode_data->d2_graphics_src_width;
-+			results->scale_ratio[i] =
-+				mode_data->d2_graphics_scale_ratio;
-+			stereo_mode[i] = mode_data->d2_graphics_stereo_mode;
-+		}
-+		results->cursor_width_pixels[i] = vbios->cursor_width;
-+	}
-+	results->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] =
-+		false;
-+	results->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] =
-+		false;
-+	if (mode_data->d1_display_write_back_dwb_enable == true) {
-+		results->enable[maximum_number_of_surfaces - 2] = true;
-+		results->enable[maximum_number_of_surfaces - 1] = true;
-+	} else {
-+		results->enable[maximum_number_of_surfaces - 2] = false;
-+		results->enable[maximum_number_of_surfaces - 1] = false;
-+	}
-+	surface_type[maximum_number_of_surfaces - 2] =
-+		def_display_write_back420_luma;
-+	surface_type[maximum_number_of_surfaces - 1] =
-+		def_display_write_back420_chroma;
-+	results->lb_size_per_component[maximum_number_of_surfaces - 2] =
-+		dceip->underlay420_luma_lb_size_per_component;
-+	results->lb_size_per_component[maximum_number_of_surfaces - 1] =
-+		dceip->underlay420_chroma_lb_size_per_component;
-+	results->bytes_per_pixel[maximum_number_of_surfaces - 2] = int_to_fixed(
-+		1);
-+	results->bytes_per_pixel[maximum_number_of_surfaces - 1] = int_to_fixed(
-+		2);
-+	results->interlace_mode[maximum_number_of_surfaces - 2] =
-+		mode_data->graphics_interlace_mode;
-+	results->interlace_mode[maximum_number_of_surfaces - 1] =
-+		mode_data->graphics_interlace_mode;
-+	results->h_taps[maximum_number_of_surfaces - 2] = int_to_fixed(1);
-+	results->h_taps[maximum_number_of_surfaces - 1] = int_to_fixed(1);
-+	results->v_taps[maximum_number_of_surfaces - 2] = int_to_fixed(1);
-+	results->v_taps[maximum_number_of_surfaces - 1] = int_to_fixed(1);
-+	results->rotation_angle[maximum_number_of_surfaces - 2] = int_to_fixed(
-+		0);
-+	results->rotation_angle[maximum_number_of_surfaces - 1] = int_to_fixed(
-+		0);
-+	tiling_mode[maximum_number_of_surfaces - 2] = def_linear;
-+	tiling_mode[maximum_number_of_surfaces - 1] = def_linear;
-+	results->lb_bpc[maximum_number_of_surfaces - 2] = int_to_fixed(8);
-+	results->lb_bpc[maximum_number_of_surfaces - 1] = int_to_fixed(8);
-+	results->compression_rate[maximum_number_of_surfaces - 2] =
-+		int_to_fixed(1);
-+	results->compression_rate[maximum_number_of_surfaces - 1] =
-+		int_to_fixed(1);
-+	results->access_one_channel_only[maximum_number_of_surfaces - 2] =
-+		false;
-+	results->access_one_channel_only[maximum_number_of_surfaces - 1] =
-+		false;
-+	results->h_total[maximum_number_of_surfaces - 2] = mode_data->d1_htotal;
-+	results->h_total[maximum_number_of_surfaces - 1] = mode_data->d1_htotal;
-+	results->pixel_rate[maximum_number_of_surfaces - 2] =
-+		mode_data->d1_pixel_rate;
-+	results->pixel_rate[maximum_number_of_surfaces - 1] =
-+		mode_data->d1_pixel_rate;
-+	results->src_width[maximum_number_of_surfaces - 2] =
-+		mode_data->d1_graphics_src_width;
-+	results->src_width[maximum_number_of_surfaces - 1] =
-+		mode_data->d1_graphics_src_width;
-+	results->src_height[maximum_number_of_surfaces - 2] =
-+		mode_data->d1_graphics_src_height;
-+	results->src_height[maximum_number_of_surfaces - 1] =
-+		mode_data->d1_graphics_src_height;
-+	results->pitch_in_pixels[maximum_number_of_surfaces - 2] =
-+		mode_data->d1_graphics_src_width;
-+	results->pitch_in_pixels[maximum_number_of_surfaces - 1] =
-+		mode_data->d1_graphics_src_width;
-+	results->scale_ratio[maximum_number_of_surfaces - 2] = int_to_fixed(1);
-+	results->scale_ratio[maximum_number_of_surfaces - 1] = int_to_fixed(1);
-+	stereo_mode[maximum_number_of_surfaces - 2] = mono;
-+	stereo_mode[maximum_number_of_surfaces - 1] = mono;
-+	results->cursor_width_pixels[maximum_number_of_surfaces - 2] =
-+		int_to_fixed(0);
-+	results->cursor_width_pixels[maximum_number_of_surfaces - 1] =
-+		int_to_fixed(0);
-+	results->use_alpha[maximum_number_of_surfaces - 2] = false;
-+	results->use_alpha[maximum_number_of_surfaces - 1] = false;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (equ(results->scale_ratio[i], int_to_fixed(1))
-+				&& surface_type[i] == def_graphics
-+				&& stereo_mode[i] == mono
-+				&& results->interlace_mode[i] == false) {
-+				results->h_taps[i] = int_to_fixed(1);
-+				results->v_taps[i] = int_to_fixed(1);
-+			}
-+			if (surface_type[i] == def_display_write_back420_chroma
-+				|| surface_type[i] == def_underlay420_chroma) {
-+				results->pitch_in_pixels_after_surface_type[i] =
-+					bw_div(results->pitch_in_pixels[i],
-+						int_to_fixed(2));
-+				results->src_width_after_surface_type = bw_div(
-+					results->src_width[i], int_to_fixed(2));
-+				results->src_height_after_surface_type = bw_div(
-+					results->src_height[i],
-+					int_to_fixed(2));
-+				results->hsr_after_surface_type = bw_div(
-+					results->scale_ratio[i],
-+					int_to_fixed(2));
-+				results->vsr_after_surface_type = bw_div(
-+					results->scale_ratio[i],
-+					int_to_fixed(2));
-+			} else {
-+				results->pitch_in_pixels_after_surface_type[i] =
-+					results->pitch_in_pixels[i];
-+				results->src_width_after_surface_type =
-+					results->src_width[i];
-+				results->src_height_after_surface_type =
-+					results->src_height[i];
-+				results->hsr_after_surface_type =
-+					results->scale_ratio[i];
-+				results->vsr_after_surface_type =
-+					results->scale_ratio[i];
-+			}
-+			if ((equ(results->rotation_angle[i], int_to_fixed(90))
-+				|| equ(results->rotation_angle[i],
-+					int_to_fixed(270)))
-+				&& surface_type[i] != def_graphics) {
-+				results->src_width_after_rotation =
-+					results->src_height_after_surface_type;
-+				results->src_height_after_rotation =
-+					results->src_width_after_surface_type;
-+				results->hsr_after_rotation =
-+					results->vsr_after_surface_type;
-+				results->vsr_after_rotation =
-+					results->hsr_after_surface_type;
-+			} else {
-+				results->src_width_after_rotation =
-+					results->src_width_after_surface_type;
-+				results->src_height_after_rotation =
-+					results->src_height_after_surface_type;
-+				results->hsr_after_rotation =
-+					results->hsr_after_surface_type;
-+				results->vsr_after_rotation =
-+					results->vsr_after_surface_type;
-+			}
-+			if (stereo_mode[i] == top_bottom) {
-+				results->source_width_pixels[i] =
-+					results->src_width_after_rotation;
-+				results->source_height_pixels = mul(
-+					int_to_fixed(2),
-+					results->src_height_after_rotation);
-+				results->hsr_after_stereo =
-+					results->hsr_after_rotation;
-+				results->vsr_after_stereo = mul(
-+					results->vsr_after_rotation,
-+					int_to_fixed(1)); //todo: confirm correctness
-+			} else if (stereo_mode[i] == side_by_side) {
-+				results->source_width_pixels[i] = mul(
-+					int_to_fixed(2),
-+					results->src_width_after_rotation);
-+				results->source_height_pixels =
-+					results->src_height_after_rotation;
-+				results->hsr_after_stereo = mul(
-+					results->hsr_after_rotation,
-+					int_to_fixed(1)); //todo: confirm correctness
-+				results->vsr_after_stereo =
-+					results->vsr_after_rotation;
-+			} else {
-+				results->source_width_pixels[i] =
-+					results->src_width_after_rotation;
-+				results->source_height_pixels =
-+					results->src_height_after_rotation;
-+				results->hsr_after_stereo =
-+					results->hsr_after_rotation;
-+				results->vsr_after_stereo =
-+					results->vsr_after_rotation;
-+			}
-+			results->hsr[i] = results->hsr_after_stereo;
-+			if (results->interlace_mode[i]) {
-+				results->vsr[i] = mul(results->vsr_after_stereo,
-+					int_to_fixed(2));
-+			} else {
-+				results->vsr[i] = results->vsr_after_stereo;
-+			}
-+			if (mode_data->panning_and_bezel_adjustment != none) {
-+				results->source_width_rounded_up_to_chunks[i] =
-+					add(
-+						bw_floor(
-+							sub(
-+								results->source_width_pixels[i],
-+								int_to_fixed(
-+									1)),
-+							int_to_fixed(128)),
-+						int_to_fixed(256));
-+			} else {
-+				results->source_width_rounded_up_to_chunks[i] =
-+					bw_ceil(results->source_width_pixels[i],
-+						int_to_fixed(128));
-+			}
-+			results->source_height_rounded_up_to_chunks[i] =
-+				results->source_height_pixels;
-+		}
-+	}
-+	if (geq(dceip->number_of_graphics_pipes,
-+		int_to_fixed(mode_data->number_of_displays))
-+		&& geq(dceip->number_of_underlay_pipes,
-+			results->number_of_underlay_surfaces)
-+		&& !(dceip->display_write_back_supported == false
-+			&& mode_data->d1_display_write_back_dwb_enable == true)) {
-+		pipe_check = def_ok;
-+	} else {
-+		pipe_check = def_notok;
-+	}
-+	hsr_check = def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (neq(results->hsr[i], int_to_fixed(1))) {
-+				if (gtn(results->hsr[i], int_to_fixed(4))) {
-+					hsr_check = def_hsr_more_than_4;
-+				} else {
-+					if (gtn(results->hsr[i],
-+						results->h_taps[i])) {
-+						hsr_check =
-+							def_hsr_more_than_htaps;
-+					} else {
-+						if (dceip->pre_downscaler_enabled
-+							== true
-+							&& gtn(results->hsr[i],
-+								int_to_fixed(1))
-+							&& leq(results->hsr[i],
-+								bw_ceil(
-+									bw_div(
-+										results->h_taps[i],
-+										int_to_fixed(
-+											4)),
-+									int_to_fixed(
-+										1)))) {
-+							hsr_check =
-+								def_ceil_htaps_div_4_more_or_eq_hsr;
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	vsr_check = def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (neq(results->vsr[i], int_to_fixed(1))) {
-+				if (gtn(results->vsr[i], int_to_fixed(4))) {
-+					vsr_check = def_vsr_more_than_4;
-+				} else {
-+					if (gtn(results->vsr[i],
-+						results->v_taps[i])) {
-+						vsr_check =
-+							def_vsr_more_than_vtaps;
-+					}
-+				}
-+			}
-+		}
-+	}
-+	lb_size_check = def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if ((dceip->pre_downscaler_enabled
-+				&& gtn(results->hsr[i], int_to_fixed(1)))) {
-+				results->source_width_in_lb = bw_div(
-+					results->source_width_pixels[i],
-+					results->hsr[i]);
-+			} else {
-+				results->source_width_in_lb =
-+					results->source_width_pixels[i];
-+			}
-+			if (equ(results->lb_bpc[i], int_to_fixed(8))) {
-+				results->lb_line_pitch =
-+					bw_ceil(
-+						mul(frc_to_fixed(24011, 3000),
-+							bw_ceil(
-+								results->source_width_in_lb,
-+								int_to_fixed(
-+									8))),
-+						int_to_fixed(48));
-+			} else if (equ(results->lb_bpc[i], int_to_fixed(10))) {
-+				results->lb_line_pitch =
-+					bw_ceil(
-+						mul(frc_to_fixed(30023, 3000),
-+							bw_ceil(
-+								results->source_width_in_lb,
-+								int_to_fixed(
-+									8))),
-+						int_to_fixed(48));
-+			} else
-+			// case else
-+			{
-+				results->lb_line_pitch = bw_ceil(
-+					mul(results->source_width_in_lb,
-+						results->lb_bpc[i]),
-+					int_to_fixed(48));
-+			}
-+			results->lb_partitions[i] = bw_floor(
-+				bw_div(results->lb_size_per_component[i],
-+					results->lb_line_pitch),
-+				int_to_fixed(1));
-+			if ((surface_type[i] != def_graphics
-+				|| dceip->graphics_lb_nodownscaling_multi_line_prefetching
-+					== true)) {
-+				results->lb_partitions_max[i] = int_to_fixed(
-+					10);
-+			} else {
-+				results->lb_partitions_max[i] = int_to_fixed(7);
-+			}
-+			results->lb_partitions[i] = bw_min(
-+				results->lb_partitions_max[i],
-+				results->lb_partitions[i]);
-+			if (gtn(add(results->v_taps[i], int_to_fixed(1)),
-+				results->lb_partitions[i])) {
-+				lb_size_check = def_notok;
-+			}
-+		}
-+	}
-+	if (mode_data->d0_fbc_enable
-+		&& (equ(mode_data->graphics_rotation_angle, int_to_fixed(90))
-+			|| equ(mode_data->graphics_rotation_angle,
-+				int_to_fixed(270))
-+			|| mode_data->d0_graphics_stereo_mode != mono
-+			|| neq(mode_data->graphics_bytes_per_pixel,
-+				int_to_fixed(4)))) {
-+		fbc_check = def_invalid_rotation_or_bpp_or_stereo;
-+	} else {
-+		fbc_check = def_ok;
-+	}
-+	rotation_check = def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if ((equ(results->rotation_angle[i], int_to_fixed(90))
-+				|| equ(results->rotation_angle[i],
-+					int_to_fixed(270)))
-+				&& (tiling_mode[i] == def_linear
-+					|| stereo_mode[i] != mono)) {
-+				rotation_check =
-+					def_invalid_linear_or_stereo_mode;
-+			}
-+		}
-+	}
-+	if (pipe_check == def_ok && hsr_check == def_ok && vsr_check == def_ok
-+		&& lb_size_check == def_ok && fbc_check == def_ok
-+		&& rotation_check == def_ok) {
-+		mode_check = def_ok;
-+	} else {
-+		mode_check = def_notok;
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if ((equ(results->rotation_angle[i], int_to_fixed(90))
-+				|| equ(results->rotation_angle[i],
-+					int_to_fixed(270)))) {
-+				if ((tiling_mode[i] == def_portrait)) {
-+					results->orthogonal_rotation[i] = false;
-+				} else {
-+					results->orthogonal_rotation[i] = true;
-+				}
-+			} else {
-+				if ((tiling_mode[i] == def_portrait)) {
-+					results->orthogonal_rotation[i] = true;
-+				} else {
-+					results->orthogonal_rotation[i] = false;
-+				}
-+			}
-+			if (equ(results->rotation_angle[i], int_to_fixed(90))
-+				|| equ(results->rotation_angle[i],
-+					int_to_fixed(270))) {
-+				results->underlay_maximum_source_efficient_for_tiling =
-+					dceip->underlay_maximum_height_efficient_for_tiling;
-+			} else {
-+				results->underlay_maximum_source_efficient_for_tiling =
-+					dceip->underlay_maximum_width_efficient_for_tiling;
-+			}
-+			if (equ(dceip->de_tiling_buffer, int_to_fixed(0))) {
-+				if (surface_type[i]
-+					== def_display_write_back420_luma
-+					|| surface_type[i]
-+						== def_display_write_back420_chroma) {
-+					results->bytes_per_request[i] =
-+						int_to_fixed(64);
-+					results->useful_bytes_per_request[i] =
-+						int_to_fixed(64);
-+					results->lines_interleaved_in_mem_access[i] =
-+						int_to_fixed(1);
-+					results->latency_hiding_lines[i] =
-+						int_to_fixed(1);
-+				} else if (tiling_mode[i] == def_linear) {
-+					results->bytes_per_request[i] =
-+						int_to_fixed(64);
-+					results->useful_bytes_per_request[i] =
-+						int_to_fixed(64);
-+					results->lines_interleaved_in_mem_access[i] =
-+						int_to_fixed(2);
-+					results->latency_hiding_lines[i] =
-+						int_to_fixed(2);
-+				} else {
-+					if (surface_type[i] == def_graphics
-+						|| (gtn(
-+							results->source_width_rounded_up_to_chunks[i],
-+							bw_ceil(
-+								results->underlay_maximum_source_efficient_for_tiling,
-+								int_to_fixed(
-+									256))))) {
-+						if (equ(
-+							results->bytes_per_pixel[i],
-+							int_to_fixed(8))) {
-+							results->lines_interleaved_in_mem_access[i] =
-+								int_to_fixed(2);
-+							results->latency_hiding_lines[i] =
-+								int_to_fixed(2);
-+							if (results->orthogonal_rotation[i]) {
-+								results->bytes_per_request[i] =
-+									int_to_fixed(
-+										32);
-+								results->useful_bytes_per_request[i] =
-+									int_to_fixed(
-+										32);
-+							} else {
-+								results->bytes_per_request[i] =
-+									int_to_fixed(
-+										64);
-+								results->useful_bytes_per_request[i] =
-+									int_to_fixed(
-+										64);
-+							}
-+						} else if (equ(
-+							results->bytes_per_pixel[i],
-+							int_to_fixed(4))) {
-+							if (results->orthogonal_rotation[i]) {
-+								results->lines_interleaved_in_mem_access[i] =
-+									int_to_fixed(
-+										2);
-+								results->latency_hiding_lines[i] =
-+									int_to_fixed(
-+										2);
-+								results->bytes_per_request[i] =
-+									int_to_fixed(
-+										32);
-+								results->useful_bytes_per_request[i] =
-+									int_to_fixed(
-+										16);
-+							} else {
-+								results->lines_interleaved_in_mem_access[i] =
-+									int_to_fixed(
-+										2);
-+								results->latency_hiding_lines[i] =
-+									int_to_fixed(
-+										2);
-+								results->bytes_per_request[i] =
-+									int_to_fixed(
-+										64);
-+								results->useful_bytes_per_request[i] =
-+									int_to_fixed(
-+										64);
-+							}
-+						} else if (equ(
-+							results->bytes_per_pixel[i],
-+							int_to_fixed(2))) {
-+							results->lines_interleaved_in_mem_access[i] =
-+								int_to_fixed(2);
-+							results->latency_hiding_lines[i] =
-+								int_to_fixed(2);
-+							results->bytes_per_request[i] =
-+								int_to_fixed(
-+									32);
-+							results->useful_bytes_per_request[i] =
-+								int_to_fixed(
-+									32);
-+						} else {
-+							results->lines_interleaved_in_mem_access[i] =
-+								int_to_fixed(2);
-+							results->latency_hiding_lines[i] =
-+								int_to_fixed(2);
-+							results->bytes_per_request[i] =
-+								int_to_fixed(
-+									32);
-+							results->useful_bytes_per_request[i] =
-+								int_to_fixed(
-+									16);
-+						}
-+					} else {
-+						results->bytes_per_request[i] =
-+							int_to_fixed(64);
-+						results->useful_bytes_per_request[i] =
-+							int_to_fixed(64);
-+						if (results->orthogonal_rotation[i]) {
-+							results->lines_interleaved_in_mem_access[i] =
-+								int_to_fixed(8);
-+							results->latency_hiding_lines[i] =
-+								int_to_fixed(4);
-+						} else {
-+							if (equ(
-+								results->bytes_per_pixel[i],
-+								int_to_fixed(
-+									4))) {
-+								results->lines_interleaved_in_mem_access[i] =
-+									int_to_fixed(
-+										2);
-+								results->latency_hiding_lines[i] =
-+									int_to_fixed(
-+										2);
-+							} else if (equ(
-+								results->bytes_per_pixel[i],
-+								int_to_fixed(
-+									2))) {
-+								results->lines_interleaved_in_mem_access[i] =
-+									int_to_fixed(
-+										4);
-+								results->latency_hiding_lines[i] =
-+									int_to_fixed(
-+										4);
-+							} else {
-+								results->lines_interleaved_in_mem_access[i] =
-+									int_to_fixed(
-+										8);
-+								results->latency_hiding_lines[i] =
-+									int_to_fixed(
-+										4);
-+							}
-+						}
-+					}
-+				}
-+			} else {
-+				results->bytes_per_request[i] = int_to_fixed(
-+					256);
-+				results->useful_bytes_per_request[i] =
-+					int_to_fixed(256);
-+				results->lines_interleaved_in_mem_access[i] =
-+					int_to_fixed(4);
-+				results->latency_hiding_lines[i] = int_to_fixed(
-+					4);
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->v_filter_init[i] =
-+				bw_floor(
-+					bw_div(
-+						(add(
-+							add(
-+								add(
-+									results->vsr[i],
-+									results->v_taps[i]),
-+								mul(
-+									mul(
-+										frc_to_fixed(
-+											1,
-+											2),
-+										results->vsr[i]),
-+									int_to_fixed(
-+										results->interlace_mode[i]))),
-+							int_to_fixed(1))),
-+						int_to_fixed(2)),
-+					int_to_fixed(1));
-+			if (mode_data->panning_and_bezel_adjustment
-+				== any_lines) {
-+				results->v_filter_init[i] = add(
-+					results->v_filter_init[i],
-+					int_to_fixed(1));
-+			}
-+			if (stereo_mode[i] == top_bottom) {
-+				v_filter_init_mode[i] = def_manual;
-+				results->v_filter_init[i] = bw_min(
-+					results->v_filter_init[i],
-+					int_to_fixed(4));
-+			} else {
-+				v_filter_init_mode[i] = def_auto;
-+			}
-+			if (stereo_mode[i] == top_bottom) {
-+				results->num_lines_at_frame_start =
-+					int_to_fixed(1);
-+			} else {
-+				results->num_lines_at_frame_start =
-+					int_to_fixed(3);
-+			}
-+			if ((gtn(results->vsr[i], int_to_fixed(1))
-+				&& surface_type[i] == def_graphics)
-+				|| mode_data->panning_and_bezel_adjustment
-+					== any_lines) {
-+				results->line_buffer_prefetch[i] = int_to_fixed(
-+					0);
-+			} else if ((((dceip->underlay_downscale_prefetch_enabled
-+				== true && surface_type[i] != def_graphics)
-+				|| surface_type[i] == def_graphics)
-+				&& (gtn(results->lb_partitions[i],
-+					add(results->v_taps[i],
-+						bw_ceil(results->vsr[i],
-+							int_to_fixed(1))))))) {
-+				results->line_buffer_prefetch[i] = int_to_fixed(
-+					1);
-+			} else {
-+				results->line_buffer_prefetch[i] = int_to_fixed(
-+					0);
-+			}
-+			results->lb_lines_in_per_line_out_in_beginning_of_frame[i] =
-+				bw_div(
-+					bw_ceil(results->v_filter_init[i],
-+						dceip->lines_interleaved_into_lb),
-+					results->num_lines_at_frame_start);
-+			if (equ(results->line_buffer_prefetch[i],
-+				int_to_fixed(1))) {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					bw_max(int_to_fixed(1),
-+						results->vsr[i]);
-+			} else if (leq(results->vsr[i], int_to_fixed(1))) {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					int_to_fixed(1);
-+			} else if (leq(results->vsr[i],
-+				bw_div(int_to_fixed(4), int_to_fixed(3)))) {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					bw_div(int_to_fixed(4), int_to_fixed(3));
-+			} else if (leq(results->vsr[i],
-+				bw_div(int_to_fixed(6), int_to_fixed(4)))) {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					bw_div(int_to_fixed(6), int_to_fixed(4));
-+			} else if (leq(results->vsr[i], int_to_fixed(2))) {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					int_to_fixed(2);
-+			} else if (leq(results->vsr[i], int_to_fixed(3))) {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					int_to_fixed(3);
-+			} else {
-+				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
-+					int_to_fixed(4);
-+			}
-+			if (equ(results->line_buffer_prefetch[i],
-+				int_to_fixed(1))
-+				|| equ(
-+					results->lb_lines_in_per_line_out_in_middle_of_frame[i],
-+					int_to_fixed(2))
-+				|| equ(
-+					results->lb_lines_in_per_line_out_in_middle_of_frame[i],
-+					int_to_fixed(4))) {
-+				results->horizontal_blank_and_chunk_granularity_factor[i] =
-+					int_to_fixed(1);
-+			} else {
-+				results->horizontal_blank_and_chunk_granularity_factor[i] =
-+					bw_div(results->h_total[i],
-+						(bw_div(
-+							(add(
-+								results->h_total[i],
-+								bw_div(
-+									(sub(
-+										results->source_width_pixels[i],
-+										dceip->chunk_width)),
-+									results->hsr[i]))),
-+							int_to_fixed(2))));
-+			}
-+			results->request_bandwidth[i] =
-+				bw_div(
-+					mul(
-+						bw_div(
-+							mul(
-+								bw_div(
-+									mul(
-+										bw_max(
-+											results->lb_lines_in_per_line_out_in_beginning_of_frame[i],
-+											results->lb_lines_in_per_line_out_in_middle_of_frame[i]),
-+										results->source_width_rounded_up_to_chunks[i]),
-+									(bw_div(
-+										results->h_total[i],
-+										results->pixel_rate[i]))),
-+								results->bytes_per_pixel[i]),
-+							results->useful_bytes_per_request[i]),
-+						results->lines_interleaved_in_mem_access[i]),
-+					results->latency_hiding_lines[i]);
-+			results->display_bandwidth[i] = mul(
-+				results->request_bandwidth[i],
-+				results->bytes_per_request[i]);
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] == def_display_write_back420_luma) {
-+				results->data_buffer_size[i] =
-+					dceip->display_write_back420_luma_mcifwr_buffer_size;
-+			} else if (surface_type[i]
-+				== def_display_write_back420_chroma) {
-+				results->data_buffer_size[i] =
-+					dceip->display_write_back420_chroma_mcifwr_buffer_size;
-+			} else if (surface_type[i] == def_underlay420_luma) {
-+				results->data_buffer_size[i] =
-+					dceip->underlay_luma_dmif_size;
-+			} else if (surface_type[i] == def_underlay420_chroma) {
-+				results->data_buffer_size[i] = bw_div(
-+					dceip->underlay_chroma_dmif_size,
-+					int_to_fixed(2));
-+			} else if (surface_type[i] == def_underlay422
-+				|| surface_type[i] == def_underlay444) {
-+				if (results->orthogonal_rotation[i] == false) {
-+					results->data_buffer_size[i] =
-+						dceip->underlay_luma_dmif_size;
-+				} else {
-+					results->data_buffer_size[i] =
-+						add(
-+							dceip->underlay_luma_dmif_size,
-+							dceip->underlay_chroma_dmif_size);
-+				}
-+			} else {
-+				if (mode_data->number_of_displays == 1
-+					&& equ(dceip->de_tiling_buffer,
-+						int_to_fixed(0))) {
-+					if (mode_data->d0_fbc_enable) {
-+						results->data_buffer_size[i] =
-+							mul(
-+								dceip->max_dmif_buffer_allocated,
-+								dceip->graphics_dmif_size);
-+					} else {
-+						results->data_buffer_size[i] =
-+							mul(
-+								mul(
-+									max_chunks_non_fbc_mode,
-+									pixels_per_chunk),
-+								results->bytes_per_pixel[i]);
-+					}
-+				} else {
-+					results->data_buffer_size[i] =
-+						dceip->graphics_dmif_size;
-+				}
-+			}
-+			if (surface_type[i] == def_display_write_back420_luma
-+				|| surface_type[i]
-+					== def_display_write_back420_chroma) {
-+				results->memory_chunk_size_in_bytes[i] =
-+					int_to_fixed(1024);
-+				results->pipe_chunk_size_in_bytes[i] =
-+					int_to_fixed(1024);
-+			} else {
-+				results->memory_chunk_size_in_bytes[i] =
-+					mul(
-+						mul(dceip->chunk_width,
-+							results->lines_interleaved_in_mem_access[i]),
-+						results->bytes_per_pixel[i]);
-+				results->pipe_chunk_size_in_bytes[i] =
-+					mul(
-+						mul(dceip->chunk_width,
-+							dceip->lines_interleaved_into_lb),
-+						results->bytes_per_pixel[i]);
-+			}
-+		}
-+	}
-+	results->min_dmif_size_in_time = int_to_fixed(9999);
-+	results->min_mcifwr_size_in_time = int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma) {
-+				if (ltn(
-+					bw_div(
-+						bw_div(
-+							mul(
-+								results->data_buffer_size[i],
-+								results->bytes_per_request[i]),
-+							results->useful_bytes_per_request[i]),
-+						results->display_bandwidth[i]),
-+					results->min_dmif_size_in_time)) {
-+					results->min_dmif_size_in_time =
-+						bw_div(
-+							bw_div(
-+								mul(
-+									results->data_buffer_size[i],
-+									results->bytes_per_request[i]),
-+								results->useful_bytes_per_request[i]),
-+							results->display_bandwidth[i]);
-+				}
-+			} else {
-+				if (ltn(
-+					bw_div(
-+						bw_div(
-+							mul(
-+								results->data_buffer_size[i],
-+								results->bytes_per_request[i]),
-+							results->useful_bytes_per_request[i]),
-+						results->display_bandwidth[i]),
-+					results->min_mcifwr_size_in_time)) {
-+					results->min_mcifwr_size_in_time =
-+						bw_div(
-+							bw_div(
-+								mul(
-+									results->data_buffer_size[i],
-+									results->bytes_per_request[i]),
-+								results->useful_bytes_per_request[i]),
-+							results->display_bandwidth[i]);
-+				}
-+			}
-+		}
-+	}
-+	results->total_requests_for_dmif_size = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]
-+			&& surface_type[i] != def_display_write_back420_luma
-+			&& surface_type[i]
-+				!= def_display_write_back420_chroma) {
-+			results->total_requests_for_dmif_size = add(
-+				results->total_requests_for_dmif_size,
-+				bw_div(results->data_buffer_size[i],
-+					results->useful_bytes_per_request[i]));
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma
-+				&& dceip->limit_excessive_outstanding_dmif_requests
-+				&& (mode_data->number_of_displays > 1
-+					|| gtn(
-+						results->total_requests_for_dmif_size,
-+						dceip->dmif_request_buffer_size))) {
-+				results->adjusted_data_buffer_size[i] =
-+					bw_min(results->data_buffer_size[i],
-+						bw_ceil(
-+							mul(
-+								results->min_dmif_size_in_time,
-+								results->display_bandwidth[i]),
-+							results->memory_chunk_size_in_bytes[i]));
-+			} else {
-+				results->adjusted_data_buffer_size[i] =
-+					results->data_buffer_size[i];
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if ((mode_data->number_of_displays == 1
-+				&& equ(results->number_of_underlay_surfaces,
-+					int_to_fixed(0)))) {
-+				results->outstanding_chunk_request_limit[i] =
-+					int_to_fixed(255);
-+			} else {
-+				results->outstanding_chunk_request_limit[i] =
-+					bw_ceil(
-+						bw_div(
-+							results->adjusted_data_buffer_size[i],
-+							results->pipe_chunk_size_in_bytes[i]),
-+						int_to_fixed(1));
-+			}
-+		}
-+	}
-+	if (mode_data->number_of_displays > 1
-+		|| (neq(mode_data->graphics_rotation_angle, int_to_fixed(0))
-+			&& neq(mode_data->graphics_rotation_angle,
-+				int_to_fixed(180)))) {
-+		results->peak_pte_request_to_eviction_ratio_limiting =
-+			dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
-+	} else {
-+		results->peak_pte_request_to_eviction_ratio_limiting =
-+			dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]
-+			&& results->scatter_gather_enable_for_pipe[i] == true) {
-+			if (tiling_mode[i] == def_linear) {
-+				results->useful_pte_per_pte_request =
-+					int_to_fixed(8);
-+				results->scatter_gather_page_width[i] = bw_div(
-+					int_to_fixed(4096),
-+					results->bytes_per_pixel[i]);
-+				results->scatter_gather_page_height[i] =
-+					int_to_fixed(1);
-+				results->scatter_gather_pte_request_rows =
-+					int_to_fixed(1);
-+				results->scatter_gather_row_height =
-+					dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode;
-+			} else if (equ(results->rotation_angle[i],
-+				int_to_fixed(0))
-+				|| equ(results->rotation_angle[i],
-+					int_to_fixed(180))) {
-+				results->useful_pte_per_pte_request =
-+					int_to_fixed(8);
-+				if (equ(results->bytes_per_pixel[i],
-+					int_to_fixed(4))) {
-+					results->scatter_gather_page_width[i] =
-+						int_to_fixed(32);
-+					results->scatter_gather_page_height[i] =
-+						int_to_fixed(32);
-+				} else if (equ(results->bytes_per_pixel[i],
-+					int_to_fixed(2))) {
-+					results->scatter_gather_page_width[i] =
-+						int_to_fixed(64);
-+					results->scatter_gather_page_height[i] =
-+						int_to_fixed(32);
-+				} else {
-+					results->scatter_gather_page_width[i] =
-+						int_to_fixed(64);
-+					results->scatter_gather_page_height[i] =
-+						int_to_fixed(64);
-+				}
-+				results->scatter_gather_pte_request_rows =
-+					dceip->scatter_gather_pte_request_rows_in_tiling_mode;
-+				results->scatter_gather_row_height =
-+					results->scatter_gather_page_height[i];
-+			} else {
-+				results->useful_pte_per_pte_request =
-+					int_to_fixed(1);
-+				if (equ(results->bytes_per_pixel[i],
-+					int_to_fixed(4))) {
-+					results->scatter_gather_page_width[i] =
-+						int_to_fixed(32);
-+					results->scatter_gather_page_height[i] =
-+						int_to_fixed(32);
-+				} else if (equ(results->bytes_per_pixel[i],
-+					int_to_fixed(2))) {
-+					results->scatter_gather_page_width[i] =
-+						int_to_fixed(32);
-+					results->scatter_gather_page_height[i] =
-+						int_to_fixed(64);
-+				} else
-+				// case else
-+				{
-+					results->scatter_gather_page_width[i] =
-+						int_to_fixed(64);
-+					results->scatter_gather_page_height[i] =
-+						int_to_fixed(64);
-+				}
-+				results->scatter_gather_pte_request_rows =
-+					dceip->scatter_gather_pte_request_rows_in_tiling_mode;
-+				results->scatter_gather_row_height =
-+					results->scatter_gather_page_height[i];
-+			}
-+			results->pte_request_per_chunk[i] = bw_div(
-+				bw_div(dceip->chunk_width,
-+					results->scatter_gather_page_width[i]),
-+				results->useful_pte_per_pte_request);
-+			results->scatter_gather_pte_requests_in_row[i] =
-+				bw_div(
-+					mul(results->scatter_gather_row_height,
-+						bw_ceil(
-+							mul(
-+								bw_div(
-+									results->source_width_rounded_up_to_chunks[i],
-+									dceip->chunk_width),
-+								results->pte_request_per_chunk[i]),
-+							int_to_fixed(1))),
-+					results->scatter_gather_page_height[i]);
-+			results->scatter_gather_pte_requests_in_vblank = mul(
-+				results->scatter_gather_pte_request_rows,
-+				results->scatter_gather_pte_requests_in_row[i]);
-+			if (equ(
-+				results->peak_pte_request_to_eviction_ratio_limiting,
-+				int_to_fixed(0))) {
-+				results->scatter_gather_pte_request_limit[i] =
-+					results->scatter_gather_pte_requests_in_vblank;
-+			} else {
-+				results->scatter_gather_pte_request_limit[i] =
-+					bw_max(
-+						dceip->minimum_outstanding_pte_request_limit,
-+						bw_min(
-+							results->scatter_gather_pte_requests_in_vblank,
-+							bw_ceil(
-+								mul(
-+									mul(
-+										bw_div(
-+											bw_ceil(
-+												results->adjusted_data_buffer_size[i],
-+												results->memory_chunk_size_in_bytes[i]),
-+											results->memory_chunk_size_in_bytes[i]),
-+										results->pte_request_per_chunk[i]),
-+									results->peak_pte_request_to_eviction_ratio_limiting),
-+								int_to_fixed(
-+									1))));
-+			}
-+		}
-+	}
-+	results->inefficient_linear_pitch_in_bytes = mul(
-+		mul(vbios->number_of_dram_banks,
-+			vbios->number_of_dram_channels), int_to_fixed(256));
-+	if (mode_data->underlay_surface_type == yuv_420) {
-+		results->inefficient_underlay_pitch_in_pixels =
-+			results->inefficient_linear_pitch_in_bytes;
-+	} else if (mode_data->underlay_surface_type == yuv_422) {
-+		results->inefficient_underlay_pitch_in_pixels = bw_div(
-+			results->inefficient_linear_pitch_in_bytes,
-+			int_to_fixed(2));
-+	} else
-+	// case else
-+	{
-+		results->inefficient_underlay_pitch_in_pixels = bw_div(
-+			results->inefficient_linear_pitch_in_bytes,
-+			int_to_fixed(4));
-+	}
-+	if (mode_data->underlay_tiling_mode == linear
-+		&& vbios->scatter_gather_enable == true
-+		&& mode_data->underlay_pitch_in_pixels.value
-+			% results->inefficient_underlay_pitch_in_pixels.value
-+			== false) {
-+		results->minimum_underlay_pitch_padding_recommended_for_efficiency =
-+			int_to_fixed(256);
-+	} else {
-+		results->minimum_underlay_pitch_padding_recommended_for_efficiency =
-+			int_to_fixed(0);
-+	}
-+	results->cursor_total_data = int_to_fixed(0);
-+	results->cursor_total_request_groups = int_to_fixed(0);
-+	results->scatter_gather_total_pte_requests = int_to_fixed(0);
-+	results->scatter_gather_total_pte_request_groups = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->cursor_total_data = add(
-+				results->cursor_total_data,
-+				mul(results->cursor_width_pixels[i],
-+					int_to_fixed(8)));
-+			results->cursor_total_request_groups = add(
-+				results->cursor_total_request_groups,
-+				bw_ceil(
-+					bw_div(results->cursor_width_pixels[i],
-+						dceip->cursor_chunk_width),
-+					int_to_fixed(1)));
-+			if (results->scatter_gather_enable_for_pipe[i]) {
-+				results->scatter_gather_total_pte_requests =
-+					add(
-+						results->scatter_gather_total_pte_requests,
-+						results->scatter_gather_pte_request_limit[i]);
-+				results->scatter_gather_total_pte_request_groups =
-+					add(
-+						results->scatter_gather_total_pte_request_groups,
-+						bw_ceil(
-+							bw_div(
-+								results->scatter_gather_pte_request_limit[i],
-+								bw_ceil(
-+									results->pte_request_per_chunk[i],
-+									int_to_fixed(
-+										1))),
-+							int_to_fixed(1)));
-+			}
-+		}
-+	}
-+	results->tile_width_in_pixels = int_to_fixed(8);
-+	results->dmif_total_number_of_data_request_page_close_open =
-+		int_to_fixed(0);
-+	results->mcifwr_total_number_of_data_request_page_close_open =
-+		int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (results->scatter_gather_enable_for_pipe[i] == true
-+				&& tiling_mode[i] != def_linear) {
-+				results->bytes_per_page_close_open =
-+					mul(
-+						results->lines_interleaved_in_mem_access[i],
-+						bw_max(
-+							mul(
-+								mul(
-+									mul(
-+										results->bytes_per_pixel[i],
-+										results->tile_width_in_pixels),
-+									vbios->number_of_dram_banks),
-+								vbios->number_of_dram_channels),
-+							mul(
-+								results->bytes_per_pixel[i],
-+								results->scatter_gather_page_width[i])));
-+			} else if (results->scatter_gather_enable_for_pipe[i]
-+				== true && tiling_mode[i] == def_linear
-+				&& (mul(
-+					results->pitch_in_pixels_after_surface_type[i],
-+					results->bytes_per_pixel[i])).value
-+					% results->inefficient_linear_pitch_in_bytes.value
-+					== false) {
-+				results->bytes_per_page_close_open =
-+					dceip->linear_mode_line_request_alternation_slice;
-+			} else {
-+				results->bytes_per_page_close_open =
-+					results->memory_chunk_size_in_bytes[i];
-+			}
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma) {
-+				results->dmif_total_number_of_data_request_page_close_open =
-+					add(
-+						results->dmif_total_number_of_data_request_page_close_open,
-+						bw_div(
-+							bw_ceil(
-+								results->adjusted_data_buffer_size[i],
-+								results->memory_chunk_size_in_bytes[i]),
-+							results->bytes_per_page_close_open));
-+			} else {
-+				results->mcifwr_total_number_of_data_request_page_close_open =
-+					add(
-+						results->mcifwr_total_number_of_data_request_page_close_open,
-+						bw_div(
-+							bw_ceil(
-+								results->adjusted_data_buffer_size[i],
-+								results->memory_chunk_size_in_bytes[i]),
-+							results->bytes_per_page_close_open));
-+			}
-+		}
-+	}
-+	results->dmif_total_page_close_open_time =
-+		bw_div(
-+			mul(
-+				(add(
-+					add(
-+						results->dmif_total_number_of_data_request_page_close_open,
-+						results->scatter_gather_total_pte_request_groups),
-+					results->cursor_total_request_groups)),
-+				vbios->trc), int_to_fixed(1000));
-+	results->mcifwr_total_page_close_open_time =
-+		bw_div(
-+			mul(
-+				results->mcifwr_total_number_of_data_request_page_close_open,
-+				vbios->trc), int_to_fixed(1000));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->adjusted_data_buffer_size_in_memory[i] = bw_div(
-+				mul(results->adjusted_data_buffer_size[i],
-+					results->bytes_per_request[i]),
-+				results->useful_bytes_per_request[i]);
-+		}
-+	}
-+	results->total_requests_for_adjusted_dmif_size = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma) {
-+				results->total_requests_for_adjusted_dmif_size =
-+					add(
-+						results->total_requests_for_adjusted_dmif_size,
-+						bw_div(
-+							results->adjusted_data_buffer_size[i],
-+							results->useful_bytes_per_request[i]));
-+			}
-+		}
-+	}
-+	if (equ(dceip->dcfclk_request_generation, int_to_fixed(1))) {
-+		results->total_dmifmc_urgent_trips = int_to_fixed(1);
-+	} else {
-+		results->total_dmifmc_urgent_trips =
-+			bw_ceil(
-+				bw_div(
-+					results->total_requests_for_adjusted_dmif_size,
-+					(add(dceip->dmif_request_buffer_size,
-+						mul(
-+							vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel,
-+							vbios->number_of_dram_channels)))),
-+				int_to_fixed(1));
-+	}
-+	results->total_dmifmc_urgent_latency = mul(vbios->dmifmc_urgent_latency,
-+		results->total_dmifmc_urgent_trips);
-+	results->total_display_reads_required_data = int_to_fixed(0);
-+	results->total_display_reads_required_dram_access_data = int_to_fixed(
-+		0);
-+	results->total_display_writes_required_data = int_to_fixed(0);
-+	results->total_display_writes_required_dram_access_data = int_to_fixed(
-+		0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma) {
-+				results->display_reads_required_data =
-+					results->adjusted_data_buffer_size_in_memory[i];
-+				results->display_reads_required_dram_access_data =
-+					mul(
-+						results->adjusted_data_buffer_size_in_memory[i],
-+						bw_ceil(
-+							bw_div(
-+								vbios->dram_channel_width_in_bits,
-+								results->bytes_per_request[i]),
-+							int_to_fixed(1)));
-+				if (results->access_one_channel_only[i]) {
-+					results->display_reads_required_dram_access_data =
-+						mul(
-+							results->display_reads_required_dram_access_data,
-+							vbios->number_of_dram_channels);
-+				}
-+				results->total_display_reads_required_data =
-+					add(
-+						results->total_display_reads_required_data,
-+						results->display_reads_required_data);
-+				results->total_display_reads_required_dram_access_data =
-+					add(
-+						results->total_display_reads_required_dram_access_data,
-+						results->display_reads_required_dram_access_data);
-+			} else {
-+				results->total_display_writes_required_data =
-+					add(
-+						results->total_display_writes_required_data,
-+						results->adjusted_data_buffer_size_in_memory[i]);
-+				results->total_display_writes_required_dram_access_data =
-+					add(
-+						results->total_display_writes_required_dram_access_data,
-+						mul(
-+							results->adjusted_data_buffer_size_in_memory[i],
-+							bw_ceil(
-+								bw_div(
-+									vbios->dram_channel_width_in_bits,
-+									results->bytes_per_request[i]),
-+								int_to_fixed(
-+									1))));
-+			}
-+		}
-+	}
-+	results->total_display_reads_required_data = add(
-+		add(results->total_display_reads_required_data,
-+			results->cursor_total_data),
-+		mul(results->scatter_gather_total_pte_requests,
-+			int_to_fixed(64)));
-+	results->total_display_reads_required_dram_access_data = add(
-+		add(results->total_display_reads_required_dram_access_data,
-+			results->cursor_total_data),
-+		mul(results->scatter_gather_total_pte_requests,
-+			int_to_fixed(64)));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (gtn(results->v_filter_init[i], int_to_fixed(4))) {
-+				results->src_pixels_for_first_output_pixel[i] =
-+					mul(
-+						results->source_width_rounded_up_to_chunks[i],
-+						int_to_fixed(4));
-+			} else {
-+				if (gtn(results->v_filter_init[i],
-+					int_to_fixed(2))) {
-+					results->src_pixels_for_first_output_pixel[i] =
-+						int_to_fixed(512);
-+				} else {
-+					results->src_pixels_for_first_output_pixel[i] =
-+						int_to_fixed(0);
-+				}
-+			}
-+			results->src_data_for_first_output_pixel[i] =
-+				bw_div(
-+					mul(
-+						mul(
-+							results->src_pixels_for_first_output_pixel[i],
-+							results->bytes_per_pixel[i]),
-+						results->bytes_per_request[i]),
-+					results->useful_bytes_per_request[i]);
-+			results->src_pixels_for_last_output_pixel[i] =
-+				mul(
-+					results->source_width_rounded_up_to_chunks[i],
-+					bw_max(
-+						bw_ceil(
-+							results->v_filter_init[i],
-+							dceip->lines_interleaved_into_lb),
-+						mul(
-+							results->horizontal_blank_and_chunk_granularity_factor[i],
-+							bw_ceil(results->vsr[i],
-+								dceip->lines_interleaved_into_lb))));
-+			results->src_data_for_last_output_pixel[i] =
-+				bw_div(
-+					mul(
-+						mul(
-+							mul(
-+								results->source_width_rounded_up_to_chunks[i],
-+								bw_max(
-+									bw_ceil(
-+										results->v_filter_init[i],
-+										dceip->lines_interleaved_into_lb),
-+									results->lines_interleaved_in_mem_access[i])),
-+							results->bytes_per_pixel[i]),
-+						results->bytes_per_request[i]),
-+					results->useful_bytes_per_request[i]);
-+			results->active_time[i] =
-+				bw_div(
-+					bw_div(
-+						results->source_width_rounded_up_to_chunks[i],
-+						results->hsr[i]),
-+					results->pixel_rate[i]);
-+		}
-+	}
-+	for (i = 0; i <= 2; i += 1) {
-+		for (j = 0; j <= 2; j += 1) {
-+			results->dmif_burst_time[i][j] =
-+				bw_max3(
-+					results->dmif_total_page_close_open_time,
-+					bw_div(
-+						results->total_display_reads_required_dram_access_data,
-+						(mul(
-+							bw_div(
-+								mul(yclk[i],
-+									vbios->dram_channel_width_in_bits),
-+								int_to_fixed(
-+									8)),
-+							vbios->number_of_dram_channels))),
-+					bw_div(
-+						results->total_display_reads_required_data,
-+						(mul(sclk[j],
-+							vbios->data_return_bus_width))));
-+			if (mode_data->d1_display_write_back_dwb_enable
-+				== true) {
-+				results->mcifwr_burst_time[i][j] =
-+					bw_max3(
-+						results->mcifwr_total_page_close_open_time,
-+						bw_div(
-+							results->total_display_writes_required_dram_access_data,
-+							(mul(
-+								bw_div(
-+									mul(
-+										yclk[i],
-+										vbios->dram_channel_width_in_bits),
-+									int_to_fixed(
-+										8)),
-+								vbios->number_of_dram_channels))),
-+						bw_div(
-+							results->total_display_writes_required_data,
-+							(mul(sclk[j],
-+								vbios->data_return_bus_width))));
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		for (j = 0; j <= 2; j += 1) {
-+			for (k = 0; k <= 2; k += 1) {
-+				if (results->enable[i]) {
-+					if (surface_type[i]
-+						!= def_display_write_back420_luma
-+						&& surface_type[i]
-+							!= def_display_write_back420_chroma) {
-+						results->line_source_transfer_time[i][j][k] =
-+							bw_max(
-+								mul(
-+									(add(
-+										results->total_dmifmc_urgent_latency,
-+										results->dmif_burst_time[j][k])),
-+									bw_floor(
-+										bw_div(
-+											results->src_data_for_first_output_pixel[i],
-+											results->adjusted_data_buffer_size_in_memory[i]),
-+										int_to_fixed(
-+											1))),
-+								sub(
-+									mul(
-+										(add(
-+											results->total_dmifmc_urgent_latency,
-+											results->dmif_burst_time[j][k])),
-+										bw_floor(
-+											bw_div(
-+												results->src_data_for_last_output_pixel[i],
-+												results->adjusted_data_buffer_size_in_memory[i]),
-+											int_to_fixed(
-+												1))),
-+									results->active_time[i]));
-+					} else {
-+						results->line_source_transfer_time[i][j][k] =
-+							bw_max(
-+								mul(
-+									(add(
-+										vbios->mcifwrmc_urgent_latency,
-+										results->mcifwr_burst_time[j][k])),
-+									bw_floor(
-+										bw_div(
-+											results->src_data_for_first_output_pixel[i],
-+											results->adjusted_data_buffer_size_in_memory[i]),
-+										int_to_fixed(
-+											1))),
-+								sub(
-+									mul(
-+										(add(
-+											vbios->mcifwrmc_urgent_latency,
-+											results->mcifwr_burst_time[j][k])),
-+										bw_floor(
-+											bw_div(
-+												results->src_data_for_last_output_pixel[i],
-+												results->adjusted_data_buffer_size_in_memory[i]),
-+											int_to_fixed(
-+												1))),
-+									results->active_time[i]));
-+					}
-+				}
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (equ(
-+				dceip->stutter_and_dram_clock_state_change_gated_before_cursor,
-+				int_to_fixed(0))
-+				&& gtn(results->cursor_width_pixels[i],
-+					int_to_fixed(0))) {
-+				if (ltn(results->vsr[i], int_to_fixed(2))) {
-+					results->cursor_latency_hiding[i] =
-+						bw_div(
-+							bw_div(
-+								mul(
-+									(sub(
-+										dceip->cursor_dcp_buffer_lines,
-+										int_to_fixed(
-+											1))),
-+									results->h_total[i]),
-+								results->vsr[i]),
-+							results->pixel_rate[i]);
-+				} else {
-+					results->cursor_latency_hiding[i] =
-+						bw_div(
-+							bw_div(
-+								mul(
-+									(sub(
-+										dceip->cursor_dcp_buffer_lines,
-+										int_to_fixed(
-+											3))),
-+									results->h_total[i]),
-+								results->vsr[i]),
-+							results->pixel_rate[i]);
-+				}
-+			} else {
-+				results->cursor_latency_hiding[i] =
-+					int_to_fixed(9999);
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (dceip->graphics_lb_nodownscaling_multi_line_prefetching
-+				== true
-+				&& (equ(results->vsr[i], int_to_fixed(1))
-+					|| (leq(results->vsr[i],
-+						frc_to_fixed(8, 10))
-+						&& leq(results->v_taps[i],
-+							int_to_fixed(2))
-+						&& equ(results->lb_bpc[i],
-+							int_to_fixed(8))))
-+				&& surface_type[i] == def_graphics) {
-+				results->minimum_latency_hiding[i] =
-+					sub(
-+						sub(
-+							add(
-+								bw_div(
-+									mul(
-+										bw_div(
-+											(bw_div(
-+												bw_div(
-+													results->data_buffer_size[i],
-+													results->bytes_per_pixel[i]),
-+												results->source_width_pixels[i])),
-+											results->vsr[i]),
-+										results->h_total[i]),
-+									results->pixel_rate[i]),
-+								results->lb_partitions[i]),
-+							int_to_fixed(1)),
-+						results->total_dmifmc_urgent_latency);
-+			} else {
-+				results->minimum_latency_hiding[i] =
-+					sub(
-+						bw_div(
-+							mul(
-+								(add(
-+									add(
-+										results->line_buffer_prefetch[i],
-+										int_to_fixed(
-+											1)),
-+									bw_div(
-+										bw_div(
-+											bw_div(
-+												results->data_buffer_size[i],
-+												results->bytes_per_pixel[i]),
-+											results->source_width_pixels[i]),
-+										results->vsr[i]))),
-+								results->h_total[i]),
-+							results->pixel_rate[i]),
-+						results->total_dmifmc_urgent_latency);
-+			}
-+			results->minimum_latency_hiding_with_cursor[i] = bw_min(
-+				results->minimum_latency_hiding[i],
-+				results->cursor_latency_hiding[i]);
-+		}
-+	}
-+	for (i = 0; i <= 2; i += 1) {
-+		for (j = 0; j <= 2; j += 1) {
-+			results->blackout_duration_margin[i][j] = int_to_fixed(
-+				9999);
-+			results->dispclk_required_for_blackout_duration[i][j] =
-+				int_to_fixed(0);
-+			results->dispclk_required_for_blackout_recovery[i][j] =
-+				int_to_fixed(0);
-+			for (k = 0; k <= maximum_number_of_surfaces - 1; k +=
-+				1) {
-+				if (results->enable[k]
-+					&& gtn(vbios->blackout_duration,
-+						int_to_fixed(0))) {
-+					if (surface_type[k]
-+						!= def_display_write_back420_luma
-+						&& surface_type[k]
-+							!= def_display_write_back420_chroma) {
-+						results->blackout_duration_margin[i][j] =
-+							bw_min(
-+								results->blackout_duration_margin[i][j],
-+								sub(
-+									sub(
-+										sub(
-+											results->minimum_latency_hiding_with_cursor[k],
-+											vbios->blackout_duration),
-+										results->dmif_burst_time[i][j]),
-+									results->line_source_transfer_time[k][i][j]));
-+						results->dispclk_required_for_blackout_duration[i][j] =
-+							bw_max3(
-+								results->dispclk_required_for_blackout_duration[i][j],
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_first_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(sub(
-+										sub(
-+											results->minimum_latency_hiding_with_cursor[k],
-+											vbios->blackout_duration),
-+										results->dmif_burst_time[i][j]))),
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_last_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(add(
-+										sub(
-+											sub(
-+												results->minimum_latency_hiding_with_cursor[k],
-+												vbios->blackout_duration),
-+											results->dmif_burst_time[i][j]),
-+										results->active_time[k]))));
-+						if (leq(
-+							vbios->maximum_blackout_recovery_time,
-+							add(
-+								mul(
-+									results->total_dmifmc_urgent_latency,
-+									int_to_fixed(
-+										2)),
-+								results->dmif_burst_time[i][j]))) {
-+							results->dispclk_required_for_blackout_recovery[i][j] =
-+								int_to_fixed(
-+									9999);
-+						} else if (ltn(
-+							results->adjusted_data_buffer_size[k],
-+							mul(
-+								bw_div(
-+									mul(
-+										results->display_bandwidth[k],
-+										results->useful_bytes_per_request[k]),
-+									results->bytes_per_request[k]),
-+								(add(
-+									add(
-+										vbios->blackout_duration,
-+										mul(
-+											results->total_dmifmc_urgent_latency,
-+											int_to_fixed(
-+												2))),
-+									results->dmif_burst_time[i][j]))))) {
-+							results->dispclk_required_for_blackout_recovery[i][j] =
-+								bw_max(
-+									results->dispclk_required_for_blackout_recovery[i][j],
-+									bw_div(
-+										mul(
-+											bw_div(
-+												bw_div(
-+													(sub(
-+														mul(
-+															bw_div(
-+																mul(
-+																	results->display_bandwidth[k],
-+																	results->useful_bytes_per_request[k]),
-+																results->bytes_per_request[k]),
-+															(add(
-+																vbios->blackout_duration,
-+																vbios->maximum_blackout_recovery_time))),
-+														results->adjusted_data_buffer_size[k])),
-+													results->bytes_per_pixel[k]),
-+												(sub(
-+													sub(
-+														vbios->maximum_blackout_recovery_time,
-+														mul(
-+															results->total_dmifmc_urgent_latency,
-+															int_to_fixed(
-+																2))),
-+													results->dmif_burst_time[i][j]))),
-+											results->latency_hiding_lines[k]),
-+										results->lines_interleaved_in_mem_access[k]));
-+						}
-+					} else {
-+						results->blackout_duration_margin[i][j] =
-+							bw_min(
-+								results->blackout_duration_margin[i][j],
-+								sub(
-+									sub(
-+										sub(
-+											sub(
-+												results->minimum_latency_hiding_with_cursor[k],
-+												vbios->blackout_duration),
-+											results->dmif_burst_time[i][j]),
-+										results->mcifwr_burst_time[i][j]),
-+									results->line_source_transfer_time[k][i][j]));
-+						results->dispclk_required_for_blackout_duration[i][j] =
-+							bw_max3(
-+								results->dispclk_required_for_blackout_duration[i][j],
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_first_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(sub(
-+										sub(
-+											sub(
-+												results->minimum_latency_hiding_with_cursor[k],
-+												vbios->blackout_duration),
-+											results->dmif_burst_time[i][j]),
-+										results->mcifwr_burst_time[i][j]))),
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_last_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(add(
-+										sub(
-+											sub(
-+												sub(
-+													results->minimum_latency_hiding_with_cursor[k],
-+													vbios->blackout_duration),
-+												results->dmif_burst_time[i][j]),
-+											results->mcifwr_burst_time[i][j]),
-+										results->active_time[k]))));
-+						if (ltn(
-+							vbios->maximum_blackout_recovery_time,
-+							add(
-+								add(
-+									mul(
-+										vbios->mcifwrmc_urgent_latency,
-+										int_to_fixed(
-+											2)),
-+									results->dmif_burst_time[i][j]),
-+								results->mcifwr_burst_time[i][j]))) {
-+							results->dispclk_required_for_blackout_recovery[i][j] =
-+								int_to_fixed(
-+									9999);
-+						} else if (ltn(
-+							results->adjusted_data_buffer_size[k],
-+							mul(
-+								bw_div(
-+									mul(
-+										results->display_bandwidth[k],
-+										results->useful_bytes_per_request[k]),
-+									results->bytes_per_request[k]),
-+								(add(
-+									add(
-+										vbios->blackout_duration,
-+										mul(
-+											results->total_dmifmc_urgent_latency,
-+											int_to_fixed(
-+												2))),
-+									results->dmif_burst_time[i][j]))))) {
-+							results->dispclk_required_for_blackout_recovery[i][j] =
-+								bw_max(
-+									results->dispclk_required_for_blackout_recovery[i][j],
-+									bw_div(
-+										mul(
-+											bw_div(
-+												bw_div(
-+													(sub(
-+														mul(
-+															bw_div(
-+																mul(
-+																	results->display_bandwidth[k],
-+																	results->useful_bytes_per_request[k]),
-+																results->bytes_per_request[k]),
-+															(add(
-+																vbios->blackout_duration,
-+																vbios->maximum_blackout_recovery_time))),
-+														results->adjusted_data_buffer_size[k])),
-+													results->bytes_per_pixel[k]),
-+												(sub(
-+													vbios->maximum_blackout_recovery_time,
-+													(add(
-+														mul(
-+															results->total_dmifmc_urgent_latency,
-+															int_to_fixed(
-+																2)),
-+														results->dmif_burst_time[i][j]))))),
-+											results->latency_hiding_lines[k]),
-+										results->lines_interleaved_in_mem_access[k]));
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	if (gtn(results->blackout_duration_margin[high][high], int_to_fixed(0))
-+		&& ltn(
-+			results->dispclk_required_for_blackout_duration[high][high],
-+			vbios->high_voltage_max_dispclk)) {
-+		results->cpup_state_change_enable = true;
-+		if (ltn(
-+			results->dispclk_required_for_blackout_recovery[high][high],
-+			vbios->high_voltage_max_dispclk)) {
-+			results->cpuc_state_change_enable = true;
-+		} else {
-+			results->cpuc_state_change_enable = false;
-+		}
-+	} else {
-+		results->cpup_state_change_enable = false;
-+		results->cpuc_state_change_enable = false;
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (mode_data->number_of_displays <= 1
-+				|| mode_data->display_synchronization_enabled
-+					== true) {
-+				results->maximum_latency_hiding[i] =
-+					int_to_fixed(450);
-+			} else {
-+				results->maximum_latency_hiding[i] =
-+					add(
-+						add(
-+							results->minimum_latency_hiding[i],
-+							bw_div(
-+								mul(
-+									bw_div(
-+										int_to_fixed(
-+											1),
-+										results->vsr[i]),
-+									results->h_total[i]),
-+								results->pixel_rate[i])),
-+						mul(frc_to_fixed(1, 2),
-+							results->total_dmifmc_urgent_latency));
-+			}
-+			results->maximum_latency_hiding_with_cursor[i] = bw_min(
-+				results->maximum_latency_hiding[i],
-+				results->cursor_latency_hiding[i]);
-+		}
-+	}
-+	for (i = 0; i <= 2; i += 1) {
-+		for (j = 0; j <= 2; j += 1) {
-+			results->dram_speed_change_margin[i][j] = int_to_fixed(
-+				9999);
-+			results->dispclk_required_for_dram_speed_change[i][j] =
-+				int_to_fixed(0);
-+			for (k = 0; k <= maximum_number_of_surfaces - 1; k +=
-+				1) {
-+				if (results->enable[k]) {
-+					if (surface_type[k]
-+						!= def_display_write_back420_luma
-+						&& surface_type[k]
-+							!= def_display_write_back420_chroma) {
-+						results->dram_speed_change_margin[i][j] =
-+							bw_min(
-+								results->dram_speed_change_margin[i][j],
-+								sub(
-+									sub(
-+										sub(
-+											results->maximum_latency_hiding_with_cursor[k],
-+											vbios->nbp_state_change_latency),
-+										results->dmif_burst_time[i][j]),
-+									results->line_source_transfer_time[k][i][j]));
-+						results->dispclk_required_for_dram_speed_change[i][j] =
-+							bw_max3(
-+								results->dispclk_required_for_dram_speed_change[i][j],
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_first_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(sub(
-+										sub(
-+											results->maximum_latency_hiding_with_cursor[k],
-+											vbios->nbp_state_change_latency),
-+										results->dmif_burst_time[i][j]))),
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_last_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(add(
-+										sub(
-+											sub(
-+												results->maximum_latency_hiding_with_cursor[k],
-+												vbios->nbp_state_change_latency),
-+											results->dmif_burst_time[i][j]),
-+										results->active_time[k]))));
-+					} else {
-+						results->dram_speed_change_margin[i][j] =
-+							bw_min(
-+								results->dram_speed_change_margin[i][j],
-+								sub(
-+									sub(
-+										sub(
-+											sub(
-+												results->maximum_latency_hiding_with_cursor[k],
-+												vbios->nbp_state_change_latency),
-+											results->dmif_burst_time[i][j]),
-+										results->mcifwr_burst_time[i][j]),
-+									results->line_source_transfer_time[k][i][j]));
-+						results->dispclk_required_for_dram_speed_change[i][j] =
-+							bw_max3(
-+								results->dispclk_required_for_dram_speed_change[i][j],
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_first_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(sub(
-+										sub(
-+											sub(
-+												results->maximum_latency_hiding_with_cursor[k],
-+												vbios->nbp_state_change_latency),
-+											results->dmif_burst_time[i][j]),
-+										results->mcifwr_burst_time[i][j]))),
-+								bw_div(
-+									bw_div(
-+										mul(
-+											results->src_pixels_for_last_output_pixel[k],
-+											dceip->display_pipe_throughput_factor),
-+										dceip->lb_write_pixels_per_dispclk),
-+									(add(
-+										sub(
-+											sub(
-+												sub(
-+													results->maximum_latency_hiding_with_cursor[k],
-+													vbios->nbp_state_change_latency),
-+												results->dmif_burst_time[i][j]),
-+											results->mcifwr_burst_time[i][j]),
-+										results->active_time[k]))));
-+					}
-+				}
-+			}
-+		}
-+	}
-+	if (gtn(results->dram_speed_change_margin[high][high], int_to_fixed(0))
-+		&& ltn(
-+			results->dispclk_required_for_dram_speed_change[high][high],
-+			vbios->high_voltage_max_dispclk)) {
-+		results->nbp_state_change_enable = true;
-+	} else {
-+		results->nbp_state_change_enable = false;
-+	}
-+	results->min_cursor_memory_interface_buffer_size_in_time = int_to_fixed(
-+		9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (gtn(results->cursor_width_pixels[i],
-+				int_to_fixed(0))) {
-+				results->min_cursor_memory_interface_buffer_size_in_time =
-+					bw_min(
-+						results->min_cursor_memory_interface_buffer_size_in_time,
-+						bw_div(
-+							mul(
-+								bw_div(
-+									bw_div(
-+										dceip->cursor_memory_interface_buffer_pixels,
-+										results->cursor_width_pixels[i]),
-+									results->vsr[i]),
-+								results->h_total[i]),
-+							results->pixel_rate[i]));
-+			}
-+		}
-+	}
-+	results->min_read_buffer_size_in_time = bw_min(
-+		results->min_cursor_memory_interface_buffer_size_in_time,
-+		results->min_dmif_size_in_time);
-+	results->display_reads_time_for_data_transfer = sub(
-+		results->min_read_buffer_size_in_time,
-+		results->total_dmifmc_urgent_latency);
-+	results->display_writes_time_for_data_transfer = sub(
-+		results->min_mcifwr_size_in_time,
-+		vbios->mcifwrmc_urgent_latency);
-+	results->dmif_required_dram_bandwidth = bw_div(
-+		results->total_display_reads_required_dram_access_data,
-+		results->display_reads_time_for_data_transfer);
-+	results->mcifwr_required_dram_bandwidth = bw_div(
-+		results->total_display_writes_required_dram_access_data,
-+		results->display_writes_time_for_data_transfer);
-+	results->required_dmifmc_urgent_latency_for_page_close_open = bw_div(
-+		(sub(results->min_read_buffer_size_in_time,
-+			results->dmif_total_page_close_open_time)),
-+		results->total_dmifmc_urgent_trips);
-+	results->required_mcifmcwr_urgent_latency = sub(
-+		results->min_mcifwr_size_in_time,
-+		results->mcifwr_total_page_close_open_time);
-+	if (gtn(results->scatter_gather_total_pte_requests,
-+		dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
-+		results->required_dram_bandwidth_gbyte_per_second =
-+			int_to_fixed(9999);
-+		yclk_message =
-+			def_exceeded_allowed_outstanding_pte_req_queue_size;
-+		y_clk_level = high;
-+		results->dram_bandwidth = mul(
-+			bw_div(
-+				mul(vbios->high_yclk,
-+					vbios->dram_channel_width_in_bits),
-+				int_to_fixed(8)),
-+			vbios->number_of_dram_channels);
-+	} else if (gtn(vbios->dmifmc_urgent_latency,
-+		results->required_dmifmc_urgent_latency_for_page_close_open)
-+		|| gtn(vbios->mcifwrmc_urgent_latency,
-+			results->required_mcifmcwr_urgent_latency)) {
-+		results->required_dram_bandwidth_gbyte_per_second =
-+			int_to_fixed(9999);
-+		yclk_message = def_exceeded_allowed_page_close_open;
-+		y_clk_level = high;
-+		results->dram_bandwidth = mul(
-+			bw_div(
-+				mul(vbios->high_yclk,
-+					vbios->dram_channel_width_in_bits),
-+				int_to_fixed(8)),
-+			vbios->number_of_dram_channels);
-+	} else {
-+		results->required_dram_bandwidth_gbyte_per_second = bw_div(
-+			bw_max(results->dmif_required_dram_bandwidth,
-+				results->mcifwr_required_dram_bandwidth),
-+			int_to_fixed(1000));
-+		if (ltn(
-+			mul(results->required_dram_bandwidth_gbyte_per_second,
-+				int_to_fixed(1000)),
-+			mul(
-+				bw_div(
-+					mul(vbios->low_yclk,
-+						vbios->dram_channel_width_in_bits),
-+					int_to_fixed(8)),
-+				vbios->number_of_dram_channels))
-+			&& (results->cpup_state_change_enable == false
-+				|| (gtn(
-+					results->blackout_duration_margin[low][high],
-+					int_to_fixed(0))
-+					&& ltn(
-+						results->dispclk_required_for_blackout_duration[low][high],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->cpuc_state_change_enable == false
-+				|| (gtn(
-+					results->blackout_duration_margin[low][high],
-+					int_to_fixed(0))
-+					&& ltn(
-+						results->dispclk_required_for_blackout_duration[low][high],
-+						vbios->high_voltage_max_dispclk)
-+					&& ltn(
-+						results->dispclk_required_for_blackout_recovery[low][high],
-+						vbios->high_voltage_max_dispclk)))
-+			&& gtn(results->dram_speed_change_margin[low][high],
-+				int_to_fixed(0))
-+			&& ltn(
-+				results->dispclk_required_for_dram_speed_change[low][high],
-+				vbios->high_voltage_max_dispclk)) {
-+			yclk_message = def_low;
-+			y_clk_level = low;
-+			results->dram_bandwidth =
-+				mul(
-+					bw_div(
-+						mul(vbios->low_yclk,
-+							vbios->dram_channel_width_in_bits),
-+						int_to_fixed(8)),
-+					vbios->number_of_dram_channels);
-+		} else if (ltn(
-+			mul(results->required_dram_bandwidth_gbyte_per_second,
-+				int_to_fixed(1000)),
-+			mul(
-+				bw_div(
-+					mul(vbios->high_yclk,
-+						vbios->dram_channel_width_in_bits),
-+					int_to_fixed(8)),
-+				vbios->number_of_dram_channels))) {
-+			yclk_message = def_high;
-+			y_clk_level = high;
-+			results->dram_bandwidth =
-+				mul(
-+					bw_div(
-+						mul(vbios->high_yclk,
-+							vbios->dram_channel_width_in_bits),
-+						int_to_fixed(8)),
-+					vbios->number_of_dram_channels);
-+		} else {
-+			yclk_message = def_exceeded_allowed_maximum_bw;
-+			y_clk_level = high;
-+			results->dram_bandwidth =
-+				mul(
-+					bw_div(
-+						mul(vbios->high_yclk,
-+							vbios->dram_channel_width_in_bits),
-+						int_to_fixed(8)),
-+					vbios->number_of_dram_channels);
-+		}
-+	}
-+	results->dmif_required_sclk = bw_div(
-+		bw_div(results->total_display_reads_required_data,
-+			results->display_reads_time_for_data_transfer),
-+		vbios->data_return_bus_width);
-+	results->mcifwr_required_sclk = bw_div(
-+		bw_div(results->total_display_writes_required_data,
-+			results->display_writes_time_for_data_transfer),
-+		vbios->data_return_bus_width);
-+	if (gtn(results->scatter_gather_total_pte_requests,
-+		dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
-+		results->required_sclk = int_to_fixed(9999);
-+		sclk_message =
-+			def_exceeded_allowed_outstanding_pte_req_queue_size;
-+		sclk_level = high;
-+	} else if (gtn(vbios->dmifmc_urgent_latency,
-+		results->required_dmifmc_urgent_latency_for_page_close_open)
-+		|| gtn(vbios->mcifwrmc_urgent_latency,
-+			results->required_mcifmcwr_urgent_latency)) {
-+		results->required_sclk = int_to_fixed(9999);
-+		sclk_message = def_exceeded_allowed_page_close_open;
-+		sclk_level = high;
-+	} else {
-+		results->required_sclk = bw_max(results->dmif_required_sclk,
-+			results->mcifwr_required_sclk);
-+		if (ltn(results->required_sclk, vbios->low_sclk)
-+			&& (results->cpup_state_change_enable == false
-+				|| (gtn(
-+					results->blackout_duration_margin[y_clk_level][low],
-+					int_to_fixed(0))
-+					&& ltn(
-+						results->dispclk_required_for_blackout_duration[y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->cpuc_state_change_enable == false
-+				|| (gtn(
-+					results->blackout_duration_margin[y_clk_level][low],
-+					int_to_fixed(0))
-+					&& ltn(
-+						results->dispclk_required_for_blackout_duration[y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)
-+					&& ltn(
-+						results->dispclk_required_for_blackout_recovery[y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->nbp_state_change_enable == false
-+				|| (gtn(
-+					results->dram_speed_change_margin[y_clk_level][low],
-+					int_to_fixed(0))
-+					&& leq(
-+						results->dispclk_required_for_dram_speed_change[y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)))) {
-+			sclk_message = def_low;
-+			sclk_level = low;
-+		} else if (ltn(results->required_sclk, vbios->mid_sclk)
-+			&& (results->cpup_state_change_enable == false
-+				|| (gtn(
-+					results->blackout_duration_margin[y_clk_level][mid],
-+					int_to_fixed(0))
-+					&& ltn(
-+						results->dispclk_required_for_blackout_duration[y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->cpuc_state_change_enable == false
-+				|| (gtn(
-+					results->blackout_duration_margin[y_clk_level][mid],
-+					int_to_fixed(0))
-+					&& ltn(
-+						results->dispclk_required_for_blackout_duration[y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)
-+					&& ltn(
-+						results->dispclk_required_for_blackout_recovery[y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->nbp_state_change_enable == false
-+				|| (gtn(
-+					results->dram_speed_change_margin[y_clk_level][mid],
-+					int_to_fixed(0))
-+					&& leq(
-+						results->dispclk_required_for_dram_speed_change[y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)))) {
-+			sclk_message = def_mid;
-+			sclk_level = mid;
-+		} else if (ltn(results->required_sclk, vbios->high_sclk)) {
-+			sclk_message = def_high;
-+			sclk_level = high;
-+		} else {
-+			sclk_message = def_exceeded_allowed_maximum_sclk;
-+			sclk_level = high;
-+		}
-+	}
-+	results->downspread_factor = add(
-+		bw_div(vbios->down_spread_percentage, int_to_fixed(100)),
-+		int_to_fixed(1));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] == def_graphics) {
-+				if (equ(results->lb_bpc[i], int_to_fixed(6))) {
-+					results->v_scaler_efficiency =
-+						dceip->graphics_vscaler_efficiency6_bit_per_component;
-+				} else if (equ(results->lb_bpc[i],
-+					int_to_fixed(8))) {
-+					results->v_scaler_efficiency =
-+						dceip->graphics_vscaler_efficiency8_bit_per_component;
-+				} else if (equ(results->lb_bpc[i],
-+					int_to_fixed(10))) {
-+					results->v_scaler_efficiency =
-+						dceip->graphics_vscaler_efficiency10_bit_per_component;
-+				} else {
-+					results->v_scaler_efficiency =
-+						dceip->graphics_vscaler_efficiency12_bit_per_component;
-+				}
-+				if (results->use_alpha[i] == true) {
-+					results->v_scaler_efficiency =
-+						bw_min(
-+							results->v_scaler_efficiency,
-+							dceip->alpha_vscaler_efficiency);
-+				}
-+			} else {
-+				if (equ(results->lb_bpc[i], int_to_fixed(6))) {
-+					results->v_scaler_efficiency =
-+						dceip->underlay_vscaler_efficiency6_bit_per_component;
-+				} else if (equ(results->lb_bpc[i],
-+					int_to_fixed(8))) {
-+					results->v_scaler_efficiency =
-+						dceip->underlay_vscaler_efficiency8_bit_per_component;
-+				} else if (equ(results->lb_bpc[i],
-+					int_to_fixed(10))) {
-+					results->v_scaler_efficiency =
-+						dceip->underlay_vscaler_efficiency10_bit_per_component;
-+				} else {
-+					results->v_scaler_efficiency =
-+						dceip->underlay_vscaler_efficiency12_bit_per_component;
-+				}
-+			}
-+			if (dceip->pre_downscaler_enabled
-+				&& gtn(results->hsr[i], int_to_fixed(1))) {
-+				results->scaler_limits_factor =
-+					bw_max(
-+						bw_div(results->v_taps[i],
-+							results->v_scaler_efficiency),
-+						bw_div(
-+							results->source_width_rounded_up_to_chunks[i],
-+							results->h_total[i]));
-+			} else {
-+				results->scaler_limits_factor =
-+					bw_max3(int_to_fixed(1),
-+						bw_ceil(
-+							bw_div(results->h_taps[i],
-+								int_to_fixed(
-+									4)),
-+							int_to_fixed(1)),
-+						mul(results->hsr[i],
-+							bw_max(
-+								bw_div(
-+									results->v_taps[i],
-+									results->v_scaler_efficiency),
-+								int_to_fixed(
-+									1))));
-+			}
-+			results->display_pipe_pixel_throughput =
-+				bw_div(
-+					bw_div(
-+						mul(
-+							bw_max(
-+								results->lb_lines_in_per_line_out_in_beginning_of_frame[i],
-+								mul(
-+									results->lb_lines_in_per_line_out_in_middle_of_frame[i],
-+									results->horizontal_blank_and_chunk_granularity_factor[i])),
-+							results->source_width_rounded_up_to_chunks[i]),
-+						(bw_div(results->h_total[i],
-+							results->pixel_rate[i]))),
-+					dceip->lb_write_pixels_per_dispclk);
-+			results->dispclk_required_without_ramping[i] =
-+				mul(results->downspread_factor,
-+					bw_max(
-+						mul(results->pixel_rate[i],
-+							results->scaler_limits_factor),
-+						mul(
-+							dceip->display_pipe_throughput_factor,
-+							results->display_pipe_pixel_throughput)));
-+			results->dispclk_required_with_ramping[i] =
-+				mul(dceip->dispclk_ramping_factor,
-+					bw_max(
-+						mul(results->pixel_rate[i],
-+							results->scaler_limits_factor),
-+						results->display_pipe_pixel_throughput));
-+		}
-+	}
-+	results->total_dispclk_required_with_ramping = int_to_fixed(0);
-+	results->total_dispclk_required_without_ramping = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (ltn(results->total_dispclk_required_with_ramping,
-+				results->dispclk_required_with_ramping[i])) {
-+				results->total_dispclk_required_with_ramping =
-+					results->dispclk_required_with_ramping[i];
-+			}
-+			if (ltn(results->total_dispclk_required_without_ramping,
-+				results->dispclk_required_without_ramping[i])) {
-+				results->total_dispclk_required_without_ramping =
-+					results->dispclk_required_without_ramping[i];
-+			}
-+		}
-+	}
-+	results->total_read_request_bandwidth = int_to_fixed(0);
-+	results->total_write_request_bandwidth = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma) {
-+				results->total_read_request_bandwidth = add(
-+					results->total_read_request_bandwidth,
-+					results->request_bandwidth[i]);
-+			} else {
-+				results->total_write_request_bandwidth = add(
-+					results->total_write_request_bandwidth,
-+					results->request_bandwidth[i]);
-+			}
-+		}
-+	}
-+	results->dispclk_required_for_total_read_request_bandwidth = bw_div(
-+		mul(results->total_read_request_bandwidth,
-+			dceip->dispclk_per_request), dceip->request_efficiency);
-+	if (equ(dceip->dcfclk_request_generation, int_to_fixed(0))) {
-+		results->total_dispclk_required_with_ramping_with_request_bandwidth =
-+			bw_max(results->total_dispclk_required_with_ramping,
-+				results->dispclk_required_for_total_read_request_bandwidth);
-+		results->total_dispclk_required_without_ramping_with_request_bandwidth =
-+			bw_max(results->total_dispclk_required_without_ramping,
-+				results->dispclk_required_for_total_read_request_bandwidth);
-+	} else {
-+		results->total_dispclk_required_with_ramping_with_request_bandwidth =
-+			results->total_dispclk_required_with_ramping;
-+		results->total_dispclk_required_without_ramping_with_request_bandwidth =
-+			results->total_dispclk_required_without_ramping;
-+	}
-+	if (results->cpuc_state_change_enable == true) {
-+		results->total_dispclk_required_with_ramping_with_request_bandwidth =
-+			bw_max3(
-+				results->total_dispclk_required_with_ramping_with_request_bandwidth,
-+				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level],
-+				results->dispclk_required_for_blackout_recovery[y_clk_level][sclk_level]);
-+		results->total_dispclk_required_without_ramping_with_request_bandwidth =
-+			bw_max3(
-+				results->total_dispclk_required_without_ramping_with_request_bandwidth,
-+				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level],
-+				results->dispclk_required_for_blackout_recovery[y_clk_level][sclk_level]);
-+	}
-+	if (results->cpup_state_change_enable == true) {
-+		results->total_dispclk_required_with_ramping_with_request_bandwidth =
-+			bw_max(
-+				results->total_dispclk_required_with_ramping_with_request_bandwidth,
-+				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level]);
-+		results->total_dispclk_required_without_ramping_with_request_bandwidth =
-+			bw_max(
-+				results->total_dispclk_required_without_ramping_with_request_bandwidth,
-+				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level]);
-+	}
-+	if (results->nbp_state_change_enable == true) {
-+		results->total_dispclk_required_with_ramping_with_request_bandwidth =
-+			bw_max(
-+				results->total_dispclk_required_with_ramping_with_request_bandwidth,
-+				results->dispclk_required_for_dram_speed_change[y_clk_level][sclk_level]);
-+		results->total_dispclk_required_without_ramping_with_request_bandwidth =
-+			bw_max(
-+				results->total_dispclk_required_without_ramping_with_request_bandwidth,
-+				results->dispclk_required_for_dram_speed_change[y_clk_level][sclk_level]);
-+	}
-+	if (ltn(
-+		results->total_dispclk_required_with_ramping_with_request_bandwidth,
-+		vbios->high_voltage_max_dispclk)) {
-+		results->dispclk =
-+			results->total_dispclk_required_with_ramping_with_request_bandwidth;
-+	} else if (ltn(
-+		results->total_dispclk_required_without_ramping_with_request_bandwidth,
-+		vbios->high_voltage_max_dispclk)) {
-+		results->dispclk = vbios->high_voltage_max_dispclk;
-+	} else {
-+		results->dispclk =
-+			results->total_dispclk_required_without_ramping_with_request_bandwidth;
-+	}
-+	if (pipe_check == def_notok) {
-+		voltage = def_na;
-+		mode_background_color = def_na_color;
-+		mode_font_color = def_vb_white;
-+	} else if (mode_check == def_notok) {
-+		voltage = def_notok;
-+		mode_background_color = def_notok_color;
-+		mode_font_color = def_vb_black;
-+	} else if (yclk_message == def_low && sclk_message == def_low
-+		&& ltn(results->dispclk, vbios->low_voltage_max_dispclk)) {
-+		voltage = def_low;
-+		mode_background_color = def_low_color;
-+		mode_font_color = def_vb_black;
-+	} else if (yclk_message == def_low
-+		&& (sclk_message == def_low || sclk_message == def_mid)
-+		&& ltn(results->dispclk, vbios->mid_voltage_max_dispclk)) {
-+		voltage = def_mid;
-+		mode_background_color = def_mid_color;
-+		mode_font_color = def_vb_black;
-+	} else if ((yclk_message == def_low || yclk_message == def_high)
-+		&& (sclk_message == def_low || sclk_message == def_mid
-+			|| sclk_message == def_high)
-+		&& leq(results->dispclk, vbios->high_voltage_max_dispclk)) {
-+		if (results->nbp_state_change_enable == true) {
-+			voltage = def_high;
-+			mode_background_color = def_high_color;
-+			mode_font_color = def_vb_black;
-+		} else {
-+			voltage = def_high_no_nbp_state_change;
-+			mode_background_color =
-+				def_high_no_nbp_state_change_color;
-+			mode_font_color = def_vb_black;
-+		}
-+	} else {
-+		voltage = def_notok;
-+		mode_background_color = def_notok_color;
-+		mode_font_color = def_vb_black;
-+	}
-+	if (mode_background_color == def_na_color
-+		|| mode_background_color == def_notok_color) {
-+		mode_pattern = def_xl_pattern_solid;
-+	} else if (results->cpup_state_change_enable == false) {
-+		mode_pattern = def_xl_pattern_checker;
-+	} else if (results->cpuc_state_change_enable == false) {
-+		mode_pattern = def_xl_pattern_light_horizontal;
-+	} else {
-+		mode_pattern = def_xl_pattern_solid;
-+	}
-+	results->blackout_recovery_time = int_to_fixed(0);
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k += 1) {
-+		if (results->enable[k]
-+			&& gtn(vbios->blackout_duration, int_to_fixed(0))
-+			&& results->cpup_state_change_enable == true) {
-+			if (surface_type[k] != def_display_write_back420_luma
-+				&& surface_type[k]
-+					!= def_display_write_back420_chroma) {
-+				results->blackout_recovery_time =
-+					bw_max(results->blackout_recovery_time,
-+						add(
-+							mul(
-+								results->total_dmifmc_urgent_latency,
-+								int_to_fixed(
-+									2)),
-+							results->dmif_burst_time[y_clk_level][sclk_level]));
-+				if (ltn(results->adjusted_data_buffer_size[k],
-+					mul(
-+						bw_div(
-+							mul(
-+								results->display_bandwidth[k],
-+								results->useful_bytes_per_request[k]),
-+							results->bytes_per_request[k]),
-+						(add(
-+							add(
-+								vbios->blackout_duration,
-+								mul(
-+									results->total_dmifmc_urgent_latency,
-+									int_to_fixed(
-+										2))),
-+							results->dmif_burst_time[y_clk_level][sclk_level]))))) {
-+					results->blackout_recovery_time =
-+						bw_max(
-+							results->blackout_recovery_time,
-+							bw_div(
-+								(sub(
-+									add(
-+										mul(
-+											bw_div(
-+												mul(
-+													results->display_bandwidth[k],
-+													results->useful_bytes_per_request[k]),
-+												results->bytes_per_request[k]),
-+											vbios->blackout_duration),
-+										bw_div(
-+											mul(
-+												mul(
-+													mul(
-+														(add(
-+															mul(
-+																results->total_dmifmc_urgent_latency,
-+																int_to_fixed(
-+																	2)),
-+															results->dmif_burst_time[y_clk_level][sclk_level])),
-+														results->dispclk),
-+													results->bytes_per_pixel[k]),
-+												results->lines_interleaved_in_mem_access[k]),
-+											results->latency_hiding_lines[k])),
-+									results->adjusted_data_buffer_size[k])),
-+								(sub(
-+									bw_div(
-+										mul(
-+											mul(
-+												results->dispclk,
-+												results->bytes_per_pixel[k]),
-+											results->lines_interleaved_in_mem_access[k]),
-+										results->latency_hiding_lines[k]),
-+									bw_div(
-+										mul(
-+											results->display_bandwidth[k],
-+											results->useful_bytes_per_request[k]),
-+										results->bytes_per_request[k])))));
-+				}
-+			} else {
-+				results->blackout_recovery_time =
-+					bw_max(results->blackout_recovery_time,
-+						add(
-+							mul(
-+								vbios->mcifwrmc_urgent_latency,
-+								int_to_fixed(
-+									2)),
-+							results->mcifwr_burst_time[y_clk_level][sclk_level]));
-+				if (ltn(results->adjusted_data_buffer_size[k],
-+					mul(
-+						bw_div(
-+							mul(
-+								results->display_bandwidth[k],
-+								results->useful_bytes_per_request[k]),
-+							results->bytes_per_request[k]),
-+						(add(
-+							add(
-+								vbios->blackout_duration,
-+								mul(
-+									vbios->mcifwrmc_urgent_latency,
-+									int_to_fixed(
-+										2))),
-+							results->mcifwr_burst_time[y_clk_level][sclk_level]))))) {
-+					results->blackout_recovery_time =
-+						bw_max(
-+							results->blackout_recovery_time,
-+							bw_div(
-+								(sub(
-+									add(
-+										mul(
-+											bw_div(
-+												mul(
-+													results->display_bandwidth[k],
-+													results->useful_bytes_per_request[k]),
-+												results->bytes_per_request[k]),
-+											vbios->blackout_duration),
-+										bw_div(
-+											mul(
-+												mul(
-+													mul(
-+														(add(
-+															add(
-+																mul(
-+																	vbios->mcifwrmc_urgent_latency,
-+																	int_to_fixed(
-+																		2)),
-+																results->dmif_burst_time[i][j]),
-+															results->mcifwr_burst_time[y_clk_level][sclk_level])),
-+														results->dispclk),
-+													results->bytes_per_pixel[k]),
-+												results->lines_interleaved_in_mem_access[k]),
-+											results->latency_hiding_lines[k])),
-+									results->adjusted_data_buffer_size[k])),
-+								(sub(
-+									bw_div(
-+										mul(
-+											mul(
-+												results->dispclk,
-+												results->bytes_per_pixel[k]),
-+											results->lines_interleaved_in_mem_access[k]),
-+										results->latency_hiding_lines[k]),
-+									bw_div(
-+										mul(
-+											results->display_bandwidth[k],
-+											results->useful_bytes_per_request[k]),
-+										results->bytes_per_request[k])))));
-+				}
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (surface_type[i] == def_display_write_back420_luma
-+				|| surface_type[i]
-+					== def_display_write_back420_chroma) {
-+				results->pixels_per_data_fifo_entry[i] =
-+					int_to_fixed(16);
-+			} else if (surface_type[i] == def_graphics) {
-+				results->pixels_per_data_fifo_entry[i] = bw_div(
-+					int_to_fixed(64),
-+					results->bytes_per_pixel[i]);
-+			} else if (results->orthogonal_rotation[i] == false) {
-+				results->pixels_per_data_fifo_entry[i] =
-+					int_to_fixed(16);
-+			} else {
-+				results->pixels_per_data_fifo_entry[i] = bw_div(
-+					int_to_fixed(16),
-+					results->bytes_per_pixel[i]);
-+			}
-+		}
-+	}
-+	results->min_pixels_per_data_fifo_entry = int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (gtn(results->min_pixels_per_data_fifo_entry,
-+				results->pixels_per_data_fifo_entry[i])) {
-+				results->min_pixels_per_data_fifo_entry =
-+					results->pixels_per_data_fifo_entry[i];
-+			}
-+		}
-+	}
-+	results->sclk_deep_sleep = bw_max(
-+		bw_div(mul(results->dispclk, frc_to_fixed(115, 100)),
-+			results->min_pixels_per_data_fifo_entry),
-+		results->total_read_request_bandwidth);
-+	results->chunk_request_time = int_to_fixed(0);
-+	results->cursor_request_time = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->chunk_request_time =
-+				add(results->chunk_request_time,
-+					bw_div(
-+						bw_div(
-+							mul(pixels_per_chunk,
-+								results->bytes_per_pixel[i]),
-+							results->useful_bytes_per_request[i]),
-+						bw_min(sclk[sclk_level],
-+							bw_div(results->dispclk,
-+								int_to_fixed(
-+									2)))));
-+		}
-+	}
-+	results->cursor_request_time = (bw_div(results->cursor_total_data,
-+		(mul(sclk[sclk_level], int_to_fixed(32)))));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->line_source_pixels_transfer_time =
-+				bw_max(
-+					bw_div(
-+						bw_div(
-+							results->src_pixels_for_first_output_pixel[i],
-+							dceip->lb_write_pixels_per_dispclk),
-+						(bw_div(results->dispclk,
-+							dceip->display_pipe_throughput_factor))),
-+					sub(
-+						bw_div(
-+							bw_div(
-+								results->src_pixels_for_last_output_pixel[i],
-+								dceip->lb_write_pixels_per_dispclk),
-+							(bw_div(results->dispclk,
-+								dceip->display_pipe_throughput_factor))),
-+						results->active_time[i]));
-+			if (surface_type[i] != def_display_write_back420_luma
-+				&& surface_type[i]
-+					!= def_display_write_back420_chroma) {
-+				results->urgent_watermark[i] =
-+					add(
-+						add(
-+							add(
-+								add(
-+									add(
-+										results->total_dmifmc_urgent_latency,
-+										results->dmif_burst_time[y_clk_level][sclk_level]),
-+									bw_max(
-+										results->line_source_pixels_transfer_time,
-+										results->line_source_transfer_time[i][y_clk_level][sclk_level])),
-+								vbios->blackout_duration),
-+							results->chunk_request_time),
-+						results->cursor_request_time);
-+				results->stutter_exit_watermark[i] =
-+					add(
-+						sub(
-+							vbios->stutter_self_refresh_exit_latency,
-+							results->total_dmifmc_urgent_latency),
-+						results->urgent_watermark[i]);
-+				results->nbp_state_change_watermark[i] =
-+					sub(
-+						add(
-+							sub(
-+								vbios->nbp_state_change_latency,
-+								results->total_dmifmc_urgent_latency),
-+							results->urgent_watermark[i]),
-+						vbios->blackout_duration);
-+			} else {
-+				results->urgent_watermark[i] =
-+					add(
-+						add(
-+							add(
-+								add(
-+									add(
-+										vbios->mcifwrmc_urgent_latency,
-+										results->mcifwr_burst_time[y_clk_level][sclk_level]),
-+									bw_max(
-+										results->line_source_pixels_transfer_time,
-+										results->line_source_transfer_time[i][y_clk_level][sclk_level])),
-+								vbios->blackout_duration),
-+							results->chunk_request_time),
-+						results->cursor_request_time);
-+				results->stutter_exit_watermark[i] =
-+					int_to_fixed(0);
-+				results->nbp_state_change_watermark[i] =
-+					add(
-+						sub(
-+							add(
-+								vbios->nbp_state_change_latency,
-+								results->dmif_burst_time[y_clk_level][sclk_level]),
-+							vbios->mcifwrmc_urgent_latency),
-+						results->urgent_watermark[i]);
-+			}
-+		}
-+	}
-+	results->stutter_mode_enable = results->cpuc_state_change_enable;
-+	if (mode_data->number_of_displays > 1) {
-+		for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+			if (results->enable[i]) {
-+				if (gtn(results->stutter_exit_watermark[i],
-+					results->cursor_latency_hiding[i])) {
-+					results->stutter_mode_enable = false;
-+				}
-+			}
-+		}
-+	}
-+	results->dmifdram_access_efficiency =
-+		bw_min(
-+			bw_div(
-+				bw_div(
-+					results->total_display_reads_required_dram_access_data,
-+					results->dram_bandwidth),
-+				results->dmif_total_page_close_open_time),
-+			int_to_fixed(1));
-+	if (gtn(results->total_display_writes_required_dram_access_data,
-+		int_to_fixed(0))) {
-+		results->mcifwrdram_access_efficiency =
-+			bw_min(
-+				bw_div(
-+					bw_div(
-+						results->total_display_writes_required_dram_access_data,
-+						results->dram_bandwidth),
-+					results->mcifwr_total_page_close_open_time),
-+				int_to_fixed(1));
-+	} else {
-+		results->mcifwrdram_access_efficiency = int_to_fixed(0);
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->average_bandwidth_no_compression[i] =
-+				bw_div(
-+					mul(
-+						mul(
-+							bw_div(
-+								mul(
-+									results->source_width_rounded_up_to_chunks[i],
-+									results->bytes_per_pixel[i]),
-+								(bw_div(
-+									results->h_total[i],
-+									results->pixel_rate[i]))),
-+							results->vsr[i]),
-+						results->bytes_per_request[i]),
-+					results->useful_bytes_per_request[i]);
-+			results->average_bandwidth[i] = bw_div(
-+				results->average_bandwidth_no_compression[i],
-+				results->compression_rate[i]);
-+		}
-+	}
-+	results->total_average_bandwidth_no_compression = int_to_fixed(0);
-+	results->total_average_bandwidth = int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->total_average_bandwidth_no_compression = add(
-+				results->total_average_bandwidth_no_compression,
-+				results->average_bandwidth_no_compression[i]);
-+			results->total_average_bandwidth = add(
-+				results->total_average_bandwidth,
-+				results->average_bandwidth[i]);
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->stutter_cycle_duration[i] =
-+				sub(
-+					mul(
-+						bw_div(
-+							bw_div(
-+								mul(
-+									bw_div(
-+										bw_div(
-+											results->adjusted_data_buffer_size[i],
-+											results->bytes_per_pixel[i]),
-+										results->source_width_rounded_up_to_chunks[i]),
-+									results->h_total[i]),
-+								results->vsr[i]),
-+							results->pixel_rate[i]),
-+						results->compression_rate[i]),
-+					bw_max(int_to_fixed(0),
-+						sub(
-+							results->stutter_exit_watermark[i],
-+							bw_div(
-+								mul(
-+									(add(
-+										results->line_buffer_prefetch[i],
-+										int_to_fixed(
-+											2))),
-+									results->h_total[i]),
-+								results->pixel_rate[i]))));
-+		}
-+	}
-+	results->total_stutter_cycle_duration = int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			if (gtn(results->total_stutter_cycle_duration,
-+				results->stutter_cycle_duration[i])) {
-+				results->total_stutter_cycle_duration =
-+					results->stutter_cycle_duration[i];
-+			}
-+		}
-+	}
-+	results->stutter_burst_time = bw_div(
-+		mul(results->total_stutter_cycle_duration,
-+			results->total_average_bandwidth),
-+		bw_min(
-+			(mul(results->dram_bandwidth,
-+				results->dmifdram_access_efficiency)),
-+			mul(sclk[sclk_level], vbios->data_return_bus_width)));
-+	results->time_in_self_refresh = sub(
-+		sub(results->total_stutter_cycle_duration,
-+			vbios->stutter_self_refresh_exit_latency),
-+		results->stutter_burst_time);
-+	if (mode_data->d1_display_write_back_dwb_enable == true) {
-+		results->stutter_efficiency = int_to_fixed(0);
-+	} else if (ltn(results->time_in_self_refresh, int_to_fixed(0))) {
-+		results->stutter_efficiency = int_to_fixed(0);
-+	} else {
-+		results->stutter_efficiency = mul(
-+			bw_div(results->time_in_self_refresh,
-+				results->total_stutter_cycle_duration),
-+			int_to_fixed(100));
-+	}
-+	results->worst_number_of_trips_to_memory = int_to_fixed(1);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]
-+			&& results->scatter_gather_enable_for_pipe[i] == true) {
-+			results->number_of_trips_to_memory_for_getting_apte_row[i] =
-+				bw_ceil(
-+					bw_div(
-+						results->scatter_gather_pte_requests_in_row[i],
-+						results->scatter_gather_pte_request_limit[i]),
-+					int_to_fixed(1));
-+			if (ltn(results->worst_number_of_trips_to_memory,
-+				results->number_of_trips_to_memory_for_getting_apte_row[i])) {
-+				results->worst_number_of_trips_to_memory =
-+					results->number_of_trips_to_memory_for_getting_apte_row[i];
-+			}
-+		}
-+	}
-+	results->immediate_flip_time = mul(
-+		results->worst_number_of_trips_to_memory,
-+		results->total_dmifmc_urgent_latency);
-+	results->latency_for_non_dmif_clients = add(
-+		results->total_dmifmc_urgent_latency,
-+		results->dmif_burst_time[y_clk_level][sclk_level]);
-+	if (mode_data->d1_display_write_back_dwb_enable == true) {
-+		results->latency_for_non_mcifwr_clients = add(
-+			vbios->mcifwrmc_urgent_latency,
-+			dceip->mcifwr_all_surfaces_burst_time);
-+	} else {
-+		results->latency_for_non_mcifwr_clients = int_to_fixed(0);
-+	}
-+	results->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div(
-+		(sub(results->min_read_buffer_size_in_time,
-+			results->dmif_burst_time[high][high])),
-+		results->total_dmifmc_urgent_trips);
-+	results->nbp_state_dram_speed_change_margin = int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		if (results->enable[i]) {
-+			results->nbp_state_dram_speed_change_margin =
-+				bw_min(
-+					results->nbp_state_dram_speed_change_margin,
-+					sub(
-+						results->maximum_latency_hiding_with_cursor[i],
-+						results->nbp_state_change_watermark[i]));
-+		}
-+	}
-+	for (i = 1; i <= 5; i += 1) {
-+		results->display_reads_time_for_data_transfer_and_urgent_latency =
-+			sub(results->min_read_buffer_size_in_time,
-+				mul(results->total_dmifmc_urgent_trips,
-+					int_to_fixed(i)));
-+		if (pipe_check == def_ok
-+			&& (gtn(
-+				results->display_reads_time_for_data_transfer_and_urgent_latency,
-+				results->dmif_total_page_close_open_time))) {
-+			results->dmif_required_sclk_for_urgent_latency[i] =
-+				bw_div(
-+					bw_div(
-+						results->total_display_reads_required_data,
-+						results->display_reads_time_for_data_transfer_and_urgent_latency),
-+					vbios->data_return_bus_width);
-+		} else {
-+			results->dmif_required_sclk_for_urgent_latency[i] =
-+				int_to_fixed(0);
-+		}
-+	}
-+
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+void bw_calcs_init(struct bw_calcs_input_dceip *bw_dceip,
-+	struct bw_calcs_input_vbios *bw_vbios)
-+{
-+	struct bw_calcs_input_dceip dceip;
-+	struct bw_calcs_input_vbios vbios;
-+
-+	vbios.number_of_dram_channels = int_to_fixed(2);
-+	vbios.dram_channel_width_in_bits = int_to_fixed(64);
-+	vbios.number_of_dram_banks = int_to_fixed(8);
-+	vbios.high_yclk = int_to_fixed(1600);
-+	vbios.low_yclk = frc_to_fixed(66666, 100);
-+	vbios.low_sclk = int_to_fixed(200);
-+	vbios.mid_sclk = int_to_fixed(300);
-+	vbios.high_sclk = frc_to_fixed(62609, 100);
-+	vbios.low_voltage_max_dispclk = int_to_fixed(352);
-+	vbios.mid_voltage_max_dispclk = int_to_fixed(467);
-+	vbios.high_voltage_max_dispclk = int_to_fixed(643);
-+	vbios.data_return_bus_width = int_to_fixed(32);
-+	vbios.trc = int_to_fixed(50);
-+	vbios.dmifmc_urgent_latency = int_to_fixed(4);
-+	vbios.stutter_self_refresh_exit_latency = frc_to_fixed(153, 10);
-+	vbios.nbp_state_change_latency = frc_to_fixed(19649, 1000);
-+	vbios.mcifwrmc_urgent_latency = int_to_fixed(10);
-+	vbios.scatter_gather_enable = true;
-+	vbios.down_spread_percentage = frc_to_fixed(5, 10);
-+	vbios.cursor_width = int_to_fixed(32);
-+	vbios.average_compression_rate = int_to_fixed(4);
-+	vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel =
-+		int_to_fixed(256);
-+	vbios.blackout_duration = int_to_fixed(18); /* us */
-+	vbios.maximum_blackout_recovery_time = int_to_fixed(20);
-+	dceip.dmif_request_buffer_size = int_to_fixed(768);
-+	dceip.de_tiling_buffer = int_to_fixed(0);
-+	dceip.dcfclk_request_generation = int_to_fixed(0);
-+	dceip.lines_interleaved_into_lb = int_to_fixed(2);
-+	dceip.chunk_width = int_to_fixed(256);
-+	dceip.number_of_graphics_pipes = int_to_fixed(3);
-+	dceip.number_of_underlay_pipes = int_to_fixed(1);
-+	dceip.display_write_back_supported = false;
-+	dceip.argb_compression_support = false;
-+	dceip.underlay_vscaler_efficiency6_bit_per_component = frc_to_fixed(
-+		35556, 10000);
-+	dceip.underlay_vscaler_efficiency8_bit_per_component = frc_to_fixed(
-+		34286, 10000);
-+	dceip.underlay_vscaler_efficiency10_bit_per_component = frc_to_fixed(32,
-+		10);
-+	dceip.underlay_vscaler_efficiency12_bit_per_component = int_to_fixed(3);
-+	dceip.graphics_vscaler_efficiency6_bit_per_component = frc_to_fixed(35,
-+		10);
-+	dceip.graphics_vscaler_efficiency8_bit_per_component = frc_to_fixed(
-+		34286, 10000);
-+	dceip.graphics_vscaler_efficiency10_bit_per_component = frc_to_fixed(32,
-+		10);
-+	dceip.graphics_vscaler_efficiency12_bit_per_component = int_to_fixed(3);
-+	dceip.alpha_vscaler_efficiency = int_to_fixed(3);
-+	dceip.max_dmif_buffer_allocated = int_to_fixed(2);
-+	dceip.graphics_dmif_size = int_to_fixed(12288);
-+	dceip.underlay_luma_dmif_size = int_to_fixed(19456);
-+	dceip.underlay_chroma_dmif_size = int_to_fixed(23552);
-+	dceip.pre_downscaler_enabled = true;
-+	dceip.underlay_downscale_prefetch_enabled = true;
-+	dceip.lb_write_pixels_per_dispclk = int_to_fixed(1);
-+	dceip.lb_size_per_component444 = int_to_fixed(82176);
-+	dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
-+	dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+		int_to_fixed(0);
-+	dceip.underlay420_luma_lb_size_per_component = int_to_fixed(82176);
-+	dceip.underlay420_chroma_lb_size_per_component = int_to_fixed(164352);
-+	dceip.underlay422_lb_size_per_component = int_to_fixed(82176);
-+	dceip.cursor_chunk_width = int_to_fixed(64);
-+	dceip.cursor_dcp_buffer_lines = int_to_fixed(4);
-+	dceip.cursor_memory_interface_buffer_pixels = int_to_fixed(64);
-+	dceip.underlay_maximum_width_efficient_for_tiling = int_to_fixed(1920);
-+	dceip.underlay_maximum_height_efficient_for_tiling = int_to_fixed(1080);
-+	dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+		frc_to_fixed(3, 10);
-+	dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+		int_to_fixed(25);
-+	dceip.minimum_outstanding_pte_request_limit = int_to_fixed(2);
-+	dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+		int_to_fixed(128);
-+	dceip.limit_excessive_outstanding_dmif_requests = true;
-+	dceip.linear_mode_line_request_alternation_slice = int_to_fixed(64);
-+	dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+		int_to_fixed(32);
-+	dceip.display_write_back420_luma_mcifwr_buffer_size = int_to_fixed(
-+		12288);
-+	dceip.display_write_back420_chroma_mcifwr_buffer_size = int_to_fixed(
-+		8192);
-+	dceip.request_efficiency = frc_to_fixed(8, 10);
-+	dceip.dispclk_per_request = int_to_fixed(2);
-+	dceip.dispclk_ramping_factor = frc_to_fixed(11, 10);
-+	dceip.display_pipe_throughput_factor = frc_to_fixed(105, 100);
-+	dceip.scatter_gather_pte_request_rows_in_tiling_mode = int_to_fixed(2);
-+	dceip.mcifwr_all_surfaces_burst_time = int_to_fixed(0); /* todo: this is a bug*/
-+
-+	*bw_dceip = dceip;
-+	*bw_vbios = vbios;
-+}
-+
-+/**
-+ * Return:
-+ *	true -	Display(s) configuration supported.
-+ *		In this case 'calcs_output' contains data for HW programming
-+ *	false - Display(s) configuration not supported (not enough bandwidth).
-+ */
-+
-+bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
-+	const struct bw_calcs_input_vbios *vbios,
-+	const struct bw_calcs_input_mode_data *mode_data,
-+	struct bw_calcs_output *calcs_output)
-+{
-+	struct bw_results_internal *bw_results_internal = dc_service_alloc(
-+				ctx, sizeof(struct bw_results_internal));
-+	struct bw_calcs_input_mode_data_internal *bw_data_internal =
-+		dc_service_alloc(
-+			ctx, sizeof(struct bw_calcs_input_mode_data_internal));
-+	switch (mode_data->number_of_displays) {
-+	case (3):
-+		bw_data_internal->d2_htotal = int_to_fixed(
-+			mode_data->displays_data[2].h_total);
-+		bw_data_internal->d2_pixel_rate =
-+			mode_data->displays_data[2].pixel_rate;
-+		bw_data_internal->d2_graphics_src_width = int_to_fixed(
-+			mode_data->displays_data[2].graphics_src_width);
-+		bw_data_internal->d2_graphics_src_height = int_to_fixed(
-+			mode_data->displays_data[2].graphics_src_height);
-+		bw_data_internal->d2_graphics_scale_ratio =
-+			mode_data->displays_data[2].graphics_scale_ratio;
-+		bw_data_internal->d2_graphics_stereo_mode =
-+			mode_data->displays_data[2].graphics_stereo_mode;
-+	case (2):
-+		bw_data_internal->d1_display_write_back_dwb_enable = false;
-+		bw_data_internal->d1_underlay_mode = ul_none;
-+		bw_data_internal->d1_underlay_scale_ratio = int_to_fixed(0);
-+		bw_data_internal->d1_htotal = int_to_fixed(
-+			mode_data->displays_data[1].h_total);
-+		bw_data_internal->d1_pixel_rate =
-+			mode_data->displays_data[1].pixel_rate;
-+		bw_data_internal->d1_graphics_src_width = int_to_fixed(
-+			mode_data->displays_data[1].graphics_src_width);
-+		bw_data_internal->d1_graphics_src_height = int_to_fixed(
-+			mode_data->displays_data[1].graphics_src_height);
-+		bw_data_internal->d1_graphics_scale_ratio =
-+			mode_data->displays_data[1].graphics_scale_ratio;
-+		bw_data_internal->d1_graphics_stereo_mode =
-+			mode_data->displays_data[1].graphics_stereo_mode;
-+
-+	case (1):
-+		bw_data_internal->d0_fbc_enable =
-+			mode_data->displays_data[0].fbc_enable;
-+		bw_data_internal->d0_lpt_enable =
-+			mode_data->displays_data[0].lpt_enable;
-+		bw_data_internal->d0_underlay_mode =
-+			mode_data->displays_data[0].underlay_mode;
-+		bw_data_internal->d0_underlay_scale_ratio = int_to_fixed(0);
-+		bw_data_internal->d0_htotal = int_to_fixed(
-+			mode_data->displays_data[0].h_total);
-+		bw_data_internal->d0_pixel_rate =
-+			mode_data->displays_data[0].pixel_rate;
-+		bw_data_internal->d0_graphics_src_width = int_to_fixed(
-+			mode_data->displays_data[0].graphics_src_width);
-+		bw_data_internal->d0_graphics_src_height = int_to_fixed(
-+			mode_data->displays_data[0].graphics_src_height);
-+		bw_data_internal->d0_graphics_scale_ratio =
-+			mode_data->displays_data[0].graphics_scale_ratio;
-+		bw_data_internal->d0_graphics_stereo_mode =
-+			mode_data->displays_data[0].graphics_stereo_mode;
-+
-+	default:
-+		/* data for all displays */
-+		bw_data_internal->number_of_displays =
-+			mode_data->number_of_displays;
-+		bw_data_internal->graphics_rotation_angle = int_to_fixed(
-+			mode_data->displays_data[0].graphics_rotation_angle);
-+		bw_data_internal->underlay_rotation_angle = int_to_fixed(
-+			mode_data->displays_data[0].underlay_rotation_angle);
-+		bw_data_internal->underlay_surface_type =
-+			mode_data->displays_data[0].underlay_surface_type;
-+		bw_data_internal->panning_and_bezel_adjustment =
-+			mode_data->displays_data[0].panning_and_bezel_adjustment;
-+		bw_data_internal->graphics_tiling_mode =
-+			mode_data->displays_data[0].graphics_tiling_mode;
-+		bw_data_internal->graphics_interlace_mode =
-+			mode_data->displays_data[0].graphics_interlace_mode;
-+		bw_data_internal->graphics_bytes_per_pixel = int_to_fixed(
-+			mode_data->displays_data[0].graphics_bytes_per_pixel);
-+		bw_data_internal->graphics_htaps = int_to_fixed(
-+			mode_data->displays_data[0].graphics_h_taps);
-+		bw_data_internal->graphics_vtaps = int_to_fixed(
-+			mode_data->displays_data[0].graphics_v_taps);
-+		bw_data_internal->graphics_lb_bpc = int_to_fixed(
-+			mode_data->displays_data[0].graphics_lb_bpc);
-+		bw_data_internal->underlay_lb_bpc = int_to_fixed(
-+			mode_data->displays_data[0].underlay_lb_bpc);
-+		bw_data_internal->underlay_tiling_mode =
-+			mode_data->displays_data[0].underlay_tiling_mode;
-+		bw_data_internal->underlay_htaps = int_to_fixed(
-+			mode_data->displays_data[0].underlay_h_taps);
-+		bw_data_internal->underlay_vtaps = int_to_fixed(
-+			mode_data->displays_data[0].underlay_v_taps);
-+		bw_data_internal->underlay_src_width = int_to_fixed(
-+			mode_data->displays_data[0].underlay_src_width);
-+		bw_data_internal->underlay_src_height = int_to_fixed(
-+			mode_data->displays_data[0].underlay_src_height);
-+		bw_data_internal->underlay_pitch_in_pixels = int_to_fixed(
-+			mode_data->displays_data[0].underlay_pitch_in_pixels);
-+		bw_data_internal->underlay_stereo_mode =
-+			mode_data->displays_data[0].underlay_stereo_mode;
-+		bw_data_internal->display_synchronization_enabled =
-+			mode_data->display_synchronization_enabled;
-+	}
-+
-+	if (bw_data_internal->number_of_displays != 0) {
-+		struct bw_fixed high_sclk = vbios->high_sclk;
-+		struct bw_fixed low_sclk = vbios->low_sclk;
-+		struct bw_fixed high_yclk = vbios->high_yclk;
-+		struct bw_fixed low_yclk = vbios->low_yclk;
-+
-+		((struct bw_calcs_input_vbios *)vbios)->low_yclk = low_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_yclk = low_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_sclk = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_sclk = low_sclk;
-+		calculate_bandwidth(dceip, vbios, bw_data_internal,
-+							bw_results_internal);
-+
-+		/* units: nanosecond, 16bit storage. */
-+		calcs_output->nbp_state_change_watermark[0].b_mark =
-+			mul(bw_results_internal->nbp_state_change_watermark[4],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->nbp_state_change_watermark[1].b_mark =
-+			mul(bw_results_internal->nbp_state_change_watermark[5],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->nbp_state_change_watermark[2].b_mark =
-+			mul(bw_results_internal->nbp_state_change_watermark[6],
-+					int_to_fixed(1000)).value >> 24;
-+
-+		calcs_output->stutter_exit_watermark[0].b_mark =
-+			mul(bw_results_internal->stutter_exit_watermark[4],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->stutter_exit_watermark[1].b_mark =
-+			mul(bw_results_internal->stutter_exit_watermark[5],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->stutter_exit_watermark[2].b_mark =
-+			mul(bw_results_internal->stutter_exit_watermark[6],
-+					int_to_fixed(1000)).value >> 24;
-+
-+		calcs_output->urgent_watermark[0].b_mark =
-+			mul(bw_results_internal->urgent_watermark[4],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->urgent_watermark[1].b_mark =
-+			mul(bw_results_internal->urgent_watermark[5],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->urgent_watermark[2].b_mark =
-+			mul(bw_results_internal->urgent_watermark[6],
-+					int_to_fixed(1000)).value >> 24;
-+
-+		((struct bw_calcs_input_vbios *)vbios)->low_yclk = high_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_yclk = high_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_sclk = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_sclk = high_sclk;
-+
-+		calculate_bandwidth(dceip, vbios, bw_data_internal,
-+							bw_results_internal);
-+
-+		calcs_output->nbp_state_change_watermark[0].a_mark =
-+			mul(bw_results_internal->nbp_state_change_watermark[4],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->nbp_state_change_watermark[1].a_mark =
-+			mul(bw_results_internal->nbp_state_change_watermark[5],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->nbp_state_change_watermark[2].a_mark =
-+			mul(bw_results_internal->nbp_state_change_watermark[6],
-+					int_to_fixed(1000)).value >> 24;
-+
-+		calcs_output->stutter_exit_watermark[0].a_mark =
-+			mul(bw_results_internal->stutter_exit_watermark[4],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->stutter_exit_watermark[1].a_mark =
-+			mul(bw_results_internal->stutter_exit_watermark[5],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->stutter_exit_watermark[2].a_mark =
-+			mul(bw_results_internal->stutter_exit_watermark[6],
-+					int_to_fixed(1000)).value >> 24;
-+
-+		calcs_output->urgent_watermark[0].a_mark =
-+			mul(bw_results_internal->urgent_watermark[4],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->urgent_watermark[1].a_mark =
-+			mul(bw_results_internal->urgent_watermark[5],
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->urgent_watermark[2].a_mark =
-+			mul(bw_results_internal->urgent_watermark[6],
-+					int_to_fixed(1000)).value >> 24;
-+
-+		calcs_output->nbp_state_change_enable =
-+			bw_results_internal->nbp_state_change_enable;
-+		calcs_output->cpuc_state_change_enable =
-+				bw_results_internal->cpuc_state_change_enable;
-+		calcs_output->cpup_state_change_enable =
-+				bw_results_internal->cpup_state_change_enable;
-+		calcs_output->stutter_mode_enable =
-+				bw_results_internal->stutter_mode_enable;
-+		calcs_output->dispclk =
-+				mul(bw_results_internal->dispclk,
-+					int_to_fixed(1000)).value >> 24;
-+		calcs_output->required_sclk =
-+			mul(bw_results_internal->required_sclk,
-+					int_to_fixed(1000)).value >> 24;
-+
-+		((struct bw_calcs_input_vbios *)vbios)->low_yclk = low_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_yclk = high_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_sclk = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_sclk = high_sclk;
-+	} else {
-+		calcs_output->nbp_state_change_enable = true;
-+		calcs_output->cpuc_state_change_enable = true;
-+		calcs_output->cpup_state_change_enable = true;
-+		calcs_output->stutter_mode_enable = true;
-+		calcs_output->dispclk = 0;
-+		calcs_output->required_sclk = 0;
-+	}
-+
-+	dc_service_free(ctx, bw_data_internal);
-+	dc_service_free(ctx, bw_results_internal);
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-new file mode 100644
-index 0000000..6bad7c6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -0,0 +1,278 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+#include "bw_fixed.h"
-+
-+
-+#define BITS_PER_FRACTIONAL_PART 24
-+
-+#define MIN_I32 \
-+	(long long)(-(1LL << (63 - BITS_PER_FRACTIONAL_PART)))
-+
-+#define MAX_I32 \
-+	(long long)((1ULL << (63 - BITS_PER_FRACTIONAL_PART)) - 1)
-+
-+#define MIN_I64 \
-+	(long long)(-(1LL << 63))
-+
-+#define MAX_I64 \
-+	(long long)((1ULL << 63) - 1)
-+
-+
-+#define FRACTIONAL_PART_MASK \
-+	((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
-+
-+#define GET_INTEGER_PART(x) \
-+	((x) >> BITS_PER_FRACTIONAL_PART)
-+
-+#define GET_FRACTIONAL_PART(x) \
-+	(FRACTIONAL_PART_MASK & (x))
-+
-+static unsigned long long abs_i64(long long arg)
-+{
-+	if (arg >= 0)
-+		return (unsigned long long)(arg);
-+	else
-+		return (unsigned long long)(-arg);
-+}
-+
-+struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3)
-+{
-+	return bw_min(bw_min(v1, v2), v3);
-+}
-+
-+struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3)
-+{
-+	return bw_max(bw_max(v1, v2), v3);
-+}
-+
-+struct bw_fixed int_to_fixed(long long value)
-+{
-+	struct bw_fixed res;
-+	ASSERT(value < MAX_I32 && value > MIN_I32);
-+	res.value = value << BITS_PER_FRACTIONAL_PART;
-+	return res;
-+}
-+
-+struct bw_fixed frc_to_fixed(long long numerator, long long denominator)
-+{
-+	struct bw_fixed res;
-+	bool arg1_negative = numerator < 0;
-+	bool arg2_negative = denominator < 0;
-+	unsigned long long arg1_value;
-+	unsigned long long arg2_value;
-+	unsigned long long remainder;
-+
-+	/* determine integer part */
-+	unsigned long long res_value;
-+
-+	ASSERT(denominator != 0);
-+
-+	arg1_value = abs_i64(numerator);
-+	arg2_value = abs_i64(denominator);
-+	remainder = arg1_value % arg2_value;
-+	res_value = arg1_value / arg2_value;
-+
-+	ASSERT(res_value <= MAX_I32);
-+
-+	/* determine fractional part */
-+	{
-+		unsigned int i = BITS_PER_FRACTIONAL_PART;
-+
-+		do
-+		{
-+			remainder <<= 1;
-+
-+			res_value <<= 1;
-+
-+			if (remainder >= arg2_value)
-+			{
-+				res_value |= 1;
-+				remainder -= arg2_value;
-+			}
-+		} while (--i != 0);
-+	}
-+
-+	/* round up LSB */
-+	{
-+		unsigned long long summand = (remainder << 1) >= arg2_value;
-+
-+		ASSERT(res_value <= MAX_I64 - summand);
-+
-+		res_value += summand;
-+	}
-+
-+	res.value = (signed long long)(res_value);
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+	return res;
-+}
-+
-+struct bw_fixed bw_min(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return (arg1.value <= arg2.value) ? arg1 : arg2;
-+}
-+
-+struct bw_fixed bw_max(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return (arg2.value <= arg1.value) ? arg1 : arg2;
-+}
-+
-+struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed significance)
-+{
-+	struct bw_fixed result;
-+	signed long long multiplicand = arg.value / abs_i64(significance.value);
-+	result.value = abs_i64(significance.value) * multiplicand;
-+	ASSERT(abs_i64(result.value) <= abs_i64(arg.value));
-+	return result;
-+}
-+
-+struct bw_fixed bw_ceil(const struct bw_fixed arg, const struct bw_fixed significance)
-+{
-+	struct bw_fixed result;
-+	result.value = arg.value + arg.value % abs_i64(significance.value);
-+	if (result.value < significance.value)
-+		result.value = significance.value;
-+	return result;
-+}
-+
-+struct bw_fixed add(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+
-+	res.value = arg1.value + arg2.value;
-+
-+	return res;
-+}
-+
-+struct bw_fixed sub(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+
-+	res.value = arg1.value - arg2.value;
-+
-+	return res;
-+}
-+
-+struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+
-+	bool arg1_negative = arg1.value < 0;
-+	bool arg2_negative = arg2.value < 0;
-+
-+	unsigned long long arg1_value = abs_i64(arg1.value);
-+	unsigned long long arg2_value = abs_i64(arg2.value);
-+
-+	unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);
-+	unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);
-+
-+	unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);
-+	unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);
-+
-+	unsigned long long tmp;
-+
-+	res.value = arg1_int * arg2_int;
-+
-+	ASSERT(res.value <= MAX_I32);
-+
-+	res.value <<= BITS_PER_FRACTIONAL_PART;
-+
-+	tmp = arg1_int * arg2_fra;
-+
-+	ASSERT(tmp <= (unsigned long long)(MAX_I64 - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg2_int * arg1_fra;
-+
-+	ASSERT(tmp <= (unsigned long long)(MAX_I64 - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg1_fra * arg2_fra;
-+
-+	tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
-+		(tmp >= (unsigned long long)(frc_to_fixed(1, 2).value));
-+
-+	ASSERT(tmp <= (unsigned long long)(MAX_I64 - res.value));
-+
-+	res.value += tmp;
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+	return res;
-+}
-+
-+struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res = frc_to_fixed(arg1.value, arg2.value);
-+	return res;
-+}
-+
-+struct bw_fixed fixed31_32_to_bw_fixed(long long raw)
-+{
-+	struct bw_fixed result = { 0 };
-+
-+	if (raw < 0) {
-+		raw = -raw;
-+		result.value = -(raw >> (32 - BITS_PER_FRACTIONAL_PART));
-+	} else {
-+		result.value = raw >> (32 - BITS_PER_FRACTIONAL_PART);
-+	}
-+
-+	return result;
-+}
-+
-+bool equ(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value == arg2.value;
-+}
-+
-+bool neq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value != arg2.value;
-+}
-+
-+bool leq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value <= arg2.value;
-+}
-+
-+bool geq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value >= arg2.value;
-+}
-+
-+bool ltn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value < arg2.value;
-+}
-+
-+bool gtn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value > arg2.value;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-new file mode 100644
-index 0000000..f8ee65e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-@@ -0,0 +1,1992 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/fixed31_32.h"
-+
-+#include "scaler_filter.h"
-+
-+enum {
-+	DOWN_DB_SCALES = 8,
-+	DOWN_DB_POINTS = 11,
-+
-+	UP_DB_SCALES = 1,
-+	UP_DB_POINTS = 7,
-+
-+	MIN_SHARPNESS = -50,
-+	MAX_SHARPNESS = 50,
-+
-+	CONST_DIVIDER = 10000000,
-+
-+	MAX_HOR_DOWNSCALE = 1666000, /* 1:6  */
-+	MAX_VER_DOWNSCALE = 1666000, /* 1:6  */
-+
-+	MAX_HOR_UPSCALE = 160000000, /* 16:1 */
-+	MAX_VER_UPSCALE = 160000000, /* 16:1 */
-+
-+	THRESHOLDRATIOLOW = 8000000, /* 0.8 */
-+	THRESHOLDRATIOUP = 10000000, /* 1.0 */
-+
-+	DOWN_DB_FUZZY = -120411996, /* -12.041200 */
-+	DOWN_DB_FLAT = -60205998, /* -6.020600 */
-+	DOWN_DB_SHARP = -10000000, /* -1.000000 */
-+
-+	UP_DB_FUZZY = -60205998, /* -6.020600 */
-+	UP_DB_FLAT = 0,
-+	UP_DB_SHARP = 60205998 /* 6.020600 */
-+};
-+
-+static inline struct fixed31_32 max_hor_downscale(void)
-+{
-+	return dal_fixed31_32_from_fraction(MAX_HOR_DOWNSCALE, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 max_ver_downscale(void)
-+{
-+	return dal_fixed31_32_from_fraction(MAX_VER_DOWNSCALE, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 max_hor_upscale(void)
-+{
-+	return dal_fixed31_32_from_fraction(MAX_HOR_UPSCALE, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 max_ver_upscale(void)
-+{
-+	return dal_fixed31_32_from_fraction(MAX_VER_UPSCALE, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 threshold_ratio_low(void)
-+{
-+	return dal_fixed31_32_from_fraction(THRESHOLDRATIOLOW, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 threshold_ratio_up(void)
-+{
-+	return dal_fixed31_32_from_fraction(THRESHOLDRATIOUP, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 down_db_fuzzy(void)
-+{
-+	return dal_fixed31_32_from_fraction(DOWN_DB_FUZZY, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 down_db_flat(void)
-+{
-+	return dal_fixed31_32_from_fraction(DOWN_DB_FLAT, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 down_db_sharp(void)
-+{
-+	return dal_fixed31_32_from_fraction(DOWN_DB_SHARP, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 up_db_fuzzy(void)
-+{
-+	return dal_fixed31_32_from_fraction(UP_DB_FUZZY, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 up_db_flat(void)
-+{
-+	return dal_fixed31_32_from_fraction(UP_DB_FLAT, CONST_DIVIDER);
-+}
-+
-+static inline struct fixed31_32 up_db_sharp(void)
-+{
-+	return dal_fixed31_32_from_fraction(UP_DB_SHARP, CONST_DIVIDER);
-+}
-+
-+static const int32_t
-+	downscaling_db_table[][DOWN_DB_SCALES + 1][DOWN_DB_POINTS] = {
-+	/* 3 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			14302719,	14302719,	14302719,
-+			10000000,	99999,		99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14302339,	14302339,	14302339,
-+			10000000,	4452010,	99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14302760,	14302760,	14302760,
-+			10000000,	7826979,	5258399,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14302819,	14302819,	14302819,
-+			10000000,	8669400,	7414469,
-+			4422729,	99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14302730,	14302730,	12791190,
-+			10000000,	9045640,	8180170,
-+			6477950,	4599249,	2019010,
-+			99999,		99999
-+		},
-+		{
-+			14302699,	14302699,	12067849,
-+			10000000,	9236029,	8541280,
-+			7252740,	6021010,	4820120,
-+			3511950,	1769340
-+		},
-+		{
-+			14302710,	14302710,	11783510,
-+			10000000,	9325690,	8704419,
-+			7595670,	6583020,	5652850,
-+			4749999,	3847680
-+		},
-+		{
-+			14302920,	14302920,	11709250,
-+			10000000,	9345560,	8754609,
-+			7692559,	6738259,	5878239,
-+			5057529,	4264070
-+		}
-+	},
-+	/* 4 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			14308999,	14308999,	14308999,
-+			10000000,	99999,		99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14308999,	14308999,	14308999,
-+			10000000,	6311039,	99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14308999,	14308999,	14308999,
-+			10000000,	8526669,	6832849,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			14308999,	14308999,	12110630,
-+			10000000,	9117940,	8230940,
-+			6320130,	3719770,	99999,
-+			99999,		99999
-+		},
-+		{
-+			14308999,	14308999,	11474980,
-+			10000000,	9370139,	8771979,
-+			7601270,	6440780,	5249999,
-+			3887520,	2039040
-+		},
-+		{
-+			14308999,	13084859,	11179579,
-+			10000000,	9495180,	9016919,
-+			8134520,	7311699,	6560329,
-+			5845720,	5155519
-+		},
-+		{
-+			14308999,	12576600,	11048669,
-+			10000000,	9550499,	9132360,
-+			8368729,	7679399,	7073119,
-+			6520900,	6015530
-+		},
-+		{
-+			14308999,	12448530,	11007410,
-+			10000000,	9566799,	9165279,
-+			8435800,	7785279,	7215780,
-+			6701470,	6240640
-+		}
-+	},
-+	/* 5 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			8971139,	8971139,	8971139,
-+			10000000,	99999,		99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			9466379,	9466379,	9466379,
-+			10000000,	5648760,	3834280,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			15000000,	15000000,	14550110,
-+			10000000,	7121120,	5994579,
-+			4314630,	2606149,	99999,
-+			99999,		99999
-+		},
-+		{
-+			15000000,	15000000,	13047469,
-+			10000000,	8368809,	7343569,
-+			5970299,	4924620,	4029389,
-+			3171139,	2276369
-+		},
-+		{
-+			15000000,	14157199,	11897679,
-+			10000000,	9166659,	8444600,
-+			7287240,	6374719,	5615460,
-+			4949580,	4350199
-+		},
-+		{
-+			15000000,	12877819,	11224579,
-+			10000000,	9488620,	9016109,
-+			8203780,	7500000,	6883730,
-+			6326839,	5818459
-+		},
-+		{
-+			14733040,	12233200,	10939040,
-+			10000000,	9608929,	9250000,
-+			8623390,	8076940,	7606369,
-+			7177749,	6785169
-+		},
-+		{
-+			14627330,	12046170,	10862360,
-+			10000000,	9639260,	9312710,
-+			8737679,	8242470,	7815709,
-+			7432209,	7082970
-+		}
-+	},
-+	/* 6 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			8231559,	8231559,	8231559,
-+			10000000,	99999,		99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			8353310,	8353310,	8353310,
-+			10000000,	5504879,	4310710,
-+			870359,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			8643479,	8643479,	8643479,
-+			10000000,	6483510,	5768150,
-+			4630779,	3580690,	2501940,
-+			1015309,	99999
-+		},
-+		{
-+			15000000,	15000000,	13493930,
-+			10000000,	7516040,	6802409,
-+			5824409,	5080109,	4454280,
-+			3896749,	3386510
-+		},
-+		{
-+			15000000,	14055930,	12321079,
-+			10000000,	8872389,	8090410,
-+			7035570,	6281229,	5676810,
-+			5165010,	4717260
-+		},
-+		{
-+			15000000,	12915290,	11311399,
-+			10000000,	9460610,	8988440,
-+			8202149,	7548679,	6999999,
-+			6510639,	6065719
-+		},
-+		{
-+			14310129,	12140829,	10901659,
-+			10000000,	9635019,	9307180,
-+			8740929,	8263260,	7858849,
-+			7499330,	7170130
-+		},
-+		{
-+			13815449,	11911309,	10801299,
-+			10000000,	9669629,	9380580,
-+			8878319,	8452050,	8097199,
-+			7785030,	7504299
-+		}
-+	},
-+	/* 7 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			10616660,	10616660,	10616660,
-+			10000000,	2646020,	99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			10099999,	10099999,	10099999,
-+			10000000,	4936839,	4112670,
-+			2729740,	896539,		99999,
-+			99999,		99999
-+		},
-+		{
-+			8345860,	8345860,	8345860,
-+			10000000,	6034079,	5371739,
-+			4466759,	3763799,	3155870,
-+			2588019,	2026730
-+		},
-+		{
-+			9298499,	9298499,	13768420,
-+			10000000,	7174239,	6524270,
-+			5670250,	5052099,	4549089,
-+			4115279,	3722150
-+		},
-+		{
-+			15000000,	14116940,	12563209,
-+			10000000,	8542140,	7782419,
-+			6865050,	6239479,	5758860,
-+			5351870,	4992800
-+		},
-+		{
-+			15000000,	12913750,	11306079,
-+			10000000,	9452580,	8969209,
-+			8168810,	7538409,	7029479,
-+			6603180,	6227809
-+		},
-+		{
-+			14390859,	11862809,	10757420,
-+			10000000,	9688709,	9404249,
-+			8904439,	8472480,	8099079,
-+			7765330,	7459110
-+		},
-+		{
-+			13752900,	11554559,	10637769,
-+			10000000,	9736120,	9499999,
-+			9079759,	8718389,	8408790,
-+			8134469,	7886120
-+		}
-+	},
-+	/* 8 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			11277090,	11277090,	11277090,
-+			10000000,	2949059,	99999,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			11196039,	11196039,	11196039,
-+			10000000,	4627540,	4018869,
-+			3018769,	2000000,	250770,
-+			99999,		99999
-+		},
-+		{
-+			10878369,	10878369,	10878369,
-+			10000000,	5657230,	5118110,
-+			4372630,	3809120,	3337709,
-+			2919510,	2535369
-+		},
-+		{
-+			9090089,	9090089,	13961290,
-+			10000000,	6929969,	6334999,
-+			5569829,	5019649,	4584150,
-+			4208610,	3876540
-+		},
-+		{
-+			15000000,	14173229,	12732659,
-+			10000000,	8267070,	7575380,
-+			6764540,	6218209,	5803539,
-+			5454990,	5146239
-+		},
-+		{
-+			15000000,	12928279,	11292259,
-+			10000000,	9447429,	8954229,
-+			8141599,	7516989,	7039459,
-+			6649519,	6316819
-+		},
-+		{
-+			14661350,	11638879,	10665880,
-+			10000000,	9722669,	9464690,
-+			9013469,	8613470,	8266339,
-+			7949870,	7663450
-+		},
-+		{
-+			13861900,	11311980,	10543940,
-+			10000000,	9772019,	9565100,
-+			9198870,	8881340,	8609200,
-+			8365769,	8147500
-+		}
-+	},
-+	/* 9 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{	10099999,	10099999,	10099999,
-+			10000000,	2939159,	1526470,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			11726609,	11726609,	11726609,
-+			10000000,	4329420,	3805609,
-+			3030480,	2363760,	1732099,
-+			980139,		99999
-+		},
-+		{
-+			10949269,	10949269,	10949269,
-+			10000000,	5452589,	4946640,
-+			4277969,	3790729,	3392640,
-+			3048950,	2750000
-+		},
-+		{
-+			8830279,	8830279,	14084529,
-+			10000000,	6743149,	6182519,
-+			5482980,	5000000,	4622060,
-+			4303340,	4022600
-+		},
-+		{
-+			9709150,	14111399,	12800760,
-+			10000000,	7989749,	7445629,
-+			6741260,	6241980,	5857459,
-+			5534989,	5255370
-+		},
-+		{
-+			15000000,	12830289,	11489900,
-+			10000000,	9302089,	8767340,
-+			8025540,	7500000,	7100800,
-+			6768149,	6481850
-+		},
-+		{
-+			14873609,	11576000,	10650579,
-+			10000000,	9731360,	9483649,
-+			9054650,	8680559,	8358049,
-+			8066400,	7802420
-+		},
-+		{
-+			12981410,	11185950,	10491620,
-+			10000000,	9795730,	9611030,
-+			9286710,	9007279,	8768100,
-+			8553469,	8361340
-+		}
-+	},
-+	/* 10 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			8993279,	8993279,	8993279,
-+			10000000,	2921360,	1905619,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			9064850,	9064850,	9064850,
-+			10000000,	4095619,	3655839,
-+			3021000,	2500000,	2031680,
-+			1566990,	1055440
-+		},
-+		{
-+			11043460,	11043460,	11043460,
-+			10000000,	5287479,	4816150,
-+			4208439,	3769229,	3418970,
-+			3117449,	2850320
-+		},
-+		{
-+			8651900,	8651900,	14169909,
-+			10000000,	6596950,	6071490,
-+			5423219,	4980779,	4644620,
-+			4362219,	4114899
-+		},
-+		{
-+			9246050,	14055370,	12832759,
-+			10000000,	7831320,	7369570,
-+			6731680,	6262450,	5897690,
-+			5592269,	5328789
-+		},
-+		{
-+			15000000,	12770450,	11642129,
-+			10000000,	9120929,	8601920,
-+			7946630,	7490440,	7140589,
-+			6847490,	6593719
-+		},
-+		{
-+			14062479,	11541219,	10644329,
-+			10000000,	9736120,	9495139,
-+			9080520,	8724340,	8419489,
-+			8146359,	7899820
-+		},
-+		{
-+			12507469,	11102950,	10457479,
-+			10000000,	9811149,	9641249,
-+			9344969,	9090980,	8875219,
-+			8684499,	8513180
-+		}
-+	},
-+	/* 11 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			10099509,	10099509,	10099509,
-+			10000000,	2788810,	2054850,
-+			99999,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			8872069,	8872069,	8872069,
-+			10000000,	3929649,	3522840,
-+			2963230,	2527720,	2157579,
-+			1823610,	1500000
-+		},
-+		{
-+			10099999,	10099999,	10099999,
-+			10000000,	5155599,	4712319,
-+			4154500,	3759450,	3448629,
-+			3183139,	2948490
-+		},
-+		{
-+			10511649,	10511649,	14216580,
-+			10000000,	6445930,	5988820,
-+			5401239,	4988409,	4673399,
-+			4410479,	4181599
-+		},
-+		{
-+			9170889,	14003310,	12949769,
-+			10000000,	7684900,	7250000,
-+			6670129,	6255810,	5934680,
-+			5664110,	5427970
-+		},
-+		{
-+			15000000,	12763030,	11734730,
-+			10000000,	8958870,	8478559,
-+			7893459,	7489529,	7179200,
-+			6917790,	6688359
-+		},
-+		{
-+			14634610,	11491880,	10619130,
-+			10000000,	9744859,	9509819,
-+			9102900,	8760340,	8463050,
-+			8202620,	7968729
-+		},
-+		{
-+			12415319,	10980290,	10405089,
-+			10000000,	9831910,	9680110,
-+			9413710,	9184579,	8987190,
-+			8813819,	8655819
-+		}
-+	},
-+	/* 12 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			10832400,	10832400,	10832400,
-+			10000000,	2700819,	2115820,
-+			750000,		99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			10747549,	10747549,	10747549,
-+			10000000,	3781630,	3415020,
-+			2914879,	2537429,	2221180,
-+			1943199,	1688420
-+		},
-+		{
-+			11630790,	11630790,	11630790,
-+			10000000,	5047429,	4631519,
-+			4113860,	3750000,	3469760,
-+			3229379,	3016360
-+		},
-+		{
-+			10780229,	10780229,	10780229,
-+			10000000,	6340010,	5935009,
-+			5387600,	4995940,	4695929,
-+			4446829,	4231610
-+		},
-+		{
-+			9055669,	13968739,	13037070,
-+			10000000,	7556660,	7149490,
-+			6625509,	6250000,	5958870,
-+			5713790,	5500869
-+		},
-+		{
-+			14614900,	12760740,	11806739,
-+			10000000,	8824530,	8388419,
-+			7857400,	7489010,	7206150,
-+			6968010,	6759889
-+		},
-+		{
-+			14894100,	11451840,	10598870,
-+			10000000,	9750000,	9521099,
-+			9122239,	8784019,	8494700,
-+			8243309,	8018680
-+		},
-+		{
-+			12298769,	10886880,	10367530,
-+			10000000,	9846829,	9708030,
-+			9464049,	9252949,	9072539,
-+			8910980,	8766649
-+		}
-+	},
-+	/* 13 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			10099999,	10099999,	10099999,
-+			10000000,	2574490,	2099110,
-+			1194889,	99999,		99999,
-+			99999,		99999
-+		},
-+		{
-+			10099999,	10099999,	10099999,
-+			10000000,	3679780,	3332070,
-+			2869139,	2530030,	2251899,
-+			2010450,	1793050
-+		},
-+		{
-+			9306690,	9306690,	9306690,
-+			10000000,	4964010,	4573009,
-+			4082309,	3742089,	3481810,
-+			3262990,	3070969
-+		},
-+		{
-+			10099999,	10099999,	10099999,
-+			10000000,	6217889,	5843269,
-+			5353810,	5000000,	4730190,
-+			4499999,	4301390
-+		},
-+		{
-+			8819990,	13964320,	13098440,
-+			10000000,	7454770,	7075160,
-+			6591439,	6250000,	5983970,
-+			5760229,	5564339
-+		},
-+		{
-+			14432849,	12727780,	11847709,
-+			10000000,	8695709,	8322049,
-+			7842620,	7500000,	7234820,
-+			7010849,	6814730
-+		},
-+		{
-+			15000000,	11440130,	10620100,
-+			10000000,	9742270,	9508739,
-+			9110010,	8782560,	8510140,
-+			8276290,	8069980
-+		},
-+		{
-+			12039999,	10825289,	10341939,
-+			10000000,	9858080,	9729740,
-+			9505100,	9310669,	9144560,
-+			8996559,	8862569
-+		}
-+	},
-+	/* 14 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			9289590,	9289590,	9289590,
-+			10000000,	2485270,	2084970,
-+			1362659,	250000,		99999,
-+			99999,		99999
-+		},
-+		{
-+			9484500,	9484500,	9484500,
-+			10000000,	3593840,	3263100,
-+			2833609,	2519409,	2267650,
-+			2050379,	1856749
-+		},
-+		{
-+			9237130,	9237130,	9237130,
-+			10000000,	4898909,	4527629,
-+			4057880,	3734529,	3490320,
-+			3287230,	3111050
-+		},
-+		{
-+			9543399,	9543399,	9543399,
-+			10000000,	6110230,	5772359,
-+			5328080,	5007240,	4757330,
-+			4545379,	4359109
-+		},
-+		{
-+			9032660,	9032660,	9032660,
-+			10000000,	7373520,	7016940,
-+			6565740,	6250000,	6002650,
-+			5794939,	5610830
-+		},
-+		{
-+			14351329,	12697319,	11875350,
-+			10000000,	8606730,	8275989,
-+			7833449,	7510430,	7257339,
-+			7043970,	6857690
-+		},
-+		{
-+			13286800,	11436090,	10643019,
-+			10000000,	9729470,	9491149,
-+			9096930,	8778640,	8519319,
-+			8299450,	8104829
-+		},
-+		{
-+			11838380,	10778709,	10322740,
-+			10000000,	9866499,	9746059,
-+			9535790,	9354810,	9200339,
-+			9063839,	8940430
-+		}
-+	},
-+	/* 15 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			9193199,	9193199,	9193199,
-+			10000000,	2400999,	2042409,
-+			1450179,	789309,		99999,
-+			99999,		99999
-+		},
-+		{
-+			10755189,	10755189,	10755189,
-+			10000000,	3532319,	3212479,
-+			2803660,	2510200,	2278629,
-+			2078720,	1899970
-+		},
-+		{
-+			8732669,	8732669,	8732669,
-+			10000000,	4821290,	4483030,
-+			4045079,	3737959,	3505080,
-+			3311960,	3143329
-+		},
-+		{
-+			9450280,	9450280,	9450280,
-+			10000000,	6040880,	5718960,
-+			5302609,	5004199,	4771710,
-+			4575310,	4404180
-+		},
-+		{
-+			10520930,	10520930,	10520930,
-+			10000000,	7298259,	6975160,
-+			6552690,	6250000,	6018469,
-+			5822089,	5648869
-+		},
-+		{
-+			14320160,	12683949,	11917040,
-+			10000000,	8541300,	8228710,
-+			7812070,	7509459,	7272909,
-+			7072560,	6895729
-+		},
-+		{
-+			15000000,	11434819,	10650700,
-+			10000000,	9723110,	9480339,
-+			9083300,	8771640,	8524850,
-+			8317480,	8135899
-+		},
-+		{
-+			11750520,	10722860,	10299190,
-+			10000000,	9875990,	9763770,
-+			9567070,	9397709,	9252669,
-+			9124029,	9008929
-+		}
-+	},
-+	/* 16 tap downscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,
-+			0,		-10000000,	-20000000,
-+			-40000000,	-60209999,	-80000000,
-+			-100000000,	-120410003
-+		},
-+		{
-+			10612260,	10612260,	10612260,
-+			10000000,	2308720,	1999289,
-+			1495770,	1009820,	315460,
-+			99999,		99999
-+		},
-+		{
-+			9394969,	9394969,	9394969,
-+			10000000,	3462660,	3162190,
-+			2780120,	2508420,	2295179,
-+			2109449,	1943989
-+		},
-+		{
-+			10609409,	10609409,	10609409,
-+			10000000,	4749999,	4447000,
-+			4039109,	3746300,	3522360,
-+			3336620,	3177059
-+		},
-+		{
-+			9435039,	9435039,	9435039,
-+			10000000,	5978109,	5675160,
-+			5282300,	5000000,	4782429,
-+			4598149,	4438050
-+		},
-+		{
-+			10592620,	10592620,	10592620,
-+			10000000,	7244589,	6940630,
-+			6537730,	6250000,	6027920,
-+			5842260,	5680159
-+		},
-+		{
-+			14282959,	12678509,	11963449,
-+			10000000,	8484349,	8181620,
-+			7785459,	7500000,	7281309,
-+			7095699,	6932809
-+		},
-+		{
-+			15000000,	11434919,	10673819,
-+			10000000,	9708179,	9456859,
-+			9060000,	8760929,	8529940,
-+			8338279,	8172209
-+		},
-+		{
-+			11690390,	10668220,	10277210,
-+			10000000,	9884750,	9780330,
-+			9597110,	9439319,	9304260,
-+			9183580,	9075019
-+		}
-+	}
-+};
-+
-+static const int32_t upscaling_db_table[][UP_DB_SCALES+1][UP_DB_POINTS] = {
-+	/* 3 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			14302920,	14302920,	11709250,
-+			10000000,
-+			8754609,	7692559,	6738259
-+		}
-+	},
-+	/*	4 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			14308999,	12448530,	11007410,
-+			10000000,	9165279,	8435800,
-+			7785279
-+		}
-+	},
-+	/* 5 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			14627330,	12046170,	10862360,
-+			10000000,
-+			9312710,	8737679,	8242470
-+		}
-+	},
-+	/* 6 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			13815449,	11911309,	10801299,
-+			10000000,
-+			9380580,	8878319,	8452050
-+		}
-+	},
-+	/* 7 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			13752900,	11554559,	10637769,
-+			10000000,
-+			9499999,	9079759,	8718389
-+		}
-+	},
-+	/* 8 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			13861900,	11311980,	10543940,
-+			10000000,
-+			9565100,	9198870,	8881340
-+		}
-+	},
-+	/* 9 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			12981410,	11185950,	10491620,
-+			10000000,
-+			9611030,	9286710,	9007279
-+		}
-+	},
-+	/* 10 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			12507469,	11102950,	10457479,
-+			10000000,
-+			9641249,	9344969,	9090980
-+		}
-+	},
-+	/* 11 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			12415319,	10980290,	10405089,
-+			10000000,
-+			9680110,	9413710,	9184579
-+		}
-+	},
-+	/* 12 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			12298769,	10886880,	10367530,
-+			10000000,
-+			9708030,	9464049,	9252949
-+		}
-+	},
-+	/* 13 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			12039999,	10825289,	10341939,
-+			10000000,
-+			9729740,	9505100,	9310669
-+		}
-+	},
-+	/* 14 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			11838380,	10778709,	10322740,
-+			10000000,
-+			9746059,	9535790,	9354810
-+		}
-+	},
-+	/* 15 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			11750520,	10722860,	10299190,
-+			10000000,
-+			9763770,	9567070,	9397709
-+		}
-+	},
-+	/* 16 tap upscaling */
-+	{
-+		{
-+			60209999,	40000000,	20000000,	0,
-+			-20000000,	-40000000,	-60209999
-+		},
-+		{
-+			11690390,	10668220,	10277210,
-+			10000000,
-+			9780330,	9597110,	9439319
-+		}
-+	}
-+};
-+
-+static bool allocate_3d_storage(
-+	struct dc_context *ctx,
-+	struct fixed31_32 ****ptr,
-+	int32_t numberof_tables,
-+	int32_t numberof_rows,
-+	int32_t numberof_columns)
-+{
-+	int32_t indexof_table = 0;
-+	int32_t indexof_row = 0;
-+
-+	struct fixed31_32 ***tables = dc_service_alloc(
-+		ctx,
-+		numberof_tables * sizeof(struct fixed31_32 **));
-+
-+	if (!tables) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	while (indexof_table != numberof_tables) {
-+		struct fixed31_32 **rows = dc_service_alloc(
-+			ctx,
-+			numberof_rows * sizeof(struct fixed31_32 *));
-+
-+		if (!rows) {
-+			BREAK_TO_DEBUGGER();
-+			--indexof_table;
-+			goto failure;
-+		}
-+
-+		tables[indexof_table] = rows;
-+
-+		while (indexof_row != numberof_rows) {
-+			struct fixed31_32 *columns = dc_service_alloc(
-+				ctx,
-+				numberof_columns * sizeof(struct fixed31_32));
-+
-+			if (!columns) {
-+				BREAK_TO_DEBUGGER();
-+				--indexof_row;
-+				goto failure;
-+			}
-+
-+			rows[indexof_row] = columns;
-+
-+			++indexof_row;
-+		}
-+
-+		indexof_row = 0;
-+
-+		++indexof_table;
-+	}
-+
-+	*ptr = tables;
-+
-+	return true;
-+
-+failure:
-+
-+	while (indexof_table >= 0) {
-+		while (indexof_row >= 0) {
-+			dc_service_free(ctx, tables[indexof_table][indexof_row]);
-+
-+			--indexof_row;
-+		}
-+
-+		indexof_row = numberof_rows - 1;
-+
-+		dc_service_free(ctx, tables[indexof_table]);
-+
-+		--indexof_table;
-+	}
-+
-+	dc_service_free(ctx, tables);
-+
-+	return false;
-+}
-+
-+static void destroy_3d_storage(
-+	struct dc_context *ctx,
-+	struct fixed31_32 ****ptr,
-+	uint32_t numberof_tables,
-+	uint32_t numberof_rows)
-+{
-+	struct fixed31_32 ***tables = *ptr;
-+
-+	uint32_t indexof_table = 0;
-+
-+	if (!tables)
-+		return;
-+
-+	while (indexof_table != numberof_tables) {
-+		uint32_t indexof_row = 0;
-+
-+		while (indexof_row != numberof_rows) {
-+			dc_service_free(
-+				ctx, tables[indexof_table][indexof_row]);
-+
-+			++indexof_row;
-+		};
-+
-+		dc_service_free(ctx, tables[indexof_table]);
-+
-+		++indexof_table;
-+	};
-+
-+	dc_service_free(ctx, tables);
-+
-+	*ptr = NULL;
-+}
-+
-+static bool create_downscaling_table(
-+	struct scaler_filter *filter)
-+{
-+	const int32_t numberof_tables =
-+		ARRAY_SIZE(downscaling_db_table);
-+	const int32_t numberof_rows =
-+		ARRAY_SIZE(downscaling_db_table[0]);
-+	const int32_t numberof_columns =
-+		ARRAY_SIZE(downscaling_db_table[0][0]);
-+
-+	int32_t indexof_table = 0;
-+
-+	if (!allocate_3d_storage(filter->ctx, &filter->downscaling_table,
-+		numberof_tables, numberof_rows, numberof_columns)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	while (indexof_table != numberof_tables) {
-+		struct fixed31_32 **table =
-+			filter->downscaling_table[indexof_table];
-+
-+		int32_t indexof_row = 0;
-+
-+		while (indexof_row != numberof_rows) {
-+			struct fixed31_32 *row = table[indexof_row];
-+
-+			int32_t indexof_column = 0;
-+
-+			while (indexof_column != numberof_columns) {
-+				row[indexof_column] =
-+dal_fixed31_32_from_fraction(
-+	downscaling_db_table[indexof_table][indexof_row][indexof_column],
-+	CONST_DIVIDER);
-+
-+				++indexof_column;
-+			}
-+
-+			++indexof_row;
-+		}
-+
-+		++indexof_table;
-+	}
-+
-+	return true;
-+}
-+
-+static inline void destroy_downscaling_table(
-+	struct scaler_filter *filter)
-+{
-+	destroy_3d_storage(
-+		filter->ctx,
-+		&filter->downscaling_table,
-+		ARRAY_SIZE(downscaling_db_table),
-+		ARRAY_SIZE(downscaling_db_table[0]));
-+}
-+
-+static bool create_upscaling_table(
-+	struct scaler_filter *filter)
-+{
-+	const int32_t numberof_tables =
-+		ARRAY_SIZE(upscaling_db_table);
-+	const int32_t numberof_rows =
-+		ARRAY_SIZE(upscaling_db_table[0]);
-+	const int32_t numberof_columns =
-+		ARRAY_SIZE(upscaling_db_table[0][0]);
-+
-+	int32_t indexof_table = 0;
-+
-+	if (!allocate_3d_storage(filter->ctx, &filter->upscaling_table,
-+		numberof_tables, numberof_rows, numberof_columns)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	while (indexof_table != numberof_tables) {
-+		struct fixed31_32 **table =
-+			filter->upscaling_table[indexof_table];
-+
-+		int32_t indexof_row = 0;
-+
-+		while (indexof_row != numberof_rows) {
-+			struct fixed31_32 *row = table[indexof_row];
-+
-+			int32_t indexof_column = 0;
-+
-+			while (indexof_column != numberof_columns) {
-+				row[indexof_column] =
-+dal_fixed31_32_from_fraction(
-+	upscaling_db_table[indexof_table][indexof_row][indexof_column],
-+	CONST_DIVIDER);
-+
-+				++indexof_column;
-+			}
-+
-+			++indexof_row;
-+		}
-+
-+		++indexof_table;
-+	}
-+
-+	return true;
-+}
-+
-+static inline void destroy_upscaling_table(
-+	struct scaler_filter *filter)
-+{
-+	destroy_3d_storage(
-+		filter->ctx,
-+		&filter->upscaling_table,
-+		ARRAY_SIZE(upscaling_db_table),
-+		ARRAY_SIZE(upscaling_db_table[0]));
-+}
-+
-+static bool same_filter_required(
-+	struct scaler_filter *filter,
-+	const struct scaler_filter_params *params,
-+	uint32_t src_size,
-+	uint32_t dst_size)
-+{
-+	if (!filter->src_size)
-+		return false;
-+	if (!filter->dst_size)
-+		return false;
-+	if (filter->src_size != src_size)
-+		return false;
-+	if (filter->dst_size != dst_size)
-+		return false;
-+	if (filter->params.taps != params->taps)
-+		return false;
-+	if (filter->params.phases != params->phases)
-+		return false;
-+	if (filter->params.sharpness != params->sharpness)
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * @brief
-+ *                                            (scale_max - scale_min)
-+ * result = scale_min + (value - value_min) * -----------------------
-+ *                                            (value_max - value_min)
-+ */
-+
-+static struct fixed31_32 interpolate(
-+	struct fixed31_32 value,
-+	struct fixed31_32 value_min,
-+	struct fixed31_32 value_max,
-+	struct fixed31_32 scale_min,
-+	struct fixed31_32 scale_max)
-+{
-+	return dal_fixed31_32_add(
-+		scale_min,
-+		dal_fixed31_32_div(
-+			dal_fixed31_32_mul(
-+				dal_fixed31_32_sub(
-+					value,
-+					value_min),
-+				dal_fixed31_32_sub(
-+					scale_max,
-+					scale_min)),
-+			dal_fixed31_32_sub(
-+				value_max,
-+				value_min)));
-+}
-+
-+static bool map_sharpness(
-+	struct scaler_filter *filter,
-+	const struct scaler_filter_params *params,
-+	uint32_t src_size,
-+	uint32_t dst_size,
-+	struct fixed31_32 *attenuation,
-+	struct fixed31_32 *decibels_at_nyquist)
-+{
-+	struct fixed31_32 ratio = dal_fixed31_32_from_fraction(
-+		dst_size,
-+		src_size);
-+
-+	const struct fixed31_32 sharp_flat =
-+		dal_fixed31_32_from_fraction(MIN_SHARPNESS + MAX_SHARPNESS, 2);
-+
-+	struct fixed31_32 sharp_max =
-+		dal_fixed31_32_from_int(MAX_SHARPNESS);
-+	struct fixed31_32 sharp_min =
-+		dal_fixed31_32_from_int(MIN_SHARPNESS);
-+
-+	uint32_t index = params->taps - 3;
-+
-+	struct fixed31_32 ratio_low;
-+	struct fixed31_32 ratio_up;
-+
-+	struct fixed31_32 db_min;
-+	struct fixed31_32 db_flat;
-+	struct fixed31_32 db_max;
-+	struct fixed31_32 db_value;
-+
-+	uint32_t i0;
-+	uint32_t i1;
-+	uint32_t row0;
-+	uint32_t row1;
-+
-+	int32_t sharp = params->sharpness;
-+
-+	if (sharp < MIN_SHARPNESS)
-+		sharp = MIN_SHARPNESS;
-+	else if (sharp > MAX_SHARPNESS)
-+		sharp = MAX_SHARPNESS;
-+
-+	if (params->flags.bits.HORIZONTAL) {
-+		if (dal_fixed31_32_lt(ratio, max_hor_downscale())) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		} else if (dal_fixed31_32_lt(
-+			max_hor_upscale(), ratio)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	} else {
-+		if (dal_fixed31_32_lt(ratio, max_ver_downscale())) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		} else if (dal_fixed31_32_lt(
-+			max_ver_upscale(), ratio)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	}
-+
-+	if (dst_size >= src_size) {
-+		if (sharp < 0) {
-+			db_max = up_db_flat();
-+			db_min = up_db_fuzzy();
-+
-+			sharp_max = sharp_flat;
-+		} else {
-+			db_max = up_db_sharp();
-+			db_min = up_db_flat();
-+
-+			sharp_min = sharp_flat;
-+		}
-+
-+		db_value = interpolate(
-+			dal_fixed31_32_from_int(sharp),
-+			sharp_min, sharp_max,
-+			db_min, db_max);
-+
-+		i0 = 0;
-+
-+		while (dal_fixed31_32_lt(
-+			db_value, filter->upscaling_table[index][0][i0]) &&
-+			(i0 < UP_DB_POINTS - 1))
-+			++i0;
-+
-+		i1 = i0 + 1;
-+
-+		if (i0 == UP_DB_POINTS - 1)
-+			i1 = i0--;
-+
-+		sharp_max = filter->upscaling_table[index][1][i0];
-+		sharp_min = filter->upscaling_table[index][1][i1];
-+
-+		db_max = filter->upscaling_table[index][0][i0];
-+		db_min = filter->upscaling_table[index][0][i1];
-+
-+		*attenuation = interpolate(
-+			db_value,
-+			db_max, db_min,
-+			sharp_max, sharp_min);
-+
-+		*decibels_at_nyquist = db_value;
-+
-+		return true;
-+	} else if ((5 * dst_size) < (src_size << 2)) {
-+		if (sharp < 0) {
-+			db_max = down_db_flat();
-+			db_min = down_db_fuzzy();
-+
-+			sharp_max = sharp_flat;
-+		} else {
-+			db_max = down_db_sharp();
-+			db_min = down_db_flat();
-+
-+			sharp_min = sharp_flat;
-+		}
-+
-+		db_value = interpolate(
-+			dal_fixed31_32_from_int(sharp),
-+			sharp_min, sharp_max,
-+			db_min, db_max);
-+	} else {
-+		struct fixed31_32 db_value_min =
-+			filter->downscaling_table[index][0][0];
-+
-+		struct fixed31_32 db_value_max =
-+			filter->downscaling_table[index][0][DOWN_DB_POINTS - 1];
-+
-+		db_min = interpolate(
-+			ratio,
-+			threshold_ratio_low(), threshold_ratio_up(),
-+			down_db_fuzzy(), up_db_fuzzy());
-+
-+		db_flat = interpolate(
-+			ratio,
-+			threshold_ratio_low(), threshold_ratio_up(),
-+			down_db_flat(), up_db_flat());
-+
-+		db_max = interpolate(
-+			ratio,
-+			threshold_ratio_low(), threshold_ratio_up(),
-+			down_db_sharp(), up_db_sharp());
-+
-+		if (sharp < 0) {
-+			db_max = db_flat;
-+
-+			db_value = interpolate(
-+				dal_fixed31_32_from_int(sharp),
-+				sharp_min, dal_fixed31_32_zero,
-+				db_min, db_max);
-+		} else {
-+			db_min = db_flat;
-+
-+			db_value = interpolate(
-+				dal_fixed31_32_from_int(sharp),
-+				dal_fixed31_32_zero, sharp_max,
-+				db_min, db_max);
-+		}
-+
-+		if (dal_fixed31_32_lt(db_value_min, db_value))
-+			db_value = db_value_min;
-+		else if (dal_fixed31_32_lt(db_value, db_value_max))
-+			db_value = db_value_max;
-+	}
-+
-+	i1 = 0;
-+
-+	while (dal_fixed31_32_lt(db_value,
-+		filter->downscaling_table[index][0][i1]) &&
-+		(i1 < DOWN_DB_POINTS - 1))
-+		++i1;
-+
-+	if (i1 == 0)
-+		i0 = i1++;
-+	else
-+		i0 = i1 - 1;
-+
-+	row0 = dal_fixed31_32_round(
-+		dal_fixed31_32_mul_int(ratio, DOWN_DB_SCALES));
-+
-+	if (dal_fixed31_32_lt(
-+		dal_fixed31_32_from_fraction(row0, DOWN_DB_SCALES), ratio)) {
-+		row1 = row0 + 1;
-+
-+		if (row1 > DOWN_DB_SCALES) {
-+			row1 = DOWN_DB_SCALES;
-+			row0 = row1 - 1;
-+		}
-+	} else {
-+		row1 = row0--;
-+
-+		if (row0 < 1) {
-+			row0 = 1;
-+			row1 = 2;
-+		}
-+	}
-+
-+	ratio_low = dal_fixed31_32_from_fraction(row0, DOWN_DB_SCALES);
-+	ratio_up = dal_fixed31_32_from_fraction(row1, DOWN_DB_SCALES);
-+
-+	sharp_max = interpolate(
-+		ratio,
-+		ratio_low, ratio_up,
-+		filter->downscaling_table[index][row0][i0],
-+		filter->downscaling_table[index][row1][i0]);
-+
-+	sharp_min = interpolate(
-+		ratio,
-+		ratio_low, ratio_up,
-+		filter->downscaling_table[index][row0][i1],
-+		filter->downscaling_table[index][row1][i1]);
-+
-+	db_max = filter->downscaling_table[index][0][i0];
-+	db_min = filter->downscaling_table[index][0][i1];
-+
-+	*attenuation = interpolate(
-+		db_value,
-+		db_max, db_min,
-+		sharp_max, sharp_min);
-+
-+	*decibels_at_nyquist = db_value;
-+
-+	return true;
-+}
-+
-+static inline struct fixed31_32 lanczos(
-+	struct fixed31_32 x,
-+	struct fixed31_32 a2)
-+{
-+	return dal_fixed31_32_mul(
-+		dal_fixed31_32_sinc(x),
-+		dal_fixed31_32_sinc(
-+			dal_fixed31_32_mul(x, a2)));
-+}
-+
-+static bool generate_filter(
-+	struct scaler_filter *filter,
-+	const struct scaler_filter_params *params,
-+	struct fixed31_32 attenuation,
-+	struct fixed31_32 *ringing)
-+{
-+	uint32_t n = params->phases * params->taps;
-+
-+	uint32_t coefficients_quantity = n;
-+	uint32_t coefficients_sum_quantity = params->phases;
-+
-+	uint32_t i;
-+	uint32_t i_limit;
-+	uint32_t j;
-+	uint32_t m;
-+
-+	struct fixed31_32 attenby2;
-+
-+	struct fixed31_32 a_max = dal_fixed31_32_zero;
-+	struct fixed31_32 a_min = dal_fixed31_32_zero;
-+
-+	if (filter->coefficients_quantity < coefficients_quantity) {
-+		if (filter->coefficients) {
-+			dc_service_free(filter->ctx, filter->coefficients);
-+
-+			filter->coefficients = NULL;
-+			filter->coefficients_quantity = 0;
-+		}
-+
-+		filter->coefficients = dc_service_alloc(
-+			filter->ctx,
-+			coefficients_quantity * sizeof(struct fixed31_32));
-+
-+		if (!filter->coefficients) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		filter->coefficients_quantity = coefficients_quantity;
-+	}
-+
-+	i = 0;
-+
-+	while (i != filter->coefficients_quantity) {
-+		filter->coefficients[i] = dal_fixed31_32_zero;
-+
-+		++i;
-+	}
-+
-+	if (filter->coefficients_sum_quantity < coefficients_sum_quantity) {
-+		if (filter->coefficients_sum) {
-+			dc_service_free(filter->ctx, filter->coefficients_sum);
-+
-+			filter->coefficients_sum = NULL;
-+			filter->coefficients_sum_quantity = 0;
-+		}
-+
-+		filter->coefficients_sum = dc_service_alloc(
-+			filter->ctx,
-+			coefficients_sum_quantity * sizeof(struct fixed31_32));
-+
-+		if (!filter->coefficients_sum) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		filter->coefficients_sum_quantity = coefficients_sum_quantity;
-+	}
-+
-+	i = 0;
-+
-+	while (i != filter->coefficients_sum_quantity) {
-+		filter->coefficients_sum[i] = dal_fixed31_32_zero;
-+
-+		++i;
-+	}
-+
-+	m = 0;
-+
-+	attenby2 = dal_fixed31_32_div_int(
-+		dal_fixed31_32_mul_int(attenuation, params->taps), 2);
-+
-+	i = 1;
-+
-+	while (i <= params->taps) {
-+		j = 0;
-+
-+		while (j != params->phases) {
-+			struct fixed31_32 x = dal_fixed31_32_mul(
-+				dal_fixed31_32_pi,
-+				dal_fixed31_32_from_fraction(
-+					(int64_t)(m << 1) - n, n));
-+
-+			uint32_t index =
-+				(params->taps - i) * params->phases + j;
-+
-+			filter->coefficients[index] = lanczos(x, attenby2);
-+
-+			++m;
-+
-+			++j;
-+		}
-+
-+		++i;
-+	}
-+
-+	i = 0;
-+
-+	while (i != params->phases) {
-+		filter->coefficients_sum[i] = dal_fixed31_32_zero;
-+
-+		m = i;
-+
-+		j = 0;
-+
-+		while (j != params->taps) {
-+			filter->coefficients_sum[i] =
-+				dal_fixed31_32_add(
-+					filter->coefficients_sum[i],
-+					filter->coefficients[m]);
-+
-+			m += params->phases;
-+
-+			++j;
-+		}
-+
-+		++i;
-+	}
-+
-+	i = 0;
-+
-+	while (i != params->phases) {
-+		m = i;
-+
-+		j = 0;
-+
-+		while (j != params->taps) {
-+			filter->coefficients[m] =
-+				dal_fixed31_32_div(
-+					filter->coefficients[m],
-+					filter->coefficients_sum[i]);
-+
-+			m += params->phases;
-+
-+			++j;
-+		}
-+
-+		++i;
-+	}
-+
-+	i = 0;
-+	i_limit = (params->phases >> 1) + 1;
-+
-+	while (i != i_limit) {
-+		m = i;
-+
-+		j = 0;
-+
-+		while (j != params->taps) {
-+			struct fixed31_32 tmp = filter->coefficients[m];
-+
-+			filter->filter[i * params->taps + j] = tmp;
-+
-+			if (dal_fixed31_32_lt(
-+				tmp, dal_fixed31_32_zero) &&
-+				dal_fixed31_32_lt(tmp, a_min))
-+				a_min = tmp;
-+			else if (dal_fixed31_32_lt(
-+				dal_fixed31_32_zero, tmp) &&
-+				dal_fixed31_32_lt(a_max, tmp))
-+				a_max = tmp;
-+
-+			m += params->phases;
-+
-+			++j;
-+		}
-+
-+		++i;
-+	}
-+
-+	if (dal_fixed31_32_eq(a_min, dal_fixed31_32_zero))
-+		*ringing = dal_fixed31_32_from_int(100);
-+	else
-+		*ringing = dal_fixed31_32_min(
-+			dal_fixed31_32_abs(
-+				dal_fixed31_32_div(a_max, a_min)),
-+			dal_fixed31_32_from_int(100));
-+
-+	return true;
-+}
-+
-+static bool construct_scaler_filter(
-+	struct dc_context *ctx,
-+	struct scaler_filter *filter)
-+{
-+	filter->src_size = 0;
-+	filter->dst_size = 0;
-+	filter->filter = NULL;
-+	filter->integer_filter = NULL;
-+	filter->filter_size_allocated = 0;
-+	filter->filter_size_effective = 0;
-+	filter->coefficients = NULL;
-+	filter->coefficients_quantity = 0;
-+	filter->coefficients_sum = NULL;
-+	filter->coefficients_sum_quantity = 0;
-+	filter->downscaling_table = NULL;
-+	filter->upscaling_table = NULL;
-+	filter->ctx = ctx;
-+
-+	if (!create_downscaling_table(filter)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!create_upscaling_table(filter)) {
-+		BREAK_TO_DEBUGGER();
-+		destroy_downscaling_table(filter);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static void destruct_scaler_filter(
-+	struct scaler_filter *filter)
-+{
-+	if (filter->coefficients_sum)
-+		dc_service_free(filter->ctx, filter->coefficients_sum);
-+
-+	if (filter->coefficients)
-+		dc_service_free(filter->ctx, filter->coefficients);
-+
-+	if (filter->integer_filter)
-+		dc_service_free(filter->ctx, filter->integer_filter);
-+
-+	if (filter->filter)
-+		dc_service_free(filter->ctx, filter->filter);
-+
-+	destroy_upscaling_table(filter);
-+
-+	destroy_downscaling_table(filter);
-+}
-+
-+struct scaler_filter *dal_scaler_filter_create(struct dc_context *ctx)
-+{
-+	struct scaler_filter *filter =
-+		dc_service_alloc(ctx, sizeof(struct scaler_filter));
-+
-+	if (!filter) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct_scaler_filter(ctx, filter))
-+		return filter;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dc_service_free(ctx, filter);
-+
-+	return NULL;
-+}
-+
-+bool dal_scaler_filter_generate(
-+	struct scaler_filter *filter,
-+	const struct scaler_filter_params *params,
-+	uint32_t src_size,
-+	uint32_t dst_size)
-+{
-+	uint32_t filter_size_required;
-+
-+	struct fixed31_32 attenuation;
-+	struct fixed31_32 decibels_at_nyquist;
-+	struct fixed31_32 ringing;
-+
-+	if (!params) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if ((params->taps < 3) || (params->taps > 16)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!src_size || !dst_size) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (same_filter_required(filter, params, src_size, dst_size))
-+		return true;
-+
-+	filter_size_required =
-+		params->taps * ((params->phases >> 1) + 1);
-+
-+	if (filter_size_required > filter->filter_size_allocated) {
-+		if (filter->filter) {
-+			dc_service_free(filter->ctx, filter->filter);
-+
-+			filter->filter = 0;
-+			filter->filter_size_allocated = 0;
-+		}
-+
-+		filter->filter = dc_service_alloc(
-+			filter->ctx,
-+			filter_size_required * sizeof(struct fixed31_32));
-+
-+		if (!filter->filter) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (filter->integer_filter) {
-+			dc_service_free(filter->ctx, filter->integer_filter);
-+
-+			filter->integer_filter = 0;
-+		}
-+
-+		filter->integer_filter = dc_service_alloc(
-+			filter->ctx,
-+			filter_size_required * sizeof(uint32_t));
-+
-+		if (!filter->integer_filter) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		filter->filter_size_allocated = filter_size_required;
-+	}
-+
-+	filter->filter_size_effective = filter_size_required;
-+
-+	if (!map_sharpness(filter, params, src_size, dst_size,
-+		&attenuation, &decibels_at_nyquist)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!generate_filter(filter, params, attenuation, &ringing)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	filter->params = *params;
-+	filter->src_size = src_size;
-+	filter->dst_size = dst_size;
-+
-+	return true;
-+}
-+
-+const struct fixed31_32 *dal_scaler_filter_get(
-+	const struct scaler_filter *filter,
-+	uint32_t **data,
-+	uint32_t *number)
-+{
-+	if (!number) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (!data) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	*number = filter->filter_size_effective;
-+	*data = filter->integer_filter;
-+
-+	return filter->filter;
-+}
-+
-+void dal_scaler_filter_destroy(
-+	struct scaler_filter **filter)
-+{
-+	if (!filter || !*filter) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	destruct_scaler_filter(*filter);
-+
-+	dc_service_free((*filter)->ctx, *filter);
-+
-+	*filter = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
-new file mode 100644
-index 0000000..668691d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
-@@ -0,0 +1,74 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SCALER_FILTER_H__
-+#define __DAL_SCALER_FILTER_H__
-+
-+struct scaler_filter_params {
-+	uint32_t taps; /* 3...16 */
-+	uint32_t phases;
-+	int32_t sharpness; /* -50...50 */
-+	union {
-+		struct {
-+			uint32_t HORIZONTAL:1;
-+			uint32_t RESERVED:31;
-+		} bits;
-+		uint32_t value;
-+	} flags;
-+};
-+
-+struct q31_32;
-+
-+struct scaler_filter {
-+	struct scaler_filter_params params;
-+	uint32_t src_size;
-+	uint32_t dst_size;
-+	struct fixed31_32 *filter;
-+	uint32_t *integer_filter;
-+	uint32_t filter_size_allocated;
-+	uint32_t filter_size_effective;
-+	struct fixed31_32 *coefficients;
-+	uint32_t coefficients_quantity;
-+	struct fixed31_32 *coefficients_sum;
-+	uint32_t coefficients_sum_quantity;
-+	struct fixed31_32 ***downscaling_table;
-+	struct fixed31_32 ***upscaling_table;
-+	struct dc_context *ctx;
-+};
-+
-+struct scaler_filter *dal_scaler_filter_create(struct dc_context *ctx);
-+void dal_scaler_filter_destroy(struct scaler_filter **ptr);
-+
-+bool dal_scaler_filter_generate(
-+	struct scaler_filter *filter,
-+	const struct scaler_filter_params *params,
-+	uint32_t src_size,
-+	uint32_t dst_size);
-+
-+const struct fixed31_32 *dal_scaler_filter_get(
-+	const struct scaler_filter *filter,
-+	uint32_t **data,
-+	uint32_t *number);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/Makefile b/drivers/gpu/drm/amd/dal/dc/connector/Makefile
-new file mode 100644
-index 0000000..ebd4115
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/connector/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'connector' sub-component of DAL.
-+# It provides the control and status of HW connectors blocks.
-+
-+
-+CONNECTOR = connector_base.o connector_signals.o
-+
-+AMD_DAL_CONNECTOR = $(addprefix $(AMDDALPATH)/dc/connector/,$(CONNECTOR))
-+
-+AMD_DAL_FILES += $(AMD_DAL_CONNECTOR)
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector.h b/drivers/gpu/drm/amd/dal/dc/connector/connector.h
-new file mode 100644
-index 0000000..7d6057b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/connector/connector.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CONNECTOR_H__
-+#define __DAL_CONNECTOR_H__
-+
-+#include "include/connector_interface.h"
-+
-+extern const uint32_t number_of_default_signals;
-+extern const uint32_t number_of_signals;
-+
-+/* Indexed by enum connector_id */
-+extern const struct connector_signals default_signals[];
-+/* Indexed by enum connector_id */
-+extern const struct connector_signals supported_signals[];
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector_base.c b/drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
-new file mode 100644
-index 0000000..34005fd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
-@@ -0,0 +1,421 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "connector.h"
-+#include "include/irq_interface.h"
-+#include "include/ddc_interface.h"
-+#include "include/connector_interface.h"
-+
-+struct connector {
-+	struct graphics_object_id id;
-+	uint32_t input_signals;
-+	uint32_t output_signals;
-+	struct adapter_service *as;
-+	struct connector_feature_support features;
-+	struct connector_signals default_signals;
-+	struct dc_context *ctx;
-+};
-+
-+static bool connector_construct(
-+	struct connector *connector,
-+	struct dc_context *ctx,
-+	struct adapter_service *as,
-+	struct graphics_object_id go_id)
-+{
-+	bool hw_ddc_polling = false;
-+	struct ddc *ddc;
-+	struct irq *hpd;
-+	enum connector_id connector_id;
-+	uint32_t signals_vector = 0;
-+	uint32_t signals_num = 0;
-+	uint32_t i;
-+
-+	if (!as) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	connector->as = as;
-+	connector->id = go_id;
-+	connector->features.ddc_line = CHANNEL_ID_UNKNOWN;
-+	connector->features.hpd_line = HPD_SOURCEID_UNKNOWN;
-+	connector->ctx = ctx;
-+
-+	ddc = dal_adapter_service_obtain_ddc(as, connector->id);
-+	hpd = dal_adapter_service_obtain_hpd_irq(as, connector->id);
-+
-+	connector_id = dal_graphics_object_id_get_connector_id(go_id);
-+
-+	/* Initialize DDC line */
-+	if (ddc) {
-+		switch (dal_ddc_get_line(ddc)) {
-+		case GPIO_DDC_LINE_DDC1:
-+			connector->features.ddc_line = CHANNEL_ID_DDC1;
-+			break;
-+		case GPIO_DDC_LINE_DDC2:
-+			connector->features.ddc_line = CHANNEL_ID_DDC2;
-+			break;
-+		case GPIO_DDC_LINE_DDC3:
-+			connector->features.ddc_line = CHANNEL_ID_DDC3;
-+			break;
-+		case GPIO_DDC_LINE_DDC4:
-+			connector->features.ddc_line = CHANNEL_ID_DDC4;
-+			break;
-+		case GPIO_DDC_LINE_DDC5:
-+			connector->features.ddc_line = CHANNEL_ID_DDC5;
-+			break;
-+		case GPIO_DDC_LINE_DDC6:
-+			connector->features.ddc_line = CHANNEL_ID_DDC6;
-+			break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			connector->features.ddc_line = CHANNEL_ID_DDC_VGA;
-+			break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			connector->features.ddc_line = CHANNEL_ID_I2C_PAD;
-+			break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			break;
-+		}
-+
-+		/* Initialize HW DDC polling support
-+		 * On DCE6.0 only DDC lines support HW polling (I2cPad does not)
-+		 */
-+
-+		if (dal_adapter_service_is_feature_supported(
-+			FEATURE_ENABLE_HW_EDID_POLLING)) {
-+			switch (dal_ddc_get_line(ddc)) {
-+			case GPIO_DDC_LINE_DDC1:
-+			case GPIO_DDC_LINE_DDC2:
-+			case GPIO_DDC_LINE_DDC3:
-+			case GPIO_DDC_LINE_DDC4:
-+			case GPIO_DDC_LINE_DDC5:
-+			case GPIO_DDC_LINE_DDC6:
-+			case GPIO_DDC_LINE_DDC_VGA:
-+				hw_ddc_polling = true;
-+			break;
-+			default:
-+			break;
-+			}
-+		}
-+
-+		dal_adapter_service_release_ddc(as, ddc);
-+	}
-+
-+	/* Initialize HPD line */
-+	if (hpd) {
-+		switch (dal_irq_get_source(hpd)) {
-+		case DC_IRQ_SOURCE_HPD1:
-+			connector->features.hpd_line = HPD_SOURCEID1;
-+		break;
-+		case DC_IRQ_SOURCE_HPD2:
-+			connector->features.hpd_line = HPD_SOURCEID2;
-+		break;
-+		case DC_IRQ_SOURCE_HPD3:
-+			connector->features.hpd_line = HPD_SOURCEID3;
-+		break;
-+		case DC_IRQ_SOURCE_HPD4:
-+			connector->features.hpd_line = HPD_SOURCEID4;
-+		break;
-+		case DC_IRQ_SOURCE_HPD5:
-+			connector->features.hpd_line = HPD_SOURCEID5;
-+		break;
-+		case DC_IRQ_SOURCE_HPD6:
-+			connector->features.hpd_line = HPD_SOURCEID6;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+		break;
-+		}
-+
-+		dal_adapter_service_release_irq(as, hpd);
-+	}
-+
-+	if ((uint32_t)connector_id >= number_of_default_signals &&
-+		(uint32_t)connector_id >= number_of_signals)
-+		return false;
-+
-+	/* Initialize default signals */
-+	connector->default_signals = default_signals[connector_id];
-+
-+	/* Fill supported signals */
-+	signals_num = supported_signals[connector_id].number_of_signals;
-+	for (i = 0; i < signals_num; i++)
-+		signals_vector |= supported_signals[connector_id].signal[i];
-+
-+	/* Connector supports same set for input and output signals */
-+	connector->input_signals = signals_vector;
-+	connector->output_signals = signals_vector;
-+
-+	switch (connector_id) {
-+	case CONNECTOR_ID_VGA:
-+		if (hw_ddc_polling
-+			&& connector->features.ddc_line != CHANNEL_ID_UNKNOWN)
-+			connector->features.HW_DDC_POLLING = true;
-+	break;
-+	case CONNECTOR_ID_SINGLE_LINK_DVII:
-+	case CONNECTOR_ID_DUAL_LINK_DVII:
-+		if (connector->features.hpd_line != HPD_SOURCEID_UNKNOWN)
-+			connector->features.HPD_FILTERING = true;
-+		if (hw_ddc_polling
-+			&& connector->features.ddc_line != CHANNEL_ID_UNKNOWN)
-+			connector->features.HW_DDC_POLLING = true;
-+	break;
-+	case CONNECTOR_ID_SINGLE_LINK_DVID:
-+	case CONNECTOR_ID_DUAL_LINK_DVID:
-+	case CONNECTOR_ID_HDMI_TYPE_A:
-+	case CONNECTOR_ID_LVDS:
-+	case CONNECTOR_ID_DISPLAY_PORT:
-+	case CONNECTOR_ID_EDP:
-+		if (connector->features.hpd_line != HPD_SOURCEID_UNKNOWN)
-+			connector->features.HPD_FILTERING = true;
-+	break;
-+	default:
-+		connector->features.HPD_FILTERING = false;
-+		connector->features.HW_DDC_POLLING = false;
-+	break;
-+	}
-+
-+	return true;
-+}
-+
-+struct connector *dal_connector_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as,
-+	struct graphics_object_id go_id)
-+{
-+	struct connector *connector = NULL;
-+
-+	connector = dc_service_alloc(ctx, sizeof(struct connector));
-+
-+	if (!connector) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (connector_construct(connector, ctx, as, go_id))
-+		return connector;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dc_service_free(ctx, connector);
-+
-+	return NULL;
-+}
-+
-+void dal_connector_destroy(struct connector **connector)
-+{
-+	if (!connector || !*connector) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dc_service_free((*connector)->ctx, *connector);
-+
-+	*connector = NULL;
-+}
-+
-+uint32_t dal_connector_enumerate_output_signals(
-+	const struct connector *connector)
-+{
-+	return connector->output_signals;
-+}
-+
-+uint32_t dal_connector_enumerate_input_signals(
-+	const struct connector *connector)
-+{
-+	return connector->input_signals;
-+}
-+
-+struct connector_signals dal_connector_get_default_signals(
-+		const struct connector *connector)
-+{
-+	return connector->default_signals;
-+}
-+
-+const struct graphics_object_id dal_connector_get_graphics_object_id(
-+	const struct connector *connector)
-+{
-+	return connector->id;
-+}
-+
-+/*
-+ *  Function: program_hpd_filter
-+ *
-+ *  @brief
-+ *     Programs HPD filter on associated HPD line
-+ *
-+ *  @param [in] delay_on_connect_in_ms: Connect filter timeout
-+ *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
-+ *
-+ *  @return
-+ *     true on success, false otherwise
-+ */
-+bool dal_connector_program_hpd_filter(
-+	const struct connector *connector,
-+	const uint32_t delay_on_connect_in_ms,
-+	const uint32_t delay_on_disconnect_in_ms)
-+{
-+	bool result = false;
-+
-+	struct irq *hpd;
-+
-+	/* Verify feature is supported */
-+
-+	if (!connector->features.HPD_FILTERING)
-+		return result;
-+
-+	/* Obtain HPD handle */
-+
-+	hpd = dal_adapter_service_obtain_hpd_irq(
-+		connector->as, connector->id);
-+
-+	if (!hpd)
-+		return result;
-+
-+	/* Setup HPD filtering */
-+
-+	if (GPIO_RESULT_OK == dal_irq_open(hpd)) {
-+		struct gpio_hpd_config config;
-+
-+		config.delay_on_connect = delay_on_connect_in_ms;
-+		config.delay_on_disconnect = delay_on_disconnect_in_ms;
-+
-+		dal_irq_setup_hpd_filter(hpd, &config);
-+
-+		dal_irq_close(hpd);
-+
-+		result = true;
-+	} else {
-+		ASSERT_CRITICAL(false);
-+	}
-+
-+	/* Release HPD handle */
-+
-+	dal_adapter_service_release_irq(connector->as, hpd);
-+
-+	return result;
-+}
-+
-+/*
-+ *  Function: setup_ddc_polling
-+ *
-+ *  @brief
-+ *     Enables/Disables HW polling on associated DDC line
-+ *
-+ *  @param [in] ddc_config: Specifies polling mode
-+ *
-+ *  @return
-+ *     true on success, false otherwise
-+ */
-+static bool setup_ddc_polling(
-+	const struct connector *connector,
-+	enum gpio_ddc_config_type ddc_config)
-+{
-+	bool result = false;
-+
-+	struct ddc *ddc;
-+
-+	/* Verify feature is supported */
-+
-+	if (!connector->features.HW_DDC_POLLING)
-+		return result;
-+
-+	/* Obtain DDC handle */
-+
-+	ddc = dal_adapter_service_obtain_ddc(
-+		connector->as, connector->id);
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return result;
-+	}
-+
-+	/* Setup DDC polling */
-+
-+	if (GPIO_RESULT_OK == dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-+		GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
-+		dal_ddc_set_config(ddc, ddc_config);
-+
-+		dal_ddc_close(ddc);
-+
-+		result = true;
-+	} else {
-+		BREAK_TO_DEBUGGER();
-+	}
-+
-+	/* Release DDC handle */
-+
-+	dal_adapter_service_release_ddc(connector->as, ddc);
-+
-+	return result;
-+}
-+
-+/*
-+ *  Function: enable_ddc_polling
-+ *
-+ *  @brief
-+ *     Enables HW polling on associated DDC line
-+ *
-+ *  @param [in] is_poll_for_connect: Specifies polling mode
-+ *
-+ *  @return
-+ *     true on success, false otherwise
-+ */
-+bool dal_connector_enable_ddc_polling(
-+	const struct connector *connector,
-+	const bool is_poll_for_connect)
-+{
-+	enum gpio_ddc_config_type ddc_config = is_poll_for_connect ?
-+		GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT :
-+		GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT;
-+
-+	return setup_ddc_polling(connector, ddc_config);
-+}
-+
-+/*
-+ *  Function: disable_ddc_polling
-+ *
-+ *  @brief
-+ *     Disables HW polling on associated DDC line
-+ *
-+ *  @return
-+ *     true on success, false otherwise
-+ */
-+bool dal_connector_disable_ddc_polling(const struct connector *connector)
-+{
-+	return setup_ddc_polling(connector,
-+		GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING);
-+}
-+
-+void dal_connector_get_features(
-+		const struct connector *con,
-+		struct connector_feature_support *cfs)
-+{
-+	dc_service_memmove(cfs, &con->features,
-+			sizeof(struct connector_feature_support));
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c b/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-new file mode 100644
-index 0000000..d1a289d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-@@ -0,0 +1,204 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "connector.h"
-+
-+static const enum signal_type signals_none[] = {
-+		SIGNAL_TYPE_NONE
-+};
-+
-+static const enum signal_type signals_single_link_dvii[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+		SIGNAL_TYPE_RGB
-+};
-+
-+static const enum signal_type signals_dual_link_dvii[] = {
-+		SIGNAL_TYPE_DVI_DUAL_LINK,
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+		SIGNAL_TYPE_RGB
-+};
-+
-+static const enum signal_type signals_single_link_dvid[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK
-+};
-+
-+static const enum signal_type signals_dual_link_dvid[] = {
-+		SIGNAL_TYPE_DVI_DUAL_LINK,
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+};
-+
-+static const enum signal_type signals_vga[] = {
-+		SIGNAL_TYPE_RGB
-+};
-+
-+static const enum signal_type signals_hdmi_type_a[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+		SIGNAL_TYPE_HDMI_TYPE_A
-+};
-+
-+static const enum signal_type signals_lvds[] = {
-+		SIGNAL_TYPE_LVDS
-+};
-+
-+static const enum signal_type signals_pcie[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+		SIGNAL_TYPE_HDMI_TYPE_A,
-+		SIGNAL_TYPE_DISPLAY_PORT
-+};
-+
-+static const enum signal_type signals_hardcode_dvi[] = {
-+		SIGNAL_TYPE_NONE
-+};
-+
-+static const enum signal_type signals_displayport[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+		SIGNAL_TYPE_HDMI_TYPE_A,
-+		SIGNAL_TYPE_DISPLAY_PORT,
-+		SIGNAL_TYPE_DISPLAY_PORT_MST
-+};
-+
-+static const enum signal_type signals_edp[] = {
-+		SIGNAL_TYPE_EDP
-+};
-+
-+static const enum signal_type signals_wireless[] = {
-+		SIGNAL_TYPE_WIRELESS
-+};
-+
-+static const enum signal_type signals_miracast[] = {
-+		SIGNAL_TYPE_WIRELESS
-+};
-+
-+static const enum signal_type default_signals_none[] = {
-+		SIGNAL_TYPE_NONE
-+};
-+
-+static const enum signal_type default_signals_single_link_dvii[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK,
-+		SIGNAL_TYPE_RGB
-+};
-+
-+static const enum signal_type default_signals_dual_link_dvii[] = {
-+		SIGNAL_TYPE_DVI_DUAL_LINK,
-+		SIGNAL_TYPE_RGB
-+};
-+
-+static const enum signal_type default_signals_single_link_dvid[] = {
-+		SIGNAL_TYPE_DVI_SINGLE_LINK
-+};
-+
-+static const enum signal_type default_signals_dual_link_dvid[] = {
-+		SIGNAL_TYPE_DVI_DUAL_LINK,
-+};
-+
-+static const enum signal_type default_signals_vga[] = {
-+		SIGNAL_TYPE_RGB
-+};
-+
-+static const enum signal_type default_signals_hdmi_type_a[] = {
-+		SIGNAL_TYPE_HDMI_TYPE_A
-+};
-+
-+static const enum signal_type default_signals_lvds[] = {
-+		SIGNAL_TYPE_LVDS
-+};
-+
-+static const enum signal_type default_signals_pcie[] = {
-+		SIGNAL_TYPE_DISPLAY_PORT
-+};
-+
-+static const enum signal_type default_signals_hardcode_dvi[] = {
-+		SIGNAL_TYPE_NONE
-+};
-+
-+static const enum signal_type default_signals_displayport[] = {
-+		SIGNAL_TYPE_DISPLAY_PORT
-+};
-+
-+static const enum signal_type default_signals_edp[] = {
-+		SIGNAL_TYPE_EDP
-+};
-+
-+static const enum signal_type default_signals_wireless[] = {
-+		SIGNAL_TYPE_WIRELESS
-+};
-+
-+static const enum signal_type default_signals_miracast[] = {
-+		SIGNAL_TYPE_WIRELESS
-+};
-+
-+/*
-+ * Signal arrays
-+ */
-+
-+#define SIGNALS_ARRAY_ELEM(a) {a, ARRAY_SIZE(a)}
-+
-+/* Indexed by enum connector_id */
-+const struct connector_signals default_signals[] = {
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		SIGNALS_ARRAY_ELEM(default_signals_single_link_dvii),
-+		SIGNALS_ARRAY_ELEM(default_signals_dual_link_dvii),
-+		SIGNALS_ARRAY_ELEM(default_signals_single_link_dvid),
-+		SIGNALS_ARRAY_ELEM(default_signals_dual_link_dvid),
-+		SIGNALS_ARRAY_ELEM(default_signals_vga),
-+		SIGNALS_ARRAY_ELEM(default_signals_hdmi_type_a),
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		SIGNALS_ARRAY_ELEM(default_signals_lvds),
-+		SIGNALS_ARRAY_ELEM(default_signals_pcie),
-+		SIGNALS_ARRAY_ELEM(default_signals_hardcode_dvi),
-+		SIGNALS_ARRAY_ELEM(default_signals_displayport),
-+		SIGNALS_ARRAY_ELEM(default_signals_edp),
-+		/* MXM dummy connector */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		SIGNALS_ARRAY_ELEM(default_signals_wireless),
-+		SIGNALS_ARRAY_ELEM(default_signals_miracast)
-+};
-+
-+const uint32_t number_of_default_signals = ARRAY_SIZE(default_signals);
-+
-+/* Indexed by enum connector_id */
-+const struct connector_signals supported_signals[] = {
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		SIGNALS_ARRAY_ELEM(signals_single_link_dvii),
-+		SIGNALS_ARRAY_ELEM(signals_dual_link_dvii),
-+		SIGNALS_ARRAY_ELEM(signals_single_link_dvid),
-+		SIGNALS_ARRAY_ELEM(signals_dual_link_dvid),
-+		SIGNALS_ARRAY_ELEM(signals_vga),
-+		SIGNALS_ARRAY_ELEM(signals_hdmi_type_a),
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		SIGNALS_ARRAY_ELEM(signals_lvds),
-+		SIGNALS_ARRAY_ELEM(signals_pcie),
-+		SIGNALS_ARRAY_ELEM(signals_hardcode_dvi),
-+		SIGNALS_ARRAY_ELEM(signals_displayport),
-+		SIGNALS_ARRAY_ELEM(signals_edp),
-+		/* MXM dummy connector */
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		SIGNALS_ARRAY_ELEM(signals_wireless),
-+		SIGNALS_ARRAY_ELEM(signals_miracast)
-+};
-+
-+const uint32_t number_of_signals = ARRAY_SIZE(supported_signals);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-new file mode 100644
-index 0000000..e13ce4e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -0,0 +1,849 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ */
-+
-+#include "dc_services.h"
-+
-+#include "dc.h"
-+
-+#include "core_status.h"
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+
-+#include "resource.h"
-+
-+#include "adapter_service_interface.h"
-+#include "clock_source_interface.h"
-+
-+#include "include/irq_service_interface.h"
-+#include "bandwidth_calcs.h"
-+#include "include/irq_service_interface.h"
-+
-+#include "link_hwss.h"
-+
-+/*******************************************************************************
-+ * Private structures
-+ ******************************************************************************/
-+
-+struct dc_target_sync_report {
-+	uint32_t h_count;
-+	uint32_t v_count;
-+};
-+
-+struct dc_sync_report {
-+	uint32_t targets_num;
-+	struct dc_target_sync_report trg_reports[MAX_TARGET_NUM];
-+};
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+static void destroy_links(struct dc *dc)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+
-+		if (NULL != dc->links[i])
-+			link_destroy(&dc->links[i]);
-+	}
-+}
-+
-+
-+static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
-+{
-+	int i;
-+	int connectors_num;
-+
-+	dc->link_count = 0;
-+
-+	connectors_num = dal_bios_parser_get_connectors_number(
-+			dal_adapter_service_get_bios_parser(
-+					init_params->adapter_srv));
-+
-+	if (0 == connectors_num || connectors_num > ENUM_ID_COUNT) {
-+		dal_error("DC: Invalid number of connectors!\n");
-+		return false;
-+	}
-+
-+	dal_output_to_console("%s: connectors_num:%d\n", __func__,
-+			connectors_num);
-+
-+	dc->links = dc_service_alloc(
-+		init_params->ctx, connectors_num * sizeof(struct core_link *));
-+
-+	if (NULL == dc->links) {
-+		dal_error("DC: failed to allocate 'links' storage!\n");
-+		goto allocate_dc_links_storage_fail;
-+	}
-+
-+	for (i = 0; i < connectors_num; i++) {
-+		struct link_init_data link_init_params = {0};
-+		struct core_link *link;
-+
-+		link_init_params.ctx = init_params->ctx;
-+		link_init_params.adapter_srv = init_params->adapter_srv;
-+		link_init_params.connector_index = i;
-+		link_init_params.link_index = dc->link_count;
-+		link_init_params.dc = dc;
-+		link =  link_create(&link_init_params);
-+
-+		if (link) {
-+			dc->links[dc->link_count] = link;
-+			link->dc = dc;
-+			++dc->link_count;
-+		}
-+		else {
-+			dal_error("DC: failed to create link!\n");
-+		}
-+	}
-+
-+	if (!dc->link_count) {
-+		dal_error("DC: no 'links' were created!\n");
-+		goto allocate_dc_links_storage_fail;
-+	}
-+
-+	return true;
-+
-+allocate_dc_links_storage_fail:
-+	return false;
-+}
-+
-+static void init_hw(struct dc *dc)
-+{
-+	int i;
-+	struct bios_parser *bp;
-+	struct transform *xfm;
-+
-+	bp = dal_adapter_service_get_bios_parser(dc->res_pool.adapter_srv);
-+	for(i = 0; i < dc->res_pool.controller_count; i++) {
-+		xfm = dc->res_pool.transforms[i];
-+
-+		dc->hwss.enable_display_power_gating(
-+				dc->ctx, i, bp,
-+				PIPE_GATING_CONTROL_INIT);
-+		dc->hwss.enable_display_power_gating(
-+				dc->ctx, i, bp,
-+				PIPE_GATING_CONTROL_DISABLE);
-+
-+		dc->hwss.transform_power_up(xfm);
-+		dc->hwss.enable_display_pipe_clock_gating(
-+			dc->ctx,
-+			true);
-+	}
-+
-+	dc->hwss.clock_gating_power_up(dc->ctx, false);
-+	dal_bios_parser_power_up(bp);
-+	/***************************************/
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		/****************************************/
-+		/* Power up AND update implementation according to the
-+		 * required signal (which may be different from the
-+		 * default signal on connector). */
-+		struct core_link *link = dc->links[i];
-+		if (dc->hwss.encoder_power_up(link->link_enc) != ENCODER_RESULT_OK) {
-+			dal_error("Failed link encoder power up!\n");
-+			return;
-+		}
-+	}
-+
-+	dal_bios_parser_set_scratch_acc_mode_change(bp);
-+
-+	for(i = 0; i < dc->res_pool.controller_count; i++) {
-+		struct timing_generator *tg = dc->res_pool.timing_generators[i];
-+
-+		dc->hwss.disable_vga(tg);
-+
-+		/* Blank controller using driver code instead of
-+		 * command table. */
-+		dc->hwss.disable_memory_requests(tg);
-+	}
-+
-+	for(i = 0; i < dc->res_pool.audio_count; i++) {
-+		struct audio *audio = dc->res_pool.audios[i];
-+
-+		if (dal_audio_power_up(audio) != AUDIO_RESULT_OK)
-+			dal_error("Failed audio power up!\n");
-+	}
-+
-+}
-+
-+static struct adapter_service *create_as(
-+		struct dc_init_data *dc_init_data,
-+		const struct dal_init_data *init)
-+{
-+	struct adapter_service *as = NULL;
-+	struct as_init_data init_data;
-+
-+	dc_service_memset(&init_data, 0, sizeof(init_data));
-+
-+	init_data.ctx = dc_init_data->ctx;
-+
-+	/* BIOS parser init data */
-+	init_data.bp_init_data.ctx = dc_init_data->ctx;
-+	init_data.bp_init_data.bios = init->asic_id.atombios_base_address;
-+
-+	/* HW init data */
-+	init_data.hw_init_data.chip_id = init->asic_id.chip_id;
-+	init_data.hw_init_data.chip_family = init->asic_id.chip_family;
-+	init_data.hw_init_data.pci_revision_id = init->asic_id.pci_revision_id;
-+	init_data.hw_init_data.fake_paths_num = init->asic_id.fake_paths_num;
-+	init_data.hw_init_data.feature_flags = init->asic_id.feature_flags;
-+	init_data.hw_init_data.hw_internal_rev = init->asic_id.hw_internal_rev;
-+	init_data.hw_init_data.runtime_flags = init->asic_id.runtime_flags;
-+	init_data.hw_init_data.vram_width = init->asic_id.vram_width;
-+	init_data.hw_init_data.vram_type = init->asic_id.vram_type;
-+
-+	/* bdf is BUS,DEVICE,FUNCTION*/
-+	init_data.bdf_info = init->bdf_info;
-+
-+	init_data.display_param = &init->display_param;
-+
-+	as = dal_adapter_service_create(&init_data);
-+
-+	return as;
-+}
-+
-+static void bw_calcs_data_update_from_pplib(struct dc *dc)
-+{
-+	struct dal_system_clock_range clk_range = { 0 };
-+
-+	dc_service_get_system_clocks_range(dc->ctx, &clk_range);
-+
-+	/* on CZ Gardenia from PPLib we get:
-+	 * clk_range.max_mclk:80000
-+	 * clk_range.min_mclk:80000
-+	 * clk_range.max_sclk:80000
-+	 * clk_range.min_sclk:30000 */
-+
-+	/* The values for calcs are stored in units of MHz, so for example
-+	 * 80000 will be stored as 800. */
-+	dc->bw_vbios.high_sclk = frc_to_fixed(clk_range.max_sclk, 100);
-+	dc->bw_vbios.low_sclk = frc_to_fixed(clk_range.min_sclk, 100);
-+
-+	dc->bw_vbios.high_yclk = frc_to_fixed(clk_range.max_mclk, 100);
-+	dc->bw_vbios.low_yclk = frc_to_fixed(clk_range.min_mclk, 100);
-+}
-+
-+static bool construct(struct dc *dc, const struct dal_init_data *init_params)
-+{
-+	struct dal_logger *logger;
-+	/* Tempory code
-+	 * TODO: replace dal_init_data with dc_init_data when dal is removed
-+	 */
-+	struct dc_init_data dc_init_data = {0};
-+
-+	/* Create dc context */
-+	/* A temp dc context is used only to allocate the memory for actual
-+	 * dc context */
-+	struct dc_context ctx = {0};
-+	ctx.cgs_device = init_params->cgs_device;
-+	ctx.dc = dc;
-+
-+	dc_init_data.ctx = dc_service_alloc(&ctx, sizeof(*dc_init_data.ctx));
-+	if (!dc_init_data.ctx) {
-+		dal_error("%s: failed to create ctx\n", __func__);
-+		goto ctx_fail;
-+	}
-+	dc_init_data.ctx->driver_context = init_params->driver;
-+	dc_init_data.ctx->cgs_device = init_params->cgs_device;
-+	dc_init_data.ctx->dc = dc;
-+
-+	/* Create logger */
-+	logger = dal_logger_create(dc_init_data.ctx);
-+
-+	if (!logger) {
-+		/* can *not* call logger. call base driver 'print error' */
-+		dal_error("%s: failed to create Logger!\n", __func__);
-+		goto logger_fail;
-+	}
-+	dc_init_data.ctx->logger = logger;
-+
-+	/* Create adapter service */
-+	dc_init_data.adapter_srv = create_as(&dc_init_data, init_params);
-+
-+	if (!dc_init_data.adapter_srv) {
-+		dal_error("%s: create_as() failed!\n", __func__);
-+		goto as_fail;
-+	}
-+
-+	/* Initialize HW controlled by Adapter Service */
-+	if (false == dal_adapter_service_initialize_hw_data(
-+			dc_init_data.adapter_srv)) {
-+		dal_error("%s: dal_adapter_service_initialize_hw_data()"\
-+				"  failed!\n", __func__);
-+		/* Note that AS exist, so have to destroy it.*/
-+		goto as_fail;
-+	}
-+
-+	dc->ctx = dc_init_data.ctx;
-+
-+	/* Create hardware sequencer */
-+	if (!dc_construct_hw_sequencer(dc_init_data.adapter_srv, dc))
-+		goto hwss_fail;
-+
-+
-+	/* TODO: create all the sub-objects of DC. */
-+	if (false == create_links(dc, &dc_init_data))
-+		goto create_links_fail;
-+
-+	if (!dc->hwss.construct_resource_pool(
-+			dc_init_data.adapter_srv,
-+			dc,
-+			&dc->res_pool))
-+		goto construct_resource_fail;
-+
-+
-+	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
-+
-+	bw_calcs_data_update_from_pplib(dc);
-+
-+	return true;
-+
-+	/**** error handling here ****/
-+construct_resource_fail:
-+create_links_fail:
-+as_fail:
-+	dal_logger_destroy(&dc_init_data.ctx->logger);
-+logger_fail:
-+hwss_fail:
-+	dc_service_free(&ctx, dc_init_data.ctx);
-+ctx_fail:
-+	return false;
-+}
-+
-+static void destruct(struct dc *dc)
-+{
-+	destroy_links(dc);
-+	dc_service_free(dc->ctx, dc->links);
-+	dc->hwss.destruct_resource_pool(&dc->res_pool);
-+	dal_logger_destroy(&dc->ctx->logger);
-+	dc_service_free(dc->ctx, dc->ctx);
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+struct dc *dc_create(const struct dal_init_data *init_params)
-+ {
-+	struct dc_context ctx = {
-+		.driver_context = init_params->driver,
-+		.cgs_device = init_params->cgs_device
-+	};
-+	struct dc *dc = dc_service_alloc(&ctx, sizeof(*dc));
-+
-+	if (NULL == dc)
-+		goto alloc_fail;
-+
-+	ctx.dc = dc;
-+	if (false == construct(dc, init_params))
-+		goto construct_fail;
-+
-+	/*TODO: separate HW and SW initialization*/
-+	init_hw(dc);
-+
-+	return dc;
-+
-+construct_fail:
-+	dc_service_free(&ctx, dc);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+void dc_destroy(struct dc **dc)
-+{
-+	destruct(*dc);
-+	dc_service_free((*dc)->ctx, *dc);
-+	*dc = NULL;
-+}
-+
-+bool dc_validate_resources(
-+		const struct dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	struct validate_context *context;
-+
-+	context = dc_service_alloc(dc->ctx, sizeof(struct validate_context));
-+	if(context == NULL)
-+		goto context_alloc_fail;
-+
-+	result = dc->hwss.validate_with_context(dc, set, set_count, context);
-+
-+	dc_service_free(dc->ctx, context);
-+context_alloc_fail:
-+
-+	return (result == DC_OK);
-+
-+}
-+
-+static void program_timing_sync(
-+		struct dc_context *dc_ctx,
-+		struct validate_context *ctx)
-+{
-+	uint8_t i;
-+	uint8_t j;
-+	uint8_t group_size = 0;
-+	uint8_t tg_count = ctx->res_ctx.pool.controller_count;
-+	struct timing_generator *tg_set[3];
-+
-+	for (i = 0; i < tg_count; i++) {
-+		if (!ctx->res_ctx.controller_ctx[i].stream)
-+			continue;
-+
-+		tg_set[0] = ctx->res_ctx.pool.timing_generators[i];
-+		group_size = 1;
-+
-+		/* Add tg to the set, search rest of the tg's for ones with
-+		 * same timing, add all tgs with same timing to the group
-+		 */
-+		for (j = i + 1; j < tg_count; j++) {
-+			if (!ctx->res_ctx.controller_ctx[j].stream)
-+				continue;
-+
-+			if (is_same_timing(
-+				&ctx->res_ctx.controller_ctx[j].stream->public
-+								.timing,
-+				&ctx->res_ctx.controller_ctx[i].stream->public
-+								.timing)) {
-+				tg_set[group_size] =
-+					ctx->res_ctx.pool.timing_generators[j];
-+				group_size++;
-+			}
-+		}
-+
-+		/* Right now we limit to one timing sync group so if one is
-+		 * found we break. A group has to be more than one tg.*/
-+		if (group_size > 1)
-+			break;
-+	}
-+
-+	if(group_size > 1) {
-+		dc_ctx->dc->hwss.enable_timing_synchronization(dc_ctx, group_size, tg_set);
-+	}
-+}
-+
-+static bool targets_changed(
-+		struct dc *dc,
-+		struct dc_target *targets[],
-+		uint8_t target_count)
-+{
-+	uint8_t i;
-+
-+	if (target_count != dc->current_context.target_count)
-+		return true;
-+
-+	for (i = 0; i < dc->current_context.target_count; i++) {
-+		if (&dc->current_context.targets[i]->public != targets[i])
-+			return true;
-+	}
-+
-+	return false;
-+}
-+
-+static void pplib_post_set_mode(
-+	struct dc *dc,
-+	const struct validate_context *context)
-+{
-+	struct dc_pp_display_configuration pp_display_cfg = { 0 };
-+
-+	pp_display_cfg.nb_pstate_switch_disable =
-+			context->bw_results.nbp_state_change_enable == false;
-+
-+	pp_display_cfg.cpu_cc6_disable =
-+			context->bw_results.cpuc_state_change_enable == false;
-+
-+	pp_display_cfg.cpu_pstate_disable =
-+			context->bw_results.cpup_state_change_enable == false;
-+
-+	/* TODO: get cpu_pstate_separation_time from BW Calcs. */
-+	pp_display_cfg.cpu_pstate_separation_time = 0;
-+
-+	dc_service_pp_post_dce_clock_change(dc->ctx, &pp_display_cfg);
-+}
-+
-+bool dc_commit_targets(
-+	struct dc *dc,
-+	struct dc_target *targets[],
-+	uint8_t target_count)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	struct validate_context *context;
-+	struct dc_validation_set set[4];
-+	uint8_t i;
-+
-+	if (false == targets_changed(dc, targets, target_count))
-+		return DC_OK;
-+
-+	dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_INTERFACE_TRACE,
-+				LOG_MINOR_COMPONENT_DC,
-+				"%s: %d targets",
-+				__func__,
-+				target_count);
-+
-+	for (i = 0; i < target_count; i++) {
-+		struct dc_target *target = targets[i];
-+
-+		dc_target_log(target,
-+				dc->ctx->logger,
-+				LOG_MAJOR_INTERFACE_TRACE,
-+				LOG_MINOR_COMPONENT_DC);
-+
-+		set[i].target = targets[i];
-+		set[i].surface_count = 0;
-+
-+	}
-+
-+	context = dc_service_alloc(dc->ctx, sizeof(struct validate_context));
-+	if (context == NULL)
-+		goto context_alloc_fail;
-+
-+	result = dc->hwss.validate_with_context(dc, set, target_count, context);
-+	if (result != DC_OK){
-+		BREAK_TO_DEBUGGER();
-+		goto fail;
-+	}
-+
-+	if (!dal_adapter_service_is_in_accelerated_mode(
-+						dc->res_pool.adapter_srv)) {
-+		dc->hwss.enable_accelerated_mode(context);
-+	}
-+
-+	for (i = 0; i < dc->current_context.target_count; i++) {
-+		/*TODO: optimize this to happen only when necessary*/
-+		dc_target_disable_memory_requests(
-+				&dc->current_context.targets[i]->public);
-+	}
-+
-+	if (result == DC_OK) {
-+		dc->hwss.reset_hw_ctx(dc, context, target_count);
-+
-+		if (context->target_count > 0)
-+			result = dc->hwss.apply_ctx_to_hw(dc, context);
-+	}
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct dc_target *dc_target = &context->targets[i]->public;
-+		if (context->targets[i]->status.surface_count > 0)
-+			dc_target_enable_memory_requests(dc_target);
-+	}
-+
-+	/* Release old targets */
-+	for (i = 0; i < dc->current_context.target_count; i++) {
-+		dc_target_release(
-+				&dc->current_context.targets[i]->public);
-+		dc->current_context.targets[i] = NULL;
-+	}
-+	/* Retain new targets*/
-+	for (i = 0; i < context->target_count; i++) {
-+		dc_target_retain(&context->targets[i]->public);
-+	}
-+
-+	dc->current_context = *context;
-+
-+	program_timing_sync(dc->ctx, context);
-+
-+	pplib_post_set_mode(dc, context);
-+
-+	/* TODO: disable unused plls*/
-+fail:
-+	dc_service_free(dc->ctx, context);
-+
-+context_alloc_fail:
-+	return (result == DC_OK);
-+}
-+
-+uint8_t dc_get_current_target_count(const struct dc *dc)
-+{
-+	return dc->current_context.target_count;
-+}
-+
-+struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i)
-+{
-+	if (i < dc->current_context.target_count)
-+		return &dc->current_context.targets[i]->public;
-+	return NULL;
-+}
-+
-+const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
-+{
-+	return &dc->links[link_index]->public;
-+}
-+
-+const struct graphics_object_id dc_get_link_id_at_index(
-+	struct dc *dc, uint32_t link_index)
-+{
-+	return dc->links[link_index]->link_id;
-+}
-+
-+const struct ddc_service *dc_get_ddc_at_index(
-+	struct dc *dc, uint32_t link_index)
-+{
-+	return dc->links[link_index]->ddc;
-+}
-+
-+const enum dc_irq_source dc_get_hpd_irq_source_at_index(
-+	struct dc *dc, uint32_t link_index)
-+{
-+	return dc->links[link_index]->public.irq_source_hpd;
-+}
-+
-+const struct audio **dc_get_audios(struct dc *dc)
-+{
-+	return (const struct audio **)dc->res_pool.audios;
-+}
-+
-+void dc_get_caps(const struct dc *dc, struct dc_caps *caps)
-+{
-+    caps->max_targets = dal_min(dc->res_pool.controller_count, dc->link_count);
-+    caps->max_links = dc->link_count;
-+    caps->max_audios = dc->res_pool.audio_count;
-+}
-+
-+void dc_flip_surface_addrs(struct dc* dc,
-+		const struct dc_surface *const surfaces[],
-+		struct dc_flip_addrs flip_addrs[],
-+		uint32_t count)
-+{
-+	uint8_t i;
-+	for (i = 0; i < count; i++) {
-+		struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
-+		/*
-+		 * TODO figure out a good way to keep track of address. Until
-+		 * then we'll have to awkwardly bypass the "const" surface.
-+		 */
-+		surface->public.address = flip_addrs[i].address;
-+		dc->hwss.update_plane_address(
-+			surface,
-+			DC_TARGET_TO_CORE(surface->status.dc_target));
-+	}
-+}
-+
-+enum dc_irq_source dc_interrupt_to_irq_source(
-+		struct dc *dc,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	return dal_irq_service_to_irq_source(dc->res_pool.irqs, src_id, ext_id);
-+}
-+
-+
-+void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
-+{
-+	dal_irq_service_set(dc->res_pool.irqs, src, enable);
-+}
-+
-+void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
-+{
-+	dal_irq_service_ack(dc->res_pool.irqs, src);
-+}
-+
-+const struct dc_target *dc_get_target_on_irq_source(
-+		const struct dc *dc,
-+		enum dc_irq_source src)
-+{
-+	uint8_t i, j;
-+	uint8_t crtc_idx;
-+
-+	switch (src) {
-+	case DC_IRQ_SOURCE_VUPDATE1:
-+	case DC_IRQ_SOURCE_VUPDATE2:
-+	case DC_IRQ_SOURCE_VUPDATE3:
-+	case DC_IRQ_SOURCE_VUPDATE4:
-+	case DC_IRQ_SOURCE_VUPDATE5:
-+	case DC_IRQ_SOURCE_VUPDATE6:
-+		crtc_idx = src - DC_IRQ_SOURCE_VUPDATE1;
-+		break;
-+	case DC_IRQ_SOURCE_PFLIP1:
-+	case DC_IRQ_SOURCE_PFLIP2:
-+	case DC_IRQ_SOURCE_PFLIP3:
-+	case DC_IRQ_SOURCE_PFLIP4:
-+	case DC_IRQ_SOURCE_PFLIP5:
-+	case DC_IRQ_SOURCE_PFLIP6:
-+	case DC_IRQ_SOURCE_PFLIP_UNDERLAY0:
-+		crtc_idx = src - DC_IRQ_SOURCE_PFLIP1;
-+		break;
-+	default:
-+		dal_error("%s: invalid irq source: %d\n!",__func__, src);
-+		goto fail;
-+	}
-+
-+	for (i = 0; i < dc->current_context.target_count; i++) {
-+		const struct core_target *target =
-+				dc->current_context.targets[i];
-+
-+		if (NULL == target) {
-+			dal_error("%s: 'dc_target' is NULL for irq source: %d\n!",
-+					__func__, src);
-+			continue;
-+		}
-+
-+		for (j = 0; j < target->stream_count; j++) {
-+			const uint8_t controller_idx =
-+					target->streams[j]->controller_idx;
-+			if (controller_idx == crtc_idx)
-+				return &target->public;
-+		}
-+	}
-+fail:
-+	return NULL;
-+}
-+
-+void dc_set_power_state(
-+	struct dc *dc,
-+	enum dc_acpi_cm_power_state power_state,
-+	enum dc_video_power_state video_power_state)
-+{
-+	dc->previous_power_state = dc->current_power_state;
-+	dc->current_power_state = video_power_state;
-+
-+	switch (power_state) {
-+	case DC_ACPI_CM_POWER_STATE_D0:
-+		init_hw(dc);
-+		break;
-+	default:
-+		/* NULL means "reset/release all DC targets" */
-+		dc_commit_targets(dc, NULL, 0);
-+
-+		dc->hwss.power_down(&dc->current_context);
-+		break;
-+	}
-+
-+}
-+
-+void dc_resume(const struct dc *dc)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < dc->link_count; i++)
-+		core_link_resume(dc->links[i]);
-+}
-+
-+void dc_print_sync_report(
-+	const struct dc *dc)
-+{
-+	uint32_t i;
-+	const struct core_target *core_target;
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct dc_target_sync_report *target_sync_report;
-+	struct dc_sync_report sync_report = { 0 };
-+
-+	if (dc->current_context.target_count > MAX_TARGET_NUM) {
-+		DC_ERROR("Target count: %d > %d!\n",
-+			dc->current_context.target_count,
-+			MAX_TARGET_NUM);
-+		return;
-+	}
-+
-+	sync_report.targets_num = dc->current_context.target_count;
-+
-+	/* Step 1: get data for sync validation */
-+	for (i = 0; i < dc->current_context.target_count; i++) {
-+
-+		core_target = dc->current_context.targets[i];
-+		target_sync_report = &sync_report.trg_reports[i];
-+
-+		dc->hwss.get_crtc_positions(
-+			core_target->streams[0]->tg,
-+			&target_sync_report->h_count,
-+			&target_sync_report->v_count);
-+
-+		DC_SYNC_INFO("GSL:target[%d]: h: %d\t v: %d\n",
-+				i,
-+				target_sync_report->h_count,
-+				target_sync_report->v_count);
-+	}
-+
-+	/* Step 2: validate that display pipes are synchronized (based on
-+	 * data from Step 1). */
-+}
-+
-+bool dc_read_dpcd(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size)
-+{
-+	struct core_link *link =
-+			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
-+	enum dc_status r = core_link_read_dpcd(link, address, data, size);
-+
-+	return r == DC_OK;
-+}
-+
-+bool dc_write_dpcd(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size)
-+{
-+	struct core_link *link =
-+			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
-+	enum dc_status r = core_link_write_dpcd(link, address, data, size);
-+
-+	return r == DC_OK;
-+}
-+
-+bool dc_link_add_sink(
-+		struct dc_link *link,
-+		struct dc_sink *sink)
-+{
-+	if (link->sink_count >= MAX_SINKS_PER_LINK) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	link->sink[link->sink_count] = sink;
-+	link->sink_count++;
-+
-+	return true;
-+}
-+
-+
-+void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink)
-+{
-+	int i;
-+
-+	if (!link->sink_count) {
-+	   BREAK_TO_DEBUGGER();
-+	   return;
-+	}
-+
-+	for (i = 0; i < link->sink_count; i++) {
-+		   if (link->sink[i] == sink) {
-+			   dc_sink_release(sink);
-+			   link->sink[i] = NULL;
-+			   link->sink_count--;
-+			   return;
-+		   }
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-new file mode 100644
-index 0000000..b9e6ffd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+#include "core_types.h"
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/dce110_hw_sequencer.h"
-+#endif
-+
-+bool dc_construct_hw_sequencer(
-+				struct adapter_service *adapter_serv,
-+				struct dc *dc)
-+{
-+	enum dce_version dce_ver = dal_adapter_service_get_dce_version(adapter_serv);
-+
-+	switch (dce_ver)
-+	{
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		return dce110_hw_sequencer_construct(dc);
-+#endif
-+	default:
-+		break;
-+	}
-+
-+	return false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-new file mode 100644
-index 0000000..a0a131e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -0,0 +1,1081 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+#include "dc_helpers.h"
-+#include "dc.h"
-+#include "core_dc.h"
-+#include "adapter_service_interface.h"
-+#include "grph_object_id.h"
-+#include "connector_interface.h"
-+#include "gpio_service_interface.h"
-+#include "ddc_service_interface.h"
-+#include "core_status.h"
-+#include "dc_link_dp.h"
-+#include "link_hwss.h"
-+#include "stream_encoder_types.h"
-+#include "link_encoder_types.h"
-+#include "hw_sequencer.h"
-+
-+
-+#define LINK_INFO(...) \
-+	dal_logger_write(dc_ctx->logger, \
-+		LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_HOTPLUG, \
-+		__VA_ARGS__)
-+
-+/*******************************************************************************
-+ * Private structures
-+ ******************************************************************************/
-+
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+static void destruct(struct core_link *link)
-+{
-+	if (link->connector)
-+		dal_connector_destroy(&link->connector);
-+
-+	if (link->ddc)
-+		dal_ddc_service_destroy(&link->ddc);
-+
-+	if(link->link_enc)
-+		link->ctx->dc->hwss.encoder_destroy(&link->link_enc);
-+}
-+
-+static bool detect_sink(struct core_link *link)
-+{
-+	uint32_t is_hpd_high = 0;
-+	struct irq *hpd_pin;
-+
-+	/* todo: may need to lock gpio access */
-+	hpd_pin = dal_adapter_service_obtain_hpd_irq(
-+			link->adapter_srv,
-+			link->link_id);
-+	if (hpd_pin == NULL)
-+		goto hpd_gpio_failure;
-+
-+	dal_irq_open(hpd_pin);
-+	dal_irq_get_value(hpd_pin, &is_hpd_high);
-+	dal_irq_close(hpd_pin);
-+	dal_adapter_service_release_irq(
-+		link->adapter_srv,
-+		hpd_pin);
-+
-+	if (is_hpd_high) {
-+		link->public.type = dc_connection_single;
-+		/* TODO: need to do the actual detection */
-+	} else {
-+		link->public.type = dc_connection_none;
-+	}
-+
-+	return true;
-+
-+hpd_gpio_failure:
-+	return false;
-+}
-+
-+
-+enum ddc_transaction_type get_ddc_transaction_type(
-+		enum signal_type sink_signal)
-+{
-+	enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
-+
-+
-+	switch (sink_signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_RGB:
-+		transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* MST does not use I2COverAux, but there is the
-+		 * SPECIAL use case for "immediate dwnstrm device
-+		 * access" (EPR#370830). */
-+		transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+
-+	return transaction_type;
-+}
-+
-+static enum signal_type get_basic_signal_type(
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id downstream)
-+{
-+	if (downstream.type == OBJECT_TYPE_CONNECTOR) {
-+		switch (downstream.id) {
-+		case CONNECTOR_ID_SINGLE_LINK_DVII:
-+			switch (encoder.id) {
-+			case ENCODER_ID_INTERNAL_DAC1:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+			case ENCODER_ID_INTERNAL_DAC2:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+				return SIGNAL_TYPE_RGB;
-+			default:
-+				return SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			}
-+		break;
-+		case CONNECTOR_ID_DUAL_LINK_DVII:
-+		{
-+			switch (encoder.id) {
-+			case ENCODER_ID_INTERNAL_DAC1:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+			case ENCODER_ID_INTERNAL_DAC2:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+				return SIGNAL_TYPE_RGB;
-+			default:
-+				return SIGNAL_TYPE_DVI_DUAL_LINK;
-+			}
-+		}
-+		break;
-+		case CONNECTOR_ID_SINGLE_LINK_DVID:
-+			return SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		case CONNECTOR_ID_DUAL_LINK_DVID:
-+			return SIGNAL_TYPE_DVI_DUAL_LINK;
-+		case CONNECTOR_ID_VGA:
-+			return SIGNAL_TYPE_RGB;
-+		case CONNECTOR_ID_HDMI_TYPE_A:
-+			return SIGNAL_TYPE_HDMI_TYPE_A;
-+		case CONNECTOR_ID_LVDS:
-+			return SIGNAL_TYPE_LVDS;
-+		case CONNECTOR_ID_DISPLAY_PORT:
-+			return SIGNAL_TYPE_DISPLAY_PORT;
-+		case CONNECTOR_ID_EDP:
-+			return SIGNAL_TYPE_EDP;
-+		default:
-+			return SIGNAL_TYPE_NONE;
-+		}
-+	} else if (downstream.type == OBJECT_TYPE_ENCODER) {
-+		switch (downstream.id) {
-+		case ENCODER_ID_EXTERNAL_NUTMEG:
-+		case ENCODER_ID_EXTERNAL_TRAVIS:
-+			return SIGNAL_TYPE_DISPLAY_PORT;
-+		default:
-+			return SIGNAL_TYPE_NONE;
-+		}
-+	}
-+
-+	return SIGNAL_TYPE_NONE;
-+}
-+
-+/*
-+ * @brief
-+ * Check whether there is a dongle on DP connector
-+ */
-+static bool is_dp_sink_present(struct core_link *link)
-+{
-+	enum gpio_result gpio_result;
-+	uint32_t clock_pin = 0;
-+	uint32_t data_pin = 0;
-+
-+	struct ddc *ddc;
-+
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(link->link_id);
-+
-+	bool present =
-+		((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
-+		(connector_id == CONNECTOR_ID_EDP));
-+
-+	ddc = dal_adapter_service_obtain_ddc(link->adapter_srv, link->link_id);
-+
-+	if (!ddc)
-+		return present;
-+
-+	/* Open GPIO and set it to I2C mode */
-+	/* Note: this GpioMode_Input will be converted
-+	 * to GpioConfigType_I2cAuxDualMode in GPIO component,
-+	 * which indicates we need additional delay */
-+
-+	if (GPIO_RESULT_OK != dal_ddc_open(
-+		ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
-+		dal_adapter_service_release_ddc(link->adapter_srv, ddc);
-+
-+		return present;
-+	}
-+
-+	/* Read GPIO: DP sink is present if both clock and data pins are zero */
-+	/* [anaumov] in DAL2, there was no check for GPIO failure */
-+
-+	gpio_result = dal_ddc_get_clock(ddc, &clock_pin);
-+	ASSERT(gpio_result == GPIO_RESULT_OK);
-+
-+	if (gpio_result == GPIO_RESULT_OK)
-+		if (link->link_enc->features.flags.bits.
-+						DP_SINK_DETECT_POLL_DATA_PIN)
-+			gpio_result = dal_ddc_get_data(ddc, &data_pin);
-+
-+	present = (gpio_result == GPIO_RESULT_OK) && !(clock_pin || data_pin);
-+
-+	dal_ddc_close(ddc);
-+
-+	dal_adapter_service_release_ddc(link->adapter_srv, ddc);
-+
-+	return present;
-+}
-+
-+/*
-+ * @brief
-+ * Detect output sink type
-+ */
-+static enum signal_type link_detect_sink(struct core_link *link)
-+{
-+	enum signal_type result = get_basic_signal_type(
-+		link->link_enc->id, link->link_id);
-+
-+	/* Internal digital encoder will detect only dongles
-+	 * that require digital signal */
-+
-+	/* Detection mechanism is different
-+	 * for different native connectors.
-+	 * LVDS connector supports only LVDS signal;
-+	 * PCIE is a bus slot, the actual connector needs to be detected first;
-+	 * eDP connector supports only eDP signal;
-+	 * HDMI should check straps for audio */
-+
-+	/* PCIE detects the actual connector on add-on board */
-+
-+	if (link->link_id.id == CONNECTOR_ID_PCIE) {
-+		/* ZAZTODO implement PCIE add-on card detection */
-+	}
-+
-+	switch (link->link_id.id) {
-+	case CONNECTOR_ID_HDMI_TYPE_A: {
-+		/* check audio support:
-+		 * if native HDMI is not supported, switch to DVI */
-+		union audio_support audio_support =
-+			dal_adapter_service_get_audio_support(
-+				link->adapter_srv);
-+
-+		if (!audio_support.bits.HDMI_AUDIO_NATIVE)
-+			if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
-+				result = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	}
-+	break;
-+	case CONNECTOR_ID_DISPLAY_PORT: {
-+
-+		/* Check whether DP signal detected: if not -
-+		 * we assume signal is DVI; it could be corrected
-+		 * to HDMI after dongle detection */
-+		if (!is_dp_sink_present(link))
-+			result = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	}
-+	break;
-+	default:
-+	break;
-+	}
-+
-+	return result;
-+}
-+
-+static enum signal_type decide_signal_from_strap_and_dongle_type(
-+		enum display_dongle_type dongle_type,
-+		union audio_support *audio_support)
-+{
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+
-+	switch (dongle_type) {
-+	case DISPLAY_DONGLE_DP_HDMI_DONGLE:
-+		if (audio_support->bits.HDMI_AUDIO_ON_DONGLE)
-+			signal =  SIGNAL_TYPE_HDMI_TYPE_A;
-+		else
-+			signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	case DISPLAY_DONGLE_DP_DVI_DONGLE:
-+		signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
-+		if (audio_support->bits.HDMI_AUDIO_NATIVE)
-+			signal =  SIGNAL_TYPE_HDMI_TYPE_A;
-+		else
-+			signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	default:
-+		signal = SIGNAL_TYPE_NONE;
-+		break;
-+	}
-+
-+	return signal;
-+}
-+
-+static enum signal_type dp_passive_dongle_detection(
-+		struct ddc_service *ddc,
-+		struct display_sink_capability *sink_cap,
-+		union audio_support *audio_support)
-+{
-+	/* TODO:These 2 functions should be protected for upstreaming purposes
-+	 * in case hackers want to save 10 cents hdmi license fee
-+	 */
-+	dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+						ddc, sink_cap);
-+	return decide_signal_from_strap_and_dongle_type(
-+			sink_cap->dongle_type,
-+			audio_support);
-+}
-+
-+static bool is_dp_active_dongle(enum display_dongle_type dongle_type)
-+{
-+	return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
-+		dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
-+		dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
-+}
-+
-+/* TODO: To beretired because this call is wrong with
-+ * pluging in of active-dongle without display*/
-+static void link_unplug(struct core_link *link)
-+{
-+	int i;
-+
-+	for (i = 0; i < link->public.sink_count; i++)
-+		dc_link_remove_sink(&link->public, link->public.sink[i]);
-+}
-+
-+static enum dc_edid_status read_edid(struct core_link *link)
-+{
-+	uint32_t edid_retry = 3;
-+	enum dc_edid_status edid_status;
-+	const struct dc_sink *dc_sink = link->public.sink[0];
-+	struct core_sink *sink = DC_SINK_TO_CORE(dc_sink);
-+
-+	if (link->public.sink[0]->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		dal_logger_write(link->ctx->logger,
-+							LOG_MAJOR_WARNING,
-+							LOG_MINOR_DETECTION_EDID_PARSER,
-+							"MST EDID read is not done here!\n");
-+		return EDID_BAD_INPUT;
-+	}
-+
-+	/* some dongles read edid incorrectly the first time,
-+	 * do check sum and retry to make sure read correct edid.
-+	 */
-+	do {
-+		sink->public.dc_edid.length =
-+				dal_ddc_service_edid_query(link->ddc);
-+
-+		if (0 == sink->public.dc_edid.length)
-+			return EDID_NO_RESPONSE;
-+
-+		dal_ddc_service_get_edid_buf(link->ddc,
-+				sink->public.dc_edid.raw_edid);
-+		edid_status = dc_helpers_parse_edid_caps(
-+				link->ctx,
-+				&sink->public.dc_edid,
-+				&sink->public.edid_caps);
-+		--edid_retry;
-+		if (edid_status == EDID_BAD_CHECKSUM)
-+			dal_logger_write(link->ctx->logger,
-+					LOG_MAJOR_WARNING,
-+					LOG_MINOR_DETECTION_EDID_PARSER,
-+					"Bad EDID checksum, retry remain: %d\n",
-+					edid_retry);
-+	} while (edid_status == EDID_BAD_CHECKSUM && edid_retry > 0);
-+
-+	return edid_status;
-+}
-+
-+void dc_link_detect(const struct dc_link *dc_link)
-+{
-+	struct core_link *link = DC_LINK_TO_LINK(dc_link);
-+	struct sink_init_data sink_init_data = { 0 };
-+	enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
-+	struct display_sink_capability sink_caps = { 0 };
-+	uint8_t i;
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+	bool converter_disable_audio = false;
-+	union audio_support audio_support =
-+		dal_adapter_service_get_audio_support(
-+			link->adapter_srv);
-+	enum dc_edid_status edid_status;
-+	struct dc_context *dc_ctx = link->ctx;
-+	struct dc_sink *dc_sink;
-+	struct core_sink *sink = NULL;
-+
-+	if (false == detect_sink(link)) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (link->public.type != dc_connection_none) {
-+		/* From Disconnected-to-Connected. */
-+		switch (link->public.connector_signal) {
-+		case SIGNAL_TYPE_HDMI_TYPE_A: {
-+			transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			if (audio_support.bits.HDMI_AUDIO_NATIVE)
-+				signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+			else
-+				signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_DVI_SINGLE_LINK: {
-+			transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_DVI_DUAL_LINK: {
-+			transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_EDP: {
-+			detect_dp_sink_caps(link);
-+			transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+			signal = SIGNAL_TYPE_EDP;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_DISPLAY_PORT: {
-+			signal = link_detect_sink(link);
-+			transaction_type = get_ddc_transaction_type(
-+					signal);
-+
-+			if (transaction_type ==
-+				DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
-+				signal =
-+					SIGNAL_TYPE_DISPLAY_PORT;
-+				detect_dp_sink_caps(link);
-+
-+				/* DP active dongles */
-+				if (is_dp_active_dongle(
-+					link->dpcd_caps.dongle_type)) {
-+					if (!link->dpcd_caps.
-+						sink_count.bits.SINK_COUNT) {
-+						link->public.type =
-+							dc_connection_none;
-+						/* active dongle unplug
-+						 * processing for short irq
-+						 */
-+						link_unplug(link);
-+						return;
-+					}
-+
-+					if (link->dpcd_caps.dongle_type !=
-+					DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
-+						converter_disable_audio = true;
-+					}
-+				}
-+				if (is_mst_supported(link)) {
-+					signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-+
-+					/*
-+					 * This call will initiate MST topology
-+					 * discovery. Which will detect
-+					 * MST ports and add new DRM connector
-+					 * DRM framework. Then read EDID via
-+					 * remote i2c over aux.In the end, will
-+					 * notify DRM detect result and save
-+					 * EDID into DRM framework.
-+					 *
-+					 * .detect is called by .fill_modes.
-+					 * .fill_modes is called by user mode
-+					 *  ioctl DRM_IOCTL_MODE_GETCONNECTOR.
-+					 *
-+					 * .get_modes is called by .fill_modes.
-+					 *
-+					 * call .get_modes, AMDGPU DM
-+					 * implementation will create new
-+					 * dc_sink and add to dc_link.
-+					 * For long HPD plug in/out, MST has its
-+					 * own handle.
-+					 *
-+					 * Therefore, just after dc_create,
-+					 * link->sink is not created for MST
-+					 * until user mode app calls
-+					 * DRM_IOCTL_MODE_GETCONNECTOR.
-+					 *
-+					 * Need check ->sink usages in case
-+					 * ->sink = NULL
-+					 * TODO: s3 resume check*/
-+
-+					if (dc_helpers_dp_mst_start_top_mgr(link->ctx, &link->public)) {
-+						return;
-+					} else {
-+						/* MST not supported */
-+						signal = SIGNAL_TYPE_DISPLAY_PORT;
-+					}
-+				}
-+			}
-+			else {
-+				/* DP passive dongles */
-+				signal = dp_passive_dongle_detection(link->ddc,
-+						&sink_caps,
-+						&audio_support);
-+			}
-+			break;
-+		}
-+
-+		default:
-+			DC_ERROR("Invalid connector type! signal:%d\n",
-+				link->public.connector_signal);
-+			return;
-+		} /* switch() */
-+
-+		if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
-+			link->dpcd_sink_count = link->dpcd_caps.sink_count.
-+					bits.SINK_COUNT;
-+			else
-+				link->dpcd_sink_count = 1;
-+
-+
-+		dal_ddc_service_set_transaction_type(
-+						link->ddc,
-+						transaction_type);
-+
-+		sink_init_data.link = &link->public;
-+		sink_init_data.sink_signal = signal;
-+		sink_init_data.dongle_max_pix_clk =
-+			sink_caps.max_hdmi_pixel_clock;
-+		sink_init_data.converter_disable_audio =
-+				converter_disable_audio;
-+
-+		dc_sink = sink_create(&sink_init_data);
-+		if (!dc_sink) {
-+			DC_ERROR("Failed to create sink!\n");
-+			return;
-+		}
-+
-+		sink = DC_SINK_TO_CORE(dc_sink);
-+
-+		/*AG TODO handle failure */
-+		/*Only non MST case here */
-+		if (!dc_link_add_sink(&link->public, &sink->public))
-+				BREAK_TO_DEBUGGER();
-+
-+		edid_status = read_edid(link);
-+
-+		switch (edid_status) {
-+		case EDID_BAD_CHECKSUM:
-+			dal_logger_write(link->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_DETECTION_EDID_PARSER,
-+				"EDID checksum invalid.\n");
-+			break;
-+		case EDID_NO_RESPONSE:
-+			dal_logger_write(link->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_DETECTION_EDID_PARSER,
-+				"No EDID read.\n");
-+			return;
-+
-+		default:
-+			break;
-+		}
-+
-+		dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_DETECTION,
-+			LOG_MINOR_DETECTION_EDID_PARSER,
-+			"%s: "
-+			"manufacturer_id = %X, "
-+			"product_id = %X, "
-+			"serial_number = %X, "
-+			"manufacture_week = %d, "
-+			"manufacture_year = %d, "
-+			"display_name = %s, "
-+			"speaker_flag = %d, "
-+			"audio_mode_count = %d\n",
-+			__func__,
-+			sink->public.edid_caps.manufacturer_id,
-+			sink->public.edid_caps.product_id,
-+			sink->public.edid_caps.serial_number,
-+			sink->public.edid_caps.manufacture_week,
-+			sink->public.edid_caps.manufacture_year,
-+			sink->public.edid_caps.display_name,
-+			sink->public.edid_caps.speaker_flags,
-+			sink->public.edid_caps.audio_mode_count);
-+
-+		for (i = 0; i < sink->public.edid_caps.audio_mode_count; i++) {
-+			dal_logger_write(link->ctx->logger,
-+				LOG_MAJOR_DETECTION,
-+				LOG_MINOR_DETECTION_EDID_PARSER,
-+				"%s: mode number = %d, "
-+				"format_code = %d, "
-+				"channel_count = %d, "
-+				"sample_rate = %d, "
-+				"sample_size = %d\n",
-+				__func__,
-+				i,
-+				sink->public.edid_caps.audio_modes[i].format_code,
-+				sink->public.edid_caps.audio_modes[i].channel_count,
-+				sink->public.edid_caps.audio_modes[i].sample_rate,
-+				sink->public.edid_caps.audio_modes[i].sample_size);
-+		}
-+
-+	} else {
-+		/* From Connected-to-Disconnected. */
-+		switch (link->public.connector_signal) {
-+		case SIGNAL_TYPE_DISPLAY_PORT:
-+			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
-+			break;
-+		default:
-+			break;
-+		}
-+		link_unplug(link);
-+	}
-+
-+	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
-+		link->link_index, &sink->public,
-+		(signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected"));
-+
-+	/* TODO: */
-+
-+	return;
-+}
-+
-+static bool construct(
-+	struct core_link *link,
-+	const struct link_init_data *init_params)
-+{
-+	struct irq *hpd_gpio = NULL;
-+	struct ddc_service_init_data ddc_service_init_data = { 0 };
-+	struct dc_context *dc_ctx = init_params->ctx;
-+	struct encoder_init_data enc_init_data = { 0 };
-+	struct connector_feature_support cfs = { 0 };
-+
-+	link->dc = init_params->dc;
-+	link->adapter_srv = init_params->adapter_srv;
-+	link->connector_index = init_params->connector_index;
-+	link->ctx = dc_ctx;
-+	link->link_index = init_params->link_index;
-+
-+	link->link_id = dal_adapter_service_get_connector_obj_id(
-+			init_params->adapter_srv,
-+			init_params->connector_index);
-+
-+	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
-+		dal_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d!\n",
-+				__func__, init_params->connector_index);
-+		goto create_fail;
-+	}
-+
-+	switch (link->link_id.id) {
-+	case CONNECTOR_ID_HDMI_TYPE_A:
-+		link->public.connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+		break;
-+	case CONNECTOR_ID_SINGLE_LINK_DVID:
-+	case CONNECTOR_ID_SINGLE_LINK_DVII:
-+		link->public.connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	case CONNECTOR_ID_DUAL_LINK_DVID:
-+	case CONNECTOR_ID_DUAL_LINK_DVII:
-+		link->public.connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		break;
-+	case CONNECTOR_ID_DISPLAY_PORT:
-+		link->public.connector_signal =	SIGNAL_TYPE_DISPLAY_PORT;
-+		hpd_gpio = dal_adapter_service_obtain_hpd_irq(
-+					init_params->adapter_srv,
-+					link->link_id);
-+
-+		if (hpd_gpio != NULL) {
-+			link->public.irq_source_hpd_rx =
-+					dal_irq_get_rx_source(hpd_gpio);
-+			dal_adapter_service_release_irq(
-+					init_params->adapter_srv, hpd_gpio);
-+		}
-+		break;
-+	case CONNECTOR_ID_EDP:
-+		link->public.connector_signal = SIGNAL_TYPE_EDP;
-+		hpd_gpio = dal_adapter_service_obtain_hpd_irq(
-+					init_params->adapter_srv,
-+					link->link_id);
-+
-+		if (hpd_gpio != NULL) {
-+			link->public.irq_source_hpd_rx =
-+					dal_irq_get_rx_source(hpd_gpio);
-+			dal_adapter_service_release_irq(
-+					init_params->adapter_srv, hpd_gpio);
-+		}
-+		break;
-+	default:
-+		dal_logger_write(dc_ctx->logger,
-+			LOG_MAJOR_WARNING, LOG_MINOR_TM_LINK_SRV,
-+			"Unsupported Connector type:%d!\n", link->link_id.id);
-+		goto create_fail;
-+	}
-+
-+	/* TODO: #DAL3 Implement id to str function.*/
-+	LINK_INFO("Connector[%d] description:\n",
-+			init_params->connector_index);
-+
-+	link->connector = dal_connector_create(dc_ctx,
-+			init_params->adapter_srv,
-+			link->link_id);
-+	if (NULL == link->connector) {
-+		DC_ERROR("Failed to create connector object!\n");
-+		goto create_fail;
-+	}
-+
-+
-+	hpd_gpio = dal_adapter_service_obtain_hpd_irq(
-+			init_params->adapter_srv,
-+			link->link_id);
-+
-+	if (hpd_gpio != NULL) {
-+		link->public.irq_source_hpd = dal_irq_get_source(hpd_gpio);
-+		dal_adapter_service_release_irq(
-+					init_params->adapter_srv, hpd_gpio);
-+	}
-+
-+	ddc_service_init_data.as = link->adapter_srv;
-+	ddc_service_init_data.ctx = link->ctx;
-+	ddc_service_init_data.id = link->link_id;
-+	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
-+
-+	if (NULL == link->ddc) {
-+		DC_ERROR("Failed to create ddc_service!\n");
-+		goto create_fail;
-+	}
-+
-+	dal_connector_get_features(link->connector, &cfs);
-+
-+	enc_init_data.adapter_service = link->adapter_srv;
-+	enc_init_data.ctx = dc_ctx;
-+	enc_init_data.encoder = dal_adapter_service_get_src_obj(
-+					link->adapter_srv, link->link_id, 0);
-+	enc_init_data.connector = link->link_id;
-+	enc_init_data.channel = cfs.ddc_line;
-+	enc_init_data.hpd_source = cfs.hpd_line;
-+	link->link_enc = dc_ctx->dc->hwss.encoder_create(&enc_init_data);
-+
-+	if( link->link_enc == NULL) {
-+		DC_ERROR("Failed to create link encoder!\n");
-+		goto create_fail;
-+	}
-+
-+	/*
-+	 * TODO check if GPIO programmed correctly
-+	 *
-+	 * If GPIO isn't programmed correctly HPD might not rise or drain
-+	 * fast enough, leading to bounces.
-+	 */
-+#define DELAY_ON_CONNECT_IN_MS 500
-+#define DELAY_ON_DISCONNECT_IN_MS 500
-+
-+	dal_connector_program_hpd_filter(
-+		link->connector,
-+		DELAY_ON_CONNECT_IN_MS,
-+		DELAY_ON_DISCONNECT_IN_MS);
-+
-+	return true;
-+
-+create_fail:
-+	return false;
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+struct core_link *link_create(const struct link_init_data *init_params)
-+{
-+	struct core_link *link =
-+			dc_service_alloc(init_params->ctx, sizeof(*link));
-+	link->ctx = init_params->ctx;
-+
-+	if (NULL == link)
-+		goto alloc_fail;
-+
-+	if (false == construct(link, init_params))
-+		goto construct_fail;
-+
-+	return link;
-+
-+construct_fail:
-+	dc_service_free(init_params->ctx, link);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+void link_destroy(struct core_link **link)
-+{
-+	destruct(*link);
-+	dc_service_free((*link)->ctx, *link);
-+	*link = NULL;
-+}
-+
-+static void dpcd_configure_panel_mode(
-+	struct core_link *link,
-+	enum dp_panel_mode panel_mode)
-+{
-+	union dpcd_edp_config edp_config_set;
-+	bool panel_mode_edp = false;
-+
-+	dc_service_memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
-+
-+	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
-+
-+		switch (panel_mode) {
-+		case DP_PANEL_MODE_EDP:
-+		case DP_PANEL_MODE_SPECIAL:
-+			panel_mode_edp = true;
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+		/*set edp panel mode in receiver*/
-+		core_link_read_dpcd(
-+			link,
-+			DPCD_ADDRESS_EDP_CONFIG_SET,
-+			&edp_config_set.raw,
-+			sizeof(edp_config_set.raw));
-+
-+		if (edp_config_set.bits.PANEL_MODE_EDP
-+			!= panel_mode_edp) {
-+			enum ddc_result result = DDC_RESULT_UNKNOWN;
-+
-+			edp_config_set.bits.PANEL_MODE_EDP =
-+			panel_mode_edp;
-+			result = core_link_write_dpcd(
-+				link,
-+				DPCD_ADDRESS_EDP_CONFIG_SET,
-+				&edp_config_set.raw,
-+				sizeof(edp_config_set.raw));
-+
-+			ASSERT(result == DDC_RESULT_SUCESSFULL);
-+		}
-+	}
-+	dal_logger_write(link->ctx->logger, LOG_MAJOR_DETECTION,
-+			LOG_MINOR_DETECTION_DP_CAPS,
-+			"Connector: %d eDP panel mode supported: %d "
-+			"eDP panel mode enabled: %d \n",
-+			link->connector_index,
-+			link->dpcd_caps.panel_mode_edp,
-+			panel_mode_edp);
-+}
-+
-+static enum dc_status enable_link_dp(struct core_stream *stream)
-+{
-+	enum dc_status status;
-+	bool skip_video_pattern;
-+	struct core_link *link = stream->sink->link;
-+	struct link_settings link_settings = {0};
-+	enum dp_panel_mode panel_mode;
-+
-+	/* get link settings for video mode timing */
-+	decide_link_settings(stream, &link_settings);
-+	status = dp_enable_link_phy(
-+		stream->sink->link,
-+		stream->signal,
-+		stream->stream_enc->id,
-+		&link_settings);
-+
-+	panel_mode = dp_get_panel_mode(link);
-+	dpcd_configure_panel_mode(link, panel_mode);
-+
-+	skip_video_pattern = true;
-+
-+	if (link_settings.link_rate == LINK_RATE_LOW)
-+			skip_video_pattern = false;
-+
-+	if (perform_link_training(link, &link_settings, skip_video_pattern)) {
-+		link->cur_link_settings = link_settings;
-+		status = DC_OK;
-+	}
-+	else
-+		status = DC_ERROR_UNEXPECTED;
-+
-+	return status;
-+}
-+
-+static enum dc_status enable_link_hdmi(struct core_stream *stream)
-+{
-+	struct core_link *link = stream->sink->link;
-+
-+	/* TODO:Need to add missing use cases, reference
-+	 * dal_hw_sequencer_enable_link_base*/
-+	enum dc_status status = DC_OK;
-+
-+	/* enable video output */
-+	/* here we need to specify that encoder output settings
-+	 * need to be calculated as for the set mode,
-+	 * it will lead to querying dynamic link capabilities
-+	 * which should be done before enable output */
-+
-+	uint32_t normalized_pix_clk = stream->public.timing.pix_clk_khz;
-+	switch (stream->public.timing.display_color_depth) {
-+	case COLOR_DEPTH_888:
-+		break;
-+	case COLOR_DEPTH_101010:
-+		normalized_pix_clk = (normalized_pix_clk * 30) / 24;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		normalized_pix_clk = (normalized_pix_clk * 36) / 24;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		normalized_pix_clk = (normalized_pix_clk * 48) / 24;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		dal_ddc_service_write_scdc_data(
-+			stream->sink->link->ddc,
-+			normalized_pix_clk,
-+			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
-+
-+	stream->sink->link->cur_link_settings.lane_count =
-+		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-+					? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+
-+	if (link->ctx->dc->hwss.encoder_enable_output(
-+			stream->sink->link->link_enc,
-+			&stream->sink->link->cur_link_settings,
-+			stream->stream_enc->id,
-+			dal_clock_source_get_id(stream->clock_source),
-+			stream->signal,
-+			stream->public.timing.display_color_depth,
-+			stream->public.timing.pix_clk_khz) != ENCODER_RESULT_OK)
-+		status = DC_ERROR_UNEXPECTED;
-+
-+	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		dal_ddc_service_read_scdc_data(link->ddc);
-+
-+	return status;
-+}
-+
-+/****************************enable_link***********************************/
-+enum dc_status core_link_enable(struct core_stream *stream)
-+{
-+	enum dc_status status;
-+	switch (stream->signal) {
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		status = enable_link_dp(stream);
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		status = enable_link_hdmi(stream);
-+		break;
-+
-+	default:
-+		status = DC_ERROR_UNEXPECTED;
-+		break;
-+	}
-+
-+	if (stream->audio) {
-+		stream->ctx->dc->hwss.set_afmt_memory_power_state(
-+				stream->ctx, stream->stream_enc->id, true);
-+		/* notify audio driver for audio modes of monitor */
-+		dal_audio_enable_azalia_audio_jack_presence(stream->audio,
-+				stream->stream_enc->id);
-+
-+		/* un-mute audio */
-+		dal_audio_unmute(stream->audio, stream->stream_enc->id,
-+				stream->signal);
-+	}
-+
-+	return status;
-+}
-+
-+enum dc_status core_link_disable(struct core_stream *stream)
-+{
-+	/* TODO  dp_set_hw_test_pattern */
-+	enum dc_status status = DC_OK;
-+	struct dc *dc = stream->ctx->dc;
-+
-+	/* here we need to specify that encoder output settings
-+	 * need to be calculated as for the set mode,
-+	 * it will lead to querying dynamic link capabilities
-+	 * which should be done before enable output */
-+
-+	if (dc_is_dp_signal(stream->signal))
-+		dp_disable_link_phy(stream->sink->link, stream->signal);
-+	else if (ENCODER_RESULT_OK != dc->hwss.encoder_disable_output(
-+					stream->sink->link->link_enc, stream->signal))
-+		status = DC_ERROR_UNEXPECTED;
-+
-+	if (stream->audio) {
-+		dc->hwss.set_afmt_memory_power_state(
-+				stream->ctx, stream->stream_enc->id, false);
-+	}
-+
-+	return status;
-+}
-+
-+enum dc_status dc_link_validate_mode_timing(
-+		const struct core_sink *sink,
-+		struct core_link *link,
-+		const struct dc_crtc_timing *timing)
-+{
-+	uint32_t max_pix_clk = sink->dongle_max_pix_clk;
-+
-+	if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
-+		return DC_EXCEED_DONGLE_MAX_CLK;
-+
-+	switch (sink->public.sink_signal) {
-+		case SIGNAL_TYPE_DISPLAY_PORT:
-+			if(!dp_validate_mode_timing(
-+					link,
-+					timing))
-+				return DC_NO_DP_LINK_BANDWIDTH;
-+			break;
-+
-+		default:
-+			break;
-+	}
-+
-+	return DC_OK;
-+}
-+
-+bool dc_link_set_backlight_level(const struct dc_link *public, uint32_t level)
-+{
-+	struct core_link *protected = DC_LINK_TO_CORE(public);
-+	struct dc_context *ctx = protected->ctx;
-+
-+	dal_logger_write(ctx->logger, LOG_MAJOR_BACKLIGHT,
-+			LOG_MINOR_BACKLIGHT_INTERFACE,
-+			"New Backlight level: %d (0x%X)\n", level, level);
-+
-+	ctx->dc->hwss.encoder_set_lcd_backlight_level(protected->link_enc, level);
-+
-+	return true;
-+}
-+
-+void core_link_resume(struct core_link *link)
-+{
-+	dal_connector_program_hpd_filter(
-+		link->connector,
-+		DELAY_ON_CONNECT_IN_MS,
-+		DELAY_ON_DISCONNECT_IN_MS);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-new file mode 100644
-index 0000000..9214aec
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -0,0 +1,1689 @@
-+/* Copyright 2015 Advanced Micro Devices, Inc. */
-+#include "dc_services.h"
-+#include "dc.h"
-+#include "dc_helpers.h"
-+#include "inc/core_types.h"
-+#include "link_hwss.h"
-+#include "ddc_service_interface.h"
-+#include "connector_interface.h"
-+#include "core_status.h"
-+#include "dpcd_defs.h"
-+
-+/* maximum pre emphasis level allowed for each voltage swing level*/
-+static const enum pre_emphasis voltage_swing_to_pre_emphasis[] = {
-+		PRE_EMPHASIS_LEVEL3,
-+		PRE_EMPHASIS_LEVEL2,
-+		PRE_EMPHASIS_LEVEL1,
-+		PRE_EMPHASIS_DISABLED };
-+
-+enum {
-+	POST_LT_ADJ_REQ_LIMIT = 6,
-+	POST_LT_ADJ_REQ_TIMEOUT = 200
-+};
-+
-+enum {
-+	LINK_TRAINING_MAX_RETRY_COUNT = 5,
-+	/* to avoid infinite loop where-in the receiver
-+	 * switches between different VS
-+	 */
-+	LINK_TRAINING_MAX_CR_RETRY = 100
-+};
-+
-+static const struct link_settings link_training_fallback_table[] = {
-+/* 2160 Mbytes/sec*/
-+{ LANE_COUNT_FOUR, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
-+/* 1080 Mbytes/sec*/
-+{ LANE_COUNT_FOUR, LINK_RATE_HIGH, LINK_SPREAD_DISABLED },
-+/* 648 Mbytes/sec*/
-+{ LANE_COUNT_FOUR, LINK_RATE_LOW, LINK_SPREAD_DISABLED },
-+/* 1080 Mbytes/sec*/
-+{ LANE_COUNT_TWO, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
-+/* 540 Mbytes/sec*/
-+{ LANE_COUNT_TWO, LINK_RATE_HIGH, LINK_SPREAD_DISABLED },
-+/* 324 Mbytes/sec*/
-+{ LANE_COUNT_TWO, LINK_RATE_LOW, LINK_SPREAD_DISABLED },
-+/* 540 Mbytes/sec*/
-+{ LANE_COUNT_ONE, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
-+/* 270 Mbytes/sec*/
-+{ LANE_COUNT_ONE, LINK_RATE_HIGH, LINK_SPREAD_DISABLED },
-+/* 162 Mbytes/sec*/
-+{ LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED } };
-+
-+static void wait_for_training_aux_rd_interval(
-+	struct core_link* link,
-+	uint32_t default_wait_in_micro_secs)
-+{
-+	uint8_t training_rd_interval;
-+
-+	/* overwrite the delay if rev > 1.1*/
-+	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
-+		/* DP 1.2 or later - retrieve delay through
-+		 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
-+		core_link_read_dpcd(
-+			link,
-+			DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL,
-+			&training_rd_interval,
-+			sizeof(training_rd_interval));
-+		default_wait_in_micro_secs = training_rd_interval ?
-+			(training_rd_interval * 4000) :
-+			default_wait_in_micro_secs;
-+	}
-+
-+	dc_service_delay_in_microseconds(link->ctx, default_wait_in_micro_secs);
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s:\n wait = %d\n",
-+		__func__,
-+		default_wait_in_micro_secs);
-+}
-+
-+static void dpcd_set_training_pattern(
-+	struct core_link* link,
-+	union dpcd_training_pattern dpcd_pattern)
-+{
-+	core_link_write_dpcd(
-+		link,
-+		DPCD_ADDRESS_TRAINING_PATTERN_SET,
-+		&dpcd_pattern.raw,
-+		1);
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s\n %x pattern = %x\n",
-+		__func__,
-+		DPCD_ADDRESS_TRAINING_PATTERN_SET,
-+		dpcd_pattern.bits.TRAINING_PATTERN_SET);
-+}
-+
-+static void dpcd_set_link_settings(
-+	struct core_link* link,
-+	const struct link_training_settings *lt_settings)
-+{
-+	uint8_t rate = (uint8_t)
-+	(lt_settings->link_settings.link_rate);
-+
-+	union down_spread_ctrl downspread = {{0}};
-+	union lane_count_set lane_count_set = {{0}};
-+	uint8_t link_set_buffer[2];
-+
-+
-+	downspread.raw = (uint8_t)
-+	(lt_settings->link_settings.link_spread);
-+
-+	lane_count_set.bits.LANE_COUNT_SET =
-+	lt_settings->link_settings.lane_count;
-+
-+	lane_count_set.bits.ENHANCED_FRAMING = 1;
-+
-+	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
-+		link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
-+
-+	link_set_buffer[0] = rate;
-+	link_set_buffer[1] = lane_count_set.raw;
-+
-+	core_link_write_dpcd(link, DPCD_ADDRESS_LINK_BW_SET,
-+	link_set_buffer, 2);
-+	core_link_write_dpcd(link, DPCD_ADDRESS_DOWNSPREAD_CNTL,
-+	&downspread.raw, sizeof(downspread));
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
-+		__func__,
-+		DPCD_ADDRESS_LINK_BW_SET,
-+		lt_settings->link_settings.link_rate,
-+		DPCD_ADDRESS_LANE_COUNT_SET,
-+		lt_settings->link_settings.lane_count,
-+		DPCD_ADDRESS_DOWNSPREAD_CNTL,
-+		lt_settings->link_settings.link_spread);
-+
-+}
-+
-+static enum dpcd_training_patterns
-+	hw_training_pattern_to_dpcd_training_pattern(
-+	struct core_link* link,
-+	enum hw_dp_training_pattern pattern)
-+{
-+	enum dpcd_training_patterns dpcd_tr_pattern =
-+	DPCD_TRAINING_PATTERN_VIDEOIDLE;
-+
-+	switch (pattern) {
-+	case HW_DP_TRAINING_PATTERN_1:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_2:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_3:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
-+		break;
-+	default:
-+		ASSERT(0);
-+		dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+			"%s: Invalid HW Training pattern: %d\n",
-+			__func__, pattern);
-+		break;
-+	}
-+
-+	return dpcd_tr_pattern;
-+
-+}
-+
-+static void dpcd_set_lt_pattern_and_lane_settings(
-+	struct core_link* link,
-+	const struct link_training_settings *lt_settings,
-+	enum hw_dp_training_pattern pattern)
-+{
-+	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
-+	const uint32_t dpcd_base_lt_offset =
-+	DPCD_ADDRESS_TRAINING_PATTERN_SET;
-+	uint8_t dpcd_lt_buffer[5] = {0};
-+	union dpcd_training_pattern dpcd_pattern = {{0}};
-+	uint32_t lane;
-+	uint32_t size_in_bytes;
-+	bool edp_workaround = false; /* TODO link_prop.INTERNAL */
-+
-+	/*****************************************************************
-+	* DpcdAddress_TrainingPatternSet
-+	*****************************************************************/
-+	dpcd_pattern.bits.TRAINING_PATTERN_SET =
-+		hw_training_pattern_to_dpcd_training_pattern(link, pattern);
-+
-+	dpcd_lt_buffer[DPCD_ADDRESS_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
-+		= dpcd_pattern.raw;
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s\n %x pattern = %x\n",
-+		__func__,
-+		DPCD_ADDRESS_TRAINING_PATTERN_SET,
-+		dpcd_pattern.bits.TRAINING_PATTERN_SET);
-+
-+
-+	/*****************************************************************
-+	* DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
-+	*****************************************************************/
-+	for (lane = 0; lane <
-+		(uint32_t)(lt_settings->link_settings.lane_count); lane++) {
-+
-+		dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
-+		(uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
-+		dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
-+		(uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
-+
-+		dpcd_lane[lane].bits.MAX_SWING_REACHED =
-+		(lt_settings->lane_settings[lane].VOLTAGE_SWING ==
-+		VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
-+		dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
-+		(lt_settings->lane_settings[lane].PRE_EMPHASIS ==
-+		PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
-+	}
-+
-+	/* concatinate everything into one buffer*/
-+
-+	size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
-+
-+	 // 0x00103 - 0x00102
-+	dc_service_memmove(
-+		&dpcd_lt_buffer[DPCD_ADDRESS_LANE0_SET - dpcd_base_lt_offset],
-+		dpcd_lane,
-+		size_in_bytes);
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s:\n %x VS set = %x  PE set = %x \
-+		max VS Reached = %x  max PE Reached = %x\n",
-+		__func__,
-+		DPCD_ADDRESS_LANE0_SET,
-+		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
-+		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
-+		dpcd_lane[0].bits.MAX_SWING_REACHED,
-+		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
-+
-+
-+	if (edp_workaround) {
-+		/* for eDP write in 2 parts because the 5-byte burst is
-+		* causing issues on some eDP panels (EPR#366724)
-+		*/
-+		core_link_write_dpcd(
-+			link,
-+			DPCD_ADDRESS_TRAINING_PATTERN_SET,
-+			&dpcd_pattern.raw,
-+			sizeof(dpcd_pattern.raw) );
-+
-+		core_link_write_dpcd(
-+			link,
-+			DPCD_ADDRESS_LANE0_SET,
-+			(uint8_t *)(dpcd_lane),
-+			size_in_bytes);
-+
-+		} else
-+		/* write it all in (1 + number-of-lanes)-byte burst*/
-+			core_link_write_dpcd(
-+				link,
-+				dpcd_base_lt_offset,
-+				dpcd_lt_buffer,
-+				size_in_bytes + sizeof(dpcd_pattern.raw) );
-+
-+	link->ln_setting = lt_settings->lane_settings[0];
-+}
-+
-+static bool is_cr_done(enum lane_count ln_count,
-+	union lane_status *dpcd_lane_status)
-+{
-+	bool done = true;
-+	uint32_t lane;
-+	/*LANEx_CR_DONE bits All 1's?*/
-+	for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
-+		if (!dpcd_lane_status[lane].bits.CR_DONE_0)
-+			done = false;
-+	}
-+	return done;
-+
-+}
-+
-+static bool is_ch_eq_done(enum lane_count ln_count,
-+	union lane_status *dpcd_lane_status,
-+	union lane_align_status_updated *lane_status_updated)
-+{
-+	bool done = true;
-+	uint32_t lane;
-+	if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
-+		done = false;
-+	else {
-+		for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
-+			if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
-+				!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
-+				done = false;
-+		}
-+	}
-+	return done;
-+
-+}
-+
-+static void update_drive_settings(
-+		struct link_training_settings *dest,
-+		struct link_training_settings src)
-+{
-+	uint32_t lane;
-+	for (lane = 0; lane < src.link_settings.lane_count; lane++) {
-+		dest->lane_settings[lane].VOLTAGE_SWING =
-+			src.lane_settings[lane].VOLTAGE_SWING;
-+		dest->lane_settings[lane].PRE_EMPHASIS =
-+			src.lane_settings[lane].PRE_EMPHASIS;
-+		dest->lane_settings[lane].POST_CURSOR2 =
-+			src.lane_settings[lane].POST_CURSOR2;
-+	}
-+}
-+
-+static uint8_t get_nibble_at_index(const uint8_t *buf,
-+	uint32_t index)
-+{
-+	uint8_t nibble;
-+	nibble = buf[index / 2];
-+
-+	if (index % 2)
-+		nibble >>= 4;
-+	else
-+		nibble &= 0x0F;
-+
-+	return nibble;
-+}
-+
-+static enum pre_emphasis get_max_pre_emphasis_for_voltage_swing(
-+	enum voltage_swing voltage)
-+{
-+	enum pre_emphasis pre_emphasis;
-+	pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
-+
-+	if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
-+		pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
-+
-+	return pre_emphasis;
-+
-+}
-+
-+static void find_max_drive_settings(
-+	const struct link_training_settings *link_training_setting,
-+	struct link_training_settings *max_lt_setting)
-+{
-+	uint32_t lane;
-+	struct lane_settings max_requested;
-+
-+	max_requested.VOLTAGE_SWING =
-+		link_training_setting->
-+		lane_settings[0].VOLTAGE_SWING;
-+	max_requested.PRE_EMPHASIS =
-+		link_training_setting->
-+		lane_settings[0].PRE_EMPHASIS;
-+	/*max_requested.postCursor2 =
-+	 * link_training_setting->laneSettings[0].postCursor2;*/
-+
-+	/* Determine what the maximum of the requested settings are*/
-+	for (lane = 1; lane < link_training_setting->link_settings.lane_count;
-+			lane++) {
-+		if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
-+			max_requested.VOLTAGE_SWING)
-+
-+			max_requested.VOLTAGE_SWING =
-+			link_training_setting->
-+			lane_settings[lane].VOLTAGE_SWING;
-+
-+
-+		if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
-+				max_requested.PRE_EMPHASIS)
-+			max_requested.PRE_EMPHASIS =
-+			link_training_setting->
-+			lane_settings[lane].PRE_EMPHASIS;
-+
-+		/*
-+		if (link_training_setting->laneSettings[lane].postCursor2 >
-+		 max_requested.postCursor2)
-+		{
-+		max_requested.postCursor2 =
-+		link_training_setting->laneSettings[lane].postCursor2;
-+		}
-+		*/
-+	}
-+
-+	/* make sure the requested settings are
-+	 * not higher than maximum settings*/
-+	if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
-+		max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
-+
-+	if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
-+		max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
-+	/*
-+	if (max_requested.postCursor2 > PostCursor2_MaxLevel)
-+	max_requested.postCursor2 = PostCursor2_MaxLevel;
-+	*/
-+
-+	/* make sure the pre-emphasis matches the voltage swing*/
-+	if (max_requested.PRE_EMPHASIS >
-+		get_max_pre_emphasis_for_voltage_swing(
-+			max_requested.VOLTAGE_SWING))
-+		max_requested.PRE_EMPHASIS =
-+		get_max_pre_emphasis_for_voltage_swing(
-+			max_requested.VOLTAGE_SWING);
-+
-+	/*
-+	 * Post Cursor2 levels are completely independent from
-+	 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
-+	 * can only be applied to each allowable combination of voltage
-+	 * swing and pre-emphasis levels */
-+	 /* if ( max_requested.postCursor2 >
-+	  *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
-+	  *  max_requested.postCursor2 =
-+	  *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
-+	  */
-+
-+	max_lt_setting->link_settings.link_rate =
-+		link_training_setting->link_settings.link_rate;
-+	max_lt_setting->link_settings.lane_count =
-+	link_training_setting->link_settings.lane_count;
-+	max_lt_setting->link_settings.link_spread =
-+		link_training_setting->link_settings.link_spread;
-+
-+	for (lane = 0; lane <
-+		link_training_setting->link_settings.lane_count;
-+		lane++) {
-+		max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
-+			max_requested.VOLTAGE_SWING;
-+		max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
-+			max_requested.PRE_EMPHASIS;
-+		/*max_lt_setting->laneSettings[lane].postCursor2 =
-+		 * max_requested.postCursor2;
-+		 */
-+	}
-+
-+}
-+
-+static void get_lane_status_and_drive_settings(
-+	struct core_link* link,
-+	const struct link_training_settings *link_training_setting,
-+	union lane_status *ln_status,
-+	union lane_align_status_updated *ln_status_updated,
-+	struct link_training_settings *req_settings)
-+{
-+	uint8_t dpcd_buf[6] = {0};
-+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
-+	struct link_training_settings request_settings = {{0}};
-+	uint32_t lane;
-+
-+	dc_service_memset(req_settings, '\0', sizeof(struct link_training_settings));
-+
-+	core_link_read_dpcd(
-+		link,
-+		DPCD_ADDRESS_LANE_01_STATUS,
-+		(uint8_t *)(dpcd_buf),
-+		sizeof(dpcd_buf));
-+
-+
-+	for (lane = 0; lane <
-+		(uint32_t)(link_training_setting->link_settings.lane_count);
-+		lane++) {
-+
-+		ln_status[lane].raw =
-+			get_nibble_at_index(&dpcd_buf[0], lane);
-+		dpcd_lane_adjust[lane].raw =
-+			get_nibble_at_index(&dpcd_buf[4], lane);
-+	}
-+
-+	ln_status_updated->raw = dpcd_buf[2];
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
-+		__func__,
-+		DPCD_ADDRESS_LANE_01_STATUS, dpcd_buf[0],
-+		DPCD_ADDRESS_LANE_23_STATUS, dpcd_buf[1]);
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
-+		__func__,
-+		DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1,
-+		dpcd_buf[4],
-+		DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3,
-+		dpcd_buf[5]);
-+
-+	/*copy to req_settings*/
-+	request_settings.link_settings.lane_count =
-+		link_training_setting->link_settings.lane_count;
-+	request_settings.link_settings.link_rate =
-+		link_training_setting->link_settings.link_rate;
-+	request_settings.link_settings.link_spread =
-+		link_training_setting->link_settings.link_spread;
-+
-+	for (lane = 0; lane <
-+		(uint32_t)(link_training_setting->link_settings.lane_count);
-+		lane++) {
-+
-+		request_settings.lane_settings[lane].VOLTAGE_SWING =
-+			(enum voltage_swing)(dpcd_lane_adjust[lane].bits.
-+				VOLTAGE_SWING_LANE);
-+		request_settings.lane_settings[lane].PRE_EMPHASIS =
-+			(enum pre_emphasis)(dpcd_lane_adjust[lane].bits.
-+				PRE_EMPHASIS_LANE);
-+	}
-+
-+	/*Note: for postcursor2, read adjusted
-+	 * postcursor2 settings from*/
-+	/*DpcdAddress_AdjustRequestPostCursor2 =
-+	 *0x020C (not implemented yet)*/
-+
-+	/* we find the maximum of the requested settings across all lanes*/
-+	/* and set this maximum for all lanes*/
-+	find_max_drive_settings(&request_settings, req_settings);
-+
-+	/* if post cursor 2 is needed in the future,
-+	 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
-+	 */
-+
-+}
-+
-+static void dpcd_set_lane_settings(
-+	struct core_link* link,
-+	const struct link_training_settings *link_training_setting)
-+{
-+	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
-+	uint32_t lane;
-+
-+	for (lane = 0; lane <
-+		(uint32_t)(link_training_setting->
-+		link_settings.lane_count);
-+		lane++) {
-+		dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
-+			(uint8_t)(link_training_setting->
-+			lane_settings[lane].VOLTAGE_SWING);
-+		dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
-+			(uint8_t)(link_training_setting->
-+			lane_settings[lane].PRE_EMPHASIS);
-+		dpcd_lane[lane].bits.MAX_SWING_REACHED =
-+			(link_training_setting->
-+			lane_settings[lane].VOLTAGE_SWING ==
-+			VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
-+		dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
-+			(link_training_setting->
-+			lane_settings[lane].PRE_EMPHASIS ==
-+			PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
-+	}
-+
-+	core_link_write_dpcd(link,
-+		DPCD_ADDRESS_LANE0_SET,
-+		(uint8_t *)(dpcd_lane),
-+		link_training_setting->link_settings.lane_count);
-+
-+	/*
-+	if (LTSettings.link.rate == LinkRate_High2)
-+	{
-+		DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
-+		for ( uint32_t lane = 0;
-+		lane < lane_count_DPMax; lane++)
-+		{
-+			dpcd_lane2[lane].bits.post_cursor2_set =
-+			static_cast<unsigned char>(
-+			LTSettings.laneSettings[lane].postCursor2);
-+			dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
-+		}
-+		m_pDpcdAccessSrv->WriteDpcdData(
-+		DpcdAddress_Lane0Set2,
-+		reinterpret_cast<unsigned char*>(dpcd_lane2),
-+		LTSettings.link.lanes);
-+	}
-+	*/
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+		"%s\n %x VS set = %x  PE set = %x \
-+		max VS Reached = %x  max PE Reached = %x\n",
-+		__func__,
-+		DPCD_ADDRESS_LANE0_SET,
-+		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
-+		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
-+		dpcd_lane[0].bits.MAX_SWING_REACHED,
-+		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
-+
-+	link->ln_setting = link_training_setting->lane_settings[0];
-+
-+}
-+
-+static bool is_max_vs_reached(
-+	const struct link_training_settings *lt_settings)
-+{
-+	uint32_t lane;
-+	for (lane = 0; lane <
-+		(uint32_t)(lt_settings->link_settings.lane_count);
-+		lane++) {
-+		if (lt_settings->lane_settings[lane].VOLTAGE_SWING
-+			== VOLTAGE_SWING_MAX_LEVEL)
-+			return true;
-+	}
-+	return false;
-+
-+}
-+
-+void set_drive_settings(
-+	struct core_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	/* program ASIC PHY settings*/
-+	dp_set_hw_lane_settings(link, lt_settings);
-+
-+	/* Notify DP sink the PHY settings from source */
-+	dpcd_set_lane_settings(link, lt_settings);
-+}
-+
-+static bool perform_post_lt_adj_req_sequence(
-+	struct core_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	enum lane_count lane_count =
-+	lt_settings->link_settings.lane_count;
-+
-+	uint32_t adj_req_count;
-+	uint32_t adj_req_timer;
-+	bool req_drv_setting_changed;
-+	uint32_t lane;
-+
-+	req_drv_setting_changed = false;
-+	for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
-+	adj_req_count++) {
-+
-+		req_drv_setting_changed = false;
-+
-+		for (adj_req_timer = 0;
-+			adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
-+			adj_req_timer++) {
-+
-+			struct link_training_settings req_settings;
-+			union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
-+			union lane_align_status_updated
-+				dpcd_lane_status_updated;
-+
-+			get_lane_status_and_drive_settings(
-+			link,
-+			lt_settings,
-+			dpcd_lane_status,
-+			&dpcd_lane_status_updated,
-+			&req_settings);
-+
-+			if (dpcd_lane_status_updated.bits.
-+					POST_LT_ADJ_REQ_IN_PROGRESS == 0)
-+				return true;
-+
-+			if (!is_cr_done(lane_count, dpcd_lane_status))
-+				return false;
-+
-+			if (!is_ch_eq_done(
-+				lane_count,
-+				dpcd_lane_status,
-+				&dpcd_lane_status_updated))
-+				return false;
-+
-+			for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
-+
-+				if (lt_settings->
-+				lane_settings[lane].VOLTAGE_SWING !=
-+				req_settings.lane_settings[lane].
-+				VOLTAGE_SWING ||
-+				lt_settings->lane_settings[lane].PRE_EMPHASIS !=
-+				req_settings.lane_settings[lane].PRE_EMPHASIS) {
-+
-+					req_drv_setting_changed = true;
-+					break;
-+				}
-+			}
-+
-+			if (req_drv_setting_changed) {
-+				update_drive_settings(
-+					lt_settings,req_settings);
-+
-+				set_drive_settings(link, lt_settings);
-+				break;
-+			}
-+
-+			dc_service_sleep_in_milliseconds(link->ctx, 1);
-+		}
-+
-+		if (!req_drv_setting_changed) {
-+			dal_logger_write(link->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_LINK_SERVICE,
-+				"%s: Post Link Training Adjust Request Timed out\n",
-+				__func__);
-+
-+			ASSERT(0);
-+			return true;
-+		}
-+	}
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_WARNING,
-+		LOG_MINOR_COMPONENT_LINK_SERVICE,
-+		"%s: Post Link Training Adjust Request limit reached\n",
-+		__func__);
-+
-+	ASSERT(0);
-+	return true;
-+
-+}
-+
-+static bool perform_channel_equalization_sequence(
-+	struct core_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	struct link_training_settings req_settings;
-+	enum hw_dp_training_pattern hw_tr_pattern;
-+	uint32_t retries_ch_eq;
-+	enum lane_count lane_count = lt_settings->link_settings.lane_count;
-+	union lane_align_status_updated dpcd_lane_status_updated = {{0}};
-+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
-+
-+	/*TODO hw_tr_pattern = HW_DP_TRAINING_PATTERN_3;*/
-+	hw_tr_pattern = HW_DP_TRAINING_PATTERN_2;
-+
-+	dp_set_hw_training_pattern(link, hw_tr_pattern);
-+
-+	for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
-+		retries_ch_eq++) {
-+
-+		dp_set_hw_lane_settings(link, lt_settings);
-+
-+		/* 2. update DPCD*/
-+		if (!retries_ch_eq)
-+			/* EPR #361076 - write as a 5-byte burst,
-+			 * but only for the 1-st iteration*/
-+			dpcd_set_lt_pattern_and_lane_settings(
-+				link,
-+				lt_settings,
-+				hw_tr_pattern);
-+		else
-+			dpcd_set_lane_settings(link, lt_settings);
-+
-+		/* 3. wait for receiver to lock-on*/
-+		wait_for_training_aux_rd_interval(link, 400);
-+
-+		/* 4. Read lane status and requested
-+		 * drive settings as set by the sink*/
-+
-+		get_lane_status_and_drive_settings(
-+			link,
-+			lt_settings,
-+			dpcd_lane_status,
-+			&dpcd_lane_status_updated,
-+			&req_settings);
-+
-+		/* 5. check CR done*/
-+		if (!is_cr_done(lane_count, dpcd_lane_status))
-+			return false;
-+
-+		/* 6. check CHEQ done*/
-+		if (is_ch_eq_done(lane_count,
-+			dpcd_lane_status,
-+			&dpcd_lane_status_updated))
-+			return true;
-+
-+		/* 7. update VS/PE/PC2 in lt_settings*/
-+		update_drive_settings(lt_settings, req_settings);
-+	}
-+
-+	return false;
-+
-+}
-+
-+static bool perform_clock_recovery_sequence(
-+	struct core_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	uint32_t retries_cr;
-+	uint32_t retry_count;
-+	uint32_t lane;
-+	struct link_training_settings req_settings;
-+	enum lane_count lane_count =
-+	lt_settings->link_settings.lane_count;
-+	enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
-+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
-+	union lane_align_status_updated dpcd_lane_status_updated;
-+
-+	retries_cr = 0;
-+	retry_count = 0;
-+	/* initial drive setting (VS/PE/PC2)*/
-+	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
-+		lt_settings->lane_settings[lane].VOLTAGE_SWING =
-+		VOLTAGE_SWING_LEVEL0;
-+		lt_settings->lane_settings[lane].PRE_EMPHASIS =
-+		PRE_EMPHASIS_DISABLED;
-+		lt_settings->lane_settings[lane].POST_CURSOR2 =
-+		POST_CURSOR2_DISABLED;
-+	}
-+
-+	dp_set_hw_training_pattern(link, hw_tr_pattern);
-+
-+	/* najeeb - The synaptics MST hub can put the LT in
-+	* infinite loop by switching the VS
-+	*/
-+	/* between level 0 and level 1 continuously, here
-+	* we try for CR lock for LinkTrainingMaxCRRetry count*/
-+	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
-+	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
-+
-+		dc_service_memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
-+		dc_service_memset(&dpcd_lane_status_updated, '\0',
-+		sizeof(dpcd_lane_status_updated));
-+
-+		/* 1. call HWSS to set lane settings*/
-+		dp_set_hw_lane_settings(
-+				link,
-+				lt_settings);
-+
-+		/* 2. update DPCD of the receiver*/
-+		if (!retries_cr)
-+			/* EPR #361076 - write as a 5-byte burst,
-+			 * but only for the 1-st iteration.*/
-+			dpcd_set_lt_pattern_and_lane_settings(
-+					link,
-+					lt_settings,
-+					hw_tr_pattern);
-+		else
-+			dpcd_set_lane_settings(
-+					link,
-+					lt_settings);
-+
-+
-+		/* 3. wait receiver to lock-on*/
-+		wait_for_training_aux_rd_interval(
-+				link,
-+				100);
-+
-+		/* 4. Read lane status and requested drive
-+		* settings as set by the sink
-+		*/
-+		get_lane_status_and_drive_settings(
-+				link,
-+				lt_settings,
-+				dpcd_lane_status,
-+				&dpcd_lane_status_updated,
-+				&req_settings);
-+
-+
-+		/* 5. check CR done*/
-+		if (is_cr_done(lane_count, dpcd_lane_status))
-+			return true;
-+
-+		/* 6. max VS reached*/
-+		if (is_max_vs_reached(lt_settings))
-+			return false;
-+
-+		/* 7. same voltage*/
-+		/* Note: VS same for all lanes,
-+		* so comparing first lane is sufficient*/
-+		if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
-+			req_settings.lane_settings[0].VOLTAGE_SWING)
-+			retries_cr++;
-+		else
-+			retries_cr = 0;
-+
-+
-+			/* 8. update VS/PE/PC2 in lt_settings*/
-+			update_drive_settings(lt_settings, req_settings);
-+
-+			retry_count++;
-+	}
-+
-+	if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
-+		ASSERT(0);
-+		dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_LINK_SERVICE,
-+			"%s: Link Training Error, could not \
-+			 get CR after %d tries. \
-+			Possibly voltage swing issue", __func__,
-+			LINK_TRAINING_MAX_CR_RETRY);
-+
-+	}
-+
-+	return false;
-+}
-+
-+ bool perform_link_training(
-+	struct core_link *link,
-+	const struct link_settings *link_setting,
-+	bool skip_video_pattern)
-+{
-+	bool status;
-+	union dpcd_training_pattern dpcd_pattern = {{0}};
-+	union lane_count_set lane_count_set = {{0}};
-+	const int8_t *link_rate = "Unknown";
-+	struct link_training_settings lt_settings;
-+
-+	status = false;
-+	dc_service_memset(&lt_settings, '\0', sizeof(lt_settings));
-+
-+	lt_settings.link_settings.link_rate = link_setting->link_rate;
-+	lt_settings.link_settings.lane_count = link_setting->lane_count;
-+
-+	/*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
-+
-+	/* TODO hard coded to SS for now
-+	 * lt_settings.link_settings.link_spread =
-+	 * dal_display_path_is_ss_supported(
-+	 * path_mode->display_path) ?
-+	 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
-+	 * LINK_SPREAD_DISABLED;
-+	 */
-+	lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
-+
-+	/* 1. set link rate, lane count and spread*/
-+	dpcd_set_link_settings(link, &lt_settings);
-+
-+	/* 2. perform link training (set link training done
-+	 *  to false is done as well)*/
-+	if (perform_clock_recovery_sequence(link, &lt_settings)) {
-+
-+		if (perform_channel_equalization_sequence(link, &lt_settings))
-+			status = true;
-+	}
-+
-+	if (status || !skip_video_pattern) {
-+
-+		/* 3. set training not in progress*/
-+		dpcd_pattern.bits.TRAINING_PATTERN_SET =
-+			DPCD_TRAINING_PATTERN_VIDEOIDLE;
-+		dpcd_set_training_pattern(link, dpcd_pattern);
-+
-+		/* 4. mainlink output idle pattern*/
-+		dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE);
-+
-+		/* 5. post training adjust if required*/
-+		if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED
-+			== 1) {
-+			if (status == true) {
-+				if (perform_post_lt_adj_req_sequence(
-+					link, &lt_settings) == false)
-+					status = false;
-+			}
-+
-+			lane_count_set.bits.LANE_COUNT_SET =
-+				lt_settings.link_settings.lane_count;
-+			lane_count_set.bits.ENHANCED_FRAMING = 1;
-+			lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
-+
-+			core_link_write_dpcd(
-+				link,
-+				DPCD_ADDRESS_LANE_COUNT_SET,
-+				&lane_count_set.raw,
-+				sizeof(lane_count_set));
-+		}
-+	}
-+
-+	/* 6. print status message*/
-+	switch (lt_settings.link_settings.link_rate) {
-+
-+	case LINK_RATE_LOW:
-+		link_rate = "Low";
-+		break;
-+	case LINK_RATE_HIGH:
-+		link_rate = "High";
-+		break;
-+	case LINK_RATE_HIGH2:
-+		link_rate = "High2";
-+		break;
-+	case LINK_RATE_RBR2:
-+		link_rate = "RBR2";
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_MST,
-+		LOG_MINOR_MST_PROGRAMMING,
-+		"Link training for %d lanes at %s rate %s\n",
-+		lt_settings.link_settings.lane_count,
-+		link_rate,
-+		status ? "succeeded" : "failed");
-+
-+	return status;
-+}
-+
-+/*TODO add more check to see if link support request link configuration */
-+static bool is_link_setting_supported(
-+	const struct link_settings *link_setting,
-+	const struct link_settings *max_link_setting)
-+{
-+	if (link_setting->lane_count > max_link_setting->lane_count ||
-+		link_setting->link_rate > max_link_setting->link_rate)
-+		return false;
-+	return true;
-+}
-+
-+static const uint32_t get_link_training_fallback_table_len(
-+	struct core_link *link)
-+{
-+	return ARRAY_SIZE(link_training_fallback_table);
-+}
-+
-+static const struct link_settings *get_link_training_fallback_table(
-+	struct core_link *link, uint32_t i)
-+{
-+	return &link_training_fallback_table[i];
-+}
-+
-+static bool exceeded_limit_link_setting(const struct link_settings *link_setting,
-+			const struct link_settings *limit_link_setting)
-+{
-+	return (link_setting->lane_count * link_setting->link_rate
-+		 > limit_link_setting->lane_count * limit_link_setting->link_rate ?
-+				 true : false);
-+}
-+
-+
-+bool dp_hbr_verify_link_cap(
-+	struct core_link *link,
-+	struct link_settings *known_limit_link_setting)
-+{
-+	struct link_settings max_link_cap = {0};
-+	bool success;
-+	bool skip_link_training;
-+	const struct link_settings *cur;
-+	bool skip_video_pattern;
-+	uint32_t i;
-+
-+	success = false;
-+	skip_link_training = false;
-+
-+	/* TODO confirm this is correct for cz */
-+	max_link_cap.lane_count = LANE_COUNT_FOUR;
-+	max_link_cap.link_rate = LINK_RATE_HIGH2;
-+	max_link_cap.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
-+
-+	/* TODO implement override and monitor patch later */
-+
-+	/* try to train the link from high to low to
-+	 * find the physical link capability
-+	 */
-+	/* disable PHY done possible by BIOS, will be done by driver itself */
-+	dp_disable_link_phy(link, link->public.connector_signal);
-+
-+	for (i = 0; i < get_link_training_fallback_table_len(link) &&
-+		!success; i++) {
-+		cur = get_link_training_fallback_table(link, i);
-+
-+		if (known_limit_link_setting->lane_count != LANE_COUNT_UNKNOWN &&
-+			exceeded_limit_link_setting(cur,
-+					known_limit_link_setting))
-+			continue;
-+
-+		if (!is_link_setting_supported(cur, &max_link_cap))
-+			continue;
-+
-+		skip_video_pattern = true;
-+		if (cur->link_rate == LINK_RATE_LOW)
-+			skip_video_pattern = false;
-+		if (dp_enable_link_phy(
-+				link,
-+				link->public.connector_signal,
-+				ENGINE_ID_UNKNOWN,
-+				cur)) {
-+			if (skip_link_training)
-+				success = true;
-+			else {
-+				uint8_t num_retries = 3;
-+				uint8_t j;
-+				uint8_t delay_between_retries = 10;
-+				for (j = 0; j < num_retries; ++j) {
-+					success = perform_link_training(
-+						link,
-+						cur,
-+						skip_video_pattern);
-+
-+					if (success)
-+						break;
-+
-+					dc_service_sleep_in_milliseconds(
-+						link->ctx,
-+						delay_between_retries);
-+
-+					delay_between_retries += 10;
-+				}
-+			}
-+		}
-+
-+		if (success)
-+			link->verified_link_cap = *cur;
-+
-+		/* always disable the link before trying another
-+		 * setting or before returning we'll enable it later
-+		 * based on the actual mode we're driving
-+		 */
-+		dp_disable_link_phy(link, link->public.connector_signal);
-+	}
-+
-+	/* Link Training failed for all Link Settings
-+	 *  (Lane Count is still unknown)
-+	 */
-+	if (!success) {
-+		/* If all LT fails for all settings,
-+		 * set verified = failed safe (1 lane low)
-+		 */
-+		link->verified_link_cap.lane_count = LANE_COUNT_ONE;
-+		link->verified_link_cap.link_rate = LINK_RATE_LOW;
-+
-+		link->verified_link_cap.link_spread =
-+		LINK_SPREAD_DISABLED;
-+	}
-+
-+	link->max_link_setting = link->verified_link_cap;
-+
-+	return success;
-+}
-+
-+static uint32_t bandwidth_in_kbps_from_timing(
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t bits_per_channel = 0;
-+	uint32_t kbps;
-+	switch (timing->display_color_depth) {
-+
-+	case COLOR_DEPTH_666:
-+		bits_per_channel = 6;
-+		break;
-+	case COLOR_DEPTH_888:
-+		bits_per_channel = 8;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		bits_per_channel = 10;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		bits_per_channel = 12;
-+		break;
-+	case COLOR_DEPTH_141414:
-+		bits_per_channel = 14;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		bits_per_channel = 16;
-+		break;
-+	default:
-+		break;
-+	}
-+	ASSERT(bits_per_channel != 0);
-+
-+	kbps = timing->pix_clk_khz;
-+	kbps *= bits_per_channel;
-+
-+	if (timing->flags.Y_ONLY != 1)
-+		/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
-+		kbps *= 3;
-+
-+	return kbps;
-+
-+}
-+
-+static uint32_t bandwidth_in_kbps_from_link_settings(
-+	const struct link_settings *link_setting)
-+{
-+	uint32_t link_rate_in_kbps = link_setting->link_rate *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+
-+	uint32_t lane_count  = link_setting->lane_count;
-+	uint32_t kbps = link_rate_in_kbps;
-+	kbps *= lane_count;
-+	kbps *= 8;   /* 8 bits per byte*/
-+
-+	return kbps;
-+
-+}
-+
-+bool dp_validate_mode_timing(
-+	struct core_link *link,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t req_bw;
-+	uint32_t max_bw;
-+
-+	const struct link_settings *link_setting;
-+
-+	/*always DP fail safe mode*/
-+	if (timing->pix_clk_khz == (uint32_t)25175 &&
-+		timing->h_addressable == (uint32_t)640 &&
-+		timing->v_addressable == (uint32_t)480)
-+		return true;
-+
-+	/* For static validation we always use reported
-+	 * link settings for other cases, when no modelist
-+	 * changed we can use verified link setting*/
-+	link_setting = &link->reported_link_cap;
-+
-+	/* TODO: DYNAMIC_VALIDATION needs to be implemented */
-+	/*if (flags.DYNAMIC_VALIDATION == 1 &&
-+		link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
-+		link_setting = &link->verified_link_cap;
-+	*/
-+
-+	req_bw = bandwidth_in_kbps_from_timing(timing);
-+	max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
-+
-+	if (req_bw < max_bw) {
-+		/* remember the biggest mode here, during
-+		 * initial link training (to get
-+		 * verified_link_cap), LS sends event about
-+		 * cannot train at reported cap to upper
-+		 * layer and upper layer will re-enumerate modes.
-+		 * this is not necessary if the lower
-+		 * verified_link_cap is enough to drive
-+		 * all the modes */
-+
-+		/* TODO: DYNAMIC_VALIDATION needs to be implemented */
-+		/* if (flags.DYNAMIC_VALIDATION == 1)
-+			dpsst->max_req_bw_for_verified_linkcap = dal_max(
-+				dpsst->max_req_bw_for_verified_linkcap, req_bw); */
-+		return true;
-+	} else
-+		return false;
-+}
-+
-+void decide_link_settings(struct core_stream *stream,
-+	struct link_settings *link_setting)
-+{
-+
-+	const struct link_settings *cur_ls;
-+	struct core_link* link;
-+	uint32_t req_bw;
-+	uint32_t link_bw;
-+	uint32_t i;
-+
-+	req_bw = bandwidth_in_kbps_from_timing(
-+			&stream->public.timing);
-+
-+	/* if preferred is specified through AMDDP, use it, if it's enough
-+	 * to drive the mode
-+	 */
-+	link = stream->sink->link;
-+
-+	if ((link->reported_link_cap.lane_count != LANE_COUNT_UNKNOWN) &&
-+		(link->reported_link_cap.link_rate <=
-+				link->verified_link_cap.link_rate)) {
-+
-+		link_bw = bandwidth_in_kbps_from_link_settings(
-+				&link->reported_link_cap);
-+
-+		if (req_bw < link_bw) {
-+			*link_setting = link->reported_link_cap;
-+			return;
-+		}
-+	}
-+
-+	/* search for first suitable setting for the requested
-+	 * bandwidth
-+	 */
-+	for (i = 0; i < get_link_training_fallback_table_len(link); i++) {
-+
-+		cur_ls = get_link_training_fallback_table(link, i);
-+
-+		link_bw =
-+				bandwidth_in_kbps_from_link_settings(
-+				cur_ls);
-+
-+		if (req_bw < link_bw) {
-+			if (is_link_setting_supported(
-+				cur_ls,
-+				&link->max_link_setting)) {
-+				*link_setting = *cur_ls;
-+				return;
-+			}
-+		}
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	ASSERT(link->verified_link_cap.lane_count !=
-+		LANE_COUNT_UNKNOWN);
-+
-+	*link_setting = link->verified_link_cap;
-+}
-+
-+/*************************Short Pulse IRQ***************************/
-+
-+static bool hpd_rx_irq_check_link_loss_status(
-+	struct core_link *link,
-+	union hpd_irq_data *hpd_irq_dpcd_data)
-+{
-+	uint8_t irq_reg_rx_power_state;
-+	enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
-+	union lane_status lane_status;
-+	uint32_t lane;
-+	bool sink_status_changed;
-+	bool return_code;
-+
-+	sink_status_changed = false;
-+	return_code = false;
-+
-+	if (link->cur_link_settings.lane_count == 0)
-+		return return_code;
-+	/*1. Check that we can handle interrupt: Not in FS DOS,
-+	 *  Not in "Display Timeout" state, Link is trained.
-+	 */
-+
-+	dpcd_result = core_link_read_dpcd(link,
-+	DPCD_ADDRESS_POWER_STATE,
-+	&irq_reg_rx_power_state,
-+	sizeof(irq_reg_rx_power_state));
-+
-+	if (dpcd_result != DC_OK) {
-+		irq_reg_rx_power_state = DP_PWR_STATE_D0;
-+		dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_HW_TRACE_HPD_IRQ,
-+			"%s: DPCD read failed to obtain power state.\n",
-+			__func__);
-+	}
-+
-+	if (irq_reg_rx_power_state == DP_PWR_STATE_D0) {
-+
-+		/*2. Check that Link Status changed, before re-training.*/
-+
-+		/*parse lane status*/
-+		for (lane = 0; lane <
-+			(uint32_t)(link->cur_link_settings.lane_count) &&
-+			!sink_status_changed; lane++) {
-+
-+			/* check status of lanes 0,1
-+			 * changed DpcdAddress_Lane01Status (0x202)*/
-+			lane_status.raw = get_nibble_at_index(
-+			&hpd_irq_dpcd_data->bytes.lane01_status.raw,
-+			lane);
-+
-+			if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
-+				!lane_status.bits.CR_DONE_0 ||
-+				!lane_status.bits.SYMBOL_LOCKED_0) {
-+				/* if one of the channel equalization, clock
-+				 * recovery or symbol lock is dropped
-+				 * consider it as (link has been
-+				 * dropped) dp sink status has changed*/
-+				sink_status_changed = true;
-+				break;
-+			}
-+
-+		}
-+
-+		/* Check interlane align.*/
-+		if (sink_status_changed ||
-+			!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
-+			INTERLANE_ALIGN_DONE) {
-+
-+			dal_logger_write(link->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_HPD_IRQ,
-+				"%s: Link Status changed.\n",
-+				__func__);
-+
-+			return_code = true;
-+		}
-+	}
-+
-+	return return_code;
-+}
-+
-+static enum dc_status read_hpd_rx_irq_data(
-+	struct core_link *link,
-+	union hpd_irq_data *irq_data)
-+{
-+	/* The HW reads 16 bytes from 200h on HPD,
-+	 * but if we get an AUX_DEFER, the HW cannot retry
-+	 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
-+	 * fail, so we now explicitly read 6 bytes which is
-+	 * the req from the above mentioned test cases.
-+	 */
-+	return core_link_read_dpcd(
-+	link,
-+	DPCD_ADDRESS_SINK_COUNT,
-+	irq_data->raw,
-+	sizeof(union hpd_irq_data));
-+}
-+
-+bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
-+{
-+	struct core_link *link = DC_LINK_TO_LINK(dc_link);
-+	union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
-+	enum dc_status result = DDC_RESULT_UNKNOWN;
-+	bool status = false;
-+	/* For use cases related to down stream connection status change,
-+	 * PSR and device auto test, refer to function handle_sst_hpd_irq
-+	 * in DAL2.1*/
-+
-+	dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_HPD_IRQ,
-+		"%s: Got short pulse HPD on connector %d\n",
-+		__func__, link->connector_index);
-+
-+	 /* All the "handle_hpd_irq_xxx()" methods
-+	 * should be called only after
-+	 * dal_dpsst_ls_read_hpd_irq_data
-+	 * Order of calls is important too
-+	 */
-+	result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
-+
-+	if (result != DC_OK) {
-+		dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_HW_TRACE_HPD_IRQ,
-+			"%s: DPCD read failed to obtain irq data\n",
-+			__func__);
-+		return false;
-+	}
-+
-+	/* check if we have MST msg and return since we poll for it */
-+	if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY ||
-+		hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
-+		return false;
-+
-+
-+	/* For now we only handle 'Downstream port status' case. */
-+	/* If we got sink count changed it means Downstream port status changed,
-+	 * then DM should call DC to do the detection. */
-+	if (hpd_rx_irq_check_link_loss_status(
-+		link,
-+		&hpd_irq_dpcd_data)) {
-+		perform_link_training(link, &link->cur_link_settings, true);
-+		status = false;
-+	}
-+
-+	if (hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
-+				!= link->dpcd_sink_count)
-+		status = true;
-+
-+	/* reasons for HPD RX:
-+	 * 1. Link Loss - ie Re-train the Link
-+	 * 2. MST sideband message
-+	 * 3. Automated Test - ie. Internal Commit
-+	 * 4. CP (copy protection) - (not interesting for DM???)
-+	 * 5. DRR
-+	 * 6. Downstream Port status changed -ie. Detect - this the only one
-+	 * which is interesting for DM because it must call dc_link_detect.
-+	 */
-+	return status;
-+}
-+
-+/*query dpcd for version and mst cap addresses*/
-+bool is_mst_supported(struct core_link *link)
-+{
-+	bool mst          = false;
-+	enum dc_status st = DC_OK;
-+	union dpcd_rev rev;
-+	union mstm_cap cap;
-+
-+	rev.raw  = 0;
-+	cap.raw  = 0;
-+
-+	st = core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV, &rev.raw,
-+			sizeof(rev));
-+
-+	if (st == DC_OK && rev.raw >= DPCD_REV_12) {
-+
-+		st = core_link_read_dpcd(link, DPCD_ADDRESS_MSTM_CAP,
-+				&cap.raw, sizeof(cap));
-+		if (st == DC_OK && cap.bits.MST_CAP == 1)
-+			mst = true;
-+	}
-+	return mst;
-+
-+}
-+
-+static void get_active_converter_info(
-+	uint8_t data, struct core_link *link)
-+{
-+	union dp_downstream_port_present ds_port = { .byte = data };
-+
-+	/* decode converter info*/
-+	if (!ds_port.fields.PORT_PRESENT) {
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
-+		ddc_service_set_dongle_type(link->ddc,
-+				link->dpcd_caps.dongle_type);
-+		return;
-+	}
-+
-+	switch (ds_port.fields.PORT_TYPE) {
-+	case DOWNSTREAM_VGA:
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
-+		break;
-+	case DOWNSTREAM_DVI_HDMI:
-+		/* At this point we don't know is it DVI or HDMI,
-+		 * assume DVI.*/
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
-+		break;
-+	default:
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
-+		break;
-+	}
-+
-+	if (link->dpcd_caps.dpcd_rev.raw >= DCS_DPCD_REV_11) {
-+		uint8_t det_caps[4];
-+		union dwnstream_port_caps_byte0 *port_caps =
-+			(union dwnstream_port_caps_byte0 *)det_caps;
-+		core_link_read_dpcd(link, DPCD_ADDRESS_DWN_STRM_PORT0_CAPS,
-+				det_caps, sizeof(det_caps));
-+
-+		switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
-+		case DOWN_STREAM_DETAILED_VGA:
-+			link->dpcd_caps.dongle_type =
-+				DISPLAY_DONGLE_DP_VGA_CONVERTER;
-+			break;
-+		case DOWN_STREAM_DETAILED_DVI:
-+			link->dpcd_caps.dongle_type =
-+				DISPLAY_DONGLE_DP_DVI_CONVERTER;
-+			break;
-+		case DOWN_STREAM_DETAILED_HDMI:
-+			link->dpcd_caps.dongle_type =
-+				DISPLAY_DONGLE_DP_HDMI_CONVERTER;
-+
-+			if (ds_port.fields.DETAILED_CAPS) {
-+
-+				union dwnstream_port_caps_byte3_hdmi
-+					hdmi_caps = {.raw = det_caps[3] };
-+
-+				link->dpcd_caps.is_dp_hdmi_s3d_converter =
-+					hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
-+			}
-+			break;
-+		}
-+	}
-+	ddc_service_set_dongle_type(link->ddc,
-+			link->dpcd_caps.dongle_type);
-+}
-+
-+static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data,
-+		int length)
-+{
-+	int retry = 0;
-+	struct dp_device_vendor_id dp_id;
-+	union dp_downstream_port_present ds_port = { 0 };
-+
-+	if (!link->dpcd_caps.dpcd_rev.raw) {
-+		do {
-+			dp_receiver_power_ctrl(link, true);
-+			core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV,
-+							dpcd_data, length);
-+			link->dpcd_caps.dpcd_rev.raw = dpcd_data[
-+				DPCD_ADDRESS_DPCD_REV -
-+				DPCD_ADDRESS_DPCD_REV];
-+		} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
-+	}
-+
-+	ds_port.byte = dpcd_data[DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT -
-+				 DPCD_ADDRESS_DPCD_REV];
-+
-+	get_active_converter_info(ds_port.byte, link);
-+
-+	/* read IEEE branch device id */
-+	core_link_read_dpcd(link, DPCD_ADDRESS_BRANCH_DEVICE_ID_START,
-+			(uint8_t *)&dp_id, sizeof(dp_id));
-+	link->dpcd_caps.branch_dev_id =
-+			(dp_id.ieee_oui[0] << 16) +
-+			(dp_id.ieee_oui[1] << 8) +
-+			dp_id.ieee_oui[2];
-+
-+	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
-+		switch (link->dpcd_caps.branch_dev_id) {
-+		/* Some active dongles (DP-VGA, DP-DLDVI converters) power down
-+		 * all internal circuits including AUX communication preventing
-+		 * reading DPCD table and EDID (spec violation).
-+		 * Encoder will skip DP RX power down on disable_output to
-+		 * keep receiver powered all the time.*/
-+		case DP_BRANCH_DEVICE_ID_1:
-+		case DP_BRANCH_DEVICE_ID_4:
-+			link->dp_wa.bits.KEEP_RECEIVER_POWERED = 1;
-+			break;
-+
-+		/* TODO: May need work around for other dongles. */
-+		default:
-+			link->dp_wa.bits.KEEP_RECEIVER_POWERED = 0;
-+			break;
-+		}
-+	} else
-+		link->dp_wa.bits.KEEP_RECEIVER_POWERED = 0;
-+}
-+
-+static void retrieve_link_cap(struct core_link *link)
-+{
-+	uint8_t dpcd_data[
-+			DPCD_ADDRESS_EDP_CONFIG_CAP -
-+			DPCD_ADDRESS_DPCD_REV + 1];
-+
-+	union down_stream_port_count down_strm_port_count;
-+	union edp_configuration_cap edp_config_cap;
-+	union max_down_spread max_down_spread;
-+	union dp_downstream_port_present ds_port = { 0 };
-+
-+	dc_service_memset(dpcd_data, '\0', sizeof(dpcd_data));
-+	dc_service_memset(&down_strm_port_count,
-+		'\0', sizeof(union down_stream_port_count));
-+	dc_service_memset(&edp_config_cap, '\0',
-+		sizeof(union edp_configuration_cap));
-+	dc_service_memset(&max_down_spread, '\0',
-+		sizeof(union max_down_spread));
-+
-+	core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV,
-+			dpcd_data, sizeof(dpcd_data));
-+	link->dpcd_caps.dpcd_rev.raw = dpcd_data[
-+		DPCD_ADDRESS_DPCD_REV -
-+		DPCD_ADDRESS_DPCD_REV];
-+
-+	ds_port.byte = dpcd_data[DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT -
-+				 DPCD_ADDRESS_DPCD_REV];
-+
-+	get_active_converter_info(ds_port.byte, link);
-+
-+	dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
-+
-+	link->dpcd_caps.allow_invalid_MSA_timing_param =
-+		down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
-+
-+	link->dpcd_caps.max_ln_count.raw = dpcd_data[
-+		DPCD_ADDRESS_MAX_LANE_COUNT - DPCD_ADDRESS_DPCD_REV];
-+
-+	max_down_spread.raw = dpcd_data[
-+		DPCD_ADDRESS_MAX_DOWNSPREAD - DPCD_ADDRESS_DPCD_REV];
-+
-+	link->reported_link_cap.lane_count =
-+		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
-+	link->reported_link_cap.link_rate = dpcd_data[
-+		DPCD_ADDRESS_MAX_LINK_RATE - DPCD_ADDRESS_DPCD_REV];
-+	link->reported_link_cap.link_spread =
-+		max_down_spread.bits.MAX_DOWN_SPREAD ?
-+		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
-+
-+	edp_config_cap.raw = dpcd_data[
-+		DPCD_ADDRESS_EDP_CONFIG_CAP - DPCD_ADDRESS_DPCD_REV];
-+	link->dpcd_caps.panel_mode_edp =
-+		edp_config_cap.bits.ALT_SCRAMBLER_RESET;
-+
-+	link->edp_revision = DPCD_EDP_REVISION_EDP_UNKNOWN;
-+
-+	/* read sink count */
-+	core_link_read_dpcd(link,
-+			DPCD_ADDRESS_SINK_COUNT,
-+			&link->dpcd_caps.sink_count.raw,
-+			sizeof(link->dpcd_caps.sink_count.raw));
-+
-+	/* Display control registers starting at DPCD 700h are only valid and
-+	 * enabled if this eDP config cap bit is set. */
-+	if (edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE) {
-+		/* Read the Panel's eDP revision at DPCD 700h. */
-+		core_link_read_dpcd(link,
-+			DPCD_ADDRESS_EDP_REV,
-+			(uint8_t *)(&link->edp_revision),
-+			sizeof(link->edp_revision));
-+	}
-+	/* TODO: Confirm if need retrieve_psr_link_cap */
-+}
-+
-+void detect_dp_sink_caps(struct core_link *link)
-+{
-+	retrieve_link_cap(link);
-+
-+	/* dc init_hw has power encoder using default
-+	 * signal for connector. For native DP, no
-+	 * need to power up encoder again. If not native
-+	 * DP, hw_init may need check signal or power up
-+	 * encoder here.
-+	 */
-+
-+	if (is_mst_supported(link)) {
-+		link->verified_link_cap = link->reported_link_cap;
-+	} else {
-+		dp_hbr_verify_link_cap(link,
-+			&link->reported_link_cap);
-+	}
-+	/* TODO save sink caps in link->sink */
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-new file mode 100644
-index 0000000..164cdeb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -0,0 +1,188 @@
-+/* Copyright 2015 Advanced Micro Devices, Inc. */
-+
-+#include "dc_services.h"
-+#include "dc.h"
-+#include "inc/core_dc.h"
-+#include "include/ddc_service_types.h"
-+#include "include/i2caux_interface.h"
-+#include "link_hwss.h"
-+#include "include/connector_interface.h"
-+#include "hw_sequencer.h"
-+#include "include/ddc_service_interface.h"
-+
-+enum dc_status core_link_read_dpcd(
-+	struct core_link* link,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t size)
-+{
-+	if (dal_ddc_service_read_dpcd_data(link->ddc, address, data, size)
-+			!= DDC_RESULT_SUCESSFULL)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status core_link_write_dpcd(
-+	struct core_link* link,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t size)
-+{
-+	if (dal_ddc_service_write_dpcd_data(link->ddc, address, data, size)
-+			!= DDC_RESULT_SUCESSFULL)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	return DC_OK;
-+}
-+
-+void dp_receiver_power_ctrl(struct core_link *link, bool on)
-+{
-+	uint8_t state;
-+
-+	state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
-+
-+	core_link_write_dpcd(link, DPCD_ADDRESS_POWER_STATE, &state,
-+			sizeof(state));
-+}
-+
-+
-+/* TODO: HBR2 need raise clock for DP link training */
-+enum dc_status dp_enable_link_phy(
-+	struct core_link *link,
-+	enum signal_type signal,
-+	enum engine_id engine,
-+	const struct link_settings *link_settings)
-+{
-+	enum dc_status status = DC_OK;
-+
-+	if (link->dc->hwss.encoder_enable_output(
-+					link->link_enc,
-+					link_settings,
-+					engine,
-+					CLOCK_SOURCE_ID_EXTERNAL,
-+					signal,
-+					COLOR_DEPTH_UNDEFINED,
-+					0) != ENCODER_RESULT_OK)
-+		status = DC_ERROR_UNEXPECTED;
-+
-+	dp_receiver_power_ctrl(link, true);
-+
-+	return status;
-+}
-+
-+void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
-+{
-+	if(!link)
-+		return;
-+
-+	if (!link->dp_wa.bits.KEEP_RECEIVER_POWERED)
-+		dp_receiver_power_ctrl(link, false);
-+
-+	link->dc->hwss.encoder_disable_output(link->link_enc, signal);
-+
-+	/* Clear current link setting.*/
-+	dc_service_memset(&link->cur_link_settings, 0,
-+			sizeof(link->cur_link_settings));
-+}
-+
-+bool dp_set_hw_training_pattern(
-+	struct core_link *link,
-+	enum hw_dp_training_pattern pattern)
-+{
-+	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
-+	struct encoder_set_dp_phy_pattern_param pattern_param = {0};
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	switch (pattern) {
-+	case HW_DP_TRAINING_PATTERN_1:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_2:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_3:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	pattern_param.dp_phy_pattern = test_pattern;
-+	pattern_param.custom_pattern = NULL;
-+	pattern_param.custom_pattern_size = 0;
-+	pattern_param.dp_panel_mode = dp_get_panel_mode(link);
-+
-+	link->ctx->dc->hwss.encoder_set_dp_phy_pattern(encoder, &pattern_param);
-+
-+	return true;
-+}
-+
-+
-+bool dp_set_hw_lane_settings(
-+	struct core_link *link,
-+	const struct link_training_settings *link_settings)
-+{
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	/* call Encoder to set lane settings */
-+	link->ctx->dc->hwss.encoder_dp_set_lane_settings(encoder, link_settings);
-+
-+	return true;
-+}
-+
-+enum dp_panel_mode dp_get_panel_mode(struct core_link *link)
-+{
-+	/* We need to explicitly check that connector
-+	 * is not DP. Some Travis_VGA get reported
-+	 * by video bios as DP.
-+	 */
-+	if (link->public.connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
-+
-+		switch (link->dpcd_caps.branch_dev_id) {
-+		case DP_BRANCH_DEVICE_ID_2:
-+			if (strncmp(
-+				link->dpcd_caps.branch_dev_name,
-+				DP_VGA_LVDS_CONVERTER_ID_2,
-+				sizeof(
-+				link->dpcd_caps.
-+				branch_dev_name)) == 0) {
-+				return DP_PANEL_MODE_SPECIAL;
-+			}
-+			break;
-+		case DP_BRANCH_DEVICE_ID_3:
-+			if (strncmp(link->dpcd_caps.branch_dev_name,
-+				DP_VGA_LVDS_CONVERTER_ID_3,
-+				sizeof(
-+				link->dpcd_caps.
-+				branch_dev_name)) == 0) {
-+				return DP_PANEL_MODE_SPECIAL;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		if (link->dpcd_caps.panel_mode_edp) {
-+			return DP_PANEL_MODE_EDP;
-+		}
-+	}
-+
-+	return DP_PANEL_MODE_DEFAULT;
-+}
-+
-+void dp_set_hw_test_pattern(
-+	struct core_link *link,
-+	enum dp_test_pattern test_pattern)
-+{
-+	struct encoder_set_dp_phy_pattern_param pattern_param = {0};
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	pattern_param.dp_phy_pattern = test_pattern;
-+	pattern_param.custom_pattern = NULL;
-+	pattern_param.custom_pattern_size = 0;
-+	pattern_param.dp_panel_mode = dp_get_panel_mode(link);
-+
-+	link->ctx->dc->hwss.encoder_set_dp_phy_pattern(encoder, &pattern_param);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-new file mode 100644
-index 0000000..5803e22
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -0,0 +1,378 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "link_encoder_types.h"
-+#include "stream_encoder_types.h"
-+
-+
-+void unreference_clock_source(
-+		struct resource_context *res_ctx,
-+		struct clock_source *clock_source)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.clk_src_count; i++) {
-+		if (res_ctx->pool.clock_sources[i] == clock_source) {
-+			res_ctx->clock_source_ref_count[i]--;
-+		}
-+	}
-+}
-+
-+void reference_clock_source(
-+		struct resource_context *res_ctx,
-+		struct clock_source *clock_source)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.clk_src_count; i++) {
-+		if (res_ctx->pool.clock_sources[i] == clock_source) {
-+			res_ctx->clock_source_ref_count[i]++;
-+		}
-+	}
-+}
-+
-+bool is_same_timing(
-+	const struct dc_crtc_timing *timing1,
-+	const struct dc_crtc_timing *timing2)
-+{
-+	return dal_memcmp(timing1, timing2, sizeof(struct dc_crtc_timing)) == 0;
-+}
-+
-+static bool is_sharable_clk_src(
-+	const struct core_stream *stream_with_clk_src,
-+	const struct core_stream *stream)
-+{
-+	enum clock_source_id id = dal_clock_source_get_id(
-+					stream_with_clk_src->clock_source);
-+
-+	if (stream_with_clk_src->clock_source == NULL)
-+		return false;
-+
-+	if (!dc_is_dp_signal(stream->signal) && id == CLOCK_SOURCE_ID_EXTERNAL)
-+		return false;
-+
-+	if(!is_same_timing(
-+		&stream_with_clk_src->public.timing, &stream->public.timing))
-+		return false;
-+
-+	return true;
-+}
-+
-+struct clock_source *find_used_clk_src_for_sharing(
-+					struct validate_context *context,
-+					struct core_stream *stream)
-+{
-+	uint8_t i, j;
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		for (j = 0; j < target->stream_count; j++)
-+		{
-+			if (target->streams[j]->clock_source == NULL)
-+				continue;
-+			if (is_sharable_clk_src(target->streams[j], stream))
-+				return target->streams[j]->clock_source;
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+static enum pixel_format convert_pixel_format_to_dalsurface(
-+		enum surface_pixel_format surface_pixel_format)
-+{
-+	enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
-+
-+	switch (surface_pixel_format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-+		dal_pixel_format = PIXEL_FORMAT_INDEX8;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+		dal_pixel_format = PIXEL_FORMAT_RGB565;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		dal_pixel_format = PIXEL_FORMAT_RGB565;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB8888;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB8888;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		dal_pixel_format = PIXEL_FORMAT_FP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		dal_pixel_format = PIXEL_FORMAT_FP16;
-+		break;
-+
-+
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+		dal_pixel_format = PIXEL_FORMAT_420BPP12;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		dal_pixel_format = PIXEL_FORMAT_420BPP12;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_422_YCb:
-+		dal_pixel_format = PIXEL_FORMAT_422BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_422_YCr:
-+		dal_pixel_format = PIXEL_FORMAT_422BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_422_CbY:
-+		dal_pixel_format = PIXEL_FORMAT_422BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_422_CrY:
-+		dal_pixel_format = PIXEL_FORMAT_422BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP32;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP32;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102:
-+		dal_pixel_format = PIXEL_FORMAT_444BPP32;
-+		break;
-+	default:
-+		dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
-+		break;
-+	}
-+	return dal_pixel_format;
-+}
-+
-+static void calculate_viewport(
-+		const struct dc_surface *surface,
-+		struct core_stream *stream)
-+{
-+	const struct rect src = surface->src_rect;
-+	const struct rect clip = surface->clip_rect;
-+	const struct rect dst = surface->dst_rect;
-+
-+	/* offset = src.ofs + (clip.ofs - dst.ofs) * scl_ratio
-+	 * num_pixels = clip.num_pix * scl_ratio
-+	 */
-+	stream->viewport.x = src.x + (clip.x - dst.x) * src.width / dst.width;
-+	stream->viewport.width = clip.width * src.width / dst.width;
-+
-+	stream->viewport.y = src.y + (clip.y - dst.y) * src.height / dst.height;
-+	stream->viewport.height = clip.height * src.height / dst.height;
-+
-+	/* Minimum viewport such that 420/422 chroma vp is non 0 */
-+	if (stream->viewport.width < 2)
-+	{
-+		stream->viewport.width = 2;
-+	}
-+	if (stream->viewport.height < 2)
-+	{
-+		stream->viewport.height = 2;
-+	}
-+}
-+
-+static void calculate_overscan(
-+		const struct dc_surface *surface,
-+		struct core_stream *stream)
-+{
-+	stream->overscan.left = stream->public.dst.x;
-+	if (stream->public.src.x < surface->clip_rect.x)
-+		stream->overscan.left += (surface->clip_rect.x
-+			- stream->public.src.x) * stream->public.dst.width
-+			/ stream->public.src.width;
-+
-+	stream->overscan.right = stream->public.timing.h_addressable
-+		- stream->public.dst.x - stream->public.dst.width;
-+	if (stream->public.src.x + stream->public.src.width
-+		> surface->clip_rect.x + surface->clip_rect.width)
-+		stream->overscan.right = stream->public.timing.h_addressable -
-+			dal_fixed31_32_floor(dal_fixed31_32_div(
-+				dal_fixed31_32_from_int(
-+						stream->viewport.width),
-+						stream->ratios.horz)) -
-+						stream->overscan.left;
-+
-+
-+	stream->overscan.top = stream->public.dst.y;
-+	if (stream->public.src.y < surface->clip_rect.y)
-+		stream->overscan.top += (surface->clip_rect.y
-+			- stream->public.src.y) * stream->public.dst.height
-+			/ stream->public.src.height;
-+
-+	stream->overscan.bottom = stream->public.timing.v_addressable
-+		- stream->public.dst.y - stream->public.dst.height;
-+	if (stream->public.src.y + stream->public.src.height
-+		> surface->clip_rect.y + surface->clip_rect.height)
-+		stream->overscan.bottom = stream->public.timing.v_addressable -
-+			dal_fixed31_32_floor(dal_fixed31_32_div(
-+				dal_fixed31_32_from_int(
-+						stream->viewport.height),
-+						stream->ratios.vert)) -
-+						stream->overscan.top;
-+
-+
-+	/* TODO: Add timing overscan to finalize overscan calculation*/
-+}
-+
-+static void calculate_scaling_ratios(
-+		const struct dc_surface *surface,
-+		struct core_stream *stream)
-+{
-+	const uint32_t in_w = stream->public.src.width;
-+	const uint32_t in_h = stream->public.src.height;
-+	const uint32_t out_w = stream->public.dst.width;
-+	const uint32_t out_h = stream->public.dst.height;
-+
-+	stream->ratios.horz = dal_fixed31_32_from_fraction(
-+					surface->src_rect.width,
-+					surface->dst_rect.width);
-+	stream->ratios.vert = dal_fixed31_32_from_fraction(
-+					surface->src_rect.height,
-+					surface->dst_rect.height);
-+
-+	if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
-+		stream->ratios.horz.value *= 2;
-+	else if (surface->stereo_format
-+					== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
-+		stream->ratios.vert.value *= 2;
-+
-+	stream->ratios.vert.value = stream->ratios.vert.value * in_h / out_h;
-+	stream->ratios.horz.value = stream->ratios.horz.value * in_w / out_w;
-+
-+	stream->ratios.horz_c = stream->ratios.horz;
-+	stream->ratios.vert_c = stream->ratios.vert;
-+
-+	if (stream->format == PIXEL_FORMAT_420BPP12) {
-+		stream->ratios.horz_c.value /= 2;
-+		stream->ratios.vert_c.value /= 2;
-+	} else if (stream->format == PIXEL_FORMAT_422BPP16) {
-+		stream->ratios.horz_c.value /= 2;
-+	}
-+}
-+
-+/*TODO: per pipe not per stream*/
-+void build_scaling_params(
-+	const struct dc_surface *surface,
-+	struct core_stream *stream)
-+{
-+	/* Important: scaling ratio calculation requires pixel format,
-+	 * overscan calculation requires scaling ratios and viewport
-+	 * and lb depth/taps calculation requires overscan. Call sequence
-+	 * is therefore important */
-+	stream->format = convert_pixel_format_to_dalsurface(surface->format);
-+
-+	calculate_viewport(surface, stream);
-+
-+	calculate_scaling_ratios(surface, stream);
-+
-+	calculate_overscan(surface, stream);
-+
-+	/* Check if scaling is required update taps if not */
-+	if (dal_fixed31_32_u2d19(stream->ratios.horz) == 1 << 19)
-+		stream->taps.h_taps = 1;
-+	else
-+		stream->taps.h_taps = surface->scaling_quality.h_taps;
-+
-+	if (dal_fixed31_32_u2d19(stream->ratios.horz_c) == 1 << 19)
-+		stream->taps.h_taps_c = 1;
-+	else
-+		stream->taps.h_taps_c = surface->scaling_quality.h_taps_c;
-+
-+	if (dal_fixed31_32_u2d19(stream->ratios.vert) == 1 << 19)
-+		stream->taps.v_taps = 1;
-+	else
-+		stream->taps.v_taps = surface->scaling_quality.v_taps;
-+
-+	if (dal_fixed31_32_u2d19(stream->ratios.vert_c) == 1 << 19)
-+		stream->taps.v_taps_c = 1;
-+	else
-+		stream->taps.v_taps_c = surface->scaling_quality.v_taps_c;
-+}
-+
-+void build_scaling_params_for_context(
-+	const struct dc *dc,
-+	struct validate_context *context)
-+{
-+	uint8_t i, j, k;
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+		for (j = 0; j < target->status.surface_count; j++) {
-+			const struct dc_surface *surface = target->status.surfaces[j];
-+			for (k = 0; k < target->stream_count; k++) {
-+				struct core_stream *stream = target->streams[k];
-+
-+				build_scaling_params(surface, stream);
-+			}
-+		}
-+	}
-+}
-+
-+bool logical_attach_surfaces_to_target(
-+		struct dc_surface *surfaces[],
-+		uint8_t surface_count,
-+		struct dc_target *dc_target)
-+{
-+	uint8_t i;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+
-+	if (target->status.surface_count >= MAX_SURFACE_NUM) {
-+		dal_error("Surface: this target has too many surfaces!\n");
-+		return false;
-+	}
-+
-+	for (i = 0; i < target->status.surface_count; i++)
-+		dc_surface_release(target->status.surfaces[i]);
-+
-+	for (i = 0; i < surface_count; i++) {
-+		struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
-+		surface->status.dc_target = &target->public;
-+		target->status.surfaces[i] = surfaces[i];
-+		dc_surface_retain(target->status.surfaces[i]);
-+	}
-+	target->status.surface_count = surface_count;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-new file mode 100644
-index 0000000..3d537d5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-@@ -0,0 +1,118 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+#include "dc_helpers.h"
-+#include "core_types.h"
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+
-+struct sink {
-+	struct core_sink protected;
-+	int ref_count;
-+};
-+
-+#define DC_SINK_TO_SINK(dc_sink) \
-+			container_of(dc_sink, struct sink, protected.public)
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+
-+static void destruct(struct sink *sink)
-+{
-+
-+}
-+
-+static bool construct(struct sink *sink, const struct sink_init_data *init_params)
-+{
-+
-+	struct core_link *core_link = DC_LINK_TO_LINK(init_params->link);
-+
-+	sink->protected.public.sink_signal = init_params->sink_signal;
-+	sink->protected.link = core_link;
-+	sink->protected.ctx = core_link->ctx;
-+	sink->protected.dongle_max_pix_clk = init_params->dongle_max_pix_clk;
-+	sink->protected.converter_disable_audio =
-+			init_params->converter_disable_audio;
-+
-+	return true;
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+void dc_sink_retain(const struct dc_sink *dc_sink)
-+{
-+	struct sink *sink = DC_SINK_TO_SINK(dc_sink);
-+
-+	++sink->ref_count;
-+}
-+
-+void dc_sink_release(const struct dc_sink *dc_sink)
-+{
-+	struct core_sink *core_sink = DC_SINK_TO_CORE(dc_sink);
-+	struct sink *sink = DC_SINK_TO_SINK(dc_sink);
-+
-+	--sink->ref_count;
-+
-+	if (sink->ref_count == 0) {
-+		destruct(sink);
-+		dc_service_free(core_sink->ctx, sink);
-+	}
-+}
-+
-+
-+/*******************************************************************************
-+ * Protected functions - visible only inside of DC (not visible in DM)
-+ ******************************************************************************/
-+
-+struct dc_sink *sink_create(const struct sink_init_data *init_params)
-+{
-+	struct core_link *core_link = DC_LINK_TO_LINK(init_params->link);
-+
-+	struct sink *sink = dc_service_alloc(core_link->ctx, sizeof(*sink));
-+
-+	if (NULL == sink)
-+		goto alloc_fail;
-+
-+	if (false == construct(sink, init_params))
-+		goto construct_fail;
-+
-+	/* TODO should we move this outside to where the assignment actually happens? */
-+	dc_sink_retain(&sink->protected.public);
-+
-+	return &sink->protected.public;
-+
-+construct_fail:
-+	dc_service_free(core_link->ctx, sink);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-new file mode 100644
-index 0000000..1a7bf50
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -0,0 +1,172 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "resource.h"
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+
-+struct stream {
-+	struct core_stream protected;
-+	int ref_count;
-+};
-+
-+#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected.public)
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+
-+static void build_bit_depth_reduction_params(
-+		struct bit_depth_reduction_params *fmt_bit_depth)
-+{
-+	/*TODO: Need to un-hardcode, refer to function with same name
-+	 * in dal2 hw_sequencer*/
-+
-+	fmt_bit_depth->flags.TRUNCATE_ENABLED = 0;
-+	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 0;
-+	fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 0;
-+	fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
-+
-+	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
-+	/* frame random is on by default */
-+	fmt_bit_depth->flags.FRAME_RANDOM = 1;
-+	/* apply RGB dithering */
-+	fmt_bit_depth->flags.RGB_RANDOM = true;
-+
-+	return;
-+
-+}
-+
-+static void setup_pixel_encoding(
-+	struct clamping_and_pixel_encoding_params *clamping)
-+{
-+	/*TODO: Need to un-hardcode, refer to function with same name
-+		 * in dal2 hw_sequencer*/
-+
-+	clamping->pixel_encoding = PIXEL_ENCODING_RGB;
-+
-+	return;
-+}
-+
-+static bool construct(struct core_stream *stream,
-+	const struct dc_sink *dc_sink_data)
-+{
-+	uint32_t i = 0;
-+
-+	stream->sink = DC_SINK_TO_CORE(dc_sink_data);
-+	stream->ctx = stream->sink->ctx;
-+	stream->public.sink = dc_sink_data;
-+
-+	dc_sink_retain(dc_sink_data);
-+
-+	build_bit_depth_reduction_params(&stream->fmt_bit_depth);
-+	setup_pixel_encoding(&stream->clamping);
-+
-+	/* Copy audio modes */
-+	/* TODO - Remove this translation */
-+	for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
-+	{
-+		stream->public.audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
-+		stream->public.audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
-+		stream->public.audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
-+		stream->public.audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
-+	}
-+	stream->public.audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
-+	stream->public.audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
-+	stream->public.audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
-+	dc_service_memmove(
-+		stream->public.audio_info.display_name,
-+		dc_sink_data->edid_caps.display_name,
-+		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
-+	stream->public.audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
-+	stream->public.audio_info.product_id = dc_sink_data->edid_caps.product_id;
-+	stream->public.audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
-+
-+	/* TODO - Unhardcode port_id */
-+	stream->public.audio_info.port_id[0] = 0x5558859e;
-+	stream->public.audio_info.port_id[1] = 0xd989449;
-+
-+	/* EDID CAP translation for HDMI 2.0 */
-+	stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
-+	return true;
-+}
-+
-+static void destruct(struct core_stream *stream)
-+{
-+	dc_sink_release(&stream->sink->public);
-+}
-+
-+void dc_stream_retain(struct dc_stream *dc_stream)
-+{
-+	struct stream *stream = DC_STREAM_TO_STREAM(dc_stream);
-+	stream->ref_count++;
-+}
-+
-+void dc_stream_release(struct dc_stream *public)
-+{
-+	struct stream *stream = DC_STREAM_TO_STREAM(public);
-+	struct core_stream *protected = DC_STREAM_TO_CORE(public);
-+	struct dc_context *ctx = protected->ctx;
-+	stream->ref_count--;
-+
-+	if (stream->ref_count == 0) {
-+		destruct(protected);
-+		dc_service_free(ctx, stream);
-+	}
-+}
-+
-+struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink)
-+{
-+	struct core_sink *sink = DC_SINK_TO_CORE(dc_sink);
-+	struct stream *stream;
-+
-+	if (sink == NULL)
-+		goto alloc_fail;
-+
-+	stream = dc_service_alloc(sink->ctx, sizeof(struct stream));
-+
-+	if (NULL == stream)
-+		goto alloc_fail;
-+
-+	if (false == construct(&stream->protected, dc_sink))
-+			goto construct_fail;
-+
-+	dc_stream_retain(&stream->protected.public);
-+
-+	return &stream->protected.public;
-+
-+construct_fail:
-+	dc_service_free(sink->ctx, stream);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-new file mode 100644
-index 0000000..41a5feb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -0,0 +1,124 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/* DC interface (public) */
-+#include "dc_services.h"
-+#include "dc.h"
-+
-+/* DC core (private) */
-+#include "core_dc.h"
-+#include "adjustment_types.h"
-+
-+
-+/*******************************************************************************
-+ * Private structures
-+ ******************************************************************************/
-+struct surface {
-+	struct core_surface protected;
-+	enum dc_irq_source irq_source;
-+	int ref_count;
-+};
-+
-+#define DC_SURFACE_TO_SURFACE(dc_surface) container_of(dc_surface, struct surface, protected.public)
-+#define CORE_SURFACE_TO_SURFACE(core_surface) container_of(core_surface, struct surface, protected)
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+static bool construct(struct dc_context *ctx, struct surface *surface)
-+{
-+	uint32_t i;
-+	struct gamma_ramp *gamma =
-+			&surface->protected.public.gamma_correction;
-+
-+	/* construct gamma default value. */
-+	for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
-+		gamma->gamma_ramp_rgb256x3x16.red[i] =
-+				(unsigned short) (i << 8);
-+		gamma->gamma_ramp_rgb256x3x16.green[i] =
-+				(unsigned short) (i << 8);
-+		gamma->gamma_ramp_rgb256x3x16.blue[i] =
-+				(unsigned short) (i << 8);
-+	}
-+	gamma->type = GAMMA_RAMP_TYPE_RGB256;
-+	gamma->size = sizeof(gamma->gamma_ramp_rgb256x3x16);
-+
-+	surface->protected.ctx = ctx;
-+	return true;
-+}
-+
-+static void destruct(struct surface *surface)
-+{
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+void enable_surface_flip_reporting(struct dc_surface *dc_surface,
-+		uint32_t controller_id)
-+{
-+	struct surface *surface = DC_SURFACE_TO_SURFACE(dc_surface);
-+	surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
-+	/*register_flip_interrupt(surface);*/
-+}
-+
-+struct dc_surface *dc_create_surface(const struct dc *dc)
-+{
-+	struct surface *surface = dc_service_alloc(dc->ctx, sizeof(*surface));
-+
-+	if (NULL == surface)
-+		goto alloc_fail;
-+
-+	if (false == construct(dc->ctx, surface))
-+		goto construct_fail;
-+
-+	dc_surface_retain(&surface->protected.public);
-+
-+	return &surface->protected.public;
-+
-+construct_fail:
-+	dc_service_free(dc->ctx, surface);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+void dc_surface_retain(const struct dc_surface *dc_surface)
-+{
-+	struct surface *surface = DC_SURFACE_TO_SURFACE(dc_surface);
-+
-+	++surface->ref_count;
-+}
-+
-+void dc_surface_release(const struct dc_surface *dc_surface)
-+{
-+	struct surface *surface = DC_SURFACE_TO_SURFACE(dc_surface);
-+	--surface->ref_count;
-+
-+	if (surface->ref_count == 0) {
-+		destruct(surface);
-+		dc_service_free(surface->protected.ctx, surface);
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-new file mode 100644
-index 0000000..9243c01
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -0,0 +1,473 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+#include "resource.h"
-+
-+#define COEFF_RANGE	3
-+#define REGAMMA_COEFF_A0	31308
-+#define REGAMMA_COEFF_A1	12920
-+#define REGAMMA_COEFF_A2	55
-+#define REGAMMA_COEFF_A3	55
-+#define REGAMMA_COEFF_GAMMA	2400
-+
-+struct target {
-+	struct core_target protected;
-+	int ref_count;
-+};
-+
-+#define DC_TARGET_TO_TARGET(dc_target) \
-+	container_of(dc_target, struct target, protected.public)
-+#define CORE_TARGET_TO_TARGET(core_target) \
-+	container_of(core_target, struct target, protected)
-+
-+static void construct(
-+	struct core_target *target,
-+	struct dc_context *ctx,
-+	struct dc_stream *dc_streams[],
-+	uint8_t stream_count)
-+{
-+	uint8_t i;
-+	for (i = 0; i < stream_count; i++) {
-+		target->streams[i] = DC_STREAM_TO_CORE(dc_streams[i]);
-+		target->public.streams[i] = dc_streams[i];
-+		dc_stream_retain(dc_streams[i]);
-+	}
-+
-+	target->ctx = ctx;
-+	target->stream_count = stream_count;
-+}
-+
-+static void destruct(struct core_target *core_target)
-+{
-+	int i;
-+
-+	for (i = 0; i < core_target->status.surface_count; i++) {
-+		dc_surface_release(core_target->status.surfaces[i]);
-+		core_target->status.surfaces[i] = 0;
-+	}
-+	for (i = 0; i < core_target->stream_count; i++) {
-+		dc_stream_release(&core_target->streams[i]->public);
-+		core_target->streams[i] = 0;
-+	}
-+}
-+
-+void dc_target_retain(struct dc_target *dc_target)
-+{
-+	struct target *target = DC_TARGET_TO_TARGET(dc_target);
-+
-+	target->ref_count++;
-+}
-+
-+void dc_target_release(struct dc_target *dc_target)
-+{
-+	struct target *target = DC_TARGET_TO_TARGET(dc_target);
-+	struct core_target *protected = DC_TARGET_TO_CORE(dc_target);
-+
-+	ASSERT(target->ref_count > 0);
-+	target->ref_count--;
-+	if (target->ref_count == 0) {
-+		destruct(protected);
-+		dc_service_free(protected->ctx, target);
-+	}
-+}
-+
-+const struct dc_target_status *dc_target_get_status(
-+					const struct dc_target* dc_target)
-+{
-+	struct core_target* target = DC_TARGET_TO_CORE(dc_target);
-+	return &target->status;
-+}
-+
-+struct dc_target *dc_create_target_for_streams(
-+		struct dc_stream *dc_streams[],
-+		uint8_t stream_count)
-+{
-+	struct core_stream *stream;
-+	struct target *target;
-+
-+	if (0 == stream_count)
-+		goto target_alloc_fail;
-+
-+	stream = DC_STREAM_TO_CORE(dc_streams[0]);
-+
-+	target = dc_service_alloc(stream->ctx, sizeof(struct target));
-+
-+	if (NULL == target)
-+		goto target_alloc_fail;
-+
-+	construct(&target->protected, stream->ctx, dc_streams, stream_count);
-+
-+	dc_target_retain(&target->protected.public);
-+
-+	return &target->protected.public;
-+
-+
-+target_alloc_fail:
-+	return NULL;
-+}
-+
-+static void build_gamma_params(
-+		enum pixel_format pixel_format,
-+		struct gamma_parameters *gamma_param)
-+{
-+	uint32_t i;
-+
-+	/* translate parameters */
-+	gamma_param->surface_pixel_format = pixel_format;
-+
-+	gamma_param->regamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_SW;
-+	gamma_param->degamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_SW;
-+
-+	gamma_param->selected_gamma_lut = GRAPHICS_GAMMA_LUT_LEGACY;
-+
-+	/* TODO support non-legacy gamma */
-+	gamma_param->disable_adjustments = false;
-+	gamma_param->flag.bits.config_is_changed = 0;
-+	gamma_param->flag.bits.regamma_update = 1;
-+	gamma_param->flag.bits.gamma_update = 1;
-+
-+	/* Set regamma */
-+	gamma_param->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB = 0;
-+	gamma_param->regamma.features.bits.OVERLAY_DEGAMMA_SRGB = 0;
-+	gamma_param->regamma.features.bits.GAMMA_RAMP_ARRAY = 0;
-+	gamma_param->regamma.features.bits.APPLY_DEGAMMA = 0;
-+
-+	for (i = 0; i < COEFF_RANGE; i++) {
-+		gamma_param->regamma.gamma_coeff.a0[i] = REGAMMA_COEFF_A0;
-+		gamma_param->regamma.gamma_coeff.a1[i] = REGAMMA_COEFF_A1;
-+		gamma_param->regamma.gamma_coeff.a2[i] = REGAMMA_COEFF_A2;
-+		gamma_param->regamma.gamma_coeff.a3[i] = REGAMMA_COEFF_A3;
-+		gamma_param->regamma.gamma_coeff.gamma[i] = REGAMMA_COEFF_GAMMA;
-+	}
-+}
-+
-+
-+static bool program_gamma(
-+		struct dc_context *ctx,
-+		struct dc_surface *surface,
-+		struct input_pixel_processor *ipp,
-+		struct output_pixel_processor *opp)
-+{
-+	struct gamma_parameters *gamma_param;
-+	bool result= false;
-+
-+	gamma_param = dc_service_alloc(ctx, sizeof(struct gamma_parameters));
-+
-+	if (!gamma_param)
-+		goto gamma_param_fail;
-+
-+	build_gamma_params(surface->format, gamma_param);
-+
-+	result = ctx->dc->hwss.set_gamma_ramp(ipp, opp,
-+			&surface->gamma_correction,
-+			gamma_param);
-+
-+	dc_service_free(ctx, gamma_param);
-+
-+gamma_param_fail:
-+	return result;
-+}
-+
-+bool dc_commit_surfaces_to_target(
-+		struct dc *dc,
-+		struct dc_surface *surfaces[],
-+		uint8_t surface_count,
-+		struct dc_target *dc_target)
-+
-+{
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	bool need_blanking = (target->status.surface_count == 0);
-+
-+	dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_INTERFACE_TRACE,
-+				LOG_MINOR_COMPONENT_DC,
-+				"%s: commit %d surfaces to target 0x%x",
-+				__func__,
-+				surface_count,
-+				dc_target);
-+
-+
-+	if (!logical_attach_surfaces_to_target(
-+						surfaces,
-+						surface_count,
-+						dc_target)) {
-+		BREAK_TO_DEBUGGER();
-+		goto unexpected_fail;
-+	}
-+
-+	for (i = 0; i < surface_count; i++)
-+		for (j = 0; j < target->stream_count; j++)
-+			build_scaling_params(surfaces[i], target->streams[j]);
-+
-+	if (dc->hwss.validate_bandwidth(dc, &dc->current_context) != DC_OK) {
-+		BREAK_TO_DEBUGGER();
-+		goto unexpected_fail;
-+	}
-+
-+	dc->hwss.program_bw(dc, &dc->current_context);
-+
-+	if (need_blanking)
-+		dc_target_disable_memory_requests(dc_target);
-+
-+	for (i = 0; i < surface_count; i++) {
-+		struct dc_surface *surface = surfaces[i];
-+		struct core_surface *core_surface = DC_SURFACE_TO_CORE(surface);
-+
-+		dal_logger_write(dc->ctx->logger,
-+					LOG_MAJOR_INTERFACE_TRACE,
-+					LOG_MINOR_COMPONENT_DC,
-+					"0x%x:",
-+					surface);
-+		dc_surface_retain(surface);
-+
-+		program_gamma(dc->ctx, surface,
-+				target->streams[0]->ipp,
-+				target->streams[0]->opp);
-+
-+		dc->hwss.set_plane_config(
-+			core_surface,
-+			target);
-+
-+		dc->hwss.update_plane_address(core_surface, target);
-+	}
-+
-+	if (surface_count > 0 && need_blanking)
-+		dc_target_enable_memory_requests(dc_target);
-+
-+	return true;
-+
-+unexpected_fail:
-+	for (i = 0; i < surface_count; i++) {
-+		target->status.surfaces[i] = NULL;
-+	}
-+	target->status.surface_count = 0;
-+
-+	return false;
-+}
-+
-+bool dc_target_is_connected_to_sink(
-+		const struct dc_target * dc_target,
-+		const struct dc_sink *dc_sink)
-+{
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	uint8_t i;
-+	for (i = 0; i < target->stream_count; i++) {
-+		if (&target->streams[i]->sink->public == dc_sink)
-+			return true;
-+	}
-+	return false;
-+}
-+
-+void dc_target_enable_memory_requests(struct dc_target *target)
-+{
-+	uint8_t i;
-+	struct core_target *core_target = DC_TARGET_TO_CORE(target);
-+	for (i = 0; i < core_target->stream_count; i++) {
-+	struct timing_generator *tg = core_target->streams[i]->tg;
-+		if (false == core_target->ctx->dc->hwss.enable_memory_requests(tg)) {
-+			dal_error("DC: failed to unblank crtc!\n");
-+			BREAK_TO_DEBUGGER();
-+		}
-+	}
-+}
-+
-+void dc_target_disable_memory_requests(struct dc_target *target)
-+{
-+	uint8_t i;
-+	struct core_target *core_target = DC_TARGET_TO_CORE(target);
-+	for (i = 0; i < core_target->stream_count; i++) {
-+	struct timing_generator *tg = core_target->streams[i]->tg;
-+
-+		if (NULL == tg) {
-+			dal_error("DC: timing generator is NULL!\n");
-+			BREAK_TO_DEBUGGER();
-+			continue;
-+		}
-+
-+		if (false == core_target->ctx->dc->hwss.disable_memory_requests(tg)) {
-+			dal_error("DC: failed to blank crtc!\n");
-+			BREAK_TO_DEBUGGER();
-+		}
-+	}
-+}
-+
-+/**
-+ * Update the cursor attributes and set cursor surface address
-+ */
-+bool dc_target_set_cursor_attributes(
-+	struct dc_target *dc_target,
-+	const struct dc_cursor_attributes *attributes)
-+{
-+	struct core_target *core_target;
-+	struct input_pixel_processor *ipp;
-+
-+	if (NULL == dc_target) {
-+		dal_error("DC: dc_target is NULL!\n");
-+			return false;
-+
-+	}
-+
-+	core_target = DC_TARGET_TO_CORE(dc_target);
-+	ipp = core_target->streams[0]->ipp;
-+
-+	if (NULL == ipp) {
-+		dal_error("DC: input pixel processor is NULL!\n");
-+		return false;
-+	}
-+
-+	if (true == core_target->ctx->dc->hwss.cursor_set_attributes(ipp, attributes))
-+		return true;
-+
-+	return false;
-+}
-+
-+bool dc_target_set_cursor_position(
-+	struct dc_target *dc_target,
-+	const struct dc_cursor_position *position)
-+{
-+	struct core_target *core_target;
-+	struct input_pixel_processor *ipp;
-+
-+	if (NULL == dc_target) {
-+		dal_error("DC: dc_target is NULL!\n");
-+		return false;
-+	}
-+
-+	if (NULL == position) {
-+		dal_error("DC: cursor position is NULL!\n");
-+		return false;
-+	}
-+
-+	core_target = DC_TARGET_TO_CORE(dc_target);
-+	ipp = core_target->streams[0]->ipp;
-+
-+	if (NULL == ipp) {
-+		dal_error("DC: input pixel processor is NULL!\n");
-+		return false;
-+	}
-+
-+
-+	if (true == core_target->ctx->dc->hwss.cursor_set_position(ipp, position))
-+		return true;
-+
-+	return false;
-+}
-+
-+/* TODO: #flip temporary to make flip work */
-+uint8_t dc_target_get_link_index(const struct dc_target *dc_target)
-+{
-+	const struct core_target *target = CONST_DC_TARGET_TO_CORE(dc_target);
-+
-+	return target->streams[0]->sink->link->link_index;
-+}
-+
-+uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
-+{
-+	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
-+	struct timing_generator *tg = core_target->streams[0]->tg;
-+
-+	return core_target->ctx->dc->hwss.get_vblank_counter(tg);
-+}
-+
-+enum dc_irq_source dc_target_get_irq_src(
-+	const struct dc_target *dc_target, const enum irq_type irq_type)
-+{
-+	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
-+
-+	/* #TODO - Remove the assumption that the controller is always in the
-+	 * first stream of a core target */
-+	uint8_t controller_idx = core_target->streams[0]->controller_idx;
-+
-+	/* Get controller id */
-+	enum controller_id crtc_id = controller_idx + 1;
-+
-+	/* Calculate controller offset */
-+	unsigned int offset = crtc_id - CONTROLLER_ID_D0;
-+	unsigned int base = irq_type;
-+
-+	/* Calculate irq source */
-+	enum dc_irq_source src = base + offset;
-+
-+	return src;
-+}
-+
-+void dc_target_log(
-+	const struct dc_target *dc_target,
-+	struct dal_logger *dal_logger,
-+	enum log_major log_major,
-+	enum log_minor log_minor)
-+{
-+	int i;
-+
-+	const struct core_target *core_target =
-+			CONST_DC_TARGET_TO_CORE(dc_target);
-+
-+	dal_logger_write(dal_logger,
-+			log_major,
-+			log_minor,
-+			"core_target 0x%x: surface_count=%d, stream_count=%d",
-+			core_target,
-+			core_target->status.surface_count,
-+			core_target->stream_count);
-+
-+	for (i = 0; i < core_target->stream_count; i++) {
-+		const struct core_stream *core_stream = core_target->streams[i];
-+
-+		dal_logger_write(dal_logger,
-+			log_major,
-+			log_minor,
-+			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;",
-+			core_stream,
-+			core_stream->public.src.x,
-+			core_stream->public.src.y,
-+			core_stream->public.src.width,
-+			core_stream->public.src.height,
-+			core_stream->public.dst.x,
-+			core_stream->public.dst.y,
-+			core_stream->public.dst.width,
-+			core_stream->public.dst.height);
-+		dal_logger_write(dal_logger,
-+			log_major,
-+			log_minor,
-+			"\tpix_clk_khz: %d, h_total: %d, v_total: %d",
-+			core_stream->public.timing.pix_clk_khz,
-+			core_stream->public.timing.h_total,
-+			core_stream->public.timing.v_total);
-+		dal_logger_write(dal_logger,
-+			log_major,
-+			log_minor,
-+			"\tsink name: %s, serial: %d",
-+			core_stream->sink->public.edid_caps.display_name,
-+			core_stream->sink->public.edid_caps.serial_number);
-+		dal_logger_write(dal_logger,
-+			log_major,
-+			log_minor,
-+			"\tconnector: %d",
-+			core_stream->sink->link->connector_index);
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-new file mode 100644
-index 0000000..1db9395
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -0,0 +1,440 @@
-+/*
-+ * Copyright 2012-14 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_INTERFACE_H_
-+#define DC_INTERFACE_H_
-+
-+#include "dc_types.h"
-+/* TODO: We should not include audio_interface.h here. Maybe just define
-+ * struct audio_info here */
-+#include "audio_interface.h"
-+#include "logger_types.h"
-+
-+#define MAX_SINKS_PER_LINK 4
-+
-+/*******************************************************************************
-+ * Display Core Interfaces
-+ ******************************************************************************/
-+struct dc_init_data {
-+	struct dc_context *ctx;
-+	struct adapter_service *adapter_srv;
-+};
-+
-+struct dc_caps {
-+    uint32_t max_targets;
-+    uint32_t max_links;
-+    uint32_t max_audios;
-+};
-+
-+void dc_get_caps(const struct dc *dc, struct dc_caps *caps);
-+
-+struct dc *dc_create(const struct dal_init_data *init_params);
-+void dc_destroy(struct dc **dc);
-+
-+/*******************************************************************************
-+ * Surface Interfaces
-+ ******************************************************************************/
-+
-+struct dc_surface {
-+	bool enabled;
-+	bool flip_immediate;
-+	struct dc_plane_address address;
-+
-+	struct scaling_taps scaling_quality;
-+	struct rect src_rect;
-+	struct rect dst_rect;
-+	struct rect clip_rect;
-+
-+	union plane_size plane_size;
-+	union plane_tiling_info tiling_info;
-+	struct plane_colorimetry colorimetry;
-+
-+	enum surface_pixel_format format;
-+	enum dc_rotation_angle rotation;
-+	enum plane_stereo_format stereo_format;
-+
-+	struct gamma_ramp gamma_correction;
-+};
-+
-+/*
-+ * This structure is filled in by dc_surface_get_status and contains
-+ * the last requested address and the currently active address so the called
-+ * can determine if there are any outstanding flips
-+ */
-+struct dc_surface_status {
-+	struct dc_plane_address requested_address;
-+	struct dc_plane_address current_address;
-+	const struct dc_target *dc_target;
-+};
-+
-+/*
-+ * Create a new surface with default parameters;
-+ */
-+struct dc_surface *dc_create_surface(const struct dc *dc);
-+const struct dc_surface_status* dc_surface_get_status(
-+						struct dc_surface *dc_surface);
-+
-+void dc_surface_retain(const struct dc_surface *dc_surface);
-+void dc_surface_release(const struct dc_surface *dc_surface);
-+
-+/*
-+ * This structure holds a surface address.  There could be multiple addresses
-+ * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
-+ * as frame durations and DCC format can also be set.
-+ */
-+struct dc_flip_addrs {
-+	struct dc_plane_address address;
-+
-+	/* TODO: DCC format info */
-+	/* TODO: add flip duration for FreeSync */
-+};
-+
-+/*
-+ * Optimized flip address update function.
-+ *
-+ * After this call:
-+ *   Surface addresses and flip attributes are programmed.
-+ *   Surface flip occur at next configured time (h_sync or v_sync flip)
-+ */
-+void dc_flip_surface_addrs(struct dc* dc,
-+		const struct dc_surface *const surfaces[],
-+		struct dc_flip_addrs flip_addrs[],
-+		uint32_t count);
-+
-+/*
-+ * Set up surface attributes and associate to a target
-+ * The surfaces parameter is an absolute set of all surface active for the target.
-+ * If no surfaces are provided, the target will be blanked; no memory read.
-+ * Any flip related attribute changes must be done through this interface.
-+ *
-+ * After this call:
-+ *   Surfaces attributes are programmed and configured to be composed into target.
-+ *   This does not trigger a flip.  No surface address is programmed.
-+ */
-+bool dc_commit_surfaces_to_target(
-+		struct dc *dc,
-+		struct dc_surface *dc_surfaces[],
-+		uint8_t surface_count,
-+		struct dc_target *dc_target);
-+
-+/*******************************************************************************
-+ * Target Interfaces
-+ ******************************************************************************/
-+#define MAX_STREAM_NUM 1
-+
-+struct dc_target {
-+	uint32_t temp;
-+	const struct dc_stream *streams[MAX_STREAM_NUM];
-+};
-+
-+/*
-+ * Target status is returned from dc_target_get_status in order to get the
-+ * the IRQ source, current frame counter and currently attached surfaces.
-+ */
-+struct dc_target_status {
-+	enum dc_irq_source page_flip_src;
-+	enum dc_irq_source v_update_src;
-+	uint32_t cur_frame_count;
-+	const struct dc_surface *surfaces[MAX_SURFACE_NUM];
-+	uint8_t surface_count;
-+};
-+
-+struct dc_target *dc_create_target_for_streams(
-+		struct dc_stream *dc_streams[],
-+		uint8_t stream_count);
-+
-+/*
-+ * Get the current target status.
-+ */
-+const struct dc_target_status *dc_target_get_status(
-+					const struct dc_target* dc_target);
-+
-+void dc_target_retain(struct dc_target *dc_target);
-+void dc_target_release(struct dc_target *dc_target);
-+void dc_target_log(
-+	const struct dc_target *dc_target,
-+	struct dal_logger *dal_logger,
-+	enum log_major log_major,
-+	enum log_minor log_minor);
-+
-+uint8_t dc_get_current_target_count(const struct dc *dc);
-+struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i);
-+
-+bool dc_target_is_connected_to_sink(
-+		const struct dc_target *dc_target,
-+		const struct dc_sink *dc_sink);
-+
-+uint8_t dc_target_get_link_index(const struct dc_target *dc_target);
-+uint8_t dc_target_get_controller_id(const struct dc_target *dc_target);
-+
-+uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
-+enum dc_irq_source dc_target_get_irq_src(
-+	const struct dc_target *dc_target, const enum irq_type irq_type);
-+
-+void dc_target_enable_memory_requests(struct dc_target *target);
-+void dc_target_disable_memory_requests(struct dc_target *target);
-+
-+/*
-+ * Structure to store surface/target associations for validation
-+ */
-+struct dc_validation_set {
-+	const struct dc_target *target;
-+	const struct dc_surface *surfaces[4];
-+	uint8_t surface_count;
-+};
-+
-+/*
-+ * This function takes a set of resources and checks that they are cofunctional.
-+ *
-+ * After this call:
-+ *   No hardware is programmed for call.  Only validation is done.
-+ */
-+bool dc_validate_resources(
-+		const struct dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count);
-+
-+/*
-+ * Set up streams and links associated to targets to drive sinks
-+ * The targets parameter is an absolute set of all active targets.
-+ *
-+ * After this call:
-+ *   Phy, Encoder, Timing Generator are programmed and enabled.
-+ *   New targets are enabled with blank stream; no memory read.
-+ */
-+bool dc_commit_targets(
-+		struct dc *dc,
-+		struct dc_target *targets[],
-+		uint8_t target_count);
-+
-+/*******************************************************************************
-+ * Stream Interfaces
-+ ******************************************************************************/
-+struct dc_stream {
-+	const struct dc_sink *sink;
-+	struct dc_crtc_timing timing;
-+
-+	struct rect src; /* viewport in target space*/
-+	struct rect dst; /* stream addressable area */
-+
-+	struct audio_info audio_info;
-+
-+	/* TODO: dithering */
-+	/* TODO: transfer function (CSC/regamma/gamut remap) */
-+	/* TODO: custom INFO packets */
-+	/* TODO: DRR/Freesync parameters */
-+	/* TODO: ABM info (DMCU) */
-+	/* TODO: PSR info */
-+	/* TODO: CEA VIC */
-+};
-+
-+/**
-+ * Create a new default stream for the requested sink
-+ */
-+struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink);
-+
-+void dc_stream_retain(struct dc_stream *dc_stream);
-+void dc_stream_release(struct dc_stream *dc_stream);
-+
-+/*******************************************************************************
-+ * Link Interfaces
-+ ******************************************************************************/
-+
-+/*
-+ * A link contains one or more sinks and their connected status.
-+ * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
-+ */
-+struct dc_link {
-+	const struct dc_sink *sink[MAX_SINKS_PER_LINK]; /* TODO: multiple sink support for MST */
-+	unsigned int sink_count;
-+	enum dc_connection_type type;
-+	enum signal_type connector_signal;
-+	enum dc_irq_source irq_source_hpd;
-+	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
-+};
-+
-+/*
-+ * Return an enumerated dc_link.  dc_link order is constant and determined at
-+ * boot time.  They cannot be created or destroyed.
-+ * Use dc_get_caps() to get number of links.
-+ */
-+const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
-+
-+/* Return id of physical connector represented by a dc_link at link_index.*/
-+const struct graphics_object_id dc_get_link_id_at_index(
-+		struct dc *dc, uint32_t link_index);
-+
-+/* Set backlight level of an embedded panel (eDP, LVDS). */
-+bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level);
-+
-+/* Request DC to detect if there is a Panel connected. */
-+void dc_link_detect(const struct dc_link *dc_link);
-+
-+/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
-+ * Return:
-+ * true - Downstream port status changed. DM should call DC to do the
-+ * detection.
-+ * false - no change in Downstream port status. No further action required
-+ * from DM. */
-+bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link);
-+
-+bool dc_link_add_sink(
-+		struct dc_link *link,
-+		struct dc_sink *sink
-+		);
-+
-+void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink);
-+
-+/*******************************************************************************
-+ * Sink Interfaces - A sink corresponds to a display output device
-+ ******************************************************************************/
-+
-+/*
-+ * The sink structure contains EDID and other display device properties
-+ */
-+struct dc_sink {
-+	enum signal_type sink_signal;
-+	struct dc_edid dc_edid; /* raw edid */
-+	struct dc_edid_caps edid_caps; /* parse display caps */
-+};
-+
-+void dc_sink_retain(const struct dc_sink *sink);
-+void dc_sink_release(const struct dc_sink *sink);
-+
-+const struct audio **dc_get_audios(struct dc *dc);
-+
-+struct sink_init_data {
-+	enum signal_type sink_signal;
-+	struct dc_link *link;
-+	uint32_t dongle_max_pix_clk;
-+	bool converter_disable_audio;
-+};
-+
-+struct dc_sink *sink_create(const struct sink_init_data *init_params);
-+
-+
-+/*******************************************************************************
-+ * Cursor interfaces - To manages the cursor within a target
-+ ******************************************************************************/
-+struct dc_cursor {
-+	struct dc_plane_address address;
-+	struct dc_cursor_attributes attributes;
-+};
-+
-+/*
-+ * Create a new cursor with default values for a given target.
-+ */
-+struct dc_cursor *dc_create_cursor_for_target(
-+		const struct dc *dc,
-+		struct dc_target *dc_target);
-+
-+/**
-+ * Commit cursor attribute changes such as pixel format and dimensions and
-+ * surface address.
-+ *
-+ * After this call:
-+ *   Cursor address and format is programmed to the new values.
-+ *   Cursor position is unmodified.
-+ */
-+bool dc_commit_cursor(
-+		const struct dc *dc,
-+		struct dc_cursor *cursor);
-+
-+/*
-+ * Optimized cursor position update
-+ *
-+ * After this call:
-+ *   Cursor position will be programmed as well as enable/disable bit.
-+ */
-+bool dc_set_cursor_position(
-+		const struct dc *dc,
-+		struct dc_cursor *cursor,
-+		struct dc_cursor_position *pos);
-+
-+
-+
-+/*******************************************************************************
-+ * Interrupt interfaces
-+ ******************************************************************************/
-+enum dc_irq_source dc_interrupt_to_irq_source(
-+		struct dc *dc,
-+		uint32_t src_id,
-+		uint32_t ext_id);
-+void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
-+void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
-+const enum dc_irq_source dc_get_hpd_irq_source_at_index(
-+		struct dc *dc, uint32_t link_index);
-+const struct dc_target *dc_get_target_on_irq_source(
-+		const struct dc *dc,
-+		enum dc_irq_source src);
-+
-+
-+/*******************************************************************************
-+ * Power Interfaces
-+ ******************************************************************************/
-+
-+void dc_set_power_state(
-+		struct dc *dc,
-+		enum dc_acpi_cm_power_state power_state,
-+		enum dc_video_power_state video_power_state);
-+void dc_resume(const struct dc *dc);
-+
-+/*******************************************************************************
-+ * DDC Interfaces
-+ ******************************************************************************/
-+
-+const struct ddc_service *dc_get_ddc_at_index(
-+		struct dc *dc, uint32_t link_index);
-+const struct dc_ddc* dc_get_ddc_from_sink(const struct dc_sink* sink);
-+const struct dc_ddc* dc_get_ddc_from_link(const struct dc_link* link);
-+bool dc_ddc_query_i2c(const struct dc_ddc* ddc,
-+		uint32_t address,
-+		uint8_t* write_buf,
-+		uint32_t write_size,
-+		uint8_t* read_buf,
-+		uint32_t read_size);
-+bool dc_ddc_dpcd_read(const struct dc_ddc* ddc, uint32_t address,
-+		uint8_t* data, uint32_t len);
-+bool dc_ddc_dpcd_write(const struct dc_ddc* ddc, uint32_t address,
-+		const uint8_t* data, uint32_t len);
-+
-+
-+
-+bool dc_read_dpcd(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size);
-+
-+bool dc_write_dpcd(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size);
-+
-+
-+#endif /* DC_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-new file mode 100644
-index 0000000..c06eb8c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -0,0 +1,75 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * This file defines helper functions provided by the Display Manager to
-+ * Display Core.
-+ */
-+#ifndef __DC_HELPERS__
-+#define __DC_HELPERS__
-+
-+#include "dc_types.h"
-+#include "dc.h"
-+
-+enum dc_edid_status dc_helpers_parse_edid_caps(
-+	struct dc_context *ctx,
-+	const struct dc_edid *edid,
-+	struct dc_edid_caps *edid_caps);
-+
-+/*
-+ * Writes payload allocation table in immediate downstream device.
-+ */
-+bool dc_helpers_dp_mst_write_payload_allocation_table(
-+		struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		struct dp_mst_stream_allocation *alloc_entity,
-+		bool enable);
-+
-+/*
-+ * Polls for ACT (allocation change trigger) handled and
-+ */
-+bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		struct dc_context *ctx,
-+		const struct dc_sink *sink);
-+/*
-+ * Sends ALLOCATE_PAYLOAD message.
-+ */
-+bool dc_helpers_dp_mst_send_payload_allocation(
-+		struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		bool enable);
-+
-+void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(
-+		void *param);
-+
-+bool dc_helpers_dp_mst_start_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link);
-+
-+void dc_helpers_dp_mst_stop_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link);
-+
-+#endif /* __DC_HELPERS__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-new file mode 100644
-index 0000000..f430864
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -0,0 +1,174 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * This file defines external dependencies of Display Core.
-+ */
-+
-+#ifndef __DC_SERVICES_H__
-+#define __DC_SERVICES_H__
-+
-+/* TODO: remove when DC is complete. */
-+#include "dal_services_types.h"
-+#include "include/dal_types.h"
-+#include "logger_interface.h"
-+#include "irq_types.h"
-+#include "dal_power_interface_types.h"
-+
-+
-+/* if the pointer is not NULL, the allocated memory is zeroed */
-+void *dc_service_alloc(struct dc_context *ctx, uint32_t size);
-+
-+void dc_service_free(struct dc_context *ctx, void *p);
-+
-+void dc_service_memset(void *p, int32_t c, uint32_t count);
-+
-+void dc_service_memmove(void *dst, const void *src, uint32_t size);
-+
-+/* TODO: rename to dc_memcmp*/
-+int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
-+
-+/* TODO: remove when windows_dm will start registering for IRQs */
-+irq_handler_idx dc_service_register_interrupt(
-+	struct dc_context *ctx,
-+	struct dc_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *handler_args);
-+
-+/* TODO: remove when windows_dm will start registering for IRQs */
-+void dc_service_unregister_interrupt(
-+	struct dc_context *ctx,
-+	enum dc_irq_source irq_source,
-+	irq_handler_idx handler_idx);
-+
-+/**************************************
-+ * Calls to Power Play (PP) component
-+ **************************************/
-+
-+/* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-+ * This is done *before* it changes DCE clock.
-+ *
-+ * If required clock is higher than current, then PP will increase the voltage.
-+ *
-+ * If required clock is lower than current, then PP will defer reduction of
-+ * voltage until the call to dc_service_pp_post_dce_clock_change().
-+ *
-+ * \input - Contains clocks needed for Mode Set.
-+ *
-+ * \output - Contains clocks adjusted by PP which DAL should use for Mode Set.
-+ *		Valid only if function returns zero.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dc_service_pp_pre_dce_clock_change(
-+	struct dc_context *ctx,
-+	struct dal_to_power_info *input,
-+	struct power_to_dal_info *output);
-+
-+struct dc_pp_display_configuration {
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+};
-+
-+/* DAL calls this function to notify PP about completion of Mode Set.
-+ * For PP it means that current DCE clocks are those which were returned
-+ * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-+ *
-+ * If the clocks are higher than before, then PP does nothing.
-+ *
-+ * If the clocks are lower than before, then PP reduces the voltage.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dc_service_pp_post_dce_clock_change(
-+	struct dc_context *ctx,
-+	const struct dc_pp_display_configuration *pp_display_cfg);
-+
-+/* The returned clocks range are 'static' system clocks which will be used for
-+ * mode validation purposes.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dc_service_get_system_clocks_range(
-+	struct dc_context *ctx,
-+	struct dal_system_clock_range *sys_clks);
-+
-+/* for future use */
-+bool dc_service_pp_set_display_clock(
-+	struct dc_context *ctx,
-+	struct dal_to_power_dclk *dclk);
-+
-+void dc_service_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
-+
-+/* end of power component calls */
-+
-+void dc_service_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds);
-+
-+/*
-+ *
-+ * general debug capabilities
-+ *
-+ */
-+#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
-+
-+#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
-+#define ASSERT_CRITICAL(expr) do {	\
-+	if (WARN_ON(!(expr))) { \
-+		kgdb_breakpoint(); \
-+	} \
-+} while (0)
-+#else
-+#define ASSERT_CRITICAL(expr) do {	\
-+	if (WARN_ON(!(expr))) { \
-+		; \
-+	} \
-+} while (0)
-+#endif
-+
-+#if defined(CONFIG_DEBUG_KERNEL_DAL)
-+#define ASSERT(expr) ASSERT_CRITICAL(expr)
-+
-+#else
-+#define ASSERT(expr) WARN_ON(!(expr))
-+#endif
-+
-+#define BREAK_TO_DEBUGGER() ASSERT(0)
-+
-+#else
-+
-+#define ASSERT_CRITICAL(expr)  do {if (expr)/* Do nothing */; } while (0)
-+
-+#define ASSERT(expr) do {if (expr)/* Do nothing */; } while (0)
-+
-+#define BREAK_TO_DEBUGGER() do {} while (0)
-+
-+#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
-+
-+#endif /* __DC_SERVICES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_temp.h b/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-new file mode 100644
-index 0000000..b609deb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-@@ -0,0 +1,508 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef DC_TEMP_H_
-+#define DC_TEMP_H_
-+
-+#include "dc_types.h"
-+
-+#define MAX_SURFACE_NUM 2
-+
-+enum clamping_range {
-+	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
-+	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
-+	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
-+	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
-+	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
-+	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
-+};
-+
-+struct clamping_and_pixel_encoding_params {
-+	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
-+	enum clamping_range clamping_level; /* Clamping identifier */
-+	enum dc_color_depth c_depth; /* Deep color use. */
-+};
-+
-+struct bit_depth_reduction_params {
-+	struct {
-+		/* truncate/round */
-+		/* trunc/round enabled*/
-+		uint32_t TRUNCATE_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
-+		uint32_t TRUNCATE_DEPTH:2;
-+		/* truncate or round*/
-+		uint32_t TRUNCATE_MODE:1;
-+
-+		/* spatial dither */
-+		/* Spatial Bit Depth Reduction enabled*/
-+		uint32_t SPATIAL_DITHER_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
-+		uint32_t SPATIAL_DITHER_DEPTH:2;
-+		/* 0-3 to select patterns*/
-+		uint32_t SPATIAL_DITHER_MODE:2;
-+		/* Enable RGB random dithering*/
-+		uint32_t RGB_RANDOM:1;
-+		/* Enable Frame random dithering*/
-+		uint32_t FRAME_RANDOM:1;
-+		/* Enable HighPass random dithering*/
-+		uint32_t HIGHPASS_RANDOM:1;
-+
-+		/* temporal dither*/
-+		 /* frame modulation enabled*/
-+		uint32_t FRAME_MODULATION_ENABLED:1;
-+		/* same as for trunc/spatial*/
-+		uint32_t FRAME_MODULATION_DEPTH:2;
-+		/* 2/4 gray levels*/
-+		uint32_t TEMPORAL_LEVEL:1;
-+		uint32_t FRC25:2;
-+		uint32_t FRC50:2;
-+		uint32_t FRC75:2;
-+	} flags;
-+
-+	uint32_t r_seed_value;
-+	uint32_t b_seed_value;
-+	uint32_t g_seed_value;
-+};
-+
-+enum pipe_gating_control {
-+	PIPE_GATING_CONTROL_DISABLE = 0,
-+	PIPE_GATING_CONTROL_ENABLE,
-+	PIPE_GATING_CONTROL_INIT
-+};
-+
-+enum surface_color_space {
-+	SURFACE_COLOR_SPACE_SRGB = 0x0000,
-+	SURFACE_COLOR_SPACE_BT601 = 0x0001,
-+	SURFACE_COLOR_SPACE_BT709 = 0x0002,
-+	SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004,
-+	SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008,
-+	SURFACE_COLOR_SPACE_XRRGB = 0x0010
-+};
-+
-+enum {
-+    MAX_LANES = 2,
-+    MAX_COFUNC_PATH = 6,
-+    LAYER_INDEX_PRIMARY = -1,
-+};
-+
-+/* Scaling format */
-+enum scaling_transformation {
-+    SCALING_TRANSFORMATION_UNINITIALIZED,
-+    SCALING_TRANSFORMATION_IDENTITY = 0x0001,
-+    SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
-+    SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
-+    SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
-+    SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
-+    SCALING_TRANSFORMATION_INVALID = 0x80000000,
-+
-+    /* Flag the first and last */
-+    SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
-+    SCALING_TRANSFORMATION_END =
-+            SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
-+};
-+
-+struct view_stereo_3d_support {
-+    enum view_3d_format format;
-+    struct {
-+        uint32_t CLONE_MODE:1;
-+        uint32_t SCALING:1;
-+        uint32_t SINGLE_FRAME_SW_PACKED:1;
-+    } features;
-+};
-+
-+struct plane_colorimetry {
-+	enum surface_color_space color_space;
-+	bool limited_range;
-+};
-+
-+enum tiling_mode {
-+    TILING_MODE_INVALID,
-+    TILING_MODE_LINEAR,
-+    TILING_MODE_TILED,
-+    TILING_MODE_COUNT
-+};
-+
-+struct view_position {
-+    uint32_t x;
-+    uint32_t y;
-+};
-+
-+union plane_tiling_info {
-+
-+	struct {
-+		/* Specifies the number of memory banks for tiling
-+		 *	purposes.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 2,4,8,16
-+		 */
-+		uint32_t NUM_BANKS:5;
-+		/* Specifies the number of tiles in the x direction
-+		 *	to be incorporated into the same bank.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 1,2,4,8
-+		 */
-+		uint32_t BANK_WIDTH:4;
-+		/* Specifies the number of tiles in the y direction to
-+		 *	be incorporated into the same bank.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 1,2,4,8
-+		 */
-+		uint32_t BANK_HEIGHT:4;
-+		/* Specifies the macro tile aspect ratio. Only applies
-+		 * to 2D and 3D tiling modes.
-+		 */
-+		uint32_t TILE_ASPECT:3;
-+		/* Specifies the number of bytes that will be stored
-+		 *	contiguously for each tile.
-+		 * If the tile data requires more storage than this
-+		 *	amount, it is split into multiple slices.
-+		 * This field must not be larger than
-+		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 * For color render targets, TILE_SPLIT >= 256B.
-+		 */
-+		uint32_t TILE_SPLIT:3;
-+		/* Specifies the addressing within a tile.
-+		 *	0x0 - DISPLAY_MICRO_TILING
-+		 *	0x1 - THIN_MICRO_TILING
-+		 *	0x2 - DEPTH_MICRO_TILING
-+		 *	0x3 - ROTATED_MICRO_TILING
-+		 */
-+		uint32_t TILE_MODE:2;
-+		/* Specifies the number of pipes and how they are
-+		 *	interleaved in the surface.
-+		 * Refer to memory addressing document for complete
-+		 *	details and constraints.
-+		 */
-+		uint32_t PIPE_CONFIG:5;
-+		/* Specifies the tiling mode of the surface.
-+		 * THIN tiles use an 8x8x1 tile size.
-+		 * THICK tiles use an 8x8x4 tile size.
-+		 * 2D tiling modes rotate banks for successive Z slices
-+		 * 3D tiling modes rotate pipes and banks for Z slices
-+		 * Refer to memory addressing document for complete
-+		 *	details and constraints.
-+		 */
-+		uint32_t ARRAY_MODE:4;
-+	} grph;
-+
-+
-+	struct {
-+		/*possible values: 2,4,8,16*/
-+		uint32_t NUM_BANKS:5;
-+		/*must use enum video_array_mode*/
-+		uint32_t ARRAY_MODE:4;
-+		/*must use enum addr_pipe_config*/
-+		uint32_t PIPE_CONFIG:5;
-+		/*possible values 1,2,4,8 */
-+		uint32_t BANK_WIDTH_LUMA:4;
-+		/*possible values 1,2,4,8 */
-+		uint32_t BANK_HEIGHT_LUMA:4;
-+		/*must use enum macro_tile_aspect*/
-+		uint32_t TILE_ASPECT_LUMA:3;
-+		/*must use enum tile_split*/
-+		uint32_t TILE_SPLIT_LUMA:3;
-+		/*must use micro_tile_mode */
-+		uint32_t TILE_MODE_LUMA:2;
-+		/*possible values: 1,2,4,8*/
-+		uint32_t BANK_WIDTH_CHROMA:4;
-+		/*possible values: 1,2,4,8*/
-+		uint32_t BANK_HEIGHT_CHROMA:4;
-+		/*must use enum macro_tile_aspect*/
-+		uint32_t TILE_ASPECT_CHROMA:3;
-+		/*must use enum tile_split*/
-+		uint32_t TILE_SPLIT_CHROMA:3;
-+		/*must use enum micro_tile_mode*/
-+		uint32_t TILE_MODE_CHROMA:2;
-+
-+	} video;
-+
-+	uint64_t value;
-+};
-+
-+union plane_size {
-+	/* Grph or Video will be selected
-+	 * based on format above:
-+	 * Use Video structure if
-+	 * format >= DalPixelFormat_VideoBegin
-+	 * else use Grph structure
-+	 */
-+	struct {
-+		struct rect surface_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch
-+		 * is 32 pixel aligned.
-+		 */
-+		uint32_t surface_pitch;
-+	} grph;
-+
-+	struct {
-+		struct rect luma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		uint32_t luma_pitch;
-+
-+		struct rect chroma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		uint32_t chroma_pitch;
-+	} video;
-+};
-+
-+/* Windows only */
-+enum dc_scaling_transform {
-+	SCL_TRANS_CENTERED = 0,
-+	SCL_TRANS_ASPECT_RATIO,
-+	SCL_TRANS_FULL
-+};
-+
-+struct dev_c_lut {
-+	uint8_t red;
-+	uint8_t green;
-+	uint8_t blue;
-+};
-+
-+struct dev_c_lut16 {
-+	uint16_t red;
-+	uint16_t green;
-+	uint16_t blue;
-+};
-+
-+enum gamma_ramp_type {
-+	GAMMA_RAMP_UNINITIALIZED = 0,
-+	GAMMA_RAMP_DEFAULT,
-+	GAMMA_RAMP_RBG256X3X16,
-+	GAMMA_RAMP_DXGI_1,
-+};
-+
-+enum surface_type {
-+	OVERLAY_SURFACE = 1, GRAPHIC_SURFACE
-+};
-+
-+#define CONST_RGB_GAMMA_VALUE 2400
-+
-+enum {
-+	RGB_256X3X16 = 256, DX_GAMMA_RAMP_MAX = 1025
-+};
-+
-+struct gamma_ramp_rgb256x3x16 {
-+	uint16_t red[RGB_256X3X16];
-+	uint16_t green[RGB_256X3X16];
-+	uint16_t blue[RGB_256X3X16];
-+};
-+
-+struct dxgi_rgb {
-+	struct fixed32_32 red;
-+	struct fixed32_32 green;
-+	struct fixed32_32 blue;
-+};
-+
-+struct gamma_ramp_dxgi_1 {
-+	struct dxgi_rgb scale;
-+	struct dxgi_rgb offset;
-+	struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX];
-+};
-+
-+struct gamma_ramp {
-+	enum gamma_ramp_type type;
-+	union {
-+		struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
-+		struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1;
-+	};
-+	uint32_t size;
-+};
-+
-+struct regamma_ramp {
-+	uint16_t gamma[RGB_256X3X16 * 3];
-+};
-+
-+/* used by Graphics and Overlay gamma */
-+struct gamma_coeff {
-+	int32_t gamma[3];
-+	int32_t a0[3]; /* index 0 for red, 1 for green, 2 for blue */
-+	int32_t a1[3];
-+	int32_t a2[3];
-+	int32_t a3[3];
-+};
-+
-+struct regamma_lut {
-+	union {
-+		struct {
-+			uint32_t GRAPHICS_DEGAMMA_SRGB :1;
-+			uint32_t OVERLAY_DEGAMMA_SRGB :1;
-+			uint32_t GAMMA_RAMP_ARRAY :1;
-+			uint32_t APPLY_DEGAMMA :1;
-+			uint32_t RESERVED :28;
-+		} bits;
-+		uint32_t value;
-+	} features;
-+
-+	union {
-+		struct regamma_ramp regamma_ramp;
-+		struct gamma_coeff gamma_coeff;
-+	};
-+};
-+
-+union gamma_flag {
-+	struct {
-+		uint32_t config_is_changed :1;
-+		uint32_t both_pipe_req :1;
-+		uint32_t regamma_update :1;
-+		uint32_t gamma_update :1;
-+		uint32_t reserved :28;
-+	} bits;
-+	uint32_t u_all;
-+};
-+
-+enum graphics_regamma_adjust {
-+	GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */
-+	GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */
-+};
-+
-+enum graphics_gamma_lut {
-+	GRAPHICS_GAMMA_LUT_LEGACY = 0, /* use only legacy LUT */
-+	GRAPHICS_GAMMA_LUT_REGAMMA, /* use only regamma LUT */
-+	GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA /* use legacy & regamma LUT's */
-+};
-+
-+enum graphics_degamma_adjust {
-+	GRAPHICS_DEGAMMA_ADJUST_BYPASS = 0, GRAPHICS_DEGAMMA_ADJUST_HW, /*without adjustments */
-+	GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */
-+};
-+
-+struct gamma_parameters {
-+	union gamma_flag flag;
-+	enum pixel_format surface_pixel_format; /*OS surface pixel format*/
-+	struct regamma_lut regamma;
-+
-+	enum graphics_regamma_adjust regamma_adjust_type;
-+	enum graphics_degamma_adjust degamma_adjust_type;
-+
-+	enum graphics_gamma_lut selected_gamma_lut;
-+
-+	bool disable_adjustments;
-+
-+	/* here we grow with parameters if necessary */
-+};
-+
-+struct pixel_format_support {
-+	bool INDEX8 :1;
-+	bool RGB565 :1;
-+	bool ARGB8888 :1;
-+	bool ARGB2101010 :1;
-+	bool ARGB2101010_XRBIAS :1;
-+	bool FP16 :1;
-+};
-+
-+struct render_mode {
-+	struct view view;
-+	enum pixel_format pixel_format;
-+};
-+
-+struct refresh_rate {
-+	uint32_t field_rate;
-+	bool INTERLACED :1;
-+	bool VIDEO_OPTIMIZED_RATE :1;
-+};
-+
-+struct stereo_3d_view {
-+	enum view_3d_format view_3d_format;
-+	union {
-+		uint32_t raw;
-+		struct /*stereo_3d_view_flags*/
-+		{
-+			bool SINGLE_FRAME_SW_PACKED :1;
-+			bool EXCLUSIVE_3D :1;
-+		} bits;
-+	} flags;
-+};
-+
-+enum solution_importance {
-+	SOLUTION_IMPORTANCE_PREFERRED = 1,
-+	/* Means we want to use this solution
-+	 * even in wide topology configurations*/
-+	SOLUTION_IMPORTANCE_SAFE,
-+	SOLUTION_IMPORTANCE_UNSAFE,
-+	SOLUTION_IMPORTANCE_DEFAULT
-+/* Temporary state , means Solution object
-+ * should define importance by itself
-+ */
-+};
-+
-+struct solution {
-+	const struct dc_mode_timing *dc_mode_timing;
-+	enum solution_importance importance;
-+	bool is_custom_mode;
-+	uint32_t scl_support[NUM_PIXEL_FORMATS];
-+	/* bit vector of the scaling that can be supported on the timing */
-+	uint32_t scl_support_guaranteed[NUM_PIXEL_FORMATS];
-+	/* subset of m_sclSupport that can be guaranteed supported */
-+};
-+
-+enum timing_select {
-+	TIMING_SELECT_DEFAULT,
-+	TIMING_SELECT_NATIVE_ONLY,
-+	TIMING_SELECT_PRESERVE_ASPECT
-+};
-+
-+enum downscale_state {
-+	DOWNSCALESTATE_DEFAULT,     // Disabled, but not user selected
-+	DOWNSCALESTATE_DISABLED,    // User disabled through CCC
-+	DOWNSCALESTATE_ENABLED      // User enabled through CCC
-+};
-+struct scaling_support {
-+	bool IDENTITY :1;
-+	bool FULL_SCREEN_SCALE :1;
-+	bool PRESERVE_ASPECT_RATIO_SCALE :1;
-+	bool CENTER_TIMING :1;
-+};
-+
-+
-+/* TODO: combine the two cursor functions into one to make cursor
-+ * programming resistant to changes in OS call sequence. */
-+bool dc_target_set_cursor_attributes(
-+	struct dc_target *dc_target,
-+	const struct dc_cursor_attributes *attributes);
-+
-+bool dc_target_set_cursor_position(
-+	struct dc_target *dc_target,
-+	const struct dc_cursor_position *position);
-+
-+/******************************************************************************
-+ * TODO: these definitions only for Timing Sync feature bring-up. Remove
-+ * when the feature is complete.
-+ *****************************************************************************/
-+
-+#define MAX_TARGET_NUM 6
-+
-+void dc_print_sync_report(
-+	const struct dc *dc);
-+
-+/******************************************************************************/
-+
-+#endif /* DC_TEMP_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-new file mode 100644
-index 0000000..b6526e9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -0,0 +1,677 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef DC_TYPES_H_
-+#define DC_TYPES_H_
-+
-+#include "fixed32_32.h"
-+#include "fixed31_32.h"
-+#include "irq_types.h"
-+
-+/* forward declarations */
-+struct dc;
-+struct dc_surface;
-+struct dc_target;
-+struct dc_stream;
-+struct dc_link;
-+struct dc_sink;
-+struct dal;
-+
-+#define MAX_EDID_BUFFER_SIZE 512
-+
-+/*Displayable pixel format in fb*/
-+enum surface_pixel_format {
-+	SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
-+	/*TOBE REMOVED paletta 256 colors*/
-+	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
-+		SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
-+	/*16 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
-+	/*16 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_RGB565,
-+	/*32 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
-+	/*32 bpp swaped*/
-+	SURFACE_PIXEL_FORMAT_GRPH_BGRA8888,
-+
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
-+	/*swaped*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
-+	/*TOBE REMOVED swaped, XR_BIAS has no differance
-+	 * for pixel layout than previous and we can
-+	 * delete this after discusion*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
-+	/*64 bpp */
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
-+	/*swaped & float*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
-+	/*grow graphics here if necessary */
-+
-+	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
-+		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_YCb,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_YCr,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_CbY,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_CrY,
-+	/*grow 422/420 video here if necessary */
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 =
-+		SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102
-+	/*grow 444 video here if necessary */
-+};
-+
-+
-+/* Pixel format */
-+enum pixel_format {
-+	/*graph*/
-+	PIXEL_FORMAT_UNINITIALIZED,
-+	PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_RGB565,
-+	PIXEL_FORMAT_ARGB8888,
-+	PIXEL_FORMAT_ARGB2101010,
-+	PIXEL_FORMAT_ARGB2101010_XRBIAS,
-+	PIXEL_FORMAT_FP16,
-+	/*video*/
-+	PIXEL_FORMAT_420BPP12,
-+	PIXEL_FORMAT_422BPP16,
-+	PIXEL_FORMAT_444BPP16,
-+	PIXEL_FORMAT_444BPP32,
-+	/*end of pixel format definition*/
-+	PIXEL_FORMAT_INVALID,
-+
-+	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
-+	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
-+	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_444BPP32,
-+	PIXEL_FORMAT_UNKNOWN
-+};
-+
-+enum plane_stereo_format {
-+	PLANE_STEREO_FORMAT_NONE = 0,
-+	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
-+	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
-+	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
-+	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
-+	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
-+	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
-+};
-+
-+/* 3D format for view, typically define how L/R eye surface is arranged within
-+ * frames
-+ */
-+enum view_3d_format {
-+	VIEW_3D_FORMAT_NONE = 0,
-+	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
-+	VIEW_3D_FORMAT_SIDE_BY_SIDE,
-+	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
-+	VIEW_3D_FORMAT_COUNT,
-+	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
-+};
-+
-+enum dc_pixel_encoding {
-+	PIXEL_ENCODING_UNDEFINED,
-+	PIXEL_ENCODING_RGB,
-+	PIXEL_ENCODING_YCBCR422,
-+	PIXEL_ENCODING_YCBCR444,
-+	PIXEL_ENCODING_YCBCR420,
-+	PIXEL_ENCODING_COUNT
-+};
-+
-+/* TODO: Find way to calculate number of bits
-+ *  Please increase if pixel_format enum increases
-+ * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-+ */
-+#define NUM_PIXEL_FORMATS 10
-+
-+
-+
-+union large_integer {
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	};
-+
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	} u;
-+
-+	int64_t quad_part;
-+};
-+
-+#define PHYSICAL_ADDRESS_LOC union large_integer
-+
-+enum dc_edid_connector_type {
-+	EDID_CONNECTOR_UNKNOWN = 0,
-+	EDID_CONNECTOR_ANALOG = 1,
-+	EDID_CONNECTOR_DIGITAL = 10,
-+	EDID_CONNECTOR_DVI = 11,
-+	EDID_CONNECTOR_HDMIA = 12,
-+	EDID_CONNECTOR_MDDI = 14,
-+	EDID_CONNECTOR_DISPLAYPORT = 15
-+};
-+
-+enum dc_edid_status {
-+	EDID_OK,
-+	EDID_BAD_INPUT,
-+	EDID_NO_RESPONSE,
-+	EDID_BAD_CHECKSUM,
-+};
-+
-+/* audio capability from EDID*/
-+struct dc_cea_audio_mode {
-+	uint8_t format_code; /* ucData[0] [6:3]*/
-+	uint8_t channel_count; /* ucData[0] [2:0]*/
-+	uint8_t sample_rate; /* ucData[1]*/
-+	union {
-+		uint8_t sample_size; /* for LPCM*/
-+		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
-+		uint8_t max_bit_rate;
-+		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
-+	};
-+};
-+
-+struct dc_edid {
-+	uint32_t length;
-+	uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
-+};
-+
-+/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
-+ * is used. In this case we assume speaker location are: front left, front
-+ * right and front center. */
-+#define DEFAULT_SPEAKER_LOCATION 5
-+
-+#define DC_MAX_AUDIO_DESC_COUNT 16
-+
-+#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
-+
-+struct dc_edid_caps {
-+	/* sink identification */
-+	uint16_t manufacturer_id;
-+	uint16_t product_id;
-+	uint32_t serial_number;
-+	uint8_t manufacture_week;
-+	uint8_t manufacture_year;
-+	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
-+
-+	/* audio caps */
-+	uint8_t speaker_flags;
-+	uint32_t audio_mode_count;
-+	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
-+	uint32_t audio_latency;
-+	uint32_t video_latency;
-+
-+	/*HDMI 2.0 caps*/
-+	uint8_t lte_340mcsc_scramble;
-+};
-+
-+struct scaling_taps {
-+	uint32_t v_taps;
-+	uint32_t h_taps;
-+	uint32_t v_taps_c;
-+	uint32_t h_taps_c;
-+};
-+
-+struct scaling_ratios {
-+	struct fixed31_32 horz;
-+	struct fixed31_32 vert;
-+	struct fixed31_32 horz_c;
-+	struct fixed31_32 vert_c;
-+};
-+
-+struct rect {
-+	uint32_t x;
-+	uint32_t y;
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+struct view {
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+struct dc_resolution {
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+
-+struct dc_mode_flags {
-+	/* note: part of refresh rate flag*/
-+	uint32_t INTERLACE :1;
-+	/* native display timing*/
-+	uint32_t NATIVE :1;
-+	/* preferred is the recommended mode, one per display */
-+	uint32_t PREFERRED :1;
-+	/* true if this mode should use reduced blanking timings
-+	 *_not_ related to the Reduced Blanking adjustment*/
-+	uint32_t REDUCED_BLANKING :1;
-+	/* note: part of refreshrate flag*/
-+	uint32_t VIDEO_OPTIMIZED_RATE :1;
-+	/* should be reported to upper layers as mode_flags*/
-+	uint32_t PACKED_PIXEL_FORMAT :1;
-+	/*< preferred view*/
-+	uint32_t PREFERRED_VIEW :1;
-+	/* this timing should be used only in tiled mode*/
-+	uint32_t TILED_MODE :1;
-+	uint32_t DSE_MODE :1;
-+	/* Refresh rate divider when Miracast sink is using a
-+	 different rate than the output display device
-+	 Must be zero for wired displays and non-zero for
-+	 Miracast displays*/
-+	uint32_t MIRACAST_REFRESH_DIVIDER;
-+};
-+
-+struct dc_crtc_timing_flags {
-+	uint32_t INTERLACE :1;
-+	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-+	 it is positive polarity --reversed with dal1 or video bios define*/
-+	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-+	 it is positive polarity --reversed with dal1 or video bios define*/
-+
-+	uint32_t HORZ_COUNT_BY_TWO:1;
-+
-+	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
-+	 timing can be driven in 3D format only
-+	 and there is no corresponding 2D timing*/
-+	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
-+	 (right eye = '1', left eye = '0') */
-+	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
-+	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
-+	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
-+	 because corresponding 2D timing also present in the list*/
-+	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
-+	 and we want to match priority of corresponding 3D timing*/
-+	uint32_t Y_ONLY :1;
-+
-+	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
-+	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
-+
-+	/* HDMI 2.0 - Support scrambling for TMDS character
-+	 * rates less than or equal to 340Mcsc */
-+	uint32_t LTE_340MCSC_SCRAMBLE:1;
-+
-+};
-+
-+enum dc_timing_standard {
-+	TIMING_STANDARD_UNDEFINED,
-+	TIMING_STANDARD_DMT,
-+	TIMING_STANDARD_GTF,
-+	TIMING_STANDARD_CVT,
-+	TIMING_STANDARD_CVT_RB,
-+	TIMING_STANDARD_CEA770,
-+	TIMING_STANDARD_CEA861,
-+	TIMING_STANDARD_HDMI,
-+	TIMING_STANDARD_TV_NTSC,
-+	TIMING_STANDARD_TV_NTSC_J,
-+	TIMING_STANDARD_TV_PAL,
-+	TIMING_STANDARD_TV_PAL_M,
-+	TIMING_STANDARD_TV_PAL_CN,
-+	TIMING_STANDARD_TV_SECAM,
-+	TIMING_STANDARD_EXPLICIT,
-+	/*!< For explicit timings from EDID, VBIOS, etc.*/
-+	TIMING_STANDARD_USER_OVERRIDE,
-+	/*!< For mode timing override by user*/
-+	TIMING_STANDARD_MAX
-+};
-+
-+enum dc_aspect_ratio {
-+	ASPECT_RATIO_NO_DATA,
-+	ASPECT_RATIO_4_3,
-+	ASPECT_RATIO_16_9,
-+	ASPECT_RATIO_64_27,
-+	ASPECT_RATIO_256_135,
-+	ASPECT_RATIO_FUTURE
-+};
-+
-+enum dc_color_depth {
-+	COLOR_DEPTH_UNDEFINED,
-+	COLOR_DEPTH_666,
-+	COLOR_DEPTH_888,
-+	COLOR_DEPTH_101010,
-+	COLOR_DEPTH_121212,
-+	COLOR_DEPTH_141414,
-+	COLOR_DEPTH_161616,
-+	COLOR_DEPTH_COUNT
-+};
-+
-+enum dc_timing_3d_format {
-+	TIMING_3D_FORMAT_NONE,
-+	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
-+	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
-+	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
-+	/* for active DP-HDMI dongle*/
-+	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
-+	TIMING_3D_FORMAT_HW_FRAME_PACKING,
-+	TIMING_3D_FORMAT_SW_FRAME_PACKING,
-+	TIMING_3D_FORMAT_ROW_INTERLEAVE,
-+	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
-+	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
-+	TIMING_3D_FORMAT_SIDE_BY_SIDE,
-+	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
-+	TIMING_3D_FORMAT_SBS_SW_PACKED,
-+	/* Side-by-side, packed by application/driver into 2D frame*/
-+	TIMING_3D_FORMAT_TB_SW_PACKED,
-+	/* Top-and-bottom, packed by application/driver into 2D frame*/
-+
-+	TIMING_3D_FORMAT_MAX,
-+};
-+
-+enum dc_timing_source {
-+	TIMING_SOURCE_UNDEFINED,
-+
-+	/* explicitly specifed by user, most important*/
-+	TIMING_SOURCE_USER_FORCED,
-+	TIMING_SOURCE_USER_OVERRIDE,
-+	TIMING_SOURCE_CUSTOM,
-+	TIMING_SOURCE_EXPLICIT,
-+
-+	/* explicitly specified by the display device, more important*/
-+	TIMING_SOURCE_EDID_CEA_SVD_3D,
-+	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
-+	TIMING_SOURCE_EDID_CEA_SVD_420,
-+	TIMING_SOURCE_EDID_DETAILED,
-+	TIMING_SOURCE_EDID_ESTABLISHED,
-+	TIMING_SOURCE_EDID_STANDARD,
-+	TIMING_SOURCE_EDID_CEA_SVD,
-+	TIMING_SOURCE_EDID_CVT_3BYTE,
-+	TIMING_SOURCE_EDID_4BYTE,
-+	TIMING_SOURCE_VBIOS,
-+	TIMING_SOURCE_CV,
-+	TIMING_SOURCE_TV,
-+	TIMING_SOURCE_HDMI_VIC,
-+
-+	/* implicitly specified by display device, still safe but less important*/
-+	TIMING_SOURCE_DEFAULT,
-+
-+	/* only used for custom base modes */
-+	TIMING_SOURCE_CUSTOM_BASE,
-+
-+	/* these timing might not work, least important*/
-+	TIMING_SOURCE_RANGELIMIT,
-+	TIMING_SOURCE_OS_FORCED,
-+	TIMING_SOURCE_IMPLICIT,
-+
-+	/* only used by default mode list*/
-+	TIMING_SOURCE_BASICMODE,
-+
-+	TIMING_SOURCE_COUNT
-+};
-+
-+enum dc_timing_support_method {
-+	TIMING_SUPPORT_METHOD_UNDEFINED,
-+	TIMING_SUPPORT_METHOD_EXPLICIT,
-+	TIMING_SUPPORT_METHOD_IMPLICIT,
-+	TIMING_SUPPORT_METHOD_NATIVE
-+};
-+
-+struct dc_mode_info {
-+	uint32_t pixel_width;
-+	uint32_t pixel_height;
-+	uint32_t field_rate;
-+	/* Vertical refresh rate for progressive modes.
-+	* Field rate for interlaced modes.*/
-+
-+	enum dc_timing_standard timing_standard;
-+	enum dc_timing_source timing_source;
-+	struct dc_mode_flags flags;
-+};
-+
-+/* TODO: assess necessity*/
-+/*scanning type*/
-+enum scanning_type {
-+	SCANNING_TYPE_NODATA = 0,
-+	SCANNING_TYPE_OVERSCAN,
-+	SCANNING_TYPE_UNDERSCAN,
-+	SCANNING_TYPE_FUTURE,
-+	SCANNING_TYPE_UNDEFINED
-+};
-+
-+struct dc_crtc_timing {
-+	uint32_t h_total;
-+	uint32_t h_border_left;
-+	uint32_t h_addressable;
-+	uint32_t h_border_right;
-+	uint32_t h_front_porch;
-+	uint32_t h_sync_width;
-+
-+	uint32_t v_total;
-+	uint32_t v_border_top;
-+	uint32_t v_addressable;
-+	uint32_t v_border_bottom;
-+	uint32_t v_front_porch;
-+	uint32_t v_sync_width;
-+
-+	uint32_t pix_clk_khz;
-+
-+	uint32_t vic;
-+	uint32_t hdmi_vic;
-+	enum dc_timing_standard timing_standard;
-+	enum dc_timing_3d_format timing_3d_format;
-+	enum dc_color_depth display_color_depth;
-+	enum dc_pixel_encoding pixel_encoding;
-+	enum dc_aspect_ratio aspect_ratio;
-+	enum scanning_type scan_type;
-+
-+	struct dc_crtc_timing_flags flags;
-+};
-+
-+struct dc_mode_timing {
-+	struct dc_mode_info mode_info;
-+	struct dc_crtc_timing crtc_timing;
-+};
-+
-+/* Rotation angle */
-+enum dc_rotation_angle {
-+	ROTATION_ANGLE_0 = 0,
-+	ROTATION_ANGLE_90,
-+	ROTATION_ANGLE_180,
-+	ROTATION_ANGLE_270,
-+	ROTATION_ANGLE_COUNT
-+};
-+
-+struct dc_cursor_position {
-+	uint32_t x;
-+	uint32_t y;
-+
-+	uint32_t x_origin;
-+	uint32_t y_origin;
-+
-+	/*
-+	 * This parameter indicates whether HW cursor should be enabled
-+	 */
-+	bool enable;
-+
-+	/*
-+	 * This parameter indicates whether cursor hot spot should be
-+	 * programmed
-+	 */
-+	bool hot_spot_enable;
-+};
-+
-+/* This enum is for programming CURSOR_MODE register field. */
-+/* What this register should be programmed to depends on */
-+/* OS requested cursor shape flags */
-+/* and what we stored in the cursor surface. */
-+enum dc_cursor_color_format {
-+	CURSOR_MODE_MONO,
-+	CURSOR_MODE_COLOR_1BIT_AND,
-+	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
-+	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
-+};
-+
-+union dc_cursor_attribute_flags {
-+	struct {
-+		uint32_t ENABLE_MAGNIFICATION:1;
-+		uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
-+		uint32_t HORIZONTAL_MIRROR:1;
-+		uint32_t VERTICAL_MIRROR:1;
-+		uint32_t RESERVED:28;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+/* This is all the parameters required by DAL in order to */
-+/* update the cursor attributes, */
-+/* including the new cursor image surface address, size, */
-+/* hotspot location, color format, etc. */
-+struct dc_cursor_attributes {
-+	PHYSICAL_ADDRESS_LOC address;
-+
-+	/* Width and height should correspond to cursor surface width x heigh */
-+	uint32_t width;
-+	uint32_t height;
-+	uint32_t x_hot;
-+	uint32_t y_hot;
-+
-+	enum dc_cursor_color_format color_format;
-+
-+	/* In case we support HW Cursor rotation in the future */
-+	enum dc_rotation_angle rotation_angle;
-+
-+	union dc_cursor_attribute_flags attribute_flags;
-+
-+};
-+
-+
-+enum dc_plane_addr_type {
-+	PLN_ADDR_TYPE_GRAPHICS = 0,
-+	PLN_ADDR_TYPE_GRPH_STEREO,
-+	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
-+	PLN_ADDR_TYPE_VIDEO_INTERLACED,
-+	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO,
-+	PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO
-+};
-+
-+struct dc_plane_address {
-+	enum dc_plane_addr_type type;
-+	union {
-+		struct{
-+			PHYSICAL_ADDRESS_LOC addr;
-+		} grph;
-+
-+		/*stereo*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC left_addr;
-+			PHYSICAL_ADDRESS_LOC right_addr;
-+		} grph_stereo;
-+
-+		/*video  progressive*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC chroma_addr;
-+			PHYSICAL_ADDRESS_LOC luma_addr;
-+		} video_progressive;
-+
-+		/*video interlaced*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC chroma_addr;
-+			PHYSICAL_ADDRESS_LOC luma_addr;
-+			PHYSICAL_ADDRESS_LOC chroma_bottom_addr;
-+			PHYSICAL_ADDRESS_LOC luma_bottom_addr;
-+		} video_interlaced;
-+
-+		/*video Progressive Stereo*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC left_chroma_addr;
-+			PHYSICAL_ADDRESS_LOC left_luma_addr;
-+			PHYSICAL_ADDRESS_LOC right_chroma_addr;
-+			PHYSICAL_ADDRESS_LOC right_luma_addr;
-+		} video_progressive_stereo;
-+
-+		/*video  interlaced stereo*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC left_chroma_addr;
-+			PHYSICAL_ADDRESS_LOC left_luma_addr;
-+			PHYSICAL_ADDRESS_LOC left_chroma_bottom_addr;
-+			PHYSICAL_ADDRESS_LOC left_luma_bottom_addr;
-+
-+			PHYSICAL_ADDRESS_LOC right_chroma_addr;
-+			PHYSICAL_ADDRESS_LOC right_luma_addr;
-+			PHYSICAL_ADDRESS_LOC right_chroma_bottom_addr;
-+			PHYSICAL_ADDRESS_LOC right_luma_bottom_addr;
-+		} video_interlaced_stereo;
-+	};
-+};
-+
-+enum dc_power_state {
-+	DC_POWER_STATE_ON = 1,
-+	DC_POWER_STATE_STANDBY,
-+	DC_POWER_STATE_SUSPEND,
-+	DC_POWER_STATE_OFF
-+};
-+
-+/* DC PowerStates */
-+enum dc_video_power_state {
-+	DC_VIDEO_POWER_UNSPECIFIED = 0,
-+	DC_VIDEO_POWER_ON = 1,
-+	DC_VIDEO_POWER_STANDBY,
-+	DC_VIDEO_POWER_SUSPEND,
-+	DC_VIDEO_POWER_OFF,
-+	DC_VIDEO_POWER_HIBERNATE,
-+	DC_VIDEO_POWER_SHUTDOWN,
-+	DC_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
-+	DC_VIDEO_POWER_AFTER_RESET,
-+	DC_VIDEO_POWER_MAXIMUM
-+};
-+
-+enum dc_acpi_cm_power_state {
-+	DC_ACPI_CM_POWER_STATE_D0 = 1,
-+	DC_ACPI_CM_POWER_STATE_D1 = 2,
-+	DC_ACPI_CM_POWER_STATE_D2 = 4,
-+	DC_ACPI_CM_POWER_STATE_D3 = 8
-+};
-+
-+struct view_port_alignment {
-+	uint8_t x_width_size_alignment;
-+	uint8_t y_height_size_alignment;
-+	uint8_t x_start_alignment;
-+	uint8_t y_start_alignment;
-+};
-+
-+enum dc_connection_type {
-+	dc_connection_none,
-+	dc_connection_single,
-+	dc_connection_mst_branch,
-+	dc_connection_active_dongle
-+};
-+
-+struct dc_csc_adjustments {
-+	struct fixed31_32 contrast;
-+	struct fixed31_32 saturation;
-+	struct fixed31_32 brightness;
-+	struct fixed31_32 hue;
-+};
-+
-+#include "dc_temp.h"
-+
-+#endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-new file mode 100644
-index 0000000..5bf9b56
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -0,0 +1,33 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
-+dce110_ipp_gamma.o dce110_link_encoder.o dce110_opp.o \
-+dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
-+dce110_timing_generator.o dce110_transform.o dce110_transform_gamut.o \
-+dce110_transform_scl.o dce110_transform_sclv.o dce110_opp_csc.o\
-+dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
-+dce110_resource.o dce110_transform_bit_depth.o
-+
-+AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
-+
-+AMD_DAL_FILES += $(AMD_DAL_DCE110)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
-+TG_DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
-+dce110_ipp_gamma.o dce110_timing_generator.o dce110_link_encoder.o \
-+dce110_opp.o dce110_opp_regamma.o dce110_opp_formatter.o dce110_opp_csc.o \
-+dce110_transform.o dce110_transform_gamut.o dce110_transform_bit_depth.o \
-+dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o dce110_resource.o
-+
-+AMD_DAL_TG_DCE110 = $(addprefix \
-+	$(AMDDALPATH)/dc/dce110/,$(TG_DCE110))
-+
-+AMD_DAL_FILES += $(AMD_DAL_TG_DCE110)
-+endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-new file mode 100644
-index 0000000..7abb790
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-@@ -0,0 +1,886 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+#include "gmc/gmc_8_2_d.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/adapter_service_interface.h"
-+
-+#include "dce110_compressor.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + cp110->offsets.dcp_offset)
-+#define DMIF_REG(reg)\
-+	(reg + cp110->offsets.dmif_offset)
-+
-+static const struct dce110_compressor_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+}
-+};
-+
-+static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
-+
-+enum fbc_idle_force {
-+	/* Bit 0 - Display registers updated */
-+	FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
-+
-+	/* Bit 2 - FBC_GRPH_COMP_EN register updated */
-+	FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
-+	/* Bit 3 - FBC_SRC_SEL register updated */
-+	FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
-+	/* Bit 4 - FBC_MIN_COMPRESSION register updated */
-+	FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
-+	/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-+	FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
-+	/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-+	FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
-+	/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-+	FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
-+
-+	/* Bit 24 - Memory write to region 0 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
-+	/* Bit 25 - Memory write to region 1 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
-+	/* Bit 26 - Memory write to region 2 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
-+	/* Bit 27 - Memory write to region 3 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
-+
-+	/* Bit 28 - Memory write from any client other than MCIF */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
-+	/* Bit 29 - CG statics screen signal is inactive */
-+	FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
-+};
-+
-+static uint32_t lpt_size_alignment(struct dce110_compressor *cp110)
-+{
-+	/*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-+	return cp110->base.raw_size * cp110->base.banks_num *
-+		cp110->base.dram_channels_num;
-+}
-+
-+static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
-+	uint32_t lpt_control)
-+{
-+	/*LPT MC Config */
-+	if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
-+		/* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-+		 * 00 - 1 CHANNEL
-+		 * 01 - 2 CHANNELS
-+		 * 02 - 4 OR 6 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ)
-+		 * 03 - 8 OR 12 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ) */
-+		switch (cp110->base.dram_channels_num) {
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		case 1:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT NUM_PIPES!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LPT NUM_BANKS is in
-+		 * GRPH_CONTROL.GRPH_NUM_BANKS register field
-+		 * Specifies the number of memory banks for tiling
-+		 * purposes. Only applies to 2D and 3D tiling modes.
-+		 * POSSIBLE VALUES:
-+		 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-+		 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-+		 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-+		 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-+		switch (cp110->base.banks_num) {
-+		case 16:
-+			set_reg_field_value(
-+				lpt_control,
-+				3,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 8:
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 4:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT NUM_BANKS!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping is in DMIF_ADDR_CALC.
-+		 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-+		 * Carrizo specifies the memory interleave per pipe.
-+		 * It effectively specifies the location of pipe bits in
-+		 * the memory address.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
-+		 * interleave
-+		 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
-+		 * interleave
-+		 */
-+		switch (cp110->base.channel_interleave_size) {
-+		case 256: /*256B */
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		case 512: /*512B */
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT INTERLEAVE_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LOW_POWER_TILING_ROW_SIZE is in
-+		 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
-+		 * for Carrizo. Specifies the size of dram row in bytes.
-+		 * This should match up with NOOFCOLS field in
-+		 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
-+		 * This register DMIF_ADDR_CALC is not used by the
-+		 * hardware as it is only used for addrlib assertions.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
-+		 * boundary
-+		 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
-+		 * boundary
-+		 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
-+		 * boundary */
-+		switch (cp110->base.raw_size) {
-+		case 4096: /*4 KB */
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 2048:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 1024:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT ROW_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+	} else {
-+		dal_logger_write(
-+			cp110->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: LPT MC Configuration is not provided",
-+			__func__);
-+	}
-+
-+	return lpt_control;
-+}
-+
-+
-+
-+static bool is_source_bigger_than_epanel_size(
-+	struct dce110_compressor *cp110,
-+	uint32_t source_view_width,
-+	uint32_t source_view_height)
-+{
-+	if (cp110->base.embedded_panel_h_size != 0 &&
-+		cp110->base.embedded_panel_v_size != 0 &&
-+		((source_view_width * source_view_height) >
-+		(cp110->base.embedded_panel_h_size *
-+			cp110->base.embedded_panel_v_size)))
-+		return true;
-+
-+	return false;
-+}
-+
-+static uint32_t align_to_chunks_number_per_line(
-+	struct dce110_compressor *cp110,
-+	uint32_t pixels)
-+{
-+	return 256 * ((pixels + 255) / 256);
-+}
-+
-+static void wait_for_fbc_state_changed(
-+	struct dce110_compressor *cp110,
-+	bool enabled)
-+{
-+	uint8_t counter = 0;
-+	uint32_t addr = mmFBC_STATUS;
-+	uint32_t value;
-+
-+	while (counter < 10) {
-+		value = dal_read_reg(cp110->base.ctx, addr);
-+		if (get_reg_field_value(
-+			value,
-+			FBC_STATUS,
-+			FBC_ENABLE_STATUS) == enabled)
-+			break;
-+		dc_service_delay_in_microseconds(cp110->base.ctx, 10);
-+		counter++;
-+	}
-+
-+	if (counter == 10) {
-+		dal_logger_write(
-+			cp110->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: wait counter exceeded, changes to HW not applied",
-+			__func__);
-+	}
-+}
-+
-+void dce110_compressor_power_up_fbc(struct compressor *compressor)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmFBC_CNTL;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
-+	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-+	if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
-+		/* HW needs to do power measurement comparison. */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			FBC_CNTL,
-+			FBC_COMP_CLK_GATE_EN);
-+	}
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_MODE;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_CNTL;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
-+	dal_write_reg(compressor->ctx, addr, value);
-+	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
-+	/*                    1 ==> 4:1 */
-+	/*                    2 ==> 8:1 */
-+	/*                  0xF ==> 1:1 */
-+	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
-+	dal_write_reg(compressor->ctx, addr, value);
-+	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
-+
-+	value = 0;
-+	dal_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+
-+	value = 0xFFFFFF;
-+	dal_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+}
-+
-+void dce110_compressor_enable_fbc(
-+	struct compressor *compressor,
-+	uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		(compressor->options.bits.DUMMY_BACKEND == 0) &&
-+		(!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
-+		(!is_source_bigger_than_epanel_size(
-+			cp110,
-+			params->source_view_width,
-+			params->source_view_height))) {
-+
-+		uint32_t addr;
-+		uint32_t value;
-+
-+		/* Before enabling FBC first need to enable LPT if applicable
-+		 * LPT state should always be changed (enable/disable) while FBC
-+		 * is disabled */
-+		if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
-+			(params->source_view_width *
-+				params->source_view_height <=
-+				dce11_one_lpt_channel_max_resolution)) {
-+			dce110_compressor_enable_lpt(compressor);
-+		}
-+
-+		addr = mmFBC_CNTL;
-+		value = dal_read_reg(compressor->ctx, addr);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		set_reg_field_value(
-+			value,
-+			params->inst,
-+			FBC_CNTL, FBC_SRC_SEL);
-+		dal_write_reg(compressor->ctx, addr, value);
-+
-+		/* Keep track of enum controller_id FBC is attached to */
-+		compressor->is_enabled = true;
-+		compressor->attached_inst = params->inst;
-+		cp110->offsets = reg_offsets[params->inst - 1];
-+
-+		/*Toggle it as there is bug in HW */
-+		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dal_write_reg(compressor->ctx, addr, value);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dal_write_reg(compressor->ctx, addr, value);
-+
-+		wait_for_fbc_state_changed(cp110, true);
-+	}
-+}
-+
-+void dce110_compressor_disable_fbc(struct compressor *compressor)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
-+		uint32_t reg_data;
-+		/* Turn off compression */
-+		reg_data = dal_read_reg(compressor->ctx, mmFBC_CNTL);
-+		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dal_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+
-+		/* Reset enum controller_id to undefined */
-+		compressor->attached_inst = 0;
-+		compressor->is_enabled = false;
-+
-+		/* Whenever disabling FBC make sure LPT is disabled if LPT
-+		 * supported */
-+		if (compressor->options.bits.LPT_SUPPORT)
-+			dce110_compressor_disable_lpt(compressor);
-+
-+		wait_for_fbc_state_changed(cp110, false);
-+	}
-+}
-+
-+bool dce110_compressor_is_fbc_enabled_in_hw(
-+	struct compressor *compressor,
-+	uint32_t *inst)
-+{
-+	/* Check the hardware register */
-+	uint32_t value;
-+
-+	value = dal_read_reg(compressor->ctx, mmFBC_STATUS);
-+	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
-+		if (inst != NULL)
-+			*inst = compressor->attached_inst;
-+		return true;
-+	}
-+
-+	value = dal_read_reg(compressor->ctx, mmFBC_MISC);
-+	if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
-+		value = dal_read_reg(compressor->ctx, mmFBC_CNTL);
-+
-+		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
-+			if (inst != NULL)
-+				*inst =
-+					compressor->attached_inst;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
-+{
-+	/* Check the hardware register */
-+	uint32_t value = dal_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	return get_reg_field_value(
-+		value,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+}
-+
-+void dce110_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+	uint32_t value = 0;
-+	uint32_t fbc_pitch = 0;
-+	uint32_t compressed_surf_address_low_part =
-+		compressor->compr_surface_address.addr.low_part;
-+
-+	/* Clear content first. */
-+	dal_write_reg(
-+		compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		0);
-+	dal_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
-+
-+	if (compressor->options.bits.LPT_SUPPORT) {
-+		uint32_t lpt_alignment = lpt_size_alignment(cp110);
-+
-+		if (lpt_alignment != 0) {
-+			compressed_surf_address_low_part =
-+				((compressed_surf_address_low_part
-+					+ (lpt_alignment - 1)) / lpt_alignment)
-+					* lpt_alignment;
-+		}
-+	}
-+
-+	/* Write address, HIGH has to be first. */
-+	dal_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		compressor->compr_surface_address.addr.high_part);
-+	dal_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
-+		compressed_surf_address_low_part);
-+
-+	fbc_pitch = align_to_chunks_number_per_line(
-+		cp110,
-+		params->source_view_width);
-+
-+	if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
-+		fbc_pitch = fbc_pitch / 8;
-+	else
-+		dal_logger_write(
-+			compressor->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: Unexpected DCE11 compression ratio",
-+			__func__);
-+
-+	/* Clear content first. */
-+	dal_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+
-+	/* Write FBC Pitch. */
-+	set_reg_field_value(
-+		value,
-+		fbc_pitch,
-+		GRPH_COMPRESS_PITCH,
-+		GRPH_COMPRESS_PITCH);
-+	dal_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+
-+}
-+
-+void dce110_compressor_disable_lpt(struct compressor *compressor)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t inx;
-+
-+	/* Disable all pipes LPT Stutter */
-+	for (inx = 0; inx < 3; inx++) {
-+		value =
-+			dal_read_reg(
-+				compressor->ctx,
-+				DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+			STUTTER_ENABLE_NONLPTCH);
-+		dal_write_reg(
-+			compressor->ctx,
-+			DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
-+			value);
-+	}
-+	/* Disable Underlay pipe LPT Stutter */
-+	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	/* Disable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	/* Clear selection of Channel(s) containing Compressed Surface */
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0xFFFFFFFF,
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dal_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
-+}
-+
-+void dce110_compressor_enable_lpt(struct compressor *compressor)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t value_control;
-+	uint32_t channels;
-+
-+	/* Enable LPT Stutter from Display pipe */
-+	value = dal_read_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dal_write_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
-+
-+	/* Enable Underlay pipe LPT Stutter */
-+	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	/* Selection of Channel(s) containing Compressed Surface: 0xfffffff
-+	 * will disable LPT.
-+	 * STCTRL_LPT_TARGETn corresponds to channel n. */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value_control = dal_read_reg(compressor->ctx, addr);
-+	channels = get_reg_field_value(value_control,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		channels + 1, /* not mentioned in programming guide,
-+				but follow DCE8.1 */
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	/* Enable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dal_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce110_compressor_program_lpt_control(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+	uint32_t rows_per_channel;
-+	uint32_t lpt_alignment;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+	uint32_t lpt_control = 0;
-+
-+	if (!compressor->options.bits.LPT_SUPPORT)
-+		return;
-+
-+	lpt_control = dal_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	/* POSSIBLE VALUES for Low Power Tiling Mode:
-+	 * 00 - Use channel 0
-+	 * 01 - Use Channel 0 and 1
-+	 * 02 - Use Channel 0,1,2,3
-+	 * 03 - reserved */
-+	switch (compressor->lpt_channels_num) {
-+	/* case 2:
-+	 * Use Channel 0 & 1 / Not used for DCE 11 */
-+	case 1:
-+		/*Use Channel 0 for LPT for DCE 11 */
-+		set_reg_field_value(
-+			lpt_control,
-+			0,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+		break;
-+	default:
-+		dal_logger_write(
-+			compressor->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: Invalid selected DRAM channels for LPT!!!",
-+			__func__);
-+		break;
-+	}
-+
-+	lpt_control = lpt_memory_control_config(cp110, lpt_control);
-+
-+	/* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
-+	 * FBC compressed surface pitch.
-+	 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
-+	 * Surface Pitch) / (Row Size * Number of Channels *
-+	 * Number of Banks)). */
-+	rows_per_channel = 0;
-+	lpt_alignment = lpt_size_alignment(cp110);
-+	source_view_width =
-+		align_to_chunks_number_per_line(
-+			cp110,
-+			params->source_view_width);
-+	source_view_height = (params->source_view_height + 1) & (~0x1);
-+
-+	if (lpt_alignment != 0) {
-+		rows_per_channel = source_view_width * source_view_height * 4;
-+		rows_per_channel =
-+			(rows_per_channel % lpt_alignment) ?
-+				(rows_per_channel / lpt_alignment + 1) :
-+				rows_per_channel / lpt_alignment;
-+	}
-+
-+	set_reg_field_value(
-+		lpt_control,
-+		rows_per_channel,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ROWS_PER_CHAN);
-+
-+	dal_write_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL, lpt_control);
-+}
-+
-+/*
-+ * DCE 11 Frame Buffer Compression Implementation
-+ */
-+
-+
-+void dce110_compressor_set_fbc_invalidation_triggers(
-+	struct compressor *compressor,
-+	uint32_t fbc_trigger)
-+{
-+	/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
-+	 * for DCE 11 regions cannot be used - does not work with S/G
-+	 */
-+	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
-+	uint32_t value = dal_read_reg(compressor->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		FBC_CLIENT_REGION_MASK,
-+		FBC_MEMORY_REGION_MASK);
-+	dal_write_reg(compressor->ctx, addr, value);
-+
-+	/* Setup events when to clear all CSM entries (effectively marking
-+	 * current compressed data invalid)
-+	 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
-+	 * Used as the initial value of the metadata sent to the compressor
-+	 * after invalidation, to indicate that the compressor should attempt
-+	 * to compress all chunks on the current pass.  Also used when the chunk
-+	 * is not successfully written to memory.
-+	 * When this CSM value is detected, FBC reads from the uncompressed
-+	 * buffer. Set events according to passed in value, these events are
-+	 * valid for DCE11:
-+	 *     - bit  0 - display register updated
-+	 *     - bit 28 - memory write from any client except from MCIF
-+	 *     - bit 29 - CG static screen signal is inactive
-+	 * In addition, DCE11.1 also needs to set new DCE11.1 specific events
-+	 * that are used to trigger invalidation on certain register changes,
-+	 * for example enabling of Alpha Compression may trigger invalidation of
-+	 * FBC once bit is set. These events are as follows:
-+	 *      - Bit 2 - FBC_GRPH_COMP_EN register updated
-+	 *      - Bit 3 - FBC_SRC_SEL register updated
-+	 *      - Bit 4 - FBC_MIN_COMPRESSION register updated
-+	 *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
-+	 *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
-+	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
-+	 */
-+	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
-+	value = dal_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		fbc_trigger |
-+		FBC_IDLE_FORCE_GRPH_COMP_EN |
-+		FBC_IDLE_FORCE_SRC_SEL_CHANGE |
-+		FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
-+		FBC_IDLE_FORCE_ALPHA_COMP_EN |
-+		FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
-+		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
-+		FBC_IDLE_FORCE_CLEAR_MASK,
-+		FBC_IDLE_FORCE_CLEAR_MASK);
-+	dal_write_reg(compressor->ctx, addr, value);
-+}
-+
-+bool dce110_compressor_construct(struct dce110_compressor *compressor,
-+	struct dc_context *ctx, struct adapter_service *as)
-+{
-+	struct embedded_panel_info panel_info;
-+
-+	compressor->base.options.bits.FBC_SUPPORT = true;
-+	if (!(dal_adapter_service_is_feature_supported(
-+		FEATURE_DISABLE_LPT_SUPPORT)))
-+		compressor->base.options.bits.LPT_SUPPORT = true;
-+	 /* For DCE 11 always use one DRAM channel for LPT */
-+	compressor->base.lpt_channels_num = 1;
-+
-+	if (dal_adapter_service_is_feature_supported(FEATURE_DUMMY_FBC_BACKEND))
-+		compressor->base.options.bits.DUMMY_BACKEND = true;
-+
-+	/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
-+	 * should not be supported */
-+	if (compressor->base.memory_bus_width == 64)
-+		compressor->base.options.bits.LPT_SUPPORT = false;
-+
-+	if (dal_adapter_service_is_feature_supported(
-+		FEATURE_DISABLE_FBC_COMP_CLK_GATE))
-+		compressor->base.options.bits.CLK_GATING_DISABLED = true;
-+
-+	compressor->base.ctx = ctx;
-+	compressor->base.embedded_panel_h_size = 0;
-+	compressor->base.embedded_panel_v_size = 0;
-+	compressor->base.memory_bus_width =
-+		dal_adapter_service_get_asic_vram_bit_width(as);
-+	compressor->base.allocated_size = 0;
-+	compressor->base.preferred_requested_size = 0;
-+	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-+	compressor->base.options.raw = 0;
-+	compressor->base.banks_num = 0;
-+	compressor->base.raw_size = 0;
-+	compressor->base.channel_interleave_size = 0;
-+	compressor->base.dram_channels_num = 0;
-+	compressor->base.lpt_channels_num = 0;
-+	compressor->base.attached_inst = 0;
-+	compressor->base.is_enabled = false;
-+
-+	if (dal_adapter_service_get_embedded_panel_info(as,
-+		&panel_info)) {
-+		compressor->base.embedded_panel_h_size =
-+			panel_info.lcd_timing.horizontal_addressable;
-+		compressor->base.embedded_panel_v_size =
-+			panel_info.lcd_timing.vertical_addressable;
-+	}
-+	return true;
-+}
-+
-+struct compressor *dce110_compressor_create(struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct dce110_compressor *cp110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_compressor));
-+
-+	if (!cp110)
-+		return NULL;
-+
-+	if (dce110_compressor_construct(cp110, ctx, as))
-+		return &cp110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, cp110);
-+	return NULL;
-+}
-+
-+void dce110_compressor_destroy(struct compressor **compressor)
-+{
-+	dc_service_free((*compressor)->ctx, TO_DCE110_COMPRESSOR(*compressor));
-+	*compressor = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
-new file mode 100644
-index 0000000..0beef22
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
-@@ -0,0 +1,84 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMPRESSOR_DCE110_H__
-+#define __DC_COMPRESSOR_DCE110_H__
-+
-+#include "../inc/compressor.h"
-+
-+#define TO_DCE110_COMPRESSOR(compressor)\
-+	container_of(compressor, struct dce110_compressor, base)
-+
-+struct dce110_compressor_reg_offsets {
-+	uint32_t dcp_offset;
-+	uint32_t dmif_offset;
-+};
-+
-+struct dce110_compressor {
-+	struct compressor base;
-+	struct dce110_compressor_reg_offsets offsets;
-+};
-+
-+struct compressor *dce110_compressor_create(struct dc_context *ctx,
-+	struct adapter_service *as);
-+
-+bool dce110_compressor_construct(struct dce110_compressor *cp110,
-+	struct dc_context *ctx, struct adapter_service *as);
-+
-+void dce110_compressor_destroy(struct compressor **cp);
-+
-+/* FBC RELATED */
-+void dce110_compressor_power_up_fbc(struct compressor *cp);
-+
-+void dce110_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params);
-+
-+void dce110_compressor_disable_fbc(struct compressor *cp);
-+
-+void dce110_compressor_set_fbc_invalidation_triggers(struct compressor *cp,
-+	uint32_t fbc_trigger);
-+
-+void dce110_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce110_compressor_get_required_compressed_surface_size(
-+	struct compressor *cp,
-+	struct fbc_input_info *input_info,
-+	struct fbc_requested_compressed_size *size);
-+
-+bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
-+	uint32_t *fbc_mapped_crtc_id);
-+
-+/* LPT RELATED */
-+void dce110_compressor_enable_lpt(struct compressor *cp);
-+
-+void dce110_compressor_disable_lpt(struct compressor *cp);
-+
-+void dce110_compressor_program_lpt_control(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-new file mode 100644
-index 0000000..74294cb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -0,0 +1,1825 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "core_status.h"
-+#include "resource.h"
-+#include "hw_sequencer.h"
-+#include "dc_helpers.h"
-+
-+#include "dce110/dce110_resource.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "dce110/dce110_link_encoder.h"
-+#include "dce110/dce110_stream_encoder.h"
-+#include "stream_encoder_types.h"
-+#include "link_encoder_types.h"
-+#include "dce110/dce110_mem_input.h"
-+#include "dce110/dce110_ipp.h"
-+#include "dce110/dce110_transform.h"
-+#include "dce110/dce110_opp.h"
-+#include "gpu/dce110/dc_clock_gating_dce110.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+struct dce110_hw_seq_reg_offsets {
-+	uint32_t dcfe_offset;
-+	uint32_t blnd_offset;
-+	uint32_t crtc_offset;
-+	uint32_t dcp_offset;
-+};
-+
-+enum crtc_stereo_mixer_mode {
-+	HW_STEREO_MIXER_MODE_INACTIVE,
-+	HW_STEREO_MIXER_MODE_ROW_INTERLEAVE,
-+	HW_STEREO_MIXER_MODE_COLUMN_INTERLEAVE,
-+	HW_STEREO_MIXER_MODE_PIXEL_INTERLEAVE,
-+	HW_STEREO_MIXER_MODE_BLENDER
-+};
-+
-+struct crtc_mixer_params {
-+	bool sub_sampling;
-+	enum crtc_stereo_mixer_mode mode;
-+};
-+
-+enum pipe_lock_control {
-+	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
-+	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
-+	PIPE_LOCK_CONTROL_SCL = 1 << 2,
-+	PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
-+	PIPE_LOCK_CONTROL_MODE = 1 << 4
-+};
-+
-+enum blender_mode {
-+	BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
-+	BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
-+	BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
-+	BLENDER_MODE_STEREO
-+};
-+
-+enum blender_type {
-+	BLENDER_TYPE_NON_SINGLE_PIPE = 0,
-+	BLENDER_TYPE_SB_SINGLE_PIPE,
-+	BLENDER_TYPE_TB_SINGLE_PIPE
-+};
-+
-+enum dc_memory_sleep_state {
-+	DC_MEMORY_SLEEP_DISABLE = 0,
-+	DC_MEMORY_LIGHT_SLEEP,
-+	DC_MEMORY_DEEP_SLEEP,
-+	DC_MEMORY_SHUTDOWN
-+};
-+enum {
-+	DCE110_PIPE_UPDATE_PENDING_DELAY = 1000,
-+	DCE110_PIPE_UPDATE_PENDING_CHECKCOUNT = 5000
-+};
-+
-+static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.blnd_offset = (mmBLND0_BLND_CONTROL - mmBLND0_BLND_CONTROL),
-+	.crtc_offset = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+	.dcp_offset = (mmDCP0_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+},
-+{
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.blnd_offset = (mmBLND1_BLND_CONTROL - mmBLND0_BLND_CONTROL),
-+	.crtc_offset = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+	.dcp_offset = (mmDCP1_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+},
-+{
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.blnd_offset = (mmBLND2_BLND_CONTROL - mmBLND0_BLND_CONTROL),
-+	.crtc_offset = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+	.dcp_offset = (mmDCP2_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+}
-+};
-+
-+#define HW_REG_DCFE(reg, id)\
-+	(reg + reg_offsets[id].dcfe_offset)
-+
-+#define HW_REG_BLND(reg, id)\
-+	(reg + reg_offsets[id].blnd_offset)
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc_offset)
-+
-+#define HW_REG_DCP(reg, id)\
-+	(reg + reg_offsets[id].dcp_offset)
-+
-+
-+static void init_pte(struct dc_context *ctx);
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+
-+static void dce110_enable_display_pipe_clock_gating(
-+	struct dc_context *ctx,
-+	bool clock_gating)
-+{
-+	/*TODO*/
-+}
-+
-+static bool dce110_enable_display_power_gating(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	struct bios_parser *bp,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (!(power_gating == PIPE_GATING_CONTROL_INIT &&
-+					(controller_id + 1) != CONTROLLER_ID_D0))
-+		bp_result = dal_bios_parser_enable_disp_power_gating(
-+						bp, controller_id + 1, cntl);
-+
-+	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-+		init_pte(ctx);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+
-+static bool set_gamma_ramp(
-+	struct input_pixel_processor *ipp,
-+	struct output_pixel_processor *opp,
-+	const struct gamma_ramp *ramp,
-+	const struct gamma_parameters *params)
-+{
-+	/*Power on LUT memory*/
-+	dce110_opp_power_on_regamma_lut(opp, true);
-+
-+	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
-+		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
-+		/* do legacy DCP for 256 colors if we are requested to do so */
-+		dce110_ipp_set_legacy_input_gamma_ramp(
-+			ipp, ramp, params);
-+
-+		dce110_ipp_set_legacy_input_gamma_mode(ipp, true);
-+
-+		/* set bypass */
-+		dce110_ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+
-+		dce110_ipp_set_degamma(ipp, params, true);
-+
-+		dce110_opp_set_regamma(opp, ramp, params, true);
-+	} else if (params->selected_gamma_lut ==
-+			GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA) {
-+		if (!dce110_opp_map_legacy_and_regamma_hw_to_x_user(
-+			opp, ramp, params)) {
-+			BREAK_TO_DEBUGGER();
-+			/* invalid parameters or bug */
-+			return false;
-+		}
-+
-+		/* do legacy DCP for 256 colors if we are requested to do so */
-+		dce110_ipp_set_legacy_input_gamma_ramp(
-+			ipp, ramp, params);
-+
-+		dce110_ipp_set_legacy_input_gamma_mode(ipp, true);
-+
-+		/* set bypass */
-+		dce110_ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+	} else {
-+		dce110_ipp_set_legacy_input_gamma_mode(ipp, false);
-+
-+		dce110_ipp_program_prescale(ipp, params->surface_pixel_format);
-+
-+		/* Do degamma step : remove the given gamma value from FB.
-+		 * For FP16 or no degamma do by pass */
-+		dce110_ipp_set_degamma(ipp, params, false);
-+
-+		dce110_opp_set_regamma(opp, ramp, params, false);
-+	}
-+
-+	/*re-enable low power mode for LUT memory*/
-+	dce110_opp_power_on_regamma_lut(opp, false);
-+
-+	return true;
-+}
-+
-+static enum dc_status bios_parser_crtc_source_select(
-+		struct core_stream *stream)
-+{
-+	/* call VBIOS table to set CRTC source for the HW
-+	 * encoder block
-+	 * note: video bios clears all FMT setting here. */
-+
-+	struct bp_crtc_source_select crtc_source_select = {0};
-+	const struct core_sink *sink = stream->sink;
-+	crtc_source_select.engine_id = stream->stream_enc->id;
-+	crtc_source_select.controller_id = stream->controller_idx + 1;
-+	/*TODO: Need to un-hardcode color depth, dp_audio and account for
-+	 * the case where signal and sink signal is different (translator
-+	 * encoder)*/
-+	crtc_source_select.signal = sink->public.sink_signal;
-+	crtc_source_select.enable_dp_audio = false;
-+	crtc_source_select.sink_signal = sink->public.sink_signal;
-+	crtc_source_select.display_output_bit_depth
-+		= PANEL_8BIT_COLOR;
-+
-+	if (BP_RESULT_OK != dal_bios_parser_crtc_source_select(
-+		dal_adapter_service_get_bios_parser(sink->link->adapter_srv),
-+		&crtc_source_select)) {
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+	return DC_OK;
-+}
-+
-+static enum color_space surface_color_to_color_space(
-+	struct plane_colorimetry *colorimetry)
-+{
-+	enum color_space color_space = COLOR_SPACE_UNKNOWN;
-+
-+	switch (colorimetry->color_space) {
-+	case SURFACE_COLOR_SPACE_SRGB:
-+	case SURFACE_COLOR_SPACE_XRRGB:
-+		if (colorimetry->limited_range)
-+			color_space = COLOR_SPACE_SRGB_LIMITED_RANGE;
-+		else
-+			color_space = COLOR_SPACE_SRGB_FULL_RANGE;
-+		break;
-+	case SURFACE_COLOR_SPACE_BT601:
-+	case SURFACE_COLOR_SPACE_XVYCC_BT601:
-+		color_space = COLOR_SPACE_YCBCR601;
-+		break;
-+	case SURFACE_COLOR_SPACE_BT709:
-+	case SURFACE_COLOR_SPACE_XVYCC_BT709:
-+		color_space = COLOR_SPACE_YCBCR709;
-+		break;
-+	}
-+
-+	return color_space;
-+}
-+
-+/*******************************FMT**************************************/
-+static void program_fmt(
-+		struct output_pixel_processor *opp,
-+		struct bit_depth_reduction_params *fmt_bit_depth,
-+		struct clamping_and_pixel_encoding_params *clamping)
-+{
-+	/* dithering is affected by <CrtcSourceSelect>, hence should be
-+	 * programmed afterwards */
-+
-+	dce110_opp_program_bit_depth_reduction(
-+		opp,
-+		fmt_bit_depth);
-+
-+	dce110_opp_program_clamping_and_pixel_encoding(
-+		opp,
-+		clamping);
-+
-+	return;
-+}
-+
-+/***************************PIPE_CONTROL***********************************/
-+static void enable_fe_clock(
-+	struct dc_context *ctx, uint8_t controller_id, bool enable)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	/*TODO: proper offset*/
-+	addr = HW_REG_DCFE(mmDCFE_CLOCK_CONTROL, controller_id);
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		enable,
-+		DCFE_CLOCK_CONTROL,
-+		DCFE_CLOCK_ENABLE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+/*
-+static void enable_stereo_mixer(
-+	struct dc_context *ctx,
-+	const struct crtc_mixer_params *params)
-+{
-+	TODO
-+}
-+*/
-+static void disable_stereo_mixer(
-+	struct dc_context *ctx)
-+{
-+	/*TODO*/
-+}
-+
-+static void init_pte(struct dc_context *ctx)
-+{
-+	uint32_t addr;
-+	uint32_t value = 0;
-+	uint32_t chunk_int = 0;
-+	uint32_t chunk_mul = 0;
-+
-+	addr = mmUNP_DVMM_PTE_CONTROL;
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DVMM_PTE_CONTROL,
-+		DVMM_USE_SINGLE_PTE);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DVMM_PTE_CONTROL,
-+		DVMM_PTE_BUFFER_MODE0);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DVMM_PTE_CONTROL,
-+		DVMM_PTE_BUFFER_MODE1);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = mmDVMM_PTE_REQ;
-+	value = dal_read_reg(ctx, addr);
-+
-+	chunk_int = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+	chunk_mul = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+	if (chunk_int != 0x4 || chunk_mul != 0x4) {
-+
-+		set_reg_field_value(
-+			value,
-+			255,
-+			DVMM_PTE_REQ,
-+			MAX_PTEREQ_TO_ISSUE);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: enable_disp_power_gating
-+ *
-+ *  @brief
-+ *     enable or disable power gating
-+ *
-+ *  @param [in] enum pipe_gating_control power_gating true - power down,
-+ *  false - power up
-+ *****************************************************************************
-+ */
-+
-+
-+/* this is a workaround for hw bug - it is a trigger on r/w */
-+
-+static void trigger_write_crtc_h_blank_start_end(
-+	struct dc_context *ctx,
-+	uint8_t controller_id)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr =  HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id);
-+	value = dal_read_reg(ctx, addr);
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static bool pipe_control_lock(
-+	struct dc_context *ctx,
-+	uint8_t controller_idx,
-+	uint32_t control_mask,
-+	bool lock)
-+{
-+	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
-+	uint32_t value = dal_read_reg(ctx, addr);
-+	bool need_to_wait = false;
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SCL)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_SCL_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_BLND_V_UPDATE_LOCK);
-+		need_to_wait = true;
-+	}
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_V_UPDATE_LOCK_MODE);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	if (!lock && need_to_wait) {
-+		uint8_t counter = 0;
-+		const uint8_t counter_limit = 100;
-+		const uint16_t delay_us = 1000;
-+
-+		uint8_t pipe_pending;
-+
-+		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
-+				controller_idx);
-+
-+		while (counter < counter_limit) {
-+			value = dal_read_reg(ctx, addr);
-+
-+			pipe_pending = 0;
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						BLND_BLNDC_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					BLND_BLNDO_UPDATE_PENDING);
-+			}
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDC_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDO_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDC_GRPH_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDO_GRPH_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDC_GRPH_SURF_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDO_GRPH_SURF_UPDATE_PENDING);
-+			}
-+
-+			if (pipe_pending == 0)
-+				break;
-+
-+			counter++;
-+			dc_service_delay_in_microseconds(ctx, delay_us);
-+		}
-+
-+		if (counter == counter_limit) {
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: wait for update exceeded (wait %d us)\n",
-+				__func__,
-+				counter * delay_us);
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: control %d, remain value %x\n",
-+				__func__,
-+				control_mask,
-+				value);
-+		} else {
-+			/* OK. */
-+		}
-+	}
-+
-+	if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER))
-+		trigger_write_crtc_h_blank_start_end(ctx, controller_idx);
-+
-+	return true;
-+}
-+
-+static void set_blender_mode(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	enum blender_mode mode)
-+{
-+	uint32_t value;
-+	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-+	uint32_t blnd_mode;
-+	uint32_t feedthrough = 0;
-+
-+	switch (mode) {
-+	case BLENDER_MODE_OTHER_PIPE:
-+		feedthrough = 0;
-+		blnd_mode = 1;
-+		break;
-+	case BLENDER_MODE_BLENDING:
-+		feedthrough = 0;
-+		blnd_mode = 2;
-+		break;
-+	case BLENDER_MODE_CURRENT_PIPE:
-+	default:
-+		feedthrough = 1;
-+		blnd_mode = 0;
-+		break;
-+	}
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		feedthrough,
-+		BLND_CONTROL,
-+		BLND_FEEDTHROUGH_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		blnd_mode,
-+		BLND_CONTROL,
-+		BLND_MODE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+/**************************************************************************/
-+static void update_bios_scratch_critical_state(struct adapter_service *as,
-+		bool state)
-+{
-+	dal_bios_parser_set_scratch_critical_state(
-+		dal_adapter_service_get_bios_parser(as),
-+		state);
-+}
-+
-+static void update_info_frame(struct core_stream *stream)
-+{
-+	dce110_stream_encoder_update_info_packets(
-+		stream->stream_enc,
-+		stream->signal,
-+		&stream->encoder_info_frame);
-+}
-+
-+
-+static void enable_stream(struct core_stream *stream)
-+{
-+	enum lane_count lane_count = LANE_COUNT_ONE;
-+
-+	struct dc_crtc_timing *timing = &stream->public.timing;
-+	struct core_link *link = stream->sink->link;
-+
-+	/* 1. update AVI info frame (HDMI, DP)
-+	 * we always need to update info frame
-+	*/
-+	uint32_t active_total_with_borders;
-+	uint32_t early_control = 0;
-+	struct timing_generator *tg = stream->tg;
-+
-+	update_info_frame(stream);
-+	/* enable early control to avoid corruption on DP monitor*/
-+	active_total_with_borders =
-+			timing->h_addressable
-+				+ timing->h_border_left
-+				+ timing->h_border_right;
-+
-+	early_control = active_total_with_borders % lane_count;
-+
-+	if (early_control == 0)
-+		early_control = lane_count;
-+
-+	dce110_timing_generator_set_early_control(tg, early_control);
-+
-+	/* enable audio only within mode set */
-+	if (stream->audio != NULL) {
-+		dal_audio_enable_output(
-+			stream->audio,
-+			stream->stream_enc->id,
-+			stream->signal);
-+	}
-+
-+	/* For MST, there are multiply stream go to only one link.
-+	 * connect DIG back_end to front_end while enable_stream and
-+	 * disconnect them during disable_stream
-+	 * BY this, it is logic clean to separate stream and link */
-+	dce110_link_encoder_connect_dig_be_to_fe(link->link_enc,
-+			stream->stream_enc->id, true);
-+
-+}
-+
-+static void disable_stream(struct core_stream *stream)
-+{
-+	struct core_link *link = stream->sink->link;
-+
-+	dce110_stream_encoder_stop_info_packets(
-+		stream->stream_enc,
-+		stream->stream_enc->id,
-+		stream->signal);
-+
-+	if (stream->audio) {
-+		/* mute audio */
-+		dal_audio_mute(stream->audio, stream->stream_enc->id,
-+				stream->signal);
-+
-+		/* TODO: notify audio driver for if audio modes list changed
-+		 * add audio mode list change flag */
-+		/* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
-+		 * stream->stream_engine_id);
-+		 */
-+	}
-+
-+	/* blank at encoder level */
-+	dce110_stream_encoder_blank(stream->stream_enc, stream->signal);
-+	dce110_link_encoder_connect_dig_be_to_fe(
-+			link->link_enc,
-+			stream->stream_enc->id,
-+			false);
-+
-+}
-+
-+static void unblank_stream(struct core_stream *stream,
-+		struct link_settings *link_settings)
-+{
-+	struct encoder_unblank_param params = { { 0 } };
-+
-+	/* only 3 items below are used by unblank */
-+	params.crtc_timing.pixel_clock =
-+		stream->public.timing.pix_clk_khz;
-+	params.link_settings.link_rate = link_settings->link_rate;
-+	params.signal = stream->signal;
-+	dce110_stream_encoder_unblank(
-+		stream->stream_enc, &params);
-+}
-+
-+static enum color_space get_output_color_space(
-+				const struct dc_crtc_timing *dc_crtc_timing)
-+{
-+	enum color_space color_space = COLOR_SPACE_SRGB_FULL_RANGE;
-+
-+	switch (dc_crtc_timing->pixel_encoding)	{
-+	case PIXEL_ENCODING_YCBCR422:
-+	case PIXEL_ENCODING_YCBCR444:
-+	case PIXEL_ENCODING_YCBCR420:
-+	{
-+		if ((dc_crtc_timing->timing_standard ==
-+			TIMING_STANDARD_CEA770) ||
-+			(dc_crtc_timing->timing_standard ==
-+				TIMING_STANDARD_CEA861)) {
-+			if (dc_crtc_timing->pix_clk_khz > 27030) {
-+				if (dc_crtc_timing->flags.Y_ONLY)
-+					color_space =
-+						COLOR_SPACE_YCBCR709_YONLY;
-+				else
-+					color_space = COLOR_SPACE_YCBCR709;
-+			} else {
-+				if (dc_crtc_timing->flags.Y_ONLY)
-+					color_space =
-+						COLOR_SPACE_YCBCR601_YONLY;
-+				else
-+					color_space = COLOR_SPACE_YCBCR601;
-+			}
-+		}
-+	}
-+	break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return color_space;
-+}
-+
-+static enum dc_status allocate_mst_payload(struct core_stream *stream)
-+{
-+	struct link_encoder *link_encoder = stream->sink->link->link_enc;
-+	struct stream_encoder *stream_encoder = stream->stream_enc;
-+	struct dp_mst_stream_allocation_table table;
-+	struct fixed31_32 avg_time_slots_per_mtp;
-+
-+	/* TODO: remove hardcode */
-+	table.stream_count = 1;
-+	table.stream_allocations[0].engine = stream_encoder->id;
-+
-+	dc_helpers_dp_mst_write_payload_allocation_table(
-+		stream->ctx,
-+		&stream->sink->public,
-+		&table.stream_allocations[0],
-+		true);
-+
-+	dce110_link_encoder_update_mst_stream_allocation_table(
-+		link_encoder,
-+		&table,
-+		false);
-+
-+	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+			stream->ctx,
-+			&stream->sink->public);
-+
-+	dc_helpers_dp_mst_send_payload_allocation(
-+			stream->ctx,
-+			&stream->sink->public,
-+			true);
-+
-+	avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
-+			table.stream_allocations[0].pbn,
-+			table.stream_allocations[0].pbn_per_slot);
-+
-+	dce110_link_encoder_set_mst_bandwidth(
-+		link_encoder,
-+		stream_encoder->id,
-+		avg_time_slots_per_mtp);
-+
-+	return DC_OK;
-+
-+}
-+
-+static enum dc_status deallocate_mst_payload(struct core_stream *stream)
-+{
-+	struct link_encoder *link_encoder = stream->sink->link->link_enc;
-+	struct stream_encoder *stream_encoder = stream->stream_enc;
-+	struct dp_mst_stream_allocation_table table;
-+	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
-+
-+	/* TODO: remove hardcode */
-+	table.stream_count = 1;
-+	table.stream_allocations[0].slot_count = 0;
-+
-+	dce110_link_encoder_set_mst_bandwidth(
-+		link_encoder,
-+		stream_encoder->id,
-+		avg_time_slots_per_mtp);
-+
-+	dc_helpers_dp_mst_write_payload_allocation_table(
-+		stream->ctx,
-+		&stream->sink->public,
-+		&table.stream_allocations[0],
-+		false);
-+
-+	dce110_link_encoder_update_mst_stream_allocation_table(
-+		link_encoder,
-+		&table,
-+		false);
-+
-+	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+			stream->ctx,
-+			&stream->sink->public);
-+
-+	dc_helpers_dp_mst_send_payload_allocation(
-+			stream->ctx,
-+			&stream->sink->public,
-+			false);
-+
-+
-+	return DC_OK;
-+
-+}
-+
-+static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
-+		struct validate_context *context,
-+		const struct dc *dc)
-+{
-+	struct core_stream *stream =
-+			context->res_ctx.controller_ctx[controller_idx].stream;
-+
-+	struct output_pixel_processor *opp =
-+		context->res_ctx.pool.opps[controller_idx];
-+	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
-+			.flags.timing_changed;
-+	enum color_space color_space;
-+
-+	if (timing_changed) {
-+
-+		disable_stream(stream);
-+		core_link_disable(stream);
-+
-+		/*TODO: AUTO check if timing changed*/
-+		if (false == dal_clock_source_program_pix_clk(
-+				stream->clock_source,
-+				&stream->pix_clk_params,
-+				&stream->pll_settings)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+
-+
-+		if (false == dce110_timing_generator_program_timing_generator(
-+				stream->tg,
-+				&stream->public.timing)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+	}
-+
-+	/*TODO: mst support - use total stream count*/
-+	dce110_allocate_dmif_buffer(stream->mi,
-+			&stream->public.timing,
-+			context->target_count);
-+
-+	if (timing_changed) {
-+		if (false == dce110_timing_generator_enable_crtc(
-+				stream->tg)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+	}
-+
-+	if (DC_OK != bios_parser_crtc_source_select(stream)) {
-+		BREAK_TO_DEBUGGER();
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	dce110_opp_set_dyn_expansion(
-+			opp,
-+			COLOR_SPACE_YCBCR601,
-+			stream->public.timing.display_color_depth,
-+			stream->sink->public.sink_signal);
-+
-+	program_fmt(
-+			opp,
-+			&stream->fmt_bit_depth,
-+			&stream->clamping);
-+
-+	dce110_link_encoder_setup(
-+		stream->sink->link->link_enc,
-+		stream->signal);
-+	if (ENCODER_RESULT_OK != dce110_stream_encoder_setup(
-+			stream->stream_enc,
-+			&stream->public.timing,
-+			stream->signal,
-+			stream->audio != NULL)) {
-+		BREAK_TO_DEBUGGER();
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	if (stream->audio != NULL) {
-+		if (AUDIO_RESULT_OK != dal_audio_setup(
-+				stream->audio,
-+				&stream->audio_output,
-+				&stream->public.audio_info)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+	}
-+
-+	/* Setup audio rate clock source */
-+	if (stream->audio != NULL)
-+		dal_audio_setup_audio_wall_dto(
-+				stream->audio,
-+				stream->signal,
-+				&stream->audio_output.crtc_info,
-+				&stream->audio_output.pll_info);
-+
-+	/* program blank color */
-+	color_space = get_output_color_space(
-+			&stream->public.timing);
-+
-+	dce110_timing_generator_program_blank_color(
-+			context->res_ctx.pool.timing_generators[controller_idx],
-+			color_space);
-+
-+	if (timing_changed) {
-+		enable_stream(stream);
-+
-+		if (DC_OK != core_link_enable(stream)) {
-+				BREAK_TO_DEBUGGER();
-+				return DC_ERROR_UNEXPECTED;
-+		}
-+		if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+			allocate_mst_payload(stream);
-+
-+	}
-+
-+	unblank_stream(stream, &stream->sink->link->cur_link_settings);
-+
-+	return DC_OK;
-+}
-+
-+
-+/******************************************************************************/
-+
-+static void power_down_encoders(struct validate_context *context)
-+{
-+	int i;
-+	struct core_target *target;
-+	struct core_stream *stream;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		target = context->targets[i];
-+		stream = target->streams[0];
-+		core_link_disable(stream);
-+	}
-+}
-+
-+static void power_down_controllers(struct validate_context *context)
-+{
-+	int i;
-+	struct core_target *target;
-+	struct core_stream *stream;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		target = context->targets[i];
-+		stream = target->streams[0];
-+
-+		dce110_timing_generator_disable_crtc(stream->tg);
-+	}
-+}
-+
-+static void power_down_clock_sources(struct validate_context *context)
-+{
-+	int i;
-+	struct core_target *target;
-+	struct core_stream *stream;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		target = context->targets[i];
-+		stream = target->streams[0];
-+
-+		if (false == dal_clock_source_power_down_pll(
-+				stream->clock_source,
-+				stream->controller_idx + 1)) {
-+			dal_error(
-+				"Failed to power down pll! (clk src index=%d)\n",
-+				i);
-+		}
-+	}
-+}
-+
-+static void power_down_all_hw_blocks(struct validate_context *context)
-+{
-+	power_down_encoders(context);
-+
-+	power_down_controllers(context);
-+
-+	power_down_clock_sources(context);
-+}
-+
-+static void disable_vga_and_power_gate_all_controllers(
-+		struct validate_context *context)
-+{
-+	int i;
-+	struct core_target *target;
-+	struct core_stream *stream;
-+	struct timing_generator *tg;
-+	struct bios_parser *bp;
-+	struct dc_context *ctx;
-+	uint8_t controller_id;
-+
-+	bp = dal_adapter_service_get_bios_parser(
-+				context->res_ctx.pool.adapter_srv);
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		target = context->targets[i];
-+		stream = target->streams[0];
-+		tg = stream->tg;
-+		ctx = stream->ctx;
-+		controller_id = stream->controller_idx;
-+
-+		dce110_timing_generator_disable_vga(tg);
-+
-+		/* Enable CLOCK gating for each pipe BEFORE controller
-+		 * powergating. */
-+		dce110_enable_display_pipe_clock_gating(ctx,
-+				true);
-+		dce110_enable_display_power_gating(ctx, controller_id, bp,
-+				PIPE_GATING_CONTROL_ENABLE);
-+	}
-+}
-+
-+/**
-+ * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
-+ *  1. Power down all DC HW blocks
-+ *  2. Disable VGA engine on all controllers
-+ *  3. Enable power gating for controller
-+ *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
-+ */
-+static void enable_accelerated_mode(struct validate_context *context)
-+{
-+	struct bios_parser *bp;
-+
-+	bp = dal_adapter_service_get_bios_parser(
-+			context->res_ctx.pool.adapter_srv);
-+
-+	power_down_all_hw_blocks(context);
-+
-+	disable_vga_and_power_gate_all_controllers(context);
-+
-+	dal_bios_parser_set_scratch_acc_mode_change(bp);
-+}
-+
-+#if 0
-+static enum clocks_state get_required_clocks_state(
-+	struct display_clock *display_clock,
-+	struct state_dependent_clocks *req_state_dep_clks)
-+{
-+	enum clocks_state clocks_required_state;
-+	enum clocks_state dp_link_required_state;
-+	enum clocks_state overall_required_state;
-+
-+	clocks_required_state = dal_display_clock_get_required_clocks_state(
-+			display_clock, req_state_dep_clks);
-+
-+	dp_link_required_state = CLOCKS_STATE_ULTRA_LOW;
-+
-+	/* overall required state is the max of required state for clocks
-+	 * (pixel, display clock) and the required state for DP link. */
-+	overall_required_state =
-+		clocks_required_state > dp_link_required_state ?
-+			clocks_required_state : dp_link_required_state;
-+
-+	/* return the min required state */
-+	return overall_required_state;
-+}
-+
-+static bool dc_pre_clock_change(
-+		struct dc_context *ctx,
-+		struct minimum_clocks_calculation_result *min_clk_in,
-+		enum clocks_state required_clocks_state,
-+		struct power_to_dal_info *output)
-+{
-+	struct dal_to_power_info input = {0};
-+
-+	input.min_deep_sleep_sclk = min_clk_in->min_deep_sleep_sclk;
-+	input.min_mclk = min_clk_in->min_mclk_khz;
-+	input.min_sclk = min_clk_in->min_sclk_khz;
-+
-+	switch (required_clocks_state) {
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		input.required_clock = PP_CLOCKS_STATE_ULTRA_LOW;
-+		break;
-+	case CLOCKS_STATE_LOW:
-+		input.required_clock = PP_CLOCKS_STATE_LOW;
-+		break;
-+	case CLOCKS_STATE_NOMINAL:
-+		input.required_clock = PP_CLOCKS_STATE_NOMINAL;
-+		break;
-+	case CLOCKS_STATE_PERFORMANCE:
-+		input.required_clock = PP_CLOCKS_STATE_PERFORMANCE;
-+		break;
-+	default:
-+		input.required_clock = PP_CLOCKS_STATE_NOMINAL;
-+		break;
-+	}
-+
-+	if (!dc_service_pp_pre_dce_clock_change(ctx, &input, output)) {
-+		dal_error("DC: dc_service_pp_pre_dce_clock_change failed!\n");
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool dc_set_clocks_and_clock_state (
-+		struct validate_context *context)
-+{
-+	struct power_to_dal_info output = {0};
-+
-+	struct display_clock *disp_clk = context->res_ctx.pool.display_clock;
-+	struct dc_context *ctx = context->targets[0]->ctx;
-+
-+
-+	if (!dc_pre_clock_change(
-+			ctx,
-+			&context->res_ctx.min_clocks,
-+			get_required_clocks_state(
-+					context->res_ctx.pool.display_clock,
-+					&context->res_ctx.state_clocks),
-+			&output)) {
-+		/* "output" was not updated by PPLib.
-+		 * DAL will use default values for set mode.
-+		 *
-+		 * Do NOT fail this call. */
-+		return true;
-+	}
-+
-+	/* PPLib accepted the "clock state" that we need, that means we
-+	 * can store it as minimum state because PPLib guarantees not go below
-+	 * that state.
-+	 *
-+	 * Update the clock state here (prior to setting Pixel clock,
-+	 * DVO clock, or Display clock) */
-+	if (!dal_display_clock_set_min_clocks_state(
-+			disp_clk, context->res_ctx.required_clocks_state)) {
-+		BREAK_TO_DEBUGGER();
-+		dal_error("DC: failed to set minimum clock state!\n");
-+	}
-+
-+
-+	/*bm_clk_info.max_mclk_khz = output.max_mclk;
-+	bm_clk_info.min_mclk_khz = output.min_mclk;
-+	bm_clk_info.max_sclk_khz = output.max_sclk;
-+	bm_clk_info.min_sclk_khz = output.min_sclk;*/
-+
-+	/* Now let Bandwidth Manager know about values we got from PPLib. */
-+	/*dal_bandwidth_manager_set_dynamic_clock_info(bw_mgr, &bm_clk_info);*/
-+
-+	return true;
-+}
-+#endif
-+
-+/**
-+ * Call display_engine_clock_dce80 to perform the Dclk programming.
-+ */
-+static void set_display_clock(struct validate_context *context)
-+{
-+	/* Program the display engine clock.
-+	 * Check DFS bypass mode support or not. DFSbypass feature is only when
-+	 * BIOS GPU info table reports support. */
-+
-+	if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
-+		/*TODO: set_display_clock_dfs_bypass(
-+				hws,
-+				path_set,
-+				context->res_ctx.pool.display_clock,
-+				context->res_ctx.min_clocks.min_dclk_khz);*/
-+	} else
-+		dal_display_clock_set_clock(context->res_ctx.pool.display_clock,
-+				context->bw_results.dispclk);
-+
-+	/* TODO: When changing display engine clock, DMCU WaitLoop must be
-+	 * reconfigured in order to maintain the same delays within DMCU
-+	 * programming sequences. */
-+
-+	/* TODO: Start GTC counter */
-+}
-+
-+static void set_displaymarks(
-+	const struct dc *dc, struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	uint8_t total_streams = 0;
-+	uint8_t target_count = context->target_count;
-+
-+	for (i = 0; i < target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->stream_count; j++) {
-+			struct core_stream *stream = target->streams[j];
-+
-+			dce110_program_nbp_watermark(
-+				stream->mi,
-+				context->bw_results
-+				.nbp_state_change_watermark[total_streams]);
-+
-+			dce110_program_stutter_watermark(
-+				stream->mi,
-+				context->bw_results
-+					.stutter_exit_watermark[total_streams]);
-+
-+			dce110_program_urgency_watermark(
-+				stream->mi,
-+				context->bw_results
-+					.urgent_watermark[total_streams],
-+				stream->public.timing.h_total,
-+				stream->public.timing.pix_clk_khz,
-+				1000 * dc->bw_vbios.blackout_duration
-+								.value >> 24);
-+			total_streams++;
-+		}
-+	}
-+}
-+
-+static void set_safe_displaymarks(struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	uint8_t target_count = context->target_count;
-+
-+	for (i = 0; i < target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->stream_count; j++) {
-+			struct core_stream *stream = target->streams[j];
-+
-+			dce110_program_safe_display_marks(stream->mi);
-+		}
-+	}
-+}
-+
-+static void dce110_program_bw(struct dc *dc, struct validate_context *context)
-+{
-+	set_safe_displaymarks(&dc->current_context);
-+	/*TODO: when pplib works*/
-+	/*dc_set_clocks_and_clock_state(context);*/
-+
-+	set_display_clock(&dc->current_context);
-+	set_displaymarks(dc, &dc->current_context);
-+}
-+
-+/*TODO: break out clock sources like timing gen/ encoder*/
-+static void dce110_switch_dp_clk_src(
-+	const struct dc_context *ctx,
-+	const struct core_stream *stream)
-+{
-+	uint32_t pixel_rate_cntl_value;
-+	uint32_t addr;
-+	enum clock_source_id id = dal_clock_source_get_id(stream->clock_source);
-+
-+	/*TODO: proper offset*/
-+	addr = mmCRTC0_PIXEL_RATE_CNTL + stream->controller_idx *
-+			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-+
-+	pixel_rate_cntl_value = dal_read_reg(ctx, addr);
-+
-+	if (id == CLOCK_SOURCE_ID_EXTERNAL) {
-+
-+		if (!get_reg_field_value(pixel_rate_cntl_value,
-+				CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE)) {
-+
-+			set_reg_field_value(pixel_rate_cntl_value, 1,
-+				CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
-+		}
-+
-+	} else {
-+		set_reg_field_value(pixel_rate_cntl_value,
-+				0,
-+				CRTC0_PIXEL_RATE_CNTL,
-+				DP_DTO0_ENABLE);
-+
-+		set_reg_field_value(pixel_rate_cntl_value,
-+				id - 1,
-+				CRTC0_PIXEL_RATE_CNTL,
-+				CRTC0_PIXEL_RATE_SOURCE);
-+	}
-+	dal_write_reg(ctx, addr, pixel_rate_cntl_value);
-+}
-+
-+static void switch_dp_clock_sources(
-+	const struct dc_context *ctx,
-+	struct validate_context *val_context)
-+{
-+	uint8_t i, j;
-+	for (i = 0; i < val_context->target_count; i++) {
-+		struct core_target *target = val_context->targets[i];
-+		for (j = 0; j < target->stream_count; j++) {
-+			struct core_stream *stream = target->streams[j];
-+
-+			if (dc_is_dp_signal(stream->signal)) {
-+				struct clock_source *clk_src =
-+					find_used_clk_src_for_sharing(
-+							val_context, stream);
-+
-+				if (clk_src != stream->clock_source) {
-+					unreference_clock_source(
-+							&val_context->res_ctx,
-+							stream->clock_source);
-+					stream->clock_source = clk_src;
-+					reference_clock_source(
-+						&val_context->res_ctx, clk_src);
-+					dce110_switch_dp_clk_src(ctx, stream);
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+/*TODO: const validate_context*/
-+static enum dc_status apply_ctx_to_hw(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	enum dc_status status;
-+	uint8_t i;
-+	struct resource_pool *pool = &context->res_ctx.pool;
-+
-+	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
-+			true);
-+	set_safe_displaymarks(context);
-+	/*TODO: when pplib works*/
-+	/*dc_set_clocks_and_clock_state(context);*/
-+
-+	set_display_clock(context);
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		struct controller_ctx *ctlr_ctx
-+			= &context->res_ctx.controller_ctx[i];
-+		if (ctlr_ctx->flags.unchanged || !ctlr_ctx->stream)
-+			continue;
-+
-+		status = apply_single_controller_ctx_to_hw(
-+				i,
-+				context,
-+				dc);
-+
-+		if (DC_OK != status)
-+			return status;
-+	}
-+	set_displaymarks(dc, context);
-+
-+	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
-+			false);
-+
-+	switch_dp_clock_sources(dc->ctx, context);
-+
-+	return DC_OK;
-+}
-+
-+
-+/*******************************************************************************
-+ * Front End programming
-+ ******************************************************************************/
-+
-+static bool setup_line_buffer_pixel_depth(
-+	const struct core_stream *stream,
-+	enum lb_pixel_depth depth,
-+	bool blank)
-+{
-+	enum lb_pixel_depth current_depth;
-+
-+	struct timing_generator *tg = stream->tg;
-+	struct transform *xfm = stream->xfm;
-+
-+	if (!dce110_transform_get_current_pixel_storage_depth(
-+		xfm,
-+		&current_depth))
-+		return false;
-+
-+	if (current_depth != depth) {
-+		if (blank)
-+			dce110_timing_generator_wait_for_vblank(tg);
-+
-+		return dce110_transform_set_pixel_storage_depth(xfm, depth);
-+	}
-+
-+	return false;
-+}
-+
-+static void hw_sequencer_build_scaler_parameter_plane(
-+		const struct core_stream *stream,
-+		struct scaler_data *scaler_data)
-+{
-+	/*TODO: per pipe not per stream*/
-+	/*TODO: get from feature from adapterservice*/
-+	scaler_data->flags.bits.SHOW_COLOURED_BORDER = false;
-+
-+	scaler_data->flags.bits.SHOULD_PROGRAM_ALPHA = 1;
-+
-+	scaler_data->flags.bits.SHOULD_PROGRAM_VIEWPORT = 0;
-+
-+	scaler_data->flags.bits.SHOULD_UNLOCK = 0;
-+
-+	scaler_data->flags.bits.INTERLACED = 0;
-+
-+	scaler_data->dal_pixel_format = stream->format;
-+
-+	scaler_data->taps = stream->taps;
-+
-+	scaler_data->viewport = stream->viewport;
-+
-+	scaler_data->overscan = stream->overscan;
-+
-+	scaler_data->ratios = &stream->ratios;
-+
-+	/*TODO rotation and adjustment */
-+	scaler_data->h_sharpness = 0;
-+	scaler_data->v_sharpness = 0;
-+
-+}
-+
-+static void set_default_colors(
-+				struct input_pixel_processor *ipp,
-+				struct output_pixel_processor *opp,
-+				enum pixel_format format,
-+				enum color_space input_color_space,
-+				enum color_space output_color_space,
-+				enum dc_color_depth color_depth)
-+{
-+	struct default_adjustment default_adjust = { 0 };
-+
-+	default_adjust.force_hw_default = false;
-+	default_adjust.color_space = output_color_space;
-+	default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
-+	default_adjust.surface_pixel_format = format;
-+
-+	/* display color depth */
-+	default_adjust.color_depth = color_depth;
-+
-+	/* Lb color depth */
-+	default_adjust.lb_color_depth = LB_PIXEL_DEPTH_24BPP;
-+	/*dal_hw_sequencer_translate_to_lb_color_depth(
-+			build_params->
-+			line_buffer_params[path_id][plane_id].depth);*/
-+
-+	dce110_opp_set_csc_default(opp, &default_adjust);
-+}
-+
-+static void program_scaler(
-+	uint8_t controller_idx,
-+	struct timing_generator *tg,
-+	struct transform *xfm,
-+	const struct core_surface *surface,
-+	const struct core_stream *stream)
-+{
-+	struct scaler_data scaler_data = { { 0 } };
-+
-+	hw_sequencer_build_scaler_parameter_plane(
-+		stream,
-+		&scaler_data);
-+
-+	setup_line_buffer_pixel_depth(
-+		stream,
-+		LB_PIXEL_DEPTH_24BPP,
-+		false);
-+
-+	dce110_timing_generator_set_overscan_color_black(
-+			tg,
-+			surface->public.colorimetry.color_space);
-+
-+	dce110_transform_set_scaler(xfm, &scaler_data);
-+
-+	dce110_transform_update_viewport(
-+			xfm,
-+			&scaler_data.viewport,
-+			false);
-+}
-+
-+
-+
-+static void configure_locking(struct dc_context *ctx, uint8_t controller_id)
-+{
-+	/* main controller should be in mode 0 (master pipe) */
-+	pipe_control_lock(
-+			ctx,
-+			controller_id,
-+			PIPE_LOCK_CONTROL_MODE,
-+			false);
-+
-+	/* TODO: for MPO finish the non-root controllers */
-+}
-+
-+/**
-+ * Program the Front End of the Pipe.
-+ * The Back End was already programmed by Set Mode.
-+ */
-+static bool set_plane_config(
-+	struct core_surface *surface,
-+	struct core_target *target)
-+{
-+	const struct dc_crtc_timing *dc_crtc_timing =
-+			&target->streams[0]->public.timing;
-+	struct mem_input *mi = target->streams[0]->mi;
-+	struct input_pixel_processor *ipp = target->streams[0]->ipp;
-+	struct timing_generator *tg = target->streams[0]->tg;
-+	struct transform *xfm = target->streams[0]->xfm;
-+	struct output_pixel_processor *opp = target->streams[0]->opp;
-+	struct dc_context *ctx = target->streams[0]->ctx;
-+	uint8_t controller_idx = target->streams[0]->controller_idx;
-+
-+	/* TODO: Clean up change, possibly change to use same type */
-+	enum color_space input_color_space =
-+					surface_color_to_color_space(&(surface->public.colorimetry));
-+
-+	configure_locking(ctx, controller_idx);
-+
-+	/* While a non-root controller is programmed we
-+	 * have to lock the root controller. */
-+	pipe_control_lock(
-+			ctx,
-+			controller_idx,
-+			PIPE_LOCK_CONTROL_GRAPHICS |
-+			PIPE_LOCK_CONTROL_SCL |
-+			PIPE_LOCK_CONTROL_BLENDER |
-+			PIPE_LOCK_CONTROL_SURFACE,
-+			true);
-+
-+	dce110_program_pix_dur(mi, dc_crtc_timing->pix_clk_khz);
-+
-+	dce110_timing_generator_program_blanking(tg, dc_crtc_timing);
-+
-+	enable_fe_clock(ctx, controller_idx, true);
-+
-+	set_default_colors(
-+			ipp,
-+			opp,
-+			target->streams[0]->format,
-+			input_color_space,
-+			get_output_color_space(dc_crtc_timing),
-+			dc_crtc_timing->display_color_depth);
-+
-+	/* program Scaler */
-+	program_scaler(
-+		controller_idx, tg, xfm, surface, target->streams[0]);
-+
-+	set_blender_mode(
-+			ctx,
-+			controller_idx,
-+			BLENDER_MODE_CURRENT_PIPE);
-+
-+#if 0
-+	program_alpha_mode(
-+			crtc,
-+			&pl_cfg->attributes.blend_flags,
-+			path_mode->mode.timing.pixel_encoding);
-+#endif
-+
-+	dce110_mem_input_program_surface_config(
-+			mi,
-+			&surface->public);
-+
-+	pipe_control_lock(
-+			ctx,
-+			controller_idx,
-+			PIPE_LOCK_CONTROL_GRAPHICS |
-+			PIPE_LOCK_CONTROL_SCL |
-+			PIPE_LOCK_CONTROL_BLENDER |
-+			PIPE_LOCK_CONTROL_SURFACE,
-+			false);
-+
-+	return true;
-+}
-+
-+static bool update_plane_address(
-+	const struct core_surface *surface,
-+	struct core_target *target)
-+{
-+	struct dc_context *ctx = target->streams[0]->ctx;
-+	struct mem_input *mi = target->streams[0]->mi;
-+	uint8_t controller_id = target->streams[0]->controller_idx;
-+
-+	/* TODO: crtc should be per surface, NOT per-target */
-+	pipe_control_lock(
-+		ctx,
-+		controller_id,
-+		PIPE_LOCK_CONTROL_SURFACE,
-+		true);
-+
-+	if (false == dce110_mem_input_program_surface_flip_and_addr(
-+		mi, &surface->public.address, surface->public.flip_immediate))
-+		return false;
-+
-+	pipe_control_lock(
-+		ctx,
-+		controller_id,
-+		PIPE_LOCK_CONTROL_SURFACE,
-+		false);
-+
-+	return true;
-+}
-+
-+static void reset_single_stream_hw_ctx(struct core_stream *stream,
-+		struct validate_context *context)
-+{
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		deallocate_mst_payload(stream);
-+
-+	disable_stream(stream);
-+	if (stream->audio) {
-+		dal_audio_disable_output(stream->audio,
-+				stream->stream_enc->id,
-+				stream->signal);
-+		stream->audio = NULL;
-+	}
-+
-+	core_link_disable(stream);
-+	dce110_timing_generator_blank_crtc(stream->tg);
-+	dce110_timing_generator_disable_crtc(stream->tg);
-+	dce110_deallocate_dmif_buffer(stream->mi, context->target_count);
-+	dce110_transform_set_scaler_bypass(stream->xfm);
-+	disable_stereo_mixer(stream->ctx);
-+	unreference_clock_source(&context->res_ctx, stream->clock_source);
-+}
-+
-+static void reset_hw_ctx(struct dc *dc,
-+		struct validate_context *context,
-+		uint8_t target_count)
-+{
-+	uint8_t i;
-+	/* look up the targets that have been removed since last commit */
-+	for (i = 0; i < dc->current_context.target_count; i++) {
-+		uint8_t controller_idx = dc->current_context.targets[i]->
-+						streams[0]->controller_idx;
-+
-+		if (context->res_ctx.controller_ctx[controller_idx].stream &&
-+				!context->res_ctx.controller_ctx[controller_idx]
-+				.flags.timing_changed)
-+			continue;
-+
-+		reset_single_stream_hw_ctx(
-+			dc->current_context.targets[i]->streams[0],
-+			&dc->current_context);
-+	}
-+}
-+
-+static void power_down(struct validate_context *context)
-+{
-+	power_down_all_hw_blocks(context);
-+	disable_vga_and_power_gate_all_controllers(context);
-+
-+}
-+
-+static bool wait_for_reset_trigger_to_occur(
-+	struct dc_context *dc_ctx,
-+	struct timing_generator *tg)
-+{
-+	bool rc = false;
-+
-+	/* To avoid endless loop we wait at most
-+	 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
-+	const uint32_t frames_to_wait_on_triggered_reset = 10;
-+	uint32_t i;
-+
-+	for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
-+
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			DC_ERROR("TG counter is not moving!\n");
-+			break;
-+		}
-+
-+		if (dce110_timing_generator_did_triggered_reset_occur(tg)) {
-+			rc = true;
-+			/* usually occurs at i=1 */
-+			DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
-+					i);
-+			break;
-+		}
-+
-+		/* Wait for one frame. */
-+		dce110_timing_generator_wait_for_vactive(tg);
-+		dce110_timing_generator_wait_for_vblank(tg);
-+	}
-+
-+	if (false == rc)
-+		DC_ERROR("GSL: Timeout on reset trigger!\n");
-+
-+	return rc;
-+}
-+
-+/* Enable timing synchronization for a group of Timing Generators. */
-+static void enable_timing_synchronization(
-+	struct dc_context *dc_ctx,
-+	uint32_t timing_generator_num,
-+	struct timing_generator *tgs[])
-+{
-+	struct dcp_gsl_params gsl_params = { 0 };
-+	struct trigger_params trigger_params;
-+	uint32_t i;
-+
-+	DC_SYNC_INFO("GSL: Setting-up...\n");
-+
-+	gsl_params.gsl_group = SYNC_SOURCE_GSL_GROUP0;
-+	gsl_params.gsl_purpose = DCP_GSL_PURPOSE_SURFACE_FLIP;
-+
-+	for (i = 0; i < timing_generator_num; i++) {
-+		/* Designate a single TG in the group as a master.
-+		 * Since HW doesn't care which one, we always assign
-+		 * the 1st one in the group. */
-+		gsl_params.timing_server = (0 == i ? true : false);
-+
-+		dce110_timing_generator_setup_global_swap_lock(tgs[i],
-+				&gsl_params);
-+	}
-+
-+	/* Reset slave controllers on master VSync */
-+	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
-+	dc_service_memset(&trigger_params, 0, sizeof(trigger_params));
-+
-+	trigger_params.edge = TRIGGER_EDGE_DEFAULT;
-+	trigger_params.source = SYNC_SOURCE_GSL_GROUP0;
-+
-+	for (i = 1 /* skip the master */; i < timing_generator_num; i++) {
-+		dce110_timing_generator_enable_reset_trigger(tgs[i],
-+				&trigger_params);
-+
-+		DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
-+		wait_for_reset_trigger_to_occur(dc_ctx, tgs[i]);
-+
-+		/* Regardless of success of the wait above, remove the reset or
-+		 * the driver will start timing out on Display requests. */
-+		DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
-+		dce110_timing_generator_disable_reset_trigger(tgs[i]);
-+	}
-+
-+	/* GSL Vblank synchronization is a one time sync mechanism, assumption
-+	 * is that the sync'ed displays will not drift out of sync over time*/
-+	DC_SYNC_INFO("GSL: Restoring register states.\n");
-+	for (i = 0; i < timing_generator_num; i++)
-+		dce110_timing_generator_tear_down_global_swap_lock(tgs[i]);
-+
-+	DC_SYNC_INFO("GSL: Set-up complete.\n");
-+}
-+
-+
-+static const struct hw_sequencer_funcs dce110_funcs = {
-+	.apply_ctx_to_hw = apply_ctx_to_hw,
-+	.reset_hw_ctx = reset_hw_ctx,
-+	.set_plane_config = set_plane_config,
-+	.update_plane_address = update_plane_address,
-+	.enable_memory_requests = dce110_timing_generator_unblank_crtc,
-+	.disable_memory_requests = dce110_timing_generator_blank_crtc,
-+	.cursor_set_attributes = dce110_ipp_cursor_set_attributes,
-+	.cursor_set_position = dce110_ipp_cursor_set_position,
-+	.set_gamma_ramp = set_gamma_ramp,
-+	.power_down = power_down,
-+	.enable_accelerated_mode = enable_accelerated_mode,
-+	.get_crtc_positions = dce110_timing_generator_get_crtc_positions,
-+	.get_vblank_counter = dce110_timing_generator_get_vblank_counter,
-+	.enable_timing_synchronization = enable_timing_synchronization,
-+	.disable_vga = dce110_timing_generator_disable_vga,
-+	.encoder_create = dce110_link_encoder_create,
-+	.encoder_destroy = dce110_link_encoder_destroy,
-+	.encoder_power_up = dce110_link_encoder_power_up,
-+	.encoder_enable_output = dce110_link_encoder_enable_output,
-+	.encoder_disable_output = dce110_link_encoder_disable_output,
-+	.encoder_set_dp_phy_pattern = dce110_link_encoder_set_dp_phy_pattern,
-+	.encoder_dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-+	.encoder_set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
-+	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
-+	.transform_power_up = dce110_transform_power_up,
-+	.construct_resource_pool = dce110_construct_resource_pool,
-+	.destruct_resource_pool = dce110_destruct_resource_pool,
-+	.validate_with_context = dce110_validate_with_context,
-+	.validate_bandwidth = dce110_validate_bandwidth,
-+	.set_afmt_memory_power_state = dce110_set_afmt_memory_power_state,
-+	.enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating,
-+	.enable_display_power_gating = dce110_enable_display_power_gating,
-+	.program_bw = dce110_program_bw
-+};
-+
-+bool dce110_hw_sequencer_construct(struct dc *dc)
-+{
-+	dc->hwss = dce110_funcs;
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-new file mode 100644
-index 0000000..def54df
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE110_H__
-+#define __DC_HWSS_DCE110_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+bool dce110_hw_sequencer_construct(struct dc *dc);
-+
-+#endif /* __DC_HWSS_DCE110_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-new file mode 100644
-index 0000000..04105ed
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_ipp.h"
-+
-+static const struct dce110_ipp_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+}
-+};
-+
-+bool dce110_ipp_construct(
-+	struct dce110_ipp* ipp,
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+		return false;
-+
-+	ipp->base.ctx = ctx;
-+
-+	ipp->base.inst = inst;
-+
-+	ipp->offsets = reg_offsets[inst-1];
-+
-+	return true;
-+}
-+
-+void dce110_ipp_destroy(struct input_pixel_processor **ipp)
-+{
-+	dc_service_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
-+	*ipp = NULL;
-+}
-+
-+struct input_pixel_processor *dce110_ipp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_ipp *ipp =
-+		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
-+
-+	if (!ipp)
-+		return NULL;
-+
-+	if (dce110_ipp_construct(ipp, ctx, inst))
-+			return &ipp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, ipp);
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-new file mode 100644
-index 0000000..1da42ff
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -0,0 +1,90 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_IPP_DCE110_H__
-+#define __DC_IPP_DCE110_H__
-+
-+#include "inc/ipp.h"
-+
-+#define TO_DCE110_IPP(input_pixel_processor)\
-+	container_of(input_pixel_processor, struct dce110_ipp, base)
-+
-+struct dce110_ipp_reg_offsets {
-+	uint32_t dcp_offset;
-+};
-+
-+struct dce110_ipp {
-+	struct input_pixel_processor base;
-+	struct dce110_ipp_reg_offsets offsets;
-+	struct dev_c_lut saved_palette[RGB_256X3X16];
-+};
-+
-+bool dce110_ipp_construct(
-+	struct dce110_ipp* ipp,
-+	struct dc_context *ctx,
-+	enum controller_id id);
-+
-+void dce110_ipp_destroy(struct input_pixel_processor **ipp);
-+
-+struct input_pixel_processor *dce110_ipp_create(
-+	struct dc_context *ctx,
-+	enum controller_id id);
-+
-+/* CURSOR RELATED */
-+bool dce110_ipp_cursor_set_position(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_cursor_position *position);
-+
-+bool dce110_ipp_cursor_set_attributes(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_cursor_attributes *attributes);
-+
-+/* DEGAMMA RELATED */
-+bool dce110_ipp_set_degamma(
-+	struct input_pixel_processor *ipp,
-+	const struct gamma_parameters *params,
-+	bool force_bypass);
-+
-+void dce110_ipp_program_prescale(
-+	struct input_pixel_processor *ipp,
-+	enum pixel_format pixel_format);
-+
-+void dce110_ipp_set_legacy_input_gamma_mode(
-+		struct input_pixel_processor *ipp,
-+		bool is_legacy);
-+
-+bool dce110_ipp_set_legacy_input_gamma_ramp(
-+	struct input_pixel_processor *ipp,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params);
-+
-+bool dce110_ipp_set_palette(
-+	struct input_pixel_processor *ipp,
-+	const struct dev_c_lut *palette,
-+	uint32_t start,
-+	uint32_t length,
-+	enum pixel_format surface_pixel_format);
-+
-+#endif /*__DC_IPP_DCE110_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-new file mode 100644
-index 0000000..08b7940
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-@@ -0,0 +1,256 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_ipp.h"
-+
-+#define CURSOR_COLOR_BLACK 0x00000000
-+#define CURSOR_COLOR_WHITE 0xFFFFFFFF
-+
-+#define DCP_REG(reg)\
-+	(reg + ipp110->offsets.dcp_offset)
-+
-+static void enable(
-+	struct dce110_ipp *ipp110,
-+	bool enable);
-+
-+static void lock(
-+	struct dce110_ipp *ipp110,
-+	bool enable);
-+
-+static void program_position(
-+	struct dce110_ipp *ipp110,
-+	uint32_t x,
-+	uint32_t y);
-+
-+static bool program_control(
-+	struct dce110_ipp *ipp110,
-+	enum dc_cursor_color_format color_format,
-+	bool enable_magnification,
-+	bool inverse_transparent_clamping);
-+
-+static void program_hotspot(
-+	struct dce110_ipp *ipp110,
-+	uint32_t x,
-+	uint32_t y);
-+
-+static void program_size(
-+	struct dce110_ipp *ipp110,
-+	uint32_t width,
-+	uint32_t height);
-+
-+static void program_address(
-+	struct dce110_ipp *ipp110,
-+	PHYSICAL_ADDRESS_LOC address);
-+
-+
-+bool dce110_ipp_cursor_set_position(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_cursor_position *position)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+
-+	/* lock cursor registers */
-+	lock(ipp110, true);
-+
-+	/* Flag passed in structure differentiates cursor enable/disable. */
-+	/* Update if it differs from cached state. */
-+	enable(ipp110, position->enable);
-+
-+	program_position(ipp110, position->x, position->y);
-+
-+	if (position->hot_spot_enable)
-+		program_hotspot(
-+				ipp110,
-+				position->x_origin,
-+				position->y_origin);
-+
-+	/* unlock cursor registers */
-+	lock(ipp110, false);
-+
-+	return true;
-+}
-+
-+bool dce110_ipp_cursor_set_attributes(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_cursor_attributes *attributes)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+	/* Lock cursor registers */
-+	lock(ipp110, true);
-+
-+	/* Program cursor control */
-+	program_control(
-+		ipp110,
-+		attributes->color_format,
-+		attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
-+		attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
-+
-+	/* Program hot spot coordinates */
-+	program_hotspot(ipp110, attributes->x_hot, attributes->y_hot);
-+
-+	/*
-+	 * Program cursor size -- NOTE: HW spec specifies that HW register
-+	 * stores size as (height - 1, width - 1)
-+	 */
-+	program_size(ipp110, attributes->width, attributes->height);
-+
-+	/* Program cursor surface address */
-+	program_address(ipp110, attributes->address);
-+
-+	/* Unlock Cursor registers. */
-+	lock(ipp110, false);
-+
-+	return true;
-+}
-+
-+static void enable(
-+	struct dce110_ipp *ipp110, bool enable)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmCUR_CONTROL);
-+
-+	value = dal_read_reg(ipp110->base.ctx, addr);
-+	set_reg_field_value(value, enable, CUR_CONTROL, CURSOR_EN);
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static void lock(
-+	struct dce110_ipp *ipp110, bool lock)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmCUR_UPDATE);
-+
-+	value = dal_read_reg(ipp110->base.ctx, addr);
-+	set_reg_field_value(value, lock, CUR_UPDATE, CURSOR_UPDATE_LOCK);
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static void program_position(
-+	struct dce110_ipp *ipp110,
-+	uint32_t x,
-+	uint32_t y)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmCUR_POSITION);
-+
-+	value = dal_read_reg(ipp110->base.ctx, addr);
-+	set_reg_field_value(value, x, CUR_POSITION, CURSOR_X_POSITION);
-+	set_reg_field_value(value, y, CUR_POSITION, CURSOR_Y_POSITION);
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static bool program_control(
-+	struct dce110_ipp *ipp110,
-+	enum dc_cursor_color_format color_format,
-+	bool enable_magnification,
-+	bool inverse_transparent_clamping)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmCUR_CONTROL);
-+	uint32_t mode = 0;
-+
-+	switch (color_format) {
-+	case CURSOR_MODE_MONO:
-+		mode = 0;
-+		break;
-+	case CURSOR_MODE_COLOR_1BIT_AND:
-+		mode = 1;
-+		break;
-+	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
-+		mode = 2;
-+		break;
-+	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
-+		mode = 3;
-+		break;
-+	default:
-+		return false;
-+	}
-+
-+	set_reg_field_value(value, mode, CUR_CONTROL, CURSOR_MODE);
-+	set_reg_field_value(value, enable_magnification,
-+			CUR_CONTROL, CURSOR_2X_MAGNIFY);
-+	set_reg_field_value(value, inverse_transparent_clamping,
-+			CUR_CONTROL, CUR_INV_TRANS_CLAMP);
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+	if (color_format == CURSOR_MODE_MONO) {
-+		addr = DCP_REG(mmCUR_COLOR1);
-+		dal_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_BLACK);
-+		addr = DCP_REG(mmCUR_COLOR2);
-+		dal_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_WHITE);
-+	}
-+	return true;
-+}
-+
-+static void program_hotspot(
-+	struct dce110_ipp *ipp110,
-+	uint32_t x,
-+	uint32_t y)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmCUR_HOT_SPOT);
-+
-+	value = dal_read_reg(ipp110->base.ctx, addr);
-+	set_reg_field_value(value, x, CUR_HOT_SPOT, CURSOR_HOT_SPOT_X);
-+	set_reg_field_value(value, y, CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y);
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static void program_size(
-+	struct dce110_ipp *ipp110,
-+	uint32_t width,
-+	uint32_t height)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmCUR_SIZE);
-+
-+	value = dal_read_reg(ipp110->base.ctx, addr);
-+	set_reg_field_value(value, width, CUR_SIZE, CURSOR_WIDTH);
-+	set_reg_field_value(value, height, CUR_SIZE, CURSOR_HEIGHT);
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static void program_address(
-+	struct dce110_ipp *ipp110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t addr = DCP_REG(mmCUR_SURFACE_ADDRESS_HIGH);
-+	/* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor
-+	 * surface base address in byte. It is 4K byte aligned.
-+	 * The correct way to program cursor surface address is to first write
-+	 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS */
-+
-+	dal_write_reg(ipp110->base.ctx, addr, address.high_part);
-+
-+	addr = DCP_REG(mmCUR_SURFACE_ADDRESS);
-+	dal_write_reg(ipp110->base.ctx, addr, address.low_part);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-new file mode 100644
-index 0000000..f2e8ef4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -0,0 +1,877 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+#include "include/fixed31_32.h"
-+#include "basics/conversion.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_ipp.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + ipp110->offsets.dcp_offset)
-+
-+enum {
-+	MAX_INPUT_LUT_ENTRY = 256
-+};
-+
-+/* CALCULATION OPERATIONS*/
-+static void convert_256_lut_entries_to_gxo_format(
-+	const struct gamma_ramp_rgb256x3x16 *lut,
-+	struct dev_c_lut16 *gamma)
-+{
-+	uint32_t i = 0;
-+
-+	ASSERT(lut);
-+	ASSERT(gamma);
-+
-+	do {
-+		gamma->red = lut->red[i];
-+		gamma->green = lut->green[i];
-+		gamma->blue = lut->blue[i];
-+
-+		++gamma;
-+		++i;
-+	} while (i != MAX_INPUT_LUT_ENTRY);
-+}
-+
-+static void convert_udx_gamma_entries_to_gxo_format(
-+	const struct gamma_ramp_dxgi_1 *lut,
-+	struct dev_c_lut16 *gamma)
-+{
-+	/* TODO here we deal with DXGI gamma table,
-+	 * originally, values was expressed as 'float',
-+	 * now values expressed as 'dal_fixed20_12'. */
-+}
-+
-+/*PROTOTYPE DECLARATIONS*/
-+static void set_lut_inc(
-+	struct dce110_ipp *ipp110,
-+	uint8_t inc,
-+	bool is_float,
-+	bool is_signed);
-+
-+static void select_lut(struct dce110_ipp *ipp110);
-+
-+static void program_black_offsets(
-+	struct dce110_ipp *ipp110,
-+	struct dev_c_lut16 *offset);
-+
-+static void program_white_offsets(
-+	struct dce110_ipp *ipp110,
-+	struct dev_c_lut16 *offset);
-+
-+static void program_black_white_offset(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format surface_pixel_format);
-+
-+static void program_lut_gamma(
-+	struct dce110_ipp *ipp110,
-+	const struct dev_c_lut16 *gamma,
-+	const struct gamma_parameters *params);
-+
-+static void program_prescale(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format pixel_format);
-+
-+static void set_legacy_input_gamma_mode(
-+	struct dce110_ipp *ipp110,
-+	bool is_legacy);
-+
-+static bool set_legacy_input_gamma_ramp_rgb256x3x16(
-+	struct dce110_ipp *ipp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params);
-+
-+static bool set_legacy_input_gamma_ramp_dxgi1(
-+	struct dce110_ipp *ipp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params);
-+
-+static bool set_default_gamma(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format surface_pixel_format);
-+
-+static void set_degamma(
-+	struct dce110_ipp *ipp110,
-+	const struct gamma_parameters *params,
-+	bool force_bypass);
-+
-+bool dce110_ipp_set_legacy_input_gamma_ramp(
-+	struct input_pixel_processor *ipp,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+
-+	switch (gamma_ramp->type) {
-+	case GAMMA_RAMP_RBG256X3X16:
-+		return set_legacy_input_gamma_ramp_rgb256x3x16(
-+				ipp110, gamma_ramp, params);
-+	case GAMMA_RAMP_DXGI_1:
-+		return set_legacy_input_gamma_ramp_dxgi1(
-+				ipp110, gamma_ramp, params);
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+bool dce110_ipp_set_palette(
-+	struct input_pixel_processor *ipp,
-+	const struct dev_c_lut *palette,
-+	uint32_t start,
-+	uint32_t length,
-+	enum pixel_format surface_pixel_format)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+	uint32_t i;
-+
-+	if (((start + length) > MAX_INPUT_LUT_ENTRY) || (NULL == palette)) {
-+		BREAK_TO_DEBUGGER();
-+		/* wrong input */
-+		return false;
-+	}
-+
-+	for (i = start; i < start + length; i++) {
-+		ipp110->saved_palette[i] = palette[i];
-+		ipp110->saved_palette[i] = palette[i];
-+		ipp110->saved_palette[i] = palette[i];
-+	}
-+
-+	return set_default_gamma(ipp110, surface_pixel_format);
-+}
-+
-+bool dce110_ipp_set_degamma(
-+	struct input_pixel_processor *ipp,
-+	const struct gamma_parameters *params,
-+	bool force_bypass)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+
-+	set_degamma(ipp110, params, force_bypass);
-+
-+	return true;
-+}
-+
-+void dce110_ipp_program_prescale(
-+	struct input_pixel_processor *ipp,
-+	enum pixel_format pixel_format)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+
-+	program_prescale(ipp110, pixel_format);
-+}
-+
-+void dce110_ipp_set_legacy_input_gamma_mode(
-+		struct input_pixel_processor *ipp,
-+		bool is_legacy)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+
-+	set_legacy_input_gamma_mode(ipp110, is_legacy);
-+}
-+
-+static void set_lut_inc(
-+	struct dce110_ipp *ipp110,
-+	uint8_t inc,
-+	bool is_float,
-+	bool is_signed)
-+{
-+	const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL);
-+
-+	uint32_t value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		inc,
-+		DC_LUT_CONTROL,
-+		DC_LUT_INC_R);
-+
-+	set_reg_field_value(
-+		value,
-+		inc,
-+		DC_LUT_CONTROL,
-+		DC_LUT_INC_G);
-+
-+	set_reg_field_value(
-+		value,
-+		inc,
-+		DC_LUT_CONTROL,
-+		DC_LUT_INC_B);
-+
-+	set_reg_field_value(
-+		value,
-+		is_float,
-+		DC_LUT_CONTROL,
-+		DC_LUT_DATA_R_FLOAT_POINT_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		is_float,
-+		DC_LUT_CONTROL,
-+		DC_LUT_DATA_G_FLOAT_POINT_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		is_float,
-+		DC_LUT_CONTROL,
-+		DC_LUT_DATA_B_FLOAT_POINT_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		is_signed,
-+		DC_LUT_CONTROL,
-+		DC_LUT_DATA_R_SIGNED_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		is_signed,
-+		DC_LUT_CONTROL,
-+		DC_LUT_DATA_G_SIGNED_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		is_signed,
-+		DC_LUT_CONTROL,
-+		DC_LUT_DATA_B_SIGNED_EN);
-+
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static void select_lut(struct dce110_ipp *ipp110)
-+{
-+	uint32_t value = 0;
-+
-+	set_lut_inc(ipp110, 0, false, false);
-+
-+	{
-+		const uint32_t addr = DCP_REG(mmDC_LUT_WRITE_EN_MASK);
-+
-+		value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+		/* enable all */
-+		set_reg_field_value(
-+			value,
-+			0x7,
-+			DC_LUT_WRITE_EN_MASK,
-+			DC_LUT_WRITE_EN_MASK);
-+
-+		dal_write_reg(ipp110->base.ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = DCP_REG(mmDC_LUT_RW_MODE);
-+
-+		value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_LUT_RW_MODE,
-+			DC_LUT_RW_MODE);
-+
-+		dal_write_reg(ipp110->base.ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL);
-+
-+		value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+		/* 00 - new u0.12 */
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DC_LUT_CONTROL,
-+			DC_LUT_DATA_R_FORMAT);
-+
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DC_LUT_CONTROL,
-+			DC_LUT_DATA_G_FORMAT);
-+
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DC_LUT_CONTROL,
-+			DC_LUT_DATA_B_FORMAT);
-+
-+		dal_write_reg(ipp110->base.ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = DCP_REG(mmDC_LUT_RW_INDEX);
-+
-+		value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_LUT_RW_INDEX,
-+			DC_LUT_RW_INDEX);
-+
-+		dal_write_reg(ipp110->base.ctx, addr, value);
-+	}
-+}
-+
-+static void program_black_offsets(
-+	struct dce110_ipp *ipp110,
-+	struct dev_c_lut16 *offset)
-+{
-+	dal_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmDC_LUT_BLACK_OFFSET_RED),
-+		offset->red);
-+	dal_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmDC_LUT_BLACK_OFFSET_GREEN),
-+		offset->green);
-+	dal_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmDC_LUT_BLACK_OFFSET_BLUE),
-+		offset->blue);
-+}
-+
-+static void program_white_offsets(
-+	struct dce110_ipp *ipp110,
-+	struct dev_c_lut16 *offset)
-+{
-+	dal_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmDC_LUT_WHITE_OFFSET_RED),
-+		offset->red);
-+	dal_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmDC_LUT_WHITE_OFFSET_GREEN),
-+		offset->green);
-+	dal_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmDC_LUT_WHITE_OFFSET_BLUE),
-+		offset->blue);
-+}
-+
-+static void program_black_white_offset(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format surface_pixel_format)
-+{
-+	struct dev_c_lut16 black_offset;
-+	struct dev_c_lut16 white_offset;
-+
-+	/* get black offset */
-+
-+	switch (surface_pixel_format) {
-+	case PIXEL_FORMAT_FP16:
-+		/* sRGB gamut, [0.0...1.0] */
-+		black_offset.red = 0;
-+		black_offset.green = 0;
-+		black_offset.blue = 0;
-+	break;
-+
-+	case PIXEL_FORMAT_ARGB2101010_XRBIAS:
-+		/* [-1.0...3.0] */
-+		black_offset.red = 0x100;
-+		black_offset.green = 0x100;
-+		black_offset.blue = 0x100;
-+	break;
-+
-+	default:
-+		black_offset.red = 0;
-+		black_offset.green = 0;
-+		black_offset.blue = 0;
-+	}
-+
-+	/* get white offset */
-+
-+	switch (surface_pixel_format) {
-+	case PIXEL_FORMAT_FP16:
-+		white_offset.red = 0x3BFF;
-+		white_offset.green = 0x3BFF;
-+		white_offset.blue = 0x3BFF;
-+	break;
-+
-+	case PIXEL_FORMAT_ARGB2101010_XRBIAS:
-+		white_offset.red = 0x37E;
-+		white_offset.green = 0x37E;
-+		white_offset.blue = 0x37E;
-+		break;
-+
-+	case PIXEL_FORMAT_ARGB8888:
-+		white_offset.red = 0xFF;
-+		white_offset.green = 0xFF;
-+		white_offset.blue = 0xFF;
-+		break;
-+
-+	default:
-+		white_offset.red = 0x3FF;
-+		white_offset.green = 0x3FF;
-+		white_offset.blue = 0x3FF;
-+	}
-+
-+	program_black_offsets(ipp110, &black_offset);
-+	program_white_offsets(ipp110, &white_offset);
-+}
-+
-+static void program_lut_gamma(
-+	struct dce110_ipp *ipp110,
-+	const struct dev_c_lut16 *gamma,
-+	const struct gamma_parameters *params)
-+{
-+	uint32_t i = 0;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	{
-+		uint8_t max_tries = 10;
-+		uint8_t counter = 0;
-+
-+		/* Power on LUT memory */
-+		value = dal_read_reg(
-+				ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCFE_MEM_PWR_CTRL,
-+			DCP_REGAMMA_MEM_PWR_DIS);
-+
-+		dal_write_reg(
-+			ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
-+
-+		while (counter < max_tries) {
-+			value =
-+				dal_read_reg(
-+					ipp110->base.ctx,
-+					DCP_REG(mmDCFE_MEM_PWR_STATUS));
-+
-+			if (get_reg_field_value(
-+				value,
-+				DCFE_MEM_PWR_STATUS,
-+				DCP_REGAMMA_MEM_PWR_STATE) == 0)
-+				break;
-+
-+			++counter;
-+		}
-+
-+		if (counter == max_tries) {
-+			dal_logger_write(ipp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: regamma lut was not powered on in a timely manner, programming still proceeds\n",
-+				__func__);
-+		}
-+	}
-+
-+	program_black_white_offset(ipp110, params->surface_pixel_format);
-+
-+	select_lut(ipp110);
-+
-+	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8) {
-+		addr = DCP_REG(mmDC_LUT_SEQ_COLOR);
-+
-+		do {
-+			struct dev_c_lut *index =
-+				ipp110->saved_palette + i;
-+
-+			set_reg_field_value(
-+				value,
-+				gamma[index->red].red,
-+				DC_LUT_SEQ_COLOR,
-+				DC_LUT_SEQ_COLOR);
-+			dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+
-+			set_reg_field_value(
-+				value,
-+				gamma[index->green].green,
-+				DC_LUT_SEQ_COLOR,
-+				DC_LUT_SEQ_COLOR);
-+			dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+
-+			set_reg_field_value(
-+				value,
-+				gamma[index->blue].blue,
-+				DC_LUT_SEQ_COLOR,
-+				DC_LUT_SEQ_COLOR);
-+			dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+			++i;
-+		} while (i != RGB_256X3X16);
-+	} else {
-+		addr = DCP_REG(mmDC_LUT_SEQ_COLOR);
-+
-+		do {
-+			set_reg_field_value(
-+				value,
-+				gamma[i].red,
-+				DC_LUT_SEQ_COLOR,
-+				DC_LUT_SEQ_COLOR);
-+			dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+
-+			set_reg_field_value(
-+				value,
-+				gamma[i].green,
-+				DC_LUT_SEQ_COLOR,
-+				DC_LUT_SEQ_COLOR);
-+			dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+
-+			set_reg_field_value(
-+				value,
-+				gamma[i].blue,
-+				DC_LUT_SEQ_COLOR,
-+				DC_LUT_SEQ_COLOR);
-+			dal_write_reg(ipp110->base.ctx, addr, value);
-+
-+			++i;
-+		} while (i != RGB_256X3X16);
-+	}
-+
-+	/*  we are done with DCP LUT memory; re-enable low power mode */
-+	value = dal_read_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFE_MEM_PWR_CTRL,
-+		DCP_REGAMMA_MEM_PWR_DIS);
-+
-+	dal_write_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
-+}
-+
-+static void program_prescale(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format pixel_format)
-+{
-+	uint32_t prescale_control;
-+	uint32_t prescale_values_grph_r = 0;
-+	uint32_t prescale_values_grph_g = 0;
-+	uint32_t prescale_values_grph_b = 0;
-+
-+	uint32_t prescale_num;
-+	uint32_t prescale_denom = 1;
-+	uint16_t prescale_hw;
-+	uint32_t bias_num = 0;
-+	uint32_t bias_denom = 1;
-+	uint16_t bias_hw;
-+
-+	const uint32_t addr_control = DCP_REG(mmPRESCALE_GRPH_CONTROL);
-+
-+	prescale_control = dal_read_reg(ipp110->base.ctx, addr_control);
-+
-+	set_reg_field_value(
-+		prescale_control,
-+		0,
-+		PRESCALE_GRPH_CONTROL,
-+		GRPH_PRESCALE_BYPASS);
-+
-+	switch (pixel_format) {
-+	case PIXEL_FORMAT_RGB565:
-+		prescale_num = 64;
-+		prescale_denom = 63;
-+	break;
-+
-+	case PIXEL_FORMAT_ARGB8888:
-+		/* This function should only be called when using regamma
-+		 * and bypassing legacy INPUT GAMMA LUT (function name is
-+		 * misleading)
-+		 */
-+		prescale_num = 256;
-+		prescale_denom = 255;
-+	break;
-+
-+	case PIXEL_FORMAT_ARGB2101010:
-+		prescale_num = 1024;
-+		prescale_denom = 1023;
-+	break;
-+
-+	case PIXEL_FORMAT_ARGB2101010_XRBIAS:
-+		prescale_num = 1024;
-+		prescale_denom = 510;
-+		bias_num = 384;
-+		bias_denom = 1024;
-+	break;
-+
-+	case PIXEL_FORMAT_FP16:
-+		prescale_num = 1;
-+	break;
-+
-+	default:
-+		prescale_num = 1;
-+
-+		set_reg_field_value(
-+			prescale_control,
-+			1,
-+			PRESCALE_GRPH_CONTROL,
-+			GRPH_PRESCALE_BYPASS);
-+	}
-+
-+	prescale_hw = fixed_point_to_int_frac(
-+		dal_fixed31_32_from_fraction(prescale_num, prescale_denom),
-+		2, 13);
-+
-+	bias_hw = fixed_point_to_int_frac(
-+		dal_fixed31_32_from_fraction(bias_num, bias_denom),
-+		2, 13);
-+
-+
-+	set_reg_field_value(
-+		prescale_values_grph_r,
-+		prescale_hw,
-+		PRESCALE_VALUES_GRPH_R,
-+		GRPH_PRESCALE_SCALE_R);
-+
-+	set_reg_field_value(
-+		prescale_values_grph_r,
-+		bias_hw,
-+		PRESCALE_VALUES_GRPH_R,
-+		GRPH_PRESCALE_BIAS_R);
-+
-+
-+	set_reg_field_value(
-+		prescale_values_grph_g,
-+		prescale_hw,
-+		PRESCALE_VALUES_GRPH_G,
-+		GRPH_PRESCALE_SCALE_G);
-+
-+	set_reg_field_value(
-+		prescale_values_grph_g,
-+		bias_hw,
-+		PRESCALE_VALUES_GRPH_G,
-+		GRPH_PRESCALE_BIAS_G);
-+
-+
-+	set_reg_field_value(
-+		prescale_values_grph_b,
-+		prescale_hw,
-+		PRESCALE_VALUES_GRPH_B,
-+		GRPH_PRESCALE_SCALE_B);
-+
-+	set_reg_field_value(
-+		prescale_values_grph_b,
-+		bias_hw,
-+		PRESCALE_VALUES_GRPH_B,
-+		GRPH_PRESCALE_BIAS_B);
-+
-+	dal_write_reg(ipp110->base.ctx,
-+		addr_control, prescale_control);
-+
-+	{
-+		dal_write_reg(ipp110->base.ctx,
-+				DCP_REG(mmPRESCALE_VALUES_GRPH_R),
-+				prescale_values_grph_r);
-+	}
-+
-+	{
-+		dal_write_reg(ipp110->base.ctx,
-+				DCP_REG(mmPRESCALE_VALUES_GRPH_G),
-+				prescale_values_grph_g);
-+	}
-+
-+	{
-+		dal_write_reg(ipp110->base.ctx,
-+				DCP_REG(mmPRESCALE_VALUES_GRPH_B),
-+				prescale_values_grph_b);
-+	}
-+}
-+
-+static void set_legacy_input_gamma_mode(
-+	struct dce110_ipp *ipp110,
-+	bool is_legacy)
-+{
-+	const uint32_t addr = DCP_REG(mmINPUT_GAMMA_CONTROL);
-+	uint32_t value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		!is_legacy,
-+		INPUT_GAMMA_CONTROL,
-+		GRPH_INPUT_GAMMA_MODE);
-+
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-+static bool set_legacy_input_gamma_ramp_rgb256x3x16(
-+	struct dce110_ipp *ipp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	struct dev_c_lut16 *gamma16 =
-+		dc_service_alloc(
-+			ipp110->base.ctx,
-+			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
-+
-+	if (!gamma16)
-+		return false;
-+
-+	convert_256_lut_entries_to_gxo_format(
-+		&gamma_ramp->gamma_ramp_rgb256x3x16, gamma16);
-+
-+	if ((params->surface_pixel_format != PIXEL_FORMAT_ARGB2101010) &&
-+		(params->surface_pixel_format !=
-+			PIXEL_FORMAT_ARGB2101010_XRBIAS) &&
-+		(params->surface_pixel_format != PIXEL_FORMAT_FP16)) {
-+		program_lut_gamma(ipp110, gamma16, params);
-+		dc_service_free(ipp110->base.ctx, gamma16);
-+		return true;
-+	}
-+
-+	/* TODO process DirectX-specific formats*/
-+	dc_service_free(ipp110->base.ctx, gamma16);
-+	return false;
-+}
-+
-+static bool set_legacy_input_gamma_ramp_dxgi1(
-+	struct dce110_ipp *ipp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	struct dev_c_lut16 *gamma16 =
-+		dc_service_alloc(
-+			ipp110->base.ctx,
-+			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
-+
-+	if (!gamma16)
-+		return false;
-+
-+	convert_udx_gamma_entries_to_gxo_format(
-+		&gamma_ramp->gamma_ramp_dxgi1, gamma16);
-+
-+	if ((params->surface_pixel_format != PIXEL_FORMAT_ARGB2101010) &&
-+		(params->surface_pixel_format !=
-+			PIXEL_FORMAT_ARGB2101010_XRBIAS) &&
-+		(params->surface_pixel_format != PIXEL_FORMAT_FP16)) {
-+		program_lut_gamma(ipp110, gamma16, params);
-+		dc_service_free(ipp110->base.ctx, gamma16);
-+		return true;
-+	}
-+
-+	/* TODO process DirectX-specific formats*/
-+	dc_service_free(ipp110->base.ctx, gamma16);
-+	return false;
-+}
-+
-+static bool set_default_gamma(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format surface_pixel_format)
-+{
-+	uint32_t i;
-+
-+	struct dev_c_lut16 *gamma16 = NULL;
-+	struct gamma_parameters *params = NULL;
-+
-+	gamma16 = dc_service_alloc(
-+			ipp110->base.ctx,
-+			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
-+
-+	if (!gamma16)
-+		return false;
-+
-+	params = dc_service_alloc(ipp110->base.ctx, sizeof(*params));
-+
-+	if (!params) {
-+		dc_service_free(ipp110->base.ctx, gamma16);
-+		return false;
-+	}
-+
-+	for (i = 0; i < MAX_INPUT_LUT_ENTRY; i++) {
-+		gamma16[i].red = gamma16[i].green =
-+			gamma16[i].blue = (uint16_t) (i << 8);
-+	}
-+
-+	params->surface_pixel_format = surface_pixel_format;
-+	params->regamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_HW;
-+	params->degamma_adjust_type = GRAPHICS_DEGAMMA_ADJUST_HW;
-+	params->selected_gamma_lut = GRAPHICS_GAMMA_LUT_REGAMMA;
-+	params->disable_adjustments = false;
-+
-+	params->regamma.features.value = 0;
-+
-+	params->regamma.features.bits.GAMMA_RAMP_ARRAY = 0;
-+	params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB = 1;
-+	params->regamma.features.bits.OVERLAY_DEGAMMA_SRGB = 1;
-+
-+	for (i = 0; i < 3; i++) {
-+		params->regamma.gamma_coeff.a0[i] = 31308;
-+		params->regamma.gamma_coeff.a1[i] = 12920;
-+		params->regamma.gamma_coeff.a2[i] = 55;
-+		params->regamma.gamma_coeff.a3[i] = 55;
-+		params->regamma.gamma_coeff.gamma[i] = 2400;
-+
-+	}
-+
-+	program_lut_gamma(ipp110, gamma16, params);
-+
-+	dc_service_free(ipp110->base.ctx, gamma16);
-+	dc_service_free(ipp110->base.ctx, params);
-+
-+	return true;
-+}
-+
-+static void set_degamma(
-+	struct dce110_ipp *ipp110,
-+	const struct gamma_parameters *params,
-+	bool force_bypass)
-+{
-+	uint32_t value;
-+	const uint32_t addr = DCP_REG(mmDEGAMMA_CONTROL);
-+	uint32_t degamma_type =
-+		params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB == 1 ?
-+			1 : 2;
-+
-+	value = dal_read_reg(ipp110->base.ctx, addr);
-+
-+	/* if by pass - no degamma
-+	 * when legacy and regamma LUT's we do degamma */
-+	if (params->degamma_adjust_type == GRAPHICS_DEGAMMA_ADJUST_BYPASS ||
-+		(params->surface_pixel_format == PIXEL_FORMAT_FP16 &&
-+			params->selected_gamma_lut ==
-+				GRAPHICS_GAMMA_LUT_REGAMMA))
-+		degamma_type = 0;
-+
-+	if (force_bypass)
-+		degamma_type = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		degamma_type,
-+		DEGAMMA_CONTROL,
-+		GRPH_DEGAMMA_MODE);
-+
-+	set_reg_field_value(
-+		value,
-+		degamma_type,
-+		DEGAMMA_CONTROL,
-+		CURSOR_DEGAMMA_MODE);
-+
-+	set_reg_field_value(
-+		value,
-+		degamma_type,
-+		DEGAMMA_CONTROL,
-+		CURSOR2_DEGAMMA_MODE);
-+
-+	dal_write_reg(ipp110->base.ctx, addr, value);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-new file mode 100644
-index 0000000..0297bd3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -0,0 +1,2049 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "core_types.h"
-+#include "link_encoder_types.h"
-+#include "dce110_link_encoder.h"
-+#include "i2caux_interface.h"
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+#define DELAY_AFTER_PIXEL_FORMAT_CHANGE 0 /* ms */
-+/* For current ASICs pixel clock - 600MHz */
-+#define MAX_ENCODER_CLK 600000
-+
-+#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 600000	
-+
-+#define DEFAULT_AUX_MAX_DATA_SIZE 16
-+#define AUX_MAX_DEFER_WRITE_RETRY 20
-+/*
-+ * @brief
-+ * Trigger Source Select
-+ * ASIC-dependent, actual values for register programming
-+ */
-+#define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
-+
-+/* all values are in milliseconds */
-+/* For eDP, after power-up/power/down,
-+ * 300/500 msec max. delay from LCDVCC to black video generation */
-+#define PANEL_POWER_UP_TIMEOUT 300
-+#define PANEL_POWER_DOWN_TIMEOUT 500
-+#define HPD_CHECK_INTERVAL 10
-+
-+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-+#define TMDS_MIN_PIXEL_CLOCK 25000
-+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-+#define TMDS_MAX_PIXEL_CLOCK 165000
-+/* For current ASICs pixel clock - 600MHz */
-+#define MAX_ENCODER_CLOCK 600000
-+
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
-+
-+static const uint32_t fe_engine_offsets[] = {
-+	mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+};
-+
-+
-+static enum transmitter translate_encoder_to_transmitter(
-+	struct graphics_object_id encoder)
-+{
-+	switch (encoder.id) {
-+	case ENCODER_ID_INTERNAL_UNIPHY:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_A;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_B;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY1:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_C;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_D;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY2:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_E;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_F;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY3:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_G;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_NUTMEG_CRT;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_TRAVIS_CRT;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_TRAVIS_LCD;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	default:
-+		return TRANSMITTER_UNKNOWN;
-+	}
-+}
-+
-+static void enable_phy_bypass_mode(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	bool enable)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	const uint32_t addr = mmDP_DPHY_CNTL + be_addr_offset;
-+
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, enable, DP_DPHY_CNTL, DPHY_BYPASS);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void disable_prbs_symbols(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	bool disable)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	const uint32_t addr = mmDP_DPHY_CNTL + be_addr_offset;
-+
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, disable,
-+			DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0);
-+
-+	set_reg_field_value(value, disable,
-+			DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1);
-+
-+	set_reg_field_value(value, disable,
-+			DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2);
-+
-+	set_reg_field_value(value, disable,
-+			DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void disable_prbs_mode(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	const uint32_t addr = mmDP_DPHY_PRBS_CNTL + be_addr_offset;
-+	uint32_t value;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, 0, DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void program_pattern_symbols(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	uint16_t pattern_symbols[8])
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	addr = mmDP_DPHY_SYM0 + be_addr_offset;
-+
-+	value = 0;
-+	set_reg_field_value(value, pattern_symbols[0],
-+			DP_DPHY_SYM0, DPHY_SYM1);
-+	set_reg_field_value(value, pattern_symbols[1],
-+			DP_DPHY_SYM0, DPHY_SYM2);
-+	set_reg_field_value(value, pattern_symbols[2],
-+			DP_DPHY_SYM0, DPHY_SYM3);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	addr = mmDP_DPHY_SYM1 + be_addr_offset;
-+
-+	value = 0;
-+	set_reg_field_value(value, pattern_symbols[3],
-+			DP_DPHY_SYM1, DPHY_SYM4);
-+	set_reg_field_value(value, pattern_symbols[4],
-+			DP_DPHY_SYM1, DPHY_SYM5);
-+	set_reg_field_value(value, pattern_symbols[5],
-+			DP_DPHY_SYM1, DPHY_SYM6);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+	addr = mmDP_DPHY_SYM2 + be_addr_offset;
-+	value = 0;
-+	set_reg_field_value(value, pattern_symbols[6],
-+			DP_DPHY_SYM2, DPHY_SYM7);
-+	set_reg_field_value(value, pattern_symbols[6],
-+			DP_DPHY_SYM2, DPHY_SYM8);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void set_dp_phy_pattern_d102(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+
-+	/* For 10-bit PRBS or debug symbols
-+	 * please use the following sequence: */
-+
-+	/* Enable debug symbols on the lanes */
-+
-+	disable_prbs_symbols(ctx, be_addr_offset, true);
-+
-+	/* Disable PRBS mode,
-+	 * make sure DPHY_PRBS_CNTL.DPHY_PRBS_EN=0 */
-+
-+	disable_prbs_mode(ctx, be_addr_offset);
-+
-+	/* Program debug symbols to be output */
-+	{
-+		uint16_t pattern_symbols[8] = {
-+			0x2AA, 0x2AA, 0x2AA, 0x2AA,
-+			0x2AA, 0x2AA, 0x2AA, 0x2AA
-+		};
-+
-+		program_pattern_symbols(ctx,
-+			be_addr_offset, pattern_symbols);
-+	}
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, true);
-+}
-+
-+static void set_link_training_complete(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	bool complete)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	const uint32_t addr = mmDP_LINK_CNTL + be_addr_offset;
-+
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, complete,
-+			DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void set_dp_phy_pattern_training_pattern(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	uint32_t index)
-+{
-+	/* Write Training Pattern */
-+
-+	dal_write_reg(ctx,
-+		mmDP_DPHY_TRAINING_PATTERN_SEL + be_addr_offset, index);
-+
-+	/* Set HW Register Training Complete to false */
-+
-+	set_link_training_complete(ctx, be_addr_offset, false);
-+
-+	/* Disable PHY Bypass mode to output Training Pattern */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+
-+	/* Disable PRBS mode,
-+	 * make sure DPHY_PRBS_CNTL.DPHY_PRBS_EN=0 */
-+
-+	disable_prbs_mode(ctx, be_addr_offset);
-+}
-+
-+static void set_dp_phy_pattern_symbol_error(
-+	struct dc_context *ctx,
-+	const int32_t addr_offset)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, addr_offset, false);
-+
-+	/* program correct panel mode*/
-+	{
-+		const uint32_t addr = mmDP_DPHY_INTERNAL_CTRL + addr_offset;
-+		uint32_t value = 0x0;
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* A PRBS23 pattern is used for most DP electrical measurements. */
-+
-+	/* Enable PRBS symbols on the lanes */
-+
-+	disable_prbs_symbols(ctx, addr_offset, false);
-+
-+	/* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
-+	{
-+		const uint32_t addr = mmDP_DPHY_PRBS_CNTL + addr_offset;
-+		uint32_t value = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+				DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL);
-+		set_reg_field_value(value, 1,
-+				DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN);
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, addr_offset, true);
-+}
-+
-+static void set_dp_phy_pattern_prbs7(
-+	struct dc_context *ctx,
-+	const int32_t addr_offset)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, addr_offset, false);
-+
-+	/* A PRBS7 pattern is used for most DP electrical measurements. */
-+
-+	/* Enable PRBS symbols on the lanes */
-+
-+	disable_prbs_symbols(ctx, addr_offset, false);
-+
-+	/* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
-+	{
-+		const uint32_t addr = mmDP_DPHY_PRBS_CNTL + addr_offset;
-+
-+		uint32_t value = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(value, 0,
-+				DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL);
-+
-+		set_reg_field_value(value, 1,
-+				DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, addr_offset, true);
-+}
-+
-+static void set_dp_phy_pattern_80bit_custom(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	const uint8_t *pattern)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+
-+	/* Enable debug symbols on the lanes */
-+
-+	disable_prbs_symbols(ctx, be_addr_offset, true);
-+
-+	/* Enable PHY bypass mode to enable the test pattern */
-+	/* TODO is it really needed ? */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, true);
-+
-+	/* Program 80 bit custom pattern */
-+	{
-+		uint16_t pattern_symbols[8];
-+
-+		pattern_symbols[0] =
-+			((pattern[1] & 0x03) << 8) | pattern[0];
-+		pattern_symbols[1] =
-+			((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
-+		pattern_symbols[2] =
-+			((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
-+		pattern_symbols[3] =
-+			(pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
-+		pattern_symbols[4] =
-+			((pattern[6] & 0x03) << 8) | pattern[5];
-+		pattern_symbols[5] =
-+			((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
-+		pattern_symbols[6] =
-+			((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
-+		pattern_symbols[7] =
-+			(pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
-+
-+		program_pattern_symbols(ctx,
-+			be_addr_offset, pattern_symbols);
-+	}
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, true);
-+}
-+
-+void dce110_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal)
-+{
-+	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		/* DP SST */
-+		set_reg_field_value(value, 0, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		/* LVDS */
-+		set_reg_field_value(value, 1, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		/* TMDS-DVI */
-+		set_reg_field_value(value, 2, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/* TMDS-HDMI */
-+		set_reg_field_value(value, 3, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* DP MST */
-+		set_reg_field_value(value, 5, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		/* invalid mode ! */
-+		break;
-+	}
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
-+static void set_dp_phy_pattern_hbr2_compliance(
-+	struct link_encoder *enc,
-+	const int32_t be_addr_offset)
-+{
-+	/*const int32_t fe_addr_offset = fe_engine_offsets[param->engine];
-+	const int32_t be_addr_offset = enc->be_engine_offset;*/
-+
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* previously there is a register DP_HBR2_EYE_PATTERN
-+	 * that is enabled to get the pattern.
-+	 * But it does not work with the latest spec change,
-+	 * so we are programming the following registers manually.
-+	 *
-+	 * The following settings have been confirmed
-+	 * by Nick Chorney and Sandra Liu */
-+
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(enc->ctx, be_addr_offset, false);
-+
-+	/* Setup DIG encoder in DP SST mode */
-+
-+	dce110_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
-+
-+	/* program correct panel mode*/
-+	{
-+		const uint32_t addr = mmDP_DPHY_INTERNAL_CTRL + be_addr_offset;
-+		uint32_t value = 0x0;
-+		dal_write_reg(enc->ctx, addr, value);
-+	}
-+
-+	/* no vbid after BS (SR)
-+	 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
-+	 * 11000260 / 11000104 / 110000FC */
-+
-+	/* TODO DP_LINK_FRAMING_CNTL should always use hardware default value
-+	 * output  except output hbr2_compliance pattern for physical PHY
-+	 * measurement. This is not normal usage case. SW should reset this
-+	 * register to hardware default value after end use of HBR2 eye
-+	 */
-+	BREAK_TO_DEBUGGER();
-+	/* TODO: do we still need this, find out at compliance test
-+	addr = mmDP_LINK_FRAMING_CNTL + fe_addr_offset;
-+
-+	value = dal_read_reg(enc->ctx, addr);
-+
-+	set_reg_field_value(value, 0xFC,
-+			DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL);
-+	set_reg_field_value(value, 1,
-+			DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE);
-+	set_reg_field_value(value, 1,
-+			DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE);
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+	 */
-+
-+	/*TODO add support for this test pattern
-+	 * support_dp_hbr2_eye_pattern
-+	 */
-+
-+	/* set link training complete */
-+	set_link_training_complete(enc->ctx, be_addr_offset, true);
-+	/* do not enable video stream */
-+	addr = mmDP_VID_STREAM_CNTL + be_addr_offset;
-+
-+	value = dal_read_reg(enc->ctx, addr);
-+
-+	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(enc->ctx, be_addr_offset, false);
-+}
-+
-+static void set_dp_phy_pattern_passthrough_mode(
-+	struct dc_context *ctx,
-+	const int32_t be_addr_offset,
-+	enum dp_panel_mode panel_mode)
-+{
-+
-+	/* program correct panel mode */
-+	{
-+		const uint32_t addr = mmDP_DPHY_INTERNAL_CTRL + be_addr_offset;
-+
-+		uint32_t value;
-+
-+		value = dal_read_reg(ctx, addr);
-+
-+		switch (panel_mode) {
-+		case DP_PANEL_MODE_EDP:
-+			value = 0x1;
-+		break;
-+		case DP_PANEL_MODE_SPECIAL:
-+			value = 0x11;
-+		break;
-+		default:
-+			value = 0x0;
-+			break;
-+		}
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* set link training complete */
-+
-+	set_link_training_complete(ctx, be_addr_offset, true);
-+
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+
-+	/* Disable PRBS mode,
-+	 * make sure DPHY_PRBS_CNTL.DPHY_PRBS_EN=0 */
-+
-+	disable_prbs_mode(ctx, be_addr_offset);
-+}
-+
-+static void construct(
-+	struct link_encoder *enc,
-+	const struct encoder_init_data *init_data)
-+{
-+	struct graphics_object_encoder_cap_info enc_cap_info = {0};
-+
-+	enc->ctx = init_data->ctx;
-+	enc->id = init_data->encoder;
-+
-+	enc->hpd_source = init_data->hpd_source;
-+	enc->connector = init_data->connector;
-+	enc->input_signals = SIGNAL_TYPE_ALL;
-+
-+	enc->adapter_service = init_data->adapter_service;
-+
-+	enc->preferred_engine = ENGINE_ID_UNKNOWN;
-+
-+	enc->features.flags.raw = 0;
-+
-+	enc->transmitter = translate_encoder_to_transmitter(
-+		init_data->encoder);
-+
-+	enc->features.flags.bits.IS_AUDIO_CAPABLE = true;
-+
-+	enc->features.max_pixel_clock = DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+
-+	/* set the flag to indicate whether driver poll the I2C data pin
-+	 * while doing the DP sink detect */
-+
-+	if (dal_adapter_service_is_feature_supported(
-+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
-+		enc->features.flags.bits.DP_SINK_DETECT_POLL_DATA_PIN = true;
-+
-+	enc->output_signals =
-+		SIGNAL_TYPE_DVI_SINGLE_LINK |
-+		SIGNAL_TYPE_DVI_DUAL_LINK |
-+		SIGNAL_TYPE_LVDS |
-+		SIGNAL_TYPE_DISPLAY_PORT |
-+		SIGNAL_TYPE_DISPLAY_PORT_MST |
-+		SIGNAL_TYPE_EDP |
-+		SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
-+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
-+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
-+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
-+	 * Prefer DIG assignment is decided by board design.
-+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
-+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
-+	 * By this, adding DIGG should not hurt DCE 8.0.
-+	 * This will let DCE 8.1 share DCE 8.0 as much as possible */
-+
-+	switch (enc->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+		enc->preferred_engine = ENGINE_ID_DIGA;
-+		enc->transmitter_offset = 0;
-+		enc->be_engine_offset = 0;
-+	break;
-+	case TRANSMITTER_UNIPHY_B:
-+		enc->preferred_engine = ENGINE_ID_DIGB;
-+
-+		enc->transmitter_offset =
-+			mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 -
-+			mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1;
-+		enc->be_engine_offset =
-+			mmDIG1_DIG_BE_CNTL - mmDIG0_DIG_BE_CNTL;
-+	break;
-+	case TRANSMITTER_UNIPHY_C:
-+		enc->preferred_engine = ENGINE_ID_DIGC;
-+		enc->transmitter_offset =
-+			mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 -
-+			mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1;
-+		enc->be_engine_offset =
-+			mmDIG2_DIG_BE_CNTL - mmDIG0_DIG_BE_CNTL;
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		enc->preferred_engine = ENGINE_ID_UNKNOWN;
-+		enc->transmitter_offset = 0;
-+		enc->be_engine_offset = 0;
-+	}
-+
-+	dal_logger_write(init_data->ctx->logger,
-+			LOG_MAJOR_I2C_AUX,
-+			LOG_MINOR_I2C_AUX_CFG,
-+			"Using channel: %s [%d]\n",
-+			DECODE_CHANNEL_ID(init_data->channel),
-+			init_data->channel);
-+
-+	switch (init_data->channel) {
-+	case CHANNEL_ID_DDC1:
-+		enc->aux_channel_offset = 0;
-+		break;
-+	case CHANNEL_ID_DDC2:
-+		enc->aux_channel_offset =
-+			mmDP_AUX1_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
-+		break;
-+	case CHANNEL_ID_DDC3:
-+		enc->aux_channel_offset =
-+			mmDP_AUX2_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
-+		break;
-+	default:
-+		/* check BIOS object table ! */
-+		dal_logger_write(init_data->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_ENCODER,
-+				"%s: Invalid channel ID\n",
-+				__func__);
-+		enc->aux_channel_offset = 0;
-+	}
-+
-+	/* Override features with DCE-specific values */
-+	if (dal_adapter_service_get_encoder_cap_info(enc->adapter_service,
-+			enc->id, &enc_cap_info))
-+		enc->features.flags.bits.IS_HBR2_CAPABLE =
-+				enc_cap_info.dp_hbr2_cap;
-+
-+	/* test pattern 3 support */
-+	enc->features.flags.bits.IS_TPS3_CAPABLE = true;
-+	enc->features.max_deep_color = COLOR_DEPTH_121212;
-+
-+	enc->features.flags.bits.IS_Y_ONLY_CAPABLE =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_SUPPORT_DP_Y_ONLY);
-+
-+	enc->features.flags.bits.IS_YCBCR_CAPABLE =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_SUPPORT_DP_YUV);
-+}
-+
-+struct link_encoder *dce110_link_encoder_create(
-+	const struct encoder_init_data *init)
-+{
-+	struct link_encoder *enc =
-+		dc_service_alloc(init->ctx, sizeof(struct link_encoder));
-+
-+	if (!enc)
-+		goto enc_create_fail;
-+
-+	construct(enc, init);
-+
-+	return enc;
-+
-+enc_create_fail:
-+	return NULL;
-+}
-+
-+void dce110_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	struct link_encoder *encoder = *enc;
-+	dc_service_free(encoder->ctx, encoder);
-+	*enc = NULL;
-+}
-+
-+void dce110_link_encoder_set_dp_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param)
-+{
-+	const int32_t offset = enc->be_engine_offset;
-+
-+
-+	switch (param->dp_phy_pattern) {
-+	case DP_TEST_PATTERN_TRAINING_PATTERN1:
-+		set_dp_phy_pattern_training_pattern(enc->ctx,
-+			offset, 0);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN2:
-+		set_dp_phy_pattern_training_pattern(enc->ctx,
-+			offset, 1);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN3:
-+		set_dp_phy_pattern_training_pattern(enc->ctx,
-+			offset, 2);
-+		break;
-+	case DP_TEST_PATTERN_D102:
-+		set_dp_phy_pattern_d102(enc->ctx, offset);
-+		break;
-+	case DP_TEST_PATTERN_SYMBOL_ERROR:
-+		set_dp_phy_pattern_symbol_error(enc->ctx, offset);
-+		break;
-+	case DP_TEST_PATTERN_PRBS7:
-+		set_dp_phy_pattern_prbs7(enc->ctx, offset);
-+		break;
-+	case DP_TEST_PATTERN_80BIT_CUSTOM:
-+		set_dp_phy_pattern_80bit_custom(
-+				enc->ctx,
-+			offset, param->custom_pattern);
-+		break;
-+	case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
-+		set_dp_phy_pattern_hbr2_compliance(
-+			enc, offset);
-+		break;
-+	case DP_TEST_PATTERN_VIDEO_MODE: {
-+		set_dp_phy_pattern_passthrough_mode(
-+			enc->ctx,
-+			offset,
-+			param->dp_panel_mode);
-+		break;
-+	}
-+
-+
-+	default:
-+		/* invalid phy pattern */
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+}
-+
-+enum encoder_result dce110_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings)
-+{
-+	union dpcd_training_lane_set training_lane_set = { { 0 } };
-+
-+	int32_t lane = 0;
-+
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (!link_settings) {
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_RESULT_ERROR;
-+	}
-+
-+	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.connector_obj_id = enc->connector;
-+	cntl.lanes_number = link_settings->link_settings.lane_count;
-+	cntl.hpd_sel = enc->hpd_source;
-+	cntl.pixel_clock = link_settings->link_settings.link_rate *
-+						LINK_RATE_REF_FREQ_IN_KHZ;
-+
-+	for (lane = 0; lane < link_settings->link_settings.lane_count; ++lane) {
-+		/* translate lane settings */
-+
-+		training_lane_set.bits.VOLTAGE_SWING_SET =
-+			link_settings->lane_settings[lane].VOLTAGE_SWING;
-+		training_lane_set.bits.PRE_EMPHASIS_SET =
-+			link_settings->lane_settings[lane].PRE_EMPHASIS;
-+
-+		/* post cursor 2 setting only applies to HBR2 link rate */
-+		if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
-+			/* this is passed to VBIOS
-+			 * to program post cursor 2 level */
-+
-+			training_lane_set.bits.POST_CURSOR2_SET =
-+				link_settings->lane_settings[lane].POST_CURSOR2;
-+		}
-+
-+		cntl.lane_select = lane;
-+		cntl.lane_settings = training_lane_set.raw;
-+
-+		/* call VBIOS table to set voltage swing and pre-emphasis */
-+
-+		dal_bios_parser_transmitter_control(
-+			dal_adapter_service_get_bios_parser(
-+				enc->adapter_service), &cntl);
-+	}
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+/* return value is bit-vector */
-+static uint8_t get_frontend_source(
-+	enum engine_id engine)
-+{
-+	switch (engine) {
-+	case ENGINE_ID_DIGA:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
-+	case ENGINE_ID_DIGB:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
-+	case ENGINE_ID_DIGC:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
-+	}
-+}
-+
-+static void configure_encoder(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	const struct link_settings *link_settings)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* set number of lanes */
-+	addr = mmDP_CONFIG + enc->be_engine_offset;
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
-+			DP_CONFIG, DP_UDI_LANES);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+}
-+
-+static bool is_panel_powered_on(struct link_encoder *link_enc)
-+{
-+	uint32_t value;
-+	bool ret;
-+
-+	value = dal_read_reg(link_enc->ctx,
-+			mmLVTMA_PWRSEQ_STATE);
-+
-+	ret = get_reg_field_value(value,
-+			LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R);
-+
-+	return ret == 1;
-+}
-+
-+/*
-+ * @brief
-+ * eDP only. Control the power of the eDP panel.
-+ */
-+static enum encoder_result link_encoder_edp_power_control(
-+	struct link_encoder *link_enc,
-+	bool power_up)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result bp_result;
-+
-+	if (dal_graphics_object_id_get_connector_id(link_enc->connector) !=
-+		CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_RESULT_ERROR;
-+	}
-+
-+	if ((power_up && !is_panel_powered_on(link_enc)) ||
-+		(!power_up && is_panel_powered_on(link_enc))) {
-+
-+		/* Send VBIOS command to prompt eDP panel power */
-+
-+		dal_logger_write(link_enc->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: Panel Power action: %s\n",
-+				__func__, (power_up ? "On":"Off"));
-+
-+		cntl.action = power_up ?
-+			TRANSMITTER_CONTROL_POWER_ON :
-+			TRANSMITTER_CONTROL_POWER_OFF;
-+		cntl.transmitter = link_enc->transmitter;
-+		cntl.connector_obj_id = link_enc->connector;
-+		cntl.coherent = false;
-+		cntl.lanes_number = LANE_COUNT_FOUR;
-+		cntl.hpd_sel = link_enc->hpd_source;
-+
-+		bp_result = dal_bios_parser_transmitter_control(
-+				dal_adapter_service_get_bios_parser(
-+					link_enc->adapter_service), &cntl);
-+
-+		if (BP_RESULT_OK != bp_result) {
-+
-+			dal_logger_write(link_enc->ctx->logger,
-+					LOG_MAJOR_ERROR,
-+					LOG_MINOR_HW_TRACE_RESUME_S3,
-+					"%s: Panel Power bp_result: %d\n",
-+					__func__, bp_result);
-+		}
-+	} else {
-+		dal_logger_write(link_enc->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: Skipping Panel Power action: %s\n",
-+				__func__, (power_up ? "On":"Off"));
-+	}
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+/*
-+ * @brief
-+ * eDP only.
-+ */
-+static void link_encoder_edp_wait_for_hpd_ready(
-+	struct link_encoder *link_enc,
-+	struct graphics_object_id connector,
-+	bool power_up)
-+{
-+	struct adapter_service *as = link_enc->adapter_service;
-+	struct irq *hpd;
-+	bool edp_hpd_high = false;
-+	uint32_t time_elapsed = 0;
-+	uint32_t timeout = power_up ?
-+		PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
-+
-+	if (dal_graphics_object_id_get_connector_id(connector) !=
-+		CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (!power_up && dal_adapter_service_is_feature_supported(
-+		FEATURE_NO_HPD_LOW_POLLING_VCC_OFF))
-+		/* from KV, we will not HPD low after turning off VCC -
-+		 * instead, we will check the SW timer in power_up(). */
-+		return;
-+
-+	/* when we power on/off the eDP panel,
-+	 * we need to wait until SENSE bit is high/low */
-+
-+	/* obtain HPD */
-+
-+	hpd = dal_adapter_service_obtain_hpd_irq(as, connector);
-+
-+	if (!hpd) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dal_irq_open(hpd);
-+
-+	/* wait until timeout or panel detected */
-+
-+	do {
-+		uint32_t detected = 0;
-+
-+		dal_irq_get_value(hpd, &detected);
-+
-+		if (!(detected ^ power_up)) {
-+			edp_hpd_high = true;
-+			break;
-+		}
-+
-+		dc_service_sleep_in_milliseconds(link_enc->ctx, HPD_CHECK_INTERVAL);
-+
-+		time_elapsed += HPD_CHECK_INTERVAL;
-+	} while (time_elapsed < timeout);
-+
-+	dal_irq_close(hpd);
-+
-+	dal_adapter_service_release_irq(as, hpd);
-+
-+	if (false == edp_hpd_high) {
-+		dal_logger_write(link_enc->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: wait timed out!\n", __func__);
-+	}
-+}
-+
-+static void aux_initialize(
-+	struct link_encoder *link_enc,
-+	enum hpd_source_id hpd_source)
-+{
-+	uint32_t addr = mmAUX_CONTROL + link_enc->aux_channel_offset;
-+
-+	uint32_t value = dal_read_reg(link_enc->ctx, addr);
-+
-+	set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
-+	set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
-+	dal_write_reg(link_enc->ctx, addr, value);
-+
-+	addr = mmAUX_DPHY_RX_CONTROL0 + link_enc->aux_channel_offset;
-+	value = dal_read_reg(link_enc->ctx, addr);
-+
-+	/* 1/4 window (the maximum allowed) */
-+	set_reg_field_value(value, 1,
-+			AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
-+	dal_write_reg(link_enc->ctx,
-+			mmAUX_DPHY_RX_CONTROL0 + link_enc->aux_channel_offset,
-+			value);
-+
-+}
-+
-+/*todo: cloned in stream enc, fix*/
-+static bool is_panel_backlight_on(struct link_encoder *link_enc)
-+{
-+	uint32_t value;
-+
-+	value = dal_read_reg(link_enc->ctx, mmLVTMA_PWRSEQ_CNTL);
-+
-+	return get_reg_field_value(value, LVTMA_PWRSEQ_CNTL, LVTMA_BLON);
-+}
-+
-+/*todo: cloned in stream enc, fix*/
-+/*
-+ * @brief
-+ * eDP only. Control the backlight of the eDP panel
-+ */
-+static enum encoder_result link_encoder_edp_backlight_control(
-+	struct link_encoder *link_enc,
-+	bool enable)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (dal_graphics_object_id_get_connector_id(link_enc->connector)
-+		!= CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_RESULT_ERROR;
-+	}
-+
-+	if (enable && is_panel_backlight_on(link_enc)) {
-+		dal_logger_write(link_enc->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: panel already powered up. Do nothing.\n",
-+				__func__);
-+		return ENCODER_RESULT_OK;
-+	}
-+
-+	if (!enable && !is_panel_powered_on(link_enc)) {
-+		dal_logger_write(link_enc->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: panel already powered down. Do nothing.\n",
-+				__func__);
-+		return ENCODER_RESULT_OK;
-+	}
-+
-+	/* Send VBIOS command to control eDP panel backlight */
-+
-+	dal_logger_write(link_enc->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_HW_TRACE_RESUME_S3,
-+			"%s: backlight action: %s\n",
-+			__func__, (enable ? "On":"Off"));
-+
-+	cntl.action = enable ?
-+		TRANSMITTER_CONTROL_BACKLIGHT_ON :
-+		TRANSMITTER_CONTROL_BACKLIGHT_OFF;
-+	/*cntl.engine_id = ctx->engine;*/
-+	cntl.transmitter = link_enc->transmitter;
-+	cntl.connector_obj_id = link_enc->connector;
-+	/*todo: unhardcode*/
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.hpd_sel = link_enc->hpd_source;
-+
-+	/* For eDP, the following delays might need to be considered
-+	 * after link training completed:
-+	 * idle period - min. accounts for required BS-Idle pattern,
-+	 * max. allows for source frame synchronization);
-+	 * 50 msec max. delay from valid video data from source
-+	 * to video on dislpay or backlight enable.
-+	 *
-+	 * Disable the delay for now.
-+	 * Enable it in the future if necessary.
-+	 */
-+	/* dc_service_sleep_in_milliseconds(50); */
-+
-+	dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			link_enc->adapter_service), &cntl);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+/*
-+ * @brief
-+ * Configure digital transmitter and enable both encoder and transmitter
-+ * Actual output will be available after calling unblank()
-+ */
-+enum encoder_result dce110_link_encoder_enable_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum engine_id engine,
-+	enum clock_source_id clock_source,
-+	enum signal_type signal,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* power up eDP panel */
-+
-+		link_encoder_edp_power_control(
-+			enc, true);
-+
-+		link_encoder_edp_wait_for_hpd_ready(
-+			enc, enc->connector, true);
-+
-+		/* have to turn off the backlight
-+		 * before power down eDP panel */
-+		link_encoder_edp_backlight_control(
-+				enc, true);
-+	}
-+
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually. */
-+	if (dc_is_dp_signal(signal))
-+		configure_encoder(enc, engine, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = engine;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = signal;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc->hpd_source;
-+	if (dc_is_dp_signal(signal))
-+		cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	else
-+		cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
-+		dc_service_sleep_in_milliseconds(
-+			enc->ctx,
-+			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
-+
-+	dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc->adapter_service),
-+		&cntl);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+static bool is_dig_enabled(const struct link_encoder *link_enc)
-+{
-+	uint32_t value;
-+
-+	value = dal_read_reg(link_enc->ctx,
-+				mmDIG_BE_EN_CNTL + link_enc->be_engine_offset);
-+
-+	return get_reg_field_value(value, DIG_BE_EN_CNTL, DIG_ENABLE);
-+}
-+
-+static void link_encoder_disable(struct link_encoder *link_enc)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* reset training pattern */
-+	addr = mmDP_DPHY_TRAINING_PATTERN_SEL + link_enc->be_engine_offset;
-+	value = dal_read_reg(link_enc->ctx, addr);
-+	set_reg_field_value(value, 0,
-+			DP_DPHY_TRAINING_PATTERN_SEL,
-+			DPHY_TRAINING_PATTERN_SEL);
-+	dal_write_reg(link_enc->ctx, addr, value);
-+
-+	/* reset training complete */
-+	addr = mmDP_LINK_CNTL + link_enc->be_engine_offset;
-+	value = dal_read_reg(link_enc->ctx, addr);
-+	set_reg_field_value(value, 0, DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE);
-+	dal_write_reg(link_enc->ctx, addr, value);
-+
-+	/* reset panel mode */
-+	addr = mmDP_DPHY_INTERNAL_CTRL + link_enc->be_engine_offset;
-+	value = 0;
-+	dal_write_reg(link_enc->ctx, addr, value);
-+}
-+
-+/*
-+ * @brief
-+ * Disable transmitter and its encoder
-+ */
-+enum encoder_result dce110_link_encoder_disable_output(
-+	struct link_encoder *link_enc,
-+	enum signal_type signal)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* have to turn off the backlight
-+		 * before power down eDP panel */
-+		link_encoder_edp_backlight_control(
-+				link_enc, false);
-+	}
-+
-+	if (!is_dig_enabled(link_enc) &&
-+		dal_adapter_service_should_optimize(link_enc->adapter_service,
-+					OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
-+		return ENCODER_RESULT_OK;
-+	}
-+	/* Power-down RX and disable GPU PHY should be paired.
-+	 * Disabling PHY without powering down RX may cause
-+	 * symbol lock loss, on which we will get DP Sink interrupt. */
-+
-+	/* There is a case for the DP active dongles
-+	 * where we want to disable the PHY but keep RX powered,
-+	 * for those we need to ignore DP Sink interrupt
-+	 * by checking lane count that has been set
-+	 * on the last do_enable_output(). */
-+
-+	/* disable transmitter */
-+	cntl.action = TRANSMITTER_CONTROL_DISABLE;
-+	cntl.transmitter = link_enc->transmitter;
-+	cntl.hpd_sel = link_enc->hpd_source;
-+	cntl.signal = signal;
-+	cntl.connector_obj_id = link_enc->connector;
-+
-+	dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			link_enc->adapter_service), &cntl);
-+
-+	/* disable encoder */
-+	if (dc_is_dp_signal(signal))
-+		link_encoder_disable(link_enc);
-+
-+	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* power down eDP panel */
-+		/* TODO: Power control cause regression, we should implement
-+		 * it properly, for now just comment it.
-+		 *
-+		 * link_encoder_edp_wait_for_hpd_ready(
-+			link_enc,
-+			link_enc->connector,
-+			false);
-+
-+		 * link_encoder_edp_power_control(
-+				link_enc, false); */
-+	}
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+static void hpd_initialize(
-+	struct link_encoder *enc,
-+	enum hpd_source_id hpd_source)
-+{
-+	/* Associate HPD with DIG_BE */
-+	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+	set_reg_field_value(value, hpd_source, DIG_BE_CNTL, DIG_HPD_SELECT);
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
-+enum encoder_result dce110_link_encoder_power_up(
-+	struct link_encoder *enc)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	enum bp_result result;
-+
-+	cntl.action = TRANSMITTER_CONTROL_INIT;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.connector_obj_id = enc->connector;
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.coherent = false;
-+	cntl.hpd_sel = enc->hpd_source;
-+
-+	result = dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc->adapter_service),
-+		&cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(enc->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_RESULT_ERROR;
-+	}
-+
-+	if (enc->connector.id == CONNECTOR_ID_LVDS) {
-+		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
-+
-+		result = dal_bios_parser_transmitter_control(
-+			dal_adapter_service_get_bios_parser(
-+				enc->adapter_service),
-+			&cntl);
-+		ASSERT(result == BP_RESULT_OK);
-+
-+	} else if (enc->connector.id == CONNECTOR_ID_EDP) {
-+		link_encoder_edp_power_control(enc, true);
-+
-+		link_encoder_edp_wait_for_hpd_ready(
-+			enc, enc->connector, true);
-+
-+	}
-+	aux_initialize(enc, enc->hpd_source);
-+
-+	/* reinitialize HPD.
-+	 * hpd_initialize() will pass DIG_FE id to HW context.
-+	 * All other routine within HW context will use fe_engine_offset
-+	 * as DIG_FE id even caller pass DIG_FE id.
-+	 * So this routine must be called first. */
-+	hpd_initialize(enc, enc->hpd_source);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+
-+static bool validate_dvi_output(
-+	const struct link_encoder *enc,
-+	enum signal_type connector_signal,
-+	enum signal_type signal,
-+	const struct dc_crtc_timing *crtc_timing)
-+{
-+	uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
-+
-+	if (enc->features.max_pixel_clock < TMDS_MAX_PIXEL_CLOCK)
-+		max_pixel_clock = enc->features.max_pixel_clock;
-+
-+	if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-+		max_pixel_clock <<= 1;
-+
-+	/* This handles the case of HDMI downgrade to DVI we don't want to
-+	 * we don't want to cap the pixel clock if the DDI is not DVI.
-+	 */
-+	if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
-+			connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
-+		max_pixel_clock = enc->features.max_pixel_clock;
-+
-+	/* DVI only support RGB pixel encoding */
-+	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-+		return false;
-+
-+	if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
-+		return false;
-+
-+	if (crtc_timing->pix_clk_khz > max_pixel_clock)
-+		return false;
-+
-+	/* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_666:
-+	case COLOR_DEPTH_888:
-+	break;
-+	case COLOR_DEPTH_101010:
-+	case COLOR_DEPTH_161616:
-+		if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
-+			return false;
-+	break;
-+	default:
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool validate_hdmi_output(
-+	const struct link_encoder *enc,
-+	const struct dc_crtc_timing *crtc_timing,
-+	uint32_t max_tmds_clk_from_edid_in_mhz,
-+	enum dc_color_depth max_hdmi_deep_color,
-+	uint32_t max_hdmi_pixel_clock)
-+{
-+	enum dc_color_depth max_deep_color = max_hdmi_deep_color;
-+
-+	/* expressed in KHz */
-+	uint32_t pixel_clock = 0;
-+
-+	if (max_deep_color > enc->features.max_deep_color)
-+		max_deep_color = enc->features.max_deep_color;
-+
-+	if (max_deep_color < crtc_timing->display_color_depth)
-+		return false;
-+
-+	if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
-+		return false;
-+
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_666:
-+		pixel_clock = (crtc_timing->pix_clk_khz * 3) >> 2;
-+	break;
-+	case COLOR_DEPTH_888:
-+		pixel_clock = crtc_timing->pix_clk_khz;
-+	break;
-+	case COLOR_DEPTH_101010:
-+		pixel_clock = (crtc_timing->pix_clk_khz * 10) >> 3;
-+	break;
-+	case COLOR_DEPTH_121212:
-+		pixel_clock = (crtc_timing->pix_clk_khz * 3) >> 1;
-+	break;
-+	case COLOR_DEPTH_161616:
-+		pixel_clock = crtc_timing->pix_clk_khz << 1;
-+	break;
-+	default:
-+	break;
-+	}
-+
-+	if (max_tmds_clk_from_edid_in_mhz > 0)
-+		if (pixel_clock > max_tmds_clk_from_edid_in_mhz * 1000)
-+			return false;
-+
-+	if ((pixel_clock == 0) ||
-+		(pixel_clock > max_hdmi_pixel_clock) ||
-+		(pixel_clock > enc->features.max_pixel_clock))
-+		return false;
-+
-+	/*
-+	 * Restriction: allow non-CE mode (IT mode) to support RGB only.
-+	 * When it is IT mode, the format mode will be 0,
-+	 * but currently the code is broken,
-+	 * VIDEO FORMAT is always 0 in validatepathMode().
-+	 * Due to overscan change - need fix there and test the impact - to do.
-+	 */
-+	if (crtc_timing->timing_standard != TIMING_STANDARD_CEA861 &&
-+		crtc_timing->timing_standard != TIMING_STANDARD_HDMI)
-+		if (crtc_timing->pixel_encoding !=
-+			PIXEL_ENCODING_RGB)
-+			return false;
-+
-+	return true;
-+}
-+
-+static bool validate_rgb_output(
-+	const struct link_encoder *enc,
-+	const struct dc_crtc_timing *crtc_timing)
-+{
-+	if (crtc_timing->pix_clk_khz > enc->features.max_pixel_clock)
-+		return false;
-+
-+	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-+		return false;
-+
-+	return true;
-+}
-+
-+static bool validate_dp_output(
-+	const struct link_encoder *enc,
-+	const struct dc_crtc_timing *crtc_timing)
-+{
-+	if (crtc_timing->pix_clk_khz > enc->features.max_pixel_clock)
-+		return false;
-+
-+	/* default RGB only */
-+	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
-+		return true;
-+
-+	if (enc->features.flags.bits.IS_YCBCR_CAPABLE)
-+		return true;
-+
-+	/* for DCE 8.x or later DP Y-only feature,
-+	 * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
-+	if (crtc_timing->flags.Y_ONLY &&
-+		enc->features.flags.bits.IS_YCBCR_CAPABLE &&
-+		crtc_timing->display_color_depth != COLOR_DEPTH_666)
-+		return true;
-+
-+	return false;
-+}
-+
-+static bool validate_wireless_output(
-+	const struct link_encoder *enc,
-+	const struct dc_crtc_timing *crtc_timing)
-+{
-+	if (crtc_timing->pix_clk_khz > enc->features.max_pixel_clock)
-+		return false;
-+
-+	/* Wireless only supports YCbCr444 */
-+	if (crtc_timing->pixel_encoding ==
-+			PIXEL_ENCODING_YCBCR444)
-+		return true;
-+
-+	return false;
-+}
-+
-+enum encoder_result dce110_link_encoder_validate_output_with_stream(
-+	struct link_encoder *enc,
-+	const struct core_stream *stream)
-+{
-+	bool is_valid;
-+
-+	switch (stream->signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		is_valid = validate_dvi_output(
-+			enc,
-+			stream->sink->link->public.connector_signal,
-+			stream->signal,
-+			&stream->public.timing);
-+	break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		is_valid = validate_hdmi_output(
-+				enc,
-+				&stream->public.timing,
-+				stream->max_tmds_clk_from_edid_in_mhz,
-+				stream->max_hdmi_deep_color,
-+				stream->max_hdmi_pixel_clock);
-+	break;
-+	case SIGNAL_TYPE_RGB:
-+		is_valid = validate_rgb_output(
-+			enc, &stream->public.timing);
-+	break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		is_valid = validate_dp_output(
-+			enc, &stream->public.timing);
-+	break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		is_valid = validate_wireless_output(
-+			enc, &stream->public.timing);
-+	break;
-+	default:
-+		is_valid = true;
-+	break;
-+	}
-+
-+	return is_valid ? ENCODER_RESULT_OK : ENCODER_RESULT_ERROR;
-+}
-+
-+/*
-+ * get_supported_stream_engines
-+ *
-+ * @brief
-+ * get a list of supported engine
-+ *
-+ * @param
-+ * const struct encoder_impl *enc - not used.
-+ *
-+ * @return
-+ * list of engines with supported ones enabled.
-+ */
-+union supported_stream_engines dce110_get_supported_stream_engines(
-+	const struct link_encoder *enc)
-+{
-+	union supported_stream_engines result = {.u_all = 0};
-+
-+	result.engine.ENGINE_ID_DIGA = 1;
-+	result.engine.ENGINE_ID_DIGB = 1;
-+	result.engine.ENGINE_ID_DIGC = 1;
-+
-+	if (enc->connector.id == CONNECTOR_ID_EDP /*|| wireless*/)
-+		result.u_all = (1 << enc->preferred_engine);
-+
-+	return result;
-+}
-+
-+void dce110_link_encoder_set_lcd_backlight_level(
-+	struct link_encoder *enc,
-+	uint32_t level)
-+{
-+	struct dc_context *ctx = enc->ctx;
-+
-+	const uint32_t backlight_update_pending_max_retry = 1000;
-+
-+	uint32_t backlight;
-+	uint32_t backlight_period;
-+	uint32_t backlight_lock;
-+
-+	uint32_t i;
-+	uint32_t backlight_24bit;
-+	uint32_t backlight_17bit;
-+	uint32_t backlight_16bit;
-+	uint32_t masked_pwm_period;
-+	uint8_t rounding_bit;
-+	uint8_t bit_count;
-+	uint64_t active_duty_cycle;
-+
-+	backlight = dal_read_reg(ctx, mmBL_PWM_CNTL);
-+	backlight_period = dal_read_reg(ctx, mmBL_PWM_PERIOD_CNTL);
-+	backlight_lock = dal_read_reg(ctx, mmBL_PWM_GRP1_REG_LOCK);
-+
-+	/*
-+	 * 1. Convert 8-bit value to 17 bit U1.16 format
-+	 * (1 integer, 16 fractional bits)
-+	 */
-+
-+	/* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
-+	 * effectively multiplying value by 256/255
-+	 * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
-+	 */
-+	backlight_24bit = level * 0x10101;
-+
-+	/* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
-+	 * used for rounding, take most significant bit of fraction for
-+	 * rounding, e.g. for 0xEFEFEF, rounding bit is 1
-+	 */
-+	rounding_bit = (backlight_24bit >> 7) & 1;
-+
-+	/* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
-+	 * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
-+	 */
-+	backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
-+
-+	/*
-+	 * 2. Find  16 bit backlight active duty cycle, where 0 <= backlight
-+	 * active duty cycle <= backlight period
-+	 */
-+
-+	/* 2.1 Apply bitmask for backlight period value based on value of BITCNT
-+	 */
-+	{
-+		uint32_t pwm_period_bitcnt = get_reg_field_value(
-+			backlight_period,
-+			BL_PWM_PERIOD_CNTL,
-+			BL_PWM_PERIOD_BITCNT);
-+		if (pwm_period_bitcnt == 0)
-+			bit_count = 16;
-+		else
-+			bit_count = pwm_period_bitcnt;
-+	}
-+
-+	/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
-+	masked_pwm_period =
-+	get_reg_field_value(
-+		backlight_period,
-+		BL_PWM_PERIOD_CNTL,
-+		BL_PWM_PERIOD) & ((1 << bit_count) - 1);
-+
-+	/* 2.2 Calculate integer active duty cycle required upper 16 bits
-+	 * contain integer component, lower 16 bits contain fractional component
-+	 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
-+	 */
-+	active_duty_cycle = backlight_17bit * masked_pwm_period;
-+
-+	/* 2.3 Calculate 16 bit active duty cycle from integer and fractional
-+	 * components shift by bitCount then mask 16 bits and add rounding bit
-+	 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
-+	 */
-+	backlight_16bit = active_duty_cycle >> bit_count;
-+	backlight_16bit &= 0xFFFF;
-+	backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
-+	set_reg_field_value(
-+		backlight,
-+		backlight_16bit,
-+		BL_PWM_CNTL,
-+		BL_ACTIVE_INT_FRAC_CNT);
-+
-+	/*
-+	 * 3. Program register with updated value
-+	 */
-+
-+	/* 3.1 Lock group 2 backlight registers */
-+	set_reg_field_value(
-+		backlight_lock,
-+		1,
-+		BL_PWM_GRP1_REG_LOCK,
-+		BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN);
-+	set_reg_field_value(
-+		backlight_lock,
-+		1,
-+		BL_PWM_GRP1_REG_LOCK,
-+		BL_PWM_GRP1_REG_LOCK);
-+	dal_write_reg(ctx, mmBL_PWM_GRP1_REG_LOCK, backlight_lock);
-+
-+	/* 3.2 Write new active duty cycle */
-+	dal_write_reg(ctx, mmBL_PWM_CNTL, backlight);
-+
-+	/* 3.3 Unlock group 2 backlight registers */
-+	set_reg_field_value(
-+		backlight_lock,
-+		0,
-+		BL_PWM_GRP1_REG_LOCK,
-+		BL_PWM_GRP1_REG_LOCK);
-+	dal_write_reg(ctx, mmBL_PWM_GRP1_REG_LOCK, backlight_lock);
-+
-+	/* 5.4.4 Wait for pending bit to be cleared */
-+	for (i = 0; i < backlight_update_pending_max_retry; ++i) {
-+		backlight_lock = dal_read_reg(ctx, mmBL_PWM_GRP1_REG_LOCK);
-+		if (!get_reg_field_value(
-+			backlight_lock,
-+			BL_PWM_GRP1_REG_LOCK,
-+			BL_PWM_GRP1_REG_UPDATE_PENDING))
-+			break;
-+
-+		dc_service_delay_in_microseconds(ctx, 10);
-+	}
-+}
-+
-+/*TODO: move to correct dce specific file*/
-+/**
-+* set_afmt_memory_power_state
-+*
-+* @brief
-+*  Power up audio formatter memory that is mapped to specified DIG
-+*/
-+void dce110_set_afmt_memory_power_state(
-+	const struct dc_context *ctx,
-+	enum engine_id id,
-+	bool enable)
-+{
-+	uint32_t value;
-+	uint32_t mem_pwr_force;
-+
-+	value = dal_read_reg(ctx, mmDCO_MEM_PWR_CTRL);
-+
-+	if (enable)
-+		mem_pwr_force = 0;
-+	else
-+		mem_pwr_force = 3;
-+
-+	/* force shutdown mode for appropriate AFMT memory */
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		set_reg_field_value(
-+			value,
-+			mem_pwr_force,
-+			DCO_MEM_PWR_CTRL,
-+			HDMI0_MEM_PWR_FORCE);
-+		break;
-+	case ENGINE_ID_DIGB:
-+		set_reg_field_value(
-+			value,
-+			mem_pwr_force,
-+			DCO_MEM_PWR_CTRL,
-+			HDMI1_MEM_PWR_FORCE);
-+		break;
-+	case ENGINE_ID_DIGC:
-+		set_reg_field_value(
-+			value,
-+			mem_pwr_force,
-+			DCO_MEM_PWR_CTRL,
-+			HDMI2_MEM_PWR_FORCE);
-+		break;
-+	default:
-+		dal_logger_write(
-+			ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Invalid Engine Id\n",
-+			__func__);
-+		break;
-+	}
-+
-+	dal_write_reg(ctx, mmDCO_MEM_PWR_CTRL, value);
-+}
-+
-+void dce110_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct dp_mst_stream_allocation_table *table,
-+	bool is_removal)
-+{
-+	int32_t addr_offset = enc->be_engine_offset;
-+	uint32_t value0;
-+	uint32_t value1;
-+	uint32_t retries = 0;
-+
-+	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
-+
-+	/* --- Set MSE Stream Attribute -
-+	 * Setup VC Payload Table on Tx Side,
-+	 * Issue allocation change trigger
-+	 * to commit payload on both tx and rx side */
-+
-+	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset);
-+	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
-+
-+	if (table->stream_count >= 1) {
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[0].engine,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SRC0);
-+
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[0].slot_count,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SLOT_COUNT0);
-+	}
-+
-+	if (table->stream_count >= 2) {
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[1].engine,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SRC1);
-+
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[1].slot_count,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SLOT_COUNT1);
-+	}
-+
-+	if (table->stream_count >= 3) {
-+		set_reg_field_value(
-+			value1,
-+			table->stream_allocations[2].engine,
-+			DP_MSE_SAT1,
-+			DP_MSE_SAT_SRC2);
-+
-+		set_reg_field_value(
-+			value1,
-+			table->stream_allocations[2].slot_count,
-+			DP_MSE_SAT1,
-+			DP_MSE_SAT_SLOT_COUNT2);
-+	}
-+
-+	/* update ASIC MSE stream allocation table */
-+	dal_write_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset, value0);
-+	dal_write_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset, value1);
-+
-+	/* --- wait for transaction finish */
-+
-+	/* send allocation change trigger (ACT) ?
-+	 * this step first sends the ACT,
-+	 * then double buffers the SAT into the hardware
-+	 * making the new allocation active on the DP MST mode link */
-+
-+	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset);
-+
-+	/* DP_MSE_SAT_UPDATE:
-+	 * 0 - No Action
-+	 * 1 - Update SAT with trigger
-+	 * 2 - Update SAT without trigger */
-+
-+	set_reg_field_value(
-+		value0,
-+		1,
-+		DP_MSE_SAT_UPDATE,
-+		DP_MSE_SAT_UPDATE);
-+
-+	dal_write_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset, value0);
-+
-+	/* wait for update to complete
-+	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
-+	 * then wait for the transmission
-+	 * of at least 16 MTP headers on immediate local link.
-+	 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
-+	 * a value of 1 indicates that DP MST mode
-+	 * is in the 16 MTP keepout region after a VC has been added.
-+	 * MST stream bandwidth (VC rate) can be configured
-+	 * after this bit is cleared */
-+
-+	do {
-+		dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+		value0 = dal_read_reg(enc->ctx,
-+				mmDP_MSE_SAT_UPDATE + addr_offset);
-+
-+		value1 = get_reg_field_value(
-+				value0,
-+				DP_MSE_SAT_UPDATE,
-+				DP_MSE_16_MTP_KEEPOUT);
-+
-+		/* bit field DP_MSE_SAT_UPDATE is set to 1 already */
-+		if (value1)
-+			break;
-+		++retries;
-+	} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+
-+	/* TODO should not need. clean this after light up
-+	 * if (is_removal)
-+	 * dal_write_reg(enc->ctx, addr, value);
-+	 */
-+}
-+
-+void dce110_link_encoder_set_mst_bandwidth(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	struct fixed31_32 avg_time_slots_per_mtp)
-+{
-+	uint32_t x = dal_fixed31_32_floor(
-+		avg_time_slots_per_mtp);
-+
-+	uint32_t y = dal_fixed31_32_ceil(
-+		dal_fixed31_32_shl(
-+			dal_fixed31_32_sub_int(
-+				avg_time_slots_per_mtp,
-+				x),
-+			26));
-+
-+	{
-+		const uint32_t addr = mmDP_MSE_RATE_CNTL +
-+				fe_engine_offsets[engine];
-+		uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			x,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_X);
-+
-+		set_reg_field_value(
-+			value,
-+			y,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_Y);
-+
-+		dal_write_reg(enc->ctx, addr, value);
-+	}
-+
-+	/* wait for update to be completed on the link
-+	 * i.e. DP_MSE_RATE_UPDATE_PENDING field (read only)
-+	 * is reset to 0 (not pending) */
-+	{
-+		const uint32_t addr = mmDP_MSE_RATE_UPDATE +
-+			fe_engine_offsets[engine];
-+		uint32_t value, field;
-+		uint32_t retries = 0;
-+
-+		do {
-+			value = dal_read_reg(enc->ctx, addr);
-+
-+			field = get_reg_field_value(
-+					value,
-+					DP_MSE_RATE_UPDATE,
-+					DP_MSE_RATE_UPDATE_PENDING);
-+
-+			if (!(field &
-+			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
-+				break;
-+
-+			dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+			++retries;
-+		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+	}
-+}
-+
-+void dce110_link_encoder_connect_dig_be_to_fe(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	bool connect)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+	uint32_t field;
-+
-+	if (engine != ENGINE_ID_UNKNOWN) {
-+		addr = mmDIG_BE_CNTL + enc->be_engine_offset;
-+		value = dal_read_reg(enc->ctx, addr);
-+
-+		field = get_reg_field_value(
-+				value,
-+				DIG_BE_CNTL,
-+				DIG_FE_SOURCE_SELECT);
-+
-+		if (connect)
-+			field |= get_frontend_source(engine);
-+		else
-+			field &= ~get_frontend_source(engine);
-+
-+		set_reg_field_value(
-+			value,
-+			field,
-+			DIG_BE_CNTL,
-+			DIG_FE_SOURCE_SELECT);
-+		dal_write_reg(enc->ctx, addr, value);
-+	}
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-new file mode 100644
-index 0000000..4331bf0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -0,0 +1,91 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_ENCODER__DCE110_H__
-+#define __DC_LINK_ENCODER__DCE110_H__
-+
-+struct link_encoder *dce110_link_encoder_create(
-+	const struct encoder_init_data *init);
-+void dce110_link_encoder_destroy(struct link_encoder **enc);
-+
-+void dce110_link_encoder_set_dp_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param);
-+
-+enum encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
-+
-+enum encoder_result dce110_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings);
-+
-+union supported_stream_engines dce110_get_supported_stream_engines(
-+	const struct link_encoder *enc);
-+
-+enum encoder_result dce110_link_encoder_validate_output_with_stream(
-+	struct link_encoder *enc,
-+	const struct core_stream *stream);
-+
-+void dce110_link_encoder_set_lcd_backlight_level(
-+	struct link_encoder *enc,
-+	uint32_t level);
-+
-+void dce110_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal);
-+
-+enum encoder_result dce110_link_encoder_enable_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum engine_id engine,
-+	enum clock_source_id clock_source,
-+	enum signal_type signal,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock);
-+
-+enum encoder_result dce110_link_encoder_disable_output(
-+	struct link_encoder *link_enc,
-+	enum signal_type signal);
-+
-+void dce110_set_afmt_memory_power_state(
-+	const struct dc_context *ctx,
-+	enum engine_id id,
-+	bool enable);
-+
-+void dce110_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct dp_mst_stream_allocation_table *table,
-+	bool is_removal);
-+
-+void dce110_link_encoder_set_mst_bandwidth(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	struct fixed31_32 avg_time_slots_per_mtp);
-+
-+void dce110_link_encoder_connect_dig_be_to_fe(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	bool connect);
-+
-+#endif /* __DC_LINK_ENCODER__DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-new file mode 100644
-index 0000000..7391a0a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -0,0 +1,969 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+/* TODO: this needs to be looked at, used by Stella's workaround*/
-+#include "gmc/gmc_8_2_d.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+
-+#include "include/logger_interface.h"
-+#include "adapter_service_interface.h"
-+#include "inc/bandwidth_calcs.h"
-+
-+#include "dce110_mem_input.h"
-+
-+#define MAX_WATERMARK 0xFFFF
-+#define SAFE_NBP_MARK 0x7FFF
-+
-+#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
-+#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
-+#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
-+
-+static const struct dce110_mem_input_reg_offsets reg_offsets[] =  {
-+{
-+	.dcp = 0,
-+	.dmif = 0,
-+	.pipe = 0,
-+},
-+{
-+	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+				- mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
-+	.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - mmPIPE0_DMIF_BUFFER_CONTROL),
-+},
-+{
-+	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+				- mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
-+	.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - mmPIPE0_DMIF_BUFFER_CONTROL),
-+}
-+};
-+
-+static void set_flip_control(
-+	struct dce110_mem_input *mem_input110,
-+	bool immediate)
-+{
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmGRPH_FLIP_CONTROL));
-+	set_reg_field_value(value, 0,
-+				GRPH_FLIP_CONTROL,
-+				GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
-+	set_reg_field_value(value, 0,
-+				GRPH_FLIP_CONTROL,
-+				GRPH_SURFACE_UPDATE_H_RETRACE_EN);
-+	if (immediate == true)
-+		set_reg_field_value(value, 1,
-+			GRPH_FLIP_CONTROL,
-+			GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
-+
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_FLIP_CONTROL),
-+		value);
-+}
-+
-+static void program_sec_addr(
-+	struct dce110_mem_input *mem_input110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t value = 0;
-+	uint32_t temp = 0;
-+	/*high register MUST be programmed first*/
-+	temp = address.high_part &
-+GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
-+
-+	set_reg_field_value(value, temp,
-+		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
-+		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
-+
-+	dal_write_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH),
-+			value);
-+
-+	temp = 0;
-+	value = 0;
-+	temp = address.low_part >>
-+	GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
-+
-+	set_reg_field_value(value, temp,
-+		GRPH_SECONDARY_SURFACE_ADDRESS,
-+		GRPH_SECONDARY_SURFACE_ADDRESS);
-+
-+	dal_write_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS),
-+			value);
-+}
-+
-+static void program_pri_addr(
-+	struct dce110_mem_input *mem_input110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t value = 0;
-+	uint32_t temp = 0;
-+
-+	/*high register MUST be programmed first*/
-+	temp = address.high_part &
-+GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
-+
-+	set_reg_field_value(value, temp,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH);
-+
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH),
-+		value);
-+
-+	temp = 0;
-+	value = 0;
-+	temp = address.low_part >>
-+	GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT;
-+
-+	set_reg_field_value(value, temp,
-+		GRPH_PRIMARY_SURFACE_ADDRESS,
-+		GRPH_PRIMARY_SURFACE_ADDRESS);
-+
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS),
-+		value);
-+}
-+
-+static void program_addr(
-+	struct dce110_mem_input *mem_input110,
-+	const struct dc_plane_address *addr)
-+{
-+	switch (addr->type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		program_pri_addr(
-+			mem_input110,
-+			addr->grph.addr);
-+		break;
-+	case PLN_ADDR_TYPE_GRPH_STEREO:
-+		program_pri_addr(
-+			mem_input110,
-+			addr->grph_stereo.left_addr);
-+		program_sec_addr(
-+			mem_input110,
-+			addr->grph_stereo.right_addr);
-+		break;
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
-+	case PLN_ADDR_TYPE_VIDEO_INTERLACED:
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO:
-+	case PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO:
-+	default:
-+		/* not supported */
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+static void enable(struct dce110_mem_input *mem_input110)
-+{
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_ENABLE));
-+	set_reg_field_value(value, 1, GRPH_ENABLE, GRPH_ENABLE);
-+	dal_write_reg(mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_ENABLE),
-+		value);
-+}
-+
-+static void program_tiling(
-+	struct dce110_mem_input *mem_input110,
-+	const union plane_tiling_info *info,
-+	const enum surface_pixel_format pixel_format)
-+{
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmGRPH_CONTROL));
-+
-+	set_reg_field_value(value, info->grph.NUM_BANKS,
-+		GRPH_CONTROL, GRPH_NUM_BANKS);
-+
-+	set_reg_field_value(value, info->grph.BANK_WIDTH,
-+		GRPH_CONTROL, GRPH_BANK_WIDTH);
-+
-+	set_reg_field_value(value, info->grph.BANK_HEIGHT,
-+		GRPH_CONTROL, GRPH_BANK_HEIGHT);
-+
-+	set_reg_field_value(value, info->grph.TILE_ASPECT,
-+		GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT);
-+
-+	set_reg_field_value(value, info->grph.TILE_SPLIT,
-+		GRPH_CONTROL, GRPH_TILE_SPLIT);
-+
-+	set_reg_field_value(value, info->grph.TILE_MODE,
-+		GRPH_CONTROL, GRPH_MICRO_TILE_MODE);
-+
-+	set_reg_field_value(value, info->grph.PIPE_CONFIG,
-+		GRPH_CONTROL, GRPH_PIPE_CONFIG);
-+
-+	set_reg_field_value(value, info->grph.ARRAY_MODE,
-+		GRPH_CONTROL, GRPH_ARRAY_MODE);
-+
-+	set_reg_field_value(value, 1,
-+		GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
-+
-+	set_reg_field_value(value, 0,
-+		GRPH_CONTROL, GRPH_Z);
-+
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_CONTROL),
-+		value);
-+}
-+
-+static void program_size_and_rotation(
-+	struct dce110_mem_input *mem_input110,
-+	enum dc_rotation_angle rotation,
-+	const union plane_size *plane_size)
-+{
-+	uint32_t value = 0;
-+	union plane_size local_size = *plane_size;
-+
-+	if (rotation == ROTATION_ANGLE_90 ||
-+		rotation == ROTATION_ANGLE_270) {
-+
-+		uint32_t swap;
-+
-+		swap = local_size.grph.surface_size.x;
-+		local_size.grph.surface_size.x =
-+			local_size.grph.surface_size.y;
-+		local_size.grph.surface_size.y  = swap;
-+
-+		swap = local_size.grph.surface_size.width;
-+		local_size.grph.surface_size.width =
-+			local_size.grph.surface_size.height;
-+		local_size.grph.surface_size.height = swap;
-+	}
-+
-+	set_reg_field_value(value, local_size.grph.surface_size.x,
-+			GRPH_X_START, GRPH_X_START);
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_X_START),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.grph.surface_size.y,
-+			GRPH_Y_START, GRPH_Y_START);
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_Y_START),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.grph.surface_size.width,
-+			GRPH_X_END, GRPH_X_END);
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_X_END),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.grph.surface_size.height,
-+			GRPH_Y_END, GRPH_Y_END);
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_Y_END),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.grph.surface_pitch,
-+			GRPH_PITCH, GRPH_PITCH);
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmGRPH_PITCH),
-+		value);
-+
-+
-+	value = 0;
-+	switch (rotation) {
-+	case ROTATION_ANGLE_90:
-+		set_reg_field_value(value, 3,
-+			HW_ROTATION, GRPH_ROTATION_ANGLE);
-+		break;
-+	case ROTATION_ANGLE_180:
-+		set_reg_field_value(value, 2,
-+			HW_ROTATION, GRPH_ROTATION_ANGLE);
-+		break;
-+	case ROTATION_ANGLE_270:
-+		set_reg_field_value(value, 1,
-+			HW_ROTATION, GRPH_ROTATION_ANGLE);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0,
-+			HW_ROTATION, GRPH_ROTATION_ANGLE);
-+		break;
-+	}
-+	dal_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmHW_ROTATION),
-+		value);
-+}
-+
-+static void program_pixel_format(
-+	struct dce110_mem_input *mem_input110,
-+	enum surface_pixel_format format)
-+{
-+	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-+		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+		uint32_t value = 0;
-+
-+		/* handle colour twizzle formats, swapping R and B */
-+		if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
-+			format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
-+			format ==
-+			SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
-+			format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
-+			set_reg_field_value(
-+				value, 2, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR);
-+			set_reg_field_value(
-+				value, 2, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR);
-+		}
-+
-+		dal_write_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmGRPH_SWAP_CNTL),
-+			value);
-+
-+
-+		value =	dal_read_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmGRPH_CONTROL));
-+
-+		switch (format) {
-+		case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-+			set_reg_field_value(
-+				value, 0, GRPH_CONTROL, GRPH_DEPTH);
-+			set_reg_field_value(
-+				value, 0, GRPH_CONTROL, GRPH_FORMAT);
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+			set_reg_field_value(
-+				value, 1, GRPH_CONTROL, GRPH_DEPTH);
-+			set_reg_field_value(
-+				value, 1, GRPH_CONTROL, GRPH_FORMAT);
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+		case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
-+			set_reg_field_value(
-+				value, 2, GRPH_CONTROL, GRPH_DEPTH);
-+			set_reg_field_value(
-+				value, 0, GRPH_CONTROL, GRPH_FORMAT);
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+			set_reg_field_value(
-+				value, 2, GRPH_CONTROL, GRPH_DEPTH);
-+			set_reg_field_value(
-+				value, 1, GRPH_CONTROL, GRPH_FORMAT);
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+			set_reg_field_value(
-+				value, 3, GRPH_CONTROL, GRPH_DEPTH);
-+			set_reg_field_value(
-+				value, 0, GRPH_CONTROL, GRPH_FORMAT);
-+			break;
-+		default:
-+			break;
-+		}
-+		dal_write_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmGRPH_CONTROL),
-+			value);
-+
-+		/*TODO [hwentlan] MOVE THIS TO CONTROLLER GAMMA!!!!!*/
-+		value = dal_read_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmPRESCALE_GRPH_CONTROL));
-+
-+		if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
-+			set_reg_field_value(
-+				value, 1, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_SELECT);
-+			set_reg_field_value(
-+				value, 1, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_R_SIGN);
-+			set_reg_field_value(
-+				value, 1, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_G_SIGN);
-+			set_reg_field_value(
-+				value, 1, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_B_SIGN);
-+		} else {
-+			set_reg_field_value(
-+				value, 0, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_SELECT);
-+			set_reg_field_value(
-+				value, 0, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_R_SIGN);
-+			set_reg_field_value(
-+				value, 0, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_G_SIGN);
-+			set_reg_field_value(
-+				value, 0, PRESCALE_GRPH_CONTROL,
-+				GRPH_PRESCALE_B_SIGN);
-+		}
-+		dal_write_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmPRESCALE_GRPH_CONTROL),
-+			value);
-+	}
-+}
-+
-+bool dce110_mem_input_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate)
-+{
-+	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-+
-+	set_flip_control(mem_input110, flip_immediate);
-+	program_addr(mem_input110,
-+		address);
-+
-+	return true;
-+}
-+
-+bool dce110_mem_input_program_surface_config(
-+	struct mem_input *mem_input,
-+	const struct dc_surface *surface)
-+{
-+	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-+
-+	enable(mem_input110);
-+	program_tiling(mem_input110, &surface->tiling_info, surface->format);
-+	program_size_and_rotation(mem_input110,
-+		surface->rotation, &surface->plane_size);
-+	program_pixel_format(mem_input110, surface->format);
-+
-+	return true;
-+}
-+
-+static void program_urgency_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t offset,
-+	struct bw_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	/* register value */
-+	uint32_t urgency_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	uint32_t urgency_addr = offset + mmDPG_PIPE_URGENCY_CONTROL;
-+	uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			1,
-+			DPG_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dal_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		marks_low.a_mark,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dal_write_reg(ctx, urgency_addr, urgency_cntl);
-+
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			2,
-+			DPG_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dal_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(urgency_cntl,
-+		marks_low.b_mark,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dal_write_reg(ctx, urgency_addr, urgency_cntl);
-+}
-+
-+void dce110_program_stutter_watermark(
-+	struct mem_input *mi,
-+	struct bw_watermarks marks)
-+{
-+	const struct dc_context *ctx = mi->ctx;
-+	const uint32_t offset = TO_DCE110_MEM_INPUT(mi)->offsets.dmif;
-+	/* register value */
-+	uint32_t stutter_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	uint32_t stutter_addr = offset + mmDPG_PIPE_STUTTER_CONTROL;
-+	uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+
-+	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		1,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dal_read_reg(ctx, stutter_addr);
-+
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set A*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.a_mark,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dal_write_reg(ctx, stutter_addr, stutter_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		2,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dal_read_reg(ctx, stutter_addr);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set B*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.b_mark,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dal_write_reg(ctx, stutter_addr, stutter_cntl);
-+}
-+
-+void dce110_program_nbp_watermark(
-+	struct mem_input *mi,
-+	struct bw_watermarks marks)
-+{
-+	const struct dc_context *ctx = mi->ctx;
-+	const uint32_t offset = TO_DCE110_MEM_INPUT(mi)->offsets.dmif;
-+	uint32_t value;
-+	uint32_t addr;
-+	/* Write mask to enable reading/writing of watermark set A */
-+	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* Write watermark set A */
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		marks.a_mark,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* Write mask to enable reading/writing of watermark set B */
-+	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* Write watermark set B */
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		marks.b_mark,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_program_safe_display_marks(struct mem_input *mi)
-+{
-+	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
-+	struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
-+	struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
-+
-+	program_urgency_watermark(
-+		mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK);
-+	dce110_program_stutter_watermark(mi, max_marks);
-+	dce110_program_nbp_watermark(mi, nbp_marks);
-+
-+}
-+
-+void dce110_program_urgency_watermark(
-+	struct mem_input *mi,
-+	struct bw_watermarks marks,
-+	uint32_t h_total,
-+	uint32_t pixel_clk_in_khz,
-+	uint32_t pstate_blackout_duration_ns)
-+{
-+	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
-+	uint32_t total_dest_line_time_ns = 1000000ULL * h_total
-+		/ pixel_clk_in_khz + pstate_blackout_duration_ns;
-+
-+	program_urgency_watermark(
-+		mi->ctx,
-+		bm_dce110->offsets.dmif,
-+		marks,
-+		total_dest_line_time_ns);
-+}
-+
-+static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
-+{
-+	uint32_t frame_time;
-+	uint32_t pixels_per_second;
-+	uint32_t pixels_per_frame;
-+	uint32_t refresh_rate;
-+	const uint32_t us_in_sec = 1000000;
-+	const uint32_t min_single_frame_time_us = 30000;
-+	/*return double of frame time*/
-+	const uint32_t single_frame_time_multiplier = 2;
-+
-+	if (timing == NULL)
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+
-+	/*TODO: should we use pixel format normalized pixel clock here?*/
-+	pixels_per_second = timing->pix_clk_khz * 1000;
-+	pixels_per_frame = timing->h_total * timing->v_total;
-+
-+	if (!pixels_per_second || !pixels_per_frame) {
-+		/* avoid division by zero */
-+		ASSERT(pixels_per_frame);
-+		ASSERT(pixels_per_second);
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+	}
-+
-+	refresh_rate = pixels_per_second / pixels_per_frame;
-+
-+	if (!refresh_rate) {
-+		/* avoid division by zero*/
-+		ASSERT(refresh_rate);
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+	}
-+
-+	frame_time = us_in_sec / refresh_rate;
-+
-+	if (frame_time < min_single_frame_time_us)
-+		frame_time = min_single_frame_time_us;
-+
-+	frame_time *= single_frame_time_multiplier;
-+
-+	return frame_time;
-+}
-+
-+void dce110_allocate_dmif_buffer(
-+		struct mem_input *mi,
-+		struct dc_crtc_timing *timing,
-+		uint32_t paths_num)
-+{
-+	const uint32_t retry_delay = 10;
-+	uint32_t retry_count = get_dmif_switch_time_us(timing) / retry_delay;
-+
-+	struct dce110_mem_input *bm110 = TO_DCE110_MEM_INPUT(mi);
-+	uint32_t addr = bm110->offsets.pipe + mmPIPE0_DMIF_BUFFER_CONTROL;
-+	uint32_t value;
-+	uint32_t field;
-+
-+	if (bm110->supported_stutter_mode
-+			& STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)
-+		goto register_underflow_int;
-+
-+	/*Allocate DMIF buffer*/
-+	value = dal_read_reg(mi->ctx, addr);
-+	field = get_reg_field_value(
-+		value, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED);
-+	if (field == 2)
-+		goto register_underflow_int;
-+
-+	set_reg_field_value(
-+			value,
-+			2,
-+			PIPE0_DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATED);
-+
-+	dal_write_reg(mi->ctx, addr, value);
-+
-+	do {
-+		value = dal_read_reg(mi->ctx, addr);
-+		field = get_reg_field_value(
-+			value,
-+			PIPE0_DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATION_COMPLETED);
-+
-+		if (field)
-+			break;
-+
-+		dc_service_delay_in_microseconds(mi->ctx, retry_delay);
-+		retry_count--;
-+
-+	} while (retry_count > 0);
-+
-+	if (field == 0)
-+		dal_logger_write(mi->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: DMIF allocation failed",
-+				__func__);
-+
-+	/*
-+	 * Stella Wong proposed the following change
-+	 *
-+	 * Value of mcHubRdReqDmifLimit.ENABLE:
-+	 * 00 - disable DMIF rdreq limit
-+	 * 01 - enable DMIF rdreq limit, disabled by DMIF stall = 1 || urg != 0
-+	 * 02 - enable DMIF rdreq limit, disable by DMIF stall = 1
-+	 * 03 - force enable DMIF rdreq limit, ignore DMIF stall / urgent
-+	 */
-+	addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
-+	value = dal_read_reg(mi->ctx, addr);
-+	if (paths_num > 1)
-+		set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+	else
-+		set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+	dal_write_reg(mi->ctx, addr, value);
-+
-+register_underflow_int:
-+	/*todo*/;
-+	/*register_interrupt(bm110, irq_source, ctrl_id);*/
-+}
-+
-+static void deallocate_dmif_buffer_helper(
-+				struct dc_context *ctx, uint32_t offset)
-+{
-+	uint32_t value;
-+	uint32_t count = 0xBB8; /* max retry count */
-+
-+	value = dal_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
-+
-+	if (!get_reg_field_value(
-+		value, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED))
-+		return;
-+
-+	set_reg_field_value(
-+		value, 0, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED);
-+
-+	dal_write_reg(
-+		ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset, value);
-+
-+	do {
-+		value = dal_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
-+		dc_service_delay_in_microseconds(ctx, 10);
-+		count--;
-+	} while (count > 0 &&
-+		!get_reg_field_value(
-+			value,
-+			PIPE0_DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATION_COMPLETED));
-+}
-+
-+void dce110_deallocate_dmif_buffer(struct mem_input *mi, uint32_t paths_num)
-+{
-+	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
-+	uint32_t value;
-+
-+	if (!(bm_dce110->supported_stutter_mode &
-+		STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)) {
-+
-+		/* De-allocate DMIF buffer first */
-+		if (mmPIPE0_DMIF_BUFFER_CONTROL + bm_dce110->offsets.pipe != 0)
-+			deallocate_dmif_buffer_helper(
-+					mi->ctx, bm_dce110->offsets.pipe);
-+	}
-+
-+	/* TODO: unregister underflow interrupt
-+	unregisterInterrupt();
-+	*/
-+
-+	/* Value of mcHubRdReqDmifLimit.ENABLE.
-+	 * 00 - disable dmif rdreq limit
-+	 * 01 - enable dmif rdreq limit, disable by dmif stall=1||urg!=0
-+	 * 02 - enable dmif rdreq limit, disable by dmif stall=1
-+	 * 03 - force enable dmif rdreq limit, ignore dmif stall/urgent
-+	 * Stella Wong proposed this change. */
-+	value = dal_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
-+	if (paths_num > 1)
-+		set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+	else
-+		set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+
-+	dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
-+}
-+
-+void dce110_program_pix_dur(struct mem_input *mi, uint32_t pix_clk_khz)
-+{
-+	uint64_t pix_dur;
-+	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
-+					+ TO_DCE110_MEM_INPUT(mi)->offsets.dmif;
-+	uint32_t value = dal_read_reg(mi->ctx, addr);
-+
-+	if (pix_clk_khz == 0)
-+		return;
-+
-+	pix_dur = 1000000000 / pix_clk_khz;
-+
-+	set_reg_field_value(
-+		value,
-+		pix_dur,
-+		DPG_PIPE_ARBITRATION_CONTROL1,
-+		PIXEL_DURATION);
-+
-+	dal_write_reg(mi->ctx, addr, value);
-+}
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce110_mem_input_construct(
-+	struct dce110_mem_input *mem_input110,
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+		return false;
-+
-+	mem_input110->base.ctx = ctx;
-+
-+	mem_input110->base.inst = inst;
-+
-+	mem_input110->offsets = reg_offsets[inst - 1];
-+
-+	mem_input110->supported_stutter_mode = 0;
-+	dal_adapter_service_get_feature_value(FEATURE_STUTTER_MODE,
-+			&(mem_input110->supported_stutter_mode),
-+			sizeof(mem_input110->supported_stutter_mode));
-+
-+	return true;
-+}
-+
-+void dce110_mem_input_destroy(struct mem_input **mem_input)
-+{
-+	dc_service_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
-+	*mem_input = NULL;
-+}
-+
-+struct mem_input *dce110_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_mem_input *mem_input110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_mem_input));
-+
-+	if (!mem_input110)
-+		return NULL;
-+
-+	if (dce110_mem_input_construct(mem_input110,
-+			ctx, inst))
-+		return &mem_input110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, mem_input110);
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-new file mode 100644
-index 0000000..9c6d278
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -0,0 +1,88 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MEM_INPUT_DCE110_H__
-+#define __DC_MEM_INPUT_DCE110_H__
-+
-+#include "inc/mem_input.h"
-+
-+#define TO_DCE110_MEM_INPUT(mi)\
-+	container_of(mi, struct dce110_mem_input, base)
-+
-+struct dce110_mem_input_reg_offsets {
-+	uint32_t dcp;
-+	uint32_t dmif;
-+	uint32_t pipe;
-+};
-+
-+struct dce110_mem_input {
-+	struct mem_input base;
-+	struct dce110_mem_input_reg_offsets offsets;
-+	uint32_t supported_stutter_mode;
-+};
-+
-+struct mem_input *dce110_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+void dce110_mem_input_destroy(struct mem_input **mem_input);
-+
-+bool dce110_mem_input_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate);
-+
-+bool  dce110_mem_input_program_surface_config(
-+	struct mem_input *mem_input,
-+	const struct dc_surface *surface);
-+
-+void dce110_program_nbp_watermark(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks marks);
-+
-+void dce110_program_stutter_watermark(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks marks);
-+
-+void dce110_program_urgency_watermark(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks marks,
-+	uint32_t h_total,
-+	uint32_t pixel_clk_in_khz,
-+	uint32_t pstate_blackout_duration_ns);
-+
-+void dce110_program_safe_display_marks(struct mem_input *mi);
-+
-+void dce110_allocate_dmif_buffer(
-+		struct mem_input *mem_input,
-+		struct dc_crtc_timing *timing,
-+		uint32_t paths_num);
-+
-+void dce110_deallocate_dmif_buffer(
-+	struct mem_input *mem_input, uint32_t paths_num);
-+
-+void dce110_program_pix_dur(
-+	struct mem_input *mem_input, uint32_t pix_clk_khz);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-new file mode 100644
-index 0000000..0fdffac
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -0,0 +1,296 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_opp.h"
-+
-+#define FROM_OPP(opp)\
-+	container_of(opp, struct dce110_opp, base)
-+
-+enum {
-+	MAX_LUT_ENTRY = 256,
-+	MAX_NUMBER_OF_ENTRIES = 256
-+};
-+
-+static const struct dce110_opp_reg_offsets reg_offsets[] = {
-+{
-+	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+static void build_evenly_distributed_points(
-+	struct gamma_pixel *points,
-+	uint32_t numberof_points,
-+	struct fixed31_32 max_value,
-+	struct fixed31_32 divider1,
-+	struct fixed31_32 divider2,
-+	struct fixed31_32 divider3)
-+{
-+	struct gamma_pixel *p = points;
-+	struct gamma_pixel *p_last = p + numberof_points - 1;
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		struct fixed31_32 value = dal_fixed31_32_div_int(
-+			dal_fixed31_32_mul_int(max_value, i),
-+			numberof_points - 1);
-+
-+		p->r = value;
-+		p->g = value;
-+		p->b = value;
-+
-+		++p;
-+		++i;
-+	} while (i != numberof_points);
-+
-+	p->r = dal_fixed31_32_div(p_last->r, divider1);
-+	p->g = dal_fixed31_32_div(p_last->g, divider1);
-+	p->b = dal_fixed31_32_div(p_last->b, divider1);
-+
-+	++p;
-+
-+	p->r = dal_fixed31_32_div(p_last->r, divider2);
-+	p->g = dal_fixed31_32_div(p_last->g, divider2);
-+	p->b = dal_fixed31_32_div(p_last->b, divider2);
-+
-+	++p;
-+
-+	p->r = dal_fixed31_32_div(p_last->r, divider3);
-+	p->g = dal_fixed31_32_div(p_last->g, divider3);
-+	p->b = dal_fixed31_32_div(p_last->b, divider3);
-+}
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce110_opp_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+		return false;
-+
-+	opp110->base.ctx = ctx;
-+
-+	opp110->base.inst = inst;
-+
-+	opp110->offsets = reg_offsets[inst - 1];
-+
-+	opp110->regamma.hw_points_num = 128;
-+	opp110->regamma.coordinates_x = NULL;
-+	opp110->regamma.rgb_resulted = NULL;
-+	opp110->regamma.rgb_regamma = NULL;
-+	opp110->regamma.coeff128 = NULL;
-+	opp110->regamma.coeff128_oem = NULL;
-+	opp110->regamma.coeff128_dx = NULL;
-+	opp110->regamma.axis_x_256 = NULL;
-+	opp110->regamma.axis_x_1025 = NULL;
-+	opp110->regamma.rgb_oem = NULL;
-+	opp110->regamma.rgb_user = NULL;
-+	opp110->regamma.extra_points = 3;
-+	opp110->regamma.use_half_points = false;
-+	opp110->regamma.x_max1 = dal_fixed31_32_one;
-+	opp110->regamma.x_max2 = dal_fixed31_32_from_int(2);
-+	opp110->regamma.x_min = dal_fixed31_32_zero;
-+	opp110->regamma.divider1 = dal_fixed31_32_from_fraction(3, 2);
-+	opp110->regamma.divider2 = dal_fixed31_32_from_int(2);
-+	opp110->regamma.divider3 = dal_fixed31_32_from_fraction(5, 2);
-+
-+	opp110->regamma.rgb_user = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pwl_float_data) *
-+		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
-+	if (!opp110->regamma.rgb_user)
-+		goto failure_1;
-+
-+	opp110->regamma.rgb_oem = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pwl_float_data) *
-+		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
-+	if (!opp110->regamma.rgb_oem)
-+		goto failure_2;
-+
-+	opp110->regamma.rgb_resulted = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pwl_result_data) *
-+		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-+	if (!opp110->regamma.rgb_resulted)
-+		goto failure_3;
-+
-+	opp110->regamma.rgb_regamma = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pwl_float_data_ex) *
-+		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-+	if (!opp110->regamma.rgb_regamma)
-+		goto failure_4;
-+
-+	opp110->regamma.coordinates_x = dc_service_alloc(
-+		ctx,
-+		sizeof(struct hw_x_point) *
-+		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-+	if (!opp110->regamma.coordinates_x)
-+		goto failure_5;
-+
-+	opp110->regamma.axis_x_256 = dc_service_alloc(
-+		ctx,
-+		sizeof(struct gamma_pixel) *
-+		(MAX_LUT_ENTRY + opp110->regamma.extra_points));
-+	if (!opp110->regamma.axis_x_256)
-+		goto failure_6;
-+
-+	opp110->regamma.axis_x_1025 = dc_service_alloc(
-+		ctx,
-+		sizeof(struct gamma_pixel) *
-+		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
-+	if (!opp110->regamma.axis_x_1025)
-+		goto failure_7;
-+
-+	opp110->regamma.coeff128 = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pixel_gamma_point) *
-+		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-+	if (!opp110->regamma.coeff128)
-+		goto failure_8;
-+
-+	opp110->regamma.coeff128_oem = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pixel_gamma_point) *
-+		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-+	if (!opp110->regamma.coeff128_oem)
-+		goto failure_9;
-+
-+	opp110->regamma.coeff128_dx = dc_service_alloc(
-+		ctx,
-+		sizeof(struct pixel_gamma_point) *
-+		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-+	if (!opp110->regamma.coeff128_dx)
-+		goto failure_10;
-+
-+	/* init palette */
-+	{
-+		uint32_t i = 0;
-+
-+		do {
-+			opp110->regamma.saved_palette[i].red = (uint8_t)i;
-+			opp110->regamma.saved_palette[i].green = (uint8_t)i;
-+			opp110->regamma.saved_palette[i].blue = (uint8_t)i;
-+
-+			++i;
-+		} while (i != MAX_LUT_ENTRY);
-+	}
-+
-+	build_evenly_distributed_points(
-+		opp110->regamma.axis_x_256,
-+		MAX_LUT_ENTRY,
-+		opp110->regamma.x_max1,
-+		opp110->regamma.divider1,
-+		opp110->regamma.divider2,
-+		opp110->regamma.divider3);
-+
-+	build_evenly_distributed_points(
-+		opp110->regamma.axis_x_1025,
-+		DX_GAMMA_RAMP_MAX,
-+		opp110->regamma.x_max1,
-+		opp110->regamma.divider1,
-+		opp110->regamma.divider2,
-+		opp110->regamma.divider3);
-+
-+	return true;
-+
-+failure_10:
-+	dc_service_free(ctx, opp110->regamma.coeff128_oem);
-+failure_9:
-+	dc_service_free(ctx, opp110->regamma.coeff128);
-+failure_8:
-+	dc_service_free(ctx, opp110->regamma.axis_x_1025);
-+failure_7:
-+	dc_service_free(ctx, opp110->regamma.axis_x_256);
-+failure_6:
-+	dc_service_free(ctx, opp110->regamma.coordinates_x);
-+failure_5:
-+	dc_service_free(ctx, opp110->regamma.rgb_regamma);
-+failure_4:
-+	dc_service_free(ctx, opp110->regamma.rgb_resulted);
-+failure_3:
-+	dc_service_free(ctx, opp110->regamma.rgb_oem);
-+failure_2:
-+	dc_service_free(ctx, opp110->regamma.rgb_user);
-+failure_1:
-+
-+	return true;
-+}
-+
-+void dce110_opp_destroy(struct output_pixel_processor **opp)
-+{
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128_dx);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128_oem);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.axis_x_1025);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.axis_x_256);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coordinates_x);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_regamma);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_resulted);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_oem);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_user);
-+	dc_service_free((*opp)->ctx, FROM_OPP(*opp));
-+	*opp = NULL;
-+}
-+
-+struct output_pixel_processor *dce110_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_opp *opp =
-+		dc_service_alloc(ctx, sizeof(struct dce110_opp));
-+
-+	if (!opp)
-+		return NULL;
-+
-+	if (dce110_opp_construct(opp,
-+			ctx, inst))
-+		return &opp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, opp);
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-new file mode 100644
-index 0000000..71fe624
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -0,0 +1,140 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_OPP_DCE110_H__
-+#define __DC_OPP_DCE110_H__
-+
-+#include "dc_types.h"
-+#include "inc/opp.h"
-+
-+enum dce110_opp_reg_type {
-+	DCE110_OPP_REG_DCP = 0,
-+	DCE110_OPP_REG_DCFE,
-+	DCE110_OPP_REG_FMT,
-+
-+	DCE110_OPP_REG_MAX
-+};
-+
-+struct dce110_regamma {
-+	struct gamma_curve arr_curve_points[16];
-+	struct curve_points arr_points[3];
-+	uint32_t hw_points_num;
-+	struct hw_x_point *coordinates_x;
-+	struct pwl_result_data *rgb_resulted;
-+
-+	/* re-gamma curve */
-+	struct pwl_float_data_ex *rgb_regamma;
-+	/* coeff used to map user evenly distributed points
-+	 * to our hardware points (predefined) for gamma 256 */
-+	struct pixel_gamma_point *coeff128;
-+	struct pixel_gamma_point *coeff128_oem;
-+	/* coeff used to map user evenly distributed points
-+	 * to our hardware points (predefined) for gamma 1025 */
-+	struct pixel_gamma_point *coeff128_dx;
-+	/* evenly distributed points, gamma 256 software points 0-255 */
-+	struct gamma_pixel *axis_x_256;
-+	/* evenly distributed points, gamma 1025 software points 0-1025 */
-+	struct gamma_pixel *axis_x_1025;
-+	/* OEM supplied gamma for regamma LUT */
-+	struct pwl_float_data *rgb_oem;
-+	/* user supplied gamma */
-+	struct pwl_float_data *rgb_user;
-+	struct dev_c_lut saved_palette[RGB_256X3X16];
-+	uint32_t extra_points;
-+	bool use_half_points;
-+	struct fixed31_32 x_max1;
-+	struct fixed31_32 x_max2;
-+	struct fixed31_32 x_min;
-+	struct fixed31_32 divider1;
-+	struct fixed31_32 divider2;
-+	struct fixed31_32 divider3;
-+};
-+
-+/* OPP RELATED */
-+#define TO_DCE110_OPP(opp)\
-+	container_of(opp, struct dce110_opp, base)
-+
-+struct dce110_opp_reg_offsets {
-+	uint32_t fmt_offset;
-+	uint32_t dcp_offset;
-+	uint32_t dcfe_offset;
-+};
-+
-+struct dce110_opp {
-+	struct output_pixel_processor base;
-+	struct dce110_opp_reg_offsets offsets;
-+	struct dce110_regamma regamma;
-+};
-+
-+bool dce110_opp_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+void dce110_opp_destroy(struct output_pixel_processor **opp);
-+
-+struct output_pixel_processor *dce110_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+/* REGAMMA RELATED */
-+void dce110_opp_power_on_regamma_lut(
-+	struct output_pixel_processor *opp,
-+	bool power_on);
-+
-+bool dce110_opp_set_regamma(
-+	struct output_pixel_processor *opp,
-+	const struct gamma_ramp *ramp,
-+	const struct gamma_parameters *params,
-+	bool force_bypass);
-+
-+bool dce110_opp_map_legacy_and_regamma_hw_to_x_user(
-+	struct output_pixel_processor *opp,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params);
-+
-+void dce110_opp_set_csc_adjustment(
-+	struct output_pixel_processor *opp,
-+	const struct grph_csc_adjustment *adjust);
-+
-+void dce110_opp_set_csc_default(
-+	struct output_pixel_processor *opp,
-+	const struct default_adjustment *default_adjust);
-+
-+/* FORMATTER RELATED */
-+void dce110_opp_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params);
-+
-+void dce110_opp_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params);
-+
-+
-+void dce110_opp_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-new file mode 100644
-index 0000000..91430c0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -0,0 +1,904 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "dce110_opp.h"
-+#include "basics/conversion.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + opp110->offsets.dcp_offset)
-+
-+enum {
-+	OUTPUT_CSC_MATRIX_SIZE = 12
-+};
-+
-+struct out_csc_color_matrix {
-+	enum color_space color_space;
-+	uint16_t regval[OUTPUT_CSC_MATRIX_SIZE];
-+};
-+
-+static const struct out_csc_color_matrix global_color_matrix[] = {
-+{ COLOR_SPACE_SRGB_FULL_RANGE,
-+	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+{ COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
-+{ COLOR_SPACE_YCBCR601,
-+	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
-+		0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-+	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-+/*  YOnly same as YCbCr709 but Y in Full range -To do. */
-+{ COLOR_SPACE_YCBCR601_YONLY, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709_YONLY, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
-+};
-+
-+enum csc_color_mode {
-+	/* 00 - BITS2:0 Bypass */
-+	CSC_COLOR_MODE_GRAPHICS_BYPASS,
-+	/* 01 - hard coded coefficient TV RGB */
-+	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
-+	/* 04 - programmable OUTPUT CSC coefficient */
-+	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
-+};
-+
-+static void program_color_matrix(
-+	struct dce110_opp *opp110,
-+	const struct out_csc_color_matrix *tbl_entry,
-+	enum grph_color_adjust_option options)
-+{
-+	struct dc_context *ctx = opp110->base.ctx;
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[0],
-+			OUTPUT_CSC_C11_C12,
-+			OUTPUT_CSC_C11);
-+
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[1],
-+			OUTPUT_CSC_C11_C12,
-+			OUTPUT_CSC_C12);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[2],
-+			OUTPUT_CSC_C13_C14,
-+			OUTPUT_CSC_C13);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[3],
-+			OUTPUT_CSC_C13_C14,
-+			OUTPUT_CSC_C14);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[4],
-+			OUTPUT_CSC_C21_C22,
-+			OUTPUT_CSC_C21);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[5],
-+			OUTPUT_CSC_C21_C22,
-+			OUTPUT_CSC_C22);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[6],
-+			OUTPUT_CSC_C23_C24,
-+			OUTPUT_CSC_C23);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[7],
-+			OUTPUT_CSC_C23_C24,
-+			OUTPUT_CSC_C24);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[8],
-+			OUTPUT_CSC_C31_C32,
-+			OUTPUT_CSC_C31);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[9],
-+			OUTPUT_CSC_C31_C32,
-+			OUTPUT_CSC_C32);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[10],
-+			OUTPUT_CSC_C33_C34,
-+			OUTPUT_CSC_C33);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[11],
-+			OUTPUT_CSC_C33_C34,
-+			OUTPUT_CSC_C34);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+/*
-+ * initialize_color_float_adj_reference_values
-+ * This initialize display color adjust input from API to HW range for later
-+ * calculation use. This is shared by all the display color adjustment.
-+ * @param :
-+ * @return None
-+ */
-+static void initialize_color_float_adj_reference_values(
-+	const struct grph_csc_adjustment *adjust,
-+	struct fixed31_32 *grph_cont,
-+	struct fixed31_32 *grph_sat,
-+	struct fixed31_32 *grph_bright,
-+	struct fixed31_32 *sin_grph_hue,
-+	struct fixed31_32 *cos_grph_hue)
-+{
-+	/* Hue adjustment could be negative. -45 ~ +45 */
-+	struct fixed31_32 hue =
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_from_fraction(adjust->grph_hue, 180),
-+			dal_fixed31_32_pi);
-+
-+	*sin_grph_hue = dal_fixed31_32_sin(hue);
-+	*cos_grph_hue = dal_fixed31_32_cos(hue);
-+
-+	if (adjust->adjust_divider) {
-+		*grph_cont =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_cont,
-+				adjust->adjust_divider);
-+		*grph_sat =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_sat,
-+				adjust->adjust_divider);
-+		*grph_bright =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_bright,
-+				adjust->adjust_divider);
-+	} else {
-+		*grph_cont = dal_fixed31_32_from_int(adjust->grph_cont);
-+		*grph_sat = dal_fixed31_32_from_int(adjust->grph_sat);
-+		*grph_bright = dal_fixed31_32_from_int(adjust->grph_bright);
-+	}
-+}
-+
-+static inline struct fixed31_32 fixed31_32_clamp(
-+	struct fixed31_32 value,
-+	int32_t min_numerator,
-+	int32_t max_numerator,
-+	int32_t denominator)
-+{
-+	return dal_fixed31_32_clamp(
-+		value,
-+		dal_fixed31_32_from_fraction(
-+			min_numerator,
-+			denominator),
-+		dal_fixed31_32_from_fraction(
-+			max_numerator,
-+			denominator));
-+}
-+
-+static void setup_reg_format(
-+	struct fixed31_32 *coefficients,
-+	uint16_t *reg_values)
-+{
-+	enum {
-+		LENGTH = 12,
-+		DENOMINATOR = 10000
-+	};
-+
-+	static const int32_t min_numerator[] = {
-+		-3 * DENOMINATOR,
-+		-DENOMINATOR
-+	};
-+
-+	static const int32_t max_numerator[] = {
-+		DENOMINATOR,
-+		DENOMINATOR
-+	};
-+
-+	static const uint8_t integer_bits[] = { 2, 0 };
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		const uint32_t index = (i % 4) == 3;
-+
-+		reg_values[i] = fixed_point_to_int_frac(
-+			fixed31_32_clamp(coefficients[(i + 8) % LENGTH],
-+				min_numerator[index],
-+				max_numerator[index],
-+				DENOMINATOR),
-+			integer_bits[index], 13);
-+
-+		++i;
-+	} while (i != LENGTH);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: setup_adjustments
-+ *  @note prepare to setup the values
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-+	struct dc_csc_adjustments *adjustments)
-+{
-+	if (adjust->adjust_divider != 0) {
-+		adjustments->brightness =
-+			dal_fixed31_32_from_fraction(adjust->grph_bright,
-+			adjust->adjust_divider);
-+		adjustments->contrast =
-+			dal_fixed31_32_from_fraction(adjust->grph_cont,
-+			adjust->adjust_divider);
-+		adjustments->saturation =
-+			dal_fixed31_32_from_fraction(adjust->grph_sat,
-+			adjust->adjust_divider);
-+	} else {
-+		adjustments->brightness =
-+			dal_fixed31_32_from_fraction(adjust->grph_bright, 1);
-+		adjustments->contrast =
-+			dal_fixed31_32_from_fraction(adjust->grph_cont, 1);
-+		adjustments->saturation =
-+			dal_fixed31_32_from_fraction(adjust->grph_sat, 1);
-+	}
-+
-+	/* convert degrees into radians */
-+	adjustments->hue =
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_from_fraction(adjust->grph_hue, 180),
-+			dal_fixed31_32_pi);
-+}
-+
-+static void prepare_tv_rgb_ideal(
-+	struct fixed31_32 *matrix)
-+{
-+	static const int32_t matrix_[] = {
-+		85546875, 0, 0, 6250000,
-+		0, 85546875, 0, 6250000,
-+		0, 0, 85546875, 6250000
-+	};
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		matrix[i] = dal_fixed31_32_from_fraction(
-+			matrix_[i],
-+			100000000);
-+		++i;
-+	} while (i != ARRAY_SIZE(matrix_));
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_rgb_adjustment_legacy
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for sRGB color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_rgb_adjustment_legacy(
-+	struct dce110_opp *opp110,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	const struct fixed31_32 k1 =
-+		dal_fixed31_32_from_fraction(701000, 1000000);
-+	const struct fixed31_32 k2 =
-+		dal_fixed31_32_from_fraction(236568, 1000000);
-+	const struct fixed31_32 k3 =
-+		dal_fixed31_32_from_fraction(-587000, 1000000);
-+	const struct fixed31_32 k4 =
-+		dal_fixed31_32_from_fraction(464432, 1000000);
-+	const struct fixed31_32 k5 =
-+		dal_fixed31_32_from_fraction(-114000, 1000000);
-+	const struct fixed31_32 k6 =
-+		dal_fixed31_32_from_fraction(-701000, 1000000);
-+	const struct fixed31_32 k7 =
-+		dal_fixed31_32_from_fraction(-299000, 1000000);
-+	const struct fixed31_32 k8 =
-+		dal_fixed31_32_from_fraction(-292569, 1000000);
-+	const struct fixed31_32 k9 =
-+		dal_fixed31_32_from_fraction(413000, 1000000);
-+	const struct fixed31_32 k10 =
-+		dal_fixed31_32_from_fraction(-92482, 1000000);
-+	const struct fixed31_32 k11 =
-+		dal_fixed31_32_from_fraction(-114000, 1000000);
-+	const struct fixed31_32 k12 =
-+		dal_fixed31_32_from_fraction(385051, 1000000);
-+	const struct fixed31_32 k13 =
-+		dal_fixed31_32_from_fraction(-299000, 1000000);
-+	const struct fixed31_32 k14 =
-+		dal_fixed31_32_from_fraction(886000, 1000000);
-+	const struct fixed31_32 k15 =
-+		dal_fixed31_32_from_fraction(-587000, 1000000);
-+	const struct fixed31_32 k16 =
-+		dal_fixed31_32_from_fraction(-741914, 1000000);
-+	const struct fixed31_32 k17 =
-+		dal_fixed31_32_from_fraction(886000, 1000000);
-+	const struct fixed31_32 k18 =
-+		dal_fixed31_32_from_fraction(-144086, 1000000);
-+
-+	const struct fixed31_32 luma_r =
-+		dal_fixed31_32_from_fraction(299, 1000);
-+	const struct fixed31_32 luma_g =
-+		dal_fixed31_32_from_fraction(587, 1000);
-+	const struct fixed31_32 luma_b =
-+		dal_fixed31_32_from_fraction(114, 1000);
-+
-+	struct out_csc_color_matrix tbl_entry;
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	struct fixed31_32 grph_cont;
-+	struct fixed31_32 grph_sat;
-+	struct fixed31_32 grph_bright;
-+	struct fixed31_32 sin_grph_hue;
-+	struct fixed31_32 cos_grph_hue;
-+
-+	initialize_color_float_adj_reference_values(
-+		adjust, &grph_cont, &grph_sat,
-+		&grph_bright, &sin_grph_hue, &cos_grph_hue);
-+
-+	/* COEF_1_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 +
-+	 * Sin(GrphHue) * K2)) */
-+	/* (Cos(GrphHue) * K1 + Sin(GrphHue) * K2) */
-+	matrix[0] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k1),
-+			dal_fixed31_32_mul(sin_grph_hue, k2));
-+	/* GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2 */
-+	matrix[0] = dal_fixed31_32_mul(grph_sat, matrix[0]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)) */
-+	matrix[0] = dal_fixed31_32_add(luma_r, matrix[0]);
-+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) *
-+	 * K2)) */
-+	matrix[0] = dal_fixed31_32_mul(grph_cont, matrix[0]);
-+
-+	/* COEF_1_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 +
-+	 * Sin(GrphHue) * K4)) */
-+	/* (Cos(GrphHue) * K3 + Sin(GrphHue) * K4) */
-+	matrix[1] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k3),
-+			dal_fixed31_32_mul(sin_grph_hue, k4));
-+	/* GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4) */
-+	matrix[1] = dal_fixed31_32_mul(grph_sat, matrix[1]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)) */
-+	matrix[1] = dal_fixed31_32_add(luma_g, matrix[1]);
-+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) *
-+	 * K4)) */
-+	matrix[1] = dal_fixed31_32_mul(grph_cont, matrix[1]);
-+
-+	/* COEF_1_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 +
-+	 * Sin(GrphHue) * K6)) */
-+	/* (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k5),
-+			dal_fixed31_32_mul(sin_grph_hue, k6));
-+	/* GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] = dal_fixed31_32_mul(grph_sat, matrix[2]);
-+	/* LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] = dal_fixed31_32_add(luma_b, matrix[2]);
-+	/* GrphCont  * (LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) *
-+	 * K6)) */
-+	matrix[2] = dal_fixed31_32_mul(grph_cont, matrix[2]);
-+
-+	/* COEF_1_4 = GrphBright */
-+	matrix[3] = grph_bright;
-+
-+	/* COEF_2_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 +
-+	 * Sin(GrphHue) * K8)) */
-+	/* (Cos(GrphHue) * K7 + Sin(GrphHue) * K8) */
-+	matrix[4] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k7),
-+			dal_fixed31_32_mul(sin_grph_hue, k8));
-+	/* GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8) */
-+	matrix[4] = dal_fixed31_32_mul(grph_sat, matrix[4]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)) */
-+	matrix[4] = dal_fixed31_32_add(luma_r, matrix[4]);
-+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) *
-+	 * K8)) */
-+	matrix[4] = dal_fixed31_32_mul(grph_cont, matrix[4]);
-+
-+	/* COEF_2_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 +
-+	 * Sin(GrphHue) * K10)) */
-+	/* (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k9),
-+			dal_fixed31_32_mul(sin_grph_hue, k10));
-+	/* GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] = dal_fixed31_32_mul(grph_sat, matrix[5]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] = dal_fixed31_32_add(luma_g, matrix[5]);
-+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) *
-+	 * K10)) */
-+	matrix[5] = dal_fixed31_32_mul(grph_cont, matrix[5]);
-+
-+	/*  COEF_2_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 +
-+	 * Sin(GrphHue) * K12)) */
-+	/* (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k11),
-+			dal_fixed31_32_mul(sin_grph_hue, k12));
-+	/* GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] = dal_fixed31_32_mul(grph_sat, matrix[6]);
-+	/*  (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] = dal_fixed31_32_add(luma_b, matrix[6]);
-+	/* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) *
-+	 * K12)) */
-+	matrix[6] = dal_fixed31_32_mul(grph_cont, matrix[6]);
-+
-+	/* COEF_2_4 = GrphBright */
-+	matrix[7] = grph_bright;
-+
-+	/* COEF_3_1 = GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 +
-+	 * Sin(GrphHue) * K14)) */
-+	/* (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k13),
-+			dal_fixed31_32_mul(sin_grph_hue, k14));
-+	/* GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] = dal_fixed31_32_mul(grph_sat, matrix[8]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] = dal_fixed31_32_add(luma_r, matrix[8]);
-+	/* GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) *
-+	 * K14)) */
-+	matrix[8] = dal_fixed31_32_mul(grph_cont, matrix[8]);
-+
-+	/* COEF_3_2    = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 +
-+	 * Sin(GrphHue) * K16)) */
-+	/* GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16) */
-+	matrix[9] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k15),
-+			dal_fixed31_32_mul(sin_grph_hue, k16));
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
-+	matrix[9] = dal_fixed31_32_mul(grph_sat, matrix[9]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
-+	matrix[9] = dal_fixed31_32_add(luma_g, matrix[9]);
-+	 /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) *
-+	  * K16)) */
-+	matrix[9] = dal_fixed31_32_mul(grph_cont, matrix[9]);
-+
-+	/*  COEF_3_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 +
-+	 * Sin(GrphHue) * K18)) */
-+	/* (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k17),
-+			dal_fixed31_32_mul(sin_grph_hue, k18));
-+	/*  GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] = dal_fixed31_32_mul(grph_sat, matrix[10]);
-+	/* (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] = dal_fixed31_32_add(luma_b, matrix[10]);
-+	 /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) *
-+	  * K18)) */
-+	matrix[10] = dal_fixed31_32_mul(grph_cont, matrix[10]);
-+
-+	/*  COEF_3_4    = GrphBright */
-+	matrix[11] = grph_bright;
-+
-+	tbl_entry.color_space = adjust->c_space;
-+
-+	convert_float_matrix(tbl_entry.regval, matrix, OUTPUT_CSC_MATRIX_SIZE);
-+
-+	program_color_matrix(
-+		opp110, &tbl_entry, adjust->color_adjust_option);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_rgb_limited_range_adjustment
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for sRGB limited color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_rgb_limited_range_adjustment(
-+	struct dce110_opp *opp110,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct out_csc_color_matrix reg_matrix;
-+	struct fixed31_32 change_matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct dc_csc_adjustments adjustments;
-+	struct fixed31_32 ideals[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	prepare_tv_rgb_ideal(ideals);
-+
-+	setup_adjustments(adjust, &adjustments);
-+
-+	calculate_adjustments(ideals, &adjustments, matrix);
-+
-+	dc_service_memmove(change_matrix, matrix, sizeof(matrix));
-+
-+	/* from 1 -> 3 */
-+	matrix[8] = change_matrix[0];
-+	matrix[9] = change_matrix[1];
-+	matrix[10] = change_matrix[2];
-+	matrix[11] = change_matrix[3];
-+
-+	/* from 2 -> 1 */
-+	matrix[0] = change_matrix[4];
-+	matrix[1] = change_matrix[5];
-+	matrix[2] = change_matrix[6];
-+	matrix[3] = change_matrix[7];
-+
-+	/* from 3 -> 2 */
-+	matrix[4] = change_matrix[8];
-+	matrix[5] = change_matrix[9];
-+	matrix[6] = change_matrix[10];
-+	matrix[7] = change_matrix[11];
-+
-+	dc_service_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+
-+	setup_reg_format(matrix, reg_matrix.regval);
-+
-+	program_color_matrix(opp110, &reg_matrix, GRPH_COLOR_MATRIX_SW);
-+}
-+
-+static void prepare_yuv_ideal(
-+	bool b601,
-+	struct fixed31_32 *matrix)
-+{
-+	static const int32_t matrix_1[] = {
-+		25578516, 50216016, 9752344, 6250000,
-+		-14764391, -28985609, 43750000, 50000000,
-+		43750000, -36635164, -7114836, 50000000
-+	};
-+
-+	static const int32_t matrix_2[] = {
-+		18187266, 61183125, 6176484, 6250000,
-+		-10025059, -33724941, 43750000, 50000000,
-+		43750000, -39738379, -4011621, 50000000
-+	};
-+
-+	const int32_t *matrix_x = b601 ? matrix_1 : matrix_2;
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		matrix[i] = dal_fixed31_32_from_fraction(
-+			matrix_x[i],
-+			100000000);
-+		++i;
-+	} while (i != ARRAY_SIZE(matrix_1));
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_yuv_adjustment
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for YUV  color spaces
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_yuv_adjustment(
-+	struct dce110_opp *opp110,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR601_YONLY);
-+	struct out_csc_color_matrix reg_matrix;
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct dc_csc_adjustments adjustments;
-+	struct fixed31_32 ideals[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	prepare_yuv_ideal(b601, ideals);
-+
-+	setup_adjustments(adjust, &adjustments);
-+
-+	if ((adjust->c_space == COLOR_SPACE_YCBCR601_YONLY) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR709_YONLY))
-+		calculate_adjustments_y_only(
-+			ideals, &adjustments, matrix);
-+	else
-+		calculate_adjustments(
-+			ideals, &adjustments, matrix);
-+
-+	dc_service_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+
-+	setup_reg_format(matrix, reg_matrix.regval);
-+
-+	program_color_matrix(opp110, &reg_matrix, GRPH_COLOR_MATRIX_SW);
-+}
-+
-+static bool configure_graphics_mode(
-+	struct dce110_opp *opp110,
-+	enum csc_color_mode config,
-+	enum graphics_csc_adjust_type csc_adjust_type,
-+	enum color_space color_space)
-+{
-+	struct dc_context *ctx = opp110->base.ctx;
-+	uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		OUTPUT_CSC_CONTROL,
-+		OUTPUT_CSC_GRPH_MODE);
-+
-+	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
-+		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
-+			set_reg_field_value(
-+				value,
-+				4,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+		} else {
-+
-+			switch (color_space) {
-+			case COLOR_SPACE_SRGB_FULL_RANGE:
-+				/* by pass */
-+				set_reg_field_value(
-+					value,
-+					0,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+				/* TV RGB */
-+				set_reg_field_value(
-+					value,
-+					1,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			case COLOR_SPACE_YCBCR601:
-+			case COLOR_SPACE_YPBPR601:
-+			case COLOR_SPACE_YCBCR601_YONLY:
-+				/* YCbCr601 */
-+				set_reg_field_value(
-+					value,
-+					2,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			case COLOR_SPACE_YCBCR709:
-+			case COLOR_SPACE_YPBPR709:
-+			case COLOR_SPACE_YCBCR709_YONLY:
-+				/* YCbCr709 */
-+				set_reg_field_value(
-+					value,
-+					3,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			default:
-+				return false;
-+			}
-+		}
-+	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB_FULL_RANGE:
-+			/* by pass */
-+			set_reg_field_value(
-+				value,
-+				0,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+			/* TV RGB */
-+			set_reg_field_value(
-+				value,
-+				1,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YPBPR601:
-+		case COLOR_SPACE_YCBCR601_YONLY:
-+			/* YCbCr601 */
-+			set_reg_field_value(
-+				value,
-+				2,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YPBPR709:
-+		case COLOR_SPACE_YCBCR709_YONLY:
-+			 /* YCbCr709 */
-+			set_reg_field_value(
-+				value,
-+				3,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else
-+		/* by pass */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_GRPH_MODE);
-+
-+	addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
-+	dal_write_reg(ctx, addr, value);
-+
-+	return true;
-+}
-+
-+void dce110_opp_set_csc_adjustment(
-+	struct output_pixel_processor *opp,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+
-+	/* Apply color adjustments: brightness, saturation, hue, contrast and
-+	 * CSC. No need for different color space routine, color space defines
-+	 * the ideal values only, but keep original design to allow quick switch
-+	 * to the old legacy routines */
-+	switch (adjust->c_space) {
-+	case COLOR_SPACE_SRGB_FULL_RANGE:
-+		set_rgb_adjustment_legacy(opp110, adjust);
-+		break;
-+	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		set_rgb_limited_range_adjustment(
-+			opp110, adjust);
-+		break;
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_YONLY:
-+	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YPBPR601:
-+	case COLOR_SPACE_YPBPR709:
-+		set_yuv_adjustment(opp110, adjust);
-+		break;
-+	default:
-+		set_rgb_adjustment_legacy(opp110, adjust);
-+		break;
-+	}
-+
-+	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-+	configure_graphics_mode(opp110, config, adjust->csc_adjust_type,
-+		adjust->c_space);
-+}
-+
-+void dce110_opp_set_csc_default(
-+	struct output_pixel_processor *opp,
-+	const struct default_adjustment *default_adjust)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
-+
-+	if (default_adjust->force_hw_default == false) {
-+		const struct out_csc_color_matrix *elm;
-+		/* currently parameter not in use */
-+		enum grph_color_adjust_option option =
-+			GRPH_COLOR_MATRIX_HW_DEFAULT;
-+		uint32_t i;
-+		/*
-+		 * HW default false we program locally defined matrix
-+		 * HW default true  we use predefined hw matrix and we
-+		 * do not need to program matrix
-+		 * OEM wants the HW default via runtime parameter.
-+		 */
-+		option = GRPH_COLOR_MATRIX_SW;
-+
-+		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
-+			elm = &global_color_matrix[i];
-+			if (elm->color_space != default_adjust->color_space)
-+				continue;
-+			/* program the matrix with default values from this
-+			 * file */
-+			program_color_matrix(opp110, elm, option);
-+			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+			break;
-+		}
-+	}
-+
-+	/* configure the what we programmed :
-+	 * 1. Default values from this file
-+	 * 2. Use hardware default from ROM_A and we do not need to program
-+	 * matrix */
-+
-+	configure_graphics_mode(opp110, config,
-+		default_adjust->csc_adjust_type,
-+		default_adjust->color_space);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-new file mode 100644
-index 0000000..fdf87bd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-@@ -0,0 +1,610 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_opp.h"
-+
-+#define FMT_REG(reg)\
-+	(reg + opp110->offsets.fmt_offset)
-+
-+/**
-+ *	set_truncation
-+ *	1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
-+ *	2) enable truncation
-+ *	3) HW remove 12bit FMT support for DCE11 power saving reason.
-+ */
-+static void set_truncation(
-+		struct dce110_opp *opp110,
-+		const struct bit_depth_reduction_params *params)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+
-+	/*Disable truncation*/
-+	value = dal_read_reg(opp110->base.ctx, addr);
-+	set_reg_field_value(value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN);
-+	set_reg_field_value(value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH);
-+	set_reg_field_value(value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE);
-+
-+	dal_write_reg(opp110->base.ctx, addr, value);
-+
-+	/* no 10bpc trunc on DCE11*/
-+	if (params->flags.TRUNCATE_ENABLED == 0 ||
-+		params->flags.TRUNCATE_DEPTH == 2)
-+		return;
-+
-+	/*Set truncation depth and Enable truncation*/
-+	set_reg_field_value(value, 1,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN);
-+	set_reg_field_value(value, params->flags.TRUNCATE_MODE,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE);
-+	set_reg_field_value(value, params->flags.TRUNCATE_DEPTH,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH);
-+
-+	dal_write_reg(opp110->base.ctx, addr, value);
-+
-+}
-+
-+/**
-+ *	set_spatial_dither
-+ *	1) set spatial dithering mode: pattern of seed
-+ *	2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
-+ *	3) set random seed
-+ *	4) set random mode
-+ *		lfsr is reset every frame or not reset
-+ *		RGB dithering method
-+ *		0: RGB data are all dithered with x^28+x^3+1
-+ *		1: R data is dithered with x^28+x^3+1
-+ *		G data is dithered with x^28+X^9+1
-+ *		B data is dithered with x^28+x^13+1
-+ *		enable high pass filter or not
-+ *	5) enable spatical dithering
-+ */
-+static void set_spatial_dither(
-+	struct dce110_opp *opp110,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	uint32_t depth_cntl_value = 0;
-+	uint32_t fmt_cntl_value = 0;
-+	uint32_t dither_r_value = 0;
-+	uint32_t dither_g_value = 0;
-+	uint32_t dither_b_value = 0;
-+
-+	/*Disable spatial (random) dithering*/
-+	depth_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE);
-+
-+	dal_write_reg(opp110->base.ctx, addr, depth_cntl_value);
-+
-+	/* no 10bpc on DCE11*/
-+	if (params->flags.SPATIAL_DITHER_ENABLED == 0 ||
-+		params->flags.SPATIAL_DITHER_DEPTH == 2)
-+		return;
-+
-+	addr = FMT_REG(mmFMT_CONTROL);
-+	fmt_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+	/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
-+	if (params->flags.FRAME_RANDOM == 1) {
-+		if (params->flags.SPATIAL_DITHER_DEPTH == 0 ||
-+		params->flags.SPATIAL_DITHER_DEPTH == 1) {
-+			set_reg_field_value(fmt_cntl_value, 15,
-+				FMT_CONTROL,
-+				FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX);
-+			set_reg_field_value(fmt_cntl_value, 2,
-+				FMT_CONTROL,
-+				FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP);
-+		} else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
-+			set_reg_field_value(fmt_cntl_value, 3,
-+				FMT_CONTROL,
-+				FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX);
-+			set_reg_field_value(fmt_cntl_value, 1,
-+				FMT_CONTROL,
-+				FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP);
-+		} else
-+			return;
-+	} else {
-+		set_reg_field_value(fmt_cntl_value, 0,
-+			FMT_CONTROL,
-+			FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX);
-+		set_reg_field_value(fmt_cntl_value, 0,
-+			FMT_CONTROL,
-+			FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP);
-+	}
-+
-+	dal_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
-+
-+	/*Set seed for random values for
-+	 * spatial dithering for R,G,B channels*/
-+	addr = FMT_REG(mmFMT_DITHER_RAND_R_SEED);
-+	set_reg_field_value(dither_r_value, params->r_seed_value,
-+		FMT_DITHER_RAND_R_SEED,
-+		FMT_RAND_R_SEED);
-+	dal_write_reg(opp110->base.ctx, addr, dither_r_value);
-+
-+	addr = FMT_REG(mmFMT_DITHER_RAND_G_SEED);
-+	set_reg_field_value(dither_g_value,
-+		params->g_seed_value,
-+		FMT_DITHER_RAND_G_SEED,
-+		FMT_RAND_G_SEED);
-+	dal_write_reg(opp110->base.ctx, addr, dither_g_value);
-+
-+	addr = FMT_REG(mmFMT_DITHER_RAND_B_SEED);
-+	set_reg_field_value(dither_b_value, params->b_seed_value,
-+		FMT_DITHER_RAND_B_SEED,
-+		FMT_RAND_B_SEED);
-+	dal_write_reg(opp110->base.ctx, addr, dither_b_value);
-+
-+	/* FMT_OFFSET_R_Cr  31:16 0x0 Setting the zero
-+	 * offset for the R/Cr channel, lower 4LSB
-+	 * is forced to zeros. Typically set to 0
-+	 * RGB and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_G_Y   31:16 0x0 Setting the zero
-+	 * offset for the G/Y  channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB
-+	 * and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_B_Cb  31:16 0x0 Setting the zero
-+	 * offset for the B/Cb channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB and
-+	 * 0x80000 YCbCr.
-+	 */
-+
-+	/*Set spatial dithering bit depth*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.SPATIAL_DITHER_DEPTH,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_DEPTH);
-+
-+	/* Set spatial dithering mode
-+	 * (default is Seed patterrn AAAA...)
-+	 */
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.SPATIAL_DITHER_MODE,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_MODE);
-+
-+	/*Reset only at startup*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.FRAME_RANDOM,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_RGB_RANDOM_ENABLE);
-+
-+	/*Set RGB data dithered with x^28+x^3+1*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.RGB_RANDOM,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_RGB_RANDOM_ENABLE);
-+
-+	/*Disable High pass filter*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.HIGHPASS_RANDOM,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_HIGHPASS_RANDOM_ENABLE);
-+
-+	/*Enable spatial dithering*/
-+	set_reg_field_value(depth_cntl_value,
-+		1,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_EN);
-+
-+	addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	dal_write_reg(opp110->base.ctx, addr, depth_cntl_value);
-+
-+}
-+
-+/**
-+ *	SetTemporalDither (Frame Modulation)
-+ *	1) set temporal dither depth
-+ *	2) select pattern: from hard-coded pattern or programmable pattern
-+ *	3) select optimized strips for BGR or RGB LCD sub-pixel
-+ *	4) set s matrix
-+ *	5) set t matrix
-+ *	6) set grey level for 0.25, 0.5, 0.75
-+ *	7) enable temporal dithering
-+ */
-+static void set_temporal_dither(
-+	struct dce110_opp *opp110,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	uint32_t value;
-+
-+	/*Disable temporal (frame modulation) dithering first*/
-+	value = dal_read_reg(opp110->base.ctx, addr);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_RESET);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_OFFSET);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_DEPTH);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_LEVEL);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_25FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_50FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_75FRC_SEL);
-+
-+	dal_write_reg(opp110->base.ctx, addr, value);
-+
-+	/* no 10bpc dither on DCE11*/
-+	if (params->flags.FRAME_MODULATION_ENABLED == 0 ||
-+		params->flags.FRAME_MODULATION_DEPTH == 2)
-+		return;
-+
-+	/* Set temporal dithering depth*/
-+	set_reg_field_value(value,
-+		params->flags.FRAME_MODULATION_DEPTH,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_DEPTH);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_RESET);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_OFFSET);
-+
-+	/*Select legacy pattern based on FRC and Temporal level*/
-+	addr = FMT_REG(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL);
-+	dal_write_reg(opp110->base.ctx, addr, 0);
-+	/*Set s matrix*/
-+	addr = FMT_REG(
-+		mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX);
-+	dal_write_reg(opp110->base.ctx, addr, 0);
-+	/*Set t matrix*/
-+	addr = FMT_REG(
-+		mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX);
-+	dal_write_reg(opp110->base.ctx, addr, 0);
-+
-+	/*Select patterns for 0.25, 0.5 and 0.75 grey level*/
-+	set_reg_field_value(value,
-+		params->flags.TEMPORAL_LEVEL,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_LEVEL);
-+
-+	set_reg_field_value(value,
-+		params->flags.FRC25,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_25FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		params->flags.FRC50,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_50FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		params->flags.FRC75,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_75FRC_SEL);
-+
-+	/*Enable bit reduction by temporal (frame modulation) dithering*/
-+	set_reg_field_value(value,
-+		1,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN);
-+
-+	addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	dal_write_reg(opp110->base.ctx, addr, value);
-+
-+}
-+
-+/**
-+ *	Set Clamping
-+ *	1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
-+ *		1 for 8 bpc
-+ *		2 for 10 bpc
-+ *		3 for 12 bpc
-+ *		7 for programable
-+ *	2) Enable clamp if Limited range requested
-+ */
-+static void set_clamping(
-+	struct dce110_opp *opp110,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	uint32_t clamp_cntl_value = 0;
-+	uint32_t red_clamp_value = 0;
-+	uint32_t green_clamp_value = 0;
-+	uint32_t blue_clamp_value = 0;
-+	uint32_t addr = FMT_REG(mmFMT_CLAMP_CNTL);
-+
-+	clamp_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+
-+	set_reg_field_value(clamp_cntl_value,
-+		0,
-+		FMT_CLAMP_CNTL,
-+		FMT_CLAMP_DATA_EN);
-+
-+	set_reg_field_value(clamp_cntl_value,
-+		0,
-+		FMT_CLAMP_CNTL,
-+		FMT_CLAMP_COLOR_FORMAT);
-+
-+	switch (params->clamping_level) {
-+	case CLAMPING_FULL_RANGE:
-+		break;
-+
-+	case CLAMPING_LIMITED_RANGE_8BPC:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		break;
-+
-+	case CLAMPING_LIMITED_RANGE_10BPC:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			2,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		break;
-+	case CLAMPING_LIMITED_RANGE_12BPC:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			3,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		break;
-+	case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			7,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		/*set the defaults*/
-+		set_reg_field_value(red_clamp_value,
-+			0x10,
-+			FMT_CLAMP_COMPONENT_R,
-+			FMT_CLAMP_LOWER_R);
-+
-+		set_reg_field_value(red_clamp_value,
-+			0xFEF,
-+			FMT_CLAMP_COMPONENT_R,
-+			FMT_CLAMP_UPPER_R);
-+
-+		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_R);
-+		dal_write_reg(opp110->base.ctx, addr, red_clamp_value);
-+
-+		set_reg_field_value(green_clamp_value,
-+			0x10,
-+			FMT_CLAMP_COMPONENT_G,
-+			FMT_CLAMP_LOWER_G);
-+
-+		set_reg_field_value(green_clamp_value,
-+			0xFEF,
-+			FMT_CLAMP_COMPONENT_G,
-+			FMT_CLAMP_UPPER_G);
-+
-+		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_G);
-+		dal_write_reg(opp110->base.ctx, addr, green_clamp_value);
-+
-+		set_reg_field_value(blue_clamp_value,
-+			0x10,
-+			FMT_CLAMP_COMPONENT_B,
-+			FMT_CLAMP_LOWER_B);
-+
-+		set_reg_field_value(blue_clamp_value,
-+			0xFEF,
-+			FMT_CLAMP_COMPONENT_B,
-+			FMT_CLAMP_UPPER_B);
-+
-+		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_B);
-+		dal_write_reg(opp110->base.ctx, addr, blue_clamp_value);
-+
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	addr = FMT_REG(mmFMT_CLAMP_CNTL);
-+	/*Set clamp control*/
-+	dal_write_reg(opp110->base.ctx, addr, clamp_cntl_value);
-+
-+}
-+
-+/**
-+ *	set_pixel_encoding
-+ *
-+ *	Set Pixel Encoding
-+ *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
-+ *		1: YCbCr 4:2:2
-+ */
-+static void set_pixel_encoding(
-+	struct dce110_opp *opp110,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	uint32_t fmt_cntl_value;
-+	uint32_t addr = FMT_REG(mmFMT_CONTROL);
-+
-+	/*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/
-+	fmt_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+
-+	set_reg_field_value(fmt_cntl_value,
-+		0,
-+		FMT_CONTROL,
-+		FMT_PIXEL_ENCODING);
-+
-+	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+		set_reg_field_value(fmt_cntl_value,
-+			1,
-+			FMT_CONTROL,
-+			FMT_PIXEL_ENCODING);
-+
-+		/*00 - Pixels drop mode ,01 - Pixels average mode*/
-+		set_reg_field_value(fmt_cntl_value,
-+			0,
-+			FMT_CONTROL,
-+			FMT_SUBSAMPLING_MODE);
-+
-+		/*00 - Cb before Cr ,01 - Cr before Cb*/
-+		set_reg_field_value(fmt_cntl_value,
-+			0,
-+			FMT_CONTROL,
-+			FMT_SUBSAMPLING_ORDER);
-+	}
-+	dal_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
-+
-+}
-+
-+void dce110_opp_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	set_truncation(opp110, params);
-+	set_spatial_dither(opp110, params);
-+	set_temporal_dither(opp110, params);
-+}
-+
-+void dce110_opp_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	set_clamping(opp110, params);
-+	set_pixel_encoding(opp110, params);
-+}
-+
-+void dce110_opp_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	uint32_t value;
-+	bool enable_dyn_exp = false;
-+	uint32_t addr = FMT_REG(mmFMT_DYNAMIC_EXP_CNTL);
-+
-+	value = dal_read_reg(opp->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-+	set_reg_field_value(value, 0,
-+		FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE);
-+
-+	/* From HW programming guide:
-+		FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output
-+		FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/
-+	if (color_sp == COLOR_SPACE_SRGB_FULL_RANGE)
-+		enable_dyn_exp = true;
-+
-+	/*00 - 10-bit -> 12-bit dynamic expansion*/
-+	/*01 - 8-bit  -> 12-bit dynamic expansion*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		switch (color_dpth) {
-+		case COLOR_DEPTH_888:
-+			set_reg_field_value(value, enable_dyn_exp ? 1:0,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-+			set_reg_field_value(value, 1,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE);
-+			break;
-+		case COLOR_DEPTH_101010:
-+			set_reg_field_value(value, enable_dyn_exp ? 1:0,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-+			set_reg_field_value(value, 0,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	dal_write_reg(opp->ctx, addr, value);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-new file mode 100644
-index 0000000..4cba172
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -0,0 +1,2473 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_opp.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + opp110->offsets.dcp_offset)
-+
-+#define DCFE_REG(reg)\
-+	(reg + opp110->offsets.dcfe_offset)
-+
-+enum {
-+	MAX_PWL_ENTRY = 128,
-+	MAX_REGIONS_NUMBER = 16
-+
-+};
-+
-+struct curve_config {
-+	uint32_t offset;
-+	int8_t segments[MAX_REGIONS_NUMBER];
-+	int8_t begin;
-+};
-+
-+/* BASE */
-+static bool find_software_points(
-+	struct dce110_opp *opp110,
-+	struct fixed31_32 hw_point,
-+	enum channel_name channel,
-+	uint32_t *index_to_start,
-+	uint32_t *index_left,
-+	uint32_t *index_right,
-+	enum hw_point_position *pos)
-+{
-+	const uint32_t max_number =
-+			RGB_256X3X16 + opp110->regamma.extra_points;
-+
-+	struct fixed31_32 left, right;
-+
-+	uint32_t i = *index_to_start;
-+
-+	while (i < max_number) {
-+		if (channel == CHANNEL_NAME_RED) {
-+			left = opp110->
-+					regamma.axis_x_256[i].r;
-+
-+			if (i < max_number - 1)
-+				right = opp110->
-+					regamma.axis_x_256[i + 1].r;
-+			else
-+				right = opp110->
-+					regamma.axis_x_256[max_number - 1].r;
-+		} else if (channel == CHANNEL_NAME_GREEN) {
-+			left = opp110->regamma.axis_x_256[i].g;
-+
-+			if (i < max_number - 1)
-+				right = opp110->
-+					regamma.axis_x_256[i + 1].g;
-+			else
-+				right = opp110->
-+					regamma.axis_x_256[max_number - 1].g;
-+		} else {
-+			left = opp110->regamma.axis_x_256[i].b;
-+
-+			if (i < max_number - 1)
-+				right = opp110->
-+					regamma.axis_x_256[i + 1].b;
-+			else
-+				right = opp110->
-+					regamma.axis_x_256[max_number - 1].b;
-+		}
-+
-+		if (dal_fixed31_32_le(left, hw_point) &&
-+			dal_fixed31_32_le(hw_point, right)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+
-+			if (i < max_number - 1)
-+				*index_right = i + 1;
-+			else
-+				*index_right = max_number - 1;
-+
-+			*pos = HW_POINT_POSITION_MIDDLE;
-+
-+			return true;
-+		} else if ((i == *index_to_start) &&
-+			dal_fixed31_32_le(hw_point, left)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+			*index_right = i;
-+
-+			*pos = HW_POINT_POSITION_LEFT;
-+
-+			return true;
-+		} else if ((i == max_number - 1) &&
-+			dal_fixed31_32_le(right, hw_point)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+			*index_right = i;
-+
-+			*pos = HW_POINT_POSITION_RIGHT;
-+
-+			return true;
-+		}
-+
-+		++i;
-+	}
-+
-+	return false;
-+}
-+
-+static bool find_software_points_dx(
-+	struct dce110_opp *opp110,
-+	struct fixed31_32 hw_point,
-+	enum channel_name channel,
-+	uint32_t *index_to_start,
-+	uint32_t *index_left,
-+	uint32_t *index_right,
-+	enum hw_point_position *pos)
-+{
-+	const uint32_t max_number = DX_GAMMA_RAMP_MAX +
-+					opp110->regamma.extra_points;
-+
-+	struct fixed31_32 left, right;
-+
-+	uint32_t i = *index_to_start;
-+
-+	while (i < max_number) {
-+		if (channel == CHANNEL_NAME_RED) {
-+			left = opp110->regamma.axis_x_1025[i].r;
-+
-+			if (i < DX_GAMMA_RAMP_MAX - 1)
-+				right = opp110->
-+					regamma.axis_x_1025[i + 1].r;
-+			else
-+				right = opp110->
-+				regamma.axis_x_1025[DX_GAMMA_RAMP_MAX-1].r;
-+		} else if (channel == CHANNEL_NAME_GREEN) {
-+			left = opp110->regamma.axis_x_1025[i].g;
-+
-+			if (i < DX_GAMMA_RAMP_MAX - 1)
-+				right = opp110->
-+					regamma.axis_x_1025[i + 1].g;
-+			else
-+				right = opp110->
-+				regamma.axis_x_1025[DX_GAMMA_RAMP_MAX-1].g;
-+		} else {
-+			left = opp110->regamma.axis_x_1025[i].b;
-+
-+			if (i < DX_GAMMA_RAMP_MAX - 1)
-+				right = opp110->
-+					regamma.axis_x_1025[i + 1].b;
-+			else
-+				right = opp110->
-+				regamma.axis_x_1025[DX_GAMMA_RAMP_MAX-1].b;
-+		}
-+
-+		if (dal_fixed31_32_le(left, hw_point) &&
-+			dal_fixed31_32_le(hw_point, right)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+
-+			if (i < DX_GAMMA_RAMP_MAX - 1)
-+				*index_right = i + 1;
-+			else
-+				*index_right = DX_GAMMA_RAMP_MAX - 1;
-+
-+			*pos = HW_POINT_POSITION_MIDDLE;
-+
-+			return true;
-+		} else if ((i == *index_to_start) &&
-+			dal_fixed31_32_le(hw_point, left)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+			*index_right = i;
-+
-+			*pos = HW_POINT_POSITION_LEFT;
-+
-+			return true;
-+		} else if ((i == max_number - 1) &&
-+			dal_fixed31_32_le(right, hw_point)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+			*index_right = i;
-+
-+			*pos = HW_POINT_POSITION_RIGHT;
-+
-+			return true;
-+		}
-+
-+		++i;
-+	}
-+
-+	return false;
-+}
-+
-+static bool build_custom_gamma_mapping_coefficients_worker(
-+	struct dce110_opp *opp110,
-+	struct pixel_gamma_point *coeff,
-+	enum channel_name channel,
-+	uint32_t number_of_points,
-+	enum pixel_format pixel_format)
-+{
-+	uint32_t i = 0;
-+
-+	while (i <= number_of_points) {
-+		struct fixed31_32 coord_x;
-+
-+		uint32_t index_to_start = 0;
-+		uint32_t index_left = 0;
-+		uint32_t index_right = 0;
-+
-+		enum hw_point_position hw_pos;
-+
-+		struct gamma_point *point;
-+
-+		struct fixed31_32 left_pos;
-+		struct fixed31_32 right_pos;
-+
-+		if (pixel_format == PIXEL_FORMAT_FP16)
-+			coord_x = opp110->
-+				regamma.coordinates_x[i].adjusted_x;
-+		else if (channel == CHANNEL_NAME_RED)
-+			coord_x = opp110->
-+				regamma.coordinates_x[i].regamma_y_red;
-+		else if (channel == CHANNEL_NAME_GREEN)
-+			coord_x = opp110->
-+				regamma.coordinates_x[i].regamma_y_green;
-+		else
-+			coord_x = opp110->
-+				regamma.coordinates_x[i].regamma_y_blue;
-+
-+		if (!find_software_points(
-+			opp110, coord_x, channel,
-+			&index_to_start, &index_left, &index_right, &hw_pos)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (index_left >= RGB_256X3X16 +
-+				opp110->regamma.extra_points) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (index_right >= RGB_256X3X16 +
-+				opp110->regamma.extra_points) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (channel == CHANNEL_NAME_RED) {
-+			point = &coeff[i].r;
-+
-+			left_pos = opp110->
-+					regamma.axis_x_256[index_left].r;
-+			right_pos = opp110->
-+					regamma.axis_x_256[index_right].r;
-+		} else if (channel == CHANNEL_NAME_GREEN) {
-+			point = &coeff[i].g;
-+
-+			left_pos = opp110->
-+					regamma.axis_x_256[index_left].g;
-+			right_pos = opp110->
-+					regamma.axis_x_256[index_right].g;
-+		} else {
-+			point = &coeff[i].b;
-+
-+			left_pos = opp110->
-+					regamma.axis_x_256[index_left].b;
-+			right_pos = opp110->
-+					regamma.axis_x_256[index_right].b;
-+		}
-+
-+		if (hw_pos == HW_POINT_POSITION_MIDDLE)
-+			point->coeff = dal_fixed31_32_div(
-+				dal_fixed31_32_sub(
-+					coord_x,
-+					left_pos),
-+				dal_fixed31_32_sub(
-+					right_pos,
-+					left_pos));
-+		else if (hw_pos == HW_POINT_POSITION_LEFT)
-+			point->coeff = opp110->regamma.x_min;
-+		else if (hw_pos == HW_POINT_POSITION_RIGHT)
-+			point->coeff = opp110->regamma.x_max2;
-+		else {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		point->left_index = index_left;
-+		point->right_index = index_right;
-+		point->pos = hw_pos;
-+
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static inline bool build_custom_gamma_mapping_coefficients(
-+	struct dce110_opp *opp110,
-+	enum channel_name channel,
-+	uint32_t number_of_points,
-+	enum pixel_format pixel_format)
-+{
-+	return build_custom_gamma_mapping_coefficients_worker(
-+		opp110, opp110->regamma.coeff128, channel,
-+		number_of_points, pixel_format);
-+}
-+
-+static inline bool build_oem_custom_gamma_mapping_coefficients(
-+	struct dce110_opp *opp110,
-+	enum channel_name channel,
-+	uint32_t number_of_points,
-+	enum pixel_format pixel_format)
-+{
-+	return build_custom_gamma_mapping_coefficients_worker(
-+		opp110, opp110->regamma.coeff128_oem, channel,
-+		number_of_points, pixel_format);
-+}
-+
-+static bool build_custom_dx_gamma_mapping_coefficients(
-+	struct dce110_opp *opp110,
-+	enum channel_name channel,
-+	uint32_t number_of_points,
-+	enum pixel_format pixel_format)
-+{
-+	uint32_t i = 0;
-+
-+	while (i <= number_of_points) {
-+		struct fixed31_32 coord_x;
-+
-+		uint32_t index_to_start = 0;
-+		uint32_t index_left = 0;
-+		uint32_t index_right = 0;
-+
-+		enum hw_point_position hw_pos;
-+
-+		struct gamma_point *point;
-+
-+		struct fixed31_32 left_pos;
-+		struct fixed31_32 right_pos;
-+
-+		if (pixel_format == PIXEL_FORMAT_FP16)
-+			coord_x = opp110->
-+			regamma.coordinates_x[i].adjusted_x;
-+		else if (channel == CHANNEL_NAME_RED)
-+			coord_x = opp110->
-+			regamma.coordinates_x[i].regamma_y_red;
-+		else if (channel == CHANNEL_NAME_GREEN)
-+			coord_x = opp110->
-+			regamma.coordinates_x[i].regamma_y_green;
-+		else
-+			coord_x = opp110->
-+			regamma.coordinates_x[i].regamma_y_blue;
-+
-+		if (!find_software_points_dx(
-+			opp110, coord_x, channel,
-+			&index_to_start, &index_left, &index_right, &hw_pos)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (index_left >= DX_GAMMA_RAMP_MAX +
-+				opp110->regamma.extra_points) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (index_right >= DX_GAMMA_RAMP_MAX +
-+				opp110->regamma.extra_points) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (channel == CHANNEL_NAME_RED) {
-+			point = &opp110->regamma.coeff128_dx[i].r;
-+
-+			left_pos = opp110->
-+					regamma.axis_x_1025[index_left].r;
-+			right_pos = opp110->
-+					regamma.axis_x_1025[index_right].r;
-+		} else if (channel == CHANNEL_NAME_GREEN) {
-+			point = &opp110->regamma.coeff128_dx[i].g;
-+
-+			left_pos = opp110->
-+					regamma.axis_x_1025[index_left].g;
-+			right_pos = opp110->
-+					regamma.axis_x_1025[index_right].g;
-+		} else {
-+			point = &opp110->regamma.coeff128_dx[i].b;
-+
-+			left_pos = opp110->
-+					regamma.axis_x_1025[index_left].b;
-+			right_pos = opp110->
-+					regamma.axis_x_1025[index_right].b;
-+		}
-+
-+		if (hw_pos == HW_POINT_POSITION_MIDDLE)
-+			point->coeff = dal_fixed31_32_div(
-+				dal_fixed31_32_sub(
-+					coord_x,
-+					left_pos),
-+				dal_fixed31_32_sub(
-+					right_pos,
-+					left_pos));
-+		else if (hw_pos == HW_POINT_POSITION_LEFT)
-+			point->coeff = opp110->regamma.x_min;
-+		else if (hw_pos == HW_POINT_POSITION_RIGHT)
-+			point->coeff = opp110->regamma.x_max2;
-+		else {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		point->left_index = index_left;
-+		point->right_index = index_right;
-+		point->pos = hw_pos;
-+
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static struct fixed31_32 calculate_mapped_value(
-+	struct dce110_opp *opp110,
-+	struct pwl_float_data *rgb,
-+	const struct pixel_gamma_point *coeff,
-+	enum channel_name channel,
-+	uint32_t max_index)
-+{
-+	const struct gamma_point *point;
-+
-+	struct fixed31_32 result;
-+
-+	if (channel == CHANNEL_NAME_RED)
-+		point = &coeff->r;
-+	else if (channel == CHANNEL_NAME_GREEN)
-+		point = &coeff->g;
-+	else
-+		point = &coeff->b;
-+
-+	if ((point->left_index < 0) || (point->left_index > max_index)) {
-+		BREAK_TO_DEBUGGER();
-+		return dal_fixed31_32_zero;
-+	}
-+
-+	if ((point->right_index < 0) || (point->right_index > max_index)) {
-+		BREAK_TO_DEBUGGER();
-+		return dal_fixed31_32_zero;
-+	}
-+
-+	if (point->pos == HW_POINT_POSITION_MIDDLE)
-+		if (channel == CHANNEL_NAME_RED)
-+			result = dal_fixed31_32_add(
-+				dal_fixed31_32_mul(
-+					point->coeff,
-+					dal_fixed31_32_sub(
-+						rgb[point->right_index].r,
-+						rgb[point->left_index].r)),
-+				rgb[point->left_index].r);
-+		else if (channel == CHANNEL_NAME_GREEN)
-+			result = dal_fixed31_32_add(
-+				dal_fixed31_32_mul(
-+					point->coeff,
-+					dal_fixed31_32_sub(
-+						rgb[point->right_index].g,
-+						rgb[point->left_index].g)),
-+				rgb[point->left_index].g);
-+		else
-+			result = dal_fixed31_32_add(
-+				dal_fixed31_32_mul(
-+					point->coeff,
-+					dal_fixed31_32_sub(
-+						rgb[point->right_index].b,
-+						rgb[point->left_index].b)),
-+				rgb[point->left_index].b);
-+	else if (point->pos == HW_POINT_POSITION_LEFT) {
-+		BREAK_TO_DEBUGGER();
-+		result = opp110->regamma.x_min;
-+	} else {
-+		BREAK_TO_DEBUGGER();
-+		result = opp110->regamma.x_max1;
-+	}
-+
-+	return result;
-+}
-+
-+static inline struct fixed31_32 calculate_regamma_user_mapped_value(
-+	struct dce110_opp *opp110,
-+	const struct pixel_gamma_point *coeff,
-+	enum channel_name channel,
-+	uint32_t max_index)
-+{
-+	return calculate_mapped_value(
-+		opp110, opp110->regamma.rgb_oem,
-+		coeff, channel, max_index);
-+}
-+
-+static inline struct fixed31_32 calculate_user_mapped_value(
-+	struct dce110_opp *opp110,
-+	const struct pixel_gamma_point *coeff,
-+	enum channel_name channel,
-+	uint32_t max_index)
-+{
-+	return calculate_mapped_value(
-+		opp110, opp110->regamma.rgb_user,
-+		coeff, channel, max_index);
-+}
-+
-+static inline struct fixed31_32 calculate_oem_mapped_value(
-+	struct dce110_opp *opp110,
-+	uint32_t index,
-+	enum channel_name channel,
-+	uint32_t max_index)
-+{
-+	return calculate_regamma_user_mapped_value(
-+		opp110, opp110->regamma.coeff128_oem +
-+		index, channel, max_index);
-+}
-+
-+static void scale_oem_gamma(
-+	struct dce110_opp *opp110,
-+	const struct regamma_ramp *regamma_ramp)
-+{
-+	const uint16_t max_driver = 0xFFFF;
-+	const uint16_t max_os = 0xFF00;
-+
-+	uint16_t scale = max_os;
-+
-+	uint32_t i;
-+
-+	struct pwl_float_data *rgb = opp110->regamma.rgb_oem;
-+	struct pwl_float_data *rgb_last = rgb + RGB_256X3X16 - 1;
-+
-+	/* find OEM maximum */
-+
-+	i = 0;
-+
-+	do {
-+		if ((regamma_ramp->gamma[i] > max_os) ||
-+			(regamma_ramp->gamma[i + RGB_256X3X16] > max_os) ||
-+			(regamma_ramp->gamma[i + 2 * RGB_256X3X16] > max_os)) {
-+			scale = max_driver;
-+			break;
-+		}
-+
-+		++i;
-+	} while (i != RGB_256X3X16);
-+
-+	/* scale */
-+
-+	i = 0;
-+
-+	do {
-+		rgb->r = dal_fixed31_32_div_int(
-+			dal_fixed31_32_from_int(
-+				regamma_ramp->gamma[i]),
-+			scale);
-+		rgb->g = dal_fixed31_32_div_int(
-+			dal_fixed31_32_from_int(
-+				regamma_ramp->gamma[i + RGB_256X3X16]),
-+			scale);
-+		rgb->b = dal_fixed31_32_div_int(
-+			dal_fixed31_32_from_int(
-+				regamma_ramp->gamma[i + 2 * RGB_256X3X16]),
-+			scale);
-+
-+		++rgb;
-+		++i;
-+	} while (i != RGB_256X3X16);
-+
-+	/* add 3 extra points, 2 physical plus 1 virtual */
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			opp110->regamma.divider1);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			opp110->regamma.divider1);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			opp110->regamma.divider1);
-+
-+	++rgb;
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			opp110->regamma.divider2);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			opp110->regamma.divider2);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			opp110->regamma.divider2);
-+
-+	++rgb;
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			opp110->regamma.divider3);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			opp110->regamma.divider3);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			opp110->regamma.divider3);
-+}
-+
-+static inline void copy_rgb_regamma_to_coordinates_x(
-+	struct dce110_opp *opp110)
-+{
-+	struct hw_x_point *coords = opp110->regamma.coordinates_x;
-+	const struct pwl_float_data_ex *rgb_regamma =
-+			opp110->regamma.rgb_regamma;
-+
-+	uint32_t i = 0;
-+
-+	while (i <= opp110->regamma.hw_points_num) {
-+		coords->regamma_y_red = rgb_regamma->r;
-+		coords->regamma_y_green = rgb_regamma->g;
-+		coords->regamma_y_blue = rgb_regamma->b;
-+
-+		++coords;
-+		++rgb_regamma;
-+		++i;
-+	}
-+}
-+
-+static bool calculate_interpolated_hardware_curve(
-+	struct dce110_opp *opp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	struct pwl_result_data *rgb_resulted =
-+			opp110->regamma.rgb_resulted;
-+
-+	const struct pixel_gamma_point *coeff;
-+	uint32_t max_entries = opp110->regamma.extra_points - 1;
-+
-+	uint32_t i = 0;
-+
-+	if (gamma_ramp->type == GAMMA_RAMP_RBG256X3X16) {
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_RED,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_GREEN,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_BLUE,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		coeff = opp110->regamma.coeff128;
-+		max_entries += RGB_256X3X16;
-+	} else if (gamma_ramp->type == GAMMA_RAMP_DXGI_1) {
-+		if (!build_custom_dx_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_RED,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_dx_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_GREEN,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_dx_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_BLUE,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		coeff = opp110->regamma.coeff128_dx;
-+		max_entries += DX_GAMMA_RAMP_MAX;
-+	} else {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	while (i <= opp110->regamma.hw_points_num) {
-+		rgb_resulted->red = calculate_user_mapped_value(
-+			opp110, coeff, CHANNEL_NAME_RED, max_entries);
-+		rgb_resulted->green = calculate_user_mapped_value(
-+			opp110, coeff, CHANNEL_NAME_GREEN, max_entries);
-+		rgb_resulted->blue = calculate_user_mapped_value(
-+			opp110, coeff, CHANNEL_NAME_BLUE, max_entries);
-+
-+		++coeff;
-+		++rgb_resulted;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static void map_standard_regamma_hw_to_x_user(
-+	struct dce110_opp *opp110,
-+	enum gamma_ramp_type type,
-+	const struct gamma_parameters *params)
-+{
-+	struct pwl_result_data *rgb_resulted =
-+			opp110->regamma.rgb_resulted;
-+	const struct pwl_float_data_ex *rgb_regamma =
-+			opp110->regamma.rgb_regamma;
-+
-+	uint32_t i = 0;
-+
-+	while (i <= opp110->regamma.hw_points_num) {
-+		rgb_resulted->red = rgb_regamma->r;
-+		rgb_resulted->green = rgb_regamma->g;
-+		rgb_resulted->blue = rgb_regamma->b;
-+
-+		++rgb_resulted;
-+		++rgb_regamma;
-+		++i;
-+	}
-+}
-+
-+bool dce110_opp_map_legacy_and_regamma_hw_to_x_user(
-+	struct output_pixel_processor *opp,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	if (params->regamma.features.bits.GAMMA_RAMP_ARRAY ||
-+		params->regamma.features.bits.APPLY_DEGAMMA) {
-+
-+		const uint32_t max_entries =
-+			RGB_256X3X16 + opp110->regamma.extra_points - 1;
-+
-+		const struct pixel_gamma_point *coeff =
-+				opp110->regamma.coeff128;
-+		struct pwl_result_data *rgb_resulted =
-+				opp110->regamma.rgb_resulted;
-+
-+		uint32_t i = 0;
-+
-+		scale_oem_gamma(opp110, &params->regamma.regamma_ramp);
-+
-+		copy_rgb_regamma_to_coordinates_x(opp110);
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_RED,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_GREEN,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_BLUE,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		while (i <= opp110->regamma.hw_points_num) {
-+			rgb_resulted->red =
-+				calculate_regamma_user_mapped_value(opp110,
-+					coeff,
-+					CHANNEL_NAME_RED, max_entries);
-+			rgb_resulted->green =
-+				calculate_regamma_user_mapped_value(opp110,
-+					coeff,
-+					CHANNEL_NAME_GREEN, max_entries);
-+			rgb_resulted->blue =
-+				calculate_regamma_user_mapped_value(opp110,
-+					coeff,
-+					CHANNEL_NAME_BLUE, max_entries);
-+
-+			++coeff;
-+			++rgb_resulted;
-+			++i;
-+		}
-+	} else
-+		map_standard_regamma_hw_to_x_user(opp110,
-+				gamma_ramp->type,
-+				params);
-+
-+	return true;
-+}
-+
-+static bool map_regamma_hw_to_x_user(
-+	struct dce110_opp *opp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	/* setup to spare calculated ideal regamma values */
-+	if (params->regamma.features.bits.GAMMA_RAMP_ARRAY ||
-+		params->regamma.features.bits.APPLY_DEGAMMA) {
-+
-+		const uint32_t max_entries =
-+			RGB_256X3X16 + opp110->regamma.extra_points - 1;
-+
-+		const struct pixel_gamma_point *coeff =
-+				opp110->regamma.coeff128;
-+		struct hw_x_point *coords =
-+				opp110->regamma.coordinates_x;
-+
-+		uint32_t i = 0;
-+
-+		scale_oem_gamma(opp110, &params->regamma.regamma_ramp);
-+
-+		copy_rgb_regamma_to_coordinates_x(opp110);
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_RED,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_GREEN,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_BLUE,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		while (i <= opp110->regamma.hw_points_num) {
-+			coords->regamma_y_red =
-+				calculate_regamma_user_mapped_value(opp110,
-+					coeff,
-+					CHANNEL_NAME_RED, max_entries);
-+			coords->regamma_y_green =
-+				calculate_regamma_user_mapped_value(opp110,
-+					coeff,
-+					CHANNEL_NAME_GREEN, max_entries);
-+			coords->regamma_y_blue =
-+				calculate_regamma_user_mapped_value(opp110,
-+					coeff,
-+					CHANNEL_NAME_BLUE, max_entries);
-+
-+			++coeff;
-+			++coords;
-+			++i;
-+		}
-+	} else {
-+		copy_rgb_regamma_to_coordinates_x(opp110);
-+	}
-+
-+	return calculate_interpolated_hardware_curve(opp110, gamma_ramp,
-+		params);
-+}
-+
-+static void build_regamma_coefficients(
-+	const struct regamma_lut *regamma,
-+	bool is_degamma_srgb,
-+	struct gamma_coefficients *coefficients)
-+{
-+	/* sRGB should apply 2.4 */
-+	static const int32_t numerator01[3] = { 31308, 31308, 31308 };
-+	static const int32_t numerator02[3] = { 12920, 12920, 12920 };
-+	static const int32_t numerator03[3] = { 55, 55, 55 };
-+	static const int32_t numerator04[3] = { 55, 55, 55 };
-+	static const int32_t numerator05[3] = { 2400, 2400, 2400 };
-+
-+	/* Non-sRGB should apply 2.2 */
-+	static const int32_t numerator11[3] = { 180000, 180000, 180000 };
-+	static const int32_t numerator12[3] = { 4500, 4500, 4500 };
-+	static const int32_t numerator13[3] = { 99, 99, 99 };
-+	static const int32_t numerator14[3] = { 99, 99, 99 };
-+	static const int32_t numerator15[3] = { 2200, 2200, 2200 };
-+
-+	const int32_t *numerator1;
-+	const int32_t *numerator2;
-+	const int32_t *numerator3;
-+	const int32_t *numerator4;
-+	const int32_t *numerator5;
-+
-+	uint32_t i = 0;
-+
-+	if (!regamma->features.bits.GAMMA_RAMP_ARRAY) {
-+		numerator1 = regamma->gamma_coeff.a0;
-+		numerator2 = regamma->gamma_coeff.a1;
-+		numerator3 = regamma->gamma_coeff.a2;
-+		numerator4 = regamma->gamma_coeff.a3;
-+		numerator5 = regamma->gamma_coeff.gamma;
-+	} else if (is_degamma_srgb) {
-+		numerator1 = numerator01;
-+		numerator2 = numerator02;
-+		numerator3 = numerator03;
-+		numerator4 = numerator04;
-+		numerator5 = numerator05;
-+	} else {
-+		numerator1 = numerator11;
-+		numerator2 = numerator12;
-+		numerator3 = numerator13;
-+		numerator4 = numerator14;
-+		numerator5 = numerator15;
-+	}
-+
-+	do {
-+		coefficients->a0[i] = dal_fixed31_32_from_fraction(
-+			numerator1[i], 10000000);
-+		coefficients->a1[i] = dal_fixed31_32_from_fraction(
-+			numerator2[i], 1000);
-+		coefficients->a2[i] = dal_fixed31_32_from_fraction(
-+			numerator3[i], 1000);
-+		coefficients->a3[i] = dal_fixed31_32_from_fraction(
-+			numerator4[i], 1000);
-+		coefficients->user_gamma[i] = dal_fixed31_32_from_fraction(
-+			numerator5[i], 1000);
-+
-+		++i;
-+	} while (i != ARRAY_SIZE(regamma->gamma_coeff.a0));
-+}
-+
-+static struct fixed31_32 translate_from_linear_space(
-+	struct fixed31_32 arg,
-+	struct fixed31_32 a0,
-+	struct fixed31_32 a1,
-+	struct fixed31_32 a2,
-+	struct fixed31_32 a3,
-+	struct fixed31_32 gamma)
-+{
-+	const struct fixed31_32 one = dal_fixed31_32_from_int(1);
-+
-+	if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0)))
-+		return dal_fixed31_32_sub(
-+			a2,
-+			dal_fixed31_32_mul(
-+				dal_fixed31_32_add(
-+					one,
-+					a3),
-+				dal_fixed31_32_pow(
-+					dal_fixed31_32_neg(arg),
-+					dal_fixed31_32_recip(gamma))));
-+	else if (dal_fixed31_32_le(a0, arg))
-+		return dal_fixed31_32_sub(
-+			dal_fixed31_32_mul(
-+				dal_fixed31_32_add(
-+					one,
-+					a3),
-+				dal_fixed31_32_pow(
-+					arg,
-+					dal_fixed31_32_recip(gamma))),
-+			a2);
-+	else
-+		return dal_fixed31_32_mul(
-+			arg,
-+			a1);
-+}
-+
-+static inline struct fixed31_32 translate_from_linear_space_ex(
-+	struct fixed31_32 arg,
-+	struct gamma_coefficients *coeff,
-+	uint32_t color_index)
-+{
-+	return translate_from_linear_space(
-+		arg,
-+		coeff->a0[color_index],
-+		coeff->a1[color_index],
-+		coeff->a2[color_index],
-+		coeff->a3[color_index],
-+		coeff->user_gamma[color_index]);
-+}
-+
-+static bool build_regamma_curve(
-+	struct dce110_opp *opp110,
-+	const struct gamma_parameters *params)
-+{
-+	struct pwl_float_data_ex *rgb = opp110->regamma.rgb_regamma;
-+
-+	uint32_t i;
-+
-+	if (!params->regamma.features.bits.GAMMA_RAMP_ARRAY &&
-+		params->regamma.features.bits.APPLY_DEGAMMA) {
-+		struct gamma_coefficients coeff;
-+
-+		struct hw_x_point *coord_x =
-+				opp110->regamma.coordinates_x;
-+
-+		build_regamma_coefficients(
-+			&params->regamma,
-+			params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB,
-+			&coeff);
-+
-+		/* Use opp110->regamma.coordinates_x to retrieve
-+		 * coordinates chosen base on given user curve (future task).
-+		 * The x values are exponentially distributed and currently
-+		 * it is hard-coded, the user curve shape is ignored.
-+		 * The future task is to recalculate opp110-
-+		 * regamma.coordinates_x based on input/user curve,
-+		 * translation from 256/1025 to 128 pwl points.
-+		 */
-+
-+		i = 0;
-+
-+		while (i != opp110->regamma.hw_points_num + 1) {
-+			rgb->r = translate_from_linear_space_ex(
-+				coord_x->adjusted_x, &coeff, 0);
-+			rgb->g = translate_from_linear_space_ex(
-+				coord_x->adjusted_x, &coeff, 1);
-+			rgb->b = translate_from_linear_space_ex(
-+				coord_x->adjusted_x, &coeff, 2);
-+
-+			++coord_x;
-+			++rgb;
-+			++i;
-+		}
-+	} else {
-+		const uint32_t max_entries =
-+			RGB_256X3X16 + opp110->regamma.extra_points - 1;
-+
-+		/* interpolate between 256 input points and output 185 points */
-+
-+		scale_oem_gamma(opp110, &params->regamma.regamma_ramp);
-+
-+		if (!build_oem_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_RED,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_oem_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_GREEN,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!build_oem_custom_gamma_mapping_coefficients(
-+			opp110, CHANNEL_NAME_BLUE,
-+			opp110->regamma.hw_points_num,
-+			params->surface_pixel_format)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		i = 0;
-+
-+		while (i != opp110->regamma.hw_points_num + 1) {
-+			rgb->r = calculate_oem_mapped_value(
-+				opp110, i, CHANNEL_NAME_RED, max_entries);
-+			rgb->g = calculate_oem_mapped_value(
-+				opp110, i, CHANNEL_NAME_GREEN, max_entries);
-+			rgb->b = calculate_oem_mapped_value(
-+				opp110, i, CHANNEL_NAME_BLUE, max_entries);
-+			++rgb;
-+			++i;
-+		}
-+	}
-+
-+	return true;
-+}
-+
-+static void build_new_custom_resulted_curve(
-+	struct dce110_opp *opp110,
-+	const struct gamma_parameters *params)
-+{
-+	struct pwl_result_data *rgb = opp110->regamma.rgb_resulted;
-+	struct pwl_result_data *rgb_plus_1 = rgb + 1;
-+
-+	uint32_t i;
-+
-+	i = 0;
-+
-+	while (i != opp110->regamma.hw_points_num + 1) {
-+		rgb->red = dal_fixed31_32_clamp(
-+			rgb->red, opp110->regamma.x_min,
-+			opp110->regamma.x_max1);
-+		rgb->green = dal_fixed31_32_clamp(
-+			rgb->green, opp110->regamma.x_min,
-+			opp110->regamma.x_max1);
-+		rgb->blue = dal_fixed31_32_clamp(
-+			rgb->blue, opp110->regamma.x_min,
-+			opp110->regamma.x_max1);
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	rgb = opp110->regamma.rgb_resulted;
-+
-+	i = 1;
-+
-+	while (i != opp110->regamma.hw_points_num + 1) {
-+		if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
-+			rgb_plus_1->red = rgb->red;
-+		if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
-+			rgb_plus_1->green = rgb->green;
-+		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
-+			rgb_plus_1->blue = rgb->blue;
-+
-+		rgb->delta_red = dal_fixed31_32_sub(
-+			rgb_plus_1->red,
-+			rgb->red);
-+		rgb->delta_green = dal_fixed31_32_sub(
-+			rgb_plus_1->green,
-+			rgb->green);
-+		rgb->delta_blue = dal_fixed31_32_sub(
-+			rgb_plus_1->blue,
-+			rgb->blue);
-+
-+		++rgb_plus_1;
-+		++rgb;
-+		++i;
-+	}
-+}
-+
-+static bool rebuild_curve_configuration_magic(
-+	struct dce110_opp *opp110)
-+{
-+	const struct fixed31_32 magic_number =
-+		dal_fixed31_32_from_fraction(249, 1000);
-+
-+	struct fixed31_32 y_r;
-+	struct fixed31_32 y_g;
-+	struct fixed31_32 y_b;
-+
-+	struct fixed31_32 y1_min;
-+	struct fixed31_32 y2_max;
-+	struct fixed31_32 y3_max;
-+
-+	y_r = opp110->regamma.rgb_resulted[0].red;
-+	y_g = opp110->regamma.rgb_resulted[0].green;
-+	y_b = opp110->regamma.rgb_resulted[0].blue;
-+
-+	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
-+
-+	opp110->regamma.arr_points[0].x =
-+			opp110->regamma.coordinates_x[0].adjusted_x;
-+	opp110->regamma.arr_points[0].y = y1_min;
-+	opp110->regamma.arr_points[0].slope = dal_fixed31_32_div(
-+		opp110->regamma.arr_points[0].y,
-+		opp110->regamma.arr_points[0].x);
-+
-+	opp110->regamma.arr_points[1].x = dal_fixed31_32_add(
-+		opp110->regamma.coordinates_x
-+		[opp110->regamma.hw_points_num - 1].adjusted_x,
-+		magic_number);
-+
-+	opp110->regamma.arr_points[2].x =
-+			opp110->regamma.arr_points[1].x;
-+
-+	y_r = opp110->regamma.rgb_resulted
-+			[opp110->regamma.hw_points_num - 1].red;
-+	y_g = opp110->regamma.rgb_resulted
-+			[opp110->regamma.hw_points_num - 1].green;
-+	y_b = opp110->regamma.rgb_resulted
-+			[opp110->regamma.hw_points_num - 1].blue;
-+
-+	y2_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-+
-+	opp110->regamma.arr_points[1].y = y2_max;
-+
-+	y_r = opp110->regamma.rgb_resulted
-+			[opp110->regamma.hw_points_num].red;
-+	y_g = opp110->regamma.rgb_resulted
-+			[opp110->regamma.hw_points_num].green;
-+	y_b = opp110->regamma.rgb_resulted
-+			[opp110->regamma.hw_points_num].blue;
-+
-+	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-+
-+	opp110->regamma.arr_points[2].y = y3_max;
-+
-+	opp110->regamma.arr_points[2].slope = dal_fixed31_32_one;
-+
-+	return true;
-+}
-+
-+static bool build_custom_float(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	bool *negative,
-+	uint32_t *mantissa,
-+	uint32_t *exponenta)
-+{
-+	uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
-+
-+	const struct fixed31_32 mantissa_constant_plus_max_fraction =
-+		dal_fixed31_32_from_fraction(
-+			(1LL << (format->mantissa_bits + 1)) - 1,
-+			1LL << format->mantissa_bits);
-+
-+	struct fixed31_32 mantiss;
-+
-+	if (dal_fixed31_32_eq(
-+		value,
-+		dal_fixed31_32_zero)) {
-+		*negative = false;
-+		*mantissa = 0;
-+		*exponenta = 0;
-+		return true;
-+	}
-+
-+	if (dal_fixed31_32_lt(
-+		value,
-+		dal_fixed31_32_zero)) {
-+		*negative = format->sign;
-+		value = dal_fixed31_32_neg(value);
-+	} else {
-+		*negative = false;
-+	}
-+
-+	if (dal_fixed31_32_lt(
-+		value,
-+		dal_fixed31_32_one)) {
-+		uint32_t i = 1;
-+
-+		do {
-+			value = dal_fixed31_32_shl(value, 1);
-+			++i;
-+		} while (dal_fixed31_32_lt(
-+			value,
-+			dal_fixed31_32_one));
-+
-+		--i;
-+
-+		if (exp_offset <= i) {
-+			*mantissa = 0;
-+			*exponenta = 0;
-+			return true;
-+		}
-+
-+		*exponenta = exp_offset - i;
-+	} else if (dal_fixed31_32_le(
-+		mantissa_constant_plus_max_fraction,
-+		value)) {
-+		uint32_t i = 1;
-+
-+		do {
-+			value = dal_fixed31_32_shr(value, 1);
-+			++i;
-+		} while (dal_fixed31_32_lt(
-+			mantissa_constant_plus_max_fraction,
-+			value));
-+
-+		*exponenta = exp_offset + i - 1;
-+	} else {
-+		*exponenta = exp_offset;
-+	}
-+
-+	mantiss = dal_fixed31_32_sub(
-+		value,
-+		dal_fixed31_32_one);
-+
-+	if (dal_fixed31_32_lt(
-+			mantiss,
-+			dal_fixed31_32_zero) ||
-+		dal_fixed31_32_lt(
-+			dal_fixed31_32_one,
-+			mantiss))
-+		mantiss = dal_fixed31_32_zero;
-+	else
-+		mantiss = dal_fixed31_32_shl(
-+			mantiss,
-+			format->mantissa_bits);
-+
-+	*mantissa = dal_fixed31_32_floor(mantiss);
-+
-+	return true;
-+}
-+
-+static bool setup_custom_float(
-+	const struct custom_float_format *format,
-+	bool negative,
-+	uint32_t mantissa,
-+	uint32_t exponenta,
-+	uint32_t *result)
-+{
-+	uint32_t i = 0;
-+	uint32_t j = 0;
-+
-+	uint32_t value = 0;
-+
-+	/* verification code:
-+	 * once calculation is ok we can remove it */
-+
-+	const uint32_t mantissa_mask =
-+		(1 << (format->mantissa_bits + 1)) - 1;
-+
-+	const uint32_t exponenta_mask =
-+		(1 << (format->exponenta_bits + 1)) - 1;
-+
-+	if (mantissa & ~mantissa_mask) {
-+		BREAK_TO_DEBUGGER();
-+		mantissa = mantissa_mask;
-+	}
-+
-+	if (exponenta & ~exponenta_mask) {
-+		BREAK_TO_DEBUGGER();
-+		exponenta = exponenta_mask;
-+	}
-+
-+	/* end of verification code */
-+
-+	while (i < format->mantissa_bits) {
-+		uint32_t mask = 1 << i;
-+
-+		if (mantissa & mask)
-+			value |= mask;
-+
-+		++i;
-+	}
-+
-+	while (j < format->exponenta_bits) {
-+		uint32_t mask = 1 << j;
-+
-+		if (exponenta & mask)
-+			value |= mask << i;
-+
-+		++j;
-+	}
-+
-+	if (negative && format->sign)
-+		value |= 1 << (i + j);
-+
-+	*result = value;
-+
-+	return true;
-+}
-+
-+static bool convert_to_custom_float_format(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	uint32_t *result)
-+{
-+	uint32_t mantissa;
-+	uint32_t exponenta;
-+	bool negative;
-+
-+	return build_custom_float(
-+		value, format, &negative, &mantissa, &exponenta) &&
-+	setup_custom_float(
-+		format, negative, mantissa, exponenta, result);
-+}
-+
-+static bool convert_to_custom_float_format_ex(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	struct custom_float_value *result)
-+{
-+	return build_custom_float(
-+		value, format,
-+		&result->negative, &result->mantissa, &result->exponenta) &&
-+	setup_custom_float(
-+		format, result->negative, result->mantissa, result->exponenta,
-+		&result->value);
-+}
-+
-+static bool convert_to_custom_float(
-+	struct dce110_opp *opp110)
-+{
-+	struct custom_float_format fmt;
-+
-+	struct pwl_result_data *rgb = opp110->regamma.rgb_resulted;
-+
-+	uint32_t i = 0;
-+
-+	fmt.exponenta_bits = 6;
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	if (!convert_to_custom_float_format(
-+		opp110->regamma.arr_points[0].x,
-+		&fmt,
-+		&opp110->regamma.arr_points[0].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		opp110->regamma.arr_points[0].offset,
-+		&fmt,
-+		&opp110->regamma.arr_points[0].custom_float_offset)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		opp110->regamma.arr_points[0].slope,
-+		&fmt,
-+		&opp110->regamma.arr_points[0].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 10;
-+	fmt.sign = false;
-+
-+	if (!convert_to_custom_float_format(
-+		opp110->regamma.arr_points[1].x,
-+		&fmt,
-+		&opp110->regamma.arr_points[1].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		opp110->regamma.arr_points[1].y,
-+		&fmt,
-+		&opp110->regamma.arr_points[1].custom_float_y)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		opp110->regamma.arr_points[2].slope,
-+		&fmt,
-+		&opp110->regamma.arr_points[2].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	while (i != opp110->regamma.hw_points_num) {
-+		if (!convert_to_custom_float_format(
-+			rgb->red,
-+			&fmt,
-+			&rgb->red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->green,
-+			&fmt,
-+			&rgb->green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->blue,
-+			&fmt,
-+			&rgb->blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->delta_red,
-+			&fmt,
-+			&rgb->delta_red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->delta_green,
-+			&fmt,
-+			&rgb->delta_green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->delta_blue,
-+			&fmt,
-+			&rgb->delta_blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static bool round_custom_float_6_12(
-+	struct hw_x_point *x)
-+{
-+	struct custom_float_format fmt;
-+
-+	struct custom_float_value value;
-+
-+	fmt.exponenta_bits = 6;
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	if (!convert_to_custom_float_format_ex(
-+		x->x, &fmt, &value))
-+		return false;
-+
-+	x->adjusted_x = x->x;
-+
-+	if (value.mantissa) {
-+		BREAK_TO_DEBUGGER();
-+
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool build_hw_curve_configuration(
-+	const struct curve_config *curve_config,
-+	struct gamma_curve *gamma_curve,
-+	struct curve_points *curve_points,
-+	struct hw_x_point *points,
-+	uint32_t *number_of_points)
-+{
-+	const int8_t max_regions_number = ARRAY_SIZE(curve_config->segments);
-+
-+	int8_t i;
-+
-+	uint8_t segments_calculation[8] = { 0 };
-+
-+	struct fixed31_32 region1 = dal_fixed31_32_zero;
-+	struct fixed31_32 region2;
-+	struct fixed31_32 increment;
-+
-+	uint32_t index = 0;
-+	uint32_t segments = 0;
-+	uint32_t max_number;
-+
-+	bool result = false;
-+
-+	if (!number_of_points) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	max_number = *number_of_points;
-+
-+	i = 0;
-+
-+	while (i != max_regions_number) {
-+		gamma_curve[i].offset = 0;
-+		gamma_curve[i].segments_num = 0;
-+
-+		++i;
-+	}
-+
-+	i = 0;
-+
-+	while (i != max_regions_number) {
-+		/* number should go in uninterruptible sequence */
-+		if (curve_config->segments[i] == -1)
-+			break;
-+
-+		ASSERT(curve_config->segments[i] >= 0);
-+
-+		segments += (1 << curve_config->segments[i]);
-+
-+		++i;
-+	}
-+
-+	if (segments > max_number) {
-+		BREAK_TO_DEBUGGER();
-+	} else {
-+		int32_t divisor;
-+		uint32_t offset = 0;
-+		int8_t begin = curve_config->begin;
-+		int32_t region_number = 0;
-+
-+		i = begin;
-+
-+		while ((index < max_number) &&
-+			(region_number < max_regions_number) &&
-+			(i <= 1)) {
-+			int32_t j = 0;
-+
-+			segments = curve_config->segments[region_number];
-+			divisor = 1 << segments;
-+
-+			if (segments == -1) {
-+				if (i > 0) {
-+					region1 = dal_fixed31_32_shl(
-+						dal_fixed31_32_one,
-+						i - 1);
-+					region2 = dal_fixed31_32_shl(
-+						dal_fixed31_32_one,
-+						i);
-+				} else {
-+					region1 = dal_fixed31_32_shr(
-+						dal_fixed31_32_one,
-+						-(i - 1));
-+					region2 = dal_fixed31_32_shr(
-+						dal_fixed31_32_one,
-+						-i);
-+				}
-+
-+				break;
-+			}
-+
-+			if (i > -1) {
-+				region1 = dal_fixed31_32_shl(
-+					dal_fixed31_32_one,
-+					i);
-+				region2 = dal_fixed31_32_shl(
-+					dal_fixed31_32_one,
-+					i + 1);
-+			} else {
-+				region1 = dal_fixed31_32_shr(
-+					dal_fixed31_32_one,
-+					-i);
-+				region2 = dal_fixed31_32_shr(
-+					dal_fixed31_32_one,
-+					-(i + 1));
-+			}
-+
-+			gamma_curve[region_number].offset = offset;
-+			gamma_curve[region_number].segments_num = segments;
-+
-+			offset += divisor;
-+
-+			++segments_calculation[segments];
-+
-+			increment = dal_fixed31_32_div_int(
-+				dal_fixed31_32_sub(
-+					region2,
-+					region1),
-+				divisor);
-+
-+			points[index].x = region1;
-+
-+			round_custom_float_6_12(points + index);
-+
-+			++index;
-+			++region_number;
-+
-+			while ((index < max_number) && (j < divisor - 1)) {
-+				region1 = dal_fixed31_32_add(
-+					region1,
-+					increment);
-+
-+				points[index].x = region1;
-+				points[index].adjusted_x = region1;
-+
-+				++index;
-+				++j;
-+			}
-+
-+			++i;
-+		}
-+
-+		points[index].x = region1;
-+
-+		round_custom_float_6_12(points + index);
-+
-+		*number_of_points = index;
-+
-+		result = true;
-+	}
-+
-+	curve_points[0].x = points[0].adjusted_x;
-+	curve_points[0].offset = dal_fixed31_32_zero;
-+
-+	curve_points[1].x = points[index - 1].adjusted_x;
-+	curve_points[1].offset = dal_fixed31_32_zero;
-+
-+	curve_points[2].x = points[index].adjusted_x;
-+	curve_points[2].offset = dal_fixed31_32_zero;
-+
-+	return result;
-+}
-+
-+static bool setup_distribution_points(
-+	struct dce110_opp *opp110)
-+{
-+	uint32_t hw_points_num = MAX_PWL_ENTRY * 2;
-+
-+	struct curve_config cfg;
-+
-+	cfg.offset = 0;
-+
-+		cfg.segments[0] = 3;
-+		cfg.segments[1] = 4;
-+		cfg.segments[2] = 4;
-+		cfg.segments[3] = 4;
-+		cfg.segments[4] = 4;
-+		cfg.segments[5] = 4;
-+		cfg.segments[6] = 4;
-+		cfg.segments[7] = 4;
-+		cfg.segments[8] = 5;
-+		cfg.segments[9] = 5;
-+		cfg.segments[10] = 0;
-+		cfg.segments[11] = -1;
-+		cfg.segments[12] = -1;
-+		cfg.segments[13] = -1;
-+		cfg.segments[14] = -1;
-+		cfg.segments[15] = -1;
-+
-+	cfg.begin = -10;
-+
-+	if (!build_hw_curve_configuration(
-+		&cfg, opp110->regamma.arr_curve_points,
-+		opp110->regamma.arr_points,
-+		opp110->regamma.coordinates_x, &hw_points_num)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	opp110->regamma.hw_points_num = hw_points_num;
-+
-+	return true;
-+}
-+
-+
-+/*
-+ *****************************************************************************
-+ *  Function: regamma_config_regions_and_segments
-+ *
-+ *     build regamma curve by using predefined hw points
-+ *     uses interface parameters ,like EDID coeff.
-+ *
-+ * @param   : parameters   interface parameters
-+ *  @return void
-+ *
-+ *  @note
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void regamma_config_regions_and_segments(
-+	struct dce110_opp *opp110)
-+{
-+	struct gamma_curve *curve;
-+	uint32_t value = 0;
-+
-+	{
-+		set_reg_field_value(
-+			value,
-+			opp110->regamma.arr_points[0].custom_float_x,
-+			REGAMMA_CNTLA_START_CNTL,
-+			REGAMMA_CNTLA_EXP_REGION_START);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			REGAMMA_CNTLA_START_CNTL,
-+			REGAMMA_CNTLA_EXP_REGION_START_SEGMENT);
-+
-+		dal_write_reg(opp110->base.ctx,
-+				DCP_REG(mmREGAMMA_CNTLA_START_CNTL),
-+				value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			opp110->regamma.arr_points[0].custom_float_slope,
-+			REGAMMA_CNTLA_SLOPE_CNTL,
-+			REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_SLOPE_CNTL), value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			opp110->regamma.arr_points[1].custom_float_x,
-+			REGAMMA_CNTLA_END_CNTL1,
-+			REGAMMA_CNTLA_EXP_REGION_END);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_END_CNTL1), value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			opp110->regamma.arr_points[2].custom_float_slope,
-+			REGAMMA_CNTLA_END_CNTL2,
-+			REGAMMA_CNTLA_EXP_REGION_END_BASE);
-+
-+		set_reg_field_value(
-+			value,
-+			opp110->regamma.arr_points[1].custom_float_y,
-+			REGAMMA_CNTLA_END_CNTL2,
-+			REGAMMA_CNTLA_EXP_REGION_END_SLOPE);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value);
-+	}
-+
-+	curve = opp110->regamma.arr_curve_points;
-+
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS);
-+
-+		dal_write_reg(
-+			opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_0_1),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_2_3),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_4_5),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_6_7),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_8_9),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_10_11),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_12_13),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_14_15),
-+			value);
-+	}
-+}
-+
-+static void program_pwl(
-+	struct dce110_opp *opp110,
-+	const struct gamma_parameters *params)
-+{
-+	uint32_t value;
-+
-+	{
-+		uint8_t max_tries = 10;
-+		uint8_t counter = 0;
-+
-+		/* Power on LUT memory */
-+		value = dal_read_reg(opp110->base.ctx,
-+				DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCFE_MEM_PWR_CTRL,
-+			DCP_REGAMMA_MEM_PWR_DIS);
-+
-+		dal_write_reg(opp110->base.ctx,
-+				DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
-+
-+		while (counter < max_tries) {
-+			value =
-+				dal_read_reg(
-+					opp110->base.ctx,
-+					DCFE_REG(mmDCFE_MEM_PWR_STATUS));
-+
-+			if (get_reg_field_value(
-+				value,
-+				DCFE_MEM_PWR_STATUS,
-+				DCP_REGAMMA_MEM_PWR_STATE) == 0)
-+				break;
-+
-+			++counter;
-+		}
-+
-+		if (counter == max_tries) {
-+			dal_logger_write(opp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: regamma lut was not powered on "
-+				"in a timely manner,"
-+				" programming still proceeds\n",
-+				__func__);
-+		}
-+	}
-+
-+	value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		7,
-+		REGAMMA_LUT_WRITE_EN_MASK,
-+		REGAMMA_LUT_WRITE_EN_MASK);
-+
-+	dal_write_reg(opp110->base.ctx,
-+		DCP_REG(mmREGAMMA_LUT_WRITE_EN_MASK), value);
-+	dal_write_reg(opp110->base.ctx,
-+		DCP_REG(mmREGAMMA_LUT_INDEX), 0);
-+
-+	/* Program REGAMMA_LUT_DATA */
-+	{
-+		const uint32_t addr = DCP_REG(mmREGAMMA_LUT_DATA);
-+
-+		uint32_t i = 0;
-+
-+		struct pwl_result_data *rgb =
-+				opp110->regamma.rgb_resulted;
-+
-+		while (i != opp110->regamma.hw_points_num) {
-+			dal_write_reg(opp110->base.ctx, addr, rgb->red_reg);
-+			dal_write_reg(opp110->base.ctx, addr, rgb->green_reg);
-+			dal_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
-+
-+			dal_write_reg(opp110->base.ctx, addr,
-+				rgb->delta_red_reg);
-+			dal_write_reg(opp110->base.ctx, addr,
-+				rgb->delta_green_reg);
-+			dal_write_reg(opp110->base.ctx, addr,
-+				rgb->delta_blue_reg);
-+
-+			++rgb;
-+			++i;
-+		}
-+	}
-+
-+	/*  we are done with DCP LUT memory; re-enable low power mode */
-+	value = dal_read_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFE_MEM_PWR_CTRL,
-+		DCP_REGAMMA_MEM_PWR_DIS);
-+
-+	dal_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
-+}
-+
-+void dce110_opp_power_on_regamma_lut(
-+	struct output_pixel_processor *opp,
-+	bool power_on)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	uint32_t value =
-+		dal_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFE_MEM_PWR_CTRL,
-+		DCP_REGAMMA_MEM_PWR_DIS);
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFE_MEM_PWR_CTRL,
-+		DCP_LUT_MEM_PWR_DIS);
-+
-+	dal_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
-+}
-+
-+static bool scale_gamma(
-+	struct dce110_opp *opp110,
-+	const struct gamma_ramp *gamma_ramp,
-+	const struct gamma_parameters *params)
-+{
-+	const struct gamma_ramp_rgb256x3x16 *gamma;
-+	bool use_palette = params->surface_pixel_format == PIXEL_FORMAT_INDEX8;
-+
-+	const uint16_t max_driver = 0xFFFF;
-+	const uint16_t max_os = 0xFF00;
-+
-+	uint16_t scaler = max_os;
-+
-+	uint32_t i;
-+
-+	struct dev_c_lut *palette = opp110->regamma.saved_palette;
-+
-+	struct pwl_float_data *rgb = opp110->regamma.rgb_user;
-+	struct pwl_float_data *rgb_last = rgb + RGB_256X3X16 - 1;
-+
-+	if (gamma_ramp->type == GAMMA_RAMP_RBG256X3X16)
-+		gamma = &gamma_ramp->gamma_ramp_rgb256x3x16;
-+	else
-+		return false; /* invalid option */
-+
-+	i = 0;
-+
-+	do {
-+		if ((gamma->red[i] > max_os) ||
-+			(gamma->green[i] > max_os) ||
-+			(gamma->blue[i] > max_os)) {
-+			scaler = max_driver;
-+			break;
-+		}
-+		++i;
-+	} while (i != RGB_256X3X16);
-+
-+	i = 0;
-+
-+	if (use_palette)
-+		do {
-+			rgb->r = dal_fixed31_32_from_fraction(
-+				gamma->red[palette->red], scaler);
-+			rgb->g = dal_fixed31_32_from_fraction(
-+				gamma->green[palette->green], scaler);
-+			rgb->b = dal_fixed31_32_from_fraction(
-+				gamma->blue[palette->blue], scaler);
-+
-+			++palette;
-+			++rgb;
-+			++i;
-+		} while (i != RGB_256X3X16);
-+	else
-+		do {
-+			rgb->r = dal_fixed31_32_from_fraction(
-+				gamma->red[i], scaler);
-+			rgb->g = dal_fixed31_32_from_fraction(
-+				gamma->green[i], scaler);
-+			rgb->b = dal_fixed31_32_from_fraction(
-+				gamma->blue[i], scaler);
-+
-+			++rgb;
-+			++i;
-+		} while (i != RGB_256X3X16);
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			opp110->regamma.divider1);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			opp110->regamma.divider1);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			opp110->regamma.divider1);
-+
-+	++rgb;
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			opp110->regamma.divider2);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			opp110->regamma.divider2);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			opp110->regamma.divider2);
-+
-+	++rgb;
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			opp110->regamma.divider3);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			opp110->regamma.divider3);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			opp110->regamma.divider3);
-+
-+	return true;
-+}
-+
-+
-+static void configure_regamma_mode(
-+	struct dce110_opp *opp110,
-+	const struct gamma_parameters *params,
-+	bool force_bypass)
-+{
-+	const uint32_t addr = DCP_REG(mmREGAMMA_CONTROL);
-+
-+	enum wide_gamut_regamma_mode mode =
-+		WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A;
-+
-+	uint32_t value = dal_read_reg(opp110->base.ctx, addr);
-+
-+	if (force_bypass) {
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+
-+		dal_write_reg(opp110->base.ctx, addr, value);
-+
-+		return;
-+	}
-+
-+	if (params->regamma_adjust_type == GRAPHICS_REGAMMA_ADJUST_BYPASS)
-+		mode = WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS;
-+	else if (params->regamma_adjust_type == GRAPHICS_REGAMMA_ADJUST_HW) {
-+		if (params->surface_pixel_format == PIXEL_FORMAT_FP16)
-+			mode = WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS;
-+		else
-+			mode = WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24;
-+	}
-+
-+	switch (mode) {
-+	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS:
-+		set_reg_field_value(
-+			value,
-+			0,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+		break;
-+	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24:
-+		set_reg_field_value(
-+			value,
-+			1,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+		break;
-+	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22:
-+		set_reg_field_value(
-+			value,
-+			2,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+		break;
-+	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A:
-+		set_reg_field_value(
-+			value,
-+			3,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+		break;
-+	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B:
-+		set_reg_field_value(
-+			value,
-+			4,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dal_write_reg(opp110->base.ctx, addr, value);
-+}
-+
-+bool dce110_opp_set_regamma(
-+	struct output_pixel_processor *opp,
-+	const struct gamma_ramp *ramp,
-+	const struct gamma_parameters *params,
-+	bool force_bypass)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	if (force_bypass) {
-+		configure_regamma_mode(opp110, params, true);
-+	} else {
-+		/* 1. Scale gamma to 0 - 1 to m_pRgbUser */
-+		if (!scale_gamma(opp110, ramp, params)) {
-+			ASSERT_CRITICAL(false);
-+			/* invalid option */
-+			return false;
-+		}
-+
-+		/* 2. Configure regamma curve without analysis (future task) */
-+		/*    and program the PWL regions and segments */
-+		if (params->regamma_adjust_type == GRAPHICS_REGAMMA_ADJUST_SW ||
-+			params->surface_pixel_format == PIXEL_FORMAT_FP16) {
-+
-+			/* 3. Setup x exponentially distributed points */
-+			if (!setup_distribution_points(opp110)) {
-+				ASSERT_CRITICAL(false);
-+				/* invalid option */
-+				return false;
-+			}
-+
-+			/* 4. Build ideal regamma curve */
-+			if (!build_regamma_curve(opp110, params)) {
-+				ASSERT_CRITICAL(false);
-+				/* invalid parameters or bug */
-+				return false;
-+			}
-+
-+			/* 5. Map user gamma (evenly distributed x points) to
-+			 * new curve when x is y from ideal regamma , step 5 */
-+			if (!map_regamma_hw_to_x_user(
-+				opp110, ramp, params)) {
-+				ASSERT_CRITICAL(false);
-+				/* invalid parameters or bug */
-+				return false;
-+			}
-+
-+			/* 6.Build and verify resulted curve */
-+			build_new_custom_resulted_curve(opp110, params);
-+
-+			/* 7. Build and translate x to hw format */
-+			if (!rebuild_curve_configuration_magic(opp110)) {
-+				ASSERT_CRITICAL(false);
-+				/* invalid parameters or bug */
-+				return false;
-+			}
-+
-+			/* 8. convert all params to the custom float format */
-+			if (!convert_to_custom_float(opp110)) {
-+				ASSERT_CRITICAL(false);
-+				/* invalid parameters or bug */
-+				return false;
-+			}
-+
-+			/* 9. program regamma curve configuration */
-+			regamma_config_regions_and_segments(opp110);
-+
-+			/* 10. Program PWL */
-+			program_pwl(opp110, params);
-+		}
-+
-+		/*
-+		 * 11. program regamma config
-+		 */
-+		configure_regamma_mode(opp110, params, false);
-+	}
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-new file mode 100644
-index 0000000..d2594a9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -0,0 +1,1276 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "dce110/dce110_link_encoder.h"
-+#include "dce110/dce110_mem_input.h"
-+#include "dce110/dce110_ipp.h"
-+#include "dce110/dce110_transform.h"
-+#include "dce110/dce110_stream_encoder.h"
-+#include "dce110/dce110_opp.h"
-+#include "link_encoder_types.h"
-+#include "stream_encoder_types.h"
-+
-+enum dce110_clk_src_array_id {
-+	DCE110_CLK_SRC_PLL0 = 0,
-+	DCE110_CLK_SRC_PLL1,
-+	DCE110_CLK_SRC_EXT,
-+
-+	DCE110_CLK_SRC_TOTAL
-+};
-+
-+static void set_vendor_info_packet(struct core_stream *stream,
-+		struct hw_info_packet *info_packet)
-+{
-+	uint32_t length = 0;
-+	bool hdmi_vic_mode = false;
-+	uint8_t checksum = 0;
-+	uint32_t i = 0;
-+	enum dc_timing_3d_format format;
-+
-+	ASSERT_CRITICAL(stream != NULL);
-+	ASSERT_CRITICAL(info_packet != NULL);
-+
-+	format = stream->public.timing.timing_3d_format;
-+
-+	/* Can be different depending on packet content */
-+	length = 5;
-+
-+	if (stream->public.timing.hdmi_vic != 0
-+			&& stream->public.timing.h_total >= 3840
-+			&& stream->public.timing.v_total >= 2160)
-+		hdmi_vic_mode = true;
-+
-+	/* According to HDMI 1.4a CTS, VSIF should be sent
-+	 * for both 3D stereo and HDMI VIC modes.
-+	 * For all other modes, there is no VSIF sent.  */
-+
-+	if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
-+		return;
-+
-+	/* 24bit IEEE Registration identifier (0x000c03). LSB first. */
-+	info_packet->sb[1] = 0x03;
-+	info_packet->sb[2] = 0x0C;
-+	info_packet->sb[3] = 0x00;
-+
-+	/*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
-+	 * The value for HDMI_Video_Format are:
-+	 * 0x0 (0b000) - No additional HDMI video format is presented in this
-+	 * packet
-+	 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
-+	 * parameter follows
-+	 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
-+	 * potentially 3D_Ext_Data follows
-+	 * 0x3..0x7 (0b011..0b111) - reserved for future use */
-+	if (format != TIMING_3D_FORMAT_NONE)
-+		info_packet->sb[4] = (2 << 5);
-+	else if (hdmi_vic_mode)
-+		info_packet->sb[4] = (1 << 5);
-+
-+	/* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
-+	 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
-+	 * The value for 3D_Structure are:
-+	 * 0x0 - Frame Packing
-+	 * 0x1 - Field Alternative
-+	 * 0x2 - Line Alternative
-+	 * 0x3 - Side-by-Side (full)
-+	 * 0x4 - L + depth
-+	 * 0x5 - L + depth + graphics + graphics-depth
-+	 * 0x6 - Top-and-Bottom
-+	 * 0x7 - Reserved for future use
-+	 * 0x8 - Side-by-Side (Half)
-+	 * 0x9..0xE - Reserved for future use
-+	 * 0xF - Not used */
-+	switch (format) {
-+	case TIMING_3D_FORMAT_HW_FRAME_PACKING:
-+	case TIMING_3D_FORMAT_SW_FRAME_PACKING:
-+		info_packet->sb[5] = (0x0 << 4);
-+		break;
-+
-+	case TIMING_3D_FORMAT_SIDE_BY_SIDE:
-+	case TIMING_3D_FORMAT_SBS_SW_PACKED:
-+		info_packet->sb[5] = (0x8 << 4);
-+		length = 6;
-+		break;
-+
-+	case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
-+	case TIMING_3D_FORMAT_TB_SW_PACKED:
-+		info_packet->sb[5] = (0x6 << 4);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	/*PB5: If PB4 is set to 0x1 (extended resolution format)
-+	 * fill PB5 with the correct HDMI VIC code */
-+	if (hdmi_vic_mode)
-+		info_packet->sb[5] = stream->public.timing.hdmi_vic;
-+
-+	/* Header */
-+	info_packet->hb0 = 0x81; /* VSIF packet type. */
-+	info_packet->hb1 = 0x01; /* Version */
-+
-+	/* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
-+	info_packet->hb2 = (uint8_t) (length);
-+
-+	/* Calculate checksum */
-+	checksum = 0;
-+	checksum += info_packet->hb0;
-+	checksum += info_packet->hb1;
-+	checksum += info_packet->hb2;
-+
-+	for (i = 1; i <= length; i++)
-+		checksum += info_packet->sb[i];
-+
-+	info_packet->sb[0] = (uint8_t) (0x100 - checksum);
-+
-+	info_packet->valid = true;
-+}
-+
-+static enum ds_color_space build_default_color_space(
-+		struct core_stream *stream)
-+{
-+	enum ds_color_space color_space =
-+			DS_COLOR_SPACE_SRGB_FULLRANGE;
-+	struct dc_crtc_timing *timing = &stream->public.timing;
-+
-+	switch (stream->signal) {
-+	/* TODO: implement other signal color space setting */
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	{
-+		uint32_t pix_clk_khz;
-+
-+		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 &&
-+			timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
-+			if (timing->timing_standard ==
-+					TIMING_STANDARD_CEA770 &&
-+				timing->timing_standard ==
-+						TIMING_STANDARD_CEA861)
-+				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
-+
-+			pix_clk_khz = timing->pix_clk_khz / 10;
-+			if (timing->h_addressable == 640 &&
-+				timing->v_addressable == 480 &&
-+				(pix_clk_khz == 2520 || pix_clk_khz == 2517))
-+				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
-+		} else {
-+			if (timing->timing_standard ==
-+					TIMING_STANDARD_CEA770 ||
-+					timing->timing_standard ==
-+					TIMING_STANDARD_CEA861) {
-+
-+				color_space =
-+					(timing->pix_clk_khz > PIXEL_CLOCK) ?
-+						DS_COLOR_SPACE_YCBCR709 :
-+						DS_COLOR_SPACE_YCBCR601;
-+			}
-+		}
-+		break;
-+	}
-+	default:
-+		switch (timing->pixel_encoding) {
-+		case PIXEL_ENCODING_YCBCR422:
-+		case PIXEL_ENCODING_YCBCR444:
-+			if (timing->pix_clk_khz > PIXEL_CLOCK)
-+				color_space = DS_COLOR_SPACE_YCBCR709;
-+			else
-+				color_space = DS_COLOR_SPACE_YCBCR601;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	}
-+	return color_space;
-+}
-+
-+static void set_avi_info_frame(struct hw_info_packet *info_packet,
-+		struct core_stream *stream)
-+{
-+	enum ds_color_space color_space = DS_COLOR_SPACE_UNKNOWN;
-+	struct info_frame info_frame = { {0} };
-+	uint32_t pixel_encoding = 0;
-+	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
-+	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
-+	bool itc = false;
-+	uint8_t cn0_cn1 = 0;
-+	uint8_t *check_sum = NULL;
-+	uint8_t byte_index = 0;
-+
-+	if (info_packet == NULL)
-+		return;
-+
-+	color_space = build_default_color_space(stream);
-+
-+	/* Initialize header */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
-+			info_frame_type = INFO_FRAME_AVI;
-+	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
-+	* not be used in HDMI 2.0 (Section 10.1) */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.version =
-+			INFO_FRAME_VERSION_2;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
-+			INFO_FRAME_SIZE_AVI;
-+
-+	/* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
-+	* according to HDMI 2.0 spec (Section 10.1)
-+	* Add "case PixelEncoding_YCbCr420:    pixelEncoding = 3; break;"
-+	* when YCbCr 4:2:0 is supported by DAL hardware. */
-+
-+	switch (stream->public.timing.pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		pixel_encoding = 1;
-+		break;
-+
-+	case PIXEL_ENCODING_YCBCR444:
-+		pixel_encoding = 2;
-+		break;
-+
-+	case PIXEL_ENCODING_RGB:
-+	default:
-+		pixel_encoding = 0;
-+	}
-+
-+	/* Y0_Y1_Y2 : The pixel encoding */
-+	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
-+		pixel_encoding;
-+
-+
-+	/* A0 = 1 Active Format Information valid */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
-+		ACTIVE_FORMAT_VALID;
-+
-+	/* B0, B1 = 3; Bar info data is valid */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
-+		BAR_INFO_BOTH_VALID;
-+
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
-+			PICTURE_SCALING_UNIFORM;
-+
-+	/* S0, S1 : Underscan / Overscan */
-+	/* TODO: un-hardcode scan type */
-+	scan_type = SCANNING_TYPE_UNDERSCAN;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
-+
-+	/* C0, C1 : Colorimetry */
-+	if (color_space == DS_COLOR_SPACE_YCBCR709)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_ITU709;
-+	else if (color_space == DS_COLOR_SPACE_YCBCR601)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_ITU601;
-+	else
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_NO_DATA;
-+
-+
-+	/* TODO: un-hardcode aspect ratio */
-+	aspect = stream->public.timing.aspect_ratio;
-+
-+	switch (aspect) {
-+	case ASPECT_RATIO_4_3:
-+	case ASPECT_RATIO_16_9:
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
-+		break;
-+
-+	case ASPECT_RATIO_NO_DATA:
-+	case ASPECT_RATIO_64_27:
-+	case ASPECT_RATIO_256_135:
-+	default:
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
-+	}
-+
-+	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
-+			ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
-+
-+	/* TODO: un-hardcode cn0_cn1 and itc */
-+	cn0_cn1 = 0;
-+	itc = false;
-+
-+	if (itc) {
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
-+			cn0_cn1;
-+	}
-+
-+	/* TODO: un-hardcode q0_q1 */
-+	if (color_space == DS_COLOR_SPACE_SRGB_FULLRANGE)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_FULL_RANGE;
-+	else if (color_space == DS_COLOR_SPACE_SRGB_LIMITEDRANGE)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_LIMITED_RANGE;
-+	else
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_DEFAULT_RANGE;
-+
-+	/* TODO : We should handle YCC quantization,
-+	 * but we do not have matrix calculation */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
-+					YYC_QUANTIZATION_LIMITED_RANGE;
-+
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
-+					stream->public.timing.vic;
-+
-+	/* pixel repetition
-+	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
-+	 * repetition start from 1 */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
-+
-+	/* Bar Info
-+	 * barTop:    Line Number of End of Top Bar.
-+	 * barBottom: Line Number of Start of Bottom Bar.
-+	 * barLeft:   Pixel Number of End of Left Bar.
-+	 * barRight:  Pixel Number of Start of Right Bar. */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
-+			stream->public.timing.v_border_top;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
-+		(stream->public.timing.v_border_top
-+			- stream->public.timing.v_border_bottom + 1);
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
-+			stream->public.timing.h_border_left;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
-+		(stream->public.timing.h_total
-+			- stream->public.timing.h_border_right + 1);
-+
-+	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
-+	check_sum =
-+		&info_frame.
-+		avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
-+	*check_sum = INFO_FRAME_AVI + INFO_FRAME_SIZE_AVI
-+			+ INFO_FRAME_VERSION_2;
-+
-+	for (byte_index = 1; byte_index <= INFO_FRAME_SIZE_AVI; byte_index++)
-+		*check_sum += info_frame.avi_info_packet.info_packet_hdmi.
-+				packet_raw_data.sb[byte_index];
-+
-+	/* one byte complement */
-+	*check_sum = (uint8_t) (0x100 - *check_sum);
-+
-+	/* Store in hw_path_mode */
-+	info_packet->hb0 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
-+	info_packet->hb1 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
-+	info_packet->hb2 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
-+
-+	for (byte_index = 0; byte_index < sizeof(info_packet->sb); byte_index++)
-+		info_packet->sb[byte_index] = info_frame.avi_info_packet.
-+		info_packet_hdmi.packet_raw_data.sb[byte_index];
-+
-+	info_packet->valid = true;
-+}
-+
-+static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
-+	struct encoder_info_frame *encoder_info_frame)
-+{
-+	dc_service_memset(
-+		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
-+
-+	/* For gamut we recalc checksum */
-+	if (hw_info_frame->gamut_packet.valid) {
-+		uint8_t chk_sum = 0;
-+		uint8_t *ptr;
-+		uint8_t i;
-+
-+		dc_service_memmove(
-+						&encoder_info_frame->gamut,
-+						&hw_info_frame->gamut_packet,
-+						sizeof(struct hw_info_packet));
-+
-+		/*start of the Gamut data. */
-+		ptr = &encoder_info_frame->gamut.sb[3];
-+
-+		for (i = 0; i <= encoder_info_frame->gamut.sb[1]; i++)
-+			chk_sum += ptr[i];
-+
-+		encoder_info_frame->gamut.sb[2] = (uint8_t) (0x100 - chk_sum);
-+	}
-+
-+	if (hw_info_frame->avi_info_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->avi,
-+						&hw_info_frame->avi_info_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->vendor_info_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->vendor,
-+						&hw_info_frame->vendor_info_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->spd_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->spd,
-+						&hw_info_frame->spd_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->vsc_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->vsc,
-+						&hw_info_frame->vsc_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+}
-+
-+static void build_info_frame(struct core_stream *stream)
-+{
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+	struct hw_info_frame info_frame = { { 0 } };
-+
-+	/* default all packets to invalid */
-+	info_frame.avi_info_packet.valid = false;
-+	info_frame.gamut_packet.valid = false;
-+	info_frame.vendor_info_packet.valid = false;
-+	info_frame.spd_packet.valid = false;
-+	info_frame.vsc_packet.valid = false;
-+
-+	signal = stream->sink->public.sink_signal;
-+
-+	/* HDMi and DP have different info packets*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		set_avi_info_frame(&info_frame.avi_info_packet,
-+				stream);
-+		set_vendor_info_packet(stream, &info_frame.vendor_info_packet);
-+	}
-+
-+	translate_info_frame(&info_frame,
-+			&stream->encoder_info_frame);
-+}
-+
-+
-+bool dce110_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	struct dc *dc,
-+	struct resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct clock_source_init_data clk_src_init_data = { 0 };
-+	struct audio_init_data audio_init_data = { 0 };
-+	struct dc_context *ctx = dc->ctx;
-+	pool->adapter_srv = adapter_serv;
-+
-+	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+
-+	clk_src_init_data.as = adapter_serv;
-+	clk_src_init_data.ctx = ctx;
-+	clk_src_init_data.clk_src_id.enum_id = ENUM_ID_1;
-+	clk_src_init_data.clk_src_id.type = OBJECT_TYPE_CLOCK_SOURCE;
-+	pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
-+
-+	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL0;
-+	pool->clock_sources[DCE110_CLK_SRC_PLL0] = dal_clock_source_create(
-+							&clk_src_init_data);
-+	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL1;
-+	pool->clock_sources[DCE110_CLK_SRC_PLL1] = dal_clock_source_create(
-+							&clk_src_init_data);
-+	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_EXTERNAL;
-+	pool->clock_sources[DCE110_CLK_SRC_EXT] = dal_clock_source_create(
-+							&clk_src_init_data);
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] == NULL) {
-+			dal_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
-+	if (pool->display_clock == NULL) {
-+		dal_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->irqs = dal_irq_service_create(
-+				dal_adapter_service_get_dce_version(
-+					dc->res_pool.adapter_srv),
-+				&init_data);
-+		if (!pool->irqs)
-+			goto irqs_create_fail;
-+
-+	}
-+
-+	pool->controller_count =
-+		dal_adapter_service_get_func_controllers_num(adapter_serv);
-+	pool->stream_enc_count = 3;
-+	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+	if (pool->scaler_filter == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dal_error("DC: failed to create filter!\n");
-+		goto filter_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		pool->timing_generators[i] = dce110_timing_generator_create(
-+				adapter_serv,
-+				ctx,
-+				i + 1);
-+		if (pool->timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->mis[i] = dce110_mem_input_create(
-+			ctx,
-+			i + 1);
-+		if (pool->mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->ipps[i] = dce110_ipp_create(
-+			ctx,
-+			i + 1);
-+		if (pool->ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->transforms[i] = dce110_transform_create(
-+				ctx,
-+				i + 1);
-+		if (pool->transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create transform!\n");
-+			goto controller_create_fail;
-+		}
-+		dce110_transform_set_scaler_filter(
-+				pool->transforms[i],
-+				pool->scaler_filter);
-+
-+		pool->opps[i] = dce110_opp_create(
-+			ctx,
-+			i + 1);
-+		if (pool->opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+	}
-+
-+	audio_init_data.as = adapter_serv;
-+	audio_init_data.ctx = ctx;
-+	pool->audio_count = 0;
-+	for (i = 0; i < pool->controller_count; i++) {
-+		struct graphics_object_id obj_id;
-+
-+		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		if (false == dal_graphics_object_id_is_valid(obj_id)) {
-+			/* no more valid audio objects */
-+			break;
-+		}
-+
-+		audio_init_data.audio_stream_id = obj_id;
-+		pool->audios[i] = dal_audio_create(&audio_init_data);
-+		if (pool->audios[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create DPPs!\n");
-+			goto audio_create_fail;
-+		}
-+		pool->audio_count++;
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		struct stream_enc_init_data enc_init_data = { 0 };
-+		/* TODO: rework fragile code*/
-+		enc_init_data.stream_engine_id = i;
-+		enc_init_data.adapter_service = adapter_serv;
-+		enc_init_data.ctx = dc->ctx;
-+		if (pool->stream_engines.u_all & 1 << i) {
-+			pool->stream_enc[i] = dce110_stream_encoder_create(
-+					&enc_init_data);
-+
-+			if (pool->stream_enc[i] == NULL) {
-+				BREAK_TO_DEBUGGER();
-+				dal_error("DC: failed to create stream_encoder!\n");
-+				goto stream_enc_create_fail;
-+			}
-+		}
-+	}
-+
-+	return true;
-+
-+stream_enc_create_fail:
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dce110_stream_encoder_destroy(&pool->stream_enc[i]);
-+	}
-+
-+audio_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+
-+controller_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce110_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce110_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce110_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL)
-+			dce110_mem_input_destroy(&pool->mis[i]);
-+
-+		if (pool->timing_generators[i] != NULL)
-+			dce110_timing_generator_destroy(
-+				&pool->timing_generators[i]);
-+	}
-+
-+filter_create_fail:
-+	dal_irq_service_destroy(&pool->irqs);
-+
-+irqs_create_fail:
-+	dal_display_clock_destroy(&pool->display_clock);
-+
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dal_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+	return false;
-+}
-+
-+void dce110_destruct_resource_pool(struct resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce110_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce110_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce110_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL)
-+			dce110_mem_input_destroy(&pool->mis[i]);
-+
-+		if (pool->timing_generators[i] != NULL)
-+			dce110_timing_generator_destroy(
-+				&pool->timing_generators[i]);
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dce110_stream_encoder_destroy(&pool->stream_enc[i]);
-+	}
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL) {
-+			dal_clock_source_destroy(&pool->clock_sources[i]);
-+		}
-+	}
-+
-+	for (i = 0; i < pool->audio_count; i++)	{
-+		if (pool->audios[i] != NULL) {
-+			dal_audio_destroy(&pool->audios[i]);
-+		}
-+	}
-+	if (pool->display_clock != NULL) {
-+		dal_display_clock_destroy(&pool->display_clock);
-+	}
-+
-+	if (pool->scaler_filter != NULL) {
-+		dal_scaler_filter_destroy(&pool->scaler_filter);
-+	}
-+	if (pool->irqs != NULL) {
-+		dal_irq_service_destroy(&pool->irqs);
-+	}
-+
-+	if (pool->adapter_srv != NULL) {
-+		dal_adapter_service_destroy(&pool->adapter_srv);
-+	}
-+}
-+
-+static void attach_stream_to_controller(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	res_ctx->controller_ctx[stream->controller_idx].stream = stream;
-+}
-+
-+static bool assign_first_free_controller(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	uint8_t i;
-+	for (i = 0; i < res_ctx->pool.controller_count; i++) {
-+		if (!res_ctx->controller_ctx[i].stream) {
-+			stream->tg = res_ctx->pool.timing_generators[i];
-+			stream->mi = res_ctx->pool.mis[i];
-+			stream->ipp = res_ctx->pool.ipps[i];
-+			stream->xfm = res_ctx->pool.transforms[i];
-+			stream->opp = res_ctx->pool.opps[i];
-+			stream->controller_idx = i;
-+			stream->dis_clk = res_ctx->pool.display_clock;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+static void set_stream_engine_in_use(
-+		struct resource_context *res_ctx,
-+		struct stream_encoder *stream_enc)
-+{
-+	int i;
-+
-+	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
-+		if (res_ctx->pool.stream_enc[i] == stream_enc)
-+			res_ctx->is_stream_enc_acquired[i] = true;
-+	}
-+}
-+
-+static struct stream_encoder *find_first_free_match_stream_enc_for_link(
-+		struct resource_context *res_ctx,
-+		struct core_link *link)
-+{
-+	uint8_t i;
-+
-+	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
-+		if (!res_ctx->is_stream_enc_acquired[i] &&
-+				res_ctx->pool.stream_enc[i]) {
-+			if (res_ctx->pool.stream_enc[i]->id ==
-+					link->link_enc->preferred_engine)
-+				return res_ctx->pool.stream_enc[i];
-+		}
-+	}
-+
-+	/* TODO: Handle MST*/
-+
-+	return NULL;
-+}
-+
-+/* TODO: release audio object */
-+static void set_audio_in_use(
-+		struct resource_context *res_ctx,
-+		struct audio *audio)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.audio_count; i++) {
-+		if (res_ctx->pool.audios[i] == audio) {
-+			res_ctx->is_audio_acquired[i] = true;
-+		}
-+	}
-+}
-+
-+static struct audio *find_first_free_audio(struct resource_context *res_ctx)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.audio_count; i++) {
-+		if (res_ctx->is_audio_acquired[i] == false) {
-+			return res_ctx->pool.audios[i];
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static struct clock_source *find_first_free_pll(
-+		struct resource_context *res_ctx)
-+{
-+	if (res_ctx->clock_source_ref_count[DCE110_CLK_SRC_PLL0] == 0) {
-+		return res_ctx->pool.clock_sources[DCE110_CLK_SRC_PLL0];
-+	}
-+	if (res_ctx->clock_source_ref_count[DCE110_CLK_SRC_PLL1] == 0) {
-+		return res_ctx->pool.clock_sources[DCE110_CLK_SRC_PLL1];
-+	}
-+
-+	return 0;
-+}
-+
-+static bool check_timing_change(struct core_stream *cur_stream,
-+		struct core_stream *new_stream)
-+{
-+	if (cur_stream == NULL)
-+		return true;
-+
-+	/* If sink pointer changed, it means this is a hotplug, we should do
-+	 * full hw setting.
-+	 */
-+	if (cur_stream->sink != new_stream->sink)
-+		return true;
-+
-+	return !is_same_timing(
-+					&cur_stream->public.timing,
-+					&new_stream->public.timing);
-+}
-+
-+static enum dc_status map_resources(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j;
-+
-+	/* mark resources used for targets that are already active */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		if (context->target_flags[i].unchanged)
-+			for (j = 0; j < target->stream_count; j++) {
-+				struct core_stream *stream = target->streams[j];
-+				attach_stream_to_controller(
-+						&context->res_ctx,
-+						stream);
-+
-+				set_stream_engine_in_use(
-+						&context->res_ctx,
-+						stream->stream_enc);
-+
-+				reference_clock_source(
-+						&context->res_ctx,
-+						stream->clock_source);
-+
-+				if (stream->audio) {
-+					set_audio_in_use(&context->res_ctx,
-+							stream->audio);
-+				}
-+			}
-+	}
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+		for (j = 0; j < target->stream_count; j++) {
-+			struct core_stream *stream = target->streams[j];
-+			struct core_stream *curr_stream;
-+
-+			if (!assign_first_free_controller(
-+					&context->res_ctx, stream))
-+				return DC_NO_CONTROLLER_RESOURCE;
-+
-+			attach_stream_to_controller(&context->res_ctx, stream);
-+
-+			stream->stream_enc =
-+				find_first_free_match_stream_enc_for_link(
-+					&context->res_ctx,
-+					stream->sink->link);
-+
-+			if (!stream->stream_enc)
-+				return DC_NO_STREAM_ENG_RESOURCE;
-+
-+			set_stream_engine_in_use(
-+					&context->res_ctx,
-+					stream->stream_enc);
-+			stream->signal =
-+				stream->sink->public.sink_signal;
-+
-+			if (dc_is_dp_signal(stream->signal))
-+				stream->clock_source = context->res_ctx.
-+					pool.clock_sources[DCE110_CLK_SRC_EXT];
-+			else
-+				stream->clock_source =
-+					find_used_clk_src_for_sharing(
-+							context, stream);
-+			if (stream->clock_source == NULL)
-+				stream->clock_source =
-+					find_first_free_pll(&context->res_ctx);
-+
-+			if (stream->clock_source == NULL)
-+				return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+			reference_clock_source(
-+					&context->res_ctx,
-+					stream->clock_source);
-+
-+			/* TODO: Add check if ASIC support and EDID audio */
-+			if (!stream->sink->converter_disable_audio &&
-+						dc_is_audio_capable_signal(
-+						stream->signal)) {
-+				stream->audio = find_first_free_audio(
-+						&context->res_ctx);
-+
-+				if (!stream->audio)
-+					return DC_NO_STREAM_AUDIO_RESOURCE;
-+
-+				set_audio_in_use(&context->res_ctx,
-+						stream->audio);
-+			}
-+			curr_stream =
-+				dc->current_context.res_ctx.controller_ctx
-+				[stream->controller_idx].stream;
-+			context->res_ctx.controller_ctx[stream->controller_idx]
-+			.flags.timing_changed =
-+				check_timing_change(curr_stream, stream);
-+
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-+{
-+	switch (crtc_id) {
-+	case CONTROLLER_ID_D0:
-+		return DTO_SOURCE_ID0;
-+	case CONTROLLER_ID_D1:
-+		return DTO_SOURCE_ID1;
-+	case CONTROLLER_ID_D2:
-+		return DTO_SOURCE_ID2;
-+	case CONTROLLER_ID_D3:
-+		return DTO_SOURCE_ID3;
-+	case CONTROLLER_ID_D4:
-+		return DTO_SOURCE_ID4;
-+	case CONTROLLER_ID_D5:
-+		return DTO_SOURCE_ID5;
-+	default:
-+		return DTO_SOURCE_UNKNOWN;
-+	}
-+}
-+
-+static void build_audio_output(
-+	const struct core_stream *stream,
-+	struct audio_output *audio_output)
-+{
-+	audio_output->engine_id = stream->stream_enc->id;
-+
-+	audio_output->signal = stream->signal;
-+
-+	/* audio_crtc_info  */
-+
-+	audio_output->crtc_info.h_total =
-+		stream->public.timing.h_total;
-+
-+	/* Audio packets are sent during actual CRTC blank physical signal, we
-+	 * need to specify actual active signal portion */
-+	audio_output->crtc_info.h_active =
-+			stream->public.timing.h_addressable
-+			+ stream->public.timing.h_border_left
-+			+ stream->public.timing.h_border_right;
-+
-+	audio_output->crtc_info.v_active =
-+			stream->public.timing.v_addressable
-+			+ stream->public.timing.v_border_top
-+			+ stream->public.timing.v_border_bottom;
-+
-+	audio_output->crtc_info.pixel_repetition = 1;
-+
-+	audio_output->crtc_info.interlaced =
-+			stream->public.timing.flags.INTERLACE;
-+
-+	audio_output->crtc_info.refresh_rate =
-+		(stream->public.timing.pix_clk_khz*1000)/
-+		(stream->public.timing.h_total*stream->public.timing.v_total);
-+
-+	audio_output->crtc_info.color_depth =
-+		stream->public.timing.display_color_depth;
-+
-+	audio_output->crtc_info.requested_pixel_clock =
-+			stream->pix_clk_params.requested_pix_clk;
-+
-+	/* TODO - Investigate why calculated pixel clk has to be
-+	 * requested pixel clk */
-+	audio_output->crtc_info.calculated_pixel_clock =
-+			stream->pix_clk_params.requested_pix_clk;
-+
-+	/* TODO: This is needed for DP */
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
-+		audio_output->pll_info.dp_dto_source_clock_in_khz =
-+			dal_display_clock_get_dp_ref_clk_frequency(
-+				stream->dis_clk);
-+	}
-+
-+	audio_output->pll_info.feed_back_divider =
-+			stream->pll_settings.feedback_divider;
-+
-+	audio_output->pll_info.dto_source =
-+		translate_to_dto_source(
-+			stream->controller_idx + 1);
-+
-+	/* TODO hard code to enable for now. Need get from stream */
-+	audio_output->pll_info.ss_enabled = true;
-+
-+	audio_output->pll_info.ss_percentage =
-+			stream->pll_settings.ss_percentage;
-+}
-+
-+static void get_pixel_clock_parameters(
-+	const struct core_stream *stream,
-+	struct pixel_clk_params *pixel_clk_params)
-+{
-+	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
-+	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
-+	pixel_clk_params->signal_type = stream->sink->public.sink_signal;
-+	pixel_clk_params->controller_id = stream->controller_idx + 1;
-+	/* TODO: un-hardcode*/
-+	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+	pixel_clk_params->flags.ENABLE_SS = 0;
-+	pixel_clk_params->color_depth =
-+		stream->public.timing.display_color_depth;
-+	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-+}
-+
-+static enum dc_status build_stream_hw_param(struct core_stream *stream)
-+{
-+	/*TODO: unhardcode*/
-+	stream->max_tmds_clk_from_edid_in_mhz = 0;
-+	stream->max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	stream->max_hdmi_pixel_clock = 600000;
-+
-+	get_pixel_clock_parameters(stream, &stream->pix_clk_params);
-+	dal_clock_source_get_pix_clk_dividers(
-+		stream->clock_source,
-+		&stream->pix_clk_params,
-+		&stream->pll_settings);
-+
-+	build_audio_output(stream, &stream->audio_output);
-+
-+	return DC_OK;
-+}
-+
-+static enum dc_status validate_mapped_resource(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	enum dc_status status = DC_OK;
-+	uint8_t i, j;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+		for (j = 0; j < target->stream_count; j++) {
-+			struct core_stream *stream = target->streams[j];
-+			struct core_link *link = stream->sink->link;
-+			status = build_stream_hw_param(stream);
-+
-+			if (status != DC_OK)
-+				return status;
-+
-+			if (!dce110_timing_generator_validate_timing(
-+					stream->tg,
-+					&stream->public.timing,
-+					SIGNAL_TYPE_HDMI_TYPE_A))
-+				return DC_FAIL_CONTROLLER_VALIDATE;
-+
-+
-+			if (dce110_link_encoder_validate_output_with_stream(
-+					link->link_enc,
-+					stream)
-+							!= ENCODER_RESULT_OK)
-+				return DC_FAIL_ENC_VALIDATE;
-+
-+			/* TODO: validate audio ASIC caps, encoder */
-+
-+			status = dc_link_validate_mode_timing(stream->sink,
-+					link,
-+					&stream->public.timing);
-+
-+			if (status != DC_OK)
-+				return status;
-+
-+			build_info_frame(stream);
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce110_validate_bandwidth(
-+	const struct dc *dc,
-+	struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t number_of_displays = 0;
-+
-+	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		for (j = 0; j < target->stream_count; j++) {
-+			struct core_stream *stream = target->streams[j];
-+			struct bw_calcs_input_single_display *disp = &context->
-+				bw_mode_data.displays_data[number_of_displays];
-+
-+			if (target->status.surface_count == 0) {
-+				disp->graphics_scale_ratio = int_to_fixed(1);
-+				disp->graphics_h_taps = 4;
-+				disp->graphics_v_taps = 4;
-+
-+			} else {
-+				disp->graphics_scale_ratio =
-+					fixed31_32_to_bw_fixed(
-+						stream->ratios.vert.value);
-+				disp->graphics_h_taps = stream->taps.h_taps;
-+				disp->graphics_v_taps = stream->taps.v_taps;
-+			}
-+
-+			disp->graphics_src_width =
-+					stream->public.timing.h_addressable;
-+			disp->graphics_src_height =
-+					stream->public.timing.v_addressable;
-+			disp->h_total = stream->public.timing.h_total;
-+			disp->pixel_rate = frc_to_fixed(
-+				stream->public.timing.pix_clk_khz, 1000);
-+
-+			/*TODO: get from surface*/
-+			disp->graphics_bytes_per_pixel = 4;
-+			disp->graphics_tiling_mode = tiled;
-+
-+			/* DCE11 defaults*/
-+			disp->graphics_lb_bpc = 10;
-+			disp->graphics_interlace_mode = false;
-+			disp->fbc_enable = false;
-+			disp->lpt_enable = false;
-+			disp->graphics_stereo_mode = mono;
-+			disp->underlay_mode = ul_none;
-+
-+			number_of_displays++;
-+		}
-+	}
-+
-+	context->bw_mode_data.number_of_displays = number_of_displays;
-+	context->bw_mode_data.display_synchronization_enabled = false;
-+
-+	dal_logger_write(dc->ctx->logger,
-+		LOG_MAJOR_BWM,
-+		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-+		"%s: Start bandwidth calculations",
-+		__func__);
-+	if (true == bw_calcs(
-+					dc->ctx,
-+					&dc->bw_dceip,
-+					&dc->bw_vbios,
-+					&context->bw_mode_data,
-+					&context->bw_results))
-+		result =  DC_OK;
-+	else {
-+		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-+		dal_logger_write(dc->ctx->logger,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_MODE_VALIDATION,
-+			"%s: Bandwidth validation failed!",
-+			__func__);
-+	}
-+
-+
-+	dal_logger_write(dc->ctx->logger,
-+		LOG_MAJOR_BWM,
-+		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-+		"%s: Finish bandwidth calculations\n nbpMark: %d",
-+		__func__,
-+		context->bw_results.nbp_state_change_watermark[0].b_mark);
-+
-+	return result;
-+}
-+
-+static void set_target_unchanged(
-+		struct validate_context *context,
-+		uint8_t target_idx)
-+{
-+	uint8_t i;
-+	struct core_target *target = context->targets[target_idx];
-+	context->target_flags[target_idx].unchanged = true;
-+	for (i = 0; i < target->stream_count; i++) {
-+		uint8_t index = target->streams[i]->controller_idx;
-+		context->res_ctx.controller_ctx[index].flags.unchanged = true;
-+	}
-+}
-+
-+enum dc_status dce110_validate_with_context(
-+		const struct dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count,
-+		struct validate_context *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t i, j;
-+	struct dc_context *dc_ctx = dc->ctx;
-+
-+	for (i = 0; i < set_count; i++) {
-+		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+
-+		for (j = 0; j < dc->current_context.target_count; j++)
-+			if (dc->current_context.targets[j] == context->targets[i])
-+				set_target_unchanged(context, i);
-+
-+		if (!context->target_flags[i].unchanged)
-+			if (!logical_attach_surfaces_to_target(
-+							(struct dc_surface **)set[i].surfaces,
-+							set[i].surface_count,
-+							&context->targets[i]->public)) {
-+				DC_ERROR("Failed to attach surface to target!\n");
-+				return DC_FAIL_ATTACH_SURFACES;
-+			}
-+	}
-+
-+	context->target_count = set_count;
-+
-+	context->res_ctx.pool = dc->res_pool;
-+
-+	result = map_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = validate_mapped_resource(dc, context);
-+
-+	if (result == DC_OK)
-+		build_scaling_params_for_context(dc, context);
-+
-+	if (result == DC_OK)
-+		result = dce110_validate_bandwidth(dc, context);
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-new file mode 100644
-index 0000000..e113d11
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-@@ -0,0 +1,55 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE110_H__
-+#define __DC_RESOURCE_DCE110_H__
-+
-+#include "core_types.h"
-+
-+struct adapter_service;
-+struct dc;
-+struct resource_pool;
-+struct dc_validation_set;
-+
-+
-+bool dce110_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	struct dc *dc,
-+	struct resource_pool *pool);
-+
-+void dce110_destruct_resource_pool(struct resource_pool *pool);
-+
-+enum dc_status dce110_validate_with_context(
-+		const struct dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count,
-+		struct validate_context *context);
-+
-+enum dc_status dce110_validate_bandwidth(
-+		const struct dc *dc,
-+		struct validate_context *context);
-+
-+#endif /* __DC_RESOURCE_DCE110_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-new file mode 100644
-index 0000000..a9edf96
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -0,0 +1,1168 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "stream_encoder_types.h"
-+#include "dce110_stream_encoder.h"
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+static const uint32_t fe_engine_offsets[] = {
-+	mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+};
-+
-+#define VBI_LINE_0 0
-+#define DP_BLANK_MAX_RETRY 20
-+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
-+
-+#ifndef HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
-+	#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x2
-+	#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
-+#endif
-+
-+static void construct(
-+	struct stream_encoder *enc,
-+	struct stream_enc_init_data *init)
-+{
-+	enc->ctx = init->ctx;
-+	enc->id = init->stream_engine_id;
-+	enc->adapter_service = init->adapter_service;
-+}
-+
-+struct stream_encoder *dce110_stream_encoder_create(
-+	struct stream_enc_init_data *init)
-+{
-+	struct stream_encoder *enc =
-+		dc_service_alloc(init->ctx, sizeof(struct stream_encoder));
-+
-+	if (!enc)
-+		goto enc_create_fail;
-+
-+	construct(enc, init);
-+
-+	return enc;
-+
-+enc_create_fail:
-+	return NULL;
-+}
-+
-+void dce110_stream_encoder_destroy(struct stream_encoder **enc)
-+{
-+	dc_service_free((*enc)->ctx, *enc);
-+	*enc = NULL;
-+}
-+
-+static void stop_hdmi_info_packets(struct dc_context *ctx, uint32_t offset)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* stop generic packets 0 & 1 on HDMI */
-+	addr = mmHDMI_GENERIC_PACKET_CONTROL0 + offset;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_SEND);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* stop generic packets 2 & 3 on HDMI */
-+	addr = mmHDMI_GENERIC_PACKET_CONTROL1 + offset;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_SEND);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* stop AVI packet on HDMI */
-+	addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AVI_INFO_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AVI_INFO_CONT);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void stop_dp_info_packets(struct dc_context *ctx, int32_t offset)
-+{
-+	/* stop generic packets on DP */
-+
-+	const uint32_t addr = mmDP_SEC_CNTL + offset;
-+
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP1_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP2_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP3_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_AVI_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_MPG_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE);
-+
-+	/* this register shared with audio info frame.
-+	 * therefore we need to keep master enabled
-+	 * if at least one of the fields is not 0 */
-+
-+	if (value)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_stream_encoder_stop_info_packets(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	enum signal_type signal)
-+{
-+	if (dc_is_hdmi_signal(signal))
-+		stop_hdmi_info_packets(
-+			enc->ctx,
-+			fe_engine_offsets[engine]);
-+	else if (dc_is_dp_signal(signal))
-+		stop_dp_info_packets(
-+			enc->ctx,
-+			fe_engine_offsets[engine]);
-+}
-+
-+
-+static void update_avi_info_packet(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	enum signal_type signal,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	const int32_t offset = fe_engine_offsets[engine];
-+
-+	uint32_t regval;
-+	uint32_t addr;
-+
-+	if (info_packet->valid) {
-+		const uint32_t *content =
-+			(const uint32_t *) &info_packet->sb[0];
-+
-+		{
-+			regval = content[0];
-+
-+			dal_write_reg(
-+				enc->ctx,
-+				mmAFMT_AVI_INFO0 + offset,
-+				regval);
-+		}
-+		{
-+			regval = content[1];
-+
-+			dal_write_reg(
-+				enc->ctx,
-+				mmAFMT_AVI_INFO1 + offset,
-+				regval);
-+		}
-+		{
-+			regval = content[2];
-+
-+			dal_write_reg(
-+				enc->ctx,
-+				mmAFMT_AVI_INFO2 + offset,
-+				regval);
-+		}
-+		{
-+			regval = content[3];
-+
-+			/* move version to AVI_INFO3 */
-+			set_reg_field_value(
-+				regval,
-+				info_packet->hb1,
-+				AFMT_AVI_INFO3,
-+				AFMT_AVI_INFO_VERSION);
-+
-+			dal_write_reg(
-+				enc->ctx,
-+				mmAFMT_AVI_INFO3 + offset,
-+				regval);
-+		}
-+
-+		if (dc_is_hdmi_signal(signal)) {
-+
-+			uint32_t control0val;
-+			uint32_t control1val;
-+
-+			addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+
-+			control0val = dal_read_reg(enc->ctx, addr);
-+
-+			set_reg_field_value(
-+				control0val,
-+				1,
-+				HDMI_INFOFRAME_CONTROL0,
-+				HDMI_AVI_INFO_SEND);
-+
-+			set_reg_field_value(
-+				control0val,
-+				1,
-+				HDMI_INFOFRAME_CONTROL0,
-+				HDMI_AVI_INFO_CONT);
-+
-+			dal_write_reg(enc->ctx, addr, control0val);
-+
-+			addr = mmHDMI_INFOFRAME_CONTROL1 + offset;
-+
-+			control1val = dal_read_reg(enc->ctx, addr);
-+
-+			set_reg_field_value(
-+				control1val,
-+				VBI_LINE_0 + 2,
-+				HDMI_INFOFRAME_CONTROL1,
-+				HDMI_AVI_INFO_LINE);
-+
-+			dal_write_reg(enc->ctx, addr, control1val);
-+		}
-+	} else if (dc_is_hdmi_signal(signal)) {
-+		addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+
-+		regval = dal_read_reg(enc->ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			0,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_SEND);
-+
-+		set_reg_field_value(
-+			regval,
-+			0,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_CONT);
-+
-+		dal_write_reg(enc->ctx, addr, regval);
-+	}
-+}
-+
-+static void update_generic_info_packet(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	uint32_t addr;
-+	uint32_t regval;
-+	/* choose which generic packet to use */
-+	{
-+		addr = mmAFMT_VBI_PACKET_CONTROL + fe_engine_offsets[engine];
-+
-+		regval = dal_read_reg(enc->ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			packet_index,
-+			AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC_INDEX);
-+
-+		dal_write_reg(enc->ctx, addr, regval);
-+	}
-+
-+	/* write generic packet header
-+	 * (4th byte is for GENERIC0 only) */
-+	{
-+		addr = mmAFMT_GENERIC_HDR + fe_engine_offsets[engine];
-+
-+		regval = 0;
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb0,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB0);
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb1,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB1);
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb2,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB2);
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb3,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB3);
-+
-+		dal_write_reg(enc->ctx, addr, regval);
-+	}
-+
-+	/* write generic packet contents
-+	 * (we never use last 4 bytes)
-+	 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
-+	{
-+		const uint32_t *content =
-+			(const uint32_t *) &info_packet->sb[0];
-+
-+		uint32_t counter = 0;
-+
-+		addr = mmAFMT_GENERIC_0 + fe_engine_offsets[engine];
-+
-+		do {
-+			dal_write_reg(enc->ctx, addr++, *content++);
-+
-+			++counter;
-+		} while (counter < 7);
-+	}
-+
-+	dal_write_reg(
-+		enc->ctx,
-+		mmAFMT_GENERIC_7 + fe_engine_offsets[engine],
-+		0);
-+
-+	/* force double-buffered packet update */
-+	{
-+		addr = mmAFMT_VBI_PACKET_CONTROL + fe_engine_offsets[engine];
-+
-+		regval = dal_read_reg(enc->ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			(packet_index == 0),
-+			AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC0_UPDATE);
-+
-+		set_reg_field_value(
-+			regval,
-+			(packet_index == 2),
-+			AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC2_UPDATE);
-+
-+		dal_write_reg(enc->ctx, addr, regval);
-+	}
-+}
-+
-+static void update_hdmi_info_packet(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	uint32_t cont, send, line;
-+	uint32_t addr = fe_engine_offsets[engine];
-+	uint32_t regval;
-+
-+	if (info_packet->valid) {
-+		update_generic_info_packet(
-+			enc,
-+			engine,
-+			packet_index,
-+			info_packet);
-+
-+		/* enable transmission of packet(s) -
-+		 * packet transmission begins on the next frame */
-+		cont = 1;
-+		/* send packet(s) every frame */
-+		send = 1;
-+		/* select line number to send packets on */
-+		line = 2;
-+	} else {
-+		cont = 0;
-+		send = 0;
-+		line = 0;
-+	}
-+
-+	/* choose which generic packet control to use */
-+
-+	switch (packet_index) {
-+	case 0:
-+	case 1:
-+		addr += mmHDMI_GENERIC_PACKET_CONTROL0;
-+		break;
-+	case 2:
-+	case 3:
-+		addr += mmHDMI_GENERIC_PACKET_CONTROL1;
-+		break;
-+	default:
-+		/* invalid HW packet index */
-+		dal_logger_write(
-+			enc->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"Invalid HW packet index: %s()\n",
-+			__func__);
-+		break;
-+	}
-+
-+	regval = dal_read_reg(enc->ctx, addr);
-+
-+	switch (packet_index) {
-+	case 0:
-+	case 2:
-+		set_reg_field_value(
-+			regval,
-+			cont,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC0_CONT);
-+		set_reg_field_value(
-+			regval,
-+			send,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC0_SEND);
-+		set_reg_field_value(
-+			regval,
-+			line,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC0_LINE);
-+		break;
-+	case 1:
-+	case 3:
-+		set_reg_field_value(
-+			regval,
-+			cont,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC1_CONT);
-+		set_reg_field_value(
-+			regval,
-+			send,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC1_SEND);
-+		set_reg_field_value(
-+			regval,
-+			line,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC1_LINE);
-+		break;
-+	default:
-+		/* invalid HW packet index */
-+		dal_logger_write(
-+			enc->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"Invalid HW packet index: %s()\n",
-+			__func__);
-+		break;
-+	}
-+
-+	dal_write_reg(enc->ctx, addr, regval);
-+}
-+
-+static void update_dp_info_packet(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + fe_engine_offsets[engine];
-+
-+	uint32_t value;
-+
-+	if (info_packet->valid)
-+		update_generic_info_packet(
-+			enc,
-+			engine,
-+			packet_index,
-+			info_packet);
-+
-+	/* enable/disable transmission of packet(s).
-+	 * If enabled, packet transmission begins on the next frame */
-+
-+	value = dal_read_reg(enc->ctx, addr);
-+
-+	switch (packet_index) {
-+	case 0:
-+		set_reg_field_value(
-+			value,
-+			info_packet->valid,
-+			DP_SEC_CNTL,
-+			DP_SEC_GSP0_ENABLE);
-+		break;
-+	case 1:
-+		set_reg_field_value(
-+			value,
-+			info_packet->valid,
-+			DP_SEC_CNTL,
-+			DP_SEC_GSP1_ENABLE);
-+		break;
-+	case 2:
-+		set_reg_field_value(
-+			value,
-+			info_packet->valid,
-+			DP_SEC_CNTL,
-+			DP_SEC_GSP2_ENABLE);
-+		break;
-+	case 3:
-+		set_reg_field_value(
-+			value,
-+			info_packet->valid,
-+			DP_SEC_CNTL,
-+			DP_SEC_GSP3_ENABLE);
-+		break;
-+	default:
-+		/* invalid HW packet index */
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	/* This bit is the master enable bit.
-+	 * When enabling secondary stream engine,
-+	 * this master bit must also be set.
-+	 * This register shared with audio info frame.
-+	 * Therefore we need to enable master bit
-+	 * if at least on of the fields is not 0 */
-+
-+	if (value)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
-+void dce110_stream_encoder_update_info_packets(
-+	struct stream_encoder *enc,
-+	enum signal_type signal,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	if (dc_is_hdmi_signal(signal)) {
-+		update_avi_info_packet(
-+			enc,
-+			enc->id,
-+			signal,
-+			&info_frame->avi);
-+		update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor);
-+		update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut);
-+		update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd);
-+	} else if (dc_is_dp_signal(signal))
-+		update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc);
-+}
-+
-+static void dp_steer_fifo_reset(
-+	struct dc_context *ctx,
-+	enum engine_id engine,
-+	bool reset)
-+{
-+	const uint32_t addr = mmDP_STEER_FIFO + fe_engine_offsets[engine];
-+
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, reset, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+/*
-+ * @brief
-+ * Output blank data,
-+ * prevents output of the actual surface data on active transmitter
-+ */
-+enum encoder_result dce110_stream_encoder_blank(
-+				struct stream_encoder *enc,
-+				enum signal_type signal)
-+{
-+	enum engine_id engine = enc->id;
-+	const uint32_t addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	uint32_t retries = 0;
-+	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
-+
-+	if (!dc_is_dp_signal(signal))
-+		return ENCODER_RESULT_OK;
-+
-+	/* Note: For CZ, we are changing driver default to disable
-+	 * stream deferred to next VBLANK. If results are positive, we
-+	 * will make the same change to all DCE versions. There are a
-+	 * handful of panels that cannot handle disable stream at
-+	 * HBLANK and will result in a white line flash across the
-+	 * screen on stream disable. */
-+
-+	/* Specify the video stream disable point
-+	 * (2 = start of the next vertical blank) */
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DP_VID_STREAM_CNTL,
-+		DP_VID_STREAM_DIS_DEFER);
-+	/* Larger delay to wait until VBLANK - use max retry of
-+	 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
-+	 * a little more because we may not trust delay accuracy. */
-+	max_retries = DP_BLANK_MAX_RETRY * 150;
-+
-+	/* disable DP stream */
-+	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	/* the encoder stops sending the video stream
-+	 * at the start of the vertical blanking.
-+	 * Poll for DP_VID_STREAM_STATUS == 0 */
-+
-+	do {
-+		value = dal_read_reg(enc->ctx, addr);
-+
-+		if (!get_reg_field_value(
-+			value,
-+			DP_VID_STREAM_CNTL,
-+			DP_VID_STREAM_STATUS))
-+			break;
-+
-+		dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+		++retries;
-+	} while (retries < max_retries);
-+
-+	ASSERT(retries <= max_retries);
-+
-+	/* Tell the DP encoder to ignore timing from CRTC, must be done after
-+	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
-+	 * complete, stream status will be stuck in video stream enabled state,
-+	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
-+	dp_steer_fifo_reset(enc->ctx, engine, true);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+static void unblank_dp_output(
-+	struct stream_encoder *enc,
-+	enum engine_id engine)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* set DIG_START to 0x1 to resync FIFO */
-+	addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	/* switch DP encoder to CRTC data */
-+	dp_steer_fifo_reset(enc->ctx, engine, false);
-+
-+	/* wait 100us for DIG/DP logic to prime
-+	 * (i.e. a few video lines) */
-+	dc_service_delay_in_microseconds(enc->ctx, 100);
-+
-+	/* the hardware would start sending video at the start of the next DP
-+	 * frame (i.e. rising edge of the vblank).
-+	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
-+	 * register has no effect on enable transition! HW always guarantees
-+	 * VID_STREAM enable at start of next frame, and this is not
-+	 * programmable */
-+	addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		true,
-+		DP_VID_STREAM_CNTL,
-+		DP_VID_STREAM_ENABLE);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+}
-+
-+static void setup_vid_stream(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	uint32_t m_vid,
-+	uint32_t n_vid)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* enable auto measurement */
-+	addr = mmDP_VID_TIMING + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
-+	 * therefore program initial value for Mvid and Nvid */
-+	addr = mmDP_VID_N + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	addr = mmDP_VID_M + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	addr = mmDP_VID_TIMING + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+/*
-+ * @brief
-+ * Stop sending blank data,
-+ * output the actual surface data on active transmitter
-+ */
-+enum encoder_result dce110_stream_encoder_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param)
-+{
-+	bool is_dp_signal = param->signal == SIGNAL_TYPE_DISPLAY_PORT
-+		|| param->signal == SIGNAL_TYPE_DISPLAY_PORT_MST
-+		|| param->signal == SIGNAL_TYPE_EDP;
-+
-+	if (!is_dp_signal)
-+		return ENCODER_RESULT_OK;
-+
-+	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
-+		uint32_t n_vid = 0x8000;
-+		uint32_t m_vid;
-+
-+		/* M / N = Fstream / Flink
-+		 * m_vid / n_vid = pixel rate / link rate */
-+
-+		uint64_t m_vid_l = n_vid;
-+
-+		m_vid_l *= param->crtc_timing.pixel_clock;
-+		m_vid_l = div_u64(m_vid_l,
-+			param->link_settings.link_rate
-+				* LINK_RATE_REF_FREQ_IN_KHZ);
-+
-+		m_vid = (uint32_t) m_vid_l;
-+
-+		setup_vid_stream(enc,
-+			enc->id, m_vid, n_vid);
-+	}
-+
-+	unblank_dp_output(enc, enc->id);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+static void set_dp_stream_attributes(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	const struct dc_crtc_timing *timing)
-+{
-+	const uint32_t addr = mmDP_PIXEL_FORMAT + fe_engine_offsets[engine];
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+	/* set pixel encoding */
-+	switch (timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(
-+			value,
-+			DP_PIXEL_ENCODING_YCBCR422,
-+			DP_PIXEL_FORMAT,
-+			DP_PIXEL_ENCODING);
-+		break;
-+	case PIXEL_ENCODING_YCBCR444:
-+		set_reg_field_value(
-+			value,
-+			DP_PIXEL_ENCODING_YCBCR444,
-+			DP_PIXEL_FORMAT,
-+			DP_PIXEL_ENCODING);
-+
-+		if (timing->flags.Y_ONLY)
-+			if (timing->display_color_depth != COLOR_DEPTH_666)
-+				/* HW testing only, no use case yet.
-+				 * Color depth of Y-only could be
-+				 * 8, 10, 12, 16 bits */
-+				set_reg_field_value(
-+					value,
-+					DP_PIXEL_ENCODING_Y_ONLY,
-+					DP_PIXEL_FORMAT,
-+					DP_PIXEL_ENCODING);
-+		/* Note: DP_MSA_MISC1 bit 7 is the indicator
-+		 * of Y-only mode.
-+		 * This bit is set in HW if register
-+		 * DP_PIXEL_ENCODING is programmed to 0x4 */
-+		break;
-+	default:
-+		set_reg_field_value(
-+			value,
-+			DP_PIXEL_ENCODING_RGB444,
-+			DP_PIXEL_FORMAT,
-+			DP_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	/* set color depth */
-+
-+	switch (timing->display_color_depth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_8BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_10BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_12BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	default:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_6BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	}
-+
-+	/* set dynamic range and YCbCr range */
-+	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_DYN_RANGE);
-+	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_YCBCR_RANGE);
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
-+static void setup_hdmi(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t output_pixel_clock = timing->pix_clk_khz;
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmHDMI_CONTROL + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_PACKET_GEN_VERSION);
-+	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_KEEPOUT_MODE);
-+	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE);
-+	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN);
-+	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE);
-+
-+	switch (timing->display_color_depth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			0,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_ENABLE);
-+		output_pixel_clock = (timing->pix_clk_khz * 30) / 24;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			2,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_ENABLE);
-+		output_pixel_clock = (timing->pix_clk_khz * 36) / 24;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		set_reg_field_value(
-+			value,
-+			3,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_ENABLE);
-+		output_pixel_clock = (timing->pix_clk_khz * 48) / 24;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (output_pixel_clock >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
-+		/* enable HDMI data scrambler */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DATA_SCRAMBLE_EN);
-+
-+		/* HDMI_CLOCK_CHANNEL_RATE_MORE_340M
-+		 * Clock channel frequency is 1/4 of character rate.*/
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_CLOCK_CHANNEL_RATE);
-+	} else if (timing->flags.LTE_340MCSC_SCRAMBLE) {
-+
-+		/* TODO: New feature for DCE11, still need to implement */
-+
-+		/* enable HDMI data scrambler */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DATA_SCRAMBLE_EN);
-+
-+		/* HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
-+		 * Clock channel frequency is the same
-+		 * as character rate */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			HDMI_CONTROL,
-+			HDMI_CLOCK_CHANNEL_RATE);
-+	}
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	addr = mmHDMI_VBI_PACKET_CONTROL + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT);
-+	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND);
-+	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND);
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	/* following belongs to audio */
-+	addr = mmHDMI_INFOFRAME_CONTROL0 + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AUDIO_INFO_SEND);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	addr = mmAFMT_INFOFRAME_CONTROL0 + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		AFMT_INFOFRAME_CONTROL0,
-+		AFMT_AUDIO_INFO_UPDATE);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	addr = mmHDMI_INFOFRAME_CONTROL1 + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		VBI_LINE_0 + 2,
-+		HDMI_INFOFRAME_CONTROL1,
-+		HDMI_AUDIO_INFO_LINE);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	addr = mmHDMI_GC + fe_engine_offsets[engine];
-+	value = dal_read_reg(enc->ctx, addr);
-+	set_reg_field_value(value, 0, HDMI_GC, HDMI_GC_AVMUTE);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+}
-+
-+static void set_tmds_stream_attributes(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	enum signal_type signal,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+	switch (timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(value, 1, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	switch (timing->pixel_encoding) {
-+	case COLOR_DEPTH_101010:
-+		if ((signal == SIGNAL_TYPE_DVI_SINGLE_LINK
-+			|| signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-+			&& timing->pixel_encoding == PIXEL_ENCODING_RGB)
-+			set_reg_field_value(
-+				value,
-+				2,
-+				DIG_FE_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DIG_FE_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
-+		break;
-+	}
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
-+/*
-+ * @brief
-+ * Associate digital encoder with specified output transmitter
-+ * and configure to output signal.
-+ * Encoder will be activated later in enable_output()
-+ */
-+enum encoder_result dce110_stream_encoder_setup(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	enum signal_type signal,
-+	bool enable_audio)
-+{
-+	if (!dc_is_dp_signal(signal)) {
-+		struct bp_encoder_control cntl;
-+
-+		cntl.action = ENCODER_CONTROL_SETUP;
-+		cntl.engine_id = enc->id;
-+		cntl.signal = signal;
-+		cntl.enable_dp_audio = enable_audio;
-+		cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+		cntl.lanes_number = (signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+					LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+		cntl.color_depth = crtc_timing->display_color_depth;
-+
-+		if (dal_bios_parser_encoder_control(
-+			dal_adapter_service_get_bios_parser(
-+				enc->adapter_service),
-+			&cntl) != BP_RESULT_OK)
-+			return ENCODER_RESULT_ERROR;
-+	}
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		/* set signal format */
-+		set_tmds_stream_attributes(
-+			enc, enc->id, signal,
-+			crtc_timing);
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/* set signal format */
-+		set_tmds_stream_attributes(
-+			enc, enc->id, signal,
-+			crtc_timing);
-+		/* setup HDMI engine */
-+		setup_hdmi(
-+			enc, enc->id, crtc_timing);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* set signal format */
-+		set_dp_stream_attributes(enc, enc->id, crtc_timing);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return ENCODER_RESULT_OK;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-new file mode 100644
-index 0000000..d2c7b90
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_STREAM_ENCODER_DCE110_H__
-+#define __DC_STREAM_ENCODER_DCE110_H__
-+
-+struct stream_enc_init_data {
-+	enum engine_id stream_engine_id;
-+	struct adapter_service *adapter_service;
-+	struct dc_context *ctx;
-+};
-+
-+struct stream_encoder *dce110_stream_encoder_create(
-+	struct stream_enc_init_data *init);
-+
-+void dce110_stream_encoder_destroy(struct stream_encoder **enc);
-+
-+void dce110_stream_encoder_stop_info_packets(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	enum signal_type signal);
-+
-+void dce110_stream_encoder_update_info_packets(
-+	struct stream_encoder *enc,
-+	enum signal_type signal,
-+	const struct encoder_info_frame *info_frame);
-+
-+enum encoder_result dce110_stream_encoder_blank(
-+	struct stream_encoder *enc,
-+	enum signal_type signal);
-+
-+enum encoder_result dce110_stream_encoder_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param);
-+
-+enum encoder_result dce110_stream_encoder_setup(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	enum signal_type signal,
-+	bool enable_audio);
-+
-+#endif /* __DC_STREAM_ENCODER_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-new file mode 100644
-index 0000000..198ff28
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -0,0 +1,1878 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/adapter_service_interface.h"
-+#include "include/logger_interface.h"
-+#include "include/timing_generator_types.h"
-+#include "dce110_timing_generator.h"
-+
-+
-+enum tg_regs_idx {
-+	IDX_CRTC_UPDATE_LOCK,
-+	IDX_CRTC_MASTER_UPDATE_LOCK,
-+	IDX_CRTC_MASTER_UPDATE_MODE,
-+	IDX_CRTC_H_TOTAL,
-+	IDX_CRTC_V_TOTAL,
-+	IDX_CRTC_H_BLANK_START_END,
-+	IDX_CRTC_V_BLANK_START_END,
-+	IDX_CRTC_H_SYNC_A,
-+	IDX_CRTC_V_SYNC_A,
-+	IDX_CRTC_H_SYNC_A_CNTL,
-+	IDX_CRTC_V_SYNC_A_CNTL,
-+	IDX_CRTC_INTERLACE_CONTROL,
-+	IDX_CRTC_BLANK_CONTROL,
-+	IDX_PIPE_PG_STATUS,
-+
-+	IDX_CRTC_TEST_PATTERN_COLOR,
-+	IDX_CRTC_TEST_PATTERN_CONTROL,
-+	IDX_CRTC_TEST_PATTERN_PARAMETERS,
-+	IDX_CRTC_FLOW_CONTROL,
-+	IDX_CRTC_STATUS,
-+	IDX_CRTC_STATUS_POSITION,
-+	IDX_CRTC_STATUS_FRAME_COUNT,
-+	IDX_CRTC_STEREO_CONTROL,
-+	IDX_CRTC_STEREO_STATUS,
-+	IDX_CRTC_STEREO_FORCE_NEXT_EYE,
-+	IDX_CRTC_3D_STRUCTURE_CONTROL,
-+	IDX_CRTC_DOUBLE_BUFFER_CONTROL,
-+	IDX_CRTC_V_TOTAL_MIN,
-+	IDX_CRTC_V_TOTAL_MAX,
-+	IDX_CRTC_V_TOTAL_CONTROL,
-+	IDX_CRTC_NOM_VERT_POSITION,
-+	IDX_CRTC_STATIC_SCREEN_CONTROL,
-+	IDX_CRTC_TRIGB_CNTL,
-+	IDX_CRTC_FORCE_COUNT_CNTL,
-+	IDX_CRTC_GSL_CONTROL,
-+	IDX_CRTC_GSL_WINDOW,
-+
-+	IDX_CRTC_CONTROL,
-+	IDX_CRTC_START_LINE_CONTROL,
-+	IDX_CRTC_COUNT_CONTROL,
-+
-+	IDX_MODE_EXT_OVERSCAN_LEFT_RIGHT,
-+	IDX_MODE_EXT_OVERSCAN_TOP_BOTTOM,
-+	IDX_DCP_GSL_CONTROL,
-+	IDX_GRPH_UPDATE,
-+
-+	IDX_CRTC_VBI_END,
-+
-+	IDX_BLND_UNDERFLOW_INTERRUPT,
-+	IDX_CRTC_BLACK_COLOR,
-+	IDX_CRTC_OVERSCAN_COLOR,
-+	IDX_CRTC_BLANK_DATA_COLOR,
-+
-+	TG_REGS_IDX_SIZE
-+};
-+
-+enum black_color_format {
-+	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
-+	BLACK_COLOR_FORMAT_RGB_LIMITED,
-+	BLACK_COLOR_FORMAT_YUV_TV,
-+	BLACK_COLOR_FORMAT_YUV_CV,
-+	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
-+
-+	BLACK_COLOR_FORMAT_COUNT
-+};
-+
-+#define regs_for_controller(id)\
-+[CONTROLLER_ID_D ## id - 1] =\
-+{[IDX_CRTC_UPDATE_LOCK] = mmCRTC ## id ## _CRTC_UPDATE_LOCK,\
-+[IDX_CRTC_MASTER_UPDATE_LOCK] = mmCRTC ## id ## _CRTC_MASTER_UPDATE_LOCK,\
-+[IDX_CRTC_MASTER_UPDATE_MODE] = mmCRTC ## id ## _CRTC_MASTER_UPDATE_MODE,\
-+[IDX_CRTC_H_TOTAL] = mmCRTC ## id ## _CRTC_H_TOTAL,\
-+[IDX_CRTC_V_TOTAL] = mmCRTC ## id ## _CRTC_V_TOTAL,\
-+[IDX_CRTC_H_BLANK_START_END] = mmCRTC ## id ## _CRTC_H_BLANK_START_END,\
-+[IDX_CRTC_V_BLANK_START_END] = mmCRTC ## id ## _CRTC_V_BLANK_START_END,\
-+[IDX_CRTC_H_SYNC_A] = mmCRTC ## id ## _CRTC_H_SYNC_A,\
-+[IDX_CRTC_V_SYNC_A] = mmCRTC ## id ## _CRTC_V_SYNC_A,\
-+[IDX_CRTC_H_SYNC_A_CNTL] = mmCRTC ## id ## _CRTC_H_SYNC_A_CNTL,\
-+[IDX_CRTC_V_SYNC_A_CNTL] = mmCRTC ## id ## _CRTC_V_SYNC_A_CNTL,\
-+[IDX_CRTC_INTERLACE_CONTROL] = mmCRTC ## id ## _CRTC_INTERLACE_CONTROL,\
-+[IDX_CRTC_BLANK_CONTROL] = mmCRTC ## id ## _CRTC_BLANK_CONTROL,\
-+[IDX_PIPE_PG_STATUS] = mmPIPE ## id ## _PG_STATUS,\
-+[IDX_CRTC_TEST_PATTERN_COLOR] = mmCRTC ## id ## _CRTC_TEST_PATTERN_COLOR,\
-+[IDX_CRTC_TEST_PATTERN_CONTROL] = mmCRTC ## id ## _CRTC_TEST_PATTERN_CONTROL,\
-+[IDX_CRTC_TEST_PATTERN_PARAMETERS] =\
-+mmCRTC ## id ## _CRTC_TEST_PATTERN_PARAMETERS,\
-+[IDX_CRTC_FLOW_CONTROL] = mmCRTC ## id ## _CRTC_FLOW_CONTROL,\
-+[IDX_CRTC_STATUS] = mmCRTC ## id ## _CRTC_STATUS,\
-+[IDX_CRTC_STATUS_POSITION] = mmCRTC ## id ## _CRTC_STATUS_POSITION,\
-+[IDX_CRTC_STATUS_FRAME_COUNT] = mmCRTC ## id ## _CRTC_STATUS_FRAME_COUNT,\
-+[IDX_CRTC_STEREO_CONTROL] = mmCRTC ## id ## _CRTC_STEREO_CONTROL,\
-+[IDX_CRTC_STEREO_STATUS] = mmCRTC ## id ## _CRTC_STEREO_STATUS,\
-+[IDX_CRTC_STEREO_FORCE_NEXT_EYE] = \
-+mmCRTC ## id ## _CRTC_STEREO_FORCE_NEXT_EYE,\
-+[IDX_CRTC_3D_STRUCTURE_CONTROL] = mmCRTC ## id ## _CRTC_3D_STRUCTURE_CONTROL,\
-+[IDX_CRTC_DOUBLE_BUFFER_CONTROL] =\
-+mmCRTC ## id ## _CRTC_DOUBLE_BUFFER_CONTROL,\
-+[IDX_CRTC_V_TOTAL_MIN] = mmCRTC ## id ## _CRTC_V_TOTAL_MIN,\
-+[IDX_CRTC_V_TOTAL_MAX] = mmCRTC ## id ## _CRTC_V_TOTAL_MAX,\
-+[IDX_CRTC_V_TOTAL_CONTROL] = mmCRTC ## id ## _CRTC_V_TOTAL_CONTROL,\
-+[IDX_CRTC_NOM_VERT_POSITION] = mmCRTC ## id ## _CRTC_NOM_VERT_POSITION,\
-+[IDX_CRTC_STATIC_SCREEN_CONTROL] =\
-+mmCRTC ## id ## _CRTC_STATIC_SCREEN_CONTROL,\
-+[IDX_CRTC_TRIGB_CNTL] = mmCRTC ## id ## _CRTC_TRIGB_CNTL,\
-+[IDX_CRTC_FORCE_COUNT_CNTL] = mmCRTC ## id ## _CRTC_FORCE_COUNT_NOW_CNTL,\
-+[IDX_CRTC_GSL_CONTROL] = mmCRTC ## id ## _CRTC_GSL_CONTROL,\
-+[IDX_CRTC_GSL_WINDOW] = mmCRTC ## id ## _CRTC_GSL_WINDOW,\
-+[IDX_CRTC_CONTROL] = mmCRTC ## id ## _CRTC_CONTROL,\
-+[IDX_CRTC_START_LINE_CONTROL] = mmCRTC ## id ## _CRTC_START_LINE_CONTROL,\
-+[IDX_CRTC_COUNT_CONTROL] = mmCRTC ## id ## _CRTC_COUNT_CONTROL,\
-+[IDX_MODE_EXT_OVERSCAN_LEFT_RIGHT] = mmSCL ## id ## _EXT_OVERSCAN_LEFT_RIGHT,\
-+[IDX_MODE_EXT_OVERSCAN_TOP_BOTTOM] = mmSCL ## id ## _EXT_OVERSCAN_TOP_BOTTOM,\
-+[IDX_DCP_GSL_CONTROL] = mmDCP ## id ## _DCP_GSL_CONTROL,\
-+[IDX_GRPH_UPDATE] = mmDCP ## id ## _GRPH_UPDATE,\
-+[IDX_CRTC_VBI_END] = mmCRTC ## id ## _CRTC_VBI_END,\
-+[IDX_BLND_UNDERFLOW_INTERRUPT] = mmBLND ## id ## _BLND_UNDERFLOW_INTERRUPT,\
-+[IDX_CRTC_BLACK_COLOR] = mmCRTC ## id ## _CRTC_BLACK_COLOR,\
-+[IDX_CRTC_OVERSCAN_COLOR] = mmCRTC ## id ## _CRTC_OVERSCAN_COLOR,\
-+[IDX_CRTC_BLANK_DATA_COLOR] = mmCRTC ## id ## _CRTC_BLANK_DATA_COLOR,\
-+}
-+
-+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
-+
-+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
-+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
-+
-+
-+#define FROM_TIMING_GENERATOR(tg)\
-+	container_of(tg, struct dce110_timing_generator, base)
-+
-+static uint32_t tg_regs[][TG_REGS_IDX_SIZE] = {
-+	regs_for_controller(0),
-+	regs_for_controller(1),
-+	regs_for_controller(2),
-+};
-+
-+/*******************************************************************************
-+ * GSL Sync related values */
-+
-+/* In VSync mode, after 4 units of time, master pipe will generate
-+ * flip_ready signal */
-+#define VFLIP_READY_DELAY 4
-+/* In HSync mode, after 2 units of time, master pipe will generate
-+ * flip_ready signal */
-+#define HFLIP_READY_DELAY 2
-+/* 6 lines delay between forcing flip and checking all pipes ready */
-+#define HFLIP_CHECK_DELAY 6
-+/* 3 lines before end of frame */
-+#define FLIP_READY_BACK_LOOKUP 3
-+
-+/* Trigger Source Select - ASIC-dependant, actual values for the
-+ * register programming */
-+enum trigger_source_select {
-+	TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0,
-+	TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1,
-+	TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2,
-+	TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3,
-+	TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4,
-+	TRIGGER_SOURCE_SELECT_GENERICF = 5,
-+	TRIGGER_SOURCE_SELECT_GENERICE = 6,
-+	TRIGGER_SOURCE_SELECT_VSYNCA = 7,
-+	TRIGGER_SOURCE_SELECT_HSYNCA = 8,
-+	TRIGGER_SOURCE_SELECT_VSYNCB = 9,
-+	TRIGGER_SOURCE_SELECT_HSYNCB = 10,
-+	TRIGGER_SOURCE_SELECT_HPD1 = 11,
-+	TRIGGER_SOURCE_SELECT_HPD2 = 12,
-+	TRIGGER_SOURCE_SELECT_GENERICD = 13,
-+	TRIGGER_SOURCE_SELECT_GENERICC = 14,
-+	TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15,
-+	TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16,
-+	TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17,
-+	TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18,
-+	TRIGGER_SOURCE_SELECT_BLONY = 19,
-+	TRIGGER_SOURCE_SELECT_GENERICA = 20,
-+	TRIGGER_SOURCE_SELECT_GENERICB = 21,
-+	TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22,
-+	TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23
-+};
-+
-+/* Trigger Source Select - ASIC-dependant, actual values for the
-+ * register programming */
-+enum trigger_polarity_select {
-+	TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0,
-+	TRIGGER_POLARITY_SELECT_CRTC = 1,
-+	TRIGGER_POLARITY_SELECT_GENERICA = 2,
-+	TRIGGER_POLARITY_SELECT_GENERICB = 3,
-+	TRIGGER_POLARITY_SELECT_HSYNCA = 4,
-+	TRIGGER_POLARITY_SELECT_HSYNCB = 5,
-+	TRIGGER_POLARITY_SELECT_VIDEO_CAPTURE = 6,
-+	TRIGGER_POLARITY_SELECT_GENERICC = 7
-+};
-+
-+/******************************************************************************/
-+
-+bool dce110_timing_generator_construct(
-+		struct timing_generator *tg,
-+		enum controller_id id)
-+{
-+	tg->controller_id = id;
-+	return true;
-+}
-+
-+static const struct crtc_black_color black_color_format[] = {
-+	/* BlackColorFormat_RGB_FullRange */
-+	{0, 0, 0},
-+	/* BlackColorFormat_RGB_Limited */
-+	{CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_RGB_LIMITED_RANGE,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_RGB_LIMITED_RANGE,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_RGB_LIMITED_RANGE},
-+	/* BlackColorFormat_YUV_TV */
-+	{CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4TV,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4TV,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4TV},
-+	/* BlackColorFormat_YUV_CV */
-+	{CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4CV,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4CV},
-+	/* BlackColorFormat_YUV_SuperAA */
-+	{CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4SUPERAA,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4SUPERAA,
-+		CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA}
-+};
-+
-+void dce110_timing_generator_color_space_to_black_color(
-+		enum color_space colorspace,
-+	struct crtc_black_color *black_color)
-+{
-+	switch (colorspace) {
-+	case COLOR_SPACE_YPBPR601:
-+		*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_TV];
-+		break;
-+
-+	case COLOR_SPACE_YPBPR709:
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+		*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
-+		break;
-+
-+	case COLOR_SPACE_N_MVPU_SUPER_AA:
-+		/* In crossfire SuperAA mode, the slave overscan data is forced
-+		 * to 0 in the pixel mixer on the master.  As a result, we need
-+		 * to adjust the blank color so that after blending the
-+		 * master+slave, it will appear black
-+		 */
-+		*black_color =
-+			black_color_format[BLACK_COLOR_FORMAT_YUV_SUPER_AA];
-+		break;
-+
-+	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		*black_color =
-+			black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
-+		break;
-+
-+	default:
-+		/* fefault is sRGB black (full range). */
-+		*black_color =
-+			black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
-+		/* default is sRGB black 0. */
-+		break;
-+	}
-+}
-+
-+/**
-+* apply_front_porch_workaround
-+*
-+* This is a workaround for a bug that has existed since R5xx and has not been
-+* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
-+*/
-+void dce110_timing_generator_apply_front_porch_workaround(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *timing)
-+{
-+	if (timing->flags.INTERLACE == 1) {
-+		if (timing->v_front_porch < 2)
-+			timing->v_front_porch = 2;
-+	} else {
-+		if (timing->v_front_porch < 1)
-+			timing->v_front_porch = 1;
-+	}
-+}
-+
-+int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
-+	const struct dc_crtc_timing *timing)
-+{
-+	return timing->v_sync_width + timing->v_front_porch;
-+}
-+
-+
-+void dce110_timing_generator_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl)
-+{
-+	uint32_t regval;
-+	uint32_t address = tg->regs[IDX_CRTC_CONTROL];
-+
-+	regval = dal_read_reg(tg->ctx, address);
-+	set_reg_field_value(regval, early_cntl,
-+			CRTC_CONTROL, CRTC_HBLANK_EARLY_CONTROL);
-+	dal_write_reg(tg->ctx, address, regval);
-+}
-+
-+/**
-+ * Enable CRTC
-+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
-+ */
-+bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
-+{
-+	enum bp_result result;
-+
-+	/* 0 value is needed by DRR and is also suggested default value for CZ
-+	 */
-+	uint32_t value;
-+
-+	value = dal_read_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_MASTER_UPDATE_MODE]);
-+	set_reg_field_value(value, 3,
-+			CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
-+	dal_write_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_MASTER_UPDATE_MODE], value);
-+
-+	result = dal_bios_parser_enable_crtc(tg->bp, tg->controller_id, true);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+void dce110_timing_generator_program_blank_color(
-+		struct timing_generator *tg,
-+		enum color_space color_space)
-+{
-+	struct crtc_black_color black_color;
-+	uint32_t addr = tg->regs[IDX_CRTC_BLACK_COLOR];
-+	uint32_t value = dal_read_reg(tg->ctx, addr);
-+
-+	dce110_timing_generator_color_space_to_black_color(
-+		color_space,
-+		&black_color);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color.black_color_b_cb,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color.black_color_g_y,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color.black_color_r_cr,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dal_write_reg(tg->ctx, addr, value);
-+}
-+
-+/**
-+ * blank_crtc
-+ * Call ASIC Control Object to Blank CRTC.
-+ */
-+
-+bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
-+{
-+	uint32_t addr = tg->regs[IDX_CRTC_BLANK_CONTROL];
-+	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint8_t counter = 100;
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_BLANK_CONTROL,
-+		CRTC_BLANK_DE_MODE);
-+
-+	dal_write_reg(tg->ctx, addr, value);
-+
-+	while (counter > 0) {
-+		value = dal_read_reg(tg->ctx, addr);
-+
-+		if (get_reg_field_value(
-+			value,
-+			CRTC_BLANK_CONTROL,
-+			CRTC_BLANK_DATA_EN) == 1 &&
-+			get_reg_field_value(
-+			value,
-+			CRTC_BLANK_CONTROL,
-+			CRTC_CURRENT_BLANK_STATE) == 1)
-+			break;
-+
-+		dc_service_sleep_in_milliseconds(tg->ctx, 1);
-+		counter--;
-+	}
-+
-+	if (!counter) {
-+		dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"timing generator %d blank timing out.\n",
-+				tg->controller_id);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ * unblank_crtc
-+ * Call ASIC Control Object to UnBlank CRTC.
-+ */
-+bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
-+{
-+	uint32_t addr = tg->regs[IDX_CRTC_BLANK_CONTROL];
-+	uint32_t value = dal_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTC_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTC_BLANK_CONTROL,
-+		CRTC_BLANK_DE_MODE);
-+
-+	dal_write_reg(tg->ctx, addr, value);
-+
-+	return true;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: is_in_vertical_blank
-+ *
-+ *  @brief
-+ *     check the current status of CRTC to check if we are in Vertical Blank
-+ *     regioneased" state
-+ *
-+ *  @return
-+ *     true if currently in blank region, false otherwise
-+ *
-+ *****************************************************************************
-+ */
-+bool dce110_timing_generator_is_in_vertical_blank(struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	addr = tg->regs[IDX_CRTC_STATUS];
-+	value = dal_read_reg(tg->ctx, addr);
-+	field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
-+	return field == 1;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: disable_stereo
-+ *
-+ *  @brief
-+ *     Disables active stereo on controller
-+ *     Frame Packing need to be disabled in vBlank or when CRTC not running
-+ *****************************************************************************
-+ */
-+#if 0
-+@TODOSTEREO
-+static void disable_stereo(struct timing_generator *tg)
-+{
-+	uint32_t addr = tg->regs[IDX_CRTC_3D_STRUCTURE_CONTROL];
-+	uint32_t value = 0;
-+	uint32_t test = 0;
-+	uint32_t field = 0;
-+	uint32_t struc_en = 0;
-+	uint32_t struc_stereo_sel_ovr = 0;
-+
-+	value = dal_read_reg(tg->ctx, addr);
-+	struc_en = get_reg_field_value(
-+			value,
-+			CRTC_3D_STRUCTURE_CONTROL,
-+			CRTC_3D_STRUCTURE_EN);
-+
-+	struc_stereo_sel_ovr = get_reg_field_value(
-+			value,
-+			CRTC_3D_STRUCTURE_CONTROL,
-+			CRTC_3D_STRUCTURE_STEREO_SEL_OVR);
-+
-+	/*
-+	 * When disabling Frame Packing in 2 step mode, we need to program both
-+	 * registers at the same frame
-+	 * Programming it in the beginning of VActive makes sure we are ok
-+	 */
-+
-+	if (struc_en != 0 && struc_stereo_sel_ovr == 0) {
-+		tg->funcs->wait_for_vblank(tg);
-+		tg->funcs->wait_for_vactive(tg);
-+	}
-+
-+	value = 0;
-+	dal_write_reg(tg->ctx, addr, value);
-+
-+
-+	addr = tg->regs[IDX_CRTC_STEREO_CONTROL];
-+	dal_write_reg(tg->ctx, addr, value);
-+}
-+#endif
-+
-+/**
-+ * disable_crtc - call ASIC Control Object to disable Timing generator.
-+ */
-+bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
-+{
-+	enum bp_result result;
-+
-+	result = dal_bios_parser_enable_crtc(tg->bp, tg->controller_id, false);
-+
-+	/* Need to make sure stereo is disabled according to the DCE5.0 spec */
-+
-+	/*
-+	 * @TODOSTEREO call this when adding stereo support
-+	 * tg->funcs->disable_stereo(tg);
-+	 */
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+/**
-+* program_horz_count_by_2
-+* Programs DxCRTC_HORZ_COUNT_BY2_EN - 1 for DVI 30bpp mode, 0 otherwise
-+*
-+*/
-+static void program_horz_count_by_2(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t regval;
-+
-+	regval = dal_read_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_COUNT_CONTROL]);
-+
-+	set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,
-+			CRTC_HORZ_COUNT_BY2_EN);
-+
-+	if (timing->flags.HORZ_COUNT_BY_TWO)
-+		set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL,
-+					CRTC_HORZ_COUNT_BY2_EN);
-+
-+	dal_write_reg(tg->ctx,
-+		tg->regs[IDX_CRTC_COUNT_CONTROL], regval);
-+}
-+
-+/**
-+ * program_timing_generator
-+ * Program CRTC Timing Registers - DxCRTC_H_*, DxCRTC_V_*, Pixel repetition.
-+ * Call ASIC Control Object to program Timings.
-+ */
-+bool dce110_timing_generator_program_timing_generator(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *dc_crtc_timing)
-+{
-+	enum bp_result result;
-+	struct bp_hw_crtc_timing_parameters bp_params;
-+	uint32_t regval;
-+
-+	uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +
-+			dc_crtc_timing->v_front_porch;
-+	uint32_t v_sync_start =dc_crtc_timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = dc_crtc_timing->h_border_right +
-+			dc_crtc_timing->h_front_porch;
-+	uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;
-+
-+	dc_service_memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
-+
-+	/* Due to an asic bug we need to apply the Front Porch workaround prior
-+	 * to programming the timing.
-+	 */
-+	dce110_timing_generator_apply_front_porch_workaround(tg, dc_crtc_timing);
-+
-+	bp_params.controller_id = tg->controller_id;
-+
-+	bp_params.h_total = dc_crtc_timing->h_total;
-+	bp_params.h_addressable =
-+		dc_crtc_timing->h_addressable;
-+	bp_params.v_total = dc_crtc_timing->v_total;
-+	bp_params.v_addressable = dc_crtc_timing->v_addressable;
-+
-+	bp_params.h_sync_start = h_sync_start;
-+	bp_params.h_sync_width = dc_crtc_timing->h_sync_width;
-+	bp_params.v_sync_start = v_sync_start;
-+	bp_params.v_sync_width = dc_crtc_timing->v_sync_width;
-+
-+	/* Set overscan */
-+	bp_params.h_overscan_left =
-+		dc_crtc_timing->h_border_left;
-+	bp_params.h_overscan_right =
-+		dc_crtc_timing->h_border_right;
-+	bp_params.v_overscan_top = dc_crtc_timing->v_border_top;
-+	bp_params.v_overscan_bottom =
-+		dc_crtc_timing->v_border_bottom;
-+
-+	/* Set flags */
-+	if (dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY == 1)
-+		bp_params.flags.HSYNC_POSITIVE_POLARITY = 1;
-+
-+	if (dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY == 1)
-+		bp_params.flags.VSYNC_POSITIVE_POLARITY = 1;
-+
-+	if (dc_crtc_timing->flags.INTERLACE == 1)
-+		bp_params.flags.INTERLACE = 1;
-+
-+	if (dc_crtc_timing->flags.HORZ_COUNT_BY_TWO == 1)
-+		bp_params.flags.HORZ_COUNT_BY_TWO = 1;
-+
-+	result = dal_bios_parser_program_crtc_timing(tg->bp, &bp_params);
-+
-+	program_horz_count_by_2(tg, dc_crtc_timing);
-+
-+
-+	regval = dal_read_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_START_LINE_CONTROL]);
-+
-+	if (dce110_timing_generator_get_vsynch_and_front_porch_size(dc_crtc_timing) <= 3) {
-+		set_reg_field_value(regval, 3,
-+				CRTC_START_LINE_CONTROL,
-+				CRTC_ADVANCED_START_LINE_POSITION);
-+
-+		set_reg_field_value(regval, 0,
-+				CRTC_START_LINE_CONTROL,
-+				CRTC_PREFETCH_EN);
-+	} else {
-+		set_reg_field_value(regval, 4,
-+				CRTC_START_LINE_CONTROL,
-+				CRTC_ADVANCED_START_LINE_POSITION);
-+
-+		set_reg_field_value(regval, 1,
-+				CRTC_START_LINE_CONTROL,
-+				CRTC_PREFETCH_EN);
-+	}
-+	dal_write_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_START_LINE_CONTROL], regval);
-+
-+	/* Enable stereo - only when we need to pack 3D frame. Other types
-+	 * of stereo handled in explicit call */
-+
-+	/* TODOSTEREO
-+	if (hw_crtc_timing->flags.PACK_3D_FRAME) {
-+		struct crtc_stereo_parameters stereo_params = { false };
-+		stereo_params.PROGRAM_STEREO = true;
-+		stereo_params.PROGRAM_POLARITY = true;
-+		stereo_params.FRAME_PACKED = true;
-+		stereo_params.RIGHT_EYE_POLARITY =
-+			hw_crtc_timing->flags.RIGHT_EYE_3D_POLARITY;
-+		tg->funcs->enable_stereo(tg, &stereo_params);
-+	}*/
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: program_drr
-+ *
-+ *  @brief
-+ *     Program dynamic refresh rate registers m_DxCRTC_V_TOTAL_*.
-+ *
-+ *  @param [in] pHwCrtcTiming: point to H
-+ *  wCrtcTiming struct
-+ *****************************************************************************
-+ */
-+void dce110_timing_generator_program_drr(
-+	struct timing_generator *tg,
-+	const struct hw_ranged_timing *timing)
-+{
-+	/* register values */
-+	uint32_t v_total_min = 0;
-+	uint32_t v_total_max = 0;
-+	uint32_t v_total_cntl = 0;
-+	uint32_t static_screen_cntl = 0;
-+
-+	uint32_t addr = 0;
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL_MIN];
-+	v_total_min = dal_read_reg(tg->ctx, addr);
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL_MAX];
-+	v_total_max = dal_read_reg(tg->ctx, addr);
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL_CONTROL];
-+	v_total_cntl = dal_read_reg(tg->ctx, addr);
-+
-+	addr = tg->regs[IDX_CRTC_STATIC_SCREEN_CONTROL];
-+	static_screen_cntl = dal_read_reg(tg->ctx, addr);
-+
-+	if (timing != NULL) {
-+		/* Set Static Screen trigger events
-+		 * If CRTC_SET_V_TOTAL_MIN_MASK_EN is set, use legacy event mask
-+		 * register
-+		 */
-+		if (get_reg_field_value(
-+			v_total_cntl,
-+			CRTC_V_TOTAL_CONTROL,
-+			CRTC_SET_V_TOTAL_MIN_MASK_EN)) {
-+			set_reg_field_value(v_total_cntl,
-+				/* TODO: add implementation
-+				translate_to_dce_static_screen_events(
-+					timing->control.event_mask.u_all),
-+					*/ 0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_SET_V_TOTAL_MIN_MASK);
-+		} else {
-+			set_reg_field_value(static_screen_cntl,
-+				/* TODO: add implementation
-+				translate_to_dce_static_screen_events(
-+					timing->control.event_mask.u_all),
-+					*/ 0,
-+				CRTC_STATIC_SCREEN_CONTROL,
-+				CRTC_STATIC_SCREEN_EVENT_MASK);
-+		}
-+
-+		/* Number of consecutive static screen frames before interrupt
-+		 * is triggered. 0 is an invalid setting, which means we should
-+		 * leaving HW setting unchanged. */
-+		if (timing->control.static_frame_count != 0) {
-+			set_reg_field_value(
-+				static_screen_cntl,
-+				timing->control.static_frame_count,
-+				CRTC_STATIC_SCREEN_CONTROL,
-+				CRTC_STATIC_SCREEN_FRAME_COUNT);
-+		}
-+
-+		/* This value is reduced by 1 based on the register definition
-+		 * of the VTOTAL value:
-+		 * CRTC_V_TOTAL should be set to Vertical total minus one. (E.g.
-+		 * for 525 lines, set to 524 = 0x20C)
-+		 */
-+		set_reg_field_value(v_total_min,
-+				timing->vertical_total_min,
-+				CRTC_V_TOTAL_MIN,
-+				CRTC_V_TOTAL_MIN);
-+		set_reg_field_value(v_total_max,
-+				timing->vertical_total_max,
-+				CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX);
-+
-+		/* set VTotalControl value according to ranged timing control.
-+		 */
-+
-+		if (timing->vertical_total_min != 0) {
-+			set_reg_field_value(v_total_cntl,
-+					1,
-+					CRTC_V_TOTAL_CONTROL,
-+					CRTC_V_TOTAL_MIN_SEL);
-+		} else {
-+			set_reg_field_value(v_total_cntl,
-+					0,
-+					CRTC_V_TOTAL_CONTROL,
-+					CRTC_V_TOTAL_MIN_SEL);
-+		}
-+		if (timing->vertical_total_max != 0) {
-+			set_reg_field_value(v_total_cntl,
-+					1,
-+					CRTC_V_TOTAL_CONTROL,
-+					CRTC_V_TOTAL_MAX_SEL);
-+		} else {
-+			set_reg_field_value(v_total_cntl,
-+					0,
-+					CRTC_V_TOTAL_CONTROL,
-+					CRTC_V_TOTAL_MAX_SEL);
-+		}
-+		set_reg_field_value(v_total_cntl,
-+				timing->control.force_lock_on_event,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_ON_EVENT);
-+		set_reg_field_value(v_total_cntl,
-+				timing->control.lock_to_master_vsync,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_TO_MASTER_VSYNC);
-+	} else {
-+		set_reg_field_value(v_total_cntl,
-+			0,
-+			CRTC_V_TOTAL_CONTROL,
-+			CRTC_SET_V_TOTAL_MIN_MASK);
-+		set_reg_field_value(static_screen_cntl,
-+			0,
-+			CRTC_STATIC_SCREEN_CONTROL,
-+			CRTC_STATIC_SCREEN_EVENT_MASK);
-+		set_reg_field_value(v_total_min,
-+				0,
-+				CRTC_V_TOTAL_MIN,
-+				CRTC_V_TOTAL_MIN);
-+		set_reg_field_value(v_total_max,
-+				0,
-+				CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MIN_SEL);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MAX_SEL);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_ON_EVENT);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_TO_MASTER_VSYNC);
-+	}
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL_MIN];
-+	dal_write_reg(tg->ctx, addr, v_total_min);
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL_MAX];
-+	dal_write_reg(tg->ctx, addr, v_total_max);
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL_CONTROL];
-+	dal_write_reg(tg->ctx, addr, v_total_cntl);
-+
-+	addr = tg->regs[IDX_CRTC_STATIC_SCREEN_CONTROL];
-+	dal_write_reg(tg->ctx, addr, static_screen_cntl);
-+}
-+
-+/*
-+ * get_vblank_counter
-+ *
-+ * @brief
-+ * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
-+ * holds the counter of frames.
-+ *
-+ * @param
-+ * struct timing_generator *tg - [in] timing generator which controls the
-+ * desired CRTC
-+ *
-+ * @return
-+ * Counter of frames, which should equal to number of vblanks.
-+ */
-+uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)
-+{
-+	uint32_t addr = tg->regs[IDX_CRTC_STATUS_FRAME_COUNT];
-+	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t field = get_reg_field_value(
-+			value, CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
-+
-+	return field;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dce110_get_crtc_positions
-+ *
-+ *  @brief
-+ *     Returns CRTC vertical/horizontal counters
-+ *
-+ *  @param [out] v_position, h_position
-+ *****************************************************************************
-+ */
-+
-+void dce110_timing_generator_get_crtc_positions(
-+	struct timing_generator *tg,
-+	int32_t *h_position,
-+	int32_t *v_position)
-+{
-+	uint32_t value;
-+
-+	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_STATUS_POSITION]);
-+
-+	*h_position = get_reg_field_value(
-+			value,
-+			CRTC_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	*v_position = get_reg_field_value(
-+			value,
-+			CRTC_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: get_crtc_scanoutpos
-+ *
-+ *  @brief
-+ *     Returns CRTC vertical/horizontal counters
-+ *
-+ *  @param [out] vpos, hpos
-+ *****************************************************************************
-+ */
-+uint32_t dce110_timing_generator_get_crtc_scanoutpos(
-+	struct timing_generator *tg,
-+	int32_t *vbl,
-+	int32_t *position)
-+{
-+	/* TODO 1: Update the implementation once caller is updated
-+	 * WARNING!! This function is returning the whole register value
-+	 * because the caller is expecting it instead of proper vertical and
-+	 * horizontal position. This should be a temporary implementation
-+	 * until the caller is updated. */
-+
-+	/* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */
-+
-+	*vbl = dal_read_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_V_BLANK_START_END]);
-+
-+	*position = dal_read_reg(tg->ctx,
-+			tg->regs[IDX_CRTC_STATUS_POSITION]);
-+
-+	/* @TODO: return value should indicate if current
-+	 * crtc is inside vblank*/
-+	return 0;
-+}
-+
-+/* TODO: is it safe to assume that mask/shift of Primary and Underlay
-+ * are the same?
-+ * For example: today CRTC_H_TOTAL == CRTCV_H_TOTAL but is it always
-+ * guaranteed? */
-+void dce110_timing_generator_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t vsync_offset = timing->v_border_bottom +
-+			timing->v_front_porch;
-+	uint32_t v_sync_start =timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+	uint32_t tmp = 0;
-+
-+	addr = tg->regs[IDX_CRTC_H_TOTAL];
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->h_total - 1,
-+		CRTC_H_TOTAL,
-+		CRTC_H_TOTAL);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = tg->regs[IDX_CRTC_V_TOTAL];
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->v_total - 1,
-+		CRTC_V_TOTAL,
-+		CRTC_V_TOTAL);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = tg->regs[IDX_CRTC_H_BLANK_START_END];
-+	value = dal_read_reg(ctx, addr);
-+
-+	tmp = timing->h_total -
-+		(h_sync_start + timing->h_border_left);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_H_BLANK_START_END,
-+		CRTC_H_BLANK_END);
-+
-+	tmp = tmp + timing->h_addressable +
-+		timing->h_border_left + timing->h_border_right;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_H_BLANK_START_END,
-+		CRTC_H_BLANK_START);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = tg->regs[IDX_CRTC_V_BLANK_START_END];
-+	value = dal_read_reg(ctx, addr);
-+
-+	tmp = timing->v_total - (v_sync_start + timing->v_border_top);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_V_BLANK_START_END,
-+		CRTC_V_BLANK_END);
-+
-+	tmp = tmp + timing->v_addressable + timing->v_border_top +
-+		timing->v_border_bottom;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_V_BLANK_START_END,
-+		CRTC_V_BLANK_START);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_timing_generator_set_test_pattern(
-+	struct timing_generator *tg,
-+	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-+	 * because this is not DP-specific (which is probably somewhere in DP
-+	 * encoder) */
-+	enum controller_dp_test_pattern test_pattern,
-+	enum dc_color_depth color_depth)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	/* TODO: add support for other test patterns */
-+	switch (test_pattern) {
-+	default:
-+		value = 0;
-+		addr = tg->regs[IDX_CRTC_TEST_PATTERN_PARAMETERS];
-+
-+		set_reg_field_value(
-+			value,
-+			6,
-+			CRTC_TEST_PATTERN_PARAMETERS,
-+			CRTC_TEST_PATTERN_VRES);
-+		set_reg_field_value(
-+			value,
-+			6,
-+			CRTC_TEST_PATTERN_PARAMETERS,
-+			CRTC_TEST_PATTERN_HRES);
-+
-+		dal_write_reg(ctx, addr, value);
-+
-+		addr = tg->regs[IDX_CRTC_TEST_PATTERN_CONTROL];
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_MODE);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_DYNAMIC_RANGE);
-+		/* add color depth translation here */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_COLOR_FORMAT);
-+		dal_write_reg(ctx, addr, value);
-+		break;
-+	} /* switch() */
-+}
-+
-+/**
-+* dce110_timing_generator_validate_timing
-+* The timing generators support a maximum display size of is 8192 x 8192 pixels,
-+* including both active display and blanking periods. Check H Total and V Total.
-+*/
-+bool dce110_timing_generator_validate_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	enum signal_type signal)
-+{
-+	uint32_t h_blank;
-+	uint32_t h_back_porch;
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+
-+	ASSERT(timing != NULL);
-+
-+	if (!timing)
-+		return false;
-+
-+	/* Check maximum number of pixels supported by Timing Generator
-+	 * (Currently will never fail, in order to fail needs display which
-+	 * needs more than 8192 horizontal and
-+	 * more than 8192 vertical total pixels)
-+	 */
-+	if (timing->h_total > tg->max_h_total ||
-+		timing->v_total > tg->max_v_total)
-+		return false;
-+
-+	h_blank = (timing->h_total - timing->h_addressable -
-+		timing->h_border_right -
-+		timing->h_border_left);
-+
-+	if (h_blank < tg->min_h_blank)
-+		return false;
-+
-+	if (timing->h_front_porch < tg->min_h_front_porch)
-+		return false;
-+
-+	h_back_porch = h_blank - (h_sync_start -
-+		timing->h_addressable -
-+		timing->h_border_right -
-+		timing->h_sync_width);
-+
-+	if (h_back_porch < tg->min_h_back_porch)
-+		return false;
-+
-+	return true;
-+}
-+
-+/**
-+* Wait till we are at the beginning of VBlank.
-+*/
-+void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg)
-+{
-+	/* We want to catch beginning of VBlank here, so if the first try are
-+	 * in VBlank, we might be very close to Active, in this case wait for
-+	 * another frame
-+	 */
-+	while (dce110_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+
-+	while (!dce110_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/**
-+* Wait till we are in VActive (anywhere in VActive)
-+*/
-+void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg)
-+{
-+	while (dce110_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+void dce110_timing_generator_destroy(struct timing_generator **tg)
-+{
-+	dc_service_free((*tg)->ctx, FROM_TIMING_GENERATOR(*tg));
-+	*tg = NULL;
-+}
-+
-+static bool timing_generator_dce110_construct(struct timing_generator *tg,
-+	struct dc_context *ctx,
-+	struct adapter_service *as,
-+	enum controller_id id)
-+{
-+	if (!as)
-+		return false;
-+
-+	switch (id) {
-+	case CONTROLLER_ID_D0:
-+	case CONTROLLER_ID_D1:
-+	case CONTROLLER_ID_D2:
-+		break;
-+	default:
-+		return false;
-+	}
-+
-+	if (!dce110_timing_generator_construct(tg, id))
-+		return false;
-+
-+	tg->ctx = ctx;
-+	tg->bp = dal_adapter_service_get_bios_parser(as);
-+	tg->regs = tg_regs[id-1];
-+
-+	tg->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	tg->min_h_blank = 56;
-+	tg->min_h_front_porch = 4;
-+	tg->min_h_back_porch = 4;
-+
-+	return true;
-+}
-+
-+struct timing_generator *dce110_timing_generator_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx,
-+	enum controller_id id)
-+{
-+	struct dce110_timing_generator *tg =
-+		dc_service_alloc(ctx, sizeof(struct dce110_timing_generator));
-+
-+	if (!tg)
-+		return NULL;
-+
-+	if (timing_generator_dce110_construct(&tg->base, ctx,
-+				as, id))
-+		return &tg->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, tg);
-+	return NULL;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dce110_timing_generator_setup_global_swap_lock
-+ *
-+ *  @brief
-+ *     Setups Global Swap Lock group for current pipe
-+ *     Pipe can join or leave GSL group, become a TimingServer or TimingClient
-+ *
-+ *  @param [in] gsl_params: setup data
-+ *****************************************************************************
-+ */
-+
-+void dce110_timing_generator_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params)
-+{
-+	uint32_t value;
-+	uint32_t address = tg->regs[IDX_DCP_GSL_CONTROL];
-+	uint32_t check_point = FLIP_READY_BACK_LOOKUP;
-+
-+	value = dal_read_reg(tg->ctx, address);
-+
-+	/* This pipe will belong to GSL Group zero. */
-+	set_reg_field_value(value,
-+			1,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL0_EN);
-+
-+	set_reg_field_value(value,
-+			gsl_params->timing_server,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_MASTER_EN);
-+
-+	set_reg_field_value(value,
-+			HFLIP_READY_DELAY,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
-+
-+        /* Keep signal low (pending high) during 6 lines.
-+         * Also defines minimum interval before re-checking signal. */
-+	set_reg_field_value(value,
-+			HFLIP_CHECK_DELAY,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
-+
-+	/* DCP_GSL_PURPOSE_SURFACE_FLIP */
-+	{
-+		uint32_t value_crtc_vtotal;
-+
-+		value_crtc_vtotal = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_V_TOTAL]);
-+
-+		set_reg_field_value(value,
-+				gsl_params->gsl_purpose,
-+				DCP_GSL_CONTROL,
-+				DCP_GSL_SYNC_SOURCE);
-+
-+		/* Checkpoint relative to end of frame */
-+		check_point = get_reg_field_value(value_crtc_vtotal,
-+				CRTC_V_TOTAL,
-+				CRTC_V_TOTAL);
-+
-+		dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_GSL_WINDOW], 0);
-+	}
-+
-+	set_reg_field_value(value,
-+			1,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
-+
-+	dal_write_reg(tg->ctx, address, value);
-+
-+	/********************************************************************/
-+	address = tg->regs[IDX_CRTC_GSL_CONTROL];
-+
-+	value = 0;
-+	set_reg_field_value(value,
-+			check_point - FLIP_READY_BACK_LOOKUP,
-+			CRTC_GSL_CONTROL,
-+			CRTC_GSL_CHECK_LINE_NUM);
-+
-+	set_reg_field_value(value,
-+			VFLIP_READY_DELAY,
-+			CRTC_GSL_CONTROL,
-+			CRTC_GSL_FORCE_DELAY);
-+
-+	dal_write_reg(tg->ctx, address, value);
-+}
-+
-+
-+void dce110_timing_generator_tear_down_global_swap_lock(
-+	struct timing_generator *tg)
-+{
-+	/* Clear all the register writes done by
-+	 * dce110_timing_generator_setup_global_swap_lock
-+	 */
-+
-+	uint32_t value;
-+	uint32_t address = tg->regs[IDX_DCP_GSL_CONTROL];
-+
-+	value = 0;
-+
-+	/* This pipe will belong to GSL Group zero. */
-+	/* Settig HW default values from reg specs */
-+	set_reg_field_value(value,
-+			0,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL0_EN);
-+
-+	set_reg_field_value(value,
-+			0,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_MASTER_EN);
-+
-+	set_reg_field_value(value,
-+			0x2,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
-+
-+
-+	set_reg_field_value(value,
-+			0x6,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
-+
-+	/* Restore DCP_GSL_PURPOSE_SURFACE_FLIP */
-+	{
-+		uint32_t value_crtc_vtotal;
-+
-+		value_crtc_vtotal = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_V_TOTAL]);
-+
-+		set_reg_field_value(value,
-+				0,
-+				DCP_GSL_CONTROL,
-+				DCP_GSL_SYNC_SOURCE);
-+	}
-+
-+	set_reg_field_value(value,
-+			0,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
-+
-+	dal_write_reg(tg->ctx, address, value);
-+
-+	/********************************************************************/
-+	address = tg->regs[IDX_CRTC_GSL_CONTROL];
-+
-+	value = 0;
-+	set_reg_field_value(value,
-+			0,
-+			CRTC_GSL_CONTROL,
-+			CRTC_GSL_CHECK_LINE_NUM);
-+
-+	set_reg_field_value(value,
-+			0x2,
-+			CRTC_GSL_CONTROL,
-+			CRTC_GSL_FORCE_DELAY);
-+
-+	dal_write_reg(tg->ctx, address, value);
-+}
-+/**
-+ *****************************************************************************
-+ *  Function: is_counter_moving
-+ *
-+ *  @brief
-+ *     check if the timing generator is currently going
-+ *
-+ *  @return
-+ *     true if currently going, false if currently paused or stopped.
-+ *
-+ *****************************************************************************
-+ */
-+
-+bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value_1 = 0;
-+	uint32_t field_1 = 0;
-+	uint32_t value_2 = 0;
-+	uint32_t field_2 = 0;
-+
-+	addr = tg->regs[IDX_CRTC_STATUS_POSITION];
-+	value_1 = dal_read_reg(tg->ctx, addr);
-+	value_2 = dal_read_reg(tg->ctx, addr);
-+
-+	field_1 = get_reg_field_value(
-+			value_1, CRTC_STATUS_POSITION, CRTC_HORZ_COUNT);
-+	field_2 = get_reg_field_value(
-+			value_2, CRTC_STATUS_POSITION, CRTC_HORZ_COUNT);
-+
-+	if (field_1 == field_2) {
-+		field_1 = get_reg_field_value(
-+			value_1, CRTC_STATUS_POSITION, CRTC_VERT_COUNT);
-+		field_2 = get_reg_field_value(
-+			value_2, CRTC_STATUS_POSITION, CRTC_VERT_COUNT);
-+		return field_1 != field_2;
-+	}
-+
-+	return true;
-+}
-+
-+/*TODO: Figure out if we need this function. */
-+void dce110_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t addr = tg->regs[IDX_CRTC_START_LINE_CONTROL];
-+	uint32_t value = dal_read_reg(tg->ctx, addr);
-+
-+	if (enable && FROM_TIMING_GENERATOR(tg)->advanced_request_enable) {
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	}
-+
-+	if (dce110_timing_generator_get_vsynch_and_front_porch_size(timing) <= 3) {
-+		set_reg_field_value(
-+			value,
-+			3,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			4,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_PROGRESSIVE_START_LINE_EARLY);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_INTERLACE_START_LINE_EARLY);
-+
-+	dal_write_reg(tg->ctx, addr, value);
-+}
-+
-+/*TODO: Figure out if we need this function. */
-+void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
-+		bool lock)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t addr = tg->regs[IDX_CRTC_MASTER_UPDATE_LOCK];
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		lock ? 1 : 0,
-+		CRTC_MASTER_UPDATE_LOCK,
-+		MASTER_UPDATE_LOCK);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_timing_generator_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	const struct trigger_params *trigger_params)
-+{
-+	uint32_t value;
-+	struct dc_context *dc_ctx = tg->ctx;
-+	uint32_t rising_edge = 0;
-+	uint32_t falling_edge = 0;
-+	enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO;
-+
-+	/* Setup trigger edge */
-+	switch (trigger_params->edge) {
-+	/* Default = based on current timing polarity */
-+	case TRIGGER_EDGE_DEFAULT:
-+		{
-+			uint32_t pol_value = dal_read_reg(tg->ctx,
-+					tg->regs[IDX_CRTC_V_SYNC_A_CNTL]);
-+
-+			/* Register spec has reversed definition:
-+			 *	0 for positive, 1 for negative */
-+			if (get_reg_field_value(pol_value,
-+					CRTC_V_SYNC_A_CNTL,
-+					CRTC_V_SYNC_A_POL) == 0) {
-+				rising_edge = 1;
-+			} else {
-+				falling_edge = 1;
-+			}
-+		}
-+		break;
-+	case TRIGGER_EDGE_RISING:
-+		rising_edge = 1;
-+		break;
-+	case TRIGGER_EDGE_FALLING:
-+		falling_edge = 1;
-+		break;
-+	case TRIGGER_EDGE_BOTH:
-+		rising_edge = 1;
-+		falling_edge = 1;
-+		break;
-+	default:
-+		DC_ERROR("Invalid Trigger Edge!\n");
-+		return;
-+	}
-+
-+	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL]);
-+
-+	switch(trigger_params->source) {
-+	/* Currently supporting only a single group, the group zero. */
-+	case SYNC_SOURCE_GSL_GROUP0:
-+		trig_src_select = TRIGGER_SOURCE_SELECT_GSL_GROUP0;
-+		break;
-+	default:
-+		DC_ERROR("Unsupported GSL Group!\n");
-+		return;
-+	}
-+
-+	set_reg_field_value(value,
-+			trig_src_select,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_SOURCE_SELECT);
-+
-+	set_reg_field_value(value,
-+			TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_POLARITY_SELECT);
-+
-+	set_reg_field_value(value,
-+			rising_edge,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_RISING_EDGE_DETECT_CNTL);
-+
-+	set_reg_field_value(value,
-+			falling_edge,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL);
-+
-+	set_reg_field_value(value,
-+			0, /* send every signal */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_FREQUENCY_SELECT);
-+
-+	set_reg_field_value(value,
-+			0, /* no delay */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_DELAY);
-+
-+	set_reg_field_value(value,
-+			1, /* clear trigger status */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_CLEAR);
-+
-+	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL], value);
-+
-+	/**************************************************************/
-+
-+	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL]);
-+
-+	set_reg_field_value(value,
-+			2, /* force H count to H_TOTAL and V count to V_TOTAL */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_MODE);
-+
-+	set_reg_field_value(value,
-+			1, /* TriggerB - we never use TriggerA */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_TRIG_SEL);
-+
-+	set_reg_field_value(value,
-+			1, /* clear trigger status */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_CLEAR);
-+
-+	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL], value);
-+}
-+
-+void dce110_timing_generator_disable_reset_trigger(
-+	struct timing_generator *tg)
-+{
-+	uint32_t value;
-+
-+	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL]);
-+
-+	set_reg_field_value(value,
-+			0, /* force counter now mode is disabled */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_MODE);
-+
-+	set_reg_field_value(value,
-+			1, /* clear trigger status */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_CLEAR);
-+
-+	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL], value);
-+
-+	/********************************************************************/
-+	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL]);
-+
-+	set_reg_field_value(value,
-+			TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_SOURCE_SELECT);
-+
-+	set_reg_field_value(value,
-+			TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_POLARITY_SELECT);
-+
-+	set_reg_field_value(value,
-+			1, /* clear trigger status */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_CLEAR);
-+
-+	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL], value);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  @brief
-+ *     Checks whether CRTC triggered reset occurred
-+ *
-+ *  @return
-+ *     true if triggered reset occurred, false otherwise
-+ *****************************************************************************
-+ */
-+bool dce110_timing_generator_did_triggered_reset_occur(
-+	struct timing_generator *tg)
-+{
-+	uint32_t value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL]);
-+
-+	return get_reg_field_value(value,
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
-+}
-+
-+/**
-+ * dce110_timing_generator_disable_vga
-+ * Turn OFF VGA Mode and Timing  - DxVGA_CONTROL
-+ * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors;
-+ */
-+void dce110_timing_generator_disable_vga(
-+	struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	switch (tg->controller_id) {
-+	case CONTROLLER_ID_D0:
-+		addr = mmD1VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		addr = mmD2VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		addr = mmD3VGA_CONTROL;
-+		break;
-+	default:
-+		break;
-+	}
-+	value = dal_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
-+	set_reg_field_value(
-+			value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
-+
-+	dal_write_reg(tg->ctx, addr, value);
-+}
-+
-+
-+/**
-+* set_overscan_color_black
-+*
-+* @param :black_color is one of the color space
-+*    :this routine will set overscan black color according to the color space.
-+* @return none
-+*/
-+
-+void dce110_timing_generator_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	enum color_space black_color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	/* Overscan Color for YUV display modes:
-+	 * to achieve a black color for both the explicit and implicit overscan,
-+	 * the overscan color registers should be programmed to: */
-+
-+	switch (black_color) {
-+	case COLOR_SPACE_YPBPR601:
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4TV,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4TV,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4TV,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	case COLOR_SPACE_YPBPR709:
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_YONLY:
-+	case COLOR_SPACE_YCBCR709_YONLY:
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4TV,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4CV,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	case COLOR_SPACE_N_MVPU_SUPER_AA:
-+		/* In crossfire SuperAA mode, the slave overscan data is forced
-+		 * to 0 in the pixel mixer on the master.  As a result, we need
-+		 * to adjust the blank color so that after blending the
-+		 * master+slave, it will appear black */
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4SUPERAA,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4SUPERAA,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_RGB_LIMITED_RANGE,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_RGB_LIMITED_RANGE,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_RGB_LIMITED_RANGE,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	default:
-+		/* default is sRGB black 0. */
-+		break;
-+	}
-+	addr = tg->regs[IDX_CRTC_OVERSCAN_COLOR];
-+	dal_write_reg(ctx, addr, value);
-+	addr = tg->regs[IDX_CRTC_BLACK_COLOR];
-+	dal_write_reg(ctx, addr, value);
-+	/* This is desirable to have a constant DAC output voltage during the
-+	 * blank time that is higher than the 0 volt reference level that the
-+	 * DAC outputs when the NBLANK signal
-+	 * is asserted low, such as for output to an analog TV. */
-+	addr = tg->regs[IDX_CRTC_BLANK_DATA_COLOR];
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* TO DO we have to program EXT registers and we need to know LB DATA
-+	 * format because it is used when more 10 , i.e. 12 bits per color
-+	 *
-+	 * m_mmDxCRTC_OVERSCAN_COLOR_EXT
-+	 * m_mmDxCRTC_BLACK_COLOR_EXT
-+	 * m_mmDxCRTC_BLANK_DATA_COLOR_EXT
-+	 */
-+
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-new file mode 100644
-index 0000000..d95a2a0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -0,0 +1,178 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_DCE110_H__
-+#define __DC_TIMING_GENERATOR_DCE110_H__
-+
-+
-+#include "../include/timing_generator_types.h"
-+#include "../include/grph_object_id.h"
-+
-+/* overscan in blank for YUV color space. For RGB, it is zero for black. */
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV 0x1f4
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4CV 0x40
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4CV 0x1f4
-+
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4TV 0x200
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4TV 0x40
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4TV 0x200
-+
-+/* overscan in blank for YUV color space when in SuperAA crossfire mode */
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4SUPERAA 0x1a2
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4SUPERAA 0x20
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA 0x1a2
-+
-+/* OVERSCAN COLOR FOR RGB LIMITED RANGE
-+ * (16~253) 16*4 (Multiple over 256 code leve) =64 (0x40) */
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_RGB_LIMITED_RANGE 0x40
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_RGB_LIMITED_RANGE 0x40
-+#define CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_RGB_LIMITED_RANGE 0X40
-+
-+struct dce110_timing_generator {
-+	struct timing_generator base;
-+	enum sync_source cached_gsl_group;
-+	bool advanced_request_enable;
-+};
-+
-+struct timing_generator *dce110_timing_generator_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx,
-+	enum controller_id id);
-+
-+void dce110_timing_generator_destroy(struct timing_generator **tg);
-+
-+bool dce110_timing_generator_construct(
-+	struct timing_generator *tg,
-+	enum controller_id id);
-+
-+void dce110_timing_generator_program_blank_color(
-+	struct timing_generator *tg,
-+	enum color_space color_space);
-+
-+bool dce110_timing_generator_blank_crtc(struct timing_generator *tg);
-+
-+bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
-+
-+bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
-+
-+bool dce110_timing_generator_is_in_vertical_blank(struct timing_generator *tg);
-+
-+void dce110_timing_generator_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing);
-+
-+bool dce110_timing_generator_program_timing_generator(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *dc_crtc_timing);
-+
-+void dce110_timing_generator_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl);
-+
-+bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg);
-+
-+bool dce110_timing_generator_validate_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	enum signal_type signal);
-+
-+void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg);
-+
-+void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg);
-+
-+void dce110_timing_generator_set_test_pattern(
-+	struct timing_generator *tg,
-+	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-+	 * because this is not DP-specific (which is probably somewhere in DP
-+	 * encoder) */
-+	enum controller_dp_test_pattern test_pattern,
-+	enum dc_color_depth color_depth);
-+
-+void dce110_timing_generator_program_drr(
-+	struct timing_generator *tg,
-+	const struct hw_ranged_timing *timing);
-+
-+uint32_t dce110_timing_generator_get_crtc_scanoutpos(
-+	struct timing_generator *tg,
-+	int32_t *vbl,
-+	int32_t *position);
-+
-+uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg);
-+
-+void dce110_timing_generator_color_space_to_black_color(
-+		enum color_space colorspace,
-+		struct crtc_black_color *black_color);
-+void dce110_timing_generator_apply_front_porch_workaround(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *timing);
-+int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
-+	const struct dc_crtc_timing *timing);
-+
-+void dce110_timing_generator_get_crtc_positions(
-+	struct timing_generator *tg,
-+	int32_t *h_position,
-+	int32_t *v_position);
-+
-+
-+/* TODO: Figure out if we need these functions*/
-+bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg);
-+
-+void dce110_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing);
-+
-+void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
-+		bool lock);
-+
-+void dce110_timing_generator_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	enum color_space black_color);
-+
-+
-+/**** Sync-related interfaces ****/
-+void dce110_timing_generator_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params);
-+void dce110_timing_generator_tear_down_global_swap_lock(
-+	struct timing_generator *tg);
-+
-+
-+void dce110_timing_generator_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	const struct trigger_params *trigger_params);
-+
-+void dce110_timing_generator_disable_reset_trigger(
-+	struct timing_generator *tg);
-+
-+bool dce110_timing_generator_did_triggered_reset_occur(
-+	struct timing_generator *tg);
-+
-+void dce110_timing_generator_disable_vga(
-+	struct timing_generator *tg);
-+
-+/**** End-of-Sync-related interfaces ****/
-+
-+#endif /* __DC_TIMING_GENERATOR_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-new file mode 100644
-index 0000000..f3b3630
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "core_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/fixed31_32.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce110_transform.h"
-+#include "dce110_transform_bit_depth.h"
-+
-+static const struct dce110_transform_reg_offsets reg_offsets[] = {
-+{
-+	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL0_SCL_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL0_SCL_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL0_SCL_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+}
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce110_transform_construct(
-+	struct dce110_transform *xfm110,
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+		return false;
-+
-+	xfm110->base.ctx = ctx;
-+
-+	xfm110->base.inst = inst;
-+
-+	xfm110->offsets = reg_offsets[inst - 1];
-+
-+	xfm110->lb_pixel_depth_supported =
-+			LB_PIXEL_DEPTH_18BPP |
-+			LB_PIXEL_DEPTH_24BPP |
-+			LB_PIXEL_DEPTH_30BPP;
-+
-+	return true;
-+}
-+
-+void dce110_transform_destroy(struct transform **xfm)
-+{
-+	dc_service_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+struct transform *dce110_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_transform *transform =
-+		dc_service_alloc(ctx, sizeof(struct dce110_transform));
-+
-+	if (!transform)
-+		return NULL;
-+
-+	if (dce110_transform_construct(transform,
-+			ctx, inst))
-+		return &transform->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, transform);
-+	return NULL;
-+}
-+
-+bool dce110_transform_power_up(struct transform *xfm)
-+{
-+	return dce110_transform_power_up_line_buffer(xfm);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-new file mode 100644
-index 0000000..edf016c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -0,0 +1,91 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_DCE110_H__
-+#define __DAL_TRANSFORM_DCE110_H__
-+
-+#include "inc/transform.h"
-+#include "include/grph_csc_types.h"
-+
-+#define TO_DCE110_TRANSFORM(transform)\
-+	container_of(transform, struct dce110_transform, base)
-+
-+struct dce110_transform_reg_offsets {
-+	uint32_t scl_offset;
-+	uint32_t dcfe_offset;
-+	uint32_t dcp_offset;
-+	uint32_t lb_offset;
-+};
-+
-+struct dce110_transform {
-+	struct transform base;
-+	struct dce110_transform_reg_offsets offsets;
-+
-+	uint32_t lb_pixel_depth_supported;
-+};
-+
-+bool dce110_transform_construct(struct dce110_transform *xfm110,
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+void dce110_transform_destroy(struct transform **xfm);
-+
-+struct transform *dce110_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+bool dce110_transform_power_up(struct transform *xfm);
-+
-+/* SCALER RELATED */
-+bool dce110_transform_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data);
-+
-+void dce110_transform_set_scaler_bypass(struct transform *xfm);
-+
-+bool dce110_transform_update_viewport(
-+	struct transform *xfm,
-+	const struct rect *view_port,
-+	bool is_fbc_attached);
-+
-+void dce110_transform_set_scaler_filter(
-+	struct transform *xfm,
-+	struct scaler_filter *filter);
-+
-+/* GAMUT RELATED */
-+void dce110_transform_set_gamut_remap(
-+	struct transform *xfm,
-+	const struct grph_csc_adjustment *adjust);
-+
-+/* BIT DEPTH RELATED */
-+bool dce110_transform_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth);
-+
-+bool dce110_transform_get_current_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth *depth);
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-new file mode 100644
-index 0000000..747f2c7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -0,0 +1,840 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_transform.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/fixed32_32.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + xfm110->offsets.dcp_offset)
-+
-+#define LB_REG(reg)\
-+	(reg + xfm110->offsets.lb_offset)
-+
-+#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-+#define LB_BITS_PER_ENTRY 144
-+
-+enum dcp_out_trunc_round_mode {
-+	DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+	DCP_OUT_TRUNC_ROUND_MODE_ROUND
-+};
-+
-+enum dcp_out_trunc_round_depth {
-+	DCP_OUT_TRUNC_ROUND_DEPTH_14BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_13BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_12BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_11BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_10BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_9BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_8BIT
-+};
-+
-+/*  defines the various methods of bit reduction available for use */
-+enum dcp_bit_depth_reduction_mode {
-+	DCP_BIT_DEPTH_REDUCTION_MODE_DITHER,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_ROUND,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_INVALID
-+};
-+
-+enum dcp_spatial_dither_mode {
-+	DCP_SPATIAL_DITHER_MODE_AAAA,
-+	DCP_SPATIAL_DITHER_MODE_A_AA_A,
-+	DCP_SPATIAL_DITHER_MODE_AABBAABB,
-+	DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC,
-+	DCP_SPATIAL_DITHER_MODE_INVALID
-+};
-+
-+enum dcp_spatial_dither_depth {
-+	DCP_SPATIAL_DITHER_DEPTH_30BPP,
-+	DCP_SPATIAL_DITHER_DEPTH_24BPP
-+};
-+
-+static bool set_clamp(
-+	struct dce110_transform *xfm110,
-+	enum dc_color_depth depth);
-+
-+static bool set_round(
-+	struct dce110_transform *xfm110,
-+	enum dcp_out_trunc_round_mode mode,
-+	enum dcp_out_trunc_round_depth depth);
-+
-+static bool set_dither(
-+	struct dce110_transform *xfm110,
-+	bool dither_enable,
-+	enum dcp_spatial_dither_mode dither_mode,
-+	enum dcp_spatial_dither_depth dither_depth,
-+	bool frame_random_enable,
-+	bool rgb_random_enable,
-+	bool highpass_random_enable);
-+
-+/**
-+ *******************************************************************************
-+ * dce110_transform_bit_depth_reduction_program
-+ *
-+ * @brief
-+ *     Programs the DCP bit depth reduction registers (Clamp, Round/Truncate,
-+ *      Dither) for dce110
-+ *
-+ * @param depth : bit depth to set the clamp to (should match denorm)
-+ *
-+ * @return
-+ *     true if succeeds.
-+ *******************************************************************************
-+ */
-+static bool program_bit_depth_reduction(
-+	struct dce110_transform *xfm110,
-+	enum dc_color_depth depth)
-+{
-+	enum dcp_bit_depth_reduction_mode depth_reduction_mode;
-+	enum dcp_spatial_dither_mode spatial_dither_mode;
-+	bool frame_random_enable;
-+	bool rgb_random_enable;
-+	bool highpass_random_enable;
-+
-+	if (depth > COLOR_DEPTH_121212) {
-+		ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
-+		return false;
-+	}
-+
-+	depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
-+
-+	spatial_dither_mode = DCP_SPATIAL_DITHER_MODE_A_AA_A;
-+
-+	frame_random_enable = true;
-+	rgb_random_enable = true;
-+	highpass_random_enable = true;
-+
-+	if (!set_clamp(xfm110, depth)) {
-+		/* Failure in set_clamp() */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+	switch (depth_reduction_mode) {
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_DITHER:
-+		/*  Spatial Dither: Set round/truncate to bypass (12bit),
-+		 *  enable Dither (30bpp) */
-+		set_round(xfm110,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-+
-+		set_dither(xfm110, true, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_ROUND:
-+		/*  Round: Enable round (10bit), disable Dither */
-+		set_round(xfm110,
-+			DCP_OUT_TRUNC_ROUND_MODE_ROUND,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-+
-+		set_dither(xfm110, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE: /*  Truncate */
-+		/*  Truncate: Enable truncate (10bit), disable Dither */
-+		set_round(xfm110,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-+
-+		set_dither(xfm110, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED: /*  Disabled */
-+		/*  Truncate: Set round/truncate to bypass (12bit),
-+		 * disable Dither */
-+		set_round(xfm110,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-+
-+		set_dither(xfm110, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	default:
-+		/* Invalid DCP Depth reduction mode */
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ *******************************************************************************
-+ * set_clamp
-+ *
-+ * @param depth : bit depth to set the clamp to (should match denorm)
-+ *
-+ * @brief
-+ *     Programs clamp according to panel bit depth.
-+ *
-+ * @return
-+ *     true if succeeds
-+ *
-+ *******************************************************************************
-+ */
-+static bool set_clamp(
-+	struct dce110_transform *xfm110,
-+	enum dc_color_depth depth)
-+{
-+	uint32_t clamp_max = 0;
-+
-+	/* At the clamp block the data will be MSB aligned, so we set the max
-+	 * clamp accordingly.
-+	 * For example, the max value for 6 bits MSB aligned (14 bit bus) would
-+	 * be "11 1111 0000 0000" in binary, so 0x3F00.
-+	 */
-+	switch (depth) {
-+	case COLOR_DEPTH_666:
-+		/* 6bit MSB aligned on 14 bit bus '11 1111 0000 0000' */
-+		clamp_max = 0x3F00;
-+		break;
-+	case COLOR_DEPTH_888:
-+		/* 8bit MSB aligned on 14 bit bus '11 1111 1100 0000' */
-+		clamp_max = 0x3FC0;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 10bit MSB aligned on 14 bit bus '11 1111 1111 1100' */
-+		clamp_max = 0x3FFC;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 12bit MSB aligned on 14 bit bus '11 1111 1111 1111' */
-+		clamp_max = 0x3FFF;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
-+		return false;
-+	}
-+
-+	{
-+		uint32_t value = 0;
-+		/*  always set min to 0 */
-+			set_reg_field_value(
-+			value,
-+			0,
-+			OUT_CLAMP_CONTROL_B_CB,
-+			OUT_CLAMP_MIN_B_CB);
-+
-+		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_B_CB,
-+			OUT_CLAMP_MAX_B_CB);
-+
-+		dal_write_reg(xfm110->base.ctx,
-+			DCP_REG(mmOUT_CLAMP_CONTROL_B_CB),
-+			value);
-+	}
-+
-+	{
-+		uint32_t value = 0;
-+		/*  always set min to 0 */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			OUT_CLAMP_CONTROL_G_Y,
-+			OUT_CLAMP_MIN_G_Y);
-+
-+		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_G_Y,
-+			OUT_CLAMP_MAX_G_Y);
-+
-+		dal_write_reg(xfm110->base.ctx,
-+			DCP_REG(mmOUT_CLAMP_CONTROL_G_Y),
-+			value);
-+	}
-+
-+	{
-+		uint32_t value = 0;
-+		/*  always set min to 0 */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MIN_R_CR);
-+
-+		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MAX_R_CR);
-+
-+		dal_write_reg(xfm110->base.ctx,
-+			DCP_REG(mmOUT_CLAMP_CONTROL_R_CR),
-+			value);
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ *******************************************************************************
-+ * set_round
-+ *
-+ * @brief
-+ *     Programs Round/Truncate
-+ *
-+ * @param [in] mode  :round or truncate
-+ * @param [in] depth :bit depth to round/truncate to
-+ OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode
-+ POSSIBLE VALUES:
-+      00 - truncate to u0.12
-+      01 - truncate to u0.11
-+      02 - truncate to u0.10
-+      03 - truncate to u0.9
-+      04 - truncate to u0.8
-+      05 - reserved
-+      06 - truncate to u0.14
-+      07 - truncate to u0.13		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MAX_R_CR);
-+      08 - round to u0.12
-+      09 - round to u0.11
-+      10 - round to u0.10
-+      11 - round to u0.9
-+      12 - round to u0.8
-+      13 - reserved
-+      14 - round to u0.14
-+      15 - round to u0.13
-+
-+ * @return
-+ *     true if succeeds.
-+ *******************************************************************************
-+ */
-+static bool set_round(
-+	struct dce110_transform *xfm110,
-+	enum dcp_out_trunc_round_mode mode,
-+	enum dcp_out_trunc_round_depth depth)
-+{
-+	uint32_t depth_bits = 0;
-+	uint32_t mode_bit = 0;
-+	/*  zero out all bits */
-+	uint32_t value = 0;
-+
-+	/*  set up bit depth */
-+	switch (depth) {
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT:
-+		depth_bits = 6;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT:
-+		depth_bits = 7;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT:
-+		depth_bits = 0;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT:
-+		depth_bits = 1;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT:
-+		depth_bits = 2;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT:
-+		depth_bits = 3;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT:
-+		depth_bits = 4;
-+		break;
-+	default:
-+		/* Invalid dcp_out_trunc_round_depth */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		depth_bits,
-+		OUT_ROUND_CONTROL,
-+		OUT_ROUND_TRUNC_MODE);
-+
-+	/*  set up round or truncate */
-+	switch (mode) {
-+	case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
-+		mode_bit = 0;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_MODE_ROUND:
-+		mode_bit = 1;
-+		break;
-+	default:
-+		/* Invalid dcp_out_trunc_round_mode */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	depth_bits |= mode_bit << 3;
-+
-+	set_reg_field_value(
-+		value,
-+		depth_bits,
-+		OUT_ROUND_CONTROL,
-+		OUT_ROUND_TRUNC_MODE);
-+
-+	/*  write the register */
-+	dal_write_reg(xfm110->base.ctx,
-+				DCP_REG(mmOUT_ROUND_CONTROL),
-+				value);
-+
-+	return true;
-+}
-+
-+/**
-+ *******************************************************************************
-+ * set_dither
-+ *
-+ * @brief
-+ *     Programs Dither
-+ *
-+ * @param [in] dither_enable        : enable dither
-+ * @param [in] dither_mode           : dither mode to set
-+ * @param [in] dither_depth          : bit depth to dither to
-+ * @param [in] frame_random_enable    : enable frame random
-+ * @param [in] rgb_random_enable      : enable rgb random
-+ * @param [in] highpass_random_enable : enable highpass random
-+ *
-+ * @return
-+ *     true if succeeds.
-+ *******************************************************************************
-+ */
-+
-+static bool set_dither(
-+	struct dce110_transform *xfm110,
-+	bool dither_enable,
-+	enum dcp_spatial_dither_mode dither_mode,
-+	enum dcp_spatial_dither_depth dither_depth,
-+	bool frame_random_enable,
-+	bool rgb_random_enable,
-+	bool highpass_random_enable)
-+{
-+	uint32_t dither_depth_bits = 0;
-+	uint32_t dither_mode_bits = 0;
-+	/*  zero out all bits */
-+	uint32_t value = 0;
-+
-+	/* set up the fields */
-+	if (dither_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_SPATIAL_DITHER_EN);
-+
-+	switch (dither_mode) {
-+	case DCP_SPATIAL_DITHER_MODE_AAAA:
-+		dither_mode_bits = 0;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_A_AA_A:
-+		dither_mode_bits = 1;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_AABBAABB:
-+		dither_mode_bits = 2;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC:
-+		dither_mode_bits = 3;
-+		break;
-+	default:
-+		/* Invalid dcp_spatial_dither_mode */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+
-+	}
-+	set_reg_field_value(
-+		value,
-+		dither_mode_bits,
-+		DCP_SPATIAL_DITHER_CNTL,
-+		DCP_SPATIAL_DITHER_MODE);
-+
-+	switch (dither_depth) {
-+	case DCP_SPATIAL_DITHER_DEPTH_30BPP:
-+		dither_depth_bits = 0;
-+		break;
-+	case DCP_SPATIAL_DITHER_DEPTH_24BPP:
-+		dither_depth_bits = 1;
-+		break;
-+	default:
-+		/* Invalid dcp_spatial_dither_depth */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		dither_depth_bits,
-+		DCP_SPATIAL_DITHER_CNTL,
-+		DCP_SPATIAL_DITHER_DEPTH);
-+
-+	if (frame_random_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_FRAME_RANDOM_ENABLE);
-+
-+	if (rgb_random_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_RGB_RANDOM_ENABLE);
-+
-+	if (highpass_random_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_HIGHPASS_RANDOM_ENABLE);
-+
-+	/*  write the register */
-+	dal_write_reg(xfm110->base.ctx,
-+				DCP_REG(mmDCP_SPATIAL_DITHER_CNTL),
-+				value);
-+
-+	return true;
-+}
-+
-+bool dce110_transform_get_max_num_of_supported_lines(
-+	struct dce110_transform *xfm110,
-+	enum lb_pixel_depth depth,
-+	uint32_t pixel_width,
-+	uint32_t *lines)
-+{
-+	uint32_t pixels_per_entries = 0;
-+	uint32_t max_pixels_supports = 0;
-+
-+	if (pixel_width == 0)
-+		return false;
-+
-+	/* Find number of pixels that can fit into a single LB entry and
-+	 * take floor of the value since we cannot store a single pixel
-+	 * across multiple entries. */
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 18;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_24BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 24;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_30BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 30;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_36BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 36;
-+		break;
-+
-+	default:
-+		dal_logger_write(xfm110->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid LB pixel depth",
-+			__func__);
-+		break;
-+	}
-+
-+	if (pixels_per_entries == 0)
-+		return false;
-+
-+	max_pixels_supports = pixels_per_entries * LB_TOTAL_NUMBER_OF_ENTRIES;
-+
-+	*lines = max_pixels_supports / pixel_width;
-+	return true;
-+}
-+
-+void dce110_transform_enable_alpha(
-+	struct dce110_transform *xfm110,
-+	bool enable)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value;
-+	uint32_t addr = LB_REG(mmLB_DATA_FORMAT);
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	if (enable == 1)
-+		set_reg_field_value(
-+				value,
-+				1,
-+				LB_DATA_FORMAT,
-+				ALPHA_EN);
-+	else
-+		set_reg_field_value(
-+				value,
-+				0,
-+				LB_DATA_FORMAT,
-+				ALPHA_EN);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static enum lb_pixel_depth translate_display_bpp_to_lb_depth(
-+	uint32_t display_bpp)
-+{
-+	switch (display_bpp) {
-+	case 18:
-+		return LB_PIXEL_DEPTH_18BPP;
-+	case 24:
-+		return LB_PIXEL_DEPTH_24BPP;
-+	case 36:
-+	case 42:
-+	case 48:
-+		return LB_PIXEL_DEPTH_36BPP;
-+	case 30:
-+	default:
-+		return LB_PIXEL_DEPTH_30BPP;
-+	}
-+}
-+
-+bool dce110_transform_get_next_lower_pixel_storage_depth(
-+	struct dce110_transform *xfm110,
-+	uint32_t display_bpp,
-+	enum lb_pixel_depth depth,
-+	enum lb_pixel_depth *lower_depth)
-+{
-+	enum lb_pixel_depth depth_req_by_display =
-+		translate_display_bpp_to_lb_depth(display_bpp);
-+	uint32_t current_required_depth = depth_req_by_display;
-+	uint32_t current_depth = depth;
-+
-+	/* if required display depth < current we could go down, for example
-+	 * from LB_PIXEL_DEPTH_30BPP to LB_PIXEL_DEPTH_24BPP
-+	 */
-+	if (current_required_depth < current_depth) {
-+		current_depth = current_depth >> 1;
-+		if (xfm110->lb_pixel_depth_supported & current_depth) {
-+			*lower_depth = current_depth;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+bool dce110_transform_is_prefetch_enabled(
-+	struct dce110_transform *xfm110)
-+{
-+	uint32_t value = dal_read_reg(
-+			xfm110->base.ctx, LB_REG(mmLB_DATA_FORMAT));
-+
-+	if (get_reg_field_value(value, LB_DATA_FORMAT, PREFETCH) == 1)
-+		return true;
-+
-+	return false;
-+}
-+
-+bool dce110_transform_get_current_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth *depth)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	uint32_t value = 0;
-+
-+	if (depth == NULL)
-+		return false;
-+
-+	value = dal_read_reg(
-+			xfm->ctx,
-+			LB_REG(mmLB_DATA_FORMAT));
-+
-+	switch (get_reg_field_value(value, LB_DATA_FORMAT, PIXEL_DEPTH)) {
-+	case 0:
-+		*depth = LB_PIXEL_DEPTH_30BPP;
-+		break;
-+	case 1:
-+		*depth = LB_PIXEL_DEPTH_24BPP;
-+		break;
-+	case 2:
-+		*depth = LB_PIXEL_DEPTH_18BPP;
-+		break;
-+	case 3:
-+		*depth = LB_PIXEL_DEPTH_36BPP;
-+		break;
-+	default:
-+		dal_logger_write(xfm->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid LB pixel depth",
-+			__func__);
-+		*depth = LB_PIXEL_DEPTH_30BPP;
-+		break;
-+	}
-+	return true;
-+
-+}
-+
-+static void set_denormalization(
-+	struct dce110_transform *xfm110,
-+	enum dc_color_depth depth)
-+{
-+	uint32_t value = dal_read_reg(xfm110->base.ctx,
-+			DCP_REG(mmDENORM_CONTROL));
-+
-+	switch (depth) {
-+	case COLOR_DEPTH_666:
-+		/* 63/64 for 6 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_888:
-+		/* Unity for 8 bit output color depth
-+		 * because prescale is disabled by default */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 1023/1024 for 10 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 4095/4096 for 12 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			5,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_141414:
-+	case COLOR_DEPTH_161616:
-+	default:
-+		/* not valid used case! */
-+		break;
-+	}
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			DCP_REG(mmDENORM_CONTROL),
-+			value);
-+
-+}
-+
-+bool dce110_transform_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool ret = true;
-+	uint32_t value;
-+	enum dc_color_depth color_depth;
-+
-+	value = dal_read_reg(
-+			xfm->ctx,
-+			LB_REG(mmLB_DATA_FORMAT));
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		color_depth = COLOR_DEPTH_666;
-+		set_reg_field_value(value, 2, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	case LB_PIXEL_DEPTH_24BPP:
-+		color_depth = COLOR_DEPTH_888;
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	case LB_PIXEL_DEPTH_30BPP:
-+		color_depth = COLOR_DEPTH_101010;
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		color_depth = COLOR_DEPTH_121212;
-+		set_reg_field_value(value, 3, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	default:
-+		ret = false;
-+		break;
-+	}
-+
-+	if (ret == true) {
-+		set_denormalization(xfm110, color_depth);
-+		ret = program_bit_depth_reduction(xfm110, color_depth);
-+
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
-+		dal_write_reg(
-+				xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
-+		if (!(xfm110->lb_pixel_depth_supported & depth)) {
-+			/*we should use unsupported capabilities
-+			 *  unless it is required by w/a*/
-+			dal_logger_write(xfm->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: Capability not supported",
-+				__func__);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+/* LB_MEMORY_CONFIG
-+ *  00 - Use all three pieces of memory
-+ *  01 - Use only one piece of memory of total 720x144 bits
-+ *  10 - Use two pieces of memory of total 960x144 bits
-+ *  11 - reserved
-+ *
-+ * LB_MEMORY_SIZE
-+ *  Total entries of LB memory.
-+ *  This number should be larger than 960. The default value is 1712(0x6B0) */
-+bool dce110_transform_power_up_line_buffer(struct transform *xfm)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	uint32_t value;
-+
-+	value = dal_read_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-+
-+	/*Use all three pieces of memory always*/
-+	set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
-+	/*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
-+	set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LB_MEMORY_CTRL,
-+			LB_MEMORY_SIZE);
-+
-+	dal_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
-new file mode 100644
-index 0000000..ff100cc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
-@@ -0,0 +1,51 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TRANSFORM_BIT_DEPTH_DCE110_H__
-+#define __DC_TRANSFORM_BIT_DEPTH_DCE110_H__
-+
-+#include "dce110_transform.h"
-+
-+bool dce110_transform_power_up_line_buffer(struct transform *xfm);
-+
-+bool dce110_transform_get_max_num_of_supported_lines(
-+	struct dce110_transform *xfm110,
-+	enum lb_pixel_depth depth,
-+	uint32_t pixel_width,
-+	uint32_t *lines);
-+
-+void dce110_transform_enable_alpha(
-+	struct dce110_transform *xfm110,
-+	bool enable);
-+
-+bool dce110_transform_get_next_lower_pixel_storage_depth(
-+	struct dce110_transform *xfm110,
-+	uint32_t display_bpp,
-+	enum lb_pixel_depth depth,
-+	enum lb_pixel_depth *lower_depth);
-+
-+bool dce110_transform_is_prefetch_enabled(
-+	struct dce110_transform *xfm110);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-new file mode 100644
-index 0000000..a5b5b01
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-@@ -0,0 +1,297 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "dce110_transform.h"
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "include/fixed31_32.h"
-+#include "include/hw_sequencer_types.h"
-+#include "basics/conversion.h"
-+#include "include/grph_object_id.h"
-+
-+enum {
-+	GAMUT_MATRIX_SIZE = 12
-+};
-+
-+#define DCP_REG(reg)\
-+	(reg + xfm110->offsets.dcp_offset)
-+
-+#define DISP_BRIGHTNESS_DEFAULT_HW 0
-+#define DISP_BRIGHTNESS_MIN_HW -25
-+#define DISP_BRIGHTNESS_MAX_HW 25
-+#define DISP_BRIGHTNESS_STEP_HW 1
-+#define DISP_BRIGHTNESS_HW_DIVIDER 100
-+
-+#define DISP_HUE_DEFAULT_HW 0
-+#define DISP_HUE_MIN_HW -30
-+#define DISP_HUE_MAX_HW 30
-+#define DISP_HUE_STEP_HW 1
-+#define DISP_HUE_HW_DIVIDER 1
-+
-+#define DISP_CONTRAST_DEFAULT_HW 100
-+#define DISP_CONTRAST_MIN_HW 50
-+#define DISP_CONTRAST_MAX_HW 150
-+#define DISP_CONTRAST_STEP_HW 1
-+#define DISP_CONTRAST_HW_DIVIDER 100
-+
-+#define DISP_SATURATION_DEFAULT_HW 100
-+#define DISP_SATURATION_MIN_HW 0
-+#define DISP_SATURATION_MAX_HW 200
-+#define DISP_SATURATION_STEP_HW 1
-+#define DISP_SATURATION_HW_DIVIDER 100
-+
-+#define DISP_KELVIN_DEGRES_DEFAULT 6500
-+#define DISP_KELVIN_DEGRES_MIN 4000
-+#define DISP_KELVIN_DEGRES_MAX 10000
-+#define DISP_KELVIN_DEGRES_STEP 100
-+#define DISP_KELVIN_HW_DIVIDER 10000
-+
-+static void program_gamut_remap(
-+	struct dce110_transform *xfm110,
-+	const uint16_t *reg_val)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-+
-+	/* the register controls ovl also */
-+	value = dal_read_reg(ctx, addr);
-+
-+	if (reg_val) {
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C11_C12);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[0],
-+				GAMUT_REMAP_C11_C12,
-+				GAMUT_REMAP_C11);
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[1],
-+				GAMUT_REMAP_C11_C12,
-+				GAMUT_REMAP_C12);
-+
-+			dal_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C13_C14);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[2],
-+				GAMUT_REMAP_C13_C14,
-+				GAMUT_REMAP_C13);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[3],
-+				GAMUT_REMAP_C13_C14,
-+				GAMUT_REMAP_C14);
-+
-+			dal_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C21_C22);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[4],
-+				GAMUT_REMAP_C21_C22,
-+				GAMUT_REMAP_C21);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[5],
-+				GAMUT_REMAP_C21_C22,
-+				GAMUT_REMAP_C22);
-+
-+			dal_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C23_C24);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[6],
-+				GAMUT_REMAP_C23_C24,
-+				GAMUT_REMAP_C23);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[7],
-+				GAMUT_REMAP_C23_C24,
-+				GAMUT_REMAP_C24);
-+
-+			dal_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C31_C32);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[8],
-+				GAMUT_REMAP_C31_C32,
-+				GAMUT_REMAP_C31);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[9],
-+				GAMUT_REMAP_C31_C32,
-+				GAMUT_REMAP_C32);
-+
-+			dal_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C33_C34);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[10],
-+				GAMUT_REMAP_C33_C34,
-+				GAMUT_REMAP_C33);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[11],
-+				GAMUT_REMAP_C33_C34,
-+				GAMUT_REMAP_C34);
-+
-+			dal_write_reg(ctx, addr, reg_data);
-+		}
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			GAMUT_REMAP_CONTROL,
-+			GRPH_GAMUT_REMAP_MODE);
-+
-+	} else
-+		set_reg_field_value(
-+			value,
-+			0,
-+			GAMUT_REMAP_CONTROL,
-+			GRPH_GAMUT_REMAP_MODE);
-+
-+	addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-+	dal_write_reg(ctx, addr, value);
-+
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_gamut_remap
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and apply color temperature adjustment to in Rgb color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+void dce110_transform_set_gamut_remap(
-+	struct transform *xfm,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+
-+	if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW ||
-+		adjust->temperature_divider == 0)
-+		program_gamut_remap(xfm110, NULL);
-+	else {
-+		struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE];
-+		uint16_t arr_reg_val[GAMUT_MATRIX_SIZE];
-+
-+		arr_matrix[0] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[0],
-+				adjust->temperature_divider);
-+		arr_matrix[1] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[1],
-+				adjust->temperature_divider);
-+		arr_matrix[2] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[2],
-+				adjust->temperature_divider);
-+		arr_matrix[3] = dal_fixed31_32_zero;
-+
-+		arr_matrix[4] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[3],
-+				adjust->temperature_divider);
-+		arr_matrix[5] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[4],
-+				adjust->temperature_divider);
-+		arr_matrix[6] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[5],
-+				adjust->temperature_divider);
-+		arr_matrix[7] = dal_fixed31_32_zero;
-+
-+		arr_matrix[8] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[6],
-+				adjust->temperature_divider);
-+		arr_matrix[9] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[7],
-+				adjust->temperature_divider);
-+		arr_matrix[10] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[8],
-+				adjust->temperature_divider);
-+		arr_matrix[11] = dal_fixed31_32_zero;
-+
-+		convert_float_matrix(
-+			arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
-+
-+		program_gamut_remap(xfm110, arr_reg_val);
-+	}
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-new file mode 100644
-index 0000000..f313d2c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -0,0 +1,818 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_transform.h"
-+
-+#define UP_SCALER_RATIO_MAX 16000
-+#define DOWN_SCALER_RATIO_MAX 250
-+#define SCALER_RATIO_DIVIDER 1000
-+
-+#define SCL_REG(reg)\
-+	(reg + xfm110->offsets.scl_offset)
-+
-+#define DCFE_REG(reg)\
-+	(reg + xfm110->offsets.dcfe_offset)
-+
-+static void disable_enhanced_sharpness(struct dce110_transform *xfm110)
-+{
-+	uint32_t  value;
-+
-+	value = dal_read_reg(xfm110->base.ctx,
-+			SCL_REG(mmSCL_F_SHARP_CONTROL));
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_HF_SHARP_EN);
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_VF_SHARP_EN);
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_HF_SHARP_SCALE_FACTOR);
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_VF_SHARP_SCALE_FACTOR);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			SCL_REG(mmSCL_F_SHARP_CONTROL), value);
-+}
-+
-+/**
-+* Function:
-+* void setup_scaling_configuration
-+*
-+* Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
-+* Input:   data
-+*
-+* Output:
-+   void
-+*/
-+static bool setup_scaling_configuration(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	if (data->taps.h_taps + data->taps.v_taps <= 2) {
-+		dce110_transform_set_scaler_bypass(&xfm110->base);
-+		return false;
-+	}
-+
-+	{
-+		addr = SCL_REG(mmSCL_MODE);
-+		value = dal_read_reg(ctx, addr);
-+
-+		if (data->dal_pixel_format <= PIXEL_FORMAT_GRPH_END)
-+			set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
-+		else
-+			set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
-+
-+		set_reg_field_value(value, 1, SCL_MODE, SCL_PSCL_EN);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		addr = SCL_REG(mmSCL_TAP_CONTROL);
-+		value = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(value, data->taps.h_taps - 1,
-+				SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+
-+		set_reg_field_value(value, data->taps.v_taps - 1,
-+				SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	{
-+		addr = SCL_REG(mmSCL_CONTROL);
-+		value = dal_read_reg(ctx, addr);
-+		 /* 1 - Replaced out of bound pixels with edge */
-+		set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
-+
-+		/* 1 - Replaced out of bound pixels with the edge pixel. */
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+* Function:
-+* void program_overscan
-+*
-+* Purpose: Programs overscan border
-+* Input:   overscan
-+*
-+* Output:
-+   void
-+*/
-+static void program_overscan(
-+		struct dce110_transform *xfm110,
-+		const struct overscan_info *overscan)
-+{
-+	uint32_t overscan_left_right = 0;
-+	uint32_t overscan_top_bottom = 0;
-+
-+	set_reg_field_value(overscan_left_right, overscan->left,
-+			EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-+
-+	set_reg_field_value(overscan_left_right, overscan->right,
-+			EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->top,
-+			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->bottom,
-+			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			SCL_REG(mmEXT_OVERSCAN_LEFT_RIGHT),
-+			overscan_left_right);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			SCL_REG(mmEXT_OVERSCAN_TOP_BOTTOM),
-+			overscan_top_bottom);
-+}
-+
-+static void program_two_taps_filter(
-+	struct dce110_transform *xfm110,
-+	bool enable,
-+	bool vertical)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+	/* 1: Hard coded 2 tap filter
-+	 * 0: Programmable 2 tap filter from coefficient RAM
-+	 */
-+	if (vertical) {
-+		addr = SCL_REG(mmSCL_VERT_FILTER_CONTROL);
-+		value = dal_read_reg(xfm110->base.ctx, addr);
-+		set_reg_field_value(
-+			value,
-+			enable ? 1 : 0,
-+				SCL_VERT_FILTER_CONTROL,
-+				SCL_V_2TAP_HARDCODE_COEF_EN);
-+
-+	} else {
-+		addr = SCL_REG(mmSCL_HORZ_FILTER_CONTROL);
-+		value = dal_read_reg(xfm110->base.ctx, addr);
-+		set_reg_field_value(
-+			value,
-+			enable ? 1 : 0,
-+			SCL_HORZ_FILTER_CONTROL,
-+			SCL_H_2TAP_HARDCODE_COEF_EN);
-+	}
-+
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+}
-+
-+static void set_coeff_update_complete(struct dce110_transform *xfm110)
-+{
-+	uint32_t value;
-+	uint32_t addr = SCL_REG(mmSCL_UPDATE);
-+
-+	value = dal_read_reg(xfm110->base.ctx, addr);
-+	set_reg_field_value(value, 1,
-+			SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+}
-+
-+static void program_filter(
-+	struct dce110_transform *xfm110,
-+	enum ram_filter_type filter_type,
-+	struct scaler_filter_params *scl_filter_params,
-+	uint32_t *coeffs,
-+	uint32_t coeffs_num)
-+{
-+	uint32_t phase = 0;
-+	uint32_t array_idx = 0;
-+	uint32_t pair = 0;
-+
-+	uint32_t taps_pairs = (scl_filter_params->taps + 1) / 2;
-+	uint32_t phases_to_program = scl_filter_params->phases / 2 + 1;
-+
-+	uint32_t i;
-+	uint32_t addr;
-+	uint32_t select_addr;
-+	uint32_t select;
-+	uint32_t data;
-+	/* We need to disable power gating on coeff memory to do programming */
-+
-+	uint32_t pwr_ctrl_orig;
-+	uint32_t pwr_ctrl_off;
-+
-+	addr = DCFE_REG(mmDCFE_MEM_PWR_CTRL);
-+	pwr_ctrl_orig = dal_read_reg(xfm110->base.ctx, addr);
-+	pwr_ctrl_off = pwr_ctrl_orig;
-+	set_reg_field_value(
-+		pwr_ctrl_off,
-+		1,
-+		DCFE_MEM_PWR_CTRL,
-+		SCL_COEFF_MEM_PWR_DIS);
-+	dal_write_reg(xfm110->base.ctx, addr, pwr_ctrl_off);
-+
-+	addr = DCFE_REG(mmDCFE_MEM_PWR_STATUS);
-+	/* Wait to disable gating: */
-+	for (i = 0;
-+		i < 10 &&
-+		get_reg_field_value(
-+			dal_read_reg(xfm110->base.ctx, addr),
-+			DCFE_MEM_PWR_STATUS,
-+			SCL_COEFF_MEM_PWR_STATE);
-+		i++)
-+		dc_service_delay_in_microseconds(xfm110->base.ctx, 1);
-+
-+	ASSERT(i < 10);
-+
-+	select_addr = SCL_REG(mmSCL_COEF_RAM_SELECT);
-+	select = dal_read_reg(xfm110->base.ctx, select_addr);
-+
-+	set_reg_field_value(
-+		select,
-+		filter_type,
-+		SCL_COEF_RAM_SELECT,
-+		SCL_C_RAM_FILTER_TYPE);
-+	set_reg_field_value(
-+		select,
-+		0,
-+		SCL_COEF_RAM_SELECT,
-+		SCL_C_RAM_TAP_PAIR_IDX);
-+	set_reg_field_value(
-+		select,
-+		0,
-+		SCL_COEF_RAM_SELECT,
-+		SCL_C_RAM_PHASE);
-+
-+	data = 0;
-+
-+	for (phase = 0; phase < phases_to_program; phase++) {
-+		/* we always program N/2 + 1 phases, total phases N, but N/2-1
-+		 * are just mirror phase 0 is unique and phase N/2 is unique
-+		 * if N is even
-+		 */
-+
-+		set_reg_field_value(
-+			select,
-+			phase,
-+			SCL_COEF_RAM_SELECT,
-+			SCL_C_RAM_PHASE);
-+
-+		for (pair = 0; pair < taps_pairs; pair++) {
-+			set_reg_field_value(
-+				select,
-+				pair,
-+				SCL_COEF_RAM_SELECT,
-+				SCL_C_RAM_TAP_PAIR_IDX);
-+			dal_write_reg(xfm110->base.ctx, select_addr, select);
-+
-+			/* even tap write enable */
-+			set_reg_field_value(
-+				data,
-+				1,
-+				SCL_COEF_RAM_TAP_DATA,
-+				SCL_C_RAM_EVEN_TAP_COEF_EN);
-+			/* even tap data */
-+			set_reg_field_value(
-+				data,
-+				coeffs[array_idx],
-+				SCL_COEF_RAM_TAP_DATA,
-+				SCL_C_RAM_EVEN_TAP_COEF);
-+
-+			/* if we have odd number of taps and the last pair is
-+			 * here then we do not need to program
-+			 */
-+			if (scl_filter_params->taps % 2 &&
-+				pair == taps_pairs - 1) {
-+				/* odd tap write disable */
-+				set_reg_field_value(
-+					data,
-+					0,
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF_EN);
-+				set_reg_field_value(
-+					data,
-+					0,
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF);
-+				array_idx += 1;
-+			} else {
-+				/* odd tap write enable */
-+				set_reg_field_value(
-+					data,
-+					1,
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF_EN);
-+				/* dbg_val: 0x1000 / sclFilterParams->taps; */
-+				set_reg_field_value(
-+					data,
-+					coeffs[array_idx + 1],
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF);
-+
-+				array_idx += 2;
-+			}
-+
-+			dal_write_reg(
-+				xfm110->base.ctx,
-+				SCL_REG(mmSCL_COEF_RAM_TAP_DATA),
-+				data);
-+		}
-+	}
-+
-+	ASSERT(coeffs_num == array_idx);
-+
-+	/* reset the power gating register */
-+	dal_write_reg(
-+		xfm110->base.ctx,
-+		DCFE_REG(mmDCFE_MEM_PWR_CTRL),
-+		pwr_ctrl_orig);
-+
-+	set_coeff_update_complete(xfm110);
-+}
-+
-+/*
-+ *
-+ * Populates an array with filter coefficients in 1.1.12 fixed point form
-+*/
-+static bool get_filter_coefficients(
-+	struct dce110_transform *xfm110,
-+	uint32_t taps,
-+	uint32_t **data_tab,
-+	uint32_t *data_size)
-+{
-+	uint32_t num = 0;
-+	uint32_t i;
-+	const struct fixed31_32 *filter =
-+		dal_scaler_filter_get(
-+			xfm110->base.filter,
-+			data_tab,
-+			&num);
-+	uint32_t *data_row;
-+
-+	if (!filter) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+	data_row = *data_tab;
-+
-+	for (i = 0; i < num; ++i) {
-+		/* req. format sign fixed 1.1.12, the values are always between
-+		 * [-1; 1]
-+		 *
-+		 * Each phase is mirrored as follows :
-+		 * 0 : Phase 0
-+		 * 1 : Phase 1 or Phase 64 - 1 / 128 - 1
-+		 * N : Phase N or Phase 64 - N / 128 - N
-+		 *
-+		 * Convert from Fixed31_32 to 1.1.12 by using floor on value
-+		 * shifted by number of required fractional bits(12)
-+		 */
-+		struct fixed31_32 value = filter[i];
-+
-+		data_row[i] =
-+			dal_fixed31_32_floor(dal_fixed31_32_shl(value, 12)) &
-+			0x3FFC;
-+	}
-+	*data_size = num;
-+
-+	return true;
-+}
-+
-+static bool program_multi_taps_filter(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data,
-+	bool horizontal)
-+{
-+	struct scaler_filter_params filter_params;
-+	enum ram_filter_type filter_type;
-+	uint32_t src_size;
-+	uint32_t dst_size;
-+
-+	uint32_t *filter_data = NULL;
-+	uint32_t filter_data_size = 0;
-+
-+	/* 16 phases total for DCE11 */
-+	filter_params.phases = 16;
-+
-+	if (horizontal) {
-+		filter_params.taps = data->taps.h_taps;
-+		filter_params.sharpness = data->h_sharpness;
-+		filter_params.flags.bits.HORIZONTAL = 1;
-+
-+		src_size = data->viewport.width;
-+		dst_size =
-+			dal_fixed31_32_floor(
-+				dal_fixed31_32_div(
-+					dal_fixed31_32_from_int(
-+						data->viewport.width),
-+					data->ratios->horz));
-+
-+		filter_type = FILTER_TYPE_RGB_Y_HORIZONTAL;
-+	} else {
-+		filter_params.taps = data->taps.v_taps;
-+		filter_params.sharpness = data->v_sharpness;
-+		filter_params.flags.bits.HORIZONTAL = 0;
-+
-+		src_size = data->viewport.height;
-+		dst_size =
-+			dal_fixed31_32_floor(
-+				dal_fixed31_32_div(
-+					dal_fixed31_32_from_int(
-+						data->viewport.height),
-+					data->ratios->vert));
-+
-+		filter_type = FILTER_TYPE_RGB_Y_VERTICAL;
-+	}
-+
-+	/* 1. Generate the coefficients */
-+	if (!dal_scaler_filter_generate(
-+		xfm110->base.filter,
-+		&filter_params,
-+		src_size,
-+		dst_size))
-+		return false;
-+
-+	/* 2. Convert coefficients to fixed point format 1.12 (note coeff.
-+	 * could be negative(!) and  range is [ from -1 to 1 ]) */
-+	if (!get_filter_coefficients(
-+		xfm110,
-+		filter_params.taps,
-+		&filter_data,
-+		&filter_data_size))
-+		return false;
-+
-+	/* 3. Program the filter */
-+	program_filter(
-+		xfm110,
-+		filter_type,
-+		&filter_params,
-+		filter_data,
-+		filter_data_size);
-+
-+	/* 4. Program the alpha if necessary */
-+	if (data->flags.bits.SHOULD_PROGRAM_ALPHA) {
-+		if (horizontal)
-+			filter_type = FILTER_TYPE_ALPHA_HORIZONTAL;
-+		else
-+			filter_type = FILTER_TYPE_ALPHA_VERTICAL;
-+
-+		program_filter(
-+			xfm110,
-+			filter_type,
-+			&filter_params,
-+			filter_data,
-+			filter_data_size);
-+	}
-+
-+	return true;
-+}
-+
-+static void program_viewport(
-+	struct dce110_transform *xfm110,
-+	const struct rect *view_port)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+
-+	addr = SCL_REG(mmVIEWPORT_START);
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		view_port->x,
-+		VIEWPORT_START,
-+		VIEWPORT_X_START);
-+	set_reg_field_value(
-+		value,
-+		view_port->y,
-+		VIEWPORT_START,
-+		VIEWPORT_Y_START);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = SCL_REG(mmVIEWPORT_SIZE);
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		view_port->height,
-+		VIEWPORT_SIZE,
-+		VIEWPORT_HEIGHT);
-+	set_reg_field_value(
-+		value,
-+		view_port->width,
-+		VIEWPORT_SIZE,
-+		VIEWPORT_WIDTH);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* TODO: add stereo support */
-+}
-+
-+static void calculate_inits(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data,
-+	struct scl_ratios_inits *inits)
-+{
-+	struct fixed31_32 h_init;
-+	struct fixed31_32 v_init;
-+	struct fixed31_32 v_init_bot;
-+
-+	inits->bottom_enable = 0;
-+	inits->h_int_scale_ratio =
-+		dal_fixed31_32_u2d19(data->ratios->horz) << 5;
-+	inits->v_int_scale_ratio =
-+		dal_fixed31_32_u2d19(data->ratios->vert) << 5;
-+
-+	h_init =
-+		dal_fixed31_32_div_int(
-+			dal_fixed31_32_add(
-+				data->ratios->horz,
-+				dal_fixed31_32_from_int(data->taps.h_taps + 1)),
-+				2);
-+	inits->h_init.integer = dal_fixed31_32_floor(h_init);
-+	inits->h_init.fraction = dal_fixed31_32_u0d19(h_init) << 5;
-+
-+	v_init =
-+		dal_fixed31_32_div_int(
-+			dal_fixed31_32_add(
-+				data->ratios->vert,
-+				dal_fixed31_32_from_int(data->taps.v_taps + 1)),
-+				2);
-+	inits->v_init.integer = dal_fixed31_32_floor(v_init);
-+	inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
-+
-+	if (data->flags.bits.INTERLACED) {
-+		v_init_bot =
-+			dal_fixed31_32_add(
-+				dal_fixed31_32_div_int(
-+					dal_fixed31_32_add(
-+						data->ratios->vert,
-+						dal_fixed31_32_from_int(
-+							data->taps.v_taps + 1)),
-+					2),
-+				data->ratios->vert);
-+		inits->v_init_bottom.integer = dal_fixed31_32_floor(v_init_bot);
-+		inits->v_init_bottom.fraction =
-+			dal_fixed31_32_u0d19(v_init_bot) << 5;
-+
-+		inits->bottom_enable = 1;
-+	}
-+}
-+
-+static void program_scl_ratios_inits(
-+	struct dce110_transform *xfm110,
-+	struct scl_ratios_inits *inits)
-+{
-+	uint32_t addr = SCL_REG(mmSCL_HORZ_FILTER_SCALE_RATIO);
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio,
-+		SCL_HORZ_FILTER_SCALE_RATIO,
-+		SCL_H_SCALE_RATIO);
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+
-+	addr = SCL_REG(mmSCL_VERT_FILTER_SCALE_RATIO);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio,
-+		SCL_VERT_FILTER_SCALE_RATIO,
-+		SCL_V_SCALE_RATIO);
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+
-+	addr = SCL_REG(mmSCL_HORZ_FILTER_INIT);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_init.integer,
-+		SCL_HORZ_FILTER_INIT,
-+		SCL_H_INIT_INT);
-+	set_reg_field_value(
-+		value,
-+		inits->h_init.fraction,
-+		SCL_HORZ_FILTER_INIT,
-+		SCL_H_INIT_FRAC);
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+
-+	addr = SCL_REG(mmSCL_VERT_FILTER_INIT);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_init.integer,
-+		SCL_VERT_FILTER_INIT,
-+		SCL_V_INIT_INT);
-+	set_reg_field_value(
-+		value,
-+		inits->v_init.fraction,
-+		SCL_VERT_FILTER_INIT,
-+		SCL_V_INIT_FRAC);
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+
-+	if (inits->bottom_enable) {
-+		addr = SCL_REG(mmSCL_VERT_FILTER_INIT_BOT);
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			inits->v_init_bottom.integer,
-+			SCL_VERT_FILTER_INIT_BOT,
-+			SCL_V_INIT_INT_BOT);
-+		set_reg_field_value(
-+			value,
-+			inits->v_init_bottom.fraction,
-+			SCL_VERT_FILTER_INIT_BOT,
-+			SCL_V_INIT_FRAC_BOT);
-+		dal_write_reg(xfm110->base.ctx, addr, value);
-+	}
-+
-+	addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		0,
-+		SCL_AUTOMATIC_MODE_CONTROL,
-+		SCL_V_CALC_AUTO_RATIO_EN);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		SCL_AUTOMATIC_MODE_CONTROL,
-+		SCL_H_CALC_AUTO_RATIO_EN);
-+	dal_write_reg(xfm110->base.ctx, addr, value);
-+}
-+
-+static void get_viewport(
-+		struct dce110_transform *xfm110,
-+		struct rect *current_view_port)
-+{
-+	uint32_t value_start;
-+	uint32_t value_size;
-+
-+	if (current_view_port == NULL)
-+		return;
-+
-+	value_start = dal_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_START));
-+	value_size = dal_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_SIZE));
-+
-+	current_view_port->x = get_reg_field_value(
-+			value_start,
-+			VIEWPORT_START,
-+			VIEWPORT_X_START);
-+	current_view_port->y = get_reg_field_value(
-+			value_start,
-+			VIEWPORT_START,
-+			VIEWPORT_Y_START);
-+	current_view_port->height = get_reg_field_value(
-+			value_size,
-+			VIEWPORT_SIZE,
-+			VIEWPORT_HEIGHT);
-+	current_view_port->width = get_reg_field_value(
-+			value_size,
-+			VIEWPORT_SIZE,
-+			VIEWPORT_WIDTH);
-+}
-+
-+
-+bool dce110_transform_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool is_scaling_required;
-+	struct dc_context *ctx = xfm->ctx;
-+
-+	{
-+		uint32_t addr = SCL_REG(mmSCL_BYPASS_CONTROL);
-+		uint32_t value = dal_read_reg(xfm->ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			SCL_BYPASS_CONTROL,
-+			SCL_BYPASS_MODE);
-+		dal_write_reg(xfm->ctx, addr, value);
-+	}
-+
-+	disable_enhanced_sharpness(xfm110);
-+
-+	/* 3. Program overscan */
-+	program_overscan(xfm110, &data->overscan);
-+
-+	/* 4. Program taps and configuration */
-+	is_scaling_required = setup_scaling_configuration(xfm110, data);
-+	if (is_scaling_required) {
-+		/* 5. Calculate and program ratio, filter initialization */
-+		struct scl_ratios_inits inits = { 0 };
-+
-+		calculate_inits(xfm110, data, &inits);
-+
-+		program_scl_ratios_inits(xfm110, &inits);
-+
-+		/* 6. Program vertical filters */
-+		if (data->taps.v_taps > 2) {
-+			program_two_taps_filter(xfm110, false, true);
-+
-+			if (!program_multi_taps_filter(xfm110, data, false)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed vertical taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter(xfm110, true, true);
-+
-+		/* 7. Program horizontal filters */
-+		if (data->taps.h_taps > 2) {
-+			program_two_taps_filter(xfm110, false, false);
-+
-+			if (!program_multi_taps_filter(xfm110, data, true)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed horizontal taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter(xfm110, true, false);
-+	}
-+
-+	return true;
-+}
-+
-+void dce110_transform_set_scaler_bypass(struct transform *xfm)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	uint32_t sclv_mode;
-+
-+	disable_enhanced_sharpness(xfm110);
-+
-+	sclv_mode = dal_read_reg(xfm->ctx, SCL_REG(mmSCL_MODE));
-+	set_reg_field_value(sclv_mode, 0, SCL_MODE, SCL_MODE);
-+	set_reg_field_value(sclv_mode, 0, SCL_MODE, SCL_PSCL_EN);
-+	dal_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
-+}
-+
-+bool dce110_transform_update_viewport(
-+	struct transform *xfm,
-+	const struct rect *view_port,
-+	bool is_fbc_attached)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool program_req = false;
-+	struct rect current_view_port;
-+
-+	if (view_port == NULL)
-+		return program_req;
-+
-+	get_viewport(xfm110, &current_view_port);
-+
-+	if (current_view_port.x != view_port->x ||
-+			current_view_port.y != view_port->y ||
-+			current_view_port.height != view_port->height ||
-+			current_view_port.width != view_port->width)
-+		program_req = true;
-+
-+	if (program_req) {
-+		/*underlay viewport is programmed with scaler
-+		 *program_viewport function pointer is not exposed*/
-+		program_viewport(xfm110, view_port);
-+	}
-+
-+	return program_req;
-+}
-+
-+void dce110_transform_set_scaler_filter(
-+	struct transform *xfm,
-+	struct scaler_filter *filter)
-+{
-+	xfm->filter = filter;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-new file mode 100644
-index 0000000..bcf20bb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-@@ -0,0 +1,531 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_transform.h"
-+
-+#define NOT_IMPLEMENTED()  DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_CONTROLLER,\
-+			"TRANSFORM SCALER:%s()\n", __func__)
-+
-+/*
-+*****************************************************************************
-+*  Function: calculateViewport
-+*
-+*  @brief
-+*     Calculates all of the data required to set the viewport
-+*
-+*  @param [in]  pData:      scaler settings data
-+*  @param [out] pLumaVp:    luma viewport information
-+*  @param [out] pChromaVp:  chroma viewport information
-+*  @param [out] srcResCx2:  source chroma resolution times 2  - for multi-taps
-+*
-+*****************************************************************************
-+*/
-+static void calculate_viewport(
-+		const struct scaler_data *scl_data,
-+		struct rect *luma_viewport,
-+		struct rect *chroma_viewport)
-+{
-+	/*Do not set chroma vp for rgb444 pixel format*/
-+	luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2;
-+	luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2;
-+	luma_viewport->width =
-+		scl_data->viewport.width - scl_data->viewport.width % 2;
-+	luma_viewport->height =
-+		scl_data->viewport.height - scl_data->viewport.height % 2;
-+
-+
-+	if (scl_data->dal_pixel_format == PIXEL_FORMAT_422BPP16) {
-+		luma_viewport->width += luma_viewport->width % 2;
-+
-+		chroma_viewport->x = luma_viewport->x / 2;
-+		chroma_viewport->width = luma_viewport->width / 2;
-+	} else if (scl_data->dal_pixel_format == PIXEL_FORMAT_420BPP12) {
-+		luma_viewport->height += luma_viewport->height % 2;
-+		luma_viewport->width += luma_viewport->width % 2;
-+		/*for 420 video chroma is 1/4 the area of luma, scaled
-+		 *vertically and horizontally
-+		 */
-+		chroma_viewport->x = luma_viewport->x / 2;
-+		chroma_viewport->y = luma_viewport->y / 2;
-+		chroma_viewport->height = luma_viewport->height / 2;
-+		chroma_viewport->width = luma_viewport->width / 2;
-+	}
-+}
-+
-+
-+static void program_viewport(
-+	struct dce110_transform *xfm110,
-+	struct rect *luma_view_port,
-+	struct rect *chroma_view_port)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+
-+	if (luma_view_port->width != 0 && luma_view_port->height != 0) {
-+		addr = mmSCLV_VIEWPORT_START;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->x,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_X_START);
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->y,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_Y_START);
-+		dal_write_reg(ctx, addr, value);
-+
-+		addr = mmSCLV_VIEWPORT_SIZE;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->height,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_HEIGHT);
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->width,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_WIDTH);
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	if (chroma_view_port->width != 0 && chroma_view_port->height != 0) {
-+		addr = mmSCLV_VIEWPORT_START_C;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->x,
-+			SCLV_VIEWPORT_START_C,
-+			VIEWPORT_X_START_C);
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->y,
-+			SCLV_VIEWPORT_START_C,
-+			VIEWPORT_Y_START_C);
-+		dal_write_reg(ctx, addr, value);
-+
-+		addr = mmSCLV_VIEWPORT_SIZE_C;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->height,
-+			SCLV_VIEWPORT_SIZE_C,
-+			VIEWPORT_HEIGHT_C);
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->width,
-+			SCLV_VIEWPORT_SIZE_C,
-+			VIEWPORT_WIDTH_C);
-+		dal_write_reg(ctx, addr, value);
-+	}
-+	/* TODO: add stereo support */
-+}
-+
-+
-+/* Until and For MPO video play story, to reduce time for implementation,
-+ * below limits are applied for now: 2_TAPS only
-+ * Use auto-calculated filter values
-+ * Following routines will be empty for now:
-+ *
-+ * programSclRatiosInits -- calcualate scaler ratio manually
-+ * calculateInits --- calcualate scaler ratio manually
-+ * programFilter -- multi-taps
-+ * GetOptimalNumberOfTaps -- will hard coded to 2 TAPS
-+ * GetNextLowerNumberOfTaps -- will hard coded to 2TAPS
-+ * validateRequestedScaleRatio - used by GetOptimalNumberOfTaps internally
-+ */
-+
-+/**
-+* Function:
-+* void setup_scaling_configuration
-+*
-+* Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
-+* Input:   data
-+*
-+* Output:
-+   void
-+*/
-+static bool setup_scaling_configuration(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data)
-+{
-+	bool is_scaling_needed = false;
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+
-+	if (data->taps.h_taps + data->taps.v_taps > 2) {
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE);
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN);
-+		is_scaling_needed = true;
-+	} else {
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
-+	}
-+
-+	if (data->taps.h_taps_c + data->taps.v_taps_c > 2) {
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C);
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C);
-+		is_scaling_needed = true;
-+	} else if (data->dal_pixel_format != PIXEL_FORMAT_420BPP12 &&
-+		data->dal_pixel_format != PIXEL_FORMAT_422BPP16) {
-+		set_reg_field_value(
-+			value,
-+			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
-+			SCLV_MODE,
-+			SCL_MODE_C);
-+		set_reg_field_value(
-+			value,
-+			get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN),
-+			SCLV_MODE,
-+			SCL_PSCL_EN_C);
-+	} else {
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
-+	}
-+	dal_write_reg(ctx, mmSCLV_MODE, value);
-+
-+	{
-+		value = dal_read_reg(ctx, mmSCLV_TAP_CONTROL);
-+
-+		set_reg_field_value(value, data->taps.h_taps - 1,
-+				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+
-+		set_reg_field_value(value, data->taps.v_taps - 1,
-+				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+
-+		set_reg_field_value(value, data->taps.h_taps_c - 1,
-+				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C);
-+
-+		set_reg_field_value(value, data->taps.v_taps_c - 1,
-+				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
-+
-+		dal_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
-+	}
-+
-+	{
-+		/* we can ignore this register because we are ok with hw
-+		 * default 0 -- change to 1 according to dal2 code*/
-+		value = dal_read_reg(ctx, mmSCLV_CONTROL);
-+		 /* 0 - Replaced out of bound pixels with black pixel
-+		  * (or any other required color) */
-+		set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
-+
-+		/* 1 - Replaced out of bound pixels with the edge pixel. */
-+		dal_write_reg(ctx, mmSCLV_CONTROL, value);
-+	}
-+
-+	return is_scaling_needed;
-+}
-+
-+/**
-+* Function:
-+* void program_overscan
-+*
-+* Purpose: Programs overscan border
-+* Input:   overscan
-+*
-+* Output:
-+   void
-+*/
-+static void program_overscan(
-+		struct dce110_transform *xfm110,
-+		const struct overscan_info *overscan)
-+{
-+	uint32_t overscan_left_right = 0;
-+	uint32_t overscan_top_bottom = 0;
-+
-+	set_reg_field_value(overscan_left_right, overscan->left,
-+		SCLV_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-+
-+	set_reg_field_value(overscan_left_right, overscan->right,
-+		SCLV_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->top,
-+		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->bottom,
-+		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			mmSCLV_EXT_OVERSCAN_LEFT_RIGHT,
-+			overscan_left_right);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			mmSCLV_EXT_OVERSCAN_TOP_BOTTOM,
-+			overscan_top_bottom);
-+}
-+/*
-+static void setup_auto_scaling(struct dce110_transform *xfm110)
-+{
-+	uint32_t value = 0;
-+	set_reg_field_value(value, 1, SCLV_AUTOMATIC_MODE_CONTROL,
-+			SCL_V_CALC_AUTO_RATIO_EN);
-+	set_reg_field_value(value, 1, SCLV_AUTOMATIC_MODE_CONTROL,
-+			SCL_H_CALC_AUTO_RATIO_EN);
-+	dal_write_reg(xfm->ctx,
-+			xfm->regs[IDX_SCL_AUTOMATIC_MODE_CONTROL],
-+			value);
-+}
-+*/
-+
-+static void program_two_taps_filter_horz(
-+	struct dce110_transform *xfm110,
-+	bool hardcode_coff)
-+{
-+	uint32_t value = 0;
-+
-+	if (hardcode_coff)
-+		set_reg_field_value(
-+				value,
-+				1,
-+				SCLV_HORZ_FILTER_CONTROL,
-+				SCL_H_2TAP_HARDCODE_COEF_EN);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			mmSCLV_HORZ_FILTER_CONTROL,
-+			value);
-+}
-+
-+static void program_two_taps_filter_vert(
-+	struct dce110_transform *xfm110,
-+	bool hardcode_coff)
-+{
-+	uint32_t value = 0;
-+
-+	if (hardcode_coff)
-+		set_reg_field_value(value, 1, SCLV_VERT_FILTER_CONTROL,
-+				SCL_V_2TAP_HARDCODE_COEF_EN);
-+
-+	dal_write_reg(xfm110->base.ctx,
-+			mmSCLV_VERT_FILTER_CONTROL,
-+			value);
-+}
-+
-+static void set_coeff_update_complete(
-+		struct dce110_transform *xfm110)
-+{
-+	/*TODO: Until now, only scaler bypass, up-scaler 2 -TAPS coeff auto
-+	 * calculation are implemented. Coefficient RAM is not used
-+	 * Do not check this flag yet
-+	 */
-+
-+	/*uint32_t value;
-+	uint32_t addr = xfm->regs[IDX_SCL_UPDATE];
-+
-+	value = dal_read_reg(xfm->ctx, addr);
-+	set_reg_field_value(value, 0,
-+			SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
-+	dal_write_reg(xfm->ctx, addr, value);*/
-+}
-+
-+static bool program_multi_taps_filter(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data,
-+	bool horizontal)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+
-+	NOT_IMPLEMENTED();
-+	return false;
-+}
-+
-+static void calculate_inits(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data,
-+	struct sclv_ratios_inits *inits,
-+	struct rect *luma_viewport,
-+	struct rect *chroma_viewport)
-+{
-+	if (data->dal_pixel_format == PIXEL_FORMAT_420BPP12 ||
-+		data->dal_pixel_format == PIXEL_FORMAT_422BPP16)
-+		inits->chroma_enable = true;
-+
-+	/* TODO: implement rest of this function properly */
-+	if (inits->chroma_enable) {
-+		inits->h_int_scale_ratio_luma = 0x1000000;
-+		inits->v_int_scale_ratio_luma = 0x1000000;
-+		inits->h_int_scale_ratio_chroma = 0x800000;
-+		inits->v_int_scale_ratio_chroma = 0x800000;
-+	}
-+}
-+
-+static void program_scl_ratios_inits(
-+	struct dce110_transform *xfm110,
-+	struct sclv_ratios_inits *inits)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio_luma,
-+		SCLV_HORZ_FILTER_SCALE_RATIO,
-+		SCL_H_SCALE_RATIO);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_SCALE_RATIO;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio_luma,
-+		SCLV_VERT_FILTER_SCALE_RATIO,
-+		SCL_V_SCALE_RATIO);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio_chroma,
-+		SCLV_HORZ_FILTER_SCALE_RATIO_C,
-+		SCL_H_SCALE_RATIO_C);
-+	dal_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C;
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio_chroma,
-+		SCLV_VERT_FILTER_SCALE_RATIO_C,
-+		SCL_V_SCALE_RATIO_C);
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_transform_underlay_set_scalerv_bypass(struct transform *xfm)
-+{
-+	uint32_t addr = mmSCLV_MODE;
-+	uint32_t value = dal_read_reg(xfm->ctx, addr);
-+
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
-+	dal_write_reg(xfm->ctx, addr, value);
-+}
-+
-+bool dce110_transform_underlay_is_scaling_enabled(struct transform *xfm)
-+{
-+	uint32_t value = dal_read_reg(xfm->ctx, mmSCLV_MODE);
-+	uint8_t scl_mode = get_reg_field_value(value, SCLV_MODE, SCL_MODE);
-+
-+	return scl_mode == 0;
-+}
-+
-+/* TODO: sync this one with DAL2 */
-+bool dce110_transform_underlay_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool is_scaling_required;
-+	struct rect luma_viewport = {0};
-+	struct rect chroma_viewport = {0};
-+	struct dc_context *ctx = xfm->ctx;
-+
-+	/* 1. Lock Scaler TODO: enable?*/
-+	/*set_scaler_update_lock(xfm, true);*/
-+
-+	/* 2. Calculate viewport, viewport programming should happen after init
-+	 * calculations as they may require an adjustment in the viewport.
-+	 */
-+
-+	calculate_viewport(data, &luma_viewport, &chroma_viewport);
-+
-+	/* 3. Program overscan */
-+	program_overscan(xfm110, &data->overscan);
-+
-+	/* 4. Program taps and configuration */
-+	is_scaling_required = setup_scaling_configuration(xfm110, data);
-+
-+	if (is_scaling_required) {
-+		/* 5. Calculate and program ratio, filter initialization */
-+
-+		struct sclv_ratios_inits inits = { 0 };
-+
-+		calculate_inits(
-+			xfm110,
-+			data,
-+			&inits,
-+			&luma_viewport,
-+			&chroma_viewport);
-+
-+		program_scl_ratios_inits(xfm110, &inits);
-+
-+		/*scaler coeff of 2-TAPS use hardware auto calculated value*/
-+
-+		/* 6. Program vertical filters */
-+		if (data->taps.v_taps > 2) {
-+			program_two_taps_filter_vert(xfm110, false);
-+
-+			if (!program_multi_taps_filter(xfm110, data, false)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed vertical taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter_vert(xfm110, true);
-+
-+		/* 7. Program horizontal filters */
-+		if (data->taps.h_taps > 2) {
-+			program_two_taps_filter_horz(xfm110, false);
-+
-+			if (!program_multi_taps_filter(xfm110, data, true)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed horizontal taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter_horz(xfm110, true);
-+	}
-+
-+	/* 8. Program the viewport */
-+	if (data->flags.bits.SHOULD_PROGRAM_VIEWPORT)
-+		program_viewport(xfm110, &luma_viewport, &chroma_viewport);
-+
-+	/* 9. Unlock the Scaler TODO: enable?*/
-+	/* Every call to "set_scaler_update_lock(xfm, TRUE)"
-+	 * must have a corresponding call to
-+	 * "set_scaler_update_lock(xfm, FALSE)" */
-+	/*set_scaler_update_lock(xfm, false);*/
-+
-+	/* TODO: investigate purpose/need of SHOULD_UNLOCK */
-+	if (data->flags.bits.SHOULD_UNLOCK == false)
-+		set_coeff_update_complete(xfm110);
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/Makefile b/drivers/gpu/drm/amd/dal/dc/dcs/Makefile
-new file mode 100644
-index 0000000..a266942
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'gpu' sub-component of DAL.
-+# It provides the control and status of HW adapter resources,
-+# that are global for the ASIC and sharable between pipes.
-+
-+DCS = ddc_service.o ddc_i2caux_helper.o
-+
-+AMD_DAL_DCS = $(addprefix $(AMDDALPATH)/dc/dcs/,$(DCS))
-+
-+AMD_DAL_FILES += $(AMD_DAL_DCS)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-new file mode 100644
-index 0000000..a4442d6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-@@ -0,0 +1,159 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "ddc_i2caux_helper.h"
-+#include "include/ddc_service_types.h"
-+#include "include/vector.h"
-+
-+struct i2c_payloads {
-+	struct vector payloads;
-+};
-+
-+struct aux_payloads {
-+	struct vector payloads;
-+};
-+
-+struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count)
-+{
-+	struct i2c_payloads *payloads;
-+
-+	payloads = dc_service_alloc(ctx, sizeof(struct i2c_payloads));
-+
-+	if (!payloads)
-+		return NULL;
-+
-+	if (dal_vector_construct(
-+		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
-+		return payloads;
-+
-+	dc_service_free(ctx, payloads);
-+	return NULL;
-+
-+}
-+
-+struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
-+{
-+	return (struct i2c_payload *)p->payloads.container;
-+}
-+
-+uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
-+{
-+	return p->payloads.count;
-+}
-+
-+void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
-+{
-+	if (!p || !*p)
-+		return;
-+	dal_vector_destruct(&(*p)->payloads);
-+	dc_service_free((*p)->payloads.ctx, *p);
-+	*p = NULL;
-+
-+}
-+
-+struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
-+{
-+	struct aux_payloads *payloads;
-+
-+	payloads = dc_service_alloc(ctx, sizeof(struct aux_payloads));
-+
-+	if (!payloads)
-+		return NULL;
-+
-+	if (dal_vector_construct(
-+		&payloads->payloads, ctx, count, sizeof(struct aux_payloads)))
-+		return payloads;
-+
-+	dc_service_free(ctx, payloads);
-+	return NULL;
-+}
-+
-+struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
-+{
-+	return (struct aux_payload *)p->payloads.container;
-+}
-+
-+uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
-+{
-+	return p->payloads.count;
-+}
-+
-+
-+void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
-+{
-+	if (!p || !*p)
-+		return;
-+
-+	dal_vector_destruct(&(*p)->payloads);
-+	dc_service_free((*p)->payloads.ctx, *p);
-+	*p = NULL;
-+}
-+
-+#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
-+
-+void dal_ddc_i2c_payloads_add(
-+	struct i2c_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write)
-+{
-+	uint32_t payload_size = EDID_SEGMENT_SIZE;
-+	uint32_t pos;
-+
-+	for (pos = 0; pos < len; pos += payload_size) {
-+		struct i2c_payload payload = {
-+			.write = write,
-+			.address = address,
-+			.length = DDC_MIN(payload_size, len - pos),
-+			.data = data + pos };
-+		dal_vector_append(&payloads->payloads, &payload);
-+	}
-+
-+}
-+
-+void dal_ddc_aux_payloads_add(
-+	struct aux_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write)
-+{
-+	uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
-+	uint32_t pos;
-+
-+	for (pos = 0; pos < len; pos += payload_size) {
-+		struct aux_payload payload = {
-+			.i2c_over_aux = true,
-+			.write = write,
-+			.address = address,
-+			.length = DDC_MIN(payload_size, len - pos),
-+			.data = data + pos };
-+		dal_vector_append(&payloads->payloads, &payload);
-+	}
-+}
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
-new file mode 100644
-index 0000000..bb628cd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
-@@ -0,0 +1,60 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2CAUX_HELPER_H__
-+#define __DAL_I2CAUX_HELPER_H__
-+
-+#include "include/i2caux_interface.h"
-+
-+#define EDID_SEGMENT_SIZE 256
-+
-+struct i2c_payloads;
-+struct aux_payloads;
-+
-+struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count);
-+struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p);
-+uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p);
-+void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p);
-+
-+struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count);
-+struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p);
-+uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p);
-+void dal_ddc_aux_payloads_destroy(struct aux_payloads **p);
-+
-+void dal_ddc_i2c_payloads_add(
-+	struct i2c_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write);
-+
-+void dal_ddc_aux_payloads_add(
-+	struct aux_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write);
-+
-+#endif /* __DAL_I2CAUX_HELPER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-new file mode 100644
-index 0000000..5436704
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-@@ -0,0 +1,1034 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/adapter_service_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/ddc_service_interface.h"
-+#include "include/ddc_service_types.h"
-+#include "include/grph_object_id.h"
-+#include "include/dpcd_defs.h"
-+#include "include/logger_interface.h"
-+#include "ddc_i2caux_helper.h"
-+#include "ddc_service.h"
-+#include "dal_services_types.h"
-+
-+#define AUX_POWER_UP_WA_DELAY 500
-+#define I2C_OVER_AUX_DEFER_WA_DELAY 70
-+
-+/* CV smart dongle slave address for retrieving supported HDTV modes*/
-+#define CV_SMART_DONGLE_ADDRESS 0x20
-+/* DVI-HDMI dongle slave address for retrieving dongle signature*/
-+#define DVI_HDMI_DONGLE_ADDRESS 0x68
-+static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
-+struct dvi_hdmi_dongle_signature_data {
-+	int8_t vendor[3];/* "AMD" */
-+	uint8_t version[2];
-+	uint8_t size;
-+	int8_t id[11];/* "6140063500G"*/
-+};
-+/* DP-HDMI dongle slave address for retrieving dongle signature*/
-+#define DP_HDMI_DONGLE_ADDRESS 0x40
-+static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
-+#define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
-+
-+struct dp_hdmi_dongle_signature_data {
-+	int8_t id[15];/* "DP-HDMI ADAPTOR"*/
-+	uint8_t eot;/* end of transmition '\x4' */
-+};
-+
-+/* Address range from 0x00 to 0x1F.*/
-+#define DP_ADAPTOR_TYPE2_SIZE 0x20
-+#define DP_ADAPTOR_TYPE2_REG_ID 0x10
-+#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
-+/* Identifies adaptor as Dual-mode adaptor */
-+#define DP_ADAPTOR_TYPE2_ID 0xA0
-+/* MHz*/
-+#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
-+/* MHz*/
-+#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
-+/* kHZ*/
-+#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
-+/* kHZ*/
-+#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000
-+
-+#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
-+
-+enum edid_read_result {
-+	EDID_READ_RESULT_EDID_MATCH = 0,
-+	EDID_READ_RESULT_EDID_MISMATCH,
-+	EDID_READ_RESULT_CHECKSUM_READ_ERR,
-+	EDID_READ_RESULT_VENDOR_READ_ERR
-+};
-+
-+/* SCDC Address defines (HDMI 2.0)*/
-+#define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
-+#define HDMI_SCDC_ADDRESS  0x54
-+#define HDMI_SCDC_SINK_VERSION 0x01
-+#define HDMI_SCDC_SOURCE_VERSION 0x02
-+#define HDMI_SCDC_UPDATE_0 0x10
-+#define HDMI_SCDC_TMDS_CONFIG 0x20
-+#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
-+#define HDMI_SCDC_CONFIG_0 0x30
-+#define HDMI_SCDC_STATUS_FLAGS 0x40
-+#define HDMI_SCDC_ERR_DETECT 0x50
-+#define HDMI_SCDC_TEST_CONFIG 0xC0
-+
-+
-+union hdmi_scdc_update_read_data
-+{
-+	uint8_t byte[2];
-+    struct
-+    {
-+        uint8_t STATUS_UPDATE:1;
-+        uint8_t CED_UPDATE:1;
-+        uint8_t RR_TEST:1;
-+        uint8_t RESERVED:5;
-+		uint8_t RESERVED2:8;
-+    } fields; 
-+};
-+
-+union hdmi_scdc_status_flags_data
-+{
-+    uint8_t byte[2];
-+    struct
-+    {
-+        uint8_t CLOCK_DETECTED:1;
-+        uint8_t CH0_LOCKED:1;
-+        uint8_t CH1_LOCKED:1;
-+        uint8_t CH2_LOCKED:1;
-+        uint8_t RESERVED:4;
-+		uint8_t RESERVED2:8;
-+    } fields;
-+};
-+
-+union hdmi_scdc_ced_data
-+{
-+    uint8_t byte[7];
-+    struct
-+    {
-+        uint8_t CH0_8LOW:8;
-+        uint8_t CH0_7HIGH:7;
-+        uint8_t CH0_VALID:1;
-+        uint8_t CH1_8LOW:8;
-+        uint8_t CH1_7HIGH:7;
-+        uint8_t CH1_VALID:1;
-+        uint8_t CH2_8LOW:8;
-+        uint8_t CH2_7HIGH:7;
-+        uint8_t CH2_VALID:1;
-+        uint8_t CHECKSUM:8;
-+    } fields;
-+};
-+
-+union hdmi_scdc_test_config_Data
-+{
-+    uint8_t byte;
-+    struct
-+    {
-+        uint8_t TEST_READ_REQUEST_DELAY:7;
-+        uint8_t TEST_READ_REQUEST: 1;
-+    } fields;
-+};
-+
-+
-+
-+union ddc_wa {
-+	struct {
-+		uint32_t DP_SKIP_POWER_OFF:1;
-+		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct ddc_flags {
-+	uint8_t EDID_QUERY_DONE_ONCE:1;
-+	uint8_t IS_INTERNAL_DISPLAY:1;
-+	uint8_t FORCE_READ_REPEATED_START:1;
-+	uint8_t EDID_STRESS_READ:1;
-+
-+};
-+
-+struct ddc_service {
-+	struct ddc *ddc_pin;
-+	struct ddc_flags flags;
-+	union ddc_wa wa;
-+	enum ddc_transaction_type transaction_type;
-+	enum display_dongle_type dongle_type;
-+	struct dp_receiver_id_info dp_receiver_id_info;
-+	struct adapter_service *as;
-+	struct dc_context *ctx;
-+
-+	uint32_t address;
-+	uint32_t edid_buf_len;
-+	uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
-+};
-+
-+static bool construct(
-+	struct ddc_service *ddc_service,
-+	struct ddc_service_init_data *init_data)
-+{
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(init_data->id);
-+
-+	ddc_service->ctx = init_data->ctx;
-+	ddc_service->as = init_data->as;
-+	ddc_service->ddc_pin = dal_adapter_service_obtain_ddc(
-+			init_data->as, init_data->id);
-+
-+	ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
-+
-+	ddc_service->flags.FORCE_READ_REPEATED_START =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_DDC_READ_FORCE_REPEATED_START);
-+
-+	ddc_service->flags.EDID_STRESS_READ =
-+			dal_adapter_service_is_feature_supported(
-+				FEATURE_EDID_STRESS_READ);
-+
-+
-+	ddc_service->flags.IS_INTERNAL_DISPLAY =
-+		connector_id == CONNECTOR_ID_EDP ||
-+		connector_id == CONNECTOR_ID_LVDS;
-+
-+	ddc_service->wa.raw = 0;
-+	return true;
-+}
-+
-+struct ddc_service *dal_ddc_service_create(
-+	struct ddc_service_init_data *init_data)
-+{
-+	struct ddc_service *ddc_service;
-+
-+	ddc_service = dc_service_alloc(init_data->ctx, sizeof(struct ddc_service));
-+
-+	if (!ddc_service)
-+		return NULL;
-+
-+	if (construct(ddc_service, init_data))
-+		return ddc_service;
-+
-+	dc_service_free(init_data->ctx, ddc_service);
-+	return NULL;
-+}
-+
-+static void destruct(struct ddc_service *ddc)
-+{
-+	if (ddc->ddc_pin)
-+		dal_adapter_service_release_ddc(ddc->as, ddc->ddc_pin);
-+}
-+
-+void dal_ddc_service_destroy(struct ddc_service **ddc)
-+{
-+	if (!ddc || !*ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+	destruct(*ddc);
-+	dc_service_free((*ddc)->ctx, *ddc);
-+	*ddc = NULL;
-+}
-+
-+enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
-+{
-+	return DDC_SERVICE_TYPE_CONNECTOR;
-+}
-+
-+void dal_ddc_service_set_transaction_type(
-+	struct ddc_service *ddc,
-+	enum ddc_transaction_type type)
-+{
-+	ddc->transaction_type = type;
-+}
-+
-+bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
-+{
-+	switch (ddc->transaction_type) {
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
-+		return true;
-+	default:
-+		break;
-+	}
-+	return false;
-+}
-+
-+void ddc_service_set_dongle_type(struct ddc_service *ddc,
-+		enum display_dongle_type dongle_type)
-+{
-+	ddc->dongle_type = dongle_type;
-+}
-+
-+static uint32_t defer_delay_converter_wa(
-+	struct ddc_service *ddc,
-+	uint32_t defer_delay)
-+{
-+	struct dp_receiver_id_info dp_rec_info = {0};
-+
-+	if (dal_ddc_service_get_dp_receiver_id_info(ddc, &dp_rec_info) &&
-+		(dp_rec_info.branch_id == DP_BRANCH_DEVICE_ID_4) &&
-+		!dal_strncmp(dp_rec_info.branch_name,
-+			DP_DVI_CONVERTER_ID_4,
-+			sizeof(dp_rec_info.branch_name)))
-+		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
-+			defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
-+
-+	return defer_delay;
-+
-+}
-+
-+#define DP_TRANSLATOR_DELAY 5
-+
-+static uint32_t get_defer_delay(struct ddc_service *ddc)
-+{
-+	uint32_t defer_delay = 0;
-+
-+	switch (ddc->transaction_type) {
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
-+		if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
-+			(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
-+			(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
-+				ddc->dongle_type)) {
-+
-+			defer_delay = DP_TRANSLATOR_DELAY;
-+
-+			defer_delay =
-+				defer_delay_converter_wa(ddc, defer_delay);
-+
-+		} else /*sink has a delay different from an Active Converter*/
-+			defer_delay = 0;
-+		break;
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
-+		defer_delay = DP_TRANSLATOR_DELAY;
-+		break;
-+	default:
-+		break;
-+	}
-+	return defer_delay;
-+}
-+
-+static bool i2c_read(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *buffer,
-+	uint32_t len)
-+{
-+	uint8_t offs_data = 0;
-+	struct i2c_payload payloads[2] = {
-+		{
-+		.write = true,
-+		.address = address,
-+		.length = 1,
-+		.data = &offs_data },
-+		{
-+		.write = false,
-+		.address = address,
-+		.length = len,
-+		.data = buffer } };
-+
-+	struct i2c_command command = {
-+		.payloads = payloads,
-+		.number_of_payloads = 2,
-+		.engine = DDC_I2C_COMMAND_ENGINE,
-+		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
-+
-+	return dal_i2caux_submit_i2c_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		&command);
-+}
-+
-+static uint8_t aux_read_edid_block(
-+	struct ddc_service *ddc,
-+	uint8_t address,
-+	uint8_t index,
-+	uint8_t *buf)
-+{
-+	struct aux_command cmd = {
-+		.payloads = NULL,
-+		.number_of_payloads = 0,
-+		.defer_delay = get_defer_delay(ddc),
-+		.max_defer_write_retry = 0 };
-+
-+	uint8_t retrieved = 0;
-+	uint8_t base_offset =
-+		(index % DDC_EDID_BLOCKS_PER_SEGMENT) * DDC_EDID_BLOCK_SIZE;
-+	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
-+
-+	for (retrieved = 0; retrieved < DDC_EDID_BLOCK_SIZE;
-+		retrieved += DEFAULT_AUX_MAX_DATA_SIZE) {
-+
-+		uint8_t offset = base_offset + retrieved;
-+
-+		struct aux_payload payloads[3] = {
-+			{
-+			.i2c_over_aux = true,
-+			.write = true,
-+			.address = DDC_EDID_SEGMENT_ADDRESS,
-+			.length = 1,
-+			.data = &segment },
-+			{
-+			.i2c_over_aux = true,
-+			.write = true,
-+			.address = address,
-+			.length = 1,
-+			.data = &offset },
-+			{
-+			.i2c_over_aux = true,
-+			.write = false,
-+			.address = address,
-+			.length = DEFAULT_AUX_MAX_DATA_SIZE,
-+			.data = &buf[retrieved] } };
-+
-+		if (segment == 0) {
-+			cmd.payloads = &payloads[1];
-+			cmd.number_of_payloads = 2;
-+		} else {
-+			cmd.payloads = payloads;
-+			cmd.number_of_payloads = 3;
-+		}
-+
-+		if (!dal_i2caux_submit_aux_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd))
-+			/* cannot read, break*/
-+			break;
-+	}
-+
-+	/* Reset segment to 0. Needed by some panels */
-+	if (0 != segment) {
-+		struct aux_payload payloads[1] = { {
-+			.i2c_over_aux = true,
-+			.write = true,
-+			.address = DDC_EDID_SEGMENT_ADDRESS,
-+			.length = 1,
-+			.data = &segment } };
-+		bool result = false;
-+
-+		segment = 0;
-+
-+		cmd.number_of_payloads = ARRAY_SIZE(payloads);
-+		cmd.payloads = payloads;
-+
-+		result = dal_i2caux_submit_aux_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd);
-+
-+		if (false == result)
-+			dal_logger_write(
-+				ddc->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
-+				"%s: Writing of EDID Segment (0x30) failed!\n",
-+				__func__);
-+	}
-+
-+	return retrieved;
-+}
-+
-+static uint8_t i2c_read_edid_block(
-+	struct ddc_service *ddc,
-+	uint8_t address,
-+	uint8_t index,
-+	uint8_t *buf)
-+{
-+	bool ret = false;
-+	uint8_t offset = (index % DDC_EDID_BLOCKS_PER_SEGMENT) *
-+		DDC_EDID_BLOCK_SIZE;
-+	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
-+
-+	struct i2c_command cmd = {
-+		.payloads = NULL,
-+		.number_of_payloads = 0,
-+		.engine = DDC_I2C_COMMAND_ENGINE,
-+		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
-+
-+	struct i2c_payload payloads[3] = {
-+		{
-+		.write = true,
-+		.address = DDC_EDID_SEGMENT_ADDRESS,
-+		.length = 1,
-+		.data = &segment },
-+		{
-+		.write = true,
-+		.address = address,
-+		.length = 1,
-+		.data = &offset },
-+		{
-+		.write = false,
-+		.address = address,
-+		.length = DDC_EDID_BLOCK_SIZE,
-+		.data = buf } };
-+/*
-+ * Some I2C engines don't handle stop/start between write-offset and read-data
-+ * commands properly. For those displays, we have to force the newer E-DDC
-+ * behavior of repeated-start which can be enabled by runtime parameter. */
-+/* Originally implemented for OnLive using NXP receiver chip */
-+
-+	if (index == 0 && !ddc->flags.FORCE_READ_REPEATED_START) {
-+		/* base block, use use DDC2B, submit as 2 commands */
-+		cmd.payloads = &payloads[1];
-+		cmd.number_of_payloads = 1;
-+
-+		if (dal_i2caux_submit_i2c_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd)) {
-+
-+			cmd.payloads = &payloads[2];
-+			cmd.number_of_payloads = 1;
-+
-+			ret = dal_i2caux_submit_i2c_command(
-+				dal_adapter_service_get_i2caux(ddc->as),
-+				ddc->ddc_pin,
-+				&cmd);
-+		}
-+
-+	} else {
-+		/*
-+		 * extension block use E-DDC, submit as 1 command
-+		 * or if repeated-start is forced by runtime parameter
-+		 */
-+		if (segment != 0) {
-+			/* include segment offset in command*/
-+			cmd.payloads = payloads;
-+			cmd.number_of_payloads = 3;
-+		} else {
-+			/* we are reading first segment,
-+			 * segment offset is not required */
-+			cmd.payloads = &payloads[1];
-+			cmd.number_of_payloads = 2;
-+		}
-+
-+		ret = dal_i2caux_submit_i2c_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd);
-+	}
-+
-+	return ret ? DDC_EDID_BLOCK_SIZE : 0;
-+}
-+
-+static uint32_t query_edid_block(
-+	struct ddc_service *ddc,
-+	uint8_t address,
-+	uint8_t index,
-+	uint8_t *buf,
-+	uint32_t size)
-+{
-+	uint32_t size_retrieved = 0;
-+
-+	if (size < DDC_EDID_BLOCK_SIZE)
-+		return 0;
-+
-+	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-+
-+		ASSERT(index < 2);
-+		size_retrieved =
-+			aux_read_edid_block(ddc, address, index, buf);
-+	} else {
-+		size_retrieved =
-+			i2c_read_edid_block(ddc, address, index, buf);
-+	}
-+
-+	return size_retrieved;
-+}
-+
-+#define DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS 0x261
-+#define DDC_TEST_ACK_ADDRESS 0x260
-+#define DDC_DPCD_EDID_TEST_ACK 0x04
-+#define DDC_DPCD_EDID_TEST_MASK 0x04
-+#define DDC_DPCD_TEST_REQUEST_ADDRESS 0x218
-+
-+static void write_dp_edid_checksum(
-+	struct ddc_service *ddc,
-+	uint8_t checksum)
-+{
-+	uint8_t dpcd_data;
-+
-+	dal_ddc_service_read_dpcd_data(
-+		ddc,
-+		DDC_DPCD_TEST_REQUEST_ADDRESS,
-+		&dpcd_data,
-+		1);
-+
-+	if (dpcd_data & DDC_DPCD_EDID_TEST_MASK) {
-+
-+		dal_ddc_service_write_dpcd_data(
-+			ddc,
-+			DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS,
-+			&checksum,
-+			1);
-+
-+		dpcd_data = DDC_DPCD_EDID_TEST_ACK;
-+
-+		dal_ddc_service_write_dpcd_data(
-+			ddc,
-+			DDC_TEST_ACK_ADDRESS,
-+			&dpcd_data,
-+			1);
-+	}
-+}
-+
-+uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc)
-+{
-+	uint32_t bytes_read = 0;
-+	uint32_t ext_cnt = 0;
-+
-+	uint8_t address;
-+	uint32_t i;
-+
-+	for (address = DDC_EDID_ADDRESS_START;
-+		address <= DDC_EDID_ADDRESS_END; ++address) {
-+
-+		bytes_read = query_edid_block(
-+			ddc,
-+			address,
-+			0,
-+			ddc->edid_buf,
-+			sizeof(ddc->edid_buf) - bytes_read);
-+
-+		if (bytes_read != DDC_EDID_BLOCK_SIZE)
-+			continue;
-+
-+		/* get the number of ext blocks*/
-+		ext_cnt = ddc->edid_buf[DDC_EDID_EXT_COUNT_OFFSET];
-+
-+		/* EDID 2.0, need to read 1 more block because EDID2.0 is
-+		 * 256 byte in size*/
-+		if (ddc->edid_buf[DDC_EDID_20_SIGNATURE_OFFSET] ==
-+			DDC_EDID_20_SIGNATURE)
-+				ext_cnt = 1;
-+
-+		for (i = 0; i < ext_cnt; i++) {
-+			/* read additional ext blocks accordingly */
-+			bytes_read += query_edid_block(
-+					ddc,
-+					address,
-+					i+1,
-+					&ddc->edid_buf[bytes_read],
-+					sizeof(ddc->edid_buf) - bytes_read);
-+		}
-+
-+		/*this is special code path for DP compliance*/
-+		if (DDC_TRANSACTION_TYPE_I2C_OVER_AUX == ddc->transaction_type)
-+			write_dp_edid_checksum(
-+				ddc,
-+				ddc->edid_buf[(ext_cnt * DDC_EDID_BLOCK_SIZE) +
-+				DDC_EDID1X_CHECKSUM_OFFSET]);
-+
-+		/*remembers the address where we fetch the EDID from
-+		 * for later signature check use */
-+		ddc->address = address;
-+
-+		break;/* already read edid, done*/
-+	}
-+
-+	ddc->edid_buf_len = bytes_read;
-+	return bytes_read;
-+}
-+
-+uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc)
-+{
-+	return ddc->edid_buf_len;
-+}
-+
-+void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf)
-+{
-+	dc_service_memmove(edid_buf,
-+			ddc->edid_buf, ddc->edid_buf_len);
-+}
-+
-+void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+	struct ddc_service *ddc,
-+	struct display_sink_capability *sink_cap)
-+{
-+	uint8_t i;
-+	bool is_valid_hdmi_signature;
-+	enum display_dongle_type *dongle = &sink_cap->dongle_type;
-+	uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
-+	bool is_type2_dongle = false;
-+	struct dp_hdmi_dongle_signature_data *dongle_signature;
-+
-+	/* Assume we have no valid DP passive dongle connected */
-+	*dongle = DISPLAY_DONGLE_NONE;
-+	sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
-+
-+	/* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
-+	if (!i2c_read(
-+		ddc,
-+		DP_HDMI_DONGLE_ADDRESS,
-+		type2_dongle_buf,
-+		sizeof(type2_dongle_buf))) {
-+		dal_logger_write(ddc->ctx->logger,
-+			LOG_MAJOR_DCS,
-+			LOG_MINOR_DCS_DONGLE_DETECTION,
-+			"Detected DP-DVI dongle.\n");
-+		*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+		sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
-+		return;
-+	}
-+
-+	/* Check if Type 2 dongle.*/
-+	if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
-+		is_type2_dongle = true;
-+
-+	dongle_signature =
-+		(struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
-+
-+	is_valid_hdmi_signature = true;
-+
-+	/* Check EOT */
-+	if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
-+		is_valid_hdmi_signature = false;
-+	}
-+
-+	/* Check signature */
-+	for (i = 0; i < sizeof(dongle_signature->id); ++i) {
-+		/* If its not the right signature,
-+		 * skip mismatch in subversion byte.*/
-+		if (dongle_signature->id[i] !=
-+			dp_hdmi_dongle_signature_str[i] && i != 3) {
-+
-+			if (is_type2_dongle) {
-+				is_valid_hdmi_signature = false;
-+				break;
-+			}
-+
-+		}
-+	}
-+
-+	if (is_type2_dongle) {
-+		uint32_t max_tmds_clk =
-+			type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
-+
-+		max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
-+
-+		if (0 == max_tmds_clk ||
-+				max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
-+				max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
-+			dal_logger_write(ddc->ctx->logger,
-+				LOG_MAJOR_DCS,
-+				LOG_MINOR_DCS_DONGLE_DETECTION,
-+				"Invalid Maximum TMDS clock");
-+			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+		} else {
-+			if (is_valid_hdmi_signature == true) {
-+				*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
-+				dal_logger_write(ddc->ctx->logger,
-+					LOG_MAJOR_DCS,
-+					LOG_MINOR_DCS_DONGLE_DETECTION,
-+					"Detected Type 2 DP-HDMI Maximum TMDS "
-+					"clock, max TMDS clock: %d MHz",
-+					max_tmds_clk);
-+			} else {
-+				*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+				dal_logger_write(ddc->ctx->logger,
-+					LOG_MAJOR_DCS,
-+					LOG_MINOR_DCS_DONGLE_DETECTION,
-+					"Detected Type 2 DP-HDMI (no valid HDMI"
-+					" signature) Maximum TMDS clock, max "
-+					"TMDS clock: %d MHz",
-+					max_tmds_clk);
-+			}
-+
-+			/* Multiply by 1000 to convert to kHz. */
-+			sink_cap->max_hdmi_pixel_clock =
-+				max_tmds_clk * 1000;
-+		}
-+
-+	} else {
-+		if (is_valid_hdmi_signature == true) {
-+			dal_logger_write(ddc->ctx->logger,
-+				LOG_MAJOR_DCS,
-+				LOG_MINOR_DCS_DONGLE_DETECTION,
-+				"Detected Type 1 DP-HDMI dongle.\n");
-+			*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
-+		}
-+		else {
-+			dal_logger_write(ddc->ctx->logger,
-+				LOG_MAJOR_DCS,
-+				LOG_MINOR_DCS_DONGLE_DETECTION,
-+				"Detected Type 1 DP-HDMI dongle (no valid HDMI "
-+				"signature).\n");
-+
-+			*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+		}
-+	}
-+
-+	return;
-+}
-+
-+enum {
-+	DP_SINK_CAP_SIZE =
-+		DPCD_ADDRESS_EDP_CONFIG_CAP - DPCD_ADDRESS_DPCD_REV + 1
-+};
-+
-+bool dal_ddc_service_query_ddc_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *write_buf,
-+	uint32_t write_size,
-+	uint8_t *read_buf,
-+	uint32_t read_size)
-+{
-+	bool ret;
-+	uint32_t payload_size =
-+		dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
-+			DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
-+
-+	uint32_t write_payloads =
-+		(write_size + payload_size - 1) / payload_size;
-+
-+	uint32_t read_payloads =
-+		(read_size + payload_size - 1) / payload_size;
-+
-+	uint32_t payloads_num = write_payloads + read_payloads;
-+
-+	if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
-+		return false;
-+
-+	/*TODO: len of payload data for i2c and aux is uint8!!!!,
-+	 *  but we want to read 256 over i2c!!!!*/
-+	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-+
-+		struct aux_payloads *payloads =
-+			dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
-+
-+		struct aux_command command = {
-+			.payloads = dal_ddc_aux_payloads_get(payloads),
-+			.number_of_payloads = 0,
-+			.defer_delay = get_defer_delay(ddc),
-+			.max_defer_write_retry = 0 };
-+
-+		dal_ddc_aux_payloads_add(
-+			payloads, address, write_size, write_buf, true);
-+
-+		dal_ddc_aux_payloads_add(
-+			payloads, address, read_size, read_buf, false);
-+
-+		command.number_of_payloads =
-+			dal_ddc_aux_payloads_get_count(payloads);
-+
-+		ret = dal_i2caux_submit_aux_command(
-+				dal_adapter_service_get_i2caux(ddc->as),
-+				ddc->ddc_pin,
-+				&command);
-+
-+		dal_ddc_aux_payloads_destroy(&payloads);
-+
-+	} else {
-+		struct i2c_payloads *payloads =
-+			dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
-+
-+		struct i2c_command command = {
-+			.payloads = dal_ddc_i2c_payloads_get(payloads),
-+			.number_of_payloads = 0,
-+			.engine = DDC_I2C_COMMAND_ENGINE,
-+			.speed =
-+				dal_adapter_service_get_sw_i2c_speed(ddc->as) };
-+
-+		dal_ddc_i2c_payloads_add(
-+			payloads, address, write_size, write_buf, true);
-+
-+		dal_ddc_i2c_payloads_add(
-+			payloads, address, read_size, read_buf, false);
-+
-+		command.number_of_payloads =
-+			dal_ddc_i2c_payloads_get_count(payloads);
-+
-+		ret = dal_i2caux_submit_i2c_command(
-+				dal_adapter_service_get_i2caux(ddc->as),
-+				ddc->ddc_pin,
-+				&command);
-+
-+		dal_ddc_i2c_payloads_destroy(&payloads);
-+	}
-+
-+	return ret;
-+}
-+
-+bool dal_ddc_service_get_dp_receiver_id_info(
-+	struct ddc_service *ddc,
-+	struct dp_receiver_id_info *info)
-+{
-+	if (!info)
-+		return false;
-+
-+	*info = ddc->dp_receiver_id_info;
-+	return true;
-+}
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t len)
-+{
-+	struct aux_payload read_payload = {
-+		.i2c_over_aux = false,
-+		.write = false,
-+		.address = address,
-+		.length = len,
-+		.data = data,
-+	};
-+	struct aux_command command = {
-+		.payloads = &read_payload,
-+		.number_of_payloads = 1,
-+		.defer_delay = 0,
-+		.max_defer_write_retry = 0,
-+	};
-+
-+	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
-+		BREAK_TO_DEBUGGER();
-+		return DDC_RESULT_FAILED_INVALID_OPERATION;
-+	}
-+
-+	if (dal_i2caux_submit_aux_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		&command))
-+		return DDC_RESULT_SUCESSFULL;
-+
-+	return DDC_RESULT_FAILED_OPERATION;
-+}
-+
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t len)
-+{
-+	struct aux_payload write_payload = {
-+		.i2c_over_aux = false,
-+		.write = true,
-+		.address = address,
-+		.length = len,
-+		.data = (uint8_t *)data,
-+	};
-+	struct aux_command command = {
-+		.payloads = &write_payload,
-+		.number_of_payloads = 1,
-+		.defer_delay = 0,
-+		.max_defer_write_retry = 0,
-+	};
-+
-+	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
-+		BREAK_TO_DEBUGGER();
-+		return DDC_RESULT_FAILED_INVALID_OPERATION;
-+	}
-+
-+	if (dal_i2caux_submit_aux_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		&command))
-+		return DDC_RESULT_SUCESSFULL;
-+
-+	return DDC_RESULT_FAILED_OPERATION;
-+}
-+
-+/*test only function*/
-+void dal_ddc_service_set_ddc_pin(
-+	struct ddc_service *ddc_service,
-+	struct ddc *ddc)
-+{
-+	ddc_service->ddc_pin = ddc;
-+}
-+
-+struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
-+{
-+	return ddc_service->ddc_pin;
-+}
-+
-+
-+void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
-+{
-+	dc_service_memset(&ddc_service->dp_receiver_id_info,
-+		0, sizeof(struct dp_receiver_id_info));
-+}
-+
-+void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
-+		uint32_t pix_clk,
-+		bool lte_340_scramble)
-+{
-+	bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
-+	uint8_t slave_address = HDMI_SCDC_ADDRESS;
-+	uint8_t offset = HDMI_SCDC_SINK_VERSION;
-+	uint8_t sink_version = 0;
-+	uint8_t write_buffer[2] = {0};
-+	/*Lower than 340 Scramble bit from SCDC caps*/
-+
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
-+			sizeof(offset), &sink_version, sizeof(sink_version));
-+	if (sink_version == 1) {
-+		/*Source Version = 1*/
-+		write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
-+		write_buffer[1] = 1;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				write_buffer, sizeof(write_buffer), NULL, 0);
-+		/*Read Request from SCDC caps*/
-+	}
-+	write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
-+
-+	if (over_340_mhz)
-+	{
-+		write_buffer[1] = 3;
-+	}
-+	else if (lte_340_scramble)
-+	{
-+		write_buffer[1] = 1;
-+	}
-+	else
-+	{
-+		write_buffer[1] = 0;
-+	}
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
-+			sizeof(write_buffer), NULL, 0);
-+}
-+
-+void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
-+{
-+	uint8_t slave_address = HDMI_SCDC_ADDRESS;
-+	uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
-+	uint8_t tmds_config = 0;
-+
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
-+			sizeof(offset), &tmds_config, sizeof(tmds_config));
-+	if (tmds_config & 0x1){
-+		union hdmi_scdc_status_flags_data status_data = {{0}};
-+		uint8_t scramble_status = 0;
-+
-+		offset = HDMI_SCDC_SCRAMBLER_STATUS;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				&offset, sizeof(offset),&scramble_status,
-+				sizeof(scramble_status));
-+		offset = HDMI_SCDC_STATUS_FLAGS;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				&offset, sizeof(offset),status_data.byte,
-+				sizeof(status_data.byte));
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-new file mode 100644
-index 0000000..e5217b7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-@@ -0,0 +1,38 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DDC_SERVICE_H__
-+#define __DAL_DDC_SERVICE_H__
-+
-+#include "include/ddc_service_types.h"
-+
-+void dal_ddc_service_set_ddc_pin(
-+	struct ddc_service *ddc_service,
-+	struct ddc *ddc);
-+
-+struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service);
-+void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service);
-+
-+#endif /* __DAL_DDC_SERVICE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-new file mode 100644
-index 0000000..7380910
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-@@ -0,0 +1,24 @@
-+#
-+# Makefile for the 'gpio' sub-component of DAL.
-+# It provides the control and status of HW GPIO pins.
-+
-+GPIO = ddc.o dvo.o gpio_base.o gpio_service.o hw_ddc.o hw_dvo.o hw_factory.o \
-+       hw_gpio.o hw_gpio_pad.o hw_gpio_pin.o hw_hpd.o hw_translate.o irq.o
-+
-+AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPIO)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+GPIO_DCE110 = hw_translate_dce110.o hw_factory_dce110.o hw_hpd_dce110.o \
-+	hw_ddc_dce110.o
-+
-+AMD_DAL_GPIO_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpio/dce110/,$(GPIO_DCE110))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPIO_DCE110)
-+endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-new file mode 100644
-index 0000000..f026464
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-@@ -0,0 +1,883 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "hw_ddc_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define ADDR_DDC_SETUP pin->addr.dc_i2c_ddc_setup
-+/*
-+ * This unit
-+ */
-+static void destruct(
-+	struct hw_ddc_dce110 *pin)
-+{
-+	dal_hw_ddc_destruct(&pin->base);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_ddc_dce110 *pin = DDC_DCE110_FROM_BASE(*ptr);
-+
-+	destruct(pin);
-+
-+	dc_service_free((*ptr)->ctx, pin);
-+
-+	*ptr = NULL;
-+}
-+
-+struct hw_ddc_dce110_init {
-+	struct hw_gpio_pin_reg hw_gpio_data_reg;
-+	struct hw_ddc_mask hw_ddc_mask;
-+	struct hw_ddc_dce110_addr hw_ddc_dce110_addr;
-+};
-+
-+static const struct hw_ddc_dce110_init
-+	hw_ddc_dce110_init_data[GPIO_DDC_LINE_COUNT] = {
-+	/* GPIO_DDC_LINE_DDC1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC1_MASK,
-+				DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_A,
-+				DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_EN,
-+				DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_Y,
-+				DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK,
-+			DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK,
-+			DC_GPIO_DDC1_MASK__AUX1_POL_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC1_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC2 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC2_MASK,
-+				DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_A,
-+				DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_EN,
-+				DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_Y,
-+				DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK,
-+			DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK,
-+			DC_GPIO_DDC2_MASK__AUX2_POL_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC2_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC3 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC3_MASK,
-+				DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_A,
-+				DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_EN,
-+				DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_Y,
-+				DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK,
-+			DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK,
-+			DC_GPIO_DDC3_MASK__AUX3_POL_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC3_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC4 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC4_MASK,
-+				DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_A,
-+				DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_EN,
-+				DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_Y,
-+				DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK,
-+			DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK,
-+			DC_GPIO_DDC4_MASK__AUX4_POL_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC4_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC5 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC5_MASK,
-+				DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_A,
-+				DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_EN,
-+				DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_Y,
-+				DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK,
-+			DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK,
-+			DC_GPIO_DDC5_MASK__AUX5_POL_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC5_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC6 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC6_MASK,
-+				DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_A,
-+				DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_EN,
-+				DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_Y,
-+				DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK,
-+			DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK,
-+			DC_GPIO_DDC6_MASK__AUX6_POL_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC6_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC_VGA */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDCVGA_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_A,
-+				DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_EN,
-+				DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_Y,
-+				DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDCVGA_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_I2CPAD */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_I2CPAD_MASK,
-+				DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_A,
-+				DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_EN,
-+				DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_Y,
-+				DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK,
-+			0,
-+			0,
-+			0
-+		},
-+		{
-+			0
-+		}
-+	}
-+};
-+
-+static const struct hw_ddc_dce110_init
-+	hw_ddc_dce110_init_clock[GPIO_DDC_LINE_COUNT] = {
-+	/* GPIO_DDC_LINE_DDC1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC1_MASK,
-+				DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_A,
-+				DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_EN,
-+				DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_Y,
-+				DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK,
-+			DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK,
-+			DC_GPIO_DDC1_MASK__AUX1_POL_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC1_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC2 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC2_MASK,
-+				DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_A,
-+				DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_EN,
-+				DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_Y,
-+				DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK,
-+			DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK,
-+			DC_GPIO_DDC2_MASK__AUX2_POL_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC2_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC3 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC3_MASK,
-+				DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_A,
-+				DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_EN,
-+				DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_Y,
-+				DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK,
-+			DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK,
-+			DC_GPIO_DDC3_MASK__AUX3_POL_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC3_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC4 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC4_MASK,
-+				DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_A,
-+				DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_EN,
-+				DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_Y,
-+				DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK,
-+			DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK,
-+			DC_GPIO_DDC4_MASK__AUX4_POL_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC4_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC5 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC5_MASK,
-+				DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_A,
-+				DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_EN,
-+				DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_Y,
-+				DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK,
-+			DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK,
-+			DC_GPIO_DDC5_MASK__AUX5_POL_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC5_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC6 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC6_MASK,
-+				DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_A,
-+				DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_EN,
-+				DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_Y,
-+				DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK,
-+			DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK,
-+			DC_GPIO_DDC6_MASK__AUX6_POL_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC6_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC_VGA */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDCVGA_MASK,
-+				DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_A,
-+				DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_EN,
-+				DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_Y,
-+				DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDCVGA_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_I2CPAD */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_I2CPAD_MASK,
-+				DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_A,
-+				DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_EN,
-+				DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_Y,
-+				DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK,
-+			0,
-+			0,
-+			0
-+		},
-+		{
-+			0
-+		}
-+	}
-+};
-+
-+static void setup_i2c_polling(
-+	struct dc_context *ctx,
-+	const uint32_t addr,
-+	bool enable_detect,
-+	bool detect_mode)
-+{
-+	uint32_t value;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		enable_detect,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_ENABLE);
-+
-+	set_reg_field_value(
-+		value,
-+		enable_detect,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_EDID_DETECT_ENABLE);
-+
-+	if (enable_detect)
-+		set_reg_field_value(
-+			value,
-+			detect_mode,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_EDID_DETECT_MODE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static enum gpio_result set_config(
-+	struct hw_gpio_pin *ptr,
-+	const struct gpio_config_data *config_data)
-+{
-+	struct hw_ddc_dce110 *pin = DDC_DCE110_FROM_BASE(ptr);
-+	struct hw_gpio *hw_gpio = NULL;
-+	uint32_t addr;
-+	uint32_t regval;
-+	uint32_t ddc_data_pd_en = 0;
-+	uint32_t ddc_clk_pd_en = 0;
-+	uint32_t aux_pad_mode = 0;
-+
-+	hw_gpio = &pin->base.base;
-+
-+	if (hw_gpio == NULL) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	/* switch dual mode GPIO to I2C/AUX mode */
-+
-+	addr = hw_gpio->pin_reg.DC_GPIO_DATA_MASK.addr;
-+
-+	regval = dal_read_reg(ptr->ctx, addr);
-+
-+	ddc_data_pd_en = get_reg_field_value(
-+			regval,
-+			DC_GPIO_DDC1_MASK,
-+			DC_GPIO_DDC1DATA_PD_EN);
-+
-+	ddc_clk_pd_en = get_reg_field_value(
-+			regval,
-+			DC_GPIO_DDC1_MASK,
-+			DC_GPIO_DDC1CLK_PD_EN);
-+
-+	aux_pad_mode = get_reg_field_value(
-+			regval,
-+			DC_GPIO_DDC1_MASK,
-+			AUX_PAD1_MODE);
-+
-+	switch (config_data->config.ddc.type) {
-+	case GPIO_DDC_CONFIG_TYPE_MODE_I2C:
-+		/* On plug-in, there is a transient level on the pad
-+		 * which must be discharged through the internal pull-down.
-+		 * Enable internal pull-down, 2.5msec discharge time
-+		 * is required for detection of AUX mode */
-+		if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
-+			if (!ddc_data_pd_en || !ddc_clk_pd_en) {
-+				set_reg_field_value(
-+					regval,
-+					1,
-+					DC_GPIO_DDC1_MASK,
-+					DC_GPIO_DDC1DATA_PD_EN);
-+
-+				set_reg_field_value(
-+					regval,
-+					1,
-+					DC_GPIO_DDC1_MASK,
-+					DC_GPIO_DDC1CLK_PD_EN);
-+
-+				dal_write_reg(ptr->ctx, addr, regval);
-+
-+				if (config_data->type ==
-+					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					/* should not affect normal I2C R/W */
-+					/* [anaumov] in DAL2, there was
-+					 * dc_service_delay_in_microseconds(2500); */
-+					dc_service_sleep_in_milliseconds(ptr->ctx, 3);
-+			}
-+		} else {
-+			uint32_t reg2 = regval;
-+			uint32_t sda_pd_dis = 0;
-+			uint32_t scl_pd_dis = 0;
-+
-+			sda_pd_dis = get_reg_field_value(
-+					reg2,
-+					DC_GPIO_I2CPAD_MASK,
-+					DC_GPIO_SDA_PD_DIS);
-+
-+			scl_pd_dis = get_reg_field_value(
-+					reg2,
-+					DC_GPIO_I2CPAD_MASK,
-+					DC_GPIO_SCL_PD_DIS);
-+
-+			if (sda_pd_dis) {
-+				sda_pd_dis = 0;
-+
-+				dal_write_reg(ptr->ctx, addr, reg2);
-+
-+				if (config_data->type ==
-+					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					/* should not affect normal I2C R/W */
-+					/* [anaumov] in DAL2, there was
-+					 * dc_service_delay_in_microseconds(2500); */
-+					dc_service_sleep_in_milliseconds(ptr->ctx, 3);
-+			}
-+
-+			if (!scl_pd_dis) {
-+				scl_pd_dis = 1;
-+
-+				dal_write_reg(ptr->ctx, addr, reg2);
-+
-+				if (config_data->type ==
-+					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					/* should not affect normal I2C R/W */
-+					/* [anaumov] in DAL2, there was
-+					 * dc_service_delay_in_microseconds(2500); */
-+					dc_service_sleep_in_milliseconds(ptr->ctx, 3);
-+			}
-+		}
-+
-+		if (aux_pad_mode) {
-+			/* let pins to get de-asserted
-+			 * before setting pad to I2C mode */
-+			if (config_data->config.ddc.data_en_bit_present ||
-+				config_data->config.ddc.clock_en_bit_present)
-+				/* [anaumov] in DAL2, there was
-+				 * dc_service_delay_in_microseconds(2000); */
-+				dc_service_sleep_in_milliseconds(ptr->ctx, 2);
-+
-+			/* set the I2C pad mode */
-+			/* read the register again,
-+			 * some bits may have been changed */
-+			regval = dal_read_reg(ptr->ctx, addr);
-+
-+			set_reg_field_value(
-+				regval,
-+				0,
-+				DC_GPIO_DDC1_MASK,
-+				AUX_PAD1_MODE);
-+
-+			dal_write_reg(ptr->ctx, addr, regval);
-+		}
-+
-+		return GPIO_RESULT_OK;
-+	case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
-+		/* set the AUX pad mode */
-+		if (!aux_pad_mode) {
-+			set_reg_field_value(
-+				regval,
-+				1,
-+				DC_GPIO_DDC1_MASK,
-+				AUX_PAD1_MODE);
-+
-+			dal_write_reg(ptr->ctx, addr, regval);
-+		}
-+
-+		return GPIO_RESULT_OK;
-+	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			setup_i2c_polling(
-+				ptr->ctx, ADDR_DDC_SETUP, 1, 0);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			setup_i2c_polling(
-+				ptr->ctx, ADDR_DDC_SETUP, 1, 1);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			setup_i2c_polling(
-+				ptr->ctx, ADDR_DDC_SETUP, 0, 0);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+}
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = dal_hw_ddc_open,
-+	.get_value = dal_hw_gpio_get_value,
-+	.set_value = dal_hw_gpio_set_value,
-+	.set_config = set_config,
-+	.change_mode = dal_hw_gpio_change_mode,
-+	.close = dal_hw_gpio_close,
-+};
-+
-+
-+static bool construct(
-+	struct hw_ddc_dce110 *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	const struct hw_ddc_dce110_init *init;
-+
-+	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if (!dal_hw_ddc_construct(&pin->base, id, en, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	pin->base.base.base.funcs = &funcs;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		init = hw_ddc_dce110_init_data + en;
-+
-+		pin->base.base.pin_reg = init->hw_gpio_data_reg;
-+		pin->base.mask = init->hw_ddc_mask;
-+		pin->addr = init->hw_ddc_dce110_addr;
-+
-+		return true;
-+	case GPIO_ID_DDC_CLOCK:
-+		init = hw_ddc_dce110_init_clock + en;
-+
-+		pin->base.base.pin_reg = init->hw_gpio_data_reg;
-+		pin->base.mask = init->hw_ddc_mask;
-+		pin->addr = init->hw_ddc_dce110_addr;
-+
-+		return true;
-+	default:
-+		ASSERT_CRITICAL(false);
-+	}
-+
-+	return false;
-+}
-+
-+struct hw_gpio_pin *dal_hw_ddc_dce110_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_ddc_dce110 *pin = dc_service_alloc(ctx, sizeof(struct hw_ddc_dce110));
-+
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(pin, id, en, ctx))
-+		return &pin->base.base.base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, pin);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h
-new file mode 100644
-index 0000000..6830369
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_DDC_DCE110_H__
-+#define __DAL_HW_DDC_DCE110_H__
-+
-+struct hw_ddc_dce110_addr {
-+	uint32_t dc_i2c_ddc_setup;
-+};
-+
-+struct hw_ddc_dce110 {
-+	struct hw_ddc base;
-+	struct hw_ddc_dce110_addr addr;
-+};
-+
-+#define DDC_DCE110_FROM_BASE(ddc_base) \
-+	container_of((HW_DDC_FROM_BASE(ddc_base)), struct hw_ddc_dce110, base)
-+
-+struct hw_gpio_pin *dal_hw_ddc_dce110_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-new file mode 100644
-index 0000000..85644c5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-@@ -0,0 +1,84 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dal_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+#include "hw_factory_dce110.h"
-+#include "hw_hpd_dce110.h"
-+#include "hw_ddc_dce110.h"
-+
-+/* fucntion table */
-+static const struct hw_factory_funcs funcs = {
-+	.create_dvo = NULL,
-+	.create_ddc_data = dal_hw_ddc_dce110_create,
-+	.create_ddc_clock = dal_hw_ddc_dce110_create,
-+	.create_generic = NULL,
-+	.create_hpd = dal_hw_hpd_dce110_create,
-+	.create_gpio_pad = NULL,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+};
-+
-+/*
-+ * dal_hw_factory_dce110_init
-+ *
-+ * @brief
-+ * Initialize HW factory function pointers and pin info
-+ *
-+ * @param
-+ * struct hw_factory *factory - [out] struct of function pointers
-+ */
-+void dal_hw_factory_dce110_init(struct hw_factory *factory)
-+{
-+	/*TODO check ASIC CAPs*/
-+	factory->number_of_pins[GPIO_ID_DVO1] = 24;
-+	factory->number_of_pins[GPIO_ID_DVO12] = 2;
-+	factory->number_of_pins[GPIO_ID_DVO24] = 1;
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h
-new file mode 100644
-index 0000000..ecf06ed
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DCE110_H__
-+#define __DAL_HW_FACTORY_DCE110_H__
-+
-+/* Initialize HW factory function pointers and pin info */
-+void dal_hw_factory_dce110_init(struct hw_factory *factory);
-+
-+#endif /* __DAL_HW_FACTORY_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-new file mode 100644
-index 0000000..34405e9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-@@ -0,0 +1,367 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_hpd.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "hw_hpd_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+static void destruct(
-+	struct hw_hpd_dce110 *pin)
-+{
-+	dal_hw_hpd_destruct(&pin->base);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_hpd_dce110 *pin = HPD_DCE110_FROM_BASE(*ptr);
-+
-+	destruct(pin);
-+
-+	dc_service_free((*ptr)->ctx, pin);
-+
-+	*ptr = NULL;
-+}
-+
-+struct hw_gpio_generic_dce110_init {
-+	struct hw_gpio_pin_reg hw_gpio_data_reg;
-+	struct hw_hpd_dce110_addr addr;
-+};
-+
-+static const struct hw_gpio_generic_dce110_init
-+	hw_gpio_generic_dce110_init[GPIO_HPD_COUNT] = {
-+	/* GPIO_HPD_1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK
-+			}
-+		},
-+		{
-+			mmHPD0_DC_HPD_INT_STATUS,
-+			mmHPD0_DC_HPD_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_2 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK
-+			}
-+		},
-+		{
-+			mmHPD1_DC_HPD_INT_STATUS,
-+			mmHPD1_DC_HPD_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_3 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK
-+			}
-+		},
-+		{
-+			mmHPD2_DC_HPD_INT_STATUS,
-+			mmHPD2_DC_HPD_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_4 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK
-+			}
-+		},
-+		{
-+			mmHPD3_DC_HPD_INT_STATUS,
-+			mmHPD3_DC_HPD_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_5 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK
-+			}
-+		},
-+		{
-+			mmHPD4_DC_HPD_INT_STATUS,
-+			mmHPD4_DC_HPD_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_6 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK
-+			}
-+		},
-+		{
-+			mmHPD5_DC_HPD_INT_STATUS,
-+			mmHPD5_DC_HPD_TOGGLE_FILT_CNTL
-+		}
-+	}
-+};
-+
-+static enum gpio_result get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	struct hw_hpd_dce110 *pin = HPD_DCE110_FROM_BASE(ptr);
-+
-+	/* in Interrupt mode we ask for SENSE bit */
-+
-+	if (ptr->mode == GPIO_MODE_INTERRUPT) {
-+		uint32_t regval;
-+		uint32_t hpd_delayed = 0;
-+		uint32_t hpd_sense = 0;
-+
-+		regval = dal_read_reg(
-+				ptr->ctx,
-+				pin->addr.DC_HPD_INT_STATUS);
-+
-+		hpd_delayed = get_reg_field_value(
-+				regval,
-+				DC_HPD_INT_STATUS,
-+				DC_HPD_SENSE_DELAYED);
-+
-+		hpd_sense = get_reg_field_value(
-+				regval,
-+				DC_HPD_INT_STATUS,
-+				DC_HPD_SENSE);
-+
-+		*value = hpd_delayed;
-+		return GPIO_RESULT_OK;
-+	}
-+
-+	/* in any other modes, operate as normal GPIO */
-+
-+	return dal_hw_gpio_get_value(ptr, value);
-+}
-+
-+static enum gpio_result set_config(
-+	struct hw_gpio_pin *ptr,
-+	const struct gpio_config_data *config_data)
-+{
-+	struct hw_hpd_dce110 *pin = HPD_DCE110_FROM_BASE(ptr);
-+
-+	if (!config_data)
-+		return GPIO_RESULT_INVALID_DATA;
-+
-+	{
-+		uint32_t value;
-+
-+		value = dal_read_reg(
-+			ptr->ctx,
-+			pin->addr.DC_HPD_TOGGLE_FILT_CNTL);
-+
-+		set_reg_field_value(
-+			value,
-+			config_data->config.hpd.delay_on_connect / 10,
-+			DC_HPD_TOGGLE_FILT_CNTL,
-+			DC_HPD_CONNECT_INT_DELAY);
-+
-+		set_reg_field_value(
-+			value,
-+			config_data->config.hpd.delay_on_disconnect / 10,
-+			DC_HPD_TOGGLE_FILT_CNTL,
-+			DC_HPD_DISCONNECT_INT_DELAY);
-+
-+		dal_write_reg(
-+			ptr->ctx,
-+			pin->addr.DC_HPD_TOGGLE_FILT_CNTL,
-+			value);
-+
-+	}
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = dal_hw_gpio_open,
-+	.get_value = get_value,
-+	.set_value = dal_hw_gpio_set_value,
-+	.set_config = set_config,
-+	.change_mode = dal_hw_gpio_change_mode,
-+	.close = dal_hw_gpio_close,
-+};
-+
-+static bool construct(
-+	struct hw_hpd_dce110 *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	const struct hw_gpio_generic_dce110_init *init;
-+
-+	if (id != GPIO_ID_HPD) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if (!dal_hw_hpd_construct(&pin->base, id, en, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	pin->base.base.base.funcs = &funcs;
-+
-+	init = hw_gpio_generic_dce110_init + en;
-+
-+	pin->base.base.pin_reg = init->hw_gpio_data_reg;
-+
-+	pin->addr = init->addr;
-+
-+	return true;
-+}
-+
-+struct hw_gpio_pin *dal_hw_hpd_dce110_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_hpd_dce110 *pin = dc_service_alloc(ctx, sizeof(struct hw_hpd_dce110));
-+
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(pin, id, en, ctx))
-+		return &pin->base.base.base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, pin);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h
-new file mode 100644
-index 0000000..d032f4b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_HPD_DCE110_H__
-+#define __DAL_HW_HPD_DCE110_H__
-+
-+struct hw_hpd_dce110_addr {
-+	uint32_t DC_HPD_INT_STATUS;
-+	uint32_t DC_HPD_TOGGLE_FILT_CNTL;
-+};
-+
-+struct hw_hpd_dce110 {
-+	struct hw_hpd base;
-+	struct hw_hpd_dce110_addr addr;
-+};
-+
-+#define HPD_DCE110_FROM_BASE(hpd_base) \
-+	container_of((HW_HPD_FROM_BASE(hpd_base)), struct hw_hpd_dce110, base)
-+
-+struct hw_gpio_pin *dal_hw_hpd_dce110_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif /*__DAL_HW_HPD_DCE110_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-new file mode 100644
-index 0000000..05ac0b2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-@@ -0,0 +1,440 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dal_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_translate.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "hw_translate_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#include "../hw_gpio_pin.h"
-+#include "../hw_dvo.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+static bool offset_to_id(
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_id *id,
-+	uint32_t *en)
-+{
-+	switch (offset) {
-+	/* DVO */
-+	case mmDC_GPIO_DVODATA_A:
-+		switch (mask) {
-+		case BUNDLE_A_MASK:
-+			*id = GPIO_ID_DVO12;
-+			*en = GPIO_DVO12_A;
-+			return true;
-+		case BUNDLE_B_MASK:
-+			*id = GPIO_ID_DVO12;
-+			*en = GPIO_DVO12_B;
-+			return true;
-+		case DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK:
-+			*id = GPIO_ID_DVO24;
-+			*en = 0;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* GENERIC */
-+	case mmDC_GPIO_GENERIC_A:
-+		*id = GPIO_ID_GENERIC;
-+		switch (mask) {
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
-+			*en = GPIO_GENERIC_A;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
-+			*en = GPIO_GENERIC_B;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
-+			*en = GPIO_GENERIC_C;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
-+			*en = GPIO_GENERIC_D;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
-+			*en = GPIO_GENERIC_E;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
-+			*en = GPIO_GENERIC_F;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
-+			*en = GPIO_GENERIC_G;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* HPD */
-+	case mmDC_GPIO_HPD_A:
-+		*id = GPIO_ID_HPD;
-+		switch (mask) {
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
-+			*en = GPIO_HPD_1;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
-+			*en = GPIO_HPD_2;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
-+			*en = GPIO_HPD_3;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
-+			*en = GPIO_HPD_4;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
-+			*en = GPIO_HPD_5;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
-+			*en = GPIO_HPD_6;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* SYNCA */
-+	case mmDC_GPIO_SYNCA_A:
-+		*id = GPIO_ID_SYNC;
-+		switch (mask) {
-+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
-+			*en = GPIO_SYNC_HSYNC_A;
-+			return true;
-+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
-+			*en = GPIO_SYNC_VSYNC_A;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* mmDC_GPIO_GENLK_MASK */
-+	case mmDC_GPIO_GENLK_A:
-+		*id = GPIO_ID_GSL;
-+		switch (mask) {
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_CLOCK;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_VSYNC;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_A;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_B;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* DDC */
-+	/* we don't care about the GPIO_ID for DDC
-+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-+	 * directly in the create method */
-+	case mmDC_GPIO_DDC1_A:
-+		*en = GPIO_DDC_LINE_DDC1;
-+		return true;
-+	case mmDC_GPIO_DDC2_A:
-+		*en = GPIO_DDC_LINE_DDC2;
-+		return true;
-+	case mmDC_GPIO_DDC3_A:
-+		*en = GPIO_DDC_LINE_DDC3;
-+		return true;
-+	case mmDC_GPIO_DDC4_A:
-+		*en = GPIO_DDC_LINE_DDC4;
-+		return true;
-+	case mmDC_GPIO_DDC5_A:
-+		*en = GPIO_DDC_LINE_DDC5;
-+		return true;
-+	case mmDC_GPIO_DDC6_A:
-+		*en = GPIO_DDC_LINE_DDC6;
-+		return true;
-+	case mmDC_GPIO_DDCVGA_A:
-+		*en = GPIO_DDC_LINE_DDC_VGA;
-+		return true;
-+	/* GPIO_I2CPAD */
-+	case mmDC_GPIO_I2CPAD_A:
-+		*en = GPIO_DDC_LINE_I2C_PAD;
-+		return true;
-+	/* Not implemented */
-+	case mmDC_GPIO_PWRSEQ_A:
-+	case mmDC_GPIO_PAD_STRENGTH_1:
-+	case mmDC_GPIO_PAD_STRENGTH_2:
-+	case mmDC_GPIO_DEBUG:
-+		return false;
-+	/* UNEXPECTED */
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+static bool id_to_offset(
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct gpio_pin_info *info)
-+{
-+	bool result = true;
-+
-+	switch (id) {
-+	case GPIO_ID_DVO12:
-+		info->offset = mmDC_GPIO_DVODATA_A;
-+		switch (en) {
-+		case GPIO_DVO12_A:
-+			info->mask = BUNDLE_A_MASK;
-+		break;
-+		case GPIO_DVO12_B:
-+			info->mask = BUNDLE_B_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_DATA:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GENERIC:
-+		info->offset = mmDC_GPIO_GENERIC_A;
-+		switch (en) {
-+		case GPIO_GENERIC_A:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
-+		break;
-+		case GPIO_GENERIC_B:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
-+		break;
-+		case GPIO_GENERIC_C:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
-+		break;
-+		case GPIO_GENERIC_D:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
-+		break;
-+		case GPIO_GENERIC_E:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
-+		break;
-+		case GPIO_GENERIC_F:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
-+		break;
-+		case GPIO_GENERIC_G:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		info->offset = mmDC_GPIO_HPD_A;
-+		switch (en) {
-+		case GPIO_HPD_1:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
-+		break;
-+		case GPIO_HPD_2:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
-+		break;
-+		case GPIO_HPD_3:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
-+		break;
-+		case GPIO_HPD_4:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
-+		break;
-+		case GPIO_HPD_5:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
-+		break;
-+		case GPIO_HPD_6:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_VSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_HSYNC_B:
-+		case GPIO_SYNC_VSYNC_B:
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
-+		break;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask =
-+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DVO24:
-+		info->offset = mmDC_GPIO_DVODATA_A;
-+		info->mask = DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK;
-+	break;
-+	case GPIO_ID_DVO1:
-+	case GPIO_ID_VIP_PAD:
-+	default:
-+		ASSERT_CRITICAL(false);
-+		result = false;
-+	}
-+
-+	if (result) {
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask_y = info->mask;
-+		info->mask_en = info->mask;
-+		info->mask_mask = info->mask;
-+	}
-+
-+	return result;
-+}
-+
-+/* function table */
-+static const struct hw_translate_funcs funcs = {
-+	.offset_to_id = offset_to_id,
-+	.id_to_offset = id_to_offset,
-+};
-+
-+/*
-+ * dal_hw_translate_dce110_init
-+ *
-+ * @brief
-+ * Initialize Hw translate function pointers.
-+ *
-+ * @param
-+ * struct hw_translate *tr - [out] struct of function pointers
-+ *
-+ */
-+void dal_hw_translate_dce110_init(struct hw_translate *tr)
-+{
-+	tr->funcs = &funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h
-new file mode 100644
-index 0000000..4d16e09
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DCE110_H__
-+#define __DAL_HW_TRANSLATE_DCE110_H__
-+
-+struct hw_translate;
-+
-+/* Initialize Hw translate function pointers */
-+void dal_hw_translate_dce110_init(struct hw_translate *tr);
-+
-+#endif /* __DAL_HW_TRANSLATE_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-new file mode 100644
-index 0000000..548b1cf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-@@ -0,0 +1,290 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/gpio_interface.h"
-+#include "include/ddc_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+#include "gpio_service.h"
-+#include "gpio.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "ddc.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+enum gpio_result dal_ddc_open(
-+	struct ddc *ddc,
-+	enum gpio_mode mode,
-+	enum gpio_ddc_config_type config_type)
-+{
-+	enum gpio_result result;
-+
-+	struct gpio_ddc_open_options data_options;
-+	struct gpio_ddc_open_options clock_options;
-+	struct gpio_config_data config_data;
-+
-+	result = dal_gpio_open_ex(ddc->pin_data, mode, &data_options);
-+
-+	if (result != GPIO_RESULT_OK) {
-+		BREAK_TO_DEBUGGER();
-+		return result;
-+	}
-+
-+	result = dal_gpio_open_ex(ddc->pin_clock, mode, &clock_options);
-+
-+	if (result != GPIO_RESULT_OK) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure;
-+	}
-+
-+	/* DDC clock and data pins should belong
-+	 * to the same DDC block id,
-+	 * we use the data pin to set the pad mode. */
-+
-+	if (mode == GPIO_MODE_INPUT)
-+		/* this is from detect_sink_type,
-+		 * we need extra delay there */
-+		config_data.type = GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE;
-+	else
-+		config_data.type = GPIO_CONFIG_TYPE_DDC;
-+
-+	config_data.config.ddc.type = config_type;
-+	config_data.config.ddc.data_en_bit_present =
-+		data_options.en_bit_present;
-+	config_data.config.ddc.clock_en_bit_present =
-+		clock_options.en_bit_present;
-+
-+	result = dal_gpio_set_config(ddc->pin_data, &config_data);
-+
-+	if (result == GPIO_RESULT_OK)
-+		return result;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dal_gpio_close(ddc->pin_clock);
-+
-+failure:
-+	dal_gpio_close(ddc->pin_data);
-+
-+	return result;
-+}
-+
-+enum gpio_result dal_ddc_get_clock(
-+	const struct ddc *ddc,
-+	uint32_t *value)
-+{
-+	return dal_gpio_get_value(ddc->pin_clock, value);
-+}
-+
-+enum gpio_result dal_ddc_set_clock(
-+	const struct ddc *ddc,
-+	uint32_t value)
-+{
-+	return dal_gpio_set_value(ddc->pin_clock, value);
-+}
-+
-+enum gpio_result dal_ddc_get_data(
-+	const struct ddc *ddc,
-+	uint32_t *value)
-+{
-+	return dal_gpio_get_value(ddc->pin_data, value);
-+}
-+
-+enum gpio_result dal_ddc_set_data(
-+	const struct ddc *ddc,
-+	uint32_t value)
-+{
-+	return dal_gpio_set_value(ddc->pin_data, value);
-+}
-+
-+enum gpio_result dal_ddc_change_mode(
-+	struct ddc *ddc,
-+	enum gpio_mode mode)
-+{
-+	enum gpio_result result;
-+
-+	enum gpio_mode original_mode =
-+		dal_gpio_get_mode(ddc->pin_data);
-+
-+	result = dal_gpio_change_mode(ddc->pin_data, mode);
-+
-+	/* [anaumov] DAL2 code returns GPIO_RESULT_NON_SPECIFIC_ERROR
-+	 * in case of failures;
-+	 * set_mode() is so that, in case of failure,
-+	 * we must explicitly set original mode */
-+
-+	if (result != GPIO_RESULT_OK)
-+		goto failure;
-+
-+	result = dal_gpio_change_mode(ddc->pin_clock, mode);
-+
-+	if (result == GPIO_RESULT_OK)
-+		return result;
-+
-+	dal_gpio_change_mode(ddc->pin_clock, original_mode);
-+
-+failure:
-+	dal_gpio_change_mode(ddc->pin_data, original_mode);
-+
-+	return result;
-+}
-+
-+bool dal_ddc_is_hw_supported(
-+	const struct ddc *ddc)
-+{
-+	return ddc->hw_info.hw_supported;
-+}
-+
-+enum gpio_ddc_line dal_ddc_get_line(
-+	const struct ddc *ddc)
-+{
-+	return (enum gpio_ddc_line)dal_gpio_get_enum(ddc->pin_data);
-+}
-+
-+bool dal_ddc_check_line_aborted(
-+	const struct ddc *self)
-+{
-+	/* No arbitration with VBIOS is performed since DCE 6.0 */
-+
-+	return false;
-+}
-+
-+enum gpio_result dal_ddc_set_config(
-+	struct ddc *ddc,
-+	enum gpio_ddc_config_type config_type)
-+{
-+	struct gpio_config_data config_data;
-+
-+	config_data.type = GPIO_CONFIG_TYPE_DDC;
-+
-+	config_data.config.ddc.type = config_type;
-+	config_data.config.ddc.data_en_bit_present = false;
-+	config_data.config.ddc.clock_en_bit_present = false;
-+
-+	return dal_gpio_set_config(ddc->pin_data, &config_data);
-+}
-+
-+void dal_ddc_close(
-+	struct ddc *ddc)
-+{
-+	dal_gpio_close(ddc->pin_clock);
-+	dal_gpio_close(ddc->pin_data);
-+}
-+
-+/*
-+ * @brief
-+ * Creation and destruction
-+ */
-+
-+struct ddc *dal_gpio_create_ddc(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	struct gpio_ddc_hw_info *info)
-+{
-+	enum gpio_id id;
-+	uint32_t en;
-+	struct ddc *ddc;
-+
-+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en))
-+		return NULL;
-+
-+	ddc = dc_service_alloc(service->ctx, sizeof(struct ddc));
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	ddc->pin_data = dal_gpio_service_create_gpio_ex(
-+		service, GPIO_ID_DDC_DATA, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+
-+	if (!ddc->pin_data) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_1;
-+	}
-+
-+	ddc->pin_clock = dal_gpio_service_create_gpio_ex(
-+		service, GPIO_ID_DDC_CLOCK, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+
-+	if (!ddc->pin_clock) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_2;
-+	}
-+
-+	ddc->hw_info = *info;
-+
-+	ddc->ctx = service->ctx;
-+
-+	return ddc;
-+
-+failure_2:
-+	dal_gpio_service_destroy_gpio(&ddc->pin_data);
-+
-+failure_1:
-+	dc_service_free(service->ctx, ddc);
-+
-+	return NULL;
-+}
-+
-+static void destruct(struct ddc *ddc)
-+{
-+	dal_ddc_close(ddc);
-+	dal_gpio_service_destroy_gpio(&ddc->pin_data);
-+	dal_gpio_service_destroy_gpio(&ddc->pin_clock);
-+
-+}
-+
-+void dal_gpio_destroy_ddc(
-+	struct ddc **ddc)
-+{
-+	if (!ddc || !*ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	destruct(*ddc);
-+	dc_service_free((*ddc)->ctx, *ddc);
-+
-+	*ddc = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
-new file mode 100644
-index 0000000..2631571
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
-@@ -0,0 +1,45 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DDC_H__
-+#define __DAL_DDC_H__
-+
-+struct ddc {
-+	struct gpio *pin_data;
-+	struct gpio *pin_clock;
-+	struct gpio_ddc_hw_info hw_info;
-+	struct dc_context *ctx;
-+};
-+
-+struct ddc *dal_gpio_create_ddc(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	struct gpio_ddc_hw_info *info);
-+
-+void dal_gpio_destroy_ddc(
-+	struct ddc **ddc);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
-new file mode 100644
-index 0000000..a237d25
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
-@@ -0,0 +1,138 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_interface.h"
-+#include "include/dvo_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+#include "gpio_service.h"
-+#include "gpio.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "dvo.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+enum gpio_result dal_dvo_open(
-+	struct dvo *dvo,
-+	enum gpio_mode mode)
-+{
-+	return dal_gpio_open(dvo->pin, mode);
-+}
-+
-+enum gpio_result dal_dvo_get_value(
-+	const struct dvo *dvo,
-+	uint32_t *value)
-+{
-+	return dal_gpio_get_value(dvo->pin, value);
-+}
-+
-+enum gpio_result dal_dvo_set_value(
-+	const struct dvo *dvo,
-+	uint32_t value)
-+{
-+	return dal_gpio_set_value(dvo->pin, value);
-+}
-+
-+void dal_dvo_close(
-+	struct dvo *dvo)
-+{
-+	dal_gpio_close(dvo->pin);
-+}
-+
-+/*
-+ * @brief
-+ * Creation and destruction
-+ */
-+
-+struct dvo *dal_dvo_create(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct dvo *dvo;
-+
-+	switch (id) {
-+	case GPIO_ID_DVO12:
-+		if ((en < GPIO_DVO12_MIN) || (en > GPIO_DVO12_MAX)) {
-+			BREAK_TO_DEBUGGER();
-+			return NULL;
-+		}
-+	break;
-+	case GPIO_ID_DVO24:
-+		if ((en < GPIO_DVO24_MIN) || (en > GPIO_DVO24_MAX)) {
-+			BREAK_TO_DEBUGGER();
-+			return NULL;
-+		}
-+	break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dvo = dc_service_alloc(service->ctx, sizeof(struct dvo));
-+
-+	if (!dvo) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dvo->pin = NULL;
-+	dvo->ctx = service->ctx;
-+
-+	return dvo;
-+}
-+
-+void dal_dvo_destroy(
-+	struct dvo **dvo)
-+{
-+	if (!dvo || !*dvo) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dal_dvo_close(*dvo);
-+
-+	dc_service_free((*dvo)->ctx, *dvo);
-+
-+	*dvo = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
-new file mode 100644
-index 0000000..0d98b51
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DVO_H__
-+#define __DAL_DVO_H__
-+
-+struct dvo {
-+	struct gpio *pin;
-+	struct dc_context *ctx;
-+};
-+
-+struct dvo *dal_dvo_create(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+void dal_dvo_destroy(
-+	struct dvo **dvo);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio.h b/drivers/gpu/drm/amd/dal/dc/gpio/gpio.h
-new file mode 100644
-index 0000000..7fcbb69
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio.h
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_H__
-+#define __DAL_GPIO_H__
-+
-+struct gpio {
-+	struct gpio_service *service;
-+	struct hw_gpio_pin *pin;
-+	enum gpio_id id;
-+	uint32_t en;
-+	enum gpio_mode mode;
-+	/* when GPIO comes from VBIOS, it has defined output state */
-+	enum gpio_pin_output_state output_state;
-+};
-+
-+struct gpio *dal_gpio_create(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_pin_output_state output_state);
-+
-+void dal_gpio_destroy(
-+	struct gpio **ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-new file mode 100644
-index 0000000..6115f59
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-@@ -0,0 +1,279 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/gpio_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+#include "gpio_service.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "gpio.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Public API
-+ */
-+
-+enum gpio_result dal_gpio_open(
-+	struct gpio *gpio,
-+	enum gpio_mode mode)
-+{
-+	return dal_gpio_open_ex(gpio, mode, NULL);
-+}
-+
-+enum gpio_result dal_gpio_open_ex(
-+	struct gpio *gpio,
-+	enum gpio_mode mode,
-+	void *options)
-+{
-+	if (gpio->pin) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_ALREADY_OPENED;
-+	}
-+
-+	gpio->mode = mode;
-+
-+	return dal_gpio_service_open(
-+		gpio->service, gpio->id, gpio->en, mode, options, &gpio->pin);
-+}
-+
-+enum gpio_result dal_gpio_get_value(
-+	const struct gpio *gpio,
-+	uint32_t *value)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->get_value(gpio->pin, value);
-+}
-+
-+enum gpio_result dal_gpio_set_value(
-+	const struct gpio *gpio,
-+	uint32_t value)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->set_value(gpio->pin, value);
-+}
-+
-+enum gpio_mode dal_gpio_get_mode(
-+	const struct gpio *gpio)
-+{
-+	return gpio->mode;
-+}
-+
-+enum gpio_result dal_gpio_change_mode(
-+	struct gpio *gpio,
-+	enum gpio_mode mode)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->change_mode(gpio->pin, mode);
-+}
-+
-+enum gpio_id dal_gpio_get_id(
-+	const struct gpio *gpio)
-+{
-+	return gpio->id;
-+}
-+
-+uint32_t dal_gpio_get_enum(
-+	const struct gpio *gpio)
-+{
-+	return gpio->en;
-+}
-+
-+enum gpio_result dal_gpio_set_config(
-+	struct gpio *gpio,
-+	const struct gpio_config_data *config_data)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->set_config(gpio->pin, config_data);
-+}
-+
-+enum gpio_result dal_gpio_get_pin_info(
-+	const struct gpio *gpio,
-+	struct gpio_pin_info *pin_info)
-+{
-+	return gpio->service->translate.funcs->id_to_offset(
-+		gpio->id, gpio->en, pin_info) ?
-+		GPIO_RESULT_OK : GPIO_RESULT_INVALID_DATA;
-+}
-+
-+enum sync_source dal_gpio_get_sync_source(
-+	const struct gpio *gpio)
-+{
-+	switch (gpio->id) {
-+	case GPIO_ID_GENERIC:
-+		switch (gpio->en) {
-+		case GPIO_GENERIC_A:
-+			return SYNC_SOURCE_IO_GENERIC_A;
-+		case GPIO_GENERIC_B:
-+			return SYNC_SOURCE_IO_GENERIC_B;
-+		case GPIO_GENERIC_C:
-+			return SYNC_SOURCE_IO_GENERIC_C;
-+		case GPIO_GENERIC_D:
-+			return SYNC_SOURCE_IO_GENERIC_D;
-+		case GPIO_GENERIC_E:
-+			return SYNC_SOURCE_IO_GENERIC_E;
-+		case GPIO_GENERIC_F:
-+			return SYNC_SOURCE_IO_GENERIC_F;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (gpio->en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			return SYNC_SOURCE_IO_HSYNC_A;
-+		case GPIO_SYNC_VSYNC_A:
-+			return SYNC_SOURCE_IO_VSYNC_A;
-+		case GPIO_SYNC_HSYNC_B:
-+			return SYNC_SOURCE_IO_HSYNC_B;
-+		case GPIO_SYNC_VSYNC_B:
-+			return SYNC_SOURCE_IO_VSYNC_B;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		switch (gpio->en) {
-+		case GPIO_HPD_1:
-+			return SYNC_SOURCE_IO_HPD1;
-+		case GPIO_HPD_2:
-+			return SYNC_SOURCE_IO_HPD2;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (gpio->en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			return SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			return SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			return SYNC_SOURCE_GSL_IO_SWAPLOCK_A;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			return SYNC_SOURCE_GSL_IO_SWAPLOCK_B;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	default:
-+		return SYNC_SOURCE_NONE;
-+	}
-+}
-+
-+enum gpio_pin_output_state dal_gpio_get_output_state(
-+	const struct gpio *gpio)
-+{
-+	return gpio->output_state;
-+}
-+
-+void dal_gpio_close(
-+	struct gpio *gpio)
-+{
-+	if (!gpio)
-+		return;
-+
-+	dal_gpio_service_close(gpio->service, &gpio->pin);
-+
-+	gpio->mode = GPIO_MODE_UNKNOWN;
-+}
-+
-+/*
-+ * @brief
-+ * Creation and destruction
-+ */
-+
-+struct gpio *dal_gpio_create(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_pin_output_state output_state)
-+{
-+	struct gpio *gpio = dc_service_alloc(service->ctx, sizeof(struct gpio));
-+
-+	if (!gpio) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	gpio->service = service;
-+	gpio->pin = NULL;
-+	gpio->id = id;
-+	gpio->en = en;
-+	gpio->mode = GPIO_MODE_UNKNOWN;
-+	gpio->output_state = output_state;
-+
-+	return gpio;
-+}
-+
-+void dal_gpio_destroy(
-+	struct gpio **gpio)
-+{
-+	if (!gpio || !*gpio) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	dal_gpio_close(*gpio);
-+
-+	dc_service_free((*gpio)->service->ctx, *gpio);
-+
-+	*gpio = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-new file mode 100644
-index 0000000..08e046b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -0,0 +1,470 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dal_services.h"
-+#include "include/gpio_interface.h"
-+#include "include/ddc_interface.h"
-+#include "include/dvo_interface.h"
-+#include "include/irq_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "gpio_service.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "hw_gpio_pin.h"
-+#include "gpio.h"
-+#include "dvo.h"
-+#include "ddc.h"
-+#include "irq.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Public API.
-+ */
-+
-+struct gpio_service *dal_gpio_service_create(
-+	enum dce_version dce_version,
-+	struct dc_context *ctx)
-+{
-+	struct gpio_service *service;
-+
-+	uint32_t index_of_id;
-+
-+	service = dc_service_alloc(ctx, sizeof(struct gpio_service));
-+
-+	if (!service) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (!dal_hw_translate_init(&service->translate, dce_version)) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_1;
-+	}
-+
-+	if (!dal_hw_factory_init(&service->factory, dce_version)) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_1;
-+	}
-+
-+	/* allocate and initialize business storage */
-+	{
-+		const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+		index_of_id = 0;
-+		service->ctx = ctx;
-+
-+		do {
-+			uint32_t number_of_bits =
-+				service->factory.number_of_pins[index_of_id];
-+
-+			uint32_t number_of_uints =
-+				(number_of_bits + bits_per_uint - 1) /
-+				bits_per_uint;
-+
-+			uint32_t *slot;
-+
-+			if (number_of_bits) {
-+				uint32_t index_of_uint = 0;
-+
-+				slot = dc_service_alloc(
-+					ctx,
-+					number_of_uints * sizeof(uint32_t));
-+
-+				if (!slot) {
-+					BREAK_TO_DEBUGGER();
-+					goto failure_2;
-+				}
-+
-+				do {
-+					slot[index_of_uint] = 0;
-+
-+					++index_of_uint;
-+				} while (index_of_uint < number_of_uints);
-+			} else
-+				slot = NULL;
-+
-+			service->busyness[index_of_id] = slot;
-+
-+			++index_of_id;
-+		} while (index_of_id < GPIO_ID_COUNT);
-+	}
-+
-+	return service;
-+
-+failure_2:
-+	while (index_of_id) {
-+		uint32_t *slot;
-+
-+		--index_of_id;
-+
-+		slot = service->busyness[index_of_id];
-+
-+		if (slot)
-+			dc_service_free(ctx, slot);
-+	};
-+
-+failure_1:
-+	dc_service_free(ctx, service);
-+
-+	return NULL;
-+}
-+
-+struct gpio *dal_gpio_service_create_gpio(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_pin_output_state output_state)
-+{
-+	enum gpio_id id;
-+	uint32_t en;
-+
-+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	return dal_gpio_create(service, id, en, output_state);
-+}
-+
-+struct gpio *dal_gpio_service_create_gpio_ex(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_pin_output_state output_state)
-+{
-+	return dal_gpio_create(service, id, en, output_state);
-+}
-+
-+void dal_gpio_service_destroy_gpio(
-+	struct gpio **gpio)
-+{
-+	dal_gpio_destroy(gpio);
-+}
-+
-+struct ddc *dal_gpio_service_create_ddc(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	struct gpio_ddc_hw_info *info)
-+{
-+	return dal_gpio_create_ddc(service, offset, mask, info);
-+}
-+
-+void dal_gpio_service_destroy_ddc(
-+	struct ddc **ddc)
-+{
-+	dal_gpio_destroy_ddc(ddc);
-+}
-+
-+struct dvo *dal_gpio_service_create_dvo(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask)
-+{
-+	enum gpio_id id;
-+	uint32_t en;
-+
-+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	return dal_dvo_create(service, id, en);
-+}
-+
-+struct dvo *dal_gpio_service_create_dvo_ex(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	return dal_dvo_create(service, id, en);
-+}
-+
-+void dal_gpio_service_destroy_dvo(
-+	struct dvo **dvo)
-+{
-+	dal_dvo_destroy(dvo);
-+}
-+
-+struct irq *dal_gpio_service_create_irq(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask)
-+{
-+	enum gpio_id id;
-+	uint32_t en;
-+
-+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	return dal_gpio_create_irq(service, id, en);
-+}
-+
-+struct irq *dal_gpio_service_create_irq_ex(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	return dal_gpio_create_irq(service, id, en);
-+}
-+
-+void dal_gpio_service_destroy_irq(
-+	struct irq **irq)
-+{
-+	dal_gpio_destroy_irq(irq);
-+}
-+
-+void dal_gpio_service_destroy(
-+	struct gpio_service **ptr)
-+{
-+	if (!ptr || !*ptr) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/* free business storage */
-+	{
-+		uint32_t index_of_id = 0;
-+
-+		do {
-+			uint32_t *slot = (*ptr)->busyness[index_of_id];
-+
-+			if (slot)
-+				dc_service_free((*ptr)->ctx, slot);
-+
-+			++index_of_id;
-+		} while (index_of_id < GPIO_ID_COUNT);
-+	}
-+
-+	dc_service_free((*ptr)->ctx, *ptr);
-+
-+	*ptr = NULL;
-+}
-+
-+/*
-+ * @brief
-+ * Private API.
-+ */
-+
-+static bool is_pin_busy(
-+	const struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	const uint32_t *slot = service->busyness[id] + (en / bits_per_uint);
-+
-+	return 0 != (*slot & (1 << (en % bits_per_uint)));
-+}
-+
-+static bool is_some_pin_busy(
-+	const struct gpio_service *service,
-+	enum gpio_id id)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	uint32_t index_of_uint = 0;
-+
-+	uint32_t number_of_uints =
-+		service->factory.number_of_pins[id];
-+
-+	number_of_uints = (number_of_uints + bits_per_uint - 1) / bits_per_uint;
-+
-+	while (index_of_uint < number_of_uints) {
-+		if (service->busyness[id][index_of_uint])
-+			return true;
-+
-+		++index_of_uint;
-+	};
-+
-+	return false;
-+}
-+
-+static void set_pin_busy(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	service->busyness[id][en / bits_per_uint] |=
-+		(1 << (en % bits_per_uint));
-+}
-+
-+static void set_pin_free(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	service->busyness[id][en / bits_per_uint] &=
-+		~(1 << (en % bits_per_uint));
-+}
-+
-+enum gpio_result dal_gpio_service_open(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_mode mode,
-+	void *options,
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_gpio_pin *pin;
-+
-+	if (!service->busyness[id]) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_OPEN_FAILED;
-+	}
-+
-+	if (is_pin_busy(service, id, en)) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_DEVICE_BUSY;
-+	}
-+
-+	switch (id) {
-+	case GPIO_ID_DVO1:
-+		/* [anaumov] not implemented, commented with "to do" */
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	case GPIO_ID_DVO12:
-+		if (!service->busyness[GPIO_ID_DVO24]) {
-+			ASSERT_CRITICAL(false);
-+			return GPIO_RESULT_OPEN_FAILED;
-+		}
-+
-+		if (is_some_pin_busy(service, GPIO_ID_DVO24)) {
-+			ASSERT_CRITICAL(false);
-+			return GPIO_RESULT_DEVICE_BUSY;
-+		}
-+
-+		pin = service->factory.funcs->create_dvo(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_DVO24:
-+		if (!service->busyness[GPIO_ID_DVO12]) {
-+			ASSERT_CRITICAL(false);
-+			return GPIO_RESULT_OPEN_FAILED;
-+		}
-+
-+		if (is_some_pin_busy(service, GPIO_ID_DVO12)) {
-+			ASSERT_CRITICAL(false);
-+			return GPIO_RESULT_DEVICE_BUSY;
-+		}
-+
-+		pin = service->factory.funcs->create_dvo(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_DDC_DATA:
-+		pin = service->factory.funcs->create_ddc_data(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		pin = service->factory.funcs->create_ddc_clock(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_GENERIC:
-+		pin = service->factory.funcs->create_generic(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_HPD:
-+		pin = service->factory.funcs->create_hpd(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_GPIO_PAD:
-+		pin = service->factory.funcs->create_gpio_pad(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_SYNC:
-+		pin = service->factory.funcs->create_sync(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_GSL:
-+		pin = service->factory.funcs->create_gsl(
-+			service->ctx, id, en);
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	if (!pin->funcs->open(pin, mode, options)) {
-+		ASSERT_CRITICAL(false);
-+		dal_gpio_service_close(service, &pin);
-+		return GPIO_RESULT_OPEN_FAILED;
-+	}
-+
-+	set_pin_busy(service, id, en);
-+	*ptr = pin;
-+	return GPIO_RESULT_OK;
-+}
-+
-+void dal_gpio_service_close(
-+	struct gpio_service *service,
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_gpio_pin *pin;
-+
-+	if (!ptr) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	pin = *ptr;
-+
-+	if (pin) {
-+		set_pin_free(service, pin->id, pin->en);
-+
-+		pin->funcs->close(pin);
-+
-+		pin->funcs->destroy(ptr);
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h
-new file mode 100644
-index 0000000..a17c438
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h
-@@ -0,0 +1,57 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_SERVICE_H__
-+#define __DAL_GPIO_SERVICE_H__
-+
-+struct hw_translate;
-+struct hw_factory;
-+
-+struct gpio_service {
-+	struct dc_context *ctx;
-+	struct hw_translate translate;
-+	struct hw_factory factory;
-+	/*
-+	 * @brief
-+	 * Business storage.
-+	 * For each member of 'enum gpio_id',
-+	 * store array of bits (packed into uint32_t slots),
-+	 * index individual bit by 'en' value */
-+	uint32_t *busyness[GPIO_ID_COUNT];
-+};
-+
-+enum gpio_result dal_gpio_service_open(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_mode mode,
-+	void *options,
-+	struct hw_gpio_pin **ptr);
-+
-+void dal_gpio_service_close(
-+	struct gpio_service *service,
-+	struct hw_gpio_pin **ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-new file mode 100644
-index 0000000..0608f16
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_gpio.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_ddc.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_HW_GPIO(ptr) \
-+	container_of((ptr), struct hw_ddc, base)
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	FROM_HW_GPIO(container_of((ptr), struct hw_gpio, base))
-+
-+bool dal_hw_ddc_open(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode,
-+	void *options)
-+{
-+	struct hw_ddc *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	uint32_t en;
-+
-+	if (!options) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	/* get the EN bit before overwriting it */
-+
-+	dal_hw_gpio_get_reg_value(
-+		ptr->ctx,
-+		&pin->base.pin_reg.DC_GPIO_DATA_EN,
-+		&en);
-+
-+	((struct gpio_ddc_open_options *)options)->en_bit_present = (en != 0);
-+
-+	return dal_hw_gpio_open(ptr, mode, options);
-+}
-+
-+bool dal_hw_ddc_construct(
-+	struct hw_ddc *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_hw_gpio_construct(&pin->base, id, en, ctx))
-+		return false;
-+
-+	pin->mask.DC_GPIO_DDC_MASK_MASK = 0;
-+	pin->mask.DC_GPIO_DDC_PD_EN_MASK = 0;
-+	pin->mask.DC_GPIO_DDC_RECV_MASK = 0;
-+	pin->mask.AUX_PAD_MODE_MASK = 0;
-+	pin->mask.AUX_POL_MASK = 0;
-+	pin->mask.DC_GPIO_DDCCLK_STR_MASK = 0;
-+
-+	return true;
-+}
-+
-+void dal_hw_ddc_destruct(
-+	struct hw_ddc *pin)
-+{
-+	dal_hw_gpio_destruct(&pin->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h
-new file mode 100644
-index 0000000..a3a727c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h
-@@ -0,0 +1,60 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_DDC_H__
-+#define __DAL_HW_DDC_H__
-+
-+struct hw_ddc_mask {
-+	uint32_t DC_GPIO_DDC_MASK_MASK;
-+	uint32_t DC_GPIO_DDC_PD_EN_MASK;
-+	uint32_t DC_GPIO_DDC_RECV_MASK;
-+	uint32_t AUX_PAD_MODE_MASK;
-+	uint32_t AUX_POL_MASK;
-+	uint32_t DC_GPIO_DDCCLK_STR_MASK;
-+};
-+
-+struct hw_ddc {
-+	struct hw_gpio base;
-+	struct hw_ddc_mask mask;
-+};
-+
-+#define HW_DDC_FROM_BASE(hw_gpio) \
-+	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_ddc, base)
-+
-+bool dal_hw_ddc_construct(
-+	struct hw_ddc *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+void dal_hw_ddc_destruct(
-+	struct hw_ddc *pin);
-+
-+bool dal_hw_ddc_open(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode,
-+	void *options);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
-new file mode 100644
-index 0000000..a5a07f0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
-@@ -0,0 +1,318 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio_pin.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_dvo.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	container_of((ptr), struct hw_dvo, base)
-+
-+static void store_dvo_registers(
-+	struct hw_dvo *pin)
-+{
-+	pin->store.dvo_mask = dal_read_reg(
-+		pin->base.ctx, pin->addr.DC_GPIO_DVODATA_MASK);
-+	pin->store.dvo_en = dal_read_reg(
-+		pin->base.ctx, pin->addr.DC_GPIO_DVODATA_EN);
-+	pin->store.dvo_data_a = dal_read_reg(
-+		pin->base.ctx, pin->addr.DC_GPIO_DVODATA_A);
-+}
-+
-+static void restore_dvo_registers(
-+	struct hw_dvo *pin)
-+{
-+	{
-+		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_MASK;
-+
-+		uint32_t data = dal_read_reg(pin->base.ctx, addr);
-+
-+		data &= ~pin->dvo_mask;
-+		data |= pin->store.dvo_mask & pin->dvo_mask;
-+
-+		dal_write_reg(pin->base.ctx, addr, data);
-+	}
-+
-+	{
-+		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_EN;
-+
-+		uint32_t data = dal_read_reg(pin->base.ctx, addr);
-+
-+		data &= ~pin->dvo_mask;
-+		data |= pin->store.dvo_en & pin->dvo_mask;
-+
-+		dal_write_reg(pin->base.ctx, addr, data);
-+	}
-+
-+	{
-+		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_A;
-+
-+		uint32_t data = dal_read_reg(pin->base.ctx, addr);
-+
-+		data &= ~pin->dvo_mask;
-+		data |= pin->store.dvo_data_a & pin->dvo_mask;
-+
-+		dal_write_reg(pin->base.ctx, addr, data);
-+	}
-+}
-+
-+static void program_dvo(
-+	struct hw_dvo *pin,
-+	bool output)
-+{
-+	/* Turn on Mask bits for the requested channel,
-+	 * this will enable the channel for software control. */
-+	{
-+		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_MASK;
-+
-+		uint32_t mask = dal_read_reg(pin->base.ctx, addr);
-+
-+		uint32_t data = pin->dvo_mask | mask;
-+
-+		dal_write_reg(pin->base.ctx, addr, data);
-+	}
-+
-+	/* Turn off/on the Enable bits on the requested channel,
-+	 * this will set it to Input/Output mode. */
-+	{
-+		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_EN;
-+
-+		uint32_t enable = dal_read_reg(pin->base.ctx, addr);
-+
-+		uint32_t data = output ?
-+			(pin->dvo_mask | enable) :
-+			(~pin->dvo_mask & enable);
-+
-+		dal_write_reg(pin->base.ctx, addr, data);
-+	}
-+}
-+
-+static void program_dvo_strength(
-+	struct hw_dvo *pin)
-+{
-+	const uint32_t addr = pin->addr.DVO_STRENGTH_CONTROL;
-+
-+	uint32_t data = dal_read_reg(pin->base.ctx, addr);
-+
-+	data &= ~pin->dvo_strength_mask;
-+	data |= pin->dvo_strength & pin->dvo_strength_mask;
-+
-+	dal_write_reg(pin->base.ctx, addr, data);
-+}
-+
-+static void disable_on_chip_terminators(
-+	struct hw_dvo *pin)
-+{
-+	const uint32_t addr = pin->addr.D1CRTC_MVP_CONTROL1;
-+
-+	uint32_t data = dal_read_reg(pin->base.ctx, addr);
-+
-+	pin->store.mvp_terminator_state = (data & pin->mvp_termination_mask);
-+
-+	data &= ~pin->mvp_termination_mask;
-+
-+	dal_write_reg(pin->base.ctx, addr, data);
-+}
-+
-+static void restore_on_chip_terminators(
-+	struct hw_dvo *pin)
-+{
-+	const uint32_t addr = pin->addr.D1CRTC_MVP_CONTROL1;
-+
-+	uint32_t data = dal_read_reg(pin->base.ctx, addr);
-+
-+	data &= ~pin->mvp_termination_mask;
-+
-+	if (pin->store.mvp_terminator_state)
-+		data |= pin->mvp_termination_mask;
-+
-+	dal_write_reg(pin->base.ctx, addr, data);
-+}
-+
-+bool dal_hw_dvo_open(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode,
-+	void *options)
-+{
-+	struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	store_dvo_registers(pin);
-+
-+	ptr->mode = mode;
-+
-+	switch (mode) {
-+	case GPIO_MODE_INPUT:
-+		program_dvo_strength(pin);
-+		disable_on_chip_terminators(pin);
-+		program_dvo(pin, false);
-+
-+		ptr->opened = true;
-+	break;
-+	case GPIO_MODE_OUTPUT:
-+		program_dvo_strength(pin);
-+		disable_on_chip_terminators(pin);
-+		program_dvo(pin, true);
-+
-+		ptr->opened = true;
-+	break;
-+	default:
-+		/* unsupported mode */
-+		BREAK_TO_DEBUGGER();
-+
-+		ptr->opened = false;
-+	}
-+
-+	return ptr->opened;
-+}
-+
-+enum gpio_result dal_hw_dvo_get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	const struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	if (ptr->mode != GPIO_MODE_INPUT)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	*value = dal_read_reg(ptr->ctx, pin->addr.DC_GPIO_DVODATA_Y);
-+
-+	*value &= pin->dvo_mask;
-+	*value >>= pin->dvo_shift;
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+enum gpio_result dal_hw_dvo_set_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t value)
-+{
-+	const struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	uint32_t masked_value;
-+
-+	if (ptr->mode != GPIO_MODE_OUTPUT) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	/* Ensure there is no overflow of the value written.
-+	 * Value cannot be more than 12 bits for a 12-bit channel. */
-+
-+	masked_value = value << pin->dvo_shift;
-+
-+	if (masked_value != (masked_value & pin->dvo_mask)) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_INVALID_DATA;
-+	}
-+
-+	masked_value &= pin->dvo_mask;
-+
-+	/* read the DataA register
-+	 * mask off the Bundle that we want to write to
-+	 * or the data into the register */
-+	{
-+		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_A;
-+
-+		uint32_t data = dal_read_reg(ptr->ctx, addr);
-+
-+		data &= ~pin->dvo_mask;
-+		data |= masked_value;
-+
-+		dal_write_reg(ptr->ctx, addr, data);
-+	}
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+void dal_hw_dvo_close(
-+	struct hw_gpio_pin *ptr)
-+{
-+	struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	restore_dvo_registers(pin);
-+	restore_on_chip_terminators(pin);
-+
-+	ptr->mode = GPIO_MODE_UNKNOWN;
-+
-+	ptr->opened = false;
-+}
-+
-+bool dal_hw_dvo_construct(
-+	struct hw_dvo *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	struct hw_gpio_pin *base = &pin->base;
-+
-+	if (!dal_hw_gpio_pin_construct(base, id, en, ctx))
-+		return false;
-+
-+	pin->addr.DC_GPIO_DVODATA_MASK = 0;
-+	pin->addr.DC_GPIO_DVODATA_EN = 0;
-+	pin->addr.DC_GPIO_DVODATA_A = 0;
-+	pin->addr.DC_GPIO_DVODATA_Y = 0;
-+	pin->addr.DVO_STRENGTH_CONTROL = 0;
-+	pin->addr.D1CRTC_MVP_CONTROL1 = 0;
-+
-+	pin->dvo_mask = 0;
-+	pin->dvo_shift = 0;
-+	pin->dvo_strength_mask = 0;
-+	pin->mvp_termination_mask = 0;
-+
-+	pin->dvo_strength = 0;
-+
-+	pin->store.dvo_mask = 0;
-+	pin->store.dvo_en = 0;
-+	pin->store.dvo_data_a = 0;
-+	pin->store.mvp_terminator_state = false;
-+
-+	return true;
-+}
-+
-+void dal_hw_dvo_destruct(
-+	struct hw_dvo *pin)
-+{
-+	dal_hw_gpio_pin_destruct(&pin->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
-new file mode 100644
-index 0000000..5a120c2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
-@@ -0,0 +1,89 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_DVO_H__
-+#define __DAL_HW_DVO_H__
-+
-+#define BUNDLE_A_SHIFT 12L
-+#define BUNDLE_B_SHIFT 0L
-+
-+struct hw_dvo {
-+	struct hw_gpio_pin base;
-+	/* Register indices are represented by member variables,
-+	 * are to be filled in by derived classes.
-+	 * These members permit the use of common code
-+	 * for programming registers where the sequence is the same
-+	 * but the register sets are different */
-+	struct {
-+		uint32_t DC_GPIO_DVODATA_MASK;
-+		uint32_t DC_GPIO_DVODATA_EN;
-+		uint32_t DC_GPIO_DVODATA_A;
-+		uint32_t DC_GPIO_DVODATA_Y;
-+		uint32_t DVO_STRENGTH_CONTROL;
-+		uint32_t D1CRTC_MVP_CONTROL1;
-+	} addr;
-+
-+	/* Mask and shift differentiates between Bundle A and Bundle B */
-+	uint32_t dvo_mask;
-+	uint32_t dvo_shift;
-+	uint32_t dvo_strength_mask;
-+	uint32_t mvp_termination_mask;
-+
-+	uint32_t dvo_strength;
-+
-+	struct {
-+		uint32_t dvo_mask;
-+		uint32_t dvo_en;
-+		uint32_t dvo_data_a;
-+		bool mvp_terminator_state;
-+	} store;
-+};
-+
-+bool dal_hw_dvo_construct(
-+	struct hw_dvo *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+void dal_hw_dvo_destruct(
-+	struct hw_dvo *pin);
-+
-+bool dal_hw_dvo_open(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode,
-+	void *options);
-+
-+enum gpio_result dal_hw_dvo_get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value);
-+
-+enum gpio_result dal_hw_dvo_set_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t value);
-+
-+void dal_hw_dvo_close(
-+	struct hw_gpio_pin *ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-new file mode 100644
-index 0000000..d1b6b7e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_factory.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/hw_factory_dce110.h"
-+#endif
-+/*
-+ * This unit
-+ */
-+
-+bool dal_hw_factory_init(
-+	struct hw_factory *factory,
-+	enum dce_version dce_version)
-+{
-+	switch (dce_version) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		dal_hw_factory_dce110_init(factory);
-+		return true;
-+#endif
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+void dal_hw_factory_destroy(
-+	struct dc_context *ctx,
-+	struct hw_factory **factory)
-+{
-+	if (!factory || !*factory) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dc_service_free(ctx, *factory);
-+
-+	*factory = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-new file mode 100644
-index 0000000..f16678c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_H__
-+#define __DAL_HW_FACTORY_H__
-+
-+struct hw_gpio_pin;
-+
-+struct hw_factory {
-+	uint32_t number_of_pins[GPIO_ID_COUNT];
-+
-+	const struct hw_factory_funcs {
-+		struct hw_gpio_pin *(*create_dvo)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_ddc_data)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_ddc_clock)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_generic)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_hpd)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_gpio_pad)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_sync)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_gsl)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+	} *funcs;
-+};
-+
-+bool dal_hw_factory_init(
-+	struct hw_factory *factory,
-+	enum dce_version dce_version);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-new file mode 100644
-index 0000000..2964d5d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-@@ -0,0 +1,408 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio_pin.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_gpio.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+enum gpio_result dal_hw_gpio_get_reg_value(
-+	struct dc_context *ctx,
-+	const struct addr_mask *reg,
-+	uint32_t *value)
-+{
-+	*value = dal_read_reg(ctx, reg->addr);
-+
-+	*value &= reg->mask;
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+enum gpio_result dal_hw_gpio_set_reg_value(
-+	struct dc_context *ctx,
-+	const struct addr_mask *reg,
-+	uint32_t value)
-+{
-+	uint32_t prev_value;
-+
-+	if ((value & reg->mask) != value) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_INVALID_DATA;
-+	}
-+
-+	prev_value = dal_read_reg(ctx, reg->addr);
-+
-+	prev_value &= ~reg->mask;
-+	prev_value |= (value & reg->mask);
-+
-+	dal_write_reg(ctx, reg->addr, prev_value);
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+uint32_t dal_hw_gpio_get_shift_from_mask(
-+	uint32_t mask)
-+{
-+	uint32_t result = 0;
-+
-+	if (!mask)
-+		return 32;
-+
-+	do {
-+		if ((1 << result) & mask)
-+			break;
-+
-+		++result;
-+	} while (result < 32);
-+
-+	return result;
-+}
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	container_of((ptr), struct hw_gpio, base)
-+
-+static void store_registers(
-+	struct hw_gpio *pin)
-+{
-+	dal_hw_gpio_get_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_MASK,
-+		&pin->store.mask);
-+	dal_hw_gpio_get_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_A,
-+		&pin->store.a);
-+	dal_hw_gpio_get_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_EN,
-+		&pin->store.en);
-+
-+	if (pin->mux_supported)
-+		dal_hw_gpio_get_reg_value(
-+			pin->base.ctx,
-+			&pin->mux_reg.GPIO_MUX_CONTROL,
-+			&pin->store.mux);
-+}
-+
-+static void restore_registers(
-+	struct hw_gpio *pin)
-+{
-+	dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_MASK,
-+		pin->store.mask);
-+	dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_A,
-+		pin->store.a);
-+	dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_EN,
-+		pin->store.en);
-+
-+	if (pin->mux_supported)
-+		dal_hw_gpio_set_reg_value(
-+			pin->base.ctx,
-+			&pin->mux_reg.GPIO_MUX_CONTROL,
-+			pin->store.mux);
-+}
-+
-+bool dal_hw_gpio_open(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode,
-+	void *options)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	store_registers(pin);
-+
-+	ptr->opened = (pin->funcs->config_mode(pin, mode) == GPIO_RESULT_OK);
-+
-+	return ptr->opened;
-+}
-+
-+enum gpio_result dal_hw_gpio_get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	const struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	enum gpio_result result;
-+
-+	switch (ptr->mode) {
-+	case GPIO_MODE_INPUT:
-+	case GPIO_MODE_OUTPUT:
-+	case GPIO_MODE_HARDWARE:
-+	case GPIO_MODE_FAST_OUTPUT:
-+		result = dal_hw_gpio_get_reg_value(
-+			ptr->ctx,
-+			&pin->pin_reg.DC_GPIO_DATA_Y,
-+			value);
-+		/* Clients does not know that the value
-+		 * comes from register and is shifted. */
-+		if (result == GPIO_RESULT_OK)
-+			*value >>= dal_hw_gpio_get_shift_from_mask(
-+				pin->pin_reg.DC_GPIO_DATA_Y.mask);
-+	break;
-+	default:
-+		result = GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	return result;
-+}
-+
-+enum gpio_result dal_hw_gpio_set_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t value)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	/* This is the public interface
-+	 * where the input comes from client, not shifted yet
-+	 * (because client does not know the shifts). */
-+
-+	switch (ptr->mode) {
-+	case GPIO_MODE_OUTPUT:
-+		return dal_hw_gpio_set_reg_value(
-+			ptr->ctx,
-+			&pin->pin_reg.DC_GPIO_DATA_A,
-+			value << dal_hw_gpio_get_shift_from_mask(
-+				pin->pin_reg.DC_GPIO_DATA_A.mask));
-+	case GPIO_MODE_FAST_OUTPUT:
-+		/* We use (EN) to faster switch (used in DDC GPIO).
-+		 * So (A) is grounded, output is driven by (EN = 0)
-+		 * to pull the line down (output == 0) and (EN=1)
-+		 * then output is tri-state */
-+		return dal_hw_gpio_set_reg_value(
-+			ptr->ctx,
-+			&pin->pin_reg.DC_GPIO_DATA_EN,
-+			pin->pin_reg.DC_GPIO_DATA_EN.mask &
-+			~(value << dal_hw_gpio_get_shift_from_mask(
-+				pin->pin_reg.DC_GPIO_DATA_EN.mask)));
-+	default:
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+}
-+
-+enum gpio_result dal_hw_gpio_change_mode(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	return pin->funcs->config_mode(pin, mode);
-+}
-+
-+void dal_hw_gpio_close(
-+	struct hw_gpio_pin *ptr)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	restore_registers(pin);
-+
-+	ptr->mode = GPIO_MODE_UNKNOWN;
-+	ptr->opened = false;
-+}
-+
-+static enum gpio_result config_mode_input(
-+	struct hw_gpio *pin)
-+{
-+	enum gpio_result result;
-+
-+	/* turn off output enable, act as input pin;
-+	 * program the pin as GPIO, mask out signal driven by HW */
-+
-+	result = dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_EN,
-+		0);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	result = dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_MASK,
-+		pin->pin_reg.DC_GPIO_DATA_MASK.mask);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+static enum gpio_result config_mode_output(
-+	struct hw_gpio *pin)
-+{
-+	enum gpio_result result;
-+
-+	/* turn on output enable, act as output pin;
-+	 * program the pin as GPIO, mask out signal driven by HW */
-+
-+	result = dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_EN,
-+		pin->pin_reg.DC_GPIO_DATA_EN.mask);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	result = dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_MASK,
-+		pin->pin_reg.DC_GPIO_DATA_MASK.mask);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+static enum gpio_result config_mode_fast_output(
-+	struct hw_gpio *pin)
-+{
-+	enum gpio_result result;
-+
-+	/* grounding the A register then use the EN register bit
-+	 * will have faster effect on the rise time */
-+
-+	result = dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_A, 0);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	result = dal_hw_gpio_set_reg_value(
-+		pin->base.ctx,
-+		&pin->pin_reg.DC_GPIO_DATA_MASK,
-+		pin->pin_reg.DC_GPIO_DATA_MASK.mask);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+static enum gpio_result config_mode_hardware(
-+	struct hw_gpio *pin)
-+{
-+	/* program the pin as tri-state, pin is driven by HW */
-+
-+	enum gpio_result result =
-+		dal_hw_gpio_set_reg_value(
-+			pin->base.ctx,
-+			&pin->pin_reg.DC_GPIO_DATA_MASK,
-+			0);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+enum gpio_result dal_hw_gpio_config_mode(
-+	struct hw_gpio *pin,
-+	enum gpio_mode mode)
-+{
-+	pin->base.mode = mode;
-+
-+	switch (mode) {
-+	case GPIO_MODE_INPUT:
-+		return config_mode_input(pin);
-+	case GPIO_MODE_OUTPUT:
-+		return config_mode_output(pin);
-+	case GPIO_MODE_FAST_OUTPUT:
-+		return config_mode_fast_output(pin);
-+	case GPIO_MODE_HARDWARE:
-+		return config_mode_hardware(pin);
-+	default:
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+}
-+
-+const struct hw_gpio_funcs func = {
-+	.config_mode = dal_hw_gpio_config_mode,
-+};
-+
-+bool dal_hw_gpio_construct(
-+	struct hw_gpio *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	struct hw_gpio_pin *base = &pin->base;
-+
-+	if (!dal_hw_gpio_pin_construct(base, id, en, ctx))
-+		return false;
-+
-+	pin->funcs = &func;
-+
-+	pin->pin_reg.DC_GPIO_DATA_MASK.addr = 0;
-+	pin->pin_reg.DC_GPIO_DATA_MASK.mask = 0;
-+	pin->pin_reg.DC_GPIO_DATA_A.addr = 0;
-+	pin->pin_reg.DC_GPIO_DATA_A.mask = 0;
-+	pin->pin_reg.DC_GPIO_DATA_EN.addr = 0;
-+	pin->pin_reg.DC_GPIO_DATA_EN.mask = 0;
-+	pin->pin_reg.DC_GPIO_DATA_Y.addr = 0;
-+	pin->pin_reg.DC_GPIO_DATA_Y.mask = 0;
-+	pin->mux_reg.GPIO_MUX_CONTROL.addr = 0;
-+	pin->mux_reg.GPIO_MUX_CONTROL.mask = 0;
-+	pin->mux_reg.GPIO_MUX_STEREO_SEL.addr = 0;
-+	pin->mux_reg.GPIO_MUX_STEREO_SEL.mask = 0;
-+
-+	pin->store.mask = 0;
-+	pin->store.a = 0;
-+	pin->store.en = 0;
-+	pin->store.mux = 0;
-+
-+	pin->mux_supported = false;
-+
-+	return true;
-+}
-+
-+void dal_hw_gpio_destruct(
-+	struct hw_gpio *pin)
-+{
-+	dal_hw_gpio_pin_destruct(&pin->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h
-new file mode 100644
-index 0000000..44eb86e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h
-@@ -0,0 +1,129 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_GPIO_H__
-+#define __DAL_HW_GPIO_H__
-+
-+struct addr_mask {
-+	uint32_t addr;
-+	uint32_t mask;
-+};
-+
-+enum gpio_result dal_hw_gpio_get_reg_value(
-+	struct dc_context *ctx,
-+	const struct addr_mask *reg,
-+	uint32_t *value);
-+
-+enum gpio_result dal_hw_gpio_set_reg_value(
-+	struct dc_context *ctx,
-+	const struct addr_mask *reg,
-+	uint32_t value);
-+
-+uint32_t dal_hw_gpio_get_shift_from_mask(
-+	uint32_t mask);
-+
-+struct hw_gpio;
-+
-+struct hw_gpio_funcs {
-+	enum gpio_result (*config_mode)(
-+		struct hw_gpio *pin,
-+		enum gpio_mode mode);
-+};
-+
-+/* Register indices are represented by member variables
-+ * and are to be filled in by constructors of derived classes.
-+ * These members permit the use of common code
-+ * for programming registers, where the sequence is the same
-+ * but register sets are different.
-+ * Some GPIOs have HW mux which allows to choose
-+ * what is the source of the signal in HW mode */
-+
-+struct hw_gpio_pin_reg {
-+	struct addr_mask DC_GPIO_DATA_MASK;
-+	struct addr_mask DC_GPIO_DATA_A;
-+	struct addr_mask DC_GPIO_DATA_EN;
-+	struct addr_mask DC_GPIO_DATA_Y;
-+};
-+
-+struct hw_gpio_mux_reg {
-+	struct addr_mask GPIO_MUX_CONTROL;
-+	struct addr_mask GPIO_MUX_STEREO_SEL;
-+};
-+
-+struct hw_gpio {
-+	struct hw_gpio_pin base;
-+	const struct hw_gpio_funcs *funcs;
-+	struct hw_gpio_pin_reg pin_reg;
-+	struct hw_gpio_mux_reg mux_reg;
-+
-+	/* variables to save register value */
-+	struct {
-+		uint32_t mask;
-+		uint32_t a;
-+		uint32_t en;
-+		uint32_t mux;
-+	} store;
-+
-+	/* GPIO MUX support */
-+	bool mux_supported;
-+};
-+
-+#define HW_GPIO_FROM_BASE(hw_gpio_pin) \
-+	container_of((hw_gpio_pin), struct hw_gpio, base)
-+
-+bool dal_hw_gpio_construct(
-+	struct hw_gpio *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+bool dal_hw_gpio_open(
-+	struct hw_gpio_pin *pin,
-+	enum gpio_mode mode,
-+	void *options);
-+
-+enum gpio_result dal_hw_gpio_get_value(
-+	const struct hw_gpio_pin *pin,
-+	uint32_t *value);
-+
-+enum gpio_result dal_hw_gpio_config_mode(
-+	struct hw_gpio *pin,
-+	enum gpio_mode mode);
-+
-+void dal_hw_gpio_destruct(
-+	struct hw_gpio *pin);
-+
-+enum gpio_result dal_hw_gpio_set_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t value);
-+
-+enum gpio_result dal_hw_gpio_change_mode(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode);
-+
-+void dal_hw_gpio_close(
-+	struct hw_gpio_pin *ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-new file mode 100644
-index 0000000..057c439
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-@@ -0,0 +1,93 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_gpio.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_gpio_pad.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_HW_GPIO(ptr) \
-+	container_of((ptr), struct hw_gpio_pad, base)
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	FROM_HW_GPIO(container_of((ptr), struct hw_gpio, base))
-+
-+enum gpio_result dal_hw_gpio_pad_get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	const struct hw_gpio_pad *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	if (ptr->mode == GPIO_MODE_INTERRUPT)
-+		/* in Interrupt mode, ask for interrupt status bit */
-+		return dal_hw_gpio_get_reg_value(
-+			ptr->ctx,
-+			&pin->gpiopad_int_status,
-+			value);
-+	else
-+		/* for any mode other than Interrupt,
-+		 * gpio_pad operates as normal GPIO */
-+		return dal_hw_gpio_get_value(ptr, value);
-+}
-+
-+bool dal_hw_gpio_pad_construct(
-+	struct hw_gpio_pad *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_hw_gpio_construct(&pin->base, id, en, ctx))
-+		return false;
-+
-+	pin->gpiopad_int_status.addr = 0;
-+	pin->gpiopad_int_status.mask = 0;
-+
-+	return true;
-+}
-+
-+void dal_hw_gpio_pad_destruct(
-+	struct hw_gpio_pad *pin)
-+{
-+	dal_hw_gpio_destruct(&pin->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h
-new file mode 100644
-index 0000000..34b470a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_GPIO_PAD_H__
-+#define __DAL_HW_GPIO_PAD_H__
-+
-+struct hw_gpio_pad {
-+	struct hw_gpio base;
-+	struct addr_mask gpiopad_int_status;
-+};
-+
-+bool dal_hw_gpio_pad_construct(
-+	struct hw_gpio_pad *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+void dal_hw_gpio_pad_destruct(
-+	struct hw_gpio_pad *pin);
-+
-+enum gpio_result dal_hw_gpio_pad_get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-new file mode 100644
-index 0000000..4ab1848
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-@@ -0,0 +1,86 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_gpio_pin.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+enum gpio_result dal_hw_gpio_pin_set_config(
-+	struct hw_gpio_pin *pin,
-+	const struct gpio_config_data *config_data)
-+{
-+	/* Attention!
-+	 * You must override this method in derived class */
-+
-+	return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+}
-+
-+enum gpio_result dal_hw_gpio_pin_change_mode(
-+	struct hw_gpio_pin *pin,
-+	enum gpio_mode mode)
-+{
-+	/* Attention!
-+	 * You must override this method in derived class */
-+
-+	return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+}
-+
-+bool dal_hw_gpio_pin_construct(
-+	struct hw_gpio_pin *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	pin->ctx = ctx;
-+	pin->id = id;
-+	pin->en = en;
-+	pin->mode = GPIO_MODE_UNKNOWN;
-+	pin->opened = false;
-+
-+	return true;
-+}
-+
-+void dal_hw_gpio_pin_destruct(
-+	struct hw_gpio_pin *pin)
-+{
-+	ASSERT(!pin->opened);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h
-new file mode 100644
-index 0000000..d1f2f27
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h
-@@ -0,0 +1,79 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_GPIO_PIN_H__
-+#define __DAL_HW_GPIO_PIN_H__
-+
-+struct hw_gpio_pin;
-+
-+struct hw_gpio_pin_funcs {
-+	void (*destroy)(
-+		struct hw_gpio_pin **ptr);
-+	bool (*open)(
-+		struct hw_gpio_pin *pin,
-+		enum gpio_mode mode,
-+		void *options);
-+	enum gpio_result (*get_value)(
-+		const struct hw_gpio_pin *pin,
-+		uint32_t *value);
-+	enum gpio_result (*set_value)(
-+		const struct hw_gpio_pin *pin,
-+		uint32_t value);
-+	enum gpio_result (*set_config)(
-+		struct hw_gpio_pin *pin,
-+		const struct gpio_config_data *config_data);
-+	enum gpio_result (*change_mode)(
-+		struct hw_gpio_pin *pin,
-+		enum gpio_mode mode);
-+	void (*close)(
-+		struct hw_gpio_pin *pin);
-+};
-+
-+struct hw_gpio_pin {
-+	const struct hw_gpio_pin_funcs *funcs;
-+	enum gpio_id id;
-+	uint32_t en;
-+	enum gpio_mode mode;
-+	bool opened;
-+	struct dc_context *ctx;
-+};
-+
-+bool dal_hw_gpio_pin_construct(
-+	struct hw_gpio_pin *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+void dal_hw_gpio_pin_destruct(
-+	struct hw_gpio_pin *pin);
-+
-+enum gpio_result dal_hw_gpio_pin_change_mode(
-+	struct hw_gpio_pin *pin,
-+	enum gpio_mode mode);
-+
-+enum gpio_result dal_hw_gpio_pin_set_config(
-+	struct hw_gpio_pin *pin,
-+	const struct gpio_config_data *config_data);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-new file mode 100644
-index 0000000..c09d74c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-@@ -0,0 +1,88 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_gpio.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_hpd.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+static enum gpio_result config_mode(
-+	struct hw_gpio *pin,
-+	enum gpio_mode mode)
-+{
-+	if (mode == GPIO_MODE_INTERRUPT) {
-+		/* Interrupt mode supported only by HPD (IrqGpio) pins. */
-+		pin->base.mode = mode;
-+
-+		return dal_hw_gpio_set_reg_value(
-+			pin->base.ctx,
-+			&pin->pin_reg.DC_GPIO_DATA_MASK,
-+			0);
-+	} else
-+		/* For any mode other than Interrupt,
-+		 * act as normal GPIO. */
-+		return dal_hw_gpio_config_mode(pin, mode);
-+}
-+
-+const struct hw_gpio_funcs hw_hpd_func = {
-+	.config_mode = config_mode,
-+};
-+
-+bool dal_hw_hpd_construct(
-+	struct hw_hpd *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_hw_gpio_construct(&pin->base, id, en, ctx))
-+		return false;
-+	pin->base.funcs = &hw_hpd_func;
-+	return true;
-+}
-+
-+void dal_hw_hpd_destruct(
-+	struct hw_hpd *pin)
-+{
-+	dal_hw_gpio_destruct(&pin->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h
-new file mode 100644
-index 0000000..3fb82df
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h
-@@ -0,0 +1,45 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_HPD_H__
-+#define __DAL_HW_HPD_H__
-+
-+struct hw_hpd {
-+	struct hw_gpio base;
-+};
-+
-+#define HW_HPD_FROM_BASE(hw_gpio) \
-+	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base)
-+
-+bool dal_hw_hpd_construct(
-+	struct hw_hpd *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+void dal_hw_hpd_destruct(
-+	struct hw_hpd *pin);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-new file mode 100644
-index 0000000..96e135f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -0,0 +1,67 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_translate.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/hw_translate_dce110.h"
-+#endif
-+
-+/*
-+ * This unit
-+ */
-+
-+bool dal_hw_translate_init(
-+	struct hw_translate *translate,
-+	enum dce_version dce_version)
-+{
-+	switch (dce_version) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		dal_hw_translate_dce110_init(translate);
-+		return true;
-+#endif
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
-new file mode 100644
-index 0000000..d5740ac
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_H__
-+#define __DAL_HW_TRANSLATE_H__
-+
-+struct hw_translate_funcs {
-+	bool (*offset_to_id)(
-+		uint32_t offset,
-+		uint32_t mask,
-+		enum gpio_id *id,
-+		uint32_t *en);
-+	bool (*id_to_offset)(
-+		enum gpio_id id,
-+		uint32_t en,
-+		struct gpio_pin_info *info);
-+};
-+
-+struct hw_translate {
-+	const struct hw_translate_funcs *funcs;
-+};
-+
-+bool dal_hw_translate_init(
-+	struct hw_translate *translate,
-+	enum dce_version dce_version);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-new file mode 100644
-index 0000000..382b89f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-@@ -0,0 +1,181 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_interface.h"
-+#include "include/irq_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_gpio_pin.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+#include "gpio_service.h"
-+#include "gpio.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "irq.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+enum gpio_result dal_irq_open(
-+	struct irq *irq)
-+{
-+	return dal_gpio_open(irq->pin, GPIO_MODE_INTERRUPT);
-+}
-+
-+enum gpio_result dal_irq_get_value(
-+	const struct irq *irq,
-+	uint32_t *value)
-+{
-+	return dal_gpio_get_value(irq->pin, value);
-+}
-+
-+enum dc_irq_source dal_irq_get_source(
-+	const struct irq *irq)
-+{
-+	enum gpio_id id = dal_gpio_get_id(irq->pin);
-+
-+	switch (id) {
-+	case GPIO_ID_HPD:
-+		return (enum dc_irq_source)(DC_IRQ_SOURCE_HPD1 +
-+			dal_gpio_get_enum(irq->pin));
-+	case GPIO_ID_GPIO_PAD:
-+		return (enum dc_irq_source)(DC_IRQ_SOURCE_GPIOPAD0 +
-+			dal_gpio_get_enum(irq->pin));
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+enum dc_irq_source dal_irq_get_rx_source(
-+	const struct irq *irq)
-+{
-+	enum gpio_id id = dal_gpio_get_id(irq->pin);
-+
-+	switch (id) {
-+	case GPIO_ID_HPD:
-+		return (enum dc_irq_source)(DC_IRQ_SOURCE_HPD1RX +
-+			dal_gpio_get_enum(irq->pin));
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+enum gpio_result dal_irq_setup_hpd_filter(
-+	struct irq *irq,
-+	struct gpio_hpd_config *config)
-+{
-+	struct gpio_config_data config_data;
-+
-+	if (!config)
-+		return GPIO_RESULT_INVALID_DATA;
-+
-+	config_data.type = GPIO_CONFIG_TYPE_HPD;
-+	config_data.config.hpd = *config;
-+
-+	return dal_gpio_set_config(irq->pin, &config_data);
-+}
-+
-+void dal_irq_close(
-+	struct irq *irq)
-+{
-+	dal_gpio_close(irq->pin);
-+}
-+
-+/*
-+ * @brief
-+ * Creation and destruction
-+ */
-+
-+struct irq *dal_gpio_create_irq(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct irq *irq;
-+
-+	switch (id) {
-+	case GPIO_ID_HPD:
-+	case GPIO_ID_GPIO_PAD:
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	irq = dc_service_alloc(service->ctx, sizeof(struct irq));
-+
-+	if (!irq) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	irq->pin = dal_gpio_service_create_gpio_ex(
-+		service, id, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+	irq->ctx = service->ctx;
-+
-+	if (irq->pin)
-+		return irq;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(service->ctx, irq);
-+
-+	return NULL;
-+}
-+
-+static void destruct(struct irq *irq)
-+{
-+	dal_irq_close(irq);
-+	dal_gpio_service_destroy_gpio(&irq->pin);
-+
-+}
-+
-+void dal_gpio_destroy_irq(
-+	struct irq **irq)
-+{
-+	if (!irq || !*irq) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	destruct(*irq);
-+	dc_service_free((*irq)->ctx, *irq);
-+
-+	*irq = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/irq.h b/drivers/gpu/drm/amd/dal/dc/gpio/irq.h
-new file mode 100644
-index 0000000..b69375c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/irq.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_H__
-+#define __DAL_IRQ_H__
-+
-+struct irq {
-+	struct gpio *pin;
-+	struct dc_context *ctx;
-+};
-+
-+struct irq *dal_gpio_create_irq(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+void dal_gpio_destroy_irq(
-+	struct irq **ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-new file mode 100644
-index 0000000..d3d6faf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-@@ -0,0 +1,26 @@
-+#
-+# Makefile for the 'gpu' sub-component of DAL.
-+# It provides the control and status of HW adapter resources,
-+# that are global for the ASIC and sharable between pipes.
-+
-+GPU = calc_pll_clock_source.o clock_source.o \
-+dc_clock_generator.o display_clock.o divider_range.o \
-+ext_clock_source.o pll_clock_source.o
-+
-+AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPU)
-+
-+
-+###############################################################################
-+# DCE 110 family
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+GPU_DCE110 = display_clock_dce110.o \
-+	pll_clock_source_dce110.o ext_clock_source_dce110.o \
-+	vce_clock_source_dce110.o dc_clock_gating_dce110.o
-+
-+AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-new file mode 100644
-index 0000000..7c94733
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-@@ -0,0 +1,407 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "calc_pll_clock_source.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/logger_interface.h"
-+
-+/**
-+* Function: calculate_fb_and_fractional_fb_divider
-+*
-+* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
-+*
-+*PARAMETERS:
-+* targetPixelClock             Desired frequency in 10 KHz
-+* ref_divider                  Reference divider (already known)
-+* postDivider                  Post Divider (already known)
-+* feedback_divider_param       Pointer where to store
-+*					calculated feedback divider value
-+* fract_feedback_divider_param Pointer where to store
-+*					calculated fract feedback divider value
-+*
-+*RETURNS:
-+* It fills the locations pointed by feedback_divider_param
-+*					and fract_feedback_divider_param
-+* It returns	- true if feedback divider not 0
-+*		- false should never happen)
-+*/
-+static bool calculate_fb_and_fractional_fb_divider(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		uint32_t target_pix_clk_khz,
-+		uint32_t ref_divider,
-+		uint32_t post_divider,
-+		uint32_t *feedback_divider_param,
-+		uint32_t *fract_feedback_divider_param)
-+{
-+	uint64_t feedback_divider;
-+
-+	feedback_divider =
-+		(uint64_t)(target_pix_clk_khz * ref_divider * post_divider);
-+	feedback_divider *= 10;
-+	/* additional factor, since we divide by 10 afterwards */
-+	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
-+	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
-+
-+/*Round to the number of precision
-+ * The following code replace the old code (ullfeedbackDivider + 5)/10
-+ * for example if the difference between the number
-+ * of fractional feedback decimal point and the fractional FB Divider precision
-+ * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
-+
-+	feedback_divider += (uint64_t)
-+			(5 * calc_pll_cs->fract_fb_divider_precision_factor);
-+	feedback_divider =
-+		div_u64(feedback_divider,
-+			calc_pll_cs->fract_fb_divider_precision_factor * 10);
-+	feedback_divider *= (uint64_t)
-+			(calc_pll_cs->fract_fb_divider_precision_factor);
-+
-+	*feedback_divider_param =
-+		div_u64_rem(
-+			feedback_divider,
-+			calc_pll_cs->fract_fb_divider_factor,
-+			fract_feedback_divider_param);
-+
-+	if (*feedback_divider_param != 0)
-+		return true;
-+	return false;
-+}
-+
-+/**
-+*calc_fb_divider_checking_tolerance
-+*
-+*DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
-+*		for passed Reference and Post divider, checking for tolerance.
-+*PARAMETERS:
-+* pll_settings		Pointer to structure
-+* ref_divider		Reference divider (already known)
-+* postDivider		Post Divider (already known)
-+* tolerance		Tolerance for Calculated Pixel Clock to be within
-+*
-+*RETURNS:
-+* It fills the PLLSettings structure with PLL Dividers values
-+* if calculated values are within required tolerance
-+* It returns	- true if eror is within tolerance
-+*		- false if eror is not within tolerance
-+*/
-+static bool calc_fb_divider_checking_tolerance(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings,
-+		uint32_t ref_divider,
-+		uint32_t post_divider,
-+		uint32_t tolerance)
-+{
-+	uint32_t feedback_divider;
-+	uint32_t fract_feedback_divider;
-+	uint32_t actual_calculated_clock_khz;
-+	uint32_t abs_err;
-+	uint64_t actual_calc_clk_khz;
-+
-+	calculate_fb_and_fractional_fb_divider(
-+			calc_pll_cs,
-+			pll_settings->adjusted_pix_clk,
-+			ref_divider,
-+			post_divider,
-+			&feedback_divider,
-+			&fract_feedback_divider);
-+
-+	/*Actual calculated value*/
-+	actual_calc_clk_khz = (uint64_t)(feedback_divider *
-+					calc_pll_cs->fract_fb_divider_factor) +
-+							fract_feedback_divider;
-+	actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
-+	actual_calc_clk_khz =
-+		div_u64(actual_calc_clk_khz,
-+			ref_divider * post_divider *
-+				calc_pll_cs->fract_fb_divider_factor);
-+
-+	actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
-+
-+	abs_err = (actual_calculated_clock_khz >
-+					pll_settings->adjusted_pix_clk)
-+			? actual_calculated_clock_khz -
-+					pll_settings->adjusted_pix_clk
-+			: pll_settings->adjusted_pix_clk -
-+						actual_calculated_clock_khz;
-+
-+	if (abs_err <= tolerance) {
-+		/*found good values*/
-+		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
-+		pll_settings->reference_divider = ref_divider;
-+		pll_settings->feedback_divider = feedback_divider;
-+		pll_settings->fract_feedback_divider = fract_feedback_divider;
-+		pll_settings->pix_clk_post_divider = post_divider;
-+		pll_settings->calculated_pix_clk =
-+			actual_calculated_clock_khz;
-+		pll_settings->vco_freq =
-+			actual_calculated_clock_khz * post_divider;
-+		return true;
-+	}
-+	return false;
-+}
-+
-+static bool calc_pll_dividers_in_range(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings,
-+		uint32_t min_ref_divider,
-+		uint32_t max_ref_divider,
-+		uint32_t min_post_divider,
-+		uint32_t max_post_divider,
-+		uint32_t err_tolerance)
-+{
-+	uint32_t ref_divider;
-+	uint32_t post_divider;
-+	uint32_t tolerance;
-+
-+/* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
-+ * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
-+	tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
-+									10000;
-+	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
-+		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
-+
-+	for (
-+			post_divider = max_post_divider;
-+			post_divider >= min_post_divider;
-+			--post_divider) {
-+		for (
-+				ref_divider = min_ref_divider;
-+				ref_divider <= max_ref_divider;
-+				++ref_divider) {
-+			if (calc_fb_divider_checking_tolerance(
-+					calc_pll_cs,
-+					pll_settings,
-+					ref_divider,
-+					post_divider,
-+					tolerance)) {
-+				return true;
-+			}
-+		}
-+	}
-+
-+	return false;
-+}
-+
-+uint32_t dal_clock_source_calculate_pixel_clock_pll_dividers(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings)
-+{
-+	uint32_t err_tolerance;
-+	uint32_t min_post_divider;
-+	uint32_t max_post_divider;
-+	uint32_t min_ref_divider;
-+	uint32_t max_ref_divider;
-+
-+	if (pll_settings->adjusted_pix_clk == 0) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s Bad requested pixel clock", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+/* 1) Find Post divider ranges */
-+	if (pll_settings->pix_clk_post_divider) {
-+		min_post_divider = pll_settings->pix_clk_post_divider;
-+		max_post_divider = pll_settings->pix_clk_post_divider;
-+	} else {
-+		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
-+		if (min_post_divider * pll_settings->adjusted_pix_clk <
-+						calc_pll_cs->min_vco_khz) {
-+			min_post_divider = calc_pll_cs->min_vco_khz /
-+					pll_settings->adjusted_pix_clk;
-+			if ((min_post_divider *
-+					pll_settings->adjusted_pix_clk) <
-+						calc_pll_cs->min_vco_khz)
-+				min_post_divider++;
-+		}
-+
-+		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
-+		if (max_post_divider * pll_settings->adjusted_pix_clk
-+				> calc_pll_cs->max_vco_khz)
-+			max_post_divider = calc_pll_cs->max_vco_khz /
-+					pll_settings->adjusted_pix_clk;
-+	}
-+
-+/* 2) Find Reference divider ranges
-+ * When SS is enabled, or for Display Port even without SS,
-+ * pll_settings->referenceDivider is not zero.
-+ * So calculate PPLL FB and fractional FB divider
-+ * using the passed reference divider*/
-+
-+	if (pll_settings->reference_divider) {
-+		min_ref_divider = pll_settings->reference_divider;
-+		max_ref_divider = pll_settings->reference_divider;
-+	} else {
-+		min_ref_divider = ((calc_pll_cs->ref_freq_khz
-+				/ calc_pll_cs->max_pll_input_freq_khz)
-+				> calc_pll_cs->min_pll_ref_divider)
-+			? calc_pll_cs->ref_freq_khz
-+					/ calc_pll_cs->max_pll_input_freq_khz
-+			: calc_pll_cs->min_pll_ref_divider;
-+
-+		max_ref_divider = ((calc_pll_cs->ref_freq_khz
-+				/ calc_pll_cs->min_pll_input_freq_khz)
-+				< calc_pll_cs->max_pll_ref_divider)
-+			? calc_pll_cs->ref_freq_khz /
-+					calc_pll_cs->min_pll_input_freq_khz
-+			: calc_pll_cs->max_pll_ref_divider;
-+	}
-+
-+/* If some parameters are invalid we could have scenario when  "min">"max"
-+ * which produced endless loop later.
-+ * We should investigate why we get the wrong parameters.
-+ * But to follow the similar logic when "adjustedPixelClock" is set to be 0
-+ * it is better to return here than cause system hang/watchdog timeout later.
-+ *  ## SVS Wed 15 Jul 2009 */
-+
-+	if (min_post_divider > max_post_divider) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s Post divider range is invalid", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+	if (min_ref_divider > max_ref_divider) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s Reference divider range is invalid", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+/* 3) Try to find PLL dividers given ranges
-+ * starting with minimal error tolerance.
-+ * Increase error tolerance until PLL dividers found*/
-+	err_tolerance = MAX_PLL_CALC_ERROR;
-+
-+	while (!calc_pll_dividers_in_range(
-+			calc_pll_cs,
-+			pll_settings,
-+			min_ref_divider,
-+			max_ref_divider,
-+			min_post_divider,
-+			max_post_divider,
-+			err_tolerance))
-+		err_tolerance += (err_tolerance > 10)
-+				? (err_tolerance / 10)
-+				: 1;
-+
-+	return err_tolerance;
-+}
-+
-+static bool calc_pll_clock_source_max_vco_construct(
-+			struct calc_pll_clock_source *calc_pll_cs,
-+			struct calc_pll_clock_source_init_data *init_data)
-+{
-+
-+	uint32_t i;
-+	struct firmware_info fw_info = { { 0 } };
-+	if (calc_pll_cs == NULL ||
-+			init_data == NULL ||
-+			init_data->bp == NULL)
-+		return false;
-+
-+	if (dal_bios_parser_get_firmware_info(
-+				init_data->bp,
-+				&fw_info) != BP_RESULT_OK)
-+		return false;
-+
-+	calc_pll_cs->ctx = init_data->ctx;
-+	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+	calc_pll_cs->min_vco_khz =
-+			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
-+	calc_pll_cs->max_vco_khz =
-+			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
-+
-+	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
-+		calc_pll_cs->max_pll_input_freq_khz =
-+			init_data->max_override_input_pxl_clk_pll_freq_khz;
-+	else
-+		calc_pll_cs->max_pll_input_freq_khz =
-+			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
-+
-+	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
-+		calc_pll_cs->min_pll_input_freq_khz =
-+			init_data->min_override_input_pxl_clk_pll_freq_khz;
-+	else
-+		calc_pll_cs->min_pll_input_freq_khz =
-+			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
-+
-+	calc_pll_cs->min_pix_clock_pll_post_divider =
-+			init_data->min_pix_clk_pll_post_divider;
-+	calc_pll_cs->max_pix_clock_pll_post_divider =
-+			init_data->max_pix_clk_pll_post_divider;
-+	calc_pll_cs->min_pll_ref_divider =
-+			init_data->min_pll_ref_divider;
-+	calc_pll_cs->max_pll_ref_divider =
-+			init_data->max_pll_ref_divider;
-+
-+	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
-+		init_data->num_fract_fb_divider_decimal_point_precision >
-+				init_data->num_fract_fb_divider_decimal_point) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"The dec point num or precision is incorrect!");
-+		return false;
-+	}
-+	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Incorrect fract feedback divider precision num!");
-+		return false;
-+	}
-+
-+	calc_pll_cs->fract_fb_divider_decimal_points_num =
-+				init_data->num_fract_fb_divider_decimal_point;
-+	calc_pll_cs->fract_fb_divider_precision =
-+			init_data->num_fract_fb_divider_decimal_point_precision;
-+	calc_pll_cs->fract_fb_divider_factor = 1;
-+	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
-+		calc_pll_cs->fract_fb_divider_factor *= 10;
-+
-+	calc_pll_cs->fract_fb_divider_precision_factor = 1;
-+	for (
-+		i = 0;
-+		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
-+				calc_pll_cs->fract_fb_divider_precision);
-+		++i)
-+		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
-+
-+	return true;
-+}
-+
-+bool dal_calc_pll_clock_source_max_vco_init(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct calc_pll_clock_source_init_data *init_data)
-+{
-+	return calc_pll_clock_source_max_vco_construct(
-+			calc_pll_cs, init_data);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-new file mode 100644
-index 0000000..be44d06
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-@@ -0,0 +1,79 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_CALC_PLL_CLOCK_SOURCE_H__
-+#define __DAL_CALC_PLL_CLOCK_SOURCE_H__
-+
-+#include "include/clock_source_types.h"
-+
-+struct calc_pll_clock_source_init_data {
-+	struct bios_parser *bp;
-+	uint32_t min_pix_clk_pll_post_divider;
-+	uint32_t max_pix_clk_pll_post_divider;
-+	uint32_t min_pll_ref_divider;
-+	uint32_t max_pll_ref_divider;
-+	uint32_t min_override_input_pxl_clk_pll_freq_khz;
-+/* if not 0, override the firmware info */
-+
-+	uint32_t max_override_input_pxl_clk_pll_freq_khz;
-+/* if not 0, override the firmware info */
-+
-+	uint32_t num_fract_fb_divider_decimal_point;
-+/* number of decimal point for fractional feedback divider value */
-+
-+	uint32_t num_fract_fb_divider_decimal_point_precision;
-+/* number of decimal point to round off for fractional feedback divider value*/
-+	struct dc_context *ctx;
-+
-+};
-+#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
-+struct calc_pll_clock_source {
-+	uint32_t ref_freq_khz;
-+	uint32_t min_pix_clock_pll_post_divider;
-+	uint32_t max_pix_clock_pll_post_divider;
-+	uint32_t min_pll_ref_divider;
-+	uint32_t max_pll_ref_divider;
-+
-+	uint32_t max_vco_khz;
-+	uint32_t min_vco_khz;
-+	uint32_t min_pll_input_freq_khz;
-+	uint32_t max_pll_input_freq_khz;
-+
-+	uint32_t fract_fb_divider_decimal_points_num;
-+	uint32_t fract_fb_divider_factor;
-+	uint32_t fract_fb_divider_precision;
-+	uint32_t fract_fb_divider_precision_factor;
-+	struct dc_context *ctx;
-+};
-+
-+
-+bool dal_calc_pll_clock_source_max_vco_init(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct calc_pll_clock_source_init_data *init_data);
-+
-+uint32_t dal_clock_source_calculate_pixel_clock_pll_dividers(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings);
-+
-+
-+#endif /*__DAL_CALC_PLL_CLOCK_SOURCE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-new file mode 100644
-index 0000000..8e700ea
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-@@ -0,0 +1,649 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/grph_object_id.h"
-+#include "include/clock_source_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "clock_source.h"
-+#include "pll_clock_source.h"
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/ext_clock_source_dce110.h"
-+#include "dce110/pll_clock_source_dce110.h"
-+#include "dce110/vce_clock_source_dce110.h"
-+#endif
-+
-+
-+struct clock_source *dal_clock_source_create(
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	enum dce_version dce_ver =
-+		dal_adapter_service_get_dce_version(clk_src_init_data->as);
-+	enum clock_source_id clk_src_id =
-+		dal_graphics_object_id_get_clock_source_id(
-+			clk_src_init_data->clk_src_id);
-+	switch (dce_ver) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	break;
-+	case DCE_VERSION_11_0:
-+	{
-+		switch (clk_src_id) {
-+		case CLOCK_SOURCE_ID_PLL0:
-+		/* fall through */
-+		case CLOCK_SOURCE_ID_PLL1:
-+		/* fall through */
-+		case CLOCK_SOURCE_ID_PLL2:
-+			return dal_pll_clock_source_dce110_create(
-+					clk_src_init_data);
-+		case CLOCK_SOURCE_ID_EXTERNAL:
-+			return dal_ext_clock_source_dce110_create(
-+					clk_src_init_data);
-+		case CLOCK_SOURCE_ID_VCE:
-+			return dal_vce_clock_source_dce110_create(
-+					clk_src_init_data);
-+		default:
-+			return NULL;
-+		}
-+	}
-+	break;
-+#endif
-+	default:
-+		dal_logger_write(clk_src_init_data->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Clock Source (id %d): not supported DCE version %d",
-+			clk_src_id,
-+			dce_ver);
-+		ASSERT_CRITICAL(false);
-+	break;
-+	}
-+	return NULL;
-+}
-+
-+const struct spread_spectrum_data *dal_clock_source_get_ss_data_entry(
-+		struct clock_source *clk_src,
-+		enum signal_type signal,
-+		uint32_t pix_clk_khz)
-+{
-+
-+	uint32_t entrys_num;
-+	uint32_t i;
-+	struct spread_spectrum_data *ss_parm = NULL;
-+	struct spread_spectrum_data *ret = NULL;
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		ss_parm = clk_src->dvi_ss_params;
-+		entrys_num = clk_src->dvi_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		ss_parm = clk_src->hdmi_ss_params;
-+		entrys_num = clk_src->hdmi_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_LVDS:
-+		ss_parm = clk_src->ep_ss_params;
-+		entrys_num = clk_src->ep_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		ss_parm = clk_src->dp_ss_params;
-+		entrys_num = clk_src->dp_ss_params_cnt;
-+		break;
-+
-+	default:
-+		ss_parm = NULL;
-+		entrys_num = 0;
-+		break;
-+	}
-+
-+	if (ss_parm == NULL)
-+		return ret;
-+
-+	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
-+		if (ss_parm->freq_range_khz >= pix_clk_khz) {
-+			ret = ss_parm;
-+			break;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+bool dal_clock_source_base_adjust_dto_pix_rate(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		uint32_t requested_pix_clk_hz)
-+{
-+	return false;
-+}
-+
-+/* Adjust clock to match given pixel rate (SS/DeepColor compensated)*/
-+bool dal_clock_source_base_adjust_pll_pixel_rate(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		uint32_t requestedPixelClockInHz)
-+{
-+	return false;
-+}
-+
-+static uint32_t retrieve_raw_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params)
-+{
-+	if (dc_is_dp_signal(pix_clk_params->signal_type))
-+		return clk_src->funcs->retrieve_dto_pix_rate_hz(
-+				clk_src,
-+				pix_clk_params);
-+	else
-+		return clk_src->funcs->retrieve_pll_pix_rate_hz(
-+				clk_src,
-+				pix_clk_params);
-+}
-+
-+
-+
-+bool dal_clock_source_adjust_pxl_clk_by_pxl_amount(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		int32_t pix_num)
-+{
-+
-+	uint32_t cur_pix_rate_hz;
-+	uint32_t reqested_pix_rate_hz;
-+	bool success = false;
-+
-+	if (pix_clk_params == NULL)
-+			return false;
-+
-+	cur_pix_rate_hz = retrieve_raw_pix_rate_hz(clk_src, pix_clk_params);
-+	reqested_pix_rate_hz = cur_pix_rate_hz + pix_num;
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[start]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n",
-+		__func__,
-+		(cur_pix_rate_hz / 1000000),
-+		(cur_pix_rate_hz / 1000) % 1000,
-+		(cur_pix_rate_hz % 1000),
-+		(reqested_pix_rate_hz / 1000000),
-+		(reqested_pix_rate_hz / 1000) % 1000,
-+		(reqested_pix_rate_hz % 1000));
-+
-+	if (dc_is_dp_signal(pix_clk_params->signal_type))
-+		success = clk_src->funcs->adjust_dto_pixel_rate(clk_src,
-+				pix_clk_params,
-+				reqested_pix_rate_hz);
-+	else
-+		success = clk_src->funcs->adjust_pll_pixel_rate(
-+				clk_src,
-+				pix_clk_params,
-+				reqested_pix_rate_hz);
-+
-+	cur_pix_rate_hz = retrieve_raw_pix_rate_hz(clk_src, pix_clk_params);
-+
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[end]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n\n",
-+		__func__,
-+		(cur_pix_rate_hz / 1000000),
-+		(cur_pix_rate_hz / 1000) % 1000,
-+		(cur_pix_rate_hz % 1000),
-+		(reqested_pix_rate_hz / 1000000),
-+		(reqested_pix_rate_hz / 1000) % 1000,
-+		(reqested_pix_rate_hz % 1000));
-+
-+	return success;
-+}
-+
-+/***************************/
-+/* private methods section */
-+/***************************/
-+
-+void dal_clock_source_get_ss_info_from_atombios(
-+		struct clock_source *clk_src,
-+		enum as_signal_type as_signal,
-+		struct spread_spectrum_data *spread_spectrum_data[],
-+		uint32_t *ss_entries_num)
-+{
-+	enum bp_result bp_result = BP_RESULT_FAILURE;
-+	struct spread_spectrum_info *ss_info;
-+	struct spread_spectrum_data *ss_data;
-+	struct spread_spectrum_info *ss_info_cur;
-+	struct spread_spectrum_data *ss_data_cur;
-+	uint32_t i;
-+
-+	if (ss_entries_num == NULL) {
-+		dal_logger_write(clk_src->ctx->logger,
-+			LOG_MAJOR_SYNC,
-+			LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+			"Invalid entry !!!\n");
-+		return;
-+	}
-+	if (spread_spectrum_data == NULL) {
-+		dal_logger_write(clk_src->ctx->logger,
-+			LOG_MAJOR_SYNC,
-+			LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+			"Invalid array pointer!!!\n");
-+		return;
-+	}
-+
-+	spread_spectrum_data[0] = NULL;
-+	*ss_entries_num = 0;
-+
-+	*ss_entries_num = dal_bios_parser_get_ss_entry_number(
-+			clk_src->bios_parser,
-+			as_signal);
-+	if (*ss_entries_num == 0)
-+		return;
-+
-+	ss_info = dc_service_alloc(clk_src->ctx, sizeof(struct spread_spectrum_info)
-+				* (*ss_entries_num));
-+	ss_info_cur = ss_info;
-+	if (ss_info == NULL)
-+		return;
-+
-+	ss_data = dc_service_alloc(clk_src->ctx, sizeof(struct spread_spectrum_data) *
-+							(*ss_entries_num));
-+	if (ss_data == NULL)
-+		goto out_free_info;
-+
-+	for (i = 0, ss_info_cur = ss_info;
-+		i < (*ss_entries_num);
-+		++i, ++ss_info_cur) {
-+		bp_result = dal_bios_parser_get_spread_spectrum_info(
-+				clk_src->bios_parser,
-+				as_signal,
-+				i,
-+				ss_info_cur);
-+		if (bp_result != BP_RESULT_OK)
-+			goto out_free_data;
-+	}
-+
-+	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
-+		i < (*ss_entries_num);
-+		++i, ++ss_info_cur, ++ss_data_cur) {
-+
-+		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
-+			dal_logger_write(clk_src->ctx->logger,
-+				LOG_MAJOR_SYNC,
-+				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+				"Invalid ATOMBIOS SS Table!!!\n");
-+			goto out_free_data;
-+		}
-+
-+		/* for HDMI check SS percentage,
-+		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
-+		if (as_signal == AS_SIGNAL_TYPE_HDMI
-+				&& ss_info_cur->spread_spectrum_percentage > 6){
-+			/* invalid input, do nothing */
-+			dal_logger_write(clk_src->ctx->logger,
-+				LOG_MAJOR_SYNC,
-+				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+				"Invalid SS percentage ");
-+			dal_logger_write(clk_src->ctx->logger,
-+				LOG_MAJOR_SYNC,
-+				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+				"for HDMI in ATOMBIOS info Table!!!\n");
-+			continue;
-+		}
-+		if (ss_info_cur->spread_percentage_divider == 1000) {
-+			/* Keep previous precision from ATOMBIOS for these
-+			* in case new precision set by ATOMBIOS for these
-+			* (otherwise all code in DCE specific classes
-+			* for all previous ASICs would need
-+			* to be updated for SS calculations,
-+			* Audio SS compensation and DP DTO SS compensation
-+			* which assumes fixed SS percentage Divider = 100)*/
-+			ss_info_cur->spread_spectrum_percentage /= 10;
-+			ss_info_cur->spread_percentage_divider = 100;
-+		}
-+
-+		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
-+		ss_data_cur->percentage =
-+				ss_info_cur->spread_spectrum_percentage;
-+		ss_data_cur->percentage_divider =
-+				ss_info_cur->spread_percentage_divider;
-+		ss_data_cur->modulation_freq_hz =
-+				ss_info_cur->spread_spectrum_range;
-+
-+		if (ss_info_cur->type.CENTER_MODE)
-+			ss_data_cur->flags.CENTER_SPREAD = 1;
-+
-+		if (ss_info_cur->type.EXTERNAL)
-+			ss_data_cur->flags.EXTERNAL_SS = 1;
-+
-+	}
-+
-+	*spread_spectrum_data = ss_data;
-+	dc_service_free(clk_src->ctx, ss_info);
-+	return;
-+
-+out_free_data:
-+	dc_service_free(clk_src->ctx, ss_data);
-+	*ss_entries_num = 0;
-+out_free_info:
-+	dc_service_free(clk_src->ctx, ss_info);
-+}
-+
-+uint32_t dal_clock_source_base_retrieve_dto_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params)
-+{
-+	return 0;
-+}
-+
-+
-+uint32_t dal_clock_source_base_retrieve_pll_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params)
-+{
-+	return 0;
-+}
-+
-+/*****************************/
-+/* interface methods section */
-+/*****************************/
-+
-+enum clock_source_id dal_clock_source_get_id(
-+		const struct clock_source *clk_src)
-+{
-+	return clk_src->clk_src_id;
-+}
-+
-+bool dal_clock_source_is_clk_src_with_fixed_freq(
-+		const struct clock_source *clk_src)
-+{
-+	return clk_src->is_clock_source_with_fixed_freq;
-+}
-+
-+const struct graphics_object_id dal_clock_source_get_graphics_object_id(
-+		const struct clock_source *clk_src)
-+{
-+	return clk_src->id;
-+}
-+
-+enum clock_sharing_level dal_clock_souce_get_clk_sharing_lvl(
-+		const struct clock_source *clk_src)
-+{
-+	return clk_src->clk_sharing_lvl;
-+}
-+
-+uint32_t dal_clock_source_get_pix_clk_dividers(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	return clk_src->funcs->
-+		get_pix_clk_dividers(clk_src, pix_clk_params, pll_settings);
-+}
-+
-+bool dal_clock_source_program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	return clk_src->funcs->
-+			program_pix_clk(clk_src, pix_clk_params, pll_settings);
-+}
-+
-+/* TODO save/restore FP was here */
-+bool dal_clock_source_adjust_pxl_clk_by_ref_pixel_rate(
-+					struct clock_source *clk_src,
-+					struct pixel_clk_params *pix_clk_params,
-+					uint32_t pix_rate_hz)
-+{
-+	uint32_t current_pix_rate_hz = 0;
-+	uint32_t raw_cur_pix_rate_hz = 0;
-+	uint32_t raw_pix_rate_hz = pix_rate_hz;
-+	bool success = false;
-+
-+	if (pix_clk_params == NULL || pix_rate_hz == 0)
-+		return false;
-+
-+	current_pix_rate_hz = retrieve_raw_pix_rate_hz(
-+				clk_src,
-+				pix_clk_params);
-+	raw_cur_pix_rate_hz = current_pix_rate_hz;
-+
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[start]: Current: %u,%03u,%03uHz, Requested: %u,%03u,%03uHz\n",
-+		__func__,
-+		(current_pix_rate_hz / 1000000),
-+		(current_pix_rate_hz / 1000) % 1000,
-+		(current_pix_rate_hz % 1000),
-+		(pix_rate_hz / 1000000),
-+		(pix_rate_hz / 1000) % 1000,
-+		(pix_rate_hz % 1000));
-+
-+	if (dc_is_dp_signal(pix_clk_params->signal_type))
-+		success = clk_src->funcs->adjust_dto_pixel_rate(
-+				clk_src,
-+				pix_clk_params,
-+				raw_pix_rate_hz);
-+	else
-+		success = clk_src->funcs->adjust_pll_pixel_rate(
-+				clk_src,
-+				pix_clk_params,
-+				raw_pix_rate_hz);
-+
-+	if (dc_is_dp_signal(pix_clk_params->signal_type))
-+		raw_cur_pix_rate_hz = clk_src->funcs->
-+				retrieve_dto_pix_rate_hz(
-+						clk_src,
-+						pix_clk_params);
-+	else
-+		raw_cur_pix_rate_hz = clk_src->funcs->
-+				retrieve_pll_pix_rate_hz(
-+						clk_src,
-+						pix_clk_params);
-+
-+	current_pix_rate_hz = raw_cur_pix_rate_hz;
-+
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[end]: Current: %u,%03u,%03uHz, Requested: %u,%03u,%03uHz\n",
-+		__func__,
-+		(current_pix_rate_hz / 1000000),
-+		(current_pix_rate_hz / 1000) % 1000,
-+		(current_pix_rate_hz % 1000),
-+		(pix_rate_hz / 1000000),
-+		(pix_rate_hz / 1000) % 1000,
-+		(pix_rate_hz % 1000));
-+
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[end]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n\n",
-+		__func__,
-+		(raw_cur_pix_rate_hz / 1000000),
-+		(raw_cur_pix_rate_hz / 1000) % 1000,
-+		(raw_cur_pix_rate_hz % 1000),
-+		(raw_pix_rate_hz / 1000000),
-+		(raw_pix_rate_hz / 1000) % 1000,
-+		(raw_pix_rate_hz % 1000));
-+
-+	return success;
-+}
-+
-+/* TODO store/restore FP was here*/
-+bool dal_clock_source_adjust_pxl_clk_by_pix_amount(
-+					struct clock_source *clk_src,
-+					struct pixel_clk_params *pix_clk_params,
-+					int32_t pix_num)
-+{
-+	bool success = false;
-+	uint32_t requested_pix_rate_hz;
-+	uint32_t cur_pix_rate_hz = retrieve_raw_pix_rate_hz(
-+			clk_src,
-+			pix_clk_params);
-+	requested_pix_rate_hz = cur_pix_rate_hz + pix_num;
-+
-+	if (pix_clk_params == NULL)
-+		return false;
-+
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[start]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n",
-+		__func__,
-+		(cur_pix_rate_hz / 1000000),
-+		(cur_pix_rate_hz / 1000) % 1000,
-+		(cur_pix_rate_hz % 1000),
-+		(requested_pix_rate_hz / 1000000),
-+		(requested_pix_rate_hz / 1000) % 1000,
-+		(requested_pix_rate_hz % 1000));
-+
-+	if (dc_is_dp_signal(pix_clk_params->signal_type))
-+		success = clk_src->funcs->adjust_dto_pixel_rate(
-+				clk_src,
-+				pix_clk_params,
-+				requested_pix_rate_hz);
-+	else
-+		success = clk_src->funcs->adjust_pll_pixel_rate(
-+				clk_src,
-+				pix_clk_params,
-+				requested_pix_rate_hz);
-+
-+	cur_pix_rate_hz = retrieve_raw_pix_rate_hz(clk_src, pix_clk_params);
-+
-+	dal_logger_write(clk_src->ctx->logger,
-+		LOG_MAJOR_SYNC,
-+		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+		"%s[end]: Current(Raw): %u,%03u,%03uHz,Requested(Raw): %u,%03u,%03uHz\n\n",
-+		__func__,
-+		(cur_pix_rate_hz / 1000000),
-+		(cur_pix_rate_hz / 1000) % 1000,
-+		(cur_pix_rate_hz % 1000),
-+		(requested_pix_rate_hz / 1000000),
-+		(requested_pix_rate_hz / 1000) % 1000,
-+		(requested_pix_rate_hz % 1000));
-+
-+	return success;
-+}
-+
-+/* TODO save/restore FP was here*/
-+uint32_t dal_clock_source_retrieve_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params)
-+{
-+	uint32_t pixel_rate_hz = 0;
-+
-+	if (pix_clk_params == NULL)
-+		return pixel_rate_hz;
-+
-+	if (dc_is_dp_signal(pix_clk_params->signal_type))
-+		pixel_rate_hz = clk_src->funcs->retrieve_dto_pix_rate_hz(
-+							clk_src,
-+							pix_clk_params);
-+	else
-+		pixel_rate_hz = clk_src->funcs->retrieve_pll_pix_rate_hz(
-+							clk_src,
-+							pix_clk_params);
-+
-+
-+	return pixel_rate_hz;
-+}
-+
-+bool dal_clock_source_construct(
-+			struct clock_source *clk_src,
-+			struct clock_source_init_data *clk_src_init_data)
-+{
-+	if (clk_src_init_data == NULL || clk_src_init_data->as == NULL)
-+		return false;
-+	clk_src->ctx = clk_src_init_data->ctx;
-+	clk_src->id = clk_src_init_data->clk_src_id;
-+	clk_src->adapter_service = clk_src_init_data->as;
-+	clk_src->bios_parser = dal_adapter_service_get_bios_parser(
-+			clk_src_init_data->as);
-+	clk_src->turn_off_ds = false;
-+	clk_src->clk_src_id = dal_graphics_object_id_get_clock_source_id(
-+						clk_src_init_data->clk_src_id);
-+	clk_src->is_gen_lock_capable = true;
-+/*NOTE is_gen_lock_capable is false only for ext clock source dce80 */
-+
-+	clk_src->ep_ss_params = NULL;
-+	clk_src->dp_ss_params = NULL;
-+	clk_src->hdmi_ss_params = NULL;
-+	clk_src->hdmi_ss_params = NULL;
-+	clk_src->ep_ss_params_cnt = 0;
-+	clk_src->dp_ss_params_cnt = 0;
-+	clk_src->hdmi_ss_params_cnt = 0;
-+	clk_src->dvi_ss_params_cnt = 0;
-+	clk_src->output_signals = SIGNAL_TYPE_ALL;
-+	clk_src->input_signals = SIGNAL_TYPE_ALL;
-+
-+	return true;
-+}
-+
-+void dal_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	if (!clk_src || !(*clk_src))
-+		return;
-+
-+	(*clk_src)->funcs->destroy(clk_src);
-+
-+	*clk_src = NULL;
-+}
-+
-+bool dal_clock_source_is_input_signal_supported(
-+		struct clock_source *clk_src,
-+		enum signal_type signal_type)
-+{
-+	/* TODO do we need this in clock_source ?? */
-+	return (clk_src->input_signals & signal_type) != 0;
-+}
-+
-+bool dal_clock_source_is_output_signal_supported(
-+		const struct clock_source *clk_src,
-+		enum signal_type signal_type)
-+{
-+	return (clk_src->output_signals & signal_type) != 0;
-+}
-+
-+bool dal_clock_source_is_gen_lock_capable(struct clock_source *clk_src)
-+{
-+	return clk_src->is_gen_lock_capable;
-+}
-+
-+bool dal_clock_source_power_down_pll(struct clock_source *clk_src,
-+		enum controller_id controller_id)
-+{
-+	return clk_src->funcs->power_down_pll(clk_src, controller_id);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-new file mode 100644
-index 0000000..0a83874
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-@@ -0,0 +1,136 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CLOCK_SOURCE_H__
-+#define __DAL_CLOCK_SOURCE_H__
-+
-+#include "include/adapter_service_types.h"
-+#include "include/bios_parser_types.h"
-+#include "include/clock_source_interface.h"
-+#include "include/clock_source_types.h"
-+
-+struct spread_spectrum_data {
-+	uint32_t percentage;		/*> In unit of 0.01% or 0.001%*/
-+	uint32_t percentage_divider;	/*> 100 or 1000	*/
-+	uint32_t freq_range_khz;
-+	uint32_t modulation_freq_hz;
-+
-+	struct spread_spectrum_flags flags;
-+};
-+
-+struct clock_source_impl {
-+	bool (*switch_dp_clock_source)(
-+			struct clock_source *clk_src,
-+			enum controller_id,
-+			enum clock_source_id);
-+	bool (*adjust_pll_pixel_rate)(
-+			struct clock_source *clk_src,
-+			struct pixel_clk_params *pix_clk_params,
-+			uint32_t requested_pix_clk_hz);
-+	bool (*adjust_dto_pixel_rate)(
-+			struct clock_source *clk_src,
-+			struct pixel_clk_params *pix_clk_params,
-+			uint32_t requested_clk_freq_hz);
-+	uint32_t (*retrieve_dto_pix_rate_hz)(
-+			struct clock_source *clk_src,
-+			struct pixel_clk_params *pix_clk_params);
-+	uint32_t (*retrieve_pll_pix_rate_hz)(
-+			struct clock_source *clk_src,
-+			struct pixel_clk_params *pix_clk_params);
-+
-+	uint32_t (*get_pix_clk_dividers)(struct clock_source *clk_src,
-+			struct pixel_clk_params *pix_clk_params,
-+			struct pll_settings *pll_settings);
-+	bool (*program_pix_clk)(struct clock_source *clk_src,
-+			struct pixel_clk_params *pix_clk_params,
-+			struct pll_settings *pll_settings);
-+	bool (*power_down_pll)(struct clock_source *clk_src,
-+			enum controller_id);
-+	void (*destroy)(struct clock_source **clk_src);
-+};
-+
-+void dal_clock_source_get_ss_info_from_atombios(
-+		struct clock_source *clk_src,
-+		enum as_signal_type as_signal,
-+		struct spread_spectrum_data *ss_data[],
-+		uint32_t *ss_entries_num);
-+uint32_t dal_clock_source_base_retrieve_dto_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params);
-+const struct spread_spectrum_data *dal_clock_source_get_ss_data_entry(
-+		struct clock_source *clk_src,
-+		enum signal_type signal,
-+		uint32_t pix_clk_khz);
-+/* for PLL and EXT clock sources */
-+struct registers {
-+	uint32_t dp_dtox_phase;
-+	uint32_t dp_dtox_modulo;
-+	uint32_t crtcx_pixel_rate_cntl;
-+};
-+
-+struct clock_source {
-+	const struct clock_source_impl *funcs;
-+	struct graphics_object_id id;
-+	enum clock_source_id clk_src_id;
-+	struct adapter_service *adapter_service;
-+	struct bios_parser *bios_parser;
-+
-+	struct spread_spectrum_data *ep_ss_params;
-+	uint32_t ep_ss_params_cnt;
-+	struct spread_spectrum_data *dp_ss_params;
-+	uint32_t dp_ss_params_cnt;
-+
-+	struct spread_spectrum_data *hdmi_ss_params;
-+	uint32_t hdmi_ss_params_cnt;
-+
-+	struct spread_spectrum_data *dvi_ss_params;
-+	uint32_t dvi_ss_params_cnt;
-+
-+	uint32_t output_signals;
-+	uint32_t input_signals;
-+
-+	bool turn_off_ds;
-+	bool is_gen_lock_capable; /*replacement for virtual method*/
-+	bool is_clock_source_with_fixed_freq; /*replacement for virtual method*/
-+	enum clock_sharing_level clk_sharing_lvl;
-+	struct dc_context *ctx;
-+};
-+
-+bool dal_clock_source_construct(
-+			struct clock_source *clk_src,
-+			struct clock_source_init_data *clk_src_init_data);
-+bool dal_clock_source_base_adjust_pll_pixel_rate(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		uint32_t requested_pix_clk_hz);
-+bool dal_clock_source_base_adjust_dto_pix_rate(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		uint32_t requested_pix_clk_hz);
-+uint32_t dal_clock_source_base_retrieve_pll_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-new file mode 100644
-index 0000000..f124dba
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-@@ -0,0 +1,92 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dc_clock_generator.h"
-+
-+void dal_dc_clock_generator_destroy(struct dc_clock_generator **dc)
-+{
-+	if (dc == NULL || *dc == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	(*dc)->funcs->destroy(dc);
-+
-+	*dc = NULL;
-+}
-+
-+void dal_dc_clock_generator_set_display_pipe_mapping(
-+	struct dc_clock_generator *dc_clk_gen,
-+	struct dccg_mapping_params *params)
-+{
-+	dc_clk_gen->funcs->set_display_pipe_mapping(dc_clk_gen, params);
-+}
-+
-+bool dal_dc_clock_generator_get_dp_ref_clk_ds_params(
-+	struct dc_clock_generator *dc_clk_gen,
-+	struct dccg_dp_ref_clk_ds_params *params)
-+{
-+	return dc_clk_gen->funcs->get_dp_ref_clk_ds_params(dc_clk_gen, params);
-+}
-+
-+bool dal_dc_clock_generator_enable_gtc_counter(
-+	struct dc_clock_generator *dc_clk_gen,
-+	uint32_t dprefclk)
-+{
-+	return dc_clk_gen->funcs->enable_gtc_counter(dc_clk_gen, dprefclk);
-+}
-+
-+void dal_dc_clock_generator_disable_gtc_counter(
-+	struct dc_clock_generator *dc_clk_gen)
-+{
-+	dc_clk_gen->funcs->disable_gtc_counter(dc_clk_gen);
-+}
-+
-+void dal_dc_clock_generator_set_gtc_group_offset(
-+	struct dc_clock_generator *dc_clk_gen,
-+	enum gtc_group group_num,
-+	uint32_t offset)
-+{
-+	dc_clk_gen->funcs->set_gtc_group_offset(dc_clk_gen, group_num, offset);
-+}
-+
-+void dal_dc_clock_generator_base_set_display_pipe_mapping(
-+	struct dc_clock_generator *base,
-+	struct dccg_mapping_params *params)
-+{
-+
-+}
-+
-+bool dal_dc_clock_generator_construct_base(
-+	struct dc_clock_generator *base,
-+	struct dc_context *ctx
-+)
-+{
-+	base->ctx = ctx;
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h
-new file mode 100644
-index 0000000..d1bf1af
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h
-@@ -0,0 +1,63 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DC_CLOCK_GENERATOR_H__
-+#define __DAL_DC_CLOCK_GENERATOR_H__
-+
-+#include "include/dc_clock_generator_interface.h"
-+
-+struct dc_clock_generator_funcs {
-+	void (*destroy)(struct dc_clock_generator **to_destroy);
-+
-+	void (*set_display_pipe_mapping)(
-+		struct dc_clock_generator *dc_clk_gen,
-+		struct dccg_mapping_params *params);
-+
-+	bool (*get_dp_ref_clk_ds_params)(
-+		struct dc_clock_generator *dc_clk_gen,
-+		struct dccg_dp_ref_clk_ds_params *params);
-+	bool (*enable_gtc_counter)(
-+		struct dc_clock_generator *dc_clk_gen,
-+		uint32_t dprefclk);
-+	void (*disable_gtc_counter)(
-+		struct dc_clock_generator *dc_clk_gen);
-+	void (*set_gtc_group_offset)(
-+		struct dc_clock_generator *dc_clk_gen,
-+		enum gtc_group group_num,
-+		uint32_t offset);
-+};
-+struct dc_clock_generator {
-+	const struct dc_clock_generator_funcs *funcs;
-+	struct dc_context *ctx;
-+};
-+bool dal_dc_clock_generator_construct_base(
-+	struct dc_clock_generator *base,
-+	struct dc_context *ctx
-+);
-+void dal_dc_clock_generator_base_set_display_pipe_mapping(
-+	struct dc_clock_generator *base,
-+	struct dccg_mapping_params *params);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-new file mode 100644
-index 0000000..e2d4228
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-@@ -0,0 +1,90 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dc_clock_gating_dce110.h"
-+
-+/******************************************************************************
-+ * Macro definitions
-+ *****************************************************************************/
-+
-+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_GPU, \
-+		"%s:%s()\n", __FILE__, __func__)
-+
-+/******************************************************************************
-+ * static functions
-+ *****************************************************************************/
-+static void force_hw_base_light_sleep(struct dc_context *ctx)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+
-+	addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
-+	/* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
-+	 * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+			value,
-+			1,
-+			DC_MEM_GLOBAL_PWR_REQ_CNTL,
-+			DC_MEM_GLOBAL_PWR_REQ_DIS);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+}
-+
-+static void enable_hw_base_light_sleep(struct dc_context *ctx)
-+{
-+	NOT_IMPLEMENTED();
-+}
-+
-+static void disable_sw_manual_control_light_sleep(
-+		struct dc_context *ctx)
-+{
-+	NOT_IMPLEMENTED();
-+}
-+
-+/******************************************************************************
-+ * public functions
-+ *****************************************************************************/
-+
-+void dal_dc_clock_gating_dce110_power_up(
-+		struct dc_context *ctx,
-+		bool enable)
-+{
-+	if (enable) {
-+		enable_hw_base_light_sleep(ctx);
-+		disable_sw_manual_control_light_sleep(ctx);
-+	} else {
-+		force_hw_base_light_sleep(ctx);
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
-new file mode 100644
-index 0000000..1bfd75a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DC_CLOCK_GATING_DCE110_H__
-+#define __DAL_DC_CLOCK_GATING_DCE110_H__
-+
-+void dal_dc_clock_gating_dce110_power_up(
-+		struct dc_context *ctx,
-+		bool enable);
-+
-+#endif /* __DAL_DC_CLOCK_GATING_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-new file mode 100644
-index 0000000..e582ba0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -0,0 +1,958 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/fixed32_32.h"
-+#include "include/logger_interface.h"
-+
-+#include "../divider_range.h"
-+
-+#include "display_clock_dce110.h"
-+
-+#define FROM_DISPLAY_CLOCK(base) \
-+	container_of(base, struct display_clock_dce110, disp_clk_base)
-+
-+static struct state_dependent_clocks max_clks_by_state[] = {
-+/*( dvo not exist in KV)*/
-+/*ClocksStateInvalid - should not be used*/
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0, .dvo_clk_khz = 0 },
-+/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000, .dvo_clk_khz = 0 },
-+/*ClocksStateLow*/
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000, .dvo_clk_khz = 0 },
-+/*ClocksStateNominal*/
-+{ .display_clk_khz = 467000, .pixel_clk_khz = 400000, .dvo_clk_khz = 0 },
-+/*ClocksStatePerformance*/
-+{ .display_clk_khz = 643000, .pixel_clk_khz = 400000, .dvo_clk_khz = 0 } };
-+
-+
-+/* Starting point for each divider range.*/
-+enum divider_range_start {
-+	DIVIDER_RANGE_01_START = 200, /* 2.00*/
-+	DIVIDER_RANGE_02_START = 1600, /* 16.00*/
-+	DIVIDER_RANGE_03_START = 3200, /* 32.00*/
-+	DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
-+};
-+
-+/* Array identifiers and count for the divider ranges.*/
-+enum divider_range_count {
-+	DIVIDER_RANGE_01 = 0,
-+	DIVIDER_RANGE_02,
-+	DIVIDER_RANGE_03,
-+	DIVIDER_RANGE_MAX /* == 3*/
-+};
-+
-+/* Ranges for divider identifiers (Divider ID or DID)
-+ mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
-+enum divider_id_register_setting {
-+	DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
-+	DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
-+	DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
-+	DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
-+};
-+
-+/* Step size between each divider within a range.
-+ Incrementing the DENTIST_DISPCLK_WDIVIDER by one
-+ will increment the divider by this much.*/
-+enum divider_range_step_size {
-+	DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
-+	DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
-+	DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
-+};
-+
-+static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
-+
-+#define DCE110_DFS_BYPASS_THRESHOLD_KHZ 400000
-+/*****************************************************************************
-+ * static functions
-+ *****************************************************************************/
-+
-+/*
-+ * store_max_clocks_state
-+ *
-+ * @brief
-+ * Cache the clock state
-+ *
-+ * @param
-+ * struct display_clock *base - [out] cach the state in this structure
-+ * enum clocks_state max_clocks_state - [in] state to be stored
-+ */
-+static void store_max_clocks_state(
-+	struct display_clock *base,
-+	enum clocks_state max_clocks_state)
-+{
-+	struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-+
-+	switch (max_clocks_state) {
-+	case CLOCKS_STATE_LOW:
-+	case CLOCKS_STATE_NOMINAL:
-+	case CLOCKS_STATE_PERFORMANCE:
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		dc->max_clks_state = max_clocks_state;
-+		break;
-+
-+	case CLOCKS_STATE_INVALID:
-+	default:
-+		/*Invalid Clocks State!*/
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+}
-+
-+static enum clocks_state get_min_clocks_state(struct display_clock *base)
-+{
-+	return base->cur_min_clks_state;
-+}
-+
-+static bool set_min_clocks_state(
-+	struct display_clock *base,
-+	enum clocks_state clocks_state)
-+{
-+	struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-+
-+	if (clocks_state > dc->max_clks_state) {
-+		/*Requested state exceeds max supported state.*/
-+		dal_logger_write(base->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Requested state exceeds max supported state");
-+		return false;
-+	} else if (clocks_state == base->cur_min_clks_state) {
-+		/*if we're trying to set the same state, we can just return
-+		 * since nothing needs to be done*/
-+		return true;
-+	}
-+
-+	base->cur_min_clks_state = clocks_state;
-+
-+	return true;
-+}
-+
-+static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
-+{
-+	uint32_t dispclk_cntl_value;
-+	uint32_t dp_ref_clk_cntl_value;
-+	uint32_t dp_ref_clk_cntl_src_sel_value;
-+	uint32_t dp_ref_clk_khz = 600000;
-+	uint32_t target_div = INVALID_DIVIDER;
-+	struct display_clock_dce110 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	/* ASSERT DP Reference Clock source is from DFS*/
-+	dp_ref_clk_cntl_value = dal_read_reg(dc->ctx,
-+			mmDPREFCLK_CNTL);
-+
-+	dp_ref_clk_cntl_src_sel_value =
-+			get_reg_field_value(
-+				dp_ref_clk_cntl_value,
-+				DPREFCLK_CNTL, DPREFCLK_SRC_SEL);
-+
-+	ASSERT(dp_ref_clk_cntl_src_sel_value == 0);
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
-+	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
-+	dispclk_cntl_value = dal_read_reg(dc->ctx,
-+			mmDENTIST_DISPCLK_CNTL);
-+
-+	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
-+	target_div = dal_divider_range_get_divider(
-+		divider_ranges,
-+		DIVIDER_RANGE_MAX,
-+		get_reg_field_value(dispclk_cntl_value,
-+			DENTIST_DISPCLK_CNTL,
-+			DENTIST_DPREFCLK_WDIVIDER));
-+
-+
-+	if (target_div != INVALID_DIVIDER) {
-+		/* Calculate the current DFS clock, in kHz.*/
-+		dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
-+			* disp_clk->dentist_vco_freq_khz) / target_div;
-+	}
-+
-+	/* SW will adjust DP REF Clock average value for all purposes
-+	 * (DP DTO / DP Audio DTO and DP GTC)
-+	 if clock is spread for all cases:
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
-+	 calculations for DS_INCR/DS_MODULO (this is planned to be default case)
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
-+	 calculations (not planned to be used, but average clock should still
-+	 be valid)
-+	 -if SS enabled on DP Ref clock and HW de-spreading disabled
-+	 (should not be case with CIK) then SW should program all rates
-+	 generated according to average value (case as with previous ASICs)
-+	  */
-+	if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) {
-+		struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+					disp_clk->gpu_pll_ss_percentage,
-+					disp_clk->gpu_pll_ss_divider), 200);
-+		struct fixed32_32 adj_dp_ref_clk_khz;
-+
-+		ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
-+								ss_percentage);
-+		adj_dp_ref_clk_khz =
-+			dal_fixed32_32_mul_int(
-+				ss_percentage,
-+				dp_ref_clk_khz);
-+		dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
-+	}
-+
-+	return dp_ref_clk_khz;
-+}
-+
-+
-+static void destroy(struct display_clock **base)
-+{
-+	struct display_clock_dce110 *dc110;
-+
-+	dc110 = DCLCK110_FROM_BASE(*base);
-+
-+	dc_service_free((*base)->ctx, dc110);
-+
-+	*base = NULL;
-+}
-+
-+static uint32_t get_validation_clock(struct display_clock *dc)
-+{
-+	uint32_t clk = 0;
-+	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-+
-+	switch (disp_clk->max_clks_state) {
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		/*Currently not supported, it has 0 in table entry*/
-+	case CLOCKS_STATE_LOW:
-+		clk = max_clks_by_state[CLOCKS_STATE_LOW].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_NOMINAL:
-+		clk = max_clks_by_state[CLOCKS_STATE_NOMINAL].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_PERFORMANCE:
-+		clk = max_clks_by_state[CLOCKS_STATE_PERFORMANCE].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_INVALID:
-+	default:
-+		/*Invalid Clocks State*/
-+		dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Invalid clock state");
-+		/* just return the display engine clock for
-+		 * lowest supported state*/
-+		clk = max_clks_by_state[CLOCKS_STATE_LOW].
-+						display_clk_khz;
-+		break;
-+	}
-+	return clk;
-+}
-+
-+static struct fixed32_32 get_deep_color_factor(struct min_clock_params *params)
-+{
-+	/* DeepColorFactor = IF (HDMI = True, bpp / 24, 1)*/
-+	struct fixed32_32 deep_color_factor = dal_fixed32_32_from_int(1);
-+
-+	if (params->signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return deep_color_factor;
-+
-+	switch (params->deep_color_depth) {
-+	case COLOR_DEPTH_101010:
-+		/*deep color ratio for 30bpp is 30/24 = 1.25*/
-+		deep_color_factor = dal_fixed32_32_from_fraction(30, 24);
-+		break;
-+
-+	case COLOR_DEPTH_121212:
-+		/* deep color ratio for 36bpp is 36/24 = 1.5*/
-+		deep_color_factor = dal_fixed32_32_from_fraction(36, 24);
-+		break;
-+
-+	case COLOR_DEPTH_161616:
-+		/* deep color ratio for 48bpp is 48/24 = 2.0 */
-+		deep_color_factor = dal_fixed32_32_from_fraction(48, 24);
-+		break;
-+	default:
-+		break;
-+	}
-+	return deep_color_factor;
-+}
-+
-+static struct fixed32_32 get_scaler_efficiency(
-+	struct dc_context *ctx,
-+	struct min_clock_params *params)
-+{
-+	struct fixed32_32 scaler_efficiency = dal_fixed32_32_from_int(3);
-+
-+	if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB18BPP) {
-+		scaler_efficiency =
-+			dal_fixed32_32_add(
-+				dal_fixed32_32_from_fraction(35555, 10000),
-+				dal_fixed32_32_from_fraction(
-+					55556,
-+					100000 * 10000));
-+	} else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB24BPP) {
-+		scaler_efficiency =
-+			dal_fixed32_32_add(
-+				dal_fixed32_32_from_fraction(34285, 10000),
-+				dal_fixed32_32_from_fraction(
-+					71429,
-+					100000 * 10000));
-+	} else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB30BPP)
-+		scaler_efficiency = dal_fixed32_32_from_fraction(32, 10);
-+
-+	return scaler_efficiency;
-+}
-+
-+static struct fixed32_32 get_lb_lines_in_per_line_out(
-+		struct min_clock_params *params,
-+		struct fixed32_32 v_scale_ratio)
-+{
-+	struct fixed32_32 two = dal_fixed32_32_from_int(2);
-+	struct fixed32_32 four = dal_fixed32_32_from_int(4);
-+	struct fixed32_32 f4_to_3 = dal_fixed32_32_from_fraction(4, 3);
-+	struct fixed32_32 f6_to_4 = dal_fixed32_32_from_fraction(6, 4);
-+
-+	if (params->line_buffer_prefetch_enabled)
-+		return dal_fixed32_32_max(v_scale_ratio, dal_fixed32_32_one);
-+	else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_one))
-+		return dal_fixed32_32_one;
-+	else if (dal_fixed32_32_le(v_scale_ratio, f4_to_3))
-+		return f4_to_3;
-+	else if (dal_fixed32_32_le(v_scale_ratio, f6_to_4))
-+		return f6_to_4;
-+	else if (dal_fixed32_32_le(v_scale_ratio, two))
-+		return two;
-+	else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_from_int(3)))
-+		return four;
-+	else
-+		return dal_fixed32_32_zero;
-+}
-+
-+static uint32_t get_actual_required_display_clk(
-+	struct display_clock_dce110 *disp_clk,
-+	uint32_t target_clk_khz)
-+{
-+	uint32_t disp_clk_khz = target_clk_khz;
-+	uint32_t div = INVALID_DIVIDER;
-+	uint32_t did = INVALID_DID;
-+	uint32_t scaled_vco =
-+		disp_clk->dentist_vco_freq_khz * DIVIDER_RANGE_SCALE_FACTOR;
-+
-+	ASSERT_CRITICAL(!!disp_clk_khz);
-+
-+	if (disp_clk_khz)
-+		div = scaled_vco / disp_clk_khz;
-+
-+	did = dal_divider_range_get_did(divider_ranges, DIVIDER_RANGE_MAX, div);
-+
-+	if (did != INVALID_DID) {
-+		div = dal_divider_range_get_divider(
-+			divider_ranges, DIVIDER_RANGE_MAX, did);
-+
-+		if ((div != INVALID_DIVIDER) &&
-+			(did > DIVIDER_RANGE_01_BASE_DIVIDER_ID))
-+			if (disp_clk_khz > (scaled_vco / div))
-+				div = dal_divider_range_get_divider(
-+					divider_ranges, DIVIDER_RANGE_MAX,
-+					did - 1);
-+
-+		if (div != INVALID_DIVIDER)
-+			disp_clk_khz = scaled_vco / div;
-+
-+	}
-+	/* We need to add 10KHz to this value because the accuracy in VBIOS is
-+	 in 10KHz units. So we need to always round the last digit up in order
-+	 to reach the next div level.*/
-+	return disp_clk_khz + 10;
-+}
-+
-+static uint32_t calc_single_display_min_clks(
-+	struct display_clock *base,
-+	struct min_clock_params *params,
-+	bool set_clk)
-+{
-+	struct fixed32_32 h_scale_ratio = dal_fixed32_32_one;
-+	struct fixed32_32 v_scale_ratio = dal_fixed32_32_one;
-+	uint32_t pix_clk_khz = 0;
-+	uint32_t lb_source_width = 0;
-+	struct fixed32_32 deep_color_factor;
-+	struct fixed32_32 scaler_efficiency;
-+	struct fixed32_32 v_filter_init;
-+	uint32_t v_filter_init_trunc;
-+	uint32_t num_lines_at_frame_start = 3;
-+	struct fixed32_32 v_filter_init_ceil;
-+	struct fixed32_32 lines_per_lines_out_at_frame_start;
-+	struct fixed32_32 lb_lines_in_per_line_out; /* in middle of the frame*/
-+	uint32_t src_wdth_rnd_to_chunks;
-+	struct fixed32_32 scaling_coeff;
-+	struct fixed32_32 h_blank_granularity_factor =
-+			dal_fixed32_32_one;
-+	struct fixed32_32 fx_disp_clk_mhz;
-+	struct fixed32_32 line_time;
-+	struct fixed32_32 disp_pipe_pix_throughput;
-+	struct fixed32_32 fx_alt_disp_clk_mhz;
-+	uint32_t disp_clk_khz;
-+	uint32_t alt_disp_clk_khz;
-+	struct display_clock_dce110 *disp_clk_110 = DCLCK110_FROM_BASE(base);
-+	uint32_t max_clk_khz = get_validation_clock(base);
-+	bool panning_allowed = false; /* TODO: receive this value from AS */
-+
-+	if (params == NULL) {
-+		dal_logger_write(base->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Invalid input parameter in %s",
-+				__func__);
-+		return 0;
-+	}
-+
-+	deep_color_factor = get_deep_color_factor(params);
-+	scaler_efficiency = get_scaler_efficiency(base->ctx, params);
-+	pix_clk_khz = params->requested_pixel_clock;
-+	lb_source_width = params->source_view.width;
-+
-+	if (0 != params->dest_view.height && 0 != params->dest_view.width) {
-+
-+		h_scale_ratio = dal_fixed32_32_from_fraction(
-+			params->source_view.width,
-+			params->dest_view.width);
-+		v_scale_ratio = dal_fixed32_32_from_fraction(
-+			params->source_view.height,
-+			params->dest_view.height);
-+	} else {
-+		dal_logger_write(base->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Destination height or width is 0!\n");
-+	}
-+
-+	v_filter_init =
-+		dal_fixed32_32_add(
-+			v_scale_ratio,
-+			dal_fixed32_32_add_int(
-+				dal_fixed32_32_div_int(
-+					dal_fixed32_32_mul_int(
-+						v_scale_ratio,
-+						params->timing_info.INTERLACED),
-+					2),
-+				params->scaling_info.v_taps + 1));
-+	v_filter_init = dal_fixed32_32_div_int(v_filter_init, 2);
-+
-+	v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
-+
-+	v_filter_init_ceil = dal_fixed32_32_from_fraction(
-+						v_filter_init_trunc, 2);
-+	v_filter_init_ceil = dal_fixed32_32_from_int(
-+		dal_fixed32_32_ceil(v_filter_init_ceil));
-+	v_filter_init_ceil = dal_fixed32_32_mul_int(v_filter_init_ceil, 2);
-+
-+	lines_per_lines_out_at_frame_start =
-+			dal_fixed32_32_div_int(v_filter_init_ceil,
-+					num_lines_at_frame_start);
-+	lb_lines_in_per_line_out =
-+			get_lb_lines_in_per_line_out(params, v_scale_ratio);
-+
-+	if (panning_allowed)
-+		src_wdth_rnd_to_chunks =
-+			((lb_source_width - 1) / 128) * 128 + 256;
-+	else
-+		src_wdth_rnd_to_chunks =
-+			((lb_source_width + 127) / 128) * 128;
-+
-+	scaling_coeff =
-+		dal_fixed32_32_div(
-+			dal_fixed32_32_from_int(params->scaling_info.v_taps),
-+			scaler_efficiency);
-+
-+	if (dal_fixed32_32_le(h_scale_ratio, dal_fixed32_32_one))
-+		scaling_coeff = dal_fixed32_32_max(
-+			dal_fixed32_32_from_int(
-+				dal_fixed32_32_ceil(
-+					dal_fixed32_32_from_fraction(
-+						params->scaling_info.h_taps,
-+						4))),
-+			dal_fixed32_32_max(
-+				dal_fixed32_32_mul(
-+					scaling_coeff,
-+					h_scale_ratio),
-+				dal_fixed32_32_one));
-+
-+	if (!params->line_buffer_prefetch_enabled &&
-+		dal_fixed32_32_floor(lb_lines_in_per_line_out) != 2 &&
-+		dal_fixed32_32_floor(lb_lines_in_per_line_out) != 4) {
-+		uint32_t line_total_pixel =
-+			params->timing_info.h_total + lb_source_width - 256;
-+		h_blank_granularity_factor = dal_fixed32_32_div(
-+			dal_fixed32_32_from_int(params->timing_info.h_total),
-+			dal_fixed32_32_div(
-+			dal_fixed32_32_from_fraction(
-+				line_total_pixel, 2),
-+				h_scale_ratio));
-+	}
-+
-+	/* Calculate display clock with ramping. Ramping factor is 1.1*/
-+	fx_disp_clk_mhz =
-+		dal_fixed32_32_div_int(
-+			dal_fixed32_32_mul_int(scaling_coeff, 11),
-+			10);
-+	line_time = dal_fixed32_32_from_fraction(
-+			params->timing_info.h_total * 1000, pix_clk_khz);
-+
-+	disp_pipe_pix_throughput = dal_fixed32_32_mul(
-+			lb_lines_in_per_line_out, h_blank_granularity_factor);
-+	disp_pipe_pix_throughput = dal_fixed32_32_max(
-+			disp_pipe_pix_throughput,
-+			lines_per_lines_out_at_frame_start);
-+	disp_pipe_pix_throughput = dal_fixed32_32_div(dal_fixed32_32_mul_int(
-+			disp_pipe_pix_throughput, src_wdth_rnd_to_chunks),
-+			line_time);
-+
-+	if (0 != params->timing_info.h_total) {
-+		fx_disp_clk_mhz =
-+			dal_fixed32_32_max(
-+				dal_fixed32_32_div_int(
-+					dal_fixed32_32_mul_int(
-+						scaling_coeff, pix_clk_khz),
-+						1000),
-+				disp_pipe_pix_throughput);
-+		fx_disp_clk_mhz =
-+			dal_fixed32_32_mul(
-+				fx_disp_clk_mhz,
-+				dal_fixed32_32_from_fraction(11, 10));
-+	}
-+
-+	fx_disp_clk_mhz = dal_fixed32_32_max(fx_disp_clk_mhz,
-+		dal_fixed32_32_mul(deep_color_factor,
-+		dal_fixed32_32_from_fraction(11, 10)));
-+
-+	/* Calculate display clock without ramping */
-+	fx_alt_disp_clk_mhz = scaling_coeff;
-+
-+	if (0 != params->timing_info.h_total) {
-+		fx_alt_disp_clk_mhz = dal_fixed32_32_max(
-+				dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
-+						scaling_coeff, pix_clk_khz),
-+						1000),
-+				dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
-+						disp_pipe_pix_throughput, 105),
-+						100));
-+	}
-+
-+	if (set_clk && disp_clk_110->ss_on_gpu_pll &&
-+			disp_clk_110->gpu_pll_ss_divider)
-+		fx_alt_disp_clk_mhz = dal_fixed32_32_mul(fx_alt_disp_clk_mhz,
-+				dal_fixed32_32_add_int(
-+				dal_fixed32_32_div_int(
-+				dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+				disp_clk_110->gpu_pll_ss_percentage,
-+				disp_clk_110->gpu_pll_ss_divider), 100),
-+				2),
-+				1));
-+
-+	/* convert to integer */
-+	disp_clk_khz = dal_fixed32_32_round(
-+			dal_fixed32_32_mul_int(fx_disp_clk_mhz, 1000));
-+	alt_disp_clk_khz = dal_fixed32_32_round(
-+			dal_fixed32_32_mul_int(fx_alt_disp_clk_mhz, 1000));
-+
-+	if ((disp_clk_khz > max_clk_khz) && (alt_disp_clk_khz <= max_clk_khz))
-+		disp_clk_khz = alt_disp_clk_khz;
-+
-+	if (set_clk) { /* only compensate clock if we are going to set it.*/
-+		disp_clk_khz = get_actual_required_display_clk(
-+			disp_clk_110, disp_clk_khz);
-+	}
-+
-+	disp_clk_khz = disp_clk_khz > max_clk_khz ? max_clk_khz : disp_clk_khz;
-+
-+	return disp_clk_khz;
-+}
-+
-+static uint32_t calculate_min_clock(
-+	struct display_clock *base,
-+	uint32_t path_num,
-+	struct min_clock_params *params)
-+{
-+	uint32_t i;
-+	uint32_t validation_clk_khz =
-+			get_validation_clock(base);
-+	uint32_t min_clk_khz = validation_clk_khz;
-+	uint32_t max_clk_khz = 0;
-+	struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-+
-+	if (dc->use_max_disp_clk)
-+		return min_clk_khz;
-+
-+	if (params != NULL) {
-+		uint32_t disp_clk_khz = 0;
-+
-+		for (i = 0; i < path_num; ++i) {
-+
-+			disp_clk_khz = calc_single_display_min_clks(
-+							base, params, true);
-+
-+			/* update the max required clock found*/
-+			if (disp_clk_khz > max_clk_khz)
-+				max_clk_khz = disp_clk_khz;
-+
-+			params++;
-+		}
-+	}
-+
-+	min_clk_khz = max_clk_khz;
-+
-+	if (min_clk_khz > validation_clk_khz)
-+		min_clk_khz = validation_clk_khz;
-+	else if (min_clk_khz < base->min_display_clk_threshold_khz)
-+		min_clk_khz = base->min_display_clk_threshold_khz;
-+
-+	if (dc->use_max_disp_clk)
-+		min_clk_khz = get_validation_clock(base);
-+
-+	return min_clk_khz;
-+}
-+
-+static bool display_clock_integrated_info_construct(
-+	struct display_clock_dce110 *disp_clk,
-+	struct adapter_service *as)
-+{
-+	struct integrated_info info;
-+	uint32_t i;
-+
-+	struct display_clock *base = &disp_clk->disp_clk_base;
-+
-+	if (!dal_adapter_service_get_integrated_info(as, &info))
-+		return false;
-+
-+	disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
-+	if (disp_clk->dentist_vco_freq_khz == 0)
-+		disp_clk->dentist_vco_freq_khz = 3600000;
-+
-+	base->min_display_clk_threshold_khz =
-+		disp_clk->dentist_vco_freq_khz / 64;
-+
-+	/*update the maximum display clock for each power state*/
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
-+
-+		switch (i) {
-+		case 0:
-+			clk_state = CLOCKS_STATE_ULTRA_LOW;
-+			break;
-+
-+		case 1:
-+			clk_state = CLOCKS_STATE_LOW;
-+			break;
-+
-+		case 2:
-+			clk_state = CLOCKS_STATE_NOMINAL;
-+			break;
-+
-+		case 3:
-+			clk_state = CLOCKS_STATE_PERFORMANCE;
-+			break;
-+
-+		default:
-+			clk_state = CLOCKS_STATE_INVALID;
-+			break;
-+		}
-+
-+		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
-+		 * check for > 100MHz*/
-+		if (info.disp_clk_voltage[i].max_supported_clk >= 100000) {
-+			max_clks_by_state[clk_state].display_clk_khz =
-+				info.disp_clk_voltage[i].max_supported_clk;
-+		}
-+	}
-+	disp_clk->dfs_bypass_enabled =
-+		dal_adapter_service_is_dfs_bypass_enabled(as);
-+	disp_clk->use_max_disp_clk =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_USE_MAX_DISPLAY_CLK);
-+
-+	return true;
-+}
-+
-+static uint32_t get_clock(struct display_clock *dc)
-+{
-+	uint32_t disp_clock = get_validation_clock(dc);
-+	uint32_t target_div = INVALID_DIVIDER;
-+	uint32_t addr = mmDENTIST_DISPCLK_CNTL;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-+
-+	if (disp_clk->dfs_bypass_enabled && disp_clk->dfs_bypass_disp_clk)
-+		return disp_clk->dfs_bypass_disp_clk;
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
-+	 DID DENTIST_DISPCLK_WDIVIDER.*/
-+	value = dal_read_reg(dc->ctx, addr);
-+	field = get_reg_field_value(
-+			value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
-+
-+	/* Convert DENTIST_DISPCLK_WDIVIDER to actual divider*/
-+	target_div = dal_divider_range_get_divider(
-+		divider_ranges,
-+		DIVIDER_RANGE_MAX,
-+		field);
-+
-+	if (target_div != INVALID_DIVIDER)
-+		/* Calculate the current DFS clock in KHz.
-+		 Should be okay up to 42.9 THz before overflowing.*/
-+		disp_clock = (DIVIDER_RANGE_SCALE_FACTOR
-+			* disp_clk->dentist_vco_freq_khz) / target_div;
-+	return disp_clock;
-+}
-+
-+static enum clocks_state get_required_clocks_state(
-+		struct display_clock *dc,
-+		struct state_dependent_clocks *req_clocks)
-+{
-+	int32_t i;
-+	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-+	enum clocks_state low_req_clk = disp_clk->max_clks_state;
-+
-+	if (!req_clocks) {
-+		/* NULL pointer*/
-+		dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: Invalid parameter",
-+				__func__);
-+		return CLOCKS_STATE_INVALID;
-+	}
-+
-+	/* Iterate from highest supported to lowest valid state, and update
-+	 * lowest RequiredState with the lowest state that satisfies
-+	 * all required clocks
-+	 */
-+	for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
-+		if ((req_clocks->display_clk_khz <=
-+			max_clks_by_state[i].display_clk_khz) &&
-+			(req_clocks->pixel_clk_khz <=
-+				max_clks_by_state[i].pixel_clk_khz))
-+			low_req_clk = i;
-+	}
-+	return low_req_clk;
-+}
-+
-+static void set_clock(
-+	struct display_clock *base,
-+	uint32_t requested_clk_khz)
-+{
-+	struct bp_pixel_clock_parameters pxl_clk_params;
-+	struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-+	struct bios_parser *bp = dal_adapter_service_get_bios_parser(base->as);
-+
-+	/* Prepare to program display clock*/
-+	dc_service_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-+
-+	pxl_clk_params.target_pixel_clock = requested_clk_khz;
-+	pxl_clk_params.pll_id = base->id;
-+
-+	dal_bios_parser_program_display_engine_pll(bp, &pxl_clk_params);
-+
-+	if (dc->dfs_bypass_enabled) {
-+
-+		/* Cache the fixed display clock*/
-+		dc->dfs_bypass_disp_clk =
-+			pxl_clk_params.dfs_bypass_display_clock;
-+	}
-+
-+	/* from power down, we need mark the clock state as ClocksStateNominal
-+	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-+	if (requested_clk_khz == 0)
-+		base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
-+}
-+
-+static void set_clock_state(
-+	struct display_clock *dc,
-+	struct display_clock_state clk_state)
-+{
-+	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-+
-+	disp_clk->clock_state = clk_state;
-+}
-+
-+static struct display_clock_state get_clock_state(
-+	struct display_clock *dc)
-+{
-+	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-+
-+	return disp_clk->clock_state;
-+}
-+
-+static uint32_t get_dfs_bypass_threshold(struct display_clock *dc)
-+{
-+	return DCE110_DFS_BYPASS_THRESHOLD_KHZ;
-+}
-+
-+static const struct display_clock_funcs funcs = {
-+	.destroy = destroy,
-+	.calculate_min_clock = calculate_min_clock,
-+	.get_clock = get_clock,
-+	.get_clock_state = get_clock_state,
-+	.get_dfs_bypass_threshold = get_dfs_bypass_threshold,
-+	.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
-+	.get_min_clocks_state = get_min_clocks_state,
-+	.get_required_clocks_state = get_required_clocks_state,
-+	.get_validation_clock = get_validation_clock,
-+	.set_clock = set_clock,
-+	.set_clock_state = set_clock_state,
-+	.set_dp_ref_clock_source = NULL,
-+	.set_min_clocks_state = set_min_clocks_state,
-+	.store_max_clocks_state = store_max_clocks_state,
-+	.validate = NULL,
-+};
-+
-+static bool dal_display_clock_dce110_construct(
-+	struct display_clock_dce110 *dc110,
-+	struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct display_clock *dc_base = &dc110->disp_clk_base;
-+
-+	if (NULL == as)
-+		return false;
-+
-+	if (!dal_display_clock_construct_base(dc_base, ctx, as))
-+		return false;
-+
-+	dc_base->funcs = &funcs;
-+
-+	dc110->dfs_bypass_disp_clk = 0;
-+
-+	if (!display_clock_integrated_info_construct(dc110, as))
-+		dal_logger_write(dc_base->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Cannot obtain VBIOS integrated info\n");
-+
-+	dc110->gpu_pll_ss_percentage = 0;
-+	dc110->gpu_pll_ss_divider = 1000;
-+	dc110->ss_on_gpu_pll = false;
-+
-+	dc_base->id = CLOCK_SOURCE_ID_DFS;
-+/* Initially set max clocks state to nominal.  This should be updated by
-+ * via a pplib call to DAL IRI eventually calling a
-+ * DisplayEngineClock_Dce110::StoreMaxClocksState().  This call will come in
-+ * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-+	dc110->max_clks_state = CLOCKS_STATE_NOMINAL;
-+
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_01],
-+		DIVIDER_RANGE_01_START,
-+		DIVIDER_RANGE_01_STEP_SIZE,
-+		DIVIDER_RANGE_01_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID);
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_02],
-+		DIVIDER_RANGE_02_START,
-+		DIVIDER_RANGE_02_STEP_SIZE,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID);
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_03],
-+		DIVIDER_RANGE_03_START,
-+		DIVIDER_RANGE_03_STEP_SIZE,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_MAX_DIVIDER_ID);
-+
-+	{
-+		uint32_t ss_info_num =
-+			dal_adapter_service_get_ss_info_num(
-+				as,
-+				AS_SIGNAL_TYPE_GPU_PLL);
-+
-+		if (ss_info_num) {
-+			struct spread_spectrum_info info;
-+			bool result;
-+
-+			dc_service_memset(&info, 0, sizeof(info));
-+
-+			result =
-+				dal_adapter_service_get_ss_info(
-+					as,
-+					AS_SIGNAL_TYPE_GPU_PLL,
-+					0,
-+					&info);
-+
-+			/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
-+			 * even if SS not enabled and in that case
-+			 * SSInfo.spreadSpectrumPercentage !=0 would be sign
-+			 * that SS is enabled
-+			 */
-+			if (result && info.spread_spectrum_percentage != 0) {
-+				dc110->ss_on_gpu_pll = true;
-+				dc110->gpu_pll_ss_divider =
-+					info.spread_percentage_divider;
-+
-+				if (info.type.CENTER_MODE == 0) {
-+					/* Currently for DP Reference clock we
-+					 * need only SS percentage for
-+					 * downspread */
-+					dc110->gpu_pll_ss_percentage =
-+						info.spread_spectrum_percentage;
-+				}
-+			}
-+
-+		}
-+	}
-+
-+	return true;
-+}
-+
-+/*****************************************************************************
-+ * public functions
-+ *****************************************************************************/
-+
-+struct display_clock *dal_display_clock_dce110_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct display_clock_dce110 *dc110;
-+
-+	dc110 = dc_service_alloc(ctx, sizeof(struct display_clock_dce110));
-+
-+	if (dc110 == NULL)
-+		return NULL;
-+
-+	if (dal_display_clock_dce110_construct(dc110, ctx, as))
-+		return &dc110->disp_clk_base;
-+
-+	dc_service_free(ctx, dc110);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h
-new file mode 100644
-index 0000000..0cdc7b5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DISPLAY_CLOCK_DCE110_H__
-+#define __DAL_DISPLAY_CLOCK_DCE110_H__
-+
-+#include "gpu/display_clock.h"
-+
-+struct display_clock_dce110 {
-+	struct display_clock disp_clk_base;
-+	/* Max display block clocks state*/
-+	enum clocks_state max_clks_state;
-+	bool use_max_disp_clk;
-+	uint32_t dentist_vco_freq_khz;
-+	/* Cache the status of DFS-bypass feature*/
-+	bool dfs_bypass_enabled;
-+	/* GPU PLL SS percentage (if down-spread enabled) */
-+	uint32_t gpu_pll_ss_percentage;
-+	/* GPU PLL SS percentage Divider (100 or 1000) */
-+	uint32_t gpu_pll_ss_divider;
-+	/* Flag for Enabled SS on GPU PLL */
-+	bool ss_on_gpu_pll;
-+	/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
-+	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
-+	uint32_t dfs_bypass_disp_clk;
-+	struct display_clock_state clock_state;
-+};
-+
-+#define DCLCK110_FROM_BASE(dc_base) \
-+	container_of(dc_base, struct display_clock_dce110, disp_clk_base)
-+
-+#endif /* __DAL_DISPLAY_CLOCK_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-new file mode 100644
-index 0000000..7fd5984
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-@@ -0,0 +1,383 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/adapter_service_interface.h"
-+#include "include/fixed32_32.h"
-+
-+#include "ext_clock_source_dce110.h"
-+
-+/**
-+ * In this file ECS stands for External Clock Source.
-+ */
-+
-+#define ECS110_FROM_BASE(clk_src_ptr)\
-+	container_of(\
-+		container_of((clk_src_ptr), struct ext_clock_source, base), \
-+			struct ext_clock_source_dce110, base)
-+
-+#define ECS_WARNING(...) \
-+	dal_logger_write(ctx->logger, LOG_MAJOR_WARNING, \
-+			LOG_MINOR_COMPONENT_GPU, __VA_ARGS__)
-+
-+#define ECS_ERROR(...) \
-+	dal_logger_write(ctx->logger, LOG_MAJOR_ERROR, \
-+			LOG_MINOR_COMPONENT_GPU, __VA_ARGS__)
-+
-+/******************************************************************************
-+ * implementation functions
-+ *****************************************************************************/
-+
-+static uint32_t controller_id_to_index(
-+		struct clock_source *clk_src,
-+		enum controller_id controller_id)
-+{
-+	struct dc_context *ctx = clk_src->ctx;
-+	uint32_t index = 0;
-+
-+	switch (controller_id) {
-+	case CONTROLLER_ID_D0:
-+		index = 0;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		index = 1;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		index = 2;
-+		break;
-+	default:
-+		ECS_ERROR("%s: invalid input controller_id = %d!\n",
-+				__func__, controller_id);
-+		break;
-+	}
-+
-+	return index;
-+}
-+
-+/* Adjust pixel rate by DTO programming (used for DisplayPort) */
-+static bool adjust_dto_pixel_rate(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		uint32_t requested_pix_clk_hz)
-+{
-+	struct ext_clock_source_dce110 *ecs110 =
-+			ECS110_FROM_BASE(clk_src);
-+	struct dc_context *ctx = clk_src->ctx;
-+	uint32_t index;
-+	uint32_t dto_phase_reg;
-+	uint32_t dto_modulo_reg;
-+	uint32_t dto_phase_rnd;
-+	uint32_t addr;
-+	uint32_t value;
-+	struct fixed32_32 dto_phase;
-+
-+	if (NULL == pix_clk_params) {
-+		ECS_WARNING("%s: invalid input!\n", __func__);
-+		return false;
-+	}
-+
-+	index = controller_id_to_index(clk_src, pix_clk_params->controller_id);
-+
-+	addr = ecs110->registers[index].dp_dtox_phase;
-+	dto_phase_reg = dal_read_reg(ctx, addr);
-+
-+	addr = ecs110->registers[index].dp_dtox_modulo;
-+	dto_modulo_reg = dal_read_reg(ctx, addr);
-+
-+	if (!dto_modulo_reg) {
-+		ECS_WARNING("%s: current modulo is zero!\n", __func__);
-+		return false;
-+	}
-+
-+	dto_phase = dal_fixed32_32_from_int(requested_pix_clk_hz);
-+
-+	dto_phase = dal_fixed32_32_mul_int(dto_phase, dto_modulo_reg);
-+
-+	dto_phase = dal_fixed32_32_div_int(dto_phase,
-+			pix_clk_params->dp_ref_clk * 1000);
-+
-+	dto_phase_rnd = dal_fixed32_32_round(dto_phase);
-+
-+	/* Program DTO Phase */
-+	if (dto_phase_reg != dto_phase_rnd) {
-+		/* If HW De-Spreading enabled on DP REF clock and if there will
-+		 * be case when Pixel rate > average DP Ref Clock, then need to
-+		 * disable de-spread for DP DTO (ATOMBIOS will program MODULO
-+		 * for average DP REF clock so no further SW adjustment
-+		 * needed) */
-+		if (pix_clk_params->de_spread_params.hw_dso_n_dp_ref_clk) {
-+
-+			addr = ecs110->registers[index].crtcx_pixel_rate_cntl;
-+			value = dal_read_reg(ctx, addr);
-+
-+			if (requested_pix_clk_hz / 1000 >
-+				pix_clk_params->
-+					de_spread_params.avg_dp_ref_clk_khz) {
-+
-+				set_reg_field_value(value, 1,
-+						CRTC0_PIXEL_RATE_CNTL,
-+						DP_DTO0_DS_DISABLE);
-+			} else {
-+				set_reg_field_value(value, 0,
-+						CRTC0_PIXEL_RATE_CNTL,
-+						DP_DTO0_DS_DISABLE);
-+			}
-+
-+			dal_write_reg(ctx, addr, value);
-+		}
-+
-+		value = 0;
-+		addr = ecs110->registers[index].dp_dtox_phase;
-+
-+		set_reg_field_value(value, dto_phase_rnd,
-+				DP_DTO0_PHASE,
-+				DP_DTO0_PHASE);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ * Retrieve Pixel Rate (in Hz) from HW registers already programmed.
-+ */
-+uint32_t retrieve_dp_pixel_rate_from_display_pll(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *params)
-+{
-+	struct dc_context *ctx = clk_src->ctx;
-+
-+	/* TODO: update when DAL2 implements  this function. */
-+	DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_GPU, "%s\n", __func__);
-+	return 0;
-+}
-+
-+static uint32_t retrieve_dto_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *params)
-+{
-+	struct ext_clock_source_dce110 *ecs110 =
-+			ECS110_FROM_BASE(clk_src);
-+	struct dc_context *ctx = clk_src->ctx;
-+	uint32_t index;
-+	uint32_t dto_phase_reg;
-+	uint32_t dto_modulo_reg;
-+	uint32_t addr;
-+	uint32_t value;
-+	uint32_t pix_rate_hz;
-+	struct fixed32_32 p_clk;
-+
-+	if (params == NULL)
-+		return 0;
-+
-+	if (NULL == params) {
-+		ECS_WARNING("%s: invalid input!\n", __func__);
-+		return false;
-+	}
-+
-+	index = controller_id_to_index(clk_src, params->controller_id);
-+
-+	addr = ecs110->registers[index].crtcx_pixel_rate_cntl;
-+	value = dal_read_reg(ctx, addr);
-+
-+	if (get_reg_field_value(value, CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE)
-+			== 1) {
-+
-+		addr = ecs110->registers[index].dp_dtox_phase;
-+		dto_phase_reg = dal_read_reg(ctx, addr);
-+
-+		addr = ecs110->registers[index].dp_dtox_modulo;
-+		dto_modulo_reg = dal_read_reg(ctx, addr);
-+
-+		if (!dto_modulo_reg) {
-+			ECS_WARNING("%s: current modulo is zero!\n", __func__);
-+			return 0;
-+		}
-+
-+		/* Calculate pixel clock from DTO Phase & Modulo*/
-+		p_clk = dal_fixed32_32_from_int(params->dp_ref_clk * 1000);
-+
-+		p_clk = dal_fixed32_32_mul_int(p_clk, dto_phase_reg);
-+
-+		p_clk = dal_fixed32_32_div_int(p_clk, dto_modulo_reg);
-+
-+		pix_rate_hz = dal_fixed32_32_round(p_clk);
-+	} else {
-+		pix_rate_hz = retrieve_dp_pixel_rate_from_display_pll(clk_src,
-+				params);
-+	}
-+
-+	return pix_rate_hz;
-+}
-+
-+/******************************************************************************
-+ * create/destroy functions
-+ *****************************************************************************/
-+
-+static void destruct(struct ext_clock_source_dce110 *ecs110)
-+{
-+	struct ext_clock_source *ext_cs = &ecs110->base;
-+	struct clock_source *base = &ext_cs->base;
-+
-+	if (NULL != base->dp_ss_params) {
-+		dc_service_free(base->ctx, base->dp_ss_params);
-+		base->dp_ss_params = NULL;
-+	}
-+
-+	dc_service_free(base->ctx, ecs110->registers);
-+	ecs110->registers = NULL;
-+}
-+
-+
-+static void destroy(struct clock_source **clk_src)
-+{
-+	struct ext_clock_source_dce110 *ecs110;
-+
-+	ecs110 = ECS110_FROM_BASE(*clk_src);
-+
-+	destruct(ecs110);
-+
-+	dc_service_free((*clk_src)->ctx, ecs110);
-+
-+	*clk_src = NULL;
-+}
-+
-+static const struct clock_source_impl funcs = {
-+	.program_pix_clk = dal_ext_clock_source_program_pix_clk,
-+	.adjust_pll_pixel_rate = dal_clock_source_base_adjust_pll_pixel_rate,
-+	.adjust_dto_pixel_rate = adjust_dto_pixel_rate,
-+	.retrieve_pll_pix_rate_hz =
-+			dal_clock_source_base_retrieve_pll_pix_rate_hz,
-+	.get_pix_clk_dividers = dal_ext_clock_source_get_pix_clk_dividers,
-+	.destroy = destroy,
-+	.retrieve_dto_pix_rate_hz = retrieve_dto_pix_rate_hz,
-+	.power_down_pll = dal_ext_clock_source_power_down_pll
-+};
-+
-+static bool construct(
-+		struct ext_clock_source_dce110 *ecs110,
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	struct dc_context *ctx = clk_src_init_data->ctx;
-+	struct ext_clock_source *ext_cs = &ecs110->base;
-+	struct clock_source *base = &ext_cs->base;
-+	uint32_t controllers_num;
-+	struct registers *registers;
-+
-+	/* None of the base construct() functions allocates memory.
-+	 * That means, in case of error, we don't have to free memory
-+	 * allocated by base. */
-+	if (!dal_ext_clock_source_construct(ext_cs, clk_src_init_data))
-+		return false;
-+
-+	base->funcs = &funcs;
-+
-+	base->is_gen_lock_capable = false;
-+	base->dp_ss_params = NULL;
-+	base->dp_ss_params_cnt = 0;
-+
-+	ecs110->registers = NULL;
-+
-+	if (base->clk_src_id != CLOCK_SOURCE_ID_EXTERNAL) {
-+		ECS_ERROR("ECS110:Invalid ClockSourceId = %d!\n",
-+				base->clk_src_id);
-+		return false;
-+	}
-+
-+	controllers_num = dal_adapter_service_get_controllers_num(
-+			base->adapter_service);
-+
-+	if (controllers_num <= 0 || controllers_num > 3) {
-+		ECS_ERROR("ECS110:Invalid number of controllers = %d!\n",
-+				controllers_num);
-+		return false;
-+	}
-+
-+	ecs110->registers = (struct registers *)
-+		(dc_service_alloc(clk_src_init_data->ctx, sizeof(struct registers) * controllers_num));
-+
-+	if (ecs110->registers == NULL) {
-+		ECS_ERROR("ECS110:Failed to allocate 'registers'!\n");
-+		return false;
-+	}
-+
-+	registers = ecs110->registers;
-+
-+	/* Assign register address. No break between cases */
-+	switch (controllers_num) {
-+	case 3:
-+		registers[2].dp_dtox_phase = mmDP_DTO2_PHASE;
-+		registers[2].dp_dtox_modulo = mmDP_DTO2_MODULO;
-+		registers[2].crtcx_pixel_rate_cntl = mmCRTC2_PIXEL_RATE_CNTL;
-+		/* fallthrough */
-+	case 2:
-+		registers[1].dp_dtox_phase = mmDP_DTO1_PHASE;
-+		registers[1].dp_dtox_modulo = mmDP_DTO1_MODULO;
-+		registers[1].crtcx_pixel_rate_cntl = mmCRTC1_PIXEL_RATE_CNTL;
-+		/* fallthrough */
-+	case 1:
-+		registers[0].dp_dtox_phase = mmDP_DTO0_PHASE;
-+		registers[0].dp_dtox_modulo = mmDP_DTO0_MODULO;
-+		registers[0].crtcx_pixel_rate_cntl = mmCRTC0_PIXEL_RATE_CNTL;
-+		break;
-+
-+	default:
-+		/* We can not get here because we checked number of
-+		 * controllers already. */
-+		break;
-+	}
-+
-+	dal_clock_source_get_ss_info_from_atombios(
-+			base,
-+			AS_SIGNAL_TYPE_DISPLAY_PORT,
-+			&base->dp_ss_params,
-+			&base->dp_ss_params_cnt);
-+
-+	return true;
-+}
-+
-+
-+struct clock_source *dal_ext_clock_source_dce110_create(
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	struct ext_clock_source_dce110 *ecs110;
-+
-+	ecs110 = dc_service_alloc(clk_src_init_data->ctx, sizeof(struct ext_clock_source_dce110));
-+
-+	if (ecs110 == NULL)
-+		return NULL;
-+
-+	if (!construct(ecs110, clk_src_init_data)) {
-+		dc_service_free(clk_src_init_data->ctx, ecs110);
-+		return NULL;
-+	}
-+
-+	return &ecs110->base.base;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
-new file mode 100644
-index 0000000..4ea2ae2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
-@@ -0,0 +1,38 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_EXT_CLOCK_SOURCE_DCE110__
-+#define __DAL_EXT_CLOCK_SOURCE_DCE110__
-+
-+#include "../ext_clock_source.h"
-+
-+struct ext_clock_source_dce110 {
-+	struct ext_clock_source base;
-+	struct registers *registers;
-+};
-+
-+struct clock_source *dal_ext_clock_source_dce110_create(
-+		struct clock_source_init_data *clk_src_init_data);
-+
-+#endif /*__DAL_EXT_CLOCK_SOURCE_DCE110__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-new file mode 100644
-index 0000000..d83eea3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-@@ -0,0 +1,718 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/adapter_service_interface.h"
-+#include "include/fixed32_32.h"
-+#include "gpu/calc_pll_clock_source.h"
-+#include "gpu/clock_source.h"
-+#include "gpu/pll_clock_source.h"
-+
-+#include "gpu/dce110/pll_clock_source_dce110.h"
-+
-+enum fract_fb_divider_dec_points {
-+	FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM = 6,
-+	FRACT_FB_DIVIDER_DEC_POINTS_NO_DS_NUM = 1,
-+};
-+
-+#define FROM_CLK_SRC(clk_src_ptr)\
-+	container_of(\
-+		container_of((clk_src_ptr), struct pll_clock_source, base), \
-+			struct pll_clock_source_dce110, base)
-+
-+static bool calculate_ss(
-+		struct pll_clock_source_dce110 *clk_src,
-+		struct pll_settings *pll_settings,
-+		const struct spread_spectrum_data *ss_data,
-+		struct delta_sigma_data *ds_data)
-+{
-+	struct fixed32_32 fb_div;
-+	struct fixed32_32 ss_amount;
-+	struct fixed32_32 ss_nslip_amount;
-+	struct fixed32_32 ss_ds_frac_amount;
-+	struct fixed32_32 ss_step_size;
-+	struct fixed32_32 modulation_time;
-+
-+	if (ds_data == NULL)
-+		return false;
-+	if (ss_data == NULL)
-+		return false;
-+	if (ss_data->percentage == 0)
-+		return false;
-+	if (pll_settings == NULL)
-+		return false;
-+
-+
-+	dc_service_memset(ds_data, 0, sizeof(struct delta_sigma_data));
-+
-+
-+
-+	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
-+	/* 6 decimal point support in fractional feedback divider */
-+	fb_div  = dal_fixed32_32_from_fraction(
-+		pll_settings->fract_feedback_divider, 1000000);
-+	fb_div = dal_fixed32_32_add_int(fb_div, pll_settings->feedback_divider);
-+
-+	ds_data->ds_frac_amount = 0;
-+	/*spreadSpectrumPercentage is in the unit of .01%,
-+	 * so have to divided by 100 * 100*/
-+	ss_amount = dal_fixed32_32_mul(
-+		fb_div, dal_fixed32_32_from_fraction(ss_data->percentage,
-+					100 * ss_data->percentage_divider));
-+	ds_data->feedback_amount = dal_fixed32_32_floor(ss_amount);
-+
-+	ss_nslip_amount = dal_fixed32_32_sub(ss_amount,
-+		dal_fixed32_32_from_int(ds_data->feedback_amount));
-+	ss_nslip_amount = dal_fixed32_32_mul_int(ss_nslip_amount, 10);
-+	ds_data->nfrac_amount = dal_fixed32_32_floor(ss_nslip_amount);
-+
-+	ss_ds_frac_amount = dal_fixed32_32_sub(ss_nslip_amount,
-+		dal_fixed32_32_from_int(ds_data->nfrac_amount));
-+	ss_ds_frac_amount = dal_fixed32_32_mul_int(ss_ds_frac_amount, 65536);
-+	ds_data->ds_frac_amount = dal_fixed32_32_floor(ss_ds_frac_amount);
-+
-+	/* compute SS_STEP_SIZE_DSFRAC */
-+	modulation_time = dal_fixed32_32_from_fraction(
-+		pll_settings->reference_freq * 1000,
-+		pll_settings->reference_divider * ss_data->modulation_freq_hz);
-+
-+
-+	if (ss_data->flags.CENTER_SPREAD)
-+		modulation_time = dal_fixed32_32_div_int(modulation_time, 4);
-+	else
-+		modulation_time = dal_fixed32_32_div_int(modulation_time, 2);
-+
-+	ss_step_size = dal_fixed32_32_div(ss_amount, modulation_time);
-+	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
-+	ss_step_size = dal_fixed32_32_mul_int(ss_step_size, 65536 * 10);
-+	ds_data->ds_frac_size =  dal_fixed32_32_floor(ss_step_size);
-+
-+	return true;
-+}
-+
-+static bool disable_spread_spectrum(struct pll_clock_source_dce110 *clk_src)
-+{
-+	enum bp_result result;
-+	struct bp_spread_spectrum_parameters bp_ss_params = {0};
-+	struct clock_source *clock_source = NULL;
-+
-+	clock_source = &clk_src->base.base;
-+	bp_ss_params.pll_id = clock_source->clk_src_id;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	result = dal_bios_parser_enable_spread_spectrum_on_ppll(
-+			clock_source->bios_parser,
-+			&bp_ss_params,
-+			false);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+static bool enable_spread_spectrum(
-+		struct pll_clock_source_dce110 *clk_src,
-+		enum signal_type signal, struct pll_settings *pll_settings)
-+{
-+	struct bp_spread_spectrum_parameters bp_params = {0};
-+	struct delta_sigma_data d_s_data;
-+	struct clock_source *clock_source = NULL;
-+	const struct spread_spectrum_data *ss_data = NULL;
-+
-+	clock_source = &clk_src->base.base;
-+	ss_data = dal_clock_source_get_ss_data_entry(
-+			clock_source,
-+			signal,
-+			pll_settings->calculated_pix_clk);
-+
-+/* Pixel clock PLL has been programmed to generate desired pixel clock,
-+ * now enable SS on pixel clock */
-+/* TODO is it OK to return true not doing anything ??*/
-+	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
-+		if (calculate_ss(clk_src, pll_settings, ss_data, &d_s_data)) {
-+			bp_params.ds.feedback_amount =
-+					d_s_data.feedback_amount;
-+			bp_params.ds.nfrac_amount =
-+					d_s_data.nfrac_amount;
-+			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
-+			bp_params.ds_frac_amount =
-+					d_s_data.ds_frac_amount;
-+			bp_params.flags.DS_TYPE = 1;
-+			bp_params.pll_id = clock_source->clk_src_id;
-+			bp_params.percentage = ss_data->percentage;
-+			if (ss_data->flags.CENTER_SPREAD)
-+				bp_params.flags.CENTER_SPREAD = 1;
-+			if (ss_data->flags.EXTERNAL_SS)
-+				bp_params.flags.EXTERNAL_SS = 1;
-+
-+			if (BP_RESULT_OK !=
-+				dal_bios_parser_enable_spread_spectrum_on_ppll(
-+						clock_source->bios_parser,
-+						&bp_params,
-+						true))
-+				return false;
-+		} else
-+			return false;
-+	}
-+	return true;
-+}
-+
-+static void program_pixel_clk_resync(
-+		struct pll_clock_source_dce110 *clk_src,
-+		enum signal_type signal_type,
-+		enum dc_color_depth colordepth)
-+{
-+	struct clock_source *clock_source = NULL;
-+	uint32_t value = 0;
-+
-+	clock_source = &clk_src->base.base;
-+
-+	value = dal_read_reg(
-+		clock_source->ctx,
-+		clk_src->pixclkx_resync_cntl);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		PIXCLK1_RESYNC_CNTL,
-+		DCCG_DEEP_COLOR_CNTL1);
-+
-+	/*
-+	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
-+	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
-+	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
-+	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
-+	 */
-+	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return;
-+
-+	switch (colordepth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			0,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			1,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			2,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	case COLOR_DEPTH_161616:
-+		set_reg_field_value(
-+			value,
-+			3,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dal_write_reg(
-+		clock_source->ctx,
-+		clk_src->pixclkx_resync_cntl,
-+		value);
-+}
-+
-+static bool program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct pll_clock_source_dce110 *pll_clk_src_dce110 =
-+						FROM_CLK_SRC(clk_src);
-+	struct bp_pixel_clock_parameters bp_pc_params = {0};
-+
-+	/* First disable SS
-+	 * ATOMBIOS will enable by default SS on PLL for DP,
-+	 * do not disable it here
-+	 */
-+	if (!dc_is_dp_signal(pix_clk_params->signal_type))
-+		disable_spread_spectrum(pll_clk_src_dce110);
-+
-+	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
-+	bp_pc_params.controller_id = pix_clk_params->controller_id;
-+	bp_pc_params.pll_id = clk_src->clk_src_id;
-+	bp_pc_params.target_pixel_clock =
-+			pll_settings->actual_pix_clk;
-+	bp_pc_params.reference_divider = pll_settings->reference_divider;
-+	bp_pc_params.feedback_divider = pll_settings->feedback_divider;
-+	bp_pc_params.fractional_feedback_divider =
-+			pll_settings->fract_feedback_divider;
-+	bp_pc_params.pixel_clock_post_divider =
-+			pll_settings->pix_clk_post_divider;
-+	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_pc_params.signal_type = pix_clk_params->signal_type;
-+	bp_pc_params.dvo_config = pix_clk_params->dvo_cfg;
-+	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
-+					pll_settings->use_external_clk;
-+
-+	if (dal_bios_parser_set_pixel_clock(clk_src->bios_parser,
-+						&bp_pc_params) != BP_RESULT_OK)
-+		return false;
-+
-+/* Enable SS
-+ * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
-+ * based on HW display PLL team, SS control settings should be programmed
-+ * during PLL Reset, but they do not have effect
-+ * until SS_EN is asserted.*/
-+	if (pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal(
-+					pix_clk_params->signal_type))
-+		if (!enable_spread_spectrum(pll_clk_src_dce110,
-+						pix_clk_params->signal_type,
-+						pll_settings))
-+			return false;
-+
-+/* Resync deep color DTO */
-+	program_pixel_clk_resync(pll_clk_src_dce110,
-+				pix_clk_params->signal_type,
-+				pix_clk_params->color_depth);
-+
-+	return true;
-+}
-+
-+static void ss_info_from_atombios_destroy(
-+	struct pll_clock_source_dce110 *clk_src)
-+{
-+	struct clock_source *cs = &clk_src->base.base;
-+
-+	if (NULL != cs->ep_ss_params) {
-+		dc_service_free(cs->ctx, cs->ep_ss_params);
-+		cs->ep_ss_params = NULL;
-+	}
-+
-+	if (NULL != cs->dp_ss_params) {
-+		dc_service_free(cs->ctx, cs->dp_ss_params);
-+		cs->dp_ss_params = NULL;
-+	}
-+
-+	if (NULL != cs->hdmi_ss_params) {
-+		dc_service_free(cs->ctx, cs->hdmi_ss_params);
-+		cs->hdmi_ss_params = NULL;
-+	}
-+
-+	if (NULL != cs->dvi_ss_params) {
-+		dc_service_free(cs->ctx, cs->dvi_ss_params);
-+		cs->dvi_ss_params = NULL;
-+	}
-+}
-+
-+static void destruct(
-+	struct pll_clock_source_dce110 *pll_cs)
-+{
-+	ss_info_from_atombios_destroy(pll_cs);
-+
-+	if (NULL != pll_cs->registers) {
-+		dc_service_free(pll_cs->base.base.ctx, pll_cs->registers);
-+		pll_cs->registers = NULL;
-+	}
-+}
-+
-+static void destroy(struct clock_source **clk_src)
-+{
-+	struct pll_clock_source_dce110 *pll_clk_src;
-+
-+	pll_clk_src = FROM_CLK_SRC(*clk_src);
-+
-+	destruct(pll_clk_src);
-+	dc_service_free((*clk_src)->ctx, pll_clk_src);
-+
-+	*clk_src = NULL;
-+}
-+
-+/**
-+ * Calculate PLL Dividers for given Clock Value.
-+ * First will call VBIOS Adjust Exec table to check if requested Pixel clock
-+ * will be Adjusted based on usage.
-+ * Then it will calculate PLL Dividers for this Adjusted clock using preferred
-+ * method (Maximum VCO frequency).
-+ *
-+ * \return
-+ *     Calculation error in units of 0.01%
-+ */
-+static uint32_t get_pix_clk_dividers(
-+		struct clock_source *cs,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct pll_clock_source_dce110 *pll_cs_110 = FROM_CLK_SRC(cs);
-+	struct pll_clock_source *pll_base = &pll_cs_110->base;
-+	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	if (pix_clk_params == NULL || pll_settings == NULL
-+			|| pix_clk_params->requested_pix_clk == 0) {
-+		dal_logger_write(cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid parameters!!\n", __func__);
-+		return pll_calc_error;
-+	}
-+
-+	dc_service_memset(pll_settings, 0, sizeof(*pll_settings));
-+
-+	/* Check if reference clock is external (not pcie/xtalin)
-+	* HW Dce80 spec:
-+	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
-+	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
-+	addr = pll_cs_110->pxpll_cntl;
-+	value = dal_read_reg(cs->ctx, addr);
-+	field = get_reg_field_value(value, PLL_CNTL, PLL_REF_DIV_SRC);
-+	pll_settings->use_external_clk = (field > 1);
-+
-+	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
-+	 * (we do not care any more from SI for some older DP Sink which
-+	 * does not report SS support, no known issues) */
-+	if ((pix_clk_params->flags.ENABLE_SS) ||
-+			(dc_is_dp_signal(pix_clk_params->signal_type))) {
-+
-+		const struct spread_spectrum_data *ss_data =
-+				dal_clock_source_get_ss_data_entry(
-+					cs,
-+					pix_clk_params->signal_type,
-+					pll_settings->adjusted_pix_clk);
-+
-+		if (NULL != ss_data)
-+			pll_settings->ss_percentage = ss_data->percentage;
-+	}
-+
-+	/* Check VBIOS AdjustPixelClock Exec table */
-+	if (!dal_pll_clock_source_adjust_pix_clk(pll_base,
-+			pix_clk_params, pll_settings)) {
-+		/* Should never happen, ASSERT and fill up values to be able
-+		 * to continue. */
-+		dal_logger_write(cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Failed to adjust pixel clock!!", __func__);
-+		pll_settings->actual_pix_clk =
-+				pix_clk_params->requested_pix_clk;
-+		pll_settings->adjusted_pix_clk =
-+				pix_clk_params->requested_pix_clk;
-+
-+		if (dc_is_dp_signal(pix_clk_params->signal_type))
-+			pll_settings->adjusted_pix_clk = 100000;
-+	}
-+
-+	/* Calculate Dividers */
-+	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
-+		/*Calculate Dividers by HDMI object, no SS case or SS case */
-+		pll_calc_error =
-+			dal_clock_source_calculate_pixel_clock_pll_dividers(
-+					&pll_cs_110->calc_pll_clock_source_hdmi,
-+					pll_settings);
-+	else
-+		/*Calculate Dividers by default object, no SS case or SS case */
-+		pll_calc_error =
-+			dal_clock_source_calculate_pixel_clock_pll_dividers(
-+					&pll_cs_110->calc_pll_clock_source,
-+					pll_settings);
-+
-+	return pll_calc_error;
-+}
-+
-+static const struct clock_source_impl funcs = {
-+	.program_pix_clk = program_pix_clk,
-+	.adjust_pll_pixel_rate = NULL,
-+	.adjust_dto_pixel_rate = NULL,
-+	.retrieve_pll_pix_rate_hz = NULL,
-+	.get_pix_clk_dividers = get_pix_clk_dividers,
-+	.destroy = destroy,
-+	.retrieve_dto_pix_rate_hz = NULL,
-+	.power_down_pll = dal_pll_clock_source_power_down_pll,
-+};
-+
-+static void ss_info_from_atombios_create(
-+	struct pll_clock_source_dce110 *clk_src)
-+{
-+	struct clock_source *base = &clk_src->base.base;
-+
-+	dal_clock_source_get_ss_info_from_atombios(
-+		base,
-+		AS_SIGNAL_TYPE_DISPLAY_PORT,
-+		&base->dp_ss_params,
-+		&base->dp_ss_params_cnt);
-+	dal_clock_source_get_ss_info_from_atombios(
-+		base,
-+		AS_SIGNAL_TYPE_LVDS,
-+		&base->ep_ss_params,
-+		&base->ep_ss_params_cnt);
-+	dal_clock_source_get_ss_info_from_atombios(
-+		base,
-+		AS_SIGNAL_TYPE_HDMI,
-+		&base->hdmi_ss_params,
-+		&base->hdmi_ss_params_cnt);
-+	dal_clock_source_get_ss_info_from_atombios(
-+		base,
-+		AS_SIGNAL_TYPE_DVI,
-+		&base->dvi_ss_params,
-+		&base->dvi_ss_params_cnt);
-+}
-+
-+
-+static bool construct(
-+		struct pll_clock_source_dce110 *pll_cs_dce110,
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	uint32_t controllers_num = 1;
-+
-+/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
-+	struct calc_pll_clock_source_init_data calc_pll_cs_init_data = {
-+		dal_adapter_service_get_bios_parser(clk_src_init_data->as),
-+		1, /* minPixelClockPLLPostDivider */
-+		PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK,
-+		/* maxPixelClockPLLPostDivider*/
-+		1,/* minPLLRefDivider*/
-+		PLL_REF_DIV__PLL_REF_DIV_MASK,/* maxPLLRefDivider*/
-+		0,
-+/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		0,
-+/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+/*numberOfFractFBDividerDecimalPoints*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+/*number of decimal point to round off for fractional feedback divider value*/
-+		clk_src_init_data->ctx
-+	};
-+/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
-+	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi = {
-+		dal_adapter_service_get_bios_parser(clk_src_init_data->as),
-+		1, /* minPixelClockPLLPostDivider */
-+		PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK,
-+		/* maxPixelClockPLLPostDivider*/
-+		1,/* minPLLRefDivider*/
-+		PLL_REF_DIV__PLL_REF_DIV_MASK,/* maxPLLRefDivider*/
-+		13500,
-+	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		27000,
-+	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+		/*numberOfFractFBDividerDecimalPoints*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+/*number of decimal point to round off for fractional feedback divider value*/
-+		clk_src_init_data->ctx
-+	};
-+
-+	struct pll_clock_source *base = &pll_cs_dce110->base;
-+	struct clock_source *superbase = &base->base;
-+
-+	if (!dal_pll_clock_source_construct(base, clk_src_init_data)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	superbase->funcs = &funcs;
-+
-+	superbase->is_clock_source_with_fixed_freq = false;
-+	superbase->clk_sharing_lvl = CLOCK_SHARING_LEVEL_DISPLAY_PORT_SHAREABLE;
-+
-+	pll_cs_dce110->registers = NULL;
-+
-+/* PLL3 should not be used although it is available in online register spec */
-+	if ((superbase->clk_src_id != CLOCK_SOURCE_ID_PLL1)
-+		&& (superbase->clk_src_id != CLOCK_SOURCE_ID_PLL0)) {
-+
-+
-+		ASSERT_CRITICAL(false);
-+		goto failure;
-+	}
-+
-+/* From Driver side PLL0 is now used for non DP timing also,
-+ * so it supports all signals except Wireless.
-+ * Wireless signal type does not require a PLL clock source,
-+ * so we will not waste a clock on it.
-+*/
-+	superbase->output_signals &= ~SIGNAL_TYPE_WIRELESS;
-+
-+	if (!dal_calc_pll_clock_source_max_vco_init(
-+		&pll_cs_dce110->calc_pll_clock_source,
-+		&calc_pll_cs_init_data)) {
-+		ASSERT_CRITICAL(false);
-+		goto failure;
-+	}
-+
-+	if (base->ref_freq_khz == 48000) {
-+		calc_pll_cs_init_data_hdmi.
-+			min_override_input_pxl_clk_pll_freq_khz = 24000;
-+		calc_pll_cs_init_data_hdmi.
-+			max_override_input_pxl_clk_pll_freq_khz = 48000;
-+	} else if (base->ref_freq_khz == 100000) {
-+		calc_pll_cs_init_data_hdmi.
-+			min_override_input_pxl_clk_pll_freq_khz = 25000;
-+		calc_pll_cs_init_data_hdmi.
-+			max_override_input_pxl_clk_pll_freq_khz = 50000;
-+	}
-+
-+	if (!dal_calc_pll_clock_source_max_vco_init(
-+			&pll_cs_dce110->calc_pll_clock_source_hdmi,
-+			&calc_pll_cs_init_data_hdmi)) {
-+		ASSERT_CRITICAL(false);
-+		goto failure;
-+	}
-+
-+	switch (superbase->clk_src_id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		pll_cs_dce110->pixclkx_resync_cntl = mmPIXCLK0_RESYNC_CNTL;
-+		pll_cs_dce110->ppll_fb_div = mmBPHYC_PLL0_PLL_FB_DIV;
-+		pll_cs_dce110->ppll_ref_div = mmBPHYC_PLL0_PLL_REF_DIV;
-+		pll_cs_dce110->ppll_post_div = mmBPHYC_PLL0_PLL_POST_DIV;
-+		pll_cs_dce110->pxpll_ds_cntl = mmBPHYC_PLL0_PLL_DS_CNTL;
-+		pll_cs_dce110->pxpll_ss_cntl = mmBPHYC_PLL0_PLL_SS_CNTL;
-+		pll_cs_dce110->pxpll_ss_dsfrac =
-+				mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC;
-+		pll_cs_dce110->pxpll_cntl = mmBPHYC_PLL0_PLL_CNTL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		pll_cs_dce110->pixclkx_resync_cntl = mmPIXCLK1_RESYNC_CNTL;
-+		pll_cs_dce110->ppll_fb_div = mmBPHYC_PLL1_PLL_FB_DIV;
-+		pll_cs_dce110->ppll_ref_div = mmBPHYC_PLL1_PLL_REF_DIV;
-+		pll_cs_dce110->ppll_post_div = mmBPHYC_PLL1_PLL_POST_DIV;
-+		pll_cs_dce110->pxpll_ds_cntl = mmBPHYC_PLL1_PLL_DS_CNTL;
-+		pll_cs_dce110->pxpll_ss_cntl = mmBPHYC_PLL1_PLL_SS_CNTL;
-+		pll_cs_dce110->pxpll_ss_dsfrac =
-+				mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC;
-+		pll_cs_dce110->pxpll_cntl = mmBPHYC_PLL1_PLL_CNTL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+	/* PLL2 is not supported */
-+	default:
-+		break;
-+	}
-+
-+	controllers_num = dal_adapter_service_get_controllers_num(
-+		superbase->adapter_service);
-+
-+	pll_cs_dce110->registers = dc_service_alloc(
-+		clk_src_init_data->ctx,
-+		sizeof(struct registers) * controllers_num);
-+
-+	if (pll_cs_dce110->registers == NULL) {
-+		ASSERT_CRITICAL(false);
-+		goto failure;
-+	}
-+
-+	/* Assign register address. No break between cases */
-+	switch (controllers_num) {
-+	case 6:
-+		pll_cs_dce110->registers[5].dp_dtox_phase =
-+				mmDP_DTO5_PHASE;
-+		pll_cs_dce110->registers[5].dp_dtox_modulo =
-+				mmDP_DTO5_MODULO;
-+		pll_cs_dce110->registers[5].crtcx_pixel_rate_cntl =
-+				mmCRTC5_PIXEL_RATE_CNTL;
-+		/* fall through*/
-+
-+	case 5:
-+		pll_cs_dce110->registers[4].dp_dtox_phase =
-+				mmDP_DTO4_PHASE;
-+		pll_cs_dce110->registers[4].dp_dtox_modulo =
-+				mmDP_DTO4_MODULO;
-+		pll_cs_dce110->registers[4].crtcx_pixel_rate_cntl =
-+				mmCRTC4_PIXEL_RATE_CNTL;
-+		/* fall through*/
-+
-+	case 4:
-+		pll_cs_dce110->registers[3].dp_dtox_phase =
-+				mmDP_DTO3_PHASE;
-+		pll_cs_dce110->registers[3].dp_dtox_modulo =
-+				mmDP_DTO3_MODULO;
-+		pll_cs_dce110->registers[3].crtcx_pixel_rate_cntl =
-+				mmCRTC3_PIXEL_RATE_CNTL;
-+		/* fall through*/
-+
-+	case 3:
-+		pll_cs_dce110->registers[2].dp_dtox_phase =
-+				mmDP_DTO2_PHASE;
-+		pll_cs_dce110->registers[2].dp_dtox_modulo =
-+				mmDP_DTO2_MODULO;
-+		pll_cs_dce110->registers[2].crtcx_pixel_rate_cntl =
-+				mmCRTC2_PIXEL_RATE_CNTL;
-+		/* fall through*/
-+
-+	case 2:
-+		pll_cs_dce110->registers[1].dp_dtox_phase =
-+				mmDP_DTO1_PHASE;
-+		pll_cs_dce110->registers[1].dp_dtox_modulo =
-+				mmDP_DTO1_MODULO;
-+		pll_cs_dce110->registers[1].crtcx_pixel_rate_cntl =
-+				mmCRTC1_PIXEL_RATE_CNTL;
-+		/* fall through*/
-+
-+	case 1:
-+		pll_cs_dce110->registers[0].dp_dtox_phase =
-+				mmDP_DTO0_PHASE;
-+		pll_cs_dce110->registers[0].dp_dtox_modulo =
-+				mmDP_DTO0_MODULO;
-+		pll_cs_dce110->registers[0].crtcx_pixel_rate_cntl =
-+				mmCRTC0_PIXEL_RATE_CNTL;
-+
-+		break;
-+
-+	default:
-+		ASSERT_CRITICAL(false);
-+		goto failure;
-+	}
-+
-+	ss_info_from_atombios_create(pll_cs_dce110);
-+
-+	return true;
-+
-+failure:
-+	destruct(pll_cs_dce110);
-+
-+	return false;
-+}
-+
-+struct clock_source *dal_pll_clock_source_dce110_create(
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	struct pll_clock_source_dce110 *clk_src =
-+		dc_service_alloc(clk_src_init_data->ctx, sizeof(struct pll_clock_source_dce110));
-+
-+	if (clk_src == NULL)
-+		return NULL;
-+
-+	if (!construct(clk_src, clk_src_init_data)) {
-+		dc_service_free(clk_src_init_data->ctx, clk_src);
-+		return NULL;
-+	}
-+	return &(clk_src->base.base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
-new file mode 100644
-index 0000000..166b29a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
-@@ -0,0 +1,55 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_PLL_CLOCK_SOURCE_DCE110_H__
-+#define __DAL_PLL_CLOCK_SOURCE_DCE110_H__
-+
-+#include "../pll_clock_source.h"
-+#include "../calc_pll_clock_source.h"
-+
-+struct pll_clock_source_dce110 {
-+	struct pll_clock_source base;
-+
-+	struct calc_pll_clock_source calc_pll_clock_source;
-+/* object for normal circumstances, SS = 0 or SS >= 0.2% (LVDS or DP)
-+ * or even for SS =~0.02 (DVI) */
-+
-+	struct calc_pll_clock_source calc_pll_clock_source_hdmi;
-+/* object for HDMI no SS or SS <= 0.06% */
-+
-+	struct registers *registers;
-+
-+	uint32_t pixclkx_resync_cntl;
-+	uint32_t ppll_fb_div;
-+	uint32_t ppll_ref_div;
-+	uint32_t ppll_post_div;
-+	uint32_t pxpll_ds_cntl;
-+	uint32_t pxpll_ss_cntl;
-+	uint32_t pxpll_ss_dsfrac;
-+	uint32_t pxpll_cntl;
-+};
-+
-+struct clock_source *dal_pll_clock_source_dce110_create(
-+		struct clock_source_init_data *clk_src_init_data);
-+
-+#endif /*__DAL_PLL_CLOCK_SOURCE_DCE110__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-new file mode 100644
-index 0000000..ce59228
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-@@ -0,0 +1,193 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dal_services.h"
-+#include "vce_clock_source_dce110.h"
-+#include "include/clock_source_types.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/logger_interface.h"
-+
-+struct vce_clock_source_dce110 {
-+	struct clock_source base;
-+	uint32_t ref_freq_khz;
-+};
-+
-+static uint32_t get_pix_clk_dividers(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct vce_clock_source_dce110 *vce_clk_src_dce110 =
-+			container_of(
-+					clk_src,
-+					struct vce_clock_source_dce110,
-+					base);
-+	if (pix_clk_params == NULL ||
-+			pll_settings == NULL ||
-+			pix_clk_params->requested_pix_clk == 0) {
-+		dal_logger_write(clk_src->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid parameters!!", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+	dc_service_memset(pll_settings, 0, sizeof(struct pll_settings));
-+	pll_settings->reference_freq = vce_clk_src_dce110->ref_freq_khz;
-+	pll_settings->actual_pix_clk =
-+			pix_clk_params->requested_pix_clk;
-+	pll_settings->adjusted_pix_clk =
-+			pix_clk_params->requested_pix_clk;
-+	pll_settings->calculated_pix_clk =
-+			pix_clk_params->requested_pix_clk;
-+
-+	return 0;
-+}
-+static bool program_pix_clk(struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct bp_pixel_clock_parameters bp_pix_clk_params = { 0 };
-+
-+	if (pll_settings->actual_pix_clk == 0)
-+		return false;
-+	/* this is SimNow for Nutmeg*/
-+
-+	bp_pix_clk_params.controller_id = pix_clk_params->controller_id;
-+	bp_pix_clk_params.pll_id = clk_src->clk_src_id;
-+	bp_pix_clk_params.target_pixel_clock = pll_settings->actual_pix_clk;
-+	bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
-+
-+	if (dal_bios_parser_set_pixel_clock(clk_src->bios_parser,
-+			&bp_pix_clk_params) == BP_RESULT_OK)
-+		return true;
-+
-+	return false;
-+}
-+
-+static bool power_down_pll(struct clock_source *clk_src,
-+		enum controller_id controller_id)
-+{
-+	return true;
-+}
-+
-+static void destruct(
-+	struct vce_clock_source_dce110 *vce_clk_src)
-+{
-+
-+}
-+
-+static void destroy(
-+	struct clock_source **clk_src)
-+{
-+	struct vce_clock_source_dce110 *vce_clk_src;
-+
-+	vce_clk_src =
-+		container_of(*clk_src, struct vce_clock_source_dce110, base);
-+
-+	destruct(vce_clk_src);
-+	dc_service_free((*clk_src)->ctx, vce_clk_src);
-+
-+	*clk_src = NULL;
-+}
-+
-+static const struct clock_source_impl funcs = {
-+	.program_pix_clk = program_pix_clk,
-+	.adjust_pll_pixel_rate = dal_clock_source_base_adjust_pll_pixel_rate,
-+	.adjust_dto_pixel_rate = dal_clock_source_base_adjust_dto_pix_rate,
-+	.retrieve_pll_pix_rate_hz =
-+		dal_clock_source_base_retrieve_pll_pix_rate_hz,
-+	.get_pix_clk_dividers = get_pix_clk_dividers,
-+	.destroy = destroy,
-+	.retrieve_dto_pix_rate_hz =
-+		dal_clock_source_base_retrieve_dto_pix_rate_hz,
-+	.power_down_pll = power_down_pll,
-+};
-+
-+static bool construct(
-+			struct vce_clock_source_dce110 *vce_clk_src,
-+			struct clock_source_init_data *clk_src_init_data)
-+{
-+	struct firmware_info fw_info = { { 0 } };
-+
-+	if (!dal_clock_source_construct(
-+		&vce_clk_src->base, clk_src_init_data)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if (vce_clk_src->base.clk_src_id != CLOCK_SOURCE_ID_VCE) {
-+		dal_logger_write(clk_src_init_data->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Invalid ClockSourceId = %d!\n",
-+			vce_clk_src->base.clk_src_id);
-+		ASSERT_CRITICAL(false);
-+		dal_logger_write(clk_src_init_data->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Failed to create DCE110VceClockSource.\n");
-+		return false;
-+	}
-+
-+	vce_clk_src->base.funcs = &funcs;
-+	vce_clk_src->base.clk_sharing_lvl = CLOCK_SHARING_LEVEL_NOT_SHAREABLE;
-+	vce_clk_src->base.is_clock_source_with_fixed_freq = false;
-+
-+
-+	/*VCE clock source only supports SignalType_Wireless*/
-+	vce_clk_src->base.output_signals |= SIGNAL_TYPE_WIRELESS;
-+
-+	/*Get Reference frequency, Input frequency range into PLL
-+	 * and Output frequency range of the PLL
-+	 * from ATOMBIOS Data table */
-+	if (dal_bios_parser_get_firmware_info(
-+			vce_clk_src->base.bios_parser,
-+			&fw_info) != BP_RESULT_OK)
-+		return false;
-+
-+	vce_clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+
-+	return true;
-+}
-+
-+
-+struct clock_source *dal_vce_clock_source_dce110_create(
-+		struct clock_source_init_data *clk_src_init_data)
-+
-+{
-+	struct vce_clock_source_dce110 *clk_src;
-+
-+	clk_src = dc_service_alloc(clk_src_init_data->ctx, sizeof(struct vce_clock_source_dce110));
-+
-+	if (clk_src == NULL)
-+		return NULL;
-+
-+	if (!construct(clk_src, clk_src_init_data)) {
-+		dc_service_free(clk_src_init_data->ctx, clk_src);
-+		return NULL;
-+	}
-+
-+	return &clk_src->base;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
-new file mode 100644
-index 0000000..227b169
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
-@@ -0,0 +1,32 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_VCE_CLOCK_SOURCE_DCE110__
-+#define __DAL_VCE_CLOCK_SOURCE_DCE110__
-+
-+#include "../clock_source.h"
-+
-+struct clock_source *dal_vce_clock_source_dce110_create(
-+		struct clock_source_init_data *clk_src_init_data);
-+
-+#endif /*__DAL_VCE_CLOCK_SOURCE_DCE110__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-new file mode 100644
-index 0000000..a11aa84
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-@@ -0,0 +1,204 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "display_clock.h"
-+#include "adapter_service_interface.h"
-+
-+void dal_display_clock_base_set_dp_ref_clock_source(
-+	struct display_clock *disp_clk,
-+	enum clock_source_id clk_src)
-+{/*must be implemented in derived*/
-+
-+}
-+
-+void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
-+	struct display_clock_state clk_state)
-+{
-+	/*Implemented only in DCE81*/
-+}
-+struct display_clock_state dal_display_clock_base_get_clock_state(
-+	struct display_clock *disp_clk)
-+{
-+	/*Implemented only in DCE81*/
-+	struct display_clock_state state = {0};
-+	return state;
-+}
-+uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
-+	struct display_clock *disp_clk)
-+{
-+	/*Implemented only in DCE81*/
-+	return 0;
-+}
-+
-+bool dal_display_clock_construct_base(
-+	struct display_clock *base,
-+	struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	base->ctx = ctx;
-+	base->id = CLOCK_SOURCE_ID_DCPLL;
-+	base->min_display_clk_threshold_khz = 0;
-+	base->as = as;
-+
-+/* Initially set current min clocks state to invalid since we
-+ * cannot make any assumption about PPLIB's initial state. This will be updated
-+ * by HWSS via SetMinClocksState() on first mode set prior to programming
-+ * state dependent clocks.*/
-+	base->cur_min_clks_state = CLOCKS_STATE_INVALID;
-+
-+	return true;
-+}
-+
-+void dal_display_clock_destroy(struct display_clock **disp_clk)
-+{
-+	if (!disp_clk || !*disp_clk) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	(*disp_clk)->funcs->destroy(disp_clk);
-+
-+	*disp_clk = NULL;
-+}
-+
-+bool dal_display_clock_validate(
-+	struct display_clock *disp_clk,
-+	struct min_clock_params *params)
-+{
-+	return disp_clk->funcs->validate(disp_clk, params);
-+}
-+
-+uint32_t dal_display_clock_calculate_min_clock(
-+	struct display_clock *disp_clk,
-+	uint32_t path_num,
-+	struct min_clock_params *params)
-+{
-+	return disp_clk->funcs->calculate_min_clock(disp_clk, path_num, params);
-+}
-+
-+uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk)
-+{
-+	return disp_clk->funcs->get_validation_clock(disp_clk);
-+}
-+
-+void dal_display_clock_set_clock(
-+	struct display_clock *disp_clk,
-+	uint32_t requested_clock_khz)
-+{
-+	disp_clk->funcs->set_clock(disp_clk, requested_clock_khz);
-+}
-+
-+uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk)
-+{
-+	return disp_clk->funcs->get_clock(disp_clk);
-+}
-+
-+enum clocks_state dal_display_clock_get_min_clocks_state(
-+	struct display_clock *disp_clk)
-+{
-+	return disp_clk->funcs->get_min_clocks_state(disp_clk);
-+}
-+
-+enum clocks_state dal_display_clock_get_required_clocks_state(
-+	struct display_clock *disp_clk,
-+	struct state_dependent_clocks *req_clocks)
-+{
-+	return disp_clk->funcs->get_required_clocks_state(disp_clk, req_clocks);
-+}
-+
-+bool dal_display_clock_set_min_clocks_state(
-+	struct display_clock *disp_clk,
-+	enum clocks_state clocks_state)
-+{
-+	return disp_clk->funcs->set_min_clocks_state(disp_clk, clocks_state);
-+}
-+
-+uint32_t dal_display_clock_get_dp_ref_clk_frequency(
-+	struct display_clock *disp_clk)
-+{
-+	return disp_clk->funcs->get_dp_ref_clk_frequency(disp_clk);
-+}
-+
-+/*the second parameter of "switchreferenceclock" is
-+ * a dummy argument for all pre dce 6.0 versions*/
-+
-+void dal_display_clock_switch_reference_clock(
-+	struct display_clock *disp_clk,
-+	bool use_external_ref_clk,
-+	uint32_t requested_clk_khz)
-+{
-+	/* TODO: requires Asic Control*/
-+	/*
-+	struct ac_pixel_clk_params params;
-+	struct asic_control *ac =
-+		dal_adapter_service_get_asic_control(disp_clk->as);
-+	dc_service_memset(&params, 0, sizeof(struct ac_pixel_clk_params));
-+
-+	params.tgt_pixel_clk_khz = requested_clk_khz;
-+	params.flags.SET_EXTERNAL_REF_DIV_SRC = use_external_ref_clk;
-+	params.pll_id = disp_clk->id;
-+	dal_asic_control_program_display_engine_pll(ac, &params);
-+	*/
-+}
-+
-+void dal_display_clock_set_dp_ref_clock_source(
-+	struct display_clock *disp_clk,
-+	enum clock_source_id clk_src)
-+{
-+	disp_clk->funcs->set_dp_ref_clock_source(disp_clk, clk_src);
-+}
-+
-+void dal_display_clock_store_max_clocks_state(
-+	struct display_clock *disp_clk,
-+	enum clocks_state max_clocks_state)
-+{
-+	disp_clk->funcs->store_max_clocks_state(disp_clk, max_clocks_state);
-+}
-+
-+void dal_display_clock_set_clock_state(
-+	struct display_clock *disp_clk,
-+	struct display_clock_state clk_state)
-+{
-+	disp_clk->funcs->set_clock_state(disp_clk, clk_state);
-+}
-+
-+struct display_clock_state dal_display_clock_get_clock_state(
-+	struct display_clock *disp_clk)
-+{
-+	return disp_clk->funcs->get_clock_state(disp_clk);
-+}
-+
-+uint32_t dal_display_clock_get_dfs_bypass_threshold(
-+	struct display_clock *disp_clk)
-+{
-+	return disp_clk->funcs->get_dfs_bypass_threshold(disp_clk);
-+}
-+
-+void dal_display_clock_invalid_clock_state(
-+	struct display_clock *disp_clk)
-+{
-+	disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
-new file mode 100644
-index 0000000..845393b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
-@@ -0,0 +1,82 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DISPLAY_CLOCK_H__
-+#define __DAL_DISPLAY_CLOCK_H__
-+
-+#include "include/display_clock_interface.h"
-+
-+struct display_clock_funcs {
-+	void (*destroy)(struct display_clock **to_destroy);
-+	bool (*validate)(struct display_clock *disp_clk,
-+		struct min_clock_params *params);
-+	uint32_t (*calculate_min_clock)(struct display_clock *disp_clk,
-+		uint32_t path_num, struct min_clock_params *params);
-+	uint32_t (*get_validation_clock)(struct display_clock *disp_clk);
-+	void (*set_clock)(struct display_clock *disp_clk,
-+		uint32_t requested_clock_khz);
-+	uint32_t (*get_clock)(struct display_clock *disp_clk);
-+	enum clocks_state (*get_min_clocks_state)(
-+		struct display_clock *disp_clk);
-+	enum clocks_state (*get_required_clocks_state)(
-+		struct display_clock *disp_clk,
-+		struct state_dependent_clocks *req_clocks);
-+	bool (*set_min_clocks_state)(struct display_clock *disp_clk,
-+		enum clocks_state clocks_state);
-+	uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
-+	void (*set_dp_ref_clock_source)(struct display_clock *disp_clk,
-+		enum clock_source_id clk_src);
-+	void (*store_max_clocks_state)(struct display_clock *disp_clk,
-+		enum clocks_state max_clocks_state);
-+	void (*set_clock_state)(struct display_clock *disp_clk,
-+		struct display_clock_state clk_state);
-+	struct display_clock_state (*get_clock_state)(
-+		struct display_clock *disp_clk);
-+	uint32_t (*get_dfs_bypass_threshold)(struct display_clock *disp_clk);
-+};
-+
-+struct display_clock {
-+	struct dc_context *ctx;
-+	const struct display_clock_funcs *funcs;
-+	uint32_t min_display_clk_threshold_khz;
-+	enum clock_source_id id;
-+	struct adapter_service *as;
-+
-+	enum clocks_state cur_min_clks_state;
-+};
-+void dal_display_clock_base_set_dp_ref_clock_source(
-+	struct display_clock *disp_clk,
-+	enum clock_source_id clk_src);
-+struct display_clock_state dal_display_clock_base_get_clock_state(
-+	struct display_clock *disp_clk);
-+uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
-+	struct display_clock *disp_clk);
-+void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
-+	struct display_clock_state clk_state);
-+bool dal_display_clock_construct_base(
-+	struct display_clock *base,
-+	struct dc_context *ctx,
-+	struct adapter_service *as);
-+#endif /* __DAL_DISPLAY_CLOCK_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-new file mode 100644
-index 0000000..3b04447
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-@@ -0,0 +1,127 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dal_services.h"
-+#include "divider_range.h"
-+
-+bool dal_divider_range_construct(
-+	struct divider_range *div_range,
-+	uint32_t range_start,
-+	uint32_t range_step,
-+	uint32_t did_min,
-+	uint32_t did_max)
-+{
-+	div_range->div_range_start = range_start;
-+	div_range->div_range_step = range_step;
-+	div_range->did_min = did_min;
-+	div_range->did_max = did_max;
-+
-+	if (div_range->div_range_step == 0) {
-+		div_range->div_range_step = 1;
-+		/*div_range_step cannot be zero*/
-+		BREAK_TO_DEBUGGER();
-+	}
-+	/* Calculate this based on the other inputs.*/
-+	/* See DividerRange.h for explanation of */
-+	/* the relationship between divider id (DID) and a divider.*/
-+	/* Number of Divider IDs = (Maximum Divider ID - Minimum Divider ID)*/
-+	/* Maximum divider identified in this range =
-+	 * (Number of Divider IDs)*Step size between dividers
-+	 *  + The start of this range.*/
-+	div_range->div_range_end = (did_max - did_min) * range_step
-+		+ range_start;
-+	return true;
-+}
-+
-+static uint32_t dal_divider_range_calc_divider(
-+	struct divider_range *div_range,
-+	uint32_t did)
-+{
-+	/* Is this DID within our range?*/
-+	if ((did < div_range->did_min) || (did >= div_range->did_max))
-+		return INVALID_DIVIDER;
-+
-+	return ((did - div_range->did_min) * div_range->div_range_step)
-+			+ div_range->div_range_start;
-+
-+}
-+
-+static uint32_t dal_divider_range_calc_did(
-+	struct divider_range *div_range,
-+	uint32_t div)
-+{
-+	uint32_t did;
-+	/* Check before dividing.*/
-+	if (div_range->div_range_step == 0) {
-+		div_range->div_range_step = 1;
-+		/*div_range_step cannot be zero*/
-+		BREAK_TO_DEBUGGER();
-+	}
-+	/* Is this divider within our range?*/
-+	if ((div < div_range->div_range_start)
-+		|| (div >= div_range->div_range_end))
-+		return INVALID_DID;
-+/* did = (divider - range_start + (range_step-1)) / range_step) + did_min*/
-+	did = div - div_range->div_range_start;
-+	did += div_range->div_range_step - 1;
-+	did /= div_range->div_range_step;
-+	did += div_range->did_min;
-+	return did;
-+}
-+
-+uint32_t dal_divider_range_get_divider(
-+	struct divider_range *div_range,
-+	uint32_t ranges_num,
-+	uint32_t did)
-+{
-+	uint32_t div = INVALID_DIVIDER;
-+	uint32_t i;
-+
-+	for (i = 0; i < ranges_num; i++) {
-+		/* Calculate divider with given divider ID*/
-+		div = dal_divider_range_calc_divider(&div_range[i], did);
-+		/* Found a valid return divider*/
-+		if (div != INVALID_DIVIDER)
-+			break;
-+	}
-+	return div;
-+}
-+uint32_t dal_divider_range_get_did(
-+	struct divider_range *div_range,
-+	uint32_t ranges_num,
-+	uint32_t divider)
-+{
-+	uint32_t did = INVALID_DID;
-+	uint32_t i;
-+
-+	for (i = 0; i < ranges_num; i++) {
-+		/*  CalcDid returns InvalidDid if a divider ID isn't found*/
-+		did = dal_divider_range_calc_did(&div_range[i], divider);
-+		/* Found a valid return did*/
-+		if (did != INVALID_DID)
-+			break;
-+	}
-+	return did;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
-new file mode 100644
-index 0000000..2ec1034
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
-@@ -0,0 +1,63 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DIVIDER_RANGE_H__
-+#define __DAL_DIVIDER_RANGE_H__
-+
-+enum divider_error_types {
-+	INVALID_DID = 0,
-+	INVALID_DIVIDER = 1
-+};
-+
-+struct divider_range {
-+	uint32_t div_range_start;
-+	/* The end of this range of dividers.*/
-+	uint32_t div_range_end;
-+	/* The distance between each divider in this range.*/
-+	uint32_t div_range_step;
-+	/* The divider id for the lowest divider.*/
-+	uint32_t did_min;
-+	/* The divider id for the highest divider.*/
-+	uint32_t did_max;
-+};
-+
-+bool dal_divider_range_construct(
-+	struct divider_range *div_range,
-+	uint32_t range_start,
-+	uint32_t range_step,
-+	uint32_t did_min,
-+	uint32_t did_max);
-+
-+uint32_t dal_divider_range_get_divider(
-+	struct divider_range *div_range,
-+	uint32_t ranges_num,
-+	uint32_t did);
-+uint32_t dal_divider_range_get_did(
-+	struct divider_range *div_range,
-+	uint32_t ranges_num,
-+	uint32_t divider);
-+
-+
-+#endif /* __DAL_DIVIDER_RANGE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-new file mode 100644
-index 0000000..ac27cd7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-@@ -0,0 +1,119 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/clock_source_types.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/logger_interface.h"
-+#include "ext_clock_source.h"
-+
-+uint32_t dal_ext_clock_source_get_pix_clk_dividers(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct ext_clock_source *ext_clk_src = container_of(
-+			clk_src,
-+			struct ext_clock_source,
-+			base);
-+
-+	if (pix_clk_params == NULL ||
-+			pll_settings == NULL ||
-+			pix_clk_params->requested_pix_clk == 0) {
-+		dal_logger_write(clk_src->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid parameters!!", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+	dc_service_memset(pll_settings, 0, sizeof(struct pll_settings));
-+	pll_settings->adjusted_pix_clk = ext_clk_src->ext_clk_freq_khz;
-+	pll_settings->calculated_pix_clk = ext_clk_src->ext_clk_freq_khz;
-+	pll_settings->actual_pix_clk =
-+			pix_clk_params->requested_pix_clk;
-+	return 0;
-+}
-+
-+bool dal_ext_clock_source_program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct bp_pixel_clock_parameters bp_pix_clk_params = {0};
-+
-+	bp_pix_clk_params.controller_id = pix_clk_params->controller_id;
-+	bp_pix_clk_params.pll_id = clk_src->clk_src_id;
-+	bp_pix_clk_params.target_pixel_clock =
-+			pix_clk_params->requested_pix_clk;
-+	bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
-+	bp_pix_clk_params.dvo_config = pix_clk_params->dvo_cfg;
-+
-+
-+	if (dal_bios_parser_set_pixel_clock(
-+					clk_src->bios_parser,
-+					&bp_pix_clk_params) == BP_RESULT_OK)
-+		return true;
-+	return false;
-+
-+}
-+
-+bool dal_ext_clock_source_power_down_pll(struct clock_source *clk_src,
-+		enum controller_id controller_id)
-+{
-+	return true;
-+}
-+
-+bool dal_ext_clock_source_construct(
-+		struct ext_clock_source *ext_clk_src,
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	struct firmware_info fw_info = { { 0 } };
-+
-+	if (!dal_clock_source_construct(
-+		&ext_clk_src->base, clk_src_init_data)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	ext_clk_src->base.clk_sharing_lvl =
-+			CLOCK_SHARING_LEVEL_DISPLAY_PORT_SHAREABLE;
-+	ext_clk_src->base.is_clock_source_with_fixed_freq = true;
-+	/*  ExtClock has fixed frequency,
-+	 * so it supports only DisplayPort signals.*/
-+	ext_clk_src->base.output_signals =
-+			SIGNAL_TYPE_DISPLAY_PORT |
-+			SIGNAL_TYPE_DISPLAY_PORT_MST |
-+			SIGNAL_TYPE_EDP;
-+
-+	/*Get External clock frequency from ATOMBIOS Data table */
-+	if (dal_bios_parser_get_firmware_info(
-+			ext_clk_src->base.bios_parser,
-+			&fw_info) != BP_RESULT_OK)
-+		return false;
-+	ext_clk_src->ext_clk_freq_khz = fw_info.
-+			external_clock_source_frequency_for_dp;
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
-new file mode 100644
-index 0000000..bef1dc4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
-@@ -0,0 +1,47 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_EXT_CLOCK_SOURCE_H__
-+#define __DAL_EXT_CLOCK_SOURCE_H__
-+
-+#include "clock_source.h"
-+
-+struct ext_clock_source {
-+	struct clock_source base;
-+	uint32_t ext_clk_freq_khz;
-+};
-+
-+bool dal_ext_clock_source_construct(
-+		struct ext_clock_source *ext_cs,
-+		struct clock_source_init_data *clk_src_init_data);
-+bool dal_ext_clock_source_power_down_pll(struct clock_source *clk_src,
-+		enum controller_id controller_id);
-+uint32_t dal_ext_clock_source_get_pix_clk_dividers(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings);
-+bool dal_ext_clock_source_program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings);
-+#endif /*__DAL_EXT_CLOCK_SOURCE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-new file mode 100644
-index 0000000..8bb0304
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-@@ -0,0 +1,141 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/bios_parser_interface.h"
-+#include "pll_clock_source.h"
-+
-+bool dal_pll_clock_source_power_down_pll(
-+		struct clock_source *clk_src,
-+		enum controller_id controller_id)
-+{
-+
-+	enum bp_result bp_result;
-+	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
-+
-+	/* If Pixel Clock is 0 it means Power Down Pll*/
-+	bp_pixel_clock_params.controller_id = controller_id;
-+	bp_pixel_clock_params.pll_id = clk_src->clk_src_id;
-+	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	bp_result = dal_bios_parser_set_pixel_clock(
-+			clk_src->bios_parser,
-+			&bp_pixel_clock_params);
-+
-+	return bp_result == BP_RESULT_OK;
-+}
-+
-+bool dal_pll_clock_source_adjust_pix_clk(
-+		struct pll_clock_source *pll_clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	uint32_t actual_pix_clk_khz = 0;
-+	uint32_t requested_clk_khz = 0;
-+	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
-+							0 };
-+	enum bp_result bp_result;
-+
-+	switch (pix_clk_params->signal_type) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A: {
-+		requested_clk_khz = pix_clk_params->requested_pix_clk;
-+
-+		switch (pix_clk_params->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			requested_clk_khz = (requested_clk_khz * 5) >> 2;
-+			break; /* x1.25*/
-+		case COLOR_DEPTH_121212:
-+			requested_clk_khz = (requested_clk_khz * 6) >> 2;
-+			break; /* x1.5*/
-+		case COLOR_DEPTH_161616:
-+			requested_clk_khz = requested_clk_khz * 2;
-+			break; /* x2.0*/
-+		default:
-+			break;
-+		}
-+
-+		actual_pix_clk_khz = requested_clk_khz;
-+	}
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		requested_clk_khz = pix_clk_params->requested_sym_clk;
-+		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
-+		break;
-+
-+	default:
-+		requested_clk_khz = pix_clk_params->requested_pix_clk;
-+		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
-+		break;
-+	}
-+
-+	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
-+	bp_adjust_pixel_clock_params.
-+		encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
-+	bp_adjust_pixel_clock_params.dvo_config = pix_clk_params->dvo_cfg;
-+	bp_adjust_pixel_clock_params.
-+		display_pll_config = pix_clk_params->disp_pll_cfg;
-+	bp_adjust_pixel_clock_params.
-+		ss_enable = pix_clk_params->flags.ENABLE_SS;
-+	bp_result = dal_bios_parser_adjust_pixel_clock(
-+			pll_clk_src->base.bios_parser,
-+			&bp_adjust_pixel_clock_params);
-+	if (bp_result == BP_RESULT_OK) {
-+		pll_settings->actual_pix_clk = actual_pix_clk_khz;
-+		pll_settings->adjusted_pix_clk =
-+			bp_adjust_pixel_clock_params.adjusted_pixel_clock;
-+		pll_settings->reference_divider =
-+			bp_adjust_pixel_clock_params.reference_divider;
-+		pll_settings->pix_clk_post_divider =
-+			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool dal_pll_clock_source_construct(
-+		struct pll_clock_source *pll_clk_src,
-+		struct clock_source_init_data *clk_src_init_data)
-+{
-+	struct firmware_info fw_info = { { 0 } };
-+
-+	if (!dal_clock_source_construct(
-+			&pll_clk_src->base,
-+			clk_src_init_data))
-+		return false;
-+
-+	if (dal_bios_parser_get_firmware_info(
-+			pll_clk_src->base.bios_parser,
-+			&fw_info) != BP_RESULT_OK)
-+		return false;
-+	pll_clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
-new file mode 100644
-index 0000000..8339e1f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
-@@ -0,0 +1,52 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_PLL_CLOCK_SOURCE_H__
-+#define __DAL_PLL_CLOCK_SOURCE_H__
-+
-+#include "gpu/clock_source.h"
-+
-+struct pll_clock_source {
-+	struct clock_source base;
-+	uint32_t ref_freq_khz;
-+};
-+
-+struct delta_sigma_data {
-+	uint32_t feedback_amount;
-+	uint32_t nfrac_amount;
-+	uint32_t ds_frac_size;
-+	uint32_t ds_frac_amount;
-+};
-+
-+bool dal_pll_clock_source_construct(
-+		struct pll_clock_source *pll_clk_src,
-+		struct clock_source_init_data *clk_src_init_data);
-+
-+bool dal_pll_clock_source_adjust_pix_clk(
-+		struct pll_clock_source *pll_clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings);
-+bool dal_pll_clock_source_power_down_pll(
-+		struct clock_source *clk_src,
-+		enum controller_id controller_id);
-+#endif /*__DAL_PLL_CLOCK_SOURCE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-new file mode 100644
-index 0000000..15902a8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-@@ -0,0 +1,23 @@
-+#
-+# Makefile for the 'i2c' sub-component of DAL.
-+# It provides the control and status of HW i2c engine of the adapter.
-+
-+I2CAUX = aux_engine.o engine_base.o i2caux.o i2c_engine.o \
-+	 i2c_generic_hw_engine.o i2c_hw_engine.o i2c_sw_engine.o
-+
-+AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
-+
-+AMD_DAL_FILES += $(AMD_DAL_I2CAUX)
-+
-+
-+###############################################################################
-+# DCE 11x family
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+I2CAUX_DCE110 = i2caux_dce110.o i2c_sw_engine_dce110.o i2c_hw_engine_dce110.o \
-+	aux_engine_dce110.o
-+
-+AMD_DAL_I2CAUX_DCE110 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce110/,$(I2CAUX_DCE110))
-+
-+AMD_DAL_FILES += $(AMD_DAL_I2CAUX_DCE110)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-new file mode 100644
-index 0000000..824ceec
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-@@ -0,0 +1,568 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "aux_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "include/link_service_types.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+enum {
-+	AUX_INVALID_REPLY_RETRY_COUNTER = 1,
-+	AUX_TIMED_OUT_RETRY_COUNTER = 2,
-+	AUX_DEFER_RETRY_COUNTER = 6
-+};
-+
-+#define FROM_ENGINE(ptr) \
-+	container_of((ptr), struct aux_engine, base)
-+
-+enum i2caux_engine_type dal_aux_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_AUX;
-+}
-+
-+bool dal_aux_engine_acquire(
-+	struct engine *engine,
-+	struct ddc *ddc)
-+{
-+	struct aux_engine *aux_engine = FROM_ENGINE(engine);
-+
-+	enum gpio_result result;
-+
-+	result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-+		GPIO_DDC_CONFIG_TYPE_MODE_AUX);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return false;
-+
-+	if (!aux_engine->funcs->acquire_engine(aux_engine)) {
-+		dal_ddc_close(ddc);
-+		return false;
-+	}
-+
-+	engine->ddc = ddc;
-+
-+	return true;
-+}
-+
-+struct read_command_context {
-+	uint8_t *buffer;
-+	uint8_t current_read_length;
-+	uint32_t offset;
-+	enum i2caux_transaction_status status;
-+
-+	struct aux_request_transaction_data request;
-+	struct aux_reply_transaction_data reply;
-+
-+	uint8_t returned_byte;
-+
-+	uint32_t timed_out_retry_aux;
-+	uint32_t invalid_reply_retry_aux;
-+	uint32_t defer_retry_aux;
-+	uint32_t defer_retry_i2c;
-+	uint32_t invalid_reply_retry_aux_on_ack;
-+
-+	bool transaction_complete;
-+	bool operation_succeeded;
-+};
-+
-+static void process_read_reply(
-+	struct aux_engine *engine,
-+	struct read_command_context *ctx)
-+{
-+	engine->funcs->process_channel_reply(engine, &ctx->reply);
-+
-+	switch (ctx->reply.status) {
-+	case AUX_TRANSACTION_REPLY_AUX_ACK:
-+		ctx->defer_retry_aux = 0;
-+		if (ctx->returned_byte > ctx->current_read_length) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else if (ctx->returned_byte < ctx->current_read_length) {
-+			ctx->current_read_length -= ctx->returned_byte;
-+
-+			ctx->offset += ctx->returned_byte;
-+
-+			++ctx->invalid_reply_retry_aux_on_ack;
-+
-+			if (ctx->invalid_reply_retry_aux_on_ack >
-+				AUX_INVALID_REPLY_RETRY_COUNTER) {
-+				ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+				ctx->operation_succeeded = false;
-+			}
-+		} else {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+			ctx->transaction_complete = true;
-+			ctx->operation_succeeded = true;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_NACK:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+		ctx->operation_succeeded = false;
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_DEFER:
-+		++ctx->defer_retry_aux;
-+
-+		if (ctx->defer_retry_aux > AUX_DEFER_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_I2C_DEFER:
-+		ctx->defer_retry_aux = 0;
-+
-+		++ctx->defer_retry_i2c;
-+
-+		if (ctx->defer_retry_i2c > AUX_DEFER_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static void process_read_request(
-+	struct aux_engine *engine,
-+	struct read_command_context *ctx)
-+{
-+	enum aux_channel_operation_result operation_result;
-+
-+	engine->funcs->submit_channel_request(engine, &ctx->request);
-+
-+	operation_result = engine->funcs->get_channel_status(
-+		engine, &ctx->returned_byte);
-+
-+	switch (operation_result) {
-+	case AUX_CHANNEL_OPERATION_SUCCEEDED:
-+		if (ctx->returned_byte > ctx->current_read_length) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else {
-+			ctx->timed_out_retry_aux = 0;
-+			ctx->invalid_reply_retry_aux = 0;
-+
-+			ctx->reply.length = ctx->returned_byte;
-+			ctx->reply.data = ctx->buffer;
-+
-+			process_read_reply(engine, ctx);
-+		}
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-+		++ctx->invalid_reply_retry_aux;
-+
-+		if (ctx->invalid_reply_retry_aux >
-+			AUX_INVALID_REPLY_RETRY_COUNTER) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else
-+			dc_service_delay_in_microseconds(engine->base.ctx, 400);
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-+		++ctx->timed_out_retry_aux;
-+
-+		if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		} else {
-+			/* DP 1.2a, table 2-58:
-+			 * "S3: AUX Request CMD PENDING:
-+			 * retry 3 times, with 400usec wait on each"
-+			 * The HW timeout is set to 550usec,
-+			 * so we should not wait here */
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static bool read_command(
-+	struct aux_engine *engine,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction)
-+{
-+	struct read_command_context ctx;
-+
-+	ctx.buffer = request->payload.data;
-+	ctx.current_read_length = request->payload.length;
-+	ctx.offset = 0;
-+	ctx.timed_out_retry_aux = 0;
-+	ctx.invalid_reply_retry_aux = 0;
-+	ctx.defer_retry_aux = 0;
-+	ctx.defer_retry_i2c = 0;
-+	ctx.invalid_reply_retry_aux_on_ack = 0;
-+	ctx.transaction_complete = false;
-+	ctx.operation_succeeded = true;
-+
-+	if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-+		ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
-+		ctx.request.address = request->payload.address;
-+	} else if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-+		ctx.request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+		ctx.request.address = request->payload.address >> 1;
-+	} else {
-+		/* in DAL2, there was no return in such case */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	ctx.request.delay = 0;
-+
-+	do {
-+		dc_service_memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-+
-+		ctx.request.data = ctx.buffer + ctx.offset;
-+		ctx.request.length = ctx.current_read_length;
-+
-+		process_read_request(engine, &ctx);
-+
-+		request->status = ctx.status;
-+
-+		if (ctx.operation_succeeded && !ctx.transaction_complete)
-+			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-+				dc_service_sleep_in_milliseconds(engine->base.ctx, engine->delay);
-+	} while (ctx.operation_succeeded && !ctx.transaction_complete);
-+
-+	return ctx.operation_succeeded;
-+}
-+
-+struct write_command_context {
-+	bool mot;
-+
-+	uint8_t *buffer;
-+	uint8_t current_write_length;
-+	enum i2caux_transaction_status status;
-+
-+	struct aux_request_transaction_data request;
-+	struct aux_reply_transaction_data reply;
-+
-+	uint8_t returned_byte;
-+
-+	uint32_t timed_out_retry_aux;
-+	uint32_t invalid_reply_retry_aux;
-+	uint32_t defer_retry_aux;
-+	uint32_t defer_retry_i2c;
-+	uint32_t max_defer_retry;
-+	uint32_t ack_m_retry;
-+
-+	uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
-+
-+	bool transaction_complete;
-+	bool operation_succeeded;
-+};
-+
-+static void process_write_reply(
-+	struct aux_engine *engine,
-+	struct write_command_context *ctx)
-+{
-+	engine->funcs->process_channel_reply(engine, &ctx->reply);
-+
-+	switch (ctx->reply.status) {
-+	case AUX_TRANSACTION_REPLY_AUX_ACK:
-+		ctx->operation_succeeded = true;
-+
-+		if (ctx->returned_byte) {
-+			ctx->request.action = ctx->mot ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-+
-+			ctx->current_write_length = 0;
-+
-+			++ctx->ack_m_retry;
-+
-+			if (ctx->ack_m_retry > AUX_DEFER_RETRY_COUNTER) {
-+				ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+				ctx->operation_succeeded = false;
-+			} else
-+				dc_service_delay_in_microseconds(engine->base.ctx, 300);
-+		} else {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+			ctx->defer_retry_aux = 0;
-+			ctx->ack_m_retry = 0;
-+			ctx->transaction_complete = true;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_NACK:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+		ctx->operation_succeeded = false;
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_DEFER:
-+		++ctx->defer_retry_aux;
-+
-+		if (ctx->defer_retry_aux > ctx->max_defer_retry) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_I2C_DEFER:
-+		ctx->defer_retry_aux = 0;
-+		ctx->current_write_length = 0;
-+
-+		ctx->request.action = ctx->mot ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-+
-+		++ctx->defer_retry_i2c;
-+
-+		if (ctx->defer_retry_i2c > ctx->max_defer_retry) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static void process_write_request(
-+	struct aux_engine *engine,
-+	struct write_command_context *ctx)
-+{
-+	enum aux_channel_operation_result operation_result;
-+
-+	engine->funcs->submit_channel_request(engine, &ctx->request);
-+
-+	operation_result = engine->funcs->get_channel_status(
-+		engine, &ctx->returned_byte);
-+
-+	switch (operation_result) {
-+	case AUX_CHANNEL_OPERATION_SUCCEEDED:
-+		ctx->timed_out_retry_aux = 0;
-+		ctx->invalid_reply_retry_aux = 0;
-+
-+		ctx->reply.length = ctx->returned_byte;
-+		ctx->reply.data = ctx->reply_data;
-+
-+		process_write_reply(engine, ctx);
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-+		++ctx->invalid_reply_retry_aux;
-+
-+		if (ctx->invalid_reply_retry_aux >
-+			AUX_INVALID_REPLY_RETRY_COUNTER) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else
-+			dc_service_delay_in_microseconds(engine->base.ctx, 400);
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-+		++ctx->timed_out_retry_aux;
-+
-+		if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		} else {
-+			/* DP 1.2a, table 2-58:
-+			 * "S3: AUX Request CMD PENDING:
-+			 * retry 3 times, with 400usec wait on each"
-+			 * The HW timeout is set to 550usec,
-+			 * so we should not wait here */
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static bool write_command(
-+	struct aux_engine *engine,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction)
-+{
-+	struct write_command_context ctx;
-+
-+	ctx.mot = middle_of_transaction;
-+	ctx.buffer = request->payload.data;
-+	ctx.current_write_length = request->payload.length;
-+	ctx.timed_out_retry_aux = 0;
-+	ctx.invalid_reply_retry_aux = 0;
-+	ctx.defer_retry_aux = 0;
-+	ctx.defer_retry_i2c = 0;
-+	ctx.ack_m_retry = 0;
-+	ctx.transaction_complete = false;
-+	ctx.operation_succeeded = true;
-+
-+	if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-+		ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
-+		ctx.request.address = request->payload.address;
-+	} else if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-+		ctx.request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+		ctx.request.address = request->payload.address >> 1;
-+	} else {
-+		/* in DAL2, there was no return in such case */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	ctx.request.delay = 0;
-+
-+	ctx.max_defer_retry =
-+		(engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
-+			engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
-+
-+	do {
-+		ctx.request.data = ctx.buffer;
-+		ctx.request.length = ctx.current_write_length;
-+
-+		process_write_request(engine, &ctx);
-+
-+		request->status = ctx.status;
-+
-+		if (ctx.operation_succeeded && !ctx.transaction_complete)
-+			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-+				dc_service_sleep_in_milliseconds(engine->base.ctx, engine->delay);
-+	} while (ctx.operation_succeeded && !ctx.transaction_complete);
-+
-+	return ctx.operation_succeeded;
-+}
-+
-+static bool end_of_transaction_command(
-+	struct aux_engine *engine,
-+	struct i2caux_transaction_request *request)
-+{
-+	struct i2caux_transaction_request dummy_request;
-+	uint8_t dummy_data;
-+
-+	/* [tcheng] We only need to send the stop (read with MOT = 0)
-+	 * for I2C-over-Aux, not native AUX */
-+
-+	if (request->payload.address_space !=
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C)
-+		return false;
-+
-+	dummy_request.operation = request->operation;
-+	dummy_request.payload.address_space = request->payload.address_space;
-+	dummy_request.payload.address = request->payload.address;
-+
-+	/*
-+	 * Add a dummy byte due to some receiver quirk
-+	 * where one byte is sent along with MOT = 0.
-+	 * Ideally this should be 0.
-+	 */
-+
-+	dummy_request.payload.length = 0;
-+	dummy_request.payload.data = &dummy_data;
-+
-+	if (request->operation == I2CAUX_TRANSACTION_READ)
-+		return read_command(engine, &dummy_request, false);
-+	else
-+		return write_command(engine, &dummy_request, false);
-+
-+	/* according Syed, it does not need now DoDummyMOT */
-+}
-+
-+bool dal_aux_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction)
-+{
-+	struct aux_engine *aux_engine = FROM_ENGINE(engine);
-+
-+	bool result;
-+	bool mot_used = true;
-+
-+	switch (request->operation) {
-+	case I2CAUX_TRANSACTION_READ:
-+		result = read_command(aux_engine, request, mot_used);
-+	break;
-+	case I2CAUX_TRANSACTION_WRITE:
-+		result = write_command(aux_engine, request, mot_used);
-+	break;
-+	default:
-+		result = false;
-+	}
-+
-+	/* [tcheng]
-+	 * need to send stop for the last transaction to free up the AUX
-+	 * if the above command fails, this would be the last transaction */
-+
-+	if (!middle_of_transaction || !result)
-+		end_of_transaction_command(aux_engine, request);
-+
-+	/* mask AUX interrupt */
-+
-+	return result;
-+}
-+
-+bool dal_aux_engine_construct(
-+	struct aux_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_i2caux_construct_engine(&engine->base, ctx))
-+		return false;
-+	engine->delay = 0;
-+	engine->max_defer_write_retry = 0;
-+	return true;
-+}
-+
-+void dal_aux_engine_destruct(
-+	struct aux_engine *engine)
-+{
-+	dal_i2caux_destruct_engine(&engine->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h
-new file mode 100644
-index 0000000..474f5e9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h
-@@ -0,0 +1,119 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUX_ENGINE_H__
-+#define __DAL_AUX_ENGINE_H__
-+
-+enum aux_transaction_type {
-+	AUX_TRANSACTION_TYPE_DP,
-+	AUX_TRANSACTION_TYPE_I2C
-+};
-+
-+struct aux_request_transaction_data {
-+	enum aux_transaction_type type;
-+	enum i2caux_transaction_action action;
-+	/* 20-bit AUX channel transaction address */
-+	uint32_t address;
-+	/* delay, in 100-microsecond units */
-+	uint8_t delay;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+enum aux_transaction_reply {
-+	AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
-+	AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
-+	AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
-+
-+	AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
-+	AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
-+	AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
-+
-+	AUX_TRANSACTION_REPLY_INVALID = 0xFF
-+};
-+
-+struct aux_reply_transaction_data {
-+	enum aux_transaction_reply status;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+enum aux_channel_operation_result {
-+	AUX_CHANNEL_OPERATION_SUCCEEDED,
-+	AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
-+	AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
-+	AUX_CHANNEL_OPERATION_FAILED_TIMEOUT
-+};
-+
-+struct aux_engine;
-+
-+struct aux_engine_funcs {
-+	void (*destroy)(
-+		struct aux_engine **ptr);
-+	bool (*acquire_engine)(
-+		struct aux_engine *engine);
-+	void (*configure)(
-+		struct aux_engine *engine,
-+		union aux_config cfg);
-+	bool (*start_gtc_sync)(
-+		struct aux_engine *engine);
-+	void (*stop_gtc_sync)(
-+		struct aux_engine *engine);
-+	void (*submit_channel_request)(
-+		struct aux_engine *engine,
-+		struct aux_request_transaction_data *request);
-+	void (*process_channel_reply)(
-+		struct aux_engine *engine,
-+		struct aux_reply_transaction_data *reply);
-+	enum aux_channel_operation_result (*get_channel_status)(
-+		struct aux_engine *engine,
-+		uint8_t *returned_bytes);
-+};
-+
-+struct aux_engine {
-+	struct engine base;
-+	const struct aux_engine_funcs *funcs;
-+	/* following values are expressed in milliseconds */
-+	uint32_t delay;
-+	uint32_t max_defer_write_retry;
-+};
-+
-+bool dal_aux_engine_construct(
-+	struct aux_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_aux_engine_destruct(
-+	struct aux_engine *engine);
-+bool dal_aux_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction);
-+bool dal_aux_engine_acquire(
-+	struct engine *ptr,
-+	struct ddc *ddc);
-+enum i2caux_engine_type dal_aux_engine_get_engine_type(
-+	const struct engine *engine);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-new file mode 100644
-index 0000000..1b40a78
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-@@ -0,0 +1,789 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../aux_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "aux_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct aux_engine *'
-+ * to 'struct aux_engine_dce110 *'
-+ */
-+#define FROM_AUX_ENGINE(ptr) \
-+	container_of((ptr), struct aux_engine_dce110, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct aux_engine_dce110 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct aux_engine_dce110 *aux_engine = FROM_ENGINE(engine);
-+
-+	const uint32_t addr = aux_engine->addr.aux_arb_control;
-+
-+	uint32_t value = dal_read_reg(engine->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		AUX_ARB_CONTROL,
-+		AUX_SW_DONE_USING_AUX_REG);
-+
-+	dal_write_reg(engine->ctx, addr, value);
-+}
-+
-+static void destruct(
-+	struct aux_engine_dce110 *engine);
-+
-+static void destroy(
-+	struct aux_engine **aux_engine)
-+{
-+	struct aux_engine_dce110 *engine = FROM_AUX_ENGINE(*aux_engine);
-+
-+	destruct(engine);
-+
-+	dc_service_free((*aux_engine)->base.ctx, engine);
-+
-+	*aux_engine = NULL;
-+}
-+
-+#define SW_CAN_ACCESS_AUX 1
-+
-+static bool acquire_engine(
-+	struct aux_engine *engine)
-+{
-+	struct aux_engine_dce110 *aux_engine = FROM_AUX_ENGINE(engine);
-+	uint32_t value;
-+	uint32_t field;
-+
-+	/* enable AUX before request SW to access AUX */
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_control;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		field = get_reg_field_value(
-+				value,
-+				AUX_CONTROL,
-+				AUX_EN);
-+
-+		if (field == 0) {
-+			uint8_t counter = 0;
-+
-+			set_reg_field_value(
-+				value,
-+				1,
-+				AUX_CONTROL,
-+				AUX_EN);
-+
-+			/*DP_AUX block as part of the enable sequence*/
-+			set_reg_field_value(
-+				value,
-+				1,
-+				AUX_CONTROL,
-+				AUX_RESET);
-+
-+			dal_write_reg(engine->base.ctx, addr, value);
-+
-+			/*poll HW to make sure reset it done*/
-+			do {
-+				dc_service_delay_in_microseconds(engine->base.ctx, 1);
-+
-+				value = dal_read_reg(engine->base.ctx, addr);
-+
-+				field = get_reg_field_value(
-+						value,
-+						AUX_CONTROL,
-+						AUX_RESET_DONE);
-+
-+				counter++;
-+
-+			} while ((field == 0) && (counter < 11));
-+
-+			set_reg_field_value(
-+				value,
-+				0,
-+				AUX_CONTROL,
-+				AUX_RESET);
-+
-+			dal_write_reg(engine->base.ctx, addr, value);
-+
-+			counter = 0;
-+
-+			do {
-+				dc_service_delay_in_microseconds(engine->base.ctx, 1);
-+
-+				value = dal_read_reg(engine->base.ctx, addr);
-+
-+				field = get_reg_field_value(
-+						value,
-+						AUX_CONTROL,
-+						AUX_RESET_DONE);
-+
-+				counter++;
-+
-+			} while ((field == 1) && (counter < 11));
-+		} /*if (field)*/
-+	}
-+
-+	/* request SW to access AUX */
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_arb_control;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_ARB_CONTROL,
-+			AUX_SW_USE_AUX_REG_REQ);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		field = get_reg_field_value(
-+				value,
-+				AUX_ARB_CONTROL,
-+				AUX_REG_RW_CNTL_STATUS);
-+
-+		return field == SW_CAN_ACCESS_AUX;
-+	}
-+}
-+
-+static void configure(
-+	struct aux_engine *engine,
-+	union aux_config cfg)
-+{
-+	struct aux_engine_dce110 *aux_engine = FROM_AUX_ENGINE(engine);
-+
-+	const uint32_t addr = aux_engine->addr.aux_control;
-+
-+	uint32_t value = dal_read_reg(engine->base.ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		(0 != cfg.bits.ALLOW_AUX_WHEN_HPD_LOW),
-+		AUX_CONTROL,
-+		AUX_IGNORE_HPD_DISCON);
-+
-+	dal_write_reg(engine->base.ctx, addr, value);
-+}
-+
-+static bool start_gtc_sync(
-+	struct aux_engine *engine)
-+{
-+	/*TODO*/
-+	return false;
-+}
-+
-+static void stop_gtc_sync(
-+	struct aux_engine *engine)
-+{
-+	/*TODO*/
-+}
-+
-+#define COMPOSE_AUX_SW_DATA_16_20(command, address) \
-+	((command) | ((0xF0000 & (address)) >> 16))
-+
-+#define COMPOSE_AUX_SW_DATA_8_15(address) \
-+	((0xFF00 & (address)) >> 8)
-+
-+#define COMPOSE_AUX_SW_DATA_0_7(address) \
-+	(0xFF & (address))
-+
-+static void submit_channel_request(
-+	struct aux_engine *engine,
-+	struct aux_request_transaction_data *request)
-+{
-+	struct aux_engine_dce110 *aux_engine = FROM_AUX_ENGINE(engine);
-+	uint32_t value;
-+	uint32_t length;
-+
-+	bool is_write =
-+		((request->type == AUX_TRANSACTION_TYPE_DP) &&
-+		 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
-+		((request->type == AUX_TRANSACTION_TYPE_I2C) &&
-+		((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
-+
-+	/* clear_aux_error */
-+	{
-+		const uint32_t addr = mmAUXN_IMPCAL;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXN_IMPCAL,
-+			AUXN_CALOUT_ERROR_AK);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXN_IMPCAL,
-+			AUXN_CALOUT_ERROR_AK);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+	{
-+		const uint32_t addr = mmAUXP_IMPCAL;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXP_IMPCAL,
-+			AUXP_CALOUT_ERROR_AK);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXP_IMPCAL,
-+			AUXP_CALOUT_ERROR_AK);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	/* force_default_calibrate */
-+	{
-+		const uint32_t addr = mmAUXN_IMPCAL;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXN_IMPCAL,
-+			AUXN_IMPCAL_ENABLE);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXN_IMPCAL,
-+			AUXN_IMPCAL_OVERRIDE_ENABLE);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+	{
-+		const uint32_t addr = mmAUXP_IMPCAL;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXP_IMPCAL,
-+			AUXP_IMPCAL_OVERRIDE_ENABLE);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXP_IMPCAL,
-+			AUXP_IMPCAL_OVERRIDE_ENABLE);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	/* set the delay and the number of bytes to write */
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_sw_control;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			request->delay,
-+			AUX_SW_CONTROL,
-+			AUX_SW_START_DELAY);
-+
-+		/* The length include
-+		 * the 4 bit header and the 20 bit address
-+		 * (that is 3 byte).
-+		 * If the requested length is non zero this means
-+		 * an addition byte specifying the length is required. */
-+
-+		length = request->length ? 4 : 3;
-+		if (is_write)
-+			length += request->length;
-+
-+		set_reg_field_value(
-+			value,
-+			length,
-+			AUX_SW_CONTROL,
-+			AUX_SW_WR_BYTES);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	/* program action and address and payload data (if 'is_write') */
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_sw_data;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_INDEX);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_DATA_RW);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_DATA,
-+			AUX_SW_AUTOINCREMENT_DISABLE);
-+
-+		set_reg_field_value(
-+			value,
-+			COMPOSE_AUX_SW_DATA_16_20(
-+				request->action, request->address),
-+			AUX_SW_DATA,
-+			AUX_SW_DATA);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_AUTOINCREMENT_DISABLE);
-+
-+		set_reg_field_value(
-+			value,
-+			COMPOSE_AUX_SW_DATA_8_15(request->address),
-+			AUX_SW_DATA,
-+			AUX_SW_DATA);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			COMPOSE_AUX_SW_DATA_0_7(request->address),
-+			AUX_SW_DATA,
-+			AUX_SW_DATA);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		if (request->length) {
-+			set_reg_field_value(
-+				value,
-+				request->length - 1,
-+				AUX_SW_DATA,
-+				AUX_SW_DATA);
-+
-+			dal_write_reg(engine->base.ctx, addr, value);
-+		}
-+
-+		if (is_write) {
-+			/* Load the HW buffer with the Data to be sent.
-+			 * This is relevant for write operation.
-+			 * For read, the data recived data will be
-+			 * processed in process_channel_reply(). */
-+			uint32_t i = 0;
-+
-+			while (i < request->length) {
-+
-+				set_reg_field_value(
-+					value,
-+					request->data[i],
-+					AUX_SW_DATA,
-+					AUX_SW_DATA);
-+
-+				dal_write_reg(
-+					engine->base.ctx, addr, value);
-+
-+				++i;
-+			}
-+		}
-+	}
-+
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_interrupt_control;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_INTERRUPT_CONTROL,
-+			AUX_SW_DONE_ACK);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_sw_control;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_CONTROL,
-+			AUX_SW_GO);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+	}
-+}
-+
-+static void process_channel_reply(
-+	struct aux_engine *engine,
-+	struct aux_reply_transaction_data *reply)
-+{
-+	struct aux_engine_dce110 *aux_engine = FROM_AUX_ENGINE(engine);
-+
-+	/* Need to do a read to get the number of bytes to process
-+	 * Alternatively, this information can be passed -
-+	 * but that causes coupling which isn't good either. */
-+
-+	uint32_t bytes_replied;
-+	uint32_t value;
-+
-+	{
-+		const uint32_t addr = aux_engine->addr.aux_sw_status;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		bytes_replied = get_reg_field_value(
-+				value,
-+				AUX_SW_STATUS,
-+				AUX_SW_REPLY_BYTE_COUNT);
-+	}
-+
-+	if (bytes_replied) {
-+		uint32_t reply_result;
-+
-+		const uint32_t addr = aux_engine->addr.aux_sw_data;
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_INDEX);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_DATA,
-+			AUX_SW_AUTOINCREMENT_DISABLE);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_DATA,
-+			AUX_SW_DATA_RW);
-+
-+		dal_write_reg(engine->base.ctx, addr, value);
-+
-+		value = dal_read_reg(engine->base.ctx, addr);
-+
-+		reply_result = get_reg_field_value(
-+				value,
-+				AUX_SW_DATA,
-+				AUX_SW_DATA);
-+
-+		reply_result = reply_result >> 4;
-+
-+		switch (reply_result) {
-+		case 0: /* ACK */ {
-+			uint32_t i = 0;
-+
-+			/* first byte was already used
-+			 * to get the command status */
-+			--bytes_replied;
-+
-+			while (i < bytes_replied) {
-+				value = dal_read_reg(
-+					engine->base.ctx, addr);
-+
-+				reply->data[i] = get_reg_field_value(
-+						value,
-+						AUX_SW_DATA,
-+						AUX_SW_DATA);
-+
-+				++i;
-+			}
-+
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
-+		}
-+		break;
-+		case 1: /* NACK */
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
-+		break;
-+		case 2: /* DEFER */
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
-+		break;
-+		case 4: /* AUX ACK / I2C NACK */
-+			reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
-+		break;
-+		case 8: /* AUX ACK / I2C DEFER */
-+			reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
-+		break;
-+		default:
-+			reply->status = AUX_TRANSACTION_REPLY_INVALID;
-+		}
-+	} else {
-+		/* Need to handle an error case...
-+		 * hopefully, upper layer function won't call this function
-+		 * if the number of bytes in the reply was 0
-+		 * because there was surely an error that was asserted
-+		 * that should have been handled
-+		 * for hot plug case, this could happens*/
-+		if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-+			ASSERT_CRITICAL(false);
-+	}
-+}
-+
-+static enum aux_channel_operation_result get_channel_status(
-+	struct aux_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	struct aux_engine_dce110 *aux_engine = FROM_AUX_ENGINE(engine);
-+
-+	const uint32_t addr = aux_engine->addr.aux_sw_status;
-+
-+	uint32_t value;
-+	uint32_t aux_sw_done;
-+
-+	if (returned_bytes == NULL) {
-+		/*caller pass NULL pointer*/
-+		ASSERT_CRITICAL(false);
-+		return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN;
-+	}
-+	*returned_bytes = 0;
-+
-+	/* poll to make sure that SW_DONE is asserted */
-+	{
-+		uint32_t time_elapsed = 0;
-+
-+		do {
-+			value = dal_read_reg(engine->base.ctx, addr);
-+
-+			aux_sw_done = get_reg_field_value(
-+					value,
-+					AUX_SW_STATUS,
-+					AUX_SW_DONE);
-+
-+			if (aux_sw_done)
-+				break;
-+
-+			dc_service_delay_in_microseconds(engine->base.ctx, 10);
-+
-+			time_elapsed += 10;
-+		} while (time_elapsed < aux_engine->timeout_period);
-+
-+
-+	}
-+
-+	/* Note that the following bits are set in 'status.bits'
-+	 * during CTS 4.2.1.2:
-+	 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
-+	 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
-+	 *
-+	 * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
-+	 * HW debugging bit and should be ignored. */
-+	if (aux_sw_done) {
-+		if (get_reg_field_value(
-+			value,
-+			AUX_SW_STATUS,
-+			AUX_SW_RX_TIMEOUT_STATE) ||
-+			get_reg_field_value(
-+				value,
-+				AUX_SW_STATUS,
-+				AUX_SW_RX_TIMEOUT))
-+			return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-+		else if (get_reg_field_value(
-+			value,
-+			AUX_SW_STATUS,
-+			AUX_SW_RX_INVALID_STOP))
-+			return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-+
-+		*returned_bytes = get_reg_field_value(
-+				value,
-+				AUX_SW_STATUS,
-+				AUX_SW_REPLY_BYTE_COUNT);
-+		if (*returned_bytes == 0)
-+			return
-+			AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-+		else {
-+			*returned_bytes -= 1;
-+			return AUX_CHANNEL_OPERATION_SUCCEEDED;
-+		}
-+	} else {
-+		/*time_elapsed >= aux_engine->timeout_period */
-+		if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-+			ASSERT_CRITICAL(false);
-+		return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-+	}
-+}
-+
-+static const int32_t aux_channel_offset[] = {
-+	mmDP_AUX0_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX1_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX2_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX3_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX4_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX5_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL
-+};
-+
-+static const struct aux_engine_funcs aux_engine_funcs = {
-+	.destroy = destroy,
-+	.acquire_engine = acquire_engine,
-+	.configure = configure,
-+	.start_gtc_sync = start_gtc_sync,
-+	.stop_gtc_sync = stop_gtc_sync,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.submit_request = dal_aux_engine_submit_request,
-+	.keep_power_up_count = dal_i2caux_keep_power_up_count,
-+	.get_engine_type = dal_aux_engine_get_engine_type,
-+	.acquire = dal_aux_engine_acquire,
-+};
-+
-+static bool construct(
-+	struct aux_engine_dce110 *engine,
-+	const struct aux_engine_dce110_init_data *aux_init_data)
-+{
-+	int32_t offset;
-+
-+	if (aux_init_data->engine_id >=
-+		sizeof(aux_channel_offset) / sizeof(int32_t)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	if (!dal_aux_engine_construct(
-+		&engine->base, aux_init_data->ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+	engine->base.base.funcs = &engine_funcs;
-+	engine->base.funcs = &aux_engine_funcs;
-+	offset = aux_channel_offset[aux_init_data->engine_id];
-+	engine->addr.aux_control = mmAUX_CONTROL + offset;
-+	engine->addr.aux_arb_control = mmAUX_ARB_CONTROL + offset;
-+	engine->addr.aux_sw_data = mmAUX_SW_DATA + offset;
-+	engine->addr.aux_sw_control = mmAUX_SW_CONTROL + offset;
-+	engine->addr.aux_interrupt_control = mmAUX_INTERRUPT_CONTROL + offset;
-+	engine->addr.aux_sw_status = mmAUX_SW_STATUS + offset;
-+	engine->addr.aux_gtc_sync_control = mmAUX_GTC_SYNC_CONTROL + offset;
-+	engine->addr.aux_gtc_sync_status = mmAUX_GTC_SYNC_STATUS + offset;
-+	engine->addr.aux_gtc_sync_controller_status =
-+		mmAUX_GTC_SYNC_CONTROLLER_STATUS + offset;
-+
-+	engine->timeout_period = aux_init_data->timeout_period;
-+
-+	return true;
-+}
-+
-+static void destruct(
-+	struct aux_engine_dce110 *engine)
-+{
-+	dal_aux_engine_destruct(&engine->base);
-+}
-+
-+struct aux_engine *dal_aux_engine_dce110_create(
-+	const struct aux_engine_dce110_init_data *aux_init_data)
-+{
-+	struct aux_engine_dce110 *engine;
-+
-+	if (!aux_init_data) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	engine = dc_service_alloc(aux_init_data->ctx, sizeof(*engine));
-+
-+	if (!engine) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(engine, aux_init_data))
-+		return &engine->base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(aux_init_data->ctx, engine);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h
-new file mode 100644
-index 0000000..ec6899e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h
-@@ -0,0 +1,56 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUX_ENGINE_DCE110_H__
-+#define __DAL_AUX_ENGINE_DCE110_H__
-+
-+#include "../aux_engine.h"
-+
-+struct aux_engine_dce110 {
-+	struct aux_engine base;
-+	struct {
-+		uint32_t aux_control;
-+		uint32_t aux_arb_control;
-+		uint32_t aux_sw_data;
-+		uint32_t aux_sw_control;
-+		uint32_t aux_interrupt_control;
-+		uint32_t aux_sw_status;
-+		uint32_t aux_gtc_sync_control;
-+		uint32_t aux_gtc_sync_status;
-+		uint32_t aux_gtc_sync_controller_status;
-+	} addr;
-+	uint32_t timeout_period;
-+};
-+
-+struct aux_engine_dce110_init_data {
-+	uint32_t engine_id;
-+	uint32_t timeout_period;
-+	struct dc_context *ctx;
-+};
-+
-+struct aux_engine *dal_aux_engine_dce110_create(
-+	const struct aux_engine_dce110_init_data *aux_init_data);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
-new file mode 100644
-index 0000000..e6b6a97
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
-@@ -0,0 +1,25 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-new file mode 100644
-index 0000000..17e89ce
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-@@ -0,0 +1,954 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+#include "include/logger_interface.h"
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_hw_engine.h"
-+#include "../i2c_generic_hw_engine.h"
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_hw_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+enum dc_i2c_status {
-+	DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-+};
-+
-+enum dc_i2c_arbitration {
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-+};
-+
-+enum {
-+	/* No timeout in HW
-+	 * (timeout implemented in SW by querying status) */
-+	I2C_SETUP_TIME_LIMIT = 255,
-+	I2C_HW_BUFFER_SIZE = 144
-+};
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct i2c_hw_engine *'
-+ * to pointer 'struct i2c_hw_engine_dce110 *'
-+ */
-+#define FROM_I2C_HW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_hw_engine_dce110, base)
-+/*
-+ * @brief
-+ * Cast pointer to 'struct i2c_engine *'
-+ * to pointer to 'struct i2c_hw_engine_dce110 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct engine *'
-+ * to 'pointer to struct i2c_hw_engine_dce110 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+
-+static void disable_i2c_hw_engine(
-+	struct i2c_hw_engine_dce110 *engine)
-+{
-+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+	uint32_t value = 0;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_ENABLE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_engine *base = NULL;
-+	bool safe_to_reset;
-+	uint32_t value = 0;
-+
-+	base = &hw_engine->base.base;
-+
-+	/* Restore original HW engine speed */
-+
-+	base->funcs->set_speed(base, hw_engine->base.original_speed);
-+
-+	/* Release I2C */
-+	{
-+		value = dal_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
-+
-+		set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_ARBITRATION,
-+				DC_I2C_SW_DONE_USING_I2C_REG);
-+
-+		dal_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
-+	}
-+
-+	/* Reset HW engine */
-+	{
-+		uint32_t i2c_sw_status = 0;
-+
-+		value = dal_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+		i2c_sw_status = get_reg_field_value(
-+				value,
-+				DC_I2C_SW_STATUS,
-+				DC_I2C_SW_STATUS);
-+		/* if used by SW, safe to reset */
-+		safe_to_reset = (i2c_sw_status == 1);
-+	}
-+	{
-+		value = dal_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+
-+		if (safe_to_reset)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_CONTROL,
-+				DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		dal_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+	}
-+
-+	/* HW I2c engine - clock gating feature */
-+	if (!hw_engine->engine_keep_power_up_count)
-+		disable_i2c_hw_engine(hw_engine);
-+}
-+
-+static void keep_power_up_count(
-+	struct engine *engine,
-+	bool keep_power_up)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-+
-+	if (keep_power_up)
-+		++hw_engine->engine_keep_power_up_count;
-+	else {
-+		--hw_engine->engine_keep_power_up_count;
-+
-+		if (!hw_engine->engine_keep_power_up_count)
-+			disable_i2c_hw_engine(hw_engine);
-+	}
-+}
-+
-+static bool setup_engine(
-+	struct i2c_engine *i2c_engine)
-+{
-+	uint32_t value = 0;
-+	struct i2c_hw_engine_dce110 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	/* Program pin select */
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value = dal_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SEND_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_TRANSACTION_COUNT);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->engine_id,
-+			DC_I2C_CONTROL,
-+			DC_I2C_DDC_SELECT);
-+
-+
-+		dal_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+
-+	/* Program time limit */
-+	{
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+
-+		value = dal_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			I2C_SETUP_TIME_LIMIT,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_TIME_LIMIT);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_ENABLE);
-+
-+		dal_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+
-+	/* Program HW priority
-+	 * set to High - interrupt software I2C at any time
-+	 * Enable restart of SW I2C that was interrupted by HW
-+	 * disable queuing of software while I2C is in use by HW */
-+	{
-+		value = dal_read_reg(i2c_engine->base.ctx,
-+				mmDC_I2C_ARBITRATION);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_NO_QUEUED_SW_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_SW_PRIORITY);
-+
-+		dal_write_reg(i2c_engine->base.ctx,
-+				mmDC_I2C_ARBITRATION, value);
-+	}
-+
-+	return true;
-+}
-+
-+static uint32_t get_speed(
-+	const struct i2c_engine *i2c_engine)
-+{
-+	const struct i2c_hw_engine_dce110 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-+
-+	uint32_t pre_scale = 0;
-+
-+	uint32_t value = dal_read_reg(i2c_engine->base.ctx, addr);
-+
-+	pre_scale = get_reg_field_value(
-+			value,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_PRESCALE);
-+
-+	/* [anaumov] it seems following is unnecessary */
-+	/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-+
-+	return pre_scale ?
-+		engine->reference_frequency / pre_scale :
-+		engine->base.default_speed;
-+}
-+
-+static void set_speed(
-+	struct i2c_engine *i2c_engine,
-+	uint32_t speed)
-+{
-+	struct i2c_hw_engine_dce110 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	if (speed) {
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-+
-+		uint32_t value = dal_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->reference_frequency / speed,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_PRESCALE);
-+
-+		set_reg_field_value(
-+			value,
-+			2,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_THRESHOLD);
-+
-+		/*DCE11, HW add 100Khz support for I2c*/
-+		if (speed > 50) {
-+			set_reg_field_value(
-+				value,
-+				2,
-+				DC_I2C_DDC1_SPEED,
-+				DC_I2C_DDC1_START_STOP_TIMING_CNTL);
-+		} else {
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_DDC1_SPEED,
-+				DC_I2C_DDC1_START_STOP_TIMING_CNTL);
-+		}
-+
-+		dal_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+}
-+
-+static inline void reset_hw_engine(struct engine *engine)
-+{
-+	uint32_t value = dal_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_CONTROL,
-+		DC_I2C_SOFT_RESET);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_CONTROL,
-+		DC_I2C_SW_STATUS_RESET);
-+
-+	dal_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+}
-+
-+static bool is_hw_busy(struct engine *engine)
-+{
-+	uint32_t i2c_sw_status = 0;
-+
-+	uint32_t value = dal_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-+		return false;
-+
-+	reset_hw_engine(engine);
-+
-+	value = dal_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-+}
-+
-+/*
-+ * @brief
-+ * DC_GPIO_DDC MM register offsets
-+ */
-+static const uint32_t transaction_addr[] = {
-+	mmDC_I2C_TRANSACTION0,
-+	mmDC_I2C_TRANSACTION1,
-+	mmDC_I2C_TRANSACTION2,
-+	mmDC_I2C_TRANSACTION3
-+};
-+
-+static bool process_transaction(
-+	struct i2c_hw_engine_dce110 *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	uint8_t length = request->length;
-+	uint8_t *buffer = request->data;
-+
-+	bool last_transaction = false;
-+	uint32_t value = 0;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	{
-+		const uint32_t addr =
-+			transaction_addr[engine->transaction_count];
-+
-+		value = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_STOP_ON_NACK0);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_START0);
-+
-+
-+		if ((engine->transaction_count == 3) ||
-+		(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_TRANSACTION0,
-+				DC_I2C_STOP0);
-+
-+			last_transaction = true;
-+		} else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_TRANSACTION0,
-+				DC_I2C_STOP0);
-+
-+		set_reg_field_value(
-+			value,
-+			(0 != (request->action &
-+					I2CAUX_TRANSACTION_ACTION_I2C_READ)),
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_RW0);
-+
-+		set_reg_field_value(
-+			value,
-+			length,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_COUNT0);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* Write the I2C address and I2C data
-+	 * into the hardware circular buffer, one byte per entry.
-+	 * As an example, the 7-bit I2C slave address for CRT monitor
-+	 * for reading DDC/EDID information is 0b1010001.
-+	 * For an I2C send operation, the LSB must be programmed to 0;
-+	 * for I2C receive operation, the LSB must be programmed to 1. */
-+
-+	{
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			false,
-+			DC_I2C_DATA,
-+			DC_I2C_DATA_RW);
-+
-+		set_reg_field_value(
-+			value,
-+			request->address,
-+			DC_I2C_DATA,
-+			DC_I2C_DATA);
-+
-+		if (engine->transaction_count == 0) {
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX);
-+
-+			/*enable index write*/
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX_WRITE);
-+
-+			engine->buffer_used_write = 0;
-+		}
-+
-+		dal_write_reg(ctx, mmDC_I2C_DATA, value);
-+
-+		engine->buffer_used_write++;
-+
-+		if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX_WRITE);
-+
-+			while (length) {
-+
-+				set_reg_field_value(
-+					value,
-+					*buffer++,
-+					DC_I2C_DATA,
-+					DC_I2C_DATA);
-+
-+				dal_write_reg(ctx, mmDC_I2C_DATA, value);
-+
-+				engine->buffer_used_write++;
-+				--length;
-+			}
-+		}
-+	}
-+
-+	++engine->transaction_count;
-+	engine->buffer_used_bytes += length + 1;
-+
-+	return last_transaction;
-+}
-+
-+static void execute_transaction(
-+	struct i2c_hw_engine_dce110 *engine)
-+{
-+	uint32_t value = 0;
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	{
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+
-+		value = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_DATA_DRIVE_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_CLK_DRIVE_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_DATA_DRIVE_SEL);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_INTRA_BYTE_DELAY);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SEND_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->transaction_count - 1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_TRANSACTION_COUNT);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* start I2C transfer */
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value	= dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		dal_write_reg(ctx, addr, value);
-+	}
-+
-+	/* all transactions were executed and HW buffer became empty
-+	 * (even though it actually happens when status becomes DONE) */
-+	engine->transaction_count = 0;
-+	engine->buffer_used_bytes = 0;
-+}
-+
-+static void submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	if (!process_transaction(FROM_I2C_ENGINE(engine), request))
-+		return;
-+
-+	if (is_hw_busy(&engine->base)) {
-+		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+		return;
-+	}
-+
-+	execute_transaction(FROM_I2C_ENGINE(engine));
-+}
-+
-+static void process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply)
-+{
-+	uint8_t length = reply->length;
-+	uint8_t *buffer = reply->data;
-+
-+	struct i2c_hw_engine_dce110 *i2c_hw_engine_dce110 =
-+		FROM_I2C_ENGINE(engine);
-+
-+	uint32_t value = 0;
-+
-+	/*set index*/
-+	set_reg_field_value(
-+		value,
-+		i2c_hw_engine_dce110->buffer_used_write,
-+		DC_I2C_DATA,
-+		DC_I2C_INDEX);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_DATA,
-+		DC_I2C_DATA_RW);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_DATA,
-+		DC_I2C_INDEX_WRITE);
-+
-+	dal_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
-+
-+	while (length) {
-+		/* after reading the status,
-+		 * if the I2C operation executed successfully
-+		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
-+		 * should read data bytes from I2C circular data buffer */
-+
-+		value = dal_read_reg(engine->base.ctx, mmDC_I2C_DATA);
-+
-+		*buffer++ = get_reg_field_value(
-+				value,
-+				DC_I2C_DATA,
-+				DC_I2C_DATA);
-+
-+		--length;
-+	}
-+}
-+
-+static enum i2c_channel_operation_result get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	uint32_t i2c_sw_status = 0;
-+	uint32_t value = dal_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
-+		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
-+		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
-+		return I2C_CHANNEL_OPERATION_TIMEOUT;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
-+		return I2C_CHANNEL_OPERATION_FAILED;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
-+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	/* in DAL2, I2C_RESULT_OK was returned */
-+	return I2C_CHANNEL_OPERATION_NOT_STARTED;
-+}
-+
-+static uint8_t get_hw_buffer_available_size(
-+	const struct i2c_hw_engine *engine)
-+{
-+	return I2C_HW_BUFFER_SIZE -
-+		FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-+}
-+
-+static uint32_t get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length)
-+{
-+	uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-+
-+	uint32_t period_timeout;
-+	uint32_t num_of_clock_stretches;
-+
-+	if (!speed)
-+		return 0;
-+
-+	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-+
-+	num_of_clock_stretches = 1 + (length << 3) + 1;
-+	num_of_clock_stretches +=
-+		(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
-+		(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-+
-+	return period_timeout * num_of_clock_stretches;
-+}
-+
-+static void destroy(
-+	struct i2c_engine **i2c_engine)
-+{
-+	struct i2c_hw_engine_dce110 *engine_dce110 =
-+			FROM_I2C_ENGINE(*i2c_engine);
-+
-+	dal_i2c_hw_engine_destruct(&engine_dce110->base);
-+
-+	dc_service_free((*i2c_engine)->base.ctx, engine_dce110);
-+
-+	*i2c_engine = NULL;
-+}
-+/*
-+ * @brief
-+ * DC_I2C_DDC1_SETUP MM register offsets
-+ *
-+ * @note
-+ * The indices of this offset array are DDC engine IDs
-+ */
-+static const int32_t ddc_setup_offset[] = {
-+
-+	mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
-+	mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
-+	mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
-+	mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
-+	mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
-+	mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
-+	mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
-+};
-+
-+/*
-+ * @brief
-+ * DC_I2C_DDC1_SPEED MM register offsets
-+ *
-+ * @note
-+ * The indices of this offset array are DDC engine IDs
-+ */
-+static const int32_t ddc_speed_offset[] = {
-+	mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
-+	mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
-+	mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
-+	mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
-+	mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
-+	mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
-+	mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
-+};
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.destroy = destroy,
-+	.get_speed = get_speed,
-+	.set_speed = set_speed,
-+	.setup_engine = setup_engine,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+	.acquire_engine = dal_i2c_hw_engine_acquire_engine,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.keep_power_up_count = keep_power_up_count,
-+	.get_engine_type = dal_i2c_hw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_hw_engine_submit_request,
-+};
-+
-+static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
-+	.get_hw_buffer_available_size = get_hw_buffer_available_size,
-+	.get_transaction_timeout = get_transaction_timeout,
-+	.wait_on_operation_result = dal_i2c_hw_engine_wait_on_operation_result,
-+};
-+
-+static bool construct(
-+	struct i2c_hw_engine_dce110 *engine_dce110,
-+	const struct i2c_hw_engine_dce110_create_arg *arg)
-+{
-+	uint32_t xtal_ref_div = 0;
-+	uint32_t value = 0;
-+
-+	/*ddc_setup_offset of dce80 and dce110 have the same register name
-+	 * but different offset. Do not need different array*/
-+	if (arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t))
-+		return false;
-+	if (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t))
-+		return false;
-+	if (!arg->reference_frequency)
-+		return false;
-+
-+	if (!dal_i2c_hw_engine_construct(&engine_dce110->base, arg->ctx))
-+		return false;
-+
-+	engine_dce110->base.base.base.funcs = &engine_funcs;
-+	engine_dce110->base.base.funcs = &i2c_engine_funcs;
-+	engine_dce110->base.funcs = &i2c_hw_engine_funcs;
-+	engine_dce110->base.default_speed = arg->default_speed;
-+
-+	engine_dce110->engine_id = arg->engine_id;
-+
-+	engine_dce110->buffer_used_bytes = 0;
-+	engine_dce110->transaction_count = 0;
-+	engine_dce110->engine_keep_power_up_count = 1;
-+
-+	/*values which are not included by arg*/
-+	engine_dce110->addr.DC_I2C_DDCX_SETUP =
-+		mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
-+	engine_dce110->addr.DC_I2C_DDCX_SPEED =
-+		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
-+
-+
-+	value = dal_read_reg(
-+		engine_dce110->base.base.base.ctx,
-+		mmMICROSECOND_TIME_BASE_DIV);
-+
-+	xtal_ref_div = get_reg_field_value(
-+			value,
-+			MICROSECOND_TIME_BASE_DIV,
-+			XTAL_REF_DIV);
-+
-+	if (xtal_ref_div == 0) {
-+		dal_logger_write(
-+				engine_dce110->base.base.base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_I2C_AUX,
-+				"Invalid base timer divider\n",
-+				__func__);
-+		xtal_ref_div = 2;
-+	}
-+
-+	/*Calculating Reference Clock by divding original frequency by
-+	 * XTAL_REF_DIV.
-+	 * At upper level, uint32_t reference_frequency =
-+	 *  dal_i2caux_get_reference_clock(as) >> 1
-+	 *  which already divided by 2. So we need x2 to get original
-+	 *  reference clock from ppll_info
-+	 */
-+	engine_dce110->reference_frequency =
-+		(arg->reference_frequency * 2) / xtal_ref_div;
-+
-+
-+	return true;
-+}
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce110_create(
-+	const struct i2c_hw_engine_dce110_create_arg *arg)
-+{
-+	struct i2c_hw_engine_dce110 *engine_dce10;
-+
-+	if (!arg) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	engine_dce10 = dc_service_alloc(arg->ctx, sizeof(struct i2c_hw_engine_dce110));
-+
-+	if (!engine_dce10) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(engine_dce10, arg))
-+		return &engine_dce10->base.base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(arg->ctx, engine_dce10);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h
-new file mode 100644
-index 0000000..fc2ae36
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h
-@@ -0,0 +1,58 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_HW_ENGINE_DCE110_H__
-+#define __DAL_I2C_HW_ENGINE_DCE110_H__
-+
-+struct i2c_hw_engine_dce110 {
-+	struct i2c_hw_engine base;
-+	struct {
-+		uint32_t DC_I2C_DDCX_SETUP;
-+		uint32_t DC_I2C_DDCX_SPEED;
-+	} addr;
-+	uint32_t engine_id;
-+	/* expressed in kilohertz */
-+	uint32_t reference_frequency;
-+	/* number of bytes currently used in HW buffer */
-+	uint32_t buffer_used_bytes;
-+	/* number of bytes used for write transaction in HW buffer
-+	 * - this will be used as the index to read from*/
-+	uint32_t buffer_used_write;
-+	/* number of pending transactions (before GO) */
-+	uint32_t transaction_count;
-+	uint32_t engine_keep_power_up_count;
-+};
-+
-+struct i2c_hw_engine_dce110_create_arg {
-+	uint32_t engine_id;
-+	uint32_t reference_frequency;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce110_create(
-+	const struct i2c_hw_engine_dce110_create_arg *arg);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-new file mode 100644
-index 0000000..c415a4e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-@@ -0,0 +1,172 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_sw_engine_dce110.h"
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_sw_engine *'
-+ * to 'struct i2c_sw_engine_dce110 *'
-+ */
-+#define FROM_I2C_SW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_sw_engine_dce110, base)
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+}
-+
-+static void destruct(
-+	struct i2c_sw_engine_dce110 *engine)
-+{
-+	dal_i2c_sw_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **engine)
-+{
-+	struct i2c_sw_engine_dce110 *sw_engine = FROM_I2C_ENGINE(*engine);
-+
-+	destruct(sw_engine);
-+
-+	dc_service_free((*engine)->base.ctx, sw_engine);
-+
-+	*engine = NULL;
-+}
-+
-+static bool acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc_handle)
-+{
-+	return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.acquire_engine = acquire_engine,
-+	.destroy = destroy,
-+	.get_speed = dal_i2c_sw_engine_get_speed,
-+	.set_speed = dal_i2c_sw_engine_set_speed,
-+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
-+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
-+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_sw_engine_submit_request,
-+	.keep_power_up_count = dal_i2caux_keep_power_up_count,
-+};
-+
-+static bool construct(
-+	struct i2c_sw_engine_dce110 *engine_dce110,
-+	const struct i2c_sw_engine_dce110_create_arg *arg_dce110)
-+{
-+	struct i2c_sw_engine_create_arg arg_base;
-+
-+	arg_base.ctx = arg_dce110->ctx;
-+	arg_base.default_speed = arg_dce110->default_speed;
-+
-+	if (!dal_i2c_sw_engine_construct(
-+			&engine_dce110->base, &arg_base)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	/*struct engine   struct engine_funcs*/
-+	engine_dce110->base.base.base.funcs = &engine_funcs;
-+	/*struct i2c_engine  struct i2c_engine_funcs*/
-+	engine_dce110->base.base.funcs = &i2c_engine_funcs;
-+	engine_dce110->base.default_speed = arg_dce110->default_speed;
-+	engine_dce110->engine_id = arg_dce110->engine_id;
-+
-+	return true;
-+}
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce110_create(
-+	const struct i2c_sw_engine_dce110_create_arg *arg)
-+{
-+	struct i2c_sw_engine_dce110 *engine_dce110;
-+
-+	if (!arg) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	engine_dce110 = dc_service_alloc(arg->ctx, sizeof(struct i2c_sw_engine_dce110));
-+
-+	if (!engine_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(engine_dce110, arg))
-+		return &engine_dce110->base.base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(arg->ctx, engine_dce110);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h
-new file mode 100644
-index 0000000..c48c61f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_SW_ENGINE_DCE110_H__
-+#define __DAL_I2C_SW_ENGINE_DCE110_H__
-+
-+struct i2c_sw_engine_dce110 {
-+	struct i2c_sw_engine base;
-+	uint32_t engine_id;
-+};
-+
-+struct i2c_sw_engine_dce110_create_arg {
-+	uint32_t engine_id;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce110_create(
-+	const struct i2c_sw_engine_dce110_create_arg *arg);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-new file mode 100644
-index 0000000..71d1a6c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-@@ -0,0 +1,260 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "i2caux_dce110.h"
-+#include "i2c_sw_engine_dce110.h"
-+#include "i2c_hw_engine_dce110.h"
-+#include "aux_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+/*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
-+#define FROM_I2C_AUX(ptr) \
-+	container_of((ptr), struct i2caux_dce110, base)
-+
-+static void destruct(
-+	struct i2caux_dce110 *i2caux_dce110)
-+{
-+	dal_i2caux_destruct(&i2caux_dce110->base);
-+}
-+
-+static void destroy(
-+	struct i2caux **i2c_engine)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
-+
-+	destruct(i2caux_dce110);
-+
-+	dc_service_free((*i2c_engine)->ctx, i2caux_dce110);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static struct i2c_engine *acquire_i2c_hw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-+
-+	struct i2c_engine *engine = NULL;
-+	/* generic hw engine is not used for EDID read
-+	 * It may be needed for external i2c device, like thermal chip,
-+	 * TODO will be implemented when needed.
-+	 * check dce80 bool non_generic for generic hw engine;
-+	 */
-+
-+	if (!ddc)
-+		return NULL;
-+
-+	if (dal_ddc_is_hw_supported(ddc)) {
-+		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-+
-+		if (line < GPIO_DDC_LINE_COUNT)
-+			engine = i2caux->i2c_hw_engines[line];
-+	}
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (!i2caux_dce110->i2c_hw_buffer_in_use &&
-+		engine->base.funcs->acquire(&engine->base, ddc)) {
-+		i2caux_dce110->i2c_hw_buffer_in_use = true;
-+		return engine;
-+	}
-+
-+	return NULL;
-+}
-+
-+static void release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-+
-+	if (engine->funcs->get_engine_type(engine) ==
-+		I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
-+		i2caux_dce110->i2c_hw_buffer_in_use = false;
-+
-+	dal_i2caux_release_engine(i2caux, engine);
-+}
-+
-+static const enum gpio_ddc_line hw_ddc_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+};
-+
-+static const enum gpio_ddc_line hw_aux_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+};
-+
-+/* function table */
-+static const struct i2caux_funcs i2caux_funcs = {
-+	.destroy = destroy,
-+	.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
-+	.release_engine = release_engine,
-+	.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
-+	.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-+};
-+
-+static bool construct(
-+	struct i2caux_dce110 *i2caux_dce110,
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	uint32_t i = 0;
-+	uint32_t reference_frequency = 0;
-+	bool use_i2c_sw_engine = false;
-+	struct i2caux *base = NULL;
-+	/*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
-+	 * does not return 48KHz, we need hard coded for 48Khz.
-+	 * Some BIOS setting incorrect cause this
-+	 * For production, we always get value from BIOS*/
-+	reference_frequency =
-+		dal_i2caux_get_reference_clock(as) >> 1;
-+
-+	use_i2c_sw_engine = dal_adapter_service_is_feature_supported(
-+		FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);
-+
-+	base = &i2caux_dce110->base;
-+
-+	if (!dal_i2caux_construct(base, as, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	i2caux_dce110->base.funcs = &i2caux_funcs;
-+	i2caux_dce110->i2c_hw_buffer_in_use = false;
-+	/* Create I2C engines (DDC lines per connector)
-+	 * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
-+	 */
-+	do {
-+		enum gpio_ddc_line line_id = hw_ddc_lines[i];
-+
-+		struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
-+
-+		if (use_i2c_sw_engine) {
-+			struct i2c_sw_engine_dce110_create_arg sw_arg;
-+
-+			sw_arg.engine_id = i;
-+			sw_arg.default_speed = base->default_i2c_sw_speed;
-+			sw_arg.ctx = ctx;
-+			base->i2c_sw_engines[line_id] =
-+				dal_i2c_sw_engine_dce110_create(&sw_arg);
-+		}
-+
-+		hw_arg_dce110.engine_id = i;
-+		hw_arg_dce110.reference_frequency = reference_frequency;
-+		hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
-+		hw_arg_dce110.ctx = ctx;
-+
-+		base->i2c_hw_engines[line_id] =
-+			dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_ddc_lines));
-+
-+	/* Create AUX engines for all lines which has assisted HW AUX
-+	 * 'i' (loop counter) used as DDC/AUX engine_id */
-+
-+	i = 0;
-+
-+	do {
-+		enum gpio_ddc_line line_id = hw_aux_lines[i];
-+
-+		struct aux_engine_dce110_init_data aux_init_data;
-+
-+		aux_init_data.engine_id = i;
-+		aux_init_data.timeout_period = base->aux_timeout_period;
-+		aux_init_data.ctx = ctx;
-+
-+		base->aux_engines[line_id] =
-+			dal_aux_engine_dce110_create(&aux_init_data);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_aux_lines));
-+
-+	/*TODO Generic I2C SW and HW*/
-+
-+	return true;
-+}
-+
-+/*
-+ * dal_i2caux_dce110_create
-+ *
-+ * @brief
-+ * public interface to allocate memory for DCE11 I2CAUX
-+ *
-+ * @param
-+ * struct adapter_service *as - [in]
-+ * struct dc_context *ctx - [in]
-+ *
-+ * @return
-+ * pointer to the base struct of DCE11 I2CAUX
-+ */
-+struct i2caux *dal_i2caux_dce110_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 =
-+		dc_service_alloc(ctx, sizeof(struct i2caux_dce110));
-+
-+	if (!i2caux_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(i2caux_dce110, as, ctx))
-+		return &i2caux_dce110->base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, i2caux_dce110);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
-new file mode 100644
-index 0000000..1a7ba1b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE110_H__
-+#define __DAL_I2C_AUX_DCE110_H__
-+
-+struct i2caux_dce110 {
-+	struct i2caux base;
-+	/* indicate the I2C HW circular buffer is in use */
-+	bool i2c_hw_buffer_in_use;
-+};
-+
-+struct i2caux *dal_i2caux_dce110_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/engine.h b/drivers/gpu/drm/amd/dal/dc/i2caux/engine.h
-new file mode 100644
-index 0000000..d3635f8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/engine.h
-@@ -0,0 +1,129 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ENGINE_H__
-+#define __DAL_ENGINE_H__
-+
-+enum i2caux_transaction_operation {
-+	I2CAUX_TRANSACTION_READ,
-+	I2CAUX_TRANSACTION_WRITE
-+};
-+
-+enum i2caux_transaction_address_space {
-+	I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
-+	I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
-+};
-+
-+struct i2caux_transaction_payload {
-+	enum i2caux_transaction_address_space address_space;
-+	uint32_t address;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+enum i2caux_transaction_status {
-+	I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
-+	I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW
-+};
-+
-+struct i2caux_transaction_request {
-+	enum i2caux_transaction_operation operation;
-+	struct i2caux_transaction_payload payload;
-+	enum i2caux_transaction_status status;
-+};
-+
-+enum i2caux_engine_type {
-+	I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
-+	I2CAUX_ENGINE_TYPE_AUX,
-+	I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
-+	I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
-+	I2CAUX_ENGINE_TYPE_I2C_SW
-+};
-+
-+enum i2c_default_speed {
-+	I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
-+	I2CAUX_DEFAULT_I2C_SW_SPEED = 50
-+};
-+
-+enum i2caux_transaction_action {
-+	I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
-+	I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
-+	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
-+
-+	I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
-+	I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
-+	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
-+
-+	I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
-+	I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
-+};
-+
-+struct engine;
-+
-+struct engine_funcs {
-+	enum i2caux_engine_type (*get_engine_type)(
-+		const struct engine *engine);
-+	bool (*acquire)(
-+		struct engine *engine,
-+		struct ddc *ddc);
-+	bool (*submit_request)(
-+		struct engine *engine,
-+		struct i2caux_transaction_request *request,
-+		bool middle_of_transaction);
-+	/* [anaumov] Actually, following method is meaningful
-+	 * only in I2C HW engines */
-+	void (*keep_power_up_count)(
-+		struct engine *engine,
-+		bool keep_power_up);
-+	void (*release_engine)(
-+		struct engine *engine);
-+};
-+
-+struct engine {
-+	const struct engine_funcs *funcs;
-+	struct ddc *ddc;
-+	struct dc_context *ctx;
-+};
-+
-+bool dal_i2caux_construct_engine(
-+	struct engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2caux_destruct_engine(
-+	struct engine *engine);
-+
-+void dal_i2caux_keep_power_up_count(
-+	struct engine *engine,
-+	bool keep_power_up);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c b/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-new file mode 100644
-index 0000000..2f87a65
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-@@ -0,0 +1,68 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+void dal_i2caux_keep_power_up_count(
-+	struct engine *engine,
-+	bool keep_power_up)
-+{
-+
-+}
-+
-+bool dal_i2caux_construct_engine(
-+	struct engine *engine,
-+	struct dc_context *ctx)
-+{
-+	engine->ddc = NULL;
-+	engine->ctx = ctx;
-+	return true;
-+}
-+
-+void dal_i2caux_destruct_engine(
-+	struct engine *engine)
-+{
-+	/* nothing to do */
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-new file mode 100644
-index 0000000..78c7d61
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-@@ -0,0 +1,122 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_engine, base)
-+
-+bool dal_i2c_engine_acquire(
-+	struct engine *engine,
-+	struct ddc *ddc_handle)
-+{
-+	struct i2c_engine *i2c_engine = FROM_ENGINE(engine);
-+
-+	uint32_t counter = 0;
-+	bool result;
-+
-+	do {
-+		result = i2c_engine->funcs->acquire_engine(
-+			i2c_engine, ddc_handle);
-+
-+		if (result)
-+			break;
-+
-+		/* i2c_engine is busy by VBios, lets wait and retry */
-+
-+		dc_service_delay_in_microseconds(engine->ctx, 10);
-+
-+		++counter;
-+	} while (counter < 2);
-+
-+	if (result) {
-+		if (!i2c_engine->funcs->setup_engine(i2c_engine)) {
-+			engine->funcs->release_engine(engine);
-+			result = false;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+bool dal_i2c_engine_setup_i2c_engine(
-+	struct i2c_engine *engine)
-+{
-+	/* Derivative classes do not have to override this */
-+
-+	return true;
-+}
-+
-+void dal_i2c_engine_submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+
-+}
-+
-+void dal_i2c_engine_process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply)
-+{
-+
-+}
-+
-+bool dal_i2c_engine_construct(
-+	struct i2c_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_i2caux_construct_engine(&engine->base, ctx))
-+		return false;
-+
-+	engine->timeout_delay = 0;
-+	return true;
-+}
-+
-+void dal_i2c_engine_destruct(
-+	struct i2c_engine *engine)
-+{
-+	dal_i2caux_destruct_engine(&engine->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h
-new file mode 100644
-index 0000000..20299fd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h
-@@ -0,0 +1,113 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_ENGINE_H__
-+#define __DAL_I2C_ENGINE_H__
-+
-+enum i2c_channel_operation_result {
-+	I2C_CHANNEL_OPERATION_SUCCEEDED,
-+	I2C_CHANNEL_OPERATION_FAILED,
-+	I2C_CHANNEL_OPERATION_NOT_GRANTED,
-+	I2C_CHANNEL_OPERATION_IS_BUSY,
-+	I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
-+	I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
-+	I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
-+	I2C_CHANNEL_OPERATION_ENGINE_BUSY,
-+	I2C_CHANNEL_OPERATION_TIMEOUT,
-+	I2C_CHANNEL_OPERATION_NO_RESPONSE,
-+	I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
-+	I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
-+	I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
-+	I2C_CHANNEL_OPERATION_NOT_STARTED
-+};
-+
-+struct i2c_request_transaction_data {
-+	enum i2caux_transaction_action action;
-+	enum i2c_channel_operation_result status;
-+	uint8_t address;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+struct i2c_reply_transaction_data {
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+struct i2c_engine;
-+
-+struct i2c_engine_funcs {
-+	void (*destroy)(
-+		struct i2c_engine **ptr);
-+	uint32_t (*get_speed)(
-+		const struct i2c_engine *engine);
-+	void (*set_speed)(
-+		struct i2c_engine *engine,
-+		uint32_t speed);
-+	bool (*acquire_engine)(
-+		struct i2c_engine *engine,
-+		struct ddc *ddc);
-+	bool (*setup_engine)(
-+		struct i2c_engine *engine);
-+	void (*submit_channel_request)(
-+		struct i2c_engine *engine,
-+		struct i2c_request_transaction_data *request);
-+	void (*process_channel_reply)(
-+		struct i2c_engine *engine,
-+		struct i2c_reply_transaction_data *reply);
-+	enum i2c_channel_operation_result (*get_channel_status)(
-+		struct i2c_engine *engine,
-+		uint8_t *returned_bytes);
-+};
-+
-+struct i2c_engine {
-+	struct engine base;
-+	const struct i2c_engine_funcs *funcs;
-+	uint32_t timeout_delay;
-+};
-+
-+bool dal_i2c_engine_construct(
-+	struct i2c_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2c_engine_destruct(
-+	struct i2c_engine *engine);
-+
-+bool dal_i2c_engine_setup_i2c_engine(
-+	struct i2c_engine *engine);
-+
-+void dal_i2c_engine_submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request);
-+
-+void dal_i2c_engine_process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply);
-+
-+bool dal_i2c_engine_acquire(
-+	struct engine *ptr,
-+	struct ddc *ddc_handle);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-new file mode 100644
-index 0000000..d91e259
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-@@ -0,0 +1,287 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+#include "i2c_engine.h"
-+#include "i2c_hw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_generic_hw_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_hw_engine *'
-+ * to 'struct i2c_generic_hw_engine *'
-+ */
-+#define FROM_I2C_HW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_generic_hw_engine, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_generic_hw_engine *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_generic_hw_engine *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW;
-+}
-+
-+/*
-+ * @brief
-+ * Single transaction handling.
-+ * Since transaction may be bigger than HW buffer size,
-+ * it divides transaction to sub-transactions
-+ * and uses batch transaction feature of the engine.
-+ */
-+bool dal_i2c_generic_hw_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction)
-+{
-+	struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_hw_engine *base = &hw_engine->base;
-+
-+	uint8_t max_payload_size =
-+		base->funcs->get_hw_buffer_available_size(base);
-+
-+	bool initial_stop_bit = !middle_of_transaction;
-+
-+	struct i2c_generic_transaction_attributes attributes;
-+
-+	enum i2c_channel_operation_result operation_result =
-+		I2C_CHANNEL_OPERATION_FAILED;
-+
-+	bool result = false;
-+
-+	/* setup transaction initial properties */
-+
-+	uint8_t address = i2caux_request->payload.address;
-+	uint8_t *current_payload = i2caux_request->payload.data;
-+	uint8_t remaining_payload_size = i2caux_request->payload.length;
-+
-+	bool first_iteration = true;
-+
-+	if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+		attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+	else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+		attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+	else {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-+		return false;
-+	}
-+
-+	/* Do batch transaction.
-+	 * Divide read/write data into payloads which fit HW buffer size.
-+	 * 1. Single transaction:
-+	 *    start_bit = 1, stop_bit depends on session state, ack_on_read = 0;
-+	 * 2. Start of batch transaction:
-+	 *    start_bit = 1, stop_bit = 0, ack_on_read = 1;
-+	 * 3. Middle of batch transaction:
-+	 *    start_bit = 0, stop_bit = 0, ack_on_read = 1;
-+	 * 4. End of batch transaction:
-+	 *    start_bit = 0, stop_bit depends on session state, ack_on_read = 0.
-+	 * Session stop bit is set if 'middle_of_transaction' = 0. */
-+
-+	while (remaining_payload_size) {
-+		uint8_t current_transaction_size;
-+		uint8_t current_payload_size;
-+
-+		bool last_iteration;
-+		bool stop_bit;
-+
-+		/* Calculate current transaction size and payload size.
-+		 * Transaction size = total number of bytes in transaction,
-+		 * including slave's address;
-+		 * Payload size = number of data bytes in transaction. */
-+
-+		if (first_iteration) {
-+			/* In the first sub-transaction we send slave's address
-+			 * thus we need to reserve one byte for it */
-+			current_transaction_size =
-+			(remaining_payload_size > max_payload_size - 1) ?
-+				max_payload_size :
-+				remaining_payload_size + 1;
-+
-+			current_payload_size = current_transaction_size - 1;
-+		} else {
-+			/* Second and further sub-transactions will have
-+			 * entire buffer reserved for data */
-+			current_transaction_size =
-+				(remaining_payload_size > max_payload_size) ?
-+				max_payload_size :
-+				remaining_payload_size;
-+
-+			current_payload_size = current_transaction_size;
-+		}
-+
-+		last_iteration =
-+			(remaining_payload_size == current_payload_size);
-+
-+		stop_bit = last_iteration ? initial_stop_bit : false;
-+
-+		/* write slave device address */
-+
-+		if (first_iteration)
-+			hw_engine->funcs->write_address(hw_engine, address);
-+
-+		/* write current portion of data, if requested */
-+
-+		if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+			hw_engine->funcs->write_data(
-+				hw_engine,
-+				current_payload,
-+				current_payload_size);
-+
-+		/* execute transaction */
-+
-+		attributes.start_bit = first_iteration;
-+		attributes.stop_bit = stop_bit;
-+		attributes.last_read = last_iteration;
-+		attributes.transaction_size = current_transaction_size;
-+
-+		hw_engine->funcs->execute_transaction(hw_engine, &attributes);
-+
-+		/* wait until transaction is processed; if it fails - quit */
-+
-+		operation_result = base->funcs->wait_on_operation_result(
-+			base,
-+			base->funcs->get_transaction_timeout(
-+				base, current_transaction_size),
-+			I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-+
-+		if (operation_result != I2C_CHANNEL_OPERATION_SUCCEEDED)
-+			break;
-+
-+		/* read current portion of data, if requested */
-+
-+		/* the read offset should be 1 for first sub-transaction,
-+		 * and 0 for any next one */
-+
-+		if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+			hw_engine->funcs->read_data(hw_engine, current_payload,
-+				current_payload_size, first_iteration ? 1 : 0);
-+
-+		/* update loop variables */
-+
-+		first_iteration = false;
-+		current_payload += current_payload_size;
-+		remaining_payload_size -= current_payload_size;
-+	}
-+
-+	/* update transaction status */
-+
-+	switch (operation_result) {
-+	case I2C_CHANNEL_OPERATION_SUCCEEDED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+		result = true;
-+	break;
-+	case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+	break;
-+	case I2C_CHANNEL_OPERATION_TIMEOUT:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+	break;
-+	case I2C_CHANNEL_OPERATION_FAILED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-+	break;
-+	default:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-+	}
-+
-+	return result;
-+}
-+
-+/*
-+ * @brief
-+ * Returns number of microseconds to wait until timeout to be considered
-+ */
-+uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length)
-+{
-+	const struct i2c_engine *base = &engine->base;
-+
-+	uint32_t speed = base->funcs->get_speed(base);
-+
-+	if (!speed)
-+		return 0;
-+
-+	/* total timeout = period_timeout * (start + data bits count + stop) */
-+
-+	return ((1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed) *
-+		(1 + (length << 3) + 1);
-+}
-+
-+bool dal_i2c_generic_hw_engine_construct(
-+	struct i2c_generic_hw_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_i2c_hw_engine_construct(&engine->base, ctx))
-+		return false;
-+	return true;
-+}
-+
-+void dal_i2c_generic_hw_engine_destruct(
-+	struct i2c_generic_hw_engine *engine)
-+{
-+	dal_i2c_hw_engine_destruct(&engine->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h
-new file mode 100644
-index 0000000..52f2aa2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h
-@@ -0,0 +1,77 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_GENERIC_HW_ENGINE_H__
-+#define __DAL_I2C_GENERIC_HW_ENGINE_H__
-+
-+struct i2c_generic_transaction_attributes {
-+	enum i2caux_transaction_action action;
-+	uint8_t transaction_size;
-+	bool start_bit;
-+	bool stop_bit;
-+	bool last_read;
-+};
-+
-+struct i2c_generic_hw_engine;
-+
-+struct i2c_generic_hw_engine_funcs {
-+	void (*write_address)(
-+		struct i2c_generic_hw_engine *engine,
-+		uint8_t address);
-+	void (*write_data)(
-+		struct i2c_generic_hw_engine *engine,
-+		const uint8_t *buffer,
-+		uint8_t length);
-+	void (*read_data)(
-+		struct i2c_generic_hw_engine *engine,
-+		uint8_t *buffer,
-+		uint8_t length,
-+		uint32_t offset);
-+	void (*execute_transaction)(
-+		struct i2c_generic_hw_engine *engine,
-+		struct i2c_generic_transaction_attributes *attributes);
-+};
-+
-+struct i2c_generic_hw_engine {
-+	struct i2c_hw_engine base;
-+	const struct i2c_generic_hw_engine_funcs *funcs;
-+};
-+
-+bool dal_i2c_generic_hw_engine_construct(
-+	struct i2c_generic_hw_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2c_generic_hw_engine_destruct(
-+	struct i2c_generic_hw_engine *engine);
-+enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
-+	const struct engine *engine);
-+bool dal_i2c_generic_hw_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction);
-+uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-new file mode 100644
-index 0000000..77f2b84
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-@@ -0,0 +1,247 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+#include "i2c_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_hw_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_hw_engine *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_hw_engine, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_hw_engine *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_I2C_DDC_HW;
-+}
-+
-+bool dal_i2c_hw_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction)
-+{
-+	struct i2c_hw_engine *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_request_transaction_data request;
-+
-+	uint32_t transaction_timeout;
-+
-+	enum i2c_channel_operation_result operation_result;
-+
-+	bool result = false;
-+
-+	/* We need following:
-+	 * transaction length will not exceed
-+	 * the number of free bytes in HW buffer (minus one for address)*/
-+
-+	if (i2caux_request->payload.length >=
-+		hw_engine->funcs->get_hw_buffer_available_size(hw_engine)) {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW;
-+		return false;
-+	}
-+
-+	if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+	else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+	else {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-+		/* [anaumov] in DAL2, there was no "return false" */
-+		return false;
-+	}
-+
-+	request.address = (uint8_t)i2caux_request->payload.address;
-+	request.length = i2caux_request->payload.length;
-+	request.data = i2caux_request->payload.data;
-+
-+	/* obtain timeout value before submitting request */
-+
-+	transaction_timeout = hw_engine->funcs->get_transaction_timeout(
-+		hw_engine, i2caux_request->payload.length + 1);
-+
-+	hw_engine->base.funcs->submit_channel_request(
-+		&hw_engine->base, &request);
-+
-+	if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
-+		(request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY)) {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
-+		return false;
-+	}
-+
-+	/* wait until transaction proceed */
-+
-+	operation_result = hw_engine->funcs->wait_on_operation_result(
-+		hw_engine,
-+		transaction_timeout,
-+		I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-+
-+	/* update transaction status */
-+
-+	switch (operation_result) {
-+	case I2C_CHANNEL_OPERATION_SUCCEEDED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+		result = true;
-+	break;
-+	case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+	break;
-+	case I2C_CHANNEL_OPERATION_TIMEOUT:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+	break;
-+	case I2C_CHANNEL_OPERATION_FAILED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-+	break;
-+	default:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-+	}
-+
-+	if (result && (i2caux_request->operation == I2CAUX_TRANSACTION_READ)) {
-+		struct i2c_reply_transaction_data reply;
-+
-+		reply.data = i2caux_request->payload.data;
-+		reply.length = i2caux_request->payload.length;
-+
-+		hw_engine->base.funcs->
-+			process_channel_reply(&hw_engine->base, &reply);
-+	}
-+
-+	return result;
-+}
-+
-+bool dal_i2c_hw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc)
-+{
-+	enum gpio_result result;
-+	uint32_t current_speed;
-+
-+	result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-+		GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return false;
-+
-+	engine->base.ddc = ddc;
-+
-+	current_speed = engine->funcs->get_speed(engine);
-+
-+	if (current_speed)
-+		FROM_I2C_ENGINE(engine)->original_speed = current_speed;
-+
-+	return true;
-+}
-+/*
-+ * @brief
-+ * Queries in a loop for current engine status
-+ * until retrieved status matches 'expected_result', or timeout occurs.
-+ * Timeout given in microseconds
-+ * and the status query frequency is also one per microsecond.
-+ */
-+enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
-+	struct i2c_hw_engine *engine,
-+	uint32_t timeout,
-+	enum i2c_channel_operation_result expected_result)
-+{
-+	enum i2c_channel_operation_result result;
-+	uint32_t i = 0;
-+
-+	if (!timeout)
-+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	do {
-+		result = engine->base.funcs->get_channel_status(
-+			&engine->base, NULL);
-+
-+		if (result != expected_result)
-+			break;
-+
-+		dc_service_delay_in_microseconds(engine->base.base.ctx, 1);
-+
-+		++i;
-+	} while (i < timeout);
-+
-+	return result;
-+}
-+
-+bool dal_i2c_hw_engine_construct(
-+	struct i2c_hw_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_i2c_engine_construct(&engine->base, ctx))
-+		return false;
-+	engine->original_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-+	engine->default_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-+	return true;
-+}
-+
-+void dal_i2c_hw_engine_destruct(
-+	struct i2c_hw_engine *engine)
-+{
-+	dal_i2c_engine_destruct(&engine->base);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h
-new file mode 100644
-index 0000000..5afbd70
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_HW_ENGINE_H__
-+#define __DAL_I2C_HW_ENGINE_H__
-+
-+enum {
-+	TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32
-+};
-+
-+struct i2c_hw_engine;
-+
-+struct i2c_hw_engine_funcs {
-+	uint8_t (*get_hw_buffer_available_size)(
-+		const struct i2c_hw_engine *engine);
-+	enum i2c_channel_operation_result (*wait_on_operation_result)(
-+		struct i2c_hw_engine *engine,
-+		uint32_t timeout,
-+		enum i2c_channel_operation_result expected_result);
-+	uint32_t (*get_transaction_timeout)(
-+		const struct i2c_hw_engine *engine,
-+		uint32_t length);
-+};
-+
-+struct i2c_hw_engine {
-+	struct i2c_engine base;
-+	const struct i2c_hw_engine_funcs *funcs;
-+
-+	/* Values below are in kilohertz */
-+	uint32_t original_speed;
-+	uint32_t default_speed;
-+};
-+
-+bool dal_i2c_hw_engine_construct(
-+	struct i2c_hw_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2c_hw_engine_destruct(
-+	struct i2c_hw_engine *engine);
-+
-+enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
-+	struct i2c_hw_engine *engine,
-+	uint32_t timeout,
-+	enum i2c_channel_operation_result expected_result);
-+
-+bool dal_i2c_hw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc);
-+
-+bool dal_i2c_hw_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction);
-+
-+enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
-+	const struct engine *engine);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-new file mode 100644
-index 0000000..c253917
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-@@ -0,0 +1,615 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+#include "i2c_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_sw_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define SCL false
-+#define SDA true
-+
-+static inline bool read_bit_from_ddc(
-+	struct ddc *ddc,
-+	bool data_nor_clock)
-+{
-+	uint32_t value = 0;
-+
-+	if (data_nor_clock)
-+		dal_ddc_get_data(ddc, &value);
-+	else
-+		dal_ddc_get_clock(ddc, &value);
-+
-+	return (value != 0);
-+}
-+
-+static inline void write_bit_to_ddc(
-+	struct ddc *ddc,
-+	bool data_nor_clock,
-+	bool bit)
-+{
-+	uint32_t value = bit ? 1 : 0;
-+
-+	if (data_nor_clock)
-+		dal_ddc_set_data(ddc, value);
-+	else
-+		dal_ddc_set_clock(ddc, value);
-+}
-+
-+static bool wait_for_scl_high(
-+	struct dc_context *ctx,
-+	struct ddc *ddc,
-+	uint16_t clock_delay_div_4)
-+{
-+	uint32_t scl_retry = 0;
-+	uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	/* 3 milliseconds delay
-+	 * to wake up some displays from "low power" state.
-+	 */
-+
-+	do {
-+		if (read_bit_from_ddc(ddc, SCL))
-+			return true;
-+
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		++scl_retry;
-+	} while (scl_retry <= scl_retry_max);
-+
-+	return false;
-+}
-+
-+static bool start_sync(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4)
-+{
-+	uint32_t retry = 0;
-+
-+	/* The I2C communications start signal is:
-+	 * the SDA going low from high, while the SCL is high. */
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	do {
-+		write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+		if (!read_bit_from_ddc(ddc_handle, SDA)) {
-+			++retry;
-+			continue;
-+		}
-+
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+		if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+			break;
-+
-+		write_bit_to_ddc(ddc_handle, SDA, false);
-+
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		return true;
-+	} while (retry <= I2C_SW_RETRIES);
-+
-+	return false;
-+}
-+
-+static bool stop_sync(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4)
-+{
-+	uint32_t retry = 0;
-+
-+	/* The I2C communications stop signal is:
-+	 * the SDA going high from low, while the SCL is high. */
-+
-+	write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SDA, false);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+		return false;
-+
-+	write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+	do {
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		if (read_bit_from_ddc(ddc_handle, SDA))
-+			return true;
-+
-+		++retry;
-+	} while (retry <= 2);
-+
-+	return false;
-+}
-+
-+static bool write_byte(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t byte)
-+{
-+	int32_t shift = 7;
-+	bool ack;
-+
-+	/* bits are transmitted serially, starting from MSB */
-+
-+	do {
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
-+
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+		if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+			return false;
-+
-+		write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+		--shift;
-+	} while (shift >= 0);
-+
-+	/* The display sends ACK by preventing the SDA from going high
-+	 * after the SCL pulse we use to send our last data bit.
-+	 * If the SDA goes high after that bit, it's a NACK */
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+		return false;
-+
-+	/* read ACK bit */
-+
-+	ack = !read_bit_from_ddc(ddc_handle, SDA);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+
-+	return ack;
-+}
-+
-+static bool read_byte(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t *byte,
-+	bool more)
-+{
-+	int32_t shift = 7;
-+
-+	uint8_t data = 0;
-+
-+	/* The data bits are read from MSB to LSB;
-+	 * bit is read while SCL is high */
-+
-+	do {
-+		write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+		if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+			return false;
-+
-+		if (read_bit_from_ddc(ddc_handle, SDA))
-+			data |= (1 << shift);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+		dc_service_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+
-+		--shift;
-+	} while (shift >= 0);
-+
-+	/* read only whole byte */
-+
-+	*byte = data;
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	/* send the acknowledge bit:
-+	 * SDA low means ACK, SDA high means NACK */
-+
-+	write_bit_to_ddc(ddc_handle, SDA, !more);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+		return false;
-+
-+	write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+
-+	return true;
-+}
-+
-+static bool i2c_write(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t address,
-+	uint8_t length,
-+	const uint8_t *data)
-+{
-+	uint32_t i = 0;
-+
-+	if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
-+		return false;
-+
-+	while (i < length) {
-+		if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
-+			return false;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static bool i2c_read(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t address,
-+	uint8_t length,
-+	uint8_t *data)
-+{
-+	uint32_t i = 0;
-+
-+	if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
-+		return false;
-+
-+	while (i < length) {
-+		if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
-+			i < length - 1))
-+			return false;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_sw_engine *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_sw_engine, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_sw_engine *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_I2C_SW;
-+}
-+
-+bool dal_i2c_sw_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction)
-+{
-+	struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_engine *base = &sw_engine->base;
-+
-+	struct i2c_request_transaction_data request;
-+	bool operation_succeeded = false;
-+
-+	if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+	else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+	else {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-+		/* in DAL2, there was no "return false" */
-+		return false;
-+	}
-+
-+	request.address = (uint8_t)i2caux_request->payload.address;
-+	request.length = i2caux_request->payload.length;
-+	request.data = i2caux_request->payload.data;
-+
-+	base->funcs->submit_channel_request(base, &request);
-+
-+	if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
-+		(request.status == I2C_CHANNEL_OPERATION_FAILED))
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
-+	else {
-+		enum i2c_channel_operation_result operation_result;
-+
-+		do {
-+			operation_result =
-+				base->funcs->get_channel_status(base, NULL);
-+
-+			switch (operation_result) {
-+			case I2C_CHANNEL_OPERATION_SUCCEEDED:
-+				i2caux_request->status =
-+					I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+				operation_succeeded = true;
-+			break;
-+			case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-+				i2caux_request->status =
-+					I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+			break;
-+			case I2C_CHANNEL_OPERATION_TIMEOUT:
-+				i2caux_request->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			break;
-+			case I2C_CHANNEL_OPERATION_FAILED:
-+				i2caux_request->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-+			break;
-+			default:
-+				i2caux_request->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-+			break;
-+			}
-+		} while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-+	}
-+
-+	return operation_succeeded;
-+}
-+
-+uint32_t dal_i2c_sw_engine_get_speed(
-+	const struct i2c_engine *engine)
-+{
-+	return FROM_I2C_ENGINE(engine)->speed;
-+}
-+
-+void dal_i2c_sw_engine_set_speed(
-+	struct i2c_engine *engine,
-+	uint32_t speed)
-+{
-+	struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-+
-+	ASSERT(speed);
-+
-+	sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
-+
-+	sw_engine->clock_delay = 1000 / sw_engine->speed;
-+
-+	if (sw_engine->clock_delay < 12)
-+		sw_engine->clock_delay = 12;
-+}
-+
-+bool dal_i2caux_i2c_sw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc)
-+{
-+	enum gpio_result result;
-+
-+	result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
-+		GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return false;
-+
-+	engine->base.ddc = ddc;
-+
-+	return true;
-+}
-+
-+void dal_i2c_sw_engine_submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *req)
-+{
-+	struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-+
-+	struct ddc *ddc = engine->base.ddc;
-+	uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
-+
-+	/* send sync (start / repeated start) */
-+
-+	bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
-+
-+	/* process payload */
-+
-+	if (result) {
-+		switch (req->action) {
-+		case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
-+		case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
-+			result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
-+				req->address, req->length, req->data);
-+		break;
-+		case I2CAUX_TRANSACTION_ACTION_I2C_READ:
-+		case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
-+			result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
-+				req->address, req->length, req->data);
-+		break;
-+		default:
-+			result = false;
-+		break;
-+		}
-+	}
-+
-+	/* send stop if not 'mot' or operation failed */
-+
-+	if (!result ||
-+		(req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		(req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
-+		if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
-+			result = false;
-+
-+	req->status = result ?
-+		I2C_CHANNEL_OPERATION_SUCCEEDED :
-+		I2C_CHANNEL_OPERATION_FAILED;
-+}
-+
-+enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	return dal_ddc_check_line_aborted(engine->base.ddc) ?
-+		I2C_CHANNEL_OPERATION_FAILED :
-+		I2C_CHANNEL_OPERATION_SUCCEEDED;
-+}
-+
-+void dal_i2c_sw_engine_destruct(
-+	struct i2c_sw_engine *engine)
-+{
-+	dal_i2c_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **ptr)
-+{
-+	dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
-+
-+	dc_service_free((*ptr)->base.ctx, *ptr);
-+	*ptr = NULL;
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
-+	.destroy = destroy,
-+	.get_speed = dal_i2c_sw_engine_get_speed,
-+	.set_speed = dal_i2c_sw_engine_set_speed,
-+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
-+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
-+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
-+};
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+
-+}
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_sw_engine_submit_request,
-+	.keep_power_up_count = dal_i2caux_keep_power_up_count,
-+};
-+
-+bool dal_i2c_sw_engine_construct(
-+	struct i2c_sw_engine *engine,
-+	const struct i2c_sw_engine_create_arg *arg)
-+{
-+	if (!dal_i2c_engine_construct(&engine->base, arg->ctx))
-+		return false;
-+
-+	dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
-+	engine->base.funcs = &i2c_engine_funcs;
-+	engine->base.base.funcs = &engine_funcs;
-+	return true;
-+}
-+
-+
-+
-+struct i2c_engine *dal_i2c_sw_engine_create(
-+	const struct i2c_sw_engine_create_arg *arg)
-+{
-+	struct i2c_sw_engine *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = dc_service_alloc(arg->ctx, sizeof(struct i2c_sw_engine));
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (dal_i2c_sw_engine_construct(engine, arg))
-+		return &engine->base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dc_service_free(arg->ctx, engine);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h
-new file mode 100644
-index 0000000..e0cb4c3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h
-@@ -0,0 +1,81 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_SW_ENGINE_H__
-+#define __DAL_I2C_SW_ENGINE_H__
-+
-+enum {
-+	I2C_SW_RETRIES = 10,
-+	I2C_SW_SCL_READ_RETRIES = 128,
-+	/* following value is in microseconds */
-+	I2C_SW_TIMEOUT_DELAY = 3000
-+};
-+
-+struct i2c_sw_engine;
-+
-+struct i2c_sw_engine {
-+	struct i2c_engine base;
-+	uint32_t clock_delay;
-+	/* Values below are in KHz */
-+	uint32_t speed;
-+	uint32_t default_speed;
-+};
-+
-+struct i2c_sw_engine_create_arg {
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+bool dal_i2c_sw_engine_construct(
-+	struct i2c_sw_engine *engine,
-+	const struct i2c_sw_engine_create_arg *arg);
-+
-+bool dal_i2caux_i2c_sw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc_handle);
-+
-+void dal_i2c_sw_engine_destruct(
-+	struct i2c_sw_engine *engine);
-+
-+struct i2c_engine *dal_i2c_sw_engine_create(
-+	const struct i2c_sw_engine_create_arg *arg);
-+enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
-+	const struct engine *engine);
-+bool dal_i2c_sw_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction);
-+uint32_t dal_i2c_sw_engine_get_speed(
-+	const struct i2c_engine *engine);
-+void dal_i2c_sw_engine_set_speed(
-+	struct i2c_engine *ptr,
-+	uint32_t speed);
-+void dal_i2c_sw_engine_submit_channel_request(
-+	struct i2c_engine *ptr,
-+	struct i2c_request_transaction_data *req);
-+enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-new file mode 100644
-index 0000000..50262a4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -0,0 +1,519 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2caux.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "engine.h"
-+#include "i2c_engine.h"
-+#include "aux_engine.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/i2caux_dce110.h"
-+#endif
-+
-+/*
-+ * @brief
-+ * Plain API, available publicly
-+ */
-+
-+struct i2caux *dal_i2caux_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	enum dce_version dce_version;
-+
-+	if (!as) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_version = dal_adapter_service_get_dce_version(as);
-+
-+	switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		return dal_i2caux_dce110_create(as, ctx);
-+#endif
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+}
-+
-+bool dal_i2caux_submit_i2c_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct i2c_command *cmd)
-+{
-+	struct i2c_engine *engine;
-+	uint8_t index_of_payload = 0;
-+	bool result;
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!cmd) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (cmd->engine) {
-+	case I2C_COMMAND_ENGINE_SW:
-+		/* try to acquire SW engine first,
-+		 * acquire HW engine if SW engine not available */
-+		engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);
-+
-+		if (!engine)
-+			engine = i2caux->funcs->acquire_i2c_hw_engine(
-+				i2caux, ddc);
-+	break;
-+	case I2C_COMMAND_ENGINE_HW:
-+	case I2C_COMMAND_ENGINE_DEFAULT:
-+	default:
-+		/* try to acquire HW engine first,
-+		 * acquire SW engine if HW engine not available */
-+		engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);
-+
-+		if (!engine)
-+			engine = i2caux->funcs->acquire_i2c_sw_engine(
-+				i2caux, ddc);
-+	}
-+
-+	if (!engine)
-+		return false;
-+
-+	engine->funcs->set_speed(engine, cmd->speed);
-+
-+	result = true;
-+
-+	while (index_of_payload < cmd->number_of_payloads) {
-+		bool mot = (index_of_payload != cmd->number_of_payloads - 1);
-+
-+		struct i2c_payload *payload = cmd->payloads + index_of_payload;
-+
-+		struct i2caux_transaction_request request = { 0 };
-+
-+		request.operation = payload->write ?
-+			I2CAUX_TRANSACTION_WRITE :
-+			I2CAUX_TRANSACTION_READ;
-+
-+		request.payload.address_space =
-+			I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
-+		request.payload.address = (payload->address << 1) |
-+			!payload->write;
-+		request.payload.length = payload->length;
-+		request.payload.data = payload->data;
-+
-+		if (!engine->base.funcs->submit_request(
-+			&engine->base, &request, mot)) {
-+			result = false;
-+			break;
-+		}
-+
-+		++index_of_payload;
-+	}
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+
-+	return result;
-+}
-+
-+bool dal_i2caux_submit_aux_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct aux_command *cmd)
-+{
-+	struct aux_engine *engine;
-+	uint8_t index_of_payload = 0;
-+	bool result;
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!cmd) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);
-+
-+	if (!engine)
-+		return false;
-+
-+	engine->delay = cmd->defer_delay;
-+	engine->max_defer_write_retry = cmd->max_defer_write_retry;
-+
-+	result = true;
-+
-+	while (index_of_payload < cmd->number_of_payloads) {
-+		bool mot = (index_of_payload != cmd->number_of_payloads - 1);
-+
-+		struct aux_payload *payload = cmd->payloads + index_of_payload;
-+
-+		struct i2caux_transaction_request request = { 0 };
-+
-+		request.operation = payload->write ?
-+			I2CAUX_TRANSACTION_WRITE :
-+			I2CAUX_TRANSACTION_READ;
-+
-+		if (payload->i2c_over_aux) {
-+			request.payload.address_space =
-+				I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
-+
-+			request.payload.address = (payload->address << 1) |
-+				!payload->write;
-+		} else {
-+			request.payload.address_space =
-+				I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD;
-+
-+			request.payload.address = payload->address;
-+		}
-+
-+		request.payload.length = payload->length;
-+		request.payload.data = payload->data;
-+
-+		if (!engine->base.funcs->submit_request(
-+			&engine->base, &request, mot)) {
-+			result = false;
-+			break;
-+		}
-+
-+		++index_of_payload;
-+	}
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+
-+	return result;
-+}
-+
-+static bool get_hw_supported_ddc_line(
-+	struct ddc *ddc,
-+	enum gpio_ddc_line *line)
-+{
-+	enum gpio_ddc_line line_found;
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!dal_ddc_is_hw_supported(ddc))
-+		return false;
-+
-+	line_found = dal_ddc_get_line(ddc);
-+
-+	if (line_found >= GPIO_DDC_LINE_COUNT)
-+		return false;
-+
-+	*line = line_found;
-+
-+	return true;
-+}
-+
-+void dal_i2caux_keep_engine_power_up(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	bool keep_power_up)
-+{
-+	enum gpio_ddc_line line;
-+	struct i2c_engine *engine;
-+
-+	if (!get_hw_supported_ddc_line(ddc, &line))
-+		return;
-+
-+	engine = i2caux->i2c_hw_engines[line];
-+
-+	engine->base.funcs->keep_power_up_count(&engine->base, keep_power_up);
-+}
-+
-+bool dal_i2caux_start_gtc_sync(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	enum gpio_ddc_line line;
-+
-+	struct aux_engine *engine;
-+
-+	bool result;
-+
-+	if (!get_hw_supported_ddc_line(ddc, &line))
-+		return false;
-+
-+	engine = i2caux->aux_engines[line];
-+
-+	if (!engine)
-+		return false;
-+
-+	if (!engine->base.funcs->acquire(&engine->base, ddc))
-+		return false;
-+
-+	result = engine->funcs->start_gtc_sync(engine);
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+
-+	return result;
-+}
-+
-+bool dal_i2caux_stop_gtc_sync(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	enum gpio_ddc_line line;
-+
-+	struct aux_engine *engine;
-+
-+	if (!get_hw_supported_ddc_line(ddc, &line))
-+		return false;
-+
-+	engine = i2caux->aux_engines[line];
-+
-+	if (!engine)
-+		return false;
-+
-+	if (!engine->base.funcs->acquire(&engine->base, ddc))
-+		return false;
-+
-+	engine->funcs->stop_gtc_sync(engine);
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+
-+	return true;
-+}
-+
-+void dal_i2caux_configure_aux(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	union aux_config cfg)
-+{
-+	struct aux_engine *engine =
-+		i2caux->funcs->acquire_aux_engine(i2caux, ddc);
-+
-+	if (!engine)
-+		return;
-+
-+	engine->funcs->configure(engine, cfg);
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+}
-+
-+void dal_i2caux_destroy(
-+	struct i2caux **i2caux)
-+{
-+	if (!i2caux || !*i2caux) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	(*i2caux)->funcs->destroy(i2caux);
-+
-+	*i2caux = NULL;
-+}
-+
-+/*
-+ * @brief
-+ * An utility function used by 'struct i2caux' and its descendants
-+ */
-+
-+uint32_t dal_i2caux_get_reference_clock(
-+	struct adapter_service *as)
-+{
-+	struct firmware_info info = { { 0 } };
-+
-+	if (!dal_adapter_service_get_firmware_info(as, &info))
-+		return 0;
-+
-+	return info.pll_info.crystal_frequency;
-+}
-+
-+/*
-+ * @brief
-+ * i2caux
-+ */
-+
-+enum {
-+	/* following are expressed in KHz */
-+	DEFAULT_I2C_SW_SPEED = 50,
-+	DEFAULT_I2C_HW_SPEED = 50,
-+
-+	/* This is the timeout as defined in DP 1.2a,
-+	 * 2.3.4 "Detailed uPacket TX AUX CH State Description". */
-+	AUX_TIMEOUT_PERIOD = 400,
-+
-+	/* Ideally, the SW timeout should be just above 550usec
-+	 * which is programmed in HW.
-+	 * But the SW timeout of 600usec is not reliable,
-+	 * because on some systems, delay_in_microseconds()
-+	 * returns faster than it should.
-+	 * EPR #379763: by trial-and-error on different systems,
-+	 * 700usec is the minimum reliable SW timeout for polling
-+	 * the AUX_SW_STATUS.AUX_SW_DONE bit.
-+	 * This timeout expires *only* when there is
-+	 * AUX Error or AUX Timeout conditions - not during normal operation.
-+	 * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
-+	 * at most within ~240usec. That means,
-+	 * increasing this timeout will not affect normal operation,
-+	 * and we'll timeout after
-+	 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
-+	 * This timeout is especially important for
-+	 * resume from S3 and CTS. */
-+	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
-+};
-+
-+struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	enum gpio_ddc_line line;
-+	struct i2c_engine *engine = NULL;
-+
-+	if (get_hw_supported_ddc_line(ddc, &line))
-+		engine = i2caux->i2c_sw_engines[line];
-+
-+	if (!engine)
-+		engine = i2caux->i2c_generic_sw_engine;
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (!engine->base.funcs->acquire(&engine->base, ddc))
-+		return NULL;
-+
-+	return engine;
-+}
-+
-+struct aux_engine *dal_i2caux_acquire_aux_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	enum gpio_ddc_line line;
-+	struct aux_engine *engine;
-+
-+	if (!get_hw_supported_ddc_line(ddc, &line))
-+		return NULL;
-+
-+	engine = i2caux->aux_engines[line];
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (!engine->base.funcs->acquire(&engine->base, ddc))
-+		return NULL;
-+
-+	return engine;
-+}
-+
-+void dal_i2caux_release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine)
-+{
-+	engine->funcs->release_engine(engine);
-+
-+	dal_ddc_close(engine->ddc);
-+
-+	engine->ddc = NULL;
-+}
-+
-+bool dal_i2caux_construct(
-+	struct i2caux *i2caux,
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	uint32_t i = 0;
-+
-+	i2caux->ctx = ctx;
-+	do {
-+		i2caux->i2c_sw_engines[i] = NULL;
-+		i2caux->i2c_hw_engines[i] = NULL;
-+		i2caux->aux_engines[i] = NULL;
-+
-+		++i;
-+	} while (i < GPIO_DDC_LINE_COUNT);
-+
-+	i2caux->i2c_generic_sw_engine = NULL;
-+	i2caux->i2c_generic_hw_engine = NULL;
-+
-+	i2caux->aux_timeout_period =
-+		SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD;
-+
-+	i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED;
-+	i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED;
-+
-+	return true;
-+}
-+
-+void dal_i2caux_destruct(
-+	struct i2caux *i2caux)
-+{
-+	uint32_t i = 0;
-+
-+	if (i2caux->i2c_generic_hw_engine)
-+		i2caux->i2c_generic_hw_engine->funcs->destroy(
-+			&i2caux->i2c_generic_hw_engine);
-+
-+	if (i2caux->i2c_generic_sw_engine)
-+		i2caux->i2c_generic_sw_engine->funcs->destroy(
-+			&i2caux->i2c_generic_sw_engine);
-+
-+	do {
-+		if (i2caux->aux_engines[i])
-+			i2caux->aux_engines[i]->funcs->destroy(
-+				&i2caux->aux_engines[i]);
-+
-+		if (i2caux->i2c_hw_engines[i])
-+			i2caux->i2c_hw_engines[i]->funcs->destroy(
-+				&i2caux->i2c_hw_engines[i]);
-+
-+		if (i2caux->i2c_sw_engines[i])
-+			i2caux->i2c_sw_engines[i]->funcs->destroy(
-+				&i2caux->i2c_sw_engines[i]);
-+
-+		++i;
-+	} while (i < GPIO_DDC_LINE_COUNT);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
-new file mode 100644
-index 0000000..76f5b63
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
-@@ -0,0 +1,123 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_H__
-+#define __DAL_I2C_AUX_H__
-+
-+uint32_t dal_i2caux_get_reference_clock(
-+	struct adapter_service *as);
-+
-+struct i2caux;
-+
-+struct engine;
-+
-+struct i2caux_funcs {
-+	void (*destroy)(struct i2caux **ptr);
-+	struct i2c_engine * (*acquire_i2c_sw_engine)(
-+		struct i2caux *i2caux,
-+		struct ddc *ddc);
-+	struct i2c_engine * (*acquire_i2c_hw_engine)(
-+		struct i2caux *i2caux,
-+		struct ddc *ddc);
-+	struct aux_engine * (*acquire_aux_engine)(
-+		struct i2caux *i2caux,
-+		struct ddc *ddc);
-+	void (*release_engine)(
-+		struct i2caux *i2caux,
-+		struct engine *engine);
-+};
-+
-+struct i2c_engine;
-+struct aux_engine;
-+
-+struct i2caux {
-+	struct dc_context *ctx;
-+	const struct i2caux_funcs *funcs;
-+	/* On ASIC we have certain amount of lines with HW DDC engine
-+	 * (4, 6, or maybe more in the future).
-+	 * For every such line, we create separate HW DDC engine
-+	 * (since we have these engines in HW) and separate SW DDC engine
-+	 * (to allow concurrent use of few lines).
-+	 * In similar way we have AUX engines. */
-+
-+	/* I2C SW engines, per DDC line.
-+	 * Only lines with HW DDC support will be initialized */
-+	struct i2c_engine *i2c_sw_engines[GPIO_DDC_LINE_COUNT];
-+
-+	/* I2C HW engines, per DDC line.
-+	 * Only lines with HW DDC support will be initialized */
-+	struct i2c_engine *i2c_hw_engines[GPIO_DDC_LINE_COUNT];
-+
-+	/* AUX engines, per DDC line.
-+	 * Only lines with HW AUX support will be initialized */
-+	struct aux_engine *aux_engines[GPIO_DDC_LINE_COUNT];
-+
-+	/* For all other lines, we can use
-+	 * single instance of generic I2C HW engine
-+	 * (since in HW, there is single instance of it)
-+	 * or single instance of generic I2C SW engine.
-+	 * AUX is not supported for other lines. */
-+
-+	/* General-purpose I2C SW engine.
-+	 * Can be assigned dynamically to any line per transaction */
-+	struct i2c_engine *i2c_generic_sw_engine;
-+
-+	/* General-purpose I2C generic HW engine.
-+	 * Can be assigned dynamically to almost any line per transaction */
-+	struct i2c_engine *i2c_generic_hw_engine;
-+
-+	/* [anaumov] in DAL2, there is a Mutex */
-+
-+	uint32_t aux_timeout_period;
-+
-+	/* expressed in KHz */
-+	uint32_t default_i2c_sw_speed;
-+	uint32_t default_i2c_hw_speed;
-+};
-+
-+bool dal_i2caux_construct(
-+	struct i2caux *i2caux,
-+	struct adapter_service *as,
-+	struct dc_context *ctx);
-+
-+void dal_i2caux_release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine);
-+
-+void dal_i2caux_destruct(
-+	struct i2caux *i2caux);
-+
-+void dal_i2caux_destroy(
-+	struct i2caux **ptr);
-+
-+struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc);
-+
-+struct aux_engine *dal_i2caux_acquire_aux_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-new file mode 100644
-index 0000000..f7315c6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -0,0 +1,463 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * Bandwidth and Watermark calculations interface.
-+ * (Refer to "DCE11_mode_support.xlsm" from Perforce.)
-+ */
-+#ifndef __BANDWIDTH_CALCS_H__
-+#define __BANDWIDTH_CALCS_H__
-+
-+#include "bw_fixed.h"
-+/*******************************************************************************
-+ * There are three types of input into Calculations:
-+ * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP
-+ * 2. board-level values - these are generally coming from VBIOS parser
-+ * 3. mode/configuration values - depending Mode, Scaling number of Displays etc.
-+ ******************************************************************************/
-+
-+enum bw_stereo_mode {
-+	mono,
-+	side_by_side,
-+	top_bottom
-+};
-+
-+enum bw_ul_mode {
-+	ul_none,
-+	ul_only,
-+	ul_blend
-+};
-+
-+enum bw_tiling_mode {
-+	linear,
-+	tiled
-+};
-+
-+enum bw_panning_and_bezel_adj {
-+	none,
-+	any_lines
-+};
-+
-+enum bw_underlay_surface_type {
-+	yuv_420,
-+	yuv_422
-+};
-+
-+struct bw_calcs_input_dceip {
-+	struct bw_fixed dmif_request_buffer_size;
-+	struct bw_fixed de_tiling_buffer;
-+	struct bw_fixed dcfclk_request_generation;
-+	struct bw_fixed lines_interleaved_into_lb;
-+	struct bw_fixed chunk_width;
-+	struct bw_fixed number_of_graphics_pipes;
-+	struct bw_fixed number_of_underlay_pipes;
-+	bool display_write_back_supported;
-+	bool argb_compression_support;
-+	struct bw_fixed underlay_vscaler_efficiency6_bit_per_component;
-+	struct bw_fixed underlay_vscaler_efficiency8_bit_per_component;
-+	struct bw_fixed underlay_vscaler_efficiency10_bit_per_component;
-+	struct bw_fixed underlay_vscaler_efficiency12_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency6_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency8_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency10_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency12_bit_per_component;
-+	struct bw_fixed alpha_vscaler_efficiency;
-+	struct bw_fixed max_dmif_buffer_allocated;
-+	struct bw_fixed graphics_dmif_size;
-+	struct bw_fixed underlay_luma_dmif_size;
-+	struct bw_fixed underlay_chroma_dmif_size;
-+	bool pre_downscaler_enabled;
-+	bool underlay_downscale_prefetch_enabled;
-+	struct bw_fixed lb_write_pixels_per_dispclk;
-+	struct bw_fixed lb_size_per_component444;
-+	bool graphics_lb_nodownscaling_multi_line_prefetching;
-+	struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor;
-+	struct bw_fixed underlay420_luma_lb_size_per_component;
-+	struct bw_fixed underlay420_chroma_lb_size_per_component;
-+	struct bw_fixed underlay422_lb_size_per_component;
-+	struct bw_fixed cursor_chunk_width;
-+	struct bw_fixed cursor_dcp_buffer_lines;
-+	struct bw_fixed cursor_memory_interface_buffer_pixels;
-+	struct bw_fixed underlay_maximum_width_efficient_for_tiling;
-+	struct bw_fixed underlay_maximum_height_efficient_for_tiling;
-+	struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
-+	struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
-+	struct bw_fixed minimum_outstanding_pte_request_limit;
-+	struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw;
-+	bool limit_excessive_outstanding_dmif_requests;
-+	struct bw_fixed linear_mode_line_request_alternation_slice;
-+	struct bw_fixed scatter_gather_lines_of_pte_prefetching_in_linear_mode;
-+	struct bw_fixed display_write_back420_luma_mcifwr_buffer_size;
-+	struct bw_fixed display_write_back420_chroma_mcifwr_buffer_size;
-+	struct bw_fixed request_efficiency;
-+	struct bw_fixed dispclk_per_request;
-+	struct bw_fixed dispclk_ramping_factor;
-+	struct bw_fixed display_pipe_throughput_factor;
-+	struct bw_fixed scatter_gather_pte_request_rows_in_tiling_mode;
-+	struct bw_fixed mcifwr_all_surfaces_burst_time; /* 0 todo: this is a bug*/
-+};
-+
-+struct bw_calcs_input_vbios {
-+	struct bw_fixed dram_channel_width_in_bits;
-+	struct bw_fixed number_of_dram_channels;
-+	struct bw_fixed number_of_dram_banks;
-+	struct bw_fixed high_yclk;
-+	struct bw_fixed high_dram_bandwidth_per_channel;
-+	struct bw_fixed low_yclk;
-+	struct bw_fixed low_dram_bandwidth_per_channel;
-+	struct bw_fixed low_sclk;
-+	struct bw_fixed mid_sclk;
-+	struct bw_fixed high_sclk;
-+	struct bw_fixed low_voltage_max_dispclk;
-+	struct bw_fixed mid_voltage_max_dispclk;
-+	struct bw_fixed high_voltage_max_dispclk;
-+	struct bw_fixed data_return_bus_width;
-+	struct bw_fixed trc;
-+	struct bw_fixed dmifmc_urgent_latency;
-+	struct bw_fixed stutter_self_refresh_exit_latency;
-+	struct bw_fixed nbp_state_change_latency;
-+	struct bw_fixed mcifwrmc_urgent_latency;
-+	bool scatter_gather_enable;
-+	struct bw_fixed down_spread_percentage;
-+	struct bw_fixed cursor_width;
-+	struct bw_fixed average_compression_rate;
-+	struct bw_fixed number_of_request_slots_gmc_reserves_for_dmif_per_channel;
-+	struct bw_fixed blackout_duration;
-+	struct bw_fixed maximum_blackout_recovery_time;
-+};
-+
-+struct bw_calcs_input_mode_data_internal {
-+	/* data for all displays */
-+	uint32_t number_of_displays;
-+	struct bw_fixed graphics_rotation_angle;
-+	struct bw_fixed underlay_rotation_angle;
-+	bool display_synchronization_enabled;
-+	enum bw_underlay_surface_type underlay_surface_type;
-+	enum bw_panning_and_bezel_adj panning_and_bezel_adjustment;
-+	enum bw_tiling_mode graphics_tiling_mode;
-+	bool graphics_interlace_mode;
-+	struct bw_fixed graphics_bytes_per_pixel;
-+	struct bw_fixed graphics_htaps;
-+	struct bw_fixed graphics_vtaps;
-+	struct bw_fixed graphics_lb_bpc;
-+	struct bw_fixed underlay_lb_bpc;
-+	enum bw_tiling_mode underlay_tiling_mode;
-+	struct bw_fixed underlay_htaps;
-+	struct bw_fixed underlay_vtaps;
-+	struct bw_fixed underlay_src_width;
-+	struct bw_fixed underlay_src_height;
-+	struct bw_fixed underlay_pitch_in_pixels;
-+	enum bw_stereo_mode underlay_stereo_mode;
-+	bool d0_fbc_enable;
-+	bool d0_lpt_enable;
-+	struct bw_fixed d0_htotal;
-+	struct bw_fixed d0_pixel_rate;
-+	struct bw_fixed d0_graphics_src_width;
-+	struct bw_fixed d0_graphics_src_height;
-+	struct bw_fixed d0_graphics_scale_ratio;
-+	enum bw_stereo_mode d0_graphics_stereo_mode;
-+	enum bw_ul_mode d0_underlay_mode;
-+	struct bw_fixed d0_underlay_scale_ratio;
-+	struct bw_fixed d1_htotal;
-+	struct bw_fixed d1_pixel_rate;
-+	struct bw_fixed d1_graphics_src_width;
-+	struct bw_fixed d1_graphics_src_height;
-+	struct bw_fixed d1_graphics_scale_ratio;
-+	enum bw_stereo_mode d1_graphics_stereo_mode;
-+	bool d1_display_write_back_dwb_enable;
-+	enum bw_ul_mode d1_underlay_mode;
-+	struct bw_fixed d1_underlay_scale_ratio;
-+	struct bw_fixed d2_htotal;
-+	struct bw_fixed d2_pixel_rate;
-+	struct bw_fixed d2_graphics_src_width;
-+	struct bw_fixed d2_graphics_src_height;
-+	struct bw_fixed d2_graphics_scale_ratio;
-+	enum bw_stereo_mode d2_graphics_stereo_mode;
-+};
-+
-+struct bw_calcs_input_single_display {
-+	uint32_t graphics_rotation_angle;
-+	uint32_t underlay_rotation_angle;
-+	enum bw_underlay_surface_type underlay_surface_type;
-+	enum bw_panning_and_bezel_adj panning_and_bezel_adjustment;
-+	uint32_t graphics_bytes_per_pixel;
-+	bool graphics_interlace_mode;
-+	enum bw_tiling_mode graphics_tiling_mode;
-+	uint32_t graphics_h_taps;
-+	uint32_t graphics_v_taps;
-+	uint32_t graphics_lb_bpc;
-+	uint32_t underlay_lb_bpc;
-+	enum bw_tiling_mode underlay_tiling_mode;
-+	uint32_t underlay_h_taps;
-+	uint32_t underlay_v_taps;
-+	uint32_t underlay_src_width;
-+	uint32_t underlay_src_height;
-+	uint32_t underlay_pitch_in_pixels;
-+	enum bw_stereo_mode underlay_stereo_mode;
-+	bool fbc_enable;
-+	bool lpt_enable;
-+	uint32_t h_total;
-+	struct bw_fixed pixel_rate;
-+	uint32_t graphics_src_width;
-+	uint32_t graphics_src_height;
-+	struct bw_fixed graphics_scale_ratio;
-+	enum bw_stereo_mode graphics_stereo_mode;
-+	enum bw_ul_mode underlay_mode;
-+};
-+
-+#define BW_CALCS_MAX_NUM_DISPLAYS 3
-+
-+struct bw_calcs_input_mode_data {
-+	/* data for all displays */
-+	uint8_t number_of_displays;
-+	bool display_synchronization_enabled;
-+
-+	struct bw_calcs_input_single_display
-+				displays_data[BW_CALCS_MAX_NUM_DISPLAYS];
-+};
-+
-+/*******************************************************************************
-+ * Output data structure(s).
-+ ******************************************************************************/
-+#define maximum_number_of_surfaces 12
-+struct bw_results_internal {
-+	bool cpup_state_change_enable;
-+	bool cpuc_state_change_enable;
-+	bool nbp_state_change_enable;
-+	bool stutter_mode_enable;
-+	struct bw_fixed number_of_underlay_surfaces;
-+	struct bw_fixed src_width_after_surface_type;
-+	struct bw_fixed src_height_after_surface_type;
-+	struct bw_fixed hsr_after_surface_type;
-+	struct bw_fixed vsr_after_surface_type;
-+	struct bw_fixed src_width_after_rotation;
-+	struct bw_fixed src_height_after_rotation;
-+	struct bw_fixed hsr_after_rotation;
-+	struct bw_fixed vsr_after_rotation;
-+	struct bw_fixed source_height_pixels;
-+	struct bw_fixed hsr_after_stereo;
-+	struct bw_fixed vsr_after_stereo;
-+	struct bw_fixed source_width_in_lb;
-+	struct bw_fixed lb_line_pitch;
-+	struct bw_fixed underlay_maximum_source_efficient_for_tiling;
-+	struct bw_fixed num_lines_at_frame_start;
-+	struct bw_fixed min_dmif_size_in_time;
-+	struct bw_fixed min_mcifwr_size_in_time;
-+	struct bw_fixed total_requests_for_dmif_size;
-+	struct bw_fixed peak_pte_request_to_eviction_ratio_limiting;
-+	struct bw_fixed useful_pte_per_pte_request;
-+	struct bw_fixed scatter_gather_pte_request_rows;
-+	struct bw_fixed scatter_gather_row_height;
-+	struct bw_fixed scatter_gather_pte_requests_in_vblank;
-+	struct bw_fixed inefficient_linear_pitch_in_bytes;
-+	struct bw_fixed inefficient_underlay_pitch_in_pixels;
-+	struct bw_fixed minimum_underlay_pitch_padding_recommended_for_efficiency;
-+	struct bw_fixed cursor_total_data;
-+	struct bw_fixed cursor_total_request_groups;
-+	struct bw_fixed scatter_gather_total_pte_requests;
-+	struct bw_fixed scatter_gather_total_pte_request_groups;
-+	struct bw_fixed tile_width_in_pixels;
-+	struct bw_fixed dmif_total_number_of_data_request_page_close_open;
-+	struct bw_fixed mcifwr_total_number_of_data_request_page_close_open;
-+	struct bw_fixed bytes_per_page_close_open;
-+	struct bw_fixed mcifwr_total_page_close_open_time;
-+	struct bw_fixed total_requests_for_adjusted_dmif_size;
-+	struct bw_fixed total_dmifmc_urgent_trips;
-+	struct bw_fixed total_dmifmc_urgent_latency;
-+	struct bw_fixed total_display_reads_required_data;
-+	struct bw_fixed total_display_reads_required_dram_access_data;
-+	struct bw_fixed total_display_writes_required_data;
-+	struct bw_fixed total_display_writes_required_dram_access_data;
-+	struct bw_fixed display_reads_required_data;
-+	struct bw_fixed display_reads_required_dram_access_data;
-+	struct bw_fixed dmif_total_page_close_open_time;
-+	struct bw_fixed min_cursor_memory_interface_buffer_size_in_time;
-+	struct bw_fixed min_read_buffer_size_in_time;
-+	struct bw_fixed display_reads_time_for_data_transfer;
-+	struct bw_fixed display_writes_time_for_data_transfer;
-+	struct bw_fixed dmif_required_dram_bandwidth;
-+	struct bw_fixed mcifwr_required_dram_bandwidth;
-+	struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open;
-+	struct bw_fixed required_mcifmcwr_urgent_latency;
-+	struct bw_fixed required_dram_bandwidth_gbyte_per_second;
-+	struct bw_fixed dram_bandwidth;
-+	struct bw_fixed dmif_required_sclk;
-+	struct bw_fixed mcifwr_required_sclk;
-+	struct bw_fixed required_sclk;
-+	struct bw_fixed downspread_factor;
-+	struct bw_fixed v_scaler_efficiency;
-+	struct bw_fixed scaler_limits_factor;
-+	struct bw_fixed display_pipe_pixel_throughput;
-+	struct bw_fixed total_dispclk_required_with_ramping;
-+	struct bw_fixed total_dispclk_required_without_ramping;
-+	struct bw_fixed total_read_request_bandwidth;
-+	struct bw_fixed total_write_request_bandwidth;
-+	struct bw_fixed dispclk_required_for_total_read_request_bandwidth;
-+	struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth;
-+	struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth;
-+	struct bw_fixed dispclk;
-+	struct bw_fixed blackout_recovery_time;
-+	struct bw_fixed min_pixels_per_data_fifo_entry;
-+	struct bw_fixed sclk_deep_sleep;
-+	struct bw_fixed chunk_request_time;
-+	struct bw_fixed cursor_request_time;
-+	struct bw_fixed line_source_pixels_transfer_time;
-+	struct bw_fixed dmifdram_access_efficiency;
-+	struct bw_fixed mcifwrdram_access_efficiency;
-+	struct bw_fixed total_average_bandwidth_no_compression;
-+	struct bw_fixed total_average_bandwidth;
-+	struct bw_fixed total_stutter_cycle_duration;
-+	struct bw_fixed stutter_burst_time;
-+	struct bw_fixed time_in_self_refresh;
-+	struct bw_fixed stutter_efficiency;
-+	struct bw_fixed worst_number_of_trips_to_memory;
-+	struct bw_fixed immediate_flip_time;
-+	struct bw_fixed latency_for_non_dmif_clients;
-+	struct bw_fixed latency_for_non_mcifwr_clients;
-+	struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk;
-+	struct bw_fixed nbp_state_dram_speed_change_margin;
-+	struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency;
-+	bool use_alpha[maximum_number_of_surfaces];
-+	bool orthogonal_rotation[maximum_number_of_surfaces];
-+	bool enable[maximum_number_of_surfaces];
-+	bool access_one_channel_only[maximum_number_of_surfaces];
-+	bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];
-+	bool interlace_mode[maximum_number_of_surfaces];
-+	struct bw_fixed bytes_per_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed h_total[maximum_number_of_surfaces];
-+	struct bw_fixed pixel_rate[maximum_number_of_surfaces];
-+	struct bw_fixed src_width[maximum_number_of_surfaces];
-+	struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces];
-+	struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces];
-+	struct bw_fixed src_height[maximum_number_of_surfaces];
-+	struct bw_fixed scale_ratio[maximum_number_of_surfaces];
-+	struct bw_fixed h_taps[maximum_number_of_surfaces];
-+	struct bw_fixed v_taps[maximum_number_of_surfaces];
-+	struct bw_fixed rotation_angle[maximum_number_of_surfaces];
-+	struct bw_fixed lb_bpc[maximum_number_of_surfaces];
-+	struct bw_fixed compression_rate[maximum_number_of_surfaces];
-+	struct bw_fixed hsr[maximum_number_of_surfaces];
-+	struct bw_fixed vsr[maximum_number_of_surfaces];
-+	struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces];
-+	struct bw_fixed source_width_pixels[maximum_number_of_surfaces];
-+	struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces];
-+	struct bw_fixed display_bandwidth[maximum_number_of_surfaces];
-+	struct bw_fixed request_bandwidth[maximum_number_of_surfaces];
-+	struct bw_fixed bytes_per_request[maximum_number_of_surfaces];
-+	struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces];
-+	struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces];
-+	struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces];
-+	struct bw_fixed lb_partitions[maximum_number_of_surfaces];
-+	struct bw_fixed lb_partitions_max[maximum_number_of_surfaces];
-+	struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces];
-+	struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces];
-+	struct bw_fixed data_buffer_size[maximum_number_of_surfaces];
-+	struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces];
-+	struct bw_fixed urgent_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed v_filter_init[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces];
-+	struct bw_fixed average_bandwidth[maximum_number_of_surfaces];
-+	struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces];
-+	struct bw_fixed lb_size_per_component[maximum_number_of_surfaces];
-+	struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces];
-+	struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces];
-+	struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces];
-+	struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces];
-+	struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces];
-+	struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces];
-+	struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces];
-+	struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces];
-+	struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces];
-+	struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces];
-+	struct bw_fixed line_buffer_prefetch[maximum_number_of_surfaces];
-+	struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces];
-+	struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces];
-+	struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces];
-+	struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces];
-+	struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed active_time[maximum_number_of_surfaces];
-+	struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces];
-+	struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces];
-+	struct bw_fixed dmif_burst_time[3][3];
-+	struct bw_fixed mcifwr_burst_time[3][3];
-+	struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][3];
-+	struct bw_fixed dram_speed_change_margin[3][3];
-+	struct bw_fixed dispclk_required_for_dram_speed_change[3][3];
-+	struct bw_fixed blackout_duration_margin[3][3];
-+	struct bw_fixed dispclk_required_for_blackout_duration[3][3];
-+	struct bw_fixed dispclk_required_for_blackout_recovery[3][3];
-+	struct bw_fixed dmif_required_sclk_for_urgent_latency[6];
-+};
-+
-+struct bw_watermarks {
-+	uint32_t a_mark;
-+	uint32_t b_mark;
-+};
-+
-+struct bw_calcs_output {
-+	bool cpuc_state_change_enable;
-+	bool cpup_state_change_enable;
-+	bool stutter_mode_enable;
-+	bool nbp_state_change_enable;
-+	struct bw_watermarks urgent_watermark[4];
-+	struct bw_watermarks stutter_exit_watermark[4];
-+	struct bw_watermarks nbp_state_change_watermark[4];
-+	uint32_t required_sclk;
-+	uint32_t dispclk;
-+};
-+
-+
-+/**
-+ * Initialize structures with data which will NOT change at runtime.
-+ */
-+void bw_calcs_init(
-+	struct bw_calcs_input_dceip *bw_dceip,
-+	struct bw_calcs_input_vbios *bw_vbios);
-+
-+/**
-+ * Return:
-+ *	true -	Display(s) configuration supported.
-+ *		In this case 'calcs_output' contains data for HW programming
-+ *	false - Display(s) configuration not supported (not enough bandwidth).
-+ */
-+bool bw_calcs(
-+	struct dc_context *ctx,
-+	const struct bw_calcs_input_dceip *dceip,
-+	const struct bw_calcs_input_vbios *vbios,
-+	const struct bw_calcs_input_mode_data *mode_data,
-+	struct bw_calcs_output *calcs_output);
-+
-+
-+#endif /* __BANDWIDTH_CALCS_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-new file mode 100644
-index 0000000..f9e267b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-@@ -0,0 +1,60 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef BW_FIXED_H_
-+#define BW_FIXED_H_
-+
-+struct bw_fixed {
-+	signed long long value;
-+};
-+
-+struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3);
-+
-+struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3);
-+
-+struct bw_fixed int_to_fixed(long long value);
-+
-+struct bw_fixed frc_to_fixed(long long num, long long denum);
-+
-+struct bw_fixed fixed31_32_to_bw_fixed(long long raw);
-+
-+struct bw_fixed add(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed sub(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+
-+struct bw_fixed bw_min(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_max(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed significance);
-+struct bw_fixed bw_ceil(const struct bw_fixed arg, const struct bw_fixed significance);
-+
-+bool equ(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool neq(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool leq(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool geq(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool ltn(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool gtn(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+
-+#endif //BW_FIXED_H_
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-new file mode 100644
-index 0000000..4992ffd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-@@ -0,0 +1,140 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMPRESSOR_H__
-+#define __DAL_COMPRESSOR_H__
-+
-+#include "include/grph_object_id.h"
-+
-+enum fbc_compress_ratio {
-+	FBC_COMPRESS_RATIO_INVALID = 0,
-+	FBC_COMPRESS_RATIO_1TO1 = 1,
-+	FBC_COMPRESS_RATIO_2TO1 = 2,
-+	FBC_COMPRESS_RATIO_4TO1 = 4,
-+	FBC_COMPRESS_RATIO_8TO1 = 8,
-+};
-+
-+union fbc_physical_address {
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	} addr;
-+};
-+
-+struct compr_addr_and_pitch_params {
-+	uint32_t inst;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+};
-+
-+struct fbc_lpt_config {
-+	uint32_t mem_channels_num;
-+	uint32_t banks_num;
-+	uint32_t chan_interleave_size;
-+	uint32_t row_size;
-+};
-+
-+struct fbc_input_info {
-+	bool dynamic_fbc_buffer_alloc;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+	uint32_t active_targets_num;
-+	struct fbc_lpt_config lpt_config;
-+};
-+
-+struct fbc_requested_compressed_size {
-+	uint32_t preferred_size;
-+	uint32_t preferred_size_alignment;
-+	uint32_t min_size;
-+	uint32_t min_size_alignment;
-+	union {
-+		struct {
-+			/*Above preferred_size must be allocated in FB pool */
-+			uint32_t PREFERRED_MUST_BE_FRAME_BUFFER_POOL:1;
-+			/*Above min_size must be allocated in FB pool */
-+			uint32_t MIN_MUST_BE_FRAME_BUFFER_POOL:1;
-+		} flags;
-+		uint32_t bits;
-+	};
-+};
-+
-+struct fbc_compressed_surface_info {
-+	union fbc_physical_address compressed_surface_address;
-+	uint32_t allocated_size;
-+	union {
-+		struct {
-+			uint32_t FB_POOL:1; /*Allocated in FB Pool */
-+			uint32_t DYNAMIC_ALLOC:1; /*Dynamic allocation */
-+		} allocation_flags;
-+		uint32_t bits;
-+	};
-+};
-+
-+enum fbc_hw_max_resolution_supported {
-+	FBC_MAX_X = 3840,
-+	FBC_MAX_Y = 2400
-+};
-+
-+struct fbc_max_resolution_supported {
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+};
-+
-+struct compressor {
-+	struct dc_context *ctx;
-+	uint32_t attached_inst;
-+	bool is_enabled;
-+
-+	union {
-+		uint32_t raw;
-+		struct {
-+			uint32_t FBC_SUPPORT:1;
-+			uint32_t FB_POOL:1;
-+			uint32_t DYNAMIC_ALLOC:1;
-+			uint32_t LPT_SUPPORT:1;
-+			uint32_t LPT_MC_CONFIG:1;
-+			uint32_t DUMMY_BACKEND:1;
-+			uint32_t CLK_GATING_DISABLED:1;
-+
-+		} bits;
-+	} options;
-+
-+	union fbc_physical_address compr_surface_address;
-+
-+	uint32_t embedded_panel_h_size;
-+	uint32_t embedded_panel_v_size;
-+	uint32_t memory_bus_width;
-+	uint32_t banks_num;
-+	uint32_t raw_size;
-+	uint32_t channel_interleave_size;
-+	uint32_t dram_channels_num;
-+
-+	uint32_t allocated_size;
-+	uint32_t preferred_requested_size;
-+	uint32_t lpt_channels_num;
-+	enum fbc_compress_ratio min_compress_ratio;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-new file mode 100644
-index 0000000..dc246e8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -0,0 +1,39 @@
-+/*
-+ * core_dc.h
-+ *
-+ *  Created on: Nov 13, 2015
-+ *      Author: yonsun
-+ */
-+
-+#ifndef __CORE_DC_H__
-+#define __CORE_DC_H__
-+
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+
-+
-+struct dc {
-+	struct dc_context *ctx;
-+
-+	/** link-related data - begin **/
-+	uint8_t link_count;
-+	struct core_link **links;
-+	/** link-related data - end **/
-+
-+	/* TODO: determine max number of targets*/
-+	struct validate_context current_context;
-+	struct resource_pool res_pool;
-+
-+	/*Power State*/
-+	enum dc_video_power_state previous_power_state;
-+	enum dc_video_power_state current_power_state;
-+
-+	/* Inputs into BW and WM calculations. */
-+	struct bw_calcs_input_dceip bw_dceip;
-+	struct bw_calcs_input_vbios bw_vbios;
-+
-+	/* HW functions */
-+	struct hw_sequencer_funcs hwss;
-+};
-+
-+#endif /* __CORE_DC_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_status.h b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-new file mode 100644
-index 0000000..9682cf8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _CORE_STATUS_H_
-+#define _CORE_STATUS_H_
-+
-+enum dc_status {
-+	DC_OK = 1,
-+
-+	DC_NO_CONTROLLER_RESOURCE,
-+	DC_NO_STREAM_ENG_RESOURCE,
-+	DC_NO_STREAM_AUDIO_RESOURCE,
-+	DC_NO_CLOCK_SOURCE_RESOURCE,
-+	DC_FAIL_CONTROLLER_VALIDATE,
-+	DC_FAIL_ENC_VALIDATE,
-+	DC_FAIL_ATTACH_SURFACES,
-+	DC_NO_DP_LINK_BANDWIDTH,
-+	DC_EXCEED_DONGLE_MAX_CLK,
-+	DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */
-+
-+	DC_ERROR_UNEXPECTED = -1
-+};
-+
-+#endif /* _CORE_STATUS_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-new file mode 100644
-index 0000000..22ab6cb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -0,0 +1,308 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _CORE_TYPES_H_
-+#define _CORE_TYPES_H_
-+
-+#include "dc.h"
-+#include "bandwidth_calcs.h"
-+#include "ddc_service_types.h"
-+
-+struct core_stream;
-+/********* core_target *************/
-+
-+#define CONST_DC_TARGET_TO_CORE(dc_target) \
-+	container_of(dc_target, const struct core_target, public)
-+#define DC_TARGET_TO_CORE(dc_target) \
-+	container_of(dc_target, struct core_target, public)
-+
-+#define MAX_PIPES 6
-+#define MAX_STREAMS 6
-+#define MAX_CLOCK_SOURCES 4
-+
-+struct core_target {
-+	struct dc_target public;
-+	struct dc_target_status status;
-+
-+	struct core_stream *streams[MAX_STREAMS];
-+	uint8_t stream_count;
-+	struct dc_context *ctx;
-+};
-+
-+/********* core_surface **********/
-+#define DC_SURFACE_TO_CORE(dc_surface) \
-+	container_of(dc_surface, struct core_surface, public)
-+
-+struct core_surface {
-+	struct dc_surface public;
-+	struct dc_surface_status status;
-+	struct dc_context *ctx;
-+};
-+
-+void enable_surface_flip_reporting(struct dc_surface *dc_surface,
-+		uint32_t controller_id);
-+
-+/********* core_stream ************/
-+#include "grph_object_id.h"
-+#include "encoder_interface.h"
-+#include "clock_source_interface.h"
-+#include "audio_interface.h"
-+
-+#define DC_STREAM_TO_CORE(dc_stream) container_of( \
-+	dc_stream, struct core_stream, public)
-+
-+#define PIXEL_CLOCK	27030
-+
-+struct core_stream {
-+	struct dc_stream public;
-+
-+	/* field internal to DC */
-+	const struct core_sink *sink;
-+
-+	struct clock_source *clock_source;
-+
-+	struct mem_input *mi;
-+	struct input_pixel_processor *ipp;
-+	struct transform *xfm;
-+	struct output_pixel_processor *opp;
-+	struct timing_generator *tg;
-+	struct stream_encoder *stream_enc;
-+	struct display_clock *dis_clk;
-+
-+	struct overscan_info overscan;
-+	struct scaling_ratios ratios;
-+	struct rect viewport;
-+	struct scaling_taps taps;
-+	enum pixel_format format;
-+
-+	uint8_t controller_idx;
-+
-+	struct audio *audio;
-+
-+	enum signal_type signal;
-+
-+	/* TODO: move these members into appropriate places (work in progress)*/
-+	/* timing validation (HDMI only) */
-+	uint32_t max_tmds_clk_from_edid_in_mhz;
-+	/* maximum supported deep color depth for HDMI */
-+	enum dc_color_depth max_hdmi_deep_color;
-+	/* maximum supported pixel clock for HDMI */
-+	uint32_t max_hdmi_pixel_clock;
-+	/* end of TODO */
-+
-+	/*TODO: AUTO merge if possible*/
-+	struct pixel_clk_params pix_clk_params;
-+	struct pll_settings pll_settings;
-+
-+	/*fmt*/
-+	/*TODO: AUTO new codepath in apply_context to hw to
-+	 * generate these bw unrelated/no fail params*/
-+	struct bit_depth_reduction_params fmt_bit_depth;
-+	struct clamping_and_pixel_encoding_params clamping;
-+	struct hw_info_frame info_frame;
-+	struct encoder_info_frame encoder_info_frame;
-+
-+	struct audio_output audio_output;
-+	struct dc_context *ctx;
-+};
-+
-+
-+/************ core_sink *****************/
-+
-+#define DC_SINK_TO_CORE(dc_sink) \
-+	container_of(dc_sink, struct core_sink, public)
-+
-+struct core_sink {
-+	/** The public, read-only (for DM) area of sink. **/
-+	struct dc_sink public;
-+	/** End-of-public area. **/
-+
-+	/** The 'protected' area - read/write access, for use only inside DC **/
-+	/* not used for now */
-+	struct core_link *link;
-+	struct dc_context *ctx;
-+	uint32_t dongle_max_pix_clk;
-+	bool converter_disable_audio;
-+};
-+
-+/************ link *****************/
-+#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public)
-+
-+struct link_init_data {
-+	const struct dc *dc;
-+	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
-+	uint32_t connector_index; /* this will be mapped to the HPD pins */
-+	uint32_t link_index; /* this is mapped to DAL display_index
-+				TODO: remove it when DC is complete. */
-+	struct adapter_service *adapter_srv;
-+};
-+
-+struct link_caps {
-+	/* support for Spread Spectrum(SS) */
-+	bool ss_supported;
-+	/* DP link settings (laneCount, linkRate, Spread) */
-+	uint32_t lane_count;
-+	uint32_t rate;
-+	uint32_t spread;
-+	enum dpcd_revision dpcd_revision;
-+};
-+
-+struct dpcd_caps {
-+	union dpcd_rev dpcd_rev;
-+	union max_lane_count max_ln_count;
-+
-+	/* dongle type (DP converter, CV smart dongle) */
-+	enum display_dongle_type dongle_type;
-+	/* Dongle's downstream count. */
-+	union sink_count sink_count;
-+	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
-+	bool is_dp_hdmi_s3d_converter;
-+
-+	bool allow_invalid_MSA_timing_param;
-+	bool panel_mode_edp;
-+	uint32_t sink_dev_id;
-+	uint32_t branch_dev_id;
-+	int8_t branch_dev_name[6];
-+};
-+
-+union dp_wa {
-+	struct {
-+		/* keep DP receiver powered up on DisplayOutput */
-+		uint32_t KEEP_RECEIVER_POWERED:1;
-+
-+		/* TODO: may add other member in.*/
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct core_link {
-+	struct dc_link public;
-+	const struct dc *dc;
-+
-+	struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/
-+
-+	uint8_t connector_index; /* this will be mapped to the HPD pins */
-+	uint8_t link_index; /* this is mapped to DAL display_index
-+				TODO: #flip remove it as soon as possible. */
-+
-+	struct adapter_service *adapter_srv;
-+	struct connector *connector;
-+	struct link_encoder *link_enc;
-+	struct ddc_service *ddc;
-+	struct graphics_object_id link_id;
-+	/* caps is the same as reported_link_cap. link_traing use
-+	 * reported_link_cap. Will clean up.  TODO */
-+	struct link_settings reported_link_cap;
-+	struct link_settings verified_link_cap;
-+	struct link_settings max_link_setting;
-+	struct link_settings cur_link_settings;
-+	struct lane_settings ln_setting;
-+	struct dpcd_caps dpcd_caps;
-+	unsigned int dpcd_sink_count;
-+
-+	enum edp_revision edp_revision;
-+	union dp_wa dp_wa;
-+};
-+
-+#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-+
-+struct core_link *link_create(const struct link_init_data *init_params);
-+void link_destroy(struct core_link **link);
-+enum dc_status core_link_enable(struct core_stream *stream);
-+
-+enum dc_status core_link_disable(struct core_stream *stream);
-+
-+enum dc_status dc_link_validate_mode_timing(
-+		const struct core_sink *sink,
-+		struct core_link *link,
-+		const struct dc_crtc_timing *timing);
-+
-+void core_link_resume(struct core_link *link);
-+
-+/********** DAL Core*********************/
-+#include "display_clock_interface.h"
-+
-+struct resource_pool {
-+	struct scaler_filter * scaler_filter;
-+
-+	struct mem_input *mis[MAX_PIPES];
-+	struct input_pixel_processor *ipps[MAX_PIPES];
-+	struct transform *transforms[MAX_PIPES];
-+	struct output_pixel_processor *opps[MAX_PIPES];
-+	struct timing_generator *timing_generators[MAX_STREAMS];
-+	struct stream_encoder *stream_enc[MAX_STREAMS];
-+
-+	uint8_t controller_count;
-+	uint8_t stream_enc_count;
-+
-+	union supported_stream_engines stream_engines;
-+
-+	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
-+	uint8_t clk_src_count;
-+
-+	struct audio *audios[MAX_STREAMS];
-+	uint8_t audio_count;
-+
-+	struct display_clock *display_clock;
-+	struct adapter_service *adapter_srv;
-+	struct irq_service *irqs;
-+};
-+
-+struct controller_ctx {
-+	struct core_surface *surface;
-+	struct core_stream *stream;
-+	struct flags {
-+		bool unchanged;
-+		bool timing_changed;
-+	} flags;
-+};
-+
-+struct resource_context {
-+	struct resource_pool pool;
-+	struct controller_ctx controller_ctx[MAX_PIPES];
-+	union supported_stream_engines used_stream_engines;
-+	bool is_stream_enc_acquired[MAX_STREAMS];
-+	bool is_audio_acquired[MAX_STREAMS];
-+	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
-+ };
-+
-+struct target_flags {
-+	bool unchanged;
-+};
-+struct validate_context {
-+	struct core_target *targets[MAX_PIPES];
-+	struct target_flags target_flags[MAX_PIPES];
-+	uint8_t target_count;
-+
-+	struct resource_context res_ctx;
-+
-+	struct bw_calcs_input_mode_data bw_mode_data;
-+	/* The output from BW and WM calculations. */
-+	struct bw_calcs_output bw_results;
-+};
-+
-+
-+#endif /* _CORE_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-new file mode 100644
-index 0000000..e3e4778
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-@@ -0,0 +1,51 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_DP_H__
-+#define __DC_LINK_DP_H__
-+
-+bool dp_hbr_verify_link_cap(
-+	struct core_link *link,
-+	struct link_settings *known_limit_link_setting);
-+
-+bool dp_validate_mode_timing(
-+	struct core_link *link,
-+	const struct dc_crtc_timing *timing);
-+
-+void decide_link_settings(
-+	struct core_stream *stream,
-+	struct link_settings *link_setting);
-+
-+bool perform_link_training(
-+	struct core_link *link,
-+	const struct link_settings *link_setting,
-+	bool skip_video_pattern);
-+
-+/*dp mst functions*/
-+bool is_mst_supported(struct core_link *link);
-+
-+void detect_dp_sink_caps(struct core_link *link);
-+
-+#endif /* __DC_LINK_DP_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-new file mode 100644
-index 0000000..2c5738f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -0,0 +1,170 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HW_SEQUENCER_H__
-+#define __DC_HW_SEQUENCER_H__
-+#include "core_types.h"
-+
-+struct hw_sequencer_funcs {
-+
-+	enum dc_status (*apply_ctx_to_hw)(
-+					const struct dc *dc,
-+					struct validate_context *context);
-+
-+	void (*reset_hw_ctx)(struct dc *dc,
-+					struct validate_context *context,
-+					uint8_t target_count);
-+
-+	bool (*set_plane_config)(
-+					struct core_surface *surface,
-+					struct core_target *target);
-+
-+	bool (*update_plane_address)(
-+					const struct core_surface *surface,
-+					struct core_target *target);
-+
-+	bool (*enable_memory_requests)(struct timing_generator *tg);
-+
-+	bool (*disable_memory_requests)(struct timing_generator *tg);
-+
-+	bool (*transform_power_up)(struct transform *xfm);
-+
-+	bool (*cursor_set_attributes)(
-+					struct input_pixel_processor *ipp,
-+					const struct dc_cursor_attributes *attributes);
-+
-+	bool (*cursor_set_position)(
-+					struct input_pixel_processor *ipp,
-+					const struct dc_cursor_position *position);
-+
-+	bool (*set_gamma_ramp)(
-+					struct input_pixel_processor *ipp,
-+					struct output_pixel_processor *opp,
-+					const struct gamma_ramp *ramp,
-+					const struct gamma_parameters *params);
-+
-+	void (*power_down)(struct validate_context *context);
-+
-+	void (*enable_accelerated_mode)(struct validate_context *context);
-+
-+	void (*get_crtc_positions)(
-+					struct timing_generator *tg,
-+					int32_t *h_position,
-+					int32_t *v_position);
-+
-+	uint32_t (*get_vblank_counter)(struct timing_generator *tg);
-+
-+	void (*enable_timing_synchronization)(
-+					struct dc_context *dc_ctx,
-+					uint32_t timing_generator_num,
-+					struct timing_generator *tgs[]);
-+
-+	void (*disable_vga)(struct timing_generator *tg);
-+
-+
-+
-+	/* link encoder sequences */
-+	struct link_encoder *(*encoder_create)(const struct encoder_init_data *init);
-+
-+	void (*encoder_destroy)(struct link_encoder **enc);
-+
-+	enum encoder_result (*encoder_power_up)(
-+					struct link_encoder *enc);
-+
-+	enum encoder_result (*encoder_enable_output)(
-+					struct link_encoder *enc,
-+					const struct link_settings *link_settings,
-+					enum engine_id engine,
-+					enum clock_source_id clock_source,
-+					enum signal_type signal,
-+					enum dc_color_depth color_depth,
-+					uint32_t pixel_clock);
-+
-+	enum encoder_result (*encoder_disable_output)(
-+					struct link_encoder *enc,
-+					enum signal_type signal);
-+
-+	void (*encoder_set_dp_phy_pattern)(
-+					struct link_encoder *enc,
-+					const struct encoder_set_dp_phy_pattern_param *param);
-+
-+	enum encoder_result (*encoder_dp_set_lane_settings)(
-+					struct link_encoder *enc,
-+					const struct link_training_settings *link_settings);
-+
-+	/* backlight control */
-+	void (*encoder_set_lcd_backlight_level)(struct link_encoder *enc,
-+					uint32_t level);
-+
-+
-+	/* power management */
-+	void (*clock_gating_power_up)(
-+					struct dc_context *ctx,
-+					bool enable);
-+
-+	void (*enable_display_pipe_clock_gating)(
-+					struct dc_context *ctx,
-+					bool clock_gating);
-+
-+	bool (*enable_display_power_gating)(
-+					struct dc_context *ctx,
-+					uint8_t controller_id,
-+					struct bios_parser *bp,
-+					enum pipe_gating_control power_gating);
-+
-+	void (*set_afmt_memory_power_state)(
-+					const struct dc_context *ctx,
-+					enum engine_id id,
-+					bool enable);
-+
-+	/* resource management and validation*/
-+	bool (*construct_resource_pool)(
-+					struct adapter_service *adapter_serv,
-+					struct dc *dc,
-+					struct resource_pool *pool);
-+
-+	void (*destruct_resource_pool)(struct resource_pool *pool);
-+
-+	enum dc_status (*validate_with_context)(
-+					const struct dc *dc,
-+					const struct dc_validation_set set[],
-+					uint8_t set_count,
-+					struct validate_context *context);
-+
-+	enum dc_status (*validate_bandwidth)(
-+					const struct dc *dc,
-+					struct validate_context *context);
-+	void (*program_bw)(
-+					struct dc *dc,
-+					struct validate_context *context);
-+
-+};
-+
-+bool dc_construct_hw_sequencer(
-+				struct adapter_service *adapter_serv,
-+				struct dc *dc);
-+
-+
-+#endif /* __DC_HW_SEQUENCER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-new file mode 100644
-index 0000000..602b4cb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -0,0 +1,66 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IPP_H__
-+#define __DAL_IPP_H__
-+
-+#include "include/plane_types.h"
-+#include "include/grph_object_id.h"
-+#include "include/grph_csc_types.h"
-+#include "include/video_csc_types.h"
-+#include "include/hw_sequencer_types.h"
-+
-+
-+#define MAXTRIX_COEFFICIENTS_NUMBER 12
-+#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
-+#define MAX_OVL_MATRIX_COUNT 12
-+
-+/* IPP RELATED */
-+struct input_pixel_processor {
-+	struct  dc_context *ctx;
-+	uint32_t inst;
-+};
-+
-+enum wide_gamut_degamma_mode {
-+	/*  00  - BITS1:0 Bypass */
-+	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_BYPASS,
-+	/*  0x1 - PWL gamma ROM A */
-+	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_PWL_ROM_A,
-+	/*  0x2 - PWL gamma ROM B */
-+	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_PWL_ROM_B,
-+	/*  00  - BITS5:4 Bypass */
-+	WIDE_GAMUT_DEGAMMA_MODE_OVL_BYPASS,
-+	/*  0x1 - PWL gamma ROM A */
-+	WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_A,
-+	/*  0x2 - PWL gamma ROM B */
-+	WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_B,
-+};
-+
-+struct dcp_video_matrix {
-+	enum ovl_color_space color_space;
-+	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
-+};
-+
-+#endif /* __DAL_IPP_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-new file mode 100644
-index 0000000..7110357
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -0,0 +1,67 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_HWSS_H__
-+#define __DC_LINK_HWSS_H__
-+
-+#include "inc/core_status.h"
-+
-+enum dc_status core_link_read_dpcd(
-+	struct core_link* link,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t size);
-+
-+enum dc_status core_link_write_dpcd(
-+	struct core_link* link,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t size);
-+
-+enum dc_status dp_enable_link_phy(
-+	struct core_link *link,
-+	enum signal_type signal,
-+	enum engine_id engine,
-+	const struct link_settings *link_settings);
-+
-+void dp_receiver_power_ctrl(struct core_link *link, bool on);
-+
-+void dp_disable_link_phy(struct core_link *link, enum signal_type signal);
-+
-+bool dp_set_hw_training_pattern(
-+	struct core_link *link,
-+	enum hw_dp_training_pattern pattern);
-+
-+bool dp_set_hw_lane_settings(
-+	struct core_link *link,
-+	const struct link_training_settings *link_settings);
-+
-+void dp_set_hw_test_pattern(
-+	struct core_link *link,
-+	enum dp_test_pattern test_pattern);
-+
-+enum dp_panel_mode dp_get_panel_mode(struct core_link *link);
-+
-+#endif /* __DC_LINK_HWSS_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-new file mode 100644
-index 0000000..458e7b5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -0,0 +1,55 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_MEM_INPUT_H__
-+#define __DAL_MEM_INPUT_H__
-+
-+#include "include/plane_types.h"
-+#include "include/grph_object_id.h"
-+#include "dc.h"
-+
-+struct mem_input {
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+};
-+
-+enum stutter_mode_type {
-+	STUTTER_MODE_LEGACY = 0X00000001,
-+	STUTTER_MODE_ENHANCED = 0X00000002,
-+	STUTTER_MODE_FID_NBP_STATE = 0X00000004,
-+	STUTTER_MODE_WATERMARK_NBP_STATE = 0X00000008,
-+	STUTTER_MODE_SINGLE_DISPLAY_MODEL = 0X00000010,
-+	STUTTER_MODE_MIXED_DISPLAY_MODEL = 0X00000020,
-+	STUTTER_MODE_DUAL_DMIF_BUFFER = 0X00000040,
-+	STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION = 0X00000080,
-+	STUTTER_MODE_NO_ADVANCED_REQUEST = 0X00000100,
-+	STUTTER_MODE_NO_LB_RESET = 0X00000200,
-+	STUTTER_MODE_DISABLED = 0X00000400,
-+	STUTTER_MODE_AGGRESSIVE_MARKS = 0X00000800,
-+	STUTTER_MODE_URGENCY = 0X00001000,
-+	STUTTER_MODE_QUAD_DMIF_BUFFER = 0X00002000,
-+	STUTTER_MODE_NOT_USED = 0X00008000
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-new file mode 100644
-index 0000000..3293e3b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -0,0 +1,206 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_OPP_H__
-+#define __DAL_OPP_H__
-+
-+#include "dc_temp.h"
-+#include "grph_object_id.h"
-+#include "grph_csc_types.h"
-+
-+struct fixed31_32;
-+
-+/* TODO: Need cleanup */
-+
-+enum wide_gamut_regamma_mode {
-+	/*  0x0  - BITS2:0 Bypass */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
-+	/*  0x1  - Fixed curve sRGB 2.4 */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24,
-+	/*  0x2  - Fixed curve xvYCC 2.22 */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22,
-+	/*  0x3  - Programmable control A */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A,
-+	/*  0x4  - Programmable control B */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B,
-+	/*  0x0  - BITS6:4 Bypass */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS,
-+	/*  0x1  - Fixed curve sRGB 2.4 */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24,
-+	/*  0x2  - Fixed curve xvYCC 2.22 */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22,
-+	/*  0x3  - Programmable control A */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A,
-+	/*  0x4  - Programmable control B */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
-+};
-+
-+struct pwl_result_data {
-+	struct fixed31_32 red;
-+	struct fixed31_32 green;
-+	struct fixed31_32 blue;
-+
-+	struct fixed31_32 delta_red;
-+	struct fixed31_32 delta_green;
-+	struct fixed31_32 delta_blue;
-+
-+	uint32_t red_reg;
-+	uint32_t green_reg;
-+	uint32_t blue_reg;
-+
-+	uint32_t delta_red_reg;
-+	uint32_t delta_green_reg;
-+	uint32_t delta_blue_reg;
-+};
-+
-+struct gamma_pixel {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+};
-+
-+struct gamma_curve {
-+	uint32_t offset;
-+	uint32_t segments_num;
-+};
-+
-+struct curve_points {
-+	struct fixed31_32 x;
-+	struct fixed31_32 y;
-+	struct fixed31_32 offset;
-+	struct fixed31_32 slope;
-+
-+	uint32_t custom_float_x;
-+	uint32_t custom_float_y;
-+	uint32_t custom_float_offset;
-+	uint32_t custom_float_slope;
-+};
-+
-+enum channel_name {
-+	CHANNEL_NAME_RED,
-+	CHANNEL_NAME_GREEN,
-+	CHANNEL_NAME_BLUE
-+};
-+
-+struct custom_float_format {
-+	uint32_t mantissa_bits;
-+	uint32_t exponenta_bits;
-+	bool sign;
-+};
-+
-+struct custom_float_value {
-+	uint32_t mantissa;
-+	uint32_t exponenta;
-+	uint32_t value;
-+	bool negative;
-+};
-+
-+struct hw_x_point {
-+	uint32_t custom_float_x;
-+	uint32_t custom_float_x_adjusted;
-+	struct fixed31_32 x;
-+	struct fixed31_32 adjusted_x;
-+	struct fixed31_32 regamma_y_red;
-+	struct fixed31_32 regamma_y_green;
-+	struct fixed31_32 regamma_y_blue;
-+
-+};
-+
-+struct pwl_float_data_ex {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+	struct fixed31_32 delta_r;
-+	struct fixed31_32 delta_g;
-+	struct fixed31_32 delta_b;
-+};
-+
-+enum hw_point_position {
-+	/* hw point sits between left and right sw points */
-+	HW_POINT_POSITION_MIDDLE,
-+	/* hw point lays left from left (smaller) sw point */
-+	HW_POINT_POSITION_LEFT,
-+	/* hw point lays stays from right (bigger) sw point */
-+	HW_POINT_POSITION_RIGHT
-+};
-+
-+struct gamma_point {
-+	int32_t left_index;
-+	int32_t right_index;
-+	enum hw_point_position pos;
-+	struct fixed31_32 coeff;
-+};
-+
-+struct pixel_gamma_point {
-+	struct gamma_point r;
-+	struct gamma_point g;
-+	struct gamma_point b;
-+};
-+
-+struct gamma_coefficients {
-+	struct fixed31_32 a0[3];
-+	struct fixed31_32 a1[3];
-+	struct fixed31_32 a2[3];
-+	struct fixed31_32 a3[3];
-+	struct fixed31_32 user_gamma[3];
-+	struct fixed31_32 user_contrast;
-+	struct fixed31_32 user_brightness;
-+};
-+
-+struct csc_adjustments {
-+	struct fixed31_32 contrast;
-+	struct fixed31_32 saturation;
-+	struct fixed31_32 brightness;
-+	struct fixed31_32 hue;
-+};
-+
-+struct pwl_float_data {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+};
-+
-+
-+/* TODO: Use when we redefine the OPP interface */
-+enum opp_regamma {
-+	OPP_REGAMMA_BYPASS = 0,
-+	OPP_REGAMMA_SRGB,
-+	OPP_REGAMMA_3_6,
-+	OPP_REGAMMA_PQ,
-+	OPP_REGAMMA_PQ_INTERIM,
-+};
-+
-+struct output_pixel_processor {
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+};
-+
-+enum fmt_stereo_action {
-+	FMT_STEREO_ACTION_ENABLE = 0,
-+	FMT_STEREO_ACTION_DISABLE,
-+	FMT_STEREO_ACTION_UPDATE_POLARITY
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-new file mode 100644
-index 0000000..0e0ba47
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -0,0 +1,61 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_
-+#define DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_
-+
-+#include "core_types.h"
-+#include "core_status.h"
-+#include "core_dc.h"
-+
-+void build_scaling_params(
-+	const struct dc_surface *surface,
-+	struct core_stream *stream);
-+
-+void build_scaling_params_for_context(
-+	const struct dc *dc,
-+	struct validate_context *context);
-+
-+void unreference_clock_source(
-+		struct resource_context *res_ctx,
-+		struct clock_source *clock_source);
-+
-+void reference_clock_source(
-+		struct resource_context *res_ctx,
-+		struct clock_source *clock_source);
-+
-+bool is_same_timing(
-+	const struct dc_crtc_timing *timing1,
-+	const struct dc_crtc_timing *timing2);
-+
-+struct clock_source *find_used_clk_src_for_sharing(
-+		struct validate_context *context,
-+		struct core_stream *stream);
-+
-+bool logical_attach_surfaces_to_target(
-+		struct dc_surface *surfaces[],
-+		uint8_t surface_count,
-+		struct dc_target *dc_target);
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-new file mode 100644
-index 0000000..8e111ce
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -0,0 +1,81 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_H__
-+#define __DAL_TRANSFORM_H__
-+
-+#include "include/scaler_types.h"
-+#include "calcs/scaler_filter.h"
-+#include "grph_object_id.h"
-+
-+enum scaling_type {
-+	SCALING_TYPE_NO_SCALING = 0,
-+	SCALING_TYPE_UPSCALING,
-+	SCALING_TYPE_DOWNSCALING
-+};
-+
-+struct transform {
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+	struct scaler_filter *filter;
-+};
-+
-+struct scaler_taps_and_ratio {
-+	uint32_t h_tap;
-+	uint32_t v_tap;
-+	uint32_t lo_ratio;
-+	uint32_t hi_ratio;
-+};
-+
-+struct scaler_taps {
-+	uint32_t h_tap;
-+	uint32_t v_tap;
-+};
-+
-+struct sclv_ratios_inits {
-+	uint32_t chroma_enable;
-+	uint32_t h_int_scale_ratio_luma;
-+	uint32_t h_int_scale_ratio_chroma;
-+	uint32_t v_int_scale_ratio_luma;
-+	uint32_t v_int_scale_ratio_chroma;
-+	struct init_int_and_frac h_init_luma;
-+	struct init_int_and_frac h_init_chroma;
-+	struct init_int_and_frac v_init_luma;
-+	struct init_int_and_frac v_init_chroma;
-+	struct init_int_and_frac h_init_lumabottom;
-+	struct init_int_and_frac h_init_chromabottom;
-+	struct init_int_and_frac v_init_lumabottom;
-+	struct init_int_and_frac v_init_chromabottom;
-+};
-+
-+enum lb_pixel_depth {
-+	/* do not change the values because it is used as bit vector */
-+	LB_PIXEL_DEPTH_18BPP = 1,
-+	LB_PIXEL_DEPTH_24BPP = 2,
-+	LB_PIXEL_DEPTH_30BPP = 4,
-+	LB_PIXEL_DEPTH_36BPP = 8
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/Makefile b/drivers/gpu/drm/amd/dal/dc/irq/Makefile
-new file mode 100644
-index 0000000..f1c5faf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/Makefile
-@@ -0,0 +1,21 @@
-+#
-+# Makefile for the 'audio' sub-component of DAL.
-+# It provides the control and status of HW adapter resources,
-+# that are global for the ASIC and sharable between pipes.
-+
-+IRQ = irq_service.o
-+
-+AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
-+
-+AMD_DAL_FILES += $(AMD_DAL_IRQ)
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-+IRQ_DCE11 = irq_service_dce110.o
-+
-+AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11))
-+
-+AMD_DAL_FILES += $(AMD_DAL_IRQ_DCE11)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-new file mode 100644
-index 0000000..2a4f14c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-@@ -0,0 +1,389 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "irq_service_dce110.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "ivsrcid/ivsrcid_vislands30.h"
-+
-+static bool hpd_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->status_reg;
-+	uint32_t value = dal_read_reg(irq_service->ctx, addr);
-+	uint32_t current_status =
-+		get_reg_field_value(
-+			value,
-+			DC_HPD_INT_STATUS,
-+			DC_HPD_SENSE_DELAYED);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	value = dal_read_reg(irq_service->ctx, info->enable_reg);
-+
-+	set_reg_field_value(
-+		value,
-+		current_status ? 0 : 1,
-+		DC_HPD_INT_CONTROL,
-+		DC_HPD_INT_POLARITY);
-+
-+	dal_write_reg(irq_service->ctx, info->enable_reg, value);
-+
-+	return true;
-+}
-+
-+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = hpd_ack
-+};
-+
-+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+#define hpd_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
-+		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
-+		.enable_value = {\
-+			DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
-+			~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
-+		},\
-+		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
-+		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
-+		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
-+		.funcs = &hpd_irq_info_funcs\
-+	}
-+
-+#define hpd_rx_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
-+		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
-+		.enable_value = {\
-+			DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
-+			~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
-+		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
-+		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
-+		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
-+		.funcs = &hpd_rx_irq_info_funcs\
-+	}
-+#define pflip_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
-+		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
-+		.enable_mask =\
-+		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-+		.enable_value = {\
-+			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-+			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
-+		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
-+		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
-+		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
-+		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
-+		.funcs = &pflip_irq_info_funcs\
-+	}
-+
-+#define vsync_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_CRTC ## reg_num ## VSYNC] = dummy_irq_entry()
-+
-+#define vupdate_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
-+		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
-+		.enable_mask =\
-+		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-+		.enable_value = {\
-+			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-+			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
-+		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
-+		.ack_mask =\
-+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
-+		.ack_value =\
-+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
-+		.funcs = &vblank_irq_info_funcs\
-+	}
-+
-+#define dummy_irq_entry() \
-+	{\
-+		.funcs = &dummy_irq_info_funcs\
-+	}
-+
-+#define i2c_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
-+
-+#define azalia_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_AZALIA ## reg_num] = dummy_irq_entry()
-+
-+#define dp_sink_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
-+
-+#define gpio_pad_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
-+
-+#define dc_underflow_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
-+
-+static bool dummy_set(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable)
-+{
-+	dal_logger_write(
-+		irq_service->ctx->logger,
-+		LOG_MAJOR_ERROR,
-+		LOG_MINOR_COMPONENT_IRQ_SERVICE,
-+		"%s: called for non-implemented irq source\n",
-+		__func__);
-+	return false;
-+}
-+
-+static bool dummy_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	dal_logger_write(
-+		irq_service->ctx->logger,
-+		LOG_MAJOR_ERROR,
-+		LOG_MINOR_COMPONENT_IRQ_SERVICE,
-+		"%s: called for non-implemented irq source\n",
-+		__func__);
-+	return false;
-+}
-+
-+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
-+	.set = dummy_set,
-+	.ack = dummy_ack
-+};
-+
-+static const struct irq_source_info
-+irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
-+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
-+	hpd_int_entry(0),
-+	hpd_int_entry(1),
-+	hpd_int_entry(2),
-+	hpd_int_entry(3),
-+	hpd_int_entry(4),
-+	hpd_int_entry(5),
-+	hpd_rx_int_entry(0),
-+	hpd_rx_int_entry(1),
-+	hpd_rx_int_entry(2),
-+	hpd_rx_int_entry(3),
-+	hpd_rx_int_entry(4),
-+	hpd_rx_int_entry(5),
-+	i2c_int_entry(1),
-+	i2c_int_entry(2),
-+	i2c_int_entry(3),
-+	i2c_int_entry(4),
-+	i2c_int_entry(5),
-+	i2c_int_entry(6),
-+	azalia_int_entry(0),
-+	azalia_int_entry(1),
-+	azalia_int_entry(2),
-+	azalia_int_entry(3),
-+	azalia_int_entry(4),
-+	azalia_int_entry(5),
-+	dp_sink_int_entry(1),
-+	dp_sink_int_entry(2),
-+	dp_sink_int_entry(3),
-+	dp_sink_int_entry(4),
-+	dp_sink_int_entry(5),
-+	dp_sink_int_entry(6),
-+	vsync_int_entry(1),
-+	vsync_int_entry(2),
-+	vsync_int_entry(3),
-+	vsync_int_entry(3),
-+	vsync_int_entry(4),
-+	vsync_int_entry(5),
-+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
-+	pflip_int_entry(0),
-+	pflip_int_entry(1),
-+	pflip_int_entry(2),
-+	pflip_int_entry(3),
-+	pflip_int_entry(4),
-+	pflip_int_entry(5),
-+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
-+	gpio_pad_int_entry(0),
-+	gpio_pad_int_entry(1),
-+	gpio_pad_int_entry(2),
-+	gpio_pad_int_entry(3),
-+	gpio_pad_int_entry(4),
-+	gpio_pad_int_entry(5),
-+	gpio_pad_int_entry(6),
-+	gpio_pad_int_entry(7),
-+	gpio_pad_int_entry(8),
-+	gpio_pad_int_entry(9),
-+	gpio_pad_int_entry(10),
-+	gpio_pad_int_entry(11),
-+	gpio_pad_int_entry(12),
-+	gpio_pad_int_entry(13),
-+	gpio_pad_int_entry(14),
-+	gpio_pad_int_entry(15),
-+	gpio_pad_int_entry(16),
-+	gpio_pad_int_entry(17),
-+	gpio_pad_int_entry(18),
-+	gpio_pad_int_entry(19),
-+	gpio_pad_int_entry(20),
-+	gpio_pad_int_entry(21),
-+	gpio_pad_int_entry(22),
-+	gpio_pad_int_entry(23),
-+	gpio_pad_int_entry(24),
-+	gpio_pad_int_entry(25),
-+	gpio_pad_int_entry(26),
-+	gpio_pad_int_entry(27),
-+	gpio_pad_int_entry(28),
-+	gpio_pad_int_entry(29),
-+	gpio_pad_int_entry(30),
-+	dc_underflow_int_entry(1),
-+	dc_underflow_int_entry(2),
-+	dc_underflow_int_entry(3),
-+	dc_underflow_int_entry(4),
-+	dc_underflow_int_entry(5),
-+	dc_underflow_int_entry(6),
-+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-+	vupdate_int_entry(0),
-+	vupdate_int_entry(1),
-+	vupdate_int_entry(2),
-+	vupdate_int_entry(3),
-+	vupdate_int_entry(4),
-+	vupdate_int_entry(5),
-+};
-+
-+static enum dc_irq_source to_dal_irq_source(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	switch (src_id) {
-+	case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE1;
-+	case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE2;
-+	case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE3;
-+	case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE4;
-+	case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE5;
-+	case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE6;
-+	case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP1;
-+	case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP2;
-+	case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP3;
-+	case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP4;
-+	case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP5;
-+	case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP6;
-+
-+	case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
-+		/* generic src_id for all HPD and HPDRX interrupts */
-+		switch (ext_id) {
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
-+			return DC_IRQ_SOURCE_HPD1;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
-+			return DC_IRQ_SOURCE_HPD2;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
-+			return DC_IRQ_SOURCE_HPD3;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
-+			return DC_IRQ_SOURCE_HPD4;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
-+			return DC_IRQ_SOURCE_HPD5;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
-+			return DC_IRQ_SOURCE_HPD6;
-+		case VISLANDS30_IV_EXTID_HPD_RX_A:
-+			return DC_IRQ_SOURCE_HPD1RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_B:
-+			return DC_IRQ_SOURCE_HPD2RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_C:
-+			return DC_IRQ_SOURCE_HPD3RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_D:
-+			return DC_IRQ_SOURCE_HPD4RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_E:
-+			return DC_IRQ_SOURCE_HPD5RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_F:
-+			return DC_IRQ_SOURCE_HPD6RX;
-+		default:
-+			return DC_IRQ_SOURCE_INVALID;
-+		}
-+		break;
-+
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+static const struct irq_service_funcs irq_service_funcs_dce110 = {
-+		.to_dal_irq_source = to_dal_irq_source
-+};
-+
-+bool construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	if (!dal_irq_service_construct(irq_service, init_data))
-+		return false;
-+
-+	irq_service->info = irq_source_info_dce110;
-+	irq_service->funcs = &irq_service_funcs_dce110;
-+
-+	return true;
-+}
-+
-+struct irq_service *dal_irq_service_dce110_create(
-+	struct irq_service_init_data *init_data)
-+{
-+	struct irq_service *irq_service = dc_service_alloc(init_data->ctx, sizeof(*irq_service));
-+
-+	if (!irq_service)
-+		return NULL;
-+
-+	if (construct(irq_service, init_data))
-+		return irq_service;
-+
-+	dc_service_free(init_data->ctx, irq_service);
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h
-new file mode 100644
-index 0000000..d6c28e9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_DCE110_H__
-+#define __DAL_IRQ_SERVICE_DCE110_H__
-+
-+#include "../irq_service.h"
-+
-+struct irq_service *dal_irq_service_dce110_create(
-+	struct irq_service_init_data *init_data);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-new file mode 100644
-index 0000000..0c7429c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -0,0 +1,173 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/irq_service_interface.h"
-+#include "include/logger_interface.h"
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#include "dce110/irq_service_dce110.h"
-+#endif
-+
-+#include "irq_service.h"
-+
-+bool dal_irq_service_construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	if (!init_data || !init_data->ctx)
-+		return false;
-+
-+	irq_service->ctx = init_data->ctx;
-+	return true;
-+}
-+
-+struct irq_service *dal_irq_service_create(
-+	enum dce_version version,
-+	struct irq_service_init_data *init_data)
-+{
-+	switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		return dal_irq_service_dce110_create(init_data);
-+#endif
-+	default:
-+		return NULL;
-+	}
-+}
-+
-+void dal_irq_service_destroy(struct irq_service **irq_service)
-+{
-+	if (!irq_service || !*irq_service) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dc_service_free((*irq_service)->ctx, *irq_service);
-+
-+	*irq_service = NULL;
-+}
-+
-+const struct irq_source_info *find_irq_source_info(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source)
-+{
-+	if (source > DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
-+		return NULL;
-+
-+	return &irq_service->info[source];
-+}
-+
-+void dal_irq_service_set_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable)
-+{
-+	uint32_t addr = info->enable_reg;
-+	uint32_t value = dal_read_reg(irq_service->ctx, addr);
-+
-+	value = (value & ~info->enable_mask) |
-+		(info->enable_value[enable ? 0 : 1] & info->enable_mask);
-+	dal_write_reg(irq_service->ctx, addr, value);
-+}
-+
-+bool dal_irq_service_set(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source,
-+	bool enable)
-+{
-+	const struct irq_source_info *info =
-+		find_irq_source_info(irq_service, source);
-+
-+	if (!info) {
-+		dal_logger_write(
-+			irq_service->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_IRQ_SERVICE,
-+			"%s: cannot find irq info table entry for %d\n",
-+			__func__,
-+			source);
-+		return false;
-+	}
-+
-+	dal_irq_service_ack(irq_service, source);
-+
-+	if (info->funcs->set)
-+		return info->funcs->set(irq_service, info, enable);
-+
-+	dal_irq_service_set_generic(irq_service, info, enable);
-+
-+	return true;
-+}
-+
-+void dal_irq_service_ack_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->ack_reg;
-+	uint32_t value = dal_read_reg(irq_service->ctx, addr);
-+
-+	value = (value & ~info->ack_mask) |
-+		(info->ack_value & info->ack_mask);
-+	dal_write_reg(irq_service->ctx, addr, value);
-+}
-+
-+bool dal_irq_service_ack(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source)
-+{
-+	const struct irq_source_info *info =
-+		find_irq_source_info(irq_service, source);
-+
-+	if (!info) {
-+		dal_logger_write(
-+			irq_service->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_IRQ_SERVICE,
-+			"%s: cannot find irq info table entry for %d\n",
-+			__func__,
-+			source);
-+		return false;
-+	}
-+
-+	if (info->funcs->ack)
-+		return info->funcs->ack(irq_service, info);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	return true;
-+}
-+
-+enum dc_irq_source dal_irq_service_to_irq_source(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	return irq_service->funcs->to_dal_irq_source(
-+		irq_service,
-+		src_id,
-+		ext_id);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.h b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.h
-new file mode 100644
-index 0000000..a2a2d69
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.h
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_H__
-+#define __DAL_IRQ_SERVICE_H__
-+
-+#include "include/irq_service_interface.h"
-+
-+#include "irq_types.h"
-+
-+struct irq_service;
-+struct irq_source_info;
-+
-+struct irq_source_info_funcs {
-+	bool (*set)(
-+		struct irq_service *irq_service,
-+		const struct irq_source_info *info,
-+		bool enable);
-+	bool (*ack)(
-+		struct irq_service *irq_service,
-+		const struct irq_source_info *info);
-+};
-+
-+struct irq_source_info {
-+	uint32_t src_id;
-+	uint32_t ext_id;
-+	uint32_t enable_reg;
-+	uint32_t enable_mask;
-+	uint32_t enable_value[2];
-+	uint32_t ack_reg;
-+	uint32_t ack_mask;
-+	uint32_t ack_value;
-+	uint32_t status_reg;
-+	const struct irq_source_info_funcs *funcs;
-+};
-+
-+struct irq_service_funcs {
-+	enum dc_irq_source (*to_dal_irq_source)(
-+			struct irq_service *irq_service,
-+			uint32_t src_id,
-+			uint32_t ext_id);
-+};
-+
-+struct irq_service {
-+	struct dc_context *ctx;
-+	const struct irq_source_info *info;
-+	const struct irq_service_funcs *funcs;
-+};
-+
-+bool dal_irq_service_construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data);
-+
-+void dal_irq_service_ack_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info);
-+
-+void dal_irq_service_set_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq_types.h b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-new file mode 100644
-index 0000000..051a1f6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-@@ -0,0 +1,199 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_TYPES_H__
-+#define __DAL_IRQ_TYPES_H__
-+
-+struct dc_context;
-+
-+typedef void (*interrupt_handler)(void *);
-+
-+typedef void *irq_handler_idx;
-+#define DAL_INVALID_IRQ_HANDLER_IDX NULL
-+
-+
-+/* The order of the IRQ sources is important and MUST match the one's
-+of base driver */
-+enum dc_irq_source {
-+	/* Use as mask to specify invalid irq source */
-+	DC_IRQ_SOURCE_INVALID = 0,
-+
-+	DC_IRQ_SOURCE_HPD1,
-+	DC_IRQ_SOURCE_HPD2,
-+	DC_IRQ_SOURCE_HPD3,
-+	DC_IRQ_SOURCE_HPD4,
-+	DC_IRQ_SOURCE_HPD5,
-+	DC_IRQ_SOURCE_HPD6,
-+
-+	DC_IRQ_SOURCE_HPD1RX,
-+	DC_IRQ_SOURCE_HPD2RX,
-+	DC_IRQ_SOURCE_HPD3RX,
-+	DC_IRQ_SOURCE_HPD4RX,
-+	DC_IRQ_SOURCE_HPD5RX,
-+	DC_IRQ_SOURCE_HPD6RX,
-+
-+	DC_IRQ_SOURCE_I2C_DDC1,
-+	DC_IRQ_SOURCE_I2C_DDC2,
-+	DC_IRQ_SOURCE_I2C_DDC3,
-+	DC_IRQ_SOURCE_I2C_DDC4,
-+	DC_IRQ_SOURCE_I2C_DDC5,
-+	DC_IRQ_SOURCE_I2C_DDC6,
-+
-+	DC_IRQ_SOURCE_AZALIA0,
-+	DC_IRQ_SOURCE_AZALIA1,
-+	DC_IRQ_SOURCE_AZALIA2,
-+	DC_IRQ_SOURCE_AZALIA3,
-+	DC_IRQ_SOURCE_AZALIA4,
-+	DC_IRQ_SOURCE_AZALIA5,
-+
-+	DC_IRQ_SOURCE_DPSINK1,
-+	DC_IRQ_SOURCE_DPSINK2,
-+	DC_IRQ_SOURCE_DPSINK3,
-+	DC_IRQ_SOURCE_DPSINK4,
-+	DC_IRQ_SOURCE_DPSINK5,
-+	DC_IRQ_SOURCE_DPSINK6,
-+
-+	DC_IRQ_SOURCE_CRTC1VSYNC,
-+	DC_IRQ_SOURCE_CRTC2VSYNC,
-+	DC_IRQ_SOURCE_CRTC3VSYNC,
-+	DC_IRQ_SOURCE_CRTC4VSYNC,
-+	DC_IRQ_SOURCE_CRTC5VSYNC,
-+	DC_IRQ_SOURCE_CRTC6VSYNC,
-+	DC_IRQ_SOURCE_TIMER,
-+
-+	DC_IRQ_SOURCE_PFLIP_FIRST,
-+	DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST,
-+	DC_IRQ_SOURCE_PFLIP2,
-+	DC_IRQ_SOURCE_PFLIP3,
-+	DC_IRQ_SOURCE_PFLIP4,
-+	DC_IRQ_SOURCE_PFLIP5,
-+	DC_IRQ_SOURCE_PFLIP6,
-+	DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
-+	DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
-+
-+	DC_IRQ_SOURCE_GPIOPAD0,
-+	DC_IRQ_SOURCE_GPIOPAD1,
-+	DC_IRQ_SOURCE_GPIOPAD2,
-+	DC_IRQ_SOURCE_GPIOPAD3,
-+	DC_IRQ_SOURCE_GPIOPAD4,
-+	DC_IRQ_SOURCE_GPIOPAD5,
-+	DC_IRQ_SOURCE_GPIOPAD6,
-+	DC_IRQ_SOURCE_GPIOPAD7,
-+	DC_IRQ_SOURCE_GPIOPAD8,
-+	DC_IRQ_SOURCE_GPIOPAD9,
-+	DC_IRQ_SOURCE_GPIOPAD10,
-+	DC_IRQ_SOURCE_GPIOPAD11,
-+	DC_IRQ_SOURCE_GPIOPAD12,
-+	DC_IRQ_SOURCE_GPIOPAD13,
-+	DC_IRQ_SOURCE_GPIOPAD14,
-+	DC_IRQ_SOURCE_GPIOPAD15,
-+	DC_IRQ_SOURCE_GPIOPAD16,
-+	DC_IRQ_SOURCE_GPIOPAD17,
-+	DC_IRQ_SOURCE_GPIOPAD18,
-+	DC_IRQ_SOURCE_GPIOPAD19,
-+	DC_IRQ_SOURCE_GPIOPAD20,
-+	DC_IRQ_SOURCE_GPIOPAD21,
-+	DC_IRQ_SOURCE_GPIOPAD22,
-+	DC_IRQ_SOURCE_GPIOPAD23,
-+	DC_IRQ_SOURCE_GPIOPAD24,
-+	DC_IRQ_SOURCE_GPIOPAD25,
-+	DC_IRQ_SOURCE_GPIOPAD26,
-+	DC_IRQ_SOURCE_GPIOPAD27,
-+	DC_IRQ_SOURCE_GPIOPAD28,
-+	DC_IRQ_SOURCE_GPIOPAD29,
-+	DC_IRQ_SOURCE_GPIOPAD30,
-+
-+	DC_IRQ_SOURCE_DC1UNDERFLOW,
-+	DC_IRQ_SOURCE_DC2UNDERFLOW,
-+	DC_IRQ_SOURCE_DC3UNDERFLOW,
-+	DC_IRQ_SOURCE_DC4UNDERFLOW,
-+	DC_IRQ_SOURCE_DC5UNDERFLOW,
-+	DC_IRQ_SOURCE_DC6UNDERFLOW,
-+
-+	DC_IRQ_SOURCE_DMCU_SCP,
-+	DC_IRQ_SOURCE_VBIOS_SW,
-+
-+	DC_IRQ_SOURCE_VUPDATE1,
-+	DC_IRQ_SOURCE_VUPDATE2,
-+	DC_IRQ_SOURCE_VUPDATE3,
-+	DC_IRQ_SOURCE_VUPDATE4,
-+	DC_IRQ_SOURCE_VUPDATE5,
-+	DC_IRQ_SOURCE_VUPDATE6,
-+
-+	DAL_IRQ_SOURCES_NUMBER
-+};
-+
-+enum irq_type
-+{
-+	IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
-+	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
-+};
-+
-+#define DAL_VALID_IRQ_SRC_NUM(src) \
-+	((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID)
-+
-+/* Number of Page Flip IRQ Sources. */
-+#define DAL_PFLIP_IRQ_SRC_NUM \
-+	(DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1)
-+
-+/* the number of contexts may be expanded in the future based on needs */
-+enum dc_interrupt_context {
-+	INTERRUPT_LOW_IRQ_CONTEXT = 0,
-+	INTERRUPT_HIGH_IRQ_CONTEXT,
-+	INTERRUPT_CONTEXT_NUMBER
-+};
-+
-+enum dc_interrupt_porlarity {
-+	INTERRUPT_POLARITY_DEFAULT = 0,
-+	INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
-+	INTERRUPT_POLARITY_HIGH,
-+	INTERRUPT_POLARITY_BOTH
-+};
-+
-+#define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \
-+	(int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
-+	(int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
-+	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
-+
-+struct dc_timer_interrupt_params {
-+	uint64_t micro_sec_interval;
-+	enum dc_interrupt_context int_context;
-+};
-+
-+struct dc_interrupt_params {
-+	/* The polarity *change* which will trigger an interrupt.
-+	 * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
-+	 * 'current_polarity' must be initialised. */
-+	enum dc_interrupt_porlarity requested_polarity;
-+	/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
-+	 * 'current_polarity' should contain the current state, which means
-+	 * the interrupt will be triggered when state changes from what is,
-+	 * in 'current_polarity'. */
-+	enum dc_interrupt_porlarity current_polarity;
-+	enum dc_irq_source irq_source;
-+	enum dc_interrupt_context int_context;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-new file mode 100644
-index 0000000..aa503a8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-@@ -0,0 +1,628 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ADAPTER_SERVICE_INTERFACE_H__
-+#define __DAL_ADAPTER_SERVICE_INTERFACE_H__
-+
-+#include "grph_object_ctrl_defs.h"
-+#include "gpio_interface.h"
-+#include "ddc_interface.h"
-+#include "irq_interface.h"
-+#include "bios_parser_interface.h"
-+#include "adapter_service_types.h"
-+#include "dal_types.h"
-+#include "asic_capability_types.h"
-+
-+/* forward declaration */
-+struct bios_parser;
-+struct i2caux;
-+struct adapter_service;
-+
-+
-+/*
-+ * enum adapter_feature_id
-+ *
-+ * Definition of all adapter features
-+ *
-+ * The enumeration defines the IDs of all the adapter features. The enum
-+ * organizes all the features into several feature sets. The range of feature
-+ * set N is from ((N-1)*32+1) to (N*32). Because there may be three value-type
-+ * feature, boolean-type, unsigned char-type and unsinged int-type, the number
-+ * of features should be 32, 4 and 1 in the feature set accordingly.
-+ *
-+ * In a boolean-type feature set N, the enumeration value of the feature should
-+ * be ((N-1)*32+1), ((N-1)*32+2), ..., (N*32).
-+ *
-+ * In an unsigned char-type feature set N, the enumeration value of the
-+ * feature should be ((N-1)*32+1), ((N-1)*32+8), ((N-1)*32+16) and (N*32).
-+ *
-+ * In an unsigned int-type feature set N, the enumeration value of the feature
-+ * should be ((N-1)*32+1)
-+ */
-+enum adapter_feature_id {
-+	FEATURE_UNKNOWN = 0,
-+
-+	/* Boolean set, up to 32 entries */
-+	FEATURE_ENABLE_HW_EDID_POLLING = 1,
-+	FEATURE_SET_01_START = FEATURE_ENABLE_HW_EDID_POLLING,
-+	FEATURE_DP_SINK_DETECT_POLL_DATA_PIN,
-+	FEATURE_UNDERFLOW_INTERRUPT,
-+	FEATURE_ALLOW_WATERMARK_ADJUSTMENT,
-+	FEATURE_LIGHT_SLEEP,
-+	FEATURE_DCP_DITHER_FRAME_RANDOM_ENABLE,
-+	FEATURE_DCP_DITHER_RGB_RANDOM_ENABLE,
-+	FEATURE_DCP_DITHER_HIGH_PASS_RANDOM_ENABLE,
-+	FEATURE_DETECT_REQUIRE_HPD_HIGH,
-+	FEATURE_LINE_BUFFER_ENHANCED_PIXEL_DEPTH, /* 10th */
-+	FEATURE_MAXIMIZE_URGENCY_WATERMARKS,
-+	FEATURE_MAXIMIZE_STUTTER_MARKS,
-+	FEATURE_MAXIMIZE_NBP_MARKS,
-+	FEATURE_RESTORE_USAGE_I2C_SW_ENGINE,
-+	FEATURE_USE_MAX_DISPLAY_CLK,
-+	FEATURE_ALLOW_EDP_RESOURCE_SHARING,
-+	FEATURE_SUPPORT_DP_YUV,
-+	FEATURE_SUPPORT_DP_Y_ONLY,
-+	FEATURE_DISABLE_DP_GTC_SYNC,
-+	FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, /* 20th */
-+	FEATURE_ENABLE_DFS_BYPASS,
-+	FEATURE_LB_HIGH_RESOLUTION,
-+	FEATURE_DP_DISPLAY_FORCE_SS_ENABLE,
-+	FEATURE_REPORT_CE_MODE_ONLY,
-+	FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT,
-+	FEATURE_DDC_READ_FORCE_REPEATED_START,
-+	FEATURE_FORCE_TIMING_RESYNC,
-+	FEATURE_TMDS_DISABLE_DITHERING,
-+	FEATURE_HDMI_DISABLE_DITHERING,
-+	FEATURE_DP_DISABLE_DITHERING, /* 30th */
-+	FEATURE_EMBEDDED_DISABLE_DITHERING,
-+	FEATURE_DISABLE_AZ_CLOCK_GATING, /* 32th. This set is full */
-+	FEATURE_SET_01_END = FEATURE_SET_01_START + 31,
-+
-+	/* Boolean set, up to 32 entries */
-+	FEATURE_WIRELESS_ENABLE = FEATURE_SET_01_END + 1,
-+	FEATURE_SET_02_START = FEATURE_WIRELESS_ENABLE,
-+	FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT,
-+	FEATURE_WIRELESS_LIMIT_720P,
-+	FEATURE_WIRELESS_ENABLE_COMPRESSED_AUDIO,
-+	FEATURE_WIRELESS_INCLUDE_UNVERIFIED_TIMINGS,
-+	FEATURE_MODIFY_TIMINGS_FOR_WIRELESS,
-+	FEATURE_ALLOW_SELF_REFRESH,
-+	FEATURE_ALLOW_DYNAMIC_PIXEL_ENCODING_CHANGE,
-+	FEATURE_ALLOW_HSYNC_VSYNC_ADJUSTMENT,
-+	FEATURE_FORCE_PSR, /* 10th */
-+	FEATURE_PREFER_3D_TIMING,
-+	FEATURE_VARI_BRIGHT_ENABLE,
-+	FEATURE_PSR_ENABLE,
-+	FEATURE_EDID_STRESS_READ,
-+	FEATURE_DP_FRAME_PACK_STEREO3D,
-+	FEATURE_ALLOW_HDMI_WITHOUT_AUDIO,
-+	FEATURE_RESTORE_USAGE_I2C_SW_ENGING,
-+	FEATURE_ABM_2_0,
-+	FEATURE_SUPPORT_MIRABILIS,
-+	FEATURE_LOAD_DMCU_FIRMWARE, /* 20th */
-+	FEATURE_ENABLE_GPU_SCALING,
-+	FEATURE_DONGLE_SINK_COUNT_CHECK,
-+	FEATURE_INSTANT_UP_SCALE_DOWN_SCALE,
-+	FEATURE_TILED_DISPLAY,
-+	FEATURE_CHANGE_I2C_SPEED_CONTROL,
-+	FEATURE_REPORT_SINGLE_SELECTED_TIMING,
-+	FEATURE_ALLOW_HDMI_HIGH_CLK_DP_DONGLE,
-+	FEATURE_SUPPORT_EXTERNAL_PANEL_DRR,
-+	FEATURE_SUPPORT_SMOOTH_BRIGHTNESS,
-+	FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, /* 30th */
-+	FEATURE_POWER_GATING_LB_PORTION, /* 31nd. One more left. */
-+	FEATURE_SET_02_END = FEATURE_SET_02_START + 31,
-+
-+	/* UInt set, 1 entry: DCP Bit Depth Reduction Mode */
-+	FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE = FEATURE_SET_02_END + 1,
-+	FEATURE_SET_03_START = FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE,
-+	FEATURE_SET_03_END = FEATURE_SET_03_START + 31,
-+
-+	/* UInt set, 1 entry: DCP Dither Mode */
-+	FEATURE_DCP_DITHER_MODE = FEATURE_SET_03_END + 1,
-+	FEATURE_SET_04_START = FEATURE_DCP_DITHER_MODE,
-+	FEATURE_SET_04_END = FEATURE_SET_04_START + 31,
-+
-+	/* UInt set, 1 entry: DCP Programming WA(workaround) */
-+	FEATURE_DCP_PROGRAMMING_WA = FEATURE_SET_04_END + 1,
-+	FEATURE_SET_06_START = FEATURE_DCP_PROGRAMMING_WA,
-+	FEATURE_SET_06_END = FEATURE_SET_06_START + 31,
-+
-+	/* UInt set, 1 entry: Maximum co-functional non-DP displays */
-+	FEATURE_MAX_COFUNC_NON_DP_DISPLAYS = FEATURE_SET_06_END + 1,
-+	FEATURE_SET_07_START = FEATURE_MAX_COFUNC_NON_DP_DISPLAYS,
-+	FEATURE_SET_07_END = FEATURE_SET_07_START + 31,
-+
-+	/* UInt set, 1 entry: Number of supported HDMI connection */
-+	FEATURE_SUPPORTED_HDMI_CONNECTION_NUM = FEATURE_SET_07_END + 1,
-+	FEATURE_SET_08_START = FEATURE_SUPPORTED_HDMI_CONNECTION_NUM,
-+	FEATURE_SET_08_END = FEATURE_SET_08_START + 31,
-+
-+	/* UInt set, 1 entry: Maximum number of controllers */
-+	FEATURE_MAX_CONTROLLER_NUM = FEATURE_SET_08_END + 1,
-+	FEATURE_SET_09_START = FEATURE_MAX_CONTROLLER_NUM,
-+	FEATURE_SET_09_END = FEATURE_SET_09_START + 31,
-+
-+	/* UInt set, 1 entry: Type of DRR support */
-+	FEATURE_DRR_SUPPORT = FEATURE_SET_09_END + 1,
-+	FEATURE_SET_10_START = FEATURE_DRR_SUPPORT,
-+	FEATURE_SET_10_END = FEATURE_SET_10_START + 31,
-+
-+	/* UInt set, 1 entry: Stutter mode support */
-+	FEATURE_STUTTER_MODE = FEATURE_SET_10_END + 1,
-+	FEATURE_SET_11_START = FEATURE_STUTTER_MODE,
-+	FEATURE_SET_11_END = FEATURE_SET_11_START + 31,
-+
-+	/* UInt set, 1 entry: Measure PSR setup time */
-+	FEATURE_PSR_SETUP_TIME_TEST = FEATURE_SET_11_END + 1,
-+	FEATURE_SET_12_START = FEATURE_PSR_SETUP_TIME_TEST,
-+	FEATURE_SET_12_END = FEATURE_SET_12_START + 31,
-+
-+	/* Boolean set, up to 32 entries */
-+	FEATURE_POWER_GATING_PIPE_IN_TILE = FEATURE_SET_12_END + 1,
-+	FEATURE_SET_13_START = FEATURE_POWER_GATING_PIPE_IN_TILE,
-+	FEATURE_USE_PPLIB,
-+	FEATURE_DISABLE_LPT_SUPPORT,
-+	FEATURE_DUMMY_FBC_BACKEND,
-+	FEATURE_DISABLE_FBC_COMP_CLK_GATE,
-+	FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL,
-+	FEATURE_PIXEL_PERFECT_OUTPUT,
-+	FEATURE_8BPP_SUPPORTED,
-+	FEATURE_SET_13_END = FEATURE_SET_13_START + 31,
-+
-+	/* UInt set, 1 entry: Display preferred view
-+	 * 0: no preferred view
-+	 * 1: native and preferred timing of embedded display will have high
-+	 *    priority, so other displays will support it always
-+	 */
-+	FEATURE_DISPLAY_PREFERRED_VIEW = FEATURE_SET_13_END + 1,
-+	FEATURE_SET_15_START = FEATURE_DISPLAY_PREFERRED_VIEW,
-+	FEATURE_SET_15_END = FEATURE_SET_15_START + 31,
-+
-+	/* UInt set, 1 entry: DAL optimization */
-+	FEATURE_OPTIMIZATION = FEATURE_SET_15_END + 1,
-+	FEATURE_SET_16_START = FEATURE_OPTIMIZATION,
-+	FEATURE_SET_16_END = FEATURE_SET_16_START + 31,
-+
-+	/* UInt set, 1 entry: Performance measurement */
-+	FEATURE_PERF_MEASURE = FEATURE_SET_16_END + 1,
-+	FEATURE_SET_17_START = FEATURE_PERF_MEASURE,
-+	FEATURE_SET_17_END = FEATURE_SET_17_START + 31,
-+
-+	/* UInt set, 1 entry: Minimum backlight value [0-255] */
-+	FEATURE_MIN_BACKLIGHT_LEVEL = FEATURE_SET_17_END + 1,
-+	FEATURE_SET_18_START = FEATURE_MIN_BACKLIGHT_LEVEL,
-+	FEATURE_SET_18_END = FEATURE_SET_18_START + 31,
-+
-+	/* UInt set, 1 entry: Maximum backlight value [0-255] */
-+	FEATURE_MAX_BACKLIGHT_LEVEL = FEATURE_SET_18_END + 1,
-+	FEATURE_SET_19_START = FEATURE_MAX_BACKLIGHT_LEVEL,
-+	FEATURE_SET_19_END = FEATURE_SET_19_START + 31,
-+
-+	/* UInt set, 1 entry: AMB setting
-+	 *
-+	 * Each byte will control the ABM configuration to use for a specific
-+	 * ABM level.
-+	 *
-+	 * HW team provided 12 different ABM min/max reduction pairs to choose
-+	 * between for each ABM level.
-+	 *
-+	 * ABM level Byte Setting
-+	 *       1    0   Default = 0 (setting 3), can be override to 1-12
-+	 *       2    1   Default = 0 (setting 7), can be override to 1-12
-+	 *       3    2   Default = 0 (setting 8), can be override to 1-12
-+	 *       4    3   Default = 0 (setting 10), can be override to 1-12
-+	 *
-+	 * For example,
-+	 * FEATURE_PREFERRED_ABM_CONFIG_SET = 0x0C060500, this represents:
-+	 * ABM level 1 use default setting (setting 3)
-+	 * ABM level 2 uses setting 5
-+	 * ABM level 3 uses setting 6
-+	 * ABM level 4 uses setting 12
-+	 * Internal use only!
-+	 */
-+	FEATURE_PREFERRED_ABM_CONFIG_SET = FEATURE_SET_19_END + 1,
-+	FEATURE_SET_20_START = FEATURE_PREFERRED_ABM_CONFIG_SET,
-+	FEATURE_SET_20_END = FEATURE_SET_20_START + 31,
-+
-+	/* UInt set, 1 entry: Change SW I2C speed */
-+	FEATURE_CHANGE_SW_I2C_SPEED = FEATURE_SET_20_END + 1,
-+	FEATURE_SET_21_START = FEATURE_CHANGE_SW_I2C_SPEED,
-+	FEATURE_SET_21_END = FEATURE_SET_21_START + 31,
-+
-+	/* UInt set, 1 entry: Change HW I2C speed */
-+	FEATURE_CHANGE_HW_I2C_SPEED = FEATURE_SET_21_END + 1,
-+	FEATURE_SET_22_START = FEATURE_CHANGE_HW_I2C_SPEED,
-+	FEATURE_SET_22_END = FEATURE_SET_22_START + 31,
-+
-+	/* UInt set, 1 entry:
-+	 * When PSR issue occurs, it is sometimes hard to debug since the
-+	 * failure occurs immediately at boot. Use this setting to skip or
-+	 * postpone PSR functionality and re-enable through DSAT. */
-+	FEATURE_DEFAULT_PSR_LEVEL = FEATURE_SET_22_END + 1,
-+	FEATURE_SET_23_START = FEATURE_DEFAULT_PSR_LEVEL,
-+	FEATURE_SET_23_END = FEATURE_SET_23_START + 31,
-+
-+	/* UInt set, 1 entry: Allowed pixel clock range for LVDS */
-+	FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE = FEATURE_SET_23_END + 1,
-+	FEATURE_SET_24_START = FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE,
-+	FEATURE_SET_24_END = FEATURE_SET_24_START + 31,
-+
-+	/* UInt set, 1 entry: Max number of clock sources */
-+	FEATURE_MAX_CLOCK_SOURCE_NUM = FEATURE_SET_24_END + 1,
-+	FEATURE_SET_25_START = FEATURE_MAX_CLOCK_SOURCE_NUM,
-+	FEATURE_SET_25_END = FEATURE_SET_25_START + 31,
-+
-+	/* UInt set, 1 entry: Select the ABM configuration to use.
-+	 *
-+	 * This feature set is used to allow packaging option to be defined
-+	 * to allow OEM to select between the default ABM configuration or
-+	 * alternative predefined configurations that may be more aggressive.
-+	 *
-+	 * Note that this regkey is meant for external use to select the
-+	 * configuration OEM wants. Whereas the other PREFERRED_ABM_CONFIG_SET
-+	 * key is only used for internal use and allows full reconfiguration.
-+	 */
-+	FEATURE_ABM_CONFIG = FEATURE_SET_25_END + 1,
-+	FEATURE_SET_26_START = FEATURE_ABM_CONFIG,
-+	FEATURE_SET_26_END = FEATURE_SET_26_START + 31,
-+
-+	/* UInt set, 1 entry: Select the default speed in which smooth
-+	 * brightness feature should converge towards target backlight level.
-+	 *
-+	 * For example, a setting of 500 means it takes 500ms to transition
-+	 * from current backlight level to the new requested backlight level.
-+	 */
-+	FEATURE_SMOOTH_BRTN_ADJ_TIME_IN_MS = FEATURE_SET_26_END + 1,
-+	FEATURE_SET_27_START = FEATURE_SMOOTH_BRTN_ADJ_TIME_IN_MS,
-+	FEATURE_SET_27_END = FEATURE_SET_27_START + 31,
-+
-+	/* Set 28: UInt set, 1 entry: Allow runtime parameter to force specific
-+	 * Static Screen Event triggers for test purposes. */
-+	FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS = FEATURE_SET_27_END + 1,
-+	FEATURE_SET_28_START = FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS,
-+	FEATURE_SET_28_END = FEATURE_SET_28_START + 31,
-+
-+	FEATURE_MAXIMUM
-+};
-+
-+/* Adapter Service type of DRR support*/
-+enum as_drr_support {
-+	AS_DRR_SUPPORT_DISABLED = 0x0,
-+	AS_DRR_SUPPORT_ENABLED = 0x1,
-+	AS_DRR_SUPPORT_MIN_FORCED_FPS = 0xA
-+};
-+
-+/* Adapter service initialize data structure*/
-+struct as_init_data {
-+	struct hw_asic_id hw_init_data;
-+	struct bp_init_data bp_init_data;
-+	struct dc_context *ctx;
-+	struct bdf_info bdf_info;
-+	const struct dal_override_parameters *display_param;
-+};
-+
-+/* Create adapter service */
-+struct adapter_service *dal_adapter_service_create(
-+	struct as_init_data *init_data);
-+
-+/* Destroy adapter service and objects it contains */
-+void dal_adapter_service_destroy(
-+	struct adapter_service **as);
-+
-+/* Get the DCE version of current ASIC */
-+enum dce_version dal_adapter_service_get_dce_version(
-+	const struct adapter_service *as);
-+
-+/* Get firmware information from BIOS */
-+bool dal_adapter_service_get_firmware_info(
-+	struct adapter_service *as,
-+	struct firmware_info *info);
-+
-+
-+/* functions to get a total number of objects of specific type */
-+uint8_t dal_adapter_service_get_connectors_num(
-+	struct adapter_service *as);
-+
-+/* Get number of controllers */
-+uint8_t dal_adapter_service_get_controllers_num(
-+	struct adapter_service *as);
-+
-+/* Get number of clock sources */
-+uint8_t dal_adapter_service_get_clock_sources_num(
-+	struct adapter_service *as);
-+
-+/* Get number of controllers */
-+uint8_t dal_adapter_service_get_func_controllers_num(
-+	struct adapter_service *as);
-+
-+/* Get number of stream engines */
-+uint8_t dal_adapter_service_get_stream_engines_num(
-+	struct adapter_service *as);
-+
-+/* functions to get object id based on object index */
-+struct graphics_object_id dal_adapter_service_get_connector_obj_id(
-+	struct adapter_service *as,
-+	uint8_t connector_index);
-+
-+/* Get number of spread spectrum entries from BIOS */
-+uint32_t dal_adapter_service_get_ss_info_num(
-+	struct adapter_service *as,
-+	enum as_signal_type signal);
-+
-+/* Get spread spectrum info from BIOS */
-+bool dal_adapter_service_get_ss_info(
-+	struct adapter_service *as,
-+	enum as_signal_type signal,
-+	uint32_t idx,
-+	struct spread_spectrum_info *info);
-+
-+/* Check if DFS bypass is enabled */
-+bool dal_adapter_service_is_dfs_bypass_enabled(struct adapter_service *as);
-+
-+/* Get memory controller latency */
-+uint32_t dal_adapter_service_get_mc_latency(
-+	struct adapter_service *as);
-+
-+/* Get the video RAM bit width set on the ASIC */
-+uint32_t dal_adapter_service_get_asic_vram_bit_width(
-+	struct adapter_service *as);
-+
-+/* Get the bug flags set on this ASIC */
-+struct asic_bugs dal_adapter_service_get_asic_bugs(
-+	struct adapter_service *as);
-+
-+/* Get efficiency of DRAM */
-+uint32_t dal_adapter_service_get_dram_bandwidth_efficiency(
-+	struct adapter_service *as);
-+
-+/* Get multiplier for the memory type */
-+uint32_t dal_adapter_service_get_memory_type_multiplier(
-+	struct adapter_service *as);
-+
-+/* Get parameters for bandwidth tuning */
-+bool dal_adapter_service_get_bandwidth_tuning_params(
-+	struct adapter_service *as,
-+	union bandwidth_tuning_params *params);
-+
-+/* Get integrated information on BIOS */
-+bool dal_adapter_service_get_integrated_info(
-+	struct adapter_service *as,
-+	struct integrated_info *info);
-+
-+/* Return if a given feature is supported by the ASIC */
-+bool dal_adapter_service_is_feature_supported(
-+	enum adapter_feature_id feature_id);
-+
-+/* Get the cached value of a given feature */
-+bool dal_adapter_service_get_feature_value(
-+	const enum adapter_feature_id feature_id,
-+	void *data,
-+	uint32_t size);
-+
-+/* Get a copy of ASIC feature flags */
-+struct asic_feature_flags dal_adapter_service_get_feature_flags(
-+	struct adapter_service *as);
-+
-+/* Obtain DDC */
-+struct ddc *dal_adapter_service_obtain_ddc(
-+	struct adapter_service *as,
-+	struct graphics_object_id id);
-+
-+/* Release DDC */
-+void dal_adapter_service_release_ddc(
-+	struct adapter_service *as,
-+	struct ddc *ddc);
-+
-+/* Obtain HPD interrupt request */
-+struct irq *dal_adapter_service_obtain_hpd_irq(
-+	struct adapter_service *as,
-+	struct graphics_object_id id);
-+
-+/* Release interrupt request */
-+void dal_adapter_service_release_irq(
-+	struct adapter_service *as,
-+	struct irq *irq);
-+
-+/* Obtain GPIO */
-+struct gpio *dal_adapter_service_obtain_gpio(
-+	struct adapter_service *as,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+/* Obtain GPIO for stereo3D*/
-+struct gpio *dal_adapter_service_obtain_stereo_gpio(struct adapter_service *as);
-+
-+/* Release GPIO */
-+void dal_adapter_service_release_gpio(
-+		struct adapter_service *as,
-+		struct gpio *gpio);
-+
-+/* Get SW I2C speed */
-+uint32_t dal_adapter_service_get_sw_i2c_speed(struct adapter_service *as);
-+
-+/* Get HW I2C speed */
-+uint32_t dal_adapter_service_get_hw_i2c_speed(struct adapter_service *as);
-+
-+/* Get line buffer size */
-+uint32_t dal_adapter_service_get_line_buffer_size(struct adapter_service *as);
-+
-+/* Get information on audio support */
-+union audio_support dal_adapter_service_get_audio_support(
-+		struct adapter_service *as);
-+
-+/* Get I2C information from BIOS */
-+bool dal_adapter_service_get_i2c_info(
-+	struct adapter_service *as,
-+	struct graphics_object_id id,
-+	struct graphics_object_i2c_info *i2c_info);
-+
-+/* Get bios parser handler */
-+struct bios_parser *dal_adapter_service_get_bios_parser(
-+	struct adapter_service *as);
-+
-+/* Get i2c aux handler */
-+struct i2caux *dal_adapter_service_get_i2caux(
-+	struct adapter_service *as);
-+
-+struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
-+	struct adapter_service *as);
-+
-+bool dal_adapter_service_initialize_hw_data(
-+	struct adapter_service *as);
-+
-+struct graphics_object_id dal_adapter_service_enum_fake_path_resource(
-+	struct adapter_service *as,
-+	uint32_t index);
-+
-+struct graphics_object_id dal_adapter_service_enum_stereo_sync_object(
-+	struct adapter_service *as,
-+	uint32_t index);
-+
-+struct graphics_object_id dal_adapter_service_enum_sync_output_object(
-+	struct adapter_service *as,
-+	uint32_t index);
-+
-+struct graphics_object_id dal_adapter_service_enum_audio_object(
-+	struct adapter_service *as,
-+	uint32_t index);
-+
-+void dal_adapter_service_update_audio_connectivity(
-+	struct adapter_service *as,
-+	uint32_t number_of_audio_capable_display_path);
-+
-+bool dal_adapter_service_has_embedded_display_connector(
-+	struct adapter_service *as);
-+
-+bool dal_adapter_service_get_embedded_panel_info(
-+	struct adapter_service *as,
-+	struct embedded_panel_info *info);
-+
-+bool dal_adapter_service_enum_embedded_panel_patch_mode(
-+	struct adapter_service *as,
-+	uint32_t index,
-+	struct embedded_panel_patch_mode *mode);
-+
-+bool dal_adapter_service_get_faked_edid_len(
-+	struct adapter_service *as,
-+	uint32_t *len);
-+
-+bool dal_adapter_service_get_faked_edid_buf(
-+	struct adapter_service *as,
-+	uint8_t *buf,
-+	uint32_t len);
-+
-+uint32_t dal_adapter_service_get_max_cofunc_non_dp_displays(void);
-+
-+uint32_t dal_adapter_service_get_single_selected_timing_signals(void);
-+
-+bool dal_adapter_service_get_device_tag(
-+	struct adapter_service *as,
-+	struct graphics_object_id connector_object_id,
-+	uint32_t device_tag_index,
-+	struct connector_device_tag_info *info);
-+
-+bool dal_adapter_service_is_device_id_supported(
-+	struct adapter_service *as,
-+	struct device_id id);
-+
-+bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as);
-+
-+bool dal_adapter_service_underscan_for_hdmi_only(struct adapter_service *as);
-+
-+uint32_t dal_adapter_service_get_src_num(
-+	struct adapter_service *as,
-+	struct graphics_object_id id);
-+
-+struct graphics_object_id dal_adapter_service_get_src_obj(
-+	struct adapter_service *as,
-+	struct graphics_object_id id,
-+	uint32_t index);
-+
-+/* Is this Fusion ASIC */
-+bool dal_adapter_service_is_fusion(struct adapter_service *as);
-+
-+/* Is this ASIC support dynamic DFSbypass switch */
-+bool dal_adapter_service_is_dfsbyass_dynamic(struct adapter_service *as);
-+
-+/* Reports whether driver settings allow requested optimization */
-+bool dal_adapter_service_should_optimize(
-+		struct adapter_service *as, enum optimization_feature feature);
-+
-+/* Determine if driver is in accelerated mode */
-+bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as);
-+
-+struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
-+	struct adapter_service *as,
-+	struct graphics_object_i2c_info *info);
-+
-+struct bdf_info dal_adapter_service_get_adapter_info(
-+	struct adapter_service *as);
-+
-+
-+/* Determine if this ASIC needs to wait on PLL lock bit */
-+bool dal_adapter_service_should_psr_skip_wait_for_pll_lock(
-+	struct adapter_service *as);
-+
-+#define SIZEOF_BACKLIGHT_LUT 101
-+#define ABSOLUTE_BACKLIGHT_MAX 255
-+#define DEFAULT_MIN_BACKLIGHT 12
-+#define DEFAULT_MAX_BACKLIGHT 255
-+#define BACKLIGHT_CURVE_COEFFB 100
-+#define BACKLIGHT_CURVE_COEFFA_FACTOR 10000
-+#define BACKLIGHT_CURVE_COEFFB_FACTOR 100
-+
-+struct panel_backlight_levels {
-+	uint32_t ac_level_percentage;
-+	uint32_t dc_level_percentage;
-+};
-+
-+bool dal_adapter_service_is_lid_open(struct adapter_service *as);
-+
-+bool dal_adapter_service_get_panel_backlight_default_levels(
-+	struct adapter_service *as,
-+	struct panel_backlight_levels *levels);
-+
-+bool dal_adapter_service_get_panel_backlight_boundaries(
-+	struct adapter_service *as,
-+	struct panel_backlight_boundaries *boundaries);
-+
-+uint32_t dal_adapter_service_get_view_port_pixel_granularity(
-+	struct adapter_service *as);
-+
-+uint32_t dal_adapter_service_get_num_of_path_per_dp_mst_connector(
-+		struct adapter_service *as);
-+
-+uint32_t dal_adapter_service_get_num_of_underlays(
-+		struct adapter_service *as);
-+
-+bool dal_adapter_service_get_encoder_cap_info(
-+		struct adapter_service *as,
-+		struct graphics_object_id id,
-+		struct graphics_object_encoder_cap_info *info);
-+
-+bool dal_adapter_service_is_mc_tuning_req(struct adapter_service *as);
-+
-+#endif /* __DAL_ADAPTER_SERVICE_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_types.h b/drivers/gpu/drm/amd/dal/include/adapter_service_types.h
-new file mode 100644
-index 0000000..fb47ef3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_types.h
-@@ -0,0 +1,70 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ADAPTER_SERVICE_TYPES_H__
-+#define __DAL_ADAPTER_SERVICE_TYPES_H__
-+
-+enum as_signal_type {
-+	AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
-+	AS_SIGNAL_TYPE_DVI,
-+	AS_SIGNAL_TYPE_HDMI,
-+	AS_SIGNAL_TYPE_LVDS,
-+	AS_SIGNAL_TYPE_DISPLAY_PORT,
-+	AS_SIGNAL_TYPE_GPU_PLL,
-+	AS_SIGNAL_TYPE_UNKNOWN
-+};
-+
-+/*
-+ * Struct used for algorithm of Bandwidth tuning parameters
-+ * the sequence of the fields is binded with runtime parameter.
-+ */
-+union bandwidth_tuning_params {
-+	struct bandwidth_tuning_params_struct {
-+		uint32_t read_delay_stutter_off_usec;
-+		uint32_t ignore_hblank_time;/*bool*/
-+		uint32_t extra_reordering_latency_usec;
-+		uint32_t extra_mc_latency_usec;
-+		uint32_t data_return_bandwidth_eff;/*in %*/
-+		uint32_t dmif_request_bandwidth_eff;/*in %*/
-+		uint32_t sclock_latency_multiplier;/*in unit of 0.01*/
-+		uint32_t mclock_latency_multiplier;/*in unit of 0.01*/
-+		uint32_t fix_latency_multiplier;/*in unit of 0.01*/
-+		 /*in unit represent in watermark*/
-+		uint32_t use_urgency_watermark_offset;
-+	} tuning_info;
-+	uint32_t arr_info[sizeof(struct bandwidth_tuning_params_struct)
-+		/ sizeof(uint32_t)];
-+};
-+
-+union audio_support {
-+	struct {
-+		uint32_t DP_AUDIO:1;
-+		uint32_t HDMI_AUDIO_ON_DONGLE:1;
-+		uint32_t HDMI_AUDIO_NATIVE:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/adjustment_interface.h b/drivers/gpu/drm/amd/dal/include/adjustment_interface.h
-new file mode 100644
-index 0000000..64a9f9f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/adjustment_interface.h
-@@ -0,0 +1,230 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ADJUSTMENT_INTERFACE_H__
-+#define __DAL_ADJUSTMENT_INTERFACE_H__
-+
-+#include "include/display_service_types.h"
-+#include "include/adjustment_types.h"
-+#include "include/overlay_types.h"
-+#include "include/display_path_interface.h"
-+
-+struct ds_underscan_desc;
-+struct adj_container;
-+struct info_frame;
-+struct ds_dispatch;
-+struct hw_adjustment_set;
-+struct path_mode;
-+struct hw_path_mode;
-+
-+enum build_path_set_reason;
-+
-+bool dal_ds_dispatch_is_adjustment_supported(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id);
-+
-+enum ds_return dal_ds_dispatch_get_type(
-+	struct ds_dispatch *adj,
-+	enum adjustment_id adjust_id,
-+	enum adjustment_data_type *type);
-+
-+enum ds_return dal_ds_dispatch_get_property(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id,
-+	union adjustment_property *property);
-+
-+enum ds_return dal_ds_dispatch_set_adjustment(
-+	struct ds_dispatch *ds,
-+	const uint32_t display_index,
-+	enum adjustment_id adjust_id,
-+	int32_t value);
-+
-+enum ds_return dal_ds_dispatch_get_adjustment_current_value(
-+	struct ds_dispatch *ds,
-+	struct adj_container *container,
-+	struct adjustment_info *info,
-+	enum adjustment_id id,
-+	bool fall_back_to_default);
-+
-+enum ds_return dal_ds_dispatch_get_adjustment_value(
-+	struct ds_dispatch *ds,
-+	struct display_path *disp_path,
-+	enum adjustment_id adj_id,
-+	bool fall_back_to_default,
-+	int32_t *value);
-+
-+const struct raw_gamma_ramp *dal_ds_dispatch_get_current_gamma(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id);
-+
-+const struct raw_gamma_ramp *dal_ds_dispatch_get_default_gamma(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id);
-+
-+enum ds_return dal_ds_dispatch_set_current_gamma(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id,
-+	const struct raw_gamma_ramp *gamma);
-+
-+enum ds_return dal_ds_dispatch_set_gamma(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id,
-+	const struct raw_gamma_ramp *gamma);
-+
-+bool dal_ds_dispatch_get_underscan_info(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	struct ds_underscan_info *info);
-+
-+bool dal_ds_dispatch_get_underscan_mode(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	struct ds_underscan_desc *desc);
-+
-+bool dal_ds_dispatch_set_underscan_mode(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	struct ds_underscan_desc *desc);
-+
-+bool dal_ds_dispatch_setup_overlay(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	struct overlay_data *data);
-+
-+struct adj_container *dal_ds_dispatch_get_adj_container_for_path(
-+	const struct ds_dispatch *ds,
-+	uint32_t display_index);
-+
-+void dal_ds_dispatch_set_applicable_adj(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	const struct adj_container *applicable);
-+
-+enum ds_return dal_ds_dispatch_set_color_gamut(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	const struct ds_set_gamut_data *data);
-+
-+enum ds_return dal_ds_dispatch_get_color_gamut(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	const struct ds_gamut_reference_data *ref,
-+	struct ds_get_gamut_data *data);
-+
-+enum ds_return dal_ds_dispatch_get_color_gamut_info(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	const struct ds_gamut_reference_data *ref,
-+	struct ds_gamut_info *data);
-+
-+enum ds_return dal_ds_dispatch_get_regamma_lut(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	struct ds_regamma_lut *data);
-+
-+enum ds_return dal_ds_dispatch_set_regamma_lut(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	struct ds_regamma_lut *data);
-+
-+enum ds_return dal_ds_dispatch_set_info_packets(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	const struct info_frame *info_frames);
-+
-+enum ds_return dal_ds_dispatch_get_info_packets(
-+	struct ds_dispatch *adj,
-+	uint32_t display_index,
-+	struct info_frame *info_frames);
-+
-+bool dal_ds_dispatch_initialize_adjustment(struct ds_dispatch *ds);
-+
-+void dal_ds_dispatch_cleanup_adjustment(struct ds_dispatch *ds);
-+
-+bool dal_ds_dispatch_build_post_set_mode_adj(
-+	struct ds_dispatch *ds,
-+	const struct path_mode *mode,
-+	struct display_path *display_path,
-+	struct hw_adjustment_set *set);
-+
-+bool dal_ds_dispatch_build_color_control_adj(
-+	struct ds_dispatch *ds,
-+	const struct path_mode *mode,
-+	struct display_path *display_path,
-+	struct hw_adjustment_set *set);
-+
-+bool dal_ds_dispatch_build_include_adj(
-+	struct ds_dispatch *ds,
-+	const struct path_mode *mode,
-+	struct display_path *display_path,
-+	struct hw_path_mode *hw_mode,
-+	struct hw_adjustment_set *set);
-+
-+bool dal_ds_dispatch_apply_scaling(
-+	struct ds_dispatch *ds,
-+	const struct path_mode *mode,
-+	struct adj_container *adj_container,
-+	enum build_path_set_reason reason,
-+	struct hw_path_mode *hw_mode);
-+
-+void dal_ds_dispatch_update_adj_container_for_path_with_mode_info(
-+	struct ds_dispatch *ds,
-+	struct display_path *display_path,
-+	const struct path_mode *path_mode);
-+
-+enum ds_return dal_ds_dispatch_get_adjustment_info(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id adjust_id,
-+	struct adjustment_info *adj_info);
-+
-+bool dal_ds_dispatch_include_adjustment(
-+	struct ds_dispatch *ds,
-+	struct display_path *disp_path,
-+	struct ds_adj_id_value adj,
-+	struct hw_adjustment_set *set);
-+
-+enum ds_return dal_ds_dispatch_set_gamma_adjustment(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum adjustment_id ad_id,
-+	const struct raw_gamma_ramp *gamma);
-+
-+void dal_ds_dispatch_update_adj_container_for_path_with_color_space(
-+	struct ds_dispatch *ds,
-+	uint32_t display_index,
-+	enum ds_color_space color_space);
-+
-+void dal_ds_dispatch_setup_default_regamma(
-+	struct ds_dispatch *ds,
-+	struct ds_regamma_lut *regamma);
-+
-+#endif /* __DAL_ADJUSTMENT_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/adjustment_types.h b/drivers/gpu/drm/amd/dal/include/adjustment_types.h
-new file mode 100644
-index 0000000..f6c0d61
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/adjustment_types.h
-@@ -0,0 +1,420 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ADJUSTMENT_TYPES_H__
-+#define __DAL_ADJUSTMENT_TYPES_H__
-+
-+#include "dal_services.h"
-+
-+/* make sure to update this when updating adj_global_info_array */
-+#define CURRENT_ADJUSTMENT_NUM 12
-+#define MAX_ADJUSTMENT_NUM (ADJ_ID_END - ADJ_ID_BEGIN)
-+#define REGAMMA_VALUE	256
-+#define REGAMMA_RANGE	(REGAMMA_VALUE*3)
-+#define ADJUST_DIVIDER	100
-+#define GAMUT_DIVIDER	10000
-+
-+
-+enum adjustment_id {
-+
-+	/*this useful type when i need to indicate unknown adjustment and code
-+	look if not the specific type*/
-+	ADJ_ID_INVALID,
-+
-+	ADJ_ID_CONTRAST,
-+	ADJ_ID_BRIGHTNESS,
-+	ADJ_ID_HUE,
-+	ADJ_ID_SATURATION,
-+	ADJ_ID_GAMMA_RAMP,
-+	ADJ_ID_GAMMA_RAMP_REGAMMA_UPDATE,
-+	ADJ_ID_TEMPERATURE,
-+	ADJ_ID_NOMINAL_RANGE_RGB_LIMITED,
-+
-+	ADJ_ID_LP_FILTER_DEFLICKER,
-+	ADJ_ID_HP_FILTER_DEFLICKER,
-+	ADJ_ID_SHARPNESS_GAIN, /*0 - 10*/
-+
-+	ADJ_ID_REDUCED_BLANKING,
-+	ADJ_ID_COHERENT,
-+	ADJ_ID_MULTIMEDIA_PASS_THROUGH,
-+
-+	ADJ_ID_VERTICAL_POSITION,
-+	ADJ_ID_HORIZONTA_LPOSITION,
-+	ADJ_ID_VERTICAL_SIZE,
-+	ADJ_ID_HORIZONTAL_SIZE,
-+	ADJ_ID_VERTICAL_SYNC,
-+	ADJ_ID_HORIZONTAL_SYNC,
-+	ADJ_ID_OVERSCAN,
-+	ADJ_ID_COMPOSITE_SYNC,
-+
-+	ADJ_ID_BIT_DEPTH_REDUCTION,/*CWDDEDI_DISPLAY_ADJINFOTYPE_BITVECTOR*/
-+	ADJ_ID_UNDERSCAN,/*CWDDEDI_DISPLAY_ADJINFOTYPE_RANGE*/
-+	ADJ_ID_UNDERSCAN_TYPE,/*CWDDEDI_DISPLAY_ADJINFOTYPE_RANGE*/
-+	ADJ_ID_TEMPERATURE_SOURCE,/*CWDDEDI_DISPLAY_ADJINFOTYPE_BITVECTOR*/
-+
-+	ADJ_ID_OVERLAY_BRIGHTNESS,
-+	ADJ_ID_OVERLAY_CONTRAST,
-+	ADJ_ID_OVERLAY_SATURATION,
-+	ADJ_ID_OVERLAY_HUE,
-+	ADJ_ID_OVERLAY_GAMMA,
-+	ADJ_ID_OVERLAY_ALPHA,
-+	ADJ_ID_OVERLAY_ALPHA_PER_PIX,
-+	ADJ_ID_OVERLAY_INV_GAMMA,
-+	ADJ_ID_OVERLAY_TEMPERATURE,/*done ,but code is commented*/
-+	ADJ_ID_OVERLAY_NOMINAL_RANGE_RGB_LIMITED,
-+
-+
-+	ADJ_ID_UNDERSCAN_TV_INTERNAL,/*internal usage only for HDMI*/
-+				/*custom TV modes*/
-+	ADJ_ID_DRIVER_REQUESTED_GAMMA,/*used to get current gamma*/
-+	ADJ_ID_GAMUT_SOURCE_GRPH,/*logical adjustment visible for DS and CDB*/
-+	ADJ_ID_GAMUT_SOURCE_OVL,/*logical adjustment visible for DS and CDB*/
-+	ADJ_ID_GAMUT_DESTINATION,/*logical adjustment visible for DS and CDB*/
-+	ADJ_ID_REGAMMA,/*logical adjustment visible for DS and CDB*/
-+	ADJ_ID_ITC_ENABLE,/*ITC flag enable by default*/
-+	ADJ_ID_CNC_CONTENT,/*display image content*/
-+	/*internal adjustment, in order to provide backward compatibility
-+	 gamut with color temperature*/
-+
-+	/* Backlight Adjustment Group*/
-+	ADJ_ID_BACKLIGHT,
-+	ADJ_ID_BACKLIGHT_OPTIMIZATION,
-+
-+	/* flag the first and last*/
-+	ADJ_ID_BEGIN = ADJ_ID_CONTRAST,
-+	ADJ_ID_END = ADJ_ID_BACKLIGHT_OPTIMIZATION,
-+};
-+
-+enum adjustment_data_type {
-+	ADJ_RANGED,
-+	ADJ_BITVECTOR,
-+	ADJ_LUT /* not handled currently */
-+};
-+
-+union adjustment_property {
-+	uint32_t u32all;
-+	struct {
-+		/*per mode adjustment*/
-+		uint32_t SAVED_WITHMODE:1;
-+		/*per edid adjustment*/
-+		uint32_t SAVED_WITHEDID:1;
-+		/*adjustment not visible to HWSS*/
-+		uint32_t CALCULATE:1;
-+		/*explisit adjustment applied by HWSS*/
-+		uint32_t INC_IN_SET_MODE:1;
-+		/*adjustment requires set mode to be applied*/
-+		uint32_t SETMODE_REQ:1;
-+		/*adjustment is applied at the end of set mode*/
-+		uint32_t POST_SET:1;
-+/*when adjustment is applied its value should be stored
-+in place and not wait for flush call*/
-+		uint32_t SAVE_IN_PLACE:1;
-+		/*adjustment is always apply*/
-+		uint32_t FORCE_SET:1;
-+		/*this adjustment is specific to individual display path.*/
-+		uint32_t SAVED_WITH_DISPLAY_IDX:1;
-+		uint32_t RESERVED_23:23;
-+	} bits;
-+};
-+
-+enum adjustment_state {
-+	ADJUSTMENT_STATE_INVALID,
-+	ADJUSTMENT_STATE_VALID,
-+	ADJUSTMENT_STATE_REQUESTED,
-+	ADJUSTMENT_STATE_COMMITTED_TO_HW,
-+};
-+
-+/* AdjustmentInfo structure - it keeps either ranged data or discrete*/
-+struct adjustment_info {
-+	enum adjustment_data_type adj_data_type;
-+	union adjustment_property adj_prop;
-+	enum adjustment_state adj_state;
-+	enum adjustment_id adj_id;
-+
-+	union data {
-+		struct ranged {
-+			int32_t min;
-+			int32_t max;
-+			int32_t def;
-+			int32_t step;
-+			int32_t cur;
-+		} ranged;
-+		struct bit_vector {
-+			int32_t system_supported;
-+			int32_t current_supported;
-+			int32_t default_val;
-+		} bit_vector;
-+	} adj_data;
-+};
-+
-+/* adjustment category
-+this should be a MASK struct with the bitfileds!!!
-+since it could be crt and cv and dfp!!!
-+the only fit is for overlay!!!*/
-+enum adjustment_category {
-+	CAT_ALL,
-+	CAT_CRT,
-+	CAT_DFP,
-+	CAT_LCD,
-+	CAT_OVERLAY,
-+	CAT_INVALID
-+};
-+
-+enum raw_gamma_ramp_type {
-+	GAMMA_RAMP_TYPE_UNINITIALIZED,
-+	GAMMA_RAMP_TYPE_DEFAULT,
-+	GAMMA_RAMP_TYPE_RGB256,
-+	GAMMA_RAMP_TYPE_FIXED_POINT
-+};
-+
-+struct raw_gamma_ramp_rgb {
-+	uint32_t red;
-+	uint32_t green;
-+	uint32_t blue;
-+};
-+
-+#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
-+struct raw_gamma_ramp {
-+	enum raw_gamma_ramp_type type;
-+	struct raw_gamma_ramp_rgb rgb_256[NUM_OF_RAW_GAMMA_RAMP_RGB_256];
-+	uint32_t size;
-+};
-+
-+struct ds_underscan_info {
-+	uint32_t default_width;
-+	uint32_t default_height;
-+	uint32_t max_width;
-+	uint32_t max_height;
-+	uint32_t min_width;
-+	uint32_t min_height;
-+	uint32_t h_step;
-+	uint32_t v_step;
-+	uint32_t default_x_pos;
-+	uint32_t default_y_pos;
-+};
-+
-+struct ds_overscan {
-+	uint32_t left;
-+	uint32_t right;
-+	uint32_t top;
-+	uint32_t bottom;
-+};
-+
-+enum ds_color_space {
-+	DS_COLOR_SPACE_UNKNOWN = 0,
-+	DS_COLOR_SPACE_SRGB_FULLRANGE = 1,
-+	DS_COLOR_SPACE_SRGB_LIMITEDRANGE,
-+	DS_COLOR_SPACE_YPBPR601,
-+	DS_COLOR_SPACE_YPBPR709,
-+	DS_COLOR_SPACE_YCBCR601,
-+	DS_COLOR_SPACE_YCBCR709,
-+	DS_COLOR_SPACE_NMVPU_SUPERAA,
-+	DS_COLOR_SPACE_YCBCR601_YONLY,
-+	DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/
-+};
-+
-+enum ds_underscan_options {
-+	DS_UNDERSCAN_OPTION_DEFAULT = 0,
-+	DS_UNDERSCAN_OPTION_USECEA861D
-+};
-+
-+enum dpms_state {
-+	DPMS_NONE = 0,
-+	DPMS_ON,
-+	DPMS_OFF,
-+};
-+
-+enum ds_gamut_reference {
-+	DS_GAMUT_REFERENCE_DESTINATION = 0,
-+	DS_GAMUT_REFERENCE_SOURCE,
-+};
-+
-+enum ds_gamut_content {
-+	DS_GAMUT_CONTENT_GRAPHICS = 0,
-+	DS_GAMUT_CONTENT_VIDEO,
-+};
-+
-+struct ds_gamut_reference_data {
-+	enum ds_gamut_reference gamut_ref;
-+	enum ds_gamut_content gamut_content;
-+};
-+
-+union ds_custom_gamut_type {
-+	uint32_t u32all;
-+	struct {
-+		uint32_t CUSTOM_WHITE_POINT:1;
-+		uint32_t CUSTOM_GAMUT_SPACE:1;
-+		uint32_t reserved:30;
-+	} bits;
-+};
-+
-+union ds_gamut_spaces {
-+	uint32_t u32all;
-+	struct {
-+		uint32_t GAMUT_SPACE_CCIR709:1;
-+		uint32_t GAMUT_SPACE_CCIR601:1;
-+		uint32_t GAMUT_SPACE_ADOBERGB:1;
-+		uint32_t GAMUT_SPACE_CIERGB:1;
-+		uint32_t GAMUT_SPACE_CUSTOM:1;
-+		uint32_t reserved:27;
-+	} bits;
-+};
-+
-+union ds_gamut_white_point {
-+	uint32_t u32all;
-+	struct {
-+		uint32_t GAMUT_WHITE_POINT_5000:1;
-+		uint32_t GAMUT_WHITE_POINT_6500:1;
-+		uint32_t GAMUT_WHITE_POINT_7500:1;
-+		uint32_t GAMUT_WHITE_POINT_9300:1;
-+		uint32_t GAMUT_WHITE_POINT_CUSTOM:1;
-+		uint32_t reserved:27;
-+	} bits;
-+};
-+
-+struct ds_gamut_space_coordinates {
-+	int32_t red_x;
-+	int32_t red_y;
-+	int32_t green_x;
-+	int32_t green_y;
-+	int32_t blue_x;
-+	int32_t blue_y;
-+
-+};
-+
-+struct ds_white_point_coordinates {
-+	int32_t white_x;
-+	int32_t white_y;
-+};
-+
-+struct ds_gamut_data {
-+	union ds_custom_gamut_type feature;
-+	union {
-+		uint32_t predefined;
-+		struct ds_white_point_coordinates custom;
-+
-+	} white_point;
-+
-+	union {
-+		uint32_t predefined;
-+		struct ds_gamut_space_coordinates custom;
-+
-+	} gamut;
-+};
-+
-+struct ds_set_gamut_data {
-+	struct ds_gamut_reference_data ref;
-+	struct ds_gamut_data gamut;
-+
-+};
-+
-+struct ds_get_gamut_data {
-+	struct ds_gamut_data gamut;
-+};
-+
-+struct ds_gamut_info {
-+/*mask of supported predefined gamuts ,started from DI_GAMUT_SPACE_CCIR709 ...*/
-+	union ds_gamut_spaces gamut_space;
-+/*mask of supported predefined white points,started from DI_WHITE_POINT_5000K */
-+	union ds_gamut_white_point white_point;
-+
-+};
-+
-+union ds_regamma_flags {
-+	uint32_t u32all;
-+	struct {
-+		/*custom/user gamam array is in use*/
-+		uint32_t GAMMA_RAMP_ARRAY:1;
-+		/*gamma from edid is in use*/
-+		uint32_t GAMMA_FROM_EDID:1;
-+		/*gamma from edid is in use , but only for Display Id 1.2*/
-+		uint32_t GAMMA_FROM_EDID_EX:1;
-+		/*user custom gamma is in use*/
-+		uint32_t GAMMA_FROM_USER:1;
-+		/*coeff. A0-A3 from user is in use*/
-+		uint32_t COEFF_FROM_USER:1;
-+		/*coeff. A0-A3 from edid is in use only for Display Id 1.2*/
-+		uint32_t COEFF_FROM_EDID:1;
-+		/*which ROM to choose for graphics*/
-+		uint32_t GRAPHICS_DEGAMMA_SRGB:1;
-+		/*which ROM to choose for video overlay*/
-+		uint32_t OVERLAY_DEGAMMA_SRGB:1;
-+		/*apply degamma removal in driver*/
-+		uint32_t APPLY_DEGAMMA:1;
-+
-+		uint32_t reserved:23;
-+	} bits;
-+};
-+
-+struct ds_regamma_ramp {
-+	uint16_t gamma[256 * 3]; /* gamma ramp packed as RGB */
-+
-+};
-+
-+struct ds_regamma_coefficients_ex {
-+	int32_t gamma[3];/*2400 use divider 1 000*/
-+	int32_t coeff_a0[3];/*31308 divider 10 000 000,0-red, 1-green, 2-blue*/
-+	int32_t coeff_a1[3];/*12920 use divider 1 000*/
-+	int32_t coeff_a2[3];/*55 use divider 1 000*/
-+	int32_t coeff_a3[3];/*55 use divider 1 000*/
-+};
-+
-+struct ds_regamma_lut {
-+	union ds_regamma_flags flags;
-+	union {
-+		struct ds_regamma_ramp gamma;
-+		struct ds_regamma_coefficients_ex coeff;
-+	};
-+};
-+
-+enum ds_backlight_optimization {
-+	DS_BACKLIGHT_OPTIMIZATION_DISABLE = 0,
-+	DS_BACKLIGHT_OPTIMIZATION_DESKTOP,
-+	DS_BACKLIGHT_OPTIMIZATION_DYNAMIC,
-+	DS_BACKLIGHT_OPTIMIZATION_DIMMED
-+};
-+
-+struct ds_adj_id_value {
-+	enum adjustment_id adj_id;
-+	enum adjustment_data_type adj_type;
-+	union adjustment_property adj_prop;
-+	int32_t value;
-+};
-+
-+struct gamut_data {
-+	union ds_custom_gamut_type option;
-+	union {
-+		union ds_gamut_white_point predefined;
-+		struct ds_white_point_coordinates custom;
-+
-+	} white_point;
-+
-+	union {
-+		union ds_gamut_spaces predefined;
-+		struct ds_gamut_space_coordinates custom;
-+
-+	} gamut;
-+};
-+#endif /* __DAL_ADJUSTMENT_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
-new file mode 100644
-index 0000000..bdeaaf9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
-@@ -0,0 +1,58 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of enc software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and enc permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ASIC_CAPABILITY_INTERFACE_H__
-+#define __DAL_ASIC_CAPABILITY_INTERFACE_H__
-+
-+/* Include */
-+#include "include/asic_capability_types.h"
-+
-+/* Forward declaration */
-+struct hw_asic_id;
-+
-+
-+/* ASIC capability */
-+struct asic_capability {
-+	struct dc_context *ctx;
-+	struct asic_caps caps;
-+	struct asic_stereo_3d_caps stereo_3d_caps;
-+	struct asic_bugs bugs;
-+	struct dal_asic_runtime_flags runtime_flags;
-+	uint32_t data[ASIC_DATA_MAX_NUMBER];
-+};
-+
-+
-+/**
-+ * Interfaces
-+ */
-+
-+/* Create and initialize ASIC capability */
-+struct asic_capability *dal_asic_capability_create(struct hw_asic_id *init,
-+		struct dc_context *ctx);
-+
-+/* Destroy ASIC capability and free memory space */
-+void dal_asic_capability_destroy(struct asic_capability **cap);
-+
-+#endif /* __DAL_ASIC_CAPABILITY_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
-new file mode 100644
-index 0000000..1cb9776
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
-@@ -0,0 +1,134 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_ASIC_CAPABILITY_TYPES_H__
-+#define __DAL_ASIC_CAPABILITY_TYPES_H__
-+
-+/*
-+ * ASIC Capabilities
-+ */
-+struct asic_caps {
-+	bool CONSUMER_SINGLE_SELECTED_TIMING:1;
-+	bool UNDERSCAN_ADJUST:1;
-+	bool DELTA_SIGMA_SUPPORT:1;
-+	bool PANEL_SELF_REFRESH_SUPPORTED:1;
-+	bool IS_FUSION:1;
-+	bool DP_MST_SUPPORTED:1;
-+	bool UNDERSCAN_FOR_HDMI_ONLY:1;
-+	bool DVI_CLOCK_SHARE_CAPABILITY:1;
-+	bool SUPPORT_CEA861E_FINAL:1;
-+	bool MIRABILIS_SUPPORTED:1;
-+	bool MIRABILIS_ENABLED_BY_DEFAULT:1;
-+	bool DEVICE_TAG_REMAP_SUPPORTED:1;
-+	bool HEADLESS_NO_OPM_SUPPORTED:1;
-+	bool WIRELESS_LIMIT_TO_720P:1;
-+	bool WIRELESS_FULL_TIMING_ADJUSTMENT:1;
-+	bool WIRELESS_TIMING_ADJUSTMENT:1;
-+	bool WIRELESS_COMPRESSED_AUDIO:1;
-+	bool VCE_SUPPORTED:1;
-+	bool HPD_CHECK_FOR_EDID:1;
-+	bool NO_VCC_OFF_HPD_POLLING:1;
-+	bool NEED_MC_TUNING:1;
-+	bool SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT:1;
-+	bool DFSBYPASS_DYNAMIC_SUPPORT:1;
-+	bool SUPPORT_8BPP:1;
-+};
-+
-+
-+/*
-+ * ASIC Stereo 3D Caps
-+ */
-+struct asic_stereo_3d_caps {
-+	bool SUPPORTED:1;
-+	bool DISPLAY_BASED_ON_WS:1;
-+	bool HDMI_FRAME_PACK:1;
-+	bool INTERLACE_FRAME_PACK:1;
-+	bool DISPLAYPORT_FRAME_PACK:1;
-+	bool DISPLAYPORT_FRAME_ALT:1;
-+	bool INTERLEAVE:1;
-+};
-+
-+
-+/*
-+ * ASIC Bugs
-+ */
-+struct asic_bugs {
-+	bool MST_SYMBOL_MISALIGNMENT:1;
-+	bool PSR_2X_LANE_GANGING:1;
-+	bool LB_WA_IS_SUPPORTED:1;
-+	bool ROM_REGISTER_ACCESS:1;
-+	bool PSR_WA_OVERSCAN_CRC_ERROR:1;
-+};
-+
-+
-+/*
-+ * ASIC Data
-+ */
-+enum asic_data {
-+	ASIC_DATA_FIRST = 0,
-+	ASIC_DATA_CONTROLLERS_NUM = ASIC_DATA_FIRST,
-+	ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM,
-+	ASIC_DATA_DCE_VERSION,
-+	ASIC_DATA_DCE_VERSION_MINOR,
-+	ASIC_DATA_VRAM_TYPE,
-+	ASIC_DATA_VRAM_BITWIDTH,
-+	ASIC_DATA_FEATURE_FLAGS,
-+	ASIC_DATA_LINEBUFFER_NUM,
-+	ASIC_DATA_LINEBUFFER_SIZE,
-+	ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
-+	ASIC_DATA_MC_LATENCY,
-+	ASIC_DATA_MC_LATENCY_SLOW,
-+	ASIC_DATA_CLOCKSOURCES_NUM,
-+	ASIC_DATA_MEMORYTYPE_MULTIPLIER,
-+	ASIC_DATA_STUTTERMODE,
-+	ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
-+	ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS,
-+	ASIC_DATA_REVISION_ID,
-+	ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
-+	ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
-+	ASIC_DATA_DIGFE_NUM,
-+	ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM,
-+	ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
-+	ASIC_DATA_NUM_OF_VIDEO_PLANES,
-+	ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ,
-+	ASIC_DATA_MAX_NUMBER /* end of enum */
-+};
-+
-+
-+/*
-+ * ASIC Feature Flags
-+ */
-+struct asic_feature_flags {
-+	union {
-+		uint32_t raw;
-+		struct {
-+			uint32_t LEGACY_CLIENT:1;
-+			uint32_t PACKED_PIXEL_FORMAT:1;
-+			uint32_t WORKSTATION_STEREO:1;
-+			uint32_t WORKSTATION:1;
-+		} bits;
-+	};
-+};
-+
-+#endif /* __DAL_ASIC_CAPABILITY_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_interface.h b/drivers/gpu/drm/amd/dal/include/audio_interface.h
-new file mode 100644
-index 0000000..bf21762
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/audio_interface.h
-@@ -0,0 +1,184 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUDIO_INTERFACE_H__
-+#define __DAL_AUDIO_INTERFACE_H__
-+
-+#include "audio_types.h"
-+#include "adapter_service_interface.h"
-+#include "signal_types.h"
-+#include "link_service_types.h"
-+
-+/* forward declaration */
-+struct audio;
-+struct dal_adapter_service;
-+
-+/*****  audio initialization data  *****/
-+/*
-+ * by audio, it means audio endpoint id. ASIC may have many endpoints.
-+ * upper sw layer will create one audio object instance for each endpoints.
-+ * ASIC support internal audio only. So enum number is used to differ
-+ * each endpoint
-+ */
-+struct audio_init_data {
-+	struct adapter_service *as;
-+	struct graphics_object_id audio_stream_id;
-+	struct dc_context *ctx;
-+};
-+
-+enum audio_result {
-+	AUDIO_RESULT_OK,
-+	AUDIO_RESULT_ERROR,
-+};
-+
-+/****** audio object create, destroy ******/
-+struct audio *dal_audio_create(
-+	const struct audio_init_data *init_data);
-+
-+void dal_audio_destroy(
-+	struct audio **audio);
-+
-+/****** graphics object interface ******/
-+const struct graphics_object_id dal_audio_get_graphics_object_id(
-+	const struct audio *audio);
-+
-+/* Enumerate Graphics Object supported Input/Output Signal Types */
-+uint32_t dal_audio_enumerate_input_signals(
-+	struct audio *audio);
-+
-+uint32_t dal_audio_enumerate_output_signals(
-+	struct audio *audio);
-+
-+/*  Check if signal supported by GraphicsObject  */
-+bool dal_audio_is_input_signal_supported(
-+	struct audio *audio,
-+	enum signal_type signal);
-+
-+bool dal_audio_is_output_signal_supported(
-+	struct audio *audio,
-+	enum signal_type signal);
-+
-+
-+/***** programming interface *****/
-+
-+/* perform power up sequence (boot up, resume, recovery) */
-+enum audio_result dal_audio_power_up(
-+	struct audio *audio);
-+
-+/* perform power down (shut down, stand by) */
-+enum audio_result dal_audio_power_down(
-+	struct audio *audio);
-+
-+/* setup audio */
-+enum audio_result dal_audio_setup(
-+	struct audio *audio,
-+	struct audio_output *output,
-+	struct audio_info *info);
-+
-+/* enable audio */
-+enum audio_result dal_audio_enable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal);
-+
-+/* disable audio */
-+enum audio_result dal_audio_disable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal);
-+
-+/* enable azalia audio endpoint */
-+enum audio_result dal_audio_enable_azalia_audio_jack_presence(
-+	struct audio *audio,
-+	enum engine_id engine_id);
-+
-+/* disable azalia audio endpoint */
-+enum audio_result dal_audio_disable_azalia_audio_jack_presence(
-+	struct audio *audio,
-+	enum engine_id engine_id);
-+
-+/* unmute audio */
-+enum audio_result dal_audio_unmute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal);
-+
-+/* mute audio */
-+enum audio_result dal_audio_mute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal);
-+
-+
-+/***** information interface *****/
-+
-+struct audio_feature_support dal_audio_get_supported_features(
-+	struct audio *audio);
-+
-+/* get audio bandwidth information */
-+void dal_audio_check_audio_bandwidth(
-+	struct audio *audio,
-+	const struct audio_crtc_info *info,
-+	uint32_t channel_count,
-+	enum signal_type signal,
-+	union audio_sample_rates *sample_rates);
-+
-+/* Enable multi channel split */
-+void dal_audio_enable_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable);
-+
-+/* get current multi channel split. */
-+enum audio_result dal_audio_get_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping);
-+
-+/* set payload value for the unsolicited response */
-+void dal_audio_set_unsolicited_response_payload(
-+	struct audio *audio,
-+	enum audio_payload payload);
-+
-+/*Assign GTC group and enable GTC value embedding*/
-+void dal_audio_enable_gtc_embedding_with_group(
-+	struct audio *audio,
-+	uint32_t group_num,
-+	uint32_t audio_latency);
-+
-+/* Disable GTC value embedding */
-+void dal_audio_disable_gtc_embedding(
-+	struct audio *audio);
-+
-+/* Update audio wall clock source */
-+void dal_audio_setup_audio_wall_dto(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h
-new file mode 100644
-index 0000000..e9c2ab3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/audio_types.h
-@@ -0,0 +1,275 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __AUDIO_TYPES_H__
-+#define __AUDIO_TYPES_H__
-+
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+
-+#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
-+#define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18
-+#define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF
-+
-+
-+struct audio_pll_hw_settings {
-+	uint32_t feed_back_divider;
-+	uint32_t step_size_integer;
-+	uint32_t step_size_fraction;
-+	uint32_t step_range;
-+};
-+
-+struct audio_clock_info {
-+	/* pixel clock frequency*/
-+	uint32_t pixel_clock_in_10khz;
-+	/* N - 32KHz audio */
-+	uint32_t n_32khz;
-+	/* CTS - 32KHz audio*/
-+	uint32_t cts_32khz;
-+	uint32_t n_44khz;
-+	uint32_t cts_44khz;
-+	uint32_t n_48khz;
-+	uint32_t cts_48khz;
-+};
-+
-+struct azalia_clock_info {
-+	uint32_t pixel_clock_in_10khz;
-+	uint32_t audio_dto_phase;
-+	uint32_t audio_dto_module;
-+	uint32_t audio_dto_wall_clock_ratio;
-+};
-+
-+enum audio_dto_source {
-+	DTO_SOURCE_UNKNOWN = 0,
-+	DTO_SOURCE_ID0,
-+	DTO_SOURCE_ID1,
-+	DTO_SOURCE_ID2,
-+	DTO_SOURCE_ID3,
-+	DTO_SOURCE_ID4,
-+	DTO_SOURCE_ID5
-+};
-+
-+union audio_sample_rates {
-+	struct sample_rates {
-+		uint8_t RATE_32:1;
-+		uint8_t RATE_44_1:1;
-+		uint8_t RATE_48:1;
-+		uint8_t RATE_88_2:1;
-+		uint8_t RATE_96:1;
-+		uint8_t RATE_176_4:1;
-+		uint8_t RATE_192:1;
-+	} rate;
-+
-+	uint8_t all;
-+};
-+
-+enum audio_format_code {
-+	AUDIO_FORMAT_CODE_FIRST = 1,
-+	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
-+
-+	AUDIO_FORMAT_CODE_AC3,
-+	/*Layers 1 & 2 */
-+	AUDIO_FORMAT_CODE_MPEG1,
-+	/*MPEG1 Layer 3 */
-+	AUDIO_FORMAT_CODE_MP3,
-+	/*multichannel */
-+	AUDIO_FORMAT_CODE_MPEG2,
-+	AUDIO_FORMAT_CODE_AAC,
-+	AUDIO_FORMAT_CODE_DTS,
-+	AUDIO_FORMAT_CODE_ATRAC,
-+	AUDIO_FORMAT_CODE_1BITAUDIO,
-+	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
-+	AUDIO_FORMAT_CODE_DTS_HD,
-+	AUDIO_FORMAT_CODE_MAT_MLP,
-+	AUDIO_FORMAT_CODE_DST,
-+	AUDIO_FORMAT_CODE_WMAPRO,
-+	AUDIO_FORMAT_CODE_LAST,
-+	AUDIO_FORMAT_CODE_COUNT =
-+		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
-+};
-+
-+struct audio_mode {
-+	 /* ucData[0] [6:3] */
-+	enum audio_format_code format_code;
-+	/* ucData[0] [2:0] */
-+	uint8_t channel_count;
-+	/* ucData[1] */
-+	union audio_sample_rates sample_rates;
-+	union {
-+		/* for LPCM */
-+		uint8_t sample_size;
-+		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
-+		uint8_t max_bit_rate;
-+		/* for Audio Formats 9-15 */
-+		uint8_t vendor_specific;
-+	};
-+};
-+
-+struct audio_info_flags {
-+
-+	union {
-+
-+		struct audio_speaker_flags {
-+			uint32_t FL_FR:1;
-+			uint32_t LFE:1;
-+			uint32_t FC:1;
-+			uint32_t RL_RR:1;
-+			uint32_t RC:1;
-+			uint32_t FLC_FRC:1;
-+			uint32_t RLC_RRC:1;
-+			uint32_t SUPPORT_AI:1;
-+		} speaker_flags;
-+
-+		struct audio_speaker_info {
-+			uint32_t ALLSPEAKERS:7;
-+			uint32_t SUPPORT_AI:1;
-+		} info;
-+
-+		uint8_t all;
-+	};
-+};
-+
-+
-+/*struct audio_info_flags {
-+	struct audio_speaker_flags {
-+		uint32_t FL_FR:1;
-+		uint32_t LFE:1;
-+		uint32_t FC:1;
-+		uint32_t RL_RR:1;
-+		uint32_t RC:1;
-+		uint32_t FLC_FRC:1;
-+		uint32_t RLC_RRC:1;
-+		uint32_t SUPPORT_AI:1;
-+	};
-+
-+	struct audio_speaker_info {
-+		uint32_t ALLSPEAKERS:7;
-+		uint32_t SUPPORT_AI:1;
-+	};
-+
-+	union {
-+		struct audio_speaker_flags speaker_flags;
-+		struct audio_speaker_info info;
-+	};
-+};
-+*/
-+
-+union audio_cea_channels {
-+	uint8_t all;
-+	struct audio_cea_channels_bits {
-+		uint32_t FL:1;
-+		uint32_t FR:1;
-+		uint32_t LFE:1;
-+		uint32_t FC:1;
-+		uint32_t RL_RC:1;
-+		uint32_t RR:1;
-+		uint32_t RC_RLC_FLC:1;
-+		uint32_t RRC_FRC:1;
-+	} channels;
-+};
-+
-+struct audio_info {
-+	struct audio_info_flags flags;
-+	uint32_t video_latency;
-+	uint32_t audio_latency;
-+	uint32_t display_index;
-+	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
-+	uint32_t manufacture_id;
-+	uint32_t product_id;
-+	/* PortID used for ContainerID when defined */
-+	uint32_t port_id[2];
-+	uint32_t mode_count;
-+	/* this field must be last in this struct */
-+	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
-+};
-+
-+struct audio_crtc_info {
-+	uint32_t h_total;
-+	uint32_t h_active;
-+	uint32_t v_active;
-+	uint32_t pixel_repetition;
-+	uint32_t requested_pixel_clock; /* in KHz */
-+	uint32_t calculated_pixel_clock; /* in KHz */
-+	uint32_t refresh_rate;
-+	enum dc_color_depth color_depth;
-+	bool interlaced;
-+};
-+
-+/* PLL information required for AZALIA DTO calculation */
-+
-+struct audio_pll_info {
-+	uint32_t dp_dto_source_clock_in_khz;
-+	uint32_t feed_back_divider;
-+	enum audio_dto_source dto_source;
-+	bool ss_enabled;
-+	uint32_t ss_percentage;
-+	uint32_t ss_percentage_divider;
-+};
-+
-+struct audio_channel_associate_info {
-+	union {
-+		struct {
-+			uint32_t ALL_CHANNEL_FL:4;
-+			uint32_t ALL_CHANNEL_FR:4;
-+			uint32_t ALL_CHANNEL_FC:4;
-+			uint32_t ALL_CHANNEL_Sub:4;
-+			uint32_t ALL_CHANNEL_SL:4;
-+			uint32_t ALL_CHANNEL_SR:4;
-+			uint32_t ALL_CHANNEL_BL:4;
-+			uint32_t ALL_CHANNEL_BR:4;
-+		} bits;
-+		uint32_t u32all;
-+	};
-+};
-+
-+struct audio_output {
-+	/* Front DIG id. */
-+	enum engine_id engine_id;
-+	/* encoder output signal */
-+	enum signal_type signal;
-+	/* video timing */
-+	struct audio_crtc_info crtc_info;
-+	/* PLL for audio */
-+	struct audio_pll_info pll_info;
-+};
-+
-+struct audio_feature_support {
-+	/* supported engines*/
-+	uint32_t ENGINE_DIGA:1;
-+	uint32_t ENGINE_DIGB:1;
-+	uint32_t ENGINE_DIGC:1;
-+	uint32_t ENGINE_DIGD:1;
-+	uint32_t ENGINE_DIGE:1;
-+	uint32_t ENGINE_DIGF:1;
-+	uint32_t ENGINE_DIGG:1;
-+	uint32_t ENGINE_DVO:1;
-+	uint32_t MULTISTREAM_AUDIO:1;
-+};
-+
-+enum audio_payload {
-+	CHANNEL_SPLIT_MAPPINGCHANG = 0x9,
-+};
-+
-+#endif /* __AUDIO_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-new file mode 100644
-index 0000000..6269164
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -0,0 +1,294 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_INTERFACE_H__
-+#define __DAL_BIOS_PARSER_INTERFACE_H__
-+
-+#include "bios_parser_types.h"
-+#include "adapter_service_types.h"
-+#include "gpio_types.h"
-+
-+struct adapter_service;
-+struct bios_parser;
-+
-+struct bp_gpio_cntl_info {
-+	uint32_t id;
-+	enum gpio_pin_output_state state;
-+};
-+
-+enum bp_result {
-+	BP_RESULT_OK = 0, /* There was no error */
-+	BP_RESULT_BADINPUT, /*Bad input parameter */
-+	BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
-+	BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
-+	BP_RESULT_NORECORD, /* Record can't be found */
-+	BP_RESULT_FAILURE
-+};
-+
-+struct bp_init_data {
-+	struct dc_context *ctx;
-+	uint8_t *bios;
-+};
-+
-+struct bios_parser *dal_bios_parser_create(
-+	struct bp_init_data *init,
-+	struct adapter_service *as);
-+void dal_bios_parser_destroy(
-+	struct bios_parser **bp);
-+void dal_bios_parser_power_down(
-+	struct bios_parser *bp);
-+void dal_bios_parser_power_up(
-+	struct bios_parser *bp);
-+
-+uint8_t dal_bios_parser_get_encoders_number(
-+	struct bios_parser *bp);
-+uint8_t dal_bios_parser_get_connectors_number(
-+	struct bios_parser *bp);
-+uint32_t dal_bios_parser_get_oem_ddc_lines_number(
-+	struct bios_parser *bp);
-+struct graphics_object_id dal_bios_parser_get_encoder_id(
-+	struct bios_parser *bp,
-+	uint32_t i);
-+struct graphics_object_id dal_bios_parser_get_connector_id(
-+	struct bios_parser *bp,
-+	uint8_t connector_index);
-+uint32_t dal_bios_parser_get_src_number(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id);
-+uint32_t dal_bios_parser_get_dst_number(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id);
-+uint32_t dal_bios_parser_get_gpio_record(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct bp_gpio_cntl_info *gpio_record,
-+	uint32_t record_size);
-+enum bp_result dal_bios_parser_get_src_obj(
-+	struct bios_parser *bp,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *src_object_id);
-+enum bp_result dal_bios_parser_get_dst_obj(
-+	struct bios_parser *bp,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *dest_object_id);
-+enum bp_result dal_bios_parser_get_i2c_info(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct graphics_object_i2c_info *info);
-+enum bp_result dal_bios_parser_get_oem_ddc_info(
-+	struct bios_parser *bp,
-+	uint32_t index,
-+	struct graphics_object_i2c_info *info);
-+enum bp_result dal_bios_parser_get_voltage_ddc_info(
-+	struct bios_parser *bp,
-+	uint32_t index,
-+	struct graphics_object_i2c_info *info);
-+enum bp_result dal_bios_parser_get_thermal_ddc_info(
-+	struct bios_parser *bp,
-+	uint32_t i2c_channel_id,
-+	struct graphics_object_i2c_info *info);
-+enum bp_result dal_bios_parser_get_hpd_info(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct graphics_object_hpd_info *info);
-+enum bp_result dal_bios_parser_get_device_tag(
-+	struct bios_parser *bp,
-+	struct graphics_object_id connector_object_id,
-+	uint32_t device_tag_index,
-+	struct connector_device_tag_info *info);
-+enum bp_result dal_bios_parser_get_firmware_info(
-+	struct bios_parser *bp,
-+	struct firmware_info *info);
-+enum bp_result dal_bios_parser_get_spread_spectrum_info(
-+	struct bios_parser *bp,
-+	enum as_signal_type signal,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info);
-+uint32_t dal_bios_parser_get_ss_entry_number(
-+	struct bios_parser *bp,
-+	enum as_signal_type signal);
-+enum bp_result dal_bios_parser_get_embedded_panel_info(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info);
-+enum bp_result dal_bios_parser_enum_embedded_panel_patch_mode(
-+	struct bios_parser *bp,
-+	uint32_t index,
-+	struct embedded_panel_patch_mode *mode);
-+enum bp_result dal_bios_parser_get_gpio_pin_info(
-+	struct bios_parser *bp,
-+	uint32_t gpio_id,
-+	struct gpio_pin_info *info);
-+enum bp_result dal_bios_parser_get_embedded_panel_info(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info);
-+enum bp_result dal_bios_parser_get_gpio_pin_info(
-+	struct bios_parser *bp,
-+	uint32_t gpio_id,
-+	struct gpio_pin_info *info);
-+enum bp_result dal_bios_parser_get_faked_edid_len(
-+	struct bios_parser *bp,
-+	uint32_t *len);
-+enum bp_result dal_bios_parser_get_faked_edid_buf(
-+	struct bios_parser *bp,
-+	uint8_t *buff,
-+	uint32_t len);
-+enum bp_result dal_bios_parser_get_encoder_cap_info(
-+	struct bios_parser *bp,
-+	struct graphics_object_id object_id,
-+	struct bp_encoder_cap_info *info);
-+enum bp_result dal_bios_parser_get_din_connector_info(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id,
-+	struct din_connector_info *info);
-+
-+bool dal_bios_parser_is_lid_open(
-+	struct bios_parser *bp);
-+bool dal_bios_parser_is_lid_status_changed(
-+	struct bios_parser *bp);
-+bool dal_bios_parser_is_display_config_changed(
-+	struct bios_parser *bp);
-+bool dal_bios_parser_is_accelerated_mode(
-+	struct bios_parser *bp);
-+void dal_bios_parser_set_scratch_lcd_scale(
-+	struct bios_parser *bp,
-+	enum lcd_scale scale);
-+enum lcd_scale  dal_bios_parser_get_scratch_lcd_scale(
-+	struct bios_parser *bp);
-+void dal_bios_parser_get_bios_event_info(
-+	struct bios_parser *bp,
-+	struct bios_event_info *info);
-+void dal_bios_parser_update_requested_backlight_level(
-+	struct bios_parser *bp,
-+	uint32_t backlight_8bit);
-+uint32_t dal_bios_parser_get_requested_backlight_level(
-+	struct bios_parser *bp);
-+void dal_bios_parser_take_backlight_control(
-+	struct bios_parser *bp,
-+	bool cntl);
-+bool dal_bios_parser_is_active_display(
-+	struct bios_parser *bp,
-+	enum signal_type signal,
-+	const struct connector_device_tag_info *device_tag);
-+enum controller_id dal_bios_parser_get_embedded_display_controller_id(
-+	struct bios_parser *bp);
-+uint32_t dal_bios_parser_get_embedded_display_refresh_rate(
-+	struct bios_parser *bp);
-+void dal_bios_parser_set_scratch_connected(
-+	struct bios_parser *bp,
-+	struct graphics_object_id connector_id,
-+	bool connected,
-+	const struct connector_device_tag_info *device_tag);
-+void dal_bios_parser_prepare_scratch_active_and_requested(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	enum signal_type signal,
-+	const struct connector_device_tag_info *device_tag);
-+void dal_bios_parser_set_scratch_active_and_requested(
-+	struct bios_parser *bp);
-+void dal_bios_parser_set_scratch_critical_state(
-+	struct bios_parser *bp,
-+	bool state);
-+void dal_bios_parser_set_scratch_acc_mode_change(
-+	struct bios_parser *bp);
-+
-+bool dal_bios_parser_is_device_id_supported(
-+	struct bios_parser *bp,
-+	struct device_id id);
-+
-+/* COMMANDS */
-+
-+enum bp_result dal_bios_parser_encoder_control(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+enum bp_result dal_bios_parser_transmitter_control(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+enum bp_result dal_bios_parser_crt_control(
-+	struct bios_parser *bp,
-+	enum engine_id engine_id,
-+	bool enable,
-+	uint32_t pixel_clock);
-+enum bp_result dal_bios_parser_dvo_encoder_control(
-+	struct bios_parser *bp,
-+	struct bp_dvo_encoder_control *cntl);
-+enum bp_result dal_bios_parser_enable_crtc(
-+	struct bios_parser *bp,
-+	enum controller_id id,
-+	bool enable);
-+enum bp_result dal_bios_parser_adjust_pixel_clock(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params);
-+enum bp_result dal_bios_parser_set_pixel_clock(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+enum bp_result dal_bios_parser_program_crtc_timing(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params);
-+enum bp_result dal_bios_parser_blank_crtc(
-+	struct bios_parser *bp,
-+	struct bp_blank_crtc_parameters *bp_params,
-+	bool blank);
-+enum bp_result dal_bios_parser_set_overscan(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_overscan_parameters *bp_params);
-+enum bp_result dal_bios_parser_crtc_source_select(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params);
-+enum bp_result dal_bios_parser_program_display_engine_pll(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+enum bp_result dal_bios_parser_get_divider_for_target_display_clock(
-+	struct bios_parser *bp,
-+	struct bp_display_clock_parameters *bp_params);
-+enum signal_type dal_bios_parser_dac_load_detect(
-+	struct bios_parser *bp,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type display_signal);
-+enum bp_result dal_bios_parser_enable_memory_requests(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable);
-+enum bp_result dal_bios_parser_external_encoder_control(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl);
-+enum bp_result dal_bios_parser_enable_disp_power_gating(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	enum bp_pipe_control_action action);
-+
-+void dal_bios_parser_post_init(struct bios_parser *bp);
-+
-+/* Parse integrated BIOS info */
-+struct integrated_info *dal_bios_parser_create_integrated_info(
-+	struct bios_parser *bp);
-+
-+/* Destroy provided integrated info */
-+void dal_bios_parser_destroy_integrated_info(struct dc_context *ctx, struct integrated_info **info);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-new file mode 100644
-index 0000000..da7d5f2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -0,0 +1,305 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_TYPES_H__
-+#define __DAL_BIOS_PARSER_TYPES_H__
-+
-+#include "include/signal_types.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "link_service_types.h"
-+
-+enum bp_encoder_control_action {
-+	/* direct VBIOS translation! Just to simplify the translation */
-+	ENCODER_CONTROL_DISABLE = 0,
-+	ENCODER_CONTROL_ENABLE,
-+	ENCODER_CONTROL_SETUP,
-+	ENCODER_CONTROL_INIT
-+};
-+
-+enum bp_transmitter_control_action {
-+	/* direct VBIOS translation! Just to simplify the translation */
-+	TRANSMITTER_CONTROL_DISABLE = 0,
-+	TRANSMITTER_CONTROL_ENABLE,
-+	TRANSMITTER_CONTROL_BACKLIGHT_OFF,
-+	TRANSMITTER_CONTROL_BACKLIGHT_ON,
-+	TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
-+	TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
-+	TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
-+	TRANSMITTER_CONTROL_INIT,
-+	TRANSMITTER_CONTROL_DEACTIVATE,
-+	TRANSMITTER_CONTROL_ACTIAVATE,
-+	TRANSMITTER_CONTROL_SETUP,
-+	TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
-+	/* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
-+	 * (power up the panel)
-+	 */
-+	TRANSMITTER_CONTROL_POWER_ON,
-+	/* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
-+	 * (power down the panel)
-+	 */
-+	TRANSMITTER_CONTROL_POWER_OFF
-+};
-+
-+enum bp_external_encoder_control_action {
-+	EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
-+	EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
-+	EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
-+	EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
-+	EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
-+	EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
-+	EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT = 0x12
-+};
-+
-+enum bp_pipe_control_action {
-+	ASIC_PIPE_DISABLE = 0,
-+	ASIC_PIPE_ENABLE,
-+	ASIC_PIPE_INIT
-+};
-+
-+struct bp_encoder_control {
-+	enum bp_encoder_control_action action;
-+	enum engine_id engine_id;
-+	enum transmitter transmitter;
-+	enum signal_type signal;
-+	enum lane_count lanes_number;
-+	enum dc_color_depth color_depth;
-+	bool enable_dp_audio;
-+	uint32_t pixel_clock; /* khz */
-+};
-+
-+struct bp_external_encoder_control {
-+	enum bp_external_encoder_control_action action;
-+	enum engine_id engine_id;
-+	enum link_rate link_rate;
-+	enum lane_count lanes_number;
-+	enum signal_type signal;
-+	enum dc_color_depth color_depth;
-+	bool coherent;
-+	struct graphics_object_id encoder_id;
-+	struct graphics_object_id connector_obj_id;
-+	uint32_t pixel_clock; /* in KHz */
-+};
-+
-+struct bp_crtc_source_select {
-+	enum engine_id engine_id;
-+	enum controller_id controller_id;
-+	/* from GPU Tx aka asic_signal */
-+	enum signal_type signal;
-+	/* sink_signal may differ from asicSignal if Translator encoder */
-+	enum signal_type sink_signal;
-+	enum display_output_bit_depth display_output_bit_depth;
-+	bool enable_dp_audio;
-+};
-+
-+struct bp_transmitter_control {
-+	enum bp_transmitter_control_action action;
-+	enum engine_id engine_id;
-+	enum transmitter transmitter; /* PhyId */
-+	enum lane_count lanes_number;
-+	enum clock_source_id pll_id; /* needed for DCE 4.0 */
-+	enum signal_type signal;
-+	enum dc_color_depth color_depth; /* not used for DCE6.0 */
-+	enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
-+	struct graphics_object_id connector_obj_id;
-+	/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
-+	 * be pixel clock * deep_color_ratio (in KHz)
-+	 */
-+	uint32_t pixel_clock;
-+	uint32_t lane_select;
-+	uint32_t lane_settings;
-+	bool coherent;
-+	bool multi_path;
-+	bool single_pll_mode;
-+};
-+
-+enum dvo_encoder_memory_rate {
-+	DVO_ENCODER_MEMORY_RATE_DDR,
-+	DVO_ENCODER_MEMORY_RATE_SDR
-+};
-+
-+enum dvo_encoder_interface_width {
-+	DVO_ENCODER_INTERFACE_WIDTH_LOW12BIT,
-+	DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT,
-+	DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT
-+};
-+
-+struct bp_dvo_encoder_control {
-+	enum bp_encoder_control_action action;
-+	enum dvo_encoder_memory_rate memory_rate;
-+	enum dvo_encoder_interface_width interface_width;
-+	uint32_t pixel_clock; /* in KHz */
-+};
-+
-+struct bp_blank_crtc_parameters {
-+	enum controller_id controller_id;
-+	uint32_t black_color_rcr;
-+	uint32_t black_color_gy;
-+	uint32_t black_color_bcb;
-+};
-+
-+struct bp_hw_crtc_timing_parameters {
-+	enum controller_id controller_id;
-+	/* horizontal part */
-+	uint32_t h_total;
-+	uint32_t h_addressable;
-+	uint32_t h_overscan_left;
-+	uint32_t h_overscan_right;
-+	uint32_t h_sync_start;
-+	uint32_t h_sync_width;
-+
-+	/* vertical part */
-+	uint32_t v_total;
-+	uint32_t v_addressable;
-+	uint32_t v_overscan_top;
-+	uint32_t v_overscan_bottom;
-+	uint32_t v_sync_start;
-+	uint32_t v_sync_width;
-+
-+	struct timing_flags {
-+		uint32_t INTERLACE:1;
-+		uint32_t PIXEL_REPETITION:4;
-+		uint32_t HSYNC_POSITIVE_POLARITY:1;
-+		uint32_t VSYNC_POSITIVE_POLARITY:1;
-+		uint32_t HORZ_COUNT_BY_TWO:1;
-+	} flags;
-+};
-+
-+struct bp_hw_crtc_overscan_parameters {
-+	enum controller_id controller_id;
-+	uint32_t h_overscan_left;
-+	uint32_t h_overscan_right;
-+	uint32_t v_overscan_top;
-+	uint32_t v_overscan_bottom;
-+};
-+
-+struct bp_adjust_pixel_clock_parameters {
-+	/* Input: Signal Type - to be converted to Encoder mode */
-+	enum signal_type signal_type;
-+	/* Input: required by V3, display pll configure parameter defined as
-+	 * following DISPPLL_CONFIG_XXXX */
-+	enum disp_pll_config display_pll_config;
-+	/* Input: Encoder object id */
-+	struct graphics_object_id encoder_object_id;
-+	/* Input: Pixel Clock (requested Pixel clock based on Video timing
-+	 * standard used) in KHz
-+	 */
-+	uint32_t pixel_clock;
-+	union {
-+		/* Input: If DVO, need passing link rate and output 12bit low or
-+		 * 24bit to VBIOS Exec table */
-+		uint32_t dvo_config;
-+		/* Input: If non DVO, not defined yet */
-+		uint32_t non_dvo_undefined;
-+	};
-+	/* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
-+	uint32_t adjusted_pixel_clock;
-+	/* Output: If non-zero, this refDiv value should be used to calculate
-+	 * other ppll params */
-+	uint32_t reference_divider;
-+	/* Output: If non-zero, this postDiv value should be used to calculate
-+	 * other ppll params */
-+	uint32_t pixel_clock_post_divider;
-+	/* Input: Enable spread spectrum */
-+	bool ss_enable;
-+};
-+
-+struct bp_pixel_clock_parameters {
-+	enum controller_id controller_id; /* (Which CRTC uses this PLL) */
-+	enum clock_source_id pll_id; /* Clock Source Id */
-+	/* signal_type -> Encoder Mode - needed by VBIOS Exec table */
-+	enum signal_type signal_type;
-+	/* Adjusted Pixel Clock (after VBIOS exec table)
-+	 * that becomes Target Pixel Clock (KHz) */
-+	uint32_t target_pixel_clock;
-+	/* Calculated Reference divider of Display PLL */
-+	uint32_t reference_divider;
-+	/* Calculated Feedback divider of Display PLL */
-+	uint32_t feedback_divider;
-+	/* Calculated Fractional Feedback divider of Display PLL */
-+	uint32_t fractional_feedback_divider;
-+	/* Calculated Pixel Clock Post divider of Display PLL */
-+	uint32_t pixel_clock_post_divider;
-+	struct graphics_object_id encoder_object_id; /* Encoder object id */
-+	/* If DVO, need passing link rate and output 12bit low or
-+	 * 24bit to VBIOS Exec table */
-+	uint32_t dvo_config;
-+	/* VBIOS returns a fixed display clock when DFS-bypass feature
-+	 * is enabled (KHz) */
-+	uint32_t dfs_bypass_display_clock;
-+	struct program_pixel_clock_flags {
-+		uint32_t FORCE_PROGRAMMING_OF_PLL:1;
-+		/* Use Engine Clock as source for Display Clock when
-+		 * programming PLL */
-+		uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
-+		/* Use external reference clock (refDivSrc for PLL) */
-+		uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
-+	} flags;
-+};
-+
-+struct bp_display_clock_parameters {
-+	uint32_t target_display_clock; /* KHz */
-+	/* Actual Display Clock set due to clock divider granularity KHz */
-+	uint32_t actual_display_clock;
-+	/* Actual Post Divider ID used to generate the actual clock */
-+	uint32_t actual_post_divider_id;
-+};
-+
-+struct spread_spectrum_flags {
-+	/* 1 = Center Spread; 0 = down spread */
-+	uint32_t CENTER_SPREAD:1;
-+	/* 1 = external; 0 = internal */
-+	uint32_t EXTERNAL_SS:1;
-+	/* 1 = delta-sigma type parameter; 0 = ver1 */
-+	uint32_t DS_TYPE:1;
-+};
-+
-+struct bp_spread_spectrum_parameters {
-+	enum clock_source_id pll_id;
-+	uint32_t percentage;
-+	uint32_t ds_frac_amount;
-+
-+	union {
-+		struct {
-+			uint32_t step;
-+			uint32_t delay;
-+			uint32_t range; /* In Hz unit */
-+		} ver1;
-+		struct {
-+			uint32_t feedback_amount;
-+			uint32_t nfrac_amount;
-+			uint32_t ds_frac_size;
-+		} ds;
-+	};
-+
-+	struct spread_spectrum_flags flags;
-+};
-+
-+struct bp_encoder_cap_info {
-+	uint32_t DP_HBR2_CAP:1;
-+	uint32_t DP_HBR2_EN:1;
-+	uint32_t RESERVED:30;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/bit_set.h b/drivers/gpu/drm/amd/dal/include/bit_set.h
-new file mode 100644
-index 0000000..3cd8d32
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/bit_set.h
-@@ -0,0 +1,61 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIT_SET_H__
-+#define __DAL_BIT_SET_H__
-+
-+struct bit_set_iterator_32 {
-+	uint32_t value;
-+};
-+
-+static inline uint32_t least_significant_bit(uint32_t bs32_container)
-+{
-+	return bs32_container & (0 - bs32_container);
-+}
-+/* iterates over bit_set_iterator by means of least significant bit purge*/
-+static inline uint32_t get_next_significant_bit(
-+		struct bit_set_iterator_32 *bs32)
-+{
-+	uint32_t lsb = least_significant_bit(bs32->value);
-+
-+	bs32->value &= ~lsb;
-+	return lsb;
-+}
-+
-+static inline void bit_set_iterator_reset_to_mask(
-+		struct bit_set_iterator_32 *bs32,
-+		uint32_t mask)
-+{
-+	bs32->value = mask;
-+}
-+
-+static inline void bit_set_iterator_construct(
-+		struct bit_set_iterator_32 *bs32,
-+		uint32_t mask)
-+{
-+	bit_set_iterator_reset_to_mask(bs32, mask);
-+}
-+
-+#endif /* __DAL_BIT_SET_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/clock_source_interface.h b/drivers/gpu/drm/amd/dal/include/clock_source_interface.h
-new file mode 100644
-index 0000000..bea4c2b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/clock_source_interface.h
-@@ -0,0 +1,89 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CLOCK_SOURCE_INTERFACE__
-+#define __DAL_CLOCK_SOURCE_INTERFACE__
-+
-+#include "include/clock_source_types.h"
-+
-+struct clock_source;
-+struct clock_source_init_data {
-+	struct adapter_service *as;
-+	struct graphics_object_id clk_src_id;
-+	struct dc_context *ctx;
-+};
-+
-+struct clock_source *dal_clock_source_create(struct clock_source_init_data *);
-+
-+void dal_clock_source_destroy(struct clock_source **clk_src);
-+
-+enum clock_source_id dal_clock_source_get_id(
-+		const struct clock_source *clk_src);
-+
-+bool dal_clock_source_is_clk_src_with_fixed_freq(
-+		const struct clock_source *clk_src);
-+
-+const struct graphics_object_id dal_clock_source_get_graphics_object_id(
-+		const struct clock_source *clk_src);
-+
-+enum clock_sharing_level dal_clock_souce_get_clk_sharing_lvl(
-+		const struct clock_source *clk_src);
-+
-+uint32_t dal_clock_source_get_pix_clk_dividers(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings);
-+
-+bool dal_clock_source_program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings);
-+
-+bool dal_clock_source_adjust_pxl_clk_by_ref_pixel_rate(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		uint32_t pix_clk_hz);
-+
-+bool dal_clock_source_adjust_pxl_clk_by_pix_amount(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		int32_t pix_num);
-+
-+uint32_t dal_clock_source_retreive_pix_rate_hz(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params);
-+
-+bool dal_clock_source_power_down_pll(struct clock_source *clk_src,
-+		enum controller_id);
-+
-+bool dal_clock_source_is_clk_in_reset(struct clock_source *clk_src);
-+
-+bool dal_clock_source_is_gen_lock_capable(struct clock_source *clk_src);
-+
-+bool dal_clock_source_is_output_signal_supported(
-+		const struct clock_source *clk_src,
-+		enum signal_type signal_type);
-+
-+#endif /*__DAL_CLOCK_SOURCE_INTERFACE__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/clock_source_types.h b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-new file mode 100644
-index 0000000..3883216
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-@@ -0,0 +1,118 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CLOCK_SOURCE_TYPES_H__
-+#define __DAL_CLOCK_SOURCE_TYPES_H__
-+
-+#include "include/signal_types.h"
-+#include "include/grph_object_ctrl_defs.h"
-+
-+/**
-+ *  ClockSharingLevel
-+ *  Enumeration for clock sharing support.
-+ *  Level <x> means sharing supported on all levels below and including <x>
-+ */
-+enum clock_sharing_level {
-+	CLOCK_SHARING_LEVEL_NOT_SHAREABLE = 0,
-+	CLOCK_SHARING_LEVEL_DP_MST_SHAREABLE,
-+	CLOCK_SHARING_LEVEL_DISPLAY_PORT_SHAREABLE
-+};
-+
-+/**
-+ *  Display Port HW De spread of Reference Clock related Parameters structure
-+ *  Store it once at boot for later usage
-+  */
-+struct csdp_ref_clk_ds_params {
-+	bool hw_dso_n_dp_ref_clk;
-+/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
-+	uint32_t avg_dp_ref_clk_khz;
-+/* Average DP Reference clock (in KHz)*/
-+	uint32_t ss_percentage_on_dp_ref_clk;
-+/* DP Reference clock SS percentage
-+ * (not to be mixed with DP IDCLK SS from PLL Settings)*/
-+	uint32_t ss_percentage_divider;
-+/* DP Reference clock SS percentage divider */
-+};
-+
-+/**
-+ *  Pixel Clock Parameters structure
-+ *  These parameters are required as input
-+ *  when calculating Pixel Clock Dividers for requested Pixel Clock
-+ */
-+struct pixel_clk_flags {
-+	uint32_t ENABLE_SS:1;
-+	uint32_t DISPLAY_BLANKED:1;
-+	uint32_t PROGRAM_PIXEL_CLOCK:1;
-+	uint32_t PROGRAM_ID_CLOCK:1;
-+};
-+
-+struct pixel_clk_params {
-+	uint32_t requested_pix_clk; /* in KHz */
-+/*> Requested Pixel Clock
-+ * (based on Video Timing standard used for requested mode)*/
-+	uint32_t requested_sym_clk; /* in KHz */
-+/*> Requested Sym Clock (relevant only for display port)*/
-+	uint32_t dp_ref_clk; /* in KHz */
-+/*> DP reference clock - calculated only for DP signal for specific cases*/
-+	struct graphics_object_id encoder_object_id;
-+/*> Encoder object Id - needed by VBIOS Exec table*/
-+	enum signal_type signal_type;
-+/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
-+	enum controller_id controller_id;
-+/*> ControllerId - which controller using this PLL*/
-+	enum dc_color_depth color_depth;
-+	struct csdp_ref_clk_ds_params de_spread_params;
-+/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
-+
-+	uint32_t dvo_cfg;
-+/*> If DVO, need passing link rate
-+ * and output 12bit low or 24bit to VBIOS Exec table*/
-+
-+	enum disp_pll_config disp_pll_cfg;
-+	struct pixel_clk_flags flags;
-+};
-+
-+/**
-+ *  Pixel Clock Dividers structure with desired Pixel Clock
-+ *  (adjusted after VBIOS exec table),
-+ *  with actually calculated Clock and reference Crystal frequency
-+ */
-+struct pll_settings {
-+	uint32_t actual_pix_clk;
-+	uint32_t adjusted_pix_clk;
-+	uint32_t calculated_pix_clk;
-+	uint32_t vco_freq;
-+	uint32_t reference_freq;
-+	uint32_t reference_divider;
-+	uint32_t feedback_divider;
-+	uint32_t fract_feedback_divider;
-+	uint32_t pix_clk_post_divider;
-+	uint32_t ss_percentage;
-+	bool use_external_clk;
-+};
-+
-+#define MAX_PLL_CALC_ERROR 0xFFFFFFFF
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/connector_interface.h b/drivers/gpu/drm/amd/dal/include/connector_interface.h
-new file mode 100644
-index 0000000..e09af7e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/connector_interface.h
-@@ -0,0 +1,82 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CONNECTOR_INTERFACE_H__
-+#define __DAL_CONNECTOR_INTERFACE_H__
-+
-+#include "adapter_service_interface.h"
-+#include "signal_types.h"
-+
-+/* forward declaration */
-+struct connector;
-+
-+struct connector_signals {
-+	const enum signal_type *signal;
-+	uint32_t number_of_signals;
-+};
-+
-+struct connector_feature_support {
-+	bool HPD_FILTERING:1;
-+	bool HW_DDC_POLLING:1;
-+	enum hpd_source_id hpd_line;
-+	enum channel_id ddc_line;
-+};
-+
-+void dal_connector_get_features(
-+		const struct connector *con,
-+		struct connector_feature_support *cfs);
-+
-+struct connector *dal_connector_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as,
-+	struct graphics_object_id go_id);
-+
-+void dal_connector_destroy(struct connector **connector);
-+
-+void dal_connector_destroy(struct connector **connector);
-+
-+const struct graphics_object_id dal_connector_get_graphics_object_id(
-+	const struct connector *connector);
-+
-+uint32_t dal_connector_enumerate_output_signals(
-+	const struct connector *connector);
-+uint32_t dal_connector_enumerate_input_signals(
-+	const struct connector *connector);
-+
-+struct connector_signals dal_connector_get_default_signals(
-+		const struct connector *connector);
-+
-+bool dal_connector_program_hpd_filter(
-+	const struct connector *connector,
-+	const uint32_t delay_on_connect_in_ms,
-+	const uint32_t delay_on_disconnect_in_ms);
-+
-+bool dal_connector_enable_ddc_polling(
-+	const struct connector *connector,
-+	const bool is_poll_for_connect);
-+
-+bool dal_connector_disable_ddc_polling(const struct connector *connector);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-new file mode 100644
-index 0000000..fa04f80
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-@@ -0,0 +1,106 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ASIC_ID_H__
-+#define __DAL_ASIC_ID_H__
-+
-+/*
-+ * ASIC internal revision ID
-+ */
-+
-+/* DCE80 (based on ci_id.h in Perforce) */
-+
-+#define	CI_BONAIRE_M_A0 0x14
-+#define	CI_BONAIRE_M_A1	0x15
-+#define	CI_HAWAII_P_A0	0x28
-+
-+#define CI_UNKNOWN	0xFF
-+
-+#define ASIC_REV_IS_BONAIRE_M(rev) \
-+	((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
-+
-+#define ASIC_REV_IS_HAWAII_P(rev) \
-+	(rev >= CI_HAWAII_P_A0)
-+
-+/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
-+#define KV_SPECTRE_A0 0x01
-+
-+/* KV2 with Spooky GFX core, including downgraded from Spectre core,
-+ * 3-4-1-1 (CU-Pix-Primitive-RB) */
-+#define KV_SPOOKY_A0 0x41
-+
-+/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define KB_KALINDI_A0 0x81
-+
-+/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define KB_KALINDI_A1 0x82
-+
-+/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define BV_KALINDI_A2 0x85
-+
-+/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define ML_GODAVARI_A0 0xA1
-+
-+/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define ML_GODAVARI_A1 0xA2
-+
-+#define KV_UNKNOWN 0xFF
-+
-+#define ASIC_REV_IS_KALINDI(rev) \
-+	((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
-+
-+#define ASIC_REV_IS_BHAVANI(rev) \
-+	((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
-+
-+#define ASIC_REV_IS_GODAVARI(rev) \
-+	((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
-+
-+/* DCE11 */
-+#define CZ_CARRIZO_A0 0x01
-+
-+#define STONEY_A0 0x61
-+#define CZ_UNKNOWN 0xFF
-+
-+#define ASIC_REV_IS_STONEY(rev) \
-+	((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
-+
-+/*
-+ * ASIC chip ID
-+ */
-+/* DCE80 */
-+#define DEVICE_ID_KALINDI_9834 0x9834
-+#define DEVICE_ID_TEMASH_9839 0x9839
-+#define DEVICE_ID_TEMASH_983D 0x983D
-+
-+
-+/* Asic Family IDs for different asic family. */
-+#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
-+#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
-+#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
-+#define FAMILY_CZ 135 /* Carrizo */
-+
-+#define	FAMILY_UNKNOWN 0xFF
-+
-+#endif /* __DAL_ASIC_ID_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_register_logger.h b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
-new file mode 100644
-index 0000000..176d811
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_REGISTER_LOGGER__
-+#define __DAL_REGISTER_LOGGER__
-+
-+/****************
-+ * API functions
-+ ***************/
-+
-+/* dal_reg_logger_push - begin Register Logging */
-+void dal_reg_logger_push(const char *caller_func);
-+/* dal_reg_logger_pop - stop Register Logging */
-+void dal_reg_logger_pop(void);
-+
-+
-+/* for internal use of the Logger only */
-+void dal_reg_logger_rw_count_increment(void);
-+bool dal_reg_logger_should_dump_register(void);
-+
-+#endif /* __DAL_REGISTER_LOGGER__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-new file mode 100644
-index 0000000..d3c91b9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -0,0 +1,292 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TYPES_H__
-+#define __DAL_TYPES_H__
-+
-+#include "dcs_types.h"
-+struct dal_logger;
-+
-+enum dce_version {
-+	DCE_VERSION_UNKNOWN = (-1),
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	DCE_VERSION_11_0,
-+#endif
-+	DCE_VERSION_MAX
-+};
-+
-+/*
-+ * ASIC Runtime Flags
-+ */
-+struct dal_asic_runtime_flags {
-+	union {
-+		uint32_t raw;
-+		struct {
-+			uint32_t EMULATE_REPLUG_ON_CAP_CHANGE:1;
-+			uint32_t SUPPORT_XRBIAS:1;
-+			uint32_t SKIP_POWER_DOWN_ON_RESUME:1;
-+			uint32_t FULL_DETECT_ON_RESUME:1;
-+			uint32_t GSL_FRAMELOCK:1;
-+			uint32_t NO_LOW_BPP_MODES:1;
-+			uint32_t BLOCK_ON_INITIAL_DETECTION:1;
-+			uint32_t OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT:1;
-+			uint32_t DRIVER_CONTROLLED_BRIGHTNESS:1;
-+			uint32_t MODIFIABLE_FRAME_DURATION:1;
-+			uint32_t MIRACAST_SUPPORTED:1;
-+			uint32_t CONNECTED_STANDBY_SUPPORTED:1;
-+			uint32_t GNB_WAKEUP_SUPPORTED:1;
-+		} bits;
-+	} flags;
-+};
-+
-+struct hw_asic_id {
-+	uint32_t chip_id;
-+	uint32_t chip_family;
-+	uint32_t pci_revision_id;
-+	uint32_t hw_internal_rev;
-+	uint32_t vram_type;
-+	uint32_t vram_width;
-+	uint32_t feature_flags;
-+	struct dal_asic_runtime_flags runtime_flags;
-+	uint32_t fake_paths_num;
-+	void *atombios_base_address;
-+};
-+
-+/* this is pci information. BDF stands for BUS,DEVICE,FUNCTION*/
-+
-+struct bdf_info {
-+	uint16_t BUS_NUMBER:8;
-+	uint16_t DEVICE_NUMBER:5;
-+	uint16_t FUNCTION_NUMBER:3;
-+};
-+
-+#define DAL_PARAM_INVALID_INT 0x80000000
-+
-+/* shift values for bool override parameter mask
-+ * bmask is for this struct,if we touch this feature
-+ * bval indicates every bit fields for this struct too,1 is enable this feature
-+ * amdgpu.disp_bval=1594, amdgpu.disp_bmask=1594 ,
-+ * finally will show log like this:
-+ * Overridden FEATURE_LIGHT_SLEEP is enabled now
-+ * Overridden FEATURE_USE_MAX_DISPLAY_CLK is enabled now
-+ * Overridden FEATURE_ENABLE_DFS_BYPASS is enabled now
-+ * Overridden FEATURE_POWER_GATING_PIPE_IN_TILE is enabled now
-+ * Overridden FEATURE_USE_PPLIB is enabled now
-+ * Overridden FEATURE_DISABLE_LPT_SUPPORT is enabled now
-+ * Overridden FEATURE_DUMMY_FBC_BACKEND is enabled now */
-+enum bool_param_shift {
-+	DAL_PARAM_MAXIMIZE_STUTTER_MARKS = 0,
-+	DAL_PARAM_LIGHT_SLEEP,
-+	DAL_PARAM_MAXIMIZE_URGENCY_WATERMARKS,
-+	DAL_PARAM_USE_MAX_DISPLAY_CLK,
-+	DAL_PARAM_ENABLE_DFS_BYPASS,
-+	DAL_PARAM_POWER_GATING_PIPE_IN_TILE,
-+	DAL_PARAM_POWER_GATING_LB_PORTION,
-+	DAL_PARAM_PSR_ENABLE,
-+	DAL_PARAM_VARI_BRIGHT_ENABLE,
-+	DAL_PARAM_USE_PPLIB,
-+	DAL_PARAM_DISABLE_LPT_SUPPORT,
-+	DAL_PARAM_DUMMY_FBC_BACKEND,
-+	DAL_PARAM_ENABLE_GPU_SCALING,
-+	DAL_BOOL_PARAM_MAX
-+};
-+
-+/* array index for integer override parameters*/
-+enum int_param_array_index {
-+	DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0,
-+	DAL_PARAM_DRR_SUPPORT,
-+	DAL_INT_PARAM_MAX
-+};
-+
-+struct dal_override_parameters {
-+	uint32_t bool_param_enable_mask;
-+	uint32_t bool_param_values;
-+	uint32_t int_param_values[DAL_INT_PARAM_MAX];
-+};
-+
-+
-+struct dal_init_data {
-+	struct hw_asic_id asic_id;
-+	struct view_port_alignment vp_alignment;
-+	struct bdf_info bdf_info;
-+	struct dal_override_parameters display_param;
-+	void *driver; /* ctx */
-+	void *cgs_device;
-+};
-+
-+struct dal_dc_init_data {
-+	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
-+	struct adapter_service *adapter_srv;
-+};
-+
-+struct dal_dev_c_lut {
-+	uint8_t red;
-+	uint8_t green;
-+	uint8_t blue;
-+	uint8_t reserved;
-+};
-+
-+struct dal_dev_gamma_lut {
-+	uint16_t red;
-+	uint16_t green;
-+	uint16_t blue;
-+};
-+
-+struct dc_context {
-+	struct dc *dc;
-+
-+	void *driver_context; /* e.g. amdgpu_device */
-+
-+	struct dal_logger *logger;
-+	void *cgs_device;
-+};
-+
-+/* Wireless display structs */
-+
-+union dal_remote_display_cea_mode_bitmap {
-+	struct {
-+		uint32_t CEA_640X480_60P:1;/*0*/
-+		uint32_t CEA_720X480_60P:1;/*1*/
-+		uint32_t CEA_720X480_60I:1;/*2*/
-+		uint32_t CEA_720X576_50P:1;/*3*/
-+		uint32_t CEA_720X576_50I:1;/*4*/
-+		uint32_t CEA_1280X720_30P:1;/*5*/
-+		uint32_t CEA_1280X720_60P:1;/*6*/
-+		uint32_t CEA_1920X1080_30P:1;/*7*/
-+		uint32_t CEA_1920X1080_60P:1;/*8*/
-+		uint32_t CEA_1920X1080_60I:1;/*9*/
-+		uint32_t CEA_1280X720_25P:1;/*10*/
-+		uint32_t CEA_1280X728_50P:1;/*11*/
-+		uint32_t CEA_1920X1080_25P:1;/*12*/
-+		uint32_t CEA_1920X1080_50P:1;/*13*/
-+		uint32_t CEA_1920X1080_50I:1;/*14*/
-+		uint32_t CEA_1280X1024_24P:1;/*15*/
-+		uint32_t CEA_1920X1080_24P:1;/*16*/
-+		uint32_t RESERVED:15;/*[17-31]*/
-+	} flags;
-+	uint32_t raw;
-+};
-+
-+union dal_remote_display_vesa_mode_bitmap {
-+	struct {
-+		uint32_t VESA_800X600_30P:1;/*0*/
-+		uint32_t VESA_800X600_60P:1;/*1*/
-+		uint32_t VESA_1024X768_30P:1;/*2*/
-+		uint32_t VESA_1024X768_60P:1;/*3*/
-+		uint32_t VESA_1152X864_30P:1;/*4*/
-+		uint32_t VESA_1152X864_60P:1;/*5*/
-+		uint32_t VESA_1280X768_30P:1;/*6*/
-+		uint32_t VESA_1280X768_60P:1;/*7*/
-+		uint32_t VESA_1280X800_30P:1;/*8*/
-+		uint32_t VESA_1280X800_60P:1;/*9*/
-+		uint32_t VESA_1360X768_30P:1;/*10*/
-+		uint32_t VESA_1360X768_60P:1;/*11*/
-+		uint32_t VESA_1366X768_30P:1;/*12*/
-+		uint32_t VESA_1366X768_60P:1;/*13*/
-+		uint32_t VESA_1280X1024_30P:1;/*14*/
-+		uint32_t VESA_1280X1024_60P:1;/*15*/
-+		uint32_t VESA_1400X1050_30P:1;/*16*/
-+		uint32_t VESA_1400X1050_60P:1;/*17*/
-+		uint32_t VESA_1440X900_30P:1;/*18*/
-+		uint32_t VESA_1440X900_60P:1;/*19*/
-+		uint32_t VESA_1600X900_30P:1;/*20*/
-+		uint32_t VESA_1600X900_60P:1;/*21*/
-+		uint32_t VESA_1600X1200_30P:1;/*22*/
-+		uint32_t VESA_1600X1200_60P:1;/*23*/
-+		uint32_t VESA_1680X1024_30P:1;/*24*/
-+		uint32_t VESA_1680X1024_60P:1;/*25*/
-+		uint32_t VESA_1680X1050_30P:1;/*26*/
-+		uint32_t VESA_1680X1050_60P:1;/*27*/
-+		uint32_t VESA_1920X1200_30P:1;/*28*/
-+		uint32_t VESA_1920X1200_60P:1;/*29*/
-+		uint32_t RESERVED:2;/*[30-31]*/
-+	} flags;
-+	uint32_t raw;
-+};
-+
-+union dal_remote_display_hh_mode_bitmap {
-+	struct {
-+		uint32_t HH_800X480_30P:1;/*0*/
-+		uint32_t HH_800X480_60P:1;/*1*/
-+		uint32_t HH_854X480_30P:1;/*2*/
-+		uint32_t HH_854X480_60P:1;/*3*/
-+		uint32_t HH_864X480_30P:1;/*4*/
-+		uint32_t HH_864X480_60P:1;/*5*/
-+		uint32_t HH_640X360_30P:1;/*6*/
-+		uint32_t HH_640X360_60P:1;/*7*/
-+		uint32_t HH_960X540_30P:1;/*8*/
-+		uint32_t HH_960X540_60P:1;/*9*/
-+		uint32_t HH_848X480_30P:1;/*10*/
-+		uint32_t HH_848X480_60P:1;/*11*/
-+		uint32_t RESERVED:20;/*[12-31]*/
-+	} flags;
-+	uint32_t raw;
-+};
-+
-+union dal_remote_display_stereo_3d_mode_bitmap {
-+	struct {
-+		uint32_t STEREO_1920X1080_24P_TOP_AND_BOTTOM:1;/*0*/
-+		uint32_t STEREO_1280X720_60P_TOP_AND_BOTTOM:1;/*1*/
-+		uint32_t STEREO_1280X720_50P_TOP_AND_BOTTOM:1;/*2*/
-+		uint32_t STEREO_1920X1080_24X2P_FRAME_ALTERNATE:1;/*3*/
-+		uint32_t STEREO_1280X720_60X2P_FRAME_ALTERNATE:1;/*4*/
-+		uint32_t STEREO_1280X720_30X2P_FRAME_ALTERNATE:1;/*5*/
-+		uint32_t STEREO_1280X720_50X2P_FRAME_ALTERNATE:1;/*6*/
-+		uint32_t STEREO_1280X720_25X2P_FRAME_ALTERNATE:1;/*7*/
-+		uint32_t STEREO_1920X1080_24P_FRAME_PACKING:1;/* 8*/
-+		uint32_t STEREO_1280X720_60P_FRAME_PACKING:1;/* 9*/
-+		uint32_t STEREO_1280X720_30P_FRAME_PACKING:1;/*10*/
-+		uint32_t STEREO_1280X720_50P_FRAME_PACKING:1;/*11*/
-+		uint32_t STEREO_1280X720_25P_FRAME_PACKING:1;/*12*/
-+		uint32_t RESERVED:19; /*[13-31]*/
-+	} flags;
-+	uint32_t raw;
-+};
-+
-+union dal_remote_display_audio_bitmap {
-+	struct {
-+		uint32_t LPCM_44100HZ_16BITS_2_CHANNELS:1;/*0*/
-+		uint32_t LPCM_48000HZ_16BITS_2_CHANNELS:1;/*1*/
-+		uint32_t AAC_48000HZ_16BITS_2_CHANNELS:1;/*2*/
-+		uint32_t AAC_48000HZ_16BITS_4_CHANNELS:1;/*3*/
-+		uint32_t AAC_48000HZ_16BITS_6_CHANNELS:1;/*4*/
-+		uint32_t AAC_48000HZ_16BITS_8_CHANNELS:1;/*5*/
-+		uint32_t AC3_48000HZ_16BITS_2_CHANNELS:1;/*6*/
-+		uint32_t AC3_48000HZ_16BITS_4_CHANNELS:1;/*7*/
-+		uint32_t AC3_48000HZ_16BITS_6_CHANNELS:1;/*8*/
-+		uint32_t RESERVED:23;/*[9-31]*/
-+	} flags;
-+	uint32_t raw;
-+};
-+
-+struct dal_remote_display_receiver_capability {
-+	union dal_remote_display_cea_mode_bitmap cea_mode;
-+	union dal_remote_display_vesa_mode_bitmap vesa_mode;
-+	union dal_remote_display_hh_mode_bitmap hh_mode;
-+	union dal_remote_display_stereo_3d_mode_bitmap stereo_3d_mode;
-+	union dal_remote_display_audio_bitmap audio;
-+};
-+
-+#endif /* __DAL_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h b/drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h
-new file mode 100644
-index 0000000..b7fb9ff
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h
-@@ -0,0 +1,77 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_CLOCK_GENERATOR_INTERFACE_H__
-+#define __DC_CLOCK_GENERATOR_INTERFACE_H__
-+
-+#include "grph_object_ctrl_defs.h"
-+#include "set_mode_types.h"
-+
-+/* Parameter for programming the DCCP_DISP_SLOW_SELECT*/
-+struct dccg_mapping_params {
-+	uint32_t controllers_num;
-+	enum controller_id *controllers;
-+};
-+
-+/* Parameters related to HW DeSpread of DP Reference Clock*/
-+struct dccg_dp_ref_clk_ds_params {
-+	struct {
-+		/* Flag for Enabled SS on DP Reference Clock*/
-+		bool SS_ENABLED:1;
-+		/* Flag for HW De Spread enabled
-+		 * (if enabled SS on DP Reference Clock)*/
-+		bool DS_ENABLED:1;
-+		/* Flag for HW De Spread Calculations enabled for DS_DTO_INCR
-+		 * and DS_DTO_MODULO (if 0 SW programs DS_DTO_INCR and
-+		 * DS_DTO_MODULO)*/
-+		bool DS_CALCULATIONS:1;
-+	} flags;
-+	/*DP Reference clock SS percentage
-+	 * (if enabled downspread on DP Reference Clock)*/
-+	uint32_t ss_percentage;
-+	/*DP Reference clock SS percentage Divider (1000 or 100)*/
-+	uint32_t ss_percentage_divider;
-+};
-+
-+struct dc_clock_generator;
-+
-+void dal_dc_clock_generator_destroy(struct dc_clock_generator **dc);
-+void dal_dc_clock_generator_set_display_pipe_mapping(
-+	struct dc_clock_generator *dc_clk_gen,
-+	struct dccg_mapping_params *params);
-+bool dal_dc_clock_generator_get_dp_ref_clk_ds_params(
-+	struct dc_clock_generator *dc_clk_gen,
-+	struct dccg_dp_ref_clk_ds_params *params);
-+bool dal_dc_clock_generator_enable_gtc_counter(
-+	struct dc_clock_generator *dc_clk_gen,
-+	uint32_t dprefclk);
-+void dal_dc_clock_generator_disable_gtc_counter(
-+	struct dc_clock_generator *dc_clk_gen);
-+void dal_dc_clock_generator_set_gtc_group_offset(
-+	struct dc_clock_generator *dc_clk_gen,
-+	enum gtc_group group_num,
-+	uint32_t offset);
-+
-+#endif /* __DC_CLOCK_GENERATOR_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dcs_interface.h b/drivers/gpu/drm/amd/dal/include/dcs_interface.h
-new file mode 100644
-index 0000000..b3474cf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dcs_interface.h
-@@ -0,0 +1,351 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DCS_INTERFACE_H__
-+#define __DAL_DCS_INTERFACE_H__
-+
-+#include "dcs_types.h"
-+#include "grph_object_id.h"
-+
-+struct dal_context;
-+struct dcs;
-+struct ddc_service;
-+enum ddc_transaction_type;
-+enum ddc_result;
-+struct display_sink_capability;
-+enum dc_timing_3d_format;
-+
-+struct dcs_cea_audio_mode_list;
-+struct dcs_customized_mode_list;
-+
-+struct dcs_init_data {
-+	struct dal_context *dal;
-+	struct adapter_service *as;
-+	struct timing_service *ts;
-+	enum dcs_interface_type interface_type;
-+	struct graphics_object_id grph_obj_id;
-+};
-+
-+struct dcs_cea_audio_mode_list *dal_dcs_cea_audio_mode_list_create(
-+	uint32_t list_size);
-+
-+void dal_dcs_cea_audio_mode_list_destroy(
-+	struct dcs_cea_audio_mode_list **list);
-+
-+bool dal_dcs_cea_audio_mode_list_append(
-+	struct dcs_cea_audio_mode_list *list,
-+	struct cea_audio_mode *cea_audio_mode);
-+uint32_t dal_dcs_cea_audio_mode_list_get_count(
-+	const struct dcs_cea_audio_mode_list *list);
-+void dal_dcs_cea_audio_mode_list_clear(
-+	struct dcs_cea_audio_mode_list *list);
-+
-+struct cea_audio_mode *dal_dcs_cea_audio_mode_list_at_index(
-+	const struct dcs_cea_audio_mode_list *list,
-+	uint32_t index);
-+
-+struct dcs *dal_dcs_create(const struct dcs_init_data *init_data);
-+
-+void dal_dcs_destroy(struct dcs **dcs);
-+
-+enum edid_retrieve_status dal_dcs_retrieve_raw_edid(struct dcs *dcs);
-+
-+uint32_t dal_dcs_get_edid_raw_data_size(struct dcs *dcs);
-+
-+enum edid_retrieve_status dal_dcs_override_raw_edid(
-+	struct dcs *dcs,
-+	uint32_t len,
-+	uint8_t *data);
-+
-+const uint8_t *dal_dcs_get_edid_raw_data(
-+	struct dcs *dcs,
-+	uint32_t *buff_size);
-+
-+enum edid_retrieve_status dal_dcs_update_edid_from_last_retrieved(
-+	struct dcs *dcs);
-+
-+/*Update DDC Service.  returns the old DdcService being replaced*/
-+struct ddc_service *dal_dcs_update_ddc(
-+	struct dcs *dcs,
-+	struct ddc_service *ddc);
-+
-+void dal_dcs_set_transaction_type(
-+	struct dcs *dcs,
-+	enum ddc_transaction_type type);
-+
-+/*updates the ModeTimingList of given path with
-+ModeTiming reported by this DCS*/
-+void dal_dcs_update_ts_timing_list_on_display(
-+	struct dcs *dcs,
-+	uint32_t display_index);
-+
-+/* DDC query on generic slave address*/
-+bool dal_dcs_query_ddc_data(
-+	struct dcs *dcs,
-+	uint32_t address,
-+	uint8_t *write_buf,
-+	uint32_t write_buff_size,
-+	uint8_t *read_buff,
-+	uint32_t read_buff_size);
-+
-+bool dal_dcs_get_vendor_product_id_info(
-+	struct dcs *dcs,
-+	struct vendor_product_id_info *info);
-+
-+bool dal_dcs_get_display_name(struct dcs *dcs, uint8_t *name, uint32_t size);
-+
-+bool dal_dcs_get_display_characteristics(
-+	struct dcs *dcs,
-+	struct display_characteristics *characteristics);
-+
-+bool dal_dcs_get_screen_info(
-+	struct dcs *dcs,
-+	struct edid_screen_info *info);
-+
-+enum dcs_edid_connector_type dal_dcs_get_connector_type(struct dcs *dcs);
-+
-+bool dal_dcs_get_display_pixel_encoding(
-+	struct dcs *dcs,
-+	struct display_pixel_encoding_support *pe);
-+
-+enum display_dongle_type dal_dcs_get_dongle_type(struct dcs *dcs);
-+
-+void dal_dcs_query_sink_capability(
-+	struct dcs *dcs,
-+	struct display_sink_capability *sink_cap,
-+	bool hpd_sense_bit);
-+
-+void dal_dcs_reset_sink_capability(struct dcs *dcs);
-+
-+bool dal_dcs_get_sink_capability(
-+	struct dcs *dcs,
-+	struct display_sink_capability *sink_cap);
-+
-+bool dal_dcs_emulate_sink_capability(
-+	struct dcs *dcs,
-+	struct display_sink_capability *sink_cap);
-+
-+bool dal_dcs_get_display_color_depth(
-+	struct dcs *dcs,
-+	struct display_color_depth_support *color_depth);
-+
-+bool dal_dcs_get_display_pixel_encoding(
-+	struct dcs *dcs,
-+	struct display_pixel_encoding_support *pixel_encoding);
-+
-+bool dal_dcs_get_cea861_support(
-+	struct dcs *dcs,
-+	struct cea861_support *cea861_support);
-+
-+bool dal_dcs_get_cea_vendor_specific_data_block(
-+	struct dcs *dcs,
-+	struct cea_vendor_specific_data_block *vendor_block);
-+
-+bool dal_dcs_get_cea_speaker_allocation_data_block(
-+	struct dcs *dcs,
-+	enum signal_type signal,
-+	union cea_speaker_allocation_data_block *spkr_data);
-+
-+bool dal_dcs_get_cea_colorimetry_data_block(
-+	struct dcs *dcs,
-+	struct cea_colorimetry_data_block *colorimetry_data_block);
-+
-+bool dal_dcs_get_cea_video_capability_data_block(
-+	struct dcs *dcs,
-+	union cea_video_capability_data_block *video_capability_data_block);
-+
-+uint32_t dal_dcs_get_extensions_num(struct dcs *dcs);
-+
-+const struct dcs_cea_audio_mode_list *dal_dcs_get_cea_audio_modes(
-+	struct dcs *dcs,
-+	enum signal_type signal);
-+
-+bool dal_dcs_is_audio_supported(struct dcs *dcs);
-+
-+bool dal_dcs_validate_customized_mode(
-+	struct dcs *dcs,
-+	const struct dcs_customized_mode *customized_mode);
-+
-+bool dal_dcs_add_customized_mode(
-+	struct dcs *dcs,
-+	struct dcs_customized_mode *customized_mode);
-+
-+bool dal_dcs_delete_customized_mode(struct dcs *dcs, uint32_t index);
-+
-+const struct dcs_customized_mode_list *dal_dcs_get_customized_modes(
-+	struct dcs *dcs);
-+
-+bool dal_dcs_delete_mode_timing_override(
-+	struct dcs *dcs,
-+	struct dcs_override_mode_timing *dcs_mode_timing);
-+
-+bool dal_dcs_set_mode_timing_override(
-+	struct dcs *dcs,
-+	uint32_t display_index,
-+	struct dcs_override_mode_timing *dcs_mode_timing);
-+
-+bool dal_dcs_get_timing_override_for_mode(
-+	struct dcs *dcs,
-+	uint32_t display_index,
-+	struct dc_mode_info *mode_info,
-+	struct dcs_override_mode_timing_list *dcs_mode_timing_list);
-+
-+uint32_t dal_dcs_get_num_mode_timing_overrides(struct dcs *dcs);
-+
-+bool dal_dcs_get_timing_override_list(
-+	struct dcs *dcs,
-+	uint32_t display_index,
-+	struct dcs_override_mode_timing_list *dcs_mode_timing_list,
-+	uint32_t size);
-+
-+bool dal_dcs_get_supported_force_hdtv_mode(
-+	struct dcs *dcs,
-+	union hdtv_mode_support *hdtv_mode);
-+
-+bool dal_dcs_get_user_force_hdtv_mode(
-+	struct dcs *dcs,
-+	union hdtv_mode_support *hdtv_mode);
-+
-+bool dal_dcs_set_user_force_hdtv_mode(
-+	struct dcs *dcs,
-+	const union hdtv_mode_support *hdtv_mode);
-+
-+bool dal_dcs_get_fid9204_allow_ce_mode_only_option(
-+	struct dcs *dcs,
-+	bool is_hdmi,
-+	bool *enable);
-+
-+bool dal_dcs_set_fid9204_allow_ce_mode_only_option(
-+	struct dcs *dcs,
-+	bool is_hdmi,
-+	bool enable);
-+
-+bool dal_dcs_get_panel_misc_info(
-+	struct dcs *dcs,
-+	union panel_misc_info *panel_info);
-+
-+enum ddc_result dal_dcs_dpcd_read(
-+	struct dcs *dcs,
-+	uint32_t address,
-+	uint8_t *buffer,
-+	uint32_t length);
-+
-+enum ddc_result dal_dcs_dpcd_write(
-+	struct dcs *dcs,
-+	uint32_t address,
-+	const uint8_t *buffer,
-+	uint32_t length);
-+
-+bool dal_dcs_get_range_limit(
-+	struct dcs *dcs,
-+	struct display_range_limits *limit);
-+
-+bool dal_dcs_set_range_limit_override(
-+	struct dcs *dcs,
-+	struct display_range_limits *limit);
-+
-+bool dal_dcs_get_user_select_limit(
-+	struct dcs *dcs,
-+	struct monitor_user_select_limits *limit);
-+
-+bool dal_dcs_set_user_select_limit(
-+	struct dcs *dcs,
-+	struct monitor_user_select_limits *limit);
-+
-+bool dal_dcs_get_dongle_mode_support(
-+	struct dcs *dcs,
-+	union hdtv_mode_support *hdtv_mode);
-+
-+bool dal_dcs_get_timing_limits(
-+	struct dcs *dcs,
-+	struct timing_limits *timing_limits);
-+
-+bool dal_dcs_get_drr_config(
-+	struct dcs *dcs,
-+	struct drr_config *config);
-+
-+bool dal_dcs_force_dp_audio(struct dcs *dcs, bool force_audio_on);
-+
-+bool dal_dcs_is_dp_audio_forced(struct dcs *dcs);
-+
-+const struct monitor_patch_info *dal_dcs_get_monitor_patch_info(
-+	struct dcs *dcs,
-+	enum monitor_patch_type patch_type);
-+
-+bool dal_dcs_set_monitor_patch_info(
-+	struct dcs *dcs,
-+	struct monitor_patch_info *patch_info);
-+
-+union dcs_monitor_patch_flags dal_dcs_get_monitor_patch_flags(struct dcs *dcs);
-+
-+enum  dcs_packed_pixel_format dal_dcs_get_enabled_packed_pixel_format(
-+	struct dcs *dcs);
-+
-+enum  dcs_packed_pixel_format dal_dcs_get_monitor_packed_pixel_format(
-+	struct dcs *dcs);
-+
-+bool dal_dcs_report_single_selected_timing(struct dcs *dcs);
-+
-+bool dal_dcs_can_tile_scale(struct dcs *dcs);
-+
-+void dal_dcs_set_single_selected_timing_restriction(
-+	struct dcs *dcs,
-+	bool value);
-+
-+const struct dcs_edid_supported_max_bw *dal_dcs_get_edid_supported_max_bw(
-+	struct dcs *dcs);
-+
-+bool dal_dcs_is_non_continous_frequency(struct dcs *dcs);
-+
-+struct dcs_stereo_3d_features dal_dcs_get_stereo_3d_features(
-+	struct dcs *dcs,
-+	enum dc_timing_3d_format format);
-+
-+union stereo_3d_support dal_dcs_get_stereo_3d_support(struct dcs *dcs);
-+
-+void dal_dcs_override_stereo_3d_support(
-+	struct dcs *dcs,
-+	union stereo_3d_support support);
-+
-+void dal_dcs_set_remote_display_receiver_capabilities(
-+	struct dcs *dcs,
-+	const struct dal_remote_display_receiver_capability *cap);
-+
-+void dal_dcs_clear_remote_display_receiver_capabilities(struct dcs *dcs);
-+
-+bool dal_dcs_get_display_tile_info(
-+	struct dcs *dcs,
-+	struct dcs_display_tile *display_tile,
-+	bool first_display);
-+
-+bool dal_dcs_get_container_id(struct dcs *dcs,
-+	struct dcs_container_id *container_id);
-+
-+bool dal_dcs_set_container_id(struct dcs *dcs,
-+	struct dcs_container_id *container_id);
-+
-+void dal_dcs_invalidate_container_id(struct dcs *dcs);
-+
-+union dcs_monitor_patch_flags dal_dcs_get_monitor_patch_flags(struct dcs *dcs);
-+
-+#endif /* __DAL_DCS_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dcs_types.h b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-new file mode 100644
-index 0000000..8c65057
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-@@ -0,0 +1,742 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DCS_TYPES_H__
-+#define __DAL_DCS_TYPES_H__
-+
-+#include "signal_types.h"
-+
-+#include "dc_types.h"
-+
-+#define NUM_OF_BYTE_EDID_COLOR_CHARACTERISTICS 10
-+#define MAX_NUMBER_OF_HDMI_VSDB_3D_EXTENDED_SUPPORT 21
-+#define MAX_NUMBER_OF_HDMI_VSDB_VICS 7
-+
-+struct drr_config {
-+	/* minimum frame per second for dynamic
-+	 * refresh rate feature; 0 if drr support not found*/
-+	uint32_t min_fps_in_microhz;
-+	bool force_lock_on_event;
-+	bool lock_to_master_vsync;
-+
-+	struct {
-+		uint8_t FORCED_BY_REGKEY_OR_ESCAPE:1;
-+		uint8_t FORCED_BY_VBIOS:1;
-+		uint8_t SUPPORTED_BY_EDID:1;
-+	} support_method;
-+};
-+
-+struct timing_limits {
-+	uint32_t min_pixel_clock_in_khz;
-+	uint32_t max_pixel_clock_in_khz;
-+};
-+
-+struct vendor_product_id_info {
-+	uint32_t manufacturer_id;
-+	uint32_t product_id;
-+	uint32_t serial_id;
-+	uint32_t manufacture_week;
-+	uint32_t manufacture_year;
-+};
-+
-+struct display_range_limits {
-+	uint32_t min_v_rate_hz;
-+	uint32_t max_v_rate_hz;
-+	uint32_t min_h_rate_khz;
-+	uint32_t max_h_rateIn_khz;
-+	uint32_t max_pix_clk_khz;
-+	bool use_override;
-+};
-+
-+struct monitor_user_select_limits {
-+	bool use_ati_override;
-+	uint32_t max_h_res;
-+	uint32_t max_v_res;
-+	uint32_t max_refresh_rate;
-+};
-+
-+enum edid_screen_aspect_ratio {
-+	EDID_SCREEN_AR_UNKNOWN = 0,
-+	EDID_SCREEN_AR_PROJECTOR,
-+	EDID_SCREEN_AR_16X9,
-+	EDID_SCREEN_AR_16X10,
-+	EDID_SCREEN_AR_4X3,
-+	EDID_SCREEN_AR_5X4,
-+	EDID_SCREEN_AR_9X16,
-+	EDID_SCREEN_AR_10X16,
-+	EDID_SCREEN_AR_3X4,
-+	EDID_SCREEN_AR_4X5
-+};
-+
-+struct edid_screen_info {
-+	enum edid_screen_aspect_ratio aspect_ratio;
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+struct display_characteristics {
-+	uint8_t gamma;
-+	uint8_t color_characteristics[NUM_OF_BYTE_EDID_COLOR_CHARACTERISTICS];
-+};
-+
-+union cv_smart_dongle_modes {
-+	uint8_t all;
-+	struct cv_smart_dongle_switches {
-+		uint8_t MODE_1080I:1;
-+		uint8_t MODE_720P:1;
-+		uint8_t MODE_540P:1;
-+		uint8_t MODE_480P:1;
-+		uint8_t MODE_480I:1;
-+		uint8_t MODE_16_9:1;
-+	} switches;
-+};
-+
-+struct cea_audio_mode {
-+	uint8_t format_code; /* ucData[0] [6:3]*/
-+	uint8_t channel_count; /* ucData[0] [2:0]*/
-+	uint8_t sample_rate; /* ucData[1]*/
-+	union {
-+		uint8_t sample_size; /* for LPCM*/
-+		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
-+		uint8_t max_bit_rate;
-+		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
-+	};
-+};
-+
-+union cea_speaker_allocation_data_block {
-+	struct {
-+		uint32_t FL_FR:1;
-+		uint32_t LFE:1;
-+		uint32_t FC:1;
-+		uint32_t RL_RR:1;
-+		uint32_t RC:1;
-+		uint32_t FLC_FRC:1;
-+		uint32_t RLC_RRC:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct cea_colorimetry_data_block {
-+	struct {
-+		uint32_t XV_YCC601:1;
-+		uint32_t XV_YCC709:1;
-+		uint32_t S_YCC601:1;
-+		uint32_t ADOBE_YCC601:1;
-+		uint32_t ADOBE_RGB:1;
-+
-+	} flag;
-+	struct {
-+		uint32_t MD0:1;
-+		uint32_t MD1:1;
-+		uint32_t MD2:1;
-+		uint32_t MD3:1;
-+	} metadata_flag;
-+};
-+
-+union cea_video_capability_data_block {
-+	struct {
-+		uint8_t S_CE0:1;
-+		uint8_t S_CE1:1;
-+		uint8_t S_IT0:1;
-+		uint8_t S_IT1:1;
-+		uint8_t S_PT0:1;
-+		uint8_t S_PT1:1;
-+		uint8_t QS:1;
-+		uint8_t QY:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+enum stereo_3d_multi_presence {
-+	STEREO_3D_MULTI_NOT_PRESENT = 0,
-+	STEREO_3D_MULTI_ALL_FORMATS,
-+	STEREO_3D_MULTI_MASKED_FORMATS,
-+	STEREO_3D_MULTI_RESERVED
-+};
-+
-+enum cea_hdmi_vic {
-+	CEA_HDMI_VIC_RESERVED = 0,
-+	CEA_HDMI_VIC_4KX2K_30,
-+	CEA_HDMI_VIC_4KX2K_25,
-+	CEA_HDMI_VIC_4KX2K_24,
-+	CEA_HDMI_VIC_4KX2K_24_SMPTE
-+};
-+
-+struct cea_hdmi_vsdb_extended_caps {
-+	uint32_t reserved;
-+	uint32_t image_size;
-+	enum stereo_3d_multi_presence stereo_3d_multi_present;
-+	bool stereo_3d_present;
-+	uint32_t hdmi_3d_len;
-+	uint32_t hdmi_vic_len;
-+};
-+
-+struct cea_vendor_specific_data_block {
-+
-+	uint32_t ieee_id;
-+
-+	struct commonent_phy {
-+		uint32_t PHY_ADDR_A:4;
-+		uint32_t PHY_ADDR_B:4;
-+		uint32_t PHY_ADDR_C:4;
-+		uint32_t PHY_ADDR_D:4;
-+	} commonent_phy_addr;
-+
-+	struct byte6 {
-+		uint32_t SUPPORTS_AI:1;
-+		uint32_t DC_48BIT:1;
-+		uint32_t DC_36BIT:1;
-+		uint32_t DC_30BIT:1;
-+		uint32_t DC_Y444:1;
-+		uint32_t DVI_DUAL:1;
-+		uint32_t RESERVED:2;
-+	} byte6;/* link capabilities*/
-+	bool byte6_valid;
-+
-+	uint32_t max_tmds_clk_mhz;
-+
-+	struct byte8 {
-+		uint32_t LATENCY_FIELDS_PRESENT:1;
-+		uint32_t ILATENCY_FIELDS_PRESENT:1;
-+		uint32_t HDMI_VIDEO_PRESENT:1;
-+		uint32_t RESERVED:1;
-+		uint32_t CNC3_GAME:1;
-+		uint32_t CNC2_CINEMA:1;
-+		uint32_t CNC1_PHOTO:1;
-+		uint32_t CNC0_GRAPHICS:1;
-+	} byte8;
-+	/*bit 6-7: latency flags to indicate valid latency fields*/
-+	/*bit 5: support of additional video format capabilities*/
-+	/* bit 0-3: flags indicating which content type is supported*/
-+	uint32_t video_latency;
-+	uint32_t audio_latency;
-+	uint32_t i_video_latency;
-+	uint32_t i_audio_latency;
-+
-+	struct cea_hdmi_vsdb_extended_caps hdmi_vsdb_extended_caps;
-+
-+	enum stereo_3d_multi_presence stereo_3d_multi_present;
-+
-+	struct {
-+		bool FRAME_PACKING:1;
-+		bool SIDE_BY_SIDE_HALF:1;
-+		bool TOP_AND_BOTTOM:1;
-+	} stereo_3d_all_support;
-+	uint16_t stereo_3d_mask;
-+
-+	enum cea_hdmi_vic hdmi_vic[MAX_NUMBER_OF_HDMI_VSDB_VICS];
-+	struct stereo_3d_extended_support {
-+		struct {
-+			bool FRAME_PACKING:1;
-+			bool SIDE_BY_SIDE_HALF:1;
-+			bool TOP_AND_BOTTOM:1;
-+		} format;
-+		uint32_t vic_index;
-+		uint32_t value;
-+		uint32_t size;
-+	} stereo_3d_extended_support[MAX_NUMBER_OF_HDMI_VSDB_3D_EXTENDED_SUPPORT];
-+};
-+
-+struct cea861_support {
-+
-+	uint32_t revision;
-+	union {
-+		struct {
-+			uint32_t NATIVE_COUNT:4;
-+			uint32_t BASE_AUDIO:1;
-+			uint32_t YCRCB444:1;
-+			uint32_t YCRCB422:1;
-+			uint32_t UNDER_SCAN:1;
-+		} features;
-+		uint8_t raw_features;
-+	};
-+};
-+
-+struct dcs_customized_mode {
-+	struct {
-+		uint32_t READ_ONLY:1;
-+		uint32_t ADD_BY_DRIVER:1;
-+		uint32_t INTERLACED:1;
-+		uint32_t BASE_MODE:1;
-+	} flags;
-+	struct dc_mode_info base_mode_info;
-+	struct dc_mode_info customized_mode_info;
-+};
-+
-+struct dcs_override_mode_timing {
-+	/* possible timing standards, bit vector of TimingStandard*/
-+	uint32_t possible_timing_standards;
-+	/* indicate driver default timing is used , no override*/
-+	bool use_driver_default_timing;
-+	struct dc_mode_timing mode_timing;
-+};
-+
-+struct dcs_override_mode_timing_list {
-+	uint32_t max_num_overrides;
-+	uint32_t num_overrides;
-+	struct dcs_override_mode_timing mode_timings[1];
-+};
-+
-+/* "interface type" is different from Signal Type because
-+ * an "interface type" can be driven by more than one Signal Type.
-+ * For example, INTERFACE_TYPE_DVI can be driven by
-+ * Single or Dual link DVI signal. */
-+enum dcs_interface_type {
-+	INTERFACE_TYPE_VGA = 0,
-+	INTERFACE_TYPE_DVI,
-+	INTERFACE_TYPE_CV,
-+	INTERFACE_TYPE_TV,
-+	INTERFACE_TYPE_LVDS,
-+	INTERFACE_TYPE_DP,
-+	INTERFACE_TYPE_WIRELESS,
-+	INTERFACE_TYPE_CF,
-+	INTERFACE_TYPE_EDP
-+};
-+
-+
-+union panel_misc_info {
-+	struct {
-+		uint32_t H_CUT_OFF:1;
-+		uint32_t H_SYNC_POLARITY:1;/*0=Active High, 1=Active Low*/
-+		uint32_t V_SYNC_POLARITY:1; /*0=Active High, 1=Active Low*/
-+		uint32_t V_CUT_OFF:1;
-+		uint32_t H_REPLICATION_BY_2:1;
-+		uint32_t V_REPLICATION_BY_2:1;
-+		uint32_t COMPOSITE_SYNC:1;
-+		uint32_t INTERLACE:1;
-+		uint32_t DOUBLE_CLOCK:1;
-+		uint32_t RGB888:1;
-+		uint32_t GREY_LEVEL:2;
-+		uint32_t SPATIAL:1;
-+		uint32_t TEMPORAL:1;
-+		uint32_t API_ENABLED:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+union hdtv_mode_support {
-+	struct {
-+		uint32_t HDTV_SUPPORT_480I:1;
-+		uint32_t HDTV_SUPPORT_480P:1;
-+		uint32_t HDTV_SUPPORT_576I25:1;
-+		uint32_t HDTV_SUPPORT_576P50:1;
-+		uint32_t HDTV_SUPPORT_720P:1;
-+		uint32_t HDTV_SUPPORT_720P50:1;
-+		uint32_t HDTV_SUPPORT_1080I:1;
-+		uint32_t HDTV_SUPPORT_1080I25:1;
-+		uint32_t HDTV_SUPPORT_1080P:1;
-+		uint32_t HDTV_SUPPORT_1080P50:1;
-+		uint32_t HDTV_SUPPORT_1080P24:1;
-+		uint32_t HDTV_SUPPORT_1080P25:1;
-+		uint32_t HDTV_SUPPORT_1080P30:1;
-+		uint32_t HDTV_SUPPORT_16X9:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+enum edid_retrieve_status {
-+	EDID_RETRIEVE_SUCCESS = 0,
-+	EDID_RETRIEVE_FAIL,
-+	EDID_RETRIEVE_SAME_EDID,
-+	EDID_RETRIEVE_FAIL_WITH_PREVIOUS_SUCCESS
-+};
-+
-+#define DCS_DECODE_EDID_RETRIEVE_STATUS(status) \
-+	(status == EDID_RETRIEVE_SUCCESS) ? "EDID_RETRIEVE_SUCCESS" : \
-+	(status == EDID_RETRIEVE_FAIL) ? "EDID_RETRIEVE_FAIL" : \
-+	(status == EDID_RETRIEVE_SAME_EDID) ? "EDID_RETRIEVE_SAME_EDID" : \
-+	(status == EDID_RETRIEVE_FAIL_WITH_PREVIOUS_SUCCESS) ? \
-+		"EDID_RETRIEVE_FAIL_WITH_PREVIOUS_SUCCESS" : "Unknown"
-+
-+
-+#ifndef TV_SIGNALFORMAT_DEFINED
-+#define TV_SIGNALFORMAT_DEFINED
-+enum tv_signal_format {
-+	TV_SIGNAL_FORMAT_UNKNOWN,
-+	TV_SIGNAL_FORMAT_NTSC,
-+	TV_SIGNAL_FORMAT_NTSC_J,
-+	TV_SIGNAL_FORMAT_PAL,
-+	TV_SIGNAL_FORMAT_PAL_M,
-+	TV_SIGNAL_FORMAT_PAL_CN,
-+	TV_SIGNAL_FORMAT_SECAM
-+};
-+#endif
-+
-+enum tv_signal_format_result {
-+	TV_SIGNAL_FORMAT_RESULT_OK,
-+	TV_SIGNAL_FORMAT_SET_MODE_REQ,
-+	TV_SIGNAL_FORMAT_REBOOT_REQ,
-+	TV_SIGNAL_FORMAT_ERROR
-+};
-+
-+enum pixel_encoding_mask {
-+	PIXEL_ENCODING_MASK_YCBCR444 = 0x01,
-+	PIXEL_ENCODING_MASK_YCBCR422 = 0x02,
-+	PIXEL_ENCODING_MASK_RGB = 0x04,
-+};
-+
-+struct display_pixel_encoding_support {
-+	uint32_t mask;
-+};
-+
-+enum color_depth_index {
-+	COLOR_DEPTH_INDEX_UNKNOWN,
-+	COLOR_DEPTH_INDEX_666 = 0x01,
-+	COLOR_DEPTH_INDEX_888 = 0x02,
-+	COLOR_DEPTH_INDEX_101010 = 0x04,
-+	COLOR_DEPTH_INDEX_121212 = 0x08,
-+	COLOR_DEPTH_INDEX_141414 = 0x10,
-+	COLOR_DEPTH_INDEX_161616 = 0x20,
-+	COLOR_DEPTH_INDEX_LAST = 0x40,
-+};
-+
-+struct display_color_depth_support {
-+	uint32_t mask;
-+	bool deep_color_native_res_only;
-+};
-+
-+struct display_color_and_pixel_support {
-+	struct display_color_depth_support color_depth_support;
-+	struct display_pixel_encoding_support pixel_encoding_support;
-+	bool deep_color_y444_support;
-+};
-+
-+enum dcs_packed_pixel_format {
-+	DCS_PACKED_PIXEL_FORMAT_NOT_PACKED = 0,
-+	DCS_PACKED_PIXEL_FORMAT_SPLIT_G70_B54_R70_B10 = 1,
-+	DCS_PACKED_PIXEL_FORMAT_R70_G76 = 2,
-+	DCS_PACKED_PIXEL_FORMAT_SPLIT_B70_G10_R70_G76 = 3,
-+	DCS_PACKED_PIXEL_FORMAT_G70_B54_R70_B10 = 4,
-+	DCS_PACKED_PIXEL_FORMAT_G70_B54 = 5,
-+	DCS_PACKED_PIXEL_FORMAT_B70_R30_G70_R74 = 6,
-+	DCS_PACKED_PIXEL_FORMAT_B70_G70_R70 = 7,
-+	DCS_PACKED_PIXEL_FORMAT_B70_R32_G70_R76 = 8,
-+};
-+
-+enum monitor_manufacturer_id {
-+	MONITOR_MANUFACTURER_ID_0 = 0x0000,
-+	MONITOR_MANUFACTURER_ID_1 = 0x3834,
-+	MONITOR_MANUFACTURER_ID_2 = 0x4d24,
-+	MONITOR_MANUFACTURER_ID_3 = 0x293E,
-+	MONITOR_MANUFACTURER_ID_4 = 0x635a,
-+	MONITOR_MANUFACTURER_ID_5 = 0x1006,
-+	MONITOR_MANUFACTURER_ID_6 = 0xc32a,
-+	MONITOR_MANUFACTURER_ID_7 = 0x4d24,
-+	MONITOR_MANUFACTURER_ID_8 = 0x110e,
-+	MONITOR_MANUFACTURER_ID_9 = 0xaf0d,
-+	MONITOR_MANUFACTURER_ID_10 = 0x6D1E,
-+	MONITOR_MANUFACTURER_ID_11 = 0xA338,
-+	MONITOR_MANUFACTURER_ID_12 = 0xC315,
-+	MONITOR_MANUFACTURER_ID_13 = 0xD94D,
-+	MONITOR_MANUFACTURER_ID_14 = 0x104D,
-+	MONITOR_MANUFACTURER_ID_15 = 0x855C,
-+	MONITOR_MANUFACTURER_ID_16 = 0x4251,
-+	MONITOR_MANUFACTURER_ID_17 = 0xA934,
-+	MONITOR_MANUFACTURER_ID_18 = 0x0C41,
-+	/* TODO: Update when EDID is available */
-+	MONITOR_MANUFACTURER_ID_19 = 0xDEAD,
-+	MONITOR_MANUFACTURER_ID_20 = 0x6904,
-+	MONITOR_MANUFACTURER_ID_21 = 0xAC10,
-+	MONITOR_MANUFACTURER_ID_22 = 0x2D4C,
-+	MONITOR_MANUFACTURER_ID_23 = 0x144E,
-+	MONITOR_MANUFACTURER_ID_24 = 0x6c50,
-+	MONITOR_MANUFACTURER_ID_26 = 0x0c41,
-+	MONITOR_MANUFACTURER_ID_27 = 0x143E,
-+	MONITOR_MANUFACTURER_ID_25 = 0xffff,
-+	MONITOR_MANUFACTURER_ID_28 = 0x3421,
-+	MONITOR_MANUFACTURER_ID_29 = 0x2D19,
-+	MONITOR_MANUFACTURER_ID_30 = 0x8B52,
-+	MONITOR_MANUFACTURER_ID_31 = 0x7204,
-+	MONITOR_MANUFACTURER_ID_32 = 0xF022,
-+	MONITOR_MANUFACTURER_ID_33 = 0x0E11,
-+	MONITOR_MANUFACTURER_ID_34 = 0xD241,
-+	MONITOR_MANUFACTURER_ID_35 = 0xAE30,
-+	MONITOR_MANUFACTURER_ID_36 = 0xF91E,
-+	MONITOR_MANUFACTURER_ID_37 = 0xAB4C,
-+};
-+
-+enum monitor_product_id {
-+	MONITOR_PRODUCT_ID_0 = 0x0000,
-+	MONITOR_PRODUCT_ID_1 = 0x0BCC,
-+	MONITOR_PRODUCT_ID_2 = 0x251F,
-+	MONITOR_PRODUCT_ID_3 = 0x5241,
-+	MONITOR_PRODUCT_ID_4 = 0x6919,
-+	MONITOR_PRODUCT_ID_5 = 0xee18,
-+	MONITOR_PRODUCT_ID_6 = 0xf008,
-+	MONITOR_PRODUCT_ID_7 = 0x2f0c,
-+	MONITOR_PRODUCT_ID_7_2 = 0x3411,
-+	MONITOR_PRODUCT_ID_9 = 0x4208,
-+	MONITOR_PRODUCT_ID_10 = 0xE51D,
-+	MONITOR_PRODUCT_ID_11 = 0x7E22,
-+	MONITOR_PRODUCT_ID_12 = 0x0E23,
-+	MONITOR_PRODUCT_ID_13 = 0x9d08,
-+	MONITOR_PRODUCT_ID_14 = 0x9236,
-+	MONITOR_PRODUCT_ID_15 = 0x9227,
-+	MONITOR_PRODUCT_ID_16 = 0x0220,
-+	MONITOR_PRODUCT_ID_17 = 0x4920,
-+	MONITOR_PRODUCT_ID_18 = 0x251f,
-+	MONITOR_PRODUCT_ID_19 = 0x1395,
-+	MONITOR_PRODUCT_ID_20 = 0xc04e,
-+	MONITOR_PRODUCT_ID_21 = 0x5787,
-+	MONITOR_PRODUCT_ID_22 = 0x5A71,
-+	MONITOR_PRODUCT_ID_23 = 0x6622,
-+	MONITOR_PRODUCT_ID_24 = 0x20C1,
-+	MONITOR_PRODUCT_ID_25 = 0x2110,
-+	MONITOR_PRODUCT_ID_26 = 0x2006,
-+	MONITOR_PRODUCT_ID_27 = 0x1827,
-+	MONITOR_PRODUCT_ID_28 = 0x0EA0,
-+	MONITOR_PRODUCT_ID_29 = 0x03D0,
-+	MONITOR_PRODUCT_ID_30 = 0x01D2,
-+	MONITOR_PRODUCT_ID_31 = 0x2801,
-+	MONITOR_PRODUCT_ID_32 = 0x0FB3,
-+	MONITOR_PRODUCT_ID_33 = 0x0FB1,
-+	MONITOR_PRODUCT_ID_34 = 0xA045,
-+	MONITOR_PRODUCT_ID_35 = 0x0001,
-+	MONITOR_PRODUCT_ID_36 = 0xA296,
-+	MONITOR_PRODUCT_ID_38 = 0x21DC,
-+	MONITOR_PRODUCT_ID_37 = 0x21EA,
-+	MONITOR_PRODUCT_ID_39 = 0x4093,
-+	MONITOR_PRODUCT_ID_40 = 0x4094,
-+	MONITOR_PRODUCT_ID_41 = 0x4094,
-+	MONITOR_PRODUCT_ID_42 = 0x32A2,
-+	MONITOR_PRODUCT_ID_43 = 0xE009,
-+	MONITOR_PRODUCT_ID_44 = 0xA010,
-+	MONITOR_PRODUCT_ID_45 = 0x405C,
-+	MONITOR_PRODUCT_ID_46 = 0xF017,
-+	MONITOR_PRODUCT_ID_47 = 0xD026,
-+	MONITOR_PRODUCT_ID_48 = 0x4036,
-+	MONITOR_PRODUCT_ID_49 = 0x4065,
-+	MONITOR_PRODUCT_ID_50 = 0xA02A,
-+	MONITOR_PRODUCT_ID_51 = 0xA02C,
-+	MONITOR_PRODUCT_ID_46_HDMI = 0xF016,
-+	MONITOR_PRODUCT_ID_53 = 0xF048,
-+	MONITOR_PRODUCT_ID_54 = 0xA0A2,
-+	MONITOR_PRODUCT_ID_55 = 0x4083,
-+	MONITOR_PRODUCT_ID_56 = 0x0E74,
-+	MONITOR_PRODUCT_ID_57 = 0x2771,
-+	MONITOR_PRODUCT_ID_58 = 0x0814,
-+	MONITOR_PRODUCT_ID_59 = 0xffff,
-+	MONITOR_PRODUCT_ID_60 = 0x3339,
-+	MONITOR_PRODUCT_ID_61 = 0x01F5,
-+	MONITOR_PRODUCT_ID_62 = 0x02A5,
-+	MONITOR_PRODUCT_ID_63 = 0x06AC,
-+	MONITOR_PRODUCT_ID_64 = 0x04D5,
-+	MONITOR_PRODUCT_ID_65 = 0x079D,
-+	MONITOR_PRODUCT_ID_66 = 0x079F,
-+	MONITOR_PRODUCT_ID_67 = 0x0797,
-+	MONITOR_PRODUCT_ID_68 = 0x0B80,
-+	MONITOR_PRODUCT_ID_69 = 0x7D06,
-+	MONITOR_PRODUCT_ID_70 = 0x0131,
-+	MONITOR_PRODUCT_ID_71 = 0x8545,
-+	MONITOR_PRODUCT_ID_72 = 0x0002,
-+	MONITOR_PRODUCT_ID_73 = 0x0125,
-+	MONITOR_PRODUCT_ID_74 = 0x00D0,
-+	MONITOR_PRODUCT_ID_75 = 0x26F7,
-+	MONITOR_PRODUCT_ID_76 = 0x26F9,
-+	MONITOR_PRODUCT_ID_77 = 0x2807,
-+	MONITOR_PRODUCT_ID_78 = 0x26F3,
-+	MONITOR_PRODUCT_ID_79 = 0x2676,
-+	MONITOR_PRODUCT_ID_80 = 0x0A72,
-+	MONITOR_PRODUCT_ID_81 = 0x2693,
-+	MONITOR_PRODUCT_ID_82 = 0x2615,
-+	MONITOR_PRODUCT_ID_83 = 0x2613,
-+	MONITOR_PRODUCT_ID_84 = 0x262D,
-+	MONITOR_PRODUCT_ID_85 = 0x264B,
-+	MONITOR_PRODUCT_ID_86 = 0x2869,
-+	MONITOR_PRODUCT_ID_87 = 0x286C,
-+	MONITOR_PRODUCT_ID_88 = 0x288F,
-+	MONITOR_PRODUCT_ID_89 = 0x2954,
-+	MONITOR_PRODUCT_ID_90 = 0x6522,
-+	MONITOR_PRODUCT_ID_91 = 0x0FAE,
-+	MONITOR_PRODUCT_ID_92 = 0x0A0C,
-+	MONITOR_PRODUCT_ID_93 = 0x00BF,
-+	MONITOR_PRODUCT_ID_94 = 0x0,
-+};
-+
-+enum monitor_patch_type {
-+	MONITOR_PATCH_TYPE_NONE,
-+	MONITOR_PATCH_TYPE_ERROR_CHECKSUM,
-+	MONITOR_PATCH_TYPE_HDTV_WITH_PURE_DFP_EDID,
-+	MONITOR_PATCH_TYPE_DO_NOT_USE_DETAILED_TIMING,
-+	MONITOR_PATCH_TYPE_DO_NOT_USE_RANGE_LIMITATION,
-+	MONITOR_PATCH_TYPE_EDID_EXTENTION_ERROR_CHECK_SUM,
-+	MONITOR_PATCH_TYPE_TURN_OFF_DISPLAY_BEFORE_MODE_CHANGE,
-+	MONITOR_PATCH_TYPE_RESTRICT_VESA_MODE_TIMING,
-+	MONITOR_PATCH_TYPE_DO_NOT_USE_EDID_MAX_PIX_CLK,
-+	MONITOR_PATCH_TYPE_VENDOR_0,
-+	MONITOR_PATCH_TYPE_RANDOM_CRT,
-+	MONITOR_PATCH_TYPE_VENDOR_1,
-+	MONITOR_PATCH_TYPE_LIMIT_PANEL_SUPPORT_RGB_ONLY,
-+	MONITOR_PATCH_TYPE_PACKED_PIXEL_FORMAT,
-+	MONITOR_PATCH_TYPE_LARGE_PANEL,
-+	MONITOR_PATCH_TYPE_STEREO_SUPPORT,
-+	/* 0 (default) - mean patch will not be applied, however it can be
-+	 * explicitly set to 1
-+	 */
-+	MONITOR_PATCH_TYPE_DUAL_EDID_PANEL,
-+	MONITOR_PATCH_TYPE_IGNORE_19X12_STD_TIMING,
-+	MONITOR_PATCH_TYPE_MULTIPLE_PACKED_TYPE,
-+	MONITOR_PATCH_TYPE_RESET_TX_ON_DISPLAY_POWER_ON,
-+	MONITOR_PATCH_TYPE_VENDOR_2,
-+	MONITOR_PATCH_TYPE_RESTRICT_PROT_DUAL_LINK_DVI,
-+	MONITOR_PATCH_TYPE_FORCE_LINK_RATE,
-+	MONITOR_PATCH_TYPE_DELAY_AFTER_DP_RECEIVER_POWER_UP,
-+	MONITOR_PATCH_TYPE_KEEP_DP_RECEIVER_POWERED,
-+	MONITOR_PATCH_TYPE_DELAY_BEFORE_READ_EDID,
-+	MONITOR_PATCH_TYPE_DELAY_AFTER_PIXEL_FORMAT_CHANGE,
-+	MONITOR_PATCH_TYPE_INCREASE_DEFER_WRITE_RETRY_I2C_OVER_AUX,
-+	MONITOR_PATCH_TYPE_NO_DEFAULT_TIMINGS,
-+	MONITOR_PATCH_TYPE_ADD_CEA861_DETAILED_TIMING_VIC16,
-+	MONITOR_PATCH_TYPE_ADD_CEA861_DETAILED_TIMING_VIC31,
-+	MONITOR_PATCH_TYPE_DELAY_BEFORE_UNMUTE,
-+	MONITOR_PATCH_TYPE_RETRY_LINK_TRAINING_ON_FAILURE,
-+	MONITOR_PATCH_TYPE_ALLOW_AUX_WHEN_HPD_LOW,
-+	MONITOR_PATCH_TYPE_TILED_DISPLAY,
-+	MONITOR_PATCH_TYPE_DISABLE_PSR_ENTRY_ABORT,
-+	MONITOR_PATCH_TYPE_EDID_EXTENTION_ERROR_CHECKSUM,
-+	MONITOR_PATCH_TYPE_ALLOW_ONLY_CE_MODE,
-+	MONITOR_PATCH_TYPE_VID_STREAM_DIFFER_TO_SYNC,
-+	MONITOR_PATCH_TYPE_EXTRA_DELAY_ON_DISCONNECT,
-+	MONITOR_PATCH_TYPE_DELAY_AFTER_DISABLE_BACKLIGHT_DFS_BYPASS,
-+	MONITOR_PATCH_TYPE_SINGLE_MODE_PACKED_PIXEL
-+};
-+
-+/* Single entry in the monitor table */
-+struct monitor_patch_info {
-+	enum monitor_manufacturer_id manufacturer_id;
-+	enum monitor_product_id product_id;
-+	enum monitor_patch_type type;
-+	uint32_t param;
-+};
-+
-+union dcs_monitor_patch_flags {
-+        struct {
-+                bool ERROR_CHECKSUM:1;
-+                bool HDTV_WITH_PURE_DFP_EDID:1;
-+                bool DO_NOT_USE_DETAILED_TIMING:1;
-+                bool DO_NOT_USE_RANGE_LIMITATION:1;
-+                bool EDID_EXTENTION_ERROR_CHECKSUM:1;
-+                bool TURN_OFF_DISPLAY_BEFORE_MODE_CHANGE:1;
-+                bool RESTRICT_VESA_MODE_TIMING:1;
-+                bool DO_NOT_USE_EDID_MAX_PIX_CLK:1;
-+                bool VENDOR_0:1;
-+                bool RANDOM_CRT:1;/* 10 bits used including this one-*/
-+                bool VENDOR_1:1;
-+                bool LIMIT_PANEL_SUPPORT_RGB_ONLY:1;
-+                bool PACKED_PIXEL_FORMAT:1;
-+                bool LARGE_PANEL:1;
-+                bool STEREO_SUPPORT:1;
-+                bool DUAL_EDID_PANEL:1;
-+                bool IGNORE_19X12_STD_TIMING:1;
-+                bool MULTIPLE_PACKED_TYPE:1;
-+                bool RESET_TX_ON_DISPLAY_POWER_ON:1;
-+                bool ALLOW_ONLY_CE_MODE:1;/* 20 bits used including this one*/
-+                bool RESTRICT_PROT_DUAL_LINK_DVI:1;
-+                bool FORCE_LINK_RATE:1;
-+                bool DELAY_AFTER_DP_RECEIVER_POWER_UP:1;
-+                bool KEEP_DP_RECEIVER_POWERED:1;
-+                bool DELAY_BEFORE_READ_EDID:1;
-+                bool DELAY_AFTER_PIXEL_FORMAT_CHANGE:1;
-+                bool INCREASE_DEFER_WRITE_RETRY_I2C_OVER_AUX:1;
-+                bool NO_DEFAULT_TIMINGS:1;
-+                bool ADD_CEA861_DETAILED_TIMING_VIC16:1;
-+                bool ADD_CEA861_DETAILED_TIMING_VIC31:1; /* 30 bits*/
-+                bool DELAY_BEFORE_UNMUTE:1;
-+                bool RETRY_LINK_TRAINING_ON_FAILURE:1;
-+                bool ALLOW_AUX_WHEN_HPD_LOW:1;
-+                bool TILED_DISPLAY:1;
-+                bool DISABLE_PSR_ENTRY_ABORT:1;
-+                bool INTERMITTENT_EDID_ERROR:1;/* 36 bits total*/
-+                bool VID_STREAM_DIFFER_TO_SYNC:1;/* 37 bits total*/
-+                bool EXTRA_DELAY_ON_DISCONNECT:1;/* 38 bits total*/
-+                bool DELAY_AFTER_DISABLE_BACKLIGHT_DFS_BYPASS:1;/* 39 bits total*/
-+        } flags;
-+        uint64_t raw;
-+};
-+
-+struct dcs_edid_supported_max_bw {
-+	uint32_t pix_clock_khz;
-+	uint32_t bits_per_pixel;
-+};
-+
-+struct dcs_stereo_3d_features {
-+	struct {
-+/* 3D Format supported by monitor (implies supported by driver)*/
-+		uint32_t SUPPORTED:1;
-+/* 3D Format supported on all timings
-+(no need to check every timing for 3D support)*/
-+		uint32_t ALL_TIMINGS:1;
-+/* 3D Format supported in clone mode*/
-+		uint32_t CLONE_MODE:1;
-+/* Scaling allowed when driving 3D Format*/
-+		uint32_t SCALING:1;
-+/* Left and right images packed by SW within single frame*/
-+		uint32_t SINGLE_FRAME_SW_PACKED:1;
-+	} flags;
-+};
-+
-+struct dcs_container_id {
-+	/*128bit GUID in binary form*/
-+	uint8_t guid[16];
-+	/* 8 byte port ID -> ELD.PortID*/
-+	uint32_t port_id[2];
-+	/* 2 byte manufacturer name -> ELD.ManufacturerName*/
-+	uint16_t manufacturer_name;
-+	/* 2 byte product code -> ELD.ProductCode*/
-+	uint16_t product_code;
-+};
-+
-+struct dcs_display_tile {
-+/*unique Id of Tiled Display. 0 - means display is not part in Tiled Display*/
-+	uint64_t id;
-+	uint32_t rows;/* size of Tiled Display in tiles*/
-+	uint32_t cols;/* size of Tiled Display in tiles*/
-+	uint32_t width;/* size of current Tile in pixels*/
-+	uint32_t height;/* size of current Tile in pixels*/
-+	uint32_t row;/* location of current Tile*/
-+	uint32_t col;/* location of current Tile*/
-+	struct {
-+		/*in pixels*/
-+		uint32_t left;
-+		uint32_t right;
-+		uint32_t top;
-+		uint32_t bottom;
-+	} bezel;/* bezel information of current tile*/
-+
-+	struct {
-+		uint32_t SEPARATE_ENCLOSURE:1;
-+		uint32_t BEZEL_INFO_PRESENT:1;
-+		uint32_t CAN_SCALE:1;
-+	} flags;
-+
-+	struct {
-+		uint32_t manufacturer_id;
-+		uint32_t product_id;
-+		uint32_t serial_id;
-+	} topology_id;
-+};
-+
-+#endif /* __DAL_DCS_TYPES_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_interface.h b/drivers/gpu/drm/amd/dal/include/ddc_interface.h
-new file mode 100644
-index 0000000..22fd31f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_interface.h
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DDC_INTERFACE_H__
-+#define __DAL_DDC_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+
-+struct ddc;
-+
-+enum gpio_result dal_ddc_open(
-+	struct ddc *ddc,
-+	enum gpio_mode mode,
-+	enum gpio_ddc_config_type config_type);
-+
-+enum gpio_result dal_ddc_get_clock(
-+	const struct ddc *ddc,
-+	uint32_t *value);
-+
-+enum gpio_result dal_ddc_set_clock(
-+	const struct ddc *ddc,
-+	uint32_t value);
-+
-+enum gpio_result dal_ddc_get_data(
-+	const struct ddc *ddc,
-+	uint32_t *value);
-+
-+enum gpio_result dal_ddc_set_data(
-+	const struct ddc *ddc,
-+	uint32_t value);
-+
-+enum gpio_result dal_ddc_change_mode(
-+	struct ddc *ddc,
-+	enum gpio_mode mode);
-+
-+bool dal_ddc_is_hw_supported(
-+	const struct ddc *ddc);
-+
-+enum gpio_ddc_line dal_ddc_get_line(
-+	const struct ddc *ddc);
-+
-+bool dal_ddc_check_line_aborted(
-+	const struct ddc *ddc);
-+
-+enum gpio_result dal_ddc_set_config(
-+	struct ddc *ddc,
-+	enum gpio_ddc_config_type config_type);
-+
-+void dal_ddc_close(
-+	struct ddc *ddc);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_interface.h b/drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
-new file mode 100644
-index 0000000..ca3e6ce
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
-@@ -0,0 +1,100 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DDC_SERVICE_INTERFACE_H__
-+#define __DAL_DDC_SERVICE_INTERFACE_H__
-+
-+#include "ddc_service_types.h"
-+
-+struct ddc_service;
-+struct adapter_service;
-+struct graphics_object_id;
-+enum ddc_result;
-+struct av_sync_data;
-+struct dp_receiver_id_info;
-+
-+struct ddc_service_init_data {
-+	struct adapter_service *as;
-+	struct graphics_object_id id;
-+	struct dc_context *ctx;
-+};
-+struct ddc_service *dal_ddc_service_create(
-+	struct ddc_service_init_data *ddc_init_data);
-+
-+void dal_ddc_service_destroy(struct ddc_service **ddc);
-+
-+enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
-+
-+void dal_ddc_service_set_transaction_type(
-+	struct ddc_service *ddc,
-+	enum ddc_transaction_type type);
-+
-+bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
-+
-+uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc);
-+
-+uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc);
-+
-+void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf);
-+
-+void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+	struct ddc_service *ddc,
-+	struct display_sink_capability *sink_cap);
-+
-+bool dal_ddc_service_query_ddc_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *write_buf,
-+	uint32_t write_size,
-+	uint8_t *read_buf,
-+	uint32_t read_size);
-+
-+bool dal_ddc_service_get_dp_receiver_id_info(
-+	struct ddc_service *ddc,
-+	struct dp_receiver_id_info *info);
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t len);
-+
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t len);
-+
-+void dal_ddc_service_write_scdc_data(
-+	struct ddc_service *ddc_service,
-+	uint32_t pix_clk,
-+	bool lte_340_scramble);
-+
-+void dal_ddc_service_read_scdc_data(
-+	struct ddc_service *ddc_service);
-+
-+void ddc_service_set_dongle_type(struct ddc_service *ddc,
-+		enum display_dongle_type dongle_type);
-+
-+#endif /* __DAL_DDC_SERVICE_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-new file mode 100644
-index 0000000..47ad2ed
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-@@ -0,0 +1,220 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DDC_SERVICE_TYPES_H__
-+#define __DAL_DDC_SERVICE_TYPES_H__
-+
-+#include "include/hw_sequencer_types.h"
-+
-+#define DP_BRANCH_DEVICE_ID_1 0x0010FA
-+#define DP_BRANCH_DEVICE_ID_2 0x0022B9
-+#define DP_SINK_DEVICE_ID_1 0x4CE000
-+#define DP_BRANCH_DEVICE_ID_3 0x00001A
-+#define DP_BRANCH_DEVICE_ID_4 0x0080e1
-+#define DP_BRANCH_DEVICE_ID_5 0x006037
-+#define DP_SINK_DEVICE_ID_2 0x001CF8
-+
-+
-+enum ddc_result {
-+	DDC_RESULT_UNKNOWN = 0,
-+	DDC_RESULT_SUCESSFULL,
-+	DDC_RESULT_FAILED_CHANNEL_BUSY,
-+	DDC_RESULT_FAILED_TIMEOUT,
-+	DDC_RESULT_FAILED_PROTOCOL_ERROR,
-+	DDC_RESULT_FAILED_NACK,
-+	DDC_RESULT_FAILED_INCOMPLETE,
-+	DDC_RESULT_FAILED_OPERATION,
-+	DDC_RESULT_FAILED_INVALID_OPERATION,
-+	DDC_RESULT_FAILED_BUFFER_OVERFLOW
-+};
-+
-+enum ddc_service_type {
-+	DDC_SERVICE_TYPE_CONNECTOR,
-+	DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
-+};
-+
-+enum ddc_transaction_type {
-+	DDC_TRANSACTION_TYPE_NONE = 0,
-+	DDC_TRANSACTION_TYPE_I2C,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
-+};
-+
-+enum display_dongle_type {
-+	DISPLAY_DONGLE_NONE = 0,
-+	/* Active converter types*/
-+	DISPLAY_DONGLE_DP_VGA_CONVERTER,
-+	DISPLAY_DONGLE_DP_DVI_CONVERTER,
-+	DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
-+	DISPLAY_DONGLE_DP_DVI_DONGLE,
-+	DISPLAY_DONGLE_DP_HDMI_DONGLE,
-+	/* Other types of dongle*/
-+	DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
-+};
-+
-+enum dcs_dpcd_revision {
-+	DCS_DPCD_REV_10 = 0x10,
-+	DCS_DPCD_REV_11 = 0x11,
-+	DCS_DPCD_REV_12 = 0x12
-+};
-+
-+/**
-+ * display sink capability
-+ */
-+struct display_sink_capability {
-+	/* dongle type (DP converter, CV smart dongle) */
-+	enum display_dongle_type dongle_type;
-+
-+	/**********************************************************
-+	 capabilities going INTO SINK DEVICE (stream capabilities)
-+	 **********************************************************/
-+	/* Dongle's downstream count. */
-+	uint32_t downstrm_sink_count;
-+	/* Is dongle's downstream count info field (downstrm_sink_count)
-+	 * valid. */
-+	bool downstrm_sink_count_valid;
-+
-+	/* Maximum additional audio delay in microsecond (us) */
-+	uint32_t additional_audio_delay;
-+	/* Audio latency value in microsecond (us) */
-+	uint32_t audio_latency;
-+	/* Interlace video latency value in microsecond (us) */
-+	uint32_t video_latency_interlace;
-+	/* Progressive video latency value in microsecond (us) */
-+	uint32_t video_latency_progressive;
-+	/* Dongle caps: Maximum pixel clock supported over dongle for HDMI */
-+	uint32_t max_hdmi_pixel_clock;
-+	/* Dongle caps: Maximum deep color supported over dongle for HDMI */
-+	enum dc_color_depth max_hdmi_deep_color;
-+
-+	/************************************************************
-+	 capabilities going OUT OF SOURCE DEVICE (link capabilities)
-+	 ************************************************************/
-+	/* support for Spread Spectrum(SS) */
-+	bool ss_supported;
-+	/* DP link settings (laneCount, linkRate, Spread) */
-+	uint32_t dp_link_lane_count;
-+	uint32_t dp_link_rate;
-+	uint32_t dp_link_spead;
-+
-+	enum dcs_dpcd_revision dpcd_revision;
-+	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
-+	bool is_dp_hdmi_s3d_converter;
-+	/* to check if we have queried the display capability
-+	 * for eDP panel already. */
-+	bool is_edp_sink_cap_valid;
-+};
-+
-+struct dp_receiver_id_info {
-+	uint32_t dpcd_rev;
-+	uint32_t sink_id;
-+	int8_t sink_id_str[6];
-+	int8_t sink_hw_revision;
-+	int8_t sink_fw_revision[2];
-+	uint32_t branch_id;
-+	int8_t branch_name[6];
-+	enum display_dongle_type dongle_type;
-+};
-+
-+struct av_sync_data {
-+	uint8_t av_granularity;/* DPCD 00023h */
-+	uint8_t aud_dec_lat1;/* DPCD 00024h */
-+	uint8_t aud_dec_lat2;/* DPCD 00025h */
-+	uint8_t aud_pp_lat1;/* DPCD 00026h */
-+	uint8_t aud_pp_lat2;/* DPCD 00027h */
-+	uint8_t vid_inter_lat;/* DPCD 00028h */
-+	uint8_t vid_prog_lat;/* DPCD 00029h */
-+	uint8_t aud_del_ins1;/* DPCD 0002Bh */
-+	uint8_t aud_del_ins2;/* DPCD 0002Ch */
-+	uint8_t aud_del_ins3;/* DPCD 0002Dh */
-+};
-+
-+/** EDID retrieval related constants, also used by MstMgr **/
-+
-+#define DDC_EDID_SEGMENT_SIZE 256
-+#define DDC_EDID_BLOCK_SIZE 128
-+#define DDC_EDID_BLOCKS_PER_SEGMENT \
-+	(DDC_EDID_SEGMENT_SIZE / DDC_EDID_BLOCK_SIZE)
-+
-+#define DDC_EDID_EXT_COUNT_OFFSET 0x7E
-+
-+#define DDC_EDID_ADDRESS_START 0x50
-+#define DDC_EDID_ADDRESS_END 0x52
-+#define DDC_EDID_SEGMENT_ADDRESS 0x30
-+
-+/* signatures for Edid 1x */
-+#define DDC_EDID1X_VENDORID_SIGNATURE_OFFSET 8
-+#define DDC_EDID1X_VENDORID_SIGNATURE_LEN 4
-+#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_OFFSET 126
-+#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_LEN 2
-+#define DDC_EDID1X_CHECKSUM_OFFSET 127
-+/* signatures for Edid 20*/
-+#define DDC_EDID_20_SIGNATURE_OFFSET 0
-+#define DDC_EDID_20_SIGNATURE 0x20
-+
-+#define DDC_EDID20_VENDORID_SIGNATURE_OFFSET 1
-+#define DDC_EDID20_VENDORID_SIGNATURE_LEN 4
-+#define DDC_EDID20_CHECKSUM_OFFSET 255
-+#define DDC_EDID20_CHECKSUM_LEN 1
-+
-+/*DP to VGA converter*/
-+static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa";
-+/*DP to Dual link DVI converter*/
-+static const uint8_t DP_DVI_CONVERTER_ID_1[] = "m2DVIa";
-+/*Travis*/
-+static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
-+/*Nutmeg*/
-+static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
-+/*DP to VGA converter*/
-+static const uint8_t DP_VGA_CONVERTER_ID_4[] = "DpVga";
-+/*DP to Dual link DVI converter*/
-+static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
-+/*DP to Dual link DVI converter 2*/
-+static const uint8_t DP_DVI_CONVERTER_ID_42[] = "v2DVIa";
-+
-+static const uint8_t DP_SINK_DEV_STRING_ID2_REV0[] = "\0\0\0\0\0\0";
-+
-+/* Identifies second generation PSR TCON from Parade: Device ID string:
-+ * yy-xx-**-**-**-**
-+ */
-+/* xx - Hw ID high byte */
-+static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_HIGH_BYTE =
-+	0x06;
-+
-+/* yy - HW ID low byte, the same silicon has several package/feature flavors */
-+static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE1 =
-+	0x61;
-+static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE2 =
-+	0x62;
-+static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE3 =
-+	0x63;
-+static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE4 =
-+	0x72;
-+static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE5 =
-+	0x73;
-+
-+#endif /* __DAL_DDC_SERVICE_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h b/drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
-new file mode 100644
-index 0000000..35a5695
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DEFAULT_MODE_LIST_INTERFACE_H__
-+#define __DAL_DEFAULT_MODE_LIST_INTERFACE_H__
-+
-+struct default_mode_list;
-+
-+uint32_t dal_default_mode_list_get_count(const struct default_mode_list *dml);
-+
-+struct dc_mode_info *dal_default_mode_list_get_mode_info_at_index(
-+		const struct default_mode_list *dml,
-+		uint32_t index);
-+
-+#endif /*__DAL_DEFAULT_MODE_LIST_INTERFACE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-new file mode 100644
-index 0000000..2f48b8a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -0,0 +1,189 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DISPLAY_CLOCK_INTERFACE_H__
-+#define __DISPLAY_CLOCK_INTERFACE_H__
-+
-+#include "hw_sequencer_types.h"
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+#include "scaler_types.h"
-+
-+/* Timing related information*/
-+struct dc_timing_params {
-+	uint32_t INTERLACED:1;
-+	uint32_t HCOUNT_BY_TWO:1;
-+	uint32_t PIXEL_REPETITION:4; /*< values 1 to 10 supported*/
-+	uint32_t PREFETCH:1;
-+
-+	uint32_t h_total;
-+	uint32_t h_addressable;
-+	uint32_t h_sync_width;
-+};
-+
-+/* Scaling related information*/
-+struct dc_scaling_params {
-+	uint32_t h_overscan_right;
-+	uint32_t h_overscan_left;
-+	uint32_t h_taps;
-+	uint32_t v_taps;
-+};
-+
-+/*Display Request Mode (1 and 2 valid when scaler is OFF)*/
-+enum display_request_mode {
-+	REQUEST_ONLY_AT_EVERY_READ_POINTER_INCREMENT = 0,
-+	REQUEST_WAITING_FOR_THE_FIRST_READ_POINTER_ONLY,
-+	REQUEST_WITHOUT_WAITING_FOR_READ_POINTER
-+};
-+
-+/* FBC minimum CompressionRatio*/
-+enum fbc_compression_ratio {
-+	FBC_COMPRESSION_NOT_USED = 0,
-+	FBC_MINIMUM_COMPRESSION_RATIO_1 = 1,
-+	FBC_MINIMUM_COMPRESSION_RATIO_2 = 2,
-+	FBC_MINIMUM_COMPRESSION_RATIO_4 = 4,
-+	FBC_MINIMUM_COMPRESSION_RATIO_8 = 8
-+};
-+
-+/* VScalerEfficiency */
-+enum v_scaler_efficiency {
-+	V_SCALER_EFFICIENCY_LB36BPP = 0,
-+	V_SCALER_EFFICIENCY_LB30BPP = 1,
-+	V_SCALER_EFFICIENCY_LB24BPP = 2,
-+	V_SCALER_EFFICIENCY_LB18BPP = 3
-+};
-+
-+/* Parameters required for minimum Engine
-+ * and minimum Display clock calculations*/
-+struct min_clock_params {
-+	uint32_t id;
-+	uint32_t requested_pixel_clock; /* in KHz */
-+	uint32_t actual_pixel_clock; /* in KHz */
-+	struct view source_view;
-+	struct view dest_view;
-+	struct dc_timing_params timing_info;
-+	struct dc_scaling_params scaling_info;
-+	struct color_quality color_info;
-+	enum signal_type signal_type;
-+	enum dc_color_depth deep_color_depth;
-+	enum v_scaler_efficiency scaler_efficiency;
-+	bool line_buffer_prefetch_enabled;
-+};
-+
-+/* Enumerations for Source selection of the Display clock */
-+enum display_clock_source_select {
-+	USE_PIXEL_CLOCK_PLL = 0,
-+	USE_EXTERNAL_CLOCK,
-+	USE_ENGINE_CLOCK
-+};
-+
-+/* Result of Minimum System and Display clock calculations.
-+ * Minimum System clock and Display clock, source and path to be used
-+ * for Display clock*/
-+struct minimum_clocks_calculation_result {
-+	uint32_t min_sclk_khz;
-+	uint32_t min_dclk_khz;
-+	uint32_t min_mclk_khz;
-+	uint32_t min_deep_sleep_sclk;
-+};
-+
-+/* Enumeration of all clocks states */
-+enum clocks_state {
-+	CLOCKS_STATE_INVALID,
-+	CLOCKS_STATE_ULTRA_LOW,
-+	CLOCKS_STATE_LOW,
-+	CLOCKS_STATE_NOMINAL,
-+	CLOCKS_STATE_PERFORMANCE
-+};
-+
-+/* Structure containing all state-dependent clocks
-+ * (dependent on "enum clocks_state") */
-+struct state_dependent_clocks {
-+	uint32_t display_clk_khz;
-+	uint32_t pixel_clk_khz;
-+	uint32_t dvo_clk_khz;
-+};
-+
-+struct display_clock_state {
-+	uint32_t DFS_BYPASS_ACTIVE:1;
-+};
-+
-+struct display_clock;
-+
-+struct display_clock *dal_display_clock_dce110_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as);
-+
-+struct display_clock *dal_display_clock_dce80_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as);
-+
-+void dal_display_clock_destroy(struct display_clock **to_destroy);
-+bool dal_display_clock_validate(
-+	struct display_clock *disp_clk,
-+	struct min_clock_params *params);
-+uint32_t dal_display_clock_calculate_min_clock(
-+	struct display_clock *disp_clk,
-+	uint32_t path_num,
-+	struct min_clock_params *params);
-+uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
-+void dal_display_clock_set_clock(
-+	struct display_clock *disp_clk,
-+	uint32_t requested_clock_khz);
-+uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk);
-+enum clocks_state dal_display_clock_get_min_clocks_state(
-+	struct display_clock *disp_clk);
-+enum clocks_state dal_display_clock_get_required_clocks_state(
-+	struct display_clock *disp_clk,
-+	struct state_dependent_clocks *req_clocks);
-+bool dal_display_clock_set_min_clocks_state(
-+	struct display_clock *disp_clk,
-+	enum clocks_state clocks_state);
-+uint32_t dal_display_clock_get_dp_ref_clk_frequency(
-+	struct display_clock *disp_clk);
-+/*the second parameter of "switchreferenceclock" is
-+ * a dummy argument for all pre dce 6.0 versions*/
-+void dal_display_clock_switch_reference_clock(
-+	struct display_clock *disp_clk,
-+	bool use_external_ref_clk,
-+	uint32_t requested_clock_khz);
-+void dal_display_clock_set_dp_ref_clock_source(
-+	struct display_clock *disp_clk,
-+	enum clock_source_id clk_src);
-+void dal_display_clock_store_max_clocks_state(
-+	struct display_clock *disp_clk,
-+	enum clocks_state max_clocks_state);
-+void dal_display_clock_set_clock_state(
-+	struct display_clock *disp_clk,
-+	struct display_clock_state clk_state);
-+struct display_clock_state dal_display_clock_get_clock_state(
-+	struct display_clock *disp_clk);
-+uint32_t dal_display_clock_get_dfs_bypass_threshold(
-+	struct display_clock *disp_clk);
-+void dal_display_clock_invalid_clock_state(
-+	struct display_clock *disp_clk);
-+
-+
-+#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_path_interface.h b/drivers/gpu/drm/amd/dal/include/display_path_interface.h
-new file mode 100644
-index 0000000..7bf2ef2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/display_path_interface.h
-@@ -0,0 +1,436 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DISPLAY_PATH_INTERFACE_H__
-+#define __DISPLAY_PATH_INTERFACE_H__
-+
-+#include "display_path_types.h"
-+#include "dcs_types.h"
-+#include "grph_object_ctrl_defs.h"
-+#include "signal_types.h"
-+#include "controller_types.h"
-+
-+struct encoder;
-+struct controller;
-+struct connector;
-+struct audio;
-+struct clock_source;
-+struct link_service;
-+struct goc_link_service_data;
-+struct drr_config;
-+
-+struct display_path;
-+
-+struct display_path *dal_display_path_create(void);
-+
-+struct display_path *dal_display_path_clone(
-+	const struct display_path *self,
-+	bool copy_active_state);
-+
-+void dal_display_path_destroy(
-+	struct display_path **to_destroy);
-+
-+bool dal_display_path_validate(
-+	struct display_path *path,
-+	enum signal_type sink_signal);
-+
-+bool dal_display_path_add_link(
-+	struct display_path *path,
-+	struct encoder *encoder);
-+
-+bool dal_display_path_add_connector(
-+	struct display_path *path,
-+	struct connector *connector);
-+
-+struct connector *dal_display_path_get_connector(
-+	struct display_path *path);
-+
-+int32_t dal_display_path_acquire(
-+	struct display_path *path);
-+
-+bool dal_display_path_is_acquired(
-+	const struct display_path *path);
-+
-+int32_t dal_display_path_get_ref_counter(
-+	const struct display_path *path);
-+
-+int32_t dal_display_path_release(
-+	struct display_path *path);
-+
-+void dal_display_path_release_resources(
-+	struct display_path *path);
-+
-+void dal_display_path_acquire_links(
-+	struct display_path *path);
-+
-+bool dal_display_path_is_source_blanked(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_source_unblanked(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_source_blanked(
-+	struct display_path *path,
-+	enum display_tri_state state);
-+
-+bool dal_display_path_is_target_blanked(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_target_unblanked(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_target_blanked(
-+	struct display_path *path,
-+	enum display_tri_state state);
-+
-+bool dal_display_path_is_target_powered_on(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_target_powered_off(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_target_powered_on(
-+	struct display_path *path,
-+	enum display_tri_state state);
-+
-+bool dal_display_path_is_target_connected(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_target_connected(
-+	struct display_path *path,
-+	bool c);
-+
-+uint32_t dal_display_path_get_display_index(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_display_index(
-+	struct display_path *path,
-+	uint32_t index);
-+
-+struct connector_device_tag_info *dal_display_path_get_device_tag(
-+	struct display_path *path);
-+
-+void dal_display_path_set_device_tag(
-+	struct display_path *path,
-+	struct connector_device_tag_info tag);
-+
-+enum clock_sharing_group dal_display_path_get_clock_sharing_group(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_clock_sharing_group(
-+	struct display_path *path,
-+	enum clock_sharing_group clock);
-+
-+union display_path_properties dal_display_path_get_properties(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_properties(
-+	struct display_path *path,
-+	union display_path_properties p);
-+
-+struct dcs *dal_display_path_get_dcs(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_dcs(
-+	struct display_path *path,
-+	struct dcs *dcs);
-+
-+uint32_t dal_display_path_get_number_of_links(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_controller(
-+	struct display_path *path,
-+	struct controller *controller);
-+
-+struct controller *dal_display_path_get_controller(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_clock_source(
-+	struct display_path *path,
-+	struct clock_source *clock);
-+
-+struct clock_source *dal_display_path_get_clock_source(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_alt_clock_source(
-+	struct display_path *path,
-+	struct clock_source *clock);
-+
-+struct clock_source *dal_display_path_get_alt_clock_source(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_fbc_info(
-+	struct display_path *path,
-+	struct fbc_info *clock);
-+
-+struct fbc_info *dal_display_path_get_fbc_info(
-+	struct display_path *path);
-+
-+void dal_display_path_set_drr_config(
-+	struct display_path *path,
-+	struct drr_config *clock);
-+
-+void dal_display_path_get_drr_config(
-+	const struct display_path *path,
-+	struct drr_config *clock);
-+
-+void dal_display_path_set_static_screen_triggers(
-+	struct display_path *path,
-+	const struct static_screen_events *events);
-+
-+void dal_display_path_get_static_screen_triggers(
-+	const struct display_path *path,
-+	struct static_screen_events *events);
-+
-+bool dal_display_path_is_psr_supported(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_drr_supported(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_link_service_data(
-+	struct display_path *path,
-+	uint32_t idx,
-+	const struct goc_link_service_data *data);
-+
-+bool dal_display_path_get_link_service_data(
-+	const struct display_path *path,
-+	uint32_t idx,
-+	struct goc_link_service_data *data);
-+
-+struct link_service *dal_display_path_get_link_query_interface(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+void dal_display_path_set_link_query_interface(
-+	struct display_path *path,
-+	uint32_t idx,
-+	struct link_service *link);
-+
-+struct link_service *dal_display_path_get_link_config_interface(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct link_service *dal_display_path_get_link_service_interface(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct encoder *dal_display_path_get_upstream_encoder(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct encoder *dal_display_path_get_upstream_object(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct encoder *dal_display_path_get_downstream_encoder(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct encoder *dal_display_path_get_downstream_object(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct audio *dal_display_path_get_audio(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+void dal_display_path_set_audio(
-+	struct display_path *path,
-+	uint32_t idx,
-+	struct audio *a);
-+
-+struct audio *dal_display_path_get_audio_object(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+void dal_display_path_set_audio_active_state(
-+	struct display_path *path,
-+	uint32_t idx,
-+	bool state);
-+
-+enum engine_id dal_display_path_get_stream_engine(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+void dal_display_path_set_stream_engine(
-+	struct display_path *path,
-+	uint32_t idx,
-+	enum engine_id id);
-+
-+bool dal_display_path_is_link_active(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+void dal_display_path_set_link_active_state(
-+	struct display_path *path,
-+	uint32_t idx,
-+	bool state);
-+
-+enum signal_type dal_display_path_get_config_signal(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+enum signal_type dal_display_path_get_query_signal(
-+	const struct display_path *path,
-+	uint32_t idx);
-+
-+struct link_service *dal_display_path_get_mst_link_service(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_sync_output_object(
-+	struct display_path *path,
-+	enum sync_source o_source,
-+	struct encoder *o_object);
-+
-+struct encoder *dal_display_path_get_sync_output_object(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_stereo_sync_object(
-+	struct display_path *path,
-+	struct encoder *stereo_sync);
-+
-+struct encoder *dal_display_path_get_stereo_sync_object(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_sync_input_source(
-+	struct display_path *path,
-+	enum sync_source s);
-+
-+enum sync_source dal_display_path_get_sync_input_source(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_sync_output_source(
-+	struct display_path *path,
-+	enum sync_source s);
-+
-+enum sync_source dal_display_path_get_sync_output_source(
-+	const struct display_path *path);
-+
-+bool dal_display_path_set_pixel_clock_safe_range(
-+	struct display_path *path,
-+	struct pixel_clock_safe_range *range);
-+
-+bool dal_display_path_get_pixel_clock_safe_range(
-+	const struct display_path *path,
-+	struct pixel_clock_safe_range *range);
-+
-+void dal_display_path_set_ddi_channel_mapping(
-+	struct display_path *path,
-+	union ddi_channel_mapping mapping);
-+
-+bool dal_display_path_set_sink_signal(
-+	struct display_path *path,
-+	enum signal_type sink_signal);
-+
-+enum signal_type dal_display_path_sink_signal_to_asic_signal(
-+	struct display_path *path,
-+	enum signal_type sink_signal);
-+
-+enum signal_type dal_display_path_sink_signal_to_link_signal(
-+	struct display_path *path,
-+	enum signal_type sink_signal,
-+	uint32_t idx);
-+
-+enum signal_type dal_display_path_downstream_to_upstream_signal(
-+	struct display_path *path,
-+	enum signal_type signal,
-+	uint32_t idx);
-+
-+bool dal_display_path_is_audio_present(
-+	const struct display_path *path,
-+	uint32_t *audio_pin);
-+
-+bool dal_display_path_is_dp_auth_supported(
-+	struct display_path *path);
-+
-+bool dal_display_path_is_vce_supported(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_sls_capable(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_gen_lock_capable(
-+	const struct display_path *path);
-+
-+struct transmitter_configuration dal_display_path_get_transmitter_configuration(
-+	const struct display_path *path,
-+	bool physical);
-+
-+bool dal_display_path_is_ss_supported(
-+	const struct display_path *path);
-+
-+bool dal_display_path_is_ss_configurable(
-+	const struct display_path *path);
-+
-+void dal_display_path_set_ss_support(
-+	struct display_path *path,
-+	bool s);
-+
-+enum signal_type dal_display_path_get_active_signal(
-+	struct display_path *path,
-+	uint32_t idx);
-+
-+bool dal_display_path_contains_object(
-+	struct display_path *path,
-+	struct graphics_object_id id);
-+
-+/* Multi-plane declarations.
-+ * This structure should also be used for Stereo. */
-+struct display_path_plane {
-+	struct controller *controller;
-+	/* During dal_tm_acquire_plane_resources() set blnd_mode, because
-+	 * "layer index" is known at that point, and we must decide how
-+	 * "controller" should do the blending */
-+	enum blender_mode blnd_mode;
-+	/* Some use-cases allow to power-gate FE.
-+	 * For example, with Full Screen Video on Underlay we can
-+	 * disable the 'root' plane.
-+	 * This flag indicates that FE should be power-gated */
-+	bool disabled;
-+};
-+
-+bool dal_display_path_add_plane(
-+	struct display_path *path,
-+	struct display_path_plane *plane);
-+
-+uint8_t dal_display_path_get_number_of_planes(
-+	const struct display_path *path);
-+
-+struct display_path_plane *dal_display_path_get_plane_at_index(
-+	const struct display_path *path,
-+	uint8_t index);
-+
-+struct controller *dal_display_path_get_controller_for_layer_index(
-+	const struct display_path *path,
-+	uint8_t layer_index);
-+
-+void dal_display_path_release_planes(
-+	struct display_path *path);
-+
-+void dal_display_path_release_non_root_planes(
-+	struct display_path *path);
-+
-+#endif /* __DISPLAY_PATH_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_path_types.h b/drivers/gpu/drm/amd/dal/include/display_path_types.h
-new file mode 100644
-index 0000000..8aac46d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/display_path_types.h
-@@ -0,0 +1,132 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DISPLAY_PATH_TYPES_H__
-+#define __DAL_DISPLAY_PATH_TYPES_H__
-+
-+#include "grph_object_defs.h"
-+
-+enum {
-+	CONTROLLER_HANDLE_INVALID = (uint32_t) (-1)
-+};
-+
-+/*Limit maximum number of cofunctional paths*/
-+enum {
-+	MAX_COFUNCTIONAL_PATHS = 6
-+};
-+
-+struct pixel_clock_safe_range {
-+	uint32_t min_frequency;
-+	uint32_t max_frequency;
-+};
-+
-+/**
-+ *  ClockSharingGroup
-+ *  Enumeration of Clock Source Sharing categories
-+ *  Instead using enum we define valid range for clock sharing group values
-+ *  This is because potential num of group can be pretty big
-+ */
-+
-+enum clock_sharing_group {
-+	/* Default group for display paths that cannot share clock source.
-+	 * Display path in such group will aqcuire clock source exclusively*/
-+	CLOCK_SHARING_GROUP_EXCLUSIVE = 0,
-+	/* DisplayPort paths will have this group if clock sharing
-+	 * level is DisplayPortShareable*/
-+	CLOCK_SHARING_GROUP_DISPLAY_PORT = 1,
-+	/* Mst paths will have this group if clock sharing
-+	 * level is DpMstShareable*/
-+	CLOCK_SHARING_GROUP_DP_MST = 2,
-+	/* Display paths will have this group when
-+	 * desired to use alternative DPRef clock source.*/
-+	CLOCK_SHARING_GROUP_ALTERNATIVE_DP_REF = 3,
-+	/* Start of generic SW sharing groups.*/
-+	CLOCK_SHARING_GROUP_GROUP1 = 4,
-+	/* Total number of clock sharing groups.*/
-+	CLOCK_SHARING_GROUP_MAX = 32,
-+};
-+/* Should be around maximal number of ever connected displays (since boot :)*/
-+/*TEMP*/
-+enum goc_link_settings_type {
-+	GOC_LINK_SETTINGS_TYPE_PREFERRED = 0,
-+	GOC_LINK_SETTINGS_TYPE_REPORTED,
-+	GOC_LINK_SETTINGS_TYPE_TRAINED,
-+	GOC_LINK_SETTINGS_TYPE_OVERRIDEN_TRAINED,
-+	GOC_LINK_SETTINGS_TYPE_MAX
-+};
-+
-+struct dp_audio_test_data {
-+
-+	struct dp_audio_test_data_flags {
-+		uint32_t test_requested:1;
-+		uint32_t disable_video:1;
-+	} flags;
-+
-+	/*struct dp_audio_test_data_flags flags;*/
-+	uint32_t sampling_rate;
-+	uint32_t channel_count;
-+	uint32_t pattern_type;
-+	uint8_t pattern_period[8];
-+};
-+
-+struct goc_link_service_data {
-+	struct dp_audio_test_data dp_audio_test_data;
-+};
-+/* END-OF-TEMP*/
-+
-+
-+union display_path_properties {
-+	struct bit_map {
-+		uint32_t ALWAYS_CONNECTED:1;
-+		uint32_t HPD_SUPPORTED:1;
-+		uint32_t NON_DESTRUCTIVE_POLLING:1;
-+		uint32_t FORCE_CONNECT_SUPPORTED:1;
-+		uint32_t FAKED_PATH:1;
-+		uint32_t IS_BRANCH_DP_MST_PATH:1;
-+		uint32_t IS_ROOT_DP_MST_PATH:1;
-+		uint32_t IS_DP_AUDIO_SUPPORTED:1;
-+		uint32_t IS_HDMI_AUDIO_SUPPORTED:1;
-+	} bits;
-+
-+	uint32_t raw;
-+};
-+
-+enum display_tri_state {
-+	DISPLAY_TRI_STATE_UNKNOWN = 0,
-+	DISPLAY_TRI_STATE_TRUE,
-+	DISPLAY_TRI_STATE_FALSE
-+};
-+
-+enum {
-+	MAX_NUM_OF_LINKS_PER_PATH = 2
-+};
-+enum {
-+	SINK_LINK_INDEX = (uint32_t) (-1)
-+};
-+enum {
-+	ASIC_LINK_INDEX = 0
-+};
-+
-+#endif /* __DAL_DISPLAY_PATH_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_service_interface.h b/drivers/gpu/drm/amd/dal/include/display_service_interface.h
-new file mode 100644
-index 0000000..b602bca
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/display_service_interface.h
-@@ -0,0 +1,165 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DISPLAY_SERVICE_INTERFACE_H__
-+#define __DISPLAY_SERVICE_INTERFACE_H__
-+
-+#include "include/display_service_types.h"
-+#include "include/display_path_types.h"
-+#include "include/grph_object_ctrl_defs.h"
-+
-+struct display_service;
-+struct ds_overlay;
-+struct ds_dispatch;
-+struct ds_synchronization;
-+struct path_mode_set;
-+
-+struct display_service *dal_display_service_create(
-+	struct ds_init_data *data);
-+
-+void dal_display_service_destroy(
-+	struct display_service **ds);
-+
-+struct ds_dispatch *dal_display_service_get_adjustment_interface(
-+	struct display_service *ds);
-+
-+struct ds_overlay *dal_display_service_get_overlay_interface(
-+	struct display_service *ds);
-+
-+struct ds_dispatch *dal_display_service_get_set_mode_interface(
-+	struct display_service *ds);
-+
-+struct ds_dispatch *dal_display_service_get_reset_mode_interface(
-+	struct display_service *ds);
-+
-+struct ds_synchronization *dal_display_service_get_synchronization_interface(
-+	struct display_service *ds);
-+
-+enum ds_return dal_display_service_notify_v_sync_int_state(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool maintain_v_sync_phase);
-+
-+enum ds_return dal_display_service_target_power_control(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool power_on);
-+
-+enum ds_return dal_display_service_power_down_active_hw(
-+	struct display_service *ds,
-+	enum dc_video_power_state state);
-+
-+enum ds_return dal_display_service_mem_request_control(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool enable);
-+
-+enum ds_return dal_display_service_set_multimedia_pass_through_mode(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool passThrough);
-+
-+enum ds_return dal_display_service_set_palette(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	const struct ds_devclut *palette,
-+	const uint32_t start,
-+	const uint32_t length);
-+
-+enum ds_return dal_display_service_apply_pix_clk_range(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	struct pixel_clock_safe_range *range);
-+
-+enum ds_return dal_display_service_get_safe_pix_clk(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	uint32_t *pix_clk_khz);
-+
-+enum ds_return dal_display_service_apply_refreshrate_adjustment(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	enum ds_refreshrate_adjust_action action,
-+	struct ds_refreshrate *refreshrate);
-+
-+enum ds_return dal_display_service_pre_ddc(
-+	struct display_service *ds,
-+	uint32_t display_index);
-+
-+enum ds_return dal_display_service_post_ddc(
-+	struct display_service *ds,
-+	uint32_t display_index);
-+
-+enum ds_return dal_display_service_backlight_control(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool enable);
-+
-+enum ds_return dal_display_service_get_backlight_user_level(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	uint32_t *level);
-+
-+enum ds_return dal_display_service_get_backlight_effective_level(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	uint32_t *level);
-+
-+enum ds_return dal_display_service_enable_hpd(
-+	struct display_service *ds,
-+	uint32_t display_index);
-+
-+enum ds_return dal_display_service_disable_hpd(
-+	struct display_service *ds,
-+	uint32_t display_index);
-+
-+enum ds_return dal_display_service_get_min_mem_channels(
-+	struct display_service *ds,
-+	const struct path_mode_set *path_mode_set,
-+	uint32_t mem_channels_num,
-+	uint32_t *min_mem_channels_num);
-+
-+enum ds_return dal_display_service_enable_advanced_request(
-+	struct display_service *ds,
-+	bool enable);
-+
-+/*Audio related*/
-+enum ds_return dal_display_service_enable_audio_endpoint(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool enable);
-+
-+enum ds_return dal_display_service_mute_audio_endpoint(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	bool mute);
-+
-+bool dal_display_service_calc_view_port_for_wide_display(
-+	struct display_service *ds,
-+	uint32_t display_index,
-+	const struct ds_view_port *set_view_port,
-+	struct ds_get_view_port *get_view_port);
-+
-+#endif /* __DISPLAY_SERVICE_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_service_types.h b/drivers/gpu/drm/amd/dal/include/display_service_types.h
-new file mode 100644
-index 0000000..4f27f59
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/display_service_types.h
-@@ -0,0 +1,167 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DISPLAY_SERVICE_TYPES_H__
-+#define __DAL_DISPLAY_SERVICE_TYPES_H__
-+struct ds_dispatch {
-+
-+};
-+
-+struct ds_view_port_alignment {
-+	uint8_t x_width_size_alignment;
-+	uint8_t y_height_size_alignment;
-+	uint8_t x_start_alignment;
-+	uint8_t y_start_alignment;
-+};
-+
-+struct hw_sequencer;
-+struct topology_mgr;
-+struct adapter_service;
-+struct timing_service;
-+
-+struct ds_init_data {
-+	struct dal_context *dal_context;
-+	struct hw_sequencer *hwss;
-+	struct topology_mgr *tm;
-+	struct adapter_service *as;
-+	struct timing_service *ts;
-+	struct ds_view_port_alignment view_port_alignment;
-+};
-+
-+enum ds_return {
-+	DS_SUCCESS,
-+	DS_SUCCESS_FALLBACK,
-+	DS_ERROR,
-+	DS_SET_MODE_REQUIRED,
-+	DS_REBOOT_REQUIRED,
-+	DS_OUT_OF_RANGE,
-+	DS_RESOURCE_UNAVAILABLE,
-+	DS_NOT_SUPPORTED
-+};
-+
-+struct ds_devclut {
-+	uint8_t red;
-+	uint8_t green;
-+	uint8_t blue;
-+	uint8_t reserved;
-+};
-+
-+enum ds_refreshrate_adjust_action {
-+	DS_REFRESHRATE_ADJUST_ACTION_SET,
-+	DS_REFRESHRATE_ADJUST_ACTION_RESET,
-+	DS_REFRESHRATE_ADJUST_ACTION_UPDATE,
-+};
-+
-+struct ds_refreshrate {
-+	uint32_t numerator;
-+	uint32_t denominator;
-+};
-+
-+/*Contains delta in pixels between two active CRTC timings and relevant timing
-+details. Delta will be positive if CRTC1 timing running before CRTC2 and
-+negative otherwise (CRTC2 timing running before CRTC1)*/
-+/*CRTC1 running before CRTC2 = CRTC1 pixel position in
-+frame smaller then CRTC2 position*/
-+struct ds_timings_delta_info {
-+	int32_t delta_in_pixels;
-+	uint32_t pix_clk_khz;
-+	uint32_t h_total;
-+	uint32_t v_total;
-+};
-+
-+enum ds_audio_os_channel_name {
-+	DS_AUDIO_OS_CHANNEL_L = 0,
-+	DS_AUDIO_OS_CHANNEL_R = 1,
-+	DS_AUDIO_OS_CHANNEL_C = 2,
-+	DS_AUDIO_OS_CHANNEL_SUB = 3,
-+	DS_AUDIO_OS_CHANNEL_RL = 4,
-+	DS_AUDIO_OS_CHANNEL_RR = 5,
-+	DS_AUDIO_OS_CHANNEL_SL = 6,
-+	DS_AUDIO_OS_CHANNEL_SR = 7,
-+	DS_AUDIO_OS_CHANNEL_SILENT = 8,
-+	DS_AUDIO_OS_CHANNEL_NO_ASSOCIATION = 15
-+};
-+
-+enum ds_audio_azalia_channel_name {
-+	DS_AUDIO_AZALIA_CHANNEL_FL = 0,
-+	DS_AUDIO_AZALIA_CHANNEL_FR = 1,
-+	DS_AUDIO_AZALIA_CHANNEL_FC = 2,
-+	DS_AUDIO_AZALIA_CHANNEL_SUB = 3,
-+	DS_AUDIO_AZALIA_CHANNEL_SL = 4,
-+	DS_AUDIO_AZALIA_CHANNEL_SR = 5,
-+	DS_AUDIO_AZALIA_CHANNEL_BL = 6,
-+	DS_AUDIO_AZALIA_CHANNEL_BR = 7,
-+	DS_AUDIO_AZALIA_CHANNEL_SILENT = 8,
-+	DS_AUDIO_AZALIA_CHANNEL_NO_ASSOCIATION = 15
-+};
-+
-+enum ds_audio_channel_format {
-+	DS_AUDIO_CHANNEL_FORMAT_2P0 = 0,
-+	DS_AUDIO_CHANNEL_FORMAT_2P1,
-+	DS_AUDIO_CHANNEL_FORMAT_5P1,
-+	DS_AUDIO_CHANNEL_FORMAT_7P1
-+};
-+
-+/*Used for get/set Mirabilis*/
-+enum ds_mirabilis_control_option {
-+	DS_MIRABILIS_UNINITIALIZE = 0,
-+	DS_MIRABILIS_DISABLE,
-+	DS_MIRABILIS_ENABLE,
-+	DS_MIRABILIS_SAVE_PROFILE
-+};
-+
-+struct ds_disp_identifier {
-+	uint32_t display_index;
-+	uint32_t manufacture_id;
-+	uint32_t product_id;
-+	uint32_t serial_no;
-+};
-+
-+struct ds_view_port {
-+	uint32_t x_start;
-+	uint32_t y_start;
-+	uint32_t width;
-+	uint32_t height;
-+	uint32_t controller;
-+};
-+
-+#define DS_MAX_NUM_VIEW_PORTS 2
-+struct ds_get_view_port {
-+	uint32_t num_of_view_ports;
-+	struct ds_view_port view_ports[DS_MAX_NUM_VIEW_PORTS];
-+};
-+
-+struct ranged_timing_preference_flags {
-+	union {
-+		struct {
-+			uint32_t prefer_enable_drr:1;
-+			uint32_t force_disable_drr:1;
-+
-+		} bits;
-+		uint32_t u32all;
-+	};
-+};
-+
-+#endif /* __DAL_DISPLAY_SERVICE_TYPE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_interface.h b/drivers/gpu/drm/amd/dal/include/dmcu_interface.h
-new file mode 100644
-index 0000000..c712cc2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dmcu_interface.h
-@@ -0,0 +1,87 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DMCU_INTERFACE_H__
-+#define __DAL_DMCU_INTERFACE_H__
-+
-+#include "grph_object_defs.h"
-+#include "dmcu_types.h"
-+
-+/* Interface functions */
-+
-+/* DMCU setup related interface functions */
-+struct dmcu *dal_dmcu_create(
-+	struct dmcu_init_data *init_data);
-+void dal_dmcu_destroy(struct dmcu **dmcu);
-+void dal_dmcu_release_hw(struct dmcu *dmcu);
-+
-+void dal_dmcu_power_up(struct dmcu *dmcu);
-+void dal_dmcu_power_down(struct dmcu *dmcu);
-+
-+void dal_dmcu_configure_wait_loop(
-+		struct dmcu *dmcu,
-+		uint32_t display_clock);
-+
-+/* PSR feature related interface functions */
-+void dal_dmcu_psr_setup(
-+		struct dmcu *dmcu,
-+		struct dmcu_context *dmcu_context);
-+void dal_dmcu_psr_enable(struct dmcu *dmcu);
-+void dal_dmcu_psr_disable(struct dmcu *dmcu);
-+void dal_dmcu_psr_block(struct dmcu *dmcu, bool block_psr);
-+bool dal_dmcu_psr_is_blocked(struct dmcu *dmcu);
-+void dal_dmcu_psr_set_level(
-+		struct dmcu *dmcu,
-+		union dmcu_psr_level psr_level);
-+void dal_dmcu_psr_allow_power_down_crtc(
-+		struct dmcu *dmcu,
-+		bool should_allow_crtc_power_down);
-+bool dal_dmcu_psr_submit_command(
-+		struct dmcu *dmcu,
-+		struct dmcu_context *dmcu_context,
-+		struct dmcu_config_data *config_data);
-+void dal_dmcu_psr_get_config_data(
-+		struct dmcu *dmcu,
-+		uint32_t v_total,
-+		struct dmcu_config_data *config_data);
-+
-+/* ABM feature related interface functions */
-+void dal_dmcu_abm_enable(
-+		struct dmcu *dmcu,
-+		enum controller_id controller_id,
-+		uint32_t vsync_rate_hz);
-+void dal_dmcu_abm_disable(struct dmcu *dmcu);
-+bool dal_dmcu_abm_enable_smooth_brightness(struct dmcu *dmcu);
-+bool dal_dmcu_abm_disable_smooth_brightness(struct dmcu *dmcu);
-+void dal_dmcu_abm_varibright_control(
-+		struct dmcu *dmcu,
-+		const struct varibright_control *varibright_control);
-+bool dal_dmcu_abm_set_backlight_level(
-+		struct dmcu *dmcu,
-+		uint8_t backlight_8_bit);
-+uint8_t dal_dmcu_abm_get_user_backlight_level(struct dmcu *dmcu);
-+uint8_t dal_dmcu_abm_get_current_backlight_level(struct dmcu *dmcu);
-+
-+#endif /* __DAL_DMCU_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_types.h b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-new file mode 100644
-index 0000000..1f3107d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-@@ -0,0 +1,199 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DMCU_TYPES_H__
-+#define __DAL_DMCU_TYPES_H__
-+
-+/* Forward declaration */
-+struct dmcu;
-+
-+/* Required information for creation and initialization of a controller */
-+struct dmcu_init_data {
-+	struct dal_context *dal_context;
-+	struct adapter_service *as;
-+	uint32_t max_engine_clock_in_khz;
-+};
-+
-+/* Interface structure defines */
-+
-+enum dmcu_action {
-+	DMCU_ACTION_PSR_ENABLE,
-+	DMCU_ACTION_PSR_EXIT,
-+	DMCU_ACTION_PSR_RFB_UPDATE,
-+	DMCU_ACTION_PSR_SET,
-+	DMCU_ACTION_PSR_CLEAR_COUNT,
-+	DMCU_ACTION_PSR_COUNT_REQUEST,
-+	DMCU_ACTION_PSR_STATE_REQUEST,
-+	DMCU_ACTION_PSR_SET_LEVEL,
-+	DMCU_ACTION_PSR_ADVANCE_STATE,
-+	DMCU_ACTION_PSR_SET_WAITLOOP
-+};
-+
-+enum dmcu_output {
-+	DMCU_OUTPUT_PSR_ACK,
-+	DMCU_OUTPUT_PSR_NACK,
-+	DMCU_OUTPUT_PSR_AUX_ERR,
-+	DMCU_OUTPUT_PSR_COUNT_STATUS,
-+	DMCU_OUTPUT_PSR_STATE_STATUS,
-+	DMCU_OUTPUT_PSR_RFB_UPDATE_ERR,
-+	DMCU_OUTPUT_PSR_ERR,
-+	DMCU_OUTPUT_PSR_GET_REPLY,
-+	DMCU_OUTPUT_PSR_ENTRY_ERROR,
-+	DMCU_OUTPUT_PSR_LT_ERROR,
-+	DMCU_OUTPUT_PSR_FORCE_SR_ERROR,
-+	DMCU_OUTPUT_PSR_SDP_SEND_TIMEOUT
-+};
-+
-+/* PSR states, based similarly on states defined in eDP specification. */
-+enum psr_state {
-+	STATE0,		/* PSR is disabled */
-+	STATE1,		/* PSR is enabled, but inactive */
-+	STATE1A,
-+	STATE2,		/* PSR is transitioning to active state */
-+	STATE2A,
-+	STATE3,		/* PSR is active; Display is in self refresh */
-+	STATE3INIT,
-+	STATE4,		/* RFB single frame update */
-+	STATE4A,
-+	STATE4B,
-+	STATE4C,
-+	STATE4D,
-+	STATE5,		/* Exiting from PSR active state */
-+	STATE5A,
-+	STATE5B,
-+	STATE5C
-+};
-+
-+enum phy_type {
-+	PHY_TYPE_UNKNOWN = 1,
-+	PHY_TYPE_PCIE_PHY = 2,
-+	PHY_TYPE_UNIPHY = 3,
-+};
-+
-+struct dmcu_context {
-+	enum channel_id channel;
-+	enum transmitter transmitter_id;
-+	enum engine_id engine_id;
-+	enum controller_id controller_id;
-+	enum phy_type phy_type;
-+	enum physical_phy_id smu_physical_phy_id;
-+
-+	/* Vertical total pixels from crtc timing.
-+	 * This is used for static screen detection.
-+	 * ie. If we want to detect half a frame,
-+	 * we use this to determine the hyst lines.*/
-+	uint32_t crtc_timing_vertical_total;
-+
-+	/* PSR supported from panel capabilities
-+	 * and current display configuration */
-+	bool psr_supported_display_config;
-+
-+	/* Whether fast link training is supported by the panel */
-+	bool psr_exit_link_training_required;
-+
-+	/* If RFB setup time is greater than the total VBLANK time, it is not
-+	 * possible for the sink to capture the video frame in the same frame
-+	 * the SDP is sent. In this case, the frame capture indication bit
-+	 * should be set and an extra static frame should be transmitted to
-+	 * the sink */
-+	bool psr_frame_capture_indication_required;
-+
-+	/* Set the last possible line SDP may be transmitted without violating
-+	 * the RFB setup time */
-+	bool sdp_transmit_line_num_deadline;
-+
-+	/* The VSync rate in Hz used to calculate the step size
-+	 * for smooth brightness feature */
-+	uint32_t vsync_rate_hz;
-+};
-+
-+union dmcu_psr_level {
-+	struct {
-+		bool SKIP_CRC:1;
-+		bool SKIP_DP_VID_STREAM_DISABLE:1;
-+		bool SKIP_PHY_POWER_DOWN:1;
-+		bool SKIP_AUX_ACK_CHECK:1;
-+		bool SKIP_CRTC_DISABLE:1;
-+		bool SKIP_AUX_RFB_CAPTURE_CHECK:1;
-+		bool SKIP_SMU_NOTIFICATION:1;
-+		bool SKIP_AUTO_STATE_ADVANCE:1;
-+		bool DISABLE_PSR_ENTRY_ABORT:1;
-+	} bits;
-+	uint32_t u32all;
-+};
-+
-+struct dmcu_config_data {
-+	/* Command sent to DMCU. */
-+	enum dmcu_action action;
-+	/* PSR Level controls which HW blocks to power down during PSR active,
-+	 * and also other sequence modifications. */
-+	union dmcu_psr_level psr_level;
-+	/* To indicate that first changed frame from active state should not
-+	 * result in exit to inactive state, but instead perform an automatic
-+	 * single frame RFB update. */
-+	bool rfb_update_auto_en;
-+	/* Number of consecutive static frames to detect before entering PSR
-+	 * active state. */
-+	uint32_t hyst_frames;
-+	/* Partial frames before entering PSR active. Note this parameter is in
-+	 * units of 100 lines. i.e. Wait a value of 5 means wait 500 additional
-+	 * lines. */
-+	uint32_t hyst_lines;
-+	/* Number of repeated AUX retries before indicating failure to driver.
-+	 * In a working case, first attempt to write/read AUX should pass. */
-+	uint32_t aux_repeat;
-+	/* Additional delay after remote frame capture before continuing to
-+	 * power down. This is mainly for debug purposes to identify timing
-+	 * issues. */
-+	uint32_t frame_delay;
-+	/* Controls how long the delay of a wait loop is. It should be tuned
-+	 * to 1 us, and needs to be reconfigured every time DISPCLK changes. */
-+	uint32_t wait_loop_num;
-+};
-+
-+struct dmcu_output_data {
-+	/* DMCU reply */
-+	enum dmcu_output output;
-+	/* The current PSR state. */
-+	uint32_t psr_state;
-+	/* The number of frames during PSR active state. */
-+	uint32_t psr_count;
-+};
-+
-+enum varibright_command {
-+	VARIBRIGHT_CMD_SET_VB_LEVEL = 0,
-+	VARIBRIGHT_CMD_USER_ENABLE,
-+	VARIBRIGHT_CMD_POST_DISPLAY_CONFIG,
-+	VARIBRIGHT_CMD_UNKNOWN
-+};
-+
-+struct varibright_control {
-+	enum varibright_command command;
-+	uint8_t level;
-+	bool enable;
-+	bool activate;
-+};
-+
-+#endif /* __DAL_DMCU_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h b/drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
-new file mode 100644
-index 0000000..a942c77
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
-@@ -0,0 +1,65 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifdef __DPCD_ACCESS_SERVICE_INTERFACE_HPP__
-+#define __DPCD_ACCESS_SERVICE_INTERFACE_HPP__
-+
-+/* DDC service transaction error codes
-+ * depends on transaction status
-+ */
-+enum ddc_result {
-+	DDCRESULT_UNKNOWN = 0,
-+	DDCRESULT_SUCESSFULL,
-+	DDCRESULT_FAILEDCHANNELBUSY,
-+	DDCRESULT_FAILEDTIMEOUT,
-+	DDCRESULT_FAILEDPROTOCOLERROR,
-+	DDCRESULT_FAILEDNACK,
-+	DDCRESULT_FAILEDINCOMPLETE,
-+	DDCRESULT_FAILEDOPERATION,
-+	DDCRESULT_FAILEDINVALIDOPERATION,
-+	DDCRESULT_FAILEDBUFFEROVERFLOW
-+};
-+
-+enum {
-+	MaxNativeAuxTransactionSize = 16
-+};
-+
-+struct display_sink_capability;
-+
-+/* TO DO: below functions can be moved to ddc_service (think about it)*/
-+enum ddc_result dal_ddc_read_dpcd_data(
-+		uint32_t address,
-+		unsigned char *data,
-+		uint32_t size);
-+
-+enum ddc_result dal_ddc_write_dpcd_data(
-+		uint32_t address,
-+		const unsigned char *data uint32_t size);
-+
-+bool dal_aux_query_dp_sink_capability(display_sink_capability *sink_cap);
-+bool start_gtc_sync(void);
-+bool stop_gtc_sync(void);
-+
-+#endif /*__DPCD_ACCESS_SERVICE_INTERFACE_HPP__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-new file mode 100644
-index 0000000..cefa1fc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -0,0 +1,869 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DPCD_DEFS_H__
-+#define __DAL_DPCD_DEFS_H__
-+
-+enum dpcd_address {
-+/* addresses marked with 1.2 are only defined since DP 1.2 spec */
-+
-+	/* Reciever Capability Field */
-+	DPCD_ADDRESS_DPCD_REV = 0x00000,
-+	DPCD_ADDRESS_MAX_LINK_RATE = 0x00001,
-+	DPCD_ADDRESS_MAX_LANE_COUNT = 0x00002,
-+	DPCD_ADDRESS_MAX_DOWNSPREAD = 0x00003,
-+	DPCD_ADDRESS_NORP = 0x00004,
-+	DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT = 0x00005,
-+	DPCD_ADDRESS_MAIN_LINK_CHANNEL_CODING = 0x00006,
-+	DPCD_ADDRESS_DOWNSTREAM_PORT_COUNT = 0x00007,
-+	DPCD_ADDRESS_RECEIVE_PORT0_CAP0 = 0x00008,
-+	DPCD_ADDRESS_RECEIVE_PORT0_CAP1 = 0x00009,
-+	DPCD_ADDRESS_RECEIVE_PORT1_CAP0 = 0x0000A,
-+	DPCD_ADDRESS_RECEIVE_PORT1_CAP1 = 0x0000B,
-+
-+	DPCD_ADDRESS_I2C_SPEED_CNTL_CAP = 0x0000C,/*1.2*/
-+	DPCD_ADDRESS_EDP_CONFIG_CAP = 0x0000D,/*1.2*/
-+	DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL = 0x000E,/*1.2*/
-+
-+	DPCD_ADDRESS_MSTM_CAP = 0x00021,/*1.2*/
-+
-+	/* Audio Video Sync Data Feild */
-+	DPCD_ADDRESS_AV_GRANULARITY = 0x0023,
-+	DPCD_ADDRESS_AUDIO_DECODE_LATENCY1 = 0x0024,
-+	DPCD_ADDRESS_AUDIO_DECODE_LATENCY2 = 0x0025,
-+	DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY1 = 0x0026,
-+	DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY2 = 0x0027,
-+	DPCD_ADDRESS_VIDEO_INTERLACED_LATENCY = 0x0028,
-+	DPCD_ADDRESS_VIDEO_PROGRESSIVE_LATENCY = 0x0029,
-+	DPCD_ADDRESS_AUDIO_DELAY_INSERT1 = 0x0002B,
-+	DPCD_ADDRESS_AUDIO_DELAY_INSERT2 = 0x0002C,
-+	DPCD_ADDRESS_AUDIO_DELAY_INSERT3 = 0x0002D,
-+
-+	/* Audio capability */
-+	DPCD_ADDRESS_NUM_OF_AUDIO_ENDPOINTS = 0x00022,
-+
-+	DPCD_ADDRESS_GUID_START = 0x00030,/*1.2*/
-+	DPCD_ADDRESS_GUID_END = 0x0003f,/*1.2*/
-+
-+	DPCD_ADDRESS_PSR_SUPPORT_VER = 0x00070,
-+	DPCD_ADDRESS_PSR_CAPABILITY = 0x00071,
-+
-+	DPCD_ADDRESS_DWN_STRM_PORT0_CAPS = 0x00080,/*1.2a*/
-+
-+	/* Link Configuration Field */
-+	DPCD_ADDRESS_LINK_BW_SET = 0x00100,
-+	DPCD_ADDRESS_LANE_COUNT_SET = 0x00101,
-+	DPCD_ADDRESS_TRAINING_PATTERN_SET = 0x00102,
-+	DPCD_ADDRESS_LANE0_SET = 0x00103,
-+	DPCD_ADDRESS_LANE1_SET = 0x00104,
-+	DPCD_ADDRESS_LANE2_SET = 0x00105,
-+	DPCD_ADDRESS_LANE3_SET = 0x00106,
-+	DPCD_ADDRESS_DOWNSPREAD_CNTL = 0x00107,
-+	DPCD_ADDRESS_I2C_SPEED_CNTL = 0x00109,/*1.2*/
-+
-+	DPCD_ADDRESS_EDP_CONFIG_SET = 0x0010A,
-+	DPCD_ADDRESS_LINK_QUAL_LANE0_SET = 0x0010B,
-+	DPCD_ADDRESS_LINK_QUAL_LANE1_SET = 0x0010C,
-+	DPCD_ADDRESS_LINK_QUAL_LANE2_SET = 0x0010D,
-+	DPCD_ADDRESS_LINK_QUAL_LANE3_SET = 0x0010E,
-+
-+	DPCD_ADDRESS_LANE0_SET2 = 0x0010F,/*1.2*/
-+	DPCD_ADDRESS_LANE2_SET2 = 0x00110,/*1.2*/
-+
-+	DPCD_ADDRESS_MSTM_CNTL = 0x00111,/*1.2*/
-+
-+	DPCD_ADDRESS_PSR_ENABLE_CFG = 0x0170,
-+
-+	/* Payload Table Configuration Field 1.2 */
-+	DPCD_ADDRESS_PAYLOAD_ALLOCATE_SET = 0x001C0,
-+	DPCD_ADDRESS_PAYLOAD_ALLOCATE_START_TIMESLOT = 0x001C1,
-+	DPCD_ADDRESS_PAYLOAD_ALLOCATE_TIMESLOT_COUNT = 0x001C2,
-+
-+	DPCD_ADDRESS_SINK_COUNT = 0x0200,
-+	DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR = 0x0201,
-+
-+	/* Link / Sink Status Field */
-+	DPCD_ADDRESS_LANE_01_STATUS = 0x00202,
-+	DPCD_ADDRESS_LANE_23_STATUS = 0x00203,
-+	DPCD_ADDRESS_LANE_ALIGN_STATUS_UPDATED = 0x0204,
-+	DPCD_ADDRESS_SINK_STATUS = 0x0205,
-+
-+	/* Adjust Request Field */
-+	DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1 = 0x0206,
-+	DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3 = 0x0207,
-+	DPCD_ADDRESS_ADJUST_REQUEST_POST_CURSOR2 = 0x020C,
-+
-+	/* Test Request Field */
-+	DPCD_ADDRESS_TEST_REQUEST = 0x0218,
-+	DPCD_ADDRESS_TEST_LINK_RATE = 0x0219,
-+	DPCD_ADDRESS_TEST_LANE_COUNT = 0x0220,
-+	DPCD_ADDRESS_TEST_PATTERN = 0x0221,
-+	DPCD_ADDRESS_TEST_MISC1 = 0x0232,
-+
-+	/* Phy Test Pattern Field */
-+	DPCD_ADDRESS_TEST_PHY_PATTERN = 0x0248,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0 = 0x0250,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_15_8 = 0x0251,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_23_16 = 0x0252,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_31_24 = 0x0253,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_39_32 = 0x0254,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_47_40 = 0x0255,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_55_48 = 0x0256,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_63_56 = 0x0257,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_71_64 = 0x0258,
-+	DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 = 0x0259,
-+
-+	/* Test Response Field*/
-+	DPCD_ADDRESS_TEST_RESPONSE = 0x0260,
-+
-+	/* Audio Test Pattern Field 1.2*/
-+	DPCD_ADDRESS_TEST_AUDIO_MODE = 0x0271,
-+	DPCD_ADDRESS_TEST_AUDIO_PATTERN_TYPE = 0x0272,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_1 = 0x0273,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_2 = 0x0274,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_3 = 0x0275,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_4 = 0x0276,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_5 = 0x0277,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_6 = 0x0278,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_7 = 0x0279,
-+	DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_8 = 0x027A,
-+
-+	/* Payload Table Status Field */
-+	DPCD_ADDRESS_PAYLOAD_TABLE_UPDATE_STATUS = 0x002C0,/*1.2*/
-+	DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT1 = 0x002C1,/*1.2*/
-+	DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT63 = 0x002FF,/*1.2*/
-+
-+	/* Source Device Specific Field */
-+	DPCD_ADDRESS_SOURCE_DEVICE_ID_START = 0x0300,
-+	DPCD_ADDRESS_SOURCE_DEVICE_ID_END = 0x0301,
-+	DPCD_ADDRESS_SOURCE_RESERVED_START = 0x030C,
-+	DPCD_ADDRESS_SOURCE_RESERVED_END = 0x03FF,
-+
-+	/* Sink Device Specific Field */
-+	DPCD_ADDRESS_SINK_DEVICE_ID_START = 0x0400,
-+	DPCD_ADDRESS_SINK_DEVICE_ID_END = 0x0402,
-+	DPCD_ADDRESS_SINK_DEVICE_STR_START = 0x0403,
-+	DPCD_ADDRESS_SINK_DEVICE_STR_END = 0x0408,
-+	DPCD_ADDRESS_SINK_REVISION_START = 0x409,
-+	DPCD_ADDRESS_SINK_REVISION_END = 0x40B,
-+
-+	/* Branch Device Specific Field */
-+	DPCD_ADDRESS_BRANCH_DEVICE_ID_START = 0x0500,
-+	DPCD_ADDRESS_BRANCH_DEVICE_ID_END = 0x0502,
-+	DPCD_ADDRESS_BRANCH_DEVICE_STR_START = 0x0503,
-+	DPCD_ADDRESS_BRANCH_DEVICE_STR_END = 0x0508,
-+
-+	DPCD_ADDRESS_POWER_STATE = 0x0600,
-+
-+	/* EDP related */
-+	DPCD_ADDRESS_EDP_REV = 0x0700,
-+	DPCD_ADDRESS_EDP_CAPABILITY = 0x0701,
-+	DPCD_ADDRESS_EDP_BACKLIGHT_ADJUST_CAP = 0x0702,
-+	DPCD_ADDRESS_EDP_GENERAL_CAP2 = 0x0703,
-+
-+	DPCD_ADDRESS_EDP_DISPLAY_CONTROL = 0x0720,
-+	DPCD_ADDRESS_EDP_BACKLIGHT_SET = 0x0721,
-+	DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_MSB = 0x0722,
-+	DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_LSB = 0x0723,
-+	DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT = 0x0724,
-+	DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MIN = 0x0725,
-+	DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MAX = 0x0726,
-+	DPCD_ADDRESS_EDP_BACKLIGHT_CONTROL_STATUS = 0x0727,
-+	DPCD_ADDRESS_EDP_BACKLIGHT_FREQ_SET = 0x0728,
-+	DPCD_ADDRESS_EDP_REVERVED = 0x0729,
-+	DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MSB = 0x072A,
-+	DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MID = 0x072B,
-+	DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_LSB = 0x072C,
-+	DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MSB = 0x072D,
-+	DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MID = 0x072E,
-+	DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_LSB = 0x072F,
-+
-+	DPCD_ADDRESS_EDP_DBC_MINIMUM_BRIGHTNESS_SET = 0x0732,
-+	DPCD_ADDRESS_EDP_DBC_MAXIMUM_BRIGHTNESS_SET = 0x0733,
-+
-+	/* Sideband MSG Buffers 1.2 */
-+	DPCD_ADDRESS_DOWN_REQ_START = 0x01000,
-+	DPCD_ADDRESS_DOWN_REQ_END = 0x011ff,
-+
-+	DPCD_ADDRESS_UP_REP_START = 0x01200,
-+	DPCD_ADDRESS_UP_REP_END = 0x013ff,
-+
-+	DPCD_ADDRESS_DOWN_REP_START = 0x01400,
-+	DPCD_ADDRESS_DOWN_REP_END = 0x015ff,
-+
-+	DPCD_ADDRESS_UP_REQ_START = 0x01600,
-+	DPCD_ADDRESS_UP_REQ_END = 0x017ff,
-+
-+	/* ESI (Event Status Indicator) Field 1.2 */
-+	DPCD_ADDRESS_SINK_COUNT_ESI = 0x02002,
-+	DPCD_ADDRESS_DEVICE_IRQ_ESI0 = 0x02003,
-+	DPCD_ADDRESS_DEVICE_IRQ_ESI1 = 0x02004,
-+	/*@todo move dpcd_address_Lane01Status back here*/
-+
-+	DPCD_ADDRESS_PSR_ERROR_STATUS = 0x2006,
-+	DPCD_ADDRESS_PSR_EVENT_STATUS = 0x2007,
-+	DPCD_ADDRESS_PSR_SINK_STATUS = 0x2008,
-+	DPCD_ADDRESS_PSR_DBG_REGISTER0 = 0x2009,
-+	DPCD_ADDRESS_PSR_DBG_REGISTER1 = 0x200A,
-+
-+	/* Travis specific addresses */
-+	DPCD_ADDRESS_TRAVIS_SINK_DEV_SEL = 0x5f0,
-+	DPCD_ADDRESS_TRAVIS_SINK_ACCESS_OFFSET	= 0x5f1,
-+	DPCD_ADDRESS_TRAVIS_SINK_ACCESS_REG = 0x5f2,
-+};
-+
-+enum dpcd_revision {
-+	DPCD_REV_10 = 0x10,
-+	DPCD_REV_11 = 0x11,
-+	DPCD_REV_12 = 0x12
-+};
-+
-+enum dp_pwr_state {
-+	DP_PWR_STATE_D0 = 1,/* direct HW translation! */
-+	DP_PWR_STATE_D3
-+};
-+
-+/* these are the types stored at DOWNSTREAMPORT_PRESENT */
-+enum dpcd_downstream_port_type {
-+	DOWNSTREAM_DP = 0,
-+	DOWNSTREAM_VGA,
-+	DOWNSTREAM_DVI_HDMI,
-+	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
-+};
-+
-+enum dpcd_link_test_patterns {
-+	LINK_TEST_PATTERN_NONE = 0,
-+	LINK_TEST_PATTERN_COLOR_RAMP,
-+	LINK_TEST_PATTERN_VERTICAL_BARS,
-+	LINK_TEST_PATTERN_COLOR_SQUARES
-+};
-+
-+enum dpcd_test_color_format {
-+	TEST_COLOR_FORMAT_RGB = 0,
-+	TEST_COLOR_FORMAT_YCBCR422,
-+	TEST_COLOR_FORMAT_YCBCR444
-+};
-+
-+enum dpcd_test_bit_depth {
-+	TEST_BIT_DEPTH_6 = 0,
-+	TEST_BIT_DEPTH_8,
-+	TEST_BIT_DEPTH_10,
-+	TEST_BIT_DEPTH_12,
-+	TEST_BIT_DEPTH_16
-+};
-+
-+/* PHY (encoder) test patterns
-+The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) */
-+enum dpcd_phy_test_patterns {
-+	PHY_TEST_PATTERN_NONE = 0,
-+	PHY_TEST_PATTERN_D10_2,
-+	PHY_TEST_PATTERN_SYMBOL_ERROR,
-+	PHY_TEST_PATTERN_PRBS7,
-+	PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
-+	PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE/* For DP1.2 only */
-+};
-+
-+enum dpcd_test_dyn_range {
-+	TEST_DYN_RANGE_VESA = 0,
-+	TEST_DYN_RANGE_CEA
-+};
-+
-+enum dpcd_audio_test_pattern {
-+	AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
-+	AUDIO_TEST_PATTERN_SAWTOOTH
-+};
-+
-+enum dpcd_audio_sampling_rate {
-+	AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
-+	AUDIO_SAMPLING_RATE_44_1KHZ,
-+	AUDIO_SAMPLING_RATE_48KHZ,
-+	AUDIO_SAMPLING_RATE_88_2KHZ,
-+	AUDIO_SAMPLING_RATE_96KHZ,
-+	AUDIO_SAMPLING_RATE_176_4KHZ,
-+	AUDIO_SAMPLING_RATE_192KHZ
-+};
-+
-+enum dpcd_audio_channels {
-+	AUDIO_CHANNELS_1 = 0,/* direct HW translation */
-+	AUDIO_CHANNELS_2,
-+	AUDIO_CHANNELS_3,
-+	AUDIO_CHANNELS_4,
-+	AUDIO_CHANNELS_5,
-+	AUDIO_CHANNELS_6,
-+	AUDIO_CHANNELS_7,
-+	AUDIO_CHANNELS_8,
-+
-+	AUDIO_CHANNELS_COUNT
-+};
-+
-+enum dpcd_audio_test_pattern_periods {
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
-+};
-+
-+/* This enum is for programming DPCD TRAINING_PATTERN_SET */
-+enum dpcd_training_patterns {
-+	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
-+	DPCD_TRAINING_PATTERN_1,
-+	DPCD_TRAINING_PATTERN_2,
-+	DPCD_TRAINING_PATTERN_3
-+};
-+
-+/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
-+It defines the possible PSR states. */
-+enum dpcd_psr_sink_states {
-+	PSR_SINK_STATE_INACTIVE = 0,
-+	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
-+	PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
-+	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
-+	PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
-+	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
-+};
-+
-+/* This enum defines the Panel's eDP revision at DPCD 700h
-+ * 00h = eDP v1.1 or lower
-+ * 01h = eDP v1.2
-+ * 02h = eDP v1.3 (PSR support starts here)
-+ * 03h = eDP v1.4
-+ * If unknown revision, treat as eDP v1.1, meaning least functionality set.
-+ * This enum has values matched to eDP spec, thus values should not change.
-+ */
-+enum dpcd_edp_revision {
-+	DPCD_EDP_REVISION_EDP_V1_1 = 0,
-+	DPCD_EDP_REVISION_EDP_V1_2 = 1,
-+	DPCD_EDP_REVISION_EDP_V1_3 = 2,
-+	DPCD_EDP_REVISION_EDP_V1_4 = 3,
-+	DPCD_EDP_REVISION_EDP_UNKNOWN = DPCD_EDP_REVISION_EDP_V1_1,
-+};
-+
-+union dpcd_rev {
-+	struct {
-+		uint8_t MINOR:4;
-+		uint8_t MAJOR:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union max_lane_count {
-+	struct {
-+		uint8_t MAX_LANE_COUNT:5;
-+		uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
-+		uint8_t TPS3_SUPPORTED:1;
-+		uint8_t ENHANCED_FRAME_CAP:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union max_down_spread {
-+	struct {
-+		uint8_t MAX_DOWN_SPREAD:1;
-+		uint8_t RESERVED:5;
-+		uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
-+		uint8_t RESERVED1:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union mstm_cap {
-+	struct {
-+		uint8_t MST_CAP:1;
-+		uint8_t RESERVED:7;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union mstm_cntl {
-+	struct {
-+		uint8_t MST_EN:1;
-+		uint8_t UP_REQ_EN:1;
-+		uint8_t UPSTREAM_IS_SRC:1;
-+		uint8_t RESERVED:5;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_count_set {
-+	struct {
-+		uint8_t LANE_COUNT_SET:5;
-+		uint8_t POST_LT_ADJ_REQ_GRANTED:1;
-+		uint8_t RESERVED:1;
-+		uint8_t ENHANCED_FRAMING:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* for DPCD_ADDRESS_I2C_SPEED_CNTL_CAP
-+ * and DPCD_ADDRESS_I2C_SPEED_CNTL
-+ */
-+union i2c_speed {
-+	struct {
-+		uint8_t _1KBPS:1;
-+		uint8_t _5KBPS:1;
-+		uint8_t _10KBPS:1;
-+		uint8_t _100KBPS:1;
-+		uint8_t _400KBPS:1;
-+		uint8_t _1MBPS:1;
-+		uint8_t reserved:2;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union payload_table_update_status {
-+	struct {
-+		uint8_t VC_PAYLOAD_TABLE_UPDATED:1;
-+		uint8_t ACT_HANDLED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union device_irq_esi_0 {
-+	struct {
-+		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
-+		uint8_t AUTOMATED_TEST_REQUEST:1;
-+		uint8_t CP_IRQ:1;
-+		uint8_t MCCS_IRQ:1;
-+		uint8_t DOWN_REP_MSG_RDY:1;
-+		uint8_t UP_REQ_MSG_RDY:1;
-+		uint8_t SINK_SPECIFIC_IRQ:1;
-+		uint8_t RESERVED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_status {
-+	struct {
-+		uint8_t CR_DONE_0:1;
-+		uint8_t CHANNEL_EQ_DONE_0:1;
-+		uint8_t SYMBOL_LOCKED_0:1;
-+		uint8_t RESERVED0:1;
-+		uint8_t CR_DONE_1:1;
-+		uint8_t CHANNEL_EQ_DONE_1:1;
-+		uint8_t SYMBOL_LOCKED_1:1;
-+		uint8_t RESERVED_1:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union device_service_irq {
-+	struct {
-+		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
-+		uint8_t AUTOMATED_TEST:1;
-+		uint8_t CP_IRQ:1;
-+		uint8_t MCCS_IRQ:1;
-+		uint8_t DOWN_REP_MSG_RDY:1;
-+		uint8_t UP_REQ_MSG_RDY:1;
-+		uint8_t SINK_SPECIFIC:1;
-+		uint8_t reserved:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union downstream_port {
-+	struct {
-+		uint8_t PRESENT:1;
-+		uint8_t TYPE:2;
-+		uint8_t FORMAT_CONV:1;
-+		uint8_t DETAILED_CAPS:1;
-+		uint8_t RESERVED:3;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union sink_count {
-+	struct {
-+		uint8_t SINK_COUNT:6;
-+		uint8_t CPREADY:1;
-+		uint8_t RESERVED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_align_status_updated {
-+	struct {
-+		uint8_t INTERLANE_ALIGN_DONE:1;
-+		uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
-+		uint8_t RESERVED:4;
-+		uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
-+		uint8_t LINK_STATUS_UPDATED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_adjust {
-+	struct {
-+		uint8_t VOLTAGE_SWING_LANE:2;
-+		uint8_t PRE_EMPHASIS_LANE:2;
-+		uint8_t RESERVED:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* Automated test structures */
-+union test_request {
-+	struct {
-+		uint8_t LINK_TRAINING:1;
-+		uint8_t LINK_TEST_PATTERN:1;
-+		uint8_t EDID_READ:1;
-+		uint8_t PHY_TEST_PATTERN:1;
-+		uint8_t AUDIO_TEST_PATTERN:1;
-+		uint8_t AUDIO_TEST_NO_VIDEO:1;
-+		uint8_t RESERVED:1;
-+		uint8_t TEST_STEREO_3D:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union test_response {
-+	struct {
-+		uint8_t ACK:1;
-+		uint8_t NO_ACK:1;
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union link_test_pattern {
-+	struct {
-+		uint8_t PATTERN:2;/*DpcdLinkTestPatterns*/
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union test_misc {
-+	struct dpcd_test_misc_bits {
-+		uint8_t SYNC_CLOCK:1;
-+		uint8_t CLR_FORMAT:2;/*DpcdTestColorFormat*/
-+		uint8_t DYN_RANGE:1;/*DpcdTestDynRange*/
-+		uint8_t YCBCR:1;/*DpcdTestYCbCrStandard*/
-+		uint8_t BPC:3;/*DpcdTestBitDepth*/
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union phy_test_pattern {
-+	struct {
-+		/* This field is 2 bits for DP1.1 and 3 bits for DP1.2.*/
-+		uint8_t PATTERN:3;
-+		uint8_t RESERVED:5;/* BY spec, bit7:2 is 0 for DP1.1.*/
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union audio_test_mode {
-+	struct {
-+		uint8_t SAMPLING_RATE:4;
-+		uint8_t CHANNEL_COUNT:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union audio_tes_tpattern_period {
-+	struct {
-+		uint8_t PATTERN_PERIOD:4;
-+		uint8_t RESERVED:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+struct audio_test_pattern_type {
-+	uint8_t value;
-+};
-+
-+union dpcd_training_pattern {
-+	struct {
-+		uint8_t TRAINING_PATTERN_SET:2;
-+		uint8_t LINK_QUAL_PATTERN_SET:2;
-+		uint8_t RECOVERED_CLOCK_OUT_EN:1;
-+		uint8_t SCRAMBLING_DISABLE:1;
-+		uint8_t RESERVED:2;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* Training Lane is used to configure downstream DP device's voltage swing
-+and pre-emphasis levels*/
-+/* The DPCD addresses are from 0x103 to 0x106*/
-+union dpcd_training_lane {
-+	struct {
-+		uint8_t VOLTAGE_SWING_SET:2;
-+		uint8_t MAX_SWING_REACHED:1;
-+		uint8_t PRE_EMPHASIS_SET:2;
-+		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
-+		uint8_t RESERVED:2;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/*Training Lane Set 2 is used to configure downstream DP device's
-+post cursor 2 level of Training Pattern 2 or 3*/
-+/* The DPCD addresses are 0x10F (TRAINING_LANE0_1_SET2)
-+and 0x110 (TRAINING_LANE2_3_SET2)*/
-+union dpcd_training_lane_set2 {
-+	struct {
-+		uint8_t POST_CURSOR2_SET:2;
-+		uint8_t MAX_POST_CURSOR2_REACHED:1;
-+		uint8_t RESERVED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dpcd_psr_configuration {
-+	struct {
-+		uint8_t ENABLE:1;
-+		uint8_t TRANSMITTER_ACTIVE_IN_PSR:1;
-+		uint8_t CRC_VERIFICATION:1;
-+		uint8_t FRAME_CAPTURE_INDICATION:1;
-+		uint8_t LINE_CAPTURE_INDICATION:1;
-+		uint8_t IRQ_HPD_WITH_CRC_ERROR:1;
-+		uint8_t RESERVED:2;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union psr_error_status {
-+	struct {
-+		uint8_t LINK_CRC_ERROR:1;
-+		uint8_t RFB_STORAGE_ERROR:1;
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union psr_event_status_ind {
-+	struct {
-+		uint8_t SINK_PSR_CAP_CHANGE:1;
-+		uint8_t RESERVED:7;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union psr_sink_psr_status {
-+	struct {
-+		uint8_t SINK_SELF_REFRESH_STATUS:3;
-+		uint8_t RESERVED:5;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* EDP related 0x701 */
-+union edp_generial_cap1 {
-+	struct {
-+		uint8_t TCON_BACKLIGHT_ADJUSTMENT_CAPABLE:1;
-+		uint8_t BACKLIGHT_PIN_ENABLE_CAPABLE:1;
-+		uint8_t BACKLIGHT_AUX_ENABLE_CAPABLE:1;
-+		uint8_t PANEL_SELFTEST_PIN_ENABLE_CAPABLE:1;
-+		uint8_t BACKLIGHT_SELFTEST_AUX_ENABLE_CAPABLE:1;
-+		uint8_t FRC_ENABLE_CAPABLE:1;
-+		uint8_t COLOR_ENGINE_CAPABLE:1;
-+		/*bit 7, pane can be controlled by 0x600*/
-+		uint8_t SET_POWER_CAPABLE:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* TMDS-converter related */
-+union dwnstream_port_caps_byte0 {
-+	struct {
-+		uint8_t DWN_STRM_PORTX_TYPE:3;
-+		uint8_t DWN_STRM_PORTX_HPD:1;
-+		uint8_t RESERVERD:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
-+enum dpcd_downstream_port_detailed_type {
-+	DOWN_STREAM_DETAILED_DP = 0,
-+	DOWN_STREAM_DETAILED_VGA,
-+	DOWN_STREAM_DETAILED_DVI,
-+	DOWN_STREAM_DETAILED_HDMI,
-+	DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
-+	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
-+};
-+
-+union dwnstream_port_caps_byte2 {
-+	struct {
-+		uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dp_downstream_port_present {
-+	uint8_t byte;
-+	struct {
-+		uint8_t PORT_PRESENT:1;
-+		uint8_t PORT_TYPE:2;
-+		uint8_t FMT_CONVERSION:1;
-+		uint8_t DETAILED_CAPS:1;
-+		uint8_t RESERVED:3;
-+	} fields;
-+};
-+
-+
-+union dwnstream_port_caps_byte3_dvi {
-+	struct {
-+		uint8_t RESERVED1:1;
-+		uint8_t DUAL_LINK:1;
-+		uint8_t HIGH_COLOR_DEPTH:1;
-+		uint8_t RESERVED2:5;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dwnstream_port_caps_byte3_hdmi {
-+	struct {
-+		uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
-+		uint8_t RESERVED:7;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/*4-byte structure for detailed capabilities of a down-stream port
-+(DP-to-TMDS converter).*/
-+union dwnstream_portx_caps {
-+	struct {
-+		union dwnstream_port_caps_byte0 byte0;
-+		uint8_t max_tmds_clk;/* byte1 */
-+		union dwnstream_port_caps_byte2 byte2;
-+
-+		union {
-+			union dwnstream_port_caps_byte3_dvi byte_dvi;
-+			union dwnstream_port_caps_byte3_hdmi byte_hdmi;
-+		} byte3;
-+	} bytes;
-+	uint8_t raw[4];
-+};
-+
-+union sink_status {
-+	struct {
-+		uint8_t RX_PORT0_STATUS:1;
-+		uint8_t RX_PORT1_STATUS:1;
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/*6-byte structure corresponding to 6 registers (200h-205h)
-+read during handling of HPD-IRQ*/
-+union hpd_irq_data {
-+	struct {
-+		union sink_count sink_cnt;/* 200h */
-+		union device_service_irq device_service_irq;/* 201h */
-+		union lane_status lane01_status;/* 202h */
-+		union lane_status lane23_status;/* 203h */
-+		union lane_align_status_updated lane_status_updated;/* 204h */
-+		union sink_status sink_status;
-+	} bytes;
-+	uint8_t raw[6];
-+};
-+
-+union down_stream_port_count {
-+	struct {
-+		uint8_t DOWN_STR_PORT_COUNT:4;
-+		uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
-+		/*Bit 6 = MSA_TIMING_PAR_IGNORED
-+		0 = Sink device requires the MSA timing parameters
-+		1 = Sink device is capable of rendering incoming video
-+		 stream without MSA timing parameters*/
-+		uint8_t IGNORE_MSA_TIMING_PARAM:1;
-+		/*Bit 7 = OUI Support
-+		0 = OUI not supported
-+		1 = OUI supported
-+		(OUI and Device Identification mandatory for DP 1.2)*/
-+		uint8_t OUI_SUPPORT:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union down_spread_ctrl {
-+	struct {
-+		uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
-+	/* Bits 4 = SPREAD_AMP. Spreading amplitude
-+	0 = Main link signal is not downspread
-+	1 = Main link signal is downspread <= 0.5%
-+	with frequency in the range of 30kHz ~ 33kHz*/
-+		uint8_t SPREAD_AMP:1;
-+		uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
-+	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
-+	0 = Source device will send valid data for the MSA Timing Params
-+	1 = Source device may send invalid data for these MSA Timing Params*/
-+		uint8_t IGNORE_MSA_TIMING_PARAM:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dpcd_edp_config {
-+	struct {
-+		uint8_t PANEL_MODE_EDP:1;
-+		uint8_t FRAMING_CHANGE_ENABLE:1;
-+		uint8_t RESERVED:5;
-+		uint8_t PANEL_SELF_TEST_ENABLE:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+struct dp_device_vendor_id {
-+	uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
-+	uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
-+};
-+
-+struct dp_sink_hw_fw_revision {
-+	uint8_t ieee_hw_rev;
-+	uint8_t ieee_fw_rev[2];
-+};
-+
-+/*DPCD register of DP receiver capability field bits-*/
-+union edp_configuration_cap {
-+	struct {
-+		uint8_t ALT_SCRAMBLER_RESET:1;
-+		uint8_t FRAMING_CHANGE:1;
-+		uint8_t RESERVED:1;
-+		uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
-+		uint8_t RESERVED2:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union psr_capabilities {
-+	struct {
-+		uint8_t EXIT_LT_NOT_REQ:1;
-+		uint8_t RFB_SETUP_TIME:3;
-+		uint8_t RESERVED:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+#endif /* __DAL_DPCD_DEFS_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dvo_interface.h b/drivers/gpu/drm/amd/dal/include/dvo_interface.h
-new file mode 100644
-index 0000000..58d2c6f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/dvo_interface.h
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DVO_INTERFACE_H__
-+#define __DAL_DVO_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+
-+struct dvo;
-+
-+enum gpio_result dal_dvo_open(
-+	struct dvo *dvo,
-+	enum gpio_mode mode);
-+
-+enum gpio_result dal_dvo_get_value(
-+	const struct dvo *dvo,
-+	uint32_t *value);
-+
-+enum gpio_result dal_dvo_set_value(
-+	const struct dvo *dvo,
-+	uint32_t value);
-+
-+void dal_dvo_close(
-+	struct dvo *dvo);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_interface.h b/drivers/gpu/drm/amd/dal/include/encoder_interface.h
-new file mode 100644
-index 0000000..5fbf816
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/encoder_interface.h
-@@ -0,0 +1,278 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of enc software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and enc permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ENCODER_INTERFACE_H__
-+#define __DAL_ENCODER_INTERFACE_H__
-+
-+#include "encoder_types.h"
-+#include "adapter_service_interface.h"
-+#include "fixed31_32.h"
-+
-+enum encoder_result {
-+	ENCODER_RESULT_OK,
-+	ENCODER_RESULT_ERROR,
-+	ENCODER_RESULT_NOBANDWIDTH,
-+	ENCODER_RESULT_SINKCONNECTIVITYCHANGED,
-+};
-+
-+struct encoder_init_data {
-+	struct adapter_service *adapter_service;
-+	enum channel_id channel;
-+	struct graphics_object_id connector;
-+	enum hpd_source_id hpd_source;
-+	/* TODO: in DAL2, here was pointer to EventManagerInterface */
-+	struct graphics_object_id encoder;
-+	struct dc_context *ctx;
-+};
-+
-+/* forward declaration */
-+struct encoder;
-+
-+struct encoder *dal_encoder_create(
-+	const struct encoder_init_data *init_data);
-+
-+/* access graphics object base */
-+const struct graphics_object_id dal_encoder_get_graphics_object_id(
-+	const struct encoder *enc);
-+
-+/*
-+ * Signal types support
-+ */
-+uint32_t dal_encoder_enumerate_input_signals(
-+	const struct encoder *enc);
-+uint32_t dal_encoder_enumerate_output_signals(
-+	const struct encoder *enc);
-+bool dal_encoder_is_input_signal_supported(
-+	const struct encoder *enc,
-+	enum signal_type signal);
-+bool dal_encoder_is_output_signal_supported(
-+	const struct encoder *enc,
-+	enum signal_type signal);
-+void dal_encoder_set_input_signals(
-+	struct encoder *enc,
-+	uint32_t signals);
-+void dal_encoder_set_output_signals(
-+	struct encoder *enc,
-+	uint32_t signals);
-+
-+/*
-+ * Programming interface
-+ */
-+/* perform power-up sequence (boot up, resume, recovery) */
-+enum encoder_result dal_encoder_power_up(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* perform power-down (shut down, stand-by */
-+enum encoder_result dal_encoder_power_down(
-+	struct encoder *enc,
-+	const struct encoder_output *output);
-+/* setup encoder block (DIG, DVO, DAC), does not enables encoder */
-+enum encoder_result dal_encoder_setup(
-+	struct encoder *enc,
-+	const struct encoder_output *output);
-+/* activate transmitter,
-+ * do preparation before enables the actual stream output */
-+enum encoder_result dal_encoder_pre_enable_output(
-+	struct encoder *enc,
-+	const struct encoder_pre_enable_output_param *param);
-+/* activate transmitter, enables actual stream output */
-+enum encoder_result dal_encoder_enable_output(
-+	struct encoder *enc,
-+	const struct encoder_output *output);
-+/* deactivate transmitter, disables stream output */
-+enum encoder_result dal_encoder_disable_output(
-+	struct encoder *enc,
-+	const struct encoder_output *output);
-+/* output blank data,
-+ *prevents output of the actual surface data on active transmitter */
-+enum encoder_result dal_encoder_blank(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* stop sending blank data,
-+ * output the actual surface data on active transmitter */
-+enum encoder_result dal_encoder_unblank(
-+	struct encoder *enc,
-+	const struct encoder_unblank_param *param);
-+/* setup stereo signal from given controller */
-+enum encoder_result dal_encoder_setup_stereo(
-+	struct encoder *enc,
-+	const struct encoder_3d_setup *setup);
-+/* enable HSync/VSync output from given controller */
-+enum encoder_result dal_encoder_enable_sync_output(
-+	struct encoder *enc,
-+	enum sync_source src);
-+/* disable HSync/VSync output */
-+enum encoder_result dal_encoder_disable_sync_output(
-+	struct encoder *enc);
-+/* action of encoder before DDC transaction */
-+enum encoder_result dal_encoder_pre_ddc(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* action of encoder after DDC transaction */
-+enum encoder_result dal_encoder_post_ddc(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* CRT DDC EDID polling interrupt interface */
-+enum encoder_result dal_encoder_update_implementation(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* set test pattern signal */
-+enum encoder_result dal_encoder_set_dp_phy_pattern(
-+	struct encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param);
-+
-+void dal_encoder_release_hw(struct encoder *enc);
-+/*
-+ * Information interface
-+ */
-+/* check whether sink is present based on SENSE detection,
-+ * analog encoders will return true */
-+bool dal_encoder_is_sink_present(
-+	struct encoder *enc,
-+	struct graphics_object_id downstream);
-+/* detect load on the sink,
-+ * for analog signal,
-+ * load detection will be called for the specified signal */
-+enum signal_type dal_encoder_detect_load(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* detect output sink type,
-+ * for digital perform sense detection,
-+ * for analog return encoder's signal type */
-+enum signal_type dal_encoder_detect_sink(
-+	struct encoder *enc,
-+	struct graphics_object_id downstream);
-+/* get transmitter id */
-+enum transmitter dal_encoder_get_transmitter(
-+	const struct encoder *enc);
-+/*  */
-+enum transmitter dal_encoder_get_paired_transmitter(
-+	const struct encoder *enc);
-+/*  */
-+enum physical_phy_id dal_encoder_get_phy(
-+	const struct encoder *enc);
-+/*  */
-+enum physical_phy_id dal_encoder_get_paired_phy(
-+	const struct encoder *enc);
-+/* reports if the encoder supports given link settings */
-+bool dal_encoder_is_link_settings_supported(
-+	struct encoder *enc,
-+	const struct link_settings *link_settings);
-+/* options and features supported by encoder */
-+struct encoder_feature_support dal_encoder_get_supported_features(
-+	const struct encoder *enc);
-+/* reports list of supported stream engines */
-+union supported_stream_engines dal_encoder_get_supported_stream_engines(
-+	const struct encoder *enc);
-+/* reports preferred stream engine */
-+enum engine_id dal_encoder_get_preferred_stream_engine(
-+	const struct encoder *enc);
-+/* reports whether clock source can be used with enc encoder */
-+bool dal_encoder_is_clock_source_supported(
-+	const struct encoder *enc,
-+	enum clock_source_id clock_source);
-+/* check encoder capabilities to confirm
-+ * specified timing is in the encoder limits
-+ * when outputting certain signal */
-+enum encoder_result dal_encoder_validate_output(
-+	struct encoder *enc,
-+	const struct encoder_output *output);
-+/* retrieves sync source which outputs VSync signal from encoder */
-+enum sync_source dal_encoder_get_vsync_output_source(
-+	const struct encoder *enc);
-+/*
-+ * Adjustments
-+ */
-+/* update AVI info frame */
-+void dal_encoder_update_info_frame(
-+	struct encoder *enc,
-+	const struct encoder_info_frame_param *param);
-+/*  */
-+void dal_encoder_stop_info_frame(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/*  */
-+enum encoder_result dal_encoder_set_lcd_backlight_level(
-+	struct encoder *enc,
-+	uint32_t level);
-+/* backlight control interface */
-+enum encoder_result dal_encoder_backlight_control(
-+	struct encoder *enc,
-+	bool enable);
-+/*
-+ * DP MST programming
-+ */
-+/* update payload slot allocation for each DP MST stream */
-+enum encoder_result dal_encoder_update_mst_alloc_table(
-+	struct encoder *enc,
-+	const struct dp_mst_stream_allocation_table *table,
-+	bool is_removal);
-+/* enable virtual channel stream with throttled value X.Y */
-+enum encoder_result dal_encoder_enable_stream(
-+	struct encoder *enc,
-+	enum engine_id engine,
-+	struct fixed31_32 throttled_vcp_size);
-+/* disable virtual channel stream */
-+enum encoder_result dal_encoder_disable_stream(
-+	struct encoder *enc,
-+	enum engine_id engine);
-+void dal_encoder_set_multi_path(struct encoder *enc, bool is_multi_path);
-+/*
-+ * Test harness
-+ */
-+/* check whether Test Pattern enabled */
-+bool dal_encoder_is_test_pattern_enabled(
-+	struct encoder *enc,
-+	enum engine_id engine);
-+/* set lane parameters */
-+enum encoder_result dal_encoder_set_lane_settings(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx,
-+	const struct link_training_settings *link_settings);
-+/* get lane parameters */
-+enum encoder_result dal_encoder_get_lane_settings(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx,
-+	struct link_training_settings *link_settings);
-+/* enable master clock of HPD interrupt */
-+void dal_encoder_enable_hpd(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+/* disable all HPD interrupts */
-+void dal_encoder_disable_hpd(
-+	struct encoder *enc,
-+	const struct encoder_context *ctx);
-+
-+/* get current HW state - used for optimization code path only */
-+enum clock_source_id dal_encoder_get_active_clock_source(
-+	const struct encoder *enc);
-+enum engine_id dal_encoder_get_active_engine(
-+	const struct encoder *enc);
-+
-+/* destroy encoder instance */
-+void dal_encoder_destroy(
-+	struct encoder **ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_types.h b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-new file mode 100644
-index 0000000..2897a1d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-@@ -0,0 +1,216 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ENCODER_TYPES_H__
-+#define __DAL_ENCODER_TYPES_H__
-+
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+#include "hw_sequencer_types.h"
-+#include "link_service_types.h"
-+
-+struct encoder_context {
-+	/*
-+	 * HW programming context
-+	 */
-+	/* DIG id. Also used as AC context */
-+	enum engine_id engine;
-+	/* DDC line */
-+	enum channel_id channel;
-+	/* HPD line */
-+	enum hpd_source_id hpd_source;
-+	/*
-+	 * ASIC Control (VBIOS) context
-+	 */
-+	/* encoder output signal */
-+	enum signal_type signal;
-+	/* native connector id */
-+	struct graphics_object_id connector;
-+	/* downstream object (can be connector or downstream encoder) */
-+	struct graphics_object_id downstream;
-+};
-+
-+union encoder_flags {
-+	struct {
-+		/* enable audio (DP/eDP only) */
-+		uint32_t ENABLE_AUDIO:1;
-+		/* coherency */
-+		uint32_t COHERENT:1;
-+		/* delay after Pixel Format change before enable transmitter */
-+		uint32_t DELAY_AFTER_PIXEL_FORMAT_CHANGE:1;
-+		/* by default, do not turn off VCC when disabling output */
-+		uint32_t TURN_OFF_VCC:1;
-+		/* by default, do wait for HPD low after turn of panel VCC */
-+		uint32_t NO_WAIT_FOR_HPD_LOW:1;
-+		/* slow DP panels don't reset internal fifo */
-+		uint32_t VID_STREAM_DIFFER_TO_SYNC:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct encoder_info_packet {
-+	bool valid;
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t hb3;
-+	uint8_t sb[28];
-+};
-+
-+struct encoder_info_frame {
-+	/* auxiliary video information */
-+	struct encoder_info_packet avi;
-+	struct encoder_info_packet gamut;
-+	struct encoder_info_packet vendor;
-+	/* source product description */
-+	struct encoder_info_packet spd;
-+	/* video stream configuration */
-+	struct encoder_info_packet vsc;
-+};
-+
-+struct encoder_info_frame_param {
-+	struct encoder_info_frame packets;
-+	struct encoder_context enc_ctx;
-+};
-+
-+/*TODO: cleanup pending encoder cleanup*/
-+struct encoder_output {
-+	/* encoder AC & HW programming context */
-+	struct encoder_context enc_ctx;
-+	/* requested timing */
-+	struct hw_crtc_timing crtc_timing;
-+	/* clock source id (PLL or external) */
-+	enum clock_source_id clock_source;
-+	/* link settings (DP/eDP only) */
-+	struct link_settings link_settings;
-+	/* info frame packets */
-+	struct encoder_info_frame info_frame;
-+	/* timing validation (HDMI only) */
-+	uint32_t max_tmds_clk_from_edid_in_mhz;
-+	/* edp panel mode */
-+	enum dp_panel_mode dp_panel_mode;
-+	/* delay in milliseconds after powering up DP receiver (DP/eDP only) */
-+	uint32_t delay_after_dp_receiver_power_up;
-+	/* various flags for features and workarounds */
-+	union encoder_flags flags;
-+	/* delay after pixel format change */
-+	uint32_t delay_after_pixel_format_change;
-+	/* controller id */
-+	enum controller_id controller;
-+	/* maximum supported deep color depth for HDMI */
-+	enum dc_color_depth max_hdmi_deep_color;
-+	/* maximum supported pixel clock for HDMI */
-+	uint32_t max_hdmi_pixel_clock;
-+};
-+
-+struct encoder_pre_enable_output_param {
-+	struct hw_crtc_timing crtc_timing;
-+	struct link_settings link_settings;
-+	struct encoder_context enc_ctx;
-+};
-+
-+struct encoder_unblank_param {
-+	struct hw_crtc_timing crtc_timing;
-+	struct link_settings link_settings;
-+	enum signal_type signal;
-+};
-+
-+/*
-+ * @brief
-+ * Parameters to setup stereo 3D mode in Encoder:
-+ * - source: used for side-band stereo sync (DVO/DAC);
-+ * - engine_id: defines engine for this Encoder;
-+ * - enable_inband: in-band stereo sync should be enabled;
-+ * - enable_sideband: side-band stereo sync should be enabled.
-+ */
-+struct encoder_3d_setup {
-+	enum engine_id engine;
-+	enum sync_source source;
-+	union {
-+		struct {
-+			uint32_t SETUP_SYNC_SOURCE:1;
-+			uint32_t ENABLE_INBAND:1;
-+			uint32_t ENABLE_SIDEBAND:1;
-+			uint32_t DISABLE_INBAND:1;
-+			uint32_t DISABLE_SIDEBAND:1;
-+		} bits;
-+		uint32_t raw;
-+	} flags;
-+};
-+
-+struct encoder_set_dp_phy_pattern_param {
-+	enum dp_test_pattern dp_phy_pattern;
-+	const uint8_t *custom_pattern;
-+	uint32_t custom_pattern_size;
-+	enum dp_panel_mode dp_panel_mode;
-+};
-+
-+struct encoder_feature_support {
-+	union {
-+		struct {
-+			/* 1 - external encoder; 0 - internal encoder */
-+			uint32_t EXTERNAL_ENCODER:1;
-+			uint32_t ANALOG_ENCODER:1;
-+			uint32_t STEREO_SYNC:1;
-+			/* check the DDC data pin
-+			 * when performing DP Sink detection */
-+			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
-+			/* CPLIB authentication
-+			 * for external DP chip supported */
-+			uint32_t CPLIB_DP_AUTHENTICATION:1;
-+			uint32_t IS_HBR2_CAPABLE:1;
-+			uint32_t IS_HBR2_VALIDATED:1;
-+			uint32_t IS_TPS3_CAPABLE:1;
-+			uint32_t IS_AUDIO_CAPABLE:1;
-+			uint32_t IS_VCE_SUPPORTED:1;
-+			uint32_t IS_CONVERTER:1;
-+			uint32_t IS_Y_ONLY_CAPABLE:1;
-+			uint32_t IS_YCBCR_CAPABLE:1;
-+		} bits;
-+		uint32_t raw;
-+	} flags;
-+	/* maximum supported deep color depth */
-+	enum dc_color_depth max_deep_color;
-+	/* maximum supported clock */
-+	uint32_t max_pixel_clock;
-+};
-+
-+enum dig_encoder_mode {
-+	DIG_ENCODER_MODE_DP,
-+	DIG_ENCODER_MODE_LVDS,
-+	DIG_ENCODER_MODE_DVI,
-+	DIG_ENCODER_MODE_HDMI,
-+	DIG_ENCODER_MODE_SDVO,
-+	DIG_ENCODER_MODE_DP_WITH_AUDIO,
-+	DIG_ENCODER_MODE_DP_MST,
-+
-+	/* direct HW translation ! */
-+	DIG_ENCODER_MODE_TV = 13,
-+	DIG_ENCODER_MODE_CV,
-+	DIG_ENCODER_MODE_CRT
-+};
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed31_32.h b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-new file mode 100644
-index 0000000..507f9f6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-@@ -0,0 +1,389 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_FIXED31_32_H__
-+#define __DAL_FIXED31_32_H__
-+
-+/*
-+ * @brief
-+ * Arithmetic operations on real numbers
-+ * represented as fixed-point numbers.
-+ * There are: 1 bit for sign,
-+ * 31 bit for integer part,
-+ * 32 bits for fractional part.
-+ *
-+ * @note
-+ * Currently, overflows and underflows are asserted;
-+ * no special result returned.
-+ */
-+
-+struct fixed31_32 {
-+	int64_t value;
-+};
-+
-+/*
-+ * @brief
-+ * Useful constants
-+ */
-+
-+static const struct fixed31_32 dal_fixed31_32_zero = { 0 };
-+static const struct fixed31_32 dal_fixed31_32_epsilon = { 1LL };
-+static const struct fixed31_32 dal_fixed31_32_half = { 0x80000000LL };
-+static const struct fixed31_32 dal_fixed31_32_one = { 0x100000000LL };
-+
-+static const struct fixed31_32 dal_fixed31_32_pi = { 13493037705LL };
-+static const struct fixed31_32 dal_fixed31_32_two_pi = { 26986075409LL };
-+static const struct fixed31_32 dal_fixed31_32_e = { 11674931555LL };
-+static const struct fixed31_32 dal_fixed31_32_ln2 = { 2977044471LL };
-+static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL };
-+
-+/*
-+ * @brief
-+ * Initialization routines
-+ */
-+
-+/*
-+ * @brief
-+ * result = numerator / denominator
-+ */
-+struct fixed31_32 dal_fixed31_32_from_fraction(
-+	int64_t numerator,
-+	int64_t denominator);
-+
-+/*
-+ * @brief
-+ * result = arg
-+ */
-+struct fixed31_32 dal_fixed31_32_from_int(
-+	int64_t arg);
-+
-+/*
-+ * @brief
-+ * Unary operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = -arg
-+ */
-+struct fixed31_32 dal_fixed31_32_neg(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = abs(arg) := (arg >= 0) ? arg : -arg
-+ */
-+struct fixed31_32 dal_fixed31_32_abs(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Binary relational operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg1 < arg2
-+ */
-+bool dal_fixed31_32_lt(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 <= arg2
-+ */
-+bool dal_fixed31_32_le(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 == arg2
-+ */
-+bool dal_fixed31_32_eq(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_min(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1
-+ */
-+struct fixed31_32 dal_fixed31_32_max(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ *          | min_value, when arg <= min_value
-+ * result = | arg, when min_value < arg < max_value
-+ *          | max_value, when arg >= max_value
-+ */
-+struct fixed31_32 dal_fixed31_32_clamp(
-+	struct fixed31_32 arg,
-+	struct fixed31_32 min_value,
-+	struct fixed31_32 max_value);
-+
-+/*
-+ * @brief
-+ * Binary shift operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg << shift
-+ */
-+struct fixed31_32 dal_fixed31_32_shl(
-+	struct fixed31_32 arg,
-+	uint8_t shift);
-+
-+/*
-+ * @brief
-+ * result = arg >> shift
-+ */
-+struct fixed31_32 dal_fixed31_32_shr(
-+	struct fixed31_32 arg,
-+	uint8_t shift);
-+
-+/*
-+ * @brief
-+ * Binary additive operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg1 + arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_add(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 - arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_sub_int(
-+	struct fixed31_32 arg1,
-+	int32_t arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 - arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_sub(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * Binary multiplicative operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg1 * arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_mul_int(
-+	struct fixed31_32 arg1,
-+	int32_t arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 * arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_mul(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = square(arg) := arg * arg
-+ */
-+struct fixed31_32 dal_fixed31_32_sqr(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = arg1 / arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_div_int(
-+	struct fixed31_32 arg1,
-+	int64_t arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 / arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_div(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * Reciprocal function
-+ */
-+
-+/*
-+ * @brief
-+ * result = reciprocal(arg) := 1 / arg
-+ *
-+ * @note
-+ * No special actions taken in case argument is zero.
-+ */
-+struct fixed31_32 dal_fixed31_32_recip(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Trigonometric functions
-+ */
-+
-+/*
-+ * @brief
-+ * result = sinc(arg) := sin(arg) / arg
-+ *
-+ * @note
-+ * Argument specified in radians,
-+ * internally it's normalized to [-2pi...2pi] range.
-+ */
-+struct fixed31_32 dal_fixed31_32_sinc(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = sin(arg)
-+ *
-+ * @note
-+ * Argument specified in radians,
-+ * internally it's normalized to [-2pi...2pi] range.
-+ */
-+struct fixed31_32 dal_fixed31_32_sin(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = cos(arg)
-+ *
-+ * @note
-+ * Argument specified in radians
-+ * and should be in [-2pi...2pi] range -
-+ * passing arguments outside that range
-+ * will cause incorrect result!
-+ */
-+struct fixed31_32 dal_fixed31_32_cos(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Transcendent functions
-+ */
-+
-+/*
-+ * @brief
-+ * result = exp(arg)
-+ *
-+ * @note
-+ * Currently, function is verified for abs(arg) <= 1.
-+ */
-+struct fixed31_32 dal_fixed31_32_exp(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = log(arg)
-+ *
-+ * @note
-+ * Currently, abs(arg) should be less than 1.
-+ * No normalization is done.
-+ * Currently, no special actions taken
-+ * in case of invalid argument(s). Take care!
-+ */
-+struct fixed31_32 dal_fixed31_32_log(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Power function
-+ */
-+
-+/*
-+ * @brief
-+ * result = pow(arg1, arg2)
-+ *
-+ * @note
-+ * Currently, abs(arg1) should be less than 1. Take care!
-+ */
-+struct fixed31_32 dal_fixed31_32_pow(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * Rounding functions
-+ */
-+
-+/*
-+ * @brief
-+ * result = floor(arg) := greatest integer lower than or equal to arg
-+ */
-+int32_t dal_fixed31_32_floor(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = round(arg) := integer nearest to arg
-+ */
-+int32_t dal_fixed31_32_round(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = ceil(arg) := lowest integer greater than or equal to arg
-+ */
-+int32_t dal_fixed31_32_ceil(
-+	struct fixed31_32 arg);
-+
-+/* the following two function are used in scaler hw programming to convert fixed
-+ * point value to format 2 bits from integer part and 19 bits from fractional
-+ * part. The same applies for u0d19, 0 bits from integer part and 19 bits from
-+ * fractional
-+ */
-+
-+uint32_t dal_fixed31_32_u2d19(
-+	struct fixed31_32 arg);
-+
-+uint32_t dal_fixed31_32_u0d19(
-+	struct fixed31_32 arg);
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-new file mode 100644
-index 0000000..5fca957
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_FIXED32_32_H__
-+#define __DAL_FIXED32_32_H__
-+
-+struct fixed32_32 {
-+	uint64_t value;
-+};
-+
-+static const struct fixed32_32 dal_fixed32_32_zero = { 0 };
-+static const struct fixed32_32 dal_fixed32_32_one = { 0x100000000LL };
-+static const struct fixed32_32 dal_fixed32_32_half = { 0x80000000LL };
-+
-+struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d);
-+struct fixed32_32 dal_fixed32_32_from_int(uint32_t value);
-+struct fixed32_32 dal_fixed32_32_add(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_add_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_sub(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_sub_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_mul(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_mul_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_div(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_div_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_min(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_max(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs);
-+bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs);
-+bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs);
-+bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs);
-+bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs);
-+bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs);
-+bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs);
-+uint32_t dal_fixed32_32_ceil(struct fixed32_32 value);
-+uint32_t dal_fixed32_32_floor(struct fixed32_32 value);
-+uint32_t dal_fixed32_32_round(struct fixed32_32 value);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_interface.h
-new file mode 100644
-index 0000000..a084d79
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_interface.h
-@@ -0,0 +1,93 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_INTERFACE_H__
-+#define __DAL_GPIO_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+#include "grph_object_defs.h"
-+
-+struct gpio;
-+
-+/* Open the handle for future use */
-+enum gpio_result dal_gpio_open(
-+	struct gpio *gpio,
-+	enum gpio_mode mode);
-+
-+enum gpio_result dal_gpio_open_ex(
-+	struct gpio *gpio,
-+	enum gpio_mode mode,
-+	void *options);
-+
-+/* Get high or low from the pin */
-+enum gpio_result dal_gpio_get_value(
-+	const struct gpio *gpio,
-+	uint32_t *value);
-+
-+/* Set pin high or low */
-+enum gpio_result dal_gpio_set_value(
-+	const struct gpio *gpio,
-+	uint32_t value);
-+
-+/* Get current mode */
-+enum gpio_mode dal_gpio_get_mode(
-+	const struct gpio *gpio);
-+
-+/* Change mode of the handle */
-+enum gpio_result dal_gpio_change_mode(
-+	struct gpio *gpio,
-+	enum gpio_mode mode);
-+
-+/* Get the GPIO id */
-+enum gpio_id dal_gpio_get_id(
-+	const struct gpio *gpio);
-+
-+/* Get the GPIO enum */
-+uint32_t dal_gpio_get_enum(
-+	const struct gpio *gpio);
-+
-+/* Set the GPIO pin configuration */
-+enum gpio_result dal_gpio_set_config(
-+	struct gpio *gpio,
-+	const struct gpio_config_data *config_data);
-+
-+/* Obtain GPIO pin info */
-+enum gpio_result dal_gpio_get_pin_info(
-+	const struct gpio *gpio,
-+	struct gpio_pin_info *pin_info);
-+
-+/* Obtain GPIO sync source */
-+enum sync_source dal_gpio_get_sync_source(
-+	const struct gpio *gpio);
-+
-+/* Obtain GPIO pin output state (active low or active high) */
-+enum gpio_pin_output_state dal_gpio_get_output_state(
-+	const struct gpio *gpio);
-+
-+/* Close the handle */
-+void dal_gpio_close(
-+	struct gpio *gpio);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-new file mode 100644
-index 0000000..b22bb1b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-@@ -0,0 +1,94 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_SERVICE_INTERFACE_H__
-+#define __DAL_GPIO_SERVICE_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+#include "gpio_interface.h"
-+#include "dvo_interface.h"
-+#include "ddc_interface.h"
-+#include "irq_interface.h"
-+
-+struct gpio_service;
-+
-+struct gpio_service *dal_gpio_service_create(
-+	enum dce_version dce_version,
-+	struct dc_context *ctx);
-+
-+struct gpio *dal_gpio_service_create_gpio(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_pin_output_state output_state);
-+
-+struct gpio *dal_gpio_service_create_gpio_ex(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_pin_output_state output_state);
-+
-+void dal_gpio_service_destroy_gpio(
-+	struct gpio **gpio);
-+
-+struct ddc *dal_gpio_service_create_ddc(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	struct gpio_ddc_hw_info *info);
-+
-+void dal_gpio_service_destroy_ddc(
-+	struct ddc **ddc);
-+
-+struct dvo *dal_gpio_service_create_dvo(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask);
-+
-+struct dvo *dal_gpio_service_create_dvo_ex(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+void dal_gpio_service_destroy_dvo(
-+	struct dvo **ptr);
-+
-+struct irq *dal_gpio_service_create_irq(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask);
-+
-+struct irq *dal_gpio_service_create_irq_ex(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+void dal_gpio_service_destroy_irq(
-+	struct irq **ptr);
-+
-+void dal_gpio_service_destroy(
-+	struct gpio_service **ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_types.h b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-new file mode 100644
-index 0000000..d616d62
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-@@ -0,0 +1,393 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_TYPES_H__
-+#define __DAL_GPIO_TYPES_H__
-+
-+#define BUNDLE_A_MASK 0x00FFF000L
-+#define BUNDLE_B_MASK 0x00000FFFL
-+
-+/*
-+ * gpio_result
-+ *
-+ * @brief
-+ * The possible return codes that the GPIO object can return.
-+ * These return codes can be generated
-+ * directly by the GPIO object or from the GPIOPin object.
-+ */
-+enum gpio_result {
-+	GPIO_RESULT_OK,
-+	GPIO_RESULT_NULL_HANDLE,
-+	GPIO_RESULT_INVALID_DATA,
-+	GPIO_RESULT_DEVICE_BUSY,
-+	GPIO_RESULT_OPEN_FAILED,
-+	GPIO_RESULT_ALREADY_OPENED,
-+	GPIO_RESULT_NON_SPECIFIC_ERROR
-+};
-+
-+/*
-+ * @brief
-+ * Used to identify the specific GPIO device
-+ *
-+ * @notes
-+ * These constants are used as indices in a vector.
-+ * Thus they should start from zero and be contiguous.
-+ */
-+enum gpio_id {
-+	GPIO_ID_UNKNOWN = (-1),
-+	GPIO_ID_DVO1,
-+	GPIO_ID_DVO12,
-+	GPIO_ID_DVO24,
-+	GPIO_ID_DDC_DATA,
-+	GPIO_ID_DDC_CLOCK,
-+	GPIO_ID_GENERIC,
-+	GPIO_ID_HPD,
-+	GPIO_ID_GPIO_PAD,
-+	GPIO_ID_VIP_PAD,
-+	GPIO_ID_SYNC,
-+	GPIO_ID_GSL, /* global swap lock */
-+	GPIO_ID_COUNT,
-+	GPIO_ID_MIN = GPIO_ID_DVO1,
-+	GPIO_ID_MAX = GPIO_ID_GSL
-+};
-+
-+#define GPIO_ENUM_UNKNOWN \
-+	32
-+
-+struct gpio_pin_info {
-+	uint32_t offset;
-+	uint32_t offset_y;
-+	uint32_t offset_en;
-+	uint32_t offset_mask;
-+
-+	uint32_t mask;
-+	uint32_t mask_y;
-+	uint32_t mask_en;
-+	uint32_t mask_mask;
-+};
-+
-+enum gpio_pin_output_state {
-+	GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW,
-+	GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH,
-+	GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
-+};
-+
-+enum gpio_dvo1 {
-+	GPIO_DVO1_UNKNOWN = (-1),
-+	GPIO_DVO1_0,
-+	GPIO_DVO1_1,
-+	GPIO_DVO1_2,
-+	GPIO_DVO1_3,
-+	GPIO_DVO1_4,
-+	GPIO_DVO1_5,
-+	GPIO_DVO1_6,
-+	GPIO_DVO1_7,
-+	GPIO_DVO1_8,
-+	GPIO_DVO1_9,
-+	GPIO_DVO1_10,
-+	GPIO_DVO1_11,
-+	GPIO_DVO1_12,
-+	GPIO_DVO1_13,
-+	GPIO_DVO1_14,
-+	GPIO_DVO1_15,
-+	GPIO_DVO1_16,
-+	GPIO_DVO1_17,
-+	GPIO_DVO1_18,
-+	GPIO_DVO1_19,
-+	GPIO_DVO1_20,
-+	GPIO_DVO1_21,
-+	GPIO_DVO1_22,
-+	GPIO_DVO1_23,
-+	GPIO_DVO1_COUNT,
-+	GPIO_DVO1_MIN = GPIO_DVO1_0,
-+	GPIO_DVO1_MAX = GPIO_DVO1_23
-+};
-+
-+enum gpio_dvo12 {
-+	GPIO_DVO12_UNKNOWN = (-1),
-+	GPIO_DVO12_A,
-+	GPIO_DVO12_B,
-+	GPIO_DVO12_COUNT,
-+	GPIO_DVO12_MIN = GPIO_DVO12_A,
-+	GPIO_DVO12_MAX = GPIO_DVO12_B
-+};
-+
-+enum gpio_dvo24 {
-+	GPIO_DVO24_UNKNOWN = (-1),
-+	GPIO_DVO24_A,
-+	GPIO_DVO24_COUNT,
-+	GPIO_DVO24_MIN = GPIO_DVO24_A,
-+	GPIO_DVO24_MAX = GPIO_DVO24_A
-+};
-+
-+enum gpio_generic {
-+	GPIO_GENERIC_UNKNOWN = (-1),
-+	GPIO_GENERIC_A,
-+	GPIO_GENERIC_B,
-+	GPIO_GENERIC_C,
-+	GPIO_GENERIC_D,
-+	GPIO_GENERIC_E,
-+	GPIO_GENERIC_F,
-+	GPIO_GENERIC_G,
-+	GPIO_GENERIC_COUNT,
-+	GPIO_GENERIC_MIN = GPIO_GENERIC_A,
-+	GPIO_GENERIC_MAX = GPIO_GENERIC_B
-+};
-+
-+enum gpio_hpd {
-+	GPIO_HPD_UNKNOWN = (-1),
-+	GPIO_HPD_1,
-+	GPIO_HPD_2,
-+	GPIO_HPD_3,
-+	GPIO_HPD_4,
-+	GPIO_HPD_5,
-+	GPIO_HPD_6,
-+	GPIO_HPD_COUNT,
-+	GPIO_HPD_MIN = GPIO_HPD_1,
-+	GPIO_HPD_MAX = GPIO_HPD_6
-+};
-+
-+enum gpio_gpio_pad {
-+	GPIO_GPIO_PAD_UNKNOWN = (-1),
-+	GPIO_GPIO_PAD_0,
-+	GPIO_GPIO_PAD_1,
-+	GPIO_GPIO_PAD_2,
-+	GPIO_GPIO_PAD_3,
-+	GPIO_GPIO_PAD_4,
-+	GPIO_GPIO_PAD_5,
-+	GPIO_GPIO_PAD_6,
-+	GPIO_GPIO_PAD_7,
-+	GPIO_GPIO_PAD_8,
-+	GPIO_GPIO_PAD_9,
-+	GPIO_GPIO_PAD_10,
-+	GPIO_GPIO_PAD_11,
-+	GPIO_GPIO_PAD_12,
-+	GPIO_GPIO_PAD_13,
-+	GPIO_GPIO_PAD_14,
-+	GPIO_GPIO_PAD_15,
-+	GPIO_GPIO_PAD_16,
-+	GPIO_GPIO_PAD_17,
-+	GPIO_GPIO_PAD_18,
-+	GPIO_GPIO_PAD_19,
-+	GPIO_GPIO_PAD_20,
-+	GPIO_GPIO_PAD_21,
-+	GPIO_GPIO_PAD_22,
-+	GPIO_GPIO_PAD_23,
-+	GPIO_GPIO_PAD_24,
-+	GPIO_GPIO_PAD_25,
-+	GPIO_GPIO_PAD_26,
-+	GPIO_GPIO_PAD_27,
-+	GPIO_GPIO_PAD_28,
-+	GPIO_GPIO_PAD_29,
-+	GPIO_GPIO_PAD_30,
-+	GPIO_GPIO_PAD_COUNT,
-+	GPIO_GPIO_PAD_MIN = GPIO_GPIO_PAD_0,
-+	GPIO_GPIO_PAD_MAX = GPIO_GPIO_PAD_30
-+};
-+
-+enum gpio_vip_pad {
-+	GPIO_VIP_PAD_UNKNOWN = (-1),
-+	/* following never used -
-+	 * GPIO_ID_DDC_CLOCK::GPIO_DDC_LINE_VIP_PAD defined instead */
-+	GPIO_VIP_PAD_SCL,
-+	/* following never used -
-+	 * GPIO_ID_DDC_DATA::GPIO_DDC_LINE_VIP_PAD defined instead */
-+	GPIO_VIP_PAD_SDA,
-+	GPIO_VIP_PAD_VHAD,
-+	GPIO_VIP_PAD_VPHCTL,
-+	GPIO_VIP_PAD_VIPCLK,
-+	GPIO_VIP_PAD_VID,
-+	GPIO_VIP_PAD_VPCLK0,
-+	GPIO_VIP_PAD_DVALID,
-+	GPIO_VIP_PAD_PSYNC,
-+	GPIO_VIP_PAD_COUNT,
-+	GPIO_VIP_PAD_MIN = GPIO_VIP_PAD_SCL,
-+	GPIO_VIP_PAD_MAX = GPIO_VIP_PAD_PSYNC
-+};
-+
-+enum gpio_sync {
-+	GPIO_SYNC_UNKNOWN = (-1),
-+	GPIO_SYNC_HSYNC_A,
-+	GPIO_SYNC_VSYNC_A,
-+	GPIO_SYNC_HSYNC_B,
-+	GPIO_SYNC_VSYNC_B,
-+	GPIO_SYNC_COUNT,
-+	GPIO_SYNC_MIN = GPIO_SYNC_HSYNC_A,
-+	GPIO_SYNC_MAX = GPIO_SYNC_VSYNC_B
-+};
-+
-+enum gpio_gsl {
-+	GPIO_GSL_UNKNOWN = (-1),
-+	GPIO_GSL_GENLOCK_CLOCK,
-+	GPIO_GSL_GENLOCK_VSYNC,
-+	GPIO_GSL_SWAPLOCK_A,
-+	GPIO_GSL_SWAPLOCK_B,
-+	GPIO_GSL_COUNT,
-+	GPIO_GSL_MIN = GPIO_GSL_GENLOCK_CLOCK,
-+	GPIO_GSL_MAX = GPIO_GSL_SWAPLOCK_B
-+};
-+
-+/*
-+ * @brief
-+ * Unique Id for DDC handle.
-+ * Values are meaningful (used as indexes to array)
-+ */
-+enum gpio_ddc_line {
-+	GPIO_DDC_LINE_UNKNOWN = (-1),
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
-+	GPIO_DDC_LINE_DDC_VGA,
-+	GPIO_DDC_LINE_VIP_PAD,
-+	GPIO_DDC_LINE_I2C_PAD = GPIO_DDC_LINE_VIP_PAD,
-+	GPIO_DDC_LINE_COUNT,
-+	GPIO_DDC_LINE_MIN = GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_MAX = GPIO_DDC_LINE_I2C_PAD
-+};
-+
-+/*
-+ * @brief
-+ * Identifies the mode of operation to open a GPIO device.
-+ * A GPIO device (pin) can be programmed in only one of these modes at a time.
-+ */
-+enum gpio_mode {
-+	GPIO_MODE_UNKNOWN = (-1),
-+	GPIO_MODE_INPUT,
-+	GPIO_MODE_OUTPUT,
-+	GPIO_MODE_FAST_OUTPUT,
-+	GPIO_MODE_HARDWARE,
-+	GPIO_MODE_INTERRUPT
-+};
-+
-+/*
-+ * @brief
-+ * Identifies the source of the signal when GPIO is in HW mode.
-+ * get_signal_source() will return GPIO_SYGNAL_SOURCE__UNKNOWN
-+ * when one of the following holds:
-+ *    1. GPIO is input GPIO
-+ *    2. GPIO is not opened in HW mode
-+ *    3. GPIO does not have fixed signal source
-+ *    (like DC_GenericA have mux instead fixed)
-+ */
-+enum gpio_signal_source {
-+	GPIO_SIGNAL_SOURCE_UNKNOWN = (-1),
-+	GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC,
-+	GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC,
-+	GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC,
-+	GPIO_SIGNAL_SOURCE_DACA_HSYNC,
-+	GPIO_SIGNAL_SOURCE_DACB_HSYNC,
-+	GPIO_SIGNAL_SOURCE_DACA_VSYNC,
-+	GPIO_SIGNAL_SOURCE_DACB_VSYNC,
-+	GPIO_SIGNAL_SOURCE_DVO_STEREO_SYNC
-+};
-+
-+enum gpio_stereo_source {
-+	GPIO_STEREO_SOURCE_UNKNOWN = (-1),
-+	GPIO_STEREO_SOURCE_D1,
-+	GPIO_STEREO_SOURCE_D2,
-+	GPIO_STEREO_SOURCE_D3,
-+	GPIO_STEREO_SOURCE_D4,
-+	GPIO_STEREO_SOURCE_D5,
-+	GPIO_STEREO_SOURCE_D6
-+};
-+
-+/*
-+ * GPIO config
-+ */
-+
-+enum gpio_config_type {
-+	GPIO_CONFIG_TYPE_NONE,
-+	GPIO_CONFIG_TYPE_DDC,
-+	GPIO_CONFIG_TYPE_HPD,
-+	GPIO_CONFIG_TYPE_GENERIC_MUX,
-+	GPIO_CONFIG_TYPE_GSL_MUX,
-+	GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE
-+};
-+
-+/* DDC configuration */
-+
-+enum gpio_ddc_config_type {
-+	GPIO_DDC_CONFIG_TYPE_MODE_AUX,
-+	GPIO_DDC_CONFIG_TYPE_MODE_I2C,
-+	GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT,
-+	GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT,
-+	GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING
-+};
-+
-+struct gpio_ddc_config {
-+	enum gpio_ddc_config_type type;
-+	bool data_en_bit_present;
-+	bool clock_en_bit_present;
-+};
-+
-+/* HPD configuration */
-+
-+struct gpio_hpd_config {
-+	uint32_t delay_on_connect; /* milliseconds */
-+	uint32_t delay_on_disconnect; /* milliseconds */
-+};
-+
-+struct gpio_generic_mux_config {
-+	bool enable_output_from_mux;
-+	enum gpio_signal_source mux_select;
-+	enum gpio_stereo_source stereo_select;
-+};
-+
-+enum gpio_gsl_mux_config_type {
-+	GPIO_GSL_MUX_CONFIG_TYPE_DISABLE,
-+	GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC,
-+	GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC
-+};
-+
-+struct gpio_gsl_mux_config {
-+	enum gpio_gsl_mux_config_type type;
-+	/* Actually sync_source type,
-+	 * however we want to avoid inter-component includes here */
-+	uint32_t gsl_group;
-+};
-+
-+struct gpio_config_data {
-+	enum gpio_config_type type;
-+	union {
-+		struct gpio_ddc_config ddc;
-+		struct gpio_hpd_config hpd;
-+		struct gpio_generic_mux_config generic_mux;
-+		struct gpio_gsl_mux_config gsl_mux;
-+	} config;
-+};
-+
-+struct gpio_ddc_hw_info {
-+	bool hw_supported;
-+	uint32_t ddc_channel;
-+};
-+
-+struct gpio_ddc_open_options {
-+	bool en_bit_present;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpu_clock_info.h b/drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
-new file mode 100644
-index 0000000..c9b47b2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPU_CLOCK_INFO__
-+#define __DAL_GPU_CLOCK_INFO__
-+
-+#include "include/gpu_interface.h"
-+
-+/*TODO this structures should be defined*/
-+struct gpu_static_clk_info;
-+struct gpu_dynamic_clk_info;
-+
-+bool init_static_clk_info(
-+		struct gpu *gpu,
-+		struct gpu_static_clk_info *st_clk_info);
-+
-+bool update_dynamic_clk_info(
-+		struct gpu *gpu,
-+		struct gpu_dynamic_clk_info *dyn_clk_info);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpu_interface.h b/drivers/gpu/drm/amd/dal/include/gpu_interface.h
-new file mode 100644
-index 0000000..63262c3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/gpu_interface.h
-@@ -0,0 +1,91 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPU_INTERFACE__
-+#define __DAL_GPU_INTERFACE__
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/grph_object_ctrl_defs.h"
-+
-+enum gpu_clocks_state {
-+	GPU_CLOCKS_STATE_INVALID,
-+	GPU_CLOCKS_STATE_ULTRA_LOW,
-+	GPU_CLOCKS_STATE_LOW,
-+	GPU_CLOCKS_STATE_NOMINAL,
-+	GPU_CLOCKS_STATE_PERFORMANCE
-+};
-+
-+struct gpu_clock_info {
-+	uint32_t min_sclk_khz;
-+	uint32_t max_sclk_khz;
-+
-+	uint32_t min_mclk_khz;
-+	uint32_t max_mclk_khz;
-+
-+	uint32_t min_dclk_khz;
-+	uint32_t max_dclk_khz;
-+};
-+
-+struct gpu;
-+struct irq_manager;
-+
-+struct gpu_init_data {
-+	struct dc_context *ctx;
-+	struct adapter_service *adapter_service;
-+	struct irq_manager *irq_manager;
-+};
-+
-+struct gpu *dal_gpu_create(struct gpu_init_data *init_data);
-+void dal_gpu_destroy(struct gpu **);
-+
-+void dal_gpu_power_up(struct gpu *);
-+void dal_gpu_power_down(
-+		struct gpu *gpu,
-+		enum dc_video_power_state power_state);
-+void dal_gpu_light_sleep_vbios_wa(struct gpu *gpu, bool enable);
-+void dal_gpu_release_hw(struct gpu *gpu);
-+
-+uint32_t dal_gpu_get_num_of_functional_controllers(const struct gpu *gpu);
-+uint32_t dal_gpu_get_max_num_of_primary_controllers(const struct gpu *gpu);
-+uint32_t dal_gpu_get_max_num_of_underlay_controllers(const struct gpu *gpu);
-+struct controller *dal_gpu_create_controller(
-+				struct gpu *gpu,
-+				uint32_t index);
-+uint32_t dal_gpu_get_num_of_clock_sources(const struct gpu *gpu);
-+struct clock_source *dal_gpu_create_clock_source(
-+	 struct gpu *gpu,
-+	uint32_t index);
-+
-+/* gpu_clock_interface implementation */
-+bool dal_gpu_init_static_clock_info(struct gpu *gpu,
-+		struct gpu_clock_info *gpu_clk_info);
-+
-+bool dal_gpu_update_dynamic_clock_info(struct gpu *gpu,
-+		struct gpu_clock_info *gpu_clk_info);
-+
-+void dal_gpu_get_static_clock_info(struct gpu *gpu,
-+		struct gpu_clock_info *gpu_clk_info);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_csc_types.h b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-new file mode 100644
-index 0000000..711b458
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_CSC_TYPES_H__
-+#define __DAL_GRPH_CSC_TYPES_H__
-+
-+#include "set_mode_types.h"
-+
-+enum color_space {
-+	COLOR_SPACE_UNKNOWN,
-+	COLOR_SPACE_SRGB_FULL_RANGE,
-+	COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	COLOR_SPACE_YPBPR601,
-+	COLOR_SPACE_YPBPR709,
-+	COLOR_SPACE_YCBCR601,
-+	COLOR_SPACE_YCBCR709,
-+	COLOR_SPACE_YCBCR601_YONLY,
-+	COLOR_SPACE_YCBCR709_YONLY,
-+	COLOR_SPACE_N_MVPU_SUPER_AA,
-+};
-+
-+enum grph_color_adjust_option {
-+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
-+	GRPH_COLOR_MATRIX_SW
-+};
-+
-+enum grph_csc_adjust_item {
-+	GRPH_ADJUSTMENT_CONTRAST = 1,
-+	GRPH_ADJUSTMENT_SATURATION,
-+	GRPH_ADJUSTMENT_BRIGHTNESS,
-+	GRPH_ADJUSTMENT_HUE,
-+	GRPH_ADJUSTMENT_COLOR_TEMPERATURE
-+};
-+
-+#define CSC_TEMPERATURE_MATRIX_SIZE 9
-+
-+enum graphics_csc_adjust_type {
-+	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
-+};
-+
-+enum graphics_gamut_adjust_type {
-+	GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_GAMUT_ADJUST_TYPE_SW  /* use adjustments */
-+};
-+
-+struct grph_csc_adjustment {
-+	enum grph_color_adjust_option color_adjust_option;
-+	enum color_space c_space;
-+	int32_t grph_cont;
-+	int32_t grph_sat;
-+	int32_t grph_bright;
-+	int32_t grph_hue;
-+	int32_t adjust_divider;
-+	int32_t temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
-+	int32_t temperature_divider;
-+	uint32_t lb_color_depth;
-+	uint8_t gamma; /* gamma from Edid */
-+	enum dc_color_depth color_depth; /* clean up to uint32_t */
-+	enum pixel_format surface_pixel_format;
-+	enum graphics_csc_adjust_type   csc_adjust_type;
-+	enum graphics_gamut_adjust_type gamut_adjust_type;
-+};
-+
-+struct default_adjustment {
-+	uint32_t lb_color_depth;
-+	enum color_space color_space;
-+	enum dc_color_depth color_depth;
-+	enum pixel_format surface_pixel_format;
-+	enum graphics_csc_adjust_type csc_adjust_type;
-+	bool force_hw_default;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-new file mode 100644
-index 0000000..d804109
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -0,0 +1,598 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
-+#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
-+
-+#include "grph_object_defs.h"
-+
-+/*
-+ * #####################################################
-+ * #####################################################
-+ *
-+ * These defines shared between asic_control/bios_parser and other
-+ * DAL components
-+ *
-+ * #####################################################
-+ * #####################################################
-+ */
-+
-+enum tv_standard {
-+	TV_STANDARD_UNKNOWN = 0, /* direct HW (mmBIOS_SCRATCH_2) translation! */
-+	TV_STANDARD_NTSC,
-+	TV_STANDARD_NTSCJ,
-+	TV_STANDARD_PAL,
-+	TV_STANDARD_PALM,
-+	TV_STANDARD_PALCN,
-+	TV_STANDARD_PALN,
-+	TV_STANDARD_PAL60,
-+	TV_STANDARD_SECAM
-+};
-+
-+enum cv_standard {
-+	CV_STANDARD_UNKNOWN = 0x0000,
-+	CV_STANDARD_HD_MASK = 0x0800,		/* Flag mask HDTV output */
-+	CV_STANDARD_SD_NTSC_MASK = 0x1000,	/* Flag mask NTSC output */
-+	CV_STANDARD_SD_NTSC_M,		/* NTSC (North America) output 1001 */
-+	CV_STANDARD_SD_NTSC_J,		/* NTSC (Japan) output 1002 */
-+	CV_STANDARD_SD_480I,		/* SDTV 480i output 1003 */
-+	CV_STANDARD_SD_480P,		/* SDTV 480p output 1004 */
-+	CV_STANDARD_HD_720_60P = 0x1800,/* HDTV 720/60p output 1800 */
-+	CV_STANDARD_HD_1080_60I,	/* HDTV 1080/60i output 1801 */
-+	CV_STANDARD_SD_PAL_MASK = 0x2000,/* Flag mask PAL output */
-+	CV_STANDARD_SD_PAL_B,			/* PAL B output 2001 */
-+	CV_STANDARD_SD_PAL_D,			/* PAL D output 2002 */
-+	CV_STANDARD_SD_PAL_G,			/* PAL G output 2003 */
-+	CV_STANDARD_SD_PAL_H,			/* PAL H output 2004 */
-+	CV_STANDARD_SD_PAL_I,			/* PAL I output 2005 */
-+	CV_STANDARD_SD_PAL_M,			/* PAL M output 2006 */
-+	CV_STANDARD_SD_PAL_N,			/* PAL N output 2007 */
-+	CV_STANDARD_SD_PAL_N_COMB,	/* PAL Combination N output 2008 */
-+	CV_STANDARD_SD_PAL_60,		/* PAL 60 output (test mode) 2009 */
-+	CV_STANDARD_SD_576I,		/* SDTV 576i output 2010 */
-+	CV_STANDARD_SD_576P,		/* SDTV 576p output 2011 */
-+	CV_STANDARD_HD_720_50P = 0x2800,/* HDTV 720/50p output 2800 */
-+	CV_STANDARD_HD_1080_50I,	/* HDTV 1080/50i output 2801 */
-+	CV_STANDARD_SD_SECAM_MASK = 0x4000, /* Flag mask SECAM output */
-+	CV_STANDARD_SD_SECAM_B,		/* SECAM B output 4001 */
-+	CV_STANDARD_SD_SECAM_D,		/* SECAM D output 4002 */
-+	CV_STANDARD_SD_SECAM_G,		/* SECAM G output 4003 */
-+	CV_STANDARD_SD_SECAM_H,		/* SECAM H output 4004 */
-+	CV_STANDARD_SD_SECAM_K,		/* SECAM K output 4005 */
-+	CV_STANDARD_SD_SECAM_K1,	/* SECAM K1 output 4006 */
-+	CV_STANDARD_SD_SECAM_L,		/* SECAM L output 4007 */
-+	CV_STANDARD_SD_SECAM_L1		/* SECAM L1 output 4009 */
-+};
-+
-+enum disp_pll_config {
-+	DISP_PLL_CONFIG_UNKNOWN = 0,
-+	DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT,
-+	DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT,
-+	DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT
-+};
-+
-+enum display_output_bit_depth {
-+	PANEL_UNDEFINE = 0,
-+	PANEL_6BIT_COLOR = 1,
-+	PANEL_8BIT_COLOR = 2,
-+	PANEL_10BIT_COLOR = 3,
-+	PANEL_12BIT_COLOR = 4,
-+	PANEL_16BIT_COLOR = 5,
-+};
-+
-+enum lcd_scale {
-+	/* No request to turn on LCD SCALER (Centering or Replication) */
-+	LCD_SCALE_NONE = 0,
-+	/* Request LCD SCALER in full panel mode */
-+	LCD_SCALE_FULLPANEL,
-+	/* Request LCD SCALER in aspect-ratio mode */
-+	LCD_SCALE_ASPECTRATIO,
-+
-+	LCD_SCALE_UNKNOWN = (-1L),
-+};
-+
-+/* Device type as abstracted by ATOM BIOS */
-+enum dal_device_type {
-+	DEVICE_TYPE_UNKNOWN = 0,
-+	DEVICE_TYPE_LCD,
-+	DEVICE_TYPE_CRT,
-+	DEVICE_TYPE_DFP,
-+	DEVICE_TYPE_CV,
-+	DEVICE_TYPE_TV,
-+	DEVICE_TYPE_CF,
-+	DEVICE_TYPE_WIRELESS
-+};
-+
-+/* Device ID as abstracted by ATOM BIOS */
-+struct device_id {
-+	enum dal_device_type device_type:16;
-+	uint32_t enum_id:16;	/* 1 based enum */
-+};
-+
-+struct graphics_object_i2c_info {
-+	struct gpio_info {
-+		uint32_t clk_mask_register_index;
-+		uint32_t clk_en_register_index;
-+		uint32_t clk_y_register_index;
-+		uint32_t clk_a_register_index;
-+		uint32_t data_mask_register_index;
-+		uint32_t data_en_register_index;
-+		uint32_t data_y_register_index;
-+		uint32_t data_a_register_index;
-+
-+		uint32_t clk_mask_shift;
-+		uint32_t clk_en_shift;
-+		uint32_t clk_y_shift;
-+		uint32_t clk_a_shift;
-+		uint32_t data_mask_shift;
-+		uint32_t data_en_shift;
-+		uint32_t data_y_shift;
-+		uint32_t data_a_shift;
-+	} gpio_info;
-+
-+	bool i2c_hw_assist;
-+	uint32_t i2c_line;
-+	uint32_t i2c_engine_id;
-+	uint32_t i2c_slave_address;
-+};
-+
-+
-+struct graphics_object_hpd_info {
-+	uint8_t hpd_int_gpio_uid;
-+	uint8_t hpd_active;
-+};
-+
-+struct connector_device_tag_info {
-+	uint32_t acpi_device;
-+	struct device_id dev_id;
-+};
-+
-+struct device_timing {
-+	struct misc_info {
-+		uint32_t HORIZONTAL_CUT_OFF:1;
-+		/* 0=Active High, 1=Active Low */
-+		uint32_t H_SYNC_POLARITY:1;
-+		/* 0=Active High, 1=Active Low */
-+		uint32_t V_SYNC_POLARITY:1;
-+		uint32_t VERTICAL_CUT_OFF:1;
-+		uint32_t H_REPLICATION_BY2:1;
-+		uint32_t V_REPLICATION_BY2:1;
-+		uint32_t COMPOSITE_SYNC:1;
-+		uint32_t INTERLACE:1;
-+		uint32_t DOUBLE_CLOCK:1;
-+		uint32_t RGB888:1;
-+		uint32_t GREY_LEVEL:2;
-+		uint32_t SPATIAL:1;
-+		uint32_t TEMPORAL:1;
-+		uint32_t API_ENABLED:1;
-+	} misc_info;
-+
-+	uint32_t pixel_clk; /* in KHz */
-+	uint32_t horizontal_addressable;
-+	uint32_t horizontal_blanking_time;
-+	uint32_t vertical_addressable;
-+	uint32_t vertical_blanking_time;
-+	uint32_t horizontal_sync_offset;
-+	uint32_t horizontal_sync_width;
-+	uint32_t vertical_sync_offset;
-+	uint32_t vertical_sync_width;
-+	uint32_t horizontal_border;
-+	uint32_t vertical_border;
-+};
-+
-+struct supported_refresh_rate {
-+	uint32_t REFRESH_RATE_30HZ:1;
-+	uint32_t REFRESH_RATE_40HZ:1;
-+	uint32_t REFRESH_RATE_48HZ:1;
-+	uint32_t REFRESH_RATE_50HZ:1;
-+	uint32_t REFRESH_RATE_60HZ:1;
-+};
-+
-+struct embedded_panel_info {
-+	struct device_timing lcd_timing;
-+	uint32_t ss_id;
-+	struct supported_refresh_rate supported_rr;
-+	uint32_t drr_enabled;
-+	uint32_t min_drr_refresh_rate;
-+};
-+
-+struct embedded_panel_patch_mode {
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+struct firmware_info {
-+	struct pll_info {
-+		uint32_t crystal_frequency; /* in KHz */
-+		uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
-+		uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
-+		uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
-+		uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
-+	} pll_info;
-+
-+	struct firmware_feature {
-+		uint32_t memory_clk_ss_percentage;
-+		uint32_t engine_clk_ss_percentage;
-+	} feature;
-+
-+	uint32_t default_display_engine_pll_frequency; /* in KHz */
-+	uint32_t external_clock_source_frequency_for_dp; /* in KHz */
-+	uint32_t smu_gpu_pll_output_freq; /* in KHz */
-+	uint8_t min_allowed_bl_level;
-+	uint8_t remote_display_config;
-+};
-+
-+/* direct HW (mmBIOS_SCRATCH_2) translation! */
-+union tv_standard_support {
-+	uint8_t u_all;
-+	struct {
-+		bool TV_SUPPORT_NTSC:1;
-+		bool TV_SUPPORT_NTSCJ:1;
-+
-+		bool TV_SUPPORT_PAL:1;
-+		bool TV_SUPPORT_PALM:1;
-+		bool TV_SUPPORT_PALCN:1;
-+		bool TV_SUPPORT_PALN:1;
-+		bool TV_SUPPORT_PAL60:1;
-+
-+		bool TV_SUPPORT_SECAM:1;
-+	} bits;
-+};
-+
-+struct analog_tv_info {
-+	union tv_standard_support tv_suppported;
-+	union tv_standard_support tv_boot_up_default;
-+};
-+
-+struct spread_spectrum_info {
-+	struct spread_spectrum_type {
-+		bool CENTER_MODE:1;
-+		bool EXTERNAL:1;
-+		bool STEP_AND_DELAY_INFO:1;
-+	} type;
-+
-+	/* in unit of 0.01% (spreadPercentageDivider = 100),
-+	otherwise in 0.001% units (spreadPercentageDivider = 1000); */
-+	uint32_t spread_spectrum_percentage;
-+	uint32_t spread_percentage_divider; /* 100 or 1000 */
-+	uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
-+
-+	union {
-+		struct step_and_delay_info {
-+			uint32_t step;
-+			uint32_t delay;
-+			uint32_t recommended_ref_div;
-+		} step_and_delay_info;
-+		/* For mem/engine/uvd, Clock Out frequence (VCO ),
-+		in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
-+		for DP, it is link clock ( 270000 or 162000 ) */
-+		uint32_t target_clock_range; /* in KHz */
-+	};
-+
-+};
-+
-+struct graphics_object_encoder_cap_info {
-+	uint32_t dp_hbr2_cap:1;
-+	uint32_t dp_hbr2_validated:1;
-+	uint32_t reserved:15;
-+};
-+
-+struct din_connector_info {
-+	uint32_t gpio_id;
-+	bool gpio_tv_active_state;
-+};
-+
-+/* Invalid channel mapping */
-+enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
-+
-+/**
-+ * DDI PHY channel mapping reflecting XBAR setting
-+ */
-+union ddi_channel_mapping {
-+	struct mapping {
-+		uint8_t lane0:2;	/* Mapping for lane 0 */
-+		uint8_t lane1:2;	/* Mapping for lane 1 */
-+		uint8_t lane2:2;	/* Mapping for lane 2 */
-+		uint8_t lane3:2;	/* Mapping for lane 3 */
-+	} mapping;
-+	uint8_t raw;
-+};
-+
-+/**
-+* Transmitter output configuration description
-+*/
-+struct transmitter_configuration_info {
-+	/* DDI PHY ID for the transmitter */
-+	enum transmitter transmitter_phy_id;
-+	/* DDI PHY channel mapping reflecting crossbar setting */
-+	union ddi_channel_mapping output_channel_mapping;
-+};
-+
-+struct transmitter_configuration {
-+	/* Configuration for the primary transmitter */
-+	struct transmitter_configuration_info primary_transmitter_config;
-+	/* Secondary transmitter configuration for Dual-link DVI */
-+	struct transmitter_configuration_info secondary_transmitter_config;
-+};
-+
-+
-+/* These size should be sufficient to store info coming from BIOS */
-+#define NUMBER_OF_UCHAR_FOR_GUID 16
-+#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
-+#define NUMBER_OF_CSR_M3_ARB 10
-+#define NUMBER_OF_DISP_CLK_VOLTAGE 4
-+#define NUMBER_OF_AVAILABLE_SCLK 5
-+
-+/* V6 */
-+struct integrated_info {
-+	struct clock_voltage_caps {
-+		/* The Voltage Index indicated by FUSE, same voltage index
-+		shared with SCLK DPM fuse table */
-+		uint32_t voltage_index;
-+		/* Maximum clock supported with specified voltage index */
-+		uint32_t max_supported_clk; /* in KHz */
-+	} disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
-+
-+	struct display_connection_info {
-+		struct external_display_path {
-+			/* A bit vector to show what devices are supported */
-+			uint32_t device_tag;
-+			/* 16bit device ACPI id. */
-+			uint32_t device_acpi_enum;
-+			/* A physical connector for displays to plug in,
-+			using object connector definitions */
-+			struct graphics_object_id device_connector_id;
-+			/* An index into external AUX/DDC channel LUT */
-+			uint8_t ext_aux_ddc_lut_index;
-+			/* An index into external HPD pin LUT */
-+			uint8_t ext_hpd_pin_lut_index;
-+			/* external encoder object id */
-+			struct graphics_object_id ext_encoder_obj_id;
-+			/* XBAR mapping of the PHY channels */
-+			union ddi_channel_mapping channel_mapping;
-+		} path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
-+
-+		uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
-+		uint8_t checksum;
-+	} ext_disp_conn_info; /* exiting long long time */
-+
-+	struct available_s_clk_list {
-+		/* Maximum clock supported with specified voltage index */
-+		uint32_t supported_s_clk; /* in KHz */
-+		/* The Voltage Index indicated by FUSE for specified SCLK */
-+		uint32_t voltage_index;
-+		/* The Voltage ID indicated by FUSE for specified SCLK */
-+		uint32_t voltage_id;
-+	} avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
-+
-+	uint8_t memory_type;
-+	uint8_t ma_channel_number;
-+	uint32_t boot_up_engine_clock; /* in KHz */
-+	uint32_t dentist_vco_freq; /* in KHz */
-+	uint32_t boot_up_uma_clock; /* in KHz */
-+	uint32_t boot_up_req_display_vector;
-+	uint32_t other_display_misc;
-+	uint32_t gpu_cap_info;
-+	uint32_t sb_mmio_base_addr;
-+	uint32_t system_config;
-+	uint32_t cpu_cap_info;
-+	uint32_t max_nb_voltage;
-+	uint32_t min_nb_voltage;
-+	uint32_t boot_up_nb_voltage;
-+	uint32_t ext_disp_conn_info_offset;
-+	uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
-+	uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
-+	uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
-+	uint32_t gmc_restore_reset_time;
-+	uint32_t minimum_n_clk;
-+	uint32_t idle_n_clk;
-+	uint32_t ddr_dll_power_up_time;
-+	uint32_t ddr_pll_power_up_time;
-+	/* start for V6 */
-+	uint32_t pcie_clk_ss_type;
-+	uint32_t lvds_ss_percentage;
-+	uint32_t lvds_sspread_rate_in_10hz;
-+	uint32_t hdmi_ss_percentage;
-+	uint32_t hdmi_sspread_rate_in_10hz;
-+	uint32_t dvi_ss_percentage;
-+	uint32_t dvi_sspread_rate_in_10_hz;
-+	uint32_t sclk_dpm_boost_margin;
-+	uint32_t sclk_dpm_throttle_margin;
-+	uint32_t sclk_dpm_tdp_limit_pg;
-+	uint32_t sclk_dpm_tdp_limit_boost;
-+	uint32_t boost_engine_clock;
-+	uint32_t boost_vid_2bit;
-+	uint32_t enable_boost;
-+	uint32_t gnb_tdp_limit;
-+	/* Start from V7 */
-+	uint32_t max_lvds_pclk_freq_in_single_link;
-+	uint32_t lvds_misc;
-+	uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
-+	uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
-+	uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
-+	uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
-+	uint32_t lvds_off_to_on_delay_in_4ms;
-+	uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
-+	uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
-+	uint32_t lvds_reserved1;
-+	uint32_t lvds_bit_depth_control_val;
-+};
-+
-+/**
-+* Power source ids.
-+*/
-+enum power_source {
-+	POWER_SOURCE_AC = 0,
-+	POWER_SOURCE_DC,
-+	POWER_SOURCE_LIMITED_POWER,
-+	POWER_SOURCE_LIMITED_POWER_2,
-+	POWER_SOURCE_MAX
-+};
-+
-+struct bios_event_info {
-+	uint32_t thermal_state;
-+	uint32_t backlight_level;
-+	enum power_source powerSource;
-+	bool has_thermal_state_changed;
-+	bool has_power_source_changed;
-+	bool has_forced_mode_changed;
-+	bool forced_mode;
-+	bool backlight_changed;
-+};
-+
-+union stereo_3d_support {
-+	struct {
-+		/* HW can alter left and right image sequentially */
-+		uint32_t FRAME_ALTERNATE:1;
-+		/* Frame Alternate + HW can integrate stereosync
-+		signal into TMDS stream */
-+		uint32_t DVI_FRAME_ALT:1;
-+		/* Frame Alternate + HW can integrate stereosync
-+		signal into DP stream */
-+		uint32_t DISPLAY_PORT_FRAME_ALT:1;
-+		/* Frame Alternate + HW can drive stereosync signal
-+		on separate line */
-+		uint32_t SIDEBAND_FRAME_ALT:1;
-+		/* SW allowed to pack left and right image into single frame.
-+		Used for HDMI only, DP has it's own flags. */
-+		uint32_t SW_FRAME_PACK:1;
-+		/* HW can pack left and right image into single HDMI frame */
-+		uint32_t PROGRESSIVE_FRAME_PACK:1;
-+		/* HW can pack left and right interlaced images into
-+		single HDMI frame */
-+		uint32_t INTERLACE_FRAME_PACK:1;
-+		/* HW can pack left and right images into single DP frame */
-+		uint32_t DISPLAY_PORT_FRAME_PACK:1;
-+		/* SW can pack left and right images into single DP frame */
-+		uint32_t DISPLAY_PORT_SW_FRAME_PACK:1;
-+		/* HW can mix left and right images into single image */
-+		uint32_t INTERLEAVE:1;
-+		/* HW can mix left and right interlaced images
-+		into single image */
-+		uint32_t INTERLACE_INTERLEAVE:1;
-+		/* Allow display-based formats (whatever supported)
-+		in WS stereo mode */
-+		uint32_t DISPLAY_3DIN_WS_MODE:1;
-+		/* Side-by-side, packed by application/driver into 2D frame */
-+		uint32_t SIDE_BY_SIDE_SW_PACKED:1;
-+		/* Top-and-bottom, packed by application/driver into 2D frame */
-+		uint32_t TOP_AND_BOTTOM_SW_PACKED:1;
-+	} bits;
-+	uint32_t u_all;
-+};
-+
-+/* Bitvector and bitfields of possible optimizations
-+ #IMPORTANT# Keep bitfields match bitvector! */
-+enum optimization_feature {
-+	/* Don't do HW programming on panels that were enabled by VBIOS */
-+	OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY = 0x1,
-+	OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME = 0x2,
-+	OF_SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME = 0x4,
-+	OF_SKIP_POWER_UP_VBIOS_ENABLED_ENCODER = 0x8,
-+	/* Do not turn off VCC while powering down on boot or resume */
-+	OF_KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME = 0x10,
-+	/* Do not turn off VCC while performing SetMode */
-+	OF_KEEP_VCC_DURING_SET_MODE = 0x20,
-+	OF_DO_NOT_WAIT_FOR_HPD_LOW = 0x40,
-+	OF_SKIP_POWER_DOWN_INACTIVE_ENCODER = 0x80
-+};
-+
-+union optimization_flags {
-+	struct {
-+		/* Don't do HW programming if panels were enabled by VBIOS */
-+		uint32_t SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:1;
-+		uint32_t SKIP_RESET_OF_ALL_HW_ON_S3RESUME:1;
-+		uint32_t SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME:1;
-+		uint32_t SKIP_POWER_UP_VBIOS_ENABLED_ENCODER:1;
-+		/* Do not turn off VCC while powering down on boot or resume */
-+		uint32_t KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME:1;
-+		/* Do not turn off VCC while performing SetMode */
-+		uint32_t KEEP_VCC_DURING_SET_MODE:1;
-+		uint32_t DO_NOT_WAIT_FOR_HPD_LOW:1;
-+	} bits;
-+	uint32_t u_all;
-+};
-+
-+/* Bitvector and bitfields of performance measurements
-+ #IMPORTANT# Keep bitfields match bitvector! */
-+enum perf_measure {
-+	PERF_MEASURE_ADAPTER_POWER_STATE = 0x1,
-+	PERF_MEASURE_DISPLAY_POWER_STATE = 0x2,
-+	PERF_MEASURE_SET_MODE_SEQ = 0x4,
-+	PERF_MEASURE_DETECT_AT_RESUME = 0x8,
-+	PERF_MEASURE_MEMORY_READ_CONTROL = 0x10,
-+};
-+
-+union perf_measure_flags {
-+	struct {
-+		uint32_t ADAPTER_POWER_STATE:1;
-+		uint32_t DISPLAY_POWER_STATE:1;
-+		uint32_t SET_MODE_SEQ:1;
-+		uint32_t DETECT_AT_RESUME:1;
-+		uint32_t MEMORY_READ_CONTROL:1;
-+
-+	} bits;
-+	uint32_t u_all;
-+};
-+
-+enum {
-+	PERF_MEASURE_POWERCODE_OFFSET = 0x0,
-+	PERF_MEASURE_POWER_CODE_MASK = 0xFF,
-+	PERF_MEASURE_POWER_STATE_OFFSET = 8,
-+	PERF_MEASURE_POWER_STATE_MASK = 0x000FF00,
-+	PERF_MEASURE_PREV_POWER_STATE_OFFSET = 16,
-+	PERF_MEASURE_PREV_POWER_STATE_MASK = 0x00FF0000,
-+	PERF_MEASURE_DISPLAY_INDEX_OFFSET = 24,
-+	PERF_MEASURE_DISPLAY_INDEX_MASK = 0xFF000000
-+};
-+
-+enum {
-+	HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
-+	TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
-+};
-+
-+/*
-+ * DFS-bypass flag
-+ */
-+/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
-+enum {
-+	DFS_BYPASS_ENABLE = 0x10
-+};
-+
-+enum {
-+	INVALID_BACKLIGHT = -1
-+};
-+
-+struct panel_backlight_boundaries {
-+	uint32_t min_signal_level;
-+	uint32_t max_signal_level;
-+};
-+
-+struct panel_backlight_default_levels {
-+	uint32_t ac_level_percentage;
-+	uint32_t dc_level_percentage;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-new file mode 100644
-index 0000000..a1e468f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-@@ -0,0 +1,328 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_OBJECT_DEFS_H__
-+#define __DAL_GRPH_OBJECT_DEFS_H__
-+
-+#include "grph_object_id.h"
-+
-+/* ********************************************************************
-+ * ********************************************************************
-+ *
-+ *  These defines shared between All Graphics Objects
-+ *
-+ * ********************************************************************
-+ * ********************************************************************
-+ */
-+
-+/* HPD unit id - HW direct translation */
-+enum hpd_source_id {
-+	HPD_SOURCEID1 = 0,
-+	HPD_SOURCEID2,
-+	HPD_SOURCEID3,
-+	HPD_SOURCEID4,
-+	HPD_SOURCEID5,
-+	HPD_SOURCEID6,
-+
-+	HPD_SOURCEID_COUNT,
-+	HPD_SOURCEID_UNKNOWN
-+};
-+
-+/* DDC unit id - HW direct translation */
-+enum channel_id {
-+	CHANNEL_ID_UNKNOWN = 0,
-+	CHANNEL_ID_DDC1,
-+	CHANNEL_ID_DDC2,
-+	CHANNEL_ID_DDC3,
-+	CHANNEL_ID_DDC4,
-+	CHANNEL_ID_DDC5,
-+	CHANNEL_ID_DDC6,
-+	CHANNEL_ID_DDC_VGA,
-+	CHANNEL_ID_I2C_PAD,
-+	CHANNEL_ID_COUNT
-+};
-+
-+#define DECODE_CHANNEL_ID(ch_id) \
-+	(ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
-+	(ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
-+	(ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
-+	(ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
-+	(ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
-+	(ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
-+	(ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
-+	(ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
-+
-+enum transmitter {
-+	TRANSMITTER_UNKNOWN = (-1L),
-+	TRANSMITTER_UNIPHY_A,
-+	TRANSMITTER_UNIPHY_B,
-+	TRANSMITTER_UNIPHY_C,
-+	TRANSMITTER_UNIPHY_D,
-+	TRANSMITTER_UNIPHY_E,
-+	TRANSMITTER_UNIPHY_F,
-+	TRANSMITTER_NUTMEG_CRT,
-+	TRANSMITTER_TRAVIS_CRT,
-+	TRANSMITTER_TRAVIS_LCD,
-+	TRANSMITTER_UNIPHY_G,
-+	TRANSMITTER_COUNT
-+};
-+
-+enum physical_phy_id {
-+	PHY_ID_UNKNOWN = (-1L),
-+	PHY_ID_0,
-+	PHY_ID_1,
-+	PHY_ID_2,
-+	PHY_ID_3,
-+	PHY_ID_4,
-+	PHY_ID_5,
-+	PHY_ID_6,
-+	PHY_ID_7,
-+	PHY_ID_8,
-+	PHY_ID_9,
-+	PHY_ID_COUNT
-+};
-+
-+/* Generic source of the synchronisation input/output signal */
-+/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
-+enum sync_source {
-+	SYNC_SOURCE_NONE = 0,
-+
-+	/* Source based on controllers */
-+	SYNC_SOURCE_CONTROLLER0,
-+	SYNC_SOURCE_CONTROLLER1,
-+	SYNC_SOURCE_CONTROLLER2,
-+	SYNC_SOURCE_CONTROLLER3,
-+	SYNC_SOURCE_CONTROLLER4,
-+	SYNC_SOURCE_CONTROLLER5,
-+
-+	/* Source based on GSL group */
-+	SYNC_SOURCE_GSL_GROUP0,
-+	SYNC_SOURCE_GSL_GROUP1,
-+	SYNC_SOURCE_GSL_GROUP2,
-+
-+	/* Source based on GSL IOs */
-+	/* These IOs normally used as GSL input/output */
-+	SYNC_SOURCE_GSL_IO_FIRST,
-+	SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
-+	SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
-+	SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
-+	SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
-+	SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
-+
-+	/* Source based on regular IOs */
-+	SYNC_SOURCE_IO_FIRST,
-+	SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
-+	SYNC_SOURCE_IO_GENERIC_B,
-+	SYNC_SOURCE_IO_GENERIC_C,
-+	SYNC_SOURCE_IO_GENERIC_D,
-+	SYNC_SOURCE_IO_GENERIC_E,
-+	SYNC_SOURCE_IO_GENERIC_F,
-+	SYNC_SOURCE_IO_HPD1,
-+	SYNC_SOURCE_IO_HPD2,
-+	SYNC_SOURCE_IO_HSYNC_A,
-+	SYNC_SOURCE_IO_VSYNC_A,
-+	SYNC_SOURCE_IO_HSYNC_B,
-+	SYNC_SOURCE_IO_VSYNC_B,
-+	SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
-+
-+	/* Misc. flow control sources */
-+	SYNC_SOURCE_DUAL_GPU_PIN
-+};
-+
-+enum trigger_edge {
-+	TRIGGER_EDGE_RISING = 0,
-+	TRIGGER_EDGE_FALLING,
-+	TRIGGER_EDGE_BOTH,
-+	TRIGGER_EDGE_DEFAULT
-+};
-+
-+/* Parameters to enable CRTC trigger */
-+struct trigger_params {
-+	enum sync_source source;
-+	enum trigger_edge edge;
-+};
-+
-+/* CRTC Static Screen event triggers */
-+struct static_screen_events {
-+	union {
-+		/* event mask to enable/disable various
-+		   trigger sources for static screen detection */
-+		struct {
-+			/* Force event high */
-+			uint32_t FRAME_START:1;
-+			/* Cursor register change */
-+			uint32_t CURSOR_MOVE:1;
-+			/* Memory write to any client other than MCIF */
-+			uint32_t MEM_WRITE:1;
-+			/* Memory write to hit memory region 0 */
-+			uint32_t MEM_REGION0_WRITE:1;
-+			/* Memory write to hit memory region 1 */
-+			uint32_t MEM_REGION1_WRITE:1;
-+			/* Memory write to hit memory region 2 */
-+			uint32_t MEM_REGION2_WRITE:1;
-+			/* Memory write to hit memory region 3 */
-+			uint32_t MEM_REGION3_WRITE:1;
-+			/* Graphics Surface Update Pending */
-+			uint32_t GFX_UPDATE:1;
-+			/* Overlay Surface Update Pending */
-+			uint32_t OVL_UPDATE:1;
-+			/* Compressed surface invalidated in FBC */
-+			uint32_t INVALIDATE_FBC_SURFACE:1;
-+			/* Register pending update in any double buffered
-+			register group in the display pipe
-+			(i.e. Blender, DCP, or SCL) */
-+			uint32_t REG_PENDING_UPDATE:1;
-+			/* Crtc_trig_a: Based on signal from any other CRTC */
-+			uint32_t CRTC_TRIG_A:1;
-+			/* Crtc_trig_b: Based on signal from any other CRTC */
-+			uint32_t CRTC_TRIG_B:1;
-+			/* Readback of CRTC nominal vertical count register
-+			by driver  indicates that OS may be trying to change
-+			mode or contents of the display therefore need to
-+			switch to higher refresh rate */
-+			uint32_t READBACK_NOMINAL_VERTICAL:1;
-+			/* Readback of CRTC dynamic vertical count register
-+			by driver  indicates that OS may be trying to change
-+			mode or contents of the display therefore need to
-+			switch to higher refresh rate */
-+			uint32_t READBACK_DYNAMIC_VERTICAL:1;
-+			/* Reserved */
-+			uint32_t RESERVED:1;
-+		} bits;
-+		uint32_t u_all;
-+	};
-+};
-+
-+
-+/*
-+ * ***************************************************************
-+ * ********************* Register programming sequences ********
-+ * ***************************************************************
-+ */
-+
-+/* GPIO/Register access sequences */
-+enum io_register_sequence {
-+	/* GLSync sequences to access SwapReady & SwapRequest
-+	GPIOs - GLSync Connector parameter */
-+	IO_REG_SEQUENCE_SWAPREADY_SET = 0,
-+	IO_REG_SEQUENCE_SWAPREADY_RESET,
-+	IO_REG_SEQUENCE_SWAPREADY_READ,
-+	IO_REG_SEQUENCE_SWAPREQUEST_SET,
-+	IO_REG_SEQUENCE_SWAPREQUEST_RESET,
-+	IO_REG_SEQUENCE_SWAPREQUEST_READ,
-+
-+	/* Frame synchronization start/stop - display index parameter */
-+	IO_REG_SEQUENCE_FRAMELOCK_STOP,
-+	IO_REG_SEQUENCE_FRAMELOCK_START,
-+
-+	/* Flip lock/unlock - GLSync Connector parameter */
-+	IO_REG_SEQUENCE_GLOBALSWAP_LOCK,
-+	IO_REG_SEQUENCE_GLOBALSWAP_UNLOCK,
-+
-+	IO_REG_SEQUENCEENUM_MAX
-+};
-+
-+#define IO_REGISTER_SEQUENCE_MAX_LENGTH 5
-+
-+/*
-+ *****************************************************************************
-+ *                             struct io_register
-+ *****************************************************************************
-+ * Generic struct for read/write register or GPIO.
-+ * It allows controlling only some bit section of register, rather then the
-+ * whole one.
-+ * For write operation should be used as following:
-+ *   1. data  = READ(Base + RegisterOffset)
-+ *   2. data &= ANDMask
-+ *   3. data |= ORMask
-+ *   4. WRITE(Base + RegisterOffset, data)
-+ *
-+ * Note: In case of regular register, ANDMask will be typically 0.
-+ *	In case of GPIO, ANDMask will have typically all bits set
-+ *	except the specific GPIO bit.
-+ *
-+ * For read operation should be used as following:
-+ *   1. data   = READ(Base + RegisterOffset)
-+ *   2. data  &= ANDMask
-+ *   3. data >>= BitShift
-+ *
-+ * Note: In case of regular register, ANDMask will be typically 0xFFFFFFFF.
-+ *	In case of GPIO, ANDMask will have typically only specific GPIO bit set
-+ *
-+ * Note: Base Address is not exposed in this structure due to
-+ *	security consideration.
-+ */
-+
-+/*
-+ * The generic sequence to program/access registers or GPIOs.
-+ * There could be 2 types of sequences - read and write.
-+ * Read sequence may have 0 or more writes and in the end one read
-+ * Write sequence may have 1 or more writes.
-+ */
-+struct io_reg_sequence {
-+	/* Ordered array of register to program */
-+	struct {
-+		/* Offset of memory mapped register or GPIO */
-+		uint32_t register_offset;
-+		/* Mask to use at AND operation (Mandatory, comes
-+		before OR operation) */
-+		uint32_t and_mask;
-+		union {
-+			/* Mask to use at OR operation (For write
-+			sequence only, comes after AND operation) */
-+			uint32_t or_mask;
-+			/* Number of bits to shift to get the actual value
-+			(For read  sequence only, comes after AND operation) */
-+			uint32_t bit_shift;
-+		};
-+	} io_registers[IO_REGISTER_SEQUENCE_MAX_LENGTH];
-+
-+	uint32_t steps_num; /* Total number of r/w steps in the sequence */
-+};
-+
-+/* Sequence ID - uniqly defines sequence on single adapter */
-+struct io_reg_sequence_id {
-+	enum io_register_sequence sequence; /* Sequence enumeration Index/ID */
-+	union {
-+		/* Refers to object to which the sequence applies.*/
-+		uint32_t index;
-+		uint32_t display_index;
-+		uint32_t controller_index;
-+		uint32_t glsync_connector_index;
-+	};
-+};
-+
-+struct fbc_info {
-+	bool fbc_enable;
-+	bool lpt_enable;
-+};
-+
-+/* Event to request TM change IRQ registration state */
-+struct hotplug_irq_data {
-+	bool disable;
-+	struct graphics_object_id connector;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-new file mode 100644
-index 0000000..fcf3eea
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -0,0 +1,285 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_OBJECT_ID_H__
-+#define __DAL_GRPH_OBJECT_ID_H__
-+
-+/* Types of graphics objects */
-+enum object_type {
-+	OBJECT_TYPE_UNKNOWN  = 0,
-+
-+	/* Direct ATOM BIOS translation */
-+	OBJECT_TYPE_GPU,
-+	OBJECT_TYPE_ENCODER,
-+	OBJECT_TYPE_CONNECTOR,
-+	OBJECT_TYPE_ROUTER,
-+	OBJECT_TYPE_GENERIC,
-+
-+	/* Driver specific */
-+	OBJECT_TYPE_AUDIO,
-+	OBJECT_TYPE_CONTROLLER,
-+	OBJECT_TYPE_CLOCK_SOURCE,
-+	OBJECT_TYPE_ENGINE,
-+
-+	OBJECT_TYPE_COUNT
-+};
-+
-+/* Enumeration inside one type of graphics objects */
-+enum object_enum_id {
-+	ENUM_ID_UNKNOWN = 0,
-+	ENUM_ID_1,
-+	ENUM_ID_2,
-+	ENUM_ID_3,
-+	ENUM_ID_4,
-+	ENUM_ID_5,
-+	ENUM_ID_6,
-+	ENUM_ID_7,
-+
-+	ENUM_ID_COUNT
-+};
-+
-+/* Generic object ids */
-+enum generic_id {
-+	GENERIC_ID_UNKNOWN = 0,
-+	GENERIC_ID_MXM_OPM,
-+	GENERIC_ID_GLSYNC,
-+	GENERIC_ID_STEREO,
-+
-+	GENERIC_ID_COUNT
-+};
-+
-+/* Controller object ids */
-+enum controller_id {
-+	CONTROLLER_ID_UNDEFINED = 0,
-+	CONTROLLER_ID_D0,
-+	CONTROLLER_ID_D1,
-+	CONTROLLER_ID_D2,
-+	CONTROLLER_ID_D3,
-+	CONTROLLER_ID_D4,
-+	CONTROLLER_ID_D5,
-+	CONTROLLER_ID_UNDERLAY0,
-+	CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
-+};
-+
-+#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
-+
-+/*
-+ * ClockSource object ids.
-+ * We maintain the order matching (more or less) ATOM BIOS
-+ * to improve optimized acquire
-+ */
-+enum clock_source_id {
-+	CLOCK_SOURCE_ID_UNDEFINED = 0,
-+	CLOCK_SOURCE_ID_PLL0,
-+	CLOCK_SOURCE_ID_PLL1,
-+	CLOCK_SOURCE_ID_PLL2,
-+	CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
-+	CLOCK_SOURCE_ID_DCPLL,
-+	CLOCK_SOURCE_ID_DFS,	/* DENTIST */
-+	CLOCK_SOURCE_ID_VCE,	/* VCE does not need a real PLL */
-+	CLOCK_SOURCE_ID_DP_DTO,	/* Used to distinguish between */
-+	/* programming pixel clock */
-+	/* and ID (Phy) clock */
-+};
-+
-+
-+/* Encoder object ids */
-+enum encoder_id {
-+	ENCODER_ID_UNKNOWN = 0,
-+
-+	/* Radeon Class Display Hardware */
-+	ENCODER_ID_INTERNAL_LVDS,
-+	ENCODER_ID_INTERNAL_TMDS1,
-+	ENCODER_ID_INTERNAL_TMDS2,
-+	ENCODER_ID_INTERNAL_DAC1,
-+	ENCODER_ID_INTERNAL_DAC2,	/* TV/CV DAC */
-+	ENCODER_ID_INTERNAL_SDVOA,
-+	ENCODER_ID_INTERNAL_SDVOB,
-+
-+	/* External Third Party Encoders */
-+	ENCODER_ID_EXTERNAL_SI170B,
-+	ENCODER_ID_EXTERNAL_CH7303,
-+	ENCODER_ID_EXTERNAL_CH7301,	/* 10 in decimal */
-+	ENCODER_ID_INTERNAL_DVO1,	/* Belongs to Radeon Display Hardware */
-+	ENCODER_ID_EXTERNAL_SDVOA,
-+	ENCODER_ID_EXTERNAL_SDVOB,
-+	ENCODER_ID_EXTERNAL_TITFP513,
-+	ENCODER_ID_INTERNAL_LVTM1,	/* not used for Radeon */
-+	ENCODER_ID_EXTERNAL_VT1623,
-+	ENCODER_ID_EXTERNAL_SI1930,	/* HDMI */
-+	ENCODER_ID_INTERNAL_HDMI,
-+
-+	/* Kaledisope (KLDSCP) Class Display Hardware */
-+	ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
-+	ENCODER_ID_INTERNAL_KLDSCP_DVO1,
-+	ENCODER_ID_INTERNAL_KLDSCP_DAC1,
-+	ENCODER_ID_INTERNAL_KLDSCP_DAC2,	/* Shared with CV/TV and CRT */
-+	/* External TMDS (dual link) */
-+	ENCODER_ID_EXTERNAL_SI178,
-+	ENCODER_ID_EXTERNAL_MVPU_FPGA,	/* MVPU FPGA chip */
-+	ENCODER_ID_INTERNAL_DDI,
-+	ENCODER_ID_EXTERNAL_VT1625,
-+	ENCODER_ID_EXTERNAL_SI1932,
-+	ENCODER_ID_EXTERNAL_AN9801,	/* External Display Port */
-+	ENCODER_ID_EXTERNAL_DP501,	/* External Display Port */
-+	ENCODER_ID_INTERNAL_UNIPHY,
-+	ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
-+	ENCODER_ID_INTERNAL_UNIPHY1,
-+	ENCODER_ID_INTERNAL_UNIPHY2,
-+	ENCODER_ID_EXTERNAL_NUTMEG,
-+	ENCODER_ID_EXTERNAL_TRAVIS,
-+
-+	ENCODER_ID_INTERNAL_WIRELESS,	/* Internal wireless display encoder */
-+	ENCODER_ID_INTERNAL_UNIPHY3,
-+
-+	ENCODER_ID_EXTERNAL_GENERIC_DVO = 0xFF
-+};
-+
-+
-+/* Connector object ids */
-+enum connector_id {
-+	CONNECTOR_ID_UNKNOWN = 0,
-+	CONNECTOR_ID_SINGLE_LINK_DVII,
-+	CONNECTOR_ID_DUAL_LINK_DVII,
-+	CONNECTOR_ID_SINGLE_LINK_DVID,
-+	CONNECTOR_ID_DUAL_LINK_DVID,
-+	CONNECTOR_ID_VGA,
-+	CONNECTOR_ID_HDMI_TYPE_A,
-+	CONNECTOR_ID_NOT_USED,
-+	CONNECTOR_ID_LVDS,
-+	CONNECTOR_ID_PCIE,
-+	CONNECTOR_ID_HARDCODE_DVI,
-+	CONNECTOR_ID_DISPLAY_PORT,
-+	CONNECTOR_ID_EDP,
-+	CONNECTOR_ID_MXM,
-+	CONNECTOR_ID_WIRELESS,		/* wireless display pseudo-connector */
-+	CONNECTOR_ID_MIRACAST,		/* used for VCE encode display path
-+					 * for Miracast */
-+
-+	CONNECTOR_ID_COUNT
-+};
-+
-+
-+/* Audio object ids */
-+enum audio_id {
-+	AUDIO_ID_UNKNOWN = 0,
-+	AUDIO_ID_INTERNAL_AZALIA
-+};
-+
-+
-+/* Engine object ids */
-+enum engine_id {
-+	ENGINE_ID_DIGA,
-+	ENGINE_ID_DIGB,
-+	ENGINE_ID_DIGC,
-+	ENGINE_ID_DIGD,
-+	ENGINE_ID_DIGE,
-+	ENGINE_ID_DIGF,
-+	ENGINE_ID_DIGG,
-+	ENGINE_ID_DVO,
-+	ENGINE_ID_DACA,
-+	ENGINE_ID_DACB,
-+	ENGINE_ID_VCE,	/* wireless display pseudo-encoder */
-+
-+	ENGINE_ID_COUNT,
-+	ENGINE_ID_UNKNOWN = (-1L)
-+};
-+
-+union supported_stream_engines {
-+	struct {
-+		uint32_t ENGINE_ID_DIGA:1;
-+		uint32_t ENGINE_ID_DIGB:1;
-+		uint32_t ENGINE_ID_DIGC:1;
-+		uint32_t ENGINE_ID_DIGD:1;
-+		uint32_t ENGINE_ID_DIGE:1;
-+		uint32_t ENGINE_ID_DIGF:1;
-+		uint32_t ENGINE_ID_DIGG:1;
-+		uint32_t ENGINE_ID_DVO:1;
-+		uint32_t ENGINE_ID_DACA:1;
-+		uint32_t ENGINE_ID_DACB:1;
-+		uint32_t ENGINE_ID_VCE:1;
-+	} engine;
-+	uint32_t u_all;
-+};
-+
-+
-+/*
-+ *****************************************************************************
-+ * graphics_object_id struct
-+ *
-+ * graphics_object_id is a very simple struct wrapping 32bit Graphics
-+ * Object identication
-+ *
-+ * This struct should stay very simple
-+ *  No dependencies at all (no includes)
-+ *  No debug messages or asserts
-+ *  No #ifndef and preprocessor directives
-+ *  No grow in space (no more data member)
-+ *****************************************************************************
-+ */
-+
-+struct graphics_object_id {
-+	uint32_t  id:8;
-+	uint32_t  enum_id:4;
-+	uint32_t  type:4;
-+	uint32_t  reserved:16; /* for padding. total size should be u32 */
-+};
-+
-+/* some simple functions for convenient graphics_object_id handle */
-+
-+static inline struct graphics_object_id dal_graphics_object_id_init(
-+	uint32_t id,
-+	enum object_enum_id enum_id,
-+	enum object_type type)
-+{
-+	struct graphics_object_id result = {
-+		id, enum_id, type, 0
-+	};
-+
-+	return result;
-+}
-+
-+bool dal_graphics_object_id_is_valid(
-+	struct graphics_object_id id);
-+bool dal_graphics_object_id_is_equal(
-+	struct graphics_object_id id1,
-+	struct graphics_object_id id2);
-+uint32_t dal_graphics_object_id_to_uint(
-+	struct graphics_object_id id);
-+
-+
-+enum controller_id dal_graphics_object_id_get_controller_id(
-+	struct graphics_object_id id);
-+enum clock_source_id dal_graphics_object_id_get_clock_source_id(
-+	struct graphics_object_id id);
-+enum encoder_id dal_graphics_object_id_get_encoder_id(
-+	struct graphics_object_id id);
-+enum connector_id dal_graphics_object_id_get_connector_id(
-+	struct graphics_object_id id);
-+enum audio_id dal_graphics_object_id_get_audio_id(
-+	struct graphics_object_id id);
-+enum engine_id dal_graphics_object_id_get_engine_id(
-+	struct graphics_object_id id);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h b/drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
-new file mode 100644
-index 0000000..10fb8e2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_ADJUSTMENT_SET_H__
-+#define __DAL_HW_ADJUSTMENT_SET_H__
-+
-+#include "include/hw_adjustment_types.h"
-+
-+struct hw_adjustment_gamma_ramp;
-+
-+struct hw_adjustment_set {
-+	struct hw_adjustment_gamma_ramp *gamma_ramp;
-+	struct hw_adjustment_deflicker *deflicker_filter;
-+	struct hw_adjustment_value *coherent;
-+	struct hw_adjustment_value *h_sync;
-+	struct hw_adjustment_value *v_sync;
-+	struct hw_adjustment_value *composite_sync;
-+	struct hw_adjustment_value *backlight;
-+	struct hw_adjustment_value *vb_level;
-+	struct hw_adjustment_color_control *color_control;
-+	union hw_adjustment_bit_depth_reduction *bit_depth;
-+};
-+/*
-+struct hw_adjustment *dal_adjustment_set_get_by_id(
-+	struct hw_adjustment_set *adjustment_set,
-+	enum hw_adjustment_id id);*/
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h b/drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
-new file mode 100644
-index 0000000..cfae832
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
-@@ -0,0 +1,205 @@
-+#ifndef __DAL_HW_ADJUSTMENT_TYPES_H__
-+#define __DAL_HW_ADJUSTMENT_TYPES_H__
-+
-+#include "hw_sequencer_types.h"
-+
-+enum hw_adjustment_id {
-+	HW_ADJUSTMENT_ID_COLOR_CONTROL,
-+	HW_ADJUSTMENT_ID_GAMMA_LUT,
-+	HW_ADJUSTMENT_ID_GAMMA_RAMP,
-+	HW_ADJUSTMENT_ID_DEFLICKER,
-+	HW_ADJUSTMENT_ID_SHARPNESS_CONTROL,
-+	HW_ADJUSTMENT_ID_TIMING,
-+	HW_ADJUSTMENT_ID_TIMING_AND_PIXEL_CLOCK,
-+	HW_ADJUSTMENT_ID_OVERSCAN,
-+	HW_ADJUSTMENT_ID_UNDERSCAN_TYPE,
-+	HW_ADJUSTMENT_ID_VERTICAL_SYNC,
-+	HW_ADJUSTMENT_ID_HORIZONTAL_SYNC,
-+	HW_ADJUSTMENT_ID_COMPOSITE_SYNC,
-+	HW_ADJUSTMENT_ID_VIDEO_STANDARD,
-+	HW_ADJUSTMENT_ID_BACKLIGHT,
-+	HW_ADJUSTMENT_ID_BIT_DEPTH_REDUCTION,
-+	HW_ADJUSTMENT_ID_REDUCED_BLANKING,
-+	HW_ADJUSTMENT_ID_COHERENT,
-+	/* OVERLAY ADJUSTMENTS*/
-+	HW_ADJUSTMENT_ID_OVERLAY,
-+	HW_ADJUSTMENT_ID_OVERLAY_ALPHA,
-+	HW_ADJUSTMENT_ID_OVERLAY_VARIABLE_GAMMA,
-+	HW_ADJUSTMENT_ID_COUNT,
-+	HW_ADJUSTMENT_ID_UNDEFINED,
-+};
-+
-+struct hw_adjustment_deflicker {
-+	int32_t hp_factor;
-+	uint32_t hp_divider;
-+	int32_t lp_factor;
-+	uint32_t lp_divider;
-+	int32_t sharpness;
-+	bool enable_sharpening;
-+};
-+
-+struct hw_adjustment_value {
-+	union {
-+		uint32_t ui_value;
-+		int32_t i_value;
-+	};
-+};
-+
-+enum hw_color_adjust_option {
-+	HWS_COLOR_MATRIX_HW_DEFAULT = 1,
-+	HWS_COLOR_MATRIX_SW
-+};
-+
-+enum {
-+	HW_TEMPERATURE_MATRIX_SIZE = 9,
-+	HW_TEMPERATURE_MATRIX_SIZE_WITH_OFFSET = 12
-+};
-+
-+struct hw_adjustment_color_control {
-+	enum hw_color_space color_space;
-+	enum hw_color_adjust_option option;
-+	enum pixel_format surface_pixel_format;
-+	enum dc_color_depth color_depth;
-+	uint32_t lb_color_depth;
-+	int32_t contrast;
-+	int32_t saturation;
-+	int32_t brightness;
-+	int32_t hue;
-+	uint32_t adjust_divider;
-+	uint32_t temperature_divider;
-+	uint32_t temperature_matrix[HW_TEMPERATURE_MATRIX_SIZE];
-+};
-+
-+struct hw_underscan_adjustment {
-+	struct hw_adjustment_deflicker deflicker;
-+	struct overscan_info hw_overscan;
-+};
-+
-+struct hw_underscan_adjustment_data {
-+	enum hw_adjustment_id hw_adj_id;
-+	struct hw_underscan_adjustment hw_underscan_adj;
-+};
-+
-+union hw_adjustment_bit_depth_reduction {
-+	uint32_t raw;
-+	struct {
-+		uint32_t TRUNCATE_ENABLED:1;
-+		uint32_t TRUNCATE_DEPTH:2;
-+		uint32_t TRUNCATE_MODE:1;
-+		uint32_t SPATIAL_DITHER_ENABLED:1;
-+		uint32_t SPATIAL_DITHER_DEPTH:2;
-+		uint32_t SPATIAL_DITHER_MODE:2;
-+		uint32_t RGB_RANDOM:1;
-+		uint32_t FRAME_RANDOM:1;
-+		uint32_t HIGHPASS_RANDOM:1;
-+		uint32_t FRAME_MODULATION_ENABLED:1;
-+		uint32_t FRAME_MODULATION_DEPTH:2;
-+		uint32_t TEMPORAL_LEVEL:1;
-+		uint32_t FRC_25:2;
-+		uint32_t FRC_50:2;
-+		uint32_t FRC_75:2;
-+	} bits;
-+};
-+
-+struct hw_color_control_range {
-+	struct hw_adjustment_range contrast;
-+	struct hw_adjustment_range saturation;
-+	struct hw_adjustment_range brightness;
-+	struct hw_adjustment_range hue;
-+	struct hw_adjustment_range temperature;
-+};
-+
-+enum hw_surface_type {
-+	HW_OVERLAY_SURFACE = 1,
-+	HW_GRAPHIC_SURFACE
-+};
-+
-+/* LUT type for GammaCorrection */
-+struct hw_gamma_lut {
-+	uint32_t red;
-+	uint32_t green;
-+	uint32_t blue;
-+};
-+
-+struct hw_devc_lut {
-+	uint8_t red;
-+	uint8_t green;
-+	uint8_t blue;
-+	uint8_t reserved;
-+};
-+
-+struct hw_adjustment_gamma_lut {
-+	struct hw_gamma_lut *pGammaLut;
-+	uint32_t size_in_elements;
-+	enum pixel_format surface_pixel_format;
-+};
-+
-+
-+enum hw_gamma_ramp_type {
-+	HW_GAMMA_RAMP_UNITIALIZED = 0,
-+	HW_GAMMA_RAMP_DEFAULT,
-+	HW_GAMMA_RAMP_RBG_256x3x16,
-+	HW_GAMMA_RAMP_RBG_DXGI_1
-+};
-+
-+#define HW_GAMMA_RAMP_RBG_256 256
-+
-+struct hw_gamma_ramp_rgb256x3x16 {
-+	unsigned short red[HW_GAMMA_RAMP_RBG_256];
-+	unsigned short green[HW_GAMMA_RAMP_RBG_256];
-+	unsigned short blue[HW_GAMMA_RAMP_RBG_256];
-+};
-+
-+union hw_gamma_flags {
-+	uint32_t raw;
-+	struct {
-+		uint32_t gamma_ramp_array :1;
-+		uint32_t graphics_degamma_srgb :1;
-+		uint32_t overlay_degamma_srgb :1;
-+		uint32_t apply_degamma :1;
-+		uint32_t reserved :28;
-+	} bits;
-+};
-+
-+struct hw_regamma_coefficients {
-+	int32_t gamma[3];
-+	int32_t a0[3];
-+	int32_t a1[3];
-+	int32_t a2[3];
-+	int32_t a3[3];
-+};
-+
-+struct hw_regamma_ramp {
-+	/* Gamma ramp packed as RGB */
-+	unsigned short gamma[256 * 3];
-+};
-+
-+struct hw_regamma_lut {
-+	union hw_gamma_flags flags;
-+	union {
-+		struct hw_regamma_ramp gamma;
-+		struct hw_regamma_coefficients coeff;
-+	};
-+};
-+
-+union hw_gamma_flag {
-+	uint32_t uint;
-+	struct {
-+		uint32_t config_is_changed :1;
-+		uint32_t regamma_update :1;
-+		uint32_t gamma_update :1;
-+		uint32_t reserved :29;
-+	} bits;
-+};
-+
-+struct hw_adjustment_gamma_ramp {
-+	uint32_t size;
-+	enum hw_gamma_ramp_type type;
-+	enum pixel_format surface_pixel_format;
-+	enum hw_color_space color_space;
-+	struct hw_regamma_lut regamma;
-+	union hw_gamma_flag flag;
-+	struct hw_gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h b/drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
-new file mode 100644
-index 0000000..28ac018
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_PATH_MODE_SET_INTERFACE_H__
-+#define __DAL_HW_PATH_MODE_SET_INTERFACE_H__
-+
-+struct hw_path_mode;
-+struct hw_path_mode_set;
-+
-+struct hw_path_mode_set *dal_hw_path_mode_set_create(void);
-+
-+void dal_hw_path_mode_set_destroy(struct hw_path_mode_set **set);
-+
-+bool dal_hw_path_mode_set_add(
-+	struct hw_path_mode_set *set,
-+	struct hw_path_mode *path_mode,
-+	uint32_t *index);
-+
-+struct hw_path_mode *dal_hw_path_mode_set_get_path_by_index(
-+	const struct hw_path_mode_set *set,
-+	uint32_t index);
-+
-+uint32_t dal_hw_path_mode_set_get_paths_number(
-+	const struct hw_path_mode_set *set);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-new file mode 100644
-index 0000000..ddd78d6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-@@ -0,0 +1,388 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_SEQUENCER_INTERFACE_H__
-+#define __DAL_HW_SEQUENCER_INTERFACE_H__
-+
-+#include "hw_sequencer_types.h"
-+#include "hw_adjustment_types.h"
-+#include "include/display_clock_interface.h"
-+#include "include/scaler_types.h"
-+#include "include/grph_csc_types.h"
-+#include "plane_types.h"
-+
-+#include "adapter_service_interface.h"
-+
-+enum hwss_result {
-+	HWSS_RESULT_OK,
-+	HWSS_RESULT_ERROR,
-+	HWSS_RESULT_NO_BANDWIDTH,
-+	HWSS_RESULT_OUT_OF_RANGE,
-+	HWSS_RESULT_NOT_SUPPORTED,
-+	HWSS_RESULT_UNKNOWN
-+};
-+
-+struct hws_init_data {
-+	struct adapter_service *as;
-+	struct dal_context *dal_context;
-+};
-+
-+/* TODO: below is three almost equal structures.
-+ * We should decide what to do with them */
-+struct blank_stream_param {
-+	struct display_path *display_path;
-+	uint32_t link_idx;
-+	struct hw_crtc_timing timing;
-+	struct link_settings link_settings;
-+};
-+
-+struct enable_stream_param {
-+	struct display_path *display_path;
-+	uint32_t link_idx;
-+	struct hw_crtc_timing timing;
-+	struct link_settings link_settings;
-+
-+	const struct hw_path_mode *path_mode;
-+};
-+
-+struct enable_link_param {
-+	struct display_path *display_path;
-+	uint32_t link_idx;
-+	struct hw_crtc_timing timing;
-+	struct link_settings link_settings;
-+
-+	bool optimized_programming;
-+	const struct hw_path_mode *path_mode;
-+};
-+
-+struct validate_link_param {
-+	const struct display_path *display_path;
-+	uint32_t link_idx;
-+	struct link_settings link_settings;
-+};
-+
-+struct set_dp_phy_pattern_param {
-+	struct display_path *display_path;
-+	uint32_t link_idx;
-+	enum dp_test_pattern test_pattern;
-+	const uint8_t *custom_pattern;
-+	uint32_t cust_pattern_size;
-+};
-+
-+struct hw_global_objects;
-+struct hw_sequencer;
-+struct hw_adjustment;
-+struct hw_path_mode_set;
-+struct hw_path_mode;
-+struct hwss_build_params;
-+struct controller;
-+
-+void dal_hw_sequencer_mute_audio_endpoint(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	bool mute);
-+
-+void dal_hw_sequencer_enable_audio_endpoint(
-+	struct hw_sequencer *hws,
-+	struct link_settings *ls,
-+	struct display_path *display_path,
-+	bool enable);
-+
-+enum hwss_result dal_hw_sequencer_reset_audio_device(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+enum hwss_result dal_hw_sequencer_validate_link(
-+	struct hw_sequencer *hws,
-+	const struct validate_link_param *param);
-+
-+bool dal_hw_sequencer_is_supported_dp_training_pattern3(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	uint32_t link_idx);
-+
-+enum hwss_result dal_hw_sequencer_set_dp_phy_pattern(
-+	struct hw_sequencer *hws,
-+	const struct set_dp_phy_pattern_param *param);
-+
-+enum hwss_result dal_hw_sequencer_set_lane_settings(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	const struct link_training_settings *link_settings);
-+
-+void dal_hw_sequencer_set_test_pattern(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode *path_mode,
-+	enum dp_test_pattern test_pattern,
-+	const struct link_training_settings *link_settings,
-+	const uint8_t *custom_pattern,
-+	uint8_t cust_pattern_size);
-+
-+bool dal_hw_sequencer_has_audio_bandwidth_changed(
-+	struct hw_sequencer *hws,
-+	const struct hw_path_mode *old,
-+	const struct hw_path_mode *new);
-+
-+void dal_hw_sequencer_enable_azalia_audio_jack_presence(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+void dal_hw_sequencer_disable_azalia_audio_jack_presence(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+void dal_hw_sequencer_enable_memory_requests(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode *path_mode);
-+
-+void dal_hw_sequencer_update_info_packets(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode *path_mode);
-+
-+/* Static validation for a SINGLE path mode.
-+ * Already "active" paths (if any) are NOT taken into account. */
-+enum hwss_result dal_hw_sequencer_validate_display_path_mode(
-+	struct hw_sequencer *hws,
-+	const struct hw_path_mode *path_mode);
-+
-+/* Validation for a SET of path modes, including Video Memory Bandwidth
-+ * validation. */
-+enum hwss_result dal_hw_sequencer_validate_display_hwpms(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode_set *path_set);
-+
-+struct hw_adjustment_gamma_ramp;
-+
-+enum hwss_result dal_hw_sequencer_set_gamma_ramp_adjustment(
-+	struct hw_sequencer *hws,
-+	const struct display_path *display_path,
-+	struct hw_adjustment_gamma_ramp *adjusment);
-+
-+enum hwss_result dal_hw_sequencer_set_color_control_adjustment(
-+	struct hw_sequencer *hws,
-+	struct controller *crtc,
-+	struct hw_adjustment_color_control *adjustment);
-+
-+enum hwss_result dal_hw_sequencer_set_vertical_sync_adjustment(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	struct hw_adjustment_value *adjustment);
-+
-+enum hwss_result dal_hw_sequencer_set_horizontal_sync_adjustment(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	struct hw_adjustment_value *adjustment);
-+
-+enum hwss_result dal_hw_sequencer_set_composite_sync_adjustment(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	struct hw_adjustment_value *adjustment);
-+
-+enum hwss_result dal_hw_sequencer_enable_sync_output(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+enum hwss_result dal_hw_sequencer_disable_sync_output(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+enum hwss_result dal_hw_sequencer_set_backlight_adjustment(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path,
-+	struct hw_adjustment_value *adjustment);
-+
-+void dal_hw_sequencer_disable_memory_requests(
-+	struct hw_sequencer *hws,
-+	const struct hw_path_mode *path_mode);
-+
-+enum hwss_result dal_hw_sequencer_enable_link(
-+	struct hw_sequencer *hws,
-+	const struct enable_link_param *in);
-+
-+void dal_hw_sequencer_disable_link(
-+	struct hw_sequencer *hws,
-+	const struct enable_link_param *in);
-+
-+void dal_hw_sequencer_enable_stream(
-+	struct hw_sequencer *hws,
-+	const struct enable_stream_param *in);
-+
-+void dal_hw_sequencer_disable_stream(
-+	struct hw_sequencer *hws,
-+	const struct enable_stream_param *in);
-+
-+void dal_hw_sequencer_blank_stream(
-+	struct hw_sequencer *hws,
-+	const struct blank_stream_param *in);
-+
-+void dal_hw_sequencer_unblank_stream(
-+	struct hw_sequencer *hws,
-+	const struct blank_stream_param *in);
-+
-+enum hwss_result dal_hw_sequencer_set_clocks_and_clock_state(
-+		struct hw_sequencer *hws,
-+		struct hw_global_objects *g_obj,
-+		const struct minimum_clocks_calculation_result *min_clk_in,
-+		enum clocks_state required_clocks_state);
-+
-+enum hwss_result dal_hw_sequencer_set_mode(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode_set *path_set);
-+
-+enum signal_type dal_hw_sequencer_detect_sink(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+enum signal_type dal_hw_sequencer_detect_load(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+bool dal_hw_sequencer_is_sink_present(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+void dal_hw_sequencer_psr_setup(
-+	struct hw_sequencer *hws,
-+	const struct hw_path_mode *path_mode,
-+	const struct psr_caps *psr_caps);
-+
-+void dal_hw_sequencer_psr_enable(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+void dal_hw_sequencer_psr_disable(
-+	struct hw_sequencer *hws,
-+	struct display_path *display_path);
-+
-+void dal_hw_sequencer_program_drr(
-+		struct hw_sequencer *hws,
-+		const struct hw_path_mode *path_mode);
-+
-+enum hwss_result dal_hw_sequencer_set_safe_displaymark(
-+		struct hw_sequencer *hws,
-+		struct hw_path_mode_set *path_set);
-+
-+enum hwss_result dal_hw_sequencer_set_displaymark(
-+		struct hw_sequencer *hws,
-+		struct hw_path_mode_set *path_set);
-+
-+void dal_hw_sequencer_destroy(struct hw_sequencer **hws);
-+
-+struct hw_sequencer *dal_hw_sequencer_create(
-+		struct hws_init_data *hws_init_data);
-+
-+enum hwss_result dal_hw_sequencer_set_overscan_adj(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode_set *set,
-+	struct hw_underscan_adjustment_data *hw_underscan);
-+
-+bool dal_hw_sequencer_enable_line_buffer_power_gating(
-+	struct line_buffer *lb,
-+	enum controller_id id,
-+	enum pixel_type pixel_type,
-+	uint32_t src_pixel_width,
-+	uint32_t dst_pixel_width,
-+	struct scaling_taps *taps,
-+	enum lb_pixel_depth lb_depth,
-+	uint32_t src_height,
-+	uint32_t dst_height,
-+	bool interlaced);
-+
-+void dal_hw_sequencer_build_scaler_parameter(
-+	const struct hw_path_mode *path_mode,
-+	const struct scaling_taps *taps,
-+	bool build_timing_required,
-+	struct scaler_data *scaler_data);
-+
-+void dal_hw_sequencer_update_info_frame(
-+	const struct hw_path_mode *hw_path_mode);
-+
-+enum hwss_result dal_hw_sequencer_set_bit_depth_reduction_adj(
-+	struct hw_sequencer *hws,
-+	struct display_path *disp_path,
-+	union hw_adjustment_bit_depth_reduction *bit_depth);
-+
-+bool dal_hw_sequencer_is_support_custom_gamut_adj(
-+	struct hw_sequencer *hws,
-+	struct display_path *disp_path,
-+	enum hw_surface_type surface_type);
-+
-+enum hwss_result dal_hw_sequencer_get_hw_color_adj_range(
-+	struct hw_sequencer *hws,
-+	struct display_path *disp_path,
-+	struct hw_color_control_range *hw_color_range);
-+
-+bool dal_hw_sequencer_is_support_custom_gamma_coefficients(
-+	struct hw_sequencer *hws,
-+	struct display_path *disp_path,
-+	enum hw_surface_type surface_type);
-+
-+enum hwss_result dal_hw_sequencer_build_csc_adjust(
-+	struct hw_sequencer *hws,
-+	struct hw_adjustment_color_control *color_control,
-+	struct grph_csc_adjustment *adjust);
-+
-+void dal_hw_sequencer_build_gamma_ramp_adj_params(
-+		const struct hw_adjustment_gamma_ramp *adjusment,
-+		struct gamma_parameters *gamma_param,
-+		struct gamma_ramp *ramp);
-+
-+void translate_from_hw_to_controller_regamma(
-+		const struct hw_regamma_lut *hw_regamma,
-+		struct regamma_lut *regamma);
-+
-+void dal_hw_sequencer_enable_wireless_idle_detection(
-+		struct hw_sequencer *hws,
-+		bool enable);
-+
-+/* Cursor interface */
-+enum hwss_result dal_hw_sequencer_set_cursor_position(
-+		struct hw_sequencer *hws,
-+		struct display_path *dp,
-+		const struct dc_cursor_position *position);
-+
-+enum hwss_result dal_hw_sequencer_set_cursor_attributes(
-+		struct hw_sequencer *hws,
-+		struct display_path *dp,
-+		const struct dc_cursor_attributes *attributes);
-+
-+/* Underlay/MPO interface */
-+enum hwss_result dal_hw_sequencer_set_plane_config(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode_set *path_set,
-+	uint32_t display_index);
-+
-+bool dal_hw_sequencer_update_plane_address(
-+	struct hw_sequencer *hws,
-+	struct display_path *dp,
-+	uint32_t num_planes,
-+	struct plane_addr_flip_info *info);
-+
-+void dal_hw_sequencer_prepare_to_release_planes(
-+	struct hw_sequencer *hws,
-+	struct hw_path_mode_set *path_set,
-+	uint32_t display_index);
-+
-+#endif /* __DAL_HW_SEQUENCER_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-new file mode 100644
-index 0000000..d5d7059
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -0,0 +1,305 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_SEQUENCER_TYPES_H__
-+#define __DAL_HW_SEQUENCER_TYPES_H__
-+
-+#include "signal_types.h"
-+#include "grph_object_defs.h"
-+#include "link_service_types.h"
-+#include "plane_types.h"
-+
-+struct color_quality {
-+	uint32_t bpp_graphics;
-+	uint32_t bpp_backend_video;
-+};
-+
-+enum {
-+	HW_MAX_NUM_VIEWPORTS = 2,
-+	HW_CURRENT_PIPE_INDEX = 0,
-+	HW_OTHER_PIPE_INDEX = 1
-+};
-+
-+struct hw_view_port_adjustment {
-+	int32_t start_adjustment;
-+	int32_t width;
-+
-+	enum controller_id controller_id;
-+};
-+
-+struct hw_view_port_adjustments {
-+	uint32_t view_ports_num;
-+	struct hw_view_port_adjustment adjustments[HW_MAX_NUM_VIEWPORTS];
-+};
-+
-+/* Timing standard */
-+enum hw_timing_standard {
-+	HW_TIMING_STANDARD_UNDEFINED,
-+	HW_TIMING_STANDARD_DMT,
-+	HW_TIMING_STANDARD_GTF,
-+	HW_TIMING_STANDARD_CVT,
-+	HW_TIMING_STANDARD_CVT_RB,
-+	HW_TIMING_STANDARD_CEA770,
-+	HW_TIMING_STANDARD_CEA861,
-+	HW_TIMING_STANDARD_HDMI,
-+	HW_TIMING_STANDARD_TV_NTSC,
-+	HW_TIMING_STANDARD_TV_NTSC_J,
-+	HW_TIMING_STANDARD_TV_PAL,
-+	HW_TIMING_STANDARD_TV_PAL_M,
-+	HW_TIMING_STANDARD_TV_PAL_CN,
-+	HW_TIMING_STANDARD_TV_SECAM,
-+	/* for explicit timings from VBIOS, EDID etc. */
-+	HW_TIMING_STANDARD_EXPLICIT
-+};
-+
-+/* identical to struct crtc_ranged_timing_control
-+ * defined in controller\timing_generator_types.h */
-+struct hw_ranged_timing_control {
-+	/* set to 1 to force dynamic counter V_COUNT
-+	 * to lock to constant rate counter V_COUNT_NOM
-+	 * on page flip event in dynamic refresh mode
-+	 * when switching from a low refresh rate to nominal refresh rate */
-+	bool force_lock_on_event;
-+	/* set to 1 to force CRTC2 (slave) to lock to CRTC1 (master) VSync
-+	 * in order to overlap their blank regions for MC clock changes */
-+	bool lock_to_master_vsync;
-+
-+	/* set to 1 to program Static Screen Detection Masks
-+	 * without enabling dynamic refresh rate */
-+	bool program_static_screen_mask;
-+	/* set to 1 to program Dynamic Refresh Rate */
-+	bool program_dynamic_refresh_rate;
-+	/* set to 1 to force disable Dynamic Refresh Rate */
-+	bool force_disable_drr;
-+
-+	/* event mask to enable/disable various trigger sources
-+	 * for static screen detection */
-+	struct static_screen_events event_mask;
-+
-+	/* Number of consecutive static screen frames before static state is
-+	 * asserted. */
-+	uint32_t static_frame_count;
-+};
-+
-+/* define the structure of Dynamic Refresh Mode */
-+struct hw_ranged_timing {
-+	/* defines the minimum possible vertical dimension of display timing
-+	 * for CRTC as supported by the panel */
-+	uint32_t vertical_total_min;
-+	/* defines the maximum possible vertical dimension of display timing
-+	 * for CRTC as supported by the panel */
-+	uint32_t vertical_total_max;
-+
-+	struct hw_ranged_timing_control control;
-+};
-+
-+/* CRTC timing structure */
-+struct hw_crtc_timing {
-+	uint32_t h_total;
-+	uint32_t h_addressable;
-+	uint32_t h_overscan_left;
-+	uint32_t h_overscan_right;
-+	uint32_t h_sync_start;
-+	uint32_t h_sync_width;
-+
-+	uint32_t v_total;
-+	uint32_t v_addressable;
-+	uint32_t v_overscan_top;
-+	uint32_t v_overscan_bottom;
-+	uint32_t v_sync_start;
-+	uint32_t v_sync_width;
-+
-+	struct hw_ranged_timing ranged_timing;
-+
-+	/* in KHz */
-+	uint32_t pixel_clock;
-+
-+	enum hw_timing_standard timing_standard;
-+	enum dc_color_depth color_depth;
-+	enum dc_pixel_encoding pixel_encoding;
-+
-+	struct {
-+		uint32_t INTERLACED:1;
-+		uint32_t DOUBLESCAN:1;
-+		uint32_t PIXEL_REPETITION:4; /* 1...10 */
-+		uint32_t HSYNC_POSITIVE_POLARITY:1;
-+		uint32_t VSYNC_POSITIVE_POLARITY:1;
-+		/* frame should be packed for 3D
-+		 * (currently this refers to HDMI 1.4a FramePacking format */
-+		uint32_t HORZ_COUNT_BY_TWO:1;
-+		uint32_t PACK_3D_FRAME:1;
-+		/* 0 - left eye polarity, 1 - right eye polarity */
-+		uint32_t RIGHT_EYE_3D_POLARITY:1;
-+		/* DVI-DL High-Color mode */
-+		uint32_t HIGH_COLOR_DL_MODE:1;
-+		uint32_t Y_ONLY:1;
-+		/* HDMI 2.0 - Support scrambling for TMDS character
-+		 * rates less than or equal to 340Mcsc */
-+		uint32_t LTE_340MCSC_SCRAMBLE:1;
-+	} flags;
-+};
-+
-+struct hw_scaling_info {
-+	struct view src;
-+	struct view dst;
-+	enum signal_type signal;
-+};
-+
-+enum hw_color_space {
-+	HW_COLOR_SPACE_UNKNOWN = 0,
-+	HW_COLOR_SPACE_SRGB_FULL_RANGE,
-+	HW_COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	HW_COLOR_SPACE_YPBPR601,
-+	HW_COLOR_SPACE_YPBPR709,
-+	HW_COLOR_SPACE_YCBCR601,
-+	HW_COLOR_SPACE_YCBCR709,
-+	HW_COLOR_SPACE_YCBCR601_YONLY,
-+	HW_COLOR_SPACE_YCBCR709_YONLY,
-+	HW_COLOR_SPACE_NMVPU_SUPERAA,
-+};
-+
-+enum hw_overlay_color_space {
-+	HW_OVERLAY_COLOR_SPACE_UNKNOWN,
-+	HW_OVERLAY_COLOR_SPACE_BT709,
-+	HW_OVERLAY_COLOR_SPACE_BT601,
-+	HW_OVERLAY_COLOR_SPACE_SMPTE240,
-+	HW_OVERLAY_COLOR_SPACE_RGB
-+};
-+
-+enum hw_overlay_backend_bpp {
-+	HW_OVERLAY_BACKEND_BPP_UNKNOWN,
-+	HW_OVERLAY_BACKEND_BPP32_FULL_BANDWIDTH,
-+	HW_OVERLAY_BACKEND_BPP16_FULL_BANDWIDTH,
-+	HW_OVERLAY_BACKEND_BPP32_HALF_BANDWIDTH,
-+};
-+enum hw_overlay_format {
-+	HW_OVERLAY_FORMAT_UNKNOWN,
-+	HW_OVERLAY_FORMAT_YUY2,
-+	HW_OVERLAY_FORMAT_UYVY,
-+	HW_OVERLAY_FORMAT_RGB565,
-+	HW_OVERLAY_FORMAT_RGB555,
-+	HW_OVERLAY_FORMAT_RGB32,
-+	HW_OVERLAY_FORMAT_YUV444,
-+	HW_OVERLAY_FORMAT_RGB32_2101010
-+};
-+
-+enum hw_scale_options {
-+	HW_SCALE_OPTION_UNKNOWN,
-+	HW_SCALE_OPTION_OVERSCAN, /* multimedia pass through mode */
-+	HW_SCALE_OPTION_UNDERSCAN
-+};
-+
-+enum hw_stereo_format {
-+	HW_STEREO_FORMAT_NONE = 0,
-+	HW_STEREO_FORMAT_SIDE_BY_SIDE = 1,
-+	HW_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
-+	HW_STEREO_FORMAT_FRAME_ALTERNATE = 3,
-+	HW_STEREO_FORMAT_ROW_INTERLEAVED = 5,
-+	HW_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
-+	HW_STEREO_FORMAT_CHECKER_BOARD = 7 /* the same as pixel interleave */
-+};
-+
-+enum hw_dithering_options {
-+	HW_DITHERING_OPTION_UNKNOWN,
-+	HW_DITHERING_OPTION_SKIP_PROGRAMMING,
-+	HW_DITHERING_OPTION_ENABLE,
-+	HW_DITHERING_OPTION_DISABLE
-+};
-+
-+struct hw_stereo_mixer_params {
-+	bool sub_sampling;
-+	bool single_pipe;
-+};
-+
-+
-+
-+struct hw_action_flags {
-+	uint32_t RESYNC_PATH:1;
-+	uint32_t TIMING_CHANGED:1;
-+	uint32_t PIXEL_ENCODING_CHANGED:1;
-+	uint32_t GAMUT_CHANGED:1;
-+	uint32_t TURN_OFF_VCC:1;
-+};
-+
-+enum hw_sync_request {
-+	HW_SYNC_REQUEST_NONE = 0,
-+	HW_SYNC_REQUEST_SET_INTERPATH,
-+	HW_SYNC_REQUEST_SET_GL_SYNC_GENLOCK,
-+	HW_SYNC_REQUEST_SET_GL_SYNC_FREE_RUN,
-+	HW_SYNC_REQUEST_SET_GL_SYNC_SHADOW,
-+	HW_SYNC_REQUEST_RESET_GLSYNC,
-+	HW_SYNC_REQUEST_RESYNC_GLSYNC,
-+	HW_SYNC_REQUEST_SET_STEREO3D
-+};
-+
-+struct hw_sync_info {
-+	enum hw_sync_request sync_request;
-+	uint32_t target_pixel_clock; /* in KHz */
-+	enum sync_source sync_source;
-+};
-+
-+/* TODO hw_info_frame and hw_info_packet structures are same as in encoder
-+ * merge it*/
-+struct hw_info_packet {
-+	bool valid;
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t hb3;
-+	uint8_t sb[28];
-+};
-+
-+struct hw_info_frame {
-+	/* Auxiliary Video Information */
-+	struct hw_info_packet avi_info_packet;
-+	struct hw_info_packet gamut_packet;
-+	struct hw_info_packet vendor_info_packet;
-+	/* Source Product Description */
-+	struct hw_info_packet spd_packet;
-+	/* Video Stream Configuration */
-+	struct hw_info_packet vsc_packet;
-+};
-+
-+
-+enum channel_command_type {
-+	CHANNEL_COMMAND_I2C,
-+	CHANNEL_COMMAND_I2C_OVER_AUX,
-+	CHANNEL_COMMAND_AUX
-+};
-+
-+
-+/* maximum TMDS transmitter pixel clock is 165 MHz. So it is KHz */
-+#define	TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
-+#define	NATIVE_HDMI_MAX_PIXEL_CLOCK_IN_KHZ 297000
-+
-+struct hw_adjustment_range {
-+	int32_t hw_default;
-+	int32_t min;
-+	int32_t max;
-+	int32_t step;
-+	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-new file mode 100644
-index 0000000..b961d24
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-@@ -0,0 +1,127 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2CAUX_INTERFACE_H__
-+#define __DAL_I2CAUX_INTERFACE_H__
-+
-+#include "ddc_interface.h"
-+#include "adapter_service_interface.h"
-+
-+struct i2c_payload {
-+	bool write;
-+	uint8_t address;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+enum i2c_command_engine {
-+	I2C_COMMAND_ENGINE_DEFAULT,
-+	I2C_COMMAND_ENGINE_SW,
-+	I2C_COMMAND_ENGINE_HW
-+};
-+
-+struct i2c_command {
-+	struct i2c_payload *payloads;
-+	uint8_t number_of_payloads;
-+
-+	enum i2c_command_engine engine;
-+
-+	/* expressed in KHz
-+	 * zero means "use default value" */
-+	uint32_t speed;
-+};
-+
-+#define DEFAULT_AUX_MAX_DATA_SIZE 16
-+#define AUX_MAX_DEFER_WRITE_RETRY 20
-+
-+struct aux_payload {
-+	/* set following flag to read/write I2C data,
-+	 * reset it to read/write DPCD data */
-+	bool i2c_over_aux;
-+	/* set following flag to write data,
-+	 * reset it to read data */
-+	bool write;
-+	uint32_t address;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+struct aux_command {
-+	struct aux_payload *payloads;
-+	uint8_t number_of_payloads;
-+
-+	/* expressed in milliseconds
-+	 * zero means "use default value" */
-+	uint32_t defer_delay;
-+
-+	/* zero means "use default value" */
-+	uint32_t max_defer_write_retry;
-+};
-+
-+union aux_config {
-+	struct {
-+		uint32_t ALLOW_AUX_WHEN_HPD_LOW:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct i2caux;
-+
-+struct i2caux *dal_i2caux_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx);
-+
-+bool dal_i2caux_submit_i2c_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct i2c_command *cmd);
-+
-+bool dal_i2caux_submit_aux_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct aux_command *cmd);
-+
-+void dal_i2caux_keep_engine_power_up(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	bool keep_power_up);
-+
-+bool dal_i2caux_start_gtc_sync(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc);
-+
-+bool dal_i2caux_stop_gtc_sync(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc);
-+
-+void dal_i2caux_configure_aux(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	union aux_config cfg);
-+
-+void dal_i2caux_destroy(
-+	struct i2caux **ptr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/irq_interface.h b/drivers/gpu/drm/amd/dal/include/irq_interface.h
-new file mode 100644
-index 0000000..0faa48f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/irq_interface.h
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_INTERFACE_H__
-+#define __DAL_IRQ_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+
-+struct irq;
-+
-+enum gpio_result dal_irq_open(
-+	struct irq *irq);
-+
-+enum gpio_result dal_irq_get_value(
-+	const struct irq *irq,
-+	uint32_t *value);
-+
-+enum dc_irq_source dal_irq_get_source(
-+	const struct irq *irq);
-+
-+enum dc_irq_source dal_irq_get_rx_source(
-+	const struct irq *irq);
-+
-+enum gpio_result dal_irq_setup_hpd_filter(
-+	struct irq *irq,
-+	struct gpio_hpd_config *config);
-+
-+void dal_irq_close(
-+	struct irq *irq);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/irq_service_interface.h b/drivers/gpu/drm/amd/dal/include/irq_service_interface.h
-new file mode 100644
-index 0000000..7ae4aeb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/irq_service_interface.h
-@@ -0,0 +1,55 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_INTERFACE_H__
-+#define __DAL_IRQ_SERVICE_INTERFACE_H__
-+
-+#include "include/adapter_service_types.h"
-+
-+struct irq_service_init_data {
-+	struct dc_context *ctx;
-+};
-+
-+struct irq_service *dal_irq_service_create(
-+	enum dce_version version,
-+	struct irq_service_init_data *init_data);
-+
-+void dal_irq_service_destroy(struct irq_service **irq_service);
-+
-+bool dal_irq_service_set(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source,
-+	bool enable);
-+
-+bool dal_irq_service_ack(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source);
-+
-+enum dc_irq_source dal_irq_service_to_irq_source(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/isr_config_types.h b/drivers/gpu/drm/amd/dal/include/isr_config_types.h
-new file mode 100644
-index 0000000..2e822f0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/isr_config_types.h
-@@ -0,0 +1,157 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ISR_TYPES_H__
-+#define __DAL_ISR_TYPES_H__
-+
-+#include "grph_object_id.h"
-+#include "dc_types.h"
-+
-+struct plane_config;
-+enum {
-+	/*move to common*/
-+	MAX_COFUNC_PATH_COMMON = 6,
-+	/*CZ worst case*/
-+	MAX_NUM_PLANES = 4
-+};
-+
-+enum plane_type {
-+	PLANE_TYPE_GRPH = 0,
-+	PLANE_TYPE_VIDEO
-+};
-+
-+struct plane_id {
-+	enum plane_type select;
-+	enum controller_id controller_id;
-+};
-+
-+union display_plane_mask {
-+	struct {
-+		uint32_t CLONE_PRIMARY_CONTROLLER_ID_SET:1;
-+		uint32_t INTERLEAVED_CONTROLLER_ID_SET:1;
-+		uint32_t RESERVED:30;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct display_plane_format {
-+    /* always valid */
-+	union display_plane_mask mask;
-+	/* always valid */
-+	uint32_t display_index;
-+    /* always valid */
-+	enum dc_timing_3d_format format;
-+	/* always valid */
-+	enum controller_id controller_id;
-+	/* valid only if CLONE_PRIMARY_CONTROLLER_ID_SET on */
-+	enum controller_id clone_primary_controller_id;
-+	/* valid only if stereo interleave mode is on */
-+	enum controller_id interleave_controller_id;
-+	/* valid only if crtc stereo  is on */
-+	uint32_t right_eye_3d_polarity:1;
-+};
-+
-+struct display_plane_set {
-+	struct display_plane_format
-+		set_mode_formats[MAX_COFUNC_PATH_COMMON];
-+	uint32_t reset_mode_index[
-+		MAX_COFUNC_PATH_COMMON];
-+	uint32_t num_set_mode_formats;
-+	uint32_t num_reset_mode_index;
-+};
-+
-+enum layers_setup {
-+	LAYERS_SETUP_NOTHING = 0,
-+	LAYERS_SETUP_SET,
-+	LAYERS_SETUP_FREE
-+};
-+
-+union plane_cfg_internal_flags {
-+	struct {
-+		uint32_t PLANE_OWNS_CRTC:1;
-+		uint32_t RESERVED:31;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+
-+struct plane_cfg_internal {
-+	const struct plane_config *config;
-+	enum layers_setup setup;
-+	union plane_cfg_internal_flags flags;
-+};
-+
-+enum lock_type {
-+	LOCK_TYPE_GRPH = 0,
-+	LOCK_TYPE_SURF,
-+	LOCK_TYPE_SCL,
-+	LOCK_TYPE_BLND,
-+    /* lock the given pipe with options above */
-+	LOCK_TYPE_THIS
-+};
-+
-+enum alpha_mode {
-+	ALPHA_MODE_PIXEL = 0,
-+	ALPHA_MODE_PIXEL_AND_GLOBAL = 1,
-+	ALPHA_MODE_GLOBAL = 2
-+};
-+
-+union alpha_mode_cfg_flag {
-+	struct {
-+		uint32_t MODE_IS_SET:1;
-+		uint32_t MODE_MULTIPLIED_IS_SET:1;
-+		uint32_t GLOBAL_ALPHA_IS_SET:1;
-+		uint32_t GLOBAL_ALPHA_GAIN_IS_SET:1;
-+
-+		uint32_t MULTIPLIED_MODE:1;
-+		uint32_t GLOBAL_ALPHA:8;
-+		/* total 21 bits! */
-+		uint32_t GLOBAL_ALPHA_GAIN:8;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct alpha_mode_cfg {
-+	union alpha_mode_cfg_flag flags;
-+	enum alpha_mode mode;
-+};
-+
-+union pending_cfg_changes {
-+	struct {
-+		uint32_t SCL_UNLOCK_REQUIRED:1;
-+		uint32_t BLND_UNLOCK_REQUIRED:1;
-+		uint32_t INPUT_CSC_SWITCH_REQUIRED:1;
-+		uint32_t OUTPUT_CSC_SWITCH_REQUIRED:1;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct pending_plane_changes {
-+	union pending_cfg_changes changes;
-+	struct plane_id id;
-+};
-+
-+
-+#endif /* __DAL_ISR_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/link_encoder_types.h b/drivers/gpu/drm/amd/dal/include/link_encoder_types.h
-new file mode 100644
-index 0000000..2a59902
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/link_encoder_types.h
-@@ -0,0 +1,32 @@
-+/*
-+ * link_encoder_types.h
-+ *
-+ *  Created on: Oct 6, 2015
-+ *      Author: yonsun
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DAL_DEV_INCLUDE_LINK_ENCODER_TYPES_H_
-+#define DRIVERS_GPU_DRM_AMD_DAL_DEV_INCLUDE_LINK_ENCODER_TYPES_H_
-+
-+#include "encoder_interface.h"
-+
-+struct link_enc_status {
-+	int dummy; /*TODO*/
-+};
-+struct link_encoder {
-+	struct adapter_service *adapter_service;
-+	int32_t be_engine_offset;
-+	int32_t aux_channel_offset;
-+	int32_t transmitter_offset;
-+	struct dc_context *ctx;
-+	struct graphics_object_id id;
-+	struct graphics_object_id connector;
-+	uint32_t input_signals;
-+	uint32_t output_signals;
-+	enum engine_id preferred_engine;
-+	struct encoder_feature_support features;
-+	enum transmitter transmitter;
-+	enum hpd_source_id hpd_source;
-+};
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_INCLUDE_LINK_ENCODER_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_interface.h b/drivers/gpu/drm/amd/dal/include/link_service_interface.h
-new file mode 100644
-index 0000000..2ac9311
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_interface.h
-@@ -0,0 +1,202 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LINK_SERVICE_INTERFACE_H__
-+#define __DAL_LINK_SERVICE_INTERFACE_H__
-+
-+#include "include/link_service_types.h"
-+
-+/* forward declaration */
-+struct link_service;
-+struct hw_crtc_timing;
-+struct hw_path_mode;
-+struct display_path;
-+struct hw_path_mode_set;
-+struct link_training_preference;
-+enum ddc_result;
-+
-+struct link_service *dal_link_service_create(
-+	struct link_service_init_data *init_data);
-+
-+void dal_link_service_destroy(
-+	struct link_service **ls);
-+
-+enum link_service_type dal_ls_get_link_service_type(
-+	struct link_service *link_service);
-+
-+bool dal_ls_validate_mode_timing(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	const struct hw_crtc_timing *timing,
-+	struct link_validation_flags flags);
-+
-+bool dal_ls_get_mst_sink_info(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct mst_sink_info *sink_info);
-+
-+bool dal_ls_get_gtc_sync_status(
-+	struct link_service *ls);
-+
-+bool dal_ls_enable_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+bool dal_ls_disable_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *poath_mode);
-+
-+bool dal_ls_optimized_enable_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct display_path *display_path);
-+
-+void dal_ls_update_stream_features(
-+	struct link_service *ls,
-+	const struct hw_path_mode *path_mode);
-+
-+bool dal_ls_blank_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+bool dal_ls_unblank_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+bool dal_ls_pre_mode_change(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+bool dal_ls_post_mode_change(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+bool dal_ls_power_on_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+bool dal_ls_power_off_stream(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	struct hw_path_mode *path_mode);
-+
-+void dal_ls_retrain_link(
-+	struct link_service *ls,
-+	struct hw_path_mode_set *path_set);
-+
-+bool dal_ls_get_current_link_setting(
-+	struct link_service *ls,
-+	struct link_settings *link_settings);
-+
-+void dal_ls_connect_link(
-+	struct link_service *ls,
-+	const struct display_path *display_path,
-+	bool initial_detection);
-+
-+void dal_ls_disconnect_link(
-+	struct link_service *ls);
-+
-+bool dal_ls_is_mst_network_present(
-+	struct link_service *ls);
-+
-+void dal_ls_invalidate_down_stream_devices(
-+	struct link_service *ls);
-+
-+bool dal_ls_are_mst_displays_cofunctional(
-+	struct link_service *ls,
-+	const uint32_t *array_display_index,
-+	uint32_t len);
-+
-+bool dal_ls_is_sink_present_at_display_index(
-+	struct link_service *ls,
-+	uint32_t display_index);
-+
-+struct ddc_service *dal_ls_obtain_mst_ddc_service(
-+	struct link_service *ls,
-+	uint32_t display_index);
-+
-+void dal_ls_release_mst_ddc_service(
-+	struct link_service *ls,
-+	struct ddc_service *ddc_service);
-+
-+void dal_ls_release_hw(
-+	struct link_service *ls);
-+
-+bool dal_ls_associate_link(
-+	struct link_service *ls,
-+	uint32_t display_index,
-+	uint32_t link_index,
-+	bool is_internal_link);
-+
-+bool dal_dpsst_ls_set_overridden_trained_link_settings(
-+	struct link_service *ls,
-+	const struct link_settings *link_settings);
-+
-+void dal_dpsst_ls_set_link_training_preference(
-+	struct link_service *ls,
-+	const struct link_training_preference *ltp);
-+
-+struct link_training_preference
-+	dal_dpsst_ls_get_link_training_preference(
-+	struct link_service *ls);
-+
-+bool dal_ls_should_send_notification(
-+	struct link_service *ls);
-+
-+uint32_t dal_ls_get_notification_display_index(
-+	struct link_service *ls);
-+
-+enum ddc_result dal_dpsst_ls_read_dpcd_data(
-+	struct link_service *ls,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t size);
-+
-+enum ddc_result dal_dpsst_ls_write_dpcd_data(
-+	struct link_service *ls,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t size);
-+
-+bool dal_ls_is_link_psr_supported(struct link_service *ls);
-+
-+bool dal_ls_is_stream_drr_supported(struct link_service *ls);
-+
-+void dal_ls_set_link_psr_capabilities(
-+		struct link_service *ls,
-+		struct psr_caps *psr_caps);
-+
-+void dal_ls_get_link_psr_capabilities(
-+		struct link_service *ls,
-+		struct psr_caps *psr_caps);
-+
-+#endif /* __DAL_LINK_SERVICE_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-new file mode 100644
-index 0000000..0df5687
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -0,0 +1,428 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LINK_SERVICE_TYPES_H__
-+#define __DAL_LINK_SERVICE_TYPES_H__
-+
-+#include "dal_services_types.h"
-+
-+#include "grph_object_id.h"
-+#include "dpcd_defs.h"
-+#include "dal_types.h"
-+#include "irq_types.h"
-+
-+/*struct mst_mgr_callback_object;*/
-+struct ddc;
-+struct irq_manager;
-+
-+enum link_service_type {
-+	LINK_SERVICE_TYPE_LEGACY = 0,
-+	LINK_SERVICE_TYPE_DP_SST,
-+	LINK_SERVICE_TYPE_DP_MST,
-+	LINK_SERVICE_TYPE_MAX
-+};
-+
-+struct link_validation_flags {
-+	uint32_t DYNAMIC_VALIDATION:1;
-+	uint32_t CANDIDATE_TIMING:1;
-+	uint32_t START_OF_VALIDATION:1;
-+};
-+
-+/* Post Cursor 2 is optional for transmitter
-+ * and it applies only to the main link operating at HBR2
-+ */
-+enum post_cursor2 {
-+	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
-+	POST_CURSOR2_LEVEL1,
-+	POST_CURSOR2_LEVEL2,
-+	POST_CURSOR2_LEVEL3,
-+	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
-+};
-+
-+enum voltage_swing {
-+	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
-+	VOLTAGE_SWING_LEVEL1,
-+	VOLTAGE_SWING_LEVEL2,
-+	VOLTAGE_SWING_LEVEL3,
-+	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
-+};
-+
-+enum pre_emphasis {
-+	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
-+	PRE_EMPHASIS_LEVEL1,
-+	PRE_EMPHASIS_LEVEL2,
-+	PRE_EMPHASIS_LEVEL3,
-+	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
-+};
-+
-+enum dpcd_value_mask {
-+	DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F,
-+	DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40,
-+	DPCD_VALUE_MASK_MAX_LANE_COUNT_ENHANCED_FRAME_EN = 0x80,
-+	DPCD_VALUE_MASK_MAX_DOWNSPREAD = 0x01,
-+	DPCD_VALUE_MASK_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE = 0x01
-+};
-+
-+enum dp_power_state {
-+	DP_POWER_STATE_D0 = 1,
-+	DP_POWER_STATE_D3
-+};
-+
-+enum dpcd_downstream_port_types {
-+	DPCD_DOWNSTREAM_DP,
-+	DPCD_DOWNSTREAM_VGA,
-+	DPCD_DOWNSTREAM_DVI_HDMI,
-+	/* has no EDID (TV, CV) */
-+	DPCD_DOWNSTREAM_NON_DDC
-+};
-+
-+enum edp_revision {
-+	/* eDP version 1.1 or lower */
-+	EDP_REVISION_11 = 0x00,
-+	/* eDP version 1.2 */
-+	EDP_REVISION_12 = 0x01,
-+	/* eDP version 1.3 */
-+	EDP_REVISION_13 = 0x02
-+};
-+
-+enum lane_count {
-+	LANE_COUNT_UNKNOWN = 0,
-+	LANE_COUNT_ONE = 1,
-+	LANE_COUNT_TWO = 2,
-+	LANE_COUNT_FOUR = 4,
-+	LANE_COUNT_EIGHT = 8,
-+	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
-+};
-+
-+/* This is actually a reference clock (27MHz) multiplier
-+ * 162MBps bandwidth for 1.62GHz like rate,
-+ * 270MBps for 2.70GHz,
-+ * 324MBps for 3.24Ghz,
-+ * 540MBps for 5.40GHz
-+ */
-+enum link_rate {
-+	LINK_RATE_UNKNOWN = 0,
-+	LINK_RATE_LOW = 0x06,
-+	LINK_RATE_HIGH = 0x0A,
-+	LINK_RATE_RBR2 = 0x0C,
-+	LINK_RATE_HIGH2 = 0x14
-+};
-+
-+enum {
-+	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
-+};
-+
-+enum link_spread {
-+	LINK_SPREAD_DISABLED = 0x00,
-+	/* 0.5 % downspread 30 kHz */
-+	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
-+	/* 0.5 % downspread 33 kHz */
-+	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
-+};
-+
-+/* DPCD_ADDR_DOWNSTREAM_PORT_PRESENT register value */
-+union dpcd_downstream_port {
-+	struct {
-+#if defined(LITTLEENDIAN_CPU)
-+		uint8_t PRESENT:1;
-+		uint8_t TYPE:2;
-+		uint8_t FORMAT_CONV:1;
-+		uint8_t RESERVED:4;
-+#elif defined(BIGENDIAN_CPU)
-+		uint8_t RESERVED:4;
-+		uint8_t FORMAT_CONV:1;
-+		uint8_t TYPE:2;
-+		uint8_t PRESENT:1;
-+#else
-+	#error ARCH not defined!
-+#endif
-+	} bits;
-+
-+	uint8_t raw;
-+};
-+
-+/* DPCD_ADDR_SINK_COUNT register value */
-+union dpcd_sink_count {
-+	struct {
-+#if defined(LITTLEENDIAN_CPU)
-+		uint8_t SINK_COUNT:6;
-+		uint8_t CP_READY:1;
-+		uint8_t RESERVED:1;
-+#elif defined(BIGENDIAN_CPU)
-+		uint8_t RESERVED:1;
-+		uint8_t CP_READY:1;
-+		uint8_t SINK_COUNT:6;
-+#else
-+	#error ARCH not defined!
-+#endif
-+	} bits;
-+
-+	uint8_t raw;
-+};
-+
-+struct link_settings {
-+	enum lane_count lane_count;
-+	enum link_rate link_rate;
-+	enum link_spread link_spread;
-+};
-+
-+struct lane_settings {
-+	enum voltage_swing VOLTAGE_SWING;
-+	enum pre_emphasis PRE_EMPHASIS;
-+	enum post_cursor2 POST_CURSOR2;
-+};
-+
-+struct link_training_settings {
-+	struct link_settings link_settings;
-+	struct lane_settings lane_settings[LANE_COUNT_DP_MAX];
-+	bool allow_invalid_msa_timing_param;
-+};
-+
-+enum hw_dp_training_pattern {
-+	HW_DP_TRAINING_PATTERN_1 = 0,
-+	HW_DP_TRAINING_PATTERN_2,
-+	HW_DP_TRAINING_PATTERN_3
-+};
-+
-+/*TODO: Move this enum test harness*/
-+/* Test patterns*/
-+enum dp_test_pattern {
-+	/* Input data is pass through Scrambler
-+	 * and 8b10b Encoder straight to output*/
-+	DP_TEST_PATTERN_VIDEO_MODE = 0,
-+	/* phy test patterns*/
-+	DP_TEST_PATTERN_D102,
-+	DP_TEST_PATTERN_SYMBOL_ERROR,
-+	DP_TEST_PATTERN_PRBS7,
-+
-+	DP_TEST_PATTERN_80BIT_CUSTOM,
-+	DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE,
-+
-+	/* Link Training Patterns */
-+	DP_TEST_PATTERN_TRAINING_PATTERN1,
-+	DP_TEST_PATTERN_TRAINING_PATTERN2,
-+	DP_TEST_PATTERN_TRAINING_PATTERN3,
-+
-+	/* link test patterns*/
-+	DP_TEST_PATTERN_COLOR_SQUARES,
-+	DP_TEST_PATTERN_COLOR_SQUARES_CEA,
-+	DP_TEST_PATTERN_VERTICAL_BARS,
-+	DP_TEST_PATTERN_HORIZONTAL_BARS,
-+	DP_TEST_PATTERN_COLOR_RAMP,
-+
-+	/* audio test patterns*/
-+	DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
-+	DP_TEST_PATTERN_AUDIO_SAWTOOTH,
-+
-+	DP_TEST_PATTERN_UNSUPPORTED
-+};
-+
-+enum dp_panel_mode {
-+	/* not required */
-+	DP_PANEL_MODE_DEFAULT,
-+	/* standard mode for eDP */
-+	DP_PANEL_MODE_EDP,
-+	/* external chips specific settings */
-+	DP_PANEL_MODE_SPECIAL
-+};
-+
-+/**
-+ * @brief LinkServiceInitOptions to set certain bits
-+ */
-+struct link_service_init_options {
-+	uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1;
-+};
-+
-+/**
-+ * @brief data required to initialize LinkService
-+ */
-+struct link_service_init_data {
-+	/* number of displays indices which the MST Mgr would manange*/
-+	uint32_t num_of_displays;
-+	enum link_service_type link_type;
-+	/*struct mst_mgr_callback_object*topology_change_callback;*/
-+	/* native aux access */
-+	struct ddc_service *dpcd_access_srv;
-+	/* for calling HWSS to program HW */
-+	struct hw_sequencer *hwss;
-+	/* the source which to register IRQ on */
-+	enum dc_irq_source irq_src_hpd_rx;
-+	enum dc_irq_source irq_src_dp_sink;
-+	/* other init options such as SW Workarounds */
-+	struct link_service_init_options init_options;
-+	uint32_t connector_enum_id;
-+	struct graphics_object_id connector_id;
-+	struct adapter_service *adapter_service;
-+	struct dc_context *ctx;
-+	struct topology_mgr *tm;
-+};
-+
-+/**
-+ * @brief LinkServiceInitOptions to set certain bits
-+ */
-+struct LinkServiceInitOptions {
-+	uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1;
-+};
-+
-+/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
-+union dpcd_training_lane_set {
-+	struct {
-+#if defined(LITTLEENDIAN_CPU)
-+		uint8_t VOLTAGE_SWING_SET:2;
-+		uint8_t MAX_SWING_REACHED:1;
-+		uint8_t PRE_EMPHASIS_SET:2;
-+		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
-+		/* following is reserved in DP 1.1 */
-+		uint8_t POST_CURSOR2_SET:2;
-+#elif defined(BIGENDIAN_CPU)
-+		uint8_t POST_CURSOR2_SET:2;
-+		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
-+		uint8_t PRE_EMPHASIS_SET:2;
-+		uint8_t MAX_SWING_REACHED:1;
-+		uint8_t VOLTAGE_SWING_SET:2;
-+#else
-+	#error ARCH not defined!
-+#endif
-+	} bits;
-+
-+	uint8_t raw;
-+};
-+
-+/* DPCD_ADDR_TRAINING_LANEx_SET2 registers value - since DP 1.2 */
-+union dpcd_training_lanes_set2 {
-+	struct {
-+#if defined(LITTLEENDIAN_CPU)
-+		uint8_t LANE0_POST_CURSOR2_SET:2;
-+		uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1;
-+		uint8_t LANE0_RESERVED:1;
-+		uint8_t LANE1_POST_CURSOR2_SET:2;
-+		uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1;
-+		uint8_t LANE1_RESERVED:1;
-+#elif defined(BIGENDIAN_CPU)
-+		uint8_t LANE1_RESERVED:1;
-+		uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1;
-+		uint8_t LANE1_POST_CURSOR2_SET:2;
-+		uint8_t LANE0_RESERVED:1;
-+		uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1;
-+		uint8_t LANE0_POST_CURSOR2_SET:2;
-+#else
-+	#error ARCH not defined!
-+#endif
-+	} bits;
-+
-+	uint8_t raw;
-+};
-+
-+/**
-+ * @brief represent the 16 byte
-+ *  global unique identifier
-+ */
-+struct mst_guid {
-+	uint8_t ids[16];
-+};
-+
-+/**
-+ * @brief represents the relative address used
-+ * to identify a node in MST topology network
-+ */
-+struct mst_rad {
-+	/* number of links. rad[0] up to
-+	 * rad [linkCount - 1] are valid. */
-+	uint32_t rad_link_count;
-+	/* relative address. rad[0] is the
-+	 * first device connected to the source.	*/
-+	uint8_t rad[15];
-+	/* extra 10 bytes for underscores; for e.g.:2_1_8*/
-+	int8_t rad_str[25];
-+};
-+
-+/**
-+ * @brief this structure is used to report
-+ * properties associated to a sink device
-+ */
-+struct mst_sink_info {
-+	/* global unique identifier */
-+	struct mst_guid guid;
-+	/* relative address */
-+	struct mst_rad  rad;
-+	/* total bandwidth available on the DP connector */
-+	uint32_t total_available_bandwidth_in_mbps;
-+	/* bandwidth allocated to the sink device. */
-+	uint32_t allocated_bandwidth_in_mbps;
-+	/* bandwidth consumed to support for the current mode. */
-+	uint32_t consumed_bandwidth_in_mbps;
-+};
-+
-+/**
-+ * @brief represent device information in MST topology
-+ */
-+struct mst_device_info {
-+	/* global unique identifier*/
-+	struct mst_guid guid;
-+	/* relative address*/
-+	struct mst_rad  rad;
-+};
-+
-+/* DP MST stream allocation (payload bandwidth number) */
-+struct dp_mst_stream_allocation {
-+	/* stream engine id (DIG) */
-+	enum engine_id engine;
-+	/* number of slots required for the DP stream in
-+	 * transport packet */
-+	uint32_t slot_count;
-+	uint32_t pbn;
-+	uint32_t pbn_per_slot;
-+};
-+
-+/* DP MST stream allocation table */
-+struct dp_mst_stream_allocation_table {
-+	/* number of DP video streams */
-+	uint32_t stream_count;
-+	/* array of stream allocations */
-+	struct dp_mst_stream_allocation stream_allocations[1];
-+};
-+
-+struct dp_test_event_data {
-+	/*size of parameters (starting from params) in bytes*/
-+	uint32_t size;
-+	/*parameters block*/
-+	uint32_t params[1];
-+};
-+
-+struct psr_caps {
-+	/* These parameters are from PSR capabilities reported by Sink DPCD. */
-+	uint8_t psr_version;
-+	uint32_t psr_rfb_setup_time;
-+	bool psr_exit_link_training_req;
-+
-+	/* These parameters are calculated in Driver, based on display timing
-+	 * and Sink capabilities.
-+	 * If VBLANK region is too small and Sink takes a long time to power up
-+	 * Remote Frame Buffer, it may take an extra frame to enter PSR */
-+	bool psr_frame_capture_indication_req;
-+	uint32_t psr_sdp_transmit_line_num_deadline;
-+};
-+
-+#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h
-new file mode 100644
-index 0000000..4d945ea
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h
-@@ -0,0 +1,153 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_INTERFACE_H__
-+#define __DAL_LOGGER_INTERFACE_H__
-+
-+#include "logger_types.h"
-+
-+struct dal_logger;
-+struct dc_context;
-+union logger_flags;
-+
-+/*
-+ * TODO: This logger functionality needs to be implemented and reworked.
-+ */
-+
-+
-+/*
-+ *
-+ * DAL logger functionality
-+ *
-+ */
-+
-+struct dal_logger *dal_logger_create(struct dc_context *ctx);
-+
-+uint32_t dal_logger_destroy(struct dal_logger **logger);
-+
-+uint32_t dal_logger_get_mask(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major, enum log_minor lvl_minor);
-+
-+uint32_t dal_logger_set_mask(
-+		struct dal_logger *logger,
-+		enum log_major lvl_major, enum log_minor lvl_minor);
-+
-+uint32_t dal_logger_get_masks(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major);
-+
-+void dal_logger_set_masks(
-+	struct dal_logger *logger,
-+	enum log_major lvl_major, uint32_t log_mask);
-+
-+uint32_t dal_logger_unset_mask(
-+		struct dal_logger *logger,
-+		enum log_major lvl_major, enum log_minor lvl_minor);
-+
-+bool dal_logger_should_log(
-+		struct dal_logger *logger,
-+		enum log_major major,
-+		enum log_minor minor);
-+
-+uint32_t dal_logger_get_flags(
-+		struct dal_logger *logger);
-+
-+void dal_logger_set_flags(
-+		struct dal_logger *logger,
-+		union logger_flags flags);
-+
-+void dal_logger_write(
-+		struct dal_logger *logger,
-+		enum log_major major,
-+		enum log_minor minor,
-+		const char *msg,
-+		...);
-+
-+void dal_logger_append(
-+		struct log_entry *entry,
-+		const char *msg,
-+		...);
-+
-+uint32_t dal_logger_read(
-+		struct dal_logger *logger,
-+		uint32_t output_buffer_size,
-+		char *output_buffer,
-+		uint32_t *bytes_read,
-+		bool single_line);
-+
-+void dal_logger_open(
-+		struct dal_logger *logger,
-+		struct log_entry *entry,
-+		enum log_major major,
-+		enum log_minor minor);
-+
-+void dal_logger_close(struct log_entry *entry);
-+
-+uint32_t dal_logger_get_buffer_size(struct dal_logger *logger);
-+
-+uint32_t dal_logger_set_buffer_size(
-+		struct dal_logger *logger,
-+		uint32_t new_size);
-+
-+const struct log_major_info *dal_logger_enum_log_major_info(
-+		struct dal_logger *logger,
-+		unsigned int enum_index);
-+
-+const struct log_minor_info *dal_logger_enum_log_minor_info(
-+		struct dal_logger *logger,
-+		enum log_major major,
-+		unsigned int enum_index);
-+
-+/* Any function which is empty or have incomplete implementation should be
-+ * marked by this macro.
-+ * Note that the message will be printed exactly once for every function
-+ * it is used in order to avoid repeating of the same message. */
-+#define DAL_LOGGER_NOT_IMPL(log_minor, fmt, ...) \
-+{ \
-+	static bool print_not_impl = true; \
-+\
-+	if (print_not_impl == true) { \
-+		print_not_impl = false; \
-+		dal_logger_write(ctx->logger, LOG_MAJOR_WARNING, \
-+		log_minor, "DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
-+	} \
-+}
-+
-+/******************************************************************************
-+ * Convenience macros to save on typing.
-+ *****************************************************************************/
-+
-+#define DC_ERROR(...) \
-+	dal_logger_write(dc_ctx->logger, \
-+		LOG_MAJOR_ERROR, LOG_MINOR_COMPONENT_DC, \
-+		__VA_ARGS__);
-+
-+#define DC_SYNC_INFO(...) \
-+	dal_logger_write(dc_ctx->logger, \
-+		LOG_MAJOR_SYNC, LOG_MINOR_SYNC_TIMING, \
-+		__VA_ARGS__);
-+
-+#endif /* __DAL_LOGGER_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
-new file mode 100644
-index 0000000..6147999
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
-@@ -0,0 +1,356 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_TYPES_H__
-+#define __DAL_LOGGER_TYPES_H__
-+
-+
-+/*
-+ * TODO: This logger functionality needs to be implemented and reworked.
-+ */
-+
-+
-+struct dal_logger;
-+
-+enum log_major {
-+/*00*/
-+	LOG_MAJOR_ERROR = 0,	/*< DAL subcomponent error MSG*/
-+/*01*/  LOG_MAJOR_WARNING,	/*< DAL subcomponent warning MSG*/
-+/*02*/  LOG_MAJOR_INTERFACE_TRACE,/*< DAL subcomponent interface tracing*/
-+/*03*/  LOG_MAJOR_HW_TRACE,	/*< Log ASIC register read/write,
-+				* ATOMBIOS exec table call and delays*/
-+
-+/*04*/  LOG_MAJOR_MST,		/*< related to multi-stream*/
-+/*05*/  LOG_MAJOR_DCS,		/*< related to Dcs*/
-+/*06*/  LOG_MAJOR_DCP,		/*< related to Dcp grph and ovl,gamam and csc*/
-+/*07*/  LOG_MAJOR_BIOS,		/*< related to BiosParser*/
-+/*08*/  LOG_MAJOR_REGISTER,	/*< register access*/
-+/*09*/  LOG_MAJOR_INFO_PACKETS,	/*< info packets*/
-+/*10*/  LOG_MAJOR_DSAT,		/*< related
-+				*	to Display System Analysis Tool*/
-+/*11*/  LOG_MAJOR_EC,		/*< External Components - MCIL Events/queries,
-+				*	PPLib notifications/queries*/
-+/*12*/  LOG_MAJOR_BWM,		/*< related to Bandwidth Manager*/
-+/*13*/  LOG_MAJOR_MODE_ENUM,	/*< related to mode enumeration*/
-+/*14*/  LOG_MAJOR_I2C_AUX,	/*< i2c and aux channel log*/
-+/*15*/  LOG_MAJOR_LINE_BUFFER,	/*< Line Buffer object logging activity*/
-+/*16*/  LOG_MAJOR_HWSS,		/*< HWSS object logging activity*/
-+/*17*/  LOG_MAJOR_OPTIMIZATION,	/*< Optimization code path*/
-+/*18*/  LOG_MAJOR_PERF_MEASURE,	/*< Performance measurement dumps*/
-+/*19*/  LOG_MAJOR_SYNC,		/*< related to HW and SW Synchronization*/
-+/*20*/  LOG_MAJOR_BACKLIGHT,	/*< related to backlight */
-+/*21*/  LOG_MAJOR_INTERRUPTS,	/*< logging for all interrupts */
-+
-+/*22*/  LOG_MAJOR_TM,		/*< related to Topology Manager*/
-+/*23*/  LOG_MAJOR_DISPLAY_SERVICE, /*< related to Display Service*/
-+/*24*/	LOG_MAJOR_FEATURE_OVERRIDE,	/*< related to features*/
-+/*25*/	LOG_MAJOR_DETECTION,	/*< related to detection*/
-+	LOG_MAJOR_COUNT,	/*< count of the Major categories*/
-+};
-+
-+/**
-+* @brief defines minor switch for logging.  each of these define sub category
-+*        of log message per LogMajor
-+*/
-+
-+
-+enum log_minor {
-+
-+	/* Special case for 'all' checkbox */
-+	LOG_MINOR_MASK_ALL = (uint32_t)-1, /* 0xFFFFFFFF */
-+/**
-+* @brief defines minor category for
-+*         LOG_MAJOR_ERROR,
-+*         LOG_MAJOR_WARNING,
-+*         LOG_MAJOR_INTERFACE_TRACE
-+*
-+* @note  each DAL subcomponent should have a corresponding enum
-+*/
-+	LOG_MINOR_COMPONENT_LINK_SERVICE = 0,
-+	LOG_MINOR_COMPONENT_DAL_INTERFACE,
-+	LOG_MINOR_COMPONENT_HWSS,
-+	LOG_MINOR_COMPONENT_ADAPTER_SERVICE,
-+	LOG_MINOR_COMPONENT_DISPLAY_SERVICE,
-+	LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER,
-+	LOG_MINOR_COMPONENT_ENCODER,
-+	LOG_MINOR_COMPONENT_I2C_AUX,
-+	LOG_MINOR_COMPONENT_AUDIO,
-+	LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
-+	LOG_MINOR_COMPONENT_DMCU,
-+	LOG_MINOR_COMPONENT_GPU,
-+	LOG_MINOR_COMPONENT_CONTROLLER,
-+	LOG_MINOR_COMPONENT_ISR,
-+	LOG_MINOR_COMPONENT_BIOS,
-+	LOG_MINOR_COMPONENT_DC,
-+	LOG_MINOR_COMPONENT_IRQ_SERVICE,
-+
-+/**
-+* @brief define minor category for LogMajor_HardwareTrace
-+*
-+* @note  defines functionality based HW programming trace
-+*/
-+	LOG_MINOR_HW_TRACE_MST = 0,
-+	LOG_MINOR_HW_TRACE_TRAVIS,
-+	LOG_MINOR_HW_TRACE_HOTPLUG,
-+	LOG_MINOR_HW_TRACE_LINK_TRAINING,
-+	LOG_MINOR_HW_TRACE_SET_MODE,
-+	LOG_MINOR_HW_TRACE_RESUME_S3,
-+	LOG_MINOR_HW_TRACE_RESUME_S4,
-+	LOG_MINOR_HW_TRACE_BOOTUP,
-+	LOG_MINOR_HW_TRACE_AUDIO,
-+	LOG_MINOR_HW_TRACE_HPD_IRQ,
-+	LOG_MINOR_HW_TRACE_INTERRUPT,
-+	LOG_MINOR_HW_TRACE_MPO,
-+
-+/**
-+* @brief defines minor category for LogMajor_Mst
-+*
-+* @note  define sub functionality related to MST
-+*/
-+	LOG_MINOR_MST_IRQ_HPD_RX = 0,
-+	LOG_MINOR_MST_IRQ_TIMER,
-+	LOG_MINOR_MST_NATIVE_AUX,
-+	LOG_MINOR_MST_SIDEBAND_MSG,
-+	LOG_MINOR_MST_MSG_TRANSACTION,
-+	LOG_MINOR_MST_SIDEBAND_MSG_PARSED,
-+	LOG_MINOR_MST_MSG_TRANSACTION_PARSED,
-+	LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS,
-+	LOG_MINOR_MST_PROGRAMMING,
-+	LOG_MINOR_MST_TOPOLOGY_DISCOVERY,
-+	LOG_MINOR_MST_CONVERTER_CAPS,
-+
-+/**
-+* @brief defines minor category for LogMajor_DCS
-+*
-+* @note  should define sub functionality related to Dcs
-+*/
-+	LOG_MINOR_DCS_EDID_EMULATOR = 0,
-+	LOG_MINOR_DCS_DONGLE_DETECTION,
-+
-+/**
-+* @brief defines minor category for DCP
-+*
-+* @note  should define sub functionality related to Dcp
-+*/
-+	LOG_MINOR_DCP_GAMMA_GRPH = 0,
-+	LOG_MINOR_DCP_GAMMA_OVL,
-+	LOG_MINOR_DCP_CSC_GRPH,
-+	LOG_MINOR_DCP_CSC_OVL,
-+	LOG_MINOR_DCP_SCALER,
-+	LOG_MINOR_DCP_SCALER_TABLES,
-+/**
-+* @brief defines minor category for LogMajor_Bios
-+*
-+* @note define sub functionality related to BiosParser
-+*/
-+	LOG_MINOR_BIOS_CMD_TABLE = 0,
-+/**
-+* @brief defines minor category for LogMajor_Bios
-+*
-+* @note define sub functionality related to BiosParser
-+*/
-+	LOG_MINOR_REGISTER_INDEX = 0,
-+/**
-+* @brief defines minor category for info packets
-+*
-+*/
-+	LOG_MINOR_INFO_PACKETS_HDMI = 0,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_DSAT
-+*
-+* @note define sub functionality related to Display System Analysis Tool
-+*/
-+	LOG_MINOR_DSAT_LOGGER = 0,
-+	LOG_MINOR_DSAT_GET_EDID,
-+	LOG_MINOR_DSAT_EDID_OVERRIDE,
-+	LOG_MINOR_DSAT_SET_ADJUSTMENTS,
-+	LOG_MINOR_DSAT_GET_ADJUSTMENTS,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_EC
-+*
-+* @note define sub functionality related to External components notifications
-+*/
-+	LOG_MINOR_EC_PPLIB_NOTIFY = 0,
-+	LOG_MINOR_EC_PPLIB_QUERY,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_BWM
-+*
-+* @note define sub functionality related to Bandwidth Manager
-+*/
-+	LOG_MINOR_BWM_MODE_VALIDATION = 0,
-+	LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-+
-+/**
-+* @brief define minor category for LogMajor_ModeEnum
-+*
-+* @note  defines functionality mode enumeration trace
-+*/
-+	LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES = 0,
-+	LOG_MINOR_MODE_ENUM_VIEW_SOLUTION,
-+	LOG_MINOR_MODE_ENUM_TS_LIST_BUILD,
-+	LOG_MINOR_MODE_ENUM_TS_LIST,
-+	LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST,
-+	LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE,
-+
-+/**
-+* @brief defines minor category for LogMajor_I2C_AUX
-+*
-+* @note define sub functionality related to I2c and Aux Channel Log
-+*/
-+	LOG_MINOR_I2C_AUX_LOG = 0,
-+	LOG_MINOR_I2C_AUX_AUX_TIMESTAMP,
-+	LOG_MINOR_I2C_AUX_CFG,
-+
-+/**
-+* @brief defines minor category for LogMajor_LineBuffer
-+*
-+* @note define sub functionality related to LineBuffer
-+*/
-+	LOG_MINOR_LINE_BUFFER_POWERGATING = 0,
-+
-+/**
-+* @brief defines minor category for LogMajor_HWSS
-+*
-+* @note define sub functionality related to HWSS
-+*/
-+	LOG_MINOR_HWSS_TAPS_VALIDATION = 0,
-+
-+/**
-+* @brief defines minor category for LogMajor_Optimization
-+*
-+* @note define sub functionality related to Optimization
-+*/
-+	LOG_MINOR_OPTMZ_GENERAL = 0,
-+	LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
-+
-+/**
-+* @brief defines minor category for LogMajor_PerfMeasure
-+*
-+* @note define sub functionality related to Performance measurement dumps
-+*/
-+	LOG_MINOR_PERF_MEASURE_GENERAL = 0,
-+	LOG_MINOR_PERF_MEASURE_HEAP_MEMORY,
-+
-+/**
-+* @brief defines minor category for LogMajor_Sync
-+*
-+* @note define sub functionality related to HW and SW Synchronization
-+*/
-+	LOG_MINOR_SYNC_HW_CLOCK_ADJUST = 0,
-+	LOG_MINOR_SYNC_TIMING,
-+
-+/**
-+* @brief defines minor category for LogMajor_Backlight
-+*
-+* @note define sub functionality related to backlight (including VariBright)
-+*/
-+	LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS = 0,
-+	LOG_MINOR_BACKLIGHT_DMCU_DELTALUT,
-+	LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT,
-+	LOG_MINOR_BACKLIGHT_INTERFACE,
-+	LOG_MINOR_BACKLIGHT_LID,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_TM
-+*
-+* @note define sub functionality related to Topology Manager
-+*/
-+	LOG_MINOR_TM_INFO = 0,
-+	LOG_MINOR_TM_IFACE_TRACE,
-+	LOG_MINOR_TM_RESOURCES,
-+	LOG_MINOR_TM_ENCODER_CTL,
-+	LOG_MINOR_TM_ENG_ASN,
-+	LOG_MINOR_TM_CONTROLLER_ASN,
-+	LOG_MINOR_TM_PWR_GATING,
-+	LOG_MINOR_TM_BUILD_DSP_PATH,
-+	LOG_MINOR_TM_DISPLAY_DETECT,
-+	LOG_MINOR_TM_LINK_SRV,
-+	LOG_MINOR_TM_NOT_IMPLEMENTED,
-+	LOG_MINOR_TM_COFUNC_PATH,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_DISPLAY_SERVICE
-+*
-+* @note define sub functionality related to Display Service
-+*/
-+	LOG_MINOR_DS_MODE_SETTING = 0,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_FEATURE_OVERRIDE
-+*
-+* @note define sub functionality related to features in adapter service
-+*/
-+	LOG_MINOR_FEATURE_OVERRIDE = 0,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_DETECTION
-+*
-+* @note define sub functionality related to detection
-+*/
-+	LOG_MINOR_DETECTION_EDID_PARSER = 0,
-+	LOG_MINOR_DETECTION_DP_CAPS,
-+};
-+
-+union logger_flags {
-+	struct {
-+		uint32_t ENABLE_CONSOLE:1; /* Print to console */
-+		uint32_t ENABLE_BUFFER:1; /* Print to buffer */
-+		uint32_t RESERVED:30;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct log_entry {
-+
-+	struct dal_logger *logger;
-+	enum log_major major;
-+	enum log_minor minor;
-+
-+	char *buf;
-+	uint32_t buf_offset;
-+	uint32_t max_buf_bytes;
-+};
-+
-+/**
-+* Structure for enumerating LogMajors and LogMinors
-+*/
-+
-+#define MAX_MAJOR_NAME_LEN 32
-+#define MAX_MINOR_NAME_LEN 32
-+
-+struct log_major_info {
-+	enum log_major major;
-+	char major_name[MAX_MAJOR_NAME_LEN];
-+};
-+
-+struct log_minor_info {
-+	enum log_minor minor;
-+	char minor_name[MAX_MINOR_NAME_LEN];
-+};
-+
-+#endif /* __DAL_LOGGER_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/mode_manager_types.h b/drivers/gpu/drm/amd/dal/include/mode_manager_types.h
-new file mode 100644
-index 0000000..576b21f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/mode_manager_types.h
-@@ -0,0 +1,71 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_MODE_MANAGER_TYPES_H__
-+#define __DAL_MODE_MANAGER_TYPES_H__
-+
-+#include "bit_set.h"
-+#include "dc_types.h"
-+
-+static inline void stereo_3d_view_reset(struct stereo_3d_view *stereo_3d_view)
-+{
-+	stereo_3d_view->view_3d_format = VIEW_3D_FORMAT_NONE;
-+	stereo_3d_view->flags.raw = 0;
-+}
-+
-+bool dal_refresh_rate_is_equal(
-+		const struct refresh_rate *lhs,
-+		const struct refresh_rate *rhs);
-+
-+bool dal_refresh_rate_less_than(
-+		const struct refresh_rate *lhs,
-+		const struct refresh_rate *rhs);
-+
-+void refresh_rate_from_mode_info(
-+		struct refresh_rate *,
-+		const struct dc_mode_info *);
-+bool dal_solution_less_than(const void *lhs, const void *rhs);
-+bool dal_view_is_equal(const struct view *lhs, const struct view *rhs);
-+
-+struct pixel_format_list {
-+	uint32_t set;
-+	struct bit_set_iterator_32 iter;
-+};
-+
-+void dal_pixel_format_list_reset_iterator(struct pixel_format_list *pfl);
-+void dal_pixel_format_list_zero_iterator(struct pixel_format_list *pfl);
-+
-+void dal_pixel_format_list_construct(
-+		struct pixel_format_list *pfl,
-+		uint32_t mask);
-+
-+uint32_t dal_pixel_format_list_next(struct pixel_format_list *pfl);
-+
-+uint32_t dal_pixel_format_list_get_count(
-+		const struct pixel_format_list *pfl);
-+enum pixel_format dal_pixel_format_list_get_pixel_format(
-+		const struct pixel_format_list *pfl);
-+
-+#endif /* __DAL_MODE_MANAGER_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/mode_query_interface.h b/drivers/gpu/drm/amd/dal/include/mode_query_interface.h
-new file mode 100644
-index 0000000..1d20e73
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/mode_query_interface.h
-@@ -0,0 +1,93 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_MODE_QUERY_INTERFACE_H__
-+#define __DAL_MODE_QUERY_INTERFACE_H__
-+
-+#include "include/set_mode_types.h"
-+#include "include/mode_manager_types.h"
-+
-+enum query_option {
-+	QUERY_OPTION_ALLOW_PAN,
-+	QUERY_OPTION_ALLOW_PAN_NO_VIEW_RESTRICTION,
-+	QUERY_OPTION_PAN_ON_LIMITED_RESOLUTION_DISP_PATH,
-+	QUERY_OPTION_NO_PAN,
-+	QUERY_OPTION_NO_PAN_NO_DISPLAY_VIEW_RESTRICTION,
-+	QUERY_OPTION_3D_LIMITED_CANDIDATES,
-+	QUERY_OPTION_TILED_DISPLAY_PREFERRED,
-+	QUERY_OPTION_MAX,
-+};
-+
-+struct topology {
-+	uint32_t disp_path_num;
-+	uint32_t display_index[MAX_COFUNC_PATH];
-+};
-+
-+struct path_mode;
-+struct mode_query;
-+
-+bool dal_mode_query_pin_path_mode(
-+		struct mode_query *mq,
-+		const struct path_mode *path_mode);
-+
-+const struct render_mode *dal_mode_query_get_current_render_mode(
-+		const struct mode_query *mq);
-+
-+const struct stereo_3d_view *dal_mode_query_get_current_3d_view(
-+		const struct mode_query *mq);
-+
-+const struct refresh_rate *dal_mode_query_get_current_refresh_rate(
-+		const struct mode_query *mq);
-+
-+const struct path_mode_set *dal_mode_query_get_current_path_mode_set(
-+		const struct mode_query *mq);
-+
-+bool dal_mode_query_select_first(struct mode_query *mq);
-+bool dal_mode_query_select_next_render_mode(struct mode_query *mq);
-+
-+bool dal_mode_query_select_render_mode(struct mode_query *mq,
-+		const struct render_mode *render_mode);
-+
-+bool dal_mode_query_select_next_view_3d_format(struct mode_query *mq);
-+bool dal_mode_query_select_view_3d_format(
-+		struct mode_query *mq,
-+		enum view_3d_format format);
-+
-+bool dal_mode_query_select_refresh_rate(struct mode_query *mq,
-+		const struct refresh_rate *refresh_rate);
-+
-+bool dal_mode_query_select_refresh_rate_ex(struct mode_query *mq,
-+		uint32_t refresh_rate,
-+		bool interlaced);
-+
-+bool dal_mode_query_select_next_scaling(struct mode_query *mq);
-+
-+bool dal_mode_query_select_next_refresh_rate(struct mode_query *mq);
-+
-+bool dal_mode_query_base_select_next_scaling(struct mode_query *mq);
-+
-+void dal_mode_query_destroy(struct mode_query **mq);
-+
-+#endif /* __DAL_MODE_QUERY_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h b/drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
-new file mode 100644
-index 0000000..a558fec
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
-@@ -0,0 +1,51 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_MODE_TIMING_LIST_INTERFACE_H__
-+#define __DAL_MODE_TIMING_LIST_INTERFACE_H__
-+
-+
-+struct mode_timing_filter;
-+struct mode_timing_list;
-+
-+struct mode_timing_list *dal_mode_timing_list_create(
-+		struct dal_context *ctx,
-+		uint32_t display_index,
-+		const struct mode_timing_filter *mt_filter);
-+
-+void dal_mode_timing_list_destroy(struct mode_timing_list **mtl);
-+
-+
-+uint32_t dal_mode_timing_list_get_count(
-+		const struct mode_timing_list *mode_timing_list);
-+
-+const struct dc_mode_timing *dal_mode_timing_list_get_timing_at_index(
-+		const struct mode_timing_list *mode_timing_list,
-+		uint32_t index);
-+
-+const struct dc_mode_timing *dal_mode_timing_list_get_single_selected_mode_timing(
-+		const struct mode_timing_list *mode_timing_list);
-+
-+#endif /*__DAL_MODE_TIMING_LIST_INTERFACE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/overlay_interface.h b/drivers/gpu/drm/amd/dal/include/overlay_interface.h
-new file mode 100644
-index 0000000..c33bd73
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/overlay_interface.h
-@@ -0,0 +1,137 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_OVERLAY_INTERFACE_H__
-+#define __DAL_OVERLAY_INTERFACE_H__
-+
-+#include "include/overlay_types.h"
-+#include "include/display_service_types.h"
-+
-+struct ds_overlay;
-+struct path_mode_set;
-+struct path_mode;
-+struct view;
-+
-+bool dal_ds_overlay_is_active(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index);
-+
-+uint32_t dal_ds_overlay_get_controller_handle(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index);
-+
-+enum ds_return dal_ds_overlay_alloc(
-+	struct ds_overlay *ovl,
-+	struct path_mode_set *path_mode_set,
-+	uint32_t display_index,
-+	struct view *view,
-+	struct overlay_data *data);
-+
-+enum ds_return dal_ds_overlay_validate(
-+	struct ds_overlay *ovl,
-+	struct path_mode_set *path_mode_set,
-+	uint32_t display_index,
-+	struct view *view,
-+	struct overlay_data *data);
-+
-+enum ds_return dal_ds_overlay_free(
-+	struct ds_overlay *ovl,
-+	struct path_mode_set *path_mode_set,
-+	uint32_t display_index);
-+
-+enum ds_return dal_ds_overlay_get_info(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	enum overlay_color_space *color_space,
-+	enum overlay_backend_bpp *backend_bpp,
-+	enum overlay_alloc_option *alloc_option,
-+	enum overlay_format *surface_format);
-+
-+enum ds_return dal_ds_overlay_set_otm(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	const struct path_mode *current_path_mode);
-+
-+enum ds_return dal_ds_overlay_reset_otm(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	struct path_mode **saved_path_mode);
-+
-+/**is in overlay theater mode*/
-+bool dal_ds_overlay_is_in_otm(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index);
-+
-+void dal_ds_overlay_set_matrix(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	const struct overlay_color_matrix *matrix);
-+
-+void dal_ds_overlay_reset_matrix(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	enum overlay_csc_matrix_type type);
-+
-+const struct overlay_color_matrix *dal_ds_overlay_get_matrix(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	enum overlay_csc_matrix_type type);
-+
-+bool dal_ds_overlay_set_color_space(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	enum overlay_color_space space);
-+
-+bool dal_ds_overlay_get_display_pixel_encoding(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	enum display_pixel_encoding *pixel_encoding);
-+
-+bool dal_ds_overlay_set_display_pixel_encoding(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	enum display_pixel_encoding pixel_encoding);
-+
-+bool dal_ds_overlay_reset_display_pixel_encoding(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index);
-+
-+/*After Set Overlay Theatre Mode (OTM) on a display path,
-+ *  saving the passed setting of Gpu scaling option for later restore*/
-+enum ds_return dal_ds_overlay_save_gpu_scaling_before_otm(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	int32_t timing_sel_before_otm);
-+
-+/* After reset Overlay Theatre Mode (OTM) on a display path,
-+ * returning the previous Gpu scaling option by SetOverlayTheatreMode*/
-+enum ds_return dal_ds_overlay_get_gpu_scaling_before_otm(
-+	struct ds_overlay *ovl,
-+	uint32_t display_index,
-+	int32_t *timing_sel_before_otm);
-+
-+uint32_t dal_ds_overlay_get_num_of_allowed(struct ds_overlay *ovl);
-+
-+#endif /* __DAL_OVERLAY_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/overlay_types.h b/drivers/gpu/drm/amd/dal/include/overlay_types.h
-new file mode 100644
-index 0000000..c001edf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/overlay_types.h
-@@ -0,0 +1,164 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_OVERLAY_TYPES_H__
-+#define __DAL_OVERLAY_TYPES_H__
-+
-+enum overlay_color_space {
-+	OVERLAY_COLOR_SPACE_UNINITIALIZED,
-+	OVERLAY_COLOR_SPACE_RGB, /* the first*/
-+	OVERLAY_COLOR_SPACE_BT601,
-+	OVERLAY_COLOR_SPACE_BT709, /* the last*/
-+	OVERLAY_COLOR_SPACE_INVALID,
-+
-+	/* flag the first and last*/
-+	OVERLAY_COLOR_SPACE_BEGIN = OVERLAY_COLOR_SPACE_RGB,
-+	OVERLAY_COLOR_SPACE_END = OVERLAY_COLOR_SPACE_BT709,
-+};
-+
-+enum overlay_backend_bpp {
-+	OVERLAY_BACKENDBPP_UNINITIALIZED,
-+
-+	OVERLAY_BACKEND_BPP_32_FULL_BANDWIDTH,/* the first*/
-+	OVERLAY_BACKEND_BPP_16_FULL_BANDWIDTH,
-+	OVERLAY_BACKEND_BPP_32_HALF_BANDWIDTH,/* the last*/
-+
-+	OVERLAY_BACKEND_BPP_INVALID,
-+
-+	/* flag the first and last*/
-+	OVERLAY_BACKEND_BPP_BEGIN = OVERLAY_BACKEND_BPP_32_FULL_BANDWIDTH,
-+	OVERLAY_BACKEND_BPP_END = OVERLAY_BACKEND_BPP_32_HALF_BANDWIDTH,
-+};
-+
-+enum overlay_alloc_option {
-+	OVERLAY_ALLOC_OPTION_UNINITIALIZED,
-+
-+	OVERLAY_ALLOC_OPTION_APPLY_OVERLAY_CSC, /* the first*/
-+	OVERLAY_ALLOC_OPTION_APPLY_DESKTOP_CSC, /* the last*/
-+
-+	OVERLAY_ALLOC_OPTION_INVALID,
-+
-+	/* flag the first and last*/
-+	OVERLAY_ALLOC_OPTION_BEGIN = OVERLAY_ALLOC_OPTION_APPLY_OVERLAY_CSC,
-+	OVERLAY_ALLOC_OPTION_END = OVERLAY_ALLOC_OPTION_APPLY_DESKTOP_CSC,
-+};
-+
-+enum overlay_format {
-+	OVERLAY_FORMAT_UNINITIALIZED,
-+	OVERLAY_FORMAT_YUY2,
-+	OVERLAY_FORMAT_UYVY,
-+	OVERLAY_FORMAT_RGB565,
-+	OVERLAY_FORMAT_RGB555,
-+	OVERLAY_FORMAT_RGB32,
-+	OVERLAY_FORMAT_YUV444,
-+	OVERLAY_FORMAT_RGB32_2101010,
-+
-+	OVERLAY_FORMAT_INVALID,
-+
-+	/* flag the first and last*/
-+	OVERLAY_FORMAT_BEGIN = OVERLAY_FORMAT_YUY2,
-+	OVERLAY_FORMAT_END = OVERLAY_FORMAT_RGB32_2101010,
-+};
-+
-+enum display_pixel_encoding {
-+	DISPLAY_PIXEL_ENCODING_UNDEFINED = 0,
-+	DISPLAY_PIXEL_ENCODING_RGB,
-+	DISPLAY_PIXEL_ENCODING_YCBCR422,
-+	DISPLAY_PIXEL_ENCODING_YCBCR444
-+};
-+
-+union overlay_data_status {
-+	uint32_t u32all;
-+	struct {
-+		uint32_t COLOR_SPACE_SET:1;
-+		uint32_t BACKEND_BPP:1;
-+		uint32_t ALLOC_OPTION:1;
-+		uint32_t SURFACE_FORMAT:1;
-+		uint32_t PIXEL_ENCODING:1;
-+		uint32_t reserved:27;
-+
-+	} bits;
-+};
-+
-+struct overlay_data {
-+	enum overlay_color_space color_space;
-+	enum overlay_backend_bpp backend_bpp;
-+	enum overlay_alloc_option alloc_option;
-+	enum overlay_format surface_format;
-+};
-+
-+enum overlay_csc_matrix_type {
-+	OVERLAY_CSC_MATRIX_NOTDEFINED = 0,
-+	OVERLAY_CSC_MATRIX_BT709,
-+	OVERLAY_CSC_MATRIX_BT601,
-+	OVERLAY_CSC_MATRIX_SMPTE240,
-+	OVERLAY_CSC_MATRIX_SRGB,
-+};
-+
-+#define DEFAULT_APP_MATRIX_DIVIDER 10000
-+#define MAX_OVL_MATRIX_COUNTS 2
-+#define OVL_BT709 0
-+#define OVL_BT601 1
-+
-+#define OVL_MATRIX_ITEM 9
-+#define OVL_MATRIX_OFFSET_ITEM 3
-+
-+struct overlay_color_matrix {
-+	enum overlay_csc_matrix_type csc_matrix;
-+/*3*3 Gamut Matrix (value is the real value * M_GAMUT_PRECISION_MULTIPLIER)*/
-+	int32_t matrix_settings[OVL_MATRIX_ITEM];
-+	int32_t offsets[OVL_MATRIX_OFFSET_ITEM];
-+};
-+
-+enum setup_adjustment_ovl_value_type {
-+	SETUP_ADJUSTMENT_MIN,
-+	SETUP_ADJUSTMENT_MAX,
-+	SETUP_ADJUSTMENT_DEF,
-+	SETUP_ADJUSTMENT_CURRENT,
-+	SETUP_ADJUSTMENT_BUNDLE_MIN,
-+	SETUP_ADJUSTMENT_BUNDLE_MAX,
-+	SETUP_ADJUSTMENT_BUNDLE_DEF,
-+	SETUP_ADJUSTMENT_BUNDLE_CURRENT
-+};
-+
-+struct overlay_parameter {
-+	union {
-+		uint32_t u32all;
-+		struct {
-+			uint32_t VALID_OVL_COLOR_SPACE:1;
-+			uint32_t VALID_VALUE_TYPE:1;
-+			uint32_t VALID_OVL_SURFACE_FORMAT:1;
-+			uint32_t CONFIG_IS_CHANGED:1;
-+			uint32_t reserved:28;
-+
-+		} bits;
-+	};
-+	/*currently colorSpace here packed, continue this list*/
-+	enum overlay_color_space color_space;
-+	enum setup_adjustment_ovl_value_type value_type;
-+	enum overlay_format surface_format;
-+};
-+
-+#endif /* OVERLAY_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h b/drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
-new file mode 100644
-index 0000000..a277010
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
-@@ -0,0 +1,107 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_PATH_MODE_SET_INTERFACE_H__
-+#define __DAL_PATH_MODE_SET_INTERFACE_H__
-+
-+/* Set of path modes */
-+struct path_mode_set {
-+	union control_flags {
-+		struct {
-+			uint32_t KEEP_DISPLAY_POWERED_OFF:1;
-+			uint32_t UNBLANCK_SOURCE_AFTER_SETMODE:1;
-+			uint32_t NODE_FAULT_UNDERSCAN:1;
-+		} bits;
-+
-+		uint32_t all;
-+	} control_flags;
-+
-+	struct path_mode path_mode_set[MAX_COFUNC_PATH];
-+	uint32_t count;
-+};
-+
-+/* Create path mode set */
-+struct path_mode_set *dal_pms_create(void);
-+
-+/* Deallocate path mode set */
-+void dal_pms_destroy(
-+	struct path_mode_set **pms);
-+
-+/* Create a copy of given path mode set */
-+struct path_mode_set *dal_pms_copy(
-+	const struct path_mode_set *copy);
-+
-+/* Constructor for path mode set */
-+bool dal_pms_construct(
-+	struct path_mode_set *set);
-+
-+/* Add a path mode into the set */
-+bool dal_pms_add_path_mode(
-+	struct path_mode_set *set,
-+	const struct path_mode *path_mode);
-+
-+/* Get number of path modes in the set */
-+uint32_t dal_pms_get_path_mode_num(
-+	const struct path_mode_set *set);
-+
-+/* Return the path mode at the index */
-+const struct path_mode *dal_pms_get_path_mode_at_index(
-+	const struct path_mode_set *set,
-+	uint32_t index);
-+
-+/* Return the path mode for the given display index */
-+const struct path_mode *dal_pms_get_path_mode_for_display_index(
-+	const struct path_mode_set *set,
-+	uint32_t index);
-+
-+/* Remove the path mode at index */
-+bool dal_pms_remove_path_mode_at_index(
-+	struct path_mode_set *set,
-+	uint32_t index);
-+
-+/* Remove the given path mode if it is found in the set */
-+bool dal_pms_remove_path_mode(
-+	struct path_mode_set *set,
-+	struct path_mode *mode);
-+
-+/* Add control flag to keep display powered off */
-+void dal_pms_keep_display_powered_off(
-+	struct path_mode_set *set,
-+	bool keep);
-+
-+/* Return control flag if display needs to be kept powered off */
-+bool dal_pms_is_display_power_off_required(
-+	const struct path_mode_set *set);
-+
-+/* Add control flag to not use default underscan*/
-+void dal_pms_fallback_remove_default_underscan(
-+	struct path_mode_set *set,
-+	bool lean);
-+
-+/* Return control flag if default underscan is not used */
-+bool dal_pms_is_fallback_no_default_underscan_enabled(
-+	struct path_mode_set *set);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/plane_types.h b/drivers/gpu/drm/amd/dal/include/plane_types.h
-new file mode 100644
-index 0000000..a2a8939
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/plane_types.h
-@@ -0,0 +1,309 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_PLANE_TYPES_H__
-+#define __DAL_PLANE_TYPES_H__
-+
-+#include "scaler_types.h"
-+
-+enum display_flip_mode {
-+	DISPLAY_FLIP_MODE_VERTICAL = 0,
-+	DISPLAY_FLIP_MODE_HORIZONTAL
-+};
-+
-+/*rect or view */
-+struct rect_position {
-+	uint32_t x;
-+	uint32_t y;
-+};
-+
-+union plane_config_change_flags {
-+	struct {
-+		uint32_t MIRROR_FLAGS:1;
-+		uint32_t BLEND_FLAGS:1;
-+		uint32_t COLORIMETRY:1;
-+		uint32_t SCALING_RECTS:1;
-+
-+		uint32_t SCALING_QUALITY:1;
-+		uint32_t VIDEO_SCAN_FORMAT:1;
-+		uint32_t STEREO_FORMAT:1;
-+		uint32_t PLANE_SIZE:1;
-+
-+		uint32_t TITLING_INFO:1;
-+		uint32_t FORMAT:1;
-+		uint32_t ROTATION:1;
-+
-+		uint32_t RESERVED:21;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+
-+enum array_mode {
-+	ARRAY_MODE_LINEAR_GENERAL = 0x00000000,
-+	ARRAY_MODE_LINEAR_ALIGNED = 0x00000001,
-+	ARRAY_MODE_1D_TILED_THIN1 = 0x00000002,
-+	ARRAY_MODE_1D_TILED_THICK = 0x00000003,
-+	ARRAY_MODE_2D_TILED_THIN1 = 0x00000004,
-+	ARRAY_MODE_PRT_TILED_THIN1 = 0x00000005,
-+	ARRAY_MODE_PRT_2D_TILED_THIN1 = 0x00000006,
-+	ARRAY_MODE_2D_TILED_THICK = 0x00000007,
-+	ARRAY_MODE_2D_TILED_X_THICK = 0x00000008,
-+	ARRAY_MODE_PRT_TILED_THICK = 0x00000009,
-+	ARRAY_MODE_PRT_2D_TILED_THICK = 0x0000000a,
-+	ARRAY_MODE_PRT_3D_TILED_THIN1 = 0x0000000b,
-+	ARRAY_MODE_3D_TILED_THIN1 = 0x0000000c,
-+	ARRAY_MODE_3D_TILED_THICK = 0x0000000d,
-+	ARRAY_MODE_3D_TILED_X_THICK = 0x0000000e,
-+	ARRAY_MODE_PRT_3D_TILED_THICK = 0x0000000f
-+};
-+
-+/* single enum for grph and video (both luma and chroma) */
-+enum tile_split {
-+	TILE_SPLIT_64B = 0x00000000,
-+	TILE_SPLIT_128B = 0x00000001,
-+	TILE_SPLIT_256B = 0x00000002,
-+	TILE_SPLIT_512B = 0x00000003,
-+	TILE_SPLIT_1KB = 0x00000004,
-+	TILE_SPLIT_2KB = 0x00000005,
-+	TILE_SPLIT_4KB = 0x00000006
-+};
-+
-+/* single enum for grph and video (both luma and chroma)*/
-+enum macro_tile_aspect {
-+	MACRO_TILE_ASPECT_1 = 0x00000000,
-+	MACRO_TILE_ASPECT_2 = 0x00000001,
-+	MACRO_TILE_ASPECT_4 = 0x00000002,
-+	MACRO_TILE_ASPECT_8 = 0x00000003
-+};
-+
-+enum video_array_mode {
-+	VIDEO_ARRAY_MODE_LINEAR_GENERAL = 0x00000000,
-+	VIDEO_ARRAY_MODE_LINEAR_ALIGNED = 0x00000001,
-+	VIDEO_ARRAY_MODE_1D_TILED_THIN1 = 0x00000002,
-+	VIDEO_ARRAY_MODE_1D_TILED_THICK = 0x00000003,
-+	VIDEO_ARRAY_MODE_2D_TILED_THIN1 = 0x00000004,
-+	VIDEO_ARRAY_MODE_2D_TILED_THICK = 0x00000007,
-+	VIDEO_ARRAY_MODE_3D_TILED_THIN1 = 0x0000000c,
-+	VIDEO_ARRAY_MODE_3D_TILED_THICK = 0x0000000d
-+};
-+
-+/* single enum for grph and video (both luma and chroma)*/
-+enum micro_tile_mode {
-+	MICRO_TILE_MODE_DISPLAY = 0x00000000,
-+	MICRO_TILE_MODE_THIN = 0x00000001,
-+	MICRO_TILE_MODE_DEPTH = 0x00000002,
-+	MICRO_TILE_MODE_ROTATED = 0x00000003
-+};
-+
-+/* KK: taken from addrlib*/
-+enum addr_pipe_config {
-+	ADDR_PIPE_CONFIG_INVALID = 0,
-+	/* 2 pipes */
-+	ADDR_PIPE_CONFIG_P2 = 1,
-+	/* 4 pipes */
-+	ADDR_PIPE_CONFIG_P4_8x16 = 5,
-+	ADDR_PIPE_CONFIG_P4_16x16 = 6,
-+	ADDR_PIPE_CONFIG_P4_16x32 = 7,
-+	ADDR_PIPE_CONFIG_P4_32x32 = 8,
-+	/* 8 pipes*/
-+	ADDR_PIPE_CONFIG_P8_16x16_8x16 = 9,
-+	ADDR_PIPE_CONFIG_P8_16x32_8x16 = 10,
-+	ADDR_PIPE_CONFIG_P8_32x32_8x16 = 11,
-+	ADDR_PIPE_CONFIG_P8_16x32_16x16 = 12,
-+	ADDR_PIPE_CONFIG_P8_32x32_16x16 = 13,
-+	ADDR_PIPE_CONFIG_P8_32x32_16x32 = 14,
-+	ADDR_PIPE_CONFIG_P8_32x64_32x32 = 15,
-+	/* 16 pipes */
-+	ADDR_PIPE_CONFIG_P16_32x32_8x16 = 17,
-+	ADDR_PIPE_CONFIG_P16_32x32_16x16 = 18,
-+	ADDR_PIPE_CONFIG_MAX = 19
-+};
-+
-+struct plane_surface_config {
-+	uint32_t layer_index;
-+	/*used in set operation*/
-+	bool enabled;
-+
-+	union plane_size plane_size;
-+	union plane_tiling_info tiling_info;
-+	/* surface pixel format from display manager or fb*/
-+	enum surface_pixel_format format;
-+	/*pixel format for DAL internal hardware programming*/
-+	enum pixel_format dal_pixel_format;
-+	enum dc_rotation_angle rotation;
-+};
-+
-+/* For Caps, maximum taps for each axis is returned*/
-+/* For Set, the requested taps will be used*/
-+struct plane_src_scaling_quality {
-+	/* INVALID_TAP_VALUE indicates DAL
-+	* decides considering aspect ratio
-+	* & bandwidth
-+	*/
-+	uint32_t h_taps;
-+	/* INVALID_TAP_VALUE indicates DAL
-+	 * decides considering aspect ratio
-+	 * & bandwidth
-+	 */
-+	uint32_t v_taps;
-+	uint32_t h_taps_c;
-+	uint32_t v_taps_c;
-+};
-+
-+struct plane_mirror_flags {
-+	union {
-+		struct {
-+			uint32_t vertical_mirror:1;
-+			uint32_t horizontal_mirror:1;
-+			uint32_t reserved:30;
-+		} bits;
-+		uint32_t value;
-+	};
-+};
-+
-+/* Note some combinations are mutually exclusive*/
-+struct plane_blend_flags {
-+	union {
-+	struct {
-+		uint32_t PER_PIXEL_ALPHA_BLEND:1;
-+		uint32_t GLOBAL_ALPHA_BLEND:1;
-+		uint32_t RESERVED:30;
-+	} bits;
-+	uint32_t value;
-+	};
-+};
-+
-+enum plane_vid_scan_fmt {
-+	PLANE_VID_SCAN_FMT_PROGRESSIVE = 0,
-+	PLANE_VID_SCAN_FMT_INTERLACED_TOP_FIRST = 1,
-+	PLANE_VID_SCAN_FMT_INTERLACED_BOTTOM_FIRST = 2
-+};
-+
-+
-+struct plane_attributes {
-+	/*mirror options  */
-+	struct plane_mirror_flags mirror_flags;
-+	/*blending options*/
-+	struct plane_blend_flags blend_flags;
-+	/*color space */
-+	struct plane_colorimetry colorimetry;
-+
-+	struct rect src_rect;
-+	struct rect dst_rect;
-+	struct rect clip_rect;
-+	struct scaling_taps scaling_quality;
-+	/*progressive, interlaced*/
-+	enum plane_vid_scan_fmt video_scan_format;
-+	enum plane_stereo_format stereo_format;
-+};
-+
-+union address_flags {
-+	struct {
-+		/* always 1 for primary surface, used in get operation*/
-+		uint32_t ENABLE:1;
-+		/* set 1 if returned address is from cache*/
-+		uint32_t ADDR_IS_PENDING:1;
-+		/* currentFrameIsRightEye for stereo only*/
-+		uint32_t CURRENT_FRAME_IS_RIGHT_EYE:1;
-+		uint32_t RESERVED:29;
-+	} bits;
-+
-+	uint32_t value;
-+};
-+
-+struct address_info {
-+	/* primary surface will be DAL_LAYER_INDEX_PRIMARY*/
-+	int32_t layer_index;
-+	/*the flags to describe the address info*/
-+	union address_flags flags;
-+	struct dc_plane_address address;
-+};
-+
-+union plane_valid_mask {
-+	struct {
-+		/* set 1 if config is valid in DalPlane*/
-+		uint32_t SURFACE_CONFIG_IS_VALID:1;
-+		/* set 1 if plane_attributes  is valid in plane*/
-+		uint32_t PLANE_ATTRIBUTE_IS_VALID:1;
-+		uint32_t RESERVED:30;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+union flip_valid_mask {
-+	struct {
-+		/* set 1 if flip_immediate is
-+		 * valid in plane_addr_flip_info
-+		 */
-+		uint32_t FLIP_VALID:1;
-+		/* set 1 if addressInfo is
-+		 * valid in plane_addr_flip_info
-+		 */
-+		uint32_t ADDRESS_VALID:1;
-+		uint32_t RESERVED:30;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct plane_addr_flip_info {
-+	uint32_t display_index;
-+	struct address_info address_info;
-+	/* flip on vsync if false . When
-+	 * flip_immediate is true then
-+	 * update_duration is unused
-+	 */
-+	bool flip_immediate;
-+	/* 48 Hz support for single and
-+	 * multi plane cases  ,set 0 when
-+	 * it is unused.
-+	 */
-+	uint32_t update_duration;
-+	union flip_valid_mask mask;
-+};
-+
-+struct plane_config {
-+	union plane_valid_mask mask;
-+	uint32_t display_index;
-+	struct plane_surface_config config;
-+	struct plane_attributes attributes;
-+	struct mp_scaling_data mp_scaling_data;
-+	union plane_config_change_flags plane_change_flags;
-+};
-+
-+struct plane_validate_config {
-+	uint32_t display_index;
-+	bool flip_immediate;
-+	struct plane_surface_config config;
-+	struct plane_attributes attributes;
-+};
-+
-+struct view_port {
-+	uint32_t display_index;
-+	struct rect view_port_rect;
-+};
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/include/scaler_types.h b/drivers/gpu/drm/amd/dal/include/scaler_types.h
-new file mode 100644
-index 0000000..db52dbc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/scaler_types.h
-@@ -0,0 +1,196 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SCALER_TYPES_H__
-+#define __DAL_SCALER_TYPES_H__
-+
-+#include "signal_types.h"
-+#include "fixed31_32.h"
-+#include "dc_types.h"
-+
-+enum pixel_type {
-+	PIXEL_TYPE_30BPP = 1,
-+	PIXEL_TYPE_20BPP
-+};
-+
-+/*overscan or window*/
-+struct overscan_info {
-+	uint32_t left;
-+	uint32_t right;
-+	uint32_t top;
-+	uint32_t bottom;
-+};
-+
-+struct mp_scaling_data {
-+	struct rect viewport;
-+	struct view dst_res;
-+	struct overscan_info overscan;
-+	struct scaling_taps taps;
-+	struct scaling_ratios ratios;
-+};
-+
-+struct scaler_validation_params {
-+	uint32_t INTERLACED:1;
-+	uint32_t CHROMA_SUB_SAMPLING:1;
-+
-+	uint32_t line_buffer_size;
-+	uint32_t display_clock; /* in KHz */
-+	uint32_t actual_pixel_clock; /* in KHz */
-+	struct view source_view;
-+	struct view dest_view;
-+	enum signal_type signal_type;
-+
-+	struct scaling_taps taps_requested;
-+	enum pixel_format pixel_format;
-+	enum dc_rotation_angle rotation;
-+};
-+
-+struct adjustment_factor {
-+	int32_t adjust;	 /* Actual adjustment value * lDivider */
-+	uint32_t divider;
-+};
-+
-+struct sharpness_adjustment {
-+	int32_t sharpness;
-+	bool enable_sharpening;
-+};
-+
-+enum scaling_options {
-+	SCALING_BYPASS = 0,
-+	SCALING_ENABLE
-+};
-+
-+/* same as Hw register */
-+enum filter_type {
-+	FILTER_TYPE_V_LOW_PASS = 0x0,
-+	FILTER_TYPE_V_HIGH_PASS = 0x1,
-+	FILTER_TYPE_H_LUMA = 0x2,
-+	FILTER_TYPE_H_CHROMA = 0x3
-+};
-+
-+/* Validation Result enumeration */
-+enum scaler_validation_code {
-+	SCALER_VALIDATION_OK = 0,
-+	SCALER_VALIDATION_INVALID_INPUT_PARAMETERS,
-+	SCALER_VALIDATION_SCALING_RATIO_NOT_SUPPORTED,
-+	SCALER_VALIDATION_SOURCE_VIEW_WIDTH_EXCEEDING_LIMIT,
-+	SCALER_VALIDATION_DISPLAY_CLOCK_BELOW_PIXEL_CLOCK,
-+	SCALER_VALIDATION_FAILURE_PREDEFINED_TAPS_NUMBER
-+};
-+
-+
-+#define FILTER_TYPE_MASK 0x0000000FL
-+#define TWO_TAPS 2
-+
-+struct init_int_and_frac {
-+	uint32_t integer;
-+	uint32_t fraction;
-+};
-+
-+struct scl_ratios_inits {
-+	uint32_t bottom_enable;
-+	uint32_t h_int_scale_ratio;
-+	uint32_t v_int_scale_ratio;
-+	struct init_int_and_frac h_init;
-+	struct init_int_and_frac v_init;
-+	struct init_int_and_frac v_init_bottom;
-+};
-+
-+union scaler_flags {
-+	uint32_t raw;
-+	struct {
-+		uint32_t INTERLACED:1;
-+		uint32_t DOUBLE_SCAN_MODE:1;
-+		/* this one is legacy flag only used in DCE80 */
-+		uint32_t RGB_COLOR_SPACE:1;
-+		uint32_t PIPE_LOCK_REQ:1;
-+		/* 4 */
-+		uint32_t WIDE_DISPLAY:1;
-+		uint32_t OTHER_PIPE:1;
-+		uint32_t SHOULD_PROGRAM_VIEWPORT:1;
-+		uint32_t SHOULD_UNLOCK:1;
-+		/* 8 */
-+		uint32_t SHOULD_PROGRAM_ALPHA:1;
-+		uint32_t SHOW_COLOURED_BORDER:1;
-+
-+		uint32_t  RESERVED:22;
-+	} bits;
-+};
-+
-+struct scaler_data {
-+	struct view src_res;
-+	struct view dst_res;
-+	struct overscan_info overscan;
-+	struct scaling_taps taps;
-+	struct adjustment_factor scale_ratio_hp_factor;
-+	struct adjustment_factor scale_ratio_lp_factor;
-+	enum pixel_type pixel_type; /*legacy*/
-+	struct sharpness_adjustment sharp_gain;
-+
-+	union scaler_flags flags;
-+	int32_t h_sharpness;
-+	int32_t v_sharpness;
-+
-+	struct view src_res_wide_display;
-+	struct view dst_res_wide_display;
-+
-+	/* it is here because of the HW bug in NI (UBTS #269539)
-+	causes glitches in this VBI signal. It shouldn't change after
-+	initialization, kind of a const */
-+	const struct hw_crtc_timing *hw_crtc_timing;
-+
-+	struct rect viewport;
-+
-+	enum pixel_format dal_pixel_format;/*plane concept*/
-+	/*stereoformat TODO*/
-+	/*hwtotation TODO*/
-+
-+	const struct scaling_ratios *ratios;
-+};
-+
-+enum bypass_type {
-+	/* 00 - 00 - Manual Centering, Manual Replication */
-+	BYPASS_TYPE_MANUAL = 0,
-+	/* 01 - 01 - Auto-Centering, No Replication */
-+	BYPASS_TYPE_AUTO_CENTER = 1,
-+	/* 02 - 10 - Auto-Centering, Auto-Replication */
-+	BYPASS_TYPE_AUTO_REPLICATION = 3
-+};
-+
-+struct replication_factor {
-+	uint32_t h_manual;
-+	uint32_t v_manual;
-+};
-+
-+enum ram_filter_type {
-+	FILTER_TYPE_RGB_Y_VERTICAL = 0,	/* 0 - RGB/Y Vertical filter */
-+	FILTER_TYPE_CBCR_VERTICAL = 1,	/* 1 - CbCr  Vertical filter */
-+	FILTER_TYPE_RGB_Y_HORIZONTAL   = 2, /* 1 - RGB/Y Horizontal filter */
-+	FILTER_TYPE_CBCR_HORIZONTAL   = 3, /* 3 - CbCr  Horizontal filter */
-+	FILTER_TYPE_ALPHA_VERTICAL    = 4, /* 4 - Alpha Vertical filter. */
-+	FILTER_TYPE_ALPHA_HORIZONTAL  = 5, /* 5 - Alpha Horizontal filter. */
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h b/drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
-new file mode 100644
-index 0000000..e4f52c4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
-@@ -0,0 +1,101 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SET_MODE_PARAMS_INTERFACE_H__
-+#define __DAL_SET_MODE_PARAMS_INTERFACE_H__
-+
-+struct set_mode_params;
-+
-+struct set_mode_params_init_data {
-+	struct hw_sequencer *hws;
-+	struct dal_context *ctx;
-+	struct topology_mgr *tm;
-+};
-+
-+struct view_stereo_3d_support dal_set_mode_params_get_stereo_3d_support(
-+	struct set_mode_params *smp,
-+	uint32_t display_index,
-+	enum dc_timing_3d_format);
-+
-+bool dal_set_mode_params_update_view_on_path(
-+	struct set_mode_params *smp,
-+	uint32_t display_index,
-+	const struct view *vw);
-+
-+bool dal_set_mode_params_update_mode_timing_on_path(
-+	struct set_mode_params *smp,
-+	uint32_t display_index,
-+	const struct dc_mode_timing *mode_timing,
-+	enum view_3d_format format);
-+
-+bool dal_set_mode_params_update_scaling_on_path(
-+	struct set_mode_params *smp,
-+	uint32_t display_index,
-+	enum scaling_transformation st);
-+
-+bool dal_set_mode_params_update_pixel_format_on_path(
-+	struct set_mode_params *smp,
-+	uint32_t display_index,
-+	enum pixel_format pf);
-+
-+bool dal_set_mode_params_update_tiling_mode_on_path(
-+		struct set_mode_params *smp,
-+		uint32_t display_index,
-+		enum tiling_mode tm);
-+
-+bool dal_set_mode_params_is_path_mode_set_supported(
-+	struct set_mode_params *smp);
-+
-+bool dal_set_mode_params_is_path_mode_set_guaranteed(
-+	struct set_mode_params *smp);
-+
-+bool dal_set_mode_params_report_single_selected_timing(
-+	struct set_mode_params *smp,
-+	uint32_t display_index);
-+
-+bool dal_set_mode_params_report_ce_mode_only(
-+	struct set_mode_params *smp,
-+	uint32_t display_index);
-+
-+struct set_mode_params *dal_set_mode_params_create(
-+		struct set_mode_params_init_data *init_data);
-+
-+bool dal_set_mode_params_init_with_topology(
-+		struct set_mode_params *smp,
-+		const uint32_t display_indicies[],
-+		uint32_t idx_num);
-+
-+bool dal_set_mode_params_is_multiple_pixel_encoding_supported(
-+	struct set_mode_params *smp,
-+	uint32_t display_index);
-+
-+enum dc_pixel_encoding dal_set_mode_params_get_default_pixel_format_preference(
-+	struct set_mode_params *smp,
-+	unsigned int display_index);
-+
-+void dal_set_mode_params_destroy(
-+		struct set_mode_params **set_mode_params);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_types.h b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-new file mode 100644
-index 0000000..3647815
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-@@ -0,0 +1,285 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SET_MODE_TYPES_H__
-+#define __DAL_SET_MODE_TYPES_H__
-+
-+#include "adjustment_types.h"
-+#include "hw_adjustment_types.h"
-+#include "include/plane_types.h"
-+#include "dc_types.h"
-+
-+/* Forward declaration */
-+struct dc_mode_timing;
-+struct display_path;
-+
-+/* State of stereo 3D for workstation */
-+enum ws_stereo_state {
-+	WS_STEREO_STATE_INACTIVE = 0,
-+	WS_STEREO_STATE_ACTIVE,
-+	WS_STEREO_STATE_ACTIVE_MASTER
-+};
-+
-+/* GTC group number */
-+enum gtc_group {
-+	GTC_GROUP_DISABLED,
-+	GTC_GROUP_1,
-+	GTC_GROUP_2,
-+	GTC_GROUP_3,
-+	GTC_GROUP_4,
-+	GTC_GROUP_5,
-+	GTC_GROUP_6,
-+	GTC_GROUP_MAX
-+};
-+
-+/* Adjustment action*/
-+enum adjustment_action {
-+	ADJUSTMENT_ACTION_UNDEFINED = 0,
-+	ADJUSTMENT_ACTION_VALIDATE,
-+	ADJUSTMENT_ACTION_SET_ADJUSTMENT
-+};
-+
-+/* Type of adjustment parameters*/
-+enum adjustment_par_type {
-+	ADJUSTMENT_PAR_TYPE_NONE = 0,
-+	ADJUSTMENT_PAR_TYPE_TIMING,
-+	ADJUSTMENT_PAR_TYPE_MODE
-+};
-+
-+/* Method of validation */
-+enum validation_method {
-+	VALIDATION_METHOD_STATIC = 0,
-+	VALIDATION_METHOD_DYNAMIC
-+};
-+
-+/* Info frame packet status */
-+enum info_frame_flag {
-+	INFO_PACKET_PACKET_INVALID = 0,
-+	INFO_PACKET_PACKET_VALID = 1,
-+	INFO_PACKET_PACKET_RESET = 2,
-+	INFO_PACKET_PACKET_UPDATE_SCAN_TYPE = 8
-+};
-+
-+/* Info frame types */
-+enum info_frame_type {
-+	INFO_FRAME_GAMUT = 0x0A,
-+	INFO_FRAME_VENDOR_INFO = 0x81,
-+	INFO_FRAME_AVI = 0x82
-+};
-+
-+/* Info frame versions */
-+enum info_frame_version {
-+	INFO_FRAME_VERSION_1 = 1,
-+	INFO_FRAME_VERSION_2 = 2,
-+	INFO_FRAME_VERSION_3 = 3
-+};
-+
-+/* Info frame size */
-+enum info_frame_size {
-+	INFO_FRAME_SIZE_AVI = 13,
-+	INFO_FRAME_SIZE_VENDOR = 25,
-+	INFO_FRAME_SIZE_AUDIO = 10
-+};
-+
-+/* Active format */
-+enum active_format_info {
-+	ACTIVE_FORMAT_NO_DATA = 0,
-+	ACTIVE_FORMAT_VALID = 1
-+};
-+/* Bar info */
-+enum bar_info {
-+	BAR_INFO_NOT_VALID = 0,
-+	BAR_INFO_VERTICAL_VALID = 1,
-+	BAR_INFO_HORIZONTAL_VALID = 2,
-+	BAR_INFO_BOTH_VALID = 3
-+};
-+
-+/* Picture scaling */
-+enum picture_scaling {
-+	PICTURE_SCALING_UNIFORM = 0,
-+	PICTURE_SCALING_HORIZONTAL = 1,
-+	PICTURE_SCALING_VERTICAL = 2,
-+	PICTURE_SCALING_BOTH = 3
-+};
-+
-+/* Colorimetry */
-+enum colorimetry {
-+	COLORIMETRY_NO_DATA = 0,
-+	COLORIMETRY_ITU601 = 1,
-+	COLORIMETRY_ITU709 = 2,
-+	COLORIMETRY_EXTENDED = 3
-+};
-+
-+/* ColorimetryEx */
-+enum colorimetry_ex {
-+	COLORIMETRY_EX_XVYCC601 = 0,
-+	COLORIMETRY_EX_XVYCC709 = 1,
-+	COLORIMETRY_EX_SYCC601 = 2,
-+	COLORIMETRY_EX_ADOBEYCC601 = 3,
-+	COLORIMETRY_EX_ADOBERGB = 4,
-+	COLORIMETRY_EX_RESERVED5 = 5,
-+	COLORIMETRY_EX_RESERVED6 = 6,
-+	COLORIMETRY_EX_RESERVED7 = 7
-+};
-+
-+/* Active format aspect ratio */
-+enum active_format_aspect_ratio {
-+	ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
-+	ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
-+	ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
-+	ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
-+};
-+
-+/* RGB quantization range */
-+enum rgb_quantization_range {
-+	RGB_QUANTIZATION_DEFAULT_RANGE = 0,
-+	RGB_QUANTIZATION_LIMITED_RANGE = 1,
-+	RGB_QUANTIZATION_FULL_RANGE = 2,
-+	RGB_QUANTIZATION_RESERVED = 3
-+};
-+
-+/* YYC quantization range */
-+enum yyc_quantization_range {
-+	YYC_QUANTIZATION_LIMITED_RANGE = 0,
-+	YYC_QUANTIZATION_FULL_RANGE = 1,
-+	YYC_QUANTIZATION_RESERVED2 = 2,
-+	YYC_QUANTIZATION_RESERVED3 = 3
-+};
-+
-+/* Rotation capability */
-+struct rotation_capability {
-+	bool ROTATION_ANGLE_0_CAP:1;
-+	bool ROTATION_ANGLE_90_CAP:1;
-+	bool ROTATION_ANGLE_180_CAP:1;
-+	bool ROTATION_ANGLE_270_CAP:1;
-+};
-+
-+/* Underscan position and size */
-+struct ds_underscan_desc {
-+	uint32_t x;
-+	uint32_t y;
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+/* View, timing and other mode related information */
-+struct path_mode {
-+	struct view view;
-+	struct rect_position view_position;
-+	enum view_3d_format view_3d_format;
-+	const struct dc_mode_timing *mode_timing;
-+	enum scaling_transformation scaling;
-+	enum pixel_format pixel_format;
-+	uint32_t display_path_index;
-+	enum tiling_mode tiling_mode;
-+	enum dc_rotation_angle rotation_angle;
-+	bool is_tiling_rotated;
-+	struct rotation_capability rotation_capability;
-+};
-+
-+struct hdmi_info_frame_header {
-+	uint8_t info_frame_type;
-+	uint8_t version;
-+	uint8_t length;
-+};
-+
-+#pragma pack(push)
-+#pragma pack(1)
-+struct info_packet_raw_data {
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t sb[28]; /* sb0~sb27 */
-+};
-+
-+union hdmi_info_packet {
-+	struct avi_info_frame {
-+		struct hdmi_info_frame_header header;
-+
-+		uint8_t CHECK_SUM:8;
-+
-+		uint8_t S0_S1:2;
-+		uint8_t B0_B1:2;
-+		uint8_t A0:1;
-+		uint8_t Y0_Y1_Y2:3;
-+
-+		uint8_t R0_R3:4;
-+		uint8_t M0_M1:2;
-+		uint8_t C0_C1:2;
-+
-+		uint8_t SC0_SC1:2;
-+		uint8_t Q0_Q1:2;
-+		uint8_t EC0_EC2:3;
-+		uint8_t ITC:1;
-+
-+		uint8_t VIC0_VIC7:8;
-+
-+		uint8_t PR0_PR3:4;
-+		uint8_t CN0_CN1:2;
-+		uint8_t YQ0_YQ1:2;
-+
-+		uint16_t bar_top;
-+		uint16_t bar_bottom;
-+		uint16_t bar_left;
-+		uint16_t bar_right;
-+
-+		uint8_t reserved[14];
-+	} bits;
-+
-+	struct info_packet_raw_data packet_raw_data;
-+};
-+
-+struct info_packet {
-+	enum info_frame_flag flags;
-+	union hdmi_info_packet info_packet_hdmi;
-+};
-+
-+struct info_frame {
-+	struct info_packet avi_info_packet;
-+	struct info_packet gamut_packet;
-+	struct info_packet vendor_info_packet;
-+	struct info_packet spd_info_packet;
-+};
-+
-+
-+/* Adjustment parameter */
-+struct adjustment_parameters {
-+	enum adjustment_par_type type;
-+	struct {
-+		enum adjustment_id ajd_id;
-+		enum hw_adjustment_id adj_id_hw;
-+	} timings;
-+};
-+
-+/* Parameters for adjustments*/
-+struct adjustment_params {
-+	enum adjustment_action action;
-+	struct adjustment_parameters params;
-+	const struct display_path *affected_path;
-+};
-+
-+#pragma pack(pop)
-+
-+#endif /* __DAL_SET_MODE_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/signal_types.h b/drivers/gpu/drm/amd/dal/include/signal_types.h
-new file mode 100644
-index 0000000..e95e821
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/signal_types.h
-@@ -0,0 +1,58 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_SIGNAL_TYPES_H__
-+#define __DC_SIGNAL_TYPES_H__
-+
-+enum signal_type {
-+	SIGNAL_TYPE_NONE		= 0L,		/* no signal */
-+	SIGNAL_TYPE_DVI_SINGLE_LINK	= (1 << 0),
-+	SIGNAL_TYPE_DVI_DUAL_LINK	= (1 << 1),
-+	SIGNAL_TYPE_HDMI_TYPE_A		= (1 << 2),
-+	SIGNAL_TYPE_LVDS		= (1 << 3),
-+	SIGNAL_TYPE_RGB			= (1 << 4),
-+	SIGNAL_TYPE_DISPLAY_PORT	= (1 << 5),
-+	SIGNAL_TYPE_DISPLAY_PORT_MST	= (1 << 6),
-+	SIGNAL_TYPE_EDP			= (1 << 7),
-+	SIGNAL_TYPE_WIRELESS		= (1 << 8),	/* Wireless Display */
-+
-+	SIGNAL_TYPE_COUNT		= 9,
-+	SIGNAL_TYPE_ALL			= (1 << SIGNAL_TYPE_COUNT) - 1
-+};
-+
-+/* help functions for signal types manipulation */
-+bool dc_is_hdmi_signal(enum signal_type signal);
-+bool dc_is_dp_sst_signal(enum signal_type signal);
-+bool dc_is_dp_signal(enum signal_type signal);
-+bool dc_is_dp_external_signal(enum signal_type signal);
-+bool dc_is_analog_signal(enum signal_type signal);
-+bool dc_is_embedded_signal(enum signal_type signal);
-+bool dc_is_dvi_signal(enum signal_type signal);
-+bool dc_is_dvi_single_link_signal(enum signal_type signal);
-+bool dc_is_dual_link_signal(enum signal_type signal);
-+bool dc_is_audio_capable_signal(enum signal_type signal);
-+bool dc_is_digital_encoder_compatible_signal(enum signal_type signal);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h b/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-new file mode 100644
-index 0000000..0d3e67c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-@@ -0,0 +1,16 @@
-+/*
-+ * stream_encoder_types.h
-+ *
-+ */
-+#include "encoder_interface.h"
-+
-+#ifndef STREAM_ENCODER_TYPES_H_
-+#define STREAM_ENCODER_TYPES_H_
-+
-+struct stream_encoder {
-+	enum engine_id id;
-+	struct adapter_service *adapter_service;
-+	struct dc_context *ctx;
-+};
-+
-+#endif /* STREAM_ENCODER_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-new file mode 100644
-index 0000000..9c4d92d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-@@ -0,0 +1,150 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
-+#define __DAL_TIMING_GENERATOR_TYPES_H__
-+
-+#include "include/grph_csc_types.h"
-+
-+/**
-+ *  These parameters are required as input when doing blanking/Unblanking
-+*/
-+struct crtc_black_color {
-+	uint32_t black_color_r_cr;
-+	uint32_t black_color_g_y;
-+	uint32_t black_color_b_cb;
-+};
-+
-+/* Contains CRTC vertical/horizontal pixel counters */
-+struct crtc_position {
-+	uint32_t vertical_count;
-+	uint32_t horizontal_count;
-+	uint32_t nominal_vcount;
-+};
-+
-+/*
-+ * Parameters to enable/disable stereo 3D mode on CRTC
-+ *  - rightEyePolarity: if true, '0' means left eye image and '1' means right
-+ *    eye image.
-+ *	 if false, '0' means right eye image and '1' means left eye image
-+ *  - framePacked:      true when HDMI 1.4a FramePacking 3D format
-+ *    enabled/disabled
-+ */
-+struct crtc_stereo_parameters {
-+	uint8_t PROGRAM_STEREO:1;
-+	uint8_t PROGRAM_POLARITY:1;
-+	uint8_t RIGHT_EYE_POLARITY:1;
-+	uint8_t FRAME_PACKED:1;
-+};
-+
-+struct crtc_stereo_status {
-+	uint8_t ENABLED:1;
-+	uint8_t CURRENT_FRAME_IS_RIGHT_EYE:1;
-+	uint8_t CURRENT_FRAME_IS_ODD_FIELD:1;
-+	uint8_t FRAME_PACKED:1;
-+	uint8_t PENDING_RESET:1;
-+};
-+
-+enum dcp_gsl_purpose {
-+	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
-+	DCP_GSL_PURPOSE_STEREO3D_PHASE,
-+	DCP_GSL_PURPOSE_UNDEFINED
-+};
-+
-+struct dcp_gsl_params {
-+	enum sync_source gsl_group;
-+	enum dcp_gsl_purpose gsl_purpose;
-+	bool timing_server;
-+	bool overlay_present;
-+	bool gsl_paused;
-+};
-+
-+struct vbi_end_signal_setup {
-+	uint32_t minimum_interval_in_us; /* microseconds */
-+	uint32_t pixel_clock; /* in KHz */
-+	bool scaler_enabled;
-+	bool interlace;
-+	uint32_t src_height;
-+	uint32_t overscan_top;
-+	uint32_t overscan_bottom;
-+	uint32_t v_total;
-+	uint32_t v_addressable;
-+	uint32_t h_total;
-+};
-+
-+#define LEFT_EYE_3D_PRIMARY_SURFACE 1
-+#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
-+
-+enum test_pattern_dyn_range {
-+	TEST_PATTERN_DYN_RANGE_VESA = 0,
-+	TEST_PATTERN_DYN_RANGE_CEA
-+};
-+
-+enum test_pattern_mode {
-+	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
-+	TEST_PATTERN_MODE_VERTICALBARS,
-+	TEST_PATTERN_MODE_HORIZONTALBARS,
-+	TEST_PATTERN_MODE_SINGLERAMP_RGB,
-+	TEST_PATTERN_MODE_DUALRAMP_RGB
-+};
-+
-+enum test_pattern_color_format {
-+	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_8,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_10,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_12
-+};
-+
-+enum controller_dp_test_pattern {
-+	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
-+	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
-+	CONTROLLER_DP_TEST_PATTERN_PRBS7,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
-+	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
-+	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-+};
-+
-+struct timing_generator {
-+	uint32_t *regs;
-+	struct bios_parser *bp;
-+	enum controller_id controller_id;
-+	struct dc_context *ctx;
-+	uint32_t max_h_total;
-+	uint32_t max_v_total;
-+
-+	uint32_t min_h_blank;
-+	uint32_t min_h_front_porch;
-+	uint32_t min_h_back_porch;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h b/drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
-new file mode 100644
-index 0000000..16e3521
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
-@@ -0,0 +1,69 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_LIST_QUERY_INTERFACE_H__
-+#define __DAL_TIMING_LIST_QUERY_INTERFACE_H__
-+
-+/* External dependencies */
-+#include "include/dcs_interface.h"
-+
-+/* Forward declarations */
-+struct dal;
-+struct dal_timing_list_query;
-+
-+enum timing_support_level {
-+	TIMING_SUPPORT_LEVEL_UNDEFINED,
-+	/* assumed to be guaranteed supported by display,
-+	* usually one timing is marked as native */
-+	TIMING_SUPPORT_LEVEL_NATIVE,
-+	/* user wants DAL to drive this timing as if Display supports it */
-+	TIMING_SUPPORT_LEVEL_GUARANTEED,
-+	/* user wants DAL to drive this timing even if display
-+	* may not support it */
-+	TIMING_SUPPORT_LEVEL_NOT_GUARANTEED
-+};
-+
-+struct timing_list_query_init_data {
-+	struct dal *dal; /* an instance of DAL */
-+	struct timing_service *timing_srv;
-+	struct dcs *dcs;
-+	uint32_t display_index;
-+};
-+
-+struct dal_timing_list_query *dal_timing_list_query_create(
-+		struct timing_list_query_init_data *init_data);
-+
-+void dal_timing_list_query_destroy(struct dal_timing_list_query **tlsq);
-+
-+/* Get count of mode timings in the list. */
-+uint32_t dal_timing_list_query_get_mode_timing_count(
-+	const struct dal_timing_list_query *tlsq);
-+
-+const struct dc_mode_timing *dal_timing_list_query_get_mode_timing_at_index(
-+	const struct dal_timing_list_query *tlsq,
-+	uint32_t index);
-+
-+
-+#endif /* __DAL_TIMING_LIST_QUERY_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/vector.h b/drivers/gpu/drm/amd/dal/include/vector.h
-new file mode 100644
-index 0000000..8233b7c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/vector.h
-@@ -0,0 +1,150 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_VECTOR_H__
-+#define __DAL_VECTOR_H__
-+
-+struct vector {
-+	uint8_t *container;
-+	uint32_t struct_size;
-+	uint32_t count;
-+	uint32_t capacity;
-+	struct dc_context *ctx;
-+};
-+
-+bool dal_vector_construct(
-+	struct vector *vector,
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size);
-+
-+struct vector *dal_vector_create(
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size);
-+
-+/* 'initial_value' is optional. If initial_value not supplied,
-+ * each "structure" in the vector will contain zeros by default. */
-+struct vector *dal_vector_presized_create(
-+	struct dc_context *ctx,
-+	uint32_t size,
-+	void *initial_value,
-+	uint32_t struct_size);
-+
-+void dal_vector_destruct(
-+	struct vector *vector);
-+
-+void dal_vector_destroy(
-+	struct vector **vector);
-+
-+uint32_t dal_vector_get_count(
-+	const struct vector *vector);
-+
-+/* dal_vector_insert_at
-+ * reallocate container if necessary
-+ * then shell items at right and insert
-+ * return if the container modified
-+ * do not check that index belongs to container
-+ * since the function is private and index is going to be calculated
-+ * either with by function or as get_count+1 */
-+bool dal_vector_insert_at(
-+	struct vector *vector,
-+	const void *what,
-+	uint32_t position);
-+
-+bool dal_vector_append(
-+	struct vector *vector,
-+	const void *item);
-+
-+/* operator[] */
-+void *dal_vector_at_index(
-+	const struct vector *vector,
-+	uint32_t index);
-+
-+void dal_vector_set_at_index(
-+	const struct vector *vector,
-+	const void *what,
-+	uint32_t index);
-+
-+/* create a clone (copy) of a vector */
-+struct vector *dal_vector_clone(
-+	const struct vector *vector_other);
-+
-+/* dal_vector_remove_at_index
-+ * Shifts elements on the right from remove position to the left,
-+ * removing an element at position by overwrite means*/
-+bool dal_vector_remove_at_index(
-+	struct vector *vector,
-+	uint32_t index);
-+
-+uint32_t dal_vector_capacity(const struct vector *vector);
-+
-+bool dal_vector_reserve(struct vector *vector, uint32_t capacity);
-+
-+void dal_vector_clear(struct vector *vector);
-+
-+/***************************************************************************
-+ * Macro definitions of TYPE-SAFE versions of vector set/get functions.
-+ ***************************************************************************/
-+
-+#define DAL_VECTOR_INSERT_AT(vector_type, type_t) \
-+	static bool vector_type##_vector_insert_at( \
-+		struct vector *vector, \
-+		type_t what, \
-+		uint32_t position) \
-+{ \
-+	return dal_vector_insert_at(vector, what, position); \
-+}
-+
-+#define DAL_VECTOR_APPEND(vector_type, type_t) \
-+	static bool vector_type##_vector_append( \
-+		struct vector *vector, \
-+		type_t item) \
-+{ \
-+	return dal_vector_append(vector, item); \
-+}
-+
-+/* Note: "type_t" is the ONLY token accepted by "checkpatch.pl" and by
-+ * "checkcommit" as *return type*.
-+ * For uniformity reasons "type_t" is used for all type-safe macro
-+ * definitions here. */
-+#define DAL_VECTOR_AT_INDEX(vector_type, type_t) \
-+	static type_t vector_type##_vector_at_index( \
-+		const struct vector *vector, \
-+		uint32_t index) \
-+{ \
-+	return dal_vector_at_index(vector, index); \
-+}
-+
-+#define DAL_VECTOR_SET_AT_INDEX(vector_type, type_t) \
-+	static void vector_type##_vector_set_at_index( \
-+		const struct vector *vector, \
-+		type_t what, \
-+		uint32_t index) \
-+{ \
-+	dal_vector_set_at_index(vector, what, index); \
-+}
-+
-+#endif /* __DAL_VECTOR_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-new file mode 100644
-index 0000000..c229f5a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -0,0 +1,135 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_VIDEO_CSC_TYPES_H__
-+#define __DAL_VIDEO_CSC_TYPES_H__
-+
-+#include "video_gamma_types.h"
-+
-+enum ovl_alpha_blending_mode {
-+	OVL_ALPHA_PER_PIXEL_GRPH_ALPHA_MODE = 0,
-+	OVL_ALPHA_PER_PIXEL_OVL_ALPHA_MODE
-+};
-+
-+enum ovl_color_space {
-+	OVL_COLOR_SPACE_UNKNOWN = 0,
-+	OVL_COLOR_SPACE_RGB,
-+	OVL_COLOR_SPACE_YUV601,
-+	OVL_COLOR_SPACE_YUV709
-+};
-+
-+enum ovl_surface_format {
-+	OVL_SURFACE_FORMAT_UNKNOWN = 0,
-+	OVL_SURFACE_FORMAT_YUY2,
-+	OVL_SURFACE_FORMAT_UYVY,
-+	OVL_SURFACE_FORMAT_RGB565,
-+	OVL_SURFACE_FORMAT_RGB555,
-+	OVL_SURFACE_FORMAT_RGB32,
-+	OVL_SURFACE_FORMAT_YUV444,
-+	OVL_SURFACE_FORMAT_RGB32_2101010
-+};
-+
-+struct ovl_color_adjust_option {
-+	uint32_t ALLOW_OVL_RGB_ADJUST:1;
-+	uint32_t ALLOW_OVL_TEMPERATURE:1;
-+	uint32_t FULL_RANGE:1; /* 0 for limited range it'is default for YUV */
-+	uint32_t OVL_MATRIX:1;
-+	uint32_t RESERVED:28;
-+};
-+
-+struct overlay_adjust_item {
-+	int32_t adjust; /* InInteger */
-+	int32_t adjust_divider;
-+};
-+
-+enum overlay_csc_adjust_type {
-+	OVERLAY_CSC_ADJUST_TYPE_BYPASS = 0,
-+	OVERLAY_CSC_ADJUST_TYPE_HW, /* without adjustments */
-+	OVERLAY_CSC_ADJUST_TYPE_SW  /* use adjustments */
-+};
-+
-+enum overlay_gamut_adjust_type {
-+	OVERLAY_GAMUT_ADJUST_TYPE_BYPASS = 0,
-+	OVERLAY_GAMUT_ADJUST_TYPE_SW /* use adjustments */
-+};
-+
-+#define TEMPERATURE_MATRIX_SIZE 9
-+#define MAXTRIX_SIZE TEMPERATURE_MAXTRIX_SIZE
-+#define MAXTRIX_SIZE_WITH_OFFSET 12
-+
-+/* overlay adjustment input */
-+union ovl_csc_flag {
-+	uint32_t u_all;
-+	struct {
-+		uint32_t CONFIG_IS_CHANGED:1;
-+		uint32_t RESERVED:31;
-+	} bits;
-+};
-+
-+struct ovl_csc_adjustment {
-+	enum ovl_color_space ovl_cs;
-+	struct ovl_color_adjust_option ovl_option;
-+	enum dc_color_depth display_color_depth;
-+	uint32_t lb_color_depth;
-+	enum pixel_format desktop_surface_pixel_format;
-+	enum ovl_surface_format ovl_sf;
-+	/* API adjustment */
-+	struct overlay_adjust_item overlay_brightness;
-+	struct overlay_adjust_item overlay_gamma;
-+	struct overlay_adjust_item overlay_contrast;
-+	struct overlay_adjust_item overlay_saturation;
-+	struct overlay_adjust_item overlay_hue; /* unit in degree from API. */
-+	int32_t f_temperature[TEMPERATURE_MATRIX_SIZE];
-+	uint32_t temperature_divider;
-+	/* OEM/Application matrix related. */
-+	int32_t matrix[MAXTRIX_SIZE_WITH_OFFSET];
-+	uint32_t matrix_divider;
-+
-+	/* DCE50 parameters */
-+	struct regamma_lut regamma;
-+	enum overlay_gamma_adjust adjust_gamma_type;
-+	enum overlay_csc_adjust_type adjust_csc_type;
-+	enum overlay_gamut_adjust_type adjust_gamut_type;
-+	union ovl_csc_flag flag;
-+
-+};
-+
-+enum ovl_csc_adjust_item {
-+	OVERLAY_BRIGHTNESS = 0,
-+	OVERLAY_GAMMA,
-+	OVERLAY_CONTRAST,
-+	OVERLAY_SATURATION,
-+	OVERLAY_HUE,
-+	OVERLAY_ALPHA,
-+	OVERLAY_ALPHA_PER_PIX,
-+	OVERLAY_COLOR_TEMPERATURE
-+};
-+
-+struct input_csc_matrix {
-+	enum color_space color_space;
-+	uint16_t regval[12];
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-new file mode 100644
-index 0000000..dc294b6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -0,0 +1,56 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_VIDEO_GAMMA_TYPES_H__
-+#define __DAL_VIDEO_GAMMA_TYPES_H__
-+
-+#include "set_mode_types.h"
-+
-+enum overlay_gamma_adjust {
-+	OVERLAY_GAMMA_ADJUST_BYPASS,
-+	OVERLAY_GAMMA_ADJUST_HW, /* without adjustments */
-+	OVERLAY_GAMMA_ADJUST_SW /* use adjustments */
-+
-+};
-+
-+union video_gamma_flag {
-+	struct {
-+		uint32_t CONFIG_IS_CHANGED:1;
-+		uint32_t RESERVED:31;
-+	} bits;
-+	uint32_t u_all;
-+};
-+
-+struct overlay_gamma_parameters {
-+	union video_gamma_flag flag;
-+	int32_t ovl_gamma_cont;
-+	enum overlay_gamma_adjust adjust_type;
-+	enum pixel_format desktop_surface;
-+	struct regamma_lut regamma;
-+
-+	/* here we grow with parameters if necessary */
-+};
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0511-drm-amd-dal-Adding-amdgpu_dm-for-dal-v2.patch b/common/recipes-kernel/linux/files/0511-drm-amd-dal-Adding-amdgpu_dm-for-dal-v2.patch
deleted file mode 100644
index c709f6e8..00000000
--- a/common/recipes-kernel/linux/files/0511-drm-amd-dal-Adding-amdgpu_dm-for-dal-v2.patch
+++ /dev/null
@@ -1,6016 +0,0 @@
-From a04ef2511da8e6d563253dd70f193979ca0ebb81 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 25 Nov 2015 14:48:16 -0500
-Subject: [PATCH 0511/1110] drm/amd/dal: Adding amdgpu_dm for dal (v2)
-
-v2: agd: fix for API changes in kernel 4.6
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile         |   17 +
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    |  251 ++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  |  350 +++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 1318 +++++++++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h      |  166 ++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c  |  814 +++++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h  |  122 +
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  353 +++
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h    |   36 +
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 2390 ++++++++++++++++++++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |   96 +
- 11 files changed, 5913 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
-new file mode 100644
-index 0000000..65ad370
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
-@@ -0,0 +1,17 @@
-+#
-+# Makefile for the 'dm' sub-component of DAL.
-+# It provides the control and status of dm blocks.
-+
-+
-+
-+AMDGPUDM = amdgpu_dm_types.o amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o
-+
-+ifneq ($(CONFIG_DRM_AMD_DAL),)
-+AMDGPUDM += amdgpu_dal_services.o amdgpu_dc_helpers.o
-+endif
-+
-+subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc
-+
-+AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))
-+
-+AMD_DAL_FILES += $(AMDGPU_DM)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-new file mode 100644
-index 0000000..a497093
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -0,0 +1,251 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/string.h>
-+#include <linux/acpi.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/amdgpu_drm.h>
-+
-+#include "amdgpu.h"
-+#include "dal_services.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+#include "amdgpu_dm_types.h"
-+#include "amdgpu_pm.h"
-+
-+/*
-+#include "logger_interface.h"
-+#include "acpimethod_atif.h"
-+#include "amdgpu_powerplay.h"
-+#include "amdgpu_notifications.h"
-+*/
-+
-+/* if the pointer is not NULL, the allocated memory is zeroed */
-+void *dc_service_alloc(struct dc_context *ctx, uint32_t size)
-+{
-+	return kzalloc(size, GFP_KERNEL);
-+}
-+
-+/* Reallocate memory. The contents will remain unchanged.*/
-+void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size)
-+{
-+	return krealloc(ptr, size, GFP_KERNEL);
-+}
-+
-+void dc_service_memmove(void *dst, const void *src, uint32_t size)
-+{
-+	memmove(dst, src, size);
-+}
-+
-+void dc_service_free(struct dc_context *ctx, void *p)
-+{
-+	kfree(p);
-+}
-+
-+void dc_service_memset(void *p, int32_t c, uint32_t count)
-+{
-+	memset(p, c, count);
-+}
-+
-+int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count)
-+{
-+	return memcmp(p1, p2, count);
-+}
-+
-+int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count)
-+{
-+	return strncmp(p1, p2, count);
-+}
-+
-+void dc_service_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
-+{
-+	if (milliseconds >= 20)
-+		msleep(milliseconds);
-+	else
-+		usleep_range(milliseconds*1000, milliseconds*1000+1);
-+}
-+
-+void dal_delay_in_nanoseconds(uint32_t nanoseconds)
-+{
-+	ndelay(nanoseconds);
-+}
-+
-+void dc_service_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds)
-+{
-+	udelay(microseconds);
-+}
-+
-+/******************************************************************************
-+ * IRQ Interfaces.
-+ *****************************************************************************/
-+
-+void dal_register_timer_interrupt(
-+	struct dc_context *ctx,
-+	struct dc_timer_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *args)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (!adev || !int_params) {
-+		DRM_ERROR("DM_IRQ: invalid input!\n");
-+		return;
-+	}
-+
-+	if (int_params->int_context != INTERRUPT_LOW_IRQ_CONTEXT) {
-+		/* only low irq ctx is supported. */
-+		DRM_ERROR("DM_IRQ: invalid context: %d!\n",
-+				int_params->int_context);
-+		return;
-+	}
-+
-+	amdgpu_dm_irq_register_timer(adev, int_params, ih, args);
-+}
-+
-+void dal_isr_acquire_lock(struct dc_context *ctx)
-+{
-+	/*TODO*/
-+}
-+
-+void dal_isr_release_lock(struct dc_context *ctx)
-+{
-+	/*TODO*/
-+}
-+
-+/******************************************************************************
-+ * End-of-IRQ Interfaces.
-+ *****************************************************************************/
-+
-+bool dal_get_platform_info(struct dc_context *ctx,
-+			struct platform_info_params *params)
-+{
-+	/*TODO*/
-+	return false;
-+}
-+
-+/* Next calls are to power component */
-+bool dc_service_pp_pre_dce_clock_change(struct dc_context *ctx,
-+				struct dal_to_power_info *input,
-+				struct power_to_dal_info *output)
-+{
-+	/*TODO*/
-+	return false;
-+}
-+
-+bool dc_service_pp_post_dce_clock_change(struct dc_context *ctx,
-+	const struct dc_pp_display_configuration *pp_display_cfg)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (adev->pm.dpm_enabled) {
-+
-+		memset(&adev->pm.pm_display_cfg, 0,
-+				sizeof(adev->pm.pm_display_cfg));
-+
-+		adev->pm.pm_display_cfg.cpu_cc6_disable =
-+			pp_display_cfg->cpu_cc6_disable;
-+
-+		adev->pm.pm_display_cfg.cpu_pstate_disable =
-+			pp_display_cfg->cpu_pstate_disable;
-+
-+		adev->pm.pm_display_cfg.cpu_pstate_separation_time =
-+			pp_display_cfg->cpu_pstate_separation_time;
-+
-+		adev->pm.pm_display_cfg.nb_pstate_switch_disable =
-+			pp_display_cfg->nb_pstate_switch_disable;
-+
-+		amd_powerplay_display_configuration_change(
-+				adev->powerplay.pp_handle,
-+				&adev->pm.pm_display_cfg);
-+
-+		/* TODO: replace by a separate call to 'apply display cfg'? */
-+		amdgpu_pm_compute_clocks(adev);
-+	}
-+	return true;
-+#else
-+	return false;
-+#endif
-+}
-+
-+bool dc_service_get_system_clocks_range(struct dc_context *ctx,
-+				struct dal_system_clock_range *sys_clks)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	/* Default values, in case PPLib is not compiled-in. */
-+	sys_clks->max_mclk = 80000;
-+	sys_clks->min_mclk = 80000;
-+
-+	sys_clks->max_sclk = 60000;
-+	sys_clks->min_sclk = 30000;
-+
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (adev->pm.dpm_enabled) {
-+		sys_clks->max_mclk = amdgpu_dpm_get_mclk(adev, false);
-+		sys_clks->min_mclk = amdgpu_dpm_get_mclk(adev, true);
-+
-+		sys_clks->max_sclk = amdgpu_dpm_get_sclk(adev, false);
-+		sys_clks->min_sclk = amdgpu_dpm_get_sclk(adev, true);
-+	}
-+#endif
-+
-+	return true;
-+}
-+
-+
-+bool dc_service_pp_set_display_clock(struct dc_context *ctx,
-+			     struct dal_to_power_dclk *dclk)
-+{
-+	/* TODO: need power component to provide appropriate interface */
-+	return false;
-+}
-+
-+/* end of calls to power component */
-+
-+/* Calls to notification */
-+
-+void dal_notify_setmode_complete(struct dc_context *ctx,
-+	uint32_t h_total,
-+	uint32_t v_total,
-+	uint32_t h_active,
-+	uint32_t v_active,
-+	uint32_t pix_clk_in_khz)
-+{
-+	/*TODO*/
-+}
-+/* End of calls to notification */
-+
-+long dal_get_pid(void)
-+{
-+	return current->pid;
-+}
-+
-+long dal_get_tgid(void)
-+{
-+	return current->tgid;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-new file mode 100644
-index 0000000..beaef70
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -0,0 +1,350 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/string.h>
-+#include <linux/acpi.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/amdgpu_drm.h>
-+#include <drm/drm_edid.h>
-+
-+#include "dc_types.h"
-+#include "amdgpu.h"
-+#include "dc.h"
-+#include "dc_services.h"
-+
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+#include "amdgpu_dm_types.h"
-+
-+/* dc_helpers_parse_edid_caps
-+ *
-+ * Parse edid caps
-+ *
-+ * @edid:	[in] pointer to edid
-+ *  edid_caps:	[in] pointer to edid caps
-+ * @return
-+ *	void
-+ * */
-+enum dc_edid_status dc_helpers_parse_edid_caps(
-+		struct dc_context *ctx,
-+		const struct dc_edid *edid,
-+		struct dc_edid_caps *edid_caps)
-+{
-+	struct edid *edid_buf = (struct edid *) edid->raw_edid;
-+	struct cea_sad *sads;
-+	int sad_count = -1;
-+	int sadb_count = -1;
-+	int i = 0;
-+	int j = 0;
-+	uint8_t *sadb = NULL;
-+
-+	enum dc_edid_status result = EDID_OK;
-+
-+	if (!edid_caps || !edid)
-+		return EDID_BAD_INPUT;
-+
-+	if (!drm_edid_is_valid(edid_buf))
-+		result = EDID_BAD_CHECKSUM;
-+
-+	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
-+					((uint16_t) edid_buf->mfg_id[1])<<8;
-+	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
-+					((uint16_t) edid_buf->prod_code[1])<<8;
-+	edid_caps->serial_number = edid_buf->serial;
-+	edid_caps->manufacture_week = edid_buf->mfg_week;
-+	edid_caps->manufacture_year = edid_buf->mfg_year;
-+
-+	/* One of the four detailed_timings stores the monitor name. It's
-+	 * stored in an array of length 13. */
-+	for (i = 0; i < 4; i++) {
-+		if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
-+			while (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] && j < 13) {
-+				if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
-+					break;
-+
-+				edid_caps->display_name[j] =
-+					edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
-+				j++;
-+			}
-+		}
-+	}
-+
-+	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
-+	if (sad_count <= 0) {
-+		DRM_INFO("SADs count is: %d, don't need to read it\n",
-+				sad_count);
-+		return result;
-+	}
-+
-+	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
-+	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
-+		struct cea_sad *sad = &sads[i];
-+
-+		edid_caps->audio_modes[i].format_code = sad->format;
-+		edid_caps->audio_modes[i].channel_count = sad->channels;
-+		edid_caps->audio_modes[i].sample_rate = sad->freq;
-+		edid_caps->audio_modes[i].sample_size = sad->byte2;
-+	}
-+
-+	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
-+
-+	if (sadb_count < 0) {
-+		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
-+		sadb_count = 0;
-+	}
-+
-+	if (sadb_count)
-+		edid_caps->speaker_flags = sadb[0];
-+	else
-+		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
-+
-+	kfree(sads);
-+	kfree(sadb);
-+
-+	return result;
-+}
-+
-+
-+static struct amdgpu_connector *get_connector_for_sink(
-+	struct drm_device *dev,
-+	const struct dc_sink *sink)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector = NULL;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (aconnector->dc_sink == sink)
-+			break;
-+	}
-+
-+	return aconnector;
-+}
-+
-+static struct amdgpu_connector *get_connector_for_link(
-+	struct drm_device *dev,
-+	const struct dc_link *link)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector = NULL;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (aconnector->dc_link == link)
-+			break;
-+	}
-+
-+	return aconnector;
-+}
-+
-+/*
-+ * Writes payload allocation table in immediate downstream device.
-+ */
-+bool dc_helpers_dp_mst_write_payload_allocation_table(
-+		struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		struct dp_mst_stream_allocation *alloc_entity,
-+		bool enable)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_crtc *crtc;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	struct drm_dp_mst_port *mst_port;
-+	int slots = 0;
-+	bool ret;
-+	int clock;
-+	int bpp;
-+	int pbn = 0;
-+
-+	aconnector = get_connector_for_sink(dev, sink);
-+	crtc = aconnector->base.state->crtc;
-+
-+	if (!aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+	mst_port = aconnector->port;
-+
-+	if (enable) {
-+		clock = crtc->state->mode.clock;
-+		/* TODO remove following hardcode value */
-+		bpp = 30;
-+
-+		/* TODO need to know link rate */
-+
-+		pbn = drm_dp_calc_pbn_mode(clock, bpp);
-+
-+		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, &slots);
-+
-+		if (!ret)
-+			return false;
-+
-+	} else {
-+		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
-+	}
-+
-+	alloc_entity->slot_count = slots;
-+	alloc_entity->pbn = pbn;
-+	alloc_entity->pbn_per_slot = mst_mgr->pbn_div;
-+
-+	ret = drm_dp_update_payload_part1(mst_mgr);
-+	if (ret)
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * Polls for ACT (allocation change trigger) handled and sends
-+ * ALLOCATE_PAYLOAD message.
-+ */
-+bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		struct dc_context *ctx,
-+		const struct dc_sink *sink)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	int ret;
-+
-+	aconnector = get_connector_for_sink(dev, sink);
-+
-+	if (!aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	ret = drm_dp_check_act_status(mst_mgr);
-+
-+	if (ret)
-+		return false;
-+
-+	return true;
-+}
-+
-+bool dc_helpers_dp_mst_send_payload_allocation(
-+		struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		bool enable)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	struct drm_dp_mst_port *mst_port;
-+	int ret;
-+
-+	aconnector = get_connector_for_sink(dev, sink);
-+
-+	mst_port = aconnector->port;
-+
-+	if (!aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	ret = drm_dp_update_payload_part2(mst_mgr);
-+
-+	if (ret)
-+		return false;
-+
-+	if (!enable)
-+		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
-+
-+	return true;
-+}
-+
-+void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
-+{
-+	uint8_t esi[8] = { 0 };
-+	uint8_t dret;
-+	bool new_irq_handled = true;
-+	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
-+
-+	/* DPCD 0x2002 - 0x2008 for down stream IRQ from MST, eDP etc. */
-+	dret = drm_dp_dpcd_read(
-+		&aconnector->dm_dp_aux.aux,
-+		DP_SINK_COUNT_ESI, esi, 8);
-+
-+	while ((dret == 8) && new_irq_handled) {
-+		uint8_t retry;
-+
-+		DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
-+
-+		/* handle HPD short pulse irq */
-+		drm_dp_mst_hpd_irq(&aconnector->mst_mgr, esi, &new_irq_handled);
-+
-+		if (new_irq_handled) {
-+			/* ACK at DPCD to notify down stream */
-+			for (retry = 0; retry < 3; retry++) {
-+				uint8_t wret;
-+
-+				wret = drm_dp_dpcd_write(
-+					&aconnector->dm_dp_aux.aux,
-+					DP_SINK_COUNT_ESI + 1,
-+					&esi[1],
-+					3);
-+				if (wret == 3)
-+					break;
-+			}
-+
-+			/* check if there is new irq to be handle */
-+			dret = drm_dp_dpcd_read(
-+				&aconnector->dm_dp_aux.aux,
-+				DP_SINK_COUNT_ESI, esi, 8);
-+		}
-+	}
-+}
-+
-+bool dc_helpers_dp_mst_start_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (aconnector)
-+		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
-+
-+	return true;
-+}
-+
-+void dc_helpers_dp_mst_stop_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (aconnector)
-+		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-new file mode 100644
-index 0000000..37810ff
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -0,0 +1,1318 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services_types.h"
-+#include "dc.h"
-+
-+#include "vid.h"
-+#include "amdgpu.h"
-+#include "atom.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_types.h"
-+
-+#include "amd_shared.h"
-+#include "amdgpu_dm_irq.h"
-+#include "dc_helpers.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+#include "ivsrcid/ivsrcid_vislands30.h"
-+
-+#include "oss/oss_3_0_d.h"
-+#include "oss/oss_3_0_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+
-+#include <drm/drm_atomic.h>
-+#include <drm/drm_atomic_helper.h>
-+#include <drm/drm_dp_mst_helper.h>
-+
-+/* TODO: Remove when mc access work around is removed */
-+static const u32 crtc_offsets[] =
-+{
-+	CRTC0_REGISTER_OFFSET,
-+	CRTC1_REGISTER_OFFSET,
-+	CRTC2_REGISTER_OFFSET,
-+	CRTC3_REGISTER_OFFSET,
-+	CRTC4_REGISTER_OFFSET,
-+	CRTC5_REGISTER_OFFSET,
-+	CRTC6_REGISTER_OFFSET
-+};
-+/* TODO: End of when Remove mc access work around is removed */
-+
-+/* Define variables here
-+ * These values will be passed to DAL for feature enable purpose
-+ * Disable ALL for HDMI light up
-+ * TODO: follow up if need this mechanism*/
-+struct dal_override_parameters display_param = {
-+	.bool_param_enable_mask = 0,
-+	.bool_param_values = 0,
-+	.int_param_values[DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS] = DAL_PARAM_INVALID_INT,
-+	.int_param_values[DAL_PARAM_DRR_SUPPORT] = DAL_PARAM_INVALID_INT,
-+};
-+
-+/* Debug facilities */
-+#define AMDGPU_DM_NOT_IMPL(fmt, ...) \
-+	DRM_INFO("DM_NOT_IMPL: " fmt, ##__VA_ARGS__)
-+
-+/*
-+ * dm_vblank_get_counter
-+ *
-+ * @brief
-+ * Get counter for number of vertical blanks
-+ *
-+ * @param
-+ * struct amdgpu_device *adev - [in] desired amdgpu device
-+ * int disp_idx - [in] which CRTC to get the counter from
-+ *
-+ * @return
-+ * Counter for vertical blanks
-+ */
-+static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
-+{
-+	if (crtc >= adev->mode_info.num_crtc)
-+		return 0;
-+	else {
-+		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
-+
-+		if (NULL == acrtc->target) {
-+			DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc);
-+			return 0;
-+		}
-+
-+		return dc_target_get_vblank_counter(acrtc->target);
-+	}
-+}
-+
-+static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
-+					u32 *vbl, u32 *position)
-+{
-+	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
-+		return -EINVAL;
-+
-+/* TODO: #DAL3 Implement scanoutpos
-+	dal_get_crtc_scanoutpos(adev->dm.dal, crtc, vbl, position);
-+*/
-+	return 0;
-+}
-+
-+static u32 dm_hpd_get_gpio_reg(struct amdgpu_device *adev)
-+{
-+	return mmDC_GPIO_HPD_A;
-+}
-+
-+
-+static bool dm_is_display_hung(struct amdgpu_device *adev)
-+{
-+	/* TODO: #DAL3 need to replace
-+	u32 crtc_hung = 0;
-+	u32 i, j, tmp;
-+
-+	crtc_hung = dal_get_connected_targets_vector(adev->dm.dal);
-+
-+	for (j = 0; j < 10; j++) {
-+		for (i = 0; i < adev->mode_info.num_crtc; i++) {
-+			if (crtc_hung & (1 << i)) {
-+				int32_t vpos1, hpos1;
-+				int32_t vpos2, hpos2;
-+
-+				tmp = dal_get_crtc_scanoutpos(
-+					adev->dm.dal,
-+					i,
-+					&vpos1,
-+					&hpos1);
-+				udelay(10);
-+				tmp = dal_get_crtc_scanoutpos(
-+					adev->dm.dal,
-+					i,
-+					&vpos2,
-+					&hpos2);
-+
-+				if (hpos1 != hpos2 && vpos1 != vpos2)
-+					crtc_hung &= ~(1 << i);
-+			}
-+		}
-+
-+		if (crtc_hung == 0)
-+			return false;
-+	}
-+*/
-+	return true;
-+}
-+
-+/* TODO: Remove mc access work around*/
-+static void dm_stop_mc_access(struct amdgpu_device *adev,
-+				     struct amdgpu_mode_mc_save *save)
-+{
-+
-+	u32 crtc_enabled, tmp;
-+	int i;
-+
-+	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
-+	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
-+
-+	/* disable VGA render */
-+	tmp = RREG32(mmVGA_RENDER_CONTROL);
-+	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
-+	WREG32(mmVGA_RENDER_CONTROL, tmp);
-+
-+	/* blank the display controllers */
-+	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-+		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
-+					     CRTC_CONTROL, CRTC_MASTER_EN);
-+		if (crtc_enabled) {
-+#if 0
-+			u32 frame_count;
-+			int j;
-+
-+			save->crtc_enabled[i] = true;
-+			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
-+			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
-+				amdgpu_display_vblank_wait(adev, i);
-+				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
-+				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
-+				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
-+				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
-+			}
-+			/* wait for the next frame */
-+			frame_count = amdgpu_display_vblank_get_counter(adev, i);
-+			for (j = 0; j < adev->usec_timeout; j++) {
-+				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
-+					break;
-+				udelay(1);
-+			}
-+			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
-+			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
-+				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
-+				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
-+			}
-+			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
-+			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
-+				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
-+				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
-+			}
-+#else
-+			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
-+			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
-+			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
-+			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
-+			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
-+			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
-+			save->crtc_enabled[i] = false;
-+			/* ***** */
-+#endif
-+		} else {
-+			save->crtc_enabled[i] = false;
-+		}
-+	}
-+}
-+
-+
-+static void dm_resume_mc_access(struct amdgpu_device *adev,
-+				       struct amdgpu_mode_mc_save *save)
-+{
-+
-+	u32 tmp, frame_count;
-+	int i, j;
-+
-+	/* update crtc base addresses */
-+	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-+		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
-+		       upper_32_bits(adev->mc.vram_start));
-+		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
-+		       upper_32_bits(adev->mc.vram_start));
-+		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
-+		       (u32)adev->mc.vram_start);
-+		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
-+		       (u32)adev->mc.vram_start);
-+
-+		if (save->crtc_enabled[i]) {
-+			tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
-+			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
-+				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
-+				WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
-+			}
-+			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
-+			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
-+				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
-+				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
-+			}
-+			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
-+			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
-+				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
-+				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
-+			}
-+			for (j = 0; j < adev->usec_timeout; j++) {
-+				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
-+				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
-+					break;
-+				udelay(1);
-+			}
-+			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
-+			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
-+			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
-+			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
-+			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
-+			/* wait for the next frame */
-+			frame_count = amdgpu_display_vblank_get_counter(adev, i);
-+			for (j = 0; j < adev->usec_timeout; j++) {
-+				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
-+					break;
-+				udelay(1);
-+			}
-+		}
-+	}
-+
-+	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
-+	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
-+
-+	/* Unlock vga access */
-+	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
-+	mdelay(1);
-+	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
-+}
-+
-+/* End of TODO: Remove mc access work around*/
-+
-+static bool dm_is_idle(void *handle)
-+{
-+	/* XXX todo */
-+	return true;
-+}
-+
-+static int dm_wait_for_idle(void *handle)
-+{
-+	/* XXX todo */
-+	return 0;
-+}
-+
-+static void dm_print_status(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	dev_info(adev->dev, "DCE 10.x registers\n");
-+	/* XXX todo */
-+}
-+
-+static int dm_soft_reset(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	u32 srbm_soft_reset = 0, tmp;
-+
-+	if (dm_is_display_hung(adev))
-+		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
-+
-+	if (srbm_soft_reset) {
-+		dm_print_status(adev);
-+
-+		tmp = RREG32(mmSRBM_SOFT_RESET);
-+		tmp |= srbm_soft_reset;
-+		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-+		WREG32(mmSRBM_SOFT_RESET, tmp);
-+		tmp = RREG32(mmSRBM_SOFT_RESET);
-+
-+		udelay(50);
-+
-+		tmp &= ~srbm_soft_reset;
-+		WREG32(mmSRBM_SOFT_RESET, tmp);
-+		tmp = RREG32(mmSRBM_SOFT_RESET);
-+
-+		/* Wait a little for things to settle down */
-+		udelay(50);
-+		dm_print_status(adev);
-+	}
-+	return 0;
-+}
-+
-+
-+
-+static void dm_pflip_high_irq(void *interrupt_params)
-+{
-+	struct amdgpu_flip_work *works;
-+	struct amdgpu_crtc *amdgpu_crtc;
-+	struct common_irq_params *irq_params = interrupt_params;
-+	struct amdgpu_device *adev = irq_params->adev;
-+	unsigned long flags;
-+	const struct dc *dc = irq_params->adev->dm.dc;
-+	const struct dc_target *dc_target =
-+			dc_get_target_on_irq_source(dc, irq_params->irq_src);
-+	uint8_t link_index = 0;
-+
-+	/* TODO: #flip address all tags together*/
-+	if (dc_target != NULL)
-+		link_index = dc_target_get_link_index(dc_target);
-+
-+	amdgpu_crtc= adev->mode_info.crtcs[link_index];
-+
-+	/* IRQ could occur when in initial stage */
-+	if(amdgpu_crtc == NULL)
-+		return;
-+
-+	spin_lock_irqsave(&adev->ddev->event_lock, flags);
-+	works = amdgpu_crtc->pflip_works;
-+	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
-+		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
-+						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
-+						 amdgpu_crtc->pflip_status,
-+						 AMDGPU_FLIP_SUBMITTED);
-+		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+		return;
-+	}
-+
-+	/* page flip completed. clean up */
-+	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
-+	amdgpu_crtc->pflip_works = NULL;
-+
-+	/* wakeup usersapce */
-+	if(works->event)
-+		drm_send_vblank_event(
-+			adev->ddev,
-+			amdgpu_crtc->crtc_id,
-+			works->event);
-+
-+	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+
-+	drm_crtc_vblank_put(&amdgpu_crtc->base);
-+	schedule_work(&works->unpin_work);
-+}
-+
-+static void dm_crtc_high_irq(void *interrupt_params)
-+{
-+	struct common_irq_params *irq_params = interrupt_params;
-+	struct amdgpu_device *adev = irq_params->adev;
-+	const struct dc *dc = irq_params->adev->dm.dc;
-+	const struct dc_target *dc_target =
-+			dc_get_target_on_irq_source(dc, irq_params->irq_src);
-+	uint8_t link_index = 0;
-+
-+	/* TODO: #flip fix all tags together*/
-+	if (dc_target != NULL)
-+		link_index = dc_target_get_link_index(dc_target);
-+
-+	drm_handle_vblank(adev->ddev, link_index);
-+
-+}
-+
-+static int dm_set_clockgating_state(void *handle,
-+		  enum amd_clockgating_state state)
-+{
-+	return 0;
-+}
-+
-+static int dm_set_powergating_state(void *handle,
-+		  enum amd_powergating_state state)
-+{
-+	return 0;
-+}
-+
-+/* Prototypes of private functions */
-+static int dm_early_init(void* handle);
-+
-+static void detect_on_all_dc_links(struct amdgpu_display_manager *dm)
-+{
-+	uint32_t i;
-+	const struct dc_link *dc_link;
-+	struct dc_caps caps = { 0 };
-+
-+	dc_get_caps(dm->dc, &caps);
-+
-+	for (i = 0; i < caps.max_links; i++) {
-+		dc_link = dc_get_link_at_index(dm->dc, i);
-+		dc_link_detect(dc_link);
-+	}
-+}
-+
-+/* Init display KMS
-+ *
-+ * Returns 0 on success
-+ */
-+int amdgpu_dm_init(struct amdgpu_device *adev)
-+{
-+	struct dal_init_data init_data;
-+	struct drm_device *ddev = adev->ddev;
-+	adev->dm.ddev = adev->ddev;
-+	adev->dm.adev = adev;
-+
-+	/* Zero all the fields */
-+	memset(&init_data, 0, sizeof(init_data));
-+
-+	/* initialize DAL's lock (for SYNC context use) */
-+	spin_lock_init(&adev->dm.dal_lock);
-+
-+	/* initialize DAL's mutex */
-+	mutex_init(&adev->dm.dal_mutex);
-+
-+	if(amdgpu_dm_irq_init(adev)) {
-+		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
-+		goto error;
-+	}
-+
-+	if (ddev->pdev) {
-+		init_data.bdf_info.DEVICE_NUMBER = PCI_SLOT(ddev->pdev->devfn);
-+		init_data.bdf_info.FUNCTION_NUMBER =
-+			PCI_FUNC(ddev->pdev->devfn);
-+		if (ddev->pdev->bus)
-+			init_data.bdf_info.BUS_NUMBER = ddev->pdev->bus->number;
-+	}
-+
-+	init_data.display_param = display_param;
-+
-+	init_data.asic_id.chip_family = adev->family;
-+
-+	init_data.asic_id.pci_revision_id = adev->rev_id;
-+	init_data.asic_id.hw_internal_rev = adev->external_rev_id;
-+
-+	init_data.asic_id.vram_width = adev->mc.vram_width;
-+	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
-+	init_data.asic_id.atombios_base_address =
-+		adev->mode_info.atom_context->bios;
-+	init_data.asic_id.runtime_flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME = 1;
-+
-+	if (adev->asic_type == CHIP_CARRIZO)
-+		init_data.asic_id.runtime_flags.flags.bits.GNB_WAKEUP_SUPPORTED = 1;
-+
-+	init_data.driver = adev;
-+
-+	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
-+
-+	if (!adev->dm.cgs_device) {
-+		DRM_ERROR("amdgpu: failed to create cgs device.\n");
-+		goto error;
-+	}
-+
-+	init_data.cgs_device = adev->dm.cgs_device;
-+
-+	adev->dm.dal = NULL;
-+
-+	/* enable gpu scaling in DAL */
-+	init_data.display_param.bool_param_enable_mask |=
-+		1 << DAL_PARAM_ENABLE_GPU_SCALING;
-+	init_data.display_param.bool_param_values |=
-+		1 << DAL_PARAM_ENABLE_GPU_SCALING;
-+
-+	/* Display Core create. */
-+	adev->dm.dc = dc_create(&init_data);
-+
-+	if (amdgpu_dm_initialize_drm_device(adev)) {
-+		DRM_ERROR(
-+		"amdgpu: failed to initialize sw for display support.\n");
-+		goto error;
-+	}
-+
-+	/* Update the actual used number of crtc */
-+	adev->mode_info.num_crtc = adev->dm.display_indexes_num;
-+
-+	/* TODO: Add_display_info? */
-+
-+	/* TODO use dynamic cursor width */
-+	adev->ddev->mode_config.cursor_width = 128;
-+	adev->ddev->mode_config.cursor_height = 128;
-+
-+	if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
-+		DRM_ERROR(
-+		"amdgpu: failed to initialize sw for display support.\n");
-+		goto error;
-+	}
-+
-+	DRM_INFO("KMS initialized.\n");
-+
-+	return 0;
-+error:
-+	amdgpu_dm_fini(adev);
-+
-+	return -1;
-+}
-+
-+void amdgpu_dm_fini(struct amdgpu_device *adev)
-+{
-+	/*
-+	 * TODO: pageflip, vlank interrupt
-+	 *
-+	 * amdgpu_dm_destroy_drm_device(&adev->dm);
-+	 * amdgpu_dm_irq_fini(adev);
-+	 */
-+
-+	if (adev->dm.cgs_device) {
-+		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
-+		adev->dm.cgs_device = NULL;
-+	}
-+
-+	/* DC Destroy TODO: Replace destroy DAL */
-+	{
-+		dc_destroy(&adev->dm.dc);
-+	}
-+	return;
-+}
-+
-+/* moved from amdgpu_dm_kms.c */
-+void amdgpu_dm_destroy()
-+{
-+}
-+
-+static int dm_sw_init(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int dm_sw_fini(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int dm_hw_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	/* Create DAL display manager */
-+	amdgpu_dm_init(adev);
-+
-+	amdgpu_dm_hpd_init(adev);
-+
-+	return 0;
-+}
-+
-+static int dm_hw_fini(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	amdgpu_dm_hpd_fini(adev);
-+
-+	amdgpu_dm_irq_fini(adev);
-+
-+	return 0;
-+}
-+
-+static int dm_suspend(void *handle)
-+{
-+	struct amdgpu_device *adev = handle;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	struct drm_crtc *crtc;
-+
-+	dc_set_power_state(
-+		dm->dc,
-+		DC_ACPI_CM_POWER_STATE_D3,
-+		DC_VIDEO_POWER_SUSPEND);
-+
-+	amdgpu_dm_irq_suspend(adev);
-+
-+	list_for_each_entry(crtc, &dm->ddev->mode_config.crtc_list, head) {
-+		crtc->mode.clock = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static int dm_resume(void *handle)
-+{
-+	int ret = 0;
-+	struct amdgpu_device *adev = handle;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+
-+	dc_set_power_state(
-+		dm->dc,
-+		DC_ACPI_CM_POWER_STATE_D0,
-+		DC_VIDEO_POWER_ON);
-+
-+	amdgpu_dm_irq_resume(adev);
-+
-+	dc_resume(dm->dc);
-+
-+	detect_on_all_dc_links(dm);
-+
-+	drm_mode_config_reset(adev->ddev);
-+
-+	return ret;
-+}
-+const struct amd_ip_funcs amdgpu_dm_funcs = {
-+	.early_init = dm_early_init,
-+	.late_init = NULL,
-+	.sw_init = dm_sw_init,
-+	.sw_fini = dm_sw_fini,
-+	.hw_init = dm_hw_init,
-+	.hw_fini = dm_hw_fini,
-+	.suspend = dm_suspend,
-+	.resume = dm_resume,
-+	.is_idle = dm_is_idle,
-+	.wait_for_idle = dm_wait_for_idle,
-+	.soft_reset = dm_soft_reset,
-+	.print_status = dm_print_status,
-+	.set_clockgating_state = dm_set_clockgating_state,
-+	.set_powergating_state = dm_set_powergating_state,
-+};
-+
-+/* TODO: it is temporary non-const, should fixed later */
-+static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
-+	.atomic_check = amdgpu_dm_atomic_check,
-+	.atomic_commit = amdgpu_dm_atomic_commit
-+};
-+
-+static bool dm_get_sink_from_link(const struct dc_link *link,
-+						struct amdgpu_connector *aconnector,
-+						const struct dc_sink **sink)
-+{
-+	int i;
-+	*sink = NULL;
-+
-+	if (!link->sink_count) {
-+		DRM_INFO("No sinks on link!\n");
-+		return true;
-+	} else if (link->sink_count > 1 && !aconnector) {
-+		DRM_ERROR("Multi sink link but no connector given!\n");
-+		return false;
-+	}
-+
-+	if (link->sink_count == 1) {
-+		*sink = link->sink[0];
-+		return true;
-+	}
-+
-+	for (i = 0; i < link->sink_count; i++)
-+		if (aconnector->dc_sink == link->sink[i])
-+			*sink =  aconnector->dc_sink;
-+
-+	return true;
-+}
-+
-+void amdgpu_dm_update_connector_after_detect(
-+	struct amdgpu_connector *aconnector)
-+{
-+	struct drm_connector *connector = &aconnector->base;
-+	struct drm_device *dev = connector->dev;
-+	const struct dc_link *dc_link = aconnector->dc_link;
-+	const struct dc_sink *sink;
-+
-+	/* MST handled by drm_mst framework */
-+	if (aconnector->mst_mgr.mst_state)
-+		return;
-+	if (!dm_get_sink_from_link(dc_link, aconnector, &sink)) {
-+		return;
-+	}
-+
-+	if (aconnector->dc_sink == sink) {
-+		/* We got a DP short pulse (Link Loss, DP CTS, etc...).
-+		 * Do nothing!! */
-+		DRM_INFO("DCHPD: connector_id=%d: dc_sink didn't change.\n",
-+				aconnector->connector_id);
-+		return;
-+	}
-+
-+	DRM_INFO("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
-+		aconnector->connector_id, aconnector->dc_sink, sink);
-+
-+	mutex_lock(&dev->mode_config.mutex);
-+
-+	/* 1. Update status of the drm connector
-+	 * 2. Send an event and let userspace tell us what to do */
-+	if (sink) {
-+		/* TODO: check if we still need the S3 mode update workaround.
-+		 * If yes, put it here. */
-+
-+		aconnector->dc_sink = sink;
-+		if (sink->dc_edid.length == 0)
-+			aconnector->edid = NULL;
-+		else {
-+			aconnector->edid =
-+				(struct edid *) sink->dc_edid.raw_edid;
-+			drm_mode_connector_update_edid_property(connector,
-+					aconnector->edid);
-+			amdgpu_dm_connector_get_modes(&aconnector->base);
-+		}
-+	} else {
-+		drm_mode_connector_update_edid_property(connector, NULL);
-+		aconnector->num_modes = 0;
-+		aconnector->dc_sink = NULL;
-+	}
-+
-+	mutex_unlock(&dev->mode_config.mutex);
-+}
-+
-+static void handle_hpd_irq(void *param)
-+{
-+	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
-+	struct drm_connector *connector = &aconnector->base;
-+	struct drm_device *dev = connector->dev;
-+
-+	dc_link_detect(aconnector->dc_link);
-+	amdgpu_dm_update_connector_after_detect(aconnector);
-+	drm_helper_hpd_irq_event(dev);
-+}
-+
-+static void handle_hpd_rx_irq(void *param)
-+{
-+	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
-+	struct drm_connector *connector = &aconnector->base;
-+	struct drm_device *dev = connector->dev;
-+
-+	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) &&
-+			!aconnector->mst_mgr.mst_state) {
-+		/* Downstream Port status changed. */
-+		dc_link_detect(aconnector->dc_link);
-+		amdgpu_dm_update_connector_after_detect(aconnector);
-+		drm_helper_hpd_irq_event(dev);
-+	}
-+
-+	if (aconnector->mst_mgr.mst_state)
-+		dc_helpers_dp_mst_handle_mst_hpd_rx_irq(param);
-+}
-+
-+static void register_hpd_handlers(struct amdgpu_device *adev)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector;
-+	const struct dc_link *dc_link;
-+	struct dc_interrupt_params int_params = {0};
-+
-+	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
-+	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-+
-+	list_for_each_entry(connector,
-+			&dev->mode_config.connector_list, head)	{
-+
-+		aconnector = to_amdgpu_connector(connector);
-+		dc_link = aconnector->dc_link;
-+
-+		int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
-+		int_params.irq_source = dc_link->irq_source_hpd;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				handle_hpd_irq,
-+				(void *) aconnector);
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
-+
-+			/* Also register for DP short pulse (hpd_rx). */
-+			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
-+			int_params.irq_source =	dc_link->irq_source_hpd_rx;
-+
-+			amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+					handle_hpd_rx_irq,
-+					(void *) aconnector);
-+		}
-+	}
-+}
-+
-+/* Register IRQ sources and initialize IRQ callbacks */
-+static int dce110_register_irq_handlers(struct amdgpu_device *adev)
-+{
-+	struct dc *dc = adev->dm.dc;
-+	struct common_irq_params *c_irq_params;
-+	struct dc_interrupt_params int_params = {0};
-+	int r;
-+	int i;
-+	struct dc_caps caps = { 0 };
-+
-+	dc_get_caps(dc, &caps);
-+
-+	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
-+	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-+
-+	/* Actions of amdgpu_irq_add_id():
-+	 * 1. Register a set() function with base driver.
-+	 *    Base driver will call set() function to enable/disable an
-+	 *    interrupt in DC hardware.
-+	 * 2. Register amdgpu_dm_irq_handler().
-+	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
-+	 *    coming from DC hardware.
-+	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
-+	 *    for acknowledging and handling. */
-+
-+	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT;
-+			i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
-+		r = amdgpu_irq_add_id(adev, i, &adev->crtc_irq);
-+		if (r) {
-+			DRM_ERROR("Failed to add crtc irq id!\n");
-+			return r;
-+		}
-+
-+		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-+		int_params.irq_source =
-+			dc_interrupt_to_irq_source(dc, i, 0);
-+
-+		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
-+
-+		c_irq_params->adev = adev;
-+		c_irq_params->irq_src = int_params.irq_source;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				dm_crtc_high_irq, c_irq_params);
-+	}
-+
-+	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
-+			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
-+		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
-+		if (r) {
-+			DRM_ERROR("Failed to add page flip irq id!\n");
-+			return r;
-+		}
-+
-+		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-+		int_params.irq_source =
-+			dc_interrupt_to_irq_source(dc, i, 0);
-+
-+		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
-+
-+		c_irq_params->adev = adev;
-+		c_irq_params->irq_src = int_params.irq_source;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				dm_pflip_high_irq, c_irq_params);
-+
-+	}
-+
-+	/* HPD */
-+	r = amdgpu_irq_add_id(adev, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A,
-+			&adev->hpd_irq);
-+	if (r) {
-+		DRM_ERROR("Failed to add hpd irq id!\n");
-+		return r;
-+	}
-+
-+	register_hpd_handlers(adev);
-+
-+	/* This is a part of HPD initialization. */
-+	drm_kms_helper_poll_init(adev->ddev);
-+
-+	return 0;
-+}
-+
-+static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
-+{
-+	int r;
-+
-+	adev->mode_info.mode_config_initialized = true;
-+
-+	amdgpu_dm_mode_funcs.fb_create =
-+		amdgpu_mode_funcs.fb_create;
-+	amdgpu_dm_mode_funcs.output_poll_changed =
-+		amdgpu_mode_funcs.output_poll_changed;
-+
-+	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
-+
-+	adev->ddev->mode_config.max_width = 16384;
-+	adev->ddev->mode_config.max_height = 16384;
-+
-+	adev->ddev->mode_config.preferred_depth = 24;
-+	adev->ddev->mode_config.prefer_shadow = 1;
-+
-+	adev->ddev->mode_config.fb_base = adev->mc.aper_base;
-+
-+	r = amdgpu_modeset_create_props(adev);
-+	if (r)
-+		return r;
-+
-+	return 0;
-+}
-+
-+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-+
-+static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
-+{
-+	struct amdgpu_display_manager *dm = bl_get_data(bd);
-+
-+	if (dc_link_set_backlight_level(dm->backlight_link,
-+			bd->props.brightness))
-+		return 0;
-+	else
-+		return 1;
-+}
-+
-+static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
-+{
-+	return bd->props.brightness;
-+}
-+
-+static const struct backlight_ops amdgpu_dm_backlight_ops = {
-+	.get_brightness = amdgpu_dm_backlight_get_brightness,
-+	.update_status	= amdgpu_dm_backlight_update_status,
-+};
-+
-+void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
-+{
-+	char bl_name[16];
-+	struct backlight_properties props = { 0 };
-+
-+	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
-+	props.type = BACKLIGHT_RAW;
-+
-+	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
-+			dm->adev->ddev->primary->index);
-+
-+	dm->backlight_dev = backlight_device_register(bl_name,
-+			dm->adev->ddev->dev,
-+			dm,
-+			&amdgpu_dm_backlight_ops,
-+			&props);
-+
-+	if (NULL == dm->backlight_dev)
-+		DRM_ERROR("DM: Backlight registration failed!\n");
-+	else
-+		DRM_INFO("DM: Registered Backlight device: %s\n", bl_name);
-+}
-+
-+#endif
-+
-+/* In this architecture, the association
-+ * connector -> encoder -> crtc
-+ * id not really requried. The crtc and connector will hold the
-+ * display_index as an abstraction to use with DAL component
-+ *
-+ * Returns 0 on success
-+ */
-+int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
-+{
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	uint32_t link_index;
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector;
-+	struct amdgpu_encoder *aencoder;
-+	struct amdgpu_crtc *acrtc;
-+	struct dc_caps caps = { 0 };
-+	uint32_t link_cnt;
-+
-+	dc_get_caps(dm->dc, &caps);
-+	link_cnt = caps.max_links;
-+
-+	if (amdgpu_dm_mode_config_init(dm->adev)) {
-+		DRM_ERROR("DM: Failed to initialize mode config\n");
-+		return -1;
-+	}
-+
-+	/* loops over all connectors on the board */
-+	for (link_index = 0; link_index < link_cnt; link_index++) {
-+
-+		if (link_index > AMDGPU_DM_MAX_DISPLAY_INDEX) {
-+			DRM_ERROR(
-+				"KMS: Cannot support more than %d display indeces\n",
-+					AMDGPU_DM_MAX_DISPLAY_INDEX);
-+			continue;
-+		}
-+
-+		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
-+		if (!aconnector)
-+			goto fail_connector;
-+
-+		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
-+		if (!aencoder)
-+			goto fail_encoder;
-+
-+		acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
-+		if (!acrtc)
-+			goto fail_crtc;
-+
-+		if (amdgpu_dm_crtc_init(
-+			dm,
-+			acrtc,
-+			link_index)) {
-+			DRM_ERROR("KMS: Failed to initialize crtc\n");
-+			goto fail;
-+		}
-+
-+		if (amdgpu_dm_encoder_init(
-+			dm->ddev,
-+			aencoder,
-+			link_index,
-+			acrtc)) {
-+			DRM_ERROR("KMS: Failed to initialize encoder\n");
-+			goto fail;
-+		}
-+
-+		if (amdgpu_dm_connector_init(
-+			dm,
-+			aconnector,
-+			link_index,
-+			aencoder)) {
-+			DRM_ERROR("KMS: Failed to initialize connector\n");
-+			goto fail;
-+		}
-+	}
-+
-+	dm->display_indexes_num = link_cnt;
-+
-+	detect_on_all_dc_links(&adev->dm);
-+	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head)
-+		amdgpu_dm_update_connector_after_detect(to_amdgpu_connector(connector));
-+
-+	/* Software is initialized. Now we can register interrupt handlers. */
-+	switch (adev->asic_type) {
-+	case CHIP_CARRIZO:
-+		if (dce110_register_irq_handlers(dm->adev)) {
-+			DRM_ERROR("DM: Failed to initialize IRQ\n");
-+			return -1;
-+		}
-+		break;
-+	default:
-+		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
-+		return -1;
-+	}
-+
-+	drm_mode_config_reset(dm->ddev);
-+
-+	return 0;
-+
-+fail:
-+	/* clean any dongling drm structure for the last (corrupted)
-+	display target */
-+	amdgpu_dm_crtc_destroy(&acrtc->base);
-+fail_crtc:
-+	amdgpu_dm_encoder_destroy(&aencoder->base);
-+fail_encoder:
-+	amdgpu_dm_connector_destroy(&aconnector->base);
-+fail_connector:
-+	if (dm->backlight_dev) {
-+		backlight_device_unregister(dm->backlight_dev);
-+		dm->backlight_dev = NULL;
-+	}
-+	return -1;
-+}
-+
-+void amdgpu_dm_destroy_drm_device(
-+				struct amdgpu_display_manager *dm)
-+{
-+	drm_mode_config_cleanup(dm->ddev);
-+	/*switch_dev_unregister(&dm->hdmi_audio_dev);*/
-+	return;
-+}
-+
-+/******************************************************************************
-+ * amdgpu_display_funcs functions
-+ *****************************************************************************/
-+
-+
-+static void dm_set_vga_render_state(struct amdgpu_device *adev,
-+					   bool render)
-+{
-+	u32 tmp;
-+
-+	/* Lockout access through VGA aperture*/
-+	tmp = RREG32(mmVGA_HDP_CONTROL);
-+	if (render)
-+		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
-+	else
-+		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
-+	WREG32(mmVGA_HDP_CONTROL, tmp);
-+
-+	/* disable VGA render */
-+	tmp = RREG32(mmVGA_RENDER_CONTROL);
-+	if (render)
-+		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
-+	else
-+		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
-+	WREG32(mmVGA_RENDER_CONTROL, tmp);
-+}
-+
-+/**
-+ * dm_bandwidth_update - program display watermarks
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Calculate and program the display watermarks and line buffer allocation.
-+ */
-+static void dm_bandwidth_update(struct amdgpu_device *adev)
-+{
-+	AMDGPU_DM_NOT_IMPL("%s\n", __func__);
-+}
-+
-+static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
-+				     u8 level)
-+{
-+	/* TODO: translate amdgpu_encoder to display_index and call DAL */
-+	AMDGPU_DM_NOT_IMPL("%s\n", __func__);
-+}
-+
-+static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
-+{
-+	/* TODO: translate amdgpu_encoder to display_index and call DAL */
-+	AMDGPU_DM_NOT_IMPL("%s\n", __func__);
-+	return 0;
-+}
-+
-+/******************************************************************************
-+ * Page Flip functions
-+ ******************************************************************************/
-+
-+void amdgpu_dm_flip_cleanup(
-+	struct amdgpu_device *adev,
-+	struct amdgpu_crtc *acrtc)
-+{
-+	int r;
-+	struct amdgpu_flip_work *works = acrtc->pflip_works;
-+
-+	acrtc->pflip_works = NULL;
-+	acrtc->pflip_status = AMDGPU_FLIP_NONE;
-+
-+	if (works) {
-+		if(works->event)
-+			drm_send_vblank_event(
-+				adev->ddev,
-+				acrtc->crtc_id,
-+				works->event);
-+
-+		r = amdgpu_bo_reserve(works->old_rbo, false);
-+		if (likely(r == 0)) {
-+			r = amdgpu_bo_unpin(works->old_rbo);
-+			if (unlikely(r != 0)) {
-+				DRM_ERROR("failed to unpin buffer after flip\n");
-+			}
-+			amdgpu_bo_unreserve(works->old_rbo);
-+		} else
-+			DRM_ERROR("failed to reserve buffer after flip\n");
-+
-+		drm_gem_object_unreference_unlocked(&works->old_rbo->gem_base);
-+		kfree(works->shared);
-+		kfree(works);
-+	}
-+}
-+
-+/**
-+ * dm_page_flip - called by amdgpu_flip_work_func(), which is triggered
-+ * 			via DRM IOCTL, by user mode.
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @crtc_id: crtc to cleanup pageflip on
-+ * @crtc_base: new address of the crtc (GPU MC address)
-+ *
-+ * Does the actual pageflip (surface address update).
-+ */
-+static void dm_page_flip(struct amdgpu_device *adev,
-+			int crtc_id, u64 crtc_base)
-+{
-+	struct amdgpu_crtc *acrtc;
-+	struct dc_target *target;
-+	struct dc_flip_addrs addr = { {0} };
-+
-+	/*
-+	 * TODO risk of concurrency issues
-+	 *
-+	 * This should guarded by the dal_mutex but we can't do this since the
-+	 * caller uses a spin_lock on event_lock.
-+	 *
-+	 * If we wait on the dal_mutex a second page flip interrupt might come,
-+	 * spin on the event_lock, disabling interrupts while it does so. At
-+	 * this point the core can no longer be pre-empted and return to the
-+	 * thread that waited on the dal_mutex and we're deadlocked.
-+	 *
-+	 * With multiple cores the same essentially happens but might just take
-+	 * a little longer to lock up all cores.
-+	 *
-+	 * The reason we should lock on dal_mutex is so that we can be sure
-+	 * nobody messes with acrtc->target after we read and check its value.
-+	 *
-+	 * We might be able to fix our concurrency issues with a work queue
-+	 * where we schedule all work items (mode_set, page_flip, etc.) and
-+	 * execute them one by one. Care needs to be taken to still deal with
-+	 * any potential concurrency issues arising from interrupt calls.
-+	 */
-+
-+	acrtc = adev->mode_info.crtcs[crtc_id];
-+	target = acrtc->target;
-+
-+	/*
-+	 * Received a page flip call after the display has been reset. Make sure
-+	 * we return the buffers.
-+	 */
-+	if (!target) {
-+		amdgpu_dm_flip_cleanup(adev, acrtc);
-+		return;
-+	}
-+
-+	addr.address.grph.addr.low_part = lower_32_bits(crtc_base);
-+	addr.address.grph.addr.high_part = upper_32_bits(crtc_base);
-+
-+	dc_flip_surface_addrs(
-+			adev->dm.dc,
-+			dc_target_get_status(target)->surfaces,
-+			&addr, 1);
-+}
-+
-+static const struct amdgpu_display_funcs display_funcs = {
-+	.set_vga_render_state = dm_set_vga_render_state,
-+	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-+	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-+	.vblank_wait = NULL, /* not called anywhere */
-+	.is_display_hung = dm_is_display_hung,/* called unconditionally */
-+	.backlight_set_level =
-+		dm_set_backlight_level,/* called unconditionally */
-+	.backlight_get_level =
-+		dm_get_backlight_level,/* called unconditionally */
-+	.hpd_sense = NULL,/* called unconditionally */
-+	.hpd_set_polarity = NULL, /* called unconditionally */
-+	.hpd_get_gpio_reg = dm_hpd_get_gpio_reg,/* called unconditionally */
-+	.page_flip = dm_page_flip, /* called unconditionally */
-+	.page_flip_get_scanoutpos =
-+		dm_crtc_get_scanoutpos,/* called unconditionally */
-+	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-+	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
-+	.stop_mc_access = dm_stop_mc_access, /* called unconditionally */
-+	.resume_mc_access = dm_resume_mc_access, /* called unconditionally */
-+};
-+
-+static void set_display_funcs(struct amdgpu_device *adev)
-+{
-+	if (adev->mode_info.funcs == NULL)
-+		adev->mode_info.funcs = &display_funcs;
-+}
-+
-+static int dm_early_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	set_display_funcs(adev);
-+	amdgpu_dm_set_irq_funcs(adev);
-+
-+	switch (adev->asic_type) {
-+	case CHIP_CARRIZO:
-+		adev->mode_info.num_crtc = 3;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 9;
-+		break;
-+	default:
-+		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
-+		return -EINVAL;
-+	}
-+
-+	/* Note: Do NOT change adev->audio_endpt_rreg and
-+	 * adev->audio_endpt_wreg because they are initialised in
-+	 * amdgpu_device_init() */
-+
-+
-+
-+	return 0;
-+}
-+
-+
-+bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm)
-+{
-+	/* TODO */
-+	return true;
-+}
-+
-+bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm)
-+{
-+	/* TODO */
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-new file mode 100644
-index 0000000..57e9c45
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -0,0 +1,166 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __AMDGPU_DM_H__
-+#define __AMDGPU_DM_H__
-+
-+/*
-+#include "linux/switch.h"
-+*/
-+
-+/*
-+ * This file contains the definition for amdgpu_display_manager
-+ * and its API for amdgpu driver's use.
-+ * This component provides all the display related functionality
-+ * and this is the only component that calls DAL API.
-+ * The API contained here intended for amdgpu driver use.
-+ * The API that is called directly from KMS framework is located
-+ * in amdgpu_dm_kms.h file
-+ */
-+
-+#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
-+/*
-+#include "include/amdgpu_dal_power_if.h"
-+#include "amdgpu_dm_irq.h"
-+*/
-+
-+#include "irq_types.h"
-+
-+/* Forward declarations */
-+struct amdgpu_device;
-+struct drm_device;
-+struct amdgpu_dm_irq_handler_data;
-+
-+struct amdgpu_dm_prev_state {
-+	struct drm_framebuffer *fb;
-+	int32_t x;
-+	int32_t y;
-+	struct drm_display_mode mode;
-+};
-+
-+struct common_irq_params {
-+	struct amdgpu_device *adev;
-+	enum dc_irq_source irq_src;
-+};
-+
-+struct irq_list_head {
-+	struct list_head head;
-+	/* In case this interrupt needs post-processing, 'work' will be queued*/
-+	struct work_struct work;
-+};
-+
-+struct amdgpu_display_manager {
-+	struct dal *dal;
-+	struct dc *dc;
-+	void *cgs_device;
-+	/* lock to be used when DAL is called from SYNC IRQ context */
-+	spinlock_t dal_lock;
-+
-+	struct amdgpu_device *adev;	/*AMD base driver*/
-+	struct drm_device *ddev;	/*DRM base driver*/
-+	u16 display_indexes_num;
-+
-+	struct amdgpu_dm_prev_state prev_state;
-+
-+	/*
-+	 * 'irq_source_handler_table' holds a list of handlers
-+	 * per (DAL) IRQ source.
-+	 *
-+	 * Each IRQ source may need to be handled at different contexts.
-+	 * By 'context' we mean, for example:
-+	 * - The ISR context, which is the direct interrupt handler.
-+	 * - The 'deferred' context - this is the post-processing of the
-+	 *	interrupt, but at a lower priority.
-+	 *
-+	 * Note that handlers are called in the same order as they were
-+	 * registered (FIFO).
-+	 */
-+	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
-+	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
-+
-+	struct common_irq_params
-+	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
-+
-+	struct common_irq_params
-+	vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
-+
-+	/* this spin lock synchronizes access to 'irq_handler_list_table' */
-+	spinlock_t irq_handler_list_table_lock;
-+
-+	/* Timer-related data. */
-+	struct list_head timer_handler_list;
-+	struct workqueue_struct *timer_workqueue;
-+
-+	/* Use dal_mutex for any activity which is NOT syncronized by
-+	 * DRM mode setting locks.
-+	 * For example: amdgpu_dm_hpd_low_irq() calls into DAL *without*
-+	 * DRM mode setting locks being acquired. This is where dal_mutex
-+	 * is acquired before calling into DAL. */
-+	struct mutex dal_mutex;
-+
-+	struct backlight_device *backlight_dev;
-+
-+	const struct dc_link *backlight_link;
-+};
-+
-+
-+/* basic init/fini API */
-+int amdgpu_dm_init(struct amdgpu_device *adev);
-+
-+void amdgpu_dm_fini(struct amdgpu_device *adev);
-+
-+void amdgpu_dm_destroy(void);
-+
-+/* initializes drm_device display related structures, based on the information
-+ * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
-+ * drm_encoder, drm_mode_config
-+ *
-+ * Returns 0 on success
-+ */
-+int amdgpu_dm_initialize_drm_device(
-+	struct amdgpu_device *adev);
-+
-+/* removes and deallocates the drm structures, created by the above function */
-+void amdgpu_dm_destroy_drm_device(
-+	struct amdgpu_display_manager *dm);
-+
-+/* Locking/Mutex */
-+bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm);
-+
-+bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm);
-+
-+/* Register "Backlight device" accessible by user-mode. */
-+void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm);
-+
-+void amdgpu_dm_flip_cleanup(
-+	struct amdgpu_device *adev,
-+	struct amdgpu_crtc *acrtc);
-+
-+extern const struct amd_ip_funcs amdgpu_dm_funcs;
-+
-+void amdgpu_dm_update_connector_after_detect(
-+	struct amdgpu_connector *aconnector);
-+
-+#endif /* __AMDGPU_DM_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-new file mode 100644
-index 0000000..9491fd0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -0,0 +1,814 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <drm/drmP.h>
-+
-+#include "dal_services_types.h"
-+#include "dc.h"
-+
-+#include "amdgpu.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+
-+
-+/******************************************************************************
-+ * Private declarations.
-+ *****************************************************************************/
-+
-+struct handler_common_data {
-+	struct list_head list;
-+	interrupt_handler handler;
-+	void *handler_arg;
-+
-+	/* DM which this handler belongs to */
-+	struct amdgpu_display_manager *dm;
-+};
-+
-+struct amdgpu_dm_irq_handler_data {
-+	struct handler_common_data hcd;
-+	/* DAL irq source which registered for this interrupt. */
-+	enum dc_irq_source irq_source;
-+};
-+
-+struct amdgpu_dm_timer_handler_data {
-+	struct handler_common_data hcd;
-+	struct delayed_work d_work;
-+};
-+
-+
-+#define DM_IRQ_TABLE_LOCK(adev, flags) \
-+	spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
-+
-+#define DM_IRQ_TABLE_UNLOCK(adev, flags) \
-+	spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
-+
-+/******************************************************************************
-+ * Private functions.
-+ *****************************************************************************/
-+
-+static void init_handler_common_data(
-+	struct handler_common_data *hcd,
-+	void (*ih)(void *),
-+	void *args,
-+	struct amdgpu_display_manager *dm)
-+{
-+	hcd->handler = ih;
-+	hcd->handler_arg = args;
-+	hcd->dm = dm;
-+}
-+
-+/**
-+ * dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
-+ *
-+ * @work: work struct
-+ */
-+static void dm_irq_work_func(struct work_struct *work)
-+{
-+	struct list_head *entry;
-+	struct irq_list_head *irq_list_head =
-+		container_of(work, struct irq_list_head, work);
-+	struct list_head *handler_list = &irq_list_head->head;
-+	struct amdgpu_dm_irq_handler_data *handler_data;
-+
-+	list_for_each(entry, handler_list) {
-+		handler_data =
-+			list_entry(
-+				entry,
-+				struct amdgpu_dm_irq_handler_data,
-+				hcd.list);
-+
-+		DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
-+				handler_data->irq_source);
-+
-+		DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
-+			handler_data->irq_source);
-+
-+		handler_data->hcd.handler(handler_data->hcd.handler_arg);
-+	}
-+
-+	/* Call a DAL subcomponent which registered for interrupt notification
-+	 * at INTERRUPT_LOW_IRQ_CONTEXT.
-+	 * (The most common use is HPD interrupt) */
-+}
-+
-+/**
-+ * Remove a handler and return a pointer to hander list from which the
-+ * handler was removed.
-+ */
-+static struct list_head *remove_irq_handler(
-+	struct amdgpu_device *adev,
-+	void *ih,
-+	const struct dc_interrupt_params *int_params)
-+{
-+	struct list_head *hnd_list;
-+	struct list_head *entry, *tmp;
-+	struct amdgpu_dm_irq_handler_data *handler;
-+	unsigned long irq_table_flags;
-+	bool handler_removed = false;
-+	enum dc_irq_source irq_source;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	irq_source = int_params->irq_source;
-+
-+	switch (int_params->int_context) {
-+	case INTERRUPT_HIGH_IRQ_CONTEXT:
-+		hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
-+		break;
-+	case INTERRUPT_LOW_IRQ_CONTEXT:
-+	default:
-+		hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
-+		break;
-+	}
-+
-+	list_for_each_safe(entry, tmp, hnd_list) {
-+
-+		handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
-+				hcd.list);
-+
-+		if (ih == handler) {
-+			/* Found our handler. Remove it from the list. */
-+			list_del(&handler->hcd.list);
-+			handler_removed = true;
-+			break;
-+		}
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	if (handler_removed == false) {
-+		/* Not necessarily an error - caller may not
-+		 * know the context. */
-+		return NULL;
-+	}
-+
-+	kfree(handler);
-+
-+	DRM_DEBUG_KMS(
-+	"DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
-+		ih, int_params->irq_source, int_params->int_context);
-+
-+	return hnd_list;
-+}
-+
-+/* If 'handler_in == NULL' then remove ALL handlers. */
-+static void remove_timer_handler(
-+	struct amdgpu_device *adev,
-+	struct amdgpu_dm_timer_handler_data *handler_in)
-+{
-+	struct amdgpu_dm_timer_handler_data *handler_temp;
-+	struct list_head *handler_list;
-+	struct list_head *entry, *tmp;
-+	unsigned long irq_table_flags;
-+	bool handler_removed = false;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	handler_list = &adev->dm.timer_handler_list;
-+
-+	list_for_each_safe(entry, tmp, handler_list) {
-+		/* Note that list_for_each_safe() guarantees that
-+		 * handler_temp is NOT null. */
-+		handler_temp = list_entry(entry,
-+				struct amdgpu_dm_timer_handler_data, hcd.list);
-+
-+		if (handler_in == NULL || handler_in == handler_temp) {
-+			list_del(&handler_temp->hcd.list);
-+			DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+			DRM_DEBUG_KMS("DM_IRQ: removing timer handler: %p\n",
-+					handler_temp);
-+
-+			if (handler_in == NULL) {
-+				/* Since it is still in the queue, it must
-+				 * be cancelled. */
-+				cancel_delayed_work_sync(&handler_temp->d_work);
-+			}
-+
-+			kfree(handler_temp);
-+			handler_removed = true;
-+
-+			DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+		}
-+
-+		if (handler_in == NULL) {
-+			/* Remove ALL handlers. */
-+			continue;
-+		}
-+
-+		if (handler_in == handler_temp) {
-+			/* Remove a SPECIFIC handler.
-+			 * Found our handler - we can stop here. */
-+			break;
-+		}
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	if (handler_in != NULL && handler_removed == false) {
-+		DRM_ERROR("DM_IRQ: handler: %p is not in the list!\n",
-+				handler_in);
-+	}
-+}
-+
-+/**
-+ * dm_timer_work_func - Handle a timer.
-+ *
-+ * @work: work struct
-+ */
-+static void dm_timer_work_func(
-+	struct work_struct *work)
-+{
-+	struct amdgpu_dm_timer_handler_data *handler_data =
-+		container_of(work, struct amdgpu_dm_timer_handler_data,
-+				d_work.work);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: work_func: handler_data=%p\n", handler_data);
-+
-+	/* Call a DAL subcomponent which registered for timer notification. */
-+	handler_data->hcd.handler(handler_data->hcd.handler_arg);
-+
-+	/* We support only "single shot" timers. That means we must delete
-+	 * the handler after it was called. */
-+	remove_timer_handler(handler_data->hcd.dm->adev, handler_data);
-+}
-+
-+static bool validate_irq_registration_params(
-+	struct dc_interrupt_params *int_params,
-+	void (*ih)(void *))
-+{
-+	if (NULL == int_params || NULL == ih) {
-+		DRM_ERROR("DM_IRQ: invalid input!\n");
-+		return false;
-+	}
-+
-+	if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
-+		DRM_ERROR("DM_IRQ: invalid context: %d!\n",
-+				int_params->int_context);
-+		return false;
-+	}
-+
-+	if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
-+		DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
-+				int_params->irq_source);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool validate_irq_unregistration_params(
-+	enum dc_irq_source irq_source,
-+	irq_handler_idx handler_idx)
-+{
-+	if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
-+		DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
-+		return false;
-+	}
-+
-+	if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
-+		DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+/******************************************************************************
-+ * Public functions.
-+ *
-+ * Note: caller is responsible for input validation.
-+ *****************************************************************************/
-+
-+void *amdgpu_dm_irq_register_interrupt(
-+	struct amdgpu_device *adev,
-+	struct dc_interrupt_params *int_params,
-+	void (*ih)(void *),
-+	void *handler_args)
-+{
-+	struct list_head *hnd_list;
-+	struct amdgpu_dm_irq_handler_data *handler_data;
-+	unsigned long irq_table_flags;
-+	enum dc_irq_source irq_source;
-+
-+	if (false == validate_irq_registration_params(int_params, ih))
-+		return DAL_INVALID_IRQ_HANDLER_IDX;
-+
-+	handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
-+	if (!handler_data) {
-+		DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
-+		return DAL_INVALID_IRQ_HANDLER_IDX;
-+	}
-+
-+	memset(handler_data, 0, sizeof(*handler_data));
-+
-+	init_handler_common_data(&handler_data->hcd, ih, handler_args,
-+			&adev->dm);
-+
-+	irq_source = int_params->irq_source;
-+
-+	handler_data->irq_source = irq_source;
-+
-+	/* Lock the list, add the handler. */
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	switch (int_params->int_context) {
-+	case INTERRUPT_HIGH_IRQ_CONTEXT:
-+		hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
-+		break;
-+	case INTERRUPT_LOW_IRQ_CONTEXT:
-+	default:
-+		hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
-+		break;
-+	}
-+
-+	list_add_tail(&handler_data->hcd.list, hnd_list);
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	/* This pointer will be stored by code which requested interrupt
-+	 * registration.
-+	 * The same pointer will be needed in order to unregister the
-+	 * interrupt. */
-+
-+	DRM_DEBUG_KMS(
-+		"DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
-+		handler_data,
-+		irq_source,
-+		int_params->int_context);
-+
-+	return handler_data;
-+}
-+
-+void amdgpu_dm_irq_unregister_interrupt(
-+	struct amdgpu_device *adev,
-+	enum dc_irq_source irq_source,
-+	void *ih)
-+{
-+	struct list_head *handler_list;
-+	struct dc_interrupt_params int_params;
-+	int i;
-+
-+	if (false == validate_irq_unregistration_params(irq_source, ih))
-+		return;
-+
-+	memset(&int_params, 0, sizeof(int_params));
-+
-+	int_params.irq_source = irq_source;
-+
-+	for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
-+
-+		int_params.int_context = i;
-+
-+		handler_list = remove_irq_handler(adev, ih, &int_params);
-+
-+		if (handler_list != NULL)
-+			break;
-+	}
-+
-+	if (handler_list == NULL) {
-+		/* If we got here, it means we searched all irq contexts
-+		 * for this irq source, but the handler was not found. */
-+		DRM_ERROR(
-+		"DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
-+			ih, irq_source);
-+	}
-+}
-+
-+int amdgpu_dm_irq_init(
-+	struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct irq_list_head *lh;
-+
-+	DRM_DEBUG_KMS("DM_IRQ\n");
-+
-+	spin_lock_init(&adev->dm.irq_handler_list_table_lock);
-+
-+	for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
-+		/* low context handler list init */
-+		lh = &adev->dm.irq_handler_list_low_tab[src];
-+		INIT_LIST_HEAD(&lh->head);
-+		INIT_WORK(&lh->work, dm_irq_work_func);
-+
-+		/* high context handler init */
-+		INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
-+	}
-+
-+	INIT_LIST_HEAD(&adev->dm.timer_handler_list);
-+
-+	/* allocate and initialize the workqueue for DM timer */
-+	adev->dm.timer_workqueue = create_singlethread_workqueue(
-+			"dm_timer_queue");
-+	if (adev->dm.timer_workqueue == NULL) {
-+		DRM_ERROR("DM_IRQ: unable to create timer queue!\n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+void amdgpu_dm_irq_register_timer(
-+	struct amdgpu_device *adev,
-+	struct dc_timer_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *args)
-+{
-+	unsigned long jf_delay;
-+	struct list_head *handler_list;
-+	struct amdgpu_dm_timer_handler_data *handler_data;
-+	unsigned long irq_table_flags;
-+
-+	handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
-+	if (!handler_data) {
-+		DRM_ERROR("DM_IRQ: failed to allocate timer handler!\n");
-+		return;
-+	}
-+
-+	memset(handler_data, 0, sizeof(*handler_data));
-+
-+	init_handler_common_data(&handler_data->hcd, ih, args, &adev->dm);
-+
-+	INIT_DELAYED_WORK(&handler_data->d_work, dm_timer_work_func);
-+
-+	/* Lock the list, add the handler. */
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	handler_list = &adev->dm.timer_handler_list;
-+
-+	list_add_tail(&handler_data->hcd.list, handler_list);
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	jf_delay = usecs_to_jiffies(int_params->micro_sec_interval);
-+
-+	queue_delayed_work(adev->dm.timer_workqueue, &handler_data->d_work,
-+			jf_delay);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: added handler:%p with micro_sec_interval=%llu\n",
-+			handler_data, int_params->micro_sec_interval);
-+	return;
-+}
-+
-+/* DM IRQ and timer resource release */
-+void amdgpu_dm_irq_fini(
-+	struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct irq_list_head *lh;
-+	DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
-+
-+	for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
-+
-+		/* The handler was removed from the table,
-+		 * it means it is safe to flush all the 'work'
-+		 * (because no code can schedule a new one). */
-+		lh = &adev->dm.irq_handler_list_low_tab[src];
-+		flush_work(&lh->work);
-+	}
-+
-+	/* Cancel ALL timers and release handlers (if any). */
-+	remove_timer_handler(adev, NULL);
-+	/* Release the queue itself. */
-+	destroy_workqueue(adev->dm.timer_workqueue);
-+}
-+
-+int amdgpu_dm_irq_suspend(
-+	struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct list_head *hnd_list_h;
-+	struct list_head *hnd_list_l;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: suspend\n");
-+
-+	/* disable HW interrupt */
-+	for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) {
-+		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
-+		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
-+		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
-+			dc_interrupt_set(adev->dm.dc, src, false);
-+
-+		DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+		flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
-+
-+		DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	return 0;
-+}
-+
-+int amdgpu_dm_irq_resume(
-+	struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct list_head *hnd_list_h, *hnd_list_l;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: resume\n");
-+
-+	/* re-enable HW interrupt */
-+	for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) {
-+		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
-+		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
-+		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
-+			dc_interrupt_set(adev->dm.dc, src, true);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	return 0;
-+}
-+
-+
-+/**
-+ * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
-+ * "irq_source".
-+ */
-+static void amdgpu_dm_irq_schedule_work(
-+	struct amdgpu_device *adev,
-+	enum dc_irq_source irq_source)
-+{
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	/* Since the caller is interested in 'work_struct' then
-+	 * the irq will be post-processed at "INTERRUPT_LOW_IRQ_CONTEXT". */
-+
-+	schedule_work(&adev->dm.irq_handler_list_low_tab[irq_source].work);
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+}
-+
-+/** amdgpu_dm_irq_immediate_work
-+ *  Callback high irq work immediately, don't send to work queue
-+ */
-+static void amdgpu_dm_irq_immediate_work(
-+	struct amdgpu_device *adev,
-+	enum dc_irq_source irq_source)
-+{
-+	struct amdgpu_dm_irq_handler_data *handler_data;
-+	struct list_head *entry;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	list_for_each(
-+		entry,
-+		&adev->dm.irq_handler_list_high_tab[irq_source]) {
-+
-+		handler_data =
-+			list_entry(
-+				entry,
-+				struct amdgpu_dm_irq_handler_data,
-+				hcd.list);
-+
-+		/* Call a subcomponent which registered for immediate
-+		 * interrupt notification */
-+		handler_data->hcd.handler(handler_data->hcd.handler_arg);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+}
-+
-+/*
-+ * amdgpu_dm_irq_handler
-+ *
-+ * Generic IRQ handler, calls all registered high irq work immediately, and
-+ * schedules work for low irq
-+ */
-+int amdgpu_dm_irq_handler(
-+		struct amdgpu_device *adev,
-+		struct amdgpu_irq_src *source,
-+		struct amdgpu_iv_entry *entry)
-+{
-+
-+	enum dc_irq_source src =
-+		dc_interrupt_to_irq_source(
-+			adev->dm.dc,
-+			entry->src_id,
-+			entry->src_data);
-+
-+	dc_interrupt_ack(adev->dm.dc, src);
-+
-+	/* Call high irq work immediately */
-+	amdgpu_dm_irq_immediate_work(adev, src);
-+	/*Schedule low_irq work */
-+	amdgpu_dm_irq_schedule_work(adev, src);
-+
-+	return 0;
-+}
-+
-+static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
-+{
-+	switch (type) {
-+	case AMDGPU_HPD_1:
-+		return DC_IRQ_SOURCE_HPD1;
-+	case AMDGPU_HPD_2:
-+		return DC_IRQ_SOURCE_HPD2;
-+	case AMDGPU_HPD_3:
-+		return DC_IRQ_SOURCE_HPD3;
-+	case AMDGPU_HPD_4:
-+		return DC_IRQ_SOURCE_HPD4;
-+	case AMDGPU_HPD_5:
-+		return DC_IRQ_SOURCE_HPD5;
-+	case AMDGPU_HPD_6:
-+		return DC_IRQ_SOURCE_HPD6;
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
-+					struct amdgpu_irq_src *source,
-+					unsigned type,
-+					enum amdgpu_interrupt_state state)
-+{
-+	enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
-+	bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
-+
-+	dc_interrupt_set(adev->dm.dc, src, st);
-+	return 0;
-+}
-+
-+static inline int dm_irq_state(
-+	struct amdgpu_device *adev,
-+	struct amdgpu_irq_src *source,
-+	unsigned crtc_id,
-+	enum amdgpu_interrupt_state state,
-+	const enum irq_type dal_irq_type,
-+	const char *func)
-+{
-+	bool st;
-+	enum dc_irq_source irq_source;
-+
-+	struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
-+
-+	if (!acrtc->target) {
-+		DRM_INFO(
-+			"%s: target is null for crtc %d, talk to David R\n",
-+			func,
-+			crtc_id);
-+		WARN_ON(true);
-+		return 0;
-+	}
-+
-+	irq_source = dc_target_get_irq_src(acrtc->target, dal_irq_type);
-+
-+	st = (state == AMDGPU_IRQ_STATE_ENABLE);
-+
-+	dc_interrupt_set(adev->dm.dc, irq_source, st);
-+	return 0;
-+}
-+
-+static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
-+					struct amdgpu_irq_src *source,
-+					unsigned crtc_id,
-+					enum amdgpu_interrupt_state state)
-+{
-+	return dm_irq_state(
-+		adev,
-+		source,
-+		crtc_id,
-+		state,
-+		IRQ_TYPE_PFLIP,
-+		__func__);
-+}
-+
-+static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
-+					struct amdgpu_irq_src *source,
-+					unsigned crtc_id,
-+					enum amdgpu_interrupt_state state)
-+{
-+	return dm_irq_state(
-+		adev,
-+		source,
-+		crtc_id,
-+		state,
-+		IRQ_TYPE_VUPDATE,
-+		__func__);
-+}
-+
-+static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
-+	.set = amdgpu_dm_set_crtc_irq_state,
-+	.process = amdgpu_dm_irq_handler,
-+};
-+
-+static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
-+	.set = amdgpu_dm_set_pflip_irq_state,
-+	.process = amdgpu_dm_irq_handler,
-+};
-+
-+static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
-+	.set = amdgpu_dm_set_hpd_irq_state,
-+	.process = amdgpu_dm_irq_handler,
-+};
-+
-+void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
-+{
-+	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
-+	adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
-+
-+	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
-+	adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
-+
-+	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
-+	adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
-+}
-+
-+/*
-+ * amdgpu_dm_hpd_init - hpd setup callback.
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Setup the hpd pins used by the card (evergreen+).
-+ * Enable the pin, set the polarity, and enable the hpd interrupts.
-+ */
-+void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_connector *connector;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		struct amdgpu_connector *amdgpu_connector =
-+				to_amdgpu_connector(connector);
-+		enum dc_irq_source src =
-+			amdgpu_dm_hpd_to_dal_irq_source(
-+				amdgpu_connector->hpd.hpd);
-+		const struct dc_link *dc_link = amdgpu_connector->dc_link;
-+
-+		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
-+			connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
-+			/* don't try to enable hpd on eDP or LVDS avoid breaking
-+			 * the aux dp channel on imac and help (but not
-+			 * completely fix)
-+			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
-+			 * also avoid interrupt storms during dpms.
-+			 */
-+			continue;
-+		}
-+
-+		dc_interrupt_set(adev->dm.dc, src, true);
-+		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
-+			dc_interrupt_set(adev->dm.dc,
-+					dc_link->irq_source_hpd_rx,
-+					true);
-+		}
-+	}
-+}
-+
-+/**
-+ * amdgpu_dm_hpd_fini - hpd tear down callback.
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Tear down the hpd pins used by the card (evergreen+).
-+ * Disable the hpd interrupts.
-+ */
-+void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_connector *connector;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		struct amdgpu_connector *amdgpu_connector =
-+				to_amdgpu_connector(connector);
-+		enum dc_irq_source src =
-+			amdgpu_dm_hpd_to_dal_irq_source(
-+				amdgpu_connector->hpd.hpd);
-+
-+		dc_interrupt_set(adev->dm.dc, src, false);
-+		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-new file mode 100644
-index 0000000..afedb50
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-@@ -0,0 +1,122 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef __AMDGPU_DM_IRQ_H__
-+#define __AMDGPU_DM_IRQ_H__
-+
-+#include "irq_types.h" /* DAL irq definitions */
-+
-+/*
-+ * Display Manager IRQ-related interfaces (for use by DAL).
-+ */
-+
-+/**
-+ * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
-+ *
-+ * This function should be called exactly once - during DM initialization.
-+ *
-+ * Returns:
-+ *	0 - success
-+ *	non-zero - error
-+ */
-+int amdgpu_dm_irq_init(
-+	struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
-+ *
-+ * This function should be called exactly once - during DM destruction.
-+ *
-+ */
-+void amdgpu_dm_irq_fini(
-+	struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
-+ *
-+ * @adev: AMD DRM device
-+ * @int_params: parameters for the irq
-+ * @ih: pointer to the irq hander function
-+ * @handler_args: arguments which will be passed to ih
-+ *
-+ * Returns:
-+ * 	IRQ Handler Index on success.
-+ * 	NULL on failure.
-+ *
-+ * Cannot be called from an interrupt handler.
-+ */
-+void *amdgpu_dm_irq_register_interrupt(
-+		struct amdgpu_device *adev,
-+		struct dc_interrupt_params *int_params,
-+		void (*ih)(void *),
-+		void *handler_args);
-+
-+/**
-+ * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
-+ *	by amdgpu_dm_irq_register_interrupt().
-+ *
-+ * @adev: AMD DRM device.
-+ * @ih_index: irq handler index which was returned by
-+ *	amdgpu_dm_irq_register_interrupt
-+ */
-+void amdgpu_dm_irq_unregister_interrupt(
-+		struct amdgpu_device *adev,
-+		enum dc_irq_source irq_source,
-+		void *ih_index);
-+
-+void amdgpu_dm_irq_register_timer(
-+	struct amdgpu_device *adev,
-+	struct dc_timer_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *args);
-+
-+/**
-+ * amdgpu_dm_irq_handler
-+ * Generic IRQ handler, calls all registered high irq work immediately, and
-+ * schedules work for low irq
-+ */
-+int amdgpu_dm_irq_handler(
-+		struct amdgpu_device *adev,
-+		struct amdgpu_irq_src *source,
-+		struct amdgpu_iv_entry *entry);
-+
-+void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
-+
-+void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
-+void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
-+ *
-+ */
-+int amdgpu_dm_irq_suspend(
-+	struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
-+ *
-+ */
-+int amdgpu_dm_irq_resume(
-+	struct amdgpu_device *adev);
-+
-+#endif /* __AMDGPU_DM_IRQ_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-new file mode 100644
-index 0000000..6d9ee15
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -0,0 +1,353 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "amdgpu.h"
-+
-+#include "amdgpu_dm_types.h"
-+
-+#include "amdgpu_dm_mst_types.h"
-+
-+#include "dc.h"
-+
-+static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
-+{
-+	struct pci_dev *pdev = to_pci_dev(aux->dev);
-+	struct drm_device *drm_dev = pci_get_drvdata(pdev);
-+	struct amdgpu_device *adev = drm_dev->dev_private;
-+	struct dc *dc = adev->dm.dc;
-+
-+	switch (msg->request) {
-+	case DP_AUX_NATIVE_READ:
-+		dc_read_dpcd(
-+			dc,
-+			TO_DM_AUX(aux)->link_index,
-+			msg->address,
-+			msg->buffer,
-+			msg->size);
-+		break;
-+	case DP_AUX_NATIVE_WRITE:
-+		dc_write_dpcd(
-+			dc,
-+			TO_DM_AUX(aux)->link_index,
-+			msg->address,
-+			msg->buffer,
-+			msg->size);
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	return msg->size;
-+}
-+
-+static enum drm_connector_status
-+dm_dp_mst_detect(struct drm_connector *connector, bool force)
-+{
-+	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
-+	struct amdgpu_connector *master = aconnector->mst_port;
-+
-+	return drm_dp_mst_detect_port(connector, &master->mst_mgr, aconnector->port);
-+}
-+
-+static void
-+dm_dp_mst_connector_destroy(struct drm_connector *connector)
-+{
-+	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
-+	struct amdgpu_encoder *amdgpu_encoder = amdgpu_connector->mst_encoder;
-+
-+	drm_encoder_cleanup(&amdgpu_encoder->base);
-+	kfree(amdgpu_encoder);
-+	drm_connector_cleanup(connector);
-+	kfree(amdgpu_connector);
-+}
-+
-+static int dm_dp_mst_connector_dpms(struct drm_connector *connector, int mode)
-+{
-+	DRM_DEBUG_KMS("\n");
-+	return 0;
-+}
-+
-+static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
-+	.dpms = dm_dp_mst_connector_dpms,
-+	.detect = dm_dp_mst_detect,
-+	.fill_modes = drm_helper_probe_single_connector_modes,
-+	.destroy = dm_dp_mst_connector_destroy,
-+	.reset = amdgpu_dm_connector_funcs_reset,
-+	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
-+	.atomic_destroy_state = amdgpu_dm_connector_atomic_destroy_state,
-+	.atomic_set_property = amdgpu_dm_connector_atomic_set_property
-+};
-+
-+static const struct dc_sink *dm_dp_mst_add_mst_sink(
-+		struct dc_link *dc_link,
-+		uint8_t *edid,
-+		uint16_t len)
-+{
-+	struct dc_sink *dc_sink;
-+	struct sink_init_data init_params = {
-+			.link = dc_link,
-+			.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST};
-+
-+	if (len > MAX_EDID_BUFFER_SIZE) {
-+		DRM_ERROR("Max EDID buffer size breached!\n");
-+		return NULL;
-+	}
-+
-+	/*
-+	 * TODO make dynamic-ish?
-+	 * dc_link->connector_signal;
-+	 */
-+
-+	dc_sink = sink_create(&init_params);
-+
-+	if (!dc_sink)
-+		return NULL;
-+
-+	dc_service_memmove(dc_sink->dc_edid.raw_edid, edid, len);
-+	dc_sink->dc_edid.length = len;
-+
-+	if (!dc_link_add_sink(
-+			dc_link,
-+			dc_sink))
-+		goto fail;
-+
-+	/* dc_sink_retain(&core_sink->public); */
-+
-+	return dc_sink;
-+
-+fail:
-+	dc_link_remove_sink(dc_link, dc_sink);
-+	return NULL;
-+}
-+
-+static int dm_dp_mst_get_modes(struct drm_connector *connector)
-+{
-+	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
-+	struct amdgpu_connector *master = aconnector->mst_port;
-+	struct edid *edid;
-+	const struct dc_sink *sink;
-+	int ret = 0;
-+
-+	edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, aconnector->port);
-+
-+	if (!edid) {
-+		drm_mode_connector_update_edid_property(
-+			&aconnector->base,
-+			NULL);
-+
-+		return ret;
-+	}
-+
-+	aconnector->edid = edid;
-+
-+	if (!aconnector->dc_sink) {
-+			sink = dm_dp_mst_add_mst_sink(
-+			(struct dc_link *)aconnector->dc_link,
-+			(uint8_t *)edid,
-+			(edid->extensions + 1) * EDID_LENGTH);
-+			aconnector->dc_sink = sink;
-+	}
-+
-+	DRM_DEBUG_KMS("edid retrieved %p\n", edid);
-+
-+	drm_mode_connector_update_edid_property(
-+		&aconnector->base,
-+		aconnector->edid);
-+
-+	ret = drm_add_edid_modes(&aconnector->base, aconnector->edid);
-+
-+	drm_edid_to_eld(&aconnector->base, aconnector->edid);
-+
-+	return ret;
-+}
-+
-+static enum drm_mode_status
-+dm_dp_mst_mode_valid(struct drm_connector *connector,
-+			struct drm_display_mode *mode)
-+{
-+	return MODE_OK;
-+}
-+
-+static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector)
-+{
-+	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
-+
-+	return &amdgpu_connector->mst_encoder->base;
-+}
-+
-+static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
-+	.get_modes = dm_dp_mst_get_modes,
-+	.mode_valid = dm_dp_mst_mode_valid,
-+	.best_encoder = dm_mst_best_encoder,
-+};
-+
-+static struct amdgpu_encoder *
-+dm_dp_create_fake_mst_encoder(struct amdgpu_connector *connector)
-+{
-+	struct drm_device *dev = connector->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_encoder *amdgpu_encoder;
-+	struct drm_encoder *encoder;
-+	const struct drm_connector_helper_funcs *connector_funcs =
-+		connector->base.helper_private;
-+	struct drm_encoder *enc_master =
-+		connector_funcs->best_encoder(&connector->base);
-+
-+	DRM_DEBUG_KMS("enc master is %p\n", enc_master);
-+	amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
-+	if (!amdgpu_encoder)
-+		return NULL;
-+
-+	encoder = &amdgpu_encoder->base;
-+	switch (adev->mode_info.num_crtc) {
-+	case 1:
-+		encoder->possible_crtcs = 0x1;
-+		break;
-+	case 2:
-+	default:
-+		encoder->possible_crtcs = 0x3;
-+		break;
-+	case 4:
-+		encoder->possible_crtcs = 0xf;
-+		break;
-+	case 6:
-+		encoder->possible_crtcs = 0x3f;
-+		break;
-+	}
-+
-+	encoder->possible_crtcs = 0x1;
-+
-+	drm_encoder_init(
-+		dev,
-+		&amdgpu_encoder->base,
-+		NULL,
-+		DRM_MODE_ENCODER_DPMST,
-+		NULL);
-+
-+	drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
-+
-+	return amdgpu_encoder;
-+}
-+
-+static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
-+							 struct drm_dp_mst_port *port,
-+							 const char *pathprop)
-+{
-+	struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr);
-+	struct drm_device *dev = master->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector *connector;
-+
-+	aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
-+	if (!aconnector)
-+		return NULL;
-+
-+	aconnector->is_mst_connector = true;
-+	connector = &aconnector->base;
-+	aconnector->port = port;
-+	aconnector->mst_port = master;
-+	aconnector->dc_link = master->dc_link;
-+
-+	/* Initialize connector state before adding the connectror to drm and framebuffer lists */
-+	amdgpu_dm_connector_funcs_reset(connector);
-+
-+	drm_connector_init(dev, connector, &dm_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
-+	drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
-+	aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
-+
-+	drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
-+	drm_mode_connector_set_path_property(connector, pathprop);
-+
-+	mutex_lock(&dev->mode_config.mutex);
-+	drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
-+	mutex_unlock(&dev->mode_config.mutex);
-+
-+	drm_connector_register(connector);
-+
-+	DRM_DEBUG_KMS(":%d\n", connector->base.id);
-+
-+	return connector;
-+}
-+
-+static void dm_dp_destroy_mst_connector(
-+	struct drm_dp_mst_topology_mgr *mgr,
-+	struct drm_connector *connector)
-+{
-+	struct amdgpu_connector *master =
-+		container_of(mgr, struct amdgpu_connector, mst_mgr);
-+	struct drm_device *dev = master->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	drm_connector_unregister(connector);
-+	/* need to nuke the connector */
-+	mutex_lock(&dev->mode_config.mutex);
-+	/* dpms off */
-+	drm_fb_helper_remove_one_connector(
-+		&adev->mode_info.rfbdev->helper,
-+		connector);
-+
-+	drm_connector_cleanup(connector);
-+	mutex_unlock(&dev->mode_config.mutex);
-+
-+	kfree(connector);
-+	DRM_DEBUG_KMS("\n");
-+}
-+
-+static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-+{
-+	struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr);
-+	struct drm_device *dev = master->base.dev;
-+
-+	drm_kms_helper_hotplug_event(dev);
-+}
-+
-+struct drm_dp_mst_topology_cbs dm_mst_cbs = {
-+	.add_connector = dm_dp_add_mst_connector,
-+	.destroy_connector = dm_dp_destroy_mst_connector,
-+	.hotplug = dm_dp_mst_hotplug,
-+};
-+
-+void amdgpu_dm_initialize_mst_connector(
-+	struct amdgpu_display_manager *dm,
-+	struct amdgpu_connector *aconnector)
-+{
-+	aconnector->dm_dp_aux.aux.name = "dmdc";
-+	aconnector->dm_dp_aux.aux.dev = dm->adev->dev;
-+	aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
-+	aconnector->dm_dp_aux.link_index = aconnector->connector_id;
-+
-+	drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
-+
-+	aconnector->mst_mgr.cbs = &dm_mst_cbs;
-+	drm_dp_mst_topology_mgr_init(
-+		&aconnector->mst_mgr,
-+		dm->adev->dev,
-+		&aconnector->dm_dp_aux.aux,
-+		16,
-+		4,
-+		aconnector->connector_id);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h
-new file mode 100644
-index 0000000..6130d62
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AMDGPU_DM_MST_TYPES_H__
-+#define __DAL_AMDGPU_DM_MST_TYPES_H__
-+
-+struct amdgpu_display_manager;
-+struct amdgpu_connector;
-+
-+void amdgpu_dm_initialize_mst_connector(
-+	struct amdgpu_display_manager *dm,
-+	struct amdgpu_connector *aconnector);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-new file mode 100644
-index 0000000..bfff48c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -0,0 +1,2390 @@
-+/*
-+ * Copyright 2012-13 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services_types.h"
-+
-+#include <linux/types.h>
-+#include <drm/drmP.h>
-+#include <drm/drm_atomic_helper.h>
-+#include <drm/drm_fb_helper.h>
-+#include <drm/drm_atomic.h>
-+#include "amdgpu.h"
-+#include "amdgpu_pm.h"
-+// We need to #undef FRAME_SIZE and DEPRECATED because they conflict
-+// with ptrace-abi.h's #define's of them.
-+#undef FRAME_SIZE
-+#undef DEPRECATED
-+
-+#include "mode_query_interface.h"
-+#include "dcs_types.h"
-+#include "mode_manager_types.h"
-+
-+/*#include "amdgpu_buffer.h"*/
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+#include "dc.h"
-+
-+#include "amdgpu_dm_types.h"
-+#include "amdgpu_dm_mst_types.h"
-+
-+struct dm_connector_state {
-+	struct drm_connector_state base;
-+
-+	enum amdgpu_rmx_type scaling;
-+	uint8_t underscan_vborder;
-+	uint8_t underscan_hborder;
-+	bool underscan_enable;
-+};
-+
-+#define to_dm_connector_state(x)\
-+	container_of((x), struct dm_connector_state, base)
-+
-+#define AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET 1
-+
-+void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
-+{
-+	drm_encoder_cleanup(encoder);
-+	kfree(encoder);
-+}
-+
-+static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
-+	.destroy = amdgpu_dm_encoder_destroy,
-+};
-+
-+static void dm_set_cursor(
-+	struct amdgpu_crtc *amdgpu_crtc,
-+	uint64_t gpu_addr,
-+	uint32_t width,
-+	uint32_t height)
-+{
-+	struct dc_cursor_attributes attributes;
-+	amdgpu_crtc->cursor_width = width;
-+	amdgpu_crtc->cursor_height = height;
-+
-+	attributes.address.high_part = upper_32_bits(gpu_addr);
-+	attributes.address.low_part  = lower_32_bits(gpu_addr);
-+	attributes.width             = width-1;
-+	attributes.height            = height-1;
-+	attributes.x_hot             = 0;
-+	attributes.y_hot             = 0;
-+	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
-+	attributes.rotation_angle    = 0;
-+	attributes.attribute_flags.value = 0;
-+
-+	if (!dc_target_set_cursor_attributes(
-+				amdgpu_crtc->target,
-+				&attributes)) {
-+		DRM_ERROR("DC failed to set cursor attributes\n");
-+	}
-+}
-+
-+static int dm_crtc_unpin_cursor_bo_old(
-+	struct amdgpu_crtc *amdgpu_crtc)
-+{
-+	struct amdgpu_bo *robj;
-+	int ret = 0;
-+
-+	if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
-+		robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
-+
-+		ret  = amdgpu_bo_reserve(robj, false);
-+
-+		if (likely(ret == 0)) {
-+			amdgpu_bo_unpin(robj);
-+			amdgpu_bo_unreserve(robj);
-+		}
-+	} else {
-+		DRM_ERROR("dm_crtc_unpin_cursor_ob_old bo %x, leaked %p\n",
-+				ret,
-+				amdgpu_crtc->cursor_bo);
-+	}
-+
-+	drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
-+	amdgpu_crtc->cursor_bo = NULL;
-+
-+	return ret;
-+}
-+
-+static int dm_crtc_pin_cursor_bo_new(
-+	struct drm_crtc *crtc,
-+	struct drm_file *file_priv,
-+	uint32_t handle,
-+	struct amdgpu_bo **ret_obj,
-+	uint64_t *gpu_addr)
-+{
-+	struct amdgpu_crtc *amdgpu_crtc;
-+	struct amdgpu_bo *robj;
-+	struct drm_gem_object *obj;
-+	int ret = EINVAL;
-+
-+	if (NULL != crtc) {
-+		amdgpu_crtc = to_amdgpu_crtc(crtc);
-+
-+		obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
-+
-+		if (!obj) {
-+			DRM_ERROR(
-+				"Cannot find cursor object %x for crtc %d\n",
-+				handle,
-+				amdgpu_crtc->crtc_id);
-+			goto release;
-+		}
-+		robj = gem_to_amdgpu_bo(obj);
-+
-+		ret  = amdgpu_bo_reserve(robj, false);
-+
-+		if (unlikely(ret != 0)) {
-+			drm_gem_object_unreference_unlocked(obj);
-+		DRM_ERROR("dm_crtc_pin_cursor_bo_new ret %x, handle %x\n",
-+				 ret, handle);
-+			goto release;
-+		}
-+
-+		ret = amdgpu_bo_pin(robj, AMDGPU_GEM_DOMAIN_VRAM, NULL);
-+
-+		if (ret == 0) {
-+			*gpu_addr = amdgpu_bo_gpu_offset(robj);
-+			*ret_obj  = robj;
-+		}
-+		amdgpu_bo_unreserve(robj);
-+		if (ret)
-+			drm_gem_object_unreference_unlocked(obj);
-+
-+	}
-+release:
-+
-+	return ret;
-+}
-+
-+static int dm_crtc_cursor_set(
-+	struct drm_crtc *crtc,
-+	struct drm_file *file_priv,
-+	uint32_t handle,
-+	uint32_t width,
-+	uint32_t height)
-+{
-+	struct amdgpu_bo *new_cursor_bo;
-+	uint64_t gpu_addr;
-+	struct dc_cursor_position position;
-+
-+	int ret;
-+
-+	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-+
-+	ret		= EINVAL;
-+	new_cursor_bo	= NULL;
-+	gpu_addr	= 0;
-+
-+	DRM_DEBUG_KMS(
-+	"%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
-+		__func__,
-+		amdgpu_crtc->crtc_id,
-+		handle,
-+		width,
-+		height,
-+		amdgpu_crtc->cursor_bo);
-+
-+	if (!handle) {
-+		/* turn off cursor */
-+		position.enable = false;
-+		position.x = 0;
-+		position.y = 0;
-+		position.hot_spot_enable = false;
-+
-+		if (amdgpu_crtc->target) {
-+			/*set cursor visible false*/
-+			dc_target_set_cursor_position(
-+				amdgpu_crtc->target,
-+				&position);
-+		}
-+		/*unpin old cursor buffer and update cache*/
-+		ret = dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
-+		goto release;
-+
-+	}
-+
-+	if ((width > amdgpu_crtc->max_cursor_width) ||
-+		(height > amdgpu_crtc->max_cursor_height)) {
-+		DRM_ERROR(
-+			"%s: bad cursor width or height %d x %d\n",
-+			__func__,
-+			width,
-+			height);
-+		goto release;
-+	}
-+	/*try to pin new cursor bo*/
-+	ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle,
-+			&new_cursor_bo, &gpu_addr);
-+	/*if map not successful then return an error*/
-+	if (ret)
-+		goto release;
-+
-+	/*program new cursor bo to hardware*/
-+	dm_set_cursor(amdgpu_crtc, gpu_addr, width, height);
-+
-+	/*un map old, not used anymore cursor bo ,
-+	 * return memory and mapping back */
-+	dm_crtc_unpin_cursor_bo_old(amdgpu_crtc);
-+
-+	/*assign new cursor bo to our internal cache*/
-+	amdgpu_crtc->cursor_bo = &new_cursor_bo->gem_base;
-+
-+release:
-+	return ret;
-+
-+}
-+
-+static int dm_crtc_cursor_move(struct drm_crtc *crtc,
-+				     int x, int y)
-+{
-+	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-+	int xorigin = 0, yorigin = 0;
-+	struct dc_cursor_position position;
-+
-+	/* avivo cursor are offset into the total surface */
-+	x += crtc->primary->state->src_x >> 16;
-+	y += crtc->primary->state->src_y >> 16;
-+
-+	/*
-+	 * TODO: for cursor debugging unguard the following
-+	 */
-+#if 0
-+	DRM_DEBUG_KMS(
-+		"%s: x %d y %d c->x %d c->y %d\n",
-+		__func__,
-+		x,
-+		y,
-+		crtc->x,
-+		crtc->y);
-+#endif
-+
-+	if (x < 0) {
-+		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
-+		x = 0;
-+	}
-+	if (y < 0) {
-+		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
-+		y = 0;
-+	}
-+
-+	position.enable = true;
-+	position.x = x;
-+	position.y = y;
-+
-+	position.hot_spot_enable = true;
-+	position.x_origin = xorigin;
-+	position.y_origin = yorigin;
-+
-+	if (!dc_target_set_cursor_position(
-+				amdgpu_crtc->target,
-+				&position)) {
-+		DRM_ERROR("DC failed to set cursor position\n");
-+		return -EINVAL;
-+	}
-+
-+#if BUILD_FEATURE_TIMING_SYNC
-+	{
-+		struct drm_device *dev = crtc->dev;
-+		struct amdgpu_device *adev = dev->dev_private;
-+		struct amdgpu_display_manager *dm = &adev->dm;
-+
-+		dc_print_sync_report(dm->dc);
-+	}
-+#endif
-+	return 0;
-+}
-+
-+static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
-+{
-+	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-+
-+	DRM_DEBUG_KMS(
-+		"%s: with cursor_bo %p\n",
-+		__func__,
-+		amdgpu_crtc->cursor_bo);
-+
-+	if (amdgpu_crtc->cursor_bo && amdgpu_crtc->target) {
-+		dm_set_cursor(
-+		amdgpu_crtc,
-+		amdgpu_bo_gpu_offset(gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo)),
-+		amdgpu_crtc->cursor_width,
-+		amdgpu_crtc->cursor_height);
-+	}
-+}
-+static bool fill_rects_from_plane_state(
-+	struct drm_plane_state *state,
-+	struct dc_surface *surface)
-+{
-+	surface->src_rect.x = state->src_x >> 16;
-+	surface->src_rect.y = state->src_y >> 16;
-+	/*we ignore for now mantissa and do not to deal with floating pixels :(*/
-+	surface->src_rect.width = state->src_w >> 16;
-+
-+	if (surface->src_rect.width == 0)
-+		return false;
-+
-+	surface->src_rect.height = state->src_h >> 16;
-+	if (surface->src_rect.height == 0)
-+		return false;
-+
-+	surface->dst_rect.x = state->crtc_x;
-+	surface->dst_rect.y = state->crtc_y;
-+
-+	if (state->crtc_w == 0)
-+		return false;
-+
-+	surface->dst_rect.width = state->crtc_w;
-+
-+	if (state->crtc_h == 0)
-+		return false;
-+
-+	surface->dst_rect.height = state->crtc_h;
-+
-+	surface->clip_rect = surface->dst_rect;
-+
-+	switch (state->rotation) {
-+	case DRM_ROTATE_0:
-+		surface->rotation = ROTATION_ANGLE_0;
-+		break;
-+	case DRM_ROTATE_90:
-+		surface->rotation = ROTATION_ANGLE_90;
-+		break;
-+	case DRM_ROTATE_180:
-+		surface->rotation = ROTATION_ANGLE_180;
-+		break;
-+	case DRM_ROTATE_270:
-+		surface->rotation = ROTATION_ANGLE_270;
-+		break;
-+	default:
-+		surface->rotation = ROTATION_ANGLE_0;
-+		break;
-+	}
-+
-+	return true;
-+}
-+static bool get_fb_info(
-+	struct amdgpu_framebuffer *amdgpu_fb,
-+	uint64_t *tiling_flags,
-+	uint64_t *fb_location)
-+{
-+	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
-+	int r = amdgpu_bo_reserve(rbo, false);
-+	if (unlikely(r != 0)){
-+		DRM_ERROR("Unable to reserve buffer\n");
-+		return false;
-+	}
-+
-+
-+	if (fb_location)
-+		*fb_location = amdgpu_bo_gpu_offset(rbo);
-+
-+	if (tiling_flags)
-+		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
-+
-+	amdgpu_bo_unreserve(rbo);
-+
-+	return true;
-+}
-+static void fill_plane_attributes_from_fb(
-+	struct dc_surface *surface,
-+	struct amdgpu_framebuffer *amdgpu_fb)
-+{
-+	uint64_t tiling_flags;
-+	uint64_t fb_location;
-+	struct drm_framebuffer *fb = &amdgpu_fb->base;
-+
-+	get_fb_info(
-+		amdgpu_fb,
-+		&tiling_flags,
-+		&fb_location);
-+
-+	surface->address.type                = PLN_ADDR_TYPE_GRAPHICS;
-+	surface->address.grph.addr.low_part  = lower_32_bits(fb_location);
-+	surface->address.grph.addr.high_part = upper_32_bits(fb_location);
-+
-+	switch (fb->pixel_format) {
-+	case DRM_FORMAT_C8:
-+		surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
-+		break;
-+	case DRM_FORMAT_RGB565:
-+		surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
-+		break;
-+	case DRM_FORMAT_XRGB8888:
-+	case DRM_FORMAT_ARGB8888:
-+		surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
-+		break;
-+	default:
-+		DRM_ERROR("Unsupported screen depth %d\n", fb->bits_per_pixel);
-+		return;
-+	}
-+
-+	surface->tiling_info.value = 0;
-+
-+	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1)
-+	{
-+		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
-+
-+		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
-+		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
-+		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
-+		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
-+		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
-+
-+
-+		/* XXX fix me for VI */
-+		surface->tiling_info.grph.NUM_BANKS = num_banks;
-+		surface->tiling_info.grph.ARRAY_MODE =
-+						ARRAY_2D_TILED_THIN1;
-+		surface->tiling_info.grph.TILE_SPLIT = tile_split;
-+		surface->tiling_info.grph.BANK_WIDTH = bankw;
-+		surface->tiling_info.grph.BANK_HEIGHT = bankh;
-+		surface->tiling_info.grph.TILE_ASPECT = mtaspect;
-+		surface->tiling_info.grph.TILE_MODE =
-+				ADDR_SURF_MICRO_TILING_DISPLAY;
-+	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
-+			== ARRAY_1D_TILED_THIN1) {
-+		surface->tiling_info.grph.ARRAY_MODE = ARRAY_1D_TILED_THIN1;
-+	}
-+
-+	surface->tiling_info.grph.PIPE_CONFIG =
-+			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
-+
-+	surface->plane_size.grph.surface_size.x = 0;
-+	surface->plane_size.grph.surface_size.y = 0;
-+	surface->plane_size.grph.surface_size.width = fb->width;
-+	surface->plane_size.grph.surface_size.height = fb->height;
-+	surface->plane_size.grph.surface_pitch =
-+		fb->pitches[0] / (fb->bits_per_pixel / 8);
-+
-+	surface->enabled = true;
-+	surface->scaling_quality.h_taps_c = 2;
-+	surface->scaling_quality.v_taps_c = 2;
-+
-+/* TODO: unhardcode */
-+	surface->colorimetry.limited_range = false;
-+	surface->colorimetry.color_space = SURFACE_COLOR_SPACE_SRGB;
-+	surface->scaling_quality.h_taps = 4;
-+	surface->scaling_quality.v_taps = 4;
-+	surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
-+
-+}
-+
-+static void fill_gamma_from_crtc(
-+	struct drm_crtc *crtc,
-+	struct dc_surface *dc_surface)
-+{
-+	int i;
-+	struct gamma_ramp *gamma;
-+	uint16_t *red, *green, *blue;
-+	int end = (crtc->gamma_size > NUM_OF_RAW_GAMMA_RAMP_RGB_256) ?
-+			NUM_OF_RAW_GAMMA_RAMP_RGB_256 : crtc->gamma_size;
-+
-+	red = crtc->gamma_store;
-+	green = red + crtc->gamma_size;
-+	blue = green + crtc->gamma_size;
-+
-+	gamma = &dc_surface->gamma_correction;
-+
-+	for (i = 0; i < end; i++) {
-+		gamma->gamma_ramp_rgb256x3x16.red[i] =
-+				(unsigned short) red[i];
-+		gamma->gamma_ramp_rgb256x3x16.green[i] =
-+				(unsigned short) green[i];
-+		gamma->gamma_ramp_rgb256x3x16.blue[i] =
-+				(unsigned short) blue[i];
-+	}
-+
-+	gamma->type = GAMMA_RAMP_RBG256X3X16;
-+	gamma->size = sizeof(gamma->gamma_ramp_rgb256x3x16);
-+}
-+
-+static void fill_plane_attributes(
-+	struct dc_surface *surface,
-+	struct drm_crtc *crtc)
-+{
-+	struct amdgpu_framebuffer *amdgpu_fb =
-+		to_amdgpu_framebuffer(crtc->primary->state->fb);
-+	fill_rects_from_plane_state(crtc->primary->state, surface);
-+	fill_plane_attributes_from_fb(
-+		surface,
-+		amdgpu_fb);
-+
-+	/* In case of gamma set, update gamma value */
-+	if (crtc->mode.private_flags &
-+			AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
-+		fill_gamma_from_crtc(crtc, surface);
-+		/* reset trigger of gamma */
-+		crtc->mode.private_flags &=
-+			~AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
-+	}
-+}
-+
-+/*****************************************************************************/
-+
-+struct amdgpu_connector *aconnector_from_drm_crtc(
-+		struct drm_crtc *crtc,
-+		struct drm_atomic_state *state)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector_state *conn_state;
-+	uint8_t i;
-+
-+	for_each_connector_in_state(state, connector, conn_state, i) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (connector->state->crtc == crtc)
-+				return aconnector;
-+	}
-+
-+	/* If we get here, not found. */
-+	return NULL;
-+}
-+
-+struct amdgpu_connector *aconnector_from_drm_crtc_id(
-+		const struct drm_crtc *crtc)
-+{
-+	struct drm_device *dev = crtc->dev;
-+	struct drm_connector *connector;
-+	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+	struct amdgpu_connector *aconnector;
-+
-+	list_for_each_entry(connector,
-+			&dev->mode_config.connector_list, head)	{
-+
-+		aconnector = to_amdgpu_connector(connector);
-+
-+		/* acrtc->crtc_id means display_index */
-+		if (aconnector->connector_id != acrtc->crtc_id)
-+			continue;
-+
-+		/* Found the connector */
-+		return aconnector;
-+	}
-+
-+	/* If we get here, not found. */
-+	return NULL;
-+}
-+
-+static void dm_dc_surface_commit(
-+		struct dc *dc,
-+		struct drm_crtc *crtc,
-+		struct amdgpu_framebuffer *afb)
-+{
-+	struct dc_surface *dc_surface;
-+	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+	struct dc_target *dc_target = acrtc->target;
-+
-+	if (!dc_target) {
-+		dal_error(
-+			"%s: Failed to obtain target on crtc (%d)!\n",
-+			__func__,
-+			acrtc->crtc_id);
-+		goto fail;
-+	}
-+
-+	dc_surface = dc_create_surface(dc);
-+
-+	if (!dc_surface) {
-+		dal_error(
-+			"%s: Failed to create a surface!\n",
-+			__func__);
-+		goto fail;
-+	}
-+
-+	/* Surface programming */
-+
-+	fill_plane_attributes(dc_surface, crtc);
-+
-+	if (false == dc_commit_surfaces_to_target(
-+			dc,
-+			&dc_surface,
-+			1,
-+			dc_target)) {
-+		dal_error(
-+			"%s: Failed to attach surface!\n",
-+			__func__);
-+	}
-+
-+	dc_surface_release(dc_surface);
-+fail:
-+	return;
-+}
-+
-+static enum dc_color_depth convert_color_depth_from_display_info(
-+		const struct drm_connector *connector)
-+{
-+	uint32_t bpc = connector->display_info.bpc;
-+
-+	/* Limited color depth to 8bit
-+	 * TODO: Still need to handle deep color*/
-+	if (bpc > 8)
-+		bpc = 8;
-+
-+	switch (bpc) {
-+	case 0:
-+		/* Temporary Work around, DRM don't parse color depth for
-+		 * EDID revision before 1.4
-+		 * TODO: Fix edid parsing
-+		 */
-+		return COLOR_DEPTH_888;
-+	case 6:
-+		return COLOR_DEPTH_666;
-+	case 8:
-+		return COLOR_DEPTH_888;
-+	case 10:
-+		return COLOR_DEPTH_101010;
-+	case 12:
-+		return COLOR_DEPTH_121212;
-+	case 14:
-+		return COLOR_DEPTH_141414;
-+	case 16:
-+		return COLOR_DEPTH_161616;
-+	default:
-+		return COLOR_DEPTH_UNDEFINED;
-+	}
-+}
-+
-+static enum dc_aspect_ratio get_aspect_ratio(
-+		const struct drm_display_mode *mode_in)
-+{
-+	int32_t width = mode_in->crtc_hdisplay * 9;
-+	int32_t height = mode_in->crtc_vdisplay * 16;
-+	if ((width - height) < 10 && (width - height) > -10)
-+		return ASPECT_RATIO_16_9;
-+	else
-+		return ASPECT_RATIO_4_3;
-+}
-+
-+/*****************************************************************************/
-+
-+static void dc_timing_from_drm_display_mode(
-+	struct dc_crtc_timing *timing_out,
-+	const struct drm_display_mode *mode_in,
-+	const struct drm_connector *connector)
-+{
-+	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
-+
-+	timing_out->h_border_left = 0;
-+	timing_out->h_border_right = 0;
-+	timing_out->v_border_top = 0;
-+	timing_out->v_border_bottom = 0;
-+	/* TODO: un-hardcode */
-+	timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
-+	timing_out->timing_standard = TIMING_STANDARD_HDMI;
-+	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
-+	timing_out->display_color_depth = convert_color_depth_from_display_info(
-+			connector);
-+	timing_out->scan_type = SCANNING_TYPE_NODATA;
-+	timing_out->hdmi_vic = 0;
-+	timing_out->vic = drm_match_cea_mode(mode_in);
-+
-+	timing_out->h_addressable = mode_in->crtc_hdisplay;
-+	timing_out->h_total = mode_in->crtc_htotal;
-+	timing_out->h_sync_width =
-+		mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
-+	timing_out->h_front_porch =
-+		mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
-+	timing_out->v_total = mode_in->crtc_vtotal;
-+	timing_out->v_addressable = mode_in->crtc_vdisplay;
-+	timing_out->v_front_porch =
-+		mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
-+	timing_out->v_sync_width =
-+		mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
-+	timing_out->pix_clk_khz = mode_in->crtc_clock;
-+	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
-+}
-+
-+static void fill_audio_info(
-+	struct audio_info *audio_info,
-+	const struct drm_connector *drm_connector,
-+	const struct dc_sink *dc_sink)
-+{
-+	int i = 0;
-+	int cea_revision = 0;
-+	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
-+
-+	audio_info->manufacture_id = edid_caps->manufacturer_id;
-+	audio_info->product_id = edid_caps->product_id;
-+
-+	cea_revision = drm_connector->display_info.cea_rev;
-+
-+	while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
-+		edid_caps->display_name[i]) {
-+		audio_info->display_name[i] = edid_caps->display_name[i];
-+		i++;
-+	}
-+
-+	if(cea_revision >= 3) {
-+		audio_info->mode_count = edid_caps->audio_mode_count;
-+
-+		for (i = 0; i < audio_info->mode_count; ++i) {
-+			audio_info->modes[i].format_code =
-+					(enum audio_format_code)
-+					(edid_caps->audio_modes[i].format_code);
-+			audio_info->modes[i].channel_count =
-+					edid_caps->audio_modes[i].channel_count;
-+			audio_info->modes[i].sample_rates.all =
-+					edid_caps->audio_modes[i].sample_rate;
-+			audio_info->modes[i].sample_size =
-+					edid_caps->audio_modes[i].sample_size;
-+		}
-+	}
-+
-+	audio_info->flags.all = edid_caps->speaker_flags;
-+
-+	/* TODO: We only check for the progressive mode, check for interlace mode too */
-+	if(drm_connector->latency_present[0]) {
-+		audio_info->video_latency = drm_connector->video_latency[0];
-+		audio_info->audio_latency = drm_connector->audio_latency[0];
-+	}
-+
-+	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */
-+
-+}
-+
-+/*TODO: move these defines elsewhere*/
-+#define DAL_MAX_CONTROLLERS 4
-+
-+static void calculate_stream_scaling_settings(
-+		const struct drm_display_mode *mode,
-+		enum amdgpu_rmx_type rmx_type,
-+		struct dc_stream *stream,
-+		uint8_t underscan_vborder,
-+		uint8_t underscan_hborder,
-+		bool underscan_enable)
-+{
-+	/* Full screen scaling by default */
-+	stream->src.width = mode->hdisplay;
-+	stream->src.height = mode->vdisplay;
-+	stream->dst.width = stream->timing.h_addressable;
-+	stream->dst.height = stream->timing.v_addressable;
-+
-+	if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
-+		if (stream->src.width * stream->dst.height <
-+				stream->src.height * stream->dst.width) {
-+			/* height needs less upscaling/more downscaling */
-+			stream->dst.width = stream->src.width *
-+					stream->dst.height / stream->src.height;
-+		} else {
-+			/* width needs less upscaling/more downscaling */
-+			stream->dst.height = stream->src.height *
-+					stream->dst.width / stream->src.width;
-+		}
-+	} else if (rmx_type == RMX_CENTER) {
-+		stream->dst = stream->src;
-+	}
-+
-+	stream->dst.x = (stream->timing.h_addressable - stream->dst.width) / 2;
-+	stream->dst.y = (stream->timing.v_addressable - stream->dst.height) / 2;
-+
-+	if (underscan_enable) {
-+		stream->dst.x += underscan_hborder / 2;
-+		stream->dst.y += underscan_vborder / 2;
-+		stream->dst.width -= underscan_hborder;
-+		stream->dst.height -= underscan_vborder;
-+	}
-+}
-+
-+
-+static void copy_crtc_timing_for_drm_display_mode(
-+		const struct drm_display_mode *src_mode,
-+		struct drm_display_mode *dst_mode)
-+{
-+	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
-+	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
-+	dst_mode->crtc_clock = src_mode->crtc_clock;
-+	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
-+	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
-+	dst_mode->crtc_hsync_start=  src_mode->crtc_hsync_start;
-+	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
-+	dst_mode->crtc_htotal = src_mode->crtc_htotal;
-+	dst_mode->crtc_hskew = src_mode->crtc_hskew;
-+	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;;
-+	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;;
-+	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;;
-+	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;;
-+	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;;
-+}
-+
-+static void decide_crtc_timing_for_drm_display_mode(
-+		struct drm_display_mode *drm_mode,
-+		const struct drm_display_mode *native_mode,
-+		bool scale_enabled)
-+{
-+	if (scale_enabled) {
-+		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
-+	} else if (native_mode->clock == drm_mode->clock &&
-+			native_mode->htotal == drm_mode->htotal &&
-+			native_mode->vtotal == drm_mode->vtotal) {
-+		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
-+	} else {
-+		/* no scaling nor amdgpu inserted, no need to patch */
-+	}
-+}
-+
-+
-+static struct dc_target *create_target_for_sink(
-+		const struct amdgpu_connector *aconnector,
-+		struct drm_display_mode *drm_mode)
-+{
-+	struct drm_display_mode *preferred_mode = NULL;
-+	const struct drm_connector *drm_connector;
-+	struct dm_connector_state *dm_state;
-+	struct dc_target *target = NULL;
-+	struct dc_stream *stream;
-+	struct drm_display_mode mode = *drm_mode;
-+	bool native_mode_found = false;
-+
-+	if (NULL == aconnector) {
-+		DRM_ERROR("aconnector is NULL!\n");
-+		goto drm_connector_null;
-+	}
-+
-+	drm_connector = &aconnector->base;
-+	dm_state = to_dm_connector_state(drm_connector->state);
-+	stream = dc_create_stream_for_sink(aconnector->dc_sink);
-+
-+	if (NULL == stream) {
-+		DRM_ERROR("Failed to create stream for sink!\n");
-+		goto stream_create_fail;
-+	}
-+
-+	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
-+		/* Search for preferred mode */
-+		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
-+			native_mode_found = true;
-+			break;
-+		}
-+	}
-+	if (!native_mode_found)
-+		preferred_mode = list_first_entry_or_null(
-+				&aconnector->base.modes,
-+				struct drm_display_mode,
-+				head);
-+
-+	decide_crtc_timing_for_drm_display_mode(
-+			&mode, preferred_mode,
-+			dm_state->scaling != RMX_OFF);
-+
-+	dc_timing_from_drm_display_mode(&stream->timing,
-+			&mode, &aconnector->base);
-+
-+	calculate_stream_scaling_settings(&mode, dm_state->scaling, stream,
-+			dm_state->underscan_vborder,
-+			dm_state->underscan_hborder,
-+			dm_state->underscan_enable);
-+
-+
-+	fill_audio_info(
-+		&stream->audio_info,
-+		drm_connector,
-+		aconnector->dc_sink);
-+
-+	target = dc_create_target_for_streams(&stream, 1);
-+	dc_stream_release(stream);
-+
-+	if (NULL == target) {
-+		DRM_ERROR("Failed to create target with streams!\n");
-+		goto target_create_fail;
-+	}
-+
-+drm_connector_null:
-+target_create_fail:
-+stream_create_fail:
-+	return target;
-+}
-+
-+void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
-+{
-+	drm_crtc_cleanup(crtc);
-+	kfree(crtc);
-+}
-+
-+static void amdgpu_dm_atomic_crtc_gamma_set(
-+		struct drm_crtc *crtc,
-+		u16 *red,
-+		u16 *green,
-+		u16 *blue,
-+		uint32_t start,
-+		uint32_t size)
-+{
-+	struct drm_device *dev = crtc->dev;
-+	struct drm_property *prop = dev->mode_config.prop_crtc_id;
-+
-+	crtc->mode.private_flags |= AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
-+
-+	drm_atomic_helper_crtc_set_property(crtc, prop, 0);
-+}
-+
-+static int dm_crtc_funcs_atomic_set_property(
-+	struct drm_crtc *crtc,
-+	struct drm_crtc_state *state,
-+	struct drm_property *property,
-+	uint64_t val)
-+{
-+	struct drm_crtc_state *new_crtc_state;
-+	struct drm_crtc *new_crtc;
-+	int i;
-+
-+	for_each_crtc_in_state(state->state, new_crtc, new_crtc_state, i) {
-+		if (new_crtc == crtc) {
-+			struct drm_plane_state *plane_state;
-+
-+			new_crtc_state->planes_changed = true;
-+
-+			/*
-+			 * Bit of magic done here. We need to ensure
-+			 * that planes get update after mode is set.
-+			 * So, we need to add primary plane to state,
-+			 * and this way atomic_update would be called
-+			 * for it
-+			 */
-+			plane_state =
-+				drm_atomic_get_plane_state(
-+					state->state,
-+					crtc->primary);
-+
-+			if (!plane_state)
-+				return -EINVAL;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/* Implemented only the options currently availible for the driver */
-+static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
-+	.reset = drm_atomic_helper_crtc_reset,
-+	.cursor_set = dm_crtc_cursor_set,
-+	.cursor_move = dm_crtc_cursor_move,
-+	.destroy = amdgpu_dm_crtc_destroy,
-+	.gamma_set = amdgpu_dm_atomic_crtc_gamma_set,
-+	.set_config = drm_atomic_helper_set_config,
-+	.page_flip = drm_atomic_helper_page_flip,
-+	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
-+	.atomic_set_property = dm_crtc_funcs_atomic_set_property
-+};
-+
-+static enum drm_connector_status
-+amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
-+{
-+	bool connected;
-+	struct amdgpu_connector *aconnector =
-+			to_amdgpu_connector(connector);
-+
-+	/*
-+	 * TODO: check whether we should lock here for mst_mgr.lock
-+	 */
-+	/* set root connector to disconnected */
-+	if (aconnector->mst_mgr.mst_state)
-+		return connector_status_disconnected;
-+
-+	connected = (NULL != aconnector->dc_sink);
-+	return (connected ? connector_status_connected :
-+			connector_status_disconnected);
-+}
-+
-+int amdgpu_dm_connector_atomic_set_property(
-+	struct drm_connector *connector,
-+	struct drm_connector_state *state,
-+	struct drm_property *property,
-+	uint64_t val)
-+{
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct dm_connector_state *dm_old_state =
-+		to_dm_connector_state(connector->state);
-+	struct dm_connector_state *dm_new_state =
-+		to_dm_connector_state(state);
-+
-+	if (property == dev->mode_config.scaling_mode_property) {
-+		struct drm_crtc_state *new_crtc_state;
-+		struct drm_crtc *crtc;
-+		int i;
-+		enum amdgpu_rmx_type rmx_type;
-+
-+		switch (val) {
-+		case DRM_MODE_SCALE_CENTER:
-+			rmx_type = RMX_CENTER;
-+			break;
-+		case DRM_MODE_SCALE_ASPECT:
-+			rmx_type = RMX_ASPECT;
-+			break;
-+		case DRM_MODE_SCALE_FULLSCREEN:
-+			rmx_type = RMX_FULL;
-+			break;
-+		case DRM_MODE_SCALE_NONE:
-+		default:
-+			rmx_type = RMX_OFF;
-+			break;
-+		}
-+
-+		if (dm_old_state->scaling == rmx_type)
-+			return 0;
-+
-+		dm_new_state->scaling = rmx_type;
-+
-+		for_each_crtc_in_state(state->state, crtc, new_crtc_state, i) {
-+			if (crtc == state->crtc) {
-+				struct drm_plane_state *plane_state;
-+
-+				new_crtc_state->mode_changed = true;
-+
-+				/*
-+				 * Bit of magic done here. We need to ensure
-+				 * that planes get update after mode is set.
-+				 * So, we need to add primary plane to state,
-+				 * and this way atomic_update would be called
-+				 * for it
-+				 */
-+				plane_state =
-+					drm_atomic_get_plane_state(
-+						state->state,
-+						crtc->primary);
-+
-+				if (!plane_state)
-+					return -EINVAL;
-+			}
-+		}
-+
-+		return 0;
-+	} else if (property == adev->mode_info.underscan_hborder_property) {
-+		dm_new_state->underscan_hborder = val;
-+		return 0;
-+	} else if (property == adev->mode_info.underscan_vborder_property) {
-+		dm_new_state->underscan_vborder = val;
-+		return 0;
-+	} else if (property == adev->mode_info.underscan_property) {
-+		struct drm_crtc_state *new_crtc_state;
-+		struct drm_crtc *crtc;
-+		int i;
-+
-+		dm_new_state->underscan_enable = val;
-+		for_each_crtc_in_state(state->state, crtc, new_crtc_state, i) {
-+			if (crtc == state->crtc) {
-+				struct drm_plane_state *plane_state;
-+
-+				new_crtc_state->mode_changed = true;
-+
-+				/*
-+				 * Bit of magic done here. We need to ensure
-+				 * that planes get update after mode is set.
-+				 * So, we need to add primary plane to state,
-+				 * and this way atomic_update would be called
-+				 * for it
-+				 */
-+				plane_state =
-+					drm_atomic_get_plane_state(
-+						state->state,
-+						crtc->primary);
-+
-+				if (!plane_state)
-+					return -EINVAL;
-+			}
-+		}
-+
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+void amdgpu_dm_connector_destroy(struct drm_connector *connector)
-+{
-+	/*drm_sysfs_connector_remove(connector);*/
-+	drm_connector_cleanup(connector);
-+	kfree(connector);
-+}
-+
-+void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
-+{
-+	struct dm_connector_state *state =
-+		to_dm_connector_state(connector->state);
-+
-+	kfree(state);
-+
-+	state = kzalloc(sizeof(*state), GFP_KERNEL);
-+
-+	if (state) {
-+		state->scaling = RMX_OFF;
-+
-+		connector->state = &state->base;
-+		connector->state->connector = connector;
-+	}
-+}
-+
-+struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
-+	struct drm_connector *connector)
-+{
-+	struct dm_connector_state *state =
-+		to_dm_connector_state(connector->state);
-+
-+	struct dm_connector_state *new_state =
-+		kzalloc(sizeof(*new_state), GFP_KERNEL);
-+
-+	if (new_state) {
-+		*new_state = *state;
-+
-+		return &new_state->base;
-+	}
-+
-+	return NULL;
-+}
-+
-+void amdgpu_dm_connector_atomic_destroy_state(
-+	struct drm_connector *connector,
-+	struct drm_connector_state *state)
-+{
-+	struct dm_connector_state *dm_state =
-+		to_dm_connector_state(state);
-+
-+	__drm_atomic_helper_connector_destroy_state(connector, state);
-+
-+	kfree(dm_state);
-+}
-+
-+static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
-+	.dpms = drm_atomic_helper_connector_dpms,
-+	.reset = amdgpu_dm_connector_funcs_reset,
-+	.detect = amdgpu_dm_connector_detect,
-+	.fill_modes = drm_helper_probe_single_connector_modes,
-+	.set_property = drm_atomic_helper_connector_set_property,
-+	.destroy = amdgpu_dm_connector_destroy,
-+	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
-+	.atomic_destroy_state = amdgpu_dm_connector_atomic_destroy_state,
-+	.atomic_set_property = amdgpu_dm_connector_atomic_set_property
-+};
-+
-+static struct drm_encoder *best_encoder(struct drm_connector *connector)
-+{
-+	int enc_id = connector->encoder_ids[0];
-+	struct drm_mode_object *obj;
-+	struct drm_encoder *encoder;
-+
-+	DRM_DEBUG_KMS("Finding the best encoder\n");
-+
-+	/* pick the encoder ids */
-+	if (enc_id) {
-+		obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
-+		if (!obj) {
-+			DRM_ERROR("Couldn't find a matching encoder for our connector\n");
-+			return NULL;
-+		}
-+		encoder = obj_to_encoder(obj);
-+		return encoder;
-+	}
-+	DRM_ERROR("No encoder id\n");
-+	return NULL;
-+}
-+
-+static int get_modes(struct drm_connector *connector)
-+{
-+	struct amdgpu_connector *amdgpu_connector =
-+			to_amdgpu_connector(connector);
-+	return amdgpu_connector->num_modes;
-+}
-+
-+static int mode_valid(struct drm_connector *connector,
-+		struct drm_display_mode *mode)
-+{
-+	int result = MODE_ERROR;
-+	const struct dc_sink *dc_sink =
-+			to_amdgpu_connector(connector)->dc_sink;
-+	struct amdgpu_device *adev = connector->dev->dev_private;
-+	struct dc_validation_set val_set = { 0 };
-+	/* TODO: Unhardcode stream count */
-+	struct dc_stream *streams[1];
-+	struct dc_target *target;
-+
-+	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
-+			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
-+		return result;
-+
-+	if (NULL == dc_sink) {
-+		DRM_ERROR("dc_sink is NULL!\n");
-+		goto stream_create_fail;
-+	}
-+
-+	streams[0] = dc_create_stream_for_sink(dc_sink);
-+
-+	if (NULL == streams[0]) {
-+		DRM_ERROR("Failed to create stream for sink!\n");
-+		goto stream_create_fail;
-+	}
-+
-+	drm_mode_set_crtcinfo(mode, 0);
-+	dc_timing_from_drm_display_mode(&streams[0]->timing, mode, connector);
-+
-+	target = dc_create_target_for_streams(streams, 1);
-+	val_set.target = target;
-+
-+	if (NULL == val_set.target) {
-+		DRM_ERROR("Failed to create target with stream!\n");
-+		goto target_create_fail;
-+	}
-+
-+	val_set.surface_count = 0;
-+	streams[0]->src.width = mode->hdisplay;
-+	streams[0]->src.height = mode->vdisplay;
-+	streams[0]->dst = streams[0]->src;
-+
-+	if (dc_validate_resources(adev->dm.dc, &val_set, 1))
-+		result = MODE_OK;
-+
-+	dc_target_release(target);
-+target_create_fail:
-+	dc_stream_release(streams[0]);
-+stream_create_fail:
-+	/* TODO: error handling*/
-+	return result;
-+}
-+
-+
-+static const struct drm_connector_helper_funcs
-+amdgpu_dm_connector_helper_funcs = {
-+	/*
-+	* If hotplug a second bigger display in FB Con mode, bigger resolution
-+	* modes will be filtered by drm_mode_validate_size(), and those modes
-+	* is missing after user start lightdm. So we need to renew modes list.
-+	* in get_modes call back, not just return the modes count
-+	*/
-+	.get_modes = get_modes,
-+	.mode_valid = mode_valid,
-+	.best_encoder = best_encoder
-+};
-+
-+static void dm_crtc_helper_disable(struct drm_crtc *crtc)
-+{
-+}
-+
-+static int dm_crtc_helper_atomic_check(
-+	struct drm_crtc *crtc,
-+	struct drm_crtc_state *state)
-+{
-+	return 0;
-+}
-+
-+static bool dm_crtc_helper_mode_fixup(
-+	struct drm_crtc *crtc,
-+	const struct drm_display_mode *mode,
-+	struct drm_display_mode *adjusted_mode)
-+{
-+	return true;
-+}
-+
-+static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
-+	.disable = dm_crtc_helper_disable,
-+	.atomic_check = dm_crtc_helper_atomic_check,
-+	.mode_fixup = dm_crtc_helper_mode_fixup
-+};
-+
-+static void dm_encoder_helper_disable(struct drm_encoder *encoder)
-+{
-+
-+}
-+
-+static int dm_encoder_helper_atomic_check(
-+	struct drm_encoder *encoder,
-+	struct drm_crtc_state *crtc_state,
-+	struct drm_connector_state *conn_state)
-+{
-+	return 0;
-+}
-+
-+const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
-+	.disable = dm_encoder_helper_disable,
-+	.atomic_check = dm_encoder_helper_atomic_check
-+};
-+
-+static const struct drm_plane_funcs dm_plane_funcs = {
-+	.reset = drm_atomic_helper_plane_reset,
-+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state
-+};
-+
-+static void clear_unrelated_fields(struct drm_plane_state *state)
-+{
-+	state->crtc = NULL;
-+	state->fb = NULL;
-+	state->state = NULL;
-+	state->fence = NULL;
-+}
-+
-+static bool page_flip_needed(
-+	struct drm_plane_state *new_state,
-+	struct drm_plane_state *old_state)
-+{
-+	struct drm_plane_state old_state_tmp;
-+	struct drm_plane_state new_state_tmp;
-+
-+	struct amdgpu_framebuffer *amdgpu_fb_old;
-+	struct amdgpu_framebuffer *amdgpu_fb_new;
-+
-+	uint64_t old_tiling_flags;
-+	uint64_t new_tiling_flags;
-+
-+	if (!old_state)
-+		return false;
-+
-+	if (!old_state->fb)
-+		return false;
-+
-+	if (!new_state)
-+		return false;
-+
-+	if (!new_state->fb)
-+		return false;
-+
-+	old_state_tmp = *old_state;
-+	new_state_tmp = *new_state;
-+
-+	if (!new_state->crtc->state->event)
-+		return false;
-+
-+	amdgpu_fb_old = to_amdgpu_framebuffer(old_state->fb);
-+	amdgpu_fb_new = to_amdgpu_framebuffer(new_state->fb);
-+
-+	if (!get_fb_info(amdgpu_fb_old, &old_tiling_flags, NULL))
-+		return false;
-+
-+	if (!get_fb_info(amdgpu_fb_new, &new_tiling_flags, NULL))
-+		return false;
-+
-+	if (old_tiling_flags != new_tiling_flags)
-+		return false;
-+
-+	clear_unrelated_fields(&old_state_tmp);
-+	clear_unrelated_fields(&new_state_tmp);
-+
-+	return memcmp(&old_state_tmp, &new_state_tmp, sizeof(old_state_tmp)) == 0;
-+}
-+
-+static int dm_plane_helper_prepare_fb(
-+	struct drm_plane *plane,
-+	const struct drm_plane_state *new_state)
-+{
-+	struct amdgpu_framebuffer *afb;
-+	struct drm_gem_object *obj;
-+	struct amdgpu_bo *rbo;
-+	int r;
-+
-+	if (!new_state->fb) {
-+		DRM_DEBUG_KMS("No FB bound\n");
-+		return 0;
-+	}
-+
-+	afb = to_amdgpu_framebuffer(new_state->fb);
-+
-+	DRM_DEBUG_KMS("Pin new framebuffer: %p\n", afb);
-+	obj = afb->obj;
-+	rbo = gem_to_amdgpu_bo(obj);
-+	r = amdgpu_bo_reserve(rbo, false);
-+	if (unlikely(r != 0))
-+		return r;
-+
-+	r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
-+
-+	amdgpu_bo_unreserve(rbo);
-+
-+	if (unlikely(r != 0)) {
-+		DRM_ERROR("Failed to pin framebuffer\n");
-+		return r;
-+	}
-+
-+	return 0;
-+}
-+
-+static void dm_plane_helper_cleanup_fb(
-+	struct drm_plane *plane,
-+	const struct drm_plane_state *old_state)
-+{
-+	struct amdgpu_bo *rbo;
-+	struct amdgpu_framebuffer *afb;
-+	int r;
-+
-+	if (!old_state->fb)
-+		return;
-+
-+	afb = to_amdgpu_framebuffer(old_state->fb);
-+	DRM_DEBUG_KMS("Unpin old framebuffer: %p\n", afb);
-+	rbo = gem_to_amdgpu_bo(afb->obj);
-+	r = amdgpu_bo_reserve(rbo, false);
-+	if (unlikely(r)) {
-+		DRM_ERROR("failed to reserve rbo before unpin\n");
-+		return;
-+	} else {
-+		amdgpu_bo_unpin(rbo);
-+		amdgpu_bo_unreserve(rbo);
-+	}
-+}
-+
-+int dm_create_validation_set_for_target(struct drm_connector *connector,
-+		struct drm_display_mode *mode, struct dc_validation_set *val_set)
-+{
-+	int result = MODE_ERROR;
-+	const struct dc_sink *dc_sink =
-+			to_amdgpu_connector(connector)->dc_sink;
-+	/* TODO: Unhardcode stream count */
-+	struct dc_stream *streams[1];
-+	struct dc_target *target;
-+
-+	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
-+			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
-+		return result;
-+
-+	if (NULL == dc_sink) {
-+		DRM_ERROR("dc_sink is NULL!\n");
-+		return result;
-+	}
-+
-+	streams[0] = dc_create_stream_for_sink(dc_sink);
-+
-+	if (NULL == streams[0]) {
-+		DRM_ERROR("Failed to create stream for sink!\n");
-+		return result;
-+	}
-+
-+	drm_mode_set_crtcinfo(mode, 0);
-+	dc_timing_from_drm_display_mode(&streams[0]->timing, mode, connector);
-+
-+	target = dc_create_target_for_streams(streams, 1);
-+	val_set->target = target;
-+
-+	if (NULL == val_set->target) {
-+		DRM_ERROR("Failed to create target with stream!\n");
-+		goto fail;
-+	}
-+
-+	streams[0]->src.width = mode->hdisplay;
-+	streams[0]->src.height = mode->vdisplay;
-+	streams[0]->dst = streams[0]->src;
-+
-+	return MODE_OK;
-+
-+fail:
-+	dc_stream_release(streams[0]);
-+	return result;
-+
-+}
-+
-+int dm_add_surface_to_validation_set(struct drm_plane *plane,
-+		    struct drm_plane_state *state, struct dc_surface **surface)
-+{
-+	int res;
-+
-+	struct amdgpu_framebuffer *afb;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_crtc *crtc;
-+	struct drm_framebuffer *fb;
-+
-+	struct drm_device *dev;
-+	struct amdgpu_device *adev;
-+
-+	res = -EINVAL;
-+
-+	if (NULL == plane || NULL == state) {
-+		DRM_ERROR("invalid parameters dm_plane_atomic_check\n");
-+		return res;
-+	}
-+
-+	crtc = state->crtc;
-+	fb = state->fb;
-+
-+
-+	afb = to_amdgpu_framebuffer(fb);
-+
-+	if (NULL == state->crtc) {
-+		return res;
-+	}
-+
-+	aconnector = aconnector_from_drm_crtc(crtc, state->state);
-+
-+	if (NULL == aconnector) {
-+		DRM_ERROR("Connector is NULL in dm_plane_atomic_check\n");
-+		return res;
-+	}
-+
-+	if (NULL == aconnector->dc_sink) {
-+		DRM_ERROR("dc_sink is NULL in dm_plane_atomic_check\n");
-+		return res;
-+	}
-+	dev  = state->crtc->dev;
-+	adev = dev->dev_private;
-+
-+	*surface = dc_create_surface(adev->dm.dc);
-+	if (NULL == *surface){
-+		DRM_ERROR("surface is NULL\n");
-+		return res;
-+	}
-+
-+	if (!fill_rects_from_plane_state( state, *surface)) {
-+		DRM_ERROR("Failed to fill surface!\n");
-+		goto fail;
-+	}
-+
-+	fill_plane_attributes_from_fb(*surface, afb);
-+
-+	return MODE_OK;
-+
-+fail:
-+	dc_surface_release(*surface);
-+	return res;
-+}
-+
-+static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
-+	.prepare_fb = dm_plane_helper_prepare_fb,
-+	.cleanup_fb = dm_plane_helper_cleanup_fb,
-+};
-+
-+/*
-+ * TODO: these are currently initialized to rgb formats only.
-+ * For future use cases we should either initialize them dynamically based on
-+ * plane capabilities, or initialize this array to all formats, so internal drm
-+ * check will succeed, and let DC to implement proper check
-+ */
-+static uint32_t rgb_formats[] = {
-+	DRM_FORMAT_XRGB4444,
-+	DRM_FORMAT_ARGB4444,
-+	DRM_FORMAT_RGBA4444,
-+	DRM_FORMAT_ARGB1555,
-+	DRM_FORMAT_RGB565,
-+	DRM_FORMAT_RGB888,
-+	DRM_FORMAT_XRGB8888,
-+	DRM_FORMAT_ARGB8888,
-+	DRM_FORMAT_RGBA8888,
-+};
-+
-+int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
-+			struct amdgpu_crtc *acrtc,
-+			uint32_t link_index)
-+{
-+	int res = -ENOMEM;
-+
-+	struct drm_plane *primary_plane =
-+		kzalloc(sizeof(*primary_plane), GFP_KERNEL);
-+
-+	if (!primary_plane)
-+		goto fail_plane;
-+
-+	/* this flag is used in legacy code only */
-+	primary_plane->format_default = true;
-+
-+	res = drm_universal_plane_init(
-+		dm->adev->ddev,
-+		primary_plane,
-+		0,
-+		&dm_plane_funcs,
-+		rgb_formats,
-+		ARRAY_SIZE(rgb_formats),
-+		DRM_PLANE_TYPE_PRIMARY, NULL);
-+
-+	primary_plane->crtc = &acrtc->base;
-+
-+	drm_plane_helper_add(primary_plane, &dm_plane_helper_funcs);
-+
-+	res = drm_crtc_init_with_planes(
-+			dm->ddev,
-+			&acrtc->base,
-+			primary_plane,
-+			NULL,
-+			&amdgpu_dm_crtc_funcs, NULL);
-+
-+	if (res)
-+		goto fail;
-+
-+	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
-+
-+	acrtc->max_cursor_width = 128;
-+	acrtc->max_cursor_height = 128;
-+
-+	acrtc->crtc_id = link_index;
-+	acrtc->base.enabled = false;
-+
-+	dm->adev->mode_info.crtcs[link_index] = acrtc;
-+	drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
-+
-+	return 0;
-+fail:
-+	kfree(primary_plane);
-+fail_plane:
-+	acrtc->crtc_id = -1;
-+	return res;
-+}
-+
-+static int to_drm_connector_type(enum signal_type st)
-+{
-+	switch (st) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		return DRM_MODE_CONNECTOR_HDMIA;
-+	case SIGNAL_TYPE_EDP:
-+		return DRM_MODE_CONNECTOR_eDP;
-+	case SIGNAL_TYPE_RGB:
-+		return DRM_MODE_CONNECTOR_VGA;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		return DRM_MODE_CONNECTOR_DisplayPort;
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+		return DRM_MODE_CONNECTOR_DVID;
-+
-+	default:
-+		return DRM_MODE_CONNECTOR_Unknown;
-+	}
-+}
-+
-+static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
-+{
-+	const struct drm_connector_helper_funcs *helper =
-+		connector->helper_private;
-+	struct drm_encoder *encoder;
-+	struct amdgpu_encoder *amdgpu_encoder;
-+
-+	encoder = helper->best_encoder(connector);
-+
-+	if (encoder == NULL)
-+		return;
-+
-+	amdgpu_encoder = to_amdgpu_encoder(encoder);
-+
-+	amdgpu_encoder->native_mode.clock = 0;
-+
-+	if (!list_empty(&connector->probed_modes)) {
-+		struct drm_display_mode *preferred_mode = NULL;
-+		list_for_each_entry(preferred_mode,
-+				&connector->probed_modes,
-+				head) {
-+		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
-+			amdgpu_encoder->native_mode = *preferred_mode;
-+		}
-+			break;
-+		}
-+
-+	}
-+}
-+
-+static struct drm_display_mode *amdgpu_dm_create_common_mode(
-+		struct drm_encoder *encoder, char *name,
-+		int hdisplay, int vdisplay)
-+{
-+	struct drm_device *dev = encoder->dev;
-+	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
-+	struct drm_display_mode *mode = NULL;
-+	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
-+
-+	mode = drm_mode_duplicate(dev, native_mode);
-+
-+	if(mode == NULL)
-+		return NULL;
-+
-+	mode->hdisplay = hdisplay;
-+	mode->vdisplay = vdisplay;
-+	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
-+	strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
-+
-+	return mode;
-+
-+}
-+
-+static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
-+					struct drm_connector *connector)
-+{
-+	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
-+	struct drm_display_mode *mode = NULL;
-+	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
-+	struct amdgpu_connector *amdgpu_connector =
-+				to_amdgpu_connector(connector);
-+	int i;
-+	int n;
-+	struct mode_size {
-+		char name[DRM_DISPLAY_MODE_LEN];
-+		int w;
-+		int h;
-+	}common_modes[] = {
-+		{  "640x480",  640,  480},
-+		{  "800x600",  800,  600},
-+		{ "1024x768", 1024,  768},
-+		{ "1280x720", 1280,  720},
-+		{ "1280x800", 1280,  800},
-+		{"1280x1024", 1280, 1024},
-+		{ "1440x900", 1440,  900},
-+		{"1680x1050", 1680, 1050},
-+		{"1600x1200", 1600, 1200},
-+		{"1920x1080", 1920, 1080},
-+		{"1920x1200", 1920, 1200}
-+	};
-+
-+	n = sizeof(common_modes) / sizeof(common_modes[0]);
-+
-+	for (i = 0; i < n; i++) {
-+		struct drm_display_mode *curmode = NULL;
-+		bool mode_existed = false;
-+
-+		if (common_modes[i].w > native_mode->hdisplay ||
-+			common_modes[i].h > native_mode->vdisplay ||
-+			(common_modes[i].w == native_mode->hdisplay &&
-+			common_modes[i].h == native_mode->vdisplay))
-+				continue;
-+
-+		list_for_each_entry(curmode, &connector->probed_modes, head) {
-+			if (common_modes[i].w == curmode->hdisplay &&
-+				common_modes[i].h == curmode->vdisplay) {
-+				mode_existed = true;
-+				break;
-+			}
-+		}
-+
-+		if (mode_existed)
-+			continue;
-+
-+		mode = amdgpu_dm_create_common_mode(encoder,
-+				common_modes[i].name, common_modes[i].w,
-+				common_modes[i].h);
-+		drm_mode_probed_add(connector, mode);
-+		amdgpu_connector->num_modes++;
-+	}
-+}
-+
-+static void amdgpu_dm_connector_ddc_get_modes(
-+	struct drm_connector *connector,
-+	struct edid *edid)
-+{
-+	struct amdgpu_connector *amdgpu_connector =
-+			to_amdgpu_connector(connector);
-+
-+	if (edid) {
-+		/* empty probed_modes */
-+		INIT_LIST_HEAD(&connector->probed_modes);
-+		amdgpu_connector->num_modes =
-+				drm_add_edid_modes(connector, edid);
-+
-+		drm_edid_to_eld(connector, edid);
-+
-+		amdgpu_dm_get_native_mode(connector);
-+	} else
-+		amdgpu_connector->num_modes = 0;
-+}
-+
-+int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
-+{
-+	const struct drm_connector_helper_funcs *helper =
-+			connector->helper_private;
-+	struct amdgpu_connector *amdgpu_connector =
-+			to_amdgpu_connector(connector);
-+	struct drm_encoder *encoder;
-+	struct edid *edid = amdgpu_connector->edid;
-+
-+	encoder = helper->best_encoder(connector);
-+
-+	amdgpu_dm_connector_ddc_get_modes(connector, edid);
-+	amdgpu_dm_connector_add_common_modes(encoder, connector);
-+	return amdgpu_connector->num_modes;
-+}
-+
-+/* Note: this function assumes that dc_link_detect() was called for the
-+ * dc_link which will be represented by this aconnector. */
-+int amdgpu_dm_connector_init(
-+	struct amdgpu_display_manager *dm,
-+	struct amdgpu_connector *aconnector,
-+	uint32_t link_index,
-+	struct amdgpu_encoder *aencoder)
-+{
-+	int res, connector_type;
-+	struct amdgpu_device *adev = dm->ddev->dev_private;
-+	struct dc *dc = dm->dc;
-+	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
-+
-+	DRM_DEBUG_KMS("%s()\n", __func__);
-+
-+	connector_type = to_drm_connector_type(link->connector_signal);
-+
-+	res = drm_connector_init(
-+			dm->ddev,
-+			&aconnector->base,
-+			&amdgpu_dm_connector_funcs,
-+			connector_type);
-+
-+	if (res) {
-+		DRM_ERROR("connector_init failed\n");
-+		aconnector->connector_id = -1;
-+		return res;
-+	}
-+
-+	drm_connector_helper_add(
-+			&aconnector->base,
-+			&amdgpu_dm_connector_helper_funcs);
-+
-+	aconnector->connector_id = link_index;
-+	aconnector->dc_link = link;
-+	aconnector->base.interlace_allowed = true;
-+	aconnector->base.doublescan_allowed = true;
-+	aconnector->hpd.hpd = link_index; /* maps to 'enum amdgpu_hpd_id' */
-+
-+	/*configure suport HPD hot plug connector_>polled default value is 0
-+	 * which means HPD hot plug not supported*/
-+	switch (connector_type) {
-+	case DRM_MODE_CONNECTOR_HDMIA:
-+		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-+		break;
-+	case DRM_MODE_CONNECTOR_DisplayPort:
-+		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-+		break;
-+	case DRM_MODE_CONNECTOR_DVID:
-+		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	drm_object_attach_property(&aconnector->base.base,
-+				dm->ddev->mode_config.scaling_mode_property,
-+				DRM_MODE_SCALE_NONE);
-+
-+	drm_object_attach_property(&aconnector->base.base,
-+				adev->mode_info.underscan_property,
-+				UNDERSCAN_OFF);
-+	drm_object_attach_property(&aconnector->base.base,
-+				adev->mode_info.underscan_hborder_property,
-+				0);
-+	drm_object_attach_property(&aconnector->base.base,
-+				adev->mode_info.underscan_vborder_property,
-+				0);
-+
-+	/* TODO: Don't do this manually anymore
-+	aconnector->base.encoder = &aencoder->base;
-+	*/
-+
-+	drm_mode_connector_attach_encoder(
-+		&aconnector->base, &aencoder->base);
-+
-+	/*drm_sysfs_connector_add(&dm_connector->base);*/
-+
-+	drm_connector_register(&aconnector->base);
-+
-+	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort)
-+		amdgpu_dm_initialize_mst_connector(dm, aconnector);
-+
-+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-+
-+	/* NOTE: this currently will create backlight device even if a panel
-+	 * is not connected to the eDP/LVDS connector.
-+	 *
-+	 * This is less than ideal but we don't have sink information at this
-+	 * stage since detection happens after. We can't do detection earlier
-+	 * since MST detection needs connectors to be created first.
-+	 */
-+	if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
-+		/* Event if registration failed, we should continue with
-+		 * DM initialization because not having a backlight control
-+		 * is better then a black screen. */
-+		amdgpu_dm_register_backlight_device(dm);
-+
-+		if (dm->backlight_dev)
-+			dm->backlight_link = link;
-+	}
-+#endif
-+
-+	return 0;
-+}
-+
-+int amdgpu_dm_encoder_init(
-+	struct drm_device *dev,
-+	struct amdgpu_encoder *aencoder,
-+	uint32_t link_index,
-+	struct amdgpu_crtc *acrtc)
-+{
-+	int res = drm_encoder_init(dev,
-+				   &aencoder->base,
-+				   &amdgpu_dm_encoder_funcs,
-+				   DRM_MODE_ENCODER_TMDS,
-+				   NULL);
-+
-+	aencoder->base.possible_crtcs = 1 << link_index;
-+
-+	if (!res)
-+		aencoder->encoder_id = link_index;
-+	else
-+		aencoder->encoder_id = -1;
-+
-+	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
-+
-+	return res;
-+}
-+
-+enum dm_commit_action {
-+	DM_COMMIT_ACTION_NOTHING,
-+	DM_COMMIT_ACTION_RESET,
-+	DM_COMMIT_ACTION_DPMS_ON,
-+	DM_COMMIT_ACTION_DPMS_OFF,
-+	DM_COMMIT_ACTION_SET
-+};
-+
-+enum dm_commit_action get_dm_commit_action(struct drm_crtc *crtc,
-+		struct drm_crtc_state *state)
-+{
-+	/* mode changed means either actually mode changed or enabled changed */
-+	/* active changed means dpms changed */
-+	if (state->mode_changed) {
-+		/* if it is got disabled - call reset mode */
-+		if (!state->enable)
-+			return DM_COMMIT_ACTION_RESET;
-+
-+		if (state->active)
-+			return DM_COMMIT_ACTION_SET;
-+		else
-+			return DM_COMMIT_ACTION_RESET;
-+	} else {
-+		/* ! mode_changed */
-+
-+		/* if it is remain disable - skip it */
-+		if (!state->enable)
-+			return DM_COMMIT_ACTION_NOTHING;
-+
-+		if (state->active_changed) {
-+			if (state->active) {
-+				return DM_COMMIT_ACTION_DPMS_ON;
-+			} else {
-+				return DM_COMMIT_ACTION_DPMS_OFF;
-+			}
-+		} else {
-+			/* ! active_changed */
-+			return DM_COMMIT_ACTION_NOTHING;
-+		}
-+	}
-+}
-+
-+static void manage_dm_interrupts(
-+	struct amdgpu_device *adev,
-+	struct amdgpu_crtc *acrtc,
-+	bool enable)
-+{
-+	if (enable) {
-+		drm_crtc_vblank_on(&acrtc->base);
-+		amdgpu_irq_get(
-+			adev,
-+			&adev->pageflip_irq,
-+			amdgpu_crtc_idx_to_irq_type(
-+				adev,
-+				acrtc->crtc_id));
-+	} else {
-+		unsigned long flags;
-+		amdgpu_irq_put(
-+			adev,
-+			&adev->pageflip_irq,
-+			amdgpu_crtc_idx_to_irq_type(
-+				adev,
-+				acrtc->crtc_id));
-+		drm_crtc_vblank_off(&acrtc->base);
-+
-+		/*
-+		 * should be called here, to guarantee no works left in queue.
-+		 * As this function sleeps it was bug to call it inside the
-+		 * amdgpu_dm_flip_cleanup function under locked event_lock
-+		 */
-+		if (acrtc->pflip_works) {
-+			flush_work(&acrtc->pflip_works->flip_work);
-+			flush_work(&acrtc->pflip_works->unpin_work);
-+		}
-+
-+		/*
-+		 * TODO: once Vitaly's change to adjust locking in
-+		 * page_flip_work_func is submitted to base driver move
-+		 * lock and check to amdgpu_dm_flip_cleanup function
-+		 */
-+
-+		spin_lock_irqsave(&adev->ddev->event_lock, flags);
-+		if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
-+			/*
-+			 * this is the case when on reset, last pending pflip
-+			 * interrupt did not not occur. Clean-up
-+			 */
-+			amdgpu_dm_flip_cleanup(adev, acrtc);
-+		}
-+		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+	}
-+}
-+
-+/*
-+ * Handle headless hotplug workaround
-+ *
-+ * In case of headless hotplug, if plugging the same monitor to the same
-+ * DDI, DRM consider it as mode unchanged. We should check whether the
-+ * sink pointer changed, and set mode_changed properly to
-+ * make sure commit is doing everything.
-+ */
-+static void handle_headless_hotplug(
-+		const struct amdgpu_crtc *acrtc,
-+		struct drm_crtc_state *state,
-+		struct amdgpu_connector **aconnector)
-+{
-+	struct amdgpu_connector *old_connector =
-+			aconnector_from_drm_crtc_id(&acrtc->base);
-+
-+	/*
-+	 * TODO Revisit this. This code is kinda hacky and might break things.
-+	 */
-+
-+	if (!old_connector)
-+		return;
-+
-+	if (!*aconnector)
-+		*aconnector = old_connector;
-+
-+	if (acrtc->target && (*aconnector)->dc_sink) {
-+		if ((*aconnector)->dc_sink !=
-+				acrtc->target->streams[0]->sink) {
-+			state->mode_changed = true;
-+		}
-+	}
-+
-+	if (!acrtc->target) {
-+		/* In case of headless with DPMS on, when system waked up,
-+		 * if no monitor connected, target is null and will not create
-+		 * new target, on that condition, we should check
-+		 * if any connector is connected, if connected,
-+		 * it means a hot plug happened after wake up,
-+		 * mode_changed should be set to true to make sure
-+		 * commit targets will do everything.
-+		 */
-+		state->mode_changed =
-+			(*aconnector)->base.status ==
-+					connector_status_connected;
-+	} else {
-+		/* In case of headless hotplug, if plug same monitor to same
-+		 * DDI, DRM consider it as mode unchanged, we should check
-+		 * sink pointer changed, and set mode changed properly to
-+		 * make sure commit doing everything.
-+		 */
-+		/* check if sink has changed from last commit */
-+		if ((*aconnector)->dc_sink && (*aconnector)->dc_sink !=
-+					acrtc->target->streams[0]->sink)
-+			state->mode_changed = true;
-+	}
-+}
-+
-+int amdgpu_dm_atomic_commit(
-+	struct drm_device *dev,
-+	struct drm_atomic_state *state,
-+	bool async)
-+{
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *old_plane_state;
-+	uint32_t i;
-+	int32_t ret;
-+	uint32_t commit_targets_count = 0;
-+	uint32_t new_crtcs_count = 0;
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *old_crtc_state;
-+
-+	struct dc_target *commit_targets[DAL_MAX_CONTROLLERS];
-+	struct amdgpu_crtc *new_crtcs[DAL_MAX_CONTROLLERS];
-+
-+	/* In this step all new fb would be pinned */
-+
-+	ret = drm_atomic_helper_prepare_planes(dev, state);
-+	if (ret)
-+		return ret;
-+
-+	/*
-+	 * This is the point of no return - everything below never fails except
-+	 * when the hw goes bonghits. Which means we can commit the new state on
-+	 * the software side now.
-+	 */
-+
-+	drm_atomic_helper_swap_state(dev, state);
-+
-+	/*
-+	 * From this point state become old state really. New state is
-+	 * initialized to appropriate objects and could be accessed from there
-+	 */
-+
-+	/*
-+	 * there is no fences usage yet in state. We can skip the following line
-+	 * wait_for_fences(dev, state);
-+	 */
-+
-+	/* update changed items */
-+	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
-+		struct amdgpu_crtc *acrtc;
-+		struct amdgpu_connector *aconnector;
-+		enum dm_commit_action action;
-+		struct drm_crtc_state *new_state = crtc->state;
-+
-+		acrtc = to_amdgpu_crtc(crtc);
-+		aconnector = aconnector_from_drm_crtc(crtc, state);
-+
-+		/* handles headless hotplug case, updating new_state and
-+		 * aconnector as needed
-+		 */
-+		handle_headless_hotplug(acrtc, new_state, &aconnector);
-+
-+		action = get_dm_commit_action(crtc, new_state);
-+
-+		if (!aconnector) {
-+			DRM_ERROR("Can't find connector for crtc %d\n", acrtc->crtc_id);
-+			break;
-+		}
-+
-+		switch (action) {
-+		case DM_COMMIT_ACTION_DPMS_ON:
-+		case DM_COMMIT_ACTION_SET: {
-+			const struct drm_connector_helper_funcs *connector_funcs;
-+			struct dc_target *new_target =
-+				create_target_for_sink(
-+					aconnector,
-+					&crtc->state->mode);
-+
-+			if (!new_target) {
-+				/*
-+				 * this could happen because of issues with
-+				 * userspace notifications delivery.
-+				 * In this case userspace tries to set mode on
-+				 * display which is disconnect in fact.
-+				 * dc_sink in NULL in this case on aconnector.
-+				 * We expect reset mode will come soon.
-+				 *
-+				 * This can also happen when unplug is done
-+				 * during resume sequence ended
-+				 */
-+				new_state->planes_changed = false;
-+				break;
-+			}
-+
-+			if (acrtc->target) {
-+				/*
-+				 * we evade vblanks and pflips on crtc that
-+				 * should be changed
-+				 */
-+				manage_dm_interrupts(adev, acrtc, false);
-+				/* this is the update mode case */
-+				dc_target_release(acrtc->target);
-+				acrtc->target = NULL;
-+			}
-+
-+			/*
-+			 * this loop saves set mode crtcs
-+			 * we needed to enable vblanks once all
-+			 * resources acquired in dc after dc_commit_targets
-+			 */
-+			new_crtcs[new_crtcs_count] = acrtc;
-+			new_crtcs_count++;
-+
-+			acrtc->target = new_target;
-+			acrtc->enabled = true;
-+			acrtc->base.enabled = true;
-+			connector_funcs = aconnector->base.helper_private;
-+			aconnector->base.encoder =
-+				connector_funcs->best_encoder(
-+					&aconnector->base);
-+			break;
-+		}
-+
-+		case DM_COMMIT_ACTION_NOTHING:
-+			break;
-+
-+		case DM_COMMIT_ACTION_DPMS_OFF:
-+		case DM_COMMIT_ACTION_RESET:
-+			/* i.e. reset mode */
-+			if (acrtc->target) {
-+				manage_dm_interrupts(adev, acrtc, false);
-+
-+				dc_target_release(acrtc->target);
-+				acrtc->target = NULL;
-+				acrtc->enabled = false;
-+				acrtc->base.enabled = false;
-+				aconnector->base.encoder = NULL;
-+			}
-+			break;
-+		} /* switch() */
-+	} /* for_each_crtc_in_state() */
-+
-+	commit_targets_count = 0;
-+
-+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+
-+		if (acrtc->target) {
-+			commit_targets[commit_targets_count] = acrtc->target;
-+			++commit_targets_count;
-+		}
-+	}
-+
-+	/* DC is optimized not to do anything if 'targets' didn't change. */
-+	dc_commit_targets(dm->dc, commit_targets, commit_targets_count);
-+
-+	/* update planes when needed */
-+	for_each_plane_in_state(state, plane, old_plane_state, i) {
-+		struct drm_plane_state *plane_state = plane->state;
-+		struct drm_crtc *crtc = plane_state->crtc;
-+		struct drm_framebuffer *fb = plane_state->fb;
-+
-+		if (fb && crtc) {
-+			if (!crtc->state->planes_changed)
-+				continue;
-+
-+			if (page_flip_needed(
-+				plane_state,
-+				old_plane_state))
-+				amdgpu_crtc_page_flip(
-+					crtc,
-+					fb,
-+					crtc->state->event,
-+					0);
-+			else
-+				dm_dc_surface_commit(
-+					dm->dc,
-+					crtc,
-+					to_amdgpu_framebuffer(fb));
-+		}
-+	}
-+
-+	for (i = 0; i < new_crtcs_count; i++) {
-+		/*
-+		 * loop to enable interrupts on newly arrived crtc
-+		 */
-+		struct amdgpu_crtc *acrtc = new_crtcs[i];
-+
-+		manage_dm_interrupts(adev, acrtc, true);
-+		dm_crtc_cursor_reset(&acrtc->base);
-+
-+	}
-+
-+	drm_atomic_helper_wait_for_vblanks(dev, state);
-+
-+	/* In this state all old framebuffers would be unpinned */
-+
-+	drm_atomic_helper_cleanup_planes(dev, state);
-+
-+	drm_atomic_state_free(state);
-+
-+	return 0;
-+}
-+
-+int amdgpu_dm_atomic_check(struct drm_device *dev,
-+			    struct drm_atomic_state *s)
-+{
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *crtc_state;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *plane_state;
-+	struct drm_connector *connector;
-+	struct drm_connector_state *conn_state;
-+	int i, j, ret, set_count;
-+	struct dc_validation_set set[MAX_TARGET_NUM] = {{ 0 }};
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_connector *aconnector = NULL;
-+	set_count = 0;
-+
-+	ret = drm_atomic_helper_check(dev,s);
-+
-+	if (ret) {
-+		DRM_ERROR("Atomic state integrity validation failed with error :%d !\n",ret);
-+		return ret;
-+	}
-+
-+	ret = -EINVAL;
-+
-+	if (s->num_connector > MAX_TARGET_NUM) {
-+		DRM_ERROR("Exceeded max targets number !\n");
-+		return ret;
-+	}
-+
-+
-+	for_each_crtc_in_state(s, crtc, crtc_state, i) {
-+		enum dm_commit_action action;
-+		aconnector = NULL;
-+
-+		action = get_dm_commit_action(crtc, crtc_state);
-+		if (action == DM_COMMIT_ACTION_DPMS_OFF || DM_COMMIT_ACTION_RESET)
-+			continue;
-+
-+		for_each_connector_in_state(s, connector, conn_state, j) {
-+			if (conn_state->crtc && conn_state->crtc == crtc) {
-+				aconnector = to_amdgpu_connector(connector);
-+				/*I assume at most once connector for CRTC*/
-+				break;
-+			}
-+		}
-+
-+		/*In this case validate against existing connector if possible*/
-+		if (!aconnector)
-+			aconnector = aconnector_from_drm_crtc(crtc, s);
-+
-+		if (!aconnector || !aconnector->dc_sink)
-+			continue;
-+
-+		set[set_count].surface_count = 0;
-+		ret = dm_create_validation_set_for_target(&aconnector->base,
-+								&crtc_state->adjusted_mode, &set[set_count]);
-+		if (ret)
-+		{
-+			DRM_ERROR("Creation of validation set target failed !\n");
-+			goto end;
-+		}
-+
-+		for_each_plane_in_state(s, plane, plane_state, j) {
-+			/*Since we use drm_atomic_helper_set_config as our hook we garnteed to have the mask in correct state*/
-+			if (crtc_state->plane_mask & (1 << drm_plane_index(plane))) {
-+				if (set[set_count].surface_count == MAX_SURFACE_NUM) {
-+					DRM_ERROR("Exceeded max surfaces number per target!\n");
-+					ret = MODE_OK;
-+					goto end;
-+				}
-+
-+				ret = dm_add_surface_to_validation_set(plane,plane_state,
-+						(struct dc_surface **)&(set[set_count].surfaces[set[set_count].surface_count]));
-+
-+				if (ret) {
-+					DRM_ERROR("Failed to add surface  for validation!\n");
-+					goto end;
-+				}
-+
-+				set[set_count].surface_count++;
-+			}
-+		}
-+
-+		set_count++;
-+	}
-+
-+	if (!set_count || dc_validate_resources(adev->dm.dc, set, set_count)) {
-+		ret = MODE_OK;
-+	}
-+end:
-+
-+	for (i = 0; i < MAX_TARGET_NUM; i++) {
-+		if (set[i].target)
-+			dc_target_release((struct dc_target *)set[i].target);
-+	}
-+
-+	return ret;
-+
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-new file mode 100644
-index 0000000..bda39be
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -0,0 +1,96 @@
-+/*
-+ * Copyright 2012-13 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#ifndef __AMDGPU_DM_TYPES_H__
-+#define __AMDGPU_DM_TYPES_H__
-+
-+#include <drm/drmP.h>
-+
-+struct plane_addr_flip_info;
-+struct amdgpu_framebuffer;
-+struct amdgpu_display_manager;
-+struct dc_validation_set;
-+struct dc_surface;
-+
-+/*TODO Jodan Hersen use the one in amdgpu_dm*/
-+int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
-+			struct amdgpu_crtc *amdgpu_crtc,
-+			uint32_t link_index);
-+int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
-+			struct amdgpu_connector *amdgpu_connector,
-+			uint32_t link_index,
-+			struct amdgpu_encoder *amdgpu_encoder);
-+int amdgpu_dm_encoder_init(struct drm_device *dev,
-+			struct amdgpu_encoder *amdgpu_encoder,
-+			uint32_t link_index,
-+			struct amdgpu_crtc *amdgpu_crtc);
-+
-+void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
-+void amdgpu_dm_connector_destroy(struct drm_connector *connector);
-+void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);
-+
-+void dm_add_display_info(
-+	struct drm_display_info *disp_info,
-+	struct amdgpu_display_manager *dm,
-+	uint32_t display_index);
-+
-+int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
-+
-+struct amdgpu_connector *aconnector_from_drm_crtc(
-+		struct drm_crtc *crtc,
-+		struct drm_atomic_state *state);
-+
-+int amdgpu_dm_atomic_commit(
-+	struct drm_device *dev,
-+	struct drm_atomic_state *state,
-+	bool async);
-+int amdgpu_dm_atomic_check(struct drm_device *dev,
-+			    	struct drm_atomic_state *state);
-+
-+int dm_create_validation_set_for_target(
-+	struct drm_connector *connector,
-+	struct drm_display_mode *mode,
-+	struct dc_validation_set *val_set);
-+int dm_add_surface_to_validation_set(
-+	struct drm_plane *plane,
-+	struct drm_plane_state *state,
-+	struct dc_surface **surface);
-+
-+void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
-+struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
-+	struct drm_connector *connector);
-+void amdgpu_dm_connector_atomic_destroy_state(
-+	struct drm_connector *connector,
-+	struct drm_connector_state *state);
-+int amdgpu_dm_connector_atomic_set_property(
-+	struct drm_connector *connector,
-+	struct drm_connector_state *state,
-+	struct drm_property *property,
-+	uint64_t val);
-+
-+extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
-+
-+#endif		/* __AMDGPU_DM_TYPES_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0512-drm-amdgpu-Use-dal-driver-for-CZ.patch b/common/recipes-kernel/linux/files/0512-drm-amdgpu-Use-dal-driver-for-CZ.patch
deleted file mode 100644
index a37d3c91..00000000
--- a/common/recipes-kernel/linux/files/0512-drm-amdgpu-Use-dal-driver-for-CZ.patch
+++ /dev/null
@@ -1,496 +0,0 @@
-From 351b71a53a01276932fe2269c2bcbd5bf35da0f2 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 31 Mar 2016 17:45:07 -0400
-Subject: [PATCH 0512/1110] drm/amdgpu: Use dal driver for CZ
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Kconfig         |  1 +
- drivers/gpu/drm/amd/amdgpu/Makefile        | 18 +++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 12 +++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 34 ++++++++++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    |  4 ++
- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c     |  5 --
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c    | 11 +++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   | 51 +++++++++++++++-
- drivers/gpu/drm/amd/amdgpu/vi.c            | 96 +++++++++++++++++++++++++++++-
- 9 files changed, 216 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig
-index 7335c04..6b9dac8 100644
---- a/drivers/gpu/drm/amd/amdgpu/Kconfig
-+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
-@@ -25,3 +25,4 @@ config DRM_AMDGPU_GART_DEBUGFS
- 	  Selecting this option creates a debugfs file to inspect the mapped
- 	  pages. Uses more memory for housekeeping, enable only for debugging.
- 
-+source "drivers/gpu/drm/amd/dal/Kconfig"
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index dceebbb..3efc971 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -3,13 +3,18 @@
- # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
- 
- FULL_AMD_PATH=$(src)/..
-+DAL_FOLDER_NAME=dal
-+FULL_AMD_DAL_PATH = $(FULL_AMD_PATH)/$(DAL_FOLDER_NAME)
- 
- ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
- 	-I$(FULL_AMD_PATH)/include \
- 	-I$(FULL_AMD_PATH)/amdgpu \
- 	-I$(FULL_AMD_PATH)/scheduler \
- 	-I$(FULL_AMD_PATH)/powerplay/inc \
--	-I$(FULL_AMD_PATH)/acp/include
-+	-I$(FULL_AMD_PATH)/acp/include \
-+	-I$(FULL_AMD_DAL_PATH) \
-+	-I$(FULL_AMD_DAL_PATH)/include \
-+	-I$(FULL_AMD_DAL_PATH)/amdgpu_dm
- 
- amdgpu-y := amdgpu_drv.o
- 
-@@ -110,9 +115,18 @@ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
- amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
- amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
- 
-+ifneq ($(CONFIG_DRM_AMD_DAL),)
-+
-+RELATIVE_AMD_DAL_PATH = ../$(DAL_FOLDER_NAME)
-+include $(FULL_AMD_DAL_PATH)/Makefile
-+
-+amdgpu-y += $(AMD_DAL_FILES)
-+
-+endif
-+
- ifneq ($(CONFIG_DRM_AMD_POWERPLAY),)
- 
--include $(FULL_AMD_PATH)/powerplay/Makefile
-+include drivers/gpu/drm/amd/powerplay/Makefile
- 
- amdgpu-y += $(AMD_POWERPLAY_FILES)
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 06cf1eb..1e5dd09 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -52,8 +52,9 @@
- #include "amdgpu_irq.h"
- #include "amdgpu_ucode.h"
- #include "amdgpu_gds.h"
--#include "amd_powerplay.h"
- #include "amdgpu_acp.h"
-+#include "amdgpu_dm.h"
-+#include "amd_powerplay.h"
- 
- #include "gpu_scheduler.h"
- 
-@@ -82,6 +83,7 @@ extern int amdgpu_vm_size;
- extern int amdgpu_vm_block_size;
- extern int amdgpu_vm_fault_stop;
- extern int amdgpu_vm_debug;
-+extern int amdgpu_dal;
- extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
- extern int amdgpu_powerplay;
-@@ -2010,6 +2012,7 @@ struct amdgpu_device {
- 
- 	/* display */
- 	struct amdgpu_mode_info		mode_info;
-+	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
- 	struct work_struct		hotplug_work;
- 	struct amdgpu_irq_src		crtc_irq;
- 	struct amdgpu_irq_src		pageflip_irq;
-@@ -2056,6 +2059,9 @@ struct amdgpu_device {
- 	/* GDS */
- 	struct amdgpu_gds		gds;
- 
-+	/* display related functionality */
-+	struct amdgpu_display_manager dm;
-+
- 	const struct amdgpu_ip_block_version *ip_blocks;
- 	int				num_ip_blocks;
- 	struct amdgpu_ip_block_status	*ip_block_status;
-@@ -2090,7 +2096,7 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
- 
- u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
- void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
--
-+bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
- /*
-  * Registers read & write functions.
-  */
-@@ -2325,6 +2331,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- 
- #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
- 
-+#define amdgpu_has_dal_support(adev) (amdgpu_dal && amdgpu_device_has_dal_support(adev))
-+
- /* Common functions */
- int amdgpu_gpu_reset(struct amdgpu_device *adev);
- void amdgpu_pci_config_reset(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 8ff3286..fcfdf2d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1378,6 +1378,28 @@ static int amdgpu_resume(struct amdgpu_device *adev)
- 	return 0;
- }
- 
-+
-+/**
-+ * amdgpu_device_has_dal_support - check if dal is supported
-+ *
-+ * @adev: amdgpu_device_pointer
-+ *
-+ * Returns true for supported, false for not supported
-+ */
-+bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
-+{
-+
-+	switch(adev->asic_type) {
-+	case CHIP_CARRIZO:
-+#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+		return true;
-+#endif
-+	default:
-+		return false;
-+	}
-+}
-+
-+
- /**
-  * amdgpu_device_init - initialize the driver
-  *
-@@ -1529,8 +1551,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 		dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
- 		return r;
- 	}
-+
- 	/* init i2c buses */
--	amdgpu_atombios_i2c_init(adev);
-+	if (!amdgpu_has_dal_support(adev))
-+		amdgpu_atombios_i2c_init(adev);
- 
- 	/* Fence driver */
- 	r = amdgpu_fence_driver_init(adev);
-@@ -1630,7 +1654,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
- 	adev->ip_block_status = NULL;
- 	adev->accel_working = false;
- 	/* free i2c buses */
--	amdgpu_i2c_fini(adev);
-+	if (!amdgpu_has_dal_support(adev))
-+		amdgpu_i2c_fini(adev);
- 	amdgpu_atombios_fini(adev);
- 	kfree(adev->bios);
- 	adev->bios = NULL;
-@@ -1811,6 +1836,11 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- 	/* blat the mode back in */
- 	if (fbcon) {
- 		drm_helper_resume_force_mode(dev);
-+		if (!amdgpu_has_dal_support(adev)) {
-+			/* pre DCE11 */
-+			drm_helper_resume_force_mode(dev);
-+		}
-+
- 		/* turn on display hw */
- 		drm_modeset_lock_all(dev);
- 		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 943cdfb..97e5b69 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -77,6 +77,7 @@ int amdgpu_vm_block_size = -1;
- int amdgpu_vm_fault_stop = 0;
- int amdgpu_vm_debug = 0;
- int amdgpu_exp_hw_support = 0;
-+int amdgpu_dal = 1;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_powerplay = -1;
-@@ -149,6 +150,9 @@ module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
- MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
- module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
- 
-+MODULE_PARM_DESC(dal, "DAL display driver (1 = enable (default), 0 = disable)");
-+module_param_named(dal, amdgpu_dal, int, 0444);
-+
- MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
- module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-index 9191467..e694c99 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-@@ -42,11 +42,6 @@
-    this contains a helper + a amdgpu fb
-    the helper contains a pointer to amdgpu framebuffer baseclass.
- */
--struct amdgpu_fbdev {
--	struct drm_fb_helper helper;
--	struct amdgpu_framebuffer rfb;
--	struct amdgpu_device *adev;
--};
- 
- static struct fb_ops amdgpufb_ops = {
- 	.owner = THIS_MODULE,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 9266c7b..4fe38d7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -36,6 +36,10 @@
- 
- #include <linux/pm_runtime.h>
- 
-+#ifdef CONFIG_DRM_AMD_DAL
-+#include "amdgpu_dm_irq.h"
-+#endif
-+
- #define AMDGPU_WAIT_IDLE_TIMEOUT 200
- 
- /*
-@@ -232,7 +236,12 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
- 		}
- 	}
- 
--	INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
-+	if (!amdgpu_has_dal_support(adev)) {
-+		/* pre DCE11 */
-+		INIT_WORK(&adev->hotplug_work,
-+				amdgpu_hotplug_work_func);
-+	}
-+
- 	INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
- 
- 	adev->irq.installed = true;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 81bd964..d7b9c93 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -37,9 +37,12 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_plane_helper.h>
-+#include <drm/drm_fb_helper.h>
- #include <linux/i2c.h>
- #include <linux/i2c-algo-bit.h>
- 
-+#include <drm/drm_dp_mst_helper.h>
-+
- struct amdgpu_bo;
- struct amdgpu_device;
- struct amdgpu_encoder;
-@@ -305,6 +308,18 @@ struct amdgpu_display_funcs {
- 				 struct amdgpu_mode_mc_save *save);
- };
- 
-+struct amdgpu_framebuffer {
-+	struct drm_framebuffer base;
-+	struct drm_gem_object *obj;
-+};
-+
-+struct amdgpu_fbdev {
-+	struct drm_fb_helper helper;
-+	struct amdgpu_framebuffer rfb;
-+	struct list_head fbdev_list;
-+	struct amdgpu_device *adev;
-+};
-+
- struct amdgpu_mode_info {
- 	struct atom_context *atom_context;
- 	struct card_info *atom_card_info;
-@@ -409,6 +424,9 @@ struct amdgpu_crtc {
- 	u32 wm_high;
- 	u32 lb_vblank_lead_lines;
- 	struct drm_display_mode hw_mode;
-+
-+	/* After Set Mode target will be non-NULL */
-+	struct dc_target *target;
- };
- 
- struct amdgpu_encoder_atom_dig {
-@@ -498,6 +516,13 @@ enum amdgpu_connector_dither {
- 	AMDGPU_FMT_DITHER_ENABLE = 1,
- };
- 
-+struct amdgpu_dm_dp_aux {
-+	struct drm_dp_aux aux;
-+	uint32_t link_index;
-+};
-+
-+#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
-+
- struct amdgpu_connector {
- 	struct drm_connector base;
- 	uint32_t connector_id;
-@@ -509,6 +534,12 @@ struct amdgpu_connector {
- 	/* we need to mind the EDID between detect
- 	   and get modes due to analog/digital/tvencoder */
- 	struct edid *edid;
-+	/* number of modes generated from EDID at 'dc_sink' */
-+	int num_modes;
-+	/* The 'old' sink - before an HPD.
-+	 * The 'current' sink is in dc_link->sink. */
-+	const struct dc_sink *dc_sink;
-+	const struct dc_link *dc_link;
- 	void *con_priv;
- 	bool dac_load_detect;
- 	bool detected_by_load; /* if the connection status was determined by load */
-@@ -519,11 +550,25 @@ struct amdgpu_connector {
- 	enum amdgpu_connector_audio audio;
- 	enum amdgpu_connector_dither dither;
- 	unsigned pixelclock_for_modeset;
-+
-+	struct drm_dp_mst_topology_mgr mst_mgr;
-+	struct amdgpu_dm_dp_aux dm_dp_aux;
-+	struct drm_dp_mst_port *port;
-+	struct amdgpu_connector *mst_port;
-+	bool is_mst_connector;
-+	struct amdgpu_encoder *mst_encoder;
- };
- 
--struct amdgpu_framebuffer {
--	struct drm_framebuffer base;
--	struct drm_gem_object *obj;
-+/* TODO: start to use this struct and remove same field from base one */
-+struct amdgpu_mst_connector {
-+	struct amdgpu_connector base;
-+
-+	struct drm_dp_mst_topology_mgr mst_mgr;
-+	struct amdgpu_dm_dp_aux dm_dp_aux;
-+	struct drm_dp_mst_port *port;
-+	struct amdgpu_connector *mst_port;
-+	bool is_mst_connector;
-+	struct amdgpu_encoder *mst_encoder;
- };
- 
- #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index ddbb63a..c3b5ed6 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -73,10 +73,11 @@
- #include "uvd_v5_0.h"
- #include "uvd_v6_0.h"
- #include "vce_v3_0.h"
--#include "amdgpu_powerplay.h"
- #if defined(CONFIG_DRM_AMD_ACP)
- #include "amdgpu_acp.h"
- #endif
-+#include "amdgpu_dm.h"
-+#include "amdgpu_powerplay.h"
- 
- /*
-  * Indirect registers accessor
-@@ -984,6 +985,89 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] =
- #endif
- };
- 
-+/*
-+ * This is temporary. After we've gone through full testing with
-+ * DAL we want to remove dce_v11
-+ */
-+#if defined(CONFIG_DRM_AMD_DAL)
-+static const struct amdgpu_ip_block_version cz_ip_blocks_dal[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vi_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gmc_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cz_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 11,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_dm_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gfx_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &sdma_v3_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 6,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &uvd_v6_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vce_v3_0_ip_funcs,
-+	},
-+#if defined(CONFIG_DRM_AMD_ACP)
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_ACP,
-+		.major = 2,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &acp_ip_funcs,
-+	},
-+#endif
-+};
-+#endif
-+
- int vi_set_ip_blocks(struct amdgpu_device *adev)
- {
- 	switch (adev->asic_type) {
-@@ -1001,8 +1085,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
-+#if defined(CONFIG_DRM_AMD_DAL)
-+		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+			adev->ip_blocks = cz_ip_blocks_dal;
-+			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_dal);
-+		} else {
-+			adev->ip_blocks = cz_ip_blocks;
-+			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
-+		}
-+#else
- 		adev->ip_blocks = cz_ip_blocks;
- 		adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
-+#endif
- 		break;
- 	default:
- 		/* FIXME: not supported yet */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0513-drm-amdgpu-fix-build-failure-with-DAL-integrated.patch b/common/recipes-kernel/linux/files/0513-drm-amdgpu-fix-build-failure-with-DAL-integrated.patch
deleted file mode 100644
index 7192d1de..00000000
--- a/common/recipes-kernel/linux/files/0513-drm-amdgpu-fix-build-failure-with-DAL-integrated.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From ca5a882eac7883d9c602b39e0782630d4e2af343 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Fri, 27 Nov 2015 18:24:01 +0800
-Subject: [PATCH 0513/1110] drm/amdgpu: fix build failure with DAL integrated
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-By: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index 3efc971..948d8a6 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -14,6 +14,7 @@ ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
- 	-I$(FULL_AMD_PATH)/acp/include \
- 	-I$(FULL_AMD_DAL_PATH) \
- 	-I$(FULL_AMD_DAL_PATH)/include \
-+	-I$(FULL_AMD_DAL_PATH)/dc \
- 	-I$(FULL_AMD_DAL_PATH)/amdgpu_dm
- 
- amdgpu-y := amdgpu_drv.o
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0514-drm-amd-dal-Fix-64-bit-division-for-32-bit-systems.patch b/common/recipes-kernel/linux/files/0514-drm-amd-dal-Fix-64-bit-division-for-32-bit-systems.patch
deleted file mode 100644
index a0d9cf8d..00000000
--- a/common/recipes-kernel/linux/files/0514-drm-amd-dal-Fix-64-bit-division-for-32-bit-systems.patch
+++ /dev/null
@@ -1,167 +0,0 @@
-From 33d0d344aafaecd354bf9285ec0b32e00b5615a7 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 30 Nov 2015 13:43:52 -0500
-Subject: [PATCH 0514/1110] drm/amd/dal: Fix 64-bit division for 32-bit systems
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 28 +++++++++++++---------
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        |  9 +++----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  6 +++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/irq_types.h             |  2 +-
- 5 files changed, 28 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 68618bb..5c72a66 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -90,6 +90,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	const uint32_t low = 0;
- 
- 	uint32_t i, j, k;
-+	uint64_t remainder;
- 	struct bw_fixed yclk[3];
- 	struct bw_fixed sclk[3];
- 	bool d0_underlay_enable;
-@@ -1350,24 +1351,26 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		results->inefficient_underlay_pitch_in_pixels = bw_div(
- 			results->inefficient_linear_pitch_in_bytes,
- 			int_to_fixed(2));
--	} else
--	// case else
--	{
-+	} else {
- 		results->inefficient_underlay_pitch_in_pixels = bw_div(
- 			results->inefficient_linear_pitch_in_bytes,
- 			int_to_fixed(4));
- 	}
-+
-+	div64_u64_rem(mode_data->underlay_pitch_in_pixels.value,
-+			results->inefficient_underlay_pitch_in_pixels.value,
-+			&remainder);
-+
- 	if (mode_data->underlay_tiling_mode == linear
- 		&& vbios->scatter_gather_enable == true
--		&& mode_data->underlay_pitch_in_pixels.value
--			% results->inefficient_underlay_pitch_in_pixels.value
--			== false) {
-+		&& remainder == 0) {
- 		results->minimum_underlay_pitch_padding_recommended_for_efficiency =
- 			int_to_fixed(256);
- 	} else {
- 		results->minimum_underlay_pitch_padding_recommended_for_efficiency =
- 			int_to_fixed(0);
- 	}
-+
- 	results->cursor_total_data = int_to_fixed(0);
- 	results->cursor_total_request_groups = int_to_fixed(0);
- 	results->scatter_gather_total_pte_requests = int_to_fixed(0);
-@@ -1410,6 +1413,13 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		int_to_fixed(0);
- 	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
- 		if (results->enable[i]) {
-+			uint64_t arg1 = mul(results->pitch_in_pixels_after_surface_type[i],
-+						results->bytes_per_pixel[i]).value;
-+
-+			div64_u64_rem(arg1,
-+					results->inefficient_linear_pitch_in_bytes.value,
-+					&remainder);
-+
- 			if (results->scatter_gather_enable_for_pipe[i] == true
- 				&& tiling_mode[i] != def_linear) {
- 				results->bytes_per_page_close_open =
-@@ -1428,11 +1438,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 								results->scatter_gather_page_width[i])));
- 			} else if (results->scatter_gather_enable_for_pipe[i]
- 				== true && tiling_mode[i] == def_linear
--				&& (mul(
--					results->pitch_in_pixels_after_surface_type[i],
--					results->bytes_per_pixel[i])).value
--					% results->inefficient_linear_pitch_in_bytes.value
--					== false) {
-+				&& remainder == 0) {
- 				results->bytes_per_page_close_open =
- 					dceip->linear_mode_line_request_alternation_slice;
- 			} else {
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index 6bad7c6..1716808 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -92,8 +92,7 @@ struct bw_fixed frc_to_fixed(long long numerator, long long denominator)
- 
- 	arg1_value = abs_i64(numerator);
- 	arg2_value = abs_i64(denominator);
--	remainder = arg1_value % arg2_value;
--	res_value = arg1_value / arg2_value;
-+	res_value = div64_u64_rem(arg1_value, arg2_value, &remainder);
- 
- 	ASSERT(res_value <= MAX_I32);
- 
-@@ -144,7 +143,8 @@ struct bw_fixed bw_max(const struct bw_fixed arg1, const struct bw_fixed arg2)
- struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed significance)
- {
- 	struct bw_fixed result;
--	signed long long multiplicand = arg.value / abs_i64(significance.value);
-+	int64_t multiplicand;
-+	multiplicand = div64_u64(arg.value, abs_i64(significance.value));
- 	result.value = abs_i64(significance.value) * multiplicand;
- 	ASSERT(abs_i64(result.value) <= abs_i64(arg.value));
- 	return result;
-@@ -153,7 +153,8 @@ struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed signif
- struct bw_fixed bw_ceil(const struct bw_fixed arg, const struct bw_fixed significance)
- {
- 	struct bw_fixed result;
--	result.value = arg.value + arg.value % abs_i64(significance.value);
-+	div64_u64_rem(arg.value, abs_i64(significance.value), &result.value);
-+	result.value += arg.value;
- 	if (result.value < significance.value)
- 		result.value = significance.value;
- 	return result;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 5803e22..082fb02 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -277,8 +277,10 @@ static void calculate_scaling_ratios(
- 					== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
- 		stream->ratios.vert.value *= 2;
- 
--	stream->ratios.vert.value = stream->ratios.vert.value * in_h / out_h;
--	stream->ratios.horz.value = stream->ratios.horz.value * in_w / out_w;
-+	stream->ratios.vert.value = div64_u64(stream->ratios.vert.value * in_h,
-+			out_h);
-+	stream->ratios.horz.value = div64_u64(stream->ratios.horz.value * in_w ,
-+			out_w);
- 
- 	stream->ratios.horz_c = stream->ratios.horz;
- 	stream->ratios.vert_c = stream->ratios.vert;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 7391a0a..50354a9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -705,7 +705,7 @@ void dce110_program_urgency_watermark(
- 	uint32_t pstate_blackout_duration_ns)
- {
- 	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
--	uint32_t total_dest_line_time_ns = 1000000ULL * h_total
-+	uint32_t total_dest_line_time_ns = 1000000UL * h_total
- 		/ pixel_clk_in_khz + pstate_blackout_duration_ns;
- 
- 	program_urgency_watermark(
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq_types.h b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-index 051a1f6..35a0991 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-@@ -178,7 +178,7 @@ enum dc_interrupt_porlarity {
- 	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
- 
- struct dc_timer_interrupt_params {
--	uint64_t micro_sec_interval;
-+	uint32_t micro_sec_interval;
- 	enum dc_interrupt_context int_context;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0515-drm-amd-dal-Use-fixed-types-instead-of-int-long-long.patch b/common/recipes-kernel/linux/files/0515-drm-amd-dal-Use-fixed-types-instead-of-int-long-long.patch
deleted file mode 100644
index 92035617..00000000
--- a/common/recipes-kernel/linux/files/0515-drm-amd-dal-Use-fixed-types-instead-of-int-long-long.patch
+++ /dev/null
@@ -1,206 +0,0 @@
-From c2e2413d4fcb76a00edca5fe7c9ae5121240af31 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 30 Nov 2015 13:59:48 -0500
-Subject: [PATCH 0515/1110] drm/amd/dal: Use fixed types instead of
- int/long/long long
-
-To keep code consistent and particularly with fixed point calcs, we want
-to use uint32_t and uint64_t instead of the common int/long/long long
-types.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c | 56 ++++++++++++++---------------
- drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h   |  8 ++---
- 2 files changed, 32 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index 1716808..8bdd0fb 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -29,16 +29,16 @@
- #define BITS_PER_FRACTIONAL_PART 24
- 
- #define MIN_I32 \
--	(long long)(-(1LL << (63 - BITS_PER_FRACTIONAL_PART)))
-+	(int64_t)(-(1LL << (63 - BITS_PER_FRACTIONAL_PART)))
- 
- #define MAX_I32 \
--	(long long)((1ULL << (63 - BITS_PER_FRACTIONAL_PART)) - 1)
-+	(int64_t)((1ULL << (63 - BITS_PER_FRACTIONAL_PART)) - 1)
- 
- #define MIN_I64 \
--	(long long)(-(1LL << 63))
-+	(int64_t)(-(1LL << 63))
- 
- #define MAX_I64 \
--	(long long)((1ULL << 63) - 1)
-+	(int64_t)((1ULL << 63) - 1)
- 
- 
- #define FRACTIONAL_PART_MASK \
-@@ -50,12 +50,12 @@
- #define GET_FRACTIONAL_PART(x) \
- 	(FRACTIONAL_PART_MASK & (x))
- 
--static unsigned long long abs_i64(long long arg)
-+static uint64_t abs_i64(int64_t arg)
- {
- 	if (arg >= 0)
--		return (unsigned long long)(arg);
-+		return (uint64_t)(arg);
- 	else
--		return (unsigned long long)(-arg);
-+		return (uint64_t)(-arg);
- }
- 
- struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3)
-@@ -68,7 +68,7 @@ struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed
- 	return bw_max(bw_max(v1, v2), v3);
- }
- 
--struct bw_fixed int_to_fixed(long long value)
-+struct bw_fixed int_to_fixed(int64_t value)
- {
- 	struct bw_fixed res;
- 	ASSERT(value < MAX_I32 && value > MIN_I32);
-@@ -76,17 +76,17 @@ struct bw_fixed int_to_fixed(long long value)
- 	return res;
- }
- 
--struct bw_fixed frc_to_fixed(long long numerator, long long denominator)
-+struct bw_fixed frc_to_fixed(int64_t numerator, int64_t denominator)
- {
- 	struct bw_fixed res;
- 	bool arg1_negative = numerator < 0;
- 	bool arg2_negative = denominator < 0;
--	unsigned long long arg1_value;
--	unsigned long long arg2_value;
--	unsigned long long remainder;
-+	uint64_t arg1_value;
-+	uint64_t arg2_value;
-+	uint64_t remainder;
- 
- 	/* determine integer part */
--	unsigned long long res_value;
-+	uint64_t res_value;
- 
- 	ASSERT(denominator != 0);
- 
-@@ -98,7 +98,7 @@ struct bw_fixed frc_to_fixed(long long numerator, long long denominator)
- 
- 	/* determine fractional part */
- 	{
--		unsigned int i = BITS_PER_FRACTIONAL_PART;
-+		uint32_t i = BITS_PER_FRACTIONAL_PART;
- 
- 		do
- 		{
-@@ -116,14 +116,14 @@ struct bw_fixed frc_to_fixed(long long numerator, long long denominator)
- 
- 	/* round up LSB */
- 	{
--		unsigned long long summand = (remainder << 1) >= arg2_value;
-+		uint64_t summand = (remainder << 1) >= arg2_value;
- 
- 		ASSERT(res_value <= MAX_I64 - summand);
- 
- 		res_value += summand;
- 	}
- 
--	res.value = (signed long long)(res_value);
-+	res.value = (int64_t)(res_value);
- 
- 	if (arg1_negative ^ arg2_negative)
- 		res.value = -res.value;
-@@ -185,16 +185,16 @@ struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 	bool arg1_negative = arg1.value < 0;
- 	bool arg2_negative = arg2.value < 0;
- 
--	unsigned long long arg1_value = abs_i64(arg1.value);
--	unsigned long long arg2_value = abs_i64(arg2.value);
-+	uint64_t arg1_value = abs_i64(arg1.value);
-+	uint64_t arg2_value = abs_i64(arg2.value);
- 
--	unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);
--	unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);
-+	uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
-+	uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
- 
--	unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);
--	unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);
-+	uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
-+	uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
- 
--	unsigned long long tmp;
-+	uint64_t tmp;
- 
- 	res.value = arg1_int * arg2_int;
- 
-@@ -204,22 +204,22 @@ struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 
- 	tmp = arg1_int * arg2_fra;
- 
--	ASSERT(tmp <= (unsigned long long)(MAX_I64 - res.value));
-+	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
- 
- 	res.value += tmp;
- 
- 	tmp = arg2_int * arg1_fra;
- 
--	ASSERT(tmp <= (unsigned long long)(MAX_I64 - res.value));
-+	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
- 
- 	res.value += tmp;
- 
- 	tmp = arg1_fra * arg2_fra;
- 
- 	tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
--		(tmp >= (unsigned long long)(frc_to_fixed(1, 2).value));
-+		(tmp >= (uint64_t)(frc_to_fixed(1, 2).value));
- 
--	ASSERT(tmp <= (unsigned long long)(MAX_I64 - res.value));
-+	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
- 
- 	res.value += tmp;
- 
-@@ -234,7 +234,7 @@ struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 	return res;
- }
- 
--struct bw_fixed fixed31_32_to_bw_fixed(long long raw)
-+struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw)
- {
- 	struct bw_fixed result = { 0 };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-index f9e267b..254cf76 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-@@ -27,18 +27,18 @@
- #define BW_FIXED_H_
- 
- struct bw_fixed {
--	signed long long value;
-+	int64_t value;
- };
- 
- struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3);
- 
- struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3);
- 
--struct bw_fixed int_to_fixed(long long value);
-+struct bw_fixed int_to_fixed(int64_t value);
- 
--struct bw_fixed frc_to_fixed(long long num, long long denum);
-+struct bw_fixed frc_to_fixed(int64_t num, int64_t denum);
- 
--struct bw_fixed fixed31_32_to_bw_fixed(long long raw);
-+struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw);
- 
- struct bw_fixed add(const struct bw_fixed arg1, const struct bw_fixed arg2);
- struct bw_fixed sub(const struct bw_fixed arg1, const struct bw_fixed arg2);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0516-drm-amd-dal-delay-mst-detection-start-till-first-drm.patch b/common/recipes-kernel/linux/files/0516-drm-amd-dal-delay-mst-detection-start-till-first-drm.patch
deleted file mode 100644
index 674c72dc..00000000
--- a/common/recipes-kernel/linux/files/0516-drm-amd-dal-delay-mst-detection-start-till-first-drm.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 5e1f831ea1b826f9f20e566ec5ac820f5ef0f696 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 24 Nov 2015 17:30:44 +0800
-Subject: [PATCH 0516/1110] drm/amd/dal: delay mst detection start till first
- drm detect
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c | 8 ++++----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c   | 8 +++++++-
- 2 files changed, 11 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index beaef70..c3b6715 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -331,8 +331,7 @@ bool dc_helpers_dp_mst_start_top_mgr(
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
--	if (aconnector)
--		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
-+	aconnector->is_mst_connector = true;
- 
- 	return true;
- }
-@@ -345,6 +344,7 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
--	if (aconnector)
--		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+	drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+
-+	aconnector->is_mst_connector = false;
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index bfff48c..59a6a28 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1002,8 +1002,14 @@ amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
- 	 * TODO: check whether we should lock here for mst_mgr.lock
- 	 */
- 	/* set root connector to disconnected */
--	if (aconnector->mst_mgr.mst_state)
-+	if (aconnector->is_mst_connector) {
-+		if (!aconnector->mst_mgr.mst_state)
-+			drm_dp_mst_topology_mgr_set_mst(
-+				&aconnector->mst_mgr,
-+				true);
-+
- 		return connector_status_disconnected;
-+	}
- 
- 	connected = (NULL != aconnector->dc_sink);
- 	return (connected ? connector_status_connected :
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0517-drm-amd-dal-Allocate-encoder-possible_crtc-mask-corr.patch b/common/recipes-kernel/linux/files/0517-drm-amd-dal-Allocate-encoder-possible_crtc-mask-corr.patch
deleted file mode 100644
index 063775dd..00000000
--- a/common/recipes-kernel/linux/files/0517-drm-amd-dal-Allocate-encoder-possible_crtc-mask-corr.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From f0fda369b2f606335085d005aac502fc003e1b7e Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 24 Nov 2015 16:52:36 -0500
-Subject: [PATCH 0517/1110] drm/amd/dal: Allocate encoder->possible_crtc mask
- correctly.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 6d9ee15..0838cca 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -239,8 +239,6 @@ dm_dp_create_fake_mst_encoder(struct amdgpu_connector *connector)
- 		break;
- 	}
- 
--	encoder->possible_crtcs = 0x1;
--
- 	drm_encoder_init(
- 		dev,
- 		&amdgpu_encoder->base,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0518-drm-amd-dal-Reorganize-link-encoder-and-stream-encod.patch b/common/recipes-kernel/linux/files/0518-drm-amd-dal-Reorganize-link-encoder-and-stream-encod.patch
deleted file mode 100644
index 5f22ada6..00000000
--- a/common/recipes-kernel/linux/files/0518-drm-amd-dal-Reorganize-link-encoder-and-stream-encod.patch
+++ /dev/null
@@ -1,1691 +0,0 @@
-From 2e6975280175f40d209cc2e86c1141a9a61fe23b Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 25 Nov 2015 11:14:09 -0500
-Subject: [PATCH 0518/1110] drm/amd/dal: Reorganize link encoder and stream
- encoder interface function order
-
-Part of link encoder & stream encoder clean-up. No functionality change.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 1103 ++++++++++----------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |   41 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  |  335 +++---
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |   18 +-
- 4 files changed, 750 insertions(+), 747 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 0297bd3..9817318 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -461,45 +461,6 @@ static void set_dp_phy_pattern_80bit_custom(
- 	enable_phy_bypass_mode(ctx, be_addr_offset, true);
- }
- 
--void dce110_link_encoder_setup(
--	struct link_encoder *enc,
--	enum signal_type signal)
--{
--	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
--	uint32_t value = dal_read_reg(enc->ctx, addr);
--
--	switch (signal) {
--	case SIGNAL_TYPE_EDP:
--	case SIGNAL_TYPE_DISPLAY_PORT:
--		/* DP SST */
--		set_reg_field_value(value, 0, DIG_BE_CNTL, DIG_MODE);
--		break;
--	case SIGNAL_TYPE_LVDS:
--		/* LVDS */
--		set_reg_field_value(value, 1, DIG_BE_CNTL, DIG_MODE);
--		break;
--	case SIGNAL_TYPE_DVI_SINGLE_LINK:
--	case SIGNAL_TYPE_DVI_DUAL_LINK:
--		/* TMDS-DVI */
--		set_reg_field_value(value, 2, DIG_BE_CNTL, DIG_MODE);
--		break;
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--		/* TMDS-HDMI */
--		set_reg_field_value(value, 3, DIG_BE_CNTL, DIG_MODE);
--		break;
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--		/* DP MST */
--		set_reg_field_value(value, 5, DIG_BE_CNTL, DIG_MODE);
--		break;
--	default:
--		ASSERT_CRITICAL(false);
--		/* invalid mode ! */
--		break;
--	}
--
--	dal_write_reg(enc->ctx, addr, value);
--}
--
- static void set_dp_phy_pattern_hbr2_compliance(
- 	struct link_encoder *enc,
- 	const int32_t be_addr_offset)
-@@ -751,137 +712,6 @@ static void construct(
- 			FEATURE_SUPPORT_DP_YUV);
- }
- 
--struct link_encoder *dce110_link_encoder_create(
--	const struct encoder_init_data *init)
--{
--	struct link_encoder *enc =
--		dc_service_alloc(init->ctx, sizeof(struct link_encoder));
--
--	if (!enc)
--		goto enc_create_fail;
--
--	construct(enc, init);
--
--	return enc;
--
--enc_create_fail:
--	return NULL;
--}
--
--void dce110_link_encoder_destroy(struct link_encoder **enc)
--{
--	struct link_encoder *encoder = *enc;
--	dc_service_free(encoder->ctx, encoder);
--	*enc = NULL;
--}
--
--void dce110_link_encoder_set_dp_phy_pattern(
--	struct link_encoder *enc,
--	const struct encoder_set_dp_phy_pattern_param *param)
--{
--	const int32_t offset = enc->be_engine_offset;
--
--
--	switch (param->dp_phy_pattern) {
--	case DP_TEST_PATTERN_TRAINING_PATTERN1:
--		set_dp_phy_pattern_training_pattern(enc->ctx,
--			offset, 0);
--		break;
--	case DP_TEST_PATTERN_TRAINING_PATTERN2:
--		set_dp_phy_pattern_training_pattern(enc->ctx,
--			offset, 1);
--		break;
--	case DP_TEST_PATTERN_TRAINING_PATTERN3:
--		set_dp_phy_pattern_training_pattern(enc->ctx,
--			offset, 2);
--		break;
--	case DP_TEST_PATTERN_D102:
--		set_dp_phy_pattern_d102(enc->ctx, offset);
--		break;
--	case DP_TEST_PATTERN_SYMBOL_ERROR:
--		set_dp_phy_pattern_symbol_error(enc->ctx, offset);
--		break;
--	case DP_TEST_PATTERN_PRBS7:
--		set_dp_phy_pattern_prbs7(enc->ctx, offset);
--		break;
--	case DP_TEST_PATTERN_80BIT_CUSTOM:
--		set_dp_phy_pattern_80bit_custom(
--				enc->ctx,
--			offset, param->custom_pattern);
--		break;
--	case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
--		set_dp_phy_pattern_hbr2_compliance(
--			enc, offset);
--		break;
--	case DP_TEST_PATTERN_VIDEO_MODE: {
--		set_dp_phy_pattern_passthrough_mode(
--			enc->ctx,
--			offset,
--			param->dp_panel_mode);
--		break;
--	}
--
--
--	default:
--		/* invalid phy pattern */
--		ASSERT_CRITICAL(false);
--		break;
--	}
--}
--
--enum encoder_result dce110_link_encoder_dp_set_lane_settings(
--	struct link_encoder *enc,
--	const struct link_training_settings *link_settings)
--{
--	union dpcd_training_lane_set training_lane_set = { { 0 } };
--
--	int32_t lane = 0;
--
--	struct bp_transmitter_control cntl = { 0 };
--
--	if (!link_settings) {
--		BREAK_TO_DEBUGGER();
--		return ENCODER_RESULT_ERROR;
--	}
--
--	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
--	cntl.transmitter = enc->transmitter;
--	cntl.connector_obj_id = enc->connector;
--	cntl.lanes_number = link_settings->link_settings.lane_count;
--	cntl.hpd_sel = enc->hpd_source;
--	cntl.pixel_clock = link_settings->link_settings.link_rate *
--						LINK_RATE_REF_FREQ_IN_KHZ;
--
--	for (lane = 0; lane < link_settings->link_settings.lane_count; ++lane) {
--		/* translate lane settings */
--
--		training_lane_set.bits.VOLTAGE_SWING_SET =
--			link_settings->lane_settings[lane].VOLTAGE_SWING;
--		training_lane_set.bits.PRE_EMPHASIS_SET =
--			link_settings->lane_settings[lane].PRE_EMPHASIS;
--
--		/* post cursor 2 setting only applies to HBR2 link rate */
--		if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
--			/* this is passed to VBIOS
--			 * to program post cursor 2 level */
--
--			training_lane_set.bits.POST_CURSOR2_SET =
--				link_settings->lane_settings[lane].POST_CURSOR2;
--		}
--
--		cntl.lane_select = lane;
--		cntl.lane_settings = training_lane_set.raw;
--
--		/* call VBIOS table to set voltage swing and pre-emphasis */
--
--		dal_bios_parser_transmitter_control(
--			dal_adapter_service_get_bios_parser(
--				enc->adapter_service), &cntl);
--	}
--
--	return ENCODER_RESULT_OK;
--}
--
- /* return value is bit-vector */
- static uint8_t get_frontend_source(
- 	enum engine_id engine)
-@@ -1167,72 +997,6 @@ static enum encoder_result link_encoder_edp_backlight_control(
- 	return ENCODER_RESULT_OK;
- }
- 
--/*
-- * @brief
-- * Configure digital transmitter and enable both encoder and transmitter
-- * Actual output will be available after calling unblank()
-- */
--enum encoder_result dce110_link_encoder_enable_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum engine_id engine,
--	enum clock_source_id clock_source,
--	enum signal_type signal,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock)
--{
--	struct bp_transmitter_control cntl = { 0 };
--
--	if (enc->connector.id == CONNECTOR_ID_EDP) {
--		/* power up eDP panel */
--
--		link_encoder_edp_power_control(
--			enc, true);
--
--		link_encoder_edp_wait_for_hpd_ready(
--			enc, enc->connector, true);
--
--		/* have to turn off the backlight
--		 * before power down eDP panel */
--		link_encoder_edp_backlight_control(
--				enc, true);
--	}
--
--	/* Enable the PHY */
--
--	/* number_of_lanes is used for pixel clock adjust,
--	 * but it's not passed to asic_control.
--	 * We need to set number of lanes manually. */
--	if (dc_is_dp_signal(signal))
--		configure_encoder(enc, engine, link_settings);
--
--	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = engine;
--	cntl.transmitter = enc->transmitter;
--	cntl.pll_id = clock_source;
--	cntl.signal = signal;
--	cntl.lanes_number = link_settings->lane_count;
--	cntl.hpd_sel = enc->hpd_source;
--	if (dc_is_dp_signal(signal))
--		cntl.pixel_clock = link_settings->link_rate
--						* LINK_RATE_REF_FREQ_IN_KHZ;
--	else
--		cntl.pixel_clock = pixel_clock;
--	cntl.color_depth = color_depth;
--
--	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
--		dc_service_sleep_in_milliseconds(
--			enc->ctx,
--			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
--
--	dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc->adapter_service),
--		&cntl);
--
--	return ENCODER_RESULT_OK;
--}
--
- static bool is_dig_enabled(const struct link_encoder *link_enc)
- {
- 	uint32_t value;
-@@ -1268,141 +1032,18 @@ static void link_encoder_disable(struct link_encoder *link_enc)
- 	dal_write_reg(link_enc->ctx, addr, value);
- }
- 
--/*
-- * @brief
-- * Disable transmitter and its encoder
-- */
--enum encoder_result dce110_link_encoder_disable_output(
--	struct link_encoder *link_enc,
--	enum signal_type signal)
-+static void hpd_initialize(
-+	struct link_encoder *enc,
-+	enum hpd_source_id hpd_source)
- {
--	struct bp_transmitter_control cntl = { 0 };
--
--	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
--		/* have to turn off the backlight
--		 * before power down eDP panel */
--		link_encoder_edp_backlight_control(
--				link_enc, false);
--	}
--
--	if (!is_dig_enabled(link_enc) &&
--		dal_adapter_service_should_optimize(link_enc->adapter_service,
--					OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
--		return ENCODER_RESULT_OK;
--	}
--	/* Power-down RX and disable GPU PHY should be paired.
--	 * Disabling PHY without powering down RX may cause
--	 * symbol lock loss, on which we will get DP Sink interrupt. */
--
--	/* There is a case for the DP active dongles
--	 * where we want to disable the PHY but keep RX powered,
--	 * for those we need to ignore DP Sink interrupt
--	 * by checking lane count that has been set
--	 * on the last do_enable_output(). */
--
--	/* disable transmitter */
--	cntl.action = TRANSMITTER_CONTROL_DISABLE;
--	cntl.transmitter = link_enc->transmitter;
--	cntl.hpd_sel = link_enc->hpd_source;
--	cntl.signal = signal;
--	cntl.connector_obj_id = link_enc->connector;
--
--	dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			link_enc->adapter_service), &cntl);
--
--	/* disable encoder */
--	if (dc_is_dp_signal(signal))
--		link_encoder_disable(link_enc);
--
--	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
--		/* power down eDP panel */
--		/* TODO: Power control cause regression, we should implement
--		 * it properly, for now just comment it.
--		 *
--		 * link_encoder_edp_wait_for_hpd_ready(
--			link_enc,
--			link_enc->connector,
--			false);
--
--		 * link_encoder_edp_power_control(
--				link_enc, false); */
--	}
--
--	return ENCODER_RESULT_OK;
--}
--
--static void hpd_initialize(
--	struct link_encoder *enc,
--	enum hpd_source_id hpd_source)
--{
--	/* Associate HPD with DIG_BE */
--	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
--	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	/* Associate HPD with DIG_BE */
-+	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, DIG_BE_CNTL, DIG_HPD_SELECT);
- 	dal_write_reg(enc->ctx, addr, value);
- }
- 
--enum encoder_result dce110_link_encoder_power_up(
--	struct link_encoder *enc)
--{
--	struct bp_transmitter_control cntl = { 0 };
--
--	enum bp_result result;
--
--	cntl.action = TRANSMITTER_CONTROL_INIT;
--	cntl.engine_id = ENGINE_ID_UNKNOWN;
--	cntl.transmitter = enc->transmitter;
--	cntl.connector_obj_id = enc->connector;
--	cntl.lanes_number = LANE_COUNT_FOUR;
--	cntl.coherent = false;
--	cntl.hpd_sel = enc->hpd_source;
--
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc->adapter_service),
--		&cntl);
--
--	if (result != BP_RESULT_OK) {
--		dal_logger_write(enc->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_ENCODER,
--			"%s: Failed to execute VBIOS command table!\n",
--			__func__);
--		BREAK_TO_DEBUGGER();
--		return ENCODER_RESULT_ERROR;
--	}
--
--	if (enc->connector.id == CONNECTOR_ID_LVDS) {
--		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
--
--		result = dal_bios_parser_transmitter_control(
--			dal_adapter_service_get_bios_parser(
--				enc->adapter_service),
--			&cntl);
--		ASSERT(result == BP_RESULT_OK);
--
--	} else if (enc->connector.id == CONNECTOR_ID_EDP) {
--		link_encoder_edp_power_control(enc, true);
--
--		link_encoder_edp_wait_for_hpd_ready(
--			enc, enc->connector, true);
--
--	}
--	aux_initialize(enc, enc->hpd_source);
--
--	/* reinitialize HPD.
--	 * hpd_initialize() will pass DIG_FE id to HW context.
--	 * All other routine within HW context will use fe_engine_offset
--	 * as DIG_FE id even caller pass DIG_FE id.
--	 * So this routine must be called first. */
--	hpd_initialize(enc, enc->hpd_source);
--
--	return ENCODER_RESULT_OK;
--}
--
--
- static bool validate_dvi_output(
- 	const struct link_encoder *enc,
- 	enum signal_type connector_signal,
-@@ -1569,6 +1210,31 @@ static bool validate_wireless_output(
- 	return false;
- }
- 
-+struct link_encoder *dce110_link_encoder_create(
-+	const struct encoder_init_data *init)
-+{
-+	struct link_encoder *enc =
-+		dc_service_alloc(init->ctx, sizeof(struct link_encoder));
-+
-+	if (!enc)
-+		goto enc_create_fail;
-+
-+	construct(enc, init);
-+
-+	return enc;
-+
-+enc_create_fail:
-+	return NULL;
-+}
-+
-+void dce110_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	struct link_encoder *encoder = *enc;
-+
-+	dc_service_free(encoder->ctx, encoder);
-+	*enc = NULL;
-+}
-+
- enum encoder_result dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream)
-@@ -1614,84 +1280,540 @@ enum encoder_result dce110_link_encoder_validate_output_with_stream(
- 	return is_valid ? ENCODER_RESULT_OK : ENCODER_RESULT_ERROR;
- }
- 
--/*
-- * get_supported_stream_engines
-- *
-- * @brief
-- * get a list of supported engine
-- *
-- * @param
-- * const struct encoder_impl *enc - not used.
-- *
-- * @return
-- * list of engines with supported ones enabled.
-- */
--union supported_stream_engines dce110_get_supported_stream_engines(
--	const struct link_encoder *enc)
-+enum encoder_result dce110_link_encoder_power_up(
-+	struct link_encoder *enc)
- {
--	union supported_stream_engines result = {.u_all = 0};
--
--	result.engine.ENGINE_ID_DIGA = 1;
--	result.engine.ENGINE_ID_DIGB = 1;
--	result.engine.ENGINE_ID_DIGC = 1;
-+	struct bp_transmitter_control cntl = { 0 };
- 
--	if (enc->connector.id == CONNECTOR_ID_EDP /*|| wireless*/)
--		result.u_all = (1 << enc->preferred_engine);
-+	enum bp_result result;
- 
--	return result;
--}
-+	cntl.action = TRANSMITTER_CONTROL_INIT;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.connector_obj_id = enc->connector;
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.coherent = false;
-+	cntl.hpd_sel = enc->hpd_source;
- 
--void dce110_link_encoder_set_lcd_backlight_level(
--	struct link_encoder *enc,
--	uint32_t level)
--{
--	struct dc_context *ctx = enc->ctx;
-+	result = dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc->adapter_service),
-+		&cntl);
- 
--	const uint32_t backlight_update_pending_max_retry = 1000;
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(enc->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_RESULT_ERROR;
-+	}
- 
--	uint32_t backlight;
--	uint32_t backlight_period;
--	uint32_t backlight_lock;
-+	if (enc->connector.id == CONNECTOR_ID_LVDS) {
-+		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
- 
--	uint32_t i;
--	uint32_t backlight_24bit;
--	uint32_t backlight_17bit;
--	uint32_t backlight_16bit;
--	uint32_t masked_pwm_period;
--	uint8_t rounding_bit;
--	uint8_t bit_count;
--	uint64_t active_duty_cycle;
-+		result = dal_bios_parser_transmitter_control(
-+			dal_adapter_service_get_bios_parser(
-+				enc->adapter_service),
-+			&cntl);
-+		ASSERT(result == BP_RESULT_OK);
- 
--	backlight = dal_read_reg(ctx, mmBL_PWM_CNTL);
--	backlight_period = dal_read_reg(ctx, mmBL_PWM_PERIOD_CNTL);
--	backlight_lock = dal_read_reg(ctx, mmBL_PWM_GRP1_REG_LOCK);
-+	} else if (enc->connector.id == CONNECTOR_ID_EDP) {
-+		link_encoder_edp_power_control(enc, true);
- 
--	/*
--	 * 1. Convert 8-bit value to 17 bit U1.16 format
--	 * (1 integer, 16 fractional bits)
--	 */
-+		link_encoder_edp_wait_for_hpd_ready(
-+			enc, enc->connector, true);
- 
--	/* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
--	 * effectively multiplying value by 256/255
--	 * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
--	 */
--	backlight_24bit = level * 0x10101;
-+	}
-+	aux_initialize(enc, enc->hpd_source);
- 
--	/* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
--	 * used for rounding, take most significant bit of fraction for
--	 * rounding, e.g. for 0xEFEFEF, rounding bit is 1
--	 */
--	rounding_bit = (backlight_24bit >> 7) & 1;
-+	/* reinitialize HPD.
-+	 * hpd_initialize() will pass DIG_FE id to HW context.
-+	 * All other routine within HW context will use fe_engine_offset
-+	 * as DIG_FE id even caller pass DIG_FE id.
-+	 * So this routine must be called first. */
-+	hpd_initialize(enc, enc->hpd_source);
- 
--	/* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
--	 * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
--	 */
--	backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
-+	return ENCODER_RESULT_OK;
-+}
- 
--	/*
--	 * 2. Find  16 bit backlight active duty cycle, where 0 <= backlight
--	 * active duty cycle <= backlight period
--	 */
-+void dce110_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal)
-+{
-+	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		/* DP SST */
-+		set_reg_field_value(value, 0, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		/* LVDS */
-+		set_reg_field_value(value, 1, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		/* TMDS-DVI */
-+		set_reg_field_value(value, 2, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/* TMDS-HDMI */
-+		set_reg_field_value(value, 3, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* DP MST */
-+		set_reg_field_value(value, 5, DIG_BE_CNTL, DIG_MODE);
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		/* invalid mode ! */
-+		break;
-+	}
-+
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
-+/*
-+ * @brief
-+ * Configure digital transmitter and enable both encoder and transmitter
-+ * Actual output will be available after calling unblank()
-+ */
-+enum encoder_result dce110_link_encoder_enable_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum engine_id engine,
-+	enum clock_source_id clock_source,
-+	enum signal_type signal,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* power up eDP panel */
-+
-+		link_encoder_edp_power_control(
-+			enc, true);
-+
-+		link_encoder_edp_wait_for_hpd_ready(
-+			enc, enc->connector, true);
-+
-+		/* have to turn off the backlight
-+		 * before power down eDP panel */
-+		link_encoder_edp_backlight_control(
-+				enc, true);
-+	}
-+
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually. */
-+	if (dc_is_dp_signal(signal))
-+		configure_encoder(enc, engine, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = engine;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = signal;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc->hpd_source;
-+	if (dc_is_dp_signal(signal))
-+		cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	else
-+		cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
-+		dc_service_sleep_in_milliseconds(
-+			enc->ctx,
-+			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
-+
-+	dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc->adapter_service),
-+		&cntl);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+/*
-+ * @brief
-+ * Disable transmitter and its encoder
-+ */
-+enum encoder_result dce110_link_encoder_disable_output(
-+	struct link_encoder *link_enc,
-+	enum signal_type signal)
-+{
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* have to turn off the backlight
-+		 * before power down eDP panel */
-+		link_encoder_edp_backlight_control(
-+				link_enc, false);
-+	}
-+
-+	if (!is_dig_enabled(link_enc) &&
-+		dal_adapter_service_should_optimize(link_enc->adapter_service,
-+					OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
-+		return ENCODER_RESULT_OK;
-+	}
-+	/* Power-down RX and disable GPU PHY should be paired.
-+	 * Disabling PHY without powering down RX may cause
-+	 * symbol lock loss, on which we will get DP Sink interrupt. */
-+
-+	/* There is a case for the DP active dongles
-+	 * where we want to disable the PHY but keep RX powered,
-+	 * for those we need to ignore DP Sink interrupt
-+	 * by checking lane count that has been set
-+	 * on the last do_enable_output(). */
-+
-+	/* disable transmitter */
-+	cntl.action = TRANSMITTER_CONTROL_DISABLE;
-+	cntl.transmitter = link_enc->transmitter;
-+	cntl.hpd_sel = link_enc->hpd_source;
-+	cntl.signal = signal;
-+	cntl.connector_obj_id = link_enc->connector;
-+
-+	dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			link_enc->adapter_service), &cntl);
-+
-+	/* disable encoder */
-+	if (dc_is_dp_signal(signal))
-+		link_encoder_disable(link_enc);
-+
-+	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* power down eDP panel */
-+		/* TODO: Power control cause regression, we should implement
-+		 * it properly, for now just comment it.
-+		 *
-+		 * link_encoder_edp_wait_for_hpd_ready(
-+			link_enc,
-+			link_enc->connector,
-+			false);
-+
-+		 * link_encoder_edp_power_control(
-+				link_enc, false); */
-+	}
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+enum encoder_result dce110_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings)
-+{
-+	union dpcd_training_lane_set training_lane_set = { { 0 } };
-+
-+	int32_t lane = 0;
-+
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (!link_settings) {
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_RESULT_ERROR;
-+	}
-+
-+	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.connector_obj_id = enc->connector;
-+	cntl.lanes_number = link_settings->link_settings.lane_count;
-+	cntl.hpd_sel = enc->hpd_source;
-+	cntl.pixel_clock = link_settings->link_settings.link_rate *
-+						LINK_RATE_REF_FREQ_IN_KHZ;
-+
-+	for (lane = 0; lane < link_settings->link_settings.lane_count; ++lane) {
-+		/* translate lane settings */
-+
-+		training_lane_set.bits.VOLTAGE_SWING_SET =
-+			link_settings->lane_settings[lane].VOLTAGE_SWING;
-+		training_lane_set.bits.PRE_EMPHASIS_SET =
-+			link_settings->lane_settings[lane].PRE_EMPHASIS;
-+
-+		/* post cursor 2 setting only applies to HBR2 link rate */
-+		if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
-+			/* this is passed to VBIOS
-+			 * to program post cursor 2 level */
-+
-+			training_lane_set.bits.POST_CURSOR2_SET =
-+				link_settings->lane_settings[lane].POST_CURSOR2;
-+		}
-+
-+		cntl.lane_select = lane;
-+		cntl.lane_settings = training_lane_set.raw;
-+
-+		/* call VBIOS table to set voltage swing and pre-emphasis */
-+
-+		dal_bios_parser_transmitter_control(
-+			dal_adapter_service_get_bios_parser(
-+				enc->adapter_service), &cntl);
-+	}
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+void dce110_link_encoder_set_dp_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param)
-+{
-+	const int32_t offset = enc->be_engine_offset;
-+
-+
-+	switch (param->dp_phy_pattern) {
-+	case DP_TEST_PATTERN_TRAINING_PATTERN1:
-+		set_dp_phy_pattern_training_pattern(enc->ctx,
-+			offset, 0);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN2:
-+		set_dp_phy_pattern_training_pattern(enc->ctx,
-+			offset, 1);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN3:
-+		set_dp_phy_pattern_training_pattern(enc->ctx,
-+			offset, 2);
-+		break;
-+	case DP_TEST_PATTERN_D102:
-+		set_dp_phy_pattern_d102(enc->ctx, offset);
-+		break;
-+	case DP_TEST_PATTERN_SYMBOL_ERROR:
-+		set_dp_phy_pattern_symbol_error(enc->ctx, offset);
-+		break;
-+	case DP_TEST_PATTERN_PRBS7:
-+		set_dp_phy_pattern_prbs7(enc->ctx, offset);
-+		break;
-+	case DP_TEST_PATTERN_80BIT_CUSTOM:
-+		set_dp_phy_pattern_80bit_custom(
-+				enc->ctx,
-+			offset, param->custom_pattern);
-+		break;
-+	case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
-+		set_dp_phy_pattern_hbr2_compliance(
-+			enc, offset);
-+		break;
-+	case DP_TEST_PATTERN_VIDEO_MODE: {
-+		set_dp_phy_pattern_passthrough_mode(
-+			enc->ctx,
-+			offset,
-+			param->dp_panel_mode);
-+		break;
-+	}
-+
-+
-+	default:
-+		/* invalid phy pattern */
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+}
-+
-+/*
-+ * get_supported_stream_engines
-+ *
-+ * @brief
-+ * get a list of supported engine
-+ *
-+ * @param
-+ * const struct encoder_impl *enc - not used.
-+ *
-+ * @return
-+ * list of engines with supported ones enabled.
-+ */
-+union supported_stream_engines dce110_get_supported_stream_engines(
-+	const struct link_encoder *enc)
-+{
-+	union supported_stream_engines result = {.u_all = 0};
-+
-+	result.engine.ENGINE_ID_DIGA = 1;
-+	result.engine.ENGINE_ID_DIGB = 1;
-+	result.engine.ENGINE_ID_DIGC = 1;
-+
-+	if (enc->connector.id == CONNECTOR_ID_EDP /*|| wireless*/)
-+		result.u_all = (1 << enc->preferred_engine);
-+
-+	return result;
-+}
-+
-+void dce110_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct dp_mst_stream_allocation_table *table,
-+	bool is_removal)
-+{
-+	int32_t addr_offset = enc->be_engine_offset;
-+	uint32_t value0;
-+	uint32_t value1;
-+	uint32_t retries = 0;
-+
-+	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
-+
-+	/* --- Set MSE Stream Attribute -
-+	 * Setup VC Payload Table on Tx Side,
-+	 * Issue allocation change trigger
-+	 * to commit payload on both tx and rx side */
-+
-+	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset);
-+	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
-+
-+	if (table->stream_count >= 1) {
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[0].engine,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SRC0);
-+
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[0].slot_count,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SLOT_COUNT0);
-+	}
-+
-+	if (table->stream_count >= 2) {
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[1].engine,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SRC1);
-+
-+		set_reg_field_value(
-+			value0,
-+			table->stream_allocations[1].slot_count,
-+			DP_MSE_SAT0,
-+			DP_MSE_SAT_SLOT_COUNT1);
-+	}
-+
-+	if (table->stream_count >= 3) {
-+		set_reg_field_value(
-+			value1,
-+			table->stream_allocations[2].engine,
-+			DP_MSE_SAT1,
-+			DP_MSE_SAT_SRC2);
-+
-+		set_reg_field_value(
-+			value1,
-+			table->stream_allocations[2].slot_count,
-+			DP_MSE_SAT1,
-+			DP_MSE_SAT_SLOT_COUNT2);
-+	}
-+
-+	/* update ASIC MSE stream allocation table */
-+	dal_write_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset, value0);
-+	dal_write_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset, value1);
-+
-+	/* --- wait for transaction finish */
-+
-+	/* send allocation change trigger (ACT) ?
-+	 * this step first sends the ACT,
-+	 * then double buffers the SAT into the hardware
-+	 * making the new allocation active on the DP MST mode link */
-+
-+	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset);
-+
-+	/* DP_MSE_SAT_UPDATE:
-+	 * 0 - No Action
-+	 * 1 - Update SAT with trigger
-+	 * 2 - Update SAT without trigger */
-+
-+	set_reg_field_value(
-+		value0,
-+		1,
-+		DP_MSE_SAT_UPDATE,
-+		DP_MSE_SAT_UPDATE);
-+
-+	dal_write_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset, value0);
-+
-+	/* wait for update to complete
-+	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
-+	 * then wait for the transmission
-+	 * of at least 16 MTP headers on immediate local link.
-+	 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
-+	 * a value of 1 indicates that DP MST mode
-+	 * is in the 16 MTP keepout region after a VC has been added.
-+	 * MST stream bandwidth (VC rate) can be configured
-+	 * after this bit is cleared */
-+
-+	do {
-+		dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+		value0 = dal_read_reg(enc->ctx,
-+				mmDP_MSE_SAT_UPDATE + addr_offset);
-+
-+		value1 = get_reg_field_value(
-+				value0,
-+				DP_MSE_SAT_UPDATE,
-+				DP_MSE_16_MTP_KEEPOUT);
-+
-+		/* bit field DP_MSE_SAT_UPDATE is set to 1 already */
-+		if (value1)
-+			break;
-+		++retries;
-+	} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+
-+	/* TODO should not need. clean this after light up
-+	 * if (is_removal)
-+	 * dal_write_reg(enc->ctx, addr, value);
-+	 */
-+}
-+
-+
-+void dce110_link_encoder_set_lcd_backlight_level(
-+	struct link_encoder *enc,
-+	uint32_t level)
-+{
-+	struct dc_context *ctx = enc->ctx;
-+
-+	const uint32_t backlight_update_pending_max_retry = 1000;
-+
-+	uint32_t backlight;
-+	uint32_t backlight_period;
-+	uint32_t backlight_lock;
-+
-+	uint32_t i;
-+	uint32_t backlight_24bit;
-+	uint32_t backlight_17bit;
-+	uint32_t backlight_16bit;
-+	uint32_t masked_pwm_period;
-+	uint8_t rounding_bit;
-+	uint8_t bit_count;
-+	uint64_t active_duty_cycle;
-+
-+	backlight = dal_read_reg(ctx, mmBL_PWM_CNTL);
-+	backlight_period = dal_read_reg(ctx, mmBL_PWM_PERIOD_CNTL);
-+	backlight_lock = dal_read_reg(ctx, mmBL_PWM_GRP1_REG_LOCK);
-+
-+	/*
-+	 * 1. Convert 8-bit value to 17 bit U1.16 format
-+	 * (1 integer, 16 fractional bits)
-+	 */
-+
-+	/* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
-+	 * effectively multiplying value by 256/255
-+	 * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
-+	 */
-+	backlight_24bit = level * 0x10101;
-+
-+	/* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
-+	 * used for rounding, take most significant bit of fraction for
-+	 * rounding, e.g. for 0xEFEFEF, rounding bit is 1
-+	 */
-+	rounding_bit = (backlight_24bit >> 7) & 1;
-+
-+	/* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
-+	 * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
-+	 */
-+	backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
-+
-+	/*
-+	 * 2. Find  16 bit backlight active duty cycle, where 0 <= backlight
-+	 * active duty cycle <= backlight period
-+	 */
- 
- 	/* 2.1 Apply bitmask for backlight period value based on value of BITCNT
- 	 */
-@@ -1831,127 +1953,6 @@ void dce110_set_afmt_memory_power_state(
- 	dal_write_reg(ctx, mmDCO_MEM_PWR_CTRL, value);
- }
- 
--void dce110_link_encoder_update_mst_stream_allocation_table(
--	struct link_encoder *enc,
--	const struct dp_mst_stream_allocation_table *table,
--	bool is_removal)
--{
--	int32_t addr_offset = enc->be_engine_offset;
--	uint32_t value0;
--	uint32_t value1;
--	uint32_t retries = 0;
--
--	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
--
--	/* --- Set MSE Stream Attribute -
--	 * Setup VC Payload Table on Tx Side,
--	 * Issue allocation change trigger
--	 * to commit payload on both tx and rx side */
--
--	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset);
--	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
--
--	if (table->stream_count >= 1) {
--		set_reg_field_value(
--			value0,
--			table->stream_allocations[0].engine,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SRC0);
--
--		set_reg_field_value(
--			value0,
--			table->stream_allocations[0].slot_count,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SLOT_COUNT0);
--	}
--
--	if (table->stream_count >= 2) {
--		set_reg_field_value(
--			value0,
--			table->stream_allocations[1].engine,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SRC1);
--
--		set_reg_field_value(
--			value0,
--			table->stream_allocations[1].slot_count,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SLOT_COUNT1);
--	}
--
--	if (table->stream_count >= 3) {
--		set_reg_field_value(
--			value1,
--			table->stream_allocations[2].engine,
--			DP_MSE_SAT1,
--			DP_MSE_SAT_SRC2);
--
--		set_reg_field_value(
--			value1,
--			table->stream_allocations[2].slot_count,
--			DP_MSE_SAT1,
--			DP_MSE_SAT_SLOT_COUNT2);
--	}
--
--	/* update ASIC MSE stream allocation table */
--	dal_write_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset, value0);
--	dal_write_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset, value1);
--
--	/* --- wait for transaction finish */
--
--	/* send allocation change trigger (ACT) ?
--	 * this step first sends the ACT,
--	 * then double buffers the SAT into the hardware
--	 * making the new allocation active on the DP MST mode link */
--
--	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset);
--
--	/* DP_MSE_SAT_UPDATE:
--	 * 0 - No Action
--	 * 1 - Update SAT with trigger
--	 * 2 - Update SAT without trigger */
--
--	set_reg_field_value(
--		value0,
--		1,
--		DP_MSE_SAT_UPDATE,
--		DP_MSE_SAT_UPDATE);
--
--	dal_write_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset, value0);
--
--	/* wait for update to complete
--	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
--	 * then wait for the transmission
--	 * of at least 16 MTP headers on immediate local link.
--	 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
--	 * a value of 1 indicates that DP MST mode
--	 * is in the 16 MTP keepout region after a VC has been added.
--	 * MST stream bandwidth (VC rate) can be configured
--	 * after this bit is cleared */
--
--	do {
--		dc_service_delay_in_microseconds(enc->ctx, 10);
--
--		value0 = dal_read_reg(enc->ctx,
--				mmDP_MSE_SAT_UPDATE + addr_offset);
--
--		value1 = get_reg_field_value(
--				value0,
--				DP_MSE_SAT_UPDATE,
--				DP_MSE_16_MTP_KEEPOUT);
--
--		/* bit field DP_MSE_SAT_UPDATE is set to 1 already */
--		if (value1)
--			break;
--		++retries;
--	} while (retries < DP_MST_UPDATE_MAX_RETRY);
--
--	/* TODO should not need. clean this after light up
--	 * if (is_removal)
--	 * dal_write_reg(enc->ctx, addr, value);
--	 */
--}
--
- void dce110_link_encoder_set_mst_bandwidth(
- 	struct link_encoder *enc,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 4331bf0..eae2267 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -30,26 +30,11 @@ struct link_encoder *dce110_link_encoder_create(
- 	const struct encoder_init_data *init);
- void dce110_link_encoder_destroy(struct link_encoder **enc);
- 
--void dce110_link_encoder_set_dp_phy_pattern(
--	struct link_encoder *enc,
--	const struct encoder_set_dp_phy_pattern_param *param);
--
--enum encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
--
--enum encoder_result dce110_link_encoder_dp_set_lane_settings(
--	struct link_encoder *enc,
--	const struct link_training_settings *link_settings);
--
--union supported_stream_engines dce110_get_supported_stream_engines(
--	const struct link_encoder *enc);
--
- enum encoder_result dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream);
- 
--void dce110_link_encoder_set_lcd_backlight_level(
--	struct link_encoder *enc,
--	uint32_t level);
-+enum encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
- 
- void dce110_link_encoder_setup(
- 	struct link_encoder *enc,
-@@ -68,16 +53,32 @@ enum encoder_result dce110_link_encoder_disable_output(
- 	struct link_encoder *link_enc,
- 	enum signal_type signal);
- 
--void dce110_set_afmt_memory_power_state(
--	const struct dc_context *ctx,
--	enum engine_id id,
--	bool enable);
-+
-+enum encoder_result dce110_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings);
-+
-+void dce110_link_encoder_set_dp_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param);
-+
-+union supported_stream_engines dce110_get_supported_stream_engines(
-+	const struct link_encoder *enc);
- 
- void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
- 	const struct dp_mst_stream_allocation_table *table,
- 	bool is_removal);
- 
-+void dce110_link_encoder_set_lcd_backlight_level(
-+	struct link_encoder *enc,
-+	uint32_t level);
-+
-+void dce110_set_afmt_memory_power_state(
-+	const struct dc_context *ctx,
-+	enum engine_id id,
-+	bool enable);
-+
- void dce110_link_encoder_set_mst_bandwidth(
- 	struct link_encoder *enc,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index a9edf96..d3ab89a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -54,29 +54,6 @@ static void construct(
- 	enc->adapter_service = init->adapter_service;
- }
- 
--struct stream_encoder *dce110_stream_encoder_create(
--	struct stream_enc_init_data *init)
--{
--	struct stream_encoder *enc =
--		dc_service_alloc(init->ctx, sizeof(struct stream_encoder));
--
--	if (!enc)
--		goto enc_create_fail;
--
--	construct(enc, init);
--
--	return enc;
--
--enc_create_fail:
--	return NULL;
--}
--
--void dce110_stream_encoder_destroy(struct stream_encoder **enc)
--{
--	dc_service_free((*enc)->ctx, *enc);
--	*enc = NULL;
--}
--
- static void stop_hdmi_info_packets(struct dc_context *ctx, uint32_t offset)
- {
- 	uint32_t addr = 0;
-@@ -207,22 +184,6 @@ static void stop_dp_info_packets(struct dc_context *ctx, int32_t offset)
- 	dal_write_reg(ctx, addr, value);
- }
- 
--void dce110_stream_encoder_stop_info_packets(
--	struct stream_encoder *enc,
--	enum engine_id engine,
--	enum signal_type signal)
--{
--	if (dc_is_hdmi_signal(signal))
--		stop_hdmi_info_packets(
--			enc->ctx,
--			fe_engine_offsets[engine]);
--	else if (dc_is_dp_signal(signal))
--		stop_dp_info_packets(
--			enc->ctx,
--			fe_engine_offsets[engine]);
--}
--
--
- static void update_avi_info_packet(
- 	struct stream_encoder *enc,
- 	enum engine_id engine,
-@@ -615,24 +576,6 @@ static void update_dp_info_packet(
- 	dal_write_reg(enc->ctx, addr, value);
- }
- 
--void dce110_stream_encoder_update_info_packets(
--	struct stream_encoder *enc,
--	enum signal_type signal,
--	const struct encoder_info_frame *info_frame)
--{
--	if (dc_is_hdmi_signal(signal)) {
--		update_avi_info_packet(
--			enc,
--			enc->id,
--			signal,
--			&info_frame->avi);
--		update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor);
--		update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut);
--		update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd);
--	} else if (dc_is_dp_signal(signal))
--		update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc);
--}
--
- static void dp_steer_fifo_reset(
- 	struct dc_context *ctx,
- 	enum engine_id engine,
-@@ -647,76 +590,6 @@ static void dp_steer_fifo_reset(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--/*
-- * @brief
-- * Output blank data,
-- * prevents output of the actual surface data on active transmitter
-- */
--enum encoder_result dce110_stream_encoder_blank(
--				struct stream_encoder *enc,
--				enum signal_type signal)
--{
--	enum engine_id engine = enc->id;
--	const uint32_t addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
--	uint32_t value = dal_read_reg(enc->ctx, addr);
--	uint32_t retries = 0;
--	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
--
--	if (!dc_is_dp_signal(signal))
--		return ENCODER_RESULT_OK;
--
--	/* Note: For CZ, we are changing driver default to disable
--	 * stream deferred to next VBLANK. If results are positive, we
--	 * will make the same change to all DCE versions. There are a
--	 * handful of panels that cannot handle disable stream at
--	 * HBLANK and will result in a white line flash across the
--	 * screen on stream disable. */
--
--	/* Specify the video stream disable point
--	 * (2 = start of the next vertical blank) */
--	set_reg_field_value(
--		value,
--		2,
--		DP_VID_STREAM_CNTL,
--		DP_VID_STREAM_DIS_DEFER);
--	/* Larger delay to wait until VBLANK - use max retry of
--	 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
--	 * a little more because we may not trust delay accuracy. */
--	max_retries = DP_BLANK_MAX_RETRY * 150;
--
--	/* disable DP stream */
--	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
--	dal_write_reg(enc->ctx, addr, value);
--
--	/* the encoder stops sending the video stream
--	 * at the start of the vertical blanking.
--	 * Poll for DP_VID_STREAM_STATUS == 0 */
--
--	do {
--		value = dal_read_reg(enc->ctx, addr);
--
--		if (!get_reg_field_value(
--			value,
--			DP_VID_STREAM_CNTL,
--			DP_VID_STREAM_STATUS))
--			break;
--
--		dc_service_delay_in_microseconds(enc->ctx, 10);
--
--		++retries;
--	} while (retries < max_retries);
--
--	ASSERT(retries <= max_retries);
--
--	/* Tell the DP encoder to ignore timing from CRTC, must be done after
--	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
--	 * complete, stream status will be stuck in video stream enabled state,
--	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
--	dp_steer_fifo_reset(enc->ctx, engine, true);
--
--	return ENCODER_RESULT_OK;
--}
--
- static void unblank_dp_output(
- 	struct stream_encoder *enc,
- 	enum engine_id engine)
-@@ -786,46 +659,6 @@ static void setup_vid_stream(
- 	set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
- 	dal_write_reg(enc->ctx, addr, value);
- }
--/*
-- * @brief
-- * Stop sending blank data,
-- * output the actual surface data on active transmitter
-- */
--enum encoder_result dce110_stream_encoder_unblank(
--	struct stream_encoder *enc,
--	const struct encoder_unblank_param *param)
--{
--	bool is_dp_signal = param->signal == SIGNAL_TYPE_DISPLAY_PORT
--		|| param->signal == SIGNAL_TYPE_DISPLAY_PORT_MST
--		|| param->signal == SIGNAL_TYPE_EDP;
--
--	if (!is_dp_signal)
--		return ENCODER_RESULT_OK;
--
--	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
--		uint32_t n_vid = 0x8000;
--		uint32_t m_vid;
--
--		/* M / N = Fstream / Flink
--		 * m_vid / n_vid = pixel rate / link rate */
--
--		uint64_t m_vid_l = n_vid;
--
--		m_vid_l *= param->crtc_timing.pixel_clock;
--		m_vid_l = div_u64(m_vid_l,
--			param->link_settings.link_rate
--				* LINK_RATE_REF_FREQ_IN_KHZ);
--
--		m_vid = (uint32_t) m_vid_l;
--
--		setup_vid_stream(enc,
--			enc->id, m_vid, n_vid);
--	}
--
--	unblank_dp_output(enc, enc->id);
--
--	return ENCODER_RESULT_OK;
--}
- 
- static void set_dp_stream_attributes(
- 	struct stream_encoder *enc,
-@@ -1106,6 +939,29 @@ static void set_tmds_stream_attributes(
- 	dal_write_reg(enc->ctx, addr, value);
- }
- 
-+struct stream_encoder *dce110_stream_encoder_create(
-+	struct stream_enc_init_data *init)
-+{
-+	struct stream_encoder *enc =
-+		dc_service_alloc(init->ctx, sizeof(struct stream_encoder));
-+
-+	if (!enc)
-+		goto enc_create_fail;
-+
-+	construct(enc, init);
-+
-+	return enc;
-+
-+enc_create_fail:
-+	return NULL;
-+}
-+
-+void dce110_stream_encoder_destroy(struct stream_encoder **enc)
-+{
-+	dc_service_free((*enc)->ctx, *enc);
-+	*enc = NULL;
-+}
-+
- /*
-  * @brief
-  * Associate digital encoder with specified output transmitter
-@@ -1166,3 +1022,148 @@ enum encoder_result dce110_stream_encoder_setup(
- 
- 	return ENCODER_RESULT_OK;
- }
-+
-+void dce110_stream_encoder_update_info_packets(
-+	struct stream_encoder *enc,
-+	enum signal_type signal,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	if (dc_is_hdmi_signal(signal)) {
-+		update_avi_info_packet(
-+			enc,
-+			enc->id,
-+			signal,
-+			&info_frame->avi);
-+		update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor);
-+		update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut);
-+		update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd);
-+	} else if (dc_is_dp_signal(signal))
-+		update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc);
-+}
-+
-+void dce110_stream_encoder_stop_info_packets(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	enum signal_type signal)
-+{
-+	if (dc_is_hdmi_signal(signal))
-+		stop_hdmi_info_packets(
-+			enc->ctx,
-+			fe_engine_offsets[engine]);
-+	else if (dc_is_dp_signal(signal))
-+		stop_dp_info_packets(
-+			enc->ctx,
-+			fe_engine_offsets[engine]);
-+}
-+
-+/*
-+ * @brief
-+ * Output blank data,
-+ * prevents output of the actual surface data on active transmitter
-+ */
-+enum encoder_result dce110_stream_encoder_blank(
-+				struct stream_encoder *enc,
-+				enum signal_type signal)
-+{
-+	enum engine_id engine = enc->id;
-+	const uint32_t addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	uint32_t retries = 0;
-+	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
-+
-+	if (!dc_is_dp_signal(signal))
-+		return ENCODER_RESULT_OK;
-+
-+	/* Note: For CZ, we are changing driver default to disable
-+	 * stream deferred to next VBLANK. If results are positive, we
-+	 * will make the same change to all DCE versions. There are a
-+	 * handful of panels that cannot handle disable stream at
-+	 * HBLANK and will result in a white line flash across the
-+	 * screen on stream disable. */
-+
-+	/* Specify the video stream disable point
-+	 * (2 = start of the next vertical blank) */
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DP_VID_STREAM_CNTL,
-+		DP_VID_STREAM_DIS_DEFER);
-+	/* Larger delay to wait until VBLANK - use max retry of
-+	 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
-+	 * a little more because we may not trust delay accuracy. */
-+	max_retries = DP_BLANK_MAX_RETRY * 150;
-+
-+	/* disable DP stream */
-+	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
-+	dal_write_reg(enc->ctx, addr, value);
-+
-+	/* the encoder stops sending the video stream
-+	 * at the start of the vertical blanking.
-+	 * Poll for DP_VID_STREAM_STATUS == 0 */
-+
-+	do {
-+		value = dal_read_reg(enc->ctx, addr);
-+
-+		if (!get_reg_field_value(
-+			value,
-+			DP_VID_STREAM_CNTL,
-+			DP_VID_STREAM_STATUS))
-+			break;
-+
-+		dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+		++retries;
-+	} while (retries < max_retries);
-+
-+	ASSERT(retries <= max_retries);
-+
-+	/* Tell the DP encoder to ignore timing from CRTC, must be done after
-+	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
-+	 * complete, stream status will be stuck in video stream enabled state,
-+	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
-+	dp_steer_fifo_reset(enc->ctx, engine, true);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+/*
-+ * @brief
-+ * Stop sending blank data,
-+ * output the actual surface data on active transmitter
-+ */
-+enum encoder_result dce110_stream_encoder_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param)
-+{
-+	bool is_dp_signal = param->signal == SIGNAL_TYPE_DISPLAY_PORT
-+		|| param->signal == SIGNAL_TYPE_DISPLAY_PORT_MST
-+		|| param->signal == SIGNAL_TYPE_EDP;
-+
-+	if (!is_dp_signal)
-+		return ENCODER_RESULT_OK;
-+
-+	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
-+		uint32_t n_vid = 0x8000;
-+		uint32_t m_vid;
-+
-+		/* M / N = Fstream / Flink
-+		 * m_vid / n_vid = pixel rate / link rate */
-+
-+		uint64_t m_vid_l = n_vid;
-+
-+		m_vid_l *= param->crtc_timing.pixel_clock;
-+		m_vid_l = div_u64(m_vid_l,
-+			param->link_settings.link_rate
-+				* LINK_RATE_REF_FREQ_IN_KHZ);
-+
-+		m_vid = (uint32_t) m_vid_l;
-+
-+		setup_vid_stream(enc,
-+			enc->id, m_vid, n_vid);
-+	}
-+
-+	unblank_dp_output(enc, enc->id);
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index d2c7b90..83df255 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -37,16 +37,22 @@ struct stream_encoder *dce110_stream_encoder_create(
- 
- void dce110_stream_encoder_destroy(struct stream_encoder **enc);
- 
--void dce110_stream_encoder_stop_info_packets(
-+enum encoder_result dce110_stream_encoder_setup(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
--	enum signal_type signal);
-+	struct dc_crtc_timing *crtc_timing,
-+	enum signal_type signal,
-+	bool enable_audio);
- 
- void dce110_stream_encoder_update_info_packets(
- 	struct stream_encoder *enc,
- 	enum signal_type signal,
- 	const struct encoder_info_frame *info_frame);
- 
-+void dce110_stream_encoder_stop_info_packets(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	enum signal_type signal);
-+
- enum encoder_result dce110_stream_encoder_blank(
- 	struct stream_encoder *enc,
- 	enum signal_type signal);
-@@ -55,10 +61,4 @@ enum encoder_result dce110_stream_encoder_unblank(
- 	struct stream_encoder *enc,
- 	const struct encoder_unblank_param *param);
- 
--enum encoder_result dce110_stream_encoder_setup(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing,
--	enum signal_type signal,
--	bool enable_audio);
--
- #endif /* __DC_STREAM_ENCODER_DCE110_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0519-drm-amd-dal-Assign-stream-encoder-in-MST-use-case.patch b/common/recipes-kernel/linux/files/0519-drm-amd-dal-Assign-stream-encoder-in-MST-use-case.patch
deleted file mode 100644
index 41a276a2..00000000
--- a/common/recipes-kernel/linux/files/0519-drm-amd-dal-Assign-stream-encoder-in-MST-use-case.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From c6f35a4f48a647c5365293ae636c1ad5a122fb3b Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 24 Nov 2015 17:44:52 -0500
-Subject: [PATCH 0519/1110] drm/amd/dal: Assign stream encoder in MST use case.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 12 ++++++++++--
- 1 file changed, 10 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index d2594a9..fb3f5be 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -784,17 +784,25 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
- 		struct core_link *link)
- {
- 	uint8_t i;
-+	int8_t j = -1;
- 
- 	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
- 		if (!res_ctx->is_stream_enc_acquired[i] &&
--				res_ctx->pool.stream_enc[i]) {
-+					res_ctx->pool.stream_enc[i]) {
-+			/* Store first available for MST second display
-+			 * in daisy chain use case */
-+			j = i;
- 			if (res_ctx->pool.stream_enc[i]->id ==
- 					link->link_enc->preferred_engine)
- 				return res_ctx->pool.stream_enc[i];
- 		}
- 	}
- 
--	/* TODO: Handle MST*/
-+	/* TODO: Handle MST properly
-+	 * Currently pick next available stream encoder if found*/
-+	if (j >= 0 && link->public.sink[0]->sink_signal ==
-+			SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		return res_ctx->pool.stream_enc[j];
- 
- 	return NULL;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0520-drm-amd-dal-Clean-up-Link-Stream-Encoder.patch b/common/recipes-kernel/linux/files/0520-drm-amd-dal-Clean-up-Link-Stream-Encoder.patch
deleted file mode 100644
index 5e3d0e64..00000000
--- a/common/recipes-kernel/linux/files/0520-drm-amd-dal-Clean-up-Link-Stream-Encoder.patch
+++ /dev/null
@@ -1,1527 +0,0 @@
-From d5172ff2745aed4b4db28cd6d90f3a23dfe1e768 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 25 Nov 2015 16:01:12 -0500
-Subject: [PATCH 0520/1110] drm/amd/dal: Clean-up Link & Stream Encoder
-
-Branch out interface functions to display specifics.
-Move switch statement to upper layer.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  84 ++-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 274 +++------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  57 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   1 -
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 667 ++++++++++++---------
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |  52 +-
- drivers/gpu/drm/amd/dal/include/encoder_types.h    |   1 -
- 7 files changed, 592 insertions(+), 544 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 74294cb..394b645 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -634,10 +634,14 @@ static void update_bios_scratch_critical_state(struct adapter_service *as,
- 
- static void update_info_frame(struct core_stream *stream)
- {
--	dce110_stream_encoder_update_info_packets(
--		stream->stream_enc,
--		stream->signal,
--		&stream->encoder_info_frame);
-+	if (dc_is_hdmi_signal(stream->signal))
-+		dce110_stream_encoder_update_hdmi_info_packets(
-+			stream->stream_enc,
-+			&stream->encoder_info_frame);
-+	else if (dc_is_dp_signal(stream->signal))
-+		dce110_stream_encoder_update_dp_info_packets(
-+			stream->stream_enc,
-+			&stream->encoder_info_frame);
- }
- 
- 
-@@ -690,10 +694,15 @@ static void disable_stream(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
- 
--	dce110_stream_encoder_stop_info_packets(
--		stream->stream_enc,
--		stream->stream_enc->id,
--		stream->signal);
-+	if (dc_is_hdmi_signal(stream->signal))
-+		dce110_stream_encoder_stop_hdmi_info_packets(
-+			stream->stream_enc->ctx,
-+			stream->stream_enc->id);
-+
-+	if (dc_is_dp_signal(stream->signal))
-+		dce110_stream_encoder_stop_dp_info_packets(
-+			stream->stream_enc->ctx,
-+			stream->stream_enc->id);
- 
- 	if (stream->audio) {
- 		/* mute audio */
-@@ -708,7 +717,9 @@ static void disable_stream(struct core_stream *stream)
- 	}
- 
- 	/* blank at encoder level */
--	dce110_stream_encoder_blank(stream->stream_enc, stream->signal);
-+	if (dc_is_dp_signal(stream->signal))
-+		dce110_stream_encoder_dp_blank(stream->stream_enc);
-+
- 	dce110_link_encoder_connect_dig_be_to_fe(
- 			link->link_enc,
- 			stream->stream_enc->id,
-@@ -725,8 +736,7 @@ static void unblank_stream(struct core_stream *stream,
- 	params.crtc_timing.pixel_clock =
- 		stream->public.timing.pix_clk_khz;
- 	params.link_settings.link_rate = link_settings->link_rate;
--	params.signal = stream->signal;
--	dce110_stream_encoder_unblank(
-+	dce110_stream_encoder_dp_unblank(
- 		stream->stream_enc, &params);
- }
- 
-@@ -787,8 +797,7 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 
- 	dce110_link_encoder_update_mst_stream_allocation_table(
- 		link_encoder,
--		&table,
--		false);
-+		&table);
- 
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
-@@ -803,8 +812,8 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 			table.stream_allocations[0].pbn,
- 			table.stream_allocations[0].pbn_per_slot);
- 
--	dce110_link_encoder_set_mst_bandwidth(
--		link_encoder,
-+	dce110_stream_encoder_set_mst_bandwidth(
-+		stream_encoder,
- 		stream_encoder->id,
- 		avg_time_slots_per_mtp);
- 
-@@ -823,8 +832,8 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	table.stream_count = 1;
- 	table.stream_allocations[0].slot_count = 0;
- 
--	dce110_link_encoder_set_mst_bandwidth(
--		link_encoder,
-+	dce110_stream_encoder_set_mst_bandwidth(
-+		stream_encoder,
- 		stream_encoder->id,
- 		avg_time_slots_per_mtp);
- 
-@@ -836,8 +845,7 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 
- 	dce110_link_encoder_update_mst_stream_allocation_table(
- 		link_encoder,
--		&table,
--		false);
-+		&table);
- 
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
-@@ -859,7 +867,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- {
- 	struct core_stream *stream =
- 			context->res_ctx.controller_ctx[controller_idx].stream;
--
- 	struct output_pixel_processor *opp =
- 		context->res_ctx.pool.opps[controller_idx];
- 	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
-@@ -921,14 +928,31 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	dce110_link_encoder_setup(
- 		stream->sink->link->link_enc,
- 		stream->signal);
--	if (ENCODER_RESULT_OK != dce110_stream_encoder_setup(
-+
-+	if (!dc_is_dp_signal(stream->signal))
-+		if (ENCODER_RESULT_OK != dce110_stream_encoder_setup(
-+				stream->stream_enc,
-+				&stream->public.timing,
-+				stream->signal,
-+				stream->audio != NULL)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+
-+	if (dc_is_dp_signal(stream->signal))
-+		dce110_stream_encoder_dp_set_stream_attribute(
- 			stream->stream_enc,
--			&stream->public.timing,
--			stream->signal,
--			stream->audio != NULL)) {
--		BREAK_TO_DEBUGGER();
--		return DC_ERROR_UNEXPECTED;
--	}
-+			&stream->public.timing);
-+
-+	if (dc_is_hdmi_signal(stream->signal))
-+		dce110_stream_encoder_hdmi_set_stream_attribute(
-+		stream->stream_enc,
-+		&stream->public.timing);
-+
-+	if (dc_is_dvi_signal(stream->signal))
-+		dce110_stream_encoder_dvi_set_stream_attribute(
-+		stream->stream_enc,
-+		&stream->public.timing);
- 
- 	if (stream->audio != NULL) {
- 		if (AUDIO_RESULT_OK != dal_audio_setup(
-@@ -968,7 +992,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 
- 	}
- 
--	unblank_stream(stream, &stream->sink->link->cur_link_settings);
-+	if (dc_is_dp_signal(stream->signal))
-+		unblank_stream(stream, &stream->sink->link->cur_link_settings);
- 
- 	return DC_OK;
- }
-@@ -1810,7 +1835,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.destruct_resource_pool = dce110_destruct_resource_pool,
- 	.validate_with_context = dce110_validate_with_context,
- 	.validate_bandwidth = dce110_validate_bandwidth,
--	.set_afmt_memory_power_state = dce110_set_afmt_memory_power_state,
-+	.set_afmt_memory_power_state =
-+	  dce110_stream_encoder_set_afmt_memory_power_state,
- 	.enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating,
- 	.enable_display_power_gating = dce110_enable_display_power_gating,
- 	.program_bw = dce110_program_bw
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 9817318..0ad582b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1377,69 +1377,39 @@ void dce110_link_encoder_setup(
- 	dal_write_reg(enc->ctx, addr, value);
- }
- 
--/*
-- * @brief
-- * Configure digital transmitter and enable both encoder and transmitter
-- * Actual output will be available after calling unblank()
-- */
--enum encoder_result dce110_link_encoder_enable_output(
-+enum encoder_result dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum engine_id engine,
- 	enum clock_source_id clock_source,
--	enum signal_type signal,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock)
- {
--	struct bp_transmitter_control cntl = { 0 };
--
--	if (enc->connector.id == CONNECTOR_ID_EDP) {
--		/* power up eDP panel */
--
--		link_encoder_edp_power_control(
--			enc, true);
--
--		link_encoder_edp_wait_for_hpd_ready(
--			enc, enc->connector, true);
--
--		/* have to turn off the backlight
--		 * before power down eDP panel */
--		link_encoder_edp_backlight_control(
--				enc, true);
--	}
--
--	/* Enable the PHY */
--
--	/* number_of_lanes is used for pixel clock adjust,
--	 * but it's not passed to asic_control.
--	 * We need to set number of lanes manually. */
--	if (dc_is_dp_signal(signal))
--		configure_encoder(enc, engine, link_settings);
--
--	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = engine;
--	cntl.transmitter = enc->transmitter;
--	cntl.pll_id = clock_source;
--	cntl.signal = signal;
--	cntl.lanes_number = link_settings->lane_count;
--	cntl.hpd_sel = enc->hpd_source;
--	if (dc_is_dp_signal(signal))
--		cntl.pixel_clock = link_settings->link_rate
--						* LINK_RATE_REF_FREQ_IN_KHZ;
--	else
--		cntl.pixel_clock = pixel_clock;
--	cntl.color_depth = color_depth;
-+	return ENCODER_RESULT_OK;
-+}
- 
--	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
--		dc_service_sleep_in_milliseconds(
--			enc->ctx,
--			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
-+enum encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock)
-+{
-+	return ENCODER_RESULT_OK;
-+}
- 
--	dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc->adapter_service),
--		&cntl);
-+/* enables DP PHY output */
-+enum encoder_result dce110_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
-+	return ENCODER_RESULT_OK;
-+}
- 
-+/* enables DP PHY output in MST mode */
-+enum encoder_result dce110_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
- 	return ENCODER_RESULT_OK;
- }
- 
-@@ -1560,6 +1530,7 @@ enum encoder_result dce110_link_encoder_dp_set_lane_settings(
- 	return ENCODER_RESULT_OK;
- }
- 
-+/* set DP PHY test and training patterns */
- void dce110_link_encoder_set_dp_phy_pattern(
- 	struct link_encoder *enc,
- 	const struct encoder_set_dp_phy_pattern_param *param)
-@@ -1614,37 +1585,10 @@ void dce110_link_encoder_set_dp_phy_pattern(
- 	}
- }
- 
--/*
-- * get_supported_stream_engines
-- *
-- * @brief
-- * get a list of supported engine
-- *
-- * @param
-- * const struct encoder_impl *enc - not used.
-- *
-- * @return
-- * list of engines with supported ones enabled.
-- */
--union supported_stream_engines dce110_get_supported_stream_engines(
--	const struct link_encoder *enc)
--{
--	union supported_stream_engines result = {.u_all = 0};
--
--	result.engine.ENGINE_ID_DIGA = 1;
--	result.engine.ENGINE_ID_DIGB = 1;
--	result.engine.ENGINE_ID_DIGC = 1;
--
--	if (enc->connector.id == CONNECTOR_ID_EDP /*|| wireless*/)
--		result.u_all = (1 << enc->preferred_engine);
--
--	return result;
--}
--
-+/* programs DP MST VC payload allocation */
- void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
--	const struct dp_mst_stream_allocation_table *table,
--	bool is_removal)
-+	const struct dp_mst_stream_allocation_table *table)
- {
- 	int32_t addr_offset = enc->be_engine_offset;
- 	uint32_t value0;
-@@ -1755,14 +1699,9 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 			break;
- 		++retries;
- 	} while (retries < DP_MST_UPDATE_MAX_RETRY);
--
--	/* TODO should not need. clean this after light up
--	 * if (is_removal)
--	 * dal_write_reg(enc->ctx, addr, value);
--	 */
- }
- 
--
-+/* black light programming */
- void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level)
-@@ -1895,125 +1834,70 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	}
- }
- 
--/*TODO: move to correct dce specific file*/
--/**
--* set_afmt_memory_power_state
--*
--* @brief
--*  Power up audio formatter memory that is mapped to specified DIG
--*/
--void dce110_set_afmt_memory_power_state(
--	const struct dc_context *ctx,
--	enum engine_id id,
--	bool enable)
--{
--	uint32_t value;
--	uint32_t mem_pwr_force;
--
--	value = dal_read_reg(ctx, mmDCO_MEM_PWR_CTRL);
--
--	if (enable)
--		mem_pwr_force = 0;
--	else
--		mem_pwr_force = 3;
--
--	/* force shutdown mode for appropriate AFMT memory */
--	switch (id) {
--	case ENGINE_ID_DIGA:
--		set_reg_field_value(
--			value,
--			mem_pwr_force,
--			DCO_MEM_PWR_CTRL,
--			HDMI0_MEM_PWR_FORCE);
--		break;
--	case ENGINE_ID_DIGB:
--		set_reg_field_value(
--			value,
--			mem_pwr_force,
--			DCO_MEM_PWR_CTRL,
--			HDMI1_MEM_PWR_FORCE);
--		break;
--	case ENGINE_ID_DIGC:
--		set_reg_field_value(
--			value,
--			mem_pwr_force,
--			DCO_MEM_PWR_CTRL,
--			HDMI2_MEM_PWR_FORCE);
--		break;
--	default:
--		dal_logger_write(
--			ctx->logger,
--			LOG_MAJOR_WARNING,
--			LOG_MINOR_COMPONENT_ENCODER,
--			"%s: Invalid Engine Id\n",
--			__func__);
--		break;
--	}
--
--	dal_write_reg(ctx, mmDCO_MEM_PWR_CTRL, value);
--}
--
--void dce110_link_encoder_set_mst_bandwidth(
-+/*
-+ * @brief
-+ * Configure digital transmitter and enable both encoder and transmitter
-+ * Actual output will be available after calling unblank()
-+ */
-+enum encoder_result dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
- 	enum engine_id engine,
--	struct fixed31_32 avg_time_slots_per_mtp)
-+	enum clock_source_id clock_source,
-+	enum signal_type signal,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock)
- {
--	uint32_t x = dal_fixed31_32_floor(
--		avg_time_slots_per_mtp);
--
--	uint32_t y = dal_fixed31_32_ceil(
--		dal_fixed31_32_shl(
--			dal_fixed31_32_sub_int(
--				avg_time_slots_per_mtp,
--				x),
--			26));
-+	struct bp_transmitter_control cntl = { 0 };
- 
--	{
--		const uint32_t addr = mmDP_MSE_RATE_CNTL +
--				fe_engine_offsets[engine];
--		uint32_t value = dal_read_reg(enc->ctx, addr);
-+	if (enc->connector.id == CONNECTOR_ID_EDP) {
-+		/* power up eDP panel */
- 
--		set_reg_field_value(
--			value,
--			x,
--			DP_MSE_RATE_CNTL,
--			DP_MSE_RATE_X);
-+		link_encoder_edp_power_control(
-+			enc, true);
- 
--		set_reg_field_value(
--			value,
--			y,
--			DP_MSE_RATE_CNTL,
--			DP_MSE_RATE_Y);
-+		link_encoder_edp_wait_for_hpd_ready(
-+			enc, enc->connector, true);
- 
--		dal_write_reg(enc->ctx, addr, value);
-+		/* have to turn off the backlight
-+		 * before power down eDP panel */
-+		link_encoder_edp_backlight_control(
-+				enc, true);
- 	}
- 
--	/* wait for update to be completed on the link
--	 * i.e. DP_MSE_RATE_UPDATE_PENDING field (read only)
--	 * is reset to 0 (not pending) */
--	{
--		const uint32_t addr = mmDP_MSE_RATE_UPDATE +
--			fe_engine_offsets[engine];
--		uint32_t value, field;
--		uint32_t retries = 0;
-+	/* Enable the PHY */
- 
--		do {
--			value = dal_read_reg(enc->ctx, addr);
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually. */
-+	if (dc_is_dp_signal(signal))
-+		configure_encoder(enc, engine, link_settings);
- 
--			field = get_reg_field_value(
--					value,
--					DP_MSE_RATE_UPDATE,
--					DP_MSE_RATE_UPDATE_PENDING);
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = engine;
-+	cntl.transmitter = enc->transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = signal;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc->hpd_source;
-+	if (dc_is_dp_signal(signal))
-+		cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	else
-+		cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
- 
--			if (!(field &
--			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
--				break;
-+	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
-+		dc_service_sleep_in_milliseconds(
-+			enc->ctx,
-+			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
- 
--			dc_service_delay_in_microseconds(enc->ctx, 10);
-+	dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc->adapter_service),
-+		&cntl);
- 
--			++retries;
--		} while (retries < DP_MST_UPDATE_MAX_RETRY);
--	}
-+	return ENCODER_RESULT_OK;
- }
- 
- void dce110_link_encoder_connect_dig_be_to_fe(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index eae2267..1032228 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -28,32 +28,58 @@
- 
- struct link_encoder *dce110_link_encoder_create(
- 	const struct encoder_init_data *init);
-+
- void dce110_link_encoder_destroy(struct link_encoder **enc);
- 
- enum encoder_result dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream);
- 
-+/****************** HW programming ************************/
-+
-+/* initialize HW */  /* why do we initialze aux in here? */
- enum encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
- 
-+/* program DIG_MODE in DIG_BE */
-+/* TODO can this be combined with enable_output? */
- void dce110_link_encoder_setup(
- 	struct link_encoder *enc,
- 	enum signal_type signal);
- 
--enum encoder_result dce110_link_encoder_enable_output(
-+/* enables TMDS PHY output */
-+/* TODO: still need depth or just pass in adjusted pixel clock? */
-+enum encoder_result dce110_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock);
-+
-+/* enables TMDS PHY output */
-+/* TODO: still need this or just pass in adjusted pixel clock? */
-+enum encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum engine_id engine,
- 	enum clock_source_id clock_source,
--	enum signal_type signal,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock);
- 
-+/* enables DP PHY output */
-+enum encoder_result dce110_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source);
-+
-+/* enables DP PHY output in MST mode */
-+enum encoder_result dce110_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source);
-+
-+/* disable PHY output */
- enum encoder_result dce110_link_encoder_disable_output(
- 	struct link_encoder *link_enc,
- 	enum signal_type signal);
- 
--
-+/* set DP lane settings */
- enum encoder_result dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings);
-@@ -62,31 +88,28 @@ void dce110_link_encoder_set_dp_phy_pattern(
- 	struct link_encoder *enc,
- 	const struct encoder_set_dp_phy_pattern_param *param);
- 
--union supported_stream_engines dce110_get_supported_stream_engines(
--	const struct link_encoder *enc);
--
-+/* programs DP MST VC payload allocation */
- void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
--	const struct dp_mst_stream_allocation_table *table,
--	bool is_removal);
-+	const struct dp_mst_stream_allocation_table *table);
- 
- void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level);
- 
--void dce110_set_afmt_memory_power_state(
--	const struct dc_context *ctx,
--	enum engine_id id,
--	bool enable);
--
--void dce110_link_encoder_set_mst_bandwidth(
-+enum encoder_result dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
- 	enum engine_id engine,
--	struct fixed31_32 avg_time_slots_per_mtp);
-+	enum clock_source_id clock_source,
-+	enum signal_type signal,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock);
- 
- void dce110_link_encoder_connect_dig_be_to_fe(
- 	struct link_encoder *enc,
- 	enum engine_id engine,
- 	bool connect);
- 
-+
- #endif /* __DC_LINK_ENCODER__DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index fb3f5be..0499976 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -624,7 +624,6 @@ bool dce110_construct_resource_pool(
- 		struct stream_enc_init_data enc_init_data = { 0 };
- 		/* TODO: rework fragile code*/
- 		enc_init_data.stream_engine_id = i;
--		enc_init_data.adapter_service = adapter_serv;
- 		enc_init_data.ctx = dc->ctx;
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index d3ab89a..37781ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -45,155 +45,28 @@ static const uint32_t fe_engine_offsets[] = {
- 	#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
- #endif
- 
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
- static void construct(
- 	struct stream_encoder *enc,
- 	struct stream_enc_init_data *init)
- {
- 	enc->ctx = init->ctx;
- 	enc->id = init->stream_engine_id;
--	enc->adapter_service = init->adapter_service;
--}
--
--static void stop_hdmi_info_packets(struct dc_context *ctx, uint32_t offset)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--
--	/* stop generic packets 0 & 1 on HDMI */
--	addr = mmHDMI_GENERIC_PACKET_CONTROL0 + offset;
--
--	value = dal_read_reg(ctx, addr);
--
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL0,
--		HDMI_GENERIC1_CONT);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL0,
--		HDMI_GENERIC1_LINE);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL0,
--		HDMI_GENERIC1_SEND);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL0,
--		HDMI_GENERIC0_CONT);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL0,
--		HDMI_GENERIC0_LINE);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL0,
--		HDMI_GENERIC0_SEND);
--
--	dal_write_reg(ctx, addr, value);
--
--	/* stop generic packets 2 & 3 on HDMI */
--	addr = mmHDMI_GENERIC_PACKET_CONTROL1 + offset;
--
--	value = dal_read_reg(ctx, addr);
--
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL1,
--		HDMI_GENERIC2_CONT);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL1,
--		HDMI_GENERIC2_LINE);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL1,
--		HDMI_GENERIC2_SEND);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL1,
--		HDMI_GENERIC3_CONT);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL1,
--		HDMI_GENERIC3_LINE);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_GENERIC_PACKET_CONTROL1,
--		HDMI_GENERIC3_SEND);
--
--	dal_write_reg(ctx, addr, value);
--
--	/* stop AVI packet on HDMI */
--	addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
--
--	value = dal_read_reg(ctx, addr);
--
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_INFOFRAME_CONTROL0,
--		HDMI_AVI_INFO_SEND);
--	set_reg_field_value(
--		value,
--		0,
--		HDMI_INFOFRAME_CONTROL0,
--		HDMI_AVI_INFO_CONT);
--
--	dal_write_reg(ctx, addr, value);
--}
--
--static void stop_dp_info_packets(struct dc_context *ctx, int32_t offset)
--{
--	/* stop generic packets on DP */
--
--	const uint32_t addr = mmDP_SEC_CNTL + offset;
--
--	uint32_t value = dal_read_reg(ctx, addr);
--
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP1_ENABLE);
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP2_ENABLE);
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP3_ENABLE);
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_AVI_ENABLE);
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_MPG_ENABLE);
--	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE);
--
--	/* this register shared with audio info frame.
--	 * therefore we need to keep master enabled
--	 * if at least one of the fields is not 0 */
--
--	if (value)
--		set_reg_field_value(
--			value,
--			1,
--			DP_SEC_CNTL,
--			DP_SEC_STREAM_ENABLE);
--
--	dal_write_reg(ctx, addr, value);
- }
- 
- static void update_avi_info_packet(
- 	struct stream_encoder *enc,
- 	enum engine_id engine,
--	enum signal_type signal,
- 	const struct encoder_info_packet *info_packet)
- {
- 	const int32_t offset = fe_engine_offsets[engine];
--
- 	uint32_t regval;
- 	uint32_t addr;
-+	uint32_t control0val;
-+	uint32_t control1val;
- 
- 	if (info_packet->valid) {
- 		const uint32_t *content =
-@@ -239,42 +112,36 @@ static void update_avi_info_packet(
- 				regval);
- 		}
- 
--		if (dc_is_hdmi_signal(signal)) {
--
--			uint32_t control0val;
--			uint32_t control1val;
--
--			addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+		addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
- 
--			control0val = dal_read_reg(enc->ctx, addr);
-+		control0val = dal_read_reg(enc->ctx, addr);
- 
--			set_reg_field_value(
--				control0val,
--				1,
--				HDMI_INFOFRAME_CONTROL0,
--				HDMI_AVI_INFO_SEND);
-+		set_reg_field_value(
-+			control0val,
-+			1,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_SEND);
- 
--			set_reg_field_value(
--				control0val,
--				1,
--				HDMI_INFOFRAME_CONTROL0,
--				HDMI_AVI_INFO_CONT);
-+		set_reg_field_value(
-+			control0val,
-+			1,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_CONT);
- 
--			dal_write_reg(enc->ctx, addr, control0val);
-+		dal_write_reg(enc->ctx, addr, control0val);
- 
--			addr = mmHDMI_INFOFRAME_CONTROL1 + offset;
-+		addr = mmHDMI_INFOFRAME_CONTROL1 + offset;
- 
--			control1val = dal_read_reg(enc->ctx, addr);
-+		control1val = dal_read_reg(enc->ctx, addr);
- 
--			set_reg_field_value(
--				control1val,
--				VBI_LINE_0 + 2,
--				HDMI_INFOFRAME_CONTROL1,
--				HDMI_AVI_INFO_LINE);
-+		set_reg_field_value(
-+			control1val,
-+			VBI_LINE_0 + 2,
-+			HDMI_INFOFRAME_CONTROL1,
-+			HDMI_AVI_INFO_LINE);
- 
--			dal_write_reg(enc->ctx, addr, control1val);
--		}
--	} else if (dc_is_hdmi_signal(signal)) {
-+		dal_write_reg(enc->ctx, addr, control1val);
-+	} else {
- 		addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
- 
- 		regval = dal_read_reg(enc->ctx, addr);
-@@ -660,6 +527,48 @@ static void setup_vid_stream(
- 	dal_write_reg(enc->ctx, addr, value);
- }
- 
-+static void set_tmds_stream_attributes(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	const struct dc_crtc_timing *timing,
-+	bool is_dvi
-+	)
-+{
-+	uint32_t addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
-+	uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+	switch (timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(value, 1, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	switch (timing->display_color_depth) {
-+	case COLOR_DEPTH_101010:
-+		if (is_dvi &&
-+			timing->pixel_encoding == PIXEL_ENCODING_RGB)
-+			set_reg_field_value(
-+				value,
-+				2,
-+				DIG_FE_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DIG_FE_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
-+		break;
-+	}
-+	dal_write_reg(enc->ctx, addr, value);
-+}
-+
- static void set_dp_stream_attributes(
- 	struct stream_encoder *enc,
- 	enum engine_id engine,
-@@ -897,48 +806,6 @@ static void setup_hdmi(
- 
- }
- 
--static void set_tmds_stream_attributes(
--	struct stream_encoder *enc,
--	enum engine_id engine,
--	enum signal_type signal,
--	const struct dc_crtc_timing *timing)
--{
--	uint32_t addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
--	uint32_t value = dal_read_reg(enc->ctx, addr);
--
--	switch (timing->pixel_encoding) {
--	case PIXEL_ENCODING_YCBCR422:
--		set_reg_field_value(value, 1, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
--		break;
--	default:
--		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
--		break;
--	}
--
--	switch (timing->pixel_encoding) {
--	case COLOR_DEPTH_101010:
--		if ((signal == SIGNAL_TYPE_DVI_SINGLE_LINK
--			|| signal == SIGNAL_TYPE_DVI_DUAL_LINK)
--			&& timing->pixel_encoding == PIXEL_ENCODING_RGB)
--			set_reg_field_value(
--				value,
--				2,
--				DIG_FE_CNTL,
--				TMDS_COLOR_FORMAT);
--		else
--			set_reg_field_value(
--				value,
--				0,
--				DIG_FE_CNTL,
--				TMDS_COLOR_FORMAT);
--		break;
--	default:
--		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
--		break;
--	}
--	dal_write_reg(enc->ctx, addr, value);
--}
--
- struct stream_encoder *dce110_stream_encoder_create(
- 	struct stream_enc_init_data *init)
- {
-@@ -974,96 +841,330 @@ enum encoder_result dce110_stream_encoder_setup(
- 	enum signal_type signal,
- 	bool enable_audio)
- {
--	if (!dc_is_dp_signal(signal)) {
--		struct bp_encoder_control cntl;
--
--		cntl.action = ENCODER_CONTROL_SETUP;
--		cntl.engine_id = enc->id;
--		cntl.signal = signal;
--		cntl.enable_dp_audio = enable_audio;
--		cntl.pixel_clock = crtc_timing->pix_clk_khz;
--		cntl.lanes_number = (signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
--					LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
--		cntl.color_depth = crtc_timing->display_color_depth;
--
--		if (dal_bios_parser_encoder_control(
-+	struct bp_encoder_control cntl;
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc->id;
-+	cntl.signal = signal;
-+	cntl.enable_dp_audio = enable_audio;
-+	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+	cntl.lanes_number = (signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+				LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+	cntl.color_depth = crtc_timing->display_color_depth;
-+
-+	if (dal_bios_parser_encoder_control(
- 			dal_adapter_service_get_bios_parser(
--				enc->adapter_service),
--			&cntl) != BP_RESULT_OK)
--			return ENCODER_RESULT_ERROR;
-+			enc->adapter_service), &cntl) != BP_RESULT_OK)
-+		return ENCODER_RESULT_ERROR;
-+
-+	return ENCODER_RESULT_OK;
-+}
-+
-+void dce110_stream_encoder_stop_hdmi_info_packets(
-+	struct dc_context *ctx,
-+	enum engine_id engine)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t offset = fe_engine_offsets[engine];
-+
-+	/* stop generic packets 0 & 1 on HDMI */
-+	addr = mmHDMI_GENERIC_PACKET_CONTROL0 + offset;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_SEND);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* stop generic packets 2 & 3 on HDMI */
-+	addr = mmHDMI_GENERIC_PACKET_CONTROL1 + offset;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_SEND);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* stop AVI packet on HDMI */
-+	addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AVI_INFO_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AVI_INFO_CONT);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_stream_encoder_stop_dp_info_packets(
-+	struct dc_context *ctx,
-+	enum engine_id engine)
-+{
-+	/* stop generic packets on DP */
-+	uint32_t offset = fe_engine_offsets[engine];
-+	const uint32_t addr = mmDP_SEC_CNTL + offset;
-+	uint32_t value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP1_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP2_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP3_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_AVI_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_MPG_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE);
-+
-+	/* this register shared with audio info frame.
-+	 * therefore we need to keep master enabled
-+	 * if at least one of the fields is not 0 */
-+
-+	if (value)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+/* setup stream encoder in dp mode */
-+void dce110_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing)
-+{
-+	set_dp_stream_attributes(enc, enc->id, crtc_timing);
-+}
-+
-+/* setup stream encoder in hdmi mode */
-+void dce110_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing)
-+{
-+	set_tmds_stream_attributes(enc, enc->id, crtc_timing, false);
-+
-+	/* setup HDMI engine */
-+	setup_hdmi(
-+		enc, enc->id, crtc_timing);
-+}
-+
-+/* setup stream encoder in dvi mode */
-+void dce110_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing)
-+{
-+	set_tmds_stream_attributes(enc, enc->id, crtc_timing, true);
-+}
-+
-+void dce110_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	enum engine_id engine,
-+	struct fixed31_32 avg_time_slots_per_mtp)
-+{
-+	uint32_t x = dal_fixed31_32_floor(
-+		avg_time_slots_per_mtp);
-+
-+	uint32_t y = dal_fixed31_32_ceil(
-+		dal_fixed31_32_shl(
-+			dal_fixed31_32_sub_int(
-+				avg_time_slots_per_mtp,
-+				x),
-+			26));
-+
-+	{
-+		const uint32_t addr = mmDP_MSE_RATE_CNTL +
-+				fe_engine_offsets[engine];
-+		uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			x,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_X);
-+
-+		set_reg_field_value(
-+			value,
-+			y,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_Y);
-+
-+		dal_write_reg(enc->ctx, addr, value);
- 	}
- 
--	switch (signal) {
--	case SIGNAL_TYPE_DVI_SINGLE_LINK:
--	case SIGNAL_TYPE_DVI_DUAL_LINK:
--		/* set signal format */
--		set_tmds_stream_attributes(
--			enc, enc->id, signal,
--			crtc_timing);
-+	/* wait for update to be completed on the link
-+	 * i.e. DP_MSE_RATE_UPDATE_PENDING field (read only)
-+	 * is reset to 0 (not pending) */
-+	{
-+		const uint32_t addr = mmDP_MSE_RATE_UPDATE +
-+			fe_engine_offsets[engine];
-+		uint32_t value, field;
-+		uint32_t retries = 0;
-+
-+		do {
-+			value = dal_read_reg(enc->ctx, addr);
-+
-+			field = get_reg_field_value(
-+					value,
-+					DP_MSE_RATE_UPDATE,
-+					DP_MSE_RATE_UPDATE_PENDING);
-+
-+			if (!(field &
-+			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
-+				break;
-+
-+			dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+			++retries;
-+		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+	}
-+}
-+
-+
-+/**
-+* set_afmt_memory_power_state
-+*
-+* @brief
-+*  Power up audio formatter memory that is mapped to specified DIG
-+*/
-+void dce110_stream_encoder_set_afmt_memory_power_state(
-+	const struct dc_context *ctx,
-+	enum engine_id id,
-+	bool enable)
-+{
-+	uint32_t value;
-+	uint32_t mem_pwr_force;
-+
-+	value = dal_read_reg(ctx, mmDCO_MEM_PWR_CTRL);
-+
-+	if (enable)
-+		mem_pwr_force = 0;
-+	else
-+		mem_pwr_force = 3;
-+
-+	/* force shutdown mode for appropriate AFMT memory */
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		set_reg_field_value(
-+			value,
-+			mem_pwr_force,
-+			DCO_MEM_PWR_CTRL,
-+			HDMI0_MEM_PWR_FORCE);
- 		break;
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--		/* set signal format */
--		set_tmds_stream_attributes(
--			enc, enc->id, signal,
--			crtc_timing);
--		/* setup HDMI engine */
--		setup_hdmi(
--			enc, enc->id, crtc_timing);
-+	case ENGINE_ID_DIGB:
-+		set_reg_field_value(
-+			value,
-+			mem_pwr_force,
-+			DCO_MEM_PWR_CTRL,
-+			HDMI1_MEM_PWR_FORCE);
- 		break;
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		/* set signal format */
--		set_dp_stream_attributes(enc, enc->id, crtc_timing);
-+	case ENGINE_ID_DIGC:
-+		set_reg_field_value(
-+			value,
-+			mem_pwr_force,
-+			DCO_MEM_PWR_CTRL,
-+			HDMI2_MEM_PWR_FORCE);
- 		break;
- 	default:
-+		dal_logger_write(
-+			ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Invalid Engine Id\n",
-+			__func__);
- 		break;
- 	}
- 
--	return ENCODER_RESULT_OK;
-+	dal_write_reg(ctx, mmDCO_MEM_PWR_CTRL, value);
- }
- 
--void dce110_stream_encoder_update_info_packets(
-+void dce110_stream_encoder_update_hdmi_info_packets(
- 	struct stream_encoder *enc,
--	enum signal_type signal,
- 	const struct encoder_info_frame *info_frame)
- {
--	if (dc_is_hdmi_signal(signal)) {
--		update_avi_info_packet(
--			enc,
--			enc->id,
--			signal,
--			&info_frame->avi);
--		update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor);
--		update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut);
--		update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd);
--	} else if (dc_is_dp_signal(signal))
--		update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc);
-+	update_avi_info_packet(
-+		enc,
-+		enc->id,
-+		&info_frame->avi);
-+	update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor);
-+	update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut);
-+	update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd);
- }
- 
--void dce110_stream_encoder_stop_info_packets(
-+void dce110_stream_encoder_update_dp_info_packets(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
--	enum signal_type signal)
-+	const struct encoder_info_frame *info_frame)
- {
--	if (dc_is_hdmi_signal(signal))
--		stop_hdmi_info_packets(
--			enc->ctx,
--			fe_engine_offsets[engine]);
--	else if (dc_is_dp_signal(signal))
--		stop_dp_info_packets(
--			enc->ctx,
--			fe_engine_offsets[engine]);
-+	update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc);
- }
- 
--/*
-- * @brief
-- * Output blank data,
-- * prevents output of the actual surface data on active transmitter
-- */
--enum encoder_result dce110_stream_encoder_blank(
--				struct stream_encoder *enc,
--				enum signal_type signal)
-+void dce110_stream_encoder_dp_blank(
-+	struct stream_encoder *enc)
- {
- 	enum engine_id engine = enc->id;
- 	const uint32_t addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
-@@ -1071,9 +1172,6 @@ enum encoder_result dce110_stream_encoder_blank(
- 	uint32_t retries = 0;
- 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
- 
--	if (!dc_is_dp_signal(signal))
--		return ENCODER_RESULT_OK;
--
- 	/* Note: For CZ, we are changing driver default to disable
- 	 * stream deferred to next VBLANK. If results are positive, we
- 	 * will make the same change to all DCE versions. There are a
-@@ -1122,26 +1220,13 @@ enum encoder_result dce110_stream_encoder_blank(
- 	 * complete, stream status will be stuck in video stream enabled state,
- 	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
- 	dp_steer_fifo_reset(enc->ctx, engine, true);
--
--	return ENCODER_RESULT_OK;
- }
- 
--/*
-- * @brief
-- * Stop sending blank data,
-- * output the actual surface data on active transmitter
-- */
--enum encoder_result dce110_stream_encoder_unblank(
-+/* output video stream to link encoder */
-+void dce110_stream_encoder_dp_unblank(
- 	struct stream_encoder *enc,
- 	const struct encoder_unblank_param *param)
- {
--	bool is_dp_signal = param->signal == SIGNAL_TYPE_DISPLAY_PORT
--		|| param->signal == SIGNAL_TYPE_DISPLAY_PORT_MST
--		|| param->signal == SIGNAL_TYPE_EDP;
--
--	if (!is_dp_signal)
--		return ENCODER_RESULT_OK;
--
- 	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
- 		uint32_t n_vid = 0x8000;
- 		uint32_t m_vid;
-@@ -1163,7 +1248,5 @@ enum encoder_result dce110_stream_encoder_unblank(
- 	}
- 
- 	unblank_dp_output(enc, enc->id);
--
--	return ENCODER_RESULT_OK;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 83df255..9c0302a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -28,7 +28,6 @@
- 
- struct stream_enc_init_data {
- 	enum engine_id stream_engine_id;
--	struct adapter_service *adapter_service;
- 	struct dc_context *ctx;
- };
- 
-@@ -37,27 +36,62 @@ struct stream_encoder *dce110_stream_encoder_create(
- 
- void dce110_stream_encoder_destroy(struct stream_encoder **enc);
- 
-+/***** HW programming ***********/
- enum encoder_result dce110_stream_encoder_setup(
- 	struct stream_encoder *enc,
- 	struct dc_crtc_timing *crtc_timing,
- 	enum signal_type signal,
- 	bool enable_audio);
- 
--void dce110_stream_encoder_update_info_packets(
-+void dce110_stream_encoder_stop_hdmi_info_packets(
-+	struct dc_context *ctx,
-+	enum engine_id engine);
-+
-+void dce110_stream_encoder_stop_dp_info_packets(
-+	struct dc_context *ctx,
-+	enum engine_id engine);
-+
-+
-+/* setup stream encoder in dp mode */
-+void dce110_stream_encoder_dp_set_stream_attribute(
- 	struct stream_encoder *enc,
--	enum signal_type signal,
--	const struct encoder_info_frame *info_frame);
-+	struct dc_crtc_timing *crtc_timing);
-+
-+/* setup stream encoder in hdmi mode */
-+void dce110_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing);
- 
--void dce110_stream_encoder_stop_info_packets(
-+/* setup stream encoder in dvi mode */
-+void dce110_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing);
-+
-+/* set throttling for DP MST */
-+void dce110_stream_encoder_set_mst_bandwidth(
- 	struct stream_encoder *enc,
- 	enum engine_id engine,
--	enum signal_type signal);
-+	struct fixed31_32 avg_time_slots_per_mtp);
-+
-+void dce110_stream_encoder_set_afmt_memory_power_state(
-+	const struct dc_context *ctx,
-+	enum engine_id id,
-+	bool enable);
- 
--enum encoder_result dce110_stream_encoder_blank(
-+void dce110_stream_encoder_update_hdmi_info_packets(
- 	struct stream_encoder *enc,
--	enum signal_type signal);
-+	const struct encoder_info_frame *info_frame);
-+
-+void dce110_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame);
-+
-+/* output blank/idle stream to link encoder */
-+void dce110_stream_encoder_dp_blank(
-+	struct stream_encoder *enc);
- 
--enum encoder_result dce110_stream_encoder_unblank(
-+/* output video stream to link encoder */
-+void dce110_stream_encoder_dp_unblank(
- 	struct stream_encoder *enc,
- 	const struct encoder_unblank_param *param);
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_types.h b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-index 2897a1d..e32498d 100644
---- a/drivers/gpu/drm/amd/dal/include/encoder_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-@@ -134,7 +134,6 @@ struct encoder_pre_enable_output_param {
- struct encoder_unblank_param {
- 	struct hw_crtc_timing crtc_timing;
- 	struct link_settings link_settings;
--	enum signal_type signal;
- };
- 
- /*
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0521-drm-amd-dal-atomic-validate-fix.patch b/common/recipes-kernel/linux/files/0521-drm-amd-dal-atomic-validate-fix.patch
deleted file mode 100644
index ee478073..00000000
--- a/common/recipes-kernel/linux/files/0521-drm-amd-dal-atomic-validate-fix.patch
+++ /dev/null
@@ -1,719 +0,0 @@
-From ba1bf08179af26ce8a1d8ac3b597085aa5424c13 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 19 Nov 2015 14:35:10 -0500
-Subject: [PATCH 0521/1110] drm/amd/dal: atomic validate fix
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 379 ++++++++++++---------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |  10 +-
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c |   4 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  26 +-
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |   2 +-
- 6 files changed, 235 insertions(+), 188 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 59a6a28..1b46426 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -337,7 +337,7 @@ static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
- 	}
- }
- static bool fill_rects_from_plane_state(
--	struct drm_plane_state *state,
-+	const struct drm_plane_state *state,
- 	struct dc_surface *surface)
- {
- 	surface->src_rect.x = state->src_x >> 16;
-@@ -388,7 +388,7 @@ static bool fill_rects_from_plane_state(
- 	return true;
- }
- static bool get_fb_info(
--	struct amdgpu_framebuffer *amdgpu_fb,
-+	const struct amdgpu_framebuffer *amdgpu_fb,
- 	uint64_t *tiling_flags,
- 	uint64_t *fb_location)
- {
-@@ -412,11 +412,11 @@ static bool get_fb_info(
- }
- static void fill_plane_attributes_from_fb(
- 	struct dc_surface *surface,
--	struct amdgpu_framebuffer *amdgpu_fb)
-+	const struct amdgpu_framebuffer *amdgpu_fb)
- {
- 	uint64_t tiling_flags;
- 	uint64_t fb_location;
--	struct drm_framebuffer *fb = &amdgpu_fb->base;
-+	const struct drm_framebuffer *fb = &amdgpu_fb->base;
- 
- 	get_fb_info(
- 		amdgpu_fb,
-@@ -495,7 +495,7 @@ static void fill_plane_attributes_from_fb(
- }
- 
- static void fill_gamma_from_crtc(
--	struct drm_crtc *crtc,
-+	const struct drm_crtc *crtc,
- 	struct dc_surface *dc_surface)
- {
- 	int i;
-@@ -524,10 +524,10 @@ static void fill_gamma_from_crtc(
- }
- 
- static void fill_plane_attributes(
--	struct dc_surface *surface,
--	struct drm_crtc *crtc)
-+			struct dc_surface *surface,
-+			const struct drm_crtc *crtc)
- {
--	struct amdgpu_framebuffer *amdgpu_fb =
-+	const struct amdgpu_framebuffer *amdgpu_fb =
- 		to_amdgpu_framebuffer(crtc->primary->state->fb);
- 	fill_rects_from_plane_state(crtc->primary->state, surface);
- 	fill_plane_attributes_from_fb(
-@@ -538,33 +538,11 @@ static void fill_plane_attributes(
- 	if (crtc->mode.private_flags &
- 			AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
- 		fill_gamma_from_crtc(crtc, surface);
--		/* reset trigger of gamma */
--		crtc->mode.private_flags &=
--			~AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
- 	}
- }
- 
- /*****************************************************************************/
- 
--struct amdgpu_connector *aconnector_from_drm_crtc(
--		struct drm_crtc *crtc,
--		struct drm_atomic_state *state)
--{
--	struct drm_connector *connector;
--	struct amdgpu_connector *aconnector;
--	struct drm_connector_state *conn_state;
--	uint8_t i;
--
--	for_each_connector_in_state(state, connector, conn_state, i) {
--		aconnector = to_amdgpu_connector(connector);
--		if (connector->state->crtc == crtc)
--				return aconnector;
--	}
--
--	/* If we get here, not found. */
--	return NULL;
--}
--
- struct amdgpu_connector *aconnector_from_drm_crtc_id(
- 		const struct drm_crtc *crtc)
- {
-@@ -592,11 +570,10 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id(
- 
- static void dm_dc_surface_commit(
- 		struct dc *dc,
--		struct drm_crtc *crtc,
--		struct amdgpu_framebuffer *afb)
-+		struct drm_crtc *crtc)
- {
- 	struct dc_surface *dc_surface;
--	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+	const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- 	struct dc_target *dc_target = acrtc->target;
- 
- 	if (!dc_target) {
-@@ -619,6 +596,12 @@ static void dm_dc_surface_commit(
- 	/* Surface programming */
- 
- 	fill_plane_attributes(dc_surface, crtc);
-+	if (crtc->mode.private_flags &
-+		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
-+		/* reset trigger of gamma */
-+		crtc->mode.private_flags &=
-+			~AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
-+	}
- 
- 	if (false == dc_commit_surfaces_to_target(
- 			dc,
-@@ -1343,8 +1326,8 @@ static void clear_unrelated_fields(struct drm_plane_state *state)
- }
- 
- static bool page_flip_needed(
--	struct drm_plane_state *new_state,
--	struct drm_plane_state *old_state)
-+	const struct drm_plane_state *new_state,
-+	const struct drm_plane_state *old_state)
- {
- 	struct drm_plane_state old_state_tmp;
- 	struct drm_plane_state new_state_tmp;
-@@ -1499,70 +1482,6 @@ fail:
- 
- }
- 
--int dm_add_surface_to_validation_set(struct drm_plane *plane,
--		    struct drm_plane_state *state, struct dc_surface **surface)
--{
--	int res;
--
--	struct amdgpu_framebuffer *afb;
--	struct amdgpu_connector *aconnector;
--	struct drm_crtc *crtc;
--	struct drm_framebuffer *fb;
--
--	struct drm_device *dev;
--	struct amdgpu_device *adev;
--
--	res = -EINVAL;
--
--	if (NULL == plane || NULL == state) {
--		DRM_ERROR("invalid parameters dm_plane_atomic_check\n");
--		return res;
--	}
--
--	crtc = state->crtc;
--	fb = state->fb;
--
--
--	afb = to_amdgpu_framebuffer(fb);
--
--	if (NULL == state->crtc) {
--		return res;
--	}
--
--	aconnector = aconnector_from_drm_crtc(crtc, state->state);
--
--	if (NULL == aconnector) {
--		DRM_ERROR("Connector is NULL in dm_plane_atomic_check\n");
--		return res;
--	}
--
--	if (NULL == aconnector->dc_sink) {
--		DRM_ERROR("dc_sink is NULL in dm_plane_atomic_check\n");
--		return res;
--	}
--	dev  = state->crtc->dev;
--	adev = dev->dev_private;
--
--	*surface = dc_create_surface(adev->dm.dc);
--	if (NULL == *surface){
--		DRM_ERROR("surface is NULL\n");
--		return res;
--	}
--
--	if (!fill_rects_from_plane_state( state, *surface)) {
--		DRM_ERROR("Failed to fill surface!\n");
--		goto fail;
--	}
--
--	fill_plane_attributes_from_fb(*surface, afb);
--
--	return MODE_OK;
--
--fail:
--	dc_surface_release(*surface);
--	return res;
--}
--
- static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
- 	.prepare_fb = dm_plane_helper_prepare_fb,
- 	.cleanup_fb = dm_plane_helper_cleanup_fb,
-@@ -1951,8 +1870,7 @@ enum dm_commit_action {
- 	DM_COMMIT_ACTION_SET
- };
- 
--enum dm_commit_action get_dm_commit_action(struct drm_crtc *crtc,
--		struct drm_crtc_state *state)
-+static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
- {
- 	/* mode changed means either actually mode changed or enabled changed */
- 	/* active changed means dpms changed */
-@@ -2103,7 +2021,7 @@ int amdgpu_dm_atomic_commit(
- 	struct amdgpu_display_manager *dm = &adev->dm;
- 	struct drm_plane *plane;
- 	struct drm_plane_state *old_plane_state;
--	uint32_t i;
-+	uint32_t i, j;
- 	int32_t ret;
- 	uint32_t commit_targets_count = 0;
- 	uint32_t new_crtcs_count = 0;
-@@ -2140,25 +2058,34 @@ int amdgpu_dm_atomic_commit(
- 	/* update changed items */
- 	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
- 		struct amdgpu_crtc *acrtc;
--		struct amdgpu_connector *aconnector;
-+		struct amdgpu_connector *aconnector = NULL;
- 		enum dm_commit_action action;
- 		struct drm_crtc_state *new_state = crtc->state;
-+		struct drm_connector *connector;
-+		struct drm_connector_state *old_con_state;
- 
- 		acrtc = to_amdgpu_crtc(crtc);
--		aconnector = aconnector_from_drm_crtc(crtc, state);
-+
-+		for_each_connector_in_state(state,
-+				connector, old_con_state, j) {
-+			if (connector->state->crtc == crtc) {
-+				aconnector = to_amdgpu_connector(connector);
-+				break;
-+			}
-+		}
- 
- 		/* handles headless hotplug case, updating new_state and
- 		 * aconnector as needed
- 		 */
- 		handle_headless_hotplug(acrtc, new_state, &aconnector);
--
--		action = get_dm_commit_action(crtc, new_state);
--
- 		if (!aconnector) {
--			DRM_ERROR("Can't find connector for crtc %d\n", acrtc->crtc_id);
-+			DRM_ERROR("Can't find connector for crtc %d\n",
-+							acrtc->crtc_id);
- 			break;
- 		}
- 
-+		action = get_dm_commit_action(new_state);
-+
- 		switch (action) {
- 		case DM_COMMIT_ACTION_DPMS_ON:
- 		case DM_COMMIT_ACTION_SET: {
-@@ -2167,7 +2094,7 @@ int amdgpu_dm_atomic_commit(
- 				create_target_for_sink(
- 					aconnector,
- 					&crtc->state->mode);
--
-+			DRM_DEBUG_KMS("Atomic commit: SET.\n");
- 			if (!new_target) {
- 				/*
- 				 * this could happen because of issues with
-@@ -2218,6 +2145,7 @@ int amdgpu_dm_atomic_commit(
- 
- 		case DM_COMMIT_ACTION_DPMS_OFF:
- 		case DM_COMMIT_ACTION_RESET:
-+			DRM_DEBUG_KMS("Atomic commit: RESET.\n");
- 			/* i.e. reset mode */
- 			if (acrtc->target) {
- 				manage_dm_interrupts(adev, acrtc, false);
-@@ -2266,10 +2194,7 @@ int amdgpu_dm_atomic_commit(
- 					crtc->state->event,
- 					0);
- 			else
--				dm_dc_surface_commit(
--					dm->dc,
--					crtc,
--					to_amdgpu_framebuffer(fb));
-+				dm_dc_surface_commit(dm->dc, crtc);
- 		}
- 	}
- 
-@@ -2295,102 +2220,224 @@ int amdgpu_dm_atomic_commit(
- 	return 0;
- }
- 
-+static uint32_t add_val_sets_surface(
-+	struct dc_validation_set *val_sets,
-+	uint32_t set_count,
-+	const struct dc_target *target,
-+	const struct dc_surface *surface)
-+{
-+	uint32_t i = 0;
-+
-+	while (i < set_count) {
-+		if (val_sets[i].target == target)
-+			break;
-+		++i;
-+	}
-+
-+	val_sets[i].surfaces[val_sets[i].surface_count] = surface;
-+	val_sets[i].surface_count++;
-+
-+	return val_sets[i].surface_count;
-+}
-+
-+static uint32_t update_in_val_sets_target(
-+	struct dc_validation_set *val_sets,
-+	uint32_t set_count,
-+	const struct dc_target *old_target,
-+	const struct dc_target *new_target)
-+{
-+	uint32_t i = 0;
-+
-+	while (i < set_count) {
-+		if (val_sets[i].target == old_target)
-+			break;
-+		++i;
-+	}
-+
-+	val_sets[i].target = new_target;
-+
-+	if (i == set_count) {
-+		/* nothing found. add new one to the end */
-+		return set_count + 1;
-+	}
-+
-+	return set_count;
-+}
-+
-+static uint32_t remove_from_val_sets(
-+	struct dc_validation_set *val_sets,
-+	uint32_t set_count,
-+	const struct dc_target *target)
-+{
-+	uint32_t i = 0;
-+
-+	while (i < set_count) {
-+		if (val_sets[i].target == target)
-+			break;
-+		++i;
-+	}
-+
-+	if (i == set_count) {
-+		/* nothing found */
-+		return set_count;
-+	}
-+
-+	memmove(
-+		&val_sets[i],
-+		&val_sets[i + 1],
-+		sizeof(struct dc_validation_set *) * (set_count - i - 1));
-+
-+	return set_count - 1;
-+}
-+
- int amdgpu_dm_atomic_check(struct drm_device *dev,
--			    struct drm_atomic_state *s)
-+			struct drm_atomic_state *state)
- {
- 	struct drm_crtc *crtc;
- 	struct drm_crtc_state *crtc_state;
- 	struct drm_plane *plane;
- 	struct drm_plane_state *plane_state;
--	struct drm_connector *connector;
--	struct drm_connector_state *conn_state;
--	int i, j, ret, set_count;
-+	int i, j, ret, set_count, new_target_count;
- 	struct dc_validation_set set[MAX_TARGET_NUM] = {{ 0 }};
-+	struct dc_target *new_targets[MAX_TARGET_NUM] = { 0 };
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct amdgpu_connector *aconnector = NULL;
--	set_count = 0;
-+	struct dc *dc = adev->dm.dc;
- 
--	ret = drm_atomic_helper_check(dev,s);
-+	ret = drm_atomic_helper_check(dev, state);
- 
- 	if (ret) {
--		DRM_ERROR("Atomic state integrity validation failed with error :%d !\n",ret);
-+		DRM_ERROR("Atomic state validation failed with error :%d !\n",
-+				ret);
- 		return ret;
- 	}
- 
- 	ret = -EINVAL;
- 
--	if (s->num_connector > MAX_TARGET_NUM) {
-+	if (state->num_connector > MAX_TARGET_NUM) {
- 		DRM_ERROR("Exceeded max targets number !\n");
- 		return ret;
- 	}
- 
-+	/* copy existing configuration */
-+	new_target_count = 0;
-+	set_count = 0;
-+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+
-+		if (acrtc->target) {
-+			set[set_count].target = acrtc->target;
-+			++set_count;
-+		}
-+	}
- 
--	for_each_crtc_in_state(s, crtc, crtc_state, i) {
-+	/* update changed items */
-+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
-+		struct amdgpu_crtc *acrtc = NULL;
-+		struct amdgpu_connector *aconnector = NULL;
- 		enum dm_commit_action action;
--		aconnector = NULL;
-+		struct drm_connector *connector;
-+		struct drm_connector_state *con_state;
- 
--		action = get_dm_commit_action(crtc, crtc_state);
--		if (action == DM_COMMIT_ACTION_DPMS_OFF || DM_COMMIT_ACTION_RESET)
--			continue;
-+		acrtc = to_amdgpu_crtc(crtc);
- 
--		for_each_connector_in_state(s, connector, conn_state, j) {
--			if (conn_state->crtc && conn_state->crtc == crtc) {
-+		for_each_connector_in_state(state, connector, con_state, j) {
-+			if (con_state->crtc == crtc) {
- 				aconnector = to_amdgpu_connector(connector);
--				/*I assume at most once connector for CRTC*/
- 				break;
- 			}
- 		}
- 
--		/*In this case validate against existing connector if possible*/
--		if (!aconnector)
--			aconnector = aconnector_from_drm_crtc(crtc, s);
-+		/*TODO:
-+		handle_headless_hotplug(acrtc, crtc_state, &aconnector);*/
- 
--		if (!aconnector || !aconnector->dc_sink)
--			continue;
-+		action = get_dm_commit_action(crtc_state);
- 
--		set[set_count].surface_count = 0;
--		ret = dm_create_validation_set_for_target(&aconnector->base,
--								&crtc_state->adjusted_mode, &set[set_count]);
--		if (ret)
--		{
--			DRM_ERROR("Creation of validation set target failed !\n");
--			goto end;
-+		switch (action) {
-+		case DM_COMMIT_ACTION_DPMS_ON:
-+		case DM_COMMIT_ACTION_SET: {
-+			struct drm_display_mode mode = crtc_state->mode;
-+			struct dc_target *new_target = NULL;
-+
-+			if (!aconnector) {
-+				DRM_ERROR("Can't find connector for crtc %d\n",
-+								acrtc->crtc_id);
-+				goto connector_not_found;
-+			}
-+			new_target =
-+				create_target_for_sink(
-+					aconnector,
-+					&mode);
-+			new_targets[new_target_count] = new_target;
-+
-+			set_count = update_in_val_sets_target(
-+					set,
-+					set_count,
-+					acrtc->target,
-+					new_target);
-+			new_target_count++;
-+			break;
- 		}
- 
--		for_each_plane_in_state(s, plane, plane_state, j) {
--			/*Since we use drm_atomic_helper_set_config as our hook we garnteed to have the mask in correct state*/
--			if (crtc_state->plane_mask & (1 << drm_plane_index(plane))) {
--				if (set[set_count].surface_count == MAX_SURFACE_NUM) {
--					DRM_ERROR("Exceeded max surfaces number per target!\n");
--					ret = MODE_OK;
--					goto end;
--				}
-+		case DM_COMMIT_ACTION_NOTHING:
-+			break;
-+		case DM_COMMIT_ACTION_DPMS_OFF:
-+		case DM_COMMIT_ACTION_RESET:
-+			/* i.e. reset mode */
-+			if (acrtc->target) {
-+				set_count = remove_from_val_sets(
-+						set,
-+						set_count,
-+						acrtc->target);
-+			}
-+			break;
-+		}
-+	}
-+
- 
--				ret = dm_add_surface_to_validation_set(plane,plane_state,
--						(struct dc_surface **)&(set[set_count].surfaces[set[set_count].surface_count]));
-+	for (i = 0; i < set_count; i++) {
-+		for_each_plane_in_state(state, plane, plane_state, j) {
-+			struct drm_plane_state *old_plane_state = plane->state;
-+			struct drm_framebuffer *fb = plane_state->fb;
-+			struct amdgpu_crtc *acrtc =
-+					to_amdgpu_crtc(plane_state->crtc);
- 
--				if (ret) {
--					DRM_ERROR("Failed to add surface  for validation!\n");
--					goto end;
--				}
-+			if (!fb || acrtc->target != set[i].target)
-+				continue;
-+			if (!plane_state->crtc->state->planes_changed)
-+				continue;
- 
--				set[set_count].surface_count++;
-+			if (!page_flip_needed(plane_state, old_plane_state)) {
-+				struct dc_surface *surface =
-+					dc_create_surface(dc);
-+
-+				fill_plane_attributes(
-+						surface, plane_state->crtc);
-+				add_val_sets_surface(
-+					set,
-+					set_count,
-+					acrtc->target,
-+					surface);
- 			}
- 		}
- 
--		set_count++;
- 	}
- 
--	if (!set_count || dc_validate_resources(adev->dm.dc, set, set_count)) {
--		ret = MODE_OK;
--	}
--end:
-+	if (set_count == 0 || dc_validate_resources(dc, set, set_count))
-+		ret = 0;
- 
--	for (i = 0; i < MAX_TARGET_NUM; i++) {
--		if (set[i].target)
--			dc_target_release((struct dc_target *)set[i].target);
-+connector_not_found:
-+	for (i = 0; i < set_count; i++) {
-+		for (j = 0; j < set[i].surface_count; j++) {
-+			dc_surface_release(
-+				(struct dc_surface *)set[i].surfaces[j]);
-+		}
- 	}
-+	for (i = 0; i < new_target_count; i++)
-+		dc_target_release(new_targets[i]);
- 
--	return ret;
-+	if (ret != 0)
-+		DRM_ERROR("Atomic check failed.\n");
- 
-+	return ret;
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index bda39be..0df4636 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -59,25 +59,17 @@ void dm_add_display_info(
- 
- int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
- 
--struct amdgpu_connector *aconnector_from_drm_crtc(
--		struct drm_crtc *crtc,
--		struct drm_atomic_state *state);
--
- int amdgpu_dm_atomic_commit(
- 	struct drm_device *dev,
- 	struct drm_atomic_state *state,
- 	bool async);
- int amdgpu_dm_atomic_check(struct drm_device *dev,
--			    	struct drm_atomic_state *state);
-+				struct drm_atomic_state *state);
- 
- int dm_create_validation_set_for_target(
- 	struct drm_connector *connector,
- 	struct drm_display_mode *mode,
- 	struct dc_validation_set *val_set);
--int dm_add_surface_to_validation_set(
--	struct drm_plane *plane,
--	struct drm_plane_state *state,
--	struct dc_surface **surface);
- 
- void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
- struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 5c72a66..346028a 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3457,7 +3457,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 				bw_results_internal->cpup_state_change_enable;
- 		calcs_output->stutter_mode_enable =
- 				bw_results_internal->stutter_mode_enable;
--		calcs_output->dispclk =
-+		calcs_output->dispclk_khz =
- 				mul(bw_results_internal->dispclk,
- 					int_to_fixed(1000)).value >> 24;
- 		calcs_output->required_sclk =
-@@ -3474,7 +3474,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 		calcs_output->cpuc_state_change_enable = true;
- 		calcs_output->cpup_state_change_enable = true;
- 		calcs_output->stutter_mode_enable = true;
--		calcs_output->dispclk = 0;
-+		calcs_output->dispclk_khz = 0;
- 		calcs_output->required_sclk = 0;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 394b645..24e35cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1237,7 +1237,7 @@ static void set_display_clock(struct validate_context *context)
- 				context->res_ctx.min_clocks.min_dclk_khz);*/
- 	} else
- 		dal_display_clock_set_clock(context->res_ctx.pool.display_clock,
--				context->bw_results.dispclk);
-+				context->bw_results.dispclk_khz);
- 
- 	/* TODO: When changing display engine clock, DMCU WaitLoop must be
- 	 * reconfigured in order to maintain the same delays within DMCU
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 0499976..6eb8152 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -44,6 +44,9 @@ enum dce110_clk_src_array_id {
- 	DCE110_CLK_SRC_TOTAL
- };
- 
-+#define DCE110_MAX_DISPCLK 643000
-+#define DCE110_MAX_SCLK 626000
-+
- static void set_vendor_info_packet(struct core_stream *stream,
- 		struct hw_info_packet *info_packet)
- {
-@@ -1197,22 +1200,27 @@ enum dc_status dce110_validate_bandwidth(
- 		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
- 		"%s: Start bandwidth calculations",
- 		__func__);
--	if (true == bw_calcs(
--					dc->ctx,
--					&dc->bw_dceip,
--					&dc->bw_vbios,
--					&context->bw_mode_data,
--					&context->bw_results))
-+	if (!bw_calcs(
-+			dc->ctx,
-+			&dc->bw_dceip,
-+			&dc->bw_vbios,
-+			&context->bw_mode_data,
-+			&context->bw_results))
-+		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-+	else
- 		result =  DC_OK;
--	else {
-+
-+
-+	if (context->bw_results.dispclk_khz > DCE110_MAX_DISPCLK
-+		|| context->bw_results.required_sclk > DCE110_MAX_SCLK)
- 		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-+
-+	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
- 		dal_logger_write(dc->ctx->logger,
- 			LOG_MAJOR_BWM,
- 			LOG_MINOR_BWM_MODE_VALIDATION,
- 			"%s: Bandwidth validation failed!",
- 			__func__);
--	}
--
- 
- 	dal_logger_write(dc->ctx->logger,
- 		LOG_MAJOR_BWM,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index f7315c6..a0c0fef 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -434,7 +434,7 @@ struct bw_calcs_output {
- 	struct bw_watermarks stutter_exit_watermark[4];
- 	struct bw_watermarks nbp_state_change_watermark[4];
- 	uint32_t required_sclk;
--	uint32_t dispclk;
-+	uint32_t dispclk_khz;
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0522-drm-amd-dal-fix-mem_input-naming-and-function-order.patch b/common/recipes-kernel/linux/files/0522-drm-amd-dal-fix-mem_input-naming-and-function-order.patch
deleted file mode 100644
index 36157d72..00000000
--- a/common/recipes-kernel/linux/files/0522-drm-amd-dal-fix-mem_input-naming-and-function-order.patch
+++ /dev/null
@@ -1,218 +0,0 @@
-From 76232e98efcee158a5b5aae58ea48532b458d2f7 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 25 Nov 2015 16:22:58 -0500
-Subject: [PATCH 0522/1110] drm/amd/dal: fix mem_input naming and function
- order
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 14 ++++-----
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 20 +++++++------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   | 33 +++++++++++-----------
- 3 files changed, 35 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 24e35cd..dddc6e2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -897,7 +897,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	}
- 
- 	/*TODO: mst support - use total stream count*/
--	dce110_allocate_dmif_buffer(stream->mi,
-+	dce110_mem_input_allocate_dmif_buffer(stream->mi,
- 			&stream->public.timing,
- 			context->target_count);
- 
-@@ -1259,17 +1259,17 @@ static void set_displaymarks(
- 		for (j = 0; j < target->stream_count; j++) {
- 			struct core_stream *stream = target->streams[j];
- 
--			dce110_program_nbp_watermark(
-+			dce110_mem_input_program_nbp_watermark(
- 				stream->mi,
- 				context->bw_results
- 				.nbp_state_change_watermark[total_streams]);
- 
--			dce110_program_stutter_watermark(
-+			dce110_mem_input_program_stutter_watermark(
- 				stream->mi,
- 				context->bw_results
- 					.stutter_exit_watermark[total_streams]);
- 
--			dce110_program_urgency_watermark(
-+			dce110_mem_input_program_urgency_watermark(
- 				stream->mi,
- 				context->bw_results
- 					.urgent_watermark[total_streams],
-@@ -1293,7 +1293,7 @@ static void set_safe_displaymarks(struct validate_context *context)
- 		for (j = 0; j < target->stream_count; j++) {
- 			struct core_stream *stream = target->streams[j];
- 
--			dce110_program_safe_display_marks(stream->mi);
-+			dce110_mem_input_program_safe_display_marks(stream->mi);
- 		}
- 	}
- }
-@@ -1588,7 +1588,7 @@ static bool set_plane_config(
- 			PIPE_LOCK_CONTROL_SURFACE,
- 			true);
- 
--	dce110_program_pix_dur(mi, dc_crtc_timing->pix_clk_khz);
-+	dce110_mem_input_program_pix_dur(mi, dc_crtc_timing->pix_clk_khz);
- 
- 	dce110_timing_generator_program_blanking(tg, dc_crtc_timing);
- 
-@@ -1679,7 +1679,7 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 	core_link_disable(stream);
- 	dce110_timing_generator_blank_crtc(stream->tg);
- 	dce110_timing_generator_disable_crtc(stream->tg);
--	dce110_deallocate_dmif_buffer(stream->mi, context->target_count);
-+	dce110_mem_input_deallocate_dmif_buffer(stream->mi, context->target_count);
- 	dce110_transform_set_scaler_bypass(stream->xfm);
- 	disable_stereo_mixer(stream->ctx);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 50354a9..e84a1ae 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -533,7 +533,7 @@ static void program_urgency_watermark(
- 	dal_write_reg(ctx, urgency_addr, urgency_cntl);
- }
- 
--void dce110_program_stutter_watermark(
-+void dce110_mem_input_program_stutter_watermark(
- 	struct mem_input *mi,
- 	struct bw_watermarks marks)
- {
-@@ -599,7 +599,7 @@ void dce110_program_stutter_watermark(
- 	dal_write_reg(ctx, stutter_addr, stutter_cntl);
- }
- 
--void dce110_program_nbp_watermark(
-+void dce110_mem_input_program_nbp_watermark(
- 	struct mem_input *mi,
- 	struct bw_watermarks marks)
- {
-@@ -684,7 +684,7 @@ void dce110_program_nbp_watermark(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--void dce110_program_safe_display_marks(struct mem_input *mi)
-+void dce110_mem_input_program_safe_display_marks(struct mem_input *mi)
- {
- 	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
- 	struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
-@@ -692,12 +692,12 @@ void dce110_program_safe_display_marks(struct mem_input *mi)
- 
- 	program_urgency_watermark(
- 		mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK);
--	dce110_program_stutter_watermark(mi, max_marks);
--	dce110_program_nbp_watermark(mi, nbp_marks);
-+	dce110_mem_input_program_stutter_watermark(mi, max_marks);
-+	dce110_mem_input_program_nbp_watermark(mi, nbp_marks);
- 
- }
- 
--void dce110_program_urgency_watermark(
-+void dce110_mem_input_program_urgency_watermark(
- 	struct mem_input *mi,
- 	struct bw_watermarks marks,
- 	uint32_t h_total,
-@@ -758,7 +758,7 @@ static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
- 	return frame_time;
- }
- 
--void dce110_allocate_dmif_buffer(
-+void dce110_mem_input_allocate_dmif_buffer(
- 		struct mem_input *mi,
- 		struct dc_crtc_timing *timing,
- 		uint32_t paths_num)
-@@ -863,7 +863,8 @@ static void deallocate_dmif_buffer_helper(
- 			DMIF_BUFFERS_ALLOCATION_COMPLETED));
- }
- 
--void dce110_deallocate_dmif_buffer(struct mem_input *mi, uint32_t paths_num)
-+void dce110_mem_input_deallocate_dmif_buffer(
-+	struct mem_input *mi, uint32_t paths_num)
- {
- 	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
- 	uint32_t value;
-@@ -896,7 +897,8 @@ void dce110_deallocate_dmif_buffer(struct mem_input *mi, uint32_t paths_num)
- 	dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
- }
- 
--void dce110_program_pix_dur(struct mem_input *mi, uint32_t pix_clk_khz)
-+void dce110_mem_input_program_pix_dur(
-+	struct mem_input *mi, uint32_t pix_clk_khz)
- {
- 	uint64_t pix_dur;
- 	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 9c6d278..0d23c81 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -48,41 +48,42 @@ struct mem_input *dce110_mem_input_create(
- 
- void dce110_mem_input_destroy(struct mem_input **mem_input);
- 
--bool dce110_mem_input_program_surface_flip_and_addr(
--	struct mem_input *mem_input,
--	const struct dc_plane_address *address,
--	bool flip_immediate);
--
--bool  dce110_mem_input_program_surface_config(
--	struct mem_input *mem_input,
--	const struct dc_surface *surface);
-+void dce110_mem_input_program_safe_display_marks(struct mem_input *mi);
- 
--void dce110_program_nbp_watermark(
-+void dce110_mem_input_program_nbp_watermark(
- 	struct mem_input *mem_input,
- 	struct bw_watermarks marks);
- 
--void dce110_program_stutter_watermark(
-+void dce110_mem_input_program_stutter_watermark(
- 	struct mem_input *mem_input,
- 	struct bw_watermarks marks);
- 
--void dce110_program_urgency_watermark(
-+void dce110_mem_input_program_urgency_watermark(
- 	struct mem_input *mem_input,
- 	struct bw_watermarks marks,
- 	uint32_t h_total,
- 	uint32_t pixel_clk_in_khz,
- 	uint32_t pstate_blackout_duration_ns);
- 
--void dce110_program_safe_display_marks(struct mem_input *mi);
--
--void dce110_allocate_dmif_buffer(
-+void dce110_mem_input_allocate_dmif_buffer(
- 		struct mem_input *mem_input,
- 		struct dc_crtc_timing *timing,
- 		uint32_t paths_num);
- 
--void dce110_deallocate_dmif_buffer(
-+void dce110_mem_input_deallocate_dmif_buffer(
- 	struct mem_input *mem_input, uint32_t paths_num);
- 
--void dce110_program_pix_dur(
-+void dce110_mem_input_program_pix_dur(
- 	struct mem_input *mem_input, uint32_t pix_clk_khz);
- 
-+bool dce110_mem_input_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate);
-+
-+bool  dce110_mem_input_program_surface_config(
-+	struct mem_input *mem_input,
-+	const struct dc_surface *surface);
-+
-+
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0523-drm-amd-dal-Pass-in-adapter_service-to-stream-encode.patch b/common/recipes-kernel/linux/files/0523-drm-amd-dal-Pass-in-adapter_service-to-stream-encode.patch
deleted file mode 100644
index cf03f5c6..00000000
--- a/common/recipes-kernel/linux/files/0523-drm-amd-dal-Pass-in-adapter_service-to-stream-encode.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 0a37f0789f0a7bd36972ad1efa94419dd968c240 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 25 Nov 2015 17:50:31 -0500
-Subject: [PATCH 0523/1110] drm/amd/dal: Pass in adapter_service to stream
- encoder
-
-Fix BSOD issue.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c       | 1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h | 1 +
- 3 files changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 6eb8152..205cd22 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -628,6 +628,7 @@ bool dce110_construct_resource_pool(
- 		/* TODO: rework fragile code*/
- 		enc_init_data.stream_engine_id = i;
- 		enc_init_data.ctx = dc->ctx;
-+		enc_init_data.adapter_service = adapter_serv;
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
- 					&enc_init_data);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 37781ab..55be9f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -55,6 +55,7 @@ static void construct(
- {
- 	enc->ctx = init->ctx;
- 	enc->id = init->stream_engine_id;
-+	enc->adapter_service = init->adapter_service;
- }
- 
- static void update_avi_info_packet(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 9c0302a..285d70e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -28,6 +28,7 @@
- 
- struct stream_enc_init_data {
- 	enum engine_id stream_engine_id;
-+	struct adapter_service *adapter_service;
- 	struct dc_context *ctx;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0524-drm-amd-dal-add-missed-mst-callback-implementation.patch b/common/recipes-kernel/linux/files/0524-drm-amd-dal-add-missed-mst-callback-implementation.patch
deleted file mode 100644
index a7bae91d..00000000
--- a/common/recipes-kernel/linux/files/0524-drm-amd-dal-add-missed-mst-callback-implementation.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 75cf587ebebb4387e355c6626a6c6b8e30e16477 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 26 Nov 2015 18:40:13 +0800
-Subject: [PATCH 0524/1110] drm/amd/dal: add missed mst callback implementation
-
-Add new register_connector callback implementation
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c  | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 0838cca..a08468b 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -257,7 +257,6 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- {
- 	struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr);
- 	struct drm_device *dev = master->base.dev;
--	struct amdgpu_device *adev = dev->dev_private;
- 	struct amdgpu_connector *aconnector;
- 	struct drm_connector *connector;
- 
-@@ -281,11 +280,6 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
- 	drm_mode_connector_set_path_property(connector, pathprop);
- 
--	mutex_lock(&dev->mode_config.mutex);
--	drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
--	mutex_unlock(&dev->mode_config.mutex);
--
--	drm_connector_register(connector);
- 
- 	DRM_DEBUG_KMS(":%d\n", connector->base.id);
- 
-@@ -323,10 +317,24 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
- 	drm_kms_helper_hotplug_event(dev);
- }
- 
-+static void dm_dp_mst_register_connector(struct drm_connector *connector)
-+{
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	mutex_lock(&dev->mode_config.mutex);
-+	drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
-+	mutex_unlock(&dev->mode_config.mutex);
-+
-+	drm_connector_register(connector);
-+
-+}
-+
- struct drm_dp_mst_topology_cbs dm_mst_cbs = {
- 	.add_connector = dm_dp_add_mst_connector,
- 	.destroy_connector = dm_dp_destroy_mst_connector,
- 	.hotplug = dm_dp_mst_hotplug,
-+	.register_connector = dm_dp_mst_register_connector
- };
- 
- void amdgpu_dm_initialize_mst_connector(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0525-drm-amd-dal-Pass-in-Bios-Parser-instead-of-Adapter-S.patch b/common/recipes-kernel/linux/files/0525-drm-amd-dal-Pass-in-Bios-Parser-instead-of-Adapter-S.patch
deleted file mode 100644
index a2cb4edc..00000000
--- a/common/recipes-kernel/linux/files/0525-drm-amd-dal-Pass-in-Bios-Parser-instead-of-Adapter-S.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 1eab0b6a5a360910cb488fe9a964c058d3a0940a Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Thu, 26 Nov 2015 11:44:09 -0500
-Subject: [PATCH 0525/1110] drm/amd/dal: Pass in Bios Parser instead of Adapter
- Service
-
-In Stream Encoder to avoid calling the entire stack.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c       | 3 ++-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 5 ++---
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h | 2 +-
- drivers/gpu/drm/amd/dal/include/stream_encoder_types.h    | 2 +-
- 4 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 205cd22..ebae5e3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -628,7 +628,8 @@ bool dce110_construct_resource_pool(
- 		/* TODO: rework fragile code*/
- 		enc_init_data.stream_engine_id = i;
- 		enc_init_data.ctx = dc->ctx;
--		enc_init_data.adapter_service = adapter_serv;
-+		enc_init_data.bp = dal_adapter_service_get_bios_parser(
-+			adapter_serv);
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
- 					&enc_init_data);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 55be9f6..ac1a948 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -55,7 +55,7 @@ static void construct(
- {
- 	enc->ctx = init->ctx;
- 	enc->id = init->stream_engine_id;
--	enc->adapter_service = init->adapter_service;
-+	enc->bp = init->bp;
- }
- 
- static void update_avi_info_packet(
-@@ -854,8 +854,7 @@ enum encoder_result dce110_stream_encoder_setup(
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
- 	if (dal_bios_parser_encoder_control(
--			dal_adapter_service_get_bios_parser(
--			enc->adapter_service), &cntl) != BP_RESULT_OK)
-+			enc->bp, &cntl) != BP_RESULT_OK)
- 		return ENCODER_RESULT_ERROR;
- 
- 	return ENCODER_RESULT_OK;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 285d70e..d4477d1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -28,7 +28,7 @@
- 
- struct stream_enc_init_data {
- 	enum engine_id stream_engine_id;
--	struct adapter_service *adapter_service;
-+	struct bios_parser *bp;
- 	struct dc_context *ctx;
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h b/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-index 0d3e67c..c0bc656 100644
---- a/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-@@ -9,7 +9,7 @@
- 
- struct stream_encoder {
- 	enum engine_id id;
--	struct adapter_service *adapter_service;
-+	struct bios_parser *bp;
- 	struct dc_context *ctx;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0526-drm-amd-dal-MST-two-monitors-light-up-add-PHY-payloa.patch b/common/recipes-kernel/linux/files/0526-drm-amd-dal-MST-two-monitors-light-up-add-PHY-payloa.patch
deleted file mode 100644
index a5412898..00000000
--- a/common/recipes-kernel/linux/files/0526-drm-amd-dal-MST-two-monitors-light-up-add-PHY-payloa.patch
+++ /dev/null
@@ -1,500 +0,0 @@
-From 7bf1102eda7d1e5ef2eeec7a04fe9e91bf321dfa Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Mon, 23 Nov 2015 15:44:57 -0500
-Subject: [PATCH 0526/1110] drm/amd/dal: MST two monitors light up add PHY
- payload alloaction 2
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 116 ++++++++++++++++++++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  63 ++++++++++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  17 ++-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  40 ++++---
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   7 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   3 +
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h         |   2 +
- .../gpu/drm/amd/dal/include/link_service_types.h   |   9 +-
- 9 files changed, 228 insertions(+), 31 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index c3b6715..7a07af5 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -32,6 +32,8 @@
- #include <drm/drm_edid.h>
- 
- #include "dc_types.h"
-+#include "core_types.h"
-+#include "stream_encoder_types.h"
- #include "amdgpu.h"
- #include "dc.h"
- #include "dc_services.h"
-@@ -167,12 +169,14 @@ static struct amdgpu_connector *get_connector_for_link(
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
- 		const struct dc_sink *sink,
--		struct dp_mst_stream_allocation *alloc_entity,
-+		struct dp_mst_stream_allocation_table *table,
- 		bool enable)
- {
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-+	struct drm_connector *connector;
-+	struct amdgpu_crtc *amdgpu_crtc;
- 	struct drm_crtc *crtc;
- 	struct drm_dp_mst_topology_mgr *mst_mgr;
- 	struct drm_dp_mst_port *mst_port;
-@@ -181,10 +185,16 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	int clock;
- 	int bpp;
- 	int pbn = 0;
-+	uint8_t i;
-+	uint8_t vcid;
-+	bool find_stream_for_sink;
- 
- 	aconnector = get_connector_for_sink(dev, sink);
- 	crtc = aconnector->base.state->crtc;
- 
-+	if (!crtc)
-+		return false;
-+
- 	if (!aconnector->mst_port)
- 		return false;
- 
-@@ -201,6 +211,8 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		pbn = drm_dp_calc_pbn_mode(clock, bpp);
- 
- 		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, &slots);
-+		/* mst_port->vcpi.vcpi is vc_id for this stream.*/
-+		vcid = mst_port->vcpi.vcpi;
- 
- 		if (!ret)
- 			return false;
-@@ -209,11 +221,105 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
- 	}
- 
--	alloc_entity->slot_count = slots;
--	alloc_entity->pbn = pbn;
--	alloc_entity->pbn_per_slot = mst_mgr->pbn_div;
--
- 	ret = drm_dp_update_payload_part1(mst_mgr);
-+
-+	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
-+	 * AUX message. The sequence is slot 1-63 allocated sequence for each
-+	 * stream. AMD ASIC stream slot allocation should follow the same
-+	 * sequence. copy DRM MST allocation to dc */
-+
-+	mutex_lock(&mst_mgr->payload_lock);
-+
-+	/* number of active streams */
-+	for (i = 0; i < mst_mgr->max_payloads; i++) {
-+		if (mst_mgr->payloads[i].num_slots == 0)
-+			break;
-+		table->stream_count++;
-+	}
-+
-+	for (i = 0; i < table->stream_count; i++) {
-+		table->stream_allocations[i].slot_count =
-+				mst_mgr->proposed_vcpis[i]->num_slots;
-+		/* mst_mgr->pbn_div is fixed value after link training for
-+		 * current link PHY */
-+		table->stream_allocations[i].pbn_per_slot = mst_mgr->pbn_div;
-+
-+		/* find which payload is for current stream
-+		 * after drm_dp_update_payload_part1, payload and proposed_vcpis
-+		 * are sync to the same allocation sequence. vcpi is not saved
-+		 * into payload by drm_dp_update_payload_part1. In order to
-+		 * find sequence of a payload within allocation sequence, we
-+		 * need check vcpi from proposed_vcpis*/
-+
-+		table->stream_allocations[i].pbn =
-+				mst_mgr->proposed_vcpis[i]->pbn;
-+
-+		if (mst_mgr->proposed_vcpis[i]->vcpi == vcid)
-+			table->cur_stream_payload_idx = i;
-+
-+		find_stream_for_sink = false;
-+
-+		list_for_each_entry(connector,
-+				&dev->mode_config.connector_list, head) {
-+
-+			aconnector = to_amdgpu_connector(connector);
-+
-+			/* not mst connector */
-+			if (!aconnector->mst_port)
-+				continue;
-+			mst_port = aconnector->port;
-+
-+			if (mst_port->vcpi.vcpi ==
-+					mst_mgr->proposed_vcpis[i]->vcpi) {
-+				/* find connector with same vcid as payload */
-+
-+				const struct dc_sink *dc_sink_connector;
-+				struct core_sink *core_sink;
-+				struct dc_target *dc_target;
-+				struct core_target *core_target;
-+				struct stream_encoder *stream_enc;
-+				uint8_t j;
-+
-+				dc_sink_connector = aconnector->dc_sink;
-+				core_sink = DC_SINK_TO_CORE(dc_sink_connector);
-+
-+				/* find stream to drive this sink
-+				 * crtc -> target -> stream -> sink */
-+				crtc = aconnector->base.state->crtc;
-+				amdgpu_crtc = to_amdgpu_crtc(crtc);
-+				dc_target = amdgpu_crtc->target;
-+				core_target = DC_TARGET_TO_CORE(dc_target);
-+
-+				for (j = 0; j < core_target->stream_count;
-+						j++) {
-+					if (core_target->streams[j]->sink ==
-+							core_sink)
-+						break;
-+				}
-+
-+				if (j < core_target->stream_count) {
-+					/* find sink --> stream --> target -->
-+					 * connector*/
-+					stream_enc =
-+					core_target->streams[j]->stream_enc;
-+					table->stream_allocations[i].engine =
-+							stream_enc->id;
-+					/* exit loop connector */
-+					find_stream_for_sink = true;
-+					break;
-+				}
-+			}
-+		}
-+		if (!find_stream_for_sink) {
-+			/* TODO: do not find stream for sink. This should not
-+			 * happen
-+			 */
-+			ASSERT(0);
-+		}
-+	}
-+
-+	mutex_unlock(&mst_mgr->payload_lock);
-+
- 	if (ret)
- 		return false;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index a0a131e..54766ae 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -708,6 +708,7 @@ static bool construct(
- 			dal_adapter_service_release_irq(
- 					init_params->adapter_srv, hpd_gpio);
- 		}
-+
- 		break;
- 	case CONNECTOR_ID_EDP:
- 		link->public.connector_signal = SIGNAL_TYPE_EDP;
-@@ -915,6 +916,51 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 	return status;
- }
- 
-+static enum dc_status enable_link_dp_mst(struct core_stream *stream)
-+{
-+	enum dc_status status;
-+	bool skip_video_pattern;
-+	struct core_link *link = stream->sink->link;
-+	struct link_settings link_settings = {0};
-+	enum dp_panel_mode panel_mode;
-+
-+	/* sink signal type after MST branch is MST. Multiple MST sinks
-+	 * share one link. Link DP PHY is enable or training only once.
-+	 */
-+	if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
-+		return DC_OK;
-+
-+	/* get link settings for video mode timing */
-+	decide_link_settings(stream, &link_settings);
-+	status = dp_enable_link_phy(
-+		stream->sink->link,
-+		stream->signal,
-+		stream->stream_enc->id,
-+		&link_settings);
-+
-+	panel_mode = dp_get_panel_mode(link);
-+	dpcd_configure_panel_mode(link, panel_mode);
-+
-+	skip_video_pattern = true;
-+
-+	if (link_settings.link_rate == LINK_RATE_LOW)
-+			skip_video_pattern = false;
-+
-+	if (perform_link_training(link, &link_settings, skip_video_pattern)) {
-+		link->cur_link_settings = link_settings;
-+
-+		/* TODO MST link shared by stream. counter? */
-+		if (link->stream_count < 4)
-+			link->stream_count++;
-+
-+		status = DC_OK;
-+	}
-+	else
-+		status = DC_ERROR_UNEXPECTED;
-+
-+	return status;
-+}
-+
- static enum dc_status enable_link_hdmi(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
-@@ -977,11 +1023,13 @@ enum dc_status core_link_enable(struct core_stream *stream)
- {
- 	enum dc_status status;
- 	switch (stream->signal) {
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_EDP:
- 		status = enable_link_dp(stream);
- 		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		status = enable_link_dp_mst(stream);
-+		break;
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
-@@ -1019,8 +1067,17 @@ enum dc_status core_link_disable(struct core_stream *stream)
- 	 * it will lead to querying dynamic link capabilities
- 	 * which should be done before enable output */
- 
--	if (dc_is_dp_signal(stream->signal))
--		dp_disable_link_phy(stream->sink->link, stream->signal);
-+	if (dc_is_dp_signal(stream->signal)) {
-+		/* SST DP, eDP */
-+		if (dc_is_dp_sst_signal(stream->signal))
-+			dp_disable_link_phy(
-+					stream->sink->link, stream->signal);
-+		else {
-+			dp_disable_link_phy_mst(
-+					stream->sink->link, stream->signal);
-+		}
-+	}
-+
- 	else if (ENCODER_RESULT_OK != dc->hwss.encoder_disable_output(
- 					stream->sink->link->link_enc, stream->signal))
- 		status = DC_ERROR_UNEXPECTED;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 164cdeb..3d6e2ea 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -73,7 +73,22 @@ enum dc_status dp_enable_link_phy(
- 
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- {
--	if(!link)
-+	if (!link->dp_wa.bits.KEEP_RECEIVER_POWERED)
-+		dp_receiver_power_ctrl(link, false);
-+
-+	link->dc->hwss.encoder_disable_output(link->link_enc, signal);
-+
-+	/* Clear current link setting.*/
-+	dc_service_memset(&link->cur_link_settings, 0,
-+			sizeof(link->cur_link_settings));
-+}
-+
-+void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal)
-+{
-+	/* MST disable link only when no stream use the link */
-+	if (link->stream_count > 0)
-+		link->stream_count--;
-+	if (link->stream_count > 0)
- 		return;
- 
- 	if (!link->dp_wa.bits.KEEP_RECEIVER_POWERED)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index c06eb8c..874c839 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -44,7 +44,7 @@ enum dc_edid_status dc_helpers_parse_edid_caps(
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
- 		const struct dc_sink *sink,
--		struct dp_mst_stream_allocation *alloc_entity,
-+		struct dp_mst_stream_allocation_table *table,
- 		bool enable);
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index dddc6e2..e631593 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -780,25 +780,31 @@ static enum color_space get_output_color_space(
- 
- static enum dc_status allocate_mst_payload(struct core_stream *stream)
- {
--	struct link_encoder *link_encoder = stream->sink->link->link_enc;
-+	struct core_link *link = stream->sink->link;
-+	struct link_encoder *link_encoder = link->link_enc;
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
--	struct dp_mst_stream_allocation_table table;
-+	struct dp_mst_stream_allocation_table table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp;
-+	uint8_t cur_stream_payload_idx;
- 
--	/* TODO: remove hardcode */
--	table.stream_count = 1;
--	table.stream_allocations[0].engine = stream_encoder->id;
-+	if (stream_encoder->id == ENGINE_ID_UNKNOWN) {
-+		/* TODO ASSERT */
-+		return DC_ERROR_UNEXPECTED;
-+	}
- 
-+	/* get calculate VC payload for stream: stream_alloc */
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->sink->public,
--		&table.stream_allocations[0],
-+		&table,
- 		true);
- 
-+	/* program DP source TX for payload */
- 	dce110_link_encoder_update_mst_stream_allocation_table(
- 		link_encoder,
- 		&table);
- 
-+	/* send down message */
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
- 			&stream->sink->public);
-@@ -808,9 +814,11 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 			&stream->sink->public,
- 			true);
- 
-+	/* slot X.Y for only current stream */
-+	cur_stream_payload_idx = table.cur_stream_payload_idx;
- 	avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
--			table.stream_allocations[0].pbn,
--			table.stream_allocations[0].pbn_per_slot);
-+		table.stream_allocations[cur_stream_payload_idx].pbn,
-+		table.stream_allocations[cur_stream_payload_idx].pbn_per_slot);
- 
- 	dce110_stream_encoder_set_mst_bandwidth(
- 		stream_encoder,
-@@ -823,24 +831,28 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 
- static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- {
--	struct link_encoder *link_encoder = stream->sink->link->link_enc;
-+	struct core_link *link = stream->sink->link;
-+	struct link_encoder *link_encoder = link->link_enc;
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
--	struct dp_mst_stream_allocation_table table;
-+	struct dp_mst_stream_allocation_table table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
- 
--	/* TODO: remove hardcode */
--	table.stream_count = 1;
--	table.stream_allocations[0].slot_count = 0;
-+	if (stream_encoder->id == ENGINE_ID_UNKNOWN) {
-+		/* TODO ASSERT */
-+		return DC_ERROR_UNEXPECTED;
-+	}
- 
-+	/* slot X.Y */
- 	dce110_stream_encoder_set_mst_bandwidth(
- 		stream_encoder,
- 		stream_encoder->id,
- 		avg_time_slots_per_mtp);
- 
-+	/* TODO: which component is responsible for remove payload table? */
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->sink->public,
--		&table.stream_allocations[0],
-+		&table,
- 		false);
- 
- 	dce110_link_encoder_update_mst_stream_allocation_table(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 0ad582b..c2c201f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1591,8 +1591,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	const struct dp_mst_stream_allocation_table *table)
- {
- 	int32_t addr_offset = enc->be_engine_offset;
--	uint32_t value0;
--	uint32_t value1;
-+	uint32_t value0 = 0;
-+	uint32_t value1 = 0;
- 	uint32_t retries = 0;
- 
- 	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
-@@ -1602,9 +1602,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * Issue allocation change trigger
- 	 * to commit payload on both tx and rx side */
- 
--	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset);
--	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
--
- 	if (table->stream_count >= 1) {
- 		set_reg_field_value(
- 			value0,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 22ab6cb..0b06314 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -225,6 +225,9 @@ struct core_link {
- 
- 	enum edp_revision edp_revision;
- 	union dp_wa dp_wa;
-+
-+	/* MST record stream using this link */
-+	uint8_t stream_count;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index 7110357..a008544 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -50,6 +50,8 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on);
- 
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal);
- 
-+void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal);
-+
- bool dp_set_hw_training_pattern(
- 	struct core_link *link,
- 	enum hw_dp_training_pattern pattern);
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 0df5687..bd3dd6d 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -37,6 +37,10 @@
- struct ddc;
- struct irq_manager;
- 
-+enum {
-+	MAX_CONTROLLER_NUM = 6
-+};
-+
- enum link_service_type {
- 	LINK_SERVICE_TYPE_LEGACY = 0,
- 	LINK_SERVICE_TYPE_DP_SST,
-@@ -399,9 +403,10 @@ struct dp_mst_stream_allocation {
- /* DP MST stream allocation table */
- struct dp_mst_stream_allocation_table {
- 	/* number of DP video streams */
--	uint32_t stream_count;
-+	uint8_t stream_count;
-+	uint8_t cur_stream_payload_idx;
- 	/* array of stream allocations */
--	struct dp_mst_stream_allocation stream_allocations[1];
-+	struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
- };
- 
- struct dp_test_event_data {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch b/common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch
deleted file mode 100644
index 21ef66e6..00000000
--- a/common/recipes-kernel/linux/files/0527-drm-amd-dal-merged-wm-programming-merged-pixel-durat.patch
+++ /dev/null
@@ -1,287 +0,0 @@
-From 8be7639656718aa9aac85d92bcf5f63ca215e641 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 26 Nov 2015 12:09:08 -0500
-Subject: [PATCH 0527/1110] drm/amd/dal: merged wm programming, merged pixel
- duration with dmif allocation
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 14 +---
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 82 +++++++++++-----------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   | 51 ++++++++++----
- 3 files changed, 83 insertions(+), 64 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index e631593..cb2e3d0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1271,18 +1271,12 @@ static void set_displaymarks(
- 		for (j = 0; j < target->stream_count; j++) {
- 			struct core_stream *stream = target->streams[j];
- 
--			dce110_mem_input_program_nbp_watermark(
-+			dce110_mem_input_program_display_marks(
- 				stream->mi,
- 				context->bw_results
--				.nbp_state_change_watermark[total_streams]);
--
--			dce110_mem_input_program_stutter_watermark(
--				stream->mi,
-+				.nbp_state_change_watermark[total_streams],
- 				context->bw_results
--					.stutter_exit_watermark[total_streams]);
--
--			dce110_mem_input_program_urgency_watermark(
--				stream->mi,
-+					.stutter_exit_watermark[total_streams],
- 				context->bw_results
- 					.urgent_watermark[total_streams],
- 				stream->public.timing.h_total,
-@@ -1600,8 +1594,6 @@ static bool set_plane_config(
- 			PIPE_LOCK_CONTROL_SURFACE,
- 			true);
- 
--	dce110_mem_input_program_pix_dur(mi, dc_crtc_timing->pix_clk_khz);
--
- 	dce110_timing_generator_program_blanking(tg, dc_crtc_timing);
- 
- 	enable_fe_clock(ctx, controller_idx, true);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index e84a1ae..e1d7e27 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -467,8 +467,8 @@ bool dce110_mem_input_program_surface_config(
- 
- 	enable(mem_input110);
- 	program_tiling(mem_input110, &surface->tiling_info, surface->format);
--	program_size_and_rotation(mem_input110,
--		surface->rotation, &surface->plane_size);
-+	program_size_and_rotation(
-+		mem_input110, surface->rotation, &surface->plane_size);
- 	program_pixel_format(mem_input110, surface->format);
- 
- 	return true;
-@@ -533,12 +533,11 @@ static void program_urgency_watermark(
- 	dal_write_reg(ctx, urgency_addr, urgency_cntl);
- }
- 
--void dce110_mem_input_program_stutter_watermark(
--	struct mem_input *mi,
-+void program_stutter_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t offset,
- 	struct bw_watermarks marks)
- {
--	const struct dc_context *ctx = mi->ctx;
--	const uint32_t offset = TO_DCE110_MEM_INPUT(mi)->offsets.dmif;
- 	/* register value */
- 	uint32_t stutter_cntl = 0;
- 	uint32_t wm_mask_cntl = 0;
-@@ -599,12 +598,11 @@ void dce110_mem_input_program_stutter_watermark(
- 	dal_write_reg(ctx, stutter_addr, stutter_cntl);
- }
- 
--void dce110_mem_input_program_nbp_watermark(
--	struct mem_input *mi,
-+void program_nbp_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t offset,
- 	struct bw_watermarks marks)
- {
--	const struct dc_context *ctx = mi->ctx;
--	const uint32_t offset = TO_DCE110_MEM_INPUT(mi)->offsets.dmif;
- 	uint32_t value;
- 	uint32_t addr;
- 	/* Write mask to enable reading/writing of watermark set A */
-@@ -692,27 +690,37 @@ void dce110_mem_input_program_safe_display_marks(struct mem_input *mi)
- 
- 	program_urgency_watermark(
- 		mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK);
--	dce110_mem_input_program_stutter_watermark(mi, max_marks);
--	dce110_mem_input_program_nbp_watermark(mi, nbp_marks);
-+	program_stutter_watermark(mi->ctx, bm_dce110->offsets.dmif, max_marks);
-+	program_nbp_watermark(mi->ctx, bm_dce110->offsets.dmif, nbp_marks);
- 
- }
- 
--void dce110_mem_input_program_urgency_watermark(
--	struct mem_input *mi,
--	struct bw_watermarks marks,
-+void dce110_mem_input_program_display_marks(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks nbp,
-+	struct bw_watermarks stutter,
-+	struct bw_watermarks urgent,
- 	uint32_t h_total,
- 	uint32_t pixel_clk_in_khz,
- 	uint32_t pstate_blackout_duration_ns)
- {
--	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
-+	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input);
- 	uint32_t total_dest_line_time_ns = 1000000UL * h_total
- 		/ pixel_clk_in_khz + pstate_blackout_duration_ns;
- 
- 	program_urgency_watermark(
--		mi->ctx,
-+		mem_input->ctx,
- 		bm_dce110->offsets.dmif,
--		marks,
-+		urgent,
- 		total_dest_line_time_ns);
-+	program_nbp_watermark(
-+		mem_input->ctx,
-+		bm_dce110->offsets.dmif,
-+		nbp);
-+	program_stutter_watermark(
-+		mem_input->ctx,
-+		bm_dce110->offsets.dmif,
-+		stutter);
- }
- 
- static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
-@@ -770,6 +778,7 @@ void dce110_mem_input_allocate_dmif_buffer(
- 	uint32_t addr = bm110->offsets.pipe + mmPIPE0_DMIF_BUFFER_CONTROL;
- 	uint32_t value;
- 	uint32_t field;
-+	uint32_t pix_dur;
- 
- 	if (bm110->supported_stutter_mode
- 			& STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)
-@@ -812,6 +821,21 @@ void dce110_mem_input_allocate_dmif_buffer(
- 				"%s: DMIF allocation failed",
- 				__func__);
- 
-+
-+	if (timing->pix_clk_khz != 0) {
-+		addr = mmDPG_PIPE_ARBITRATION_CONTROL1 + bm110->offsets.dmif;
-+		value = dal_read_reg(mi->ctx, addr);
-+		pix_dur = 1000000000ULL / timing->pix_clk_khz;
-+
-+		set_reg_field_value(
-+			value,
-+			pix_dur,
-+			DPG_PIPE_ARBITRATION_CONTROL1,
-+			PIXEL_DURATION);
-+
-+		dal_write_reg(mi->ctx, addr, value);
-+	}
-+
- 	/*
- 	 * Stella Wong proposed the following change
- 	 *
-@@ -897,28 +921,6 @@ void dce110_mem_input_deallocate_dmif_buffer(
- 	dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
- }
- 
--void dce110_mem_input_program_pix_dur(
--	struct mem_input *mi, uint32_t pix_clk_khz)
--{
--	uint64_t pix_dur;
--	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
--					+ TO_DCE110_MEM_INPUT(mi)->offsets.dmif;
--	uint32_t value = dal_read_reg(mi->ctx, addr);
--
--	if (pix_clk_khz == 0)
--		return;
--
--	pix_dur = 1000000000 / pix_clk_khz;
--
--	set_reg_field_value(
--		value,
--		pix_dur,
--		DPG_PIPE_ARBITRATION_CONTROL1,
--		PIXEL_DURATION);
--
--	dal_write_reg(mi->ctx, addr, value);
--}
--
- /*****************************************/
- /* Constructor, Destructor               */
- /*****************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 0d23c81..88697be 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -48,39 +48,64 @@ struct mem_input *dce110_mem_input_create(
- 
- void dce110_mem_input_destroy(struct mem_input **mem_input);
- 
-+/*
-+ * dce110_mem_input_program_display_marks
-+ *
-+ * This function will program nbp stutter and urgency watermarks to maximum
-+ * safe values
-+ */
- void dce110_mem_input_program_safe_display_marks(struct mem_input *mi);
- 
--void dce110_mem_input_program_nbp_watermark(
--	struct mem_input *mem_input,
--	struct bw_watermarks marks);
--
--void dce110_mem_input_program_stutter_watermark(
--	struct mem_input *mem_input,
--	struct bw_watermarks marks);
--
--void dce110_mem_input_program_urgency_watermark(
-+/*
-+ * dce110_mem_input_program_display_marks
-+ *
-+ * This function will program nbp stutter and urgency watermarks to minimum
-+ * allowable values
-+ */
-+void dce110_mem_input_program_display_marks(
- 	struct mem_input *mem_input,
--	struct bw_watermarks marks,
-+	struct bw_watermarks nbp,
-+	struct bw_watermarks stutter,
-+	struct bw_watermarks urgent,
- 	uint32_t h_total,
- 	uint32_t pixel_clk_in_khz,
- 	uint32_t pstate_blackout_duration_ns);
- 
-+/*
-+ * dce110_mem_input_allocate_dmif_buffer
-+ *
-+ * This function will allocate a dmif buffer and program required
-+ * pixel duration for pipe
-+ */
- void dce110_mem_input_allocate_dmif_buffer(
- 		struct mem_input *mem_input,
- 		struct dc_crtc_timing *timing,
- 		uint32_t paths_num);
- 
-+/*
-+ * dce110_mem_input_deallocate_dmif_buffer
-+ *
-+ * This function will deallocate a dmif buffer from pipe
-+ */
- void dce110_mem_input_deallocate_dmif_buffer(
- 	struct mem_input *mem_input, uint32_t paths_num);
- 
--void dce110_mem_input_program_pix_dur(
--	struct mem_input *mem_input, uint32_t pix_clk_khz);
--
-+/*
-+ * dce110_mem_input_program_surface_flip_and_addr
-+ *
-+ * This function programs hsync/vsync mode and surface address
-+ */
- bool dce110_mem_input_program_surface_flip_and_addr(
- 	struct mem_input *mem_input,
- 	const struct dc_plane_address *address,
- 	bool flip_immediate);
- 
-+/*
-+ * dce110_mem_input_program_surface_config
-+ *
-+ * This function will program surface tiling, size, rotation and pixel format
-+ * to corresponding dcp registers.
-+ */
- bool  dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
- 	const struct dc_surface *surface);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0528-drm-amd-dal-MST-two-monitors-light-up-clean-up-2.patch b/common/recipes-kernel/linux/files/0528-drm-amd-dal-MST-two-monitors-light-up-clean-up-2.patch
deleted file mode 100644
index ba89c892..00000000
--- a/common/recipes-kernel/linux/files/0528-drm-amd-dal-MST-two-monitors-light-up-clean-up-2.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From 28897678b3f95373dd892650dfacbf8d79d247d9 Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Thu, 26 Nov 2015 16:00:08 -0500
-Subject: [PATCH 0528/1110] drm/amd/dal: MST two monitors light up clean up 2
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 38 +++-------------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |  6 ++--
- 2 files changed, 9 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 54766ae..5a59f38 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -918,11 +918,11 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 
- static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- {
--	enum dc_status status;
--	bool skip_video_pattern;
- 	struct core_link *link = stream->sink->link;
--	struct link_settings link_settings = {0};
--	enum dp_panel_mode panel_mode;
-+
-+	/* TODO MST link shared by stream. counter? */
-+	if (link->stream_count < 4)
-+		link->stream_count++;
- 
- 	/* sink signal type after MST branch is MST. Multiple MST sinks
- 	 * share one link. Link DP PHY is enable or training only once.
-@@ -930,35 +930,7 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- 	if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
- 		return DC_OK;
- 
--	/* get link settings for video mode timing */
--	decide_link_settings(stream, &link_settings);
--	status = dp_enable_link_phy(
--		stream->sink->link,
--		stream->signal,
--		stream->stream_enc->id,
--		&link_settings);
--
--	panel_mode = dp_get_panel_mode(link);
--	dpcd_configure_panel_mode(link, panel_mode);
--
--	skip_video_pattern = true;
--
--	if (link_settings.link_rate == LINK_RATE_LOW)
--			skip_video_pattern = false;
--
--	if (perform_link_training(link, &link_settings, skip_video_pattern)) {
--		link->cur_link_settings = link_settings;
--
--		/* TODO MST link shared by stream. counter? */
--		if (link->stream_count < 4)
--			link->stream_count++;
--
--		status = DC_OK;
--	}
--	else
--		status = DC_ERROR_UNEXPECTED;
--
--	return status;
-+	return enable_link_dp(stream);
- }
- 
- static enum dc_status enable_link_hdmi(struct core_stream *stream)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index c2c201f..bd3962e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1591,8 +1591,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	const struct dp_mst_stream_allocation_table *table)
- {
- 	int32_t addr_offset = enc->be_engine_offset;
--	uint32_t value0 = 0;
--	uint32_t value1 = 0;
-+	uint32_t value0;
-+	uint32_t value1;
- 	uint32_t retries = 0;
- 
- 	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
-@@ -1601,6 +1601,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * Setup VC Payload Table on Tx Side,
- 	 * Issue allocation change trigger
- 	 * to commit payload on both tx and rx side */
-+	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset);
-+	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
- 
- 	if (table->stream_count >= 1) {
- 		set_reg_field_value(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0529-drm-amd-dal-reduce-input-for-mem_input_program_surfa.patch b/common/recipes-kernel/linux/files/0529-drm-amd-dal-reduce-input-for-mem_input_program_surfa.patch
deleted file mode 100644
index d06a6164..00000000
--- a/common/recipes-kernel/linux/files/0529-drm-amd-dal-reduce-input-for-mem_input_program_surfa.patch
+++ /dev/null
@@ -1,95 +0,0 @@
-From 16e662ce24e63c45a5070c1391e52d7db0a749b6 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 26 Nov 2015 17:06:19 -0500
-Subject: [PATCH 0529/1110] drm/amd/dal: reduce input for
- mem_input_program_surface_config
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c |  5 ++++-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c    | 12 +++++++-----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h    |  5 ++++-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c     |  2 +-
- 4 files changed, 16 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index cb2e3d0..cf893c3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1624,7 +1624,10 @@ static bool set_plane_config(
- 
- 	dce110_mem_input_program_surface_config(
- 			mi,
--			&surface->public);
-+			surface->public.format,
-+			&surface->public.tiling_info,
-+			&surface->public.plane_size,
-+			surface->public.rotation);
- 
- 	pipe_control_lock(
- 			ctx,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index e1d7e27..889c02d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -461,15 +461,17 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- 
- bool dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
--	const struct dc_surface *surface)
-+	enum surface_pixel_format format,
-+	union plane_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation)
- {
- 	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- 
- 	enable(mem_input110);
--	program_tiling(mem_input110, &surface->tiling_info, surface->format);
--	program_size_and_rotation(
--		mem_input110, surface->rotation, &surface->plane_size);
--	program_pixel_format(mem_input110, surface->format);
-+	program_tiling(mem_input110, tiling_info, format);
-+	program_size_and_rotation(mem_input110, rotation, plane_size);
-+	program_pixel_format(mem_input110, format);
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 88697be..7392750 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -108,7 +108,10 @@ bool dce110_mem_input_program_surface_flip_and_addr(
-  */
- bool  dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
--	const struct dc_surface *surface);
-+	enum surface_pixel_format format,
-+	union plane_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation);
- 
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index ebae5e3..126ebd2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -625,11 +625,11 @@ bool dce110_construct_resource_pool(
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		struct stream_enc_init_data enc_init_data = { 0 };
--		/* TODO: rework fragile code*/
- 		enc_init_data.stream_engine_id = i;
- 		enc_init_data.ctx = dc->ctx;
- 		enc_init_data.bp = dal_adapter_service_get_bios_parser(
- 			adapter_serv);
-+		/* TODO: rework fragile code*/
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
- 					&enc_init_data);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0530-drm-amd-dal-Clean-up-Stream-Encoder.patch b/common/recipes-kernel/linux/files/0530-drm-amd-dal-Clean-up-Stream-Encoder.patch
deleted file mode 100644
index 0a114f85..00000000
--- a/common/recipes-kernel/linux/files/0530-drm-amd-dal-Clean-up-Stream-Encoder.patch
+++ /dev/null
@@ -1,743 +0,0 @@
-From 3b98862c1d08b4230b91f9eb7e8c4aa1292b0cfe Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Thu, 26 Nov 2015 15:36:48 -0500
-Subject: [PATCH 0530/1110] drm/amd/dal: Clean up Stream Encoder
-
-Remove AFMT Memory Power State Programming.
-Refactor Setup.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   7 -
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  27 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 353 +++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |  33 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   5 -
- 5 files changed, 165 insertions(+), 260 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 5a59f38..ec85e87 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1014,8 +1014,6 @@ enum dc_status core_link_enable(struct core_stream *stream)
- 	}
- 
- 	if (stream->audio) {
--		stream->ctx->dc->hwss.set_afmt_memory_power_state(
--				stream->ctx, stream->stream_enc->id, true);
- 		/* notify audio driver for audio modes of monitor */
- 		dal_audio_enable_azalia_audio_jack_presence(stream->audio,
- 				stream->stream_enc->id);
-@@ -1054,11 +1052,6 @@ enum dc_status core_link_disable(struct core_stream *stream)
- 					stream->sink->link->link_enc, stream->signal))
- 		status = DC_ERROR_UNEXPECTED;
- 
--	if (stream->audio) {
--		dc->hwss.set_afmt_memory_power_state(
--				stream->ctx, stream->stream_enc->id, false);
--	}
--
- 	return status;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index cf893c3..cbe27a4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -696,13 +696,11 @@ static void disable_stream(struct core_stream *stream)
- 
- 	if (dc_is_hdmi_signal(stream->signal))
- 		dce110_stream_encoder_stop_hdmi_info_packets(
--			stream->stream_enc->ctx,
--			stream->stream_enc->id);
-+			stream->stream_enc);
- 
- 	if (dc_is_dp_signal(stream->signal))
- 		dce110_stream_encoder_stop_dp_info_packets(
--			stream->stream_enc->ctx,
--			stream->stream_enc->id);
-+			stream->stream_enc);
- 
- 	if (stream->audio) {
- 		/* mute audio */
-@@ -822,7 +820,6 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 
- 	dce110_stream_encoder_set_mst_bandwidth(
- 		stream_encoder,
--		stream_encoder->id,
- 		avg_time_slots_per_mtp);
- 
- 	return DC_OK;
-@@ -845,7 +842,6 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	/* slot X.Y */
- 	dce110_stream_encoder_set_mst_bandwidth(
- 		stream_encoder,
--		stream_encoder->id,
- 		avg_time_slots_per_mtp);
- 
- 	/* TODO: which component is responsible for remove payload table? */
-@@ -941,16 +937,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		stream->sink->link->link_enc,
- 		stream->signal);
- 
--	if (!dc_is_dp_signal(stream->signal))
--		if (ENCODER_RESULT_OK != dce110_stream_encoder_setup(
--				stream->stream_enc,
--				&stream->public.timing,
--				stream->signal,
--				stream->audio != NULL)) {
--			BREAK_TO_DEBUGGER();
--			return DC_ERROR_UNEXPECTED;
--		}
--
- 	if (dc_is_dp_signal(stream->signal))
- 		dce110_stream_encoder_dp_set_stream_attribute(
- 			stream->stream_enc,
-@@ -959,12 +945,15 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	if (dc_is_hdmi_signal(stream->signal))
- 		dce110_stream_encoder_hdmi_set_stream_attribute(
- 		stream->stream_enc,
--		&stream->public.timing);
-+		&stream->public.timing,
-+		stream->audio != NULL);
- 
- 	if (dc_is_dvi_signal(stream->signal))
- 		dce110_stream_encoder_dvi_set_stream_attribute(
- 		stream->stream_enc,
--		&stream->public.timing);
-+		&stream->public.timing,
-+		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+		true : false);
- 
- 	if (stream->audio != NULL) {
- 		if (AUDIO_RESULT_OK != dal_audio_setup(
-@@ -1842,8 +1831,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.destruct_resource_pool = dce110_destruct_resource_pool,
- 	.validate_with_context = dce110_validate_with_context,
- 	.validate_bandwidth = dce110_validate_bandwidth,
--	.set_afmt_memory_power_state =
--	  dce110_stream_encoder_set_afmt_memory_power_state,
- 	.enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating,
- 	.enable_display_power_gating = dce110_enable_display_power_gating,
- 	.program_bw = dce110_program_bw
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index ac1a948..95dbc35 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -60,9 +60,9 @@ static void construct(
- 
- static void update_avi_info_packet(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	const struct encoder_info_packet *info_packet)
- {
-+	enum engine_id engine = enc->id;
- 	const int32_t offset = fe_engine_offsets[engine];
- 	uint32_t regval;
- 	uint32_t addr;
-@@ -165,10 +165,10 @@ static void update_avi_info_packet(
- 
- static void update_generic_info_packet(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
- {
-+	enum engine_id engine = enc->id;
- 	uint32_t addr;
- 	uint32_t regval;
- 	/* choose which generic packet to use */
-@@ -267,10 +267,10 @@ static void update_generic_info_packet(
- 
- static void update_hdmi_info_packet(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
- {
-+	enum engine_id engine = enc->id;
- 	uint32_t cont, send, line;
- 	uint32_t addr = fe_engine_offsets[engine];
- 	uint32_t regval;
-@@ -278,7 +278,6 @@ static void update_hdmi_info_packet(
- 	if (info_packet->valid) {
- 		update_generic_info_packet(
- 			enc,
--			engine,
- 			packet_index,
- 			info_packet);
- 
-@@ -372,10 +371,10 @@ static void update_hdmi_info_packet(
- 
- static void update_dp_info_packet(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
- {
-+	enum engine_id engine = enc->id;
- 	const uint32_t addr = mmDP_SEC_CNTL + fe_engine_offsets[engine];
- 
- 	uint32_t value;
-@@ -383,7 +382,6 @@ static void update_dp_info_packet(
- 	if (info_packet->valid)
- 		update_generic_info_packet(
- 			enc,
--			engine,
- 			packet_index,
- 			info_packet);
- 
-@@ -445,10 +443,11 @@ static void update_dp_info_packet(
- }
- 
- static void dp_steer_fifo_reset(
--	struct dc_context *ctx,
--	enum engine_id engine,
-+	struct stream_encoder *enc,
- 	bool reset)
- {
-+	struct dc_context *ctx = enc->ctx;
-+	enum engine_id engine = enc->id;
- 	const uint32_t addr = mmDP_STEER_FIFO + fe_engine_offsets[engine];
- 
- 	uint32_t value = dal_read_reg(ctx, addr);
-@@ -459,9 +458,9 @@ static void dp_steer_fifo_reset(
- }
- 
- static void unblank_dp_output(
--	struct stream_encoder *enc,
--	enum engine_id engine)
-+	struct stream_encoder *enc)
- {
-+	enum engine_id engine = enc->id;
- 	uint32_t addr;
- 	uint32_t value;
- 
-@@ -472,7 +471,7 @@ static void unblank_dp_output(
- 	dal_write_reg(enc->ctx, addr, value);
- 
- 	/* switch DP encoder to CRTC data */
--	dp_steer_fifo_reset(enc->ctx, engine, false);
-+	dp_steer_fifo_reset(enc, false);
- 
- 	/* wait 100us for DIG/DP logic to prime
- 	 * (i.e. a few video lines) */
-@@ -497,10 +496,10 @@ static void unblank_dp_output(
- 
- static void setup_vid_stream(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	uint32_t m_vid,
- 	uint32_t n_vid)
- {
-+	enum engine_id engine = enc->id;
- 	uint32_t addr;
- 	uint32_t value;
- 
-@@ -530,11 +529,11 @@ static void setup_vid_stream(
- 
- static void set_tmds_stream_attributes(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	const struct dc_crtc_timing *timing,
- 	bool is_dvi
- 	)
- {
-+	enum engine_id engine = enc->id;
- 	uint32_t addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
- 	uint32_t value = dal_read_reg(enc->ctx, addr);
- 
-@@ -572,9 +571,9 @@ static void set_tmds_stream_attributes(
- 
- static void set_dp_stream_attributes(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	const struct dc_crtc_timing *timing)
- {
-+	enum engine_id engine = enc->id;
- 	const uint32_t addr = mmDP_PIXEL_FORMAT + fe_engine_offsets[engine];
- 	uint32_t value = dal_read_reg(enc->ctx, addr);
- 
-@@ -660,9 +659,9 @@ static void set_dp_stream_attributes(
- 
- static void setup_hdmi(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	const struct dc_crtc_timing *timing)
- {
-+	enum engine_id engine = enc->id;
- 	uint32_t output_pixel_clock = timing->pix_clk_khz;
- 	uint32_t value;
- 	uint32_t addr;
-@@ -830,40 +829,147 @@ void dce110_stream_encoder_destroy(struct stream_encoder **enc)
- 	*enc = NULL;
- }
- 
--/*
-- * @brief
-- * Associate digital encoder with specified output transmitter
-- * and configure to output signal.
-- * Encoder will be activated later in enable_output()
-- */
--enum encoder_result dce110_stream_encoder_setup(
-+/* setup stream encoder in dp mode */
-+void dce110_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing)
-+{
-+	set_dp_stream_attributes(enc, crtc_timing);
-+}
-+
-+/* setup stream encoder in hdmi mode */
-+void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	struct stream_encoder *enc,
- 	struct dc_crtc_timing *crtc_timing,
--	enum signal_type signal,
- 	bool enable_audio)
- {
--	struct bp_encoder_control cntl;
-+	struct bp_encoder_control cntl = {0};
- 
- 	cntl.action = ENCODER_CONTROL_SETUP;
- 	cntl.engine_id = enc->id;
--	cntl.signal = signal;
-+	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- 	cntl.enable_dp_audio = enable_audio;
- 	cntl.pixel_clock = crtc_timing->pix_clk_khz;
--	cntl.lanes_number = (signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.color_depth = crtc_timing->display_color_depth;
-+
-+	if (dal_bios_parser_encoder_control(
-+			enc->bp, &cntl) != BP_RESULT_OK)
-+		return;
-+
-+
-+	set_tmds_stream_attributes(enc, crtc_timing, false);
-+
-+	/* setup HDMI engine */
-+	setup_hdmi(enc, crtc_timing);
-+}
-+
-+/* setup stream encoder in dvi mode */
-+void dce110_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link)
-+{
-+	struct bp_encoder_control cntl = {0};
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc->id;
-+	cntl.signal = is_dual_link ?
-+		SIGNAL_TYPE_DVI_DUAL_LINK :
-+		SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	cntl.enable_dp_audio = false;
-+	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+	cntl.lanes_number = (is_dual_link) ?
- 				LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
- 	if (dal_bios_parser_encoder_control(
- 			enc->bp, &cntl) != BP_RESULT_OK)
--		return ENCODER_RESULT_ERROR;
-+		return;
- 
--	return ENCODER_RESULT_OK;
-+	set_tmds_stream_attributes(enc, crtc_timing, true);
-+}
-+
-+void dce110_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	struct fixed31_32 avg_time_slots_per_mtp)
-+{
-+	uint32_t x = dal_fixed31_32_floor(
-+		avg_time_slots_per_mtp);
-+
-+	uint32_t y = dal_fixed31_32_ceil(
-+		dal_fixed31_32_shl(
-+			dal_fixed31_32_sub_int(
-+				avg_time_slots_per_mtp,
-+				x),
-+			26));
-+	enum engine_id engine = enc->id;
-+
-+	{
-+		const uint32_t addr = mmDP_MSE_RATE_CNTL +
-+				fe_engine_offsets[engine];
-+		uint32_t value = dal_read_reg(enc->ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			x,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_X);
-+
-+		set_reg_field_value(
-+			value,
-+			y,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_Y);
-+
-+		dal_write_reg(enc->ctx, addr, value);
-+	}
-+
-+	/* wait for update to be completed on the link */
-+	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
-+	/* is reset to 0 (not pending) */
-+	{
-+		const uint32_t addr = mmDP_MSE_RATE_UPDATE +
-+			fe_engine_offsets[engine];
-+		uint32_t value, field;
-+		uint32_t retries = 0;
-+
-+		do {
-+			value = dal_read_reg(enc->ctx, addr);
-+
-+			field = get_reg_field_value(
-+					value,
-+					DP_MSE_RATE_UPDATE,
-+					DP_MSE_RATE_UPDATE_PENDING);
-+
-+			if (!(field &
-+			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
-+				break;
-+
-+			dc_service_delay_in_microseconds(enc->ctx, 10);
-+
-+			++retries;
-+		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+	}
-+}
-+
-+void dce110_stream_encoder_update_hdmi_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	update_avi_info_packet(
-+		enc,
-+		&info_frame->avi);
-+	update_hdmi_info_packet(enc, 0, &info_frame->vendor);
-+	update_hdmi_info_packet(enc, 1, &info_frame->gamut);
-+	update_hdmi_info_packet(enc, 2, &info_frame->spd);
- }
- 
- void dce110_stream_encoder_stop_hdmi_info_packets(
--	struct dc_context *ctx,
--	enum engine_id engine)
-+	struct stream_encoder *enc)
- {
-+	struct dc_context *ctx = enc->ctx;
-+	enum engine_id engine = enc->id;
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 	uint32_t offset = fe_engine_offsets[engine];
-@@ -962,12 +1068,19 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 
- 	dal_write_reg(ctx, addr, value);
- }
-+void dce110_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	update_dp_info_packet(enc, 0, &info_frame->vsc);
-+}
- 
- void dce110_stream_encoder_stop_dp_info_packets(
--	struct dc_context *ctx,
--	enum engine_id engine)
-+	struct stream_encoder *enc)
- {
- 	/* stop generic packets on DP */
-+	struct dc_context *ctx = enc->ctx;
-+	enum engine_id engine = enc->id;
- 	uint32_t offset = fe_engine_offsets[engine];
- 	const uint32_t addr = mmDP_SEC_CNTL + offset;
- 	uint32_t value = dal_read_reg(ctx, addr);
-@@ -994,175 +1107,6 @@ void dce110_stream_encoder_stop_dp_info_packets(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--/* setup stream encoder in dp mode */
--void dce110_stream_encoder_dp_set_stream_attribute(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing)
--{
--	set_dp_stream_attributes(enc, enc->id, crtc_timing);
--}
--
--/* setup stream encoder in hdmi mode */
--void dce110_stream_encoder_hdmi_set_stream_attribute(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing)
--{
--	set_tmds_stream_attributes(enc, enc->id, crtc_timing, false);
--
--	/* setup HDMI engine */
--	setup_hdmi(
--		enc, enc->id, crtc_timing);
--}
--
--/* setup stream encoder in dvi mode */
--void dce110_stream_encoder_dvi_set_stream_attribute(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing)
--{
--	set_tmds_stream_attributes(enc, enc->id, crtc_timing, true);
--}
--
--void dce110_stream_encoder_set_mst_bandwidth(
--	struct stream_encoder *enc,
--	enum engine_id engine,
--	struct fixed31_32 avg_time_slots_per_mtp)
--{
--	uint32_t x = dal_fixed31_32_floor(
--		avg_time_slots_per_mtp);
--
--	uint32_t y = dal_fixed31_32_ceil(
--		dal_fixed31_32_shl(
--			dal_fixed31_32_sub_int(
--				avg_time_slots_per_mtp,
--				x),
--			26));
--
--	{
--		const uint32_t addr = mmDP_MSE_RATE_CNTL +
--				fe_engine_offsets[engine];
--		uint32_t value = dal_read_reg(enc->ctx, addr);
--
--		set_reg_field_value(
--			value,
--			x,
--			DP_MSE_RATE_CNTL,
--			DP_MSE_RATE_X);
--
--		set_reg_field_value(
--			value,
--			y,
--			DP_MSE_RATE_CNTL,
--			DP_MSE_RATE_Y);
--
--		dal_write_reg(enc->ctx, addr, value);
--	}
--
--	/* wait for update to be completed on the link
--	 * i.e. DP_MSE_RATE_UPDATE_PENDING field (read only)
--	 * is reset to 0 (not pending) */
--	{
--		const uint32_t addr = mmDP_MSE_RATE_UPDATE +
--			fe_engine_offsets[engine];
--		uint32_t value, field;
--		uint32_t retries = 0;
--
--		do {
--			value = dal_read_reg(enc->ctx, addr);
--
--			field = get_reg_field_value(
--					value,
--					DP_MSE_RATE_UPDATE,
--					DP_MSE_RATE_UPDATE_PENDING);
--
--			if (!(field &
--			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
--				break;
--
--			dc_service_delay_in_microseconds(enc->ctx, 10);
--
--			++retries;
--		} while (retries < DP_MST_UPDATE_MAX_RETRY);
--	}
--}
--
--
--/**
--* set_afmt_memory_power_state
--*
--* @brief
--*  Power up audio formatter memory that is mapped to specified DIG
--*/
--void dce110_stream_encoder_set_afmt_memory_power_state(
--	const struct dc_context *ctx,
--	enum engine_id id,
--	bool enable)
--{
--	uint32_t value;
--	uint32_t mem_pwr_force;
--
--	value = dal_read_reg(ctx, mmDCO_MEM_PWR_CTRL);
--
--	if (enable)
--		mem_pwr_force = 0;
--	else
--		mem_pwr_force = 3;
--
--	/* force shutdown mode for appropriate AFMT memory */
--	switch (id) {
--	case ENGINE_ID_DIGA:
--		set_reg_field_value(
--			value,
--			mem_pwr_force,
--			DCO_MEM_PWR_CTRL,
--			HDMI0_MEM_PWR_FORCE);
--		break;
--	case ENGINE_ID_DIGB:
--		set_reg_field_value(
--			value,
--			mem_pwr_force,
--			DCO_MEM_PWR_CTRL,
--			HDMI1_MEM_PWR_FORCE);
--		break;
--	case ENGINE_ID_DIGC:
--		set_reg_field_value(
--			value,
--			mem_pwr_force,
--			DCO_MEM_PWR_CTRL,
--			HDMI2_MEM_PWR_FORCE);
--		break;
--	default:
--		dal_logger_write(
--			ctx->logger,
--			LOG_MAJOR_WARNING,
--			LOG_MINOR_COMPONENT_ENCODER,
--			"%s: Invalid Engine Id\n",
--			__func__);
--		break;
--	}
--
--	dal_write_reg(ctx, mmDCO_MEM_PWR_CTRL, value);
--}
--
--void dce110_stream_encoder_update_hdmi_info_packets(
--	struct stream_encoder *enc,
--	const struct encoder_info_frame *info_frame)
--{
--	update_avi_info_packet(
--		enc,
--		enc->id,
--		&info_frame->avi);
--	update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor);
--	update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut);
--	update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd);
--}
--
--void dce110_stream_encoder_update_dp_info_packets(
--	struct stream_encoder *enc,
--	const struct encoder_info_frame *info_frame)
--{
--	update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc);
--}
--
- void dce110_stream_encoder_dp_blank(
- 	struct stream_encoder *enc)
- {
-@@ -1219,7 +1163,7 @@ void dce110_stream_encoder_dp_blank(
- 	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
- 	 * complete, stream status will be stuck in video stream enabled state,
- 	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
--	dp_steer_fifo_reset(enc->ctx, engine, true);
-+	dp_steer_fifo_reset(enc, true);
- }
- 
- /* output video stream to link encoder */
-@@ -1243,10 +1187,9 @@ void dce110_stream_encoder_dp_unblank(
- 
- 		m_vid = (uint32_t) m_vid_l;
- 
--		setup_vid_stream(enc,
--			enc->id, m_vid, n_vid);
-+		setup_vid_stream(enc, m_vid, n_vid);
- 	}
- 
--	unblank_dp_output(enc, enc->id);
-+	unblank_dp_output(enc);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index d4477d1..a520691 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -38,21 +38,6 @@ struct stream_encoder *dce110_stream_encoder_create(
- void dce110_stream_encoder_destroy(struct stream_encoder **enc);
- 
- /***** HW programming ***********/
--enum encoder_result dce110_stream_encoder_setup(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing,
--	enum signal_type signal,
--	bool enable_audio);
--
--void dce110_stream_encoder_stop_hdmi_info_packets(
--	struct dc_context *ctx,
--	enum engine_id engine);
--
--void dce110_stream_encoder_stop_dp_info_packets(
--	struct dc_context *ctx,
--	enum engine_id engine);
--
--
- /* setup stream encoder in dp mode */
- void dce110_stream_encoder_dp_set_stream_attribute(
- 	struct stream_encoder *enc,
-@@ -61,32 +46,34 @@ void dce110_stream_encoder_dp_set_stream_attribute(
- /* setup stream encoder in hdmi mode */
- void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing);
-+	struct dc_crtc_timing *crtc_timing,
-+	bool enable_audio);
- 
- /* setup stream encoder in dvi mode */
- void dce110_stream_encoder_dvi_set_stream_attribute(
- 	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing);
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link);
- 
- /* set throttling for DP MST */
- void dce110_stream_encoder_set_mst_bandwidth(
- 	struct stream_encoder *enc,
--	enum engine_id engine,
- 	struct fixed31_32 avg_time_slots_per_mtp);
- 
--void dce110_stream_encoder_set_afmt_memory_power_state(
--	const struct dc_context *ctx,
--	enum engine_id id,
--	bool enable);
--
- void dce110_stream_encoder_update_hdmi_info_packets(
- 	struct stream_encoder *enc,
- 	const struct encoder_info_frame *info_frame);
- 
-+void dce110_stream_encoder_stop_hdmi_info_packets(
-+	struct stream_encoder *enc);
-+
- void dce110_stream_encoder_update_dp_info_packets(
- 	struct stream_encoder *enc,
- 	const struct encoder_info_frame *info_frame);
- 
-+void dce110_stream_encoder_stop_dp_info_packets(
-+	struct stream_encoder *enc);
-+
- /* output blank/idle stream to link encoder */
- void dce110_stream_encoder_dp_blank(
- 	struct stream_encoder *enc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 2c5738f..99a0458 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -134,11 +134,6 @@ struct hw_sequencer_funcs {
- 					struct bios_parser *bp,
- 					enum pipe_gating_control power_gating);
- 
--	void (*set_afmt_memory_power_state)(
--					const struct dc_context *ctx,
--					enum engine_id id,
--					bool enable);
--
- 	/* resource management and validation*/
- 	bool (*construct_resource_pool)(
- 					struct adapter_service *adapter_serv,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0531-drm-amd-dal-Move-scaling-param-to-commit-surface-and.patch b/common/recipes-kernel/linux/files/0531-drm-amd-dal-Move-scaling-param-to-commit-surface-and.patch
deleted file mode 100644
index 26447c5d..00000000
--- a/common/recipes-kernel/linux/files/0531-drm-amd-dal-Move-scaling-param-to-commit-surface-and.patch
+++ /dev/null
@@ -1,305 +0,0 @@
-From 3c44e37fd5c3d29c3cab012e360f1b8ea7f44f57 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 25 Nov 2015 16:13:55 -0500
-Subject: [PATCH 0531/1110] drm/amd/dal: Move scaling param to commit surface
- and fix underscan flash
-
-1. Move destination rectangle calculation to commit surface instead of commit targets.
-2. Change set property so that there is no mode change only surface change.
-
-This fixes flashing of the screen when underscan adjustment is set.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 131 ++++++++++++---------
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         |   3 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  21 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |   8 ++
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   3 +
- 5 files changed, 109 insertions(+), 57 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 1b46426..113c2e0 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -568,9 +568,59 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id(
- 	return NULL;
- }
- 
-+static void calculate_stream_scaling_settings(
-+		const struct drm_display_mode *mode,
-+		const struct dc_stream *stream,
-+		struct dm_connector_state *dm_state)
-+{
-+	enum amdgpu_rmx_type rmx_type;
-+
-+	struct rect src = { 0 }; /* viewport in target space*/
-+	struct rect dst = { 0 }; /* stream addressable area */
-+
-+	/* Full screen scaling by default */
-+	src.width = mode->hdisplay;
-+	src.height = mode->vdisplay;
-+	dst.width = stream->timing.h_addressable;
-+	dst.height = stream->timing.v_addressable;
-+
-+	rmx_type = dm_state->scaling;
-+	if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
-+		if (src.width * dst.height <
-+				src.height * dst.width) {
-+			/* height needs less upscaling/more downscaling */
-+			dst.width = src.width *
-+					dst.height / src.height;
-+		} else {
-+			/* width needs less upscaling/more downscaling */
-+			dst.height = src.height *
-+					dst.width / src.width;
-+		}
-+	} else if (rmx_type == RMX_CENTER) {
-+		dst = src;
-+	}
-+
-+	dst.x = (stream->timing.h_addressable - dst.width) / 2;
-+	dst.y = (stream->timing.v_addressable - dst.height) / 2;
-+
-+	if (dm_state->underscan_enable) {
-+		dst.x += dm_state->underscan_hborder / 2;
-+		dst.y += dm_state->underscan_vborder / 2;
-+		dst.width -= dm_state->underscan_hborder;
-+		dst.height -= dm_state->underscan_vborder;
-+	}
-+
-+	dc_update_stream(stream, &src, &dst);
-+
-+	DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
-+			dst.x, dst.y, dst.width, dst.height);
-+
-+}
-+
- static void dm_dc_surface_commit(
- 		struct dc *dc,
--		struct drm_crtc *crtc)
-+		struct drm_crtc *crtc,
-+		struct dm_connector_state *dm_state)
- {
- 	struct dc_surface *dc_surface;
- 	const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-@@ -593,8 +643,11 @@ static void dm_dc_surface_commit(
- 		goto fail;
- 	}
- 
--	/* Surface programming */
-+	calculate_stream_scaling_settings(&crtc->state->mode,
-+			dc_target->streams[0],
-+			dm_state);
- 
-+	/* Surface programming */
- 	fill_plane_attributes(dc_surface, crtc);
- 	if (crtc->mode.private_flags &
- 		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
-@@ -753,47 +806,6 @@ static void fill_audio_info(
- /*TODO: move these defines elsewhere*/
- #define DAL_MAX_CONTROLLERS 4
- 
--static void calculate_stream_scaling_settings(
--		const struct drm_display_mode *mode,
--		enum amdgpu_rmx_type rmx_type,
--		struct dc_stream *stream,
--		uint8_t underscan_vborder,
--		uint8_t underscan_hborder,
--		bool underscan_enable)
--{
--	/* Full screen scaling by default */
--	stream->src.width = mode->hdisplay;
--	stream->src.height = mode->vdisplay;
--	stream->dst.width = stream->timing.h_addressable;
--	stream->dst.height = stream->timing.v_addressable;
--
--	if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
--		if (stream->src.width * stream->dst.height <
--				stream->src.height * stream->dst.width) {
--			/* height needs less upscaling/more downscaling */
--			stream->dst.width = stream->src.width *
--					stream->dst.height / stream->src.height;
--		} else {
--			/* width needs less upscaling/more downscaling */
--			stream->dst.height = stream->src.height *
--					stream->dst.width / stream->src.width;
--		}
--	} else if (rmx_type == RMX_CENTER) {
--		stream->dst = stream->src;
--	}
--
--	stream->dst.x = (stream->timing.h_addressable - stream->dst.width) / 2;
--	stream->dst.y = (stream->timing.v_addressable - stream->dst.height) / 2;
--
--	if (underscan_enable) {
--		stream->dst.x += underscan_hborder / 2;
--		stream->dst.y += underscan_vborder / 2;
--		stream->dst.width -= underscan_hborder;
--		stream->dst.height -= underscan_vborder;
--	}
--}
--
--
- static void copy_crtc_timing_for_drm_display_mode(
- 		const struct drm_display_mode *src_mode,
- 		struct drm_display_mode *dst_mode)
-@@ -877,12 +889,6 @@ static struct dc_target *create_target_for_sink(
- 	dc_timing_from_drm_display_mode(&stream->timing,
- 			&mode, &aconnector->base);
- 
--	calculate_stream_scaling_settings(&mode, dm_state->scaling, stream,
--			dm_state->underscan_vborder,
--			dm_state->underscan_hborder,
--			dm_state->underscan_enable);
--
--
- 	fill_audio_info(
- 		&stream->audio_info,
- 		drm_connector,
-@@ -1079,8 +1085,6 @@ int amdgpu_dm_connector_atomic_set_property(
- 			if (crtc == state->crtc) {
- 				struct drm_plane_state *plane_state;
- 
--				new_crtc_state->mode_changed = true;
--
- 				/*
- 				 * Bit of magic done here. We need to ensure
- 				 * that planes get update after mode is set.
-@@ -1122,6 +1126,9 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
- 
- 	if (state) {
- 		state->scaling = RMX_OFF;
-+		state->underscan_enable = false;
-+		state->underscan_hborder = 0;
-+		state->underscan_vborder = 0;
- 
- 		connector->state = &state->base;
- 		connector->state->connector = connector;
-@@ -2180,10 +2187,10 @@ int amdgpu_dm_atomic_commit(
- 		struct drm_plane_state *plane_state = plane->state;
- 		struct drm_crtc *crtc = plane_state->crtc;
- 		struct drm_framebuffer *fb = plane_state->fb;
-+		struct drm_connector *connector;
- 
--		if (fb && crtc) {
--			if (!crtc->state->planes_changed)
--				continue;
-+		if (fb && crtc && crtc->state->planes_changed) {
-+			struct dm_connector_state *dm_state = NULL;
- 
- 			if (page_flip_needed(
- 				plane_state,
-@@ -2193,8 +2200,20 @@ int amdgpu_dm_atomic_commit(
- 					fb,
- 					crtc->state->event,
- 					0);
--			else
--				dm_dc_surface_commit(dm->dc, crtc);
-+			else {
-+				list_for_each_entry(connector,
-+						&dev->mode_config.connector_list, head)	{
-+					if (connector->state->crtc == crtc) {
-+						dm_state = to_dm_connector_state(connector->state);
-+						break;
-+					}
-+				}
-+
-+				dm_dc_surface_commit(
-+					dm->dc,
-+					crtc,
-+					dm_state);
-+			}
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index 50db743..5aadda7 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -237,6 +237,7 @@ struct log_major_mask_info {
- 		(1 << LOG_MINOR_HW_TRACE_HPD_IRQ)
- #define LG_HW_TR_PLANES_MSK (1 << LOG_MINOR_HW_TRACE_MPO)
- #define LG_ALL_MSK 0xffffffff
-+#define LG_DCP_MSK ~(1 << LOG_MINOR_DCP_SCALER)
- 
- #define LG_SYNC_MSK (1 << LOG_MINOR_SYNC_TIMING)
- 
-@@ -254,7 +255,7 @@ static const struct log_major_mask_info log_major_mask_info_tbl[] = {
- 								hw_trace_minor_info_tbl,     NUM_ELEMENTS(hw_trace_minor_info_tbl)},
- 	{{LOG_MAJOR_MST,             "MST"         }, LG_ALL_MSK, mst_minor_info_tbl,          NUM_ELEMENTS(mst_minor_info_tbl)},
- 	{{LOG_MAJOR_DCS,             "DCS"         }, LG_ALL_MSK, dcs_minor_info_tbl,          NUM_ELEMENTS(dcs_minor_info_tbl)},
--	{{LOG_MAJOR_DCP,             "DCP"         }, LG_ALL_MSK, dcp_minor_info_tbl,          NUM_ELEMENTS(dcp_minor_info_tbl)},
-+	{{LOG_MAJOR_DCP,             "DCP"         }, LG_DCP_MSK, dcp_minor_info_tbl,          NUM_ELEMENTS(dcp_minor_info_tbl)},
- 	{{LOG_MAJOR_BIOS,            "Bios"        }, LG_ALL_MSK, bios_minor_info_tbl,         NUM_ELEMENTS(bios_minor_info_tbl)},
- 	{{LOG_MAJOR_REGISTER,        "Register"    }, LG_ALL_MSK, reg_minor_info_tbl,          NUM_ELEMENTS(reg_minor_info_tbl)},
- 	{{LOG_MAJOR_INFO_PACKETS,    "InfoPacket"  }, LG_ALL_MSK, info_packet_minor_info_tbl,  NUM_ELEMENTS(info_packet_minor_info_tbl)},
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 082fb02..e5b1d02 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -330,6 +330,27 @@ void build_scaling_params(
- 		stream->taps.v_taps_c = 1;
- 	else
- 		stream->taps.v_taps_c = surface->scaling_quality.v_taps_c;
-+
-+	dal_logger_write(stream->ctx->logger,
-+				LOG_MAJOR_DCP,
-+				LOG_MINOR_DCP_SCALER,
-+				"%s: Overscan:\n bot:%d left:%d right:%d "
-+				"top:%d\nViewport:\nheight:%d width:%d x:%d "
-+				"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
-+				"y:%d\n",
-+				__func__,
-+				stream->overscan.bottom,
-+				stream->overscan.left,
-+				stream->overscan.right,
-+				stream->overscan.top,
-+				stream->viewport.height,
-+				stream->viewport.width,
-+				stream->viewport.x,
-+				stream->viewport.y,
-+				surface->dst_rect.height,
-+				surface->dst_rect.width,
-+				surface->dst_rect.x,
-+				surface->dst_rect.y);
- }
- 
- void build_scaling_params_for_context(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index 1a7bf50..986368a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -168,5 +168,13 @@ alloc_fail:
- 	return NULL;
- }
- 
-+void dc_update_stream(const struct dc_stream *dc_stream,
-+		struct rect *src,
-+		struct rect *dst)
-+{
-+	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
- 
-+	stream->public.src = *src;
-+	stream->public.dst = *dst;
-+}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 1db9395..0cb9d77 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -258,6 +258,9 @@ struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink);
- void dc_stream_retain(struct dc_stream *dc_stream);
- void dc_stream_release(struct dc_stream *dc_stream);
- 
-+void dc_update_stream(const struct dc_stream *dc_stream,
-+		struct rect *src, struct rect *dst);
-+
- /*******************************************************************************
-  * Link Interfaces
-  ******************************************************************************/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0532-drm-amd-dal-Add-delay-for-MST-after-LT.patch b/common/recipes-kernel/linux/files/0532-drm-amd-dal-Add-delay-for-MST-after-LT.patch
deleted file mode 100644
index 4429a43e..00000000
--- a/common/recipes-kernel/linux/files/0532-drm-amd-dal-Add-delay-for-MST-after-LT.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 5d2f400cef10bbe7e5c6eee77c7368eb3500e164 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 27 Nov 2015 00:03:20 -0500
-Subject: [PATCH 0532/1110] drm/amd/dal: Add delay for MST after LT
-
-This gives the receiver some time to establish the link
-and seems to have a positive impact on ACT handled.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index ec85e87..0e97180 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1001,6 +1001,7 @@ enum dc_status core_link_enable(struct core_stream *stream)
- 		break;
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 		status = enable_link_dp_mst(stream);
-+		dc_service_sleep_in_milliseconds(stream->ctx, 200);
- 		break;
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0533-drm-amd-dal-Don-t-retrain-the-link-when-enabling-2nd.patch b/common/recipes-kernel/linux/files/0533-drm-amd-dal-Don-t-retrain-the-link-when-enabling-2nd.patch
deleted file mode 100644
index 9bc612df..00000000
--- a/common/recipes-kernel/linux/files/0533-drm-amd-dal-Don-t-retrain-the-link-when-enabling-2nd.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From 6d4d095d35d911aaa0387649958a8d1feb3ce2c8 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 27 Nov 2015 00:04:11 -0500
-Subject: [PATCH 0533/1110] drm/amd/dal: Don't retrain the link when enabling
- 2nd stream
-
-For MST we don't want to retrain the link when enabling
-the 2nd stream. This avoids that but also introduces a hole
-in the logic in that we don't disable the link after the
-last stream is cleaned up. This logic needs to be cleaned up
-further.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c      | 14 +++++++++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 18 +++++++++++++-----
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h    |  3 ++-
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h     |  2 +-
- 4 files changed, 27 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 0e97180..3484db5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -919,10 +919,18 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
-+	bool already_enabled = false;
-+	int i;
-+
-+
-+	for (i = 0; i < link->enabled_stream_count; i++) {
-+		if (link->enabled_streams[i] == stream)
-+			already_enabled = true;
-+	}
- 
- 	/* TODO MST link shared by stream. counter? */
--	if (link->stream_count < 4)
--		link->stream_count++;
-+	if (!already_enabled)
-+		link->enabled_streams[link->enabled_stream_count++] = stream;
- 
- 	/* sink signal type after MST branch is MST. Multiple MST sinks
- 	 * share one link. Link DP PHY is enable or training only once.
-@@ -1045,7 +1053,7 @@ enum dc_status core_link_disable(struct core_stream *stream)
- 					stream->sink->link, stream->signal);
- 		else {
- 			dp_disable_link_phy_mst(
--					stream->sink->link, stream->signal);
-+					stream->sink->link, stream);
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 3d6e2ea..551a98f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -83,18 +83,26 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 			sizeof(link->cur_link_settings));
- }
- 
--void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal)
-+void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
- {
-+	int i, j;
-+
-+	for (i = 0; i < link->enabled_stream_count; i++) {
-+		if (link->enabled_streams[i] == stream) {
-+			link->enabled_stream_count--;
-+			for (j = i; i < link->enabled_stream_count; j++)
-+				link->enabled_streams[j] = link->enabled_streams[j+1];
-+		}
-+	}
- 	/* MST disable link only when no stream use the link */
--	if (link->stream_count > 0)
--		link->stream_count--;
--	if (link->stream_count > 0)
-+	if (link->enabled_stream_count > 0) {
- 		return;
-+	}
- 
- 	if (!link->dp_wa.bits.KEEP_RECEIVER_POWERED)
- 		dp_receiver_power_ctrl(link, false);
- 
--	link->dc->hwss.encoder_disable_output(link->link_enc, signal);
-+	link->dc->hwss.encoder_disable_output(link->link_enc, stream->signal);
- 
- 	/* Clear current link setting.*/
- 	dc_service_memset(&link->cur_link_settings, 0,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 0b06314..f18034c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -227,7 +227,8 @@ struct core_link {
- 	union dp_wa dp_wa;
- 
- 	/* MST record stream using this link */
--	uint8_t stream_count;
-+	const struct core_stream *enabled_streams[MAX_SINKS_PER_LINK];
-+	uint8_t enabled_stream_count;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index a008544..c86c942 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -50,7 +50,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on);
- 
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal);
- 
--void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal);
-+void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream);
- 
- bool dp_set_hw_training_pattern(
- 	struct core_link *link,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0534-drm-amd-dal-Use-correct-index-when-iterating-enabled.patch b/common/recipes-kernel/linux/files/0534-drm-amd-dal-Use-correct-index-when-iterating-enabled.patch
deleted file mode 100644
index 0d7c8848..00000000
--- a/common/recipes-kernel/linux/files/0534-drm-amd-dal-Use-correct-index-when-iterating-enabled.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 7081369ebfd85c326cee2f2f2d363fa3318714e2 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 27 Nov 2015 11:51:05 -0500
-Subject: [PATCH 0534/1110] drm/amd/dal: Use correct index when iterating
- enabled streams
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 551a98f..e7673ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -90,7 +90,7 @@ void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
- 	for (i = 0; i < link->enabled_stream_count; i++) {
- 		if (link->enabled_streams[i] == stream) {
- 			link->enabled_stream_count--;
--			for (j = i; i < link->enabled_stream_count; j++)
-+			for (j = i; j < link->enabled_stream_count; j++)
- 				link->enabled_streams[j] = link->enabled_streams[j+1];
- 		}
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0535-drm-amd-dal-Reset-DPCD-sink-count-on-disconnect.patch b/common/recipes-kernel/linux/files/0535-drm-amd-dal-Reset-DPCD-sink-count-on-disconnect.patch
deleted file mode 100644
index 8ac9c230..00000000
--- a/common/recipes-kernel/linux/files/0535-drm-amd-dal-Reset-DPCD-sink-count-on-disconnect.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 9990c805161886a9afccff039e99ffbaf9cd3fc9 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 27 Nov 2015 12:22:36 -0500
-Subject: [PATCH 0535/1110] drm/amd/dal: Reset DPCD sink count on disconnect
-
-This fixes active dongle downstream hotplug
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 3484db5..647d141 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -363,6 +363,8 @@ static void link_unplug(struct core_link *link)
- 
- 	for (i = 0; i < link->public.sink_count; i++)
- 		dc_link_remove_sink(&link->public, link->public.sink[i]);
-+
-+	link->dpcd_sink_count = 0;
- }
- 
- static enum dc_edid_status read_edid(struct core_link *link)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0536-drm-amd-dal-refactor-helpers-to-use-dc-types.patch b/common/recipes-kernel/linux/files/0536-drm-amd-dal-refactor-helpers-to-use-dc-types.patch
deleted file mode 100644
index 7bc77984..00000000
--- a/common/recipes-kernel/linux/files/0536-drm-amd-dal-refactor-helpers-to-use-dc-types.patch
+++ /dev/null
@@ -1,208 +0,0 @@
-From 185d80bfd5cedb4bc951562f008bc80da3788128 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 30 Nov 2015 13:15:47 -0500
-Subject: [PATCH 0536/1110] drm/amd/dal: refactor helpers to use dc types
-
-We should not access core types from DM
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 103 +++++++++++----------
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |   1 +
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   2 +-
- .../gpu/drm/amd/dal/include/link_service_types.h   |   2 +-
- 4 files changed, 56 insertions(+), 52 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 7a07af5..5b780e1 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -31,9 +31,6 @@
- #include <drm/amdgpu_drm.h>
- #include <drm/drm_edid.h>
- 
--#include "dc_types.h"
--#include "core_types.h"
--#include "stream_encoder_types.h"
- #include "amdgpu.h"
- #include "dc.h"
- #include "dc_services.h"
-@@ -234,22 +231,27 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	for (i = 0; i < mst_mgr->max_payloads; i++) {
- 		if (mst_mgr->payloads[i].num_slots == 0)
- 			break;
--		table->stream_count++;
- 	}
- 
-+	table->stream_count = i;
-+
- 	for (i = 0; i < table->stream_count; i++) {
- 		table->stream_allocations[i].slot_count =
- 				mst_mgr->proposed_vcpis[i]->num_slots;
--		/* mst_mgr->pbn_div is fixed value after link training for
--		 * current link PHY */
-+		/*
-+		 * mst_mgr->pbn_div is fixed value after link training for
-+		 * current link PHY
-+		 */
- 		table->stream_allocations[i].pbn_per_slot = mst_mgr->pbn_div;
- 
--		/* find which payload is for current stream
--		 * after drm_dp_update_payload_part1, payload and proposed_vcpis
-+		/*
-+		 * find which payload is for current stream after
-+		 * drm_dp_update_payload_part1, payload and proposed_vcpis
- 		 * are sync to the same allocation sequence. vcpi is not saved
- 		 * into payload by drm_dp_update_payload_part1. In order to
- 		 * find sequence of a payload within allocation sequence, we
--		 * need check vcpi from proposed_vcpis*/
-+		 * need check vcpi from proposed_vcpis
-+		 */
- 
- 		table->stream_allocations[i].pbn =
- 				mst_mgr->proposed_vcpis[i]->pbn;
-@@ -259,59 +261,60 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 
- 		find_stream_for_sink = false;
- 
--		list_for_each_entry(connector,
--				&dev->mode_config.connector_list, head) {
-+		list_for_each_entry(
-+			connector,
-+			&dev->mode_config.connector_list,
-+			head) {
-+			const struct dc_sink *dc_sink_connector;
-+			struct dc_target *dc_target;
-+			uint8_t j;
- 
- 			aconnector = to_amdgpu_connector(connector);
- 
- 			/* not mst connector */
- 			if (!aconnector->mst_port)
- 				continue;
-+
- 			mst_port = aconnector->port;
- 
--			if (mst_port->vcpi.vcpi ==
--					mst_mgr->proposed_vcpis[i]->vcpi) {
--				/* find connector with same vcid as payload */
--
--				const struct dc_sink *dc_sink_connector;
--				struct core_sink *core_sink;
--				struct dc_target *dc_target;
--				struct core_target *core_target;
--				struct stream_encoder *stream_enc;
--				uint8_t j;
--
--				dc_sink_connector = aconnector->dc_sink;
--				core_sink = DC_SINK_TO_CORE(dc_sink_connector);
--
--				/* find stream to drive this sink
--				 * crtc -> target -> stream -> sink */
--				crtc = aconnector->base.state->crtc;
--				amdgpu_crtc = to_amdgpu_crtc(crtc);
--				dc_target = amdgpu_crtc->target;
--				core_target = DC_TARGET_TO_CORE(dc_target);
--
--				for (j = 0; j < core_target->stream_count;
--						j++) {
--					if (core_target->streams[j]->sink ==
--							core_sink)
--						break;
--				}
--
--				if (j < core_target->stream_count) {
--					/* find sink --> stream --> target -->
--					 * connector*/
--					stream_enc =
--					core_target->streams[j]->stream_enc;
--					table->stream_allocations[i].engine =
--							stream_enc->id;
--					/* exit loop connector */
--					find_stream_for_sink = true;
-+			if (mst_port->vcpi.vcpi !=
-+					mst_mgr->proposed_vcpis[i]->vcpi)
-+				continue;
-+
-+			/* find connector with same vcid as payload */
-+
-+			dc_sink_connector = aconnector->dc_sink;
-+
-+			/*
-+			 * find stream to drive this sink
-+			 * crtc -> target -> stream -> sink
-+			 */
-+			crtc = aconnector->base.state->crtc;
-+			amdgpu_crtc = to_amdgpu_crtc(crtc);
-+			dc_target = amdgpu_crtc->target;
-+
-+			for (j = 0; j < dc_target->stream_count; j++) {
-+				if (dc_target->streams[j]->sink ==
-+					dc_sink_connector)
- 					break;
--				}
-+			}
-+
-+			if (j < dc_target->stream_count) {
-+				/*
-+				 * find sink --> stream --> target -->
-+				 * connector
-+				 */
-+				table->stream_allocations[i].engine =
-+					dc_target->streams[j];
-+				/* exit loop connector */
-+				find_stream_for_sink = true;
-+				break;
- 			}
- 		}
-+
- 		if (!find_stream_for_sink) {
--			/* TODO: do not find stream for sink. This should not
-+			/*
-+			 * TODO: do not find stream for sink. This should not
- 			 * happen
- 			 */
- 			ASSERT(0);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 9243c01..1a8d8d6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -59,6 +59,7 @@ static void construct(
- 
- 	target->ctx = ctx;
- 	target->stream_count = stream_count;
-+	target->public.stream_count = stream_count;
- }
- 
- static void destruct(struct core_target *core_target)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 0cb9d77..77fa4c8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -145,7 +145,7 @@ bool dc_commit_surfaces_to_target(
- #define MAX_STREAM_NUM 1
- 
- struct dc_target {
--	uint32_t temp;
-+	uint8_t stream_count;
- 	const struct dc_stream *streams[MAX_STREAM_NUM];
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index bd3dd6d..796c1ea 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -392,7 +392,7 @@ struct mst_device_info {
- /* DP MST stream allocation (payload bandwidth number) */
- struct dp_mst_stream_allocation {
- 	/* stream engine id (DIG) */
--	enum engine_id engine;
-+	const struct dc_stream *engine;
- 	/* number of slots required for the DP stream in
- 	 * transport packet */
- 	uint32_t slot_count;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0537-drm-amd-dal-keep-streams-in-public-target.patch b/common/recipes-kernel/linux/files/0537-drm-amd-dal-keep-streams-in-public-target.patch
deleted file mode 100644
index 46e43b74..00000000
--- a/common/recipes-kernel/linux/files/0537-drm-amd-dal-keep-streams-in-public-target.patch
+++ /dev/null
@@ -1,567 +0,0 @@
-From 2e9920f97abd7b84fadfb4b2e741ec6fba266bfb Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 30 Nov 2015 15:08:32 +0800
-Subject: [PATCH 0537/1110] drm/amd/dal: keep streams in public target
-
-In order to remove copy of the same information from core_target
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 25 +++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 22 ++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 60 +++++++++++--------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 64 ++++++++++++---------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 67 +++++++++++++---------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  2 -
- 6 files changed, 141 insertions(+), 99 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e13ce4e..286bdde 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -690,12 +690,13 @@ const struct dc_target *dc_get_target_on_irq_source(
- 		break;
- 	default:
- 		dal_error("%s: invalid irq source: %d\n!",__func__, src);
--		goto fail;
-+		return NULL;
- 	}
- 
- 	for (i = 0; i < dc->current_context.target_count; i++) {
--		const struct core_target *target =
--				dc->current_context.targets[i];
-+		struct core_target *target = dc->current_context.targets[i];
-+
-+		struct dc_target *dc_target;
- 
- 		if (NULL == target) {
- 			dal_error("%s: 'dc_target' is NULL for irq source: %d\n!",
-@@ -703,14 +704,18 @@ const struct dc_target *dc_get_target_on_irq_source(
- 			continue;
- 		}
- 
--		for (j = 0; j < target->stream_count; j++) {
--			const uint8_t controller_idx =
--					target->streams[j]->controller_idx;
-+		dc_target = &target->public;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct core_stream *stream =
-+				DC_STREAM_TO_CORE(dc_target->streams[j]);
-+			const uint8_t controller_idx = stream->controller_idx;
-+
- 			if (controller_idx == crtc_idx)
--				return &target->public;
-+				return dc_target;
- 		}
- 	}
--fail:
-+
- 	return NULL;
- }
- 
-@@ -749,6 +754,7 @@ void dc_print_sync_report(
- {
- 	uint32_t i;
- 	const struct core_target *core_target;
-+	const struct core_stream *core_stream;
- 	struct dc_context *dc_ctx = dc->ctx;
- 	struct dc_target_sync_report *target_sync_report;
- 	struct dc_sync_report sync_report = { 0 };
-@@ -767,9 +773,10 @@ void dc_print_sync_report(
- 
- 		core_target = dc->current_context.targets[i];
- 		target_sync_report = &sync_report.trg_reports[i];
-+		core_stream = DC_STREAM_TO_CORE(core_target->public.streams[0]);
- 
- 		dc->hwss.get_crtc_positions(
--			core_target->streams[0]->tg,
-+			core_stream->tg,
- 			&target_sync_report->h_count,
- 			&target_sync_report->v_count);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index e5b1d02..f1f7347 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -88,12 +88,15 @@ struct clock_source *find_used_clk_src_for_sharing(
- 	uint8_t i, j;
- 	for (i = 0; i < context->target_count; i++) {
- 		struct core_target *target = context->targets[i];
--		for (j = 0; j < target->stream_count; j++)
--		{
--			if (target->streams[j]->clock_source == NULL)
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *clock_source_stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			if (clock_source_stream->clock_source == NULL)
- 				continue;
--			if (is_sharable_clk_src(target->streams[j], stream))
--				return target->streams[j]->clock_source;
-+
-+			if (is_sharable_clk_src(clock_source_stream, stream))
-+				return clock_source_stream->clock_source;
- 		}
- 	}
- 
-@@ -363,9 +366,12 @@ void build_scaling_params_for_context(
- 		if (context->target_flags[i].unchanged)
- 			continue;
- 		for (j = 0; j < target->status.surface_count; j++) {
--			const struct dc_surface *surface = target->status.surfaces[j];
--			for (k = 0; k < target->stream_count; k++) {
--				struct core_stream *stream = target->streams[k];
-+			const struct dc_surface *surface =
-+				target->status.surfaces[j];
-+			for (k = 0; k < target->public.stream_count; k++) {
-+				struct core_stream *stream =
-+					DC_STREAM_TO_CORE(
-+						target->public.streams[k]);
- 
- 				build_scaling_params(surface, stream);
- 			}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 1a8d8d6..6e89050 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -52,13 +52,11 @@ static void construct(
- {
- 	uint8_t i;
- 	for (i = 0; i < stream_count; i++) {
--		target->streams[i] = DC_STREAM_TO_CORE(dc_streams[i]);
- 		target->public.streams[i] = dc_streams[i];
- 		dc_stream_retain(dc_streams[i]);
- 	}
- 
- 	target->ctx = ctx;
--	target->stream_count = stream_count;
- 	target->public.stream_count = stream_count;
- }
- 
-@@ -68,11 +66,12 @@ static void destruct(struct core_target *core_target)
- 
- 	for (i = 0; i < core_target->status.surface_count; i++) {
- 		dc_surface_release(core_target->status.surfaces[i]);
--		core_target->status.surfaces[i] = 0;
-+		core_target->status.surfaces[i] = NULL;
- 	}
--	for (i = 0; i < core_target->stream_count; i++) {
--		dc_stream_release(&core_target->streams[i]->public);
--		core_target->streams[i] = 0;
-+	for (i = 0; i < core_target->public.stream_count; i++) {
-+		dc_stream_release(
-+			(struct dc_stream *)core_target->public.streams[i]);
-+		core_target->public.streams[i] = NULL;
- 	}
- }
- 
-@@ -222,8 +221,10 @@ bool dc_commit_surfaces_to_target(
- 	}
- 
- 	for (i = 0; i < surface_count; i++)
--		for (j = 0; j < target->stream_count; j++)
--			build_scaling_params(surfaces[i], target->streams[j]);
-+		for (j = 0; j < target->public.stream_count; j++)
-+			build_scaling_params(
-+				surfaces[i],
-+				DC_STREAM_TO_CORE(target->public.streams[j]));
- 
- 	if (dc->hwss.validate_bandwidth(dc, &dc->current_context) != DC_OK) {
- 		BREAK_TO_DEBUGGER();
-@@ -247,8 +248,8 @@ bool dc_commit_surfaces_to_target(
- 		dc_surface_retain(surface);
- 
- 		program_gamma(dc->ctx, surface,
--				target->streams[0]->ipp,
--				target->streams[0]->opp);
-+			DC_STREAM_TO_CORE(target->public.streams[0])->ipp,
-+			DC_STREAM_TO_CORE(target->public.streams[0])->opp);
- 
- 		dc->hwss.set_plane_config(
- 			core_surface,
-@@ -277,8 +278,8 @@ bool dc_target_is_connected_to_sink(
- {
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
- 	uint8_t i;
--	for (i = 0; i < target->stream_count; i++) {
--		if (&target->streams[i]->sink->public == dc_sink)
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		if (target->public.streams[i]->sink == dc_sink)
- 			return true;
- 	}
- 	return false;
-@@ -288,9 +289,11 @@ void dc_target_enable_memory_requests(struct dc_target *target)
- {
- 	uint8_t i;
- 	struct core_target *core_target = DC_TARGET_TO_CORE(target);
--	for (i = 0; i < core_target->stream_count; i++) {
--	struct timing_generator *tg = core_target->streams[i]->tg;
--		if (false == core_target->ctx->dc->hwss.enable_memory_requests(tg)) {
-+	for (i = 0; i < core_target->public.stream_count; i++) {
-+		struct timing_generator *tg =
-+			DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
-+
-+		if (!core_target->ctx->dc->hwss.enable_memory_requests(tg)) {
- 			dal_error("DC: failed to unblank crtc!\n");
- 			BREAK_TO_DEBUGGER();
- 		}
-@@ -301,8 +304,9 @@ void dc_target_disable_memory_requests(struct dc_target *target)
- {
- 	uint8_t i;
- 	struct core_target *core_target = DC_TARGET_TO_CORE(target);
--	for (i = 0; i < core_target->stream_count; i++) {
--	struct timing_generator *tg = core_target->streams[i]->tg;
-+	for (i = 0; i < core_target->public.stream_count; i++) {
-+	struct timing_generator *tg =
-+		DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
- 
- 		if (NULL == tg) {
- 			dal_error("DC: timing generator is NULL!\n");
-@@ -334,7 +338,7 @@ bool dc_target_set_cursor_attributes(
- 	}
- 
- 	core_target = DC_TARGET_TO_CORE(dc_target);
--	ipp = core_target->streams[0]->ipp;
-+	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
- 
- 	if (NULL == ipp) {
- 		dal_error("DC: input pixel processor is NULL!\n");
-@@ -365,7 +369,7 @@ bool dc_target_set_cursor_position(
- 	}
- 
- 	core_target = DC_TARGET_TO_CORE(dc_target);
--	ipp = core_target->streams[0]->ipp;
-+	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
- 
- 	if (NULL == ipp) {
- 		dal_error("DC: input pixel processor is NULL!\n");
-@@ -383,14 +387,17 @@ bool dc_target_set_cursor_position(
- uint8_t dc_target_get_link_index(const struct dc_target *dc_target)
- {
- 	const struct core_target *target = CONST_DC_TARGET_TO_CORE(dc_target);
-+	const struct core_sink *sink =
-+		DC_SINK_TO_CORE(target->public.streams[0]->sink);
- 
--	return target->streams[0]->sink->link->link_index;
-+	return sink->link->link_index;
- }
- 
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- {
- 	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
--	struct timing_generator *tg = core_target->streams[0]->tg;
-+	struct timing_generator *tg =
-+		DC_STREAM_TO_CORE(core_target->public.streams[0])->tg;
- 
- 	return core_target->ctx->dc->hwss.get_vblank_counter(tg);
- }
-@@ -402,7 +409,9 @@ enum dc_irq_source dc_target_get_irq_src(
- 
- 	/* #TODO - Remove the assumption that the controller is always in the
- 	 * first stream of a core target */
--	uint8_t controller_idx = core_target->streams[0]->controller_idx;
-+	struct core_stream *stream =
-+		DC_STREAM_TO_CORE(core_target->public.streams[0]);
-+	uint8_t controller_idx = stream->controller_idx;
- 
- 	/* Get controller id */
- 	enum controller_id crtc_id = controller_idx + 1;
-@@ -434,10 +443,11 @@ void dc_target_log(
- 			"core_target 0x%x: surface_count=%d, stream_count=%d",
- 			core_target,
- 			core_target->status.surface_count,
--			core_target->stream_count);
-+			core_target->public.stream_count);
- 
--	for (i = 0; i < core_target->stream_count; i++) {
--		const struct core_stream *core_stream = core_target->streams[i];
-+	for (i = 0; i < core_target->public.stream_count; i++) {
-+		const struct core_stream *core_stream =
-+			DC_STREAM_TO_CORE(core_target->public.streams[i]);
- 
- 		dal_logger_write(dal_logger,
- 			log_major,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index cbe27a4..29e7b80 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1010,7 +1010,7 @@ static void power_down_encoders(struct validate_context *context)
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		target = context->targets[i];
--		stream = target->streams[0];
-+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 		core_link_disable(stream);
- 	}
- }
-@@ -1023,7 +1023,7 @@ static void power_down_controllers(struct validate_context *context)
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		target = context->targets[i];
--		stream = target->streams[0];
-+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 
- 		dce110_timing_generator_disable_crtc(stream->tg);
- 	}
-@@ -1037,7 +1037,7 @@ static void power_down_clock_sources(struct validate_context *context)
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		target = context->targets[i];
--		stream = target->streams[0];
-+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 
- 		if (false == dal_clock_source_power_down_pll(
- 				stream->clock_source,
-@@ -1074,7 +1074,7 @@ static void disable_vga_and_power_gate_all_controllers(
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		target = context->targets[i];
--		stream = target->streams[0];
-+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 		tg = stream->tg;
- 		ctx = stream->ctx;
- 		controller_id = stream->controller_idx;
-@@ -1257,8 +1257,9 @@ static void set_displaymarks(
- 	for (i = 0; i < target_count; i++) {
- 		struct core_target *target = context->targets[i];
- 
--		for (j = 0; j < target->stream_count; j++) {
--			struct core_stream *stream = target->streams[j];
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
- 			dce110_mem_input_program_display_marks(
- 				stream->mi,
-@@ -1285,8 +1286,9 @@ static void set_safe_displaymarks(struct validate_context *context)
- 	for (i = 0; i < target_count; i++) {
- 		struct core_target *target = context->targets[i];
- 
--		for (j = 0; j < target->stream_count; j++) {
--			struct core_stream *stream = target->streams[j];
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
- 			dce110_mem_input_program_safe_display_marks(stream->mi);
- 		}
-@@ -1348,8 +1350,9 @@ static void switch_dp_clock_sources(
- 	uint8_t i, j;
- 	for (i = 0; i < val_context->target_count; i++) {
- 		struct core_target *target = val_context->targets[i];
--		for (j = 0; j < target->stream_count; j++) {
--			struct core_stream *stream = target->streams[j];
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
- 			if (dc_is_dp_signal(stream->signal)) {
- 				struct clock_source *clk_src =
-@@ -1556,15 +1559,17 @@ static bool set_plane_config(
- 	struct core_surface *surface,
- 	struct core_target *target)
- {
-+	const struct core_stream *core_stream =
-+		DC_STREAM_TO_CORE(target->public.streams[0]);
- 	const struct dc_crtc_timing *dc_crtc_timing =
--			&target->streams[0]->public.timing;
--	struct mem_input *mi = target->streams[0]->mi;
--	struct input_pixel_processor *ipp = target->streams[0]->ipp;
--	struct timing_generator *tg = target->streams[0]->tg;
--	struct transform *xfm = target->streams[0]->xfm;
--	struct output_pixel_processor *opp = target->streams[0]->opp;
--	struct dc_context *ctx = target->streams[0]->ctx;
--	uint8_t controller_idx = target->streams[0]->controller_idx;
-+			&target->public.streams[0]->timing;
-+	struct mem_input *mi = core_stream->mi;
-+	struct input_pixel_processor *ipp = core_stream->ipp;
-+	struct timing_generator *tg = core_stream->tg;
-+	struct transform *xfm = core_stream->xfm;
-+	struct output_pixel_processor *opp = core_stream->opp;
-+	struct dc_context *ctx = core_stream->ctx;
-+	uint8_t controller_idx = core_stream->controller_idx;
- 
- 	/* TODO: Clean up change, possibly change to use same type */
- 	enum color_space input_color_space =
-@@ -1590,14 +1595,14 @@ static bool set_plane_config(
- 	set_default_colors(
- 			ipp,
- 			opp,
--			target->streams[0]->format,
-+			core_stream->format,
- 			input_color_space,
- 			get_output_color_space(dc_crtc_timing),
- 			dc_crtc_timing->display_color_depth);
- 
- 	/* program Scaler */
- 	program_scaler(
--		controller_idx, tg, xfm, surface, target->streams[0]);
-+		controller_idx, tg, xfm, surface, core_stream);
- 
- 	set_blender_mode(
- 			ctx,
-@@ -1634,9 +1639,11 @@ static bool update_plane_address(
- 	const struct core_surface *surface,
- 	struct core_target *target)
- {
--	struct dc_context *ctx = target->streams[0]->ctx;
--	struct mem_input *mi = target->streams[0]->mi;
--	uint8_t controller_id = target->streams[0]->controller_idx;
-+	const struct core_stream *core_stream =
-+		DC_STREAM_TO_CORE(target->public.streams[0]);
-+	struct dc_context *ctx = core_stream->ctx;
-+	struct mem_input *mi = core_stream->mi;
-+	uint8_t controller_id = core_stream->controller_idx;
- 
- 	/* TODO: crtc should be per surface, NOT per-target */
- 	pipe_control_lock(
-@@ -1688,17 +1695,18 @@ static void reset_hw_ctx(struct dc *dc,
- 	uint8_t i;
- 	/* look up the targets that have been removed since last commit */
- 	for (i = 0; i < dc->current_context.target_count; i++) {
--		uint8_t controller_idx = dc->current_context.targets[i]->
--						streams[0]->controller_idx;
-+		const struct core_target *core_target =
-+			dc->current_context.targets[i];
-+		struct core_stream *core_stream =
-+			DC_STREAM_TO_CORE(core_target->public.streams[0]);
-+		uint8_t controller_idx = core_stream->controller_idx;
- 
- 		if (context->res_ctx.controller_ctx[controller_idx].stream &&
- 				!context->res_ctx.controller_ctx[controller_idx]
- 				.flags.timing_changed)
- 			continue;
- 
--		reset_single_stream_hw_ctx(
--			dc->current_context.targets[i]->streams[0],
--			&dc->current_context);
-+		reset_single_stream_hw_ctx(core_stream, &dc->current_context);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 126ebd2..de71d39 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -876,35 +876,43 @@ static enum dc_status map_resources(
- 	/* mark resources used for targets that are already active */
- 	for (i = 0; i < context->target_count; i++) {
- 		struct core_target *target = context->targets[i];
--		if (context->target_flags[i].unchanged)
--			for (j = 0; j < target->stream_count; j++) {
--				struct core_stream *stream = target->streams[j];
--				attach_stream_to_controller(
--						&context->res_ctx,
--						stream);
--
--				set_stream_engine_in_use(
--						&context->res_ctx,
--						stream->stream_enc);
--
--				reference_clock_source(
--						&context->res_ctx,
--						stream->clock_source);
--
--				if (stream->audio) {
--					set_audio_in_use(&context->res_ctx,
--							stream->audio);
--				}
-+
-+		if (!context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			attach_stream_to_controller(
-+				&context->res_ctx,
-+				stream);
-+
-+			set_stream_engine_in_use(
-+				&context->res_ctx,
-+				stream->stream_enc);
-+
-+			reference_clock_source(
-+				&context->res_ctx,
-+				stream->clock_source);
-+
-+			if (stream->audio) {
-+				set_audio_in_use(&context->res_ctx,
-+					stream->audio);
- 			}
-+		}
- 	}
- 
- 	/* acquire new resources */
- 	for (i = 0; i < context->target_count; i++) {
- 		struct core_target *target = context->targets[i];
-+
- 		if (context->target_flags[i].unchanged)
- 			continue;
--		for (j = 0; j < target->stream_count; j++) {
--			struct core_stream *stream = target->streams[j];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct core_stream *curr_stream;
- 
- 			if (!assign_first_free_controller(
-@@ -1103,9 +1111,11 @@ static enum dc_status validate_mapped_resource(
- 		struct core_target *target = context->targets[i];
- 		if (context->target_flags[i].unchanged)
- 			continue;
--		for (j = 0; j < target->stream_count; j++) {
--			struct core_stream *stream = target->streams[j];
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct core_link *link = stream->sink->link;
-+
- 			status = build_stream_hw_param(stream);
- 
- 			if (status != DC_OK)
-@@ -1152,8 +1162,9 @@ enum dc_status dce110_validate_bandwidth(
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		struct core_target *target = context->targets[i];
--		for (j = 0; j < target->stream_count; j++) {
--			struct core_stream *stream = target->streams[j];
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct bw_calcs_input_single_display *disp = &context->
- 				bw_mode_data.displays_data[number_of_displays];
- 
-@@ -1241,8 +1252,10 @@ static void set_target_unchanged(
- 	uint8_t i;
- 	struct core_target *target = context->targets[target_idx];
- 	context->target_flags[target_idx].unchanged = true;
--	for (i = 0; i < target->stream_count; i++) {
--		uint8_t index = target->streams[i]->controller_idx;
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		struct core_stream *core_stream =
-+			DC_STREAM_TO_CORE(target->public.streams[i]);
-+		uint8_t index = core_stream->controller_idx;
- 		context->res_ctx.controller_ctx[index].flags.unchanged = true;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index f18034c..b636a9c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -46,8 +46,6 @@ struct core_target {
- 	struct dc_target public;
- 	struct dc_target_status status;
- 
--	struct core_stream *streams[MAX_STREAMS];
--	uint8_t stream_count;
- 	struct dc_context *ctx;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0538-drm-amd-dal-Add-PPLib-interfaces-to-get-Static-Clock.patch b/common/recipes-kernel/linux/files/0538-drm-amd-dal-Add-PPLib-interfaces-to-get-Static-Clock.patch
deleted file mode 100644
index af73cfdc..00000000
--- a/common/recipes-kernel/linux/files/0538-drm-amd-dal-Add-PPLib-interfaces-to-get-Static-Clock.patch
+++ /dev/null
@@ -1,198 +0,0 @@
-From d94eb061338a573c1303a95fcc51d45162f20c90 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Mon, 30 Nov 2015 14:42:51 -0500
-Subject: [PATCH 0538/1110] drm/amd/dal: Add PPLib interfaces to get Static
- Clocks and Clocks-by-level.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    | 54 ++++++++++++++-----
- drivers/gpu/drm/amd/dal/dc/dc_services.h           | 60 ++++++++++++++++++++--
- 2 files changed, 98 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index a497093..ba54282 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -147,17 +147,20 @@ bool dal_get_platform_info(struct dc_context *ctx,
- 	return false;
- }
- 
--/* Next calls are to power component */
--bool dc_service_pp_pre_dce_clock_change(struct dc_context *ctx,
--				struct dal_to_power_info *input,
--				struct power_to_dal_info *output)
-+/**** power component interfaces ****/
-+
-+bool dc_service_pp_pre_dce_clock_change(
-+		struct dc_context *ctx,
-+		struct dal_to_power_info *input,
-+		struct power_to_dal_info *output)
- {
- 	/*TODO*/
- 	return false;
- }
- 
--bool dc_service_pp_post_dce_clock_change(struct dc_context *ctx,
--	const struct dc_pp_display_configuration *pp_display_cfg)
-+bool dc_service_pp_post_dce_clock_change(
-+		struct dc_context *ctx,
-+		const struct dc_pp_display_configuration *pp_display_cfg)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	struct amdgpu_device *adev = ctx->driver_context;
-@@ -179,6 +182,11 @@ bool dc_service_pp_post_dce_clock_change(struct dc_context *ctx,
- 		adev->pm.pm_display_cfg.nb_pstate_switch_disable =
- 			pp_display_cfg->nb_pstate_switch_disable;
- 
-+		/* TODO: complete implementation of
-+		 * amd_powerplay_display_configuration_change().
-+		 * Follow example of:
-+		 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
-+		 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
- 		amd_powerplay_display_configuration_change(
- 				adev->powerplay.pp_handle,
- 				&adev->pm.pm_display_cfg);
-@@ -192,8 +200,9 @@ bool dc_service_pp_post_dce_clock_change(struct dc_context *ctx,
- #endif
- }
- 
--bool dc_service_get_system_clocks_range(struct dc_context *ctx,
--				struct dal_system_clock_range *sys_clks)
-+bool dc_service_get_system_clocks_range(
-+		struct dc_context *ctx,
-+		struct dal_system_clock_range *sys_clks)
- {
- 	struct amdgpu_device *adev = ctx->driver_context;
- 
-@@ -218,14 +227,35 @@ bool dc_service_get_system_clocks_range(struct dc_context *ctx,
- }
- 
- 
--bool dc_service_pp_set_display_clock(struct dc_context *ctx,
--			     struct dal_to_power_dclk *dclk)
-+bool dc_service_get_clock_levels_by_type(
-+		struct dc_context *ctx,
-+		enum dc_pp_clock_type clk_type,
-+		struct dc_pp_clock_levels *clk_level_info)
- {
--	/* TODO: need power component to provide appropriate interface */
-+	/* TODO: follow implementation of:
-+	 * PhwCz_GetClocksByType - powerplay\hwmgr\cz_hwmgr.c
-+	 * PHM_GetClockByType - powerplay\hwmgr\hardwaremanager.c
-+	 * PP_IRI_GetClockByType - powerplay\eventmgr\iri.c */
-+
-+	DRM_INFO("%s - not implemented\n", __func__);
- 	return false;
- }
- 
--/* end of calls to power component */
-+bool dc_service_get_static_clocks(
-+	struct dc_context *ctx,
-+	struct dc_pp_static_clock_info *static_clk_info)
-+{
-+	/* TODO: follow implementation of:
-+	 * PhwCz_GetDALPowerLevel - powerplay\hwmgr\cz_hwmgr.c
-+	 * PHM_GetDALPowerLevel - powerplay\hwmgr\hardwaremanager.c
-+	 * PP_IRI_GetStaticClocksInfo - powerplay\eventmgr\iri.c */
-+
-+	DRM_INFO("%s - not implemented\n", __func__);
-+	return false;
-+}
-+
-+/**** end of power component interfaces ****/
-+
- 
- /* Calls to notification */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index f430864..6290885 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -64,7 +64,7 @@ void dc_service_unregister_interrupt(
- 	irq_handler_idx handler_idx);
- 
- /**************************************
-- * Calls to Power Play (PP) component
-+ * Power Play (PP) interfaces
-  **************************************/
- 
- /* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-@@ -95,6 +95,47 @@ struct dc_pp_display_configuration {
- 	uint32_t cpu_pstate_separation_time;
- };
- 
-+enum dc_pp_clock_type {
-+	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-+	DC_PP_CLOCK_TYPE_ENGINE_CLK,
-+	DC_PP_CLOCK_TYPE_MEMORY_CLK
-+};
-+
-+#define DC_PP_MAX_CLOCK_LEVELS 8
-+
-+struct dc_pp_clock_levels {
-+	enum dc_pp_clock_type clock_type;
-+	uint32_t num_levels;
-+	uint32_t clocks_in_hz[DC_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+enum dc_pp_clocks_state {
-+	DC_PP_CLOCKS_STATE_INVALID = 0,
-+	DC_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DC_PP_CLOCKS_STATE_LOW,
-+	DC_PP_CLOCKS_STATE_NOMINAL,
-+	DC_PP_CLOCKS_STATE_PERFORMANCE,
-+
-+	/* Starting from DCE11, Max 8 levels of DPM state supported. */
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DC_PP_CLOCKS_STATE_INVALID,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_0 = DC_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_1 = DC_PP_CLOCKS_STATE_LOW,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_2 = DC_PP_CLOCKS_STATE_NOMINAL,
-+	/* to be backward compatible */
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_3 = DC_PP_CLOCKS_STATE_PERFORMANCE,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_4 = DC_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_5 = DC_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_6 = DC_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_7 = DC_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
-+};
-+
-+struct dc_pp_static_clock_info {
-+	uint32_t max_engine_clock_hz;
-+	uint32_t max_memory_clock_hz;
-+	 /* max possible display block clocks state */
-+	enum dc_pp_clocks_state max_clocks_state;
-+};
-+
- /* DAL calls this function to notify PP about completion of Mode Set.
-  * For PP it means that current DCE clocks are those which were returned
-  * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-@@ -120,10 +161,21 @@ bool dc_service_get_system_clocks_range(
- 	struct dc_context *ctx,
- 	struct dal_system_clock_range *sys_clks);
- 
--/* for future use */
--bool dc_service_pp_set_display_clock(
-+
-+bool dc_service_get_clock_levels_by_type(
- 	struct dc_context *ctx,
--	struct dal_to_power_dclk *dclk);
-+	enum dc_pp_clock_type clk_type,
-+	struct dc_pp_clock_levels *clk_level_info);
-+
-+/* Use this for mode validation.
-+ * TODO: when this interface is implemented on Linux, should we remove
-+ * dc_service_get_system_clocks_range() ?? */
-+bool dc_service_get_static_clocks(
-+	struct dc_context *ctx,
-+	struct dc_pp_static_clock_info *static_clk_info);
-+
-+
-+/****** end of PP interfaces ******/
- 
- void dc_service_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0539-drm-amd-dal-Fix-engine_id-usage-in-update_mst_stream.patch b/common/recipes-kernel/linux/files/0539-drm-amd-dal-Fix-engine_id-usage-in-update_mst_stream.patch
deleted file mode 100644
index 3adb8452..00000000
--- a/common/recipes-kernel/linux/files/0539-drm-amd-dal-Fix-engine_id-usage-in-update_mst_stream.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 2205d2e6213fc8890b47a8e1b1d7bddeaddf3e41 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Mon, 30 Nov 2015 16:06:40 -0500
-Subject: [PATCH 0539/1110] drm/amd/dal: Fix engine_id usage in
- update_mst_stream_allocation_table
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 14 +++++++++++---
- 1 file changed, 11 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index bd3962e..91796ac 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -26,6 +26,7 @@
- #include "dal_services.h"
- #include "core_types.h"
- #include "link_encoder_types.h"
-+#include "stream_encoder_types.h"
- #include "dce110_link_encoder.h"
- #include "i2caux_interface.h"
- #include "dce/dce_11_0_d.h"
-@@ -1594,6 +1595,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	uint32_t value0;
- 	uint32_t value1;
- 	uint32_t retries = 0;
-+	struct core_stream *core_stream = NULL;
- 
- 	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
- 
-@@ -1605,9 +1607,11 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
- 
- 	if (table->stream_count >= 1) {
-+		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[0].engine);
-+
- 		set_reg_field_value(
- 			value0,
--			table->stream_allocations[0].engine,
-+			core_stream->stream_enc->id,
- 			DP_MSE_SAT0,
- 			DP_MSE_SAT_SRC0);
- 
-@@ -1619,9 +1623,11 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	}
- 
- 	if (table->stream_count >= 2) {
-+		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[1].engine);
-+
- 		set_reg_field_value(
- 			value0,
--			table->stream_allocations[1].engine,
-+			core_stream->stream_enc->id,
- 			DP_MSE_SAT0,
- 			DP_MSE_SAT_SRC1);
- 
-@@ -1633,9 +1639,11 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	}
- 
- 	if (table->stream_count >= 3) {
-+		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[2].engine);
-+
- 		set_reg_field_value(
- 			value1,
--			table->stream_allocations[2].engine,
-+			core_stream->stream_enc->id,
- 			DP_MSE_SAT1,
- 			DP_MSE_SAT_SRC2);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0540-drm-amd-dal-Fix-bug-for-DP-MST-audio.patch b/common/recipes-kernel/linux/files/0540-drm-amd-dal-Fix-bug-for-DP-MST-audio.patch
deleted file mode 100644
index 530370ea..00000000
--- a/common/recipes-kernel/linux/files/0540-drm-amd-dal-Fix-bug-for-DP-MST-audio.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 0c3d341226575f99ee5c9860e952bbb40e3c5cee Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Mon, 30 Nov 2015 16:31:55 -0500
-Subject: [PATCH 0540/1110] drm/amd/dal: Fix bug for DP MST audio
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 13 +++++++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c              | 18 +++++-------------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  4 ++--
- 3 files changed, 16 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index a08468b..86c17e6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -24,14 +24,11 @@
-  */
- 
- #include "dal_services.h"
--
- #include "amdgpu.h"
--
- #include "amdgpu_dm_types.h"
--
- #include "amdgpu_dm_mst_types.h"
--
- #include "dc.h"
-+#include "dc_helpers.h"
- 
- static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
- {
-@@ -111,6 +108,7 @@ static const struct dc_sink *dm_dp_mst_add_mst_sink(
- 	struct sink_init_data init_params = {
- 			.link = dc_link,
- 			.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST};
-+	enum dc_edid_status edid_status;
- 
- 	if (len > MAX_EDID_BUFFER_SIZE) {
- 		DRM_ERROR("Max EDID buffer size breached!\n");
-@@ -135,6 +133,13 @@ static const struct dc_sink *dm_dp_mst_add_mst_sink(
- 			dc_sink))
- 		goto fail;
- 
-+	edid_status = dc_helpers_parse_edid_caps(
-+			NULL,
-+			&dc_sink->dc_edid,
-+			&dc_sink->edid_caps);
-+	if (edid_status != EDID_OK)
-+		goto fail;
-+
- 	/* dc_sink_retain(&core_sink->public); */
- 
- 	return dc_sink;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 647d141..2ae41c7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -367,20 +367,12 @@ static void link_unplug(struct core_link *link)
- 	link->dpcd_sink_count = 0;
- }
- 
--static enum dc_edid_status read_edid(struct core_link *link)
-+static enum dc_edid_status read_edid(
-+	struct core_link *link,
-+	struct core_sink *sink)
- {
- 	uint32_t edid_retry = 3;
- 	enum dc_edid_status edid_status;
--	const struct dc_sink *dc_sink = link->public.sink[0];
--	struct core_sink *sink = DC_SINK_TO_CORE(dc_sink);
--
--	if (link->public.sink[0]->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
--		dal_logger_write(link->ctx->logger,
--							LOG_MAJOR_WARNING,
--							LOG_MINOR_DETECTION_EDID_PARSER,
--							"MST EDID read is not done here!\n");
--		return EDID_BAD_INPUT;
--	}
- 
- 	/* some dongles read edid incorrectly the first time,
- 	 * do check sum and retry to make sure read correct edid.
-@@ -395,7 +387,7 @@ static enum dc_edid_status read_edid(struct core_link *link)
- 		dal_ddc_service_get_edid_buf(link->ddc,
- 				sink->public.dc_edid.raw_edid);
- 		edid_status = dc_helpers_parse_edid_caps(
--				link->ctx,
-+				NULL,
- 				&sink->public.dc_edid,
- 				&sink->public.edid_caps);
- 		--edid_retry;
-@@ -580,7 +572,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		if (!dc_link_add_sink(&link->public, &sink->public))
- 				BREAK_TO_DEBUGGER();
- 
--		edid_status = read_edid(link);
-+		edid_status = read_edid(link, sink);
- 
- 		switch (edid_status) {
- 		case EDID_BAD_CHECKSUM:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index de71d39..37ffc0e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1044,8 +1044,8 @@ static void build_audio_output(
- 	audio_output->crtc_info.calculated_pixel_clock =
- 			stream->pix_clk_params.requested_pix_clk;
- 
--	/* TODO: This is needed for DP */
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
- 		audio_output->pll_info.dp_dto_source_clock_in_khz =
- 			dal_display_clock_get_dp_ref_clk_frequency(
- 				stream->dis_clk);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0541-drm-amd-dal-add-active-dongle-downstream-hotplug-han.patch b/common/recipes-kernel/linux/files/0541-drm-amd-dal-add-active-dongle-downstream-hotplug-han.patch
deleted file mode 100644
index 9f4ea4ee..00000000
--- a/common/recipes-kernel/linux/files/0541-drm-amd-dal-add-active-dongle-downstream-hotplug-han.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From d0cba8cced836a355e30dfccf70c90f3ee7d39fa Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 30 Nov 2015 16:50:11 -0500
-Subject: [PATCH 0541/1110] drm/amd/dal: add active dongle downstream hotplug
- handling
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c      | 16 ++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c |  8 +++-----
- 2 files changed, 11 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 286bdde..60cbb47 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -839,17 +839,17 @@ void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink)
- 	int i;
- 
- 	if (!link->sink_count) {
--	   BREAK_TO_DEBUGGER();
--	   return;
-+		BREAK_TO_DEBUGGER();
-+		return;
- 	}
- 
- 	for (i = 0; i < link->sink_count; i++) {
--		   if (link->sink[i] == sink) {
--			   dc_sink_release(sink);
--			   link->sink[i] = NULL;
--			   link->sink_count--;
--			   return;
--		   }
-+		if (link->sink[i] == sink) {
-+			dc_sink_release(sink);
-+			link->sink[i] = NULL;
-+			link->sink_count--;
-+			return;
-+		}
- 	}
- 
- 	BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 2ae41c7..ba087b3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -355,9 +355,7 @@ static bool is_dp_active_dongle(enum display_dongle_type dongle_type)
- 		dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
- }
- 
--/* TODO: To beretired because this call is wrong with
-- * pluging in of active-dongle without display*/
--static void link_unplug(struct core_link *link)
-+static void link_disconnect_all_sinks(struct core_link *link)
- {
- 	int i;
- 
-@@ -476,7 +474,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 						/* active dongle unplug
- 						 * processing for short irq
- 						 */
--						link_unplug(link);
-+						link_disconnect_all_sinks(link);
- 						return;
- 					}
- 
-@@ -640,7 +638,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		default:
- 			break;
- 		}
--		link_unplug(link);
-+		link_disconnect_all_sinks(link);
- 	}
- 
- 	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0542-drm-amd-dal-small-refactoring-in-DP-related-code.patch b/common/recipes-kernel/linux/files/0542-drm-amd-dal-small-refactoring-in-DP-related-code.patch
deleted file mode 100644
index 4d1a5e40..00000000
--- a/common/recipes-kernel/linux/files/0542-drm-amd-dal-small-refactoring-in-DP-related-code.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 4f1d9df2b807835c4c977392abcb0e65b2f51f46 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 1 Dec 2015 18:26:31 +0800
-Subject: [PATCH 0542/1110] drm/amd/dal: small refactoring in DP related code
-
-Reuse regular DP code in MST case instead of duplication
-Ident properly few places in link training code
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c   | 16 ++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 12 ++----------
- 2 files changed, 10 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 9214aec..71e6f8c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1315,9 +1315,9 @@ static bool hpd_rx_irq_check_link_loss_status(
- 	 */
- 
- 	dpcd_result = core_link_read_dpcd(link,
--	DPCD_ADDRESS_POWER_STATE,
--	&irq_reg_rx_power_state,
--	sizeof(irq_reg_rx_power_state));
-+		DPCD_ADDRESS_POWER_STATE,
-+		&irq_reg_rx_power_state,
-+		sizeof(irq_reg_rx_power_state));
- 
- 	if (dpcd_result != DC_OK) {
- 		irq_reg_rx_power_state = DP_PWR_STATE_D0;
-@@ -1333,15 +1333,15 @@ static bool hpd_rx_irq_check_link_loss_status(
- 		/*2. Check that Link Status changed, before re-training.*/
- 
- 		/*parse lane status*/
--		for (lane = 0; lane <
--			(uint32_t)(link->cur_link_settings.lane_count) &&
--			!sink_status_changed; lane++) {
-+		for (lane = 0;
-+			lane < link->cur_link_settings.lane_count;
-+			lane++) {
- 
- 			/* check status of lanes 0,1
- 			 * changed DpcdAddress_Lane01Status (0x202)*/
- 			lane_status.raw = get_nibble_at_index(
--			&hpd_irq_dpcd_data->bytes.lane01_status.raw,
--			lane);
-+				&hpd_irq_dpcd_data->bytes.lane01_status.raw,
-+				lane);
- 
- 			if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
- 				!lane_status.bits.CR_DONE_0 ||
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index e7673ed..8ef4674 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -95,18 +95,10 @@ void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
- 		}
- 	}
- 	/* MST disable link only when no stream use the link */
--	if (link->enabled_stream_count > 0) {
-+	if (link->enabled_stream_count > 0)
- 		return;
--	}
--
--	if (!link->dp_wa.bits.KEEP_RECEIVER_POWERED)
--		dp_receiver_power_ctrl(link, false);
- 
--	link->dc->hwss.encoder_disable_output(link->link_enc, stream->signal);
--
--	/* Clear current link setting.*/
--	dc_service_memset(&link->cur_link_settings, 0,
--			sizeof(link->cur_link_settings));
-+	dp_disable_link_phy(link, stream->signal);
- }
- 
- bool dp_set_hw_training_pattern(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0543-drm-amd-dal-fix-bug-in-dc_link_remove_sink.patch b/common/recipes-kernel/linux/files/0543-drm-amd-dal-fix-bug-in-dc_link_remove_sink.patch
deleted file mode 100644
index eeb74f28..00000000
--- a/common/recipes-kernel/linux/files/0543-drm-amd-dal-fix-bug-in-dc_link_remove_sink.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 7e21aac36597382339dcd4ce4a0353b45601196e Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 1 Dec 2015 18:32:26 +0800
-Subject: [PATCH 0543/1110] drm/amd/dal: fix bug in dc_link_remove_sink
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 8 ++++++++
- drivers/gpu/drm/amd/dal/dc/dc.h      | 2 +-
- 2 files changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 60cbb47..fded924 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -847,6 +847,14 @@ void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink)
- 		if (link->sink[i] == sink) {
- 			dc_sink_release(sink);
- 			link->sink[i] = NULL;
-+
-+			/* shrink array to remove empty place */
-+			dc_service_memmove(
-+				&link->sink[i],
-+				&link->sink[i + 1],
-+				(link->sink_count - i - 1) *
-+				sizeof(link->sink[i]));
-+
- 			link->sink_count--;
- 			return;
- 		}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 77fa4c8..7b611d7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -270,7 +270,7 @@ void dc_update_stream(const struct dc_stream *dc_stream,
-  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
-  */
- struct dc_link {
--	const struct dc_sink *sink[MAX_SINKS_PER_LINK]; /* TODO: multiple sink support for MST */
-+	const struct dc_sink *sink[MAX_SINKS_PER_LINK];
- 	unsigned int sink_count;
- 	enum dc_connection_type type;
- 	enum signal_type connector_signal;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0544-drm-amd-dal-fix-pflip-issue-with-mst-displays.patch b/common/recipes-kernel/linux/files/0544-drm-amd-dal-fix-pflip-issue-with-mst-displays.patch
deleted file mode 100644
index f95d8e27..00000000
--- a/common/recipes-kernel/linux/files/0544-drm-amd-dal-fix-pflip-issue-with-mst-displays.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From f69f9d619521f1698cc38e1a3324497fc858c786 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 1 Dec 2015 18:46:42 +0800
-Subject: [PATCH 0544/1110] drm/amd/dal: fix pflip issue with mst displays
-
-There is no correspondance between link and crtc indexes anymore
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 40 +++++++++++++++++++--------
- 1 file changed, 29 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 37810ff..a414586 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -349,7 +349,30 @@ static int dm_soft_reset(void *handle)
- 	return 0;
- }
- 
-+static struct amdgpu_crtc *get_crtc_by_target(
-+	struct amdgpu_device *adev,
-+	const struct dc_target *dc_target)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_crtc *crtc;
-+	struct amdgpu_crtc *amdgpu_crtc;
- 
-+	/*
-+	 * following if is check inherited from both functions where this one is
-+	 * used now. Need to be checked why it could happen.
-+	 */
-+	if (dc_target == NULL)
-+		return adev->mode_info.crtcs[0];
-+
-+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+		amdgpu_crtc = to_amdgpu_crtc(crtc);
-+
-+		if (amdgpu_crtc->target == dc_target)
-+			return amdgpu_crtc;
-+	}
-+
-+	return NULL;
-+}
- 
- static void dm_pflip_high_irq(void *interrupt_params)
- {
-@@ -361,13 +384,8 @@ static void dm_pflip_high_irq(void *interrupt_params)
- 	const struct dc *dc = irq_params->adev->dm.dc;
- 	const struct dc_target *dc_target =
- 			dc_get_target_on_irq_source(dc, irq_params->irq_src);
--	uint8_t link_index = 0;
--
--	/* TODO: #flip address all tags together*/
--	if (dc_target != NULL)
--		link_index = dc_target_get_link_index(dc_target);
- 
--	amdgpu_crtc= adev->mode_info.crtcs[link_index];
-+	amdgpu_crtc = get_crtc_by_target(adev, dc_target);
- 
- 	/* IRQ could occur when in initial stage */
- 	if(amdgpu_crtc == NULL)
-@@ -408,13 +426,13 @@ static void dm_crtc_high_irq(void *interrupt_params)
- 	const struct dc *dc = irq_params->adev->dm.dc;
- 	const struct dc_target *dc_target =
- 			dc_get_target_on_irq_source(dc, irq_params->irq_src);
--	uint8_t link_index = 0;
-+	uint8_t crtc_index = 0;
-+	struct amdgpu_crtc *acrtc = get_crtc_by_target(adev, dc_target);
- 
--	/* TODO: #flip fix all tags together*/
--	if (dc_target != NULL)
--		link_index = dc_target_get_link_index(dc_target);
-+	if (acrtc)
-+		crtc_index = acrtc->crtc_id;
- 
--	drm_handle_vblank(adev->ddev, link_index);
-+	drm_handle_vblank(adev->ddev, crtc_index);
- 
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0545-drm-amd-dal-simplify-atomic-gamma-programming-code.patch b/common/recipes-kernel/linux/files/0545-drm-amd-dal-simplify-atomic-gamma-programming-code.patch
deleted file mode 100644
index d504ee7b..00000000
--- a/common/recipes-kernel/linux/files/0545-drm-amd-dal-simplify-atomic-gamma-programming-code.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From f4bb1a4a62b205458c674f79c31fcaf8255896ff Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 1 Dec 2015 19:29:49 +0800
-Subject: [PATCH 0545/1110] drm/amd/dal: simplify atomic gamma programming code
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 67 +++++++++++-----------
- 1 file changed, 35 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 113c2e0..90bb0d2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -932,36 +932,28 @@ static void amdgpu_dm_atomic_crtc_gamma_set(
- 
- static int dm_crtc_funcs_atomic_set_property(
- 	struct drm_crtc *crtc,
--	struct drm_crtc_state *state,
-+	struct drm_crtc_state *crtc_state,
- 	struct drm_property *property,
- 	uint64_t val)
- {
--	struct drm_crtc_state *new_crtc_state;
--	struct drm_crtc *new_crtc;
--	int i;
--
--	for_each_crtc_in_state(state->state, new_crtc, new_crtc_state, i) {
--		if (new_crtc == crtc) {
--			struct drm_plane_state *plane_state;
-+	struct drm_plane_state *plane_state;
- 
--			new_crtc_state->planes_changed = true;
-+	crtc_state->planes_changed = true;
- 
--			/*
--			 * Bit of magic done here. We need to ensure
--			 * that planes get update after mode is set.
--			 * So, we need to add primary plane to state,
--			 * and this way atomic_update would be called
--			 * for it
--			 */
--			plane_state =
--				drm_atomic_get_plane_state(
--					state->state,
--					crtc->primary);
-+	/*
-+	 * Bit of magic done here. We need to ensure
-+	 * that planes get update after mode is set.
-+	 * So, we need to add primary plane to state,
-+	 * and this way atomic_update would be called
-+	 * for it
-+	 */
-+	plane_state =
-+		drm_atomic_get_plane_state(
-+			crtc_state->state,
-+			crtc->primary);
- 
--			if (!plane_state)
--				return -EINVAL;
--		}
--	}
-+	if (!plane_state)
-+		return -EINVAL;
- 
- 	return 0;
- }
-@@ -1007,7 +999,7 @@ amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
- 
- int amdgpu_dm_connector_atomic_set_property(
- 	struct drm_connector *connector,
--	struct drm_connector_state *state,
-+	struct drm_connector_state *connector_state,
- 	struct drm_property *property,
- 	uint64_t val)
- {
-@@ -1016,7 +1008,7 @@ int amdgpu_dm_connector_atomic_set_property(
- 	struct dm_connector_state *dm_old_state =
- 		to_dm_connector_state(connector->state);
- 	struct dm_connector_state *dm_new_state =
--		to_dm_connector_state(state);
-+		to_dm_connector_state(connector_state);
- 
- 	if (property == dev->mode_config.scaling_mode_property) {
- 		struct drm_crtc_state *new_crtc_state;
-@@ -1045,8 +1037,13 @@ int amdgpu_dm_connector_atomic_set_property(
- 
- 		dm_new_state->scaling = rmx_type;
- 
--		for_each_crtc_in_state(state->state, crtc, new_crtc_state, i) {
--			if (crtc == state->crtc) {
-+		for_each_crtc_in_state(
-+			connector_state->state,
-+			crtc,
-+			new_crtc_state,
-+			i) {
-+
-+			if (crtc == connector_state->crtc) {
- 				struct drm_plane_state *plane_state;
- 
- 				new_crtc_state->mode_changed = true;
-@@ -1060,7 +1057,7 @@ int amdgpu_dm_connector_atomic_set_property(
- 				 */
- 				plane_state =
- 					drm_atomic_get_plane_state(
--						state->state,
-+						connector_state->state,
- 						crtc->primary);
- 
- 				if (!plane_state)
-@@ -1081,8 +1078,14 @@ int amdgpu_dm_connector_atomic_set_property(
- 		int i;
- 
- 		dm_new_state->underscan_enable = val;
--		for_each_crtc_in_state(state->state, crtc, new_crtc_state, i) {
--			if (crtc == state->crtc) {
-+
-+		for_each_crtc_in_state(
-+			connector_state->state,
-+			crtc,
-+			new_crtc_state,
-+			i) {
-+
-+			if (crtc == connector_state->crtc) {
- 				struct drm_plane_state *plane_state;
- 
- 				/*
-@@ -1094,7 +1097,7 @@ int amdgpu_dm_connector_atomic_set_property(
- 				 */
- 				plane_state =
- 					drm_atomic_get_plane_state(
--						state->state,
-+						connector_state->state,
- 						crtc->primary);
- 
- 				if (!plane_state)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0546-drm-amd-dal-temporary-fix-in-headless-processing-cod.patch b/common/recipes-kernel/linux/files/0546-drm-amd-dal-temporary-fix-in-headless-processing-cod.patch
deleted file mode 100644
index 165e360c..00000000
--- a/common/recipes-kernel/linux/files/0546-drm-amd-dal-temporary-fix-in-headless-processing-cod.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From c389a8716f3b798cf1b1cb274846bc9966fe1b70 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 1 Dec 2015 19:31:57 +0800
-Subject: [PATCH 0546/1110] drm/amd/dal: temporary fix in headless processing
- code for MST
-
-We cannot rely in function aconnector_from_drm_crtc_id for crtc_id to
-be equal to connector_id. It is not the case anymore. Because of that
-there was a segfault:
-
-1. Pageflip atomic commit;
-2. No connector provided in state, so aconnector is NULL;
-3. Incorrect physical MST connector selected in handle_headless_hotplug,
-and set mode is scheduled for it;
-4. Segfault because there is no modes exist on this connector.
-
-We need to revisit handle_headless_hotplug logic, and retest them.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 90bb0d2..7990a48 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -556,8 +556,7 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id(
- 
- 		aconnector = to_amdgpu_connector(connector);
- 
--		/* acrtc->crtc_id means display_index */
--		if (aconnector->connector_id != acrtc->crtc_id)
-+		if (aconnector->base.state->crtc != &acrtc->base)
- 			continue;
- 
- 		/* Found the connector */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0547-drm-amd-dal-fix-bug-in-edid_read.patch b/common/recipes-kernel/linux/files/0547-drm-amd-dal-fix-bug-in-edid_read.patch
deleted file mode 100644
index 425098eb..00000000
--- a/common/recipes-kernel/linux/files/0547-drm-amd-dal-fix-bug-in-edid_read.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 8893b256a1de567711249ec1a11d32776e7cefd0 Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Tue, 1 Dec 2015 10:34:54 -0500
-Subject: [PATCH 0547/1110] drm/amd/dal: fix bug in edid_read
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index ba087b3..bffd561 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -385,7 +385,7 @@ static enum dc_edid_status read_edid(
- 		dal_ddc_service_get_edid_buf(link->ddc,
- 				sink->public.dc_edid.raw_edid);
- 		edid_status = dc_helpers_parse_edid_caps(
--				NULL,
-+				sink->ctx,
- 				&sink->public.dc_edid,
- 				&sink->public.edid_caps);
- 		--edid_retry;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0548-drm-amd-dal-Refactor-DCE11-to-split-HW-agnostic-code.patch b/common/recipes-kernel/linux/files/0548-drm-amd-dal-Refactor-DCE11-to-split-HW-agnostic-code.patch
deleted file mode 100644
index aaf365f1..00000000
--- a/common/recipes-kernel/linux/files/0548-drm-amd-dal-Refactor-DCE11-to-split-HW-agnostic-code.patch
+++ /dev/null
@@ -1,1566 +0,0 @@
-From 6463e29e299eb8d0b8657af6d8487fe3829691fe Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Tue, 1 Dec 2015 10:04:47 -0500
-Subject: [PATCH 0548/1110] drm/amd/dal: Refactor DCE11 to split HW agnostic
- code into separate /dce folder.
-
-[Use Case] To support new ASIC enablement on DAL3, we want to minimize code duplication to speed up the effort. Inside dce110_resource about half the code is not dce110 specific. For example, building avi_info_frame is the same for all DCEs, as is mapping most resources with the exception of clock source (e.g. we always assign first free controller, audio, etc.).
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 722 ++-------------------
- drivers/gpu/drm/amd/dal/dc/dce_base/Makefile       |  23 +
- .../drm/amd/dal/dc/dce_base/dce_base_resource.c    | 667 +++++++++++++++++++
- .../drm/amd/dal/dc/dce_base/dce_base_resource.h    |  37 ++
- 5 files changed, 793 insertions(+), 658 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce_base/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index 6926356..285e30d 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -3,7 +3,7 @@
- #
- 
- DC_LIBS = adapter asic_capability audio basics bios calcs connector \
--dcs gpio gpu i2caux irq
-+dcs gpio gpu i2caux irq dce_base
- 
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- DC_LIBS += dce110
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 37ffc0e..7e69dd5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -24,8 +24,13 @@
-  */
- #include "dc_services.h"
- 
-+#include "link_encoder_types.h"
-+#include "stream_encoder_types.h"
-+
- #include "resource.h"
-+#include "dce_base/dce_base_resource.h"
- #include "include/irq_service_interface.h"
-+
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_mem_input.h"
-@@ -33,8 +38,6 @@
- #include "dce110/dce110_transform.h"
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
--#include "link_encoder_types.h"
--#include "stream_encoder_types.h"
- 
- enum dce110_clk_src_array_id {
- 	DCE110_CLK_SRC_PLL0 = 0,
-@@ -47,437 +50,6 @@ enum dce110_clk_src_array_id {
- #define DCE110_MAX_DISPCLK 643000
- #define DCE110_MAX_SCLK 626000
- 
--static void set_vendor_info_packet(struct core_stream *stream,
--		struct hw_info_packet *info_packet)
--{
--	uint32_t length = 0;
--	bool hdmi_vic_mode = false;
--	uint8_t checksum = 0;
--	uint32_t i = 0;
--	enum dc_timing_3d_format format;
--
--	ASSERT_CRITICAL(stream != NULL);
--	ASSERT_CRITICAL(info_packet != NULL);
--
--	format = stream->public.timing.timing_3d_format;
--
--	/* Can be different depending on packet content */
--	length = 5;
--
--	if (stream->public.timing.hdmi_vic != 0
--			&& stream->public.timing.h_total >= 3840
--			&& stream->public.timing.v_total >= 2160)
--		hdmi_vic_mode = true;
--
--	/* According to HDMI 1.4a CTS, VSIF should be sent
--	 * for both 3D stereo and HDMI VIC modes.
--	 * For all other modes, there is no VSIF sent.  */
--
--	if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
--		return;
--
--	/* 24bit IEEE Registration identifier (0x000c03). LSB first. */
--	info_packet->sb[1] = 0x03;
--	info_packet->sb[2] = 0x0C;
--	info_packet->sb[3] = 0x00;
--
--	/*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
--	 * The value for HDMI_Video_Format are:
--	 * 0x0 (0b000) - No additional HDMI video format is presented in this
--	 * packet
--	 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
--	 * parameter follows
--	 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
--	 * potentially 3D_Ext_Data follows
--	 * 0x3..0x7 (0b011..0b111) - reserved for future use */
--	if (format != TIMING_3D_FORMAT_NONE)
--		info_packet->sb[4] = (2 << 5);
--	else if (hdmi_vic_mode)
--		info_packet->sb[4] = (1 << 5);
--
--	/* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
--	 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
--	 * The value for 3D_Structure are:
--	 * 0x0 - Frame Packing
--	 * 0x1 - Field Alternative
--	 * 0x2 - Line Alternative
--	 * 0x3 - Side-by-Side (full)
--	 * 0x4 - L + depth
--	 * 0x5 - L + depth + graphics + graphics-depth
--	 * 0x6 - Top-and-Bottom
--	 * 0x7 - Reserved for future use
--	 * 0x8 - Side-by-Side (Half)
--	 * 0x9..0xE - Reserved for future use
--	 * 0xF - Not used */
--	switch (format) {
--	case TIMING_3D_FORMAT_HW_FRAME_PACKING:
--	case TIMING_3D_FORMAT_SW_FRAME_PACKING:
--		info_packet->sb[5] = (0x0 << 4);
--		break;
--
--	case TIMING_3D_FORMAT_SIDE_BY_SIDE:
--	case TIMING_3D_FORMAT_SBS_SW_PACKED:
--		info_packet->sb[5] = (0x8 << 4);
--		length = 6;
--		break;
--
--	case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
--	case TIMING_3D_FORMAT_TB_SW_PACKED:
--		info_packet->sb[5] = (0x6 << 4);
--		break;
--
--	default:
--		break;
--	}
--
--	/*PB5: If PB4 is set to 0x1 (extended resolution format)
--	 * fill PB5 with the correct HDMI VIC code */
--	if (hdmi_vic_mode)
--		info_packet->sb[5] = stream->public.timing.hdmi_vic;
--
--	/* Header */
--	info_packet->hb0 = 0x81; /* VSIF packet type. */
--	info_packet->hb1 = 0x01; /* Version */
--
--	/* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
--	info_packet->hb2 = (uint8_t) (length);
--
--	/* Calculate checksum */
--	checksum = 0;
--	checksum += info_packet->hb0;
--	checksum += info_packet->hb1;
--	checksum += info_packet->hb2;
--
--	for (i = 1; i <= length; i++)
--		checksum += info_packet->sb[i];
--
--	info_packet->sb[0] = (uint8_t) (0x100 - checksum);
--
--	info_packet->valid = true;
--}
--
--static enum ds_color_space build_default_color_space(
--		struct core_stream *stream)
--{
--	enum ds_color_space color_space =
--			DS_COLOR_SPACE_SRGB_FULLRANGE;
--	struct dc_crtc_timing *timing = &stream->public.timing;
--
--	switch (stream->signal) {
--	/* TODO: implement other signal color space setting */
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		break;
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--	{
--		uint32_t pix_clk_khz;
--
--		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 &&
--			timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
--			if (timing->timing_standard ==
--					TIMING_STANDARD_CEA770 &&
--				timing->timing_standard ==
--						TIMING_STANDARD_CEA861)
--				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
--
--			pix_clk_khz = timing->pix_clk_khz / 10;
--			if (timing->h_addressable == 640 &&
--				timing->v_addressable == 480 &&
--				(pix_clk_khz == 2520 || pix_clk_khz == 2517))
--				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
--		} else {
--			if (timing->timing_standard ==
--					TIMING_STANDARD_CEA770 ||
--					timing->timing_standard ==
--					TIMING_STANDARD_CEA861) {
--
--				color_space =
--					(timing->pix_clk_khz > PIXEL_CLOCK) ?
--						DS_COLOR_SPACE_YCBCR709 :
--						DS_COLOR_SPACE_YCBCR601;
--			}
--		}
--		break;
--	}
--	default:
--		switch (timing->pixel_encoding) {
--		case PIXEL_ENCODING_YCBCR422:
--		case PIXEL_ENCODING_YCBCR444:
--			if (timing->pix_clk_khz > PIXEL_CLOCK)
--				color_space = DS_COLOR_SPACE_YCBCR709;
--			else
--				color_space = DS_COLOR_SPACE_YCBCR601;
--			break;
--		default:
--			break;
--		}
--		break;
--	}
--	return color_space;
--}
--
--static void set_avi_info_frame(struct hw_info_packet *info_packet,
--		struct core_stream *stream)
--{
--	enum ds_color_space color_space = DS_COLOR_SPACE_UNKNOWN;
--	struct info_frame info_frame = { {0} };
--	uint32_t pixel_encoding = 0;
--	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
--	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
--	bool itc = false;
--	uint8_t cn0_cn1 = 0;
--	uint8_t *check_sum = NULL;
--	uint8_t byte_index = 0;
--
--	if (info_packet == NULL)
--		return;
--
--	color_space = build_default_color_space(stream);
--
--	/* Initialize header */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
--			info_frame_type = INFO_FRAME_AVI;
--	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
--	* not be used in HDMI 2.0 (Section 10.1) */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.header.version =
--			INFO_FRAME_VERSION_2;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
--			INFO_FRAME_SIZE_AVI;
--
--	/* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
--	* according to HDMI 2.0 spec (Section 10.1)
--	* Add "case PixelEncoding_YCbCr420:    pixelEncoding = 3; break;"
--	* when YCbCr 4:2:0 is supported by DAL hardware. */
--
--	switch (stream->public.timing.pixel_encoding) {
--	case PIXEL_ENCODING_YCBCR422:
--		pixel_encoding = 1;
--		break;
--
--	case PIXEL_ENCODING_YCBCR444:
--		pixel_encoding = 2;
--		break;
--
--	case PIXEL_ENCODING_RGB:
--	default:
--		pixel_encoding = 0;
--	}
--
--	/* Y0_Y1_Y2 : The pixel encoding */
--	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
--		pixel_encoding;
--
--
--	/* A0 = 1 Active Format Information valid */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
--		ACTIVE_FORMAT_VALID;
--
--	/* B0, B1 = 3; Bar info data is valid */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
--		BAR_INFO_BOTH_VALID;
--
--	info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
--			PICTURE_SCALING_UNIFORM;
--
--	/* S0, S1 : Underscan / Overscan */
--	/* TODO: un-hardcode scan type */
--	scan_type = SCANNING_TYPE_UNDERSCAN;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
--
--	/* C0, C1 : Colorimetry */
--	if (color_space == DS_COLOR_SPACE_YCBCR709)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
--				COLORIMETRY_ITU709;
--	else if (color_space == DS_COLOR_SPACE_YCBCR601)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
--				COLORIMETRY_ITU601;
--	else
--		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
--				COLORIMETRY_NO_DATA;
--
--
--	/* TODO: un-hardcode aspect ratio */
--	aspect = stream->public.timing.aspect_ratio;
--
--	switch (aspect) {
--	case ASPECT_RATIO_4_3:
--	case ASPECT_RATIO_16_9:
--		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
--		break;
--
--	case ASPECT_RATIO_NO_DATA:
--	case ASPECT_RATIO_64_27:
--	case ASPECT_RATIO_256_135:
--	default:
--		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
--	}
--
--	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
--			ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
--
--	/* TODO: un-hardcode cn0_cn1 and itc */
--	cn0_cn1 = 0;
--	itc = false;
--
--	if (itc) {
--		info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
--		info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
--			cn0_cn1;
--	}
--
--	/* TODO: un-hardcode q0_q1 */
--	if (color_space == DS_COLOR_SPACE_SRGB_FULLRANGE)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
--						RGB_QUANTIZATION_FULL_RANGE;
--	else if (color_space == DS_COLOR_SPACE_SRGB_LIMITEDRANGE)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
--						RGB_QUANTIZATION_LIMITED_RANGE;
--	else
--		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
--						RGB_QUANTIZATION_DEFAULT_RANGE;
--
--	/* TODO : We should handle YCC quantization,
--	 * but we do not have matrix calculation */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
--					YYC_QUANTIZATION_LIMITED_RANGE;
--
--	info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
--					stream->public.timing.vic;
--
--	/* pixel repetition
--	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
--	 * repetition start from 1 */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
--
--	/* Bar Info
--	 * barTop:    Line Number of End of Top Bar.
--	 * barBottom: Line Number of Start of Bottom Bar.
--	 * barLeft:   Pixel Number of End of Left Bar.
--	 * barRight:  Pixel Number of Start of Right Bar. */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
--			stream->public.timing.v_border_top;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
--		(stream->public.timing.v_border_top
--			- stream->public.timing.v_border_bottom + 1);
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
--			stream->public.timing.h_border_left;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
--		(stream->public.timing.h_total
--			- stream->public.timing.h_border_right + 1);
--
--	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
--	check_sum =
--		&info_frame.
--		avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
--	*check_sum = INFO_FRAME_AVI + INFO_FRAME_SIZE_AVI
--			+ INFO_FRAME_VERSION_2;
--
--	for (byte_index = 1; byte_index <= INFO_FRAME_SIZE_AVI; byte_index++)
--		*check_sum += info_frame.avi_info_packet.info_packet_hdmi.
--				packet_raw_data.sb[byte_index];
--
--	/* one byte complement */
--	*check_sum = (uint8_t) (0x100 - *check_sum);
--
--	/* Store in hw_path_mode */
--	info_packet->hb0 =
--		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
--	info_packet->hb1 =
--		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
--	info_packet->hb2 =
--		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
--
--	for (byte_index = 0; byte_index < sizeof(info_packet->sb); byte_index++)
--		info_packet->sb[byte_index] = info_frame.avi_info_packet.
--		info_packet_hdmi.packet_raw_data.sb[byte_index];
--
--	info_packet->valid = true;
--}
--
--static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
--	struct encoder_info_frame *encoder_info_frame)
--{
--	dc_service_memset(
--		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
--
--	/* For gamut we recalc checksum */
--	if (hw_info_frame->gamut_packet.valid) {
--		uint8_t chk_sum = 0;
--		uint8_t *ptr;
--		uint8_t i;
--
--		dc_service_memmove(
--						&encoder_info_frame->gamut,
--						&hw_info_frame->gamut_packet,
--						sizeof(struct hw_info_packet));
--
--		/*start of the Gamut data. */
--		ptr = &encoder_info_frame->gamut.sb[3];
--
--		for (i = 0; i <= encoder_info_frame->gamut.sb[1]; i++)
--			chk_sum += ptr[i];
--
--		encoder_info_frame->gamut.sb[2] = (uint8_t) (0x100 - chk_sum);
--	}
--
--	if (hw_info_frame->avi_info_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->avi,
--						&hw_info_frame->avi_info_packet,
--						sizeof(struct hw_info_packet));
--	}
--
--	if (hw_info_frame->vendor_info_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->vendor,
--						&hw_info_frame->vendor_info_packet,
--						sizeof(struct hw_info_packet));
--	}
--
--	if (hw_info_frame->spd_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->spd,
--						&hw_info_frame->spd_packet,
--						sizeof(struct hw_info_packet));
--	}
--
--	if (hw_info_frame->vsc_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->vsc,
--						&hw_info_frame->vsc_packet,
--						sizeof(struct hw_info_packet));
--	}
--}
--
--static void build_info_frame(struct core_stream *stream)
--{
--	enum signal_type signal = SIGNAL_TYPE_NONE;
--	struct hw_info_frame info_frame = { { 0 } };
--
--	/* default all packets to invalid */
--	info_frame.avi_info_packet.valid = false;
--	info_frame.gamut_packet.valid = false;
--	info_frame.vendor_info_packet.valid = false;
--	info_frame.spd_packet.valid = false;
--	info_frame.vsc_packet.valid = false;
--
--	signal = stream->sink->public.sink_signal;
--
--	/* HDMi and DP have different info packets*/
--	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
--		set_avi_info_frame(&info_frame.avi_info_packet,
--				stream);
--		set_vendor_info_packet(stream, &info_frame.vendor_info_packet);
--	}
--
--	translate_info_frame(&info_frame,
--			&stream->encoder_info_frame);
--}
--
--
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -744,99 +316,6 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 	}
- }
- 
--static void attach_stream_to_controller(
--		struct resource_context *res_ctx,
--		struct core_stream *stream)
--{
--	res_ctx->controller_ctx[stream->controller_idx].stream = stream;
--}
--
--static bool assign_first_free_controller(
--		struct resource_context *res_ctx,
--		struct core_stream *stream)
--{
--	uint8_t i;
--	for (i = 0; i < res_ctx->pool.controller_count; i++) {
--		if (!res_ctx->controller_ctx[i].stream) {
--			stream->tg = res_ctx->pool.timing_generators[i];
--			stream->mi = res_ctx->pool.mis[i];
--			stream->ipp = res_ctx->pool.ipps[i];
--			stream->xfm = res_ctx->pool.transforms[i];
--			stream->opp = res_ctx->pool.opps[i];
--			stream->controller_idx = i;
--			stream->dis_clk = res_ctx->pool.display_clock;
--			return true;
--		}
--	}
--	return false;
--}
--
--static void set_stream_engine_in_use(
--		struct resource_context *res_ctx,
--		struct stream_encoder *stream_enc)
--{
--	int i;
--
--	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
--		if (res_ctx->pool.stream_enc[i] == stream_enc)
--			res_ctx->is_stream_enc_acquired[i] = true;
--	}
--}
--
--static struct stream_encoder *find_first_free_match_stream_enc_for_link(
--		struct resource_context *res_ctx,
--		struct core_link *link)
--{
--	uint8_t i;
--	int8_t j = -1;
--
--	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
--		if (!res_ctx->is_stream_enc_acquired[i] &&
--					res_ctx->pool.stream_enc[i]) {
--			/* Store first available for MST second display
--			 * in daisy chain use case */
--			j = i;
--			if (res_ctx->pool.stream_enc[i]->id ==
--					link->link_enc->preferred_engine)
--				return res_ctx->pool.stream_enc[i];
--		}
--	}
--
--	/* TODO: Handle MST properly
--	 * Currently pick next available stream encoder if found*/
--	if (j >= 0 && link->public.sink[0]->sink_signal ==
--			SIGNAL_TYPE_DISPLAY_PORT_MST)
--		return res_ctx->pool.stream_enc[j];
--
--	return NULL;
--}
--
--/* TODO: release audio object */
--static void set_audio_in_use(
--		struct resource_context *res_ctx,
--		struct audio *audio)
--{
--	int i;
--	for (i = 0; i < res_ctx->pool.audio_count; i++) {
--		if (res_ctx->pool.audios[i] == audio) {
--			res_ctx->is_audio_acquired[i] = true;
--		}
--	}
--}
--
--static struct audio *find_first_free_audio(struct resource_context *res_ctx)
--{
--	int i;
--	for (i = 0; i < res_ctx->pool.audio_count; i++) {
--		if (res_ctx->is_audio_acquired[i] == false) {
--			return res_ctx->pool.audios[i];
--		}
--	}
--
--	return 0;
--}
--
--
- static struct clock_source *find_first_free_pll(
- 		struct resource_context *res_ctx)
- {
-@@ -850,135 +329,6 @@ static struct clock_source *find_first_free_pll(
- 	return 0;
- }
- 
--static bool check_timing_change(struct core_stream *cur_stream,
--		struct core_stream *new_stream)
--{
--	if (cur_stream == NULL)
--		return true;
--
--	/* If sink pointer changed, it means this is a hotplug, we should do
--	 * full hw setting.
--	 */
--	if (cur_stream->sink != new_stream->sink)
--		return true;
--
--	return !is_same_timing(
--					&cur_stream->public.timing,
--					&new_stream->public.timing);
--}
--
--static enum dc_status map_resources(
--		const struct dc *dc,
--		struct validate_context *context)
--{
--	uint8_t i, j;
--
--	/* mark resources used for targets that are already active */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (!context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			attach_stream_to_controller(
--				&context->res_ctx,
--				stream);
--
--			set_stream_engine_in_use(
--				&context->res_ctx,
--				stream->stream_enc);
--
--			reference_clock_source(
--				&context->res_ctx,
--				stream->clock_source);
--
--			if (stream->audio) {
--				set_audio_in_use(&context->res_ctx,
--					stream->audio);
--			}
--		}
--	}
--
--	/* acquire new resources */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct core_stream *curr_stream;
--
--			if (!assign_first_free_controller(
--					&context->res_ctx, stream))
--				return DC_NO_CONTROLLER_RESOURCE;
--
--			attach_stream_to_controller(&context->res_ctx, stream);
--
--			stream->stream_enc =
--				find_first_free_match_stream_enc_for_link(
--					&context->res_ctx,
--					stream->sink->link);
--
--			if (!stream->stream_enc)
--				return DC_NO_STREAM_ENG_RESOURCE;
--
--			set_stream_engine_in_use(
--					&context->res_ctx,
--					stream->stream_enc);
--			stream->signal =
--				stream->sink->public.sink_signal;
--
--			if (dc_is_dp_signal(stream->signal))
--				stream->clock_source = context->res_ctx.
--					pool.clock_sources[DCE110_CLK_SRC_EXT];
--			else
--				stream->clock_source =
--					find_used_clk_src_for_sharing(
--							context, stream);
--			if (stream->clock_source == NULL)
--				stream->clock_source =
--					find_first_free_pll(&context->res_ctx);
--
--			if (stream->clock_source == NULL)
--				return DC_NO_CLOCK_SOURCE_RESOURCE;
--
--			reference_clock_source(
--					&context->res_ctx,
--					stream->clock_source);
--
--			/* TODO: Add check if ASIC support and EDID audio */
--			if (!stream->sink->converter_disable_audio &&
--						dc_is_audio_capable_signal(
--						stream->signal)) {
--				stream->audio = find_first_free_audio(
--						&context->res_ctx);
--
--				if (!stream->audio)
--					return DC_NO_STREAM_AUDIO_RESOURCE;
--
--				set_audio_in_use(&context->res_ctx,
--						stream->audio);
--			}
--			curr_stream =
--				dc->current_context.res_ctx.controller_ctx
--				[stream->controller_idx].stream;
--			context->res_ctx.controller_ctx[stream->controller_idx]
--			.flags.timing_changed =
--				check_timing_change(curr_stream, stream);
--
--		}
--	}
--
--	return DC_OK;
--}
--
- static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
- {
- 	switch (crtc_id) {
-@@ -1143,7 +493,7 @@ static enum dc_status validate_mapped_resource(
- 			if (status != DC_OK)
- 				return status;
- 
--			build_info_frame(stream);
-+			dce_base_build_info_frame(stream);
- 		}
- 	}
- 
-@@ -1260,6 +610,63 @@ static void set_target_unchanged(
- 	}
- }
- 
-+static enum dc_status map_clock_resources(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j;
-+
-+	/* mark resources used for targets that are already active */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (!context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			reference_clock_source(
-+				&context->res_ctx,
-+				stream->clock_source);
-+		}
-+	}
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			if (dc_is_dp_signal(stream->signal))
-+				stream->clock_source = context->res_ctx.
-+					pool.clock_sources[DCE110_CLK_SRC_EXT];
-+			else
-+				stream->clock_source =
-+					find_used_clk_src_for_sharing(
-+							context, stream);
-+			if (stream->clock_source == NULL)
-+				stream->clock_source =
-+					find_first_free_pll(&context->res_ctx);
-+
-+			if (stream->clock_source == NULL)
-+				return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+			reference_clock_source(
-+					&context->res_ctx,
-+					stream->clock_source);
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
- enum dc_status dce110_validate_with_context(
- 		const struct dc *dc,
- 		const struct dc_validation_set set[],
-@@ -1291,7 +698,8 @@ enum dc_status dce110_validate_with_context(
- 
- 	context->res_ctx.pool = dc->res_pool;
- 
--	result = map_resources(dc, context);
-+	result = dce_base_map_resources(dc, context);
-+	result = map_clock_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = validate_mapped_resource(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/Makefile b/drivers/gpu/drm/amd/dal/dc/dce_base/Makefile
-new file mode 100644
-index 0000000..4f239f5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/Makefile
-@@ -0,0 +1,23 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE_BASE = dce_base_resource.o
-+
-+AMD_DAL_DCE_BASE = $(addprefix $(AMDDALPATH)/dc/dce_base/,$(DCE_BASE))
-+
-+AMD_DAL_FILES += $(AMD_DAL_DCE_BASE)
-+
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
-+TG_DCE_BASE = dce_base_resource.o
-+
-+AMD_DAL_TG_DCE110 = $(addprefix \
-+	$(AMDDALPATH)/dc/dce_base/,$(TG_DCE_BASE))
-+
-+AMD_DAL_FILES += $(AMD_DAL_TG_DCE_BASE)
-+endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-new file mode 100644
-index 0000000..06047ab
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -0,0 +1,667 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dce_base_resource.h"
-+
-+#include "dc_services.h"
-+
-+#include "adjustment_types.h"
-+#include "set_mode_types.h"
-+#include "stream_encoder_types.h"
-+#include "link_encoder_types.h"
-+
-+#include "resource.h"
-+
-+static void attach_stream_to_controller(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	res_ctx->controller_ctx[stream->controller_idx].stream = stream;
-+}
-+
-+static void set_stream_engine_in_use(
-+		struct resource_context *res_ctx,
-+		struct stream_encoder *stream_enc)
-+{
-+	int i;
-+
-+	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
-+		if (res_ctx->pool.stream_enc[i] == stream_enc)
-+			res_ctx->is_stream_enc_acquired[i] = true;
-+	}
-+}
-+
-+/* TODO: release audio object */
-+static void set_audio_in_use(
-+		struct resource_context *res_ctx,
-+		struct audio *audio)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.audio_count; i++) {
-+		if (res_ctx->pool.audios[i] == audio) {
-+			res_ctx->is_audio_acquired[i] = true;
-+		}
-+	}
-+}
-+
-+static bool assign_first_free_controller(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	uint8_t i;
-+	for (i = 0; i < res_ctx->pool.controller_count; i++) {
-+		if (!res_ctx->controller_ctx[i].stream) {
-+			stream->tg = res_ctx->pool.timing_generators[i];
-+			stream->mi = res_ctx->pool.mis[i];
-+			stream->ipp = res_ctx->pool.ipps[i];
-+			stream->xfm = res_ctx->pool.transforms[i];
-+			stream->opp = res_ctx->pool.opps[i];
-+			stream->controller_idx = i;
-+			stream->dis_clk = res_ctx->pool.display_clock;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+static struct stream_encoder *find_first_free_match_stream_enc_for_link(
-+		struct resource_context *res_ctx,
-+		struct core_link *link)
-+{
-+	uint8_t i;
-+	int8_t j = -1;
-+
-+	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
-+		if (!res_ctx->is_stream_enc_acquired[i] &&
-+					res_ctx->pool.stream_enc[i]) {
-+			/* Store first available for MST second display
-+			 * in daisy chain use case */
-+			j = i;
-+			if (res_ctx->pool.stream_enc[i]->id ==
-+					link->link_enc->preferred_engine)
-+				return res_ctx->pool.stream_enc[i];
-+		}
-+	}
-+
-+	/* TODO: Handle MST properly
-+	 * Currently pick next available stream encoder if found*/
-+	if (j >= 0 && link->public.sink[0]->sink_signal ==
-+			SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		return res_ctx->pool.stream_enc[j];
-+
-+	return NULL;
-+}
-+
-+static struct audio *find_first_free_audio(struct resource_context *res_ctx)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.audio_count; i++) {
-+		if (res_ctx->is_audio_acquired[i] == false) {
-+			return res_ctx->pool.audios[i];
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static bool check_timing_change(struct core_stream *cur_stream,
-+		struct core_stream *new_stream)
-+{
-+	if (cur_stream == NULL)
-+		return true;
-+
-+	/* If sink pointer changed, it means this is a hotplug, we should do
-+	 * full hw setting.
-+	 */
-+	if (cur_stream->sink != new_stream->sink)
-+		return true;
-+
-+	return !is_same_timing(
-+					&cur_stream->public.timing,
-+					&new_stream->public.timing);
-+}
-+
-+enum dc_status dce_base_map_resources(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j;
-+
-+	/* mark resources used for targets that are already active */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (!context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			attach_stream_to_controller(
-+				&context->res_ctx,
-+				stream);
-+
-+			set_stream_engine_in_use(
-+				&context->res_ctx,
-+				stream->stream_enc);
-+
-+			reference_clock_source(
-+				&context->res_ctx,
-+				stream->clock_source);
-+
-+			if (stream->audio) {
-+				set_audio_in_use(&context->res_ctx,
-+					stream->audio);
-+			}
-+		}
-+	}
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct core_stream *curr_stream;
-+
-+			if (!assign_first_free_controller(
-+					&context->res_ctx, stream))
-+				return DC_NO_CONTROLLER_RESOURCE;
-+
-+			attach_stream_to_controller(&context->res_ctx, stream);
-+
-+			stream->stream_enc =
-+				find_first_free_match_stream_enc_for_link(
-+					&context->res_ctx,
-+					stream->sink->link);
-+
-+			if (!stream->stream_enc)
-+				return DC_NO_STREAM_ENG_RESOURCE;
-+
-+			set_stream_engine_in_use(
-+					&context->res_ctx,
-+					stream->stream_enc);
-+			stream->signal =
-+				stream->sink->public.sink_signal;
-+
-+			/* TODO: Add check if ASIC support and EDID audio */
-+			if (!stream->sink->converter_disable_audio &&
-+						dc_is_audio_capable_signal(
-+						stream->signal)) {
-+				stream->audio = find_first_free_audio(
-+						&context->res_ctx);
-+
-+				if (!stream->audio)
-+					return DC_NO_STREAM_AUDIO_RESOURCE;
-+
-+				set_audio_in_use(&context->res_ctx,
-+						stream->audio);
-+			}
-+			curr_stream =
-+				dc->current_context.res_ctx.controller_ctx
-+				[stream->controller_idx].stream;
-+			context->res_ctx.controller_ctx[stream->controller_idx]
-+			.flags.timing_changed =
-+				check_timing_change(curr_stream, stream);
-+
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+static enum ds_color_space build_default_color_space(
-+		struct core_stream *stream)
-+{
-+	enum ds_color_space color_space =
-+			DS_COLOR_SPACE_SRGB_FULLRANGE;
-+	struct dc_crtc_timing *timing = &stream->public.timing;
-+
-+	switch (stream->signal) {
-+	/* TODO: implement other signal color space setting */
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	{
-+		uint32_t pix_clk_khz;
-+
-+		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 &&
-+			timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
-+			if (timing->timing_standard ==
-+					TIMING_STANDARD_CEA770 &&
-+				timing->timing_standard ==
-+						TIMING_STANDARD_CEA861)
-+				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
-+
-+			pix_clk_khz = timing->pix_clk_khz / 10;
-+			if (timing->h_addressable == 640 &&
-+				timing->v_addressable == 480 &&
-+				(pix_clk_khz == 2520 || pix_clk_khz == 2517))
-+				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
-+		} else {
-+			if (timing->timing_standard ==
-+					TIMING_STANDARD_CEA770 ||
-+					timing->timing_standard ==
-+					TIMING_STANDARD_CEA861) {
-+
-+				color_space =
-+					(timing->pix_clk_khz > PIXEL_CLOCK) ?
-+						DS_COLOR_SPACE_YCBCR709 :
-+						DS_COLOR_SPACE_YCBCR601;
-+			}
-+		}
-+		break;
-+	}
-+	default:
-+		switch (timing->pixel_encoding) {
-+		case PIXEL_ENCODING_YCBCR422:
-+		case PIXEL_ENCODING_YCBCR444:
-+			if (timing->pix_clk_khz > PIXEL_CLOCK)
-+				color_space = DS_COLOR_SPACE_YCBCR709;
-+			else
-+				color_space = DS_COLOR_SPACE_YCBCR601;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	}
-+	return color_space;
-+}
-+
-+static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
-+	struct encoder_info_frame *encoder_info_frame)
-+{
-+	dc_service_memset(
-+		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
-+
-+	/* For gamut we recalc checksum */
-+	if (hw_info_frame->gamut_packet.valid) {
-+		uint8_t chk_sum = 0;
-+		uint8_t *ptr;
-+		uint8_t i;
-+
-+		dc_service_memmove(
-+						&encoder_info_frame->gamut,
-+						&hw_info_frame->gamut_packet,
-+						sizeof(struct hw_info_packet));
-+
-+		/*start of the Gamut data. */
-+		ptr = &encoder_info_frame->gamut.sb[3];
-+
-+		for (i = 0; i <= encoder_info_frame->gamut.sb[1]; i++)
-+			chk_sum += ptr[i];
-+
-+		encoder_info_frame->gamut.sb[2] = (uint8_t) (0x100 - chk_sum);
-+	}
-+
-+	if (hw_info_frame->avi_info_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->avi,
-+						&hw_info_frame->avi_info_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->vendor_info_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->vendor,
-+						&hw_info_frame->vendor_info_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->spd_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->spd,
-+						&hw_info_frame->spd_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->vsc_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->vsc,
-+						&hw_info_frame->vsc_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+}
-+
-+static void set_avi_info_frame(struct hw_info_packet *info_packet,
-+		struct core_stream *stream)
-+{
-+	enum ds_color_space color_space = DS_COLOR_SPACE_UNKNOWN;
-+	struct info_frame info_frame = { {0} };
-+	uint32_t pixel_encoding = 0;
-+	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
-+	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
-+	bool itc = false;
-+	uint8_t cn0_cn1 = 0;
-+	uint8_t *check_sum = NULL;
-+	uint8_t byte_index = 0;
-+
-+	if (info_packet == NULL)
-+		return;
-+
-+	color_space = build_default_color_space(stream);
-+
-+	/* Initialize header */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
-+			info_frame_type = INFO_FRAME_AVI;
-+	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
-+	* not be used in HDMI 2.0 (Section 10.1) */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.version =
-+			INFO_FRAME_VERSION_2;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
-+			INFO_FRAME_SIZE_AVI;
-+
-+	/* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
-+	* according to HDMI 2.0 spec (Section 10.1)
-+	* Add "case PixelEncoding_YCbCr420:    pixelEncoding = 3; break;"
-+	* when YCbCr 4:2:0 is supported by DAL hardware. */
-+
-+	switch (stream->public.timing.pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		pixel_encoding = 1;
-+		break;
-+
-+	case PIXEL_ENCODING_YCBCR444:
-+		pixel_encoding = 2;
-+		break;
-+
-+	case PIXEL_ENCODING_RGB:
-+	default:
-+		pixel_encoding = 0;
-+	}
-+
-+	/* Y0_Y1_Y2 : The pixel encoding */
-+	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
-+		pixel_encoding;
-+
-+
-+	/* A0 = 1 Active Format Information valid */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
-+		ACTIVE_FORMAT_VALID;
-+
-+	/* B0, B1 = 3; Bar info data is valid */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
-+		BAR_INFO_BOTH_VALID;
-+
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
-+			PICTURE_SCALING_UNIFORM;
-+
-+	/* S0, S1 : Underscan / Overscan */
-+	/* TODO: un-hardcode scan type */
-+	scan_type = SCANNING_TYPE_UNDERSCAN;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
-+
-+	/* C0, C1 : Colorimetry */
-+	if (color_space == DS_COLOR_SPACE_YCBCR709)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_ITU709;
-+	else if (color_space == DS_COLOR_SPACE_YCBCR601)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_ITU601;
-+	else
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_NO_DATA;
-+
-+
-+	/* TODO: un-hardcode aspect ratio */
-+	aspect = stream->public.timing.aspect_ratio;
-+
-+	switch (aspect) {
-+	case ASPECT_RATIO_4_3:
-+	case ASPECT_RATIO_16_9:
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
-+		break;
-+
-+	case ASPECT_RATIO_NO_DATA:
-+	case ASPECT_RATIO_64_27:
-+	case ASPECT_RATIO_256_135:
-+	default:
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
-+	}
-+
-+	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
-+			ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
-+
-+	/* TODO: un-hardcode cn0_cn1 and itc */
-+	cn0_cn1 = 0;
-+	itc = false;
-+
-+	if (itc) {
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
-+			cn0_cn1;
-+	}
-+
-+	/* TODO: un-hardcode q0_q1 */
-+	if (color_space == DS_COLOR_SPACE_SRGB_FULLRANGE)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_FULL_RANGE;
-+	else if (color_space == DS_COLOR_SPACE_SRGB_LIMITEDRANGE)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_LIMITED_RANGE;
-+	else
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_DEFAULT_RANGE;
-+
-+	/* TODO : We should handle YCC quantization,
-+	 * but we do not have matrix calculation */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
-+					YYC_QUANTIZATION_LIMITED_RANGE;
-+
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
-+					stream->public.timing.vic;
-+
-+	/* pixel repetition
-+	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
-+	 * repetition start from 1 */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
-+
-+	/* Bar Info
-+	 * barTop:    Line Number of End of Top Bar.
-+	 * barBottom: Line Number of Start of Bottom Bar.
-+	 * barLeft:   Pixel Number of End of Left Bar.
-+	 * barRight:  Pixel Number of Start of Right Bar. */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
-+			stream->public.timing.v_border_top;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
-+		(stream->public.timing.v_border_top
-+			- stream->public.timing.v_border_bottom + 1);
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
-+			stream->public.timing.h_border_left;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
-+		(stream->public.timing.h_total
-+			- stream->public.timing.h_border_right + 1);
-+
-+	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
-+	check_sum =
-+		&info_frame.
-+		avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
-+	*check_sum = INFO_FRAME_AVI + INFO_FRAME_SIZE_AVI
-+			+ INFO_FRAME_VERSION_2;
-+
-+	for (byte_index = 1; byte_index <= INFO_FRAME_SIZE_AVI; byte_index++)
-+		*check_sum += info_frame.avi_info_packet.info_packet_hdmi.
-+				packet_raw_data.sb[byte_index];
-+
-+	/* one byte complement */
-+	*check_sum = (uint8_t) (0x100 - *check_sum);
-+
-+	/* Store in hw_path_mode */
-+	info_packet->hb0 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
-+	info_packet->hb1 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
-+	info_packet->hb2 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
-+
-+	for (byte_index = 0; byte_index < sizeof(info_packet->sb); byte_index++)
-+		info_packet->sb[byte_index] = info_frame.avi_info_packet.
-+		info_packet_hdmi.packet_raw_data.sb[byte_index];
-+
-+	info_packet->valid = true;
-+}
-+
-+static void set_vendor_info_packet(struct core_stream *stream,
-+		struct hw_info_packet *info_packet)
-+{
-+	uint32_t length = 0;
-+	bool hdmi_vic_mode = false;
-+	uint8_t checksum = 0;
-+	uint32_t i = 0;
-+	enum dc_timing_3d_format format;
-+
-+	ASSERT_CRITICAL(stream != NULL);
-+	ASSERT_CRITICAL(info_packet != NULL);
-+
-+	format = stream->public.timing.timing_3d_format;
-+
-+	/* Can be different depending on packet content */
-+	length = 5;
-+
-+	if (stream->public.timing.hdmi_vic != 0
-+			&& stream->public.timing.h_total >= 3840
-+			&& stream->public.timing.v_total >= 2160)
-+		hdmi_vic_mode = true;
-+
-+	/* According to HDMI 1.4a CTS, VSIF should be sent
-+	 * for both 3D stereo and HDMI VIC modes.
-+	 * For all other modes, there is no VSIF sent.  */
-+
-+	if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
-+		return;
-+
-+	/* 24bit IEEE Registration identifier (0x000c03). LSB first. */
-+	info_packet->sb[1] = 0x03;
-+	info_packet->sb[2] = 0x0C;
-+	info_packet->sb[3] = 0x00;
-+
-+	/*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
-+	 * The value for HDMI_Video_Format are:
-+	 * 0x0 (0b000) - No additional HDMI video format is presented in this
-+	 * packet
-+	 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
-+	 * parameter follows
-+	 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
-+	 * potentially 3D_Ext_Data follows
-+	 * 0x3..0x7 (0b011..0b111) - reserved for future use */
-+	if (format != TIMING_3D_FORMAT_NONE)
-+		info_packet->sb[4] = (2 << 5);
-+	else if (hdmi_vic_mode)
-+		info_packet->sb[4] = (1 << 5);
-+
-+	/* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
-+	 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
-+	 * The value for 3D_Structure are:
-+	 * 0x0 - Frame Packing
-+	 * 0x1 - Field Alternative
-+	 * 0x2 - Line Alternative
-+	 * 0x3 - Side-by-Side (full)
-+	 * 0x4 - L + depth
-+	 * 0x5 - L + depth + graphics + graphics-depth
-+	 * 0x6 - Top-and-Bottom
-+	 * 0x7 - Reserved for future use
-+	 * 0x8 - Side-by-Side (Half)
-+	 * 0x9..0xE - Reserved for future use
-+	 * 0xF - Not used */
-+	switch (format) {
-+	case TIMING_3D_FORMAT_HW_FRAME_PACKING:
-+	case TIMING_3D_FORMAT_SW_FRAME_PACKING:
-+		info_packet->sb[5] = (0x0 << 4);
-+		break;
-+
-+	case TIMING_3D_FORMAT_SIDE_BY_SIDE:
-+	case TIMING_3D_FORMAT_SBS_SW_PACKED:
-+		info_packet->sb[5] = (0x8 << 4);
-+		length = 6;
-+		break;
-+
-+	case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
-+	case TIMING_3D_FORMAT_TB_SW_PACKED:
-+		info_packet->sb[5] = (0x6 << 4);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	/*PB5: If PB4 is set to 0x1 (extended resolution format)
-+	 * fill PB5 with the correct HDMI VIC code */
-+	if (hdmi_vic_mode)
-+		info_packet->sb[5] = stream->public.timing.hdmi_vic;
-+
-+	/* Header */
-+	info_packet->hb0 = 0x81; /* VSIF packet type. */
-+	info_packet->hb1 = 0x01; /* Version */
-+
-+	/* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
-+	info_packet->hb2 = (uint8_t) (length);
-+
-+	/* Calculate checksum */
-+	checksum = 0;
-+	checksum += info_packet->hb0;
-+	checksum += info_packet->hb1;
-+	checksum += info_packet->hb2;
-+
-+	for (i = 1; i <= length; i++)
-+		checksum += info_packet->sb[i];
-+
-+	info_packet->sb[0] = (uint8_t) (0x100 - checksum);
-+
-+	info_packet->valid = true;
-+}
-+
-+void dce_base_build_info_frame(struct core_stream *stream)
-+{
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+	struct hw_info_frame info_frame = { { 0 } };
-+
-+	/* default all packets to invalid */
-+	info_frame.avi_info_packet.valid = false;
-+	info_frame.gamut_packet.valid = false;
-+	info_frame.vendor_info_packet.valid = false;
-+	info_frame.spd_packet.valid = false;
-+	info_frame.vsc_packet.valid = false;
-+
-+	signal = stream->sink->public.sink_signal;
-+
-+	/* HDMi and DP have different info packets*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		set_avi_info_frame(&info_frame.avi_info_packet,
-+				stream);
-+		set_vendor_info_packet(stream, &info_frame.vendor_info_packet);
-+	}
-+
-+	translate_info_frame(&info_frame,
-+			&stream->encoder_info_frame);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h
-new file mode 100644
-index 0000000..eec06f0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h
-@@ -0,0 +1,37 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DCE_BASE_RESOURCE_H__
-+#define __DCE_BASE_RESOURCE_H__
-+
-+#include "dc_services.h"
-+#include "resource.h"
-+
-+void dce_base_build_info_frame(struct core_stream *stream);
-+
-+enum dc_status dce_base_map_resources(
-+	const struct dc *dc,
-+	struct validate_context *context);
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0549-drm-amd-dal-Register-offset-cleanup-on-Link-and-Stre.patch b/common/recipes-kernel/linux/files/0549-drm-amd-dal-Register-offset-cleanup-on-Link-and-Stre.patch
deleted file mode 100644
index 2a8b9388..00000000
--- a/common/recipes-kernel/linux/files/0549-drm-amd-dal-Register-offset-cleanup-on-Link-and-Stre.patch
+++ /dev/null
@@ -1,3066 +0,0 @@
-From f70c0b0d07c60b286d39ab64adba19df67094f97 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Mon, 30 Nov 2015 17:04:12 -0500
-Subject: [PATCH 0549/1110] drm/amd/dal: Register offset cleanup on Link and
- Stream Encoder
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   4 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |   4 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   8 +
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   2 -
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 801 +++++++++++----------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  35 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  10 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 441 ++++++------
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |  21 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   8 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |  28 +
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h    |  18 +
- drivers/gpu/drm/amd/dal/include/encoder_types.h    |  10 +
- .../gpu/drm/amd/dal/include/link_encoder_types.h   |  32 -
- .../gpu/drm/amd/dal/include/stream_encoder_types.h |  16 -
- 16 files changed, 753 insertions(+), 687 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/link_encoder_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index bffd561..0af5005 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -35,8 +35,8 @@
- #include "core_status.h"
- #include "dc_link_dp.h"
- #include "link_hwss.h"
--#include "stream_encoder_types.h"
--#include "link_encoder_types.h"
-+#include "stream_encoder.h"
-+#include "link_encoder.h"
- #include "hw_sequencer.h"
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index f1f7347..7d90532 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -26,8 +26,8 @@
- 
- #include "resource.h"
- #include "include/irq_service_interface.h"
--#include "link_encoder_types.h"
--#include "stream_encoder_types.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
- 
- 
- void unreference_clock_source(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index b6526e9..db7608e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -672,6 +672,14 @@ struct dc_csc_adjustments {
- 	struct fixed31_32 hue;
- };
- 
-+enum dc_encoder_result {
-+	ENCODER_RESULT_OK,
-+	ENCODER_RESULT_ERROR,
-+	ENCODER_RESULT_NOBANDWIDTH,
-+	ENCODER_RESULT_SINKCONNECTIVITYCHANGED
-+#endif
-+};
-+
- #include "dc_temp.h"
- 
- #endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 29e7b80..9c0bcbb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -34,8 +34,6 @@
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_stream_encoder.h"
--#include "stream_encoder_types.h"
--#include "link_encoder_types.h"
- #include "dce110/dce110_mem_input.h"
- #include "dce110/dce110_ipp.h"
- #include "dce110/dce110_transform.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 91796ac..4381a94 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -25,8 +25,8 @@
- 
- #include "dal_services.h"
- #include "core_types.h"
--#include "link_encoder_types.h"
--#include "stream_encoder_types.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
- #include "dce110_link_encoder.h"
- #include "i2caux_interface.h"
- #include "dce/dce_11_0_d.h"
-@@ -83,12 +83,26 @@ enum {
- #endif
- 
- 
--static const uint32_t fe_engine_offsets[] = {
--	mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
--	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
--	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
--};
-+#define DIG_REG(reg)\
-+	(reg + enc110->offsets.dig_offset)
-+
-+#define DP_REG(reg)\
-+	(reg + enc110->offsets.dp_offset)
- 
-+static const struct dce110_link_enc_offsets reg_offsets[] = {
-+{
-+	.dig_offset = (mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
-+	.dp_offset = (mmDP0_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+},
-+{
-+	.dig_offset = (mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
-+	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+},
-+{
-+	.dig_offset = (mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
-+	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+}
-+};
- 
- static enum transmitter translate_encoder_to_transmitter(
- 	struct graphics_object_id encoder)
-@@ -156,14 +170,14 @@ static enum transmitter translate_encoder_to_transmitter(
- }
- 
- static void enable_phy_bypass_mode(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	bool enable)
- {
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
-+	struct dc_context *ctx = enc110->base.ctx;
- 
--	const uint32_t addr = mmDP_DPHY_CNTL + be_addr_offset;
-+	const uint32_t addr = DP_REG(mmDP_DPHY_CNTL);
- 
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -173,14 +187,14 @@ static void enable_phy_bypass_mode(
- }
- 
- static void disable_prbs_symbols(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	bool disable)
- {
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
-+	struct dc_context *ctx = enc110->base.ctx;
- 
--	const uint32_t addr = mmDP_DPHY_CNTL + be_addr_offset;
-+	const uint32_t addr = DP_REG(mmDP_DPHY_CNTL);
- 
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -200,13 +214,13 @@ static void disable_prbs_symbols(
- }
- 
- static void disable_prbs_mode(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset)
-+	struct dce110_link_encoder *enc110)
- {
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
-+	struct dc_context *ctx = enc110->base.ctx;
- 
--	const uint32_t addr = mmDP_DPHY_PRBS_CNTL + be_addr_offset;
-+	const uint32_t addr = DP_REG(mmDP_DPHY_PRBS_CNTL);
- 	uint32_t value;
- 
- 	value = dal_read_reg(ctx, addr);
-@@ -217,17 +231,17 @@ static void disable_prbs_mode(
- }
- 
- static void program_pattern_symbols(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	uint16_t pattern_symbols[8])
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
- 
--	addr = mmDP_DPHY_SYM0 + be_addr_offset;
-+	addr = DP_REG(mmDP_DPHY_SYM0);
- 
- 	value = 0;
- 	set_reg_field_value(value, pattern_symbols[0],
-@@ -241,7 +255,7 @@ static void program_pattern_symbols(
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
- 
--	addr = mmDP_DPHY_SYM1 + be_addr_offset;
-+	addr = DP_REG(mmDP_DPHY_SYM1);
- 
- 	value = 0;
- 	set_reg_field_value(value, pattern_symbols[3],
-@@ -254,7 +268,7 @@ static void program_pattern_symbols(
- 
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
--	addr = mmDP_DPHY_SYM2 + be_addr_offset;
-+	addr = DP_REG(mmDP_DPHY_SYM2);
- 	value = 0;
- 	set_reg_field_value(value, pattern_symbols[6],
- 			DP_DPHY_SYM2, DPHY_SYM7);
-@@ -265,24 +279,22 @@ static void program_pattern_symbols(
- }
- 
- static void set_dp_phy_pattern_d102(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset)
-+	struct dce110_link_encoder *enc110)
- {
- 	/* Disable PHY Bypass mode to setup the test pattern */
--
--	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* For 10-bit PRBS or debug symbols
- 	 * please use the following sequence: */
- 
- 	/* Enable debug symbols on the lanes */
- 
--	disable_prbs_symbols(ctx, be_addr_offset, true);
-+	disable_prbs_symbols(enc110, true);
- 
- 	/* Disable PRBS mode,
- 	 * make sure DPHY_PRBS_CNTL.DPHY_PRBS_EN=0 */
- 
--	disable_prbs_mode(ctx, be_addr_offset);
-+	disable_prbs_mode(enc110);
- 
- 	/* Program debug symbols to be output */
- 	{
-@@ -291,25 +303,22 @@ static void set_dp_phy_pattern_d102(
- 			0x2AA, 0x2AA, 0x2AA, 0x2AA
- 		};
- 
--		program_pattern_symbols(ctx,
--			be_addr_offset, pattern_symbols);
-+		program_pattern_symbols(enc110, pattern_symbols);
- 	}
- 
- 	/* Enable phy bypass mode to enable the test pattern */
- 
--	enable_phy_bypass_mode(ctx, be_addr_offset, true);
-+	enable_phy_bypass_mode(enc110, true);
- }
- 
- static void set_link_training_complete(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	bool complete)
- {
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
--
--	const uint32_t addr = mmDP_LINK_CNTL + be_addr_offset;
--
-+	struct dc_context *ctx = enc110->base.ctx;
-+	const uint32_t addr = DP_REG(mmDP_LINK_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, complete,
-@@ -319,40 +328,40 @@ static void set_link_training_complete(
- }
- 
- static void set_dp_phy_pattern_training_pattern(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	uint32_t index)
- {
- 	/* Write Training Pattern */
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DP_REG(mmDP_DPHY_TRAINING_PATTERN_SEL);
- 
--	dal_write_reg(ctx,
--		mmDP_DPHY_TRAINING_PATTERN_SEL + be_addr_offset, index);
-+	dal_write_reg(ctx, addr, index);
- 
- 	/* Set HW Register Training Complete to false */
- 
--	set_link_training_complete(ctx, be_addr_offset, false);
-+	set_link_training_complete(enc110, false);
- 
- 	/* Disable PHY Bypass mode to output Training Pattern */
- 
--	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* Disable PRBS mode,
- 	 * make sure DPHY_PRBS_CNTL.DPHY_PRBS_EN=0 */
- 
--	disable_prbs_mode(ctx, be_addr_offset);
-+	disable_prbs_mode(enc110);
- }
- 
- static void set_dp_phy_pattern_symbol_error(
--	struct dc_context *ctx,
--	const int32_t addr_offset)
-+	struct dce110_link_encoder *enc110)
- {
- 	/* Disable PHY Bypass mode to setup the test pattern */
-+	struct dc_context *ctx = enc110->base.ctx;
- 
--	enable_phy_bypass_mode(ctx, addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* program correct panel mode*/
- 	{
--		const uint32_t addr = mmDP_DPHY_INTERNAL_CTRL + addr_offset;
-+		const uint32_t addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
- 		uint32_t value = 0x0;
- 		dal_write_reg(ctx, addr, value);
- 	}
-@@ -361,11 +370,11 @@ static void set_dp_phy_pattern_symbol_error(
- 
- 	/* Enable PRBS symbols on the lanes */
- 
--	disable_prbs_symbols(ctx, addr_offset, false);
-+	disable_prbs_symbols(enc110, false);
- 
- 	/* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
- 	{
--		const uint32_t addr = mmDP_DPHY_PRBS_CNTL + addr_offset;
-+		const uint32_t addr = DP_REG(mmDP_DPHY_PRBS_CNTL);
- 		uint32_t value = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(value, 1,
-@@ -377,26 +386,26 @@ static void set_dp_phy_pattern_symbol_error(
- 
- 	/* Enable phy bypass mode to enable the test pattern */
- 
--	enable_phy_bypass_mode(ctx, addr_offset, true);
-+	enable_phy_bypass_mode(enc110, true);
- }
- 
- static void set_dp_phy_pattern_prbs7(
--	struct dc_context *ctx,
--	const int32_t addr_offset)
-+	struct dce110_link_encoder *enc110)
- {
- 	/* Disable PHY Bypass mode to setup the test pattern */
-+	struct dc_context *ctx = enc110->base.ctx;
- 
--	enable_phy_bypass_mode(ctx, addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* A PRBS7 pattern is used for most DP electrical measurements. */
- 
- 	/* Enable PRBS symbols on the lanes */
- 
--	disable_prbs_symbols(ctx, addr_offset, false);
-+	disable_prbs_symbols(enc110, false);
- 
- 	/* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
- 	{
--		const uint32_t addr = mmDP_DPHY_PRBS_CNTL + addr_offset;
-+		const uint32_t addr = DP_REG(mmDP_DPHY_PRBS_CNTL);
- 
- 		uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -411,26 +420,24 @@ static void set_dp_phy_pattern_prbs7(
- 
- 	/* Enable phy bypass mode to enable the test pattern */
- 
--	enable_phy_bypass_mode(ctx, addr_offset, true);
-+	enable_phy_bypass_mode(enc110, true);
- }
- 
- static void set_dp_phy_pattern_80bit_custom(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	const uint8_t *pattern)
- {
- 	/* Disable PHY Bypass mode to setup the test pattern */
--
--	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* Enable debug symbols on the lanes */
- 
--	disable_prbs_symbols(ctx, be_addr_offset, true);
-+	disable_prbs_symbols(enc110, true);
- 
- 	/* Enable PHY bypass mode to enable the test pattern */
- 	/* TODO is it really needed ? */
- 
--	enable_phy_bypass_mode(ctx, be_addr_offset, true);
-+	enable_phy_bypass_mode(enc110, true);
- 
- 	/* Program 80 bit custom pattern */
- 	{
-@@ -453,22 +460,18 @@ static void set_dp_phy_pattern_80bit_custom(
- 		pattern_symbols[7] =
- 			(pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
- 
--		program_pattern_symbols(ctx,
--			be_addr_offset, pattern_symbols);
-+		program_pattern_symbols(enc110, pattern_symbols);
- 	}
- 
- 	/* Enable phy bypass mode to enable the test pattern */
- 
--	enable_phy_bypass_mode(ctx, be_addr_offset, true);
-+	enable_phy_bypass_mode(enc110, true);
- }
- 
- static void set_dp_phy_pattern_hbr2_compliance(
--	struct link_encoder *enc,
--	const int32_t be_addr_offset)
-+	struct dce110_link_encoder *enc110)
- {
--	/*const int32_t fe_addr_offset = fe_engine_offsets[param->engine];
--	const int32_t be_addr_offset = enc->be_engine_offset;*/
--
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 
-@@ -482,17 +485,17 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 
- 	/* Disable PHY Bypass mode to setup the test pattern */
- 
--	enable_phy_bypass_mode(enc->ctx, be_addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* Setup DIG encoder in DP SST mode */
- 
--	dce110_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
-+	dce110_link_encoder_setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
- 
- 	/* program correct panel mode*/
- 	{
--		const uint32_t addr = mmDP_DPHY_INTERNAL_CTRL + be_addr_offset;
-+		const uint32_t addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
- 		uint32_t value = 0x0;
--		dal_write_reg(enc->ctx, addr, value);
-+		dal_write_reg(ctx, addr, value);
- 	}
- 
- 	/* no vbid after BS (SR)
-@@ -508,7 +511,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	/* TODO: do we still need this, find out at compliance test
- 	addr = mmDP_LINK_FRAMING_CNTL + fe_addr_offset;
- 
--	value = dal_read_reg(enc->ctx, addr);
-+	value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0xFC,
- 			DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL);
-@@ -517,7 +520,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	set_reg_field_value(value, 1,
- 			DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE);
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 	 */
- 
- 	/*TODO add support for this test pattern
-@@ -525,30 +528,30 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	 */
- 
- 	/* set link training complete */
--	set_link_training_complete(enc->ctx, be_addr_offset, true);
-+	set_link_training_complete(enc110, true);
- 	/* do not enable video stream */
--	addr = mmDP_VID_STREAM_CNTL + be_addr_offset;
-+	addr = DP_REG(mmDP_VID_STREAM_CNTL);
- 
--	value = dal_read_reg(enc->ctx, addr);
-+	value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* Disable PHY Bypass mode to setup the test pattern */
- 
--	enable_phy_bypass_mode(enc->ctx, be_addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- }
- 
- static void set_dp_phy_pattern_passthrough_mode(
--	struct dc_context *ctx,
--	const int32_t be_addr_offset,
-+	struct dce110_link_encoder *enc110,
- 	enum dp_panel_mode panel_mode)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 
- 	/* program correct panel mode */
- 	{
--		const uint32_t addr = mmDP_DPHY_INTERNAL_CTRL + be_addr_offset;
-+		const uint32_t addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
- 
- 		uint32_t value;
- 
-@@ -571,146 +574,16 @@ static void set_dp_phy_pattern_passthrough_mode(
- 
- 	/* set link training complete */
- 
--	set_link_training_complete(ctx, be_addr_offset, true);
-+	set_link_training_complete(enc110, true);
- 
- 	/* Disable PHY Bypass mode to setup the test pattern */
- 
--	enable_phy_bypass_mode(ctx, be_addr_offset, false);
-+	enable_phy_bypass_mode(enc110, false);
- 
- 	/* Disable PRBS mode,
- 	 * make sure DPHY_PRBS_CNTL.DPHY_PRBS_EN=0 */
- 
--	disable_prbs_mode(ctx, be_addr_offset);
--}
--
--static void construct(
--	struct link_encoder *enc,
--	const struct encoder_init_data *init_data)
--{
--	struct graphics_object_encoder_cap_info enc_cap_info = {0};
--
--	enc->ctx = init_data->ctx;
--	enc->id = init_data->encoder;
--
--	enc->hpd_source = init_data->hpd_source;
--	enc->connector = init_data->connector;
--	enc->input_signals = SIGNAL_TYPE_ALL;
--
--	enc->adapter_service = init_data->adapter_service;
--
--	enc->preferred_engine = ENGINE_ID_UNKNOWN;
--
--	enc->features.flags.raw = 0;
--
--	enc->transmitter = translate_encoder_to_transmitter(
--		init_data->encoder);
--
--	enc->features.flags.bits.IS_AUDIO_CAPABLE = true;
--
--	enc->features.max_pixel_clock = DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
--
--	/* set the flag to indicate whether driver poll the I2C data pin
--	 * while doing the DP sink detect */
--
--	if (dal_adapter_service_is_feature_supported(
--		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
--		enc->features.flags.bits.DP_SINK_DETECT_POLL_DATA_PIN = true;
--
--	enc->output_signals =
--		SIGNAL_TYPE_DVI_SINGLE_LINK |
--		SIGNAL_TYPE_DVI_DUAL_LINK |
--		SIGNAL_TYPE_LVDS |
--		SIGNAL_TYPE_DISPLAY_PORT |
--		SIGNAL_TYPE_DISPLAY_PORT_MST |
--		SIGNAL_TYPE_EDP |
--		SIGNAL_TYPE_HDMI_TYPE_A;
--
--	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
--	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
--	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
--	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
--	 * Prefer DIG assignment is decided by board design.
--	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
--	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
--	 * By this, adding DIGG should not hurt DCE 8.0.
--	 * This will let DCE 8.1 share DCE 8.0 as much as possible */
--
--	switch (enc->transmitter) {
--	case TRANSMITTER_UNIPHY_A:
--		enc->preferred_engine = ENGINE_ID_DIGA;
--		enc->transmitter_offset = 0;
--		enc->be_engine_offset = 0;
--	break;
--	case TRANSMITTER_UNIPHY_B:
--		enc->preferred_engine = ENGINE_ID_DIGB;
--
--		enc->transmitter_offset =
--			mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 -
--			mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1;
--		enc->be_engine_offset =
--			mmDIG1_DIG_BE_CNTL - mmDIG0_DIG_BE_CNTL;
--	break;
--	case TRANSMITTER_UNIPHY_C:
--		enc->preferred_engine = ENGINE_ID_DIGC;
--		enc->transmitter_offset =
--			mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 -
--			mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1;
--		enc->be_engine_offset =
--			mmDIG2_DIG_BE_CNTL - mmDIG0_DIG_BE_CNTL;
--	break;
--	default:
--		ASSERT_CRITICAL(false);
--		enc->preferred_engine = ENGINE_ID_UNKNOWN;
--		enc->transmitter_offset = 0;
--		enc->be_engine_offset = 0;
--	}
--
--	dal_logger_write(init_data->ctx->logger,
--			LOG_MAJOR_I2C_AUX,
--			LOG_MINOR_I2C_AUX_CFG,
--			"Using channel: %s [%d]\n",
--			DECODE_CHANNEL_ID(init_data->channel),
--			init_data->channel);
--
--	switch (init_data->channel) {
--	case CHANNEL_ID_DDC1:
--		enc->aux_channel_offset = 0;
--		break;
--	case CHANNEL_ID_DDC2:
--		enc->aux_channel_offset =
--			mmDP_AUX1_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
--		break;
--	case CHANNEL_ID_DDC3:
--		enc->aux_channel_offset =
--			mmDP_AUX2_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
--		break;
--	default:
--		/* check BIOS object table ! */
--		dal_logger_write(init_data->ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_ENCODER,
--				"%s: Invalid channel ID\n",
--				__func__);
--		enc->aux_channel_offset = 0;
--	}
--
--	/* Override features with DCE-specific values */
--	if (dal_adapter_service_get_encoder_cap_info(enc->adapter_service,
--			enc->id, &enc_cap_info))
--		enc->features.flags.bits.IS_HBR2_CAPABLE =
--				enc_cap_info.dp_hbr2_cap;
--
--	/* test pattern 3 support */
--	enc->features.flags.bits.IS_TPS3_CAPABLE = true;
--	enc->features.max_deep_color = COLOR_DEPTH_121212;
--
--	enc->features.flags.bits.IS_Y_ONLY_CAPABLE =
--		dal_adapter_service_is_feature_supported(
--			FEATURE_SUPPORT_DP_Y_ONLY);
--
--	enc->features.flags.bits.IS_YCBCR_CAPABLE =
--		dal_adapter_service_is_feature_supported(
--			FEATURE_SUPPORT_DP_YUV);
-+	disable_prbs_mode(enc110);
- }
- 
- /* return value is bit-vector */
-@@ -731,28 +604,30 @@ static uint8_t get_frontend_source(
- }
- 
- static void configure_encoder(
--	struct link_encoder *enc,
-+	struct dce110_link_encoder *enc110,
- 	enum engine_id engine,
- 	const struct link_settings *link_settings)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 
- 	/* set number of lanes */
--	addr = mmDP_CONFIG + enc->be_engine_offset;
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DP_REG(mmDP_CONFIG);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
- 			DP_CONFIG, DP_UDI_LANES);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- }
- 
--static bool is_panel_powered_on(struct link_encoder *link_enc)
-+static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 	bool ret;
- 
--	value = dal_read_reg(link_enc->ctx,
-+	value = dal_read_reg(ctx,
- 			mmLVTMA_PWRSEQ_STATE);
- 
- 	ret = get_reg_field_value(value,
-@@ -765,25 +640,26 @@ static bool is_panel_powered_on(struct link_encoder *link_enc)
-  * @brief
-  * eDP only. Control the power of the eDP panel.
-  */
--static enum encoder_result link_encoder_edp_power_control(
--	struct link_encoder *link_enc,
-+static enum dc_encoder_result link_encoder_edp_power_control(
-+	struct dce110_link_encoder *enc110,
- 	bool power_up)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 	enum bp_result bp_result;
- 
--	if (dal_graphics_object_id_get_connector_id(link_enc->connector) !=
-+	if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
- 		CONNECTOR_ID_EDP) {
- 		BREAK_TO_DEBUGGER();
- 		return ENCODER_RESULT_ERROR;
- 	}
- 
--	if ((power_up && !is_panel_powered_on(link_enc)) ||
--		(!power_up && is_panel_powered_on(link_enc))) {
-+	if ((power_up && !is_panel_powered_on(enc110)) ||
-+		(!power_up && is_panel_powered_on(enc110))) {
- 
- 		/* Send VBIOS command to prompt eDP panel power */
- 
--		dal_logger_write(link_enc->ctx->logger,
-+		dal_logger_write(ctx->logger,
- 				LOG_MAJOR_HW_TRACE,
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: Panel Power action: %s\n",
-@@ -792,26 +668,26 @@ static enum encoder_result link_encoder_edp_power_control(
- 		cntl.action = power_up ?
- 			TRANSMITTER_CONTROL_POWER_ON :
- 			TRANSMITTER_CONTROL_POWER_OFF;
--		cntl.transmitter = link_enc->transmitter;
--		cntl.connector_obj_id = link_enc->connector;
-+		cntl.transmitter = enc110->base.transmitter;
-+		cntl.connector_obj_id = enc110->base.connector;
- 		cntl.coherent = false;
- 		cntl.lanes_number = LANE_COUNT_FOUR;
--		cntl.hpd_sel = link_enc->hpd_source;
-+		cntl.hpd_sel = enc110->base.hpd_source;
- 
- 		bp_result = dal_bios_parser_transmitter_control(
- 				dal_adapter_service_get_bios_parser(
--					link_enc->adapter_service), &cntl);
-+					enc110->base.adapter_service), &cntl);
- 
- 		if (BP_RESULT_OK != bp_result) {
- 
--			dal_logger_write(link_enc->ctx->logger,
-+			dal_logger_write(ctx->logger,
- 					LOG_MAJOR_ERROR,
- 					LOG_MINOR_HW_TRACE_RESUME_S3,
- 					"%s: Panel Power bp_result: %d\n",
- 					__func__, bp_result);
- 		}
- 	} else {
--		dal_logger_write(link_enc->ctx->logger,
-+		dal_logger_write(ctx->logger,
- 				LOG_MAJOR_HW_TRACE,
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: Skipping Panel Power action: %s\n",
-@@ -826,11 +702,12 @@ static enum encoder_result link_encoder_edp_power_control(
-  * eDP only.
-  */
- static void link_encoder_edp_wait_for_hpd_ready(
--	struct link_encoder *link_enc,
--	struct graphics_object_id connector,
-+	struct dce110_link_encoder *enc110,
- 	bool power_up)
- {
--	struct adapter_service *as = link_enc->adapter_service;
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct adapter_service *as = enc110->base.adapter_service;
-+	struct graphics_object_id connector = enc110->base.connector;
- 	struct irq *hpd;
- 	bool edp_hpd_high = false;
- 	uint32_t time_elapsed = 0;
-@@ -875,7 +752,7 @@ static void link_encoder_edp_wait_for_hpd_ready(
- 			break;
- 		}
- 
--		dc_service_sleep_in_milliseconds(link_enc->ctx, HPD_CHECK_INTERVAL);
-+		dc_service_sleep_in_milliseconds(ctx, HPD_CHECK_INTERVAL);
- 
- 		time_elapsed += HPD_CHECK_INTERVAL;
- 	} while (time_elapsed < timeout);
-@@ -885,7 +762,7 @@ static void link_encoder_edp_wait_for_hpd_ready(
- 	dal_adapter_service_release_irq(as, hpd);
- 
- 	if (false == edp_hpd_high) {
--		dal_logger_write(link_enc->ctx->logger,
-+		dal_logger_write(ctx->logger,
- 				LOG_MAJOR_ERROR,
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: wait timed out!\n", __func__);
-@@ -893,35 +770,37 @@ static void link_encoder_edp_wait_for_hpd_ready(
- }
- 
- static void aux_initialize(
--	struct link_encoder *link_enc,
--	enum hpd_source_id hpd_source)
-+	struct dce110_link_encoder *enc110)
- {
--	uint32_t addr = mmAUX_CONTROL + link_enc->aux_channel_offset;
--
--	uint32_t value = dal_read_reg(link_enc->ctx, addr);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	enum hpd_source_id hpd_source = enc110->base.hpd_source;
-+	uint32_t addr = mmAUX_CONTROL + enc110->base.aux_channel_offset;
-+	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
- 	set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
--	dal_write_reg(link_enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmAUX_DPHY_RX_CONTROL0 + link_enc->aux_channel_offset;
--	value = dal_read_reg(link_enc->ctx, addr);
-+	addr = mmAUX_DPHY_RX_CONTROL0 + enc110->base.aux_channel_offset;
-+	value = dal_read_reg(ctx, addr);
- 
- 	/* 1/4 window (the maximum allowed) */
- 	set_reg_field_value(value, 1,
- 			AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
--	dal_write_reg(link_enc->ctx,
--			mmAUX_DPHY_RX_CONTROL0 + link_enc->aux_channel_offset,
-+	dal_write_reg(ctx,
-+			mmAUX_DPHY_RX_CONTROL0 +
-+			enc110->base.aux_channel_offset,
- 			value);
- 
- }
- 
- /*todo: cloned in stream enc, fix*/
--static bool is_panel_backlight_on(struct link_encoder *link_enc)
-+static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 
--	value = dal_read_reg(link_enc->ctx, mmLVTMA_PWRSEQ_CNTL);
-+	value = dal_read_reg(ctx, mmLVTMA_PWRSEQ_CNTL);
- 
- 	return get_reg_field_value(value, LVTMA_PWRSEQ_CNTL, LVTMA_BLON);
- }
-@@ -931,20 +810,21 @@ static bool is_panel_backlight_on(struct link_encoder *link_enc)
-  * @brief
-  * eDP only. Control the backlight of the eDP panel
-  */
--static enum encoder_result link_encoder_edp_backlight_control(
--	struct link_encoder *link_enc,
-+static enum dc_encoder_result link_encoder_edp_backlight_control(
-+	struct dce110_link_encoder *enc110,
- 	bool enable)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 
--	if (dal_graphics_object_id_get_connector_id(link_enc->connector)
-+	if (dal_graphics_object_id_get_connector_id(enc110->base.connector)
- 		!= CONNECTOR_ID_EDP) {
- 		BREAK_TO_DEBUGGER();
- 		return ENCODER_RESULT_ERROR;
- 	}
- 
--	if (enable && is_panel_backlight_on(link_enc)) {
--		dal_logger_write(link_enc->ctx->logger,
-+	if (enable && is_panel_backlight_on(enc110)) {
-+		dal_logger_write(ctx->logger,
- 				LOG_MAJOR_HW_TRACE,
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: panel already powered up. Do nothing.\n",
-@@ -952,8 +832,8 @@ static enum encoder_result link_encoder_edp_backlight_control(
- 		return ENCODER_RESULT_OK;
- 	}
- 
--	if (!enable && !is_panel_powered_on(link_enc)) {
--		dal_logger_write(link_enc->ctx->logger,
-+	if (!enable && !is_panel_powered_on(enc110)) {
-+		dal_logger_write(ctx->logger,
- 				LOG_MAJOR_HW_TRACE,
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: panel already powered down. Do nothing.\n",
-@@ -963,7 +843,7 @@ static enum encoder_result link_encoder_edp_backlight_control(
- 
- 	/* Send VBIOS command to control eDP panel backlight */
- 
--	dal_logger_write(link_enc->ctx->logger,
-+	dal_logger_write(ctx->logger,
- 			LOG_MAJOR_HW_TRACE,
- 			LOG_MINOR_HW_TRACE_RESUME_S3,
- 			"%s: backlight action: %s\n",
-@@ -973,11 +853,11 @@ static enum encoder_result link_encoder_edp_backlight_control(
- 		TRANSMITTER_CONTROL_BACKLIGHT_ON :
- 		TRANSMITTER_CONTROL_BACKLIGHT_OFF;
- 	/*cntl.engine_id = ctx->engine;*/
--	cntl.transmitter = link_enc->transmitter;
--	cntl.connector_obj_id = link_enc->connector;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.connector_obj_id = enc110->base.connector;
- 	/*todo: unhardcode*/
- 	cntl.lanes_number = LANE_COUNT_FOUR;
--	cntl.hpd_sel = link_enc->hpd_source;
-+	cntl.hpd_sel = enc110->base.hpd_source;
- 
- 	/* For eDP, the following delays might need to be considered
- 	 * after link training completed:
-@@ -993,68 +873,70 @@ static enum encoder_result link_encoder_edp_backlight_control(
- 
- 	dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
--			link_enc->adapter_service), &cntl);
-+			enc110->base.adapter_service), &cntl);
- 
- 	return ENCODER_RESULT_OK;
- }
- 
--static bool is_dig_enabled(const struct link_encoder *link_enc)
-+static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 
--	value = dal_read_reg(link_enc->ctx,
--				mmDIG_BE_EN_CNTL + link_enc->be_engine_offset);
-+	value = dal_read_reg(ctx, DIG_REG(mmDIG_BE_EN_CNTL));
- 
- 	return get_reg_field_value(value, DIG_BE_EN_CNTL, DIG_ENABLE);
- }
- 
--static void link_encoder_disable(struct link_encoder *link_enc)
-+static void link_encoder_disable(struct dce110_link_encoder *enc110)
- {
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 
- 	/* reset training pattern */
--	addr = mmDP_DPHY_TRAINING_PATTERN_SEL + link_enc->be_engine_offset;
--	value = dal_read_reg(link_enc->ctx, addr);
-+	addr = DP_REG(mmDP_DPHY_TRAINING_PATTERN_SEL);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0,
- 			DP_DPHY_TRAINING_PATTERN_SEL,
- 			DPHY_TRAINING_PATTERN_SEL);
--	dal_write_reg(link_enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* reset training complete */
--	addr = mmDP_LINK_CNTL + link_enc->be_engine_offset;
--	value = dal_read_reg(link_enc->ctx, addr);
-+	addr = DP_REG(mmDP_LINK_CNTL);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE);
--	dal_write_reg(link_enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* reset panel mode */
--	addr = mmDP_DPHY_INTERNAL_CTRL + link_enc->be_engine_offset;
-+	addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
- 	value = 0;
--	dal_write_reg(link_enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- static void hpd_initialize(
--	struct link_encoder *enc,
--	enum hpd_source_id hpd_source)
-+	struct dce110_link_encoder *enc110)
- {
- 	/* Associate HPD with DIG_BE */
--	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
--	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	enum hpd_source_id hpd_source = enc110->base.hpd_source;
-+	const uint32_t addr = DIG_REG(mmDIG_BE_CNTL);
-+	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, DIG_BE_CNTL, DIG_HPD_SELECT);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- static bool validate_dvi_output(
--	const struct link_encoder *enc,
-+	const struct dce110_link_encoder *enc110,
- 	enum signal_type connector_signal,
- 	enum signal_type signal,
- 	const struct dc_crtc_timing *crtc_timing)
- {
- 	uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
- 
--	if (enc->features.max_pixel_clock < TMDS_MAX_PIXEL_CLOCK)
--		max_pixel_clock = enc->features.max_pixel_clock;
-+	if (enc110->base.features.max_pixel_clock < TMDS_MAX_PIXEL_CLOCK)
-+		max_pixel_clock = enc110->base.features.max_pixel_clock;
- 
- 	if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- 		max_pixel_clock <<= 1;
-@@ -1064,7 +946,7 @@ static bool validate_dvi_output(
- 	 */
- 	if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
- 			connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
--		max_pixel_clock = enc->features.max_pixel_clock;
-+		max_pixel_clock = enc110->base.features.max_pixel_clock;
- 
- 	/* DVI only support RGB pixel encoding */
- 	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-@@ -1094,7 +976,7 @@ static bool validate_dvi_output(
- }
- 
- static bool validate_hdmi_output(
--	const struct link_encoder *enc,
-+	const struct dce110_link_encoder *enc110,
- 	const struct dc_crtc_timing *crtc_timing,
- 	uint32_t max_tmds_clk_from_edid_in_mhz,
- 	enum dc_color_depth max_hdmi_deep_color,
-@@ -1105,8 +987,8 @@ static bool validate_hdmi_output(
- 	/* expressed in KHz */
- 	uint32_t pixel_clock = 0;
- 
--	if (max_deep_color > enc->features.max_deep_color)
--		max_deep_color = enc->features.max_deep_color;
-+	if (max_deep_color > enc110->base.features.max_deep_color)
-+		max_deep_color = enc110->base.features.max_deep_color;
- 
- 	if (max_deep_color < crtc_timing->display_color_depth)
- 		return false;
-@@ -1140,7 +1022,7 @@ static bool validate_hdmi_output(
- 
- 	if ((pixel_clock == 0) ||
- 		(pixel_clock > max_hdmi_pixel_clock) ||
--		(pixel_clock > enc->features.max_pixel_clock))
-+		(pixel_clock > enc110->base.features.max_pixel_clock))
- 		return false;
- 
- 	/*
-@@ -1160,10 +1042,10 @@ static bool validate_hdmi_output(
- }
- 
- static bool validate_rgb_output(
--	const struct link_encoder *enc,
-+	const struct dce110_link_encoder *enc110,
- 	const struct dc_crtc_timing *crtc_timing)
- {
--	if (crtc_timing->pix_clk_khz > enc->features.max_pixel_clock)
-+	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
- 		return false;
- 
- 	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-@@ -1173,23 +1055,23 @@ static bool validate_rgb_output(
- }
- 
- static bool validate_dp_output(
--	const struct link_encoder *enc,
-+	const struct dce110_link_encoder *enc110,
- 	const struct dc_crtc_timing *crtc_timing)
- {
--	if (crtc_timing->pix_clk_khz > enc->features.max_pixel_clock)
-+	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
- 		return false;
- 
- 	/* default RGB only */
- 	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
- 		return true;
- 
--	if (enc->features.flags.bits.IS_YCBCR_CAPABLE)
-+	if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
- 		return true;
- 
- 	/* for DCE 8.x or later DP Y-only feature,
- 	 * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
- 	if (crtc_timing->flags.Y_ONLY &&
--		enc->features.flags.bits.IS_YCBCR_CAPABLE &&
-+		enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
- 		crtc_timing->display_color_depth != COLOR_DEPTH_666)
- 		return true;
- 
-@@ -1197,10 +1079,10 @@ static bool validate_dp_output(
- }
- 
- static bool validate_wireless_output(
--	const struct link_encoder *enc,
-+	const struct dce110_link_encoder *enc110,
- 	const struct dc_crtc_timing *crtc_timing)
- {
--	if (crtc_timing->pix_clk_khz > enc->features.max_pixel_clock)
-+	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
- 		return false;
- 
- 	/* Wireless only supports YCbCr444 */
-@@ -1211,49 +1093,171 @@ static bool validate_wireless_output(
- 	return false;
- }
- 
-+bool dce110_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data)
-+{
-+	struct graphics_object_encoder_cap_info enc_cap_info = {0};
-+
-+	enc110->base.ctx = init_data->ctx;
-+	enc110->base.id = init_data->encoder;
-+
-+	enc110->base.hpd_source = init_data->hpd_source;
-+	enc110->base.connector = init_data->connector;
-+	enc110->base.input_signals = SIGNAL_TYPE_ALL;
-+
-+	enc110->base.adapter_service = init_data->adapter_service;
-+
-+	enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-+
-+	enc110->base.features.flags.raw = 0;
-+
-+	enc110->base.transmitter = translate_encoder_to_transmitter(
-+		init_data->encoder);
-+
-+	enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
-+
-+	enc110->base.features.max_pixel_clock =
-+		DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+
-+	/* set the flag to indicate whether driver poll the I2C data pin
-+	 * while doing the DP sink detect
-+	 */
-+
-+	if (dal_adapter_service_is_feature_supported(
-+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
-+		enc110->base.features.flags.bits.
-+			DP_SINK_DETECT_POLL_DATA_PIN = true;
-+
-+	enc110->base.output_signals =
-+		SIGNAL_TYPE_DVI_SINGLE_LINK |
-+		SIGNAL_TYPE_DVI_DUAL_LINK |
-+		SIGNAL_TYPE_LVDS |
-+		SIGNAL_TYPE_DISPLAY_PORT |
-+		SIGNAL_TYPE_DISPLAY_PORT_MST |
-+		SIGNAL_TYPE_EDP |
-+		SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
-+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
-+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
-+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
-+	 * Prefer DIG assignment is decided by board design.
-+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
-+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
-+	 * By this, adding DIGG should not hurt DCE 8.0.
-+	 * This will let DCE 8.1 share DCE 8.0 as much as possible
-+	 */
-+
-+	switch (enc110->base.transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGA;
-+	break;
-+	case TRANSMITTER_UNIPHY_B:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGB;
-+	break;
-+	case TRANSMITTER_UNIPHY_C:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGC;
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-+	}
-+
-+	enc110->offsets = reg_offsets[enc110->base.transmitter];
-+
-+	dal_logger_write(init_data->ctx->logger,
-+			LOG_MAJOR_I2C_AUX,
-+			LOG_MINOR_I2C_AUX_CFG,
-+			"Using channel: %s [%d]\n",
-+			DECODE_CHANNEL_ID(init_data->channel),
-+			init_data->channel);
-+
-+	switch (init_data->channel) {
-+	case CHANNEL_ID_DDC1:
-+		enc110->base.aux_channel_offset = 0;
-+		break;
-+	case CHANNEL_ID_DDC2:
-+		enc110->base.aux_channel_offset =
-+			mmDP_AUX1_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
-+		break;
-+	case CHANNEL_ID_DDC3:
-+		enc110->base.aux_channel_offset =
-+			mmDP_AUX2_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
-+		break;
-+	default:
-+		/* check BIOS object table ! */
-+		dal_logger_write(init_data->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_ENCODER,
-+				"%s: Invalid channel ID\n",
-+				__func__);
-+		enc110->base.aux_channel_offset = 0;
-+	}
-+
-+	/* Override features with DCE-specific values */
-+	if (dal_adapter_service_get_encoder_cap_info(
-+			enc110->base.adapter_service,
-+			enc110->base.id, &enc_cap_info))
-+		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
-+				enc_cap_info.dp_hbr2_cap;
-+
-+	/* test pattern 3 support */
-+	enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
-+	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-+
-+	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_SUPPORT_DP_Y_ONLY);
-+
-+	enc110->base.features.flags.bits.IS_YCBCR_CAPABLE =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_SUPPORT_DP_YUV);
-+	return true;
-+}
-+
- struct link_encoder *dce110_link_encoder_create(
- 	const struct encoder_init_data *init)
- {
--	struct link_encoder *enc =
--		dc_service_alloc(init->ctx, sizeof(struct link_encoder));
--
--	if (!enc)
--		goto enc_create_fail;
-+	struct dce110_link_encoder *enc110 =
-+		dc_service_alloc(init->ctx, sizeof(struct dce110_link_encoder));
- 
--	construct(enc, init);
-+	if (!enc110)
-+		return NULL;
- 
--	return enc;
-+	if (dce110_link_encoder_construct(enc110, init))
-+		return &enc110->base;
- 
--enc_create_fail:
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(init->ctx, enc110);
- 	return NULL;
- }
- 
- void dce110_link_encoder_destroy(struct link_encoder **enc)
- {
--	struct link_encoder *encoder = *enc;
--
--	dc_service_free(encoder->ctx, encoder);
-+	dc_service_free((*enc)->ctx, TO_DCE110_LINK_ENC(*enc));
- 	*enc = NULL;
- }
- 
--enum encoder_result dce110_link_encoder_validate_output_with_stream(
-+enum dc_encoder_result dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	bool is_valid;
- 
- 	switch (stream->signal) {
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 		is_valid = validate_dvi_output(
--			enc,
-+			enc110,
- 			stream->sink->link->public.connector_signal,
- 			stream->signal,
- 			&stream->public.timing);
- 	break;
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
- 		is_valid = validate_hdmi_output(
--				enc,
-+				enc110,
- 				&stream->public.timing,
- 				stream->max_tmds_clk_from_edid_in_mhz,
- 				stream->max_hdmi_deep_color,
-@@ -1261,17 +1265,17 @@ enum encoder_result dce110_link_encoder_validate_output_with_stream(
- 	break;
- 	case SIGNAL_TYPE_RGB:
- 		is_valid = validate_rgb_output(
--			enc, &stream->public.timing);
-+			enc110, &stream->public.timing);
- 	break;
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 	case SIGNAL_TYPE_EDP:
- 		is_valid = validate_dp_output(
--			enc, &stream->public.timing);
-+			enc110, &stream->public.timing);
- 	break;
- 	case SIGNAL_TYPE_WIRELESS:
- 		is_valid = validate_wireless_output(
--			enc, &stream->public.timing);
-+			enc110, &stream->public.timing);
- 	break;
- 	default:
- 		is_valid = true;
-@@ -1281,28 +1285,30 @@ enum encoder_result dce110_link_encoder_validate_output_with_stream(
- 	return is_valid ? ENCODER_RESULT_OK : ENCODER_RESULT_ERROR;
- }
- 
--enum encoder_result dce110_link_encoder_power_up(
-+enum dc_encoder_result dce110_link_encoder_power_up(
- 	struct link_encoder *enc)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 
- 	enum bp_result result;
- 
- 	cntl.action = TRANSMITTER_CONTROL_INIT;
- 	cntl.engine_id = ENGINE_ID_UNKNOWN;
--	cntl.transmitter = enc->transmitter;
--	cntl.connector_obj_id = enc->connector;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.connector_obj_id = enc110->base.connector;
- 	cntl.lanes_number = LANE_COUNT_FOUR;
- 	cntl.coherent = false;
--	cntl.hpd_sel = enc->hpd_source;
-+	cntl.hpd_sel = enc110->base.hpd_source;
- 
- 	result = dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
--			enc->adapter_service),
-+			enc110->base.adapter_service),
- 		&cntl);
- 
- 	if (result != BP_RESULT_OK) {
--		dal_logger_write(enc->ctx->logger,
-+		dal_logger_write(ctx->logger,
- 			LOG_MAJOR_ERROR,
- 			LOG_MINOR_COMPONENT_ENCODER,
- 			"%s: Failed to execute VBIOS command table!\n",
-@@ -1311,30 +1317,30 @@ enum encoder_result dce110_link_encoder_power_up(
- 		return ENCODER_RESULT_ERROR;
- 	}
- 
--	if (enc->connector.id == CONNECTOR_ID_LVDS) {
-+	if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
- 		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
- 
- 		result = dal_bios_parser_transmitter_control(
- 			dal_adapter_service_get_bios_parser(
--				enc->adapter_service),
-+				enc110->base.adapter_service),
- 			&cntl);
- 		ASSERT(result == BP_RESULT_OK);
- 
--	} else if (enc->connector.id == CONNECTOR_ID_EDP) {
--		link_encoder_edp_power_control(enc, true);
-+	} else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-+		link_encoder_edp_power_control(enc110, true);
- 
- 		link_encoder_edp_wait_for_hpd_ready(
--			enc, enc->connector, true);
-+			enc110, true);
- 
- 	}
--	aux_initialize(enc, enc->hpd_source);
-+	aux_initialize(enc110);
- 
- 	/* reinitialize HPD.
- 	 * hpd_initialize() will pass DIG_FE id to HW context.
- 	 * All other routine within HW context will use fe_engine_offset
- 	 * as DIG_FE id even caller pass DIG_FE id.
- 	 * So this routine must be called first. */
--	hpd_initialize(enc, enc->hpd_source);
-+	hpd_initialize(enc110);
- 
- 	return ENCODER_RESULT_OK;
- }
-@@ -1343,8 +1349,10 @@ void dce110_link_encoder_setup(
- 	struct link_encoder *enc,
- 	enum signal_type signal)
- {
--	const uint32_t addr = mmDIG_BE_CNTL + enc->be_engine_offset;
--	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	const uint32_t addr = DIG_REG(mmDIG_BE_CNTL);
-+	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	switch (signal) {
- 	case SIGNAL_TYPE_EDP:
-@@ -1375,10 +1383,10 @@ void dce110_link_encoder_setup(
- 		break;
- 	}
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
--enum encoder_result dce110_link_encoder_enable_tmds_output(
-+enum dc_encoder_result dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
-@@ -1387,7 +1395,7 @@ enum encoder_result dce110_link_encoder_enable_tmds_output(
- 	return ENCODER_RESULT_OK;
- }
- 
--enum encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
-+enum dc_encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
-@@ -1397,7 +1405,7 @@ enum encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
- }
- 
- /* enables DP PHY output */
--enum encoder_result dce110_link_encoder_enable_dp_output(
-+enum dc_encoder_result dce110_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source)
-@@ -1406,7 +1414,7 @@ enum encoder_result dce110_link_encoder_enable_dp_output(
- }
- 
- /* enables DP PHY output in MST mode */
--enum encoder_result dce110_link_encoder_enable_dp_mst_output(
-+enum dc_encoder_result dce110_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source)
-@@ -1418,22 +1426,24 @@ enum encoder_result dce110_link_encoder_enable_dp_mst_output(
-  * @brief
-  * Disable transmitter and its encoder
-  */
--enum encoder_result dce110_link_encoder_disable_output(
--	struct link_encoder *link_enc,
-+enum dc_encoder_result dce110_link_encoder_disable_output(
-+	struct link_encoder *enc,
- 	enum signal_type signal)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct bp_transmitter_control cntl = { 0 };
- 
--	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
-+	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- 		/* have to turn off the backlight
- 		 * before power down eDP panel */
- 		link_encoder_edp_backlight_control(
--				link_enc, false);
-+				enc110, false);
- 	}
- 
--	if (!is_dig_enabled(link_enc) &&
--		dal_adapter_service_should_optimize(link_enc->adapter_service,
--					OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
-+	if (!is_dig_enabled(enc110) &&
-+		dal_adapter_service_should_optimize(
-+			enc110->base.adapter_service,
-+			OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
- 		return ENCODER_RESULT_OK;
- 	}
- 	/* Power-down RX and disable GPU PHY should be paired.
-@@ -1448,20 +1458,20 @@ enum encoder_result dce110_link_encoder_disable_output(
- 
- 	/* disable transmitter */
- 	cntl.action = TRANSMITTER_CONTROL_DISABLE;
--	cntl.transmitter = link_enc->transmitter;
--	cntl.hpd_sel = link_enc->hpd_source;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.hpd_sel = enc110->base.hpd_source;
- 	cntl.signal = signal;
--	cntl.connector_obj_id = link_enc->connector;
-+	cntl.connector_obj_id = enc110->base.connector;
- 
- 	dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
--			link_enc->adapter_service), &cntl);
-+			enc110->base.adapter_service), &cntl);
- 
- 	/* disable encoder */
- 	if (dc_is_dp_signal(signal))
--		link_encoder_disable(link_enc);
-+		link_encoder_disable(enc110);
- 
--	if (link_enc->connector.id == CONNECTOR_ID_EDP) {
-+	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- 		/* power down eDP panel */
- 		/* TODO: Power control cause regression, we should implement
- 		 * it properly, for now just comment it.
-@@ -1478,14 +1488,13 @@ enum encoder_result dce110_link_encoder_disable_output(
- 	return ENCODER_RESULT_OK;
- }
- 
--enum encoder_result dce110_link_encoder_dp_set_lane_settings(
-+enum dc_encoder_result dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	union dpcd_training_lane_set training_lane_set = { { 0 } };
--
- 	int32_t lane = 0;
--
- 	struct bp_transmitter_control cntl = { 0 };
- 
- 	if (!link_settings) {
-@@ -1494,10 +1503,10 @@ enum encoder_result dce110_link_encoder_dp_set_lane_settings(
- 	}
- 
- 	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
--	cntl.transmitter = enc->transmitter;
--	cntl.connector_obj_id = enc->connector;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.connector_obj_id = enc110->base.connector;
- 	cntl.lanes_number = link_settings->link_settings.lane_count;
--	cntl.hpd_sel = enc->hpd_source;
-+	cntl.hpd_sel = enc110->base.hpd_source;
- 	cntl.pixel_clock = link_settings->link_settings.link_rate *
- 						LINK_RATE_REF_FREQ_IN_KHZ;
- 
-@@ -1525,7 +1534,7 @@ enum encoder_result dce110_link_encoder_dp_set_lane_settings(
- 
- 		dal_bios_parser_transmitter_control(
- 			dal_adapter_service_get_bios_parser(
--				enc->adapter_service), &cntl);
-+				enc110->base.adapter_service), &cntl);
- 	}
- 
- 	return ENCODER_RESULT_OK;
-@@ -1536,49 +1545,40 @@ void dce110_link_encoder_set_dp_phy_pattern(
- 	struct link_encoder *enc,
- 	const struct encoder_set_dp_phy_pattern_param *param)
- {
--	const int32_t offset = enc->be_engine_offset;
--
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 
- 	switch (param->dp_phy_pattern) {
- 	case DP_TEST_PATTERN_TRAINING_PATTERN1:
--		set_dp_phy_pattern_training_pattern(enc->ctx,
--			offset, 0);
-+		set_dp_phy_pattern_training_pattern(enc110, 0);
- 		break;
- 	case DP_TEST_PATTERN_TRAINING_PATTERN2:
--		set_dp_phy_pattern_training_pattern(enc->ctx,
--			offset, 1);
-+		set_dp_phy_pattern_training_pattern(enc110, 1);
- 		break;
- 	case DP_TEST_PATTERN_TRAINING_PATTERN3:
--		set_dp_phy_pattern_training_pattern(enc->ctx,
--			offset, 2);
-+		set_dp_phy_pattern_training_pattern(enc110, 2);
- 		break;
- 	case DP_TEST_PATTERN_D102:
--		set_dp_phy_pattern_d102(enc->ctx, offset);
-+		set_dp_phy_pattern_d102(enc110);
- 		break;
- 	case DP_TEST_PATTERN_SYMBOL_ERROR:
--		set_dp_phy_pattern_symbol_error(enc->ctx, offset);
-+		set_dp_phy_pattern_symbol_error(enc110);
- 		break;
- 	case DP_TEST_PATTERN_PRBS7:
--		set_dp_phy_pattern_prbs7(enc->ctx, offset);
-+		set_dp_phy_pattern_prbs7(enc110);
- 		break;
- 	case DP_TEST_PATTERN_80BIT_CUSTOM:
- 		set_dp_phy_pattern_80bit_custom(
--				enc->ctx,
--			offset, param->custom_pattern);
-+			enc110, param->custom_pattern);
- 		break;
- 	case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
--		set_dp_phy_pattern_hbr2_compliance(
--			enc, offset);
-+		set_dp_phy_pattern_hbr2_compliance(enc110);
- 		break;
- 	case DP_TEST_PATTERN_VIDEO_MODE: {
- 		set_dp_phy_pattern_passthrough_mode(
--			enc->ctx,
--			offset,
--			param->dp_panel_mode);
-+			enc110, param->dp_panel_mode);
- 		break;
- 	}
- 
--
- 	default:
- 		/* invalid phy pattern */
- 		ASSERT_CRITICAL(false);
-@@ -1591,7 +1591,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
- 	const struct dp_mst_stream_allocation_table *table)
- {
--	int32_t addr_offset = enc->be_engine_offset;
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value0;
- 	uint32_t value1;
- 	uint32_t retries = 0;
-@@ -1603,8 +1604,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * Setup VC Payload Table on Tx Side,
- 	 * Issue allocation change trigger
- 	 * to commit payload on both tx and rx side */
--	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset);
--	value1 = dal_read_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset);
-+	value0 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT0));
-+	value1 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT1));
- 
- 	if (table->stream_count >= 1) {
- 		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[0].engine);
-@@ -1655,8 +1656,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	}
- 
- 	/* update ASIC MSE stream allocation table */
--	dal_write_reg(enc->ctx, mmDP_MSE_SAT0 + addr_offset, value0);
--	dal_write_reg(enc->ctx, mmDP_MSE_SAT1 + addr_offset, value1);
-+	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT0), value0);
-+	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT1), value1);
- 
- 	/* --- wait for transaction finish */
- 
-@@ -1665,7 +1666,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * then double buffers the SAT into the hardware
- 	 * making the new allocation active on the DP MST mode link */
- 
--	value0 = dal_read_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset);
-+	value0 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT_UPDATE));
- 
- 	/* DP_MSE_SAT_UPDATE:
- 	 * 0 - No Action
-@@ -1678,7 +1679,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_UPDATE,
- 		DP_MSE_SAT_UPDATE);
- 
--	dal_write_reg(enc->ctx, mmDP_MSE_SAT_UPDATE + addr_offset, value0);
-+	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT_UPDATE), value0);
- 
- 	/* wait for update to complete
- 	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
-@@ -1691,10 +1692,10 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * after this bit is cleared */
- 
- 	do {
--		dc_service_delay_in_microseconds(enc->ctx, 10);
-+		dc_service_delay_in_microseconds(ctx, 10);
- 
--		value0 = dal_read_reg(enc->ctx,
--				mmDP_MSE_SAT_UPDATE + addr_offset);
-+		value0 = dal_read_reg(ctx,
-+				DP_REG(mmDP_MSE_SAT_UPDATE));
- 
- 		value1 = get_reg_field_value(
- 				value0,
-@@ -1713,7 +1714,8 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level)
- {
--	struct dc_context *ctx = enc->ctx;
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 
- 	const uint32_t backlight_update_pending_max_retry = 1000;
- 
-@@ -1846,7 +1848,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
-  * Configure digital transmitter and enable both encoder and transmitter
-  * Actual output will be available after calling unblank()
-  */
--enum encoder_result dce110_link_encoder_enable_output(
-+enum dc_encoder_result dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum engine_id engine,
-@@ -1855,21 +1857,20 @@ enum encoder_result dce110_link_encoder_enable_output(
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 
--	if (enc->connector.id == CONNECTOR_ID_EDP) {
-+	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- 		/* power up eDP panel */
- 
--		link_encoder_edp_power_control(
--			enc, true);
-+		link_encoder_edp_power_control(enc110, true);
- 
--		link_encoder_edp_wait_for_hpd_ready(
--			enc, enc->connector, true);
-+		link_encoder_edp_wait_for_hpd_ready(enc110, true);
- 
- 		/* have to turn off the backlight
- 		 * before power down eDP panel */
--		link_encoder_edp_backlight_control(
--				enc, true);
-+		link_encoder_edp_backlight_control(enc110, true);
- 	}
- 
- 	/* Enable the PHY */
-@@ -1878,15 +1879,15 @@ enum encoder_result dce110_link_encoder_enable_output(
- 	 * but it's not passed to asic_control.
- 	 * We need to set number of lanes manually. */
- 	if (dc_is_dp_signal(signal))
--		configure_encoder(enc, engine, link_settings);
-+		configure_encoder(enc110, engine, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
- 	cntl.engine_id = engine;
--	cntl.transmitter = enc->transmitter;
-+	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = signal;
- 	cntl.lanes_number = link_settings->lane_count;
--	cntl.hpd_sel = enc->hpd_source;
-+	cntl.hpd_sel = enc110->base.hpd_source;
- 	if (dc_is_dp_signal(signal))
- 		cntl.pixel_clock = link_settings->link_rate
- 						* LINK_RATE_REF_FREQ_IN_KHZ;
-@@ -1896,12 +1897,12 @@ enum encoder_result dce110_link_encoder_enable_output(
- 
- 	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
- 		dc_service_sleep_in_milliseconds(
--			enc->ctx,
-+			ctx,
- 			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
- 
- 	dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
--			enc->adapter_service),
-+			enc110->base.adapter_service),
- 		&cntl);
- 
- 	return ENCODER_RESULT_OK;
-@@ -1912,13 +1913,15 @@ void dce110_link_encoder_connect_dig_be_to_fe(
- 	enum engine_id engine,
- 	bool connect)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 	uint32_t field;
- 
- 	if (engine != ENGINE_ID_UNKNOWN) {
--		addr = mmDIG_BE_CNTL + enc->be_engine_offset;
--		value = dal_read_reg(enc->ctx, addr);
-+		addr = DIG_REG(mmDIG_BE_CNTL);
-+		value = dal_read_reg(ctx, addr);
- 
- 		field = get_reg_field_value(
- 				value,
-@@ -1935,7 +1938,7 @@ void dce110_link_encoder_connect_dig_be_to_fe(
- 			field,
- 			DIG_BE_CNTL,
- 			DIG_FE_SOURCE_SELECT);
--		dal_write_reg(enc->ctx, addr, value);
-+		dal_write_reg(ctx, addr, value);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 1032228..064e50c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -26,19 +26,34 @@
- #ifndef __DC_LINK_ENCODER__DCE110_H__
- #define __DC_LINK_ENCODER__DCE110_H__
- 
-+#include "inc/link_encoder.h"
-+
-+#define TO_DCE110_LINK_ENC(link_encoder)\
-+	container_of(link_encoder, struct dce110_link_encoder, base)
-+
-+struct dce110_link_enc_offsets {
-+	uint32_t dig_offset;
-+	uint32_t dp_offset;
-+};
-+
-+struct dce110_link_encoder {
-+	struct link_encoder base;
-+	struct dce110_link_enc_offsets offsets;
-+};
-+
- struct link_encoder *dce110_link_encoder_create(
- 	const struct encoder_init_data *init);
- 
- void dce110_link_encoder_destroy(struct link_encoder **enc);
- 
--enum encoder_result dce110_link_encoder_validate_output_with_stream(
-+enum dc_encoder_result dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream);
- 
- /****************** HW programming ************************/
- 
- /* initialize HW */  /* why do we initialze aux in here? */
--enum encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
-+enum dc_encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
- 
- /* program DIG_MODE in DIG_BE */
- /* TODO can this be combined with enable_output? */
-@@ -48,7 +63,7 @@ void dce110_link_encoder_setup(
- 
- /* enables TMDS PHY output */
- /* TODO: still need depth or just pass in adjusted pixel clock? */
--enum encoder_result dce110_link_encoder_enable_tmds_output(
-+enum dc_encoder_result dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
-@@ -56,31 +71,31 @@ enum encoder_result dce110_link_encoder_enable_tmds_output(
- 
- /* enables TMDS PHY output */
- /* TODO: still need this or just pass in adjusted pixel clock? */
--enum encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
-+enum dc_encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock);
- 
- /* enables DP PHY output */
--enum encoder_result dce110_link_encoder_enable_dp_output(
-+enum dc_encoder_result dce110_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source);
- 
- /* enables DP PHY output in MST mode */
--enum encoder_result dce110_link_encoder_enable_dp_mst_output(
-+enum dc_encoder_result dce110_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source);
- 
- /* disable PHY output */
--enum encoder_result dce110_link_encoder_disable_output(
--	struct link_encoder *link_enc,
-+enum dc_encoder_result dce110_link_encoder_disable_output(
-+	struct link_encoder *enc,
- 	enum signal_type signal);
- 
- /* set DP lane settings */
--enum encoder_result dce110_link_encoder_dp_set_lane_settings(
-+enum dc_encoder_result dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings);
- 
-@@ -97,7 +112,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level);
- 
--enum encoder_result dce110_link_encoder_enable_output(
-+enum dc_encoder_result dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 7e69dd5..77fbbe4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -196,16 +196,12 @@ bool dce110_construct_resource_pool(
- 	}
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
--		struct stream_enc_init_data enc_init_data = { 0 };
--		enc_init_data.stream_engine_id = i;
--		enc_init_data.ctx = dc->ctx;
--		enc_init_data.bp = dal_adapter_service_get_bios_parser(
--			adapter_serv);
- 		/* TODO: rework fragile code*/
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
--					&enc_init_data);
--
-+				i, dc->ctx,
-+				dal_adapter_service_get_bios_parser(
-+					adapter_serv));
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
- 				dal_error("DC: failed to create stream_encoder!\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 95dbc35..8f5560a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -24,16 +24,30 @@
-  */
- 
- #include "dal_services.h"
--#include "stream_encoder_types.h"
- #include "dce110_stream_encoder.h"
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
- 
--static const uint32_t fe_engine_offsets[] = {
--	mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
--	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
--	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+#define DIG_REG(reg)\
-+	(reg + enc110->offsets.dig_offset)
-+
-+#define DP_REG(reg)\
-+	(reg + enc110->offsets.dp_offset)
-+
-+static const struct dce110_stream_enc_offsets reg_offsets[] = {
-+{
-+	.dig_offset = (mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
-+	.dp_offset = (mmDP0_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+},
-+{
-+	.dig_offset = (mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
-+	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+},
-+{
-+	.dig_offset = (mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
-+	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+}
- };
- 
- #define VBI_LINE_0 0
-@@ -49,21 +63,11 @@ enum {
- 	DP_MST_UPDATE_MAX_RETRY = 50
- };
- 
--static void construct(
--	struct stream_encoder *enc,
--	struct stream_enc_init_data *init)
--{
--	enc->ctx = init->ctx;
--	enc->id = init->stream_engine_id;
--	enc->bp = init->bp;
--}
--
- static void update_avi_info_packet(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	const struct encoder_info_packet *info_packet)
- {
--	enum engine_id engine = enc->id;
--	const int32_t offset = fe_engine_offsets[engine];
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t regval;
- 	uint32_t addr;
- 	uint32_t control0val;
-@@ -73,49 +77,44 @@ static void update_avi_info_packet(
- 		const uint32_t *content =
- 			(const uint32_t *) &info_packet->sb[0];
- 
--		{
--			regval = content[0];
--
--			dal_write_reg(
--				enc->ctx,
--				mmAFMT_AVI_INFO0 + offset,
--				regval);
--		}
--		{
--			regval = content[1];
--
--			dal_write_reg(
--				enc->ctx,
--				mmAFMT_AVI_INFO1 + offset,
--				regval);
--		}
--		{
--			regval = content[2];
--
--			dal_write_reg(
--				enc->ctx,
--				mmAFMT_AVI_INFO2 + offset,
--				regval);
--		}
--		{
--			regval = content[3];
--
--			/* move version to AVI_INFO3 */
--			set_reg_field_value(
--				regval,
--				info_packet->hb1,
--				AFMT_AVI_INFO3,
--				AFMT_AVI_INFO_VERSION);
-+		addr = DIG_REG(mmAFMT_AVI_INFO0);
-+		regval = content[0];
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+		regval = content[1];
-+
-+		addr = DIG_REG(mmAFMT_AVI_INFO1);
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+		regval = content[2];
-+
-+		addr = DIG_REG(mmAFMT_AVI_INFO2);
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+		regval = content[3];
-+
-+		/* move version to AVI_INFO3 */
-+		addr = DIG_REG(mmAFMT_AVI_INFO3);
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb1,
-+			AFMT_AVI_INFO3,
-+			AFMT_AVI_INFO_VERSION);
- 
--			dal_write_reg(
--				enc->ctx,
--				mmAFMT_AVI_INFO3 + offset,
--				regval);
--		}
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
- 
--		addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
- 
--		control0val = dal_read_reg(enc->ctx, addr);
-+		control0val = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			control0val,
-@@ -129,11 +128,11 @@ static void update_avi_info_packet(
- 			HDMI_INFOFRAME_CONTROL0,
- 			HDMI_AVI_INFO_CONT);
- 
--		dal_write_reg(enc->ctx, addr, control0val);
-+		dal_write_reg(ctx, addr, control0val);
- 
--		addr = mmHDMI_INFOFRAME_CONTROL1 + offset;
-+		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL1);
- 
--		control1val = dal_read_reg(enc->ctx, addr);
-+		control1val = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			control1val,
-@@ -141,11 +140,11 @@ static void update_avi_info_packet(
- 			HDMI_INFOFRAME_CONTROL1,
- 			HDMI_AVI_INFO_LINE);
- 
--		dal_write_reg(enc->ctx, addr, control1val);
-+		dal_write_reg(ctx, addr, control1val);
- 	} else {
--		addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
- 
--		regval = dal_read_reg(enc->ctx, addr);
-+		regval = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			regval,
-@@ -159,23 +158,23 @@ static void update_avi_info_packet(
- 			HDMI_INFOFRAME_CONTROL0,
- 			HDMI_AVI_INFO_CONT);
- 
--		dal_write_reg(enc->ctx, addr, regval);
-+		dal_write_reg(ctx, addr, regval);
- 	}
- }
- 
- static void update_generic_info_packet(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
- {
--	enum engine_id engine = enc->id;
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t regval;
- 	/* choose which generic packet to use */
- 	{
--		addr = mmAFMT_VBI_PACKET_CONTROL + fe_engine_offsets[engine];
-+		addr = DIG_REG(mmAFMT_VBI_PACKET_CONTROL);
- 
--		regval = dal_read_reg(enc->ctx, addr);
-+		regval = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			regval,
-@@ -183,13 +182,13 @@ static void update_generic_info_packet(
- 			AFMT_VBI_PACKET_CONTROL,
- 			AFMT_GENERIC_INDEX);
- 
--		dal_write_reg(enc->ctx, addr, regval);
-+		dal_write_reg(ctx, addr, regval);
- 	}
- 
- 	/* write generic packet header
- 	 * (4th byte is for GENERIC0 only) */
- 	{
--		addr = mmAFMT_GENERIC_HDR + fe_engine_offsets[engine];
-+		addr = DIG_REG(mmAFMT_GENERIC_HDR);
- 
- 		regval = 0;
- 
-@@ -217,7 +216,7 @@ static void update_generic_info_packet(
- 			AFMT_GENERIC_HDR,
- 			AFMT_GENERIC_HB3);
- 
--		dal_write_reg(enc->ctx, addr, regval);
-+		dal_write_reg(ctx, addr, regval);
- 	}
- 
- 	/* write generic packet contents
-@@ -229,25 +228,27 @@ static void update_generic_info_packet(
- 
- 		uint32_t counter = 0;
- 
--		addr = mmAFMT_GENERIC_0 + fe_engine_offsets[engine];
-+		addr = DIG_REG(mmAFMT_GENERIC_0);
- 
- 		do {
--			dal_write_reg(enc->ctx, addr++, *content++);
-+			dal_write_reg(ctx, addr++, *content++);
- 
- 			++counter;
- 		} while (counter < 7);
- 	}
- 
-+	addr = DIG_REG(mmAFMT_GENERIC_7);
-+
- 	dal_write_reg(
--		enc->ctx,
--		mmAFMT_GENERIC_7 + fe_engine_offsets[engine],
-+		ctx,
-+		addr,
- 		0);
- 
- 	/* force double-buffered packet update */
- 	{
--		addr = mmAFMT_VBI_PACKET_CONTROL + fe_engine_offsets[engine];
-+		addr = DIG_REG(mmAFMT_VBI_PACKET_CONTROL);
- 
--		regval = dal_read_reg(enc->ctx, addr);
-+		regval = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			regval,
-@@ -261,23 +262,23 @@ static void update_generic_info_packet(
- 			AFMT_VBI_PACKET_CONTROL,
- 			AFMT_GENERIC2_UPDATE);
- 
--		dal_write_reg(enc->ctx, addr, regval);
-+		dal_write_reg(ctx, addr, regval);
- 	}
- }
- 
- static void update_hdmi_info_packet(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
- {
--	enum engine_id engine = enc->id;
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t cont, send, line;
--	uint32_t addr = fe_engine_offsets[engine];
-+	uint32_t addr;
- 	uint32_t regval;
- 
- 	if (info_packet->valid) {
- 		update_generic_info_packet(
--			enc,
-+			enc110,
- 			packet_index,
- 			info_packet);
- 
-@@ -299,24 +300,24 @@ static void update_hdmi_info_packet(
- 	switch (packet_index) {
- 	case 0:
- 	case 1:
--		addr += mmHDMI_GENERIC_PACKET_CONTROL0;
-+		addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL0);
- 		break;
- 	case 2:
- 	case 3:
--		addr += mmHDMI_GENERIC_PACKET_CONTROL1;
-+		addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL1);
- 		break;
- 	default:
- 		/* invalid HW packet index */
- 		dal_logger_write(
--			enc->ctx->logger,
-+			ctx->logger,
- 			LOG_MAJOR_WARNING,
- 			LOG_MINOR_COMPONENT_ENCODER,
- 			"Invalid HW packet index: %s()\n",
- 			__func__);
--		break;
-+		return;
- 	}
- 
--	regval = dal_read_reg(enc->ctx, addr);
-+	regval = dal_read_reg(ctx, addr);
- 
- 	switch (packet_index) {
- 	case 0:
-@@ -358,37 +359,37 @@ static void update_hdmi_info_packet(
- 	default:
- 		/* invalid HW packet index */
- 		dal_logger_write(
--			enc->ctx->logger,
-+			ctx->logger,
- 			LOG_MAJOR_WARNING,
- 			LOG_MINOR_COMPONENT_ENCODER,
- 			"Invalid HW packet index: %s()\n",
- 			__func__);
--		break;
-+		return;
- 	}
- 
--	dal_write_reg(enc->ctx, addr, regval);
-+	dal_write_reg(ctx, addr, regval);
- }
- 
- static void update_dp_info_packet(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
- {
--	enum engine_id engine = enc->id;
--	const uint32_t addr = mmDP_SEC_CNTL + fe_engine_offsets[engine];
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
- 
- 	uint32_t value;
- 
- 	if (info_packet->valid)
- 		update_generic_info_packet(
--			enc,
-+			enc110,
- 			packet_index,
- 			info_packet);
- 
- 	/* enable/disable transmission of packet(s).
- 	 * If enabled, packet transmission begins on the next frame */
- 
--	value = dal_read_reg(enc->ctx, addr);
-+	value = dal_read_reg(ctx, addr);
- 
- 	switch (packet_index) {
- 	case 0:
-@@ -439,16 +440,15 @@ static void update_dp_info_packet(
- 			DP_SEC_CNTL,
- 			DP_SEC_STREAM_ENABLE);
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- static void dp_steer_fifo_reset(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	bool reset)
- {
--	struct dc_context *ctx = enc->ctx;
--	enum engine_id engine = enc->id;
--	const uint32_t addr = mmDP_STEER_FIFO + fe_engine_offsets[engine];
-+	struct dc_context *ctx = enc110->base.ctx;
-+	const uint32_t addr = DP_REG(mmDP_STEER_FIFO);
- 
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -458,24 +458,24 @@ static void dp_steer_fifo_reset(
- }
- 
- static void unblank_dp_output(
--	struct stream_encoder *enc)
-+	struct dce110_stream_encoder *enc110)
- {
--	enum engine_id engine = enc->id;
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 
- 	/* set DIG_START to 0x1 to resync FIFO */
--	addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmDIG_FE_CNTL);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* switch DP encoder to CRTC data */
--	dp_steer_fifo_reset(enc, false);
-+	dp_steer_fifo_reset(enc110, false);
- 
- 	/* wait 100us for DIG/DP logic to prime
- 	 * (i.e. a few video lines) */
--	dc_service_delay_in_microseconds(enc->ctx, 100);
-+	dc_service_delay_in_microseconds(ctx, 100);
- 
- 	/* the hardware would start sending video at the start of the next DP
- 	 * frame (i.e. rising edge of the vblank).
-@@ -483,59 +483,59 @@ static void unblank_dp_output(
- 	 * register has no effect on enable transition! HW always guarantees
- 	 * VID_STREAM enable at start of next frame, and this is not
- 	 * programmable */
--	addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DP_REG(mmDP_VID_STREAM_CNTL);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		true,
- 		DP_VID_STREAM_CNTL,
- 		DP_VID_STREAM_ENABLE);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- }
- 
- static void setup_vid_stream(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	uint32_t m_vid,
- 	uint32_t n_vid)
- {
--	enum engine_id engine = enc->id;
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t value;
- 
- 	/* enable auto measurement */
--	addr = mmDP_VID_TIMING + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DP_REG(mmDP_VID_TIMING);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
- 	 * therefore program initial value for Mvid and Nvid */
--	addr = mmDP_VID_N + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DP_REG(mmDP_VID_N);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmDP_VID_M + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DP_REG(mmDP_VID_M);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmDP_VID_TIMING + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DP_REG(mmDP_VID_TIMING);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- static void set_tmds_stream_attributes(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	const struct dc_crtc_timing *timing,
- 	bool is_dvi
- 	)
- {
--	enum engine_id engine = enc->id;
--	uint32_t addr = mmDIG_FE_CNTL + fe_engine_offsets[engine];
--	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DIG_REG(mmDIG_FE_CNTL);
-+	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	switch (timing->pixel_encoding) {
- 	case PIXEL_ENCODING_YCBCR422:
-@@ -566,16 +566,16 @@ static void set_tmds_stream_attributes(
- 		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
- 		break;
- 	}
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- static void set_dp_stream_attributes(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	const struct dc_crtc_timing *timing)
- {
--	enum engine_id engine = enc->id;
--	const uint32_t addr = mmDP_PIXEL_FORMAT + fe_engine_offsets[engine];
--	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	const uint32_t addr = DP_REG(mmDP_PIXEL_FORMAT);
-+	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	/* set pixel encoding */
- 	switch (timing->pixel_encoding) {
-@@ -654,20 +654,20 @@ static void set_dp_stream_attributes(
- 	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_DYN_RANGE);
- 	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_YCBCR_RANGE);
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- static void setup_hdmi(
--	struct stream_encoder *enc,
-+	struct dce110_stream_encoder *enc110,
- 	const struct dc_crtc_timing *timing)
- {
--	enum engine_id engine = enc->id;
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t output_pixel_clock = timing->pix_clk_khz;
- 	uint32_t value;
- 	uint32_t addr;
- 
--	addr = mmHDMI_CONTROL + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmHDMI_CONTROL);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_PACKET_GEN_VERSION);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_KEEPOUT_MODE);
- 	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE);
-@@ -761,71 +761,89 @@ static void setup_hdmi(
- 			HDMI_CLOCK_CHANNEL_RATE);
- 	}
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmHDMI_VBI_PACKET_CONTROL + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmHDMI_VBI_PACKET_CONTROL);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND);
- 
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* following belongs to audio */
--	addr = mmHDMI_INFOFRAME_CONTROL0 + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		HDMI_INFOFRAME_CONTROL0,
- 		HDMI_AUDIO_INFO_SEND);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmAFMT_INFOFRAME_CONTROL0 + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmAFMT_INFOFRAME_CONTROL0);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		AFMT_INFOFRAME_CONTROL0,
- 		AFMT_AUDIO_INFO_UPDATE);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmHDMI_INFOFRAME_CONTROL1 + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL1);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		VBI_LINE_0 + 2,
- 		HDMI_INFOFRAME_CONTROL1,
- 		HDMI_AUDIO_INFO_LINE);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
--	addr = mmHDMI_GC + fe_engine_offsets[engine];
--	value = dal_read_reg(enc->ctx, addr);
-+	addr = DIG_REG(mmHDMI_GC);
-+	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, HDMI_GC, HDMI_GC_AVMUTE);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- }
- 
--struct stream_encoder *dce110_stream_encoder_create(
--	struct stream_enc_init_data *init)
-+bool dce110_stream_encoder_construct(
-+	struct dce110_stream_encoder *enc110,
-+	struct dc_context *ctx,
-+	struct bios_parser *bp,
-+	enum engine_id eng_id)
- {
--	struct stream_encoder *enc =
--		dc_service_alloc(init->ctx, sizeof(struct stream_encoder));
-+	if (eng_id > ARRAY_SIZE(reg_offsets))
-+		return false;
-+
-+	enc110->base.ctx = ctx;
-+	enc110->base.id = eng_id;
-+	enc110->base.bp = bp;
-+	enc110->offsets = reg_offsets[eng_id];
- 
--	if (!enc)
--		goto enc_create_fail;
-+	return true;
-+}
- 
--	construct(enc, init);
-+struct stream_encoder *dce110_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx,
-+	struct bios_parser *bp)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
- 
--	return enc;
-+	if (!enc110)
-+		return NULL;
-+	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id))
-+		return &enc110->base;
- 
--enc_create_fail:
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, enc110);
- 	return NULL;
- }
- 
- void dce110_stream_encoder_destroy(struct stream_encoder **enc)
- {
--	dc_service_free((*enc)->ctx, *enc);
-+	dc_service_free((*enc)->ctx, TO_DCE110_STREAM_ENC(*enc));
- 	*enc = NULL;
- }
- 
-@@ -834,7 +852,9 @@ void dce110_stream_encoder_dp_set_stream_attribute(
- 	struct stream_encoder *enc,
- 	struct dc_crtc_timing *crtc_timing)
- {
--	set_dp_stream_attributes(enc, crtc_timing);
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+
-+	set_dp_stream_attributes(enc110, crtc_timing);
- }
- 
- /* setup stream encoder in hdmi mode */
-@@ -843,10 +863,11 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	struct dc_crtc_timing *crtc_timing,
- 	bool enable_audio)
- {
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
- 	struct bp_encoder_control cntl = {0};
- 
- 	cntl.action = ENCODER_CONTROL_SETUP;
--	cntl.engine_id = enc->id;
-+	cntl.engine_id = enc110->base.id;
- 	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- 	cntl.enable_dp_audio = enable_audio;
- 	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-@@ -858,10 +879,10 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 		return;
- 
- 
--	set_tmds_stream_attributes(enc, crtc_timing, false);
-+	set_tmds_stream_attributes(enc110, crtc_timing, false);
- 
- 	/* setup HDMI engine */
--	setup_hdmi(enc, crtc_timing);
-+	setup_hdmi(enc110, crtc_timing);
- }
- 
- /* setup stream encoder in dvi mode */
-@@ -870,10 +891,11 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 	struct dc_crtc_timing *crtc_timing,
- 	bool is_dual_link)
- {
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
- 	struct bp_encoder_control cntl = {0};
- 
- 	cntl.action = ENCODER_CONTROL_SETUP;
--	cntl.engine_id = enc->id;
-+	cntl.engine_id = enc110->base.id;
- 	cntl.signal = is_dual_link ?
- 		SIGNAL_TYPE_DVI_DUAL_LINK :
- 		SIGNAL_TYPE_DVI_SINGLE_LINK;
-@@ -884,31 +906,34 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
- 	if (dal_bios_parser_encoder_control(
--			enc->bp, &cntl) != BP_RESULT_OK)
-+			enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
--	set_tmds_stream_attributes(enc, crtc_timing, true);
-+	set_tmds_stream_attributes(enc110, crtc_timing, true);
- }
- 
- void dce110_stream_encoder_set_mst_bandwidth(
- 	struct stream_encoder *enc,
- 	struct fixed31_32 avg_time_slots_per_mtp)
- {
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t field;
-+	uint32_t value;
-+	uint32_t retries = 0;
- 	uint32_t x = dal_fixed31_32_floor(
- 		avg_time_slots_per_mtp);
--
- 	uint32_t y = dal_fixed31_32_ceil(
- 		dal_fixed31_32_shl(
- 			dal_fixed31_32_sub_int(
- 				avg_time_slots_per_mtp,
- 				x),
- 			26));
--	enum engine_id engine = enc->id;
- 
- 	{
--		const uint32_t addr = mmDP_MSE_RATE_CNTL +
--				fe_engine_offsets[engine];
--		uint32_t value = dal_read_reg(enc->ctx, addr);
-+		addr = DP_REG(mmDP_MSE_RATE_CNTL);
-+		value = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -922,20 +947,17 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 			DP_MSE_RATE_CNTL,
- 			DP_MSE_RATE_Y);
- 
--		dal_write_reg(enc->ctx, addr, value);
-+		dal_write_reg(ctx, addr, value);
- 	}
- 
- 	/* wait for update to be completed on the link */
- 	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
- 	/* is reset to 0 (not pending) */
- 	{
--		const uint32_t addr = mmDP_MSE_RATE_UPDATE +
--			fe_engine_offsets[engine];
--		uint32_t value, field;
--		uint32_t retries = 0;
-+		addr = DP_REG(mmDP_MSE_RATE_UPDATE);
- 
- 		do {
--			value = dal_read_reg(enc->ctx, addr);
-+			value = dal_read_reg(ctx, addr);
- 
- 			field = get_reg_field_value(
- 					value,
-@@ -946,7 +968,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
- 				break;
- 
--			dc_service_delay_in_microseconds(enc->ctx, 10);
-+			dc_service_delay_in_microseconds(ctx, 10);
- 
- 			++retries;
- 		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-@@ -957,25 +979,26 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 	struct stream_encoder *enc,
- 	const struct encoder_info_frame *info_frame)
- {
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+
- 	update_avi_info_packet(
--		enc,
-+		enc110,
- 		&info_frame->avi);
--	update_hdmi_info_packet(enc, 0, &info_frame->vendor);
--	update_hdmi_info_packet(enc, 1, &info_frame->gamut);
--	update_hdmi_info_packet(enc, 2, &info_frame->spd);
-+	update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
-+	update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
-+	update_hdmi_info_packet(enc110, 2, &info_frame->spd);
- }
- 
- void dce110_stream_encoder_stop_hdmi_info_packets(
- 	struct stream_encoder *enc)
- {
--	struct dc_context *ctx = enc->ctx;
--	enum engine_id engine = enc->id;
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
--	uint32_t offset = fe_engine_offsets[engine];
- 
- 	/* stop generic packets 0 & 1 on HDMI */
--	addr = mmHDMI_GENERIC_PACKET_CONTROL0 + offset;
-+	addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL0);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -1013,7 +1036,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* stop generic packets 2 & 3 on HDMI */
--	addr = mmHDMI_GENERIC_PACKET_CONTROL1 + offset;
-+	addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL1);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -1051,7 +1074,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* stop AVI packet on HDMI */
--	addr = mmHDMI_INFOFRAME_CONTROL0 + offset;
-+	addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -1072,17 +1095,18 @@ void dce110_stream_encoder_update_dp_info_packets(
- 	struct stream_encoder *enc,
- 	const struct encoder_info_frame *info_frame)
- {
--	update_dp_info_packet(enc, 0, &info_frame->vsc);
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+
-+	update_dp_info_packet(enc110, 0, &info_frame->vsc);
- }
- 
- void dce110_stream_encoder_stop_dp_info_packets(
- 	struct stream_encoder *enc)
- {
- 	/* stop generic packets on DP */
--	struct dc_context *ctx = enc->ctx;
--	enum engine_id engine = enc->id;
--	uint32_t offset = fe_engine_offsets[engine];
--	const uint32_t addr = mmDP_SEC_CNTL + offset;
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
-@@ -1110,9 +1134,10 @@ void dce110_stream_encoder_stop_dp_info_packets(
- void dce110_stream_encoder_dp_blank(
- 	struct stream_encoder *enc)
- {
--	enum engine_id engine = enc->id;
--	const uint32_t addr = mmDP_VID_STREAM_CNTL + fe_engine_offsets[engine];
--	uint32_t value = dal_read_reg(enc->ctx, addr);
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DP_REG(mmDP_VID_STREAM_CNTL);
-+	uint32_t value = dal_read_reg(ctx, addr);
- 	uint32_t retries = 0;
- 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
- 
-@@ -1137,14 +1162,14 @@ void dce110_stream_encoder_dp_blank(
- 
- 	/* disable DP stream */
- 	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
--	dal_write_reg(enc->ctx, addr, value);
-+	dal_write_reg(ctx, addr, value);
- 
- 	/* the encoder stops sending the video stream
- 	 * at the start of the vertical blanking.
- 	 * Poll for DP_VID_STREAM_STATUS == 0 */
- 
- 	do {
--		value = dal_read_reg(enc->ctx, addr);
-+		value = dal_read_reg(ctx, addr);
- 
- 		if (!get_reg_field_value(
- 			value,
-@@ -1152,7 +1177,7 @@ void dce110_stream_encoder_dp_blank(
- 			DP_VID_STREAM_STATUS))
- 			break;
- 
--		dc_service_delay_in_microseconds(enc->ctx, 10);
-+		dc_service_delay_in_microseconds(ctx, 10);
- 
- 		++retries;
- 	} while (retries < max_retries);
-@@ -1163,7 +1188,7 @@ void dce110_stream_encoder_dp_blank(
- 	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
- 	 * complete, stream status will be stuck in video stream enabled state,
- 	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
--	dp_steer_fifo_reset(enc, true);
-+	dp_steer_fifo_reset(enc110, true);
- }
- 
- /* output video stream to link encoder */
-@@ -1171,6 +1196,8 @@ void dce110_stream_encoder_dp_unblank(
- 	struct stream_encoder *enc,
- 	const struct encoder_unblank_param *param)
- {
-+	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+
- 	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
- 		uint32_t n_vid = 0x8000;
- 		uint32_t m_vid;
-@@ -1187,9 +1214,9 @@ void dce110_stream_encoder_dp_unblank(
- 
- 		m_vid = (uint32_t) m_vid_l;
- 
--		setup_vid_stream(enc, m_vid, n_vid);
-+		setup_vid_stream(enc110, m_vid, n_vid);
- 	}
- 
--	unblank_dp_output(enc);
-+	unblank_dp_output(enc110);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index a520691..8d859a9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -26,14 +26,25 @@
- #ifndef __DC_STREAM_ENCODER_DCE110_H__
- #define __DC_STREAM_ENCODER_DCE110_H__
- 
--struct stream_enc_init_data {
--	enum engine_id stream_engine_id;
--	struct bios_parser *bp;
--	struct dc_context *ctx;
-+#include "inc/stream_encoder.h"
-+
-+#define TO_DCE110_STREAM_ENC(stream_encoder)\
-+	container_of(stream_encoder, struct dce110_stream_encoder, base)
-+
-+struct dce110_stream_enc_offsets {
-+	uint32_t dig_offset;
-+	uint32_t dp_offset;
-+};
-+
-+struct dce110_stream_encoder {
-+	struct stream_encoder base;
-+	struct dce110_stream_enc_offsets offsets;
- };
- 
- struct stream_encoder *dce110_stream_encoder_create(
--	struct stream_enc_init_data *init);
-+	enum engine_id eng_id,
-+	struct dc_context *ctx,
-+	struct bios_parser *bp);
- 
- void dce110_stream_encoder_destroy(struct stream_encoder **enc);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index b636a9c..ecc1cdc 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -64,7 +64,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 
- /********* core_stream ************/
- #include "grph_object_id.h"
--#include "encoder_interface.h"
-+#include "encoder_types.h"
- #include "clock_source_interface.h"
- #include "audio_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 99a0458..c4151c1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -90,10 +90,10 @@ struct hw_sequencer_funcs {
- 
- 	void (*encoder_destroy)(struct link_encoder **enc);
- 
--	enum encoder_result (*encoder_power_up)(
-+	enum dc_encoder_result (*encoder_power_up)(
- 					struct link_encoder *enc);
- 
--	enum encoder_result (*encoder_enable_output)(
-+	enum dc_encoder_result (*encoder_enable_output)(
- 					struct link_encoder *enc,
- 					const struct link_settings *link_settings,
- 					enum engine_id engine,
-@@ -102,7 +102,7 @@ struct hw_sequencer_funcs {
- 					enum dc_color_depth color_depth,
- 					uint32_t pixel_clock);
- 
--	enum encoder_result (*encoder_disable_output)(
-+	enum dc_encoder_result (*encoder_disable_output)(
- 					struct link_encoder *enc,
- 					enum signal_type signal);
- 
-@@ -110,7 +110,7 @@ struct hw_sequencer_funcs {
- 					struct link_encoder *enc,
- 					const struct encoder_set_dp_phy_pattern_param *param);
- 
--	enum encoder_result (*encoder_dp_set_lane_settings)(
-+	enum dc_encoder_result (*encoder_dp_set_lane_settings)(
- 					struct link_encoder *enc,
- 					const struct link_training_settings *link_settings);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-new file mode 100644
-index 0000000..8b19b00
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -0,0 +1,28 @@
-+/*
-+ * link_encoder.h
-+ *
-+ *  Created on: Oct 6, 2015
-+ *      Author: yonsun
-+ */
-+
-+#ifndef LINK_ENCODER_H_
-+#define LINK_ENCODER_H_
-+
-+struct link_enc_status {
-+	int dummy; /*TODO*/
-+};
-+struct link_encoder {
-+	struct adapter_service *adapter_service;
-+	int32_t aux_channel_offset;
-+	struct dc_context *ctx;
-+	struct graphics_object_id id;
-+	struct graphics_object_id connector;
-+	uint32_t input_signals;
-+	uint32_t output_signals;
-+	enum engine_id preferred_engine;
-+	struct encoder_feature_support features;
-+	enum transmitter transmitter;
-+	enum hpd_source_id hpd_source;
-+};
-+
-+#endif /* LINK_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-new file mode 100644
-index 0000000..d2da14a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-@@ -0,0 +1,18 @@
-+/*
-+ * stream_encoder.h
-+ *
-+ */
-+
-+#ifndef STREAM_ENCODER_H_
-+#define STREAM_ENCODER_H_
-+
-+#include "include/encoder_types.h"
-+#include "include/bios_parser_interface.h"
-+
-+struct stream_encoder {
-+	struct dc_context *ctx;
-+	struct bios_parser *bp;
-+	enum engine_id id;
-+};
-+
-+#endif /* STREAM_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_types.h b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-index e32498d..c267d30 100644
---- a/drivers/gpu/drm/amd/dal/include/encoder_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-@@ -31,6 +31,16 @@
- #include "hw_sequencer_types.h"
- #include "link_service_types.h"
- 
-+struct encoder_init_data {
-+	struct adapter_service *adapter_service;
-+	enum channel_id channel;
-+	struct graphics_object_id connector;
-+	enum hpd_source_id hpd_source;
-+	/* TODO: in DAL2, here was pointer to EventManagerInterface */
-+	struct graphics_object_id encoder;
-+	struct dc_context *ctx;
-+};
-+
- struct encoder_context {
- 	/*
- 	 * HW programming context
-diff --git a/drivers/gpu/drm/amd/dal/include/link_encoder_types.h b/drivers/gpu/drm/amd/dal/include/link_encoder_types.h
-deleted file mode 100644
-index 2a59902..0000000
---- a/drivers/gpu/drm/amd/dal/include/link_encoder_types.h
-+++ /dev/null
-@@ -1,32 +0,0 @@
--/*
-- * link_encoder_types.h
-- *
-- *  Created on: Oct 6, 2015
-- *      Author: yonsun
-- */
--
--#ifndef DRIVERS_GPU_DRM_AMD_DAL_DEV_INCLUDE_LINK_ENCODER_TYPES_H_
--#define DRIVERS_GPU_DRM_AMD_DAL_DEV_INCLUDE_LINK_ENCODER_TYPES_H_
--
--#include "encoder_interface.h"
--
--struct link_enc_status {
--	int dummy; /*TODO*/
--};
--struct link_encoder {
--	struct adapter_service *adapter_service;
--	int32_t be_engine_offset;
--	int32_t aux_channel_offset;
--	int32_t transmitter_offset;
--	struct dc_context *ctx;
--	struct graphics_object_id id;
--	struct graphics_object_id connector;
--	uint32_t input_signals;
--	uint32_t output_signals;
--	enum engine_id preferred_engine;
--	struct encoder_feature_support features;
--	enum transmitter transmitter;
--	enum hpd_source_id hpd_source;
--};
--
--#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_INCLUDE_LINK_ENCODER_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h b/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-deleted file mode 100644
-index c0bc656..0000000
---- a/drivers/gpu/drm/amd/dal/include/stream_encoder_types.h
-+++ /dev/null
-@@ -1,16 +0,0 @@
--/*
-- * stream_encoder_types.h
-- *
-- */
--#include "encoder_interface.h"
--
--#ifndef STREAM_ENCODER_TYPES_H_
--#define STREAM_ENCODER_TYPES_H_
--
--struct stream_encoder {
--	enum engine_id id;
--	struct bios_parser *bp;
--	struct dc_context *ctx;
--};
--
--#endif /* STREAM_ENCODER_TYPES_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0550-drm-amd-dal-clean-DP-MST-payload-alloc-and-dealloc-f.patch b/common/recipes-kernel/linux/files/0550-drm-amd-dal-clean-DP-MST-payload-alloc-and-dealloc-f.patch
deleted file mode 100644
index 1b36a087..00000000
--- a/common/recipes-kernel/linux/files/0550-drm-amd-dal-clean-DP-MST-payload-alloc-and-dealloc-f.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From a039d976c4ee405b2e410e6e663223b262fa931e Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Tue, 1 Dec 2015 11:43:19 -0500
-Subject: [PATCH 0550/1110] drm/amd/dal: clean DP MST payload alloc and dealloc
- for new stream before link enable
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 11 +++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  5 ++--
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 33 ++++++++++++++++------
- 3 files changed, 33 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 0af5005..f0719e9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -890,6 +890,9 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 		stream->stream_enc->id,
- 		&link_settings);
- 
-+	if (status == DC_ERROR_UNEXPECTED)
-+		return status;
-+
- 	panel_mode = dp_get_panel_mode(link);
- 	dpcd_configure_panel_mode(link, panel_mode);
- 
-@@ -914,15 +917,15 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- 	bool already_enabled = false;
- 	int i;
- 
--
- 	for (i = 0; i < link->enabled_stream_count; i++) {
- 		if (link->enabled_streams[i] == stream)
- 			already_enabled = true;
- 	}
- 
--	/* TODO MST link shared by stream. counter? */
--	if (!already_enabled)
-+	if (!already_enabled && link->enabled_stream_count < MAX_SINKS_PER_LINK)
- 		link->enabled_streams[link->enabled_stream_count++] = stream;
-+	else if (link->enabled_stream_count >= MAX_SINKS_PER_LINK)
-+		return DC_ERROR_UNEXPECTED;
- 
- 	/* sink signal type after MST branch is MST. Multiple MST sinks
- 	 * share one link. Link DP PHY is enable or training only once.
-@@ -1014,7 +1017,7 @@ enum dc_status core_link_enable(struct core_stream *stream)
- 		break;
- 	}
- 
--	if (stream->audio) {
-+	if (stream->audio && status == DC_OK) {
- 		/* notify audio driver for audio modes of monitor */
- 		dal_audio_enable_azalia_audio_jack_presence(stream->audio,
- 				stream->stream_enc->id);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 8ef4674..7961a4e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -46,8 +46,6 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
- 			sizeof(state));
- }
- 
--
--/* TODO: HBR2 need raise clock for DP link training */
- enum dc_status dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
-@@ -66,7 +64,8 @@ enum dc_status dp_enable_link_phy(
- 					0) != ENCODER_RESULT_OK)
- 		status = DC_ERROR_UNEXPECTED;
- 
--	dp_receiver_power_ctrl(link, true);
-+	if (status == DC_OK)
-+		dp_receiver_power_ctrl(link, true);
- 
- 	return status;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 9c0bcbb..046ab0c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -783,10 +783,10 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	struct fixed31_32 avg_time_slots_per_mtp;
- 	uint8_t cur_stream_payload_idx;
- 
--	if (stream_encoder->id == ENGINE_ID_UNKNOWN) {
--		/* TODO ASSERT */
--		return DC_ERROR_UNEXPECTED;
--	}
-+	/* enable_link_dp_mst already check link->enabled_stream_count
-+	 * and stream is in link->stream[]. This is called during set mode,
-+	 * stream_enc is available.
-+	 */
- 
- 	/* get calculate VC payload for stream: stream_alloc */
- 	dc_helpers_dp_mst_write_payload_allocation_table(
-@@ -831,11 +831,24 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
- 	struct dp_mst_stream_allocation_table table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
-+	uint8_t i;
- 
--	if (stream_encoder->id == ENGINE_ID_UNKNOWN) {
--		/* TODO ASSERT */
--		return DC_ERROR_UNEXPECTED;
-+	/* deallocate_mst_payload is called before disable link. When mode or
-+	 * disable/enable monitor, new stream is created which is not in link
-+	 * stream[] yet. For this, payload is not allocated yet, so de-alloc
-+	 * should not done. For new mode set, map_resources will get engine
-+	 * for new stream, so stream_enc->id should be validated until here.
-+	 */
-+	if (link->enabled_stream_count == 0)
-+		return DC_OK;
-+
-+	for (i = 0; i < link->enabled_stream_count; i++) {
-+		if (link->enabled_streams[i] == stream)
-+			break;
- 	}
-+	/* stream is not in link stream list */
-+	if (i == link->enabled_stream_count)
-+		return DC_OK;
- 
- 	/* slot X.Y */
- 	dce110_stream_encoder_set_mst_bandwidth(
-@@ -862,9 +875,7 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 			&stream->sink->public,
- 			false);
- 
--
- 	return DC_OK;
--
- }
- 
- static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
-@@ -1009,6 +1020,10 @@ static void power_down_encoders(struct validate_context *context)
- 	for (i = 0; i < context->target_count; i++) {
- 		target = context->targets[i];
- 		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
-+
-+		if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+			deallocate_mst_payload(stream);
-+
- 		core_link_disable(stream);
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0551-drm-amd-dal-Don-t-access-const-sink.patch b/common/recipes-kernel/linux/files/0551-drm-amd-dal-Don-t-access-const-sink.patch
deleted file mode 100644
index aa39901e..00000000
--- a/common/recipes-kernel/linux/files/0551-drm-amd-dal-Don-t-access-const-sink.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 00cefb514cdb0602a9b7279fc564e2df97c60183 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 1 Dec 2015 11:11:01 -0500
-Subject: [PATCH 0551/1110] drm/amd/dal: Don't access const sink
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 9 ++++-----
- 1 file changed, 4 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index fded924..01e961a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -849,11 +849,10 @@ void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink)
- 			link->sink[i] = NULL;
- 
- 			/* shrink array to remove empty place */
--			dc_service_memmove(
--				&link->sink[i],
--				&link->sink[i + 1],
--				(link->sink_count - i - 1) *
--				sizeof(link->sink[i]));
-+			while (i < link->sink_count - 1) {
-+				link->sink[i] = link->sink[i+1];
-+				i++;
-+			}
- 
- 			link->sink_count--;
- 			return;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0552-drm-amd-dal-Fix-minor-fomatting-issue-and-dependenci.patch b/common/recipes-kernel/linux/files/0552-drm-amd-dal-Fix-minor-fomatting-issue-and-dependenci.patch
deleted file mode 100644
index ba9ddb38..00000000
--- a/common/recipes-kernel/linux/files/0552-drm-amd-dal-Fix-minor-fomatting-issue-and-dependenci.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From 055597f0f621a9a8fbd6775150531a1337a0ff4d Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Tue, 1 Dec 2015 13:00:00 -0500
-Subject: [PATCH 0552/1110] drm/amd/dal: Fix minor fomatting issue and
- dependencies
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c   | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c       | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 5 +++--
- drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c   | 4 ++--
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h             | 2 ++
- 5 files changed, 11 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 4381a94..c047bcb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1093,7 +1093,7 @@ static bool validate_wireless_output(
- 	return false;
- }
- 
--bool dce110_link_encoder_construct(
-+static bool construct(
- 	struct dce110_link_encoder *enc110,
- 	const struct encoder_init_data *init_data)
- {
-@@ -1225,7 +1225,7 @@ struct link_encoder *dce110_link_encoder_create(
- 	if (!enc110)
- 		return NULL;
- 
--	if (dce110_link_encoder_construct(enc110, init))
-+	if (construct(enc110, init))
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 77fbbe4..6ad681b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -24,8 +24,8 @@
-  */
- #include "dc_services.h"
- 
--#include "link_encoder_types.h"
--#include "stream_encoder_types.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
- 
- #include "resource.h"
- #include "dce_base/dce_base_resource.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 8f5560a..4bf3128 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -806,7 +806,7 @@ static void setup_hdmi(
- 
- }
- 
--bool dce110_stream_encoder_construct(
-+static bool construct(
- 	struct dce110_stream_encoder *enc110,
- 	struct dc_context *ctx,
- 	struct bios_parser *bp,
-@@ -833,7 +833,8 @@ struct stream_encoder *dce110_stream_encoder_create(
- 
- 	if (!enc110)
- 		return NULL;
--	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id))
-+
-+	if (construct(enc110, ctx, bp, eng_id))
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-index 06047ab..ba74ff5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -28,8 +28,8 @@
- 
- #include "adjustment_types.h"
- #include "set_mode_types.h"
--#include "stream_encoder_types.h"
--#include "link_encoder_types.h"
-+#include "stream_encoder.h"
-+#include "link_encoder.h"
- 
- #include "resource.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index 8b19b00..d4a0d24 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -8,6 +8,8 @@
- #ifndef LINK_ENCODER_H_
- #define LINK_ENCODER_H_
- 
-+#include "include/encoder_types.h"
-+
- struct link_enc_status {
- 	int dummy; /*TODO*/
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0553-drm-amd-dal-Fix-Offset-bug.patch b/common/recipes-kernel/linux/files/0553-drm-amd-dal-Fix-Offset-bug.patch
deleted file mode 100644
index dbc248ec..00000000
--- a/common/recipes-kernel/linux/files/0553-drm-amd-dal-Fix-Offset-bug.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 412582cef9d18b9cc43a75ae18eccbf539e9f6b8 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Tue, 1 Dec 2015 14:14:01 -0500
-Subject: [PATCH 0553/1110] drm/amd/dal: Fix Offset bug
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c   | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index c047bcb..cf6da5a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -100,7 +100,7 @@ static const struct dce110_link_enc_offsets reg_offsets[] = {
- },
- {
- 	.dig_offset = (mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+	.dp_offset = (mmDP2_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
- }
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 4bf3128..a07758f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -46,7 +46,7 @@ static const struct dce110_stream_enc_offsets reg_offsets[] = {
- },
- {
- 	.dig_offset = (mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
-+	.dp_offset = (mmDP2_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
- }
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0554-drm-amd-dal-Treat-warnings-as-errors.patch b/common/recipes-kernel/linux/files/0554-drm-amd-dal-Treat-warnings-as-errors.patch
deleted file mode 100644
index af776d2b..00000000
--- a/common/recipes-kernel/linux/files/0554-drm-amd-dal-Treat-warnings-as-errors.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From cb5336555b89e440bad0c786ef666d9006e6dd97 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 1 Dec 2015 14:08:19 -0500
-Subject: [PATCH 0554/1110] drm/amd/dal: Treat warnings as errors
-
-Also fix any existing warnings
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/Makefile                      | 2 ++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c | 2 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c     | 2 +-
- 3 files changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile
-index bdf5d18..d5db32e 100644
---- a/drivers/gpu/drm/amd/dal/Makefile
-+++ b/drivers/gpu/drm/amd/dal/Makefile
-@@ -5,6 +5,8 @@
- 
- AMDDALPATH = $(RELATIVE_AMD_DAL_PATH)
- 
-+subdir-ccflags-y += -Werror
-+
- subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include -DDAL_CZ_BRINGUP
- 
- subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 5b780e1..6b70a41 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -183,7 +183,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	int bpp;
- 	int pbn = 0;
- 	uint8_t i;
--	uint8_t vcid;
-+	uint8_t vcid = 0;
- 	bool find_stream_for_sink;
- 
- 	aconnector = get_connector_for_sink(dev, sink);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index 9491fd0..05a0053 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -466,7 +466,7 @@ void amdgpu_dm_irq_register_timer(
- 	queue_delayed_work(adev->dm.timer_workqueue, &handler_data->d_work,
- 			jf_delay);
- 
--	DRM_DEBUG_KMS("DM_IRQ: added handler:%p with micro_sec_interval=%llu\n",
-+	DRM_DEBUG_KMS("DM_IRQ: added handler:%p with micro_sec_interval=%u\n",
- 			handler_data, int_params->micro_sec_interval);
- 	return;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0555-drm-amd-dal-Simplify-return-value-for-HW-programming.patch b/common/recipes-kernel/linux/files/0555-drm-amd-dal-Simplify-return-value-for-HW-programming.patch
deleted file mode 100644
index c261c9f8..00000000
--- a/common/recipes-kernel/linux/files/0555-drm-amd-dal-Simplify-return-value-for-HW-programming.patch
+++ /dev/null
@@ -1,469 +0,0 @@
-From e329df58f0107375dd3d19c4405113a25e884912 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Tue, 1 Dec 2015 15:04:11 -0500
-Subject: [PATCH 0555/1110] drm/amd/dal: Simplify return value for HW
- programming
-
-Only OK & ERROR used.  Replace with bool.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  8 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  4 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  8 ---
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 58 +++++++++++-----------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    | 18 +++----
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  5 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  8 +--
- 8 files changed, 51 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 01e961a..14e10b9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -162,7 +162,7 @@ static void init_hw(struct dc *dc)
- 		 * required signal (which may be different from the
- 		 * default signal on connector). */
- 		struct core_link *link = dc->links[i];
--		if (dc->hwss.encoder_power_up(link->link_enc) != ENCODER_RESULT_OK) {
-+		if (!dc->hwss.encoder_power_up(link->link_enc)) {
- 			dal_error("Failed link encoder power up!\n");
- 			return;
- 		}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index f0719e9..58eac92 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -977,14 +977,14 @@ static enum dc_status enable_link_hdmi(struct core_stream *stream)
- 		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- 					? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
- 
--	if (link->ctx->dc->hwss.encoder_enable_output(
-+	if (!link->ctx->dc->hwss.encoder_enable_output(
- 			stream->sink->link->link_enc,
- 			&stream->sink->link->cur_link_settings,
- 			stream->stream_enc->id,
- 			dal_clock_source_get_id(stream->clock_source),
- 			stream->signal,
- 			stream->public.timing.display_color_depth,
--			stream->public.timing.pix_clk_khz) != ENCODER_RESULT_OK)
-+			stream->public.timing.pix_clk_khz))
- 		status = DC_ERROR_UNEXPECTED;
- 
- 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-@@ -1052,8 +1052,8 @@ enum dc_status core_link_disable(struct core_stream *stream)
- 		}
- 	}
- 
--	else if (ENCODER_RESULT_OK != dc->hwss.encoder_disable_output(
--					stream->sink->link->link_enc, stream->signal))
-+	else if (!dc->hwss.encoder_disable_output(
-+				stream->sink->link->link_enc, stream->signal))
- 		status = DC_ERROR_UNEXPECTED;
- 
- 	return status;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 7961a4e..054b0a3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -54,14 +54,14 @@ enum dc_status dp_enable_link_phy(
- {
- 	enum dc_status status = DC_OK;
- 
--	if (link->dc->hwss.encoder_enable_output(
-+	if (!link->dc->hwss.encoder_enable_output(
- 					link->link_enc,
- 					link_settings,
- 					engine,
- 					CLOCK_SOURCE_ID_EXTERNAL,
- 					signal,
- 					COLOR_DEPTH_UNDEFINED,
--					0) != ENCODER_RESULT_OK)
-+					0))
- 		status = DC_ERROR_UNEXPECTED;
- 
- 	if (status == DC_OK)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index db7608e..b6526e9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -672,14 +672,6 @@ struct dc_csc_adjustments {
- 	struct fixed31_32 hue;
- };
- 
--enum dc_encoder_result {
--	ENCODER_RESULT_OK,
--	ENCODER_RESULT_ERROR,
--	ENCODER_RESULT_NOBANDWIDTH,
--	ENCODER_RESULT_SINKCONNECTIVITYCHANGED
--#endif
--};
--
- #include "dc_temp.h"
- 
- #endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index cf6da5a..63e8c47 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -640,7 +640,7 @@ static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
-  * @brief
-  * eDP only. Control the power of the eDP panel.
-  */
--static enum dc_encoder_result link_encoder_edp_power_control(
-+static bool link_encoder_edp_power_control(
- 	struct dce110_link_encoder *enc110,
- 	bool power_up)
- {
-@@ -651,7 +651,7 @@ static enum dc_encoder_result link_encoder_edp_power_control(
- 	if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
- 		CONNECTOR_ID_EDP) {
- 		BREAK_TO_DEBUGGER();
--		return ENCODER_RESULT_ERROR;
-+		return false;
- 	}
- 
- 	if ((power_up && !is_panel_powered_on(enc110)) ||
-@@ -694,7 +694,7 @@ static enum dc_encoder_result link_encoder_edp_power_control(
- 				__func__, (power_up ? "On":"Off"));
- 	}
- 
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- /*
-@@ -810,7 +810,7 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
-  * @brief
-  * eDP only. Control the backlight of the eDP panel
-  */
--static enum dc_encoder_result link_encoder_edp_backlight_control(
-+static bool link_encoder_edp_backlight_control(
- 	struct dce110_link_encoder *enc110,
- 	bool enable)
- {
-@@ -820,7 +820,7 @@ static enum dc_encoder_result link_encoder_edp_backlight_control(
- 	if (dal_graphics_object_id_get_connector_id(enc110->base.connector)
- 		!= CONNECTOR_ID_EDP) {
- 		BREAK_TO_DEBUGGER();
--		return ENCODER_RESULT_ERROR;
-+		return false;
- 	}
- 
- 	if (enable && is_panel_backlight_on(enc110)) {
-@@ -829,7 +829,7 @@ static enum dc_encoder_result link_encoder_edp_backlight_control(
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: panel already powered up. Do nothing.\n",
- 				__func__);
--		return ENCODER_RESULT_OK;
-+		return true;
- 	}
- 
- 	if (!enable && !is_panel_powered_on(enc110)) {
-@@ -838,7 +838,7 @@ static enum dc_encoder_result link_encoder_edp_backlight_control(
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: panel already powered down. Do nothing.\n",
- 				__func__);
--		return ENCODER_RESULT_OK;
-+		return true;
- 	}
- 
- 	/* Send VBIOS command to control eDP panel backlight */
-@@ -875,7 +875,7 @@ static enum dc_encoder_result link_encoder_edp_backlight_control(
- 		dal_adapter_service_get_bios_parser(
- 			enc110->base.adapter_service), &cntl);
- 
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
-@@ -1239,7 +1239,7 @@ void dce110_link_encoder_destroy(struct link_encoder **enc)
- 	*enc = NULL;
- }
- 
--enum dc_encoder_result dce110_link_encoder_validate_output_with_stream(
-+bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream)
- {
-@@ -1282,10 +1282,10 @@ enum dc_encoder_result dce110_link_encoder_validate_output_with_stream(
- 	break;
- 	}
- 
--	return is_valid ? ENCODER_RESULT_OK : ENCODER_RESULT_ERROR;
-+	return is_valid;
- }
- 
--enum dc_encoder_result dce110_link_encoder_power_up(
-+bool dce110_link_encoder_power_up(
- 	struct link_encoder *enc)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-@@ -1314,7 +1314,7 @@ enum dc_encoder_result dce110_link_encoder_power_up(
- 			"%s: Failed to execute VBIOS command table!\n",
- 			__func__);
- 		BREAK_TO_DEBUGGER();
--		return ENCODER_RESULT_ERROR;
-+		return false;
- 	}
- 
- 	if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
-@@ -1342,7 +1342,7 @@ enum dc_encoder_result dce110_link_encoder_power_up(
- 	 * So this routine must be called first. */
- 	hpd_initialize(enc110);
- 
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- void dce110_link_encoder_setup(
-@@ -1386,47 +1386,47 @@ void dce110_link_encoder_setup(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--enum dc_encoder_result dce110_link_encoder_enable_tmds_output(
-+bool dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock)
- {
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
--enum dc_encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
-+bool dce110_link_encoder_enable_dual_link_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock)
- {
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- /* enables DP PHY output */
--enum dc_encoder_result dce110_link_encoder_enable_dp_output(
-+bool dce110_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source)
- {
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- /* enables DP PHY output in MST mode */
--enum dc_encoder_result dce110_link_encoder_enable_dp_mst_output(
-+bool dce110_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source)
- {
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- /*
-  * @brief
-  * Disable transmitter and its encoder
-  */
--enum dc_encoder_result dce110_link_encoder_disable_output(
-+bool dce110_link_encoder_disable_output(
- 	struct link_encoder *enc,
- 	enum signal_type signal)
- {
-@@ -1444,7 +1444,7 @@ enum dc_encoder_result dce110_link_encoder_disable_output(
- 		dal_adapter_service_should_optimize(
- 			enc110->base.adapter_service,
- 			OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
--		return ENCODER_RESULT_OK;
-+		return true;
- 	}
- 	/* Power-down RX and disable GPU PHY should be paired.
- 	 * Disabling PHY without powering down RX may cause
-@@ -1485,10 +1485,10 @@ enum dc_encoder_result dce110_link_encoder_disable_output(
- 				link_enc, false); */
- 	}
- 
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
--enum dc_encoder_result dce110_link_encoder_dp_set_lane_settings(
-+bool dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings)
- {
-@@ -1499,7 +1499,7 @@ enum dc_encoder_result dce110_link_encoder_dp_set_lane_settings(
- 
- 	if (!link_settings) {
- 		BREAK_TO_DEBUGGER();
--		return ENCODER_RESULT_ERROR;
-+		return false;
- 	}
- 
- 	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
-@@ -1537,7 +1537,7 @@ enum dc_encoder_result dce110_link_encoder_dp_set_lane_settings(
- 				enc110->base.adapter_service), &cntl);
- 	}
- 
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- /* set DP PHY test and training patterns */
-@@ -1848,7 +1848,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
-  * Configure digital transmitter and enable both encoder and transmitter
-  * Actual output will be available after calling unblank()
-  */
--enum dc_encoder_result dce110_link_encoder_enable_output(
-+bool dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum engine_id engine,
-@@ -1905,7 +1905,7 @@ enum dc_encoder_result dce110_link_encoder_enable_output(
- 			enc110->base.adapter_service),
- 		&cntl);
- 
--	return ENCODER_RESULT_OK;
-+	return true;
- }
- 
- void dce110_link_encoder_connect_dig_be_to_fe(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 064e50c..334cc1f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -46,14 +46,14 @@ struct link_encoder *dce110_link_encoder_create(
- 
- void dce110_link_encoder_destroy(struct link_encoder **enc);
- 
--enum dc_encoder_result dce110_link_encoder_validate_output_with_stream(
-+bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
- 	const struct core_stream *stream);
- 
- /****************** HW programming ************************/
- 
- /* initialize HW */  /* why do we initialze aux in here? */
--enum dc_encoder_result dce110_link_encoder_power_up(struct link_encoder *enc);
-+bool dce110_link_encoder_power_up(struct link_encoder *enc);
- 
- /* program DIG_MODE in DIG_BE */
- /* TODO can this be combined with enable_output? */
-@@ -63,7 +63,7 @@ void dce110_link_encoder_setup(
- 
- /* enables TMDS PHY output */
- /* TODO: still need depth or just pass in adjusted pixel clock? */
--enum dc_encoder_result dce110_link_encoder_enable_tmds_output(
-+bool dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
-@@ -71,31 +71,31 @@ enum dc_encoder_result dce110_link_encoder_enable_tmds_output(
- 
- /* enables TMDS PHY output */
- /* TODO: still need this or just pass in adjusted pixel clock? */
--enum dc_encoder_result dce110_link_encoder_enable_dual_link_tmds_output(
-+bool dce110_link_encoder_enable_dual_link_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock);
- 
- /* enables DP PHY output */
--enum dc_encoder_result dce110_link_encoder_enable_dp_output(
-+bool dce110_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source);
- 
- /* enables DP PHY output in MST mode */
--enum dc_encoder_result dce110_link_encoder_enable_dp_mst_output(
-+bool dce110_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum clock_source_id clock_source);
- 
- /* disable PHY output */
--enum dc_encoder_result dce110_link_encoder_disable_output(
-+bool dce110_link_encoder_disable_output(
- 	struct link_encoder *enc,
- 	enum signal_type signal);
- 
- /* set DP lane settings */
--enum dc_encoder_result dce110_link_encoder_dp_set_lane_settings(
-+bool dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings);
- 
-@@ -112,7 +112,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level);
- 
--enum dc_encoder_result dce110_link_encoder_enable_output(
-+bool dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 6ad681b..e206802 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -474,10 +474,9 @@ static enum dc_status validate_mapped_resource(
- 				return DC_FAIL_CONTROLLER_VALIDATE;
- 
- 
--			if (dce110_link_encoder_validate_output_with_stream(
-+			if (!dce110_link_encoder_validate_output_with_stream(
- 					link->link_enc,
--					stream)
--							!= ENCODER_RESULT_OK)
-+					stream))
- 				return DC_FAIL_ENC_VALIDATE;
- 
- 			/* TODO: validate audio ASIC caps, encoder */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index c4151c1..e414021 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -90,10 +90,10 @@ struct hw_sequencer_funcs {
- 
- 	void (*encoder_destroy)(struct link_encoder **enc);
- 
--	enum dc_encoder_result (*encoder_power_up)(
-+	bool (*encoder_power_up)(
- 					struct link_encoder *enc);
- 
--	enum dc_encoder_result (*encoder_enable_output)(
-+	bool (*encoder_enable_output)(
- 					struct link_encoder *enc,
- 					const struct link_settings *link_settings,
- 					enum engine_id engine,
-@@ -102,7 +102,7 @@ struct hw_sequencer_funcs {
- 					enum dc_color_depth color_depth,
- 					uint32_t pixel_clock);
- 
--	enum dc_encoder_result (*encoder_disable_output)(
-+	bool (*encoder_disable_output)(
- 					struct link_encoder *enc,
- 					enum signal_type signal);
- 
-@@ -110,7 +110,7 @@ struct hw_sequencer_funcs {
- 					struct link_encoder *enc,
- 					const struct encoder_set_dp_phy_pattern_param *param);
- 
--	enum dc_encoder_result (*encoder_dp_set_lane_settings)(
-+	bool (*encoder_dp_set_lane_settings)(
- 					struct link_encoder *enc,
- 					const struct link_training_settings *link_settings);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0556-drm-amd-dal-expand-dc_services-struct-definition-for.patch b/common/recipes-kernel/linux/files/0556-drm-amd-dal-expand-dc_services-struct-definition-for.patch
deleted file mode 100644
index 848bda16..00000000
--- a/common/recipes-kernel/linux/files/0556-drm-amd-dal-expand-dc_services-struct-definition-for.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 441357226053fd14f5e81126ae1565069194a7ee Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 1 Dec 2015 14:46:51 -0500
-Subject: [PATCH 0556/1110] drm/amd/dal: expand dc_services struct definition
- for notifying pplib of display config
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_services.h | 22 +++++++++++++++++++++-
- 1 file changed, 21 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index 6290885..314ae58 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -37,7 +37,6 @@
- #include "irq_types.h"
- #include "dal_power_interface_types.h"
- 
--
- /* if the pointer is not NULL, the allocated memory is zeroed */
- void *dc_service_alloc(struct dc_context *ctx, uint32_t size);
- 
-@@ -93,6 +92,27 @@ struct dc_pp_display_configuration {
- 	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
- 	bool cpu_pstate_disable;
- 	uint32_t cpu_pstate_separation_time;
-+
-+	uint32_t max_displays;
-+	uint32_t active_displays;
-+
-+	/* 10khz steps */
-+	uint32_t min_memory_clock_khz;
-+	uint32_t min_engine_clock_khz;
-+	uint32_t min_engine_clock_deep_sleep_khz;
-+
-+	uint32_t avail_mclk_switch_time_us;
-+	uint32_t avail_mclk_switch_time_in_disp_active_us;
-+
-+	uint32_t disp_clk_khz;
-+
-+	bool all_displays_in_sync;
-+
-+	/*Controller Index of primary display - used in MCLK SMC switching hang
-+	 * SW Workaround*/
-+	uint32_t crtc_index;
-+	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+	uint32_t line_time_in_us;
- };
- 
- enum dc_pp_clock_type {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0557-drm-amd-dal-Pass-stream-instead-of-sink-to-MST-helpe.patch b/common/recipes-kernel/linux/files/0557-drm-amd-dal-Pass-stream-instead-of-sink-to-MST-helpe.patch
deleted file mode 100644
index 40b81819..00000000
--- a/common/recipes-kernel/linux/files/0557-drm-amd-dal-Pass-stream-instead-of-sink-to-MST-helpe.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From 3d87533c0a0f6f71ad48298c6076e0df2261cfcb Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 1 Dec 2015 16:00:57 -0500
-Subject: [PATCH 0557/1110] drm/amd/dal: Pass stream instead of sink to MST
- helpers
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 18 +++++++++---------
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h                |  6 +++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 12 ++++++------
- 3 files changed, 18 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 6b70a41..053add1 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -165,7 +165,7 @@ static struct amdgpu_connector *get_connector_for_link(
-  */
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
--		const struct dc_sink *sink,
-+		const struct dc_stream *stream,
- 		struct dp_mst_stream_allocation_table *table,
- 		bool enable)
- {
-@@ -186,7 +186,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	uint8_t vcid = 0;
- 	bool find_stream_for_sink;
- 
--	aconnector = get_connector_for_sink(dev, sink);
-+	aconnector = get_connector_for_sink(dev, stream->sink);
- 	crtc = aconnector->base.state->crtc;
- 
- 	if (!crtc)
-@@ -265,7 +265,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 			connector,
- 			&dev->mode_config.connector_list,
- 			head) {
--			const struct dc_sink *dc_sink_connector;
-+			const struct dc_sink *dc_sink;
- 			struct dc_target *dc_target;
- 			uint8_t j;
- 
-@@ -283,7 +283,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 
- 			/* find connector with same vcid as payload */
- 
--			dc_sink_connector = aconnector->dc_sink;
-+			dc_sink = aconnector->dc_sink;
- 
- 			/*
- 			 * find stream to drive this sink
-@@ -295,7 +295,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 
- 			for (j = 0; j < dc_target->stream_count; j++) {
- 				if (dc_target->streams[j]->sink ==
--					dc_sink_connector)
-+					dc_sink)
- 					break;
- 			}
- 
-@@ -335,7 +335,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
-  */
- bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		struct dc_context *ctx,
--		const struct dc_sink *sink)
-+		const struct dc_stream *stream)
- {
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
-@@ -343,7 +343,7 @@ bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 	struct drm_dp_mst_topology_mgr *mst_mgr;
- 	int ret;
- 
--	aconnector = get_connector_for_sink(dev, sink);
-+	aconnector = get_connector_for_sink(dev, stream->sink);
- 
- 	if (!aconnector->mst_port)
- 		return false;
-@@ -360,7 +360,7 @@ bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 
- bool dc_helpers_dp_mst_send_payload_allocation(
- 		struct dc_context *ctx,
--		const struct dc_sink *sink,
-+		const struct dc_stream *stream,
- 		bool enable)
- {
- 	struct amdgpu_device *adev = ctx->driver_context;
-@@ -370,7 +370,7 @@ bool dc_helpers_dp_mst_send_payload_allocation(
- 	struct drm_dp_mst_port *mst_port;
- 	int ret;
- 
--	aconnector = get_connector_for_sink(dev, sink);
-+	aconnector = get_connector_for_sink(dev, stream->sink);
- 
- 	mst_port = aconnector->port;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index 874c839..c0fbb65 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -43,7 +43,7 @@ enum dc_edid_status dc_helpers_parse_edid_caps(
-  */
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
--		const struct dc_sink *sink,
-+		const struct dc_stream *stream,
- 		struct dp_mst_stream_allocation_table *table,
- 		bool enable);
- 
-@@ -52,13 +52,13 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
-  */
- bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		struct dc_context *ctx,
--		const struct dc_sink *sink);
-+		const struct dc_stream *stream);
- /*
-  * Sends ALLOCATE_PAYLOAD message.
-  */
- bool dc_helpers_dp_mst_send_payload_allocation(
- 		struct dc_context *ctx,
--		const struct dc_sink *sink,
-+		const struct dc_stream *stream,
- 		bool enable);
- 
- void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 046ab0c..0be98a8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -791,7 +791,7 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	/* get calculate VC payload for stream: stream_alloc */
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
--		&stream->sink->public,
-+		&stream->public,
- 		&table,
- 		true);
- 
-@@ -803,11 +803,11 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	/* send down message */
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
--			&stream->sink->public);
-+			&stream->public);
- 
- 	dc_helpers_dp_mst_send_payload_allocation(
- 			stream->ctx,
--			&stream->sink->public,
-+			&stream->public,
- 			true);
- 
- 	/* slot X.Y for only current stream */
-@@ -858,7 +858,7 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	/* TODO: which component is responsible for remove payload table? */
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
--		&stream->sink->public,
-+		&stream->public,
- 		&table,
- 		false);
- 
-@@ -868,11 +868,11 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
--			&stream->sink->public);
-+			&stream->public);
- 
- 	dc_helpers_dp_mst_send_payload_allocation(
- 			stream->ctx,
--			&stream->sink->public,
-+			&stream->public,
- 			false);
- 
- 	return DC_OK;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0558-drm-amd-dal-Call-stream-as-it-is-in-payload-table.patch b/common/recipes-kernel/linux/files/0558-drm-amd-dal-Call-stream-as-it-is-in-payload-table.patch
deleted file mode 100644
index 91a2437a..00000000
--- a/common/recipes-kernel/linux/files/0558-drm-amd-dal-Call-stream-as-it-is-in-payload-table.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 3bd6a2f365fb669a0077ec321389c197fee37758 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 1 Dec 2015 16:47:39 -0500
-Subject: [PATCH 0558/1110] drm/amd/dal: Call stream as it is in payload table
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c   | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 9 ++++++---
- drivers/gpu/drm/amd/dal/include/link_service_types.h    | 2 +-
- 3 files changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 053add1..2554e1a 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -304,7 +304,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 				 * find sink --> stream --> target -->
- 				 * connector
- 				 */
--				table->stream_allocations[i].engine =
-+				table->stream_allocations[i].stream =
- 					dc_target->streams[j];
- 				/* exit loop connector */
- 				find_stream_for_sink = true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 63e8c47..cd1924a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1608,7 +1608,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	value1 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT1));
- 
- 	if (table->stream_count >= 1) {
--		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[0].engine);
-+		core_stream =
-+			DC_STREAM_TO_CORE(table->stream_allocations[0].stream);
- 
- 		set_reg_field_value(
- 			value0,
-@@ -1624,7 +1625,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	}
- 
- 	if (table->stream_count >= 2) {
--		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[1].engine);
-+		core_stream =
-+			DC_STREAM_TO_CORE(table->stream_allocations[1].stream);
- 
- 		set_reg_field_value(
- 			value0,
-@@ -1640,7 +1642,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	}
- 
- 	if (table->stream_count >= 3) {
--		core_stream = DC_STREAM_TO_CORE(table->stream_allocations[2].engine);
-+		core_stream =
-+			DC_STREAM_TO_CORE(table->stream_allocations[2].stream);
- 
- 		set_reg_field_value(
- 			value1,
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 796c1ea..d91f4b0 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -392,7 +392,7 @@ struct mst_device_info {
- /* DP MST stream allocation (payload bandwidth number) */
- struct dp_mst_stream_allocation {
- 	/* stream engine id (DIG) */
--	const struct dc_stream *engine;
-+	const struct dc_stream *stream;
- 	/* number of slots required for the DP stream in
- 	 * transport packet */
- 	uint32_t slot_count;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0559-drm-amd-dal-fix-compilation-error-if-PPLib-is-not-en.patch b/common/recipes-kernel/linux/files/0559-drm-amd-dal-fix-compilation-error-if-PPLib-is-not-en.patch
deleted file mode 100644
index 505042cf..00000000
--- a/common/recipes-kernel/linux/files/0559-drm-amd-dal-fix-compilation-error-if-PPLib-is-not-en.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 4bca918aa5fa121fd55af8053fe27b0d6acbfe7b Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 2 Dec 2015 11:05:23 +0800
-Subject: [PATCH 0559/1110] drm/amd/dal: fix compilation error if PPLib is not
- enabled
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index ba54282..3b97b64 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -204,7 +204,9 @@ bool dc_service_get_system_clocks_range(
- 		struct dc_context *ctx,
- 		struct dal_system_clock_range *sys_clks)
- {
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
- 	struct amdgpu_device *adev = ctx->driver_context;
-+#endif
- 
- 	/* Default values, in case PPLib is not compiled-in. */
- 	sys_clks->max_mclk = 80000;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0560-drm-amd-dal-use-new-state-in-atomic_check.patch b/common/recipes-kernel/linux/files/0560-drm-amd-dal-use-new-state-in-atomic_check.patch
deleted file mode 100644
index 5b9f7dcc..00000000
--- a/common/recipes-kernel/linux/files/0560-drm-amd-dal-use-new-state-in-atomic_check.patch
+++ /dev/null
@@ -1,168 +0,0 @@
-From 02aa957e7c799e8d69b44a85e5fa50d2d73580cf Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 2 Dec 2015 19:18:59 +0800
-Subject: [PATCH 0560/1110] drm/amd/dal: use new state in atomic_check
-
-Pass new state to fill_plane_attributes functions, so fb variable is available.
-We should not segfault in case target is not created in atomic_check.
-Removed unneeded cast
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 61 ++++++++++++++--------
- 1 file changed, 39 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 7990a48..4c460c0 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -525,18 +525,20 @@ static void fill_gamma_from_crtc(
- 
- static void fill_plane_attributes(
- 			struct dc_surface *surface,
--			const struct drm_crtc *crtc)
-+			struct drm_plane_state *state)
- {
- 	const struct amdgpu_framebuffer *amdgpu_fb =
--		to_amdgpu_framebuffer(crtc->primary->state->fb);
--	fill_rects_from_plane_state(crtc->primary->state, surface);
-+		to_amdgpu_framebuffer(state->fb);
-+	const struct drm_crtc *crtc = state->crtc;
-+
-+	fill_rects_from_plane_state(state, surface);
- 	fill_plane_attributes_from_fb(
- 		surface,
- 		amdgpu_fb);
- 
- 	/* In case of gamma set, update gamma value */
- 	if (crtc->mode.private_flags &
--			AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
-+		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
- 		fill_gamma_from_crtc(crtc, surface);
- 	}
- }
-@@ -647,7 +649,7 @@ static void dm_dc_surface_commit(
- 			dm_state);
- 
- 	/* Surface programming */
--	fill_plane_attributes(dc_surface, crtc);
-+	fill_plane_attributes(dc_surface, crtc->primary->state);
- 	if (crtc->mode.private_flags &
- 		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
- 		/* reset trigger of gamma */
-@@ -2087,14 +2089,15 @@ int amdgpu_dm_atomic_commit(
- 		 * aconnector as needed
- 		 */
- 		handle_headless_hotplug(acrtc, new_state, &aconnector);
--		if (!aconnector) {
-+
-+		action = get_dm_commit_action(new_state);
-+
-+		if (!aconnector && action != DM_COMMIT_ACTION_NOTHING) {
- 			DRM_ERROR("Can't find connector for crtc %d\n",
- 							acrtc->crtc_id);
- 			break;
- 		}
- 
--		action = get_dm_commit_action(new_state);
--
- 		switch (action) {
- 		case DM_COMMIT_ACTION_DPMS_ON:
- 		case DM_COMMIT_ACTION_SET: {
-@@ -2318,7 +2321,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 	struct drm_crtc_state *crtc_state;
- 	struct drm_plane *plane;
- 	struct drm_plane_state *plane_state;
--	int i, j, ret, set_count, new_target_count;
-+	int i;
-+	int j;
-+	int ret;
-+	int set_count;
-+	int new_target_count;
- 	struct dc_validation_set set[MAX_TARGET_NUM] = {{ 0 }};
- 	struct dc_target *new_targets[MAX_TARGET_NUM] = { 0 };
- 	struct amdgpu_device *adev = dev->dev_private;
-@@ -2334,11 +2341,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 
- 	ret = -EINVAL;
- 
--	if (state->num_connector > MAX_TARGET_NUM) {
--		DRM_ERROR("Exceeded max targets number !\n");
--		return ret;
--	}
--
- 	/* copy existing configuration */
- 	new_target_count = 0;
- 	set_count = 0;
-@@ -2381,14 +2383,27 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 			struct dc_target *new_target = NULL;
- 
- 			if (!aconnector) {
--				DRM_ERROR("Can't find connector for crtc %d\n",
--								acrtc->crtc_id);
-+				DRM_ERROR(
-+					"%s: Can't find connector for crtc %d\n",
-+					__func__,
-+					acrtc->crtc_id);
- 				goto connector_not_found;
- 			}
-+
- 			new_target =
- 				create_target_for_sink(
- 					aconnector,
- 					&mode);
-+
-+			if (!new_target) {
-+				DRM_ERROR(
-+					"%s: Can't create target for crtc %d\n",
-+					__func__,
-+					acrtc->crtc_id);
-+				goto connector_not_found;
-+
-+			}
-+
- 			new_targets[new_target_count] = new_target;
- 
- 			set_count = update_in_val_sets_target(
-@@ -2420,12 +2435,13 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 		for_each_plane_in_state(state, plane, plane_state, j) {
- 			struct drm_plane_state *old_plane_state = plane->state;
- 			struct drm_framebuffer *fb = plane_state->fb;
--			struct amdgpu_crtc *acrtc =
--					to_amdgpu_crtc(plane_state->crtc);
-+			struct drm_crtc *crtc = plane_state->crtc;
-+			struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- 
- 			if (!fb || acrtc->target != set[i].target)
- 				continue;
--			if (!plane_state->crtc->state->planes_changed)
-+
-+			if (!crtc->state->planes_changed)
- 				continue;
- 
- 			if (!page_flip_needed(plane_state, old_plane_state)) {
-@@ -2433,7 +2449,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 					dc_create_surface(dc);
- 
- 				fill_plane_attributes(
--						surface, plane_state->crtc);
-+					surface,
-+					plane_state);
-+
- 				add_val_sets_surface(
- 					set,
- 					set_count,
-@@ -2450,8 +2468,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- connector_not_found:
- 	for (i = 0; i < set_count; i++) {
- 		for (j = 0; j < set[i].surface_count; j++) {
--			dc_surface_release(
--				(struct dc_surface *)set[i].surfaces[j]);
-+			dc_surface_release(set[i].surfaces[j]);
- 		}
- 	}
- 	for (i = 0; i < new_target_count; i++)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0561-drm-amd-dal-Fail-validation-if-YCbCr-420-since-curre.patch b/common/recipes-kernel/linux/files/0561-drm-amd-dal-Fail-validation-if-YCbCr-420-since-curre.patch
deleted file mode 100644
index be091be5..00000000
--- a/common/recipes-kernel/linux/files/0561-drm-amd-dal-Fail-validation-if-YCbCr-420-since-curre.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From bbf673f918a152ebb3cfd541497908de2f631f91 Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Wed, 2 Dec 2015 13:55:16 -0500
-Subject: [PATCH 0561/1110] drm/amd/dal: Fail validation if YCbCr 420 since
- current HW does not support it
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index cd1924a..3e2ac27 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1038,6 +1038,10 @@ static bool validate_hdmi_output(
- 			PIXEL_ENCODING_RGB)
- 			return false;
- 
-+	/* DCE11 HW does not support 420 */
-+	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		return false;
-+
- 	return true;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0562-drm-amd-dal-expand-pplib_post_set_mode-to-more-close.patch b/common/recipes-kernel/linux/files/0562-drm-amd-dal-expand-pplib_post_set_mode-to-more-close.patch
deleted file mode 100644
index 94f9214f..00000000
--- a/common/recipes-kernel/linux/files/0562-drm-amd-dal-expand-pplib_post_set_mode-to-more-close.patch
+++ /dev/null
@@ -1,136 +0,0 @@
-From 735b5a7c29412ae29eeedf41513d70c115c480e8 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 1 Dec 2015 16:25:04 -0500
-Subject: [PATCH 0562/1110] drm/amd/dal: expand pplib_post_set_mode to more
- closely mirror NotifyMultiDisplayConfig
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c |  9 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 56 ++++++++++++++++++++--
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  3 ++
- 3 files changed, 64 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 346028a..742c4ec 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3460,9 +3460,18 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 		calcs_output->dispclk_khz =
- 				mul(bw_results_internal->dispclk,
- 					int_to_fixed(1000)).value >> 24;
-+		calcs_output->blackout_recovery_time_us =
-+			mul(bw_results_internal->blackout_recovery_time,
-+					int_to_fixed(1000)).value >> 24;
- 		calcs_output->required_sclk =
- 			mul(bw_results_internal->required_sclk,
- 					int_to_fixed(1000)).value >> 24;
-+		calcs_output->required_sclk_deep_sleep =
-+			mul(bw_results_internal->sclk_deep_sleep,
-+					int_to_fixed(1000)).value >> 24;
-+		/*TODO:fix formula to unhardcode*/
-+		calcs_output->required_yclk =
-+				mul(high_yclk, int_to_fixed(1000)).value >> 24;
- 
- 		((struct bw_calcs_input_vbios *)vbios)->low_yclk = low_yclk;
- 		((struct bw_calcs_input_vbios *)vbios)->high_yclk = high_yclk;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 14e10b9..b7aa85d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -465,23 +465,71 @@ static bool targets_changed(
- 	return false;
- }
- 
-+
-+static uint32_t get_min_vblank_time_us(const struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	uint32_t min_vertical_blank_time = -1;
-+	for (i = 0; i < context->target_count; i++) {
-+		const struct core_target *target = context->targets[i];
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct dc_stream *stream =
-+						target->public.streams[j];
-+			uint32_t vertical_blank_in_pixels = 0;
-+			uint32_t vertical_blank_time = 0;
-+
-+			vertical_blank_in_pixels = stream->timing.h_total *
-+				(stream->timing.v_total
-+				- stream->timing.v_addressable);
-+			/*TODO: - vertical timing overscan if we still support*/
-+			vertical_blank_time = vertical_blank_in_pixels * 1000
-+				/ stream->timing.pix_clk_khz;
-+			/*TODO: doublescan doubles, pixel repetition mults*/
-+
-+			if (min_vertical_blank_time > vertical_blank_time)
-+				min_vertical_blank_time = vertical_blank_time;
-+		}
-+	}
-+
-+	return min_vertical_blank_time;
-+}
-+
- static void pplib_post_set_mode(
- 	struct dc *dc,
- 	const struct validate_context *context)
- {
-+	uint8_t i;
- 	struct dc_pp_display_configuration pp_display_cfg = { 0 };
- 
- 	pp_display_cfg.nb_pstate_switch_disable =
- 			context->bw_results.nbp_state_change_enable == false;
--
- 	pp_display_cfg.cpu_cc6_disable =
- 			context->bw_results.cpuc_state_change_enable == false;
--
- 	pp_display_cfg.cpu_pstate_disable =
- 			context->bw_results.cpup_state_change_enable == false;
-+	pp_display_cfg.cpu_pstate_separation_time =
-+			context->bw_results.blackout_recovery_time_us;
-+
-+	pp_display_cfg.max_displays = dc->link_count;
-+	for (i = 0; i < context->target_count; i++)
-+		pp_display_cfg.active_displays +=
-+				context->targets[i]->public.stream_count;
-+
-+	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk;
-+	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
-+	pp_display_cfg.min_engine_clock_deep_sleep_khz
-+			= context->bw_results.required_sclk_deep_sleep;
-+
-+	pp_display_cfg.avail_mclk_switch_time_us =
-+						get_min_vblank_time_us(context);
-+	/* TODO: dce11.2*/
-+	pp_display_cfg.avail_mclk_switch_time_in_disp_active_us = 0;
-+
-+	pp_display_cfg.disp_clk_khz = context->bw_results.dispclk_khz;
- 
--	/* TODO: get cpu_pstate_separation_time from BW Calcs. */
--	pp_display_cfg.cpu_pstate_separation_time = 0;
-+	/* TODO: unhardcode, is this still applicable?*/
-+	pp_display_cfg.crtc_index = 0;
-+	pp_display_cfg.line_time_in_us = 0;
- 
- 	dc_service_pp_post_dce_clock_change(dc->ctx, &pp_display_cfg);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index a0c0fef..a304ce8 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -434,7 +434,10 @@ struct bw_calcs_output {
- 	struct bw_watermarks stutter_exit_watermark[4];
- 	struct bw_watermarks nbp_state_change_watermark[4];
- 	uint32_t required_sclk;
-+	uint32_t required_sclk_deep_sleep;
-+	uint32_t required_yclk;
- 	uint32_t dispclk_khz;
-+	uint32_t blackout_recovery_time_us;
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0563-drm-amd-dal-Fix-DCE80-bandwidth-programming-model-to.patch b/common/recipes-kernel/linux/files/0563-drm-amd-dal-Fix-DCE80-bandwidth-programming-model-to.patch
deleted file mode 100644
index e17699d8..00000000
--- a/common/recipes-kernel/linux/files/0563-drm-amd-dal-Fix-DCE80-bandwidth-programming-model-to.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From cf63c3c07c98db9373e60f4bbf49a60978a23cab Mon Sep 17 00:00:00 2001
-From: Aric Cyr <aric.cyr@amd.com>
-Date: Wed, 2 Dec 2015 14:15:06 -0500
-Subject: [PATCH 0563/1110] drm/amd/dal: Fix DCE80 bandwidth programming model
- to match DCE110
-
-Signed-off-by: Aric Cyr <aric.cyr@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 6 +++---
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c    | 5 ++---
- 2 files changed, 5 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 0be98a8..1d289ba 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1310,12 +1310,12 @@ static void set_safe_displaymarks(struct validate_context *context)
- 
- static void dce110_program_bw(struct dc *dc, struct validate_context *context)
- {
--	set_safe_displaymarks(&dc->current_context);
-+	set_safe_displaymarks(context);
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
--	set_display_clock(&dc->current_context);
--	set_displaymarks(dc, &dc->current_context);
-+	set_display_clock(context);
-+	set_displaymarks(dc, context);
- }
- 
- /*TODO: break out clock sources like timing gen/ encoder*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 889c02d..f7ef317 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -535,7 +535,7 @@ static void program_urgency_watermark(
- 	dal_write_reg(ctx, urgency_addr, urgency_cntl);
- }
- 
--void program_stutter_watermark(
-+static void program_stutter_watermark(
- 	const struct dc_context *ctx,
- 	const uint32_t offset,
- 	struct bw_watermarks marks)
-@@ -600,7 +600,7 @@ void program_stutter_watermark(
- 	dal_write_reg(ctx, stutter_addr, stutter_cntl);
- }
- 
--void program_nbp_watermark(
-+static void program_nbp_watermark(
- 	const struct dc_context *ctx,
- 	const uint32_t offset,
- 	struct bw_watermarks marks)
-@@ -694,7 +694,6 @@ void dce110_mem_input_program_safe_display_marks(struct mem_input *mi)
- 		mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK);
- 	program_stutter_watermark(mi->ctx, bm_dce110->offsets.dmif, max_marks);
- 	program_nbp_watermark(mi->ctx, bm_dce110->offsets.dmif, nbp_marks);
--
- }
- 
- void dce110_mem_input_program_display_marks(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch b/common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch
deleted file mode 100644
index fab78caf..00000000
--- a/common/recipes-kernel/linux/files/0564-drm-amd-dal-Bool-to-Void-on-Link-Encoder-Programming.patch
+++ /dev/null
@@ -1,760 +0,0 @@
-From f71d6bcc11dd4cdf0e0ebe7e4d4419174406b2ee Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 2 Dec 2015 11:48:07 -0500
-Subject: [PATCH 0564/1110] drm/amd/dal: Bool to Void on Link Encoder
- Programming
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   5 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  33 +---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       |  48 ++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  18 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 205 +++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  36 +---
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   8 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h         |   4 +-
- 9 files changed, 141 insertions(+), 218 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index b7aa85d..e141e99 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -162,10 +162,7 @@ static void init_hw(struct dc *dc)
- 		 * required signal (which may be different from the
- 		 * default signal on connector). */
- 		struct core_link *link = dc->links[i];
--		if (!dc->hwss.encoder_power_up(link->link_enc)) {
--			dal_error("Failed link encoder power up!\n");
--			return;
--		}
-+		dc->hwss.encoder_power_up(link->link_enc);
- 	}
- 
- 	dal_bios_parser_set_scratch_acc_mode_change(bp);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 58eac92..d8bf8e9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -884,15 +884,12 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 
- 	/* get link settings for video mode timing */
- 	decide_link_settings(stream, &link_settings);
--	status = dp_enable_link_phy(
-+	dp_enable_link_phy(
- 		stream->sink->link,
- 		stream->signal,
- 		stream->stream_enc->id,
- 		&link_settings);
- 
--	if (status == DC_ERROR_UNEXPECTED)
--		return status;
--
- 	panel_mode = dp_get_panel_mode(link);
- 	dpcd_configure_panel_mode(link, panel_mode);
- 
-@@ -936,20 +933,15 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- 	return enable_link_dp(stream);
- }
- 
--static enum dc_status enable_link_hdmi(struct core_stream *stream)
-+static void enable_link_hdmi(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
- 
--	/* TODO:Need to add missing use cases, reference
--	 * dal_hw_sequencer_enable_link_base*/
--	enum dc_status status = DC_OK;
--
- 	/* enable video output */
- 	/* here we need to specify that encoder output settings
- 	 * need to be calculated as for the set mode,
- 	 * it will lead to querying dynamic link capabilities
- 	 * which should be done before enable output */
--
- 	uint32_t normalized_pix_clk = stream->public.timing.pix_clk_khz;
- 	switch (stream->public.timing.display_color_depth) {
- 	case COLOR_DEPTH_888:
-@@ -977,20 +969,17 @@ static enum dc_status enable_link_hdmi(struct core_stream *stream)
- 		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- 					? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
- 
--	if (!link->ctx->dc->hwss.encoder_enable_output(
-+	link->ctx->dc->hwss.encoder_enable_output(
- 			stream->sink->link->link_enc,
- 			&stream->sink->link->cur_link_settings,
- 			stream->stream_enc->id,
- 			dal_clock_source_get_id(stream->clock_source),
- 			stream->signal,
- 			stream->public.timing.display_color_depth,
--			stream->public.timing.pix_clk_khz))
--		status = DC_ERROR_UNEXPECTED;
-+			stream->public.timing.pix_clk_khz);
- 
- 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 		dal_ddc_service_read_scdc_data(link->ddc);
--
--	return status;
- }
- 
- /****************************enable_link***********************************/
-@@ -1009,7 +998,8 @@ enum dc_status core_link_enable(struct core_stream *stream)
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
--		status = enable_link_hdmi(stream);
-+		enable_link_hdmi(stream);
-+		status = DC_OK;
- 		break;
- 
- 	default:
-@@ -1030,10 +1020,9 @@ enum dc_status core_link_enable(struct core_stream *stream)
- 	return status;
- }
- 
--enum dc_status core_link_disable(struct core_stream *stream)
-+void core_link_disable(struct core_stream *stream)
- {
- 	/* TODO  dp_set_hw_test_pattern */
--	enum dc_status status = DC_OK;
- 	struct dc *dc = stream->ctx->dc;
- 
- 	/* here we need to specify that encoder output settings
-@@ -1051,12 +1040,8 @@ enum dc_status core_link_disable(struct core_stream *stream)
- 					stream->sink->link, stream);
- 		}
- 	}
--
--	else if (!dc->hwss.encoder_disable_output(
--				stream->sink->link->link_enc, stream->signal))
--		status = DC_ERROR_UNEXPECTED;
--
--	return status;
-+	dc->hwss.encoder_disable_output(
-+		stream->sink->link->link_enc, stream->signal);
- }
- 
- enum dc_status dc_link_validate_mode_timing(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 71e6f8c..2852440 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1071,32 +1071,34 @@ bool dp_hbr_verify_link_cap(
- 		skip_video_pattern = true;
- 		if (cur->link_rate == LINK_RATE_LOW)
- 			skip_video_pattern = false;
--		if (dp_enable_link_phy(
-+
-+		dp_enable_link_phy(
- 				link,
- 				link->public.connector_signal,
- 				ENGINE_ID_UNKNOWN,
--				cur)) {
--			if (skip_link_training)
--				success = true;
--			else {
--				uint8_t num_retries = 3;
--				uint8_t j;
--				uint8_t delay_between_retries = 10;
--				for (j = 0; j < num_retries; ++j) {
--					success = perform_link_training(
--						link,
--						cur,
--						skip_video_pattern);
--
--					if (success)
--						break;
--
--					dc_service_sleep_in_milliseconds(
--						link->ctx,
--						delay_between_retries);
--
--					delay_between_retries += 10;
--				}
-+				cur);
-+
-+		if (skip_link_training)
-+			success = true;
-+		else {
-+			uint8_t num_retries = 3;
-+			uint8_t j;
-+			uint8_t delay_between_retries = 10;
-+
-+			for (j = 0; j < num_retries; ++j) {
-+				success = perform_link_training(
-+					link,
-+					cur,
-+					skip_video_pattern);
-+
-+				if (success)
-+					break;
-+
-+				dc_service_sleep_in_milliseconds(
-+					link->ctx,
-+					delay_between_retries);
-+
-+				delay_between_retries += 10;
- 			}
- 		}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 054b0a3..2913d5c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -46,28 +46,22 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
- 			sizeof(state));
- }
- 
--enum dc_status dp_enable_link_phy(
-+void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
- 	enum engine_id engine,
- 	const struct link_settings *link_settings)
- {
--	enum dc_status status = DC_OK;
--
--	if (!link->dc->hwss.encoder_enable_output(
-+	link->dc->hwss.encoder_enable_output(
- 					link->link_enc,
- 					link_settings,
- 					engine,
- 					CLOCK_SOURCE_ID_EXTERNAL,
- 					signal,
- 					COLOR_DEPTH_UNDEFINED,
--					0))
--		status = DC_ERROR_UNEXPECTED;
--
--	if (status == DC_OK)
--		dp_receiver_power_ctrl(link, true);
-+					0);
- 
--	return status;
-+	dp_receiver_power_ctrl(link, true);
- }
- 
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
-@@ -133,7 +127,7 @@ bool dp_set_hw_training_pattern(
- }
- 
- 
--bool dp_set_hw_lane_settings(
-+void dp_set_hw_lane_settings(
- 	struct core_link *link,
- 	const struct link_training_settings *link_settings)
- {
-@@ -141,8 +135,6 @@ bool dp_set_hw_lane_settings(
- 
- 	/* call Encoder to set lane settings */
- 	link->ctx->dc->hwss.encoder_dp_set_lane_settings(encoder, link_settings);
--
--	return true;
- }
- 
- enum dp_panel_mode dp_get_panel_mode(struct core_link *link)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 3e2ac27..3d902f3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -640,7 +640,7 @@ static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
-  * @brief
-  * eDP only. Control the power of the eDP panel.
-  */
--static bool link_encoder_edp_power_control(
-+static void link_encoder_edp_power_control(
- 	struct dce110_link_encoder *enc110,
- 	bool power_up)
- {
-@@ -651,7 +651,7 @@ static bool link_encoder_edp_power_control(
- 	if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
- 		CONNECTOR_ID_EDP) {
- 		BREAK_TO_DEBUGGER();
--		return false;
-+		return;
- 	}
- 
- 	if ((power_up && !is_panel_powered_on(enc110)) ||
-@@ -693,8 +693,6 @@ static bool link_encoder_edp_power_control(
- 				"%s: Skipping Panel Power action: %s\n",
- 				__func__, (power_up ? "On":"Off"));
- 	}
--
--	return true;
- }
- 
- /*
-@@ -810,7 +808,7 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
-  * @brief
-  * eDP only. Control the backlight of the eDP panel
-  */
--static bool link_encoder_edp_backlight_control(
-+static void link_encoder_edp_backlight_control(
- 	struct dce110_link_encoder *enc110,
- 	bool enable)
- {
-@@ -820,7 +818,7 @@ static bool link_encoder_edp_backlight_control(
- 	if (dal_graphics_object_id_get_connector_id(enc110->base.connector)
- 		!= CONNECTOR_ID_EDP) {
- 		BREAK_TO_DEBUGGER();
--		return false;
-+		return;
- 	}
- 
- 	if (enable && is_panel_backlight_on(enc110)) {
-@@ -829,7 +827,7 @@ static bool link_encoder_edp_backlight_control(
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: panel already powered up. Do nothing.\n",
- 				__func__);
--		return true;
-+		return;
- 	}
- 
- 	if (!enable && !is_panel_powered_on(enc110)) {
-@@ -838,7 +836,7 @@ static bool link_encoder_edp_backlight_control(
- 				LOG_MINOR_HW_TRACE_RESUME_S3,
- 				"%s: panel already powered down. Do nothing.\n",
- 				__func__);
--		return true;
-+		return;
- 	}
- 
- 	/* Send VBIOS command to control eDP panel backlight */
-@@ -874,8 +872,6 @@ static bool link_encoder_edp_backlight_control(
- 	dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
- 			enc110->base.adapter_service), &cntl);
--
--	return true;
- }
- 
- static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
-@@ -1289,13 +1285,12 @@ bool dce110_link_encoder_validate_output_with_stream(
- 	return is_valid;
- }
- 
--bool dce110_link_encoder_power_up(
-+void dce110_link_encoder_power_up(
- 	struct link_encoder *enc)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
--
- 	enum bp_result result;
- 
- 	cntl.action = TRANSMITTER_CONTROL_INIT;
-@@ -1318,7 +1313,7 @@ bool dce110_link_encoder_power_up(
- 			"%s: Failed to execute VBIOS command table!\n",
- 			__func__);
- 		BREAK_TO_DEBUGGER();
--		return false;
-+		return;
- 	}
- 
- 	if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
-@@ -1345,8 +1340,6 @@ bool dce110_link_encoder_power_up(
- 	 * as DIG_FE id even caller pass DIG_FE id.
- 	 * So this routine must be called first. */
- 	hpd_initialize(enc110);
--
--	return true;
- }
- 
- void dce110_link_encoder_setup(
-@@ -1390,52 +1383,93 @@ void dce110_link_encoder_setup(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--bool dce110_link_encoder_enable_tmds_output(
-+/*
-+ * @brief
-+ * Configure digital transmitter and enable both encoder and transmitter
-+ * Actual output will be available after calling unblank()
-+ */
-+void dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum engine_id engine,
- 	enum clock_source_id clock_source,
-+	enum signal_type signal,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock)
- {
--	return true;
--}
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
- 
--bool dce110_link_encoder_enable_dual_link_tmds_output(
--	struct link_encoder *enc,
--	enum clock_source_id clock_source,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock)
--{
--	return true;
--}
-+	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-+		/* power up eDP panel */
- 
--/* enables DP PHY output */
--bool dce110_link_encoder_enable_dp_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum clock_source_id clock_source)
--{
--	return true;
--}
-+		link_encoder_edp_power_control(enc110, true);
- 
--/* enables DP PHY output in MST mode */
--bool dce110_link_encoder_enable_dp_mst_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum clock_source_id clock_source)
--{
--	return true;
-+		link_encoder_edp_wait_for_hpd_ready(enc110, true);
-+
-+		/* have to turn off the backlight
-+		 * before power down eDP panel
-+		 */
-+		link_encoder_edp_backlight_control(enc110, true);
-+	}
-+
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually.
-+	 */
-+	if (dc_is_dp_signal(signal))
-+		configure_encoder(enc110, engine, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = engine;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = signal;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	if (dc_is_dp_signal(signal))
-+		cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	else
-+		cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
-+		dc_service_sleep_in_milliseconds(
-+			ctx,
-+			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
-+
-+	result = dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc110->base.adapter_service),
-+		&cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
- }
- 
- /*
-  * @brief
-  * Disable transmitter and its encoder
-  */
--bool dce110_link_encoder_disable_output(
-+void dce110_link_encoder_disable_output(
- 	struct link_encoder *enc,
- 	enum signal_type signal)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
- 
- 	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- 		/* have to turn off the backlight
-@@ -1448,7 +1482,7 @@ bool dce110_link_encoder_disable_output(
- 		dal_adapter_service_should_optimize(
- 			enc110->base.adapter_service,
- 			OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
--		return true;
-+		return;
- 	}
- 	/* Power-down RX and disable GPU PHY should be paired.
- 	 * Disabling PHY without powering down RX may cause
-@@ -1467,10 +1501,20 @@ bool dce110_link_encoder_disable_output(
- 	cntl.signal = signal;
- 	cntl.connector_obj_id = enc110->base.connector;
- 
--	dal_bios_parser_transmitter_control(
-+	result = dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
- 			enc110->base.adapter_service), &cntl);
- 
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
- 	/* disable encoder */
- 	if (dc_is_dp_signal(signal))
- 		link_encoder_disable(enc110);
-@@ -1488,11 +1532,9 @@ bool dce110_link_encoder_disable_output(
- 		 * link_encoder_edp_power_control(
- 				link_enc, false); */
- 	}
--
--	return true;
- }
- 
--bool dce110_link_encoder_dp_set_lane_settings(
-+void dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings)
- {
-@@ -1503,7 +1545,7 @@ bool dce110_link_encoder_dp_set_lane_settings(
- 
- 	if (!link_settings) {
- 		BREAK_TO_DEBUGGER();
--		return false;
-+		return;
- 	}
- 
- 	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
-@@ -1540,8 +1582,6 @@ bool dce110_link_encoder_dp_set_lane_settings(
- 			dal_adapter_service_get_bios_parser(
- 				enc110->base.adapter_service), &cntl);
- 	}
--
--	return true;
- }
- 
- /* set DP PHY test and training patterns */
-@@ -1850,71 +1890,6 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	}
- }
- 
--/*
-- * @brief
-- * Configure digital transmitter and enable both encoder and transmitter
-- * Actual output will be available after calling unblank()
-- */
--bool dce110_link_encoder_enable_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum engine_id engine,
--	enum clock_source_id clock_source,
--	enum signal_type signal,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock)
--{
--	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
--	struct dc_context *ctx = enc110->base.ctx;
--	struct bp_transmitter_control cntl = { 0 };
--
--	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
--		/* power up eDP panel */
--
--		link_encoder_edp_power_control(enc110, true);
--
--		link_encoder_edp_wait_for_hpd_ready(enc110, true);
--
--		/* have to turn off the backlight
--		 * before power down eDP panel */
--		link_encoder_edp_backlight_control(enc110, true);
--	}
--
--	/* Enable the PHY */
--
--	/* number_of_lanes is used for pixel clock adjust,
--	 * but it's not passed to asic_control.
--	 * We need to set number of lanes manually. */
--	if (dc_is_dp_signal(signal))
--		configure_encoder(enc110, engine, link_settings);
--
--	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = engine;
--	cntl.transmitter = enc110->base.transmitter;
--	cntl.pll_id = clock_source;
--	cntl.signal = signal;
--	cntl.lanes_number = link_settings->lane_count;
--	cntl.hpd_sel = enc110->base.hpd_source;
--	if (dc_is_dp_signal(signal))
--		cntl.pixel_clock = link_settings->link_rate
--						* LINK_RATE_REF_FREQ_IN_KHZ;
--	else
--		cntl.pixel_clock = pixel_clock;
--	cntl.color_depth = color_depth;
--
--	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
--		dc_service_sleep_in_milliseconds(
--			ctx,
--			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
--
--	dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service),
--		&cntl);
--
--	return true;
--}
--
- void dce110_link_encoder_connect_dig_be_to_fe(
- 	struct link_encoder *enc,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 334cc1f..820a7b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -53,7 +53,7 @@ bool dce110_link_encoder_validate_output_with_stream(
- /****************** HW programming ************************/
- 
- /* initialize HW */  /* why do we initialze aux in here? */
--bool dce110_link_encoder_power_up(struct link_encoder *enc);
-+void dce110_link_encoder_power_up(struct link_encoder *enc);
- 
- /* program DIG_MODE in DIG_BE */
- /* TODO can this be combined with enable_output? */
-@@ -61,41 +61,13 @@ void dce110_link_encoder_setup(
- 	struct link_encoder *enc,
- 	enum signal_type signal);
- 
--/* enables TMDS PHY output */
--/* TODO: still need depth or just pass in adjusted pixel clock? */
--bool dce110_link_encoder_enable_tmds_output(
--	struct link_encoder *enc,
--	enum clock_source_id clock_source,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock);
--
--/* enables TMDS PHY output */
--/* TODO: still need this or just pass in adjusted pixel clock? */
--bool dce110_link_encoder_enable_dual_link_tmds_output(
--	struct link_encoder *enc,
--	enum clock_source_id clock_source,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock);
--
--/* enables DP PHY output */
--bool dce110_link_encoder_enable_dp_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum clock_source_id clock_source);
--
--/* enables DP PHY output in MST mode */
--bool dce110_link_encoder_enable_dp_mst_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum clock_source_id clock_source);
--
- /* disable PHY output */
--bool dce110_link_encoder_disable_output(
-+void dce110_link_encoder_disable_output(
- 	struct link_encoder *enc,
- 	enum signal_type signal);
- 
- /* set DP lane settings */
--bool dce110_link_encoder_dp_set_lane_settings(
-+void dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings);
- 
-@@ -112,7 +84,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level);
- 
--bool dce110_link_encoder_enable_output(
-+void dce110_link_encoder_enable_output(
- 	struct link_encoder *enc,
- 	const struct link_settings *link_settings,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index ecc1cdc..bea3c36 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -235,7 +235,7 @@ struct core_link *link_create(const struct link_init_data *init_params);
- void link_destroy(struct core_link **link);
- enum dc_status core_link_enable(struct core_stream *stream);
- 
--enum dc_status core_link_disable(struct core_stream *stream);
-+void core_link_disable(struct core_stream *stream);
- 
- enum dc_status dc_link_validate_mode_timing(
- 		const struct core_sink *sink,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index e414021..3114fbd 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -90,10 +90,10 @@ struct hw_sequencer_funcs {
- 
- 	void (*encoder_destroy)(struct link_encoder **enc);
- 
--	bool (*encoder_power_up)(
-+	void (*encoder_power_up)(
- 					struct link_encoder *enc);
- 
--	bool (*encoder_enable_output)(
-+	void (*encoder_enable_output)(
- 					struct link_encoder *enc,
- 					const struct link_settings *link_settings,
- 					enum engine_id engine,
-@@ -102,7 +102,7 @@ struct hw_sequencer_funcs {
- 					enum dc_color_depth color_depth,
- 					uint32_t pixel_clock);
- 
--	bool (*encoder_disable_output)(
-+	void (*encoder_disable_output)(
- 					struct link_encoder *enc,
- 					enum signal_type signal);
- 
-@@ -110,7 +110,7 @@ struct hw_sequencer_funcs {
- 					struct link_encoder *enc,
- 					const struct encoder_set_dp_phy_pattern_param *param);
- 
--	bool (*encoder_dp_set_lane_settings)(
-+	void (*encoder_dp_set_lane_settings)(
- 					struct link_encoder *enc,
- 					const struct link_training_settings *link_settings);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index c86c942..28d9d04 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -40,7 +40,7 @@ enum dc_status core_link_write_dpcd(
- 	const uint8_t *data,
- 	uint32_t size);
- 
--enum dc_status dp_enable_link_phy(
-+void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
- 	enum engine_id engine,
-@@ -56,7 +56,7 @@ bool dp_set_hw_training_pattern(
- 	struct core_link *link,
- 	enum hw_dp_training_pattern pattern);
- 
--bool dp_set_hw_lane_settings(
-+void dp_set_hw_lane_settings(
- 	struct core_link *link,
- 	const struct link_training_settings *link_settings);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0565-drm-amd-dal-Move-enabling-of-stream-link-to-dc_link.patch b/common/recipes-kernel/linux/files/0565-drm-amd-dal-Move-enabling-of-stream-link-to-dc_link.patch
deleted file mode 100644
index 223e106a..00000000
--- a/common/recipes-kernel/linux/files/0565-drm-amd-dal-Move-enabling-of-stream-link-to-dc_link.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From c5a1ee9146c9d2e4212dc85bc71a08b34db60e05 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 2 Dec 2015 11:41:18 -0500
-Subject: [PATCH 0565/1110] drm/amd/dal: Move enabling of stream & link to
- dc_link
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 68 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  5 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 65 ++-------------------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  4 ++
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  9 +++
- 5 files changed, 90 insertions(+), 61 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index d8bf8e9..f29aea7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1090,3 +1090,71 @@ void core_link_resume(struct core_link *link)
- 		DELAY_ON_CONNECT_IN_MS,
- 		DELAY_ON_DISCONNECT_IN_MS);
- }
-+
-+
-+static enum dc_status allocate_mst_payload(struct core_stream *stream)
-+{
-+	struct core_link *link = stream->sink->link;
-+	struct link_encoder *link_encoder = link->link_enc;
-+	struct stream_encoder *stream_encoder = stream->stream_enc;
-+	struct dp_mst_stream_allocation_table table = {0};
-+	struct fixed31_32 avg_time_slots_per_mtp;
-+	uint8_t cur_stream_payload_idx;
-+	struct dc *dc = stream->ctx->dc;
-+
-+	/* enable_link_dp_mst already check link->enabled_stream_count
-+	 * and stream is in link->stream[]. This is called during set mode,
-+	 * stream_enc is available.
-+	 */
-+
-+	/* get calculate VC payload for stream: stream_alloc */
-+	dc_helpers_dp_mst_write_payload_allocation_table(
-+		stream->ctx,
-+		&stream->public,
-+		&table,
-+		true);
-+
-+	/* program DP source TX for payload */
-+	dc->hwss.update_mst_stream_allocation_table(
-+		link_encoder,
-+		&table);
-+
-+	/* send down message */
-+	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+			stream->ctx,
-+			&stream->public);
-+
-+	dc_helpers_dp_mst_send_payload_allocation(
-+			stream->ctx,
-+			&stream->public,
-+			true);
-+
-+	/* slot X.Y for only current stream */
-+	cur_stream_payload_idx = table.cur_stream_payload_idx;
-+	avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
-+		table.stream_allocations[cur_stream_payload_idx].pbn,
-+		table.stream_allocations[cur_stream_payload_idx].pbn_per_slot);
-+
-+	dc->hwss.set_mst_bandwidth(
-+		stream_encoder,
-+		avg_time_slots_per_mtp);
-+
-+	return DC_OK;
-+
-+}
-+
-+void core_link_enable_stream(
-+		struct core_link *link,
-+		struct core_stream *stream)
-+{
-+	struct dc *dc = stream->ctx->dc;
-+
-+	dc->hwss.enable_stream(stream);
-+
-+	if (DC_OK != core_link_enable(stream)) {
-+			BREAK_TO_DEBUGGER();
-+			return;
-+	}
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		allocate_mst_payload(stream);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 2913d5c..4c9eae4 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -9,6 +9,10 @@
- #include "include/connector_interface.h"
- #include "hw_sequencer.h"
- #include "include/ddc_service_interface.h"
-+#include "dc_helpers.h"
-+#include "dce110/dce110_link_encoder.h"
-+#include "dce110/dce110_stream_encoder.h"
-+
- 
- enum dc_status core_link_read_dpcd(
- 	struct core_link* link,
-@@ -191,4 +195,3 @@ void dp_set_hw_test_pattern(
- 
- 	link->ctx->dc->hwss.encoder_set_dp_phy_pattern(encoder, &pattern_param);
- }
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 1d289ba..fa71095 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -774,56 +774,6 @@ static enum color_space get_output_color_space(
- 	return color_space;
- }
- 
--static enum dc_status allocate_mst_payload(struct core_stream *stream)
--{
--	struct core_link *link = stream->sink->link;
--	struct link_encoder *link_encoder = link->link_enc;
--	struct stream_encoder *stream_encoder = stream->stream_enc;
--	struct dp_mst_stream_allocation_table table = {0};
--	struct fixed31_32 avg_time_slots_per_mtp;
--	uint8_t cur_stream_payload_idx;
--
--	/* enable_link_dp_mst already check link->enabled_stream_count
--	 * and stream is in link->stream[]. This is called during set mode,
--	 * stream_enc is available.
--	 */
--
--	/* get calculate VC payload for stream: stream_alloc */
--	dc_helpers_dp_mst_write_payload_allocation_table(
--		stream->ctx,
--		&stream->public,
--		&table,
--		true);
--
--	/* program DP source TX for payload */
--	dce110_link_encoder_update_mst_stream_allocation_table(
--		link_encoder,
--		&table);
--
--	/* send down message */
--	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
--			stream->ctx,
--			&stream->public);
--
--	dc_helpers_dp_mst_send_payload_allocation(
--			stream->ctx,
--			&stream->public,
--			true);
--
--	/* slot X.Y for only current stream */
--	cur_stream_payload_idx = table.cur_stream_payload_idx;
--	avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
--		table.stream_allocations[cur_stream_payload_idx].pbn,
--		table.stream_allocations[cur_stream_payload_idx].pbn_per_slot);
--
--	dce110_stream_encoder_set_mst_bandwidth(
--		stream_encoder,
--		avg_time_slots_per_mtp);
--
--	return DC_OK;
--
--}
--
- static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
-@@ -991,15 +941,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			color_space);
- 
- 	if (timing_changed) {
--		enable_stream(stream);
--
--		if (DC_OK != core_link_enable(stream)) {
--				BREAK_TO_DEBUGGER();
--				return DC_ERROR_UNEXPECTED;
--		}
--		if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
--			allocate_mst_payload(stream);
--
-+		core_link_enable_stream(stream->sink->link, stream);
- 	}
- 
- 	if (dc_is_dp_signal(stream->signal))
-@@ -1854,7 +1796,10 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.validate_bandwidth = dce110_validate_bandwidth,
- 	.enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating,
- 	.enable_display_power_gating = dce110_enable_display_power_gating,
--	.program_bw = dce110_program_bw
-+	.program_bw = dce110_program_bw,
-+	.enable_stream = enable_stream,
-+	.update_mst_stream_allocation_table = dce110_link_encoder_update_mst_stream_allocation_table,
-+	.set_mst_bandwidth = dce110_stream_encoder_set_mst_bandwidth
- };
- 
- bool dce110_hw_sequencer_construct(struct dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index bea3c36..299b13e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -244,6 +244,10 @@ enum dc_status dc_link_validate_mode_timing(
- 
- void core_link_resume(struct core_link *link);
- 
-+void core_link_enable_stream(
-+		struct core_link *link,
-+		struct core_stream *stream);
-+
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 3114fbd..0502c4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -154,7 +154,16 @@ struct hw_sequencer_funcs {
- 	void (*program_bw)(
- 					struct dc *dc,
- 					struct validate_context *context);
-+	void (*enable_stream)(
-+					struct core_stream *stream);
- 
-+	void (*update_mst_stream_allocation_table)(
-+					struct link_encoder *enc,
-+					const struct dp_mst_stream_allocation_table *table);
-+
-+	void (*set_mst_bandwidth)(
-+					struct stream_encoder *enc,
-+					struct fixed31_32 avg_time_slots_per_mtp);
- };
- 
- bool dc_construct_hw_sequencer(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0566-drm-amd-dal-Move-disabling-of-link-stream-to-dc_link.patch b/common/recipes-kernel/linux/files/0566-drm-amd-dal-Move-disabling-of-link-stream-to-dc_link.patch
deleted file mode 100644
index 41cd7e2d..00000000
--- a/common/recipes-kernel/linux/files/0566-drm-amd-dal-Move-disabling-of-link-stream-to-dc_link.patch
+++ /dev/null
@@ -1,287 +0,0 @@
-From ab87ad6d7fa27c5910f4ed67f13cc76660cb9ea4 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 2 Dec 2015 15:03:30 -0500
-Subject: [PATCH 0566/1110] drm/amd/dal: Move disabling of link & stream to
- dc_link
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 77 +++++++++++++++++++++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 72 ++------------------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  7 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  3 +
- 4 files changed, 87 insertions(+), 72 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index f29aea7..ad890a5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -983,7 +983,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- }
- 
- /****************************enable_link***********************************/
--enum dc_status core_link_enable(struct core_stream *stream)
-+static enum dc_status enable_link(struct core_stream *stream)
- {
- 	enum dc_status status;
- 	switch (stream->signal) {
-@@ -1020,7 +1020,7 @@ enum dc_status core_link_enable(struct core_stream *stream)
- 	return status;
- }
- 
--void core_link_disable(struct core_stream *stream)
-+static void disable_link(struct core_stream *stream)
- {
- 	/* TODO  dp_set_hw_test_pattern */
- 	struct dc *dc = stream->ctx->dc;
-@@ -1143,6 +1143,61 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 
- }
- 
-+static enum dc_status deallocate_mst_payload(struct core_stream *stream)
-+{
-+	struct core_link *link = stream->sink->link;
-+	struct link_encoder *link_encoder = link->link_enc;
-+	struct stream_encoder *stream_encoder = stream->stream_enc;
-+	struct dp_mst_stream_allocation_table table = {0};
-+	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
-+	uint8_t i;
-+	struct dc *dc = stream->ctx->dc;
-+
-+	/* deallocate_mst_payload is called before disable link. When mode or
-+	 * disable/enable monitor, new stream is created which is not in link
-+	 * stream[] yet. For this, payload is not allocated yet, so de-alloc
-+	 * should not done. For new mode set, map_resources will get engine
-+	 * for new stream, so stream_enc->id should be validated until here.
-+	 */
-+	if (link->enabled_stream_count == 0)
-+		return DC_OK;
-+
-+	for (i = 0; i < link->enabled_stream_count; i++) {
-+		if (link->enabled_streams[i] == stream)
-+			break;
-+	}
-+	/* stream is not in link stream list */
-+	if (i == link->enabled_stream_count)
-+		return DC_OK;
-+
-+	/* slot X.Y */
-+	dc->hwss.set_mst_bandwidth(
-+		stream_encoder,
-+		avg_time_slots_per_mtp);
-+
-+	/* TODO: which component is responsible for remove payload table? */
-+	dc_helpers_dp_mst_write_payload_allocation_table(
-+		stream->ctx,
-+		&stream->public,
-+		&table,
-+		false);
-+
-+	dc->hwss.update_mst_stream_allocation_table(
-+		link_encoder,
-+		&table);
-+
-+	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+			stream->ctx,
-+			&stream->public);
-+
-+	dc_helpers_dp_mst_send_payload_allocation(
-+			stream->ctx,
-+			&stream->public,
-+			false);
-+
-+	return DC_OK;
-+}
-+
- void core_link_enable_stream(
- 		struct core_link *link,
- 		struct core_stream *stream)
-@@ -1151,10 +1206,26 @@ void core_link_enable_stream(
- 
- 	dc->hwss.enable_stream(stream);
- 
--	if (DC_OK != core_link_enable(stream)) {
-+	if (DC_OK != enable_link(stream)) {
- 			BREAK_TO_DEBUGGER();
- 			return;
- 	}
- 	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		allocate_mst_payload(stream);
- }
-+
-+void core_link_disable_stream(
-+		struct core_link *link,
-+		struct core_stream *stream)
-+{
-+	struct dc *dc = stream->ctx->dc;
-+
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		deallocate_mst_payload(stream);
-+
-+	dc->hwss.disable_stream(stream);
-+
-+	disable_link(stream);
-+
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index fa71095..81935e5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -774,60 +774,6 @@ static enum color_space get_output_color_space(
- 	return color_space;
- }
- 
--static enum dc_status deallocate_mst_payload(struct core_stream *stream)
--{
--	struct core_link *link = stream->sink->link;
--	struct link_encoder *link_encoder = link->link_enc;
--	struct stream_encoder *stream_encoder = stream->stream_enc;
--	struct dp_mst_stream_allocation_table table = {0};
--	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
--	uint8_t i;
--
--	/* deallocate_mst_payload is called before disable link. When mode or
--	 * disable/enable monitor, new stream is created which is not in link
--	 * stream[] yet. For this, payload is not allocated yet, so de-alloc
--	 * should not done. For new mode set, map_resources will get engine
--	 * for new stream, so stream_enc->id should be validated until here.
--	 */
--	if (link->enabled_stream_count == 0)
--		return DC_OK;
--
--	for (i = 0; i < link->enabled_stream_count; i++) {
--		if (link->enabled_streams[i] == stream)
--			break;
--	}
--	/* stream is not in link stream list */
--	if (i == link->enabled_stream_count)
--		return DC_OK;
--
--	/* slot X.Y */
--	dce110_stream_encoder_set_mst_bandwidth(
--		stream_encoder,
--		avg_time_slots_per_mtp);
--
--	/* TODO: which component is responsible for remove payload table? */
--	dc_helpers_dp_mst_write_payload_allocation_table(
--		stream->ctx,
--		&stream->public,
--		&table,
--		false);
--
--	dce110_link_encoder_update_mst_stream_allocation_table(
--		link_encoder,
--		&table);
--
--	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
--			stream->ctx,
--			&stream->public);
--
--	dc_helpers_dp_mst_send_payload_allocation(
--			stream->ctx,
--			&stream->public,
--			false);
--
--	return DC_OK;
--}
--
- static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		struct validate_context *context,
- 		const struct dc *dc)
-@@ -841,9 +787,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	enum color_space color_space;
- 
- 	if (timing_changed) {
--
--		disable_stream(stream);
--		core_link_disable(stream);
-+		core_link_disable_stream(
-+				stream->sink->link, stream);
- 
- 		/*TODO: AUTO check if timing changed*/
- 		if (false == dal_clock_source_program_pix_clk(
-@@ -963,10 +908,7 @@ static void power_down_encoders(struct validate_context *context)
- 		target = context->targets[i];
- 		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 
--		if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
--			deallocate_mst_payload(stream);
--
--		core_link_disable(stream);
-+		core_link_disable_stream(stream->sink->link, stream);
- 	}
- }
- 
-@@ -1623,10 +1565,6 @@ static bool update_plane_address(
- static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 		struct validate_context *context)
- {
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
--		deallocate_mst_payload(stream);
--
--	disable_stream(stream);
- 	if (stream->audio) {
- 		dal_audio_disable_output(stream->audio,
- 				stream->stream_enc->id,
-@@ -1634,7 +1572,8 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 		stream->audio = NULL;
- 	}
- 
--	core_link_disable(stream);
-+	core_link_disable_stream(stream->sink->link, stream);
-+
- 	dce110_timing_generator_blank_crtc(stream->tg);
- 	dce110_timing_generator_disable_crtc(stream->tg);
- 	dce110_mem_input_deallocate_dmif_buffer(stream->mi, context->target_count);
-@@ -1798,6 +1737,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.enable_display_power_gating = dce110_enable_display_power_gating,
- 	.program_bw = dce110_program_bw,
- 	.enable_stream = enable_stream,
-+	.disable_stream = disable_stream,
- 	.update_mst_stream_allocation_table = dce110_link_encoder_update_mst_stream_allocation_table,
- 	.set_mst_bandwidth = dce110_stream_encoder_set_mst_bandwidth
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 299b13e..3781751 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -233,9 +233,6 @@ struct core_link {
- 
- struct core_link *link_create(const struct link_init_data *init_params);
- void link_destroy(struct core_link **link);
--enum dc_status core_link_enable(struct core_stream *stream);
--
--void core_link_disable(struct core_stream *stream);
- 
- enum dc_status dc_link_validate_mode_timing(
- 		const struct core_sink *sink,
-@@ -248,6 +245,10 @@ void core_link_enable_stream(
- 		struct core_link *link,
- 		struct core_stream *stream);
- 
-+void core_link_disable_stream(
-+		struct core_link *link,
-+		struct core_stream *stream);
-+
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 0502c4d..67cc020 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -157,6 +157,9 @@ struct hw_sequencer_funcs {
- 	void (*enable_stream)(
- 					struct core_stream *stream);
- 
-+	void (*disable_stream)(
-+					struct core_stream *stream);
-+
- 	void (*update_mst_stream_allocation_table)(
- 					struct link_encoder *enc,
- 					const struct dp_mst_stream_allocation_table *table);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0567-drm-amd-dal-Fix-issue-where-2nd-MST-display-didn-t-l.patch b/common/recipes-kernel/linux/files/0567-drm-amd-dal-Fix-issue-where-2nd-MST-display-didn-t-l.patch
deleted file mode 100644
index 8120f018..00000000
--- a/common/recipes-kernel/linux/files/0567-drm-amd-dal-Fix-issue-where-2nd-MST-display-didn-t-l.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From e95652d303d0fb9a09f11dc28195118bc65e8ad7 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 2 Dec 2015 22:38:58 -0500
-Subject: [PATCH 0567/1110] drm/amd/dal: Fix issue where 2nd MST display didn't
- light up
-
-Fix breakage caused by link encoder refactoring.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index ad890a5..44b3a2b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1022,9 +1022,10 @@ static enum dc_status enable_link(struct core_stream *stream)
- 
- static void disable_link(struct core_stream *stream)
- {
--	/* TODO  dp_set_hw_test_pattern */
- 	struct dc *dc = stream->ctx->dc;
- 
-+	/* TODO  dp_set_hw_test_pattern */
-+
- 	/* here we need to specify that encoder output settings
- 	 * need to be calculated as for the set mode,
- 	 * it will lead to querying dynamic link capabilities
-@@ -1039,9 +1040,10 @@ static void disable_link(struct core_stream *stream)
- 			dp_disable_link_phy_mst(
- 					stream->sink->link, stream);
- 		}
-+	} else {
-+		dc->hwss.encoder_disable_output(
-+				stream->sink->link->link_enc, stream->signal);
- 	}
--	dc->hwss.encoder_disable_output(
--		stream->sink->link->link_enc, stream->signal);
- }
- 
- enum dc_status dc_link_validate_mode_timing(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0568-drm-amd-dal-fix-incorrect-cursor-error-msg.patch b/common/recipes-kernel/linux/files/0568-drm-amd-dal-fix-incorrect-cursor-error-msg.patch
deleted file mode 100644
index fb5e4bb9..00000000
--- a/common/recipes-kernel/linux/files/0568-drm-amd-dal-fix-incorrect-cursor-error-msg.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 10396990f4bef04210419ce23b4997f696fb06af Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 3 Dec 2015 11:40:23 +0800
-Subject: [PATCH 0568/1110] drm/amd/dal: fix incorrect cursor error msg
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 19 +++++++++++++++----
- 1 file changed, 15 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 4c460c0..3b64ffe 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -115,13 +115,24 @@ static int dm_crtc_unpin_cursor_bo_old(
- 		ret  = amdgpu_bo_reserve(robj, false);
- 
- 		if (likely(ret == 0)) {
--			amdgpu_bo_unpin(robj);
-+			ret = amdgpu_bo_unpin(robj);
-+
-+			if (unlikely(ret != 0)) {
-+				DRM_ERROR(
-+					"%s: unpin failed (ret=%d), bo %p\n",
-+					__func__,
-+					ret,
-+					amdgpu_crtc->cursor_bo);
-+			}
-+
- 			amdgpu_bo_unreserve(robj);
--		}
--	} else {
--		DRM_ERROR("dm_crtc_unpin_cursor_ob_old bo %x, leaked %p\n",
-+		} else {
-+			DRM_ERROR(
-+				"%s: reserve failed (ret=%d), bo %p\n",
-+				__func__,
- 				ret,
- 				amdgpu_crtc->cursor_bo);
-+		}
- 	}
- 
- 	drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0569-drm-amd-dal-Add-support-for-flip-immediate.patch b/common/recipes-kernel/linux/files/0569-drm-amd-dal-Add-support-for-flip-immediate.patch
deleted file mode 100644
index 502d9a8e..00000000
--- a/common/recipes-kernel/linux/files/0569-drm-amd-dal-Add-support-for-flip-immediate.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 0c539fa4be268f4c03fea1de64cdc576d45f7943 Mon Sep 17 00:00:00 2001
-From: Aric Cyr <aric.cyr@amd.com>
-Date: Wed, 2 Dec 2015 18:08:18 -0500
-Subject: [PATCH 0569/1110] drm/amd/dal: Add support for flip-immediate
-
-Signed-off-by: Aric Cyr <aric.cyr@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 ++
- drivers/gpu/drm/amd/dal/dc/dc.h      | 2 +-
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e141e99..1eee73e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -683,6 +683,8 @@ void dc_flip_surface_addrs(struct dc* dc,
- 		 * then we'll have to awkwardly bypass the "const" surface.
- 		 */
- 		surface->public.address = flip_addrs[i].address;
-+		surface->public.flip_immediate = flip_addrs[i].flip_immediate;
-+
- 		dc->hwss.update_plane_address(
- 			surface,
- 			DC_TARGET_TO_CORE(surface->status.dc_target));
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 7b611d7..2d92d14 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -106,7 +106,7 @@ void dc_surface_release(const struct dc_surface *dc_surface);
-  */
- struct dc_flip_addrs {
- 	struct dc_plane_address address;
--
-+	bool flip_immediate;
- 	/* TODO: DCC format info */
- 	/* TODO: add flip duration for FreeSync */
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0570-drm-amd-dal-Modified-service-interface-for-pplib.patch b/common/recipes-kernel/linux/files/0570-drm-amd-dal-Modified-service-interface-for-pplib.patch
deleted file mode 100644
index a32c75d0..00000000
--- a/common/recipes-kernel/linux/files/0570-drm-amd-dal-Modified-service-interface-for-pplib.patch
+++ /dev/null
@@ -1,230 +0,0 @@
-From c483231e18b07c8330aeaffa8c1c69c1cba8e3ad Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Tue, 1 Dec 2015 09:19:28 -0500
-Subject: [PATCH 0570/1110] drm/amd/dal: Modified service interface for pplib.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    | 55 ++++++++++------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  2 +-
- drivers/gpu/drm/amd/dal/dc/dc_services.h           | 75 ++++++++++++----------
- 3 files changed, 76 insertions(+), 56 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index 3b97b64..b2886d2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -29,7 +29,6 @@
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/amdgpu_drm.h>
--
- #include "amdgpu.h"
- #include "dal_services.h"
- #include "amdgpu_dm.h"
-@@ -158,7 +157,7 @@ bool dc_service_pp_pre_dce_clock_change(
- 	return false;
- }
- 
--bool dc_service_pp_post_dce_clock_change(
-+bool dc_service_pp_apply_display_requirements(
- 		struct dc_context *ctx,
- 		const struct dc_pp_display_configuration *pp_display_cfg)
- {
-@@ -194,6 +193,7 @@ bool dc_service_pp_post_dce_clock_change(
- 		/* TODO: replace by a separate call to 'apply display cfg'? */
- 		amdgpu_pm_compute_clocks(adev);
- 	}
-+
- 	return true;
- #else
- 	return false;
-@@ -229,31 +229,46 @@ bool dc_service_get_system_clocks_range(
- }
- 
- 
--bool dc_service_get_clock_levels_by_type(
-+bool dc_service_pp_get_clock_levels_by_type(
- 		struct dc_context *ctx,
- 		enum dc_pp_clock_type clk_type,
--		struct dc_pp_clock_levels *clk_level_info)
-+		struct dc_pp_clock_levels *clks)
- {
--	/* TODO: follow implementation of:
--	 * PhwCz_GetClocksByType - powerplay\hwmgr\cz_hwmgr.c
--	 * PHM_GetClockByType - powerplay\hwmgr\hardwaremanager.c
--	 * PP_IRI_GetClockByType - powerplay\eventmgr\iri.c */
--
--	DRM_INFO("%s - not implemented\n", __func__);
--	return false;
--}
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+/* TODO: get clks from pplib.
-+	struct amdgpu_device *adev = ctx->driver_context;
- 
--bool dc_service_get_static_clocks(
--	struct dc_context *ctx,
--	struct dc_pp_static_clock_info *static_clk_info)
--{
--	/* TODO: follow implementation of:
--	 * PhwCz_GetDALPowerLevel - powerplay\hwmgr\cz_hwmgr.c
--	 * PHM_GetDALPowerLevel - powerplay\hwmgr\hardwaremanager.c
--	 * PP_IRI_GetStaticClocksInfo - powerplay\eventmgr\iri.c */
-+	return (amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle,
-+			(int)clk_type, (void *)clks) == 0);
-+			*/
-+	uint32_t disp_clks_in_hz[8] = {
-+			30000, 41143, 48000, 53334, 62609, 62609, 62609, 62609 };
-+	uint32_t sclks_in_hz[8] = {
-+			20000, 26667, 34286, 41143, 45000, 51429, 57600, 62609 };
-+	uint32_t mclks_in_hz[8] = { 33300, 80000, 0, 0, 0, 0, 0, 0 };
-+
-+	switch (clk_type) {
-+	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		clks->num_levels = 8;
-+		dc_service_memmove(clks->clocks_in_hz, disp_clks_in_hz, 8);
-+		break;
-+	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+		clks->num_levels = 8;
-+		dc_service_memmove(clks->clocks_in_hz, sclks_in_hz, 8);
-+		break;
-+	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+		clks->num_levels = 2;
-+		dc_service_memmove(clks->clocks_in_hz, mclks_in_hz, 8);
-+		break;
-+	default:
-+		return false;
-+	}
- 
-+	return true;
-+#else
- 	DRM_INFO("%s - not implemented\n", __func__);
- 	return false;
-+#endif
- }
- 
- /**** end of power component interfaces ****/
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 1eee73e..0b7c252 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -528,7 +528,7 @@ static void pplib_post_set_mode(
- 	pp_display_cfg.crtc_index = 0;
- 	pp_display_cfg.line_time_in_us = 0;
- 
--	dc_service_pp_post_dce_clock_change(dc->ctx, &pp_display_cfg);
-+	dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
- }
- 
- bool dc_commit_targets(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index 314ae58..3dcbc54 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -115,20 +115,6 @@ struct dc_pp_display_configuration {
- 	uint32_t line_time_in_us;
- };
- 
--enum dc_pp_clock_type {
--	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
--	DC_PP_CLOCK_TYPE_ENGINE_CLK,
--	DC_PP_CLOCK_TYPE_MEMORY_CLK
--};
--
--#define DC_PP_MAX_CLOCK_LEVELS 8
--
--struct dc_pp_clock_levels {
--	enum dc_pp_clock_type clock_type;
--	uint32_t num_levels;
--	uint32_t clocks_in_hz[DC_PP_MAX_CLOCK_LEVELS];
--};
--
- enum dc_pp_clocks_state {
- 	DC_PP_CLOCKS_STATE_INVALID = 0,
- 	DC_PP_CLOCKS_STATE_ULTRA_LOW,
-@@ -156,21 +142,6 @@ struct dc_pp_static_clock_info {
- 	enum dc_pp_clocks_state max_clocks_state;
- };
- 
--/* DAL calls this function to notify PP about completion of Mode Set.
-- * For PP it means that current DCE clocks are those which were returned
-- * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-- *
-- * If the clocks are higher than before, then PP does nothing.
-- *
-- * If the clocks are lower than before, then PP reduces the voltage.
-- *
-- * \returns	true - call is successful
-- *		false - call failed
-- */
--bool dc_service_pp_post_dce_clock_change(
--	struct dc_context *ctx,
--	const struct dc_pp_display_configuration *pp_display_cfg);
--
- /* The returned clocks range are 'static' system clocks which will be used for
-  * mode validation purposes.
-  *
-@@ -181,18 +152,52 @@ bool dc_service_get_system_clocks_range(
- 	struct dc_context *ctx,
- 	struct dal_system_clock_range *sys_clks);
- 
-+enum dc_pp_clock_type {
-+	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-+	DC_PP_CLOCK_TYPE_ENGINE_CLK,
-+	DC_PP_CLOCK_TYPE_MEMORY_CLK
-+};
-+
-+#define DC_PP_MAX_CLOCK_LEVELS 8
-+
-+struct dc_pp_clock_levels {
-+	uint32_t num_levels;
-+	uint32_t clocks_in_hz[DC_PP_MAX_CLOCK_LEVELS];
-+
-+	/* TODO: add latency
-+	 * do we need to know invalid (unsustainable boost) level for watermark
-+	 * programming? if not we can just report less elements in array
-+	 */
-+};
- 
--bool dc_service_get_clock_levels_by_type(
-+/* Gets valid clocks levels from pplib
-+ *
-+ * input: clk_type - display clk / sclk / mem clk
-+ *
-+ * output: array of valid clock levels for given type in ascending order,
-+ * with invalid levels filtered out
-+ *
-+ */
-+bool dc_service_pp_get_clock_levels_by_type(
- 	struct dc_context *ctx,
- 	enum dc_pp_clock_type clk_type,
- 	struct dc_pp_clock_levels *clk_level_info);
- 
--/* Use this for mode validation.
-- * TODO: when this interface is implemented on Linux, should we remove
-- * dc_service_get_system_clocks_range() ?? */
--bool dc_service_get_static_clocks(
-+
-+/* DAL calls this function to notify PP about completion of Mode Set.
-+ * For PP it means that current DCE clocks are those which were returned
-+ * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-+ *
-+ * If the clocks are higher than before, then PP does nothing.
-+ *
-+ * If the clocks are lower than before, then PP reduces the voltage.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dc_service_pp_apply_display_requirements(
- 	struct dc_context *ctx,
--	struct dc_pp_static_clock_info *static_clk_info);
-+	const struct dc_pp_display_configuration *pp_display_cfg);
- 
- 
- /****** end of PP interfaces ******/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0571-drm-amd-dal-fix-hotplug-of-HDMI-display-with-DP-MST.patch b/common/recipes-kernel/linux/files/0571-drm-amd-dal-fix-hotplug-of-HDMI-display-with-DP-MST.patch
deleted file mode 100644
index 4d17abb4..00000000
--- a/common/recipes-kernel/linux/files/0571-drm-amd-dal-fix-hotplug-of-HDMI-display-with-DP-MST.patch
+++ /dev/null
@@ -1,188 +0,0 @@
-From 3c7852bb487f519596c4ac96c4a5c40fd2e66984 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 3 Dec 2015 19:17:12 +0800
-Subject: [PATCH 0571/1110] drm/amd/dal: fix hotplug of HDMI display with DP
- MST
-
-Segfault happens in the following case:
-we are about to get set mode for connector who's only
-possible crtc (in encoder crtc mask) is already used by
-MST connector, that is why DRM will try to
-re-assing crtcs in order to make configuration
-supported. For our implementation we need to make all
-encoders support all crtcs (added function to initilize mask properly),
-then this issue will never arise again.
-
-Added sanity check for non NULL connector state. This check
-should be needed when used with actual drm_atomic_commit ioctl in future.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 16 +---
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 86 ++++++++++++++++------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |  2 +
- 3 files changed, 65 insertions(+), 39 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 86c17e6..9e41114 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -228,21 +228,7 @@ dm_dp_create_fake_mst_encoder(struct amdgpu_connector *connector)
- 		return NULL;
- 
- 	encoder = &amdgpu_encoder->base;
--	switch (adev->mode_info.num_crtc) {
--	case 1:
--		encoder->possible_crtcs = 0x1;
--		break;
--	case 2:
--	default:
--		encoder->possible_crtcs = 0x3;
--		break;
--	case 4:
--		encoder->possible_crtcs = 0xf;
--		break;
--	case 6:
--		encoder->possible_crtcs = 0x3f;
--		break;
--	}
-+	encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
- 
- 	drm_encoder_init(
- 		dev,
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 3b64ffe..6dc7ead 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1860,19 +1860,40 @@ int amdgpu_dm_connector_init(
- 	return 0;
- }
- 
-+int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
-+{
-+	switch (adev->mode_info.num_crtc) {
-+	case 1:
-+		return 0x1;
-+	case 2:
-+		return 0x3;
-+	case 3:
-+		return 0x7;
-+	case 4:
-+		return 0xf;
-+	case 5:
-+		return 0x1f;
-+	case 6:
-+	default:
-+		return 0x3f;
-+	}
-+}
-+
- int amdgpu_dm_encoder_init(
- 	struct drm_device *dev,
- 	struct amdgpu_encoder *aencoder,
- 	uint32_t link_index,
- 	struct amdgpu_crtc *acrtc)
- {
-+	struct amdgpu_device *adev = dev->dev_private;
-+
- 	int res = drm_encoder_init(dev,
- 				   &aencoder->base,
- 				   &amdgpu_dm_encoder_funcs,
- 				   DRM_MODE_ENCODER_TMDS,
- 				   NULL);
- 
--	aencoder->base.possible_crtcs = 1 << link_index;
-+	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
- 
- 	if (!res)
- 		aencoder->encoder_id = link_index;
-@@ -2204,32 +2225,49 @@ int amdgpu_dm_atomic_commit(
- 		struct drm_crtc *crtc = plane_state->crtc;
- 		struct drm_framebuffer *fb = plane_state->fb;
- 		struct drm_connector *connector;
-+		struct dm_connector_state *dm_state = NULL;
- 
--		if (fb && crtc && crtc->state->planes_changed) {
--			struct dm_connector_state *dm_state = NULL;
--
--			if (page_flip_needed(
--				plane_state,
--				old_plane_state))
--				amdgpu_crtc_page_flip(
--					crtc,
--					fb,
--					crtc->state->event,
--					0);
--			else {
--				list_for_each_entry(connector,
--						&dev->mode_config.connector_list, head)	{
--					if (connector->state->crtc == crtc) {
--						dm_state = to_dm_connector_state(connector->state);
--						break;
--					}
--				}
-+		if (!fb || !crtc || !crtc->state->planes_changed)
-+			continue;
- 
--				dm_dc_surface_commit(
--					dm->dc,
--					crtc,
--					dm_state);
-+		if (page_flip_needed(
-+			plane_state,
-+			old_plane_state))
-+			amdgpu_crtc_page_flip(
-+				crtc,
-+				fb,
-+				crtc->state->event,
-+				0);
-+		else {
-+			list_for_each_entry(connector,
-+				&dev->mode_config.connector_list, head)	{
-+				if (connector->state->crtc == crtc) {
-+					dm_state = to_dm_connector_state(connector->state);
-+					break;
-+				}
- 			}
-+
-+			/*
-+			 * This situation happens in the following case:
-+			 * we are about to get set mode for connector who's only
-+			 * possible crtc (in encoder crtc mask) is used by
-+			 * another connector, that is why it will try to
-+			 * re-assing crtcs in order to make configuration
-+			 * supported. For our implementation we need to make all
-+			 * encoders support all crtcs, then this issue will
-+			 * never arise again. But to guard code from this issue
-+			 * check is left.
-+			 *
-+			 * Also it should be needed when used with actual
-+			 * drm_atomic_commit ioctl in future
-+			 */
-+			if (!dm_state)
-+				continue;
-+
-+			dm_dc_surface_commit(
-+				dm->dc,
-+				crtc,
-+				dm_state);
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 0df4636..0639732 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -83,6 +83,8 @@ int amdgpu_dm_connector_atomic_set_property(
- 	struct drm_property *property,
- 	uint64_t val);
- 
-+int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
-+
- extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
- 
- #endif		/* __AMDGPU_DM_TYPES_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0572-drm-amd-dal-temporary-fix-for-MST-chaing-disconnect.patch b/common/recipes-kernel/linux/files/0572-drm-amd-dal-temporary-fix-for-MST-chaing-disconnect.patch
deleted file mode 100644
index 80a914ad..00000000
--- a/common/recipes-kernel/linux/files/0572-drm-amd-dal-temporary-fix-for-MST-chaing-disconnect.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 4617b27b7d395c4b7c885030e6b41623ddd5581f Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 3 Dec 2015 19:22:04 +0800
-Subject: [PATCH 0572/1110] drm/amd/dal: temporary fix for MST chaing
- disconnect
-
-Unplug of MST chain happened (two displays),
-payload allocation table is empty on first reset mode,
-and cause 0 division in avg_time_slots_per_mtp calculation
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 44b3a2b..8dc3af2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1116,6 +1116,15 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 		&table,
- 		true);
- 
-+	/*
-+	 * temporary fix. Unplug of MST chain happened (two displays),
-+	 * table is empty on first reset mode, and cause 0 division in
-+	 * avg_time_slots_per_mtp calculation
-+	 */
-+
-+	if (table.stream_count == 0)
-+		return DC_OK;
-+
- 	/* program DP source TX for payload */
- 	dc->hwss.update_mst_stream_allocation_table(
- 		link_encoder,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0573-drm-amd-dal-add-single-display-infor-to-notify-pplib.patch b/common/recipes-kernel/linux/files/0573-drm-amd-dal-add-single-display-infor-to-notify-pplib.patch
deleted file mode 100644
index 8b426c98..00000000
--- a/common/recipes-kernel/linux/files/0573-drm-amd-dal-add-single-display-infor-to-notify-pplib.patch
+++ /dev/null
@@ -1,622 +0,0 @@
-From 9c05026f1eca2f9a6d1aeb97c6130f9848cdfa97 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 3 Dec 2015 14:13:20 -0500
-Subject: [PATCH 0573/1110] drm/amd/dal: add single display infor to notify
- pplib with
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    |  6 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 94 ++++++++++++++++------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 76 +++++++++++++----
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  3 +-
- drivers/gpu/drm/amd/dal/dc/dc_services.h           | 30 +++++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     |  4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  4 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 20 ++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   |  4 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  2 +
- 11 files changed, 170 insertions(+), 77 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index b2886d2..fd54703 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -158,7 +158,7 @@ bool dc_service_pp_pre_dce_clock_change(
- }
- 
- bool dc_service_pp_apply_display_requirements(
--		struct dc_context *ctx,
-+		const struct dc_context *ctx,
- 		const struct dc_pp_display_configuration *pp_display_cfg)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
-@@ -201,7 +201,7 @@ bool dc_service_pp_apply_display_requirements(
- }
- 
- bool dc_service_get_system_clocks_range(
--		struct dc_context *ctx,
-+		const struct dc_context *ctx,
- 		struct dal_system_clock_range *sys_clks)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
-@@ -230,7 +230,7 @@ bool dc_service_get_system_clocks_range(
- 
- 
- bool dc_service_pp_get_clock_levels_by_type(
--		struct dc_context *ctx,
-+		const struct dc_context *ctx,
- 		enum dc_pp_clock_type clk_type,
- 		struct dc_pp_clock_levels *clks)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 0b7c252..57277ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -40,6 +40,8 @@
- #include "include/irq_service_interface.h"
- 
- #include "link_hwss.h"
-+#include "opp.h"
-+#include "link_encoder.h"
- 
- /*******************************************************************************
-  * Private structures
-@@ -462,40 +464,81 @@ static bool targets_changed(
- 	return false;
- }
- 
--
--static uint32_t get_min_vblank_time_us(const struct validate_context *context)
-+static uint32_t get_min_vblank_time_us(const struct validate_context* context)
- {
- 	uint8_t i, j;
- 	uint32_t min_vertical_blank_time = -1;
- 	for (i = 0; i < context->target_count; i++) {
--		const struct core_target *target = context->targets[i];
-+		const struct core_target* target = context->targets[i];
- 		for (j = 0; j < target->public.stream_count; j++) {
--			const struct dc_stream *stream =
-+			const struct dc_stream* stream =
- 						target->public.streams[j];
- 			uint32_t vertical_blank_in_pixels = 0;
- 			uint32_t vertical_blank_time = 0;
--
- 			vertical_blank_in_pixels = stream->timing.h_total *
- 				(stream->timing.v_total
--				- stream->timing.v_addressable);
--			/*TODO: - vertical timing overscan if we still support*/
--			vertical_blank_time = vertical_blank_in_pixels * 1000
--				/ stream->timing.pix_clk_khz;
--			/*TODO: doublescan doubles, pixel repetition mults*/
--
-+					- stream->timing.v_addressable);
-+			vertical_blank_time = vertical_blank_in_pixels
-+				* 1000 / stream->timing.pix_clk_khz;
- 			if (min_vertical_blank_time > vertical_blank_time)
- 				min_vertical_blank_time = vertical_blank_time;
- 		}
- 	}
--
- 	return min_vertical_blank_time;
- }
- 
--static void pplib_post_set_mode(
--	struct dc *dc,
-+static void fill_display_configs(
-+	const struct validate_context* context,
-+	struct dc_pp_display_configuration *pp_display_cfg)
-+{
-+	uint8_t i, j;
-+	uint8_t num_cfgs = 0;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		const struct core_target* target = context->targets[i];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct core_stream *stream =
-+			DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct dc_pp_single_disp_config *cfg =
-+					&pp_display_cfg->disp_configs[num_cfgs];
-+
-+			num_cfgs++;
-+			cfg->signal = stream->signal;
-+			cfg->pipe_idx = stream->opp->inst;
-+			cfg->src_height = stream->public.src.height;
-+			cfg->src_width = stream->public.src.width;
-+			cfg->ddi_channel_mapping =
-+				stream->sink->link->ddi_channel_mapping.raw;
-+			cfg->transmitter =
-+				stream->sink->link->link_enc->transmitter;
-+			cfg->link_settings =
-+					stream->sink->link->cur_link_settings;
-+			cfg->sym_clock = stream->public.timing.pix_clk_khz;
-+			switch (stream->public.timing.display_color_depth) {
-+			case COLOR_DEPTH_101010:
-+				cfg->sym_clock = (cfg->sym_clock * 30) / 24;
-+				break;
-+			case COLOR_DEPTH_121212:
-+				cfg->sym_clock = (cfg->sym_clock * 36) / 24;
-+				break;
-+			case COLOR_DEPTH_161616:
-+				cfg->sym_clock = (cfg->sym_clock * 48) / 24;
-+				break;
-+			default:
-+				break;
-+			}
-+			/* TODO: unhardcode*/
-+			cfg->v_refresh = 60;
-+		}
-+	}
-+	pp_display_cfg->display_count = num_cfgs;
-+}
-+
-+static void pplib_apply_display_requirements(
-+	const struct dc *dc,
- 	const struct validate_context *context)
- {
--	uint8_t i;
- 	struct dc_pp_display_configuration pp_display_cfg = { 0 };
- 
- 	pp_display_cfg.nb_pstate_switch_disable =
-@@ -507,11 +550,6 @@ static void pplib_post_set_mode(
- 	pp_display_cfg.cpu_pstate_separation_time =
- 			context->bw_results.blackout_recovery_time_us;
- 
--	pp_display_cfg.max_displays = dc->link_count;
--	for (i = 0; i < context->target_count; i++)
--		pp_display_cfg.active_displays +=
--				context->targets[i]->public.stream_count;
--
- 	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk;
- 	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
- 	pp_display_cfg.min_engine_clock_deep_sleep_khz
-@@ -524,9 +562,17 @@ static void pplib_post_set_mode(
- 
- 	pp_display_cfg.disp_clk_khz = context->bw_results.dispclk_khz;
- 
--	/* TODO: unhardcode, is this still applicable?*/
--	pp_display_cfg.crtc_index = 0;
--	pp_display_cfg.line_time_in_us = 0;
-+	fill_display_configs(context, &pp_display_cfg);
-+
-+	/* TODO: is this still applicable?*/
-+	if (pp_display_cfg.display_count == 1) {
-+		const struct dc_crtc_timing *timing =
-+			&context->targets[0]->public.streams[0]->timing;
-+		pp_display_cfg.crtc_index =
-+			pp_display_cfg.disp_configs[0].pipe_idx;
-+		pp_display_cfg.line_time_in_us = timing->h_total * 1000
-+							/ timing->pix_clk_khz;
-+	}
- 
- 	dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
- }
-@@ -613,7 +659,7 @@ bool dc_commit_targets(
- 
- 	program_timing_sync(dc->ctx, context);
- 
--	pplib_post_set_mode(dc, context);
-+	pplib_apply_display_requirements(dc, context);
- 
- 	/* TODO: disable unused plls*/
- fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 8dc3af2..ac39dff 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -654,20 +654,23 @@ static bool construct(
- 	struct core_link *link,
- 	const struct link_init_data *init_params)
- {
-+	uint8_t i;
-+	struct adapter_service *as = init_params->adapter_srv;
- 	struct irq *hpd_gpio = NULL;
- 	struct ddc_service_init_data ddc_service_init_data = { 0 };
- 	struct dc_context *dc_ctx = init_params->ctx;
- 	struct encoder_init_data enc_init_data = { 0 };
- 	struct connector_feature_support cfs = { 0 };
-+	struct integrated_info info = {{{ 0 }}};
- 
- 	link->dc = init_params->dc;
--	link->adapter_srv = init_params->adapter_srv;
-+	link->adapter_srv = as;
- 	link->connector_index = init_params->connector_index;
- 	link->ctx = dc_ctx;
- 	link->link_index = init_params->link_index;
- 
- 	link->link_id = dal_adapter_service_get_connector_obj_id(
--			init_params->adapter_srv,
-+			as,
- 			init_params->connector_index);
- 
- 	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
-@@ -691,28 +694,28 @@ static bool construct(
- 	case CONNECTOR_ID_DISPLAY_PORT:
- 		link->public.connector_signal =	SIGNAL_TYPE_DISPLAY_PORT;
- 		hpd_gpio = dal_adapter_service_obtain_hpd_irq(
--					init_params->adapter_srv,
-+					as,
- 					link->link_id);
- 
- 		if (hpd_gpio != NULL) {
- 			link->public.irq_source_hpd_rx =
- 					dal_irq_get_rx_source(hpd_gpio);
- 			dal_adapter_service_release_irq(
--					init_params->adapter_srv, hpd_gpio);
-+					as, hpd_gpio);
- 		}
- 
- 		break;
- 	case CONNECTOR_ID_EDP:
- 		link->public.connector_signal = SIGNAL_TYPE_EDP;
- 		hpd_gpio = dal_adapter_service_obtain_hpd_irq(
--					init_params->adapter_srv,
-+					as,
- 					link->link_id);
- 
- 		if (hpd_gpio != NULL) {
- 			link->public.irq_source_hpd_rx =
- 					dal_irq_get_rx_source(hpd_gpio);
- 			dal_adapter_service_release_irq(
--					init_params->adapter_srv, hpd_gpio);
-+					as, hpd_gpio);
- 		}
- 		break;
- 	default:
-@@ -726,26 +729,21 @@ static bool construct(
- 	LINK_INFO("Connector[%d] description:\n",
- 			init_params->connector_index);
- 
--	link->connector = dal_connector_create(dc_ctx,
--			init_params->adapter_srv,
--			link->link_id);
-+	link->connector = dal_connector_create(dc_ctx, as, link->link_id);
- 	if (NULL == link->connector) {
- 		DC_ERROR("Failed to create connector object!\n");
- 		goto create_fail;
- 	}
- 
- 
--	hpd_gpio = dal_adapter_service_obtain_hpd_irq(
--			init_params->adapter_srv,
--			link->link_id);
-+	hpd_gpio = dal_adapter_service_obtain_hpd_irq(as, link->link_id);
- 
- 	if (hpd_gpio != NULL) {
- 		link->public.irq_source_hpd = dal_irq_get_source(hpd_gpio);
--		dal_adapter_service_release_irq(
--					init_params->adapter_srv, hpd_gpio);
-+		dal_adapter_service_release_irq(as, hpd_gpio);
- 	}
- 
--	ddc_service_init_data.as = link->adapter_srv;
-+	ddc_service_init_data.as = as;
- 	ddc_service_init_data.ctx = link->ctx;
- 	ddc_service_init_data.id = link->link_id;
- 	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
-@@ -757,10 +755,10 @@ static bool construct(
- 
- 	dal_connector_get_features(link->connector, &cfs);
- 
--	enc_init_data.adapter_service = link->adapter_srv;
-+	enc_init_data.adapter_service = as;
- 	enc_init_data.ctx = dc_ctx;
- 	enc_init_data.encoder = dal_adapter_service_get_src_obj(
--					link->adapter_srv, link->link_id, 0);
-+							as, link->link_id, 0);
- 	enc_init_data.connector = link->link_id;
- 	enc_init_data.channel = cfs.ddc_line;
- 	enc_init_data.hpd_source = cfs.hpd_line;
-@@ -771,6 +769,50 @@ static bool construct(
- 		goto create_fail;
- 	}
- 
-+	if (!dal_adapter_service_get_integrated_info(as, &info)) {
-+		DC_ERROR("Failed to get integrated info!\n");
-+		goto create_fail;
-+	}
-+
-+	for (i = 0; ; i++) {
-+		if (!dal_adapter_service_get_device_tag(
-+				as, link->link_id, i, &link->device_tag)) {
-+			DC_ERROR("Failed to find device tag!\n");
-+			goto create_fail;
-+		}
-+
-+		/* Look for device tag that matches connector signal,
-+		 * CRT for rgb, LCD for other supported signal tyes
-+		 */
-+		if (!dal_adapter_service_is_device_id_supported(
-+						as, link->device_tag.dev_id))
-+			continue;
-+		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
-+			&& link->public.connector_signal != SIGNAL_TYPE_RGB)
-+			continue;
-+		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
-+			&& link->public.connector_signal == SIGNAL_TYPE_RGB)
-+			continue;
-+		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_WIRELESS
-+			&& link->public.connector_signal != SIGNAL_TYPE_WIRELESS)
-+			continue;
-+		break;
-+	}
-+
-+	/* Look for channel mapping corresponding to connector and device tag */
-+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
-+		struct external_display_path *path =
-+			&info.ext_disp_conn_info.path[i];
-+		if (path->device_connector_id.enum_id == link->link_id.enum_id
-+			&& path->device_connector_id.id == link->link_id.id
-+			&& path->device_connector_id.type == link->link_id.type
-+			&& path->device_acpi_enum
-+					== link->device_tag.acpi_device) {
-+			link->ddi_channel_mapping = path->channel_mapping;
-+			break;
-+		}
-+	}
-+
- 	/*
- 	 * TODO check if GPIO programmed correctly
- 	 *
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 2d92d14..df76992 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -437,7 +437,6 @@ bool dc_write_dpcd(
- 		uint32_t link_index,
- 		uint32_t address,
- 		uint8_t *data,
--		uint32_t size);
--
-+	uint32_t size);
- 
- #endif /* DC_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index 3dcbc54..c2172ea 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -32,10 +32,11 @@
- 
- /* TODO: remove when DC is complete. */
- #include "dal_services_types.h"
--#include "include/dal_types.h"
- #include "logger_interface.h"
-+#include "include/dal_types.h"
- #include "irq_types.h"
- #include "dal_power_interface_types.h"
-+#include "link_service_types.h"
- 
- /* if the pointer is not NULL, the allocated memory is zeroed */
- void *dc_service_alloc(struct dc_context *ctx, uint32_t size);
-@@ -87,15 +88,25 @@ bool dc_service_pp_pre_dce_clock_change(
- 	struct dal_to_power_info *input,
- 	struct power_to_dal_info *output);
- 
-+struct dc_pp_single_disp_config
-+{
-+	enum signal_type signal;
-+	uint8_t transmitter;
-+	uint8_t ddi_channel_mapping;
-+	uint8_t pipe_idx;
-+	uint32_t src_height;
-+	uint32_t src_width;
-+	uint32_t v_refresh;
-+	uint32_t sym_clock; /* HDMI only */
-+	struct link_settings link_settings; /* DP only */
-+};
-+
- struct dc_pp_display_configuration {
- 	bool nb_pstate_switch_disable;/* controls NB PState switch */
- 	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
- 	bool cpu_pstate_disable;
- 	uint32_t cpu_pstate_separation_time;
- 
--	uint32_t max_displays;
--	uint32_t active_displays;
--
- 	/* 10khz steps */
- 	uint32_t min_memory_clock_khz;
- 	uint32_t min_engine_clock_khz;
-@@ -108,9 +119,12 @@ struct dc_pp_display_configuration {
- 
- 	bool all_displays_in_sync;
- 
-+	uint8_t display_count;
-+	struct dc_pp_single_disp_config disp_configs[3];
-+
- 	/*Controller Index of primary display - used in MCLK SMC switching hang
- 	 * SW Workaround*/
--	uint32_t crtc_index;
-+	uint8_t crtc_index;
- 	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
- 	uint32_t line_time_in_us;
- };
-@@ -149,7 +163,7 @@ struct dc_pp_static_clock_info {
-  *		false - call failed
-  */
- bool dc_service_get_system_clocks_range(
--	struct dc_context *ctx,
-+	const struct dc_context *ctx,
- 	struct dal_system_clock_range *sys_clks);
- 
- enum dc_pp_clock_type {
-@@ -179,7 +193,7 @@ struct dc_pp_clock_levels {
-  *
-  */
- bool dc_service_pp_get_clock_levels_by_type(
--	struct dc_context *ctx,
-+	const struct dc_context *ctx,
- 	enum dc_pp_clock_type clk_type,
- 	struct dc_pp_clock_levels *clk_level_info);
- 
-@@ -196,7 +210,7 @@ bool dc_service_pp_get_clock_levels_by_type(
-  *		false - call failed
-  */
- bool dc_service_pp_apply_display_requirements(
--	struct dc_context *ctx,
-+	const struct dc_context *ctx,
- 	const struct dc_pp_display_configuration *pp_display_cfg);
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-index 04105ed..f45da2e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -48,14 +48,14 @@ bool dce110_ipp_construct(
- 	struct dc_context *ctx,
- 	uint32_t inst)
- {
--	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+	if (inst >= ARRAY_SIZE(reg_offsets))
- 		return false;
- 
- 	ipp->base.ctx = ctx;
- 
- 	ipp->base.inst = inst;
- 
--	ipp->offsets = reg_offsets[inst-1];
-+	ipp->offsets = reg_offsets[inst];
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index f7ef317..ab2241d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -931,14 +931,14 @@ bool dce110_mem_input_construct(
- 	struct dc_context *ctx,
- 	uint32_t inst)
- {
--	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+	if (inst >= ARRAY_SIZE(reg_offsets))
- 		return false;
- 
- 	mem_input110->base.ctx = ctx;
- 
- 	mem_input110->base.inst = inst;
- 
--	mem_input110->offsets = reg_offsets[inst - 1];
-+	mem_input110->offsets = reg_offsets[inst];
- 
- 	mem_input110->supported_stutter_mode = 0;
- 	dal_adapter_service_get_feature_value(FEATURE_STUTTER_MODE,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 0fdffac..410b52f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -106,14 +106,14 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
- 	struct dc_context *ctx,
- 	uint32_t inst)
- {
--	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+	if (inst >= ARRAY_SIZE(reg_offsets))
- 		return false;
- 
- 	opp110->base.ctx = ctx;
- 
- 	opp110->base.inst = inst;
- 
--	opp110->offsets = reg_offsets[inst - 1];
-+	opp110->offsets = reg_offsets[inst];
- 
- 	opp110->regamma.hw_points_num = 128;
- 	opp110->regamma.coordinates_x = NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index e206802..45a069a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -120,18 +120,14 @@ bool dce110_construct_resource_pool(
- 
- 	for (i = 0; i < pool->controller_count; i++) {
- 		pool->timing_generators[i] = dce110_timing_generator_create(
--				adapter_serv,
--				ctx,
--				i + 1);
-+				adapter_serv, ctx, i + 1);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error("DC: failed to create tg!\n");
- 			goto controller_create_fail;
- 		}
- 
--		pool->mis[i] = dce110_mem_input_create(
--			ctx,
--			i + 1);
-+		pool->mis[i] = dce110_mem_input_create(ctx, i);
- 		if (pool->mis[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-@@ -139,9 +135,7 @@ bool dce110_construct_resource_pool(
- 			goto controller_create_fail;
- 		}
- 
--		pool->ipps[i] = dce110_ipp_create(
--			ctx,
--			i + 1);
-+		pool->ipps[i] = dce110_ipp_create(ctx, i);
- 		if (pool->ipps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-@@ -149,9 +143,7 @@ bool dce110_construct_resource_pool(
- 			goto controller_create_fail;
- 		}
- 
--		pool->transforms[i] = dce110_transform_create(
--				ctx,
--				i + 1);
-+		pool->transforms[i] = dce110_transform_create(ctx, i);
- 		if (pool->transforms[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-@@ -162,9 +154,7 @@ bool dce110_construct_resource_pool(
- 				pool->transforms[i],
- 				pool->scaler_filter);
- 
--		pool->opps[i] = dce110_opp_create(
--			ctx,
--			i + 1);
-+		pool->opps[i] = dce110_opp_create(ctx, i);
- 		if (pool->opps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-index f3b3630..a7648e5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -67,14 +67,14 @@ bool dce110_transform_construct(
- 	struct dc_context *ctx,
- 	uint32_t inst)
- {
--	if ((inst < 1) || (inst > ARRAY_SIZE(reg_offsets)))
-+	if (inst >= ARRAY_SIZE(reg_offsets))
- 		return false;
- 
- 	xfm110->base.ctx = ctx;
- 
- 	xfm110->base.inst = inst;
- 
--	xfm110->offsets = reg_offsets[inst - 1];
-+	xfm110->offsets = reg_offsets[inst];
- 
- 	xfm110->lb_pixel_depth_supported =
- 			LB_PIXEL_DEPTH_18BPP |
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 3781751..a728446 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -211,6 +211,8 @@ struct core_link {
- 	struct link_encoder *link_enc;
- 	struct ddc_service *ddc;
- 	struct graphics_object_id link_id;
-+	union ddi_channel_mapping ddi_channel_mapping;
-+	struct connector_device_tag_info device_tag;
- 	/* caps is the same as reported_link_cap. link_traing use
- 	 * reported_link_cap. Will clean up.  TODO */
- 	struct link_settings reported_link_cap;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0574-drm-amd-dal-Call-atomic-dpms-function-for-MST.patch b/common/recipes-kernel/linux/files/0574-drm-amd-dal-Call-atomic-dpms-function-for-MST.patch
deleted file mode 100644
index d3904b31..00000000
--- a/common/recipes-kernel/linux/files/0574-drm-amd-dal-Call-atomic-dpms-function-for-MST.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 3ba7399178fbd241da609dfb01080ed9ac55c88c Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 3 Dec 2015 15:36:20 -0500
-Subject: [PATCH 0574/1110] drm/amd/dal: Call atomic dpms function for MST
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ++-------
- 1 file changed, 2 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 9e41114..df80f5c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -23,6 +23,7 @@
-  *
-  */
- 
-+#include <drm/drm_atomic_helper.h>
- #include "dal_services.h"
- #include "amdgpu.h"
- #include "amdgpu_dm_types.h"
-@@ -82,14 +83,8 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector)
- 	kfree(amdgpu_connector);
- }
- 
--static int dm_dp_mst_connector_dpms(struct drm_connector *connector, int mode)
--{
--	DRM_DEBUG_KMS("\n");
--	return 0;
--}
--
- static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
--	.dpms = dm_dp_mst_connector_dpms,
-+	.dpms = drm_atomic_helper_connector_dpms,
- 	.detect = dm_dp_mst_detect,
- 	.fill_modes = drm_helper_probe_single_connector_modes,
- 	.destroy = dm_dp_mst_connector_destroy,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0575-drm-amd-dal-amd-dc-Implement-get-memory-and-engine-c.patch b/common/recipes-kernel/linux/files/0575-drm-amd-dal-amd-dc-Implement-get-memory-and-engine-c.patch
deleted file mode 100644
index a3f305ba..00000000
--- a/common/recipes-kernel/linux/files/0575-drm-amd-dal-amd-dc-Implement-get-memory-and-engine-c.patch
+++ /dev/null
@@ -1,179 +0,0 @@
-From a5e65a3bdc11c64a135c4312bf79c6b7baf879c2 Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Thu, 3 Dec 2015 13:48:04 -0500
-Subject: [PATCH 0575/1110] drm/amd/dal: amd/dc Implement get memory and engine
- clocks from PPLib
-
-Added comments for clocks: PPLib uses tens of kHz, DM uses kHz,
-but DC does in fixed point MHz
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    | 53 ++++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 45 +++++++++++++++---
- drivers/gpu/drm/amd/dal/dc/dc_services.h           |  2 +-
- 3 files changed, 73 insertions(+), 27 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index fd54703..2c02d18 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -234,43 +234,58 @@ bool dc_service_pp_get_clock_levels_by_type(
- 		enum dc_pp_clock_type clk_type,
- 		struct dc_pp_clock_levels *clks)
- {
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--/* TODO: get clks from pplib.
-+
-+/*
-+ #ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if(amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle,
-+		(int)clk_type, (void *)clks) == fail
-+		PPlib return clocks in tens of kHz
-+		divide by 10 & push to the clks which kHz
-+#endif
-+*/
-+
- 	struct amdgpu_device *adev = ctx->driver_context;
- 
--	return (amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle,
--			(int)clk_type, (void *)clks) == 0);
--			*/
--	uint32_t disp_clks_in_hz[8] = {
--			30000, 41143, 48000, 53334, 62609, 62609, 62609, 62609 };
--	uint32_t sclks_in_hz[8] = {
--			20000, 26667, 34286, 41143, 45000, 51429, 57600, 62609 };
--	uint32_t mclks_in_hz[8] = { 33300, 80000, 0, 0, 0, 0, 0, 0 };
-+	uint32_t disp_clks_in_khz[8] = {
-+	300000, 411430, 480000, 533340, 626090, 626090, 626090, 626090 };
-+	uint32_t sclks_in_khz[8] = {
-+	200000, 266670, 342860, 411430, 450000, 514290, 576000, 626090 };
-+	uint32_t mclks_in_khz[8] = { 333000, 800000 };
-+
-+	struct amd_pp_dal_clock_info info = {0};
- 
- 	switch (clk_type) {
- 	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
- 		clks->num_levels = 8;
--		dc_service_memmove(clks->clocks_in_hz, disp_clks_in_hz, 8);
-+		dc_service_memmove(clks->clocks_in_khz, disp_clks_in_khz,
-+				sizeof(disp_clks_in_khz));
- 		break;
- 	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
- 		clks->num_levels = 8;
--		dc_service_memmove(clks->clocks_in_hz, sclks_in_hz, 8);
-+		dc_service_memmove(clks->clocks_in_khz, sclks_in_khz,
-+				sizeof(sclks_in_khz));
- 		break;
- 	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
- 		clks->num_levels = 2;
--		dc_service_memmove(clks->clocks_in_hz, mclks_in_hz, 8);
-+		dc_service_memmove(clks->clocks_in_khz, mclks_in_khz,
-+				sizeof(mclks_in_khz));
- 		break;
- 	default:
- 		return false;
- 	}
--
--	return true;
--#else
--	DRM_INFO("%s - not implemented\n", __func__);
--	return false;
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (clk_type ==  DC_PP_CLOCK_TYPE_ENGINE_CLK ||
-+		clk_type ==  DC_PP_CLOCK_TYPE_DISPLAY_CLK) {
-+		if (0 == amd_powerplay_get_display_power_level(
-+				adev->powerplay.pp_handle, &info) &&
-+				info.level < clks->num_levels) {
-+		/*if the max possible power level less then use smaller*/
-+			clks->num_levels = info.level;
-+		}
-+	}
- #endif
-+	return true;
- }
--
- /**** end of power component interfaces ****/
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 57277ed..599bf2f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -226,9 +226,45 @@ static struct adapter_service *create_as(
- 
- static void bw_calcs_data_update_from_pplib(struct dc *dc)
- {
--	struct dal_system_clock_range clk_range = { 0 };
-+	struct dc_pp_clock_levels clks = {0};
- 
--	dc_service_get_system_clocks_range(dc->ctx, &clk_range);
-+	/*do system clock*/
-+	dc_service_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DC_PP_CLOCK_TYPE_ENGINE_CLK,
-+			&clks);
-+	/* convert all the clock fro kHz to fix point mHz */
-+	dc->bw_vbios.high_sclk = frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.mid_sclk  = frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios.low_sclk  = frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do display clock*/
-+	dc_service_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DC_PP_CLOCK_TYPE_DISPLAY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios.high_voltage_max_dispclk = frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.mid_voltage_max_dispclk  = frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios.low_voltage_max_dispclk  = frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do memory clock*/
-+	dc_service_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DC_PP_CLOCK_TYPE_MEMORY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios.low_yclk = frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+	dc->bw_vbios.high_yclk = frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	return;
- 
- 	/* on CZ Gardenia from PPLib we get:
- 	 * clk_range.max_mclk:80000
-@@ -238,11 +274,6 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 
- 	/* The values for calcs are stored in units of MHz, so for example
- 	 * 80000 will be stored as 800. */
--	dc->bw_vbios.high_sclk = frc_to_fixed(clk_range.max_sclk, 100);
--	dc->bw_vbios.low_sclk = frc_to_fixed(clk_range.min_sclk, 100);
--
--	dc->bw_vbios.high_yclk = frc_to_fixed(clk_range.max_mclk, 100);
--	dc->bw_vbios.low_yclk = frc_to_fixed(clk_range.min_mclk, 100);
- }
- 
- static bool construct(struct dc *dc, const struct dal_init_data *init_params)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index c2172ea..a584b6a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -176,7 +176,7 @@ enum dc_pp_clock_type {
- 
- struct dc_pp_clock_levels {
- 	uint32_t num_levels;
--	uint32_t clocks_in_hz[DC_PP_MAX_CLOCK_LEVELS];
-+	uint32_t clocks_in_khz[DC_PP_MAX_CLOCK_LEVELS];
- 
- 	/* TODO: add latency
- 	 * do we need to know invalid (unsustainable boost) level for watermark
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0576-drm-amd-dal-Fix-compile-errors.patch b/common/recipes-kernel/linux/files/0576-drm-amd-dal-Fix-compile-errors.patch
deleted file mode 100644
index afd3f937..00000000
--- a/common/recipes-kernel/linux/files/0576-drm-amd-dal-Fix-compile-errors.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e53ec50463bbf21d92e74c8a6c01e4b221ae1661 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 3 Dec 2015 17:23:49 -0500
-Subject: [PATCH 0576/1110] drm/amd/dal: Fix compile errors.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_services.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index a584b6a..136c323 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -150,8 +150,8 @@ enum dc_pp_clocks_state {
- };
- 
- struct dc_pp_static_clock_info {
--	uint32_t max_engine_clock_hz;
--	uint32_t max_memory_clock_hz;
-+	uint32_t max_sclk_khz;
-+	uint32_t max_mclk_khz;
- 	 /* max possible display block clocks state */
- 	enum dc_pp_clocks_state max_clocks_state;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0577-drm-amd-dal-Add-unit-mhz-to-clock-members-in-bw-cals.patch b/common/recipes-kernel/linux/files/0577-drm-amd-dal-Add-unit-mhz-to-clock-members-in-bw-cals.patch
deleted file mode 100644
index f8a658f7..00000000
--- a/common/recipes-kernel/linux/files/0577-drm-amd-dal-Add-unit-mhz-to-clock-members-in-bw-cals.patch
+++ /dev/null
@@ -1,425 +0,0 @@
-From 95237b75776c9c5c7c1a9c5afa6f230a345d1bd0 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Thu, 3 Dec 2015 17:28:13 -0500
-Subject: [PATCH 0577/1110] drm/amd/dal: Add unit mhz to clock members in bw
- cals.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 129 +++++++++++----------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  16 +--
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  16 +--
- 3 files changed, 81 insertions(+), 80 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 742c4ec..e9fc75f 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -114,12 +114,12 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	enum bw_defines mode_check;
- 	uint32_t y_clk_level;
- 	uint32_t sclk_level;
--	yclk[high] = vbios->high_yclk;
--	yclk[mid] = vbios->high_yclk;
--	yclk[low] = vbios->low_yclk;
--	sclk[high] = vbios->high_sclk;
--	sclk[mid] = vbios->mid_sclk;
--	sclk[low] = vbios->low_sclk;
-+	yclk[high] = vbios->high_yclk_mhz;
-+	yclk[mid] = vbios->high_yclk_mhz;
-+	yclk[low] = vbios->low_yclk_mhz;
-+	sclk[high] = vbios->high_sclk_mhz;
-+	sclk[mid] = vbios->mid_sclk_mhz;
-+	sclk[low] = vbios->low_sclk_mhz;
- 	if (mode_data->d0_underlay_mode == ul_none) {
- 		d0_underlay_enable = false;
- 	} else {
-@@ -2060,11 +2060,11 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	if (gtn(results->blackout_duration_margin[high][high], int_to_fixed(0))
- 		&& ltn(
- 			results->dispclk_required_for_blackout_duration[high][high],
--			vbios->high_voltage_max_dispclk)) {
-+			vbios->high_voltage_max_dispclk_mhz)) {
- 		results->cpup_state_change_enable = true;
- 		if (ltn(
- 			results->dispclk_required_for_blackout_recovery[high][high],
--			vbios->high_voltage_max_dispclk)) {
-+			vbios->high_voltage_max_dispclk_mhz)) {
- 			results->cpuc_state_change_enable = true;
- 		} else {
- 			results->cpuc_state_change_enable = false;
-@@ -2203,7 +2203,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	if (gtn(results->dram_speed_change_margin[high][high], int_to_fixed(0))
- 		&& ltn(
- 			results->dispclk_required_for_dram_speed_change[high][high],
--			vbios->high_voltage_max_dispclk)) {
-+			vbios->high_voltage_max_dispclk_mhz)) {
- 		results->nbp_state_change_enable = true;
- 	} else {
- 		results->nbp_state_change_enable = false;
-@@ -2260,7 +2260,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		y_clk_level = high;
- 		results->dram_bandwidth = mul(
- 			bw_div(
--				mul(vbios->high_yclk,
-+				mul(vbios->high_yclk_mhz,
- 					vbios->dram_channel_width_in_bits),
- 				int_to_fixed(8)),
- 			vbios->number_of_dram_channels);
-@@ -2274,7 +2274,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		y_clk_level = high;
- 		results->dram_bandwidth = mul(
- 			bw_div(
--				mul(vbios->high_yclk,
-+				mul(vbios->high_yclk_mhz,
- 					vbios->dram_channel_width_in_bits),
- 				int_to_fixed(8)),
- 			vbios->number_of_dram_channels);
-@@ -2288,7 +2288,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				int_to_fixed(1000)),
- 			mul(
- 				bw_div(
--					mul(vbios->low_yclk,
-+					mul(vbios->low_yclk_mhz,
- 						vbios->dram_channel_width_in_bits),
- 					int_to_fixed(8)),
- 				vbios->number_of_dram_channels))
-@@ -2298,28 +2298,28 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					int_to_fixed(0))
- 					&& ltn(
- 						results->dispclk_required_for_blackout_duration[low][high],
--						vbios->high_voltage_max_dispclk)))
-+						vbios->high_voltage_max_dispclk_mhz)))
- 			&& (results->cpuc_state_change_enable == false
- 				|| (gtn(
- 					results->blackout_duration_margin[low][high],
- 					int_to_fixed(0))
- 					&& ltn(
- 						results->dispclk_required_for_blackout_duration[low][high],
--						vbios->high_voltage_max_dispclk)
-+						vbios->high_voltage_max_dispclk_mhz)
- 					&& ltn(
- 						results->dispclk_required_for_blackout_recovery[low][high],
--						vbios->high_voltage_max_dispclk)))
-+						vbios->high_voltage_max_dispclk_mhz)))
- 			&& gtn(results->dram_speed_change_margin[low][high],
- 				int_to_fixed(0))
- 			&& ltn(
- 				results->dispclk_required_for_dram_speed_change[low][high],
--				vbios->high_voltage_max_dispclk)) {
-+				vbios->high_voltage_max_dispclk_mhz)) {
- 			yclk_message = def_low;
- 			y_clk_level = low;
- 			results->dram_bandwidth =
- 				mul(
- 					bw_div(
--						mul(vbios->low_yclk,
-+						mul(vbios->low_yclk_mhz,
- 							vbios->dram_channel_width_in_bits),
- 						int_to_fixed(8)),
- 					vbios->number_of_dram_channels);
-@@ -2328,7 +2328,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				int_to_fixed(1000)),
- 			mul(
- 				bw_div(
--					mul(vbios->high_yclk,
-+					mul(vbios->high_yclk_mhz,
- 						vbios->dram_channel_width_in_bits),
- 					int_to_fixed(8)),
- 				vbios->number_of_dram_channels))) {
-@@ -2337,7 +2337,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			results->dram_bandwidth =
- 				mul(
- 					bw_div(
--						mul(vbios->high_yclk,
-+						mul(vbios->high_yclk_mhz,
- 							vbios->dram_channel_width_in_bits),
- 						int_to_fixed(8)),
- 					vbios->number_of_dram_channels);
-@@ -2347,7 +2347,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			results->dram_bandwidth =
- 				mul(
- 					bw_div(
--						mul(vbios->high_yclk,
-+						mul(vbios->high_yclk_mhz,
- 							vbios->dram_channel_width_in_bits),
- 						int_to_fixed(8)),
- 					vbios->number_of_dram_channels);
-@@ -2377,61 +2377,61 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	} else {
- 		results->required_sclk = bw_max(results->dmif_required_sclk,
- 			results->mcifwr_required_sclk);
--		if (ltn(results->required_sclk, vbios->low_sclk)
-+		if (ltn(results->required_sclk, vbios->low_sclk_mhz)
- 			&& (results->cpup_state_change_enable == false
- 				|| (gtn(
- 					results->blackout_duration_margin[y_clk_level][low],
- 					int_to_fixed(0))
- 					&& ltn(
- 						results->dispclk_required_for_blackout_duration[y_clk_level][low],
--						vbios->high_voltage_max_dispclk)))
-+						vbios->high_voltage_max_dispclk_mhz)))
- 			&& (results->cpuc_state_change_enable == false
- 				|| (gtn(
- 					results->blackout_duration_margin[y_clk_level][low],
- 					int_to_fixed(0))
- 					&& ltn(
- 						results->dispclk_required_for_blackout_duration[y_clk_level][low],
--						vbios->high_voltage_max_dispclk)
-+						vbios->high_voltage_max_dispclk_mhz)
- 					&& ltn(
- 						results->dispclk_required_for_blackout_recovery[y_clk_level][low],
--						vbios->high_voltage_max_dispclk)))
-+						vbios->high_voltage_max_dispclk_mhz)))
- 			&& (results->nbp_state_change_enable == false
- 				|| (gtn(
- 					results->dram_speed_change_margin[y_clk_level][low],
- 					int_to_fixed(0))
- 					&& leq(
- 						results->dispclk_required_for_dram_speed_change[y_clk_level][low],
--						vbios->high_voltage_max_dispclk)))) {
-+						vbios->high_voltage_max_dispclk_mhz)))) {
- 			sclk_message = def_low;
- 			sclk_level = low;
--		} else if (ltn(results->required_sclk, vbios->mid_sclk)
-+		} else if (ltn(results->required_sclk, vbios->mid_sclk_mhz)
- 			&& (results->cpup_state_change_enable == false
- 				|| (gtn(
- 					results->blackout_duration_margin[y_clk_level][mid],
- 					int_to_fixed(0))
- 					&& ltn(
- 						results->dispclk_required_for_blackout_duration[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk)))
-+						vbios->high_voltage_max_dispclk_mhz)))
- 			&& (results->cpuc_state_change_enable == false
- 				|| (gtn(
- 					results->blackout_duration_margin[y_clk_level][mid],
- 					int_to_fixed(0))
- 					&& ltn(
- 						results->dispclk_required_for_blackout_duration[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk)
-+						vbios->high_voltage_max_dispclk_mhz)
- 					&& ltn(
- 						results->dispclk_required_for_blackout_recovery[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk)))
-+						vbios->high_voltage_max_dispclk_mhz)))
- 			&& (results->nbp_state_change_enable == false
- 				|| (gtn(
- 					results->dram_speed_change_margin[y_clk_level][mid],
- 					int_to_fixed(0))
- 					&& leq(
- 						results->dispclk_required_for_dram_speed_change[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk)))) {
-+						vbios->high_voltage_max_dispclk_mhz)))) {
- 			sclk_message = def_mid;
- 			sclk_level = mid;
--		} else if (ltn(results->required_sclk, vbios->high_sclk)) {
-+		} else if (ltn(results->required_sclk, vbios->high_sclk_mhz)) {
- 			sclk_message = def_high;
- 			sclk_level = high;
- 		} else {
-@@ -2620,13 +2620,13 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	}
- 	if (ltn(
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth,
--		vbios->high_voltage_max_dispclk)) {
-+		vbios->high_voltage_max_dispclk_mhz)) {
- 		results->dispclk =
- 			results->total_dispclk_required_with_ramping_with_request_bandwidth;
- 	} else if (ltn(
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth,
--		vbios->high_voltage_max_dispclk)) {
--		results->dispclk = vbios->high_voltage_max_dispclk;
-+		vbios->high_voltage_max_dispclk_mhz)) {
-+		results->dispclk = vbios->high_voltage_max_dispclk_mhz;
- 	} else {
- 		results->dispclk =
- 			results->total_dispclk_required_without_ramping_with_request_bandwidth;
-@@ -2640,20 +2640,20 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		mode_background_color = def_notok_color;
- 		mode_font_color = def_vb_black;
- 	} else if (yclk_message == def_low && sclk_message == def_low
--		&& ltn(results->dispclk, vbios->low_voltage_max_dispclk)) {
-+		&& ltn(results->dispclk, vbios->low_voltage_max_dispclk_mhz)) {
- 		voltage = def_low;
- 		mode_background_color = def_low_color;
- 		mode_font_color = def_vb_black;
- 	} else if (yclk_message == def_low
- 		&& (sclk_message == def_low || sclk_message == def_mid)
--		&& ltn(results->dispclk, vbios->mid_voltage_max_dispclk)) {
-+		&& ltn(results->dispclk, vbios->mid_voltage_max_dispclk_mhz)) {
- 		voltage = def_mid;
- 		mode_background_color = def_mid_color;
- 		mode_font_color = def_vb_black;
- 	} else if ((yclk_message == def_low || yclk_message == def_high)
- 		&& (sclk_message == def_low || sclk_message == def_mid
- 			|| sclk_message == def_high)
--		&& leq(results->dispclk, vbios->high_voltage_max_dispclk)) {
-+		&& leq(results->dispclk, vbios->high_voltage_max_dispclk_mhz)) {
- 		if (results->nbp_state_change_enable == true) {
- 			voltage = def_high;
- 			mode_background_color = def_high_color;
-@@ -3161,14 +3161,14 @@ void bw_calcs_init(struct bw_calcs_input_dceip *bw_dceip,
- 	vbios.number_of_dram_channels = int_to_fixed(2);
- 	vbios.dram_channel_width_in_bits = int_to_fixed(64);
- 	vbios.number_of_dram_banks = int_to_fixed(8);
--	vbios.high_yclk = int_to_fixed(1600);
--	vbios.low_yclk = frc_to_fixed(66666, 100);
--	vbios.low_sclk = int_to_fixed(200);
--	vbios.mid_sclk = int_to_fixed(300);
--	vbios.high_sclk = frc_to_fixed(62609, 100);
--	vbios.low_voltage_max_dispclk = int_to_fixed(352);
--	vbios.mid_voltage_max_dispclk = int_to_fixed(467);
--	vbios.high_voltage_max_dispclk = int_to_fixed(643);
-+	vbios.high_yclk_mhz = int_to_fixed(1600);
-+	vbios.low_yclk_mhz = frc_to_fixed(66666, 100);
-+	vbios.low_sclk_mhz = int_to_fixed(200);
-+	vbios.mid_sclk_mhz = int_to_fixed(300);
-+	vbios.high_sclk_mhz = frc_to_fixed(62609, 100);
-+	vbios.low_voltage_max_dispclk_mhz = int_to_fixed(352);
-+	vbios.mid_voltage_max_dispclk_mhz = int_to_fixed(467);
-+	vbios.high_voltage_max_dispclk_mhz = int_to_fixed(643);
- 	vbios.data_return_bus_width = int_to_fixed(32);
- 	vbios.trc = int_to_fixed(50);
- 	vbios.dmifmc_urgent_latency = int_to_fixed(4);
-@@ -3366,16 +3366,16 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 	}
- 
- 	if (bw_data_internal->number_of_displays != 0) {
--		struct bw_fixed high_sclk = vbios->high_sclk;
--		struct bw_fixed low_sclk = vbios->low_sclk;
--		struct bw_fixed high_yclk = vbios->high_yclk;
--		struct bw_fixed low_yclk = vbios->low_yclk;
-+		struct bw_fixed high_sclk = vbios->high_sclk_mhz;
-+		struct bw_fixed low_sclk = vbios->low_sclk_mhz;
-+		struct bw_fixed high_yclk = vbios->high_yclk_mhz;
-+		struct bw_fixed low_yclk = vbios->low_yclk_mhz;
- 
--		((struct bw_calcs_input_vbios *)vbios)->low_yclk = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_yclk = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->low_sclk = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_sclk = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = low_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_yclk_mhz = low_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_sclk_mhz = low_sclk;
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
- 
-@@ -3410,11 +3410,11 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 			mul(bw_results_internal->urgent_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
--		((struct bw_calcs_input_vbios *)vbios)->low_yclk = high_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_yclk = high_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->low_sclk = high_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk = high_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_sclk = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = high_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_yclk_mhz = high_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_sclk_mhz = high_sclk;
- 
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
-@@ -3473,11 +3473,12 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 		calcs_output->required_yclk =
- 				mul(high_yclk, int_to_fixed(1000)).value >> 24;
- 
--		((struct bw_calcs_input_vbios *)vbios)->low_yclk = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_yclk = high_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->low_sclk = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk = high_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_sclk = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = low_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_yclk_mhz =
-+								high_yclk;
-+		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = low_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->high_sclk_mhz = high_sclk;
- 	} else {
- 		calcs_output->nbp_state_change_enable = true;
- 		calcs_output->cpuc_state_change_enable = true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 599bf2f..50505f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -234,11 +234,11 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			DC_PP_CLOCK_TYPE_ENGINE_CLK,
- 			&clks);
- 	/* convert all the clock fro kHz to fix point mHz */
--	dc->bw_vbios.high_sclk = frc_to_fixed(
-+	dc->bw_vbios.high_sclk_mhz = frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	dc->bw_vbios.mid_sclk  = frc_to_fixed(
-+	dc->bw_vbios.mid_sclk_mhz  = frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels>>1], 1000);
--	dc->bw_vbios.low_sclk  = frc_to_fixed(
-+	dc->bw_vbios.low_sclk_mhz  = frc_to_fixed(
- 			clks.clocks_in_khz[0], 1000);
- 
- 	/*do display clock*/
-@@ -247,11 +247,11 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			DC_PP_CLOCK_TYPE_DISPLAY_CLK,
- 			&clks);
- 
--	dc->bw_vbios.high_voltage_max_dispclk = frc_to_fixed(
-+	dc->bw_vbios.high_voltage_max_dispclk_mhz = frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	dc->bw_vbios.mid_voltage_max_dispclk  = frc_to_fixed(
-+	dc->bw_vbios.mid_voltage_max_dispclk_mhz  = frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels>>1], 1000);
--	dc->bw_vbios.low_voltage_max_dispclk  = frc_to_fixed(
-+	dc->bw_vbios.low_voltage_max_dispclk_mhz  = frc_to_fixed(
- 			clks.clocks_in_khz[0], 1000);
- 
- 	/*do memory clock*/
-@@ -260,9 +260,9 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			DC_PP_CLOCK_TYPE_MEMORY_CLK,
- 			&clks);
- 
--	dc->bw_vbios.low_yclk = frc_to_fixed(
-+	dc->bw_vbios.low_yclk_mhz = frc_to_fixed(
- 			clks.clocks_in_khz[0], 1000);
--	dc->bw_vbios.high_yclk = frc_to_fixed(
-+	dc->bw_vbios.high_yclk_mhz = frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
- 	return;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index a304ce8..6422298 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -123,16 +123,16 @@ struct bw_calcs_input_vbios {
- 	struct bw_fixed dram_channel_width_in_bits;
- 	struct bw_fixed number_of_dram_channels;
- 	struct bw_fixed number_of_dram_banks;
--	struct bw_fixed high_yclk;
-+	struct bw_fixed high_yclk_mhz;
- 	struct bw_fixed high_dram_bandwidth_per_channel;
--	struct bw_fixed low_yclk;
-+	struct bw_fixed low_yclk_mhz;
- 	struct bw_fixed low_dram_bandwidth_per_channel;
--	struct bw_fixed low_sclk;
--	struct bw_fixed mid_sclk;
--	struct bw_fixed high_sclk;
--	struct bw_fixed low_voltage_max_dispclk;
--	struct bw_fixed mid_voltage_max_dispclk;
--	struct bw_fixed high_voltage_max_dispclk;
-+	struct bw_fixed low_sclk_mhz;
-+	struct bw_fixed mid_sclk_mhz;
-+	struct bw_fixed high_sclk_mhz;
-+	struct bw_fixed low_voltage_max_dispclk_mhz;
-+	struct bw_fixed mid_voltage_max_dispclk_mhz;
-+	struct bw_fixed high_voltage_max_dispclk_mhz;
- 	struct bw_fixed data_return_bus_width;
- 	struct bw_fixed trc;
- 	struct bw_fixed dmifmc_urgent_latency;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0578-drm-amd-dal-Add-implementation-for-get-clock-levels-.patch b/common/recipes-kernel/linux/files/0578-drm-amd-dal-Add-implementation-for-get-clock-levels-.patch
deleted file mode 100644
index e99ebc79..00000000
--- a/common/recipes-kernel/linux/files/0578-drm-amd-dal-Add-implementation-for-get-clock-levels-.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 8c6925686b2cc2b711899da30c6b810d3ce31f00 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 3 Dec 2015 14:11:22 -0500
-Subject: [PATCH 0578/1110] drm/amd/dal: Add implementation for get clock
- levels by type
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_services.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index 136c323..1d350d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -152,6 +152,7 @@ enum dc_pp_clocks_state {
- struct dc_pp_static_clock_info {
- 	uint32_t max_sclk_khz;
- 	uint32_t max_mclk_khz;
-+
- 	 /* max possible display block clocks state */
- 	enum dc_pp_clocks_state max_clocks_state;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0579-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch b/common/recipes-kernel/linux/files/0579-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch
deleted file mode 100644
index 89b7c452..00000000
--- a/common/recipes-kernel/linux/files/0579-drm-amd-dal-Fix-compile-error-for-case-CONFIG_DRM_AM.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 46ba14f748219dc91f3c65020c3ab7b35ace4cc8 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Mon, 7 Dec 2015 13:29:36 -0500
-Subject: [PATCH 0579/1110] drm/amd/dal: Fix compile error for case
- "CONFIG_DRM_AMD_POWERPLAY not defined".
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c | 11 +++++------
- 1 file changed, 5 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index 2c02d18..e9308f3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -234,7 +234,6 @@ bool dc_service_pp_get_clock_levels_by_type(
- 		enum dc_pp_clock_type clk_type,
- 		struct dc_pp_clock_levels *clks)
- {
--
- /*
-  #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	if(amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle,
-@@ -243,17 +242,12 @@ bool dc_service_pp_get_clock_levels_by_type(
- 		divide by 10 & push to the clks which kHz
- #endif
- */
--
--	struct amdgpu_device *adev = ctx->driver_context;
--
- 	uint32_t disp_clks_in_khz[8] = {
- 	300000, 411430, 480000, 533340, 626090, 626090, 626090, 626090 };
- 	uint32_t sclks_in_khz[8] = {
- 	200000, 266670, 342860, 411430, 450000, 514290, 576000, 626090 };
- 	uint32_t mclks_in_khz[8] = { 333000, 800000 };
- 
--	struct amd_pp_dal_clock_info info = {0};
--
- 	switch (clk_type) {
- 	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
- 		clks->num_levels = 8;
-@@ -273,9 +267,14 @@ bool dc_service_pp_get_clock_levels_by_type(
- 	default:
- 		return false;
- 	}
-+
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	if (clk_type ==  DC_PP_CLOCK_TYPE_ENGINE_CLK ||
- 		clk_type ==  DC_PP_CLOCK_TYPE_DISPLAY_CLK) {
-+
-+		struct amdgpu_device *adev = ctx->driver_context;
-+		struct amd_pp_dal_clock_info info = {0};
-+
- 		if (0 == amd_powerplay_get_display_power_level(
- 				adev->powerplay.pp_handle, &info) &&
- 				info.level < clks->num_levels) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0580-drm-amd-dal-Fix-issue-where-unused-HW-is-not-powered.patch b/common/recipes-kernel/linux/files/0580-drm-amd-dal-Fix-issue-where-unused-HW-is-not-powered.patch
deleted file mode 100644
index 605db313..00000000
--- a/common/recipes-kernel/linux/files/0580-drm-amd-dal-Fix-issue-where-unused-HW-is-not-powered.patch
+++ /dev/null
@@ -1,278 +0,0 @@
-From a174d4b05bfe7554d77c1c3be0ad56fbbb8b2fd9 Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Sat, 5 Dec 2015 01:57:27 -0500
-Subject: [PATCH 0580/1110] drm/amd/dal: Fix issue where unused HW is not
- powered down after boot
-
-[Description]
-init_hw is called on dc create and on set power state call,
-but what appears incorrect is that it is setting accelerated
-mode bit in scratch register.
-
-We actually expect accelerated mode bit to be set on first commit,
-when we actually enter accelerated mode. Entering accelerated
-mode actually involves a handoff between VBIOS controlled
-programming of display pipe to Driver control. During this process,
-we want to init and power down all existing HW.
-
-Power down of HW in enter accelerated mode was also not very
-correct, since it currently takes the first commit context. But what
-we really wanted to do is power everything off.
-
-Finally, we need to do power gate of pipe when unused, but also
-ungate when enabling the pipe.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  6 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 97 +++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  4 +-
- 3 files changed, 53 insertions(+), 54 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 50505f4..7fc9f17 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -167,8 +167,6 @@ static void init_hw(struct dc *dc)
- 		dc->hwss.encoder_power_up(link->link_enc);
- 	}
- 
--	dal_bios_parser_set_scratch_acc_mode_change(bp);
--
- 	for(i = 0; i < dc->res_pool.controller_count; i++) {
- 		struct timing_generator *tg = dc->res_pool.timing_generators[i];
- 
-@@ -653,7 +651,7 @@ bool dc_commit_targets(
- 
- 	if (!dal_adapter_service_is_in_accelerated_mode(
- 						dc->res_pool.adapter_srv)) {
--		dc->hwss.enable_accelerated_mode(context);
-+		dc->hwss.enable_accelerated_mode(dc);
- 	}
- 
- 	for (i = 0; i < dc->current_context.target_count; i++) {
-@@ -859,7 +857,7 @@ void dc_set_power_state(
- 		/* NULL means "reset/release all DC targets" */
- 		dc_commit_targets(dc, NULL, 0);
- 
--		dc->hwss.power_down(&dc->current_context);
-+		dc->hwss.power_down(dc);
- 		break;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 81935e5..edbf3ce 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -785,8 +785,21 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
- 			.flags.timing_changed;
- 	enum color_space color_space;
-+	struct bios_parser *bp;
-+
-+	bp = dal_adapter_service_get_bios_parser(
-+			context->res_ctx.pool.adapter_srv);
- 
- 	if (timing_changed) {
-+		dce110_enable_display_power_gating(
-+				stream->ctx, controller_idx, bp,
-+				PIPE_GATING_CONTROL_DISABLE);
-+
-+		/* Must blank CRTC after disabling power gating and before any
-+		 * programming, otherwise CRTC will be hung in bad state
-+		 */
-+		dce110_timing_generator_blank_crtc(stream->tg);
-+
- 		core_link_disable_stream(
- 				stream->sink->link, stream);
- 
-@@ -898,47 +911,34 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 
- /******************************************************************************/
- 
--static void power_down_encoders(struct validate_context *context)
-+static void power_down_encoders(struct dc *dc)
- {
- 	int i;
--	struct core_target *target;
--	struct core_stream *stream;
- 
--	for (i = 0; i < context->target_count; i++) {
--		target = context->targets[i];
--		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
--
--		core_link_disable_stream(stream->sink->link, stream);
-+	for (i = 0; i < dc->link_count; i++) {
-+		dce110_link_encoder_disable_output(
-+				dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
- 	}
- }
- 
--static void power_down_controllers(struct validate_context *context)
-+static void power_down_controllers(struct dc *dc)
- {
- 	int i;
--	struct core_target *target;
--	struct core_stream *stream;
--
--	for (i = 0; i < context->target_count; i++) {
--		target = context->targets[i];
--		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 
--		dce110_timing_generator_disable_crtc(stream->tg);
-+	for (i = 0; i < dc->res_pool.controller_count; i++) {
-+		dce110_timing_generator_disable_crtc(
-+				dc->res_pool.timing_generators[i]);
- 	}
- }
- 
--static void power_down_clock_sources(struct validate_context *context)
-+static void power_down_clock_sources(struct dc *dc)
- {
- 	int i;
--	struct core_target *target;
--	struct core_stream *stream;
--
--	for (i = 0; i < context->target_count; i++) {
--		target = context->targets[i];
--		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
- 
-+	for (i = 0; i < dc->res_pool.clk_src_count; i++) {
- 		if (false == dal_clock_source_power_down_pll(
--				stream->clock_source,
--				stream->controller_idx + 1)) {
-+				dc->res_pool.clock_sources[i],
-+				i+1)) {
- 			dal_error(
- 				"Failed to power down pll! (clk src index=%d)\n",
- 				i);
-@@ -946,35 +946,29 @@ static void power_down_clock_sources(struct validate_context *context)
- 	}
- }
- 
--static void power_down_all_hw_blocks(struct validate_context *context)
-+static void power_down_all_hw_blocks(struct dc *dc)
- {
--	power_down_encoders(context);
-+	power_down_encoders(dc);
- 
--	power_down_controllers(context);
-+	power_down_controllers(dc);
- 
--	power_down_clock_sources(context);
-+	power_down_clock_sources(dc);
- }
- 
- static void disable_vga_and_power_gate_all_controllers(
--		struct validate_context *context)
-+		struct dc *dc)
- {
- 	int i;
--	struct core_target *target;
--	struct core_stream *stream;
- 	struct timing_generator *tg;
- 	struct bios_parser *bp;
- 	struct dc_context *ctx;
--	uint8_t controller_id;
- 
- 	bp = dal_adapter_service_get_bios_parser(
--				context->res_ctx.pool.adapter_srv);
-+			dc->res_pool.adapter_srv);
- 
--	for (i = 0; i < context->target_count; i++) {
--		target = context->targets[i];
--		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
--		tg = stream->tg;
--		ctx = stream->ctx;
--		controller_id = stream->controller_idx;
-+	for (i = 0; i < dc->res_pool.controller_count; i++) {
-+		tg = dc->res_pool.timing_generators[i];
-+		ctx = dc->ctx;
- 
- 		dce110_timing_generator_disable_vga(tg);
- 
-@@ -982,7 +976,7 @@ static void disable_vga_and_power_gate_all_controllers(
- 		 * powergating. */
- 		dce110_enable_display_pipe_clock_gating(ctx,
- 				true);
--		dce110_enable_display_power_gating(ctx, controller_id, bp,
-+		dce110_enable_display_power_gating(ctx, i+1, bp,
- 				PIPE_GATING_CONTROL_ENABLE);
- 	}
- }
-@@ -994,16 +988,16 @@ static void disable_vga_and_power_gate_all_controllers(
-  *  3. Enable power gating for controller
-  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
-  */
--static void enable_accelerated_mode(struct validate_context *context)
-+static void enable_accelerated_mode(struct dc *dc)
- {
- 	struct bios_parser *bp;
- 
- 	bp = dal_adapter_service_get_bios_parser(
--			context->res_ctx.pool.adapter_srv);
-+			dc->res_pool.adapter_srv);
- 
--	power_down_all_hw_blocks(context);
-+	power_down_all_hw_blocks(dc);
- 
--	disable_vga_and_power_gate_all_controllers(context);
-+	disable_vga_and_power_gate_all_controllers(dc);
- 
- 	dal_bios_parser_set_scratch_acc_mode_change(bp);
- }
-@@ -1565,6 +1559,10 @@ static bool update_plane_address(
- static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 		struct validate_context *context)
- {
-+	struct bios_parser *bp;
-+
-+	bp = dal_adapter_service_get_bios_parser(
-+			context->res_ctx.pool.adapter_srv);
- 	if (stream->audio) {
- 		dal_audio_disable_output(stream->audio,
- 				stream->stream_enc->id,
-@@ -1580,6 +1578,9 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 	dce110_transform_set_scaler_bypass(stream->xfm);
- 	disable_stereo_mixer(stream->ctx);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
-+	dce110_enable_display_power_gating(
-+			stream->ctx, stream->controller_idx, bp,
-+			PIPE_GATING_CONTROL_ENABLE);
- }
- 
- static void reset_hw_ctx(struct dc *dc,
-@@ -1604,10 +1605,10 @@ static void reset_hw_ctx(struct dc *dc,
- 	}
- }
- 
--static void power_down(struct validate_context *context)
-+static void power_down(struct dc *dc)
- {
--	power_down_all_hw_blocks(context);
--	disable_vga_and_power_gate_all_controllers(context);
-+	power_down_all_hw_blocks(dc);
-+	disable_vga_and_power_gate_all_controllers(dc);
- 
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 67cc020..b9f21bb 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -65,9 +65,9 @@ struct hw_sequencer_funcs {
- 					const struct gamma_ramp *ramp,
- 					const struct gamma_parameters *params);
- 
--	void (*power_down)(struct validate_context *context);
-+	void (*power_down)(struct dc *dc);
- 
--	void (*enable_accelerated_mode)(struct validate_context *context);
-+	void (*enable_accelerated_mode)(struct dc *dc);
- 
- 	void (*get_crtc_positions)(
- 					struct timing_generator *tg,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0581-drm-amd-dal-prototype-change-of-detection-scheme.patch b/common/recipes-kernel/linux/files/0581-drm-amd-dal-prototype-change-of-detection-scheme.patch
deleted file mode 100644
index 4b8f2f48..00000000
--- a/common/recipes-kernel/linux/files/0581-drm-amd-dal-prototype-change-of-detection-scheme.patch
+++ /dev/null
@@ -1,114 +0,0 @@
-From d1418336f40446595c3081efa14d74721ccad847 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 4 Dec 2015 19:51:18 +0800
-Subject: [PATCH 0581/1110] drm/amd/dal: prototype change of detection scheme
-
-Some facts below:
-
-1. One interrupt handler work can be processed at a time;
-2. Remote i2c read starts at hpd rx thread;
-3. Even though new interrupts come, they are blocked.
-
-This change is just work in progress in order to understand real
-root cause of the issue.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c          | 18 +++++++++++++++++-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h          |  2 ++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  5 ++++-
- 3 files changed, 23 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index a414586..ab546a7 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -465,6 +465,14 @@ static void detect_on_all_dc_links(struct amdgpu_display_manager *dm)
- 	}
- }
- 
-+static void hotplug_notify_work_func(struct work_struct *work)
-+{
-+	struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
-+	struct drm_device *dev = dm->ddev;
-+
-+	drm_kms_helper_hotplug_event(dev);
-+}
-+
- /* Init display KMS
-  *
-  * Returns 0 on success
-@@ -536,6 +544,8 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
- 	/* Display Core create. */
- 	adev->dm.dc = dc_create(&init_data);
- 
-+	INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
-+
- 	if (amdgpu_dm_initialize_drm_device(adev)) {
- 		DRM_ERROR(
- 		"amdgpu: failed to initialize sw for display support.\n");
-@@ -785,6 +795,10 @@ static void handle_hpd_rx_irq(void *param)
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
- 
-+	if (aconnector->mst_mgr.mst_state) {
-+		mutex_lock(&aconnector->mst_mgr.aux->hw_mutex);
-+	}
-+
- 	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) &&
- 			!aconnector->mst_mgr.mst_state) {
- 		/* Downstream Port status changed. */
-@@ -793,8 +807,10 @@ static void handle_hpd_rx_irq(void *param)
- 		drm_helper_hpd_irq_event(dev);
- 	}
- 
--	if (aconnector->mst_mgr.mst_state)
-+	if (aconnector->mst_mgr.mst_state) {
-+		mutex_unlock(&aconnector->mst_mgr.aux->hw_mutex);
- 		dc_helpers_dp_mst_handle_mst_hpd_rx_irq(param);
-+	}
- }
- 
- static void register_hpd_handlers(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 57e9c45..c4ae90b 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -123,6 +123,8 @@ struct amdgpu_display_manager {
- 	struct backlight_device *backlight_dev;
- 
- 	const struct dc_link *backlight_link;
-+
-+	struct work_struct mst_hotplug_work;
- };
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index df80f5c..2f3a784 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -152,6 +152,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
- 	const struct dc_sink *sink;
- 	int ret = 0;
- 
-+	flush_work(&master->mst_mgr.work);
-+
- 	edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, aconnector->port);
- 
- 	if (!edid) {
-@@ -299,8 +301,9 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
- {
- 	struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr);
- 	struct drm_device *dev = master->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
- 
--	drm_kms_helper_hotplug_event(dev);
-+	schedule_work(&adev->dm.mst_hotplug_work);
- }
- 
- static void dm_dp_mst_register_connector(struct drm_connector *connector)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0582-drm-amd-dal-Add-callback-to-DM-for-aux-access.patch b/common/recipes-kernel/linux/files/0582-drm-amd-dal-Add-callback-to-DM-for-aux-access.patch
deleted file mode 100644
index 5a3f3610..00000000
--- a/common/recipes-kernel/linux/files/0582-drm-amd-dal-Add-callback-to-DM-for-aux-access.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From 930261e14dcdc6f224fe8f4336eacb3b80533d21 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Mon, 7 Dec 2015 13:27:26 -0500
-Subject: [PATCH 0582/1110] drm/amd/dal: Add callback to DM for aux access
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 41 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |  9 ++---
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 19 +++++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     | 12 +++----
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            | 14 ++++++++
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c       |  2 ++
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h       | 11 ++++++
- 7 files changed, 91 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 2554e1a..7d3b2d3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -457,3 +457,44 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 
- 	aconnector->is_mst_connector = false;
- }
-+
-+bool dc_helper_dp_read_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size) {
-+
-+
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
-+			data, size) > 0;
-+}
-+
-+bool dc_helper_dp_write_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t size) {
-+
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, address,
-+			(uint8_t *)data, size) > 0;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index ab546a7..9bb8165 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -795,20 +795,15 @@ static void handle_hpd_rx_irq(void *param)
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
- 
--	if (aconnector->mst_mgr.mst_state) {
--		mutex_lock(&aconnector->mst_mgr.aux->hw_mutex);
--	}
--
- 	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) &&
--			!aconnector->mst_mgr.mst_state) {
-+			!aconnector->is_mst_connector) {
- 		/* Downstream Port status changed. */
- 		dc_link_detect(aconnector->dc_link);
- 		amdgpu_dm_update_connector_after_detect(aconnector);
- 		drm_helper_hpd_irq_event(dev);
- 	}
- 
--	if (aconnector->mst_mgr.mst_state) {
--		mutex_unlock(&aconnector->mst_mgr.aux->hw_mutex);
-+	if (aconnector->is_mst_connector) {
- 		dc_helpers_dp_mst_handle_mst_hpd_rx_irq(param);
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 7fc9f17..d8c0799 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -43,6 +43,8 @@
- #include "opp.h"
- #include "link_encoder.h"
- 
-+#include "dcs/ddc_service.h"
-+
- /*******************************************************************************
-  * Private structures
-  ******************************************************************************/
-@@ -912,6 +914,7 @@ void dc_print_sync_report(
- 	 * data from Step 1). */
- }
- 
-+/*AG TODO Create callbacks for WIN DM */
- bool dc_read_dpcd(
- 		struct dc *dc,
- 		uint32_t link_index,
-@@ -921,9 +924,13 @@ bool dc_read_dpcd(
- {
- 	struct core_link *link =
- 			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
--	enum dc_status r = core_link_read_dpcd(link, address, data, size);
- 
--	return r == DC_OK;
-+	enum ddc_result r = dal_ddc_service_read_dpcd_data(
-+			link->ddc,
-+			address,
-+			data,
-+			size);
-+	return r == DDC_RESULT_SUCESSFULL;
- }
- 
- bool dc_write_dpcd(
-@@ -935,9 +942,13 @@ bool dc_write_dpcd(
- {
- 	struct core_link *link =
- 			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
--	enum dc_status r = core_link_write_dpcd(link, address, data, size);
- 
--	return r == DC_OK;
-+	enum ddc_result r = dal_ddc_service_write_dpcd_data(
-+			link->ddc,
-+			address,
-+			data,
-+			size);
-+	return r == DDC_RESULT_SUCESSFULL;
- }
- 
- bool dc_link_add_sink(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 4c9eae4..3a80a10 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -20,9 +20,9 @@ enum dc_status core_link_read_dpcd(
- 	uint8_t *data,
- 	uint32_t size)
- {
--	if (dal_ddc_service_read_dpcd_data(link->ddc, address, data, size)
--			!= DDC_RESULT_SUCESSFULL)
--		return DC_ERROR_UNEXPECTED;
-+	if (!dc_helper_dp_read_dpcd(link->ctx,
-+			&link->public, address, data, size))
-+			return DC_ERROR_UNEXPECTED;
- 
- 	return DC_OK;
- }
-@@ -33,9 +33,9 @@ enum dc_status core_link_write_dpcd(
- 	const uint8_t *data,
- 	uint32_t size)
- {
--	if (dal_ddc_service_write_dpcd_data(link->ddc, address, data, size)
--			!= DDC_RESULT_SUCESSFULL)
--		return DC_ERROR_UNEXPECTED;
-+	if (!dc_helper_dp_write_dpcd(link->ctx,
-+			&link->public, address, data, size))
-+				return DC_ERROR_UNEXPECTED;
- 
- 	return DC_OK;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index c0fbb65..66f4d2d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -72,4 +72,18 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link);
- 
-+bool dc_helper_dp_read_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size);
-+
-+bool dc_helper_dp_write_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t size);
-+
- #endif /* __DC_HELPERS__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-index 5436704..854ff3f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-@@ -564,6 +564,8 @@ static uint32_t query_edid_block(
- #define DDC_DPCD_EDID_TEST_MASK 0x04
- #define DDC_DPCD_TEST_REQUEST_ADDRESS 0x218
- 
-+/* AG TODO GO throug DM callback here like for DPCD */
-+
- static void write_dp_edid_checksum(
- 	struct ddc_service *ddc,
- 	uint8_t checksum)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-index e5217b7..3bf2a9e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-@@ -35,4 +35,15 @@ void dal_ddc_service_set_ddc_pin(
- struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service);
- void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service);
- 
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t len);
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t len);
-+
- #endif /* __DAL_DDC_SERVICE_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0583-drm-amd-dal-Clean-up-some-comments.patch b/common/recipes-kernel/linux/files/0583-drm-amd-dal-Clean-up-some-comments.patch
deleted file mode 100644
index 32c7c2c9..00000000
--- a/common/recipes-kernel/linux/files/0583-drm-amd-dal-Clean-up-some-comments.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From bbf96a5827b9edd9c06d23f649ca9e8b8d3ae7c2 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 8 Dec 2015 15:46:47 -0500
-Subject: [PATCH 0583/1110] drm/amd/dal: Clean up some comments
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_services.h | 2 --
- drivers/gpu/drm/amd/dal/dc/dc_temp.h     | 1 -
- 2 files changed, 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index 1d350d8..edb558d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -50,14 +50,12 @@ void dc_service_memmove(void *dst, const void *src, uint32_t size);
- /* TODO: rename to dc_memcmp*/
- int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
- 
--/* TODO: remove when windows_dm will start registering for IRQs */
- irq_handler_idx dc_service_register_interrupt(
- 	struct dc_context *ctx,
- 	struct dc_interrupt_params *int_params,
- 	interrupt_handler ih,
- 	void *handler_args);
- 
--/* TODO: remove when windows_dm will start registering for IRQs */
- void dc_service_unregister_interrupt(
- 	struct dc_context *ctx,
- 	enum dc_irq_source irq_source,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_temp.h b/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-index b609deb..fc5b810 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-@@ -274,7 +274,6 @@ union plane_size {
- 	} video;
- };
- 
--/* Windows only */
- enum dc_scaling_transform {
- 	SCL_TRANS_CENTERED = 0,
- 	SCL_TRANS_ASPECT_RATIO,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0584-drm-amd-dal-Fix-up-HDMI-1080p-light-up-on-discrete-A.patch b/common/recipes-kernel/linux/files/0584-drm-amd-dal-Fix-up-HDMI-1080p-light-up-on-discrete-A.patch
deleted file mode 100644
index 08b043b6..00000000
--- a/common/recipes-kernel/linux/files/0584-drm-amd-dal-Fix-up-HDMI-1080p-light-up-on-discrete-A.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From e72203816f45859fbe2868fabb38b4056c6e895b Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Tue, 8 Dec 2015 10:30:43 -0500
-Subject: [PATCH 0584/1110] drm/amd/dal: Fix-up HDMI 1080p light up on discrete
- ASIC
-
-1.) Discrete does not have integrated table, yet DC depends on this to construct.  This dependency should be removed.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index ac39dff..e7a12e0 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -769,10 +769,7 @@ static bool construct(
- 		goto create_fail;
- 	}
- 
--	if (!dal_adapter_service_get_integrated_info(as, &info)) {
--		DC_ERROR("Failed to get integrated info!\n");
--		goto create_fail;
--	}
-+	dal_adapter_service_get_integrated_info(as, &info);
- 
- 	for (i = 0; ; i++) {
- 		if (!dal_adapter_service_get_device_tag(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0585-drm-amd-dal-Clean-up-aux-access-layer-in-DM.patch b/common/recipes-kernel/linux/files/0585-drm-amd-dal-Clean-up-aux-access-layer-in-DM.patch
deleted file mode 100644
index 8be6706a..00000000
--- a/common/recipes-kernel/linux/files/0585-drm-amd-dal-Clean-up-aux-access-layer-in-DM.patch
+++ /dev/null
@@ -1,135 +0,0 @@
-From 028c8faa6f36780fa082a5eb2ded31b7ecde8dba Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 8 Dec 2015 13:08:49 -0500
-Subject: [PATCH 0585/1110] drm/amd/dal: Clean up aux access layer in DM
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c | 6 ++++--
- drivers/gpu/drm/amd/dal/dc/core/dc.c                  | 3 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c        | 8 ++++++--
- drivers/gpu/drm/amd/dal/dc/dc.h                       | 2 +-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h               | 8 ++++++++
- 5 files changed, 20 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 7d3b2d3..b388dee 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -460,6 +460,7 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 
- bool dc_helper_dp_read_dpcd(
- 		struct dc_context *ctx,
-+		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		uint8_t *data,
-@@ -481,6 +482,7 @@ bool dc_helper_dp_read_dpcd(
- 
- bool dc_helper_dp_write_dpcd(
- 		struct dc_context *ctx,
-+		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		const uint8_t *data,
-@@ -495,6 +497,6 @@ bool dc_helper_dp_write_dpcd(
- 		return false;
- 	}
- 
--	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, address,
--			(uint8_t *)data, size) > 0;
-+	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
-+			address, (uint8_t *)data, size) > 0;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index d8c0799..feda859 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -914,7 +914,6 @@ void dc_print_sync_report(
- 	 * data from Step 1). */
- }
- 
--/*AG TODO Create callbacks for WIN DM */
- bool dc_read_dpcd(
- 		struct dc *dc,
- 		uint32_t link_index,
-@@ -937,7 +936,7 @@ bool dc_write_dpcd(
- 		struct dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
--		uint8_t *data,
-+		const uint8_t *data,
- 		uint32_t size)
- {
- 	struct core_link *link =
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 3a80a10..91aec82 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -21,7 +21,9 @@ enum dc_status core_link_read_dpcd(
- 	uint32_t size)
- {
- 	if (!dc_helper_dp_read_dpcd(link->ctx,
--			&link->public, address, data, size))
-+			link->link_index,
-+			&link->public,
-+			address, data, size))
- 			return DC_ERROR_UNEXPECTED;
- 
- 	return DC_OK;
-@@ -34,7 +36,9 @@ enum dc_status core_link_write_dpcd(
- 	uint32_t size)
- {
- 	if (!dc_helper_dp_write_dpcd(link->ctx,
--			&link->public, address, data, size))
-+			link->link_index,
-+			&link->public,
-+			address, data, size))
- 				return DC_ERROR_UNEXPECTED;
- 
- 	return DC_OK;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index df76992..fa2712c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -436,7 +436,7 @@ bool dc_write_dpcd(
- 		struct dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
--		uint8_t *data,
-+		const uint8_t *data,
- 	uint32_t size);
- 
- #endif /* DC_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index 66f4d2d..fe76833 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -72,15 +72,23 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link);
- 
-+/**
-+ * OS specific aux read callback.
-+ */
- bool dc_helper_dp_read_dpcd(
- 		struct dc_context *ctx,
-+		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		uint8_t *data,
- 		uint32_t size);
- 
-+/**
-+ * OS specific aux write callback.
-+ */
- bool dc_helper_dp_write_dpcd(
- 		struct dc_context *ctx,
-+		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		const uint8_t *data,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0586-drm-amd-dal-Fix-uint64-vs-int64-warnings.patch b/common/recipes-kernel/linux/files/0586-drm-amd-dal-Fix-uint64-vs-int64-warnings.patch
deleted file mode 100644
index faccde51..00000000
--- a/common/recipes-kernel/linux/files/0586-drm-amd-dal-Fix-uint64-vs-int64-warnings.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From b28613871a2ee3fa67ee67d18a9a47603ecf4cb2 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 30 Nov 2015 17:55:33 -0500
-Subject: [PATCH 0586/1110] drm/amd/dal: Fix uint64 vs int64 warnings
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c |  8 ++++----
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        | 12 ++++++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  4 ++--
- 3 files changed, 14 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index e9fc75f..542b3d7 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -1357,8 +1357,8 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			int_to_fixed(4));
- 	}
- 
--	div64_u64_rem(mode_data->underlay_pitch_in_pixels.value,
--			results->inefficient_underlay_pitch_in_pixels.value,
-+	div64_u64_rem((uint64_t)mode_data->underlay_pitch_in_pixels.value,
-+			(uint64_t)results->inefficient_underlay_pitch_in_pixels.value,
- 			&remainder);
- 
- 	if (mode_data->underlay_tiling_mode == linear
-@@ -1413,11 +1413,11 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		int_to_fixed(0);
- 	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
- 		if (results->enable[i]) {
--			uint64_t arg1 = mul(results->pitch_in_pixels_after_surface_type[i],
-+			uint64_t arg1 = (uint64_t)mul(results->pitch_in_pixels_after_surface_type[i],
- 						results->bytes_per_pixel[i]).value;
- 
- 			div64_u64_rem(arg1,
--					results->inefficient_linear_pitch_in_bytes.value,
-+					(uint64_t)results->inefficient_linear_pitch_in_bytes.value,
- 					&remainder);
- 
- 			if (results->scatter_gather_enable_for_pipe[i] == true
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index 8bdd0fb..646fafe 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -90,8 +90,8 @@ struct bw_fixed frc_to_fixed(int64_t numerator, int64_t denominator)
- 
- 	ASSERT(denominator != 0);
- 
--	arg1_value = abs_i64(numerator);
--	arg2_value = abs_i64(denominator);
-+	arg1_value = (uint64_t)abs_i64(numerator);
-+	arg2_value = (uint64_t)abs_i64(denominator);
- 	res_value = div64_u64_rem(arg1_value, arg2_value, &remainder);
- 
- 	ASSERT(res_value <= MAX_I32);
-@@ -144,7 +144,7 @@ struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed signif
- {
- 	struct bw_fixed result;
- 	int64_t multiplicand;
--	multiplicand = div64_u64(arg.value, abs_i64(significance.value));
-+	multiplicand = div64_s64(arg.value, abs_i64(significance.value));
- 	result.value = abs_i64(significance.value) * multiplicand;
- 	ASSERT(abs_i64(result.value) <= abs_i64(arg.value));
- 	return result;
-@@ -153,7 +153,11 @@ struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed signif
- struct bw_fixed bw_ceil(const struct bw_fixed arg, const struct bw_fixed significance)
- {
- 	struct bw_fixed result;
--	div64_u64_rem(arg.value, abs_i64(significance.value), &result.value);
-+	div64_u64_rem(
-+			(uint64_t)arg.value,
-+			(uint64_t)abs_i64(significance.value),
-+			(uint64_t *)&result.value
-+	);
- 	result.value += arg.value;
- 	if (result.value < significance.value)
- 		result.value = significance.value;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 7d90532..861d80a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -280,9 +280,9 @@ static void calculate_scaling_ratios(
- 					== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
- 		stream->ratios.vert.value *= 2;
- 
--	stream->ratios.vert.value = div64_u64(stream->ratios.vert.value * in_h,
-+	stream->ratios.vert.value = div64_s64(stream->ratios.vert.value * in_h,
- 			out_h);
--	stream->ratios.horz.value = div64_u64(stream->ratios.horz.value * in_w ,
-+	stream->ratios.horz.value = div64_s64(stream->ratios.horz.value * in_w ,
- 			out_w);
- 
- 	stream->ratios.horz_c = stream->ratios.horz;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0587-drm-amdgpu-add-semaphore-to-connector-for-mst-syncro.patch b/common/recipes-kernel/linux/files/0587-drm-amdgpu-add-semaphore-to-connector-for-mst-syncro.patch
deleted file mode 100644
index 18922a65..00000000
--- a/common/recipes-kernel/linux/files/0587-drm-amdgpu-add-semaphore-to-connector-for-mst-syncro.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 67c41a1d4ed9c0c182453e17a4591af75c80ee76 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:30:37 +0800
-Subject: [PATCH 0587/1110] drm/amdgpu: add semaphore to connector for mst
- syncronization
-
-When MST branch got disconnected we need to wait to delete
-MST connector, and make sure that reset mode occured on that connector
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index d7b9c93..17811f5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -557,6 +557,7 @@ struct amdgpu_connector {
- 	struct amdgpu_connector *mst_port;
- 	bool is_mst_connector;
- 	struct amdgpu_encoder *mst_encoder;
-+	struct semaphore mst_sem;
- };
- 
- /* TODO: start to use this struct and remove same field from base one */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0588-drm-amdgpu-make-DC-target-const.patch b/common/recipes-kernel/linux/files/0588-drm-amdgpu-make-DC-target-const.patch
deleted file mode 100644
index ebd153fc..00000000
--- a/common/recipes-kernel/linux/files/0588-drm-amdgpu-make-DC-target-const.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 26bfeac51775dd0291c7fd579a2208a7a8490ea1 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:33:45 +0800
-Subject: [PATCH 0588/1110] drm/amdgpu: make DC target const
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 17811f5..61c2345 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -540,6 +540,7 @@ struct amdgpu_connector {
- 	 * The 'current' sink is in dc_link->sink. */
- 	const struct dc_sink *dc_sink;
- 	const struct dc_link *dc_link;
-+	const struct dc_target *target;
- 	void *con_priv;
- 	bool dac_load_detect;
- 	bool detected_by_load; /* if the connection status was determined by load */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0589-drm-amd-dal-Prepare-support-for-next-Asic-generation.patch b/common/recipes-kernel/linux/files/0589-drm-amd-dal-Prepare-support-for-next-Asic-generation.patch
deleted file mode 100644
index dd7e80e1..00000000
--- a/common/recipes-kernel/linux/files/0589-drm-amd-dal-Prepare-support-for-next-Asic-generation.patch
+++ /dev/null
@@ -1,3746 +0,0 @@
-From 52f9ede2646da29cec38ea3536c714eb8f60906c Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Thu, 3 Dec 2015 11:01:33 -0500
-Subject: [PATCH 0589/1110] drm/amd/dal: Prepare support for next Asic
- generation
-
-Support new atombios interfaces.
-Clean up code as preparation for next Asic generation.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |   3 +
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 723 ++++++++--------
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    | 912 +++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/bios/command_table.h    |   3 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |   2 +-
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |   3 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   2 +
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c      |   1 +
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h      |   4 +
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c   |   2 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   2 +-
- .../drm/amd/dal/include/bios_parser_interface.h    |   3 +
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |  35 +
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   |  19 +-
- 14 files changed, 1010 insertions(+), 704 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index 6bac3ed..f553b7a 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -30,7 +30,10 @@
- #include "audio.h"
- #include "hw_ctx_audio.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/audio_dce110.h"
-+#include "dce110/hw_ctx_audio_dce110.h"
-+#endif
- 
- /***** static function : only used within audio.c *****/
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 7a2b247..1d02be9 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -94,6 +94,7 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- 	ATOM_OBJECT *object);
- static void process_ext_display_connection_info(struct bios_parser *bp);
- 
-+
- #define BIOS_IMAGE_SIZE_OFFSET 2
- #define BIOS_IMAGE_SIZE_UNIT 512
- 
-@@ -922,7 +923,7 @@ static enum bp_result get_firmware_info_v1_4(
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
- 	info->pll_info.crystal_frequency =
--			le16_to_cpu(firmware_info->usReferenceClock) * 10;
-+		le16_to_cpu(firmware_info->usReferenceClock) * 10;
- 	info->pll_info.min_input_pxl_clk_pll_frequency =
- 		le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
- 	info->pll_info.max_input_pxl_clk_pll_frequency =
-@@ -973,7 +974,7 @@ static enum bp_result get_firmware_info_v2_1(
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
- 	info->pll_info.crystal_frequency =
--			le16_to_cpu(firmwareInfo->usCoreReferenceClock) * 10;
-+		le16_to_cpu(firmwareInfo->usCoreReferenceClock) * 10;
- 	info->pll_info.min_input_pxl_clk_pll_frequency =
- 		le16_to_cpu(firmwareInfo->usMinPixelClockPLL_Input) * 10;
- 	info->pll_info.max_input_pxl_clk_pll_frequency =
-@@ -1059,7 +1060,7 @@ static enum bp_result get_firmware_info_v2_2(
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
- 	info->pll_info.crystal_frequency =
--			le16_to_cpu(firmware_info->usCoreReferenceClock) * 10;
-+		le16_to_cpu(firmware_info->usCoreReferenceClock) * 10;
- 	info->pll_info.min_input_pxl_clk_pll_frequency =
- 		le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
- 	info->pll_info.max_input_pxl_clk_pll_frequency =
-@@ -1082,10 +1083,10 @@ static enum bp_result get_firmware_info_v2_2(
- 		/* unit of 0.01% */
- 		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
- 	else if (get_ss_info_v3_1(bp,
--		ASIC_INTERNAL_MEMORY_SS, index, &internal_ss) == BP_RESULT_OK) {
-+			ASIC_INTERNAL_MEMORY_SS, index, &internal_ss) == BP_RESULT_OK) {
- 		if (internal_ss.spread_spectrum_percentage) {
- 			info->feature.memory_clk_ss_percentage =
--				internal_ss.spread_spectrum_percentage;
-+					internal_ss.spread_spectrum_percentage;
- 			if (internal_ss.type.CENTER_MODE) {
- 				/* if it is centermode, the exact SS Percentage
- 				 * will be round up of half of the percentage
-@@ -1105,10 +1106,10 @@ static enum bp_result get_firmware_info_v2_2(
- 		/* unit of 0.01% */
- 		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
- 	else if (get_ss_info_v3_1(bp,
--		ASIC_INTERNAL_ENGINE_SS, index, &internal_ss) == BP_RESULT_OK) {
-+			ASIC_INTERNAL_ENGINE_SS, index, &internal_ss) == BP_RESULT_OK) {
- 		if (internal_ss.spread_spectrum_percentage) {
- 			info->feature.engine_clk_ss_percentage =
--				internal_ss.spread_spectrum_percentage;
-+					internal_ss.spread_spectrum_percentage;
- 			if (internal_ss.type.CENTER_MODE) {
- 				/* if it is centermode, the exact SS Percentage
- 				 * will be round up of half of the percentage
-@@ -1126,7 +1127,7 @@ static enum bp_result get_firmware_info_v2_2(
- 	info->min_allowed_bl_level = firmware_info->ucMinAllowedBL_Level;
- 	/* Used starting from CI */
- 	info->smu_gpu_pll_output_freq =
--		(uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10);
-+			(uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10);
- 
- 	return BP_RESULT_OK;
- }
-@@ -1153,11 +1154,11 @@ static enum bp_result get_ss_info_v3_1(
- 		DATA_TABLES(ASIC_InternalSS_Info));
- 	table_size =
- 		(le16_to_cpu(ss_table_header_include->sHeader.usStructureSize)
--		- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				- sizeof(ATOM_COMMON_TABLE_HEADER))
- 				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
- 
- 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
--		&ss_table_header_include->asSpreadSpectrum[0];
-+				&ss_table_header_include->asSpreadSpectrum[0];
- 
- 	dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
- 
-@@ -1193,17 +1194,17 @@ static enum bp_result get_ss_info_v3_1(
- 
- 		/* #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 */
- 		if (SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
--			& tbl[i].ucSpreadSpectrumMode)
-+				& tbl[i].ucSpreadSpectrumMode)
- 			ss_info->spread_percentage_divider = 1000;
- 
- 		ss_info->type.STEP_AND_DELAY_INFO = false;
--		 /* convert [10KHz] into [KHz] */
-+		/* convert [10KHz] into [KHz] */
- 		ss_info->target_clock_range =
--			le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+				le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
- 		ss_info->spread_spectrum_percentage =
--			(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+				(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
- 		ss_info->spread_spectrum_range =
--			(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+				(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
- 
- 		return BP_RESULT_OK;
- 	}
-@@ -1247,7 +1248,17 @@ enum bp_result dal_bios_parser_set_pixel_clock(
- 	if (!bp->cmd_tbl.set_pixel_clock)
- 		return BP_RESULT_FAILURE;
- 
--		return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
-+	return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
-+}
-+
-+enum bp_result dal_bios_parser_set_dce_clock(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params)
-+{
-+	if (!bp->cmd_tbl.set_dce_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_dce_clock(bp, bp_params);
- }
- 
- enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
-@@ -1605,10 +1616,10 @@ enum bp_result dal_bios_parser_get_spread_spectrum_info(
- 			break;
- 		}
- 		break;
--	default:
--		break;
-+		default:
-+			break;
- 	}
--		/* there can not be more then one entry for SS Info table */
-+	/* there can not be more then one entry for SS Info table */
- 	return result;
- }
- 
-@@ -1673,11 +1684,11 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
- 	dc_service_memset(info, 0, sizeof(struct spread_spectrum_info));
- 
- 	tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
--		- sizeof(ATOM_COMMON_TABLE_HEADER))
--				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+					/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
- 
- 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
--				&(header->asSpreadSpectrum[0]);
-+					&(header->asSpreadSpectrum[0]);
- 	for (i = 0; i < tbl_size; i++) {
- 		result = BP_RESULT_NORECORD;
- 
-@@ -1755,7 +1766,7 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 		struct embedded_panel_info panel_info;
- 
- 		if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
--			== BP_RESULT_OK)
-+				== BP_RESULT_OK)
- 			id_local = panel_info.ss_id;
- 		break;
- 	}
-@@ -1767,8 +1778,8 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 		return result;
- 
- 	table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
--		sizeof(ATOM_COMMON_TABLE_HEADER)) /
--			sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+			sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+					sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
- 
- 	for (i = 0; i < table_size; i++) {
- 		if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
-@@ -1777,11 +1788,11 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 		dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
- 
- 		if (ATOM_EXTERNAL_SS_MASK &
--			tbl->asSS_Info[i].ucSpreadSpectrumType)
-+				tbl->asSS_Info[i].ucSpreadSpectrumType)
- 			ss_info->type.EXTERNAL = true;
- 
- 		if (ATOM_SS_CENTRE_SPREAD_MODE_MASK &
--			tbl->asSS_Info[i].ucSpreadSpectrumType)
-+				tbl->asSS_Info[i].ucSpreadSpectrumType)
- 			ss_info->type.CENTER_MODE = true;
- 
- 		ss_info->type.STEP_AND_DELAY_INFO = true;
-@@ -1836,7 +1847,7 @@ enum bp_result dal_bios_parser_get_embedded_panel_info(
- 		default:
- 			break;
- 		}
--	default:
-+		default:
- 			break;
- 	}
- 
-@@ -1878,7 +1889,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
- 	/* doesn't have borders, so we should be okay leaving this as is for
- 	 * now.  May need to revisit if we ever have LVDS with borders*/
- 	info->lcd_timing.horizontal_blanking_time =
--		le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+			le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
- 	/* usVActive does not include borders, according to VBIOS team*/
- 	info->lcd_timing.vertical_addressable =
- 			le16_to_cpu(lvds->sLCDTiming.usVActive);
-@@ -1937,7 +1948,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
- 
- 	/*Drr panel support can be reported by VBIOS*/
- 	if (LCDPANEL_CAP_DRR_SUPPORTED
--		& lvds->ucLCDPanel_SpecialHandlingCap)
-+			& lvds->ucLCDPanel_SpecialHandlingCap)
- 		info->drr_enabled = 1;
- 
- 	if (ATOM_PANEL_MISC_DUAL & lvds->ucLVDS_Misc)
-@@ -1948,7 +1959,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
- 
- 	info->lcd_timing.misc_info.GREY_LEVEL =
- 		(uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL &
--		lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT;
-+			lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT;
- 
- 	if (ATOM_PANEL_MISC_SPATIAL & lvds->ucLVDS_Misc)
- 		info->lcd_timing.misc_info.SPATIAL = true;
-@@ -1980,17 +1991,17 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 		return BP_RESULT_BADBIOSTABLE;
- 
- 	if (!((1 == lvds->sHeader.ucTableFormatRevision)
--		&& (3 <= lvds->sHeader.ucTableContentRevision)))
-+			&& (3 <= lvds->sHeader.ucTableContentRevision)))
- 		return BP_RESULT_UNSUPPORTED;
- 
- 	dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
- 
- 	/* We need to convert from 10KHz units into KHz units */
- 	info->lcd_timing.pixel_clk =
--		le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+			le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
- 	/* usHActive does not include borders, according to VBIOS team */
- 	info->lcd_timing.horizontal_addressable =
--		le16_to_cpu(lvds->sLCDTiming.usHActive);
-+			le16_to_cpu(lvds->sLCDTiming.usHActive);
- 	/* usHBlanking_Time includes borders, so we should really be subtracting
- 	 * borders duing this translation, but LVDS generally*/
- 	/* doesn't have borders, so we should be okay leaving this as is for
-@@ -2040,13 +2051,13 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 
- 	/* Drr panel support can be reported by VBIOS*/
- 	if (LCDPANEL_CAP_V13_DRR_SUPPORTED
--		& lvds->ucLCDPanel_SpecialHandlingCap)
-+			& lvds->ucLCDPanel_SpecialHandlingCap)
- 		info->drr_enabled = 1;
- 
- 	/* Get supported refresh rate*/
- 	if (info->drr_enabled == 1) {
- 		uint8_t min_rr =
--			lvds->sRefreshRateSupport.ucMinRefreshRateForDRR;
-+				lvds->sRefreshRateSupport.ucMinRefreshRateForDRR;
- 		uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate;
- 
- 		if (min_rr != 0) {
-@@ -2081,8 +2092,8 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 		info->lcd_timing.misc_info.RGB888 = true;
- 
- 	info->lcd_timing.misc_info.GREY_LEVEL =
--		(uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL &
--		lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT;
-+			(uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL &
-+				lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT;
- 
- 	return BP_RESULT_OK;
- }
-@@ -2150,7 +2161,7 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- 	}
- 
- 	offset = le16_to_cpu(object->usRecordOffset)
--			+ bp->object_info_tbl_offset;
-+					+ bp->object_info_tbl_offset;
- 
- 	for (;;) {
- 		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-@@ -2161,7 +2172,7 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- 		offset += header->ucRecordSize;
- 
- 		if (LAST_RECORD_TYPE == header->ucRecordType ||
--			!header->ucRecordSize)
-+				!header->ucRecordSize)
- 			break;
- 
- 		if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType)
-@@ -2210,7 +2221,7 @@ enum bp_result dal_bios_parser_get_din_connector_info(
- 	}
- 
- 	offset = le16_to_cpu(object->usRecordOffset)
--				+ bp->object_info_tbl_offset;
-+						+ bp->object_info_tbl_offset;
- 
- 	for (;;) {
- 		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-@@ -2224,15 +2235,15 @@ enum bp_result dal_bios_parser_get_din_connector_info(
- 
- 		/* get out of the loop if no more records */
- 		if (LAST_RECORD_TYPE == header->ucRecordType ||
--			!header->ucRecordSize)
-+				!header->ucRecordSize)
- 			break;
- 
- 		if (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE !=
--			header->ucRecordType)
-+				header->ucRecordType)
- 			continue;
- 
- 		if (sizeof(ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD)
--			> header->ucRecordSize)
-+				> header->ucRecordSize)
- 			continue;
- 
- 		record = (ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *)header;
-@@ -2285,7 +2296,7 @@ uint32_t dal_bios_parser_get_ss_entry_number(
- 		return get_ss_entry_number_from_ss_info_tbl(bp, ss_id);
- 
- 	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
--		DATA_TABLES(ASIC_InternalSS_Info));
-+			DATA_TABLES(ASIC_InternalSS_Info));
- 	get_atom_data_table_revision(header, &revision);
- 
- 	switch (revision.major) {
-@@ -2301,14 +2312,14 @@ uint32_t dal_bios_parser_get_ss_entry_number(
- 		switch (revision.minor) {
- 		case 1:
- 			return
--			get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
--				bp, ss_id);
-+				get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+						bp, ss_id);
- 		default:
- 			break;
- 		}
- 		break;
--	default:
--		break;
-+		default:
-+			break;
- 	}
- 
- 	return 0;
-@@ -2341,11 +2352,11 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
- 		return number;
- 
- 	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
--		DATA_TABLES(SS_Info));
-+			DATA_TABLES(SS_Info));
- 	get_atom_data_table_revision(header, &revision);
- 
- 	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO,
--		DATA_TABLES(SS_Info));
-+			DATA_TABLES(SS_Info));
- 
- 	if (1 != revision.major || 2 > revision.minor)
- 		return number;
-@@ -2359,7 +2370,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
- 		struct embedded_panel_info panel_info;
- 
- 		if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
--			== BP_RESULT_OK)
-+				== BP_RESULT_OK)
- 			id_local = panel_info.ss_id;
- 		break;
- 	}
-@@ -2371,8 +2382,8 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
- 		return number;
- 
- 	table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
--		sizeof(ATOM_COMMON_TABLE_HEADER)) /
--			sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+			sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+					sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
- 
- 	for (i = 0; i < table_size; i++)
- 		if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) {
-@@ -2424,14 +2435,14 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
- 		return 0;
- 
- 	header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
--		DATA_TABLES(ASIC_InternalSS_Info));
-+			DATA_TABLES(ASIC_InternalSS_Info));
- 
- 	size = (le16_to_cpu(header_include->sHeader.usStructureSize)
--		- sizeof(ATOM_COMMON_TABLE_HEADER))
--				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+						/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
- 
- 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
--		&header_include->asSpreadSpectrum[0];
-+				&header_include->asSpreadSpectrum[0];
- 	for (i = 0; i < size; i++)
- 		if (tbl[i].ucClockIndication == (uint8_t)id)
- 			return 1;
-@@ -2460,13 +2471,13 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
- 		return number;
- 
- 	header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
--		DATA_TABLES(ASIC_InternalSS_Info));
-+			DATA_TABLES(ASIC_InternalSS_Info));
- 	size = (le16_to_cpu(header_include->sHeader.usStructureSize) -
--		sizeof(ATOM_COMMON_TABLE_HEADER)) /
--			sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+			sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+					sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
- 
- 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
--		&header_include->asSpreadSpectrum[0];
-+				&header_include->asSpreadSpectrum[0];
- 
- 	for (i = 0; i < size; i++)
- 		if (tbl[i].ucClockIndication == (uint8_t)id)
-@@ -2491,14 +2502,14 @@ static ATOM_FAKE_EDID_PATCH_RECORD *get_faked_edid_record(
- 		return NULL;
- 
- 	if (1 != info->sHeader.ucTableFormatRevision
--		|| 2 > info->sHeader.ucTableContentRevision)
-+			|| 2 > info->sHeader.ucTableContentRevision)
- 		return NULL;
- 
- 	if (!le16_to_cpu(info->usExtInfoTableOffset))
- 		return NULL;
- 
- 	record = GET_IMAGE(uint8_t, DATA_TABLES(LVDS_Info)
--		+ le16_to_cpu(info->usExtInfoTableOffset));
-+			+ le16_to_cpu(info->usExtInfoTableOffset));
- 
- 	if (!record)
- 		return NULL;
-@@ -2586,15 +2597,15 @@ enum bp_result dal_bios_parser_get_gpio_pin_info(
- 		return BP_RESULT_BADBIOSTABLE;
- 
- 	if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_PIN_LUT)
--		> le16_to_cpu(header->sHeader.usStructureSize))
-+			> le16_to_cpu(header->sHeader.usStructureSize))
- 		return BP_RESULT_BADBIOSTABLE;
- 
- 	if (1 != header->sHeader.ucTableContentRevision)
- 		return BP_RESULT_UNSUPPORTED;
- 
- 	count = (le16_to_cpu(header->sHeader.usStructureSize)
--		- sizeof(ATOM_COMMON_TABLE_HEADER))
--		/ sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
- 	for (i = 0; i < count; ++i) {
- 		if (header->asGPIO_Pin[i].ucGPIO_ID != gpio_id)
- 			continue;
-@@ -2650,14 +2661,14 @@ enum bp_result dal_bios_parser_enum_embedded_panel_patch_mode(
- 		return BP_RESULT_BADBIOSTABLE;
- 
- 	if (1 != info->sHeader.ucTableFormatRevision
--		|| 2 > info->sHeader.ucTableContentRevision)
-+			|| 2 > info->sHeader.ucTableContentRevision)
- 		return BP_RESULT_UNSUPPORTED;
- 
- 	if (!le16_to_cpu(info->usExtInfoTableOffset))
- 		return BP_RESULT_UNSUPPORTED;
- 
- 	record = GET_IMAGE(uint8_t, list_of_tables->LVDS_Info +
--		le16_to_cpu(info->usExtInfoTableOffset));
-+			le16_to_cpu(info->usExtInfoTableOffset));
- 
- 	if (!record)
- 		return BP_RESULT_BADBIOSTABLE;
-@@ -2707,7 +2718,7 @@ static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
- 		return BP_RESULT_BADBIOSTABLE;
- 
- 	if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_I2C_ASSIGMENT)
--		> le16_to_cpu(header->sHeader.usStructureSize))
-+			> le16_to_cpu(header->sHeader.usStructureSize))
- 		return BP_RESULT_BADBIOSTABLE;
- 
- 	if (1 != header->sHeader.ucTableContentRevision)
-@@ -2715,8 +2726,8 @@ static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
- 
- 	/* get data count */
- 	count = (le16_to_cpu(header->sHeader.usStructureSize)
--		- sizeof(ATOM_COMMON_TABLE_HEADER))
--		/ sizeof(ATOM_GPIO_I2C_ASSIGMENT);
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_GPIO_I2C_ASSIGMENT);
- 	if (count < record->sucI2cId.bfI2C_LineMux)
- 		return BP_RESULT_BADBIOSTABLE;
- 
-@@ -2727,38 +2738,38 @@ static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
- 	info->i2c_slave_address = record->ucI2CAddr;
- 
- 	info->gpio_info.clk_mask_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkMaskRegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkMaskRegisterIndex);
- 	info->gpio_info.clk_en_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkEnRegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkEnRegisterIndex);
- 	info->gpio_info.clk_y_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkY_RegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkY_RegisterIndex);
- 	info->gpio_info.clk_a_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkA_RegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkA_RegisterIndex);
- 	info->gpio_info.data_mask_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataMaskRegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataMaskRegisterIndex);
- 	info->gpio_info.data_en_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataEnRegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataEnRegisterIndex);
- 	info->gpio_info.data_y_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataY_RegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataY_RegisterIndex);
- 	info->gpio_info.data_a_register_index =
--		le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataA_RegisterIndex);
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataA_RegisterIndex);
- 
- 	info->gpio_info.clk_mask_shift =
--		header->asGPIO_Info[info->i2c_line].ucClkMaskShift;
-+			header->asGPIO_Info[info->i2c_line].ucClkMaskShift;
- 	info->gpio_info.clk_en_shift =
--		header->asGPIO_Info[info->i2c_line].ucClkEnShift;
-+			header->asGPIO_Info[info->i2c_line].ucClkEnShift;
- 	info->gpio_info.clk_y_shift =
--		header->asGPIO_Info[info->i2c_line].ucClkY_Shift;
-+			header->asGPIO_Info[info->i2c_line].ucClkY_Shift;
- 	info->gpio_info.clk_a_shift =
--		header->asGPIO_Info[info->i2c_line].ucClkA_Shift;
-+			header->asGPIO_Info[info->i2c_line].ucClkA_Shift;
- 	info->gpio_info.data_mask_shift =
--		header->asGPIO_Info[info->i2c_line].ucDataMaskShift;
-+			header->asGPIO_Info[info->i2c_line].ucDataMaskShift;
- 	info->gpio_info.data_en_shift =
--		header->asGPIO_Info[info->i2c_line].ucDataEnShift;
-+			header->asGPIO_Info[info->i2c_line].ucDataEnShift;
- 	info->gpio_info.data_y_shift =
--		header->asGPIO_Info[info->i2c_line].ucDataY_Shift;
-+			header->asGPIO_Info[info->i2c_line].ucDataY_Shift;
- 	info->gpio_info.data_a_shift =
--		header->asGPIO_Info[info->i2c_line].ucDataA_Shift;
-+			header->asGPIO_Info[info->i2c_line].ucDataA_Shift;
- 
- 	return BP_RESULT_OK;
- }
-@@ -2801,8 +2812,8 @@ static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
- 
- 	for (i = 0; i < tbl->ucNumberOfObjects; i++)
- 		if (dal_graphics_object_id_is_equal(id,
--			object_id_from_bios_object_id(
--				le16_to_cpu(tbl->asObjects[i].usObjectID))))
-+				object_id_from_bios_object_id(
-+						le16_to_cpu(tbl->asObjects[i].usObjectID))))
- 			return &tbl->asObjects[i];
- 
- 	return NULL;
-@@ -2820,7 +2831,7 @@ static uint32_t get_dest_obj_list(struct bios_parser *bp,
- 	}
- 
- 	offset = le16_to_cpu(object->usSrcDstTableOffset)
--				+ bp->object_info_tbl_offset;
-+						+ bp->object_info_tbl_offset;
- 
- 	number = GET_IMAGE(uint8_t, offset);
- 	if (!number)
-@@ -2835,7 +2846,7 @@ static uint32_t get_dest_obj_list(struct bios_parser *bp,
- 
- 	offset += sizeof(uint8_t);
- 	*id_list = (uint16_t *)get_image(bp, offset,
--		*number * sizeof(uint16_t));
-+			*number * sizeof(uint16_t));
- 
- 	if (!*id_list)
- 		return 0;
-@@ -2855,7 +2866,7 @@ static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
- 	}
- 
- 	offset = le16_to_cpu(object->usSrcDstTableOffset)
--			+ bp->object_info_tbl_offset;
-+					+ bp->object_info_tbl_offset;
- 
- 	number = GET_IMAGE(uint8_t, offset);
- 	if (!number)
-@@ -2863,7 +2874,7 @@ static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
- 
- 	offset += sizeof(uint8_t);
- 	*id_list = (uint16_t *)get_image(bp, offset,
--		*number * sizeof(uint16_t));
-+			*number * sizeof(uint16_t));
- 
- 	if (!*id_list)
- 		return 0;
-@@ -2883,7 +2894,7 @@ static uint32_t get_dst_number_from_object(struct bios_parser *bp,
- 	}
- 
- 	offset = le16_to_cpu(object->usSrcDstTableOffset)
--			+ bp->object_info_tbl_offset;
-+					+ bp->object_info_tbl_offset;
- 
- 	number = GET_IMAGE(uint8_t, offset);
- 	if (!number)
-@@ -2924,11 +2935,11 @@ static uint32_t get_record_size(uint8_t *record)
- 
- 	case LCD_FAKE_EDID_PATCH_RECORD_TYPE: {
- 		ATOM_FAKE_EDID_PATCH_RECORD *fake_record =
--			(ATOM_FAKE_EDID_PATCH_RECORD *) record;
-+				(ATOM_FAKE_EDID_PATCH_RECORD *) record;
- 		uint32_t edid_size = get_edid_size(fake_record);
- 
- 		return sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + edid_size
--			- sizeof(fake_record->ucFakeEDIDString);
-+				- sizeof(fake_record->ucFakeEDIDString);
- 	}
- 
- 	case LCD_PANEL_RESOLUTION_RECORD_TYPE:
-@@ -2967,7 +2978,7 @@ static struct graphics_object_id object_id_from_bios_object_id(
- 		return go_id;
- 
- 	go_id = dal_graphics_object_id_init(
--		id_from_bios_object_id(type, bios_object_id), enum_id, type);
-+			id_from_bios_object_id(type, bios_object_id), enum_id, type);
- 
- 	return go_id;
- }
-@@ -2975,7 +2986,7 @@ static struct graphics_object_id object_id_from_bios_object_id(
- static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
- {
- 	uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
--		>> OBJECT_TYPE_SHIFT;
-+				>> OBJECT_TYPE_SHIFT;
- 	enum object_type object_type;
- 
- 	switch (bios_object_type) {
-@@ -3005,7 +3016,7 @@ static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
- static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
- {
- 	uint32_t bios_enum_id =
--		(bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
-+			(bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
- 	enum object_enum_id id;
- 
- 	switch (bios_enum_id) {
-@@ -3048,7 +3059,7 @@ static uint32_t id_from_bios_object_id(enum object_type type,
- 		return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);
- 	case OBJECT_TYPE_CONNECTOR:
- 		return (uint32_t)connector_id_from_bios_object_id(
--			bios_object_id);
-+				bios_object_id);
- 	case OBJECT_TYPE_GENERIC:
- 		return generic_id_from_bios_object_id(bios_object_id);
- 	default:
-@@ -3341,9 +3352,9 @@ static void get_atom_data_table_revision(
- 		return;
- 
- 	tbl_revision->major =
--		(uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl);
-+			(uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl);
- 	tbl_revision->minor =
--		(uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl);
-+			(uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl);
- }
- 
- static uint32_t signal_to_ss_id(enum as_signal_type signal)
-@@ -3388,52 +3399,52 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
- 			break;
- 		}
- 		break;
--	case DEVICE_TYPE_CRT:
--		switch (enum_id) {
--		case 1:
--			return ATOM_DEVICE_CRT1_SUPPORT;
--		case 2:
--			return ATOM_DEVICE_CRT2_SUPPORT;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_DFP:
--		switch (enum_id) {
--		case 1:
--			return ATOM_DEVICE_DFP1_SUPPORT;
--		case 2:
--			return ATOM_DEVICE_DFP2_SUPPORT;
--		case 3:
--			return ATOM_DEVICE_DFP3_SUPPORT;
--		case 4:
--			return ATOM_DEVICE_DFP4_SUPPORT;
--		case 5:
--			return ATOM_DEVICE_DFP5_SUPPORT;
--		case 6:
--			return ATOM_DEVICE_DFP6_SUPPORT;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_CV:
--		switch (enum_id) {
--		case 1:
--			return ATOM_DEVICE_CV_SUPPORT;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_TV:
--		switch (enum_id) {
--		case 1:
--			return ATOM_DEVICE_TV1_SUPPORT;
--		default:
-+		case DEVICE_TYPE_CRT:
-+			switch (enum_id) {
-+			case 1:
-+				return ATOM_DEVICE_CRT1_SUPPORT;
-+			case 2:
-+				return ATOM_DEVICE_CRT2_SUPPORT;
-+			default:
-+				break;
-+			}
- 			break;
--		}
--		break;
--	default:
--		break;
-+			case DEVICE_TYPE_DFP:
-+				switch (enum_id) {
-+				case 1:
-+					return ATOM_DEVICE_DFP1_SUPPORT;
-+				case 2:
-+					return ATOM_DEVICE_DFP2_SUPPORT;
-+				case 3:
-+					return ATOM_DEVICE_DFP3_SUPPORT;
-+				case 4:
-+					return ATOM_DEVICE_DFP4_SUPPORT;
-+				case 5:
-+					return ATOM_DEVICE_DFP5_SUPPORT;
-+				case 6:
-+					return ATOM_DEVICE_DFP6_SUPPORT;
-+				default:
-+					break;
-+				}
-+				break;
-+				case DEVICE_TYPE_CV:
-+					switch (enum_id) {
-+					case 1:
-+						return ATOM_DEVICE_CV_SUPPORT;
-+					default:
-+						break;
-+					}
-+					break;
-+					case DEVICE_TYPE_TV:
-+						switch (enum_id) {
-+						case 1:
-+							return ATOM_DEVICE_TV1_SUPPORT;
-+						default:
-+							break;
-+						}
-+						break;
-+						default:
-+							break;
- 	};
- 
- 	/* Unidentified device ID, return empty support mask. */
-@@ -3441,8 +3452,8 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
- }
- 
- /**
--*  HwContext interface for writing MM registers
--*/
-+ *  HwContext interface for writing MM registers
-+ */
- 
- static bool i2c_read(
- 	struct bios_parser *bp,
-@@ -3466,27 +3477,27 @@ static bool i2c_read(
- 
- 	{
- 		struct i2c_payload payloads[] = {
--			{
--				.address = i2c_info->i2c_slave_address >> 1,
--				.data = offset,
--				.length = sizeof(offset),
--				.write = true
--			},
--			{
--				.address = i2c_info->i2c_slave_address >> 1,
--				.data = buffer,
--				.length = length,
--				.write = false
--			}
-+				{
-+						.address = i2c_info->i2c_slave_address >> 1,
-+						.data = offset,
-+						.length = sizeof(offset),
-+						.write = true
-+				},
-+				{
-+						.address = i2c_info->i2c_slave_address >> 1,
-+						.data = buffer,
-+						.length = length,
-+						.write = false
-+				}
- 		};
- 
- 		cmd.payloads = payloads;
- 		cmd.number_of_payloads = ARRAY_SIZE(payloads);
- 
- 		result = dal_i2caux_submit_i2c_command(
--			dal_adapter_service_get_i2caux(bp->as),
--			ddc,
--			&cmd);
-+				dal_adapter_service_get_i2caux(bp->as),
-+				ddc,
-+				&cmd);
- 	}
- 
- 	dal_adapter_service_release_ddc(bp->as, ddc);
-@@ -3519,20 +3530,20 @@ static enum bp_result get_ext_display_connection_info(
- 		struct graphics_object_i2c_info i2c_info;
- 
- 		gpio_i2c_header = GET_IMAGE(ATOM_GPIO_I2C_INFO,
--			bp->master_data_tbl->ListOfDataTables.GPIO_I2C_Info);
-+				bp->master_data_tbl->ListOfDataTables.GPIO_I2C_Info);
- 
- 		if (NULL == gpio_i2c_header)
- 			return BP_RESULT_BADBIOSTABLE;
- 
- 		if (get_gpio_i2c_info(bp, i2c_record, &i2c_info) !=
--			BP_RESULT_OK)
-+				BP_RESULT_OK)
- 			return BP_RESULT_BADBIOSTABLE;
- 
- 		if (i2c_read(
--			bp,
--			&i2c_info,
--			(uint8_t *)ext_display_connection_info_tbl,
--			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
-+				bp,
-+				&i2c_info,
-+				(uint8_t *)ext_display_connection_info_tbl,
-+				sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
- 			config_tbl_present = true;
- 		}
- 	}
-@@ -3541,7 +3552,7 @@ static enum bp_result get_ext_display_connection_info(
- 	if (config_tbl_present)
- 		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; i++) {
- 			if (ext_display_connection_info_tbl->ucGuid[i]
--				!= ext_display_connection_guid[i]) {
-+														!= ext_display_connection_guid[i]) {
- 				config_tbl_present = false;
- 				break;
- 			}
-@@ -3551,10 +3562,10 @@ static enum bp_result get_ext_display_connection_info(
- 	if (config_tbl_present) {
- 		uint8_t check_sum = 0;
- 		uint8_t *buf =
--			(uint8_t *)ext_display_connection_info_tbl;
-+				(uint8_t *)ext_display_connection_info_tbl;
- 
- 		for (i = 0; i < sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
--			i++) {
-+				i++) {
- 			check_sum += buf[i];
- 		}
- 
-@@ -3646,9 +3657,9 @@ static bool get_patched_device_tag(
- 	/* Use fallback behaviour if not supported. */
- 	if (!bp->remap_device_tags) {
- 		device_tag->ulACPIDeviceEnum =
--			cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+				cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
- 		device_tag->usDeviceID =
--			cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceTag));
-+				cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceTag));
- 		return true;
- 	}
- 
-@@ -3658,7 +3669,7 @@ static bool get_patched_device_tag(
- 		/* Assign this device ID if supported. */
- 		if ((device_support & dev_id) != 0) {
- 			device_tag->ulACPIDeviceEnum =
--				cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+					cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
- 			device_tag->usDeviceID = cpu_to_le16((USHORT) dev_id);
- 			return true;
- 		}
-@@ -3688,31 +3699,31 @@ static void add_device_tag_from_ext_display_path(
- 	ATOM_CONNECTOR_DEVICE_TAG *device_tag = NULL;
- 	ATOM_CONNECTOR_DEVICE_TAG_RECORD *device_tag_record = NULL;
- 	enum bp_result result =
--		dal_bios_parser_get_device_tag_record(
--			bp, object, &device_tag_record);
-+			dal_bios_parser_get_device_tag_record(
-+					bp, object, &device_tag_record);
- 
- 	if ((le16_to_cpu(ext_display_path->usDeviceTag) != CONNECTOR_OBJECT_ID_NONE)
--		&& (result == BP_RESULT_OK)) {
-+			&& (result == BP_RESULT_OK)) {
- 		uint8_t index;
- 
- 		if ((device_tag_record->ucNumberOfDevice == 1) &&
--			(le16_to_cpu(device_tag_record->asDeviceTag[0].usDeviceID) == 0)) {
-+				(le16_to_cpu(device_tag_record->asDeviceTag[0].usDeviceID) == 0)) {
- 			/*Workaround bug in current VBIOS releases where
- 			 * ucNumberOfDevice = 1 but there is no actual device
- 			 * tag data. This w/a is temporary until the updated
- 			 * VBIOS is distributed. */
- 			device_tag_record->ucNumberOfDevice =
--				device_tag_record->ucNumberOfDevice - 1;
-+					device_tag_record->ucNumberOfDevice - 1;
- 		}
- 
- 		/* Attempt to find a matching device ID. */
- 		index = device_tag_record->ucNumberOfDevice;
- 		device_tag = &device_tag_record->asDeviceTag[index];
- 		if (get_patched_device_tag(
--			bp,
--			ext_display_path,
--			*device_support,
--			device_tag)) {
-+				bp,
-+				ext_display_path,
-+				*device_support,
-+				device_tag)) {
- 			/* Update cached device support to remove assigned ID.
- 			 */
- 			*device_support &= ~le16_to_cpu(device_tag->usDeviceID);
-@@ -3737,7 +3748,7 @@ static EXT_DISPLAY_PATH *get_ext_display_path_entry(
- {
- 	EXT_DISPLAY_PATH *ext_display_path;
- 	uint32_t ext_display_path_index =
--		((bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT) - 1;
-+			((bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT) - 1;
- 
- 	if (ext_display_path_index >= MAX_NUMBER_OF_EXT_DISPLAY_PATH)
- 		return NULL;
-@@ -3770,7 +3781,7 @@ static ATOM_CONNECTOR_AUXDDC_LUT_RECORD *get_ext_connector_aux_ddc_lut_record(
- 	}
- 
- 	offset = le16_to_cpu(object->usRecordOffset)
--			+ bp->object_info_tbl_offset;
-+					+ bp->object_info_tbl_offset;
- 
- 	for (;;) {
- 		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-@@ -3779,13 +3790,13 @@ static ATOM_CONNECTOR_AUXDDC_LUT_RECORD *get_ext_connector_aux_ddc_lut_record(
- 			return NULL;
- 
- 		if (LAST_RECORD_TYPE == header->ucRecordType ||
--			0 == header->ucRecordSize)
-+				0 == header->ucRecordSize)
- 			break;
- 
- 		if (ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE ==
--			header->ucRecordType &&
--			sizeof(ATOM_CONNECTOR_AUXDDC_LUT_RECORD) <=
--			header->ucRecordSize)
-+				header->ucRecordType &&
-+				sizeof(ATOM_CONNECTOR_AUXDDC_LUT_RECORD) <=
-+				header->ucRecordSize)
- 			return (ATOM_CONNECTOR_AUXDDC_LUT_RECORD *)(header);
- 
- 		offset += header->ucRecordSize;
-@@ -3814,7 +3825,7 @@ static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
- 	}
- 
- 	offset = le16_to_cpu(object->usRecordOffset)
--			+ bp->object_info_tbl_offset;
-+					+ bp->object_info_tbl_offset;
- 
- 	for (;;) {
- 		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-@@ -3823,13 +3834,13 @@ static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
- 			return NULL;
- 
- 		if (LAST_RECORD_TYPE == header->ucRecordType ||
--			0 == header->ucRecordSize)
-+				0 == header->ucRecordSize)
- 			break;
- 
- 		if (ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE ==
--			header->ucRecordType &&
--			sizeof(ATOM_CONNECTOR_HPDPIN_LUT_RECORD) <=
--			header->ucRecordSize)
-+				header->ucRecordType &&
-+				sizeof(ATOM_CONNECTOR_HPDPIN_LUT_RECORD) <=
-+				header->ucRecordSize)
- 			return (ATOM_CONNECTOR_HPDPIN_LUT_RECORD *)header;
- 
- 		offset += header->ucRecordSize;
-@@ -3866,13 +3877,13 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 	ATOM_OBJECT *opm_object = NULL;
- 	uint32_t i = 0;
- 	struct graphics_object_id opm_object_id =
--		dal_graphics_object_id_init(
--			GENERIC_ID_MXM_OPM,
--			ENUM_ID_1,
--			OBJECT_TYPE_GENERIC);
-+			dal_graphics_object_id_init(
-+					GENERIC_ID_MXM_OPM,
-+					ENUM_ID_1,
-+					OBJECT_TYPE_GENERIC);
- 	ATOM_CONNECTOR_DEVICE_TAG_RECORD *dev_tag_record;
- 	uint32_t cached_device_support =
--		le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport);
-+			le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport);
- 
- 	uint32_t dst_number;
- 	uint16_t *dst_object_id_list;
-@@ -3882,23 +3893,23 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 		return BP_RESULT_UNSUPPORTED;
- 
- 	dc_service_memset(&ext_display_connection_info_tbl, 0,
--		sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
-+			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
- 
- 	connector_tbl_offset = bp->object_info_tbl_offset
--		+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+			+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
- 	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
- 
- 	/* Read Connector info table from EEPROM through i2c */
- 	if (get_ext_display_connection_info(
--		bp,
--		opm_object,
--		&ext_display_connection_info_tbl) != BP_RESULT_OK) {
-+			bp,
-+			opm_object,
-+			&ext_display_connection_info_tbl) != BP_RESULT_OK) {
- 		if (bp->headless_no_opm) {
- 			/* Failed to read OPM, remove all non-CF connectors. */
- 			for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
- 				object = &connector_tbl->asObjects[i];
- 				object_id = object_id_from_bios_object_id(
--					le16_to_cpu(object->usObjectID));
-+						le16_to_cpu(object->usObjectID));
- 				if (OBJECT_TYPE_CONNECTOR == object_id.type)
- 					object->usObjectID = cpu_to_le16(0);
- 			}
-@@ -3907,17 +3918,17 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 		}
- 
- 		dal_logger_write(bp->ctx->logger,
--			LOG_MAJOR_BIOS,
--			LOG_MINOR_BIOS_CMD_TABLE,
--			"%s: Failed to read Connection Info Table", __func__);
-+				LOG_MAJOR_BIOS,
-+				LOG_MINOR_BIOS_CMD_TABLE,
-+				"%s: Failed to read Connection Info Table", __func__);
- 		return BP_RESULT_UNSUPPORTED;
- 	}
- 
- 	/* Get pointer to AUX/DDC and HPD LUTs */
- 	aux_ddc_lut_record =
--		get_ext_connector_aux_ddc_lut_record(bp, opm_object);
-+			get_ext_connector_aux_ddc_lut_record(bp, opm_object);
- 	hpd_pin_lut_record =
--		get_ext_connector_hpd_pin_lut_record(bp, opm_object);
-+			get_ext_connector_hpd_pin_lut_record(bp, opm_object);
- 
- 	if ((aux_ddc_lut_record == NULL) || (hpd_pin_lut_record == NULL))
- 		return BP_RESULT_UNSUPPORTED;
-@@ -3929,21 +3940,21 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 			/* Remove support for all non-MXM connectors. */
- 			object = &connector_tbl->asObjects[i];
- 			object_id = object_id_from_bios_object_id(
--				le16_to_cpu(object->usObjectID));
-+					le16_to_cpu(object->usObjectID));
- 			if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
--				(CONNECTOR_ID_MXM == object_id.id))
-+					(CONNECTOR_ID_MXM == object_id.id))
- 				continue;
- 
- 			/* Remove support for all device tags. */
- 			if (dal_bios_parser_get_device_tag_record(
--				bp, object, &dev_tag_record) != BP_RESULT_OK)
-+					bp, object, &dev_tag_record) != BP_RESULT_OK)
- 				continue;
- 
- 			for (j = 0; j < dev_tag_record->ucNumberOfDevice; ++j) {
- 				ATOM_CONNECTOR_DEVICE_TAG *device_tag =
--					&dev_tag_record->asDeviceTag[j];
-+						&dev_tag_record->asDeviceTag[j];
- 				cached_device_support &=
--					~le16_to_cpu(device_tag->usDeviceID);
-+						~le16_to_cpu(device_tag->usDeviceID);
- 			}
- 		}
- 	}
-@@ -3956,37 +3967,37 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 		object = &connector_tbl->asObjects[i];
- 		object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
- 		if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
--			(CONNECTOR_ID_MXM != object_id.id))
-+				(CONNECTOR_ID_MXM != object_id.id))
- 			continue;
- 
- 		/* Get the correct connection info table entry based on the enum
- 		 * id. */
- 		ext_display_path = get_ext_display_path_entry(
--			&ext_display_connection_info_tbl,
--			le16_to_cpu(object->usObjectID));
-+				&ext_display_connection_info_tbl,
-+				le16_to_cpu(object->usObjectID));
- 		if (!ext_display_path)
- 			return BP_RESULT_FAILURE;
- 
- 		/* Patch device connector ID */
- 		object->usObjectID =
--			cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceConnector));
-+				cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceConnector));
- 
- 		/* Patch device tag, ulACPIDeviceEnum. */
- 		add_device_tag_from_ext_display_path(
--			bp,
--			object,
--			ext_display_path,
--			&cached_device_support);
-+				bp,
-+				object,
-+				ext_display_path,
-+				&cached_device_support);
- 
- 		/* Patch HPD info */
- 		if (ext_display_path->ucExtHPDPINLutIndex <
--			MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES) {
-+				MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES) {
- 			hpd_record = get_hpd_record(bp, object);
- 			if (hpd_record) {
- 				uint8_t index =
--					ext_display_path->ucExtHPDPINLutIndex;
-+						ext_display_path->ucExtHPDPINLutIndex;
- 				hpd_record->ucHPDIntGPIOID =
--					hpd_pin_lut_record->ucHPDPINMap[index];
-+						hpd_pin_lut_record->ucHPDPINMap[index];
- 			} else {
- 				BREAK_TO_DEBUGGER();
- 				/* Invalid hpd record */
-@@ -3996,13 +4007,13 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 
- 		/* Patch I2C/AUX info */
- 		if (ext_display_path->ucExtHPDPINLutIndex <
--			MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES) {
-+				MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES) {
- 			i2c_record = get_i2c_record(bp, object);
- 			if (i2c_record) {
- 				uint8_t index =
--					ext_display_path->ucExtAUXDDCLutIndex;
-+						ext_display_path->ucExtAUXDDCLutIndex;
- 				i2c_record->sucI2cId =
--					aux_ddc_lut_record->ucAUXDDCMap[index];
-+						aux_ddc_lut_record->ucAUXDDCMap[index];
- 			} else {
- 				BREAK_TO_DEBUGGER();
- 				/* Invalid I2C record */
-@@ -4013,37 +4024,37 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 		/* Merge with other MXM connectors that map to the same physical
- 		 * connector. */
- 		for (j = i + 1;
--			j < connector_tbl->ucNumberOfObjects; j++) {
-+				j < connector_tbl->ucNumberOfObjects; j++) {
- 			ATOM_OBJECT *next_object;
- 			struct graphics_object_id next_object_id;
- 			EXT_DISPLAY_PATH *next_ext_display_path;
- 
- 			next_object = &connector_tbl->asObjects[j];
- 			next_object_id = object_id_from_bios_object_id(
--				le16_to_cpu(next_object->usObjectID));
-+					le16_to_cpu(next_object->usObjectID));
- 
- 			if ((OBJECT_TYPE_CONNECTOR != next_object_id.type) &&
--				(CONNECTOR_ID_MXM == next_object_id.id))
-+					(CONNECTOR_ID_MXM == next_object_id.id))
- 				continue;
- 
- 			next_ext_display_path = get_ext_display_path_entry(
--				&ext_display_connection_info_tbl,
--				le16_to_cpu(next_object->usObjectID));
-+					&ext_display_connection_info_tbl,
-+					le16_to_cpu(next_object->usObjectID));
- 
- 			if (next_ext_display_path == NULL)
- 				return BP_RESULT_FAILURE;
- 
- 			/* Merge if using same connector. */
- 			if ((le16_to_cpu(next_ext_display_path->usDeviceConnector) ==
--				le16_to_cpu(ext_display_path->usDeviceConnector)) &&
--				(le16_to_cpu(ext_display_path->usDeviceConnector) != 0)) {
-+					le16_to_cpu(ext_display_path->usDeviceConnector)) &&
-+					(le16_to_cpu(ext_display_path->usDeviceConnector) != 0)) {
- 				/* Clear duplicate connector from table. */
- 				next_object->usObjectID = cpu_to_le16(0);
- 				add_device_tag_from_ext_display_path(
--					bp,
--					object,
--					ext_display_path,
--					&cached_device_support);
-+						bp,
-+						object,
-+						ext_display_path,
-+						&cached_device_support);
- 			}
- 		}
- 	}
-@@ -4053,7 +4064,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 	 *  display connection info table */
- 
- 	encoder_table_offset = bp->object_info_tbl_offset
--		+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+			+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
- 	encoder_table = GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
- 
- 	for (i = 0; i < encoder_table->ucNumberOfObjects; i++) {
-@@ -4065,24 +4076,24 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 
- 		for (j = 0; j < dst_number; j++) {
- 			object_id = object_id_from_bios_object_id(
--				dst_object_id_list[j]);
-+					dst_object_id_list[j]);
- 
- 			if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
--				(CONNECTOR_ID_MXM != object_id.id))
-+					(CONNECTOR_ID_MXM != object_id.id))
- 				continue;
- 
- 			/* Get the correct connection info table entry based on
- 			 * the enum id. */
- 			ext_display_path =
--				get_ext_display_path_entry(
--					&ext_display_connection_info_tbl,
--					dst_object_id_list[j]);
-+					get_ext_display_path_entry(
-+							&ext_display_connection_info_tbl,
-+							dst_object_id_list[j]);
- 
- 			if (ext_display_path == NULL)
- 				return BP_RESULT_FAILURE;
- 
- 			dst_object_id_list[j] =
--				le16_to_cpu(ext_display_path->usDeviceConnector);
-+					le16_to_cpu(ext_display_path->usDeviceConnector);
- 		}
- 	}
- 
-@@ -4111,7 +4122,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 	uint32_t i = 0;
- 
- 	connector_tbl_offset = bp->object_info_tbl_offset +
--		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+			le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
- 	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
- 
- 	/* Look for MXM connectors to determine whether we need patch the VBIOS
-@@ -4122,7 +4133,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 		object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
- 
- 		if ((OBJECT_TYPE_CONNECTOR == object_id.type) &&
--			(CONNECTOR_ID_MXM == object_id.id)) {
-+				(CONNECTOR_ID_MXM == object_id.id)) {
- 			/* Once we found MXM connector - we can break */
- 			mxm_connector_found = true;
- 			break;
-@@ -4150,20 +4161,20 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 		original_bios = bp->bios;
- 		bp->bios = bp->bios_local_image;
- 		connector_tbl =
--			GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+				GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
- 
- 		/* Step 2: (only if MXM connector found) Patch BIOS image with
- 		 * info from external module */
- 		if (mxm_connector_found &&
--			patch_bios_image_from_ext_display_connection_info(bp) !=
--				BP_RESULT_OK) {
-+				patch_bios_image_from_ext_display_connection_info(bp) !=
-+						BP_RESULT_OK) {
- 			/* Patching the bios image has failed. We will copy
- 			 * again original image provided and afterwards
- 			 * only remove null entries */
- 			dc_service_memmove(
--				bp->bios_local_image,
--				original_bios,
--				bp->bios_size);
-+					bp->bios_local_image,
-+					original_bios,
-+					bp->bios_size);
- 		}
- 
- 		/* Step 3: Compact connector table (remove null entries, valid
-@@ -4171,17 +4182,17 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 		for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
- 			object = &connector_tbl->asObjects[i];
- 			object_id = object_id_from_bios_object_id(
--				le16_to_cpu(object->usObjectID));
-+					le16_to_cpu(object->usObjectID));
- 
- 			if (OBJECT_TYPE_CONNECTOR != object_id.type)
- 				continue;
- 
- 			if (i != connectors_num) {
- 				dc_service_memmove(
--					&connector_tbl->
--					asObjects[connectors_num],
--					object,
--					sizeof(ATOM_OBJECT));
-+						&connector_tbl->
-+						asObjects[connectors_num],
-+						object,
-+						sizeof(ATOM_OBJECT));
- 			}
- 			++connectors_num;
- 		}
-@@ -4199,27 +4210,27 @@ bool dal_bios_parser_is_accelerated_mode(
- {
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	return bp->bios_helper->is_accelerated_mode(
--		bp->ctx);
-+			bp->ctx);
- #else
- 	dal_logger_write(bp->ctx->logger,
--		LOG_MAJOR_BIOS,
--		LOG_MINOR_BIOS_CMD_TABLE,
--		"%s: VBIOS is not supported", __func__);
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: VBIOS is not supported", __func__);
- 	return false;
- #endif
- }
- 
- /**
--* dal_bios_parser_set_scratch_connected
--*
--* @brief
--*  update VBIOS scratch register about connected displays
--*
--* @param
--*  bool - update scratch register or just prepare info to be updated
--*  bool - connection state
--*  const ConnectorDeviceTagInfo* - pointer to device type and enum ID
--*/
-+ * dal_bios_parser_set_scratch_connected
-+ *
-+ * @brief
-+ *  update VBIOS scratch register about connected displays
-+ *
-+ * @param
-+ *  bool - update scratch register or just prepare info to be updated
-+ *  bool - connection state
-+ *  const ConnectorDeviceTagInfo* - pointer to device type and enum ID
-+ */
- void dal_bios_parser_set_scratch_connected(
- 	struct bios_parser *bp,
- 	struct graphics_object_id connector_id,
-@@ -4228,25 +4239,25 @@ void dal_bios_parser_set_scratch_connected(
- {
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_connected(
--		bp->ctx,
--		connector_id, connected, device_tag);
-+			bp->ctx,
-+			connector_id, connected, device_tag);
- #else
- 	dal_logger_write(bp->ctx->logger,
--		LOG_MAJOR_BIOS,
--		LOG_MINOR_BIOS_CMD_TABLE,
--		"%s: VBIOS is not supported", __func__);
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: VBIOS is not supported", __func__);
- #endif
- }
- 
- /**
--* dal_bios_parser_set_scratch_critical_state
--*
--* @brief
--*  update critical state bit in VBIOS scratch register
--*
--* @param
--*  bool - to set or reset state
--*/
-+ * dal_bios_parser_set_scratch_critical_state
-+ *
-+ * @brief
-+ *  update critical state bit in VBIOS scratch register
-+ *
-+ * @param
-+ *  bool - to set or reset state
-+ */
- void dal_bios_parser_set_scratch_critical_state(
- 	struct bios_parser *bp,
- 	bool state)
-@@ -4256,9 +4267,9 @@ void dal_bios_parser_set_scratch_critical_state(
- 			bp->ctx, state);
- #else
- 	dal_logger_write(bp->ctx->logger,
--		LOG_MAJOR_BIOS,
--		LOG_MINOR_BIOS_CMD_TABLE,
--		"%s: VBIOS is not supported", __func__);
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: VBIOS is not supported", __func__);
- #endif
- }
- 
-@@ -4267,27 +4278,27 @@ void dal_bios_parser_set_scratch_acc_mode_change(
- {
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_acc_mode_change(
--		bp->ctx);
-+			bp->ctx);
- #else
- 	dal_logger_write(bp->ctx->logger,
--		LOG_MAJOR_BIOS,
--		LOG_MINOR_BIOS_CMD_TABLE,
--		"%s: VBIOS is not supported", __func__);
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: VBIOS is not supported", __func__);
- #endif
- }
- 
- /**
--* dal_bios_parser_prepare_scratch_active_and_requested
--*
--* @brief
--*  update VBIOS scratch registers about active and requested displays
--*
--* @param
--*  enum controller_id - controller Id
--*  enum signal_type signal - signal type used on display
--*  const struct connector_device_tag_info * - pointer to display type and
--*  enum Id
--*/
-+ * dal_bios_parser_prepare_scratch_active_and_requested
-+ *
-+ * @brief
-+ *  update VBIOS scratch registers about active and requested displays
-+ *
-+ * @param
-+ *  enum controller_id - controller Id
-+ *  enum signal_type signal - signal type used on display
-+ *  const struct connector_device_tag_info * - pointer to display type and
-+ *  enum Id
-+ */
- void dal_bios_parser_prepare_scratch_active_and_requested(
- 	struct bios_parser *bp,
- 	enum controller_id controller_id,
-@@ -4303,9 +4314,9 @@ void dal_bios_parser_prepare_scratch_active_and_requested(
- 			device_tag);
- #else
- 	dal_logger_write(bp->ctx->logger,
--		LOG_MAJOR_BIOS,
--		LOG_MINOR_BIOS_CMD_TABLE,
--		"%s: VBIOS is not supported", __func__);
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: VBIOS is not supported", __func__);
- #endif
- }
- 
-@@ -4314,13 +4325,13 @@ void dal_bios_parser_set_scratch_active_and_requested(
- {
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_active_and_requested(
--		bp->ctx,
--		&bp->vbios_helper_data);
-+			bp->ctx,
-+			&bp->vbios_helper_data);
- #else
- 	dal_logger_write(bp->ctx->logger,
--		LOG_MAJOR_BIOS,
--		LOG_MINOR_BIOS_CMD_TABLE,
--		"%s: VBIOS is not supported", __func__);
-+			LOG_MAJOR_BIOS,
-+			LOG_MINOR_BIOS_CMD_TABLE,
-+			"%s: VBIOS is not supported", __func__);
- #endif
- }
- 
-@@ -4347,29 +4358,29 @@ static enum bp_result get_integrated_info_v8(
- 	uint32_t i;
- 
- 	info_v8 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_8,
--		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+			bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
- 
- 	if (info_v8 != NULL) {
- 		info->boot_up_engine_clock =
--			le32_to_cpu(info_v8->ulBootUpEngineClock) * 10;
-+				le32_to_cpu(info_v8->ulBootUpEngineClock) * 10;
- 		info->dentist_vco_freq =
--			le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
-+				le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
- 		info->boot_up_uma_clock =
--			le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
-+				le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
- 
- 		for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- 			/* Convert [10KHz] into [KHz] */
- 			info->disp_clk_voltage[i].max_supported_clk =
- 					le32_to_cpu(info_v8->sDISPCLK_Voltage[i].
--					ulMaximumSupportedCLK) * 10;
-+							ulMaximumSupportedCLK) * 10;
- 			info->disp_clk_voltage[i].voltage_index =
--				le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
-+					le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
- 		}
- 
- 		info->boot_up_req_display_vector =
--			le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
-+				le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
- 		info->gpu_cap_info =
--			le32_to_cpu(info_v8->ulGPUCapInfo);
-+				le32_to_cpu(info_v8->ulGPUCapInfo);
- 
- 		/*
- 		 * system_config: Bit[0] = 0 : PCIE power gating disabled
-@@ -4394,8 +4405,8 @@ static enum bp_result get_integrated_info_v8(
- 				le32_to_cpu(info_v8->ulNbpStateNClkFreq[0]);
- 		for (i = 1; i < 4; ++i)
- 			info->minimum_n_clk =
--			info->minimum_n_clk < le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]) ?
--			info->minimum_n_clk : le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]);
-+					info->minimum_n_clk < le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]) ?
-+							info->minimum_n_clk : le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]);
- 
- 		info->idle_n_clk = le32_to_cpu(info_v8->ulIdleNClk);
- 		info->ddr_dll_power_up_time =
-@@ -4439,11 +4450,11 @@ static enum bp_result get_integrated_info_v8(
- 		for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
- 			/* Convert [10KHz] into [KHz] */
- 			info->avail_s_clk[i].supported_s_clk =
--				le32_to_cpu(info_v8->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+					le32_to_cpu(info_v8->sAvail_SCLK[i].ulSupportedSCLK) * 10;
- 			info->avail_s_clk[i].voltage_index =
--				le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageIndex);
-+					le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageIndex);
- 			info->avail_s_clk[i].voltage_id =
--				le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageID);
-+					le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageID);
- 		}
- 
- 		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-@@ -4454,22 +4465,22 @@ static enum bp_result get_integrated_info_v8(
- 		for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
- 			info->ext_disp_conn_info.path[i].device_connector_id =
- 					object_id_from_bios_object_id(
--			le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+							le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceConnector));
- 
- 			info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
- 					object_id_from_bios_object_id(
--			le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+							le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
- 
- 			info->ext_disp_conn_info.path[i].device_tag =
--				le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceTag);
-+					le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceTag);
- 			info->ext_disp_conn_info.path[i].device_acpi_enum =
--				le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+					le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
- 			info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
--			info_v8->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+					info_v8->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
- 			info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
--			info_v8->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+					info_v8->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
- 			info->ext_disp_conn_info.path[i].channel_mapping.raw =
--			info_v8->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+					info_v8->sExtDispConnInfo.sPath[i].ucChannelMapping;
- 		}
- 		info->ext_disp_conn_info.checksum =
- 				info_v8->sExtDispConnInfo.ucChecksum;
-@@ -4503,7 +4514,7 @@ static enum bp_result get_integrated_info_v9(
- 	uint32_t i;
- 
- 	info_v9 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_9,
--		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+			bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
- 
- 	if (info_v9 != NULL) {
- 		info->boot_up_engine_clock =
-@@ -4516,9 +4527,9 @@ static enum bp_result get_integrated_info_v9(
- 		for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- 			/* Convert [10KHz] into [KHz] */
- 			info->disp_clk_voltage[i].max_supported_clk =
--				le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
-+					le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
- 			info->disp_clk_voltage[i].voltage_index =
--				le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
-+					le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
- 		}
- 
- 		info->boot_up_req_display_vector =
-@@ -4548,8 +4559,8 @@ static enum bp_result get_integrated_info_v9(
- 				le32_to_cpu(info_v9->ulNbpStateNClkFreq[0]);
- 		for (i = 1; i < 4; ++i)
- 			info->minimum_n_clk =
--			info->minimum_n_clk < le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]) ?
--			info->minimum_n_clk : le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]);
-+					info->minimum_n_clk < le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]) ?
-+							info->minimum_n_clk : le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]);
- 
- 		info->idle_n_clk = le32_to_cpu(info_v9->ulIdleNClk);
- 		info->ddr_dll_power_up_time =
-@@ -4593,11 +4604,11 @@ static enum bp_result get_integrated_info_v9(
- 		for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
- 			/* Convert [10KHz] into [KHz] */
- 			info->avail_s_clk[i].supported_s_clk =
--				le32_to_cpu(info_v9->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+					le32_to_cpu(info_v9->sAvail_SCLK[i].ulSupportedSCLK) * 10;
- 			info->avail_s_clk[i].voltage_index =
--				le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageIndex);
-+					le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageIndex);
- 			info->avail_s_clk[i].voltage_id =
--				le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageID);
-+					le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageID);
- 		}
- 
- 		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-@@ -4608,22 +4619,22 @@ static enum bp_result get_integrated_info_v9(
- 		for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
- 			info->ext_disp_conn_info.path[i].device_connector_id =
- 					object_id_from_bios_object_id(
--			le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+							le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceConnector));
- 
- 			info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
- 					object_id_from_bios_object_id(
--			le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+							le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
- 
- 			info->ext_disp_conn_info.path[i].device_tag =
--				le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceTag);
-+					le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceTag);
- 			info->ext_disp_conn_info.path[i].device_acpi_enum =
--				le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+					le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
- 			info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
--			info_v9->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+					info_v9->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
- 			info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
--			info_v9->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+					info_v9->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
- 			info->ext_disp_conn_info.path[i].channel_mapping.raw =
--			info_v9->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+					info_v9->sExtDispConnInfo.sPath[i].ucChannelMapping;
- 		}
- 		info->ext_disp_conn_info.checksum =
- 				info_v9->sExtDispConnInfo.ucChecksum;
-@@ -4658,9 +4669,9 @@ static enum bp_result construct_integrated_info(
- 	struct atom_data_revision revision;
- 
- 	if (info != NULL &&
--		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo) {
-+			bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo) {
- 		header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
--		bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+				bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
- 
- 		get_atom_data_table_revision(header, &revision);
- 
-@@ -4687,12 +4698,12 @@ static enum bp_result construct_integrated_info(
- 		for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- 			for (j = i; j > 0; --j) {
- 				if (
--				info->disp_clk_voltage[j].max_supported_clk <
--				info->disp_clk_voltage[j-1].max_supported_clk) {
-+						info->disp_clk_voltage[j].max_supported_clk <
-+						info->disp_clk_voltage[j-1].max_supported_clk) {
- 					/* swap j and j - 1*/
- 					temp = info->disp_clk_voltage[j-1];
- 					info->disp_clk_voltage[j-1] =
--						info->disp_clk_voltage[j];
-+							info->disp_clk_voltage[j];
- 					info->disp_clk_voltage[j] = temp;
- 				}
- 			}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index a807ab6..8503eca 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -67,6 +67,7 @@ static void init_compute_memore_engine_pll(struct bios_parser *bp);
- static void init_external_encoder_control(struct bios_parser *bp);
- static void init_enable_disp_power_gating(struct bios_parser *bp);
- static void init_program_clock(struct bios_parser *bp);
-+static void init_set_dce_clock(struct bios_parser *bp);
- 
- void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
- {
-@@ -89,22 +90,23 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
- 	init_compute_memore_engine_pll(bp);
- 	init_external_encoder_control(bp);
- 	init_enable_disp_power_gating(bp);
-+	init_set_dce_clock(bp);
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  D I G E N C O D E R C O N T R O L
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  D I G E N C O D E R C O N T R O L
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- static enum bp_result encoder_control_digx_v3(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
- 
- static enum bp_result encoder_control_digx_v4(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
- static void init_encoder_control_dig_v1(struct bios_parser *bp);
- 
- static void init_dig_encoder_control(struct bios_parser *bp)
-@@ -126,14 +128,14 @@ static void init_dig_encoder_control(struct bios_parser *bp)
- }
- 
- static enum bp_result encoder_control_dig_v1(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
- static enum bp_result encoder_control_dig1_v1(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
- static enum bp_result encoder_control_dig2_v1(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
- 
- static void init_encoder_control_dig_v1(struct bios_parser *bp)
- {
-@@ -153,8 +155,8 @@ static void init_encoder_control_dig_v1(struct bios_parser *bp)
- }
- 
- static enum bp_result encoder_control_dig_v1(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-@@ -180,8 +182,8 @@ static enum bp_result encoder_control_dig_v1(
- }
- 
- static enum bp_result encoder_control_dig1_v1(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-@@ -195,8 +197,8 @@ static enum bp_result encoder_control_dig1_v1(
- }
- 
- static enum bp_result encoder_control_dig2_v1(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-@@ -210,8 +212,8 @@ static enum bp_result encoder_control_dig2_v1(
- }
- 
- static enum bp_result encoder_control_digx_v3(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DIG_ENCODER_CONTROL_PARAMETERS_V3 params = {0};
-@@ -227,9 +229,9 @@ static enum bp_result encoder_control_digx_v3(
- 	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
- 	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 	params.ucEncoderMode =
--		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--				cntl->signal,
--				cntl->enable_dp_audio);
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio);
- 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
- 
- 	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-@@ -257,8 +259,8 @@ static enum bp_result encoder_control_digx_v3(
- }
- 
- static enum bp_result encoder_control_digx_v4(
--		struct bios_parser *bp,
--		struct bp_encoder_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DIG_ENCODER_CONTROL_PARAMETERS_V4 params = {0};
-@@ -275,9 +277,9 @@ static enum bp_result encoder_control_digx_v4(
- 	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
- 	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 	params.ucEncoderMode =
--		(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
--				cntl->signal,
--				cntl->enable_dp_audio));
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio));
- 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
- 
- 	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-@@ -305,16 +307,16 @@ static enum bp_result encoder_control_digx_v4(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                 DVO ENCODER CONTROL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                 DVO ENCODER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result dvo_encoder_control_v3(
--		struct bios_parser *bp,
--		struct bp_dvo_encoder_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_dvo_encoder_control *cntl);
- 
- static void init_dvo_encoder_control(struct bios_parser *bp)
- {
-@@ -329,8 +331,8 @@ static void init_dvo_encoder_control(struct bios_parser *bp)
- }
- 
- static enum bp_result dvo_encoder_control_v3(
--		struct bios_parser *bp,
--		struct bp_dvo_encoder_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_dvo_encoder_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DVO_ENCODER_CONTROL_PARAMETERS_V3 params;
-@@ -364,25 +366,28 @@ static enum bp_result dvo_encoder_control_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  TRANSMITTER CONTROL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  TRANSMITTER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result transmitter_control_v2(
--		struct bios_parser *bp,
--		struct bp_transmitter_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
- static enum bp_result transmitter_control_v3(
--		struct bios_parser *bp,
--		struct bp_transmitter_control *cntl);
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
- static enum bp_result transmitter_control_v4(
- 	struct bios_parser *bp,
- 	struct bp_transmitter_control *cntl);
- static enum bp_result transmitter_control_v1_5(
- 	struct bios_parser *bp,
- 	struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v1_6(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
- 
- static void init_transmitter_control(struct bios_parser *bp)
- {
-@@ -405,6 +410,9 @@ static void init_transmitter_control(struct bios_parser *bp)
- 	case 5:
- 		bp->cmd_tbl.transmitter_control = transmitter_control_v1_5;
- 		break;
-+	case 6:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
-+		break;
- 	default:
- 		bp->cmd_tbl.transmitter_control = NULL;
- 		break;
-@@ -412,8 +420,8 @@ static void init_transmitter_control(struct bios_parser *bp)
- }
- 
- static enum bp_result transmitter_control_v2(
--		struct bios_parser *bp,
--		struct bp_transmitter_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 params;
-@@ -449,7 +457,7 @@ static enum bp_result transmitter_control_v2(
- 
- 		/* connector object id */
- 		params.usInitInfo =
--			cpu_to_le16((uint8_t)cntl->connector_obj_id.id);
-+				cpu_to_le16((uint8_t)cntl->connector_obj_id.id);
- 		break;
- 	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
- 		/* votage swing and pre-emphsis */
-@@ -471,13 +479,13 @@ static enum bp_result transmitter_control_v2(
- 			 * We need to convert from KHz units into 20KHz units
- 			 */
- 			params.usPixelClock =
--				cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
- 		} else
- 			/* link rate, half for dual link
- 			 * We need to convert from KHz units into 10KHz units
- 			 */
- 			params.usPixelClock =
--				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 		break;
- 	}
- 
-@@ -520,8 +528,8 @@ static enum bp_result transmitter_control_v2(
- 	 * =3 reserved
- 	 */
- 	params.acConfig.ucTransmitterSel =
--		(uint8_t)bp->cmd_helper->transmitter_bp_to_atom(
--			cntl->transmitter);
-+			(uint8_t)bp->cmd_helper->transmitter_bp_to_atom(
-+					cntl->transmitter);
- 
- 	params.ucAction = (uint8_t)cntl->action;
- 
-@@ -532,17 +540,17 @@ static enum bp_result transmitter_control_v2(
- }
- 
- static enum bp_result transmitter_control_v3(
--		struct bios_parser *bp,
--		struct bp_transmitter_control *cntl)
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 params;
- 	uint32_t pll_id;
- 	enum connector_id conn_id =
--		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 	bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
--			|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
-+					|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
- 
- 	dc_service_memset(&params, 0, sizeof(params));
- 
-@@ -577,7 +585,7 @@ static enum bp_result transmitter_control_v3(
- 
- 		/* connector object id */
- 		params.usInitInfo =
--			cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+				cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
- 		break;
- 	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
- 		/* votage swing and pre-emphsis */
-@@ -608,26 +616,26 @@ static enum bp_result transmitter_control_v3(
- 			 * We need to convert from KHz units into 20KHz units
- 			 */
- 			params.usPixelClock =
--				cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
- 		} else {
- 			/* link rate, half for dual link
- 			 * We need to convert from KHz units into 10KHz units
- 			 */
- 			params.usPixelClock =
--				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 			if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 				switch (cntl->color_depth) {
- 				case COLOR_DEPTH_101010:
- 					params.usPixelClock =
--						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
-+							cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
- 					break;
- 				case COLOR_DEPTH_121212:
- 					params.usPixelClock =
--						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
-+							cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
- 					break;
- 				case COLOR_DEPTH_161616:
- 					params.usPixelClock =
--						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
-+							cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
- 					break;
- 				default:
- 					break;
-@@ -643,8 +651,8 @@ static enum bp_result transmitter_control_v3(
- 	params.acConfig.fCoherentMode = cntl->coherent;
- 
- 	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
--			|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
--			|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
- 		/* Bit2: Transmitter Link selection
- 		 * =0 when bit0=0, single link A/C/E, when bit0=1,
- 		 * master link A/C/E
-@@ -668,7 +676,7 @@ static enum bp_result transmitter_control_v3(
- 	 * =3 reserved
- 	 */
- 	params.acConfig.ucTransmitterSel =
--		(uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);
-+			(uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);
- 
- 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
- 
-@@ -690,7 +698,7 @@ static enum bp_result transmitter_control_v4(
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 params;
- 	uint32_t ref_clk_src_id;
- 	enum connector_id conn_id =
--		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 
- 	dc_service_memset(&params, 0, sizeof(params));
-@@ -715,7 +723,7 @@ static enum bp_result transmitter_control_v4(
- 	case TRANSMITTER_CONTROL_INIT:
- 	{
- 		if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
--			(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+				(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
- 			/* on INIT this bit should be set according to the
- 			 * phisycal connector
- 			 * Bit0: dual link connector flag
-@@ -726,7 +734,7 @@ static enum bp_result transmitter_control_v4(
- 
- 		/* connector object id */
- 		params.usInitInfo =
--			cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+				cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
- 	}
- 	break;
- 	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-@@ -736,7 +744,7 @@ static enum bp_result transmitter_control_v4(
- 		break;
- 	default:
- 		if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
--			(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+				(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
- 			/* on ENABLE/DISABLE this bit should be set according to
- 			 * actual timing (number of lanes)
- 			 * Bit0: dual link connector flag
-@@ -751,27 +759,27 @@ static enum bp_result transmitter_control_v4(
- 			 * We need to convert from KHz units into 20KHz units
- 			 */
- 			params.usPixelClock =
--				cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
- 		else {
- 			/* link rate, half for dual link
- 			 * We need to convert from KHz units into 10KHz units
- 			 */
- 			params.usPixelClock =
--				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 
- 			if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 				switch (cntl->color_depth) {
- 				case COLOR_DEPTH_101010:
- 					params.usPixelClock =
--						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
-+							cpu_to_le16((le16_to_cpu(params.usPixelClock) * 30) / 24);
- 					break;
- 				case COLOR_DEPTH_121212:
- 					params.usPixelClock =
--						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
-+							cpu_to_le16((le16_to_cpu(params.usPixelClock) * 36) / 24);
- 					break;
- 				case COLOR_DEPTH_161616:
- 					params.usPixelClock =
--						cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
-+							cpu_to_le16((le16_to_cpu(params.usPixelClock) * 48) / 24);
- 					break;
- 				default:
- 					break;
-@@ -878,8 +886,8 @@ static enum bp_result transmitter_control_v1_5(
- 			break;
- 		}
- 		break;
--	default:
--		break;
-+		default:
-+			break;
- 	}
- 
- 	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-@@ -888,13 +896,76 @@ static enum bp_result transmitter_control_v1_5(
- 	return result;
- }
- 
-+static enum bp_result transmitter_control_v1_6(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 params;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
-+	params.ucAction = (uint8_t)cntl->action;
-+
-+	if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
-+		params.ucDPLaneSet = (uint8_t)cntl->lane_settings;
-+	else
-+		params.ucDigMode = cmd->signal_type_to_atom_dig_mode(cntl->signal);
-+
-+	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+	params.ucHPDSel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
-+	params.ucDigEncoderSel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
-+	params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
-+	params.ulSymClock = cntl->pixel_clock/10;
-+
-+	/*
-+	 * In SI/TN case, caller have to set usPixelClock as following:
-+	 * DP mode: usPixelClock = DP_LINK_CLOCK/10
-+	 * (DP_LINK_CLOCK = 1.62GHz, 2.7GHz, 5.4GHz)
-+	 * DVI single link mode: usPixelClock = pixel clock
-+	 * DVI dual link mode: usPixelClock = pixel clock
-+	 * HDMI mode: usPixelClock = pixel clock * deep_color_ratio
-+	 * (=1: 8bpp, =1.25: 10bpp, =1.5:12bpp, =2: 16bpp)
-+	 * LVDS mode: usPixelClock = pixel clock
-+	 */
-+	switch (cntl->signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.ulSymClock =
-+				cpu_to_le16((le16_to_cpu(params.ulSymClock) * 30) / 24);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.ulSymClock =
-+				cpu_to_le16((le16_to_cpu(params.ulSymClock) * 36) / 24);
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.ulSymClock =
-+				cpu_to_le16((le16_to_cpu(params.ulSymClock) * 48) / 24);
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+		default:
-+			break;
-+	}
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+#endif
-+	return result;
-+}
-+
- /*******************************************************************************
--********************************************************************************
--**
--**                  SET PIXEL CLOCK
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  SET PIXEL CLOCK
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result set_pixel_clock_v3(
- 	struct bios_parser *bp,
-@@ -905,6 +976,9 @@ static enum bp_result set_pixel_clock_v5(
- static enum bp_result set_pixel_clock_v6(
- 	struct bios_parser *bp,
- 	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v7(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
- 
- static void init_set_pixel_clock(struct bios_parser *bp)
- {
-@@ -918,6 +992,9 @@ static void init_set_pixel_clock(struct bios_parser *bp)
- 	case 6:
- 		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v6;
- 		break;
-+	case 7:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
-+		break;
- 	default:
- 		bp->cmd_tbl.set_pixel_clock = NULL;
- 		break;
-@@ -942,26 +1019,26 @@ static enum bp_result set_pixel_clock_v3(
- 		return BP_RESULT_BADINPUT;
- 
- 	allocation.sPCLKInput.usRefDiv =
--		cpu_to_le16((uint16_t)bp_params->reference_divider);
-+			cpu_to_le16((uint16_t)bp_params->reference_divider);
- 	allocation.sPCLKInput.usFbDiv =
--		cpu_to_le16((uint16_t)bp_params->feedback_divider);
-+			cpu_to_le16((uint16_t)bp_params->feedback_divider);
- 	allocation.sPCLKInput.ucFracFbDiv =
--		(uint8_t)bp_params->fractional_feedback_divider;
-+			(uint8_t)bp_params->fractional_feedback_divider;
- 	allocation.sPCLKInput.ucPostDiv =
--		(uint8_t)bp_params->pixel_clock_post_divider;
-+			(uint8_t)bp_params->pixel_clock_post_divider;
- 
- 	/* We need to convert from KHz units into 10KHz units */
- 	allocation.sPCLKInput.usPixelClock =
--		cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+			cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
- 
- 	params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
- 	params->ucTransmitterId =
--		bp->cmd_helper->encoder_id_to_atom(
--			dal_graphics_object_id_get_encoder_id(
--				bp_params->encoder_object_id));
-+			bp->cmd_helper->encoder_id_to_atom(
-+					dal_graphics_object_id_get_encoder_id(
-+							bp_params->encoder_object_id));
- 	params->ucEncoderMode =
--		(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
--			bp_params->signal_type, false));
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					bp_params->signal_type, false));
- 
- 	if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
- 		params->ucMiscInfo |= PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-@@ -1008,37 +1085,37 @@ static enum bp_result set_pixel_clock_v5(
- 	dc_service_memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
--		&& bp->cmd_helper->controller_id_to_atom(
--			bp_params->controller_id, &controller_id)) {
-+			&& bp->cmd_helper->controller_id_to_atom(
-+					bp_params->controller_id, &controller_id)) {
- 		clk.sPCLKInput.ucCRTC = controller_id;
- 		clk.sPCLKInput.ucPpll = (uint8_t)pll_id;
- 		clk.sPCLKInput.ucRefDiv =
--			(uint8_t)(bp_params->reference_divider);
-+				(uint8_t)(bp_params->reference_divider);
- 		clk.sPCLKInput.usFbDiv =
--			cpu_to_le16((uint16_t)(bp_params->feedback_divider));
-+				cpu_to_le16((uint16_t)(bp_params->feedback_divider));
- 		clk.sPCLKInput.ulFbDivDecFrac =
--			cpu_to_le32(bp_params->fractional_feedback_divider);
-+				cpu_to_le32(bp_params->fractional_feedback_divider);
- 		clk.sPCLKInput.ucPostDiv =
--			(uint8_t)(bp_params->pixel_clock_post_divider);
-+				(uint8_t)(bp_params->pixel_clock_post_divider);
- 		clk.sPCLKInput.ucTransmitterID =
--			bp->cmd_helper->encoder_id_to_atom(
--				dal_graphics_object_id_get_encoder_id(
--					bp_params->encoder_object_id));
-+				bp->cmd_helper->encoder_id_to_atom(
-+						dal_graphics_object_id_get_encoder_id(
-+								bp_params->encoder_object_id));
- 		clk.sPCLKInput.ucEncoderMode =
--			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--				bp_params->signal_type, false);
-+				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+						bp_params->signal_type, false);
- 
- 		/* We need to convert from KHz units into 10KHz units */
- 		clk.sPCLKInput.usPixelClock =
--			cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+				cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
- 
- 		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
- 			clk.sPCLKInput.ucMiscInfo |=
--				PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+					PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
- 
- 		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
- 			clk.sPCLKInput.ucMiscInfo |=
--				PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+					PIXEL_CLOCK_MISC_REF_DIV_SRC;
- 
- 		/* clkV5.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0: 24bpp
- 		 * =1:30bpp, =2:32bpp
-@@ -1065,8 +1142,8 @@ static enum bp_result set_pixel_clock_v6(
- 	dc_service_memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
--		&& bp->cmd_helper->controller_id_to_atom(
--			bp_params->controller_id, &controller_id)) {
-+			&& bp->cmd_helper->controller_id_to_atom(
-+					bp_params->controller_id, &controller_id)) {
- 		/* Note: VBIOS still wants to use ucCRTC name which is now
- 		 * 1 byte in ULONG
- 		 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-@@ -1089,33 +1166,33 @@ static enum bp_result set_pixel_clock_v6(
- 		clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;
- 		clk.sPCLKInput.ucPpll = (uint8_t) pll_id;
- 		clk.sPCLKInput.ucRefDiv =
--			(uint8_t) bp_params->reference_divider;
-+				(uint8_t) bp_params->reference_divider;
- 		clk.sPCLKInput.usFbDiv =
--			cpu_to_le16((uint16_t) bp_params->feedback_divider);
-+				cpu_to_le16((uint16_t) bp_params->feedback_divider);
- 		clk.sPCLKInput.ulFbDivDecFrac =
--			cpu_to_le32(bp_params->fractional_feedback_divider);
-+				cpu_to_le32(bp_params->fractional_feedback_divider);
- 		clk.sPCLKInput.ucPostDiv =
--			(uint8_t) bp_params->pixel_clock_post_divider;
-+				(uint8_t) bp_params->pixel_clock_post_divider;
- 		clk.sPCLKInput.ucTransmitterID =
--			bp->cmd_helper->encoder_id_to_atom(
--				dal_graphics_object_id_get_encoder_id(
--					bp_params->encoder_object_id));
-+				bp->cmd_helper->encoder_id_to_atom(
-+						dal_graphics_object_id_get_encoder_id(
-+								bp_params->encoder_object_id));
- 		clk.sPCLKInput.ucEncoderMode =
--			(uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
--				bp_params->signal_type, false);
-+				(uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
-+						bp_params->signal_type, false);
- 
- 		/* We need to convert from KHz units into 10KHz units */
- 		clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
--			cpu_to_le32(bp_params->target_pixel_clock / 10);
-+				cpu_to_le32(bp_params->target_pixel_clock / 10);
- 
- 		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
- 			clk.sPCLKInput.ucMiscInfo |=
--				PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL;
-+					PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL;
- 		}
- 
- 		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) {
- 			clk.sPCLKInput.ucMiscInfo |=
--				PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
-+					PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
- 		}
- 
- 		/* clkV6.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0:
-@@ -1131,13 +1208,84 @@ static enum bp_result set_pixel_clock_v6(
- 	return result;
- }
- 
-+static enum bp_result set_pixel_clock_v7(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+	PIXEL_CLOCK_PARAMETERS_V7 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	dc_service_memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+			&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
-+		/* Note: VBIOS still wants to use ucCRTC name which is now
-+		 * 1 byte in ULONG
-+		 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-+		 *{
-+		 * target the pixel clock to drive the CRTC timing.
-+		 * ULONG ulPixelClock:24;
-+		 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
-+		 * previous version.
-+		 * ATOM_CRTC1~6, indicate the CRTC controller to
-+		 * ULONG ucCRTC:8;
-+		 * drive the pixel clock. not used for DCPLL case.
-+		 *}CRTC_PIXEL_CLOCK_FREQ;
-+		 *union
-+		 *{
-+		 * pixel clock and CRTC id frequency
-+		 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
-+		 * ULONG ulDispEngClkFreq; dispclk frequency
-+		 *};
-+		 */
-+		clk.ucCRTC = controller_id;
-+		clk.ucPpll = (uint8_t) pll_id;
-+		clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
-+		clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+		clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
-+
-+		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC;
-+
-+		if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
-+
-+		if (bp_params->flags.SUPPORT_YUV_420)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
-+
-+		if (bp_params->flags.SET_XTALIN_REF_SRC)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
-+
-+		if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
-+
-+		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
-+
-+		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+#endif
-+	return result;
-+}
-+
- /*******************************************************************************
--********************************************************************************
--**
--**                  ENABLE PIXEL CLOCK SS
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  ENABLE PIXEL CLOCK SS
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- static enum bp_result enable_spread_spectrum_on_ppll_v1(
- 	struct bios_parser *bp,
- 	struct bp_spread_spectrum_parameters *bp_params,
-@@ -1156,15 +1304,15 @@ static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp)
- 	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) {
- 	case 1:
- 		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
--			enable_spread_spectrum_on_ppll_v1;
-+				enable_spread_spectrum_on_ppll_v1;
- 		break;
- 	case 2:
- 		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
--			enable_spread_spectrum_on_ppll_v2;
-+				enable_spread_spectrum_on_ppll_v2;
- 		break;
- 	case 3:
- 		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
--			enable_spread_spectrum_on_ppll_v3;
-+				enable_spread_spectrum_on_ppll_v3;
- 		break;
- 	default:
- 		bp->cmd_tbl.enable_spread_spectrum_on_ppll = NULL;
-@@ -1188,14 +1336,14 @@ static enum bp_result enable_spread_spectrum_on_ppll_v1(
- 		params.ucEnable = ATOM_DISABLE;
- 
- 	params.usSpreadSpectrumPercentage =
--		cpu_to_le16((uint16_t)bp_params->percentage);
-+			cpu_to_le16((uint16_t)bp_params->percentage);
- 	params.ucSpreadSpectrumStep =
--		(uint8_t)bp_params->ver1.step;
-+			(uint8_t)bp_params->ver1.step;
- 	params.ucSpreadSpectrumDelay =
--		(uint8_t)bp_params->ver1.delay;
-+			(uint8_t)bp_params->ver1.delay;
- 	/* convert back to unit of 10KHz */
- 	params.ucSpreadSpectrumRange =
--		(uint8_t)(bp_params->ver1.range / 10000);
-+			(uint8_t)(bp_params->ver1.range / 10000);
- 
- 	if (bp_params->flags.EXTERNAL_SS)
- 		params.ucSpreadSpectrumType |= ATOM_EXTERNAL_SS_MASK;
-@@ -1237,28 +1385,28 @@ static enum bp_result enable_spread_spectrum_on_ppll_v2(
- 		params.ucEnable = ATOM_ENABLE;
- 
- 		params.usSpreadSpectrumPercentage =
--			cpu_to_le16((uint16_t)(bp_params->percentage));
-+				cpu_to_le16((uint16_t)(bp_params->percentage));
- 		params.usSpreadSpectrumStep =
--			cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+				cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
- 
- 		if (bp_params->flags.EXTERNAL_SS)
- 			params.ucSpreadSpectrumType |=
--				ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD;
-+					ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD;
- 
- 		if (bp_params->flags.CENTER_SPREAD)
- 			params.ucSpreadSpectrumType |=
--				ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD;
-+					ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD;
- 
- 		/* Both amounts need to be left shifted first before bit
- 		 * comparison. Otherwise, the result will always be zero here
- 		 */
- 		params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
--			((bp_params->ds.feedback_amount <<
--				ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT) &
--				ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK) |
--			((bp_params->ds.nfrac_amount <<
--				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
--				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK)));
-+				((bp_params->ds.feedback_amount <<
-+						ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT) &
-+						ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK) |
-+						((bp_params->ds.nfrac_amount <<
-+								ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
-+								ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK)));
- 	} else
- 		params.ucEnable = ATOM_DISABLE;
- 
-@@ -1307,27 +1455,27 @@ static enum bp_result enable_spread_spectrum_on_ppll_v3(
- 		params.ucEnable = ATOM_ENABLE;
- 
- 		params.usSpreadSpectrumAmountFrac =
--			cpu_to_le16((uint16_t)(bp_params->ds_frac_amount));
-+				cpu_to_le16((uint16_t)(bp_params->ds_frac_amount));
- 		params.usSpreadSpectrumStep =
--			cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+				cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
- 
- 		if (bp_params->flags.EXTERNAL_SS)
- 			params.ucSpreadSpectrumType |=
--				ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD;
-+					ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD;
- 		if (bp_params->flags.CENTER_SPREAD)
- 			params.ucSpreadSpectrumType |=
--				ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD;
-+					ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD;
- 
- 		/* Both amounts need to be left shifted first before bit
- 		 * comparison. Otherwise, the result will always be zero here
- 		 */
- 		params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
--			((bp_params->ds.feedback_amount <<
--				ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT) &
--				ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK) |
--			((bp_params->ds.nfrac_amount <<
--				ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT) &
--				ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK)));
-+				((bp_params->ds.feedback_amount <<
-+						ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT) &
-+						ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK) |
-+						((bp_params->ds.nfrac_amount <<
-+								ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT) &
-+								ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK)));
- 	} else
- 		params.ucEnable = ATOM_DISABLE;
- 
-@@ -1338,12 +1486,12 @@ static enum bp_result enable_spread_spectrum_on_ppll_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  ADJUST DISPLAY PLL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  ADJUST DISPLAY PLL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result adjust_display_pll_v2(
- 	struct bios_parser *bp,
-@@ -1372,7 +1520,7 @@ static bool adjust_display_pll_bug_patch(ADJUST_DISPLAY_PLL_PARAMETERS *params)
- 	/* vbios bug: pixel clock should not be doubled for DVO with 24bit
- 	 * interface */
- 	if ((params->ucTransmitterID == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
--		&& (params->ucDVOConfig == DVO_ENCODER_CONFIG_24BIT))
-+			&& (params->ucDVOConfig == DVO_ENCODER_CONFIG_24BIT))
- 		/* the current pixel clock is good. no adjustment is required */
- 		return true;
- 	return false;
-@@ -1391,16 +1539,16 @@ static enum bp_result adjust_display_pll_v2(
- 
- 	params.usPixelClock = cpu_to_le16((uint16_t)(pixel_clock_10KHz_in));
- 	params.ucTransmitterID =
--		bp->cmd_helper->encoder_id_to_atom(
--			dal_graphics_object_id_get_encoder_id(
--				bp_params->encoder_object_id));
-+			bp->cmd_helper->encoder_id_to_atom(
-+					dal_graphics_object_id_get_encoder_id(
-+							bp_params->encoder_object_id));
- 	params.ucEncodeMode =
--		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--			bp_params->signal_type, false);
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					bp_params->signal_type, false);
- 	params.ucDVOConfig = (uint8_t)(bp_params->dvo_config);
- 
- 	if (adjust_display_pll_bug_patch(&params)
--		|| EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
-+			|| EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
- 		/* Convert output pixel clock back 10KHz-->KHz: multiply
- 		 * original pixel clock in KHz by ratio
- 		 * [output pxlClk/input pxlClk] */
-@@ -1409,8 +1557,8 @@ static enum bp_result adjust_display_pll_v2(
- 		uint64_t pixel_clock = (uint64_t)bp_params->pixel_clock;
- 
- 		bp_params->adjusted_pixel_clock =
--			div_u64(pixel_clock * pixel_clock_10KHz_out,
--				pixel_clock_10KHz_in);
-+				div_u64(pixel_clock * pixel_clock_10KHz_out,
-+						pixel_clock_10KHz_in);
- 		result = BP_RESULT_OK;
- 	}
- 
-@@ -1431,31 +1579,31 @@ static enum bp_result adjust_display_pll_v3(
- 	 * output pixel clock back 10KHz-->KHz */
- 	params.sInput.usPixelClock = cpu_to_le16((uint16_t)pixel_clk_10_kHz_in);
- 	params.sInput.ucTransmitterID =
--		bp->cmd_helper->encoder_id_to_atom(
--			dal_graphics_object_id_get_encoder_id(
--				bp_params->encoder_object_id));
-+			bp->cmd_helper->encoder_id_to_atom(
-+					dal_graphics_object_id_get_encoder_id(
-+							bp_params->encoder_object_id));
- 	params.sInput.ucEncodeMode =
--		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--			bp_params->signal_type, false);
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					bp_params->signal_type, false);
- 
- 	if (DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT ==
--		bp_params->display_pll_config)
-+			bp_params->display_pll_config)
- 		params.sInput.ucDispPllConfig =
--			DISPPLL_CONFIG_DVO_DDR_SPEED |
--			DISPPLL_CONFIG_DVO_LOW12BIT;
-+				DISPPLL_CONFIG_DVO_DDR_SPEED |
-+				DISPPLL_CONFIG_DVO_LOW12BIT;
- 	else if (DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT ==
--		bp_params->display_pll_config)
-+			bp_params->display_pll_config)
- 		params.sInput.ucDispPllConfig =
--			DISPPLL_CONFIG_DVO_DDR_SPEED |
--			DISPPLL_CONFIG_DVO_UPPER12BIT;
-+				DISPPLL_CONFIG_DVO_DDR_SPEED |
-+				DISPPLL_CONFIG_DVO_UPPER12BIT;
- 	else if (DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT ==
--		bp_params->display_pll_config)
-+			bp_params->display_pll_config)
- 		params.sInput.ucDispPllConfig =
--			DISPPLL_CONFIG_DVO_DDR_SPEED | DISPPLL_CONFIG_DVO_24BIT;
-+				DISPPLL_CONFIG_DVO_DDR_SPEED | DISPPLL_CONFIG_DVO_24BIT;
- 	else
- 		/* this does not mean anything here */
- 		params.sInput.ucDispPllConfig =
--			(uint8_t)(bp_params->display_pll_config);
-+				(uint8_t)(bp_params->display_pll_config);
- 
- 	if (bp_params->ss_enable == true)
- 		params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
-@@ -1468,13 +1616,13 @@ static enum bp_result adjust_display_pll_v3(
- 		 * original pixel clock in KHz by ratio
- 		 * [output pxlClk/input pxlClk] */
- 		uint64_t pixel_clk_10_khz_out =
--			(uint64_t)le32_to_cpu(params.sOutput.ulDispPllFreq);
-+				(uint64_t)le32_to_cpu(params.sOutput.ulDispPllFreq);
- 		uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
- 
- 		if (pixel_clk_10_kHz_in != 0) {
- 			bp_params->adjusted_pixel_clock =
--				div_u64(pixel_clk * pixel_clk_10_khz_out,
--					pixel_clk_10_kHz_in);
-+					div_u64(pixel_clk * pixel_clk_10_khz_out,
-+							pixel_clk_10_kHz_in);
- 		} else {
- 			bp_params->adjusted_pixel_clock = 0;
- 			BREAK_TO_DEBUGGER();
-@@ -1490,12 +1638,12 @@ static enum bp_result adjust_display_pll_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  DAC ENCODER CONTROL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  DAC ENCODER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result dac1_encoder_control_v1(
- 	struct bios_parser *bp,
-@@ -1589,12 +1737,12 @@ static enum bp_result dac2_encoder_control_v1(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  DAC OUTPUT CONTROL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  DAC OUTPUT CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- static enum bp_result dac1_output_control_v1(
- 	struct bios_parser *bp,
- 	bool enable);
-@@ -1623,7 +1771,7 @@ static void init_dac_output_control(struct bios_parser *bp)
- }
- 
- static enum bp_result dac1_output_control_v1(
--		struct bios_parser *bp, bool enable)
-+	struct bios_parser *bp, bool enable)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-@@ -1640,7 +1788,7 @@ static enum bp_result dac1_output_control_v1(
- }
- 
- static enum bp_result dac2_output_control_v1(
--		struct bios_parser *bp, bool enable)
-+	struct bios_parser *bp, bool enable)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-@@ -1657,12 +1805,12 @@ static enum bp_result dac2_output_control_v1(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  DAC LOAD DETECTION
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  DAC LOAD DETECTION
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum signal_type dac_load_detection_v3(
- 	struct bios_parser *bp,
-@@ -1711,8 +1859,8 @@ static enum signal_type dac_load_detection_v3(
- 			break;
- 		}
- 		break;
--	default:
--		return signal;
-+		default:
-+			return signal;
- 	}
- 
- 	/* set the encoder to detect on */
-@@ -1736,10 +1884,10 @@ static enum signal_type dac_load_detection_v3(
- 		return signal;
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
- 	signal = bp->bios_helper->detect_sink(
--		bp->ctx,
--		encoder,
--		connector,
--		display_signal);
-+			bp->ctx,
-+			encoder,
-+			connector,
-+			display_signal);
- #else
- 	BREAK_TO_DEBUGGER(); /* VBios is needed */
- #endif
-@@ -1748,17 +1896,17 @@ static enum signal_type dac_load_detection_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                 BLANK CRTC
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                 BLANK CRTC
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result blank_crtc_v1(
--		struct bios_parser *bp,
--		struct bp_blank_crtc_parameters *bp_params,
--		bool blank);
-+	struct bios_parser *bp,
-+	struct bp_blank_crtc_parameters *bp_params,
-+	bool blank);
- 
- static void init_blank_crtc(struct bios_parser *bp)
- {
-@@ -1773,9 +1921,9 @@ static void init_blank_crtc(struct bios_parser *bp)
- }
- 
- static enum bp_result blank_crtc_v1(
--		struct bios_parser *bp,
--		struct bp_blank_crtc_parameters *bp_params,
--		bool blank)
-+	struct bios_parser *bp,
-+	struct bp_blank_crtc_parameters *bp_params,
-+	bool blank)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	BLANK_CRTC_PARAMETERS params = {0};
-@@ -1790,11 +1938,11 @@ static enum bp_result blank_crtc_v1(
- 		else
- 			params.ucBlanking = ATOM_BLANKING_OFF;
- 		params.usBlackColorRCr =
--			cpu_to_le16((uint16_t)bp_params->black_color_rcr);
-+				cpu_to_le16((uint16_t)bp_params->black_color_rcr);
- 		params.usBlackColorGY =
--			cpu_to_le16((uint16_t)bp_params->black_color_gy);
-+				cpu_to_le16((uint16_t)bp_params->black_color_gy);
- 		params.usBlackColorBCb =
--			cpu_to_le16((uint16_t)bp_params->black_color_bcb);
-+				cpu_to_le16((uint16_t)bp_params->black_color_bcb);
- 
- 		if (EXEC_BIOS_CMD_TABLE(BlankCRTC, params))
- 			result = BP_RESULT_OK;
-@@ -1808,29 +1956,29 @@ static enum bp_result blank_crtc_v1(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  SET CRTC TIMING
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  SET CRTC TIMING
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result set_crtc_using_dtd_timing_v3(
--		struct bios_parser *bp,
--		struct bp_hw_crtc_timing_parameters *bp_params);
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params);
- static enum bp_result set_crtc_timing_v1(
--		struct bios_parser *bp,
--		struct bp_hw_crtc_timing_parameters *bp_params);
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params);
- 
- static void init_set_crtc_timing(struct bios_parser *bp)
- {
- 	uint32_t dtd_version =
--		BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_UsingDTDTiming);
-+			BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_UsingDTDTiming);
- 	if (dtd_version > 2)
- 		switch (dtd_version) {
- 		case 3:
- 			bp->cmd_tbl.set_crtc_timing =
--				set_crtc_using_dtd_timing_v3;
-+					set_crtc_using_dtd_timing_v3;
- 			break;
- 		default:
- 			bp->cmd_tbl.set_crtc_timing = NULL;
-@@ -1848,15 +1996,15 @@ static void init_set_crtc_timing(struct bios_parser *bp)
- }
- 
- static enum bp_result set_crtc_timing_v1(
--		struct bios_parser *bp,
--		struct bp_hw_crtc_timing_parameters *bp_params)
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION params = {0};
- 	uint8_t atom_controller_id;
- 
- 	if (bp->cmd_helper->controller_id_to_atom(
--		bp_params->controller_id, &atom_controller_id))
-+			bp_params->controller_id, &atom_controller_id))
- 		params.ucCRTC = atom_controller_id;
- 
- 	params.usH_Total = cpu_to_le16((uint16_t)(bp_params->h_total));
-@@ -1884,15 +2032,15 @@ static enum bp_result set_crtc_timing_v1(
- 
- 	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
- 
- 	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
- 
- 	if (bp_params->flags.INTERLACE) {
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
- 
- 		/* original DAL code has this condition to apply tis for
- 		 * non-TV/CV only due to complex MV testing for possible
-@@ -1908,12 +2056,12 @@ static enum bp_result set_crtc_timing_v1(
- 		 * (spec CEA 861) or CEA timing table.
- 		 */
- 		params.usV_SyncStart =
--			cpu_to_le16((uint16_t)(bp_params->v_sync_start + 1));
-+				cpu_to_le16((uint16_t)(bp_params->v_sync_start + 1));
- 	}
- 
- 	if (bp_params->flags.HORZ_COUNT_BY_TWO)
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
- 
- 	if (EXEC_BIOS_CMD_TABLE(SetCRTC_Timing, params))
- 		result = BP_RESULT_OK;
-@@ -1922,38 +2070,38 @@ static enum bp_result set_crtc_timing_v1(
- }
- 
- static enum bp_result set_crtc_using_dtd_timing_v3(
--		struct bios_parser *bp,
--		struct bp_hw_crtc_timing_parameters *bp_params)
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
- {
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	SET_CRTC_USING_DTD_TIMING_PARAMETERS params = {0};
- 	uint8_t atom_controller_id;
- 
- 	if (bp->cmd_helper->controller_id_to_atom(
--		bp_params->controller_id, &atom_controller_id))
-+			bp_params->controller_id, &atom_controller_id))
- 		params.ucCRTC = atom_controller_id;
- 
- 	/* bios usH_Size wants h addressable size */
- 	params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable);
- 	/* bios usH_Blanking_Time wants borders included in blanking */
- 	params.usH_Blanking_Time =
--		cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
-+			cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
- 	/* bios usV_Size wants v addressable size */
- 	params.usV_Size = cpu_to_le16((uint16_t)bp_params->v_addressable);
- 	/* bios usV_Blanking_Time wants borders included in blanking */
- 	params.usV_Blanking_Time =
--		cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
-+			cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
- 	/* bios usHSyncOffset is the offset from the end of h addressable,
- 	 * our horizontalSyncStart is the offset from the beginning
- 	 * of h addressable */
- 	params.usH_SyncOffset =
--		cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
-+			cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
- 	params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
- 	/* bios usHSyncOffset is the offset from the end of v addressable,
- 	 * our verticalSyncStart is the offset from the beginning of
- 	 * v addressable */
- 	params.usV_SyncOffset =
--		cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
- 	params.usV_SyncWidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
- 
- 	/* we assume that overscan from original timing does not get bigger
-@@ -1963,16 +2111,16 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
- 
- 	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
- 
- 	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
- 
- 
- 	if (bp_params->flags.INTERLACE)	{
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
- 
- 		/* original DAL code has this condition to apply this
- 		 * for non-TV/CV only
-@@ -1990,14 +2138,14 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
- 			 * or CEA timing table.
- 			 */
- 			params.usV_SyncOffset =
--				cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1);
-+					cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1);
- 
- 		}
- 	}
- 
- 	if (bp_params->flags.HORZ_COUNT_BY_TWO)
- 		params.susModeMiscInfo.usAccess =
--			cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
- 
- 	if (EXEC_BIOS_CMD_TABLE(SetCRTC_UsingDTDTiming, params))
- 		result = BP_RESULT_OK;
-@@ -2006,12 +2154,12 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  SET CRTC OVERSCAN
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  SET CRTC OVERSCAN
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result set_crtc_overscan_v1(
- 	struct bios_parser *bp,
-@@ -2038,7 +2186,7 @@ static enum bp_result set_crtc_overscan_v1(
- 	uint8_t atom_controller_id;
- 
- 	if (bp->cmd_helper->controller_id_to_atom(
--		bp_params->controller_id, &atom_controller_id))
-+			bp_params->controller_id, &atom_controller_id))
- 		params.ucCRTC = atom_controller_id;
- 	else
- 		return BP_RESULT_BADINPUT;
-@@ -2059,12 +2207,12 @@ static enum bp_result set_crtc_overscan_v1(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  SELECT CRTC SOURCE
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  SELECT CRTC SOURCE
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result select_crtc_source_v2(
- 	struct bios_parser *bp,
-@@ -2102,26 +2250,26 @@ static enum bp_result select_crtc_source_v2(
- 
- 	/* set controller id */
- 	if (bp->cmd_helper->controller_id_to_atom(
--		bp_params->controller_id, &atom_controller_id))
-+			bp_params->controller_id, &atom_controller_id))
- 		params.ucCRTC = atom_controller_id;
- 	else
- 		return BP_RESULT_FAILURE;
- 
- 	/* set encoder id */
- 	if (bp->cmd_helper->engine_bp_to_atom(
--		bp_params->engine_id, &atom_engine_id))
-+			bp_params->engine_id, &atom_engine_id))
- 		params.ucEncoderID = (uint8_t)atom_engine_id;
- 	else
- 		return BP_RESULT_FAILURE;
- 
- 	if (SIGNAL_TYPE_EDP == s ||
- 			(SIGNAL_TYPE_DISPLAY_PORT == s &&
--				SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+					SIGNAL_TYPE_LVDS == bp_params->sink_signal))
- 		s = SIGNAL_TYPE_LVDS;
- 
- 	params.ucEncodeMode =
--		(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--			s, bp_params->enable_dp_audio);
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					s, bp_params->enable_dp_audio);
- 
- 	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
- 		result = BP_RESULT_OK;
-@@ -2155,12 +2303,12 @@ static enum bp_result select_crtc_source_v3(
- 
- 	if (SIGNAL_TYPE_EDP == s ||
- 			(SIGNAL_TYPE_DISPLAY_PORT == s &&
--			SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+					SIGNAL_TYPE_LVDS == bp_params->sink_signal))
- 		s = SIGNAL_TYPE_LVDS;
- 
- 	params.ucEncodeMode =
--		bp->cmd_helper->encoder_mode_bp_to_atom(
--			s, bp_params->enable_dp_audio);
-+			bp->cmd_helper->encoder_mode_bp_to_atom(
-+					s, bp_params->enable_dp_audio);
- 	/* Needed for VBIOS Random Spatial Dithering feature */
- 	params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
- 
-@@ -2171,12 +2319,12 @@ static enum bp_result select_crtc_source_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  ENABLE CRTC
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  ENABLE CRTC
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result enable_crtc_v1(
- 	struct bios_parser *bp,
-@@ -2221,12 +2369,12 @@ static enum bp_result enable_crtc_v1(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  ENABLE CRTC MEM REQ
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  ENABLE CRTC MEM REQ
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result enable_crtc_mem_req_v1(
- 	struct bios_parser *bp,
-@@ -2272,12 +2420,12 @@ static enum bp_result enable_crtc_mem_req_v1(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  DISPLAY PLL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  DISPLAY PLL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result program_clock_v5(
- 	struct bios_parser *bp,
-@@ -2312,7 +2460,7 @@ static enum bp_result program_clock_v5(
- 
- 	dc_service_memset(&params, 0, sizeof(params));
- 	if (!bp->cmd_helper->clock_source_id_to_atom(
--		bp_params->pll_id, &atom_pll_id)) {
-+			bp_params->pll_id, &atom_pll_id)) {
- 		BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
- 		return BP_RESULT_BADINPUT;
- 	}
-@@ -2320,7 +2468,7 @@ static enum bp_result program_clock_v5(
- 	/* We need to convert from KHz units into 10KHz units */
- 	params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
- 	params.sPCLKInput.usPixelClock =
--		cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
-+			cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
- 	params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
- 
- 	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-@@ -2344,7 +2492,7 @@ static enum bp_result program_clock_v6(
- 	dc_service_memset(&params, 0, sizeof(params));
- 
- 	if (!bp->cmd_helper->clock_source_id_to_atom(
--		bp_params->pll_id, &atom_pll_id)) {
-+			bp_params->pll_id, &atom_pll_id)) {
- 		BREAK_TO_DEBUGGER(); /*Invalid Input!!*/
- 		return BP_RESULT_BADINPUT;
- 	}
-@@ -2352,7 +2500,7 @@ static enum bp_result program_clock_v6(
- 	/* We need to convert from KHz units into 10KHz units */
- 	params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
- 	params.sPCLKInput.ulDispEngClkFreq =
--		cpu_to_le32(bp_params->target_pixel_clock / 10);
-+			cpu_to_le32(bp_params->target_pixel_clock / 10);
- 
- 	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
- 		params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-@@ -2361,7 +2509,7 @@ static enum bp_result program_clock_v6(
- 		/* True display clock is returned by VBIOS if DFS bypass
- 		 * is enabled. */
- 		bp_params->dfs_bypass_display_clock =
--			(uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10);
-+				(uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10);
- 		result = BP_RESULT_OK;
- 	}
- 
-@@ -2369,12 +2517,12 @@ static enum bp_result program_clock_v6(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                 COMPUTE MEMORY ENGINE PLL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                 COMPUTE MEMORY ENGINE PLL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result compute_memore_engine_pll_v4(
- 	struct bios_parser *bp,
-@@ -2385,7 +2533,7 @@ static void init_compute_memore_engine_pll(struct bios_parser *bp)
- 	switch (BIOS_CMD_TABLE_PARA_REVISION(ComputeMemoryEnginePLL)) {
- 	case 4:
- 		bp->cmd_tbl.compute_memore_engine_pll =
--			compute_memore_engine_pll_v4;
-+				compute_memore_engine_pll_v4;
- 		break;
- 	default:
- 		bp->cmd_tbl.compute_memore_engine_pll = NULL;
-@@ -2419,12 +2567,12 @@ static enum bp_result compute_memore_engine_pll_v4(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  EXTERNAL ENCODER CONTROL
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  EXTERNAL ENCODER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result external_encoder_control_v3(
- 	struct bios_parser *bp,
-@@ -2436,7 +2584,7 @@ static void init_external_encoder_control(
- 	switch (BIOS_CMD_TABLE_PARA_REVISION(ExternalEncoderControl)) {
- 	case 3:
- 		bp->cmd_tbl.external_encoder_control =
--			external_encoder_control_v3;
-+				external_encoder_control_v3;
- 		break;
- 	default:
- 		bp->cmd_tbl.external_encoder_control = NULL;
-@@ -2494,7 +2642,7 @@ static enum bp_result external_encoder_control_v3(
- 		/* output display connector type. Only valid in encoder
- 		 * initialization */
- 		cntl_params->usConnectorId =
--			cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
-+				cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
- 		break;
- 	case EXTERNAL_ENCODER_CONTROL_SETUP:
- 		/* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in
-@@ -2503,12 +2651,12 @@ static enum bp_result external_encoder_control_v3(
- 		 * Only valid in setup and enableoutput
- 		 */
- 		cntl_params->usPixelClock =
--			cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 		/* Indicate display output signal type drive by external
- 		 * encoder, only valid in setup and enableoutput */
- 		cntl_params->ucEncoderMode =
--			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--				cntl->signal, false);
-+				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+						cntl->signal, false);
- 
- 		if (is_input_signal_dp) {
- 			/* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz,
-@@ -2519,7 +2667,7 @@ static enum bp_result external_encoder_control_v3(
- 			 * in DP mode, only valid in encoder setup in DP mode.
- 			 */
- 			cntl_params->ucBitPerColor =
--				(uint8_t)(cntl->color_depth);
-+					(uint8_t)(cntl->color_depth);
- 		}
- 		/* Indicate how many lanes used by external encoder, only valid
- 		 * in encoder setup and enableoutput. */
-@@ -2527,10 +2675,10 @@ static enum bp_result external_encoder_control_v3(
- 		break;
- 	case EXTERNAL_ENCODER_CONTROL_ENABLE:
- 		cntl_params->usPixelClock =
--			cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
- 		cntl_params->ucEncoderMode =
--			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
--				cntl->signal, false);
-+				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+						cntl->signal, false);
- 		cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;
- 		break;
- 	default:
-@@ -2549,10 +2697,10 @@ static enum bp_result external_encoder_control_v3(
- 			 * ExternalEncoderControl runs detection and save result
- 			 * in BIOS scratch registers. */
- 			cntl->signal = bp->bios_helper->detect_sink(
--				bp->ctx,
--				encoder,
--				cntl->connector_obj_id,
--				cntl->signal);
-+					bp->ctx,
-+					encoder,
-+					cntl->connector_obj_id,
-+					cntl->signal);
- 		else/* BIOS table does not work. */
- #endif
- 		{
-@@ -2565,12 +2713,12 @@ static enum bp_result external_encoder_control_v3(
- }
- 
- /*******************************************************************************
--********************************************************************************
--**
--**                  ENABLE DISPLAY POWER GATING
--**
--********************************************************************************
--*******************************************************************************/
-+ ********************************************************************************
-+ **
-+ **                  ENABLE DISPLAY POWER GATING
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
- 
- static enum bp_result enable_disp_power_gating_v2_1(
- 	struct bios_parser *bp,
-@@ -2583,7 +2731,7 @@ static void init_enable_disp_power_gating(
- 	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating)) {
- 	case 1:
- 		bp->cmd_tbl.enable_disp_power_gating =
--			enable_disp_power_gating_v2_1;
-+				enable_disp_power_gating_v2_1;
- 		break;
- 	default:
- 		bp->cmd_tbl.enable_disp_power_gating = NULL;
-@@ -2607,10 +2755,88 @@ static enum bp_result enable_disp_power_gating_v2_1(
- 		return BP_RESULT_BADINPUT;
- 
- 	params.ucEnable =
--		bp->cmd_helper->disp_power_gating_action_to_atom(action);
-+			bp->cmd_helper->disp_power_gating_action_to_atom(action);
- 
- 	if (EXEC_BIOS_CMD_TABLE(EnableDispPowerGating, params))
- 		result = BP_RESULT_OK;
- 
- 	return result;
- }
-+
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  SET DCE CLOCK
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+enum bp_result set_dce_clock_v2_1(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params);
-+#endif
-+
-+static void init_set_dce_clock(struct bios_parser *bp)
-+{
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetDCEClock)) {
-+	case 1:
-+		bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_dce_clock = NULL;
-+		break;
-+	}
-+#endif
-+}
-+
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+static enum bp_result set_dce_clock_v2_1(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	SET_DCE_CLOCK_PS_ALLOCATION_V2_1 params;
-+	uint32_t atom_pll_id;
-+	uint32_t atom_clock_type;
-+
-+	dc_service_memset(&params, 0, sizeof(params));
-+
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+
-+	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
-+			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
-+		return BP_RESULT_BADINPUT;
-+
-+	params.asParam.ucDCEClkSrc  = atom_pll_id;
-+	params.asParam.ucDCEClkType = atom_clock_type;
-+
-+	if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
-+		if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
-+
-+		if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
-+
-+		if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
-+
-+		if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
-+	}
-+	else
-+		/* only program clock frequency if display clock is used; VBIOS will program DPREFCLK */
-+		/* We need to convert from KHz units into 10KHz units */
-+		params.asParam.ulDCEClkFreq = cpu_to_le32(bp_params->target_clock_frequency / 10);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetDCEClock, params)) {
-+		/* Convert from 10KHz units back to KHz */
-+		bp_params->target_clock_frequency = le32_to_cpu(params.asParam.ulDCEClkFreq) * 10;
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-index 814d31f..e233ea6 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-@@ -110,6 +110,9 @@ struct cmd_tbl {
- 		struct bios_parser *bp,
- 		enum controller_id crtc_id,
- 		enum bp_pipe_control_action action);
-+	enum bp_result (*set_dce_clock)(
-+		struct bios_parser *bp,
-+		struct bp_set_dce_clock_parameters *bp_params);
- };
- 
- void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp);
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index dad1426..51027c5 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -42,8 +42,8 @@ bool dal_bios_parser_init_cmd_tbl_helper(
- 	case DCE_VERSION_11_0:
- 		*h = dal_cmd_tbl_helper_dce110_get_table();
- 		return true;
--
- #endif
-+
- 	default:
- 		/* Unsupported DCE */
- 		BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-index e5c00de..cf563ce 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-@@ -57,6 +57,9 @@ struct command_table_helper {
- 	uint8_t (*phy_id_to_atom)(enum transmitter t);
- 	uint8_t (*disp_power_gating_action_to_atom)(
- 			enum bp_pipe_control_action action);
-+	bool (*dc_clock_type_to_atom)(enum bp_dce_clock_type id,
-+			uint32_t *atom_clock_type);
-+    uint8_t (*transmitter_color_depth_to_atom)(enum transmitter_color_depth id);
- };
- 
- bool dal_bios_parser_init_cmd_tbl_helper(const struct command_table_helper **h,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 45a069a..6121277 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -684,6 +684,8 @@ enum dc_status dce110_validate_with_context(
- 	context->res_ctx.pool = dc->res_pool;
- 
- 	result = dce_base_map_resources(dc, context);
-+
-+	if (result == DC_OK)
- 	result = map_clock_resources(dc, context);
- 
- 	if (result == DC_OK)
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-index 8e700ea..11f16b7 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-@@ -75,6 +75,7 @@ struct clock_source *dal_clock_source_create(
- 	}
- 	break;
- #endif
-+
- 	default:
- 		dal_logger_write(clk_src_init_data->ctx->logger,
- 			LOG_MAJOR_ERROR,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-index 0a83874..0210f03 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-@@ -88,6 +88,10 @@ struct registers {
- 	uint32_t dp_dtox_phase;
- 	uint32_t dp_dtox_modulo;
- 	uint32_t crtcx_pixel_rate_cntl;
-+	uint32_t combophyx_pll_wrap_cntl;
-+	uint32_t combophyx_freq_cntl0;
-+	uint32_t combophyx_freq_cntl2;
-+	uint32_t combophyx_freq_cntl3;
- };
- 
- struct clock_source {
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-index 71d1a6c..3de8951 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-@@ -125,12 +125,14 @@ static const enum gpio_ddc_line hw_ddc_lines[] = {
- 	GPIO_DDC_LINE_DDC1,
- 	GPIO_DDC_LINE_DDC2,
- 	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
- };
- 
- static const enum gpio_ddc_line hw_aux_lines[] = {
- 	GPIO_DDC_LINE_DDC1,
- 	GPIO_DDC_LINE_DDC2,
- 	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
- };
- 
- /* function table */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index a728446..6ef41b1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -40,7 +40,7 @@ struct core_stream;
- 
- #define MAX_PIPES 6
- #define MAX_STREAMS 6
--#define MAX_CLOCK_SOURCES 4
-+#define MAX_CLOCK_SOURCES 7
- 
- struct core_target {
- 	struct dc_target public;
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-index 6269164..13fa8ab 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -243,6 +243,9 @@ enum bp_result dal_bios_parser_adjust_pixel_clock(
- enum bp_result dal_bios_parser_set_pixel_clock(
- 	struct bios_parser *bp,
- 	struct bp_pixel_clock_parameters *bp_params);
-+enum bp_result dal_bios_parser_set_dce_clock(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params);
- enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
- 	struct bios_parser *bp,
- 	struct bp_spread_spectrum_parameters *bp_params,
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index da7d5f2..4176f28 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -248,6 +248,9 @@ struct bp_pixel_clock_parameters {
- 	/* VBIOS returns a fixed display clock when DFS-bypass feature
- 	 * is enabled (KHz) */
- 	uint32_t dfs_bypass_display_clock;
-+	/* color depth to support HDMI deep color */
-+	enum transmitter_color_depth color_depth;
-+
- 	struct program_pixel_clock_flags {
- 		uint32_t FORCE_PROGRAMMING_OF_PLL:1;
- 		/* Use Engine Clock as source for Display Clock when
-@@ -255,6 +258,14 @@ struct bp_pixel_clock_parameters {
- 		uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
- 		/* Use external reference clock (refDivSrc for PLL) */
- 		uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
-+		/* Force program PHY PLL only */
-+		uint32_t PROGRAM_PHY_PLL_ONLY:1;
-+		/* Support for YUV420 */
-+		uint32_t SUPPORT_YUV_420:1;
-+		/* Use XTALIN reference clock source */
-+		uint32_t SET_XTALIN_REF_SRC:1;
-+		/* Use GENLK reference clock source */
-+		uint32_t SET_GENLOCK_REF_DIV_SRC:1;
- 	} flags;
- };
- 
-@@ -266,6 +277,30 @@ struct bp_display_clock_parameters {
- 	uint32_t actual_post_divider_id;
- };
- 
-+enum bp_dce_clock_type {
-+	DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
-+	DCECLOCK_TYPE_DPREFCLK      = 1
-+};
-+
-+/* DCE Clock Parameters structure for SetDceClock Exec command table */
-+struct bp_set_dce_clock_parameters {
-+	enum clock_source_id pll_id; /* Clock Source Id */
-+	/* Display clock or DPREFCLK value */
-+	uint32_t target_clock_frequency;
-+	/* Clock to set: =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK */
-+	enum bp_dce_clock_type clock_type;
-+
-+	struct set_dce_clock_flags {
-+		uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
-+		/* Use XTALIN reference clock source */
-+		uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
-+		/* Use PCIE reference clock source */
-+		uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
-+		/* Use GENLK reference clock source */
-+		uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
-+	} flags;
-+};
-+
- struct spread_spectrum_flags {
- 	/* 1 = Center Spread; 0 = down spread */
- 	uint32_t CENTER_SPREAD:1;
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-index fcf3eea..5d69a34 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -99,9 +99,16 @@ enum clock_source_id {
- 	CLOCK_SOURCE_ID_DCPLL,
- 	CLOCK_SOURCE_ID_DFS,	/* DENTIST */
- 	CLOCK_SOURCE_ID_VCE,	/* VCE does not need a real PLL */
--	CLOCK_SOURCE_ID_DP_DTO,	/* Used to distinguish between */
--	/* programming pixel clock */
--	/* and ID (Phy) clock */
-+	/* Used to distinguish between programming pixel clock and ID (Phy) clock */
-+	CLOCK_SOURCE_ID_DP_DTO,
-+
-+	CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
-+	CLOCK_SOURCE_COMBO_PHY_PLL1,
-+	CLOCK_SOURCE_COMBO_PHY_PLL2,
-+	CLOCK_SOURCE_COMBO_PHY_PLL3,
-+	CLOCK_SOURCE_COMBO_PHY_PLL4,
-+	CLOCK_SOURCE_COMBO_PHY_PLL5,
-+	CLOCK_SOURCE_COMBO_DISPLAY_PLL0
- };
- 
- 
-@@ -224,6 +231,12 @@ union supported_stream_engines {
- 	uint32_t u_all;
- };
- 
-+enum transmitter_color_depth {
-+	TRANSMITTER_COLOR_DEPTH_24 = 0,  /* 8  bits */
-+	TRANSMITTER_COLOR_DEPTH_30,      /* 10 bits */
-+	TRANSMITTER_COLOR_DEPTH_36,      /* 12 bits */
-+	TRANSMITTER_COLOR_DEPTH_48       /* 16 bits */
-+};
- 
- /*
-  *****************************************************************************
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0590-drm-amd-dal-clean-up-watermark-structs.patch b/common/recipes-kernel/linux/files/0590-drm-amd-dal-clean-up-watermark-structs.patch
deleted file mode 100644
index acf3a3dc..00000000
--- a/common/recipes-kernel/linux/files/0590-drm-amd-dal-clean-up-watermark-structs.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From 26cb0f6a249c7a51de01fec74b8a8a07e47aacb5 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 3 Dec 2015 16:33:14 -0500
-Subject: [PATCH 0590/1110] drm/amd/dal: clean up watermark structs
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 58 ++++++++++------------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  6 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  9 ++--
- 5 files changed, 35 insertions(+), 42 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 542b3d7..2b54eb6 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3367,85 +3367,79 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 
- 	if (bw_data_internal->number_of_displays != 0) {
- 		struct bw_fixed high_sclk = vbios->high_sclk_mhz;
-+		struct bw_fixed mid_sclk = vbios->mid_sclk_mhz;
- 		struct bw_fixed low_sclk = vbios->low_sclk_mhz;
- 		struct bw_fixed high_yclk = vbios->high_yclk_mhz;
- 		struct bw_fixed low_yclk = vbios->low_yclk_mhz;
- 
--		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_yclk_mhz = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_sclk_mhz = low_sclk;
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
- 
- 		/* units: nanosecond, 16bit storage. */
--		calcs_output->nbp_state_change_watermark[0].b_mark =
-+		calcs_output->nbp_state_change_wm_ns[0].b_mark =
- 			mul(bw_results_internal->nbp_state_change_watermark[4],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->nbp_state_change_watermark[1].b_mark =
-+		calcs_output->nbp_state_change_wm_ns[1].b_mark =
- 			mul(bw_results_internal->nbp_state_change_watermark[5],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->nbp_state_change_watermark[2].b_mark =
-+		calcs_output->nbp_state_change_wm_ns[2].b_mark =
- 			mul(bw_results_internal->nbp_state_change_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
--		calcs_output->stutter_exit_watermark[0].b_mark =
-+		calcs_output->stutter_exit_wm_ns[0].b_mark =
- 			mul(bw_results_internal->stutter_exit_watermark[4],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->stutter_exit_watermark[1].b_mark =
-+		calcs_output->stutter_exit_wm_ns[1].b_mark =
- 			mul(bw_results_internal->stutter_exit_watermark[5],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->stutter_exit_watermark[2].b_mark =
-+		calcs_output->stutter_exit_wm_ns[2].b_mark =
- 			mul(bw_results_internal->stutter_exit_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
--		calcs_output->urgent_watermark[0].b_mark =
-+		calcs_output->urgent_wm_ns[0].b_mark =
- 			mul(bw_results_internal->urgent_watermark[4],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->urgent_watermark[1].b_mark =
-+		calcs_output->urgent_wm_ns[1].b_mark =
- 			mul(bw_results_internal->urgent_watermark[5],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->urgent_watermark[2].b_mark =
-+		calcs_output->urgent_wm_ns[2].b_mark =
- 			mul(bw_results_internal->urgent_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
- 		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = high_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_yclk_mhz = high_yclk;
- 		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = high_sclk;
- 		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = high_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_sclk_mhz = high_sclk;
- 
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
- 
--		calcs_output->nbp_state_change_watermark[0].a_mark =
-+		calcs_output->nbp_state_change_wm_ns[0].a_mark =
- 			mul(bw_results_internal->nbp_state_change_watermark[4],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->nbp_state_change_watermark[1].a_mark =
-+		calcs_output->nbp_state_change_wm_ns[1].a_mark =
- 			mul(bw_results_internal->nbp_state_change_watermark[5],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->nbp_state_change_watermark[2].a_mark =
-+		calcs_output->nbp_state_change_wm_ns[2].a_mark =
- 			mul(bw_results_internal->nbp_state_change_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
--		calcs_output->stutter_exit_watermark[0].a_mark =
-+		calcs_output->stutter_exit_wm_ns[0].a_mark =
- 			mul(bw_results_internal->stutter_exit_watermark[4],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->stutter_exit_watermark[1].a_mark =
-+		calcs_output->stutter_exit_wm_ns[1].a_mark =
- 			mul(bw_results_internal->stutter_exit_watermark[5],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->stutter_exit_watermark[2].a_mark =
-+		calcs_output->stutter_exit_wm_ns[2].a_mark =
- 			mul(bw_results_internal->stutter_exit_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
--		calcs_output->urgent_watermark[0].a_mark =
-+		calcs_output->urgent_wm_ns[0].a_mark =
- 			mul(bw_results_internal->urgent_watermark[4],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->urgent_watermark[1].a_mark =
-+		calcs_output->urgent_wm_ns[1].a_mark =
- 			mul(bw_results_internal->urgent_watermark[5],
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->urgent_watermark[2].a_mark =
-+		calcs_output->urgent_wm_ns[2].a_mark =
- 			mul(bw_results_internal->urgent_watermark[6],
- 					int_to_fixed(1000)).value >> 24;
- 
-@@ -3460,25 +3454,23 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 		calcs_output->dispclk_khz =
- 				mul(bw_results_internal->dispclk,
- 					int_to_fixed(1000)).value >> 24;
--		calcs_output->blackout_recovery_time_us =
--			mul(bw_results_internal->blackout_recovery_time,
--					int_to_fixed(1000)).value >> 24;
-+		/*TODO:fix formula to unhardcode use levels*/
-+		calcs_output->required_blackout_duration_us =
-+			add(bw_results_internal->blackout_duration_margin[2][2],
-+					vbios->blackout_duration).value >> 24;
- 		calcs_output->required_sclk =
- 			mul(bw_results_internal->required_sclk,
- 					int_to_fixed(1000)).value >> 24;
- 		calcs_output->required_sclk_deep_sleep =
- 			mul(bw_results_internal->sclk_deep_sleep,
- 					int_to_fixed(1000)).value >> 24;
--		/*TODO:fix formula to unhardcode*/
-+		/*TODO:fix formula to unhardcode use levels*/
- 		calcs_output->required_yclk =
- 				mul(high_yclk, int_to_fixed(1000)).value >> 24;
- 
- 		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_yclk_mhz =
--								high_yclk;
- 		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = high_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->high_sclk_mhz = high_sclk;
-+		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = mid_sclk;
- 	} else {
- 		calcs_output->nbp_state_change_enable = true;
- 		calcs_output->cpuc_state_change_enable = true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index feda859..6351ef5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -579,7 +579,7 @@ static void pplib_apply_display_requirements(
- 	pp_display_cfg.cpu_pstate_disable =
- 			context->bw_results.cpup_state_change_enable == false;
- 	pp_display_cfg.cpu_pstate_separation_time =
--			context->bw_results.blackout_recovery_time_us;
-+			context->bw_results.required_blackout_duration_us;
- 
- 	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk;
- 	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index edbf3ce..10cc727 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1155,11 +1155,11 @@ static void set_displaymarks(
- 			dce110_mem_input_program_display_marks(
- 				stream->mi,
- 				context->bw_results
--				.nbp_state_change_watermark[total_streams],
-+				.nbp_state_change_wm_ns[total_streams],
- 				context->bw_results
--					.stutter_exit_watermark[total_streams],
-+					.stutter_exit_wm_ns[total_streams],
- 				context->bw_results
--					.urgent_watermark[total_streams],
-+					.urgent_wm_ns[total_streams],
- 				stream->public.timing.h_total,
- 				stream->public.timing.pix_clk_khz,
- 				1000 * dc->bw_vbios.blackout_duration
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 6121277..400271e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -575,7 +575,7 @@ enum dc_status dce110_validate_bandwidth(
- 		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
- 		"%s: Finish bandwidth calculations\n nbpMark: %d",
- 		__func__,
--		context->bw_results.nbp_state_change_watermark[0].b_mark);
-+		context->bw_results.nbp_state_change_wm_ns[0].b_mark);
- 
- 	return result;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index 6422298..fb04ce3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -242,6 +242,7 @@ struct bw_calcs_input_mode_data {
-  * Output data structure(s).
-  ******************************************************************************/
- #define maximum_number_of_surfaces 12
-+/*Units : MHz, us */
- struct bw_results_internal {
- 	bool cpup_state_change_enable;
- 	bool cpuc_state_change_enable;
-@@ -430,14 +431,14 @@ struct bw_calcs_output {
- 	bool cpup_state_change_enable;
- 	bool stutter_mode_enable;
- 	bool nbp_state_change_enable;
--	struct bw_watermarks urgent_watermark[4];
--	struct bw_watermarks stutter_exit_watermark[4];
--	struct bw_watermarks nbp_state_change_watermark[4];
-+	struct bw_watermarks urgent_wm_ns[4];
-+	struct bw_watermarks stutter_exit_wm_ns[4];
-+	struct bw_watermarks nbp_state_change_wm_ns[4];
- 	uint32_t required_sclk;
- 	uint32_t required_sclk_deep_sleep;
- 	uint32_t required_yclk;
- 	uint32_t dispclk_khz;
--	uint32_t blackout_recovery_time_us;
-+	uint32_t required_blackout_duration_us;
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0591-drm-amd-dal-Define-debug-DPCD-registers.patch b/common/recipes-kernel/linux/files/0591-drm-amd-dal-Define-debug-DPCD-registers.patch
deleted file mode 100644
index 19d7e08d..00000000
--- a/common/recipes-kernel/linux/files/0591-drm-amd-dal-Define-debug-DPCD-registers.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 393505c33d9d729a566c246193e4011c2de84cf9 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Mon, 7 Dec 2015 17:52:01 -0500
-Subject: [PATCH 0591/1110] drm/amd/dal: Define debug DPCD registers
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index cefa1fc..bd410cc 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -158,8 +158,12 @@ enum dpcd_address {
- 	/* Source Device Specific Field */
- 	DPCD_ADDRESS_SOURCE_DEVICE_ID_START = 0x0300,
- 	DPCD_ADDRESS_SOURCE_DEVICE_ID_END = 0x0301,
--	DPCD_ADDRESS_SOURCE_RESERVED_START = 0x030C,
--	DPCD_ADDRESS_SOURCE_RESERVED_END = 0x03FF,
-+	DPCD_ADDRESS_AMD_INTERNAL_DEBUG_START       = 0x030C,
-+	DPCD_ADDRESS_AMD_INTERNAL_DEBUG_END         = 0x030F,
-+	DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_START    = 0x0310,
-+	DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_END      = 0x037F,
-+	DPCD_ADDRESS_SOURCE_RESERVED_START         = 0x0380,
-+	DPCD_ADDRESS_SOURCE_RESERVED_END           = 0x03FF,
- 
- 	/* Sink Device Specific Field */
- 	DPCD_ADDRESS_SINK_DEVICE_ID_START = 0x0400,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0592-drm-amd-dal-fix-issue-when-removing-sinks-where-arra.patch b/common/recipes-kernel/linux/files/0592-drm-amd-dal-fix-issue-when-removing-sinks-where-arra.patch
deleted file mode 100644
index 3767a7dc..00000000
--- a/common/recipes-kernel/linux/files/0592-drm-amd-dal-fix-issue-when-removing-sinks-where-arra.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From b16aa9724e42f2a9d6f581ab5940f649fe44eea9 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 19:20:12 +0800
-Subject: [PATCH 0592/1110] drm/amd/dal: fix issue when removing sinks where
- array index is incorrect
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 15 ++++++++++-----
- 1 file changed, 10 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index e7a12e0..fe36786 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -357,10 +357,13 @@ static bool is_dp_active_dongle(enum display_dongle_type dongle_type)
- 
- static void link_disconnect_all_sinks(struct core_link *link)
- {
--	int i;
--
--	for (i = 0; i < link->public.sink_count; i++)
--		dc_link_remove_sink(&link->public, link->public.sink[i]);
-+	/*
-+	 * as sink_count changed inside dc_link_remove_sink, we should not
-+	 * use it for range check for loop, because half of sinks will not
-+	 * be removed
-+	 */
-+	while (link->public.sink_count)
-+		dc_link_remove_sink(&link->public, link->public.sink[0]);
- 
- 	link->dpcd_sink_count = 0;
- }
-@@ -516,7 +519,9 @@ void dc_link_detect(const struct dc_link *dc_link)
- 					 * ->sink = NULL
- 					 * TODO: s3 resume check*/
- 
--					if (dc_helpers_dp_mst_start_top_mgr(link->ctx, &link->public)) {
-+					if (dc_helpers_dp_mst_start_top_mgr(
-+						link->ctx,
-+						&link->public)) {
- 						return;
- 					} else {
- 						/* MST not supported */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0593-drm-amd-dal-do-not-use-MST-sink-for-regular-connecto.patch b/common/recipes-kernel/linux/files/0593-drm-amd-dal-do-not-use-MST-sink-for-regular-connecto.patch
deleted file mode 100644
index 40596ee6..00000000
--- a/common/recipes-kernel/linux/files/0593-drm-amd-dal-do-not-use-MST-sink-for-regular-connecto.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From d4a92b1b70422f7a67d28503d7beb3ed5fce9a7e Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 19:34:30 +0800
-Subject: [PATCH 0593/1110] drm/amd/dal: do not use MST sink for regular
- connector
-
-This fix is intention to block set mode on non-MST when
-MST branch was disconnected. It is temporary, proper fix
-based on sink refcounts will be applied
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 9bb8165..e68598f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -736,10 +736,18 @@ void amdgpu_dm_update_connector_after_detect(
- 	/* MST handled by drm_mst framework */
- 	if (aconnector->mst_mgr.mst_state)
- 		return;
-+
- 	if (!dm_get_sink_from_link(dc_link, aconnector, &sink)) {
- 		return;
- 	}
- 
-+	/*
-+	 * TODO: temporary guard to look for proper fix
-+	 * if this sink is MST sink, we should not do anything
-+	 */
-+	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		return;
-+
- 	if (aconnector->dc_sink == sink) {
- 		/* We got a DP short pulse (Link Loss, DP CTS, etc...).
- 		 * Do nothing!! */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0594-drm-amd-dal-use-const-for-new-link-sink-mgmt-interfa.patch b/common/recipes-kernel/linux/files/0594-drm-amd-dal-use-const-for-new-link-sink-mgmt-interfa.patch
deleted file mode 100644
index a4d995cf..00000000
--- a/common/recipes-kernel/linux/files/0594-drm-amd-dal-use-const-for-new-link-sink-mgmt-interfa.patch
+++ /dev/null
@@ -1,177 +0,0 @@
-From 9cdf4728c089667bee0b2297aa7ba84103f7e130 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 19:50:16 +0800
-Subject: [PATCH 0594/1110] drm/amd/dal: use const for new link sink mgmt
- interfaces
-
-We should be consistent with our approach to forbid object
-changes from DM, interface we provide should receive const
-pointer as parameter
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 21 ++++++++++------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 29 ++++++++++++----------
- drivers/gpu/drm/amd/dal/dc/dc.h                    | 11 ++++----
- 3 files changed, 34 insertions(+), 27 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 2f3a784..ca4a244 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -94,8 +94,8 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
- 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property
- };
- 
--static const struct dc_sink *dm_dp_mst_add_mst_sink(
--		struct dc_link *dc_link,
-+static struct dc_sink *dm_dp_mst_add_mst_sink(
-+		const struct dc_link *dc_link,
- 		uint8_t *edid,
- 		uint16_t len)
- {
-@@ -110,6 +110,11 @@ static const struct dc_sink *dm_dp_mst_add_mst_sink(
- 		return NULL;
- 	}
- 
-+	if (!dc_link) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
- 	/*
- 	 * TODO make dynamic-ish?
- 	 * dc_link->connector_signal;
-@@ -126,7 +131,7 @@ static const struct dc_sink *dm_dp_mst_add_mst_sink(
- 	if (!dc_link_add_sink(
- 			dc_link,
- 			dc_sink))
--		goto fail;
-+		goto fail_add_sink;
- 
- 	edid_status = dc_helpers_parse_edid_caps(
- 			NULL,
-@@ -138,9 +143,9 @@ static const struct dc_sink *dm_dp_mst_add_mst_sink(
- 	/* dc_sink_retain(&core_sink->public); */
- 
- 	return dc_sink;
--
- fail:
- 	dc_link_remove_sink(dc_link, dc_sink);
-+fail_add_sink:
- 	return NULL;
- }
- 
-@@ -168,10 +173,10 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
- 
- 	if (!aconnector->dc_sink) {
- 			sink = dm_dp_mst_add_mst_sink(
--			(struct dc_link *)aconnector->dc_link,
--			(uint8_t *)edid,
--			(edid->extensions + 1) * EDID_LENGTH);
--			aconnector->dc_sink = sink;
-+				aconnector->dc_link,
-+				(uint8_t *)edid,
-+				(edid->extensions + 1) * EDID_LENGTH);
-+				aconnector->dc_sink = sink;
- 	}
- 
- 	DRM_DEBUG_KMS("edid retrieved %p\n", edid);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 6351ef5..a20a5ef 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -950,43 +950,46 @@ bool dc_write_dpcd(
- 	return r == DDC_RESULT_SUCESSFULL;
- }
- 
--bool dc_link_add_sink(
--		struct dc_link *link,
--		struct dc_sink *sink)
-+bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
- {
--	if (link->sink_count >= MAX_SINKS_PER_LINK) {
-+	struct core_link *core_link = DC_LINK_TO_LINK(link);
-+	struct dc_link *dc_link = &core_link->public;
-+
-+	if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
- 		BREAK_TO_DEBUGGER();
- 		return false;
- 	}
- 
--	link->sink[link->sink_count] = sink;
--	link->sink_count++;
-+	dc_link->sink[link->sink_count] = sink;
-+	dc_link->sink_count++;
- 
- 	return true;
- }
- 
- 
--void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink)
-+void dc_link_remove_sink(const struct dc_link *link, const struct dc_sink *sink)
- {
- 	int i;
-+	struct core_link *core_link = DC_LINK_TO_LINK(link);
-+	struct dc_link *dc_link = &core_link->public;
- 
- 	if (!link->sink_count) {
- 		BREAK_TO_DEBUGGER();
- 		return;
- 	}
- 
--	for (i = 0; i < link->sink_count; i++) {
--		if (link->sink[i] == sink) {
-+	for (i = 0; i < dc_link->sink_count; i++) {
-+		if (dc_link->sink[i] == sink) {
- 			dc_sink_release(sink);
--			link->sink[i] = NULL;
-+			dc_link->sink[i] = NULL;
- 
- 			/* shrink array to remove empty place */
--			while (i < link->sink_count - 1) {
--				link->sink[i] = link->sink[i+1];
-+			while (i < dc_link->sink_count - 1) {
-+				dc_link->sink[i] = dc_link->sink[i+1];
- 				i++;
- 			}
- 
--			link->sink_count--;
-+			dc_link->sink_count--;
- 			return;
- 		}
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index fa2712c..bbeaf23 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -303,12 +303,11 @@ void dc_link_detect(const struct dc_link *dc_link);
-  * from DM. */
- bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link);
- 
--bool dc_link_add_sink(
--		struct dc_link *link,
--		struct dc_sink *sink
--		);
-+bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink);
- 
--void dc_link_remove_sink(struct dc_link *link, const struct dc_sink *sink);
-+void dc_link_remove_sink(
-+	const struct dc_link *link,
-+	const struct dc_sink *sink);
- 
- /*******************************************************************************
-  * Sink Interfaces - A sink corresponds to a display output device
-@@ -330,7 +329,7 @@ const struct audio **dc_get_audios(struct dc *dc);
- 
- struct sink_init_data {
- 	enum signal_type sink_signal;
--	struct dc_link *link;
-+	const struct dc_link *link;
- 	uint32_t dongle_max_pix_clk;
- 	bool converter_disable_audio;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0595-drm-amd-dal-do-not-remove-MST-sinks-in-DC.patch b/common/recipes-kernel/linux/files/0595-drm-amd-dal-do-not-remove-MST-sinks-in-DC.patch
deleted file mode 100644
index db0bf660..00000000
--- a/common/recipes-kernel/linux/files/0595-drm-amd-dal-do-not-remove-MST-sinks-in-DC.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From d906352dfc34ffcd1459b21b6f1f2de61c5ac85d Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 19:57:21 +0800
-Subject: [PATCH 0595/1110] drm/amd/dal: do not remove MST sinks in DC
-
-They will be removed by appropriate code in DM, as
-they were created in DM
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 18 +++++++++++++++++-
- 1 file changed, 17 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index fe36786..2f2800f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -639,11 +639,27 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		switch (link->public.connector_signal) {
- 		case SIGNAL_TYPE_DISPLAY_PORT:
- 			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
-+			/*
-+			 * in this case sinks would be removed in outer level
-+			 */
-+
-+			/*
-+			 * TODO: this is the only way to understand that link
-+			 * was in mst mode. Proposal for future to add
-+			 * additional field to link that will show actual state.
-+			 *
-+			 * For the change: for mst we create sink outside, and
-+			 * should remove them in the same place
-+			 */
-+			if (link->public.sink_count == 1 &&
-+				link->public.sink[0]->sink_signal !=
-+					SIGNAL_TYPE_DISPLAY_PORT_MST)
-+				link_disconnect_all_sinks(link);
- 			break;
- 		default:
-+			link_disconnect_all_sinks(link);
- 			break;
- 		}
--		link_disconnect_all_sinks(link);
- 	}
- 
- 	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0596-drm-amd-dal-find-proper-connector-in-reset-case.patch b/common/recipes-kernel/linux/files/0596-drm-amd-dal-find-proper-connector-in-reset-case.patch
deleted file mode 100644
index 41c738e6..00000000
--- a/common/recipes-kernel/linux/files/0596-drm-amd-dal-find-proper-connector-in-reset-case.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 52b28a87980253648b092fa584ae9be4e67ecead Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:03:01 +0800
-Subject: [PATCH 0596/1110] drm/amd/dal: find proper connector in reset case
-
-Find connector on reset properly, and allow reset mode occur for
-MST connector.
-
-It also remove warning messages seen previously
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 6dc7ead..9f467eb 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2115,6 +2115,16 @@ int amdgpu_dm_atomic_commit(
- 				aconnector = to_amdgpu_connector(connector);
- 				break;
- 			}
-+
-+			/*
-+			 * this is the case when reset occur, connector is
-+			 * removed from new crtc state. We need to update
-+			 * connector state anyway. Access it from old_con_state
-+			 */
-+			if (old_con_state->crtc == crtc) {
-+				aconnector = to_amdgpu_connector(connector);
-+				break;
-+			}
- 		}
- 
- 		/* handles headless hotplug case, updating new_state and
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0597-drm-amd-dal-remove-mst-sink-from-connector-and-link.patch b/common/recipes-kernel/linux/files/0597-drm-amd-dal-remove-mst-sink-from-connector-and-link.patch
deleted file mode 100644
index 25068d12..00000000
--- a/common/recipes-kernel/linux/files/0597-drm-amd-dal-remove-mst-sink-from-connector-and-link.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From cd50910fc45ff921fa6d02303026231e92a98b36 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:09:07 +0800
-Subject: [PATCH 0597/1110] drm/amd/dal: remove mst sink from connector and
- link
-
-When we detected that MST sink was disconnected, connector sink
-pointer should be cleaned-up and sink should be freed
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index ca4a244..16c82a2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -68,7 +68,18 @@ dm_dp_mst_detect(struct drm_connector *connector, bool force)
- 	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
- 	struct amdgpu_connector *master = aconnector->mst_port;
- 
--	return drm_dp_mst_detect_port(connector, &master->mst_mgr, aconnector->port);
-+	enum drm_connector_status status =
-+		drm_dp_mst_detect_port(
-+			connector,
-+			&master->mst_mgr,
-+			aconnector->port);
-+
-+	if (status == connector_status_disconnected && aconnector->dc_sink) {
-+		dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
-+		aconnector->dc_sink = NULL;
-+	}
-+
-+	return status;
- }
- 
- static void
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0598-drm-amd-dal-do-not-remove-MST-connector-until-reset-.patch b/common/recipes-kernel/linux/files/0598-drm-amd-dal-do-not-remove-MST-connector-until-reset-.patch
deleted file mode 100644
index 84248e1d..00000000
--- a/common/recipes-kernel/linux/files/0598-drm-amd-dal-do-not-remove-MST-connector-until-reset-.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 7a7302602be80b3033dbd4218be3b8fc8d6b2db0 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:18:00 +0800
-Subject: [PATCH 0598/1110] drm/amd/dal: do not remove MST connector until
- reset mode
-
-Before MST connector removal we need to make sure reset mode happened
-from user space, and all state is clear
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 7 +++++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c     | 5 +++++
- 2 files changed, 12 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 16c82a2..733d8aa 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -274,6 +274,8 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	aconnector->mst_port = master;
- 	aconnector->dc_link = master->dc_link;
- 
-+	sema_init(&aconnector->mst_sem, 1);
-+
- 	/* Initialize connector state before adding the connectror to drm and framebuffer lists */
- 	amdgpu_dm_connector_funcs_reset(connector);
- 
-@@ -296,8 +298,13 @@ static void dm_dp_destroy_mst_connector(
- {
- 	struct amdgpu_connector *master =
- 		container_of(mgr, struct amdgpu_connector, mst_mgr);
-+	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
- 	struct drm_device *dev = master->base.dev;
- 	struct amdgpu_device *adev = dev->dev_private;
-+
-+	/* wait until reset mode occur */
-+	down(&aconnector->mst_sem);
-+
- 	drm_connector_unregister(connector);
- 	/* need to nuke the connector */
- 	mutex_lock(&dev->mode_config.mutex);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 9f467eb..ea7a623 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1856,6 +1856,7 @@ int amdgpu_dm_connector_init(
- 			dm->backlight_link = link;
- 	}
- #endif
-+	sema_init(&aconnector->mst_sem, 1);
- 
- 	return 0;
- }
-@@ -2174,6 +2175,7 @@ int amdgpu_dm_atomic_commit(
- 				/* this is the update mode case */
- 				dc_target_release(acrtc->target);
- 				acrtc->target = NULL;
-+				up(&aconnector->mst_sem);
- 			}
- 
- 			/*
-@@ -2187,10 +2189,12 @@ int amdgpu_dm_atomic_commit(
- 			acrtc->target = new_target;
- 			acrtc->enabled = true;
- 			acrtc->base.enabled = true;
-+
- 			connector_funcs = aconnector->base.helper_private;
- 			aconnector->base.encoder =
- 				connector_funcs->best_encoder(
- 					&aconnector->base);
-+			down(&aconnector->mst_sem);
- 			break;
- 		}
- 
-@@ -2209,6 +2213,7 @@ int amdgpu_dm_atomic_commit(
- 				acrtc->enabled = false;
- 				acrtc->base.enabled = false;
- 				aconnector->base.encoder = NULL;
-+				up(&aconnector->mst_sem);
- 			}
- 			break;
- 		} /* switch() */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0599-drm-amd-dal-notify-userspace-on-MST-branch-disconnec.patch b/common/recipes-kernel/linux/files/0599-drm-amd-dal-notify-userspace-on-MST-branch-disconnec.patch
deleted file mode 100644
index cfa42198..00000000
--- a/common/recipes-kernel/linux/files/0599-drm-amd-dal-notify-userspace-on-MST-branch-disconnec.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From b624316ed999cd0a9aa1361e24cb6d99e7f42f54 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:25:16 +0800
-Subject: [PATCH 0599/1110] drm/amd/dal: notify userspace on MST branch
- disconnect
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 733d8aa..bd35d2e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -273,6 +273,7 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	aconnector->port = port;
- 	aconnector->mst_port = master;
- 	aconnector->dc_link = master->dc_link;
-+	aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
- 
- 	sema_init(&aconnector->mst_sem, 1);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0600-drm-amd-dal-Prepare-DP-support-for-next-ASIC-generat.patch b/common/recipes-kernel/linux/files/0600-drm-amd-dal-Prepare-DP-support-for-next-ASIC-generat.patch
deleted file mode 100644
index dff3b960..00000000
--- a/common/recipes-kernel/linux/files/0600-drm-amd-dal-Prepare-DP-support-for-next-ASIC-generat.patch
+++ /dev/null
@@ -1,197 +0,0 @@
-From 8a73138524b386d7bd3183004fbf86c91a43328c Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Tue, 8 Dec 2015 17:48:05 -0500
-Subject: [PATCH 0600/1110] drm/amd/dal: Prepare DP support for next ASIC
- generation
-
-1.) Fix link encoder not properly initializing HPD for AUX
-2.) Fix V6 atombios HPD src incorrectly shifted by 4 bits
-3.) Fixed connector object ID mismatch
-4.) Fixed PLL clock source programming incorrectly multiplying pixel clock by 100
-5.) Fixed calling VBIOS pixel clock programming being called with clock off by factor of 10
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    |  2 +-
- .../drm/amd/dal/dc/connector/connector_signals.c   | 38 ++++++++++++++++++++--
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h      |  1 +
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.c    |  2 +-
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c   |  4 +++
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   | 30 ++++++++---------
- 6 files changed, 57 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index 8503eca..c686cc8 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -1247,7 +1247,7 @@ static enum bp_result set_pixel_clock_v7(
- 		clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
- 
- 		/* We need to convert from KHz units into 10KHz units */
--		clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock / 10);
-+		clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock * 10);
- 
- 		clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c b/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-index d1a289d..3a5d75b 100644
---- a/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-+++ b/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-@@ -165,14 +165,31 @@ const struct connector_signals default_signals[] = {
- 		SIGNALS_ARRAY_ELEM(default_signals_single_link_dvid),
- 		SIGNALS_ARRAY_ELEM(default_signals_dual_link_dvid),
- 		SIGNALS_ARRAY_ELEM(default_signals_vga),
-+		/* Composite */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		/* S Video */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		/* YPbPr */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		/* DConnector */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		/* 9pinDIN */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
-+		/* SCART */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
- 		SIGNALS_ARRAY_ELEM(default_signals_hdmi_type_a),
-+		/* Not Used */
- 		SIGNALS_ARRAY_ELEM(default_signals_none),
- 		SIGNALS_ARRAY_ELEM(default_signals_lvds),
-+		/* 7pin DIN*/
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
- 		SIGNALS_ARRAY_ELEM(default_signals_pcie),
-+		/* CrossFire */
-+		SIGNALS_ARRAY_ELEM(default_signals_none),
- 		SIGNALS_ARRAY_ELEM(default_signals_hardcode_dvi),
- 		SIGNALS_ARRAY_ELEM(default_signals_displayport),
- 		SIGNALS_ARRAY_ELEM(default_signals_edp),
--		/* MXM dummy connector */
-+		/* MXM*/
- 		SIGNALS_ARRAY_ELEM(default_signals_none),
- 		SIGNALS_ARRAY_ELEM(default_signals_wireless),
- 		SIGNALS_ARRAY_ELEM(default_signals_miracast)
-@@ -188,14 +205,31 @@ const struct connector_signals supported_signals[] = {
- 		SIGNALS_ARRAY_ELEM(signals_single_link_dvid),
- 		SIGNALS_ARRAY_ELEM(signals_dual_link_dvid),
- 		SIGNALS_ARRAY_ELEM(signals_vga),
-+		/* Composite */
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		/* S Video */
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		/* YPbPr */
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		/* DConnector */
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		/* 9pinDIN */
-+		SIGNALS_ARRAY_ELEM(signals_none),
-+		/* SCART */
-+		SIGNALS_ARRAY_ELEM(signals_none),
- 		SIGNALS_ARRAY_ELEM(signals_hdmi_type_a),
-+		/* Note Used */
- 		SIGNALS_ARRAY_ELEM(signals_none),
- 		SIGNALS_ARRAY_ELEM(signals_lvds),
-+		/* 7pin DIN*/
-+		SIGNALS_ARRAY_ELEM(signals_none),
- 		SIGNALS_ARRAY_ELEM(signals_pcie),
-+		/* CrossFire */
-+		SIGNALS_ARRAY_ELEM(signals_none),
- 		SIGNALS_ARRAY_ELEM(signals_hardcode_dvi),
- 		SIGNALS_ARRAY_ELEM(signals_displayport),
- 		SIGNALS_ARRAY_ELEM(signals_edp),
--		/* MXM dummy connector */
-+		/* MXM */
- 		SIGNALS_ARRAY_ELEM(signals_none),
- 		SIGNALS_ARRAY_ELEM(signals_wireless),
- 		SIGNALS_ARRAY_ELEM(signals_miracast)
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-index 0210f03..67ececd 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-@@ -88,6 +88,7 @@ struct registers {
- 	uint32_t dp_dtox_phase;
- 	uint32_t dp_dtox_modulo;
- 	uint32_t crtcx_pixel_rate_cntl;
-+	uint32_t crtcx_phypll_pixel_rate_cntl;
- 	uint32_t combophyx_pll_wrap_cntl;
- 	uint32_t combophyx_freq_cntl0;
- 	uint32_t combophyx_freq_cntl2;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-index 7fd5984..80f7da7 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-@@ -168,7 +168,7 @@ static bool adjust_dto_pixel_rate(
- /**
-  * Retrieve Pixel Rate (in Hz) from HW registers already programmed.
-  */
--uint32_t retrieve_dp_pixel_rate_from_display_pll(
-+static uint32_t retrieve_dp_pixel_rate_from_display_pll(
- 		struct clock_source *clk_src,
- 		struct pixel_clk_params *params)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-index 3de8951..05f5778 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-@@ -126,6 +126,8 @@ static const enum gpio_ddc_line hw_ddc_lines[] = {
- 	GPIO_DDC_LINE_DDC2,
- 	GPIO_DDC_LINE_DDC3,
- 	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
- };
- 
- static const enum gpio_ddc_line hw_aux_lines[] = {
-@@ -133,6 +135,8 @@ static const enum gpio_ddc_line hw_aux_lines[] = {
- 	GPIO_DDC_LINE_DDC2,
- 	GPIO_DDC_LINE_DDC3,
- 	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
- };
- 
- /* function table */
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-index 5d69a34..1eafe7c 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -168,22 +168,20 @@ enum encoder_id {
- /* Connector object ids */
- enum connector_id {
- 	CONNECTOR_ID_UNKNOWN = 0,
--	CONNECTOR_ID_SINGLE_LINK_DVII,
--	CONNECTOR_ID_DUAL_LINK_DVII,
--	CONNECTOR_ID_SINGLE_LINK_DVID,
--	CONNECTOR_ID_DUAL_LINK_DVID,
--	CONNECTOR_ID_VGA,
--	CONNECTOR_ID_HDMI_TYPE_A,
--	CONNECTOR_ID_NOT_USED,
--	CONNECTOR_ID_LVDS,
--	CONNECTOR_ID_PCIE,
--	CONNECTOR_ID_HARDCODE_DVI,
--	CONNECTOR_ID_DISPLAY_PORT,
--	CONNECTOR_ID_EDP,
--	CONNECTOR_ID_MXM,
--	CONNECTOR_ID_WIRELESS,		/* wireless display pseudo-connector */
--	CONNECTOR_ID_MIRACAST,		/* used for VCE encode display path
--					 * for Miracast */
-+	CONNECTOR_ID_SINGLE_LINK_DVII = 1,
-+	CONNECTOR_ID_DUAL_LINK_DVII = 2,
-+	CONNECTOR_ID_SINGLE_LINK_DVID = 3,
-+	CONNECTOR_ID_DUAL_LINK_DVID = 4,
-+	CONNECTOR_ID_VGA = 5,
-+	CONNECTOR_ID_HDMI_TYPE_A = 12,
-+	CONNECTOR_ID_LVDS = 14,
-+	CONNECTOR_ID_PCIE = 16,
-+	CONNECTOR_ID_HARDCODE_DVI = 18,
-+	CONNECTOR_ID_DISPLAY_PORT = 19,
-+	CONNECTOR_ID_EDP = 20,
-+	CONNECTOR_ID_MXM = 21,
-+	CONNECTOR_ID_WIRELESS = 22,
-+	CONNECTOR_ID_MIRACAST = 23,
- 
- 	CONNECTOR_ID_COUNT
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0601-drm-amd-dal-use-more-robust-locking-for-MST.patch b/common/recipes-kernel/linux/files/0601-drm-amd-dal-use-more-robust-locking-for-MST.patch
deleted file mode 100644
index f110dab9..00000000
--- a/common/recipes-kernel/linux/files/0601-drm-amd-dal-use-more-robust-locking-for-MST.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 7c57782d480aecd86de11320e7772eafc772817a Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Dec 2015 20:27:15 +0800
-Subject: [PATCH 0601/1110] drm/amd/dal: use more robust locking for MST
-
-Used during connectors management
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index bd35d2e..ba1c854 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -308,14 +308,14 @@ static void dm_dp_destroy_mst_connector(
- 
- 	drm_connector_unregister(connector);
- 	/* need to nuke the connector */
--	mutex_lock(&dev->mode_config.mutex);
-+	drm_modeset_lock_all(dev);
- 	/* dpms off */
- 	drm_fb_helper_remove_one_connector(
- 		&adev->mode_info.rfbdev->helper,
- 		connector);
- 
- 	drm_connector_cleanup(connector);
--	mutex_unlock(&dev->mode_config.mutex);
-+	drm_modeset_unlock_all(dev);
- 
- 	kfree(connector);
- 	DRM_DEBUG_KMS("\n");
-@@ -335,9 +335,9 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector)
- 	struct drm_device *dev = connector->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
- 
--	mutex_lock(&dev->mode_config.mutex);
-+	drm_modeset_lock_all(dev);
- 	drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
--	mutex_unlock(&dev->mode_config.mutex);
-+	drm_modeset_unlock_all(dev);
- 
- 	drm_connector_register(connector);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0602-drm-amd-dal-add-bpp-from-dc_stream-for-payload-calcu.patch b/common/recipes-kernel/linux/files/0602-drm-amd-dal-add-bpp-from-dc_stream-for-payload-calcu.patch
deleted file mode 100644
index 7e3027fe..00000000
--- a/common/recipes-kernel/linux/files/0602-drm-amd-dal-add-bpp-from-dc_stream-for-payload-calcu.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 6a68f6c7463143c11ab2c6fb6c67c7ce13b1ed13 Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Wed, 9 Dec 2015 14:43:28 -0500
-Subject: [PATCH 0602/1110] drm/amd/dal: add bpp from dc_stream for payload
- calculation
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 33 +++++++++++++++++++---
- 1 file changed, 29 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index b388dee..87db164 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -180,7 +180,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	int slots = 0;
- 	bool ret;
- 	int clock;
--	int bpp;
-+	int bpp = 0;
- 	int pbn = 0;
- 	uint8_t i;
- 	uint8_t vcid = 0;
-@@ -199,9 +199,34 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	mst_port = aconnector->port;
- 
- 	if (enable) {
--		clock = crtc->state->mode.clock;
--		/* TODO remove following hardcode value */
--		bpp = 30;
-+		clock = stream->timing.pix_clk_khz;
-+
-+		switch (stream->timing.display_color_depth) {
-+
-+		case COLOR_DEPTH_666:
-+			bpp = 6;
-+			break;
-+		case COLOR_DEPTH_888:
-+			bpp = 8;
-+			break;
-+		case COLOR_DEPTH_101010:
-+			bpp = 10;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			bpp = 12;
-+			break;
-+		case COLOR_DEPTH_141414:
-+			bpp = 14;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			bpp = 16;
-+			break;
-+		default:
-+			ASSERT(bpp != 0);
-+			break;
-+		}
-+
-+		bpp = bpp * 3;
- 
- 		/* TODO need to know link rate */
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0603-drm-amd-dal-refactor-initial-detection.patch b/common/recipes-kernel/linux/files/0603-drm-amd-dal-refactor-initial-detection.patch
deleted file mode 100644
index 89965d98..00000000
--- a/common/recipes-kernel/linux/files/0603-drm-amd-dal-refactor-initial-detection.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 4d75ceb23fc5f0a4b1f1be1d09a04997e0ebe2da Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 7 Dec 2015 19:50:37 +0800
-Subject: [PATCH 0603/1110] drm/amd/dal: refactor initial detection
-
-We should not use iteration on connectors when we need
-iterate on links
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index e68598f..f85ce3b 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1025,7 +1025,6 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- {
- 	struct amdgpu_display_manager *dm = &adev->dm;
- 	uint32_t link_index;
--	struct drm_connector *connector;
- 	struct amdgpu_connector *aconnector;
- 	struct amdgpu_encoder *aencoder;
- 	struct amdgpu_crtc *acrtc;
-@@ -1087,14 +1086,15 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 			DRM_ERROR("KMS: Failed to initialize connector\n");
- 			goto fail;
- 		}
-+
-+		dc_link_detect(dc_get_link_at_index(dm->dc, link_index));
-+
-+		amdgpu_dm_update_connector_after_detect(
-+			aconnector);
- 	}
- 
- 	dm->display_indexes_num = link_cnt;
- 
--	detect_on_all_dc_links(&adev->dm);
--	list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head)
--		amdgpu_dm_update_connector_after_detect(to_amdgpu_connector(connector));
--
- 	/* Software is initialized. Now we can register interrupt handlers. */
- 	switch (adev->asic_type) {
- 	case CHIP_CARRIZO:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0604-drm-amd-dal-Fix-regamma-code-path.patch b/common/recipes-kernel/linux/files/0604-drm-amd-dal-Fix-regamma-code-path.patch
deleted file mode 100644
index 6a99bbf1..00000000
--- a/common/recipes-kernel/linux/files/0604-drm-amd-dal-Fix-regamma-code-path.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From dffc4ee3af58eb1f31ade966ec57232a27b4d653 Mon Sep 17 00:00:00 2001
-From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
-Date: Wed, 9 Dec 2015 11:19:01 -0500
-Subject: [PATCH 0604/1110] drm/amd/dal: Fix regamma code path
-
-[Description] Fix the logic in dal3 for enabling regamma, so that regamma can be applied correctly.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  6 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 64 +++++++++++-----------
- 2 files changed, 35 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 6e89050..9ae98c5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -142,7 +142,7 @@ static void build_gamma_params(
- 	gamma_param->regamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_SW;
- 	gamma_param->degamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_SW;
- 
--	gamma_param->selected_gamma_lut = GRAPHICS_GAMMA_LUT_LEGACY;
-+	gamma_param->selected_gamma_lut = GRAPHICS_GAMMA_LUT_REGAMMA;
- 
- 	/* TODO support non-legacy gamma */
- 	gamma_param->disable_adjustments = false;
-@@ -151,8 +151,8 @@ static void build_gamma_params(
- 	gamma_param->flag.bits.gamma_update = 1;
- 
- 	/* Set regamma */
--	gamma_param->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB = 0;
--	gamma_param->regamma.features.bits.OVERLAY_DEGAMMA_SRGB = 0;
-+	gamma_param->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB = 1;
-+	gamma_param->regamma.features.bits.OVERLAY_DEGAMMA_SRGB = 1;
- 	gamma_param->regamma.features.bits.GAMMA_RAMP_ARRAY = 0;
- 	gamma_param->regamma.features.bits.APPLY_DEGAMMA = 0;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index 4cba172..cf116f1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -1027,42 +1027,42 @@ static bool build_regamma_curve(
- 
- 	uint32_t i;
- 
--	if (!params->regamma.features.bits.GAMMA_RAMP_ARRAY &&
--		params->regamma.features.bits.APPLY_DEGAMMA) {
--		struct gamma_coefficients coeff;
-+	struct gamma_coefficients coeff;
- 
--		struct hw_x_point *coord_x =
--				opp110->regamma.coordinates_x;
-+	struct hw_x_point *coord_x =
-+		opp110->regamma.coordinates_x;
- 
--		build_regamma_coefficients(
--			&params->regamma,
--			params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB,
--			&coeff);
--
--		/* Use opp110->regamma.coordinates_x to retrieve
--		 * coordinates chosen base on given user curve (future task).
--		 * The x values are exponentially distributed and currently
--		 * it is hard-coded, the user curve shape is ignored.
--		 * The future task is to recalculate opp110-
--		 * regamma.coordinates_x based on input/user curve,
--		 * translation from 256/1025 to 128 pwl points.
--		 */
-+	build_regamma_coefficients(
-+		&params->regamma,
-+		params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB,
-+		&coeff);
- 
--		i = 0;
-+	/* Use opp110->regamma.coordinates_x to retrieve
-+	 * coordinates chosen base on given user curve (future task).
-+	 * The x values are exponentially distributed and currently
-+	 * it is hard-coded, the user curve shape is ignored.
-+	 * The future task is to recalculate opp110-
-+	 * regamma.coordinates_x based on input/user curve,
-+	 * translation from 256/1025 to 128 pwl points.
-+	 */
- 
--		while (i != opp110->regamma.hw_points_num + 1) {
--			rgb->r = translate_from_linear_space_ex(
--				coord_x->adjusted_x, &coeff, 0);
--			rgb->g = translate_from_linear_space_ex(
--				coord_x->adjusted_x, &coeff, 1);
--			rgb->b = translate_from_linear_space_ex(
--				coord_x->adjusted_x, &coeff, 2);
--
--			++coord_x;
--			++rgb;
--			++i;
--		}
--	} else {
-+	i = 0;
-+
-+	while (i != opp110->regamma.hw_points_num + 1) {
-+		rgb->r = translate_from_linear_space_ex(
-+			coord_x->adjusted_x, &coeff, 0);
-+		rgb->g = translate_from_linear_space_ex(
-+			coord_x->adjusted_x, &coeff, 1);
-+		rgb->b = translate_from_linear_space_ex(
-+			coord_x->adjusted_x, &coeff, 2);
-+
-+		++coord_x;
-+		++rgb;
-+		++i;
-+	}
-+
-+	if (params->regamma.features.bits.GAMMA_RAMP_ARRAY &&
-+			!params->regamma.features.bits.APPLY_DEGAMMA) {
- 		const uint32_t max_entries =
- 			RGB_256X3X16 + opp110->regamma.extra_points - 1;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0605-drm-amd-dal-pass-configuration-data-from-dc-to-dm.patch b/common/recipes-kernel/linux/files/0605-drm-amd-dal-pass-configuration-data-from-dc-to-dm.patch
deleted file mode 100644
index 7c0fb348..00000000
--- a/common/recipes-kernel/linux/files/0605-drm-amd-dal-pass-configuration-data-from-dc-to-dm.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From d66bfff0d2fddbb7af889e924288b4092ccac088 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 1 Dec 2015 16:59:23 -0500
-Subject: [PATCH 0605/1110] drm/amd/dal: pass configuration data from dc to dm
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    | 30 ++++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index e9308f3..94c8a38 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -181,6 +181,36 @@ bool dc_service_pp_apply_display_requirements(
- 		adev->pm.pm_display_cfg.nb_pstate_switch_disable =
- 			pp_display_cfg->nb_pstate_switch_disable;
- 
-+		adev->pm.pm_display_cfg.num_display =
-+				pp_display_cfg->display_count;
-+		adev->pm.pm_display_cfg.num_path_including_non_display =
-+				pp_display_cfg->display_count;
-+
-+		adev->pm.pm_display_cfg.min_core_set_clock =
-+				pp_display_cfg->min_engine_clock_khz/10;
-+		adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
-+				pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
-+		adev->pm.pm_display_cfg.min_mem_set_clock =
-+				pp_display_cfg->min_memory_clock_khz/10;
-+
-+		adev->pm.pm_display_cfg.multi_monitor_in_sync =
-+				pp_display_cfg->all_displays_in_sync;
-+		adev->pm.pm_display_cfg.min_vblank_time =
-+				pp_display_cfg->avail_mclk_switch_time_us;
-+
-+		adev->pm.pm_display_cfg.display_clk =
-+				pp_display_cfg->disp_clk_khz/10;
-+
-+		adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
-+				pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
-+
-+		adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
-+		adev->pm.pm_display_cfg.line_time_in_us =
-+				pp_display_cfg->line_time_in_us;
-+
-+		adev->pm.pm_display_cfg.crossfire_display_index = -1;
-+		adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
-+
- 		/* TODO: complete implementation of
- 		 * amd_powerplay_display_configuration_change().
- 		 * Follow example of:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0606-drm-amd-dal-Log-connector-signal-at-creation.patch b/common/recipes-kernel/linux/files/0606-drm-amd-dal-Log-connector-signal-at-creation.patch
deleted file mode 100644
index bc57099e..00000000
--- a/common/recipes-kernel/linux/files/0606-drm-amd-dal-Log-connector-signal-at-creation.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From e1d8a5f671bd8f6a20aac19e8c2cb43df7d14808 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 11 Dec 2015 09:19:36 -0500
-Subject: [PATCH 0606/1110] drm/amd/dal: Log connector signal at creation
-
-This will help us better understand what configuration
-QA used for testing when they give us a dmesg log.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 2f2800f..5890555 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -747,8 +747,10 @@ static bool construct(
- 	}
- 
- 	/* TODO: #DAL3 Implement id to str function.*/
--	LINK_INFO("Connector[%d] description:\n",
--			init_params->connector_index);
-+	LINK_INFO("Connector[%d] description:"
-+			"signal %d\n",
-+			init_params->connector_index,
-+			link->public.connector_signal);
- 
- 	link->connector = dal_connector_create(dc_ctx, as, link->link_id);
- 	if (NULL == link->connector) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0607-drm-amd-dal-share-initialization-between-connectors.patch b/common/recipes-kernel/linux/files/0607-drm-amd-dal-share-initialization-between-connectors.patch
deleted file mode 100644
index ff9eec50..00000000
--- a/common/recipes-kernel/linux/files/0607-drm-amd-dal-share-initialization-between-connectors.patch
+++ /dev/null
@@ -1,221 +0,0 @@
-From c0f9678f83fea7283f961c8853062637400b4693 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 10 Dec 2015 20:12:49 +0800
-Subject: [PATCH 0607/1110] drm/amd/dal: share initialization between
- connectors
-
-Also initialize DPMS to OFF state
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 37 +++++++---
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 82 +++++++++++++---------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |  7 ++
- 3 files changed, 84 insertions(+), 42 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index ba1c854..3246dcd 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -261,6 +261,7 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- {
- 	struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr);
- 	struct drm_device *dev = master->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
- 	struct amdgpu_connector *aconnector;
- 	struct drm_connector *connector;
- 
-@@ -272,21 +273,41 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	connector = &aconnector->base;
- 	aconnector->port = port;
- 	aconnector->mst_port = master;
--	aconnector->dc_link = master->dc_link;
--	aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
- 
--	sema_init(&aconnector->mst_sem, 1);
-+	if (drm_connector_init(
-+		dev,
-+		connector,
-+		&dm_dp_mst_connector_funcs,
-+		DRM_MODE_CONNECTOR_DisplayPort)) {
-+		kfree(aconnector);
-+		return NULL;
-+	}
-+	drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
- 
--	/* Initialize connector state before adding the connectror to drm and framebuffer lists */
--	amdgpu_dm_connector_funcs_reset(connector);
-+	amdgpu_dm_connector_init_helper(
-+		&adev->dm,
-+		aconnector,
-+		DRM_MODE_CONNECTOR_DisplayPort,
-+		master->dc_link,
-+		master->connector_id);
- 
--	drm_connector_init(dev, connector, &dm_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
--	drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
- 	aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
- 
--	drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
-+	/*
-+	 * TODO: understand why this one is needed
-+	 */
-+	drm_object_attach_property(
-+		&connector->base,
-+		dev->mode_config.path_property,
-+		0);
-+
- 	drm_mode_connector_set_path_property(connector, pathprop);
- 
-+	/*
-+	 * Initialize connector state before adding the connectror to drm and
-+	 * framebuffer lists
-+	 */
-+	amdgpu_dm_connector_funcs_reset(connector);
- 
- 	DRM_DEBUG_KMS(":%d\n", connector->base.id);
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index ea7a623..45a2a68 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1753,45 +1753,24 @@ int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
- 	return amdgpu_connector->num_modes;
- }
- 
--/* Note: this function assumes that dc_link_detect() was called for the
-- * dc_link which will be represented by this aconnector. */
--int amdgpu_dm_connector_init(
-+void amdgpu_dm_connector_init_helper(
- 	struct amdgpu_display_manager *dm,
- 	struct amdgpu_connector *aconnector,
--	uint32_t link_index,
--	struct amdgpu_encoder *aencoder)
-+	int connector_type,
-+	const struct dc_link *link,
-+	int link_index)
- {
--	int res, connector_type;
- 	struct amdgpu_device *adev = dm->ddev->dev_private;
--	struct dc *dc = dm->dc;
--	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
--
--	DRM_DEBUG_KMS("%s()\n", __func__);
--
--	connector_type = to_drm_connector_type(link->connector_signal);
--
--	res = drm_connector_init(
--			dm->ddev,
--			&aconnector->base,
--			&amdgpu_dm_connector_funcs,
--			connector_type);
--
--	if (res) {
--		DRM_ERROR("connector_init failed\n");
--		aconnector->connector_id = -1;
--		return res;
--	}
--
--	drm_connector_helper_add(
--			&aconnector->base,
--			&amdgpu_dm_connector_helper_funcs);
- 
- 	aconnector->connector_id = link_index;
- 	aconnector->dc_link = link;
- 	aconnector->base.interlace_allowed = true;
- 	aconnector->base.doublescan_allowed = true;
-+	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
- 	aconnector->hpd.hpd = link_index; /* maps to 'enum amdgpu_hpd_id' */
- 
-+
-+
- 	/*configure suport HPD hot plug connector_>polled default value is 0
- 	 * which means HPD hot plug not supported*/
- 	switch (connector_type) {
-@@ -1822,15 +1801,51 @@ int amdgpu_dm_connector_init(
- 				adev->mode_info.underscan_vborder_property,
- 				0);
- 
--	/* TODO: Don't do this manually anymore
--	aconnector->base.encoder = &aencoder->base;
--	*/
-+	sema_init(&aconnector->mst_sem, 1);
-+}
-+
-+/* Note: this function assumes that dc_link_detect() was called for the
-+ * dc_link which will be represented by this aconnector. */
-+int amdgpu_dm_connector_init(
-+	struct amdgpu_display_manager *dm,
-+	struct amdgpu_connector *aconnector,
-+	uint32_t link_index,
-+	struct amdgpu_encoder *aencoder)
-+{
-+	int res, connector_type;
-+	struct dc *dc = dm->dc;
-+	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
-+
-+	DRM_DEBUG_KMS("%s()\n", __func__);
-+
-+	connector_type = to_drm_connector_type(link->connector_signal);
-+
-+	res = drm_connector_init(
-+			dm->ddev,
-+			&aconnector->base,
-+			&amdgpu_dm_connector_funcs,
-+			connector_type);
-+
-+	if (res) {
-+		DRM_ERROR("connector_init failed\n");
-+		aconnector->connector_id = -1;
-+		return res;
-+	}
-+
-+	drm_connector_helper_add(
-+			&aconnector->base,
-+			&amdgpu_dm_connector_helper_funcs);
-+
-+	amdgpu_dm_connector_init_helper(
-+		dm,
-+		aconnector,
-+		connector_type,
-+		link,
-+		link_index);
- 
- 	drm_mode_connector_attach_encoder(
- 		&aconnector->base, &aencoder->base);
- 
--	/*drm_sysfs_connector_add(&dm_connector->base);*/
--
- 	drm_connector_register(&aconnector->base);
- 
- 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort)
-@@ -1856,7 +1871,6 @@ int amdgpu_dm_connector_init(
- 			dm->backlight_link = link;
- 	}
- #endif
--	sema_init(&aconnector->mst_sem, 1);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 0639732..1b8b3eb 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -85,6 +85,13 @@ int amdgpu_dm_connector_atomic_set_property(
- 
- int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
- 
-+void amdgpu_dm_connector_init_helper(
-+	struct amdgpu_display_manager *dm,
-+	struct amdgpu_connector *aconnector,
-+	int connector_type,
-+	const struct dc_link *link,
-+	int link_index);
-+
- extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
- 
- #endif		/* __AMDGPU_DM_TYPES_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0608-drm-amd-dal-use-DRM-helper-to-update-legacy-state.patch b/common/recipes-kernel/linux/files/0608-drm-amd-dal-use-DRM-helper-to-update-legacy-state.patch
deleted file mode 100644
index 405de584..00000000
--- a/common/recipes-kernel/linux/files/0608-drm-amd-dal-use-DRM-helper-to-update-legacy-state.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 5e17c458aedbc2ac66c987e2dda38e9321d2a6cc Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 10 Dec 2015 20:17:56 +0800
-Subject: [PATCH 0608/1110] drm/amd/dal: use DRM helper to update legacy state
-
-Although legacy state of DRM objects (e.g. crtc, connector etc.)
-should not be used by atomic code, DRM code still uses it to report
-information to userspace.
-
-Previously part of legacy state was updated by amdgpu atomic_commit.
-It was found that dpms state was not updated, and drm provides helper
-function to update legacy state.
-
-This change removes amdgpu atomic_commit code to update state and
-start to use DRM helper function for this.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 11 +++--------
- 1 file changed, 3 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 45a2a68..a9ff09d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2113,6 +2113,8 @@ int amdgpu_dm_atomic_commit(
- 	 * wait_for_fences(dev, state);
- 	 */
- 
-+	drm_atomic_helper_update_legacy_modeset_state(dev, state);
-+
- 	/* update changed items */
- 	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
- 		struct amdgpu_crtc *acrtc;
-@@ -2158,7 +2160,6 @@ int amdgpu_dm_atomic_commit(
- 		switch (action) {
- 		case DM_COMMIT_ACTION_DPMS_ON:
- 		case DM_COMMIT_ACTION_SET: {
--			const struct drm_connector_helper_funcs *connector_funcs;
- 			struct dc_target *new_target =
- 				create_target_for_sink(
- 					aconnector,
-@@ -2202,12 +2203,7 @@ int amdgpu_dm_atomic_commit(
- 
- 			acrtc->target = new_target;
- 			acrtc->enabled = true;
--			acrtc->base.enabled = true;
- 
--			connector_funcs = aconnector->base.helper_private;
--			aconnector->base.encoder =
--				connector_funcs->best_encoder(
--					&aconnector->base);
- 			down(&aconnector->mst_sem);
- 			break;
- 		}
-@@ -2225,8 +2221,7 @@ int amdgpu_dm_atomic_commit(
- 				dc_target_release(acrtc->target);
- 				acrtc->target = NULL;
- 				acrtc->enabled = false;
--				acrtc->base.enabled = false;
--				aconnector->base.encoder = NULL;
-+
- 				up(&aconnector->mst_sem);
- 			}
- 			break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0609-drm-amd-dal-split-selection-of-connector-in-commit.patch b/common/recipes-kernel/linux/files/0609-drm-amd-dal-split-selection-of-connector-in-commit.patch
deleted file mode 100644
index 7e7dbd26..00000000
--- a/common/recipes-kernel/linux/files/0609-drm-amd-dal-split-selection-of-connector-in-commit.patch
+++ /dev/null
@@ -1,131 +0,0 @@
-From c9ba7980b34bcfd93743b190c00ea8903122d198 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 10 Dec 2015 20:20:48 +0800
-Subject: [PATCH 0609/1110] drm/amd/dal: split selection of connector in commit
-
-During commit there could be situation when there are two connectors
-in state. For SET mode action new connector should be used.
-For RESET mode action old connector should be used.
-
-In old code there was a situation when OLD connector sink
-used for SET mode.
-
-Also it uses new and old connector to update MST semaphore properly
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 45 +++++++++++++---------
- 1 file changed, 26 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a9ff09d..633f0de 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2118,7 +2118,8 @@ int amdgpu_dm_atomic_commit(
- 	/* update changed items */
- 	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
- 		struct amdgpu_crtc *acrtc;
--		struct amdgpu_connector *aconnector = NULL;
-+		struct amdgpu_connector *aconnector_new = NULL;
-+		struct amdgpu_connector *aconnector_old = NULL;
- 		enum dm_commit_action action;
- 		struct drm_crtc_state *new_state = crtc->state;
- 		struct drm_connector *connector;
-@@ -2126,20 +2127,30 @@ int amdgpu_dm_atomic_commit(
- 
- 		acrtc = to_amdgpu_crtc(crtc);
- 
--		for_each_connector_in_state(state,
--				connector, old_con_state, j) {
-+		for_each_connector_in_state(
-+			state,
-+			connector,
-+			old_con_state,
-+			j) {
- 			if (connector->state->crtc == crtc) {
--				aconnector = to_amdgpu_connector(connector);
-+				aconnector_new = to_amdgpu_connector(connector);
- 				break;
- 			}
-+		}
- 
-+		for_each_connector_in_state(
-+			state,
-+			connector,
-+			old_con_state,
-+			j) {
- 			/*
--			 * this is the case when reset occur, connector is
--			 * removed from new crtc state. We need to update
--			 * connector state anyway. Access it from old_con_state
-+			 * this is the case when reset occur, connector
-+			 * is removed from new crtc state. We need to
-+			 * update connector state anyway. Access it from
-+			 * old_con_state
- 			 */
- 			if (old_con_state->crtc == crtc) {
--				aconnector = to_amdgpu_connector(connector);
-+				aconnector_old = to_amdgpu_connector(connector);
- 				break;
- 			}
- 		}
-@@ -2147,24 +2158,20 @@ int amdgpu_dm_atomic_commit(
- 		/* handles headless hotplug case, updating new_state and
- 		 * aconnector as needed
- 		 */
--		handle_headless_hotplug(acrtc, new_state, &aconnector);
-+		handle_headless_hotplug(acrtc, new_state, &aconnector_new);
- 
- 		action = get_dm_commit_action(new_state);
- 
--		if (!aconnector && action != DM_COMMIT_ACTION_NOTHING) {
--			DRM_ERROR("Can't find connector for crtc %d\n",
--							acrtc->crtc_id);
--			break;
--		}
--
- 		switch (action) {
- 		case DM_COMMIT_ACTION_DPMS_ON:
- 		case DM_COMMIT_ACTION_SET: {
- 			struct dc_target *new_target =
- 				create_target_for_sink(
--					aconnector,
-+					aconnector_new,
- 					&crtc->state->mode);
-+
- 			DRM_DEBUG_KMS("Atomic commit: SET.\n");
-+
- 			if (!new_target) {
- 				/*
- 				 * this could happen because of issues with
-@@ -2190,7 +2197,7 @@ int amdgpu_dm_atomic_commit(
- 				/* this is the update mode case */
- 				dc_target_release(acrtc->target);
- 				acrtc->target = NULL;
--				up(&aconnector->mst_sem);
-+				up(&aconnector_old->mst_sem);
- 			}
- 
- 			/*
-@@ -2204,7 +2211,7 @@ int amdgpu_dm_atomic_commit(
- 			acrtc->target = new_target;
- 			acrtc->enabled = true;
- 
--			down(&aconnector->mst_sem);
-+			down(&aconnector_new->mst_sem);
- 			break;
- 		}
- 
-@@ -2222,7 +2229,7 @@ int amdgpu_dm_atomic_commit(
- 				acrtc->target = NULL;
- 				acrtc->enabled = false;
- 
--				up(&aconnector->mst_sem);
-+				up(&aconnector_old->mst_sem);
- 			}
- 			break;
- 		} /* switch() */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0610-drm-amd-dal-clean-MST-payload-hw-table-on-update.patch b/common/recipes-kernel/linux/files/0610-drm-amd-dal-clean-MST-payload-hw-table-on-update.patch
deleted file mode 100644
index 986ce8cb..00000000
--- a/common/recipes-kernel/linux/files/0610-drm-amd-dal-clean-MST-payload-hw-table-on-update.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From 65612b6c62b3271dcbf8bb112d0da22291e53ed6 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 11 Dec 2015 20:12:41 +0800
-Subject: [PATCH 0610/1110] drm/amd/dal: clean MST payload hw table on update
-
-On each update of HW payloads table from SW it should be clean.
-Consider situation when configuration changes from 2 displays
-to 1. SW table contains 1 row. HW table contains 2 rows. Only 1st
-row updated.
-
-After this change HW table always consistent with SW
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 93 ++++++++++++++--------
- 1 file changed, 58 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 3d902f3..8ddccdf 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1637,17 +1637,22 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t value0;
--	uint32_t value1;
-+	uint32_t value0 = 0;
-+	uint32_t value1 = 0;
-+	uint32_t slots = 0;
-+	uint32_t src = 0;
- 	uint32_t retries = 0;
- 	struct core_stream *core_stream = NULL;
- 
-+
- 	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
- 
- 	/* --- Set MSE Stream Attribute -
- 	 * Setup VC Payload Table on Tx Side,
- 	 * Issue allocation change trigger
- 	 * to commit payload on both tx and rx side */
-+
-+	/* we should clean-up table each time */
- 	value0 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT0));
- 	value1 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT1));
- 
-@@ -1655,53 +1660,71 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		core_stream =
- 			DC_STREAM_TO_CORE(table->stream_allocations[0].stream);
- 
--		set_reg_field_value(
--			value0,
--			core_stream->stream_enc->id,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SRC0);
--
--		set_reg_field_value(
--			value0,
--			table->stream_allocations[0].slot_count,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SLOT_COUNT0);
-+		src = core_stream->stream_enc->id;
-+		slots = table->stream_allocations[0].slot_count;
-+	} else {
-+		src = 0;
-+		slots = 0;
- 	}
- 
-+	set_reg_field_value(
-+		value0,
-+		src,
-+		DP_MSE_SAT0,
-+		DP_MSE_SAT_SRC0);
-+
-+	set_reg_field_value(
-+		value0,
-+		slots,
-+		DP_MSE_SAT0,
-+		DP_MSE_SAT_SLOT_COUNT0);
-+
- 	if (table->stream_count >= 2) {
- 		core_stream =
- 			DC_STREAM_TO_CORE(table->stream_allocations[1].stream);
- 
--		set_reg_field_value(
--			value0,
--			core_stream->stream_enc->id,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SRC1);
--
--		set_reg_field_value(
--			value0,
--			table->stream_allocations[1].slot_count,
--			DP_MSE_SAT0,
--			DP_MSE_SAT_SLOT_COUNT1);
-+		src = core_stream->stream_enc->id;
-+		slots = table->stream_allocations[1].slot_count;
-+	} else {
-+		src = 0;
-+		slots = 0;
- 	}
- 
-+	set_reg_field_value(
-+		value0,
-+		src,
-+		DP_MSE_SAT0,
-+		DP_MSE_SAT_SRC1);
-+
-+	set_reg_field_value(
-+		value0,
-+		slots,
-+		DP_MSE_SAT0,
-+		DP_MSE_SAT_SLOT_COUNT1);
-+
- 	if (table->stream_count >= 3) {
- 		core_stream =
- 			DC_STREAM_TO_CORE(table->stream_allocations[2].stream);
- 
--		set_reg_field_value(
--			value1,
--			core_stream->stream_enc->id,
--			DP_MSE_SAT1,
--			DP_MSE_SAT_SRC2);
--
--		set_reg_field_value(
--			value1,
--			table->stream_allocations[2].slot_count,
--			DP_MSE_SAT1,
--			DP_MSE_SAT_SLOT_COUNT2);
-+		src = core_stream->stream_enc->id;
-+		slots = table->stream_allocations[2].slot_count;
-+	} else {
-+		src = 0;
-+		slots = 0;
- 	}
- 
-+	set_reg_field_value(
-+		value1,
-+		src,
-+		DP_MSE_SAT1,
-+		DP_MSE_SAT_SRC2);
-+
-+	set_reg_field_value(
-+		value1,
-+		slots,
-+		DP_MSE_SAT1,
-+		DP_MSE_SAT_SLOT_COUNT2);
-+
- 	/* update ASIC MSE stream allocation table */
- 	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT0), value0);
- 	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT1), value1);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0611-drm-amd-dal-remove-SW-payload-row-on-reset.patch b/common/recipes-kernel/linux/files/0611-drm-amd-dal-remove-SW-payload-row-on-reset.patch
deleted file mode 100644
index c5c3f196..00000000
--- a/common/recipes-kernel/linux/files/0611-drm-amd-dal-remove-SW-payload-row-on-reset.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 3c465d6c8a8ac98685575699b50964a8054e3a3b Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 11 Dec 2015 20:18:54 +0800
-Subject: [PATCH 0611/1110] drm/amd/dal: remove SW payload row on reset
-
-dc_helpers_dp_mst_write_payload_allocation_table required
-passed stream connector to have crtc. However during reset
-mode it does not have one as state got already updated.
-Also it is not used
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c | 4 ----
- 1 file changed, 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 87db164..f2d1dc8 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -187,10 +187,6 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	bool find_stream_for_sink;
- 
- 	aconnector = get_connector_for_sink(dev, stream->sink);
--	crtc = aconnector->base.state->crtc;
--
--	if (!crtc)
--		return false;
- 
- 	if (!aconnector->mst_port)
- 		return false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0612-drm-amd-dal-do-not-clean-dc_link-on-MST-disconnect.patch b/common/recipes-kernel/linux/files/0612-drm-amd-dal-do-not-clean-dc_link-on-MST-disconnect.patch
deleted file mode 100644
index c614fd29..00000000
--- a/common/recipes-kernel/linux/files/0612-drm-amd-dal-do-not-clean-dc_link-on-MST-disconnect.patch
+++ /dev/null
@@ -1,119 +0,0 @@
-From 7cc988ac024ed34c946722e036eec93f117069bd Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 11 Dec 2015 20:28:48 +0800
-Subject: [PATCH 0612/1110] drm/amd/dal: do not clean dc_link on MST disconnect
-
-This change restores previous behaviour, because mapping between
-stream and connector is needed till reset mode, where it is accessed
-for payload allocation.
-
-We currently have the following references to dc_sink:
-
-1. Hard reference in stream. Cleaned-up when target destroyed on reset mode;
-2. Hard reference in link. Clean-up on HPD disconnect event;
-3. Weak reference in aconnector. Weak means it does not controlled by counter.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 37 ++++++++++++----------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 19 ++---------
- 2 files changed, 23 insertions(+), 33 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 3246dcd..f2926ff 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -75,8 +75,7 @@ dm_dp_mst_detect(struct drm_connector *connector, bool force)
- 			aconnector->port);
- 
- 	if (status == connector_status_disconnected && aconnector->dc_sink) {
--		dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
--		aconnector->dc_sink = NULL;
-+		aconnector->edid = NULL;
- 	}
- 
- 	return status;
-@@ -170,25 +169,31 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
- 
- 	flush_work(&master->mst_mgr.work);
- 
--	edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, aconnector->port);
-+	if (!aconnector->edid) {
-+		edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, aconnector->port);
- 
--	if (!edid) {
--		drm_mode_connector_update_edid_property(
--			&aconnector->base,
--			NULL);
-+		if (!edid) {
-+			drm_mode_connector_update_edid_property(
-+				&aconnector->base,
-+				NULL);
- 
--		return ret;
--	}
-+			return ret;
-+		}
- 
--	aconnector->edid = edid;
-+		aconnector->edid = edid;
- 
--	if (!aconnector->dc_sink) {
--			sink = dm_dp_mst_add_mst_sink(
-+		if (aconnector->dc_sink)
-+			dc_link_remove_sink(
- 				aconnector->dc_link,
--				(uint8_t *)edid,
--				(edid->extensions + 1) * EDID_LENGTH);
--				aconnector->dc_sink = sink;
--	}
-+				aconnector->dc_sink);
-+
-+		sink = dm_dp_mst_add_mst_sink(
-+			aconnector->dc_link,
-+			(uint8_t *)edid,
-+			(edid->extensions + 1) * EDID_LENGTH);
-+		aconnector->dc_sink = sink;
-+	} else
-+		edid = aconnector->edid;
- 
- 	DRM_DEBUG_KMS("edid retrieved %p\n", edid);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 5890555..add76ca 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -639,27 +639,12 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		switch (link->public.connector_signal) {
- 		case SIGNAL_TYPE_DISPLAY_PORT:
- 			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
--			/*
--			 * in this case sinks would be removed in outer level
--			 */
--
--			/*
--			 * TODO: this is the only way to understand that link
--			 * was in mst mode. Proposal for future to add
--			 * additional field to link that will show actual state.
--			 *
--			 * For the change: for mst we create sink outside, and
--			 * should remove them in the same place
--			 */
--			if (link->public.sink_count == 1 &&
--				link->public.sink[0]->sink_signal !=
--					SIGNAL_TYPE_DISPLAY_PORT_MST)
--				link_disconnect_all_sinks(link);
- 			break;
- 		default:
--			link_disconnect_all_sinks(link);
- 			break;
- 		}
-+
-+		link_disconnect_all_sinks(link);
- 	}
- 
- 	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0613-drm-amd-dal-Integrate-amd_powerplay_get_clock_by_typ.patch b/common/recipes-kernel/linux/files/0613-drm-amd-dal-Integrate-amd_powerplay_get_clock_by_typ.patch
deleted file mode 100644
index a2e8e7d3..00000000
--- a/common/recipes-kernel/linux/files/0613-drm-amd-dal-Integrate-amd_powerplay_get_clock_by_typ.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From 16c580abc2cbfc2a6dedecd88773bce4c0611a12 Mon Sep 17 00:00:00 2001
-From: "Signed-off-by: David Rokhvarg" <David.Rokhvarg@amd.com>
-Date: Thu, 3 Mar 2016 17:32:18 -0500
-Subject: [PATCH 0613/1110] drm/amd/dal: Integrate
- amd_powerplay_get_clock_by_type() into DM.
-
-This replaces hardcoded values by PPLib values.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    | 155 +++++++++++++++++----
- drivers/gpu/drm/amd/dal/dc/dc_services.h           |   8 +-
- 2 files changed, 133 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index 94c8a38..12b9475 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -258,34 +258,24 @@ bool dc_service_get_system_clocks_range(
- 	return true;
- }
- 
--
--bool dc_service_pp_get_clock_levels_by_type(
--		const struct dc_context *ctx,
-+static void get_default_clock_levels(
- 		enum dc_pp_clock_type clk_type,
- 		struct dc_pp_clock_levels *clks)
- {
--/*
-- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if(amd_powerplay_get_clocks_by_type(adev->powerplay.pp_handle,
--		(int)clk_type, (void *)clks) == fail
--		PPlib return clocks in tens of kHz
--		divide by 10 & push to the clks which kHz
--#endif
--*/
--	uint32_t disp_clks_in_khz[8] = {
--	300000, 411430, 480000, 533340, 626090, 626090, 626090, 626090 };
--	uint32_t sclks_in_khz[8] = {
--	200000, 266670, 342860, 411430, 450000, 514290, 576000, 626090 };
--	uint32_t mclks_in_khz[8] = { 333000, 800000 };
-+	uint32_t disp_clks_in_khz[6] = {
-+			300000, 400000, 496560, 626090, 685720, 757900 };
-+	uint32_t sclks_in_khz[6] = {
-+			300000, 360000, 423530, 514290, 626090, 720000 };
-+	uint32_t mclks_in_khz[2] = { 333000, 800000 };
- 
- 	switch (clk_type) {
- 	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
--		clks->num_levels = 8;
-+		clks->num_levels = 6;
- 		dc_service_memmove(clks->clocks_in_khz, disp_clks_in_khz,
- 				sizeof(disp_clks_in_khz));
- 		break;
- 	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
--		clks->num_levels = 8;
-+		clks->num_levels = 6;
- 		dc_service_memmove(clks->clocks_in_khz, sclks_in_khz,
- 				sizeof(sclks_in_khz));
- 		break;
-@@ -295,26 +285,135 @@ bool dc_service_pp_get_clock_levels_by_type(
- 				sizeof(mclks_in_khz));
- 		break;
- 	default:
--		return false;
-+		clks->num_levels = 0;
-+		break;
- 	}
-+}
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (clk_type ==  DC_PP_CLOCK_TYPE_ENGINE_CLK ||
--		clk_type ==  DC_PP_CLOCK_TYPE_DISPLAY_CLK) {
-+static enum amd_pp_clock_type dc_to_pp_clock_type(
-+		enum dc_pp_clock_type dc_pp_clk_type)
-+{
-+	enum amd_pp_clock_type amd_pp_clk_type = 0;
-+
-+	switch (dc_pp_clk_type) {
-+	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		amd_pp_clk_type = amd_pp_disp_clock;
-+		break;
-+	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+		amd_pp_clk_type = amd_pp_sys_clock;
-+		break;
-+	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+		amd_pp_clk_type = amd_pp_mem_clock;
-+		break;
-+	default:
-+		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
-+				dc_pp_clk_type);
-+		break;
-+	}
- 
--		struct amdgpu_device *adev = ctx->driver_context;
--		struct amd_pp_dal_clock_info info = {0};
-+	return amd_pp_clk_type;
-+}
-+
-+static void pp_to_dc_clock_levels(
-+		const struct amd_pp_clocks *pp_clks,
-+		struct dc_pp_clock_levels *dc_clks,
-+		enum dc_pp_clock_type dc_clk_type)
-+{
-+	uint32_t i;
- 
--		if (0 == amd_powerplay_get_display_power_level(
--				adev->powerplay.pp_handle, &info) &&
--				info.level < clks->num_levels) {
--		/*if the max possible power level less then use smaller*/
--			clks->num_levels = info.level;
-+	if (pp_clks->count > DC_PP_MAX_CLOCK_LEVELS) {
-+		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
-+				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
-+				pp_clks->count,
-+				DC_PP_MAX_CLOCK_LEVELS);
-+
-+		dc_clks->num_levels = DC_PP_MAX_CLOCK_LEVELS;
-+	} else
-+		dc_clks->num_levels = pp_clks->count;
-+
-+	DRM_INFO("DM_PPLIB: values for %s clock\n",
-+			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
-+
-+	for (i = 0; i < dc_clks->num_levels; i++) {
-+		DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
-+		/* translate 10kHz to kHz */
-+		dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
-+	}
-+}
-+#endif
-+
-+bool dc_service_pp_get_clock_levels_by_type(
-+		const struct dc_context *ctx,
-+		enum dc_pp_clock_type clk_type,
-+		struct dc_pp_clock_levels *dc_clks)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	void *pp_handle = adev->powerplay.pp_handle;
-+	struct amd_pp_clocks pp_clks = { 0 };
-+	struct amd_pp_simple_clock_info validation_clks = { 0 };
-+	uint32_t i;
-+
-+	if (amd_powerplay_get_clock_by_type(pp_handle,
-+			dc_to_pp_clock_type(clk_type), &pp_clks)) {
-+		/* Error in pplib. Provide default values. */
-+		get_default_clock_levels(clk_type, dc_clks);
-+		return true;
-+	}
-+
-+	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
-+
-+	if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
-+			&validation_clks)) {
-+		/* Error in pplib. Provide default values. */
-+		DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
-+		validation_clks.engine_max_clock = 72000;
-+		validation_clks.memory_max_clock = 80000;
-+		validation_clks.level = 0;
-+	}
-+
-+	DRM_INFO("DM_PPLIB: Validation clocks:\n");
-+	DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
-+			validation_clks.engine_max_clock);
-+	DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
-+			validation_clks.memory_max_clock);
-+	DRM_INFO("DM_PPLIB:    level           : %d\n",
-+			validation_clks.level);
-+
-+	/* Translate 10 kHz to kHz. */
-+	validation_clks.engine_max_clock *= 10;
-+	validation_clks.memory_max_clock *= 10;
-+
-+	/* Determine the highest non-boosted level from the Validation Clocks */
-+	if (clk_type == DC_PP_CLOCK_TYPE_ENGINE_CLK) {
-+		for (i = 0; i < dc_clks->num_levels; i++) {
-+			if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
-+				/* This clock is higher the validation clock.
-+				 * Than means the previous one is the highest
-+				 * non-boosted one. */
-+				DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
-+						dc_clks->num_levels, i + 1);
-+				dc_clks->num_levels = i;
-+				break;
-+			}
-+		}
-+	} else if (clk_type == DC_PP_CLOCK_TYPE_MEMORY_CLK) {
-+		for (i = 0; i < dc_clks->num_levels; i++) {
-+			if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
-+				DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
-+						dc_clks->num_levels, i + 1);
-+				dc_clks->num_levels = i;
-+				break;
-+			}
- 		}
- 	}
-+#else
-+	get_default_clock_levels(clk_type, dc_clks);
- #endif
- 	return true;
- }
-+
- /**** end of power component interfaces ****/
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index edb558d..907b415 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -105,7 +105,6 @@ struct dc_pp_display_configuration {
- 	bool cpu_pstate_disable;
- 	uint32_t cpu_pstate_separation_time;
- 
--	/* 10khz steps */
- 	uint32_t min_memory_clock_khz;
- 	uint32_t min_engine_clock_khz;
- 	uint32_t min_engine_clock_deep_sleep_khz;
-@@ -167,10 +166,15 @@ bool dc_service_get_system_clocks_range(
- 
- enum dc_pp_clock_type {
- 	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
--	DC_PP_CLOCK_TYPE_ENGINE_CLK,
-+	DC_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
- 	DC_PP_CLOCK_TYPE_MEMORY_CLK
- };
- 
-+#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
-+	(clk_type) == DC_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
-+	(clk_type) == DC_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-+	(clk_type) == DC_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
-+
- #define DC_PP_MAX_CLOCK_LEVELS 8
- 
- struct dc_pp_clock_levels {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0614-drm-amd-dal-check-stream-on-payload-table-update.patch b/common/recipes-kernel/linux/files/0614-drm-amd-dal-check-stream-on-payload-table-update.patch
deleted file mode 100644
index 5e2e47ef..00000000
--- a/common/recipes-kernel/linux/files/0614-drm-amd-dal-check-stream-on-payload-table-update.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 07acd42b825ae77bcd0d41c0179b9eada8db54dd Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 14 Dec 2015 19:04:17 +0800
-Subject: [PATCH 0614/1110] drm/amd/dal: check stream on payload table update
-
-There is a situation when drm crtc moved from one connector
-to another, and MST connector can lack DC target for one
-commit. It should be guarded both in DM and DC
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  |  8 ++++
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 47 ++++++++++++++--------
- 2 files changed, 38 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index f2d1dc8..0230ee9 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -311,6 +311,14 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 			 * crtc -> target -> stream -> sink
- 			 */
- 			crtc = aconnector->base.state->crtc;
-+
-+			/*
-+			 * this situation can happen when crtc moved from one
-+			 * connector to another for any reason
-+			 */
-+			if (!crtc)
-+				continue;
-+
- 			amdgpu_crtc = to_amdgpu_crtc(crtc);
- 			dc_target = amdgpu_crtc->target;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 8ddccdf..d71efa9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1630,6 +1630,24 @@ void dce110_link_encoder_set_dp_phy_pattern(
- 	}
- }
- 
-+static void fill_stream_allocation_row_info(
-+	const struct dp_mst_stream_allocation *stream_allocation,
-+	uint32_t *src,
-+	uint32_t *slots)
-+{
-+	const struct dc_stream *dc_stream = stream_allocation->stream;
-+	struct core_stream *core_stream;
-+
-+	if (dc_stream) {
-+		core_stream = DC_STREAM_TO_CORE(dc_stream);
-+		*src = core_stream->stream_enc->id;
-+		*slots = stream_allocation->slot_count;
-+	} else {
-+		*src = 0;
-+		*slots = 0;
-+	}
-+}
-+
- /* programs DP MST VC payload allocation */
- void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
-@@ -1642,8 +1660,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	uint32_t slots = 0;
- 	uint32_t src = 0;
- 	uint32_t retries = 0;
--	struct core_stream *core_stream = NULL;
--
- 
- 	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
- 
-@@ -1657,11 +1673,10 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	value1 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT1));
- 
- 	if (table->stream_count >= 1) {
--		core_stream =
--			DC_STREAM_TO_CORE(table->stream_allocations[0].stream);
--
--		src = core_stream->stream_enc->id;
--		slots = table->stream_allocations[0].slot_count;
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[0],
-+			&src,
-+			&slots);
- 	} else {
- 		src = 0;
- 		slots = 0;
-@@ -1680,11 +1695,10 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_SLOT_COUNT0);
- 
- 	if (table->stream_count >= 2) {
--		core_stream =
--			DC_STREAM_TO_CORE(table->stream_allocations[1].stream);
--
--		src = core_stream->stream_enc->id;
--		slots = table->stream_allocations[1].slot_count;
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[1],
-+			&src,
-+			&slots);
- 	} else {
- 		src = 0;
- 		slots = 0;
-@@ -1703,11 +1717,10 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_SLOT_COUNT1);
- 
- 	if (table->stream_count >= 3) {
--		core_stream =
--			DC_STREAM_TO_CORE(table->stream_allocations[2].stream);
--
--		src = core_stream->stream_enc->id;
--		slots = table->stream_allocations[2].slot_count;
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[2],
-+			&src,
-+			&slots);
- 	} else {
- 		src = 0;
- 		slots = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0615-drm-amd-dal-validate-MST-connector-modes.patch b/common/recipes-kernel/linux/files/0615-drm-amd-dal-validate-MST-connector-modes.patch
deleted file mode 100644
index 56f36226..00000000
--- a/common/recipes-kernel/linux/files/0615-drm-amd-dal-validate-MST-connector-modes.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 68bcc74a6347c314d95b61240a1849868d021214 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 14 Dec 2015 19:08:47 +0800
-Subject: [PATCH 0615/1110] drm/amd/dal: validate MST connector modes
-
-Same validation should be applied for MST connector,
-as for regular one.
-
-In this change default validation function is exposed
-globally and used for MST connector
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 9 +--------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c     | 5 +++--
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h     | 4 ++++
- 3 files changed, 8 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index f2926ff..fb71d88 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -208,13 +208,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
- 	return ret;
- }
- 
--static enum drm_mode_status
--dm_dp_mst_mode_valid(struct drm_connector *connector,
--			struct drm_display_mode *mode)
--{
--	return MODE_OK;
--}
--
- static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector)
- {
- 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
-@@ -224,7 +217,7 @@ static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector)
- 
- static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
- 	.get_modes = dm_dp_mst_get_modes,
--	.mode_valid = dm_dp_mst_mode_valid,
-+	.mode_valid = amdgpu_dm_connector_mode_valid,
- 	.best_encoder = dm_mst_best_encoder,
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 633f0de..fff17cd 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1221,7 +1221,8 @@ static int get_modes(struct drm_connector *connector)
- 	return amdgpu_connector->num_modes;
- }
- 
--static int mode_valid(struct drm_connector *connector,
-+int amdgpu_dm_connector_mode_valid(
-+		struct drm_connector *connector,
- 		struct drm_display_mode *mode)
- {
- 	int result = MODE_ERROR;
-@@ -1286,7 +1287,7 @@ amdgpu_dm_connector_helper_funcs = {
- 	* in get_modes call back, not just return the modes count
- 	*/
- 	.get_modes = get_modes,
--	.mode_valid = mode_valid,
-+	.mode_valid = amdgpu_dm_connector_mode_valid,
- 	.best_encoder = best_encoder
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 1b8b3eb..5d1152e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -92,6 +92,10 @@ void amdgpu_dm_connector_init_helper(
- 	const struct dc_link *link,
- 	int link_index);
- 
-+int amdgpu_dm_connector_mode_valid(
-+	struct drm_connector *connector,
-+	struct drm_display_mode *mode);
-+
- extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
- 
- #endif		/* __AMDGPU_DM_TYPES_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0616-drm-amd-dal-clean-up-MST-sem-usage.patch b/common/recipes-kernel/linux/files/0616-drm-amd-dal-clean-up-MST-sem-usage.patch
deleted file mode 100644
index b06e3c13..00000000
--- a/common/recipes-kernel/linux/files/0616-drm-amd-dal-clean-up-MST-sem-usage.patch
+++ /dev/null
@@ -1,153 +0,0 @@
-From f6b6c40260c9fda070dcfd495d46ca7cd49a7cef Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 14 Dec 2015 19:13:28 +0800
-Subject: [PATCH 0616/1110] drm/amd/dal: clean-up MST sem usage
-
-In previous implementation semaphore update was
-done in the same loop as crtc. It was dependent
-on crtc order and could lead to dead-lock.
-
-Consider the following sitatuation, crtc is moved
-from one connector to another.
-
-Initial state:
-CRTC1 - CONNECTOR1
-CRTC2 - CONNECTOR2
-
-CONNECTOR1 got disconnected
-
-Set mode received to use CRTC1 on CONNECTOR2
-In state we have both connectors and crtcs,
-added as affected.
-First would be set on CRTC1, and then reset on CRTC2.
-And this will deadlock.
-
-This issue addressed by the current change. Also
-now all semaphore management done in one place.
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 51 +++++++++++-----------
- 1 file changed, 25 insertions(+), 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index fff17cd..326242f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2071,6 +2071,25 @@ static void handle_headless_hotplug(
- 	}
- }
- 
-+static void update_connector_sem_state(struct drm_atomic_state *state)
-+{
-+	struct drm_connector *connector;
-+	struct drm_connector_state *old_con_state;
-+	struct amdgpu_connector *aconnector = NULL;
-+	int i;
-+
-+	for_each_connector_in_state(state, connector, old_con_state, i) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (old_con_state->crtc) {
-+			if (!connector->state->crtc)
-+				up(&aconnector->mst_sem);
-+		} else {
-+			if (connector->state->crtc)
-+				down(&aconnector->mst_sem);
-+		}
-+	}
-+}
-+
- int amdgpu_dm_atomic_commit(
- 	struct drm_device *dev,
- 	struct drm_atomic_state *state,
-@@ -2119,8 +2138,7 @@ int amdgpu_dm_atomic_commit(
- 	/* update changed items */
- 	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
- 		struct amdgpu_crtc *acrtc;
--		struct amdgpu_connector *aconnector_new = NULL;
--		struct amdgpu_connector *aconnector_old = NULL;
-+		struct amdgpu_connector *aconnector = NULL;
- 		enum dm_commit_action action;
- 		struct drm_crtc_state *new_state = crtc->state;
- 		struct drm_connector *connector;
-@@ -2134,24 +2152,7 @@ int amdgpu_dm_atomic_commit(
- 			old_con_state,
- 			j) {
- 			if (connector->state->crtc == crtc) {
--				aconnector_new = to_amdgpu_connector(connector);
--				break;
--			}
--		}
--
--		for_each_connector_in_state(
--			state,
--			connector,
--			old_con_state,
--			j) {
--			/*
--			 * this is the case when reset occur, connector
--			 * is removed from new crtc state. We need to
--			 * update connector state anyway. Access it from
--			 * old_con_state
--			 */
--			if (old_con_state->crtc == crtc) {
--				aconnector_old = to_amdgpu_connector(connector);
-+				aconnector = to_amdgpu_connector(connector);
- 				break;
- 			}
- 		}
-@@ -2159,7 +2160,7 @@ int amdgpu_dm_atomic_commit(
- 		/* handles headless hotplug case, updating new_state and
- 		 * aconnector as needed
- 		 */
--		handle_headless_hotplug(acrtc, new_state, &aconnector_new);
-+		handle_headless_hotplug(acrtc, new_state, &aconnector);
- 
- 		action = get_dm_commit_action(new_state);
- 
-@@ -2168,7 +2169,7 @@ int amdgpu_dm_atomic_commit(
- 		case DM_COMMIT_ACTION_SET: {
- 			struct dc_target *new_target =
- 				create_target_for_sink(
--					aconnector_new,
-+					aconnector,
- 					&crtc->state->mode);
- 
- 			DRM_DEBUG_KMS("Atomic commit: SET.\n");
-@@ -2198,7 +2199,6 @@ int amdgpu_dm_atomic_commit(
- 				/* this is the update mode case */
- 				dc_target_release(acrtc->target);
- 				acrtc->target = NULL;
--				up(&aconnector_old->mst_sem);
- 			}
- 
- 			/*
-@@ -2212,7 +2212,6 @@ int amdgpu_dm_atomic_commit(
- 			acrtc->target = new_target;
- 			acrtc->enabled = true;
- 
--			down(&aconnector_new->mst_sem);
- 			break;
- 		}
- 
-@@ -2229,13 +2228,13 @@ int amdgpu_dm_atomic_commit(
- 				dc_target_release(acrtc->target);
- 				acrtc->target = NULL;
- 				acrtc->enabled = false;
--
--				up(&aconnector_old->mst_sem);
- 			}
- 			break;
- 		} /* switch() */
- 	} /* for_each_crtc_in_state() */
- 
-+	update_connector_sem_state(state);
-+
- 	commit_targets_count = 0;
- 
- 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0617-drm-amd-dal-guard-drm-mst-manager-usage.patch b/common/recipes-kernel/linux/files/0617-drm-amd-dal-guard-drm-mst-manager-usage.patch
deleted file mode 100644
index 77d6d23a..00000000
--- a/common/recipes-kernel/linux/files/0617-drm-amd-dal-guard-drm-mst-manager-usage.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 8e6c227f5d427aa1409515d1804a5c39de5995f8 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 14 Dec 2015 19:22:38 +0800
-Subject: [PATCH 0617/1110] drm/amd/dal: guard drm mst manager usage
-
-In case mst branch got disconnected, and mst manager
-is not active, we should not call its functions.
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 0230ee9..ddc40c9 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -192,6 +192,10 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		return false;
- 
- 	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
- 	mst_port = aconnector->port;
- 
- 	if (enable) {
-@@ -379,6 +383,9 @@ bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 
- 	mst_mgr = &aconnector->mst_port->mst_mgr;
- 
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
- 	ret = drm_dp_check_act_status(mst_mgr);
- 
- 	if (ret)
-@@ -408,6 +415,9 @@ bool dc_helpers_dp_mst_send_payload_allocation(
- 
- 	mst_mgr = &aconnector->mst_port->mst_mgr;
- 
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
- 	ret = drm_dp_update_payload_part2(mst_mgr);
- 
- 	if (ret)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0618-drm-amd-dal-Validate-required-clocks-against-PPLib-V.patch b/common/recipes-kernel/linux/files/0618-drm-amd-dal-Validate-required-clocks-against-PPLib-V.patch
deleted file mode 100644
index d3e98541..00000000
--- a/common/recipes-kernel/linux/files/0618-drm-amd-dal-Validate-required-clocks-against-PPLib-V.patch
+++ /dev/null
@@ -1,141 +0,0 @@
-From dbea428ece2b816e0b5957956258631adabdc83d Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 10 Dec 2015 16:42:09 -0500
-Subject: [PATCH 0618/1110] drm/amd/dal: Validate required clocks against PPLib
- Validation clocks.
-
-This replaces hardcoded values with values from PPLib (used during Mode
-validation).
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 26 +++++++++++++++++++++-
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        |  5 +++++
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 10 ---------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  8 -------
- drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h          |  2 ++
- 5 files changed, 32 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 2b54eb6..6fc1ee6 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3253,6 +3253,29 @@ void bw_calcs_init(struct bw_calcs_input_dceip *bw_dceip,
- }
- 
- /**
-+ * Compare calculated (required) clocks against the clocks available at
-+ * maximum voltage (max Performance Level).
-+ */
-+static bool is_display_configuration_supported(
-+	const struct bw_calcs_input_vbios *vbios,
-+	const struct bw_calcs_output *calcs_output)
-+{
-+	uint32_t int_max_clk;
-+
-+	int_max_clk = fixed_to_int(vbios->high_voltage_max_dispclk_mhz);
-+	int_max_clk *= 1000; /* MHz to kHz */
-+	if (calcs_output->dispclk_khz > int_max_clk)
-+		return false;
-+
-+	int_max_clk = fixed_to_int(vbios->high_sclk_mhz);
-+	int_max_clk *= 1000; /* MHz to kHz */
-+	if (calcs_output->required_sclk > int_max_clk)
-+		return false;
-+
-+	return true;
-+}
-+
-+/**
-  * Return:
-  *	true -	Display(s) configuration supported.
-  *		In this case 'calcs_output' contains data for HW programming
-@@ -3482,5 +3505,6 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 
- 	dc_service_free(ctx, bw_data_internal);
- 	dc_service_free(ctx, bw_results_internal);
--	return true;
-+
-+	return is_display_configuration_supported(vbios, calcs_output);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index 646fafe..e1dd610 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -76,6 +76,11 @@ struct bw_fixed int_to_fixed(int64_t value)
- 	return res;
- }
- 
-+uint32_t fixed_to_int(struct bw_fixed value)
-+{
-+	return GET_INTEGER_PART(value.value);
-+}
-+
- struct bw_fixed frc_to_fixed(int64_t numerator, int64_t denominator)
- {
- 	struct bw_fixed res;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index a20a5ef..3284fda 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -264,16 +264,6 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			clks.clocks_in_khz[0], 1000);
- 	dc->bw_vbios.high_yclk_mhz = frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	return;
--
--	/* on CZ Gardenia from PPLib we get:
--	 * clk_range.max_mclk:80000
--	 * clk_range.min_mclk:80000
--	 * clk_range.max_sclk:80000
--	 * clk_range.min_sclk:30000 */
--
--	/* The values for calcs are stored in units of MHz, so for example
--	 * 80000 will be stored as 800. */
- }
- 
- static bool construct(struct dc *dc, const struct dal_init_data *init_params)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 400271e..afe54c3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -47,9 +47,6 @@ enum dce110_clk_src_array_id {
- 	DCE110_CLK_SRC_TOTAL
- };
- 
--#define DCE110_MAX_DISPCLK 643000
--#define DCE110_MAX_SCLK 626000
--
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -558,11 +555,6 @@ enum dc_status dce110_validate_bandwidth(
- 	else
- 		result =  DC_OK;
- 
--
--	if (context->bw_results.dispclk_khz > DCE110_MAX_DISPCLK
--		|| context->bw_results.required_sclk > DCE110_MAX_SCLK)
--		result =  DC_FAIL_BANDWIDTH_VALIDATE;
--
- 	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
- 		dal_logger_write(dc->ctx->logger,
- 			LOG_MAJOR_BWM,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-index 254cf76..cd0c889 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-@@ -36,6 +36,8 @@ struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed
- 
- struct bw_fixed int_to_fixed(int64_t value);
- 
-+uint32_t fixed_to_int(struct bw_fixed value);
-+
- struct bw_fixed frc_to_fixed(int64_t num, int64_t denum);
- 
- struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0619-drm-amd-dal-Prepare-bring-up-off-next-ASIC-generatio.patch b/common/recipes-kernel/linux/files/0619-drm-amd-dal-Prepare-bring-up-off-next-ASIC-generatio.patch
deleted file mode 100644
index f1a31bfd..00000000
--- a/common/recipes-kernel/linux/files/0619-drm-amd-dal-Prepare-bring-up-off-next-ASIC-generatio.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 3b8139200a5a7b4b86616a546d3cd6dc49177b36 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Tue, 8 Dec 2015 14:22:41 -0500
-Subject: [PATCH 0619/1110] drm/amd/dal: Prepare bring up off next ASIC
- generation
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index c686cc8..87fc14b 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -2772,7 +2772,7 @@ static enum bp_result enable_disp_power_gating_v2_1(
-  ********************************************************************************
-  *******************************************************************************/
- #ifdef LATEST_ATOM_BIOS_SUPPORT
--enum bp_result set_dce_clock_v2_1(
-+static enum bp_result set_dce_clock_v2_1(
- 	struct bios_parser *bp,
- 	struct bp_set_dce_clock_parameters *bp_params);
- #endif
-@@ -2801,11 +2801,10 @@ static enum bp_result set_dce_clock_v2_1(
- 	SET_DCE_CLOCK_PS_ALLOCATION_V2_1 params;
- 	uint32_t atom_pll_id;
- 	uint32_t atom_clock_type;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
- 
- 	dc_service_memset(&params, 0, sizeof(params));
- 
--	const struct command_table_helper *cmd = bp->cmd_helper;
--
- 	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
- 			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
- 		return BP_RESULT_BADINPUT;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0620-drm-amd-dal-adjust-DVI-signal-type-based-on-pixel-cl.patch b/common/recipes-kernel/linux/files/0620-drm-amd-dal-adjust-DVI-signal-type-based-on-pixel-cl.patch
deleted file mode 100644
index 5cd38d1e..00000000
--- a/common/recipes-kernel/linux/files/0620-drm-amd-dal-adjust-DVI-signal-type-based-on-pixel-cl.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 74c3a774117be295931635fea069402a0a50df47 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Tue, 15 Dec 2015 13:59:37 -0500
-Subject: [PATCH 0620/1110] drm/amd/dal: adjust DVI signal type based on pixel
- clk
-
-In case of asic supporting dual link DVI, sigal type should
-be adjusted based on mode timing pixel clock, otherwise timing
-on panel may be wrong.
-Solution:
-In case of DVI, Check mode timing pixel clock before assign
-signal type from dc_sink to stream.
-If pixel clock more than 165Mhz, consider it as dual link,
-otherwise, single link.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce_base/dce_base_resource.c    | 27 ++++++++++++++++++++--
- 1 file changed, 25 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-index ba74ff5..8996475 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -33,6 +33,9 @@
- 
- #include "resource.h"
- 
-+/* Maximum TMDS single link pixel clock 165MHz */
-+#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
-+
- static void attach_stream_to_controller(
- 		struct resource_context *res_ctx,
- 		struct core_stream *stream)
-@@ -142,6 +145,26 @@ static bool check_timing_change(struct core_stream *cur_stream,
- 					&new_stream->public.timing);
- }
- 
-+static void set_stream_signal(struct core_stream *stream)
-+{
-+	struct dc_sink *dc_sink = (struct dc_sink *)stream->public.sink;
-+
-+	/* For asic supports dual link DVI, we should adjust signal type
-+	 * based on timing pixel clock. If pixel clock more than 165Mhz,
-+	 * signal is dual link, otherwise, single link.
-+	 */
-+	if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
-+			dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK) {
-+		if (stream->public.timing.pix_clk_khz >
-+			TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
-+			dc_sink->sink_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		else
-+			dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	}
-+
-+	stream->signal = dc_sink->sink_signal;
-+}
-+
- enum dc_status dce_base_map_resources(
- 		const struct dc *dc,
- 		struct validate_context *context)
-@@ -207,8 +230,8 @@ enum dc_status dce_base_map_resources(
- 			set_stream_engine_in_use(
- 					&context->res_ctx,
- 					stream->stream_enc);
--			stream->signal =
--				stream->sink->public.sink_signal;
-+
-+			set_stream_signal(stream);
- 
- 			/* TODO: Add check if ASIC support and EDID audio */
- 			if (!stream->sink->converter_disable_audio &&
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0621-drm-amd-dal-updated-bandwidth-formula.patch b/common/recipes-kernel/linux/files/0621-drm-amd-dal-updated-bandwidth-formula.patch
deleted file mode 100644
index 8d7ddd75..00000000
--- a/common/recipes-kernel/linux/files/0621-drm-amd-dal-updated-bandwidth-formula.patch
+++ /dev/null
@@ -1,6489 +0,0 @@
-From 103dd18c0f1c4014bee3c6f554b160aa8fc62525 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 15 Dec 2015 10:51:31 -0500
-Subject: [PATCH 0621/1110] drm/amd/dal: updated bandwidth formula
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 4108 +++++++++++---------
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        |   68 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   20 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   26 +-
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  251 +-
- drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h          |   36 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |    4 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |    2 +-
- 8 files changed, 2511 insertions(+), 2004 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 6fc1ee6..3cbf6f8 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -31,80 +31,31 @@
-  * Private Functions
-  ******************************************************************************/
- 
--enum bw_defines {
--	def_ok,
--	def_na,
--	def_notok,
--	def_display_write_back420_chroma,
--	def_display_write_back420_luma,
--	def_graphics,
--	def_xl_pattern_solid,
--	def_xl_pattern_light_horizontal,
--	def_xl_pattern_checker,
--	def_notok_color,
--	def_na_color,
--	def_vb_black,
--	def_vb_white,
--	def_high_no_nbp_state_change_color,
--	def_high_no_nbp_state_change,
--	def_high_color,
--	def_mid_color,
--	def_low_color,
--	def_high,
--	def_mid,
--	def_low,
--	def_exceeded_allowed_maximum_sclk,
--	def_exceeded_allowed_maximum_bw,
--	def_exceeded_allowed_page_close_open,
--	def_exceeded_allowed_outstanding_pte_req_queue_size,
--	def_linear,
--	def_underlay444,
--	def_underlay422,
--	def_underlay420_chroma,
--	def_underlay420_luma,
--	def_any_lines,
--	def_auto,
--	def_manual,
--	def_portrait,
--	def_invalid_linear_or_stereo_mode,
--	def_invalid_rotation_or_bpp_or_stereo,
--	def_vsr_more_than_vtaps,
--	def_vsr_more_than_4,
--	def_ceil_htaps_div_4_more_or_eq_hsr,
--	def_hsr_more_than_htaps,
--	def_hsr_more_than_4,
--	def_none,
--	def_blended,
--	def_landscape
--};
-+static void calculate_bandwidth(
-+	const struct bw_calcs_dceip *dceip,
-+	const struct bw_calcs_vbios *vbios,
-+	const struct bw_calcs_mode_data_internal *mode_data,
-+	struct bw_calcs_results *results)
- 
--static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
--	const struct bw_calcs_input_vbios *vbios,
--	const struct bw_calcs_input_mode_data_internal *mode_data,
--	struct bw_results_internal *results)
- {
--	const struct bw_fixed pixels_per_chunk = int_to_fixed(512);
--	const struct bw_fixed max_chunks_non_fbc_mode = int_to_fixed(16);
--	const uint32_t high = 2;
--	const uint32_t mid = 1;
--	const uint32_t low = 0;
-+	const int32_t pixels_per_chunk = 512;
-+	const int32_t max_chunks_non_fbc_mode = 16;
-+	const int32_t high = 2;
-+	const int32_t mid = 1;
-+	const int32_t low = 0;
- 
--	uint32_t i, j, k;
--	uint64_t remainder;
-+	int32_t i, j, k;
- 	struct bw_fixed yclk[3];
- 	struct bw_fixed sclk[3];
- 	bool d0_underlay_enable;
- 	bool d1_underlay_enable;
-+	enum bw_defines sclk_message;
-+	enum bw_defines yclk_message;
- 	enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
- 	enum bw_defines tiling_mode[maximum_number_of_surfaces];
--	enum bw_stereo_mode stereo_mode[maximum_number_of_surfaces];
-+	enum bw_defines stereo_mode[maximum_number_of_surfaces];
- 	enum bw_defines surface_type[maximum_number_of_surfaces];
- 	enum bw_defines voltage;
--	enum bw_defines mode_background_color;
--	enum bw_defines mode_font_color;
--	enum bw_defines mode_pattern;
--	enum bw_defines sclk_message;
--	enum bw_defines yclk_message;
- 	enum bw_defines pipe_check;
- 	enum bw_defines hsr_check;
- 	enum bw_defines vsr_check;
-@@ -112,35 +63,50 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	enum bw_defines fbc_check;
- 	enum bw_defines rotation_check;
- 	enum bw_defines mode_check;
--	uint32_t y_clk_level;
--	uint32_t sclk_level;
--	yclk[high] = vbios->high_yclk_mhz;
--	yclk[mid] = vbios->high_yclk_mhz;
--	yclk[low] = vbios->low_yclk_mhz;
--	sclk[high] = vbios->high_sclk_mhz;
--	sclk[mid] = vbios->mid_sclk_mhz;
--	sclk[low] = vbios->low_sclk_mhz;
--	if (mode_data->d0_underlay_mode == ul_none) {
--		d0_underlay_enable = false;
-+
-+	yclk[low] = vbios->low_yclk;
-+	yclk[mid] = vbios->high_yclk;
-+	yclk[high] = vbios->high_yclk;
-+	sclk[low] = vbios->low_sclk;
-+	sclk[mid] = vbios->mid_sclk;
-+	sclk[high] = vbios->high_sclk;
-+	/* surface assignment:*/
-+	/* 0: d0 underlay or underlay luma*/
-+	/* 1: d0 underlay chroma*/
-+	/* 2: d1 underlay or underlay luma*/
-+	/* 3: d1 underlay chroma*/
-+	/* 4: d0 graphics*/
-+	/* 5: d1 graphics*/
-+	/* 6: d2 graphics*/
-+	/* 7: d3 graphics, same mode as d2*/
-+	/* 8: d4 graphics, same mode as d2*/
-+	/* 9: d5 graphics, same mode as d2*/
-+	/* ...*/
-+	/* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
-+	/* maximum_number_of_surfaces-1: d1 display_write_back420 chroma*/
-+	/* underlay luma and chroma surface parameters from spreadsheet*/
-+	if (mode_data->d0_underlay_mode == bw_def_none) {
-+		d0_underlay_enable = 0;
- 	} else {
--		d0_underlay_enable = true;
-+		d0_underlay_enable = 1;
- 	}
--	if (mode_data->d1_underlay_mode == ul_none) {
--		d1_underlay_enable = false;
-+	if (mode_data->d1_underlay_mode == bw_def_none) {
-+		d1_underlay_enable = 0;
- 	} else {
--		d1_underlay_enable = true;
--	}
--	results->number_of_underlay_surfaces = int_to_fixed(
--		d0_underlay_enable + d1_underlay_enable);
--	if (mode_data->underlay_surface_type == yuv_420) {
--		surface_type[0] = def_underlay420_luma;
--		surface_type[2] = def_underlay420_luma;
--		results->bytes_per_pixel[0] = int_to_fixed(1);
--		results->bytes_per_pixel[2] = int_to_fixed(1);
--		surface_type[1] = def_underlay420_chroma;
--		surface_type[3] = def_underlay420_chroma;
--		results->bytes_per_pixel[1] = int_to_fixed(2);
--		results->bytes_per_pixel[3] = int_to_fixed(2);
-+		d1_underlay_enable = 1;
-+	}
-+	results->number_of_underlay_surfaces = d0_underlay_enable
-+		+ d1_underlay_enable;
-+	switch (mode_data->underlay_surface_type) {
-+	case bw_def_420:
-+		surface_type[0] = bw_def_underlay420_luma;
-+		surface_type[2] = bw_def_underlay420_luma;
-+		results->bytes_per_pixel[0] = 1;
-+		results->bytes_per_pixel[2] = 1;
-+		surface_type[1] = bw_def_underlay420_chroma;
-+		surface_type[3] = bw_def_underlay420_chroma;
-+		results->bytes_per_pixel[1] = 2;
-+		results->bytes_per_pixel[3] = 2;
- 		results->lb_size_per_component[0] =
- 			dceip->underlay420_luma_lb_size_per_component;
- 		results->lb_size_per_component[1] =
-@@ -149,54 +115,62 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			dceip->underlay420_luma_lb_size_per_component;
- 		results->lb_size_per_component[3] =
- 			dceip->underlay420_chroma_lb_size_per_component;
--	} else if (mode_data->underlay_surface_type == yuv_422) {
--		surface_type[0] = def_underlay422;
--		surface_type[2] = def_underlay422;
--		results->bytes_per_pixel[0] = int_to_fixed(2);
--		results->bytes_per_pixel[2] = int_to_fixed(2);
-+		break;
-+	case bw_def_422:
-+		surface_type[0] = bw_def_underlay422;
-+		surface_type[2] = bw_def_underlay422;
-+		results->bytes_per_pixel[0] = 2;
-+		results->bytes_per_pixel[2] = 2;
- 		results->lb_size_per_component[0] =
- 			dceip->underlay422_lb_size_per_component;
- 		results->lb_size_per_component[2] =
- 			dceip->underlay422_lb_size_per_component;
--	} else {
--		surface_type[0] = def_underlay444;
--		surface_type[2] = def_underlay444;
--		results->bytes_per_pixel[0] = int_to_fixed(4);
--		results->bytes_per_pixel[2] = int_to_fixed(4);
-+		break;
-+	default:
-+		surface_type[0] = bw_def_underlay444;
-+		surface_type[2] = bw_def_underlay444;
-+		results->bytes_per_pixel[0] = 4;
-+		results->bytes_per_pixel[2] = 4;
- 		results->lb_size_per_component[0] =
- 			dceip->lb_size_per_component444;
- 		results->lb_size_per_component[2] =
- 			dceip->lb_size_per_component444;
-+		break;
- 	}
- 	if (d0_underlay_enable) {
--		if (mode_data->underlay_surface_type == yuv_420) {
--			results->enable[0] = true;
--			results->enable[1] = true;
--		} else {
--			results->enable[0] = true;
--			results->enable[1] = false;
-+		switch (mode_data->underlay_surface_type) {
-+		case bw_def_420:
-+			results->enable[0] = 1;
-+			results->enable[1] = 1;
-+			break;
-+		default:
-+			results->enable[0] = 1;
-+			results->enable[1] = 0;
-+			break;
- 		}
- 	} else {
--		results->enable[0] = false;
--		results->enable[1] = false;
-+		results->enable[0] = 0;
-+		results->enable[1] = 0;
- 	}
- 	if (d1_underlay_enable) {
--		if (mode_data->underlay_surface_type == yuv_420) {
--			results->enable[2] = true;
--			results->enable[3] = true;
--		} else {
--			results->enable[2] = true;
--			results->enable[3] = false;
-+		switch (mode_data->underlay_surface_type) {
-+		case bw_def_420:
-+			results->enable[2] = 1;
-+			results->enable[3] = 1;
-+			break;
-+		default:
-+			results->enable[2] = 1;
-+			results->enable[3] = 0;
-+			break;
- 		}
- 	} else {
--		results->enable[2] = false;
--		results->enable[3] = false;
-+		results->enable[2] = 0;
-+		results->enable[3] = 0;
- 	}
--
--	results->use_alpha[0] = false;
--	results->use_alpha[1] = false;
--	results->use_alpha[2] = false;
--	results->use_alpha[3] = false;
-+	results->use_alpha[0] = 0;
-+	results->use_alpha[1] = 0;
-+	results->use_alpha[2] = 0;
-+	results->use_alpha[3] = 0;
- 	results->scatter_gather_enable_for_pipe[0] =
- 		vbios->scatter_gather_enable;
- 	results->scatter_gather_enable_for_pipe[1] =
-@@ -209,52 +183,64 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	results->interlace_mode[1] = mode_data->graphics_interlace_mode;
- 	results->interlace_mode[2] = mode_data->graphics_interlace_mode;
- 	results->interlace_mode[3] = mode_data->graphics_interlace_mode;
--	results->h_total[0] = mode_data->d0_htotal;
--	results->h_total[1] = mode_data->d0_htotal;
--	results->h_total[2] = mode_data->d1_htotal;
--	results->h_total[3] = mode_data->d1_htotal;
-+	results->h_total[0] = bw_int_to_fixed(mode_data->d0_htotal);
-+	results->h_total[1] = bw_int_to_fixed(mode_data->d0_htotal);
-+	results->h_total[2] = bw_int_to_fixed(mode_data->d1_htotal);
-+	results->h_total[3] = bw_int_to_fixed(mode_data->d1_htotal);
- 	results->pixel_rate[0] = mode_data->d0_pixel_rate;
- 	results->pixel_rate[1] = mode_data->d0_pixel_rate;
- 	results->pixel_rate[2] = mode_data->d1_pixel_rate;
- 	results->pixel_rate[3] = mode_data->d1_pixel_rate;
--	results->src_width[0] = mode_data->underlay_src_width;
--	results->src_width[1] = mode_data->underlay_src_width;
--	results->src_width[2] = mode_data->underlay_src_width;
--	results->src_width[3] = mode_data->underlay_src_width;
--	results->src_height[0] = mode_data->underlay_src_height;
--	results->src_height[1] = mode_data->underlay_src_height;
--	results->src_height[2] = mode_data->underlay_src_height;
--	results->src_height[3] = mode_data->underlay_src_height;
--	results->pitch_in_pixels[0] = mode_data->underlay_pitch_in_pixels;
--	results->pitch_in_pixels[1] = mode_data->underlay_pitch_in_pixels;
--	results->pitch_in_pixels[2] = mode_data->underlay_pitch_in_pixels;
--	results->pitch_in_pixels[3] = mode_data->underlay_pitch_in_pixels;
-+	results->src_width[0] = bw_int_to_fixed(mode_data->underlay_src_width);
-+	results->src_width[1] = bw_int_to_fixed(mode_data->underlay_src_width);
-+	results->src_width[2] = bw_int_to_fixed(mode_data->underlay_src_width);
-+	results->src_width[3] = bw_int_to_fixed(mode_data->underlay_src_width);
-+	results->src_height[0] = bw_int_to_fixed(
-+		mode_data->underlay_src_height);
-+	results->src_height[1] = bw_int_to_fixed(
-+		mode_data->underlay_src_height);
-+	results->src_height[2] = bw_int_to_fixed(
-+		mode_data->underlay_src_height);
-+	results->src_height[3] = bw_int_to_fixed(
-+		mode_data->underlay_src_height);
-+	results->pitch_in_pixels[0] = bw_int_to_fixed(
-+		mode_data->underlay_pitch_in_pixels);
-+	results->pitch_in_pixels[1] = bw_int_to_fixed(
-+		mode_data->underlay_pitch_in_pixels);
-+	results->pitch_in_pixels[2] = bw_int_to_fixed(
-+		mode_data->underlay_pitch_in_pixels);
-+	results->pitch_in_pixels[3] = bw_int_to_fixed(
-+		mode_data->underlay_pitch_in_pixels);
- 	results->scale_ratio[0] = mode_data->d0_underlay_scale_ratio;
- 	results->scale_ratio[1] = mode_data->d0_underlay_scale_ratio;
- 	results->scale_ratio[2] = mode_data->d1_underlay_scale_ratio;
- 	results->scale_ratio[3] = mode_data->d1_underlay_scale_ratio;
--	results->h_taps[0] = mode_data->underlay_htaps;
--	results->h_taps[1] = mode_data->underlay_htaps;
--	results->h_taps[2] = mode_data->underlay_htaps;
--	results->h_taps[3] = mode_data->underlay_htaps;
--	results->v_taps[0] = mode_data->underlay_vtaps;
--	results->v_taps[1] = mode_data->underlay_vtaps;
--	results->v_taps[2] = mode_data->underlay_vtaps;
--	results->v_taps[3] = mode_data->underlay_vtaps;
--	results->rotation_angle[0] = mode_data->underlay_rotation_angle;
--	results->rotation_angle[1] = mode_data->underlay_rotation_angle;
--	results->rotation_angle[2] = mode_data->underlay_rotation_angle;
--	results->rotation_angle[3] = mode_data->underlay_rotation_angle;
--	if (mode_data->underlay_tiling_mode == linear) {
--		tiling_mode[0] = def_linear;
--		tiling_mode[1] = def_linear;
--		tiling_mode[2] = def_linear;
--		tiling_mode[3] = def_linear;
-+	results->h_taps[0] = bw_int_to_fixed(mode_data->underlay_htaps);
-+	results->h_taps[1] = bw_int_to_fixed(mode_data->underlay_htaps);
-+	results->h_taps[2] = bw_int_to_fixed(mode_data->underlay_htaps);
-+	results->h_taps[3] = bw_int_to_fixed(mode_data->underlay_htaps);
-+	results->v_taps[0] = bw_int_to_fixed(mode_data->underlay_vtaps);
-+	results->v_taps[1] = bw_int_to_fixed(mode_data->underlay_vtaps);
-+	results->v_taps[2] = bw_int_to_fixed(mode_data->underlay_vtaps);
-+	results->v_taps[3] = bw_int_to_fixed(mode_data->underlay_vtaps);
-+	results->rotation_angle[0] = bw_int_to_fixed(
-+		mode_data->underlay_rotation_angle);
-+	results->rotation_angle[1] = bw_int_to_fixed(
-+		mode_data->underlay_rotation_angle);
-+	results->rotation_angle[2] = bw_int_to_fixed(
-+		mode_data->underlay_rotation_angle);
-+	results->rotation_angle[3] = bw_int_to_fixed(
-+		mode_data->underlay_rotation_angle);
-+	if (mode_data->underlay_tiling_mode == bw_def_linear) {
-+		tiling_mode[0] = bw_def_linear;
-+		tiling_mode[1] = bw_def_linear;
-+		tiling_mode[2] = bw_def_linear;
-+		tiling_mode[3] = bw_def_linear;
- 	} else {
--		tiling_mode[0] = def_landscape;
--		tiling_mode[1] = def_landscape;
--		tiling_mode[2] = def_landscape;
--		tiling_mode[3] = def_landscape;
-+		tiling_mode[0] = bw_def_landscape;
-+		tiling_mode[1] = bw_def_landscape;
-+		tiling_mode[2] = bw_def_landscape;
-+		tiling_mode[3] = bw_def_landscape;
- 	}
- 	stereo_mode[0] = mode_data->underlay_stereo_mode;
- 	stereo_mode[1] = mode_data->underlay_stereo_mode;
-@@ -264,224 +250,252 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	results->lb_bpc[1] = mode_data->underlay_lb_bpc;
- 	results->lb_bpc[2] = mode_data->underlay_lb_bpc;
- 	results->lb_bpc[3] = mode_data->underlay_lb_bpc;
--	results->compression_rate[0] = int_to_fixed(1);
--	results->compression_rate[1] = int_to_fixed(1);
--	results->compression_rate[2] = int_to_fixed(1);
--	results->compression_rate[3] = int_to_fixed(1);
--	results->access_one_channel_only[0] = false;
--	results->access_one_channel_only[1] = false;
--	results->access_one_channel_only[2] = false;
--	results->access_one_channel_only[3] = false;
--	results->cursor_width_pixels[0] = int_to_fixed(0);
--	results->cursor_width_pixels[1] = int_to_fixed(0);
--	results->cursor_width_pixels[2] = int_to_fixed(0);
--	results->cursor_width_pixels[3] = int_to_fixed(0);
--	for (i = 4; i <= maximum_number_of_surfaces - 3; i += 1) {
-+	results->compression_rate[0] = bw_int_to_fixed(1);
-+	results->compression_rate[1] = bw_int_to_fixed(1);
-+	results->compression_rate[2] = bw_int_to_fixed(1);
-+	results->compression_rate[3] = bw_int_to_fixed(1);
-+	results->access_one_channel_only[0] = 0;
-+	results->access_one_channel_only[1] = 0;
-+	results->access_one_channel_only[2] = 0;
-+	results->access_one_channel_only[3] = 0;
-+	results->cursor_width_pixels[0] = bw_int_to_fixed(0);
-+	results->cursor_width_pixels[1] = bw_int_to_fixed(0);
-+	results->cursor_width_pixels[2] = bw_int_to_fixed(0);
-+	results->cursor_width_pixels[3] = bw_int_to_fixed(0);
-+	/* graphics surface parameters from spreadsheet*/
-+	for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {
- 		if (i < mode_data->number_of_displays + 4) {
--			if (i == 4 && mode_data->d0_underlay_mode == ul_only) {
--				results->enable[i] = false;
--				results->use_alpha[i] = false;
-+			if (i == 4
-+				&& mode_data->d0_underlay_mode
-+					== bw_def_underlay_only) {
-+				results->enable[i] = 0;
-+				results->use_alpha[i] = 0;
- 			} else if (i == 4
--				&& mode_data->d0_underlay_mode == ul_blend) {
--				results->enable[i] = true;
--				results->use_alpha[i] = true;
-+				&& mode_data->d0_underlay_mode
-+					== bw_def_blend) {
-+				results->enable[i] = 1;
-+				results->use_alpha[i] = 1;
- 			} else if (i == 4) {
--				results->enable[i] = true;
--				results->use_alpha[i] = false;
-+				results->enable[i] = 1;
-+				results->use_alpha[i] = 0;
- 			} else if (i == 5
--				&& mode_data->d1_underlay_mode == ul_only) {
--				results->enable[i] = false;
--				results->use_alpha[i] = false;
-+				&& mode_data->d1_underlay_mode
-+					== bw_def_underlay_only) {
-+				results->enable[i] = 0;
-+				results->use_alpha[i] = 0;
- 			} else if (i == 5
--				&& mode_data->d1_underlay_mode == ul_blend) {
--				results->enable[i] = true;
--				results->use_alpha[i] = true;
-+				&& mode_data->d1_underlay_mode
-+					== bw_def_blend) {
-+				results->enable[i] = 1;
-+				results->use_alpha[i] = 1;
- 			} else {
--				results->enable[i] = true;
--				results->use_alpha[i] = false;
-+				results->enable[i] = 1;
-+				results->use_alpha[i] = 0;
- 			}
- 		} else {
--			results->enable[i] = false;
--			results->use_alpha[i] = false;
-+			results->enable[i] = 0;
-+			results->use_alpha[i] = 0;
- 		}
- 		results->scatter_gather_enable_for_pipe[i] =
- 			vbios->scatter_gather_enable;
--		surface_type[i] = def_graphics;
-+		surface_type[i] = bw_def_graphics;
- 		results->lb_size_per_component[i] =
- 			dceip->lb_size_per_component444;
- 		results->bytes_per_pixel[i] =
- 			mode_data->graphics_bytes_per_pixel;
- 		results->interlace_mode[i] = mode_data->graphics_interlace_mode;
--		results->h_taps[i] = mode_data->graphics_htaps;
--		results->v_taps[i] = mode_data->graphics_vtaps;
--		results->rotation_angle[i] = mode_data->graphics_rotation_angle;
--		if (mode_data->graphics_tiling_mode == linear) {
--			tiling_mode[i] = def_linear;
--		} else if (equ(mode_data->graphics_rotation_angle,
--			int_to_fixed(0))
--			|| equ(mode_data->graphics_rotation_angle,
--				int_to_fixed(180))) {
--			tiling_mode[i] = def_landscape;
-+		results->h_taps[i] = bw_int_to_fixed(mode_data->graphics_htaps);
-+		results->v_taps[i] = bw_int_to_fixed(mode_data->graphics_vtaps);
-+		results->rotation_angle[i] = bw_int_to_fixed(
-+			mode_data->graphics_rotation_angle);
-+		if (mode_data->graphics_tiling_mode == bw_def_linear) {
-+			tiling_mode[i] = bw_def_linear;
-+		} else if (mode_data->graphics_rotation_angle == 0
-+			|| mode_data->graphics_rotation_angle == 180) {
-+			tiling_mode[i] = bw_def_landscape;
- 		} else {
--			tiling_mode[i] = def_portrait;
-+			tiling_mode[i] = bw_def_portrait;
- 		}
- 		results->lb_bpc[i] = mode_data->graphics_lb_bpc;
- 		if (i == 4) {
--			/* todo: check original d0_underlay_mode comparison, possible bug there*/
- 			if (mode_data->d0_fbc_enable
- 				&& (dceip->argb_compression_support
- 					|| mode_data->d0_underlay_mode
--						!= ul_blend)) {
--				results->compression_rate[i] =
--					vbios->average_compression_rate;
-+						!= bw_def_blended)) {
-+				results->compression_rate[i] = bw_int_to_fixed(
-+					vbios->average_compression_rate);
- 				results->access_one_channel_only[i] =
- 					mode_data->d0_lpt_enable;
- 			} else {
--				results->compression_rate[i] = int_to_fixed(1);
--				results->access_one_channel_only[i] = false;
-+				results->compression_rate[i] = bw_int_to_fixed(
-+					1);
-+				results->access_one_channel_only[i] = 0;
- 			}
--			results->h_total[i] = mode_data->d0_htotal;
-+			results->h_total[i] = bw_int_to_fixed(
-+				mode_data->d0_htotal);
- 			results->pixel_rate[i] = mode_data->d0_pixel_rate;
--			results->src_width[i] =
--				mode_data->d0_graphics_src_width;
--			results->src_height[i] =
--				mode_data->d0_graphics_src_height;
--			results->pitch_in_pixels[i] =
--				mode_data->d0_graphics_src_width;
-+			results->src_width[i] = bw_int_to_fixed(
-+				mode_data->d0_graphics_src_width);
-+			results->src_height[i] = bw_int_to_fixed(
-+				mode_data->d0_graphics_src_height);
-+			results->pitch_in_pixels[i] = bw_int_to_fixed(
-+				mode_data->d0_graphics_src_width);
- 			results->scale_ratio[i] =
- 				mode_data->d0_graphics_scale_ratio;
- 			stereo_mode[i] = mode_data->d0_graphics_stereo_mode;
- 		} else if (i == 5) {
--			results->compression_rate[i] = int_to_fixed(1);
--			results->access_one_channel_only[i] = false;
--			results->h_total[i] = mode_data->d1_htotal;
-+			results->compression_rate[i] = bw_int_to_fixed(1);
-+			results->access_one_channel_only[i] = 0;
-+			results->h_total[i] = bw_int_to_fixed(
-+				mode_data->d1_htotal);
- 			results->pixel_rate[i] = mode_data->d1_pixel_rate;
--			results->src_width[i] =
--				mode_data->d1_graphics_src_width;
--			results->src_height[i] =
--				mode_data->d1_graphics_src_height;
--			results->pitch_in_pixels[i] =
--				mode_data->d1_graphics_src_width;
-+			results->src_width[i] = bw_int_to_fixed(
-+				mode_data->d1_graphics_src_width);
-+			results->src_height[i] = bw_int_to_fixed(
-+				mode_data->d1_graphics_src_height);
-+			results->pitch_in_pixels[i] = bw_int_to_fixed(
-+				mode_data->d1_graphics_src_width);
- 			results->scale_ratio[i] =
- 				mode_data->d1_graphics_scale_ratio;
- 			stereo_mode[i] = mode_data->d1_graphics_stereo_mode;
- 		} else {
--			results->compression_rate[i] = int_to_fixed(1);
--			results->access_one_channel_only[i] = false;
--			results->h_total[i] = mode_data->d2_htotal;
-+			results->compression_rate[i] = bw_int_to_fixed(1);
-+			results->access_one_channel_only[i] = 0;
-+			results->h_total[i] = bw_int_to_fixed(
-+				mode_data->d2_htotal);
- 			results->pixel_rate[i] = mode_data->d2_pixel_rate;
--			results->src_width[i] =
--				mode_data->d2_graphics_src_width;
--			results->src_height[i] =
--				mode_data->d2_graphics_src_height;
--			results->pitch_in_pixels[i] =
--				mode_data->d2_graphics_src_width;
-+			results->src_width[i] = bw_int_to_fixed(
-+				mode_data->d2_graphics_src_width);
-+			results->src_height[i] = bw_int_to_fixed(
-+				mode_data->d2_graphics_src_height);
-+			results->pitch_in_pixels[i] = bw_int_to_fixed(
-+				mode_data->d2_graphics_src_width);
- 			results->scale_ratio[i] =
- 				mode_data->d2_graphics_scale_ratio;
- 			stereo_mode[i] = mode_data->d2_graphics_stereo_mode;
- 		}
--		results->cursor_width_pixels[i] = vbios->cursor_width;
-+		results->cursor_width_pixels[i] = bw_int_to_fixed(
-+			vbios->cursor_width);
- 	}
-+	/* display_write_back420*/
- 	results->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] =
--		false;
-+		0;
- 	results->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] =
--		false;
--	if (mode_data->d1_display_write_back_dwb_enable == true) {
--		results->enable[maximum_number_of_surfaces - 2] = true;
--		results->enable[maximum_number_of_surfaces - 1] = true;
-+		0;
-+	if (mode_data->d1_display_write_back_dwb_enable == 1) {
-+		results->enable[maximum_number_of_surfaces - 2] = 1;
-+		results->enable[maximum_number_of_surfaces - 1] = 1;
- 	} else {
--		results->enable[maximum_number_of_surfaces - 2] = false;
--		results->enable[maximum_number_of_surfaces - 1] = false;
-+		results->enable[maximum_number_of_surfaces - 2] = 0;
-+		results->enable[maximum_number_of_surfaces - 1] = 0;
- 	}
- 	surface_type[maximum_number_of_surfaces - 2] =
--		def_display_write_back420_luma;
-+		bw_def_display_write_back420_luma;
- 	surface_type[maximum_number_of_surfaces - 1] =
--		def_display_write_back420_chroma;
-+		bw_def_display_write_back420_chroma;
- 	results->lb_size_per_component[maximum_number_of_surfaces - 2] =
- 		dceip->underlay420_luma_lb_size_per_component;
- 	results->lb_size_per_component[maximum_number_of_surfaces - 1] =
- 		dceip->underlay420_chroma_lb_size_per_component;
--	results->bytes_per_pixel[maximum_number_of_surfaces - 2] = int_to_fixed(
--		1);
--	results->bytes_per_pixel[maximum_number_of_surfaces - 1] = int_to_fixed(
--		2);
-+	results->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1;
-+	results->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2;
- 	results->interlace_mode[maximum_number_of_surfaces - 2] =
- 		mode_data->graphics_interlace_mode;
- 	results->interlace_mode[maximum_number_of_surfaces - 1] =
- 		mode_data->graphics_interlace_mode;
--	results->h_taps[maximum_number_of_surfaces - 2] = int_to_fixed(1);
--	results->h_taps[maximum_number_of_surfaces - 1] = int_to_fixed(1);
--	results->v_taps[maximum_number_of_surfaces - 2] = int_to_fixed(1);
--	results->v_taps[maximum_number_of_surfaces - 1] = int_to_fixed(1);
--	results->rotation_angle[maximum_number_of_surfaces - 2] = int_to_fixed(
--		0);
--	results->rotation_angle[maximum_number_of_surfaces - 1] = int_to_fixed(
--		0);
--	tiling_mode[maximum_number_of_surfaces - 2] = def_linear;
--	tiling_mode[maximum_number_of_surfaces - 1] = def_linear;
--	results->lb_bpc[maximum_number_of_surfaces - 2] = int_to_fixed(8);
--	results->lb_bpc[maximum_number_of_surfaces - 1] = int_to_fixed(8);
-+	results->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	results->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	results->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	results->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	results->rotation_angle[maximum_number_of_surfaces - 2] =
-+		bw_int_to_fixed(0);
-+	results->rotation_angle[maximum_number_of_surfaces - 1] =
-+		bw_int_to_fixed(0);
-+	tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
-+	tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
-+	results->lb_bpc[maximum_number_of_surfaces - 2] = 8;
-+	results->lb_bpc[maximum_number_of_surfaces - 1] = 8;
- 	results->compression_rate[maximum_number_of_surfaces - 2] =
--		int_to_fixed(1);
-+		bw_int_to_fixed(1);
- 	results->compression_rate[maximum_number_of_surfaces - 1] =
--		int_to_fixed(1);
--	results->access_one_channel_only[maximum_number_of_surfaces - 2] =
--		false;
--	results->access_one_channel_only[maximum_number_of_surfaces - 1] =
--		false;
--	results->h_total[maximum_number_of_surfaces - 2] = mode_data->d1_htotal;
--	results->h_total[maximum_number_of_surfaces - 1] = mode_data->d1_htotal;
-+		bw_int_to_fixed(1);
-+	results->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;
-+	results->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;
-+	results->h_total[maximum_number_of_surfaces - 2] = bw_int_to_fixed(
-+		mode_data->d1_htotal);
-+	results->h_total[maximum_number_of_surfaces - 1] = bw_int_to_fixed(
-+		mode_data->d1_htotal);
- 	results->pixel_rate[maximum_number_of_surfaces - 2] =
- 		mode_data->d1_pixel_rate;
- 	results->pixel_rate[maximum_number_of_surfaces - 1] =
- 		mode_data->d1_pixel_rate;
--	results->src_width[maximum_number_of_surfaces - 2] =
--		mode_data->d1_graphics_src_width;
--	results->src_width[maximum_number_of_surfaces - 1] =
--		mode_data->d1_graphics_src_width;
--	results->src_height[maximum_number_of_surfaces - 2] =
--		mode_data->d1_graphics_src_height;
--	results->src_height[maximum_number_of_surfaces - 1] =
--		mode_data->d1_graphics_src_height;
-+	results->src_width[maximum_number_of_surfaces - 2] = bw_int_to_fixed(
-+		mode_data->d1_graphics_src_width);
-+	results->src_width[maximum_number_of_surfaces - 1] = bw_int_to_fixed(
-+		mode_data->d1_graphics_src_width);
-+	results->src_height[maximum_number_of_surfaces - 2] = bw_int_to_fixed(
-+		mode_data->d1_graphics_src_height);
-+	results->src_height[maximum_number_of_surfaces - 1] = bw_int_to_fixed(
-+		mode_data->d1_graphics_src_height);
- 	results->pitch_in_pixels[maximum_number_of_surfaces - 2] =
--		mode_data->d1_graphics_src_width;
-+		bw_int_to_fixed(mode_data->d1_graphics_src_width);
- 	results->pitch_in_pixels[maximum_number_of_surfaces - 1] =
--		mode_data->d1_graphics_src_width;
--	results->scale_ratio[maximum_number_of_surfaces - 2] = int_to_fixed(1);
--	results->scale_ratio[maximum_number_of_surfaces - 1] = int_to_fixed(1);
--	stereo_mode[maximum_number_of_surfaces - 2] = mono;
--	stereo_mode[maximum_number_of_surfaces - 1] = mono;
-+		bw_int_to_fixed(mode_data->d1_graphics_src_width);
-+	results->scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(
-+		1);
-+	results->scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(
-+		1);
-+	stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono;
-+	stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono;
- 	results->cursor_width_pixels[maximum_number_of_surfaces - 2] =
--		int_to_fixed(0);
-+		bw_int_to_fixed(0);
- 	results->cursor_width_pixels[maximum_number_of_surfaces - 1] =
--		int_to_fixed(0);
--	results->use_alpha[maximum_number_of_surfaces - 2] = false;
--	results->use_alpha[maximum_number_of_surfaces - 1] = false;
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		bw_int_to_fixed(0);
-+	results->use_alpha[maximum_number_of_surfaces - 2] = 0;
-+	results->use_alpha[maximum_number_of_surfaces - 1] = 0;
-+	/*mode check calculations:*/
-+	/* mode within dce ip capabilities*/
-+	/* fbc*/
-+	/* hsr*/
-+	/* vsr*/
-+	/* lb size*/
-+	/*effective scaling source and ratios:*/
-+	/*for graphics, non-stereo, non-interlace surfaces when the size of the source and destination are the same, only one tap is used*/
-+	/*420 chroma has half the width, height, horizontal and vertical scaling ratios than luma*/
-+	/*rotating an underlay surface swaps the width, height, horizontal and vertical scaling ratios*/
-+	/*in top-bottom stereo mode there is 2:1 vertical downscaling for each eye*/
-+	/*in side-by-side stereo mode there is 2:1 horizontal downscaling for each eye*/
-+	/*in interlace mode there is 2:1 vertical downscaling for each field*/
-+	/*in panning or bezel adjustment mode the source width has an extra 128 pixels*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (equ(results->scale_ratio[i], int_to_fixed(1))
--				&& surface_type[i] == def_graphics
--				&& stereo_mode[i] == mono
--				&& results->interlace_mode[i] == false) {
--				results->h_taps[i] = int_to_fixed(1);
--				results->v_taps[i] = int_to_fixed(1);
-+			if (bw_equ(results->scale_ratio[i], bw_int_to_fixed(1))
-+				&& surface_type[i] == bw_def_graphics
-+				&& stereo_mode[i] == bw_def_mono
-+				&& results->interlace_mode[i] == 0) {
-+				results->h_taps[i] = bw_int_to_fixed(1);
-+				results->v_taps[i] = bw_int_to_fixed(1);
- 			}
--			if (surface_type[i] == def_display_write_back420_chroma
--				|| surface_type[i] == def_underlay420_chroma) {
-+			if (surface_type[i]
-+				== bw_def_display_write_back420_chroma
-+				|| surface_type[i]
-+					== bw_def_underlay420_chroma) {
- 				results->pitch_in_pixels_after_surface_type[i] =
--					bw_div(results->pitch_in_pixels[i],
--						int_to_fixed(2));
-+					bw_div(
-+						results->pitch_in_pixels[i],
-+						bw_int_to_fixed(2));
- 				results->src_width_after_surface_type = bw_div(
--					results->src_width[i], int_to_fixed(2));
-+					results->src_width[i],
-+					bw_int_to_fixed(2));
- 				results->src_height_after_surface_type = bw_div(
- 					results->src_height[i],
--					int_to_fixed(2));
-+					bw_int_to_fixed(2));
- 				results->hsr_after_surface_type = bw_div(
- 					results->scale_ratio[i],
--					int_to_fixed(2));
-+					bw_int_to_fixed(2));
- 				results->vsr_after_surface_type = bw_div(
- 					results->scale_ratio[i],
--					int_to_fixed(2));
-+					bw_int_to_fixed(2));
- 			} else {
- 				results->pitch_in_pixels_after_surface_type[i] =
- 					results->pitch_in_pixels[i];
-@@ -494,10 +508,13 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				results->vsr_after_surface_type =
- 					results->scale_ratio[i];
- 			}
--			if ((equ(results->rotation_angle[i], int_to_fixed(90))
--				|| equ(results->rotation_angle[i],
--					int_to_fixed(270)))
--				&& surface_type[i] != def_graphics) {
-+			if ((bw_equ(
-+				results->rotation_angle[i],
-+				bw_int_to_fixed(90))
-+				|| bw_equ(
-+					results->rotation_angle[i],
-+					bw_int_to_fixed(270)))
-+				&& surface_type[i] != bw_def_graphics) {
- 				results->src_width_after_rotation =
- 					results->src_height_after_surface_type;
- 				results->src_height_after_rotation =
-@@ -516,29 +533,32 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				results->vsr_after_rotation =
- 					results->vsr_after_surface_type;
- 			}
--			if (stereo_mode[i] == top_bottom) {
-+			switch (stereo_mode[i]) {
-+			case bw_def_top_bottom:
- 				results->source_width_pixels[i] =
- 					results->src_width_after_rotation;
--				results->source_height_pixels = mul(
--					int_to_fixed(2),
-+				results->source_height_pixels = bw_mul(
-+					bw_int_to_fixed(2),
- 					results->src_height_after_rotation);
- 				results->hsr_after_stereo =
- 					results->hsr_after_rotation;
--				results->vsr_after_stereo = mul(
--					results->vsr_after_rotation,
--					int_to_fixed(1)); //todo: confirm correctness
--			} else if (stereo_mode[i] == side_by_side) {
--				results->source_width_pixels[i] = mul(
--					int_to_fixed(2),
-+				results->vsr_after_stereo = bw_mul(
-+					bw_int_to_fixed(1),
-+					results->vsr_after_rotation);
-+				break;
-+			case bw_def_side_by_side:
-+				results->source_width_pixels[i] = bw_mul(
-+					bw_int_to_fixed(2),
- 					results->src_width_after_rotation);
- 				results->source_height_pixels =
- 					results->src_height_after_rotation;
--				results->hsr_after_stereo = mul(
--					results->hsr_after_rotation,
--					int_to_fixed(1)); //todo: confirm correctness
-+				results->hsr_after_stereo = bw_mul(
-+					bw_int_to_fixed(1),
-+					results->hsr_after_rotation);
- 				results->vsr_after_stereo =
- 					results->vsr_after_rotation;
--			} else {
-+				break;
-+			default:
- 				results->source_width_pixels[i] =
- 					results->src_width_after_rotation;
- 				results->source_height_pixels =
-@@ -547,96 +567,119 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					results->hsr_after_rotation;
- 				results->vsr_after_stereo =
- 					results->vsr_after_rotation;
-+				break;
- 			}
- 			results->hsr[i] = results->hsr_after_stereo;
- 			if (results->interlace_mode[i]) {
--				results->vsr[i] = mul(results->vsr_after_stereo,
--					int_to_fixed(2));
-+				results->vsr[i] = bw_mul(
-+					results->vsr_after_stereo,
-+					bw_int_to_fixed(2));
- 			} else {
- 				results->vsr[i] = results->vsr_after_stereo;
- 			}
--			if (mode_data->panning_and_bezel_adjustment != none) {
-+			if (mode_data->panning_and_bezel_adjustment
-+				!= bw_def_none) {
- 				results->source_width_rounded_up_to_chunks[i] =
--					add(
--						bw_floor(
--							sub(
-+					bw_add(
-+						bw_floor2(
-+							bw_sub(
- 								results->source_width_pixels[i],
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									1)),
--							int_to_fixed(128)),
--						int_to_fixed(256));
-+							bw_int_to_fixed(128)),
-+						bw_int_to_fixed(256));
- 			} else {
- 				results->source_width_rounded_up_to_chunks[i] =
--					bw_ceil(results->source_width_pixels[i],
--						int_to_fixed(128));
-+					bw_ceil2(
-+						results->source_width_pixels[i],
-+						bw_int_to_fixed(128));
- 			}
- 			results->source_height_rounded_up_to_chunks[i] =
- 				results->source_height_pixels;
- 		}
- 	}
--	if (geq(dceip->number_of_graphics_pipes,
--		int_to_fixed(mode_data->number_of_displays))
--		&& geq(dceip->number_of_underlay_pipes,
--			results->number_of_underlay_surfaces)
--		&& !(dceip->display_write_back_supported == false
--			&& mode_data->d1_display_write_back_dwb_enable == true)) {
--		pipe_check = def_ok;
-+	/*mode support checks:*/
-+	/*the number of graphics and underlay pipes is limited by the ip support*/
-+	/*maximum horizontal and vertical scale ratio is 4, and should not exceed the number of taps*/
-+	/*for downscaling with the pre-downscaler, the horizontal scale ratio must be more than the ceiling of one quarter of the number of taps*/
-+	/*the pre-downscaler reduces the line buffer source by the horizontal scale ratio*/
-+	/*the number of lines in the line buffer has to exceed the number of vertical taps*/
-+	/*the size of the line in the line buffer is the product of the source width and the bits per component, rounded up to a multiple of 48*/
-+	/*the size of the line in the line buffer in the case of 10 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
-+	/*the size of the line in the line buffer in the case of 8 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
-+	/*frame buffer compression is not supported with stereo mode, rotation, or non- 888 formats*/
-+	/*rotation is not supported with linear of stereo modes*/
-+	if (dceip->number_of_graphics_pipes >= mode_data->number_of_displays
-+		&& dceip->number_of_underlay_pipes
-+			>= results->number_of_underlay_surfaces
-+		&& !(dceip->display_write_back_supported == 0
-+			&& mode_data->d1_display_write_back_dwb_enable == 1)) {
-+		pipe_check = bw_def_ok;
- 	} else {
--		pipe_check = def_notok;
-+		pipe_check = bw_def_notok;
- 	}
--	hsr_check = def_ok;
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	hsr_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (neq(results->hsr[i], int_to_fixed(1))) {
--				if (gtn(results->hsr[i], int_to_fixed(4))) {
--					hsr_check = def_hsr_more_than_4;
-+			if (bw_neq(results->hsr[i], bw_int_to_fixed(1))) {
-+				if (bw_mtn(
-+					results->hsr[i],
-+					bw_int_to_fixed(4))) {
-+					hsr_check = bw_def_hsr_mtn_4;
- 				} else {
--					if (gtn(results->hsr[i],
-+					if (bw_mtn(
-+						results->hsr[i],
- 						results->h_taps[i])) {
- 						hsr_check =
--							def_hsr_more_than_htaps;
-+							bw_def_hsr_mtn_h_taps;
- 					} else {
- 						if (dceip->pre_downscaler_enabled
--							== true
--							&& gtn(results->hsr[i],
--								int_to_fixed(1))
--							&& leq(results->hsr[i],
--								bw_ceil(
-+							== 1
-+							&& bw_mtn(
-+								results->hsr[i],
-+								bw_int_to_fixed(
-+									1))
-+							&& bw_leq(
-+								results->hsr[i],
-+								bw_ceil2(
- 									bw_div(
- 										results->h_taps[i],
--										int_to_fixed(
-+										bw_int_to_fixed(
- 											4)),
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										1)))) {
- 							hsr_check =
--								def_ceil_htaps_div_4_more_or_eq_hsr;
-+								bw_def_ceiling__h_taps_div_4___meq_hsr;
- 						}
- 					}
- 				}
- 			}
- 		}
- 	}
--	vsr_check = def_ok;
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	vsr_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (neq(results->vsr[i], int_to_fixed(1))) {
--				if (gtn(results->vsr[i], int_to_fixed(4))) {
--					vsr_check = def_vsr_more_than_4;
-+			if (bw_neq(results->vsr[i], bw_int_to_fixed(1))) {
-+				if (bw_mtn(
-+					results->vsr[i],
-+					bw_int_to_fixed(4))) {
-+					vsr_check = bw_def_vsr_mtn_4;
- 				} else {
--					if (gtn(results->vsr[i],
-+					if (bw_mtn(
-+						results->vsr[i],
- 						results->v_taps[i])) {
- 						vsr_check =
--							def_vsr_more_than_vtaps;
-+							bw_def_vsr_mtn_v_taps;
- 					}
- 				}
- 			}
- 		}
- 	}
--	lb_size_check = def_ok;
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	lb_size_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			if ((dceip->pre_downscaler_enabled
--				&& gtn(results->hsr[i], int_to_fixed(1)))) {
-+				&& bw_mtn(results->hsr[i], bw_int_to_fixed(1)))) {
- 				results->source_width_in_lb = bw_div(
- 					results->source_width_pixels[i],
- 					results->hsr[i]);
-@@ -644,490 +687,597 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				results->source_width_in_lb =
- 					results->source_width_pixels[i];
- 			}
--			if (equ(results->lb_bpc[i], int_to_fixed(8))) {
-+			switch (results->lb_bpc[i]) {
-+			case 8:
- 				results->lb_line_pitch =
--					bw_ceil(
--						mul(frc_to_fixed(24011, 3000),
--							bw_ceil(
-+					bw_ceil2(
-+						bw_mul(
-+							bw_div(
-+								bw_frc_to_fixed(
-+									2401171875ULL,
-+									100000000),
-+								bw_int_to_fixed(
-+									3)),
-+							bw_ceil2(
- 								results->source_width_in_lb,
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									8))),
--						int_to_fixed(48));
--			} else if (equ(results->lb_bpc[i], int_to_fixed(10))) {
-+						bw_int_to_fixed(48));
-+				break;
-+			case 10:
- 				results->lb_line_pitch =
--					bw_ceil(
--						mul(frc_to_fixed(30023, 3000),
--							bw_ceil(
-+					bw_ceil2(
-+						bw_mul(
-+							bw_div(
-+								bw_frc_to_fixed(
-+									300234375,
-+									10000000),
-+								bw_int_to_fixed(
-+									3)),
-+							bw_ceil2(
- 								results->source_width_in_lb,
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									8))),
--						int_to_fixed(48));
--			} else
--			// case else
--			{
--				results->lb_line_pitch = bw_ceil(
--					mul(results->source_width_in_lb,
--						results->lb_bpc[i]),
--					int_to_fixed(48));
-+						bw_int_to_fixed(48));
-+				break;
-+			default:
-+				results->lb_line_pitch = bw_ceil2(
-+					bw_mul(
-+						bw_int_to_fixed(
-+							results->lb_bpc[i]),
-+						results->source_width_in_lb),
-+					bw_int_to_fixed(48));
-+				break;
- 			}
--			results->lb_partitions[i] = bw_floor(
--				bw_div(results->lb_size_per_component[i],
-+			results->lb_partitions[i] = bw_floor2(
-+				bw_div(
-+					results->lb_size_per_component[i],
- 					results->lb_line_pitch),
--				int_to_fixed(1));
--			if ((surface_type[i] != def_graphics
-+				bw_int_to_fixed(1));
-+			/*clamp the partitions to the maxium number supported by the lb*/
-+			if ((surface_type[i] != bw_def_graphics
- 				|| dceip->graphics_lb_nodownscaling_multi_line_prefetching
--					== true)) {
--				results->lb_partitions_max[i] = int_to_fixed(
-+					== 1)) {
-+				results->lb_partitions_max[i] = bw_int_to_fixed(
- 					10);
- 			} else {
--				results->lb_partitions_max[i] = int_to_fixed(7);
-+				results->lb_partitions_max[i] = bw_int_to_fixed(
-+					7);
- 			}
--			results->lb_partitions[i] = bw_min(
-+			results->lb_partitions[i] = bw_min2(
- 				results->lb_partitions_max[i],
- 				results->lb_partitions[i]);
--			if (gtn(add(results->v_taps[i], int_to_fixed(1)),
-+			if (bw_mtn(
-+				bw_add(results->v_taps[i], bw_int_to_fixed(1)),
- 				results->lb_partitions[i])) {
--				lb_size_check = def_notok;
-+				lb_size_check = bw_def_notok;
- 			}
- 		}
- 	}
- 	if (mode_data->d0_fbc_enable
--		&& (equ(mode_data->graphics_rotation_angle, int_to_fixed(90))
--			|| equ(mode_data->graphics_rotation_angle,
--				int_to_fixed(270))
--			|| mode_data->d0_graphics_stereo_mode != mono
--			|| neq(mode_data->graphics_bytes_per_pixel,
--				int_to_fixed(4)))) {
--		fbc_check = def_invalid_rotation_or_bpp_or_stereo;
-+		&& (mode_data->graphics_rotation_angle == 90
-+			|| mode_data->graphics_rotation_angle == 270
-+			|| mode_data->d0_graphics_stereo_mode != bw_def_mono
-+			|| mode_data->graphics_bytes_per_pixel != 4)) {
-+		fbc_check = bw_def_invalid_rotation_or_bpp_or_stereo;
- 	} else {
--		fbc_check = def_ok;
-+		fbc_check = bw_def_ok;
- 	}
--	rotation_check = def_ok;
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	rotation_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if ((equ(results->rotation_angle[i], int_to_fixed(90))
--				|| equ(results->rotation_angle[i],
--					int_to_fixed(270)))
--				&& (tiling_mode[i] == def_linear
--					|| stereo_mode[i] != mono)) {
-+			if ((bw_equ(
-+				results->rotation_angle[i],
-+				bw_int_to_fixed(90))
-+				|| bw_equ(
-+					results->rotation_angle[i],
-+					bw_int_to_fixed(270)))
-+				&& (tiling_mode[i] == bw_def_linear
-+					|| stereo_mode[i] != bw_def_mono)) {
- 				rotation_check =
--					def_invalid_linear_or_stereo_mode;
-+					bw_def_invalid_linear_or_stereo_mode;
- 			}
- 		}
- 	}
--	if (pipe_check == def_ok && hsr_check == def_ok && vsr_check == def_ok
--		&& lb_size_check == def_ok && fbc_check == def_ok
--		&& rotation_check == def_ok) {
--		mode_check = def_ok;
-+	if (pipe_check == bw_def_ok && hsr_check == bw_def_ok
-+		&& vsr_check == bw_def_ok && lb_size_check == bw_def_ok
-+		&& fbc_check == bw_def_ok && rotation_check == bw_def_ok) {
-+		mode_check = bw_def_ok;
- 	} else {
--		mode_check = def_notok;
--	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		mode_check = bw_def_notok;
-+	}
-+	/*memory request size and latency hiding:*/
-+	/*request size is normally 64 byte, 2-line interleaved, with full latency hiding*/
-+	/*the display write-back requests are single line*/
-+	/*for tiled graphics surfaces, or undelay surfaces with width higher than the maximum size for full efficiency, request size is 32 byte in 8 and 16 bpp or if the rotation is orthogonal to the tiling grain. only half is useful of the bytes in the request size in 8 bpp or in 32 bpp if the rotation is orthogonal to the tiling grain.*/
-+	/*for undelay surfaces with width lower than the maximum size for full efficiency, requests are 4-line interleaved in 16bpp if the rotation is parallel to the tiling grain, and 8-line interleaved with 4-line latency hiding in 8bpp or if the rotation is orthogonal to the tiling grain.*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if ((equ(results->rotation_angle[i], int_to_fixed(90))
--				|| equ(results->rotation_angle[i],
--					int_to_fixed(270)))) {
--				if ((tiling_mode[i] == def_portrait)) {
--					results->orthogonal_rotation[i] = false;
-+			if ((bw_equ(
-+				results->rotation_angle[i],
-+				bw_int_to_fixed(90))
-+				|| bw_equ(
-+					results->rotation_angle[i],
-+					bw_int_to_fixed(270)))) {
-+				if ((tiling_mode[i] == bw_def_portrait)) {
-+					results->orthogonal_rotation[i] = 0;
- 				} else {
--					results->orthogonal_rotation[i] = true;
-+					results->orthogonal_rotation[i] = 1;
- 				}
- 			} else {
--				if ((tiling_mode[i] == def_portrait)) {
--					results->orthogonal_rotation[i] = true;
-+				if ((tiling_mode[i] == bw_def_portrait)) {
-+					results->orthogonal_rotation[i] = 1;
- 				} else {
--					results->orthogonal_rotation[i] = false;
-+					results->orthogonal_rotation[i] = 0;
- 				}
- 			}
--			if (equ(results->rotation_angle[i], int_to_fixed(90))
--				|| equ(results->rotation_angle[i],
--					int_to_fixed(270))) {
-+			if (bw_equ(
-+				results->rotation_angle[i],
-+				bw_int_to_fixed(90))
-+				|| bw_equ(
-+					results->rotation_angle[i],
-+					bw_int_to_fixed(270))) {
- 				results->underlay_maximum_source_efficient_for_tiling =
- 					dceip->underlay_maximum_height_efficient_for_tiling;
- 			} else {
- 				results->underlay_maximum_source_efficient_for_tiling =
- 					dceip->underlay_maximum_width_efficient_for_tiling;
- 			}
--			if (equ(dceip->de_tiling_buffer, int_to_fixed(0))) {
-+			if (bw_equ(
-+				dceip->de_tiling_buffer,
-+				bw_int_to_fixed(0))) {
- 				if (surface_type[i]
--					== def_display_write_back420_luma
-+					== bw_def_display_write_back420_luma
- 					|| surface_type[i]
--						== def_display_write_back420_chroma) {
-+						== bw_def_display_write_back420_chroma) {
- 					results->bytes_per_request[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->useful_bytes_per_request[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->lines_interleaved_in_mem_access[i] =
--						int_to_fixed(1);
-+						bw_int_to_fixed(1);
- 					results->latency_hiding_lines[i] =
--						int_to_fixed(1);
--				} else if (tiling_mode[i] == def_linear) {
-+						bw_int_to_fixed(1);
-+				} else if (tiling_mode[i] == bw_def_linear) {
- 					results->bytes_per_request[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->useful_bytes_per_request[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->lines_interleaved_in_mem_access[i] =
--						int_to_fixed(2);
-+						bw_int_to_fixed(2);
- 					results->latency_hiding_lines[i] =
--						int_to_fixed(2);
-+						bw_int_to_fixed(2);
- 				} else {
--					if (surface_type[i] == def_graphics
--						|| (gtn(
-+					if (surface_type[i] == bw_def_graphics
-+						|| (bw_mtn(
- 							results->source_width_rounded_up_to_chunks[i],
--							bw_ceil(
-+							bw_ceil2(
- 								results->underlay_maximum_source_efficient_for_tiling,
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									256))))) {
--						if (equ(
--							results->bytes_per_pixel[i],
--							int_to_fixed(8))) {
-+						switch (results->bytes_per_pixel[i]) {
-+						case 8:
- 							results->lines_interleaved_in_mem_access[i] =
--								int_to_fixed(2);
-+								bw_int_to_fixed(
-+									2);
- 							results->latency_hiding_lines[i] =
--								int_to_fixed(2);
-+								bw_int_to_fixed(
-+									2);
- 							if (results->orthogonal_rotation[i]) {
- 								results->bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										32);
- 								results->useful_bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										32);
- 							} else {
- 								results->bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										64);
- 								results->useful_bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										64);
- 							}
--						} else if (equ(
--							results->bytes_per_pixel[i],
--							int_to_fixed(4))) {
-+							break;
-+						case 4:
- 							if (results->orthogonal_rotation[i]) {
- 								results->lines_interleaved_in_mem_access[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										2);
- 								results->latency_hiding_lines[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										2);
- 								results->bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										32);
- 								results->useful_bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										16);
- 							} else {
- 								results->lines_interleaved_in_mem_access[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										2);
- 								results->latency_hiding_lines[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										2);
- 								results->bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										64);
- 								results->useful_bytes_per_request[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										64);
- 							}
--						} else if (equ(
--							results->bytes_per_pixel[i],
--							int_to_fixed(2))) {
-+							break;
-+						case 2:
- 							results->lines_interleaved_in_mem_access[i] =
--								int_to_fixed(2);
-+								bw_int_to_fixed(
-+									2);
- 							results->latency_hiding_lines[i] =
--								int_to_fixed(2);
-+								bw_int_to_fixed(
-+									2);
- 							results->bytes_per_request[i] =
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									32);
- 							results->useful_bytes_per_request[i] =
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									32);
--						} else {
-+							break;
-+						default:
- 							results->lines_interleaved_in_mem_access[i] =
--								int_to_fixed(2);
-+								bw_int_to_fixed(
-+									2);
- 							results->latency_hiding_lines[i] =
--								int_to_fixed(2);
-+								bw_int_to_fixed(
-+									2);
- 							results->bytes_per_request[i] =
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									32);
- 							results->useful_bytes_per_request[i] =
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									16);
-+							break;
- 						}
- 					} else {
- 						results->bytes_per_request[i] =
--							int_to_fixed(64);
-+							bw_int_to_fixed(64);
- 						results->useful_bytes_per_request[i] =
--							int_to_fixed(64);
-+							bw_int_to_fixed(64);
- 						if (results->orthogonal_rotation[i]) {
- 							results->lines_interleaved_in_mem_access[i] =
--								int_to_fixed(8);
-+								bw_int_to_fixed(
-+									8);
- 							results->latency_hiding_lines[i] =
--								int_to_fixed(4);
-+								bw_int_to_fixed(
-+									4);
- 						} else {
--							if (equ(
--								results->bytes_per_pixel[i],
--								int_to_fixed(
--									4))) {
-+							switch (results->bytes_per_pixel[i]) {
-+							case 4:
- 								results->lines_interleaved_in_mem_access[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										2);
- 								results->latency_hiding_lines[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										2);
--							} else if (equ(
--								results->bytes_per_pixel[i],
--								int_to_fixed(
--									2))) {
-+								break;
-+							case 2:
- 								results->lines_interleaved_in_mem_access[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										4);
- 								results->latency_hiding_lines[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										4);
--							} else {
-+								break;
-+							default:
- 								results->lines_interleaved_in_mem_access[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										8);
- 								results->latency_hiding_lines[i] =
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										4);
-+								break;
- 							}
- 						}
- 					}
- 				}
- 			} else {
--				results->bytes_per_request[i] = int_to_fixed(
-+				results->bytes_per_request[i] = bw_int_to_fixed(
- 					256);
- 				results->useful_bytes_per_request[i] =
--					int_to_fixed(256);
-+					bw_int_to_fixed(256);
- 				results->lines_interleaved_in_mem_access[i] =
--					int_to_fixed(4);
--				results->latency_hiding_lines[i] = int_to_fixed(
--					4);
-+					bw_int_to_fixed(4);
-+				results->latency_hiding_lines[i] =
-+					bw_int_to_fixed(4);
- 			}
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*requested peak bandwidth:*/
-+	/*the peak request-per-second bandwidth is the product of the maximum source lines in per line out in the beginning and in the middle of the frame, the ratio of the source width to the line time, the ratio of line interleaving in memory to lines of latency hiding, and the ratio of bytes per pixel to useful bytes per request.*/
-+	/*the peak bandwidth is the peak request-per-second bandwidth times the request size.*/
-+	/*the line buffer lines in per line out in the beginning of the frame is the vertical filter initialization value rounded up to even and divided by the line times for initialization, which is normally three.*/
-+	/*the line buffer lines in per line out in the middle of the frame is at least one, or the vertical scale ratio, rounded up to line pairs if not doing line buffer prefetching.*/
-+	/*the non-prefetching rounding up of the vertical scale ratio can also be done up to 1 (for a 0,2 pattern), 4/3 (for a 0,2,2 pattern), 6/4 (for a 0,2,2,2 pattern), or 3 (for a 2,4 pattern).*/
-+	/*the scaler vertical filter initialization value is calculated by the hardware as the floor of the average of the vertical scale ratio and the number of vertical taps increased by one.  add one more for possible odd line panning/bezel adjustment mode.*/
-+	/*for the bottom interlace field an extra 50% of the vertical scale ratio is considered for this calculation.*/
-+	/*in top-bottom stereo mode software has to set the filter initialization value manually and explicitly limit it to 4.  further, there is only one line time for initialization.*/
-+	/*line buffer prefetching is done when the number of lines in the line buffer exceeds the number of taps plus the ceiling of the vertical scale ratio.*/
-+	/*line buffer prefetching is not done when downscaling in the graphics pipe or for possible odd line panning/bezel adjustment mode.*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			results->v_filter_init[i] =
--				bw_floor(
-+				bw_floor2(
- 					bw_div(
--						(add(
--							add(
--								add(
--									results->vsr[i],
-+						(bw_add(
-+							bw_add(
-+								bw_add(
-+									bw_int_to_fixed(
-+										1),
- 									results->v_taps[i]),
--								mul(
--									mul(
--										frc_to_fixed(
--											1,
--											2),
--										results->vsr[i]),
--									int_to_fixed(
--										results->interlace_mode[i]))),
--							int_to_fixed(1))),
--						int_to_fixed(2)),
--					int_to_fixed(1));
-+								results->vsr[i]),
-+							bw_mul(
-+								bw_mul(
-+									bw_int_to_fixed(
-+										results->interlace_mode[i]),
-+									bw_frc_to_fixed(
-+										5,
-+										10)),
-+								results->vsr[i]))),
-+						bw_int_to_fixed(2)),
-+					bw_int_to_fixed(1));
- 			if (mode_data->panning_and_bezel_adjustment
--				== any_lines) {
--				results->v_filter_init[i] = add(
-+				== bw_def_any_lines) {
-+				results->v_filter_init[i] = bw_add(
- 					results->v_filter_init[i],
--					int_to_fixed(1));
-+					bw_int_to_fixed(1));
- 			}
--			if (stereo_mode[i] == top_bottom) {
--				v_filter_init_mode[i] = def_manual;
--				results->v_filter_init[i] = bw_min(
-+			if (stereo_mode[i] == bw_def_top_bottom) {
-+				v_filter_init_mode[i] = bw_def_manual;
-+				results->v_filter_init[i] = bw_min2(
- 					results->v_filter_init[i],
--					int_to_fixed(4));
-+					bw_int_to_fixed(4));
- 			} else {
--				v_filter_init_mode[i] = def_auto;
-+				v_filter_init_mode[i] = bw_def_auto;
- 			}
--			if (stereo_mode[i] == top_bottom) {
-+			if (stereo_mode[i] == bw_def_top_bottom) {
- 				results->num_lines_at_frame_start =
--					int_to_fixed(1);
-+					bw_int_to_fixed(1);
- 			} else {
- 				results->num_lines_at_frame_start =
--					int_to_fixed(3);
-+					bw_int_to_fixed(3);
- 			}
--			if ((gtn(results->vsr[i], int_to_fixed(1))
--				&& surface_type[i] == def_graphics)
-+			if ((bw_mtn(results->vsr[i], bw_int_to_fixed(1))
-+				&& surface_type[i] == bw_def_graphics)
- 				|| mode_data->panning_and_bezel_adjustment
--					== any_lines) {
--				results->line_buffer_prefetch[i] = int_to_fixed(
--					0);
-+					== bw_def_any_lines) {
-+				results->line_buffer_prefetch[i] = 0;
- 			} else if ((((dceip->underlay_downscale_prefetch_enabled
--				== true && surface_type[i] != def_graphics)
--				|| surface_type[i] == def_graphics)
--				&& (gtn(results->lb_partitions[i],
--					add(results->v_taps[i],
--						bw_ceil(results->vsr[i],
--							int_to_fixed(1))))))) {
--				results->line_buffer_prefetch[i] = int_to_fixed(
--					1);
-+				== 1 && surface_type[i] != bw_def_graphics)
-+				|| surface_type[i] == bw_def_graphics)
-+				&& (bw_mtn(
-+					results->lb_partitions[i],
-+					bw_add(
-+						results->v_taps[i],
-+						bw_ceil2(
-+							results->vsr[i],
-+							bw_int_to_fixed(1))))))) {
-+				results->line_buffer_prefetch[i] = 1;
- 			} else {
--				results->line_buffer_prefetch[i] = int_to_fixed(
--					0);
-+				results->line_buffer_prefetch[i] = 0;
- 			}
- 			results->lb_lines_in_per_line_out_in_beginning_of_frame[i] =
- 				bw_div(
--					bw_ceil(results->v_filter_init[i],
--						dceip->lines_interleaved_into_lb),
-+					bw_ceil2(
-+						results->v_filter_init[i],
-+						bw_int_to_fixed(
-+							dceip->lines_interleaved_into_lb)),
- 					results->num_lines_at_frame_start);
--			if (equ(results->line_buffer_prefetch[i],
--				int_to_fixed(1))) {
-+			if (results->line_buffer_prefetch[i] == 1) {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					bw_max(int_to_fixed(1),
-+					bw_max2(
-+						bw_int_to_fixed(1),
- 						results->vsr[i]);
--			} else if (leq(results->vsr[i], int_to_fixed(1))) {
-+			} else if (bw_leq(
-+				results->vsr[i],
-+				bw_int_to_fixed(1))) {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					int_to_fixed(1);
--			} else if (leq(results->vsr[i],
--				bw_div(int_to_fixed(4), int_to_fixed(3)))) {
-+					bw_int_to_fixed(1);
-+			} else if (bw_leq(
-+				results->vsr[i],
-+				bw_int_to_fixed(4 / 3))) {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					bw_div(int_to_fixed(4), int_to_fixed(3));
--			} else if (leq(results->vsr[i],
--				bw_div(int_to_fixed(6), int_to_fixed(4)))) {
-+					bw_div(
-+						bw_int_to_fixed(4),
-+						bw_int_to_fixed(3));
-+			} else if (bw_leq(
-+				results->vsr[i],
-+				bw_int_to_fixed(6 / 4))) {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					bw_div(int_to_fixed(6), int_to_fixed(4));
--			} else if (leq(results->vsr[i], int_to_fixed(2))) {
-+					bw_div(
-+						bw_int_to_fixed(6),
-+						bw_int_to_fixed(4));
-+			} else if (bw_leq(
-+				results->vsr[i],
-+				bw_int_to_fixed(2))) {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					int_to_fixed(2);
--			} else if (leq(results->vsr[i], int_to_fixed(3))) {
-+					bw_int_to_fixed(2);
-+			} else if (bw_leq(
-+				results->vsr[i],
-+				bw_int_to_fixed(3))) {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					int_to_fixed(3);
-+					bw_int_to_fixed(3);
- 			} else {
- 				results->lb_lines_in_per_line_out_in_middle_of_frame[i] =
--					int_to_fixed(4);
-+					bw_int_to_fixed(4);
- 			}
--			if (equ(results->line_buffer_prefetch[i],
--				int_to_fixed(1))
--				|| equ(
-+			if (results->line_buffer_prefetch[i] == 1
-+				|| bw_equ(
- 					results->lb_lines_in_per_line_out_in_middle_of_frame[i],
--					int_to_fixed(2))
--				|| equ(
-+					bw_int_to_fixed(2))
-+				|| bw_equ(
- 					results->lb_lines_in_per_line_out_in_middle_of_frame[i],
--					int_to_fixed(4))) {
-+					bw_int_to_fixed(4))) {
- 				results->horizontal_blank_and_chunk_granularity_factor[i] =
--					int_to_fixed(1);
-+					bw_int_to_fixed(1);
- 			} else {
- 				results->horizontal_blank_and_chunk_granularity_factor[i] =
--					bw_div(results->h_total[i],
-+					bw_div(
-+						results->h_total[i],
- 						(bw_div(
--							(add(
-+							(bw_add(
- 								results->h_total[i],
- 								bw_div(
--									(sub(
-+									(bw_sub(
- 										results->source_width_pixels[i],
--										dceip->chunk_width)),
-+										bw_int_to_fixed(
-+											dceip->chunk_width))),
- 									results->hsr[i]))),
--							int_to_fixed(2))));
-+							bw_int_to_fixed(2))));
- 			}
- 			results->request_bandwidth[i] =
- 				bw_div(
--					mul(
-+					bw_mul(
- 						bw_div(
--							mul(
-+							bw_mul(
- 								bw_div(
--									mul(
--										bw_max(
-+									bw_mul(
-+										bw_max2(
- 											results->lb_lines_in_per_line_out_in_beginning_of_frame[i],
- 											results->lb_lines_in_per_line_out_in_middle_of_frame[i]),
- 										results->source_width_rounded_up_to_chunks[i]),
- 									(bw_div(
- 										results->h_total[i],
- 										results->pixel_rate[i]))),
--								results->bytes_per_pixel[i]),
-+								bw_int_to_fixed(
-+									results->bytes_per_pixel[i])),
- 							results->useful_bytes_per_request[i]),
- 						results->lines_interleaved_in_mem_access[i]),
- 					results->latency_hiding_lines[i]);
--			results->display_bandwidth[i] = mul(
-+			results->display_bandwidth[i] = bw_mul(
- 				results->request_bandwidth[i],
- 				results->bytes_per_request[i]);
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*outstanding chunk request limit*/
-+	/*if underlay buffer sharing is enabled, the data buffer size for underlay in 422 or 444 is the sum of the luma and chroma data buffer sizes.*/
-+	/*underlay buffer sharing mode is only permitted in orthogonal rotation modes.*/
-+	/*if there is only one display enabled, the data buffer size for graphics is doubled.*/
-+	/*the memory chunk size in bytes is 1024 for the writeback, and 256 times the memory line interleaving and the bytes per pixel for graphics*/
-+	/*and underlay.*/
-+	/*the pipe chunk size uses 2 for line interleaving, except for the write back, in which case it is 1.*/
-+	/*graphics and underlay data buffer size is adjusted (limited) using the outstanding chunk request limit if there is more than one*/
-+	/*display enabled or if the dmif request buffer is not large enough for the total data buffer size.*/
-+	/*the outstanding chunk request limit is the ceiling of the adjusted data buffer size divided by the chunk size in bytes*/
-+	/*the adjusted data buffer size is the product of the display bandwidth and the minimum effective data buffer size in terms of time,*/
-+	/*rounded up to the chunk size in bytes, but should not exceed the original data buffer size*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] == def_display_write_back420_luma) {
-+			switch (surface_type[i]) {
-+			case bw_def_display_write_back420_luma:
- 				results->data_buffer_size[i] =
--					dceip->display_write_back420_luma_mcifwr_buffer_size;
--			} else if (surface_type[i]
--				== def_display_write_back420_chroma) {
-+					bw_int_to_fixed(
-+						dceip->display_write_back420_luma_mcifwr_buffer_size);
-+				break;
-+			case bw_def_display_write_back420_chroma:
- 				results->data_buffer_size[i] =
--					dceip->display_write_back420_chroma_mcifwr_buffer_size;
--			} else if (surface_type[i] == def_underlay420_luma) {
-+					bw_int_to_fixed(
-+						dceip->display_write_back420_chroma_mcifwr_buffer_size);
-+				break;
-+			case bw_def_underlay420_luma:
-+				results->data_buffer_size[i] = bw_int_to_fixed(
-+					dceip->underlay_luma_dmif_size);
-+				break;
-+			case bw_def_underlay420_chroma:
- 				results->data_buffer_size[i] =
--					dceip->underlay_luma_dmif_size;
--			} else if (surface_type[i] == def_underlay420_chroma) {
--				results->data_buffer_size[i] = bw_div(
--					dceip->underlay_chroma_dmif_size,
--					int_to_fixed(2));
--			} else if (surface_type[i] == def_underlay422
--				|| surface_type[i] == def_underlay444) {
--				if (results->orthogonal_rotation[i] == false) {
-+					bw_div(
-+						bw_int_to_fixed(
-+							dceip->underlay_chroma_dmif_size),
-+						bw_int_to_fixed(2));
-+				break;
-+			case bw_def_underlay422:
-+			case bw_def_underlay444:
-+				if (results->orthogonal_rotation[i] == 0) {
- 					results->data_buffer_size[i] =
--						dceip->underlay_luma_dmif_size;
-+						bw_int_to_fixed(
-+							dceip->underlay_luma_dmif_size);
- 				} else {
- 					results->data_buffer_size[i] =
--						add(
--							dceip->underlay_luma_dmif_size,
--							dceip->underlay_chroma_dmif_size);
-+						bw_add(
-+							bw_int_to_fixed(
-+								dceip->underlay_luma_dmif_size),
-+							bw_int_to_fixed(
-+								dceip->underlay_chroma_dmif_size));
- 				}
--			} else {
-+				break;
-+			default:
- 				if (mode_data->number_of_displays == 1
--					&& equ(dceip->de_tiling_buffer,
--						int_to_fixed(0))) {
-+					&& bw_equ(
-+						dceip->de_tiling_buffer,
-+						bw_int_to_fixed(0))) {
- 					if (mode_data->d0_fbc_enable) {
- 						results->data_buffer_size[i] =
--							mul(
--								dceip->max_dmif_buffer_allocated,
--								dceip->graphics_dmif_size);
-+							bw_mul(
-+								bw_int_to_fixed(
-+									dceip->max_dmif_buffer_allocated),
-+								bw_int_to_fixed(
-+									dceip->graphics_dmif_size));
- 					} else {
-+						/*the effective dmif buffer size in non-fbc mode is limited by the 16 entry chunk tracker*/
- 						results->data_buffer_size[i] =
--							mul(
--								mul(
--									max_chunks_non_fbc_mode,
--									pixels_per_chunk),
--								results->bytes_per_pixel[i]);
-+							bw_mul(
-+								bw_mul(
-+									bw_int_to_fixed(
-+										max_chunks_non_fbc_mode),
-+									bw_int_to_fixed(
-+										pixels_per_chunk)),
-+								bw_int_to_fixed(
-+									results->bytes_per_pixel[i]));
- 					}
- 				} else {
- 					results->data_buffer_size[i] =
--						dceip->graphics_dmif_size;
-+						bw_int_to_fixed(
-+							dceip->graphics_dmif_size);
- 				}
-+				break;
- 			}
--			if (surface_type[i] == def_display_write_back420_luma
-+			if (surface_type[i] == bw_def_display_write_back420_luma
- 				|| surface_type[i]
--					== def_display_write_back420_chroma) {
-+					== bw_def_display_write_back420_chroma) {
- 				results->memory_chunk_size_in_bytes[i] =
--					int_to_fixed(1024);
-+					bw_int_to_fixed(1024);
- 				results->pipe_chunk_size_in_bytes[i] =
--					int_to_fixed(1024);
-+					bw_int_to_fixed(1024);
- 			} else {
- 				results->memory_chunk_size_in_bytes[i] =
--					mul(
--						mul(dceip->chunk_width,
-+					bw_mul(
-+						bw_mul(
-+							bw_int_to_fixed(
-+								dceip->chunk_width),
- 							results->lines_interleaved_in_mem_access[i]),
--						results->bytes_per_pixel[i]);
-+						bw_int_to_fixed(
-+							results->bytes_per_pixel[i]));
- 				results->pipe_chunk_size_in_bytes[i] =
--					mul(
--						mul(dceip->chunk_width,
--							dceip->lines_interleaved_into_lb),
--						results->bytes_per_pixel[i]);
-+					bw_mul(
-+						bw_mul(
-+							bw_int_to_fixed(
-+								dceip->chunk_width),
-+							bw_int_to_fixed(
-+								dceip->lines_interleaved_into_lb)),
-+						bw_int_to_fixed(
-+							results->bytes_per_pixel[i]));
- 			}
- 		}
- 	}
--	results->min_dmif_size_in_time = int_to_fixed(9999);
--	results->min_mcifwr_size_in_time = int_to_fixed(9999);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->min_dmif_size_in_time = bw_int_to_fixed(9999);
-+	results->min_mcifwr_size_in_time = bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma) {
--				if (ltn(
-+					!= bw_def_display_write_back420_chroma) {
-+				if (bw_ltn(
- 					bw_div(
- 						bw_div(
--							mul(
-+							bw_mul(
- 								results->data_buffer_size[i],
- 								results->bytes_per_request[i]),
- 							results->useful_bytes_per_request[i]),
-@@ -1136,17 +1286,17 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					results->min_dmif_size_in_time =
- 						bw_div(
- 							bw_div(
--								mul(
-+								bw_mul(
- 									results->data_buffer_size[i],
- 									results->bytes_per_request[i]),
- 								results->useful_bytes_per_request[i]),
- 							results->display_bandwidth[i]);
- 				}
- 			} else {
--				if (ltn(
-+				if (bw_ltn(
- 					bw_div(
- 						bw_div(
--							mul(
-+							bw_mul(
- 								results->data_buffer_size[i],
- 								results->bytes_per_request[i]),
- 							results->useful_bytes_per_request[i]),
-@@ -1155,7 +1305,7 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					results->min_mcifwr_size_in_time =
- 						bw_div(
- 							bw_div(
--								mul(
-+								bw_mul(
- 									results->data_buffer_size[i],
- 									results->bytes_per_request[i]),
- 								results->useful_bytes_per_request[i]),
-@@ -1164,32 +1314,34 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	results->total_requests_for_dmif_size = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_requests_for_dmif_size = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]
--			&& surface_type[i] != def_display_write_back420_luma
-+			&& surface_type[i] != bw_def_display_write_back420_luma
- 			&& surface_type[i]
--				!= def_display_write_back420_chroma) {
--			results->total_requests_for_dmif_size = add(
-+				!= bw_def_display_write_back420_chroma) {
-+			results->total_requests_for_dmif_size = bw_add(
- 				results->total_requests_for_dmif_size,
--				bw_div(results->data_buffer_size[i],
-+				bw_div(
-+					results->data_buffer_size[i],
- 					results->useful_bytes_per_request[i]));
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma
-+					!= bw_def_display_write_back420_chroma
- 				&& dceip->limit_excessive_outstanding_dmif_requests
- 				&& (mode_data->number_of_displays > 1
--					|| gtn(
-+					|| bw_mtn(
- 						results->total_requests_for_dmif_size,
- 						dceip->dmif_request_buffer_size))) {
- 				results->adjusted_data_buffer_size[i] =
--					bw_min(results->data_buffer_size[i],
--						bw_ceil(
--							mul(
-+					bw_min2(
-+						results->data_buffer_size[i],
-+						bw_ceil2(
-+							bw_mul(
- 								results->min_dmif_size_in_time,
- 								results->display_bandwidth[i]),
- 							results->memory_chunk_size_in_bytes[i]));
-@@ -1199,269 +1351,324 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			if ((mode_data->number_of_displays == 1
--				&& equ(results->number_of_underlay_surfaces,
--					int_to_fixed(0)))) {
-+				&& results->number_of_underlay_surfaces == 0)) {
-+				/*set maximum chunk limit if only one graphic pipe is enabled*/
- 				results->outstanding_chunk_request_limit[i] =
--					int_to_fixed(255);
-+					bw_int_to_fixed(255);
- 			} else {
- 				results->outstanding_chunk_request_limit[i] =
--					bw_ceil(
-+					bw_ceil2(
- 						bw_div(
- 							results->adjusted_data_buffer_size[i],
- 							results->pipe_chunk_size_in_bytes[i]),
--						int_to_fixed(1));
-+						bw_int_to_fixed(1));
- 			}
- 		}
- 	}
-+	/*outstanding pte request limit*/
-+	/*in tiling mode with no rotation the sg pte requests are 8 useful pt_es, the sg row height is the page height and the sg page width x height is 64x64 for 8bpp, 64x32 for 16 bpp, 32x32 for 32 bpp*/
-+	/*in tiling mode with rotation the sg pte requests are only one useful pte, and the sg row height is also the page height, but the sg page width and height are swapped*/
-+	/*in linear mode the pte requests are 8 useful pt_es, the sg page width is 4096 divided by the bytes per pixel, the sg page height is 1, but there is just one row whose height is the lines of pte prefetching*/
-+	/*the outstanding pte request limit is obtained by multiplying the outstanding chunk request limit by the peak pte request to eviction limiting ratio, rounding up to integer, multiplying by the pte requests per chunk, and rounding up to integer again*/
-+	/*if not using peak pte request to eviction limiting, the outstanding pte request limit is the pte requests in the vblank*/
-+	/*the pte requests in the vblank is the product of the number of pte request rows times the number of pte requests in a row*/
-+	/*the number of pte requests in a row is the quotient of the source width divided by 256, multiplied by the pte requests per chunk, rounded up to even, multiplied by the scatter-gather row height and divided by the scatter-gather page height*/
-+	/*the pte requests per chunk is 256 divided by the scatter-gather page width and the useful pt_es per pte request*/
- 	if (mode_data->number_of_displays > 1
--		|| (neq(mode_data->graphics_rotation_angle, int_to_fixed(0))
--			&& neq(mode_data->graphics_rotation_angle,
--				int_to_fixed(180)))) {
-+		|| (mode_data->graphics_rotation_angle != 0
-+			&& mode_data->graphics_rotation_angle != 180)) {
- 		results->peak_pte_request_to_eviction_ratio_limiting =
- 			dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
- 	} else {
- 		results->peak_pte_request_to_eviction_ratio_limiting =
- 			dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]
--			&& results->scatter_gather_enable_for_pipe[i] == true) {
--			if (tiling_mode[i] == def_linear) {
-+			&& results->scatter_gather_enable_for_pipe[i] == 1) {
-+			if (tiling_mode[i] == bw_def_linear) {
- 				results->useful_pte_per_pte_request =
--					int_to_fixed(8);
-+					bw_int_to_fixed(8);
- 				results->scatter_gather_page_width[i] = bw_div(
--					int_to_fixed(4096),
--					results->bytes_per_pixel[i]);
-+					bw_int_to_fixed(4096),
-+					bw_int_to_fixed(
-+						results->bytes_per_pixel[i]));
- 				results->scatter_gather_page_height[i] =
--					int_to_fixed(1);
-+					bw_int_to_fixed(1);
- 				results->scatter_gather_pte_request_rows =
--					int_to_fixed(1);
-+					bw_int_to_fixed(1);
- 				results->scatter_gather_row_height =
--					dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode;
--			} else if (equ(results->rotation_angle[i],
--				int_to_fixed(0))
--				|| equ(results->rotation_angle[i],
--					int_to_fixed(180))) {
-+					bw_int_to_fixed(
-+						dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
-+			} else if (bw_equ(
-+				results->rotation_angle[i],
-+				bw_int_to_fixed(0))
-+				|| bw_equ(
-+					results->rotation_angle[i],
-+					bw_int_to_fixed(180))) {
- 				results->useful_pte_per_pte_request =
--					int_to_fixed(8);
--				if (equ(results->bytes_per_pixel[i],
--					int_to_fixed(4))) {
-+					bw_int_to_fixed(8);
-+				switch (results->bytes_per_pixel[i]) {
-+				case 4:
- 					results->scatter_gather_page_width[i] =
--						int_to_fixed(32);
-+						bw_int_to_fixed(32);
- 					results->scatter_gather_page_height[i] =
--						int_to_fixed(32);
--				} else if (equ(results->bytes_per_pixel[i],
--					int_to_fixed(2))) {
-+						bw_int_to_fixed(32);
-+					break;
-+				case 2:
- 					results->scatter_gather_page_width[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->scatter_gather_page_height[i] =
--						int_to_fixed(32);
--				} else {
-+						bw_int_to_fixed(32);
-+					break;
-+				default:
- 					results->scatter_gather_page_width[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->scatter_gather_page_height[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
-+					break;
- 				}
- 				results->scatter_gather_pte_request_rows =
--					dceip->scatter_gather_pte_request_rows_in_tiling_mode;
-+					bw_int_to_fixed(
-+						dceip->scatter_gather_pte_request_rows_in_tiling_mode);
- 				results->scatter_gather_row_height =
- 					results->scatter_gather_page_height[i];
- 			} else {
- 				results->useful_pte_per_pte_request =
--					int_to_fixed(1);
--				if (equ(results->bytes_per_pixel[i],
--					int_to_fixed(4))) {
-+					bw_int_to_fixed(1);
-+				switch (results->bytes_per_pixel[i]) {
-+				case 4:
- 					results->scatter_gather_page_width[i] =
--						int_to_fixed(32);
-+						bw_int_to_fixed(32);
- 					results->scatter_gather_page_height[i] =
--						int_to_fixed(32);
--				} else if (equ(results->bytes_per_pixel[i],
--					int_to_fixed(2))) {
-+						bw_int_to_fixed(32);
-+					break;
-+				case 2:
- 					results->scatter_gather_page_width[i] =
--						int_to_fixed(32);
-+						bw_int_to_fixed(32);
- 					results->scatter_gather_page_height[i] =
--						int_to_fixed(64);
--				} else
--				// case else
--				{
-+						bw_int_to_fixed(64);
-+					break;
-+				default:
- 					results->scatter_gather_page_width[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
- 					results->scatter_gather_page_height[i] =
--						int_to_fixed(64);
-+						bw_int_to_fixed(64);
-+					break;
- 				}
- 				results->scatter_gather_pte_request_rows =
--					dceip->scatter_gather_pte_request_rows_in_tiling_mode;
-+					bw_int_to_fixed(
-+						dceip->scatter_gather_pte_request_rows_in_tiling_mode);
- 				results->scatter_gather_row_height =
- 					results->scatter_gather_page_height[i];
- 			}
- 			results->pte_request_per_chunk[i] = bw_div(
--				bw_div(dceip->chunk_width,
-+				bw_div(
-+					bw_int_to_fixed(dceip->chunk_width),
- 					results->scatter_gather_page_width[i]),
- 				results->useful_pte_per_pte_request);
- 			results->scatter_gather_pte_requests_in_row[i] =
- 				bw_div(
--					mul(results->scatter_gather_row_height,
--						bw_ceil(
--							mul(
-+					bw_mul(
-+						bw_ceil2(
-+							bw_mul(
- 								bw_div(
- 									results->source_width_rounded_up_to_chunks[i],
--									dceip->chunk_width),
-+									bw_int_to_fixed(
-+										dceip->chunk_width)),
- 								results->pte_request_per_chunk[i]),
--							int_to_fixed(1))),
-+							bw_int_to_fixed(1)),
-+						results->scatter_gather_row_height),
- 					results->scatter_gather_page_height[i]);
--			results->scatter_gather_pte_requests_in_vblank = mul(
-+			results->scatter_gather_pte_requests_in_vblank = bw_mul(
- 				results->scatter_gather_pte_request_rows,
- 				results->scatter_gather_pte_requests_in_row[i]);
--			if (equ(
-+			if (bw_equ(
- 				results->peak_pte_request_to_eviction_ratio_limiting,
--				int_to_fixed(0))) {
-+				bw_int_to_fixed(0))) {
- 				results->scatter_gather_pte_request_limit[i] =
- 					results->scatter_gather_pte_requests_in_vblank;
- 			} else {
- 				results->scatter_gather_pte_request_limit[i] =
--					bw_max(
-+					bw_max2(
- 						dceip->minimum_outstanding_pte_request_limit,
--						bw_min(
-+						bw_min2(
- 							results->scatter_gather_pte_requests_in_vblank,
--							bw_ceil(
--								mul(
--									mul(
-+							bw_ceil2(
-+								bw_mul(
-+									bw_mul(
- 										bw_div(
--											bw_ceil(
-+											bw_ceil2(
- 												results->adjusted_data_buffer_size[i],
- 												results->memory_chunk_size_in_bytes[i]),
- 											results->memory_chunk_size_in_bytes[i]),
- 										results->pte_request_per_chunk[i]),
- 									results->peak_pte_request_to_eviction_ratio_limiting),
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									1))));
- 			}
- 		}
- 	}
--	results->inefficient_linear_pitch_in_bytes = mul(
--		mul(vbios->number_of_dram_banks,
--			vbios->number_of_dram_channels), int_to_fixed(256));
--	if (mode_data->underlay_surface_type == yuv_420) {
-+	/*pitch padding recommended for efficiency in linear mode*/
-+	/*in linear mode graphics or underlay with scatter gather, a pitch that is a multiple of the channel interleave (256 bytes) times the channel-bank rotation is not efficient*/
-+	/*if that is the case it is recommended to pad the pitch by at least 256 pixels*/
-+	results->inefficient_linear_pitch_in_bytes = bw_mul(
-+		bw_mul(
-+			bw_int_to_fixed(256),
-+			bw_int_to_fixed(vbios->number_of_dram_banks)),
-+		bw_int_to_fixed(vbios->number_of_dram_channels));
-+	switch (mode_data->underlay_surface_type) {
-+	case bw_def_420:
- 		results->inefficient_underlay_pitch_in_pixels =
- 			results->inefficient_linear_pitch_in_bytes;
--	} else if (mode_data->underlay_surface_type == yuv_422) {
-+		break;
-+	case bw_def_422:
- 		results->inefficient_underlay_pitch_in_pixels = bw_div(
- 			results->inefficient_linear_pitch_in_bytes,
--			int_to_fixed(2));
--	} else {
-+			bw_int_to_fixed(2));
-+		break;
-+	default:
- 		results->inefficient_underlay_pitch_in_pixels = bw_div(
- 			results->inefficient_linear_pitch_in_bytes,
--			int_to_fixed(4));
--	}
--
--	div64_u64_rem((uint64_t)mode_data->underlay_pitch_in_pixels.value,
--			(uint64_t)results->inefficient_underlay_pitch_in_pixels.value,
--			&remainder);
--
--	if (mode_data->underlay_tiling_mode == linear
--		&& vbios->scatter_gather_enable == true
--		&& remainder == 0) {
-+			bw_int_to_fixed(4));
-+		break;
-+	}
-+	if (mode_data->underlay_tiling_mode == bw_def_linear
-+		&& vbios->scatter_gather_enable == 1
-+		&& bw_equ(
-+			bw_mod(
-+				bw_int_to_fixed(
-+					mode_data->underlay_pitch_in_pixels),
-+				results->inefficient_underlay_pitch_in_pixels),
-+			bw_int_to_fixed(0))) {
- 		results->minimum_underlay_pitch_padding_recommended_for_efficiency =
--			int_to_fixed(256);
-+			bw_int_to_fixed(256);
- 	} else {
- 		results->minimum_underlay_pitch_padding_recommended_for_efficiency =
--			int_to_fixed(0);
--	}
--
--	results->cursor_total_data = int_to_fixed(0);
--	results->cursor_total_request_groups = int_to_fixed(0);
--	results->scatter_gather_total_pte_requests = int_to_fixed(0);
--	results->scatter_gather_total_pte_request_groups = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+			bw_int_to_fixed(0);
-+	}
-+	/*pixel transfer time*/
-+	/*the dmif and mcifwr yclk(pclk) required is the one that allows the transfer of all pipe's data buffer size in memory in the time for data transfer*/
-+	/*for dmif, pte and cursor requests have to be included.*/
-+	/*the dram data requirement is doubled when the data request size in bytes is less than the dram channel width times the burst size (8)*/
-+	/*the dram data requirement is also multiplied by the number of channels in the case of low power tiling*/
-+	/*the page close-open time is determined by trc and the number of page close-opens*/
-+	/*in tiled mode graphics or underlay with scatter-gather enabled the bytes per page close-open is the product of the memory line interleave times the maximum of the scatter-gather page width and the product of the tile width (8 pixels) times the number of channels times the number of banks.*/
-+	/*in linear mode graphics or underlay with scatter-gather enabled and inefficient pitch, the bytes per page close-open is the line request alternation slice, because different lines are in completely different 4k address bases.*/
-+	/*otherwise, the bytes page close-open is the chunk size because that is the arbitration slice.*/
-+	/*pte requests are grouped by pte requests per chunk if that is more than 1. each group costs a page close-open time for dmif reads*/
-+	/*cursor requests outstanding are limited to a group of two source lines. each group costs a page close-open time for dmif reads*/
-+	/*the display reads and writes time for data transfer is the minimum data or cursor buffer size in time minus the mc urgent latency*/
-+	/*the mc urgent latency is experienced more than one time if the number of dmif requests in the data buffer exceeds the request buffer size plus the request slots reserved for dmif in the dram channel arbiter queues*/
-+	/*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
-+	/*the data burst time is the maximum of the total page close-open time, total dmif/mcifwr buffer size in memory divided by the dram bandwidth, and the total dmif/mcifwr buffer size in memory divided by the 32 byte sclk data bus bandwidth, each multiplied by its efficiency.*/
-+	/*the source line transfer time is the maximum for all surfaces of the maximum of the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the fist pixel, and the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the last pixel plus the active time.*/
-+	/*the source pixels for the first output pixel is 512 if the scaler vertical filter initialization value is greater than 2, and it is 4 times the source width if it is greater than 4.*/
-+	/*the source pixels for the last output pixel is the source width times the scaler vertical filter initialization value rounded up to even*/
-+	/*the source data for these pixels is the number of pixels times the bytes per pixel times the bytes per request divided by the useful bytes per request.*/
-+	results->cursor_total_data = bw_int_to_fixed(0);
-+	results->cursor_total_request_groups = bw_int_to_fixed(0);
-+	results->scatter_gather_total_pte_requests = bw_int_to_fixed(0);
-+	results->scatter_gather_total_pte_request_groups = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			results->cursor_total_data = add(
--				results->cursor_total_data,
--				mul(results->cursor_width_pixels[i],
--					int_to_fixed(8)));
--			results->cursor_total_request_groups = add(
-+			results->cursor_total_data =
-+				bw_add(
-+					results->cursor_total_data,
-+					bw_mul(
-+						bw_mul(
-+							bw_int_to_fixed(2),
-+							results->cursor_width_pixels[i]),
-+						bw_int_to_fixed(4)));
-+			results->cursor_total_request_groups = bw_add(
- 				results->cursor_total_request_groups,
--				bw_ceil(
--					bw_div(results->cursor_width_pixels[i],
-+				bw_ceil2(
-+					bw_div(
-+						results->cursor_width_pixels[i],
- 						dceip->cursor_chunk_width),
--					int_to_fixed(1)));
-+					bw_int_to_fixed(1)));
- 			if (results->scatter_gather_enable_for_pipe[i]) {
- 				results->scatter_gather_total_pte_requests =
--					add(
-+					bw_add(
- 						results->scatter_gather_total_pte_requests,
- 						results->scatter_gather_pte_request_limit[i]);
- 				results->scatter_gather_total_pte_request_groups =
--					add(
-+					bw_add(
- 						results->scatter_gather_total_pte_request_groups,
--						bw_ceil(
-+						bw_ceil2(
- 							bw_div(
- 								results->scatter_gather_pte_request_limit[i],
--								bw_ceil(
-+								bw_ceil2(
- 									results->pte_request_per_chunk[i],
--									int_to_fixed(
-+									bw_int_to_fixed(
- 										1))),
--							int_to_fixed(1)));
-+							bw_int_to_fixed(1)));
- 			}
- 		}
- 	}
--	results->tile_width_in_pixels = int_to_fixed(8);
-+	results->tile_width_in_pixels = bw_int_to_fixed(8);
- 	results->dmif_total_number_of_data_request_page_close_open =
--		int_to_fixed(0);
-+		bw_int_to_fixed(0);
- 	results->mcifwr_total_number_of_data_request_page_close_open =
--		int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			uint64_t arg1 = (uint64_t)mul(results->pitch_in_pixels_after_surface_type[i],
--						results->bytes_per_pixel[i]).value;
--
--			div64_u64_rem(arg1,
--					(uint64_t)results->inefficient_linear_pitch_in_bytes.value,
--					&remainder);
--
--			if (results->scatter_gather_enable_for_pipe[i] == true
--				&& tiling_mode[i] != def_linear) {
-+			if (results->scatter_gather_enable_for_pipe[i] == 1
-+				&& tiling_mode[i] != bw_def_linear) {
- 				results->bytes_per_page_close_open =
--					mul(
-+					bw_mul(
- 						results->lines_interleaved_in_mem_access[i],
--						bw_max(
--							mul(
--								mul(
--									mul(
--										results->bytes_per_pixel[i],
-+						bw_max2(
-+							bw_mul(
-+								bw_mul(
-+									bw_mul(
-+										bw_int_to_fixed(
-+											results->bytes_per_pixel[i]),
- 										results->tile_width_in_pixels),
--									vbios->number_of_dram_banks),
--								vbios->number_of_dram_channels),
--							mul(
--								results->bytes_per_pixel[i],
-+									bw_int_to_fixed(
-+										vbios->number_of_dram_banks)),
-+								bw_int_to_fixed(
-+									vbios->number_of_dram_channels)),
-+							bw_mul(
-+								bw_int_to_fixed(
-+									results->bytes_per_pixel[i]),
- 								results->scatter_gather_page_width[i])));
- 			} else if (results->scatter_gather_enable_for_pipe[i]
--				== true && tiling_mode[i] == def_linear
--				&& remainder == 0) {
-+				== 1 && tiling_mode[i] == bw_def_linear
-+				&& bw_equ(
-+					bw_mod(
-+						(bw_mul(
-+							results->pitch_in_pixels_after_surface_type[i],
-+							bw_int_to_fixed(
-+								results->bytes_per_pixel[i]))),
-+						results->inefficient_linear_pitch_in_bytes),
-+					bw_int_to_fixed(0))) {
- 				results->bytes_per_page_close_open =
- 					dceip->linear_mode_line_request_alternation_slice;
- 			} else {
- 				results->bytes_per_page_close_open =
- 					results->memory_chunk_size_in_bytes[i];
- 			}
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma) {
-+					!= bw_def_display_write_back420_chroma) {
- 				results->dmif_total_number_of_data_request_page_close_open =
--					add(
-+					bw_add(
- 						results->dmif_total_number_of_data_request_page_close_open,
- 						bw_div(
--							bw_ceil(
-+							bw_ceil2(
- 								results->adjusted_data_buffer_size[i],
- 								results->memory_chunk_size_in_bytes[i]),
- 							results->bytes_per_page_close_open));
- 			} else {
- 				results->mcifwr_total_number_of_data_request_page_close_open =
--					add(
-+					bw_add(
- 						results->mcifwr_total_number_of_data_request_page_close_open,
- 						bw_div(
--							bw_ceil(
-+							bw_ceil2(
- 								results->adjusted_data_buffer_size[i],
- 								results->memory_chunk_size_in_bytes[i]),
- 							results->bytes_per_page_close_open));
-@@ -1470,34 +1677,38 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 	}
- 	results->dmif_total_page_close_open_time =
- 		bw_div(
--			mul(
--				(add(
--					add(
-+			bw_mul(
-+				(bw_add(
-+					bw_add(
- 						results->dmif_total_number_of_data_request_page_close_open,
- 						results->scatter_gather_total_pte_request_groups),
- 					results->cursor_total_request_groups)),
--				vbios->trc), int_to_fixed(1000));
-+				vbios->trc),
-+			bw_int_to_fixed(1000));
- 	results->mcifwr_total_page_close_open_time =
- 		bw_div(
--			mul(
-+			bw_mul(
- 				results->mcifwr_total_number_of_data_request_page_close_open,
--				vbios->trc), int_to_fixed(1000));
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+				vbios->trc),
-+			bw_int_to_fixed(1000));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			results->adjusted_data_buffer_size_in_memory[i] = bw_div(
--				mul(results->adjusted_data_buffer_size[i],
--					results->bytes_per_request[i]),
--				results->useful_bytes_per_request[i]);
-+			results->adjusted_data_buffer_size_in_memory[i] =
-+				bw_div(
-+					bw_mul(
-+						results->adjusted_data_buffer_size[i],
-+						results->bytes_per_request[i]),
-+					results->useful_bytes_per_request[i]);
- 		}
- 	}
--	results->total_requests_for_adjusted_dmif_size = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_requests_for_adjusted_dmif_size = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma) {
-+					!= bw_def_display_write_back420_chroma) {
- 				results->total_requests_for_adjusted_dmif_size =
--					add(
-+					bw_add(
- 						results->total_requests_for_adjusted_dmif_size,
- 						bw_div(
- 							results->adjusted_data_buffer_size[i],
-@@ -1505,133 +1716,151 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	if (equ(dceip->dcfclk_request_generation, int_to_fixed(1))) {
--		results->total_dmifmc_urgent_trips = int_to_fixed(1);
-+	if (dceip->dcfclk_request_generation == 1) {
-+		results->total_dmifmc_urgent_trips = bw_int_to_fixed(1);
- 	} else {
- 		results->total_dmifmc_urgent_trips =
--			bw_ceil(
-+			bw_ceil2(
- 				bw_div(
- 					results->total_requests_for_adjusted_dmif_size,
--					(add(dceip->dmif_request_buffer_size,
--						mul(
--							vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel,
--							vbios->number_of_dram_channels)))),
--				int_to_fixed(1));
--	}
--	results->total_dmifmc_urgent_latency = mul(vbios->dmifmc_urgent_latency,
-+					(bw_add(
-+						dceip->dmif_request_buffer_size,
-+						bw_int_to_fixed(
-+							vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel
-+								* vbios->number_of_dram_channels)))),
-+				bw_int_to_fixed(1));
-+	}
-+	results->total_dmifmc_urgent_latency = bw_mul(
-+		vbios->dmifmc_urgent_latency,
- 		results->total_dmifmc_urgent_trips);
--	results->total_display_reads_required_data = int_to_fixed(0);
--	results->total_display_reads_required_dram_access_data = int_to_fixed(
--		0);
--	results->total_display_writes_required_data = int_to_fixed(0);
--	results->total_display_writes_required_dram_access_data = int_to_fixed(
--		0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_display_reads_required_data = bw_int_to_fixed(0);
-+	results->total_display_reads_required_dram_access_data =
-+		bw_int_to_fixed(0);
-+	results->total_display_writes_required_data = bw_int_to_fixed(0);
-+	results->total_display_writes_required_dram_access_data =
-+		bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma) {
-+					!= bw_def_display_write_back420_chroma) {
- 				results->display_reads_required_data =
- 					results->adjusted_data_buffer_size_in_memory[i];
- 				results->display_reads_required_dram_access_data =
--					mul(
-+					bw_mul(
- 						results->adjusted_data_buffer_size_in_memory[i],
--						bw_ceil(
-+						bw_ceil2(
- 							bw_div(
--								vbios->dram_channel_width_in_bits,
-+								bw_int_to_fixed(
-+									vbios->dram_channel_width_in_bits),
- 								results->bytes_per_request[i]),
--							int_to_fixed(1)));
-+							bw_int_to_fixed(1)));
- 				if (results->access_one_channel_only[i]) {
- 					results->display_reads_required_dram_access_data =
--						mul(
-+						bw_mul(
- 							results->display_reads_required_dram_access_data,
--							vbios->number_of_dram_channels);
-+							bw_int_to_fixed(
-+								vbios->number_of_dram_channels));
- 				}
- 				results->total_display_reads_required_data =
--					add(
-+					bw_add(
- 						results->total_display_reads_required_data,
- 						results->display_reads_required_data);
- 				results->total_display_reads_required_dram_access_data =
--					add(
-+					bw_add(
- 						results->total_display_reads_required_dram_access_data,
- 						results->display_reads_required_dram_access_data);
- 			} else {
- 				results->total_display_writes_required_data =
--					add(
-+					bw_add(
- 						results->total_display_writes_required_data,
- 						results->adjusted_data_buffer_size_in_memory[i]);
- 				results->total_display_writes_required_dram_access_data =
--					add(
-+					bw_add(
- 						results->total_display_writes_required_dram_access_data,
--						mul(
-+						bw_mul(
- 							results->adjusted_data_buffer_size_in_memory[i],
--							bw_ceil(
-+							bw_ceil2(
- 								bw_div(
--									vbios->dram_channel_width_in_bits,
-+									bw_int_to_fixed(
-+										vbios->dram_channel_width_in_bits),
- 									results->bytes_per_request[i]),
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									1))));
- 			}
- 		}
- 	}
--	results->total_display_reads_required_data = add(
--		add(results->total_display_reads_required_data,
-+	results->total_display_reads_required_data = bw_add(
-+		bw_add(
-+			results->total_display_reads_required_data,
- 			results->cursor_total_data),
--		mul(results->scatter_gather_total_pte_requests,
--			int_to_fixed(64)));
--	results->total_display_reads_required_dram_access_data = add(
--		add(results->total_display_reads_required_dram_access_data,
-+		bw_mul(
-+			results->scatter_gather_total_pte_requests,
-+			bw_int_to_fixed(64)));
-+	results->total_display_reads_required_dram_access_data = bw_add(
-+		bw_add(
-+			results->total_display_reads_required_dram_access_data,
- 			results->cursor_total_data),
--		mul(results->scatter_gather_total_pte_requests,
--			int_to_fixed(64)));
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		bw_mul(
-+			results->scatter_gather_total_pte_requests,
-+			bw_int_to_fixed(64)));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (gtn(results->v_filter_init[i], int_to_fixed(4))) {
-+			if (bw_mtn(
-+				results->v_filter_init[i],
-+				bw_int_to_fixed(4))) {
- 				results->src_pixels_for_first_output_pixel[i] =
--					mul(
--						results->source_width_rounded_up_to_chunks[i],
--						int_to_fixed(4));
-+					bw_mul(
-+						bw_int_to_fixed(4),
-+						results->source_width_rounded_up_to_chunks[i]);
- 			} else {
--				if (gtn(results->v_filter_init[i],
--					int_to_fixed(2))) {
-+				if (bw_mtn(
-+					results->v_filter_init[i],
-+					bw_int_to_fixed(2))) {
- 					results->src_pixels_for_first_output_pixel[i] =
--						int_to_fixed(512);
-+						bw_int_to_fixed(512);
- 				} else {
- 					results->src_pixels_for_first_output_pixel[i] =
--						int_to_fixed(0);
-+						bw_int_to_fixed(0);
- 				}
- 			}
- 			results->src_data_for_first_output_pixel[i] =
- 				bw_div(
--					mul(
--						mul(
-+					bw_mul(
-+						bw_mul(
- 							results->src_pixels_for_first_output_pixel[i],
--							results->bytes_per_pixel[i]),
-+							bw_int_to_fixed(
-+								results->bytes_per_pixel[i])),
- 						results->bytes_per_request[i]),
- 					results->useful_bytes_per_request[i]);
- 			results->src_pixels_for_last_output_pixel[i] =
--				mul(
-+				bw_mul(
- 					results->source_width_rounded_up_to_chunks[i],
--					bw_max(
--						bw_ceil(
-+					bw_max2(
-+						bw_ceil2(
- 							results->v_filter_init[i],
--							dceip->lines_interleaved_into_lb),
--						mul(
--							results->horizontal_blank_and_chunk_granularity_factor[i],
--							bw_ceil(results->vsr[i],
--								dceip->lines_interleaved_into_lb))));
-+							bw_int_to_fixed(
-+								dceip->lines_interleaved_into_lb)),
-+						bw_mul(
-+							bw_ceil2(
-+								results->vsr[i],
-+								bw_int_to_fixed(
-+									dceip->lines_interleaved_into_lb)),
-+							results->horizontal_blank_and_chunk_granularity_factor[i])));
- 			results->src_data_for_last_output_pixel[i] =
- 				bw_div(
--					mul(
--						mul(
--							mul(
-+					bw_mul(
-+						bw_mul(
-+							bw_mul(
- 								results->source_width_rounded_up_to_chunks[i],
--								bw_max(
--									bw_ceil(
-+								bw_max2(
-+									bw_ceil2(
- 										results->v_filter_init[i],
--										dceip->lines_interleaved_into_lb),
-+										bw_int_to_fixed(
-+											dceip->lines_interleaved_into_lb)),
- 									results->lines_interleaved_in_mem_access[i])),
--							results->bytes_per_pixel[i]),
-+							bw_int_to_fixed(
-+								results->bytes_per_pixel[i])),
- 						results->bytes_per_request[i]),
- 					results->useful_bytes_per_request[i]);
- 			results->active_time[i] =
-@@ -1642,101 +1871,107 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					results->pixel_rate[i]);
- 		}
- 	}
--	for (i = 0; i <= 2; i += 1) {
--		for (j = 0; j <= 2; j += 1) {
-+	for (i = 0; i <= 2; i++) {
-+		for (j = 0; j <= 2; j++) {
- 			results->dmif_burst_time[i][j] =
- 				bw_max3(
- 					results->dmif_total_page_close_open_time,
- 					bw_div(
- 						results->total_display_reads_required_dram_access_data,
--						(mul(
-+						(bw_mul(
- 							bw_div(
--								mul(yclk[i],
--									vbios->dram_channel_width_in_bits),
--								int_to_fixed(
-+								bw_mul(
-+									yclk[i],
-+									bw_int_to_fixed(
-+										vbios->dram_channel_width_in_bits)),
-+								bw_int_to_fixed(
- 									8)),
--							vbios->number_of_dram_channels))),
-+							bw_int_to_fixed(
-+								vbios->number_of_dram_channels)))),
- 					bw_div(
- 						results->total_display_reads_required_data,
--						(mul(sclk[j],
-+						(bw_mul(
-+							sclk[j],
- 							vbios->data_return_bus_width))));
--			if (mode_data->d1_display_write_back_dwb_enable
--				== true) {
-+			if (mode_data->d1_display_write_back_dwb_enable == 1) {
- 				results->mcifwr_burst_time[i][j] =
- 					bw_max3(
- 						results->mcifwr_total_page_close_open_time,
- 						bw_div(
- 							results->total_display_writes_required_dram_access_data,
--							(mul(
-+							(bw_mul(
- 								bw_div(
--									mul(
-+									bw_mul(
- 										yclk[i],
--										vbios->dram_channel_width_in_bits),
--									int_to_fixed(
-+										bw_int_to_fixed(
-+											vbios->dram_channel_width_in_bits)),
-+									bw_int_to_fixed(
- 										8)),
--								vbios->number_of_dram_channels))),
-+								bw_int_to_fixed(
-+									vbios->number_of_dram_channels)))),
- 						bw_div(
- 							results->total_display_writes_required_data,
--							(mul(sclk[j],
-+							(bw_mul(
-+								sclk[j],
- 								vbios->data_return_bus_width))));
- 			}
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
--		for (j = 0; j <= 2; j += 1) {
--			for (k = 0; k <= 2; k += 1) {
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		for (j = 0; j <= 2; j++) {
-+			for (k = 0; k <= 2; k++) {
- 				if (results->enable[i]) {
- 					if (surface_type[i]
--						!= def_display_write_back420_luma
-+						!= bw_def_display_write_back420_luma
- 						&& surface_type[i]
--							!= def_display_write_back420_chroma) {
-+							!= bw_def_display_write_back420_chroma) {
- 						results->line_source_transfer_time[i][j][k] =
--							bw_max(
--								mul(
--									(add(
-+							bw_max2(
-+								bw_mul(
-+									(bw_add(
- 										results->total_dmifmc_urgent_latency,
- 										results->dmif_burst_time[j][k])),
--									bw_floor(
-+									bw_floor2(
- 										bw_div(
- 											results->src_data_for_first_output_pixel[i],
- 											results->adjusted_data_buffer_size_in_memory[i]),
--										int_to_fixed(
-+										bw_int_to_fixed(
- 											1))),
--								sub(
--									mul(
--										(add(
-+								bw_sub(
-+									bw_mul(
-+										(bw_add(
- 											results->total_dmifmc_urgent_latency,
- 											results->dmif_burst_time[j][k])),
--										bw_floor(
-+										bw_floor2(
- 											bw_div(
- 												results->src_data_for_last_output_pixel[i],
- 												results->adjusted_data_buffer_size_in_memory[i]),
--											int_to_fixed(
-+											bw_int_to_fixed(
- 												1))),
- 									results->active_time[i]));
- 					} else {
- 						results->line_source_transfer_time[i][j][k] =
--							bw_max(
--								mul(
--									(add(
-+							bw_max2(
-+								bw_mul(
-+									(bw_add(
- 										vbios->mcifwrmc_urgent_latency,
- 										results->mcifwr_burst_time[j][k])),
--									bw_floor(
-+									bw_floor2(
- 										bw_div(
- 											results->src_data_for_first_output_pixel[i],
- 											results->adjusted_data_buffer_size_in_memory[i]),
--										int_to_fixed(
-+										bw_int_to_fixed(
- 											1))),
--								sub(
--									mul(
--										(add(
-+								bw_sub(
-+									bw_mul(
-+										(bw_add(
- 											vbios->mcifwrmc_urgent_latency,
- 											results->mcifwr_burst_time[j][k])),
--										bw_floor(
-+										bw_floor2(
- 											bw_div(
- 												results->src_data_for_last_output_pixel[i],
- 												results->adjusted_data_buffer_size_in_memory[i]),
--											int_to_fixed(
-+											bw_int_to_fixed(
- 												1))),
- 									results->active_time[i]));
- 					}
-@@ -1744,21 +1979,35 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*cpu c-state and p-state change enable*/
-+	/*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
-+	/*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
-+	/*condition for the blackout duration:*/
-+	/* minimum latency hiding > blackout duration + dmif burst time + line source transfer time*/
-+	/*condition for the blackout recovery:*/
-+	/* recovery time >  dmif burst time + 2 * urgent latency*/
-+	/* recovery time > (display bw * blackout duration  + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
-+	/*                  / (dispclk - display bw)*/
-+	/*the minimum latency hiding is the minimum for all pipes of one screen line time, plus one more line time if doing lb prefetch, plus the dmif data buffer size equivalent in time, minus the urgent latency.*/
-+	/*the minimum latency hiding is  further limited by the cursor.  the cursor latency hiding is the number of lines of the cursor buffer, minus one if the downscaling is less than two, or minus three if it is more*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (equ(
-+			if (bw_equ(
- 				dceip->stutter_and_dram_clock_state_change_gated_before_cursor,
--				int_to_fixed(0))
--				&& gtn(results->cursor_width_pixels[i],
--					int_to_fixed(0))) {
--				if (ltn(results->vsr[i], int_to_fixed(2))) {
-+				bw_int_to_fixed(0))
-+				&& bw_mtn(
-+					results->cursor_width_pixels[i],
-+					bw_int_to_fixed(0))) {
-+				if (bw_ltn(
-+					results->vsr[i],
-+					bw_int_to_fixed(2))) {
- 					results->cursor_latency_hiding[i] =
- 						bw_div(
- 							bw_div(
--								mul(
--									(sub(
-+								bw_mul(
-+									(bw_sub(
- 										dceip->cursor_dcp_buffer_lines,
--										int_to_fixed(
-+										bw_int_to_fixed(
- 											1))),
- 									results->h_total[i]),
- 								results->vsr[i]),
-@@ -1767,10 +2016,10 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					results->cursor_latency_hiding[i] =
- 						bw_div(
- 							bw_div(
--								mul(
--									(sub(
-+								bw_mul(
-+									(bw_sub(
- 										dceip->cursor_dcp_buffer_lines,
--										int_to_fixed(
-+										bw_int_to_fixed(
- 											3))),
- 									results->h_total[i]),
- 								results->vsr[i]),
-@@ -1778,89 +2027,93 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				}
- 			} else {
- 				results->cursor_latency_hiding[i] =
--					int_to_fixed(9999);
-+					bw_int_to_fixed(9999);
- 			}
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			if (dceip->graphics_lb_nodownscaling_multi_line_prefetching
--				== true
--				&& (equ(results->vsr[i], int_to_fixed(1))
--					|| (leq(results->vsr[i],
--						frc_to_fixed(8, 10))
--						&& leq(results->v_taps[i],
--							int_to_fixed(2))
--						&& equ(results->lb_bpc[i],
--							int_to_fixed(8))))
--				&& surface_type[i] == def_graphics) {
-+				== 1
-+				&& (bw_equ(results->vsr[i], bw_int_to_fixed(1))
-+					|| (bw_leq(
-+						results->vsr[i],
-+						bw_frc_to_fixed(8, 10))
-+						&& bw_leq(
-+							results->v_taps[i],
-+							bw_int_to_fixed(2))
-+						&& results->lb_bpc[i] == 8))
-+				&& surface_type[i] == bw_def_graphics) {
- 				results->minimum_latency_hiding[i] =
--					sub(
--						sub(
--							add(
-+					bw_sub(
-+						bw_div(
-+							bw_mul(
- 								bw_div(
--									mul(
-+									(bw_add(
-+										bw_sub(
-+											results->lb_partitions[i],
-+											bw_int_to_fixed(
-+												1)),
- 										bw_div(
--											(bw_div(
--												bw_div(
--													results->data_buffer_size[i],
--													results->bytes_per_pixel[i]),
--												results->source_width_pixels[i])),
--											results->vsr[i]),
--										results->h_total[i]),
--									results->pixel_rate[i]),
--								results->lb_partitions[i]),
--							int_to_fixed(1)),
-+											bw_div(
-+												results->data_buffer_size[i],
-+												bw_int_to_fixed(
-+													results->bytes_per_pixel[i])),
-+											results->source_width_pixels[i]))),
-+									results->vsr[i]),
-+								results->h_total[i]),
-+							results->pixel_rate[i]),
- 						results->total_dmifmc_urgent_latency);
- 			} else {
- 				results->minimum_latency_hiding[i] =
--					sub(
-+					bw_sub(
- 						bw_div(
--							mul(
--								(add(
--									add(
--										results->line_buffer_prefetch[i],
--										int_to_fixed(
--											1)),
-+							bw_mul(
-+								(bw_add(
-+									bw_int_to_fixed(
-+										1
-+											+ results->line_buffer_prefetch[i]),
- 									bw_div(
- 										bw_div(
- 											bw_div(
- 												results->data_buffer_size[i],
--												results->bytes_per_pixel[i]),
-+												bw_int_to_fixed(
-+													results->bytes_per_pixel[i])),
- 											results->source_width_pixels[i]),
- 										results->vsr[i]))),
- 								results->h_total[i]),
- 							results->pixel_rate[i]),
- 						results->total_dmifmc_urgent_latency);
- 			}
--			results->minimum_latency_hiding_with_cursor[i] = bw_min(
--				results->minimum_latency_hiding[i],
--				results->cursor_latency_hiding[i]);
-+			results->minimum_latency_hiding_with_cursor[i] =
-+				bw_min2(
-+					results->minimum_latency_hiding[i],
-+					results->cursor_latency_hiding[i]);
- 		}
- 	}
--	for (i = 0; i <= 2; i += 1) {
--		for (j = 0; j <= 2; j += 1) {
--			results->blackout_duration_margin[i][j] = int_to_fixed(
--				9999);
-+	for (i = 0; i <= 2; i++) {
-+		for (j = 0; j <= 2; j++) {
-+			results->blackout_duration_margin[i][j] =
-+				bw_int_to_fixed(9999);
- 			results->dispclk_required_for_blackout_duration[i][j] =
--				int_to_fixed(0);
-+				bw_int_to_fixed(0);
- 			results->dispclk_required_for_blackout_recovery[i][j] =
--				int_to_fixed(0);
--			for (k = 0; k <= maximum_number_of_surfaces - 1; k +=
--				1) {
-+				bw_int_to_fixed(0);
-+			for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
- 				if (results->enable[k]
--					&& gtn(vbios->blackout_duration,
--						int_to_fixed(0))) {
-+					&& bw_mtn(
-+						vbios->blackout_duration,
-+						bw_int_to_fixed(0))) {
- 					if (surface_type[k]
--						!= def_display_write_back420_luma
-+						!= bw_def_display_write_back420_luma
- 						&& surface_type[k]
--							!= def_display_write_back420_chroma) {
-+							!= bw_def_display_write_back420_chroma) {
- 						results->blackout_duration_margin[i][j] =
--							bw_min(
-+							bw_min2(
- 								results->blackout_duration_margin[i][j],
--								sub(
--									sub(
--										sub(
-+								bw_sub(
-+									bw_sub(
-+										bw_sub(
- 											results->minimum_latency_hiding_with_cursor[k],
- 											vbios->blackout_duration),
- 										results->dmif_burst_time[i][j]),
-@@ -1870,93 +2123,94 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 								results->dispclk_required_for_blackout_duration[i][j],
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_first_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(sub(
--										sub(
-+									(bw_sub(
-+										bw_sub(
- 											results->minimum_latency_hiding_with_cursor[k],
- 											vbios->blackout_duration),
- 										results->dmif_burst_time[i][j]))),
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_last_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(add(
--										sub(
--											sub(
-+									(bw_add(
-+										bw_sub(
-+											bw_sub(
- 												results->minimum_latency_hiding_with_cursor[k],
- 												vbios->blackout_duration),
- 											results->dmif_burst_time[i][j]),
- 										results->active_time[k]))));
--						if (leq(
-+						if (bw_leq(
- 							vbios->maximum_blackout_recovery_time,
--							add(
--								mul(
--									results->total_dmifmc_urgent_latency,
--									int_to_fixed(
--										2)),
-+							bw_add(
-+								bw_mul(
-+									bw_int_to_fixed(
-+										2),
-+									results->total_dmifmc_urgent_latency),
- 								results->dmif_burst_time[i][j]))) {
- 							results->dispclk_required_for_blackout_recovery[i][j] =
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									9999);
--						} else if (ltn(
-+						} else if (bw_ltn(
- 							results->adjusted_data_buffer_size[k],
--							mul(
-+							bw_mul(
- 								bw_div(
--									mul(
-+									bw_mul(
- 										results->display_bandwidth[k],
- 										results->useful_bytes_per_request[k]),
- 									results->bytes_per_request[k]),
--								(add(
--									add(
--										vbios->blackout_duration,
--										mul(
--											results->total_dmifmc_urgent_latency,
--											int_to_fixed(
--												2))),
--									results->dmif_burst_time[i][j]))))) {
-+								(bw_add(
-+									vbios->blackout_duration,
-+									bw_add(
-+										bw_mul(
-+											bw_int_to_fixed(
-+												2),
-+											results->total_dmifmc_urgent_latency),
-+										results->dmif_burst_time[i][j])))))) {
- 							results->dispclk_required_for_blackout_recovery[i][j] =
--								bw_max(
-+								bw_max2(
- 									results->dispclk_required_for_blackout_recovery[i][j],
- 									bw_div(
--										mul(
-+										bw_mul(
- 											bw_div(
- 												bw_div(
--													(sub(
--														mul(
-+													(bw_sub(
-+														bw_mul(
- 															bw_div(
--																mul(
-+																bw_mul(
- 																	results->display_bandwidth[k],
- 																	results->useful_bytes_per_request[k]),
- 																results->bytes_per_request[k]),
--															(add(
-+															(bw_add(
- 																vbios->blackout_duration,
- 																vbios->maximum_blackout_recovery_time))),
- 														results->adjusted_data_buffer_size[k])),
--													results->bytes_per_pixel[k]),
--												(sub(
--													sub(
--														vbios->maximum_blackout_recovery_time,
--														mul(
--															results->total_dmifmc_urgent_latency,
--															int_to_fixed(
--																2))),
--													results->dmif_burst_time[i][j]))),
-+													bw_int_to_fixed(
-+														results->bytes_per_pixel[k])),
-+												(bw_sub(
-+													vbios->maximum_blackout_recovery_time,
-+													bw_sub(
-+														bw_mul(
-+															bw_int_to_fixed(
-+																2),
-+															results->total_dmifmc_urgent_latency),
-+														results->dmif_burst_time[i][j])))),
- 											results->latency_hiding_lines[k]),
- 										results->lines_interleaved_in_mem_access[k]));
- 						}
- 					} else {
- 						results->blackout_duration_margin[i][j] =
--							bw_min(
-+							bw_min2(
- 								results->blackout_duration_margin[i][j],
--								sub(
--									sub(
--										sub(
--											sub(
-+								bw_sub(
-+									bw_sub(
-+										bw_sub(
-+											bw_sub(
- 												results->minimum_latency_hiding_with_cursor[k],
- 												vbios->blackout_duration),
- 											results->dmif_burst_time[i][j]),
-@@ -1967,87 +2221,88 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 								results->dispclk_required_for_blackout_duration[i][j],
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_first_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(sub(
--										sub(
--											sub(
-+									(bw_sub(
-+										bw_sub(
-+											bw_sub(
- 												results->minimum_latency_hiding_with_cursor[k],
- 												vbios->blackout_duration),
- 											results->dmif_burst_time[i][j]),
- 										results->mcifwr_burst_time[i][j]))),
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_last_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(add(
--										sub(
--											sub(
--												sub(
-+									(bw_add(
-+										bw_sub(
-+											bw_sub(
-+												bw_sub(
- 													results->minimum_latency_hiding_with_cursor[k],
- 													vbios->blackout_duration),
- 												results->dmif_burst_time[i][j]),
- 											results->mcifwr_burst_time[i][j]),
- 										results->active_time[k]))));
--						if (ltn(
-+						if (bw_ltn(
- 							vbios->maximum_blackout_recovery_time,
--							add(
--								add(
--									mul(
--										vbios->mcifwrmc_urgent_latency,
--										int_to_fixed(
--											2)),
-+							bw_add(
-+								bw_add(
-+									bw_mul(
-+										bw_int_to_fixed(
-+											2),
-+										vbios->mcifwrmc_urgent_latency),
- 									results->dmif_burst_time[i][j]),
- 								results->mcifwr_burst_time[i][j]))) {
- 							results->dispclk_required_for_blackout_recovery[i][j] =
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									9999);
--						} else if (ltn(
-+						} else if (bw_ltn(
- 							results->adjusted_data_buffer_size[k],
--							mul(
-+							bw_mul(
- 								bw_div(
--									mul(
-+									bw_mul(
- 										results->display_bandwidth[k],
- 										results->useful_bytes_per_request[k]),
- 									results->bytes_per_request[k]),
--								(add(
--									add(
--										vbios->blackout_duration,
--										mul(
--											results->total_dmifmc_urgent_latency,
--											int_to_fixed(
--												2))),
--									results->dmif_burst_time[i][j]))))) {
-+								(bw_add(
-+									vbios->blackout_duration,
-+									bw_add(
-+										bw_mul(
-+											bw_int_to_fixed(
-+												2),
-+											results->total_dmifmc_urgent_latency),
-+										results->dmif_burst_time[i][j])))))) {
- 							results->dispclk_required_for_blackout_recovery[i][j] =
--								bw_max(
-+								bw_max2(
- 									results->dispclk_required_for_blackout_recovery[i][j],
- 									bw_div(
--										mul(
-+										bw_mul(
- 											bw_div(
- 												bw_div(
--													(sub(
--														mul(
-+													(bw_sub(
-+														bw_mul(
- 															bw_div(
--																mul(
-+																bw_mul(
- 																	results->display_bandwidth[k],
- 																	results->useful_bytes_per_request[k]),
- 																results->bytes_per_request[k]),
--															(add(
-+															(bw_add(
- 																vbios->blackout_duration,
- 																vbios->maximum_blackout_recovery_time))),
- 														results->adjusted_data_buffer_size[k])),
--													results->bytes_per_pixel[k]),
--												(sub(
-+													bw_int_to_fixed(
-+														results->bytes_per_pixel[k])),
-+												(bw_sub(
- 													vbios->maximum_blackout_recovery_time,
--													(add(
--														mul(
--															results->total_dmifmc_urgent_latency,
--															int_to_fixed(
--																2)),
-+													(bw_add(
-+														bw_mul(
-+															bw_int_to_fixed(
-+																2),
-+															results->total_dmifmc_urgent_latency),
- 														results->dmif_burst_time[i][j]))))),
- 											results->latency_hiding_lines[k]),
- 										results->lines_interleaved_in_mem_access[k]));
-@@ -2057,69 +2312,79 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	if (gtn(results->blackout_duration_margin[high][high], int_to_fixed(0))
--		&& ltn(
-+	if (bw_mtn(
-+		results->blackout_duration_margin[high][high],
-+		bw_int_to_fixed(0))
-+		&& bw_ltn(
- 			results->dispclk_required_for_blackout_duration[high][high],
--			vbios->high_voltage_max_dispclk_mhz)) {
--		results->cpup_state_change_enable = true;
--		if (ltn(
-+			vbios->high_voltage_max_dispclk)) {
-+		results->cpup_state_change_enable = bw_def_yes;
-+		if (bw_ltn(
- 			results->dispclk_required_for_blackout_recovery[high][high],
--			vbios->high_voltage_max_dispclk_mhz)) {
--			results->cpuc_state_change_enable = true;
-+			vbios->high_voltage_max_dispclk)) {
-+			results->cpuc_state_change_enable = bw_def_yes;
- 		} else {
--			results->cpuc_state_change_enable = false;
-+			results->cpuc_state_change_enable = bw_def_no;
- 		}
- 	} else {
--		results->cpup_state_change_enable = false;
--		results->cpuc_state_change_enable = false;
--	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		results->cpup_state_change_enable = bw_def_no;
-+		results->cpuc_state_change_enable = bw_def_no;
-+	}
-+	/*nb p-state change enable*/
-+	/*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be below the maximum.*/
-+	/*the dram speed/p-state change margin is the minimum for all surfaces of the maximum latency hiding minus the dram speed/p-state change latency, minus the dmif burst time, minus the source line transfer time*/
-+	/*the maximum latency hiding is the minimum latency hiding plus one source line used for de-tiling in the line buffer, plus half the urgent latency*/
-+	/*if stutter and dram clock state change are gated before cursor then the cursor latency hiding does not limit stutter or dram clock state change*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			if (mode_data->number_of_displays <= 1
- 				|| mode_data->display_synchronization_enabled
--					== true) {
-+					== bw_def_yes) {
- 				results->maximum_latency_hiding[i] =
--					int_to_fixed(450);
-+					bw_int_to_fixed(450);
- 			} else {
- 				results->maximum_latency_hiding[i] =
--					add(
--						add(
--							results->minimum_latency_hiding[i],
-+					bw_add(
-+						results->minimum_latency_hiding[i],
-+						bw_add(
- 							bw_div(
--								mul(
-+								bw_mul(
- 									bw_div(
--										int_to_fixed(
-+										bw_int_to_fixed(
- 											1),
- 										results->vsr[i]),
- 									results->h_total[i]),
--								results->pixel_rate[i])),
--						mul(frc_to_fixed(1, 2),
--							results->total_dmifmc_urgent_latency));
-+								results->pixel_rate[i]),
-+							bw_mul(
-+								bw_frc_to_fixed(
-+									5,
-+									10),
-+								results->total_dmifmc_urgent_latency)));
- 			}
--			results->maximum_latency_hiding_with_cursor[i] = bw_min(
--				results->maximum_latency_hiding[i],
--				results->cursor_latency_hiding[i]);
-+			results->maximum_latency_hiding_with_cursor[i] =
-+				bw_min2(
-+					results->maximum_latency_hiding[i],
-+					results->cursor_latency_hiding[i]);
- 		}
- 	}
--	for (i = 0; i <= 2; i += 1) {
--		for (j = 0; j <= 2; j += 1) {
--			results->dram_speed_change_margin[i][j] = int_to_fixed(
--				9999);
-+	for (i = 0; i <= 2; i++) {
-+		for (j = 0; j <= 2; j++) {
-+			results->dram_speed_change_margin[i][j] =
-+				bw_int_to_fixed(9999);
- 			results->dispclk_required_for_dram_speed_change[i][j] =
--				int_to_fixed(0);
--			for (k = 0; k <= maximum_number_of_surfaces - 1; k +=
--				1) {
-+				bw_int_to_fixed(0);
-+			for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
- 				if (results->enable[k]) {
- 					if (surface_type[k]
--						!= def_display_write_back420_luma
-+						!= bw_def_display_write_back420_luma
- 						&& surface_type[k]
--							!= def_display_write_back420_chroma) {
-+							!= bw_def_display_write_back420_chroma) {
- 						results->dram_speed_change_margin[i][j] =
--							bw_min(
-+							bw_min2(
- 								results->dram_speed_change_margin[i][j],
--								sub(
--									sub(
--										sub(
-+								bw_sub(
-+									bw_sub(
-+										bw_sub(
- 											results->maximum_latency_hiding_with_cursor[k],
- 											vbios->nbp_state_change_latency),
- 										results->dmif_burst_time[i][j]),
-@@ -2129,36 +2394,36 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 								results->dispclk_required_for_dram_speed_change[i][j],
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_first_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(sub(
--										sub(
-+									(bw_sub(
-+										bw_sub(
- 											results->maximum_latency_hiding_with_cursor[k],
- 											vbios->nbp_state_change_latency),
- 										results->dmif_burst_time[i][j]))),
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_last_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(add(
--										sub(
--											sub(
-+									(bw_add(
-+										bw_sub(
-+											bw_sub(
- 												results->maximum_latency_hiding_with_cursor[k],
- 												vbios->nbp_state_change_latency),
- 											results->dmif_burst_time[i][j]),
- 										results->active_time[k]))));
- 					} else {
- 						results->dram_speed_change_margin[i][j] =
--							bw_min(
-+							bw_min2(
- 								results->dram_speed_change_margin[i][j],
--								sub(
--									sub(
--										sub(
--											sub(
-+								bw_sub(
-+									bw_sub(
-+										bw_sub(
-+											bw_sub(
- 												results->maximum_latency_hiding_with_cursor[k],
- 												vbios->nbp_state_change_latency),
- 											results->dmif_burst_time[i][j]),
-@@ -2169,27 +2434,27 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 								results->dispclk_required_for_dram_speed_change[i][j],
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_first_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(sub(
--										sub(
--											sub(
-+									(bw_sub(
-+										bw_sub(
-+											bw_sub(
- 												results->maximum_latency_hiding_with_cursor[k],
- 												vbios->nbp_state_change_latency),
- 											results->dmif_burst_time[i][j]),
- 										results->mcifwr_burst_time[i][j]))),
- 								bw_div(
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->src_pixels_for_last_output_pixel[k],
- 											dceip->display_pipe_throughput_factor),
- 										dceip->lb_write_pixels_per_dispclk),
--									(add(
--										sub(
--											sub(
--												sub(
-+									(bw_add(
-+										bw_sub(
-+											bw_sub(
-+												bw_sub(
- 													results->maximum_latency_hiding_with_cursor[k],
- 													vbios->nbp_state_change_latency),
- 												results->dmif_burst_time[i][j]),
-@@ -2200,25 +2465,32 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	if (gtn(results->dram_speed_change_margin[high][high], int_to_fixed(0))
--		&& ltn(
-+	if (bw_mtn(
-+		results->dram_speed_change_margin[high][high],
-+		bw_int_to_fixed(0))
-+		&& bw_ltn(
- 			results->dispclk_required_for_dram_speed_change[high][high],
--			vbios->high_voltage_max_dispclk_mhz)) {
--		results->nbp_state_change_enable = true;
-+			vbios->high_voltage_max_dispclk)) {
-+		results->nbp_state_change_enable = bw_def_yes;
- 	} else {
--		results->nbp_state_change_enable = false;
--	}
--	results->min_cursor_memory_interface_buffer_size_in_time = int_to_fixed(
--		9999);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		results->nbp_state_change_enable = bw_def_no;
-+	}
-+	/*required yclk(pclk)*/
-+	/*yclk requirement only makes sense if the dmif and mcifwr data total page close-open time is less than the time for data transfer and the total pte requests fit in the scatter-gather saw queque size*/
-+	/*if that is the case, the yclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/low yclk(pclk) is chosen accordingly*/
-+	/*high yclk(pclk) has to be selected when dram speed/p-state change is not possible.*/
-+	results->min_cursor_memory_interface_buffer_size_in_time =
-+		bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (gtn(results->cursor_width_pixels[i],
--				int_to_fixed(0))) {
-+			if (bw_mtn(
-+				results->cursor_width_pixels[i],
-+				bw_int_to_fixed(0))) {
- 				results->min_cursor_memory_interface_buffer_size_in_time =
--					bw_min(
-+					bw_min2(
- 						results->min_cursor_memory_interface_buffer_size_in_time,
- 						bw_div(
--							mul(
-+							bw_mul(
- 								bw_div(
- 									bw_div(
- 										dceip->cursor_memory_interface_buffer_pixels,
-@@ -2229,13 +2501,13 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	results->min_read_buffer_size_in_time = bw_min(
-+	results->min_read_buffer_size_in_time = bw_min2(
- 		results->min_cursor_memory_interface_buffer_size_in_time,
- 		results->min_dmif_size_in_time);
--	results->display_reads_time_for_data_transfer = sub(
-+	results->display_reads_time_for_data_transfer = bw_sub(
- 		results->min_read_buffer_size_in_time,
- 		results->total_dmifmc_urgent_latency);
--	results->display_writes_time_for_data_transfer = sub(
-+	results->display_writes_time_for_data_transfer = bw_sub(
- 		results->min_mcifwr_size_in_time,
- 		vbios->mcifwrmc_urgent_latency);
- 	results->dmif_required_dram_bandwidth = bw_div(
-@@ -2245,340 +2517,419 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		results->total_display_writes_required_dram_access_data,
- 		results->display_writes_time_for_data_transfer);
- 	results->required_dmifmc_urgent_latency_for_page_close_open = bw_div(
--		(sub(results->min_read_buffer_size_in_time,
-+		(bw_sub(
-+			results->min_read_buffer_size_in_time,
- 			results->dmif_total_page_close_open_time)),
- 		results->total_dmifmc_urgent_trips);
--	results->required_mcifmcwr_urgent_latency = sub(
-+	results->required_mcifmcwr_urgent_latency = bw_sub(
- 		results->min_mcifwr_size_in_time,
- 		results->mcifwr_total_page_close_open_time);
--	if (gtn(results->scatter_gather_total_pte_requests,
-+	if (bw_mtn(
-+		results->scatter_gather_total_pte_requests,
- 		dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
- 		results->required_dram_bandwidth_gbyte_per_second =
--			int_to_fixed(9999);
-+			bw_int_to_fixed(9999);
- 		yclk_message =
--			def_exceeded_allowed_outstanding_pte_req_queue_size;
--		y_clk_level = high;
--		results->dram_bandwidth = mul(
--			bw_div(
--				mul(vbios->high_yclk_mhz,
--					vbios->dram_channel_width_in_bits),
--				int_to_fixed(8)),
--			vbios->number_of_dram_channels);
--	} else if (gtn(vbios->dmifmc_urgent_latency,
-+			bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
-+		results->y_clk_level = high;
-+		results->dram_bandwidth =
-+			bw_mul(
-+				bw_div(
-+					bw_mul(
-+						yclk[high],
-+						bw_int_to_fixed(
-+							vbios->dram_channel_width_in_bits)),
-+					bw_int_to_fixed(8)),
-+				bw_int_to_fixed(
-+					vbios->number_of_dram_channels));
-+	} else if (bw_mtn(
-+		vbios->dmifmc_urgent_latency,
- 		results->required_dmifmc_urgent_latency_for_page_close_open)
--		|| gtn(vbios->mcifwrmc_urgent_latency,
-+		|| bw_mtn(
-+			vbios->mcifwrmc_urgent_latency,
- 			results->required_mcifmcwr_urgent_latency)) {
- 		results->required_dram_bandwidth_gbyte_per_second =
--			int_to_fixed(9999);
--		yclk_message = def_exceeded_allowed_page_close_open;
--		y_clk_level = high;
--		results->dram_bandwidth = mul(
--			bw_div(
--				mul(vbios->high_yclk_mhz,
--					vbios->dram_channel_width_in_bits),
--				int_to_fixed(8)),
--			vbios->number_of_dram_channels);
-+			bw_int_to_fixed(9999);
-+		yclk_message = bw_def_exceeded_allowed_page_close_open;
-+		results->y_clk_level = high;
-+		results->dram_bandwidth =
-+			bw_mul(
-+				bw_div(
-+					bw_mul(
-+						yclk[high],
-+						bw_int_to_fixed(
-+							vbios->dram_channel_width_in_bits)),
-+					bw_int_to_fixed(8)),
-+				bw_int_to_fixed(
-+					vbios->number_of_dram_channels));
- 	} else {
- 		results->required_dram_bandwidth_gbyte_per_second = bw_div(
--			bw_max(results->dmif_required_dram_bandwidth,
-+			bw_max2(
-+				results->dmif_required_dram_bandwidth,
- 				results->mcifwr_required_dram_bandwidth),
--			int_to_fixed(1000));
--		if (ltn(
--			mul(results->required_dram_bandwidth_gbyte_per_second,
--				int_to_fixed(1000)),
--			mul(
-+			bw_int_to_fixed(1000));
-+		if (bw_ltn(
-+			bw_mul(
-+				results->required_dram_bandwidth_gbyte_per_second,
-+				bw_int_to_fixed(1000)),
-+			bw_mul(
- 				bw_div(
--					mul(vbios->low_yclk_mhz,
--						vbios->dram_channel_width_in_bits),
--					int_to_fixed(8)),
--				vbios->number_of_dram_channels))
--			&& (results->cpup_state_change_enable == false
--				|| (gtn(
-+					bw_mul(
-+						yclk[low],
-+						bw_int_to_fixed(
-+							vbios->dram_channel_width_in_bits)),
-+					bw_int_to_fixed(8)),
-+				bw_int_to_fixed(
-+					vbios->number_of_dram_channels)))
-+			&& (results->cpup_state_change_enable == bw_def_no
-+				|| (bw_mtn(
- 					results->blackout_duration_margin[low][high],
--					int_to_fixed(0))
--					&& ltn(
-+					bw_int_to_fixed(0))
-+					&& bw_ltn(
- 						results->dispclk_required_for_blackout_duration[low][high],
--						vbios->high_voltage_max_dispclk_mhz)))
--			&& (results->cpuc_state_change_enable == false
--				|| (gtn(
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->cpuc_state_change_enable == bw_def_no
-+				|| (bw_mtn(
- 					results->blackout_duration_margin[low][high],
--					int_to_fixed(0))
--					&& ltn(
-+					bw_int_to_fixed(0))
-+					&& bw_ltn(
- 						results->dispclk_required_for_blackout_duration[low][high],
--						vbios->high_voltage_max_dispclk_mhz)
--					&& ltn(
-+						vbios->high_voltage_max_dispclk)
-+					&& bw_ltn(
- 						results->dispclk_required_for_blackout_recovery[low][high],
--						vbios->high_voltage_max_dispclk_mhz)))
--			&& gtn(results->dram_speed_change_margin[low][high],
--				int_to_fixed(0))
--			&& ltn(
-+						vbios->high_voltage_max_dispclk)))
-+			&& bw_mtn(
-+				results->dram_speed_change_margin[low][high],
-+				bw_int_to_fixed(0))
-+			&& bw_ltn(
- 				results->dispclk_required_for_dram_speed_change[low][high],
--				vbios->high_voltage_max_dispclk_mhz)) {
--			yclk_message = def_low;
--			y_clk_level = low;
-+				vbios->high_voltage_max_dispclk)) {
-+			yclk_message = bw_def_low;
-+			results->y_clk_level = low;
- 			results->dram_bandwidth =
--				mul(
-+				bw_mul(
- 					bw_div(
--						mul(vbios->low_yclk_mhz,
--							vbios->dram_channel_width_in_bits),
--						int_to_fixed(8)),
--					vbios->number_of_dram_channels);
--		} else if (ltn(
--			mul(results->required_dram_bandwidth_gbyte_per_second,
--				int_to_fixed(1000)),
--			mul(
-+						bw_mul(
-+							yclk[low],
-+							bw_int_to_fixed(
-+								vbios->dram_channel_width_in_bits)),
-+						bw_int_to_fixed(8)),
-+					bw_int_to_fixed(
-+						vbios->number_of_dram_channels));
-+		} else if (bw_ltn(
-+			bw_mul(
-+				results->required_dram_bandwidth_gbyte_per_second,
-+				bw_int_to_fixed(1000)),
-+			bw_mul(
- 				bw_div(
--					mul(vbios->high_yclk_mhz,
--						vbios->dram_channel_width_in_bits),
--					int_to_fixed(8)),
--				vbios->number_of_dram_channels))) {
--			yclk_message = def_high;
--			y_clk_level = high;
-+					bw_mul(
-+						yclk[high],
-+						bw_int_to_fixed(
-+							vbios->dram_channel_width_in_bits)),
-+					bw_int_to_fixed(8)),
-+				bw_int_to_fixed(
-+					vbios->number_of_dram_channels)))) {
-+			yclk_message = bw_def_high;
-+			results->y_clk_level = high;
- 			results->dram_bandwidth =
--				mul(
-+				bw_mul(
- 					bw_div(
--						mul(vbios->high_yclk_mhz,
--							vbios->dram_channel_width_in_bits),
--						int_to_fixed(8)),
--					vbios->number_of_dram_channels);
-+						bw_mul(
-+							yclk[high],
-+							bw_int_to_fixed(
-+								vbios->dram_channel_width_in_bits)),
-+						bw_int_to_fixed(8)),
-+					bw_int_to_fixed(
-+						vbios->number_of_dram_channels));
- 		} else {
--			yclk_message = def_exceeded_allowed_maximum_bw;
--			y_clk_level = high;
-+			yclk_message = bw_def_exceeded_allowed_maximum_bw;
-+			results->y_clk_level = high;
- 			results->dram_bandwidth =
--				mul(
-+				bw_mul(
- 					bw_div(
--						mul(vbios->high_yclk_mhz,
--							vbios->dram_channel_width_in_bits),
--						int_to_fixed(8)),
--					vbios->number_of_dram_channels);
-+						bw_mul(
-+							yclk[high],
-+							bw_int_to_fixed(
-+								vbios->dram_channel_width_in_bits)),
-+						bw_int_to_fixed(8)),
-+					bw_int_to_fixed(
-+						vbios->number_of_dram_channels));
- 		}
- 	}
-+	/*required sclk*/
-+	/*sclk requirement only makes sense if the total pte requests fit in the scatter-gather saw queque size*/
-+	/*if that is the case, the sclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/mid/low sclk is chosen accordingly, unless that choice results in foresaking dram speed/nb p-state change.*/
-+	/*the dmif and mcifwr sclk required is the one that allows the transfer of all pipe's data buffer size through the sclk bus in the time for data transfer*/
-+	/*for dmif, pte and cursor requests have to be included.*/
- 	results->dmif_required_sclk = bw_div(
--		bw_div(results->total_display_reads_required_data,
-+		bw_div(
-+			results->total_display_reads_required_data,
- 			results->display_reads_time_for_data_transfer),
- 		vbios->data_return_bus_width);
- 	results->mcifwr_required_sclk = bw_div(
--		bw_div(results->total_display_writes_required_data,
-+		bw_div(
-+			results->total_display_writes_required_data,
- 			results->display_writes_time_for_data_transfer),
- 		vbios->data_return_bus_width);
--	if (gtn(results->scatter_gather_total_pte_requests,
-+	if (bw_mtn(
-+		results->scatter_gather_total_pte_requests,
- 		dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
--		results->required_sclk = int_to_fixed(9999);
-+		results->required_sclk = bw_int_to_fixed(9999);
- 		sclk_message =
--			def_exceeded_allowed_outstanding_pte_req_queue_size;
--		sclk_level = high;
--	} else if (gtn(vbios->dmifmc_urgent_latency,
-+			bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
-+		results->sclk_level = high;
-+	} else if (bw_mtn(
-+		vbios->dmifmc_urgent_latency,
- 		results->required_dmifmc_urgent_latency_for_page_close_open)
--		|| gtn(vbios->mcifwrmc_urgent_latency,
-+		|| bw_mtn(
-+			vbios->mcifwrmc_urgent_latency,
- 			results->required_mcifmcwr_urgent_latency)) {
--		results->required_sclk = int_to_fixed(9999);
--		sclk_message = def_exceeded_allowed_page_close_open;
--		sclk_level = high;
-+		results->required_sclk = bw_int_to_fixed(9999);
-+		sclk_message = bw_def_exceeded_allowed_page_close_open;
-+		results->sclk_level = high;
- 	} else {
--		results->required_sclk = bw_max(results->dmif_required_sclk,
-+		results->required_sclk = bw_max2(
-+			results->dmif_required_sclk,
- 			results->mcifwr_required_sclk);
--		if (ltn(results->required_sclk, vbios->low_sclk_mhz)
--			&& (results->cpup_state_change_enable == false
--				|| (gtn(
--					results->blackout_duration_margin[y_clk_level][low],
--					int_to_fixed(0))
--					&& ltn(
--						results->dispclk_required_for_blackout_duration[y_clk_level][low],
--						vbios->high_voltage_max_dispclk_mhz)))
--			&& (results->cpuc_state_change_enable == false
--				|| (gtn(
--					results->blackout_duration_margin[y_clk_level][low],
--					int_to_fixed(0))
--					&& ltn(
--						results->dispclk_required_for_blackout_duration[y_clk_level][low],
--						vbios->high_voltage_max_dispclk_mhz)
--					&& ltn(
--						results->dispclk_required_for_blackout_recovery[y_clk_level][low],
--						vbios->high_voltage_max_dispclk_mhz)))
--			&& (results->nbp_state_change_enable == false
--				|| (gtn(
--					results->dram_speed_change_margin[y_clk_level][low],
--					int_to_fixed(0))
--					&& leq(
--						results->dispclk_required_for_dram_speed_change[y_clk_level][low],
--						vbios->high_voltage_max_dispclk_mhz)))) {
--			sclk_message = def_low;
--			sclk_level = low;
--		} else if (ltn(results->required_sclk, vbios->mid_sclk_mhz)
--			&& (results->cpup_state_change_enable == false
--				|| (gtn(
--					results->blackout_duration_margin[y_clk_level][mid],
--					int_to_fixed(0))
--					&& ltn(
--						results->dispclk_required_for_blackout_duration[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk_mhz)))
--			&& (results->cpuc_state_change_enable == false
--				|| (gtn(
--					results->blackout_duration_margin[y_clk_level][mid],
--					int_to_fixed(0))
--					&& ltn(
--						results->dispclk_required_for_blackout_duration[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk_mhz)
--					&& ltn(
--						results->dispclk_required_for_blackout_recovery[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk_mhz)))
--			&& (results->nbp_state_change_enable == false
--				|| (gtn(
--					results->dram_speed_change_margin[y_clk_level][mid],
--					int_to_fixed(0))
--					&& leq(
--						results->dispclk_required_for_dram_speed_change[y_clk_level][mid],
--						vbios->high_voltage_max_dispclk_mhz)))) {
--			sclk_message = def_mid;
--			sclk_level = mid;
--		} else if (ltn(results->required_sclk, vbios->high_sclk_mhz)) {
--			sclk_message = def_high;
--			sclk_level = high;
-+		if (bw_ltn(results->required_sclk, sclk[low])
-+			&& (results->cpup_state_change_enable == bw_def_no
-+				|| (bw_mtn(
-+					results->blackout_duration_margin[results->y_clk_level][low],
-+					bw_int_to_fixed(0))
-+					&& bw_ltn(
-+						results->dispclk_required_for_blackout_duration[results->y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->cpuc_state_change_enable == bw_def_no
-+				|| (bw_mtn(
-+					results->blackout_duration_margin[results->y_clk_level][low],
-+					bw_int_to_fixed(0))
-+					&& bw_ltn(
-+						results->dispclk_required_for_blackout_duration[results->y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)
-+					&& bw_ltn(
-+						results->dispclk_required_for_blackout_recovery[results->y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->nbp_state_change_enable == bw_def_no
-+				|| (bw_mtn(
-+					results->dram_speed_change_margin[results->y_clk_level][low],
-+					bw_int_to_fixed(0))
-+					&& bw_leq(
-+						results->dispclk_required_for_dram_speed_change[results->y_clk_level][low],
-+						vbios->high_voltage_max_dispclk)))) {
-+			sclk_message = bw_def_low;
-+			results->sclk_level = low;
-+		} else if (bw_ltn(results->required_sclk, sclk[mid])
-+			&& (results->cpup_state_change_enable == bw_def_no
-+				|| (bw_mtn(
-+					results->blackout_duration_margin[results->y_clk_level][mid],
-+					bw_int_to_fixed(0))
-+					&& bw_ltn(
-+						results->dispclk_required_for_blackout_duration[results->y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->cpuc_state_change_enable == bw_def_no
-+				|| (bw_mtn(
-+					results->blackout_duration_margin[results->y_clk_level][mid],
-+					bw_int_to_fixed(0))
-+					&& bw_ltn(
-+						results->dispclk_required_for_blackout_duration[results->y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)
-+					&& bw_ltn(
-+						results->dispclk_required_for_blackout_recovery[results->y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)))
-+			&& (results->nbp_state_change_enable == bw_def_no
-+				|| (bw_mtn(
-+					results->dram_speed_change_margin[results->y_clk_level][mid],
-+					bw_int_to_fixed(0))
-+					&& bw_leq(
-+						results->dispclk_required_for_dram_speed_change[results->y_clk_level][mid],
-+						vbios->high_voltage_max_dispclk)))) {
-+			sclk_message = bw_def_mid;
-+			results->sclk_level = mid;
-+		} else if (bw_ltn(results->required_sclk, sclk[high])) {
-+			sclk_message = bw_def_high;
-+			results->sclk_level = high;
- 		} else {
--			sclk_message = def_exceeded_allowed_maximum_sclk;
--			sclk_level = high;
-+			sclk_message = bw_def_exceeded_allowed_maximum_sclk;
-+			results->sclk_level = high;
- 		}
- 	}
--	results->downspread_factor = add(
--		bw_div(vbios->down_spread_percentage, int_to_fixed(100)),
--		int_to_fixed(1));
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*dispclk*/
-+	/*if dispclk is set to the maximum, ramping is not required.  dispclk required without ramping is less than the dispclk required with ramping.*/
-+	/*if dispclk required without ramping is more than the maximum dispclk, that is the dispclk required, and the mode is not supported*/
-+	/*if that does not happen, but dispclk required with ramping is more than the maximum dispclk, dispclk required is just the maximum dispclk*/
-+	/*if that does not happen either, dispclk required is the dispclk required with ramping.*/
-+	/*dispclk required without ramping is the maximum of the one required for display pipe pixel throughput, for scaler throughput, for total read request thrrougput and for dram/np p-state change if enabled.*/
-+	/*the display pipe pixel throughput is the maximum of lines in per line out in the beginning of the frame and lines in per line out in the middle of the frame multiplied by the horizontal blank and chunk granularity factor, altogether multiplied by the ratio of the source width to the line time, divided by the line buffer pixels per dispclk throughput, and multiplied by the display pipe throughput factor.*/
-+	/*the horizontal blank and chunk granularity factor is the ratio of the line time divided by the line time minus half the horizontal blank and chunk time.  it applies when the lines in per line out is not 2 or 4.*/
-+	/*the dispclk required for scaler throughput is the product of the pixel rate and the scaling limits factor.*/
-+	/*the dispclk required for total read request throughput is the product of the peak request-per-second bandwidth and the dispclk cycles per request, divided by the request efficiency.*/
-+	/*for the dispclk required with ramping, instead of multiplying just the pipe throughput by the display pipe throughput factor, we multiply the scaler and pipe throughput by the ramping factor.*/
-+	/*the scaling limits factor is the product of the horizontal scale ratio, and the ratio of the vertical taps divided by the scaler efficiency clamped to at least 1.*/
-+	/*the scaling limits factor itself it also clamped to at least 1*/
-+	/*if doing downscaling with the pre-downscaler enabled, the horizontal scale ratio should not be considered above (use "1")*/
-+	results->downspread_factor = bw_add(
-+		bw_int_to_fixed(1),
-+		bw_div(vbios->down_spread_percentage, bw_int_to_fixed(100)));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] == def_graphics) {
--				if (equ(results->lb_bpc[i], int_to_fixed(6))) {
-+			if (surface_type[i] == bw_def_graphics) {
-+				switch (results->lb_bpc[i]) {
-+				case 6:
- 					results->v_scaler_efficiency =
- 						dceip->graphics_vscaler_efficiency6_bit_per_component;
--				} else if (equ(results->lb_bpc[i],
--					int_to_fixed(8))) {
-+					break;
-+				case 8:
- 					results->v_scaler_efficiency =
- 						dceip->graphics_vscaler_efficiency8_bit_per_component;
--				} else if (equ(results->lb_bpc[i],
--					int_to_fixed(10))) {
-+					break;
-+				case 10:
- 					results->v_scaler_efficiency =
- 						dceip->graphics_vscaler_efficiency10_bit_per_component;
--				} else {
-+					break;
-+				default:
- 					results->v_scaler_efficiency =
- 						dceip->graphics_vscaler_efficiency12_bit_per_component;
-+					break;
- 				}
--				if (results->use_alpha[i] == true) {
-+				if (results->use_alpha[i] == 1) {
- 					results->v_scaler_efficiency =
--						bw_min(
-+						bw_min2(
- 							results->v_scaler_efficiency,
- 							dceip->alpha_vscaler_efficiency);
- 				}
- 			} else {
--				if (equ(results->lb_bpc[i], int_to_fixed(6))) {
-+				switch (results->lb_bpc[i]) {
-+				case 6:
- 					results->v_scaler_efficiency =
- 						dceip->underlay_vscaler_efficiency6_bit_per_component;
--				} else if (equ(results->lb_bpc[i],
--					int_to_fixed(8))) {
-+					break;
-+				case 8:
- 					results->v_scaler_efficiency =
- 						dceip->underlay_vscaler_efficiency8_bit_per_component;
--				} else if (equ(results->lb_bpc[i],
--					int_to_fixed(10))) {
-+					break;
-+				case 10:
- 					results->v_scaler_efficiency =
- 						dceip->underlay_vscaler_efficiency10_bit_per_component;
--				} else {
-+					break;
-+				default:
- 					results->v_scaler_efficiency =
- 						dceip->underlay_vscaler_efficiency12_bit_per_component;
-+					break;
- 				}
- 			}
- 			if (dceip->pre_downscaler_enabled
--				&& gtn(results->hsr[i], int_to_fixed(1))) {
-+				&& bw_mtn(
-+					results->hsr[i],
-+					bw_int_to_fixed(1))) {
- 				results->scaler_limits_factor =
--					bw_max(
--						bw_div(results->v_taps[i],
-+					bw_max2(
-+						bw_div(
-+							results->v_taps[i],
- 							results->v_scaler_efficiency),
- 						bw_div(
- 							results->source_width_rounded_up_to_chunks[i],
- 							results->h_total[i]));
- 			} else {
- 				results->scaler_limits_factor =
--					bw_max3(int_to_fixed(1),
--						bw_ceil(
--							bw_div(results->h_taps[i],
--								int_to_fixed(
-+					bw_max3(
-+						bw_int_to_fixed(1),
-+						bw_ceil2(
-+							bw_div(
-+								results->h_taps[i],
-+								bw_int_to_fixed(
- 									4)),
--							int_to_fixed(1)),
--						mul(results->hsr[i],
--							bw_max(
-+							bw_int_to_fixed(1)),
-+						bw_mul(
-+							results->hsr[i],
-+							bw_max2(
- 								bw_div(
- 									results->v_taps[i],
- 									results->v_scaler_efficiency),
--								int_to_fixed(
-+								bw_int_to_fixed(
- 									1))));
- 			}
- 			results->display_pipe_pixel_throughput =
- 				bw_div(
- 					bw_div(
--						mul(
--							bw_max(
-+						bw_mul(
-+							bw_max2(
- 								results->lb_lines_in_per_line_out_in_beginning_of_frame[i],
--								mul(
-+								bw_mul(
- 									results->lb_lines_in_per_line_out_in_middle_of_frame[i],
- 									results->horizontal_blank_and_chunk_granularity_factor[i])),
- 							results->source_width_rounded_up_to_chunks[i]),
--						(bw_div(results->h_total[i],
-+						(bw_div(
-+							results->h_total[i],
- 							results->pixel_rate[i]))),
- 					dceip->lb_write_pixels_per_dispclk);
- 			results->dispclk_required_without_ramping[i] =
--				mul(results->downspread_factor,
--					bw_max(
--						mul(results->pixel_rate[i],
-+				bw_mul(
-+					results->downspread_factor,
-+					bw_max2(
-+						bw_mul(
-+							results->pixel_rate[i],
- 							results->scaler_limits_factor),
--						mul(
-+						bw_mul(
- 							dceip->display_pipe_throughput_factor,
- 							results->display_pipe_pixel_throughput)));
- 			results->dispclk_required_with_ramping[i] =
--				mul(dceip->dispclk_ramping_factor,
--					bw_max(
--						mul(results->pixel_rate[i],
-+				bw_mul(
-+					dceip->dispclk_ramping_factor,
-+					bw_max2(
-+						bw_mul(
-+							results->pixel_rate[i],
- 							results->scaler_limits_factor),
- 						results->display_pipe_pixel_throughput));
- 		}
- 	}
--	results->total_dispclk_required_with_ramping = int_to_fixed(0);
--	results->total_dispclk_required_without_ramping = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_dispclk_required_with_ramping = bw_int_to_fixed(0);
-+	results->total_dispclk_required_without_ramping = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (ltn(results->total_dispclk_required_with_ramping,
-+			if (bw_ltn(
-+				results->total_dispclk_required_with_ramping,
- 				results->dispclk_required_with_ramping[i])) {
- 				results->total_dispclk_required_with_ramping =
- 					results->dispclk_required_with_ramping[i];
- 			}
--			if (ltn(results->total_dispclk_required_without_ramping,
-+			if (bw_ltn(
-+				results->total_dispclk_required_without_ramping,
- 				results->dispclk_required_without_ramping[i])) {
- 				results->total_dispclk_required_without_ramping =
- 					results->dispclk_required_without_ramping[i];
- 			}
- 		}
- 	}
--	results->total_read_request_bandwidth = int_to_fixed(0);
--	results->total_write_request_bandwidth = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_read_request_bandwidth = bw_int_to_fixed(0);
-+	results->total_write_request_bandwidth = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma) {
--				results->total_read_request_bandwidth = add(
-+					!= bw_def_display_write_back420_chroma) {
-+				results->total_read_request_bandwidth = bw_add(
- 					results->total_read_request_bandwidth,
- 					results->request_bandwidth[i]);
- 			} else {
--				results->total_write_request_bandwidth = add(
-+				results->total_write_request_bandwidth = bw_add(
- 					results->total_write_request_bandwidth,
- 					results->request_bandwidth[i]);
- 			}
- 		}
- 	}
- 	results->dispclk_required_for_total_read_request_bandwidth = bw_div(
--		mul(results->total_read_request_bandwidth,
--			dceip->dispclk_per_request), dceip->request_efficiency);
--	if (equ(dceip->dcfclk_request_generation, int_to_fixed(0))) {
-+		bw_mul(
-+			results->total_read_request_bandwidth,
-+			dceip->dispclk_per_request),
-+		dceip->request_efficiency);
-+	if (dceip->dcfclk_request_generation == 0) {
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth =
--			bw_max(results->total_dispclk_required_with_ramping,
-+			bw_max2(
-+				results->total_dispclk_required_with_ramping,
- 				results->dispclk_required_for_total_read_request_bandwidth);
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth =
--			bw_max(results->total_dispclk_required_without_ramping,
-+			bw_max2(
-+				results->total_dispclk_required_without_ramping,
- 				results->dispclk_required_for_total_read_request_bandwidth);
- 	} else {
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth =
-@@ -2586,236 +2937,225 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth =
- 			results->total_dispclk_required_without_ramping;
- 	}
--	if (results->cpuc_state_change_enable == true) {
-+	if (results->cpuc_state_change_enable == bw_def_yes) {
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth =
- 			bw_max3(
- 				results->total_dispclk_required_with_ramping_with_request_bandwidth,
--				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level],
--				results->dispclk_required_for_blackout_recovery[y_clk_level][sclk_level]);
-+				results->dispclk_required_for_blackout_duration[results->y_clk_level][results->sclk_level],
-+				results->dispclk_required_for_blackout_recovery[results->y_clk_level][results->sclk_level]);
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth =
- 			bw_max3(
- 				results->total_dispclk_required_without_ramping_with_request_bandwidth,
--				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level],
--				results->dispclk_required_for_blackout_recovery[y_clk_level][sclk_level]);
-+				results->dispclk_required_for_blackout_duration[results->y_clk_level][results->sclk_level],
-+				results->dispclk_required_for_blackout_recovery[results->y_clk_level][results->sclk_level]);
- 	}
--	if (results->cpup_state_change_enable == true) {
-+	if (results->cpup_state_change_enable == bw_def_yes) {
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth =
--			bw_max(
-+			bw_max2(
- 				results->total_dispclk_required_with_ramping_with_request_bandwidth,
--				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level]);
-+				results->dispclk_required_for_blackout_duration[results->y_clk_level][results->sclk_level]);
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth =
--			bw_max(
-+			bw_max2(
- 				results->total_dispclk_required_without_ramping_with_request_bandwidth,
--				results->dispclk_required_for_blackout_duration[y_clk_level][sclk_level]);
-+				results->dispclk_required_for_blackout_duration[results->y_clk_level][results->sclk_level]);
- 	}
--	if (results->nbp_state_change_enable == true) {
-+	if (results->nbp_state_change_enable == bw_def_yes) {
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth =
--			bw_max(
-+			bw_max2(
- 				results->total_dispclk_required_with_ramping_with_request_bandwidth,
--				results->dispclk_required_for_dram_speed_change[y_clk_level][sclk_level]);
-+				results->dispclk_required_for_dram_speed_change[results->y_clk_level][results->sclk_level]);
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth =
--			bw_max(
-+			bw_max2(
- 				results->total_dispclk_required_without_ramping_with_request_bandwidth,
--				results->dispclk_required_for_dram_speed_change[y_clk_level][sclk_level]);
-+				results->dispclk_required_for_dram_speed_change[results->y_clk_level][results->sclk_level]);
- 	}
--	if (ltn(
-+	if (bw_ltn(
- 		results->total_dispclk_required_with_ramping_with_request_bandwidth,
--		vbios->high_voltage_max_dispclk_mhz)) {
-+		vbios->high_voltage_max_dispclk)) {
- 		results->dispclk =
- 			results->total_dispclk_required_with_ramping_with_request_bandwidth;
--	} else if (ltn(
-+	} else if (bw_ltn(
- 		results->total_dispclk_required_without_ramping_with_request_bandwidth,
--		vbios->high_voltage_max_dispclk_mhz)) {
--		results->dispclk = vbios->high_voltage_max_dispclk_mhz;
-+		vbios->high_voltage_max_dispclk)) {
-+		results->dispclk = vbios->high_voltage_max_dispclk;
- 	} else {
- 		results->dispclk =
- 			results->total_dispclk_required_without_ramping_with_request_bandwidth;
- 	}
--	if (pipe_check == def_notok) {
--		voltage = def_na;
--		mode_background_color = def_na_color;
--		mode_font_color = def_vb_white;
--	} else if (mode_check == def_notok) {
--		voltage = def_notok;
--		mode_background_color = def_notok_color;
--		mode_font_color = def_vb_black;
--	} else if (yclk_message == def_low && sclk_message == def_low
--		&& ltn(results->dispclk, vbios->low_voltage_max_dispclk_mhz)) {
--		voltage = def_low;
--		mode_background_color = def_low_color;
--		mode_font_color = def_vb_black;
--	} else if (yclk_message == def_low
--		&& (sclk_message == def_low || sclk_message == def_mid)
--		&& ltn(results->dispclk, vbios->mid_voltage_max_dispclk_mhz)) {
--		voltage = def_mid;
--		mode_background_color = def_mid_color;
--		mode_font_color = def_vb_black;
--	} else if ((yclk_message == def_low || yclk_message == def_high)
--		&& (sclk_message == def_low || sclk_message == def_mid
--			|| sclk_message == def_high)
--		&& leq(results->dispclk, vbios->high_voltage_max_dispclk_mhz)) {
--		if (results->nbp_state_change_enable == true) {
--			voltage = def_high;
--			mode_background_color = def_high_color;
--			mode_font_color = def_vb_black;
-+	/* required core voltage*/
-+	/* the core voltage required is low if sclk, yclk(pclk)and dispclk are within the low limits*/
-+	/* otherwise, the core voltage required is medium if yclk (pclk) is within the low limit and sclk and dispclk are within the medium limit*/
-+	/* otherwise, the core voltage required is high if the three clocks are within the high limits*/
-+	/* otherwise, or if the mode is not supported, core voltage requirement is not applicable*/
-+	if (pipe_check == bw_def_notok) {
-+		voltage = bw_def_na;
-+	} else if (mode_check == bw_def_notok) {
-+		voltage = bw_def_notok;
-+	} else if (yclk_message == bw_def_low && sclk_message == bw_def_low
-+		&& bw_ltn(results->dispclk, vbios->low_voltage_max_dispclk)) {
-+		voltage = bw_def_low;
-+	} else if (yclk_message == bw_def_low
-+		&& (sclk_message == bw_def_low || sclk_message == bw_def_mid)
-+		&& bw_ltn(results->dispclk, vbios->mid_voltage_max_dispclk)) {
-+		voltage = bw_def_mid;
-+	} else if ((yclk_message == bw_def_low || yclk_message == bw_def_high)
-+		&& (sclk_message == bw_def_low || sclk_message == bw_def_mid
-+			|| sclk_message == bw_def_high)
-+		&& bw_leq(results->dispclk, vbios->high_voltage_max_dispclk)) {
-+		if (results->nbp_state_change_enable == bw_def_yes) {
-+			voltage = bw_def_high;
- 		} else {
--			voltage = def_high_no_nbp_state_change;
--			mode_background_color =
--				def_high_no_nbp_state_change_color;
--			mode_font_color = def_vb_black;
-+			voltage = bw_def_high_no_nbp_state_change;
- 		}
- 	} else {
--		voltage = def_notok;
--		mode_background_color = def_notok_color;
--		mode_font_color = def_vb_black;
--	}
--	if (mode_background_color == def_na_color
--		|| mode_background_color == def_notok_color) {
--		mode_pattern = def_xl_pattern_solid;
--	} else if (results->cpup_state_change_enable == false) {
--		mode_pattern = def_xl_pattern_checker;
--	} else if (results->cpuc_state_change_enable == false) {
--		mode_pattern = def_xl_pattern_light_horizontal;
--	} else {
--		mode_pattern = def_xl_pattern_solid;
-+		voltage = bw_def_notok;
- 	}
--	results->blackout_recovery_time = int_to_fixed(0);
--	for (k = 0; k <= maximum_number_of_surfaces - 1; k += 1) {
-+	/*required blackout recovery time*/
-+	results->blackout_recovery_time = bw_int_to_fixed(0);
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
- 		if (results->enable[k]
--			&& gtn(vbios->blackout_duration, int_to_fixed(0))
--			&& results->cpup_state_change_enable == true) {
--			if (surface_type[k] != def_display_write_back420_luma
-+			&& bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))
-+			&& results->cpup_state_change_enable == bw_def_yes) {
-+			if (surface_type[k] != bw_def_display_write_back420_luma
- 				&& surface_type[k]
--					!= def_display_write_back420_chroma) {
-+					!= bw_def_display_write_back420_chroma) {
- 				results->blackout_recovery_time =
--					bw_max(results->blackout_recovery_time,
--						add(
--							mul(
--								results->total_dmifmc_urgent_latency,
--								int_to_fixed(
--									2)),
--							results->dmif_burst_time[y_clk_level][sclk_level]));
--				if (ltn(results->adjusted_data_buffer_size[k],
--					mul(
-+					bw_max2(
-+						results->blackout_recovery_time,
-+						bw_add(
-+							bw_mul(
-+								bw_int_to_fixed(
-+									2),
-+								results->total_dmifmc_urgent_latency),
-+							results->dmif_burst_time[results->y_clk_level][results->sclk_level]));
-+				if (bw_ltn(
-+					results->adjusted_data_buffer_size[k],
-+					bw_mul(
- 						bw_div(
--							mul(
-+							bw_mul(
- 								results->display_bandwidth[k],
- 								results->useful_bytes_per_request[k]),
- 							results->bytes_per_request[k]),
--						(add(
--							add(
--								vbios->blackout_duration,
--								mul(
--									results->total_dmifmc_urgent_latency,
--									int_to_fixed(
--										2))),
--							results->dmif_burst_time[y_clk_level][sclk_level]))))) {
-+						(bw_add(
-+							vbios->blackout_duration,
-+							bw_add(
-+								bw_mul(
-+									bw_int_to_fixed(
-+										2),
-+									results->total_dmifmc_urgent_latency),
-+								results->dmif_burst_time[results->y_clk_level][results->sclk_level])))))) {
- 					results->blackout_recovery_time =
--						bw_max(
-+						bw_max2(
- 							results->blackout_recovery_time,
- 							bw_div(
--								(sub(
--									add(
--										mul(
--											bw_div(
--												mul(
--													results->display_bandwidth[k],
--													results->useful_bytes_per_request[k]),
--												results->bytes_per_request[k]),
--											vbios->blackout_duration),
-+								(bw_add(
-+									bw_mul(
-+										bw_div(
-+											bw_mul(
-+												results->display_bandwidth[k],
-+												results->useful_bytes_per_request[k]),
-+											results->bytes_per_request[k]),
-+										vbios->blackout_duration),
-+									bw_sub(
- 										bw_div(
--											mul(
--												mul(
--													mul(
--														(add(
--															mul(
--																results->total_dmifmc_urgent_latency,
--																int_to_fixed(
--																	2)),
--															results->dmif_burst_time[y_clk_level][sclk_level])),
-+											bw_mul(
-+												bw_mul(
-+													bw_mul(
-+														(bw_add(
-+															bw_mul(
-+																bw_int_to_fixed(
-+																	2),
-+																results->total_dmifmc_urgent_latency),
-+															results->dmif_burst_time[results->y_clk_level][results->sclk_level])),
- 														results->dispclk),
--													results->bytes_per_pixel[k]),
-+													bw_int_to_fixed(
-+														results->bytes_per_pixel[k])),
- 												results->lines_interleaved_in_mem_access[k]),
--											results->latency_hiding_lines[k])),
--									results->adjusted_data_buffer_size[k])),
--								(sub(
-+											results->latency_hiding_lines[k]),
-+										results->adjusted_data_buffer_size[k]))),
-+								(bw_sub(
- 									bw_div(
--										mul(
--											mul(
-+										bw_mul(
-+											bw_mul(
- 												results->dispclk,
--												results->bytes_per_pixel[k]),
-+												bw_int_to_fixed(
-+													results->bytes_per_pixel[k])),
- 											results->lines_interleaved_in_mem_access[k]),
- 										results->latency_hiding_lines[k]),
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->display_bandwidth[k],
- 											results->useful_bytes_per_request[k]),
- 										results->bytes_per_request[k])))));
- 				}
- 			} else {
- 				results->blackout_recovery_time =
--					bw_max(results->blackout_recovery_time,
--						add(
--							mul(
--								vbios->mcifwrmc_urgent_latency,
--								int_to_fixed(
--									2)),
--							results->mcifwr_burst_time[y_clk_level][sclk_level]));
--				if (ltn(results->adjusted_data_buffer_size[k],
--					mul(
-+					bw_max2(
-+						results->blackout_recovery_time,
-+						bw_add(
-+							bw_mul(
-+								bw_int_to_fixed(
-+									2),
-+								vbios->mcifwrmc_urgent_latency),
-+							results->mcifwr_burst_time[results->y_clk_level][results->sclk_level]));
-+				if (bw_ltn(
-+					results->adjusted_data_buffer_size[k],
-+					bw_mul(
- 						bw_div(
--							mul(
-+							bw_mul(
- 								results->display_bandwidth[k],
- 								results->useful_bytes_per_request[k]),
- 							results->bytes_per_request[k]),
--						(add(
--							add(
--								vbios->blackout_duration,
--								mul(
--									vbios->mcifwrmc_urgent_latency,
--									int_to_fixed(
--										2))),
--							results->mcifwr_burst_time[y_clk_level][sclk_level]))))) {
-+						(bw_add(
-+							vbios->blackout_duration,
-+							bw_add(
-+								bw_mul(
-+									bw_int_to_fixed(
-+										2),
-+									vbios->mcifwrmc_urgent_latency),
-+								results->mcifwr_burst_time[results->y_clk_level][results->sclk_level])))))) {
- 					results->blackout_recovery_time =
--						bw_max(
-+						bw_max2(
- 							results->blackout_recovery_time,
- 							bw_div(
--								(sub(
--									add(
--										mul(
--											bw_div(
--												mul(
--													results->display_bandwidth[k],
--													results->useful_bytes_per_request[k]),
--												results->bytes_per_request[k]),
--											vbios->blackout_duration),
-+								(bw_add(
-+									bw_mul(
-+										bw_div(
-+											bw_mul(
-+												results->display_bandwidth[k],
-+												results->useful_bytes_per_request[k]),
-+											results->bytes_per_request[k]),
-+										vbios->blackout_duration),
-+									bw_sub(
- 										bw_div(
--											mul(
--												mul(
--													mul(
--														(add(
--															add(
--																mul(
--																	vbios->mcifwrmc_urgent_latency,
--																	int_to_fixed(
--																		2)),
-+											bw_mul(
-+												bw_mul(
-+													bw_mul(
-+														(bw_add(
-+															bw_add(
-+																bw_mul(
-+																	bw_int_to_fixed(
-+																		2),
-+																	vbios->mcifwrmc_urgent_latency),
- 																results->dmif_burst_time[i][j]),
--															results->mcifwr_burst_time[y_clk_level][sclk_level])),
-+															results->mcifwr_burst_time[results->y_clk_level][results->sclk_level])),
- 														results->dispclk),
--													results->bytes_per_pixel[k]),
-+													bw_int_to_fixed(
-+														results->bytes_per_pixel[k])),
- 												results->lines_interleaved_in_mem_access[k]),
--											results->latency_hiding_lines[k])),
--									results->adjusted_data_buffer_size[k])),
--								(sub(
-+											results->latency_hiding_lines[k]),
-+										results->adjusted_data_buffer_size[k]))),
-+								(bw_sub(
- 									bw_div(
--										mul(
--											mul(
-+										bw_mul(
-+											bw_mul(
- 												results->dispclk,
--												results->bytes_per_pixel[k]),
-+												bw_int_to_fixed(
-+													results->bytes_per_pixel[k])),
- 											results->lines_interleaved_in_mem_access[k]),
- 										results->latency_hiding_lines[k]),
- 									bw_div(
--										mul(
-+										bw_mul(
- 											results->display_bandwidth[k],
- 											results->useful_bytes_per_request[k]),
- 										results->bytes_per_request[k])))));
-@@ -2823,179 +3163,229 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 			}
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*sclk deep sleep*/
-+	/*during self-refresh, sclk can be reduced to dispclk divided by the minimum pixels in the data fifo entry, with 15% margin, but shoudl not be set to less than the request bandwidth.*/
-+	/*the data fifo entry is 16 pixels for the writeback, 64 bytes/bytes_per_pixel for the graphics, 16 pixels for the parallel rotation underlay,*/
-+	/*and 16 bytes/bytes_per_pixel for the orthogonal rotation underlay.*/
-+	/*in parallel mode (underlay pipe), the data read from the dmifv buffer is variable and based on the pixel depth (8bbp - 16 bytes, 16 bpp - 32 bytes, 32 bpp - 64 bytes)*/
-+	/*in orthogonal mode (underlay pipe), the data read from the dmifv buffer is fixed at 16 bytes.*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (surface_type[i] == def_display_write_back420_luma
-+			if (surface_type[i] == bw_def_display_write_back420_luma
- 				|| surface_type[i]
--					== def_display_write_back420_chroma) {
-+					== bw_def_display_write_back420_chroma) {
- 				results->pixels_per_data_fifo_entry[i] =
--					int_to_fixed(16);
--			} else if (surface_type[i] == def_graphics) {
-+					bw_int_to_fixed(16);
-+			} else if (surface_type[i] == bw_def_graphics) {
- 				results->pixels_per_data_fifo_entry[i] = bw_div(
--					int_to_fixed(64),
--					results->bytes_per_pixel[i]);
--			} else if (results->orthogonal_rotation[i] == false) {
-+					bw_int_to_fixed(64),
-+					bw_int_to_fixed(
-+						results->bytes_per_pixel[i]));
-+			} else if (results->orthogonal_rotation[i] == 0) {
- 				results->pixels_per_data_fifo_entry[i] =
--					int_to_fixed(16);
-+					bw_int_to_fixed(16);
- 			} else {
- 				results->pixels_per_data_fifo_entry[i] = bw_div(
--					int_to_fixed(16),
--					results->bytes_per_pixel[i]);
-+					bw_int_to_fixed(16),
-+					bw_int_to_fixed(
-+						results->bytes_per_pixel[i]));
- 			}
- 		}
- 	}
--	results->min_pixels_per_data_fifo_entry = int_to_fixed(9999);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->min_pixels_per_data_fifo_entry = bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (gtn(results->min_pixels_per_data_fifo_entry,
-+			if (bw_mtn(
-+				results->min_pixels_per_data_fifo_entry,
- 				results->pixels_per_data_fifo_entry[i])) {
- 				results->min_pixels_per_data_fifo_entry =
- 					results->pixels_per_data_fifo_entry[i];
- 			}
- 		}
- 	}
--	results->sclk_deep_sleep = bw_max(
--		bw_div(mul(results->dispclk, frc_to_fixed(115, 100)),
-+	results->sclk_deep_sleep = bw_max2(
-+		bw_div(
-+			bw_mul(results->dispclk, bw_frc_to_fixed(115, 100)),
- 			results->min_pixels_per_data_fifo_entry),
- 		results->total_read_request_bandwidth);
--	results->chunk_request_time = int_to_fixed(0);
--	results->cursor_request_time = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*urgent, stutter and nb-p_state watermark*/
-+	/*the urgent watermark is the maximum of the urgent trip time plus the pixel transfer time, the urgent trip times to get data for the first pixel, and the urgent trip times to get data for the last pixel.*/
-+	/*the stutter exit watermark is the self refresh exit time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.  it does not apply to the writeback.*/
-+	/*the nb p-state change watermark is the dram speed/p-state change time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.*/
-+	/*the pixel transfer time is the maximum of the time to transfer the source pixels required for the first output pixel, and the time to transfer the pixels for the last output pixel minus the active line time.*/
-+	/*blackout_duration is added to the urgent watermark*/
-+	results->chunk_request_time = bw_int_to_fixed(0);
-+	results->cursor_request_time = bw_int_to_fixed(0);
-+	/*compute total time to request one chunk from each active display pipe*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			results->chunk_request_time =
--				add(results->chunk_request_time,
--					bw_div(
--						bw_div(
--							mul(pixels_per_chunk,
--								results->bytes_per_pixel[i]),
--							results->useful_bytes_per_request[i]),
--						bw_min(sclk[sclk_level],
--							bw_div(results->dispclk,
--								int_to_fixed(
--									2)))));
-+				bw_add(
-+					results->chunk_request_time,
-+					(bw_div(
-+						(bw_div(
-+							bw_int_to_fixed(
-+								pixels_per_chunk
-+									* results->bytes_per_pixel[i]),
-+							results->useful_bytes_per_request[i])),
-+						bw_min2(
-+							sclk[results->sclk_level],
-+							bw_div(
-+								results->dispclk,
-+								bw_int_to_fixed(
-+									2))))));
- 		}
- 	}
--	results->cursor_request_time = (bw_div(results->cursor_total_data,
--		(mul(sclk[sclk_level], int_to_fixed(32)))));
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*compute total time to request cursor data*/
-+	results->cursor_request_time = (bw_div(
-+		results->cursor_total_data,
-+		(bw_mul(bw_int_to_fixed(32), sclk[results->sclk_level]))));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			results->line_source_pixels_transfer_time =
--				bw_max(
-+				bw_max2(
- 					bw_div(
- 						bw_div(
- 							results->src_pixels_for_first_output_pixel[i],
- 							dceip->lb_write_pixels_per_dispclk),
--						(bw_div(results->dispclk,
-+						(bw_div(
-+							results->dispclk,
- 							dceip->display_pipe_throughput_factor))),
--					sub(
-+					bw_sub(
- 						bw_div(
- 							bw_div(
- 								results->src_pixels_for_last_output_pixel[i],
- 								dceip->lb_write_pixels_per_dispclk),
--							(bw_div(results->dispclk,
-+							(bw_div(
-+								results->dispclk,
- 								dceip->display_pipe_throughput_factor))),
- 						results->active_time[i]));
--			if (surface_type[i] != def_display_write_back420_luma
-+			if (surface_type[i] != bw_def_display_write_back420_luma
- 				&& surface_type[i]
--					!= def_display_write_back420_chroma) {
-+					!= bw_def_display_write_back420_chroma) {
- 				results->urgent_watermark[i] =
--					add(
--						add(
--							add(
--								add(
--									add(
-+					bw_add(
-+						bw_add(
-+							bw_add(
-+								bw_add(
-+									bw_add(
- 										results->total_dmifmc_urgent_latency,
--										results->dmif_burst_time[y_clk_level][sclk_level]),
--									bw_max(
-+										results->dmif_burst_time[results->y_clk_level][results->sclk_level]),
-+									bw_max2(
- 										results->line_source_pixels_transfer_time,
--										results->line_source_transfer_time[i][y_clk_level][sclk_level])),
-+										results->line_source_transfer_time[i][results->y_clk_level][results->sclk_level])),
- 								vbios->blackout_duration),
- 							results->chunk_request_time),
- 						results->cursor_request_time);
- 				results->stutter_exit_watermark[i] =
--					add(
--						sub(
-+					bw_add(
-+						bw_sub(
- 							vbios->stutter_self_refresh_exit_latency,
- 							results->total_dmifmc_urgent_latency),
- 						results->urgent_watermark[i]);
-+				/*unconditionally remove black out time from the nb p_state watermark*/
- 				results->nbp_state_change_watermark[i] =
--					sub(
--						add(
--							sub(
-+					bw_sub(
-+						bw_add(
-+							bw_sub(
- 								vbios->nbp_state_change_latency,
- 								results->total_dmifmc_urgent_latency),
- 							results->urgent_watermark[i]),
- 						vbios->blackout_duration);
- 			} else {
- 				results->urgent_watermark[i] =
--					add(
--						add(
--							add(
--								add(
--									add(
-+					bw_add(
-+						bw_add(
-+							bw_add(
-+								bw_add(
-+									bw_add(
- 										vbios->mcifwrmc_urgent_latency,
--										results->mcifwr_burst_time[y_clk_level][sclk_level]),
--									bw_max(
-+										results->mcifwr_burst_time[results->y_clk_level][results->sclk_level]),
-+									bw_max2(
- 										results->line_source_pixels_transfer_time,
--										results->line_source_transfer_time[i][y_clk_level][sclk_level])),
-+										results->line_source_transfer_time[i][results->y_clk_level][results->sclk_level])),
- 								vbios->blackout_duration),
- 							results->chunk_request_time),
- 						results->cursor_request_time);
- 				results->stutter_exit_watermark[i] =
--					int_to_fixed(0);
-+					bw_int_to_fixed(0);
- 				results->nbp_state_change_watermark[i] =
--					add(
--						sub(
--							add(
-+					bw_add(
-+						bw_sub(
-+							bw_add(
- 								vbios->nbp_state_change_latency,
--								results->dmif_burst_time[y_clk_level][sclk_level]),
-+								results->dmif_burst_time[results->y_clk_level][results->sclk_level]),
- 							vbios->mcifwrmc_urgent_latency),
- 						results->urgent_watermark[i]);
- 			}
- 		}
- 	}
-+	/*stutter mode enable*/
-+	/*in the multi-display case the stutter exit watermark cannot exceed the cursor dcp buffer size*/
- 	results->stutter_mode_enable = results->cpuc_state_change_enable;
- 	if (mode_data->number_of_displays > 1) {
--		for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+		for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 			if (results->enable[i]) {
--				if (gtn(results->stutter_exit_watermark[i],
-+				if (bw_mtn(
-+					results->stutter_exit_watermark[i],
- 					results->cursor_latency_hiding[i])) {
--					results->stutter_mode_enable = false;
-+					results->stutter_mode_enable =
-+						bw_def_no;
- 				}
- 			}
- 		}
- 	}
-+	/*performance metrics*/
-+	/* display read access efficiency (%)*/
-+	/* display write back access efficiency (%)*/
-+	/* stutter efficiency (%)*/
-+	/* extra underlay pitch recommended for efficiency (pixels)*/
-+	/* immediate flip time (us)*/
-+	/* latency for other clients due to urgent display read (us)*/
-+	/* latency for other clients due to urgent display write (us)*/
-+	/* average bandwidth consumed by display (no compression) (gb/s)*/
-+	/* required dram  bandwidth (gb/s)*/
-+	/* required sclk (m_hz)*/
-+	/* required rd urgent latency (us)*/
-+	/* nb p-state change margin (us)*/
-+	/*dmif and mcifwr dram access efficiency*/
-+	/*is the ratio between the ideal dram access time (which is the data buffer size in memory divided by the dram bandwidth), and the actual time which is the total page close-open time.  but it cannot exceed the dram efficiency provided by the memory subsystem*/
- 	results->dmifdram_access_efficiency =
--		bw_min(
-+		bw_min2(
- 			bw_div(
- 				bw_div(
- 					results->total_display_reads_required_dram_access_data,
- 					results->dram_bandwidth),
- 				results->dmif_total_page_close_open_time),
--			int_to_fixed(1));
--	if (gtn(results->total_display_writes_required_dram_access_data,
--		int_to_fixed(0))) {
-+			bw_int_to_fixed(1));
-+	if (bw_mtn(
-+		results->total_display_writes_required_dram_access_data,
-+		bw_int_to_fixed(0))) {
- 		results->mcifwrdram_access_efficiency =
--			bw_min(
-+			bw_min2(
- 				bw_div(
- 					bw_div(
- 						results->total_display_writes_required_dram_access_data,
- 						results->dram_bandwidth),
- 					results->mcifwr_total_page_close_open_time),
--				int_to_fixed(1));
-+				bw_int_to_fixed(1));
- 	} else {
--		results->mcifwrdram_access_efficiency = int_to_fixed(0);
-+		results->mcifwrdram_access_efficiency = bw_int_to_fixed(0);
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*average bandwidth*/
-+	/*the average bandwidth with no compression is the vertical active time is the source width times the bytes per pixel divided by the line time, multiplied by the vertical scale ratio and the ratio of bytes per request divided by the useful bytes per request.*/
-+	/*the average bandwidth with compression is the same, divided by the compression ratio*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			results->average_bandwidth_no_compression[i] =
- 				bw_div(
--					mul(
--						mul(
-+					bw_mul(
-+						bw_mul(
- 							bw_div(
--								mul(
-+								bw_mul(
- 									results->source_width_rounded_up_to_chunks[i],
--									results->bytes_per_pixel[i]),
-+									bw_int_to_fixed(
-+										results->bytes_per_pixel[i])),
- 								(bw_div(
- 									results->h_total[i],
- 									results->pixel_rate[i]))),
-@@ -3007,52 +3397,61 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 				results->compression_rate[i]);
- 		}
- 	}
--	results->total_average_bandwidth_no_compression = int_to_fixed(0);
--	results->total_average_bandwidth = int_to_fixed(0);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_average_bandwidth_no_compression = bw_int_to_fixed(0);
-+	results->total_average_bandwidth = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			results->total_average_bandwidth_no_compression = add(
--				results->total_average_bandwidth_no_compression,
--				results->average_bandwidth_no_compression[i]);
--			results->total_average_bandwidth = add(
-+			results->total_average_bandwidth_no_compression =
-+				bw_add(
-+					results->total_average_bandwidth_no_compression,
-+					results->average_bandwidth_no_compression[i]);
-+			results->total_average_bandwidth = bw_add(
- 				results->total_average_bandwidth,
- 				results->average_bandwidth[i]);
- 		}
- 	}
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*stutter efficiency*/
-+	/*the stutter efficiency is the frame-average time in self-refresh divided by the frame-average stutter cycle duration.  only applies if the display write-back is not enabled.*/
-+	/*the frame-average stutter cycle used is the minimum for all pipes of the frame-average data buffer size in time, times the compression rate*/
-+	/*the frame-average time in self-refresh is the stutter cycle minus the self refresh exit latency and the burst time*/
-+	/*the stutter cycle is the dmif buffer size reduced by the excess of the stutter exit watermark over the lb size in time.*/
-+	/*the burst time is the data needed during the stutter cycle divided by the available bandwidth*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			results->stutter_cycle_duration[i] =
--				sub(
--					mul(
-+				bw_sub(
-+					bw_mul(
- 						bw_div(
- 							bw_div(
--								mul(
-+								bw_mul(
- 									bw_div(
- 										bw_div(
- 											results->adjusted_data_buffer_size[i],
--											results->bytes_per_pixel[i]),
-+											bw_int_to_fixed(
-+												results->bytes_per_pixel[i])),
- 										results->source_width_rounded_up_to_chunks[i]),
- 									results->h_total[i]),
- 								results->vsr[i]),
- 							results->pixel_rate[i]),
- 						results->compression_rate[i]),
--					bw_max(int_to_fixed(0),
--						sub(
-+					bw_max2(
-+						bw_int_to_fixed(0),
-+						bw_sub(
- 							results->stutter_exit_watermark[i],
- 							bw_div(
--								mul(
--									(add(
--										results->line_buffer_prefetch[i],
--										int_to_fixed(
--											2))),
-+								bw_mul(
-+									bw_int_to_fixed(
-+										(2
-+											+ results->line_buffer_prefetch[i])),
- 									results->h_total[i]),
- 								results->pixel_rate[i]))));
- 		}
- 	}
--	results->total_stutter_cycle_duration = int_to_fixed(9999);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	results->total_stutter_cycle_duration = bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
--			if (gtn(results->total_stutter_cycle_duration,
-+			if (bw_mtn(
-+				results->total_stutter_cycle_duration,
- 				results->stutter_cycle_duration[i])) {
- 				results->total_stutter_cycle_duration =
- 					results->stutter_cycle_duration[i];
-@@ -3060,78 +3459,98 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 		}
- 	}
- 	results->stutter_burst_time = bw_div(
--		mul(results->total_stutter_cycle_duration,
-+		bw_mul(
-+			results->total_stutter_cycle_duration,
- 			results->total_average_bandwidth),
--		bw_min(
--			(mul(results->dram_bandwidth,
-+		bw_min2(
-+			(bw_mul(
-+				results->dram_bandwidth,
- 				results->dmifdram_access_efficiency)),
--			mul(sclk[sclk_level], vbios->data_return_bus_width)));
--	results->time_in_self_refresh = sub(
--		sub(results->total_stutter_cycle_duration,
-+			bw_mul(
-+				sclk[results->sclk_level],
-+				vbios->data_return_bus_width)));
-+	results->time_in_self_refresh = bw_sub(
-+		bw_sub(
-+			results->total_stutter_cycle_duration,
- 			vbios->stutter_self_refresh_exit_latency),
- 		results->stutter_burst_time);
--	if (mode_data->d1_display_write_back_dwb_enable == true) {
--		results->stutter_efficiency = int_to_fixed(0);
--	} else if (ltn(results->time_in_self_refresh, int_to_fixed(0))) {
--		results->stutter_efficiency = int_to_fixed(0);
-+	if (mode_data->d1_display_write_back_dwb_enable == 1) {
-+		results->stutter_efficiency = bw_int_to_fixed(0);
-+	} else if (bw_ltn(results->time_in_self_refresh, bw_int_to_fixed(0))) {
-+		results->stutter_efficiency = bw_int_to_fixed(0);
- 	} else {
--		results->stutter_efficiency = mul(
--			bw_div(results->time_in_self_refresh,
-+		results->stutter_efficiency = bw_mul(
-+			bw_div(
-+				results->time_in_self_refresh,
- 				results->total_stutter_cycle_duration),
--			int_to_fixed(100));
-+			bw_int_to_fixed(100));
- 	}
--	results->worst_number_of_trips_to_memory = int_to_fixed(1);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*immediate flip time*/
-+	/*if scatter gather is enabled, the immediate flip takes a number of urgent memory trips equivalent to the pte requests in a row divided by the pte request limit.*/
-+	/*otherwise, it may take just one urgenr memory trip*/
-+	results->worst_number_of_trips_to_memory = bw_int_to_fixed(1);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]
--			&& results->scatter_gather_enable_for_pipe[i] == true) {
-+			&& results->scatter_gather_enable_for_pipe[i] == 1) {
- 			results->number_of_trips_to_memory_for_getting_apte_row[i] =
--				bw_ceil(
-+				bw_ceil2(
- 					bw_div(
- 						results->scatter_gather_pte_requests_in_row[i],
- 						results->scatter_gather_pte_request_limit[i]),
--					int_to_fixed(1));
--			if (ltn(results->worst_number_of_trips_to_memory,
-+					bw_int_to_fixed(1));
-+			if (bw_ltn(
-+				results->worst_number_of_trips_to_memory,
- 				results->number_of_trips_to_memory_for_getting_apte_row[i])) {
- 				results->worst_number_of_trips_to_memory =
- 					results->number_of_trips_to_memory_for_getting_apte_row[i];
- 			}
- 		}
- 	}
--	results->immediate_flip_time = mul(
-+	results->immediate_flip_time = bw_mul(
- 		results->worst_number_of_trips_to_memory,
- 		results->total_dmifmc_urgent_latency);
--	results->latency_for_non_dmif_clients = add(
--		results->total_dmifmc_urgent_latency,
--		results->dmif_burst_time[y_clk_level][sclk_level]);
--	if (mode_data->d1_display_write_back_dwb_enable == true) {
--		results->latency_for_non_mcifwr_clients = add(
-+	/*worst latency for other clients*/
-+	/*it is the urgent latency plus the urgent burst time*/
-+	results->latency_for_non_dmif_clients =
-+		bw_add(
-+			results->total_dmifmc_urgent_latency,
-+			results->dmif_burst_time[results->y_clk_level][results->sclk_level]);
-+	if (mode_data->d1_display_write_back_dwb_enable == 1) {
-+		results->latency_for_non_mcifwr_clients = bw_add(
- 			vbios->mcifwrmc_urgent_latency,
- 			dceip->mcifwr_all_surfaces_burst_time);
- 	} else {
--		results->latency_for_non_mcifwr_clients = int_to_fixed(0);
-+		results->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);
- 	}
-+	/*dmif mc urgent latency suppported in high sclk and yclk*/
- 	results->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div(
--		(sub(results->min_read_buffer_size_in_time,
-+		(bw_sub(
-+			results->min_read_buffer_size_in_time,
- 			results->dmif_burst_time[high][high])),
- 		results->total_dmifmc_urgent_trips);
--	results->nbp_state_dram_speed_change_margin = int_to_fixed(9999);
--	for (i = 0; i <= maximum_number_of_surfaces - 1; i += 1) {
-+	/*dram speed/p-state change margin*/
-+	/*in the multi-display case the nb p-state change watermark cannot exceed the average lb size plus the dmif size or the cursor dcp buffer size*/
-+	results->nbp_state_dram_speed_change_margin = bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
- 		if (results->enable[i]) {
- 			results->nbp_state_dram_speed_change_margin =
--				bw_min(
-+				bw_min2(
- 					results->nbp_state_dram_speed_change_margin,
--					sub(
-+					bw_sub(
- 						results->maximum_latency_hiding_with_cursor[i],
- 						results->nbp_state_change_watermark[i]));
- 		}
- 	}
--	for (i = 1; i <= 5; i += 1) {
-+	/*sclk required vs urgent latency*/
-+	for (i = 1; i <= 5; i++) {
- 		results->display_reads_time_for_data_transfer_and_urgent_latency =
--			sub(results->min_read_buffer_size_in_time,
--				mul(results->total_dmifmc_urgent_trips,
--					int_to_fixed(i)));
--		if (pipe_check == def_ok
--			&& (gtn(
-+			bw_sub(
-+				results->min_read_buffer_size_in_time,
-+				bw_mul(
-+					results->total_dmifmc_urgent_trips,
-+					bw_int_to_fixed(i)));
-+		if (pipe_check == bw_def_ok
-+			&& (bw_mtn(
- 				results->display_reads_time_for_data_transfer_and_urgent_latency,
- 				results->dmif_total_page_close_open_time))) {
- 			results->dmif_required_sclk_for_urgent_latency[i] =
-@@ -3142,111 +3561,109 @@ static void calculate_bandwidth(const struct bw_calcs_input_dceip *dceip,
- 					vbios->data_return_bus_width);
- 		} else {
- 			results->dmif_required_sclk_for_urgent_latency[i] =
--				int_to_fixed(0);
-+				bw_int_to_fixed(bw_def_na);
- 		}
- 	}
--
- }
- 
- /*******************************************************************************
-  * Public functions
-  ******************************************************************************/
- 
--void bw_calcs_init(struct bw_calcs_input_dceip *bw_dceip,
--	struct bw_calcs_input_vbios *bw_vbios)
-+void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
-+	struct bw_calcs_vbios *bw_vbios)
- {
--	struct bw_calcs_input_dceip dceip;
--	struct bw_calcs_input_vbios vbios;
-+	struct bw_calcs_dceip dceip = {{ 0 }};
-+	struct bw_calcs_vbios vbios = { 0 };
- 
--	vbios.number_of_dram_channels = int_to_fixed(2);
--	vbios.dram_channel_width_in_bits = int_to_fixed(64);
--	vbios.number_of_dram_banks = int_to_fixed(8);
--	vbios.high_yclk_mhz = int_to_fixed(1600);
--	vbios.low_yclk_mhz = frc_to_fixed(66666, 100);
--	vbios.low_sclk_mhz = int_to_fixed(200);
--	vbios.mid_sclk_mhz = int_to_fixed(300);
--	vbios.high_sclk_mhz = frc_to_fixed(62609, 100);
--	vbios.low_voltage_max_dispclk_mhz = int_to_fixed(352);
--	vbios.mid_voltage_max_dispclk_mhz = int_to_fixed(467);
--	vbios.high_voltage_max_dispclk_mhz = int_to_fixed(643);
--	vbios.data_return_bus_width = int_to_fixed(32);
--	vbios.trc = int_to_fixed(50);
--	vbios.dmifmc_urgent_latency = int_to_fixed(4);
--	vbios.stutter_self_refresh_exit_latency = frc_to_fixed(153, 10);
--	vbios.nbp_state_change_latency = frc_to_fixed(19649, 1000);
--	vbios.mcifwrmc_urgent_latency = int_to_fixed(10);
-+	vbios.number_of_dram_channels = 2;
-+	vbios.dram_channel_width_in_bits = 64;
-+	vbios.number_of_dram_banks = 8;
-+	vbios.high_yclk = bw_int_to_fixed(1600);
-+	vbios.mid_yclk = bw_int_to_fixed(1600);
-+	vbios.low_yclk = bw_frc_to_fixed(66666, 100);
-+	vbios.low_sclk = bw_int_to_fixed(200);
-+	vbios.mid_sclk = bw_int_to_fixed(300);
-+	vbios.high_sclk = bw_frc_to_fixed(62609, 100);
-+	vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
-+	vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
-+	vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
-+	vbios.data_return_bus_width = bw_int_to_fixed(32);
-+	vbios.trc = bw_int_to_fixed(50);
-+	vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-+	vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 10);
-+	vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
-+	vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
- 	vbios.scatter_gather_enable = true;
--	vbios.down_spread_percentage = frc_to_fixed(5, 10);
--	vbios.cursor_width = int_to_fixed(32);
--	vbios.average_compression_rate = int_to_fixed(4);
--	vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel =
--		int_to_fixed(256);
--	vbios.blackout_duration = int_to_fixed(18); /* us */
--	vbios.maximum_blackout_recovery_time = int_to_fixed(20);
--	dceip.dmif_request_buffer_size = int_to_fixed(768);
--	dceip.de_tiling_buffer = int_to_fixed(0);
--	dceip.dcfclk_request_generation = int_to_fixed(0);
--	dceip.lines_interleaved_into_lb = int_to_fixed(2);
--	dceip.chunk_width = int_to_fixed(256);
--	dceip.number_of_graphics_pipes = int_to_fixed(3);
--	dceip.number_of_underlay_pipes = int_to_fixed(1);
-+	vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+	vbios.cursor_width = 32;
-+	vbios.average_compression_rate = 4;
-+	vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
-+	vbios.blackout_duration = bw_int_to_fixed(18); /* us */
-+	vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
-+
-+
-+	dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+	dceip.de_tiling_buffer = bw_int_to_fixed(0);
-+	dceip.dcfclk_request_generation = 0;
-+	dceip.lines_interleaved_into_lb = 2;
-+	dceip.chunk_width = 256;
-+	dceip.number_of_graphics_pipes = 3;
-+	dceip.number_of_underlay_pipes = 1;
- 	dceip.display_write_back_supported = false;
- 	dceip.argb_compression_support = false;
--	dceip.underlay_vscaler_efficiency6_bit_per_component = frc_to_fixed(
-+	dceip.underlay_vscaler_efficiency6_bit_per_component = bw_frc_to_fixed(
- 		35556, 10000);
--	dceip.underlay_vscaler_efficiency8_bit_per_component = frc_to_fixed(
-+	dceip.underlay_vscaler_efficiency8_bit_per_component = bw_frc_to_fixed(
- 		34286, 10000);
--	dceip.underlay_vscaler_efficiency10_bit_per_component = frc_to_fixed(32,
-+	dceip.underlay_vscaler_efficiency10_bit_per_component = bw_frc_to_fixed(32,
- 		10);
--	dceip.underlay_vscaler_efficiency12_bit_per_component = int_to_fixed(3);
--	dceip.graphics_vscaler_efficiency6_bit_per_component = frc_to_fixed(35,
-+	dceip.underlay_vscaler_efficiency12_bit_per_component = bw_int_to_fixed(3);
-+	dceip.graphics_vscaler_efficiency6_bit_per_component = bw_frc_to_fixed(35,
- 		10);
--	dceip.graphics_vscaler_efficiency8_bit_per_component = frc_to_fixed(
-+	dceip.graphics_vscaler_efficiency8_bit_per_component = bw_frc_to_fixed(
- 		34286, 10000);
--	dceip.graphics_vscaler_efficiency10_bit_per_component = frc_to_fixed(32,
-+	dceip.graphics_vscaler_efficiency10_bit_per_component = bw_frc_to_fixed(32,
- 		10);
--	dceip.graphics_vscaler_efficiency12_bit_per_component = int_to_fixed(3);
--	dceip.alpha_vscaler_efficiency = int_to_fixed(3);
--	dceip.max_dmif_buffer_allocated = int_to_fixed(2);
--	dceip.graphics_dmif_size = int_to_fixed(12288);
--	dceip.underlay_luma_dmif_size = int_to_fixed(19456);
--	dceip.underlay_chroma_dmif_size = int_to_fixed(23552);
-+	dceip.graphics_vscaler_efficiency12_bit_per_component = bw_int_to_fixed(3);
-+	dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+	dceip.max_dmif_buffer_allocated = 2;
-+	dceip.graphics_dmif_size = 12288;
-+	dceip.underlay_luma_dmif_size = 19456;
-+	dceip.underlay_chroma_dmif_size = 23552;
- 	dceip.pre_downscaler_enabled = true;
- 	dceip.underlay_downscale_prefetch_enabled = true;
--	dceip.lb_write_pixels_per_dispclk = int_to_fixed(1);
--	dceip.lb_size_per_component444 = int_to_fixed(82176);
-+	dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+	dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
- 	dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
- 	dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
--		int_to_fixed(0);
--	dceip.underlay420_luma_lb_size_per_component = int_to_fixed(82176);
--	dceip.underlay420_chroma_lb_size_per_component = int_to_fixed(164352);
--	dceip.underlay422_lb_size_per_component = int_to_fixed(82176);
--	dceip.cursor_chunk_width = int_to_fixed(64);
--	dceip.cursor_dcp_buffer_lines = int_to_fixed(4);
--	dceip.cursor_memory_interface_buffer_pixels = int_to_fixed(64);
--	dceip.underlay_maximum_width_efficient_for_tiling = int_to_fixed(1920);
--	dceip.underlay_maximum_height_efficient_for_tiling = int_to_fixed(1080);
-+		bw_int_to_fixed(0);
-+	dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(82176);
-+	dceip.underlay420_chroma_lb_size_per_component = bw_int_to_fixed(164352);
-+	dceip.underlay422_lb_size_per_component = bw_int_to_fixed(82176);
-+	dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+	dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+	dceip.cursor_memory_interface_buffer_pixels = bw_int_to_fixed(64);
-+	dceip.underlay_maximum_width_efficient_for_tiling = bw_int_to_fixed(1920);
-+	dceip.underlay_maximum_height_efficient_for_tiling = bw_int_to_fixed(1080);
- 	dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
--		frc_to_fixed(3, 10);
-+		bw_frc_to_fixed(3, 10);
- 	dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
--		int_to_fixed(25);
--	dceip.minimum_outstanding_pte_request_limit = int_to_fixed(2);
-+		bw_int_to_fixed(25);
-+	dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(2);
- 	dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
--		int_to_fixed(128);
-+		bw_int_to_fixed(128);
- 	dceip.limit_excessive_outstanding_dmif_requests = true;
--	dceip.linear_mode_line_request_alternation_slice = int_to_fixed(64);
--	dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
--		int_to_fixed(32);
--	dceip.display_write_back420_luma_mcifwr_buffer_size = int_to_fixed(
--		12288);
--	dceip.display_write_back420_chroma_mcifwr_buffer_size = int_to_fixed(
--		8192);
--	dceip.request_efficiency = frc_to_fixed(8, 10);
--	dceip.dispclk_per_request = int_to_fixed(2);
--	dceip.dispclk_ramping_factor = frc_to_fixed(11, 10);
--	dceip.display_pipe_throughput_factor = frc_to_fixed(105, 100);
--	dceip.scatter_gather_pte_request_rows_in_tiling_mode = int_to_fixed(2);
--	dceip.mcifwr_all_surfaces_burst_time = int_to_fixed(0); /* todo: this is a bug*/
-+	dceip.linear_mode_line_request_alternation_slice = bw_int_to_fixed(64);
-+	dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode = 32;
-+	dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+	dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+	dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+	dceip.dispclk_per_request = bw_int_to_fixed(2);
-+	dceip.dispclk_ramping_factor = bw_frc_to_fixed(11, 10);
-+	dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
-+	dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
- 
- 	*bw_dceip = dceip;
- 	*bw_vbios = vbios;
-@@ -3257,17 +3674,17 @@ void bw_calcs_init(struct bw_calcs_input_dceip *bw_dceip,
-  * maximum voltage (max Performance Level).
-  */
- static bool is_display_configuration_supported(
--	const struct bw_calcs_input_vbios *vbios,
-+	const struct bw_calcs_vbios *vbios,
- 	const struct bw_calcs_output *calcs_output)
- {
- 	uint32_t int_max_clk;
- 
--	int_max_clk = fixed_to_int(vbios->high_voltage_max_dispclk_mhz);
-+	int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk);
- 	int_max_clk *= 1000; /* MHz to kHz */
- 	if (calcs_output->dispclk_khz > int_max_clk)
- 		return false;
- 
--	int_max_clk = fixed_to_int(vbios->high_sclk_mhz);
-+	int_max_clk = bw_fixed_to_int(vbios->high_sclk);
- 	int_max_clk *= 1000; /* MHz to kHz */
- 	if (calcs_output->required_sclk > int_max_clk)
- 		return false;
-@@ -3282,42 +3699,42 @@ static bool is_display_configuration_supported(
-  *	false - Display(s) configuration not supported (not enough bandwidth).
-  */
- 
--bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
--	const struct bw_calcs_input_vbios *vbios,
--	const struct bw_calcs_input_mode_data *mode_data,
-+bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
-+	const struct bw_calcs_vbios *vbios,
-+	const struct bw_calcs_mode_data *mode_data,
- 	struct bw_calcs_output *calcs_output)
- {
--	struct bw_results_internal *bw_results_internal = dc_service_alloc(
--				ctx, sizeof(struct bw_results_internal));
--	struct bw_calcs_input_mode_data_internal *bw_data_internal =
-+	struct bw_calcs_results *bw_results_internal = dc_service_alloc(
-+				ctx, sizeof(struct bw_calcs_results));
-+	struct bw_calcs_mode_data_internal *bw_data_internal =
- 		dc_service_alloc(
--			ctx, sizeof(struct bw_calcs_input_mode_data_internal));
-+			ctx, sizeof(struct bw_calcs_mode_data_internal));
- 	switch (mode_data->number_of_displays) {
- 	case (3):
--		bw_data_internal->d2_htotal = int_to_fixed(
--			mode_data->displays_data[2].h_total);
-+		bw_data_internal->d2_htotal =
-+			mode_data->displays_data[2].h_total;
- 		bw_data_internal->d2_pixel_rate =
- 			mode_data->displays_data[2].pixel_rate;
--		bw_data_internal->d2_graphics_src_width = int_to_fixed(
--			mode_data->displays_data[2].graphics_src_width);
--		bw_data_internal->d2_graphics_src_height = int_to_fixed(
--			mode_data->displays_data[2].graphics_src_height);
-+		bw_data_internal->d2_graphics_src_width =
-+			mode_data->displays_data[2].graphics_src_width;
-+		bw_data_internal->d2_graphics_src_height =
-+			mode_data->displays_data[2].graphics_src_height;
- 		bw_data_internal->d2_graphics_scale_ratio =
- 			mode_data->displays_data[2].graphics_scale_ratio;
- 		bw_data_internal->d2_graphics_stereo_mode =
- 			mode_data->displays_data[2].graphics_stereo_mode;
- 	case (2):
- 		bw_data_internal->d1_display_write_back_dwb_enable = false;
--		bw_data_internal->d1_underlay_mode = ul_none;
--		bw_data_internal->d1_underlay_scale_ratio = int_to_fixed(0);
--		bw_data_internal->d1_htotal = int_to_fixed(
--			mode_data->displays_data[1].h_total);
-+		bw_data_internal->d1_underlay_mode = bw_def_none;
-+		bw_data_internal->d1_underlay_scale_ratio = bw_int_to_fixed(0);
-+		bw_data_internal->d1_htotal =
-+			mode_data->displays_data[1].h_total;
- 		bw_data_internal->d1_pixel_rate =
- 			mode_data->displays_data[1].pixel_rate;
--		bw_data_internal->d1_graphics_src_width = int_to_fixed(
--			mode_data->displays_data[1].graphics_src_width);
--		bw_data_internal->d1_graphics_src_height = int_to_fixed(
--			mode_data->displays_data[1].graphics_src_height);
-+		bw_data_internal->d1_graphics_src_width =
-+			mode_data->displays_data[1].graphics_src_width;
-+		bw_data_internal->d1_graphics_src_height =
-+			mode_data->displays_data[1].graphics_src_height;
- 		bw_data_internal->d1_graphics_scale_ratio =
- 			mode_data->displays_data[1].graphics_scale_ratio;
- 		bw_data_internal->d1_graphics_stereo_mode =
-@@ -3330,15 +3747,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 			mode_data->displays_data[0].lpt_enable;
- 		bw_data_internal->d0_underlay_mode =
- 			mode_data->displays_data[0].underlay_mode;
--		bw_data_internal->d0_underlay_scale_ratio = int_to_fixed(0);
--		bw_data_internal->d0_htotal = int_to_fixed(
--			mode_data->displays_data[0].h_total);
-+		bw_data_internal->d0_underlay_scale_ratio = bw_int_to_fixed(0);
-+		bw_data_internal->d0_htotal =
-+			mode_data->displays_data[0].h_total;
- 		bw_data_internal->d0_pixel_rate =
- 			mode_data->displays_data[0].pixel_rate;
--		bw_data_internal->d0_graphics_src_width = int_to_fixed(
--			mode_data->displays_data[0].graphics_src_width);
--		bw_data_internal->d0_graphics_src_height = int_to_fixed(
--			mode_data->displays_data[0].graphics_src_height);
-+		bw_data_internal->d0_graphics_src_width =
-+			mode_data->displays_data[0].graphics_src_width;
-+		bw_data_internal->d0_graphics_src_height =
-+			mode_data->displays_data[0].graphics_src_height;
- 		bw_data_internal->d0_graphics_scale_ratio =
- 			mode_data->displays_data[0].graphics_scale_ratio;
- 		bw_data_internal->d0_graphics_stereo_mode =
-@@ -3348,10 +3765,10 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 		/* data for all displays */
- 		bw_data_internal->number_of_displays =
- 			mode_data->number_of_displays;
--		bw_data_internal->graphics_rotation_angle = int_to_fixed(
--			mode_data->displays_data[0].graphics_rotation_angle);
--		bw_data_internal->underlay_rotation_angle = int_to_fixed(
--			mode_data->displays_data[0].underlay_rotation_angle);
-+		bw_data_internal->graphics_rotation_angle =
-+			mode_data->displays_data[0].graphics_rotation_angle;
-+		bw_data_internal->underlay_rotation_angle =
-+			mode_data->displays_data[0].underlay_rotation_angle;
- 		bw_data_internal->underlay_surface_type =
- 			mode_data->displays_data[0].underlay_surface_type;
- 		bw_data_internal->panning_and_bezel_adjustment =
-@@ -3360,28 +3777,28 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 			mode_data->displays_data[0].graphics_tiling_mode;
- 		bw_data_internal->graphics_interlace_mode =
- 			mode_data->displays_data[0].graphics_interlace_mode;
--		bw_data_internal->graphics_bytes_per_pixel = int_to_fixed(
--			mode_data->displays_data[0].graphics_bytes_per_pixel);
--		bw_data_internal->graphics_htaps = int_to_fixed(
--			mode_data->displays_data[0].graphics_h_taps);
--		bw_data_internal->graphics_vtaps = int_to_fixed(
--			mode_data->displays_data[0].graphics_v_taps);
--		bw_data_internal->graphics_lb_bpc = int_to_fixed(
--			mode_data->displays_data[0].graphics_lb_bpc);
--		bw_data_internal->underlay_lb_bpc = int_to_fixed(
--			mode_data->displays_data[0].underlay_lb_bpc);
-+		bw_data_internal->graphics_bytes_per_pixel =
-+			mode_data->displays_data[0].graphics_bytes_per_pixel;
-+		bw_data_internal->graphics_htaps =
-+			mode_data->displays_data[0].graphics_h_taps;
-+		bw_data_internal->graphics_vtaps =
-+			mode_data->displays_data[0].graphics_v_taps;
-+		bw_data_internal->graphics_lb_bpc =
-+			mode_data->displays_data[0].graphics_lb_bpc;
-+		bw_data_internal->underlay_lb_bpc =
-+			mode_data->displays_data[0].underlay_lb_bpc;
- 		bw_data_internal->underlay_tiling_mode =
- 			mode_data->displays_data[0].underlay_tiling_mode;
--		bw_data_internal->underlay_htaps = int_to_fixed(
--			mode_data->displays_data[0].underlay_h_taps);
--		bw_data_internal->underlay_vtaps = int_to_fixed(
--			mode_data->displays_data[0].underlay_v_taps);
--		bw_data_internal->underlay_src_width = int_to_fixed(
--			mode_data->displays_data[0].underlay_src_width);
--		bw_data_internal->underlay_src_height = int_to_fixed(
--			mode_data->displays_data[0].underlay_src_height);
--		bw_data_internal->underlay_pitch_in_pixels = int_to_fixed(
--			mode_data->displays_data[0].underlay_pitch_in_pixels);
-+		bw_data_internal->underlay_htaps =
-+			mode_data->displays_data[0].underlay_h_taps;
-+		bw_data_internal->underlay_vtaps =
-+			mode_data->displays_data[0].underlay_v_taps;
-+		bw_data_internal->underlay_src_width =
-+			mode_data->displays_data[0].underlay_src_width;
-+		bw_data_internal->underlay_src_height =
-+			mode_data->displays_data[0].underlay_src_height;
-+		bw_data_internal->underlay_pitch_in_pixels =
-+			mode_data->displays_data[0].underlay_pitch_in_pixels;
- 		bw_data_internal->underlay_stereo_mode =
- 			mode_data->displays_data[0].underlay_stereo_mode;
- 		bw_data_internal->display_synchronization_enabled =
-@@ -3389,111 +3806,126 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_input_dceip *dceip,
- 	}
- 
- 	if (bw_data_internal->number_of_displays != 0) {
--		struct bw_fixed high_sclk = vbios->high_sclk_mhz;
--		struct bw_fixed mid_sclk = vbios->mid_sclk_mhz;
--		struct bw_fixed low_sclk = vbios->low_sclk_mhz;
--		struct bw_fixed high_yclk = vbios->high_yclk_mhz;
--		struct bw_fixed low_yclk = vbios->low_yclk_mhz;
-+		uint8_t yclk_lvl, sclk_lvl;
-+		struct bw_fixed high_sclk = vbios->high_sclk;
-+		struct bw_fixed mid_sclk = vbios->mid_sclk;
-+		struct bw_fixed low_sclk = vbios->low_sclk;
-+		struct bw_fixed high_yclk = vbios->high_yclk;
-+		struct bw_fixed mid_yclk = vbios->mid_yclk;
-+		struct bw_fixed low_yclk = vbios->low_yclk;
- 
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
- 
-+		yclk_lvl = bw_results_internal->y_clk_level;
-+		sclk_lvl = bw_results_internal->sclk_level;
-+
-+		calcs_output->all_displays_in_sync =
-+			mode_data->display_synchronization_enabled;
-+		calcs_output->nbp_state_change_enable =
-+			bw_results_internal->nbp_state_change_enable;
-+		calcs_output->cpuc_state_change_enable =
-+				bw_results_internal->cpuc_state_change_enable;
-+		calcs_output->cpup_state_change_enable =
-+				bw_results_internal->cpup_state_change_enable;
-+		calcs_output->stutter_mode_enable =
-+				bw_results_internal->stutter_mode_enable;
-+		calcs_output->dispclk_khz =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->dispclk,
-+					bw_int_to_fixed(1000)));
-+		calcs_output->required_blackout_duration_us =
-+			bw_fixed_to_int(bw_add(bw_results_internal->
-+				blackout_duration_margin[yclk_lvl][sclk_lvl],
-+				vbios->blackout_duration));
-+		calcs_output->required_sclk =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->required_sclk,
-+					bw_int_to_fixed(1000)));
-+		calcs_output->required_sclk_deep_sleep =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->sclk_deep_sleep,
-+					bw_int_to_fixed(1000)));
-+		if (yclk_lvl == 0)
-+			calcs_output->required_yclk = bw_fixed_to_int(
-+				bw_mul(low_yclk, bw_int_to_fixed(1000)));
-+		else if (yclk_lvl == 1)
-+			calcs_output->required_yclk = bw_fixed_to_int(
-+				bw_mul(mid_yclk, bw_int_to_fixed(1000)));
-+		else
-+			calcs_output->required_yclk = bw_fixed_to_int(
-+				bw_mul(high_yclk, bw_int_to_fixed(1000)));
-+
- 		/* units: nanosecond, 16bit storage. */
- 		calcs_output->nbp_state_change_wm_ns[0].b_mark =
--			mul(bw_results_internal->nbp_state_change_watermark[4],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[4],bw_int_to_fixed(1000)));
- 		calcs_output->nbp_state_change_wm_ns[1].b_mark =
--			mul(bw_results_internal->nbp_state_change_watermark[5],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
- 		calcs_output->nbp_state_change_wm_ns[2].b_mark =
--			mul(bw_results_internal->nbp_state_change_watermark[6],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
- 
- 		calcs_output->stutter_exit_wm_ns[0].b_mark =
--			mul(bw_results_internal->stutter_exit_watermark[4],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
- 		calcs_output->stutter_exit_wm_ns[1].b_mark =
--			mul(bw_results_internal->stutter_exit_watermark[5],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
- 		calcs_output->stutter_exit_wm_ns[2].b_mark =
--			mul(bw_results_internal->stutter_exit_watermark[6],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
- 
- 		calcs_output->urgent_wm_ns[0].b_mark =
--			mul(bw_results_internal->urgent_watermark[4],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[4], bw_int_to_fixed(1000)));
- 		calcs_output->urgent_wm_ns[1].b_mark =
--			mul(bw_results_internal->urgent_watermark[5],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[5], bw_int_to_fixed(1000)));
- 		calcs_output->urgent_wm_ns[2].b_mark =
--			mul(bw_results_internal->urgent_watermark[6],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[6], bw_int_to_fixed(1000)));
- 
--		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = high_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = high_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = high_sclk;
-+		((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
-+		((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
-+		((struct bw_calcs_vbios *)vbios)->low_sclk = high_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid_sclk = high_sclk;
- 
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
- 
- 		calcs_output->nbp_state_change_wm_ns[0].a_mark =
--			mul(bw_results_internal->nbp_state_change_watermark[4],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
- 		calcs_output->nbp_state_change_wm_ns[1].a_mark =
--			mul(bw_results_internal->nbp_state_change_watermark[5],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
- 		calcs_output->nbp_state_change_wm_ns[2].a_mark =
--			mul(bw_results_internal->nbp_state_change_watermark[6],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
- 
- 		calcs_output->stutter_exit_wm_ns[0].a_mark =
--			mul(bw_results_internal->stutter_exit_watermark[4],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
- 		calcs_output->stutter_exit_wm_ns[1].a_mark =
--			mul(bw_results_internal->stutter_exit_watermark[5],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
- 		calcs_output->stutter_exit_wm_ns[2].a_mark =
--			mul(bw_results_internal->stutter_exit_watermark[6],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
- 
- 		calcs_output->urgent_wm_ns[0].a_mark =
--			mul(bw_results_internal->urgent_watermark[4],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[4], bw_int_to_fixed(1000)));
- 		calcs_output->urgent_wm_ns[1].a_mark =
--			mul(bw_results_internal->urgent_watermark[5],
--					int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[5], bw_int_to_fixed(1000)));
- 		calcs_output->urgent_wm_ns[2].a_mark =
--			mul(bw_results_internal->urgent_watermark[6],
--					int_to_fixed(1000)).value >> 24;
--
--		calcs_output->nbp_state_change_enable =
--			bw_results_internal->nbp_state_change_enable;
--		calcs_output->cpuc_state_change_enable =
--				bw_results_internal->cpuc_state_change_enable;
--		calcs_output->cpup_state_change_enable =
--				bw_results_internal->cpup_state_change_enable;
--		calcs_output->stutter_mode_enable =
--				bw_results_internal->stutter_mode_enable;
--		calcs_output->dispclk_khz =
--				mul(bw_results_internal->dispclk,
--					int_to_fixed(1000)).value >> 24;
--		/*TODO:fix formula to unhardcode use levels*/
--		calcs_output->required_blackout_duration_us =
--			add(bw_results_internal->blackout_duration_margin[2][2],
--					vbios->blackout_duration).value >> 24;
--		calcs_output->required_sclk =
--			mul(bw_results_internal->required_sclk,
--					int_to_fixed(1000)).value >> 24;
--		calcs_output->required_sclk_deep_sleep =
--			mul(bw_results_internal->sclk_deep_sleep,
--					int_to_fixed(1000)).value >> 24;
--		/*TODO:fix formula to unhardcode use levels*/
--		calcs_output->required_yclk =
--				mul(high_yclk, int_to_fixed(1000)).value >> 24;
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[6], bw_int_to_fixed(1000)));
- 
--		((struct bw_calcs_input_vbios *)vbios)->low_yclk_mhz = low_yclk;
--		((struct bw_calcs_input_vbios *)vbios)->low_sclk_mhz = low_sclk;
--		((struct bw_calcs_input_vbios *)vbios)->mid_sclk_mhz = mid_sclk;
-+		((struct bw_calcs_vbios *)vbios)->low_yclk = low_yclk;
-+		((struct bw_calcs_vbios *)vbios)->mid_yclk = mid_yclk;
-+		((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid_sclk = mid_sclk;
- 	} else {
- 		calcs_output->nbp_state_change_enable = true;
- 		calcs_output->cpuc_state_change_enable = true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index e1dd610..b076bec 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -60,15 +60,15 @@ static uint64_t abs_i64(int64_t arg)
- 
- struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3)
- {
--	return bw_min(bw_min(v1, v2), v3);
-+	return bw_min2(bw_min2(v1, v2), v3);
- }
- 
- struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3)
- {
--	return bw_max(bw_max(v1, v2), v3);
-+	return bw_max2(bw_max2(v1, v2), v3);
- }
- 
--struct bw_fixed int_to_fixed(int64_t value)
-+struct bw_fixed bw_int_to_fixed(int64_t value)
- {
- 	struct bw_fixed res;
- 	ASSERT(value < MAX_I32 && value > MIN_I32);
-@@ -76,12 +76,12 @@ struct bw_fixed int_to_fixed(int64_t value)
- 	return res;
- }
- 
--uint32_t fixed_to_int(struct bw_fixed value)
-+int32_t bw_fixed_to_int(struct bw_fixed value)
- {
- 	return GET_INTEGER_PART(value.value);
- }
- 
--struct bw_fixed frc_to_fixed(int64_t numerator, int64_t denominator)
-+struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t denominator)
- {
- 	struct bw_fixed res;
- 	bool arg1_negative = numerator < 0;
-@@ -135,17 +135,19 @@ struct bw_fixed frc_to_fixed(int64_t numerator, int64_t denominator)
- 	return res;
- }
- 
--struct bw_fixed bw_min(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+struct bw_fixed bw_min2(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return (arg1.value <= arg2.value) ? arg1 : arg2;
- }
- 
--struct bw_fixed bw_max(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+struct bw_fixed bw_max2(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return (arg2.value <= arg1.value) ? arg1 : arg2;
- }
- 
--struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed significance)
-+struct bw_fixed bw_floor2(
-+	const struct bw_fixed arg,
-+	const struct bw_fixed significance)
- {
- 	struct bw_fixed result;
- 	int64_t multiplicand;
-@@ -155,21 +157,25 @@ struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed signif
- 	return result;
- }
- 
--struct bw_fixed bw_ceil(const struct bw_fixed arg, const struct bw_fixed significance)
-+struct bw_fixed bw_ceil2(
-+	const struct bw_fixed arg,
-+	const struct bw_fixed significance)
- {
- 	struct bw_fixed result;
--	div64_u64_rem(
--			(uint64_t)arg.value,
--			(uint64_t)abs_i64(significance.value),
--			(uint64_t *)&result.value
--	);
--	result.value += arg.value;
--	if (result.value < significance.value)
--		result.value = significance.value;
-+	int64_t multiplicand;
-+
-+	multiplicand = div64_s64(arg.value, abs_i64(significance.value));
-+	result.value = abs_i64(significance.value) * multiplicand;
-+	if (abs_i64(result.value) < abs_i64(arg.value)) {
-+		if (arg.value < 0)
-+			result.value -= abs_i64(significance.value);
-+		else
-+			result.value += abs_i64(significance.value);
-+	}
- 	return result;
- }
- 
--struct bw_fixed add(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+struct bw_fixed bw_add(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	struct bw_fixed res;
- 
-@@ -178,7 +184,7 @@ struct bw_fixed add(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 	return res;
- }
- 
--struct bw_fixed sub(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+struct bw_fixed bw_sub(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	struct bw_fixed res;
- 
-@@ -187,7 +193,7 @@ struct bw_fixed sub(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 	return res;
- }
- 
--struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	struct bw_fixed res;
- 
-@@ -226,7 +232,7 @@ struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 	tmp = arg1_fra * arg2_fra;
- 
- 	tmp = (tmp >> BITS_PER_FRACTIONAL_PART) +
--		(tmp >= (uint64_t)(frc_to_fixed(1, 2).value));
-+		(tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
- 
- 	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
- 
-@@ -239,10 +245,16 @@ struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
- 
- struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
--	struct bw_fixed res = frc_to_fixed(arg1.value, arg2.value);
-+	struct bw_fixed res = bw_frc_to_fixed(arg1.value, arg2.value);
- 	return res;
- }
- 
-+struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+	div64_u64_rem(arg1.value, arg2.value, &res.value);
-+	return res;
-+}
- struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw)
- {
- 	struct bw_fixed result = { 0 };
-@@ -257,32 +269,32 @@ struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw)
- 	return result;
- }
- 
--bool equ(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return arg1.value == arg2.value;
- }
- 
--bool neq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return arg1.value != arg2.value;
- }
- 
--bool leq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return arg1.value <= arg2.value;
- }
- 
--bool geq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return arg1.value >= arg2.value;
- }
- 
--bool ltn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return arg1.value < arg2.value;
- }
- 
--bool gtn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2)
- {
- 	return arg1.value > arg2.value;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 3284fda..1e52e74 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -234,11 +234,11 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			DC_PP_CLOCK_TYPE_ENGINE_CLK,
- 			&clks);
- 	/* convert all the clock fro kHz to fix point mHz */
--	dc->bw_vbios.high_sclk_mhz = frc_to_fixed(
-+	dc->bw_vbios.high_sclk = bw_frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	dc->bw_vbios.mid_sclk_mhz  = frc_to_fixed(
-+	dc->bw_vbios.mid_sclk  = bw_frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels>>1], 1000);
--	dc->bw_vbios.low_sclk_mhz  = frc_to_fixed(
-+	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
- 			clks.clocks_in_khz[0], 1000);
- 
- 	/*do display clock*/
-@@ -247,11 +247,11 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			DC_PP_CLOCK_TYPE_DISPLAY_CLK,
- 			&clks);
- 
--	dc->bw_vbios.high_voltage_max_dispclk_mhz = frc_to_fixed(
-+	dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	dc->bw_vbios.mid_voltage_max_dispclk_mhz  = frc_to_fixed(
-+	dc->bw_vbios.mid_voltage_max_dispclk  = bw_frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels>>1], 1000);
--	dc->bw_vbios.low_voltage_max_dispclk_mhz  = frc_to_fixed(
-+	dc->bw_vbios.low_voltage_max_dispclk  = bw_frc_to_fixed(
- 			clks.clocks_in_khz[0], 1000);
- 
- 	/*do memory clock*/
-@@ -260,9 +260,11 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			DC_PP_CLOCK_TYPE_MEMORY_CLK,
- 			&clks);
- 
--	dc->bw_vbios.low_yclk_mhz = frc_to_fixed(
-+	dc->bw_vbios.low_yclk = bw_frc_to_fixed(
- 			clks.clocks_in_khz[0], 1000);
--	dc->bw_vbios.high_yclk_mhz = frc_to_fixed(
-+	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.high_yclk = bw_frc_to_fixed(
- 			clks.clocks_in_khz[clks.num_levels-1], 1000);
- }
- 
-@@ -562,6 +564,8 @@ static void pplib_apply_display_requirements(
- {
- 	struct dc_pp_display_configuration pp_display_cfg = { 0 };
- 
-+	pp_display_cfg.all_displays_in_sync =
-+		context->bw_results.all_displays_in_sync;
- 	pp_display_cfg.nb_pstate_switch_disable =
- 			context->bw_results.nbp_state_change_enable == false;
- 	pp_display_cfg.cpu_cc6_disable =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index afe54c3..0e38513 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -489,6 +489,8 @@ enum dc_status dce110_validate_bandwidth(
- 	uint8_t i, j;
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	uint8_t number_of_displays = 0;
-+	bool all_displays_in_sync = true;
-+	struct dc_crtc_timing prev_timing;
- 
- 	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
- 
-@@ -501,7 +503,7 @@ enum dc_status dce110_validate_bandwidth(
- 				bw_mode_data.displays_data[number_of_displays];
- 
- 			if (target->status.surface_count == 0) {
--				disp->graphics_scale_ratio = int_to_fixed(1);
-+				disp->graphics_scale_ratio = bw_int_to_fixed(1);
- 				disp->graphics_h_taps = 4;
- 				disp->graphics_v_taps = 4;
- 
-@@ -518,27 +520,39 @@ enum dc_status dce110_validate_bandwidth(
- 			disp->graphics_src_height =
- 					stream->public.timing.v_addressable;
- 			disp->h_total = stream->public.timing.h_total;
--			disp->pixel_rate = frc_to_fixed(
-+			disp->pixel_rate = bw_frc_to_fixed(
- 				stream->public.timing.pix_clk_khz, 1000);
- 
- 			/*TODO: get from surface*/
- 			disp->graphics_bytes_per_pixel = 4;
--			disp->graphics_tiling_mode = tiled;
-+			disp->graphics_tiling_mode = bw_def_tiled;
- 
- 			/* DCE11 defaults*/
- 			disp->graphics_lb_bpc = 10;
- 			disp->graphics_interlace_mode = false;
- 			disp->fbc_enable = false;
- 			disp->lpt_enable = false;
--			disp->graphics_stereo_mode = mono;
--			disp->underlay_mode = ul_none;
-+			disp->graphics_stereo_mode = bw_def_mono;
-+			disp->underlay_mode = bw_def_none;
-+
-+			/*All displays will be synchronized if timings are all
-+			 * the same
-+			 */
-+			if (number_of_displays != 0 && all_displays_in_sync)
-+				if (dal_memcmp(&prev_timing,
-+					&stream->public.timing,
-+					sizeof(struct dc_crtc_timing))!= 0)
-+					all_displays_in_sync = false;
-+			if (number_of_displays == 0)
-+				prev_timing = stream->public.timing;
- 
- 			number_of_displays++;
- 		}
- 	}
- 
- 	context->bw_mode_data.number_of_displays = number_of_displays;
--	context->bw_mode_data.display_synchronization_enabled = false;
-+	context->bw_mode_data.display_synchronization_enabled =
-+							all_displays_in_sync;
- 
- 	dal_logger_write(dc->ctx->logger,
- 		LOG_MAJOR_BWM,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index fb04ce3..0d228ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -37,42 +37,76 @@
-  * 2. board-level values - these are generally coming from VBIOS parser
-  * 3. mode/configuration values - depending Mode, Scaling number of Displays etc.
-  ******************************************************************************/
-+enum bw_defines {
-+	/*Common*/
-+	bw_def_no = 0,
-+	bw_def_none = 0,
-+	bw_def_yes = 1,
-+	bw_def_ok = 1,
-+	bw_def_high = 2,
-+	bw_def_mid = 1,
-+	bw_def_low = 0,
- 
--enum bw_stereo_mode {
--	mono,
--	side_by_side,
--	top_bottom
--};
-+	/*Internal*/
-+	bw_defs_start = 255,
-+	bw_def_underlay422,
-+	bw_def_underlay420_luma,
-+	bw_def_underlay420_chroma,
-+	bw_def_underlay444,
-+	bw_def_graphics,
-+	bw_def_display_write_back420_luma,
-+	bw_def_display_write_back420_chroma,
-+	bw_def_portrait,
-+	bw_def_hsr_mtn_4,
-+	bw_def_hsr_mtn_h_taps,
-+	bw_def_ceiling__h_taps_div_4___meq_hsr,
-+	bw_def_invalid_linear_or_stereo_mode,
-+	bw_def_invalid_rotation_or_bpp_or_stereo,
-+	bw_def_vsr_mtn_v_taps,
-+	bw_def_vsr_mtn_4,
-+	bw_def_auto,
-+	bw_def_manual,
-+	bw_def_exceeded_allowed_maximum_sclk,
-+	bw_def_exceeded_allowed_page_close_open,
-+	bw_def_exceeded_allowed_outstanding_pte_req_queue_size,
-+	bw_def_exceeded_allowed_maximum_bw,
-+	bw_def_high_no_nbp_state_change,
-+	bw_def_landscape,
- 
--enum bw_ul_mode {
--	ul_none,
--	ul_only,
--	ul_blend
--};
-+	/*Panning and bezel*/
-+	bw_def_any_lines,
- 
--enum bw_tiling_mode {
--	linear,
--	tiled
--};
-+	/*Underlay mode*/
-+	bw_def_underlay_only,
-+	bw_def_blended,
-+	bw_def_blend,
- 
--enum bw_panning_and_bezel_adj {
--	none,
--	any_lines
--};
-+	/*Stereo mode*/
-+	bw_def_mono,
-+	bw_def_side_by_side,
-+	bw_def_top_bottom,
- 
--enum bw_underlay_surface_type {
--	yuv_420,
--	yuv_422
-+	/*Underlay surface type*/
-+	bw_def_420,
-+	bw_def_422,
-+	bw_def_444,
-+
-+	/*Tiling mode*/
-+	bw_def_linear,
-+	bw_def_tiled,
-+
-+	bw_def_notok = -1,
-+	bw_def_na = -1
- };
- 
--struct bw_calcs_input_dceip {
-+struct bw_calcs_dceip {
- 	struct bw_fixed dmif_request_buffer_size;
- 	struct bw_fixed de_tiling_buffer;
--	struct bw_fixed dcfclk_request_generation;
--	struct bw_fixed lines_interleaved_into_lb;
--	struct bw_fixed chunk_width;
--	struct bw_fixed number_of_graphics_pipes;
--	struct bw_fixed number_of_underlay_pipes;
-+	bool dcfclk_request_generation;
-+	uint32_t lines_interleaved_into_lb;
-+	uint32_t chunk_width;
-+	uint32_t number_of_graphics_pipes;
-+	uint32_t number_of_underlay_pipes;
- 	bool display_write_back_supported;
- 	bool argb_compression_support;
- 	struct bw_fixed underlay_vscaler_efficiency6_bit_per_component;
-@@ -84,10 +118,10 @@ struct bw_calcs_input_dceip {
- 	struct bw_fixed graphics_vscaler_efficiency10_bit_per_component;
- 	struct bw_fixed graphics_vscaler_efficiency12_bit_per_component;
- 	struct bw_fixed alpha_vscaler_efficiency;
--	struct bw_fixed max_dmif_buffer_allocated;
--	struct bw_fixed graphics_dmif_size;
--	struct bw_fixed underlay_luma_dmif_size;
--	struct bw_fixed underlay_chroma_dmif_size;
-+	uint32_t max_dmif_buffer_allocated;
-+	uint32_t graphics_dmif_size;
-+	uint32_t underlay_luma_dmif_size;
-+	uint32_t underlay_chroma_dmif_size;
- 	bool pre_downscaler_enabled;
- 	bool underlay_downscale_prefetch_enabled;
- 	struct bw_fixed lb_write_pixels_per_dispclk;
-@@ -108,31 +142,30 @@ struct bw_calcs_input_dceip {
- 	struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw;
- 	bool limit_excessive_outstanding_dmif_requests;
- 	struct bw_fixed linear_mode_line_request_alternation_slice;
--	struct bw_fixed scatter_gather_lines_of_pte_prefetching_in_linear_mode;
--	struct bw_fixed display_write_back420_luma_mcifwr_buffer_size;
--	struct bw_fixed display_write_back420_chroma_mcifwr_buffer_size;
-+	uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode;
-+	uint32_t display_write_back420_luma_mcifwr_buffer_size;
-+	uint32_t display_write_back420_chroma_mcifwr_buffer_size;
- 	struct bw_fixed request_efficiency;
- 	struct bw_fixed dispclk_per_request;
- 	struct bw_fixed dispclk_ramping_factor;
- 	struct bw_fixed display_pipe_throughput_factor;
--	struct bw_fixed scatter_gather_pte_request_rows_in_tiling_mode;
-+	uint32_t scatter_gather_pte_request_rows_in_tiling_mode;
- 	struct bw_fixed mcifwr_all_surfaces_burst_time; /* 0 todo: this is a bug*/
- };
- 
--struct bw_calcs_input_vbios {
--	struct bw_fixed dram_channel_width_in_bits;
--	struct bw_fixed number_of_dram_channels;
--	struct bw_fixed number_of_dram_banks;
--	struct bw_fixed high_yclk_mhz;
--	struct bw_fixed high_dram_bandwidth_per_channel;
--	struct bw_fixed low_yclk_mhz;
--	struct bw_fixed low_dram_bandwidth_per_channel;
--	struct bw_fixed low_sclk_mhz;
--	struct bw_fixed mid_sclk_mhz;
--	struct bw_fixed high_sclk_mhz;
--	struct bw_fixed low_voltage_max_dispclk_mhz;
--	struct bw_fixed mid_voltage_max_dispclk_mhz;
--	struct bw_fixed high_voltage_max_dispclk_mhz;
-+struct bw_calcs_vbios {
-+	uint32_t dram_channel_width_in_bits;
-+	uint32_t number_of_dram_channels;
-+	uint32_t number_of_dram_banks;
-+	struct bw_fixed high_yclk; /*MHz*/
-+	struct bw_fixed mid_yclk; /*MHz*/
-+	struct bw_fixed low_yclk; /*MHz*/
-+	struct bw_fixed low_sclk; /*MHz*/
-+	struct bw_fixed mid_sclk; /*MHz*/
-+	struct bw_fixed high_sclk; /*MHz*/
-+	struct bw_fixed low_voltage_max_dispclk; /*MHz*/
-+	struct bw_fixed mid_voltage_max_dispclk; /*MHz*/
-+	struct bw_fixed high_voltage_max_dispclk; /*MHz*/
- 	struct bw_fixed data_return_bus_width;
- 	struct bw_fixed trc;
- 	struct bw_fixed dmifmc_urgent_latency;
-@@ -141,81 +174,82 @@ struct bw_calcs_input_vbios {
- 	struct bw_fixed mcifwrmc_urgent_latency;
- 	bool scatter_gather_enable;
- 	struct bw_fixed down_spread_percentage;
--	struct bw_fixed cursor_width;
--	struct bw_fixed average_compression_rate;
--	struct bw_fixed number_of_request_slots_gmc_reserves_for_dmif_per_channel;
-+	uint32_t cursor_width;
-+	uint32_t average_compression_rate;
-+	uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel;
- 	struct bw_fixed blackout_duration;
- 	struct bw_fixed maximum_blackout_recovery_time;
- };
- 
--struct bw_calcs_input_mode_data_internal {
-+struct bw_calcs_mode_data_internal {
- 	/* data for all displays */
- 	uint32_t number_of_displays;
--	struct bw_fixed graphics_rotation_angle;
--	struct bw_fixed underlay_rotation_angle;
--	bool display_synchronization_enabled;
--	enum bw_underlay_surface_type underlay_surface_type;
--	enum bw_panning_and_bezel_adj panning_and_bezel_adjustment;
--	enum bw_tiling_mode graphics_tiling_mode;
-+	uint32_t graphics_rotation_angle;
-+	uint32_t underlay_rotation_angle;
-+	enum bw_defines display_synchronization_enabled;
-+	enum bw_defines underlay_surface_type;
-+	enum bw_defines panning_and_bezel_adjustment;
-+	enum bw_defines graphics_tiling_mode;
- 	bool graphics_interlace_mode;
--	struct bw_fixed graphics_bytes_per_pixel;
--	struct bw_fixed graphics_htaps;
--	struct bw_fixed graphics_vtaps;
--	struct bw_fixed graphics_lb_bpc;
--	struct bw_fixed underlay_lb_bpc;
--	enum bw_tiling_mode underlay_tiling_mode;
--	struct bw_fixed underlay_htaps;
--	struct bw_fixed underlay_vtaps;
--	struct bw_fixed underlay_src_width;
--	struct bw_fixed underlay_src_height;
--	struct bw_fixed underlay_pitch_in_pixels;
--	enum bw_stereo_mode underlay_stereo_mode;
-+	uint32_t graphics_bytes_per_pixel;
-+	uint32_t graphics_htaps;
-+	uint32_t graphics_vtaps;
-+	uint32_t graphics_lb_bpc;
-+	uint32_t underlay_lb_bpc;
-+	enum bw_defines underlay_tiling_mode;
-+	uint32_t underlay_htaps;
-+	uint32_t underlay_vtaps;
-+	uint32_t underlay_src_width;
-+	uint32_t underlay_src_height;
-+	uint32_t underlay_pitch_in_pixels;
-+	enum bw_defines underlay_stereo_mode;
- 	bool d0_fbc_enable;
- 	bool d0_lpt_enable;
--	struct bw_fixed d0_htotal;
-+	uint32_t d0_htotal;
- 	struct bw_fixed d0_pixel_rate;
--	struct bw_fixed d0_graphics_src_width;
--	struct bw_fixed d0_graphics_src_height;
-+	uint32_t d0_graphics_src_width;
-+	uint32_t d0_graphics_src_height;
- 	struct bw_fixed d0_graphics_scale_ratio;
--	enum bw_stereo_mode d0_graphics_stereo_mode;
--	enum bw_ul_mode d0_underlay_mode;
-+	enum bw_defines d0_graphics_stereo_mode;
-+	enum bw_defines d0_underlay_mode;
- 	struct bw_fixed d0_underlay_scale_ratio;
--	struct bw_fixed d1_htotal;
-+	uint32_t d1_htotal;
- 	struct bw_fixed d1_pixel_rate;
--	struct bw_fixed d1_graphics_src_width;
--	struct bw_fixed d1_graphics_src_height;
-+	uint32_t d1_graphics_src_width;
-+	uint32_t d1_graphics_src_height;
- 	struct bw_fixed d1_graphics_scale_ratio;
--	enum bw_stereo_mode d1_graphics_stereo_mode;
-+	enum bw_defines d1_graphics_stereo_mode;
- 	bool d1_display_write_back_dwb_enable;
--	enum bw_ul_mode d1_underlay_mode;
-+	enum bw_defines d1_underlay_mode;
- 	struct bw_fixed d1_underlay_scale_ratio;
--	struct bw_fixed d2_htotal;
-+	uint32_t d2_htotal;
- 	struct bw_fixed d2_pixel_rate;
--	struct bw_fixed d2_graphics_src_width;
--	struct bw_fixed d2_graphics_src_height;
-+	uint32_t d2_graphics_src_width;
-+	uint32_t d2_graphics_src_height;
- 	struct bw_fixed d2_graphics_scale_ratio;
--	enum bw_stereo_mode d2_graphics_stereo_mode;
-+	enum bw_defines d2_graphics_stereo_mode;
- };
- 
-+
- struct bw_calcs_input_single_display {
- 	uint32_t graphics_rotation_angle;
- 	uint32_t underlay_rotation_angle;
--	enum bw_underlay_surface_type underlay_surface_type;
--	enum bw_panning_and_bezel_adj panning_and_bezel_adjustment;
-+	enum bw_defines underlay_surface_type;
-+	enum bw_defines panning_and_bezel_adjustment;
- 	uint32_t graphics_bytes_per_pixel;
- 	bool graphics_interlace_mode;
--	enum bw_tiling_mode graphics_tiling_mode;
-+	enum bw_defines graphics_tiling_mode;
- 	uint32_t graphics_h_taps;
- 	uint32_t graphics_v_taps;
- 	uint32_t graphics_lb_bpc;
- 	uint32_t underlay_lb_bpc;
--	enum bw_tiling_mode underlay_tiling_mode;
-+	enum bw_defines underlay_tiling_mode;
- 	uint32_t underlay_h_taps;
- 	uint32_t underlay_v_taps;
- 	uint32_t underlay_src_width;
- 	uint32_t underlay_src_height;
- 	uint32_t underlay_pitch_in_pixels;
--	enum bw_stereo_mode underlay_stereo_mode;
-+	enum bw_defines underlay_stereo_mode;
- 	bool fbc_enable;
- 	bool lpt_enable;
- 	uint32_t h_total;
-@@ -223,13 +257,13 @@ struct bw_calcs_input_single_display {
- 	uint32_t graphics_src_width;
- 	uint32_t graphics_src_height;
- 	struct bw_fixed graphics_scale_ratio;
--	enum bw_stereo_mode graphics_stereo_mode;
--	enum bw_ul_mode underlay_mode;
-+	enum bw_defines graphics_stereo_mode;
-+	enum bw_defines underlay_mode;
- };
- 
- #define BW_CALCS_MAX_NUM_DISPLAYS 3
- 
--struct bw_calcs_input_mode_data {
-+struct bw_calcs_mode_data {
- 	/* data for all displays */
- 	uint8_t number_of_displays;
- 	bool display_synchronization_enabled;
-@@ -243,12 +277,14 @@ struct bw_calcs_input_mode_data {
-  ******************************************************************************/
- #define maximum_number_of_surfaces 12
- /*Units : MHz, us */
--struct bw_results_internal {
-+struct bw_calcs_results {
- 	bool cpup_state_change_enable;
- 	bool cpuc_state_change_enable;
- 	bool nbp_state_change_enable;
- 	bool stutter_mode_enable;
--	struct bw_fixed number_of_underlay_surfaces;
-+	uint32_t y_clk_level;
-+	uint32_t sclk_level;
-+	uint32_t number_of_underlay_surfaces;
- 	struct bw_fixed src_width_after_surface_type;
- 	struct bw_fixed src_height_after_surface_type;
- 	struct bw_fixed hsr_after_surface_type;
-@@ -340,13 +376,17 @@ struct bw_results_internal {
- 	struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk;
- 	struct bw_fixed nbp_state_dram_speed_change_margin;
- 	struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency;
-+	bool displays_match_flag[maximum_number_of_surfaces];
- 	bool use_alpha[maximum_number_of_surfaces];
- 	bool orthogonal_rotation[maximum_number_of_surfaces];
- 	bool enable[maximum_number_of_surfaces];
- 	bool access_one_channel_only[maximum_number_of_surfaces];
- 	bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];
- 	bool interlace_mode[maximum_number_of_surfaces];
--	struct bw_fixed bytes_per_pixel[maximum_number_of_surfaces];
-+	bool display_pstate_change_enable[maximum_number_of_surfaces];
-+	struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces];
-+	struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces];
-+	uint32_t bytes_per_pixel[maximum_number_of_surfaces];
- 	struct bw_fixed h_total[maximum_number_of_surfaces];
- 	struct bw_fixed pixel_rate[maximum_number_of_surfaces];
- 	struct bw_fixed src_width[maximum_number_of_surfaces];
-@@ -357,7 +397,7 @@ struct bw_results_internal {
- 	struct bw_fixed h_taps[maximum_number_of_surfaces];
- 	struct bw_fixed v_taps[maximum_number_of_surfaces];
- 	struct bw_fixed rotation_angle[maximum_number_of_surfaces];
--	struct bw_fixed lb_bpc[maximum_number_of_surfaces];
-+	uint32_t lb_bpc[maximum_number_of_surfaces];
- 	struct bw_fixed compression_rate[maximum_number_of_surfaces];
- 	struct bw_fixed hsr[maximum_number_of_surfaces];
- 	struct bw_fixed vsr[maximum_number_of_surfaces];
-@@ -398,7 +438,7 @@ struct bw_results_internal {
- 	struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces];
- 	struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces];
- 	struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces];
--	struct bw_fixed line_buffer_prefetch[maximum_number_of_surfaces];
-+	bool line_buffer_prefetch[maximum_number_of_surfaces];
- 	struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces];
- 	struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces];
- 	struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces];
-@@ -413,6 +453,8 @@ struct bw_results_internal {
- 	struct bw_fixed dmif_burst_time[3][3];
- 	struct bw_fixed mcifwr_burst_time[3][3];
- 	struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][3];
-+	struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][3];
-+	struct bw_fixed min_dram_speed_change_margin[3][3];
- 	struct bw_fixed dram_speed_change_margin[3][3];
- 	struct bw_fixed dispclk_required_for_dram_speed_change[3][3];
- 	struct bw_fixed blackout_duration_margin[3][3];
-@@ -431,6 +473,7 @@ struct bw_calcs_output {
- 	bool cpup_state_change_enable;
- 	bool stutter_mode_enable;
- 	bool nbp_state_change_enable;
-+	bool all_displays_in_sync;
- 	struct bw_watermarks urgent_wm_ns[4];
- 	struct bw_watermarks stutter_exit_wm_ns[4];
- 	struct bw_watermarks nbp_state_change_wm_ns[4];
-@@ -438,7 +481,7 @@ struct bw_calcs_output {
- 	uint32_t required_sclk_deep_sleep;
- 	uint32_t required_yclk;
- 	uint32_t dispclk_khz;
--	uint32_t required_blackout_duration_us;
-+	int32_t required_blackout_duration_us;
- };
- 
- 
-@@ -446,8 +489,8 @@ struct bw_calcs_output {
-  * Initialize structures with data which will NOT change at runtime.
-  */
- void bw_calcs_init(
--	struct bw_calcs_input_dceip *bw_dceip,
--	struct bw_calcs_input_vbios *bw_vbios);
-+	struct bw_calcs_dceip *bw_dceip,
-+	struct bw_calcs_vbios *bw_vbios);
- 
- /**
-  * Return:
-@@ -457,9 +500,9 @@ void bw_calcs_init(
-  */
- bool bw_calcs(
- 	struct dc_context *ctx,
--	const struct bw_calcs_input_dceip *dceip,
--	const struct bw_calcs_input_vbios *vbios,
--	const struct bw_calcs_input_mode_data *mode_data,
-+	const struct bw_calcs_dceip *dceip,
-+	const struct bw_calcs_vbios *vbios,
-+	const struct bw_calcs_mode_data *mode_data,
- 	struct bw_calcs_output *calcs_output);
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-index cd0c889..ff271cc 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-@@ -34,29 +34,31 @@ struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed
- 
- struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3);
- 
--struct bw_fixed int_to_fixed(int64_t value);
-+struct bw_fixed bw_int_to_fixed(int64_t value);
- 
--uint32_t fixed_to_int(struct bw_fixed value);
-+int32_t bw_fixed_to_int(struct bw_fixed value);
- 
--struct bw_fixed frc_to_fixed(int64_t num, int64_t denum);
-+struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum);
- 
- struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw);
- 
--struct bw_fixed add(const struct bw_fixed arg1, const struct bw_fixed arg2);
--struct bw_fixed sub(const struct bw_fixed arg1, const struct bw_fixed arg2);
--struct bw_fixed mul(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_add(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_sub(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2);
- struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+
-+struct bw_fixed bw_min2(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_max2(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+struct bw_fixed bw_floor2(const struct bw_fixed arg, const struct bw_fixed significance);
-+struct bw_fixed bw_ceil2(const struct bw_fixed arg, const struct bw_fixed significance);
-+
-+bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2);
- 
--struct bw_fixed bw_min(const struct bw_fixed arg1, const struct bw_fixed arg2);
--struct bw_fixed bw_max(const struct bw_fixed arg1, const struct bw_fixed arg2);
--struct bw_fixed bw_floor(const struct bw_fixed arg, const struct bw_fixed significance);
--struct bw_fixed bw_ceil(const struct bw_fixed arg, const struct bw_fixed significance);
--
--bool equ(const struct bw_fixed arg1, const struct bw_fixed arg2);
--bool neq(const struct bw_fixed arg1, const struct bw_fixed arg2);
--bool leq(const struct bw_fixed arg1, const struct bw_fixed arg2);
--bool geq(const struct bw_fixed arg1, const struct bw_fixed arg2);
--bool ltn(const struct bw_fixed arg1, const struct bw_fixed arg2);
--bool gtn(const struct bw_fixed arg1, const struct bw_fixed arg2);
- 
- #endif //BW_FIXED_H_
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index dc246e8..66f7544 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -29,8 +29,8 @@ struct dc {
- 	enum dc_video_power_state current_power_state;
- 
- 	/* Inputs into BW and WM calculations. */
--	struct bw_calcs_input_dceip bw_dceip;
--	struct bw_calcs_input_vbios bw_vbios;
-+	struct bw_calcs_dceip bw_dceip;
-+	struct bw_calcs_vbios bw_vbios;
- 
- 	/* HW functions */
- 	struct hw_sequencer_funcs hwss;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 6ef41b1..b35ec1a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -308,7 +308,7 @@ struct validate_context {
- 
- 	struct resource_context res_ctx;
- 
--	struct bw_calcs_input_mode_data bw_mode_data;
-+	struct bw_calcs_mode_data bw_mode_data;
- 	/* The output from BW and WM calculations. */
- 	struct bw_calcs_output bw_results;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0622-drm-amd-dal-Fix-IRQ-sources-for-HPD-control-config.patch b/common/recipes-kernel/linux/files/0622-drm-amd-dal-Fix-IRQ-sources-for-HPD-control-config.patch
deleted file mode 100644
index a5a1a86a..00000000
--- a/common/recipes-kernel/linux/files/0622-drm-amd-dal-Fix-IRQ-sources-for-HPD-control-config.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From d424d082f83547cd54d00be2d29b965143ac90d4 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Mon, 14 Dec 2015 17:10:45 -0500
-Subject: [PATCH 0622/1110] drm/amd/dal: Fix IRQ sources for HPD
- control/config.
-
-This resolves the "headless boot/hpd" issue by removing the
-use of "amdgpu_connector->hpd.hpd" (which was not properly
-initialized).
-Instead, only "dc_link->irq_source_hpd" will be used
-for HPD irq control/config.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c   | 20 ++++++++++----------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c |  4 +---
- 2 files changed, 11 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index 05a0053..ab6df66 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -761,9 +761,7 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
- 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- 		struct amdgpu_connector *amdgpu_connector =
- 				to_amdgpu_connector(connector);
--		enum dc_irq_source src =
--			amdgpu_dm_hpd_to_dal_irq_source(
--				amdgpu_connector->hpd.hpd);
-+
- 		const struct dc_link *dc_link = amdgpu_connector->dc_link;
- 
- 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
-@@ -777,8 +775,7 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
- 			continue;
- 		}
- 
--		dc_interrupt_set(adev->dm.dc, src, true);
--		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
-+		dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, true);
- 
- 		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
- 			dc_interrupt_set(adev->dm.dc,
-@@ -804,11 +801,14 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
- 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- 		struct amdgpu_connector *amdgpu_connector =
- 				to_amdgpu_connector(connector);
--		enum dc_irq_source src =
--			amdgpu_dm_hpd_to_dal_irq_source(
--				amdgpu_connector->hpd.hpd);
-+		const struct dc_link *dc_link = amdgpu_connector->dc_link;
- 
--		dc_interrupt_set(adev->dm.dc, src, false);
--		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
-+		dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
-+			dc_interrupt_set(adev->dm.dc,
-+					dc_link->irq_source_hpd_rx,
-+					false);
-+		}
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 326242f..465d9bf 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1768,9 +1768,7 @@ void amdgpu_dm_connector_init_helper(
- 	aconnector->base.interlace_allowed = true;
- 	aconnector->base.doublescan_allowed = true;
- 	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
--	aconnector->hpd.hpd = link_index; /* maps to 'enum amdgpu_hpd_id' */
--
--
-+	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
- 
- 	/*configure suport HPD hot plug connector_>polled default value is 0
- 	 * which means HPD hot plug not supported*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0623-drm-amd-dal-Unblanking-logic-change-in-DM-DC.patch b/common/recipes-kernel/linux/files/0623-drm-amd-dal-Unblanking-logic-change-in-DM-DC.patch
deleted file mode 100644
index d05c9d44..00000000
--- a/common/recipes-kernel/linux/files/0623-drm-amd-dal-Unblanking-logic-change-in-DM-DC.patch
+++ /dev/null
@@ -1,135 +0,0 @@
-From 56f1ac8be4cdb4f124348e34d9838fc3df9b5ccf Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Tue, 15 Dec 2015 18:08:17 -0500
-Subject: [PATCH 0623/1110] drm/amd/dal: Unblanking logic change in DM/DC
-
-DC should unblank and blank displays in commit_surfaces based on *enabled*
-surfaces rather than just surface count.
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 36 ++++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  2 +-
- 3 files changed, 25 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 465d9bf..516d321 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -492,7 +492,7 @@ static void fill_plane_attributes_from_fb(
- 	surface->plane_size.grph.surface_pitch =
- 		fb->pitches[0] / (fb->bits_per_pixel / 8);
- 
--	surface->enabled = true;
-+	surface->visible = true;
- 	surface->scaling_quality.h_taps_c = 2;
- 	surface->scaling_quality.v_taps_c = 2;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 9ae98c5..82cdae1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -194,36 +194,46 @@ gamma_param_fail:
- 
- bool dc_commit_surfaces_to_target(
- 		struct dc *dc,
--		struct dc_surface *surfaces[],
--		uint8_t surface_count,
-+		struct dc_surface *new_surfaces[],
-+		uint8_t new_surface_count,
- 		struct dc_target *dc_target)
- 
- {
- 	uint8_t i, j;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	bool need_blanking = (target->status.surface_count == 0);
-+
-+	bool current_enabled_surface_count = 0;
-+	bool new_enabled_surface_count = 0;
-+
-+	for (i = 0; i < target->status.surface_count; i++)
-+		if (target->status.surfaces[i]->visible)
-+			current_enabled_surface_count++;
-+
-+	for (i = 0; i < new_surface_count; i++)
-+		if (new_surfaces[i]->visible)
-+			new_enabled_surface_count++;
- 
- 	dal_logger_write(dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC,
- 				"%s: commit %d surfaces to target 0x%x",
- 				__func__,
--				surface_count,
-+				new_surface_count,
- 				dc_target);
- 
- 
- 	if (!logical_attach_surfaces_to_target(
--						surfaces,
--						surface_count,
-+						new_surfaces,
-+						new_surface_count,
- 						dc_target)) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
- 	}
- 
--	for (i = 0; i < surface_count; i++)
-+	for (i = 0; i < new_surface_count; i++)
- 		for (j = 0; j < target->public.stream_count; j++)
- 			build_scaling_params(
--				surfaces[i],
-+				new_surfaces[i],
- 				DC_STREAM_TO_CORE(target->public.streams[j]));
- 
- 	if (dc->hwss.validate_bandwidth(dc, &dc->current_context) != DC_OK) {
-@@ -233,11 +243,11 @@ bool dc_commit_surfaces_to_target(
- 
- 	dc->hwss.program_bw(dc, &dc->current_context);
- 
--	if (need_blanking)
-+	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
- 		dc_target_disable_memory_requests(dc_target);
- 
--	for (i = 0; i < surface_count; i++) {
--		struct dc_surface *surface = surfaces[i];
-+	for (i = 0; i < new_surface_count; i++) {
-+		struct dc_surface *surface = new_surfaces[i];
- 		struct core_surface *core_surface = DC_SURFACE_TO_CORE(surface);
- 
- 		dal_logger_write(dc->ctx->logger,
-@@ -258,13 +268,13 @@ bool dc_commit_surfaces_to_target(
- 		dc->hwss.update_plane_address(core_surface, target);
- 	}
- 
--	if (surface_count > 0 && need_blanking)
-+	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
- 		dc_target_enable_memory_requests(dc_target);
- 
- 	return true;
- 
- unexpected_fail:
--	for (i = 0; i < surface_count; i++) {
-+	for (i = 0; i < new_surface_count; i++) {
- 		target->status.surfaces[i] = NULL;
- 	}
- 	target->status.surface_count = 0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index bbeaf23..264b428 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -58,7 +58,7 @@ void dc_destroy(struct dc **dc);
-  ******************************************************************************/
- 
- struct dc_surface {
--	bool enabled;
-+	bool visible;
- 	bool flip_immediate;
- 	struct dc_plane_address address;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0624-drm-amd-dal-Add-new-gamma-ramp-interface-to-dc.patch b/common/recipes-kernel/linux/files/0624-drm-amd-dal-Add-new-gamma-ramp-interface-to-dc.patch
deleted file mode 100644
index 902e118d..00000000
--- a/common/recipes-kernel/linux/files/0624-drm-amd-dal-Add-new-gamma-ramp-interface-to-dc.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From b32b1a0948a3ee9817e9b3ea421ffe74f09a4103 Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Wed, 16 Dec 2015 14:41:31 -0500
-Subject: [PATCH 0624/1110] drm/amd/dal: Add new gamma ramp interface to dc
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc.h       |  3 ++-
- drivers/gpu/drm/amd/dal/dc/dc_types.h | 32 ++++++++++++++++++++++++++++++++
- 2 files changed, 34 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 264b428..c9cdd9c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -75,7 +75,8 @@ struct dc_surface {
- 	enum dc_rotation_angle rotation;
- 	enum plane_stereo_format stereo_format;
- 
--	struct gamma_ramp gamma_correction;
-+	struct gamma_ramp gamma_correction; /* deprecated */
-+	struct dc_gamma_ramp gamma;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index b6526e9..1834fe0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -665,6 +665,38 @@ enum dc_connection_type {
- 	dc_connection_active_dongle
- };
- 
-+/*
-+ * Gamma ramp representation in DC
-+ *
-+ * A gamma ramp is just a curve defined within the range of [min, max] with
-+ * arbitrary precision.
-+ *
-+ * DM is responsible for providing DC with an interface to obtain any y value
-+ * within that range with a selected precision.
-+ *
-+ * bit32 ------------------------------------------------- bit 0
-+ *       [  padding  ][ exponent bits ][  fraction bits  ]
-+ *
-+ * DC specifies the input x value and precision to the callback function
-+ * get_gamma_value as well as providing the context and DM returns the y
-+ * value.
-+ *
-+ * If fraction_bits + exponent_bits exceed width of 32 bits, get_gamma_value
-+ * returns 0.  If x is outside the bounds of [min, max], get_gamma_value
-+ * returns 0.
-+ *
-+ */
-+struct dc_gamma_ramp {
-+	uint32_t (*get_gamma_value) (
-+			void *context,
-+			uint8_t exponent_bits,
-+			uint8_t fraction_bits,
-+			uint32_t x);
-+	void *context;
-+	uint32_t min;
-+	uint32_t max;
-+};
-+
- struct dc_csc_adjustments {
- 	struct fixed31_32 contrast;
- 	struct fixed31_32 saturation;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0625-drm-amd-dal-fix-edp-detection-segfault.patch b/common/recipes-kernel/linux/files/0625-drm-amd-dal-fix-edp-detection-segfault.patch
deleted file mode 100644
index 18330e90..00000000
--- a/common/recipes-kernel/linux/files/0625-drm-amd-dal-fix-edp-detection-segfault.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 96e2d129b65ddabca68cb65a78dc2729d8ad0ea6 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 16 Dec 2015 15:42:34 -0500
-Subject: [PATCH 0625/1110] drm/amd/dal: fix edp detection segfault
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 516d321..c98fdbf 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1847,7 +1847,8 @@ int amdgpu_dm_connector_init(
- 
- 	drm_connector_register(&aconnector->base);
- 
--	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort)
-+	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
-+		|| connector_type == DRM_MODE_CONNECTOR_eDP)
- 		amdgpu_dm_initialize_mst_connector(dm, aconnector);
- 
- #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0626-drm-amd-dal-fix-yclk-value.patch b/common/recipes-kernel/linux/files/0626-drm-amd-dal-fix-yclk-value.patch
deleted file mode 100644
index c264cf3d..00000000
--- a/common/recipes-kernel/linux/files/0626-drm-amd-dal-fix-yclk-value.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 59283ade1a230d72f31e79b5cdecd65ad3f222c4 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 16 Dec 2015 11:48:58 -0500
-Subject: [PATCH 0626/1110] drm/amd/dal: fix yclk value
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c                        | 13 +++++++++----
- .../gpu/drm/amd/dal/utils/bw_calc_test_harness/.gitignore   |  4 ++++
- drivers/gpu/drm/amd/dal/utils/vba_to_c_converter/.gitignore |  4 ++++
- 3 files changed, 17 insertions(+), 4 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/utils/bw_calc_test_harness/.gitignore
- create mode 100644 drivers/gpu/drm/amd/dal/utils/vba_to_c_converter/.gitignore
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 1e52e74..a37cd87 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -224,6 +224,8 @@ static struct adapter_service *create_as(
- 	return as;
- }
- 
-+/* TODO unhardcode, 4 for CZ*/
-+#define MEMORY_TYPE_MULTIPLIER 4
- static void bw_calcs_data_update_from_pplib(struct dc *dc)
- {
- 	struct dc_pp_clock_levels clks = {0};
-@@ -261,11 +263,13 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			&clks);
- 
- 	dc->bw_vbios.low_yclk = bw_frc_to_fixed(
--			clks.clocks_in_khz[0], 1000);
-+		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
- 	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
--			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
- 	dc->bw_vbios.high_yclk = bw_frc_to_fixed(
--			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
- }
- 
- static bool construct(struct dc *dc, const struct dal_init_data *init_params)
-@@ -575,7 +579,8 @@ static void pplib_apply_display_requirements(
- 	pp_display_cfg.cpu_pstate_separation_time =
- 			context->bw_results.required_blackout_duration_us;
- 
--	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk;
-+	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk
-+		/ MEMORY_TYPE_MULTIPLIER;
- 	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
- 	pp_display_cfg.min_engine_clock_deep_sleep_khz
- 			= context->bw_results.required_sclk_deep_sleep;
-diff --git a/drivers/gpu/drm/amd/dal/utils/bw_calc_test_harness/.gitignore b/drivers/gpu/drm/amd/dal/utils/bw_calc_test_harness/.gitignore
-new file mode 100644
-index 0000000..4d12de1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/utils/bw_calc_test_harness/.gitignore
-@@ -0,0 +1,4 @@
-+x64
-+Debug
-+*.user
-+*.sdf
-\ No newline at end of file
-diff --git a/drivers/gpu/drm/amd/dal/utils/vba_to_c_converter/.gitignore b/drivers/gpu/drm/amd/dal/utils/vba_to_c_converter/.gitignore
-new file mode 100644
-index 0000000..7b285df
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/utils/vba_to_c_converter/.gitignore
-@@ -0,0 +1,4 @@
-+bin
-+obj
-+*.user
-+*.sdf
-\ No newline at end of file
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0627-drm-amd-dal-remove-MST-get_modes-flush_work.patch b/common/recipes-kernel/linux/files/0627-drm-amd-dal-remove-MST-get_modes-flush_work.patch
deleted file mode 100644
index 8f2b01f6..00000000
--- a/common/recipes-kernel/linux/files/0627-drm-amd-dal-remove-MST-get_modes-flush_work.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 38bb05256efbef226ccaa639dcac09ddad6c9542 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 15 Dec 2015 20:25:34 +0800
-Subject: [PATCH 0627/1110] drm/amd/dal: remove MST get_modes flush_work
-
-As DRM MST detection changed, this is not needed
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index fb71d88..56ca101 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -167,8 +167,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
- 	const struct dc_sink *sink;
- 	int ret = 0;
- 
--	flush_work(&master->mst_mgr.work);
--
- 	if (!aconnector->edid) {
- 		edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, aconnector->port);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0628-drm-amd-dal-create-actual-number-of-CRTCs.patch b/common/recipes-kernel/linux/files/0628-drm-amd-dal-create-actual-number-of-CRTCs.patch
deleted file mode 100644
index 15104b1d..00000000
--- a/common/recipes-kernel/linux/files/0628-drm-amd-dal-create-actual-number-of-CRTCs.patch
+++ /dev/null
@@ -1,257 +0,0 @@
-From d3efc3aa67f80f319aa7f2c7a6fd767292018596 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 15 Dec 2015 20:29:08 +0800
-Subject: [PATCH 0628/1110] drm/amd/dal: create actual number of CRTCs
-
-For MST we need to create actual number of CRTCs, not
-number of links.
-
-Consider the situation:
-
-1. One DDI DP connector available on board;
-2. One DRM CRTC created for it;
-3. DRM does not allow set mode on newly arrived MST downstream display
-as there is no connectors left, event though 3 is still available.
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 85 +++++++++-------------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 28 +++++--
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |  8 +-
- 3 files changed, 61 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index f85ce3b..c69ae16 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -578,10 +578,10 @@ error:
- 
- void amdgpu_dm_fini(struct amdgpu_device *adev)
- {
-+	amdgpu_dm_destroy_drm_device(&adev->dm);
- 	/*
- 	 * TODO: pageflip, vlank interrupt
- 	 *
--	 * amdgpu_dm_destroy_drm_device(&adev->dm);
- 	 * amdgpu_dm_irq_fini(adev);
- 	 */
- 
-@@ -1024,7 +1024,7 @@ void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
- int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- {
- 	struct amdgpu_display_manager *dm = &adev->dm;
--	uint32_t link_index;
-+	uint32_t i;
- 	struct amdgpu_connector *aconnector;
- 	struct amdgpu_encoder *aencoder;
- 	struct amdgpu_crtc *acrtc;
-@@ -1039,62 +1039,58 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 		return -1;
- 	}
- 
-+	for (i = 0; i < caps.max_targets; i++) {
-+		acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
-+		if (!acrtc)
-+			goto fail;
-+
-+		if (amdgpu_dm_crtc_init(
-+			dm,
-+			acrtc,
-+			i)) {
-+			DRM_ERROR("KMS: Failed to initialize crtc\n");
-+			kfree(acrtc);
-+			goto fail;
-+		}
-+	}
-+
-+	dm->display_indexes_num = caps.max_targets;
-+
- 	/* loops over all connectors on the board */
--	for (link_index = 0; link_index < link_cnt; link_index++) {
-+	for (i = 0; i < link_cnt; i++) {
- 
--		if (link_index > AMDGPU_DM_MAX_DISPLAY_INDEX) {
-+		if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
- 			DRM_ERROR(
--				"KMS: Cannot support more than %d display indeces\n",
-+				"KMS: Cannot support more than %d display indexes\n",
- 					AMDGPU_DM_MAX_DISPLAY_INDEX);
- 			continue;
- 		}
- 
- 		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
- 		if (!aconnector)
--			goto fail_connector;
-+			goto fail;
- 
- 		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
--		if (!aencoder)
--			goto fail_encoder;
--
--		acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
--		if (!acrtc)
--			goto fail_crtc;
--
--		if (amdgpu_dm_crtc_init(
--			dm,
--			acrtc,
--			link_index)) {
--			DRM_ERROR("KMS: Failed to initialize crtc\n");
--			goto fail;
-+		if (!aencoder) {
-+			goto fail_free_connector;
- 		}
- 
--		if (amdgpu_dm_encoder_init(
--			dm->ddev,
--			aencoder,
--			link_index,
--			acrtc)) {
-+		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
- 			DRM_ERROR("KMS: Failed to initialize encoder\n");
--			goto fail;
-+			goto fail_free_encoder;
- 		}
- 
--		if (amdgpu_dm_connector_init(
--			dm,
--			aconnector,
--			link_index,
--			aencoder)) {
-+		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
- 			DRM_ERROR("KMS: Failed to initialize connector\n");
--			goto fail;
-+			goto fail_free_connector;
- 		}
- 
--		dc_link_detect(dc_get_link_at_index(dm->dc, link_index));
-+		dc_link_detect(dc_get_link_at_index(dm->dc, i));
- 
- 		amdgpu_dm_update_connector_after_detect(
- 			aconnector);
- 	}
- 
--	dm->display_indexes_num = link_cnt;
--
- 	/* Software is initialized. Now we can register interrupt handlers. */
- 	switch (adev->asic_type) {
- 	case CHIP_CARRIZO:
-@@ -1111,28 +1107,17 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 	drm_mode_config_reset(dm->ddev);
- 
- 	return 0;
--
-+fail_free_encoder:
-+	kfree(aencoder);
-+fail_free_connector:
-+	kfree(aconnector);
- fail:
--	/* clean any dongling drm structure for the last (corrupted)
--	display target */
--	amdgpu_dm_crtc_destroy(&acrtc->base);
--fail_crtc:
--	amdgpu_dm_encoder_destroy(&aencoder->base);
--fail_encoder:
--	amdgpu_dm_connector_destroy(&aconnector->base);
--fail_connector:
--	if (dm->backlight_dev) {
--		backlight_device_unregister(dm->backlight_dev);
--		dm->backlight_dev = NULL;
--	}
- 	return -1;
- }
- 
--void amdgpu_dm_destroy_drm_device(
--				struct amdgpu_display_manager *dm)
-+void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
- {
- 	drm_mode_config_cleanup(dm->ddev);
--	/*switch_dev_unregister(&dm->hdmi_audio_dev);*/
- 	return;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index c98fdbf..3189e87 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1125,7 +1125,24 @@ int amdgpu_dm_connector_atomic_set_property(
- 
- void amdgpu_dm_connector_destroy(struct drm_connector *connector)
- {
--	/*drm_sysfs_connector_remove(connector);*/
-+	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
-+	const struct dc_link *link = aconnector->dc_link;
-+	struct amdgpu_device *adev = connector->dev->dev_private;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-+
-+	if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
-+		amdgpu_dm_register_backlight_device(dm);
-+
-+		if (dm->backlight_dev) {
-+			backlight_device_unregister(dm->backlight_dev);
-+			dm->backlight_dev = NULL;
-+		}
-+
-+	}
-+#endif
-+	drm_connector_unregister(connector);
- 	drm_connector_cleanup(connector);
- 	kfree(connector);
- }
-@@ -1530,7 +1547,7 @@ static uint32_t rgb_formats[] = {
- 
- int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 			struct amdgpu_crtc *acrtc,
--			uint32_t link_index)
-+			uint32_t crtc_index)
- {
- 	int res = -ENOMEM;
- 
-@@ -1571,10 +1588,10 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 	acrtc->max_cursor_width = 128;
- 	acrtc->max_cursor_height = 128;
- 
--	acrtc->crtc_id = link_index;
-+	acrtc->crtc_id = crtc_index;
- 	acrtc->base.enabled = false;
- 
--	dm->adev->mode_info.crtcs[link_index] = acrtc;
-+	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
- 	drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
- 
- 	return 0;
-@@ -1897,8 +1914,7 @@ int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
- int amdgpu_dm_encoder_init(
- 	struct drm_device *dev,
- 	struct amdgpu_encoder *aencoder,
--	uint32_t link_index,
--	struct amdgpu_crtc *acrtc)
-+	uint32_t link_index)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 5d1152e..d737e33 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -43,10 +43,10 @@ int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
- 			struct amdgpu_connector *amdgpu_connector,
- 			uint32_t link_index,
- 			struct amdgpu_encoder *amdgpu_encoder);
--int amdgpu_dm_encoder_init(struct drm_device *dev,
--			struct amdgpu_encoder *amdgpu_encoder,
--			uint32_t link_index,
--			struct amdgpu_crtc *amdgpu_crtc);
-+int amdgpu_dm_encoder_init(
-+	struct drm_device *dev,
-+	struct amdgpu_encoder *aencoder,
-+	uint32_t link_index);
- 
- void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
- void amdgpu_dm_connector_destroy(struct drm_connector *connector);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0629-drm-amd-dal-remove-sink-from-MST-link.patch b/common/recipes-kernel/linux/files/0629-drm-amd-dal-remove-sink-from-MST-link.patch
deleted file mode 100644
index 0c810ae4..00000000
--- a/common/recipes-kernel/linux/files/0629-drm-amd-dal-remove-sink-from-MST-link.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 135156ce80dfeb517b3f0bb197c94be978267f6a Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 17 Dec 2015 19:19:08 +0800
-Subject: [PATCH 0629/1110] drm/amd/dal: remove sink from MST link
-
-When we remove MST display downstream, we should remove
-sink during connector destruction.
-
-Also do not report error if sink already removed from link.
-This can happen in case of physical disconnect of mst branch.
-
-Links will be removed in dc_link_detect. But fake removal in
-MST connector destruction is not of harm, as sink not in
-array already
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 7 +++++--
- drivers/gpu/drm/amd/dal/dc/core/dc.c                    | 2 --
- 2 files changed, 5 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 56ca101..164d80a 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -74,7 +74,8 @@ dm_dp_mst_detect(struct drm_connector *connector, bool force)
- 			&master->mst_mgr,
- 			aconnector->port);
- 
--	if (status == connector_status_disconnected && aconnector->dc_sink) {
-+	if (status == connector_status_disconnected && aconnector->edid) {
-+		kfree(aconnector->edid);
- 		aconnector->edid = NULL;
- 	}
- 
-@@ -334,7 +335,9 @@ static void dm_dp_destroy_mst_connector(
- 	drm_connector_cleanup(connector);
- 	drm_modeset_unlock_all(dev);
- 
--	kfree(connector);
-+	dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
-+
-+	kfree(aconnector);
- 	DRM_DEBUG_KMS("\n");
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index a37cd87..4a75cb9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -992,6 +992,4 @@ void dc_link_remove_sink(const struct dc_link *link, const struct dc_sink *sink)
- 			return;
- 		}
- 	}
--
--	BREAK_TO_DEBUGGER();
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0630-drm-amd-dal-return-actual-contollers-number-in-caps.patch b/common/recipes-kernel/linux/files/0630-drm-amd-dal-return-actual-contollers-number-in-caps.patch
deleted file mode 100644
index 73f84191..00000000
--- a/common/recipes-kernel/linux/files/0630-drm-amd-dal-return-actual-contollers-number-in-caps.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From c83273cc2b8cf4f4bcd734d8c3230041bf19cb9a Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 15 Dec 2015 20:31:48 +0800
-Subject: [PATCH 0630/1110] drm/amd/dal: return actual contollers number in
- caps
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 4a75cb9..941d167 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -741,7 +741,7 @@ const struct audio **dc_get_audios(struct dc *dc)
- 
- void dc_get_caps(const struct dc *dc, struct dc_caps *caps)
- {
--    caps->max_targets = dal_min(dc->res_pool.controller_count, dc->link_count);
-+    caps->max_targets = dc->res_pool.controller_count;
-     caps->max_links = dc->link_count;
-     caps->max_audios = dc->res_pool.audio_count;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0631-drm-amd-dal-fix-reset-mode-warning-msg.patch b/common/recipes-kernel/linux/files/0631-drm-amd-dal-fix-reset-mode-warning-msg.patch
deleted file mode 100644
index da97af7f..00000000
--- a/common/recipes-kernel/linux/files/0631-drm-amd-dal-fix-reset-mode-warning-msg.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From d2a0579cf2cd7889a8bc17117e848f79a5575c47 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 3 Mar 2016 17:44:33 -0500
-Subject: [PATCH 0631/1110] drm/amd/dal: fix reset mode warning msg
-
-We should call surface programming in case of mode
-reset (actual reset or DPMS). Warning was printed
-that target is NULL.
-
-Also removed debug prints for buffers prepare/remove,
-that occurs on each pageflip and pollutes log
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 3189e87..910f646 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1430,7 +1430,6 @@ static int dm_plane_helper_prepare_fb(
- 
- 	afb = to_amdgpu_framebuffer(new_state->fb);
- 
--	DRM_DEBUG_KMS("Pin new framebuffer: %p\n", afb);
- 	obj = afb->obj;
- 	rbo = gem_to_amdgpu_bo(obj);
- 	r = amdgpu_bo_reserve(rbo, false);
-@@ -1461,7 +1460,6 @@ static void dm_plane_helper_cleanup_fb(
- 		return;
- 
- 	afb = to_amdgpu_framebuffer(old_state->fb);
--	DRM_DEBUG_KMS("Unpin old framebuffer: %p\n", afb);
- 	rbo = gem_to_amdgpu_bo(afb->obj);
- 	r = amdgpu_bo_reserve(rbo, false);
- 	if (unlikely(r)) {
-@@ -2273,7 +2271,8 @@ int amdgpu_dm_atomic_commit(
- 		struct drm_connector *connector;
- 		struct dm_connector_state *dm_state = NULL;
- 
--		if (!fb || !crtc || !crtc->state->planes_changed)
-+		if (!fb || !crtc || !crtc->state->planes_changed ||
-+			!crtc->state->active)
- 			continue;
- 
- 		if (page_flip_needed(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0632-drm-amd-dal-attach-tile-MST-connector-property.patch b/common/recipes-kernel/linux/files/0632-drm-amd-dal-attach-tile-MST-connector-property.patch
deleted file mode 100644
index 68b4095e..00000000
--- a/common/recipes-kernel/linux/files/0632-drm-amd-dal-attach-tile-MST-connector-property.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From a590fa50f6476c14d33cbd8b3a7ff0ee6deef1fc Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 17 Dec 2015 19:30:54 +0800
-Subject: [PATCH 0632/1110] drm/amd/dal: attach tile MST connector property
-
-As it is used in DRM code, it is better to be initialized
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 164d80a..4704204 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -297,6 +297,10 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 		&connector->base,
- 		dev->mode_config.path_property,
- 		0);
-+	drm_object_attach_property(
-+		&connector->base,
-+		dev->mode_config.tile_property,
-+		0);
- 
- 	drm_mode_connector_set_path_property(connector, pathprop);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0633-drm-amd-dal-change-in-MST-connector-detection.patch b/common/recipes-kernel/linux/files/0633-drm-amd-dal-change-in-MST-connector-detection.patch
deleted file mode 100644
index 54872241..00000000
--- a/common/recipes-kernel/linux/files/0633-drm-amd-dal-change-in-MST-connector-detection.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 4961892bc6ef5703863922ed00a9901e5df8c862 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 17 Dec 2015 19:32:45 +0800
-Subject: [PATCH 0633/1110] drm/amd/dal: change in MST connector detection
-
-Only report connector as connected when edid available on
-it. This will make sink available on connector in all
-cases.
-
-It also guarantees that we safe if any hotplug notifications
-come.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 4704204..7ef2e60 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -79,6 +79,14 @@ dm_dp_mst_detect(struct drm_connector *connector, bool force)
- 		aconnector->edid = NULL;
- 	}
- 
-+	/*
-+	 * we do not want to make this connector connected until we have edid on
-+	 * it
-+	 */
-+	if (status == connector_status_connected &&
-+		!aconnector->port->cached_edid)
-+		status = connector_status_disconnected;
-+
- 	return status;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0634-drm-amd-dal-set-scaling-to-2-taps-until-proper-story.patch b/common/recipes-kernel/linux/files/0634-drm-amd-dal-set-scaling-to-2-taps-until-proper-story.patch
deleted file mode 100644
index b21f16b1..00000000
--- a/common/recipes-kernel/linux/files/0634-drm-amd-dal-set-scaling-to-2-taps-until-proper-story.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 7a06bcc4c4b80aae60c36d678c292ab9e6303e40 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 17 Dec 2015 15:01:14 -0500
-Subject: [PATCH 0634/1110] drm/amd/dal: set scaling to 2 taps until proper
- story
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 910f646..50bd964 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -499,8 +499,8 @@ static void fill_plane_attributes_from_fb(
- /* TODO: unhardcode */
- 	surface->colorimetry.limited_range = false;
- 	surface->colorimetry.color_space = SURFACE_COLOR_SPACE_SRGB;
--	surface->scaling_quality.h_taps = 4;
--	surface->scaling_quality.v_taps = 4;
-+	surface->scaling_quality.h_taps = 2;
-+	surface->scaling_quality.v_taps = 2;
- 	surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
- 
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0635-drm-amd-dal-Switch-from-MST-state-to-our-own-flag-si.patch b/common/recipes-kernel/linux/files/0635-drm-amd-dal-Switch-from-MST-state-to-our-own-flag-si.patch
deleted file mode 100644
index f6d9f581..00000000
--- a/common/recipes-kernel/linux/files/0635-drm-amd-dal-Switch-from-MST-state-to-our-own-flag-si.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 7166707dad450ace2190bb13f9faffa6a2be911a Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Thu, 17 Dec 2015 16:01:54 -0500
-Subject: [PATCH 0635/1110] drm/amd/dal: Switch from MST state to our own flag
- since it set in same thread.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index c69ae16..a62c7db 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -734,7 +734,7 @@ void amdgpu_dm_update_connector_after_detect(
- 	const struct dc_sink *sink;
- 
- 	/* MST handled by drm_mst framework */
--	if (aconnector->mst_mgr.mst_state)
-+	if (aconnector->is_mst_connector)
- 		return;
- 
- 	if (!dm_get_sink_from_link(dc_link, aconnector, &sink)) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0636-drm-amd-dal-Modifed-check-conditions-for-switch-dp-c.patch b/common/recipes-kernel/linux/files/0636-drm-amd-dal-Modifed-check-conditions-for-switch-dp-c.patch
deleted file mode 100644
index 92412781..00000000
--- a/common/recipes-kernel/linux/files/0636-drm-amd-dal-Modifed-check-conditions-for-switch-dp-c.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 316a9a10e0046cd4eafe57f575e4591721c5a897 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Thu, 17 Dec 2015 16:13:59 -0500
-Subject: [PATCH 0636/1110] drm/amd/dal: Modifed check conditions for switch dp
- clock source.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c           | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 3 ++-
- 2 files changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 861d80a..ef13968 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -71,7 +71,7 @@ static bool is_sharable_clk_src(
- 	if (stream_with_clk_src->clock_source == NULL)
- 		return false;
- 
--	if (!dc_is_dp_signal(stream->signal) && id == CLOCK_SOURCE_ID_EXTERNAL)
-+	if (id == CLOCK_SOURCE_ID_EXTERNAL)
- 		return false;
- 
- 	if(!is_same_timing(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 10cc727..d944781 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1250,7 +1250,8 @@ static void switch_dp_clock_sources(
- 					find_used_clk_src_for_sharing(
- 							val_context, stream);
- 
--				if (clk_src != stream->clock_source) {
-+				if (clk_src &&
-+					clk_src != stream->clock_source) {
- 					unreference_clock_source(
- 							&val_context->res_ctx,
- 							stream->clock_source);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0637-drm-amd-dal-Do-not-dereference-NULL-sink-at-the-end-.patch b/common/recipes-kernel/linux/files/0637-drm-amd-dal-Do-not-dereference-NULL-sink-at-the-end-.patch
deleted file mode 100644
index 196818eb..00000000
--- a/common/recipes-kernel/linux/files/0637-drm-amd-dal-Do-not-dereference-NULL-sink-at-the-end-.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 011186be4edf1b60f71a8a19c0234660e9a84bb9 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 17 Dec 2015 15:02:29 -0500
-Subject: [PATCH 0637/1110] drm/amd/dal: Do not dereference NULL sink at the
- end of sink detection.
-
-While printing detection results for Disconnect case a null sink pointer
-was dereferenced.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 12 +++++++-----
- 1 file changed, 7 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index add76ca..d4b1085 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -647,11 +647,13 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		link_disconnect_all_sinks(link);
- 	}
- 
--	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
--		link->link_index, &sink->public,
--		(signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected"));
--
--	/* TODO: */
-+	if (signal == SIGNAL_TYPE_NONE) {
-+		LINK_INFO("link=%d is now Disconnected.\n",
-+				link->link_index);
-+	} else {
-+		LINK_INFO("link=%d is now Connected. Sink ptr=%p Signal=%d\n",
-+				link->link_index, &sink->public, signal);
-+	}
- 
- 	return;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0638-drm-amd-dal-Fix-NULL-pointer-derefference-on-set-mod.patch b/common/recipes-kernel/linux/files/0638-drm-amd-dal-Fix-NULL-pointer-derefference-on-set-mod.patch
deleted file mode 100644
index 0fa57829..00000000
--- a/common/recipes-kernel/linux/files/0638-drm-amd-dal-Fix-NULL-pointer-derefference-on-set-mod.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 24a7470d5d199476c2ecc66499c900cfb08ef70b Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Thu, 17 Dec 2015 16:25:57 -0500
-Subject: [PATCH 0638/1110] drm/amd/dal: Fix NULL pointer derefference on set
- mode
-
-The preferreed mode could be zero
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 50bd964..bbadc59 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -893,6 +893,10 @@ static struct dc_target *create_target_for_sink(
- 				&aconnector->base.modes,
- 				struct drm_display_mode,
- 				head);
-+	if (NULL == preferred_mode) {
-+		DRM_ERROR("No preferred mode found\n");
-+		goto stream_create_fail;
-+	}
- 
- 	decide_crtc_timing_for_drm_display_mode(
- 			&mode, preferred_mode,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0639-drm-amd-dal-get-modes-in-get_modes-instead-of-cachin.patch b/common/recipes-kernel/linux/files/0639-drm-amd-dal-get-modes-in-get_modes-instead-of-cachin.patch
deleted file mode 100644
index 55a7d3e4..00000000
--- a/common/recipes-kernel/linux/files/0639-drm-amd-dal-get-modes-in-get_modes-instead-of-cachin.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 790ec28579208fa4331b7cffc0c0b76135145c8e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 16 Dec 2015 17:02:52 -0500
-Subject: [PATCH 0639/1110] drm/amd/dal: get modes in get_modes, instead of
- caching
-
-The old way of populating modes no longer works in the drm-next
-kernel tree.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c       | 1 -
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 4 +---
- 2 files changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index a62c7db..b2b7820 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -775,7 +775,6 @@ void amdgpu_dm_update_connector_after_detect(
- 				(struct edid *) sink->dc_edid.raw_edid;
- 			drm_mode_connector_update_edid_property(connector,
- 					aconnector->edid);
--			amdgpu_dm_connector_get_modes(&aconnector->base);
- 		}
- 	} else {
- 		drm_mode_connector_update_edid_property(connector, NULL);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index bbadc59..a4ec911 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1237,9 +1237,7 @@ static struct drm_encoder *best_encoder(struct drm_connector *connector)
- 
- static int get_modes(struct drm_connector *connector)
- {
--	struct amdgpu_connector *amdgpu_connector =
--			to_amdgpu_connector(connector);
--	return amdgpu_connector->num_modes;
-+	return amdgpu_dm_connector_get_modes(connector);
- }
- 
- int amdgpu_dm_connector_mode_valid(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0640-drm-amd-dal-set-gamma-flag-in-future-state.patch b/common/recipes-kernel/linux/files/0640-drm-amd-dal-set-gamma-flag-in-future-state.patch
deleted file mode 100644
index 132a3d2e..00000000
--- a/common/recipes-kernel/linux/files/0640-drm-amd-dal-set-gamma-flag-in-future-state.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From b8373c165a002c742ba94cdc3f74d111039b7f83 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 17 Dec 2015 18:56:03 -0500
-Subject: [PATCH 0640/1110] drm/amd/dal: set gamma flag in future state
-
-This fixes the set gamma regression
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a4ec911..0062404 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -941,7 +941,7 @@ static void amdgpu_dm_atomic_crtc_gamma_set(
- 	struct drm_device *dev = crtc->dev;
- 	struct drm_property *prop = dev->mode_config.prop_crtc_id;
- 
--	crtc->mode.private_flags |= AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
-+	crtc->state->mode.private_flags |= AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
- 
- 	drm_atomic_helper_crtc_set_property(crtc, prop, 0);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0641-drm-amd-dal-Remove-dead-headers.patch b/common/recipes-kernel/linux/files/0641-drm-amd-dal-Remove-dead-headers.patch
deleted file mode 100644
index efe9d9ce..00000000
--- a/common/recipes-kernel/linux/files/0641-drm-amd-dal-Remove-dead-headers.patch
+++ /dev/null
@@ -1,2319 +0,0 @@
-From 359a1cc0ce2c139d86022274e682c1a7b0780018 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 17 Dec 2015 20:48:16 -0500
-Subject: [PATCH 0641/1110] drm/amd/dal: Remove dead headers
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |   8 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_gamut.c |   1 -
- .../drm/amd/dal/dc/dce_base/dce_base_resource.c    |   1 -
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     |   1 +
- .../gpu/drm/amd/dal/include/adjustment_interface.h | 230 --------------
- drivers/gpu/drm/amd/dal/include/bit_set.h          |  61 ----
- drivers/gpu/drm/amd/dal/include/dal_types.h        |   4 +-
- drivers/gpu/drm/amd/dal/include/dcs_interface.h    | 351 ---------------------
- .../gpu/drm/amd/dal/include/ddc_service_types.h    |   2 -
- .../amd/dal/include/default_mode_list_interface.h  |  37 ---
- .../gpu/drm/amd/dal/include/display_path_types.h   | 132 --------
- .../dal/include/dpcd_access_service_interface.h    |  65 ----
- drivers/gpu/drm/amd/dal/include/gpu_clock_info.h   |  43 ---
- drivers/gpu/drm/amd/dal/include/gpu_interface.h    |  91 ------
- .../gpu/drm/amd/dal/include/hw_adjustment_set.h    |  50 ---
- .../amd/dal/include/hw_path_mode_set_interface.h   |  48 ---
- drivers/gpu/drm/amd/dal/include/isr_config_types.h | 157 ---------
- .../gpu/drm/amd/dal/include/mode_manager_types.h   |  71 -----
- .../gpu/drm/amd/dal/include/mode_query_interface.h |  93 ------
- .../amd/dal/include/mode_timing_list_interface.h   |  51 ---
- .../gpu/drm/amd/dal/include/overlay_interface.h    | 137 --------
- drivers/gpu/drm/amd/dal/include/overlay_types.h    | 164 ----------
- .../drm/amd/dal/include/path_mode_set_interface.h  | 107 -------
- .../amd/dal/include/set_mode_params_interface.h    | 101 ------
- .../amd/dal/include/timing_list_query_interface.h  |  69 ----
- 25 files changed, 6 insertions(+), 2069 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/include/adjustment_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/bit_set.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/dcs_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/display_path_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/gpu_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/isr_config_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/mode_manager_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/mode_query_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/overlay_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/overlay_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 0062404..e142508 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -37,12 +37,6 @@
- #undef FRAME_SIZE
- #undef DEPRECATED
- 
--#include "mode_query_interface.h"
--#include "dcs_types.h"
--#include "mode_manager_types.h"
--
--/*#include "amdgpu_buffer.h"*/
--
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
-@@ -505,6 +499,8 @@ static void fill_plane_attributes_from_fb(
- 
- }
- 
-+#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
-+
- static void fill_gamma_from_crtc(
- 	const struct drm_crtc *crtc,
- 	struct dc_surface *dc_surface)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-index a5b5b01..0dd4355 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-@@ -27,7 +27,6 @@
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
- #include "include/fixed31_32.h"
--#include "include/hw_sequencer_types.h"
- #include "basics/conversion.h"
- #include "include/grph_object_id.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-index 8996475..3633402 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -26,7 +26,6 @@
- 
- #include "dc_services.h"
- 
--#include "adjustment_types.h"
- #include "set_mode_types.h"
- #include "stream_encoder.h"
- #include "link_encoder.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-index 08e046b..660f80f 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -30,6 +30,7 @@
- #include "dal_services.h"
- #include "include/gpio_interface.h"
- #include "include/ddc_interface.h"
-+/* TODO remove dvo */
- #include "include/dvo_interface.h"
- #include "include/irq_interface.h"
- #include "include/gpio_service_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/include/adjustment_interface.h b/drivers/gpu/drm/amd/dal/include/adjustment_interface.h
-deleted file mode 100644
-index 64a9f9f..0000000
---- a/drivers/gpu/drm/amd/dal/include/adjustment_interface.h
-+++ /dev/null
-@@ -1,230 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_ADJUSTMENT_INTERFACE_H__
--#define __DAL_ADJUSTMENT_INTERFACE_H__
--
--#include "include/display_service_types.h"
--#include "include/adjustment_types.h"
--#include "include/overlay_types.h"
--#include "include/display_path_interface.h"
--
--struct ds_underscan_desc;
--struct adj_container;
--struct info_frame;
--struct ds_dispatch;
--struct hw_adjustment_set;
--struct path_mode;
--struct hw_path_mode;
--
--enum build_path_set_reason;
--
--bool dal_ds_dispatch_is_adjustment_supported(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id adjust_id);
--
--enum ds_return dal_ds_dispatch_get_type(
--	struct ds_dispatch *adj,
--	enum adjustment_id adjust_id,
--	enum adjustment_data_type *type);
--
--enum ds_return dal_ds_dispatch_get_property(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	enum adjustment_id adjust_id,
--	union adjustment_property *property);
--
--enum ds_return dal_ds_dispatch_set_adjustment(
--	struct ds_dispatch *ds,
--	const uint32_t display_index,
--	enum adjustment_id adjust_id,
--	int32_t value);
--
--enum ds_return dal_ds_dispatch_get_adjustment_current_value(
--	struct ds_dispatch *ds,
--	struct adj_container *container,
--	struct adjustment_info *info,
--	enum adjustment_id id,
--	bool fall_back_to_default);
--
--enum ds_return dal_ds_dispatch_get_adjustment_value(
--	struct ds_dispatch *ds,
--	struct display_path *disp_path,
--	enum adjustment_id adj_id,
--	bool fall_back_to_default,
--	int32_t *value);
--
--const struct raw_gamma_ramp *dal_ds_dispatch_get_current_gamma(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id adjust_id);
--
--const struct raw_gamma_ramp *dal_ds_dispatch_get_default_gamma(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id adjust_id);
--
--enum ds_return dal_ds_dispatch_set_current_gamma(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id adjust_id,
--	const struct raw_gamma_ramp *gamma);
--
--enum ds_return dal_ds_dispatch_set_gamma(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id adjust_id,
--	const struct raw_gamma_ramp *gamma);
--
--bool dal_ds_dispatch_get_underscan_info(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	struct ds_underscan_info *info);
--
--bool dal_ds_dispatch_get_underscan_mode(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	struct ds_underscan_desc *desc);
--
--bool dal_ds_dispatch_set_underscan_mode(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	struct ds_underscan_desc *desc);
--
--bool dal_ds_dispatch_setup_overlay(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	struct overlay_data *data);
--
--struct adj_container *dal_ds_dispatch_get_adj_container_for_path(
--	const struct ds_dispatch *ds,
--	uint32_t display_index);
--
--void dal_ds_dispatch_set_applicable_adj(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	const struct adj_container *applicable);
--
--enum ds_return dal_ds_dispatch_set_color_gamut(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	const struct ds_set_gamut_data *data);
--
--enum ds_return dal_ds_dispatch_get_color_gamut(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	const struct ds_gamut_reference_data *ref,
--	struct ds_get_gamut_data *data);
--
--enum ds_return dal_ds_dispatch_get_color_gamut_info(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	const struct ds_gamut_reference_data *ref,
--	struct ds_gamut_info *data);
--
--enum ds_return dal_ds_dispatch_get_regamma_lut(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	struct ds_regamma_lut *data);
--
--enum ds_return dal_ds_dispatch_set_regamma_lut(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	struct ds_regamma_lut *data);
--
--enum ds_return dal_ds_dispatch_set_info_packets(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	const struct info_frame *info_frames);
--
--enum ds_return dal_ds_dispatch_get_info_packets(
--	struct ds_dispatch *adj,
--	uint32_t display_index,
--	struct info_frame *info_frames);
--
--bool dal_ds_dispatch_initialize_adjustment(struct ds_dispatch *ds);
--
--void dal_ds_dispatch_cleanup_adjustment(struct ds_dispatch *ds);
--
--bool dal_ds_dispatch_build_post_set_mode_adj(
--	struct ds_dispatch *ds,
--	const struct path_mode *mode,
--	struct display_path *display_path,
--	struct hw_adjustment_set *set);
--
--bool dal_ds_dispatch_build_color_control_adj(
--	struct ds_dispatch *ds,
--	const struct path_mode *mode,
--	struct display_path *display_path,
--	struct hw_adjustment_set *set);
--
--bool dal_ds_dispatch_build_include_adj(
--	struct ds_dispatch *ds,
--	const struct path_mode *mode,
--	struct display_path *display_path,
--	struct hw_path_mode *hw_mode,
--	struct hw_adjustment_set *set);
--
--bool dal_ds_dispatch_apply_scaling(
--	struct ds_dispatch *ds,
--	const struct path_mode *mode,
--	struct adj_container *adj_container,
--	enum build_path_set_reason reason,
--	struct hw_path_mode *hw_mode);
--
--void dal_ds_dispatch_update_adj_container_for_path_with_mode_info(
--	struct ds_dispatch *ds,
--	struct display_path *display_path,
--	const struct path_mode *path_mode);
--
--enum ds_return dal_ds_dispatch_get_adjustment_info(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id adjust_id,
--	struct adjustment_info *adj_info);
--
--bool dal_ds_dispatch_include_adjustment(
--	struct ds_dispatch *ds,
--	struct display_path *disp_path,
--	struct ds_adj_id_value adj,
--	struct hw_adjustment_set *set);
--
--enum ds_return dal_ds_dispatch_set_gamma_adjustment(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum adjustment_id ad_id,
--	const struct raw_gamma_ramp *gamma);
--
--void dal_ds_dispatch_update_adj_container_for_path_with_color_space(
--	struct ds_dispatch *ds,
--	uint32_t display_index,
--	enum ds_color_space color_space);
--
--void dal_ds_dispatch_setup_default_regamma(
--	struct ds_dispatch *ds,
--	struct ds_regamma_lut *regamma);
--
--#endif /* __DAL_ADJUSTMENT_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/bit_set.h b/drivers/gpu/drm/amd/dal/include/bit_set.h
-deleted file mode 100644
-index 3cd8d32..0000000
---- a/drivers/gpu/drm/amd/dal/include/bit_set.h
-+++ /dev/null
-@@ -1,61 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_BIT_SET_H__
--#define __DAL_BIT_SET_H__
--
--struct bit_set_iterator_32 {
--	uint32_t value;
--};
--
--static inline uint32_t least_significant_bit(uint32_t bs32_container)
--{
--	return bs32_container & (0 - bs32_container);
--}
--/* iterates over bit_set_iterator by means of least significant bit purge*/
--static inline uint32_t get_next_significant_bit(
--		struct bit_set_iterator_32 *bs32)
--{
--	uint32_t lsb = least_significant_bit(bs32->value);
--
--	bs32->value &= ~lsb;
--	return lsb;
--}
--
--static inline void bit_set_iterator_reset_to_mask(
--		struct bit_set_iterator_32 *bs32,
--		uint32_t mask)
--{
--	bs32->value = mask;
--}
--
--static inline void bit_set_iterator_construct(
--		struct bit_set_iterator_32 *bs32,
--		uint32_t mask)
--{
--	bit_set_iterator_reset_to_mask(bs32, mask);
--}
--
--#endif /* __DAL_BIT_SET_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index d3c91b9..5539c19 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -26,7 +26,9 @@
- #ifndef __DAL_TYPES_H__
- #define __DAL_TYPES_H__
- 
--#include "dcs_types.h"
-+#include "signal_types.h"
-+#include "dc_types.h"
-+
- struct dal_logger;
- 
- enum dce_version {
-diff --git a/drivers/gpu/drm/amd/dal/include/dcs_interface.h b/drivers/gpu/drm/amd/dal/include/dcs_interface.h
-deleted file mode 100644
-index b3474cf..0000000
---- a/drivers/gpu/drm/amd/dal/include/dcs_interface.h
-+++ /dev/null
-@@ -1,351 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_DCS_INTERFACE_H__
--#define __DAL_DCS_INTERFACE_H__
--
--#include "dcs_types.h"
--#include "grph_object_id.h"
--
--struct dal_context;
--struct dcs;
--struct ddc_service;
--enum ddc_transaction_type;
--enum ddc_result;
--struct display_sink_capability;
--enum dc_timing_3d_format;
--
--struct dcs_cea_audio_mode_list;
--struct dcs_customized_mode_list;
--
--struct dcs_init_data {
--	struct dal_context *dal;
--	struct adapter_service *as;
--	struct timing_service *ts;
--	enum dcs_interface_type interface_type;
--	struct graphics_object_id grph_obj_id;
--};
--
--struct dcs_cea_audio_mode_list *dal_dcs_cea_audio_mode_list_create(
--	uint32_t list_size);
--
--void dal_dcs_cea_audio_mode_list_destroy(
--	struct dcs_cea_audio_mode_list **list);
--
--bool dal_dcs_cea_audio_mode_list_append(
--	struct dcs_cea_audio_mode_list *list,
--	struct cea_audio_mode *cea_audio_mode);
--uint32_t dal_dcs_cea_audio_mode_list_get_count(
--	const struct dcs_cea_audio_mode_list *list);
--void dal_dcs_cea_audio_mode_list_clear(
--	struct dcs_cea_audio_mode_list *list);
--
--struct cea_audio_mode *dal_dcs_cea_audio_mode_list_at_index(
--	const struct dcs_cea_audio_mode_list *list,
--	uint32_t index);
--
--struct dcs *dal_dcs_create(const struct dcs_init_data *init_data);
--
--void dal_dcs_destroy(struct dcs **dcs);
--
--enum edid_retrieve_status dal_dcs_retrieve_raw_edid(struct dcs *dcs);
--
--uint32_t dal_dcs_get_edid_raw_data_size(struct dcs *dcs);
--
--enum edid_retrieve_status dal_dcs_override_raw_edid(
--	struct dcs *dcs,
--	uint32_t len,
--	uint8_t *data);
--
--const uint8_t *dal_dcs_get_edid_raw_data(
--	struct dcs *dcs,
--	uint32_t *buff_size);
--
--enum edid_retrieve_status dal_dcs_update_edid_from_last_retrieved(
--	struct dcs *dcs);
--
--/*Update DDC Service.  returns the old DdcService being replaced*/
--struct ddc_service *dal_dcs_update_ddc(
--	struct dcs *dcs,
--	struct ddc_service *ddc);
--
--void dal_dcs_set_transaction_type(
--	struct dcs *dcs,
--	enum ddc_transaction_type type);
--
--/*updates the ModeTimingList of given path with
--ModeTiming reported by this DCS*/
--void dal_dcs_update_ts_timing_list_on_display(
--	struct dcs *dcs,
--	uint32_t display_index);
--
--/* DDC query on generic slave address*/
--bool dal_dcs_query_ddc_data(
--	struct dcs *dcs,
--	uint32_t address,
--	uint8_t *write_buf,
--	uint32_t write_buff_size,
--	uint8_t *read_buff,
--	uint32_t read_buff_size);
--
--bool dal_dcs_get_vendor_product_id_info(
--	struct dcs *dcs,
--	struct vendor_product_id_info *info);
--
--bool dal_dcs_get_display_name(struct dcs *dcs, uint8_t *name, uint32_t size);
--
--bool dal_dcs_get_display_characteristics(
--	struct dcs *dcs,
--	struct display_characteristics *characteristics);
--
--bool dal_dcs_get_screen_info(
--	struct dcs *dcs,
--	struct edid_screen_info *info);
--
--enum dcs_edid_connector_type dal_dcs_get_connector_type(struct dcs *dcs);
--
--bool dal_dcs_get_display_pixel_encoding(
--	struct dcs *dcs,
--	struct display_pixel_encoding_support *pe);
--
--enum display_dongle_type dal_dcs_get_dongle_type(struct dcs *dcs);
--
--void dal_dcs_query_sink_capability(
--	struct dcs *dcs,
--	struct display_sink_capability *sink_cap,
--	bool hpd_sense_bit);
--
--void dal_dcs_reset_sink_capability(struct dcs *dcs);
--
--bool dal_dcs_get_sink_capability(
--	struct dcs *dcs,
--	struct display_sink_capability *sink_cap);
--
--bool dal_dcs_emulate_sink_capability(
--	struct dcs *dcs,
--	struct display_sink_capability *sink_cap);
--
--bool dal_dcs_get_display_color_depth(
--	struct dcs *dcs,
--	struct display_color_depth_support *color_depth);
--
--bool dal_dcs_get_display_pixel_encoding(
--	struct dcs *dcs,
--	struct display_pixel_encoding_support *pixel_encoding);
--
--bool dal_dcs_get_cea861_support(
--	struct dcs *dcs,
--	struct cea861_support *cea861_support);
--
--bool dal_dcs_get_cea_vendor_specific_data_block(
--	struct dcs *dcs,
--	struct cea_vendor_specific_data_block *vendor_block);
--
--bool dal_dcs_get_cea_speaker_allocation_data_block(
--	struct dcs *dcs,
--	enum signal_type signal,
--	union cea_speaker_allocation_data_block *spkr_data);
--
--bool dal_dcs_get_cea_colorimetry_data_block(
--	struct dcs *dcs,
--	struct cea_colorimetry_data_block *colorimetry_data_block);
--
--bool dal_dcs_get_cea_video_capability_data_block(
--	struct dcs *dcs,
--	union cea_video_capability_data_block *video_capability_data_block);
--
--uint32_t dal_dcs_get_extensions_num(struct dcs *dcs);
--
--const struct dcs_cea_audio_mode_list *dal_dcs_get_cea_audio_modes(
--	struct dcs *dcs,
--	enum signal_type signal);
--
--bool dal_dcs_is_audio_supported(struct dcs *dcs);
--
--bool dal_dcs_validate_customized_mode(
--	struct dcs *dcs,
--	const struct dcs_customized_mode *customized_mode);
--
--bool dal_dcs_add_customized_mode(
--	struct dcs *dcs,
--	struct dcs_customized_mode *customized_mode);
--
--bool dal_dcs_delete_customized_mode(struct dcs *dcs, uint32_t index);
--
--const struct dcs_customized_mode_list *dal_dcs_get_customized_modes(
--	struct dcs *dcs);
--
--bool dal_dcs_delete_mode_timing_override(
--	struct dcs *dcs,
--	struct dcs_override_mode_timing *dcs_mode_timing);
--
--bool dal_dcs_set_mode_timing_override(
--	struct dcs *dcs,
--	uint32_t display_index,
--	struct dcs_override_mode_timing *dcs_mode_timing);
--
--bool dal_dcs_get_timing_override_for_mode(
--	struct dcs *dcs,
--	uint32_t display_index,
--	struct dc_mode_info *mode_info,
--	struct dcs_override_mode_timing_list *dcs_mode_timing_list);
--
--uint32_t dal_dcs_get_num_mode_timing_overrides(struct dcs *dcs);
--
--bool dal_dcs_get_timing_override_list(
--	struct dcs *dcs,
--	uint32_t display_index,
--	struct dcs_override_mode_timing_list *dcs_mode_timing_list,
--	uint32_t size);
--
--bool dal_dcs_get_supported_force_hdtv_mode(
--	struct dcs *dcs,
--	union hdtv_mode_support *hdtv_mode);
--
--bool dal_dcs_get_user_force_hdtv_mode(
--	struct dcs *dcs,
--	union hdtv_mode_support *hdtv_mode);
--
--bool dal_dcs_set_user_force_hdtv_mode(
--	struct dcs *dcs,
--	const union hdtv_mode_support *hdtv_mode);
--
--bool dal_dcs_get_fid9204_allow_ce_mode_only_option(
--	struct dcs *dcs,
--	bool is_hdmi,
--	bool *enable);
--
--bool dal_dcs_set_fid9204_allow_ce_mode_only_option(
--	struct dcs *dcs,
--	bool is_hdmi,
--	bool enable);
--
--bool dal_dcs_get_panel_misc_info(
--	struct dcs *dcs,
--	union panel_misc_info *panel_info);
--
--enum ddc_result dal_dcs_dpcd_read(
--	struct dcs *dcs,
--	uint32_t address,
--	uint8_t *buffer,
--	uint32_t length);
--
--enum ddc_result dal_dcs_dpcd_write(
--	struct dcs *dcs,
--	uint32_t address,
--	const uint8_t *buffer,
--	uint32_t length);
--
--bool dal_dcs_get_range_limit(
--	struct dcs *dcs,
--	struct display_range_limits *limit);
--
--bool dal_dcs_set_range_limit_override(
--	struct dcs *dcs,
--	struct display_range_limits *limit);
--
--bool dal_dcs_get_user_select_limit(
--	struct dcs *dcs,
--	struct monitor_user_select_limits *limit);
--
--bool dal_dcs_set_user_select_limit(
--	struct dcs *dcs,
--	struct monitor_user_select_limits *limit);
--
--bool dal_dcs_get_dongle_mode_support(
--	struct dcs *dcs,
--	union hdtv_mode_support *hdtv_mode);
--
--bool dal_dcs_get_timing_limits(
--	struct dcs *dcs,
--	struct timing_limits *timing_limits);
--
--bool dal_dcs_get_drr_config(
--	struct dcs *dcs,
--	struct drr_config *config);
--
--bool dal_dcs_force_dp_audio(struct dcs *dcs, bool force_audio_on);
--
--bool dal_dcs_is_dp_audio_forced(struct dcs *dcs);
--
--const struct monitor_patch_info *dal_dcs_get_monitor_patch_info(
--	struct dcs *dcs,
--	enum monitor_patch_type patch_type);
--
--bool dal_dcs_set_monitor_patch_info(
--	struct dcs *dcs,
--	struct monitor_patch_info *patch_info);
--
--union dcs_monitor_patch_flags dal_dcs_get_monitor_patch_flags(struct dcs *dcs);
--
--enum  dcs_packed_pixel_format dal_dcs_get_enabled_packed_pixel_format(
--	struct dcs *dcs);
--
--enum  dcs_packed_pixel_format dal_dcs_get_monitor_packed_pixel_format(
--	struct dcs *dcs);
--
--bool dal_dcs_report_single_selected_timing(struct dcs *dcs);
--
--bool dal_dcs_can_tile_scale(struct dcs *dcs);
--
--void dal_dcs_set_single_selected_timing_restriction(
--	struct dcs *dcs,
--	bool value);
--
--const struct dcs_edid_supported_max_bw *dal_dcs_get_edid_supported_max_bw(
--	struct dcs *dcs);
--
--bool dal_dcs_is_non_continous_frequency(struct dcs *dcs);
--
--struct dcs_stereo_3d_features dal_dcs_get_stereo_3d_features(
--	struct dcs *dcs,
--	enum dc_timing_3d_format format);
--
--union stereo_3d_support dal_dcs_get_stereo_3d_support(struct dcs *dcs);
--
--void dal_dcs_override_stereo_3d_support(
--	struct dcs *dcs,
--	union stereo_3d_support support);
--
--void dal_dcs_set_remote_display_receiver_capabilities(
--	struct dcs *dcs,
--	const struct dal_remote_display_receiver_capability *cap);
--
--void dal_dcs_clear_remote_display_receiver_capabilities(struct dcs *dcs);
--
--bool dal_dcs_get_display_tile_info(
--	struct dcs *dcs,
--	struct dcs_display_tile *display_tile,
--	bool first_display);
--
--bool dal_dcs_get_container_id(struct dcs *dcs,
--	struct dcs_container_id *container_id);
--
--bool dal_dcs_set_container_id(struct dcs *dcs,
--	struct dcs_container_id *container_id);
--
--void dal_dcs_invalidate_container_id(struct dcs *dcs);
--
--union dcs_monitor_patch_flags dal_dcs_get_monitor_patch_flags(struct dcs *dcs);
--
--#endif /* __DAL_DCS_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-index 47ad2ed..21fd17e 100644
---- a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-@@ -25,8 +25,6 @@
- #ifndef __DAL_DDC_SERVICE_TYPES_H__
- #define __DAL_DDC_SERVICE_TYPES_H__
- 
--#include "include/hw_sequencer_types.h"
--
- #define DP_BRANCH_DEVICE_ID_1 0x0010FA
- #define DP_BRANCH_DEVICE_ID_2 0x0022B9
- #define DP_SINK_DEVICE_ID_1 0x4CE000
-diff --git a/drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h b/drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
-deleted file mode 100644
-index 35a5695..0000000
---- a/drivers/gpu/drm/amd/dal/include/default_mode_list_interface.h
-+++ /dev/null
-@@ -1,37 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_DEFAULT_MODE_LIST_INTERFACE_H__
--#define __DAL_DEFAULT_MODE_LIST_INTERFACE_H__
--
--struct default_mode_list;
--
--uint32_t dal_default_mode_list_get_count(const struct default_mode_list *dml);
--
--struct dc_mode_info *dal_default_mode_list_get_mode_info_at_index(
--		const struct default_mode_list *dml,
--		uint32_t index);
--
--#endif /*__DAL_DEFAULT_MODE_LIST_INTERFACE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/display_path_types.h b/drivers/gpu/drm/amd/dal/include/display_path_types.h
-deleted file mode 100644
-index 8aac46d..0000000
---- a/drivers/gpu/drm/amd/dal/include/display_path_types.h
-+++ /dev/null
-@@ -1,132 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_DISPLAY_PATH_TYPES_H__
--#define __DAL_DISPLAY_PATH_TYPES_H__
--
--#include "grph_object_defs.h"
--
--enum {
--	CONTROLLER_HANDLE_INVALID = (uint32_t) (-1)
--};
--
--/*Limit maximum number of cofunctional paths*/
--enum {
--	MAX_COFUNCTIONAL_PATHS = 6
--};
--
--struct pixel_clock_safe_range {
--	uint32_t min_frequency;
--	uint32_t max_frequency;
--};
--
--/**
-- *  ClockSharingGroup
-- *  Enumeration of Clock Source Sharing categories
-- *  Instead using enum we define valid range for clock sharing group values
-- *  This is because potential num of group can be pretty big
-- */
--
--enum clock_sharing_group {
--	/* Default group for display paths that cannot share clock source.
--	 * Display path in such group will aqcuire clock source exclusively*/
--	CLOCK_SHARING_GROUP_EXCLUSIVE = 0,
--	/* DisplayPort paths will have this group if clock sharing
--	 * level is DisplayPortShareable*/
--	CLOCK_SHARING_GROUP_DISPLAY_PORT = 1,
--	/* Mst paths will have this group if clock sharing
--	 * level is DpMstShareable*/
--	CLOCK_SHARING_GROUP_DP_MST = 2,
--	/* Display paths will have this group when
--	 * desired to use alternative DPRef clock source.*/
--	CLOCK_SHARING_GROUP_ALTERNATIVE_DP_REF = 3,
--	/* Start of generic SW sharing groups.*/
--	CLOCK_SHARING_GROUP_GROUP1 = 4,
--	/* Total number of clock sharing groups.*/
--	CLOCK_SHARING_GROUP_MAX = 32,
--};
--/* Should be around maximal number of ever connected displays (since boot :)*/
--/*TEMP*/
--enum goc_link_settings_type {
--	GOC_LINK_SETTINGS_TYPE_PREFERRED = 0,
--	GOC_LINK_SETTINGS_TYPE_REPORTED,
--	GOC_LINK_SETTINGS_TYPE_TRAINED,
--	GOC_LINK_SETTINGS_TYPE_OVERRIDEN_TRAINED,
--	GOC_LINK_SETTINGS_TYPE_MAX
--};
--
--struct dp_audio_test_data {
--
--	struct dp_audio_test_data_flags {
--		uint32_t test_requested:1;
--		uint32_t disable_video:1;
--	} flags;
--
--	/*struct dp_audio_test_data_flags flags;*/
--	uint32_t sampling_rate;
--	uint32_t channel_count;
--	uint32_t pattern_type;
--	uint8_t pattern_period[8];
--};
--
--struct goc_link_service_data {
--	struct dp_audio_test_data dp_audio_test_data;
--};
--/* END-OF-TEMP*/
--
--
--union display_path_properties {
--	struct bit_map {
--		uint32_t ALWAYS_CONNECTED:1;
--		uint32_t HPD_SUPPORTED:1;
--		uint32_t NON_DESTRUCTIVE_POLLING:1;
--		uint32_t FORCE_CONNECT_SUPPORTED:1;
--		uint32_t FAKED_PATH:1;
--		uint32_t IS_BRANCH_DP_MST_PATH:1;
--		uint32_t IS_ROOT_DP_MST_PATH:1;
--		uint32_t IS_DP_AUDIO_SUPPORTED:1;
--		uint32_t IS_HDMI_AUDIO_SUPPORTED:1;
--	} bits;
--
--	uint32_t raw;
--};
--
--enum display_tri_state {
--	DISPLAY_TRI_STATE_UNKNOWN = 0,
--	DISPLAY_TRI_STATE_TRUE,
--	DISPLAY_TRI_STATE_FALSE
--};
--
--enum {
--	MAX_NUM_OF_LINKS_PER_PATH = 2
--};
--enum {
--	SINK_LINK_INDEX = (uint32_t) (-1)
--};
--enum {
--	ASIC_LINK_INDEX = 0
--};
--
--#endif /* __DAL_DISPLAY_PATH_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h b/drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
-deleted file mode 100644
-index a942c77..0000000
---- a/drivers/gpu/drm/amd/dal/include/dpcd_access_service_interface.h
-+++ /dev/null
-@@ -1,65 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifdef __DPCD_ACCESS_SERVICE_INTERFACE_HPP__
--#define __DPCD_ACCESS_SERVICE_INTERFACE_HPP__
--
--/* DDC service transaction error codes
-- * depends on transaction status
-- */
--enum ddc_result {
--	DDCRESULT_UNKNOWN = 0,
--	DDCRESULT_SUCESSFULL,
--	DDCRESULT_FAILEDCHANNELBUSY,
--	DDCRESULT_FAILEDTIMEOUT,
--	DDCRESULT_FAILEDPROTOCOLERROR,
--	DDCRESULT_FAILEDNACK,
--	DDCRESULT_FAILEDINCOMPLETE,
--	DDCRESULT_FAILEDOPERATION,
--	DDCRESULT_FAILEDINVALIDOPERATION,
--	DDCRESULT_FAILEDBUFFEROVERFLOW
--};
--
--enum {
--	MaxNativeAuxTransactionSize = 16
--};
--
--struct display_sink_capability;
--
--/* TO DO: below functions can be moved to ddc_service (think about it)*/
--enum ddc_result dal_ddc_read_dpcd_data(
--		uint32_t address,
--		unsigned char *data,
--		uint32_t size);
--
--enum ddc_result dal_ddc_write_dpcd_data(
--		uint32_t address,
--		const unsigned char *data uint32_t size);
--
--bool dal_aux_query_dp_sink_capability(display_sink_capability *sink_cap);
--bool start_gtc_sync(void);
--bool stop_gtc_sync(void);
--
--#endif /*__DPCD_ACCESS_SERVICE_INTERFACE_HPP__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/gpu_clock_info.h b/drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
-deleted file mode 100644
-index c9b47b2..0000000
---- a/drivers/gpu/drm/amd/dal/include/gpu_clock_info.h
-+++ /dev/null
-@@ -1,43 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_GPU_CLOCK_INFO__
--#define __DAL_GPU_CLOCK_INFO__
--
--#include "include/gpu_interface.h"
--
--/*TODO this structures should be defined*/
--struct gpu_static_clk_info;
--struct gpu_dynamic_clk_info;
--
--bool init_static_clk_info(
--		struct gpu *gpu,
--		struct gpu_static_clk_info *st_clk_info);
--
--bool update_dynamic_clk_info(
--		struct gpu *gpu,
--		struct gpu_dynamic_clk_info *dyn_clk_info);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpu_interface.h b/drivers/gpu/drm/amd/dal/include/gpu_interface.h
-deleted file mode 100644
-index 63262c3..0000000
---- a/drivers/gpu/drm/amd/dal/include/gpu_interface.h
-+++ /dev/null
-@@ -1,91 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_GPU_INTERFACE__
--#define __DAL_GPU_INTERFACE__
--
--#include "include/adapter_service_interface.h"
--#include "include/grph_object_ctrl_defs.h"
--
--enum gpu_clocks_state {
--	GPU_CLOCKS_STATE_INVALID,
--	GPU_CLOCKS_STATE_ULTRA_LOW,
--	GPU_CLOCKS_STATE_LOW,
--	GPU_CLOCKS_STATE_NOMINAL,
--	GPU_CLOCKS_STATE_PERFORMANCE
--};
--
--struct gpu_clock_info {
--	uint32_t min_sclk_khz;
--	uint32_t max_sclk_khz;
--
--	uint32_t min_mclk_khz;
--	uint32_t max_mclk_khz;
--
--	uint32_t min_dclk_khz;
--	uint32_t max_dclk_khz;
--};
--
--struct gpu;
--struct irq_manager;
--
--struct gpu_init_data {
--	struct dc_context *ctx;
--	struct adapter_service *adapter_service;
--	struct irq_manager *irq_manager;
--};
--
--struct gpu *dal_gpu_create(struct gpu_init_data *init_data);
--void dal_gpu_destroy(struct gpu **);
--
--void dal_gpu_power_up(struct gpu *);
--void dal_gpu_power_down(
--		struct gpu *gpu,
--		enum dc_video_power_state power_state);
--void dal_gpu_light_sleep_vbios_wa(struct gpu *gpu, bool enable);
--void dal_gpu_release_hw(struct gpu *gpu);
--
--uint32_t dal_gpu_get_num_of_functional_controllers(const struct gpu *gpu);
--uint32_t dal_gpu_get_max_num_of_primary_controllers(const struct gpu *gpu);
--uint32_t dal_gpu_get_max_num_of_underlay_controllers(const struct gpu *gpu);
--struct controller *dal_gpu_create_controller(
--				struct gpu *gpu,
--				uint32_t index);
--uint32_t dal_gpu_get_num_of_clock_sources(const struct gpu *gpu);
--struct clock_source *dal_gpu_create_clock_source(
--	 struct gpu *gpu,
--	uint32_t index);
--
--/* gpu_clock_interface implementation */
--bool dal_gpu_init_static_clock_info(struct gpu *gpu,
--		struct gpu_clock_info *gpu_clk_info);
--
--bool dal_gpu_update_dynamic_clock_info(struct gpu *gpu,
--		struct gpu_clock_info *gpu_clk_info);
--
--void dal_gpu_get_static_clock_info(struct gpu *gpu,
--		struct gpu_clock_info *gpu_clk_info);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h b/drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
-deleted file mode 100644
-index 10fb8e2..0000000
---- a/drivers/gpu/drm/amd/dal/include/hw_adjustment_set.h
-+++ /dev/null
-@@ -1,50 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_HW_ADJUSTMENT_SET_H__
--#define __DAL_HW_ADJUSTMENT_SET_H__
--
--#include "include/hw_adjustment_types.h"
--
--struct hw_adjustment_gamma_ramp;
--
--struct hw_adjustment_set {
--	struct hw_adjustment_gamma_ramp *gamma_ramp;
--	struct hw_adjustment_deflicker *deflicker_filter;
--	struct hw_adjustment_value *coherent;
--	struct hw_adjustment_value *h_sync;
--	struct hw_adjustment_value *v_sync;
--	struct hw_adjustment_value *composite_sync;
--	struct hw_adjustment_value *backlight;
--	struct hw_adjustment_value *vb_level;
--	struct hw_adjustment_color_control *color_control;
--	union hw_adjustment_bit_depth_reduction *bit_depth;
--};
--/*
--struct hw_adjustment *dal_adjustment_set_get_by_id(
--	struct hw_adjustment_set *adjustment_set,
--	enum hw_adjustment_id id);*/
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h b/drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
-deleted file mode 100644
-index 28ac018..0000000
---- a/drivers/gpu/drm/amd/dal/include/hw_path_mode_set_interface.h
-+++ /dev/null
-@@ -1,48 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_HW_PATH_MODE_SET_INTERFACE_H__
--#define __DAL_HW_PATH_MODE_SET_INTERFACE_H__
--
--struct hw_path_mode;
--struct hw_path_mode_set;
--
--struct hw_path_mode_set *dal_hw_path_mode_set_create(void);
--
--void dal_hw_path_mode_set_destroy(struct hw_path_mode_set **set);
--
--bool dal_hw_path_mode_set_add(
--	struct hw_path_mode_set *set,
--	struct hw_path_mode *path_mode,
--	uint32_t *index);
--
--struct hw_path_mode *dal_hw_path_mode_set_get_path_by_index(
--	const struct hw_path_mode_set *set,
--	uint32_t index);
--
--uint32_t dal_hw_path_mode_set_get_paths_number(
--	const struct hw_path_mode_set *set);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/isr_config_types.h b/drivers/gpu/drm/amd/dal/include/isr_config_types.h
-deleted file mode 100644
-index 2e822f0..0000000
---- a/drivers/gpu/drm/amd/dal/include/isr_config_types.h
-+++ /dev/null
-@@ -1,157 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_ISR_TYPES_H__
--#define __DAL_ISR_TYPES_H__
--
--#include "grph_object_id.h"
--#include "dc_types.h"
--
--struct plane_config;
--enum {
--	/*move to common*/
--	MAX_COFUNC_PATH_COMMON = 6,
--	/*CZ worst case*/
--	MAX_NUM_PLANES = 4
--};
--
--enum plane_type {
--	PLANE_TYPE_GRPH = 0,
--	PLANE_TYPE_VIDEO
--};
--
--struct plane_id {
--	enum plane_type select;
--	enum controller_id controller_id;
--};
--
--union display_plane_mask {
--	struct {
--		uint32_t CLONE_PRIMARY_CONTROLLER_ID_SET:1;
--		uint32_t INTERLEAVED_CONTROLLER_ID_SET:1;
--		uint32_t RESERVED:30;
--	} bits;
--	uint32_t value;
--};
--
--struct display_plane_format {
--    /* always valid */
--	union display_plane_mask mask;
--	/* always valid */
--	uint32_t display_index;
--    /* always valid */
--	enum dc_timing_3d_format format;
--	/* always valid */
--	enum controller_id controller_id;
--	/* valid only if CLONE_PRIMARY_CONTROLLER_ID_SET on */
--	enum controller_id clone_primary_controller_id;
--	/* valid only if stereo interleave mode is on */
--	enum controller_id interleave_controller_id;
--	/* valid only if crtc stereo  is on */
--	uint32_t right_eye_3d_polarity:1;
--};
--
--struct display_plane_set {
--	struct display_plane_format
--		set_mode_formats[MAX_COFUNC_PATH_COMMON];
--	uint32_t reset_mode_index[
--		MAX_COFUNC_PATH_COMMON];
--	uint32_t num_set_mode_formats;
--	uint32_t num_reset_mode_index;
--};
--
--enum layers_setup {
--	LAYERS_SETUP_NOTHING = 0,
--	LAYERS_SETUP_SET,
--	LAYERS_SETUP_FREE
--};
--
--union plane_cfg_internal_flags {
--	struct {
--		uint32_t PLANE_OWNS_CRTC:1;
--		uint32_t RESERVED:31;
--	} bits;
--	uint32_t value;
--};
--
--
--struct plane_cfg_internal {
--	const struct plane_config *config;
--	enum layers_setup setup;
--	union plane_cfg_internal_flags flags;
--};
--
--enum lock_type {
--	LOCK_TYPE_GRPH = 0,
--	LOCK_TYPE_SURF,
--	LOCK_TYPE_SCL,
--	LOCK_TYPE_BLND,
--    /* lock the given pipe with options above */
--	LOCK_TYPE_THIS
--};
--
--enum alpha_mode {
--	ALPHA_MODE_PIXEL = 0,
--	ALPHA_MODE_PIXEL_AND_GLOBAL = 1,
--	ALPHA_MODE_GLOBAL = 2
--};
--
--union alpha_mode_cfg_flag {
--	struct {
--		uint32_t MODE_IS_SET:1;
--		uint32_t MODE_MULTIPLIED_IS_SET:1;
--		uint32_t GLOBAL_ALPHA_IS_SET:1;
--		uint32_t GLOBAL_ALPHA_GAIN_IS_SET:1;
--
--		uint32_t MULTIPLIED_MODE:1;
--		uint32_t GLOBAL_ALPHA:8;
--		/* total 21 bits! */
--		uint32_t GLOBAL_ALPHA_GAIN:8;
--	} bits;
--	uint32_t value;
--};
--
--struct alpha_mode_cfg {
--	union alpha_mode_cfg_flag flags;
--	enum alpha_mode mode;
--};
--
--union pending_cfg_changes {
--	struct {
--		uint32_t SCL_UNLOCK_REQUIRED:1;
--		uint32_t BLND_UNLOCK_REQUIRED:1;
--		uint32_t INPUT_CSC_SWITCH_REQUIRED:1;
--		uint32_t OUTPUT_CSC_SWITCH_REQUIRED:1;
--	} bits;
--	uint32_t value;
--};
--
--struct pending_plane_changes {
--	union pending_cfg_changes changes;
--	struct plane_id id;
--};
--
--
--#endif /* __DAL_ISR_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/mode_manager_types.h b/drivers/gpu/drm/amd/dal/include/mode_manager_types.h
-deleted file mode 100644
-index 576b21f..0000000
---- a/drivers/gpu/drm/amd/dal/include/mode_manager_types.h
-+++ /dev/null
-@@ -1,71 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_MODE_MANAGER_TYPES_H__
--#define __DAL_MODE_MANAGER_TYPES_H__
--
--#include "bit_set.h"
--#include "dc_types.h"
--
--static inline void stereo_3d_view_reset(struct stereo_3d_view *stereo_3d_view)
--{
--	stereo_3d_view->view_3d_format = VIEW_3D_FORMAT_NONE;
--	stereo_3d_view->flags.raw = 0;
--}
--
--bool dal_refresh_rate_is_equal(
--		const struct refresh_rate *lhs,
--		const struct refresh_rate *rhs);
--
--bool dal_refresh_rate_less_than(
--		const struct refresh_rate *lhs,
--		const struct refresh_rate *rhs);
--
--void refresh_rate_from_mode_info(
--		struct refresh_rate *,
--		const struct dc_mode_info *);
--bool dal_solution_less_than(const void *lhs, const void *rhs);
--bool dal_view_is_equal(const struct view *lhs, const struct view *rhs);
--
--struct pixel_format_list {
--	uint32_t set;
--	struct bit_set_iterator_32 iter;
--};
--
--void dal_pixel_format_list_reset_iterator(struct pixel_format_list *pfl);
--void dal_pixel_format_list_zero_iterator(struct pixel_format_list *pfl);
--
--void dal_pixel_format_list_construct(
--		struct pixel_format_list *pfl,
--		uint32_t mask);
--
--uint32_t dal_pixel_format_list_next(struct pixel_format_list *pfl);
--
--uint32_t dal_pixel_format_list_get_count(
--		const struct pixel_format_list *pfl);
--enum pixel_format dal_pixel_format_list_get_pixel_format(
--		const struct pixel_format_list *pfl);
--
--#endif /* __DAL_MODE_MANAGER_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/mode_query_interface.h b/drivers/gpu/drm/amd/dal/include/mode_query_interface.h
-deleted file mode 100644
-index 1d20e73..0000000
---- a/drivers/gpu/drm/amd/dal/include/mode_query_interface.h
-+++ /dev/null
-@@ -1,93 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_MODE_QUERY_INTERFACE_H__
--#define __DAL_MODE_QUERY_INTERFACE_H__
--
--#include "include/set_mode_types.h"
--#include "include/mode_manager_types.h"
--
--enum query_option {
--	QUERY_OPTION_ALLOW_PAN,
--	QUERY_OPTION_ALLOW_PAN_NO_VIEW_RESTRICTION,
--	QUERY_OPTION_PAN_ON_LIMITED_RESOLUTION_DISP_PATH,
--	QUERY_OPTION_NO_PAN,
--	QUERY_OPTION_NO_PAN_NO_DISPLAY_VIEW_RESTRICTION,
--	QUERY_OPTION_3D_LIMITED_CANDIDATES,
--	QUERY_OPTION_TILED_DISPLAY_PREFERRED,
--	QUERY_OPTION_MAX,
--};
--
--struct topology {
--	uint32_t disp_path_num;
--	uint32_t display_index[MAX_COFUNC_PATH];
--};
--
--struct path_mode;
--struct mode_query;
--
--bool dal_mode_query_pin_path_mode(
--		struct mode_query *mq,
--		const struct path_mode *path_mode);
--
--const struct render_mode *dal_mode_query_get_current_render_mode(
--		const struct mode_query *mq);
--
--const struct stereo_3d_view *dal_mode_query_get_current_3d_view(
--		const struct mode_query *mq);
--
--const struct refresh_rate *dal_mode_query_get_current_refresh_rate(
--		const struct mode_query *mq);
--
--const struct path_mode_set *dal_mode_query_get_current_path_mode_set(
--		const struct mode_query *mq);
--
--bool dal_mode_query_select_first(struct mode_query *mq);
--bool dal_mode_query_select_next_render_mode(struct mode_query *mq);
--
--bool dal_mode_query_select_render_mode(struct mode_query *mq,
--		const struct render_mode *render_mode);
--
--bool dal_mode_query_select_next_view_3d_format(struct mode_query *mq);
--bool dal_mode_query_select_view_3d_format(
--		struct mode_query *mq,
--		enum view_3d_format format);
--
--bool dal_mode_query_select_refresh_rate(struct mode_query *mq,
--		const struct refresh_rate *refresh_rate);
--
--bool dal_mode_query_select_refresh_rate_ex(struct mode_query *mq,
--		uint32_t refresh_rate,
--		bool interlaced);
--
--bool dal_mode_query_select_next_scaling(struct mode_query *mq);
--
--bool dal_mode_query_select_next_refresh_rate(struct mode_query *mq);
--
--bool dal_mode_query_base_select_next_scaling(struct mode_query *mq);
--
--void dal_mode_query_destroy(struct mode_query **mq);
--
--#endif /* __DAL_MODE_QUERY_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h b/drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
-deleted file mode 100644
-index a558fec..0000000
---- a/drivers/gpu/drm/amd/dal/include/mode_timing_list_interface.h
-+++ /dev/null
-@@ -1,51 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_MODE_TIMING_LIST_INTERFACE_H__
--#define __DAL_MODE_TIMING_LIST_INTERFACE_H__
--
--
--struct mode_timing_filter;
--struct mode_timing_list;
--
--struct mode_timing_list *dal_mode_timing_list_create(
--		struct dal_context *ctx,
--		uint32_t display_index,
--		const struct mode_timing_filter *mt_filter);
--
--void dal_mode_timing_list_destroy(struct mode_timing_list **mtl);
--
--
--uint32_t dal_mode_timing_list_get_count(
--		const struct mode_timing_list *mode_timing_list);
--
--const struct dc_mode_timing *dal_mode_timing_list_get_timing_at_index(
--		const struct mode_timing_list *mode_timing_list,
--		uint32_t index);
--
--const struct dc_mode_timing *dal_mode_timing_list_get_single_selected_mode_timing(
--		const struct mode_timing_list *mode_timing_list);
--
--#endif /*__DAL_MODE_TIMING_LIST_INTERFACE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/overlay_interface.h b/drivers/gpu/drm/amd/dal/include/overlay_interface.h
-deleted file mode 100644
-index c33bd73..0000000
---- a/drivers/gpu/drm/amd/dal/include/overlay_interface.h
-+++ /dev/null
-@@ -1,137 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_OVERLAY_INTERFACE_H__
--#define __DAL_OVERLAY_INTERFACE_H__
--
--#include "include/overlay_types.h"
--#include "include/display_service_types.h"
--
--struct ds_overlay;
--struct path_mode_set;
--struct path_mode;
--struct view;
--
--bool dal_ds_overlay_is_active(
--	struct ds_overlay *ovl,
--	uint32_t display_index);
--
--uint32_t dal_ds_overlay_get_controller_handle(
--	struct ds_overlay *ovl,
--	uint32_t display_index);
--
--enum ds_return dal_ds_overlay_alloc(
--	struct ds_overlay *ovl,
--	struct path_mode_set *path_mode_set,
--	uint32_t display_index,
--	struct view *view,
--	struct overlay_data *data);
--
--enum ds_return dal_ds_overlay_validate(
--	struct ds_overlay *ovl,
--	struct path_mode_set *path_mode_set,
--	uint32_t display_index,
--	struct view *view,
--	struct overlay_data *data);
--
--enum ds_return dal_ds_overlay_free(
--	struct ds_overlay *ovl,
--	struct path_mode_set *path_mode_set,
--	uint32_t display_index);
--
--enum ds_return dal_ds_overlay_get_info(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	enum overlay_color_space *color_space,
--	enum overlay_backend_bpp *backend_bpp,
--	enum overlay_alloc_option *alloc_option,
--	enum overlay_format *surface_format);
--
--enum ds_return dal_ds_overlay_set_otm(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	const struct path_mode *current_path_mode);
--
--enum ds_return dal_ds_overlay_reset_otm(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	struct path_mode **saved_path_mode);
--
--/**is in overlay theater mode*/
--bool dal_ds_overlay_is_in_otm(
--	struct ds_overlay *ovl,
--	uint32_t display_index);
--
--void dal_ds_overlay_set_matrix(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	const struct overlay_color_matrix *matrix);
--
--void dal_ds_overlay_reset_matrix(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	enum overlay_csc_matrix_type type);
--
--const struct overlay_color_matrix *dal_ds_overlay_get_matrix(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	enum overlay_csc_matrix_type type);
--
--bool dal_ds_overlay_set_color_space(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	enum overlay_color_space space);
--
--bool dal_ds_overlay_get_display_pixel_encoding(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	enum display_pixel_encoding *pixel_encoding);
--
--bool dal_ds_overlay_set_display_pixel_encoding(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	enum display_pixel_encoding pixel_encoding);
--
--bool dal_ds_overlay_reset_display_pixel_encoding(
--	struct ds_overlay *ovl,
--	uint32_t display_index);
--
--/*After Set Overlay Theatre Mode (OTM) on a display path,
-- *  saving the passed setting of Gpu scaling option for later restore*/
--enum ds_return dal_ds_overlay_save_gpu_scaling_before_otm(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	int32_t timing_sel_before_otm);
--
--/* After reset Overlay Theatre Mode (OTM) on a display path,
-- * returning the previous Gpu scaling option by SetOverlayTheatreMode*/
--enum ds_return dal_ds_overlay_get_gpu_scaling_before_otm(
--	struct ds_overlay *ovl,
--	uint32_t display_index,
--	int32_t *timing_sel_before_otm);
--
--uint32_t dal_ds_overlay_get_num_of_allowed(struct ds_overlay *ovl);
--
--#endif /* __DAL_OVERLAY_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/overlay_types.h b/drivers/gpu/drm/amd/dal/include/overlay_types.h
-deleted file mode 100644
-index c001edf..0000000
---- a/drivers/gpu/drm/amd/dal/include/overlay_types.h
-+++ /dev/null
-@@ -1,164 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_OVERLAY_TYPES_H__
--#define __DAL_OVERLAY_TYPES_H__
--
--enum overlay_color_space {
--	OVERLAY_COLOR_SPACE_UNINITIALIZED,
--	OVERLAY_COLOR_SPACE_RGB, /* the first*/
--	OVERLAY_COLOR_SPACE_BT601,
--	OVERLAY_COLOR_SPACE_BT709, /* the last*/
--	OVERLAY_COLOR_SPACE_INVALID,
--
--	/* flag the first and last*/
--	OVERLAY_COLOR_SPACE_BEGIN = OVERLAY_COLOR_SPACE_RGB,
--	OVERLAY_COLOR_SPACE_END = OVERLAY_COLOR_SPACE_BT709,
--};
--
--enum overlay_backend_bpp {
--	OVERLAY_BACKENDBPP_UNINITIALIZED,
--
--	OVERLAY_BACKEND_BPP_32_FULL_BANDWIDTH,/* the first*/
--	OVERLAY_BACKEND_BPP_16_FULL_BANDWIDTH,
--	OVERLAY_BACKEND_BPP_32_HALF_BANDWIDTH,/* the last*/
--
--	OVERLAY_BACKEND_BPP_INVALID,
--
--	/* flag the first and last*/
--	OVERLAY_BACKEND_BPP_BEGIN = OVERLAY_BACKEND_BPP_32_FULL_BANDWIDTH,
--	OVERLAY_BACKEND_BPP_END = OVERLAY_BACKEND_BPP_32_HALF_BANDWIDTH,
--};
--
--enum overlay_alloc_option {
--	OVERLAY_ALLOC_OPTION_UNINITIALIZED,
--
--	OVERLAY_ALLOC_OPTION_APPLY_OVERLAY_CSC, /* the first*/
--	OVERLAY_ALLOC_OPTION_APPLY_DESKTOP_CSC, /* the last*/
--
--	OVERLAY_ALLOC_OPTION_INVALID,
--
--	/* flag the first and last*/
--	OVERLAY_ALLOC_OPTION_BEGIN = OVERLAY_ALLOC_OPTION_APPLY_OVERLAY_CSC,
--	OVERLAY_ALLOC_OPTION_END = OVERLAY_ALLOC_OPTION_APPLY_DESKTOP_CSC,
--};
--
--enum overlay_format {
--	OVERLAY_FORMAT_UNINITIALIZED,
--	OVERLAY_FORMAT_YUY2,
--	OVERLAY_FORMAT_UYVY,
--	OVERLAY_FORMAT_RGB565,
--	OVERLAY_FORMAT_RGB555,
--	OVERLAY_FORMAT_RGB32,
--	OVERLAY_FORMAT_YUV444,
--	OVERLAY_FORMAT_RGB32_2101010,
--
--	OVERLAY_FORMAT_INVALID,
--
--	/* flag the first and last*/
--	OVERLAY_FORMAT_BEGIN = OVERLAY_FORMAT_YUY2,
--	OVERLAY_FORMAT_END = OVERLAY_FORMAT_RGB32_2101010,
--};
--
--enum display_pixel_encoding {
--	DISPLAY_PIXEL_ENCODING_UNDEFINED = 0,
--	DISPLAY_PIXEL_ENCODING_RGB,
--	DISPLAY_PIXEL_ENCODING_YCBCR422,
--	DISPLAY_PIXEL_ENCODING_YCBCR444
--};
--
--union overlay_data_status {
--	uint32_t u32all;
--	struct {
--		uint32_t COLOR_SPACE_SET:1;
--		uint32_t BACKEND_BPP:1;
--		uint32_t ALLOC_OPTION:1;
--		uint32_t SURFACE_FORMAT:1;
--		uint32_t PIXEL_ENCODING:1;
--		uint32_t reserved:27;
--
--	} bits;
--};
--
--struct overlay_data {
--	enum overlay_color_space color_space;
--	enum overlay_backend_bpp backend_bpp;
--	enum overlay_alloc_option alloc_option;
--	enum overlay_format surface_format;
--};
--
--enum overlay_csc_matrix_type {
--	OVERLAY_CSC_MATRIX_NOTDEFINED = 0,
--	OVERLAY_CSC_MATRIX_BT709,
--	OVERLAY_CSC_MATRIX_BT601,
--	OVERLAY_CSC_MATRIX_SMPTE240,
--	OVERLAY_CSC_MATRIX_SRGB,
--};
--
--#define DEFAULT_APP_MATRIX_DIVIDER 10000
--#define MAX_OVL_MATRIX_COUNTS 2
--#define OVL_BT709 0
--#define OVL_BT601 1
--
--#define OVL_MATRIX_ITEM 9
--#define OVL_MATRIX_OFFSET_ITEM 3
--
--struct overlay_color_matrix {
--	enum overlay_csc_matrix_type csc_matrix;
--/*3*3 Gamut Matrix (value is the real value * M_GAMUT_PRECISION_MULTIPLIER)*/
--	int32_t matrix_settings[OVL_MATRIX_ITEM];
--	int32_t offsets[OVL_MATRIX_OFFSET_ITEM];
--};
--
--enum setup_adjustment_ovl_value_type {
--	SETUP_ADJUSTMENT_MIN,
--	SETUP_ADJUSTMENT_MAX,
--	SETUP_ADJUSTMENT_DEF,
--	SETUP_ADJUSTMENT_CURRENT,
--	SETUP_ADJUSTMENT_BUNDLE_MIN,
--	SETUP_ADJUSTMENT_BUNDLE_MAX,
--	SETUP_ADJUSTMENT_BUNDLE_DEF,
--	SETUP_ADJUSTMENT_BUNDLE_CURRENT
--};
--
--struct overlay_parameter {
--	union {
--		uint32_t u32all;
--		struct {
--			uint32_t VALID_OVL_COLOR_SPACE:1;
--			uint32_t VALID_VALUE_TYPE:1;
--			uint32_t VALID_OVL_SURFACE_FORMAT:1;
--			uint32_t CONFIG_IS_CHANGED:1;
--			uint32_t reserved:28;
--
--		} bits;
--	};
--	/*currently colorSpace here packed, continue this list*/
--	enum overlay_color_space color_space;
--	enum setup_adjustment_ovl_value_type value_type;
--	enum overlay_format surface_format;
--};
--
--#endif /* OVERLAY_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h b/drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
-deleted file mode 100644
-index a277010..0000000
---- a/drivers/gpu/drm/amd/dal/include/path_mode_set_interface.h
-+++ /dev/null
-@@ -1,107 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_PATH_MODE_SET_INTERFACE_H__
--#define __DAL_PATH_MODE_SET_INTERFACE_H__
--
--/* Set of path modes */
--struct path_mode_set {
--	union control_flags {
--		struct {
--			uint32_t KEEP_DISPLAY_POWERED_OFF:1;
--			uint32_t UNBLANCK_SOURCE_AFTER_SETMODE:1;
--			uint32_t NODE_FAULT_UNDERSCAN:1;
--		} bits;
--
--		uint32_t all;
--	} control_flags;
--
--	struct path_mode path_mode_set[MAX_COFUNC_PATH];
--	uint32_t count;
--};
--
--/* Create path mode set */
--struct path_mode_set *dal_pms_create(void);
--
--/* Deallocate path mode set */
--void dal_pms_destroy(
--	struct path_mode_set **pms);
--
--/* Create a copy of given path mode set */
--struct path_mode_set *dal_pms_copy(
--	const struct path_mode_set *copy);
--
--/* Constructor for path mode set */
--bool dal_pms_construct(
--	struct path_mode_set *set);
--
--/* Add a path mode into the set */
--bool dal_pms_add_path_mode(
--	struct path_mode_set *set,
--	const struct path_mode *path_mode);
--
--/* Get number of path modes in the set */
--uint32_t dal_pms_get_path_mode_num(
--	const struct path_mode_set *set);
--
--/* Return the path mode at the index */
--const struct path_mode *dal_pms_get_path_mode_at_index(
--	const struct path_mode_set *set,
--	uint32_t index);
--
--/* Return the path mode for the given display index */
--const struct path_mode *dal_pms_get_path_mode_for_display_index(
--	const struct path_mode_set *set,
--	uint32_t index);
--
--/* Remove the path mode at index */
--bool dal_pms_remove_path_mode_at_index(
--	struct path_mode_set *set,
--	uint32_t index);
--
--/* Remove the given path mode if it is found in the set */
--bool dal_pms_remove_path_mode(
--	struct path_mode_set *set,
--	struct path_mode *mode);
--
--/* Add control flag to keep display powered off */
--void dal_pms_keep_display_powered_off(
--	struct path_mode_set *set,
--	bool keep);
--
--/* Return control flag if display needs to be kept powered off */
--bool dal_pms_is_display_power_off_required(
--	const struct path_mode_set *set);
--
--/* Add control flag to not use default underscan*/
--void dal_pms_fallback_remove_default_underscan(
--	struct path_mode_set *set,
--	bool lean);
--
--/* Return control flag if default underscan is not used */
--bool dal_pms_is_fallback_no_default_underscan_enabled(
--	struct path_mode_set *set);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h b/drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
-deleted file mode 100644
-index e4f52c4..0000000
---- a/drivers/gpu/drm/amd/dal/include/set_mode_params_interface.h
-+++ /dev/null
-@@ -1,101 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_SET_MODE_PARAMS_INTERFACE_H__
--#define __DAL_SET_MODE_PARAMS_INTERFACE_H__
--
--struct set_mode_params;
--
--struct set_mode_params_init_data {
--	struct hw_sequencer *hws;
--	struct dal_context *ctx;
--	struct topology_mgr *tm;
--};
--
--struct view_stereo_3d_support dal_set_mode_params_get_stereo_3d_support(
--	struct set_mode_params *smp,
--	uint32_t display_index,
--	enum dc_timing_3d_format);
--
--bool dal_set_mode_params_update_view_on_path(
--	struct set_mode_params *smp,
--	uint32_t display_index,
--	const struct view *vw);
--
--bool dal_set_mode_params_update_mode_timing_on_path(
--	struct set_mode_params *smp,
--	uint32_t display_index,
--	const struct dc_mode_timing *mode_timing,
--	enum view_3d_format format);
--
--bool dal_set_mode_params_update_scaling_on_path(
--	struct set_mode_params *smp,
--	uint32_t display_index,
--	enum scaling_transformation st);
--
--bool dal_set_mode_params_update_pixel_format_on_path(
--	struct set_mode_params *smp,
--	uint32_t display_index,
--	enum pixel_format pf);
--
--bool dal_set_mode_params_update_tiling_mode_on_path(
--		struct set_mode_params *smp,
--		uint32_t display_index,
--		enum tiling_mode tm);
--
--bool dal_set_mode_params_is_path_mode_set_supported(
--	struct set_mode_params *smp);
--
--bool dal_set_mode_params_is_path_mode_set_guaranteed(
--	struct set_mode_params *smp);
--
--bool dal_set_mode_params_report_single_selected_timing(
--	struct set_mode_params *smp,
--	uint32_t display_index);
--
--bool dal_set_mode_params_report_ce_mode_only(
--	struct set_mode_params *smp,
--	uint32_t display_index);
--
--struct set_mode_params *dal_set_mode_params_create(
--		struct set_mode_params_init_data *init_data);
--
--bool dal_set_mode_params_init_with_topology(
--		struct set_mode_params *smp,
--		const uint32_t display_indicies[],
--		uint32_t idx_num);
--
--bool dal_set_mode_params_is_multiple_pixel_encoding_supported(
--	struct set_mode_params *smp,
--	uint32_t display_index);
--
--enum dc_pixel_encoding dal_set_mode_params_get_default_pixel_format_preference(
--	struct set_mode_params *smp,
--	unsigned int display_index);
--
--void dal_set_mode_params_destroy(
--		struct set_mode_params **set_mode_params);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h b/drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
-deleted file mode 100644
-index 16e3521..0000000
---- a/drivers/gpu/drm/amd/dal/include/timing_list_query_interface.h
-+++ /dev/null
-@@ -1,69 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_TIMING_LIST_QUERY_INTERFACE_H__
--#define __DAL_TIMING_LIST_QUERY_INTERFACE_H__
--
--/* External dependencies */
--#include "include/dcs_interface.h"
--
--/* Forward declarations */
--struct dal;
--struct dal_timing_list_query;
--
--enum timing_support_level {
--	TIMING_SUPPORT_LEVEL_UNDEFINED,
--	/* assumed to be guaranteed supported by display,
--	* usually one timing is marked as native */
--	TIMING_SUPPORT_LEVEL_NATIVE,
--	/* user wants DAL to drive this timing as if Display supports it */
--	TIMING_SUPPORT_LEVEL_GUARANTEED,
--	/* user wants DAL to drive this timing even if display
--	* may not support it */
--	TIMING_SUPPORT_LEVEL_NOT_GUARANTEED
--};
--
--struct timing_list_query_init_data {
--	struct dal *dal; /* an instance of DAL */
--	struct timing_service *timing_srv;
--	struct dcs *dcs;
--	uint32_t display_index;
--};
--
--struct dal_timing_list_query *dal_timing_list_query_create(
--		struct timing_list_query_init_data *init_data);
--
--void dal_timing_list_query_destroy(struct dal_timing_list_query **tlsq);
--
--/* Get count of mode timings in the list. */
--uint32_t dal_timing_list_query_get_mode_timing_count(
--	const struct dal_timing_list_query *tlsq);
--
--const struct dc_mode_timing *dal_timing_list_query_get_mode_timing_at_index(
--	const struct dal_timing_list_query *tlsq,
--	uint32_t index);
--
--
--#endif /* __DAL_TIMING_LIST_QUERY_INTERFACE_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0642-drm-amd-dal-DP-MST-Detection.patch b/common/recipes-kernel/linux/files/0642-drm-amd-dal-DP-MST-Detection.patch
deleted file mode 100644
index ccc717d3..00000000
--- a/common/recipes-kernel/linux/files/0642-drm-amd-dal-DP-MST-Detection.patch
+++ /dev/null
@@ -1,171 +0,0 @@
-From a3148a748fde1246f26b494675147e2793b890f1 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Fri, 18 Dec 2015 11:52:24 -0500
-Subject: [PATCH 0642/1110] drm/amd/dal: DP MST Detection
-
-MSTManager allows DP MST to be detected.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c |  2 --
- drivers/gpu/drm/amd/dal/dc/core/dc.c                  |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c             | 12 ++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c        |  2 --
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c           |  2 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                       |  1 +
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h               |  2 --
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h           |  2 --
- 8 files changed, 7 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index ddc40c9..0a05774 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -499,7 +499,6 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 
- bool dc_helper_dp_read_dpcd(
- 		struct dc_context *ctx,
--		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		uint8_t *data,
-@@ -521,7 +520,6 @@ bool dc_helper_dp_read_dpcd(
- 
- bool dc_helper_dp_write_dpcd(
- 		struct dc_context *ctx,
--		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		const uint8_t *data,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 941d167..2c9a404 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -365,7 +365,6 @@ static void destruct(struct dc *dc)
- 	dc_service_free(dc->ctx, dc->links);
- 	dc->hwss.destruct_resource_pool(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
--	dc_service_free(dc->ctx, dc->ctx);
- }
- 
- /*******************************************************************************
-@@ -403,6 +402,7 @@ void dc_destroy(struct dc **dc)
- {
- 	destruct(*dc);
- 	dc_service_free((*dc)->ctx, *dc);
-+	dc_service_free((*dc)->ctx, (*dc)->ctx);
- 	*dc = NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index d4b1085..5516ec7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -647,13 +647,9 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		link_disconnect_all_sinks(link);
- 	}
- 
--	if (signal == SIGNAL_TYPE_NONE) {
--		LINK_INFO("link=%d is now Disconnected.\n",
--				link->link_index);
--	} else {
--		LINK_INFO("link=%d is now Connected. Sink ptr=%p Signal=%d\n",
--				link->link_index, &sink->public, signal);
--	}
-+	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
-+		link->public.link_index, &sink->public,
-+		(signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected"));
- 
- 	return;
- }
-@@ -675,7 +671,7 @@ static bool construct(
- 	link->adapter_srv = as;
- 	link->connector_index = init_params->connector_index;
- 	link->ctx = dc_ctx;
--	link->link_index = init_params->link_index;
-+	link->public.link_index = init_params->link_index;
- 
- 	link->link_id = dal_adapter_service_get_connector_obj_id(
- 			as,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 91aec82..727c812 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -21,7 +21,6 @@ enum dc_status core_link_read_dpcd(
- 	uint32_t size)
- {
- 	if (!dc_helper_dp_read_dpcd(link->ctx,
--			link->link_index,
- 			&link->public,
- 			address, data, size))
- 			return DC_ERROR_UNEXPECTED;
-@@ -36,7 +35,6 @@ enum dc_status core_link_write_dpcd(
- 	uint32_t size)
- {
- 	if (!dc_helper_dp_write_dpcd(link->ctx,
--			link->link_index,
- 			&link->public,
- 			address, data, size))
- 				return DC_ERROR_UNEXPECTED;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 82cdae1..3a1f605 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -400,7 +400,7 @@ uint8_t dc_target_get_link_index(const struct dc_target *dc_target)
- 	const struct core_sink *sink =
- 		DC_SINK_TO_CORE(target->public.streams[0]->sink);
- 
--	return sink->link->link_index;
-+	return sink->link->public.link_index;
- }
- 
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index c9cdd9c..007fdc4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -273,6 +273,7 @@ void dc_update_stream(const struct dc_stream *dc_stream,
- struct dc_link {
- 	const struct dc_sink *sink[MAX_SINKS_PER_LINK];
- 	unsigned int sink_count;
-+	unsigned int link_index;
- 	enum dc_connection_type type;
- 	enum signal_type connector_signal;
- 	enum dc_irq_source irq_source_hpd;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index fe76833..d96e907 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -77,7 +77,6 @@ void dc_helpers_dp_mst_stop_top_mgr(
-  */
- bool dc_helper_dp_read_dpcd(
- 		struct dc_context *ctx,
--		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		uint8_t *data,
-@@ -88,7 +87,6 @@ bool dc_helper_dp_read_dpcd(
-  */
- bool dc_helper_dp_write_dpcd(
- 		struct dc_context *ctx,
--		uint8_t link_index,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		const uint8_t *data,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index b35ec1a..194b3e0 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -203,8 +203,6 @@ struct core_link {
- 	struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/
- 
- 	uint8_t connector_index; /* this will be mapped to the HPD pins */
--	uint8_t link_index; /* this is mapped to DAL display_index
--				TODO: #flip remove it as soon as possible. */
- 
- 	struct adapter_service *adapter_srv;
- 	struct connector *connector;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0643-drm-amd-dal-destroy-mst-connector-after-reset-mode.patch b/common/recipes-kernel/linux/files/0643-drm-amd-dal-destroy-mst-connector-after-reset-mode.patch
deleted file mode 100644
index 1bc54391..00000000
--- a/common/recipes-kernel/linux/files/0643-drm-amd-dal-destroy-mst-connector-after-reset-mode.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From a5363a8957efa2eb9f0feafe395033588b43e3c4 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 18 Dec 2015 18:46:32 +0800
-Subject: [PATCH 0643/1110] drm/amd/dal: destroy mst connector after reset mode
-
-MST semaphore lock/unlock done after actual dc_commit_target is
-done. Need to make sure MST connectors alive till that time
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index e142508..33fe1a4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2244,8 +2244,6 @@ int amdgpu_dm_atomic_commit(
- 		} /* switch() */
- 	} /* for_each_crtc_in_state() */
- 
--	update_connector_sem_state(state);
--
- 	commit_targets_count = 0;
- 
- 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-@@ -2261,6 +2259,8 @@ int amdgpu_dm_atomic_commit(
- 	/* DC is optimized not to do anything if 'targets' didn't change. */
- 	dc_commit_targets(dm->dc, commit_targets, commit_targets_count);
- 
-+	update_connector_sem_state(state);
-+
- 	/* update planes when needed */
- 	for_each_plane_in_state(state, plane, old_plane_state, i) {
- 		struct drm_plane_state *plane_state = plane->state;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0644-drm-amd-dal-Refactor-link-encoder-interface.patch b/common/recipes-kernel/linux/files/0644-drm-amd-dal-Refactor-link-encoder-interface.patch
deleted file mode 100644
index 158510f1..00000000
--- a/common/recipes-kernel/linux/files/0644-drm-amd-dal-Refactor-link-encoder-interface.patch
+++ /dev/null
@@ -1,483 +0,0 @@
-From 23c6d8e0bf49db5d89c2a6e6030979d7f9a229da Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Mon, 21 Dec 2015 13:46:25 -0500
-Subject: [PATCH 0644/1110] drm/amd/dal: Refactor link encoder interface.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  20 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  18 +--
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   9 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 159 +++++++++++++++++----
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  41 ++++--
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  42 ++++--
- 7 files changed, 222 insertions(+), 69 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 2c9a404..df243c2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -166,7 +166,7 @@ static void init_hw(struct dc *dc)
- 		 * required signal (which may be different from the
- 		 * default signal on connector). */
- 		struct core_link *link = dc->links[i];
--		dc->hwss.encoder_power_up(link->link_enc);
-+		dc->hwss.encoder_hw_init(link->link_enc);
- 	}
- 
- 	for(i = 0; i < dc->res_pool.controller_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 5516ec7..9b8f536 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1013,15 +1013,19 @@ static void enable_link_hdmi(struct core_stream *stream)
- 	stream->sink->link->cur_link_settings.lane_count =
- 		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- 					? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+	if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-+		link->ctx->dc->hwss.encoder_enable_dual_link_tmds_output(
-+				stream->sink->link->link_enc,
-+				dal_clock_source_get_id(stream->clock_source),
-+				stream->public.timing.display_color_depth,
-+				stream->public.timing.pix_clk_khz);
-+	else
-+		link->ctx->dc->hwss.encoder_enable_tmds_output(
-+				stream->sink->link->link_enc,
-+				dal_clock_source_get_id(stream->clock_source),
-+				stream->public.timing.display_color_depth,
-+				stream->public.timing.pix_clk_khz);
- 
--	link->ctx->dc->hwss.encoder_enable_output(
--			stream->sink->link->link_enc,
--			&stream->sink->link->cur_link_settings,
--			stream->stream_enc->id,
--			dal_clock_source_get_id(stream->clock_source),
--			stream->signal,
--			stream->public.timing.display_color_depth,
--			stream->public.timing.pix_clk_khz);
- 
- 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 		dal_ddc_service_read_scdc_data(link->ddc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 727c812..a1617bc 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -58,14 +58,16 @@ void dp_enable_link_phy(
- 	enum engine_id engine,
- 	const struct link_settings *link_settings)
- {
--	link->dc->hwss.encoder_enable_output(
--					link->link_enc,
--					link_settings,
--					engine,
--					CLOCK_SOURCE_ID_EXTERNAL,
--					signal,
--					COLOR_DEPTH_UNDEFINED,
--					0);
-+	if (signal == SIGNAL_TYPE_DISPLAY_PORT)
-+		link->dc->hwss.encoder_enable_dp_output(
-+						link->link_enc,
-+						link_settings,
-+						CLOCK_SOURCE_ID_EXTERNAL);
-+	else
-+		link->dc->hwss.encoder_enable_dp_mst_output(
-+						link->link_enc,
-+						link_settings,
-+						CLOCK_SOURCE_ID_EXTERNAL);
- 
- 	dp_receiver_power_ctrl(link, true);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index d944781..6a59fc3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1723,8 +1723,13 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.disable_vga = dce110_timing_generator_disable_vga,
- 	.encoder_create = dce110_link_encoder_create,
- 	.encoder_destroy = dce110_link_encoder_destroy,
--	.encoder_power_up = dce110_link_encoder_power_up,
--	.encoder_enable_output = dce110_link_encoder_enable_output,
-+	.encoder_hw_init = dce110_link_encoder_hw_init,
-+	.encoder_enable_tmds_output = dce110_link_encoder_enable_tmds_output,
-+	.encoder_enable_dual_link_tmds_output =
-+			dce110_link_encoder_enable_dual_link_tmds_output,
-+	.encoder_enable_dp_output = dce110_link_encoder_enable_dp_output,
-+	.encoder_enable_dp_mst_output =
-+			dce110_link_encoder_enable_dp_mst_output,
- 	.encoder_disable_output = dce110_link_encoder_disable_output,
- 	.encoder_set_dp_phy_pattern = dce110_link_encoder_set_dp_phy_pattern,
- 	.encoder_dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index d71efa9..08711c2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -33,7 +33,6 @@
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
- 
--#define DELAY_AFTER_PIXEL_FORMAT_CHANGE 0 /* ms */
- /* For current ASICs pixel clock - 600MHz */
- #define MAX_ENCODER_CLK 600000
- 
-@@ -605,7 +604,6 @@ static uint8_t get_frontend_source(
- 
- static void configure_encoder(
- 	struct dce110_link_encoder *enc110,
--	enum engine_id engine,
- 	const struct link_settings *link_settings)
- {
- 	struct dc_context *ctx = enc110->base.ctx;
-@@ -1285,7 +1283,7 @@ bool dce110_link_encoder_validate_output_with_stream(
- 	return is_valid;
- }
- 
--void dce110_link_encoder_power_up(
-+void dce110_link_encoder_hw_init(
- 	struct link_encoder *enc)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-@@ -1383,17 +1381,10 @@ void dce110_link_encoder_setup(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--/*
-- * @brief
-- * Configure digital transmitter and enable both encoder and transmitter
-- * Actual output will be available after calling unblank()
-- */
--void dce110_link_encoder_enable_output(
-+/* TODO: still need depth or just pass in adjusted pixel clock? */
-+void dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum engine_id engine,
- 	enum clock_source_id clock_source,
--	enum signal_type signal,
- 	enum dc_color_depth color_depth,
- 	uint32_t pixel_clock)
- {
-@@ -1402,6 +1393,87 @@ void dce110_link_encoder_enable_output(
- 	struct bp_transmitter_control cntl = { 0 };
- 	enum bp_result result;
- 
-+	/* Enable the PHY */
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = enc->transmitter;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	cntl.lanes_number = 4;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+
-+	cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	result = dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc110->base.adapter_service),
-+		&cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+/* enables TMDS PHY output */
-+/* TODO: still need this or just pass in adjusted pixel clock? */
-+void dce110_link_encoder_enable_dual_link_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	/* Enable the PHY */
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = enc->transmitter;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+	cntl.lanes_number = 8;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+
-+	cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	result = dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc110->base.adapter_service),
-+		&cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+/* enables DP PHY output */
-+void dce110_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+	enum engine_id engine = enc->transmitter;
-+
- 	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- 		/* power up eDP panel */
- 
-@@ -1421,27 +1493,19 @@ void dce110_link_encoder_enable_output(
- 	 * but it's not passed to asic_control.
- 	 * We need to set number of lanes manually.
- 	 */
--	if (dc_is_dp_signal(signal))
--		configure_encoder(enc110, engine, link_settings);
-+	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
- 	cntl.engine_id = engine;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
--	cntl.signal = signal;
-+	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
- 	cntl.lanes_number = link_settings->lane_count;
- 	cntl.hpd_sel = enc110->base.hpd_source;
--	if (dc_is_dp_signal(signal))
--		cntl.pixel_clock = link_settings->link_rate
-+	cntl.pixel_clock = link_settings->link_rate
- 						* LINK_RATE_REF_FREQ_IN_KHZ;
--	else
--		cntl.pixel_clock = pixel_clock;
--	cntl.color_depth = color_depth;
--
--	if (DELAY_AFTER_PIXEL_FORMAT_CHANGE)
--		dc_service_sleep_in_milliseconds(
--			ctx,
--			DELAY_AFTER_PIXEL_FORMAT_CHANGE);
-+	/* TODO: check if undefined works */
-+	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
- 
- 	result = dal_bios_parser_transmitter_control(
- 		dal_adapter_service_get_bios_parser(
-@@ -1458,6 +1522,51 @@ void dce110_link_encoder_enable_output(
- 	}
- }
- 
-+/* enables DP PHY output in MST mode */
-+void dce110_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+	enum engine_id engine = enc->transmitter;
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually.
-+	 */
-+	configure_encoder(enc110, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = engine;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	/* TODO: check if undefined works */
-+	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
-+
-+	result = dal_bios_parser_transmitter_control(
-+		dal_adapter_service_get_bios_parser(
-+			enc110->base.adapter_service),
-+		&cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
- /*
-  * @brief
-  * Disable transmitter and its encoder
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 820a7b8..c5b16f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -53,7 +53,7 @@ bool dce110_link_encoder_validate_output_with_stream(
- /****************** HW programming ************************/
- 
- /* initialize HW */  /* why do we initialze aux in here? */
--void dce110_link_encoder_power_up(struct link_encoder *enc);
-+void dce110_link_encoder_hw_init(struct link_encoder *enc);
- 
- /* program DIG_MODE in DIG_BE */
- /* TODO can this be combined with enable_output? */
-@@ -61,9 +61,37 @@ void dce110_link_encoder_setup(
- 	struct link_encoder *enc,
- 	enum signal_type signal);
- 
-+/* enables TMDS PHY output */
-+/* TODO: still need depth or just pass in adjusted pixel clock? */
-+void dce110_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock);
-+
-+/* enables TMDS PHY output */
-+/* TODO: still need this or just pass in adjusted pixel clock? */
-+void dce110_link_encoder_enable_dual_link_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	uint32_t pixel_clock);
-+
-+/* enables DP PHY output */
-+void dce110_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source);
-+
-+/* enables DP PHY output in MST mode */
-+void dce110_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source);
-+
- /* disable PHY output */
- void dce110_link_encoder_disable_output(
--	struct link_encoder *enc,
-+	struct link_encoder *link_enc,
- 	enum signal_type signal);
- 
- /* set DP lane settings */
-@@ -84,15 +112,6 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level);
- 
--void dce110_link_encoder_enable_output(
--	struct link_encoder *enc,
--	const struct link_settings *link_settings,
--	enum engine_id engine,
--	enum clock_source_id clock_source,
--	enum signal_type signal,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock);
--
- void dce110_link_encoder_connect_dig_be_to_fe(
- 	struct link_encoder *enc,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index b9f21bb..50af714 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -52,12 +52,12 @@ struct hw_sequencer_funcs {
- 	bool (*transform_power_up)(struct transform *xfm);
- 
- 	bool (*cursor_set_attributes)(
--					struct input_pixel_processor *ipp,
--					const struct dc_cursor_attributes *attributes);
-+				struct input_pixel_processor *ipp,
-+				const struct dc_cursor_attributes *attributes);
- 
- 	bool (*cursor_set_position)(
--					struct input_pixel_processor *ipp,
--					const struct dc_cursor_position *position);
-+				struct input_pixel_processor *ipp,
-+				const struct dc_cursor_position *position);
- 
- 	bool (*set_gamma_ramp)(
- 					struct input_pixel_processor *ipp,
-@@ -86,33 +86,47 @@ struct hw_sequencer_funcs {
- 
- 
- 	/* link encoder sequences */
--	struct link_encoder *(*encoder_create)(const struct encoder_init_data *init);
-+	struct link_encoder *(*encoder_create)(
-+			const struct encoder_init_data *init);
- 
- 	void (*encoder_destroy)(struct link_encoder **enc);
- 
--	void (*encoder_power_up)(
-+	void (*encoder_hw_init)(
- 					struct link_encoder *enc);
- 
--	void (*encoder_enable_output)(
-+	void (*encoder_enable_tmds_output)(
- 					struct link_encoder *enc,
--					const struct link_settings *link_settings,
--					enum engine_id engine,
- 					enum clock_source_id clock_source,
--					enum signal_type signal,
- 					enum dc_color_depth color_depth,
- 					uint32_t pixel_clock);
- 
-+	void (*encoder_enable_dual_link_tmds_output)(
-+					struct link_encoder *enc,
-+					enum clock_source_id clock_source,
-+					enum dc_color_depth color_depth,
-+					uint32_t pixel_clock);
-+
-+	void (*encoder_enable_dp_output)(
-+				struct link_encoder *enc,
-+				const struct link_settings *link_settings,
-+				enum clock_source_id clock_source);
-+
-+	void (*encoder_enable_dp_mst_output)(
-+				struct link_encoder *enc,
-+				const struct link_settings *link_settings,
-+				enum clock_source_id clock_source);
-+
- 	void (*encoder_disable_output)(
- 					struct link_encoder *enc,
- 					enum signal_type signal);
- 
- 	void (*encoder_set_dp_phy_pattern)(
--					struct link_encoder *enc,
--					const struct encoder_set_dp_phy_pattern_param *param);
-+			struct link_encoder *enc,
-+			const struct encoder_set_dp_phy_pattern_param *param);
- 
- 	void (*encoder_dp_set_lane_settings)(
--					struct link_encoder *enc,
--					const struct link_training_settings *link_settings);
-+			struct link_encoder *enc,
-+			const struct link_training_settings *link_settings);
- 
- 	/* backlight control */
- 	void (*encoder_set_lcd_backlight_level)(struct link_encoder *enc,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0645-drm-amd-dal-Swap-enable_stream-and-enable_link-call-.patch b/common/recipes-kernel/linux/files/0645-drm-amd-dal-Swap-enable_stream-and-enable_link-call-.patch
deleted file mode 100644
index 937256d1..00000000
--- a/common/recipes-kernel/linux/files/0645-drm-amd-dal-Swap-enable_stream-and-enable_link-call-.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From 91e820d9c69db1a828a4b1d2d563085639806a48 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Tue, 22 Dec 2015 13:53:24 -0500
-Subject: [PATCH 0645/1110] drm/amd/dal: Swap enable_stream and enable_link
- call sequence.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c               |  6 +++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c            |  1 -
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c          |  1 -
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 11 +++++------
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h              |  1 -
- 5 files changed, 8 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 9b8f536..12c214f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -932,7 +932,6 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 	dp_enable_link_phy(
- 		stream->sink->link,
- 		stream->signal,
--		stream->stream_enc->id,
- 		&link_settings);
- 
- 	panel_mode = dp_get_panel_mode(link);
-@@ -1264,12 +1263,13 @@ void core_link_enable_stream(
- {
- 	struct dc *dc = stream->ctx->dc;
- 
--	dc->hwss.enable_stream(stream);
--
- 	if (DC_OK != enable_link(stream)) {
- 			BREAK_TO_DEBUGGER();
- 			return;
- 	}
-+
-+	dc->hwss.enable_stream(stream);
-+
- 	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		allocate_mst_payload(stream);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 2852440..c0390e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1075,7 +1075,6 @@ bool dp_hbr_verify_link_cap(
- 		dp_enable_link_phy(
- 				link,
- 				link->public.connector_signal,
--				ENGINE_ID_UNKNOWN,
- 				cur);
- 
- 		if (skip_link_training)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index a1617bc..5ed0380 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -55,7 +55,6 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
- void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
--	enum engine_id engine,
- 	const struct link_settings *link_settings)
- {
- 	if (signal == SIGNAL_TYPE_DISPLAY_PORT)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 08711c2..8fc8258 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1396,7 +1396,7 @@ void dce110_link_encoder_enable_tmds_output(
- 	/* Enable the PHY */
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = enc->transmitter;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-@@ -1437,7 +1437,7 @@ void dce110_link_encoder_enable_dual_link_tmds_output(
- 	/* Enable the PHY */
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = enc->transmitter;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-@@ -1472,7 +1472,6 @@ void dce110_link_encoder_enable_dp_output(
- 	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 	enum bp_result result;
--	enum engine_id engine = enc->transmitter;
- 
- 	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
- 		/* power up eDP panel */
-@@ -1496,7 +1495,7 @@ void dce110_link_encoder_enable_dp_output(
- 	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = engine;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
-@@ -1532,7 +1531,7 @@ void dce110_link_encoder_enable_dp_mst_output(
- 	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 	enum bp_result result;
--	enum engine_id engine = enc->transmitter;
-+
- 	/* Enable the PHY */
- 
- 	/* number_of_lanes is used for pixel clock adjust,
-@@ -1542,7 +1541,7 @@ void dce110_link_encoder_enable_dp_mst_output(
- 	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = engine;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index 28d9d04..d9a48c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -43,7 +43,6 @@ enum dc_status core_link_write_dpcd(
- void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
--	enum engine_id engine,
- 	const struct link_settings *link_settings);
- 
- void dp_receiver_power_ctrl(struct core_link *link, bool on);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0646-drm-amd-dal-Refactor-timing-generator-fix-set_early_.patch b/common/recipes-kernel/linux/files/0646-drm-amd-dal-Refactor-timing-generator-fix-set_early_.patch
deleted file mode 100644
index 91277954..00000000
--- a/common/recipes-kernel/linux/files/0646-drm-amd-dal-Refactor-timing-generator-fix-set_early_.patch
+++ /dev/null
@@ -1,440 +0,0 @@
-From 9e1fd9a6eb9af6fa33d31a39d4f3de07ae38fe23 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 23 Dec 2015 09:06:00 -0500
-Subject: [PATCH 0646/1110] drm/amd/dal: Refactor timing generator, fix
- set_early_control bug.
-
-In case of non-DP panel, early_control need to be 0.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   6 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   6 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 131 +++++++++----------
- .../amd/dal/dc/dce110/dce110_timing_generator.h    | 140 +++++++++++----------
- 5 files changed, 138 insertions(+), 147 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 12c214f..0bb3799 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1009,9 +1009,9 @@ static void enable_link_hdmi(struct core_stream *stream)
- 			normalized_pix_clk,
- 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
- 
--	stream->sink->link->cur_link_settings.lane_count =
--		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
--					? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+	dc_service_memset(&stream->sink->link->cur_link_settings, 0,
-+			sizeof(struct link_settings));
-+
- 	if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- 		link->ctx->dc->hwss.encoder_enable_dual_link_tmds_output(
- 				stream->sink->link->link_enc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 6a59fc3..a34cd6d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -645,7 +645,8 @@ static void update_info_frame(struct core_stream *stream)
- 
- static void enable_stream(struct core_stream *stream)
- {
--	enum lane_count lane_count = LANE_COUNT_ONE;
-+	enum lane_count lane_count =
-+			stream->sink->link->cur_link_settings.lane_count;
- 
- 	struct dc_crtc_timing *timing = &stream->public.timing;
- 	struct core_link *link = stream->sink->link;
-@@ -664,7 +665,8 @@ static void enable_stream(struct core_stream *stream)
- 				+ timing->h_border_left
- 				+ timing->h_border_right;
- 
--	early_control = active_total_with_borders % lane_count;
-+	if (lane_count != 0)
-+		early_control = active_total_with_borders % lane_count;
- 
- 	if (early_control == 0)
- 		early_control = lane_count;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 8fc8258..a2dd6ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1399,7 +1399,7 @@ void dce110_link_encoder_enable_tmds_output(
- 	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
--	cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- 	cntl.lanes_number = 4;
- 	cntl.hpd_sel = enc110->base.hpd_source;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 198ff28..182d23e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -233,7 +233,7 @@ enum trigger_polarity_select {
- 
- /******************************************************************************/
- 
--bool dce110_timing_generator_construct(
-+static bool dce110_timing_generator_construct(
- 		struct timing_generator *tg,
- 		enum controller_id id)
- {
-@@ -262,7 +262,32 @@ static const struct crtc_black_color black_color_format[] = {
- 		CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA}
- };
- 
--void dce110_timing_generator_color_space_to_black_color(
-+/**
-+* apply_front_porch_workaround
-+*
-+* This is a workaround for a bug that has existed since R5xx and has not been
-+* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
-+*/
-+static void dce110_timing_generator_apply_front_porch_workaround(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *timing)
-+{
-+	if (timing->flags.INTERLACE == 1) {
-+		if (timing->v_front_porch < 2)
-+			timing->v_front_porch = 2;
-+	} else {
-+		if (timing->v_front_porch < 1)
-+			timing->v_front_porch = 1;
-+	}
-+}
-+
-+static int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
-+	const struct dc_crtc_timing *timing)
-+{
-+	return timing->v_sync_width + timing->v_front_porch;
-+}
-+
-+static void dce110_timing_generator_color_space_to_black_color(
- 		enum color_space colorspace,
- 	struct crtc_black_color *black_color)
- {
-@@ -302,31 +327,31 @@ void dce110_timing_generator_color_space_to_black_color(
- }
- 
- /**
--* apply_front_porch_workaround
--*
--* This is a workaround for a bug that has existed since R5xx and has not been
--* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
--*/
--void dce110_timing_generator_apply_front_porch_workaround(
--	struct timing_generator *tg,
--	struct dc_crtc_timing *timing)
-+ *****************************************************************************
-+ *  Function: is_in_vertical_blank
-+ *
-+ *  @brief
-+ *     check the current status of CRTC to check if we are in Vertical Blank
-+ *     regioneased" state
-+ *
-+ *  @return
-+ *     true if currently in blank region, false otherwise
-+ *
-+ *****************************************************************************
-+ */
-+static bool dce110_timing_generator_is_in_vertical_blank(
-+		struct timing_generator *tg)
- {
--	if (timing->flags.INTERLACE == 1) {
--		if (timing->v_front_porch < 2)
--			timing->v_front_porch = 2;
--	} else {
--		if (timing->v_front_porch < 1)
--			timing->v_front_porch = 1;
--	}
--}
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
- 
--int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
--	const struct dc_crtc_timing *timing)
--{
--	return timing->v_sync_width + timing->v_front_porch;
-+	addr = tg->regs[IDX_CRTC_STATUS];
-+	value = dal_read_reg(tg->ctx, addr);
-+	field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
-+	return field == 1;
- }
- 
--
- void dce110_timing_generator_set_early_control(
- 		struct timing_generator *tg,
- 		uint32_t early_cntl)
-@@ -476,31 +501,6 @@ bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- 
- /**
-  *****************************************************************************
-- *  Function: is_in_vertical_blank
-- *
-- *  @brief
-- *     check the current status of CRTC to check if we are in Vertical Blank
-- *     regioneased" state
-- *
-- *  @return
-- *     true if currently in blank region, false otherwise
-- *
-- *****************************************************************************
-- */
--bool dce110_timing_generator_is_in_vertical_blank(struct timing_generator *tg)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--	uint32_t field = 0;
--
--	addr = tg->regs[IDX_CRTC_STATUS];
--	value = dal_read_reg(tg->ctx, addr);
--	field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
--	return field == 1;
--}
--
--/**
-- *****************************************************************************
-  *  Function: disable_stereo
-  *
-  *  @brief
-@@ -1424,33 +1424,20 @@ void dce110_timing_generator_tear_down_global_swap_lock(
-  *
-  *****************************************************************************
-  */
--
- bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg)
- {
--	uint32_t addr = 0;
--	uint32_t value_1 = 0;
--	uint32_t field_1 = 0;
--	uint32_t value_2 = 0;
--	uint32_t field_2 = 0;
--
--	addr = tg->regs[IDX_CRTC_STATUS_POSITION];
--	value_1 = dal_read_reg(tg->ctx, addr);
--	value_2 = dal_read_reg(tg->ctx, addr);
--
--	field_1 = get_reg_field_value(
--			value_1, CRTC_STATUS_POSITION, CRTC_HORZ_COUNT);
--	field_2 = get_reg_field_value(
--			value_2, CRTC_STATUS_POSITION, CRTC_HORZ_COUNT);
--
--	if (field_1 == field_2) {
--		field_1 = get_reg_field_value(
--			value_1, CRTC_STATUS_POSITION, CRTC_VERT_COUNT);
--		field_2 = get_reg_field_value(
--			value_2, CRTC_STATUS_POSITION, CRTC_VERT_COUNT);
--		return field_1 != field_2;
--	}
-+	uint32_t h1 = 0;
-+	uint32_t h2 = 0;
-+	uint32_t v1 = 0;
-+	uint32_t v2 = 0;
- 
--	return true;
-+	dce110_timing_generator_get_crtc_positions(tg, &h1, &v1);
-+	dce110_timing_generator_get_crtc_positions(tg, &h2, &v2);
-+
-+	if (h1 == h2 && v1 == v2)
-+		return false;
-+	else
-+		return true;
- }
- 
- /*TODO: Figure out if we need this function. */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index d95a2a0..c75c659 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -56,52 +56,102 @@ struct dce110_timing_generator {
- 	bool advanced_request_enable;
- };
- 
-+/********** Create and destroy **********/
- struct timing_generator *dce110_timing_generator_create(
- 	struct adapter_service *as,
- 	struct dc_context *ctx,
- 	enum controller_id id);
--
- void dce110_timing_generator_destroy(struct timing_generator **tg);
- 
--bool dce110_timing_generator_construct(
-+/* determine if given timing can be supported by TG */
-+bool dce110_timing_generator_validate_timing(
- 	struct timing_generator *tg,
--	enum controller_id id);
-+	const struct dc_crtc_timing *timing,
-+	enum signal_type signal);
- 
--void dce110_timing_generator_program_blank_color(
--	struct timing_generator *tg,
--	enum color_space color_space);
-+/******** HW programming ************/
- 
--bool dce110_timing_generator_blank_crtc(struct timing_generator *tg);
-+/* Program timing generator with given timing */
-+bool dce110_timing_generator_program_timing_generator(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *dc_crtc_timing);
- 
-+/* Disable/Enable Timing Generator */
- bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
--
- bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
- 
--bool dce110_timing_generator_is_in_vertical_blank(struct timing_generator *tg);
-+void dce110_timing_generator_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl);
- 
--void dce110_timing_generator_program_blanking(
-+/**************** TG current status ******************/
-+
-+/* return the current frame counter. Used by Linux kernel DRM */
-+uint32_t dce110_timing_generator_get_vblank_counter(
-+		struct timing_generator *tg);
-+
-+/* Get current H and V position */
-+void dce110_timing_generator_get_crtc_positions(
- 	struct timing_generator *tg,
--	const struct dc_crtc_timing *timing);
-+	int32_t *h_position,
-+	int32_t *v_position);
- 
--bool dce110_timing_generator_program_timing_generator(
-+/* return true if TG counter is moving. false if TG is stopped */
-+bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg);
-+
-+/* wait until TG is in beginning of vertical blank region */
-+void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg);
-+
-+/* wait until TG is in beginning of active region */
-+void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg);
-+
-+
-+/*********** Timing Generator Synchronization routines ****/
-+
-+/* Setups Global Swap Lock group, TimingServer or TimingClient*/
-+void dce110_timing_generator_setup_global_swap_lock(
- 	struct timing_generator *tg,
--	struct dc_crtc_timing *dc_crtc_timing);
-+	const struct dcp_gsl_params *gsl_params);
- 
--void dce110_timing_generator_set_early_control(
--		struct timing_generator *tg,
--		uint32_t early_cntl);
-+/* Clear all the register writes done by setup_global_swap_lock */
-+void dce110_timing_generator_tear_down_global_swap_lock(
-+	struct timing_generator *tg);
-+
-+/* Reset slave controllers on master VSync */
-+void dce110_timing_generator_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	const struct trigger_params *trigger_params);
-+
-+/* disabling trigger-reset */
-+void dce110_timing_generator_disable_reset_trigger(
-+	struct timing_generator *tg);
-+
-+/* Checks whether CRTC triggered reset occurred */
-+bool dce110_timing_generator_did_triggered_reset_occur(
-+	struct timing_generator *tg);
- 
-+/******** Stuff to move to other virtual HW objects *****************/
-+/* TODO: Should we move it to mem_input interface? */
-+bool dce110_timing_generator_blank_crtc(struct timing_generator *tg);
- bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg);
-+void dce110_timing_generator_disable_vga(struct timing_generator *tg);
- 
--bool dce110_timing_generator_validate_timing(
-+/* TODO: Should we move it to transform */
-+void dce110_timing_generator_program_blanking(
- 	struct timing_generator *tg,
--	const struct dc_crtc_timing *timing,
--	enum signal_type signal);
-+	const struct dc_crtc_timing *timing);
- 
--void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg);
-+/* TODO: Should we move it to opp? */
-+void dce110_timing_generator_program_blank_color(
-+	struct timing_generator *tg,
-+	enum color_space color_space);
-+void dce110_timing_generator_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	enum color_space black_color);
-+/*************** End-of-move ********************/
- 
--void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg);
- 
-+/* Not called yet */
- void dce110_timing_generator_set_test_pattern(
- 	struct timing_generator *tg,
- 	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-@@ -119,26 +169,6 @@ uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	int32_t *vbl,
- 	int32_t *position);
- 
--uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg);
--
--void dce110_timing_generator_color_space_to_black_color(
--		enum color_space colorspace,
--		struct crtc_black_color *black_color);
--void dce110_timing_generator_apply_front_porch_workaround(
--	struct timing_generator *tg,
--	struct dc_crtc_timing *timing);
--int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
--	const struct dc_crtc_timing *timing);
--
--void dce110_timing_generator_get_crtc_positions(
--	struct timing_generator *tg,
--	int32_t *h_position,
--	int32_t *v_position);
--
--
--/* TODO: Figure out if we need these functions*/
--bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg);
--
- void dce110_timing_generator_enable_advanced_request(
- 	struct timing_generator *tg,
- 	bool enable,
-@@ -147,32 +177,4 @@ void dce110_timing_generator_enable_advanced_request(
- void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
- 		bool lock);
- 
--void dce110_timing_generator_set_overscan_color_black(
--	struct timing_generator *tg,
--	enum color_space black_color);
--
--
--/**** Sync-related interfaces ****/
--void dce110_timing_generator_setup_global_swap_lock(
--	struct timing_generator *tg,
--	const struct dcp_gsl_params *gsl_params);
--void dce110_timing_generator_tear_down_global_swap_lock(
--	struct timing_generator *tg);
--
--
--void dce110_timing_generator_enable_reset_trigger(
--	struct timing_generator *tg,
--	const struct trigger_params *trigger_params);
--
--void dce110_timing_generator_disable_reset_trigger(
--	struct timing_generator *tg);
--
--bool dce110_timing_generator_did_triggered_reset_occur(
--	struct timing_generator *tg);
--
--void dce110_timing_generator_disable_vga(
--	struct timing_generator *tg);
--
--/**** End-of-Sync-related interfaces ****/
--
- #endif /* __DC_TIMING_GENERATOR_DCE110_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0647-drm-amd-dal-Properly-handle-sink-removal.patch b/common/recipes-kernel/linux/files/0647-drm-amd-dal-Properly-handle-sink-removal.patch
deleted file mode 100644
index 263623a4..00000000
--- a/common/recipes-kernel/linux/files/0647-drm-amd-dal-Properly-handle-sink-removal.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 6d9c0236d50e7730bcafb04c3c5855b9251249f7 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 23 Dec 2015 10:57:17 -0500
-Subject: [PATCH 0647/1110] drm/amd/dal: Properly handle sink removal
-
-This fixes assert in dc_link_remove_sink when unplug mst display
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c |  3 ++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c               | 13 +++++--------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h             |  2 ++
- 3 files changed, 9 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 7ef2e60..e765f57 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -347,7 +347,8 @@ static void dm_dp_destroy_mst_connector(
- 	drm_connector_cleanup(connector);
- 	drm_modeset_unlock_all(dev);
- 
--	dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
-+	if (aconnector->dc_sink)
-+		dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
- 
- 	kfree(aconnector);
- 	DRM_DEBUG_KMS("\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 0bb3799..646706e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -522,6 +522,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 					if (dc_helpers_dp_mst_start_top_mgr(
- 						link->ctx,
- 						&link->public)) {
-+						link->mst_enabled = true;
- 						return;
- 					} else {
- 						/* MST not supported */
-@@ -636,15 +637,11 @@ void dc_link_detect(const struct dc_link *dc_link)
- 
- 	} else {
- 		/* From Connected-to-Disconnected. */
--		switch (link->public.connector_signal) {
--		case SIGNAL_TYPE_DISPLAY_PORT:
-+		if (link->mst_enabled) {
- 			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
--			break;
--		default:
--			break;
--		}
--
--		link_disconnect_all_sinks(link);
-+			link->mst_enabled = false;
-+		} else
-+			link_disconnect_all_sinks(link);
- 	}
- 
- 	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 194b3e0..dc871ad 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -227,6 +227,8 @@ struct core_link {
- 	/* MST record stream using this link */
- 	const struct core_stream *enabled_streams[MAX_SINKS_PER_LINK];
- 	uint8_t enabled_stream_count;
-+
-+	bool mst_enabled;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0648-amdgpu-fix-fbcon-S3-resume-with-dal_enabled.patch b/common/recipes-kernel/linux/files/0648-amdgpu-fix-fbcon-S3-resume-with-dal_enabled.patch
deleted file mode 100644
index fca39794..00000000
--- a/common/recipes-kernel/linux/files/0648-amdgpu-fix-fbcon-S3-resume-with-dal_enabled.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From dd67446826dc75dc276782294ae552c1d0fc102a Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 5 Jan 2016 11:46:09 -0500
-Subject: [PATCH 0648/1110] amdgpu: fix fbcon S3 resume with dal_enabled
-
-DAL does not use drm_helper_resume_force_mode and
-drm_helper_connector_dpms for resuming from S3
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-By: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index fcfdf2d..7e24cdb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1835,18 +1835,17 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- 
- 	/* blat the mode back in */
- 	if (fbcon) {
--		drm_helper_resume_force_mode(dev);
- 		if (!amdgpu_has_dal_support(adev)) {
- 			/* pre DCE11 */
- 			drm_helper_resume_force_mode(dev);
--		}
- 
--		/* turn on display hw */
--		drm_modeset_lock_all(dev);
--		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-+			/* turn on display hw */
-+			drm_modeset_lock_all(dev);
-+			list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-+			}
-+			drm_modeset_unlock_all(dev);
- 		}
--		drm_modeset_unlock_all(dev);
- 	}
- 
- 	drm_kms_helper_poll_enable(dev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0649-drm-amd-dal-Remove-registration-of-Poll-for-connecto.patch b/common/recipes-kernel/linux/files/0649-drm-amd-dal-Remove-registration-of-Poll-for-connecto.patch
deleted file mode 100644
index 4d6514e6..00000000
--- a/common/recipes-kernel/linux/files/0649-drm-amd-dal-Remove-registration-of-Poll-for-connecto.patch
+++ /dev/null
@@ -1,146 +0,0 @@
-From f30dd83168f27183295c41c761935bc41c72073e Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Tue, 22 Dec 2015 17:57:28 -0500
-Subject: [PATCH 0649/1110] drm/amd/dal: Remove registration of Poll for
- connector.
-
-Our display detection is interrupt-driven, no need to register for
-Poll from DRM.
-
-Also this results in:
-- less notifications from kernel to user mode about hpd events.
-- less contention on MST state is triggered from user-mode.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 29 +++++++++++++++++++---
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |  7 ++----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 20 +++++----------
- 3 files changed, 34 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 0a05774..e856f0c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -471,6 +471,30 @@ void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- 	}
- }
- 
-+/* Depending on Root connector state, update MST state of all connectors
-+ * belonging to it. */
-+static void set_mst_topology_state(struct drm_device *dev)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector = NULL;
-+
-+	mutex_lock(&dev->mode_config.mutex);
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		mutex_unlock(&dev->mode_config.mutex);
-+
-+		aconnector = to_amdgpu_connector(connector);
-+
-+		if (aconnector->is_mst_connector)
-+			drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr,
-+					aconnector->is_mst_connector);
-+
-+		mutex_lock(&dev->mode_config.mutex);
-+	}
-+
-+	mutex_unlock(&dev->mode_config.mutex);
-+}
-+
- bool dc_helpers_dp_mst_start_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link)
-@@ -480,7 +504,7 @@ bool dc_helpers_dp_mst_start_top_mgr(
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
- 	aconnector->is_mst_connector = true;
--
-+	set_mst_topology_state(dev);
- 	return true;
- }
- 
-@@ -492,9 +516,8 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
--	drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
--
- 	aconnector->is_mst_connector = false;
-+	set_mst_topology_state(dev);
- }
- 
- bool dc_helper_dp_read_dpcd(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index b2b7820..62df355 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -793,7 +793,7 @@ static void handle_hpd_irq(void *param)
- 
- 	dc_link_detect(aconnector->dc_link);
- 	amdgpu_dm_update_connector_after_detect(aconnector);
--	drm_helper_hpd_irq_event(dev);
-+	drm_kms_helper_hotplug_event(dev);
- }
- 
- static void handle_hpd_rx_irq(void *param)
-@@ -807,7 +807,7 @@ static void handle_hpd_rx_irq(void *param)
- 		/* Downstream Port status changed. */
- 		dc_link_detect(aconnector->dc_link);
- 		amdgpu_dm_update_connector_after_detect(aconnector);
--		drm_helper_hpd_irq_event(dev);
-+		drm_kms_helper_hotplug_event(dev);
- 	}
- 
- 	if (aconnector->is_mst_connector) {
-@@ -930,9 +930,6 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
- 
- 	register_hpd_handlers(adev);
- 
--	/* This is a part of HPD initialization. */
--	drm_kms_helper_poll_init(adev->ddev);
--
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 33fe1a4..492939e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -988,23 +988,15 @@ static enum drm_connector_status
- amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
- {
- 	bool connected;
--	struct amdgpu_connector *aconnector =
--			to_amdgpu_connector(connector);
--
--	/*
--	 * TODO: check whether we should lock here for mst_mgr.lock
--	 */
--	/* set root connector to disconnected */
--	if (aconnector->is_mst_connector) {
--		if (!aconnector->mst_mgr.mst_state)
--			drm_dp_mst_topology_mgr_set_mst(
--				&aconnector->mst_mgr,
--				true);
-+	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
- 
--		return connector_status_disconnected;
--	}
-+	/* Notes:
-+	 * 1. This interface is NOT called in context of HPD irq.
-+	 * 2. This interface *is called* in context of user-mode ioctl. Which
-+	 * makes it a bad place for *any* MST-related activit. */
- 
- 	connected = (NULL != aconnector->dc_sink);
-+
- 	return (connected ? connector_status_connected :
- 			connector_status_disconnected);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0650-drm-amd-dal-Refactor-timing-generator.patch b/common/recipes-kernel/linux/files/0650-drm-amd-dal-Refactor-timing-generator.patch
deleted file mode 100644
index 4b83b4b3..00000000
--- a/common/recipes-kernel/linux/files/0650-drm-amd-dal-Refactor-timing-generator.patch
+++ /dev/null
@@ -1,717 +0,0 @@
-From 204f22d4fef912e6ee47572f2deecf8d4c5ccc3c Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 23 Dec 2015 16:27:53 -0500
-Subject: [PATCH 0650/1110] drm/amd/dal: Refactor timing generator.
-
-Change the way to access register the same
-as stream_encoder.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 269 ++++++++-------------
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   6 +
- .../drm/amd/dal/include/timing_generator_types.h   |   1 -
- 3 files changed, 103 insertions(+), 173 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 182d23e..3c6c04a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -37,64 +37,6 @@
- #include "include/timing_generator_types.h"
- #include "dce110_timing_generator.h"
- 
--
--enum tg_regs_idx {
--	IDX_CRTC_UPDATE_LOCK,
--	IDX_CRTC_MASTER_UPDATE_LOCK,
--	IDX_CRTC_MASTER_UPDATE_MODE,
--	IDX_CRTC_H_TOTAL,
--	IDX_CRTC_V_TOTAL,
--	IDX_CRTC_H_BLANK_START_END,
--	IDX_CRTC_V_BLANK_START_END,
--	IDX_CRTC_H_SYNC_A,
--	IDX_CRTC_V_SYNC_A,
--	IDX_CRTC_H_SYNC_A_CNTL,
--	IDX_CRTC_V_SYNC_A_CNTL,
--	IDX_CRTC_INTERLACE_CONTROL,
--	IDX_CRTC_BLANK_CONTROL,
--	IDX_PIPE_PG_STATUS,
--
--	IDX_CRTC_TEST_PATTERN_COLOR,
--	IDX_CRTC_TEST_PATTERN_CONTROL,
--	IDX_CRTC_TEST_PATTERN_PARAMETERS,
--	IDX_CRTC_FLOW_CONTROL,
--	IDX_CRTC_STATUS,
--	IDX_CRTC_STATUS_POSITION,
--	IDX_CRTC_STATUS_FRAME_COUNT,
--	IDX_CRTC_STEREO_CONTROL,
--	IDX_CRTC_STEREO_STATUS,
--	IDX_CRTC_STEREO_FORCE_NEXT_EYE,
--	IDX_CRTC_3D_STRUCTURE_CONTROL,
--	IDX_CRTC_DOUBLE_BUFFER_CONTROL,
--	IDX_CRTC_V_TOTAL_MIN,
--	IDX_CRTC_V_TOTAL_MAX,
--	IDX_CRTC_V_TOTAL_CONTROL,
--	IDX_CRTC_NOM_VERT_POSITION,
--	IDX_CRTC_STATIC_SCREEN_CONTROL,
--	IDX_CRTC_TRIGB_CNTL,
--	IDX_CRTC_FORCE_COUNT_CNTL,
--	IDX_CRTC_GSL_CONTROL,
--	IDX_CRTC_GSL_WINDOW,
--
--	IDX_CRTC_CONTROL,
--	IDX_CRTC_START_LINE_CONTROL,
--	IDX_CRTC_COUNT_CONTROL,
--
--	IDX_MODE_EXT_OVERSCAN_LEFT_RIGHT,
--	IDX_MODE_EXT_OVERSCAN_TOP_BOTTOM,
--	IDX_DCP_GSL_CONTROL,
--	IDX_GRPH_UPDATE,
--
--	IDX_CRTC_VBI_END,
--
--	IDX_BLND_UNDERFLOW_INTERRUPT,
--	IDX_CRTC_BLACK_COLOR,
--	IDX_CRTC_OVERSCAN_COLOR,
--	IDX_CRTC_BLANK_DATA_COLOR,
--
--	TG_REGS_IDX_SIZE
--};
--
- enum black_color_format {
- 	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
- 	BLACK_COLOR_FORMAT_RGB_LIMITED,
-@@ -105,61 +47,6 @@ enum black_color_format {
- 	BLACK_COLOR_FORMAT_COUNT
- };
- 
--#define regs_for_controller(id)\
--[CONTROLLER_ID_D ## id - 1] =\
--{[IDX_CRTC_UPDATE_LOCK] = mmCRTC ## id ## _CRTC_UPDATE_LOCK,\
--[IDX_CRTC_MASTER_UPDATE_LOCK] = mmCRTC ## id ## _CRTC_MASTER_UPDATE_LOCK,\
--[IDX_CRTC_MASTER_UPDATE_MODE] = mmCRTC ## id ## _CRTC_MASTER_UPDATE_MODE,\
--[IDX_CRTC_H_TOTAL] = mmCRTC ## id ## _CRTC_H_TOTAL,\
--[IDX_CRTC_V_TOTAL] = mmCRTC ## id ## _CRTC_V_TOTAL,\
--[IDX_CRTC_H_BLANK_START_END] = mmCRTC ## id ## _CRTC_H_BLANK_START_END,\
--[IDX_CRTC_V_BLANK_START_END] = mmCRTC ## id ## _CRTC_V_BLANK_START_END,\
--[IDX_CRTC_H_SYNC_A] = mmCRTC ## id ## _CRTC_H_SYNC_A,\
--[IDX_CRTC_V_SYNC_A] = mmCRTC ## id ## _CRTC_V_SYNC_A,\
--[IDX_CRTC_H_SYNC_A_CNTL] = mmCRTC ## id ## _CRTC_H_SYNC_A_CNTL,\
--[IDX_CRTC_V_SYNC_A_CNTL] = mmCRTC ## id ## _CRTC_V_SYNC_A_CNTL,\
--[IDX_CRTC_INTERLACE_CONTROL] = mmCRTC ## id ## _CRTC_INTERLACE_CONTROL,\
--[IDX_CRTC_BLANK_CONTROL] = mmCRTC ## id ## _CRTC_BLANK_CONTROL,\
--[IDX_PIPE_PG_STATUS] = mmPIPE ## id ## _PG_STATUS,\
--[IDX_CRTC_TEST_PATTERN_COLOR] = mmCRTC ## id ## _CRTC_TEST_PATTERN_COLOR,\
--[IDX_CRTC_TEST_PATTERN_CONTROL] = mmCRTC ## id ## _CRTC_TEST_PATTERN_CONTROL,\
--[IDX_CRTC_TEST_PATTERN_PARAMETERS] =\
--mmCRTC ## id ## _CRTC_TEST_PATTERN_PARAMETERS,\
--[IDX_CRTC_FLOW_CONTROL] = mmCRTC ## id ## _CRTC_FLOW_CONTROL,\
--[IDX_CRTC_STATUS] = mmCRTC ## id ## _CRTC_STATUS,\
--[IDX_CRTC_STATUS_POSITION] = mmCRTC ## id ## _CRTC_STATUS_POSITION,\
--[IDX_CRTC_STATUS_FRAME_COUNT] = mmCRTC ## id ## _CRTC_STATUS_FRAME_COUNT,\
--[IDX_CRTC_STEREO_CONTROL] = mmCRTC ## id ## _CRTC_STEREO_CONTROL,\
--[IDX_CRTC_STEREO_STATUS] = mmCRTC ## id ## _CRTC_STEREO_STATUS,\
--[IDX_CRTC_STEREO_FORCE_NEXT_EYE] = \
--mmCRTC ## id ## _CRTC_STEREO_FORCE_NEXT_EYE,\
--[IDX_CRTC_3D_STRUCTURE_CONTROL] = mmCRTC ## id ## _CRTC_3D_STRUCTURE_CONTROL,\
--[IDX_CRTC_DOUBLE_BUFFER_CONTROL] =\
--mmCRTC ## id ## _CRTC_DOUBLE_BUFFER_CONTROL,\
--[IDX_CRTC_V_TOTAL_MIN] = mmCRTC ## id ## _CRTC_V_TOTAL_MIN,\
--[IDX_CRTC_V_TOTAL_MAX] = mmCRTC ## id ## _CRTC_V_TOTAL_MAX,\
--[IDX_CRTC_V_TOTAL_CONTROL] = mmCRTC ## id ## _CRTC_V_TOTAL_CONTROL,\
--[IDX_CRTC_NOM_VERT_POSITION] = mmCRTC ## id ## _CRTC_NOM_VERT_POSITION,\
--[IDX_CRTC_STATIC_SCREEN_CONTROL] =\
--mmCRTC ## id ## _CRTC_STATIC_SCREEN_CONTROL,\
--[IDX_CRTC_TRIGB_CNTL] = mmCRTC ## id ## _CRTC_TRIGB_CNTL,\
--[IDX_CRTC_FORCE_COUNT_CNTL] = mmCRTC ## id ## _CRTC_FORCE_COUNT_NOW_CNTL,\
--[IDX_CRTC_GSL_CONTROL] = mmCRTC ## id ## _CRTC_GSL_CONTROL,\
--[IDX_CRTC_GSL_WINDOW] = mmCRTC ## id ## _CRTC_GSL_WINDOW,\
--[IDX_CRTC_CONTROL] = mmCRTC ## id ## _CRTC_CONTROL,\
--[IDX_CRTC_START_LINE_CONTROL] = mmCRTC ## id ## _CRTC_START_LINE_CONTROL,\
--[IDX_CRTC_COUNT_CONTROL] = mmCRTC ## id ## _CRTC_COUNT_CONTROL,\
--[IDX_MODE_EXT_OVERSCAN_LEFT_RIGHT] = mmSCL ## id ## _EXT_OVERSCAN_LEFT_RIGHT,\
--[IDX_MODE_EXT_OVERSCAN_TOP_BOTTOM] = mmSCL ## id ## _EXT_OVERSCAN_TOP_BOTTOM,\
--[IDX_DCP_GSL_CONTROL] = mmDCP ## id ## _DCP_GSL_CONTROL,\
--[IDX_GRPH_UPDATE] = mmDCP ## id ## _GRPH_UPDATE,\
--[IDX_CRTC_VBI_END] = mmCRTC ## id ## _CRTC_VBI_END,\
--[IDX_BLND_UNDERFLOW_INTERRUPT] = mmBLND ## id ## _BLND_UNDERFLOW_INTERRUPT,\
--[IDX_CRTC_BLACK_COLOR] = mmCRTC ## id ## _CRTC_BLACK_COLOR,\
--[IDX_CRTC_OVERSCAN_COLOR] = mmCRTC ## id ## _CRTC_OVERSCAN_COLOR,\
--[IDX_CRTC_BLANK_DATA_COLOR] = mmCRTC ## id ## _CRTC_BLANK_DATA_COLOR,\
--}
--
- #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
- 
- #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
-@@ -169,12 +56,23 @@ mmCRTC ## id ## _CRTC_STATIC_SCREEN_CONTROL,\
- #define FROM_TIMING_GENERATOR(tg)\
- 	container_of(tg, struct dce110_timing_generator, base)
- 
--static uint32_t tg_regs[][TG_REGS_IDX_SIZE] = {
--	regs_for_controller(0),
--	regs_for_controller(1),
--	regs_for_controller(2),
--};
-+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
-+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
- 
-+static const struct dce110_timing_generator_offsets reg_offsets[] = {
-+	{
-+		.crtc = 0,
-+		.dcp = 0,
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	}
-+};
- /*******************************************************************************
-  * GSL Sync related values */
- 
-@@ -237,7 +135,10 @@ static bool dce110_timing_generator_construct(
- 		struct timing_generator *tg,
- 		enum controller_id id)
- {
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+
- 	tg->controller_id = id;
-+	tg110->offsets = reg_offsets[id - 1];
- 	return true;
- }
- 
-@@ -345,8 +246,9 @@ static bool dce110_timing_generator_is_in_vertical_blank(
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 	uint32_t field = 0;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
--	addr = tg->regs[IDX_CRTC_STATUS];
-+	addr = CRTC_REG(mmCRTC_STATUS);
- 	value = dal_read_reg(tg->ctx, addr);
- 	field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
- 	return field == 1;
-@@ -357,7 +259,8 @@ void dce110_timing_generator_set_early_control(
- 		uint32_t early_cntl)
- {
- 	uint32_t regval;
--	uint32_t address = tg->regs[IDX_CRTC_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t address = CRTC_REG(mmCRTC_CONTROL);
- 
- 	regval = dal_read_reg(tg->ctx, address);
- 	set_reg_field_value(regval, early_cntl,
-@@ -376,13 +279,14 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	/* 0 value is needed by DRR and is also suggested default value for CZ
- 	 */
- 	uint32_t value;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	value = dal_read_reg(tg->ctx,
--			tg->regs[IDX_CRTC_MASTER_UPDATE_MODE]);
-+			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
- 	set_reg_field_value(value, 3,
- 			CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
- 	dal_write_reg(tg->ctx,
--			tg->regs[IDX_CRTC_MASTER_UPDATE_MODE], value);
-+			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
- 	result = dal_bios_parser_enable_crtc(tg->bp, tg->controller_id, true);
- 
-@@ -394,7 +298,8 @@ void dce110_timing_generator_program_blank_color(
- 		enum color_space color_space)
- {
- 	struct crtc_black_color black_color;
--	uint32_t addr = tg->regs[IDX_CRTC_BLACK_COLOR];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
- 	dce110_timing_generator_color_space_to_black_color(
-@@ -427,7 +332,8 @@ void dce110_timing_generator_program_blank_color(
- 
- bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- {
--	uint32_t addr = tg->regs[IDX_CRTC_BLANK_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_BLANK_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 	uint8_t counter = 100;
- 
-@@ -479,7 +385,8 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
-  */
- bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- {
--	uint32_t addr = tg->regs[IDX_CRTC_BLANK_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_BLANK_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
- 	set_reg_field_value(
-@@ -512,7 +419,8 @@ bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- @TODOSTEREO
- static void disable_stereo(struct timing_generator *tg)
- {
--	uint32_t addr = tg->regs[IDX_CRTC_3D_STRUCTURE_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL);
- 	uint32_t value = 0;
- 	uint32_t test = 0;
- 	uint32_t field = 0;
-@@ -579,9 +487,10 @@ static void program_horz_count_by_2(
- 	const struct dc_crtc_timing *timing)
- {
- 	uint32_t regval;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	regval = dal_read_reg(tg->ctx,
--			tg->regs[IDX_CRTC_COUNT_CONTROL]);
-+			CRTC_REG(mmCRTC_COUNT_CONTROL));
- 
- 	set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,
- 			CRTC_HORZ_COUNT_BY2_EN);
-@@ -591,7 +500,7 @@ static void program_horz_count_by_2(
- 					CRTC_HORZ_COUNT_BY2_EN);
- 
- 	dal_write_reg(tg->ctx,
--		tg->regs[IDX_CRTC_COUNT_CONTROL], regval);
-+			CRTC_REG(mmCRTC_COUNT_CONTROL), regval);
- }
- 
- /**
-@@ -606,6 +515,7 @@ bool dce110_timing_generator_program_timing_generator(
- 	enum bp_result result;
- 	struct bp_hw_crtc_timing_parameters bp_params;
- 	uint32_t regval;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +
- 			dc_crtc_timing->v_front_porch;
-@@ -663,7 +573,7 @@ bool dce110_timing_generator_program_timing_generator(
- 
- 
- 	regval = dal_read_reg(tg->ctx,
--			tg->regs[IDX_CRTC_START_LINE_CONTROL]);
-+			CRTC_REG(mmCRTC_START_LINE_CONTROL));
- 
- 	if (dce110_timing_generator_get_vsynch_and_front_porch_size(dc_crtc_timing) <= 3) {
- 		set_reg_field_value(regval, 3,
-@@ -683,7 +593,7 @@ bool dce110_timing_generator_program_timing_generator(
- 				CRTC_PREFETCH_EN);
- 	}
- 	dal_write_reg(tg->ctx,
--			tg->regs[IDX_CRTC_START_LINE_CONTROL], regval);
-+			CRTC_REG(mmCRTC_START_LINE_CONTROL), regval);
- 
- 	/* Enable stereo - only when we need to pack 3D frame. Other types
- 	 * of stereo handled in explicit call */
-@@ -722,19 +632,20 @@ void dce110_timing_generator_program_drr(
- 	uint32_t v_total_max = 0;
- 	uint32_t v_total_cntl = 0;
- 	uint32_t static_screen_cntl = 0;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	uint32_t addr = 0;
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL_MIN];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
- 	v_total_min = dal_read_reg(tg->ctx, addr);
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL_MAX];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
- 	v_total_max = dal_read_reg(tg->ctx, addr);
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL_CONTROL];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL);
- 	v_total_cntl = dal_read_reg(tg->ctx, addr);
- 
--	addr = tg->regs[IDX_CRTC_STATIC_SCREEN_CONTROL];
-+	addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL);
- 	static_screen_cntl = dal_read_reg(tg->ctx, addr);
- 
- 	if (timing != NULL) {
-@@ -856,16 +767,16 @@ void dce110_timing_generator_program_drr(
- 				CRTC_FORCE_LOCK_TO_MASTER_VSYNC);
- 	}
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL_MIN];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
- 	dal_write_reg(tg->ctx, addr, v_total_min);
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL_MAX];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
- 	dal_write_reg(tg->ctx, addr, v_total_max);
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL_CONTROL];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL);
- 	dal_write_reg(tg->ctx, addr, v_total_cntl);
- 
--	addr = tg->regs[IDX_CRTC_STATIC_SCREEN_CONTROL];
-+	addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL);
- 	dal_write_reg(tg->ctx, addr, static_screen_cntl);
- }
- 
-@@ -885,7 +796,8 @@ void dce110_timing_generator_program_drr(
-  */
- uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)
- {
--	uint32_t addr = tg->regs[IDX_CRTC_STATUS_FRAME_COUNT];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 	uint32_t field = get_reg_field_value(
- 			value, CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
-@@ -910,8 +822,9 @@ void dce110_timing_generator_get_crtc_positions(
- 	int32_t *v_position)
- {
- 	uint32_t value;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
--	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_STATUS_POSITION]);
-+	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION));
- 
- 	*h_position = get_reg_field_value(
- 			value,
-@@ -939,6 +852,7 @@ uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	int32_t *vbl,
- 	int32_t *position)
- {
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 	/* TODO 1: Update the implementation once caller is updated
- 	 * WARNING!! This function is returning the whole register value
- 	 * because the caller is expecting it instead of proper vertical and
-@@ -948,10 +862,10 @@ uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	/* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */
- 
- 	*vbl = dal_read_reg(tg->ctx,
--			tg->regs[IDX_CRTC_V_BLANK_START_END]);
-+			CRTC_REG(mmCRTC_V_BLANK_START_END));
- 
- 	*position = dal_read_reg(tg->ctx,
--			tg->regs[IDX_CRTC_STATUS_POSITION]);
-+			CRTC_REG(mmCRTC_STATUS_POSITION));
- 
- 	/* @TODO: return value should indicate if current
- 	 * crtc is inside vblank*/
-@@ -973,13 +887,14 @@ void dce110_timing_generator_program_blanking(
- 	uint32_t hsync_offset = timing->h_border_right +
- 			timing->h_front_porch;
- 	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
- 	uint32_t addr = 0;
- 	uint32_t tmp = 0;
- 
--	addr = tg->regs[IDX_CRTC_H_TOTAL];
-+	addr = CRTC_REG(mmCRTC_H_TOTAL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
-@@ -988,7 +903,7 @@ void dce110_timing_generator_program_blanking(
- 		CRTC_H_TOTAL);
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = tg->regs[IDX_CRTC_V_TOTAL];
-+	addr = CRTC_REG(mmCRTC_V_TOTAL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
-@@ -997,7 +912,7 @@ void dce110_timing_generator_program_blanking(
- 		CRTC_V_TOTAL);
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = tg->regs[IDX_CRTC_H_BLANK_START_END];
-+	addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
- 	value = dal_read_reg(ctx, addr);
- 
- 	tmp = timing->h_total -
-@@ -1020,7 +935,7 @@ void dce110_timing_generator_program_blanking(
- 
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = tg->regs[IDX_CRTC_V_BLANK_START_END];
-+	addr = CRTC_REG(mmCRTC_V_BLANK_START_END);
- 	value = dal_read_reg(ctx, addr);
- 
- 	tmp = timing->v_total - (v_sync_start + timing->v_border_top);
-@@ -1054,12 +969,13 @@ void dce110_timing_generator_set_test_pattern(
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value;
- 	uint32_t addr;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	/* TODO: add support for other test patterns */
- 	switch (test_pattern) {
- 	default:
- 		value = 0;
--		addr = tg->regs[IDX_CRTC_TEST_PATTERN_PARAMETERS];
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS);
- 
- 		set_reg_field_value(
- 			value,
-@@ -1074,7 +990,7 @@ void dce110_timing_generator_set_test_pattern(
- 
- 		dal_write_reg(ctx, addr, value);
- 
--		addr = tg->regs[IDX_CRTC_TEST_PATTERN_CONTROL];
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL);
- 		value = 0;
- 
- 		set_reg_field_value(
-@@ -1221,7 +1137,6 @@ static bool timing_generator_dce110_construct(struct timing_generator *tg,
- 
- 	tg->ctx = ctx;
- 	tg->bp = dal_adapter_service_get_bios_parser(as);
--	tg->regs = tg_regs[id-1];
- 
- 	tg->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
- 	tg->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-@@ -1270,7 +1185,8 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	const struct dcp_gsl_params *gsl_params)
- {
- 	uint32_t value;
--	uint32_t address = tg->regs[IDX_DCP_GSL_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
- 	uint32_t check_point = FLIP_READY_BACK_LOOKUP;
- 
- 	value = dal_read_reg(tg->ctx, address);
-@@ -1302,7 +1218,8 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	{
- 		uint32_t value_crtc_vtotal;
- 
--		value_crtc_vtotal = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_V_TOTAL]);
-+		value_crtc_vtotal = dal_read_reg(tg->ctx,
-+				CRTC_REG(mmCRTC_V_TOTAL));
- 
- 		set_reg_field_value(value,
- 				gsl_params->gsl_purpose,
-@@ -1314,7 +1231,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 				CRTC_V_TOTAL,
- 				CRTC_V_TOTAL);
- 
--		dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_GSL_WINDOW], 0);
-+		dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0);
- 	}
- 
- 	set_reg_field_value(value,
-@@ -1325,7 +1242,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	dal_write_reg(tg->ctx, address, value);
- 
- 	/********************************************************************/
--	address = tg->regs[IDX_CRTC_GSL_CONTROL];
-+	address = CRTC_REG(mmCRTC_GSL_CONTROL);
- 
- 	value = 0;
- 	set_reg_field_value(value,
-@@ -1350,7 +1267,8 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 	 */
- 
- 	uint32_t value;
--	uint32_t address = tg->regs[IDX_DCP_GSL_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
- 
- 	value = 0;
- 
-@@ -1381,7 +1299,8 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 	{
- 		uint32_t value_crtc_vtotal;
- 
--		value_crtc_vtotal = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_V_TOTAL]);
-+		value_crtc_vtotal = dal_read_reg(tg->ctx,
-+				CRTC_REG(mmCRTC_V_TOTAL));
- 
- 		set_reg_field_value(value,
- 				0,
-@@ -1397,7 +1316,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 	dal_write_reg(tg->ctx, address, value);
- 
- 	/********************************************************************/
--	address = tg->regs[IDX_CRTC_GSL_CONTROL];
-+	address = CRTC_REG(mmCRTC_GSL_CONTROL);
- 
- 	value = 0;
- 	set_reg_field_value(value,
-@@ -1446,7 +1365,8 @@ void dce110_timing_generator_enable_advanced_request(
- 	bool enable,
- 	const struct dc_crtc_timing *timing)
- {
--	uint32_t addr = tg->regs[IDX_CRTC_START_LINE_CONTROL];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
- 	if (enable && FROM_TIMING_GENERATOR(tg)->advanced_request_enable) {
-@@ -1507,7 +1427,8 @@ void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
- 		bool lock)
- {
- 	struct dc_context *ctx = tg->ctx;
--	uint32_t addr = tg->regs[IDX_CRTC_MASTER_UPDATE_LOCK];
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
-@@ -1528,6 +1449,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 	uint32_t rising_edge = 0;
- 	uint32_t falling_edge = 0;
- 	enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
- 	/* Setup trigger edge */
- 	switch (trigger_params->edge) {
-@@ -1535,7 +1457,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 	case TRIGGER_EDGE_DEFAULT:
- 		{
- 			uint32_t pol_value = dal_read_reg(tg->ctx,
--					tg->regs[IDX_CRTC_V_SYNC_A_CNTL]);
-+					CRTC_REG(mmCRTC_V_SYNC_A_CNTL));
- 
- 			/* Register spec has reversed definition:
- 			 *	0 for positive, 1 for negative */
-@@ -1563,7 +1485,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 		return;
- 	}
- 
--	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL]);
-+	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
- 
- 	switch(trigger_params->source) {
- 	/* Currently supporting only a single group, the group zero. */
-@@ -1610,11 +1532,11 @@ void dce110_timing_generator_enable_reset_trigger(
- 			CRTC_TRIGB_CNTL,
- 			CRTC_TRIGB_CLEAR);
- 
--	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL], value);
-+	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
- 
- 	/**************************************************************/
- 
--	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL]);
-+	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
- 	set_reg_field_value(value,
- 			2, /* force H count to H_TOTAL and V count to V_TOTAL */
-@@ -1631,15 +1553,16 @@ void dce110_timing_generator_enable_reset_trigger(
- 			CRTC_FORCE_COUNT_NOW_CNTL,
- 			CRTC_FORCE_COUNT_NOW_CLEAR);
- 
--	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL], value);
-+	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
- }
- 
- void dce110_timing_generator_disable_reset_trigger(
- 	struct timing_generator *tg)
- {
- 	uint32_t value;
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 
--	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL]);
-+	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
- 	set_reg_field_value(value,
- 			0, /* force counter now mode is disabled */
-@@ -1651,10 +1574,10 @@ void dce110_timing_generator_disable_reset_trigger(
- 			CRTC_FORCE_COUNT_NOW_CNTL,
- 			CRTC_FORCE_COUNT_NOW_CLEAR);
- 
--	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL], value);
-+	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
- 
- 	/********************************************************************/
--	value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL]);
-+	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
- 
- 	set_reg_field_value(value,
- 			TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
-@@ -1671,7 +1594,7 @@ void dce110_timing_generator_disable_reset_trigger(
- 			CRTC_TRIGB_CNTL,
- 			CRTC_TRIGB_CLEAR);
- 
--	dal_write_reg(tg->ctx, tg->regs[IDX_CRTC_TRIGB_CNTL], value);
-+	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
- }
- 
- /**
-@@ -1686,7 +1609,9 @@ void dce110_timing_generator_disable_reset_trigger(
- bool dce110_timing_generator_did_triggered_reset_occur(
- 	struct timing_generator *tg)
- {
--	uint32_t value = dal_read_reg(tg->ctx, tg->regs[IDX_CRTC_FORCE_COUNT_CNTL]);
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	uint32_t value = dal_read_reg(tg->ctx,
-+			CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
- 	return get_reg_field_value(value,
- 			CRTC_FORCE_COUNT_NOW_CNTL,
-@@ -1744,7 +1669,7 @@ void dce110_timing_generator_set_overscan_color_black(
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
- 	uint32_t addr;
--
-+	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
- 	/* Overscan Color for YUV display modes:
- 	 * to achieve a black color for both the explicit and implicit overscan,
- 	 * the overscan color registers should be programmed to: */
-@@ -1842,15 +1767,15 @@ void dce110_timing_generator_set_overscan_color_black(
- 		/* default is sRGB black 0. */
- 		break;
- 	}
--	addr = tg->regs[IDX_CRTC_OVERSCAN_COLOR];
-+	addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR);
- 	dal_write_reg(ctx, addr, value);
--	addr = tg->regs[IDX_CRTC_BLACK_COLOR];
-+	addr = CRTC_REG(mmCRTC_BLACK_COLOR);
- 	dal_write_reg(ctx, addr, value);
- 	/* This is desirable to have a constant DAC output voltage during the
- 	 * blank time that is higher than the 0 volt reference level that the
- 	 * DAC outputs when the NBLANK signal
- 	 * is asserted low, such as for output to an analog TV. */
--	addr = tg->regs[IDX_CRTC_BLANK_DATA_COLOR];
-+	addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR);
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* TO DO we have to program EXT registers and we need to know LB DATA
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index c75c659..c4a815f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -50,8 +50,14 @@
- #define CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_RGB_LIMITED_RANGE 0x40
- #define CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_RGB_LIMITED_RANGE 0X40
- 
-+struct dce110_timing_generator_offsets {
-+	uint32_t crtc;
-+	uint32_t dcp;
-+};
-+
- struct dce110_timing_generator {
- 	struct timing_generator base;
-+	struct dce110_timing_generator_offsets offsets;
- 	enum sync_source cached_gsl_group;
- 	bool advanced_request_enable;
- };
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-index 9c4d92d..bc04acd 100644
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-@@ -135,7 +135,6 @@ enum controller_dp_test_pattern {
- };
- 
- struct timing_generator {
--	uint32_t *regs;
- 	struct bios_parser *bp;
- 	enum controller_id controller_id;
- 	struct dc_context *ctx;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0651-drm-amd-dal-remove-mst-semaphore.patch b/common/recipes-kernel/linux/files/0651-drm-amd-dal-remove-mst-semaphore.patch
deleted file mode 100644
index 43565b02..00000000
--- a/common/recipes-kernel/linux/files/0651-drm-amd-dal-remove-mst-semaphore.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 653684ef3e912682ec10babaa5e080439b55cc9e Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 18 Dec 2015 18:46:32 +0800
-Subject: [PATCH 0651/1110] drm/amd/dal: remove mst semaphore
-
-After fix applied to userspace we do not need
-to defer connectors destruction and so can remove
-mst semaphore usage
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  3 ---
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 23 ----------------------
- 2 files changed, 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index e765f57..d47ec32 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -333,9 +333,6 @@ static void dm_dp_destroy_mst_connector(
- 	struct drm_device *dev = master->base.dev;
- 	struct amdgpu_device *adev = dev->dev_private;
- 
--	/* wait until reset mode occur */
--	down(&aconnector->mst_sem);
--
- 	drm_connector_unregister(connector);
- 	/* need to nuke the connector */
- 	drm_modeset_lock_all(dev);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 492939e..00a0139 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1804,8 +1804,6 @@ void amdgpu_dm_connector_init_helper(
- 	drm_object_attach_property(&aconnector->base.base,
- 				adev->mode_info.underscan_vborder_property,
- 				0);
--
--	sema_init(&aconnector->mst_sem, 1);
- }
- 
- /* Note: this function assumes that dc_link_detect() was called for the
-@@ -2074,25 +2072,6 @@ static void handle_headless_hotplug(
- 	}
- }
- 
--static void update_connector_sem_state(struct drm_atomic_state *state)
--{
--	struct drm_connector *connector;
--	struct drm_connector_state *old_con_state;
--	struct amdgpu_connector *aconnector = NULL;
--	int i;
--
--	for_each_connector_in_state(state, connector, old_con_state, i) {
--		aconnector = to_amdgpu_connector(connector);
--		if (old_con_state->crtc) {
--			if (!connector->state->crtc)
--				up(&aconnector->mst_sem);
--		} else {
--			if (connector->state->crtc)
--				down(&aconnector->mst_sem);
--		}
--	}
--}
--
- int amdgpu_dm_atomic_commit(
- 	struct drm_device *dev,
- 	struct drm_atomic_state *state,
-@@ -2251,8 +2230,6 @@ int amdgpu_dm_atomic_commit(
- 	/* DC is optimized not to do anything if 'targets' didn't change. */
- 	dc_commit_targets(dm->dc, commit_targets, commit_targets_count);
- 
--	update_connector_sem_state(state);
--
- 	/* update planes when needed */
- 	for_each_plane_in_state(state, plane, old_plane_state, i) {
- 		struct drm_plane_state *plane_state = plane->state;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0652-drm-amd-dal-Start-Stop-MST-Topology-only-for-root-co.patch b/common/recipes-kernel/linux/files/0652-drm-amd-dal-Start-Stop-MST-Topology-only-for-root-co.patch
deleted file mode 100644
index b38985ee..00000000
--- a/common/recipes-kernel/linux/files/0652-drm-amd-dal-Start-Stop-MST-Topology-only-for-root-co.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From 05f91cf29df67de0c2d8895b1cd0099f17febc0a Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Tue, 29 Dec 2015 14:40:40 -0500
-Subject: [PATCH 0652/1110] drm/amd/dal: Start/Stop MST Topology only for
- 'root' connector.
-
-drm_dp_mst_topology_mgr_set_mst() should be called only for the
-phisycal 'aconnector' - to start/stop MST Topology Manager in it.
-The dynamically-created 'aconnectors' are handled by DRM MST and
-we should not start/stop anything in them.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 38 ++++++----------------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 11 +++----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  7 +++-
- 3 files changed, 21 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index e856f0c..95a129e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -471,30 +471,6 @@ void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- 	}
- }
- 
--/* Depending on Root connector state, update MST state of all connectors
-- * belonging to it. */
--static void set_mst_topology_state(struct drm_device *dev)
--{
--	struct drm_connector *connector;
--	struct amdgpu_connector *aconnector = NULL;
--
--	mutex_lock(&dev->mode_config.mutex);
--
--	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--		mutex_unlock(&dev->mode_config.mutex);
--
--		aconnector = to_amdgpu_connector(connector);
--
--		if (aconnector->is_mst_connector)
--			drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr,
--					aconnector->is_mst_connector);
--
--		mutex_lock(&dev->mode_config.mutex);
--	}
--
--	mutex_unlock(&dev->mode_config.mutex);
--}
--
- bool dc_helpers_dp_mst_start_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link)
-@@ -503,8 +479,11 @@ bool dc_helpers_dp_mst_start_top_mgr(
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
--	aconnector->is_mst_connector = true;
--	set_mst_topology_state(dev);
-+	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
-+			aconnector, aconnector->base.base.id);
-+
-+	drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
-+
- 	return true;
- }
- 
-@@ -516,8 +495,11 @@ void dc_helpers_dp_mst_stop_top_mgr(
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
--	aconnector->is_mst_connector = false;
--	set_mst_topology_state(dev);
-+	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
-+			aconnector, aconnector->base.base.id);
-+
-+	if (aconnector->mst_mgr.mst_state == true)
-+		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
- }
- 
- bool dc_helper_dp_read_dpcd(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 62df355..d472a17 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -734,12 +734,11 @@ void amdgpu_dm_update_connector_after_detect(
- 	const struct dc_sink *sink;
- 
- 	/* MST handled by drm_mst framework */
--	if (aconnector->is_mst_connector)
-+	if (aconnector->mst_mgr.mst_state == true)
- 		return;
- 
--	if (!dm_get_sink_from_link(dc_link, aconnector, &sink)) {
-+	if (!dm_get_sink_from_link(dc_link, aconnector, &sink))
- 		return;
--	}
- 
- 	/*
- 	 * TODO: temporary guard to look for proper fix
-@@ -801,18 +800,18 @@ static void handle_hpd_rx_irq(void *param)
- 	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
-+	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
- 
- 	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) &&
--			!aconnector->is_mst_connector) {
-+			!is_mst_root_connector) {
- 		/* Downstream Port status changed. */
- 		dc_link_detect(aconnector->dc_link);
- 		amdgpu_dm_update_connector_after_detect(aconnector);
- 		drm_kms_helper_hotplug_event(dev);
- 	}
- 
--	if (aconnector->is_mst_connector) {
-+	if (is_mst_root_connector)
- 		dc_helpers_dp_mst_handle_mst_hpd_rx_irq(param);
--	}
- }
- 
- static void register_hpd_handlers(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index d47ec32..f976409 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -274,7 +274,6 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	if (!aconnector)
- 		return NULL;
- 
--	aconnector->is_mst_connector = true;
- 	connector = &aconnector->base;
- 	aconnector->port = port;
- 	aconnector->mst_port = master;
-@@ -318,6 +317,9 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	 */
- 	amdgpu_dm_connector_funcs_reset(connector);
- 
-+	DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
-+			aconnector, connector->base.id, aconnector->mst_port);
-+
- 	DRM_DEBUG_KMS(":%d\n", connector->base.id);
- 
- 	return connector;
-@@ -333,6 +335,9 @@ static void dm_dp_destroy_mst_connector(
- 	struct drm_device *dev = master->base.dev;
- 	struct amdgpu_device *adev = dev->dev_private;
- 
-+	DRM_INFO("DM_MST: destroying connector: %p [id: %d] [master: %p]\n",
-+			aconnector, connector->base.id, aconnector->mst_port);
-+
- 	drm_connector_unregister(connector);
- 	/* need to nuke the connector */
- 	drm_modeset_lock_all(dev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0653-drm-amd-dal-Skip-unrelated-MST-connectors-in-payload.patch b/common/recipes-kernel/linux/files/0653-drm-amd-dal-Skip-unrelated-MST-connectors-in-payload.patch
deleted file mode 100644
index c7a246fa..00000000
--- a/common/recipes-kernel/linux/files/0653-drm-amd-dal-Skip-unrelated-MST-connectors-in-payload.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 79420fd2deba83ee02425411bfe1ecf908bc29f5 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Wed, 30 Dec 2015 11:14:42 -0500
-Subject: [PATCH 0653/1110] drm/amd/dal: Skip unrelated MST connectors in
- payload allocation.
-
-Skip MST connectors belonging to other 'root' connectors during payload allocation.
-This fixes multi-MST configuration light-up.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 95a129e..744ab94 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -177,6 +177,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	struct drm_crtc *crtc;
- 	struct drm_dp_mst_topology_mgr *mst_mgr;
- 	struct drm_dp_mst_port *mst_port;
-+	struct amdgpu_connector *master_port;
- 	int slots = 0;
- 	bool ret;
- 	int clock;
-@@ -191,7 +192,8 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	if (!aconnector->mst_port)
- 		return false;
- 
--	mst_mgr = &aconnector->mst_port->mst_mgr;
-+	master_port = aconnector->mst_port;
-+	mst_mgr = &master_port->mst_mgr;
- 
- 	if (!mst_mgr->mst_state)
- 		return false;
-@@ -300,6 +302,11 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 			if (!aconnector->mst_port)
- 				continue;
- 
-+			if (master_port != aconnector->mst_port) {
-+				/* Not the same physical connector. */
-+				continue;
-+			}
-+
- 			mst_port = aconnector->port;
- 
- 			if (mst_port->vcpi.vcpi !=
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0654-drm-amd-dal-Fixed-DVI-passive-dongle-not-lightup-iss.patch b/common/recipes-kernel/linux/files/0654-drm-amd-dal-Fixed-DVI-passive-dongle-not-lightup-iss.patch
deleted file mode 100644
index 43d6b78b..00000000
--- a/common/recipes-kernel/linux/files/0654-drm-amd-dal-Fixed-DVI-passive-dongle-not-lightup-iss.patch
+++ /dev/null
@@ -1,178 +0,0 @@
-From 722aac86197d621d2b8a2db2ffcf21c4e464c3a1 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 30 Dec 2015 10:27:05 -0500
-Subject: [PATCH 0654/1110] drm/amd/dal: Fixed DVI passive dongle not lightup
- issue.
-
-In case of HDMI or DVI, combined two callback to one.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 20 +++-----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  2 -
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 53 +++++-----------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    | 10 +---
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  8 +---
- 5 files changed, 22 insertions(+), 71 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 646706e..2211f38 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1009,19 +1009,13 @@ static void enable_link_hdmi(struct core_stream *stream)
- 	dc_service_memset(&stream->sink->link->cur_link_settings, 0,
- 			sizeof(struct link_settings));
- 
--	if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
--		link->ctx->dc->hwss.encoder_enable_dual_link_tmds_output(
--				stream->sink->link->link_enc,
--				dal_clock_source_get_id(stream->clock_source),
--				stream->public.timing.display_color_depth,
--				stream->public.timing.pix_clk_khz);
--	else
--		link->ctx->dc->hwss.encoder_enable_tmds_output(
--				stream->sink->link->link_enc,
--				dal_clock_source_get_id(stream->clock_source),
--				stream->public.timing.display_color_depth,
--				stream->public.timing.pix_clk_khz);
--
-+	link->ctx->dc->hwss.encoder_enable_tmds_output(
-+			stream->sink->link->link_enc,
-+			dal_clock_source_get_id(stream->clock_source),
-+			stream->public.timing.display_color_depth,
-+			stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
-+			stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
-+			stream->public.timing.pix_clk_khz);
- 
- 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 		dal_ddc_service_read_scdc_data(link->ddc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index a34cd6d..b71f7e7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1727,8 +1727,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.encoder_destroy = dce110_link_encoder_destroy,
- 	.encoder_hw_init = dce110_link_encoder_hw_init,
- 	.encoder_enable_tmds_output = dce110_link_encoder_enable_tmds_output,
--	.encoder_enable_dual_link_tmds_output =
--			dce110_link_encoder_enable_dual_link_tmds_output,
- 	.encoder_enable_dp_output = dce110_link_encoder_enable_dp_output,
- 	.encoder_enable_dp_mst_output =
- 			dce110_link_encoder_enable_dp_mst_output,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index a2dd6ed..deaf94d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1386,6 +1386,8 @@ void dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
- 	uint32_t pixel_clock)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-@@ -1399,49 +1401,16 @@ void dce110_link_encoder_enable_tmds_output(
- 	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
--	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
--	cntl.lanes_number = 4;
--	cntl.hpd_sel = enc110->base.hpd_source;
--
--	cntl.pixel_clock = pixel_clock;
--	cntl.color_depth = color_depth;
--
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service),
--		&cntl);
--
--	if (result != BP_RESULT_OK) {
--		dal_logger_write(ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_ENCODER,
--			"%s: Failed to execute VBIOS command table!\n",
--			__func__);
--		BREAK_TO_DEBUGGER();
-+	if (hdmi) {
-+		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+		cntl.lanes_number = 4;
-+	} else if (dual_link) {
-+		cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		cntl.lanes_number = 8;
-+	} else {
-+		cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		cntl.lanes_number = 4;
- 	}
--}
--
--/* enables TMDS PHY output */
--/* TODO: still need this or just pass in adjusted pixel clock? */
--void dce110_link_encoder_enable_dual_link_tmds_output(
--	struct link_encoder *enc,
--	enum clock_source_id clock_source,
--	enum dc_color_depth color_depth,
--	uint32_t pixel_clock)
--{
--	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
--	struct dc_context *ctx = enc110->base.ctx;
--	struct bp_transmitter_control cntl = { 0 };
--	enum bp_result result;
--
--	/* Enable the PHY */
--
--	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = ENGINE_ID_UNKNOWN;
--	cntl.transmitter = enc110->base.transmitter;
--	cntl.pll_id = clock_source;
--	cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
--	cntl.lanes_number = 8;
- 	cntl.hpd_sel = enc110->base.hpd_source;
- 
- 	cntl.pixel_clock = pixel_clock;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index c5b16f6..156cdc8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -67,14 +67,8 @@ void dce110_link_encoder_enable_tmds_output(
- 	struct link_encoder *enc,
- 	enum clock_source_id clock_source,
- 	enum dc_color_depth color_depth,
--	uint32_t pixel_clock);
--
--/* enables TMDS PHY output */
--/* TODO: still need this or just pass in adjusted pixel clock? */
--void dce110_link_encoder_enable_dual_link_tmds_output(
--	struct link_encoder *enc,
--	enum clock_source_id clock_source,
--	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
- 	uint32_t pixel_clock);
- 
- /* enables DP PHY output */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 50af714..317110e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -98,12 +98,8 @@ struct hw_sequencer_funcs {
- 					struct link_encoder *enc,
- 					enum clock_source_id clock_source,
- 					enum dc_color_depth color_depth,
--					uint32_t pixel_clock);
--
--	void (*encoder_enable_dual_link_tmds_output)(
--					struct link_encoder *enc,
--					enum clock_source_id clock_source,
--					enum dc_color_depth color_depth,
-+					bool hdmi,
-+					bool dual_link,
- 					uint32_t pixel_clock);
- 
- 	void (*encoder_enable_dp_output)(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0655-drm-amd-dal-Guard-against-seg-fault-when-register-co.patch b/common/recipes-kernel/linux/files/0655-drm-amd-dal-Guard-against-seg-fault-when-register-co.patch
deleted file mode 100644
index d4b9e1f5..00000000
--- a/common/recipes-kernel/linux/files/0655-drm-amd-dal-Guard-against-seg-fault-when-register-co.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 522ba5e07873da08707873583df040aed9b3af17 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 30 Dec 2015 14:27:55 -0500
-Subject: [PATCH 0655/1110] drm/amd/dal: Guard against seg fault when register
- connector before fbdev init
-
-Registration of MST connectors happen on workqueue, if it is scheduled before we hit
-fbdev init, we will segfault. Simply check for NULL inside the critical region will
-resolve this, since the fbdev init function will add missing connectors anyway.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index f976409..e7b675e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -371,7 +371,11 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector)
- 	struct amdgpu_device *adev = dev->dev_private;
- 
- 	drm_modeset_lock_all(dev);
--	drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
-+	if (adev->mode_info.rfbdev)
-+		drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
-+	else
-+		DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
-+
- 	drm_modeset_unlock_all(dev);
- 
- 	drm_connector_register(connector);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0656-drm-amd-dal-Fix-bug-when-cleaning-up-dc-ctx.patch b/common/recipes-kernel/linux/files/0656-drm-amd-dal-Fix-bug-when-cleaning-up-dc-ctx.patch
deleted file mode 100644
index 1949d45d..00000000
--- a/common/recipes-kernel/linux/files/0656-drm-amd-dal-Fix-bug-when-cleaning-up-dc-ctx.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From d7dd25a26d67bdae8d1e43240151fdce4395a427 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Mon, 4 Jan 2016 16:42:22 -0500
-Subject: [PATCH 0656/1110] drm/amd/dal: Fix bug when cleaning up dc->ctx
-
-Since free dc clears the memory block for dc including dc->ctx, no need to clear dc->ctx again.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index df243c2..ea31bc6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -402,7 +402,6 @@ void dc_destroy(struct dc **dc)
- {
- 	destruct(*dc);
- 	dc_service_free((*dc)->ctx, *dc);
--	dc_service_free((*dc)->ctx, (*dc)->ctx);
- 	*dc = NULL;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0657-drm-amd-dal-underscan-test-corruption-fix.patch b/common/recipes-kernel/linux/files/0657-drm-amd-dal-underscan-test-corruption-fix.patch
deleted file mode 100644
index 052fe74e..00000000
--- a/common/recipes-kernel/linux/files/0657-drm-amd-dal-underscan-test-corruption-fix.patch
+++ /dev/null
@@ -1,362 +0,0 @@
-From bbd79287d0d9e85c690cf512ef4eda8ad55e7d97 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 4 Jan 2016 17:41:42 -0500
-Subject: [PATCH 0657/1110] drm/amd/dal: underscan test corruption fix
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c          | 119 -------------------------
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 121 ++++++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c   |  13 ++-
- drivers/gpu/drm/amd/dal/dc/inc/resource.h     |   7 ++
- 4 files changed, 139 insertions(+), 121 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index ea31bc6..662df13 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -40,7 +40,6 @@
- #include "include/irq_service_interface.h"
- 
- #include "link_hwss.h"
--#include "opp.h"
- #include "link_encoder.h"
- 
- #include "dcs/ddc_service.h"
-@@ -224,8 +223,6 @@ static struct adapter_service *create_as(
- 	return as;
- }
- 
--/* TODO unhardcode, 4 for CZ*/
--#define MEMORY_TYPE_MULTIPLIER 4
- static void bw_calcs_data_update_from_pplib(struct dc *dc)
- {
- 	struct dc_pp_clock_levels clks = {0};
-@@ -490,122 +487,6 @@ static bool targets_changed(
- 	return false;
- }
- 
--static uint32_t get_min_vblank_time_us(const struct validate_context* context)
--{
--	uint8_t i, j;
--	uint32_t min_vertical_blank_time = -1;
--	for (i = 0; i < context->target_count; i++) {
--		const struct core_target* target = context->targets[i];
--		for (j = 0; j < target->public.stream_count; j++) {
--			const struct dc_stream* stream =
--						target->public.streams[j];
--			uint32_t vertical_blank_in_pixels = 0;
--			uint32_t vertical_blank_time = 0;
--			vertical_blank_in_pixels = stream->timing.h_total *
--				(stream->timing.v_total
--					- stream->timing.v_addressable);
--			vertical_blank_time = vertical_blank_in_pixels
--				* 1000 / stream->timing.pix_clk_khz;
--			if (min_vertical_blank_time > vertical_blank_time)
--				min_vertical_blank_time = vertical_blank_time;
--		}
--	}
--	return min_vertical_blank_time;
--}
--
--static void fill_display_configs(
--	const struct validate_context* context,
--	struct dc_pp_display_configuration *pp_display_cfg)
--{
--	uint8_t i, j;
--	uint8_t num_cfgs = 0;
--
--	for (i = 0; i < context->target_count; i++) {
--		const struct core_target* target = context->targets[i];
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			const struct core_stream *stream =
--			DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct dc_pp_single_disp_config *cfg =
--					&pp_display_cfg->disp_configs[num_cfgs];
--
--			num_cfgs++;
--			cfg->signal = stream->signal;
--			cfg->pipe_idx = stream->opp->inst;
--			cfg->src_height = stream->public.src.height;
--			cfg->src_width = stream->public.src.width;
--			cfg->ddi_channel_mapping =
--				stream->sink->link->ddi_channel_mapping.raw;
--			cfg->transmitter =
--				stream->sink->link->link_enc->transmitter;
--			cfg->link_settings =
--					stream->sink->link->cur_link_settings;
--			cfg->sym_clock = stream->public.timing.pix_clk_khz;
--			switch (stream->public.timing.display_color_depth) {
--			case COLOR_DEPTH_101010:
--				cfg->sym_clock = (cfg->sym_clock * 30) / 24;
--				break;
--			case COLOR_DEPTH_121212:
--				cfg->sym_clock = (cfg->sym_clock * 36) / 24;
--				break;
--			case COLOR_DEPTH_161616:
--				cfg->sym_clock = (cfg->sym_clock * 48) / 24;
--				break;
--			default:
--				break;
--			}
--			/* TODO: unhardcode*/
--			cfg->v_refresh = 60;
--		}
--	}
--	pp_display_cfg->display_count = num_cfgs;
--}
--
--static void pplib_apply_display_requirements(
--	const struct dc *dc,
--	const struct validate_context *context)
--{
--	struct dc_pp_display_configuration pp_display_cfg = { 0 };
--
--	pp_display_cfg.all_displays_in_sync =
--		context->bw_results.all_displays_in_sync;
--	pp_display_cfg.nb_pstate_switch_disable =
--			context->bw_results.nbp_state_change_enable == false;
--	pp_display_cfg.cpu_cc6_disable =
--			context->bw_results.cpuc_state_change_enable == false;
--	pp_display_cfg.cpu_pstate_disable =
--			context->bw_results.cpup_state_change_enable == false;
--	pp_display_cfg.cpu_pstate_separation_time =
--			context->bw_results.required_blackout_duration_us;
--
--	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk
--		/ MEMORY_TYPE_MULTIPLIER;
--	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
--	pp_display_cfg.min_engine_clock_deep_sleep_khz
--			= context->bw_results.required_sclk_deep_sleep;
--
--	pp_display_cfg.avail_mclk_switch_time_us =
--						get_min_vblank_time_us(context);
--	/* TODO: dce11.2*/
--	pp_display_cfg.avail_mclk_switch_time_in_disp_active_us = 0;
--
--	pp_display_cfg.disp_clk_khz = context->bw_results.dispclk_khz;
--
--	fill_display_configs(context, &pp_display_cfg);
--
--	/* TODO: is this still applicable?*/
--	if (pp_display_cfg.display_count == 1) {
--		const struct dc_crtc_timing *timing =
--			&context->targets[0]->public.streams[0]->timing;
--		pp_display_cfg.crtc_index =
--			pp_display_cfg.disp_configs[0].pipe_idx;
--		pp_display_cfg.line_time_in_us = timing->h_total * 1000
--							/ timing->pix_clk_khz;
--	}
--
--	dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
--}
--
- bool dc_commit_targets(
- 	struct dc *dc,
- 	struct dc_target *targets[],
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index ef13968..ab081c1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -28,6 +28,7 @@
- #include "include/irq_service_interface.h"
- #include "link_encoder.h"
- #include "stream_encoder.h"
-+#include "opp.h"
- 
- 
- void unreference_clock_source(
-@@ -405,3 +406,123 @@ bool logical_attach_surfaces_to_target(
- 
- 	return true;
- }
-+
-+static uint32_t get_min_vblank_time_us(const struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	uint32_t min_vertical_blank_time = -1;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		const struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct dc_stream *stream =
-+						target->public.streams[j];
-+			uint32_t vertical_blank_in_pixels = 0;
-+			uint32_t vertical_blank_time = 0;
-+
-+			vertical_blank_in_pixels = stream->timing.h_total *
-+				(stream->timing.v_total
-+					- stream->timing.v_addressable);
-+			vertical_blank_time = vertical_blank_in_pixels
-+				* 1000 / stream->timing.pix_clk_khz;
-+			if (min_vertical_blank_time > vertical_blank_time)
-+				min_vertical_blank_time = vertical_blank_time;
-+		}
-+	}
-+	return min_vertical_blank_time;
-+}
-+
-+static void fill_display_configs(
-+	const struct validate_context *context,
-+	struct dc_pp_display_configuration *pp_display_cfg)
-+{
-+	uint8_t i, j;
-+	uint8_t num_cfgs = 0;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		const struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct core_stream *stream =
-+			DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct dc_pp_single_disp_config *cfg =
-+					&pp_display_cfg->disp_configs[num_cfgs];
-+
-+			num_cfgs++;
-+			cfg->signal = stream->signal;
-+			cfg->pipe_idx = stream->opp->inst;
-+			cfg->src_height = stream->public.src.height;
-+			cfg->src_width = stream->public.src.width;
-+			cfg->ddi_channel_mapping =
-+				stream->sink->link->ddi_channel_mapping.raw;
-+			cfg->transmitter =
-+				stream->sink->link->link_enc->transmitter;
-+			cfg->link_settings =
-+					stream->sink->link->cur_link_settings;
-+			cfg->sym_clock = stream->public.timing.pix_clk_khz;
-+			switch (stream->public.timing.display_color_depth) {
-+			case COLOR_DEPTH_101010:
-+				cfg->sym_clock = (cfg->sym_clock * 30) / 24;
-+				break;
-+			case COLOR_DEPTH_121212:
-+				cfg->sym_clock = (cfg->sym_clock * 36) / 24;
-+				break;
-+			case COLOR_DEPTH_161616:
-+				cfg->sym_clock = (cfg->sym_clock * 48) / 24;
-+				break;
-+			default:
-+				break;
-+			}
-+			/* TODO: unhardcode*/
-+			cfg->v_refresh = 60;
-+		}
-+	}
-+	pp_display_cfg->display_count = num_cfgs;
-+}
-+
-+void pplib_apply_display_requirements(
-+	const struct dc *dc,
-+	const struct validate_context *context)
-+{
-+	struct dc_pp_display_configuration pp_display_cfg = { 0 };
-+
-+	pp_display_cfg.all_displays_in_sync =
-+		context->bw_results.all_displays_in_sync;
-+	pp_display_cfg.nb_pstate_switch_disable =
-+			context->bw_results.nbp_state_change_enable == false;
-+	pp_display_cfg.cpu_cc6_disable =
-+			context->bw_results.cpuc_state_change_enable == false;
-+	pp_display_cfg.cpu_pstate_disable =
-+			context->bw_results.cpup_state_change_enable == false;
-+	pp_display_cfg.cpu_pstate_separation_time =
-+			context->bw_results.required_blackout_duration_us;
-+
-+	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk
-+		/ MEMORY_TYPE_MULTIPLIER;
-+	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
-+	pp_display_cfg.min_engine_clock_deep_sleep_khz
-+			= context->bw_results.required_sclk_deep_sleep;
-+
-+	pp_display_cfg.avail_mclk_switch_time_us =
-+						get_min_vblank_time_us(context);
-+	/* TODO: dce11.2*/
-+	pp_display_cfg.avail_mclk_switch_time_in_disp_active_us = 0;
-+
-+	pp_display_cfg.disp_clk_khz = context->bw_results.dispclk_khz;
-+
-+	fill_display_configs(context, &pp_display_cfg);
-+
-+	/* TODO: is this still applicable?*/
-+	if (pp_display_cfg.display_count == 1) {
-+		const struct dc_crtc_timing *timing =
-+			&context->targets[0]->public.streams[0]->timing;
-+
-+		pp_display_cfg.crtc_index =
-+			pp_display_cfg.disp_configs[0].pipe_idx;
-+		pp_display_cfg.line_time_in_us = timing->h_total * 1000
-+							/ timing->pix_clk_khz;
-+	}
-+
-+	dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 3a1f605..433f712 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -200,6 +200,7 @@ bool dc_commit_surfaces_to_target(
- 
- {
- 	uint8_t i, j;
-+	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
- 
- 	bool current_enabled_surface_count = 0;
-@@ -241,7 +242,10 @@ bool dc_commit_surfaces_to_target(
- 		goto unexpected_fail;
- 	}
- 
--	dc->hwss.program_bw(dc, &dc->current_context);
-+	if (prev_disp_clk < dc->current_context.bw_results.dispclk_khz) {
-+		dc->hwss.program_bw(dc, &dc->current_context);
-+		pplib_apply_display_requirements(dc, &dc->current_context);
-+	}
- 
- 	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
- 		dc_target_disable_memory_requests(dc_target);
-@@ -267,10 +271,15 @@ bool dc_commit_surfaces_to_target(
- 
- 		dc->hwss.update_plane_address(core_surface, target);
- 	}
--
- 	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
- 		dc_target_enable_memory_requests(dc_target);
- 
-+	/* Lower display clock if necessary */
-+	if (prev_disp_clk > dc->current_context.bw_results.dispclk_khz) {
-+		dc->hwss.program_bw(dc, &dc->current_context);
-+		pplib_apply_display_requirements(dc, &dc->current_context);
-+	}
-+
- 	return true;
- 
- unexpected_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 0e0ba47..80a67c9 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -29,6 +29,9 @@
- #include "core_status.h"
- #include "core_dc.h"
- 
-+/* TODO unhardcode, 4 for CZ*/
-+#define MEMORY_TYPE_MULTIPLIER 4
-+
- void build_scaling_params(
- 	const struct dc_surface *surface,
- 	struct core_stream *stream);
-@@ -58,4 +61,8 @@ bool logical_attach_surfaces_to_target(
- 		uint8_t surface_count,
- 		struct dc_target *dc_target);
- 
-+void pplib_apply_display_requirements(
-+	const struct dc *dc,
-+	const struct validate_context *context);
-+
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0658-drm-amd-dal-add-bw_result-logging.patch b/common/recipes-kernel/linux/files/0658-drm-amd-dal-add-bw_result-logging.patch
deleted file mode 100644
index ec95e491..00000000
--- a/common/recipes-kernel/linux/files/0658-drm-amd-dal-add-bw_result-logging.patch
+++ /dev/null
@@ -1,225 +0,0 @@
-From b96d5c9da90d267519257bf183d48e3442af4dd9 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 5 Jan 2016 12:02:31 -0500
-Subject: [PATCH 0658/1110] drm/amd/dal: add bw_result logging
-
-Also fixed number of taps used for multi-sisplay config bw calculations.
-Utils part of the change fixes line endings.
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         | 18 +++--
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 92 +++++++++++++++++++---
- 3 files changed, 96 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index 5aadda7..b2bf14f 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -241,7 +241,8 @@ struct log_major_mask_info {
- 
- #define LG_SYNC_MSK (1 << LOG_MINOR_SYNC_TIMING)
- 
--#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION)
-+#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION) | \
-+		(1 << LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS)
- 
- 
- static const struct log_major_mask_info log_major_mask_info_tbl[] = {
-@@ -620,7 +621,8 @@ void dal_logger_write(
- 			/* Concatenate onto end of entry buffer */
- 			append_entry(&entry, buffer, size);
- 		} else {
--			append_entry(&entry, "LOG_ERROR\n", 12);
-+			append_entry(&entry,
-+				"LOG_ERROR, line too long or null\n", 35);
- 		}
- 
- 		dal_logger_close(&entry);
-@@ -658,7 +660,12 @@ void dal_logger_append(
- 
- 		size = dal_log_to_buffer(
- 			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
--		append_entry(entry, buffer, size);
-+
-+		if (size < DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE - 1) {
-+			append_entry(entry, buffer, size);
-+		} else {
-+			append_entry(entry, "LOG_ERROR, line too long\n", 27);
-+		}
- 
- 		va_end(args);
- 	}
-@@ -758,11 +765,10 @@ void dal_logger_open(
- 
- 	entry->buf = dc_service_alloc(
- 		logger->ctx,
--		DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char));
-+		DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char));
- 
- 	entry->buf_offset = 0;
--	entry->max_buf_bytes =
--			DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char);
-+	entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
- 
- 	logger->open_count++;
- 	entry->major = major;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index b71f7e7..fa6b9b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1286,7 +1286,9 @@ static enum dc_status apply_ctx_to_hw(
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
--	set_display_clock(context);
-+	if (context->bw_results.dispclk_khz
-+		> dc->current_context.bw_results.dispclk_khz)
-+		set_display_clock(context);
- 
- 	for (i = 0; i < pool->controller_count; i++) {
- 		struct controller_ctx *ctlr_ctx
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 0e38513..cb084da 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -489,6 +489,8 @@ enum dc_status dce110_validate_bandwidth(
- 	uint8_t i, j;
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	uint8_t number_of_displays = 0;
-+	uint8_t max_htaps = 1;
-+	uint8_t max_vtaps = 1;
- 	bool all_displays_in_sync = true;
- 	struct dc_crtc_timing prev_timing;
- 
-@@ -504,8 +506,16 @@ enum dc_status dce110_validate_bandwidth(
- 
- 			if (target->status.surface_count == 0) {
- 				disp->graphics_scale_ratio = bw_int_to_fixed(1);
--				disp->graphics_h_taps = 4;
--				disp->graphics_v_taps = 4;
-+				disp->graphics_h_taps = 2;
-+				disp->graphics_v_taps = 2;
-+
-+				/* TODO: remove when bw formula accepts taps per
-+				 * display
-+				 */
-+				if (max_vtaps < 2)
-+					max_vtaps = 2;
-+				if (max_htaps < 2)
-+					max_htaps = 2;
- 
- 			} else {
- 				disp->graphics_scale_ratio =
-@@ -513,6 +523,14 @@ enum dc_status dce110_validate_bandwidth(
- 						stream->ratios.vert.value);
- 				disp->graphics_h_taps = stream->taps.h_taps;
- 				disp->graphics_v_taps = stream->taps.v_taps;
-+
-+				/* TODO: remove when bw formula accepts taps per
-+				 * display
-+				 */
-+				if (max_vtaps < stream->taps.v_taps)
-+					max_vtaps = stream->taps.v_taps;
-+				if (max_htaps < stream->taps.h_taps)
-+					max_htaps = stream->taps.h_taps;
- 			}
- 
- 			disp->graphics_src_width =
-@@ -550,15 +568,23 @@ enum dc_status dce110_validate_bandwidth(
- 		}
- 	}
- 
-+	/* TODO: remove when bw formula accepts taps per
-+	 * display
-+	 */
-+	context->bw_mode_data.displays_data[0].graphics_v_taps = max_vtaps;
-+	context->bw_mode_data.displays_data[0].graphics_h_taps = max_htaps;
-+
- 	context->bw_mode_data.number_of_displays = number_of_displays;
- 	context->bw_mode_data.display_synchronization_enabled =
- 							all_displays_in_sync;
- 
--	dal_logger_write(dc->ctx->logger,
-+	dal_logger_write(
-+		dc->ctx->logger,
- 		LOG_MAJOR_BWM,
- 		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
--		"%s: Start bandwidth calculations",
-+		"%s: start",
- 		__func__);
-+
- 	if (!bw_calcs(
- 			dc->ctx,
- 			&dc->bw_dceip,
-@@ -576,13 +602,57 @@ enum dc_status dce110_validate_bandwidth(
- 			"%s: Bandwidth validation failed!",
- 			__func__);
- 
--	dal_logger_write(dc->ctx->logger,
--		LOG_MAJOR_BWM,
--		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
--		"%s: Finish bandwidth calculations\n nbpMark: %d",
--		__func__,
--		context->bw_results.nbp_state_change_wm_ns[0].b_mark);
--
-+	if (dal_memcmp(&dc->current_context.bw_results,
-+			&context->bw_results, sizeof(context->bw_results))) {
-+		struct log_entry log_entry;
-+		dal_logger_open(
-+			dc->ctx->logger,
-+			&log_entry,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
-+		dal_logger_append(&log_entry, "%s: finish, numDisplays: %d\n"
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			__func__, number_of_displays,
-+			context->bw_results.nbp_state_change_wm_ns[0].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[0].a_mark,
-+			context->bw_results.urgent_wm_ns[0].b_mark,
-+			context->bw_results.urgent_wm_ns[0].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[1].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[1].a_mark,
-+			context->bw_results.urgent_wm_ns[1].b_mark,
-+			context->bw_results.urgent_wm_ns[1].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[2].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[2].a_mark,
-+			context->bw_results.urgent_wm_ns[2].b_mark,
-+			context->bw_results.urgent_wm_ns[2].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].a_mark,
-+			context->bw_results.stutter_mode_enable);
-+		dal_logger_append(&log_entry,
-+			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
-+			"sclk: %d sclk_sleep: %d yclk: %d blackout_duration: %d\n",
-+			context->bw_results.cpuc_state_change_enable,
-+			context->bw_results.cpup_state_change_enable,
-+			context->bw_results.nbp_state_change_enable,
-+			context->bw_results.all_displays_in_sync,
-+			context->bw_results.dispclk_khz,
-+			context->bw_results.required_sclk,
-+			context->bw_results.required_sclk_deep_sleep,
-+			context->bw_results.required_yclk,
-+			context->bw_results.required_blackout_duration_us);
-+		dal_logger_close(&log_entry);
-+	}
- 	return result;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0659-drm-amd-dal-Guard-ASIC-specific-functions-in-display.patch b/common/recipes-kernel/linux/files/0659-drm-amd-dal-Guard-ASIC-specific-functions-in-display.patch
deleted file mode 100644
index a03e1815..00000000
--- a/common/recipes-kernel/linux/files/0659-drm-amd-dal-Guard-ASIC-specific-functions-in-display.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 7cd46365573adc9fc6f6d1f0207f1fe3c720b846 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 18 Dec 2015 11:06:05 -0500
-Subject: [PATCH 0659/1110] drm/amd/dal: Guard ASIC specific functions in
- display_clock header
-
-Guarding unguarded ASIC specific function headers in
-display_clock_interface.h. These should probably be
-moved to ASIC specific files.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/include/display_clock_interface.h | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index 2f48b8a..f3a1cee 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -132,13 +132,17 @@ struct display_clock_state {
- 
- struct display_clock;
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- struct display_clock *dal_display_clock_dce110_create(
- 	struct dc_context *ctx,
- 	struct adapter_service *as);
-+#endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
- struct display_clock *dal_display_clock_dce80_create(
- 	struct dc_context *ctx,
- 	struct adapter_service *as);
-+#endif
- 
- void dal_display_clock_destroy(struct display_clock **to_destroy);
- bool dal_display_clock_validate(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0660-drm-amd-dal-Remove-connector.patch b/common/recipes-kernel/linux/files/0660-drm-amd-dal-Remove-connector.patch
deleted file mode 100644
index 4255fbfe..00000000
--- a/common/recipes-kernel/linux/files/0660-drm-amd-dal-Remove-connector.patch
+++ /dev/null
@@ -1,1170 +0,0 @@
-From 4a73a01e394537a888a0842062d3c5f0eef5ddd6 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 17 Dec 2015 22:14:58 -0500
-Subject: [PATCH 0660/1110] drm/amd/dal: Remove connector
-
-We're programming hpd filter but no hpd polling.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |   2 +-
- drivers/gpu/drm/amd/dal/dc/connector/Makefile      |  10 -
- drivers/gpu/drm/amd/dal/dc/connector/connector.h   |  39 --
- .../gpu/drm/amd/dal/dc/connector/connector_base.c  | 421 ---------------------
- .../drm/amd/dal/dc/connector/connector_signals.c   | 238 ------------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 188 +++++++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       |   1 -
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |   1 -
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   1 -
- .../gpu/drm/amd/dal/include/connector_interface.h  |  82 ----
- 10 files changed, 161 insertions(+), 822 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/connector/Makefile
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
- delete mode 100644 drivers/gpu/drm/amd/dal/include/connector_interface.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index 285e30d..0ab2c18 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for Display Core (dc) component.
- #
- 
--DC_LIBS = adapter asic_capability audio basics bios calcs connector \
-+DC_LIBS = adapter asic_capability audio basics bios calcs \
- dcs gpio gpu i2caux irq dce_base
- 
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/Makefile b/drivers/gpu/drm/amd/dal/dc/connector/Makefile
-deleted file mode 100644
-index ebd4115..0000000
---- a/drivers/gpu/drm/amd/dal/dc/connector/Makefile
-+++ /dev/null
-@@ -1,10 +0,0 @@
--#
--# Makefile for the 'connector' sub-component of DAL.
--# It provides the control and status of HW connectors blocks.
--
--
--CONNECTOR = connector_base.o connector_signals.o
--
--AMD_DAL_CONNECTOR = $(addprefix $(AMDDALPATH)/dc/connector/,$(CONNECTOR))
--
--AMD_DAL_FILES += $(AMD_DAL_CONNECTOR)
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector.h b/drivers/gpu/drm/amd/dal/dc/connector/connector.h
-deleted file mode 100644
-index 7d6057b..0000000
---- a/drivers/gpu/drm/amd/dal/dc/connector/connector.h
-+++ /dev/null
-@@ -1,39 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_CONNECTOR_H__
--#define __DAL_CONNECTOR_H__
--
--#include "include/connector_interface.h"
--
--extern const uint32_t number_of_default_signals;
--extern const uint32_t number_of_signals;
--
--/* Indexed by enum connector_id */
--extern const struct connector_signals default_signals[];
--/* Indexed by enum connector_id */
--extern const struct connector_signals supported_signals[];
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector_base.c b/drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
-deleted file mode 100644
-index 34005fd..0000000
---- a/drivers/gpu/drm/amd/dal/dc/connector/connector_base.c
-+++ /dev/null
-@@ -1,421 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dal_services.h"
--
--#include "connector.h"
--#include "include/irq_interface.h"
--#include "include/ddc_interface.h"
--#include "include/connector_interface.h"
--
--struct connector {
--	struct graphics_object_id id;
--	uint32_t input_signals;
--	uint32_t output_signals;
--	struct adapter_service *as;
--	struct connector_feature_support features;
--	struct connector_signals default_signals;
--	struct dc_context *ctx;
--};
--
--static bool connector_construct(
--	struct connector *connector,
--	struct dc_context *ctx,
--	struct adapter_service *as,
--	struct graphics_object_id go_id)
--{
--	bool hw_ddc_polling = false;
--	struct ddc *ddc;
--	struct irq *hpd;
--	enum connector_id connector_id;
--	uint32_t signals_vector = 0;
--	uint32_t signals_num = 0;
--	uint32_t i;
--
--	if (!as) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	connector->as = as;
--	connector->id = go_id;
--	connector->features.ddc_line = CHANNEL_ID_UNKNOWN;
--	connector->features.hpd_line = HPD_SOURCEID_UNKNOWN;
--	connector->ctx = ctx;
--
--	ddc = dal_adapter_service_obtain_ddc(as, connector->id);
--	hpd = dal_adapter_service_obtain_hpd_irq(as, connector->id);
--
--	connector_id = dal_graphics_object_id_get_connector_id(go_id);
--
--	/* Initialize DDC line */
--	if (ddc) {
--		switch (dal_ddc_get_line(ddc)) {
--		case GPIO_DDC_LINE_DDC1:
--			connector->features.ddc_line = CHANNEL_ID_DDC1;
--			break;
--		case GPIO_DDC_LINE_DDC2:
--			connector->features.ddc_line = CHANNEL_ID_DDC2;
--			break;
--		case GPIO_DDC_LINE_DDC3:
--			connector->features.ddc_line = CHANNEL_ID_DDC3;
--			break;
--		case GPIO_DDC_LINE_DDC4:
--			connector->features.ddc_line = CHANNEL_ID_DDC4;
--			break;
--		case GPIO_DDC_LINE_DDC5:
--			connector->features.ddc_line = CHANNEL_ID_DDC5;
--			break;
--		case GPIO_DDC_LINE_DDC6:
--			connector->features.ddc_line = CHANNEL_ID_DDC6;
--			break;
--		case GPIO_DDC_LINE_DDC_VGA:
--			connector->features.ddc_line = CHANNEL_ID_DDC_VGA;
--			break;
--		case GPIO_DDC_LINE_I2C_PAD:
--			connector->features.ddc_line = CHANNEL_ID_I2C_PAD;
--			break;
--		default:
--			BREAK_TO_DEBUGGER();
--			break;
--		}
--
--		/* Initialize HW DDC polling support
--		 * On DCE6.0 only DDC lines support HW polling (I2cPad does not)
--		 */
--
--		if (dal_adapter_service_is_feature_supported(
--			FEATURE_ENABLE_HW_EDID_POLLING)) {
--			switch (dal_ddc_get_line(ddc)) {
--			case GPIO_DDC_LINE_DDC1:
--			case GPIO_DDC_LINE_DDC2:
--			case GPIO_DDC_LINE_DDC3:
--			case GPIO_DDC_LINE_DDC4:
--			case GPIO_DDC_LINE_DDC5:
--			case GPIO_DDC_LINE_DDC6:
--			case GPIO_DDC_LINE_DDC_VGA:
--				hw_ddc_polling = true;
--			break;
--			default:
--			break;
--			}
--		}
--
--		dal_adapter_service_release_ddc(as, ddc);
--	}
--
--	/* Initialize HPD line */
--	if (hpd) {
--		switch (dal_irq_get_source(hpd)) {
--		case DC_IRQ_SOURCE_HPD1:
--			connector->features.hpd_line = HPD_SOURCEID1;
--		break;
--		case DC_IRQ_SOURCE_HPD2:
--			connector->features.hpd_line = HPD_SOURCEID2;
--		break;
--		case DC_IRQ_SOURCE_HPD3:
--			connector->features.hpd_line = HPD_SOURCEID3;
--		break;
--		case DC_IRQ_SOURCE_HPD4:
--			connector->features.hpd_line = HPD_SOURCEID4;
--		break;
--		case DC_IRQ_SOURCE_HPD5:
--			connector->features.hpd_line = HPD_SOURCEID5;
--		break;
--		case DC_IRQ_SOURCE_HPD6:
--			connector->features.hpd_line = HPD_SOURCEID6;
--		break;
--		default:
--			BREAK_TO_DEBUGGER();
--		break;
--		}
--
--		dal_adapter_service_release_irq(as, hpd);
--	}
--
--	if ((uint32_t)connector_id >= number_of_default_signals &&
--		(uint32_t)connector_id >= number_of_signals)
--		return false;
--
--	/* Initialize default signals */
--	connector->default_signals = default_signals[connector_id];
--
--	/* Fill supported signals */
--	signals_num = supported_signals[connector_id].number_of_signals;
--	for (i = 0; i < signals_num; i++)
--		signals_vector |= supported_signals[connector_id].signal[i];
--
--	/* Connector supports same set for input and output signals */
--	connector->input_signals = signals_vector;
--	connector->output_signals = signals_vector;
--
--	switch (connector_id) {
--	case CONNECTOR_ID_VGA:
--		if (hw_ddc_polling
--			&& connector->features.ddc_line != CHANNEL_ID_UNKNOWN)
--			connector->features.HW_DDC_POLLING = true;
--	break;
--	case CONNECTOR_ID_SINGLE_LINK_DVII:
--	case CONNECTOR_ID_DUAL_LINK_DVII:
--		if (connector->features.hpd_line != HPD_SOURCEID_UNKNOWN)
--			connector->features.HPD_FILTERING = true;
--		if (hw_ddc_polling
--			&& connector->features.ddc_line != CHANNEL_ID_UNKNOWN)
--			connector->features.HW_DDC_POLLING = true;
--	break;
--	case CONNECTOR_ID_SINGLE_LINK_DVID:
--	case CONNECTOR_ID_DUAL_LINK_DVID:
--	case CONNECTOR_ID_HDMI_TYPE_A:
--	case CONNECTOR_ID_LVDS:
--	case CONNECTOR_ID_DISPLAY_PORT:
--	case CONNECTOR_ID_EDP:
--		if (connector->features.hpd_line != HPD_SOURCEID_UNKNOWN)
--			connector->features.HPD_FILTERING = true;
--	break;
--	default:
--		connector->features.HPD_FILTERING = false;
--		connector->features.HW_DDC_POLLING = false;
--	break;
--	}
--
--	return true;
--}
--
--struct connector *dal_connector_create(
--	struct dc_context *ctx,
--	struct adapter_service *as,
--	struct graphics_object_id go_id)
--{
--	struct connector *connector = NULL;
--
--	connector = dc_service_alloc(ctx, sizeof(struct connector));
--
--	if (!connector) {
--		BREAK_TO_DEBUGGER();
--		return NULL;
--	}
--
--	if (connector_construct(connector, ctx, as, go_id))
--		return connector;
--
--	BREAK_TO_DEBUGGER();
--
--	dc_service_free(ctx, connector);
--
--	return NULL;
--}
--
--void dal_connector_destroy(struct connector **connector)
--{
--	if (!connector || !*connector) {
--		BREAK_TO_DEBUGGER();
--		return;
--	}
--
--	dc_service_free((*connector)->ctx, *connector);
--
--	*connector = NULL;
--}
--
--uint32_t dal_connector_enumerate_output_signals(
--	const struct connector *connector)
--{
--	return connector->output_signals;
--}
--
--uint32_t dal_connector_enumerate_input_signals(
--	const struct connector *connector)
--{
--	return connector->input_signals;
--}
--
--struct connector_signals dal_connector_get_default_signals(
--		const struct connector *connector)
--{
--	return connector->default_signals;
--}
--
--const struct graphics_object_id dal_connector_get_graphics_object_id(
--	const struct connector *connector)
--{
--	return connector->id;
--}
--
--/*
-- *  Function: program_hpd_filter
-- *
-- *  @brief
-- *     Programs HPD filter on associated HPD line
-- *
-- *  @param [in] delay_on_connect_in_ms: Connect filter timeout
-- *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
-- *
-- *  @return
-- *     true on success, false otherwise
-- */
--bool dal_connector_program_hpd_filter(
--	const struct connector *connector,
--	const uint32_t delay_on_connect_in_ms,
--	const uint32_t delay_on_disconnect_in_ms)
--{
--	bool result = false;
--
--	struct irq *hpd;
--
--	/* Verify feature is supported */
--
--	if (!connector->features.HPD_FILTERING)
--		return result;
--
--	/* Obtain HPD handle */
--
--	hpd = dal_adapter_service_obtain_hpd_irq(
--		connector->as, connector->id);
--
--	if (!hpd)
--		return result;
--
--	/* Setup HPD filtering */
--
--	if (GPIO_RESULT_OK == dal_irq_open(hpd)) {
--		struct gpio_hpd_config config;
--
--		config.delay_on_connect = delay_on_connect_in_ms;
--		config.delay_on_disconnect = delay_on_disconnect_in_ms;
--
--		dal_irq_setup_hpd_filter(hpd, &config);
--
--		dal_irq_close(hpd);
--
--		result = true;
--	} else {
--		ASSERT_CRITICAL(false);
--	}
--
--	/* Release HPD handle */
--
--	dal_adapter_service_release_irq(connector->as, hpd);
--
--	return result;
--}
--
--/*
-- *  Function: setup_ddc_polling
-- *
-- *  @brief
-- *     Enables/Disables HW polling on associated DDC line
-- *
-- *  @param [in] ddc_config: Specifies polling mode
-- *
-- *  @return
-- *     true on success, false otherwise
-- */
--static bool setup_ddc_polling(
--	const struct connector *connector,
--	enum gpio_ddc_config_type ddc_config)
--{
--	bool result = false;
--
--	struct ddc *ddc;
--
--	/* Verify feature is supported */
--
--	if (!connector->features.HW_DDC_POLLING)
--		return result;
--
--	/* Obtain DDC handle */
--
--	ddc = dal_adapter_service_obtain_ddc(
--		connector->as, connector->id);
--
--	if (!ddc) {
--		BREAK_TO_DEBUGGER();
--		return result;
--	}
--
--	/* Setup DDC polling */
--
--	if (GPIO_RESULT_OK == dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
--		GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
--		dal_ddc_set_config(ddc, ddc_config);
--
--		dal_ddc_close(ddc);
--
--		result = true;
--	} else {
--		BREAK_TO_DEBUGGER();
--	}
--
--	/* Release DDC handle */
--
--	dal_adapter_service_release_ddc(connector->as, ddc);
--
--	return result;
--}
--
--/*
-- *  Function: enable_ddc_polling
-- *
-- *  @brief
-- *     Enables HW polling on associated DDC line
-- *
-- *  @param [in] is_poll_for_connect: Specifies polling mode
-- *
-- *  @return
-- *     true on success, false otherwise
-- */
--bool dal_connector_enable_ddc_polling(
--	const struct connector *connector,
--	const bool is_poll_for_connect)
--{
--	enum gpio_ddc_config_type ddc_config = is_poll_for_connect ?
--		GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT :
--		GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT;
--
--	return setup_ddc_polling(connector, ddc_config);
--}
--
--/*
-- *  Function: disable_ddc_polling
-- *
-- *  @brief
-- *     Disables HW polling on associated DDC line
-- *
-- *  @return
-- *     true on success, false otherwise
-- */
--bool dal_connector_disable_ddc_polling(const struct connector *connector)
--{
--	return setup_ddc_polling(connector,
--		GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING);
--}
--
--void dal_connector_get_features(
--		const struct connector *con,
--		struct connector_feature_support *cfs)
--{
--	dc_service_memmove(cfs, &con->features,
--			sizeof(struct connector_feature_support));
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c b/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-deleted file mode 100644
-index 3a5d75b..0000000
---- a/drivers/gpu/drm/amd/dal/dc/connector/connector_signals.c
-+++ /dev/null
-@@ -1,238 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dal_services.h"
--
--#include "connector.h"
--
--static const enum signal_type signals_none[] = {
--		SIGNAL_TYPE_NONE
--};
--
--static const enum signal_type signals_single_link_dvii[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--		SIGNAL_TYPE_RGB
--};
--
--static const enum signal_type signals_dual_link_dvii[] = {
--		SIGNAL_TYPE_DVI_DUAL_LINK,
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--		SIGNAL_TYPE_RGB
--};
--
--static const enum signal_type signals_single_link_dvid[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK
--};
--
--static const enum signal_type signals_dual_link_dvid[] = {
--		SIGNAL_TYPE_DVI_DUAL_LINK,
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--};
--
--static const enum signal_type signals_vga[] = {
--		SIGNAL_TYPE_RGB
--};
--
--static const enum signal_type signals_hdmi_type_a[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--		SIGNAL_TYPE_HDMI_TYPE_A
--};
--
--static const enum signal_type signals_lvds[] = {
--		SIGNAL_TYPE_LVDS
--};
--
--static const enum signal_type signals_pcie[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--		SIGNAL_TYPE_HDMI_TYPE_A,
--		SIGNAL_TYPE_DISPLAY_PORT
--};
--
--static const enum signal_type signals_hardcode_dvi[] = {
--		SIGNAL_TYPE_NONE
--};
--
--static const enum signal_type signals_displayport[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--		SIGNAL_TYPE_HDMI_TYPE_A,
--		SIGNAL_TYPE_DISPLAY_PORT,
--		SIGNAL_TYPE_DISPLAY_PORT_MST
--};
--
--static const enum signal_type signals_edp[] = {
--		SIGNAL_TYPE_EDP
--};
--
--static const enum signal_type signals_wireless[] = {
--		SIGNAL_TYPE_WIRELESS
--};
--
--static const enum signal_type signals_miracast[] = {
--		SIGNAL_TYPE_WIRELESS
--};
--
--static const enum signal_type default_signals_none[] = {
--		SIGNAL_TYPE_NONE
--};
--
--static const enum signal_type default_signals_single_link_dvii[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK,
--		SIGNAL_TYPE_RGB
--};
--
--static const enum signal_type default_signals_dual_link_dvii[] = {
--		SIGNAL_TYPE_DVI_DUAL_LINK,
--		SIGNAL_TYPE_RGB
--};
--
--static const enum signal_type default_signals_single_link_dvid[] = {
--		SIGNAL_TYPE_DVI_SINGLE_LINK
--};
--
--static const enum signal_type default_signals_dual_link_dvid[] = {
--		SIGNAL_TYPE_DVI_DUAL_LINK,
--};
--
--static const enum signal_type default_signals_vga[] = {
--		SIGNAL_TYPE_RGB
--};
--
--static const enum signal_type default_signals_hdmi_type_a[] = {
--		SIGNAL_TYPE_HDMI_TYPE_A
--};
--
--static const enum signal_type default_signals_lvds[] = {
--		SIGNAL_TYPE_LVDS
--};
--
--static const enum signal_type default_signals_pcie[] = {
--		SIGNAL_TYPE_DISPLAY_PORT
--};
--
--static const enum signal_type default_signals_hardcode_dvi[] = {
--		SIGNAL_TYPE_NONE
--};
--
--static const enum signal_type default_signals_displayport[] = {
--		SIGNAL_TYPE_DISPLAY_PORT
--};
--
--static const enum signal_type default_signals_edp[] = {
--		SIGNAL_TYPE_EDP
--};
--
--static const enum signal_type default_signals_wireless[] = {
--		SIGNAL_TYPE_WIRELESS
--};
--
--static const enum signal_type default_signals_miracast[] = {
--		SIGNAL_TYPE_WIRELESS
--};
--
--/*
-- * Signal arrays
-- */
--
--#define SIGNALS_ARRAY_ELEM(a) {a, ARRAY_SIZE(a)}
--
--/* Indexed by enum connector_id */
--const struct connector_signals default_signals[] = {
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		SIGNALS_ARRAY_ELEM(default_signals_single_link_dvii),
--		SIGNALS_ARRAY_ELEM(default_signals_dual_link_dvii),
--		SIGNALS_ARRAY_ELEM(default_signals_single_link_dvid),
--		SIGNALS_ARRAY_ELEM(default_signals_dual_link_dvid),
--		SIGNALS_ARRAY_ELEM(default_signals_vga),
--		/* Composite */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		/* S Video */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		/* YPbPr */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		/* DConnector */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		/* 9pinDIN */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		/* SCART */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		SIGNALS_ARRAY_ELEM(default_signals_hdmi_type_a),
--		/* Not Used */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		SIGNALS_ARRAY_ELEM(default_signals_lvds),
--		/* 7pin DIN*/
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		SIGNALS_ARRAY_ELEM(default_signals_pcie),
--		/* CrossFire */
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		SIGNALS_ARRAY_ELEM(default_signals_hardcode_dvi),
--		SIGNALS_ARRAY_ELEM(default_signals_displayport),
--		SIGNALS_ARRAY_ELEM(default_signals_edp),
--		/* MXM*/
--		SIGNALS_ARRAY_ELEM(default_signals_none),
--		SIGNALS_ARRAY_ELEM(default_signals_wireless),
--		SIGNALS_ARRAY_ELEM(default_signals_miracast)
--};
--
--const uint32_t number_of_default_signals = ARRAY_SIZE(default_signals);
--
--/* Indexed by enum connector_id */
--const struct connector_signals supported_signals[] = {
--		SIGNALS_ARRAY_ELEM(signals_none),
--		SIGNALS_ARRAY_ELEM(signals_single_link_dvii),
--		SIGNALS_ARRAY_ELEM(signals_dual_link_dvii),
--		SIGNALS_ARRAY_ELEM(signals_single_link_dvid),
--		SIGNALS_ARRAY_ELEM(signals_dual_link_dvid),
--		SIGNALS_ARRAY_ELEM(signals_vga),
--		/* Composite */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		/* S Video */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		/* YPbPr */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		/* DConnector */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		/* 9pinDIN */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		/* SCART */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		SIGNALS_ARRAY_ELEM(signals_hdmi_type_a),
--		/* Note Used */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		SIGNALS_ARRAY_ELEM(signals_lvds),
--		/* 7pin DIN*/
--		SIGNALS_ARRAY_ELEM(signals_none),
--		SIGNALS_ARRAY_ELEM(signals_pcie),
--		/* CrossFire */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		SIGNALS_ARRAY_ELEM(signals_hardcode_dvi),
--		SIGNALS_ARRAY_ELEM(signals_displayport),
--		SIGNALS_ARRAY_ELEM(signals_edp),
--		/* MXM */
--		SIGNALS_ARRAY_ELEM(signals_none),
--		SIGNALS_ARRAY_ELEM(signals_wireless),
--		SIGNALS_ARRAY_ELEM(signals_miracast)
--};
--
--const uint32_t number_of_signals = ARRAY_SIZE(supported_signals);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 2211f38..3347174 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -29,7 +29,6 @@
- #include "core_dc.h"
- #include "adapter_service_interface.h"
- #include "grph_object_id.h"
--#include "connector_interface.h"
- #include "gpio_service_interface.h"
- #include "ddc_service_interface.h"
- #include "core_status.h"
-@@ -45,6 +44,10 @@
- 		LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_HOTPLUG, \
- 		__VA_ARGS__)
- 
-+#define DELAY_ON_CONNECT_IN_MS 500
-+#define DELAY_ON_DISCONNECT_IN_MS 500
-+
-+
- /*******************************************************************************
-  * Private structures
-  ******************************************************************************/
-@@ -55,9 +58,6 @@
-  ******************************************************************************/
- static void destruct(struct core_link *link)
- {
--	if (link->connector)
--		dal_connector_destroy(&link->connector);
--
- 	if (link->ddc)
- 		dal_ddc_service_destroy(&link->ddc);
- 
-@@ -65,6 +65,73 @@ static void destruct(struct core_link *link)
- 		link->ctx->dc->hwss.encoder_destroy(&link->link_enc);
- }
- 
-+/*
-+ *  Function: program_hpd_filter
-+ *
-+ *  @brief
-+ *     Programs HPD filter on associated HPD line
-+ *
-+ *  @param [in] delay_on_connect_in_ms: Connect filter timeout
-+ *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
-+ *
-+ *  @return
-+ *     true on success, false otherwise
-+ */
-+static bool program_hpd_filter(
-+	const struct core_link *link)
-+{
-+	bool result = false;
-+
-+	struct irq *hpd;
-+
-+	/* Verify feature is supported */
-+
-+	switch (link->public.connector_signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* program hpd filter */
-+		break;
-+	default:
-+		/* don't program hpd filter */
-+		return false;
-+	}
-+
-+	/* Obtain HPD handle */
-+	hpd = dal_adapter_service_obtain_hpd_irq(
-+		link->adapter_srv, link->link_id);
-+
-+	if (!hpd)
-+		return result;
-+
-+	/* Setup HPD filtering */
-+
-+	if (dal_irq_open(hpd) == GPIO_RESULT_OK) {
-+		struct gpio_hpd_config config;
-+
-+		config.delay_on_connect = DELAY_ON_CONNECT_IN_MS;
-+		config.delay_on_disconnect = DELAY_ON_DISCONNECT_IN_MS;
-+
-+		dal_irq_setup_hpd_filter(hpd, &config);
-+
-+		dal_irq_close(hpd);
-+
-+		result = true;
-+	} else {
-+		ASSERT_CRITICAL(false);
-+	}
-+
-+	/* Release HPD handle */
-+
-+	dal_adapter_service_release_irq(link->adapter_srv, hpd);
-+
-+	return result;
-+}
-+
- static bool detect_sink(struct core_link *link)
- {
- 	uint32_t is_hpd_high = 0;
-@@ -651,6 +718,91 @@ void dc_link_detect(const struct dc_link *dc_link)
- 	return;
- }
- 
-+static enum hpd_source_id get_hpd_line(
-+		struct core_link *link,
-+		struct adapter_service *as)
-+{
-+	struct irq *hpd;
-+	enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
-+
-+	hpd = dal_adapter_service_obtain_hpd_irq(as, link->link_id);
-+
-+	if (hpd) {
-+		switch (dal_irq_get_source(hpd)) {
-+		case DC_IRQ_SOURCE_HPD1:
-+			hpd_id = HPD_SOURCEID1;
-+		break;
-+		case DC_IRQ_SOURCE_HPD2:
-+			hpd_id = HPD_SOURCEID2;
-+		break;
-+		case DC_IRQ_SOURCE_HPD3:
-+			hpd_id = HPD_SOURCEID3;
-+		break;
-+		case DC_IRQ_SOURCE_HPD4:
-+			hpd_id = HPD_SOURCEID4;
-+		break;
-+		case DC_IRQ_SOURCE_HPD5:
-+			hpd_id = HPD_SOURCEID5;
-+		break;
-+		case DC_IRQ_SOURCE_HPD6:
-+			hpd_id = HPD_SOURCEID6;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+		break;
-+		}
-+
-+		dal_adapter_service_release_irq(as, hpd);
-+	}
-+
-+	return hpd_id;
-+}
-+
-+static enum channel_id get_ddc_line(struct core_link *link, struct adapter_service *as)
-+{
-+	struct ddc *ddc;
-+	enum channel_id channel = CHANNEL_ID_UNKNOWN;
-+
-+	ddc = dal_adapter_service_obtain_ddc(as, link->link_id);
-+
-+	if (ddc) {
-+		switch (dal_ddc_get_line(ddc)) {
-+		case GPIO_DDC_LINE_DDC1:
-+			channel = CHANNEL_ID_DDC1;
-+			break;
-+		case GPIO_DDC_LINE_DDC2:
-+			channel = CHANNEL_ID_DDC2;
-+			break;
-+		case GPIO_DDC_LINE_DDC3:
-+			channel = CHANNEL_ID_DDC3;
-+			break;
-+		case GPIO_DDC_LINE_DDC4:
-+			channel = CHANNEL_ID_DDC4;
-+			break;
-+		case GPIO_DDC_LINE_DDC5:
-+			channel = CHANNEL_ID_DDC5;
-+			break;
-+		case GPIO_DDC_LINE_DDC6:
-+			channel = CHANNEL_ID_DDC6;
-+			break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			channel = CHANNEL_ID_DDC_VGA;
-+			break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			channel = CHANNEL_ID_I2C_PAD;
-+			break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			break;
-+		}
-+
-+		dal_adapter_service_release_ddc(as, ddc);
-+	}
-+
-+	return channel;
-+}
-+
-+
- static bool construct(
- 	struct core_link *link,
- 	const struct link_init_data *init_params)
-@@ -661,7 +813,6 @@ static bool construct(
- 	struct ddc_service_init_data ddc_service_init_data = { 0 };
- 	struct dc_context *dc_ctx = init_params->ctx;
- 	struct encoder_init_data enc_init_data = { 0 };
--	struct connector_feature_support cfs = { 0 };
- 	struct integrated_info info = {{{ 0 }}};
- 
- 	link->dc = init_params->dc;
-@@ -732,13 +883,6 @@ static bool construct(
- 			init_params->connector_index,
- 			link->public.connector_signal);
- 
--	link->connector = dal_connector_create(dc_ctx, as, link->link_id);
--	if (NULL == link->connector) {
--		DC_ERROR("Failed to create connector object!\n");
--		goto create_fail;
--	}
--
--
- 	hpd_gpio = dal_adapter_service_obtain_hpd_irq(as, link->link_id);
- 
- 	if (hpd_gpio != NULL) {
-@@ -756,15 +900,13 @@ static bool construct(
- 		goto create_fail;
- 	}
- 
--	dal_connector_get_features(link->connector, &cfs);
--
- 	enc_init_data.adapter_service = as;
- 	enc_init_data.ctx = dc_ctx;
- 	enc_init_data.encoder = dal_adapter_service_get_src_obj(
- 							as, link->link_id, 0);
- 	enc_init_data.connector = link->link_id;
--	enc_init_data.channel = cfs.ddc_line;
--	enc_init_data.hpd_source = cfs.hpd_line;
-+	enc_init_data.channel = get_ddc_line(link, as);
-+	enc_init_data.hpd_source = get_hpd_line(link, as);
- 	link->link_enc = dc_ctx->dc->hwss.encoder_create(&enc_init_data);
- 
- 	if( link->link_enc == NULL) {
-@@ -819,13 +961,7 @@ static bool construct(
- 	 * If GPIO isn't programmed correctly HPD might not rise or drain
- 	 * fast enough, leading to bounces.
- 	 */
--#define DELAY_ON_CONNECT_IN_MS 500
--#define DELAY_ON_DISCONNECT_IN_MS 500
--
--	dal_connector_program_hpd_filter(
--		link->connector,
--		DELAY_ON_CONNECT_IN_MS,
--		DELAY_ON_DISCONNECT_IN_MS);
-+	program_hpd_filter(link);
- 
- 	return true;
- 
-@@ -1126,10 +1262,7 @@ bool dc_link_set_backlight_level(const struct dc_link *public, uint32_t level)
- 
- void core_link_resume(struct core_link *link)
- {
--	dal_connector_program_hpd_filter(
--		link->connector,
--		DELAY_ON_CONNECT_IN_MS,
--		DELAY_ON_DISCONNECT_IN_MS);
-+	program_hpd_filter(link);
- }
- 
- 
-@@ -1279,4 +1412,3 @@ void core_link_disable_stream(
- 	disable_link(stream);
- 
- }
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index c0390e1..787091f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -5,7 +5,6 @@
- #include "inc/core_types.h"
- #include "link_hwss.h"
- #include "ddc_service_interface.h"
--#include "connector_interface.h"
- #include "core_status.h"
- #include "dpcd_defs.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 5ed0380..715aa9f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -6,7 +6,6 @@
- #include "include/ddc_service_types.h"
- #include "include/i2caux_interface.h"
- #include "link_hwss.h"
--#include "include/connector_interface.h"
- #include "hw_sequencer.h"
- #include "include/ddc_service_interface.h"
- #include "dc_helpers.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index dc871ad..26f5002 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -205,7 +205,6 @@ struct core_link {
- 	uint8_t connector_index; /* this will be mapped to the HPD pins */
- 
- 	struct adapter_service *adapter_srv;
--	struct connector *connector;
- 	struct link_encoder *link_enc;
- 	struct ddc_service *ddc;
- 	struct graphics_object_id link_id;
-diff --git a/drivers/gpu/drm/amd/dal/include/connector_interface.h b/drivers/gpu/drm/amd/dal/include/connector_interface.h
-deleted file mode 100644
-index e09af7e..0000000
---- a/drivers/gpu/drm/amd/dal/include/connector_interface.h
-+++ /dev/null
-@@ -1,82 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_CONNECTOR_INTERFACE_H__
--#define __DAL_CONNECTOR_INTERFACE_H__
--
--#include "adapter_service_interface.h"
--#include "signal_types.h"
--
--/* forward declaration */
--struct connector;
--
--struct connector_signals {
--	const enum signal_type *signal;
--	uint32_t number_of_signals;
--};
--
--struct connector_feature_support {
--	bool HPD_FILTERING:1;
--	bool HW_DDC_POLLING:1;
--	enum hpd_source_id hpd_line;
--	enum channel_id ddc_line;
--};
--
--void dal_connector_get_features(
--		const struct connector *con,
--		struct connector_feature_support *cfs);
--
--struct connector *dal_connector_create(
--	struct dc_context *ctx,
--	struct adapter_service *as,
--	struct graphics_object_id go_id);
--
--void dal_connector_destroy(struct connector **connector);
--
--void dal_connector_destroy(struct connector **connector);
--
--const struct graphics_object_id dal_connector_get_graphics_object_id(
--	const struct connector *connector);
--
--uint32_t dal_connector_enumerate_output_signals(
--	const struct connector *connector);
--uint32_t dal_connector_enumerate_input_signals(
--	const struct connector *connector);
--
--struct connector_signals dal_connector_get_default_signals(
--		const struct connector *connector);
--
--bool dal_connector_program_hpd_filter(
--	const struct connector *connector,
--	const uint32_t delay_on_connect_in_ms,
--	const uint32_t delay_on_disconnect_in_ms);
--
--bool dal_connector_enable_ddc_polling(
--	const struct connector *connector,
--	const bool is_poll_for_connect);
--
--bool dal_connector_disable_ddc_polling(const struct connector *connector);
--
--#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0661-drm-amd-dal-Refactor-DCE11-timing-generator.patch b/common/recipes-kernel/linux/files/0661-drm-amd-dal-Refactor-DCE11-timing-generator.patch
deleted file mode 100644
index a4a031d0..00000000
--- a/common/recipes-kernel/linux/files/0661-drm-amd-dal-Refactor-DCE11-timing-generator.patch
+++ /dev/null
@@ -1,1270 +0,0 @@
-From fc2a45ea5855721d7cf2c891e9592b4c63dd612c Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Tue, 29 Dec 2015 19:25:37 -0500
-Subject: [PATCH 0661/1110] drm/amd/dal: Refactor DCE11 timing generator
-
-Refactor timing generator for DCE11 to be called directly from DC rather than
-exclusively through HWSS.
-
-This is meant as a template to avoid always going through HWSS for all calls to HW.
-This creates a better defined role for HWSS to only implement actual
-sequences rather than as a generic layer.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  87 +++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  71 +++-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 363 +++++++++++++--------
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |  55 +++-
- .../amd/dal/include/timing_generator_interface.h   |  30 ++
- .../drm/amd/dal/include/timing_generator_types.h   |  50 ++-
- 6 files changed, 470 insertions(+), 186 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index fa6b9b4..1085137 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -671,7 +671,7 @@ static void enable_stream(struct core_stream *stream)
- 	if (early_control == 0)
- 		early_control = lane_count;
- 
--	dce110_timing_generator_set_early_control(tg, early_control);
-+	tg->funcs->set_early_control(tg, early_control);
- 
- 	/* enable audio only within mode set */
- 	if (stream->audio != NULL) {
-@@ -800,7 +800,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		/* Must blank CRTC after disabling power gating and before any
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
--		dce110_timing_generator_blank_crtc(stream->tg);
-+		stream->tg->funcs->set_blank(stream->tg, true);
- 
- 		core_link_disable_stream(
- 				stream->sink->link, stream);
-@@ -815,12 +815,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		}
- 
- 
--		if (false == dce110_timing_generator_program_timing_generator(
-+		stream->tg->funcs->program_timing(
- 				stream->tg,
--				&stream->public.timing)) {
--			BREAK_TO_DEBUGGER();
--			return DC_ERROR_UNEXPECTED;
--		}
-+				&stream->public.timing,
-+				true);
- 	}
- 
- 	/*TODO: mst support - use total stream count*/
-@@ -829,7 +827,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			context->target_count);
- 
- 	if (timing_changed) {
--		if (false == dce110_timing_generator_enable_crtc(
-+		if (false == stream->tg->funcs->enable_crtc(
- 				stream->tg)) {
- 			BREAK_TO_DEBUGGER();
- 			return DC_ERROR_UNEXPECTED;
-@@ -896,7 +894,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	color_space = get_output_color_space(
- 			&stream->public.timing);
- 
--	dce110_timing_generator_program_blank_color(
-+	stream->tg->funcs->set_blank_color(
- 			context->res_ctx.pool.timing_generators[controller_idx],
- 			color_space);
- 
-@@ -928,7 +926,7 @@ static void power_down_controllers(struct dc *dc)
- 	int i;
- 
- 	for (i = 0; i < dc->res_pool.controller_count; i++) {
--		dce110_timing_generator_disable_crtc(
-+		dc->res_pool.timing_generators[i]->funcs->disable_crtc(
- 				dc->res_pool.timing_generators[i]);
- 	}
- }
-@@ -972,7 +970,7 @@ static void disable_vga_and_power_gate_all_controllers(
- 		tg = dc->res_pool.timing_generators[i];
- 		ctx = dc->ctx;
- 
--		dce110_timing_generator_disable_vga(tg);
-+		tg->funcs->disable_vga(tg);
- 
- 		/* Enable CLOCK gating for each pipe BEFORE controller
- 		 * powergating. */
-@@ -1336,7 +1334,7 @@ static bool setup_line_buffer_pixel_depth(
- 
- 	if (current_depth != depth) {
- 		if (blank)
--			dce110_timing_generator_wait_for_vblank(tg);
-+			tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
- 
- 		return dce110_transform_set_pixel_storage_depth(xfm, depth);
- 	}
-@@ -1421,9 +1419,7 @@ static void program_scaler(
- 		LB_PIXEL_DEPTH_24BPP,
- 		false);
- 
--	dce110_timing_generator_set_overscan_color_black(
--			tg,
--			surface->public.colorimetry.color_space);
-+	tg->funcs->set_overscan_blank_color(tg, surface->public.colorimetry.color_space);
- 
- 	dce110_transform_set_scaler(xfm, &scaler_data);
- 
-@@ -1433,8 +1429,6 @@ static void program_scaler(
- 			false);
- }
- 
--
--
- static void configure_locking(struct dc_context *ctx, uint8_t controller_id)
- {
- 	/* main controller should be in mode 0 (master pipe) */
-@@ -1484,7 +1478,7 @@ static bool set_plane_config(
- 			PIPE_LOCK_CONTROL_SURFACE,
- 			true);
- 
--	dce110_timing_generator_program_blanking(tg, dc_crtc_timing);
-+	tg->funcs->program_timing(tg, dc_crtc_timing, false);
- 
- 	enable_fe_clock(ctx, controller_idx, true);
- 
-@@ -1577,8 +1571,8 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 
- 	core_link_disable_stream(stream->sink->link, stream);
- 
--	dce110_timing_generator_blank_crtc(stream->tg);
--	dce110_timing_generator_disable_crtc(stream->tg);
-+	stream->tg->funcs->set_blank(stream->tg, true);
-+	stream->tg->funcs->disable_crtc(stream->tg);
- 	dce110_mem_input_deallocate_dmif_buffer(stream->mi, context->target_count);
- 	dce110_transform_set_scaler_bypass(stream->xfm);
- 	disable_stereo_mixer(stream->ctx);
-@@ -1630,12 +1624,12 @@ static bool wait_for_reset_trigger_to_occur(
- 
- 	for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
- 
--		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+		if (!tg->funcs->is_counter_moving(tg)) {
- 			DC_ERROR("TG counter is not moving!\n");
- 			break;
- 		}
- 
--		if (dce110_timing_generator_did_triggered_reset_occur(tg)) {
-+		if (tg->funcs->did_triggered_reset_occur(tg)) {
- 			rc = true;
- 			/* usually occurs at i=1 */
- 			DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
-@@ -1644,8 +1638,8 @@ static bool wait_for_reset_trigger_to_occur(
- 		}
- 
- 		/* Wait for one frame. */
--		dce110_timing_generator_wait_for_vactive(tg);
--		dce110_timing_generator_wait_for_vblank(tg);
-+		tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
-+		tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
- 	}
- 
- 	if (false == rc)
-@@ -1675,8 +1669,7 @@ static void enable_timing_synchronization(
- 		 * the 1st one in the group. */
- 		gsl_params.timing_server = (0 == i ? true : false);
- 
--		dce110_timing_generator_setup_global_swap_lock(tgs[i],
--				&gsl_params);
-+		tgs[i]->funcs->setup_global_swap_lock(tgs[i], &gsl_params);
- 	}
- 
- 	/* Reset slave controllers on master VSync */
-@@ -1687,8 +1680,7 @@ static void enable_timing_synchronization(
- 	trigger_params.source = SYNC_SOURCE_GSL_GROUP0;
- 
- 	for (i = 1 /* skip the master */; i < timing_generator_num; i++) {
--		dce110_timing_generator_enable_reset_trigger(tgs[i],
--				&trigger_params);
-+		tgs[i]->funcs->enable_reset_trigger(tgs[i], &trigger_params);
- 
- 		DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
- 		wait_for_reset_trigger_to_occur(dc_ctx, tgs[i]);
-@@ -1696,35 +1688,60 @@ static void enable_timing_synchronization(
- 		/* Regardless of success of the wait above, remove the reset or
- 		 * the driver will start timing out on Display requests. */
- 		DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
--		dce110_timing_generator_disable_reset_trigger(tgs[i]);
-+		tgs[i]->funcs->disable_reset_trigger(tgs[i]);
- 	}
- 
- 	/* GSL Vblank synchronization is a one time sync mechanism, assumption
- 	 * is that the sync'ed displays will not drift out of sync over time*/
- 	DC_SYNC_INFO("GSL: Restoring register states.\n");
- 	for (i = 0; i < timing_generator_num; i++)
--		dce110_timing_generator_tear_down_global_swap_lock(tgs[i]);
-+		tgs[i]->funcs->tear_down_global_swap_lock(tgs[i]);
- 
- 	DC_SYNC_INFO("GSL: Set-up complete.\n");
- }
- 
-+static void get_crtc_positions(struct timing_generator *tg,
-+		int32_t *h_position, int32_t *v_position)
-+{
-+	tg->funcs->get_position(tg, h_position, v_position);
-+}
-+
-+static bool enable_memory_request(struct timing_generator *tg)
-+{
-+	return tg->funcs->set_blank(tg, false);
-+}
-+
-+static bool disable_memory_requests(struct timing_generator *tg)
-+{
-+	return tg->funcs->set_blank(tg, true);
-+}
-+
-+static uint32_t get_vblank_counter(struct timing_generator *tg)
-+{
-+	return tg->funcs->get_frame_count(tg);
-+}
-+
-+static void disable_vga(struct timing_generator *tg)
-+{
-+	tg->funcs->disable_vga(tg);
-+}
- 
- static const struct hw_sequencer_funcs dce110_funcs = {
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
- 	.reset_hw_ctx = reset_hw_ctx,
- 	.set_plane_config = set_plane_config,
- 	.update_plane_address = update_plane_address,
--	.enable_memory_requests = dce110_timing_generator_unblank_crtc,
--	.disable_memory_requests = dce110_timing_generator_blank_crtc,
-+	.enable_memory_requests = enable_memory_request,
-+	.disable_memory_requests = disable_memory_requests,
- 	.cursor_set_attributes = dce110_ipp_cursor_set_attributes,
- 	.cursor_set_position = dce110_ipp_cursor_set_position,
- 	.set_gamma_ramp = set_gamma_ramp,
- 	.power_down = power_down,
- 	.enable_accelerated_mode = enable_accelerated_mode,
--	.get_crtc_positions = dce110_timing_generator_get_crtc_positions,
--	.get_vblank_counter = dce110_timing_generator_get_vblank_counter,
-+	.get_crtc_positions = get_crtc_positions,
-+	.get_vblank_counter = get_vblank_counter,
- 	.enable_timing_synchronization = enable_timing_synchronization,
--	.disable_vga = dce110_timing_generator_disable_vga,
-+	.disable_vga = disable_vga,
- 	.encoder_create = dce110_link_encoder_create,
- 	.encoder_destroy = dce110_link_encoder_destroy,
- 	.encoder_hw_init = dce110_link_encoder_hw_init,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index cb084da..d789853 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -30,6 +30,7 @@
- #include "resource.h"
- #include "dce_base/dce_base_resource.h"
- #include "include/irq_service_interface.h"
-+#include "include/timing_generator_interface.h"
- 
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
-@@ -39,6 +40,8 @@
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
- 
-+#include "dce/dce_11_0_d.h"
-+
- enum dce110_clk_src_array_id {
- 	DCE110_CLK_SRC_PLL0 = 0,
- 	DCE110_CLK_SRC_PLL1,
-@@ -47,6 +50,53 @@ enum dce110_clk_src_array_id {
- 	DCE110_CLK_SRC_TOTAL
- };
- 
-+static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
-+		{
-+			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+		}
-+};
-+
-+static struct timing_generator *dce110_timing_generator_create(
-+		struct adapter_service *as,
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_timing_generator));
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
-+		return &tg110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, tg110);
-+	return NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -117,7 +167,7 @@ bool dce110_construct_resource_pool(
- 
- 	for (i = 0; i < pool->controller_count; i++) {
- 		pool->timing_generators[i] = dce110_timing_generator_create(
--				adapter_serv, ctx, i + 1);
-+				adapter_serv, ctx, i, &dce110_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error("DC: failed to create tg!\n");
-@@ -225,9 +275,10 @@ controller_create_fail:
- 		if (pool->mis[i] != NULL)
- 			dce110_mem_input_destroy(&pool->mis[i]);
- 
--		if (pool->timing_generators[i] != NULL)
--			dce110_timing_generator_destroy(
--				&pool->timing_generators[i]);
-+		if (pool->timing_generators[i] != NULL)	{
-+			dc_service_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
- 	}
- 
- filter_create_fail:
-@@ -262,9 +313,10 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 		if (pool->mis[i] != NULL)
- 			dce110_mem_input_destroy(&pool->mis[i]);
- 
--		if (pool->timing_generators[i] != NULL)
--			dce110_timing_generator_destroy(
--				&pool->timing_generators[i]);
-+		if (pool->timing_generators[i] != NULL)	{
-+			dc_service_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
- 	}
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
-@@ -454,10 +506,7 @@ static enum dc_status validate_mapped_resource(
- 			if (status != DC_OK)
- 				return status;
- 
--			if (!dce110_timing_generator_validate_timing(
--					stream->tg,
--					&stream->public.timing,
--					SIGNAL_TYPE_HDMI_TYPE_A))
-+			if (!stream->tg->funcs->validate_timing(stream->tg, &stream->public.timing))
- 				return DC_FAIL_CONTROLLER_VALIDATE;
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 3c6c04a..b47ba61 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -52,27 +52,16 @@ enum black_color_format {
- #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
- #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
- 
--
--#define FROM_TIMING_GENERATOR(tg)\
--	container_of(tg, struct dce110_timing_generator, base)
--
- #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
- #define DCP_REG(reg) (reg + tg110->offsets.dcp)
- 
--static const struct dce110_timing_generator_offsets reg_offsets[] = {
--	{
--		.crtc = 0,
--		.dcp = 0,
--	},
--	{
--		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
--		.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	},
--	{
--		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
--		.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	}
--};
-+/* Flowing register offsets are same in files of
-+ * dce/dce_11_0_d.h
-+ * dce/vi_ellesmere_p/vi_ellesmere_d.h
-+ *
-+ * So we can create dce110 timing generator to use it.
-+ */
-+
- /*******************************************************************************
-  * GSL Sync related values */
- 
-@@ -131,16 +120,31 @@ enum trigger_polarity_select {
- 
- /******************************************************************************/
- 
--static bool dce110_timing_generator_construct(
--		struct timing_generator *tg,
--		enum controller_id id)
--{
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
--
--	tg->controller_id = id;
--	tg110->offsets = reg_offsets[id - 1];
--	return true;
--}
-+static struct timing_generator_funcs dce110_tg_funcs = {
-+		.validate_timing = dce110_tg_validate_timing,
-+		.program_timing = dce110_tg_program_timing,
-+		.enable_crtc = dce110_timing_generator_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_disable_crtc,
-+		.is_counter_moving = dce110_timing_generator_is_counter_moving,
-+		.get_position = dce110_timing_generator_get_crtc_positions,
-+		.get_frame_count = dce110_timing_generator_get_vblank_counter,
-+		.set_early_control = dce110_timing_generator_set_early_control,
-+		.wait_for_state = dce110_tg_wait_for_state,
-+		.set_blank = dce110_tg_set_blank,
-+		.set_colors = dce110_tg_set_colors,
-+		.set_overscan_blank_color =
-+				dce110_timing_generator_set_overscan_color_black,
-+		.set_blank_color = dce110_timing_generator_program_blank_color,
-+		.disable_vga = dce110_timing_generator_disable_vga,
-+		.did_triggered_reset_occur =
-+				dce110_timing_generator_did_triggered_reset_occur,
-+		.setup_global_swap_lock =
-+				dce110_timing_generator_setup_global_swap_lock,
-+		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
-+		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
-+		.tear_down_global_swap_lock =
-+				dce110_timing_generator_tear_down_global_swap_lock,
-+};
- 
- static const struct crtc_black_color black_color_format[] = {
- 	/* BlackColorFormat_RGB_FullRange */
-@@ -246,7 +250,7 @@ static bool dce110_timing_generator_is_in_vertical_blank(
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 	uint32_t field = 0;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	addr = CRTC_REG(mmCRTC_STATUS);
- 	value = dal_read_reg(tg->ctx, addr);
-@@ -259,7 +263,7 @@ void dce110_timing_generator_set_early_control(
- 		uint32_t early_cntl)
- {
- 	uint32_t regval;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t address = CRTC_REG(mmCRTC_CONTROL);
- 
- 	regval = dal_read_reg(tg->ctx, address);
-@@ -279,7 +283,7 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	/* 0 value is needed by DRR and is also suggested default value for CZ
- 	 */
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	value = dal_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
-@@ -288,7 +292,7 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	dal_write_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
--	result = dal_bios_parser_enable_crtc(tg->bp, tg->controller_id, true);
-+	result = dal_bios_parser_enable_crtc(tg->bp, tg110->controller_id, true);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -298,7 +302,7 @@ void dce110_timing_generator_program_blank_color(
- 		enum color_space color_space)
- {
- 	struct crtc_black_color black_color;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
-@@ -332,7 +336,7 @@ void dce110_timing_generator_program_blank_color(
- 
- bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLANK_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 	uint8_t counter = 100;
-@@ -372,7 +376,7 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- 		dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- 				LOG_MINOR_COMPONENT_CONTROLLER,
- 				"timing generator %d blank timing out.\n",
--				tg->controller_id);
-+				tg110->controller_id);
- 		return false;
- 	}
- 
-@@ -385,7 +389,7 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
-  */
- bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLANK_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
-@@ -419,7 +423,7 @@ bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- @TODOSTEREO
- static void disable_stereo(struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL);
- 	uint32_t value = 0;
- 	uint32_t test = 0;
-@@ -465,7 +469,9 @@ bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
- {
- 	enum bp_result result;
- 
--	result = dal_bios_parser_enable_crtc(tg->bp, tg->controller_id, false);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	result = dal_bios_parser_enable_crtc(tg->bp, tg110->controller_id, false);
- 
- 	/* Need to make sure stereo is disabled according to the DCE5.0 spec */
- 
-@@ -487,7 +493,7 @@ static void program_horz_count_by_2(
- 	const struct dc_crtc_timing *timing)
- {
- 	uint32_t regval;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	regval = dal_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_COUNT_CONTROL));
-@@ -510,12 +516,13 @@ static void program_horz_count_by_2(
-  */
- bool dce110_timing_generator_program_timing_generator(
- 	struct timing_generator *tg,
--	struct dc_crtc_timing *dc_crtc_timing)
-+	const struct dc_crtc_timing *dc_crtc_timing)
- {
- 	enum bp_result result;
- 	struct bp_hw_crtc_timing_parameters bp_params;
-+	struct dc_crtc_timing patched_crtc_timing;
- 	uint32_t regval;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +
- 			dc_crtc_timing->v_front_porch;
-@@ -530,52 +537,54 @@ bool dce110_timing_generator_program_timing_generator(
- 	/* Due to an asic bug we need to apply the Front Porch workaround prior
- 	 * to programming the timing.
- 	 */
--	dce110_timing_generator_apply_front_porch_workaround(tg, dc_crtc_timing);
- 
--	bp_params.controller_id = tg->controller_id;
-+	patched_crtc_timing = *dc_crtc_timing;
-+
-+	dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing);
-+
-+	bp_params.controller_id = tg110->controller_id;
- 
--	bp_params.h_total = dc_crtc_timing->h_total;
-+	bp_params.h_total = patched_crtc_timing.h_total;
- 	bp_params.h_addressable =
--		dc_crtc_timing->h_addressable;
--	bp_params.v_total = dc_crtc_timing->v_total;
--	bp_params.v_addressable = dc_crtc_timing->v_addressable;
-+		patched_crtc_timing.h_addressable;
-+	bp_params.v_total = patched_crtc_timing.v_total;
-+	bp_params.v_addressable = patched_crtc_timing.v_addressable;
- 
- 	bp_params.h_sync_start = h_sync_start;
--	bp_params.h_sync_width = dc_crtc_timing->h_sync_width;
-+	bp_params.h_sync_width = patched_crtc_timing.h_sync_width;
- 	bp_params.v_sync_start = v_sync_start;
--	bp_params.v_sync_width = dc_crtc_timing->v_sync_width;
-+	bp_params.v_sync_width = patched_crtc_timing.v_sync_width;
- 
- 	/* Set overscan */
- 	bp_params.h_overscan_left =
--		dc_crtc_timing->h_border_left;
-+		patched_crtc_timing.h_border_left;
- 	bp_params.h_overscan_right =
--		dc_crtc_timing->h_border_right;
--	bp_params.v_overscan_top = dc_crtc_timing->v_border_top;
-+		patched_crtc_timing.h_border_right;
-+	bp_params.v_overscan_top = patched_crtc_timing.v_border_top;
- 	bp_params.v_overscan_bottom =
--		dc_crtc_timing->v_border_bottom;
-+		patched_crtc_timing.v_border_bottom;
- 
- 	/* Set flags */
--	if (dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY == 1)
-+	if (patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY == 1)
- 		bp_params.flags.HSYNC_POSITIVE_POLARITY = 1;
- 
--	if (dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY == 1)
-+	if (patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY == 1)
- 		bp_params.flags.VSYNC_POSITIVE_POLARITY = 1;
- 
--	if (dc_crtc_timing->flags.INTERLACE == 1)
-+	if (patched_crtc_timing.flags.INTERLACE == 1)
- 		bp_params.flags.INTERLACE = 1;
- 
--	if (dc_crtc_timing->flags.HORZ_COUNT_BY_TWO == 1)
-+	if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1)
- 		bp_params.flags.HORZ_COUNT_BY_TWO = 1;
- 
- 	result = dal_bios_parser_program_crtc_timing(tg->bp, &bp_params);
- 
--	program_horz_count_by_2(tg, dc_crtc_timing);
--
-+	program_horz_count_by_2(tg, &patched_crtc_timing);
- 
- 	regval = dal_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_START_LINE_CONTROL));
- 
--	if (dce110_timing_generator_get_vsynch_and_front_porch_size(dc_crtc_timing) <= 3) {
-+	if (dce110_timing_generator_get_vsynch_and_front_porch_size(&patched_crtc_timing) <= 3) {
- 		set_reg_field_value(regval, 3,
- 				CRTC_START_LINE_CONTROL,
- 				CRTC_ADVANCED_START_LINE_POSITION);
-@@ -632,7 +641,7 @@ void dce110_timing_generator_program_drr(
- 	uint32_t v_total_max = 0;
- 	uint32_t v_total_cntl = 0;
- 	uint32_t static_screen_cntl = 0;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	uint32_t addr = 0;
- 
-@@ -796,7 +805,7 @@ void dce110_timing_generator_program_drr(
-  */
- uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 	uint32_t field = get_reg_field_value(
-@@ -822,7 +831,7 @@ void dce110_timing_generator_get_crtc_positions(
- 	int32_t *v_position)
- {
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION));
- 
-@@ -852,7 +861,7 @@ uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	int32_t *vbl,
- 	int32_t *position)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	/* TODO 1: Update the implementation once caller is updated
- 	 * WARNING!! This function is returning the whole register value
- 	 * because the caller is expecting it instead of proper vertical and
-@@ -887,7 +896,7 @@ void dce110_timing_generator_program_blanking(
- 	uint32_t hsync_offset = timing->h_border_right +
- 			timing->h_front_porch;
- 	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
-@@ -969,7 +978,7 @@ void dce110_timing_generator_set_test_pattern(
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value;
- 	uint32_t addr;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	/* TODO: add support for other test patterns */
- 	switch (test_pattern) {
-@@ -1037,6 +1046,8 @@ bool dce110_timing_generator_validate_timing(
- 			timing->h_front_porch;
- 	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
- 
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
- 	ASSERT(timing != NULL);
- 
- 	if (!timing)
-@@ -1047,18 +1058,18 @@ bool dce110_timing_generator_validate_timing(
- 	 * needs more than 8192 horizontal and
- 	 * more than 8192 vertical total pixels)
- 	 */
--	if (timing->h_total > tg->max_h_total ||
--		timing->v_total > tg->max_v_total)
-+	if (timing->h_total > tg110->max_h_total ||
-+		timing->v_total > tg110->max_v_total)
- 		return false;
- 
- 	h_blank = (timing->h_total - timing->h_addressable -
- 		timing->h_border_right -
- 		timing->h_border_left);
- 
--	if (h_blank < tg->min_h_blank)
-+	if (h_blank < tg110->min_h_blank)
- 		return false;
- 
--	if (timing->h_front_porch < tg->min_h_front_porch)
-+	if (timing->h_front_porch < tg110->min_h_front_porch)
- 		return false;
- 
- 	h_back_porch = h_blank - (h_sync_start -
-@@ -1066,7 +1077,7 @@ bool dce110_timing_generator_validate_timing(
- 		timing->h_border_right -
- 		timing->h_sync_width);
- 
--	if (h_back_porch < tg->min_h_back_porch)
-+	if (h_back_porch < tg110->min_h_back_porch)
- 		return false;
- 
- 	return true;
-@@ -1109,63 +1120,35 @@ void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg)
- 	}
- }
- 
--void dce110_timing_generator_destroy(struct timing_generator **tg)
--{
--	dc_service_free((*tg)->ctx, FROM_TIMING_GENERATOR(*tg));
--	*tg = NULL;
--}
--
--static bool timing_generator_dce110_construct(struct timing_generator *tg,
--	struct dc_context *ctx,
-+bool dce110_timing_generator_construct(
-+	struct dce110_timing_generator *tg110,
- 	struct adapter_service *as,
--	enum controller_id id)
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets)
- {
--	if (!as)
-+	if (!tg110)
- 		return false;
- 
--	switch (id) {
--	case CONTROLLER_ID_D0:
--	case CONTROLLER_ID_D1:
--	case CONTROLLER_ID_D2:
--		break;
--	default:
-+	if (!as)
- 		return false;
--	}
- 
--	if (!dce110_timing_generator_construct(tg, id))
--		return false;
-+	tg110->controller_id = CONTROLLER_ID_D0 + instance;
-+	tg110->offsets = *offsets;
- 
--	tg->ctx = ctx;
--	tg->bp = dal_adapter_service_get_bios_parser(as);
-+	tg110->base.funcs = &dce110_tg_funcs;
- 
--	tg->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
--	tg->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = dal_adapter_service_get_bios_parser(as);
- 
--	tg->min_h_blank = 56;
--	tg->min_h_front_porch = 4;
--	tg->min_h_back_porch = 4;
-+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
- 
--	return true;
--}
-+	tg110->min_h_blank = 56;
-+	tg110->min_h_front_porch = 4;
-+	tg110->min_h_back_porch = 4;
- 
--struct timing_generator *dce110_timing_generator_create(
--	struct adapter_service *as,
--	struct dc_context *ctx,
--	enum controller_id id)
--{
--	struct dce110_timing_generator *tg =
--		dc_service_alloc(ctx, sizeof(struct dce110_timing_generator));
--
--	if (!tg)
--		return NULL;
--
--	if (timing_generator_dce110_construct(&tg->base, ctx,
--				as, id))
--		return &tg->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, tg);
--	return NULL;
-+	return true;
- }
- 
- /**
-@@ -1185,7 +1168,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	const struct dcp_gsl_params *gsl_params)
- {
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
- 	uint32_t check_point = FLIP_READY_BACK_LOOKUP;
- 
-@@ -1267,7 +1250,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 	 */
- 
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
- 
- 	value = 0;
-@@ -1365,11 +1348,11 @@ void dce110_timing_generator_enable_advanced_request(
- 	bool enable,
- 	const struct dc_crtc_timing *timing)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
--	if (enable && FROM_TIMING_GENERATOR(tg)->advanced_request_enable) {
-+	if (enable && DCE110TG_FROM_TG(tg)->advanced_request_enable) {
- 		set_reg_field_value(
- 			value,
- 			0,
-@@ -1427,7 +1410,7 @@ void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
- 		bool lock)
- {
- 	struct dc_context *ctx = tg->ctx;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -1449,7 +1432,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 	uint32_t rising_edge = 0;
- 	uint32_t falling_edge = 0;
- 	enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	/* Setup trigger edge */
- 	switch (trigger_params->edge) {
-@@ -1560,7 +1543,7 @@ void dce110_timing_generator_disable_reset_trigger(
- 	struct timing_generator *tg)
- {
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
-@@ -1609,7 +1592,7 @@ void dce110_timing_generator_disable_reset_trigger(
- bool dce110_timing_generator_did_triggered_reset_occur(
- 	struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t value = dal_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
-@@ -1629,7 +1612,9 @@ void dce110_timing_generator_disable_vga(
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 
--	switch (tg->controller_id) {
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	switch (tg110->controller_id) {
- 	case CONTROLLER_ID_D0:
- 		addr = mmD1VGA_CONTROL;
- 		break;
-@@ -1653,7 +1638,6 @@ void dce110_timing_generator_disable_vga(
- 	dal_write_reg(tg->ctx, addr, value);
- }
- 
--
- /**
- * set_overscan_color_black
- *
-@@ -1669,7 +1653,7 @@ void dce110_timing_generator_set_overscan_color_black(
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
- 	uint32_t addr;
--	struct dce110_timing_generator *tg110 = FROM_TIMING_GENERATOR(tg);
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	/* Overscan Color for YUV display modes:
- 	 * to achieve a black color for both the explicit and implicit overscan,
- 	 * the overscan color registers should be programmed to: */
-@@ -1788,3 +1772,126 @@ void dce110_timing_generator_set_overscan_color_black(
- 
- }
- 
-+void dce110_tg_program_blank_color(struct timing_generator *tg,
-+		const struct crtc_black_color *black_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
-+	uint32_t value = dal_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color->black_color_b_cb,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color->black_color_g_y,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color->black_color_r_cr,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dal_write_reg(tg->ctx, addr, value);
-+
-+	addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR);
-+	dal_write_reg(tg->ctx, addr, value);
-+}
-+
-+void dce110_tg_set_overscan_color(struct timing_generator *tg,
-+	const struct crtc_black_color *overscan_color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->black_color_b_cb,
-+		CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_BLUE);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->black_color_g_y,
-+		CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_GREEN);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->black_color_r_cr,
-+		CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_RED);
-+
-+	addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR);
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_tg_get_position(struct timing_generator *tg,
-+	struct crtc_position *position)
-+{
-+	int32_t h_position;
-+	int32_t v_position;
-+
-+	dce110_timing_generator_get_crtc_positions(tg, &h_position, &v_position);
-+
-+	position->horizontal_count = (uint32_t)h_position;
-+	position->vertical_count = (uint32_t)v_position;
-+}
-+
-+void dce110_tg_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (use_vbios)
-+		dce110_timing_generator_program_timing_generator(tg, timing);
-+	else
-+		dce110_timing_generator_program_blanking(tg, timing);
-+}
-+
-+bool dce110_tg_set_blank(struct timing_generator *tg,
-+		bool enable_blanking)
-+{
-+	if (enable_blanking)
-+		return dce110_timing_generator_blank_crtc(tg);
-+	else
-+		return dce110_timing_generator_unblank_crtc(tg);
-+}
-+
-+bool dce110_tg_validate_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
-+}
-+
-+
-+void dce110_tg_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state)
-+{
-+	switch (state) {
-+	case CRTC_STATE_VBLANK:
-+		dce110_timing_generator_wait_for_vblank(tg);
-+		break;
-+
-+	case CRTC_STATE_VACTIVE:
-+		dce110_timing_generator_wait_for_vactive(tg);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+void dce110_tg_set_colors(struct timing_generator *tg,
-+	const struct crtc_black_color *blank_color,
-+	const struct crtc_black_color *overscan_color)
-+{
-+	if (blank_color != NULL)
-+		dce110_tg_program_blank_color(tg, blank_color);
-+	if (overscan_color != NULL)
-+		dce110_tg_set_overscan_color(tg, overscan_color);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index c4a815f..4192972 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -58,16 +58,29 @@ struct dce110_timing_generator_offsets {
- struct dce110_timing_generator {
- 	struct timing_generator base;
- 	struct dce110_timing_generator_offsets offsets;
-+
-+	enum controller_id controller_id;
-+
-+	uint32_t max_h_total;
-+	uint32_t max_v_total;
-+
-+	uint32_t min_h_blank;
-+	uint32_t min_h_front_porch;
-+	uint32_t min_h_back_porch;
-+
- 	enum sync_source cached_gsl_group;
- 	bool advanced_request_enable;
- };
- 
--/********** Create and destroy **********/
--struct timing_generator *dce110_timing_generator_create(
-+#define DCE110TG_FROM_TG(tg)\
-+	container_of(tg, struct dce110_timing_generator, base)
-+
-+bool dce110_timing_generator_construct(
-+	struct dce110_timing_generator *tg,
- 	struct adapter_service *as,
- 	struct dc_context *ctx,
--	enum controller_id id);
--void dce110_timing_generator_destroy(struct timing_generator **tg);
-+	enum controller_id id,
-+	const struct dce110_timing_generator_offsets *offsets);
- 
- /* determine if given timing can be supported by TG */
- bool dce110_timing_generator_validate_timing(
-@@ -80,7 +93,7 @@ bool dce110_timing_generator_validate_timing(
- /* Program timing generator with given timing */
- bool dce110_timing_generator_program_timing_generator(
- 	struct timing_generator *tg,
--	struct dc_crtc_timing *dc_crtc_timing);
-+	const struct dc_crtc_timing *dc_crtc_timing);
- 
- /* Disable/Enable Timing Generator */
- bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
-@@ -140,17 +153,20 @@ bool dce110_timing_generator_did_triggered_reset_occur(
- /* TODO: Should we move it to mem_input interface? */
- bool dce110_timing_generator_blank_crtc(struct timing_generator *tg);
- bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg);
-+/* Move to enable accelerated mode */
- void dce110_timing_generator_disable_vga(struct timing_generator *tg);
--
- /* TODO: Should we move it to transform */
-+/* Fully program CRTC timing in timing generator */
- void dce110_timing_generator_program_blanking(
- 	struct timing_generator *tg,
- 	const struct dc_crtc_timing *timing);
- 
- /* TODO: Should we move it to opp? */
-+/* Combine with below and move YUV/RGB color conversion to SW layer */
- void dce110_timing_generator_program_blank_color(
- 	struct timing_generator *tg,
- 	enum color_space color_space);
-+/* Combine with above and move YUV/RGB color conversion to SW layer */
- void dce110_timing_generator_set_overscan_color_black(
- 	struct timing_generator *tg,
- 	enum color_space black_color);
-@@ -183,4 +199,31 @@ void dce110_timing_generator_enable_advanced_request(
- void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
- 		bool lock);
- 
-+void dce110_tg_program_blank_color(struct timing_generator *tg,
-+	const struct crtc_black_color *black_color);
-+
-+void dce110_tg_set_overscan_color(struct timing_generator *tg,
-+	const struct crtc_black_color *overscan_color);
-+
-+void dce110_tg_get_position(struct timing_generator *tg,
-+	struct crtc_position *position);
-+
-+void dce110_tg_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios);
-+
-+bool dce110_tg_set_blank(struct timing_generator *tg,
-+		bool enable_blanking);
-+
-+bool dce110_tg_validate_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing);
-+
-+
-+void dce110_tg_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state);
-+
-+void dce110_tg_set_colors(struct timing_generator *tg,
-+	const struct crtc_black_color *blank_color,
-+	const struct crtc_black_color *overscan_color);
-+
- #endif /* __DC_TIMING_GENERATOR_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h b/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-new file mode 100644
-index 0000000..da3e694
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-@@ -0,0 +1,30 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_GENERATOR_INTERFACE_H__
-+#define __DAL_TIMING_GENERATOR_TNTERFACE_H__
-+#include "timing_generator_types.h"
-+
-+#endif /* AMD_DAL_DEV_INCLUDE_TIMING_GENERATOR_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-index bc04acd..15773c0 100644
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-@@ -28,6 +28,7 @@
- 
- #include "include/grph_csc_types.h"
- 
-+
- /**
-  *  These parameters are required as input when doing blanking/Unblanking
- */
-@@ -134,16 +135,53 @@ enum controller_dp_test_pattern {
- 	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
- };
- 
-+enum crtc_state {
-+	CRTC_STATE_VBLANK = 0,
-+	CRTC_STATE_VACTIVE
-+};
-+
- struct timing_generator {
-+	struct timing_generator_funcs *funcs;
- 	struct bios_parser *bp;
--	enum controller_id controller_id;
- 	struct dc_context *ctx;
--	uint32_t max_h_total;
--	uint32_t max_v_total;
-+};
-+
- 
--	uint32_t min_h_blank;
--	uint32_t min_h_front_porch;
--	uint32_t min_h_back_porch;
-+struct dc_crtc_timing;
-+
-+struct timing_generator_funcs {
-+	bool (*validate_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing);
-+	void (*program_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing,
-+							bool use_vbios);
-+	bool (*enable_crtc)(struct timing_generator *tg);
-+	bool (*disable_crtc)(struct timing_generator *tg);
-+	bool (*is_counter_moving)(struct timing_generator *tg);
-+	void (*get_position)(struct timing_generator *tg,
-+								int32_t *h_position,
-+								int32_t *v_position);
-+	uint32_t (*get_frame_count)(struct timing_generator *tg);
-+	void (*set_early_control)(struct timing_generator *tg,
-+							   uint32_t early_cntl);
-+	void (*wait_for_state)(struct timing_generator *tg,
-+							enum crtc_state state);
-+	bool (*set_blank)(struct timing_generator *tg,
-+					   bool enable_blanking);
-+	void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color);
-+	void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color);
-+	void (*set_colors)(struct timing_generator *tg,
-+						const struct crtc_black_color *blank_color,
-+						const struct crtc_black_color *overscan_color);
-+
-+	void (*disable_vga)(struct timing_generator *tg);
-+	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
-+	void (*setup_global_swap_lock)(struct timing_generator *tg,
-+							const struct dcp_gsl_params *gsl_params);
-+	void (*enable_reset_trigger)(struct timing_generator *tg,
-+						const struct trigger_params *trigger_params);
-+	void (*disable_reset_trigger)(struct timing_generator *tg);
-+	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
- };
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0662-amdgpu-dce8-Update-IP-tables-to-enable-DAL-on-bonair.patch b/common/recipes-kernel/linux/files/0662-amdgpu-dce8-Update-IP-tables-to-enable-DAL-on-bonair.patch
deleted file mode 100644
index 15b39a50..00000000
--- a/common/recipes-kernel/linux/files/0662-amdgpu-dce8-Update-IP-tables-to-enable-DAL-on-bonair.patch
+++ /dev/null
@@ -1,237 +0,0 @@
-From 7f26858f4a6c4bfca0f6b2ec08db493c270825a4 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Tue, 5 Jan 2016 16:37:46 -0500
-Subject: [PATCH 0662/1110] amdgpu/dce8: Update IP tables to enable DAL on
- bonaire and hawaii
-
-Update IP tables for bonaire and hawaii to enable DAL rather than the legacy dce8 code.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   8 +-
- drivers/gpu/drm/amd/amdgpu/cik.c           | 161 +++++++++++++++++++++++++++++
- 2 files changed, 167 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 7e24cdb..a38ac17 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1388,10 +1388,14 @@ static int amdgpu_resume(struct amdgpu_device *adev)
-  */
- bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- {
--
- 	switch(adev->asic_type) {
--	case CHIP_CARRIZO:
-+#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
-+		return true;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case CHIP_CARRIZO:
- 		return true;
- #endif
- 	default:
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 009598b..7efe693 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -65,6 +65,7 @@
- #include "oss/oss_2_0_d.h"
- #include "oss/oss_2_0_sh_mask.h"
- 
-+#include "amdgpu_dm.h"
- #include "amdgpu_amdkfd.h"
- #include "amdgpu_powerplay.h"
- 
-@@ -1626,6 +1627,76 @@ static uint32_t cik_get_rev_id(struct amdgpu_device *adev)
- 		>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
- }
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+static const struct amdgpu_ip_block_version bonaire_ip_blocks_dal[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 1,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cik_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 7,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gmc_v7_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cik_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 7,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_dm_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 7,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &gfx_v7_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cik_sdma_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 4,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &uvd_v4_2_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vce_v2_0_ip_funcs,
-+	},
-+};
-+#endif
-+
- static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
- {
- 	/* ORDER MATTERS! */
-@@ -1694,6 +1765,76 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
- 	},
- };
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+static const struct amdgpu_ip_block_version hawaii_ip_blocks_dal[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 1,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cik_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 7,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gmc_v7_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cik_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 7,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_dm_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 7,
-+		.minor = 3,
-+		.rev = 0,
-+		.funcs = &gfx_v7_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &cik_sdma_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 4,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &uvd_v4_2_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vce_v2_0_ip_funcs,
-+	},
-+};
-+#endif
-+
- static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
- {
- 	/* ORDER MATTERS! */
-@@ -1970,12 +2111,32 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
- {
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+			adev->ip_blocks = bonaire_ip_blocks_dal;
-+			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_dal);
-+		} else {
-+			adev->ip_blocks = bonaire_ip_blocks;
-+			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
-+		}
-+#else
- 		adev->ip_blocks = bonaire_ip_blocks;
- 		adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
-+#endif
- 		break;
- 	case CHIP_HAWAII:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+			adev->ip_blocks = hawaii_ip_blocks_dal;
-+			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_dal);
-+		} else {
-+			adev->ip_blocks = hawaii_ip_blocks;
-+			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
-+		}
-+#else
- 		adev->ip_blocks = hawaii_ip_blocks;
- 		adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
-+#endif
- 		break;
- 	case CHIP_KAVERI:
- 		adev->ip_blocks = kaveri_ip_blocks;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch b/common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch
deleted file mode 100644
index acc6aacc..00000000
--- a/common/recipes-kernel/linux/files/0663-drm-amd-dal-Fix-and-refactor-DCE8.0-resource.patch
+++ /dev/null
@@ -1,171 +0,0 @@
-From 3f48989ca1abfcd9a60e29be1b0ea2297d74562c Mon Sep 17 00:00:00 2001
-From: Aric Cyr <aric.cyr@amd.com>
-Date: Tue, 5 Jan 2016 17:24:37 -0500
-Subject: [PATCH 0663/1110] drm/amd/dal: Fix and refactor DCE8.0 resource
-
-Signed-off-by: Aric Cyr <aric.cyr@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 46 +++++++---------------
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |  4 +-
- .../drm/amd/dal/include/timing_generator_types.h   |  2 +
- 4 files changed, 19 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index d789853..d7eea0d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -811,7 +811,7 @@ enum dc_status dce110_validate_with_context(
- 	result = dce_base_map_resources(dc, context);
- 
- 	if (result == DC_OK)
--	result = map_clock_resources(dc, context);
-+		result = map_clock_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = validate_mapped_resource(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index b47ba61..2c7c27f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -144,6 +144,8 @@ static struct timing_generator_funcs dce110_tg_funcs = {
- 		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
- 		.tear_down_global_swap_lock =
- 				dce110_timing_generator_tear_down_global_swap_lock,
-+		.enable_advanced_request =
-+				dce110_timing_generator_enable_advanced_request
- };
- 
- static const struct crtc_black_color black_color_format[] = {
-@@ -186,12 +188,6 @@ static void dce110_timing_generator_apply_front_porch_workaround(
- 	}
- }
- 
--static int32_t dce110_timing_generator_get_vsynch_and_front_porch_size(
--	const struct dc_crtc_timing *timing)
--{
--	return timing->v_sync_width + timing->v_front_porch;
--}
--
- static void dce110_timing_generator_color_space_to_black_color(
- 		enum color_space colorspace,
- 	struct crtc_black_color *black_color)
-@@ -521,7 +517,6 @@ bool dce110_timing_generator_program_timing_generator(
- 	enum bp_result result;
- 	struct bp_hw_crtc_timing_parameters bp_params;
- 	struct dc_crtc_timing patched_crtc_timing;
--	uint32_t regval;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +
-@@ -581,28 +576,7 @@ bool dce110_timing_generator_program_timing_generator(
- 
- 	program_horz_count_by_2(tg, &patched_crtc_timing);
- 
--	regval = dal_read_reg(tg->ctx,
--			CRTC_REG(mmCRTC_START_LINE_CONTROL));
--
--	if (dce110_timing_generator_get_vsynch_and_front_porch_size(&patched_crtc_timing) <= 3) {
--		set_reg_field_value(regval, 3,
--				CRTC_START_LINE_CONTROL,
--				CRTC_ADVANCED_START_LINE_POSITION);
--
--		set_reg_field_value(regval, 0,
--				CRTC_START_LINE_CONTROL,
--				CRTC_PREFETCH_EN);
--	} else {
--		set_reg_field_value(regval, 4,
--				CRTC_START_LINE_CONTROL,
--				CRTC_ADVANCED_START_LINE_POSITION);
--
--		set_reg_field_value(regval, 1,
--				CRTC_START_LINE_CONTROL,
--				CRTC_PREFETCH_EN);
--	}
--	dal_write_reg(tg->ctx,
--			CRTC_REG(mmCRTC_START_LINE_CONTROL), regval);
-+	tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing);
- 
- 	/* Enable stereo - only when we need to pack 3D frame. Other types
- 	 * of stereo handled in explicit call */
-@@ -1342,7 +1316,6 @@ bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg)
- 		return true;
- }
- 
--/*TODO: Figure out if we need this function. */
- void dce110_timing_generator_enable_advanced_request(
- 	struct timing_generator *tg,
- 	bool enable,
-@@ -1352,7 +1325,7 @@ void dce110_timing_generator_enable_advanced_request(
- 	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
- 	uint32_t value = dal_read_reg(tg->ctx, addr);
- 
--	if (enable && DCE110TG_FROM_TG(tg)->advanced_request_enable) {
-+	if (enable && !DCE110TG_FROM_TG(tg)->disable_advanced_request) {
- 		set_reg_field_value(
- 			value,
- 			0,
-@@ -1366,7 +1339,7 @@ void dce110_timing_generator_enable_advanced_request(
- 			CRTC_LEGACY_REQUESTOR_EN);
- 	}
- 
--	if (dce110_timing_generator_get_vsynch_and_front_porch_size(timing) <= 3) {
-+	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
- 		set_reg_field_value(
- 			value,
- 			3,
-@@ -1624,6 +1597,15 @@ void dce110_timing_generator_disable_vga(
- 	case CONTROLLER_ID_D2:
- 		addr = mmD3VGA_CONTROL;
- 		break;
-+	case CONTROLLER_ID_D3:
-+		addr = mmD4VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D4:
-+		addr = mmD5VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D5:
-+		addr = mmD6VGA_CONTROL;
-+		break;
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 4192972..c787530 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -69,7 +69,7 @@ struct dce110_timing_generator {
- 	uint32_t min_h_back_porch;
- 
- 	enum sync_source cached_gsl_group;
--	bool advanced_request_enable;
-+	bool disable_advanced_request;
- };
- 
- #define DCE110TG_FROM_TG(tg)\
-@@ -79,7 +79,7 @@ bool dce110_timing_generator_construct(
- 	struct dce110_timing_generator *tg,
- 	struct adapter_service *as,
- 	struct dc_context *ctx,
--	enum controller_id id,
-+	uint32_t instance,
- 	const struct dce110_timing_generator_offsets *offsets);
- 
- /* determine if given timing can be supported by TG */
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-index 15773c0..3f5f1ec 100644
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-@@ -182,6 +182,8 @@ struct timing_generator_funcs {
- 						const struct trigger_params *trigger_params);
- 	void (*disable_reset_trigger)(struct timing_generator *tg);
- 	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
-+	void (*enable_advanced_request)(struct timing_generator *tg,
-+					bool enable, const struct dc_crtc_timing *timing);
- };
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0664-drm-amd-dal-save-MST-connection-type-in-link.patch b/common/recipes-kernel/linux/files/0664-drm-amd-dal-save-MST-connection-type-in-link.patch
deleted file mode 100644
index aa588c2b..00000000
--- a/common/recipes-kernel/linux/files/0664-drm-amd-dal-save-MST-connection-type-in-link.patch
+++ /dev/null
@@ -1,356 +0,0 @@
-From 1acb9372d7fb8a8adabf732fdbd676f990e06490 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 4 Jan 2016 10:53:15 +0800
-Subject: [PATCH 0664/1110] drm/amd/dal: save MST connection type in link
-
-Use existing connection type field in public instead
-of adding new fields. MST connection type already provided
-
-This is follow-up change for
-commit ece83f70387e2b6638d8e099e328599b233de4f5
-("drm/amd/dal: Properly handle sink removal")
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 214 +++++++++++----------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   2 -
- .../gpu/drm/amd/dal/include/ddc_service_types.h    |   3 +
- 3 files changed, 115 insertions(+), 104 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 3347174..94990b9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -132,7 +132,7 @@ static bool program_hpd_filter(
- 	return result;
- }
- 
--static bool detect_sink(struct core_link *link)
-+static bool detect_sink(struct core_link *link, enum dc_connection_type *type)
- {
- 	uint32_t is_hpd_high = 0;
- 	struct irq *hpd_pin;
-@@ -152,10 +152,10 @@ static bool detect_sink(struct core_link *link)
- 		hpd_pin);
- 
- 	if (is_hpd_high) {
--		link->public.type = dc_connection_single;
-+		*type = dc_connection_single;
- 		/* TODO: need to do the actual detection */
- 	} else {
--		link->public.type = dc_connection_none;
-+		*type = dc_connection_none;
- 	}
- 
- 	return true;
-@@ -470,14 +470,87 @@ static enum dc_edid_status read_edid(
- 	return edid_status;
- }
- 
-+static void dc_link_detect_dp(
-+	struct core_link *link,
-+	struct display_sink_capability *sink_caps,
-+	bool *converter_disable_audio,
-+	union audio_support *audio_support)
-+{
-+	sink_caps->signal = link_detect_sink(link);
-+	sink_caps->transaction_type =
-+		get_ddc_transaction_type(sink_caps->signal);
-+
-+	if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
-+		sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-+		detect_dp_sink_caps(link);
-+
-+		/* DP active dongles */
-+		if (is_dp_active_dongle(link->dpcd_caps.dongle_type)) {
-+			if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
-+				link->public.type = dc_connection_none;
-+				/*
-+				 * active dongle unplug processing for short irq
-+				 */
-+				link_disconnect_all_sinks(link);
-+				return;
-+			}
-+
-+			if (link->dpcd_caps.dongle_type !=
-+			DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
-+				*converter_disable_audio = true;
-+			}
-+		}
-+		if (is_mst_supported(link)) {
-+			sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-+
-+			/*
-+			 * This call will initiate MST topology discovery. Which
-+			 * will detect MST ports and add new DRM connector DRM
-+			 * framework. Then read EDID via remote i2c over aux. In
-+			 * the end, will notify DRM detect result and save EDID
-+			 * into DRM framework.
-+			 *
-+			 * .detect is called by .fill_modes.
-+			 * .fill_modes is called by user mode ioctl
-+			 * DRM_IOCTL_MODE_GETCONNECTOR.
-+			 *
-+			 * .get_modes is called by .fill_modes.
-+			 *
-+			 * call .get_modes, AMDGPU DM implementation will create
-+			 * new dc_sink and add to dc_link. For long HPD plug
-+			 * in/out, MST has its own handle.
-+			 *
-+			 * Therefore, just after dc_create, link->sink is not
-+			 * created for MST until user mode app calls
-+			 * DRM_IOCTL_MODE_GETCONNECTOR.
-+			 *
-+			 * Need check ->sink usages in case ->sink = NULL
-+			 * TODO: s3 resume check
-+			 */
-+
-+			if (dc_helpers_dp_mst_start_top_mgr(
-+				link->ctx,
-+				&link->public)) {
-+				link->public.type = dc_connection_mst_branch;
-+			} else {
-+				/* MST not supported */
-+				sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-+			}
-+		}
-+	} else {
-+		/* DP passive dongles */
-+		sink_caps->signal = dp_passive_dongle_detection(link->ddc,
-+				sink_caps,
-+				audio_support);
-+	}
-+}
-+
- void dc_link_detect(const struct dc_link *dc_link)
- {
- 	struct core_link *link = DC_LINK_TO_LINK(dc_link);
- 	struct sink_init_data sink_init_data = { 0 };
--	enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
- 	struct display_sink_capability sink_caps = { 0 };
- 	uint8_t i;
--	enum signal_type signal = SIGNAL_TYPE_NONE;
- 	bool converter_disable_audio = false;
- 	union audio_support audio_support =
- 		dal_adapter_service_get_audio_support(
-@@ -486,123 +559,57 @@ void dc_link_detect(const struct dc_link *dc_link)
- 	struct dc_context *dc_ctx = link->ctx;
- 	struct dc_sink *dc_sink;
- 	struct core_sink *sink = NULL;
-+	enum dc_connection_type new_connection_type = dc_connection_none;
- 
--	if (false == detect_sink(link)) {
-+	if (false == detect_sink(link, &new_connection_type)) {
- 		BREAK_TO_DEBUGGER();
- 		return;
- 	}
- 
--	if (link->public.type != dc_connection_none) {
-+	if (new_connection_type != dc_connection_none) {
-+		link->public.type = new_connection_type;
-+
- 		/* From Disconnected-to-Connected. */
- 		switch (link->public.connector_signal) {
- 		case SIGNAL_TYPE_HDMI_TYPE_A: {
--			transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
- 			if (audio_support.bits.HDMI_AUDIO_NATIVE)
--				signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+				sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- 			else
--				signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+				sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- 			break;
- 		}
- 
- 		case SIGNAL_TYPE_DVI_SINGLE_LINK: {
--			transaction_type = DDC_TRANSACTION_TYPE_I2C;
--			signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- 			break;
- 		}
- 
- 		case SIGNAL_TYPE_DVI_DUAL_LINK: {
--			transaction_type = DDC_TRANSACTION_TYPE_I2C;
--			signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
- 			break;
- 		}
- 
- 		case SIGNAL_TYPE_EDP: {
- 			detect_dp_sink_caps(link);
--			transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
--			signal = SIGNAL_TYPE_EDP;
-+			sink_caps.transaction_type =
-+				DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+			sink_caps.signal = SIGNAL_TYPE_EDP;
- 			break;
- 		}
- 
- 		case SIGNAL_TYPE_DISPLAY_PORT: {
--			signal = link_detect_sink(link);
--			transaction_type = get_ddc_transaction_type(
--					signal);
--
--			if (transaction_type ==
--				DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
--				signal =
--					SIGNAL_TYPE_DISPLAY_PORT;
--				detect_dp_sink_caps(link);
--
--				/* DP active dongles */
--				if (is_dp_active_dongle(
--					link->dpcd_caps.dongle_type)) {
--					if (!link->dpcd_caps.
--						sink_count.bits.SINK_COUNT) {
--						link->public.type =
--							dc_connection_none;
--						/* active dongle unplug
--						 * processing for short irq
--						 */
--						link_disconnect_all_sinks(link);
--						return;
--					}
--
--					if (link->dpcd_caps.dongle_type !=
--					DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
--						converter_disable_audio = true;
--					}
--				}
--				if (is_mst_supported(link)) {
--					signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
--
--					/*
--					 * This call will initiate MST topology
--					 * discovery. Which will detect
--					 * MST ports and add new DRM connector
--					 * DRM framework. Then read EDID via
--					 * remote i2c over aux.In the end, will
--					 * notify DRM detect result and save
--					 * EDID into DRM framework.
--					 *
--					 * .detect is called by .fill_modes.
--					 * .fill_modes is called by user mode
--					 *  ioctl DRM_IOCTL_MODE_GETCONNECTOR.
--					 *
--					 * .get_modes is called by .fill_modes.
--					 *
--					 * call .get_modes, AMDGPU DM
--					 * implementation will create new
--					 * dc_sink and add to dc_link.
--					 * For long HPD plug in/out, MST has its
--					 * own handle.
--					 *
--					 * Therefore, just after dc_create,
--					 * link->sink is not created for MST
--					 * until user mode app calls
--					 * DRM_IOCTL_MODE_GETCONNECTOR.
--					 *
--					 * Need check ->sink usages in case
--					 * ->sink = NULL
--					 * TODO: s3 resume check*/
--
--					if (dc_helpers_dp_mst_start_top_mgr(
--						link->ctx,
--						&link->public)) {
--						link->mst_enabled = true;
--						return;
--					} else {
--						/* MST not supported */
--						signal = SIGNAL_TYPE_DISPLAY_PORT;
--					}
--				}
--			}
--			else {
--				/* DP passive dongles */
--				signal = dp_passive_dongle_detection(link->ddc,
--						&sink_caps,
--						&audio_support);
--			}
-+			dc_link_detect_dp(
-+				link,
-+				&sink_caps,
-+				&converter_disable_audio,
-+				&audio_support);
-+
-+			if (link->public.type == dc_connection_mst_branch)
-+				return;
-+
- 			break;
- 		}
- 
-@@ -621,14 +628,14 @@ void dc_link_detect(const struct dc_link *dc_link)
- 
- 		dal_ddc_service_set_transaction_type(
- 						link->ddc,
--						transaction_type);
-+						sink_caps.transaction_type);
- 
- 		sink_init_data.link = &link->public;
--		sink_init_data.sink_signal = signal;
-+		sink_init_data.sink_signal = sink_caps.signal;
- 		sink_init_data.dongle_max_pix_clk =
- 			sink_caps.max_hdmi_pixel_clock;
- 		sink_init_data.converter_disable_audio =
--				converter_disable_audio;
-+			converter_disable_audio;
- 
- 		dc_sink = sink_create(&sink_init_data);
- 		if (!dc_sink) {
-@@ -704,16 +711,19 @@ void dc_link_detect(const struct dc_link *dc_link)
- 
- 	} else {
- 		/* From Connected-to-Disconnected. */
--		if (link->mst_enabled) {
-+		if (link->public.type == dc_connection_mst_branch)
- 			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
--			link->mst_enabled = false;
--		} else
-+		else
- 			link_disconnect_all_sinks(link);
-+
-+		link->public.type = dc_connection_none;
-+		sink_caps.signal = SIGNAL_TYPE_NONE;
- 	}
- 
- 	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
- 		link->public.link_index, &sink->public,
--		(signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected"));
-+		(sink_caps.signal == SIGNAL_TYPE_NONE ?
-+			"Disconnected":"Connected"));
- 
- 	return;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 26f5002..2b97d4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -226,8 +226,6 @@ struct core_link {
- 	/* MST record stream using this link */
- 	const struct core_stream *enabled_streams[MAX_SINKS_PER_LINK];
- 	uint8_t enabled_stream_count;
--
--	bool mst_enabled;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-index 21fd17e..cbdb6df 100644
---- a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-@@ -125,6 +125,9 @@ struct display_sink_capability {
- 	/* to check if we have queried the display capability
- 	 * for eDP panel already. */
- 	bool is_edp_sink_cap_valid;
-+
-+	enum ddc_transaction_type transaction_type;
-+	enum signal_type signal;
- };
- 
- struct dp_receiver_id_info {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0665-drm-amd-dal-Enable-Bonaire-on-Linux.patch b/common/recipes-kernel/linux/files/0665-drm-amd-dal-Enable-Bonaire-on-Linux.patch
deleted file mode 100644
index 2f0e1dea..00000000
--- a/common/recipes-kernel/linux/files/0665-drm-amd-dal-Enable-Bonaire-on-Linux.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From c438a2c1e0213b2fb9d6825f32a5b2f610fe176a Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Tue, 5 Jan 2016 16:22:11 -0500
-Subject: [PATCH 0665/1110] drm/amd/dal: Enable Bonaire on Linux
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index d472a17..1093ab8 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1088,6 +1088,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 
- 	/* Software is initialized. Now we can register interrupt handlers. */
- 	switch (adev->asic_type) {
-+	case CHIP_BONAIRE:
- 	case CHIP_CARRIZO:
- 		if (dce110_register_irq_handlers(dm->adev)) {
- 			DRM_ERROR("DM: Failed to initialize IRQ\n");
-@@ -1302,6 +1303,11 @@ static int dm_early_init(void *handle)
- 	amdgpu_dm_set_irq_funcs(adev);
- 
- 	switch (adev->asic_type) {
-+	case CHIP_BONAIRE:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		break;
- 	case CHIP_CARRIZO:
- 		adev->mode_info.num_crtc = 3;
- 		adev->mode_info.num_hpd = 6;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0666-drm-amd-dal-Clean-up-payload-allocation-table-creati.patch b/common/recipes-kernel/linux/files/0666-drm-amd-dal-Clean-up-payload-allocation-table-creati.patch
deleted file mode 100644
index dd004da1..00000000
--- a/common/recipes-kernel/linux/files/0666-drm-amd-dal-Clean-up-payload-allocation-table-creati.patch
+++ /dev/null
@@ -1,265 +0,0 @@
-From d81c058644e81c8ac321d3e7747c4133a78e120a Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 2 Dec 2015 23:25:25 -0500
-Subject: [PATCH 0666/1110] drm/amd/dal: Clean up payload allocation table
- creation
-
-Using mst_mgr payload's vcpi now since it's been upstreamed.
-
-Also breaking payload table creation into more readble chunks.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 201 ++++++++-------------
- 1 file changed, 80 insertions(+), 121 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 744ab94..3a71159 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -160,6 +160,84 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
-+static const struct dc_stream *get_stream_for_vcid(
-+		struct drm_device *dev,
-+		struct amdgpu_connector *master_port,
-+		int vcid)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_crtc *crtc;
-+	struct amdgpu_crtc *acrtc;
-+	struct dc_target *dc_target;
-+
-+	list_for_each_entry(
-+		connector,
-+		&dev->mode_config.connector_list,
-+		head) {
-+
-+		aconnector = to_amdgpu_connector(connector);
-+
-+		/* Check whether mst connector */
-+		if (!aconnector->mst_port)
-+			continue;
-+
-+		/* Check whether same physical connector. */
-+		if (master_port != aconnector->mst_port) {
-+			continue;
-+		}
-+
-+		if (aconnector->port->vcpi.vcpi == vcid) {
-+			crtc = aconnector->base.state->crtc;
-+			acrtc = to_amdgpu_crtc(crtc);
-+			dc_target = acrtc->target;
-+			return dc_target->streams[0];
-+		}
-+	}
-+	return NULL;
-+}
-+
-+static void get_payload_table(
-+		struct drm_device *dev,
-+		struct amdgpu_connector *aconnector,
-+		struct dp_mst_stream_allocation_table *table)
-+{
-+	int i;
-+	struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
-+	struct amdgpu_connector *master_port = aconnector->mst_port;
-+
-+	mutex_lock(&mst_mgr->payload_lock);
-+
-+	/* number of active streams */
-+	for (i = 0; i < mst_mgr->max_payloads; i++) {
-+		if (mst_mgr->payloads[i].num_slots == 0)
-+			break;
-+
-+		if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
-+				mst_mgr->payloads[i].payload_state == DP_PAYLOAD_REMOTE) {
-+			table->stream_allocations[i].slot_count = mst_mgr->payloads[i].num_slots;
-+			table->stream_allocations[i].stream =
-+					get_stream_for_vcid(
-+							dev,
-+							master_port,
-+							mst_mgr->payloads[i].vcpi);
-+
-+			if (mst_mgr->payloads[i].vcpi ==
-+					aconnector->port->vcpi.vcpi)
-+				table->cur_stream_payload_idx = i;
-+
-+			/* TODO remove the following and calculate in DC */
-+			table->stream_allocations[i].pbn_per_slot = mst_mgr->pbn_div;
-+			table->stream_allocations[i].pbn = mst_mgr->proposed_vcpis[i]->pbn;
-+		}
-+	}
-+
-+	table->stream_count = i;
-+
-+	mutex_unlock(&mst_mgr->payload_lock);
-+
-+}
-+
- /*
-  * Writes payload allocation table in immediate downstream device.
-  */
-@@ -172,28 +250,20 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
--	struct drm_connector *connector;
--	struct amdgpu_crtc *amdgpu_crtc;
--	struct drm_crtc *crtc;
- 	struct drm_dp_mst_topology_mgr *mst_mgr;
- 	struct drm_dp_mst_port *mst_port;
--	struct amdgpu_connector *master_port;
- 	int slots = 0;
- 	bool ret;
- 	int clock;
- 	int bpp = 0;
- 	int pbn = 0;
--	uint8_t i;
--	uint8_t vcid = 0;
--	bool find_stream_for_sink;
- 
- 	aconnector = get_connector_for_sink(dev, stream->sink);
- 
- 	if (!aconnector->mst_port)
- 		return false;
- 
--	master_port = aconnector->mst_port;
--	mst_mgr = &master_port->mst_mgr;
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
- 
- 	if (!mst_mgr->mst_state)
- 		return false;
-@@ -235,8 +305,6 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		pbn = drm_dp_calc_pbn_mode(clock, bpp);
- 
- 		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, &slots);
--		/* mst_port->vcpi.vcpi is vc_id for this stream.*/
--		vcid = mst_port->vcpi.vcpi;
- 
- 		if (!ret)
- 			return false;
-@@ -252,116 +320,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	 * stream. AMD ASIC stream slot allocation should follow the same
- 	 * sequence. copy DRM MST allocation to dc */
- 
--	mutex_lock(&mst_mgr->payload_lock);
--
--	/* number of active streams */
--	for (i = 0; i < mst_mgr->max_payloads; i++) {
--		if (mst_mgr->payloads[i].num_slots == 0)
--			break;
--	}
--
--	table->stream_count = i;
--
--	for (i = 0; i < table->stream_count; i++) {
--		table->stream_allocations[i].slot_count =
--				mst_mgr->proposed_vcpis[i]->num_slots;
--		/*
--		 * mst_mgr->pbn_div is fixed value after link training for
--		 * current link PHY
--		 */
--		table->stream_allocations[i].pbn_per_slot = mst_mgr->pbn_div;
--
--		/*
--		 * find which payload is for current stream after
--		 * drm_dp_update_payload_part1, payload and proposed_vcpis
--		 * are sync to the same allocation sequence. vcpi is not saved
--		 * into payload by drm_dp_update_payload_part1. In order to
--		 * find sequence of a payload within allocation sequence, we
--		 * need check vcpi from proposed_vcpis
--		 */
--
--		table->stream_allocations[i].pbn =
--				mst_mgr->proposed_vcpis[i]->pbn;
--
--		if (mst_mgr->proposed_vcpis[i]->vcpi == vcid)
--			table->cur_stream_payload_idx = i;
--
--		find_stream_for_sink = false;
--
--		list_for_each_entry(
--			connector,
--			&dev->mode_config.connector_list,
--			head) {
--			const struct dc_sink *dc_sink;
--			struct dc_target *dc_target;
--			uint8_t j;
--
--			aconnector = to_amdgpu_connector(connector);
--
--			/* not mst connector */
--			if (!aconnector->mst_port)
--				continue;
--
--			if (master_port != aconnector->mst_port) {
--				/* Not the same physical connector. */
--				continue;
--			}
--
--			mst_port = aconnector->port;
--
--			if (mst_port->vcpi.vcpi !=
--					mst_mgr->proposed_vcpis[i]->vcpi)
--				continue;
--
--			/* find connector with same vcid as payload */
--
--			dc_sink = aconnector->dc_sink;
--
--			/*
--			 * find stream to drive this sink
--			 * crtc -> target -> stream -> sink
--			 */
--			crtc = aconnector->base.state->crtc;
--
--			/*
--			 * this situation can happen when crtc moved from one
--			 * connector to another for any reason
--			 */
--			if (!crtc)
--				continue;
--
--			amdgpu_crtc = to_amdgpu_crtc(crtc);
--			dc_target = amdgpu_crtc->target;
--
--			for (j = 0; j < dc_target->stream_count; j++) {
--				if (dc_target->streams[j]->sink ==
--					dc_sink)
--					break;
--			}
--
--			if (j < dc_target->stream_count) {
--				/*
--				 * find sink --> stream --> target -->
--				 * connector
--				 */
--				table->stream_allocations[i].stream =
--					dc_target->streams[j];
--				/* exit loop connector */
--				find_stream_for_sink = true;
--				break;
--			}
--		}
--
--		if (!find_stream_for_sink) {
--			/*
--			 * TODO: do not find stream for sink. This should not
--			 * happen
--			 */
--			ASSERT(0);
--		}
--	}
--
--	mutex_unlock(&mst_mgr->payload_lock);
-+	get_payload_table(dev, aconnector, table);
- 
- 	if (ret)
- 		return false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0667-drm-amd-dal-Deallocate-dc-ctx-upon-destruct.patch b/common/recipes-kernel/linux/files/0667-drm-amd-dal-Deallocate-dc-ctx-upon-destruct.patch
deleted file mode 100644
index 54bd9ae2..00000000
--- a/common/recipes-kernel/linux/files/0667-drm-amd-dal-Deallocate-dc-ctx-upon-destruct.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From b95ac9aabb5be346a107ac4d9f8e12c0aefe62f3 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 6 Jan 2016 11:37:40 -0500
-Subject: [PATCH 0667/1110] drm/amd/dal: Deallocate dc->ctx upon destruct
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 662df13..96ec35f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -362,6 +362,7 @@ static void destruct(struct dc *dc)
- 	dc_service_free(dc->ctx, dc->links);
- 	dc->hwss.destruct_resource_pool(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
-+	dc_service_free(dc->ctx, dc->ctx);
- }
- 
- /*******************************************************************************
-@@ -397,8 +398,9 @@ alloc_fail:
- 
- void dc_destroy(struct dc **dc)
- {
-+	struct dc_context ctx = *(*dc)->ctx;
- 	destruct(*dc);
--	dc_service_free((*dc)->ctx, *dc);
-+	dc_service_free(&ctx, *dc);
- 	*dc = NULL;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0668-drm-amd-dal-Compute-x-y-for-MST-in-dc_link.patch b/common/recipes-kernel/linux/files/0668-drm-amd-dal-Compute-x-y-for-MST-in-dc_link.patch
deleted file mode 100644
index 29597e77..00000000
--- a/common/recipes-kernel/linux/files/0668-drm-amd-dal-Compute-x-y-for-MST-in-dc_link.patch
+++ /dev/null
@@ -1,167 +0,0 @@
-From 489af48fca5911be0db30127181a2c11bff9772d Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 3 Dec 2015 00:18:30 -0500
-Subject: [PATCH 0668/1110] drm/amd/dal: Compute x/y for MST in dc_link
-
-Computing x/y for MST more accurately, based on DAL2 code,
-rather than doing what radeon driver did.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  |  8 ---
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 69 ++++++++++++++++++++--
- .../gpu/drm/amd/dal/include/link_service_types.h   |  3 -
- 3 files changed, 63 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 3a71159..578517f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -221,14 +221,6 @@ static void get_payload_table(
- 							dev,
- 							master_port,
- 							mst_mgr->payloads[i].vcpi);
--
--			if (mst_mgr->payloads[i].vcpi ==
--					aconnector->port->vcpi.vcpi)
--				table->cur_stream_payload_idx = i;
--
--			/* TODO remove the following and calculate in DC */
--			table->stream_allocations[i].pbn_per_slot = mst_mgr->pbn_div;
--			table->stream_allocations[i].pbn = mst_mgr->proposed_vcpis[i]->pbn;
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 94990b9..5e39a41 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -37,6 +37,7 @@
- #include "stream_encoder.h"
- #include "link_encoder.h"
- #include "hw_sequencer.h"
-+#include "fixed31_32.h"
- 
- 
- #define LINK_INFO(...) \
-@@ -52,6 +53,10 @@
-  * Private structures
-  ******************************************************************************/
- 
-+enum {
-+	LINK_RATE_REF_FREQ_IN_MHZ = 27,
-+	PEAK_FACTOR_X1000 = 1006
-+};
- 
- /*******************************************************************************
-  * Private functions
-@@ -1275,6 +1280,59 @@ void core_link_resume(struct core_link *link)
- 	program_hpd_filter(link);
- }
- 
-+static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
-+{
-+	struct link_settings *link_settings = &stream->sink->link->cur_link_settings;
-+	uint32_t link_rate_in_mbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
-+	struct fixed31_32 mbps = dal_fixed31_32_from_int(link_rate_in_mbps * link_settings->lane_count);
-+
-+	return dal_fixed31_32_div_int(mbps, 54);
-+}
-+
-+static int get_color_depth(struct core_stream *stream)
-+{
-+	switch (stream->pix_clk_params.color_depth) {
-+	case COLOR_DEPTH_666: return 6;
-+	case COLOR_DEPTH_888: return 8;
-+	case COLOR_DEPTH_101010: return 10;
-+	case COLOR_DEPTH_121212: return 12;
-+	case COLOR_DEPTH_141414: return 14;
-+	case COLOR_DEPTH_161616: return 16;
-+	default: return 0;
-+	}
-+}
-+
-+static struct fixed31_32 get_pbn_from_timing(struct core_stream *stream)
-+{
-+	uint32_t bpc;
-+	uint64_t kbps;
-+	struct fixed31_32 peak_kbps;
-+	uint32_t numerator;
-+	uint32_t denominator;
-+
-+	bpc = get_color_depth(stream);
-+	kbps = stream->pix_clk_params.requested_pix_clk * bpc * 3;
-+
-+	/*
-+	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
-+	 *
-+	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
-+	 * common multiplier to render an integer PBN for all link rate/lane
-+	 * counts combinations
-+	 * 	 *
-+	 * calculate
-+	 * 	peak_kbps *= (1006/1000)
-+	 * 	peak_kbps *= (64/54)
-+	 * 	peak_kbps *= 8    convert to bytes
-+	 */
-+
-+	numerator = 64 * PEAK_FACTOR_X1000;
-+	denominator = 54 * 8 * 1000 * 1000;
-+	kbps *= numerator;
-+	peak_kbps = dal_fixed31_32_from_fraction(kbps, denominator);
-+
-+	return peak_kbps;
-+}
- 
- static enum dc_status allocate_mst_payload(struct core_stream *stream)
- {
-@@ -1283,8 +1341,9 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
- 	struct dp_mst_stream_allocation_table table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp;
--	uint8_t cur_stream_payload_idx;
- 	struct dc *dc = stream->ctx->dc;
-+	struct fixed31_32 pbn;
-+	struct fixed31_32 pbn_per_slot;
- 
- 	/* enable_link_dp_mst already check link->enabled_stream_count
- 	 * and stream is in link->stream[]. This is called during set mode,
-@@ -1322,11 +1381,9 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 			&stream->public,
- 			true);
- 
--	/* slot X.Y for only current stream */
--	cur_stream_payload_idx = table.cur_stream_payload_idx;
--	avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
--		table.stream_allocations[cur_stream_payload_idx].pbn,
--		table.stream_allocations[cur_stream_payload_idx].pbn_per_slot);
-+	pbn_per_slot = get_pbn_per_slot(stream);
-+	pbn = get_pbn_from_timing(stream);
-+	avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
- 
- 	dc->hwss.set_mst_bandwidth(
- 		stream_encoder,
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index d91f4b0..429d969 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -396,15 +396,12 @@ struct dp_mst_stream_allocation {
- 	/* number of slots required for the DP stream in
- 	 * transport packet */
- 	uint32_t slot_count;
--	uint32_t pbn;
--	uint32_t pbn_per_slot;
- };
- 
- /* DP MST stream allocation table */
- struct dp_mst_stream_allocation_table {
- 	/* number of DP video streams */
- 	uint8_t stream_count;
--	uint8_t cur_stream_payload_idx;
- 	/* array of stream allocations */
- 	struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0669-drm-amd-dal-Balance-dc-surface-reference-count.patch b/common/recipes-kernel/linux/files/0669-drm-amd-dal-Balance-dc-surface-reference-count.patch
deleted file mode 100644
index 837b2bcb..00000000
--- a/common/recipes-kernel/linux/files/0669-drm-amd-dal-Balance-dc-surface-reference-count.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 3a59831ac84fbcc1d02d4a3b3ecd2077bcd81ee4 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Wed, 6 Jan 2016 15:49:08 -0500
-Subject: [PATCH 0669/1110] drm/amd/dal: Balance dc surface reference count.
-
-This resolves memory leak because of double increment of
-surface reference count in dc_commit_surfaces_to_target().
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 5 +++--
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c   | 2 +-
- 2 files changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index ab081c1..1ad317a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -388,8 +388,9 @@ bool logical_attach_surfaces_to_target(
- 	uint8_t i;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
- 
--	if (target->status.surface_count >= MAX_SURFACE_NUM) {
--		dal_error("Surface: this target has too many surfaces!\n");
-+	if (surface_count > MAX_SURFACE_NUM) {
-+		dal_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
-+			surface_count, MAX_SURFACE_NUM);
- 		return false;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 433f712..31374ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -259,7 +259,6 @@ bool dc_commit_surfaces_to_target(
- 					LOG_MINOR_COMPONENT_DC,
- 					"0x%x:",
- 					surface);
--		dc_surface_retain(surface);
- 
- 		program_gamma(dc->ctx, surface,
- 			DC_STREAM_TO_CORE(target->public.streams[0])->ipp,
-@@ -271,6 +270,7 @@ bool dc_commit_surfaces_to_target(
- 
- 		dc->hwss.update_plane_address(core_surface, target);
- 	}
-+
- 	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
- 		dc_target_enable_memory_requests(dc_target);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0670-drm-amd-dal-Reuse-MST-connectors-to-resolve-headless.patch b/common/recipes-kernel/linux/files/0670-drm-amd-dal-Reuse-MST-connectors-to-resolve-headless.patch
deleted file mode 100644
index 25edd9e4..00000000
--- a/common/recipes-kernel/linux/files/0670-drm-amd-dal-Reuse-MST-connectors-to-resolve-headless.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 482cbc6b1bcc9f633ec2cde2ef7f968c10d96500 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 5 Jan 2016 19:59:00 -0500
-Subject: [PATCH 0670/1110] drm/amd/dal: Reuse MST connectors to resolve
- headless issues
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 57 +++++++++++++---------
- 1 file changed, 34 insertions(+), 23 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index e7b675e..1d1cd48 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -270,6 +270,24 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	struct amdgpu_connector *aconnector;
- 	struct drm_connector *connector;
- 
-+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-+	drm_for_each_connector(connector, dev) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (aconnector->mst_port == master
-+				&& !aconnector->port) {
-+			DRM_INFO("DM_MST: reusing connector: %p [id: %d] [master: %p]\n",
-+						aconnector, connector->base.id, aconnector->mst_port);
-+
-+			aconnector->port = port;
-+			drm_mode_connector_set_path_property(connector, pathprop);
-+
-+			drm_modeset_unlock(&dev->mode_config.connection_mutex);
-+			return &aconnector->base;
-+		}
-+	}
-+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
-+
-+
- 	aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
- 	if (!aconnector)
- 		return NULL;
-@@ -329,31 +347,13 @@ static void dm_dp_destroy_mst_connector(
- 	struct drm_dp_mst_topology_mgr *mgr,
- 	struct drm_connector *connector)
- {
--	struct amdgpu_connector *master =
--		container_of(mgr, struct amdgpu_connector, mst_mgr);
- 	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
--	struct drm_device *dev = master->base.dev;
--	struct amdgpu_device *adev = dev->dev_private;
--
--	DRM_INFO("DM_MST: destroying connector: %p [id: %d] [master: %p]\n",
--			aconnector, connector->base.id, aconnector->mst_port);
- 
--	drm_connector_unregister(connector);
--	/* need to nuke the connector */
--	drm_modeset_lock_all(dev);
--	/* dpms off */
--	drm_fb_helper_remove_one_connector(
--		&adev->mode_info.rfbdev->helper,
--		connector);
--
--	drm_connector_cleanup(connector);
--	drm_modeset_unlock_all(dev);
-+	DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
-+				aconnector, connector->base.id, aconnector->mst_port);
- 
--	if (aconnector->dc_sink)
--		dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
--
--	kfree(aconnector);
--	DRM_DEBUG_KMS("\n");
-+	aconnector->port = NULL;
-+	aconnector->edid = NULL;
- }
- 
- static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-@@ -369,10 +369,21 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector)
- {
- 	struct drm_device *dev = connector->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
-+	int i;
- 
- 	drm_modeset_lock_all(dev);
--	if (adev->mode_info.rfbdev)
-+	if (adev->mode_info.rfbdev) {
-+		/*Do not add if already registered in past*/
-+		for (i = 0; i < adev->mode_info.rfbdev->helper.connector_count; i++) {
-+			if (adev->mode_info.rfbdev->helper.connector_info[i]->connector
-+					== connector) {
-+				drm_modeset_unlock_all(dev);
-+				return;
-+			}
-+		}
-+
- 		drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
-+	}
- 	else
- 		DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0671-drm-amd-dal-Fix-eDP-to-use-non-mst-codepath-for-link.patch b/common/recipes-kernel/linux/files/0671-drm-amd-dal-Fix-eDP-to-use-non-mst-codepath-for-link.patch
deleted file mode 100644
index 667d315b..00000000
--- a/common/recipes-kernel/linux/files/0671-drm-amd-dal-Fix-eDP-to-use-non-mst-codepath-for-link.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 5a998f2872363cc1ed90b018cf89b835610dcad9 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Wed, 6 Jan 2016 17:41:42 -0500
-Subject: [PATCH 0671/1110] drm/amd/dal: Fix eDP to use non-mst codepath for
- link phy enablement
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 715aa9f..1356238 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -56,7 +56,7 @@ void dp_enable_link_phy(
- 	enum signal_type signal,
- 	const struct link_settings *link_settings)
- {
--	if (signal == SIGNAL_TYPE_DISPLAY_PORT)
-+	if (dc_is_dp_sst_signal(signal))
- 		link->dc->hwss.encoder_enable_dp_output(
- 						link->link_enc,
- 						link_settings,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0672-drm-amd-dal-disable-BM-calcs-log-by-default.patch b/common/recipes-kernel/linux/files/0672-drm-amd-dal-disable-BM-calcs-log-by-default.patch
deleted file mode 100644
index ec6b5405..00000000
--- a/common/recipes-kernel/linux/files/0672-drm-amd-dal-disable-BM-calcs-log-by-default.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From df17e72a8d5ff3f1d576e7cdd74bbf92b2c3ba64 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 7 Jan 2016 16:11:42 +0800
-Subject: [PATCH 0672/1110] drm/amd/dal: disable BM calcs log by default
-
-It is only related to verbose output, not for
-errors.
-
-Also, do not output anything in case logger
-buffer is empty. This will remove empty DRM
-output case nothing was added to buffer
-after dal_logger_open.
-
-This could happen in case dal_logger_close was
-called just after dal_logger_open, or when log
-major/minor disabled
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/basics/logger.c | 20 ++++++++++----------
- 1 file changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index b2bf14f..9c2a889 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -241,9 +241,7 @@ struct log_major_mask_info {
- 
- #define LG_SYNC_MSK (1 << LOG_MINOR_SYNC_TIMING)
- 
--#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION) | \
--		(1 << LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS)
--
-+#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION)
- 
- static const struct log_major_mask_info log_major_mask_info_tbl[] = {
- 	/* LogMajor                  major name       default     MinorTble                    tblElementCnt */
-@@ -402,13 +400,15 @@ static void log_to_debug_console(struct log_entry *entry)
- 	if (logger->flags.bits.ENABLE_CONSOLE == 0)
- 		return;
- 
--	switch (entry->major) {
--	case LOG_MAJOR_ERROR:
--		dal_error("%s", entry->buf);
--		break;
--	default:
--		dal_output_to_console("%s", entry->buf);
--		break;
-+	if (entry->buf_offset) {
-+		switch (entry->major) {
-+		case LOG_MAJOR_ERROR:
-+			dal_error("%s", entry->buf);
-+			break;
-+		default:
-+			dal_output_to_console("%s", entry->buf);
-+			break;
-+		}
- 	}
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0673-drm-amd-dal-Avoid-edid-mem-leak-by-deferring-edid-po.patch b/common/recipes-kernel/linux/files/0673-drm-amd-dal-Avoid-edid-mem-leak-by-deferring-edid-po.patch
deleted file mode 100644
index 9a9705c0..00000000
--- a/common/recipes-kernel/linux/files/0673-drm-amd-dal-Avoid-edid-mem-leak-by-deferring-edid-po.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 7600e4131a6fc695a2f5364f74db4a0b51d447b8 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 6 Jan 2016 22:44:58 -0500
-Subject: [PATCH 0673/1110] drm/amd/dal: Avoid edid mem leak by deferring edid
- pointer reset to detect hook where it's released properly.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 1d1cd48..3d36e91 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -353,7 +353,6 @@ static void dm_dp_destroy_mst_connector(
- 				aconnector, connector->base.id, aconnector->mst_port);
- 
- 	aconnector->port = NULL;
--	aconnector->edid = NULL;
- }
- 
- static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0674-drm-amd-dal-Fix-header-guard.patch b/common/recipes-kernel/linux/files/0674-drm-amd-dal-Fix-header-guard.patch
deleted file mode 100644
index ddb0732d..00000000
--- a/common/recipes-kernel/linux/files/0674-drm-amd-dal-Fix-header-guard.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From b239500427a70f85a028a77218fbf592dc7eaa73 Mon Sep 17 00:00:00 2001
-From: Ken Chalmers <ken.chalmers@amd.com>
-Date: Thu, 7 Jan 2016 13:32:12 -0500
-Subject: [PATCH 0674/1110] drm/amd/dal: Fix header guard
-
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/include/timing_generator_interface.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h b/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-index da3e694..32d545d 100644
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-@@ -24,7 +24,7 @@
-  */
- 
- #ifndef __DAL_TIMING_GENERATOR_INTERFACE_H__
--#define __DAL_TIMING_GENERATOR_TNTERFACE_H__
-+#define __DAL_TIMING_GENERATOR_INTERFACE_H__
- #include "timing_generator_types.h"
- 
- #endif /* AMD_DAL_DEV_INCLUDE_TIMING_GENERATOR_INTERFACE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0675-drm-amd-dal-fix-in-stream-encoder-allocation.patch b/common/recipes-kernel/linux/files/0675-drm-amd-dal-fix-in-stream-encoder-allocation.patch
deleted file mode 100644
index 610aca0a..00000000
--- a/common/recipes-kernel/linux/files/0675-drm-amd-dal-fix-in-stream-encoder-allocation.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From dd54dd6d5d123f4e3fa6abda61a96a740342b7bb Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 7 Jan 2016 18:39:43 +0800
-Subject: [PATCH 0675/1110] drm/amd/dal: fix in stream encoder allocation
-
-In case preferred stream for non-MST link already
-acquired, pick-up left free stream encoder
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-index 3633402..1b091be 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -106,10 +106,19 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
- 		}
- 	}
- 
--	/* TODO: Handle MST properly
--	 * Currently pick next available stream encoder if found*/
--	if (j >= 0 && link->public.sink[0]->sink_signal ==
--			SIGNAL_TYPE_DISPLAY_PORT_MST)
-+	/*
-+	 * below can happen in cases when stream encoder is acquired:
-+	 * 1) for second MST display in chain, so preferred engine already
-+	 * acquired;
-+	 * 2) for another link, which preferred engine already acquired by any
-+	 * MST configuration.
-+	 *
-+	 * If signal is of DP type and preferred engine not found, return last available
-+	 *
-+	 * TODO - This is just a patch up and a generic solution is
-+	 * required for non DP connectors.
-+	 */
-+	if (j >= 0 &&  dc_is_dp_signal(link->public.sink[0]->sink_signal))
- 		return res_ctx->pool.stream_enc[j];
- 
- 	return NULL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0676-drm-amd-dal-Release-sink-for-MST-connector-when-rese.patch b/common/recipes-kernel/linux/files/0676-drm-amd-dal-Release-sink-for-MST-connector-when-rese.patch
deleted file mode 100644
index a16b6003..00000000
--- a/common/recipes-kernel/linux/files/0676-drm-amd-dal-Release-sink-for-MST-connector-when-rese.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6b700407c7a426c98575368f2ca3489db1358fc8 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Thu, 7 Jan 2016 17:08:15 -0500
-Subject: [PATCH 0676/1110] drm/amd/dal: Release sink for MST connector when
- resetting the connector.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c           | 5 +++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++
- 2 files changed, 7 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 1093ab8..a98d1dd 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -789,8 +789,13 @@ static void handle_hpd_irq(void *param)
- 	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
-+	bool mst_connector = aconnector->mst_mgr.mst_state;
- 
- 	dc_link_detect(aconnector->dc_link);
-+	/*Wait for complition of all MST connectors reset
-+	 * so the link is clean from sinks. */
-+	if (mst_connector && aconnector->dc_link->type == dc_connection_none)
-+		flush_work(&aconnector->mst_mgr.destroy_connector_work);
- 	amdgpu_dm_update_connector_after_detect(aconnector);
- 	drm_kms_helper_hotplug_event(dev);
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 3d36e91..80bd0c6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -353,6 +353,8 @@ static void dm_dp_destroy_mst_connector(
- 				aconnector, connector->base.id, aconnector->mst_port);
- 
- 	aconnector->port = NULL;
-+	if (aconnector->dc_sink)
-+		dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
- }
- 
- static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0677-drm-amd-dal-Fix-issue-with-sink-being-added-to-link-.patch b/common/recipes-kernel/linux/files/0677-drm-amd-dal-Fix-issue-with-sink-being-added-to-link-.patch
deleted file mode 100644
index 3a669073..00000000
--- a/common/recipes-kernel/linux/files/0677-drm-amd-dal-Fix-issue-with-sink-being-added-to-link-.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From c8a6b99b04833217438fd1bc18a6655ae96855e6 Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Thu, 7 Jan 2016 16:47:25 -0500
-Subject: [PATCH 0677/1110] drm/amd/dal: Fix issue with sink being added to
- link on each dc_link_detect
-
-In normal hotplug case, all sinks are removed from link on disconnect.
-On connect, new sinks are added to link.
-
-If there is force triggered detection, such as on S3 resume, there may be
-existing sink when dc_link_detect is called. In this case, existing code
-keeps adding more sinks to link.
-
-This change assumes dc_link_detect will detect the correct new state and
-add the new sinks properly.
-So at the start of dc_link_detect, we should first detach all existing sinks.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 5e39a41..5f24ef1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -571,6 +571,11 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		return;
- 	}
- 
-+	/* Free existing state before doing detection on SST
-+	 * TODO: For MST, need to investigate if the same is required. */
-+	if (link->public.type != dc_connection_mst_branch)
-+		link_disconnect_all_sinks(link);
-+
- 	if (new_connection_type != dc_connection_none) {
- 		link->public.type = new_connection_type;
- 
-@@ -718,8 +723,6 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		/* From Connected-to-Disconnected. */
- 		if (link->public.type == dc_connection_mst_branch)
- 			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
--		else
--			link_disconnect_all_sinks(link);
- 
- 		link->public.type = dc_connection_none;
- 		sink_caps.signal = SIGNAL_TYPE_NONE;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0678-drm-amd-dal-disable-hpd-filtering-on-DP-connectors.patch b/common/recipes-kernel/linux/files/0678-drm-amd-dal-disable-hpd-filtering-on-DP-connectors.patch
deleted file mode 100644
index 66b26fb5..00000000
--- a/common/recipes-kernel/linux/files/0678-drm-amd-dal-disable-hpd-filtering-on-DP-connectors.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 6284910be3b672cccb130746c82bb32d531dd707 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 7 Jan 2016 16:18:57 +0800
-Subject: [PATCH 0678/1110] drm/amd/dal: disable hpd filtering on DP connectors
-
-Also, decrease disconnect filter time to default value
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 5f24ef1..ac6785a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -46,7 +46,7 @@
- 		__VA_ARGS__)
- 
- #define DELAY_ON_CONNECT_IN_MS 500
--#define DELAY_ON_DISCONNECT_IN_MS 500
-+#define DELAY_ON_DISCONNECT_IN_MS 100
- 
- 
- /*******************************************************************************
-@@ -95,12 +95,12 @@ static bool program_hpd_filter(
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/* program hpd filter */
-+		break;
- 	case SIGNAL_TYPE_LVDS:
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 	case SIGNAL_TYPE_EDP:
--		/* program hpd filter */
--		break;
- 	default:
- 		/* don't program hpd filter */
- 		return false;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0679-drm-amd-dal-MST-get-stream-hadle-refact.patch b/common/recipes-kernel/linux/files/0679-drm-amd-dal-MST-get-stream-hadle-refact.patch
deleted file mode 100644
index 6a6c82bf..00000000
--- a/common/recipes-kernel/linux/files/0679-drm-amd-dal-MST-get-stream-hadle-refact.patch
+++ /dev/null
@@ -1,498 +0,0 @@
-From ddd580e8ff564c5d5f0b4fa941f8e64e365ea0d3 Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Thu, 7 Jan 2016 15:06:08 -0500
-Subject: [PATCH 0679/1110] drm/amd/dal: MST get stream hadle refact
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  |  94 ++++++-------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 147 +++++++++++++++------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  11 +-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |   3 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   2 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   7 +-
- .../gpu/drm/amd/dal/include/link_service_types.h   |   1 +
- 7 files changed, 167 insertions(+), 98 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 578517f..ff9b5c1 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -160,74 +160,73 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
--static const struct dc_stream *get_stream_for_vcid(
--		struct drm_device *dev,
--		struct amdgpu_connector *master_port,
--		int vcid)
-+const struct dp_mst_stream_allocation *find_stream_with_matching_vcpi(
-+	const struct dp_mst_stream_allocation_table *table,
-+	uint32_t vcpi)
- {
--	struct drm_connector *connector;
--	struct amdgpu_connector *aconnector;
--	struct drm_crtc *crtc;
--	struct amdgpu_crtc *acrtc;
--	struct dc_target *dc_target;
--
--	list_for_each_entry(
--		connector,
--		&dev->mode_config.connector_list,
--		head) {
--
--		aconnector = to_amdgpu_connector(connector);
--
--		/* Check whether mst connector */
--		if (!aconnector->mst_port)
--			continue;
--
--		/* Check whether same physical connector. */
--		if (master_port != aconnector->mst_port) {
--			continue;
--		}
-+	int i;
- 
--		if (aconnector->port->vcpi.vcpi == vcid) {
--			crtc = aconnector->base.state->crtc;
--			acrtc = to_amdgpu_crtc(crtc);
--			dc_target = acrtc->target;
--			return dc_target->streams[0];
--		}
-+	for (i = 0; i < table->stream_count; i++) {
-+		const struct dp_mst_stream_allocation *sa =
-+				&table->stream_allocations[i];
-+		if (sa->vcp_id == vcpi)
-+			return sa;
- 	}
- 	return NULL;
- }
- 
-+
- static void get_payload_table(
- 		struct drm_device *dev,
- 		struct amdgpu_connector *aconnector,
--		struct dp_mst_stream_allocation_table *table)
-+		const struct dc_stream *stream,
-+		const struct dp_mst_stream_allocation_table *cur_table,
-+		struct dp_mst_stream_allocation_table *proposed_table)
- {
- 	int i;
--	struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
--	struct amdgpu_connector *master_port = aconnector->mst_port;
-+	struct drm_dp_mst_topology_mgr *mst_mgr =
-+			&aconnector->mst_port->mst_mgr;
- 
- 	mutex_lock(&mst_mgr->payload_lock);
- 
-+	proposed_table->stream_count = 0;
-+
- 	/* number of active streams */
- 	for (i = 0; i < mst_mgr->max_payloads; i++) {
- 		if (mst_mgr->payloads[i].num_slots == 0)
--			break;
-+			break; /* end of vcp_id table */
-+
-+		ASSERT(mst_mgr->payloads[i].payload_state !=
-+				DP_PAYLOAD_DELETE_LOCAL);
- 
- 		if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
--				mst_mgr->payloads[i].payload_state == DP_PAYLOAD_REMOTE) {
--			table->stream_allocations[i].slot_count = mst_mgr->payloads[i].num_slots;
--			table->stream_allocations[i].stream =
--					get_stream_for_vcid(
--							dev,
--							master_port,
--							mst_mgr->payloads[i].vcpi);
-+			mst_mgr->payloads[i].payload_state ==
-+					DP_PAYLOAD_REMOTE) {
-+
-+			const struct dp_mst_stream_allocation *sa_src
-+				= find_stream_with_matching_vcpi(
-+					cur_table,
-+					mst_mgr->proposed_vcpis[i]->vcpi);
-+
-+			if (sa_src) {
-+				proposed_table->stream_allocations[
-+					proposed_table->stream_count] = *sa_src;
-+				proposed_table->stream_count++;
-+			} else {
-+				struct dp_mst_stream_allocation *sa =
-+					&proposed_table->stream_allocations[
-+						proposed_table->stream_count];
-+
-+				sa->slot_count =
-+						mst_mgr->payloads[i].num_slots;
-+				sa->stream = stream;
-+				sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
-+				proposed_table->stream_count++;
-+			}
- 		}
- 	}
- 
--	table->stream_count = i;
--
- 	mutex_unlock(&mst_mgr->payload_lock);
--
- }
- 
- /*
-@@ -236,7 +235,8 @@ static void get_payload_table(
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream,
--		struct dp_mst_stream_allocation_table *table,
-+		const struct dp_mst_stream_allocation_table *cur_table,
-+		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable)
- {
- 	struct amdgpu_device *adev = ctx->driver_context;
-@@ -312,7 +312,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	 * stream. AMD ASIC stream slot allocation should follow the same
- 	 * sequence. copy DRM MST allocation to dc */
- 
--	get_payload_table(dev, aconnector, table);
-+	get_payload_table(dev, aconnector, stream, cur_table, proposed_table);
- 
- 	if (ret)
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index ac6785a..794465e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1106,18 +1106,6 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
--	bool already_enabled = false;
--	int i;
--
--	for (i = 0; i < link->enabled_stream_count; i++) {
--		if (link->enabled_streams[i] == stream)
--			already_enabled = true;
--	}
--
--	if (!already_enabled && link->enabled_stream_count < MAX_SINKS_PER_LINK)
--		link->enabled_streams[link->enabled_stream_count++] = stream;
--	else if (link->enabled_stream_count >= MAX_SINKS_PER_LINK)
--		return DC_ERROR_UNEXPECTED;
- 
- 	/* sink signal type after MST branch is MST. Multiple MST sinks
- 	 * share one link. Link DP PHY is enable or training only once.
-@@ -1285,9 +1273,12 @@ void core_link_resume(struct core_link *link)
- 
- static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
- {
--	struct link_settings *link_settings = &stream->sink->link->cur_link_settings;
--	uint32_t link_rate_in_mbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
--	struct fixed31_32 mbps = dal_fixed31_32_from_int(link_rate_in_mbps * link_settings->lane_count);
-+	struct link_settings *link_settings =
-+			&stream->sink->link->cur_link_settings;
-+	uint32_t link_rate_in_mbps =
-+			link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
-+	struct fixed31_32 mbps = dal_fixed31_32_from_int(
-+			link_rate_in_mbps * link_settings->lane_count);
- 
- 	return dal_fixed31_32_div_int(mbps, 54);
- }
-@@ -1318,15 +1309,13 @@ static struct fixed31_32 get_pbn_from_timing(struct core_stream *stream)
- 
- 	/*
- 	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
--	 *
- 	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
- 	 * common multiplier to render an integer PBN for all link rate/lane
- 	 * counts combinations
--	 * 	 *
- 	 * calculate
--	 * 	peak_kbps *= (1006/1000)
--	 * 	peak_kbps *= (64/54)
--	 * 	peak_kbps *= 8    convert to bytes
-+	 * peak_kbps *= (1006/1000)
-+	 * peak_kbps *= (64/54)
-+	 * peak_kbps *= 8    convert to bytes
- 	 */
- 
- 	numerator = 64 * PEAK_FACTOR_X1000;
-@@ -1342,11 +1331,12 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	struct core_link *link = stream->sink->link;
- 	struct link_encoder *link_encoder = link->link_enc;
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
--	struct dp_mst_stream_allocation_table table = {0};
-+	struct dp_mst_stream_allocation_table proposed_table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp;
- 	struct dc *dc = stream->ctx->dc;
- 	struct fixed31_32 pbn;
- 	struct fixed31_32 pbn_per_slot;
-+	uint8_t i;
- 
- 	/* enable_link_dp_mst already check link->enabled_stream_count
- 	 * and stream is in link->stream[]. This is called during set mode,
-@@ -1357,22 +1347,53 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->public,
--		&table,
-+		&link->stream_alloc_table,
-+		&proposed_table,
- 		true);
- 
-+	dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_MST,
-+			LOG_MINOR_MST_PROGRAMMING,
-+			"%s  "
-+			"stream_count: %d: \n ",
-+			__func__,
-+			proposed_table.stream_count);
-+
-+	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
-+		dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_MST,
-+		LOG_MINOR_MST_PROGRAMMING,
-+		"stream[%d]: 0x%x      "
-+		"stream[%d].vcp_id: %d      "
-+		"stream[%d].slot_count: %d\n",
-+		i,
-+		proposed_table.stream_allocations[i].stream,
-+		i,
-+		proposed_table.stream_allocations[i].vcp_id,
-+		i,
-+		proposed_table.stream_allocations[i].slot_count);
-+	}
-+
-+	ASSERT(proposed_table.stream_count > 0);
-+	ASSERT(proposed_table.stream_count -
-+			link->stream_alloc_table.stream_count == 1);
-+
- 	/*
- 	 * temporary fix. Unplug of MST chain happened (two displays),
- 	 * table is empty on first reset mode, and cause 0 division in
- 	 * avg_time_slots_per_mtp calculation
- 	 */
- 
--	if (table.stream_count == 0)
-+	/* to be removed or debugged */
-+	if (proposed_table.stream_count == 0)
- 		return DC_OK;
- 
- 	/* program DP source TX for payload */
- 	dc->hwss.update_mst_stream_allocation_table(
- 		link_encoder,
--		&table);
-+		&proposed_table);
-+
-+	link->stream_alloc_table = proposed_table;
- 
- 	/* send down message */
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-@@ -1384,10 +1405,12 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 			&stream->public,
- 			true);
- 
-+	/* slot X.Y for only current stream */
- 	pbn_per_slot = get_pbn_per_slot(stream);
- 	pbn = get_pbn_from_timing(stream);
- 	avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
- 
-+
- 	dc->hwss.set_mst_bandwidth(
- 		stream_encoder,
- 		avg_time_slots_per_mtp);
-@@ -1401,10 +1424,10 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	struct core_link *link = stream->sink->link;
- 	struct link_encoder *link_encoder = link->link_enc;
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
--	struct dp_mst_stream_allocation_table table = {0};
-+	struct dp_mst_stream_allocation_table proposed_table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
--	uint8_t i;
- 	struct dc *dc = stream->ctx->dc;
-+	uint8_t i;
- 
- 	/* deallocate_mst_payload is called before disable link. When mode or
- 	 * disable/enable monitor, new stream is created which is not in link
-@@ -1412,16 +1435,6 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	 * should not done. For new mode set, map_resources will get engine
- 	 * for new stream, so stream_enc->id should be validated until here.
- 	 */
--	if (link->enabled_stream_count == 0)
--		return DC_OK;
--
--	for (i = 0; i < link->enabled_stream_count; i++) {
--		if (link->enabled_streams[i] == stream)
--			break;
--	}
--	/* stream is not in link stream list */
--	if (i == link->enabled_stream_count)
--		return DC_OK;
- 
- 	/* slot X.Y */
- 	dc->hwss.set_mst_bandwidth(
-@@ -1432,12 +1445,41 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->public,
--		&table,
-+		&link->stream_alloc_table,
-+		&proposed_table,
- 		false);
- 
-+	dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_MST,
-+			LOG_MINOR_MST_PROGRAMMING,
-+			"%s"
-+			"stream_count: %d: ",
-+			__func__,
-+			proposed_table.stream_count);
-+
-+	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
-+		dal_logger_write(link->ctx->logger,
-+		LOG_MAJOR_MST,
-+		LOG_MINOR_MST_PROGRAMMING,
-+		"stream[%d]: 0x%x"
-+		"stream[%d].vcp_id: %d"
-+		"stream[%d].slot_count: %d",
-+		i,
-+		proposed_table.stream_allocations[i].stream,
-+		i,
-+		proposed_table.stream_allocations[i].vcp_id,
-+		i,
-+		proposed_table.stream_allocations[i].slot_count);
-+	}
-+
-+	ASSERT(link->stream_alloc_table.stream_count -
-+			proposed_table.stream_count == 1);
-+
- 	dc->hwss.update_mst_stream_allocation_table(
- 		link_encoder,
--		&table);
-+		&proposed_table);
-+
-+	link->stream_alloc_table = proposed_table;
- 
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
-@@ -1482,3 +1524,32 @@ void core_link_disable_stream(
- 	disable_link(stream);
- 
- }
-+
-+void core_link_update_stream(
-+		struct core_link *link,
-+		struct core_stream *stream)
-+{
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		uint32_t i;
-+
-+		for (i = 0; i < link->stream_alloc_table.stream_count; i++) {
-+			const struct core_stream *s;
-+
-+			s = DC_STREAM_TO_CORE(
-+				link->stream_alloc_table.
-+				stream_allocations[i].stream);
-+
-+			if (stream->stream_enc == s->stream_enc) {
-+			link->stream_alloc_table.stream_allocations[i].stream =
-+					&stream->public;
-+
-+			dal_logger_write(link->ctx->logger,
-+					LOG_MAJOR_MST,
-+					LOG_MINOR_MST_PROGRAMMING,
-+					"%s  ",
-+					__func__);
-+			break;
-+			}
-+		}
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 1356238..27acac8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -84,17 +84,8 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 
- void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
- {
--	int i, j;
--
--	for (i = 0; i < link->enabled_stream_count; i++) {
--		if (link->enabled_streams[i] == stream) {
--			link->enabled_stream_count--;
--			for (j = i; j < link->enabled_stream_count; j++)
--				link->enabled_streams[j] = link->enabled_streams[j+1];
--		}
--	}
- 	/* MST disable link only when no stream use the link */
--	if (link->enabled_stream_count > 0)
-+	if (link->stream_alloc_table.stream_count > 0)
- 		return;
- 
- 	dp_disable_link_phy(link, stream->signal);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index d96e907..b4c338a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -44,7 +44,8 @@ enum dc_edid_status dc_helpers_parse_edid_caps(
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream,
--		struct dp_mst_stream_allocation_table *table,
-+		const struct dp_mst_stream_allocation_table *cur_table,
-+		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable);
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 1085137..685301b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -900,6 +900,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 
- 	if (timing_changed) {
- 		core_link_enable_stream(stream->sink->link, stream);
-+	} else {
-+		core_link_update_stream(stream->sink->link, stream);
- 	}
- 
- 	if (dc_is_dp_signal(stream->signal))
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 2b97d4d..5f918c1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -224,8 +224,7 @@ struct core_link {
- 	union dp_wa dp_wa;
- 
- 	/* MST record stream using this link */
--	const struct core_stream *enabled_streams[MAX_SINKS_PER_LINK];
--	uint8_t enabled_stream_count;
-+	struct dp_mst_stream_allocation_table stream_alloc_table;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-@@ -248,6 +247,10 @@ void core_link_disable_stream(
- 		struct core_link *link,
- 		struct core_stream *stream);
- 
-+void core_link_update_stream(
-+		struct core_link *link,
-+		struct core_stream *stream);
-+
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 429d969..573dd5c 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -393,6 +393,7 @@ struct mst_device_info {
- struct dp_mst_stream_allocation {
- 	/* stream engine id (DIG) */
- 	const struct dc_stream *stream;
-+	uint32_t vcp_id;
- 	/* number of slots required for the DP stream in
- 	 * transport packet */
- 	uint32_t slot_count;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0680-drm-amd-dal-Refactor-Stream-Encoder-for-DCE8-11.patch b/common/recipes-kernel/linux/files/0680-drm-amd-dal-Refactor-Stream-Encoder-for-DCE8-11.patch
deleted file mode 100644
index c39b410d..00000000
--- a/common/recipes-kernel/linux/files/0680-drm-amd-dal-Refactor-Stream-Encoder-for-DCE8-11.patch
+++ /dev/null
@@ -1,1341 +0,0 @@
-From 5e0ac3c9da50fb9f57d0f5992a8895eafece9e22 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Thu, 7 Jan 2016 20:14:28 -0500
-Subject: [PATCH 0680/1110] drm/amd/dal: Refactor Stream Encoder for DCE8/11
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  27 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  81 ++-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 805 +++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |  16 +-
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h    |  33 +
- 5 files changed, 465 insertions(+), 497 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 685301b..0d8b050 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -633,11 +633,11 @@ static void update_bios_scratch_critical_state(struct adapter_service *as,
- static void update_info_frame(struct core_stream *stream)
- {
- 	if (dc_is_hdmi_signal(stream->signal))
--		dce110_stream_encoder_update_hdmi_info_packets(
-+		stream->stream_enc->funcs->update_hdmi_info_packets(
- 			stream->stream_enc,
- 			&stream->encoder_info_frame);
- 	else if (dc_is_dp_signal(stream->signal))
--		dce110_stream_encoder_update_dp_info_packets(
-+		stream->stream_enc->funcs->update_dp_info_packets(
- 			stream->stream_enc,
- 			&stream->encoder_info_frame);
- }
-@@ -695,11 +695,11 @@ static void disable_stream(struct core_stream *stream)
- 	struct core_link *link = stream->sink->link;
- 
- 	if (dc_is_hdmi_signal(stream->signal))
--		dce110_stream_encoder_stop_hdmi_info_packets(
-+		stream->stream_enc->funcs->stop_hdmi_info_packets(
- 			stream->stream_enc);
- 
- 	if (dc_is_dp_signal(stream->signal))
--		dce110_stream_encoder_stop_dp_info_packets(
-+		stream->stream_enc->funcs->stop_dp_info_packets(
- 			stream->stream_enc);
- 
- 	if (stream->audio) {
-@@ -716,7 +716,7 @@ static void disable_stream(struct core_stream *stream)
- 
- 	/* blank at encoder level */
- 	if (dc_is_dp_signal(stream->signal))
--		dce110_stream_encoder_dp_blank(stream->stream_enc);
-+		stream->stream_enc->funcs->dp_blank(stream->stream_enc);
- 
- 	dce110_link_encoder_connect_dig_be_to_fe(
- 			link->link_enc,
-@@ -734,7 +734,7 @@ static void unblank_stream(struct core_stream *stream,
- 	params.crtc_timing.pixel_clock =
- 		stream->public.timing.pix_clk_khz;
- 	params.link_settings.link_rate = link_settings->link_rate;
--	dce110_stream_encoder_dp_unblank(
-+	stream->stream_enc->funcs->dp_unblank(
- 		stream->stream_enc, &params);
- }
- 
-@@ -855,18 +855,18 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		stream->signal);
- 
- 	if (dc_is_dp_signal(stream->signal))
--		dce110_stream_encoder_dp_set_stream_attribute(
-+		stream->stream_enc->funcs->dp_set_stream_attribute(
- 			stream->stream_enc,
- 			&stream->public.timing);
- 
- 	if (dc_is_hdmi_signal(stream->signal))
--		dce110_stream_encoder_hdmi_set_stream_attribute(
-+		stream->stream_enc->funcs->hdmi_set_stream_attribute(
- 		stream->stream_enc,
- 		&stream->public.timing,
- 		stream->audio != NULL);
- 
- 	if (dc_is_dvi_signal(stream->signal))
--		dce110_stream_encoder_dvi_set_stream_attribute(
-+		stream->stream_enc->funcs->dvi_set_stream_attribute(
- 		stream->stream_enc,
- 		&stream->public.timing,
- 		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-@@ -1728,6 +1728,13 @@ static void disable_vga(struct timing_generator *tg)
- 	tg->funcs->disable_vga(tg);
- }
- 
-+static void set_mst_bandwidth(struct stream_encoder *stream_enc,
-+	struct fixed31_32 avg_time_slots_per_mtp)
-+{
-+	stream_enc->funcs->set_mst_bandwidth(stream_enc,
-+		avg_time_slots_per_mtp);
-+}
-+
- static const struct hw_sequencer_funcs dce110_funcs = {
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
- 	.reset_hw_ctx = reset_hw_ctx,
-@@ -1767,7 +1774,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.enable_stream = enable_stream,
- 	.disable_stream = disable_stream,
- 	.update_mst_stream_allocation_table = dce110_link_encoder_update_mst_stream_allocation_table,
--	.set_mst_bandwidth = dce110_stream_encoder_set_mst_bandwidth
-+	.set_mst_bandwidth = set_mst_bandwidth
- };
- 
- bool dce110_hw_sequencer_construct(struct dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index d7eea0d..266b761 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -51,32 +51,36 @@ enum dce110_clk_src_array_id {
- };
- 
- static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
--		{
--			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
--			.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
--		},
--		{
--			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
--			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
--		},
--		{
--			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
--			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
--		},
--		{
--			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
--			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
--		},
--		{
--			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
--			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
--		},
--		{
--			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
--			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
--		}
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	}
-+};
-+
-+static const struct dce110_stream_enc_offsets dce110_str_enc_offsets[] = {
-+	{
-+		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	}
- };
- 
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -97,6 +101,26 @@ static struct timing_generator *dce110_timing_generator_create(
- 	return NULL;
- }
- 
-+static struct stream_encoder *dce110_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx,
-+	struct bios_parser *bp,
-+	const struct dce110_stream_enc_offsets *offsets)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, offsets))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, enc110);
-+	return NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -238,7 +262,8 @@ bool dce110_construct_resource_pool(
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
- 				i, dc->ctx,
- 				dal_adapter_service_get_bios_parser(
--					adapter_serv));
-+					adapter_serv),
-+				&dce110_str_enc_offsets[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
- 				dal_error("DC: failed to create stream_encoder!\n");
-@@ -252,7 +277,8 @@ bool dce110_construct_resource_pool(
- stream_enc_create_fail:
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dce110_stream_encoder_destroy(&pool->stream_enc[i]);
-+			dc_service_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- audio_create_fail:
-@@ -321,7 +347,8 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dce110_stream_encoder_destroy(&pool->stream_enc[i]);
-+			dc_service_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index a07758f..81996f7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -30,25 +30,10 @@
- #include "dce/dce_11_0_enum.h"
- 
- #define DIG_REG(reg)\
--	(reg + enc110->offsets.dig_offset)
-+	(reg + enc110->offsets.dig)
- 
- #define DP_REG(reg)\
--	(reg + enc110->offsets.dp_offset)
--
--static const struct dce110_stream_enc_offsets reg_offsets[] = {
--{
--	.dig_offset = (mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP0_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
--},
--{
--	.dig_offset = (mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
--},
--{
--	.dig_offset = (mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP2_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
--}
--};
-+	(reg + enc110->offsets.dig)
- 
- #define VBI_LINE_0 0
- #define DP_BLANK_MAX_RETRY 20
-@@ -63,106 +48,30 @@ enum {
- 	DP_MST_UPDATE_MAX_RETRY = 50
- };
- 
--static void update_avi_info_packet(
--	struct dce110_stream_encoder *enc110,
--	const struct encoder_info_packet *info_packet)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t regval;
--	uint32_t addr;
--	uint32_t control0val;
--	uint32_t control1val;
--
--	if (info_packet->valid) {
--		const uint32_t *content =
--			(const uint32_t *) &info_packet->sb[0];
--
--		addr = DIG_REG(mmAFMT_AVI_INFO0);
--		regval = content[0];
--		dal_write_reg(
--			ctx,
--			addr,
--			regval);
--		regval = content[1];
--
--		addr = DIG_REG(mmAFMT_AVI_INFO1);
--		dal_write_reg(
--			ctx,
--			addr,
--			regval);
--		regval = content[2];
--
--		addr = DIG_REG(mmAFMT_AVI_INFO2);
--		dal_write_reg(
--			ctx,
--			addr,
--			regval);
--		regval = content[3];
--
--		/* move version to AVI_INFO3 */
--		addr = DIG_REG(mmAFMT_AVI_INFO3);
--		set_reg_field_value(
--			regval,
--			info_packet->hb1,
--			AFMT_AVI_INFO3,
--			AFMT_AVI_INFO_VERSION);
--
--		dal_write_reg(
--			ctx,
--			addr,
--			regval);
--
--		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
--
--		control0val = dal_read_reg(ctx, addr);
--
--		set_reg_field_value(
--			control0val,
--			1,
--			HDMI_INFOFRAME_CONTROL0,
--			HDMI_AVI_INFO_SEND);
--
--		set_reg_field_value(
--			control0val,
--			1,
--			HDMI_INFOFRAME_CONTROL0,
--			HDMI_AVI_INFO_CONT);
--
--		dal_write_reg(ctx, addr, control0val);
--
--		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL1);
--
--		control1val = dal_read_reg(ctx, addr);
--
--		set_reg_field_value(
--			control1val,
--			VBI_LINE_0 + 2,
--			HDMI_INFOFRAME_CONTROL1,
--			HDMI_AVI_INFO_LINE);
--
--		dal_write_reg(ctx, addr, control1val);
--	} else {
--		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
--
--		regval = dal_read_reg(ctx, addr);
--
--		set_reg_field_value(
--			regval,
--			0,
--			HDMI_INFOFRAME_CONTROL0,
--			HDMI_AVI_INFO_SEND);
--
--		set_reg_field_value(
--			regval,
--			0,
--			HDMI_INFOFRAME_CONTROL0,
--			HDMI_AVI_INFO_CONT);
--
--		dal_write_reg(ctx, addr, regval);
--	}
--}
-+static struct stream_encoder_funcs dce110_str_enc_funcs = {
-+	.dp_set_stream_attribute =
-+		dce110_stream_encoder_dp_set_stream_attribute,
-+	.hdmi_set_stream_attribute =
-+		dce110_stream_encoder_hdmi_set_stream_attribute,
-+	.dvi_set_stream_attribute =
-+		dce110_stream_encoder_dvi_set_stream_attribute,
-+	.set_mst_bandwidth =
-+		dce110_stream_encoder_set_mst_bandwidth,
-+	.update_hdmi_info_packets =
-+		dce110_stream_encoder_update_hdmi_info_packets,
-+	.stop_hdmi_info_packets =
-+		dce110_stream_encoder_stop_hdmi_info_packets,
-+	.update_dp_info_packets =
-+		dce110_stream_encoder_update_dp_info_packets,
-+	.stop_dp_info_packets =
-+		dce110_stream_encoder_stop_dp_info_packets,
-+	.dp_blank =
-+		dce110_stream_encoder_dp_blank,
-+	.dp_unblank =
-+		dce110_stream_encoder_dp_unblank,
-+};
- 
--static void update_generic_info_packet(
-+static void dce110_update_generic_info_packet(
- 	struct dce110_stream_encoder *enc110,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
-@@ -266,7 +175,7 @@ static void update_generic_info_packet(
- 	}
- }
- 
--static void update_hdmi_info_packet(
-+static void dce110_update_hdmi_info_packet(
- 	struct dce110_stream_encoder *enc110,
- 	uint32_t packet_index,
- 	const struct encoder_info_packet *info_packet)
-@@ -277,7 +186,7 @@ static void update_hdmi_info_packet(
- 	uint32_t regval;
- 
- 	if (info_packet->valid) {
--		update_generic_info_packet(
-+		dce110_update_generic_info_packet(
- 			enc110,
- 			packet_index,
- 			info_packet);
-@@ -370,215 +279,39 @@ static void update_hdmi_info_packet(
- 	dal_write_reg(ctx, addr, regval);
- }
- 
--static void update_dp_info_packet(
--	struct dce110_stream_encoder *enc110,
--	uint32_t packet_index,
--	const struct encoder_info_packet *info_packet)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
--
--	uint32_t value;
--
--	if (info_packet->valid)
--		update_generic_info_packet(
--			enc110,
--			packet_index,
--			info_packet);
--
--	/* enable/disable transmission of packet(s).
--	 * If enabled, packet transmission begins on the next frame */
--
--	value = dal_read_reg(ctx, addr);
--
--	switch (packet_index) {
--	case 0:
--		set_reg_field_value(
--			value,
--			info_packet->valid,
--			DP_SEC_CNTL,
--			DP_SEC_GSP0_ENABLE);
--		break;
--	case 1:
--		set_reg_field_value(
--			value,
--			info_packet->valid,
--			DP_SEC_CNTL,
--			DP_SEC_GSP1_ENABLE);
--		break;
--	case 2:
--		set_reg_field_value(
--			value,
--			info_packet->valid,
--			DP_SEC_CNTL,
--			DP_SEC_GSP2_ENABLE);
--		break;
--	case 3:
--		set_reg_field_value(
--			value,
--			info_packet->valid,
--			DP_SEC_CNTL,
--			DP_SEC_GSP3_ENABLE);
--		break;
--	default:
--		/* invalid HW packet index */
--		ASSERT_CRITICAL(false);
--		return;
--	}
--
--	/* This bit is the master enable bit.
--	 * When enabling secondary stream engine,
--	 * this master bit must also be set.
--	 * This register shared with audio info frame.
--	 * Therefore we need to enable master bit
--	 * if at least on of the fields is not 0 */
--
--	if (value)
--		set_reg_field_value(
--			value,
--			1,
--			DP_SEC_CNTL,
--			DP_SEC_STREAM_ENABLE);
--
--	dal_write_reg(ctx, addr, value);
--}
--
--static void dp_steer_fifo_reset(
--	struct dce110_stream_encoder *enc110,
--	bool reset)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	const uint32_t addr = DP_REG(mmDP_STEER_FIFO);
--
--	uint32_t value = dal_read_reg(ctx, addr);
--
--	set_reg_field_value(value, reset, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
--
--	dal_write_reg(ctx, addr, value);
--}
--
--static void unblank_dp_output(
--	struct dce110_stream_encoder *enc110)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr;
--	uint32_t value;
--
--	/* set DIG_START to 0x1 to resync FIFO */
--	addr = DIG_REG(mmDIG_FE_CNTL);
--	value = dal_read_reg(ctx, addr);
--	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
--	dal_write_reg(ctx, addr, value);
--
--	/* switch DP encoder to CRTC data */
--	dp_steer_fifo_reset(enc110, false);
--
--	/* wait 100us for DIG/DP logic to prime
--	 * (i.e. a few video lines) */
--	dc_service_delay_in_microseconds(ctx, 100);
--
--	/* the hardware would start sending video at the start of the next DP
--	 * frame (i.e. rising edge of the vblank).
--	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
--	 * register has no effect on enable transition! HW always guarantees
--	 * VID_STREAM enable at start of next frame, and this is not
--	 * programmable */
--	addr = DP_REG(mmDP_VID_STREAM_CNTL);
--	value = dal_read_reg(ctx, addr);
--	set_reg_field_value(
--		value,
--		true,
--		DP_VID_STREAM_CNTL,
--		DP_VID_STREAM_ENABLE);
--	dal_write_reg(ctx, addr, value);
--
--}
--
--static void setup_vid_stream(
--	struct dce110_stream_encoder *enc110,
--	uint32_t m_vid,
--	uint32_t n_vid)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr;
--	uint32_t value;
--
--	/* enable auto measurement */
--	addr = DP_REG(mmDP_VID_TIMING);
--	value = dal_read_reg(ctx, addr);
--	set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
--	dal_write_reg(ctx, addr, value);
--
--	/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
--	 * therefore program initial value for Mvid and Nvid */
--	addr = DP_REG(mmDP_VID_N);
--	value = dal_read_reg(ctx, addr);
--	set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
--	dal_write_reg(ctx, addr, value);
--
--	addr = DP_REG(mmDP_VID_M);
--	value = dal_read_reg(ctx, addr);
--	set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
--	dal_write_reg(ctx, addr, value);
--
--	addr = DP_REG(mmDP_VID_TIMING);
--	value = dal_read_reg(ctx, addr);
--	set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
--	dal_write_reg(ctx, addr, value);
--}
--
--static void set_tmds_stream_attributes(
-+bool dce110_stream_encoder_construct(
- 	struct dce110_stream_encoder *enc110,
--	const struct dc_crtc_timing *timing,
--	bool is_dvi
--	)
-+	struct dc_context *ctx,
-+	struct bios_parser *bp,
-+	enum engine_id eng_id,
-+	const struct dce110_stream_enc_offsets *offsets)
- {
--	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DIG_REG(mmDIG_FE_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	if (!enc110)
-+		return false;
-+	if (!bp)
-+		return false;
- 
--	switch (timing->pixel_encoding) {
--	case PIXEL_ENCODING_YCBCR422:
--		set_reg_field_value(value, 1, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
--		break;
--	default:
--		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
--		break;
--	}
-+	enc110->base.funcs = &dce110_str_enc_funcs;
-+	enc110->base.ctx = ctx;
-+	enc110->base.id = eng_id;
-+	enc110->base.bp = bp;
-+	enc110->offsets = *offsets;
- 
--	switch (timing->display_color_depth) {
--	case COLOR_DEPTH_101010:
--		if (is_dvi &&
--			timing->pixel_encoding == PIXEL_ENCODING_RGB)
--			set_reg_field_value(
--				value,
--				2,
--				DIG_FE_CNTL,
--				TMDS_COLOR_FORMAT);
--		else
--			set_reg_field_value(
--				value,
--				0,
--				DIG_FE_CNTL,
--				TMDS_COLOR_FORMAT);
--		break;
--	default:
--		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
--		break;
--	}
--	dal_write_reg(ctx, addr, value);
-+	return true;
- }
- 
--static void set_dp_stream_attributes(
--	struct dce110_stream_encoder *enc110,
--	const struct dc_crtc_timing *timing)
-+/* setup stream encoder in dp mode */
-+void dce110_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing)
- {
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	const uint32_t addr = DP_REG(mmDP_PIXEL_FORMAT);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	/* set pixel encoding */
--	switch (timing->pixel_encoding) {
-+	switch (crtc_timing->pixel_encoding) {
- 	case PIXEL_ENCODING_YCBCR422:
- 		set_reg_field_value(
- 			value,
-@@ -593,8 +326,8 @@ static void set_dp_stream_attributes(
- 			DP_PIXEL_FORMAT,
- 			DP_PIXEL_ENCODING);
- 
--		if (timing->flags.Y_ONLY)
--			if (timing->display_color_depth != COLOR_DEPTH_666)
-+		if (crtc_timing->flags.Y_ONLY)
-+			if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
- 				/* HW testing only, no use case yet.
- 				 * Color depth of Y-only could be
- 				 * 8, 10, 12, 16 bits */
-@@ -619,7 +352,7 @@ static void set_dp_stream_attributes(
- 
- 	/* set color depth */
- 
--	switch (timing->display_color_depth) {
-+	switch (crtc_timing->display_color_depth) {
- 	case COLOR_DEPTH_888:
- 		set_reg_field_value(
- 			value,
-@@ -642,30 +375,61 @@ static void set_dp_stream_attributes(
- 			DP_COMPONENT_DEPTH);
- 		break;
- 	default:
--		set_reg_field_value(
--			value,
--			DP_COMPONENT_DEPTH_6BPC,
--			DP_PIXEL_FORMAT,
--			DP_COMPONENT_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_6BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	}
-+
-+	/* set dynamic range and YCbCr range */
-+	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_DYN_RANGE);
-+	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_YCBCR_RANGE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+/* setup stream encoder in hdmi mode */
-+void dce110_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool enable_audio)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t output_pixel_clock = crtc_timing->pix_clk_khz;
-+	uint32_t value;
-+	uint32_t addr;
-+	struct bp_encoder_control cntl = {0};
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc110->base.id;
-+	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+	cntl.enable_dp_audio = enable_audio;
-+	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.color_depth = crtc_timing->display_color_depth;
-+
-+	if (dal_bios_parser_encoder_control(
-+			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+		return;
-+
-+	addr = DIG_REG(mmDIG_FE_CNTL);
-+	value = dal_read_reg(ctx, addr);
-+
-+	switch (crtc_timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(value, 1, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
- 		break;
- 	}
--
--	/* set dynamic range and YCbCr range */
--	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_DYN_RANGE);
--	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_YCBCR_RANGE);
--
-+	set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
- 	dal_write_reg(ctx, addr, value);
--}
--
--static void setup_hdmi(
--	struct dce110_stream_encoder *enc110,
--	const struct dc_crtc_timing *timing)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t output_pixel_clock = timing->pix_clk_khz;
--	uint32_t value;
--	uint32_t addr;
- 
-+	/* setup HDMI engine */
- 	addr = DIG_REG(mmHDMI_CONTROL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_PACKET_GEN_VERSION);
-@@ -674,7 +438,7 @@ static void setup_hdmi(
- 	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN);
- 	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE);
- 
--	switch (timing->display_color_depth) {
-+	switch (crtc_timing->display_color_depth) {
- 	case COLOR_DEPTH_888:
- 		set_reg_field_value(
- 			value,
-@@ -693,7 +457,7 @@ static void setup_hdmi(
- 			1,
- 			HDMI_CONTROL,
- 			HDMI_DEEP_COLOR_ENABLE);
--		output_pixel_clock = (timing->pix_clk_khz * 30) / 24;
-+		output_pixel_clock = (crtc_timing->pix_clk_khz * 30) / 24;
- 		break;
- 	case COLOR_DEPTH_121212:
- 		set_reg_field_value(
-@@ -706,7 +470,7 @@ static void setup_hdmi(
- 			1,
- 			HDMI_CONTROL,
- 			HDMI_DEEP_COLOR_ENABLE);
--		output_pixel_clock = (timing->pix_clk_khz * 36) / 24;
-+		output_pixel_clock = (crtc_timing->pix_clk_khz * 36) / 24;
- 		break;
- 	case COLOR_DEPTH_161616:
- 		set_reg_field_value(
-@@ -719,7 +483,7 @@ static void setup_hdmi(
- 			1,
- 			HDMI_CONTROL,
- 			HDMI_DEEP_COLOR_ENABLE);
--		output_pixel_clock = (timing->pix_clk_khz * 48) / 24;
-+		output_pixel_clock = (crtc_timing->pix_clk_khz * 48) / 24;
- 		break;
- 	default:
- 		break;
-@@ -740,7 +504,7 @@ static void setup_hdmi(
- 			1,
- 			HDMI_CONTROL,
- 			HDMI_CLOCK_CHANNEL_RATE);
--	} else if (timing->flags.LTE_340MCSC_SCRAMBLE) {
-+	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
- 
- 		/* TODO: New feature for DCE11, still need to implement */
- 
-@@ -803,87 +567,6 @@ static void setup_hdmi(
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, HDMI_GC, HDMI_GC_AVMUTE);
- 	dal_write_reg(ctx, addr, value);
--
--}
--
--static bool construct(
--	struct dce110_stream_encoder *enc110,
--	struct dc_context *ctx,
--	struct bios_parser *bp,
--	enum engine_id eng_id)
--{
--	if (eng_id > ARRAY_SIZE(reg_offsets))
--		return false;
--
--	enc110->base.ctx = ctx;
--	enc110->base.id = eng_id;
--	enc110->base.bp = bp;
--	enc110->offsets = reg_offsets[eng_id];
--
--	return true;
--}
--
--struct stream_encoder *dce110_stream_encoder_create(
--	enum engine_id eng_id,
--	struct dc_context *ctx,
--	struct bios_parser *bp)
--{
--	struct dce110_stream_encoder *enc110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
--
--	if (!enc110)
--		return NULL;
--
--	if (construct(enc110, ctx, bp, eng_id))
--		return &enc110->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, enc110);
--	return NULL;
--}
--
--void dce110_stream_encoder_destroy(struct stream_encoder **enc)
--{
--	dc_service_free((*enc)->ctx, TO_DCE110_STREAM_ENC(*enc));
--	*enc = NULL;
--}
--
--/* setup stream encoder in dp mode */
--void dce110_stream_encoder_dp_set_stream_attribute(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing)
--{
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
--
--	set_dp_stream_attributes(enc110, crtc_timing);
--}
--
--/* setup stream encoder in hdmi mode */
--void dce110_stream_encoder_hdmi_set_stream_attribute(
--	struct stream_encoder *enc,
--	struct dc_crtc_timing *crtc_timing,
--	bool enable_audio)
--{
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
--	struct bp_encoder_control cntl = {0};
--
--	cntl.action = ENCODER_CONTROL_SETUP;
--	cntl.engine_id = enc110->base.id;
--	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
--	cntl.enable_dp_audio = enable_audio;
--	cntl.pixel_clock = crtc_timing->pix_clk_khz;
--	cntl.lanes_number = LANE_COUNT_FOUR;
--	cntl.color_depth = crtc_timing->display_color_depth;
--
--	if (dal_bios_parser_encoder_control(
--			enc->bp, &cntl) != BP_RESULT_OK)
--		return;
--
--
--	set_tmds_stream_attributes(enc110, crtc_timing, false);
--
--	/* setup HDMI engine */
--	setup_hdmi(enc110, crtc_timing);
- }
- 
- /* setup stream encoder in dvi mode */
-@@ -892,7 +575,10 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 	struct dc_crtc_timing *crtc_timing,
- 	bool is_dual_link)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DIG_REG(mmDIG_FE_CNTL);
-+	uint32_t value = dal_read_reg(ctx, addr);
- 	struct bp_encoder_control cntl = {0};
- 
- 	cntl.action = ENCODER_CONTROL_SETUP;
-@@ -910,14 +596,42 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 			enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
--	set_tmds_stream_attributes(enc110, crtc_timing, true);
-+	switch (crtc_timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(value, 1, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_101010:
-+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
-+			set_reg_field_value(
-+				value,
-+				2,
-+				DIG_FE_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DIG_FE_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
-+		break;
-+	}
-+	dal_write_reg(ctx, addr, value);
- }
- 
- void dce110_stream_encoder_set_mst_bandwidth(
- 	struct stream_encoder *enc,
- 	struct fixed31_32 avg_time_slots_per_mtp)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
- 	uint32_t field;
-@@ -980,20 +694,110 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 	struct stream_encoder *enc,
- 	const struct encoder_info_frame *info_frame)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
--
--	update_avi_info_packet(
--		enc110,
--		&info_frame->avi);
--	update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
--	update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
--	update_hdmi_info_packet(enc110, 2, &info_frame->spd);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t regval;
-+	uint32_t addr;
-+	uint32_t control0val;
-+	uint32_t control1val;
-+
-+	if (info_frame->avi.valid) {
-+		const uint32_t *content =
-+			(const uint32_t *) &info_frame->avi.sb[0];
-+
-+		addr = DIG_REG(mmAFMT_AVI_INFO0);
-+		regval = content[0];
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+		regval = content[1];
-+
-+		addr = DIG_REG(mmAFMT_AVI_INFO1);
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+		regval = content[2];
-+
-+		addr = DIG_REG(mmAFMT_AVI_INFO2);
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+		regval = content[3];
-+
-+		/* move version to AVI_INFO3 */
-+		addr = DIG_REG(mmAFMT_AVI_INFO3);
-+		set_reg_field_value(
-+			regval,
-+			info_frame->avi.hb1,
-+			AFMT_AVI_INFO3,
-+			AFMT_AVI_INFO_VERSION);
-+
-+		dal_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+
-+		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+
-+		control0val = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			control0val,
-+			1,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_SEND);
-+
-+		set_reg_field_value(
-+			control0val,
-+			1,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_CONT);
-+
-+		dal_write_reg(ctx, addr, control0val);
-+
-+		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL1);
-+
-+		control1val = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			control1val,
-+			VBI_LINE_0 + 2,
-+			HDMI_INFOFRAME_CONTROL1,
-+			HDMI_AVI_INFO_LINE);
-+
-+		dal_write_reg(ctx, addr, control1val);
-+	} else {
-+		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+
-+		regval = dal_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			0,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_SEND);
-+
-+		set_reg_field_value(
-+			regval,
-+			0,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_CONT);
-+
-+		dal_write_reg(ctx, addr, regval);
-+	}
-+
-+	dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
-+	dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
-+	dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
- }
- 
- void dce110_stream_encoder_stop_hdmi_info_packets(
- 	struct stream_encoder *enc)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
-@@ -1096,16 +900,50 @@ void dce110_stream_encoder_update_dp_info_packets(
- 	struct stream_encoder *enc,
- 	const struct encoder_info_frame *info_frame)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
-+	uint32_t value;
-+
-+	if (info_frame->vsc.valid)
-+		dce110_update_generic_info_packet(
-+			enc110,
-+			0,
-+			&info_frame->vsc);
-+
-+	/* enable/disable transmission of packet(s).
-+	*  If enabled, packet transmission begins on the next frame
-+	*/
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		info_frame->vsc.valid,
-+		DP_SEC_CNTL,
-+		DP_SEC_GSP0_ENABLE);
-+	/* This bit is the master enable bit.
-+	* When enabling secondary stream engine,
-+	* this master bit must also be set.
-+	* This register shared with audio info frame.
-+	* Therefore we need to enable master bit
-+	* if at least on of the fields is not 0
-+	*/
-+	if (value)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
- 
--	update_dp_info_packet(enc110, 0, &info_frame->vsc);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- void dce110_stream_encoder_stop_dp_info_packets(
- 	struct stream_encoder *enc)
- {
- 	/* stop generic packets on DP */
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
-@@ -1135,7 +973,7 @@ void dce110_stream_encoder_stop_dp_info_packets(
- void dce110_stream_encoder_dp_blank(
- 	struct stream_encoder *enc)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = DP_REG(mmDP_VID_STREAM_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
-@@ -1157,8 +995,9 @@ void dce110_stream_encoder_dp_blank(
- 		DP_VID_STREAM_CNTL,
- 		DP_VID_STREAM_DIS_DEFER);
- 	/* Larger delay to wait until VBLANK - use max retry of
--	 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
--	 * a little more because we may not trust delay accuracy. */
-+	* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
-+	* a little more because we may not trust delay accuracy.
-+	*/
- 	max_retries = DP_BLANK_MAX_RETRY * 150;
- 
- 	/* disable DP stream */
-@@ -1166,8 +1005,9 @@ void dce110_stream_encoder_dp_blank(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* the encoder stops sending the video stream
--	 * at the start of the vertical blanking.
--	 * Poll for DP_VID_STREAM_STATUS == 0 */
-+	* at the start of the vertical blanking.
-+	* Poll for DP_VID_STREAM_STATUS == 0
-+	*/
- 
- 	do {
- 		value = dal_read_reg(ctx, addr);
-@@ -1186,10 +1026,14 @@ void dce110_stream_encoder_dp_blank(
- 	ASSERT(retries <= max_retries);
- 
- 	/* Tell the DP encoder to ignore timing from CRTC, must be done after
--	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
--	 * complete, stream status will be stuck in video stream enabled state,
--	 * i.e. DP_VID_STREAM_STATUS stuck at 1. */
--	dp_steer_fifo_reset(enc110, true);
-+	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
-+	* complete, stream status will be stuck in video stream enabled state,
-+	* i.e. DP_VID_STREAM_STATUS stuck at 1.
-+	*/
-+	addr = DP_REG(mmDP_STEER_FIFO);
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(value, true, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
-+	dal_write_reg(ctx, addr, value);
- }
- 
- /* output video stream to link encoder */
-@@ -1197,14 +1041,18 @@ void dce110_stream_encoder_dp_unblank(
- 	struct stream_encoder *enc,
- 	const struct encoder_unblank_param *param)
- {
--	struct dce110_stream_encoder *enc110 = TO_DCE110_STREAM_ENC(enc);
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t value;
- 
- 	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
- 		uint32_t n_vid = 0x8000;
- 		uint32_t m_vid;
- 
- 		/* M / N = Fstream / Flink
--		 * m_vid / n_vid = pixel rate / link rate */
-+		* m_vid / n_vid = pixel rate / link rate
-+		*/
- 
- 		uint64_t m_vid_l = n_vid;
- 
-@@ -1215,9 +1063,62 @@ void dce110_stream_encoder_dp_unblank(
- 
- 		m_vid = (uint32_t) m_vid_l;
- 
--		setup_vid_stream(enc110, m_vid, n_vid);
-+		/* enable auto measurement */
-+		addr = DP_REG(mmDP_VID_TIMING);
-+		value = dal_read_reg(ctx, addr);
-+		set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
-+		dal_write_reg(ctx, addr, value);
-+
-+		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
-+		* therefore program initial value for Mvid and Nvid
-+		*/
-+		addr = DP_REG(mmDP_VID_N);
-+		value = dal_read_reg(ctx, addr);
-+		set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
-+		dal_write_reg(ctx, addr, value);
-+
-+		addr = DP_REG(mmDP_VID_M);
-+		value = dal_read_reg(ctx, addr);
-+		set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
-+		dal_write_reg(ctx, addr, value);
-+
-+		addr = DP_REG(mmDP_VID_TIMING);
-+		value = dal_read_reg(ctx, addr);
-+		set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
-+		dal_write_reg(ctx, addr, value);
- 	}
- 
--	unblank_dp_output(enc110);
-+	/* set DIG_START to 0x1 to resync FIFO */
-+	addr = DIG_REG(mmDIG_FE_CNTL);
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* switch DP encoder to CRTC data */
-+	addr = DP_REG(mmDP_STEER_FIFO);
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(value, 0, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
-+	dal_write_reg(ctx, addr, value);
-+
-+	/* wait 100us for DIG/DP logic to prime
-+	* (i.e. a few video lines)
-+	*/
-+	dc_service_delay_in_microseconds(ctx, 100);
-+
-+	/* the hardware would start sending video at the start of the next DP
-+	* frame (i.e. rising edge of the vblank).
-+	* NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
-+	* register has no effect on enable transition! HW always guarantees
-+	* VID_STREAM enable at start of next frame, and this is not
-+	* programmable
-+	*/
-+	addr = DP_REG(mmDP_VID_STREAM_CNTL);
-+	value = dal_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		true,
-+		DP_VID_STREAM_CNTL,
-+		DP_VID_STREAM_ENABLE);
-+	dal_write_reg(ctx, addr, value);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 8d859a9..200308c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -28,12 +28,12 @@
- 
- #include "inc/stream_encoder.h"
- 
--#define TO_DCE110_STREAM_ENC(stream_encoder)\
-+#define DCE110STRENC_FROM_STRENC(stream_encoder)\
- 	container_of(stream_encoder, struct dce110_stream_encoder, base)
- 
- struct dce110_stream_enc_offsets {
--	uint32_t dig_offset;
--	uint32_t dp_offset;
-+	uint32_t dig;
-+	uint32_t dp;
- };
- 
- struct dce110_stream_encoder {
-@@ -41,12 +41,12 @@ struct dce110_stream_encoder {
- 	struct dce110_stream_enc_offsets offsets;
- };
- 
--struct stream_encoder *dce110_stream_encoder_create(
--	enum engine_id eng_id,
-+bool dce110_stream_encoder_construct(
-+	struct dce110_stream_encoder *enc110,
- 	struct dc_context *ctx,
--	struct bios_parser *bp);
--
--void dce110_stream_encoder_destroy(struct stream_encoder **enc);
-+	struct bios_parser *bp,
-+	enum engine_id eng_id,
-+	const struct dce110_stream_enc_offsets *offsets);
- 
- /***** HW programming ***********/
- /* setup stream encoder in dp mode */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-index d2da14a..25028b7 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-@@ -10,9 +10,42 @@
- #include "include/bios_parser_interface.h"
- 
- struct stream_encoder {
-+	struct stream_encoder_funcs *funcs;
- 	struct dc_context *ctx;
- 	struct bios_parser *bp;
- 	enum engine_id id;
- };
- 
-+struct stream_encoder_funcs {
-+	void (*dp_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing);
-+	void (*hdmi_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		bool enable_audio);
-+	void (*dvi_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		bool is_dual_link);
-+	void (*set_mst_bandwidth)(
-+		struct stream_encoder *enc,
-+		struct fixed31_32 avg_time_slots_per_mtp);
-+	void (*update_hdmi_info_packets)(
-+		struct stream_encoder *enc,
-+		const struct encoder_info_frame *info_frame);
-+	void (*stop_hdmi_info_packets)(
-+		struct stream_encoder *enc);
-+	void (*update_dp_info_packets)(
-+		struct stream_encoder *enc,
-+		const struct encoder_info_frame *info_frame);
-+	void (*stop_dp_info_packets)(
-+		struct stream_encoder *enc);
-+	void (*dp_blank)(
-+		struct stream_encoder *enc);
-+	void (*dp_unblank)(
-+		struct stream_encoder *enc,
-+		const struct encoder_unblank_param *param);
-+};
-+
- #endif /* STREAM_ENCODER_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0681-drm-amd-dal-virtual-link-and-sink-support.patch b/common/recipes-kernel/linux/files/0681-drm-amd-dal-virtual-link-and-sink-support.patch
deleted file mode 100644
index 41509b3c..00000000
--- a/common/recipes-kernel/linux/files/0681-drm-amd-dal-virtual-link-and-sink-support.patch
+++ /dev/null
@@ -1,667 +0,0 @@
-From d2375cf918a6a0fe2d6dce2b480e8e094ab2d074 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 7 Jan 2016 18:09:48 -0500
-Subject: [PATCH 0681/1110] drm/amd/dal: virtual link and sink support
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  4 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  2 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 44 +++++++++-------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 16 +++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 10 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  5 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_sink.c          | 12 ++---
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  4 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  6 ++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 58 +++++++++++-----------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 14 ++++--
- .../drm/amd/dal/dc/dce_base/dce_base_resource.c    | 26 ++++++----
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  7 +--
- drivers/gpu/drm/amd/dal/include/dal_types.h        |  1 +
- drivers/gpu/drm/amd/dal/include/signal_types.h     |  3 +-
- 17 files changed, 124 insertions(+), 92 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 80bd0c6..61e12ad 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -119,7 +119,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 		uint16_t len)
- {
- 	struct dc_sink *dc_sink;
--	struct sink_init_data init_params = {
-+	struct dc_sink_init_data init_params = {
- 			.link = dc_link,
- 			.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST};
- 	enum dc_edid_status edid_status;
-@@ -139,7 +139,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 	 * dc_link->connector_signal;
- 	 */
- 
--	dc_sink = sink_create(&init_params);
-+	dc_sink = dc_sink_create(&init_params);
- 
- 	if (!dc_sink)
- 		return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 00a0139..7df2d28 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1605,6 +1605,8 @@ static int to_drm_connector_type(enum signal_type st)
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 		return DRM_MODE_CONNECTOR_DVID;
-+	case SIGNAL_TYPE_VIRTUAL:
-+		return DRM_MODE_CONNECTOR_VIRTUAL;
- 
- 	default:
- 		return DRM_MODE_CONNECTOR_Unknown;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 96ec35f..397b664 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -92,14 +92,6 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 	dal_output_to_console("%s: connectors_num:%d\n", __func__,
- 			connectors_num);
- 
--	dc->links = dc_service_alloc(
--		init_params->ctx, connectors_num * sizeof(struct core_link *));
--
--	if (NULL == dc->links) {
--		dal_error("DC: failed to allocate 'links' storage!\n");
--		goto allocate_dc_links_storage_fail;
--	}
--
- 	for (i = 0; i < connectors_num; i++) {
- 		struct link_init_data link_init_params = {0};
- 		struct core_link *link;
-@@ -121,14 +113,28 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 		}
- 	}
- 
--	if (!dc->link_count) {
--		dal_error("DC: no 'links' were created!\n");
--		goto allocate_dc_links_storage_fail;
-+	for (i = 0; i < init_params->num_virtual_links; i++) {
-+		struct core_link *link =
-+			dc_service_alloc(dc->ctx, sizeof(*link));
-+
-+		if (link == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			goto failed_alloc;
-+		}
-+
-+		link->adapter_srv = init_params->adapter_srv;
-+		link->ctx = init_params->ctx;
-+		link->dc = dc;
-+		link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
-+
-+		link->public.link_index = dc->link_count;
-+		dc->links[dc->link_count] = link;
-+		dc->link_count++;
- 	}
- 
- 	return true;
- 
--allocate_dc_links_storage_fail:
-+failed_alloc:
- 	return false;
- }
- 
-@@ -165,7 +171,8 @@ static void init_hw(struct dc *dc)
- 		 * required signal (which may be different from the
- 		 * default signal on connector). */
- 		struct core_link *link = dc->links[i];
--		dc->hwss.encoder_hw_init(link->link_enc);
-+		if (link->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
-+			dc->hwss.encoder_hw_init(link->link_enc);
- 	}
- 
- 	for(i = 0; i < dc->res_pool.controller_count; i++) {
-@@ -291,6 +298,7 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 	}
- 	dc_init_data.ctx->driver_context = init_params->driver;
- 	dc_init_data.ctx->cgs_device = init_params->cgs_device;
-+	dc_init_data.num_virtual_links = init_params->num_virtual_links;
- 	dc_init_data.ctx->dc = dc;
- 
- 	/* Create logger */
-@@ -359,7 +367,6 @@ ctx_fail:
- static void destruct(struct dc *dc)
- {
- 	destroy_links(dc);
--	dc_service_free(dc->ctx, dc->links);
- 	dc->hwss.destruct_resource_pool(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
- 	dc_service_free(dc->ctx, dc->ctx);
-@@ -623,9 +630,9 @@ const struct audio **dc_get_audios(struct dc *dc)
- 
- void dc_get_caps(const struct dc *dc, struct dc_caps *caps)
- {
--    caps->max_targets = dc->res_pool.controller_count;
--    caps->max_links = dc->link_count;
--    caps->max_audios = dc->res_pool.audio_count;
-+	caps->max_targets = dc->res_pool.controller_count;
-+	caps->max_links = dc->link_count;
-+	caps->max_audios = dc->res_pool.audio_count;
- }
- 
- void dc_flip_surface_addrs(struct dc* dc,
-@@ -843,6 +850,9 @@ bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
- 
- 	dc_link->sink[link->sink_count] = sink;
- 	dc_link->sink_count++;
-+	if (sink->sink_signal == SIGNAL_TYPE_VIRTUAL
-+		&& link->connector_signal == SIGNAL_TYPE_VIRTUAL)
-+		dc_link->type = dc_connection_single;
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 794465e..2ef0451 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -553,7 +553,7 @@ static void dc_link_detect_dp(
- void dc_link_detect(const struct dc_link *dc_link)
- {
- 	struct core_link *link = DC_LINK_TO_LINK(dc_link);
--	struct sink_init_data sink_init_data = { 0 };
-+	struct dc_sink_init_data sink_init_data = { 0 };
- 	struct display_sink_capability sink_caps = { 0 };
- 	uint8_t i;
- 	bool converter_disable_audio = false;
-@@ -566,6 +566,9 @@ void dc_link_detect(const struct dc_link *dc_link)
- 	struct core_sink *sink = NULL;
- 	enum dc_connection_type new_connection_type = dc_connection_none;
- 
-+	if (link->public.connector_signal == SIGNAL_TYPE_VIRTUAL)
-+		return;
-+
- 	if (false == detect_sink(link, &new_connection_type)) {
- 		BREAK_TO_DEBUGGER();
- 		return;
-@@ -647,7 +650,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		sink_init_data.converter_disable_audio =
- 			converter_disable_audio;
- 
--		dc_sink = sink_create(&sink_init_data);
-+		dc_sink = dc_sink_create(&sink_init_data);
- 		if (!dc_sink) {
- 			DC_ERROR("Failed to create sink!\n");
- 			return;
-@@ -835,7 +838,6 @@ static bool construct(
- 
- 	link->dc = init_params->dc;
- 	link->adapter_srv = as;
--	link->connector_index = init_params->connector_index;
- 	link->ctx = dc_ctx;
- 	link->public.link_index = init_params->link_index;
- 
-@@ -994,7 +996,6 @@ struct core_link *link_create(const struct link_init_data *init_params)
- {
- 	struct core_link *link =
- 			dc_service_alloc(init_params->ctx, sizeof(*link));
--	link->ctx = init_params->ctx;
- 
- 	if (NULL == link)
- 		goto alloc_fail;
-@@ -1063,9 +1064,9 @@ static void dpcd_configure_panel_mode(
- 	}
- 	dal_logger_write(link->ctx->logger, LOG_MAJOR_DETECTION,
- 			LOG_MINOR_DETECTION_DP_CAPS,
--			"Connector: %d eDP panel mode supported: %d "
-+			"Link: %d eDP panel mode supported: %d "
- 			"eDP panel mode enabled: %d \n",
--			link->connector_index,
-+			link->public.link_index,
- 			link->dpcd_caps.panel_mode_edp,
- 			panel_mode_edp);
- }
-@@ -1268,7 +1269,8 @@ bool dc_link_set_backlight_level(const struct dc_link *public, uint32_t level)
- 
- void core_link_resume(struct core_link *link)
- {
--	program_hpd_filter(link);
-+	if (link->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
-+		program_hpd_filter(link);
- }
- 
- static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 787091f..4c17ff1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1404,8 +1404,8 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 	dal_logger_write(link->ctx->logger,
- 		LOG_MAJOR_HW_TRACE,
- 		LOG_MINOR_HW_TRACE_HPD_IRQ,
--		"%s: Got short pulse HPD on connector %d\n",
--		__func__, link->connector_index);
-+		"%s: Got short pulse HPD on link %d\n",
-+		__func__, link->public.link_index);
- 
- 	 /* All the "handle_hpd_irq_xxx()" methods
- 	 * should be called only after
-@@ -1582,16 +1582,16 @@ static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data,
- 		 * keep receiver powered all the time.*/
- 		case DP_BRANCH_DEVICE_ID_1:
- 		case DP_BRANCH_DEVICE_ID_4:
--			link->dp_wa.bits.KEEP_RECEIVER_POWERED = 1;
-+			link->wa_flags.dp_keep_receiver_powered = true;
- 			break;
- 
- 		/* TODO: May need work around for other dongles. */
- 		default:
--			link->dp_wa.bits.KEEP_RECEIVER_POWERED = 0;
-+			link->wa_flags.dp_keep_receiver_powered = false;
- 			break;
- 		}
- 	} else
--		link->dp_wa.bits.KEEP_RECEIVER_POWERED = 0;
-+		link->wa_flags.dp_keep_receiver_powered = false;
- }
- 
- static void retrieve_link_cap(struct core_link *link)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 27acac8..e9ae9e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -72,7 +72,7 @@ void dp_enable_link_phy(
- 
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- {
--	if (!link->dp_wa.bits.KEEP_RECEIVER_POWERED)
-+	if (!link->wa_flags.dp_keep_receiver_powered)
- 		dp_receiver_power_ctrl(link, false);
- 
- 	link->dc->hwss.encoder_disable_output(link->link_enc, signal);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 1ad317a..557f918 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -457,8 +457,11 @@ static void fill_display_configs(
- 			cfg->src_width = stream->public.src.width;
- 			cfg->ddi_channel_mapping =
- 				stream->sink->link->ddi_channel_mapping.raw;
--			cfg->transmitter =
-+			if (stream->signal != SIGNAL_TYPE_VIRTUAL)
-+				cfg->transmitter =
- 				stream->sink->link->link_enc->transmitter;
-+			else
-+				cfg->transmitter = TRANSMITTER_UNKNOWN;
- 			cfg->link_settings =
- 					stream->sink->link->cur_link_settings;
- 			cfg->sym_clock = stream->public.timing.pix_clk_khz;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-index 3d537d5..608fb99 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-@@ -48,7 +48,7 @@ static void destruct(struct sink *sink)
- 
- }
- 
--static bool construct(struct sink *sink, const struct sink_init_data *init_params)
-+static bool construct(struct sink *sink, const struct dc_sink_init_data *init_params)
- {
- 
- 	struct core_link *core_link = DC_LINK_TO_LINK(init_params->link);
-@@ -87,12 +87,7 @@ void dc_sink_release(const struct dc_sink *dc_sink)
- 	}
- }
- 
--
--/*******************************************************************************
-- * Protected functions - visible only inside of DC (not visible in DM)
-- ******************************************************************************/
--
--struct dc_sink *sink_create(const struct sink_init_data *init_params)
-+struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
- {
- 	struct core_link *core_link = DC_LINK_TO_LINK(init_params->link);
- 
-@@ -116,3 +111,6 @@ alloc_fail:
- 	return NULL;
- }
- 
-+/*******************************************************************************
-+ * Protected functions - visible only inside of DC (not visible in DM)
-+ ******************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 31374ab..b8420bf 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -497,7 +497,7 @@ void dc_target_log(
- 		dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"\tconnector: %d",
--			core_stream->sink->link->connector_index);
-+			"\tlink: %d",
-+			core_stream->sink->link->public.link_index);
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 007fdc4..bcfd96d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -40,6 +40,7 @@
- struct dc_init_data {
- 	struct dc_context *ctx;
- 	struct adapter_service *adapter_srv;
-+	uint8_t num_virtual_links;
- };
- 
- struct dc_caps {
-@@ -311,6 +312,7 @@ void dc_link_remove_sink(
- 	const struct dc_link *link,
- 	const struct dc_sink *sink);
- 
-+
- /*******************************************************************************
-  * Sink Interfaces - A sink corresponds to a display output device
-  ******************************************************************************/
-@@ -329,14 +331,14 @@ void dc_sink_release(const struct dc_sink *sink);
- 
- const struct audio **dc_get_audios(struct dc *dc);
- 
--struct sink_init_data {
-+struct dc_sink_init_data {
- 	enum signal_type sink_signal;
- 	const struct dc_link *link;
- 	uint32_t dongle_max_pix_clk;
- 	bool converter_disable_audio;
- };
- 
--struct dc_sink *sink_create(const struct sink_init_data *init_params);
-+struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
- 
- 
- /*******************************************************************************
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 0d8b050..4f37282 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -802,8 +802,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		 */
- 		stream->tg->funcs->set_blank(stream->tg, true);
- 
--		core_link_disable_stream(
--				stream->sink->link, stream);
-+		if (stream->signal != SIGNAL_TYPE_VIRTUAL)
-+			core_link_disable_stream(stream->sink->link, stream);
- 
- 		/*TODO: AUTO check if timing changed*/
- 		if (false == dal_clock_source_program_pix_clk(
-@@ -822,9 +822,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	}
- 
- 	/*TODO: mst support - use total stream count*/
--	dce110_mem_input_allocate_dmif_buffer(stream->mi,
--			&stream->public.timing,
--			context->target_count);
-+	dce110_mem_input_allocate_dmif_buffer(
-+					stream->mi,
-+					&stream->public.timing,
-+					context->target_count);
- 
- 	if (timing_changed) {
- 		if (false == stream->tg->funcs->enable_crtc(
-@@ -834,10 +835,11 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		}
- 	}
- 
--	if (DC_OK != bios_parser_crtc_source_select(stream)) {
--		BREAK_TO_DEBUGGER();
--		return DC_ERROR_UNEXPECTED;
--	}
-+	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
-+		if (DC_OK != bios_parser_crtc_source_select(stream)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
- 
- 	dce110_opp_set_dyn_expansion(
- 			opp,
-@@ -845,14 +847,12 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			stream->public.timing.display_color_depth,
- 			stream->sink->public.sink_signal);
- 
--	program_fmt(
--			opp,
--			&stream->fmt_bit_depth,
--			&stream->clamping);
-+	program_fmt(opp, &stream->fmt_bit_depth, &stream->clamping);
- 
--	dce110_link_encoder_setup(
--		stream->sink->link->link_enc,
--		stream->signal);
-+	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
-+		dce110_link_encoder_setup(
-+			stream->sink->link->link_enc,
-+			stream->signal);
- 
- 	if (dc_is_dp_signal(stream->signal))
- 		stream->stream_enc->funcs->dp_set_stream_attribute(
-@@ -861,16 +861,16 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 
- 	if (dc_is_hdmi_signal(stream->signal))
- 		stream->stream_enc->funcs->hdmi_set_stream_attribute(
--		stream->stream_enc,
--		&stream->public.timing,
--		stream->audio != NULL);
-+			stream->stream_enc,
-+			&stream->public.timing,
-+			stream->audio != NULL);
- 
- 	if (dc_is_dvi_signal(stream->signal))
- 		stream->stream_enc->funcs->dvi_set_stream_attribute(
--		stream->stream_enc,
--		&stream->public.timing,
--		(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
--		true : false);
-+			stream->stream_enc,
-+			&stream->public.timing,
-+			(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+			true : false);
- 
- 	if (stream->audio != NULL) {
- 		if (AUDIO_RESULT_OK != dal_audio_setup(
-@@ -891,14 +891,12 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 				&stream->audio_output.pll_info);
- 
- 	/* program blank color */
--	color_space = get_output_color_space(
--			&stream->public.timing);
--
-+	color_space = get_output_color_space(&stream->public.timing);
- 	stream->tg->funcs->set_blank_color(
- 			context->res_ctx.pool.timing_generators[controller_idx],
- 			color_space);
- 
--	if (timing_changed) {
-+	if (timing_changed && stream->signal != SIGNAL_TYPE_VIRTUAL) {
- 		core_link_enable_stream(stream->sink->link, stream);
- 	} else {
- 		core_link_update_stream(stream->sink->link, stream);
-@@ -918,7 +916,8 @@ static void power_down_encoders(struct dc *dc)
- 	int i;
- 
- 	for (i = 0; i < dc->link_count; i++) {
--		dce110_link_encoder_disable_output(
-+		if (dc->links[i]->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
-+			dce110_link_encoder_disable_output(
- 				dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
- 	}
- }
-@@ -1571,7 +1570,8 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 		stream->audio = NULL;
- 	}
- 
--	core_link_disable_stream(stream->sink->link, stream);
-+	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
-+		core_link_disable_stream(stream->sink->link, stream);
- 
- 	stream->tg->funcs->set_blank(stream->tg, true);
- 	stream->tg->funcs->disable_crtc(stream->tg);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 266b761..f3610b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -528,14 +528,17 @@ static enum dc_status validate_mapped_resource(
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct core_link *link = stream->sink->link;
- 
--			status = build_stream_hw_param(stream);
-+			if (!stream->tg->funcs->validate_timing(
-+					stream->tg, &stream->public.timing))
-+				return DC_FAIL_CONTROLLER_VALIDATE;
- 
--			if (status != DC_OK)
-+			if (stream->signal == SIGNAL_TYPE_VIRTUAL)
- 				return status;
- 
--			if (!stream->tg->funcs->validate_timing(stream->tg, &stream->public.timing))
--				return DC_FAIL_CONTROLLER_VALIDATE;
-+			status = build_stream_hw_param(stream);
- 
-+			if (status != DC_OK)
-+				return status;
- 
- 			if (!dce110_link_encoder_validate_output_with_stream(
- 					link->link_enc,
-@@ -781,7 +784,8 @@ static enum dc_status map_clock_resources(
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			if (dc_is_dp_signal(stream->signal))
-+			if (dc_is_dp_signal(stream->signal)
-+				|| stream->signal == SIGNAL_TYPE_VIRTUAL)
- 				stream->clock_source = context->res_ctx.
- 					pool.clock_sources[DCE110_CLK_SRC_EXT];
- 			else
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-index 1b091be..85cff3b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -227,6 +227,23 @@ enum dc_status dce_base_map_resources(
- 
- 			attach_stream_to_controller(&context->res_ctx, stream);
- 
-+			set_stream_signal(stream);
-+
-+			curr_stream =
-+				dc->current_context.res_ctx.controller_ctx
-+				[stream->controller_idx].stream;
-+			context->res_ctx.controller_ctx[stream->controller_idx]
-+			.flags.timing_changed =
-+				check_timing_change(curr_stream, stream);
-+
-+			/*
-+			 * we do not need stream encoder or audio resources
-+			 * when connecting to virtual link
-+			 */
-+			if (stream->sink->link->public.connector_signal ==
-+							SIGNAL_TYPE_VIRTUAL)
-+				continue;
-+
- 			stream->stream_enc =
- 				find_first_free_match_stream_enc_for_link(
- 					&context->res_ctx,
-@@ -239,8 +256,6 @@ enum dc_status dce_base_map_resources(
- 					&context->res_ctx,
- 					stream->stream_enc);
- 
--			set_stream_signal(stream);
--
- 			/* TODO: Add check if ASIC support and EDID audio */
- 			if (!stream->sink->converter_disable_audio &&
- 						dc_is_audio_capable_signal(
-@@ -254,13 +269,6 @@ enum dc_status dce_base_map_resources(
- 				set_audio_in_use(&context->res_ctx,
- 						stream->audio);
- 			}
--			curr_stream =
--				dc->current_context.res_ctx.controller_ctx
--				[stream->controller_idx].stream;
--			context->res_ctx.controller_ctx[stream->controller_idx]
--			.flags.timing_changed =
--				check_timing_change(curr_stream, stream);
--
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index 66f7544..9d62a24 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -17,7 +17,7 @@ struct dc {
- 
- 	/** link-related data - begin **/
- 	uint8_t link_count;
--	struct core_link **links;
-+	struct core_link *links[MAX_PIPES * 2];
- 	/** link-related data - end **/
- 
- 	/* TODO: determine max number of targets*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 5f918c1..192399b 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -202,8 +202,6 @@ struct core_link {
- 
- 	struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/
- 
--	uint8_t connector_index; /* this will be mapped to the HPD pins */
--
- 	struct adapter_service *adapter_srv;
- 	struct link_encoder *link_enc;
- 	struct ddc_service *ddc;
-@@ -221,10 +219,13 @@ struct core_link {
- 	unsigned int dpcd_sink_count;
- 
- 	enum edp_revision edp_revision;
--	union dp_wa dp_wa;
- 
- 	/* MST record stream using this link */
- 	struct dp_mst_stream_allocation_table stream_alloc_table;
-+
-+	struct link_flags {
-+		bool dp_keep_receiver_powered;
-+	} wa_flags;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 5539c19..5ec4784 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -136,6 +136,7 @@ struct dal_init_data {
- 	struct dal_override_parameters display_param;
- 	void *driver; /* ctx */
- 	void *cgs_device;
-+	uint8_t num_virtual_links;
- };
- 
- struct dal_dc_init_data {
-diff --git a/drivers/gpu/drm/amd/dal/include/signal_types.h b/drivers/gpu/drm/amd/dal/include/signal_types.h
-index e95e821..a50f7ed 100644
---- a/drivers/gpu/drm/amd/dal/include/signal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/signal_types.h
-@@ -37,8 +37,9 @@ enum signal_type {
- 	SIGNAL_TYPE_DISPLAY_PORT_MST	= (1 << 6),
- 	SIGNAL_TYPE_EDP			= (1 << 7),
- 	SIGNAL_TYPE_WIRELESS		= (1 << 8),	/* Wireless Display */
-+	SIGNAL_TYPE_VIRTUAL		= (1 << 9),	/* Virtual Display */
- 
--	SIGNAL_TYPE_COUNT		= 9,
-+	SIGNAL_TYPE_COUNT		= 10,
- 	SIGNAL_TYPE_ALL			= (1 << SIGNAL_TYPE_COUNT) - 1
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0682-drm-amd-dal-Split-sinks-into-physical-sink-pointer-a.patch b/common/recipes-kernel/linux/files/0682-drm-amd-dal-Split-sinks-into-physical-sink-pointer-a.patch
deleted file mode 100644
index 0a94c886..00000000
--- a/common/recipes-kernel/linux/files/0682-drm-amd-dal-Split-sinks-into-physical-sink-pointer-a.patch
+++ /dev/null
@@ -1,288 +0,0 @@
-From b92469fcc4bf7e3291852123f38c4f66c6d58545 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 8 Jan 2016 16:28:50 -0500
-Subject: [PATCH 0682/1110] drm/amd/dal: Split sinks into physical sink pointer
- and array of sinks for MST
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 38 +++-------------------
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  8 ++---
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 12 +++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 26 +++++----------
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  7 ++--
- .../drm/amd/dal/dc/dce_base/dce_base_resource.c    |  6 +++-
- 6 files changed, 31 insertions(+), 66 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index a98d1dd..118821d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -698,47 +698,19 @@ static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
- 	.atomic_commit = amdgpu_dm_atomic_commit
- };
- 
--static bool dm_get_sink_from_link(const struct dc_link *link,
--						struct amdgpu_connector *aconnector,
--						const struct dc_sink **sink)
--{
--	int i;
--	*sink = NULL;
--
--	if (!link->sink_count) {
--		DRM_INFO("No sinks on link!\n");
--		return true;
--	} else if (link->sink_count > 1 && !aconnector) {
--		DRM_ERROR("Multi sink link but no connector given!\n");
--		return false;
--	}
--
--	if (link->sink_count == 1) {
--		*sink = link->sink[0];
--		return true;
--	}
--
--	for (i = 0; i < link->sink_count; i++)
--		if (aconnector->dc_sink == link->sink[i])
--			*sink =  aconnector->dc_sink;
--
--	return true;
--}
- 
- void amdgpu_dm_update_connector_after_detect(
- 	struct amdgpu_connector *aconnector)
- {
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
--	const struct dc_link *dc_link = aconnector->dc_link;
- 	const struct dc_sink *sink;
- 
- 	/* MST handled by drm_mst framework */
- 	if (aconnector->mst_mgr.mst_state == true)
- 		return;
- 
--	if (!dm_get_sink_from_link(dc_link, aconnector, &sink))
--		return;
-+	sink = aconnector->dc_link->local_sink;
- 
- 	/*
- 	 * TODO: temporary guard to look for proper fix
-@@ -789,13 +761,11 @@ static void handle_hpd_irq(void *param)
- 	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
--	bool mst_connector = aconnector->mst_mgr.mst_state;
- 
- 	dc_link_detect(aconnector->dc_link);
--	/*Wait for complition of all MST connectors reset
--	 * so the link is clean from sinks. */
--	if (mst_connector && aconnector->dc_link->type == dc_connection_none)
--		flush_work(&aconnector->mst_mgr.destroy_connector_work);
-+	if (aconnector->dc_link->type == dc_connection_mst_branch)
-+		return;
-+
- 	amdgpu_dm_update_connector_after_detect(aconnector);
- 	drm_kms_helper_hotplug_event(dev);
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 61e12ad..88b9730 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -147,7 +147,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 	dc_service_memmove(dc_sink->dc_edid.raw_edid, edid, len);
- 	dc_sink->dc_edid.length = len;
- 
--	if (!dc_link_add_sink(
-+	if (!dc_link_add_remote_sink(
- 			dc_link,
- 			dc_sink))
- 		goto fail_add_sink;
-@@ -163,7 +163,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 
- 	return dc_sink;
- fail:
--	dc_link_remove_sink(dc_link, dc_sink);
-+	dc_link_remove_remote_sink(dc_link, dc_sink);
- fail_add_sink:
- 	return NULL;
- }
-@@ -190,7 +190,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
- 		aconnector->edid = edid;
- 
- 		if (aconnector->dc_sink)
--			dc_link_remove_sink(
-+			dc_link_remove_remote_sink(
- 				aconnector->dc_link,
- 				aconnector->dc_sink);
- 
-@@ -354,7 +354,7 @@ static void dm_dp_destroy_mst_connector(
- 
- 	aconnector->port = NULL;
- 	if (aconnector->dc_sink)
--		dc_link_remove_sink(aconnector->dc_link, aconnector->dc_sink);
-+		dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
- }
- 
- static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 397b664..e003f78 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -838,7 +838,7 @@ bool dc_write_dpcd(
- 	return r == DDC_RESULT_SUCESSFULL;
- }
- 
--bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
-+bool dc_link_add_remote_sink(const struct dc_link *link, struct dc_sink *sink)
- {
- 	struct core_link *core_link = DC_LINK_TO_LINK(link);
- 	struct dc_link *dc_link = &core_link->public;
-@@ -848,7 +848,7 @@ bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
- 		return false;
- 	}
- 
--	dc_link->sink[link->sink_count] = sink;
-+	dc_link->remote_sinks[link->sink_count] = sink;
- 	dc_link->sink_count++;
- 	if (sink->sink_signal == SIGNAL_TYPE_VIRTUAL
- 		&& link->connector_signal == SIGNAL_TYPE_VIRTUAL)
-@@ -858,7 +858,7 @@ bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
- }
- 
- 
--void dc_link_remove_sink(const struct dc_link *link, const struct dc_sink *sink)
-+void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
- {
- 	int i;
- 	struct core_link *core_link = DC_LINK_TO_LINK(link);
-@@ -870,13 +870,13 @@ void dc_link_remove_sink(const struct dc_link *link, const struct dc_sink *sink)
- 	}
- 
- 	for (i = 0; i < dc_link->sink_count; i++) {
--		if (dc_link->sink[i] == sink) {
-+		if (dc_link->remote_sinks[i] == sink) {
- 			dc_sink_release(sink);
--			dc_link->sink[i] = NULL;
-+			dc_link->remote_sinks[i] = NULL;
- 
- 			/* shrink array to remove empty place */
- 			while (i < dc_link->sink_count - 1) {
--				dc_link->sink[i] = dc_link->sink[i+1];
-+				dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
- 				i++;
- 			}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 2ef0451..c5ff145 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -427,15 +427,12 @@ static bool is_dp_active_dongle(enum display_dongle_type dongle_type)
- 		dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
- }
- 
--static void link_disconnect_all_sinks(struct core_link *link)
-+static void link_disconnect_sink(struct core_link *link)
- {
--	/*
--	 * as sink_count changed inside dc_link_remove_sink, we should not
--	 * use it for range check for loop, because half of sinks will not
--	 * be removed
--	 */
--	while (link->public.sink_count)
--		dc_link_remove_sink(&link->public, link->public.sink[0]);
-+	if (link->public.local_sink) {
-+		dc_sink_release(link->public.local_sink);
-+		link->public.local_sink = NULL;
-+	}
- 
- 	link->dpcd_sink_count = 0;
- }
-@@ -496,7 +493,7 @@ static void dc_link_detect_dp(
- 				/*
- 				 * active dongle unplug processing for short irq
- 				 */
--				link_disconnect_all_sinks(link);
-+				link_disconnect_sink(link);
- 				return;
- 			}
- 
-@@ -574,10 +571,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		return;
- 	}
- 
--	/* Free existing state before doing detection on SST
--	 * TODO: For MST, need to investigate if the same is required. */
--	if (link->public.type != dc_connection_mst_branch)
--		link_disconnect_all_sinks(link);
-+	link_disconnect_sink(link);
- 
- 	if (new_connection_type != dc_connection_none) {
- 		link->public.type = new_connection_type;
-@@ -657,11 +651,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		}
- 
- 		sink = DC_SINK_TO_CORE(dc_sink);
--
--		/*AG TODO handle failure */
--		/*Only non MST case here */
--		if (!dc_link_add_sink(&link->public, &sink->public))
--				BREAK_TO_DEBUGGER();
-+		link->public.local_sink = &sink->public;
- 
- 		edid_status = read_edid(link, sink);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index bcfd96d..df7e34b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -272,8 +272,9 @@ void dc_update_stream(const struct dc_stream *dc_stream,
-  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
-  */
- struct dc_link {
--	const struct dc_sink *sink[MAX_SINKS_PER_LINK];
-+	const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
- 	unsigned int sink_count;
-+	const struct dc_sink *local_sink;
- 	unsigned int link_index;
- 	enum dc_connection_type type;
- 	enum signal_type connector_signal;
-@@ -306,9 +307,9 @@ void dc_link_detect(const struct dc_link *dc_link);
-  * from DM. */
- bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link);
- 
--bool dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink);
-+bool dc_link_add_remote_sink(const struct dc_link *link, struct dc_sink *sink);
- 
--void dc_link_remove_sink(
-+void dc_link_remove_remote_sink(
- 	const struct dc_link *link,
- 	const struct dc_sink *sink);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-index 85cff3b..0907f3c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-@@ -93,6 +93,7 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
- {
- 	uint8_t i;
- 	int8_t j = -1;
-+	const struct dc_sink *sink = NULL;
- 
- 	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
- 		if (!res_ctx->is_stream_enc_acquired[i] &&
-@@ -118,7 +119,10 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
- 	 * TODO - This is just a patch up and a generic solution is
- 	 * required for non DP connectors.
- 	 */
--	if (j >= 0 &&  dc_is_dp_signal(link->public.sink[0]->sink_signal))
-+
-+	sink = link->public.local_sink ? link->public.local_sink : link->public.remote_sinks[0];
-+
-+	if (sink && j >= 0 &&  dc_is_dp_signal(sink->sink_signal))
- 		return res_ctx->pool.stream_enc[j];
- 
- 	return NULL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0683-drm-amd-dal-Define-interface-for-External-VBIOS-part.patch b/common/recipes-kernel/linux/files/0683-drm-amd-dal-Define-interface-for-External-VBIOS-part.patch
deleted file mode 100644
index 85c17bf2..00000000
--- a/common/recipes-kernel/linux/files/0683-drm-amd-dal-Define-interface-for-External-VBIOS-part.patch
+++ /dev/null
@@ -1,354 +0,0 @@
-From 028d2eb5ef5519c27bdbf497651faf9273559c0f Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Fri, 8 Jan 2016 15:40:44 -0500
-Subject: [PATCH 0683/1110] drm/amd/dal: Define interface for External VBIOS -
- part 1.
-
-Current use is to allow Diagnositcs/Validation of DCE on FPGA.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   | 36 ++++++++++++++-----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h   |  3 +-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 14 +++++++-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h      |  6 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  9 +++--
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         | 40 ++++++++++++++++++++++
- .../amd/dal/include/adapter_service_interface.h    |  1 +
- .../drm/amd/dal/include/bios_parser_interface.h    |  7 ++--
- drivers/gpu/drm/amd/dal/include/dal_types.h        |  4 +++
- 9 files changed, 104 insertions(+), 16 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 4f9a637..6084466 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -34,6 +34,7 @@
- #include "include/asic_capability_interface.h"
- #include "include/logger_interface.h"
- 
-+#include "dc_bios_types.h"
- #include "adapter_service.h"
- #include "hw_ctx_adapter_service.h"
- #include "wireless_data_source.h"
-@@ -735,10 +736,16 @@ static bool adapter_service_construct(
- 		goto failed_to_generate_features;
- 	}
- 
--	/* Create BIOS parser */
--	init_data->bp_init_data.ctx = init_data->ctx;
--	as->bios_parser =
--		dal_bios_parser_create(&init_data->bp_init_data, as);
-+	if (init_data->vbios_override) {
-+		/* TODO: remove the typecast */
-+		as->bios_parser = (struct bios_parser *)init_data->vbios_override;
-+	} else {
-+		/* Create BIOS parser */
-+		init_data->bp_init_data.ctx = init_data->ctx;
-+
-+		as->bios_parser =
-+			dal_bios_parser_create(&init_data->bp_init_data, as);
-+	}
- 
- 	if (!as->bios_parser) {
- 		ASSERT_CRITICAL(false);
-@@ -905,7 +912,6 @@ uint8_t dal_adapter_service_get_controllers_num(
- 	return result;
- }
- 
--
- /** Get total number of connectors.
-  *
-  * \param as	Adapter Service
-@@ -918,9 +924,13 @@ uint8_t dal_adapter_service_get_connectors_num(
- {
- 	uint8_t vbios_connectors_num = 0;
- 	uint8_t wireless_connectors_num = 0;
-+	struct dc_bios *dcb;
-+
-+	/* TODO: remove type cast */
-+	dcb = (struct dc_bios*)dal_adapter_service_get_bios_parser(as);
-+
-+	vbios_connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
--	vbios_connectors_num = dal_bios_parser_get_connectors_number(
--			as->bios_parser);
- 	wireless_connectors_num = wireless_get_connectors_num(as);
- 
- 	return vbios_connectors_num + wireless_connectors_num;
-@@ -1004,8 +1014,13 @@ struct graphics_object_id dal_adapter_service_get_connector_obj_id(
- 		struct adapter_service *as,
- 		uint8_t connector_index)
- {
--	uint8_t bios_connectors_num =
--		dal_bios_parser_get_connectors_number(as->bios_parser);
-+	struct dc_bios *dcb;
-+	uint8_t bios_connectors_num;
-+
-+	/* TODO: remove type cast */
-+	dcb = (struct dc_bios*)dal_adapter_service_get_bios_parser(as);
-+
-+	bios_connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
- 	if (connector_index >= bios_connectors_num)
- 		return wireless_get_connector_id(
-@@ -1651,9 +1666,12 @@ uint32_t dal_adapter_service_get_memory_type_multiplier(
-  *
-  * Get BIOS parser handler
-  */
-+/* TODO: change return type to 'dc_bios'. */
- struct bios_parser *dal_adapter_service_get_bios_parser(
- 	struct adapter_service *as)
- {
-+	/* TODO: conditionally return 'override' or 'real'.
-+	 * Works for now because 'base' is first member of 'bios parser' */
- 	return as->bios_parser;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-index 25ac648..dd5bb00 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -35,12 +35,13 @@
-  */
- struct gpio_service;
- struct asic_cap;
-+struct dc_bios;
- 
- /* Adapter service */
- struct adapter_service {
- 	struct dc_context *ctx;
- 	struct asic_capability *asic_cap;
--	struct bios_parser *bios_parser;
-+	struct bios_parser *bios_parser;/* TODO: remove it. replace by struct dc_bios *dcb; */
- 	struct gpio_service *gpio_service;
- 	struct i2caux *i2caux;
- 	struct wireless_data wireless_data;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 1d02be9..3329322 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -27,6 +27,7 @@
- 
- #include "atom.h"
- 
-+#include "dc_bios_types.h"
- #include "include/adapter_service_interface.h"
- #include "include/grph_object_ctrl_defs.h"
- #include "include/bios_parser_interface.h"
-@@ -98,6 +99,13 @@ static void process_ext_display_connection_info(struct bios_parser *bp);
- #define BIOS_IMAGE_SIZE_OFFSET 2
- #define BIOS_IMAGE_SIZE_UNIT 512
- 
-+/*****************************************************************************/
-+static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb);
-+
-+const struct dc_vbios_funcs vbios_funcs = {
-+	.get_connectors_number = bios_parser_get_connectors_number
-+};
-+
- static bool bios_parser_construct(
- 	struct bios_parser *bp,
- 	struct bp_init_data *init,
-@@ -117,6 +125,8 @@ static bool bios_parser_construct(
- 	if (!init->bios)
- 		return false;
- 
-+	bp->base.funcs = &vbios_funcs;
-+
- 	dce_version = dal_adapter_service_get_dce_version(as);
- 	bp->ctx = init->ctx;
- 	bp->as = as;
-@@ -255,8 +265,10 @@ uint8_t dal_bios_parser_get_encoders_number(struct bios_parser *bp)
- 		le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset));
- }
- 
--uint8_t dal_bios_parser_get_connectors_number(struct bios_parser *bp)
-+static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	return get_number_of_objects(bp,
- 		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset));
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-index db169f1..f8fa108 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-@@ -26,6 +26,7 @@
- #ifndef __DAL_BIOS_PARSER_H__
- #define __DAL_BIOS_PARSER_H__
- 
-+#include "dc_bios_types.h"
- #include "bios_parser_helper.h"
- 
- struct atom_data_revision {
-@@ -50,6 +51,7 @@ enum spread_spectrum_id {
- };
- 
- struct bios_parser {
-+	struct dc_bios base;
- 	struct dc_context *ctx;
- 	struct adapter_service *as;
- 
-@@ -75,4 +77,8 @@ struct bios_parser {
- 	bool headless_no_opm;
- };
- 
-+/* Bios Parser from DC Bios */
-+#define BP_FROM_DCB(dc_bios) \
-+	container_of(dc_bios, struct bios_parser, base)
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e003f78..00a2453 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -34,6 +34,7 @@
- 
- #include "adapter_service_interface.h"
- #include "clock_source_interface.h"
-+#include "dc_bios_types.h"
- 
- #include "include/irq_service_interface.h"
- #include "bandwidth_calcs.h"
-@@ -77,12 +78,13 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- {
- 	int i;
- 	int connectors_num;
-+	struct dc_bios *dcb;
- 
- 	dc->link_count = 0;
- 
--	connectors_num = dal_bios_parser_get_connectors_number(
--			dal_adapter_service_get_bios_parser(
--					init_params->adapter_srv));
-+	dcb = (struct dc_bios*)dal_adapter_service_get_bios_parser(init_params->adapter_srv);
-+
-+	connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
- 	if (0 == connectors_num || connectors_num > ENUM_ID_COUNT) {
- 		dal_error("DC: Invalid number of connectors!\n");
-@@ -224,6 +226,7 @@ static struct adapter_service *create_as(
- 	init_data.bdf_info = init->bdf_info;
- 
- 	init_data.display_param = &init->display_param;
-+	init_data.vbios_override = init->vbios_override;
- 
- 	as = dal_adapter_service_create(&init_data);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-new file mode 100644
-index 0000000..a82cbee
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_BIOS_TYPES_H
-+#define DC_BIOS_TYPES_H
-+
-+struct dc_vbios_funcs;
-+
-+struct dc_bios {
-+	const struct dc_vbios_funcs *funcs;
-+};
-+
-+struct dc_vbios_funcs {
-+	uint8_t (*get_connectors_number)(struct dc_bios *bios);
-+};
-+
-+
-+#endif /* DC_BIOS_TYPES_H */
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-index aa503a8..e449db6 100644
---- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-@@ -322,6 +322,7 @@ struct as_init_data {
- 	struct dc_context *ctx;
- 	struct bdf_info bdf_info;
- 	const struct dal_override_parameters *display_param;
-+	struct dc_bios *vbios_override;
- };
- 
- /* Create adapter service */
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-index 13fa8ab..77999fc 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -57,6 +57,8 @@ struct bios_parser *dal_bios_parser_create(
- 	struct adapter_service *as);
- void dal_bios_parser_destroy(
- 	struct bios_parser **bp);
-+
-+
- void dal_bios_parser_power_down(
- 	struct bios_parser *bp);
- void dal_bios_parser_power_up(
-@@ -64,8 +66,6 @@ void dal_bios_parser_power_up(
- 
- uint8_t dal_bios_parser_get_encoders_number(
- 	struct bios_parser *bp);
--uint8_t dal_bios_parser_get_connectors_number(
--	struct bios_parser *bp);
- uint32_t dal_bios_parser_get_oem_ddc_lines_number(
- 	struct bios_parser *bp);
- struct graphics_object_id dal_bios_parser_get_encoder_id(
-@@ -294,4 +294,7 @@ struct integrated_info *dal_bios_parser_create_integrated_info(
- 
- /* Destroy provided integrated info */
- void dal_bios_parser_destroy_integrated_info(struct dc_context *ctx, struct integrated_info **info);
-+
-+
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 5ec4784..caaacf6 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -30,6 +30,7 @@
- #include "dc_types.h"
- 
- struct dal_logger;
-+struct dc_bios;
- 
- enum dce_version {
- 	DCE_VERSION_UNKNOWN = (-1),
-@@ -137,6 +138,9 @@ struct dal_init_data {
- 	void *driver; /* ctx */
- 	void *cgs_device;
- 	uint8_t num_virtual_links;
-+	/* If 'vbios_override' not NULL, it will be called instead
-+	 * of the real VBIOS. Intended use is Diagnostics on FPGA. */
-+	struct dc_bios *vbios_override;
- };
- 
- struct dal_dc_init_data {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0684-drm-amd-dal-Don-t-handle-DP-short-pulse-until-necess.patch b/common/recipes-kernel/linux/files/0684-drm-amd-dal-Don-t-handle-DP-short-pulse-until-necess.patch
deleted file mode 100644
index 8be2f454..00000000
--- a/common/recipes-kernel/linux/files/0684-drm-amd-dal-Don-t-handle-DP-short-pulse-until-necess.patch
+++ /dev/null
@@ -1,168 +0,0 @@
-From 970cdba09cfb837d01232020b6e8381a6fe301c1 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Mon, 11 Jan 2016 11:45:11 -0500
-Subject: [PATCH 0684/1110] drm/amd/dal: Don't handle DP short pulse until
- necessary
-
-We shouldn't handle DP short pulse interrupts until one
-of the following is met
-1) The link is established (cur_link_settings != unknown)
-2) We kicked off MST detection
-3) We know we're dealing with an active dongle
-
-This works around an issue where the short pulse handler
-is trying to acquire the AUX line while EDID read is
-still happening. We still don't protect the AUX line
-properly in this case.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c    | 13 +++-------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 36 ++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h  |  7 +++++-
- 3 files changed, 45 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index c5ff145..e9e36c8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -420,13 +420,6 @@ static enum signal_type dp_passive_dongle_detection(
- 			audio_support);
- }
- 
--static bool is_dp_active_dongle(enum display_dongle_type dongle_type)
--{
--	return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
--		dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
--		dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
--}
--
- static void link_disconnect_sink(struct core_link *link)
- {
- 	if (link->public.local_sink) {
-@@ -472,7 +465,7 @@ static enum dc_edid_status read_edid(
- 	return edid_status;
- }
- 
--static void dc_link_detect_dp(
-+static void detect_dp(
- 	struct core_link *link,
- 	struct display_sink_capability *sink_caps,
- 	bool *converter_disable_audio,
-@@ -487,7 +480,7 @@ static void dc_link_detect_dp(
- 		detect_dp_sink_caps(link);
- 
- 		/* DP active dongles */
--		if (is_dp_active_dongle(link->dpcd_caps.dongle_type)) {
-+		if (is_dp_active_dongle(link)) {
- 			if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
- 				link->public.type = dc_connection_none;
- 				/*
-@@ -608,7 +601,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		}
- 
- 		case SIGNAL_TYPE_DISPLAY_PORT: {
--			dc_link_detect_dp(
-+			detect_dp(
- 				link,
- 				&sink_caps,
- 				&converter_disable_audio,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 4c17ff1..eaea78e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1,6 +1,7 @@
- /* Copyright 2015 Advanced Micro Devices, Inc. */
- #include "dc_services.h"
- #include "dc.h"
-+#include "dc_link_dp.h"
- #include "dc_helpers.h"
- #include "inc/core_types.h"
- #include "link_hwss.h"
-@@ -1391,6 +1392,23 @@ static enum dc_status read_hpd_rx_irq_data(
- 	sizeof(union hpd_irq_data));
- }
- 
-+static bool allow_hpd_rx_irq(const struct core_link *link)
-+{
-+	/*
-+	 * Don't handle RX IRQ unless one of following is met:
-+	 * 1) The link is established (cur_link_settings != unknown)
-+	 * 2) We kicked off MST detection
-+	 * 3) We know we're dealing with an active dongle
-+	 */
-+
-+	if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
-+		(link->public.type == dc_connection_mst_branch) ||
-+		is_dp_active_dongle(link))
-+		return true;
-+
-+	return false;
-+}
-+
- bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- {
- 	struct core_link *link = DC_LINK_TO_LINK(dc_link);
-@@ -1407,6 +1425,15 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 		"%s: Got short pulse HPD on link %d\n",
- 		__func__, link->public.link_index);
- 
-+	if (!allow_hpd_rx_irq(link)) {
-+		dal_logger_write(link->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_HW_TRACE_HPD_IRQ,
-+			"%s: skipping HPD handling on %d\n",
-+			__func__, link->public.link_index);
-+		return false;
-+	}
-+
- 	 /* All the "handle_hpd_irq_xxx()" methods
- 	 * should be called only after
- 	 * dal_dpsst_ls_read_hpd_irq_data
-@@ -1480,6 +1507,15 @@ bool is_mst_supported(struct core_link *link)
- 
- }
- 
-+bool is_dp_active_dongle(const struct core_link *link)
-+{
-+	enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
-+
-+	return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
-+			(dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
-+			(dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
-+}
-+
- static void get_active_converter_info(
- 	uint8_t data, struct core_link *link)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-index e3e4778..682c0b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-@@ -26,6 +26,10 @@
- #ifndef __DC_LINK_DP_H__
- #define __DC_LINK_DP_H__
- 
-+struct core_link;
-+struct core_stream;
-+struct link_settings;
-+
- bool dp_hbr_verify_link_cap(
- 	struct core_link *link,
- 	struct link_settings *known_limit_link_setting);
-@@ -43,9 +47,10 @@ bool perform_link_training(
- 	const struct link_settings *link_setting,
- 	bool skip_video_pattern);
- 
--/*dp mst functions*/
- bool is_mst_supported(struct core_link *link);
- 
- void detect_dp_sink_caps(struct core_link *link);
- 
-+bool is_dp_active_dongle(const struct core_link *link);
-+
- #endif /* __DC_LINK_DP_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0685-drm-amd-dal-Avoid-flood-kernel-with-storm-of-work-it.patch b/common/recipes-kernel/linux/files/0685-drm-amd-dal-Avoid-flood-kernel-with-storm-of-work-it.patch
deleted file mode 100644
index 00775cf4..00000000
--- a/common/recipes-kernel/linux/files/0685-drm-amd-dal-Avoid-flood-kernel-with-storm-of-work-it.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From b3d16ddfc98550586b5c2534532bf4bfc8941a83 Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Mon, 11 Jan 2016 14:19:10 -0500
-Subject: [PATCH 0685/1110] drm/amd/dal: Avoid flood kernel with storm of work
- items
-
-Add work item to system only when handler is  available.
-The change decrease the boot time and improve system
-performance by not overload the system thread pool with
-thousands of empty work items.
-
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index ab6df66..7cfb754 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -558,15 +558,21 @@ static void amdgpu_dm_irq_schedule_work(
- 	enum dc_irq_source irq_source)
- {
- 	unsigned long irq_table_flags;
-+	struct work_struct *work = NULL;
- 
- 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
- 
--	/* Since the caller is interested in 'work_struct' then
--	 * the irq will be post-processed at "INTERRUPT_LOW_IRQ_CONTEXT". */
--
--	schedule_work(&adev->dm.irq_handler_list_low_tab[irq_source].work);
-+	if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
-+		work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
- 
- 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	if (work) {
-+		if (!schedule_work(work))
-+			DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
-+						irq_source);
-+	}
-+
- }
- 
- /** amdgpu_dm_irq_immediate_work
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0686-drm-amd-dal-Skip-notification-for-MST-connectors.patch b/common/recipes-kernel/linux/files/0686-drm-amd-dal-Skip-notification-for-MST-connectors.patch
deleted file mode 100644
index a82dcd7d..00000000
--- a/common/recipes-kernel/linux/files/0686-drm-amd-dal-Skip-notification-for-MST-connectors.patch
+++ /dev/null
@@ -1,193 +0,0 @@
-From 8b19f17d2f345718701054ebe6ef1cf21c8a64a0 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Sat, 9 Jan 2016 23:59:18 -0500
-Subject: [PATCH 0686/1110] drm/amd/dal: Skip notification for MST connectors
-
-Skip connector status update and notification for MST connectors
-and for detection failures.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 27 +++++++++++-----------
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  4 +++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 16 ++++++-------
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  8 +++++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  2 +-
- 5 files changed, 32 insertions(+), 25 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 118821d..cee507c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -762,12 +762,13 @@ static void handle_hpd_irq(void *param)
- 	struct drm_connector *connector = &aconnector->base;
- 	struct drm_device *dev = connector->dev;
- 
--	dc_link_detect(aconnector->dc_link);
--	if (aconnector->dc_link->type == dc_connection_mst_branch)
--		return;
--
--	amdgpu_dm_update_connector_after_detect(aconnector);
--	drm_kms_helper_hotplug_event(dev);
-+	/* In case of failure or MST no need to update connector status or notify the OS
-+	 * since (for MST case) MST does this in it's own context.
-+	 */
-+	if (dc_link_detect(aconnector->dc_link)) {
-+		amdgpu_dm_update_connector_after_detect(aconnector);
-+		drm_kms_helper_hotplug_event(dev);
-+	}
- }
- 
- static void handle_hpd_rx_irq(void *param)
-@@ -780,9 +781,10 @@ static void handle_hpd_rx_irq(void *param)
- 	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) &&
- 			!is_mst_root_connector) {
- 		/* Downstream Port status changed. */
--		dc_link_detect(aconnector->dc_link);
--		amdgpu_dm_update_connector_after_detect(aconnector);
--		drm_kms_helper_hotplug_event(dev);
-+		if (dc_link_detect(aconnector->dc_link)) {
-+			amdgpu_dm_update_connector_after_detect(aconnector);
-+			drm_kms_helper_hotplug_event(dev);
-+		}
- 	}
- 
- 	if (is_mst_root_connector)
-@@ -1055,10 +1057,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 			goto fail_free_connector;
- 		}
- 
--		dc_link_detect(dc_get_link_at_index(dm->dc, i));
--
--		amdgpu_dm_update_connector_after_detect(
--			aconnector);
-+		if (dc_link_detect(dc_get_link_at_index(dm->dc, i)))
-+			amdgpu_dm_update_connector_after_detect(
-+				aconnector);
- 	}
- 
- 	/* Software is initialized. Now we can register interrupt handlers. */
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 88b9730..aeab396 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -353,8 +353,10 @@ static void dm_dp_destroy_mst_connector(
- 				aconnector, connector->base.id, aconnector->mst_port);
- 
- 	aconnector->port = NULL;
--	if (aconnector->dc_sink)
-+	if (aconnector->dc_sink) {
- 		dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
-+		aconnector->dc_sink = NULL;
-+	}
- }
- 
- static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index e9e36c8..a634a44 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -540,7 +540,7 @@ static void detect_dp(
- 	}
- }
- 
--void dc_link_detect(const struct dc_link *dc_link)
-+bool dc_link_detect(const struct dc_link *dc_link)
- {
- 	struct core_link *link = DC_LINK_TO_LINK(dc_link);
- 	struct dc_sink_init_data sink_init_data = { 0 };
-@@ -557,11 +557,11 @@ void dc_link_detect(const struct dc_link *dc_link)
- 	enum dc_connection_type new_connection_type = dc_connection_none;
- 
- 	if (link->public.connector_signal == SIGNAL_TYPE_VIRTUAL)
--		return;
-+		return false;
- 
- 	if (false == detect_sink(link, &new_connection_type)) {
- 		BREAK_TO_DEBUGGER();
--		return;
-+		return false;
- 	}
- 
- 	link_disconnect_sink(link);
-@@ -608,7 +608,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 				&audio_support);
- 
- 			if (link->public.type == dc_connection_mst_branch)
--				return;
-+				return false;
- 
- 			break;
- 		}
-@@ -616,7 +616,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		default:
- 			DC_ERROR("Invalid connector type! signal:%d\n",
- 				link->public.connector_signal);
--			return;
-+			return false;
- 		} /* switch() */
- 
- 		if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
-@@ -640,7 +640,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		dc_sink = dc_sink_create(&sink_init_data);
- 		if (!dc_sink) {
- 			DC_ERROR("Failed to create sink!\n");
--			return;
-+			return false;
- 		}
- 
- 		sink = DC_SINK_TO_CORE(dc_sink);
-@@ -660,7 +660,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 				LOG_MAJOR_ERROR,
- 				LOG_MINOR_DETECTION_EDID_PARSER,
- 				"No EDID read.\n");
--			return;
-+			return false;
- 
- 		default:
- 			break;
-@@ -719,7 +719,7 @@ void dc_link_detect(const struct dc_link *dc_link)
- 		(sink_caps.signal == SIGNAL_TYPE_NONE ?
- 			"Disconnected":"Connected"));
- 
--	return;
-+	return true;
- }
- 
- static enum hpd_source_id get_hpd_line(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index df7e34b..a2f26cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -296,8 +296,12 @@ const struct graphics_object_id dc_get_link_id_at_index(
- /* Set backlight level of an embedded panel (eDP, LVDS). */
- bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level);
- 
--/* Request DC to detect if there is a Panel connected. */
--void dc_link_detect(const struct dc_link *dc_link);
-+/* Request DC to detect if there is a Panel connected.
-+ * Return false for any type of detection failure or MST detection
-+ * true otherwise. True meaning further action is required (status update
-+ * and OS notification).
-+ */
-+bool dc_link_detect(const struct dc_link *dc_link);
- 
- /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
-  * Return:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index f3610b4..80d3f8a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -661,7 +661,7 @@ enum dc_status dce110_validate_bandwidth(
- 		dc->ctx->logger,
- 		LOG_MAJOR_BWM,
- 		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
--		"%s: start",
-+		"%s: start\n",
- 		__func__);
- 
- 	if (!bw_calcs(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0687-drm-amd-dal-Don-t-deallocate-payloads-when-whole-cha.patch b/common/recipes-kernel/linux/files/0687-drm-amd-dal-Don-t-deallocate-payloads-when-whole-cha.patch
deleted file mode 100644
index 07846b6d..00000000
--- a/common/recipes-kernel/linux/files/0687-drm-amd-dal-Don-t-deallocate-payloads-when-whole-cha.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From ac37f391082bdbbd9919148b911b0ad54deccb45 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 12 Jan 2016 12:29:09 -0500
-Subject: [PATCH 0687/1110] drm/amd/dal: Don't deallocate payloads when whole
- chain disconnected
-
-When the whole MST chain is disconnected we don't want to
-deallocate payloads at reset_mode. dc_helpers_dp_mst_stop_top_mgr
-will already clean up mst_mgr internal state.
-
-When switching the first MST monitor in a daisy-chain from MST to SST mode
-this way we avoid GPIO collision between DPCD access for deallocating
-the old MST displays and EDID read for the new SST dispaly.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index a634a44..8bd254c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1501,7 +1501,8 @@ void core_link_disable_stream(
- {
- 	struct dc *dc = stream->ctx->dc;
- 
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST &&
-+		link->public.type == dc_connection_mst_branch)
- 		deallocate_mst_payload(stream);
- 
- 	dc->hwss.disable_stream(stream);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0688-drm-amd-dal-remove-incorrect-assert.patch b/common/recipes-kernel/linux/files/0688-drm-amd-dal-remove-incorrect-assert.patch
deleted file mode 100644
index a92065de..00000000
--- a/common/recipes-kernel/linux/files/0688-drm-amd-dal-remove-incorrect-assert.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 037891c1c1cf9f07e438a78c450770609d7af76b Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Tue, 12 Jan 2016 12:40:25 -0500
-Subject: [PATCH 0688/1110] drm/amd/dal: remove incorrect assert
-
-DRM may remove and add two MST playloads at the same time
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 8bd254c..a994a4c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1360,8 +1360,6 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	}
- 
- 	ASSERT(proposed_table.stream_count > 0);
--	ASSERT(proposed_table.stream_count -
--			link->stream_alloc_table.stream_count == 1);
- 
- 	/*
- 	 * temporary fix. Unplug of MST chain happened (two displays),
-@@ -1457,9 +1455,6 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 		proposed_table.stream_allocations[i].slot_count);
- 	}
- 
--	ASSERT(link->stream_alloc_table.stream_count -
--			proposed_table.stream_count == 1);
--
- 	dc->hwss.update_mst_stream_allocation_table(
- 		link_encoder,
- 		&proposed_table);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0689-drm-amdgpu-Use-non-polling-user-mode-notification-for-DAL.patch b/common/recipes-kernel/linux/files/0689-drm-amdgpu-Use-non-polling-user-mode-notification-for-DAL.patch
deleted file mode 100644
index 14a1f57f..00000000
--- a/common/recipes-kernel/linux/files/0689-drm-amdgpu-Use-non-polling-user-mode-notification-for-DAL.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 7f629b8c628b12e1c913baeb82709b464ddffd7b Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 27 Sep 2016 14:07:02 +0530
-Subject: [PATCH] Use non-polling user mode notification for DAL
-
-DAL do not use polling for user mode notification. This
-change allow actual user mode notification on S3 resume
-when DAL is enabled
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 21 +++++++++++++++------
- 1 file changed, 15 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 59209e4..cfeebcc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1707,12 +1707,14 @@ int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
- 
- 	drm_kms_helper_poll_disable(dev);
- 
--	/* turn off display hw */
--	drm_modeset_lock_all(dev);
--	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
-+	if (!amdgpu_has_dal_support(adev)) {
-+		/* turn off display hw */
-+		drm_modeset_lock_all(dev);
-+		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
-+		}
-+		drm_modeset_unlock_all(dev);
- 	}
--	drm_modeset_unlock_all(dev);
- 
- 	/* unpin the front buffers and cursors */
- 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-@@ -1807,6 +1809,9 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- 	if (r)
- 		DRM_ERROR("amdgpu_resume failed (%d).\n", r);
- 
-+	if (r)
-+		DRM_ERROR("amdgpu_resume failed (%d).\n", r);
-+
- 	amdgpu_fence_driver_resume(adev);
- 
- 	if (resume) {
-@@ -1866,7 +1871,11 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- #ifdef CONFIG_PM
- 	dev->dev->power.disable_depth++;
- #endif
--	drm_helper_hpd_irq_event(dev);
-+
-+	if (!amdgpu_has_dal_support(adev))
-+		drm_helper_hpd_irq_event(dev);
-+	else
-+		drm_kms_helper_hotplug_event(dev);
- #ifdef CONFIG_PM
- 	dev->dev->power.disable_depth--;
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch b/common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch
deleted file mode 100644
index 8cd267ce..00000000
--- a/common/recipes-kernel/linux/files/0690-drm-amdgpu-Initial-Tonga-Light-up.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From 91d210eb79966cddb5d4d4d01d96d6643287be6b Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 18 Jan 2016 16:52:24 -0500
-Subject: [PATCH 0690/1110] drm/amdgpu: Initial Tonga Light up
-
-Use DM functions for tonga and fiji when DAL is enabled.
-This change combined with a change in DAL allows tonga light up
-with DAL.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   5 +
- drivers/gpu/drm/amd/amdgpu/vi.c            | 156 +++++++++++++++++++++++++++++
- 2 files changed, 161 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 7c27e5a..3de29d9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1398,6 +1398,11 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- 	case CHIP_CARRIZO:
- 		return true;
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case CHIP_TONGA:
-+	case CHIP_FIJI:
-+		return true;
-+#endif
- 	default:
- 		return false;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index c3b5ed6..fc02cad 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1066,6 +1066,142 @@ static const struct amdgpu_ip_block_version cz_ip_blocks_dal[] =
- 	},
- #endif
- };
-+
-+static const struct amdgpu_ip_block_version tonga_ip_blocks_dal[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vi_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gmc_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &tonga_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 7,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 10,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &amdgpu_dm_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gfx_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &sdma_v3_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 5,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &uvd_v5_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vce_v3_0_ip_funcs,
-+	},
-+};
-+
-+static const struct amdgpu_ip_block_version fiji_ip_blocks_dal[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vi_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 8,
-+		.minor = 5,
-+		.rev = 0,
-+		.funcs = &gmc_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &tonga_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 7,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 10,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &amdgpu_dm_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gfx_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &sdma_v3_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 6,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &uvd_v6_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 3,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vce_v3_0_ip_funcs,
-+	},
-+};
- #endif
- 
- int vi_set_ip_blocks(struct amdgpu_device *adev)
-@@ -1076,12 +1212,32 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
- 		break;
- 	case CHIP_FIJI:
-+#if defined(CONFIG_DRM_AMD_DAL)
-+		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+			adev->ip_blocks = fiji_ip_blocks_dal;
-+			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_dal);
-+		} else {
-+			adev->ip_blocks = fiji_ip_blocks;
-+			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
-+		}
-+#else
- 		adev->ip_blocks = fiji_ip_blocks;
- 		adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
-+#endif
- 		break;
- 	case CHIP_TONGA:
-+#if defined(CONFIG_DRM_AMD_DAL)
-+		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+			adev->ip_blocks = tonga_ip_blocks_dal;
-+			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_dal);
-+		} else {
-+			adev->ip_blocks = tonga_ip_blocks;
-+			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
-+		}
-+#else
- 		adev->ip_blocks = tonga_ip_blocks;
- 		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
-+#endif
- 		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0691-drm-amd-dal-Defer-MST-start-to-after-HPD_RX-enabled-.patch b/common/recipes-kernel/linux/files/0691-drm-amd-dal-Defer-MST-start-to-after-HPD_RX-enabled-.patch
deleted file mode 100644
index 7e769f78..00000000
--- a/common/recipes-kernel/linux/files/0691-drm-amd-dal-Defer-MST-start-to-after-HPD_RX-enabled-.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From 067bb023f9fef32a30c1ca1974a38f97ab4ea338 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 13 Jan 2016 14:49:57 -0500
-Subject: [PATCH 0691/1110] drm/amd/dal: Defer MST start to after HPD_RX
- enabled on boot.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 13 +++++---
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 37 +++++++++++++++++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  9 +++---
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  3 +-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |  3 +-
- 5 files changed, 51 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index ff9b5c1..855f9f9 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -431,18 +431,23 @@ void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- 
- bool dc_helpers_dp_mst_start_top_mgr(
- 		struct dc_context *ctx,
--		const struct dc_link *link)
-+		const struct dc_link *link,
-+		bool boot)
- {
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- 
-+	if (boot) {
-+		DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
-+					aconnector, aconnector->base.base.id);
-+		return true;
-+	}
-+
- 	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
- 			aconnector, aconnector->base.base.id);
- 
--	drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
--
--	return true;
-+	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
- }
- 
- void dc_helpers_dp_mst_stop_top_mgr(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index cee507c..0f281b6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -461,7 +461,7 @@ static void detect_on_all_dc_links(struct amdgpu_display_manager *dm)
- 
- 	for (i = 0; i < caps.max_links; i++) {
- 		dc_link = dc_get_link_at_index(dm->dc, i);
--		dc_link_detect(dc_link);
-+		dc_link_detect(dc_link, false);
- 	}
- }
- 
-@@ -612,6 +612,31 @@ static int dm_sw_fini(void *handle)
- 	return 0;
- }
- 
-+
-+static void detect_link_for_all_connectors(struct drm_device *dev)
-+{
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector *connector;
-+
-+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-+
-+	drm_for_each_connector(connector, dev) {
-+		   aconnector = to_amdgpu_connector(connector);
-+		   if (aconnector->dc_link->type == dc_connection_mst_branch) {
-+			   DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
-+						aconnector, aconnector->base.base.id);
-+
-+				if (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) < 0) {
-+					DRM_ERROR("DM_MST: Failed to start MST\n");
-+					((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
-+				}
-+		   }
-+	}
-+
-+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
-+}
-+
-+
- static int dm_hw_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -620,6 +645,10 @@ static int dm_hw_init(void *handle)
- 
- 	amdgpu_dm_hpd_init(adev);
- 
-+	detect_link_for_all_connectors(adev->ddev);
-+
-+
-+
- 	return 0;
- }
- 
-@@ -765,7 +794,7 @@ static void handle_hpd_irq(void *param)
- 	/* In case of failure or MST no need to update connector status or notify the OS
- 	 * since (for MST case) MST does this in it's own context.
- 	 */
--	if (dc_link_detect(aconnector->dc_link)) {
-+	if (dc_link_detect(aconnector->dc_link, false)) {
- 		amdgpu_dm_update_connector_after_detect(aconnector);
- 		drm_kms_helper_hotplug_event(dev);
- 	}
-@@ -781,7 +810,7 @@ static void handle_hpd_rx_irq(void *param)
- 	if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) &&
- 			!is_mst_root_connector) {
- 		/* Downstream Port status changed. */
--		if (dc_link_detect(aconnector->dc_link)) {
-+		if (dc_link_detect(aconnector->dc_link, false)) {
- 			amdgpu_dm_update_connector_after_detect(aconnector);
- 			drm_kms_helper_hotplug_event(dev);
- 		}
-@@ -1057,7 +1086,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 			goto fail_free_connector;
- 		}
- 
--		if (dc_link_detect(dc_get_link_at_index(dm->dc, i)))
-+		if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
- 			amdgpu_dm_update_connector_after_detect(
- 				aconnector);
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index a994a4c..b034c2f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -469,7 +469,8 @@ static void detect_dp(
- 	struct core_link *link,
- 	struct display_sink_capability *sink_caps,
- 	bool *converter_disable_audio,
--	union audio_support *audio_support)
-+	union audio_support *audio_support,
-+	bool boot)
- {
- 	sink_caps->signal = link_detect_sink(link);
- 	sink_caps->transaction_type =
-@@ -525,7 +526,7 @@ static void detect_dp(
- 
- 			if (dc_helpers_dp_mst_start_top_mgr(
- 				link->ctx,
--				&link->public)) {
-+				&link->public, boot)) {
- 				link->public.type = dc_connection_mst_branch;
- 			} else {
- 				/* MST not supported */
-@@ -540,7 +541,7 @@ static void detect_dp(
- 	}
- }
- 
--bool dc_link_detect(const struct dc_link *dc_link)
-+bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- {
- 	struct core_link *link = DC_LINK_TO_LINK(dc_link);
- 	struct dc_sink_init_data sink_init_data = { 0 };
-@@ -605,7 +606,7 @@ bool dc_link_detect(const struct dc_link *dc_link)
- 				link,
- 				&sink_caps,
- 				&converter_disable_audio,
--				&audio_support);
-+				&audio_support, boot);
- 
- 			if (link->public.type == dc_connection_mst_branch)
- 				return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index a2f26cb..f86ddb0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -297,11 +297,12 @@ const struct graphics_object_id dc_get_link_id_at_index(
- bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level);
- 
- /* Request DC to detect if there is a Panel connected.
-+ * boot - If this call is during initial boot.
-  * Return false for any type of detection failure or MST detection
-  * true otherwise. True meaning further action is required (status update
-  * and OS notification).
-  */
--bool dc_link_detect(const struct dc_link *dc_link);
-+bool dc_link_detect(const struct dc_link *dc_link, bool boot);
- 
- /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
-  * Return:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index b4c338a..7a14300 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -67,7 +67,8 @@ void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(
- 
- bool dc_helpers_dp_mst_start_top_mgr(
- 		struct dc_context *ctx,
--		const struct dc_link *link);
-+		const struct dc_link *link,
-+		bool boot);
- 
- void dc_helpers_dp_mst_stop_top_mgr(
- 		struct dc_context *ctx,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0692-drm-amd-dal-Define-interface-for-External-VBIOS-part.patch b/common/recipes-kernel/linux/files/0692-drm-amd-dal-Define-interface-for-External-VBIOS-part.patch
deleted file mode 100644
index 315c116c..00000000
--- a/common/recipes-kernel/linux/files/0692-drm-amd-dal-Define-interface-for-External-VBIOS-part.patch
+++ /dev/null
@@ -1,3301 +0,0 @@
-From 777022b361d791813c9e399bd7d7b1e3efe28232 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Tue, 12 Jan 2016 12:01:10 -0500
-Subject: [PATCH 0692/1110] drm/amd/dal: Define interface for External VBIOS -
- part 2.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   | 140 ++--
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h   |   5 +-
- .../drm/amd/dal/dc/adapter/wireless_data_source.c  |   9 +-
- .../drm/amd/dal/dc/adapter/wireless_data_source.h  |   4 +-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 807 ++++++++++++++-------
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |   1 -
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   4 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   5 +-
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         | 248 ++++++-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |   2 +
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  51 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |  59 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  |   7 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |   7 +-
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c |   2 +-
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h |   4 +-
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c      |   7 +-
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h      |   2 +-
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |   4 +-
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.c    |   6 +-
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.c    |   4 +-
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c  |  11 +-
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c  |   7 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h    |   4 +-
- .../amd/dal/include/adapter_service_interface.h    |   3 +-
- .../drm/amd/dal/include/adapter_service_types.h    |   1 +
- .../drm/amd/dal/include/bios_parser_interface.h    | 216 +-----
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |  19 +-
- .../drm/amd/dal/include/timing_generator_types.h   |   3 +-
- 32 files changed, 1007 insertions(+), 641 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 6084466..b3b3be7 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -26,15 +26,15 @@
- 
- #include "dal_services.h"
- 
-+#include "dc_bios_types.h"
-+
- #include "include/adapter_service_interface.h"
- #include "include/i2caux_interface.h"
- #include "include/asic_capability_types.h"
--#include "include/bios_parser_interface.h"
- #include "include/gpio_service_interface.h"
- #include "include/asic_capability_interface.h"
- #include "include/logger_interface.h"
- 
--#include "dc_bios_types.h"
- #include "adapter_service.h"
- #include "hw_ctx_adapter_service.h"
- #include "wireless_data_source.h"
-@@ -233,10 +233,8 @@ static void initialize_backlight_caps(
- 			return;
- 	}
- 
--	if (dal_bios_parser_get_firmware_info
--			(as->bios_parser, &fw_info)	!= BP_RESULT_OK ||
--		dal_bios_parser_get_embedded_panel_info
--			(as->bios_parser, &panel_info) != BP_RESULT_OK)
-+	if (as->dcb->funcs->get_firmware_info(as->dcb, &fw_info) != BP_RESULT_OK ||
-+		as->dcb->funcs->get_embedded_panel_info(as->dcb, &panel_info) != BP_RESULT_OK)
- 		return;
- 
- 	params.data = &caps;
-@@ -553,7 +551,7 @@ static bool get_hpd_info(struct adapter_service *as,
- 	struct graphics_object_hpd_info *info)
- {
- 	return BP_RESULT_OK ==
--		dal_bios_parser_get_hpd_info(as->bios_parser, id, info);
-+		as->dcb->funcs->get_hpd_info(as->dcb, id, info);
- }
- 
- /*
-@@ -687,10 +685,10 @@ static void adapter_service_destruct(
- {
- 	dal_adapter_service_destroy_hw_ctx(&as->hw_ctx);
- 	dal_i2caux_destroy(&as->i2caux);
--	dal_bios_parser_destroy(&as->bios_parser);
- 	dal_gpio_service_destroy(&as->gpio_service);
- 	dal_asic_capability_destroy(&as->asic_cap);
--	dal_bios_parser_destroy_integrated_info(as->ctx, &as->integrated_info);
-+	as->dcb->funcs->destroy_integrated_info(as->dcb, &as->integrated_info);
-+	dal_bios_parser_destroy(&as->dcb);
- }
- 
- /*
-@@ -736,18 +734,16 @@ static bool adapter_service_construct(
- 		goto failed_to_generate_features;
- 	}
- 
--	if (init_data->vbios_override) {
--		/* TODO: remove the typecast */
--		as->bios_parser = (struct bios_parser *)init_data->vbios_override;
--	} else {
-+	if (init_data->vbios_override)
-+		as->dcb = init_data->vbios_override;
-+	else {
- 		/* Create BIOS parser */
- 		init_data->bp_init_data.ctx = init_data->ctx;
- 
--		as->bios_parser =
--			dal_bios_parser_create(&init_data->bp_init_data, as);
-+		as->dcb = dal_bios_parser_create(&init_data->bp_init_data, as);
- 	}
- 
--	if (!as->bios_parser) {
-+	if (!as->dcb) {
- 		ASSERT_CRITICAL(false);
- 		goto failed_to_create_bios_parser;
- 	}
-@@ -784,10 +780,10 @@ static bool adapter_service_construct(
- 	/* Avoid wireless encoder creation in upstream branch. */
- 
- 	/* Integrated info is not provided on discrete ASIC. NULL is allowed */
--	as->integrated_info = dal_bios_parser_create_integrated_info(
--			as->bios_parser);
-+	as->integrated_info = as->dcb->funcs->create_integrated_info(
-+			as->dcb);
- 
--	dal_bios_parser_post_init(as->bios_parser);
-+	as->dcb->funcs->post_init(as->dcb);
- 
- 	/* Generate backlight translation table and initializes
- 			  other brightness properties */
-@@ -809,7 +805,7 @@ failed_to_create_i2caux:
- 	dal_gpio_service_destroy(&as->gpio_service);
- 
- failed_to_create_gpio_service:
--	dal_bios_parser_destroy(&as->bios_parser);
-+	dal_bios_parser_destroy(&as->dcb);
- 
- failed_to_create_bios_parser:
- 	dal_asic_capability_destroy(&as->asic_cap);
-@@ -926,8 +922,7 @@ uint8_t dal_adapter_service_get_connectors_num(
- 	uint8_t wireless_connectors_num = 0;
- 	struct dc_bios *dcb;
- 
--	/* TODO: remove type cast */
--	dcb = (struct dc_bios*)dal_adapter_service_get_bios_parser(as);
-+	dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	vbios_connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
-@@ -964,7 +959,7 @@ uint32_t dal_adapter_service_get_src_num(
- 	if (is_wireless_object(id))
- 		return wireless_get_srcs_num(as, id);
- 	else
--		return dal_bios_parser_get_src_number(as->bios_parser, id);
-+		return as->dcb->funcs->get_src_number(as->dcb, id);
- }
- 
- /**
-@@ -989,8 +984,8 @@ struct graphics_object_id dal_adapter_service_get_src_obj(
- 		src_object_id = wireless_get_src_obj_id(as, id, index);
- 	else {
- 		if (BP_RESULT_OK !=
--			dal_bios_parser_get_src_obj(
--				as->bios_parser, id, index, &src_object_id))
-+			as->dcb->funcs->get_src_obj(
-+				as->dcb, id, index, &src_object_id))
- 			src_object_id =
- 				dal_graphics_object_id_init(
- 					0,
-@@ -1017,8 +1012,7 @@ struct graphics_object_id dal_adapter_service_get_connector_obj_id(
- 	struct dc_bios *dcb;
- 	uint8_t bios_connectors_num;
- 
--	/* TODO: remove type cast */
--	dcb = (struct dc_bios*)dal_adapter_service_get_bios_parser(as);
-+	dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	bios_connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
-@@ -1027,8 +1021,8 @@ struct graphics_object_id dal_adapter_service_get_connector_obj_id(
- 				as,
- 				connector_index);
- 	else
--		return dal_bios_parser_get_connector_id(
--				as->bios_parser,
-+		return as->dcb->funcs->get_connector_id(
-+				as->dcb,
- 				connector_index);
- }
- 
-@@ -1038,7 +1032,7 @@ bool dal_adapter_service_get_device_tag(
- 		uint32_t device_tag_index,
- 		struct connector_device_tag_info *info)
- {
--	if (BP_RESULT_OK == dal_bios_parser_get_device_tag(as->bios_parser,
-+	if (BP_RESULT_OK == as->dcb->funcs->get_device_tag(as->dcb,
- 			connector_object_id, device_tag_index, info))
- 		return true;
- 	else
-@@ -1049,7 +1043,7 @@ bool dal_adapter_service_get_device_tag(
- bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
- 		struct device_id id)
- {
--	return dal_bios_parser_is_device_id_supported(as->bios_parser, id);
-+	return as->dcb->funcs->is_device_id_supported(as->dcb, id);
- }
- 
- bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as)
-@@ -1092,7 +1086,7 @@ uint8_t dal_adapter_service_get_clock_sources_num(
- 	 * as a clock source for DP
- 	 */
- 	enum bp_result bp_result =
--			dal_bios_parser_get_firmware_info(as->bios_parser,
-+			as->dcb->funcs->get_firmware_info(as->dcb,
- 					&fw_info);
- 
- 	if (BP_RESULT_OK == bp_result &&
-@@ -1211,7 +1205,7 @@ bool dal_adapter_service_get_i2c_info(
- 	}
- 
- 	return BP_RESULT_OK ==
--		dal_bios_parser_get_i2c_info(as->bios_parser, id, i2c_info);
-+		as->dcb->funcs->get_i2c_info(as->dcb, id, i2c_info);
- }
- 
- /*
-@@ -1269,7 +1263,7 @@ struct irq *dal_adapter_service_obtain_hpd_irq(
- 	if (!get_hpd_info(as, id, &hpd_info))
- 		return NULL;
- 
--	bp_result = dal_bios_parser_get_gpio_pin_info(as->bios_parser,
-+	bp_result = as->dcb->funcs->get_gpio_pin_info(as->dcb,
- 		hpd_info.hpd_int_gpio_uid, &pin_info);
- 
- 	if (bp_result != BP_RESULT_OK) {
-@@ -1304,7 +1298,7 @@ uint32_t dal_adapter_service_get_ss_info_num(
- 	struct adapter_service *as,
- 	enum as_signal_type signal)
- {
--	return dal_bios_parser_get_ss_entry_number(as->bios_parser, signal);
-+	return as->dcb->funcs->get_ss_entry_number(as->dcb, signal);
- }
- 
- /*
-@@ -1319,8 +1313,8 @@ bool dal_adapter_service_get_ss_info(
- 	struct spread_spectrum_info *info)
- {
- 	enum bp_result bp_result =
--		dal_bios_parser_get_spread_spectrum_info(
--			as->bios_parser, signal, idx, info);
-+		as->dcb->funcs->get_spread_spectrum_info(
-+			as->dcb, signal, idx, info);
- 
- 	return BP_RESULT_OK == bp_result;
- }
-@@ -1510,22 +1504,20 @@ struct gpio *dal_adapter_service_obtain_stereo_gpio(
- 	result.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
- 
- 	/* Case 1 : Workstation stereo */
--	if (result.bits.WORKSTATION_STEREO)
-+	if (result.bits.WORKSTATION_STEREO) {
- 		/* "active low" <--> "default 3d right eye polarity" = false */
--		return dal_gpio_service_create_gpio_ex(
--			as->gpio_service, GPIO_ID_GENERIC, GPIO_GENERIC_A,
--			GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW);
-+		return dal_gpio_service_create_gpio_ex(as->gpio_service,
-+				GPIO_ID_GENERIC, GPIO_GENERIC_A,
-+				GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW);
- 	/* Case 2 : runtime parameter override for sideband stereo */
--	else if (have_param_stereo_gpio) {
-+	} else if (have_param_stereo_gpio) {
- 		/* TODO implement */
- 		return NULL;
--	/* Case 3 : VBIOS gives us GPIO for sideband stereo */
-+		/* Case 3 : VBIOS gives us GPIO for sideband stereo */
- 	} else {
- 		const struct graphics_object_id id =
--			dal_graphics_object_id_init(
--				GENERIC_ID_STEREO,
--				ENUM_ID_1,
--				OBJECT_TYPE_GENERIC);
-+				dal_graphics_object_id_init(GENERIC_ID_STEREO,
-+						ENUM_ID_1, OBJECT_TYPE_GENERIC);
- 
- 		struct bp_gpio_cntl_info cntl_info;
- 		struct gpio_pin_info pin_info;
-@@ -1533,18 +1525,21 @@ struct gpio *dal_adapter_service_obtain_stereo_gpio(
- 		/* Get GPIO record for this object.
- 		 * Stereo GPIO record should have exactly one entry
- 		 * where active state defines stereosync polarity */
--		if (1 != dal_bios_parser_get_gpio_record(
--			as->bios_parser, id, &cntl_info, 1)) {
-+		if (1 != as->dcb->funcs->get_gpio_record(
-+						as->dcb, id, &cntl_info,
-+						1)) {
- 			return NULL;
--		} else if (BP_RESULT_OK != dal_bios_parser_get_gpio_pin_info(
--			as->bios_parser, cntl_info.id, &pin_info)) {
-+		} else if (BP_RESULT_OK
-+				!= as->dcb->funcs->get_gpio_pin_info(
-+						as->dcb, cntl_info.id,
-+						&pin_info)) {
- 			/*ASSERT_CRITICAL(false);*/
- 			return NULL;
--		} else
--			return dal_gpio_service_create_gpio_ex(
--				as->gpio_service,
--				pin_info.offset, pin_info.mask,
--				cntl_info.state);
-+		} else {
-+			return dal_gpio_service_create_gpio_ex(as->gpio_service,
-+					pin_info.offset, pin_info.mask,
-+					cntl_info.state);
-+		}
- 	}
- }
- 
-@@ -1569,7 +1564,7 @@ bool dal_adapter_service_get_firmware_info(
- 	struct adapter_service *as,
- 	struct firmware_info *info)
- {
--	return dal_bios_parser_get_firmware_info(as->bios_parser, info) ==
-+	return as->dcb->funcs->get_firmware_info(as->dcb, info) ==
- 		BP_RESULT_OK;
- }
- 
-@@ -1666,13 +1661,10 @@ uint32_t dal_adapter_service_get_memory_type_multiplier(
-  *
-  * Get BIOS parser handler
-  */
--/* TODO: change return type to 'dc_bios'. */
--struct bios_parser *dal_adapter_service_get_bios_parser(
-+struct dc_bios *dal_adapter_service_get_bios_parser(
- 	struct adapter_service *as)
- {
--	/* TODO: conditionally return 'override' or 'real'.
--	 * Works for now because 'base' is first member of 'bios parser' */
--	return as->bios_parser;
-+	return as->dcb;
- }
- 
- /*
-@@ -1764,8 +1756,7 @@ bool dal_adapter_service_get_embedded_panel_info(
- 		/*TODO: add DALASSERT_MSG here*/
- 		return false;
- 
--	result = dal_bios_parser_get_embedded_panel_info(
--		as->bios_parser, info);
-+	result = as->dcb->funcs->get_embedded_panel_info(as->dcb, info);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1781,8 +1772,8 @@ bool dal_adapter_service_enum_embedded_panel_patch_mode(
- 		/*TODO: add DALASSERT_MSG here*/
- 		return false;
- 
--	result = dal_bios_parser_enum_embedded_panel_patch_mode(
--		as->bios_parser, index, mode);
-+	result = as->dcb->funcs->enum_embedded_panel_patch_mode(
-+		as->dcb, index, mode);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1793,9 +1784,8 @@ bool dal_adapter_service_get_faked_edid_len(
- {
- 	enum bp_result result;
- 
--	result = dal_bios_parser_get_faked_edid_len(
--		as->bios_parser,
--		len);
-+	result = as->dcb->funcs->get_faked_edid_len(as->dcb, len);
-+
- 	return result == BP_RESULT_OK;
- }
- 
-@@ -1806,8 +1796,8 @@ bool dal_adapter_service_get_faked_edid_buf(
- {
- 	enum bp_result result;
- 
--	result = dal_bios_parser_get_faked_edid_buf(
--		as->bios_parser,
-+	result = as->dcb->funcs->get_faked_edid_buf(
-+		as->dcb,
- 		buf,
- 		len);
- 	return result == BP_RESULT_OK;
-@@ -1896,7 +1886,7 @@ bool dal_adapter_service_should_optimize(
-  */
- bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as)
- {
--	return dal_bios_parser_is_accelerated_mode(as->bios_parser);
-+	return as->dcb->funcs->is_accelerated_mode(as->dcb);
- }
- 
- struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
-@@ -1946,7 +1936,7 @@ bool dal_adapter_service_is_lid_open(struct adapter_service *as)
- 		return is_lid_open;
- 
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
--	return dal_bios_parser_is_lid_open(as->bios_parser);
-+	return as->dcb->funcs->is_lid_open(as->dcb);
- #else
- 	return false;
- #endif
-@@ -2033,8 +2023,8 @@ bool dal_adapter_service_get_encoder_cap_info(
- 	 * - dpHbr2Cap: indicates supported/not supported by HW Encoder
- 	 * - dpHbr2En : indicates DP spec compliant/not compliant
- 	 */
--	result = dal_bios_parser_get_encoder_cap_info(
--			as->bios_parser,
-+	result = as->dcb->funcs->get_encoder_cap_info(
-+			as->dcb,
- 			id,
- 			&bp_cap_info);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-index dd5bb00..5bb4446 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -27,6 +27,7 @@
- #define __DAL_ADAPTER_SERVICE_H__
- 
- /* Include */
-+#include "dc_bios_types.h"
- #include "include/adapter_service_interface.h"
- #include "wireless_data_source.h"
- 
-@@ -35,13 +36,13 @@
-  */
- struct gpio_service;
- struct asic_cap;
--struct dc_bios;
-+
- 
- /* Adapter service */
- struct adapter_service {
- 	struct dc_context *ctx;
- 	struct asic_capability *asic_cap;
--	struct bios_parser *bios_parser;/* TODO: remove it. replace by struct dc_bios *dcb; */
-+	struct dc_bios *dcb;
- 	struct gpio_service *gpio_service;
- 	struct i2caux *i2caux;
- 	struct wireless_data wireless_data;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-index dcb885d..0249829 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-@@ -32,12 +32,12 @@
- 
- /*construct wireless data*/
- bool wireless_data_init(struct wireless_data *data,
--		struct bios_parser *bp,
-+		struct dc_bios *dcb,
- 		struct wireless_init_data *init_data)
- {
- 	struct firmware_info info;
- 
--	if (data == NULL || bp == NULL || init_data == NULL) {
-+	if (data == NULL || dcb == NULL || init_data == NULL) {
- 		ASSERT_CRITICAL(false);
- 		return false;
- 	}
-@@ -66,10 +66,9 @@ bool wireless_data_init(struct wireless_data *data,
- 		 * Check if SBIOS sets remote display enable, exposed
- 		 * through VBIOS. This is only valid for APU, not dGPU
- 		 */
--		dal_bios_parser_get_firmware_info(bp, &info);
-+		dcb->funcs->get_firmware_info(dcb, &info);
- 
--		if ((REMOTE_DISPLAY_ENABLE ==
--			info.remote_display_config) &&
-+		if ((REMOTE_DISPLAY_ENABLE == info.remote_display_config) &&
- 				init_data->fusion) {
- 			data->wireless_enable = true;
- 			data->wireless_disp_path_enable = true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-index 54b140a..b64089e 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-@@ -33,7 +33,7 @@
-  * Forward declaration
-  */
- struct adapter_service;
--struct bios_parser;
-+struct dc_bios;
- 
- /* Wireless data init structure */
- struct wireless_init_data {
-@@ -55,7 +55,7 @@ struct wireless_data {
- /*construct wireless data*/
- bool wireless_data_init(
- 	struct wireless_data *data,
--	struct bios_parser *bp,
-+	struct dc_bios *dcb,
- 	struct wireless_init_data *init_data);
- 
- uint8_t wireless_get_clocks_num(
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 3329322..3ca165b 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -40,6 +40,7 @@
- #endif
- #include "command_table_helper.h"
- #include "bios_parser.h"
-+#include "bios_parser_interface.h"
- 
- #define THREE_PERCENT_OF_10000 300
- 
-@@ -100,101 +101,21 @@ static void process_ext_display_connection_info(struct bios_parser *bp);
- #define BIOS_IMAGE_SIZE_UNIT 512
- 
- /*****************************************************************************/
--static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb);
--
--const struct dc_vbios_funcs vbios_funcs = {
--	.get_connectors_number = bios_parser_get_connectors_number
--};
--
- static bool bios_parser_construct(
- 	struct bios_parser *bp,
- 	struct bp_init_data *init,
--	struct adapter_service *as)
--{
--	uint16_t *rom_header_offset = NULL;
--	ATOM_ROM_HEADER *rom_header = NULL;
--	ATOM_OBJECT_HEADER *object_info_tbl;
--	enum dce_version dce_version;
--
--	if (!as)
--		return false;
-+	struct adapter_service *as);
- 
--	if (!init)
--		return false;
-+static uint8_t bios_parser_get_connectors_number(
-+	struct dc_bios *dcb);
- 
--	if (!init->bios)
--		return false;
--
--	bp->base.funcs = &vbios_funcs;
--
--	dce_version = dal_adapter_service_get_dce_version(as);
--	bp->ctx = init->ctx;
--	bp->as = as;
--	bp->bios = init->bios;
--	bp->bios_size = bp->bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT;
--	bp->bios_local_image = NULL;
--	bp->lcd_scale = LCD_SCALE_UNKNOWN;
--
--	rom_header_offset =
--	GET_IMAGE(uint16_t, OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
--
--	if (!rom_header_offset)
--		return false;
--
--	rom_header = GET_IMAGE(ATOM_ROM_HEADER, *rom_header_offset);
--
--	if (!rom_header)
--		return false;
--
--	bp->master_data_tbl =
--	GET_IMAGE(ATOM_MASTER_DATA_TABLE,
--		rom_header->usMasterDataTableOffset);
--
--	if (!bp->master_data_tbl)
--		return false;
--
--	bp->object_info_tbl_offset = DATA_TABLES(Object_Header);
--
--	if (!bp->object_info_tbl_offset)
--		return false;
--
--	object_info_tbl =
--	GET_IMAGE(ATOM_OBJECT_HEADER, bp->object_info_tbl_offset);
--
--	if (!object_info_tbl)
--		return false;
--
--	get_atom_data_table_revision(&object_info_tbl->sHeader,
--		&bp->object_info_tbl.revision);
--
--	if (bp->object_info_tbl.revision.major == 1
--		&& bp->object_info_tbl.revision.minor >= 3) {
--		ATOM_OBJECT_HEADER_V3 *tbl_v3;
--
--		tbl_v3 = GET_IMAGE(ATOM_OBJECT_HEADER_V3,
--			bp->object_info_tbl_offset);
--		if (!tbl_v3)
--			return false;
--
--		bp->object_info_tbl.v1_3 = tbl_v3;
--	} else if (bp->object_info_tbl.revision.major == 1
--		&& bp->object_info_tbl.revision.minor >= 1)
--		bp->object_info_tbl.v1_1 = object_info_tbl;
--	else
--		return false;
--
--#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
--	bp->vbios_helper_data.active = 0;
--	bp->vbios_helper_data.requested = 0;
--	dal_bios_parser_init_bios_helper(bp, dce_version);
--#endif
--	dal_bios_parser_init_cmd_tbl(bp);
--	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
-+static enum bp_result bios_parser_get_embedded_panel_info(
-+	struct dc_bios *dcb,
-+	struct embedded_panel_info *info);
- 
--	return true;
--}
-+/*****************************************************************************/
- 
--struct bios_parser *dal_bios_parser_create(
-+struct dc_bios *dal_bios_parser_create(
- 	struct bp_init_data *init, struct adapter_service *as)
- {
- 	struct bios_parser *bp = NULL;
-@@ -204,7 +125,7 @@ struct bios_parser *dal_bios_parser_create(
- 		return NULL;
- 
- 	if (bios_parser_construct(bp, init, as))
--		return bp;
-+		return &bp->base;
- 
- 	dc_service_free(init->ctx, bp);
- 	BREAK_TO_DEBUGGER();
-@@ -217,29 +138,35 @@ static void destruct(struct bios_parser *bp)
- 		dc_service_free(bp->ctx, bp->bios_local_image);
- }
- 
--void dal_bios_parser_destroy(struct bios_parser **bp)
-+void dal_bios_parser_destroy(struct dc_bios **dcb)
- {
--	if (!bp || !*bp) {
-+	struct bios_parser *bp = BP_FROM_DCB(*dcb);
-+
-+	if (!bp) {
- 		BREAK_TO_DEBUGGER();
- 		return;
- 	}
- 
--	destruct(*bp);
-+	destruct(bp);
- 
--	dc_service_free((*bp)->ctx, *bp);
--	*bp = NULL;
-+	dc_service_free((bp)->ctx, bp);
-+	*dcb = NULL;
- }
- 
--void dal_bios_parser_power_down(struct bios_parser *bp)
-+static void bios_parser_power_down(struct dc_bios *dcb)
- {
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	dal_bios_parser_set_scratch_lcd_scale(bp, bp->lcd_scale);
- #endif
- }
- 
--void dal_bios_parser_power_up(struct bios_parser *bp)
-+static void bios_parser_power_up(struct dc_bios *dcb)
- {
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (bp->lcd_scale == LCD_SCALE_UNKNOWN)
- 		bp->lcd_scale = dal_bios_parser_get_scratch_lcd_scale(bp);
- #endif
-@@ -259,8 +186,10 @@ static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)
- 		return table->ucNumberOfObjects;
- }
- 
--uint8_t dal_bios_parser_get_encoders_number(struct bios_parser *bp)
-+static uint8_t bios_parser_get_encoders_number(struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	return get_number_of_objects(bp,
- 		le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset));
- }
-@@ -273,9 +202,10 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
- 		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset));
- }
- 
--uint32_t dal_bios_parser_get_oem_ddc_lines_number(struct bios_parser *bp)
-+static uint32_t bios_parser_get_oem_ddc_lines_number(struct dc_bios *dcb)
- {
- 	uint32_t number = 0;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (DATA_TABLES(OemInfo) != 0) {
- 		ATOM_OEM_INFO *info;
-@@ -296,9 +226,11 @@ uint32_t dal_bios_parser_get_oem_ddc_lines_number(struct bios_parser *bp)
- 	return number;
- }
- 
--struct graphics_object_id dal_bios_parser_get_encoder_id(struct bios_parser *bp,
-+static struct graphics_object_id bios_parser_get_encoder_id(
-+	struct dc_bios *dcb,
- 	uint32_t i)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct graphics_object_id object_id = dal_graphics_object_id_init(
- 		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
- 
-@@ -317,10 +249,11 @@ struct graphics_object_id dal_bios_parser_get_encoder_id(struct bios_parser *bp,
- 	return object_id;
- }
- 
--struct graphics_object_id dal_bios_parser_get_connector_id(
--	struct bios_parser *bp,
-+static struct graphics_object_id bios_parser_get_connector_id(
-+	struct dc_bios *dcb,
- 	uint8_t i)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct graphics_object_id object_id = dal_graphics_object_id_init(
- 		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
- 
-@@ -339,12 +272,13 @@ struct graphics_object_id dal_bios_parser_get_connector_id(
- 	return object_id;
- }
- 
--uint32_t dal_bios_parser_get_src_number(struct bios_parser *bp,
-+static uint32_t bios_parser_get_src_number(struct dc_bios *dcb,
- 	struct graphics_object_id id)
- {
- 	uint32_t offset;
- 	uint8_t *number;
- 	ATOM_OBJECT *object;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	object = get_bios_object(bp, id);
- 
-@@ -363,21 +297,23 @@ uint32_t dal_bios_parser_get_src_number(struct bios_parser *bp,
- 	return *number;
- }
- 
--uint32_t dal_bios_parser_get_dst_number(struct bios_parser *bp,
-+static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb,
- 	struct graphics_object_id id)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object = get_bios_object(bp, id);
- 
- 	return get_dst_number_from_object(bp, object);
- }
- 
--enum bp_result dal_bios_parser_get_src_obj(struct bios_parser *bp,
-+static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
- 	struct graphics_object_id object_id, uint32_t index,
- 	struct graphics_object_id *src_object_id)
- {
- 	uint32_t number;
- 	uint16_t *id;
- 	ATOM_OBJECT *object;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!src_object_id)
- 		return BP_RESULT_BADINPUT;
-@@ -399,13 +335,14 @@ enum bp_result dal_bios_parser_get_src_obj(struct bios_parser *bp,
- 	return BP_RESULT_OK;
- }
- 
--enum bp_result dal_bios_parser_get_dst_obj(struct bios_parser *bp,
-+static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
- 	struct graphics_object_id object_id, uint32_t index,
- 	struct graphics_object_id *dest_object_id)
- {
- 	uint32_t number;
- 	uint16_t *id;
- 	ATOM_OBJECT *object;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!dest_object_id)
- 		return BP_RESULT_BADINPUT;
-@@ -422,10 +359,11 @@ enum bp_result dal_bios_parser_get_dst_obj(struct bios_parser *bp,
- 	return BP_RESULT_OK;
- }
- 
--enum bp_result dal_bios_parser_get_oem_ddc_info(struct bios_parser *bp,
-+static enum bp_result bios_parser_get_oem_ddc_info(struct dc_bios *dcb,
- 	uint32_t index,
- 	struct graphics_object_i2c_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!info)
- 		return BP_RESULT_BADINPUT;
-@@ -458,7 +396,7 @@ enum bp_result dal_bios_parser_get_oem_ddc_info(struct bios_parser *bp,
- 	return BP_RESULT_NORECORD;
- }
- 
--enum bp_result dal_bios_parser_get_i2c_info(struct bios_parser *bp,
-+static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
- 	struct graphics_object_id id,
- 	struct graphics_object_i2c_info *info)
- {
-@@ -466,6 +404,7 @@ enum bp_result dal_bios_parser_get_i2c_info(struct bios_parser *bp,
- 	ATOM_OBJECT *object;
- 	ATOM_COMMON_RECORD_HEADER *header;
- 	ATOM_I2C_RECORD *record;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!info)
- 		return BP_RESULT_BADINPUT;
-@@ -563,7 +502,28 @@ static enum bp_result get_voltage_ddc_info_v3(uint8_t *i2c_line,
- 	return result;
- }
- 
--enum bp_result dal_bios_parser_get_voltage_ddc_info(struct bios_parser *bp,
-+static enum bp_result bios_parser_get_thermal_ddc_info(
-+	struct dc_bios *dcb,
-+	uint32_t i2c_channel_id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_I2C_ID_CONFIG_ACCESS *config;
-+	ATOM_I2C_RECORD record;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	config = (ATOM_I2C_ID_CONFIG_ACCESS *) &i2c_channel_id;
-+
-+	record.sucI2cId.bfHW_Capable = config->sbfAccess.bfHW_Capable;
-+	record.sucI2cId.bfI2C_LineMux = config->sbfAccess.bfI2C_LineMux;
-+	record.sucI2cId.bfHW_EngineID = config->sbfAccess.bfHW_EngineID;
-+
-+	return get_gpio_i2c_info(bp, &record, info);
-+}
-+
-+static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
- 	uint32_t index,
- 	struct graphics_object_i2c_info *info)
- {
-@@ -572,6 +532,7 @@ enum bp_result dal_bios_parser_get_voltage_ddc_info(struct bios_parser *bp,
- 	uint8_t *voltage_info_address;
- 	ATOM_COMMON_TABLE_HEADER *header;
- 	struct atom_data_revision revision = {0};
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!DATA_TABLES(VoltageObjectInfo))
- 		return result;
-@@ -599,34 +560,14 @@ enum bp_result dal_bios_parser_get_voltage_ddc_info(struct bios_parser *bp,
- 	}
- 
- 	if (result == BP_RESULT_OK)
--		result = dal_bios_parser_get_thermal_ddc_info(bp,
-+		result = bios_parser_get_thermal_ddc_info(dcb,
- 			i2c_line, info);
- 
- 
- 	return result;
- }
- 
--enum bp_result dal_bios_parser_get_thermal_ddc_info(
--	struct bios_parser *bp,
--	uint32_t i2c_channel_id,
--	struct graphics_object_i2c_info *info)
--{
--	ATOM_I2C_ID_CONFIG_ACCESS *config;
--	ATOM_I2C_RECORD record;
--
--	if (!info)
--		return BP_RESULT_BADINPUT;
--
--	config = (ATOM_I2C_ID_CONFIG_ACCESS *) &i2c_channel_id;
--
--	record.sucI2cId.bfHW_Capable = config->sbfAccess.bfHW_Capable;
--	record.sucI2cId.bfI2C_LineMux = config->sbfAccess.bfI2C_LineMux;
--	record.sucI2cId.bfHW_EngineID = config->sbfAccess.bfHW_EngineID;
--
--	return get_gpio_i2c_info(bp, &record, info);
--}
--
--enum bp_result dal_bios_parser_get_ddc_info_for_i2c_line(struct bios_parser *bp,
-+enum bp_result bios_parser_get_ddc_info_for_i2c_line(struct bios_parser *bp,
- 	uint8_t i2c_line, struct graphics_object_i2c_info *info)
- {
- 	uint32_t offset;
-@@ -690,10 +631,11 @@ enum bp_result dal_bios_parser_get_ddc_info_for_i2c_line(struct bios_parser *bp,
- 	return BP_RESULT_NORECORD;
- }
- 
--enum bp_result dal_bios_parser_get_hpd_info(struct bios_parser *bp,
-+static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb,
- 	struct graphics_object_id id,
- 	struct graphics_object_hpd_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object;
- 	ATOM_HPD_INT_RECORD *record = NULL;
- 
-@@ -716,12 +658,13 @@ enum bp_result dal_bios_parser_get_hpd_info(struct bios_parser *bp,
- 	return BP_RESULT_NORECORD;
- }
- 
--uint32_t dal_bios_parser_get_gpio_record(
--	struct bios_parser *bp,
-+static uint32_t bios_parser_get_gpio_record(
-+	struct dc_bios *dcb,
- 	struct graphics_object_id id,
- 	struct bp_gpio_cntl_info *gpio_record,
- 	uint32_t record_size)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_COMMON_RECORD_HEADER *header = NULL;
- 	ATOM_OBJECT_GPIO_CNTL_RECORD *record = NULL;
- 	ATOM_OBJECT *object = get_bios_object(bp, id);
-@@ -789,7 +732,7 @@ uint32_t dal_bios_parser_get_gpio_record(
- 	return pins_number;
- }
- 
--enum bp_result dal_bios_parser_get_device_tag_record(
-+enum bp_result bios_parser_get_device_tag_record(
- 	struct bios_parser *bp,
- 	ATOM_OBJECT *object,
- 	ATOM_CONNECTOR_DEVICE_TAG_RECORD **record)
-@@ -826,12 +769,13 @@ enum bp_result dal_bios_parser_get_device_tag_record(
- 	return BP_RESULT_NORECORD;
- }
- 
--enum bp_result dal_bios_parser_get_device_tag(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_device_tag(
-+	struct dc_bios *dcb,
- 	struct graphics_object_id connector_object_id,
- 	uint32_t device_tag_index,
- 	struct connector_device_tag_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object;
- 	ATOM_CONNECTOR_DEVICE_TAG_RECORD *record = NULL;
- 	ATOM_CONNECTOR_DEVICE_TAG *device_tag;
-@@ -847,7 +791,7 @@ enum bp_result dal_bios_parser_get_device_tag(
- 		return BP_RESULT_BADINPUT;
- 	}
- 
--	if (dal_bios_parser_get_device_tag_record(bp, object, &record)
-+	if (bios_parser_get_device_tag_record(bp, object, &record)
- 		!= BP_RESULT_OK)
- 		return BP_RESULT_NORECORD;
- 
-@@ -873,10 +817,11 @@ static enum bp_result get_firmware_info_v2_2(
- 	struct bios_parser *bp,
- 	struct firmware_info *info);
- 
--enum bp_result dal_bios_parser_get_firmware_info(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_firmware_info(
-+	struct dc_bios *dcb,
- 	struct firmware_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	enum bp_result result = BP_RESULT_BADBIOSTABLE;
- 	ATOM_COMMON_TABLE_HEADER *header;
- 	struct atom_data_revision revision;
-@@ -1223,61 +1168,73 @@ static enum bp_result get_ss_info_v3_1(
- 	return BP_RESULT_NORECORD;
- }
- 
--enum bp_result dal_bios_parser_transmitter_control(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_transmitter_control(
-+	struct dc_bios *dcb,
- 	struct bp_transmitter_control *cntl)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.transmitter_control)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.transmitter_control(bp, cntl);
- }
- 
--enum bp_result dal_bios_parser_encoder_control(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_encoder_control(
-+	struct dc_bios *dcb,
- 	struct bp_encoder_control *cntl)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.dig_encoder_control)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
- }
- 
--enum bp_result dal_bios_parser_adjust_pixel_clock(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_adjust_pixel_clock(
-+	struct dc_bios *dcb,
- 	struct bp_adjust_pixel_clock_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.adjust_display_pll)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.adjust_display_pll(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_set_pixel_clock(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_set_pixel_clock(
-+	struct dc_bios *dcb,
- 	struct bp_pixel_clock_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.set_pixel_clock)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_set_dce_clock(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_set_dce_clock(
-+	struct dc_bios *dcb,
- 	struct bp_set_dce_clock_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.set_dce_clock)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.set_dce_clock(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_enable_spread_spectrum_on_ppll(
-+	struct dc_bios *dcb,
- 	struct bp_spread_spectrum_parameters *bp_params,
- 	bool enable)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.enable_spread_spectrum_on_ppll)
- 		return BP_RESULT_FAILURE;
- 
-@@ -1286,20 +1243,23 @@ enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
- 
- }
- 
--enum bp_result dal_bios_parser_program_crtc_timing(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_program_crtc_timing(
-+	struct dc_bios *dcb,
- 	struct bp_hw_crtc_timing_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.set_crtc_timing)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_program_display_engine_pll(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_program_display_engine_pll(
-+	struct dc_bios *dcb,
- 	struct bp_pixel_clock_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!bp->cmd_tbl.program_clock)
- 		return BP_RESULT_FAILURE;
-@@ -1308,12 +1268,14 @@ enum bp_result dal_bios_parser_program_display_engine_pll(
- 
- }
- 
--enum signal_type dal_bios_parser_dac_load_detect(
--	struct bios_parser *bp,
-+static enum signal_type bios_parser_dac_load_detect(
-+	struct dc_bios *dcb,
- 	struct graphics_object_id encoder,
- 	struct graphics_object_id connector,
- 	enum signal_type display_signal)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.dac_load_detection)
- 		return SIGNAL_TYPE_NONE;
- 
-@@ -1321,62 +1283,73 @@ enum signal_type dal_bios_parser_dac_load_detect(
- 		display_signal);
- }
- 
--enum bp_result dal_bios_parser_get_divider_for_target_display_clock(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_divider_for_target_display_clock(
-+	struct dc_bios *dcb,
- 	struct bp_display_clock_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.compute_memore_engine_pll)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.compute_memore_engine_pll(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_dvo_encoder_control(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_dvo_encoder_control(
-+	struct dc_bios *dcb,
- 	struct bp_dvo_encoder_control *cntl)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.dvo_encoder_control)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.dvo_encoder_control(bp, cntl);
- }
- 
--enum bp_result dal_bios_parser_enable_crtc(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_enable_crtc(
-+	struct dc_bios *dcb,
- 	enum controller_id id,
- 	bool enable)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.enable_crtc)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.enable_crtc(bp, id, enable);
- }
- 
--enum bp_result dal_bios_parser_blank_crtc(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_blank_crtc(
-+	struct dc_bios *dcb,
- 	struct bp_blank_crtc_parameters *bp_params,
- 	bool blank)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.blank_crtc)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.blank_crtc(bp, bp_params, blank);
- }
- 
--enum bp_result dal_bios_parser_crtc_source_select(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_crtc_source_select(
-+	struct dc_bios *dcb,
- 	struct bp_crtc_source_select *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.select_crtc_source)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.select_crtc_source(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_set_overscan(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_set_overscan(
-+	struct dc_bios *dcb,
- 	struct bp_hw_crtc_overscan_parameters *bp_params)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	if (!bp->cmd_tbl.set_crtc_overscan)
- 		return BP_RESULT_FAILURE;
-@@ -1384,32 +1357,38 @@ enum bp_result dal_bios_parser_set_overscan(
- 	return bp->cmd_tbl.set_crtc_overscan(bp, bp_params);
- }
- 
--enum bp_result dal_bios_parser_enable_memory_requests(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_enable_memory_requests(
-+	struct dc_bios *dcb,
- 	enum controller_id controller_id,
- 	bool enable)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.enable_crtc_mem_req)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.enable_crtc_mem_req(bp, controller_id, enable);
- }
- 
--enum bp_result dal_bios_parser_external_encoder_control(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_external_encoder_control(
-+	struct dc_bios *dcb,
- 	struct bp_external_encoder_control *cntl)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.external_encoder_control)
- 		return BP_RESULT_FAILURE;
- 
- 	return bp->cmd_tbl.external_encoder_control(bp, cntl);
- }
- 
--enum bp_result dal_bios_parser_enable_disp_power_gating(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_enable_disp_power_gating(
-+	struct dc_bios *dcb,
- 	enum controller_id controller_id,
- 	enum bp_pipe_control_action action)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (!bp->cmd_tbl.enable_disp_power_gating)
- 		return BP_RESULT_FAILURE;
- 
-@@ -1417,21 +1396,24 @@ enum bp_result dal_bios_parser_enable_disp_power_gating(
- 		action);
- }
- 
--bool dal_bios_parser_is_device_id_supported(
--	struct bios_parser *bp,
-+static bool bios_parser_is_device_id_supported(
-+	struct dc_bios *dcb,
- 	struct device_id id)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	uint32_t mask = get_support_mask_for_device_id(id);
- 
- 	return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0;
- }
- 
--enum bp_result dal_bios_parser_crt_control(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_crt_control(
-+	struct dc_bios *dcb,
- 	enum engine_id engine_id,
- 	bool enable,
- 	uint32_t pixel_clock)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	uint8_t standard;
- 
- 	if (!bp->cmd_tbl.dac1_encoder_control &&
-@@ -1568,7 +1550,7 @@ static enum bp_result get_ss_info_from_tbl(
- 	uint32_t id,
- 	struct spread_spectrum_info *ss_info);
- /**
-- * dal_bios_parser_get_spread_spectrum_info
-+ * bios_parser_get_spread_spectrum_info
-  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
-  * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
-  * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1,
-@@ -1580,12 +1562,13 @@ static enum bp_result get_ss_info_from_tbl(
-  * @param [out] ss_info, sprectrum information structure,
-  * @return Bios parser result code
-  */
--enum bp_result dal_bios_parser_get_spread_spectrum_info(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_spread_spectrum_info(
-+	struct dc_bios *dcb,
- 	enum as_signal_type signal,
- 	uint32_t index,
- 	struct spread_spectrum_info *ss_info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	enum bp_result result = BP_RESULT_UNSUPPORTED;
- 	uint32_t clk_id_ss = 0;
- 	ATOM_COMMON_TABLE_HEADER *header;
-@@ -1777,7 +1760,7 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 	{
- 		struct embedded_panel_info panel_info;
- 
--		if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
-+		if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info)
- 				== BP_RESULT_OK)
- 			id_local = panel_info.ss_id;
- 		break;
-@@ -1833,10 +1816,11 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 	struct bios_parser *bp,
- 	struct embedded_panel_info *info);
- 
--enum bp_result dal_bios_parser_get_embedded_panel_info(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_embedded_panel_info(
-+	struct dc_bios *dcb,
- 	struct embedded_panel_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_COMMON_TABLE_HEADER *hdr;
- 
- 	if (!DATA_TABLES(LCD_Info))
-@@ -2111,7 +2095,7 @@ static enum bp_result get_embedded_panel_info_v1_3(
- }
- 
- /**
-- * dal_bios_parser_get_encoder_cap_info
-+ * bios_parser_get_encoder_cap_info
-  *
-  * @brief
-  *  Get encoder capability information of input object id
-@@ -2122,11 +2106,12 @@ static enum bp_result get_embedded_panel_info_v1_3(
-  * @return Bios parser result code
-  *
-  */
--enum bp_result dal_bios_parser_get_encoder_cap_info(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_encoder_cap_info(
-+	struct dc_bios *dcb,
- 	struct graphics_object_id object_id,
- 	struct bp_encoder_cap_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object;
- 	ATOM_ENCODER_CAP_RECORD *record = NULL;
- 
-@@ -2198,7 +2183,7 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- }
- 
- /**
-- * dal_bios_parser_get_din_connector_info
-+ * bios_parser_get_din_connector_info
-  * @brief
-  *   Get GPIO record for the DIN connector, this GPIO tells whether there is a
-  *    CV dumb dongle
-@@ -2209,11 +2194,12 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
-  * @param info             - GPIO record infor
-  * @return Bios parser result code
-  */
--enum bp_result dal_bios_parser_get_din_connector_info(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_din_connector_info(
-+	struct dc_bios *dcb,
- 	struct graphics_object_id id,
- 	struct din_connector_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_COMMON_RECORD_HEADER *header;
- 	ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD *record = NULL;
- 	ATOM_OBJECT *object;
-@@ -2294,10 +2280,11 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
-  * @param[in] signal, ASSignalType to be converted to SSid
-  * @return number of SS Entry that match the signal
-  */
--uint32_t dal_bios_parser_get_ss_entry_number(
--	struct bios_parser *bp,
-+static uint32_t bios_parser_get_ss_entry_number(
-+	struct dc_bios *dcb,
- 	enum as_signal_type signal)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	uint32_t ss_id = 0;
- 	ATOM_COMMON_TABLE_HEADER *header;
- 	struct atom_data_revision revision;
-@@ -2381,7 +2368,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
- 	case ASIC_INTERNAL_SS_ON_LVDS: {
- 		struct embedded_panel_info panel_info;
- 
--		if (dal_bios_parser_get_embedded_panel_info(bp, &panel_info)
-+		if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info)
- 				== BP_RESULT_OK)
- 			id_local = panel_info.ss_id;
- 		break;
-@@ -2544,10 +2531,11 @@ static ATOM_FAKE_EDID_PATCH_RECORD *get_faked_edid_record(
- 	return (ATOM_FAKE_EDID_PATCH_RECORD *)record;
- }
- 
--enum bp_result dal_bios_parser_get_faked_edid_len(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_faked_edid_len(
-+	struct dc_bios *dcb,
- 	uint32_t *len)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
- 
- 	if (!edid_record)
-@@ -2558,11 +2546,12 @@ enum bp_result dal_bios_parser_get_faked_edid_len(
- 	return BP_RESULT_OK;
- }
- 
--enum bp_result dal_bios_parser_get_faked_edid_buf(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_faked_edid_buf(
-+	struct dc_bios *dcb,
- 	uint8_t *buff,
- 	uint32_t len)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
- 	uint32_t edid_size;
- 
-@@ -2580,7 +2569,7 @@ enum bp_result dal_bios_parser_get_faked_edid_buf(
- }
- 
- /**
-- * dal_bios_parser_get_gpio_pin_info
-+ * bios_parser_get_gpio_pin_info
-  * Get GpioPin information of input gpio id
-  *
-  * @param gpio_id, GPIO ID
-@@ -2592,11 +2581,12 @@ enum bp_result dal_bios_parser_get_faked_edid_buf(
-  *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA
-  *  offset/mask
-  */
--enum bp_result dal_bios_parser_get_gpio_pin_info(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_get_gpio_pin_info(
-+	struct dc_bios *dcb,
- 	uint32_t gpio_id,
- 	struct gpio_pin_info *info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_GPIO_PIN_LUT *header;
- 	uint32_t count = 0;
- 	uint32_t i = 0;
-@@ -2648,11 +2638,12 @@ enum bp_result dal_bios_parser_get_gpio_pin_info(
-  * @param info, embedded panel patch mode structure
-  * @return Bios parser result code
-  */
--enum bp_result dal_bios_parser_enum_embedded_panel_patch_mode(
--	struct bios_parser *bp,
-+static enum bp_result bios_parser_enum_embedded_panel_patch_mode(
-+	struct dc_bios *dcb,
- 	uint32_t index,
- 	struct embedded_panel_patch_mode *mode)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	uint32_t record_size;
- 	uint32_t record_index;
- 	uint8_t *record;
-@@ -3711,7 +3702,7 @@ static void add_device_tag_from_ext_display_path(
- 	ATOM_CONNECTOR_DEVICE_TAG *device_tag = NULL;
- 	ATOM_CONNECTOR_DEVICE_TAG_RECORD *device_tag_record = NULL;
- 	enum bp_result result =
--			dal_bios_parser_get_device_tag_record(
-+			bios_parser_get_device_tag_record(
- 					bp, object, &device_tag_record);
- 
- 	if ((le16_to_cpu(ext_display_path->usDeviceTag) != CONNECTOR_OBJECT_ID_NONE)
-@@ -3958,7 +3949,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 				continue;
- 
- 			/* Remove support for all device tags. */
--			if (dal_bios_parser_get_device_tag_record(
-+			if (bios_parser_get_device_tag_record(
- 					bp, object, &dev_tag_record) != BP_RESULT_OK)
- 				continue;
- 
-@@ -4212,14 +4203,18 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 	}
- }
- 
--void dal_bios_parser_post_init(struct bios_parser *bp)
-+static void bios_parser_post_init(struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	process_ext_display_connection_info(bp);
- }
- 
--bool dal_bios_parser_is_accelerated_mode(
--	struct bios_parser *bp)
-+static bool bios_parser_is_accelerated_mode(
-+	struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	return bp->bios_helper->is_accelerated_mode(
- 			bp->ctx);
-@@ -4233,7 +4228,7 @@ bool dal_bios_parser_is_accelerated_mode(
- }
- 
- /**
-- * dal_bios_parser_set_scratch_connected
-+ * bios_parser_set_scratch_connected
-  *
-  * @brief
-  *  update VBIOS scratch register about connected displays
-@@ -4243,12 +4238,14 @@ bool dal_bios_parser_is_accelerated_mode(
-  *  bool - connection state
-  *  const ConnectorDeviceTagInfo* - pointer to device type and enum ID
-  */
--void dal_bios_parser_set_scratch_connected(
--	struct bios_parser *bp,
-+static void bios_parser_set_scratch_connected(
-+	struct dc_bios *dcb,
- 	struct graphics_object_id connector_id,
- 	bool connected,
- 	const struct connector_device_tag_info *device_tag)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_connected(
- 			bp->ctx,
-@@ -4262,7 +4259,7 @@ void dal_bios_parser_set_scratch_connected(
- }
- 
- /**
-- * dal_bios_parser_set_scratch_critical_state
-+ * bios_parser_set_scratch_critical_state
-  *
-  * @brief
-  *  update critical state bit in VBIOS scratch register
-@@ -4270,10 +4267,12 @@ void dal_bios_parser_set_scratch_connected(
-  * @param
-  *  bool - to set or reset state
-  */
--void dal_bios_parser_set_scratch_critical_state(
--	struct bios_parser *bp,
-+static void bios_parser_set_scratch_critical_state(
-+	struct dc_bios *dcb,
- 	bool state)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_critical_state(
- 			bp->ctx, state);
-@@ -4285,9 +4284,11 @@ void dal_bios_parser_set_scratch_critical_state(
- #endif
- }
- 
--void dal_bios_parser_set_scratch_acc_mode_change(
--	struct bios_parser *bp)
-+static void bios_parser_set_scratch_acc_mode_change(
-+	struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_acc_mode_change(
- 			bp->ctx);
-@@ -4300,7 +4301,7 @@ void dal_bios_parser_set_scratch_acc_mode_change(
- }
- 
- /**
-- * dal_bios_parser_prepare_scratch_active_and_requested
-+ * bios_parser_prepare_scratch_active_and_requested
-  *
-  * @brief
-  *  update VBIOS scratch registers about active and requested displays
-@@ -4311,12 +4312,14 @@ void dal_bios_parser_set_scratch_acc_mode_change(
-  *  const struct connector_device_tag_info * - pointer to display type and
-  *  enum Id
-  */
--void dal_bios_parser_prepare_scratch_active_and_requested(
--	struct bios_parser *bp,
-+static void bios_parser_prepare_scratch_active_and_requested(
-+	struct dc_bios *dcb,
- 	enum controller_id controller_id,
- 	enum signal_type signal,
- 	const struct connector_device_tag_info *device_tag)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->prepare_scratch_active_and_requested(
- 			bp->ctx,
-@@ -4332,9 +4335,11 @@ void dal_bios_parser_prepare_scratch_active_and_requested(
- #endif
- }
- 
--void dal_bios_parser_set_scratch_active_and_requested(
--	struct bios_parser *bp)
-+static void bios_parser_set_scratch_active_and_requested(
-+	struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- #ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	bp->bios_helper->set_scratch_active_and_requested(
- 			bp->ctx,
-@@ -4726,21 +4731,11 @@ static enum bp_result construct_integrated_info(
- 	return result;
- }
- 
--/*
-- * dal_bios_parser_create_integrated_info
-- *
-- * @brief
-- * Create integrated info
-- *
-- * @param
-- * bios_parser *bp - [in] BIOS  parser handler
-- *
-- * @return
-- * struct integrated_info * - pointer to the newly created integrated info
-- */
--struct integrated_info *dal_bios_parser_create_integrated_info(
--	struct bios_parser *bp)
-+
-+static struct integrated_info *bios_parser_create_integrated_info(
-+	struct dc_bios *dcb)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct integrated_info *info = NULL;
- 
- 	info = dc_service_alloc(bp->ctx, sizeof(struct integrated_info));
-@@ -4758,24 +4753,344 @@ struct integrated_info *dal_bios_parser_create_integrated_info(
- 	return NULL;
- }
- 
--/*
-- * dal_bios_parser_destroy_integrated_info
-- *
-- * @brief
-- * Destroy provided integrated info
-- *
-- * @param
-- * struct integrated_info **info - [in] info to be destroied
-- */
--void dal_bios_parser_destroy_integrated_info(struct dc_context *ctx, struct integrated_info **info)
-+static void bios_parser_destroy_integrated_info(
-+	struct dc_bios *dcb,
-+	struct integrated_info **info)
- {
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
- 	if (info == NULL) {
- 		ASSERT_CRITICAL(0);
- 		return;
- 	}
- 
- 	if (*info != NULL) {
--		dc_service_free(ctx, *info);
-+		dc_service_free(bp->ctx, *info);
- 		*info = NULL;
- 	}
- }
-+
-+/******************************************************************************
-+ * Stub-functions */
-+static bool is_lid_open(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+static bool is_lid_status_changed(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+static bool is_display_config_changed(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+static void set_scratch_lcd_scale(
-+	struct dc_bios *bios,
-+	enum lcd_scale scale)
-+{
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static enum lcd_scale get_scratch_lcd_scale(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return LCD_SCALE_NONE;
-+}
-+
-+static void get_bios_event_info(
-+	struct dc_bios *bios,
-+	struct bios_event_info *info)
-+{
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static void update_requested_backlight_level(
-+	struct dc_bios *bios,
-+	uint32_t backlight_8bit)
-+{
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static uint32_t get_requested_backlight_level(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return 0;
-+}
-+
-+static void take_backlight_control(
-+	struct dc_bios *bios,
-+	bool cntl)
-+{
-+	BREAK_TO_DEBUGGER();
-+}
-+
-+static bool is_active_display(
-+	struct dc_bios *bios,
-+	enum signal_type signal,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return false;
-+}
-+
-+static enum controller_id get_embedded_display_controller_id(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return CONTROLLER_ID_UNDEFINED;
-+}
-+
-+static uint32_t get_embedded_display_refresh_rate(
-+	struct dc_bios *bios)
-+{
-+	BREAK_TO_DEBUGGER();
-+	return 0;
-+}
-+
-+/******************************************************************************/
-+
-+static const struct dc_vbios_funcs vbios_funcs = {
-+	.get_connectors_number = bios_parser_get_connectors_number,
-+
-+	.power_down = bios_parser_power_down,
-+
-+	.power_up = bios_parser_power_up,
-+
-+	.get_encoders_number = bios_parser_get_encoders_number,
-+
-+	.get_oem_ddc_lines_number = bios_parser_get_oem_ddc_lines_number,
-+
-+	.get_encoder_id = bios_parser_get_encoder_id,
-+
-+	.get_connector_id = bios_parser_get_connector_id,
-+
-+	.get_src_number = bios_parser_get_src_number,
-+
-+	.get_dst_number = bios_parser_get_dst_number,
-+
-+	.get_gpio_record = bios_parser_get_gpio_record,
-+
-+	.get_src_obj = bios_parser_get_src_obj,
-+
-+	.get_dst_obj = bios_parser_get_dst_obj,
-+
-+	.get_i2c_info = bios_parser_get_i2c_info,
-+
-+	.get_oem_ddc_info = bios_parser_get_oem_ddc_info,
-+
-+	.get_voltage_ddc_info = bios_parser_get_voltage_ddc_info,
-+
-+	.get_thermal_ddc_info = bios_parser_get_thermal_ddc_info,
-+
-+	.get_hpd_info = bios_parser_get_hpd_info,
-+
-+	.get_device_tag = bios_parser_get_device_tag,
-+
-+	.get_firmware_info = bios_parser_get_firmware_info,
-+
-+	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
-+
-+	.get_ss_entry_number = bios_parser_get_ss_entry_number,
-+
-+	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
-+
-+	.enum_embedded_panel_patch_mode = bios_parser_enum_embedded_panel_patch_mode,
-+
-+	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
-+
-+	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
-+
-+	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
-+
-+	.get_faked_edid_len = bios_parser_get_faked_edid_len,
-+
-+	.get_faked_edid_buf = bios_parser_get_faked_edid_buf,
-+
-+	.get_encoder_cap_info = bios_parser_get_encoder_cap_info,
-+
-+	.get_din_connector_info = bios_parser_get_din_connector_info,
-+
-+	.is_lid_open = is_lid_open,
-+
-+	.is_lid_status_changed = is_lid_status_changed,
-+
-+	.is_display_config_changed = is_display_config_changed,
-+
-+	.is_accelerated_mode = bios_parser_is_accelerated_mode,
-+
-+	.set_scratch_lcd_scale = set_scratch_lcd_scale,
-+
-+	.get_scratch_lcd_scale = get_scratch_lcd_scale,
-+
-+	.get_bios_event_info = get_bios_event_info,
-+
-+	.update_requested_backlight_level = update_requested_backlight_level,
-+
-+	.get_requested_backlight_level = get_requested_backlight_level,
-+
-+	.take_backlight_control = take_backlight_control,
-+
-+	.is_active_display = is_active_display,
-+
-+	.get_embedded_display_controller_id = get_embedded_display_controller_id,
-+
-+	.get_embedded_display_refresh_rate = get_embedded_display_refresh_rate,
-+
-+	.set_scratch_connected = bios_parser_set_scratch_connected,
-+
-+	.prepare_scratch_active_and_requested = bios_parser_prepare_scratch_active_and_requested,
-+
-+	.set_scratch_active_and_requested = bios_parser_set_scratch_active_and_requested,
-+
-+	.set_scratch_critical_state = bios_parser_set_scratch_critical_state,
-+
-+	.set_scratch_acc_mode_change = bios_parser_set_scratch_acc_mode_change,
-+
-+	.is_device_id_supported = bios_parser_is_device_id_supported,
-+
-+	/* COMMANDS */
-+	.encoder_control = bios_parser_encoder_control,
-+
-+	.transmitter_control = bios_parser_transmitter_control,
-+
-+	.crt_control = bios_parser_crt_control,
-+
-+	.dvo_encoder_control = bios_parser_dvo_encoder_control,
-+
-+	.enable_crtc = bios_parser_enable_crtc,
-+
-+	.adjust_pixel_clock = bios_parser_adjust_pixel_clock,
-+
-+	.set_pixel_clock = bios_parser_set_pixel_clock,
-+
-+	.set_dce_clock = bios_parser_set_dce_clock,
-+
-+	.enable_spread_spectrum_on_ppll = bios_parser_enable_spread_spectrum_on_ppll,
-+
-+	.program_crtc_timing = bios_parser_program_crtc_timing,
-+
-+	.blank_crtc = bios_parser_blank_crtc,
-+
-+	.set_overscan = bios_parser_set_overscan,
-+
-+	.crtc_source_select = bios_parser_crtc_source_select,
-+
-+	.program_display_engine_pll = bios_parser_program_display_engine_pll,
-+
-+	.get_divider_for_target_display_clock = bios_parser_get_divider_for_target_display_clock,
-+
-+	.dac_load_detect = bios_parser_dac_load_detect,
-+
-+	.enable_memory_requests = bios_parser_enable_memory_requests,
-+
-+	.external_encoder_control = bios_parser_external_encoder_control,
-+
-+	.enable_disp_power_gating = bios_parser_enable_disp_power_gating,
-+
-+	.post_init = bios_parser_post_init,
-+
-+	.create_integrated_info = bios_parser_create_integrated_info,
-+
-+	.destroy_integrated_info = bios_parser_destroy_integrated_info,
-+};
-+
-+static bool bios_parser_construct(
-+	struct bios_parser *bp,
-+	struct bp_init_data *init,
-+	struct adapter_service *as)
-+{
-+	uint16_t *rom_header_offset = NULL;
-+	ATOM_ROM_HEADER *rom_header = NULL;
-+	ATOM_OBJECT_HEADER *object_info_tbl;
-+	enum dce_version dce_version;
-+
-+	if (!as)
-+		return false;
-+
-+	if (!init)
-+		return false;
-+
-+	if (!init->bios)
-+		return false;
-+
-+	bp->base.funcs = &vbios_funcs;
-+
-+	dce_version = dal_adapter_service_get_dce_version(as);
-+	bp->ctx = init->ctx;
-+	bp->as = as;
-+	bp->bios = init->bios;
-+	bp->bios_size = bp->bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT;
-+	bp->bios_local_image = NULL;
-+	bp->lcd_scale = LCD_SCALE_UNKNOWN;
-+
-+	rom_header_offset =
-+	GET_IMAGE(uint16_t, OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
-+
-+	if (!rom_header_offset)
-+		return false;
-+
-+	rom_header = GET_IMAGE(ATOM_ROM_HEADER, *rom_header_offset);
-+
-+	if (!rom_header)
-+		return false;
-+
-+	bp->master_data_tbl =
-+	GET_IMAGE(ATOM_MASTER_DATA_TABLE,
-+		rom_header->usMasterDataTableOffset);
-+
-+	if (!bp->master_data_tbl)
-+		return false;
-+
-+	bp->object_info_tbl_offset = DATA_TABLES(Object_Header);
-+
-+	if (!bp->object_info_tbl_offset)
-+		return false;
-+
-+	object_info_tbl =
-+	GET_IMAGE(ATOM_OBJECT_HEADER, bp->object_info_tbl_offset);
-+
-+	if (!object_info_tbl)
-+		return false;
-+
-+	get_atom_data_table_revision(&object_info_tbl->sHeader,
-+		&bp->object_info_tbl.revision);
-+
-+	if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 3) {
-+		ATOM_OBJECT_HEADER_V3 *tbl_v3;
-+
-+		tbl_v3 = GET_IMAGE(ATOM_OBJECT_HEADER_V3,
-+			bp->object_info_tbl_offset);
-+		if (!tbl_v3)
-+			return false;
-+
-+		bp->object_info_tbl.v1_3 = tbl_v3;
-+	} else if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 1)
-+		bp->object_info_tbl.v1_1 = object_info_tbl;
-+	else
-+		return false;
-+
-+#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-+	bp->vbios_helper_data.active = 0;
-+	bp->vbios_helper_data.requested = 0;
-+	dal_bios_parser_init_bios_helper(bp, dce_version);
-+#endif
-+	dal_bios_parser_init_cmd_tbl(bp);
-+	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
-+
-+	return true;
-+}
-+
-+/******************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index 0089800..a0927cf 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -28,7 +28,6 @@
- #include "atom.h"
- 
- #include "include/bios_parser_types.h"
--#include "include/adapter_service_types.h"
- #include "bios_parser_helper.h"
- #include "command_table_helper.h"
- #include "command_table.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 00a2453..841e02e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -143,7 +143,7 @@ failed_alloc:
- static void init_hw(struct dc *dc)
- {
- 	int i;
--	struct bios_parser *bp;
-+	struct dc_bios *bp;
- 	struct transform *xfm;
- 
- 	bp = dal_adapter_service_get_bios_parser(dc->res_pool.adapter_srv);
-@@ -164,7 +164,7 @@ static void init_hw(struct dc *dc)
- 	}
- 
- 	dc->hwss.clock_gating_power_up(dc->ctx, false);
--	dal_bios_parser_power_up(bp);
-+	bp->funcs->power_up(bp);
- 	/***************************************/
- 
- 	for (i = 0; i < dc->link_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index f86ddb0..341c968 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -27,9 +27,8 @@
- #define DC_INTERFACE_H_
- 
- #include "dc_types.h"
--/* TODO: We should not include audio_interface.h here. Maybe just define
-- * struct audio_info here */
--#include "audio_interface.h"
-+#include "dal_types.h"
-+#include "audio_types.h"
- #include "logger_types.h"
- 
- #define MAX_SINKS_PER_LINK 4
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index a82cbee..0f85f63 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -26,15 +26,255 @@
- #ifndef DC_BIOS_TYPES_H
- #define DC_BIOS_TYPES_H
- 
--struct dc_vbios_funcs;
-+/******************************************************************************
-+ * Interface file for VBIOS implementations.
-+ *
-+ * The default implementation is inside DC.
-+ * Display Manager (which instantiates DC) has the option to supply it's own
-+ * (external to DC) implementation of VBIOS, which will be called by DC, using
-+ * this interface.
-+ * (The intended use is Diagnostics, but other uses may appear.)
-+ *****************************************************************************/
-+
-+#include "include/bios_parser_types.h"
- 
--struct dc_bios {
--	const struct dc_vbios_funcs *funcs;
--};
- 
- struct dc_vbios_funcs {
- 	uint8_t (*get_connectors_number)(struct dc_bios *bios);
-+
-+	void (*power_down)(struct dc_bios *bios);
-+	void (*power_up)(struct dc_bios *bios);
-+
-+	uint8_t (*get_encoders_number)(struct dc_bios *bios);
-+	uint32_t (*get_oem_ddc_lines_number)(struct dc_bios *bios);
-+
-+	struct graphics_object_id (*get_encoder_id)(
-+		struct dc_bios *bios,
-+		uint32_t i);
-+	struct graphics_object_id (*get_connector_id)(
-+		struct dc_bios *bios,
-+		uint8_t connector_index);
-+	uint32_t (*get_src_number)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id id);
-+	uint32_t (*get_dst_number)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id id);
-+
-+	uint32_t (*get_gpio_record)(
-+		struct dc_bios *dcb,
-+		struct graphics_object_id id,
-+		struct bp_gpio_cntl_info *gpio_record,
-+		uint32_t record_size);
-+
-+	enum bp_result (*get_src_obj)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id object_id, uint32_t index,
-+		struct graphics_object_id *src_object_id);
-+	enum bp_result (*get_dst_obj)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id object_id, uint32_t index,
-+		struct graphics_object_id *dest_object_id);
-+	enum bp_result (*get_oem_ddc_info)(
-+		struct dc_bios *bios,
-+		uint32_t index,
-+		struct graphics_object_i2c_info *info);
-+
-+	enum bp_result (*get_i2c_info)(
-+		struct dc_bios *dcb,
-+		struct graphics_object_id id,
-+		struct graphics_object_i2c_info *info);
-+
-+	enum bp_result (*get_voltage_ddc_info)(
-+		struct dc_bios *bios,
-+		uint32_t index,
-+		struct graphics_object_i2c_info *info);
-+	enum bp_result (*get_thermal_ddc_info)(
-+		struct dc_bios *bios,
-+		uint32_t i2c_channel_id,
-+		struct graphics_object_i2c_info *info);
-+	enum bp_result (*get_hpd_info)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id id,
-+		struct graphics_object_hpd_info *info);
-+	enum bp_result (*get_device_tag)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id connector_object_id,
-+		uint32_t device_tag_index,
-+		struct connector_device_tag_info *info);
-+	enum bp_result (*get_firmware_info)(
-+		struct dc_bios *bios,
-+		struct firmware_info *info);
-+	enum bp_result (*get_spread_spectrum_info)(
-+		struct dc_bios *bios,
-+		enum as_signal_type signal,
-+		uint32_t index,
-+		struct spread_spectrum_info *ss_info);
-+	uint32_t (*get_ss_entry_number)(
-+		struct dc_bios *bios,
-+		enum as_signal_type signal);
-+	enum bp_result (*get_embedded_panel_info)(
-+		struct dc_bios *bios,
-+		struct embedded_panel_info *info);
-+	enum bp_result (*enum_embedded_panel_patch_mode)(
-+		struct dc_bios *bios,
-+		uint32_t index,
-+		struct embedded_panel_patch_mode *mode);
-+	enum bp_result (*get_gpio_pin_info)(
-+		struct dc_bios *bios,
-+		uint32_t gpio_id,
-+		struct gpio_pin_info *info);
-+	enum bp_result (*get_faked_edid_len)(
-+		struct dc_bios *bios,
-+		uint32_t *len);
-+	enum bp_result (*get_faked_edid_buf)(
-+		struct dc_bios *bios,
-+		uint8_t *buff,
-+		uint32_t len);
-+	enum bp_result (*get_encoder_cap_info)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id object_id,
-+		struct bp_encoder_cap_info *info);
-+	enum bp_result (*get_din_connector_info)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id id,
-+		struct din_connector_info *info);
-+
-+	bool (*is_lid_open)(
-+		struct dc_bios *bios);
-+	bool (*is_lid_status_changed)(
-+		struct dc_bios *bios);
-+	bool (*is_display_config_changed)(
-+		struct dc_bios *bios);
-+	bool (*is_accelerated_mode)(
-+		struct dc_bios *bios);
-+	void (*set_scratch_lcd_scale)(
-+		struct dc_bios *bios,
-+		enum lcd_scale scale);
-+	enum lcd_scale  (*get_scratch_lcd_scale)(
-+		struct dc_bios *bios);
-+	void (*get_bios_event_info)(
-+		struct dc_bios *bios,
-+		struct bios_event_info *info);
-+	void (*update_requested_backlight_level)(
-+		struct dc_bios *bios,
-+		uint32_t backlight_8bit);
-+	uint32_t (*get_requested_backlight_level)(
-+		struct dc_bios *bios);
-+	void (*take_backlight_control)(
-+		struct dc_bios *bios,
-+		bool cntl);
-+	bool (*is_active_display)(
-+		struct dc_bios *bios,
-+		enum signal_type signal,
-+		const struct connector_device_tag_info *device_tag);
-+	enum controller_id (*get_embedded_display_controller_id)(
-+		struct dc_bios *bios);
-+	uint32_t (*get_embedded_display_refresh_rate)(
-+		struct dc_bios *bios);
-+	void (*set_scratch_connected)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id connector_id,
-+		bool connected,
-+		const struct connector_device_tag_info *device_tag);
-+	void (*prepare_scratch_active_and_requested)(
-+		struct dc_bios *bios,
-+		enum controller_id controller_id,
-+		enum signal_type signal,
-+		const struct connector_device_tag_info *device_tag);
-+	void (*set_scratch_active_and_requested)(
-+		struct dc_bios *bios);
-+	void (*set_scratch_critical_state)(
-+		struct dc_bios *bios,
-+		bool state);
-+	void (*set_scratch_acc_mode_change)(
-+		struct dc_bios *bios);
-+
-+	bool (*is_device_id_supported)(
-+		struct dc_bios *bios,
-+		struct device_id id);
-+
-+	/* COMMANDS */
-+
-+	enum bp_result (*encoder_control)(
-+		struct dc_bios *bios,
-+		struct bp_encoder_control *cntl);
-+	enum bp_result (*transmitter_control)(
-+		struct dc_bios *bios,
-+		struct bp_transmitter_control *cntl);
-+	enum bp_result (*crt_control)(
-+		struct dc_bios *bios,
-+		enum engine_id engine_id,
-+		bool enable,
-+		uint32_t pixel_clock);
-+	enum bp_result (*dvo_encoder_control)(
-+		struct dc_bios *bios,
-+		struct bp_dvo_encoder_control *cntl);
-+	enum bp_result (*enable_crtc)(
-+		struct dc_bios *bios,
-+		enum controller_id id,
-+		bool enable);
-+	enum bp_result (*adjust_pixel_clock)(
-+		struct dc_bios *bios,
-+		struct bp_adjust_pixel_clock_parameters *bp_params);
-+	enum bp_result (*set_pixel_clock)(
-+		struct dc_bios *bios,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*set_dce_clock)(
-+		struct dc_bios *bios,
-+		struct bp_set_dce_clock_parameters *bp_params);
-+	enum bp_result (*enable_spread_spectrum_on_ppll)(
-+		struct dc_bios *bios,
-+		struct bp_spread_spectrum_parameters *bp_params,
-+		bool enable);
-+	enum bp_result (*program_crtc_timing)(
-+		struct dc_bios *bios,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+	enum bp_result (*blank_crtc)(
-+		struct dc_bios *bios,
-+		struct bp_blank_crtc_parameters *bp_params,
-+		bool blank);
-+	enum bp_result (*set_overscan)(
-+		struct dc_bios *bios,
-+		struct bp_hw_crtc_overscan_parameters *bp_params);
-+	enum bp_result (*crtc_source_select)(
-+		struct dc_bios *bios,
-+		struct bp_crtc_source_select *bp_params);
-+	enum bp_result (*program_display_engine_pll)(
-+		struct dc_bios *bios,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*get_divider_for_target_display_clock)(
-+		struct dc_bios *bios,
-+		struct bp_display_clock_parameters *bp_params);
-+	enum signal_type (*dac_load_detect)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id encoder,
-+		struct graphics_object_id connector,
-+		enum signal_type display_signal);
-+	enum bp_result (*enable_memory_requests)(
-+		struct dc_bios *bios,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*external_encoder_control)(
-+		struct dc_bios *bios,
-+		struct bp_external_encoder_control *cntl);
-+	enum bp_result (*enable_disp_power_gating)(
-+		struct dc_bios *bios,
-+		enum controller_id controller_id,
-+		enum bp_pipe_control_action action);
-+
-+	void (*post_init)(struct dc_bios *bios);
-+
-+	struct integrated_info *(*create_integrated_info)(
-+		struct dc_bios *bios);
-+
-+	void (*destroy_integrated_info)(
-+		struct dc_bios *dcb,
-+		struct integrated_info **info);
- };
- 
-+struct dc_bios {
-+	const struct dc_vbios_funcs *funcs;
-+};
- 
- #endif /* DC_BIOS_TYPES_H */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index 7a14300..bd082d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -33,6 +33,8 @@
- #include "dc_types.h"
- #include "dc.h"
- 
-+struct dp_mst_stream_allocation_table;
-+
- enum dc_edid_status dc_helpers_parse_edid_caps(
- 	struct dc_context *ctx,
- 	const struct dc_edid *edid,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 4f37282..fbcd799 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -24,6 +24,7 @@
-  */
- #include "dc_services.h"
- #include "dc.h"
-+#include "dc_bios_types.h"
- #include "core_types.h"
- #include "core_status.h"
- #include "resource.h"
-@@ -146,7 +147,7 @@ static void dce110_enable_display_pipe_clock_gating(
- static bool dce110_enable_display_power_gating(
- 	struct dc_context *ctx,
- 	uint8_t controller_id,
--	struct bios_parser *bp,
-+	struct dc_bios *dcb,
- 	enum pipe_gating_control power_gating)
- {
- 	enum bp_result bp_result = BP_RESULT_OK;
-@@ -161,8 +162,8 @@ static bool dce110_enable_display_power_gating(
- 
- 	if (!(power_gating == PIPE_GATING_CONTROL_INIT &&
- 					(controller_id + 1) != CONTROLLER_ID_D0))
--		bp_result = dal_bios_parser_enable_disp_power_gating(
--						bp, controller_id + 1, cntl);
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
- 
- 	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
- 		init_pte(ctx);
-@@ -235,12 +236,13 @@ static bool set_gamma_ramp(
- static enum dc_status bios_parser_crtc_source_select(
- 		struct core_stream *stream)
- {
-+	struct dc_bios *dcb;
- 	/* call VBIOS table to set CRTC source for the HW
- 	 * encoder block
- 	 * note: video bios clears all FMT setting here. */
--
- 	struct bp_crtc_source_select crtc_source_select = {0};
- 	const struct core_sink *sink = stream->sink;
-+
- 	crtc_source_select.engine_id = stream->stream_enc->id;
- 	crtc_source_select.controller_id = stream->controller_idx + 1;
- 	/*TODO: Need to un-hardcode color depth, dp_audio and account for
-@@ -249,14 +251,16 @@ static enum dc_status bios_parser_crtc_source_select(
- 	crtc_source_select.signal = sink->public.sink_signal;
- 	crtc_source_select.enable_dp_audio = false;
- 	crtc_source_select.sink_signal = sink->public.sink_signal;
--	crtc_source_select.display_output_bit_depth
--		= PANEL_8BIT_COLOR;
-+	crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
-+
-+	dcb = dal_adapter_service_get_bios_parser(sink->link->adapter_srv);
- 
--	if (BP_RESULT_OK != dal_bios_parser_crtc_source_select(
--		dal_adapter_service_get_bios_parser(sink->link->adapter_srv),
-+	if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
-+		dcb,
- 		&crtc_source_select)) {
- 		return DC_ERROR_UNEXPECTED;
- 	}
-+
- 	return DC_OK;
- }
- 
-@@ -625,9 +629,9 @@ static void set_blender_mode(
- static void update_bios_scratch_critical_state(struct adapter_service *as,
- 		bool state)
- {
--	dal_bios_parser_set_scratch_critical_state(
--		dal_adapter_service_get_bios_parser(as),
--		state);
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	dcb->funcs->set_scratch_critical_state(dcb, state);
- }
- 
- static void update_info_frame(struct core_stream *stream)
-@@ -787,14 +791,14 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
- 			.flags.timing_changed;
- 	enum color_space color_space;
--	struct bios_parser *bp;
-+	struct dc_bios *dcb;
- 
--	bp = dal_adapter_service_get_bios_parser(
-+	dcb = dal_adapter_service_get_bios_parser(
- 			context->res_ctx.pool.adapter_srv);
- 
- 	if (timing_changed) {
- 		dce110_enable_display_power_gating(
--				stream->ctx, controller_idx, bp,
-+				stream->ctx, controller_idx, dcb,
- 				PIPE_GATING_CONTROL_DISABLE);
- 
- 		/* Must blank CRTC after disabling power gating and before any
-@@ -961,10 +965,10 @@ static void disable_vga_and_power_gate_all_controllers(
- {
- 	int i;
- 	struct timing_generator *tg;
--	struct bios_parser *bp;
-+	struct dc_bios *dcb;
- 	struct dc_context *ctx;
- 
--	bp = dal_adapter_service_get_bios_parser(
-+	dcb = dal_adapter_service_get_bios_parser(
- 			dc->res_pool.adapter_srv);
- 
- 	for (i = 0; i < dc->res_pool.controller_count; i++) {
-@@ -977,7 +981,7 @@ static void disable_vga_and_power_gate_all_controllers(
- 		 * powergating. */
- 		dce110_enable_display_pipe_clock_gating(ctx,
- 				true);
--		dce110_enable_display_power_gating(ctx, i+1, bp,
-+		dce110_enable_display_power_gating(ctx, i+1, dcb,
- 				PIPE_GATING_CONTROL_ENABLE);
- 	}
- }
-@@ -991,16 +995,15 @@ static void disable_vga_and_power_gate_all_controllers(
-  */
- static void enable_accelerated_mode(struct dc *dc)
- {
--	struct bios_parser *bp;
-+	struct dc_bios *dcb;
- 
--	bp = dal_adapter_service_get_bios_parser(
--			dc->res_pool.adapter_srv);
-+	dcb = dal_adapter_service_get_bios_parser(dc->res_pool.adapter_srv);
- 
- 	power_down_all_hw_blocks(dc);
- 
- 	disable_vga_and_power_gate_all_controllers(dc);
- 
--	dal_bios_parser_set_scratch_acc_mode_change(bp);
-+	dcb->funcs->set_scratch_acc_mode_change(dcb);
- }
- 
- #if 0
-@@ -1559,9 +1562,9 @@ static bool update_plane_address(
- static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 		struct validate_context *context)
- {
--	struct bios_parser *bp;
-+	struct dc_bios *dcb;
- 
--	bp = dal_adapter_service_get_bios_parser(
-+	dcb = dal_adapter_service_get_bios_parser(
- 			context->res_ctx.pool.adapter_srv);
- 	if (stream->audio) {
- 		dal_audio_disable_output(stream->audio,
-@@ -1580,7 +1583,7 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 	disable_stereo_mixer(stream->ctx);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
- 	dce110_enable_display_power_gating(
--			stream->ctx, stream->controller_idx, bp,
-+			stream->ctx, stream->controller_idx, dcb,
- 			PIPE_GATING_CONTROL_ENABLE);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index deaf94d..73ba7b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -29,6 +29,8 @@
- #include "stream_encoder.h"
- #include "dce110_link_encoder.h"
- #include "i2caux_interface.h"
-+#include "dc_bios_types.h"
-+
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
-@@ -168,6 +170,19 @@ static enum transmitter translate_encoder_to_transmitter(
- 	}
- }
- 
-+static enum bp_result link_transmitter_control(
-+	struct dce110_link_encoder *enc110,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result;
-+	struct dc_bios *bp = dal_adapter_service_get_bios_parser(
-+					enc110->base.adapter_service);
-+
-+	result = bp->funcs->transmitter_control(bp, cntl);
-+
-+	return result;
-+}
-+
- static void enable_phy_bypass_mode(
- 	struct dce110_link_encoder *enc110,
- 	bool enable)
-@@ -672,9 +687,7 @@ static void link_encoder_edp_power_control(
- 		cntl.lanes_number = LANE_COUNT_FOUR;
- 		cntl.hpd_sel = enc110->base.hpd_source;
- 
--		bp_result = dal_bios_parser_transmitter_control(
--				dal_adapter_service_get_bios_parser(
--					enc110->base.adapter_service), &cntl);
-+		bp_result = link_transmitter_control(enc110, &cntl);
- 
- 		if (BP_RESULT_OK != bp_result) {
- 
-@@ -866,10 +879,7 @@ static void link_encoder_edp_backlight_control(
- 	 * Enable it in the future if necessary.
- 	 */
- 	/* dc_service_sleep_in_milliseconds(50); */
--
--	dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service), &cntl);
-+	link_transmitter_control(enc110, &cntl);
- }
- 
- static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
-@@ -1299,10 +1309,7 @@ void dce110_link_encoder_hw_init(
- 	cntl.coherent = false;
- 	cntl.hpd_sel = enc110->base.hpd_source;
- 
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service),
--		&cntl);
-+	result = link_transmitter_control(enc110, &cntl);
- 
- 	if (result != BP_RESULT_OK) {
- 		dal_logger_write(ctx->logger,
-@@ -1317,10 +1324,8 @@ void dce110_link_encoder_hw_init(
- 	if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
- 		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
- 
--		result = dal_bios_parser_transmitter_control(
--			dal_adapter_service_get_bios_parser(
--				enc110->base.adapter_service),
--			&cntl);
-+		result = link_transmitter_control(enc110, &cntl);
-+
- 		ASSERT(result == BP_RESULT_OK);
- 
- 	} else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-@@ -1416,10 +1421,7 @@ void dce110_link_encoder_enable_tmds_output(
- 	cntl.pixel_clock = pixel_clock;
- 	cntl.color_depth = color_depth;
- 
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service),
--		&cntl);
-+	result = link_transmitter_control(enc110, &cntl);
- 
- 	if (result != BP_RESULT_OK) {
- 		dal_logger_write(ctx->logger,
-@@ -1475,10 +1477,7 @@ void dce110_link_encoder_enable_dp_output(
- 	/* TODO: check if undefined works */
- 	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
- 
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service),
--		&cntl);
-+	result = link_transmitter_control(enc110, &cntl);
- 
- 	if (result != BP_RESULT_OK) {
- 		dal_logger_write(ctx->logger,
-@@ -1521,10 +1520,7 @@ void dce110_link_encoder_enable_dp_mst_output(
- 	/* TODO: check if undefined works */
- 	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
- 
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service),
--		&cntl);
-+	result = link_transmitter_control(enc110, &cntl);
- 
- 	if (result != BP_RESULT_OK) {
- 		dal_logger_write(ctx->logger,
-@@ -1578,9 +1574,7 @@ void dce110_link_encoder_disable_output(
- 	cntl.signal = signal;
- 	cntl.connector_obj_id = enc110->base.connector;
- 
--	result = dal_bios_parser_transmitter_control(
--		dal_adapter_service_get_bios_parser(
--			enc110->base.adapter_service), &cntl);
-+	result = link_transmitter_control(enc110, &cntl);
- 
- 	if (result != BP_RESULT_OK) {
- 		dal_logger_write(ctx->logger,
-@@ -1654,10 +1648,7 @@ void dce110_link_encoder_dp_set_lane_settings(
- 		cntl.lane_settings = training_lane_set.raw;
- 
- 		/* call VBIOS table to set voltage swing and pre-emphasis */
--
--		dal_bios_parser_transmitter_control(
--			dal_adapter_service_get_bios_parser(
--				enc110->base.adapter_service), &cntl);
-+		link_transmitter_control(enc110, &cntl);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 80d3f8a..565f9cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -104,7 +104,7 @@ static struct timing_generator *dce110_timing_generator_create(
- static struct stream_encoder *dce110_stream_encoder_create(
- 	enum engine_id eng_id,
- 	struct dc_context *ctx,
--	struct bios_parser *bp,
-+	struct dc_bios *bp,
- 	const struct dce110_stream_enc_offsets *offsets)
- {
- 	struct dce110_stream_encoder *enc110 =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 81996f7..87f59ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -24,6 +24,7 @@
-  */
- 
- #include "dal_services.h"
-+#include "dc_bios_types.h"
- #include "dce110_stream_encoder.h"
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -282,7 +283,7 @@ static void dce110_update_hdmi_info_packet(
- bool dce110_stream_encoder_construct(
- 	struct dce110_stream_encoder *enc110,
- 	struct dc_context *ctx,
--	struct bios_parser *bp,
-+	struct dc_bios *bp,
- 	enum engine_id eng_id,
- 	const struct dce110_stream_enc_offsets *offsets)
- {
-@@ -411,7 +412,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	cntl.lanes_number = LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
--	if (dal_bios_parser_encoder_control(
-+	if (enc110->base.bp->funcs->encoder_control(
- 			enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
-@@ -592,7 +593,7 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 				LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
--	if (dal_bios_parser_encoder_control(
-+	if (enc110->base.bp->funcs->encoder_control(
- 			enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 200308c..ddc16cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -44,7 +44,7 @@ struct dce110_stream_encoder {
- bool dce110_stream_encoder_construct(
- 	struct dce110_stream_encoder *enc110,
- 	struct dc_context *ctx,
--	struct bios_parser *bp,
-+	struct dc_bios *bp,
- 	enum engine_id eng_id,
- 	const struct dce110_stream_enc_offsets *offsets);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 2c7c27f..5dc3605 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -30,6 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dc_types.h"
-+#include "dc_bios_types.h"
- 
- #include "include/grph_object_id.h"
- #include "include/adapter_service_interface.h"
-@@ -288,7 +289,7 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	dal_write_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
--	result = dal_bios_parser_enable_crtc(tg->bp, tg110->controller_id, true);
-+	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -467,7 +468,7 @@ bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
- 
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	result = dal_bios_parser_enable_crtc(tg->bp, tg110->controller_id, false);
-+	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);
- 
- 	/* Need to make sure stereo is disabled according to the DCE5.0 spec */
- 
-@@ -572,7 +573,7 @@ bool dce110_timing_generator_program_timing_generator(
- 	if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1)
- 		bp_params.flags.HORZ_COUNT_BY_TWO = 1;
- 
--	result = dal_bios_parser_program_crtc_timing(tg->bp, &bp_params);
-+	result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params);
- 
- 	program_horz_count_by_2(tg, &patched_crtc_timing);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-index 7c94733..acc8838 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-@@ -326,7 +326,7 @@ static bool calc_pll_clock_source_max_vco_construct(
- 			init_data->bp == NULL)
- 		return false;
- 
--	if (dal_bios_parser_get_firmware_info(
-+	if (init_data->bp->funcs->get_firmware_info(
- 				init_data->bp,
- 				&fw_info) != BP_RESULT_OK)
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-index be44d06..48db3d6 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-@@ -24,10 +24,12 @@
- #ifndef __DAL_CALC_PLL_CLOCK_SOURCE_H__
- #define __DAL_CALC_PLL_CLOCK_SOURCE_H__
- 
-+#include "dc_bios_types.h"
-+
- #include "include/clock_source_types.h"
- 
- struct calc_pll_clock_source_init_data {
--	struct bios_parser *bp;
-+	struct dc_bios *bp;
- 	uint32_t min_pix_clk_pll_post_divider;
- 	uint32_t max_pix_clk_pll_post_divider;
- 	uint32_t min_pll_ref_divider;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-index 11f16b7..cd4a91e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-@@ -265,9 +265,10 @@ void dal_clock_source_get_ss_info_from_atombios(
- 	spread_spectrum_data[0] = NULL;
- 	*ss_entries_num = 0;
- 
--	*ss_entries_num = dal_bios_parser_get_ss_entry_number(
-+	*ss_entries_num = clk_src->bios_parser->funcs->get_ss_entry_number(
- 			clk_src->bios_parser,
- 			as_signal);
-+
- 	if (*ss_entries_num == 0)
- 		return;
- 
-@@ -285,11 +286,13 @@ void dal_clock_source_get_ss_info_from_atombios(
- 	for (i = 0, ss_info_cur = ss_info;
- 		i < (*ss_entries_num);
- 		++i, ++ss_info_cur) {
--		bp_result = dal_bios_parser_get_spread_spectrum_info(
-+
-+		bp_result = clk_src->bios_parser->funcs->get_spread_spectrum_info(
- 				clk_src->bios_parser,
- 				as_signal,
- 				i,
- 				ss_info_cur);
-+
- 		if (bp_result != BP_RESULT_OK)
- 			goto out_free_data;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-index 67ececd..a7863cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-@@ -100,7 +100,7 @@ struct clock_source {
- 	struct graphics_object_id id;
- 	enum clock_source_id clk_src_id;
- 	struct adapter_service *adapter_service;
--	struct bios_parser *bios_parser;
-+	struct dc_bios *bios_parser;
- 
- 	struct spread_spectrum_data *ep_ss_params;
- 	uint32_t ep_ss_params_cnt;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index e582ba0..a2a615a 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -774,7 +774,7 @@ static void set_clock(
- {
- 	struct bp_pixel_clock_parameters pxl_clk_params;
- 	struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
--	struct bios_parser *bp = dal_adapter_service_get_bios_parser(base->as);
-+	struct dc_bios *bp = dal_adapter_service_get_bios_parser(base->as);
- 
- 	/* Prepare to program display clock*/
- 	dc_service_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-@@ -782,7 +782,7 @@ static void set_clock(
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = base->id;
- 
--	dal_bios_parser_program_display_engine_pll(bp, &pxl_clk_params);
-+	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
- 
- 	if (dc->dfs_bypass_enabled) {
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-index d83eea3..cce9b0b 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-@@ -127,7 +127,7 @@ static bool disable_spread_spectrum(struct pll_clock_source_dce110 *clk_src)
- 	bp_ss_params.pll_id = clock_source->clk_src_id;
- 
- 	/*Call ASICControl to process ATOMBIOS Exec table*/
--	result = dal_bios_parser_enable_spread_spectrum_on_ppll(
-+	result = clock_source->bios_parser->funcs->enable_spread_spectrum_on_ppll(
- 			clock_source->bios_parser,
- 			&bp_ss_params,
- 			false);
-@@ -171,7 +171,7 @@ static bool enable_spread_spectrum(
- 				bp_params.flags.EXTERNAL_SS = 1;
- 
- 			if (BP_RESULT_OK !=
--				dal_bios_parser_enable_spread_spectrum_on_ppll(
-+				clock_source->bios_parser->funcs->enable_spread_spectrum_on_ppll(
- 						clock_source->bios_parser,
- 						&bp_params,
- 						true))
-@@ -283,7 +283,7 @@ static bool program_pix_clk(
- 	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
- 					pll_settings->use_external_clk;
- 
--	if (dal_bios_parser_set_pixel_clock(clk_src->bios_parser,
-+	if (clk_src->bios_parser->funcs->set_pixel_clock(clk_src->bios_parser,
- 						&bp_pc_params) != BP_RESULT_OK)
- 		return false;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-index ce59228..0a0b516 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-@@ -79,7 +79,7 @@ static bool program_pix_clk(struct clock_source *clk_src,
- 	bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
- 	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
- 
--	if (dal_bios_parser_set_pixel_clock(clk_src->bios_parser,
-+	if (clk_src->bios_parser->funcs->set_pixel_clock(clk_src->bios_parser,
- 			&bp_pix_clk_params) == BP_RESULT_OK)
- 		return true;
- 
-@@ -162,7 +162,7 @@ static bool construct(
- 	/*Get Reference frequency, Input frequency range into PLL
- 	 * and Output frequency range of the PLL
- 	 * from ATOMBIOS Data table */
--	if (dal_bios_parser_get_firmware_info(
-+	if (vce_clk_src->base.bios_parser->funcs->get_firmware_info(
- 			vce_clk_src->base.bios_parser,
- 			&fw_info) != BP_RESULT_OK)
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-index ac27cd7..3a26312 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-@@ -23,8 +23,9 @@
-  */
- 
- #include "dal_services.h"
--#include "include/clock_source_types.h"
-+
- #include "include/bios_parser_interface.h"
-+#include "include/clock_source_types.h"
- #include "include/logger_interface.h"
- #include "ext_clock_source.h"
- 
-@@ -71,11 +72,11 @@ bool dal_ext_clock_source_program_pix_clk(
- 	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
- 	bp_pix_clk_params.dvo_config = pix_clk_params->dvo_cfg;
- 
--
--	if (dal_bios_parser_set_pixel_clock(
-+	if (clk_src->bios_parser->funcs->set_pixel_clock(
- 					clk_src->bios_parser,
- 					&bp_pix_clk_params) == BP_RESULT_OK)
- 		return true;
-+
- 	return false;
- 
- }
-@@ -108,11 +109,13 @@ bool dal_ext_clock_source_construct(
- 			SIGNAL_TYPE_DISPLAY_PORT_MST |
- 			SIGNAL_TYPE_EDP;
- 
-+
- 	/*Get External clock frequency from ATOMBIOS Data table */
--	if (dal_bios_parser_get_firmware_info(
-+	if (ext_clk_src->base.bios_parser->funcs->get_firmware_info(
- 			ext_clk_src->base.bios_parser,
- 			&fw_info) != BP_RESULT_OK)
- 		return false;
-+
- 	ext_clk_src->ext_clk_freq_khz = fw_info.
- 			external_clock_source_frequency_for_dp;
- 	return true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-index 8bb0304..3049842 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-@@ -40,7 +40,7 @@ bool dal_pll_clock_source_power_down_pll(
- 	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
- 
- 	/*Call ASICControl to process ATOMBIOS Exec table*/
--	bp_result = dal_bios_parser_set_pixel_clock(
-+	bp_result = clk_src->bios_parser->funcs->set_pixel_clock(
- 			clk_src->bios_parser,
- 			&bp_pixel_clock_params);
- 
-@@ -102,7 +102,7 @@ bool dal_pll_clock_source_adjust_pix_clk(
- 		display_pll_config = pix_clk_params->disp_pll_cfg;
- 	bp_adjust_pixel_clock_params.
- 		ss_enable = pix_clk_params->flags.ENABLE_SS;
--	bp_result = dal_bios_parser_adjust_pixel_clock(
-+	bp_result = pll_clk_src->base.bios_parser->funcs->adjust_pixel_clock(
- 			pll_clk_src->base.bios_parser,
- 			&bp_adjust_pixel_clock_params);
- 	if (bp_result == BP_RESULT_OK) {
-@@ -131,10 +131,11 @@ bool dal_pll_clock_source_construct(
- 			clk_src_init_data))
- 		return false;
- 
--	if (dal_bios_parser_get_firmware_info(
-+	if (pll_clk_src->base.bios_parser->funcs->get_firmware_info(
- 			pll_clk_src->base.bios_parser,
- 			&fw_info) != BP_RESULT_OK)
- 		return false;
-+
- 	pll_clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
- 
- 	return true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 317110e..a5ccb5e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -141,7 +141,7 @@ struct hw_sequencer_funcs {
- 	bool (*enable_display_power_gating)(
- 					struct dc_context *ctx,
- 					uint8_t controller_id,
--					struct bios_parser *bp,
-+					struct dc_bios *dcb,
- 					enum pipe_gating_control power_gating);
- 
- 	/* resource management and validation*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-index 25028b7..9665356 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-@@ -9,10 +9,12 @@
- #include "include/encoder_types.h"
- #include "include/bios_parser_interface.h"
- 
-+struct dc_bios;
-+
- struct stream_encoder {
- 	struct stream_encoder_funcs *funcs;
- 	struct dc_context *ctx;
--	struct bios_parser *bp;
-+	struct dc_bios *bp;
- 	enum engine_id id;
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-index e449db6..2851266 100644
---- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-@@ -36,7 +36,6 @@
- #include "asic_capability_types.h"
- 
- /* forward declaration */
--struct bios_parser;
- struct i2caux;
- struct adapter_service;
- 
-@@ -481,7 +480,7 @@ bool dal_adapter_service_get_i2c_info(
- 	struct graphics_object_i2c_info *i2c_info);
- 
- /* Get bios parser handler */
--struct bios_parser *dal_adapter_service_get_bios_parser(
-+struct dc_bios *dal_adapter_service_get_bios_parser(
- 	struct adapter_service *as);
- 
- /* Get i2c aux handler */
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_types.h b/drivers/gpu/drm/amd/dal/include/adapter_service_types.h
-index fb47ef3..4cb4b4b 100644
---- a/drivers/gpu/drm/amd/dal/include/adapter_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_types.h
-@@ -26,6 +26,7 @@
- #ifndef __DAL_ADAPTER_SERVICE_TYPES_H__
- #define __DAL_ADAPTER_SERVICE_TYPES_H__
- 
-+/* TODO: include signal_types.h and remove this enum */
- enum as_signal_type {
- 	AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
- 	AS_SIGNAL_TYPE_DVI,
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-index 77999fc..e4291b9 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -26,143 +26,25 @@
- #ifndef __DAL_BIOS_PARSER_INTERFACE_H__
- #define __DAL_BIOS_PARSER_INTERFACE_H__
- 
--#include "bios_parser_types.h"
--#include "adapter_service_types.h"
--#include "gpio_types.h"
-+#include "dc_bios_types.h"
- 
- struct adapter_service;
- struct bios_parser;
- 
--struct bp_gpio_cntl_info {
--	uint32_t id;
--	enum gpio_pin_output_state state;
--};
--
--enum bp_result {
--	BP_RESULT_OK = 0, /* There was no error */
--	BP_RESULT_BADINPUT, /*Bad input parameter */
--	BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
--	BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
--	BP_RESULT_NORECORD, /* Record can't be found */
--	BP_RESULT_FAILURE
--};
--
- struct bp_init_data {
- 	struct dc_context *ctx;
- 	uint8_t *bios;
- };
- 
--struct bios_parser *dal_bios_parser_create(
-+struct dc_bios *dal_bios_parser_create(
- 	struct bp_init_data *init,
- 	struct adapter_service *as);
--void dal_bios_parser_destroy(
--	struct bios_parser **bp);
--
--
--void dal_bios_parser_power_down(
--	struct bios_parser *bp);
--void dal_bios_parser_power_up(
--	struct bios_parser *bp);
- 
--uint8_t dal_bios_parser_get_encoders_number(
--	struct bios_parser *bp);
--uint32_t dal_bios_parser_get_oem_ddc_lines_number(
--	struct bios_parser *bp);
--struct graphics_object_id dal_bios_parser_get_encoder_id(
--	struct bios_parser *bp,
--	uint32_t i);
--struct graphics_object_id dal_bios_parser_get_connector_id(
--	struct bios_parser *bp,
--	uint8_t connector_index);
--uint32_t dal_bios_parser_get_src_number(
--	struct bios_parser *bp,
--	struct graphics_object_id id);
--uint32_t dal_bios_parser_get_dst_number(
--	struct bios_parser *bp,
--	struct graphics_object_id id);
--uint32_t dal_bios_parser_get_gpio_record(
--	struct bios_parser *bp,
--	struct graphics_object_id id,
--	struct bp_gpio_cntl_info *gpio_record,
--	uint32_t record_size);
--enum bp_result dal_bios_parser_get_src_obj(
--	struct bios_parser *bp,
--	struct graphics_object_id object_id, uint32_t index,
--	struct graphics_object_id *src_object_id);
--enum bp_result dal_bios_parser_get_dst_obj(
--	struct bios_parser *bp,
--	struct graphics_object_id object_id, uint32_t index,
--	struct graphics_object_id *dest_object_id);
--enum bp_result dal_bios_parser_get_i2c_info(
--	struct bios_parser *bp,
--	struct graphics_object_id id,
--	struct graphics_object_i2c_info *info);
--enum bp_result dal_bios_parser_get_oem_ddc_info(
--	struct bios_parser *bp,
--	uint32_t index,
--	struct graphics_object_i2c_info *info);
--enum bp_result dal_bios_parser_get_voltage_ddc_info(
--	struct bios_parser *bp,
--	uint32_t index,
--	struct graphics_object_i2c_info *info);
--enum bp_result dal_bios_parser_get_thermal_ddc_info(
--	struct bios_parser *bp,
--	uint32_t i2c_channel_id,
--	struct graphics_object_i2c_info *info);
--enum bp_result dal_bios_parser_get_hpd_info(
--	struct bios_parser *bp,
--	struct graphics_object_id id,
--	struct graphics_object_hpd_info *info);
--enum bp_result dal_bios_parser_get_device_tag(
--	struct bios_parser *bp,
--	struct graphics_object_id connector_object_id,
--	uint32_t device_tag_index,
--	struct connector_device_tag_info *info);
--enum bp_result dal_bios_parser_get_firmware_info(
--	struct bios_parser *bp,
--	struct firmware_info *info);
--enum bp_result dal_bios_parser_get_spread_spectrum_info(
--	struct bios_parser *bp,
--	enum as_signal_type signal,
--	uint32_t index,
--	struct spread_spectrum_info *ss_info);
--uint32_t dal_bios_parser_get_ss_entry_number(
--	struct bios_parser *bp,
--	enum as_signal_type signal);
--enum bp_result dal_bios_parser_get_embedded_panel_info(
--	struct bios_parser *bp,
--	struct embedded_panel_info *info);
--enum bp_result dal_bios_parser_enum_embedded_panel_patch_mode(
--	struct bios_parser *bp,
--	uint32_t index,
--	struct embedded_panel_patch_mode *mode);
--enum bp_result dal_bios_parser_get_gpio_pin_info(
--	struct bios_parser *bp,
--	uint32_t gpio_id,
--	struct gpio_pin_info *info);
--enum bp_result dal_bios_parser_get_embedded_panel_info(
--	struct bios_parser *bp,
--	struct embedded_panel_info *info);
--enum bp_result dal_bios_parser_get_gpio_pin_info(
--	struct bios_parser *bp,
--	uint32_t gpio_id,
--	struct gpio_pin_info *info);
--enum bp_result dal_bios_parser_get_faked_edid_len(
--	struct bios_parser *bp,
--	uint32_t *len);
--enum bp_result dal_bios_parser_get_faked_edid_buf(
--	struct bios_parser *bp,
--	uint8_t *buff,
--	uint32_t len);
--enum bp_result dal_bios_parser_get_encoder_cap_info(
--	struct bios_parser *bp,
--	struct graphics_object_id object_id,
--	struct bp_encoder_cap_info *info);
--enum bp_result dal_bios_parser_get_din_connector_info(
--	struct bios_parser *bp,
--	struct graphics_object_id id,
--	struct din_connector_info *info);
-+void dal_bios_parser_destroy(
-+	struct dc_bios **dcb);
- 
-+/*****************************************************************************/
-+/* Interfaces of BIOS Parser Helper */
- bool dal_bios_parser_is_lid_open(
- 	struct bios_parser *bp);
- bool dal_bios_parser_is_lid_status_changed(
-@@ -213,88 +95,4 @@ void dal_bios_parser_set_scratch_critical_state(
- void dal_bios_parser_set_scratch_acc_mode_change(
- 	struct bios_parser *bp);
- 
--bool dal_bios_parser_is_device_id_supported(
--	struct bios_parser *bp,
--	struct device_id id);
--
--/* COMMANDS */
--
--enum bp_result dal_bios_parser_encoder_control(
--	struct bios_parser *bp,
--	struct bp_encoder_control *cntl);
--enum bp_result dal_bios_parser_transmitter_control(
--	struct bios_parser *bp,
--	struct bp_transmitter_control *cntl);
--enum bp_result dal_bios_parser_crt_control(
--	struct bios_parser *bp,
--	enum engine_id engine_id,
--	bool enable,
--	uint32_t pixel_clock);
--enum bp_result dal_bios_parser_dvo_encoder_control(
--	struct bios_parser *bp,
--	struct bp_dvo_encoder_control *cntl);
--enum bp_result dal_bios_parser_enable_crtc(
--	struct bios_parser *bp,
--	enum controller_id id,
--	bool enable);
--enum bp_result dal_bios_parser_adjust_pixel_clock(
--	struct bios_parser *bp,
--	struct bp_adjust_pixel_clock_parameters *bp_params);
--enum bp_result dal_bios_parser_set_pixel_clock(
--	struct bios_parser *bp,
--	struct bp_pixel_clock_parameters *bp_params);
--enum bp_result dal_bios_parser_set_dce_clock(
--	struct bios_parser *bp,
--	struct bp_set_dce_clock_parameters *bp_params);
--enum bp_result dal_bios_parser_enable_spread_spectrum_on_ppll(
--	struct bios_parser *bp,
--	struct bp_spread_spectrum_parameters *bp_params,
--	bool enable);
--enum bp_result dal_bios_parser_program_crtc_timing(
--	struct bios_parser *bp,
--	struct bp_hw_crtc_timing_parameters *bp_params);
--enum bp_result dal_bios_parser_blank_crtc(
--	struct bios_parser *bp,
--	struct bp_blank_crtc_parameters *bp_params,
--	bool blank);
--enum bp_result dal_bios_parser_set_overscan(
--	struct bios_parser *bp,
--	struct bp_hw_crtc_overscan_parameters *bp_params);
--enum bp_result dal_bios_parser_crtc_source_select(
--	struct bios_parser *bp,
--	struct bp_crtc_source_select *bp_params);
--enum bp_result dal_bios_parser_program_display_engine_pll(
--	struct bios_parser *bp,
--	struct bp_pixel_clock_parameters *bp_params);
--enum bp_result dal_bios_parser_get_divider_for_target_display_clock(
--	struct bios_parser *bp,
--	struct bp_display_clock_parameters *bp_params);
--enum signal_type dal_bios_parser_dac_load_detect(
--	struct bios_parser *bp,
--	struct graphics_object_id encoder,
--	struct graphics_object_id connector,
--	enum signal_type display_signal);
--enum bp_result dal_bios_parser_enable_memory_requests(
--	struct bios_parser *bp,
--	enum controller_id controller_id,
--	bool enable);
--enum bp_result dal_bios_parser_external_encoder_control(
--	struct bios_parser *bp,
--	struct bp_external_encoder_control *cntl);
--enum bp_result dal_bios_parser_enable_disp_power_gating(
--	struct bios_parser *bp,
--	enum controller_id controller_id,
--	enum bp_pipe_control_action action);
--
--void dal_bios_parser_post_init(struct bios_parser *bp);
--
--/* Parse integrated BIOS info */
--struct integrated_info *dal_bios_parser_create_integrated_info(
--	struct bios_parser *bp);
--
--/* Destroy provided integrated info */
--void dal_bios_parser_destroy_integrated_info(struct dc_context *ctx, struct integrated_info **info);
--
--
--
--#endif
-+#endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index 4176f28..7b93997 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -28,7 +28,17 @@
- 
- #include "include/signal_types.h"
- #include "include/grph_object_ctrl_defs.h"
--#include "link_service_types.h"
-+#include "include/gpio_types.h"
-+#include "include/adapter_service_types.h" /* for as_signal_type */
-+
-+enum bp_result {
-+	BP_RESULT_OK = 0, /* There was no error */
-+	BP_RESULT_BADINPUT, /*Bad input parameter */
-+	BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
-+	BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
-+	BP_RESULT_NORECORD, /* Record can't be found */
-+	BP_RESULT_FAILURE
-+};
- 
- enum bp_encoder_control_action {
- 	/* direct VBIOS translation! Just to simplify the translation */
-@@ -337,4 +347,9 @@ struct bp_encoder_cap_info {
- 	uint32_t RESERVED:30;
- };
- 
--#endif
-+struct bp_gpio_cntl_info {
-+	uint32_t id;
-+	enum gpio_pin_output_state state;
-+};
-+
-+#endif /*__DAL_BIOS_PARSER_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-index 3f5f1ec..75dfbab 100644
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-@@ -28,6 +28,7 @@
- 
- #include "include/grph_csc_types.h"
- 
-+struct dc_bios;
- 
- /**
-  *  These parameters are required as input when doing blanking/Unblanking
-@@ -142,7 +143,7 @@ enum crtc_state {
- 
- struct timing_generator {
- 	struct timing_generator_funcs *funcs;
--	struct bios_parser *bp;
-+	struct dc_bios *bp;
- 	struct dc_context *ctx;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0693-drm-amd-dal-S3-implementation-using-atomic-commit.patch b/common/recipes-kernel/linux/files/0693-drm-amd-dal-S3-implementation-using-atomic-commit.patch
deleted file mode 100644
index 7a51dfd2..00000000
--- a/common/recipes-kernel/linux/files/0693-drm-amd-dal-S3-implementation-using-atomic-commit.patch
+++ /dev/null
@@ -1,268 +0,0 @@
-From 6b7df58f42c838b25452e13e26b054564d352730 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 12 Jan 2016 12:02:08 -0500
-Subject: [PATCH 0693/1110] drm/amd/dal: S3 implementation using atomic commit
-
-Allow suspend resume by reconstructing the drm_atomic_state on
-resume and calling atomic commit. This implementation works
-with display configurationas up to 3 displays, but cannot handle
-display swapping due to modelist not being properly updated.
-Modes in the mode list are only emptied during disconnect, the
-swap display during S3 use case never goes through a disconnect state
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 164 ++++++++++++++++++---
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  17 ++-
- 2 files changed, 151 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 0f281b6..6de5703 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -451,20 +451,6 @@ static int dm_set_powergating_state(void *handle,
- /* Prototypes of private functions */
- static int dm_early_init(void* handle);
- 
--static void detect_on_all_dc_links(struct amdgpu_display_manager *dm)
--{
--	uint32_t i;
--	const struct dc_link *dc_link;
--	struct dc_caps caps = { 0 };
--
--	dc_get_caps(dm->dc, &caps);
--
--	for (i = 0; i < caps.max_links; i++) {
--		dc_link = dc_get_link_at_index(dm->dc, i);
--		dc_link_detect(dc_link, false);
--	}
--}
--
- static void hotplug_notify_work_func(struct work_struct *work)
- {
- 	struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
-@@ -663,11 +649,78 @@ static int dm_hw_fini(void *handle)
- 	return 0;
- }
- 
-+static int dm_display_suspend(struct drm_device *ddev)
-+{
-+	struct drm_mode_config *config = &ddev->mode_config;
-+	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
-+	struct drm_atomic_state *state;
-+	struct drm_crtc *crtc;
-+	unsigned crtc_mask = 0;
-+	int ret = 0;
-+
-+	if (WARN_ON(!ctx))
-+		return 0;
-+
-+	lockdep_assert_held(&ctx->ww_ctx);
-+
-+	state = drm_atomic_state_alloc(ddev);
-+	if (WARN_ON(!state))
-+		return -ENOMEM;
-+
-+	state->acquire_ctx = ctx;
-+	state->allow_modeset = true;
-+
-+	/* Set all active crtcs to inactive, to turn off displays*/
-+	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
-+		struct drm_crtc_state *crtc_state =
-+			drm_atomic_get_crtc_state(state, crtc);
-+
-+		ret = PTR_ERR_OR_ZERO(crtc_state);
-+		if (ret)
-+			goto free;
-+
-+		if (!crtc_state->active)
-+			continue;
-+
-+		crtc_state->active = false;
-+		crtc_mask |= (1 << drm_crtc_index(crtc));
-+	}
-+
-+	if (crtc_mask) {
-+		ret = drm_atomic_commit(state);
-+
-+		/* In case of failure, revert everything we did*/
-+		if (!ret) {
-+			list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head)
-+				if (crtc_mask & (1 << drm_crtc_index(crtc)))
-+					crtc->state->active = true;
-+
-+			return ret;
-+		}
-+	}
-+
-+free:
-+	if (ret) {
-+		DRM_ERROR("Suspending crtc's failed with %i\n", ret);
-+		drm_atomic_state_free(state);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
- static int dm_suspend(void *handle)
- {
- 	struct amdgpu_device *adev = handle;
- 	struct amdgpu_display_manager *dm = &adev->dm;
--	struct drm_crtc *crtc;
-+	struct drm_device *ddev = adev->ddev;
-+	int ret = 0;
-+
-+	drm_modeset_lock_all(ddev);
-+	ret = dm_display_suspend(ddev);
-+	drm_modeset_unlock_all(ddev);
-+
-+	if (ret)
-+		goto fail;
- 
- 	dc_set_power_state(
- 		dm->dc,
-@@ -675,32 +728,95 @@ static int dm_suspend(void *handle)
- 		DC_VIDEO_POWER_SUSPEND);
- 
- 	amdgpu_dm_irq_suspend(adev);
-+fail:
-+	return ret;
-+}
-+
-+static int dm_display_resume(struct drm_device *ddev)
-+{
-+	int ret = 0;
-+	struct drm_connector *connector;
-+
-+	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
-+	struct drm_plane *plane;
-+	struct drm_crtc *crtc;
- 
--	list_for_each_entry(crtc, &dm->ddev->mode_config.crtc_list, head) {
--		crtc->mode.clock = 0;
-+	if (!state)
-+		return ENOMEM;
-+
-+	state->acquire_ctx = ddev->mode_config.acquire_ctx;
-+
-+	/* Construct an atomic state to restore previous display setting*/
-+	/* Attach crtcs to drm_atomic_state*/
-+	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
-+		struct drm_crtc_state *crtc_state =
-+			drm_atomic_get_crtc_state(state, crtc);
-+
-+		ret = PTR_ERR_OR_ZERO(crtc_state);
-+		if (ret)
-+			goto err;
-+
-+		/* force a restore */
-+		crtc_state->mode_changed = true;
- 	}
- 
--	return 0;
-+	/* Attach planes to drm_atomic_state*/
-+	list_for_each_entry(plane, &ddev->mode_config.plane_list, head) {
-+		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, plane));
-+		if (ret)
-+			goto err;
-+	}
-+
-+	/* Attach connectors to drm_atomic_state*/
-+	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
-+		ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, connector));
-+		if (ret)
-+			goto err;
-+	}
-+
-+	/* Call commit internally with the state we just constructed */
-+	ret = drm_atomic_commit(state);
-+	if (!ret)
-+		return 0;
-+
-+err:
-+	DRM_ERROR("Restoring old state failed with %i\n", ret);
-+	drm_atomic_state_free(state);
-+
-+	return ret;
- }
- 
- static int dm_resume(void *handle)
- {
--	int ret = 0;
- 	struct amdgpu_device *adev = handle;
-+	struct drm_device *ddev = adev->ddev;
- 	struct amdgpu_display_manager *dm = &adev->dm;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector *connector;
-+	int ret = 0;
- 
-+	/* power on hardware */
- 	dc_set_power_state(
- 		dm->dc,
- 		DC_ACPI_CM_POWER_STATE_D0,
- 		DC_VIDEO_POWER_ON);
- 
--	amdgpu_dm_irq_resume(adev);
--
-+	/* program HPD filter*/
- 	dc_resume(dm->dc);
-+	/* resume IRQ */
-+	amdgpu_dm_irq_resume(adev);
-+	/* Do detection*/
-+	list_for_each_entry(connector,
-+			&ddev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		dc_link_detect(aconnector->dc_link, false);
-+		aconnector->dc_sink = NULL;
-+		amdgpu_dm_update_connector_after_detect(aconnector);
-+	}
- 
--	detect_on_all_dc_links(dm);
--
--	drm_mode_config_reset(adev->ddev);
-+	drm_modeset_lock_all(ddev);
-+	ret = dm_display_resume(ddev);
-+	drm_modeset_unlock_all(ddev);
- 
- 	return ret;
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 7df2d28..04044ff 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2171,6 +2171,8 @@ int amdgpu_dm_atomic_commit(
- 				 * during resume sequence ended
- 				 */
- 				new_state->planes_changed = false;
-+				DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n",
-+						__func__, acrtc->base.base.id);
- 				break;
- 			}
- 
-@@ -2458,13 +2460,16 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 					aconnector,
- 					&mode);
- 
-+			/*
-+			 * we can have no target on ACTION_SET if a display
-+			 * was disconnected during S3, in this case it not and
-+			 * error, the OS will be updated after detection, and
-+			 * do the right thing on next atomic commit
-+			 */
- 			if (!new_target) {
--				DRM_ERROR(
--					"%s: Can't create target for crtc %d\n",
--					__func__,
--					acrtc->crtc_id);
--				goto connector_not_found;
--
-+				DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n",
-+						__func__, acrtc->base.base.id);
-+				break;
- 			}
- 
- 			new_targets[new_target_count] = new_target;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0694-drm-amd-dal-Fixed-active-dongle-bug.patch b/common/recipes-kernel/linux/files/0694-drm-amd-dal-Fixed-active-dongle-bug.patch
deleted file mode 100644
index 4f96a03a..00000000
--- a/common/recipes-kernel/linux/files/0694-drm-amd-dal-Fixed-active-dongle-bug.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 34af1a5d58c45ab82c2a01034843ac81b6838349 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Thu, 14 Jan 2016 11:17:10 -0500
-Subject: [PATCH 0694/1110] drm/amd/dal: Fixed active dongle bug.
-
-In case of active dongle downstream unplug,
-dc_link_detect doesn't handle correctly.
-Add connection type check after detect_dp.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index b034c2f..46132f2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -608,6 +608,10 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 				&converter_disable_audio,
- 				&audio_support, boot);
- 
-+			/* Active dongle downstream unplug */
-+			if (link->public.type == dc_connection_none)
-+				return true;
-+
- 			if (link->public.type == dc_connection_mst_branch)
- 				return false;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0695-drm-amd-dal-Re-enable-interrupt-after-hotplug-notify.patch b/common/recipes-kernel/linux/files/0695-drm-amd-dal-Re-enable-interrupt-after-hotplug-notify.patch
deleted file mode 100644
index 17c3906d..00000000
--- a/common/recipes-kernel/linux/files/0695-drm-amd-dal-Re-enable-interrupt-after-hotplug-notify.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From d3f85dbd65bbabe5f225a9ffe0c8715389392900 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 14 Jan 2016 17:41:51 -0500
-Subject: [PATCH 0695/1110] drm/amd/dal: Re-enable interrupt after hotplug
- notify
-
-On S3 resume, re-enable interrupt after hotplug notify to guarantee
-OS knows about a disconnect that happend during S3 before any HPD
-can fire and change the connection status of the connector. This
-Fixes pageflip issues on S3 resume observed when multiple displays
-are connected.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 6de5703..9879512 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -801,10 +801,6 @@ static int dm_resume(void *handle)
- 		DC_ACPI_CM_POWER_STATE_D0,
- 		DC_VIDEO_POWER_ON);
- 
--	/* program HPD filter*/
--	dc_resume(dm->dc);
--	/* resume IRQ */
--	amdgpu_dm_irq_resume(adev);
- 	/* Do detection*/
- 	list_for_each_entry(connector,
- 			&ddev->mode_config.connector_list, head) {
-@@ -814,10 +810,18 @@ static int dm_resume(void *handle)
- 		amdgpu_dm_update_connector_after_detect(aconnector);
- 	}
- 
-+
- 	drm_modeset_lock_all(ddev);
- 	ret = dm_display_resume(ddev);
- 	drm_modeset_unlock_all(ddev);
- 
-+	drm_kms_helper_hotplug_event(ddev);
-+
-+	/* program HPD filter*/
-+	dc_resume(dm->dc);
-+	/* resume IRQ */
-+	amdgpu_dm_irq_resume(adev);
-+
- 	return ret;
- }
- const struct amd_ip_funcs amdgpu_dm_funcs = {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0696-drm-amd-dal-Fix-waiting-on-mmDP_MSE_SAT_UPDATE-to-co.patch b/common/recipes-kernel/linux/files/0696-drm-amd-dal-Fix-waiting-on-mmDP_MSE_SAT_UPDATE-to-co.patch
deleted file mode 100644
index 44a63863..00000000
--- a/common/recipes-kernel/linux/files/0696-drm-amd-dal-Fix-waiting-on-mmDP_MSE_SAT_UPDATE-to-co.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From bc97aaf45e3ff5ec9c9532775bae5faeb3d01a46 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Thu, 14 Jan 2016 18:23:43 -0500
-Subject: [PATCH 0696/1110] drm/amd/dal: Fix waiting on mmDP_MSE_SAT_UPDATE to
- correct form.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 73ba7b8..0f0ecfe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1725,6 +1725,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value0 = 0;
- 	uint32_t value1 = 0;
-+	uint32_t value2 = 0;
- 	uint32_t slots = 0;
- 	uint32_t src = 0;
- 	uint32_t retries = 0;
-@@ -1851,10 +1852,14 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		value1 = get_reg_field_value(
- 				value0,
- 				DP_MSE_SAT_UPDATE,
-+				DP_MSE_SAT_UPDATE);
-+		value2 = get_reg_field_value(
-+				value0,
-+				DP_MSE_SAT_UPDATE,
- 				DP_MSE_16_MTP_KEEPOUT);
- 
- 		/* bit field DP_MSE_SAT_UPDATE is set to 1 already */
--		if (value1)
-+		if (!value1 && !value2)
- 			break;
- 		++retries;
- 	} while (retries < DP_MST_UPDATE_MAX_RETRY);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0697-drm-amd-dal-Add-simple-logger-of-DPCD-tx-rx-traffic.patch b/common/recipes-kernel/linux/files/0697-drm-amd-dal-Add-simple-logger-of-DPCD-tx-rx-traffic.patch
deleted file mode 100644
index a8dacb2a..00000000
--- a/common/recipes-kernel/linux/files/0697-drm-amd-dal-Add-simple-logger-of-DPCD-tx-rx-traffic.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 0df59f35855ec8c33bfe7e3ab6a9b592d6e20860 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Sat, 16 Jan 2016 00:18:36 -0500
-Subject: [PATCH 0697/1110] drm/amd/dal: Add simple logger of DPCD tx/rx
- traffic.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 55 +++++++++++++++++++++-
- 1 file changed, 53 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index aeab396..fe5e366 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -31,16 +31,59 @@
- #include "dc.h"
- #include "dc_helpers.h"
- 
-+/* #define TRACE_DPCD */
-+
-+#ifdef TRACE_DPCD
-+#define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
-+
-+static inline char *side_band_msg_type_to_str(uint32_t address)
-+{
-+	static char str[10] = {0};
-+
-+	if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
-+		strcpy(str, "DOWN_REQ");
-+	else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
-+		strcpy(str, "UP_REP");
-+	else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
-+		strcpy(str, "DOWN_REP");
-+	else
-+		strcpy(str, "UP_REQ");
-+
-+	return str;
-+}
-+
-+void log_dpcd(uint8_t type,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size,
-+		bool res)
-+{
-+	DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
-+			(type == DP_AUX_NATIVE_READ) ||
-+			(type == DP_AUX_I2C_READ) ?
-+					"Read" : "Write",
-+			address,
-+			SIDE_BAND_MSG(address) ?
-+					side_band_msg_type_to_str(address) : "Nop",
-+			res ? "OK" : "Fail");
-+
-+	if (res) {
-+		print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
-+	}
-+}
-+#endif
-+
- static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
- {
- 	struct pci_dev *pdev = to_pci_dev(aux->dev);
- 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
- 	struct amdgpu_device *adev = drm_dev->dev_private;
- 	struct dc *dc = adev->dm.dc;
-+	bool res;
- 
- 	switch (msg->request) {
- 	case DP_AUX_NATIVE_READ:
--		dc_read_dpcd(
-+		res = dc_read_dpcd(
- 			dc,
- 			TO_DM_AUX(aux)->link_index,
- 			msg->address,
-@@ -48,7 +91,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 			msg->size);
- 		break;
- 	case DP_AUX_NATIVE_WRITE:
--		dc_write_dpcd(
-+		res = dc_write_dpcd(
- 			dc,
- 			TO_DM_AUX(aux)->link_index,
- 			msg->address,
-@@ -59,6 +102,14 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 		return 0;
- 	}
- 
-+#ifdef TRACE_DPCD
-+	log_dpcd(msg->request,
-+			msg->address,
-+			msg->buffer,
-+			msg->size,
-+			res);
-+#endif
-+
- 	return msg->size;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0698-drm-amd-dal-Refactor-mem_input.patch b/common/recipes-kernel/linux/files/0698-drm-amd-dal-Refactor-mem_input.patch
deleted file mode 100644
index 7e02ef1a..00000000
--- a/common/recipes-kernel/linux/files/0698-drm-amd-dal-Refactor-mem_input.patch
+++ /dev/null
@@ -1,387 +0,0 @@
-From c6ee9d1602d2f0c99e7904d938c70a1b712ab0de Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Mon, 18 Jan 2016 16:47:07 -0500
-Subject: [PATCH 0698/1110] drm/amd/dal: Refactor mem_input.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 15 +++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 77 ++++++++++------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |  8 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 63 ++++++++++++++++--
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |  3 +
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         | 29 ++++++++
- 6 files changed, 135 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index fbcd799..14ad0cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -826,7 +826,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	}
- 
- 	/*TODO: mst support - use total stream count*/
--	dce110_mem_input_allocate_dmif_buffer(
-+	stream->mi->funcs->mem_input_allocate_dmif_buffer(
- 					stream->mi,
- 					&stream->public.timing,
- 					context->target_count);
-@@ -1156,7 +1156,7 @@ static void set_displaymarks(
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			dce110_mem_input_program_display_marks(
-+			stream->mi->funcs->mem_input_program_display_marks(
- 				stream->mi,
- 				context->bw_results
- 				.nbp_state_change_wm_ns[total_streams],
-@@ -1185,7 +1185,8 @@ static void set_safe_displaymarks(struct validate_context *context)
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			dce110_mem_input_program_safe_display_marks(stream->mi);
-+			stream->mi->funcs->mem_input_program_safe_display_marks(
-+					stream->mi);
- 		}
- 	}
- }
-@@ -1510,7 +1511,7 @@ static bool set_plane_config(
- 			path_mode->mode.timing.pixel_encoding);
- #endif
- 
--	dce110_mem_input_program_surface_config(
-+	mi->funcs->mem_input_program_surface_config(
- 			mi,
- 			surface->public.format,
- 			&surface->public.tiling_info,
-@@ -1546,7 +1547,8 @@ static bool update_plane_address(
- 		PIPE_LOCK_CONTROL_SURFACE,
- 		true);
- 
--	if (false == dce110_mem_input_program_surface_flip_and_addr(
-+	if (false ==
-+		core_stream->mi->funcs->mem_input_program_surface_flip_and_addr(
- 		mi, &surface->public.address, surface->public.flip_immediate))
- 		return false;
- 
-@@ -1578,7 +1580,8 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 
- 	stream->tg->funcs->set_blank(stream->tg, true);
- 	stream->tg->funcs->disable_crtc(stream->tg);
--	dce110_mem_input_deallocate_dmif_buffer(stream->mi, context->target_count);
-+	stream->mi->funcs->mem_input_deallocate_dmif_buffer(
-+			stream->mi, context->target_count);
- 	dce110_transform_set_scaler_bypass(stream->xfm);
- 	disable_stereo_mixer(stream->ctx);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index ab2241d..5c76d15 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -43,26 +43,6 @@
- #define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
- #define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
- 
--static const struct dce110_mem_input_reg_offsets reg_offsets[] =  {
--{
--	.dcp = 0,
--	.dmif = 0,
--	.pipe = 0,
--},
--{
--	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
--				- mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
--	.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL - mmPIPE0_DMIF_BUFFER_CONTROL),
--},
--{
--	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
--				- mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL),
--	.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL - mmPIPE0_DMIF_BUFFER_CONTROL),
--}
--};
--
- static void set_flip_control(
- 	struct dce110_mem_input *mem_input110,
- 	bool immediate)
-@@ -445,6 +425,19 @@ static void program_pixel_format(
- 	}
- }
- 
-+static void wait_for_no_surface_update_pending(
-+				struct dce110_mem_input *mem_input110)
-+{
-+	uint32_t value;
-+
-+	do  {
-+		value = dal_read_reg(mem_input110->base.ctx,
-+				DCP_REG(mmGRPH_UPDATE));
-+
-+	} while (get_reg_field_value(value, GRPH_UPDATE,
-+			GRPH_SURFACE_UPDATE_PENDING));
-+}
-+
- bool dce110_mem_input_program_surface_flip_and_addr(
- 	struct mem_input *mem_input,
- 	const struct dc_plane_address *address,
-@@ -456,6 +449,9 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- 	program_addr(mem_input110,
- 		address);
- 
-+	if (flip_immediate)
-+		wait_for_no_surface_update_pending(mem_input110);
-+
- 	return true;
- }
- 
-@@ -922,6 +918,19 @@ void dce110_mem_input_deallocate_dmif_buffer(
- 	dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
- }
- 
-+static struct mem_input_funcs dce110_mem_input_funcs = {
-+	.mem_input_program_safe_display_marks =
-+			dce110_mem_input_program_safe_display_marks,
-+	.mem_input_program_display_marks =
-+			dce110_mem_input_program_display_marks,
-+	.mem_input_allocate_dmif_buffer = dce110_mem_input_allocate_dmif_buffer,
-+	.mem_input_deallocate_dmif_buffer =
-+			dce110_mem_input_deallocate_dmif_buffer,
-+	.mem_input_program_surface_flip_and_addr =
-+			dce110_mem_input_program_surface_flip_and_addr,
-+	.mem_input_program_surface_config =
-+			dce110_mem_input_program_surface_config,
-+};
- /*****************************************/
- /* Constructor, Destructor               */
- /*****************************************/
-@@ -929,16 +938,15 @@ void dce110_mem_input_deallocate_dmif_buffer(
- bool dce110_mem_input_construct(
- 	struct dce110_mem_input *mem_input110,
- 	struct dc_context *ctx,
--	uint32_t inst)
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets)
- {
--	if (inst >= ARRAY_SIZE(reg_offsets))
--		return false;
--
-+	mem_input110->base.funcs = &dce110_mem_input_funcs;
- 	mem_input110->base.ctx = ctx;
- 
- 	mem_input110->base.inst = inst;
- 
--	mem_input110->offsets = reg_offsets[inst];
-+	mem_input110->offsets = *offsets;
- 
- 	mem_input110->supported_stutter_mode = 0;
- 	dal_adapter_service_get_feature_value(FEATURE_STUTTER_MODE,
-@@ -953,22 +961,3 @@ void dce110_mem_input_destroy(struct mem_input **mem_input)
- 	dc_service_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
- 	*mem_input = NULL;
- }
--
--struct mem_input *dce110_mem_input_create(
--	struct dc_context *ctx,
--	uint32_t inst)
--{
--	struct dce110_mem_input *mem_input110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_mem_input));
--
--	if (!mem_input110)
--		return NULL;
--
--	if (dce110_mem_input_construct(mem_input110,
--			ctx, inst))
--		return &mem_input110->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, mem_input110);
--	return NULL;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 7392750..997070b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -42,11 +42,11 @@ struct dce110_mem_input {
- 	uint32_t supported_stutter_mode;
- };
- 
--struct mem_input *dce110_mem_input_create(
-+bool dce110_mem_input_construct(
-+	struct dce110_mem_input *mem_input110,
- 	struct dc_context *ctx,
--	uint32_t inst);
--
--void dce110_mem_input_destroy(struct mem_input **mem_input);
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets);
- 
- /*
-  * dce110_mem_input_program_display_marks
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 565f9cb..49c70fc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -80,6 +80,29 @@ static const struct dce110_stream_enc_offsets dce110_str_enc_offsets[] = {
- 	}
- };
- 
-+static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
-+	{
-+		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	}
-+};
- 
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
-@@ -121,6 +144,26 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 	return NULL;
- }
- 
-+static struct mem_input *dce110_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offset)
-+{
-+	struct dce110_mem_input *mem_input110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_mem_input));
-+
-+	if (!mem_input110)
-+		return NULL;
-+
-+	if (dce110_mem_input_construct(mem_input110,
-+			ctx, inst, offset))
-+		return &mem_input110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, mem_input110);
-+	return NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -198,7 +241,8 @@ bool dce110_construct_resource_pool(
- 			goto controller_create_fail;
- 		}
- 
--		pool->mis[i] = dce110_mem_input_create(ctx, i);
-+		pool->mis[i] = dce110_mem_input_create(ctx, i,
-+				&dce110_mi_reg_offsets[i]);
- 		if (pool->mis[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-@@ -298,11 +342,15 @@ controller_create_fail:
- 		if (pool->ipps[i] != NULL)
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
--		if (pool->mis[i] != NULL)
--			dce110_mem_input_destroy(&pool->mis[i]);
-+		if (pool->mis[i] != NULL) {
-+			dc_service_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dc_service_free(pool->timing_generators[i]->ctx,
-+				DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
-@@ -336,8 +384,11 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 		if (pool->ipps[i] != NULL)
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
--		if (pool->mis[i] != NULL)
--			dce110_mem_input_destroy(&pool->mis[i]);
-+		if (pool->mis[i] != NULL) {
-+			dc_service_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
- 			dc_service_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index c787530..a84ab8b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -53,6 +53,9 @@
- struct dce110_timing_generator_offsets {
- 	uint32_t crtc;
- 	uint32_t dcp;
-+
-+	/* DCE80 use only */
-+	uint32_t dmif;
- };
- 
- struct dce110_timing_generator {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 458e7b5..0d34248 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -30,10 +30,39 @@
- #include "dc.h"
- 
- struct mem_input {
-+	struct mem_input_funcs *funcs;
- 	struct dc_context *ctx;
- 	uint32_t inst;
- };
- 
-+struct mem_input_funcs {
-+	void (*mem_input_program_safe_display_marks)(struct mem_input *mi);
-+	void (*mem_input_program_display_marks)(
-+		struct mem_input *mem_input,
-+		struct bw_watermarks nbp,
-+		struct bw_watermarks stutter,
-+		struct bw_watermarks urgent,
-+		uint32_t h_total,
-+		uint32_t pixel_clk_in_khz,
-+		uint32_t pstate_blackout_duration_ns);
-+	void (*mem_input_allocate_dmif_buffer)(
-+			struct mem_input *mem_input,
-+			struct dc_crtc_timing *timing,
-+			uint32_t paths_num);
-+	void (*mem_input_deallocate_dmif_buffer)(
-+		struct mem_input *mem_input, uint32_t paths_num);
-+	bool (*mem_input_program_surface_flip_and_addr)(
-+		struct mem_input *mem_input,
-+		const struct dc_plane_address *address,
-+		bool flip_immediate);
-+	bool (*mem_input_program_surface_config)(
-+		struct mem_input *mem_input,
-+		enum surface_pixel_format format,
-+		union plane_tiling_info *tiling_info,
-+		union plane_size *plane_size,
-+		enum dc_rotation_angle rotation);
-+};
-+
- enum stutter_mode_type {
- 	STUTTER_MODE_LEGACY = 0X00000001,
- 	STUTTER_MODE_ENHANCED = 0X00000002,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0699-drm-amd-dal-restyle-transorm-remove-redundant-code.patch b/common/recipes-kernel/linux/files/0699-drm-amd-dal-restyle-transorm-remove-redundant-code.patch
deleted file mode 100644
index da360f38..00000000
--- a/common/recipes-kernel/linux/files/0699-drm-amd-dal-restyle-transorm-remove-redundant-code.patch
+++ /dev/null
@@ -1,344 +0,0 @@
-From 5b752785d79aa0a7a87d1a314ec189ed49f45adf Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 18 Jan 2016 16:57:50 -0500
-Subject: [PATCH 0699/1110] drm/amd/dal: restyle transorm, remove redundant
- code
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  3 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 10 ++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 49 +++++++++++++++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   | 68 +++++++---------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |  9 +--
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         | 34 +++++++++++
- 6 files changed, 111 insertions(+), 62 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 841e02e..737ed87 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -39,6 +39,7 @@
- #include "include/irq_service_interface.h"
- #include "bandwidth_calcs.h"
- #include "include/irq_service_interface.h"
-+#include "inc/transform.h"
- 
- #include "link_hwss.h"
- #include "link_encoder.h"
-@@ -157,7 +158,7 @@ static void init_hw(struct dc *dc)
- 				dc->ctx, i, bp,
- 				PIPE_GATING_CONTROL_DISABLE);
- 
--		dc->hwss.transform_power_up(xfm);
-+		xfm->funcs->transform_power_up(xfm);
- 		dc->hwss.enable_display_pipe_clock_gating(
- 			dc->ctx,
- 			true);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 14ad0cd..612afe5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1332,7 +1332,7 @@ static bool setup_line_buffer_pixel_depth(
- 	struct timing_generator *tg = stream->tg;
- 	struct transform *xfm = stream->xfm;
- 
--	if (!dce110_transform_get_current_pixel_storage_depth(
-+	if (!xfm->funcs->transform_get_current_pixel_storage_depth(
- 		xfm,
- 		&current_depth))
- 		return false;
-@@ -1341,7 +1341,7 @@ static bool setup_line_buffer_pixel_depth(
- 		if (blank)
- 			tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
- 
--		return dce110_transform_set_pixel_storage_depth(xfm, depth);
-+		return xfm->funcs->transform_set_pixel_storage_depth(xfm, depth);
- 	}
- 
- 	return false;
-@@ -1426,9 +1426,9 @@ static void program_scaler(
- 
- 	tg->funcs->set_overscan_blank_color(tg, surface->public.colorimetry.color_space);
- 
--	dce110_transform_set_scaler(xfm, &scaler_data);
-+	xfm->funcs->transform_set_scaler(xfm, &scaler_data);
- 
--	dce110_transform_update_viewport(
-+	xfm->funcs->transform_update_viewport(
- 			xfm,
- 			&scaler_data.viewport,
- 			false);
-@@ -1582,7 +1582,7 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 	stream->tg->funcs->disable_crtc(stream->tg);
- 	stream->mi->funcs->mem_input_deallocate_dmif_buffer(
- 			stream->mi, context->target_count);
--	dce110_transform_set_scaler_bypass(stream->xfm);
-+	stream->xfm->funcs->transform_set_scaler_bypass(stream->xfm);
- 	disable_stereo_mixer(stream->ctx);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
- 	dce110_enable_display_power_gating(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 49c70fc..4c85dd1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -104,6 +104,25 @@ static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
- 	}
- };
- 
-+static const struct dce110_transform_reg_offsets dce110_xfm_offsets[] = {
-+{
-+	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL0_SCL_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL0_SCL_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL0_SCL_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+}
-+};
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -164,6 +183,31 @@ static struct mem_input *dce110_mem_input_create(
- 	return NULL;
- }
- 
-+static void dce110_transform_destroy(struct transform **xfm)
-+{
-+	dc_service_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce110_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_transform_reg_offsets *offsets)
-+{
-+	struct dce110_transform *transform =
-+		dc_service_alloc(ctx, sizeof(struct dce110_transform));
-+
-+	if (!transform)
-+		return NULL;
-+
-+	if (dce110_transform_construct(transform, ctx, inst, offsets))
-+		return &transform->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, transform);
-+	return NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -258,14 +302,15 @@ bool dce110_construct_resource_pool(
- 			goto controller_create_fail;
- 		}
- 
--		pool->transforms[i] = dce110_transform_create(ctx, i);
-+		pool->transforms[i] = dce110_transform_create(
-+					ctx, i, &dce110_xfm_offsets[i]);
- 		if (pool->transforms[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
- 				"DC: failed to create transform!\n");
- 			goto controller_create_fail;
- 		}
--		dce110_transform_set_scaler_filter(
-+		pool->transforms[i]->funcs->transform_set_scaler_filter(
- 				pool->transforms[i],
- 				pool->scaler_filter);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-index a7648e5..5a87ded 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -39,23 +39,23 @@
- #include "dce110_transform.h"
- #include "dce110_transform_bit_depth.h"
- 
--static const struct dce110_transform_reg_offsets reg_offsets[] = {
--{
--	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL0_SCL_CONTROL),
--	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
--},
--{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL0_SCL_CONTROL),
--	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
--},
--{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL0_SCL_CONTROL),
--	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
--}
-+static struct transform_funcs dce110_transform_funcs = {
-+	.transform_power_up =
-+		dce110_transform_power_up,
-+	.transform_set_scaler =
-+		dce110_transform_set_scaler,
-+	.transform_set_scaler_bypass =
-+		dce110_transform_set_scaler_bypass,
-+	.transform_update_viewport =
-+		dce110_transform_update_viewport,
-+	.transform_set_scaler_filter =
-+		dce110_transform_set_scaler_filter,
-+	.transform_set_gamut_remap =
-+		dce110_transform_set_gamut_remap,
-+	.transform_set_pixel_storage_depth =
-+		dce110_transform_set_pixel_storage_depth,
-+	.transform_get_current_pixel_storage_depth =
-+		dce110_transform_get_current_pixel_storage_depth
- };
- 
- /*****************************************/
-@@ -65,16 +65,15 @@ static const struct dce110_transform_reg_offsets reg_offsets[] = {
- bool dce110_transform_construct(
- 	struct dce110_transform *xfm110,
- 	struct dc_context *ctx,
--	uint32_t inst)
-+	uint32_t inst,
-+	const struct dce110_transform_reg_offsets *reg_offsets)
- {
--	if (inst >= ARRAY_SIZE(reg_offsets))
--		return false;
--
- 	xfm110->base.ctx = ctx;
- 
- 	xfm110->base.inst = inst;
-+	xfm110->base.funcs = &dce110_transform_funcs;
- 
--	xfm110->offsets = reg_offsets[inst];
-+	xfm110->offsets = *reg_offsets;
- 
- 	xfm110->lb_pixel_depth_supported =
- 			LB_PIXEL_DEPTH_18BPP |
-@@ -84,31 +83,6 @@ bool dce110_transform_construct(
- 	return true;
- }
- 
--void dce110_transform_destroy(struct transform **xfm)
--{
--	dc_service_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
--	*xfm = NULL;
--}
--
--struct transform *dce110_transform_create(
--	struct dc_context *ctx,
--	uint32_t inst)
--{
--	struct dce110_transform *transform =
--		dc_service_alloc(ctx, sizeof(struct dce110_transform));
--
--	if (!transform)
--		return NULL;
--
--	if (dce110_transform_construct(transform,
--			ctx, inst))
--		return &transform->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, transform);
--	return NULL;
--}
--
- bool dce110_transform_power_up(struct transform *xfm)
- {
- 	return dce110_transform_power_up_line_buffer(xfm);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index edf016c..229f588 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -47,13 +47,8 @@ struct dce110_transform {
- 
- bool dce110_transform_construct(struct dce110_transform *xfm110,
- 	struct dc_context *ctx,
--	uint32_t inst);
--
--void dce110_transform_destroy(struct transform **xfm);
--
--struct transform *dce110_transform_create(
--	struct dc_context *ctx,
--	uint32_t inst);
-+	uint32_t inst,
-+	const struct dce110_transform_reg_offsets *reg_offsets);
- 
- bool dce110_transform_power_up(struct transform *xfm);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 8e111ce..7b882ec 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -27,6 +27,7 @@
- #define __DAL_TRANSFORM_H__
- 
- #include "include/scaler_types.h"
-+#include "include/grph_csc_types.h"
- #include "calcs/scaler_filter.h"
- #include "grph_object_id.h"
- 
-@@ -37,11 +38,13 @@ enum scaling_type {
- };
- 
- struct transform {
-+	struct transform_funcs *funcs;
- 	struct dc_context *ctx;
- 	uint32_t inst;
- 	struct scaler_filter *filter;
- };
- 
-+
- struct scaler_taps_and_ratio {
- 	uint32_t h_tap;
- 	uint32_t v_tap;
-@@ -78,4 +81,35 @@ enum lb_pixel_depth {
- 	LB_PIXEL_DEPTH_36BPP = 8
- };
- 
-+struct transform_funcs {
-+	bool (*transform_power_up)(struct transform *xfm);
-+
-+	bool (*transform_set_scaler)(
-+		struct transform *xfm,
-+		const struct scaler_data *data);
-+
-+	void (*transform_set_scaler_bypass)(struct transform *xfm);
-+
-+	bool (*transform_update_viewport)(
-+		struct transform *xfm,
-+		const struct rect *view_port,
-+		bool is_fbc_attached);
-+
-+	void (*transform_set_scaler_filter)(
-+		struct transform *xfm,
-+		struct scaler_filter *filter);
-+
-+	void (*transform_set_gamut_remap)(
-+		struct transform *xfm,
-+		const struct grph_csc_adjustment *adjust);
-+
-+	bool (*transform_set_pixel_storage_depth)(
-+		struct transform *xfm,
-+		enum lb_pixel_depth depth);
-+
-+	bool (*transform_get_current_pixel_storage_depth)(
-+		struct transform *xfm,
-+		enum lb_pixel_depth *depth);
-+};
-+
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0700-drm-amd-dal-added-dc_link_add_sink-interface-for-man.patch b/common/recipes-kernel/linux/files/0700-drm-amd-dal-added-dc_link_add_sink-interface-for-man.patch
deleted file mode 100644
index 606f1761..00000000
--- a/common/recipes-kernel/linux/files/0700-drm-amd-dal-added-dc_link_add_sink-interface-for-man.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 348ab42bdeacf933ca78f92203acebb3b7dadb33 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 19 Jan 2016 15:08:38 -0500
-Subject: [PATCH 0700/1110] drm/amd/dal: added dc_link_add_sink interface for
- manually adding sinks
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 11 +++++++++++
- drivers/gpu/drm/amd/dal/dc/dc.h      |  2 ++
- 2 files changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 737ed87..4e87da5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -861,6 +861,17 @@ bool dc_link_add_remote_sink(const struct dc_link *link, struct dc_sink *sink)
- 	return true;
- }
- 
-+void dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
-+{
-+	struct core_link *core_link = DC_LINK_TO_LINK(link);
-+	struct dc_link *dc_link = &core_link->public;
-+
-+	dc_link->local_sink = sink;
-+	dc_link->sink_count = 1;
-+	if (sink->sink_signal == SIGNAL_TYPE_VIRTUAL
-+		&& link->connector_signal == SIGNAL_TYPE_VIRTUAL)
-+		dc_link->type = dc_connection_single;
-+}
- 
- void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 341c968..c541ecf 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -317,6 +317,8 @@ void dc_link_remove_remote_sink(
- 	const struct dc_link *link,
- 	const struct dc_sink *sink);
- 
-+/* Used by diagnostics for virtual link at the moment */
-+void dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink);
- 
- /*******************************************************************************
-  * Sink Interfaces - A sink corresponds to a display output device
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0701-drm-amd-dal-xfm-register-naming-refactor.patch b/common/recipes-kernel/linux/files/0701-drm-amd-dal-xfm-register-naming-refactor.patch
deleted file mode 100644
index ea228e67..00000000
--- a/common/recipes-kernel/linux/files/0701-drm-amd-dal-xfm-register-naming-refactor.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From d591b19ba73dbfb889d72c37bb3df8525fdff091 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 19 Jan 2016 15:42:10 -0500
-Subject: [PATCH 0701/1110] drm/amd/dal: xfm register naming refactor
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 24 +++++++++++-----------
- 1 file changed, 12 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 4c85dd1..09f245c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -106,20 +106,20 @@ static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
- 
- static const struct dce110_transform_reg_offsets dce110_xfm_offsets[] = {
- {
--	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL0_SCL_CONTROL),
--	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
- },
--{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL0_SCL_CONTROL),
--	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
- },
--{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL0_SCL_CONTROL),
--	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB0_LB_DATA_FORMAT),
-+{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
- }
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0702-drm-amd-dal-remove-dce_base-duplicates-dc-core.patch b/common/recipes-kernel/linux/files/0702-drm-amd-dal-remove-dce_base-duplicates-dc-core.patch
deleted file mode 100644
index 31dc1573..00000000
--- a/common/recipes-kernel/linux/files/0702-drm-amd-dal-remove-dce_base-duplicates-dc-core.patch
+++ /dev/null
@@ -1,1554 +0,0 @@
-From 96b68c05612faea94081e7a5c35b10c3cbd95cf1 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 19 Jan 2016 16:22:40 -0500
-Subject: [PATCH 0702/1110] drm/amd/dal: remove dce_base, duplicates dc core
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 677 ++++++++++++++++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   5 +-
- drivers/gpu/drm/amd/dal/dc/dce_base/Makefile       |  23 -
- .../drm/amd/dal/dc/dce_base/dce_base_resource.c    | 710 ---------------------
- .../drm/amd/dal/dc/dce_base/dce_base_resource.h    |  37 --
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |   6 +
- 7 files changed, 686 insertions(+), 774 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce_base/Makefile
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index 0ab2c18..fc1dd0e 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -3,7 +3,7 @@
- #
- 
- DC_LIBS = adapter asic_capability audio basics bios calcs \
--dcs gpio gpu i2caux irq dce_base
-+dcs gpio gpu i2caux irq
- 
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- DC_LIBS += dce110
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 557f918..52fcdc1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -530,3 +530,680 @@ void pplib_apply_display_requirements(
- 
- 	dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
- }
-+
-+/* Maximum TMDS single link pixel clock 165MHz */
-+#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
-+
-+static void attach_stream_to_controller(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	res_ctx->controller_ctx[stream->controller_idx].stream = stream;
-+}
-+
-+static void set_stream_engine_in_use(
-+		struct resource_context *res_ctx,
-+		struct stream_encoder *stream_enc)
-+{
-+	int i;
-+
-+	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
-+		if (res_ctx->pool.stream_enc[i] == stream_enc)
-+			res_ctx->is_stream_enc_acquired[i] = true;
-+	}
-+}
-+
-+/* TODO: release audio object */
-+static void set_audio_in_use(
-+		struct resource_context *res_ctx,
-+		struct audio *audio)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.audio_count; i++) {
-+		if (res_ctx->pool.audios[i] == audio) {
-+			res_ctx->is_audio_acquired[i] = true;
-+		}
-+	}
-+}
-+
-+static bool assign_first_free_controller(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	uint8_t i;
-+	for (i = 0; i < res_ctx->pool.controller_count; i++) {
-+		if (!res_ctx->controller_ctx[i].stream) {
-+			stream->tg = res_ctx->pool.timing_generators[i];
-+			stream->mi = res_ctx->pool.mis[i];
-+			stream->ipp = res_ctx->pool.ipps[i];
-+			stream->xfm = res_ctx->pool.transforms[i];
-+			stream->opp = res_ctx->pool.opps[i];
-+			stream->controller_idx = i;
-+			stream->dis_clk = res_ctx->pool.display_clock;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+static struct stream_encoder *find_first_free_match_stream_enc_for_link(
-+		struct resource_context *res_ctx,
-+		struct core_link *link)
-+{
-+	uint8_t i;
-+	int8_t j = -1;
-+	const struct dc_sink *sink = NULL;
-+
-+	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
-+		if (!res_ctx->is_stream_enc_acquired[i] &&
-+					res_ctx->pool.stream_enc[i]) {
-+			/* Store first available for MST second display
-+			 * in daisy chain use case */
-+			j = i;
-+			if (res_ctx->pool.stream_enc[i]->id ==
-+					link->link_enc->preferred_engine)
-+				return res_ctx->pool.stream_enc[i];
-+		}
-+	}
-+
-+	/*
-+	 * below can happen in cases when stream encoder is acquired:
-+	 * 1) for second MST display in chain, so preferred engine already
-+	 * acquired;
-+	 * 2) for another link, which preferred engine already acquired by any
-+	 * MST configuration.
-+	 *
-+	 * If signal is of DP type and preferred engine not found, return last available
-+	 *
-+	 * TODO - This is just a patch up and a generic solution is
-+	 * required for non DP connectors.
-+	 */
-+
-+	sink = link->public.local_sink ? link->public.local_sink : link->public.remote_sinks[0];
-+
-+	if (sink && j >= 0 &&  dc_is_dp_signal(sink->sink_signal))
-+		return res_ctx->pool.stream_enc[j];
-+
-+	return NULL;
-+}
-+
-+static struct audio *find_first_free_audio(struct resource_context *res_ctx)
-+{
-+	int i;
-+	for (i = 0; i < res_ctx->pool.audio_count; i++) {
-+		if (res_ctx->is_audio_acquired[i] == false) {
-+			return res_ctx->pool.audios[i];
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static bool check_timing_change(struct core_stream *cur_stream,
-+		struct core_stream *new_stream)
-+{
-+	if (cur_stream == NULL)
-+		return true;
-+
-+	/* If sink pointer changed, it means this is a hotplug, we should do
-+	 * full hw setting.
-+	 */
-+	if (cur_stream->sink != new_stream->sink)
-+		return true;
-+
-+	return !is_same_timing(
-+					&cur_stream->public.timing,
-+					&new_stream->public.timing);
-+}
-+
-+static void set_stream_signal(struct core_stream *stream)
-+{
-+	struct dc_sink *dc_sink = (struct dc_sink *)stream->public.sink;
-+
-+	/* For asic supports dual link DVI, we should adjust signal type
-+	 * based on timing pixel clock. If pixel clock more than 165Mhz,
-+	 * signal is dual link, otherwise, single link.
-+	 */
-+	if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
-+			dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK) {
-+		if (stream->public.timing.pix_clk_khz >
-+			TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
-+			dc_sink->sink_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		else
-+			dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	}
-+
-+	stream->signal = dc_sink->sink_signal;
-+}
-+
-+enum dc_status map_resources(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j;
-+
-+	/* mark resources used for targets that are already active */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (!context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			attach_stream_to_controller(
-+				&context->res_ctx,
-+				stream);
-+
-+			set_stream_engine_in_use(
-+				&context->res_ctx,
-+				stream->stream_enc);
-+
-+			reference_clock_source(
-+				&context->res_ctx,
-+				stream->clock_source);
-+
-+			if (stream->audio) {
-+				set_audio_in_use(&context->res_ctx,
-+					stream->audio);
-+			}
-+		}
-+	}
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct core_stream *curr_stream;
-+
-+			if (!assign_first_free_controller(
-+					&context->res_ctx, stream))
-+				return DC_NO_CONTROLLER_RESOURCE;
-+
-+			attach_stream_to_controller(&context->res_ctx, stream);
-+
-+			set_stream_signal(stream);
-+
-+			curr_stream =
-+				dc->current_context.res_ctx.controller_ctx
-+				[stream->controller_idx].stream;
-+			context->res_ctx.controller_ctx[stream->controller_idx]
-+			.flags.timing_changed =
-+				check_timing_change(curr_stream, stream);
-+
-+			/*
-+			 * we do not need stream encoder or audio resources
-+			 * when connecting to virtual link
-+			 */
-+			if (stream->sink->link->public.connector_signal ==
-+							SIGNAL_TYPE_VIRTUAL)
-+				continue;
-+
-+			stream->stream_enc =
-+				find_first_free_match_stream_enc_for_link(
-+					&context->res_ctx,
-+					stream->sink->link);
-+
-+			if (!stream->stream_enc)
-+				return DC_NO_STREAM_ENG_RESOURCE;
-+
-+			set_stream_engine_in_use(
-+					&context->res_ctx,
-+					stream->stream_enc);
-+
-+			/* TODO: Add check if ASIC support and EDID audio */
-+			if (!stream->sink->converter_disable_audio &&
-+						dc_is_audio_capable_signal(
-+						stream->signal)) {
-+				stream->audio = find_first_free_audio(
-+						&context->res_ctx);
-+
-+				if (!stream->audio)
-+					return DC_NO_STREAM_AUDIO_RESOURCE;
-+
-+				set_audio_in_use(&context->res_ctx,
-+						stream->audio);
-+			}
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+static enum ds_color_space build_default_color_space(
-+		struct core_stream *stream)
-+{
-+	enum ds_color_space color_space =
-+			DS_COLOR_SPACE_SRGB_FULLRANGE;
-+	struct dc_crtc_timing *timing = &stream->public.timing;
-+
-+	switch (stream->signal) {
-+	/* TODO: implement other signal color space setting */
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	{
-+		uint32_t pix_clk_khz;
-+
-+		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 &&
-+			timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
-+			if (timing->timing_standard ==
-+					TIMING_STANDARD_CEA770 &&
-+				timing->timing_standard ==
-+						TIMING_STANDARD_CEA861)
-+				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
-+
-+			pix_clk_khz = timing->pix_clk_khz / 10;
-+			if (timing->h_addressable == 640 &&
-+				timing->v_addressable == 480 &&
-+				(pix_clk_khz == 2520 || pix_clk_khz == 2517))
-+				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
-+		} else {
-+			if (timing->timing_standard ==
-+					TIMING_STANDARD_CEA770 ||
-+					timing->timing_standard ==
-+					TIMING_STANDARD_CEA861) {
-+
-+				color_space =
-+					(timing->pix_clk_khz > PIXEL_CLOCK) ?
-+						DS_COLOR_SPACE_YCBCR709 :
-+						DS_COLOR_SPACE_YCBCR601;
-+			}
-+		}
-+		break;
-+	}
-+	default:
-+		switch (timing->pixel_encoding) {
-+		case PIXEL_ENCODING_YCBCR422:
-+		case PIXEL_ENCODING_YCBCR444:
-+			if (timing->pix_clk_khz > PIXEL_CLOCK)
-+				color_space = DS_COLOR_SPACE_YCBCR709;
-+			else
-+				color_space = DS_COLOR_SPACE_YCBCR601;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	}
-+	return color_space;
-+}
-+
-+static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
-+	struct encoder_info_frame *encoder_info_frame)
-+{
-+	dc_service_memset(
-+		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
-+
-+	/* For gamut we recalc checksum */
-+	if (hw_info_frame->gamut_packet.valid) {
-+		uint8_t chk_sum = 0;
-+		uint8_t *ptr;
-+		uint8_t i;
-+
-+		dc_service_memmove(
-+						&encoder_info_frame->gamut,
-+						&hw_info_frame->gamut_packet,
-+						sizeof(struct hw_info_packet));
-+
-+		/*start of the Gamut data. */
-+		ptr = &encoder_info_frame->gamut.sb[3];
-+
-+		for (i = 0; i <= encoder_info_frame->gamut.sb[1]; i++)
-+			chk_sum += ptr[i];
-+
-+		encoder_info_frame->gamut.sb[2] = (uint8_t) (0x100 - chk_sum);
-+	}
-+
-+	if (hw_info_frame->avi_info_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->avi,
-+						&hw_info_frame->avi_info_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->vendor_info_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->vendor,
-+						&hw_info_frame->vendor_info_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->spd_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->spd,
-+						&hw_info_frame->spd_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+
-+	if (hw_info_frame->vsc_packet.valid) {
-+		dc_service_memmove(
-+						&encoder_info_frame->vsc,
-+						&hw_info_frame->vsc_packet,
-+						sizeof(struct hw_info_packet));
-+	}
-+}
-+
-+static void set_avi_info_frame(struct hw_info_packet *info_packet,
-+		struct core_stream *stream)
-+{
-+	enum ds_color_space color_space = DS_COLOR_SPACE_UNKNOWN;
-+	struct info_frame info_frame = { {0} };
-+	uint32_t pixel_encoding = 0;
-+	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
-+	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
-+	bool itc = false;
-+	uint8_t cn0_cn1 = 0;
-+	uint8_t *check_sum = NULL;
-+	uint8_t byte_index = 0;
-+
-+	if (info_packet == NULL)
-+		return;
-+
-+	color_space = build_default_color_space(stream);
-+
-+	/* Initialize header */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
-+			info_frame_type = INFO_FRAME_AVI;
-+	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
-+	* not be used in HDMI 2.0 (Section 10.1) */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.version =
-+			INFO_FRAME_VERSION_2;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
-+			INFO_FRAME_SIZE_AVI;
-+
-+	/* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
-+	* according to HDMI 2.0 spec (Section 10.1)
-+	* Add "case PixelEncoding_YCbCr420:    pixelEncoding = 3; break;"
-+	* when YCbCr 4:2:0 is supported by DAL hardware. */
-+
-+	switch (stream->public.timing.pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		pixel_encoding = 1;
-+		break;
-+
-+	case PIXEL_ENCODING_YCBCR444:
-+		pixel_encoding = 2;
-+		break;
-+
-+	case PIXEL_ENCODING_RGB:
-+	default:
-+		pixel_encoding = 0;
-+	}
-+
-+	/* Y0_Y1_Y2 : The pixel encoding */
-+	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
-+		pixel_encoding;
-+
-+
-+	/* A0 = 1 Active Format Information valid */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
-+		ACTIVE_FORMAT_VALID;
-+
-+	/* B0, B1 = 3; Bar info data is valid */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
-+		BAR_INFO_BOTH_VALID;
-+
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
-+			PICTURE_SCALING_UNIFORM;
-+
-+	/* S0, S1 : Underscan / Overscan */
-+	/* TODO: un-hardcode scan type */
-+	scan_type = SCANNING_TYPE_UNDERSCAN;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
-+
-+	/* C0, C1 : Colorimetry */
-+	if (color_space == DS_COLOR_SPACE_YCBCR709)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_ITU709;
-+	else if (color_space == DS_COLOR_SPACE_YCBCR601)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_ITU601;
-+	else
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
-+				COLORIMETRY_NO_DATA;
-+
-+
-+	/* TODO: un-hardcode aspect ratio */
-+	aspect = stream->public.timing.aspect_ratio;
-+
-+	switch (aspect) {
-+	case ASPECT_RATIO_4_3:
-+	case ASPECT_RATIO_16_9:
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
-+		break;
-+
-+	case ASPECT_RATIO_NO_DATA:
-+	case ASPECT_RATIO_64_27:
-+	case ASPECT_RATIO_256_135:
-+	default:
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
-+	}
-+
-+	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
-+			ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
-+
-+	/* TODO: un-hardcode cn0_cn1 and itc */
-+	cn0_cn1 = 0;
-+	itc = false;
-+
-+	if (itc) {
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
-+			cn0_cn1;
-+	}
-+
-+	/* TODO: un-hardcode q0_q1 */
-+	if (color_space == DS_COLOR_SPACE_SRGB_FULLRANGE)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_FULL_RANGE;
-+	else if (color_space == DS_COLOR_SPACE_SRGB_LIMITEDRANGE)
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_LIMITED_RANGE;
-+	else
-+		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
-+						RGB_QUANTIZATION_DEFAULT_RANGE;
-+
-+	/* TODO : We should handle YCC quantization,
-+	 * but we do not have matrix calculation */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
-+					YYC_QUANTIZATION_LIMITED_RANGE;
-+
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
-+					stream->public.timing.vic;
-+
-+	/* pixel repetition
-+	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
-+	 * repetition start from 1 */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
-+
-+	/* Bar Info
-+	 * barTop:    Line Number of End of Top Bar.
-+	 * barBottom: Line Number of Start of Bottom Bar.
-+	 * barLeft:   Pixel Number of End of Left Bar.
-+	 * barRight:  Pixel Number of Start of Right Bar. */
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
-+			stream->public.timing.v_border_top;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
-+		(stream->public.timing.v_border_top
-+			- stream->public.timing.v_border_bottom + 1);
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
-+			stream->public.timing.h_border_left;
-+	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
-+		(stream->public.timing.h_total
-+			- stream->public.timing.h_border_right + 1);
-+
-+	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
-+	check_sum =
-+		&info_frame.
-+		avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
-+	*check_sum = INFO_FRAME_AVI + INFO_FRAME_SIZE_AVI
-+			+ INFO_FRAME_VERSION_2;
-+
-+	for (byte_index = 1; byte_index <= INFO_FRAME_SIZE_AVI; byte_index++)
-+		*check_sum += info_frame.avi_info_packet.info_packet_hdmi.
-+				packet_raw_data.sb[byte_index];
-+
-+	/* one byte complement */
-+	*check_sum = (uint8_t) (0x100 - *check_sum);
-+
-+	/* Store in hw_path_mode */
-+	info_packet->hb0 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
-+	info_packet->hb1 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
-+	info_packet->hb2 =
-+		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
-+
-+	for (byte_index = 0; byte_index < sizeof(info_packet->sb); byte_index++)
-+		info_packet->sb[byte_index] = info_frame.avi_info_packet.
-+		info_packet_hdmi.packet_raw_data.sb[byte_index];
-+
-+	info_packet->valid = true;
-+}
-+
-+static void set_vendor_info_packet(struct core_stream *stream,
-+		struct hw_info_packet *info_packet)
-+{
-+	uint32_t length = 0;
-+	bool hdmi_vic_mode = false;
-+	uint8_t checksum = 0;
-+	uint32_t i = 0;
-+	enum dc_timing_3d_format format;
-+
-+	ASSERT_CRITICAL(stream != NULL);
-+	ASSERT_CRITICAL(info_packet != NULL);
-+
-+	format = stream->public.timing.timing_3d_format;
-+
-+	/* Can be different depending on packet content */
-+	length = 5;
-+
-+	if (stream->public.timing.hdmi_vic != 0
-+			&& stream->public.timing.h_total >= 3840
-+			&& stream->public.timing.v_total >= 2160)
-+		hdmi_vic_mode = true;
-+
-+	/* According to HDMI 1.4a CTS, VSIF should be sent
-+	 * for both 3D stereo and HDMI VIC modes.
-+	 * For all other modes, there is no VSIF sent.  */
-+
-+	if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
-+		return;
-+
-+	/* 24bit IEEE Registration identifier (0x000c03). LSB first. */
-+	info_packet->sb[1] = 0x03;
-+	info_packet->sb[2] = 0x0C;
-+	info_packet->sb[3] = 0x00;
-+
-+	/*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
-+	 * The value for HDMI_Video_Format are:
-+	 * 0x0 (0b000) - No additional HDMI video format is presented in this
-+	 * packet
-+	 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
-+	 * parameter follows
-+	 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
-+	 * potentially 3D_Ext_Data follows
-+	 * 0x3..0x7 (0b011..0b111) - reserved for future use */
-+	if (format != TIMING_3D_FORMAT_NONE)
-+		info_packet->sb[4] = (2 << 5);
-+	else if (hdmi_vic_mode)
-+		info_packet->sb[4] = (1 << 5);
-+
-+	/* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
-+	 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
-+	 * The value for 3D_Structure are:
-+	 * 0x0 - Frame Packing
-+	 * 0x1 - Field Alternative
-+	 * 0x2 - Line Alternative
-+	 * 0x3 - Side-by-Side (full)
-+	 * 0x4 - L + depth
-+	 * 0x5 - L + depth + graphics + graphics-depth
-+	 * 0x6 - Top-and-Bottom
-+	 * 0x7 - Reserved for future use
-+	 * 0x8 - Side-by-Side (Half)
-+	 * 0x9..0xE - Reserved for future use
-+	 * 0xF - Not used */
-+	switch (format) {
-+	case TIMING_3D_FORMAT_HW_FRAME_PACKING:
-+	case TIMING_3D_FORMAT_SW_FRAME_PACKING:
-+		info_packet->sb[5] = (0x0 << 4);
-+		break;
-+
-+	case TIMING_3D_FORMAT_SIDE_BY_SIDE:
-+	case TIMING_3D_FORMAT_SBS_SW_PACKED:
-+		info_packet->sb[5] = (0x8 << 4);
-+		length = 6;
-+		break;
-+
-+	case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
-+	case TIMING_3D_FORMAT_TB_SW_PACKED:
-+		info_packet->sb[5] = (0x6 << 4);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	/*PB5: If PB4 is set to 0x1 (extended resolution format)
-+	 * fill PB5 with the correct HDMI VIC code */
-+	if (hdmi_vic_mode)
-+		info_packet->sb[5] = stream->public.timing.hdmi_vic;
-+
-+	/* Header */
-+	info_packet->hb0 = 0x81; /* VSIF packet type. */
-+	info_packet->hb1 = 0x01; /* Version */
-+
-+	/* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
-+	info_packet->hb2 = (uint8_t) (length);
-+
-+	/* Calculate checksum */
-+	checksum = 0;
-+	checksum += info_packet->hb0;
-+	checksum += info_packet->hb1;
-+	checksum += info_packet->hb2;
-+
-+	for (i = 1; i <= length; i++)
-+		checksum += info_packet->sb[i];
-+
-+	info_packet->sb[0] = (uint8_t) (0x100 - checksum);
-+
-+	info_packet->valid = true;
-+}
-+
-+void build_info_frame(struct core_stream *stream)
-+{
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+	struct hw_info_frame info_frame = { { 0 } };
-+
-+	/* default all packets to invalid */
-+	info_frame.avi_info_packet.valid = false;
-+	info_frame.gamut_packet.valid = false;
-+	info_frame.vendor_info_packet.valid = false;
-+	info_frame.spd_packet.valid = false;
-+	info_frame.vsc_packet.valid = false;
-+
-+	signal = stream->sink->public.sink_signal;
-+
-+	/* HDMi and DP have different info packets*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		set_avi_info_frame(&info_frame.avi_info_packet,
-+				stream);
-+		set_vendor_info_packet(stream, &info_frame.vendor_info_packet);
-+	}
-+
-+	translate_info_frame(&info_frame,
-+			&stream->encoder_info_frame);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 09f245c..7880ccb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -28,7 +28,6 @@
- #include "stream_encoder.h"
- 
- #include "resource.h"
--#include "dce_base/dce_base_resource.h"
- #include "include/irq_service_interface.h"
- #include "include/timing_generator_interface.h"
- 
-@@ -650,7 +649,7 @@ static enum dc_status validate_mapped_resource(
- 			if (status != DC_OK)
- 				return status;
- 
--			dce_base_build_info_frame(stream);
-+			build_info_frame(stream);
- 		}
- 	}
- 
-@@ -935,7 +934,7 @@ enum dc_status dce110_validate_with_context(
- 
- 	context->res_ctx.pool = dc->res_pool;
- 
--	result = dce_base_map_resources(dc, context);
-+	result = map_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = map_clock_resources(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/Makefile b/drivers/gpu/drm/amd/dal/dc/dce_base/Makefile
-deleted file mode 100644
-index 4f239f5..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/Makefile
-+++ /dev/null
-@@ -1,23 +0,0 @@
--#
--# Makefile for the 'controller' sub-component of DAL.
--# It provides the control and status of HW CRTC block.
--
--DCE_BASE = dce_base_resource.o
--
--AMD_DAL_DCE_BASE = $(addprefix $(AMDDALPATH)/dc/dce_base/,$(DCE_BASE))
--
--AMD_DAL_FILES += $(AMD_DAL_DCE_BASE)
--
--
--###############################################################################
--# DCE 11x
--###############################################################################
--ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
--TG_DCE_BASE = dce_base_resource.o
--
--AMD_DAL_TG_DCE110 = $(addprefix \
--	$(AMDDALPATH)/dc/dce_base/,$(TG_DCE_BASE))
--
--AMD_DAL_FILES += $(AMD_DAL_TG_DCE_BASE)
--endif
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-deleted file mode 100644
-index 0907f3c..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.c
-+++ /dev/null
-@@ -1,710 +0,0 @@
--/*
--* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#include "dce_base_resource.h"
--
--#include "dc_services.h"
--
--#include "set_mode_types.h"
--#include "stream_encoder.h"
--#include "link_encoder.h"
--
--#include "resource.h"
--
--/* Maximum TMDS single link pixel clock 165MHz */
--#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
--
--static void attach_stream_to_controller(
--		struct resource_context *res_ctx,
--		struct core_stream *stream)
--{
--	res_ctx->controller_ctx[stream->controller_idx].stream = stream;
--}
--
--static void set_stream_engine_in_use(
--		struct resource_context *res_ctx,
--		struct stream_encoder *stream_enc)
--{
--	int i;
--
--	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
--		if (res_ctx->pool.stream_enc[i] == stream_enc)
--			res_ctx->is_stream_enc_acquired[i] = true;
--	}
--}
--
--/* TODO: release audio object */
--static void set_audio_in_use(
--		struct resource_context *res_ctx,
--		struct audio *audio)
--{
--	int i;
--	for (i = 0; i < res_ctx->pool.audio_count; i++) {
--		if (res_ctx->pool.audios[i] == audio) {
--			res_ctx->is_audio_acquired[i] = true;
--		}
--	}
--}
--
--static bool assign_first_free_controller(
--		struct resource_context *res_ctx,
--		struct core_stream *stream)
--{
--	uint8_t i;
--	for (i = 0; i < res_ctx->pool.controller_count; i++) {
--		if (!res_ctx->controller_ctx[i].stream) {
--			stream->tg = res_ctx->pool.timing_generators[i];
--			stream->mi = res_ctx->pool.mis[i];
--			stream->ipp = res_ctx->pool.ipps[i];
--			stream->xfm = res_ctx->pool.transforms[i];
--			stream->opp = res_ctx->pool.opps[i];
--			stream->controller_idx = i;
--			stream->dis_clk = res_ctx->pool.display_clock;
--			return true;
--		}
--	}
--	return false;
--}
--
--static struct stream_encoder *find_first_free_match_stream_enc_for_link(
--		struct resource_context *res_ctx,
--		struct core_link *link)
--{
--	uint8_t i;
--	int8_t j = -1;
--	const struct dc_sink *sink = NULL;
--
--	for (i = 0; i < res_ctx->pool.stream_enc_count; i++) {
--		if (!res_ctx->is_stream_enc_acquired[i] &&
--					res_ctx->pool.stream_enc[i]) {
--			/* Store first available for MST second display
--			 * in daisy chain use case */
--			j = i;
--			if (res_ctx->pool.stream_enc[i]->id ==
--					link->link_enc->preferred_engine)
--				return res_ctx->pool.stream_enc[i];
--		}
--	}
--
--	/*
--	 * below can happen in cases when stream encoder is acquired:
--	 * 1) for second MST display in chain, so preferred engine already
--	 * acquired;
--	 * 2) for another link, which preferred engine already acquired by any
--	 * MST configuration.
--	 *
--	 * If signal is of DP type and preferred engine not found, return last available
--	 *
--	 * TODO - This is just a patch up and a generic solution is
--	 * required for non DP connectors.
--	 */
--
--	sink = link->public.local_sink ? link->public.local_sink : link->public.remote_sinks[0];
--
--	if (sink && j >= 0 &&  dc_is_dp_signal(sink->sink_signal))
--		return res_ctx->pool.stream_enc[j];
--
--	return NULL;
--}
--
--static struct audio *find_first_free_audio(struct resource_context *res_ctx)
--{
--	int i;
--	for (i = 0; i < res_ctx->pool.audio_count; i++) {
--		if (res_ctx->is_audio_acquired[i] == false) {
--			return res_ctx->pool.audios[i];
--		}
--	}
--
--	return 0;
--}
--
--static bool check_timing_change(struct core_stream *cur_stream,
--		struct core_stream *new_stream)
--{
--	if (cur_stream == NULL)
--		return true;
--
--	/* If sink pointer changed, it means this is a hotplug, we should do
--	 * full hw setting.
--	 */
--	if (cur_stream->sink != new_stream->sink)
--		return true;
--
--	return !is_same_timing(
--					&cur_stream->public.timing,
--					&new_stream->public.timing);
--}
--
--static void set_stream_signal(struct core_stream *stream)
--{
--	struct dc_sink *dc_sink = (struct dc_sink *)stream->public.sink;
--
--	/* For asic supports dual link DVI, we should adjust signal type
--	 * based on timing pixel clock. If pixel clock more than 165Mhz,
--	 * signal is dual link, otherwise, single link.
--	 */
--	if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
--			dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK) {
--		if (stream->public.timing.pix_clk_khz >
--			TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
--			dc_sink->sink_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
--		else
--			dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
--	}
--
--	stream->signal = dc_sink->sink_signal;
--}
--
--enum dc_status dce_base_map_resources(
--		const struct dc *dc,
--		struct validate_context *context)
--{
--	uint8_t i, j;
--
--	/* mark resources used for targets that are already active */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (!context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			attach_stream_to_controller(
--				&context->res_ctx,
--				stream);
--
--			set_stream_engine_in_use(
--				&context->res_ctx,
--				stream->stream_enc);
--
--			reference_clock_source(
--				&context->res_ctx,
--				stream->clock_source);
--
--			if (stream->audio) {
--				set_audio_in_use(&context->res_ctx,
--					stream->audio);
--			}
--		}
--	}
--
--	/* acquire new resources */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct core_stream *curr_stream;
--
--			if (!assign_first_free_controller(
--					&context->res_ctx, stream))
--				return DC_NO_CONTROLLER_RESOURCE;
--
--			attach_stream_to_controller(&context->res_ctx, stream);
--
--			set_stream_signal(stream);
--
--			curr_stream =
--				dc->current_context.res_ctx.controller_ctx
--				[stream->controller_idx].stream;
--			context->res_ctx.controller_ctx[stream->controller_idx]
--			.flags.timing_changed =
--				check_timing_change(curr_stream, stream);
--
--			/*
--			 * we do not need stream encoder or audio resources
--			 * when connecting to virtual link
--			 */
--			if (stream->sink->link->public.connector_signal ==
--							SIGNAL_TYPE_VIRTUAL)
--				continue;
--
--			stream->stream_enc =
--				find_first_free_match_stream_enc_for_link(
--					&context->res_ctx,
--					stream->sink->link);
--
--			if (!stream->stream_enc)
--				return DC_NO_STREAM_ENG_RESOURCE;
--
--			set_stream_engine_in_use(
--					&context->res_ctx,
--					stream->stream_enc);
--
--			/* TODO: Add check if ASIC support and EDID audio */
--			if (!stream->sink->converter_disable_audio &&
--						dc_is_audio_capable_signal(
--						stream->signal)) {
--				stream->audio = find_first_free_audio(
--						&context->res_ctx);
--
--				if (!stream->audio)
--					return DC_NO_STREAM_AUDIO_RESOURCE;
--
--				set_audio_in_use(&context->res_ctx,
--						stream->audio);
--			}
--		}
--	}
--
--	return DC_OK;
--}
--
--static enum ds_color_space build_default_color_space(
--		struct core_stream *stream)
--{
--	enum ds_color_space color_space =
--			DS_COLOR_SPACE_SRGB_FULLRANGE;
--	struct dc_crtc_timing *timing = &stream->public.timing;
--
--	switch (stream->signal) {
--	/* TODO: implement other signal color space setting */
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		break;
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--	{
--		uint32_t pix_clk_khz;
--
--		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 &&
--			timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
--			if (timing->timing_standard ==
--					TIMING_STANDARD_CEA770 &&
--				timing->timing_standard ==
--						TIMING_STANDARD_CEA861)
--				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
--
--			pix_clk_khz = timing->pix_clk_khz / 10;
--			if (timing->h_addressable == 640 &&
--				timing->v_addressable == 480 &&
--				(pix_clk_khz == 2520 || pix_clk_khz == 2517))
--				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
--		} else {
--			if (timing->timing_standard ==
--					TIMING_STANDARD_CEA770 ||
--					timing->timing_standard ==
--					TIMING_STANDARD_CEA861) {
--
--				color_space =
--					(timing->pix_clk_khz > PIXEL_CLOCK) ?
--						DS_COLOR_SPACE_YCBCR709 :
--						DS_COLOR_SPACE_YCBCR601;
--			}
--		}
--		break;
--	}
--	default:
--		switch (timing->pixel_encoding) {
--		case PIXEL_ENCODING_YCBCR422:
--		case PIXEL_ENCODING_YCBCR444:
--			if (timing->pix_clk_khz > PIXEL_CLOCK)
--				color_space = DS_COLOR_SPACE_YCBCR709;
--			else
--				color_space = DS_COLOR_SPACE_YCBCR601;
--			break;
--		default:
--			break;
--		}
--		break;
--	}
--	return color_space;
--}
--
--static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
--	struct encoder_info_frame *encoder_info_frame)
--{
--	dc_service_memset(
--		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
--
--	/* For gamut we recalc checksum */
--	if (hw_info_frame->gamut_packet.valid) {
--		uint8_t chk_sum = 0;
--		uint8_t *ptr;
--		uint8_t i;
--
--		dc_service_memmove(
--						&encoder_info_frame->gamut,
--						&hw_info_frame->gamut_packet,
--						sizeof(struct hw_info_packet));
--
--		/*start of the Gamut data. */
--		ptr = &encoder_info_frame->gamut.sb[3];
--
--		for (i = 0; i <= encoder_info_frame->gamut.sb[1]; i++)
--			chk_sum += ptr[i];
--
--		encoder_info_frame->gamut.sb[2] = (uint8_t) (0x100 - chk_sum);
--	}
--
--	if (hw_info_frame->avi_info_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->avi,
--						&hw_info_frame->avi_info_packet,
--						sizeof(struct hw_info_packet));
--	}
--
--	if (hw_info_frame->vendor_info_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->vendor,
--						&hw_info_frame->vendor_info_packet,
--						sizeof(struct hw_info_packet));
--	}
--
--	if (hw_info_frame->spd_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->spd,
--						&hw_info_frame->spd_packet,
--						sizeof(struct hw_info_packet));
--	}
--
--	if (hw_info_frame->vsc_packet.valid) {
--		dc_service_memmove(
--						&encoder_info_frame->vsc,
--						&hw_info_frame->vsc_packet,
--						sizeof(struct hw_info_packet));
--	}
--}
--
--static void set_avi_info_frame(struct hw_info_packet *info_packet,
--		struct core_stream *stream)
--{
--	enum ds_color_space color_space = DS_COLOR_SPACE_UNKNOWN;
--	struct info_frame info_frame = { {0} };
--	uint32_t pixel_encoding = 0;
--	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
--	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
--	bool itc = false;
--	uint8_t cn0_cn1 = 0;
--	uint8_t *check_sum = NULL;
--	uint8_t byte_index = 0;
--
--	if (info_packet == NULL)
--		return;
--
--	color_space = build_default_color_space(stream);
--
--	/* Initialize header */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
--			info_frame_type = INFO_FRAME_AVI;
--	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
--	* not be used in HDMI 2.0 (Section 10.1) */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.header.version =
--			INFO_FRAME_VERSION_2;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.header.length =
--			INFO_FRAME_SIZE_AVI;
--
--	/* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
--	* according to HDMI 2.0 spec (Section 10.1)
--	* Add "case PixelEncoding_YCbCr420:    pixelEncoding = 3; break;"
--	* when YCbCr 4:2:0 is supported by DAL hardware. */
--
--	switch (stream->public.timing.pixel_encoding) {
--	case PIXEL_ENCODING_YCBCR422:
--		pixel_encoding = 1;
--		break;
--
--	case PIXEL_ENCODING_YCBCR444:
--		pixel_encoding = 2;
--		break;
--
--	case PIXEL_ENCODING_RGB:
--	default:
--		pixel_encoding = 0;
--	}
--
--	/* Y0_Y1_Y2 : The pixel encoding */
--	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
--		pixel_encoding;
--
--
--	/* A0 = 1 Active Format Information valid */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
--		ACTIVE_FORMAT_VALID;
--
--	/* B0, B1 = 3; Bar info data is valid */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.B0_B1 =
--		BAR_INFO_BOTH_VALID;
--
--	info_frame.avi_info_packet.info_packet_hdmi.bits.SC0_SC1 =
--			PICTURE_SCALING_UNIFORM;
--
--	/* S0, S1 : Underscan / Overscan */
--	/* TODO: un-hardcode scan type */
--	scan_type = SCANNING_TYPE_UNDERSCAN;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.S0_S1 = scan_type;
--
--	/* C0, C1 : Colorimetry */
--	if (color_space == DS_COLOR_SPACE_YCBCR709)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
--				COLORIMETRY_ITU709;
--	else if (color_space == DS_COLOR_SPACE_YCBCR601)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
--				COLORIMETRY_ITU601;
--	else
--		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
--				COLORIMETRY_NO_DATA;
--
--
--	/* TODO: un-hardcode aspect ratio */
--	aspect = stream->public.timing.aspect_ratio;
--
--	switch (aspect) {
--	case ASPECT_RATIO_4_3:
--	case ASPECT_RATIO_16_9:
--		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = aspect;
--		break;
--
--	case ASPECT_RATIO_NO_DATA:
--	case ASPECT_RATIO_64_27:
--	case ASPECT_RATIO_256_135:
--	default:
--		info_frame.avi_info_packet.info_packet_hdmi.bits.M0_M1 = 0;
--	}
--
--	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.R0_R3 =
--			ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
--
--	/* TODO: un-hardcode cn0_cn1 and itc */
--	cn0_cn1 = 0;
--	itc = false;
--
--	if (itc) {
--		info_frame.avi_info_packet.info_packet_hdmi.bits.ITC = 1;
--		info_frame.avi_info_packet.info_packet_hdmi.bits.CN0_CN1 =
--			cn0_cn1;
--	}
--
--	/* TODO: un-hardcode q0_q1 */
--	if (color_space == DS_COLOR_SPACE_SRGB_FULLRANGE)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
--						RGB_QUANTIZATION_FULL_RANGE;
--	else if (color_space == DS_COLOR_SPACE_SRGB_LIMITEDRANGE)
--		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
--						RGB_QUANTIZATION_LIMITED_RANGE;
--	else
--		info_frame.avi_info_packet.info_packet_hdmi.bits.Q0_Q1 =
--						RGB_QUANTIZATION_DEFAULT_RANGE;
--
--	/* TODO : We should handle YCC quantization,
--	 * but we do not have matrix calculation */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.YQ0_YQ1 =
--					YYC_QUANTIZATION_LIMITED_RANGE;
--
--	info_frame.avi_info_packet.info_packet_hdmi.bits.VIC0_VIC7 =
--					stream->public.timing.vic;
--
--	/* pixel repetition
--	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
--	 * repetition start from 1 */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.PR0_PR3 = 0;
--
--	/* Bar Info
--	 * barTop:    Line Number of End of Top Bar.
--	 * barBottom: Line Number of Start of Bottom Bar.
--	 * barLeft:   Pixel Number of End of Left Bar.
--	 * barRight:  Pixel Number of Start of Right Bar. */
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_top =
--			stream->public.timing.v_border_top;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_bottom =
--		(stream->public.timing.v_border_top
--			- stream->public.timing.v_border_bottom + 1);
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_left =
--			stream->public.timing.h_border_left;
--	info_frame.avi_info_packet.info_packet_hdmi.bits.bar_right =
--		(stream->public.timing.h_total
--			- stream->public.timing.h_border_right + 1);
--
--	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
--	check_sum =
--		&info_frame.
--		avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
--	*check_sum = INFO_FRAME_AVI + INFO_FRAME_SIZE_AVI
--			+ INFO_FRAME_VERSION_2;
--
--	for (byte_index = 1; byte_index <= INFO_FRAME_SIZE_AVI; byte_index++)
--		*check_sum += info_frame.avi_info_packet.info_packet_hdmi.
--				packet_raw_data.sb[byte_index];
--
--	/* one byte complement */
--	*check_sum = (uint8_t) (0x100 - *check_sum);
--
--	/* Store in hw_path_mode */
--	info_packet->hb0 =
--		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb0;
--	info_packet->hb1 =
--		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb1;
--	info_packet->hb2 =
--		info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.hb2;
--
--	for (byte_index = 0; byte_index < sizeof(info_packet->sb); byte_index++)
--		info_packet->sb[byte_index] = info_frame.avi_info_packet.
--		info_packet_hdmi.packet_raw_data.sb[byte_index];
--
--	info_packet->valid = true;
--}
--
--static void set_vendor_info_packet(struct core_stream *stream,
--		struct hw_info_packet *info_packet)
--{
--	uint32_t length = 0;
--	bool hdmi_vic_mode = false;
--	uint8_t checksum = 0;
--	uint32_t i = 0;
--	enum dc_timing_3d_format format;
--
--	ASSERT_CRITICAL(stream != NULL);
--	ASSERT_CRITICAL(info_packet != NULL);
--
--	format = stream->public.timing.timing_3d_format;
--
--	/* Can be different depending on packet content */
--	length = 5;
--
--	if (stream->public.timing.hdmi_vic != 0
--			&& stream->public.timing.h_total >= 3840
--			&& stream->public.timing.v_total >= 2160)
--		hdmi_vic_mode = true;
--
--	/* According to HDMI 1.4a CTS, VSIF should be sent
--	 * for both 3D stereo and HDMI VIC modes.
--	 * For all other modes, there is no VSIF sent.  */
--
--	if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
--		return;
--
--	/* 24bit IEEE Registration identifier (0x000c03). LSB first. */
--	info_packet->sb[1] = 0x03;
--	info_packet->sb[2] = 0x0C;
--	info_packet->sb[3] = 0x00;
--
--	/*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
--	 * The value for HDMI_Video_Format are:
--	 * 0x0 (0b000) - No additional HDMI video format is presented in this
--	 * packet
--	 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
--	 * parameter follows
--	 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
--	 * potentially 3D_Ext_Data follows
--	 * 0x3..0x7 (0b011..0b111) - reserved for future use */
--	if (format != TIMING_3D_FORMAT_NONE)
--		info_packet->sb[4] = (2 << 5);
--	else if (hdmi_vic_mode)
--		info_packet->sb[4] = (1 << 5);
--
--	/* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
--	 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
--	 * The value for 3D_Structure are:
--	 * 0x0 - Frame Packing
--	 * 0x1 - Field Alternative
--	 * 0x2 - Line Alternative
--	 * 0x3 - Side-by-Side (full)
--	 * 0x4 - L + depth
--	 * 0x5 - L + depth + graphics + graphics-depth
--	 * 0x6 - Top-and-Bottom
--	 * 0x7 - Reserved for future use
--	 * 0x8 - Side-by-Side (Half)
--	 * 0x9..0xE - Reserved for future use
--	 * 0xF - Not used */
--	switch (format) {
--	case TIMING_3D_FORMAT_HW_FRAME_PACKING:
--	case TIMING_3D_FORMAT_SW_FRAME_PACKING:
--		info_packet->sb[5] = (0x0 << 4);
--		break;
--
--	case TIMING_3D_FORMAT_SIDE_BY_SIDE:
--	case TIMING_3D_FORMAT_SBS_SW_PACKED:
--		info_packet->sb[5] = (0x8 << 4);
--		length = 6;
--		break;
--
--	case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
--	case TIMING_3D_FORMAT_TB_SW_PACKED:
--		info_packet->sb[5] = (0x6 << 4);
--		break;
--
--	default:
--		break;
--	}
--
--	/*PB5: If PB4 is set to 0x1 (extended resolution format)
--	 * fill PB5 with the correct HDMI VIC code */
--	if (hdmi_vic_mode)
--		info_packet->sb[5] = stream->public.timing.hdmi_vic;
--
--	/* Header */
--	info_packet->hb0 = 0x81; /* VSIF packet type. */
--	info_packet->hb1 = 0x01; /* Version */
--
--	/* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
--	info_packet->hb2 = (uint8_t) (length);
--
--	/* Calculate checksum */
--	checksum = 0;
--	checksum += info_packet->hb0;
--	checksum += info_packet->hb1;
--	checksum += info_packet->hb2;
--
--	for (i = 1; i <= length; i++)
--		checksum += info_packet->sb[i];
--
--	info_packet->sb[0] = (uint8_t) (0x100 - checksum);
--
--	info_packet->valid = true;
--}
--
--void dce_base_build_info_frame(struct core_stream *stream)
--{
--	enum signal_type signal = SIGNAL_TYPE_NONE;
--	struct hw_info_frame info_frame = { { 0 } };
--
--	/* default all packets to invalid */
--	info_frame.avi_info_packet.valid = false;
--	info_frame.gamut_packet.valid = false;
--	info_frame.vendor_info_packet.valid = false;
--	info_frame.spd_packet.valid = false;
--	info_frame.vsc_packet.valid = false;
--
--	signal = stream->sink->public.sink_signal;
--
--	/* HDMi and DP have different info packets*/
--	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
--		set_avi_info_frame(&info_frame.avi_info_packet,
--				stream);
--		set_vendor_info_packet(stream, &info_frame.vendor_info_packet);
--	}
--
--	translate_info_frame(&info_frame,
--			&stream->encoder_info_frame);
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h b/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h
-deleted file mode 100644
-index eec06f0..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dce_base/dce_base_resource.h
-+++ /dev/null
-@@ -1,37 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DCE_BASE_RESOURCE_H__
--#define __DCE_BASE_RESOURCE_H__
--
--#include "dc_services.h"
--#include "resource.h"
--
--void dce_base_build_info_frame(struct core_stream *stream);
--
--enum dc_status dce_base_map_resources(
--	const struct dc *dc,
--	struct validate_context *context);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 80a67c9..fac4c8b 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -65,4 +65,10 @@ void pplib_apply_display_requirements(
- 	const struct dc *dc,
- 	const struct validate_context *context);
- 
-+void build_info_frame(struct core_stream *stream);
-+
-+enum dc_status map_resources(
-+	const struct dc *dc,
-+	struct validate_context *context);
-+
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0703-drm-amd-dal-Override-some-virtual-functions-for-Diag.patch b/common/recipes-kernel/linux/files/0703-drm-amd-dal-Override-some-virtual-functions-for-Diag.patch
deleted file mode 100644
index ab27d06e..00000000
--- a/common/recipes-kernel/linux/files/0703-drm-amd-dal-Override-some-virtual-functions-for-Diag.patch
+++ /dev/null
@@ -1,1709 +0,0 @@
-From 060a4205ae78b9cb3ffafcf0078c4011ca20d8ee Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Tue, 19 Jan 2016 13:43:50 -0500
-Subject: [PATCH 0703/1110] drm/amd/dal: Override some virtual functions for
- Diagnostics use.
-
-This will prevent access to registers which are non-existent on
-FPGA emulation.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   2 +
- drivers/gpu/drm/amd/dal/dc/adapter/Makefile        |   6 +
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   | 180 +++++++++++++--------
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h   |   4 +-
- .../diagnostics/hw_ctx_adapter_service_diag.c      | 133 +++++++++++++++
- .../diagnostics/hw_ctx_adapter_service_diag.h      |  33 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   6 +
- drivers/gpu/drm/amd/dal/dc/gpio/Makefile           |   8 +
- .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c  |  98 +++++++++++
- .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h  |  34 ++++
- .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c  |  70 ++++++++
- .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.h  |  32 ++++
- .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c  | 102 ++++++++++++
- .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h  |  35 ++++
- .../dal/dc/gpio/diagnostics/hw_translate_diag.c    |  42 +++++
- .../dal/dc/gpio/diagnostics/hw_translate_diag.h    |  34 ++++
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     |   9 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |  14 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h       |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |  13 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h     |   3 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/Makefile         |  10 ++
- .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c    | 113 +++++++++++++
- .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h    |  33 ++++
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |  11 ++
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |   6 +
- .../amd/dal/include/adapter_service_interface.h    |   4 +
- drivers/gpu/drm/amd/dal/include/dal_types.h        |   7 +
- .../drm/amd/dal/include/gpio_service_interface.h   |   3 +-
- 29 files changed, 973 insertions(+), 75 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 9879512..7614ac8 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -527,6 +527,8 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
- 	init_data.display_param.bool_param_values |=
- 		1 << DAL_PARAM_ENABLE_GPU_SCALING;
- 
-+	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
-+
- 	/* Display Core create. */
- 	adev->dm.dc = dc_create(&init_data);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-index 8ede504..2c6ca7a 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-@@ -16,3 +16,9 @@ AMD_DAL_FILES += $(AMD_DAL_ADAPTER)
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce110/hw_ctx_adapter_service_dce110.o
- endif
-+
-+###############################################################################
-+# FPGA Diagnositcs
-+###############################################################################
-+
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.o
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index b3b3be7..b8d6033 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -45,6 +45,8 @@
- #include "dce110/hw_ctx_adapter_service_dce110.h"
- #endif
- 
-+#include "diagnostics/hw_ctx_adapter_service_diag.h"
-+
- /*
-  * Adapter service feature entry table.
-  *
-@@ -224,6 +226,7 @@ static void initialize_backlight_caps(
- 	struct platform_info_params params;
- 	bool custom_curve_present = false;
- 	bool custom_min_max_present = false;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	if (!(PM_GET_EXTENDED_BRIGHNESS_CAPS & as->platform_methods_mask)) {
- 			dal_logger_write(as->ctx->logger,
-@@ -233,8 +236,8 @@ static void initialize_backlight_caps(
- 			return;
- 	}
- 
--	if (as->dcb->funcs->get_firmware_info(as->dcb, &fw_info) != BP_RESULT_OK ||
--		as->dcb->funcs->get_embedded_panel_info(as->dcb, &panel_info) != BP_RESULT_OK)
-+	if (dcb->funcs->get_firmware_info(dcb, &fw_info) != BP_RESULT_OK ||
-+		dcb->funcs->get_embedded_panel_info(dcb, &panel_info) != BP_RESULT_OK)
- 		return;
- 
- 	params.data = &caps;
-@@ -550,8 +553,9 @@ static bool get_hpd_info(struct adapter_service *as,
- 	struct graphics_object_id id,
- 	struct graphics_object_hpd_info *info)
- {
--	return BP_RESULT_OK ==
--		as->dcb->funcs->get_hpd_info(as->dcb, id, info);
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	return BP_RESULT_OK == dcb->funcs->get_hpd_info(dcb, id, info);
- }
- 
- /*
-@@ -662,8 +666,16 @@ static bool generate_feature_set(
-  */
- static struct hw_ctx_adapter_service *create_hw_ctx(
- 	enum dce_version dce_version,
-+	enum dce_environment dce_environment,
- 	struct dc_context *ctx)
- {
-+	switch (dce_environment) {
-+	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+		return dal_adapter_service_create_hw_ctx_diag(ctx);
-+	default:
-+		break;
-+	}
-+
- 	switch (dce_version) {
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
-@@ -683,12 +695,20 @@ static struct hw_ctx_adapter_service *create_hw_ctx(
- static void adapter_service_destruct(
- 	struct adapter_service *as)
- {
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
- 	dal_adapter_service_destroy_hw_ctx(&as->hw_ctx);
- 	dal_i2caux_destroy(&as->i2caux);
- 	dal_gpio_service_destroy(&as->gpio_service);
- 	dal_asic_capability_destroy(&as->asic_cap);
--	as->dcb->funcs->destroy_integrated_info(as->dcb, &as->integrated_info);
--	dal_bios_parser_destroy(&as->dcb);
-+
-+	dcb->funcs->destroy_integrated_info(dcb, &as->integrated_info);
-+
-+	if (as->dcb_internal) {
-+		/* We are responsible only for destruction of Internal BIOS.
-+		 * The External one will be destroyed by its creator. */
-+		dal_bios_parser_destroy(&as->dcb_internal);
-+	}
- }
- 
- /*
-@@ -700,6 +720,9 @@ static bool adapter_service_construct(
- 	struct adapter_service *as,
- 	struct as_init_data *init_data)
- {
-+	struct dc_bios *dcb;
-+	enum dce_version dce_version;
-+
- 	if (!init_data)
- 		return false;
- 
-@@ -734,25 +757,32 @@ static bool adapter_service_construct(
- 		goto failed_to_generate_features;
- 	}
- 
-+	as->dce_environment = init_data->dce_environment;
-+
- 	if (init_data->vbios_override)
--		as->dcb = init_data->vbios_override;
-+		as->dcb_override = init_data->vbios_override;
- 	else {
- 		/* Create BIOS parser */
- 		init_data->bp_init_data.ctx = init_data->ctx;
- 
--		as->dcb = dal_bios_parser_create(&init_data->bp_init_data, as);
--	}
-+		as->dcb_internal = dal_bios_parser_create(
-+				&init_data->bp_init_data, as);
- 
--	if (!as->dcb) {
--		ASSERT_CRITICAL(false);
--		goto failed_to_create_bios_parser;
-+		if (!as->dcb_internal) {
-+			ASSERT_CRITICAL(false);
-+			goto failed_to_create_bios_parser;
-+		}
- 	}
- 
-+	dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	dce_version = dal_adapter_service_get_dce_version(as);
-+
- 	/* Create GPIO service */
--	as->gpio_service =
--		dal_gpio_service_create(
--				dal_adapter_service_get_dce_version(as),
--				as->ctx);
-+	as->gpio_service = dal_gpio_service_create(
-+			dce_version,
-+			as->dce_environment,
-+			as->ctx);
- 
- 	if (!as->gpio_service) {
- 		ASSERT_CRITICAL(false);
-@@ -769,8 +799,9 @@ static bool adapter_service_construct(
- 
- 	/* Create Adapter Service HW Context*/
- 	as->hw_ctx = create_hw_ctx(
--		dal_adapter_service_get_dce_version(as),
--		as->ctx);
-+			dce_version,
-+			as->dce_environment,
-+			as->ctx);
- 
- 	if (!as->hw_ctx) {
- 		ASSERT_CRITICAL(false);
-@@ -780,10 +811,9 @@ static bool adapter_service_construct(
- 	/* Avoid wireless encoder creation in upstream branch. */
- 
- 	/* Integrated info is not provided on discrete ASIC. NULL is allowed */
--	as->integrated_info = as->dcb->funcs->create_integrated_info(
--			as->dcb);
-+	as->integrated_info = dcb->funcs->create_integrated_info(dcb);
- 
--	as->dcb->funcs->post_init(as->dcb);
-+	dcb->funcs->post_init(dcb);
- 
- 	/* Generate backlight translation table and initializes
- 			  other brightness properties */
-@@ -805,7 +835,8 @@ failed_to_create_i2caux:
- 	dal_gpio_service_destroy(&as->gpio_service);
- 
- failed_to_create_gpio_service:
--	dal_bios_parser_destroy(&as->dcb);
-+	if (as->dcb_internal)
-+		dal_bios_parser_destroy(&as->dcb_internal);
- 
- failed_to_create_bios_parser:
- 	dal_asic_capability_destroy(&as->asic_cap);
-@@ -890,6 +921,13 @@ enum dce_version dal_adapter_service_get_dce_version(
- 	}
- }
- 
-+enum dce_environment dal_adapter_service_get_dce_environment(
-+	const struct adapter_service *as)
-+{
-+	return as->dce_environment;
-+}
-+
-+
- /*
-  * dal_adapter_service_get_controllers_num
-  *
-@@ -956,10 +994,12 @@ static bool is_wireless_object(struct graphics_object_id id)
- uint32_t dal_adapter_service_get_src_num(
- 	struct adapter_service *as, struct graphics_object_id id)
- {
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
- 	if (is_wireless_object(id))
- 		return wireless_get_srcs_num(as, id);
- 	else
--		return as->dcb->funcs->get_src_number(as->dcb, id);
-+		return dcb->funcs->get_src_number(dcb, id);
- }
- 
- /**
-@@ -979,18 +1019,19 @@ struct graphics_object_id dal_adapter_service_get_src_obj(
- 	uint32_t index)
- {
- 	struct graphics_object_id src_object_id;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	if (is_wireless_object(id))
- 		src_object_id = wireless_get_src_obj_id(as, id, index);
- 	else {
--		if (BP_RESULT_OK !=
--			as->dcb->funcs->get_src_obj(
--				as->dcb, id, index, &src_object_id))
-+		if (BP_RESULT_OK != dcb->funcs->get_src_obj(dcb, id, index,
-+				&src_object_id)) {
- 			src_object_id =
- 				dal_graphics_object_id_init(
- 					0,
- 					ENUM_ID_UNKNOWN,
- 					OBJECT_TYPE_UNKNOWN);
-+		}
- 	}
- 
- 	return src_object_id;
-@@ -1017,13 +1058,9 @@ struct graphics_object_id dal_adapter_service_get_connector_obj_id(
- 	bios_connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
- 	if (connector_index >= bios_connectors_num)
--		return wireless_get_connector_id(
--				as,
--				connector_index);
-+		return wireless_get_connector_id(as, connector_index);
- 	else
--		return as->dcb->funcs->get_connector_id(
--				as->dcb,
--				connector_index);
-+		return dcb->funcs->get_connector_id(dcb, connector_index);
- }
- 
- bool dal_adapter_service_get_device_tag(
-@@ -1032,7 +1069,9 @@ bool dal_adapter_service_get_device_tag(
- 		uint32_t device_tag_index,
- 		struct connector_device_tag_info *info)
- {
--	if (BP_RESULT_OK == as->dcb->funcs->get_device_tag(as->dcb,
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	if (BP_RESULT_OK == dcb->funcs->get_device_tag(dcb,
- 			connector_object_id, device_tag_index, info))
- 		return true;
- 	else
-@@ -1043,7 +1082,9 @@ bool dal_adapter_service_get_device_tag(
- bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
- 		struct device_id id)
- {
--	return as->dcb->funcs->is_device_id_supported(as->dcb, id);
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	return dcb->funcs->is_device_id_supported(dcb, id);
- }
- 
- bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as)
-@@ -1080,14 +1121,13 @@ uint8_t dal_adapter_service_get_clock_sources_num(
- 	struct firmware_info fw_info;
- 	uint32_t max_clk_src = 0;
- 	uint32_t num = as->asic_cap->data[ASIC_DATA_CLOCKSOURCES_NUM];
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	/*
- 	 * Check is system supports the use of the External clock source
- 	 * as a clock source for DP
- 	 */
--	enum bp_result bp_result =
--			as->dcb->funcs->get_firmware_info(as->dcb,
--					&fw_info);
-+	enum bp_result bp_result = dcb->funcs->get_firmware_info(dcb, &fw_info);
- 
- 	if (BP_RESULT_OK == bp_result &&
- 			fw_info.external_clock_source_frequency_for_dp != 0)
-@@ -1199,13 +1239,14 @@ bool dal_adapter_service_get_i2c_info(
- 	struct graphics_object_id id,
- 	struct graphics_object_i2c_info *i2c_info)
- {
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
- 	if (!i2c_info) {
- 		ASSERT_CRITICAL(false);
- 		return false;
- 	}
- 
--	return BP_RESULT_OK ==
--		as->dcb->funcs->get_i2c_info(as->dcb, id, i2c_info);
-+	return BP_RESULT_OK == dcb->funcs->get_i2c_info(dcb, id, i2c_info);
- }
- 
- /*
-@@ -1256,14 +1297,14 @@ struct irq *dal_adapter_service_obtain_hpd_irq(
- 	struct graphics_object_id id)
- {
- 	enum bp_result bp_result;
--
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 	struct graphics_object_hpd_info hpd_info;
- 	struct gpio_pin_info pin_info;
- 
- 	if (!get_hpd_info(as, id, &hpd_info))
- 		return NULL;
- 
--	bp_result = as->dcb->funcs->get_gpio_pin_info(as->dcb,
-+	bp_result = dcb->funcs->get_gpio_pin_info(dcb,
- 		hpd_info.hpd_int_gpio_uid, &pin_info);
- 
- 	if (bp_result != BP_RESULT_OK) {
-@@ -1298,7 +1339,9 @@ uint32_t dal_adapter_service_get_ss_info_num(
- 	struct adapter_service *as,
- 	enum as_signal_type signal)
- {
--	return as->dcb->funcs->get_ss_entry_number(as->dcb, signal);
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	return dcb->funcs->get_ss_entry_number(dcb, signal);
- }
- 
- /*
-@@ -1312,9 +1355,10 @@ bool dal_adapter_service_get_ss_info(
- 	uint32_t idx,
- 	struct spread_spectrum_info *info)
- {
--	enum bp_result bp_result =
--		as->dcb->funcs->get_spread_spectrum_info(
--			as->dcb, signal, idx, info);
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	enum bp_result bp_result = dcb->funcs->get_spread_spectrum_info(dcb,
-+			signal, idx, info);
- 
- 	return BP_RESULT_OK == bp_result;
- }
-@@ -1521,17 +1565,18 @@ struct gpio *dal_adapter_service_obtain_stereo_gpio(
- 
- 		struct bp_gpio_cntl_info cntl_info;
- 		struct gpio_pin_info pin_info;
-+		struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 		/* Get GPIO record for this object.
- 		 * Stereo GPIO record should have exactly one entry
- 		 * where active state defines stereosync polarity */
--		if (1 != as->dcb->funcs->get_gpio_record(
--						as->dcb, id, &cntl_info,
-+		if (1 != dcb->funcs->get_gpio_record(
-+						dcb, id, &cntl_info,
- 						1)) {
- 			return NULL;
- 		} else if (BP_RESULT_OK
--				!= as->dcb->funcs->get_gpio_pin_info(
--						as->dcb, cntl_info.id,
-+				!= dcb->funcs->get_gpio_pin_info(
-+						dcb, cntl_info.id,
- 						&pin_info)) {
- 			/*ASSERT_CRITICAL(false);*/
- 			return NULL;
-@@ -1564,8 +1609,9 @@ bool dal_adapter_service_get_firmware_info(
- 	struct adapter_service *as,
- 	struct firmware_info *info)
- {
--	return as->dcb->funcs->get_firmware_info(as->dcb, info) ==
--		BP_RESULT_OK;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	return dcb->funcs->get_firmware_info(dcb, info) == BP_RESULT_OK;
- }
- 
- /*
-@@ -1664,7 +1710,7 @@ uint32_t dal_adapter_service_get_memory_type_multiplier(
- struct dc_bios *dal_adapter_service_get_bios_parser(
- 	struct adapter_service *as)
- {
--	return as->dcb;
-+	return as->dcb_override ? as->dcb_override : as->dcb_internal;
- }
- 
- /*
-@@ -1751,12 +1797,13 @@ bool dal_adapter_service_get_embedded_panel_info(
- 	struct embedded_panel_info *info)
- {
- 	enum bp_result result;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	if (info == NULL)
- 		/*TODO: add DALASSERT_MSG here*/
- 		return false;
- 
--	result = as->dcb->funcs->get_embedded_panel_info(as->dcb, info);
-+	result = dcb->funcs->get_embedded_panel_info(dcb, info);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1767,13 +1814,13 @@ bool dal_adapter_service_enum_embedded_panel_patch_mode(
- 	struct embedded_panel_patch_mode *mode)
- {
- 	enum bp_result result;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	if (mode == NULL)
- 		/*TODO: add DALASSERT_MSG here*/
- 		return false;
- 
--	result = as->dcb->funcs->enum_embedded_panel_patch_mode(
--		as->dcb, index, mode);
-+	result = dcb->funcs->enum_embedded_panel_patch_mode(dcb, index, mode);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1783,8 +1830,9 @@ bool dal_adapter_service_get_faked_edid_len(
- 	uint32_t *len)
- {
- 	enum bp_result result;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	result = as->dcb->funcs->get_faked_edid_len(as->dcb, len);
-+	result = dcb->funcs->get_faked_edid_len(dcb, len);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1795,11 +1843,10 @@ bool dal_adapter_service_get_faked_edid_buf(
- 	uint32_t len)
- {
- 	enum bp_result result;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	result = dcb->funcs->get_faked_edid_buf(dcb, buf, len);
- 
--	result = as->dcb->funcs->get_faked_edid_buf(
--		as->dcb,
--		buf,
--		len);
- 	return result == BP_RESULT_OK;
- 
- }
-@@ -1886,7 +1933,9 @@ bool dal_adapter_service_should_optimize(
-  */
- bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as)
- {
--	return as->dcb->funcs->is_accelerated_mode(as->dcb);
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
-+
-+	return dcb->funcs->is_accelerated_mode(dcb);
- }
- 
- struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
-@@ -1927,6 +1976,7 @@ bool dal_adapter_service_is_lid_open(struct adapter_service *as)
- {
- 	bool is_lid_open = false;
- 	struct platform_info_params params;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	params.data = &is_lid_open;
- 	params.method = PM_GET_LID_STATE;
-@@ -1936,7 +1986,7 @@ bool dal_adapter_service_is_lid_open(struct adapter_service *as)
- 		return is_lid_open;
- 
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
--	return as->dcb->funcs->is_lid_open(as->dcb);
-+	return dcb->funcs->is_lid_open(dcb);
- #else
- 	return false;
- #endif
-@@ -2009,6 +2059,7 @@ bool dal_adapter_service_get_encoder_cap_info(
- {
- 	struct bp_encoder_cap_info bp_cap_info = {0};
- 	enum bp_result result;
-+	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	if (NULL == info) {
- 		ASSERT_CRITICAL(false);
-@@ -2023,10 +2074,7 @@ bool dal_adapter_service_get_encoder_cap_info(
- 	 * - dpHbr2Cap: indicates supported/not supported by HW Encoder
- 	 * - dpHbr2En : indicates DP spec compliant/not compliant
- 	 */
--	result = as->dcb->funcs->get_encoder_cap_info(
--			as->dcb,
--			id,
--			&bp_cap_info);
-+	result = dcb->funcs->get_encoder_cap_info(dcb, id, &bp_cap_info);
- 
- 	/* Set dp_hbr2_validated flag (it's equal to Enable) */
- 	info->dp_hbr2_validated = bp_cap_info.DP_HBR2_EN;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-index 5bb4446..60464e8 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -42,7 +42,9 @@ struct asic_cap;
- struct adapter_service {
- 	struct dc_context *ctx;
- 	struct asic_capability *asic_cap;
--	struct dc_bios *dcb;
-+	struct dc_bios *dcb_internal;/* created by DC */
-+	struct dc_bios *dcb_override;/* supplied by creator of DC */
-+	enum dce_environment dce_environment;
- 	struct gpio_service *gpio_service;
- 	struct i2caux *i2caux;
- 	struct wireless_data wireless_data;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-new file mode 100644
-index 0000000..de45ce3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-@@ -0,0 +1,133 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/* FPGA Diagnostics version of AS HW CTX. */
-+
-+#include "dal_services.h"
-+
-+#include "../hw_ctx_adapter_service.h"
-+
-+#include "hw_ctx_adapter_service_diag.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/grph_object_id.h"
-+
-+static const struct graphics_object_id invalid_go = {
-+	0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN
-+};
-+
-+static void destroy(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+}
-+
-+static bool power_up(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	return true;
-+}
-+
-+static struct graphics_object_id enum_fake_path_resource(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_stereo_sync_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_sync_output_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_audio_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static void update_audio_connectivity(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t number_of_audio_capable_display_path,
-+	uint32_t number_of_controllers)
-+{
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+	destroy,
-+	power_up,
-+	enum_fake_path_resource,
-+	enum_stereo_sync_object,
-+	enum_sync_output_object,
-+	enum_audio_object,
-+	update_audio_connectivity
-+};
-+
-+static bool construct(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	struct dc_context *ctx)
-+
-+{
-+	if (!dal_adapter_service_construct_hw_ctx(hw_ctx, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	hw_ctx->funcs = &funcs;
-+
-+	return true;
-+}
-+
-+struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
-+	struct dc_context *ctx)
-+{
-+	struct hw_ctx_adapter_service *hw_ctx = dc_service_alloc(ctx,
-+			sizeof(*hw_ctx));
-+
-+	if (!hw_ctx) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(hw_ctx, ctx))
-+		return hw_ctx;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, hw_ctx);
-+
-+	return NULL;
-+}
-+
-+/*****************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h
-new file mode 100644
-index 0000000..39ae752
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_DIAG_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_DIAG_H__
-+
-+
-+struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
-+		struct dc_context *ctx);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DIAG_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 4e87da5..14a1171 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -228,6 +228,7 @@ static struct adapter_service *create_as(
- 
- 	init_data.display_param = &init->display_param;
- 	init_data.vbios_override = init->vbios_override;
-+	init_data.dce_environment = init->dce_environment;
- 
- 	as = dal_adapter_service_create(&init_data);
- 
-@@ -334,6 +335,11 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 
- 	dc->ctx = dc_init_data.ctx;
- 
-+	dc->dce_version = dal_adapter_service_get_dce_version(
-+			dc_init_data.adapter_srv);
-+	dc->dce_environment = dal_adapter_service_get_dce_environment(
-+			dc_init_data.adapter_srv);
-+
- 	/* Create hardware sequencer */
- 	if (!dc_construct_hw_sequencer(dc_init_data.adapter_srv, dc))
- 		goto hwss_fail;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-index 7380910..50a1d34 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-@@ -22,3 +22,11 @@ AMD_DAL_GPIO_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpio/dce110/,$(GPIO_DCE110))
- AMD_DAL_FILES += $(AMD_DAL_GPIO_DCE110)
- endif
- 
-+###############################################################################
-+# Diagnostics on FPGA
-+###############################################################################
-+GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o hw_hpd_diag.o hw_ddc_diag.o
-+
-+AMD_DAL_GPIO_DIAG_FPGA = $(addprefix $(AMDDALPATH)/dc/gpio/diagnostics/,$(GPIO_DIAG_FPGA))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPIO_DIAG_FPGA)
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-new file mode 100644
-index 0000000..f566241
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+
-+/*
-+ * This unit
-+ */
-+static void destruct(
-+	struct hw_ddc *pin)
-+{
-+	dal_hw_ddc_destruct(pin);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr);
-+
-+	destruct(pin);
-+
-+	dc_service_free((*ptr)->ctx, pin);
-+
-+	*ptr = NULL;
-+}
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = NULL,
-+	.get_value = NULL,
-+	.set_value = NULL,
-+	.set_config = NULL,
-+	.change_mode = NULL,
-+	.close = NULL,
-+};
-+
-+static bool construct(
-+	struct hw_ddc *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	pin->base.base.funcs = &funcs;
-+	return true;
-+}
-+
-+struct hw_gpio_pin *dal_hw_ddc_diag_fpga_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_ddc *pin = dc_service_alloc(ctx, sizeof(struct hw_ddc));
-+
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(pin, id, en, ctx))
-+		return &pin->base.base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, pin);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h
-new file mode 100644
-index 0000000..7515aaf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_DDC_DIAG_FPGA_H__
-+#define __DAL_HW_DDC_DIAG_FPGA_H__
-+
-+struct hw_gpio_pin *dal_hw_ddc_diag_fpga_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-new file mode 100644
-index 0000000..13b69e2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-@@ -0,0 +1,70 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dal_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+/* function table */
-+static const struct hw_factory_funcs funcs = {
-+	.create_dvo = NULL,
-+	.create_ddc_data = NULL,
-+	.create_ddc_clock = NULL,
-+	.create_generic = NULL,
-+	.create_hpd = NULL,
-+	.create_gpio_pad = NULL,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+};
-+
-+void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
-+{
-+	factory->number_of_pins[GPIO_ID_DVO1] = 24;
-+	factory->number_of_pins[GPIO_ID_DVO12] = 2;
-+	factory->number_of_pins[GPIO_ID_DVO24] = 1;
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.h b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.h
-new file mode 100644
-index 0000000..8a74f6a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DIAG_FPGA_H__
-+#define __DAL_HW_FACTORY_DIAG_FPGA_H__
-+
-+/* Initialize HW factory function pointers and pin info */
-+void dal_hw_factory_diag_fpga_init(struct hw_factory *factory);
-+
-+#endif /* __DAL_HW_FACTORY_DIAG_FPGA_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-new file mode 100644
-index 0000000..baf5caf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/gpio_types.h"
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_hpd.h"
-+
-+
-+static void destruct(
-+	struct hw_hpd *pin)
-+{
-+	dal_hw_hpd_destruct(pin);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_hpd *pin = HW_HPD_FROM_BASE(*ptr);
-+
-+	destruct(pin);
-+
-+	dc_service_free((*ptr)->ctx, pin);
-+
-+	*ptr = NULL;
-+}
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = NULL,
-+	.get_value = NULL,
-+	.set_value = NULL,
-+	.set_config = NULL,
-+	.change_mode = NULL,
-+	.close = NULL,
-+};
-+
-+static bool construct(
-+	struct hw_hpd *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_hw_hpd_construct(pin, id, en, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	pin->base.base.funcs = &funcs;
-+
-+	return true;
-+}
-+
-+struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_hpd *pin = dc_service_alloc(ctx, sizeof(struct hw_hpd));
-+
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(pin, id, en, ctx))
-+		return &pin->base.base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, pin);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h
-new file mode 100644
-index 0000000..bfa2c24
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_HPD_DIAG_FPGA_H__
-+#define __DAL_HW_HPD_DIAG_FPGA_H__
-+
-+
-+struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif /*__DAL_HW_HPD_DIAG_FPGA_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-new file mode 100644
-index 0000000..6d4da30
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#include "dal_services.h"
-+#include "include/gpio_types.h"
-+
-+#include "../hw_translate.h"
-+
-+
-+/* function table */
-+static const struct hw_translate_funcs funcs = {
-+	.offset_to_id = NULL,
-+	.id_to_offset = NULL,
-+};
-+
-+void dal_hw_translate_diag_fpga_init(struct hw_translate *tr)
-+{
-+	tr->funcs = &funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.h b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.h
-new file mode 100644
-index 0000000..4f05324
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-+#define __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-+
-+struct hw_translate;
-+
-+/* Initialize Hw translate function pointers */
-+void dal_hw_translate_diag_fpga_init(struct hw_translate *tr);
-+
-+#endif /* __DAL_HW_TRANSLATE_DIAG_FPGA_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-index 660f80f..3a6b5f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -63,7 +63,8 @@
-  */
- 
- struct gpio_service *dal_gpio_service_create(
--	enum dce_version dce_version,
-+	enum dce_version dce_version_major,
-+	enum dce_version dce_version_minor,
- 	struct dc_context *ctx)
- {
- 	struct gpio_service *service;
-@@ -77,12 +78,14 @@ struct gpio_service *dal_gpio_service_create(
- 		return NULL;
- 	}
- 
--	if (!dal_hw_translate_init(&service->translate, dce_version)) {
-+	if (!dal_hw_translate_init(&service->translate, dce_version_major,
-+			dce_version_minor)) {
- 		BREAK_TO_DEBUGGER();
- 		goto failure_1;
- 	}
- 
--	if (!dal_hw_factory_init(&service->factory, dce_version)) {
-+	if (!dal_hw_factory_init(&service->factory, dce_version_major,
-+			dce_version_minor)) {
- 		BREAK_TO_DEBUGGER();
- 		goto failure_1;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index d1b6b7e..a01024e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -44,14 +44,26 @@
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/hw_factory_dce110.h"
- #endif
-+
-+#include "diagnostics/hw_factory_diag.h"
-+
- /*
-  * This unit
-  */
- 
- bool dal_hw_factory_init(
- 	struct hw_factory *factory,
--	enum dce_version dce_version)
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment)
- {
-+	switch (dce_environment) {
-+	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+		dal_hw_factory_diag_fpga_init(factory);
-+		return true;
-+	default:
-+		break;
-+	}
-+
- 	switch (dce_version) {
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-index f16678c..7fef3fa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-@@ -69,6 +69,7 @@ struct hw_factory {
- 
- bool dal_hw_factory_init(
- 	struct hw_factory *factory,
--	enum dce_version dce_version);
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment);
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index 96e135f..d49e952 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -45,14 +45,25 @@
- #include "dce110/hw_translate_dce110.h"
- #endif
- 
-+#include "diagnostics/hw_translate_diag.h"
-+
- /*
-  * This unit
-  */
- 
- bool dal_hw_translate_init(
- 	struct hw_translate *translate,
--	enum dce_version dce_version)
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment)
- {
-+	switch (dce_environment) {
-+	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+		dal_hw_translate_diag_fpga_init(translate);
-+		return true;
-+	default:
-+		break;
-+	}
-+
- 	switch (dce_version) {
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
-index d5740ac..3a7d89c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h
-@@ -44,6 +44,7 @@ struct hw_translate {
- 
- bool dal_hw_translate_init(
- 	struct hw_translate *translate,
--	enum dce_version dce_version);
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment);
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-index 15902a8..390d83d 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-@@ -21,3 +21,13 @@ AMD_DAL_I2CAUX_DCE110 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce110/,$(I2CAUX_DCE
- 
- AMD_DAL_FILES += $(AMD_DAL_I2CAUX_DCE110)
- endif
-+
-+###############################################################################
-+# Diagnostics on FPGA
-+###############################################################################
-+I2CAUX_DIAG = i2caux_diag.o
-+
-+AMD_DAL_I2CAUX_DIAG = $(addprefix $(AMDDALPATH)/dc/i2caux/diagnostics/,$(I2CAUX_DIAG))
-+
-+AMD_DAL_FILES += $(AMD_DAL_I2CAUX_DIAG)
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-new file mode 100644
-index 0000000..86b606d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-@@ -0,0 +1,113 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "i2caux_diag.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+static void destruct(
-+	struct i2caux *i2caux)
-+{
-+	dal_i2caux_destruct(i2caux);
-+}
-+
-+static void destroy(
-+	struct i2caux **i2c_engine)
-+{
-+	destruct(*i2c_engine);
-+
-+	dc_service_free((*i2c_engine)->ctx, *i2c_engine);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+
-+
-+/* function table */
-+static const struct i2caux_funcs i2caux_funcs = {
-+	.destroy = destroy,
-+	.acquire_i2c_hw_engine = NULL,
-+	.release_engine = NULL,
-+	.acquire_i2c_sw_engine = NULL,
-+	.acquire_aux_engine = NULL,
-+};
-+
-+static bool construct(
-+	struct i2caux *i2caux,
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_i2caux_construct(i2caux, as, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	i2caux->funcs = &i2caux_funcs;
-+
-+	return true;
-+}
-+
-+struct i2caux *dal_i2caux_diag_fpga_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	struct i2caux *i2caux =	dc_service_alloc(ctx, sizeof(struct i2caux));
-+
-+	if (!i2caux) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(i2caux, as, ctx))
-+		return i2caux;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dc_service_free(ctx, i2caux);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h
-new file mode 100644
-index 0000000..3de250b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DIAG_FPGA_H__
-+#define __DAL_I2C_AUX_DIAG_FPGA_H__
-+
-+struct i2caux *dal_i2caux_diag_fpga_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DIAG_FPGA_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 50262a4..6de108c 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -53,6 +53,8 @@
- #include "dce110/i2caux_dce110.h"
- #endif
- 
-+#include "diagnostics/i2caux_diag.h"
-+
- /*
-  * @brief
-  * Plain API, available publicly
-@@ -63,6 +65,7 @@ struct i2caux *dal_i2caux_create(
- 	struct dc_context *ctx)
- {
- 	enum dce_version dce_version;
-+	enum dce_environment dce_environment;
- 
- 	if (!as) {
- 		BREAK_TO_DEBUGGER();
-@@ -70,6 +73,14 @@ struct i2caux *dal_i2caux_create(
- 	}
- 
- 	dce_version = dal_adapter_service_get_dce_version(as);
-+	dce_environment = dal_adapter_service_get_dce_environment(as);
-+
-+	switch (dce_environment) {
-+	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+		return dal_i2caux_diag_fpga_create(as, ctx);
-+	default:
-+		break;
-+	}
- 
- 	switch (dce_version) {
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index 9d62a24..be46f97 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -34,6 +34,12 @@ struct dc {
- 
- 	/* HW functions */
- 	struct hw_sequencer_funcs hwss;
-+
-+	/* Diagnostics */
-+	enum dce_version dce_version;
-+	enum dce_environment dce_environment;
- };
- 
-+#define IS_DIAGNOSTICS_DC(dc) ((dc)->dce_environment == DCE_ENV_DIAG_FPGA_MAXIMUS)
-+
- #endif /* __CORE_DC_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-index 2851266..8ebbe65 100644
---- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-@@ -322,6 +322,7 @@ struct as_init_data {
- 	struct bdf_info bdf_info;
- 	const struct dal_override_parameters *display_param;
- 	struct dc_bios *vbios_override;
-+	enum dce_environment dce_environment;
- };
- 
- /* Create adapter service */
-@@ -336,6 +337,9 @@ void dal_adapter_service_destroy(
- enum dce_version dal_adapter_service_get_dce_version(
- 	const struct adapter_service *as);
- 
-+enum dce_environment dal_adapter_service_get_dce_environment(
-+	const struct adapter_service *as);
-+
- /* Get firmware information from BIOS */
- bool dal_adapter_service_get_firmware_info(
- 	struct adapter_service *as,
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index caaacf6..f756d36 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -40,6 +40,12 @@ enum dce_version {
- 	DCE_VERSION_MAX
- };
- 
-+enum dce_environment {
-+	DCE_ENV_PRODUCTION_DRV = 0,
-+	DCE_ENV_DIAG_FPGA_MAXIMUS, /* Emulation on FPGA, in Maximus System. */
-+	DCE_ENV_DIAG_SILICON, /* Emulation on real HW */
-+};
-+
- /*
-  * ASIC Runtime Flags
-  */
-@@ -141,6 +147,7 @@ struct dal_init_data {
- 	/* If 'vbios_override' not NULL, it will be called instead
- 	 * of the real VBIOS. Intended use is Diagnostics on FPGA. */
- 	struct dc_bios *vbios_override;
-+	enum dce_environment dce_environment;
- };
- 
- struct dal_dc_init_data {
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-index b22bb1b..b4f30dd 100644
---- a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-@@ -35,7 +35,8 @@
- struct gpio_service;
- 
- struct gpio_service *dal_gpio_service_create(
--	enum dce_version dce_version,
-+	enum dce_version dce_version_major,
-+	enum dce_version dce_version_minor,
- 	struct dc_context *ctx);
- 
- struct gpio *dal_gpio_service_create_gpio(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0704-drm-amd-dal-optimize-out-dc-validation-on-flip.patch b/common/recipes-kernel/linux/files/0704-drm-amd-dal-optimize-out-dc-validation-on-flip.patch
deleted file mode 100644
index fd1962c5..00000000
--- a/common/recipes-kernel/linux/files/0704-drm-amd-dal-optimize-out-dc-validation-on-flip.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From f5db199898ea549bb38316a867e46bef41c96390 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 19 Jan 2016 16:31:57 -0500
-Subject: [PATCH 0704/1110] drm/amd/dal: optimize out dc validation on flip
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 04044ff..f2b25cd 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2395,6 +2395,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 	struct dc_target *new_targets[MAX_TARGET_NUM] = { 0 };
- 	struct amdgpu_device *adev = dev->dev_private;
- 	struct dc *dc = adev->dm.dc;
-+	bool need_to_validate = false;
- 
- 	ret = drm_atomic_helper_check(dev, state);
- 
-@@ -2480,6 +2481,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 					acrtc->target,
- 					new_target);
- 			new_target_count++;
-+			need_to_validate = true;
- 			break;
- 		}
- 
-@@ -2525,12 +2527,14 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 					set_count,
- 					acrtc->target,
- 					surface);
-+				need_to_validate = true;
- 			}
- 		}
- 
- 	}
- 
--	if (set_count == 0 || dc_validate_resources(dc, set, set_count))
-+	if (need_to_validate == false || set_count == 0
-+				|| dc_validate_resources(dc, set, set_count))
- 		ret = 0;
- 
- connector_not_found:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0705-drm-amd-dal-IPP-refactoring-part.patch b/common/recipes-kernel/linux/files/0705-drm-amd-dal-IPP-refactoring-part.patch
deleted file mode 100644
index b7e63ded..00000000
--- a/common/recipes-kernel/linux/files/0705-drm-amd-dal-IPP-refactoring-part.patch
+++ /dev/null
@@ -1,413 +0,0 @@
-From a3b2dec5c70efe7ebe3c65f164ad50fda6b51f33 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 19 Jan 2016 14:20:03 -0500
-Subject: [PATCH 0705/1110] drm/amd/dal: IPP refactoring part.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  5 ++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 23 ++++++-----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     | 46 ++++++----------------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     | 16 +++++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   | 14 ++-----
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 34 +++++++++++++++-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  8 ----
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               | 39 ++++++++++++++++++
- 8 files changed, 114 insertions(+), 71 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index b8420bf..e7df2e2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -26,6 +26,7 @@
- #include "core_types.h"
- #include "hw_sequencer.h"
- #include "resource.h"
-+#include "ipp.h"
- 
- #define COEFF_RANGE	3
- #define REGAMMA_COEFF_A0	31308
-@@ -364,7 +365,7 @@ bool dc_target_set_cursor_attributes(
- 		return false;
- 	}
- 
--	if (true == core_target->ctx->dc->hwss.cursor_set_attributes(ipp, attributes))
-+	if (true == ipp->funcs->ipp_cursor_set_attributes(ipp, attributes))
- 		return true;
- 
- 	return false;
-@@ -396,7 +397,7 @@ bool dc_target_set_cursor_position(
- 	}
- 
- 
--	if (true == core_target->ctx->dc->hwss.cursor_set_position(ipp, position))
-+	if (true == ipp->funcs->ipp_cursor_set_position(ipp, position))
- 		return true;
- 
- 	return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 612afe5..59a3bce 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -187,15 +187,15 @@ static bool set_gamma_ramp(
- 	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
- 		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
- 		/* do legacy DCP for 256 colors if we are requested to do so */
--		dce110_ipp_set_legacy_input_gamma_ramp(
-+		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
- 			ipp, ramp, params);
- 
--		dce110_ipp_set_legacy_input_gamma_mode(ipp, true);
-+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
- 
- 		/* set bypass */
--		dce110_ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
- 
--		dce110_ipp_set_degamma(ipp, params, true);
-+		ipp->funcs->ipp_set_degamma(ipp, params, true);
- 
- 		dce110_opp_set_regamma(opp, ramp, params, true);
- 	} else if (params->selected_gamma_lut ==
-@@ -208,21 +208,21 @@ static bool set_gamma_ramp(
- 		}
- 
- 		/* do legacy DCP for 256 colors if we are requested to do so */
--		dce110_ipp_set_legacy_input_gamma_ramp(
-+		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
- 			ipp, ramp, params);
- 
--		dce110_ipp_set_legacy_input_gamma_mode(ipp, true);
-+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
- 
- 		/* set bypass */
--		dce110_ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
- 	} else {
--		dce110_ipp_set_legacy_input_gamma_mode(ipp, false);
-+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, false);
- 
--		dce110_ipp_program_prescale(ipp, params->surface_pixel_format);
-+		ipp->funcs->ipp_program_prescale(ipp, params->surface_pixel_format);
- 
- 		/* Do degamma step : remove the given gamma value from FB.
- 		 * For FP16 or no degamma do by pass */
--		dce110_ipp_set_degamma(ipp, params, false);
-+		ipp->funcs->ipp_set_degamma(ipp, params, false);
- 
- 		dce110_opp_set_regamma(opp, ramp, params, false);
- 	}
-@@ -1741,6 +1741,7 @@ static void set_mst_bandwidth(struct stream_encoder *stream_enc,
- 		avg_time_slots_per_mtp);
- }
- 
-+
- static const struct hw_sequencer_funcs dce110_funcs = {
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
- 	.reset_hw_ctx = reset_hw_ctx,
-@@ -1748,8 +1749,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.update_plane_address = update_plane_address,
- 	.enable_memory_requests = enable_memory_request,
- 	.disable_memory_requests = disable_memory_requests,
--	.cursor_set_attributes = dce110_ipp_cursor_set_attributes,
--	.cursor_set_position = dce110_ipp_cursor_set_position,
- 	.set_gamma_ramp = set_gamma_ramp,
- 	.power_down = power_down,
- 	.enable_accelerated_mode = enable_accelerated_mode,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-index f45da2e..a29dc51 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -31,31 +31,29 @@
- 
- #include "dce110_ipp.h"
- 
--static const struct dce110_ipp_reg_offsets reg_offsets[] = {
--{
--	.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
--},
--{
--	.dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL),
--},
--{
--	.dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL),
--}
-+static struct ipp_funcs funcs = {
-+		.ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes,
-+		.ipp_cursor_set_position = dce110_ipp_cursor_set_position,
-+		.ipp_program_prescale = dce110_ipp_program_prescale,
-+		.ipp_set_degamma = dce110_ipp_set_degamma,
-+		.ipp_set_legacy_input_gamma_mode = dce110_ipp_set_legacy_input_gamma_mode,
-+		.ipp_set_legacy_input_gamma_ramp = dce110_ipp_set_legacy_input_gamma_ramp,
-+		.ipp_set_palette = dce110_ipp_set_palette,
- };
- 
- bool dce110_ipp_construct(
- 	struct dce110_ipp* ipp,
- 	struct dc_context *ctx,
--	uint32_t inst)
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offset)
- {
--	if (inst >= ARRAY_SIZE(reg_offsets))
--		return false;
--
- 	ipp->base.ctx = ctx;
- 
- 	ipp->base.inst = inst;
- 
--	ipp->offsets = reg_offsets[inst];
-+	ipp->offsets = *offset;
-+
-+	ipp->base.funcs = &funcs;
- 
- 	return true;
- }
-@@ -65,21 +63,3 @@ void dce110_ipp_destroy(struct input_pixel_processor **ipp)
- 	dc_service_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
- 	*ipp = NULL;
- }
--
--struct input_pixel_processor *dce110_ipp_create(
--	struct dc_context *ctx,
--	uint32_t inst)
--{
--	struct dce110_ipp *ipp =
--		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
--
--	if (!ipp)
--		return NULL;
--
--	if (dce110_ipp_construct(ipp, ctx, inst))
--			return &ipp->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, ipp);
--	return NULL;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index 1da42ff..f0e9e7d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -44,14 +44,11 @@ struct dce110_ipp {
- bool dce110_ipp_construct(
- 	struct dce110_ipp* ipp,
- 	struct dc_context *ctx,
--	enum controller_id id);
-+	enum controller_id id,
-+	const struct dce110_ipp_reg_offsets *offset);
- 
- void dce110_ipp_destroy(struct input_pixel_processor **ipp);
- 
--struct input_pixel_processor *dce110_ipp_create(
--	struct dc_context *ctx,
--	enum controller_id id);
--
- /* CURSOR RELATED */
- bool dce110_ipp_cursor_set_position(
- 	struct input_pixel_processor *ipp,
-@@ -87,4 +84,13 @@ bool dce110_ipp_set_palette(
- 	uint32_t length,
- 	enum pixel_format surface_pixel_format);
- 
-+/*
-+ * Helper functions to be resused in other ASICs
-+ */
-+void dce110_helper_select_lut(struct dce110_ipp *ipp110);
-+
-+void dce110_helper_program_black_white_offset(
-+	struct dce110_ipp *ipp110,
-+	enum pixel_format surface_pixel_format);
-+
- #endif /*__DC_IPP_DCE110_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index f2e8ef4..b7186b1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -76,8 +76,6 @@ static void set_lut_inc(
- 	bool is_float,
- 	bool is_signed);
- 
--static void select_lut(struct dce110_ipp *ipp110);
--
- static void program_black_offsets(
- 	struct dce110_ipp *ipp110,
- 	struct dev_c_lut16 *offset);
-@@ -86,10 +84,6 @@ static void program_white_offsets(
- 	struct dce110_ipp *ipp110,
- 	struct dev_c_lut16 *offset);
- 
--static void program_black_white_offset(
--	struct dce110_ipp *ipp110,
--	enum pixel_format surface_pixel_format);
--
- static void program_lut_gamma(
- 	struct dce110_ipp *ipp110,
- 	const struct dev_c_lut16 *gamma,
-@@ -264,7 +258,7 @@ static void set_lut_inc(
- 	dal_write_reg(ipp110->base.ctx, addr, value);
- }
- 
--static void select_lut(struct dce110_ipp *ipp110)
-+void dce110_helper_select_lut(struct dce110_ipp *ipp110)
- {
- 	uint32_t value = 0;
- 
-@@ -371,7 +365,7 @@ static void program_white_offsets(
- 		offset->blue);
- }
- 
--static void program_black_white_offset(
-+void dce110_helper_program_black_white_offset(
- 	struct dce110_ipp *ipp110,
- 	enum pixel_format surface_pixel_format)
- {
-@@ -482,9 +476,9 @@ static void program_lut_gamma(
- 		}
- 	}
- 
--	program_black_white_offset(ipp110, params->surface_pixel_format);
-+	dce110_helper_program_black_white_offset(ipp110, params->surface_pixel_format);
- 
--	select_lut(ipp110);
-+	dce110_helper_select_lut(ipp110);
- 
- 	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8) {
- 		addr = DCP_REG(mmDC_LUT_SEQ_COLOR);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 7880ccb..8f04707 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -122,6 +122,19 @@ static const struct dce110_transform_reg_offsets dce110_xfm_offsets[] = {
- }
- };
- 
-+static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
-+}
-+};
-+
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -207,6 +220,25 @@ static struct transform *dce110_transform_create(
- 	return NULL;
- }
- 
-+static struct input_pixel_processor *dce110_ipp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offsets)
-+{
-+	struct dce110_ipp *ipp =
-+		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
-+
-+	if (!ipp)
-+		return NULL;
-+
-+	if (dce110_ipp_construct(ipp, ctx, inst, offsets))
-+		return &ipp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, ipp);
-+	return NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -293,7 +325,7 @@ bool dce110_construct_resource_pool(
- 			goto controller_create_fail;
- 		}
- 
--		pool->ipps[i] = dce110_ipp_create(ctx, i);
-+		pool->ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]);
- 		if (pool->ipps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index a5ccb5e..59ed137 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -51,14 +51,6 @@ struct hw_sequencer_funcs {
- 
- 	bool (*transform_power_up)(struct transform *xfm);
- 
--	bool (*cursor_set_attributes)(
--				struct input_pixel_processor *ipp,
--				const struct dc_cursor_attributes *attributes);
--
--	bool (*cursor_set_position)(
--				struct input_pixel_processor *ipp,
--				const struct dc_cursor_position *position);
--
- 	bool (*set_gamma_ramp)(
- 					struct input_pixel_processor *ipp,
- 					struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index 602b4cb..20bb785 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -41,6 +41,7 @@
- struct input_pixel_processor {
- 	struct  dc_context *ctx;
- 	uint32_t inst;
-+	struct ipp_funcs *funcs;
- };
- 
- enum wide_gamut_degamma_mode {
-@@ -63,4 +64,42 @@ struct dcp_video_matrix {
- 	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
- };
- 
-+struct ipp_funcs {
-+
-+	/* CURSOR RELATED */
-+	bool (*ipp_cursor_set_position)(
-+		struct input_pixel_processor *ipp,
-+		const struct dc_cursor_position *position);
-+
-+	bool (*ipp_cursor_set_attributes)(
-+		struct input_pixel_processor *ipp,
-+		const struct dc_cursor_attributes *attributes);
-+
-+	/* DEGAMMA RELATED */
-+	bool (*ipp_set_degamma)(
-+		struct input_pixel_processor *ipp,
-+		const struct gamma_parameters *params,
-+		bool force_bypass);
-+
-+	void (*ipp_program_prescale)(
-+		struct input_pixel_processor *ipp,
-+		enum pixel_format pixel_format);
-+
-+	void (*ipp_set_legacy_input_gamma_mode)(
-+			struct input_pixel_processor *ipp,
-+			bool is_legacy);
-+
-+	bool (*ipp_set_legacy_input_gamma_ramp)(
-+		struct input_pixel_processor *ipp,
-+		const struct gamma_ramp *gamma_ramp,
-+		const struct gamma_parameters *params);
-+
-+	bool (*ipp_set_palette)(
-+		struct input_pixel_processor *ipp,
-+		const struct dev_c_lut *palette,
-+		uint32_t start,
-+		uint32_t length,
-+		enum pixel_format surface_pixel_format);
-+};
-+
- #endif /* __DAL_IPP_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0706-drm-amd-dal-Reset-DP_MSE_SAT-when-disabling-MST-disp.patch b/common/recipes-kernel/linux/files/0706-drm-amd-dal-Reset-DP_MSE_SAT-when-disabling-MST-disp.patch
deleted file mode 100644
index 01d71231..00000000
--- a/common/recipes-kernel/linux/files/0706-drm-amd-dal-Reset-DP_MSE_SAT-when-disabling-MST-disp.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 0294e1dd47e242d58e815adc9916df03f42b475e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 13 Jan 2016 22:44:36 -0500
-Subject: [PATCH 0706/1110] drm/amd/dal: Reset DP_MSE_SAT when disabling MST
- display
-
-SST display doesn't reliably light up when DP_MSE_SAT registers are
-set. Make sure we clear those when disabling an MST display.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c    | 20 ++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c |  6 ++++--
- 2 files changed, 16 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 46132f2..c8419a8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1416,6 +1416,7 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
- 	struct dc *dc = stream->ctx->dc;
- 	uint8_t i;
-+	bool mst_mode = (link->public.type == dc_connection_mst_branch);
- 
- 	/* deallocate_mst_payload is called before disable link. When mode or
- 	 * disable/enable monitor, new stream is created which is not in link
-@@ -1430,12 +1431,13 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 		avg_time_slots_per_mtp);
- 
- 	/* TODO: which component is responsible for remove payload table? */
--	dc_helpers_dp_mst_write_payload_allocation_table(
--		stream->ctx,
--		&stream->public,
--		&link->stream_alloc_table,
--		&proposed_table,
--		false);
-+	if (mst_mode)
-+		dc_helpers_dp_mst_write_payload_allocation_table(
-+				stream->ctx,
-+				&stream->public,
-+				&link->stream_alloc_table,
-+				&proposed_table,
-+				false);
- 
- 	dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_MST,
-@@ -1466,14 +1468,16 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 
- 	link->stream_alloc_table = proposed_table;
- 
--	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+	if (mst_mode) {
-+		dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
- 			&stream->public);
- 
--	dc_helpers_dp_mst_send_payload_allocation(
-+		dc_helpers_dp_mst_send_payload_allocation(
- 			stream->ctx,
- 			&stream->public,
- 			false);
-+	}
- 
- 	return DC_OK;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index eaea78e..c4cbede 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -989,10 +989,12 @@ static bool perform_clock_recovery_sequence(
- 	dal_logger_write(link->ctx->logger,
- 		LOG_MAJOR_MST,
- 		LOG_MINOR_MST_PROGRAMMING,
--		"Link training for %d lanes at %s rate %s\n",
-+		"Link training for %d lanes at %s rate %s with PE %d, VS %d\n",
- 		lt_settings.link_settings.lane_count,
- 		link_rate,
--		status ? "succeeded" : "failed");
-+		status ? "succeeded" : "failed",
-+		lt_settings.lane_settings[0].PRE_EMPHASIS,
-+		lt_settings.lane_settings[0].VOLTAGE_SWING);
- 
- 	return status;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0707-drm-amd-dal-Log-MST-branch-connect-disconnect.patch b/common/recipes-kernel/linux/files/0707-drm-amd-dal-Log-MST-branch-connect-disconnect.patch
deleted file mode 100644
index 30e19acf..00000000
--- a/common/recipes-kernel/linux/files/0707-drm-amd-dal-Log-MST-branch-connect-disconnect.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 39b33ac96c2a539e9ddb832ebe1ec69fbc77b02f Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 15 Jan 2016 08:58:53 -0500
-Subject: [PATCH 0707/1110] drm/amd/dal: Log MST branch connect/disconnect
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index c8419a8..3c96810 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -612,8 +612,11 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 			if (link->public.type == dc_connection_none)
- 				return true;
- 
--			if (link->public.type == dc_connection_mst_branch)
-+			if (link->public.type == dc_connection_mst_branch) {
-+				LINK_INFO("link=%d, mst branch is now Connected\n",
-+					link->public.link_index);
- 				return false;
-+			}
- 
- 			break;
- 		}
-@@ -712,8 +715,11 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 
- 	} else {
- 		/* From Connected-to-Disconnected. */
--		if (link->public.type == dc_connection_mst_branch)
-+		if (link->public.type == dc_connection_mst_branch) {
-+			LINK_INFO("link=%d, mst branch is now Disconnected\n",
-+				link->public.link_index);
- 			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
-+		}
- 
- 		link->public.type = dc_connection_none;
- 		sink_caps.signal = SIGNAL_TYPE_NONE;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0708-drm-amd-dal-Refactor-Link-Encoder.patch b/common/recipes-kernel/linux/files/0708-drm-amd-dal-Refactor-Link-Encoder.patch
deleted file mode 100644
index bda66a86..00000000
--- a/common/recipes-kernel/linux/files/0708-drm-amd-dal-Refactor-Link-Encoder.patch
+++ /dev/null
@@ -1,1169 +0,0 @@
-From b29a44047266c022dac059e93bf902cb078704ea Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Tue, 12 Jan 2016 16:53:50 -0500
-Subject: [PATCH 0708/1110] drm/amd/dal: Refactor Link Encoder
-
-DCE8, 11, etc. refactored with duplicate reduction.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  89 +++++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  31 ++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  63 ++---
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 306 ++++++++-------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  24 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  45 ++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.h    |   5 +
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |   5 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   7 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  37 ---
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |  40 +++
- drivers/gpu/drm/amd/dal/include/encoder_types.h    |   1 +
- 13 files changed, 348 insertions(+), 307 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 14a1171..e49ec86 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -175,7 +175,7 @@ static void init_hw(struct dc *dc)
- 		 * default signal on connector). */
- 		struct core_link *link = dc->links[i];
- 		if (link->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
--			dc->hwss.encoder_hw_init(link->link_enc);
-+			link->link_enc->funcs->hw_init(link->link_enc);
- 	}
- 
- 	for(i = 0; i < dc->res_pool.controller_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 3c96810..3f6a7bb 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -817,6 +817,71 @@ static enum channel_id get_ddc_line(struct core_link *link, struct adapter_servi
- 	return channel;
- }
- 
-+static enum transmitter translate_encoder_to_transmitter(
-+	struct graphics_object_id encoder)
-+{
-+	switch (encoder.id) {
-+	case ENCODER_ID_INTERNAL_UNIPHY:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_A;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_B;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY1:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_C;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_D;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY2:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_E;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_F;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY3:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_G;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_NUTMEG_CRT;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_TRAVIS_CRT;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_TRAVIS_LCD;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	default:
-+		return TRANSMITTER_UNKNOWN;
-+	}
-+}
-+
- 
- static bool construct(
- 	struct core_link *link,
-@@ -921,6 +986,8 @@ static bool construct(
- 	enc_init_data.connector = link->link_id;
- 	enc_init_data.channel = get_ddc_line(link, as);
- 	enc_init_data.hpd_source = get_hpd_line(link, as);
-+	enc_init_data.transmitter =
-+			translate_encoder_to_transmitter(enc_init_data.encoder);
- 	link->link_enc = dc_ctx->dc->hwss.encoder_create(&enc_init_data);
- 
- 	if( link->link_enc == NULL) {
-@@ -1146,8 +1213,8 @@ static void enable_link_hdmi(struct core_stream *stream)
- 	dc_service_memset(&stream->sink->link->cur_link_settings, 0,
- 			sizeof(struct link_settings));
- 
--	link->ctx->dc->hwss.encoder_enable_tmds_output(
--			stream->sink->link->link_enc,
-+	link->link_enc->funcs->enable_tmds_output(
-+			link->link_enc,
- 			dal_clock_source_get_id(stream->clock_source),
- 			stream->public.timing.display_color_depth,
- 			stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
-@@ -1198,8 +1265,6 @@ static enum dc_status enable_link(struct core_stream *stream)
- 
- static void disable_link(struct core_stream *stream)
- {
--	struct dc *dc = stream->ctx->dc;
--
- 	/* TODO  dp_set_hw_test_pattern */
- 
- 	/* here we need to specify that encoder output settings
-@@ -1217,8 +1282,10 @@ static void disable_link(struct core_stream *stream)
- 					stream->sink->link, stream);
- 		}
- 	} else {
--		dc->hwss.encoder_disable_output(
--				stream->sink->link->link_enc, stream->signal);
-+		struct link_encoder *encoder =
-+				stream->sink->link->link_enc;
-+
-+		encoder->funcs->disable_output(encoder, stream->signal);
- 	}
- }
- 
-@@ -1249,14 +1316,14 @@ enum dc_status dc_link_validate_mode_timing(
- 
- bool dc_link_set_backlight_level(const struct dc_link *public, uint32_t level)
- {
--	struct core_link *protected = DC_LINK_TO_CORE(public);
--	struct dc_context *ctx = protected->ctx;
-+	struct core_link *link = DC_LINK_TO_CORE(public);
-+	struct dc_context *ctx = link->ctx;
- 
- 	dal_logger_write(ctx->logger, LOG_MAJOR_BACKLIGHT,
- 			LOG_MINOR_BACKLIGHT_INTERFACE,
- 			"New Backlight level: %d (0x%X)\n", level, level);
- 
--	ctx->dc->hwss.encoder_set_lcd_backlight_level(protected->link_enc, level);
-+	link->link_enc->funcs->set_lcd_backlight_level(link->link_enc, level);
- 
- 	return true;
- }
-@@ -1383,7 +1450,7 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 		return DC_OK;
- 
- 	/* program DP source TX for payload */
--	dc->hwss.update_mst_stream_allocation_table(
-+	link_encoder->funcs->update_mst_stream_allocation_table(
- 		link_encoder,
- 		&proposed_table);
- 
-@@ -1468,7 +1535,7 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 		proposed_table.stream_allocations[i].slot_count);
- 	}
- 
--	dc->hwss.update_mst_stream_allocation_table(
-+	link_encoder->funcs->update_mst_stream_allocation_table(
- 		link_encoder,
- 		&proposed_table);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index e9ae9e1..8f1b869 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -56,16 +56,24 @@ void dp_enable_link_phy(
- 	enum signal_type signal,
- 	const struct link_settings *link_settings)
- {
--	if (dc_is_dp_sst_signal(signal))
--		link->dc->hwss.encoder_enable_dp_output(
--						link->link_enc,
-+	struct link_encoder *link_enc = link->link_enc;
-+
-+	if (dc_is_dp_sst_signal(signal)) {
-+		if (signal == SIGNAL_TYPE_EDP) {
-+			link_enc->funcs->power_control(link_enc, true);
-+			link_enc->funcs->backlight_control(link_enc, true);
-+		}
-+
-+		link_enc->funcs->enable_dp_output(
-+						link_enc,
- 						link_settings,
- 						CLOCK_SOURCE_ID_EXTERNAL);
--	else
--		link->dc->hwss.encoder_enable_dp_mst_output(
--						link->link_enc,
-+	} else {
-+		link_enc->funcs->enable_dp_mst_output(
-+						link_enc,
- 						link_settings,
- 						CLOCK_SOURCE_ID_EXTERNAL);
-+	}
- 
- 	dp_receiver_power_ctrl(link, true);
- }
-@@ -75,7 +83,10 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 	if (!link->wa_flags.dp_keep_receiver_powered)
- 		dp_receiver_power_ctrl(link, false);
- 
--	link->dc->hwss.encoder_disable_output(link->link_enc, signal);
-+	if (signal == SIGNAL_TYPE_EDP)
-+		link->link_enc->funcs->backlight_control(link->link_enc, false);
-+
-+	link->link_enc->funcs->disable_output(link->link_enc, signal);
- 
- 	/* Clear current link setting.*/
- 	dc_service_memset(&link->cur_link_settings, 0,
-@@ -118,7 +129,7 @@ bool dp_set_hw_training_pattern(
- 	pattern_param.custom_pattern_size = 0;
- 	pattern_param.dp_panel_mode = dp_get_panel_mode(link);
- 
--	link->ctx->dc->hwss.encoder_set_dp_phy_pattern(encoder, &pattern_param);
-+	encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
- 
- 	return true;
- }
-@@ -131,7 +142,7 @@ void dp_set_hw_lane_settings(
- 	struct link_encoder *encoder = link->link_enc;
- 
- 	/* call Encoder to set lane settings */
--	link->ctx->dc->hwss.encoder_dp_set_lane_settings(encoder, link_settings);
-+	encoder->funcs->dp_set_lane_settings(encoder, link_settings);
- }
- 
- enum dp_panel_mode dp_get_panel_mode(struct core_link *link)
-@@ -186,5 +197,5 @@ void dp_set_hw_test_pattern(
- 	pattern_param.custom_pattern_size = 0;
- 	pattern_param.dp_panel_mode = dp_get_panel_mode(link);
- 
--	link->ctx->dc->hwss.encoder_set_dp_phy_pattern(encoder, &pattern_param);
-+	encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 59a3bce..8afd42e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -46,10 +46,10 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- struct dce110_hw_seq_reg_offsets {
--	uint32_t dcfe_offset;
--	uint32_t blnd_offset;
--	uint32_t crtc_offset;
--	uint32_t dcp_offset;
-+	uint32_t dcfe;
-+	uint32_t blnd;
-+	uint32_t crtc;
-+	uint32_t dcp;
- };
- 
- enum crtc_stereo_mixer_mode {
-@@ -99,36 +99,36 @@ enum {
- 
- static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- {
--	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.blnd_offset = (mmBLND0_BLND_CONTROL - mmBLND0_BLND_CONTROL),
--	.crtc_offset = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
--	.dcp_offset = (mmDCP0_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+	.dcfe = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+	.dcp = (mmDCP0_DVMM_PTE_CONTROL - mmDVMM_PTE_CONTROL),
- },
- {
--	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.blnd_offset = (mmBLND1_BLND_CONTROL - mmBLND0_BLND_CONTROL),
--	.crtc_offset = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
--	.dcp_offset = (mmDCP1_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+	.dcfe = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.blnd = (mmBLND1_BLND_CONTROL - mmBLND0_BLND_CONTROL),
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+	.dcp = (mmDCP1_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
- },
- {
--	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.blnd_offset = (mmBLND2_BLND_CONTROL - mmBLND0_BLND_CONTROL),
--	.crtc_offset = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
--	.dcp_offset = (mmDCP2_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+	.dcfe = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.blnd = (mmBLND2_BLND_CONTROL - mmBLND0_BLND_CONTROL),
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+	.dcp = (mmDCP2_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
- }
- };
- 
- #define HW_REG_DCFE(reg, id)\
--	(reg + reg_offsets[id].dcfe_offset)
-+	(reg + reg_offsets[id].dcfe)
- 
- #define HW_REG_BLND(reg, id)\
--	(reg + reg_offsets[id].blnd_offset)
-+	(reg + reg_offsets[id].blnd)
- 
- #define HW_REG_CRTC(reg, id)\
--	(reg + reg_offsets[id].crtc_offset)
-+	(reg + reg_offsets[id].crtc)
- 
- #define HW_REG_DCP(reg, id)\
--	(reg + reg_offsets[id].dcp_offset)
-+	(reg + reg_offsets[id].dcp)
- 
- 
- static void init_pte(struct dc_context *ctx);
-@@ -689,7 +689,7 @@ static void enable_stream(struct core_stream *stream)
- 	 * connect DIG back_end to front_end while enable_stream and
- 	 * disconnect them during disable_stream
- 	 * BY this, it is logic clean to separate stream and link */
--	dce110_link_encoder_connect_dig_be_to_fe(link->link_enc,
-+	 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
- 			stream->stream_enc->id, true);
- 
- }
-@@ -722,7 +722,7 @@ static void disable_stream(struct core_stream *stream)
- 	if (dc_is_dp_signal(stream->signal))
- 		stream->stream_enc->funcs->dp_blank(stream->stream_enc);
- 
--	dce110_link_encoder_connect_dig_be_to_fe(
-+	link->link_enc->funcs->connect_dig_be_to_fe(
- 			link->link_enc,
- 			stream->stream_enc->id,
- 			false);
-@@ -854,7 +854,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	program_fmt(opp, &stream->fmt_bit_depth, &stream->clamping);
- 
- 	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
--		dce110_link_encoder_setup(
-+		stream->sink->link->link_enc->funcs->setup(
- 			stream->sink->link->link_enc,
- 			stream->signal);
- 
-@@ -921,7 +921,7 @@ static void power_down_encoders(struct dc *dc)
- 
- 	for (i = 0; i < dc->link_count; i++) {
- 		if (dc->links[i]->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
--			dce110_link_encoder_disable_output(
-+			dc->links[i]->link_enc->funcs->disable_output(
- 				dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
- 	}
- }
-@@ -1758,28 +1758,19 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.disable_vga = disable_vga,
- 	.encoder_create = dce110_link_encoder_create,
- 	.encoder_destroy = dce110_link_encoder_destroy,
--	.encoder_hw_init = dce110_link_encoder_hw_init,
--	.encoder_enable_tmds_output = dce110_link_encoder_enable_tmds_output,
--	.encoder_enable_dp_output = dce110_link_encoder_enable_dp_output,
--	.encoder_enable_dp_mst_output =
--			dce110_link_encoder_enable_dp_mst_output,
--	.encoder_disable_output = dce110_link_encoder_disable_output,
--	.encoder_set_dp_phy_pattern = dce110_link_encoder_set_dp_phy_pattern,
--	.encoder_dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
--	.encoder_set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- 	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
- 	.transform_power_up = dce110_transform_power_up,
- 	.construct_resource_pool = dce110_construct_resource_pool,
- 	.destruct_resource_pool = dce110_destruct_resource_pool,
- 	.validate_with_context = dce110_validate_with_context,
- 	.validate_bandwidth = dce110_validate_bandwidth,
--	.enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating,
-+	.enable_display_pipe_clock_gating =
-+		dce110_enable_display_pipe_clock_gating,
- 	.enable_display_power_gating = dce110_enable_display_power_gating,
- 	.program_bw = dce110_program_bw,
- 	.enable_stream = enable_stream,
- 	.disable_stream = disable_stream,
--	.update_mst_stream_allocation_table = dce110_link_encoder_update_mst_stream_allocation_table,
--	.set_mst_bandwidth = set_mst_bandwidth
-+	.set_mst_bandwidth = set_mst_bandwidth,
- };
- 
- bool dce110_hw_sequencer_construct(struct dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 0f0ecfe..3eaced4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -51,6 +51,9 @@
- #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
- #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
- #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
- 
- /* all values are in milliseconds */
- /* For eDP, after power-up/power/down,
-@@ -85,91 +88,30 @@ enum {
- 
- 
- #define DIG_REG(reg)\
--	(reg + enc110->offsets.dig_offset)
-+	(reg + enc110->offsets.dig)
- 
- #define DP_REG(reg)\
--	(reg + enc110->offsets.dp_offset)
--
--static const struct dce110_link_enc_offsets reg_offsets[] = {
--{
--	.dig_offset = (mmDIG0_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP0_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
--},
--{
--	.dig_offset = (mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP1_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
--},
--{
--	.dig_offset = (mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL),
--	.dp_offset = (mmDP2_DP_SEC_CNTL - mmDP0_DP_SEC_CNTL)
--}
-+	(reg + enc110->offsets.dp)
-+
-+static struct link_encoder_funcs dce110_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		dce110_link_encoder_validate_output_with_stream,
-+	.hw_init = dce110_link_encoder_hw_init,
-+	.setup = dce110_link_encoder_setup,
-+	.enable_tmds_output = dce110_link_encoder_enable_tmds_output,
-+	.enable_dp_output = dce110_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
-+	.disable_output = dce110_link_encoder_disable_output,
-+	.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		dce110_link_encoder_update_mst_stream_allocation_table,
-+	.set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
-+	.backlight_control = dce110_link_encoder_edp_backlight_control,
-+	.power_control = dce110_link_encoder_edp_power_control,
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe
- };
- 
--static enum transmitter translate_encoder_to_transmitter(
--	struct graphics_object_id encoder)
--{
--	switch (encoder.id) {
--	case ENCODER_ID_INTERNAL_UNIPHY:
--		switch (encoder.enum_id) {
--		case ENUM_ID_1:
--			return TRANSMITTER_UNIPHY_A;
--		case ENUM_ID_2:
--			return TRANSMITTER_UNIPHY_B;
--		default:
--			return TRANSMITTER_UNKNOWN;
--		}
--	break;
--	case ENCODER_ID_INTERNAL_UNIPHY1:
--		switch (encoder.enum_id) {
--		case ENUM_ID_1:
--			return TRANSMITTER_UNIPHY_C;
--		case ENUM_ID_2:
--			return TRANSMITTER_UNIPHY_D;
--		default:
--			return TRANSMITTER_UNKNOWN;
--		}
--	break;
--	case ENCODER_ID_INTERNAL_UNIPHY2:
--		switch (encoder.enum_id) {
--		case ENUM_ID_1:
--			return TRANSMITTER_UNIPHY_E;
--		case ENUM_ID_2:
--			return TRANSMITTER_UNIPHY_F;
--		default:
--			return TRANSMITTER_UNKNOWN;
--		}
--	break;
--	case ENCODER_ID_INTERNAL_UNIPHY3:
--		switch (encoder.enum_id) {
--		case ENUM_ID_1:
--			return TRANSMITTER_UNIPHY_G;
--		default:
--			return TRANSMITTER_UNKNOWN;
--		}
--	break;
--	case ENCODER_ID_EXTERNAL_NUTMEG:
--		switch (encoder.enum_id) {
--		case ENUM_ID_1:
--			return TRANSMITTER_NUTMEG_CRT;
--		default:
--			return TRANSMITTER_UNKNOWN;
--		}
--	break;
--	case ENCODER_ID_EXTERNAL_TRAVIS:
--		switch (encoder.enum_id) {
--		case ENUM_ID_1:
--			return TRANSMITTER_TRAVIS_CRT;
--		case ENUM_ID_2:
--			return TRANSMITTER_TRAVIS_LCD;
--		default:
--			return TRANSMITTER_UNKNOWN;
--		}
--	break;
--	default:
--		return TRANSMITTER_UNKNOWN;
--	}
--}
--
- static enum bp_result link_transmitter_control(
- 	struct dce110_link_encoder *enc110,
- 	struct bp_transmitter_control *cntl)
-@@ -503,7 +445,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 
- 	/* Setup DIG encoder in DP SST mode */
- 
--	dce110_link_encoder_setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
-+	enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
- 
- 	/* program correct panel mode*/
- 	{
-@@ -611,6 +553,12 @@ static uint8_t get_frontend_source(
- 		return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
- 	case ENGINE_ID_DIGC:
- 		return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
-+	case ENGINE_ID_DIGD:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
-+	case ENGINE_ID_DIGE:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
-+	case ENGINE_ID_DIGF:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
- 	default:
- 		ASSERT_CRITICAL(false);
- 		return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
-@@ -651,63 +599,6 @@ static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
- 
- /*
-  * @brief
-- * eDP only. Control the power of the eDP panel.
-- */
--static void link_encoder_edp_power_control(
--	struct dce110_link_encoder *enc110,
--	bool power_up)
--{
--	struct dc_context *ctx = enc110->base.ctx;
--	struct bp_transmitter_control cntl = { 0 };
--	enum bp_result bp_result;
--
--	if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
--		CONNECTOR_ID_EDP) {
--		BREAK_TO_DEBUGGER();
--		return;
--	}
--
--	if ((power_up && !is_panel_powered_on(enc110)) ||
--		(!power_up && is_panel_powered_on(enc110))) {
--
--		/* Send VBIOS command to prompt eDP panel power */
--
--		dal_logger_write(ctx->logger,
--				LOG_MAJOR_HW_TRACE,
--				LOG_MINOR_HW_TRACE_RESUME_S3,
--				"%s: Panel Power action: %s\n",
--				__func__, (power_up ? "On":"Off"));
--
--		cntl.action = power_up ?
--			TRANSMITTER_CONTROL_POWER_ON :
--			TRANSMITTER_CONTROL_POWER_OFF;
--		cntl.transmitter = enc110->base.transmitter;
--		cntl.connector_obj_id = enc110->base.connector;
--		cntl.coherent = false;
--		cntl.lanes_number = LANE_COUNT_FOUR;
--		cntl.hpd_sel = enc110->base.hpd_source;
--
--		bp_result = link_transmitter_control(enc110, &cntl);
--
--		if (BP_RESULT_OK != bp_result) {
--
--			dal_logger_write(ctx->logger,
--					LOG_MAJOR_ERROR,
--					LOG_MINOR_HW_TRACE_RESUME_S3,
--					"%s: Panel Power bp_result: %d\n",
--					__func__, bp_result);
--		}
--	} else {
--		dal_logger_write(ctx->logger,
--				LOG_MAJOR_HW_TRACE,
--				LOG_MINOR_HW_TRACE_RESUME_S3,
--				"%s: Skipping Panel Power action: %s\n",
--				__func__, (power_up ? "On":"Off"));
--	}
--}
--
--/*
-- * @brief
-  * eDP only.
-  */
- static void link_encoder_edp_wait_for_hpd_ready(
-@@ -778,6 +669,66 @@ static void link_encoder_edp_wait_for_hpd_ready(
- 	}
- }
- 
-+/*
-+ * @brief
-+ * eDP only. Control the power of the eDP panel.
-+ */
-+void dce110_link_encoder_edp_power_control(
-+	struct link_encoder *enc,
-+	bool power_up)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result bp_result;
-+
-+	if (dal_graphics_object_id_get_connector_id(enc110->base.connector) !=
-+		CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if ((power_up && !is_panel_powered_on(enc110)) ||
-+		(!power_up && is_panel_powered_on(enc110))) {
-+
-+		/* Send VBIOS command to prompt eDP panel power */
-+
-+		dal_logger_write(ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: Panel Power action: %s\n",
-+				__func__, (power_up ? "On":"Off"));
-+
-+		cntl.action = power_up ?
-+			TRANSMITTER_CONTROL_POWER_ON :
-+			TRANSMITTER_CONTROL_POWER_OFF;
-+		cntl.transmitter = enc110->base.transmitter;
-+		cntl.connector_obj_id = enc110->base.connector;
-+		cntl.coherent = false;
-+		cntl.lanes_number = LANE_COUNT_FOUR;
-+		cntl.hpd_sel = enc110->base.hpd_source;
-+
-+		bp_result = link_transmitter_control(enc110, &cntl);
-+
-+		if (BP_RESULT_OK != bp_result) {
-+
-+			dal_logger_write(ctx->logger,
-+					LOG_MAJOR_ERROR,
-+					LOG_MINOR_HW_TRACE_RESUME_S3,
-+					"%s: Panel Power bp_result: %d\n",
-+					__func__, bp_result);
-+		}
-+	} else {
-+		dal_logger_write(ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_HW_TRACE_RESUME_S3,
-+				"%s: Skipping Panel Power action: %s\n",
-+				__func__, (power_up ? "On":"Off"));
-+	}
-+
-+	link_encoder_edp_wait_for_hpd_ready(enc110, true);
-+}
-+
- static void aux_initialize(
- 	struct dce110_link_encoder *enc110)
- {
-@@ -819,10 +770,11 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
-  * @brief
-  * eDP only. Control the backlight of the eDP panel
-  */
--static void link_encoder_edp_backlight_control(
--	struct dce110_link_encoder *enc110,
-+void dce110_link_encoder_edp_backlight_control(
-+	struct link_encoder *enc,
- 	bool enable)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	struct bp_transmitter_control cntl = { 0 };
- 
-@@ -987,10 +939,14 @@ static bool validate_hdmi_output(
- 	uint32_t max_hdmi_pixel_clock)
- {
- 	enum dc_color_depth max_deep_color = max_hdmi_deep_color;
--
- 	/* expressed in KHz */
- 	uint32_t pixel_clock = 0;
- 
-+	/*TODO: unhardcode*/
-+	max_tmds_clk_from_edid_in_mhz = 0;
-+	max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	max_hdmi_pixel_clock = 600000;
-+
- 	if (max_deep_color > enc110->base.features.max_deep_color)
- 		max_deep_color = enc110->base.features.max_deep_color;
- 
-@@ -1101,12 +1057,14 @@ static bool validate_wireless_output(
- 	return false;
- }
- 
--static bool construct(
-+bool dce110_link_encoder_construct(
- 	struct dce110_link_encoder *enc110,
--	const struct encoder_init_data *init_data)
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_offsets *offsets)
- {
- 	struct graphics_object_encoder_cap_info enc_cap_info = {0};
- 
-+	enc110->base.funcs = &dce110_lnk_enc_funcs;
- 	enc110->base.ctx = init_data->ctx;
- 	enc110->base.id = init_data->encoder;
- 
-@@ -1120,8 +1078,7 @@ static bool construct(
- 
- 	enc110->base.features.flags.raw = 0;
- 
--	enc110->base.transmitter = translate_encoder_to_transmitter(
--		init_data->encoder);
-+	enc110->base.transmitter = init_data->transmitter;
- 
- 	enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
- 
-@@ -1157,6 +1114,8 @@ static bool construct(
- 	 * This will let DCE 8.1 share DCE 8.0 as much as possible
- 	 */
- 
-+	enc110->offsets = *offsets;
-+
- 	switch (enc110->base.transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
- 		enc110->base.preferred_engine = ENGINE_ID_DIGA;
-@@ -1172,8 +1131,6 @@ static bool construct(
- 		enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
- 	}
- 
--	enc110->offsets = reg_offsets[enc110->base.transmitter];
--
- 	dal_logger_write(init_data->ctx->logger,
- 			LOG_MAJOR_I2C_AUX,
- 			LOG_MINOR_I2C_AUX_CFG,
-@@ -1224,32 +1181,9 @@ static bool construct(
- 	return true;
- }
- 
--struct link_encoder *dce110_link_encoder_create(
--	const struct encoder_init_data *init)
--{
--	struct dce110_link_encoder *enc110 =
--		dc_service_alloc(init->ctx, sizeof(struct dce110_link_encoder));
--
--	if (!enc110)
--		return NULL;
--
--	if (construct(enc110, init))
--		return &enc110->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(init->ctx, enc110);
--	return NULL;
--}
--
--void dce110_link_encoder_destroy(struct link_encoder **enc)
--{
--	dc_service_free((*enc)->ctx, TO_DCE110_LINK_ENC(*enc));
--	*enc = NULL;
--}
--
- bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
--	const struct core_stream *stream)
-+	struct core_stream *stream)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	bool is_valid;
-@@ -1329,11 +1263,7 @@ void dce110_link_encoder_hw_init(
- 		ASSERT(result == BP_RESULT_OK);
- 
- 	} else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
--		link_encoder_edp_power_control(enc110, true);
--
--		link_encoder_edp_wait_for_hpd_ready(
--			enc110, true);
--
-+		enc->funcs->power_control(&enc110->base, true);
- 	}
- 	aux_initialize(enc110);
- 
-@@ -1444,19 +1374,6 @@ void dce110_link_encoder_enable_dp_output(
- 	struct bp_transmitter_control cntl = { 0 };
- 	enum bp_result result;
- 
--	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
--		/* power up eDP panel */
--
--		link_encoder_edp_power_control(enc110, true);
--
--		link_encoder_edp_wait_for_hpd_ready(enc110, true);
--
--		/* have to turn off the backlight
--		 * before power down eDP panel
--		 */
--		link_encoder_edp_backlight_control(enc110, true);
--	}
--
- 	/* Enable the PHY */
- 
- 	/* number_of_lanes is used for pixel clock adjust,
-@@ -1544,13 +1461,6 @@ void dce110_link_encoder_disable_output(
- 	struct bp_transmitter_control cntl = { 0 };
- 	enum bp_result result;
- 
--	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
--		/* have to turn off the backlight
--		 * before power down eDP panel */
--		link_encoder_edp_backlight_control(
--				enc110, false);
--	}
--
- 	if (!is_dig_enabled(enc110) &&
- 		dal_adapter_service_should_optimize(
- 			enc110->base.adapter_service,
-@@ -1653,7 +1563,7 @@ void dce110_link_encoder_dp_set_lane_settings(
- }
- 
- /* set DP PHY test and training patterns */
--void dce110_link_encoder_set_dp_phy_pattern(
-+void dce110_link_encoder_dp_set_phy_pattern(
- 	struct link_encoder *enc,
- 	const struct encoder_set_dp_phy_pattern_param *param)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 156cdc8..df6e265 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -32,8 +32,8 @@
- 	container_of(link_encoder, struct dce110_link_encoder, base)
- 
- struct dce110_link_enc_offsets {
--	uint32_t dig_offset;
--	uint32_t dp_offset;
-+	int32_t dig;
-+	int32_t dp;
- };
- 
- struct dce110_link_encoder {
-@@ -41,14 +41,14 @@ struct dce110_link_encoder {
- 	struct dce110_link_enc_offsets offsets;
- };
- 
--struct link_encoder *dce110_link_encoder_create(
--	const struct encoder_init_data *init);
--
--void dce110_link_encoder_destroy(struct link_encoder **enc);
-+bool dce110_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_offsets *offsets);
- 
- bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
--	const struct core_stream *stream);
-+	struct core_stream *stream);
- 
- /****************** HW programming ************************/
- 
-@@ -93,7 +93,7 @@ void dce110_link_encoder_dp_set_lane_settings(
- 	struct link_encoder *enc,
- 	const struct link_training_settings *link_settings);
- 
--void dce110_link_encoder_set_dp_phy_pattern(
-+void dce110_link_encoder_dp_set_phy_pattern(
- 	struct link_encoder *enc,
- 	const struct encoder_set_dp_phy_pattern_param *param);
- 
-@@ -106,6 +106,14 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
- 	uint32_t level);
- 
-+void dce110_link_encoder_edp_backlight_control(
-+	struct link_encoder *enc,
-+	bool enable);
-+
-+void dce110_link_encoder_edp_power_control(
-+	struct link_encoder *enc,
-+	bool power_up);
-+
- void dce110_link_encoder_connect_dig_be_to_fe(
- 	struct link_encoder *enc,
- 	enum engine_id engine,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 8f04707..c43dd07 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -79,6 +79,21 @@ static const struct dce110_stream_enc_offsets dce110_str_enc_offsets[] = {
- 	}
- };
- 
-+static const struct dce110_link_enc_offsets dce110_lnk_enc_reg_offsets[] = {
-+	{
-+		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	}
-+};
-+
- static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
- 	{
- 		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-@@ -239,6 +254,34 @@ static struct input_pixel_processor *dce110_ipp_create(
- 	return NULL;
- }
- 
-+struct link_encoder *dce110_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		dc_service_alloc(
-+			enc_init_data->ctx,
-+			sizeof(struct dce110_link_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce110_link_encoder_construct(
-+			enc110,
-+			enc_init_data,
-+			&dce110_lnk_enc_reg_offsets[enc_init_data->transmitter]))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(enc_init_data->ctx, enc110);
-+	return NULL;
-+}
-+
-+void dce110_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	dc_service_free((*enc)->ctx, TO_DCE110_LINK_ENC(*enc));
-+	*enc = NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	struct dc *dc,
-@@ -667,7 +710,7 @@ static enum dc_status validate_mapped_resource(
- 			if (status != DC_OK)
- 				return status;
- 
--			if (!dce110_link_encoder_validate_output_with_stream(
-+			if (!link->link_enc->funcs->validate_output_with_stream(
- 					link->link_enc,
- 					stream))
- 				return DC_FAIL_ENC_VALIDATE;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-index e113d11..e47b19d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-@@ -51,5 +51,10 @@ enum dc_status dce110_validate_bandwidth(
- 		const struct dc *dc,
- 		struct validate_context *context);
- 
-+struct link_encoder *dce110_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data);
-+
-+void dce110_link_encoder_destroy(struct link_encoder **enc);
-+
- #endif /* __DC_RESOURCE_DCE110_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index ddc16cd..7e110b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -32,13 +32,14 @@
- 	container_of(stream_encoder, struct dce110_stream_encoder, base)
- 
- struct dce110_stream_enc_offsets {
--	uint32_t dig;
--	uint32_t dp;
-+	int32_t dig;
-+	int32_t dp;
- };
- 
- struct dce110_stream_encoder {
- 	struct stream_encoder base;
- 	struct dce110_stream_enc_offsets offsets;
-+	struct dce110_stream_enc_offsets derived_offsets;
- };
- 
- bool dce110_stream_encoder_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index a84ab8b..e6aaacc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -51,16 +51,17 @@
- #define CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_RGB_LIMITED_RANGE 0X40
- 
- struct dce110_timing_generator_offsets {
--	uint32_t crtc;
--	uint32_t dcp;
-+	int32_t crtc;
-+	int32_t dcp;
- 
- 	/* DCE80 use only */
--	uint32_t dmif;
-+	int32_t dmif;
- };
- 
- struct dce110_timing_generator {
- 	struct timing_generator base;
- 	struct dce110_timing_generator_offsets offsets;
-+	struct dce110_timing_generator_offsets derived_offsets;
- 
- 	enum controller_id controller_id;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 59ed137..46721cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -83,39 +83,6 @@ struct hw_sequencer_funcs {
- 
- 	void (*encoder_destroy)(struct link_encoder **enc);
- 
--	void (*encoder_hw_init)(
--					struct link_encoder *enc);
--
--	void (*encoder_enable_tmds_output)(
--					struct link_encoder *enc,
--					enum clock_source_id clock_source,
--					enum dc_color_depth color_depth,
--					bool hdmi,
--					bool dual_link,
--					uint32_t pixel_clock);
--
--	void (*encoder_enable_dp_output)(
--				struct link_encoder *enc,
--				const struct link_settings *link_settings,
--				enum clock_source_id clock_source);
--
--	void (*encoder_enable_dp_mst_output)(
--				struct link_encoder *enc,
--				const struct link_settings *link_settings,
--				enum clock_source_id clock_source);
--
--	void (*encoder_disable_output)(
--					struct link_encoder *enc,
--					enum signal_type signal);
--
--	void (*encoder_set_dp_phy_pattern)(
--			struct link_encoder *enc,
--			const struct encoder_set_dp_phy_pattern_param *param);
--
--	void (*encoder_dp_set_lane_settings)(
--			struct link_encoder *enc,
--			const struct link_training_settings *link_settings);
--
- 	/* backlight control */
- 	void (*encoder_set_lcd_backlight_level)(struct link_encoder *enc,
- 					uint32_t level);
-@@ -162,10 +129,6 @@ struct hw_sequencer_funcs {
- 	void (*disable_stream)(
- 					struct core_stream *stream);
- 
--	void (*update_mst_stream_allocation_table)(
--					struct link_encoder *enc,
--					const struct dp_mst_stream_allocation_table *table);
--
- 	void (*set_mst_bandwidth)(
- 					struct stream_encoder *enc,
- 					struct fixed31_32 avg_time_slots_per_mtp);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index d4a0d24..f63c479 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -9,11 +9,13 @@
- #define LINK_ENCODER_H_
- 
- #include "include/encoder_types.h"
-+#include "core_types.h"
- 
- struct link_enc_status {
- 	int dummy; /*TODO*/
- };
- struct link_encoder {
-+	struct link_encoder_funcs *funcs;
- 	struct adapter_service *adapter_service;
- 	int32_t aux_channel_offset;
- 	struct dc_context *ctx;
-@@ -27,4 +29,42 @@ struct link_encoder {
- 	enum hpd_source_id hpd_source;
- };
- 
-+struct link_encoder_funcs {
-+	bool (*validate_output_with_stream)(struct link_encoder *enc,
-+		struct core_stream *stream);
-+	void (*hw_init)(struct link_encoder *enc);
-+	void (*setup)(struct link_encoder *enc,
-+		enum signal_type signal);
-+	void (*enable_tmds_output)(struct link_encoder *enc,
-+		enum clock_source_id clock_source,
-+		enum dc_color_depth color_depth,
-+		bool hdmi,
-+		bool dual_link,
-+		uint32_t pixel_clock);
-+	void (*enable_dp_output)(struct link_encoder *enc,
-+		const struct link_settings *link_settings,
-+		enum clock_source_id clock_source);
-+	void (*enable_dp_mst_output)(struct link_encoder *enc,
-+		const struct link_settings *link_settings,
-+		enum clock_source_id clock_source);
-+	void (*disable_output)(struct link_encoder *link_enc,
-+		enum signal_type signal);
-+	void (*dp_set_lane_settings)(struct link_encoder *enc,
-+		const struct link_training_settings *link_settings);
-+	void (*dp_set_phy_pattern)(struct link_encoder *enc,
-+		const struct encoder_set_dp_phy_pattern_param *para);
-+	void (*update_mst_stream_allocation_table)(
-+		struct link_encoder *enc,
-+		const struct dp_mst_stream_allocation_table *table);
-+	void (*set_lcd_backlight_level) (struct link_encoder *enc,
-+		uint32_t level);
-+	void (*backlight_control) (struct link_encoder *enc,
-+		bool enable);
-+	void (*power_control) (struct link_encoder *enc,
-+		bool power_up);
-+	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
-+		enum engine_id engine,
-+		bool connect);
-+};
-+
- #endif /* LINK_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_types.h b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-index c267d30..6a7b317 100644
---- a/drivers/gpu/drm/amd/dal/include/encoder_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-@@ -39,6 +39,7 @@ struct encoder_init_data {
- 	/* TODO: in DAL2, here was pointer to EventManagerInterface */
- 	struct graphics_object_id encoder;
- 	struct dc_context *ctx;
-+	enum transmitter transmitter;
- };
- 
- struct encoder_context {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch b/common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch
deleted file mode 100644
index 8cbf3b98..00000000
--- a/common/recipes-kernel/linux/files/0709-drm-amd-dal-Add-PreModeChange-event-to-PPLIB.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From c3eeb9ac6864b945dcb60a84847d1afe9ef59776 Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Thu, 14 Jan 2016 14:49:08 -0500
-Subject: [PATCH 0709/1110] drm/amd/dal: Add PreModeChange event to PPLIB
-
-[Description]
-Before this change, we only send PostModeChange event.
-What happens is that PPLIB does not know we are changing
-display configuration beforehand. By the time we send Post
-event, it is already too late, and this may cause soft hang
-waiting on SMU to transition power states.
-
-This issues was found specifically during S3 resume tests,
-when we commit 0 targets while entering S3 state. On
-resume, we re-enable the display without first telling PPLIB.
-
-This change adds a PreModeChange notification at the start
-of dc_commit_targets.
-
-Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c | 16 ++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/core/dc.c                    |  2 ++
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c           |  6 ++++++
- drivers/gpu/drm/amd/dal/dc/dc_services.h                |  3 +++
- drivers/gpu/drm/amd/dal/dc/inc/resource.h               |  2 ++
- 5 files changed, 29 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index 12b9475..b67599d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -157,6 +157,22 @@ bool dc_service_pp_pre_dce_clock_change(
- 	return false;
- }
- 
-+bool dc_service_pp_apply_safe_state(
-+		const struct dc_context *ctx)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (adev->pm.dpm_enabled) {
-+		/* TODO: Does this require PreModeChange event to PPLIB? */
-+	}
-+
-+	return true;
-+#else
-+	return false;
-+#endif
-+}
-+
- bool dc_service_pp_apply_display_requirements(
- 		const struct dc_context *ctx,
- 		const struct dc_pp_display_configuration *pp_display_cfg)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e49ec86..b68ecb7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -549,6 +549,8 @@ bool dc_commit_targets(
- 		goto fail;
- 	}
- 
-+	pplib_apply_safe_state(dc);
-+
- 	if (!dal_adapter_service_is_in_accelerated_mode(
- 						dc->res_pool.adapter_srv)) {
- 		dc->hwss.enable_accelerated_mode(dc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 52fcdc1..7cc4ed2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -485,6 +485,12 @@ static void fill_display_configs(
- 	pp_display_cfg->display_count = num_cfgs;
- }
- 
-+void pplib_apply_safe_state(
-+	const struct dc *dc)
-+{
-+	dc_service_pp_apply_safe_state(dc->ctx);
-+}
-+
- void pplib_apply_display_requirements(
- 	const struct dc *dc,
- 	const struct validate_context *context)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index 907b415..b8b8b20 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -201,6 +201,9 @@ bool dc_service_pp_get_clock_levels_by_type(
- 	struct dc_pp_clock_levels *clk_level_info);
- 
- 
-+bool dc_service_pp_apply_safe_state(
-+		const struct dc_context *ctx);
-+
- /* DAL calls this function to notify PP about completion of Mode Set.
-  * For PP it means that current DCE clocks are those which were returned
-  * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index fac4c8b..ea6be75 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -61,6 +61,8 @@ bool logical_attach_surfaces_to_target(
- 		uint8_t surface_count,
- 		struct dc_target *dc_target);
- 
-+void pplib_apply_safe_state(const struct dc *dc);
-+
- void pplib_apply_display_requirements(
- 	const struct dc *dc,
- 	const struct validate_context *context);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0710-drm-amd-dal-tonga-initial-light-up.patch b/common/recipes-kernel/linux/files/0710-drm-amd-dal-tonga-initial-light-up.patch
deleted file mode 100644
index 54121450..00000000
--- a/common/recipes-kernel/linux/files/0710-drm-amd-dal-tonga-initial-light-up.patch
+++ /dev/null
@@ -1,664 +0,0 @@
-From 03e60574d37c6d9ab73d4aee14c0327224c0c3be Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 19 Jan 2016 17:24:37 -0500
-Subject: [PATCH 0710/1110] drm/amd/dal: tonga initial light up
-
-Add Tonga support by reusing dce110, has corresponding
-kernel change
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   8 ++
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   4 +
- .../gpu/drm/amd/dal/dc/asic_capability/Makefile    |  12 ++
- .../amd/dal/dc/asic_capability/asic_capability.c   |  14 +-
- .../dc/asic_capability/carrizo_asic_capability.c   |   1 +
- .../dal/dc/asic_capability/tonga_asic_capability.c | 147 +++++++++++++++++++++
- .../dal/dc/asic_capability/tonga_asic_capability.h |  18 +++
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |   4 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |   6 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |   2 +-
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |   6 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |   4 +
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   9 ++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  13 ++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  28 +++-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |   5 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |   3 +
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c      |   5 +-
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |   5 +-
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |   4 +
- drivers/gpu/drm/amd/dal/include/dal_asic_id.h      |  11 ++
- drivers/gpu/drm/amd/dal/include/dal_types.h        |   3 +
- 24 files changed, 308 insertions(+), 8 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 7614ac8..2cece0f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1216,6 +1216,8 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 	/* Software is initialized. Now we can register interrupt handlers. */
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
-+	case CHIP_TONGA:
-+	case CHIP_FIJI:
- 	case CHIP_CARRIZO:
- 		if (dce110_register_irq_handlers(dm->adev)) {
- 			DRM_ERROR("DM: Failed to initialize IRQ\n");
-@@ -1435,6 +1437,12 @@ static int dm_early_init(void *handle)
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 6;
- 		break;
-+	case CHIP_FIJI:
-+	case CHIP_TONGA:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 7;
-+		break;
- 	case CHIP_CARRIZO:
- 		adev->mode_info.num_crtc = 3;
- 		adev->mode_info.num_hpd = 6;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index b8d6033..17a9d2c 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -677,6 +677,10 @@ static struct hw_ctx_adapter_service *create_hw_ctx(
- 	}
- 
- 	switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		return dal_adapter_service_create_hw_ctx_dce110(ctx);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		return dal_adapter_service_create_hw_ctx_dce110(ctx);
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-index 5e01a86..8491b38 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-@@ -9,6 +9,18 @@ AMD_DAL_ASIC_CAPABILITY = \
- 
- AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
- 
-+###############################################################################
-+# DCE 10x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE10_0
-+ASIC_CAPABILITY_DCE10 = tonga_asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY_DCE10 = \
-+	$(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE10))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE10)
-+endif
-+
- 
- ###############################################################################
- # DCE 11x
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index a532e2f..b3eb665 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -32,6 +32,9 @@
- #include "include/dal_types.h"
- #include "include/dal_asic_id.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+#include "tonga_asic_capability.h"
-+#endif
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "carrizo_asic_capability.h"
-@@ -97,7 +100,16 @@ static bool construct(
- 		asic_supported = true;
- #endif
- 		break;
--
-+ 	case FAMILY_VI:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+		if (ASIC_REV_IS_TONGA_P(init->hw_internal_rev) ||
-+				ASIC_REV_IS_FIJI_P(init->hw_internal_rev)) {
-+			tonga_asic_capability_create(cap, init);
-+			asic_supported = true;
-+			break;
-+		}
-+#endif
-+		break;
- 	default:
- 		/* unsupported "chip_family" */
- 		break;
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-index f57d3f7..b106ccc 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-@@ -49,6 +49,7 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
- 	uint32_t e_fuse_setting;
- 	/* ASIC data */
- 	cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
-+	cap->data[ASIC_DATA_DIGFE_NUM] = 3;
- 	cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
- 	cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
- 	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-new file mode 100644
-index 0000000..599c47d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-@@ -0,0 +1,147 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dal_services.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+
-+#include "tonga_asic_capability.h"
-+
-+#include "atom.h"
-+#include "dce/dce_10_0_d.h"
-+#include "smu/smu_8_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+#include "dal_asic_id.h"
-+
-+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS     0xC0014074
-+
-+/*
-+ * carrizo_asic_capability_create
-+ *
-+ * Create and initiate Carrizo capability.
-+ */
-+void tonga_asic_capability_create(struct asic_capability *cap,
-+	struct hw_asic_id *init)
-+{
-+	uint32_t e_fuse_setting;
-+	/* ASIC data */
-+	cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
-+	cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
-+	cap->data[ASIC_DATA_DIGFE_NUM] = 6;
-+	cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
-+
-+	cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
-+	cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
-+	cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
-+	cap->data[ASIC_DATA_MC_LATENCY] = 5000;
-+	cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
-+	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
-+	cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-+	cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
-+	cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
-+
-+	cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
-+
-+	cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
-+	cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
-+	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
-+	cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
-+
-+
-+	/* ASIC basic capability */
-+	cap->caps.IS_FUSION = true;
-+	cap->caps.DP_MST_SUPPORTED = true;
-+	cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
-+	cap->caps.MIRABILIS_SUPPORTED = true;
-+	cap->caps.NO_VCC_OFF_HPD_POLLING = true;
-+	cap->caps.VCE_SUPPORTED = true;
-+	cap->caps.HPD_CHECK_FOR_EDID = true;
-+	cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
-+	cap->caps.SUPPORT_8BPP = false;
-+
-+	/* ASIC stereo 3d capability */
-+	cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
-+	cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
-+	cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
-+	cap->stereo_3d_caps.INTERLEAVE = true;
-+
-+	e_fuse_setting = dal_read_index_reg(cap->ctx, CGS_IND_REG__SMC,
-+			ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-+
-+	/* Bits [28:27]*/
-+	switch ((e_fuse_setting >> 27) & 0x3) {
-+	case 0:
-+		/* both VCE engine are working*/
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
-+		/*
-+		 * TODO:
-+		 * cap->caps.wirelessLowVCEPerformance = false;
-+		 * m_AsicCaps.vceInstance0Enabled = true;
-+		 * m_AsicCaps.vceInstance1Enabled = true;
-+		 */
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 1:
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+		/*
-+		 * TODO:
-+		 * m_AsicCaps.wirelessLowVCEPerformance = false;
-+		 * m_AsicCaps.vceInstance1Enabled = true;
-+		 */
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 2:
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+		/*
-+		 * TODO:
-+		 * m_AsicCaps.wirelessLowVCEPerformance = false;
-+		 * m_AsicCaps.vceInstance0Enabled = true;
-+		 */
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 3:
-+		/*
-+		 * VCE_DISABLE = 0x3  - both VCE
-+		 * instances are in harvesting,
-+		 * no VCE supported any more.
-+		 */
-+		cap->caps.VCE_SUPPORTED = false;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
-new file mode 100644
-index 0000000..ca6d683
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
-@@ -0,0 +1,18 @@
-+/*
-+ * tonga_asic_capability.h
-+ *
-+ *  Created on: 2016-01-18
-+ *      Author: qyang
-+ */
-+
-+#ifndef TONGA_ASIC_CAPABILITY_H_
-+#define TONGA_ASIC_CAPABILITY_H_
-+
-+/* Forward declaration */
-+struct asic_capability;
-+
-+/* Create and initialize Carrizo data */
-+void tonga_asic_capability_create(struct asic_capability *cap,
-+	struct hw_asic_id *init);
-+
-+#endif /* TONGA_ASIC_CAPABILITY_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index f553b7a..2737851 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -264,6 +264,10 @@ struct audio *dal_audio_create(
- 
- 	as = init_data->as;
- 	switch (dal_adapter_service_get_dce_version(as)) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		return dal_audio_create_dce110(init_data);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		return dal_audio_create_dce110(init_data);
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index a0927cf..da559b0 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -39,6 +39,12 @@ bool dal_bios_parser_init_bios_helper(
- {
- 	switch (version) {
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
-+		return true;
-+
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index d0e9de9..1ad7455 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -26,7 +26,7 @@
- #ifndef __DAL_BIOS_PARSER_HELPER_H__
- #define __DAL_BIOS_PARSER_HELPER_H__
- 
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/bios_parser_helper_dce110.h"
- #endif
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index 51027c5..e0407f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -38,6 +38,12 @@ bool dal_bios_parser_init_cmd_tbl_helper(
- {
- 	switch (dce) {
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		*h = dal_cmd_tbl_helper_dce110_get_table();
-+		return true;
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		*h = dal_cmd_tbl_helper_dce110_get_table();
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-index cf563ce..4646cab 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-@@ -26,7 +26,7 @@
- #ifndef __DAL_COMMAND_TABLE_HELPER_H__
- #define __DAL_COMMAND_TABLE_HELPER_H__
- 
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/command_table_helper_dce110.h"
- #endif
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-index b9e6ffd..2cac267 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -37,6 +37,10 @@ bool dc_construct_hw_sequencer(
- 
- 	switch (dce_ver)
- 	{
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		return dce110_hw_sequencer_construct(dc);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		return dce110_hw_sequencer_construct(dc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 3eaced4..b4e8467 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1126,6 +1126,15 @@ bool dce110_link_encoder_construct(
- 	case TRANSMITTER_UNIPHY_C:
- 		enc110->base.preferred_engine = ENGINE_ID_DIGC;
- 	break;
-+	case TRANSMITTER_UNIPHY_D:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGD;
-+	break;
-+	case TRANSMITTER_UNIPHY_E:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGE;
-+	break;
-+	case TRANSMITTER_UNIPHY_F:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGF;
-+	break;
- 	default:
- 		ASSERT_CRITICAL(false);
- 		enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 410b52f..3fd12eb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -52,6 +52,19 @@ static const struct dce110_opp_reg_offsets reg_offsets[] = {
- {	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
- 	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
- 	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
- }
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index c43dd07..96f4423 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -61,6 +61,18 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
- 	{
- 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
- 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
- 	}
- };
- 
-@@ -146,10 +158,18 @@ static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
- },
- {
- 	.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
- }
- };
- 
--
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -296,6 +316,9 @@ bool dce110_construct_resource_pool(
- 	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
- 
- 	clk_src_init_data.as = adapter_serv;
- 	clk_src_init_data.ctx = ctx;
-@@ -342,7 +365,8 @@ bool dce110_construct_resource_pool(
- 
- 	pool->controller_count =
- 		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count = 3;
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
-+			adapter_serv);
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index a01024e..7e93014 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -66,6 +66,11 @@ bool dal_hw_factory_init(
- 
- 	switch (dce_version) {
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		dal_hw_factory_dce110_init(factory);
-+		return true;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		dal_hw_factory_dce110_init(factory);
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index d49e952..0e768df 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -67,6 +67,9 @@ bool dal_hw_translate_init(
- 	switch (dce_version) {
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+#endif
- 	case DCE_VERSION_11_0:
- 		dal_hw_translate_dce110_init(translate);
- 		return true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-index cd4a91e..a2e618e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-@@ -34,7 +34,7 @@
- #include "clock_source.h"
- #include "pll_clock_source.h"
- 
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/ext_clock_source_dce110.h"
- #include "dce110/pll_clock_source_dce110.h"
- #include "dce110/vce_clock_source_dce110.h"
-@@ -53,6 +53,9 @@ struct clock_source *dal_clock_source_create(
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	break;
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+#endif
- 	case DCE_VERSION_11_0:
- 	{
- 		switch (clk_src_id) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-index 80f7da7..ae70e41 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-@@ -314,7 +314,7 @@ static bool construct(
- 	controllers_num = dal_adapter_service_get_controllers_num(
- 			base->adapter_service);
- 
--	if (controllers_num <= 0 || controllers_num > 3) {
-+	if (controllers_num <= 0 || controllers_num > 6) {
- 		ECS_ERROR("ECS110:Invalid number of controllers = %d!\n",
- 				controllers_num);
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 6de108c..941213d 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -49,7 +49,7 @@
-  * This unit
-  */
- 
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/i2caux_dce110.h"
- #endif
- 
-@@ -84,6 +84,9 @@ struct i2caux *dal_i2caux_create(
- 
- 	switch (dce_version) {
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+#endif
- 	case DCE_VERSION_11_0:
- 		return dal_i2caux_dce110_create(as, ctx);
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-index 0c7429c..b54e813 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -50,6 +50,10 @@ struct irq_service *dal_irq_service_create(
- 	struct irq_service_init_data *init_data)
- {
- 	switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		return dal_irq_service_dce110_create(init_data);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		return dal_irq_service_dce110_create(init_data);
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-index fa04f80..78f88b1 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-@@ -77,6 +77,17 @@
- #define ASIC_REV_IS_GODAVARI(rev) \
- 	((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
- 
-+/* VI Family */
-+/* DCE10 */
-+#define VI_TONGA_P_A0 20
-+#define VI_TONGA_P_A1 21
-+#define VI_FIJI_P_A0 60
-+
-+#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
-+		(eChipRev < 40))
-+#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
-+		(eChipRev < 80))
-+
- /* DCE11 */
- #define CZ_CARRIZO_A0 0x01
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index f756d36..8e54862 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -34,6 +34,9 @@ struct dc_bios;
- 
- enum dce_version {
- 	DCE_VERSION_UNKNOWN = (-1),
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	DCE_VERSION_10_0,
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	DCE_VERSION_11_0,
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0711-drm-amd-dal-Fix-issue-with-pipe-powergating-not-call.patch b/common/recipes-kernel/linux/files/0711-drm-amd-dal-Fix-issue-with-pipe-powergating-not-call.patch
deleted file mode 100644
index 0d3f4031..00000000
--- a/common/recipes-kernel/linux/files/0711-drm-amd-dal-Fix-issue-with-pipe-powergating-not-call.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 721a853673f5fadb7e85df677bcb3930b0a1758e Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Wed, 20 Jan 2016 13:41:59 -0500
-Subject: [PATCH 0711/1110] drm/amd/dal: Fix issue with pipe powergating not
- calling pipe 0 correctly
-
-[Description]
-Code double incremented the controller index, so pipe 0 was never programmed.
-
-Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 8afd42e..24b8824 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -981,7 +981,7 @@ static void disable_vga_and_power_gate_all_controllers(
- 		 * powergating. */
- 		dce110_enable_display_pipe_clock_gating(ctx,
- 				true);
--		dce110_enable_display_power_gating(ctx, i+1, dcb,
-+		dce110_enable_display_power_gating(ctx, i, dcb,
- 				PIPE_GATING_CONTROL_ENABLE);
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0712-drm-amd-dal-Do-not-access-mmMC_HUB_RDREQ_DMIF_LIMIT-.patch b/common/recipes-kernel/linux/files/0712-drm-amd-dal-Do-not-access-mmMC_HUB_RDREQ_DMIF_LIMIT-.patch
deleted file mode 100644
index e3680fa6..00000000
--- a/common/recipes-kernel/linux/files/0712-drm-amd-dal-Do-not-access-mmMC_HUB_RDREQ_DMIF_LIMIT-.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From c09775dd062c6bb44e45cafabf92c43b0d711a3a Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 21 Jan 2016 13:33:22 -0500
-Subject: [PATCH 0712/1110] drm/amd/dal: Do not access
- mmMC_HUB_RDREQ_DMIF_LIMIT if in Diag env.
-
-This register is *not* a Display register and is not valid in
-Diagnostics environment on FPGA/Maximus.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  4 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 33 +++++++++++++---------
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |  6 ----
- drivers/gpu/drm/amd/dal/include/dal_types.h        |  6 ++++
- 4 files changed, 27 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index b68ecb7..81bcc1e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -335,9 +335,9 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 
- 	dc->ctx = dc_init_data.ctx;
- 
--	dc->dce_version = dal_adapter_service_get_dce_version(
-+	dc->ctx->dce_version = dal_adapter_service_get_dce_version(
- 			dc_init_data.adapter_srv);
--	dc->dce_environment = dal_adapter_service_get_dce_environment(
-+	dc->ctx->dce_environment = dal_adapter_service_get_dce_environment(
- 			dc_init_data.adapter_srv);
- 
- 	/* Create hardware sequencer */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 5c76d15..392a075 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -842,13 +842,16 @@ void dce110_mem_input_allocate_dmif_buffer(
- 	 * 02 - enable DMIF rdreq limit, disable by DMIF stall = 1
- 	 * 03 - force enable DMIF rdreq limit, ignore DMIF stall / urgent
- 	 */
--	addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
--	value = dal_read_reg(mi->ctx, addr);
--	if (paths_num > 1)
--		set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
--	else
--		set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
--	dal_write_reg(mi->ctx, addr, value);
-+	if (!IS_DIAG_MAXIMUS_DC(mi->ctx)) {
-+		addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
-+		value = dal_read_reg(mi->ctx, addr);
-+
-+		if (paths_num > 1)
-+			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+		else
-+			set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+		dal_write_reg(mi->ctx, addr, value);
-+	}
- 
- register_underflow_int:
- 	/*todo*/;
-@@ -909,13 +912,15 @@ void dce110_mem_input_deallocate_dmif_buffer(
- 	 * 02 - enable dmif rdreq limit, disable by dmif stall=1
- 	 * 03 - force enable dmif rdreq limit, ignore dmif stall/urgent
- 	 * Stella Wong proposed this change. */
--	value = dal_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
--	if (paths_num > 1)
--		set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
--	else
--		set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
--
--	dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
-+	if (!IS_DIAG_MAXIMUS_DC(mi->ctx)) {
-+		value = dal_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
-+		if (paths_num > 1)
-+			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+		else
-+			set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+
-+		dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
-+	}
- }
- 
- static struct mem_input_funcs dce110_mem_input_funcs = {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index be46f97..9d62a24 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -34,12 +34,6 @@ struct dc {
- 
- 	/* HW functions */
- 	struct hw_sequencer_funcs hwss;
--
--	/* Diagnostics */
--	enum dce_version dce_version;
--	enum dce_environment dce_environment;
- };
- 
--#define IS_DIAGNOSTICS_DC(dc) ((dc)->dce_environment == DCE_ENV_DIAG_FPGA_MAXIMUS)
--
- #endif /* __CORE_DC_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 8e54862..73c13c4 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -178,8 +178,14 @@ struct dc_context {
- 
- 	struct dal_logger *logger;
- 	void *cgs_device;
-+
-+	/* Diagnostics */
-+	enum dce_version dce_version;
-+	enum dce_environment dce_environment;
- };
- 
-+#define IS_DIAG_MAXIMUS_DC(dcctx) ((dcctx)->dce_environment == DCE_ENV_DIAG_FPGA_MAXIMUS)
-+
- /* Wireless display structs */
- 
- union dal_remote_display_cea_mode_bitmap {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0713-drm-amd-dal-create-dce100-resource.patch b/common/recipes-kernel/linux/files/0713-drm-amd-dal-create-dce100-resource.patch
deleted file mode 100644
index 1694c249..00000000
--- a/common/recipes-kernel/linux/files/0713-drm-amd-dal-create-dce100-resource.patch
+++ /dev/null
@@ -1,1225 +0,0 @@
-From 43d730fd93c53ecad452edd80ee2fa4b5ad7c1f3 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 20 Jan 2016 17:43:06 -0500
-Subject: [PATCH 0713/1110] drm/amd/dal: create dce100 resource
-
-This has been verified by creating dce100 resouce
-in dce110_hwsequencer
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |    4 +
- drivers/gpu/drm/amd/dal/dc/dce100/Makefile         |   23 +
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 1122 ++++++++++++++++++++
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.h    |   24 +
- 4 files changed, 1173 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index fc1dd0e..05d8ce7 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -9,6 +9,10 @@ ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- DC_LIBS += dce110
- endif
- 
-+ifdef CONFIG_DRM_AMD_DAL_DCE10_0
-+DC_LIBS += dce100
-+endif
-+
- AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS)))
- 
- include $(AMD_DC)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-new file mode 100644
-index 0000000..4c0b4d5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-@@ -0,0 +1,23 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE100 = dce100_resource.o
-+
-+AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
-+
-+AMD_DAL_FILES += $(AMD_DAL_DCE100)
-+
-+
-+###############################################################################
-+# DCE 10x
-+###############################################################################
-+ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
-+TG_DCE100 = dce100_resource.o
-+
-+AMD_DAL_TG_DCE100 = $(addprefix \
-+	$(AMDDALPATH)/dc/dce100/,$(TG_DCE100))
-+
-+AMD_DAL_FILES += $(AMD_DAL_TG_DCE100)
-+endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-new file mode 100644
-index 0000000..72493d7
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -0,0 +1,1122 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dc_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "include/timing_generator_interface.h"
-+
-+#include "dce110/dce110_timing_generator.h"
-+#include "dce110/dce110_link_encoder.h"
-+#include "dce110/dce110_mem_input.h"
-+#include "dce110/dce110_ipp.h"
-+#include "dce110/dce110_transform.h"
-+#include "dce110/dce110_stream_encoder.h"
-+#include "dce110/dce110_opp.h"
-+
-+#include "dce/dce_10_0_d.h"
-+
-+enum dce100_clk_src_array_id {
-+	DCE100_CLK_SRC_PLL0 = 0,
-+	DCE100_CLK_SRC_PLL1,
-+	DCE100_CLK_SRC_EXT,
-+
-+	DCE100_CLK_SRC_TOTAL
-+};
-+
-+static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	}
-+};
-+
-+static const struct dce110_stream_enc_offsets dce100_str_enc_offsets[] = {
-+	{
-+		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG3_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP3_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG4_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP4_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG5_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP5_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG6_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP6_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	}
-+};
-+
-+static const struct dce110_link_enc_offsets dce100_lnk_enc_reg_offsets[] = {
-+	{
-+		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG3_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP3_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG4_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP4_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG5_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP5_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	},
-+	{
-+		.dig = (mmDIG6_DIG_FE_CNTL - mmDIG_FE_CNTL),
-+		.dp  = (mmDP6_DP_SEC_CNTL - mmDP_SEC_CNTL)
-+	}
-+};
-+
-+static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
-+	{
-+		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	}
-+};
-+
-+static const struct dce110_transform_reg_offsets dce100_xfm_offsets[] = {
-+{
-+	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{
-+	.scl_offset = (mmSCL3_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB3_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL4_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB4_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL5_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB5_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+}
-+};
-+
-+static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
-+}
-+};
-+
-+static struct timing_generator *dce100_timing_generator_create(
-+		struct adapter_service *as,
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_timing_generator));
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	if (dce110_timing_generator_construct(tg110, as, ctx, instance,
-+			offsets))
-+		return &tg110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, tg110);
-+	return NULL;
-+}
-+
-+static struct stream_encoder *dce100_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp,
-+	const struct dce110_stream_enc_offsets *offsets)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, offsets))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, enc110);
-+	return NULL;
-+}
-+
-+static struct mem_input *dce100_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offset)
-+{
-+	struct dce110_mem_input *mem_input110 =
-+		dc_service_alloc(ctx, sizeof(struct dce110_mem_input));
-+
-+	if (!mem_input110)
-+		return NULL;
-+
-+	if (dce110_mem_input_construct(mem_input110,
-+			ctx, inst, offset))
-+		return &mem_input110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, mem_input110);
-+	return NULL;
-+}
-+
-+static void dce100_transform_destroy(struct transform **xfm)
-+{
-+	dc_service_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce100_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_transform_reg_offsets *offsets)
-+{
-+	struct dce110_transform *transform =
-+		dc_service_alloc(ctx, sizeof(struct dce110_transform));
-+
-+	if (!transform)
-+		return NULL;
-+
-+	if (dce110_transform_construct(transform, ctx, inst, offsets))
-+		return &transform->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, transform);
-+	return NULL;
-+}
-+
-+static struct input_pixel_processor *dce100_ipp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offsets)
-+{
-+	struct dce110_ipp *ipp =
-+		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
-+
-+	if (!ipp)
-+		return NULL;
-+
-+	if (dce110_ipp_construct(ipp, ctx, inst, offsets))
-+		return &ipp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, ipp);
-+	return NULL;
-+}
-+
-+struct link_encoder *dce100_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		dc_service_alloc(
-+			enc_init_data->ctx,
-+			sizeof(struct dce110_link_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce110_link_encoder_construct(
-+			enc110,
-+			enc_init_data,
-+			&dce100_lnk_enc_reg_offsets[enc_init_data->transmitter]))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(enc_init_data->ctx, enc110);
-+	return NULL;
-+}
-+
-+bool dce100_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	struct dc *dc,
-+	struct resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct clock_source_init_data clk_src_init_data = { 0 };
-+	struct audio_init_data audio_init_data = { 0 };
-+	struct dc_context *ctx = dc->ctx;
-+
-+	pool->adapter_srv = adapter_serv;
-+
-+	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
-+
-+	clk_src_init_data.as = adapter_serv;
-+	clk_src_init_data.ctx = ctx;
-+	clk_src_init_data.clk_src_id.enum_id = ENUM_ID_1;
-+	clk_src_init_data.clk_src_id.type = OBJECT_TYPE_CLOCK_SOURCE;
-+	pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
-+
-+	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL0;
-+	pool->clock_sources[DCE100_CLK_SRC_PLL0] = dal_clock_source_create(
-+							&clk_src_init_data);
-+	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL1;
-+	pool->clock_sources[DCE100_CLK_SRC_PLL1] = dal_clock_source_create(
-+							&clk_src_init_data);
-+	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_EXTERNAL;
-+	pool->clock_sources[DCE100_CLK_SRC_EXT] = dal_clock_source_create(
-+							&clk_src_init_data);
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] == NULL) {
-+			dal_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
-+	if (pool->display_clock == NULL) {
-+		dal_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+
-+		init_data.ctx = dc->ctx;
-+		pool->irqs = dal_irq_service_create(
-+				dal_adapter_service_get_dce_version(
-+					dc->res_pool.adapter_srv),
-+				&init_data);
-+		if (!pool->irqs)
-+			goto irqs_create_fail;
-+
-+	}
-+
-+	pool->controller_count =
-+		dal_adapter_service_get_func_controllers_num(adapter_serv);
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
-+			adapter_serv);
-+	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+	if (pool->scaler_filter == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dal_error("DC: failed to create filter!\n");
-+		goto filter_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		pool->timing_generators[i] = dce100_timing_generator_create(
-+				adapter_serv, ctx, i, &dce100_tg_offsets[i]);
-+		if (pool->timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->mis[i] = dce100_mem_input_create(ctx, i,
-+				&dce100_mi_reg_offsets[i]);
-+		if (pool->mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->ipps[i] = dce100_ipp_create(ctx, i,
-+				&dce100_ipp_reg_offsets[i]);
-+		if (pool->ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->transforms[i] = dce100_transform_create(
-+					ctx, i, &dce100_xfm_offsets[i]);
-+		if (pool->transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create transform!\n");
-+			goto controller_create_fail;
-+		}
-+		pool->transforms[i]->funcs->transform_set_scaler_filter(
-+				pool->transforms[i],
-+				pool->scaler_filter);
-+
-+		pool->opps[i] = dce110_opp_create(ctx, i);
-+		if (pool->opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+	}
-+
-+	audio_init_data.as = adapter_serv;
-+	audio_init_data.ctx = ctx;
-+	pool->audio_count = 0;
-+	for (i = 0; i < pool->controller_count; i++) {
-+		struct graphics_object_id obj_id;
-+
-+		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		if (false == dal_graphics_object_id_is_valid(obj_id)) {
-+			/* no more valid audio objects */
-+			break;
-+		}
-+
-+		audio_init_data.audio_stream_id = obj_id;
-+		pool->audios[i] = dal_audio_create(&audio_init_data);
-+		if (pool->audios[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create DPPs!\n");
-+			goto audio_create_fail;
-+		}
-+		pool->audio_count++;
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		/* TODO: rework fragile code*/
-+		if (pool->stream_engines.u_all & 1 << i) {
-+			pool->stream_enc[i] = dce100_stream_encoder_create(
-+				i, dc->ctx,
-+				dal_adapter_service_get_bios_parser(
-+					adapter_serv),
-+				&dce100_str_enc_offsets[i]);
-+			if (pool->stream_enc[i] == NULL) {
-+				BREAK_TO_DEBUGGER();
-+				dal_error("DC: failed to create stream_encoder!\n");
-+				goto stream_enc_create_fail;
-+			}
-+		}
-+	}
-+
-+	return true;
-+
-+stream_enc_create_fail:
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dc_service_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+audio_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+
-+controller_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce110_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce100_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce110_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dc_service_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL)	{
-+			dc_service_free(pool->timing_generators[i]->ctx,
-+				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+filter_create_fail:
-+	dal_irq_service_destroy(&pool->irqs);
-+
-+irqs_create_fail:
-+	dal_display_clock_destroy(&pool->display_clock);
-+
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dal_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+	return false;
-+}
-+
-+void dce100_destruct_resource_pool(struct resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce110_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce100_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce110_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dc_service_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL)	{
-+			dc_service_free(pool->timing_generators[i]->ctx,
-+					DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dc_service_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dal_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+
-+	for (i = 0; i < pool->audio_count; i++)	{
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+	if (pool->display_clock != NULL)
-+		dal_display_clock_destroy(&pool->display_clock);
-+
-+	if (pool->scaler_filter != NULL)
-+		dal_scaler_filter_destroy(&pool->scaler_filter);
-+
-+	if (pool->irqs != NULL)
-+		dal_irq_service_destroy(&pool->irqs);
-+
-+	if (pool->adapter_srv != NULL)
-+		dal_adapter_service_destroy(&pool->adapter_srv);
-+}
-+
-+static struct clock_source *find_first_free_pll(
-+		struct resource_context *res_ctx)
-+{
-+	if (res_ctx->clock_source_ref_count[DCE100_CLK_SRC_PLL0] == 0)
-+		return res_ctx->pool.clock_sources[DCE100_CLK_SRC_PLL0];
-+
-+	if (res_ctx->clock_source_ref_count[DCE100_CLK_SRC_PLL1] == 0)
-+		return res_ctx->pool.clock_sources[DCE100_CLK_SRC_PLL1];
-+
-+	return 0;
-+}
-+
-+static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-+{
-+	switch (crtc_id) {
-+	case CONTROLLER_ID_D0:
-+		return DTO_SOURCE_ID0;
-+	case CONTROLLER_ID_D1:
-+		return DTO_SOURCE_ID1;
-+	case CONTROLLER_ID_D2:
-+		return DTO_SOURCE_ID2;
-+	case CONTROLLER_ID_D3:
-+		return DTO_SOURCE_ID3;
-+	case CONTROLLER_ID_D4:
-+		return DTO_SOURCE_ID4;
-+	case CONTROLLER_ID_D5:
-+		return DTO_SOURCE_ID5;
-+	default:
-+		return DTO_SOURCE_UNKNOWN;
-+	}
-+}
-+
-+static void build_audio_output(
-+	const struct core_stream *stream,
-+	struct audio_output *audio_output)
-+{
-+	audio_output->engine_id = stream->stream_enc->id;
-+
-+	audio_output->signal = stream->signal;
-+
-+	/* audio_crtc_info  */
-+
-+	audio_output->crtc_info.h_total =
-+		stream->public.timing.h_total;
-+
-+	/*
-+	 * Audio packets are sent during actual CRTC blank physical signal, we
-+	 * need to specify actual active signal portion
-+	 */
-+	audio_output->crtc_info.h_active =
-+			stream->public.timing.h_addressable
-+			+ stream->public.timing.h_border_left
-+			+ stream->public.timing.h_border_right;
-+
-+	audio_output->crtc_info.v_active =
-+			stream->public.timing.v_addressable
-+			+ stream->public.timing.v_border_top
-+			+ stream->public.timing.v_border_bottom;
-+
-+	audio_output->crtc_info.pixel_repetition = 1;
-+
-+	audio_output->crtc_info.interlaced =
-+			stream->public.timing.flags.INTERLACE;
-+
-+	audio_output->crtc_info.refresh_rate =
-+		(stream->public.timing.pix_clk_khz*1000)/
-+		(stream->public.timing.h_total*stream->public.timing.v_total);
-+
-+	audio_output->crtc_info.color_depth =
-+		stream->public.timing.display_color_depth;
-+
-+	audio_output->crtc_info.requested_pixel_clock =
-+			stream->pix_clk_params.requested_pix_clk;
-+
-+	/*
-+	 * TODO - Investigate why calculated pixel clk has to be
-+	 * requested pixel clk
-+	 */
-+	audio_output->crtc_info.calculated_pixel_clock =
-+			stream->pix_clk_params.requested_pix_clk;
-+
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		audio_output->pll_info.dp_dto_source_clock_in_khz =
-+			dal_display_clock_get_dp_ref_clk_frequency(
-+				stream->dis_clk);
-+	}
-+
-+	audio_output->pll_info.feed_back_divider =
-+			stream->pll_settings.feedback_divider;
-+
-+	audio_output->pll_info.dto_source =
-+		translate_to_dto_source(
-+			stream->controller_idx + 1);
-+
-+	/* TODO hard code to enable for now. Need get from stream */
-+	audio_output->pll_info.ss_enabled = true;
-+
-+	audio_output->pll_info.ss_percentage =
-+			stream->pll_settings.ss_percentage;
-+}
-+
-+static void get_pixel_clock_parameters(
-+	const struct core_stream *stream,
-+	struct pixel_clk_params *pixel_clk_params)
-+{
-+	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
-+	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
-+	pixel_clk_params->signal_type = stream->sink->public.sink_signal;
-+	pixel_clk_params->controller_id = stream->controller_idx + 1;
-+	/* TODO: un-hardcode*/
-+	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+	pixel_clk_params->flags.ENABLE_SS = 0;
-+	pixel_clk_params->color_depth =
-+		stream->public.timing.display_color_depth;
-+	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-+}
-+
-+static enum dc_status build_stream_hw_param(struct core_stream *stream)
-+{
-+	/*TODO: unhardcode*/
-+	stream->max_tmds_clk_from_edid_in_mhz = 0;
-+	stream->max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	stream->max_hdmi_pixel_clock = 600000;
-+
-+	get_pixel_clock_parameters(stream, &stream->pix_clk_params);
-+	dal_clock_source_get_pix_clk_dividers(
-+		stream->clock_source,
-+		&stream->pix_clk_params,
-+		&stream->pll_settings);
-+
-+	build_audio_output(stream, &stream->audio_output);
-+
-+	return DC_OK;
-+}
-+
-+static enum dc_status validate_mapped_resource(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	enum dc_status status = DC_OK;
-+	uint8_t i, j;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct core_link *link = stream->sink->link;
-+
-+			if (!stream->tg->funcs->validate_timing(
-+					stream->tg, &stream->public.timing))
-+				return DC_FAIL_CONTROLLER_VALIDATE;
-+
-+			if (stream->signal == SIGNAL_TYPE_VIRTUAL)
-+				return status;
-+
-+			status = build_stream_hw_param(stream);
-+
-+			if (status != DC_OK)
-+				return status;
-+
-+			if (!link->link_enc->funcs->validate_output_with_stream(
-+					link->link_enc,
-+					stream))
-+				return DC_FAIL_ENC_VALIDATE;
-+
-+			/* TODO: validate audio ASIC caps, encoder */
-+
-+			status = dc_link_validate_mode_timing(stream->sink,
-+					link,
-+					&stream->public.timing);
-+
-+			if (status != DC_OK)
-+				return status;
-+
-+			build_info_frame(stream);
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce100_validate_bandwidth(
-+	const struct dc *dc,
-+	struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t number_of_displays = 0;
-+	uint8_t max_htaps = 1;
-+	uint8_t max_vtaps = 1;
-+	bool all_displays_in_sync = true;
-+	struct dc_crtc_timing prev_timing;
-+
-+	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct bw_calcs_input_single_display *disp = &context->
-+				bw_mode_data.displays_data[number_of_displays];
-+
-+			if (target->status.surface_count == 0) {
-+				disp->graphics_scale_ratio = bw_int_to_fixed(1);
-+				disp->graphics_h_taps = 2;
-+				disp->graphics_v_taps = 2;
-+
-+				/* TODO: remove when bw formula accepts taps per
-+				 * display
-+				 */
-+				if (max_vtaps < 2)
-+					max_vtaps = 2;
-+				if (max_htaps < 2)
-+					max_htaps = 2;
-+
-+			} else {
-+				disp->graphics_scale_ratio =
-+					fixed31_32_to_bw_fixed(
-+						stream->ratios.vert.value);
-+				disp->graphics_h_taps = stream->taps.h_taps;
-+				disp->graphics_v_taps = stream->taps.v_taps;
-+
-+				/* TODO: remove when bw formula accepts taps per
-+				 * display
-+				 */
-+				if (max_vtaps < stream->taps.v_taps)
-+					max_vtaps = stream->taps.v_taps;
-+				if (max_htaps < stream->taps.h_taps)
-+					max_htaps = stream->taps.h_taps;
-+			}
-+
-+			disp->graphics_src_width =
-+					stream->public.timing.h_addressable;
-+			disp->graphics_src_height =
-+					stream->public.timing.v_addressable;
-+			disp->h_total = stream->public.timing.h_total;
-+			disp->pixel_rate = bw_frc_to_fixed(
-+				stream->public.timing.pix_clk_khz, 1000);
-+
-+			/*TODO: get from surface*/
-+			disp->graphics_bytes_per_pixel = 4;
-+			disp->graphics_tiling_mode = bw_def_tiled;
-+
-+			/* DCE11 defaults*/
-+			disp->graphics_lb_bpc = 10;
-+			disp->graphics_interlace_mode = false;
-+			disp->fbc_enable = false;
-+			disp->lpt_enable = false;
-+			disp->graphics_stereo_mode = bw_def_mono;
-+			disp->underlay_mode = bw_def_none;
-+
-+			/*All displays will be synchronized if timings are all
-+			 * the same
-+			 */
-+			if (number_of_displays != 0 && all_displays_in_sync)
-+				if (dal_memcmp(&prev_timing,
-+					&stream->public.timing,
-+					sizeof(struct dc_crtc_timing)) != 0)
-+					all_displays_in_sync = false;
-+			if (number_of_displays == 0)
-+				prev_timing = stream->public.timing;
-+
-+			number_of_displays++;
-+		}
-+	}
-+
-+	/* TODO: remove when bw formula accepts taps per
-+	 * display
-+	 */
-+	context->bw_mode_data.displays_data[0].graphics_v_taps = max_vtaps;
-+	context->bw_mode_data.displays_data[0].graphics_h_taps = max_htaps;
-+
-+	context->bw_mode_data.number_of_displays = number_of_displays;
-+	context->bw_mode_data.display_synchronization_enabled =
-+							all_displays_in_sync;
-+
-+	dal_logger_write(
-+		dc->ctx->logger,
-+		LOG_MAJOR_BWM,
-+		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-+		"%s: start\n",
-+		__func__);
-+
-+	if (!bw_calcs(
-+			dc->ctx,
-+			&dc->bw_dceip,
-+			&dc->bw_vbios,
-+			&context->bw_mode_data,
-+			&context->bw_results))
-+		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-+	else
-+		result =  DC_OK;
-+
-+	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
-+		dal_logger_write(dc->ctx->logger,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_MODE_VALIDATION,
-+			"%s: Bandwidth validation failed!",
-+			__func__);
-+
-+	if (dal_memcmp(&dc->current_context.bw_results,
-+			&context->bw_results, sizeof(context->bw_results))) {
-+		struct log_entry log_entry;
-+
-+		dal_logger_open(
-+			dc->ctx->logger,
-+			&log_entry,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
-+		dal_logger_append(&log_entry, "%s: finish, numDisplays: %d\n"
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			__func__, number_of_displays,
-+			context->bw_results.nbp_state_change_wm_ns[0].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[0].a_mark,
-+			context->bw_results.urgent_wm_ns[0].b_mark,
-+			context->bw_results.urgent_wm_ns[0].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[1].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[1].a_mark,
-+			context->bw_results.urgent_wm_ns[1].b_mark,
-+			context->bw_results.urgent_wm_ns[1].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[2].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[2].a_mark,
-+			context->bw_results.urgent_wm_ns[2].b_mark,
-+			context->bw_results.urgent_wm_ns[2].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].a_mark,
-+			context->bw_results.stutter_mode_enable);
-+		dal_logger_append(&log_entry,
-+			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
-+			"sclk: %d sclk_sleep: %d yclk: %d blackout_duration: %d\n",
-+			context->bw_results.cpuc_state_change_enable,
-+			context->bw_results.cpup_state_change_enable,
-+			context->bw_results.nbp_state_change_enable,
-+			context->bw_results.all_displays_in_sync,
-+			context->bw_results.dispclk_khz,
-+			context->bw_results.required_sclk,
-+			context->bw_results.required_sclk_deep_sleep,
-+			context->bw_results.required_yclk,
-+			context->bw_results.required_blackout_duration_us);
-+		dal_logger_close(&log_entry);
-+	}
-+	return result;
-+}
-+
-+static void set_target_unchanged(
-+		struct validate_context *context,
-+		uint8_t target_idx)
-+{
-+	uint8_t i;
-+	struct core_target *target = context->targets[target_idx];
-+
-+	context->target_flags[target_idx].unchanged = true;
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		struct core_stream *core_stream =
-+			DC_STREAM_TO_CORE(target->public.streams[i]);
-+		uint8_t index = core_stream->controller_idx;
-+
-+		context->res_ctx.controller_ctx[index].flags.unchanged = true;
-+	}
-+}
-+
-+static enum dc_status map_clock_resources(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j;
-+
-+	/* mark resources used for targets that are already active */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (!context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			reference_clock_source(
-+				&context->res_ctx,
-+				stream->clock_source);
-+		}
-+	}
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			if (dc_is_dp_signal(stream->signal)
-+				|| stream->signal == SIGNAL_TYPE_VIRTUAL)
-+				stream->clock_source = context->res_ctx.
-+					pool.clock_sources[DCE100_CLK_SRC_EXT];
-+			else
-+				stream->clock_source =
-+					find_used_clk_src_for_sharing(
-+							context, stream);
-+			if (stream->clock_source == NULL)
-+				stream->clock_source =
-+					find_first_free_pll(&context->res_ctx);
-+
-+			if (stream->clock_source == NULL)
-+				return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+			reference_clock_source(
-+					&context->res_ctx,
-+					stream->clock_source);
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce100_validate_with_context(
-+		const struct dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count,
-+		struct validate_context *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t i, j;
-+	struct dc_context *dc_ctx = dc->ctx;
-+
-+	for (i = 0; i < set_count; i++) {
-+		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+
-+		for (j = 0; j < dc->current_context.target_count; j++)
-+			if (dc->current_context.targets[j] == context->targets[i])
-+				set_target_unchanged(context, i);
-+
-+		if (!context->target_flags[i].unchanged)
-+			if (!logical_attach_surfaces_to_target(
-+					(struct dc_surface **)set[i].surfaces,
-+					set[i].surface_count,
-+					&context->targets[i]->public)) {
-+				DC_ERROR("Failed to attach surface to target!\n");
-+				return DC_FAIL_ATTACH_SURFACES;
-+			}
-+	}
-+
-+	context->target_count = set_count;
-+
-+	context->res_ctx.pool = dc->res_pool;
-+
-+	result = map_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = map_clock_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = validate_mapped_resource(dc, context);
-+
-+	if (result == DC_OK)
-+		build_scaling_params_for_context(dc, context);
-+
-+	if (result == DC_OK)
-+		result = dce100_validate_bandwidth(dc, context);
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-new file mode 100644
-index 0000000..1ae3ecc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-@@ -0,0 +1,24 @@
-+/*
-+ * dce100_resource.h
-+ *
-+ *  Created on: 2016-01-20
-+ *      Author: qyang
-+ */
-+
-+#ifndef DCE100_RESOURCE_H_
-+#define DCE100_RESOURCE_H_
-+
-+struct adapter_service;
-+struct dc;
-+struct resource_pool;
-+struct dc_validation_set;
-+
-+
-+bool dce100_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	struct dc *dc,
-+	struct resource_pool *pool);
-+
-+void dce100_destruct_resource_pool(struct resource_pool *pool);
-+
-+#endif /* DCE100_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0714-drm-amd-dal-Removed-dce_version-from-dc_context.patch b/common/recipes-kernel/linux/files/0714-drm-amd-dal-Removed-dce_version-from-dc_context.patch
deleted file mode 100644
index ce6e781e..00000000
--- a/common/recipes-kernel/linux/files/0714-drm-amd-dal-Removed-dce_version-from-dc_context.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From e4ed5a099fbafc6a8902d9fff731e91c338ccea2 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 21 Jan 2016 15:52:43 -0500
-Subject: [PATCH 0714/1110] drm/amd/dal: Removed dce_version from dc_context.
-
-Also, improved valdation of 'number of links' to create,
-which take into account 'Diagnostics' environment.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c        | 20 ++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 10 +++++-----
- drivers/gpu/drm/amd/dal/include/dal_types.h |  2 --
- 3 files changed, 17 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 81bcc1e..d953784 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -83,17 +83,23 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 
- 	dc->link_count = 0;
- 
--	dcb = (struct dc_bios*)dal_adapter_service_get_bios_parser(init_params->adapter_srv);
-+	dcb = dal_adapter_service_get_bios_parser(init_params->adapter_srv);
- 
- 	connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
--	if (0 == connectors_num || connectors_num > ENUM_ID_COUNT) {
--		dal_error("DC: Invalid number of connectors!\n");
-+	if (connectors_num > ENUM_ID_COUNT) {
-+		dal_error("DC: Number of connectors %d exceeds maximum of %d!\n",
-+				connectors_num, ENUM_ID_COUNT);
- 		return false;
- 	}
- 
--	dal_output_to_console("%s: connectors_num:%d\n", __func__,
--			connectors_num);
-+	if (connectors_num == 0 && init_params->num_virtual_links == 0) {
-+		dal_error("DC: Number of connectors can not be zero!\n");
-+		return false;
-+	}
-+
-+	dal_output_to_console("DC: %s: connectors_num: physical:%d, virtual:%d\n",
-+			__func__, connectors_num, init_params->num_virtual_links);
- 
- 	for (i = 0; i < connectors_num; i++) {
- 		struct link_init_data link_init_params = {0};
-@@ -335,8 +341,6 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 
- 	dc->ctx = dc_init_data.ctx;
- 
--	dc->ctx->dce_version = dal_adapter_service_get_dce_version(
--			dc_init_data.adapter_srv);
- 	dc->ctx->dce_environment = dal_adapter_service_get_dce_environment(
- 			dc_init_data.adapter_srv);
- 
-@@ -522,7 +526,7 @@ bool dc_commit_targets(
- 	dal_logger_write(dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC,
--				"%s: %d targets",
-+				"%s: %d targets\n",
- 				__func__,
- 				target_count);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index e7df2e2..a71034c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -460,7 +460,7 @@ void dc_target_log(
- 	dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"core_target 0x%x: surface_count=%d, stream_count=%d",
-+			"core_target 0x%x: surface_count=%d, stream_count=%d\n",
- 			core_target,
- 			core_target->status.surface_count,
- 			core_target->public.stream_count);
-@@ -472,7 +472,7 @@ void dc_target_log(
- 		dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;",
-+			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n",
- 			core_stream,
- 			core_stream->public.src.x,
- 			core_stream->public.src.y,
-@@ -485,20 +485,20 @@ void dc_target_log(
- 		dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"\tpix_clk_khz: %d, h_total: %d, v_total: %d",
-+			"\tpix_clk_khz: %d, h_total: %d, v_total: %d\n",
- 			core_stream->public.timing.pix_clk_khz,
- 			core_stream->public.timing.h_total,
- 			core_stream->public.timing.v_total);
- 		dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"\tsink name: %s, serial: %d",
-+			"\tsink name: %s, serial: %d\n",
- 			core_stream->sink->public.edid_caps.display_name,
- 			core_stream->sink->public.edid_caps.serial_number);
- 		dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"\tlink: %d",
-+			"\tlink: %d\n",
- 			core_stream->sink->link->public.link_index);
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 73c13c4..0e16ebb 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -179,8 +179,6 @@ struct dc_context {
- 	struct dal_logger *logger;
- 	void *cgs_device;
- 
--	/* Diagnostics */
--	enum dce_version dce_version;
- 	enum dce_environment dce_environment;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0715-drm-amd-dal-add-virtual-link-and-stream-encoders.patch b/common/recipes-kernel/linux/files/0715-drm-amd-dal-add-virtual-link-and-stream-encoders.patch
deleted file mode 100644
index b49a65d2..00000000
--- a/common/recipes-kernel/linux/files/0715-drm-amd-dal-add-virtual-link-and-stream-encoders.patch
+++ /dev/null
@@ -1,799 +0,0 @@
-From fd5a57c67269301e7441f4e3acff12bd42d1bf2f Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 21 Jan 2016 11:38:21 -0500
-Subject: [PATCH 0715/1110] drm/amd/dal: add virtual link and stream encoders
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |   2 +-
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |   1 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  37 ++++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   7 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  13 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  20 ++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  18 ++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.h    |   1 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   4 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   1 +
- drivers/gpu/drm/amd/dal/dc/virtual/Makefile        |   9 ++
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.c  | 131 +++++++++++++++++++++
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.h  |  35 ++++++
- .../amd/dal/dc/virtual/virtual_stream_encoder.c    | 124 +++++++++++++++++++
- .../amd/dal/dc/virtual/virtual_stream_encoder.h    |  39 ++++++
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   |   6 +-
- 17 files changed, 406 insertions(+), 44 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index 05d8ce7..4396203 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -3,7 +3,7 @@
- #
- 
- DC_LIBS = adapter asic_capability audio basics bios calcs \
--dcs gpio gpu i2caux irq
-+dcs gpio gpu i2caux irq virtual
- 
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- DC_LIBS += dce110
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index e0407f4..83a80d5 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -311,6 +311,7 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
- 		return ENCODER_OBJECT_ID_INTERNAL_VCE;
- 	case ENCODER_ID_EXTERNAL_GENERIC_DVO:
- 		return ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO;
-+	case ENCODER_ID_INTERNAL_VIRTUAL:
- 	case ENCODER_ID_UNKNOWN:
- 		return ENCODER_OBJECT_ID_NONE;
- 	default:
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index d953784..71df979 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -40,6 +40,7 @@
- #include "bandwidth_calcs.h"
- #include "include/irq_service_interface.h"
- #include "inc/transform.h"
-+#include "../virtual/virtual_link_encoder.h"
- 
- #include "link_hwss.h"
- #include "link_encoder.h"
-@@ -125,6 +126,7 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 	for (i = 0; i < init_params->num_virtual_links; i++) {
- 		struct core_link *link =
- 			dc_service_alloc(dc->ctx, sizeof(*link));
-+		struct encoder_init_data enc_init = { 0 };
- 
- 		if (link == NULL) {
- 			BREAK_TO_DEBUGGER();
-@@ -135,6 +137,22 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 		link->ctx = init_params->ctx;
- 		link->dc = dc;
- 		link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
-+		link->link_id.type = OBJECT_TYPE_CONNECTOR;
-+		link->link_id.id = CONNECTOR_ID_VIRTUAL;
-+		link->link_id.enum_id = ENUM_ID_1;
-+		link->link_enc =
-+			dc_service_alloc(dc->ctx, sizeof(*link->link_enc));
-+
-+		enc_init.adapter_service = init_params->adapter_srv;
-+		enc_init.ctx = init_params->ctx;
-+		enc_init.channel = CHANNEL_ID_UNKNOWN;
-+		enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
-+		enc_init.transmitter = TRANSMITTER_UNKNOWN;
-+		enc_init.connector = link->link_id;
-+		enc_init.encoder.type = OBJECT_TYPE_ENCODER;
-+		enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
-+		enc_init.encoder.enum_id = ENUM_ID_1;
-+		virtual_link_encoder_construct(link->link_enc, &enc_init);
- 
- 		link->public.link_index = dc->link_count;
- 		dc->links[dc->link_count] = link;
-@@ -180,8 +198,7 @@ static void init_hw(struct dc *dc)
- 		 * required signal (which may be different from the
- 		 * default signal on connector). */
- 		struct core_link *link = dc->links[i];
--		if (link->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
--			link->link_enc->funcs->hw_init(link->link_enc);
-+		link->link_enc->funcs->hw_init(link->link_enc);
- 	}
- 
- 	for(i = 0; i < dc->res_pool.controller_count; i++) {
-@@ -355,6 +372,7 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 
- 	if (!dc->hwss.construct_resource_pool(
- 			dc_init_data.adapter_srv,
-+			dc_init_data.num_virtual_links,
- 			dc,
- 			&dc->res_pool))
- 		goto construct_resource_fail;
-@@ -866,23 +884,24 @@ bool dc_link_add_remote_sink(const struct dc_link *link, struct dc_sink *sink)
- 
- 	dc_link->remote_sinks[link->sink_count] = sink;
- 	dc_link->sink_count++;
--	if (sink->sink_signal == SIGNAL_TYPE_VIRTUAL
--		&& link->connector_signal == SIGNAL_TYPE_VIRTUAL)
--		dc_link->type = dc_connection_single;
- 
- 	return true;
- }
- 
--void dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink)
-+void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
- {
- 	struct core_link *core_link = DC_LINK_TO_LINK(link);
- 	struct dc_link *dc_link = &core_link->public;
- 
- 	dc_link->local_sink = sink;
--	dc_link->sink_count = 1;
--	if (sink->sink_signal == SIGNAL_TYPE_VIRTUAL
--		&& link->connector_signal == SIGNAL_TYPE_VIRTUAL)
-+
-+	if (sink == NULL) {
-+		dc_link->sink_count = 0;
-+		dc_link->type = dc_connection_none;
-+	} else {
-+		dc_link->sink_count = 1;
- 		dc_link->type = dc_connection_single;
-+	}
- }
- 
- void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 3f6a7bb..912f3fe 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1228,7 +1228,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- /****************************enable_link***********************************/
- static enum dc_status enable_link(struct core_stream *stream)
- {
--	enum dc_status status;
-+	enum dc_status status = DC_ERROR_UNEXPECTED;
- 	switch (stream->signal) {
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_EDP:
-@@ -1244,9 +1244,10 @@ static enum dc_status enable_link(struct core_stream *stream)
- 		enable_link_hdmi(stream);
- 		status = DC_OK;
- 		break;
--
-+	case SIGNAL_TYPE_VIRTUAL:
-+		status = DC_OK;
-+		break;
- 	default:
--		status = DC_ERROR_UNEXPECTED;
- 		break;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 7cc4ed2..c52a1e2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -457,11 +457,8 @@ static void fill_display_configs(
- 			cfg->src_width = stream->public.src.width;
- 			cfg->ddi_channel_mapping =
- 				stream->sink->link->ddi_channel_mapping.raw;
--			if (stream->signal != SIGNAL_TYPE_VIRTUAL)
--				cfg->transmitter =
-+			cfg->transmitter =
- 				stream->sink->link->link_enc->transmitter;
--			else
--				cfg->transmitter = TRANSMITTER_UNKNOWN;
- 			cfg->link_settings =
- 					stream->sink->link->cur_link_settings;
- 			cfg->sym_clock = stream->public.timing.pix_clk_khz;
-@@ -745,14 +742,6 @@ enum dc_status map_resources(
- 			.flags.timing_changed =
- 				check_timing_change(curr_stream, stream);
- 
--			/*
--			 * we do not need stream encoder or audio resources
--			 * when connecting to virtual link
--			 */
--			if (stream->sink->link->public.connector_signal ==
--							SIGNAL_TYPE_VIRTUAL)
--				continue;
--
- 			stream->stream_enc =
- 				find_first_free_match_stream_enc_for_link(
- 					&context->res_ctx,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index c541ecf..a06a8a7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -318,7 +318,7 @@ void dc_link_remove_remote_sink(
- 	const struct dc_sink *sink);
- 
- /* Used by diagnostics for virtual link at the moment */
--void dc_link_add_sink(const struct dc_link *link, struct dc_sink *sink);
-+void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink);
- 
- /*******************************************************************************
-  * Sink Interfaces - A sink corresponds to a display output device
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 24b8824..44ad5a2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -806,8 +806,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		 */
- 		stream->tg->funcs->set_blank(stream->tg, true);
- 
--		if (stream->signal != SIGNAL_TYPE_VIRTUAL)
--			core_link_disable_stream(stream->sink->link, stream);
-+		core_link_disable_stream(stream->sink->link, stream);
- 
- 		/*TODO: AUTO check if timing changed*/
- 		if (false == dal_clock_source_program_pix_clk(
-@@ -818,7 +817,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			return DC_ERROR_UNEXPECTED;
- 		}
- 
--
- 		stream->tg->funcs->program_timing(
- 				stream->tg,
- 				&stream->public.timing,
-@@ -839,6 +837,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		}
- 	}
- 
-+	/* TODO: move to stream encoder */
- 	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
- 		if (DC_OK != bios_parser_crtc_source_select(stream)) {
- 			BREAK_TO_DEBUGGER();
-@@ -853,10 +852,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 
- 	program_fmt(opp, &stream->fmt_bit_depth, &stream->clamping);
- 
--	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
--		stream->sink->link->link_enc->funcs->setup(
--			stream->sink->link->link_enc,
--			stream->signal);
-+	stream->sink->link->link_enc->funcs->setup(
-+		stream->sink->link->link_enc,
-+		stream->signal);
- 
- 	if (dc_is_dp_signal(stream->signal))
- 		stream->stream_enc->funcs->dp_set_stream_attribute(
-@@ -900,7 +898,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			context->res_ctx.pool.timing_generators[controller_idx],
- 			color_space);
- 
--	if (timing_changed && stream->signal != SIGNAL_TYPE_VIRTUAL) {
-+	if (timing_changed) {
- 		core_link_enable_stream(stream->sink->link, stream);
- 	} else {
- 		core_link_update_stream(stream->sink->link, stream);
-@@ -920,8 +918,7 @@ static void power_down_encoders(struct dc *dc)
- 	int i;
- 
- 	for (i = 0; i < dc->link_count; i++) {
--		if (dc->links[i]->public.connector_signal != SIGNAL_TYPE_VIRTUAL)
--			dc->links[i]->link_enc->funcs->disable_output(
-+		dc->links[i]->link_enc->funcs->disable_output(
- 				dc->links[i]->link_enc, SIGNAL_TYPE_NONE);
- 	}
- }
-@@ -1575,8 +1572,7 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 		stream->audio = NULL;
- 	}
- 
--	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
--		core_link_disable_stream(stream->sink->link, stream);
-+	core_link_disable_stream(stream->sink->link, stream);
- 
- 	stream->tg->funcs->set_blank(stream->tg, true);
- 	stream->tg->funcs->disable_crtc(stream->tg);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 96f4423..fd8a928 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -30,6 +30,7 @@
- #include "resource.h"
- #include "include/irq_service_interface.h"
- #include "include/timing_generator_interface.h"
-+#include "../virtual/virtual_stream_encoder.h"
- 
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
-@@ -304,6 +305,7 @@ void dce110_link_encoder_destroy(struct link_encoder **enc)
- 
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool)
- {
-@@ -459,6 +461,19 @@ bool dce110_construct_resource_pool(
- 		}
- 	}
- 
-+	for (i = 0; i < num_virtual_links; i++) {
-+		pool->stream_enc[pool->stream_enc_count] =
-+			virtual_stream_encoder_create(
-+				dc->ctx, dal_adapter_service_get_bios_parser(
-+								adapter_serv));
-+		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create stream_encoder!\n");
-+			goto stream_enc_create_fail;
-+		}
-+		pool->stream_enc_count++;
-+	}
-+
- 	return true;
- 
- stream_enc_create_fail:
-@@ -726,9 +741,6 @@ static enum dc_status validate_mapped_resource(
- 					stream->tg, &stream->public.timing))
- 				return DC_FAIL_CONTROLLER_VALIDATE;
- 
--			if (stream->signal == SIGNAL_TYPE_VIRTUAL)
--				return status;
--
- 			status = build_stream_hw_param(stream);
- 
- 			if (status != DC_OK)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-index e47b19d..5f00a3c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-@@ -36,6 +36,7 @@ struct dc_validation_set;
- 
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 192399b..f31ee42 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -263,7 +263,7 @@ struct resource_pool {
- 	struct transform *transforms[MAX_PIPES];
- 	struct output_pixel_processor *opps[MAX_PIPES];
- 	struct timing_generator *timing_generators[MAX_STREAMS];
--	struct stream_encoder *stream_enc[MAX_STREAMS];
-+	struct stream_encoder *stream_enc[MAX_PIPES * 2];
- 
- 	uint8_t controller_count;
- 	uint8_t stream_enc_count;
-@@ -294,7 +294,7 @@ struct resource_context {
- 	struct resource_pool pool;
- 	struct controller_ctx controller_ctx[MAX_PIPES];
- 	union supported_stream_engines used_stream_engines;
--	bool is_stream_enc_acquired[MAX_STREAMS];
-+	bool is_stream_enc_acquired[MAX_PIPES * 2];
- 	bool is_audio_acquired[MAX_STREAMS];
- 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
-  };
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 46721cd..0bbf9b5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -106,6 +106,7 @@ struct hw_sequencer_funcs {
- 	/* resource management and validation*/
- 	bool (*construct_resource_pool)(
- 					struct adapter_service *adapter_serv,
-+					uint8_t num_virtual_links,
- 					struct dc *dc,
- 					struct resource_pool *pool);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/Makefile b/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
-new file mode 100644
-index 0000000..0e2cbc0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
-@@ -0,0 +1,9 @@
-+#
-+# Makefile for the virtual sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o
-+
-+AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL))
-+
-+AMD_DAL_FILES += $(AMD_DAL_VIRTUAL)
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-new file mode 100644
-index 0000000..5fa9af8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -0,0 +1,131 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "virtual_link_encoder.h"
-+
-+#define VIRTUAL_MAX_PIXEL_CLK_IN_KHZ 600000
-+
-+static bool virtual_link_encoder_validate_output_with_stream(
-+	struct link_encoder *enc,
-+	struct core_stream *stream) { return true; }
-+
-+static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
-+
-+static void virtual_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal) {}
-+
-+static void virtual_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
-+	uint32_t pixel_clock) {}
-+
-+static void virtual_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source) {}
-+
-+static void virtual_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct link_settings *link_settings,
-+	enum clock_source_id clock_source) {}
-+
-+static void virtual_link_encoder_disable_output(
-+	struct link_encoder *link_enc,
-+	enum signal_type signal) {}
-+
-+static void virtual_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings) {}
-+
-+static void virtual_link_encoder_dp_set_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param) {}
-+
-+static void virtual_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct dp_mst_stream_allocation_table *table) {}
-+
-+static void virtual_link_encoder_set_lcd_backlight_level(
-+	struct link_encoder *enc,
-+	uint32_t level) {}
-+
-+static void virtual_link_encoder_edp_backlight_control(
-+	struct link_encoder *enc,
-+	bool enable) {}
-+
-+static void virtual_link_encoder_edp_power_control(
-+	struct link_encoder *enc,
-+	bool power_up) {}
-+
-+static void virtual_link_encoder_connect_dig_be_to_fe(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	bool connect) {}
-+
-+static struct link_encoder_funcs virtual_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		virtual_link_encoder_validate_output_with_stream,
-+	.hw_init = virtual_link_encoder_hw_init,
-+	.setup = virtual_link_encoder_setup,
-+	.enable_tmds_output = virtual_link_encoder_enable_tmds_output,
-+	.enable_dp_output = virtual_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = virtual_link_encoder_enable_dp_mst_output,
-+	.disable_output = virtual_link_encoder_disable_output,
-+	.dp_set_lane_settings = virtual_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = virtual_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		virtual_link_encoder_update_mst_stream_allocation_table,
-+	.set_lcd_backlight_level = virtual_link_encoder_set_lcd_backlight_level,
-+	.backlight_control = virtual_link_encoder_edp_backlight_control,
-+	.power_control = virtual_link_encoder_edp_power_control,
-+	.connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe
-+};
-+
-+bool virtual_link_encoder_construct(
-+	struct link_encoder *enc, const struct encoder_init_data *init_data)
-+{
-+	enc->funcs = &virtual_lnk_enc_funcs;
-+	enc->ctx = init_data->ctx;
-+	enc->id = init_data->encoder;
-+
-+	enc->hpd_source = init_data->hpd_source;
-+	enc->connector = init_data->connector;
-+
-+	enc->adapter_service = init_data->adapter_service;
-+
-+	enc->transmitter = init_data->transmitter;
-+
-+	enc->features.max_pixel_clock = VIRTUAL_MAX_PIXEL_CLK_IN_KHZ;
-+
-+	enc->output_signals = SIGNAL_TYPE_VIRTUAL;
-+
-+	enc->preferred_engine = ENGINE_ID_VIRTUAL;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-new file mode 100644
-index 0000000..c34bd04
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_VIRTUAL_LINK_ENCODER_H__
-+#define __DC_VIRTUAL_LINK_ENCODER_H__
-+
-+#include "inc/link_encoder.h"
-+
-+bool virtual_link_encoder_construct(
-+	struct link_encoder *enc, const struct encoder_init_data *init_data);
-+
-+
-+#endif /* __DC_VIRTUAL_LINK_ENCODER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-new file mode 100644
-index 0000000..dcfda67
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-@@ -0,0 +1,124 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "virtual_stream_encoder.h"
-+#include "dc_services.h"
-+
-+static void virtual_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing) {}
-+
-+static void virtual_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool enable_audio) {}
-+
-+static void virtual_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link) {}
-+
-+static void virtual_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	struct fixed31_32 avg_time_slots_per_mtp) {}
-+
-+static void virtual_stream_encoder_update_hdmi_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame) {}
-+
-+static void virtual_stream_encoder_stop_hdmi_info_packets(
-+	struct stream_encoder *enc) {}
-+
-+static void virtual_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame) {}
-+
-+static void virtual_stream_encoder_stop_dp_info_packets(
-+	struct stream_encoder *enc) {}
-+
-+static void virtual_stream_encoder_dp_blank(
-+	struct stream_encoder *enc) {}
-+
-+static void virtual_stream_encoder_dp_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param) {}
-+
-+static struct stream_encoder_funcs virtual_str_enc_funcs = {
-+	.dp_set_stream_attribute =
-+		virtual_stream_encoder_dp_set_stream_attribute,
-+	.hdmi_set_stream_attribute =
-+		virtual_stream_encoder_hdmi_set_stream_attribute,
-+	.dvi_set_stream_attribute =
-+		virtual_stream_encoder_dvi_set_stream_attribute,
-+	.set_mst_bandwidth =
-+		virtual_stream_encoder_set_mst_bandwidth,
-+	.update_hdmi_info_packets =
-+		virtual_stream_encoder_update_hdmi_info_packets,
-+	.stop_hdmi_info_packets =
-+		virtual_stream_encoder_stop_hdmi_info_packets,
-+	.update_dp_info_packets =
-+		virtual_stream_encoder_update_dp_info_packets,
-+	.stop_dp_info_packets =
-+		virtual_stream_encoder_stop_dp_info_packets,
-+	.dp_blank =
-+		virtual_stream_encoder_dp_blank,
-+	.dp_unblank =
-+		virtual_stream_encoder_dp_unblank,
-+};
-+
-+bool virtual_stream_encoder_construct(
-+	struct stream_encoder *enc,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp)
-+{
-+	if (!enc)
-+		return false;
-+	if (!bp)
-+		return false;
-+
-+	enc->funcs = &virtual_str_enc_funcs;
-+	enc->ctx = ctx;
-+	enc->id = ENGINE_ID_VIRTUAL;
-+	enc->bp = bp;
-+
-+	return true;
-+}
-+
-+struct stream_encoder *virtual_stream_encoder_create(
-+	struct dc_context *ctx, struct dc_bios *bp)
-+{
-+	struct stream_encoder *enc = dc_service_alloc(ctx, sizeof(*enc));
-+
-+	if (!enc)
-+		return NULL;
-+
-+	if (virtual_stream_encoder_construct(enc, ctx, bp))
-+		return enc;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, enc);
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
-new file mode 100644
-index 0000000..dce8425
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_VIRTUAL_STREAM_ENCODER_H__
-+#define __DC_VIRTUAL_STREAM_ENCODER_H__
-+
-+#include "inc/stream_encoder.h"
-+
-+struct stream_encoder *virtual_stream_encoder_create(
-+	struct dc_context *ctx, struct dc_bios *bp);
-+
-+bool virtual_stream_encoder_construct(
-+	struct stream_encoder *enc,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp);
-+
-+#endif /* __DC_VIRTUAL_STREAM_ENCODER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-index 1eafe7c..2f73797 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -26,6 +26,8 @@
- #ifndef __DAL_GRPH_OBJECT_ID_H__
- #define __DAL_GRPH_OBJECT_ID_H__
- 
-+#include "dal_services_types.h"
-+
- /* Types of graphics objects */
- enum object_type {
- 	OBJECT_TYPE_UNKNOWN  = 0,
-@@ -160,6 +162,7 @@ enum encoder_id {
- 
- 	ENCODER_ID_INTERNAL_WIRELESS,	/* Internal wireless display encoder */
- 	ENCODER_ID_INTERNAL_UNIPHY3,
-+	ENCODER_ID_INTERNAL_VIRTUAL,
- 
- 	ENCODER_ID_EXTERNAL_GENERIC_DVO = 0xFF
- };
-@@ -183,7 +186,7 @@ enum connector_id {
- 	CONNECTOR_ID_WIRELESS = 22,
- 	CONNECTOR_ID_MIRACAST = 23,
- 
--	CONNECTOR_ID_COUNT
-+	CONNECTOR_ID_VIRTUAL = 100
- };
- 
- 
-@@ -207,6 +210,7 @@ enum engine_id {
- 	ENGINE_ID_DACA,
- 	ENGINE_ID_DACB,
- 	ENGINE_ID_VCE,	/* wireless display pseudo-encoder */
-+	ENGINE_ID_VIRTUAL,
- 
- 	ENGINE_ID_COUNT,
- 	ENGINE_ID_UNKNOWN = (-1L)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0716-drm-amd-dal-Remove-the-CZ_BRINGUP-flag.patch b/common/recipes-kernel/linux/files/0716-drm-amd-dal-Remove-the-CZ_BRINGUP-flag.patch
deleted file mode 100644
index 8d12c009..00000000
--- a/common/recipes-kernel/linux/files/0716-drm-amd-dal-Remove-the-CZ_BRINGUP-flag.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From c635964c79b9d7d677a739f095655138296a5583 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 21 Jan 2016 13:42:16 -0500
-Subject: [PATCH 0716/1110] drm/amd/dal: Remove the CZ_BRINGUP flag
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/Makefile                     |  2 +-
- drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c | 12 +-----------
- 2 files changed, 2 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile
-index d5db32e..25ae464 100644
---- a/drivers/gpu/drm/amd/dal/Makefile
-+++ b/drivers/gpu/drm/amd/dal/Makefile
-@@ -7,7 +7,7 @@ AMDDALPATH = $(RELATIVE_AMD_DAL_PATH)
- 
- subdir-ccflags-y += -Werror
- 
--subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include -DDAL_CZ_BRINGUP
-+subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include
- 
- subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 17a9d2c..941d304 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -69,11 +69,7 @@
-  * makes it an int type.
-  */
- 
--static
--#if !defined(DAL_CZ_BRINGUP)
--const
--#endif
--struct feature_source_entry feature_entry_table[] = {
-+static struct feature_source_entry feature_entry_table[] = {
- 	/* Feature name | default value | is boolean type */
- 	{FEATURE_ENABLE_HW_EDID_POLLING, false, true},
- 	{FEATURE_DP_SINK_DETECT_POLL_DATA_PIN, false, true},
-@@ -96,11 +92,7 @@ struct feature_source_entry feature_entry_table[] = {
- 	 * Driver uses SW I2C.
- 	 * Make Test uses HW I2C.
- 	 */
--#if defined(DAL_CZ_BRINGUP)
- 	{FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, true, true},
--#else
--	{FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, false, true},
--#endif
- 	{FEATURE_USE_MAX_DISPLAY_CLK, false, true},
- 	{FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
- 	{FEATURE_SUPPORT_DP_YUV, false, true},
-@@ -740,7 +732,6 @@ static bool adapter_service_construct(
- 		return false;
- 	}
- 
--#if defined(DAL_CZ_BRINGUP)
- 	if (dal_adapter_service_get_dce_version(as) == DCE_VERSION_11_0) {
- 		uint32_t i;
- 
-@@ -753,7 +744,6 @@ static bool adapter_service_construct(
- 				feature_entry_table[i].default_value = true;
- 		}
- 	}
--#endif
- 
- 	/* Generate feature set table */
- 	if (!generate_feature_set(as, init_data->display_param)) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0717-drm-amd-dal-Re-use-link-encoder-programming-between-.patch b/common/recipes-kernel/linux/files/0717-drm-amd-dal-Re-use-link-encoder-programming-between-.patch
deleted file mode 100644
index b80b8d40..00000000
--- a/common/recipes-kernel/linux/files/0717-drm-amd-dal-Re-use-link-encoder-programming-between-.patch
+++ /dev/null
@@ -1,641 +0,0 @@
-From fb35c3c4a17d0afac98439fa768d3cc96cd8c6db Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 21 Jan 2016 11:43:56 -0500
-Subject: [PATCH 0717/1110] drm/amd/dal: Re-use link encoder programming
- between DCEs
-
-Pass register values into link_encoder HW programming code
-so we can reuse it between DCEs.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 144 +++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  43 +++++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  81 +++++++++---
- 3 files changed, 162 insertions(+), 106 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index b4e8467..780c3a6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -35,10 +35,19 @@
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
- 
-+#define LINK_REG(reg)\
-+	(enc110->link_regs->reg)
-+
-+#define AUX_REG(reg)\
-+	(enc110->aux_regs->reg)
-+
-+#define BL_REG(reg)\
-+	(enc110->bl_regs->reg)
-+
- /* For current ASICs pixel clock - 600MHz */
- #define MAX_ENCODER_CLK 600000
- 
--#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 600000	
-+#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 600000
- 
- #define DEFAULT_AUX_MAX_DATA_SIZE 16
- #define AUX_MAX_DEFER_WRITE_RETRY 20
-@@ -73,20 +82,6 @@ enum {
- 	DP_MST_UPDATE_MAX_RETRY = 50
- };
- 
--#ifndef mmDP_DPHY_INTERNAL_CTRL
--	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
--	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
--	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
--	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
--	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
--	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
--	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
--	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
--	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
--	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
--#endif
--
--
- #define DIG_REG(reg)\
- 	(reg + enc110->offsets.dig)
- 
-@@ -133,7 +128,7 @@ static void enable_phy_bypass_mode(
- 	 * transmitter is used for the offset */
- 	struct dc_context *ctx = enc110->base.ctx;
- 
--	const uint32_t addr = DP_REG(mmDP_DPHY_CNTL);
-+	const uint32_t addr = LINK_REG(DP_DPHY_CNTL);
- 
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -150,7 +145,7 @@ static void disable_prbs_symbols(
- 	 * transmitter is used for the offset */
- 	struct dc_context *ctx = enc110->base.ctx;
- 
--	const uint32_t addr = DP_REG(mmDP_DPHY_CNTL);
-+	const uint32_t addr = LINK_REG(DP_DPHY_CNTL);
- 
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -176,7 +171,7 @@ static void disable_prbs_mode(
- 	 * transmitter is used for the offset */
- 	struct dc_context *ctx = enc110->base.ctx;
- 
--	const uint32_t addr = DP_REG(mmDP_DPHY_PRBS_CNTL);
-+	const uint32_t addr = LINK_REG(DP_DPHY_PRBS_CNTL);
- 	uint32_t value;
- 
- 	value = dal_read_reg(ctx, addr);
-@@ -197,7 +192,7 @@ static void program_pattern_symbols(
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
- 
--	addr = DP_REG(mmDP_DPHY_SYM0);
-+	addr = LINK_REG(DP_DPHY_SYM0);
- 
- 	value = 0;
- 	set_reg_field_value(value, pattern_symbols[0],
-@@ -211,7 +206,7 @@ static void program_pattern_symbols(
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
- 
--	addr = DP_REG(mmDP_DPHY_SYM1);
-+	addr = LINK_REG(DP_DPHY_SYM1);
- 
- 	value = 0;
- 	set_reg_field_value(value, pattern_symbols[3],
-@@ -224,7 +219,7 @@ static void program_pattern_symbols(
- 
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
--	addr = DP_REG(mmDP_DPHY_SYM2);
-+	addr = LINK_REG(DP_DPHY_SYM2);
- 	value = 0;
- 	set_reg_field_value(value, pattern_symbols[6],
- 			DP_DPHY_SYM2, DPHY_SYM7);
-@@ -274,7 +269,7 @@ static void set_link_training_complete(
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
- 	struct dc_context *ctx = enc110->base.ctx;
--	const uint32_t addr = DP_REG(mmDP_LINK_CNTL);
-+	const uint32_t addr = LINK_REG(DP_LINK_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, complete,
-@@ -289,7 +284,7 @@ static void set_dp_phy_pattern_training_pattern(
- {
- 	/* Write Training Pattern */
- 	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DP_REG(mmDP_DPHY_TRAINING_PATTERN_SEL);
-+	uint32_t addr = LINK_REG(DP_DPHY_TRAINING_PATTERN_SEL);
- 
- 	dal_write_reg(ctx, addr, index);
- 
-@@ -317,7 +312,7 @@ static void set_dp_phy_pattern_symbol_error(
- 
- 	/* program correct panel mode*/
- 	{
--		const uint32_t addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
-+		const uint32_t addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 		uint32_t value = 0x0;
- 		dal_write_reg(ctx, addr, value);
- 	}
-@@ -330,7 +325,7 @@ static void set_dp_phy_pattern_symbol_error(
- 
- 	/* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
- 	{
--		const uint32_t addr = DP_REG(mmDP_DPHY_PRBS_CNTL);
-+		const uint32_t addr = LINK_REG(DP_DPHY_PRBS_CNTL);
- 		uint32_t value = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(value, 1,
-@@ -361,7 +356,7 @@ static void set_dp_phy_pattern_prbs7(
- 
- 	/* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
- 	{
--		const uint32_t addr = DP_REG(mmDP_DPHY_PRBS_CNTL);
-+		const uint32_t addr = LINK_REG(DP_DPHY_PRBS_CNTL);
- 
- 		uint32_t value = dal_read_reg(ctx, addr);
- 
-@@ -449,7 +444,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 
- 	/* program correct panel mode*/
- 	{
--		const uint32_t addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
-+		const uint32_t addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 		uint32_t value = 0x0;
- 		dal_write_reg(ctx, addr, value);
- 	}
-@@ -486,7 +481,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	/* set link training complete */
- 	set_link_training_complete(enc110, true);
- 	/* do not enable video stream */
--	addr = DP_REG(mmDP_VID_STREAM_CNTL);
-+	addr = LINK_REG(DP_VID_STREAM_CNTL);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -507,7 +502,7 @@ static void set_dp_phy_pattern_passthrough_mode(
- 
- 	/* program correct panel mode */
- 	{
--		const uint32_t addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
-+		const uint32_t addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 
- 		uint32_t value;
- 
-@@ -574,7 +569,7 @@ static void configure_encoder(
- 	uint32_t value;
- 
- 	/* set number of lanes */
--	addr = DP_REG(mmDP_CONFIG);
-+	addr = LINK_REG(DP_CONFIG);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
- 			DP_CONFIG, DP_UDI_LANES);
-@@ -589,7 +584,7 @@ static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
- 	bool ret;
- 
- 	value = dal_read_reg(ctx,
--			mmLVTMA_PWRSEQ_STATE);
-+			BL_REG(LVTMA_PWRSEQ_STATE));
- 
- 	ret = get_reg_field_value(value,
- 			LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R);
-@@ -734,23 +729,20 @@ static void aux_initialize(
- {
- 	struct dc_context *ctx = enc110->base.ctx;
- 	enum hpd_source_id hpd_source = enc110->base.hpd_source;
--	uint32_t addr = mmAUX_CONTROL + enc110->base.aux_channel_offset;
-+	uint32_t addr = AUX_REG(AUX_CONTROL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
- 	set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = mmAUX_DPHY_RX_CONTROL0 + enc110->base.aux_channel_offset;
-+	addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
- 	value = dal_read_reg(ctx, addr);
- 
- 	/* 1/4 window (the maximum allowed) */
- 	set_reg_field_value(value, 1,
- 			AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
--	dal_write_reg(ctx,
--			mmAUX_DPHY_RX_CONTROL0 +
--			enc110->base.aux_channel_offset,
--			value);
-+	dal_write_reg(ctx, addr, value);
- 
- }
- 
-@@ -760,7 +752,7 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 
--	value = dal_read_reg(ctx, mmLVTMA_PWRSEQ_CNTL);
-+	value = dal_read_reg(ctx, BL_REG(LVTMA_PWRSEQ_CNTL));
- 
- 	return get_reg_field_value(value, LVTMA_PWRSEQ_CNTL, LVTMA_BLON);
- }
-@@ -839,7 +831,7 @@ static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 
--	value = dal_read_reg(ctx, DIG_REG(mmDIG_BE_EN_CNTL));
-+	value = dal_read_reg(ctx, LINK_REG(DIG_BE_EN_CNTL));
- 
- 	return get_reg_field_value(value, DIG_BE_EN_CNTL, DIG_ENABLE);
- }
-@@ -851,7 +843,7 @@ static void link_encoder_disable(struct dce110_link_encoder *enc110)
- 	uint32_t value;
- 
- 	/* reset training pattern */
--	addr = DP_REG(mmDP_DPHY_TRAINING_PATTERN_SEL);
-+	addr = LINK_REG(DP_DPHY_TRAINING_PATTERN_SEL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0,
- 			DP_DPHY_TRAINING_PATTERN_SEL,
-@@ -859,13 +851,13 @@ static void link_encoder_disable(struct dce110_link_encoder *enc110)
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* reset training complete */
--	addr = DP_REG(mmDP_LINK_CNTL);
-+	addr = LINK_REG(DP_LINK_CNTL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE);
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* reset panel mode */
--	addr = DP_REG(mmDP_DPHY_INTERNAL_CTRL);
-+	addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 	value = 0;
- 	dal_write_reg(ctx, addr, value);
- }
-@@ -876,7 +868,7 @@ static void hpd_initialize(
- 	/* Associate HPD with DIG_BE */
- 	struct dc_context *ctx = enc110->base.ctx;
- 	enum hpd_source_id hpd_source = enc110->base.hpd_source;
--	const uint32_t addr = DIG_REG(mmDIG_BE_CNTL);
-+	const uint32_t addr = LINK_REG(DIG_BE_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, DIG_BE_CNTL, DIG_HPD_SELECT);
-@@ -1060,7 +1052,9 @@ static bool validate_wireless_output(
- bool dce110_link_encoder_construct(
- 	struct dce110_link_encoder *enc110,
- 	const struct encoder_init_data *init_data,
--	const struct dce110_link_enc_offsets *offsets)
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs)
- {
- 	struct graphics_object_encoder_cap_info enc_cap_info = {0};
- 
-@@ -1114,7 +1108,9 @@ bool dce110_link_encoder_construct(
- 	 * This will let DCE 8.1 share DCE 8.0 as much as possible
- 	 */
- 
--	enc110->offsets = *offsets;
-+	enc110->link_regs = link_regs;
-+	enc110->aux_regs = aux_regs;
-+	enc110->bl_regs = bl_regs;
- 
- 	switch (enc110->base.transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -1147,28 +1143,6 @@ bool dce110_link_encoder_construct(
- 			DECODE_CHANNEL_ID(init_data->channel),
- 			init_data->channel);
- 
--	switch (init_data->channel) {
--	case CHANNEL_ID_DDC1:
--		enc110->base.aux_channel_offset = 0;
--		break;
--	case CHANNEL_ID_DDC2:
--		enc110->base.aux_channel_offset =
--			mmDP_AUX1_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
--		break;
--	case CHANNEL_ID_DDC3:
--		enc110->base.aux_channel_offset =
--			mmDP_AUX2_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL;
--		break;
--	default:
--		/* check BIOS object table ! */
--		dal_logger_write(init_data->ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_ENCODER,
--				"%s: Invalid channel ID\n",
--				__func__);
--		enc110->base.aux_channel_offset = 0;
--	}
--
- 	/* Override features with DCE-specific values */
- 	if (dal_adapter_service_get_encoder_cap_info(
- 			enc110->base.adapter_service,
-@@ -1290,7 +1264,7 @@ void dce110_link_encoder_setup(
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	const uint32_t addr = DIG_REG(mmDIG_BE_CNTL);
-+	const uint32_t addr = LINK_REG(DIG_BE_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	switch (signal) {
-@@ -1392,7 +1366,7 @@ void dce110_link_encoder_enable_dp_output(
- 	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = ENGINE_ID_UNKNOWN;
-+	cntl.engine_id = enc->preferred_engine;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
-@@ -1435,7 +1409,7 @@ void dce110_link_encoder_enable_dp_mst_output(
- 	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = ENGINE_ID_UNKNOWN;
-+	cntl.engine_id = enc->preferred_engine;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-@@ -1657,8 +1631,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * to commit payload on both tx and rx side */
- 
- 	/* we should clean-up table each time */
--	value0 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT0));
--	value1 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT1));
-+	value0 = dal_read_reg(ctx, LINK_REG(DP_MSE_SAT0));
-+	value1 = dal_read_reg(ctx, LINK_REG(DP_MSE_SAT1));
- 
- 	if (table->stream_count >= 1) {
- 		fill_stream_allocation_row_info(
-@@ -1727,8 +1701,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_SLOT_COUNT2);
- 
- 	/* update ASIC MSE stream allocation table */
--	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT0), value0);
--	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT1), value1);
-+	dal_write_reg(ctx, LINK_REG(DP_MSE_SAT0), value0);
-+	dal_write_reg(ctx, LINK_REG(DP_MSE_SAT1), value1);
- 
- 	/* --- wait for transaction finish */
- 
-@@ -1737,7 +1711,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * then double buffers the SAT into the hardware
- 	 * making the new allocation active on the DP MST mode link */
- 
--	value0 = dal_read_reg(ctx, DP_REG(mmDP_MSE_SAT_UPDATE));
-+	value0 = dal_read_reg(ctx, LINK_REG(DP_MSE_SAT_UPDATE));
- 
- 	/* DP_MSE_SAT_UPDATE:
- 	 * 0 - No Action
-@@ -1750,7 +1724,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_UPDATE,
- 		DP_MSE_SAT_UPDATE);
- 
--	dal_write_reg(ctx, DP_REG(mmDP_MSE_SAT_UPDATE), value0);
-+	dal_write_reg(ctx, LINK_REG(DP_MSE_SAT_UPDATE), value0);
- 
- 	/* wait for update to complete
- 	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
-@@ -1766,7 +1740,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		dc_service_delay_in_microseconds(ctx, 10);
- 
- 		value0 = dal_read_reg(ctx,
--				DP_REG(mmDP_MSE_SAT_UPDATE));
-+				LINK_REG(DP_MSE_SAT_UPDATE));
- 
- 		value1 = get_reg_field_value(
- 				value0,
-@@ -1807,9 +1781,9 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	uint8_t bit_count;
- 	uint64_t active_duty_cycle;
- 
--	backlight = dal_read_reg(ctx, mmBL_PWM_CNTL);
--	backlight_period = dal_read_reg(ctx, mmBL_PWM_PERIOD_CNTL);
--	backlight_lock = dal_read_reg(ctx, mmBL_PWM_GRP1_REG_LOCK);
-+	backlight = dal_read_reg(ctx, BL_REG(BL_PWM_CNTL));
-+	backlight_period = dal_read_reg(ctx, BL_REG(BL_PWM_PERIOD_CNTL));
-+	backlight_lock = dal_read_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK));
- 
- 	/*
- 	 * 1. Convert 8-bit value to 17 bit U1.16 format
-@@ -1892,10 +1866,10 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 		1,
- 		BL_PWM_GRP1_REG_LOCK,
- 		BL_PWM_GRP1_REG_LOCK);
--	dal_write_reg(ctx, mmBL_PWM_GRP1_REG_LOCK, backlight_lock);
-+	dal_write_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK), backlight_lock);
- 
- 	/* 3.2 Write new active duty cycle */
--	dal_write_reg(ctx, mmBL_PWM_CNTL, backlight);
-+	dal_write_reg(ctx, BL_REG(BL_PWM_CNTL), backlight);
- 
- 	/* 3.3 Unlock group 2 backlight registers */
- 	set_reg_field_value(
-@@ -1903,11 +1877,11 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 		0,
- 		BL_PWM_GRP1_REG_LOCK,
- 		BL_PWM_GRP1_REG_LOCK);
--	dal_write_reg(ctx, mmBL_PWM_GRP1_REG_LOCK, backlight_lock);
-+	dal_write_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK), backlight_lock);
- 
- 	/* 5.4.4 Wait for pending bit to be cleared */
- 	for (i = 0; i < backlight_update_pending_max_retry; ++i) {
--		backlight_lock = dal_read_reg(ctx, mmBL_PWM_GRP1_REG_LOCK);
-+		backlight_lock = dal_read_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK));
- 		if (!get_reg_field_value(
- 			backlight_lock,
- 			BL_PWM_GRP1_REG_LOCK,
-@@ -1930,7 +1904,7 @@ void dce110_link_encoder_connect_dig_be_to_fe(
- 	uint32_t field;
- 
- 	if (engine != ENGINE_ID_UNKNOWN) {
--		addr = DIG_REG(mmDIG_BE_CNTL);
-+		addr = LINK_REG(DIG_BE_CNTL);
- 		value = dal_read_reg(ctx, addr);
- 
- 		field = get_reg_field_value(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index df6e265..31a33a8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -31,20 +31,53 @@
- #define TO_DCE110_LINK_ENC(link_encoder)\
- 	container_of(link_encoder, struct dce110_link_encoder, base)
- 
--struct dce110_link_enc_offsets {
--	int32_t dig;
--	int32_t dp;
-+struct dce110_link_enc_bl_registers {
-+	uint32_t BL_PWM_CNTL;
-+	uint32_t BL_PWM_GRP1_REG_LOCK;
-+	uint32_t BL_PWM_PERIOD_CNTL;
-+	uint32_t LVTMA_PWRSEQ_CNTL;
-+	uint32_t LVTMA_PWRSEQ_STATE;
-+};
-+
-+struct dce110_link_enc_aux_registers {
-+	uint32_t AUX_CONTROL;
-+	uint32_t AUX_DPHY_RX_CONTROL0;
-+};
-+
-+struct dce110_link_enc_registers {
-+	uint32_t DIG_BE_CNTL;
-+	uint32_t DIG_BE_EN_CNTL;
-+	uint32_t DP_CONFIG;
-+	uint32_t DP_DPHY_CNTL;
-+	uint32_t DP_DPHY_INTERNAL_CTRL;
-+	uint32_t DP_DPHY_PRBS_CNTL;
-+	uint32_t DP_DPHY_SYM0;
-+	uint32_t DP_DPHY_SYM1;
-+	uint32_t DP_DPHY_SYM2;
-+	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
-+	uint32_t DP_LINK_CNTL;
-+	uint32_t DP_LINK_FRAMING_CNTL;
-+	uint32_t DP_MSE_SAT0;
-+	uint32_t DP_MSE_SAT1;
-+	uint32_t DP_MSE_SAT2;
-+	uint32_t DP_MSE_SAT_UPDATE;
-+	uint32_t DP_SEC_CNTL;
-+	uint32_t DP_VID_STREAM_CNTL;
- };
- 
- struct dce110_link_encoder {
- 	struct link_encoder base;
--	struct dce110_link_enc_offsets offsets;
-+	const struct dce110_link_enc_registers *link_regs;
-+	const struct dce110_link_enc_aux_registers *aux_regs;
-+	const struct dce110_link_enc_bl_registers *bl_regs;
- };
- 
- bool dce110_link_encoder_construct(
- 	struct dce110_link_encoder *enc110,
- 	const struct encoder_init_data *init_data,
--	const struct dce110_link_enc_offsets *offsets);
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs);
- 
- bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index fd8a928..adc1668 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -42,6 +42,20 @@
- 
- #include "dce/dce_11_0_d.h"
- 
-+/* TODO remove these defines */
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
- enum dce110_clk_src_array_id {
- 	DCE110_CLK_SRC_PLL0 = 0,
- 	DCE110_CLK_SRC_PLL1,
-@@ -92,21 +106,6 @@ static const struct dce110_stream_enc_offsets dce110_str_enc_offsets[] = {
- 	}
- };
- 
--static const struct dce110_link_enc_offsets dce110_lnk_enc_reg_offsets[] = {
--	{
--		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	}
--};
--
- static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
- 	{
- 		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-@@ -171,6 +170,54 @@ static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
- }
- };
- 
-+static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
-+		.BL_PWM_CNTL = mmBL_PWM_CNTL,
-+		.BL_PWM_GRP1_REG_LOCK = mmBL_PWM_GRP1_REG_LOCK,
-+		.BL_PWM_PERIOD_CNTL = mmBL_PWM_PERIOD_CNTL,
-+		.LVTMA_PWRSEQ_CNTL = mmLVTMA_PWRSEQ_CNTL,
-+		.LVTMA_PWRSEQ_STATE = mmLVTMA_PWRSEQ_STATE
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	.AUX_CONTROL = mmDP_AUX ## id ## _AUX_CONTROL,\
-+	.AUX_DPHY_RX_CONTROL0 = mmDP_AUX ## id ## _AUX_DPHY_RX_CONTROL0\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+	aux_regs(0),
-+	aux_regs(1),
-+	aux_regs(2)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	.DIG_BE_CNTL = mmDIG ## id ## _DIG_BE_CNTL,\
-+	.DIG_BE_EN_CNTL = mmDIG ## id ## _DIG_BE_EN_CNTL,\
-+	.DP_CONFIG = mmDP ## id ## _DP_CONFIG,\
-+	.DP_DPHY_CNTL = mmDP ## id ## _DP_DPHY_CNTL,\
-+	.DP_DPHY_INTERNAL_CTRL = mmDP ## id ## _DP_DPHY_INTERNAL_CTRL,\
-+	.DP_DPHY_PRBS_CNTL = mmDP ## id ## _DP_DPHY_PRBS_CNTL,\
-+	.DP_DPHY_SYM0 = mmDP ## id ## _DP_DPHY_SYM0,\
-+	.DP_DPHY_SYM1 = mmDP ## id ## _DP_DPHY_SYM1,\
-+	.DP_DPHY_SYM2 = mmDP ## id ## _DP_DPHY_SYM2,\
-+	.DP_DPHY_TRAINING_PATTERN_SEL = mmDP ## id ## _DP_DPHY_TRAINING_PATTERN_SEL,\
-+	.DP_LINK_CNTL = mmDP ## id ## _DP_LINK_CNTL,\
-+	.DP_LINK_FRAMING_CNTL = mmDP ## id ## _DP_LINK_FRAMING_CNTL,\
-+	.DP_MSE_SAT0 = mmDP ## id ## _DP_MSE_SAT0,\
-+	.DP_MSE_SAT1 = mmDP ## id ## _DP_MSE_SAT1,\
-+	.DP_MSE_SAT2 = mmDP ## id ## _DP_MSE_SAT2,\
-+	.DP_MSE_SAT_UPDATE = mmDP ## id ## _DP_MSE_SAT_UPDATE,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2)
-+};
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -289,7 +336,9 @@ struct link_encoder *dce110_link_encoder_create(
- 	if (dce110_link_encoder_construct(
- 			enc110,
- 			enc_init_data,
--			&dce110_lnk_enc_reg_offsets[enc_init_data->transmitter]))
-+			&link_enc_regs[enc_init_data->transmitter],
-+			&link_enc_aux_regs[enc_init_data->channel - 1],
-+			&link_enc_bl_regs))
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0718-drm-amd-dal-Re-use-stream-encoder-programming-betwee.patch b/common/recipes-kernel/linux/files/0718-drm-amd-dal-Re-use-stream-encoder-programming-betwee.patch
deleted file mode 100644
index 8dbebf04..00000000
--- a/common/recipes-kernel/linux/files/0718-drm-amd-dal-Re-use-stream-encoder-programming-betwee.patch
+++ /dev/null
@@ -1,548 +0,0 @@
-From f73ae7e29da9a00a3131c7e5a759a2a9e1adfae5 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 21 Jan 2016 16:38:09 -0500
-Subject: [PATCH 0718/1110] drm/amd/dal: Re-use stream encoder programming
- between DCEs
-
-Pass register values into stream_encoder HW programming code
-so we can reuse it between DCEs.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 58 +++++++++-----
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 89 +++++++++++-----------
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  | 36 +++++++--
- 3 files changed, 113 insertions(+), 70 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index adc1668..823926c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -91,21 +91,6 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
- 	}
- };
- 
--static const struct dce110_stream_enc_offsets dce110_str_enc_offsets[] = {
--	{
--		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	}
--};
--
- static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = {
- 	{
- 		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-@@ -218,6 +203,43 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
- 	link_regs(2)
- };
- 
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	.AFMT_AVI_INFO0 = mmDIG ## id ## _AFMT_AVI_INFO0,\
-+	.AFMT_AVI_INFO1 = mmDIG ## id ## _AFMT_AVI_INFO1,\
-+	.AFMT_AVI_INFO2 = mmDIG ## id ## _AFMT_AVI_INFO2,\
-+	.AFMT_AVI_INFO3 = mmDIG ## id ## _AFMT_AVI_INFO3,\
-+	.AFMT_GENERIC_0 = mmDIG ## id ## _AFMT_GENERIC_0,\
-+	.AFMT_GENERIC_7 = mmDIG ## id ## _AFMT_GENERIC_7,\
-+	.AFMT_GENERIC_HDR = mmDIG ## id ## _AFMT_GENERIC_HDR,\
-+	.AFMT_INFOFRAME_CONTROL0 = mmDIG ## id ## _AFMT_INFOFRAME_CONTROL0,\
-+	.AFMT_VBI_PACKET_CONTROL = mmDIG ## id ## _AFMT_VBI_PACKET_CONTROL,\
-+	.DIG_FE_CNTL = mmDIG ## id ## _DIG_FE_CNTL,\
-+	.DP_MSE_RATE_CNTL = mmDP ## id ## _DP_MSE_RATE_CNTL,\
-+	.DP_MSE_RATE_UPDATE = mmDP ## id ## _DP_MSE_RATE_UPDATE,\
-+	.DP_PIXEL_FORMAT = mmDP ## id ## _DP_PIXEL_FORMAT,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_STEER_FIFO = mmDP ## id ## _DP_STEER_FIFO,\
-+	.DP_VID_M = mmDP ## id ## _DP_VID_M,\
-+	.DP_VID_N = mmDP ## id ## _DP_VID_N,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL,\
-+	.DP_VID_TIMING = mmDP ## id ## _DP_VID_TIMING,\
-+	.HDMI_CONTROL = mmDIG ## id ## _HDMI_CONTROL,\
-+	.HDMI_GC = mmDIG ## id ## _HDMI_GC,\
-+	.HDMI_GENERIC_PACKET_CONTROL0 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL0,\
-+	.HDMI_GENERIC_PACKET_CONTROL1 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL1,\
-+	.HDMI_INFOFRAME_CONTROL0 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL0,\
-+	.HDMI_INFOFRAME_CONTROL1 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL1,\
-+	.HDMI_VBI_PACKET_CONTROL = mmDIG ## id ## _HDMI_VBI_PACKET_CONTROL,\
-+	.TMDS_CNTL = mmDIG ## id ## _TMDS_CNTL\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2)
-+};
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -242,7 +264,7 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 	enum engine_id eng_id,
- 	struct dc_context *ctx,
- 	struct dc_bios *bp,
--	const struct dce110_stream_enc_offsets *offsets)
-+	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
- 		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
-@@ -250,7 +272,7 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 	if (!enc110)
- 		return NULL;
- 
--	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, offsets))
-+	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, regs))
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
-@@ -501,7 +523,7 @@ bool dce110_construct_resource_pool(
- 				i, dc->ctx,
- 				dal_adapter_service_get_bios_parser(
- 					adapter_serv),
--				&dce110_str_enc_offsets[i]);
-+				&stream_enc_regs[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
- 				dal_error("DC: failed to create stream_encoder!\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 87f59ee..5b432d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -30,11 +30,8 @@
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
- 
--#define DIG_REG(reg)\
--	(reg + enc110->offsets.dig)
--
--#define DP_REG(reg)\
--	(reg + enc110->offsets.dig)
-+#define LINK_REG(reg)\
-+	(enc110->regs->reg)
- 
- #define VBI_LINE_0 0
- #define DP_BLANK_MAX_RETRY 20
-@@ -82,7 +79,7 @@ static void dce110_update_generic_info_packet(
- 	uint32_t regval;
- 	/* choose which generic packet to use */
- 	{
--		addr = DIG_REG(mmAFMT_VBI_PACKET_CONTROL);
-+		addr = LINK_REG(AFMT_VBI_PACKET_CONTROL);
- 
- 		regval = dal_read_reg(ctx, addr);
- 
-@@ -98,7 +95,7 @@ static void dce110_update_generic_info_packet(
- 	/* write generic packet header
- 	 * (4th byte is for GENERIC0 only) */
- 	{
--		addr = DIG_REG(mmAFMT_GENERIC_HDR);
-+		addr = LINK_REG(AFMT_GENERIC_HDR);
- 
- 		regval = 0;
- 
-@@ -138,7 +135,7 @@ static void dce110_update_generic_info_packet(
- 
- 		uint32_t counter = 0;
- 
--		addr = DIG_REG(mmAFMT_GENERIC_0);
-+		addr = LINK_REG(AFMT_GENERIC_0);
- 
- 		do {
- 			dal_write_reg(ctx, addr++, *content++);
-@@ -147,7 +144,7 @@ static void dce110_update_generic_info_packet(
- 		} while (counter < 7);
- 	}
- 
--	addr = DIG_REG(mmAFMT_GENERIC_7);
-+	addr = LINK_REG(AFMT_GENERIC_7);
- 
- 	dal_write_reg(
- 		ctx,
-@@ -156,7 +153,7 @@ static void dce110_update_generic_info_packet(
- 
- 	/* force double-buffered packet update */
- 	{
--		addr = DIG_REG(mmAFMT_VBI_PACKET_CONTROL);
-+		addr = LINK_REG(AFMT_VBI_PACKET_CONTROL);
- 
- 		regval = dal_read_reg(ctx, addr);
- 
-@@ -210,11 +207,11 @@ static void dce110_update_hdmi_info_packet(
- 	switch (packet_index) {
- 	case 0:
- 	case 1:
--		addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL0);
-+		addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL0);
- 		break;
- 	case 2:
- 	case 3:
--		addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL1);
-+		addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL1);
- 		break;
- 	default:
- 		/* invalid HW packet index */
-@@ -285,7 +282,7 @@ bool dce110_stream_encoder_construct(
- 	struct dc_context *ctx,
- 	struct dc_bios *bp,
- 	enum engine_id eng_id,
--	const struct dce110_stream_enc_offsets *offsets)
-+	const struct dce110_stream_enc_registers *regs)
- {
- 	if (!enc110)
- 		return false;
-@@ -296,7 +293,7 @@ bool dce110_stream_encoder_construct(
- 	enc110->base.ctx = ctx;
- 	enc110->base.id = eng_id;
- 	enc110->base.bp = bp;
--	enc110->offsets = *offsets;
-+	enc110->regs = regs;
- 
- 	return true;
- }
-@@ -308,7 +305,7 @@ void dce110_stream_encoder_dp_set_stream_attribute(
- {
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	const uint32_t addr = DP_REG(mmDP_PIXEL_FORMAT);
-+	const uint32_t addr = LINK_REG(DP_PIXEL_FORMAT);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	/* set pixel encoding */
-@@ -416,7 +413,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 			enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
--	addr = DIG_REG(mmDIG_FE_CNTL);
-+	addr = LINK_REG(DIG_FE_CNTL);
- 	value = dal_read_reg(ctx, addr);
- 
- 	switch (crtc_timing->pixel_encoding) {
-@@ -431,7 +428,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* setup HDMI engine */
--	addr = DIG_REG(mmHDMI_CONTROL);
-+	addr = LINK_REG(HDMI_CONTROL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_PACKET_GEN_VERSION);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_KEEPOUT_MODE);
-@@ -528,7 +525,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = DIG_REG(mmHDMI_VBI_PACKET_CONTROL);
-+	addr = LINK_REG(HDMI_VBI_PACKET_CONTROL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND);
-@@ -537,7 +534,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* following belongs to audio */
--	addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+	addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
-@@ -546,7 +543,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 		HDMI_AUDIO_INFO_SEND);
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = DIG_REG(mmAFMT_INFOFRAME_CONTROL0);
-+	addr = LINK_REG(AFMT_INFOFRAME_CONTROL0);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
-@@ -555,7 +552,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 		AFMT_AUDIO_INFO_UPDATE);
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL1);
-+	addr = LINK_REG(HDMI_INFOFRAME_CONTROL1);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
-@@ -564,7 +561,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 		HDMI_AUDIO_INFO_LINE);
- 	dal_write_reg(ctx, addr, value);
- 
--	addr = DIG_REG(mmHDMI_GC);
-+	addr = LINK_REG(HDMI_GC);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, HDMI_GC, HDMI_GC_AVMUTE);
- 	dal_write_reg(ctx, addr, value);
-@@ -578,7 +575,7 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- {
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DIG_REG(mmDIG_FE_CNTL);
-+	uint32_t addr = LINK_REG(DIG_FE_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 	struct bp_encoder_control cntl = {0};
- 
-@@ -648,7 +645,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 			26));
- 
- 	{
--		addr = DP_REG(mmDP_MSE_RATE_CNTL);
-+		addr = LINK_REG(DP_MSE_RATE_CNTL);
- 		value = dal_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
-@@ -670,7 +667,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
- 	/* is reset to 0 (not pending) */
- 	{
--		addr = DP_REG(mmDP_MSE_RATE_UPDATE);
-+		addr = LINK_REG(DP_MSE_RATE_UPDATE);
- 
- 		do {
- 			value = dal_read_reg(ctx, addr);
-@@ -706,7 +703,7 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 		const uint32_t *content =
- 			(const uint32_t *) &info_frame->avi.sb[0];
- 
--		addr = DIG_REG(mmAFMT_AVI_INFO0);
-+		addr = LINK_REG(AFMT_AVI_INFO0);
- 		regval = content[0];
- 		dal_write_reg(
- 			ctx,
-@@ -714,14 +711,14 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 			regval);
- 		regval = content[1];
- 
--		addr = DIG_REG(mmAFMT_AVI_INFO1);
-+		addr = LINK_REG(AFMT_AVI_INFO1);
- 		dal_write_reg(
- 			ctx,
- 			addr,
- 			regval);
- 		regval = content[2];
- 
--		addr = DIG_REG(mmAFMT_AVI_INFO2);
-+		addr = LINK_REG(AFMT_AVI_INFO2);
- 		dal_write_reg(
- 			ctx,
- 			addr,
-@@ -729,7 +726,7 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 		regval = content[3];
- 
- 		/* move version to AVI_INFO3 */
--		addr = DIG_REG(mmAFMT_AVI_INFO3);
-+		addr = LINK_REG(AFMT_AVI_INFO3);
- 		set_reg_field_value(
- 			regval,
- 			info_frame->avi.hb1,
-@@ -741,7 +738,7 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 			addr,
- 			regval);
- 
--		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+		addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 
- 		control0val = dal_read_reg(ctx, addr);
- 
-@@ -759,7 +756,7 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 
- 		dal_write_reg(ctx, addr, control0val);
- 
--		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL1);
-+		addr = LINK_REG(HDMI_INFOFRAME_CONTROL1);
- 
- 		control1val = dal_read_reg(ctx, addr);
- 
-@@ -771,7 +768,7 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 
- 		dal_write_reg(ctx, addr, control1val);
- 	} else {
--		addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+		addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 
- 		regval = dal_read_reg(ctx, addr);
- 
-@@ -804,7 +801,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 	uint32_t value = 0;
- 
- 	/* stop generic packets 0 & 1 on HDMI */
--	addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL0);
-+	addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL0);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -842,7 +839,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* stop generic packets 2 & 3 on HDMI */
--	addr = DIG_REG(mmHDMI_GENERIC_PACKET_CONTROL1);
-+	addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL1);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -880,7 +877,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* stop AVI packet on HDMI */
--	addr = DIG_REG(mmHDMI_INFOFRAME_CONTROL0);
-+	addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 
- 	value = dal_read_reg(ctx, addr);
- 
-@@ -903,7 +900,7 @@ void dce110_stream_encoder_update_dp_info_packets(
- {
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
-+	uint32_t addr = LINK_REG(DP_SEC_CNTL);
- 	uint32_t value;
- 
- 	if (info_frame->vsc.valid)
-@@ -946,7 +943,7 @@ void dce110_stream_encoder_stop_dp_info_packets(
- 	/* stop generic packets on DP */
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DP_REG(mmDP_SEC_CNTL);
-+	uint32_t addr = LINK_REG(DP_SEC_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
-@@ -976,7 +973,7 @@ void dce110_stream_encoder_dp_blank(
- {
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
--	uint32_t addr = DP_REG(mmDP_VID_STREAM_CNTL);
-+	uint32_t addr = LINK_REG(DP_VID_STREAM_CNTL);
- 	uint32_t value = dal_read_reg(ctx, addr);
- 	uint32_t retries = 0;
- 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
-@@ -1031,7 +1028,7 @@ void dce110_stream_encoder_dp_blank(
- 	* complete, stream status will be stuck in video stream enabled state,
- 	* i.e. DP_VID_STREAM_STATUS stuck at 1.
- 	*/
--	addr = DP_REG(mmDP_STEER_FIFO);
-+	addr = LINK_REG(DP_STEER_FIFO);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, true, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
- 	dal_write_reg(ctx, addr, value);
-@@ -1065,7 +1062,7 @@ void dce110_stream_encoder_dp_unblank(
- 		m_vid = (uint32_t) m_vid_l;
- 
- 		/* enable auto measurement */
--		addr = DP_REG(mmDP_VID_TIMING);
-+		addr = LINK_REG(DP_VID_TIMING);
- 		value = dal_read_reg(ctx, addr);
- 		set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
- 		dal_write_reg(ctx, addr, value);
-@@ -1073,30 +1070,30 @@ void dce110_stream_encoder_dp_unblank(
- 		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
- 		* therefore program initial value for Mvid and Nvid
- 		*/
--		addr = DP_REG(mmDP_VID_N);
-+		addr = LINK_REG(DP_VID_N);
- 		value = dal_read_reg(ctx, addr);
- 		set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
- 		dal_write_reg(ctx, addr, value);
- 
--		addr = DP_REG(mmDP_VID_M);
-+		addr = LINK_REG(DP_VID_M);
- 		value = dal_read_reg(ctx, addr);
- 		set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
- 		dal_write_reg(ctx, addr, value);
- 
--		addr = DP_REG(mmDP_VID_TIMING);
-+		addr = LINK_REG(DP_VID_TIMING);
- 		value = dal_read_reg(ctx, addr);
- 		set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
- 		dal_write_reg(ctx, addr, value);
- 	}
- 
- 	/* set DIG_START to 0x1 to resync FIFO */
--	addr = DIG_REG(mmDIG_FE_CNTL);
-+	addr = LINK_REG(DIG_FE_CNTL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
- 	dal_write_reg(ctx, addr, value);
- 
- 	/* switch DP encoder to CRTC data */
--	addr = DP_REG(mmDP_STEER_FIFO);
-+	addr = LINK_REG(DP_STEER_FIFO);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
- 	dal_write_reg(ctx, addr, value);
-@@ -1113,7 +1110,7 @@ void dce110_stream_encoder_dp_unblank(
- 	* VID_STREAM enable at start of next frame, and this is not
- 	* programmable
- 	*/
--	addr = DP_REG(mmDP_VID_STREAM_CNTL);
-+	addr = LINK_REG(DP_VID_STREAM_CNTL);
- 	value = dal_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 7e110b4..5753a1b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -31,15 +31,39 @@
- #define DCE110STRENC_FROM_STRENC(stream_encoder)\
- 	container_of(stream_encoder, struct dce110_stream_encoder, base)
- 
--struct dce110_stream_enc_offsets {
--	int32_t dig;
--	int32_t dp;
-+struct dce110_stream_enc_registers {
-+	uint32_t AFMT_AVI_INFO0;
-+	uint32_t AFMT_AVI_INFO1;
-+	uint32_t AFMT_AVI_INFO2;
-+	uint32_t AFMT_AVI_INFO3;
-+	uint32_t AFMT_GENERIC_0;
-+	uint32_t AFMT_GENERIC_7;
-+	uint32_t AFMT_GENERIC_HDR;
-+	uint32_t AFMT_INFOFRAME_CONTROL0;
-+	uint32_t AFMT_VBI_PACKET_CONTROL;
-+	uint32_t DIG_FE_CNTL;
-+	uint32_t DP_MSE_RATE_CNTL;
-+	uint32_t DP_MSE_RATE_UPDATE;
-+	uint32_t DP_PIXEL_FORMAT;
-+	uint32_t DP_SEC_CNTL;
-+	uint32_t DP_STEER_FIFO;
-+	uint32_t DP_VID_M;
-+	uint32_t DP_VID_N;
-+	uint32_t DP_VID_STREAM_CNTL;
-+	uint32_t DP_VID_TIMING;
-+	uint32_t HDMI_CONTROL;
-+	uint32_t HDMI_GC;
-+	uint32_t HDMI_GENERIC_PACKET_CONTROL0;
-+	uint32_t HDMI_GENERIC_PACKET_CONTROL1;
-+	uint32_t HDMI_INFOFRAME_CONTROL0;
-+	uint32_t HDMI_INFOFRAME_CONTROL1;
-+	uint32_t HDMI_VBI_PACKET_CONTROL;
-+	uint32_t TMDS_CNTL;
- };
- 
- struct dce110_stream_encoder {
- 	struct stream_encoder base;
--	struct dce110_stream_enc_offsets offsets;
--	struct dce110_stream_enc_offsets derived_offsets;
-+	const struct dce110_stream_enc_registers *regs;
- };
- 
- bool dce110_stream_encoder_construct(
-@@ -47,7 +71,7 @@ bool dce110_stream_encoder_construct(
- 	struct dc_context *ctx,
- 	struct dc_bios *bp,
- 	enum engine_id eng_id,
--	const struct dce110_stream_enc_offsets *offsets);
-+	const struct dce110_stream_enc_registers *regs);
- 
- /***** HW programming ***********/
- /* setup stream encoder in dp mode */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0719-drm-amd-dal-update-core-link-mst-stream-allocation-t.patch b/common/recipes-kernel/linux/files/0719-drm-amd-dal-update-core-link-mst-stream-allocation-t.patch
deleted file mode 100644
index 841aadb1..00000000
--- a/common/recipes-kernel/linux/files/0719-drm-amd-dal-update-core-link-mst-stream-allocation-t.patch
+++ /dev/null
@@ -1,499 +0,0 @@
-From c02f297bf62cbfe4cda8955332780e5ebb0c3e90 Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Mon, 11 Jan 2016 16:53:07 -0500
-Subject: [PATCH 0719/1110] drm/amd/dal: update core link mst stream allocation
- table with stream encoder
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  |  43 +-------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 122 +++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |   1 -
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   5 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |  12 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  26 ++++-
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |   2 +-
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.c  |   2 +-
- .../gpu/drm/amd/dal/include/link_service_types.h   |   8 +-
- 11 files changed, 113 insertions(+), 112 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-index 855f9f9..ab426e3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-@@ -160,27 +160,8 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
--const struct dp_mst_stream_allocation *find_stream_with_matching_vcpi(
--	const struct dp_mst_stream_allocation_table *table,
--	uint32_t vcpi)
--{
--	int i;
--
--	for (i = 0; i < table->stream_count; i++) {
--		const struct dp_mst_stream_allocation *sa =
--				&table->stream_allocations[i];
--		if (sa->vcp_id == vcpi)
--			return sa;
--	}
--	return NULL;
--}
--
--
- static void get_payload_table(
--		struct drm_device *dev,
- 		struct amdgpu_connector *aconnector,
--		const struct dc_stream *stream,
--		const struct dp_mst_stream_allocation_table *cur_table,
- 		struct dp_mst_stream_allocation_table *proposed_table)
- {
- 	int i;
-@@ -203,26 +184,13 @@ static void get_payload_table(
- 			mst_mgr->payloads[i].payload_state ==
- 					DP_PAYLOAD_REMOTE) {
- 
--			const struct dp_mst_stream_allocation *sa_src
--				= find_stream_with_matching_vcpi(
--					cur_table,
--					mst_mgr->proposed_vcpis[i]->vcpi);
--
--			if (sa_src) {
--				proposed_table->stream_allocations[
--					proposed_table->stream_count] = *sa_src;
--				proposed_table->stream_count++;
--			} else {
--				struct dp_mst_stream_allocation *sa =
-+			struct dp_mst_stream_allocation *sa =
- 					&proposed_table->stream_allocations[
- 						proposed_table->stream_count];
- 
--				sa->slot_count =
--						mst_mgr->payloads[i].num_slots;
--				sa->stream = stream;
--				sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
--				proposed_table->stream_count++;
--			}
-+			sa->slot_count = mst_mgr->payloads[i].num_slots;
-+			sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
-+			proposed_table->stream_count++;
- 		}
- 	}
- 
-@@ -235,7 +203,6 @@ static void get_payload_table(
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream,
--		const struct dp_mst_stream_allocation_table *cur_table,
- 		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable)
- {
-@@ -312,7 +279,7 @@ bool dc_helpers_dp_mst_write_payload_allocation_table(
- 	 * stream. AMD ASIC stream slot allocation should follow the same
- 	 * sequence. copy DRM MST allocation to dc */
- 
--	get_payload_table(dev, aconnector, stream, cur_table, proposed_table);
-+	get_payload_table(aconnector, proposed_table);
- 
- 	if (ret)
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 912f3fe..caba06e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1390,6 +1390,58 @@ static struct fixed31_32 get_pbn_from_timing(struct core_stream *stream)
- 	return peak_kbps;
- }
- 
-+static void update_mst_stream_alloc_table(
-+	struct core_link *link,
-+	struct core_stream *stream,
-+	const struct dp_mst_stream_allocation_table *proposed_table)
-+{
-+	struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
-+			{ 0 } };
-+	struct link_mst_stream_allocation *dc_alloc;
-+
-+	int i;
-+	int j;
-+
-+	/* if DRM proposed_table has more than one new payload */
-+	ASSERT(proposed_table->stream_count -
-+			link->mst_stream_alloc_table.stream_count < 2);
-+
-+	/* copy proposed_table to core_link, add stream encoder */
-+	for (i = 0; i < proposed_table->stream_count; i++) {
-+
-+		for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
-+			dc_alloc =
-+			&link->mst_stream_alloc_table.stream_allocations[j];
-+
-+			if (dc_alloc->vcp_id ==
-+				proposed_table->stream_allocations[i].vcp_id) {
-+
-+				work_table[i] = *dc_alloc;
-+				break; /* exit j loop */
-+			}
-+		}
-+
-+		/* new vcp_id */
-+		if (j == link->mst_stream_alloc_table.stream_count) {
-+			work_table[i].vcp_id =
-+				proposed_table->stream_allocations[i].vcp_id;
-+			work_table[i].slot_count =
-+				proposed_table->stream_allocations[i].slot_count;
-+			work_table[i].stream_enc = stream->stream_enc;
-+		}
-+	}
-+
-+	/* update link->mst_stream_alloc_table with work_table */
-+	link->mst_stream_alloc_table.stream_count =
-+			proposed_table->stream_count;
-+	for (i = 0; i < MAX_CONTROLLER_NUM; i++)
-+		link->mst_stream_alloc_table.stream_allocations[i] =
-+				work_table[i];
-+}
-+
-+/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
-+ * because stream_encoder is not exposed to dm
-+ */
- static enum dc_status allocate_mst_payload(struct core_stream *stream)
- {
- 	struct core_link *link = stream->sink->link;
-@@ -1411,31 +1463,32 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	dc_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->public,
--		&link->stream_alloc_table,
- 		&proposed_table,
- 		true);
- 
-+	update_mst_stream_alloc_table(link, stream, &proposed_table);
-+
- 	dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_MST,
- 			LOG_MINOR_MST_PROGRAMMING,
- 			"%s  "
- 			"stream_count: %d: \n ",
- 			__func__,
--			proposed_table.stream_count);
-+			link->mst_stream_alloc_table.stream_count);
- 
- 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
- 		dal_logger_write(link->ctx->logger,
- 		LOG_MAJOR_MST,
- 		LOG_MINOR_MST_PROGRAMMING,
--		"stream[%d]: 0x%x      "
-+		"stream_enc[%d]: 0x%x      "
- 		"stream[%d].vcp_id: %d      "
- 		"stream[%d].slot_count: %d\n",
- 		i,
--		proposed_table.stream_allocations[i].stream,
-+		link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
- 		i,
--		proposed_table.stream_allocations[i].vcp_id,
-+		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
- 		i,
--		proposed_table.stream_allocations[i].slot_count);
-+		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
- 	}
- 
- 	ASSERT(proposed_table.stream_count > 0);
-@@ -1453,9 +1506,7 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	/* program DP source TX for payload */
- 	link_encoder->funcs->update_mst_stream_allocation_table(
- 		link_encoder,
--		&proposed_table);
--
--	link->stream_alloc_table = proposed_table;
-+		&link->mst_stream_alloc_table);
- 
- 	/* send down message */
- 	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-@@ -1509,9 +1560,15 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 		dc_helpers_dp_mst_write_payload_allocation_table(
- 				stream->ctx,
- 				&stream->public,
--				&link->stream_alloc_table,
- 				&proposed_table,
- 				false);
-+	dc_helpers_dp_mst_write_payload_allocation_table(
-+		stream->ctx,
-+		&stream->public,
-+		&proposed_table,
-+		false);
-+
-+	update_mst_stream_alloc_table(link, stream, &proposed_table);
- 
- 	dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_MST,
-@@ -1519,28 +1576,26 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 			"%s"
- 			"stream_count: %d: ",
- 			__func__,
--			proposed_table.stream_count);
-+			link->mst_stream_alloc_table.stream_count);
- 
- 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
- 		dal_logger_write(link->ctx->logger,
- 		LOG_MAJOR_MST,
- 		LOG_MINOR_MST_PROGRAMMING,
--		"stream[%d]: 0x%x"
--		"stream[%d].vcp_id: %d"
--		"stream[%d].slot_count: %d",
-+		"stream_enc[%d]: 0x%x      "
-+		"stream[%d].vcp_id: %d      "
-+		"stream[%d].slot_count: %d\n",
- 		i,
--		proposed_table.stream_allocations[i].stream,
-+		link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
- 		i,
--		proposed_table.stream_allocations[i].vcp_id,
-+		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
- 		i,
--		proposed_table.stream_allocations[i].slot_count);
-+		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
- 	}
- 
- 	link_encoder->funcs->update_mst_stream_allocation_table(
- 		link_encoder,
--		&proposed_table);
--
--	link->stream_alloc_table = proposed_table;
-+		&link->mst_stream_alloc_table);
- 
- 	if (mst_mode) {
- 		dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-@@ -1589,31 +1644,4 @@ void core_link_disable_stream(
- 
- }
- 
--void core_link_update_stream(
--		struct core_link *link,
--		struct core_stream *stream)
--{
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
--		uint32_t i;
- 
--		for (i = 0; i < link->stream_alloc_table.stream_count; i++) {
--			const struct core_stream *s;
--
--			s = DC_STREAM_TO_CORE(
--				link->stream_alloc_table.
--				stream_allocations[i].stream);
--
--			if (stream->stream_enc == s->stream_enc) {
--			link->stream_alloc_table.stream_allocations[i].stream =
--					&stream->public;
--
--			dal_logger_write(link->ctx->logger,
--					LOG_MAJOR_MST,
--					LOG_MINOR_MST_PROGRAMMING,
--					"%s  ",
--					__func__);
--			break;
--			}
--		}
--	}
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 8f1b869..2ed9eb8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -96,7 +96,7 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
- {
- 	/* MST disable link only when no stream use the link */
--	if (link->stream_alloc_table.stream_count > 0)
-+	if (link->mst_stream_alloc_table.stream_count > 0)
- 		return;
- 
- 	dp_disable_link_phy(link, stream->signal);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-index bd082d8..6bb1160 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-@@ -46,7 +46,6 @@ enum dc_edid_status dc_helpers_parse_edid_caps(
- bool dc_helpers_dp_mst_write_payload_allocation_table(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream,
--		const struct dp_mst_stream_allocation_table *cur_table,
- 		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 44ad5a2..74d437e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -898,11 +898,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			context->res_ctx.pool.timing_generators[controller_idx],
- 			color_space);
- 
--	if (timing_changed) {
-+	if (timing_changed)
- 		core_link_enable_stream(stream->sink->link, stream);
--	} else {
--		core_link_update_stream(stream->sink->link, stream);
--	}
- 
- 	if (dc_is_dp_signal(stream->signal))
- 		unblank_stream(stream, &stream->sink->link->cur_link_settings);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 780c3a6..4a83e25 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1592,16 +1592,14 @@ void dce110_link_encoder_dp_set_phy_pattern(
- }
- 
- static void fill_stream_allocation_row_info(
--	const struct dp_mst_stream_allocation *stream_allocation,
-+	const struct link_mst_stream_allocation *stream_allocation,
- 	uint32_t *src,
- 	uint32_t *slots)
- {
--	const struct dc_stream *dc_stream = stream_allocation->stream;
--	struct core_stream *core_stream;
-+	const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
- 
--	if (dc_stream) {
--		core_stream = DC_STREAM_TO_CORE(dc_stream);
--		*src = core_stream->stream_enc->id;
-+	if (stream_enc) {
-+		*src = stream_enc->id;
- 		*slots = stream_allocation->slot_count;
- 	} else {
- 		*src = 0;
-@@ -1612,7 +1610,7 @@ static void fill_stream_allocation_row_info(
- /* programs DP MST VC payload allocation */
- void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
--	const struct dp_mst_stream_allocation_table *table)
-+	const struct link_mst_stream_allocation_table *table)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 31a33a8..46e2971 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -133,7 +133,7 @@ void dce110_link_encoder_dp_set_phy_pattern(
- /* programs DP MST VC payload allocation */
- void dce110_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
--	const struct dp_mst_stream_allocation_table *table);
-+	const struct link_mst_stream_allocation_table *table);
- 
- void dce110_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index f31ee42..1597b33 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -196,6 +196,25 @@ union dp_wa {
- 	uint32_t raw;
- };
- 
-+/* DP MST stream allocation (payload bandwidth number) */
-+struct link_mst_stream_allocation {
-+	/* DIG front */
-+	const struct stream_encoder *stream_enc;
-+	/* associate DRM payload table with DC stream encoder */
-+	uint8_t vcp_id;
-+	/* number of slots required for the DP stream in transport packet */
-+	uint8_t slot_count;
-+};
-+
-+/* DP MST stream allocation table */
-+struct link_mst_stream_allocation_table {
-+	/* number of DP video streams */
-+	int stream_count;
-+	/* array of stream allocations */
-+	struct link_mst_stream_allocation
-+	stream_allocations[MAX_CONTROLLER_NUM];
-+};
-+
- struct core_link {
- 	struct dc_link public;
- 	const struct dc *dc;
-@@ -221,11 +240,10 @@ struct core_link {
- 	enum edp_revision edp_revision;
- 
- 	/* MST record stream using this link */
--	struct dp_mst_stream_allocation_table stream_alloc_table;
--
- 	struct link_flags {
- 		bool dp_keep_receiver_powered;
- 	} wa_flags;
-+	struct link_mst_stream_allocation_table mst_stream_alloc_table;
- };
- 
- #define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-@@ -248,10 +266,6 @@ void core_link_disable_stream(
- 		struct core_link *link,
- 		struct core_stream *stream);
- 
--void core_link_update_stream(
--		struct core_link *link,
--		struct core_stream *stream);
--
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index f63c479..95defa8 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -55,7 +55,7 @@ struct link_encoder_funcs {
- 		const struct encoder_set_dp_phy_pattern_param *para);
- 	void (*update_mst_stream_allocation_table)(
- 		struct link_encoder *enc,
--		const struct dp_mst_stream_allocation_table *table);
-+		const struct link_mst_stream_allocation_table *table);
- 	void (*set_lcd_backlight_level) (struct link_encoder *enc,
- 		uint32_t level);
- 	void (*backlight_control) (struct link_encoder *enc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-index 5fa9af8..4d48daa 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -69,7 +69,7 @@ static void virtual_link_encoder_dp_set_phy_pattern(
- 
- static void virtual_link_encoder_update_mst_stream_allocation_table(
- 	struct link_encoder *enc,
--	const struct dp_mst_stream_allocation_table *table) {}
-+	const struct link_mst_stream_allocation_table *table) {}
- 
- static void virtual_link_encoder_set_lcd_backlight_level(
- 	struct link_encoder *enc,
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 573dd5c..30fc6f0 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -391,18 +391,16 @@ struct mst_device_info {
- 
- /* DP MST stream allocation (payload bandwidth number) */
- struct dp_mst_stream_allocation {
--	/* stream engine id (DIG) */
--	const struct dc_stream *stream;
--	uint32_t vcp_id;
-+	uint8_t vcp_id;
- 	/* number of slots required for the DP stream in
- 	 * transport packet */
--	uint32_t slot_count;
-+	uint8_t slot_count;
- };
- 
- /* DP MST stream allocation table */
- struct dp_mst_stream_allocation_table {
- 	/* number of DP video streams */
--	uint8_t stream_count;
-+	int stream_count;
- 	/* array of stream allocations */
- 	struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0720-drm-amd-dal-Clean-up-unused-TG-types-move-to-dc-inc.patch b/common/recipes-kernel/linux/files/0720-drm-amd-dal-Clean-up-unused-TG-types-move-to-dc-inc.patch
deleted file mode 100644
index 6c7b475a..00000000
--- a/common/recipes-kernel/linux/files/0720-drm-amd-dal-Clean-up-unused-TG-types-move-to-dc-inc.patch
+++ /dev/null
@@ -1,503 +0,0 @@
-From d5cfe6c222d46b7bec5153c86657e0bde6de3efc Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 21 Jan 2016 16:31:43 -0500
-Subject: [PATCH 0720/1110] drm/amd/dal: Clean up unused TG types, move to
- dc/inc
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   1 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |  13 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   2 +-
- .../drm/amd/dal/dc/inc/timing_generator_types.h    | 155 +++++++++++++++++
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |   4 +-
- .../amd/dal/include/timing_generator_interface.h   |  30 ----
- .../drm/amd/dal/include/timing_generator_types.h   | 190 ---------------------
- 8 files changed, 160 insertions(+), 237 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 71df979..0664af2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -36,7 +36,6 @@
- #include "clock_source_interface.h"
- #include "dc_bios_types.h"
- 
--#include "include/irq_service_interface.h"
- #include "bandwidth_calcs.h"
- #include "include/irq_service_interface.h"
- #include "inc/transform.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 823926c..d2970f8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -29,8 +29,8 @@
- 
- #include "resource.h"
- #include "include/irq_service_interface.h"
--#include "include/timing_generator_interface.h"
- #include "../virtual/virtual_stream_encoder.h"
-+#include "inc/timing_generator_types.h"
- 
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 5dc3605..1bb89d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -35,7 +35,7 @@
- #include "include/grph_object_id.h"
- #include "include/adapter_service_interface.h"
- #include "include/logger_interface.h"
--#include "include/timing_generator_types.h"
-+#include "inc/timing_generator_types.h"
- #include "dce110_timing_generator.h"
- 
- enum black_color_format {
-@@ -582,17 +582,6 @@ bool dce110_timing_generator_program_timing_generator(
- 	/* Enable stereo - only when we need to pack 3D frame. Other types
- 	 * of stereo handled in explicit call */
- 
--	/* TODOSTEREO
--	if (hw_crtc_timing->flags.PACK_3D_FRAME) {
--		struct crtc_stereo_parameters stereo_params = { false };
--		stereo_params.PROGRAM_STEREO = true;
--		stereo_params.PROGRAM_POLARITY = true;
--		stereo_params.FRAME_PACKED = true;
--		stereo_params.RIGHT_EYE_POLARITY =
--			hw_crtc_timing->flags.RIGHT_EYE_3D_POLARITY;
--		tg->funcs->enable_stereo(tg, &stereo_params);
--	}*/
--
- 	return result == BP_RESULT_OK;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index e6aaacc..0ef4708 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -27,7 +27,7 @@
- #define __DC_TIMING_GENERATOR_DCE110_H__
- 
- 
--#include "../include/timing_generator_types.h"
-+#include "inc/timing_generator_types.h"
- #include "../include/grph_object_id.h"
- 
- /* overscan in blank for YUV color space. For RGB, it is zero for black. */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h
-new file mode 100644
-index 0000000..e9ca169
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h
-@@ -0,0 +1,155 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
-+#define __DAL_TIMING_GENERATOR_TYPES_H__
-+
-+#include "include/grph_csc_types.h"
-+
-+struct dc_bios;
-+
-+/**
-+ *  These parameters are required as input when doing blanking/Unblanking
-+*/
-+struct crtc_black_color {
-+	uint32_t black_color_r_cr;
-+	uint32_t black_color_g_y;
-+	uint32_t black_color_b_cb;
-+};
-+
-+/* Contains CRTC vertical/horizontal pixel counters */
-+struct crtc_position {
-+	uint32_t vertical_count;
-+	uint32_t horizontal_count;
-+	uint32_t nominal_vcount;
-+};
-+
-+
-+enum dcp_gsl_purpose {
-+	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
-+	DCP_GSL_PURPOSE_STEREO3D_PHASE,
-+	DCP_GSL_PURPOSE_UNDEFINED
-+};
-+
-+struct dcp_gsl_params {
-+	enum sync_source gsl_group;
-+	enum dcp_gsl_purpose gsl_purpose;
-+	bool timing_server;
-+	bool overlay_present;
-+	bool gsl_paused;
-+};
-+
-+#define LEFT_EYE_3D_PRIMARY_SURFACE 1
-+#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
-+
-+enum test_pattern_dyn_range {
-+	TEST_PATTERN_DYN_RANGE_VESA = 0,
-+	TEST_PATTERN_DYN_RANGE_CEA
-+};
-+
-+enum test_pattern_mode {
-+	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
-+	TEST_PATTERN_MODE_VERTICALBARS,
-+	TEST_PATTERN_MODE_HORIZONTALBARS,
-+	TEST_PATTERN_MODE_SINGLERAMP_RGB,
-+	TEST_PATTERN_MODE_DUALRAMP_RGB
-+};
-+
-+enum test_pattern_color_format {
-+	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_8,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_10,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_12
-+};
-+
-+enum controller_dp_test_pattern {
-+	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
-+	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
-+	CONTROLLER_DP_TEST_PATTERN_PRBS7,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
-+	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
-+	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-+};
-+
-+enum crtc_state {
-+	CRTC_STATE_VBLANK = 0,
-+	CRTC_STATE_VACTIVE
-+};
-+
-+struct timing_generator {
-+	struct timing_generator_funcs *funcs;
-+	struct dc_bios *bp;
-+	struct dc_context *ctx;
-+};
-+
-+
-+struct dc_crtc_timing;
-+
-+struct timing_generator_funcs {
-+	bool (*validate_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing);
-+	void (*program_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing,
-+							bool use_vbios);
-+	bool (*enable_crtc)(struct timing_generator *tg);
-+	bool (*disable_crtc)(struct timing_generator *tg);
-+	bool (*is_counter_moving)(struct timing_generator *tg);
-+	void (*get_position)(struct timing_generator *tg,
-+								int32_t *h_position,
-+								int32_t *v_position);
-+	uint32_t (*get_frame_count)(struct timing_generator *tg);
-+	void (*set_early_control)(struct timing_generator *tg,
-+							   uint32_t early_cntl);
-+	void (*wait_for_state)(struct timing_generator *tg,
-+							enum crtc_state state);
-+	bool (*set_blank)(struct timing_generator *tg,
-+					   bool enable_blanking);
-+	void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color);
-+	void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color);
-+	void (*set_colors)(struct timing_generator *tg,
-+						const struct crtc_black_color *blank_color,
-+						const struct crtc_black_color *overscan_color);
-+
-+	void (*disable_vga)(struct timing_generator *tg);
-+	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
-+	void (*setup_global_swap_lock)(struct timing_generator *tg,
-+							const struct dcp_gsl_params *gsl_params);
-+	void (*enable_reset_trigger)(struct timing_generator *tg,
-+						const struct trigger_params *trigger_params);
-+	void (*disable_reset_trigger)(struct timing_generator *tg);
-+	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
-+	void (*enable_advanced_request)(struct timing_generator *tg,
-+					bool enable, const struct dc_crtc_timing *timing);
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index d5d7059..e9e1124 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -74,8 +74,8 @@ enum hw_timing_standard {
- 	HW_TIMING_STANDARD_EXPLICIT
- };
- 
--/* identical to struct crtc_ranged_timing_control
-- * defined in controller\timing_generator_types.h */
-+/* TODO: identical to struct crtc_ranged_timing_control
-+ * defined in inc\timing_generator_types.h */
- struct hw_ranged_timing_control {
- 	/* set to 1 to force dynamic counter V_COUNT
- 	 * to lock to constant rate counter V_COUNT_NOM
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h b/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-deleted file mode 100644
-index 32d545d..0000000
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_interface.h
-+++ /dev/null
-@@ -1,30 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_TIMING_GENERATOR_INTERFACE_H__
--#define __DAL_TIMING_GENERATOR_INTERFACE_H__
--#include "timing_generator_types.h"
--
--#endif /* AMD_DAL_DEV_INCLUDE_TIMING_GENERATOR_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h b/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-deleted file mode 100644
-index 75dfbab..0000000
---- a/drivers/gpu/drm/amd/dal/include/timing_generator_types.h
-+++ /dev/null
-@@ -1,190 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
--#define __DAL_TIMING_GENERATOR_TYPES_H__
--
--#include "include/grph_csc_types.h"
--
--struct dc_bios;
--
--/**
-- *  These parameters are required as input when doing blanking/Unblanking
--*/
--struct crtc_black_color {
--	uint32_t black_color_r_cr;
--	uint32_t black_color_g_y;
--	uint32_t black_color_b_cb;
--};
--
--/* Contains CRTC vertical/horizontal pixel counters */
--struct crtc_position {
--	uint32_t vertical_count;
--	uint32_t horizontal_count;
--	uint32_t nominal_vcount;
--};
--
--/*
-- * Parameters to enable/disable stereo 3D mode on CRTC
-- *  - rightEyePolarity: if true, '0' means left eye image and '1' means right
-- *    eye image.
-- *	 if false, '0' means right eye image and '1' means left eye image
-- *  - framePacked:      true when HDMI 1.4a FramePacking 3D format
-- *    enabled/disabled
-- */
--struct crtc_stereo_parameters {
--	uint8_t PROGRAM_STEREO:1;
--	uint8_t PROGRAM_POLARITY:1;
--	uint8_t RIGHT_EYE_POLARITY:1;
--	uint8_t FRAME_PACKED:1;
--};
--
--struct crtc_stereo_status {
--	uint8_t ENABLED:1;
--	uint8_t CURRENT_FRAME_IS_RIGHT_EYE:1;
--	uint8_t CURRENT_FRAME_IS_ODD_FIELD:1;
--	uint8_t FRAME_PACKED:1;
--	uint8_t PENDING_RESET:1;
--};
--
--enum dcp_gsl_purpose {
--	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
--	DCP_GSL_PURPOSE_STEREO3D_PHASE,
--	DCP_GSL_PURPOSE_UNDEFINED
--};
--
--struct dcp_gsl_params {
--	enum sync_source gsl_group;
--	enum dcp_gsl_purpose gsl_purpose;
--	bool timing_server;
--	bool overlay_present;
--	bool gsl_paused;
--};
--
--struct vbi_end_signal_setup {
--	uint32_t minimum_interval_in_us; /* microseconds */
--	uint32_t pixel_clock; /* in KHz */
--	bool scaler_enabled;
--	bool interlace;
--	uint32_t src_height;
--	uint32_t overscan_top;
--	uint32_t overscan_bottom;
--	uint32_t v_total;
--	uint32_t v_addressable;
--	uint32_t h_total;
--};
--
--#define LEFT_EYE_3D_PRIMARY_SURFACE 1
--#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
--
--enum test_pattern_dyn_range {
--	TEST_PATTERN_DYN_RANGE_VESA = 0,
--	TEST_PATTERN_DYN_RANGE_CEA
--};
--
--enum test_pattern_mode {
--	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
--	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
--	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
--	TEST_PATTERN_MODE_VERTICALBARS,
--	TEST_PATTERN_MODE_HORIZONTALBARS,
--	TEST_PATTERN_MODE_SINGLERAMP_RGB,
--	TEST_PATTERN_MODE_DUALRAMP_RGB
--};
--
--enum test_pattern_color_format {
--	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
--	TEST_PATTERN_COLOR_FORMAT_BPC_8,
--	TEST_PATTERN_COLOR_FORMAT_BPC_10,
--	TEST_PATTERN_COLOR_FORMAT_BPC_12
--};
--
--enum controller_dp_test_pattern {
--	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
--	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
--	CONTROLLER_DP_TEST_PATTERN_PRBS7,
--	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
--	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
--	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
--	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
--	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
--	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
--};
--
--enum crtc_state {
--	CRTC_STATE_VBLANK = 0,
--	CRTC_STATE_VACTIVE
--};
--
--struct timing_generator {
--	struct timing_generator_funcs *funcs;
--	struct dc_bios *bp;
--	struct dc_context *ctx;
--};
--
--
--struct dc_crtc_timing;
--
--struct timing_generator_funcs {
--	bool (*validate_timing)(struct timing_generator *tg,
--							const struct dc_crtc_timing *timing);
--	void (*program_timing)(struct timing_generator *tg,
--							const struct dc_crtc_timing *timing,
--							bool use_vbios);
--	bool (*enable_crtc)(struct timing_generator *tg);
--	bool (*disable_crtc)(struct timing_generator *tg);
--	bool (*is_counter_moving)(struct timing_generator *tg);
--	void (*get_position)(struct timing_generator *tg,
--								int32_t *h_position,
--								int32_t *v_position);
--	uint32_t (*get_frame_count)(struct timing_generator *tg);
--	void (*set_early_control)(struct timing_generator *tg,
--							   uint32_t early_cntl);
--	void (*wait_for_state)(struct timing_generator *tg,
--							enum crtc_state state);
--	bool (*set_blank)(struct timing_generator *tg,
--					   bool enable_blanking);
--	void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color);
--	void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color);
--	void (*set_colors)(struct timing_generator *tg,
--						const struct crtc_black_color *blank_color,
--						const struct crtc_black_color *overscan_color);
--
--	void (*disable_vga)(struct timing_generator *tg);
--	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
--	void (*setup_global_swap_lock)(struct timing_generator *tg,
--							const struct dcp_gsl_params *gsl_params);
--	void (*enable_reset_trigger)(struct timing_generator *tg,
--						const struct trigger_params *trigger_params);
--	void (*disable_reset_trigger)(struct timing_generator *tg);
--	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
--	void (*enable_advanced_request)(struct timing_generator *tg,
--					bool enable, const struct dc_crtc_timing *timing);
--};
--
--#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0721-drm-amd-dal-Clean-up-encoder_types.patch b/common/recipes-kernel/linux/files/0721-drm-amd-dal-Clean-up-encoder_types.patch
deleted file mode 100644
index ac0df675..00000000
--- a/common/recipes-kernel/linux/files/0721-drm-amd-dal-Clean-up-encoder_types.patch
+++ /dev/null
@@ -1,482 +0,0 @@
-From e7a65721f0c60083acca9fb17486f30e5ac3a776 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 21 Jan 2016 17:28:30 -0500
-Subject: [PATCH 0721/1110] drm/amd/dal: Clean up encoder_types
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_types.h           |   1 +
- drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h  | 129 ++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h   |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h |   2 +-
- drivers/gpu/drm/amd/dal/dc/irq_types.h          |   2 +
- drivers/gpu/drm/amd/dal/include/dal_types.h     |   1 +
- drivers/gpu/drm/amd/dal/include/encoder_types.h | 226 ------------------------
- drivers/gpu/drm/amd/dal/include/fixed31_32.h    |   2 +
- drivers/gpu/drm/amd/dal/include/fixed32_32.h    |   3 +
- 9 files changed, 140 insertions(+), 228 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/encoder_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 1834fe0..b932ec1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -25,6 +25,7 @@
- #ifndef DC_TYPES_H_
- #define DC_TYPES_H_
- 
-+#include "dal_services_types.h"
- #include "fixed32_32.h"
- #include "fixed31_32.h"
- #include "irq_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h b/drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h
-new file mode 100644
-index 0000000..7f3b9ad
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h
-@@ -0,0 +1,129 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ENCODER_TYPES_H__
-+#define __DAL_ENCODER_TYPES_H__
-+
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+#include "hw_sequencer_types.h"
-+#include "link_service_types.h"
-+
-+struct encoder_init_data {
-+	struct adapter_service *adapter_service;
-+	enum channel_id channel;
-+	struct graphics_object_id connector;
-+	enum hpd_source_id hpd_source;
-+	/* TODO: in DAL2, here was pointer to EventManagerInterface */
-+	struct graphics_object_id encoder;
-+	struct dc_context *ctx;
-+	enum transmitter transmitter;
-+};
-+
-+struct encoder_context {
-+	/*
-+	 * HW programming context
-+	 */
-+	/* DIG id. Also used as AC context */
-+	enum engine_id engine;
-+	/* DDC line */
-+	enum channel_id channel;
-+	/* HPD line */
-+	enum hpd_source_id hpd_source;
-+	/*
-+	 * ASIC Control (VBIOS) context
-+	 */
-+	/* encoder output signal */
-+	enum signal_type signal;
-+	/* native connector id */
-+	struct graphics_object_id connector;
-+	/* downstream object (can be connector or downstream encoder) */
-+	struct graphics_object_id downstream;
-+};
-+
-+struct encoder_info_packet {
-+	bool valid;
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t hb3;
-+	uint8_t sb[28];
-+};
-+
-+struct encoder_info_frame {
-+	/* auxiliary video information */
-+	struct encoder_info_packet avi;
-+	struct encoder_info_packet gamut;
-+	struct encoder_info_packet vendor;
-+	/* source product description */
-+	struct encoder_info_packet spd;
-+	/* video stream configuration */
-+	struct encoder_info_packet vsc;
-+};
-+
-+struct encoder_unblank_param {
-+	struct hw_crtc_timing crtc_timing;
-+	struct link_settings link_settings;
-+};
-+
-+struct encoder_set_dp_phy_pattern_param {
-+	enum dp_test_pattern dp_phy_pattern;
-+	const uint8_t *custom_pattern;
-+	uint32_t custom_pattern_size;
-+	enum dp_panel_mode dp_panel_mode;
-+};
-+
-+struct encoder_feature_support {
-+	union {
-+		struct {
-+			/* 1 - external encoder; 0 - internal encoder */
-+			uint32_t EXTERNAL_ENCODER:1;
-+			uint32_t ANALOG_ENCODER:1;
-+			uint32_t STEREO_SYNC:1;
-+			/* check the DDC data pin
-+			 * when performing DP Sink detection */
-+			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
-+			/* CPLIB authentication
-+			 * for external DP chip supported */
-+			uint32_t CPLIB_DP_AUTHENTICATION:1;
-+			uint32_t IS_HBR2_CAPABLE:1;
-+			uint32_t IS_HBR2_VALIDATED:1;
-+			uint32_t IS_TPS3_CAPABLE:1;
-+			uint32_t IS_AUDIO_CAPABLE:1;
-+			uint32_t IS_VCE_SUPPORTED:1;
-+			uint32_t IS_CONVERTER:1;
-+			uint32_t IS_Y_ONLY_CAPABLE:1;
-+			uint32_t IS_YCBCR_CAPABLE:1;
-+		} bits;
-+		uint32_t raw;
-+	} flags;
-+	/* maximum supported deep color depth */
-+	enum dc_color_depth max_deep_color;
-+	/* maximum supported clock */
-+	uint32_t max_pixel_clock;
-+};
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index 95defa8..23920e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -8,8 +8,8 @@
- #ifndef LINK_ENCODER_H_
- #define LINK_ENCODER_H_
- 
--#include "include/encoder_types.h"
- #include "core_types.h"
-+#include "encoder_types.h"
- 
- struct link_enc_status {
- 	int dummy; /*TODO*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-index 9665356..3de1f80 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-@@ -6,7 +6,7 @@
- #ifndef STREAM_ENCODER_H_
- #define STREAM_ENCODER_H_
- 
--#include "include/encoder_types.h"
-+#include "encoder_types.h"
- #include "include/bios_parser_interface.h"
- 
- struct dc_bios;
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq_types.h b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-index 35a0991..f8f2395 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-@@ -26,6 +26,8 @@
- #ifndef __DAL_IRQ_TYPES_H__
- #define __DAL_IRQ_TYPES_H__
- 
-+#include "dal_services_types.h"
-+
- struct dc_context;
- 
- typedef void (*interrupt_handler)(void *);
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 0e16ebb..77bd09b 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -26,6 +26,7 @@
- #ifndef __DAL_TYPES_H__
- #define __DAL_TYPES_H__
- 
-+#include "dal_services_types.h"
- #include "signal_types.h"
- #include "dc_types.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_types.h b/drivers/gpu/drm/amd/dal/include/encoder_types.h
-deleted file mode 100644
-index 6a7b317..0000000
---- a/drivers/gpu/drm/amd/dal/include/encoder_types.h
-+++ /dev/null
-@@ -1,226 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_ENCODER_TYPES_H__
--#define __DAL_ENCODER_TYPES_H__
--
--#include "grph_object_defs.h"
--#include "signal_types.h"
--#include "hw_sequencer_types.h"
--#include "link_service_types.h"
--
--struct encoder_init_data {
--	struct adapter_service *adapter_service;
--	enum channel_id channel;
--	struct graphics_object_id connector;
--	enum hpd_source_id hpd_source;
--	/* TODO: in DAL2, here was pointer to EventManagerInterface */
--	struct graphics_object_id encoder;
--	struct dc_context *ctx;
--	enum transmitter transmitter;
--};
--
--struct encoder_context {
--	/*
--	 * HW programming context
--	 */
--	/* DIG id. Also used as AC context */
--	enum engine_id engine;
--	/* DDC line */
--	enum channel_id channel;
--	/* HPD line */
--	enum hpd_source_id hpd_source;
--	/*
--	 * ASIC Control (VBIOS) context
--	 */
--	/* encoder output signal */
--	enum signal_type signal;
--	/* native connector id */
--	struct graphics_object_id connector;
--	/* downstream object (can be connector or downstream encoder) */
--	struct graphics_object_id downstream;
--};
--
--union encoder_flags {
--	struct {
--		/* enable audio (DP/eDP only) */
--		uint32_t ENABLE_AUDIO:1;
--		/* coherency */
--		uint32_t COHERENT:1;
--		/* delay after Pixel Format change before enable transmitter */
--		uint32_t DELAY_AFTER_PIXEL_FORMAT_CHANGE:1;
--		/* by default, do not turn off VCC when disabling output */
--		uint32_t TURN_OFF_VCC:1;
--		/* by default, do wait for HPD low after turn of panel VCC */
--		uint32_t NO_WAIT_FOR_HPD_LOW:1;
--		/* slow DP panels don't reset internal fifo */
--		uint32_t VID_STREAM_DIFFER_TO_SYNC:1;
--	} bits;
--	uint32_t raw;
--};
--
--struct encoder_info_packet {
--	bool valid;
--	uint8_t hb0;
--	uint8_t hb1;
--	uint8_t hb2;
--	uint8_t hb3;
--	uint8_t sb[28];
--};
--
--struct encoder_info_frame {
--	/* auxiliary video information */
--	struct encoder_info_packet avi;
--	struct encoder_info_packet gamut;
--	struct encoder_info_packet vendor;
--	/* source product description */
--	struct encoder_info_packet spd;
--	/* video stream configuration */
--	struct encoder_info_packet vsc;
--};
--
--struct encoder_info_frame_param {
--	struct encoder_info_frame packets;
--	struct encoder_context enc_ctx;
--};
--
--/*TODO: cleanup pending encoder cleanup*/
--struct encoder_output {
--	/* encoder AC & HW programming context */
--	struct encoder_context enc_ctx;
--	/* requested timing */
--	struct hw_crtc_timing crtc_timing;
--	/* clock source id (PLL or external) */
--	enum clock_source_id clock_source;
--	/* link settings (DP/eDP only) */
--	struct link_settings link_settings;
--	/* info frame packets */
--	struct encoder_info_frame info_frame;
--	/* timing validation (HDMI only) */
--	uint32_t max_tmds_clk_from_edid_in_mhz;
--	/* edp panel mode */
--	enum dp_panel_mode dp_panel_mode;
--	/* delay in milliseconds after powering up DP receiver (DP/eDP only) */
--	uint32_t delay_after_dp_receiver_power_up;
--	/* various flags for features and workarounds */
--	union encoder_flags flags;
--	/* delay after pixel format change */
--	uint32_t delay_after_pixel_format_change;
--	/* controller id */
--	enum controller_id controller;
--	/* maximum supported deep color depth for HDMI */
--	enum dc_color_depth max_hdmi_deep_color;
--	/* maximum supported pixel clock for HDMI */
--	uint32_t max_hdmi_pixel_clock;
--};
--
--struct encoder_pre_enable_output_param {
--	struct hw_crtc_timing crtc_timing;
--	struct link_settings link_settings;
--	struct encoder_context enc_ctx;
--};
--
--struct encoder_unblank_param {
--	struct hw_crtc_timing crtc_timing;
--	struct link_settings link_settings;
--};
--
--/*
-- * @brief
-- * Parameters to setup stereo 3D mode in Encoder:
-- * - source: used for side-band stereo sync (DVO/DAC);
-- * - engine_id: defines engine for this Encoder;
-- * - enable_inband: in-band stereo sync should be enabled;
-- * - enable_sideband: side-band stereo sync should be enabled.
-- */
--struct encoder_3d_setup {
--	enum engine_id engine;
--	enum sync_source source;
--	union {
--		struct {
--			uint32_t SETUP_SYNC_SOURCE:1;
--			uint32_t ENABLE_INBAND:1;
--			uint32_t ENABLE_SIDEBAND:1;
--			uint32_t DISABLE_INBAND:1;
--			uint32_t DISABLE_SIDEBAND:1;
--		} bits;
--		uint32_t raw;
--	} flags;
--};
--
--struct encoder_set_dp_phy_pattern_param {
--	enum dp_test_pattern dp_phy_pattern;
--	const uint8_t *custom_pattern;
--	uint32_t custom_pattern_size;
--	enum dp_panel_mode dp_panel_mode;
--};
--
--struct encoder_feature_support {
--	union {
--		struct {
--			/* 1 - external encoder; 0 - internal encoder */
--			uint32_t EXTERNAL_ENCODER:1;
--			uint32_t ANALOG_ENCODER:1;
--			uint32_t STEREO_SYNC:1;
--			/* check the DDC data pin
--			 * when performing DP Sink detection */
--			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
--			/* CPLIB authentication
--			 * for external DP chip supported */
--			uint32_t CPLIB_DP_AUTHENTICATION:1;
--			uint32_t IS_HBR2_CAPABLE:1;
--			uint32_t IS_HBR2_VALIDATED:1;
--			uint32_t IS_TPS3_CAPABLE:1;
--			uint32_t IS_AUDIO_CAPABLE:1;
--			uint32_t IS_VCE_SUPPORTED:1;
--			uint32_t IS_CONVERTER:1;
--			uint32_t IS_Y_ONLY_CAPABLE:1;
--			uint32_t IS_YCBCR_CAPABLE:1;
--		} bits;
--		uint32_t raw;
--	} flags;
--	/* maximum supported deep color depth */
--	enum dc_color_depth max_deep_color;
--	/* maximum supported clock */
--	uint32_t max_pixel_clock;
--};
--
--enum dig_encoder_mode {
--	DIG_ENCODER_MODE_DP,
--	DIG_ENCODER_MODE_LVDS,
--	DIG_ENCODER_MODE_DVI,
--	DIG_ENCODER_MODE_HDMI,
--	DIG_ENCODER_MODE_SDVO,
--	DIG_ENCODER_MODE_DP_WITH_AUDIO,
--	DIG_ENCODER_MODE_DP_MST,
--
--	/* direct HW translation ! */
--	DIG_ENCODER_MODE_TV = 13,
--	DIG_ENCODER_MODE_CV,
--	DIG_ENCODER_MODE_CRT
--};
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed31_32.h b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-index 507f9f6..4577809 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-@@ -26,6 +26,8 @@
- #ifndef __DAL_FIXED31_32_H__
- #define __DAL_FIXED31_32_H__
- 
-+#include "dal_services_types.h"
-+
- /*
-  * @brief
-  * Arithmetic operations on real numbers
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-index 5fca957..5291a30 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -26,6 +26,9 @@
- #ifndef __DAL_FIXED32_32_H__
- #define __DAL_FIXED32_32_H__
- 
-+#include "dal_services_types.h"
-+
-+
- struct fixed32_32 {
- 	uint64_t value;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0722-drm-amd-dal-Clean-up-set_mode_interface-and-adjustme.patch b/common/recipes-kernel/linux/files/0722-drm-amd-dal-Clean-up-set_mode_interface-and-adjustme.patch
deleted file mode 100644
index df8124ec..00000000
--- a/common/recipes-kernel/linux/files/0722-drm-amd-dal-Clean-up-set_mode_interface-and-adjustme.patch
+++ /dev/null
@@ -1,1028 +0,0 @@
-From 93c0370877ada6230c6fab7687f299aca2f9495b Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 21 Jan 2016 18:04:08 -0500
-Subject: [PATCH 0722/1110] drm/amd/dal: Clean up set_mode_interface and
- adjustment structs
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |   3 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   7 -
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   1 +
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |  99 +++++
- drivers/gpu/drm/amd/dal/include/adjustment_types.h | 420 ---------------------
- .../gpu/drm/amd/dal/include/hw_adjustment_types.h  | 205 ----------
- drivers/gpu/drm/amd/dal/include/set_mode_types.h   | 144 +------
- 9 files changed, 104 insertions(+), 779 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/include/adjustment_types.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index c52a1e2..2aa8db1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -29,7 +29,7 @@
- #include "link_encoder.h"
- #include "stream_encoder.h"
- #include "opp.h"
--
-+#include "transform.h"
- 
- void unreference_clock_source(
- 		struct resource_context *res_ctx,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 41a5feb..ce60e9d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -29,8 +29,7 @@
- 
- /* DC core (private) */
- #include "core_dc.h"
--#include "adjustment_types.h"
--
-+#include "inc/transform.h"
- 
- /*******************************************************************************
-  * Private structures
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 74d437e..f899565 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1498,13 +1498,6 @@ static bool set_plane_config(
- 			controller_idx,
- 			BLENDER_MODE_CURRENT_PIPE);
- 
--#if 0
--	program_alpha_mode(
--			crtc,
--			&pl_cfg->attributes.blend_flags,
--			path_mode->mode.timing.pixel_encoding);
--#endif
--
- 	mi->funcs->mem_input_program_surface_config(
- 			mi,
- 			surface->public.format,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 0ef4708..0a57052 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -29,6 +29,7 @@
- 
- #include "inc/timing_generator_types.h"
- #include "../include/grph_object_id.h"
-+#include "../include/hw_sequencer_types.h"
- 
- /* overscan in blank for YUV color space. For RGB, it is zero for black. */
- #define CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV 0x1f4
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index 9d62a24..2d5644c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -10,7 +10,7 @@
- 
- #include "core_types.h"
- #include "hw_sequencer.h"
--
-+#include "dal_services.h"
- 
- struct dc {
- 	struct dc_context *ctx;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 7b882ec..50dde2d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -81,6 +81,105 @@ enum lb_pixel_depth {
- 	LB_PIXEL_DEPTH_36BPP = 8
- };
- 
-+
-+struct raw_gamma_ramp_rgb {
-+       uint32_t red;
-+       uint32_t green;
-+       uint32_t blue;
-+};
-+
-+enum raw_gamma_ramp_type {
-+       GAMMA_RAMP_TYPE_UNINITIALIZED,
-+       GAMMA_RAMP_TYPE_DEFAULT,
-+       GAMMA_RAMP_TYPE_RGB256,
-+       GAMMA_RAMP_TYPE_FIXED_POINT
-+};
-+
-+#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
-+struct raw_gamma_ramp {
-+       enum raw_gamma_ramp_type type;
-+       struct raw_gamma_ramp_rgb rgb_256[NUM_OF_RAW_GAMMA_RAMP_RGB_256];
-+       uint32_t size;
-+};
-+
-+
-+/* Colorimetry */
-+enum colorimetry {
-+       COLORIMETRY_NO_DATA = 0,
-+       COLORIMETRY_ITU601 = 1,
-+       COLORIMETRY_ITU709 = 2,
-+       COLORIMETRY_EXTENDED = 3
-+};
-+
-+/* ColorimetryEx */
-+enum colorimetry_ex {
-+       COLORIMETRY_EX_XVYCC601 = 0,
-+       COLORIMETRY_EX_XVYCC709 = 1,
-+       COLORIMETRY_EX_SYCC601 = 2,
-+       COLORIMETRY_EX_ADOBEYCC601 = 3,
-+       COLORIMETRY_EX_ADOBERGB = 4,
-+       COLORIMETRY_EX_RESERVED5 = 5,
-+       COLORIMETRY_EX_RESERVED6 = 6,
-+       COLORIMETRY_EX_RESERVED7 = 7
-+};
-+
-+enum ds_color_space {
-+       DS_COLOR_SPACE_UNKNOWN = 0,
-+       DS_COLOR_SPACE_SRGB_FULLRANGE = 1,
-+       DS_COLOR_SPACE_SRGB_LIMITEDRANGE,
-+       DS_COLOR_SPACE_YPBPR601,
-+       DS_COLOR_SPACE_YPBPR709,
-+       DS_COLOR_SPACE_YCBCR601,
-+       DS_COLOR_SPACE_YCBCR709,
-+       DS_COLOR_SPACE_NMVPU_SUPERAA,
-+       DS_COLOR_SPACE_YCBCR601_YONLY,
-+       DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/
-+};
-+
-+
-+enum active_format_info {
-+       ACTIVE_FORMAT_NO_DATA = 0,
-+       ACTIVE_FORMAT_VALID = 1
-+};
-+
-+/* Active format aspect ratio */
-+enum active_format_aspect_ratio {
-+       ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
-+       ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
-+       ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
-+       ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
-+};
-+
-+enum bar_info {
-+       BAR_INFO_NOT_VALID = 0,
-+       BAR_INFO_VERTICAL_VALID = 1,
-+       BAR_INFO_HORIZONTAL_VALID = 2,
-+       BAR_INFO_BOTH_VALID = 3
-+};
-+
-+enum picture_scaling {
-+       PICTURE_SCALING_UNIFORM = 0,
-+       PICTURE_SCALING_HORIZONTAL = 1,
-+       PICTURE_SCALING_VERTICAL = 2,
-+       PICTURE_SCALING_BOTH = 3
-+};
-+
-+/* RGB quantization range */
-+enum rgb_quantization_range {
-+       RGB_QUANTIZATION_DEFAULT_RANGE = 0,
-+       RGB_QUANTIZATION_LIMITED_RANGE = 1,
-+       RGB_QUANTIZATION_FULL_RANGE = 2,
-+       RGB_QUANTIZATION_RESERVED = 3
-+};
-+
-+/* YYC quantization range */
-+enum yyc_quantization_range {
-+       YYC_QUANTIZATION_LIMITED_RANGE = 0,
-+       YYC_QUANTIZATION_FULL_RANGE = 1,
-+       YYC_QUANTIZATION_RESERVED2 = 2,
-+       YYC_QUANTIZATION_RESERVED3 = 3
-+};
-+
- struct transform_funcs {
- 	bool (*transform_power_up)(struct transform *xfm);
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/adjustment_types.h b/drivers/gpu/drm/amd/dal/include/adjustment_types.h
-deleted file mode 100644
-index f6c0d61..0000000
---- a/drivers/gpu/drm/amd/dal/include/adjustment_types.h
-+++ /dev/null
-@@ -1,420 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_ADJUSTMENT_TYPES_H__
--#define __DAL_ADJUSTMENT_TYPES_H__
--
--#include "dal_services.h"
--
--/* make sure to update this when updating adj_global_info_array */
--#define CURRENT_ADJUSTMENT_NUM 12
--#define MAX_ADJUSTMENT_NUM (ADJ_ID_END - ADJ_ID_BEGIN)
--#define REGAMMA_VALUE	256
--#define REGAMMA_RANGE	(REGAMMA_VALUE*3)
--#define ADJUST_DIVIDER	100
--#define GAMUT_DIVIDER	10000
--
--
--enum adjustment_id {
--
--	/*this useful type when i need to indicate unknown adjustment and code
--	look if not the specific type*/
--	ADJ_ID_INVALID,
--
--	ADJ_ID_CONTRAST,
--	ADJ_ID_BRIGHTNESS,
--	ADJ_ID_HUE,
--	ADJ_ID_SATURATION,
--	ADJ_ID_GAMMA_RAMP,
--	ADJ_ID_GAMMA_RAMP_REGAMMA_UPDATE,
--	ADJ_ID_TEMPERATURE,
--	ADJ_ID_NOMINAL_RANGE_RGB_LIMITED,
--
--	ADJ_ID_LP_FILTER_DEFLICKER,
--	ADJ_ID_HP_FILTER_DEFLICKER,
--	ADJ_ID_SHARPNESS_GAIN, /*0 - 10*/
--
--	ADJ_ID_REDUCED_BLANKING,
--	ADJ_ID_COHERENT,
--	ADJ_ID_MULTIMEDIA_PASS_THROUGH,
--
--	ADJ_ID_VERTICAL_POSITION,
--	ADJ_ID_HORIZONTA_LPOSITION,
--	ADJ_ID_VERTICAL_SIZE,
--	ADJ_ID_HORIZONTAL_SIZE,
--	ADJ_ID_VERTICAL_SYNC,
--	ADJ_ID_HORIZONTAL_SYNC,
--	ADJ_ID_OVERSCAN,
--	ADJ_ID_COMPOSITE_SYNC,
--
--	ADJ_ID_BIT_DEPTH_REDUCTION,/*CWDDEDI_DISPLAY_ADJINFOTYPE_BITVECTOR*/
--	ADJ_ID_UNDERSCAN,/*CWDDEDI_DISPLAY_ADJINFOTYPE_RANGE*/
--	ADJ_ID_UNDERSCAN_TYPE,/*CWDDEDI_DISPLAY_ADJINFOTYPE_RANGE*/
--	ADJ_ID_TEMPERATURE_SOURCE,/*CWDDEDI_DISPLAY_ADJINFOTYPE_BITVECTOR*/
--
--	ADJ_ID_OVERLAY_BRIGHTNESS,
--	ADJ_ID_OVERLAY_CONTRAST,
--	ADJ_ID_OVERLAY_SATURATION,
--	ADJ_ID_OVERLAY_HUE,
--	ADJ_ID_OVERLAY_GAMMA,
--	ADJ_ID_OVERLAY_ALPHA,
--	ADJ_ID_OVERLAY_ALPHA_PER_PIX,
--	ADJ_ID_OVERLAY_INV_GAMMA,
--	ADJ_ID_OVERLAY_TEMPERATURE,/*done ,but code is commented*/
--	ADJ_ID_OVERLAY_NOMINAL_RANGE_RGB_LIMITED,
--
--
--	ADJ_ID_UNDERSCAN_TV_INTERNAL,/*internal usage only for HDMI*/
--				/*custom TV modes*/
--	ADJ_ID_DRIVER_REQUESTED_GAMMA,/*used to get current gamma*/
--	ADJ_ID_GAMUT_SOURCE_GRPH,/*logical adjustment visible for DS and CDB*/
--	ADJ_ID_GAMUT_SOURCE_OVL,/*logical adjustment visible for DS and CDB*/
--	ADJ_ID_GAMUT_DESTINATION,/*logical adjustment visible for DS and CDB*/
--	ADJ_ID_REGAMMA,/*logical adjustment visible for DS and CDB*/
--	ADJ_ID_ITC_ENABLE,/*ITC flag enable by default*/
--	ADJ_ID_CNC_CONTENT,/*display image content*/
--	/*internal adjustment, in order to provide backward compatibility
--	 gamut with color temperature*/
--
--	/* Backlight Adjustment Group*/
--	ADJ_ID_BACKLIGHT,
--	ADJ_ID_BACKLIGHT_OPTIMIZATION,
--
--	/* flag the first and last*/
--	ADJ_ID_BEGIN = ADJ_ID_CONTRAST,
--	ADJ_ID_END = ADJ_ID_BACKLIGHT_OPTIMIZATION,
--};
--
--enum adjustment_data_type {
--	ADJ_RANGED,
--	ADJ_BITVECTOR,
--	ADJ_LUT /* not handled currently */
--};
--
--union adjustment_property {
--	uint32_t u32all;
--	struct {
--		/*per mode adjustment*/
--		uint32_t SAVED_WITHMODE:1;
--		/*per edid adjustment*/
--		uint32_t SAVED_WITHEDID:1;
--		/*adjustment not visible to HWSS*/
--		uint32_t CALCULATE:1;
--		/*explisit adjustment applied by HWSS*/
--		uint32_t INC_IN_SET_MODE:1;
--		/*adjustment requires set mode to be applied*/
--		uint32_t SETMODE_REQ:1;
--		/*adjustment is applied at the end of set mode*/
--		uint32_t POST_SET:1;
--/*when adjustment is applied its value should be stored
--in place and not wait for flush call*/
--		uint32_t SAVE_IN_PLACE:1;
--		/*adjustment is always apply*/
--		uint32_t FORCE_SET:1;
--		/*this adjustment is specific to individual display path.*/
--		uint32_t SAVED_WITH_DISPLAY_IDX:1;
--		uint32_t RESERVED_23:23;
--	} bits;
--};
--
--enum adjustment_state {
--	ADJUSTMENT_STATE_INVALID,
--	ADJUSTMENT_STATE_VALID,
--	ADJUSTMENT_STATE_REQUESTED,
--	ADJUSTMENT_STATE_COMMITTED_TO_HW,
--};
--
--/* AdjustmentInfo structure - it keeps either ranged data or discrete*/
--struct adjustment_info {
--	enum adjustment_data_type adj_data_type;
--	union adjustment_property adj_prop;
--	enum adjustment_state adj_state;
--	enum adjustment_id adj_id;
--
--	union data {
--		struct ranged {
--			int32_t min;
--			int32_t max;
--			int32_t def;
--			int32_t step;
--			int32_t cur;
--		} ranged;
--		struct bit_vector {
--			int32_t system_supported;
--			int32_t current_supported;
--			int32_t default_val;
--		} bit_vector;
--	} adj_data;
--};
--
--/* adjustment category
--this should be a MASK struct with the bitfileds!!!
--since it could be crt and cv and dfp!!!
--the only fit is for overlay!!!*/
--enum adjustment_category {
--	CAT_ALL,
--	CAT_CRT,
--	CAT_DFP,
--	CAT_LCD,
--	CAT_OVERLAY,
--	CAT_INVALID
--};
--
--enum raw_gamma_ramp_type {
--	GAMMA_RAMP_TYPE_UNINITIALIZED,
--	GAMMA_RAMP_TYPE_DEFAULT,
--	GAMMA_RAMP_TYPE_RGB256,
--	GAMMA_RAMP_TYPE_FIXED_POINT
--};
--
--struct raw_gamma_ramp_rgb {
--	uint32_t red;
--	uint32_t green;
--	uint32_t blue;
--};
--
--#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
--struct raw_gamma_ramp {
--	enum raw_gamma_ramp_type type;
--	struct raw_gamma_ramp_rgb rgb_256[NUM_OF_RAW_GAMMA_RAMP_RGB_256];
--	uint32_t size;
--};
--
--struct ds_underscan_info {
--	uint32_t default_width;
--	uint32_t default_height;
--	uint32_t max_width;
--	uint32_t max_height;
--	uint32_t min_width;
--	uint32_t min_height;
--	uint32_t h_step;
--	uint32_t v_step;
--	uint32_t default_x_pos;
--	uint32_t default_y_pos;
--};
--
--struct ds_overscan {
--	uint32_t left;
--	uint32_t right;
--	uint32_t top;
--	uint32_t bottom;
--};
--
--enum ds_color_space {
--	DS_COLOR_SPACE_UNKNOWN = 0,
--	DS_COLOR_SPACE_SRGB_FULLRANGE = 1,
--	DS_COLOR_SPACE_SRGB_LIMITEDRANGE,
--	DS_COLOR_SPACE_YPBPR601,
--	DS_COLOR_SPACE_YPBPR709,
--	DS_COLOR_SPACE_YCBCR601,
--	DS_COLOR_SPACE_YCBCR709,
--	DS_COLOR_SPACE_NMVPU_SUPERAA,
--	DS_COLOR_SPACE_YCBCR601_YONLY,
--	DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/
--};
--
--enum ds_underscan_options {
--	DS_UNDERSCAN_OPTION_DEFAULT = 0,
--	DS_UNDERSCAN_OPTION_USECEA861D
--};
--
--enum dpms_state {
--	DPMS_NONE = 0,
--	DPMS_ON,
--	DPMS_OFF,
--};
--
--enum ds_gamut_reference {
--	DS_GAMUT_REFERENCE_DESTINATION = 0,
--	DS_GAMUT_REFERENCE_SOURCE,
--};
--
--enum ds_gamut_content {
--	DS_GAMUT_CONTENT_GRAPHICS = 0,
--	DS_GAMUT_CONTENT_VIDEO,
--};
--
--struct ds_gamut_reference_data {
--	enum ds_gamut_reference gamut_ref;
--	enum ds_gamut_content gamut_content;
--};
--
--union ds_custom_gamut_type {
--	uint32_t u32all;
--	struct {
--		uint32_t CUSTOM_WHITE_POINT:1;
--		uint32_t CUSTOM_GAMUT_SPACE:1;
--		uint32_t reserved:30;
--	} bits;
--};
--
--union ds_gamut_spaces {
--	uint32_t u32all;
--	struct {
--		uint32_t GAMUT_SPACE_CCIR709:1;
--		uint32_t GAMUT_SPACE_CCIR601:1;
--		uint32_t GAMUT_SPACE_ADOBERGB:1;
--		uint32_t GAMUT_SPACE_CIERGB:1;
--		uint32_t GAMUT_SPACE_CUSTOM:1;
--		uint32_t reserved:27;
--	} bits;
--};
--
--union ds_gamut_white_point {
--	uint32_t u32all;
--	struct {
--		uint32_t GAMUT_WHITE_POINT_5000:1;
--		uint32_t GAMUT_WHITE_POINT_6500:1;
--		uint32_t GAMUT_WHITE_POINT_7500:1;
--		uint32_t GAMUT_WHITE_POINT_9300:1;
--		uint32_t GAMUT_WHITE_POINT_CUSTOM:1;
--		uint32_t reserved:27;
--	} bits;
--};
--
--struct ds_gamut_space_coordinates {
--	int32_t red_x;
--	int32_t red_y;
--	int32_t green_x;
--	int32_t green_y;
--	int32_t blue_x;
--	int32_t blue_y;
--
--};
--
--struct ds_white_point_coordinates {
--	int32_t white_x;
--	int32_t white_y;
--};
--
--struct ds_gamut_data {
--	union ds_custom_gamut_type feature;
--	union {
--		uint32_t predefined;
--		struct ds_white_point_coordinates custom;
--
--	} white_point;
--
--	union {
--		uint32_t predefined;
--		struct ds_gamut_space_coordinates custom;
--
--	} gamut;
--};
--
--struct ds_set_gamut_data {
--	struct ds_gamut_reference_data ref;
--	struct ds_gamut_data gamut;
--
--};
--
--struct ds_get_gamut_data {
--	struct ds_gamut_data gamut;
--};
--
--struct ds_gamut_info {
--/*mask of supported predefined gamuts ,started from DI_GAMUT_SPACE_CCIR709 ...*/
--	union ds_gamut_spaces gamut_space;
--/*mask of supported predefined white points,started from DI_WHITE_POINT_5000K */
--	union ds_gamut_white_point white_point;
--
--};
--
--union ds_regamma_flags {
--	uint32_t u32all;
--	struct {
--		/*custom/user gamam array is in use*/
--		uint32_t GAMMA_RAMP_ARRAY:1;
--		/*gamma from edid is in use*/
--		uint32_t GAMMA_FROM_EDID:1;
--		/*gamma from edid is in use , but only for Display Id 1.2*/
--		uint32_t GAMMA_FROM_EDID_EX:1;
--		/*user custom gamma is in use*/
--		uint32_t GAMMA_FROM_USER:1;
--		/*coeff. A0-A3 from user is in use*/
--		uint32_t COEFF_FROM_USER:1;
--		/*coeff. A0-A3 from edid is in use only for Display Id 1.2*/
--		uint32_t COEFF_FROM_EDID:1;
--		/*which ROM to choose for graphics*/
--		uint32_t GRAPHICS_DEGAMMA_SRGB:1;
--		/*which ROM to choose for video overlay*/
--		uint32_t OVERLAY_DEGAMMA_SRGB:1;
--		/*apply degamma removal in driver*/
--		uint32_t APPLY_DEGAMMA:1;
--
--		uint32_t reserved:23;
--	} bits;
--};
--
--struct ds_regamma_ramp {
--	uint16_t gamma[256 * 3]; /* gamma ramp packed as RGB */
--
--};
--
--struct ds_regamma_coefficients_ex {
--	int32_t gamma[3];/*2400 use divider 1 000*/
--	int32_t coeff_a0[3];/*31308 divider 10 000 000,0-red, 1-green, 2-blue*/
--	int32_t coeff_a1[3];/*12920 use divider 1 000*/
--	int32_t coeff_a2[3];/*55 use divider 1 000*/
--	int32_t coeff_a3[3];/*55 use divider 1 000*/
--};
--
--struct ds_regamma_lut {
--	union ds_regamma_flags flags;
--	union {
--		struct ds_regamma_ramp gamma;
--		struct ds_regamma_coefficients_ex coeff;
--	};
--};
--
--enum ds_backlight_optimization {
--	DS_BACKLIGHT_OPTIMIZATION_DISABLE = 0,
--	DS_BACKLIGHT_OPTIMIZATION_DESKTOP,
--	DS_BACKLIGHT_OPTIMIZATION_DYNAMIC,
--	DS_BACKLIGHT_OPTIMIZATION_DIMMED
--};
--
--struct ds_adj_id_value {
--	enum adjustment_id adj_id;
--	enum adjustment_data_type adj_type;
--	union adjustment_property adj_prop;
--	int32_t value;
--};
--
--struct gamut_data {
--	union ds_custom_gamut_type option;
--	union {
--		union ds_gamut_white_point predefined;
--		struct ds_white_point_coordinates custom;
--
--	} white_point;
--
--	union {
--		union ds_gamut_spaces predefined;
--		struct ds_gamut_space_coordinates custom;
--
--	} gamut;
--};
--#endif /* __DAL_ADJUSTMENT_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h b/drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
-deleted file mode 100644
-index cfae832..0000000
---- a/drivers/gpu/drm/amd/dal/include/hw_adjustment_types.h
-+++ /dev/null
-@@ -1,205 +0,0 @@
--#ifndef __DAL_HW_ADJUSTMENT_TYPES_H__
--#define __DAL_HW_ADJUSTMENT_TYPES_H__
--
--#include "hw_sequencer_types.h"
--
--enum hw_adjustment_id {
--	HW_ADJUSTMENT_ID_COLOR_CONTROL,
--	HW_ADJUSTMENT_ID_GAMMA_LUT,
--	HW_ADJUSTMENT_ID_GAMMA_RAMP,
--	HW_ADJUSTMENT_ID_DEFLICKER,
--	HW_ADJUSTMENT_ID_SHARPNESS_CONTROL,
--	HW_ADJUSTMENT_ID_TIMING,
--	HW_ADJUSTMENT_ID_TIMING_AND_PIXEL_CLOCK,
--	HW_ADJUSTMENT_ID_OVERSCAN,
--	HW_ADJUSTMENT_ID_UNDERSCAN_TYPE,
--	HW_ADJUSTMENT_ID_VERTICAL_SYNC,
--	HW_ADJUSTMENT_ID_HORIZONTAL_SYNC,
--	HW_ADJUSTMENT_ID_COMPOSITE_SYNC,
--	HW_ADJUSTMENT_ID_VIDEO_STANDARD,
--	HW_ADJUSTMENT_ID_BACKLIGHT,
--	HW_ADJUSTMENT_ID_BIT_DEPTH_REDUCTION,
--	HW_ADJUSTMENT_ID_REDUCED_BLANKING,
--	HW_ADJUSTMENT_ID_COHERENT,
--	/* OVERLAY ADJUSTMENTS*/
--	HW_ADJUSTMENT_ID_OVERLAY,
--	HW_ADJUSTMENT_ID_OVERLAY_ALPHA,
--	HW_ADJUSTMENT_ID_OVERLAY_VARIABLE_GAMMA,
--	HW_ADJUSTMENT_ID_COUNT,
--	HW_ADJUSTMENT_ID_UNDEFINED,
--};
--
--struct hw_adjustment_deflicker {
--	int32_t hp_factor;
--	uint32_t hp_divider;
--	int32_t lp_factor;
--	uint32_t lp_divider;
--	int32_t sharpness;
--	bool enable_sharpening;
--};
--
--struct hw_adjustment_value {
--	union {
--		uint32_t ui_value;
--		int32_t i_value;
--	};
--};
--
--enum hw_color_adjust_option {
--	HWS_COLOR_MATRIX_HW_DEFAULT = 1,
--	HWS_COLOR_MATRIX_SW
--};
--
--enum {
--	HW_TEMPERATURE_MATRIX_SIZE = 9,
--	HW_TEMPERATURE_MATRIX_SIZE_WITH_OFFSET = 12
--};
--
--struct hw_adjustment_color_control {
--	enum hw_color_space color_space;
--	enum hw_color_adjust_option option;
--	enum pixel_format surface_pixel_format;
--	enum dc_color_depth color_depth;
--	uint32_t lb_color_depth;
--	int32_t contrast;
--	int32_t saturation;
--	int32_t brightness;
--	int32_t hue;
--	uint32_t adjust_divider;
--	uint32_t temperature_divider;
--	uint32_t temperature_matrix[HW_TEMPERATURE_MATRIX_SIZE];
--};
--
--struct hw_underscan_adjustment {
--	struct hw_adjustment_deflicker deflicker;
--	struct overscan_info hw_overscan;
--};
--
--struct hw_underscan_adjustment_data {
--	enum hw_adjustment_id hw_adj_id;
--	struct hw_underscan_adjustment hw_underscan_adj;
--};
--
--union hw_adjustment_bit_depth_reduction {
--	uint32_t raw;
--	struct {
--		uint32_t TRUNCATE_ENABLED:1;
--		uint32_t TRUNCATE_DEPTH:2;
--		uint32_t TRUNCATE_MODE:1;
--		uint32_t SPATIAL_DITHER_ENABLED:1;
--		uint32_t SPATIAL_DITHER_DEPTH:2;
--		uint32_t SPATIAL_DITHER_MODE:2;
--		uint32_t RGB_RANDOM:1;
--		uint32_t FRAME_RANDOM:1;
--		uint32_t HIGHPASS_RANDOM:1;
--		uint32_t FRAME_MODULATION_ENABLED:1;
--		uint32_t FRAME_MODULATION_DEPTH:2;
--		uint32_t TEMPORAL_LEVEL:1;
--		uint32_t FRC_25:2;
--		uint32_t FRC_50:2;
--		uint32_t FRC_75:2;
--	} bits;
--};
--
--struct hw_color_control_range {
--	struct hw_adjustment_range contrast;
--	struct hw_adjustment_range saturation;
--	struct hw_adjustment_range brightness;
--	struct hw_adjustment_range hue;
--	struct hw_adjustment_range temperature;
--};
--
--enum hw_surface_type {
--	HW_OVERLAY_SURFACE = 1,
--	HW_GRAPHIC_SURFACE
--};
--
--/* LUT type for GammaCorrection */
--struct hw_gamma_lut {
--	uint32_t red;
--	uint32_t green;
--	uint32_t blue;
--};
--
--struct hw_devc_lut {
--	uint8_t red;
--	uint8_t green;
--	uint8_t blue;
--	uint8_t reserved;
--};
--
--struct hw_adjustment_gamma_lut {
--	struct hw_gamma_lut *pGammaLut;
--	uint32_t size_in_elements;
--	enum pixel_format surface_pixel_format;
--};
--
--
--enum hw_gamma_ramp_type {
--	HW_GAMMA_RAMP_UNITIALIZED = 0,
--	HW_GAMMA_RAMP_DEFAULT,
--	HW_GAMMA_RAMP_RBG_256x3x16,
--	HW_GAMMA_RAMP_RBG_DXGI_1
--};
--
--#define HW_GAMMA_RAMP_RBG_256 256
--
--struct hw_gamma_ramp_rgb256x3x16 {
--	unsigned short red[HW_GAMMA_RAMP_RBG_256];
--	unsigned short green[HW_GAMMA_RAMP_RBG_256];
--	unsigned short blue[HW_GAMMA_RAMP_RBG_256];
--};
--
--union hw_gamma_flags {
--	uint32_t raw;
--	struct {
--		uint32_t gamma_ramp_array :1;
--		uint32_t graphics_degamma_srgb :1;
--		uint32_t overlay_degamma_srgb :1;
--		uint32_t apply_degamma :1;
--		uint32_t reserved :28;
--	} bits;
--};
--
--struct hw_regamma_coefficients {
--	int32_t gamma[3];
--	int32_t a0[3];
--	int32_t a1[3];
--	int32_t a2[3];
--	int32_t a3[3];
--};
--
--struct hw_regamma_ramp {
--	/* Gamma ramp packed as RGB */
--	unsigned short gamma[256 * 3];
--};
--
--struct hw_regamma_lut {
--	union hw_gamma_flags flags;
--	union {
--		struct hw_regamma_ramp gamma;
--		struct hw_regamma_coefficients coeff;
--	};
--};
--
--union hw_gamma_flag {
--	uint32_t uint;
--	struct {
--		uint32_t config_is_changed :1;
--		uint32_t regamma_update :1;
--		uint32_t gamma_update :1;
--		uint32_t reserved :29;
--	} bits;
--};
--
--struct hw_adjustment_gamma_ramp {
--	uint32_t size;
--	enum hw_gamma_ramp_type type;
--	enum pixel_format surface_pixel_format;
--	enum hw_color_space color_space;
--	struct hw_regamma_lut regamma;
--	union hw_gamma_flag flag;
--	struct hw_gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
--};
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_types.h b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-index 3647815..a7d8119 100644
---- a/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-@@ -26,21 +26,9 @@
- #ifndef __DAL_SET_MODE_TYPES_H__
- #define __DAL_SET_MODE_TYPES_H__
- 
--#include "adjustment_types.h"
--#include "hw_adjustment_types.h"
- #include "include/plane_types.h"
- #include "dc_types.h"
- 
--/* Forward declaration */
--struct dc_mode_timing;
--struct display_path;
--
--/* State of stereo 3D for workstation */
--enum ws_stereo_state {
--	WS_STEREO_STATE_INACTIVE = 0,
--	WS_STEREO_STATE_ACTIVE,
--	WS_STEREO_STATE_ACTIVE_MASTER
--};
- 
- /* GTC group number */
- enum gtc_group {
-@@ -54,26 +42,6 @@ enum gtc_group {
- 	GTC_GROUP_MAX
- };
- 
--/* Adjustment action*/
--enum adjustment_action {
--	ADJUSTMENT_ACTION_UNDEFINED = 0,
--	ADJUSTMENT_ACTION_VALIDATE,
--	ADJUSTMENT_ACTION_SET_ADJUSTMENT
--};
--
--/* Type of adjustment parameters*/
--enum adjustment_par_type {
--	ADJUSTMENT_PAR_TYPE_NONE = 0,
--	ADJUSTMENT_PAR_TYPE_TIMING,
--	ADJUSTMENT_PAR_TYPE_MODE
--};
--
--/* Method of validation */
--enum validation_method {
--	VALIDATION_METHOD_STATIC = 0,
--	VALIDATION_METHOD_DYNAMIC
--};
--
- /* Info frame packet status */
- enum info_frame_flag {
- 	INFO_PACKET_PACKET_INVALID = 0,
-@@ -103,102 +71,6 @@ enum info_frame_size {
- 	INFO_FRAME_SIZE_AUDIO = 10
- };
- 
--/* Active format */
--enum active_format_info {
--	ACTIVE_FORMAT_NO_DATA = 0,
--	ACTIVE_FORMAT_VALID = 1
--};
--/* Bar info */
--enum bar_info {
--	BAR_INFO_NOT_VALID = 0,
--	BAR_INFO_VERTICAL_VALID = 1,
--	BAR_INFO_HORIZONTAL_VALID = 2,
--	BAR_INFO_BOTH_VALID = 3
--};
--
--/* Picture scaling */
--enum picture_scaling {
--	PICTURE_SCALING_UNIFORM = 0,
--	PICTURE_SCALING_HORIZONTAL = 1,
--	PICTURE_SCALING_VERTICAL = 2,
--	PICTURE_SCALING_BOTH = 3
--};
--
--/* Colorimetry */
--enum colorimetry {
--	COLORIMETRY_NO_DATA = 0,
--	COLORIMETRY_ITU601 = 1,
--	COLORIMETRY_ITU709 = 2,
--	COLORIMETRY_EXTENDED = 3
--};
--
--/* ColorimetryEx */
--enum colorimetry_ex {
--	COLORIMETRY_EX_XVYCC601 = 0,
--	COLORIMETRY_EX_XVYCC709 = 1,
--	COLORIMETRY_EX_SYCC601 = 2,
--	COLORIMETRY_EX_ADOBEYCC601 = 3,
--	COLORIMETRY_EX_ADOBERGB = 4,
--	COLORIMETRY_EX_RESERVED5 = 5,
--	COLORIMETRY_EX_RESERVED6 = 6,
--	COLORIMETRY_EX_RESERVED7 = 7
--};
--
--/* Active format aspect ratio */
--enum active_format_aspect_ratio {
--	ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
--	ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
--	ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
--	ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
--};
--
--/* RGB quantization range */
--enum rgb_quantization_range {
--	RGB_QUANTIZATION_DEFAULT_RANGE = 0,
--	RGB_QUANTIZATION_LIMITED_RANGE = 1,
--	RGB_QUANTIZATION_FULL_RANGE = 2,
--	RGB_QUANTIZATION_RESERVED = 3
--};
--
--/* YYC quantization range */
--enum yyc_quantization_range {
--	YYC_QUANTIZATION_LIMITED_RANGE = 0,
--	YYC_QUANTIZATION_FULL_RANGE = 1,
--	YYC_QUANTIZATION_RESERVED2 = 2,
--	YYC_QUANTIZATION_RESERVED3 = 3
--};
--
--/* Rotation capability */
--struct rotation_capability {
--	bool ROTATION_ANGLE_0_CAP:1;
--	bool ROTATION_ANGLE_90_CAP:1;
--	bool ROTATION_ANGLE_180_CAP:1;
--	bool ROTATION_ANGLE_270_CAP:1;
--};
--
--/* Underscan position and size */
--struct ds_underscan_desc {
--	uint32_t x;
--	uint32_t y;
--	uint32_t width;
--	uint32_t height;
--};
--
--/* View, timing and other mode related information */
--struct path_mode {
--	struct view view;
--	struct rect_position view_position;
--	enum view_3d_format view_3d_format;
--	const struct dc_mode_timing *mode_timing;
--	enum scaling_transformation scaling;
--	enum pixel_format pixel_format;
--	uint32_t display_path_index;
--	enum tiling_mode tiling_mode;
--	enum dc_rotation_angle rotation_angle;
--	bool is_tiling_rotated;
--	struct rotation_capability rotation_capability;
--};
--
- struct hdmi_info_frame_header {
- 	uint8_t info_frame_type;
- 	uint8_t version;
-@@ -207,6 +79,7 @@ struct hdmi_info_frame_header {
- 
- #pragma pack(push)
- #pragma pack(1)
-+
- struct info_packet_raw_data {
- 	uint8_t hb0;
- 	uint8_t hb1;
-@@ -264,21 +137,6 @@ struct info_frame {
- };
- 
- 
--/* Adjustment parameter */
--struct adjustment_parameters {
--	enum adjustment_par_type type;
--	struct {
--		enum adjustment_id ajd_id;
--		enum hw_adjustment_id adj_id_hw;
--	} timings;
--};
--
--/* Parameters for adjustments*/
--struct adjustment_params {
--	enum adjustment_action action;
--	struct adjustment_parameters params;
--	const struct display_path *affected_path;
--};
- 
- #pragma pack(pop)
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch b/common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch
deleted file mode 100644
index afae08d7..00000000
--- a/common/recipes-kernel/linux/files/0723-drm-amd-dal-dc-clean-up-remove-dvo-related.patch
+++ /dev/null
@@ -1,1791 +0,0 @@
-From ea839f5eb154581fccd3db4b8878a251802e15b5 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 29 Jan 2016 15:36:48 -0500
-Subject: [PATCH 0723/1110] drm/amd/dal: dc clean up - remove dvo related
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      |  69 +----
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    | 111 -------
- drivers/gpu/drm/amd/dal/dc/bios/command_table.h    |   3 -
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |  37 ---
- .../dc/bios/dce110/command_table_helper_dce110.c   |   4 -
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |   3 -
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/Makefile           |   2 +-
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c |   4 -
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c   |  40 ---
- .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c  |   5 -
- drivers/gpu/drm/amd/dal/dc/gpio/dvo.c              | 138 ---------
- drivers/gpu/drm/amd/dal/dc/gpio/dvo.h              |  42 ---
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     |  88 ------
- drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c           | 318 ---------------------
- drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h           |  89 ------
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h       |   4 -
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |  11 +-
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.c    |   4 +-
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c  |   1 -
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c  |   3 -
- drivers/gpu/drm/amd/dal/include/audio_types.h      |   1 -
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |  31 --
- .../gpu/drm/amd/dal/include/clock_source_types.h   |   5 -
- .../drm/amd/dal/include/display_clock_interface.h  |   1 -
- drivers/gpu/drm/amd/dal/include/dvo_interface.h    |  48 ----
- .../drm/amd/dal/include/gpio_service_interface.h   |  14 -
- drivers/gpu/drm/amd/dal/include/gpio_types.h       |  54 +---
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    |   7 -
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   |  21 --
- 30 files changed, 12 insertions(+), 1149 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/dvo_interface.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 3ca165b..8d675f0 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -1295,18 +1295,6 @@ static enum bp_result bios_parser_get_divider_for_target_display_clock(
- 	return bp->cmd_tbl.compute_memore_engine_pll(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_dvo_encoder_control(
--	struct dc_bios *dcb,
--	struct bp_dvo_encoder_control *cntl)
--{
--	struct bios_parser *bp = BP_FROM_DCB(dcb);
--
--	if (!bp->cmd_tbl.dvo_encoder_control)
--		return BP_RESULT_FAILURE;
--
--	return bp->cmd_tbl.dvo_encoder_control(bp, cntl);
--}
--
- static enum bp_result bios_parser_enable_crtc(
- 	struct dc_bios *dcb,
- 	enum controller_id id,
-@@ -3143,78 +3131,27 @@ static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
- 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
- 		id = ENCODER_ID_INTERNAL_DAC2;
- 		break;
--	case ENCODER_OBJECT_ID_INTERNAL_SDVOA:
--		id = ENCODER_ID_INTERNAL_SDVOA;
--		break;
--	case ENCODER_OBJECT_ID_INTERNAL_SDVOB:
--		id = ENCODER_ID_INTERNAL_SDVOB;
--		break;
--	case ENCODER_OBJECT_ID_SI170B:
--		id = ENCODER_ID_EXTERNAL_SI170B;
--		break;
--	case ENCODER_OBJECT_ID_CH7303:
--		id = ENCODER_ID_EXTERNAL_CH7303;
--		break;
--	case ENCODER_OBJECT_ID_CH7301:
--		id = ENCODER_ID_EXTERNAL_CH7301;
--		break;
--	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
--		id = ENCODER_ID_INTERNAL_DVO1;
--		break;
--	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
--		id = ENCODER_ID_EXTERNAL_SDVOA;
--		break;
--	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
--		id = ENCODER_ID_EXTERNAL_SDVOB;
--		break;
--	case ENCODER_OBJECT_ID_TITFP513:
--		id = ENCODER_ID_EXTERNAL_TITFP513;
--		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
- 		id = ENCODER_ID_INTERNAL_LVTM1;
- 		break;
--	case ENCODER_OBJECT_ID_VT1623:
--		id = ENCODER_ID_EXTERNAL_VT1623;
--		break;
--	case ENCODER_OBJECT_ID_HDMI_SI1930:
--		id = ENCODER_ID_EXTERNAL_SI1930;
--		break;
- 	case ENCODER_OBJECT_ID_HDMI_INTERNAL:
- 		id = ENCODER_ID_INTERNAL_HDMI;
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
- 		id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
- 		break;
--	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
--		id = ENCODER_ID_INTERNAL_KLDSCP_DVO1;
--		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- 		id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- 		id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
- 		break;
--	case ENCODER_OBJECT_ID_SI178:
--		id = ENCODER_ID_EXTERNAL_SI178;
--		break;
- 	case ENCODER_OBJECT_ID_MVPU_FPGA:
- 		id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
- 		id = ENCODER_ID_INTERNAL_DDI;
- 		break;
--	case ENCODER_OBJECT_ID_VT1625:
--		id = ENCODER_ID_EXTERNAL_VT1625;
--		break;
--	case ENCODER_OBJECT_ID_HDMI_SI1932:
--		id = ENCODER_ID_EXTERNAL_SI1932;
--		break;
--	case ENCODER_OBJECT_ID_DP_AN9801:
--		id = ENCODER_ID_EXTERNAL_AN9801;
--		break;
--	case ENCODER_OBJECT_ID_DP_DP501:
--		id = ENCODER_ID_EXTERNAL_DP501;
--		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- 		id = ENCODER_ID_INTERNAL_UNIPHY;
- 		break;
-@@ -3227,9 +3164,6 @@ static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
- 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- 		id = ENCODER_ID_INTERNAL_UNIPHY2;
- 		break;
--	case ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO:
--		id = ENCODER_ID_EXTERNAL_GENERIC_DVO;
--		break;
- 	case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
- 		id = ENCODER_ID_EXTERNAL_NUTMEG;
- 		break;
-@@ -3241,6 +3175,7 @@ static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
- 		break;
- 	default:
- 		id = ENCODER_ID_UNKNOWN;
-+		ASSERT(0);
- 		break;
- 	}
- 
-@@ -4966,8 +4901,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
- 
- 	.crt_control = bios_parser_crt_control,
- 
--	.dvo_encoder_control = bios_parser_dvo_encoder_control,
--
- 	.enable_crtc = bios_parser_enable_crtc,
- 
- 	.adjust_pixel_clock = bios_parser_adjust_pixel_clock,
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index 87fc14b..cba54f3 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -49,7 +49,6 @@
- 
- 
- static void init_dig_encoder_control(struct bios_parser *bp);
--static void init_dvo_encoder_control(struct bios_parser *bp);
- static void init_transmitter_control(struct bios_parser *bp);
- static void init_set_pixel_clock(struct bios_parser *bp);
- static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
-@@ -72,7 +71,6 @@ static void init_set_dce_clock(struct bios_parser *bp);
- void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
- {
- 	init_dig_encoder_control(bp);
--	init_dvo_encoder_control(bp);
- 	init_transmitter_control(bp);
- 	init_set_pixel_clock(bp);
- 	init_enable_spread_spectrum_on_ppll(bp);
-@@ -309,65 +307,6 @@ static enum bp_result encoder_control_digx_v4(
- /*******************************************************************************
-  ********************************************************************************
-  **
-- **                 DVO ENCODER CONTROL
-- **
-- ********************************************************************************
-- *******************************************************************************/
--
--static enum bp_result dvo_encoder_control_v3(
--	struct bios_parser *bp,
--	struct bp_dvo_encoder_control *cntl);
--
--static void init_dvo_encoder_control(struct bios_parser *bp)
--{
--	switch (BIOS_CMD_TABLE_PARA_REVISION(DVOEncoderControl)) {
--	case 3:
--		bp->cmd_tbl.dvo_encoder_control = dvo_encoder_control_v3;
--		break;
--	default:
--		bp->cmd_tbl.dvo_encoder_control = NULL;
--		break;
--	}
--}
--
--static enum bp_result dvo_encoder_control_v3(
--	struct bios_parser *bp,
--	struct bp_dvo_encoder_control *cntl)
--{
--	enum bp_result result = BP_RESULT_FAILURE;
--	DVO_ENCODER_CONTROL_PARAMETERS_V3 params;
--	uint8_t config = 0;
--
--	if (cntl->memory_rate == DVO_ENCODER_MEMORY_RATE_SDR)
--		config |= DVO_ENCODER_CONFIG_SDR_SPEED;
--
--	switch (cntl->interface_width) {
--	case DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT:
--		config |= DVO_ENCODER_CONFIG_24BIT;
--		break;
--	case DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT:
--		config |= DVO_ENCODER_CONFIG_UPPER12BIT;
--		break;
--	default:
--		config |= DVO_ENCODER_CONFIG_LOW12BIT;
--		break;
--	}
--
--	/* We need to convert from KHz units into 10KHz units */
--	dc_service_memset(&params, 0, sizeof(params));
--	params.ucAction = (uint8_t) cntl->action;
--	params.usPixelClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
--	params.ucDVOConfig = config;
--
--	if (EXEC_BIOS_CMD_TABLE(DVOEncoderControl, params))
--		result = BP_RESULT_OK;
--
--	return result;
--}
--
--/*******************************************************************************
-- ********************************************************************************
-- **
-  **                  TRANSMITTER CONTROL
-  **
-  ********************************************************************************
-@@ -1515,17 +1454,6 @@ static void init_adjust_display_pll(struct bios_parser *bp)
- 	}
- }
- 
--static bool adjust_display_pll_bug_patch(ADJUST_DISPLAY_PLL_PARAMETERS *params)
--{
--	/* vbios bug: pixel clock should not be doubled for DVO with 24bit
--	 * interface */
--	if ((params->ucTransmitterID == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
--			&& (params->ucDVOConfig == DVO_ENCODER_CONFIG_24BIT))
--		/* the current pixel clock is good. no adjustment is required */
--		return true;
--	return false;
--}
--
- static enum bp_result adjust_display_pll_v2(
- 	struct bios_parser *bp,
- 	struct bp_adjust_pixel_clock_parameters *bp_params)
-@@ -1545,23 +1473,6 @@ static enum bp_result adjust_display_pll_v2(
- 	params.ucEncodeMode =
- 			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
- 					bp_params->signal_type, false);
--	params.ucDVOConfig = (uint8_t)(bp_params->dvo_config);
--
--	if (adjust_display_pll_bug_patch(&params)
--			|| EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
--		/* Convert output pixel clock back 10KHz-->KHz: multiply
--		 * original pixel clock in KHz by ratio
--		 * [output pxlClk/input pxlClk] */
--		uint64_t pixel_clock_10KHz_out =
--				le16_to_cpu((uint64_t)params.usPixelClock);
--		uint64_t pixel_clock = (uint64_t)bp_params->pixel_clock;
--
--		bp_params->adjusted_pixel_clock =
--				div_u64(pixel_clock * pixel_clock_10KHz_out,
--						pixel_clock_10KHz_in);
--		result = BP_RESULT_OK;
--	}
--
- 	return result;
- }
- 
-@@ -1586,25 +1497,6 @@ static enum bp_result adjust_display_pll_v3(
- 			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
- 					bp_params->signal_type, false);
- 
--	if (DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT ==
--			bp_params->display_pll_config)
--		params.sInput.ucDispPllConfig =
--				DISPPLL_CONFIG_DVO_DDR_SPEED |
--				DISPPLL_CONFIG_DVO_LOW12BIT;
--	else if (DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT ==
--			bp_params->display_pll_config)
--		params.sInput.ucDispPllConfig =
--				DISPPLL_CONFIG_DVO_DDR_SPEED |
--				DISPPLL_CONFIG_DVO_UPPER12BIT;
--	else if (DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT ==
--			bp_params->display_pll_config)
--		params.sInput.ucDispPllConfig =
--				DISPPLL_CONFIG_DVO_DDR_SPEED | DISPPLL_CONFIG_DVO_24BIT;
--	else
--		/* this does not mean anything here */
--		params.sInput.ucDispPllConfig =
--				(uint8_t)(bp_params->display_pll_config);
--
- 	if (bp_params->ss_enable == true)
- 		params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
- 
-@@ -1873,9 +1765,6 @@ static enum signal_type dac_load_detection_v3(
- 	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
- 		params.sDacload.ucDacType = ATOM_DAC_B;
- 		break;
--	case ENCODER_ID_EXTERNAL_CH7303:
--		params.sDacload.ucDacType = ATOM_EXT_DAC;
--		break;
- 	default:
- 		return signal;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-index e233ea6..3cb0c7f 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.h
-@@ -39,9 +39,6 @@ struct cmd_tbl {
- 	enum bp_result (*encoder_control_dig2)(
- 		struct bios_parser *bp,
- 		struct bp_encoder_control *control);
--	enum bp_result (*dvo_encoder_control)(
--		struct bios_parser *bp,
--		struct bp_dvo_encoder_control *cntl);
- 	enum bp_result (*transmitter_control)(
- 		struct bios_parser *bp,
- 		struct bp_transmitter_control *control);
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index 83a80d5..36d1240 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -245,30 +245,8 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
- 		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
- 	case ENCODER_ID_INTERNAL_DAC2:
- 		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
--	case ENCODER_ID_INTERNAL_SDVOA:
--		return ENCODER_OBJECT_ID_INTERNAL_SDVOA;
--	case ENCODER_ID_INTERNAL_SDVOB:
--		return ENCODER_OBJECT_ID_INTERNAL_SDVOB;
--	case ENCODER_ID_EXTERNAL_SI170B:
--		return ENCODER_OBJECT_ID_SI170B;
--	case ENCODER_ID_EXTERNAL_CH7303:
--		return ENCODER_OBJECT_ID_CH7303;
--	case ENCODER_ID_EXTERNAL_CH7301:
--		return ENCODER_OBJECT_ID_CH7301;
--	case ENCODER_ID_INTERNAL_DVO1:
--		return ENCODER_OBJECT_ID_INTERNAL_DVO1;
--	case ENCODER_ID_EXTERNAL_SDVOA:
--		return ENCODER_OBJECT_ID_EXTERNAL_SDVOA;
--	case ENCODER_ID_EXTERNAL_SDVOB:
--		return ENCODER_OBJECT_ID_EXTERNAL_SDVOB;
--	case ENCODER_ID_EXTERNAL_TITFP513:
--		return ENCODER_OBJECT_ID_TITFP513;
- 	case ENCODER_ID_INTERNAL_LVTM1:
- 		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
--	case ENCODER_ID_EXTERNAL_VT1623:
--		return ENCODER_OBJECT_ID_VT1623;
--	case ENCODER_ID_EXTERNAL_SI1930:
--		return ENCODER_OBJECT_ID_HDMI_SI1930;
- 	case ENCODER_ID_INTERNAL_HDMI:
- 		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
- 	case ENCODER_ID_EXTERNAL_TRAVIS:
-@@ -277,26 +255,14 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
- 		return ENCODER_OBJECT_ID_NUTMEG;
- 	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
- 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
--	case ENCODER_ID_INTERNAL_KLDSCP_DVO1:
--		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
- 	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
- 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
- 	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
- 		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
--	case ENCODER_ID_EXTERNAL_SI178:
--		return ENCODER_OBJECT_ID_SI178;
- 	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
- 		return ENCODER_OBJECT_ID_MVPU_FPGA;
- 	case ENCODER_ID_INTERNAL_DDI:
- 		return ENCODER_OBJECT_ID_INTERNAL_DDI;
--	case ENCODER_ID_EXTERNAL_VT1625:
--		return ENCODER_OBJECT_ID_VT1625;
--	case ENCODER_ID_EXTERNAL_SI1932:
--		return ENCODER_OBJECT_ID_HDMI_SI1932;
--	case ENCODER_ID_EXTERNAL_AN9801:
--		return ENCODER_OBJECT_ID_DP_AN9801;
--	case ENCODER_ID_EXTERNAL_DP501:
--		return ENCODER_OBJECT_ID_DP_DP501;
- 	case ENCODER_ID_INTERNAL_UNIPHY:
- 		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
- 	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
-@@ -309,9 +275,6 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(
- 		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
- 	case ENCODER_ID_INTERNAL_WIRELESS:
- 		return ENCODER_OBJECT_ID_INTERNAL_VCE;
--	case ENCODER_ID_EXTERNAL_GENERIC_DVO:
--		return ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO;
--	case ENCODER_ID_INTERNAL_VIRTUAL:
- 	case ENCODER_ID_UNKNOWN:
- 		return ENCODER_OBJECT_ID_NONE;
- 	default:
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-index e75b51b..0319382 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-@@ -270,10 +270,6 @@ static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
- 			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
- 			result = true;
- 			break;
--		case ENGINE_ID_DVO:
--			*atom_engine_id = ASIC_EXT_DIG_ENCODER_ID;
--			result = true;
--			break;
- 		case ENGINE_ID_DACA:
- 			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
- 			result = true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index 0f85f63..53f0477 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -207,9 +207,6 @@ struct dc_vbios_funcs {
- 		enum engine_id engine_id,
- 		bool enable,
- 		uint32_t pixel_clock);
--	enum bp_result (*dvo_encoder_control)(
--		struct dc_bios *bios,
--		struct bp_dvo_encoder_control *cntl);
- 	enum bp_result (*enable_crtc)(
- 		struct dc_bios *bios,
- 		enum controller_id id,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index f899565..0eafe16 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1090,7 +1090,8 @@ static bool dc_set_clocks_and_clock_state (
- 	 * that state.
- 	 *
- 	 * Update the clock state here (prior to setting Pixel clock,
--	 * DVO clock, or Display clock) */
-+	 * or Display clock)
-+	 **/
- 	if (!dal_display_clock_set_min_clocks_state(
- 			disp_clk, context->res_ctx.required_clocks_state)) {
- 		BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-index 50a1d34..2507bb5 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'gpio' sub-component of DAL.
- # It provides the control and status of HW GPIO pins.
- 
--GPIO = ddc.o dvo.o gpio_base.o gpio_service.o hw_ddc.o hw_dvo.o hw_factory.o \
-+GPIO = ddc.o gpio_base.o gpio_service.o hw_ddc.o hw_factory.o \
-        hw_gpio.o hw_gpio_pad.o hw_gpio_pin.o hw_hpd.o hw_translate.o irq.o
- 
- AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-index 85644c5..55d6986 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-@@ -46,7 +46,6 @@
- 
- /* fucntion table */
- static const struct hw_factory_funcs funcs = {
--	.create_dvo = NULL,
- 	.create_ddc_data = dal_hw_ddc_dce110_create,
- 	.create_ddc_clock = dal_hw_ddc_dce110_create,
- 	.create_generic = NULL,
-@@ -68,9 +67,6 @@ static const struct hw_factory_funcs funcs = {
- void dal_hw_factory_dce110_init(struct hw_factory *factory)
- {
- 	/*TODO check ASIC CAPs*/
--	factory->number_of_pins[GPIO_ID_DVO1] = 24;
--	factory->number_of_pins[GPIO_ID_DVO12] = 2;
--	factory->number_of_pins[GPIO_ID_DVO24] = 1;
- 	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
- 	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
- 	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-index 05ac0b2..38512fa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-@@ -45,7 +45,6 @@
-  */
- 
- #include "../hw_gpio_pin.h"
--#include "../hw_dvo.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -57,26 +56,6 @@ static bool offset_to_id(
- 	uint32_t *en)
- {
- 	switch (offset) {
--	/* DVO */
--	case mmDC_GPIO_DVODATA_A:
--		switch (mask) {
--		case BUNDLE_A_MASK:
--			*id = GPIO_ID_DVO12;
--			*en = GPIO_DVO12_A;
--			return true;
--		case BUNDLE_B_MASK:
--			*id = GPIO_ID_DVO12;
--			*en = GPIO_DVO12_B;
--			return true;
--		case DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK:
--			*id = GPIO_ID_DVO24;
--			*en = 0;
--			return true;
--		default:
--			ASSERT_CRITICAL(false);
--			return false;
--		}
--	break;
- 	/* GENERIC */
- 	case mmDC_GPIO_GENERIC_A:
- 		*id = GPIO_ID_GENERIC;
-@@ -220,20 +199,6 @@ static bool id_to_offset(
- 	bool result = true;
- 
- 	switch (id) {
--	case GPIO_ID_DVO12:
--		info->offset = mmDC_GPIO_DVODATA_A;
--		switch (en) {
--		case GPIO_DVO12_A:
--			info->mask = BUNDLE_A_MASK;
--		break;
--		case GPIO_DVO12_B:
--			info->mask = BUNDLE_B_MASK;
--		break;
--		default:
--			ASSERT_CRITICAL(false);
--			result = false;
--		}
--	break;
- 	case GPIO_ID_DDC_DATA:
- 		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
- 		switch (en) {
-@@ -394,11 +359,6 @@ static bool id_to_offset(
- 			result = false;
- 		}
- 	break;
--	case GPIO_ID_DVO24:
--		info->offset = mmDC_GPIO_DVODATA_A;
--		info->mask = DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK;
--	break;
--	case GPIO_ID_DVO1:
- 	case GPIO_ID_VIP_PAD:
- 	default:
- 		ASSERT_CRITICAL(false);
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-index 13b69e2..59503c4 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-@@ -42,7 +42,6 @@
- 
- /* function table */
- static const struct hw_factory_funcs funcs = {
--	.create_dvo = NULL,
- 	.create_ddc_data = NULL,
- 	.create_ddc_clock = NULL,
- 	.create_generic = NULL,
-@@ -54,9 +53,6 @@ static const struct hw_factory_funcs funcs = {
- 
- void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
- {
--	factory->number_of_pins[GPIO_ID_DVO1] = 24;
--	factory->number_of_pins[GPIO_ID_DVO12] = 2;
--	factory->number_of_pins[GPIO_ID_DVO24] = 1;
- 	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
- 	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
- 	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-@@ -65,6 +61,5 @@ void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
- 	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
- 	factory->number_of_pins[GPIO_ID_SYNC] = 2;
- 	factory->number_of_pins[GPIO_ID_GSL] = 4;
--
- 	factory->funcs = &funcs;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
-deleted file mode 100644
-index a237d25..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.c
-+++ /dev/null
-@@ -1,138 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dal_services.h"
--
--/*
-- * Pre-requisites: headers required by header of this unit
-- */
--
--#include "include/gpio_interface.h"
--#include "include/dvo_interface.h"
--#include "include/gpio_service_interface.h"
--#include "hw_gpio_pin.h"
--#include "hw_translate.h"
--#include "hw_factory.h"
--#include "gpio_service.h"
--#include "gpio.h"
--
--/*
-- * Header of this unit
-- */
--
--#include "dvo.h"
--
--/*
-- * Post-requisites: headers required by this unit
-- */
--
--/*
-- * This unit
-- */
--
--enum gpio_result dal_dvo_open(
--	struct dvo *dvo,
--	enum gpio_mode mode)
--{
--	return dal_gpio_open(dvo->pin, mode);
--}
--
--enum gpio_result dal_dvo_get_value(
--	const struct dvo *dvo,
--	uint32_t *value)
--{
--	return dal_gpio_get_value(dvo->pin, value);
--}
--
--enum gpio_result dal_dvo_set_value(
--	const struct dvo *dvo,
--	uint32_t value)
--{
--	return dal_gpio_set_value(dvo->pin, value);
--}
--
--void dal_dvo_close(
--	struct dvo *dvo)
--{
--	dal_gpio_close(dvo->pin);
--}
--
--/*
-- * @brief
-- * Creation and destruction
-- */
--
--struct dvo *dal_dvo_create(
--	struct gpio_service *service,
--	enum gpio_id id,
--	uint32_t en)
--{
--	struct dvo *dvo;
--
--	switch (id) {
--	case GPIO_ID_DVO12:
--		if ((en < GPIO_DVO12_MIN) || (en > GPIO_DVO12_MAX)) {
--			BREAK_TO_DEBUGGER();
--			return NULL;
--		}
--	break;
--	case GPIO_ID_DVO24:
--		if ((en < GPIO_DVO24_MIN) || (en > GPIO_DVO24_MAX)) {
--			BREAK_TO_DEBUGGER();
--			return NULL;
--		}
--	break;
--	default:
--		BREAK_TO_DEBUGGER();
--		return NULL;
--	}
--
--	dvo = dc_service_alloc(service->ctx, sizeof(struct dvo));
--
--	if (!dvo) {
--		BREAK_TO_DEBUGGER();
--		return NULL;
--	}
--
--	dvo->pin = NULL;
--	dvo->ctx = service->ctx;
--
--	return dvo;
--}
--
--void dal_dvo_destroy(
--	struct dvo **dvo)
--{
--	if (!dvo || !*dvo) {
--		BREAK_TO_DEBUGGER();
--		return;
--	}
--
--	dal_dvo_close(*dvo);
--
--	dc_service_free((*dvo)->ctx, *dvo);
--
--	*dvo = NULL;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h b/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
-deleted file mode 100644
-index 0d98b51..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dvo.h
-+++ /dev/null
-@@ -1,42 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_DVO_H__
--#define __DAL_DVO_H__
--
--struct dvo {
--	struct gpio *pin;
--	struct dc_context *ctx;
--};
--
--struct dvo *dal_dvo_create(
--	struct gpio_service *service,
--	enum gpio_id id,
--	uint32_t en);
--
--void dal_dvo_destroy(
--	struct dvo **dvo);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-index 3a6b5f4..0920545 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -30,8 +30,6 @@
- #include "dal_services.h"
- #include "include/gpio_interface.h"
- #include "include/ddc_interface.h"
--/* TODO remove dvo */
--#include "include/dvo_interface.h"
- #include "include/irq_interface.h"
- #include "include/gpio_service_interface.h"
- #include "hw_translate.h"
-@@ -49,7 +47,6 @@
- 
- #include "hw_gpio_pin.h"
- #include "gpio.h"
--#include "dvo.h"
- #include "ddc.h"
- #include "irq.h"
- 
-@@ -200,36 +197,6 @@ void dal_gpio_service_destroy_ddc(
- 	dal_gpio_destroy_ddc(ddc);
- }
- 
--struct dvo *dal_gpio_service_create_dvo(
--	struct gpio_service *service,
--	uint32_t offset,
--	uint32_t mask)
--{
--	enum gpio_id id;
--	uint32_t en;
--
--	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
--		BREAK_TO_DEBUGGER();
--		return NULL;
--	}
--
--	return dal_dvo_create(service, id, en);
--}
--
--struct dvo *dal_gpio_service_create_dvo_ex(
--	struct gpio_service *service,
--	enum gpio_id id,
--	uint32_t en)
--{
--	return dal_dvo_create(service, id, en);
--}
--
--void dal_gpio_service_destroy_dvo(
--	struct dvo **dvo)
--{
--	dal_dvo_destroy(dvo);
--}
--
- struct irq *dal_gpio_service_create_irq(
- 	struct gpio_service *service,
- 	uint32_t offset,
-@@ -304,29 +271,6 @@ static bool is_pin_busy(
- 	return 0 != (*slot & (1 << (en % bits_per_uint)));
- }
- 
--static bool is_some_pin_busy(
--	const struct gpio_service *service,
--	enum gpio_id id)
--{
--	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
--
--	uint32_t index_of_uint = 0;
--
--	uint32_t number_of_uints =
--		service->factory.number_of_pins[id];
--
--	number_of_uints = (number_of_uints + bits_per_uint - 1) / bits_per_uint;
--
--	while (index_of_uint < number_of_uints) {
--		if (service->busyness[id][index_of_uint])
--			return true;
--
--		++index_of_uint;
--	};
--
--	return false;
--}
--
- static void set_pin_busy(
- 	struct gpio_service *service,
- 	enum gpio_id id,
-@@ -370,38 +314,6 @@ enum gpio_result dal_gpio_service_open(
- 	}
- 
- 	switch (id) {
--	case GPIO_ID_DVO1:
--		/* [anaumov] not implemented, commented with "to do" */
--		ASSERT_CRITICAL(false);
--		return GPIO_RESULT_NON_SPECIFIC_ERROR;
--	case GPIO_ID_DVO12:
--		if (!service->busyness[GPIO_ID_DVO24]) {
--			ASSERT_CRITICAL(false);
--			return GPIO_RESULT_OPEN_FAILED;
--		}
--
--		if (is_some_pin_busy(service, GPIO_ID_DVO24)) {
--			ASSERT_CRITICAL(false);
--			return GPIO_RESULT_DEVICE_BUSY;
--		}
--
--		pin = service->factory.funcs->create_dvo(
--			service->ctx, id, en);
--	break;
--	case GPIO_ID_DVO24:
--		if (!service->busyness[GPIO_ID_DVO12]) {
--			ASSERT_CRITICAL(false);
--			return GPIO_RESULT_OPEN_FAILED;
--		}
--
--		if (is_some_pin_busy(service, GPIO_ID_DVO12)) {
--			ASSERT_CRITICAL(false);
--			return GPIO_RESULT_DEVICE_BUSY;
--		}
--
--		pin = service->factory.funcs->create_dvo(
--			service->ctx, id, en);
--	break;
- 	case GPIO_ID_DDC_DATA:
- 		pin = service->factory.funcs->create_ddc_data(
- 			service->ctx, id, en);
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
-deleted file mode 100644
-index a5a07f0..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.c
-+++ /dev/null
-@@ -1,318 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dal_services.h"
--
--/*
-- * Pre-requisites: headers required by header of this unit
-- */
--
--#include "include/gpio_types.h"
--#include "hw_gpio_pin.h"
--
--/*
-- * Header of this unit
-- */
--
--#include "hw_dvo.h"
--
--/*
-- * Post-requisites: headers required by this unit
-- */
--
--/*
-- * This unit
-- */
--
--#define FROM_HW_GPIO_PIN(ptr) \
--	container_of((ptr), struct hw_dvo, base)
--
--static void store_dvo_registers(
--	struct hw_dvo *pin)
--{
--	pin->store.dvo_mask = dal_read_reg(
--		pin->base.ctx, pin->addr.DC_GPIO_DVODATA_MASK);
--	pin->store.dvo_en = dal_read_reg(
--		pin->base.ctx, pin->addr.DC_GPIO_DVODATA_EN);
--	pin->store.dvo_data_a = dal_read_reg(
--		pin->base.ctx, pin->addr.DC_GPIO_DVODATA_A);
--}
--
--static void restore_dvo_registers(
--	struct hw_dvo *pin)
--{
--	{
--		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_MASK;
--
--		uint32_t data = dal_read_reg(pin->base.ctx, addr);
--
--		data &= ~pin->dvo_mask;
--		data |= pin->store.dvo_mask & pin->dvo_mask;
--
--		dal_write_reg(pin->base.ctx, addr, data);
--	}
--
--	{
--		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_EN;
--
--		uint32_t data = dal_read_reg(pin->base.ctx, addr);
--
--		data &= ~pin->dvo_mask;
--		data |= pin->store.dvo_en & pin->dvo_mask;
--
--		dal_write_reg(pin->base.ctx, addr, data);
--	}
--
--	{
--		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_A;
--
--		uint32_t data = dal_read_reg(pin->base.ctx, addr);
--
--		data &= ~pin->dvo_mask;
--		data |= pin->store.dvo_data_a & pin->dvo_mask;
--
--		dal_write_reg(pin->base.ctx, addr, data);
--	}
--}
--
--static void program_dvo(
--	struct hw_dvo *pin,
--	bool output)
--{
--	/* Turn on Mask bits for the requested channel,
--	 * this will enable the channel for software control. */
--	{
--		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_MASK;
--
--		uint32_t mask = dal_read_reg(pin->base.ctx, addr);
--
--		uint32_t data = pin->dvo_mask | mask;
--
--		dal_write_reg(pin->base.ctx, addr, data);
--	}
--
--	/* Turn off/on the Enable bits on the requested channel,
--	 * this will set it to Input/Output mode. */
--	{
--		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_EN;
--
--		uint32_t enable = dal_read_reg(pin->base.ctx, addr);
--
--		uint32_t data = output ?
--			(pin->dvo_mask | enable) :
--			(~pin->dvo_mask & enable);
--
--		dal_write_reg(pin->base.ctx, addr, data);
--	}
--}
--
--static void program_dvo_strength(
--	struct hw_dvo *pin)
--{
--	const uint32_t addr = pin->addr.DVO_STRENGTH_CONTROL;
--
--	uint32_t data = dal_read_reg(pin->base.ctx, addr);
--
--	data &= ~pin->dvo_strength_mask;
--	data |= pin->dvo_strength & pin->dvo_strength_mask;
--
--	dal_write_reg(pin->base.ctx, addr, data);
--}
--
--static void disable_on_chip_terminators(
--	struct hw_dvo *pin)
--{
--	const uint32_t addr = pin->addr.D1CRTC_MVP_CONTROL1;
--
--	uint32_t data = dal_read_reg(pin->base.ctx, addr);
--
--	pin->store.mvp_terminator_state = (data & pin->mvp_termination_mask);
--
--	data &= ~pin->mvp_termination_mask;
--
--	dal_write_reg(pin->base.ctx, addr, data);
--}
--
--static void restore_on_chip_terminators(
--	struct hw_dvo *pin)
--{
--	const uint32_t addr = pin->addr.D1CRTC_MVP_CONTROL1;
--
--	uint32_t data = dal_read_reg(pin->base.ctx, addr);
--
--	data &= ~pin->mvp_termination_mask;
--
--	if (pin->store.mvp_terminator_state)
--		data |= pin->mvp_termination_mask;
--
--	dal_write_reg(pin->base.ctx, addr, data);
--}
--
--bool dal_hw_dvo_open(
--	struct hw_gpio_pin *ptr,
--	enum gpio_mode mode,
--	void *options)
--{
--	struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
--
--	store_dvo_registers(pin);
--
--	ptr->mode = mode;
--
--	switch (mode) {
--	case GPIO_MODE_INPUT:
--		program_dvo_strength(pin);
--		disable_on_chip_terminators(pin);
--		program_dvo(pin, false);
--
--		ptr->opened = true;
--	break;
--	case GPIO_MODE_OUTPUT:
--		program_dvo_strength(pin);
--		disable_on_chip_terminators(pin);
--		program_dvo(pin, true);
--
--		ptr->opened = true;
--	break;
--	default:
--		/* unsupported mode */
--		BREAK_TO_DEBUGGER();
--
--		ptr->opened = false;
--	}
--
--	return ptr->opened;
--}
--
--enum gpio_result dal_hw_dvo_get_value(
--	const struct hw_gpio_pin *ptr,
--	uint32_t *value)
--{
--	const struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
--
--	if (ptr->mode != GPIO_MODE_INPUT)
--		return GPIO_RESULT_NON_SPECIFIC_ERROR;
--
--	*value = dal_read_reg(ptr->ctx, pin->addr.DC_GPIO_DVODATA_Y);
--
--	*value &= pin->dvo_mask;
--	*value >>= pin->dvo_shift;
--
--	return GPIO_RESULT_OK;
--}
--
--enum gpio_result dal_hw_dvo_set_value(
--	const struct hw_gpio_pin *ptr,
--	uint32_t value)
--{
--	const struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
--
--	uint32_t masked_value;
--
--	if (ptr->mode != GPIO_MODE_OUTPUT) {
--		BREAK_TO_DEBUGGER();
--		return GPIO_RESULT_NON_SPECIFIC_ERROR;
--	}
--
--	/* Ensure there is no overflow of the value written.
--	 * Value cannot be more than 12 bits for a 12-bit channel. */
--
--	masked_value = value << pin->dvo_shift;
--
--	if (masked_value != (masked_value & pin->dvo_mask)) {
--		BREAK_TO_DEBUGGER();
--		return GPIO_RESULT_INVALID_DATA;
--	}
--
--	masked_value &= pin->dvo_mask;
--
--	/* read the DataA register
--	 * mask off the Bundle that we want to write to
--	 * or the data into the register */
--	{
--		const uint32_t addr = pin->addr.DC_GPIO_DVODATA_A;
--
--		uint32_t data = dal_read_reg(ptr->ctx, addr);
--
--		data &= ~pin->dvo_mask;
--		data |= masked_value;
--
--		dal_write_reg(ptr->ctx, addr, data);
--	}
--
--	return GPIO_RESULT_OK;
--}
--
--void dal_hw_dvo_close(
--	struct hw_gpio_pin *ptr)
--{
--	struct hw_dvo *pin = FROM_HW_GPIO_PIN(ptr);
--
--	restore_dvo_registers(pin);
--	restore_on_chip_terminators(pin);
--
--	ptr->mode = GPIO_MODE_UNKNOWN;
--
--	ptr->opened = false;
--}
--
--bool dal_hw_dvo_construct(
--	struct hw_dvo *pin,
--	enum gpio_id id,
--	uint32_t en,
--	struct dc_context *ctx)
--{
--	struct hw_gpio_pin *base = &pin->base;
--
--	if (!dal_hw_gpio_pin_construct(base, id, en, ctx))
--		return false;
--
--	pin->addr.DC_GPIO_DVODATA_MASK = 0;
--	pin->addr.DC_GPIO_DVODATA_EN = 0;
--	pin->addr.DC_GPIO_DVODATA_A = 0;
--	pin->addr.DC_GPIO_DVODATA_Y = 0;
--	pin->addr.DVO_STRENGTH_CONTROL = 0;
--	pin->addr.D1CRTC_MVP_CONTROL1 = 0;
--
--	pin->dvo_mask = 0;
--	pin->dvo_shift = 0;
--	pin->dvo_strength_mask = 0;
--	pin->mvp_termination_mask = 0;
--
--	pin->dvo_strength = 0;
--
--	pin->store.dvo_mask = 0;
--	pin->store.dvo_en = 0;
--	pin->store.dvo_data_a = 0;
--	pin->store.mvp_terminator_state = false;
--
--	return true;
--}
--
--void dal_hw_dvo_destruct(
--	struct hw_dvo *pin)
--{
--	dal_hw_gpio_pin_destruct(&pin->base);
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
-deleted file mode 100644
-index 5a120c2..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_dvo.h
-+++ /dev/null
-@@ -1,89 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_HW_DVO_H__
--#define __DAL_HW_DVO_H__
--
--#define BUNDLE_A_SHIFT 12L
--#define BUNDLE_B_SHIFT 0L
--
--struct hw_dvo {
--	struct hw_gpio_pin base;
--	/* Register indices are represented by member variables,
--	 * are to be filled in by derived classes.
--	 * These members permit the use of common code
--	 * for programming registers where the sequence is the same
--	 * but the register sets are different */
--	struct {
--		uint32_t DC_GPIO_DVODATA_MASK;
--		uint32_t DC_GPIO_DVODATA_EN;
--		uint32_t DC_GPIO_DVODATA_A;
--		uint32_t DC_GPIO_DVODATA_Y;
--		uint32_t DVO_STRENGTH_CONTROL;
--		uint32_t D1CRTC_MVP_CONTROL1;
--	} addr;
--
--	/* Mask and shift differentiates between Bundle A and Bundle B */
--	uint32_t dvo_mask;
--	uint32_t dvo_shift;
--	uint32_t dvo_strength_mask;
--	uint32_t mvp_termination_mask;
--
--	uint32_t dvo_strength;
--
--	struct {
--		uint32_t dvo_mask;
--		uint32_t dvo_en;
--		uint32_t dvo_data_a;
--		bool mvp_terminator_state;
--	} store;
--};
--
--bool dal_hw_dvo_construct(
--	struct hw_dvo *pin,
--	enum gpio_id id,
--	uint32_t en,
--	struct dc_context *ctx);
--
--void dal_hw_dvo_destruct(
--	struct hw_dvo *pin);
--
--bool dal_hw_dvo_open(
--	struct hw_gpio_pin *ptr,
--	enum gpio_mode mode,
--	void *options);
--
--enum gpio_result dal_hw_dvo_get_value(
--	const struct hw_gpio_pin *ptr,
--	uint32_t *value);
--
--enum gpio_result dal_hw_dvo_set_value(
--	const struct hw_gpio_pin *ptr,
--	uint32_t value);
--
--void dal_hw_dvo_close(
--	struct hw_gpio_pin *ptr);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-index 7fef3fa..1fa8b6d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h
-@@ -32,10 +32,6 @@ struct hw_factory {
- 	uint32_t number_of_pins[GPIO_ID_COUNT];
- 
- 	const struct hw_factory_funcs {
--		struct hw_gpio_pin *(*create_dvo)(
--			struct dc_context *ctx,
--			enum gpio_id id,
--			uint32_t en);
- 		struct hw_gpio_pin *(*create_ddc_data)(
- 			struct dc_context *ctx,
- 			enum gpio_id id,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index a2a615a..6cf3955 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -41,17 +41,16 @@
- 	container_of(base, struct display_clock_dce110, disp_clk_base)
- 
- static struct state_dependent_clocks max_clks_by_state[] = {
--/*( dvo not exist in KV)*/
- /*ClocksStateInvalid - should not be used*/
--{ .display_clk_khz = 0, .pixel_clk_khz = 0, .dvo_clk_khz = 0 },
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
- /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
--{ .display_clk_khz = 352000, .pixel_clk_khz = 330000, .dvo_clk_khz = 0 },
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
- /*ClocksStateLow*/
--{ .display_clk_khz = 352000, .pixel_clk_khz = 330000, .dvo_clk_khz = 0 },
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
- /*ClocksStateNominal*/
--{ .display_clk_khz = 467000, .pixel_clk_khz = 400000, .dvo_clk_khz = 0 },
-+{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
- /*ClocksStatePerformance*/
--{ .display_clk_khz = 643000, .pixel_clk_khz = 400000, .dvo_clk_khz = 0 } };
-+{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
- 
- 
- /* Starting point for each divider range.*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-index cce9b0b..019ea02 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-@@ -279,7 +279,6 @@ static bool program_pix_clk(
- 			pll_settings->pix_clk_post_divider;
- 	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
- 	bp_pc_params.signal_type = pix_clk_params->signal_type;
--	bp_pc_params.dvo_config = pix_clk_params->dvo_cfg;
- 	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
- 					pll_settings->use_external_clk;
- 
-@@ -392,7 +391,8 @@ static uint32_t get_pix_clk_dividers(
- 	/* Check if reference clock is external (not pcie/xtalin)
- 	* HW Dce80 spec:
- 	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
--	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
-+	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK
-+	*/
- 	addr = pll_cs_110->pxpll_cntl;
- 	value = dal_read_reg(cs->ctx, addr);
- 	field = get_reg_field_value(value, PLL_CNTL, PLL_REF_DIV_SRC);
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-index 3a26312..6cd0b3f 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-@@ -70,7 +70,6 @@ bool dal_ext_clock_source_program_pix_clk(
- 			pix_clk_params->requested_pix_clk;
- 	bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
- 	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
--	bp_pix_clk_params.dvo_config = pix_clk_params->dvo_cfg;
- 
- 	if (clk_src->bios_parser->funcs->set_pixel_clock(
- 					clk_src->bios_parser,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-index 3049842..aa5a667 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-@@ -97,9 +97,6 @@ bool dal_pll_clock_source_adjust_pix_clk(
- 	bp_adjust_pixel_clock_params.
- 		encoder_object_id = pix_clk_params->encoder_object_id;
- 	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
--	bp_adjust_pixel_clock_params.dvo_config = pix_clk_params->dvo_cfg;
--	bp_adjust_pixel_clock_params.
--		display_pll_config = pix_clk_params->disp_pll_cfg;
- 	bp_adjust_pixel_clock_params.
- 		ss_enable = pix_clk_params->flags.ENABLE_SS;
- 	bp_result = pll_clk_src->base.bios_parser->funcs->adjust_pixel_clock(
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h
-index e9c2ab3..204c5d8 100644
---- a/drivers/gpu/drm/amd/dal/include/audio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/audio_types.h
-@@ -264,7 +264,6 @@ struct audio_feature_support {
- 	uint32_t ENGINE_DIGE:1;
- 	uint32_t ENGINE_DIGF:1;
- 	uint32_t ENGINE_DIGG:1;
--	uint32_t ENGINE_DVO:1;
- 	uint32_t MULTISTREAM_AUDIO:1;
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index 7b93997..b4b93c6 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -144,24 +144,6 @@ struct bp_transmitter_control {
- 	bool single_pll_mode;
- };
- 
--enum dvo_encoder_memory_rate {
--	DVO_ENCODER_MEMORY_RATE_DDR,
--	DVO_ENCODER_MEMORY_RATE_SDR
--};
--
--enum dvo_encoder_interface_width {
--	DVO_ENCODER_INTERFACE_WIDTH_LOW12BIT,
--	DVO_ENCODER_INTERFACE_WIDTH_HIGH12BIT,
--	DVO_ENCODER_INTERFACE_WIDTH_FULL24BIT
--};
--
--struct bp_dvo_encoder_control {
--	enum bp_encoder_control_action action;
--	enum dvo_encoder_memory_rate memory_rate;
--	enum dvo_encoder_interface_width interface_width;
--	uint32_t pixel_clock; /* in KHz */
--};
--
- struct bp_blank_crtc_parameters {
- 	enum controller_id controller_id;
- 	uint32_t black_color_rcr;
-@@ -207,22 +189,12 @@ struct bp_hw_crtc_overscan_parameters {
- struct bp_adjust_pixel_clock_parameters {
- 	/* Input: Signal Type - to be converted to Encoder mode */
- 	enum signal_type signal_type;
--	/* Input: required by V3, display pll configure parameter defined as
--	 * following DISPPLL_CONFIG_XXXX */
--	enum disp_pll_config display_pll_config;
- 	/* Input: Encoder object id */
- 	struct graphics_object_id encoder_object_id;
- 	/* Input: Pixel Clock (requested Pixel clock based on Video timing
- 	 * standard used) in KHz
- 	 */
- 	uint32_t pixel_clock;
--	union {
--		/* Input: If DVO, need passing link rate and output 12bit low or
--		 * 24bit to VBIOS Exec table */
--		uint32_t dvo_config;
--		/* Input: If non DVO, not defined yet */
--		uint32_t non_dvo_undefined;
--	};
- 	/* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
- 	uint32_t adjusted_pixel_clock;
- 	/* Output: If non-zero, this refDiv value should be used to calculate
-@@ -252,9 +224,6 @@ struct bp_pixel_clock_parameters {
- 	/* Calculated Pixel Clock Post divider of Display PLL */
- 	uint32_t pixel_clock_post_divider;
- 	struct graphics_object_id encoder_object_id; /* Encoder object id */
--	/* If DVO, need passing link rate and output 12bit low or
--	 * 24bit to VBIOS Exec table */
--	uint32_t dvo_config;
- 	/* VBIOS returns a fixed display clock when DFS-bypass feature
- 	 * is enabled (KHz) */
- 	uint32_t dfs_bypass_display_clock;
-diff --git a/drivers/gpu/drm/amd/dal/include/clock_source_types.h b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-index 3883216..4c323a9 100644
---- a/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-@@ -86,11 +86,6 @@ struct pixel_clk_params {
- 	struct csdp_ref_clk_ds_params de_spread_params;
- /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
- 
--	uint32_t dvo_cfg;
--/*> If DVO, need passing link rate
-- * and output 12bit low or 24bit to VBIOS Exec table*/
--
--	enum disp_pll_config disp_pll_cfg;
- 	struct pixel_clk_flags flags;
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index f3a1cee..009b583 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -123,7 +123,6 @@ enum clocks_state {
- struct state_dependent_clocks {
- 	uint32_t display_clk_khz;
- 	uint32_t pixel_clk_khz;
--	uint32_t dvo_clk_khz;
- };
- 
- struct display_clock_state {
-diff --git a/drivers/gpu/drm/amd/dal/include/dvo_interface.h b/drivers/gpu/drm/amd/dal/include/dvo_interface.h
-deleted file mode 100644
-index 58d2c6f..0000000
---- a/drivers/gpu/drm/amd/dal/include/dvo_interface.h
-+++ /dev/null
-@@ -1,48 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_DVO_INTERFACE_H__
--#define __DAL_DVO_INTERFACE_H__
--
--#include "gpio_types.h"
--
--struct dvo;
--
--enum gpio_result dal_dvo_open(
--	struct dvo *dvo,
--	enum gpio_mode mode);
--
--enum gpio_result dal_dvo_get_value(
--	const struct dvo *dvo,
--	uint32_t *value);
--
--enum gpio_result dal_dvo_set_value(
--	const struct dvo *dvo,
--	uint32_t value);
--
--void dal_dvo_close(
--	struct dvo *dvo);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-index b4f30dd..3f1b923 100644
---- a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h
-@@ -28,7 +28,6 @@
- 
- #include "gpio_types.h"
- #include "gpio_interface.h"
--#include "dvo_interface.h"
- #include "ddc_interface.h"
- #include "irq_interface.h"
- 
-@@ -63,19 +62,6 @@ struct ddc *dal_gpio_service_create_ddc(
- void dal_gpio_service_destroy_ddc(
- 	struct ddc **ddc);
- 
--struct dvo *dal_gpio_service_create_dvo(
--	struct gpio_service *service,
--	uint32_t offset,
--	uint32_t mask);
--
--struct dvo *dal_gpio_service_create_dvo_ex(
--	struct gpio_service *service,
--	enum gpio_id id,
--	uint32_t en);
--
--void dal_gpio_service_destroy_dvo(
--	struct dvo **ptr);
--
- struct irq *dal_gpio_service_create_irq(
- 	struct gpio_service *service,
- 	uint32_t offset,
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_types.h b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-index d616d62..6d3214b 100644
---- a/drivers/gpu/drm/amd/dal/include/gpio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-@@ -57,9 +57,6 @@ enum gpio_result {
-  */
- enum gpio_id {
- 	GPIO_ID_UNKNOWN = (-1),
--	GPIO_ID_DVO1,
--	GPIO_ID_DVO12,
--	GPIO_ID_DVO24,
- 	GPIO_ID_DDC_DATA,
- 	GPIO_ID_DDC_CLOCK,
- 	GPIO_ID_GENERIC,
-@@ -69,7 +66,7 @@ enum gpio_id {
- 	GPIO_ID_SYNC,
- 	GPIO_ID_GSL, /* global swap lock */
- 	GPIO_ID_COUNT,
--	GPIO_ID_MIN = GPIO_ID_DVO1,
-+	GPIO_ID_MIN = GPIO_ID_DDC_DATA,
- 	GPIO_ID_MAX = GPIO_ID_GSL
- };
- 
-@@ -94,54 +91,6 @@ enum gpio_pin_output_state {
- 	GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
- };
- 
--enum gpio_dvo1 {
--	GPIO_DVO1_UNKNOWN = (-1),
--	GPIO_DVO1_0,
--	GPIO_DVO1_1,
--	GPIO_DVO1_2,
--	GPIO_DVO1_3,
--	GPIO_DVO1_4,
--	GPIO_DVO1_5,
--	GPIO_DVO1_6,
--	GPIO_DVO1_7,
--	GPIO_DVO1_8,
--	GPIO_DVO1_9,
--	GPIO_DVO1_10,
--	GPIO_DVO1_11,
--	GPIO_DVO1_12,
--	GPIO_DVO1_13,
--	GPIO_DVO1_14,
--	GPIO_DVO1_15,
--	GPIO_DVO1_16,
--	GPIO_DVO1_17,
--	GPIO_DVO1_18,
--	GPIO_DVO1_19,
--	GPIO_DVO1_20,
--	GPIO_DVO1_21,
--	GPIO_DVO1_22,
--	GPIO_DVO1_23,
--	GPIO_DVO1_COUNT,
--	GPIO_DVO1_MIN = GPIO_DVO1_0,
--	GPIO_DVO1_MAX = GPIO_DVO1_23
--};
--
--enum gpio_dvo12 {
--	GPIO_DVO12_UNKNOWN = (-1),
--	GPIO_DVO12_A,
--	GPIO_DVO12_B,
--	GPIO_DVO12_COUNT,
--	GPIO_DVO12_MIN = GPIO_DVO12_A,
--	GPIO_DVO12_MAX = GPIO_DVO12_B
--};
--
--enum gpio_dvo24 {
--	GPIO_DVO24_UNKNOWN = (-1),
--	GPIO_DVO24_A,
--	GPIO_DVO24_COUNT,
--	GPIO_DVO24_MIN = GPIO_DVO24_A,
--	GPIO_DVO24_MAX = GPIO_DVO24_A
--};
--
- enum gpio_generic {
- 	GPIO_GENERIC_UNKNOWN = (-1),
- 	GPIO_GENERIC_A,
-@@ -303,7 +252,6 @@ enum gpio_signal_source {
- 	GPIO_SIGNAL_SOURCE_DACB_HSYNC,
- 	GPIO_SIGNAL_SOURCE_DACA_VSYNC,
- 	GPIO_SIGNAL_SOURCE_DACB_VSYNC,
--	GPIO_SIGNAL_SOURCE_DVO_STEREO_SYNC
- };
- 
- enum gpio_stereo_source {
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index d804109..c6de837 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -86,13 +86,6 @@ enum cv_standard {
- 	CV_STANDARD_SD_SECAM_L1		/* SECAM L1 output 4009 */
- };
- 
--enum disp_pll_config {
--	DISP_PLL_CONFIG_UNKNOWN = 0,
--	DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT,
--	DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT,
--	DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT
--};
--
- enum display_output_bit_depth {
- 	PANEL_UNDEFINE = 0,
- 	PANEL_6BIT_COLOR = 1,
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-index 2f73797..4938435 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -124,35 +124,18 @@ enum encoder_id {
- 	ENCODER_ID_INTERNAL_TMDS2,
- 	ENCODER_ID_INTERNAL_DAC1,
- 	ENCODER_ID_INTERNAL_DAC2,	/* TV/CV DAC */
--	ENCODER_ID_INTERNAL_SDVOA,
--	ENCODER_ID_INTERNAL_SDVOB,
- 
- 	/* External Third Party Encoders */
--	ENCODER_ID_EXTERNAL_SI170B,
--	ENCODER_ID_EXTERNAL_CH7303,
--	ENCODER_ID_EXTERNAL_CH7301,	/* 10 in decimal */
--	ENCODER_ID_INTERNAL_DVO1,	/* Belongs to Radeon Display Hardware */
--	ENCODER_ID_EXTERNAL_SDVOA,
--	ENCODER_ID_EXTERNAL_SDVOB,
--	ENCODER_ID_EXTERNAL_TITFP513,
- 	ENCODER_ID_INTERNAL_LVTM1,	/* not used for Radeon */
--	ENCODER_ID_EXTERNAL_VT1623,
--	ENCODER_ID_EXTERNAL_SI1930,	/* HDMI */
- 	ENCODER_ID_INTERNAL_HDMI,
- 
- 	/* Kaledisope (KLDSCP) Class Display Hardware */
- 	ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
--	ENCODER_ID_INTERNAL_KLDSCP_DVO1,
- 	ENCODER_ID_INTERNAL_KLDSCP_DAC1,
- 	ENCODER_ID_INTERNAL_KLDSCP_DAC2,	/* Shared with CV/TV and CRT */
- 	/* External TMDS (dual link) */
--	ENCODER_ID_EXTERNAL_SI178,
- 	ENCODER_ID_EXTERNAL_MVPU_FPGA,	/* MVPU FPGA chip */
- 	ENCODER_ID_INTERNAL_DDI,
--	ENCODER_ID_EXTERNAL_VT1625,
--	ENCODER_ID_EXTERNAL_SI1932,
--	ENCODER_ID_EXTERNAL_AN9801,	/* External Display Port */
--	ENCODER_ID_EXTERNAL_DP501,	/* External Display Port */
- 	ENCODER_ID_INTERNAL_UNIPHY,
- 	ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
- 	ENCODER_ID_INTERNAL_UNIPHY1,
-@@ -163,8 +146,6 @@ enum encoder_id {
- 	ENCODER_ID_INTERNAL_WIRELESS,	/* Internal wireless display encoder */
- 	ENCODER_ID_INTERNAL_UNIPHY3,
- 	ENCODER_ID_INTERNAL_VIRTUAL,
--
--	ENCODER_ID_EXTERNAL_GENERIC_DVO = 0xFF
- };
- 
- 
-@@ -206,7 +187,6 @@ enum engine_id {
- 	ENGINE_ID_DIGE,
- 	ENGINE_ID_DIGF,
- 	ENGINE_ID_DIGG,
--	ENGINE_ID_DVO,
- 	ENGINE_ID_DACA,
- 	ENGINE_ID_DACB,
- 	ENGINE_ID_VCE,	/* wireless display pseudo-encoder */
-@@ -225,7 +205,6 @@ union supported_stream_engines {
- 		uint32_t ENGINE_ID_DIGE:1;
- 		uint32_t ENGINE_ID_DIGF:1;
- 		uint32_t ENGINE_ID_DIGG:1;
--		uint32_t ENGINE_ID_DVO:1;
- 		uint32_t ENGINE_ID_DACA:1;
- 		uint32_t ENGINE_ID_DACB:1;
- 		uint32_t ENGINE_ID_VCE:1;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0724-drm-amd-dal-Fix-up-register-includes-for-encoder.patch b/common/recipes-kernel/linux/files/0724-drm-amd-dal-Fix-up-register-includes-for-encoder.patch
deleted file mode 100644
index 65cd6918..00000000
--- a/common/recipes-kernel/linux/files/0724-drm-amd-dal-Fix-up-register-includes-for-encoder.patch
+++ /dev/null
@@ -1,268 +0,0 @@
-From 442cbfbe3240c715b5603f9568dc586401ad9ecf Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 22 Jan 2016 14:41:43 -0500
-Subject: [PATCH 0724/1110] drm/amd/dal: Fix up register includes for encoder
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   2 +
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 173 +++++++++++++--------
- 2 files changed, 108 insertions(+), 67 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 941d304..66c5034 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -732,6 +732,7 @@ static bool adapter_service_construct(
- 		return false;
- 	}
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	if (dal_adapter_service_get_dce_version(as) == DCE_VERSION_11_0) {
- 		uint32_t i;
- 
-@@ -744,6 +745,7 @@ static bool adapter_service_construct(
- 				feature_entry_table[i].default_value = true;
- 		}
- 	}
-+#endif
- 
- 	/* Generate feature set table */
- 	if (!generate_feature_set(as, init_data->display_param)) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 72493d7..5e43d4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -29,7 +29,6 @@
- 
- #include "resource.h"
- #include "include/irq_service_interface.h"
--#include "include/timing_generator_interface.h"
- 
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
-@@ -41,6 +40,20 @@
- 
- #include "dce/dce_10_0_d.h"
- 
-+/* TODO remove these defines */
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
- enum dce100_clk_src_array_id {
- 	DCE100_CLK_SRC_PLL0 = 0,
- 	DCE100_CLK_SRC_PLL1,
-@@ -76,68 +89,6 @@ static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
- 	}
- };
- 
--static const struct dce110_stream_enc_offsets dce100_str_enc_offsets[] = {
--	{
--		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG3_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP3_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG4_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP4_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG5_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP5_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG6_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP6_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	}
--};
--
--static const struct dce110_link_enc_offsets dce100_lnk_enc_reg_offsets[] = {
--	{
--		.dig = (mmDIG0_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP0_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG1_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP1_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG2_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP2_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG3_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP3_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG4_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP4_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG5_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP5_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	},
--	{
--		.dig = (mmDIG6_DIG_FE_CNTL - mmDIG_FE_CNTL),
--		.dp  = (mmDP6_DP_SEC_CNTL - mmDP_SEC_CNTL)
--	}
--};
--
- static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
- 	{
- 		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-@@ -239,6 +190,92 @@ static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
- }
- };
- 
-+
-+static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
-+		.BL_PWM_CNTL = mmBL_PWM_CNTL,
-+		.BL_PWM_GRP1_REG_LOCK = mmBL_PWM_GRP1_REG_LOCK,
-+		.BL_PWM_PERIOD_CNTL = mmBL_PWM_PERIOD_CNTL,
-+		.LVTMA_PWRSEQ_CNTL = mmLVTMA_PWRSEQ_CNTL,
-+		.LVTMA_PWRSEQ_STATE = mmLVTMA_PWRSEQ_STATE
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	.AUX_CONTROL = mmDP_AUX ## id ## _AUX_CONTROL,\
-+	.AUX_DPHY_RX_CONTROL0 = mmDP_AUX ## id ## _AUX_DPHY_RX_CONTROL0\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+	aux_regs(0),
-+	aux_regs(1),
-+	aux_regs(2)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	.DIG_BE_CNTL = mmDIG ## id ## _DIG_BE_CNTL,\
-+	.DIG_BE_EN_CNTL = mmDIG ## id ## _DIG_BE_EN_CNTL,\
-+	.DP_CONFIG = mmDP ## id ## _DP_CONFIG,\
-+	.DP_DPHY_CNTL = mmDP ## id ## _DP_DPHY_CNTL,\
-+	.DP_DPHY_INTERNAL_CTRL = mmDP ## id ## _DP_DPHY_INTERNAL_CTRL,\
-+	.DP_DPHY_PRBS_CNTL = mmDP ## id ## _DP_DPHY_PRBS_CNTL,\
-+	.DP_DPHY_SYM0 = mmDP ## id ## _DP_DPHY_SYM0,\
-+	.DP_DPHY_SYM1 = mmDP ## id ## _DP_DPHY_SYM1,\
-+	.DP_DPHY_SYM2 = mmDP ## id ## _DP_DPHY_SYM2,\
-+	.DP_DPHY_TRAINING_PATTERN_SEL = mmDP ## id ## _DP_DPHY_TRAINING_PATTERN_SEL,\
-+	.DP_LINK_CNTL = mmDP ## id ## _DP_LINK_CNTL,\
-+	.DP_LINK_FRAMING_CNTL = mmDP ## id ## _DP_LINK_FRAMING_CNTL,\
-+	.DP_MSE_SAT0 = mmDP ## id ## _DP_MSE_SAT0,\
-+	.DP_MSE_SAT1 = mmDP ## id ## _DP_MSE_SAT1,\
-+	.DP_MSE_SAT2 = mmDP ## id ## _DP_MSE_SAT2,\
-+	.DP_MSE_SAT_UPDATE = mmDP ## id ## _DP_MSE_SAT_UPDATE,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2)
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	.AFMT_AVI_INFO0 = mmDIG ## id ## _AFMT_AVI_INFO0,\
-+	.AFMT_AVI_INFO1 = mmDIG ## id ## _AFMT_AVI_INFO1,\
-+	.AFMT_AVI_INFO2 = mmDIG ## id ## _AFMT_AVI_INFO2,\
-+	.AFMT_AVI_INFO3 = mmDIG ## id ## _AFMT_AVI_INFO3,\
-+	.AFMT_GENERIC_0 = mmDIG ## id ## _AFMT_GENERIC_0,\
-+	.AFMT_GENERIC_7 = mmDIG ## id ## _AFMT_GENERIC_7,\
-+	.AFMT_GENERIC_HDR = mmDIG ## id ## _AFMT_GENERIC_HDR,\
-+	.AFMT_INFOFRAME_CONTROL0 = mmDIG ## id ## _AFMT_INFOFRAME_CONTROL0,\
-+	.AFMT_VBI_PACKET_CONTROL = mmDIG ## id ## _AFMT_VBI_PACKET_CONTROL,\
-+	.DIG_FE_CNTL = mmDIG ## id ## _DIG_FE_CNTL,\
-+	.DP_MSE_RATE_CNTL = mmDP ## id ## _DP_MSE_RATE_CNTL,\
-+	.DP_MSE_RATE_UPDATE = mmDP ## id ## _DP_MSE_RATE_UPDATE,\
-+	.DP_PIXEL_FORMAT = mmDP ## id ## _DP_PIXEL_FORMAT,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_STEER_FIFO = mmDP ## id ## _DP_STEER_FIFO,\
-+	.DP_VID_M = mmDP ## id ## _DP_VID_M,\
-+	.DP_VID_N = mmDP ## id ## _DP_VID_N,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL,\
-+	.DP_VID_TIMING = mmDP ## id ## _DP_VID_TIMING,\
-+	.HDMI_CONTROL = mmDIG ## id ## _HDMI_CONTROL,\
-+	.HDMI_GC = mmDIG ## id ## _HDMI_GC,\
-+	.HDMI_GENERIC_PACKET_CONTROL0 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL0,\
-+	.HDMI_GENERIC_PACKET_CONTROL1 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL1,\
-+	.HDMI_INFOFRAME_CONTROL0 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL0,\
-+	.HDMI_INFOFRAME_CONTROL1 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL1,\
-+	.HDMI_VBI_PACKET_CONTROL = mmDIG ## id ## _HDMI_VBI_PACKET_CONTROL,\
-+	.TMDS_CNTL = mmDIG ## id ## _TMDS_CNTL\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2)
-+};
-+
- static struct timing_generator *dce100_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -264,7 +301,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
- 	enum engine_id eng_id,
- 	struct dc_context *ctx,
- 	struct dc_bios *bp,
--	const struct dce110_stream_enc_offsets *offsets)
-+	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
- 		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
-@@ -272,7 +309,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
- 	if (!enc110)
- 		return NULL;
- 
--	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, offsets))
-+	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, regs))
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
-@@ -358,7 +395,9 @@ struct link_encoder *dce100_link_encoder_create(
- 	if (dce110_link_encoder_construct(
- 			enc110,
- 			enc_init_data,
--			&dce100_lnk_enc_reg_offsets[enc_init_data->transmitter]))
-+			&link_enc_regs[enc_init_data->transmitter],
-+			&link_enc_aux_regs[enc_init_data->channel - 1],
-+			&link_enc_bl_regs))
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
-@@ -517,7 +556,7 @@ bool dce100_construct_resource_pool(
- 				i, dc->ctx,
- 				dal_adapter_service_get_bios_parser(
- 					adapter_serv),
--				&dce100_str_enc_offsets[i]);
-+				&stream_enc_regs[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
- 				dal_error("DC: failed to create stream_encoder!\n");
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0725-drm-amd-dal-Fix-issue-with-pipe-powergating-sequence.patch b/common/recipes-kernel/linux/files/0725-drm-amd-dal-Fix-issue-with-pipe-powergating-sequence.patch
deleted file mode 100644
index 294bd40e..00000000
--- a/common/recipes-kernel/linux/files/0725-drm-amd-dal-Fix-issue-with-pipe-powergating-sequence.patch
+++ /dev/null
@@ -1,152 +0,0 @@
-From 660c54dae5f3de13f4a4ed6232575f3c598a5a6a Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Wed, 20 Jan 2016 18:16:03 -0500
-Subject: [PATCH 0725/1110] drm/amd/dal: Fix issue with pipe powergating
- sequence
-
-[Description]
-It looks like pipe powergating was previously never working
-properly and pipe0 was mostly always forced on.
-After fixing the pipe powergating we find severe underflow
-issues that is caused by bad sequence.
-
-We need to unpowergate the pipe early, before we program
-watermarks.
-
-Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 46 +++++++++++++++++++---
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 21 ++++++++--
- 2 files changed, 58 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index a71034c..7f4f2f3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -193,6 +193,34 @@ gamma_param_fail:
- 	return result;
- }
- 
-+static bool validate_surface_address(
-+		struct dc_plane_address address)
-+{
-+	bool is_valid_address = false;
-+
-+	switch (address.type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		if (address.grph.addr.quad_part != 0)
-+			is_valid_address = true;
-+		break;
-+	case PLN_ADDR_TYPE_GRPH_STEREO:
-+		if ((address.grph_stereo.left_addr.quad_part != 0) &&
-+			(address.grph_stereo.right_addr.quad_part != 0)) {
-+			is_valid_address = true;
-+		}
-+		break;
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
-+	case PLN_ADDR_TYPE_VIDEO_INTERLACED:
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO:
-+	case PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO:
-+	default:
-+		/* not supported */
-+		BREAK_TO_DEBUGGER();
-+	}
-+
-+	return is_valid_address;
-+}
-+
- bool dc_commit_surfaces_to_target(
- 		struct dc *dc,
- 		struct dc_surface *new_surfaces[],
-@@ -200,12 +228,17 @@ bool dc_commit_surfaces_to_target(
- 		struct dc_target *dc_target)
- 
- {
--	uint8_t i, j;
-+	int i, j;
- 	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
- 
--	bool current_enabled_surface_count = 0;
--	bool new_enabled_surface_count = 0;
-+	int current_enabled_surface_count = 0;
-+	int new_enabled_surface_count = 0;
-+
-+	if (!dal_adapter_service_is_in_accelerated_mode(
-+						dc->res_pool.adapter_srv)) {
-+		return false;
-+	}
- 
- 	for (i = 0; i < target->status.surface_count; i++)
- 		if (target->status.surfaces[i]->visible)
-@@ -218,7 +251,7 @@ bool dc_commit_surfaces_to_target(
- 	dal_logger_write(dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC,
--				"%s: commit %d surfaces to target 0x%x",
-+				"%s: commit %d surfaces to target 0x%x\n",
- 				__func__,
- 				new_surface_count,
- 				dc_target);
-@@ -254,6 +287,8 @@ bool dc_commit_surfaces_to_target(
- 	for (i = 0; i < new_surface_count; i++) {
- 		struct dc_surface *surface = new_surfaces[i];
- 		struct core_surface *core_surface = DC_SURFACE_TO_CORE(surface);
-+		bool is_valid_address =
-+				validate_surface_address(surface->address);
- 
- 		dal_logger_write(dc->ctx->logger,
- 					LOG_MAJOR_INTERFACE_TRACE,
-@@ -269,7 +304,8 @@ bool dc_commit_surfaces_to_target(
- 			core_surface,
- 			target);
- 
--		dc->hwss.update_plane_address(core_surface, target);
-+		if (is_valid_address)
-+			dc->hwss.update_plane_address(core_surface, target);
- 	}
- 
- 	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 0eafe16..674e795 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -797,10 +797,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			context->res_ctx.pool.adapter_srv);
- 
- 	if (timing_changed) {
--		dce110_enable_display_power_gating(
--				stream->ctx, controller_idx, dcb,
--				PIPE_GATING_CONTROL_DISABLE);
--
- 		/* Must blank CRTC after disabling power gating and before any
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
-@@ -1280,6 +1276,23 @@ static enum dc_status apply_ctx_to_hw(
- 
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
- 			true);
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		struct controller_ctx *ctlr_ctx
-+			= &context->res_ctx.controller_ctx[i];
-+		struct dc_bios *dcb;
-+
-+		if (ctlr_ctx->flags.unchanged || !ctlr_ctx->stream)
-+			continue;
-+
-+		dcb = dal_adapter_service_get_bios_parser(
-+				context->res_ctx.pool.adapter_srv);
-+
-+		dce110_enable_display_power_gating(
-+				dc->ctx, i, dcb,
-+				PIPE_GATING_CONTROL_DISABLE);
-+	}
-+
- 	set_safe_displaymarks(context);
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0726-drm-amd-dal-Remove-display_service_types.patch b/common/recipes-kernel/linux/files/0726-drm-amd-dal-Remove-display_service_types.patch
deleted file mode 100644
index 7d6dcb82..00000000
--- a/common/recipes-kernel/linux/files/0726-drm-amd-dal-Remove-display_service_types.patch
+++ /dev/null
@@ -1,361 +0,0 @@
-From 26c29ed9dea230c28a7dd4638ca062d66ca7aeb8 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Fri, 22 Jan 2016 15:27:36 -0500
-Subject: [PATCH 0726/1110] drm/amd/dal: Remove display_service_types
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../amd/dal/include/display_service_interface.h    | 165 --------------------
- .../drm/amd/dal/include/display_service_types.h    | 167 ---------------------
- 2 files changed, 332 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/include/display_service_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/display_service_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/include/display_service_interface.h b/drivers/gpu/drm/amd/dal/include/display_service_interface.h
-deleted file mode 100644
-index b602bca..0000000
---- a/drivers/gpu/drm/amd/dal/include/display_service_interface.h
-+++ /dev/null
-@@ -1,165 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DISPLAY_SERVICE_INTERFACE_H__
--#define __DISPLAY_SERVICE_INTERFACE_H__
--
--#include "include/display_service_types.h"
--#include "include/display_path_types.h"
--#include "include/grph_object_ctrl_defs.h"
--
--struct display_service;
--struct ds_overlay;
--struct ds_dispatch;
--struct ds_synchronization;
--struct path_mode_set;
--
--struct display_service *dal_display_service_create(
--	struct ds_init_data *data);
--
--void dal_display_service_destroy(
--	struct display_service **ds);
--
--struct ds_dispatch *dal_display_service_get_adjustment_interface(
--	struct display_service *ds);
--
--struct ds_overlay *dal_display_service_get_overlay_interface(
--	struct display_service *ds);
--
--struct ds_dispatch *dal_display_service_get_set_mode_interface(
--	struct display_service *ds);
--
--struct ds_dispatch *dal_display_service_get_reset_mode_interface(
--	struct display_service *ds);
--
--struct ds_synchronization *dal_display_service_get_synchronization_interface(
--	struct display_service *ds);
--
--enum ds_return dal_display_service_notify_v_sync_int_state(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool maintain_v_sync_phase);
--
--enum ds_return dal_display_service_target_power_control(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool power_on);
--
--enum ds_return dal_display_service_power_down_active_hw(
--	struct display_service *ds,
--	enum dc_video_power_state state);
--
--enum ds_return dal_display_service_mem_request_control(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool enable);
--
--enum ds_return dal_display_service_set_multimedia_pass_through_mode(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool passThrough);
--
--enum ds_return dal_display_service_set_palette(
--	struct display_service *ds,
--	uint32_t display_index,
--	const struct ds_devclut *palette,
--	const uint32_t start,
--	const uint32_t length);
--
--enum ds_return dal_display_service_apply_pix_clk_range(
--	struct display_service *ds,
--	uint32_t display_index,
--	struct pixel_clock_safe_range *range);
--
--enum ds_return dal_display_service_get_safe_pix_clk(
--	struct display_service *ds,
--	uint32_t display_index,
--	uint32_t *pix_clk_khz);
--
--enum ds_return dal_display_service_apply_refreshrate_adjustment(
--	struct display_service *ds,
--	uint32_t display_index,
--	enum ds_refreshrate_adjust_action action,
--	struct ds_refreshrate *refreshrate);
--
--enum ds_return dal_display_service_pre_ddc(
--	struct display_service *ds,
--	uint32_t display_index);
--
--enum ds_return dal_display_service_post_ddc(
--	struct display_service *ds,
--	uint32_t display_index);
--
--enum ds_return dal_display_service_backlight_control(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool enable);
--
--enum ds_return dal_display_service_get_backlight_user_level(
--	struct display_service *ds,
--	uint32_t display_index,
--	uint32_t *level);
--
--enum ds_return dal_display_service_get_backlight_effective_level(
--	struct display_service *ds,
--	uint32_t display_index,
--	uint32_t *level);
--
--enum ds_return dal_display_service_enable_hpd(
--	struct display_service *ds,
--	uint32_t display_index);
--
--enum ds_return dal_display_service_disable_hpd(
--	struct display_service *ds,
--	uint32_t display_index);
--
--enum ds_return dal_display_service_get_min_mem_channels(
--	struct display_service *ds,
--	const struct path_mode_set *path_mode_set,
--	uint32_t mem_channels_num,
--	uint32_t *min_mem_channels_num);
--
--enum ds_return dal_display_service_enable_advanced_request(
--	struct display_service *ds,
--	bool enable);
--
--/*Audio related*/
--enum ds_return dal_display_service_enable_audio_endpoint(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool enable);
--
--enum ds_return dal_display_service_mute_audio_endpoint(
--	struct display_service *ds,
--	uint32_t display_index,
--	bool mute);
--
--bool dal_display_service_calc_view_port_for_wide_display(
--	struct display_service *ds,
--	uint32_t display_index,
--	const struct ds_view_port *set_view_port,
--	struct ds_get_view_port *get_view_port);
--
--#endif /* __DISPLAY_SERVICE_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_service_types.h b/drivers/gpu/drm/amd/dal/include/display_service_types.h
-deleted file mode 100644
-index 4f27f59..0000000
---- a/drivers/gpu/drm/amd/dal/include/display_service_types.h
-+++ /dev/null
-@@ -1,167 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_DISPLAY_SERVICE_TYPES_H__
--#define __DAL_DISPLAY_SERVICE_TYPES_H__
--struct ds_dispatch {
--
--};
--
--struct ds_view_port_alignment {
--	uint8_t x_width_size_alignment;
--	uint8_t y_height_size_alignment;
--	uint8_t x_start_alignment;
--	uint8_t y_start_alignment;
--};
--
--struct hw_sequencer;
--struct topology_mgr;
--struct adapter_service;
--struct timing_service;
--
--struct ds_init_data {
--	struct dal_context *dal_context;
--	struct hw_sequencer *hwss;
--	struct topology_mgr *tm;
--	struct adapter_service *as;
--	struct timing_service *ts;
--	struct ds_view_port_alignment view_port_alignment;
--};
--
--enum ds_return {
--	DS_SUCCESS,
--	DS_SUCCESS_FALLBACK,
--	DS_ERROR,
--	DS_SET_MODE_REQUIRED,
--	DS_REBOOT_REQUIRED,
--	DS_OUT_OF_RANGE,
--	DS_RESOURCE_UNAVAILABLE,
--	DS_NOT_SUPPORTED
--};
--
--struct ds_devclut {
--	uint8_t red;
--	uint8_t green;
--	uint8_t blue;
--	uint8_t reserved;
--};
--
--enum ds_refreshrate_adjust_action {
--	DS_REFRESHRATE_ADJUST_ACTION_SET,
--	DS_REFRESHRATE_ADJUST_ACTION_RESET,
--	DS_REFRESHRATE_ADJUST_ACTION_UPDATE,
--};
--
--struct ds_refreshrate {
--	uint32_t numerator;
--	uint32_t denominator;
--};
--
--/*Contains delta in pixels between two active CRTC timings and relevant timing
--details. Delta will be positive if CRTC1 timing running before CRTC2 and
--negative otherwise (CRTC2 timing running before CRTC1)*/
--/*CRTC1 running before CRTC2 = CRTC1 pixel position in
--frame smaller then CRTC2 position*/
--struct ds_timings_delta_info {
--	int32_t delta_in_pixels;
--	uint32_t pix_clk_khz;
--	uint32_t h_total;
--	uint32_t v_total;
--};
--
--enum ds_audio_os_channel_name {
--	DS_AUDIO_OS_CHANNEL_L = 0,
--	DS_AUDIO_OS_CHANNEL_R = 1,
--	DS_AUDIO_OS_CHANNEL_C = 2,
--	DS_AUDIO_OS_CHANNEL_SUB = 3,
--	DS_AUDIO_OS_CHANNEL_RL = 4,
--	DS_AUDIO_OS_CHANNEL_RR = 5,
--	DS_AUDIO_OS_CHANNEL_SL = 6,
--	DS_AUDIO_OS_CHANNEL_SR = 7,
--	DS_AUDIO_OS_CHANNEL_SILENT = 8,
--	DS_AUDIO_OS_CHANNEL_NO_ASSOCIATION = 15
--};
--
--enum ds_audio_azalia_channel_name {
--	DS_AUDIO_AZALIA_CHANNEL_FL = 0,
--	DS_AUDIO_AZALIA_CHANNEL_FR = 1,
--	DS_AUDIO_AZALIA_CHANNEL_FC = 2,
--	DS_AUDIO_AZALIA_CHANNEL_SUB = 3,
--	DS_AUDIO_AZALIA_CHANNEL_SL = 4,
--	DS_AUDIO_AZALIA_CHANNEL_SR = 5,
--	DS_AUDIO_AZALIA_CHANNEL_BL = 6,
--	DS_AUDIO_AZALIA_CHANNEL_BR = 7,
--	DS_AUDIO_AZALIA_CHANNEL_SILENT = 8,
--	DS_AUDIO_AZALIA_CHANNEL_NO_ASSOCIATION = 15
--};
--
--enum ds_audio_channel_format {
--	DS_AUDIO_CHANNEL_FORMAT_2P0 = 0,
--	DS_AUDIO_CHANNEL_FORMAT_2P1,
--	DS_AUDIO_CHANNEL_FORMAT_5P1,
--	DS_AUDIO_CHANNEL_FORMAT_7P1
--};
--
--/*Used for get/set Mirabilis*/
--enum ds_mirabilis_control_option {
--	DS_MIRABILIS_UNINITIALIZE = 0,
--	DS_MIRABILIS_DISABLE,
--	DS_MIRABILIS_ENABLE,
--	DS_MIRABILIS_SAVE_PROFILE
--};
--
--struct ds_disp_identifier {
--	uint32_t display_index;
--	uint32_t manufacture_id;
--	uint32_t product_id;
--	uint32_t serial_no;
--};
--
--struct ds_view_port {
--	uint32_t x_start;
--	uint32_t y_start;
--	uint32_t width;
--	uint32_t height;
--	uint32_t controller;
--};
--
--#define DS_MAX_NUM_VIEW_PORTS 2
--struct ds_get_view_port {
--	uint32_t num_of_view_ports;
--	struct ds_view_port view_ports[DS_MAX_NUM_VIEW_PORTS];
--};
--
--struct ranged_timing_preference_flags {
--	union {
--		struct {
--			uint32_t prefer_enable_drr:1;
--			uint32_t force_disable_drr:1;
--
--		} bits;
--		uint32_t u32all;
--	};
--};
--
--#endif /* __DAL_DISPLAY_SERVICE_TYPE_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0727-drm-amd-dal-Split-encoder_types-into-link-and-stream.patch b/common/recipes-kernel/linux/files/0727-drm-amd-dal-Split-encoder_types-into-link-and-stream.patch
deleted file mode 100644
index 3c0f2702..00000000
--- a/common/recipes-kernel/linux/files/0727-drm-amd-dal-Split-encoder_types-into-link-and-stream.patch
+++ /dev/null
@@ -1,317 +0,0 @@
-From ab0ebdeda2007e1f288f3585f1e0e227034f8840 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Fri, 22 Jan 2016 15:43:46 -0500
-Subject: [PATCH 0727/1110] drm/amd/dal: Split encoder_types into link and
- stream
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   5 +-
- drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h     | 129 ---------------------
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |  55 ++++++++-
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h    |  39 ++++++-
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |   1 +
- drivers/gpu/drm/amd/dal/include/signal_types.h     |   2 +
- 6 files changed, 97 insertions(+), 134 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 1597b33..b0654ca 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -64,9 +64,12 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 
- /********* core_stream ************/
- #include "grph_object_id.h"
--#include "encoder_types.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
- #include "clock_source_interface.h"
- #include "audio_interface.h"
-+#include "scaler_types.h"
-+#include "hw_sequencer_types.h"
- 
- #define DC_STREAM_TO_CORE(dc_stream) container_of( \
- 	dc_stream, struct core_stream, public)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h b/drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h
-deleted file mode 100644
-index 7f3b9ad..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/encoder_types.h
-+++ /dev/null
-@@ -1,129 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_ENCODER_TYPES_H__
--#define __DAL_ENCODER_TYPES_H__
--
--#include "grph_object_defs.h"
--#include "signal_types.h"
--#include "hw_sequencer_types.h"
--#include "link_service_types.h"
--
--struct encoder_init_data {
--	struct adapter_service *adapter_service;
--	enum channel_id channel;
--	struct graphics_object_id connector;
--	enum hpd_source_id hpd_source;
--	/* TODO: in DAL2, here was pointer to EventManagerInterface */
--	struct graphics_object_id encoder;
--	struct dc_context *ctx;
--	enum transmitter transmitter;
--};
--
--struct encoder_context {
--	/*
--	 * HW programming context
--	 */
--	/* DIG id. Also used as AC context */
--	enum engine_id engine;
--	/* DDC line */
--	enum channel_id channel;
--	/* HPD line */
--	enum hpd_source_id hpd_source;
--	/*
--	 * ASIC Control (VBIOS) context
--	 */
--	/* encoder output signal */
--	enum signal_type signal;
--	/* native connector id */
--	struct graphics_object_id connector;
--	/* downstream object (can be connector or downstream encoder) */
--	struct graphics_object_id downstream;
--};
--
--struct encoder_info_packet {
--	bool valid;
--	uint8_t hb0;
--	uint8_t hb1;
--	uint8_t hb2;
--	uint8_t hb3;
--	uint8_t sb[28];
--};
--
--struct encoder_info_frame {
--	/* auxiliary video information */
--	struct encoder_info_packet avi;
--	struct encoder_info_packet gamut;
--	struct encoder_info_packet vendor;
--	/* source product description */
--	struct encoder_info_packet spd;
--	/* video stream configuration */
--	struct encoder_info_packet vsc;
--};
--
--struct encoder_unblank_param {
--	struct hw_crtc_timing crtc_timing;
--	struct link_settings link_settings;
--};
--
--struct encoder_set_dp_phy_pattern_param {
--	enum dp_test_pattern dp_phy_pattern;
--	const uint8_t *custom_pattern;
--	uint32_t custom_pattern_size;
--	enum dp_panel_mode dp_panel_mode;
--};
--
--struct encoder_feature_support {
--	union {
--		struct {
--			/* 1 - external encoder; 0 - internal encoder */
--			uint32_t EXTERNAL_ENCODER:1;
--			uint32_t ANALOG_ENCODER:1;
--			uint32_t STEREO_SYNC:1;
--			/* check the DDC data pin
--			 * when performing DP Sink detection */
--			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
--			/* CPLIB authentication
--			 * for external DP chip supported */
--			uint32_t CPLIB_DP_AUTHENTICATION:1;
--			uint32_t IS_HBR2_CAPABLE:1;
--			uint32_t IS_HBR2_VALIDATED:1;
--			uint32_t IS_TPS3_CAPABLE:1;
--			uint32_t IS_AUDIO_CAPABLE:1;
--			uint32_t IS_VCE_SUPPORTED:1;
--			uint32_t IS_CONVERTER:1;
--			uint32_t IS_Y_ONLY_CAPABLE:1;
--			uint32_t IS_YCBCR_CAPABLE:1;
--		} bits;
--		uint32_t raw;
--	} flags;
--	/* maximum supported deep color depth */
--	enum dc_color_depth max_deep_color;
--	/* maximum supported clock */
--	uint32_t max_pixel_clock;
--};
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index 23920e1..df9019a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -8,8 +8,59 @@
- #ifndef LINK_ENCODER_H_
- #define LINK_ENCODER_H_
- 
--#include "core_types.h"
--#include "encoder_types.h"
-+#include "dal_services_types.h"
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+#include "dc_types.h"
-+
-+struct dc_context;
-+struct adapter_service;
-+struct encoder_set_dp_phy_pattern_param;
-+struct link_mst_stream_allocation_table;
-+struct link_settings;
-+struct link_training_settings;
-+struct core_stream;
-+
-+struct encoder_init_data {
-+	struct adapter_service *adapter_service;
-+	enum channel_id channel;
-+	struct graphics_object_id connector;
-+	enum hpd_source_id hpd_source;
-+	/* TODO: in DAL2, here was pointer to EventManagerInterface */
-+	struct graphics_object_id encoder;
-+	struct dc_context *ctx;
-+	enum transmitter transmitter;
-+};
-+
-+struct encoder_feature_support {
-+	union {
-+		struct {
-+			/* 1 - external encoder; 0 - internal encoder */
-+			uint32_t EXTERNAL_ENCODER:1;
-+			uint32_t ANALOG_ENCODER:1;
-+			uint32_t STEREO_SYNC:1;
-+			/* check the DDC data pin
-+			 * when performing DP Sink detection */
-+			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
-+			/* CPLIB authentication
-+			 * for external DP chip supported */
-+			uint32_t CPLIB_DP_AUTHENTICATION:1;
-+			uint32_t IS_HBR2_CAPABLE:1;
-+			uint32_t IS_HBR2_VALIDATED:1;
-+			uint32_t IS_TPS3_CAPABLE:1;
-+			uint32_t IS_AUDIO_CAPABLE:1;
-+			uint32_t IS_VCE_SUPPORTED:1;
-+			uint32_t IS_CONVERTER:1;
-+			uint32_t IS_Y_ONLY_CAPABLE:1;
-+			uint32_t IS_YCBCR_CAPABLE:1;
-+		} bits;
-+		uint32_t raw;
-+	} flags;
-+	/* maximum supported deep color depth */
-+	enum dc_color_depth max_deep_color;
-+	/* maximum supported clock */
-+	uint32_t max_pixel_clock;
-+};
- 
- struct link_enc_status {
- 	int dummy; /*TODO*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-index 3de1f80..6bb1d00 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-@@ -6,10 +6,45 @@
- #ifndef STREAM_ENCODER_H_
- #define STREAM_ENCODER_H_
- 
--#include "encoder_types.h"
--#include "include/bios_parser_interface.h"
-+#include "include/hw_sequencer_types.h"
- 
- struct dc_bios;
-+struct dc_context;
-+struct dc_crtc_timing;
-+
-+
-+struct encoder_info_packet {
-+	bool valid;
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t hb3;
-+	uint8_t sb[28];
-+};
-+
-+struct encoder_info_frame {
-+	/* auxiliary video information */
-+	struct encoder_info_packet avi;
-+	struct encoder_info_packet gamut;
-+	struct encoder_info_packet vendor;
-+	/* source product description */
-+	struct encoder_info_packet spd;
-+	/* video stream configuration */
-+	struct encoder_info_packet vsc;
-+};
-+
-+struct encoder_unblank_param {
-+	struct hw_crtc_timing crtc_timing;
-+	struct link_settings link_settings;
-+};
-+
-+struct encoder_set_dp_phy_pattern_param {
-+	enum dp_test_pattern dp_phy_pattern;
-+	const uint8_t *custom_pattern;
-+	uint32_t custom_pattern_size;
-+	enum dp_panel_mode dp_panel_mode;
-+};
-+
- 
- struct stream_encoder {
- 	struct stream_encoder_funcs *funcs;
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index b4b93c6..6f72e25 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -30,6 +30,7 @@
- #include "include/grph_object_ctrl_defs.h"
- #include "include/gpio_types.h"
- #include "include/adapter_service_types.h" /* for as_signal_type */
-+#include "include/link_service_types.h"
- 
- enum bp_result {
- 	BP_RESULT_OK = 0, /* There was no error */
-diff --git a/drivers/gpu/drm/amd/dal/include/signal_types.h b/drivers/gpu/drm/amd/dal/include/signal_types.h
-index a50f7ed..827c316 100644
---- a/drivers/gpu/drm/amd/dal/include/signal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/signal_types.h
-@@ -26,6 +26,8 @@
- #ifndef __DC_SIGNAL_TYPES_H__
- #define __DC_SIGNAL_TYPES_H__
- 
-+#include "dal_services_types.h"
-+
- enum signal_type {
- 	SIGNAL_TYPE_NONE		= 0L,		/* no signal */
- 	SIGNAL_TYPE_DVI_SINGLE_LINK	= (1 << 0),
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0728-drm-amd-dal-OPP-refactoring.patch b/common/recipes-kernel/linux/files/0728-drm-amd-dal-OPP-refactoring.patch
deleted file mode 100644
index 1e4199fa..00000000
--- a/common/recipes-kernel/linux/files/0728-drm-amd-dal-OPP-refactoring.patch
+++ /dev/null
@@ -1,524 +0,0 @@
-From a8dbea4b89559bc636b7f78c23a61738a3b87ee5 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 22 Jan 2016 10:58:47 -0500
-Subject: [PATCH 0728/1110] drm/amd/dal: OPP refactoring
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 77 +++++++++++++++++-
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.h    |  1 +
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 19 ++---
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     | 93 +++++++---------------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     | 11 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 55 ++++++++++++-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               | 42 ++++++++++
- 7 files changed, 214 insertions(+), 84 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 5e43d4d..2bf66c6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -276,6 +276,38 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
- 	stream_enc_regs(2)
- };
- 
-+#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
-+
-+static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
-+{
-+	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT_CONTROL),
-+	.dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+
- static struct timing_generator *dce100_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -405,8 +437,47 @@ struct link_encoder *dce100_link_encoder_create(
- 	return NULL;
- }
- 
-+
-+struct output_pixel_processor *dce100_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offset)
-+{
-+	struct dce110_opp *opp =
-+		dc_service_alloc(ctx, sizeof(struct dce110_opp));
-+
-+	if (!opp)
-+		return NULL;
-+
-+	if (dce110_opp_construct(opp,
-+			ctx, inst, offset))
-+		return &opp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, opp);
-+	return NULL;
-+}
-+
-+
-+void dce100_opp_destroy(struct output_pixel_processor **opp)
-+{
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
-+	*opp = NULL;
-+}
-+
- bool dce100_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool)
- {
-@@ -518,7 +589,7 @@ bool dce100_construct_resource_pool(
- 				pool->transforms[i],
- 				pool->scaler_filter);
- 
--		pool->opps[i] = dce110_opp_create(ctx, i);
-+		pool->opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]);
- 		if (pool->opps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-@@ -583,7 +654,7 @@ audio_create_fail:
- controller_create_fail:
- 	for (i = 0; i < pool->controller_count; i++) {
- 		if (pool->opps[i] != NULL)
--			dce110_opp_destroy(&pool->opps[i]);
-+			dce100_opp_destroy(&pool->opps[i]);
- 
- 		if (pool->transforms[i] != NULL)
- 			dce100_transform_destroy(&pool->transforms[i]);
-@@ -625,7 +696,7 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 
- 	for (i = 0; i < pool->controller_count; i++) {
- 		if (pool->opps[i] != NULL)
--			dce110_opp_destroy(&pool->opps[i]);
-+			dce100_opp_destroy(&pool->opps[i]);
- 
- 		if (pool->transforms[i] != NULL)
- 			dce100_transform_destroy(&pool->transforms[i]);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-index 1ae3ecc..a70bfee 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-@@ -16,6 +16,7 @@ struct dc_validation_set;
- 
- bool dce100_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 674e795..1fc4c07 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -182,7 +182,8 @@ static bool set_gamma_ramp(
- 	const struct gamma_parameters *params)
- {
- 	/*Power on LUT memory*/
--	dce110_opp_power_on_regamma_lut(opp, true);
-+	opp->funcs->opp_power_on_regamma_lut(opp, true);
-+
- 
- 	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
- 		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
-@@ -197,10 +198,10 @@ static bool set_gamma_ramp(
- 
- 		ipp->funcs->ipp_set_degamma(ipp, params, true);
- 
--		dce110_opp_set_regamma(opp, ramp, params, true);
-+		opp->funcs->opp_set_regamma(opp, ramp, params, true);
- 	} else if (params->selected_gamma_lut ==
- 			GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA) {
--		if (!dce110_opp_map_legacy_and_regamma_hw_to_x_user(
-+		if (!opp->funcs->opp_map_legacy_and_regamma_hw_to_x_user(
- 			opp, ramp, params)) {
- 			BREAK_TO_DEBUGGER();
- 			/* invalid parameters or bug */
-@@ -224,11 +225,11 @@ static bool set_gamma_ramp(
- 		 * For FP16 or no degamma do by pass */
- 		ipp->funcs->ipp_set_degamma(ipp, params, false);
- 
--		dce110_opp_set_regamma(opp, ramp, params, false);
-+		opp->funcs->opp_set_regamma(opp, ramp, params, false);
- 	}
- 
- 	/*re-enable low power mode for LUT memory*/
--	dce110_opp_power_on_regamma_lut(opp, false);
-+	opp->funcs->opp_power_on_regamma_lut(opp, false);
- 
- 	return true;
- }
-@@ -299,11 +300,11 @@ static void program_fmt(
- 	/* dithering is affected by <CrtcSourceSelect>, hence should be
- 	 * programmed afterwards */
- 
--	dce110_opp_program_bit_depth_reduction(
-+	opp->funcs->opp_program_bit_depth_reduction(
- 		opp,
- 		fmt_bit_depth);
- 
--	dce110_opp_program_clamping_and_pixel_encoding(
-+	opp->funcs->opp_program_clamping_and_pixel_encoding(
- 		opp,
- 		clamping);
- 
-@@ -840,7 +841,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			return DC_ERROR_UNEXPECTED;
- 		}
- 
--	dce110_opp_set_dyn_expansion(
-+	opp->funcs->opp_set_dyn_expansion(
- 			opp,
- 			COLOR_SPACE_YCBCR601,
- 			stream->public.timing.display_color_depth,
-@@ -1411,7 +1412,7 @@ static void set_default_colors(
- 			build_params->
- 			line_buffer_params[path_id][plane_id].depth);*/
- 
--	dce110_opp_set_csc_default(opp, &default_adjust);
-+	opp->funcs->opp_set_csc_default(opp, &default_adjust);
- }
- 
- static void program_scaler(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 3fd12eb..5003c89 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -31,43 +31,11 @@
- 
- #include "dce110_opp.h"
- 
--#define FROM_OPP(opp)\
--	container_of(opp, struct dce110_opp, base)
--
- enum {
- 	MAX_LUT_ENTRY = 256,
- 	MAX_NUMBER_OF_ENTRIES = 256
- };
- 
--static const struct dce110_opp_reg_offsets reg_offsets[] = {
--{
--	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
--	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--},
--{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
--	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--},
--{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
--	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--},
--{
--	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
--	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--},
--{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
--	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--},
--{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
--	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
--}
--};
--
- static void build_evenly_distributed_points(
- 	struct gamma_pixel *points,
- 	uint32_t numberof_points,
-@@ -115,18 +83,30 @@ static void build_evenly_distributed_points(
- /* Constructor, Destructor               */
- /*****************************************/
- 
-+struct opp_funcs funcs = {
-+		.opp_map_legacy_and_regamma_hw_to_x_user = dce110_opp_map_legacy_and_regamma_hw_to_x_user,
-+		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
-+		.opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction,
-+		.opp_program_clamping_and_pixel_encoding = dce110_opp_program_clamping_and_pixel_encoding,
-+		.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
-+		.opp_set_csc_default = dce110_opp_set_csc_default,
-+		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-+		.opp_set_regamma = dce110_opp_set_regamma
-+};
-+
- bool dce110_opp_construct(struct dce110_opp *opp110,
- 	struct dc_context *ctx,
--	uint32_t inst)
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offsets)
- {
--	if (inst >= ARRAY_SIZE(reg_offsets))
--		return false;
-+
-+	opp110->base.funcs = &funcs;
- 
- 	opp110->base.ctx = ctx;
- 
- 	opp110->base.inst = inst;
- 
--	opp110->offsets = reg_offsets[inst];
-+	opp110->offsets = *offsets;
- 
- 	opp110->regamma.hw_points_num = 128;
- 	opp110->regamma.coordinates_x = NULL;
-@@ -274,36 +254,17 @@ failure_1:
- 
- void dce110_opp_destroy(struct output_pixel_processor **opp)
- {
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128_dx);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128_oem);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.axis_x_1025);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.axis_x_256);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coordinates_x);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_regamma);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_resulted);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_oem);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_user);
--	dc_service_free((*opp)->ctx, FROM_OPP(*opp));
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
-+	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
- 	*opp = NULL;
- }
- 
--struct output_pixel_processor *dce110_opp_create(
--	struct dc_context *ctx,
--	uint32_t inst)
--{
--	struct dce110_opp *opp =
--		dc_service_alloc(ctx, sizeof(struct dce110_opp));
--
--	if (!opp)
--		return NULL;
--
--	if (dce110_opp_construct(opp,
--			ctx, inst))
--		return &opp->base;
--
--	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, opp);
--	return NULL;
--}
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index 71fe624..f9b828c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -28,6 +28,10 @@
- #include "dc_types.h"
- #include "inc/opp.h"
- 
-+
-+#define FROM_DCE11_OPP(opp)\
-+	container_of(opp, struct dce110_opp, base)
-+
- enum dce110_opp_reg_type {
- 	DCE110_OPP_REG_DCP = 0,
- 	DCE110_OPP_REG_DCFE,
-@@ -89,14 +93,11 @@ struct dce110_opp {
- 
- bool dce110_opp_construct(struct dce110_opp *opp110,
- 	struct dc_context *ctx,
--	uint32_t inst);
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offsets);
- 
- void dce110_opp_destroy(struct output_pixel_processor **opp);
- 
--struct output_pixel_processor *dce110_opp_create(
--	struct dc_context *ctx,
--	uint32_t inst);
--
- /* REGAMMA RELATED */
- void dce110_opp_power_on_regamma_lut(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index d2970f8..44558d5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -240,6 +240,38 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
- 	stream_enc_regs(2)
- };
- 
-+
-+/* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
-+static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = {
-+{
-+	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -374,6 +406,27 @@ void dce110_link_encoder_destroy(struct link_encoder **enc)
- 	*enc = NULL;
- }
- 
-+
-+static struct output_pixel_processor *dce110_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offsets)
-+{
-+	struct dce110_opp *opp =
-+		dc_service_alloc(ctx, sizeof(struct dce110_opp));
-+
-+	if (!opp)
-+		return NULL;
-+
-+	if (dce110_opp_construct(opp,
-+			ctx, inst, offsets))
-+		return &opp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dc_service_free(ctx, opp);
-+	return NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
-@@ -485,7 +538,7 @@ bool dce110_construct_resource_pool(
- 				pool->transforms[i],
- 				pool->scaler_filter);
- 
--		pool->opps[i] = dce110_opp_create(ctx, i);
-+		pool->opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]);
- 		if (pool->opps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dal_error(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 3293e3b..543848a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -195,6 +195,7 @@ enum opp_regamma {
- struct output_pixel_processor {
- 	struct dc_context *ctx;
- 	uint32_t inst;
-+	struct opp_funcs *funcs;
- };
- 
- enum fmt_stereo_action {
-@@ -203,4 +204,45 @@ enum fmt_stereo_action {
- 	FMT_STEREO_ACTION_UPDATE_POLARITY
- };
- 
-+struct opp_funcs {
-+	void (*opp_power_on_regamma_lut)(
-+		struct output_pixel_processor *opp,
-+		bool power_on);
-+
-+	bool (*opp_set_regamma)(
-+		struct output_pixel_processor *opp,
-+		const struct gamma_ramp *ramp,
-+		const struct gamma_parameters *params,
-+		bool force_bypass);
-+
-+	bool (*opp_map_legacy_and_regamma_hw_to_x_user)(
-+		struct output_pixel_processor *opp,
-+		const struct gamma_ramp *gamma_ramp,
-+		const struct gamma_parameters *params);
-+
-+	void (*opp_set_csc_adjustment)(
-+		struct output_pixel_processor *opp,
-+		const struct grph_csc_adjustment *adjust);
-+
-+	void (*opp_set_csc_default)(
-+		struct output_pixel_processor *opp,
-+		const struct default_adjustment *default_adjust);
-+
-+	/* FORMATTER RELATED */
-+	void (*opp_program_bit_depth_reduction)(
-+		struct output_pixel_processor *opp,
-+		const struct bit_depth_reduction_params *params);
-+
-+	void (*opp_program_clamping_and_pixel_encoding)(
-+		struct output_pixel_processor *opp,
-+		const struct clamping_and_pixel_encoding_params *params);
-+
-+
-+	void (*opp_set_dyn_expansion)(
-+		struct output_pixel_processor *opp,
-+		enum color_space color_sp,
-+		enum dc_color_depth color_dpth,
-+		enum signal_type signal);
-+};
-+
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0729-drm-amd-dal-Make-use-of-amdgpu_crtc-cursor_addr.patch b/common/recipes-kernel/linux/files/0729-drm-amd-dal-Make-use-of-amdgpu_crtc-cursor_addr.patch
deleted file mode 100644
index 8e88181a..00000000
--- a/common/recipes-kernel/linux/files/0729-drm-amd-dal-Make-use-of-amdgpu_crtc-cursor_addr.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-From 299511579bbef4d7e67360cb382ac58f4d37a828 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com>
-Date: Tue, 19 Jan 2016 16:37:18 +0900
-Subject: [PATCH 0729/1110] drm/amd/dal: Make use of amdgpu_crtc->cursor_addr
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 22 ++++++++++++----------
- 1 file changed, 12 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index f2b25cd..c472530 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -139,8 +139,7 @@ static int dm_crtc_pin_cursor_bo_new(
- 	struct drm_crtc *crtc,
- 	struct drm_file *file_priv,
- 	uint32_t handle,
--	struct amdgpu_bo **ret_obj,
--	uint64_t *gpu_addr)
-+	struct amdgpu_bo **ret_obj)
- {
- 	struct amdgpu_crtc *amdgpu_crtc;
- 	struct amdgpu_bo *robj;
-@@ -148,6 +147,10 @@ static int dm_crtc_pin_cursor_bo_new(
- 	int ret = EINVAL;
- 
- 	if (NULL != crtc) {
-+		struct drm_device *dev = crtc->dev;
-+		struct amdgpu_device *adev = dev->dev_private;
-+		uint64_t gpu_addr;
-+
- 		amdgpu_crtc = to_amdgpu_crtc(crtc);
- 
- 		obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
-@@ -170,10 +173,12 @@ static int dm_crtc_pin_cursor_bo_new(
- 			goto release;
- 		}
- 
--		ret = amdgpu_bo_pin(robj, AMDGPU_GEM_DOMAIN_VRAM, NULL);
-+		ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 0,
-+						adev->mc.visible_vram_size,
-+						&gpu_addr);
- 
- 		if (ret == 0) {
--			*gpu_addr = amdgpu_bo_gpu_offset(robj);
-+			amdgpu_crtc->cursor_addr = gpu_addr;
- 			*ret_obj  = robj;
- 		}
- 		amdgpu_bo_unreserve(robj);
-@@ -194,7 +199,6 @@ static int dm_crtc_cursor_set(
- 	uint32_t height)
- {
- 	struct amdgpu_bo *new_cursor_bo;
--	uint64_t gpu_addr;
- 	struct dc_cursor_position position;
- 
- 	int ret;
-@@ -203,7 +207,6 @@ static int dm_crtc_cursor_set(
- 
- 	ret		= EINVAL;
- 	new_cursor_bo	= NULL;
--	gpu_addr	= 0;
- 
- 	DRM_DEBUG_KMS(
- 	"%s: crtc_id=%d with handle %d and size %d to %d, bo_object %p\n",
-@@ -243,14 +246,13 @@ static int dm_crtc_cursor_set(
- 		goto release;
- 	}
- 	/*try to pin new cursor bo*/
--	ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle,
--			&new_cursor_bo, &gpu_addr);
-+	ret = dm_crtc_pin_cursor_bo_new(crtc, file_priv, handle, &new_cursor_bo);
- 	/*if map not successful then return an error*/
- 	if (ret)
- 		goto release;
- 
- 	/*program new cursor bo to hardware*/
--	dm_set_cursor(amdgpu_crtc, gpu_addr, width, height);
-+	dm_set_cursor(amdgpu_crtc, amdgpu_crtc->cursor_addr, width, height);
- 
- 	/*un map old, not used anymore cursor bo ,
- 	 * return memory and mapping back */
-@@ -336,7 +338,7 @@ static void dm_crtc_cursor_reset(struct drm_crtc *crtc)
- 	if (amdgpu_crtc->cursor_bo && amdgpu_crtc->target) {
- 		dm_set_cursor(
- 		amdgpu_crtc,
--		amdgpu_bo_gpu_offset(gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo)),
-+		amdgpu_crtc->cursor_addr,
- 		amdgpu_crtc->cursor_width,
- 		amdgpu_crtc->cursor_height);
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0730-drm-amd-dal-Remove-plane_types.patch b/common/recipes-kernel/linux/files/0730-drm-amd-dal-Remove-plane_types.patch
deleted file mode 100644
index 98252a61..00000000
--- a/common/recipes-kernel/linux/files/0730-drm-amd-dal-Remove-plane_types.patch
+++ /dev/null
@@ -1,400 +0,0 @@
-From 1a9af13fd2aad6d03868a21ba84a2ebd66bc46b9 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Fri, 22 Jan 2016 18:16:19 -0500
-Subject: [PATCH 0730/1110] drm/amd/dal: Remove plane_types
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |   1 -
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |   1 -
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |   1 -
- drivers/gpu/drm/amd/dal/include/plane_types.h      | 309 ---------------------
- drivers/gpu/drm/amd/dal/include/set_mode_types.h   |   1 -
- 6 files changed, 1 insertion(+), 314 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/include/plane_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index d737e33..0481075 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -29,7 +29,6 @@
- 
- #include <drm/drmP.h>
- 
--struct plane_addr_flip_info;
- struct amdgpu_framebuffer;
- struct amdgpu_display_manager;
- struct dc_validation_set;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index 20bb785..e7151cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -1,3 +1,4 @@
-+
- /*
-  * Copyright 2015 Advanced Micro Devices, Inc.
-  *
-@@ -26,7 +27,6 @@
- #ifndef __DAL_IPP_H__
- #define __DAL_IPP_H__
- 
--#include "include/plane_types.h"
- #include "include/grph_object_id.h"
- #include "include/grph_csc_types.h"
- #include "include/video_csc_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 0d34248..2647f84 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -25,7 +25,6 @@
- #ifndef __DAL_MEM_INPUT_H__
- #define __DAL_MEM_INPUT_H__
- 
--#include "include/plane_types.h"
- #include "include/grph_object_id.h"
- #include "dc.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index e9e1124..ad7b906 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -29,7 +29,6 @@
- #include "signal_types.h"
- #include "grph_object_defs.h"
- #include "link_service_types.h"
--#include "plane_types.h"
- 
- struct color_quality {
- 	uint32_t bpp_graphics;
-diff --git a/drivers/gpu/drm/amd/dal/include/plane_types.h b/drivers/gpu/drm/amd/dal/include/plane_types.h
-deleted file mode 100644
-index a2a8939..0000000
---- a/drivers/gpu/drm/amd/dal/include/plane_types.h
-+++ /dev/null
-@@ -1,309 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_PLANE_TYPES_H__
--#define __DAL_PLANE_TYPES_H__
--
--#include "scaler_types.h"
--
--enum display_flip_mode {
--	DISPLAY_FLIP_MODE_VERTICAL = 0,
--	DISPLAY_FLIP_MODE_HORIZONTAL
--};
--
--/*rect or view */
--struct rect_position {
--	uint32_t x;
--	uint32_t y;
--};
--
--union plane_config_change_flags {
--	struct {
--		uint32_t MIRROR_FLAGS:1;
--		uint32_t BLEND_FLAGS:1;
--		uint32_t COLORIMETRY:1;
--		uint32_t SCALING_RECTS:1;
--
--		uint32_t SCALING_QUALITY:1;
--		uint32_t VIDEO_SCAN_FORMAT:1;
--		uint32_t STEREO_FORMAT:1;
--		uint32_t PLANE_SIZE:1;
--
--		uint32_t TITLING_INFO:1;
--		uint32_t FORMAT:1;
--		uint32_t ROTATION:1;
--
--		uint32_t RESERVED:21;
--	} bits;
--	uint32_t value;
--};
--
--
--enum array_mode {
--	ARRAY_MODE_LINEAR_GENERAL = 0x00000000,
--	ARRAY_MODE_LINEAR_ALIGNED = 0x00000001,
--	ARRAY_MODE_1D_TILED_THIN1 = 0x00000002,
--	ARRAY_MODE_1D_TILED_THICK = 0x00000003,
--	ARRAY_MODE_2D_TILED_THIN1 = 0x00000004,
--	ARRAY_MODE_PRT_TILED_THIN1 = 0x00000005,
--	ARRAY_MODE_PRT_2D_TILED_THIN1 = 0x00000006,
--	ARRAY_MODE_2D_TILED_THICK = 0x00000007,
--	ARRAY_MODE_2D_TILED_X_THICK = 0x00000008,
--	ARRAY_MODE_PRT_TILED_THICK = 0x00000009,
--	ARRAY_MODE_PRT_2D_TILED_THICK = 0x0000000a,
--	ARRAY_MODE_PRT_3D_TILED_THIN1 = 0x0000000b,
--	ARRAY_MODE_3D_TILED_THIN1 = 0x0000000c,
--	ARRAY_MODE_3D_TILED_THICK = 0x0000000d,
--	ARRAY_MODE_3D_TILED_X_THICK = 0x0000000e,
--	ARRAY_MODE_PRT_3D_TILED_THICK = 0x0000000f
--};
--
--/* single enum for grph and video (both luma and chroma) */
--enum tile_split {
--	TILE_SPLIT_64B = 0x00000000,
--	TILE_SPLIT_128B = 0x00000001,
--	TILE_SPLIT_256B = 0x00000002,
--	TILE_SPLIT_512B = 0x00000003,
--	TILE_SPLIT_1KB = 0x00000004,
--	TILE_SPLIT_2KB = 0x00000005,
--	TILE_SPLIT_4KB = 0x00000006
--};
--
--/* single enum for grph and video (both luma and chroma)*/
--enum macro_tile_aspect {
--	MACRO_TILE_ASPECT_1 = 0x00000000,
--	MACRO_TILE_ASPECT_2 = 0x00000001,
--	MACRO_TILE_ASPECT_4 = 0x00000002,
--	MACRO_TILE_ASPECT_8 = 0x00000003
--};
--
--enum video_array_mode {
--	VIDEO_ARRAY_MODE_LINEAR_GENERAL = 0x00000000,
--	VIDEO_ARRAY_MODE_LINEAR_ALIGNED = 0x00000001,
--	VIDEO_ARRAY_MODE_1D_TILED_THIN1 = 0x00000002,
--	VIDEO_ARRAY_MODE_1D_TILED_THICK = 0x00000003,
--	VIDEO_ARRAY_MODE_2D_TILED_THIN1 = 0x00000004,
--	VIDEO_ARRAY_MODE_2D_TILED_THICK = 0x00000007,
--	VIDEO_ARRAY_MODE_3D_TILED_THIN1 = 0x0000000c,
--	VIDEO_ARRAY_MODE_3D_TILED_THICK = 0x0000000d
--};
--
--/* single enum for grph and video (both luma and chroma)*/
--enum micro_tile_mode {
--	MICRO_TILE_MODE_DISPLAY = 0x00000000,
--	MICRO_TILE_MODE_THIN = 0x00000001,
--	MICRO_TILE_MODE_DEPTH = 0x00000002,
--	MICRO_TILE_MODE_ROTATED = 0x00000003
--};
--
--/* KK: taken from addrlib*/
--enum addr_pipe_config {
--	ADDR_PIPE_CONFIG_INVALID = 0,
--	/* 2 pipes */
--	ADDR_PIPE_CONFIG_P2 = 1,
--	/* 4 pipes */
--	ADDR_PIPE_CONFIG_P4_8x16 = 5,
--	ADDR_PIPE_CONFIG_P4_16x16 = 6,
--	ADDR_PIPE_CONFIG_P4_16x32 = 7,
--	ADDR_PIPE_CONFIG_P4_32x32 = 8,
--	/* 8 pipes*/
--	ADDR_PIPE_CONFIG_P8_16x16_8x16 = 9,
--	ADDR_PIPE_CONFIG_P8_16x32_8x16 = 10,
--	ADDR_PIPE_CONFIG_P8_32x32_8x16 = 11,
--	ADDR_PIPE_CONFIG_P8_16x32_16x16 = 12,
--	ADDR_PIPE_CONFIG_P8_32x32_16x16 = 13,
--	ADDR_PIPE_CONFIG_P8_32x32_16x32 = 14,
--	ADDR_PIPE_CONFIG_P8_32x64_32x32 = 15,
--	/* 16 pipes */
--	ADDR_PIPE_CONFIG_P16_32x32_8x16 = 17,
--	ADDR_PIPE_CONFIG_P16_32x32_16x16 = 18,
--	ADDR_PIPE_CONFIG_MAX = 19
--};
--
--struct plane_surface_config {
--	uint32_t layer_index;
--	/*used in set operation*/
--	bool enabled;
--
--	union plane_size plane_size;
--	union plane_tiling_info tiling_info;
--	/* surface pixel format from display manager or fb*/
--	enum surface_pixel_format format;
--	/*pixel format for DAL internal hardware programming*/
--	enum pixel_format dal_pixel_format;
--	enum dc_rotation_angle rotation;
--};
--
--/* For Caps, maximum taps for each axis is returned*/
--/* For Set, the requested taps will be used*/
--struct plane_src_scaling_quality {
--	/* INVALID_TAP_VALUE indicates DAL
--	* decides considering aspect ratio
--	* & bandwidth
--	*/
--	uint32_t h_taps;
--	/* INVALID_TAP_VALUE indicates DAL
--	 * decides considering aspect ratio
--	 * & bandwidth
--	 */
--	uint32_t v_taps;
--	uint32_t h_taps_c;
--	uint32_t v_taps_c;
--};
--
--struct plane_mirror_flags {
--	union {
--		struct {
--			uint32_t vertical_mirror:1;
--			uint32_t horizontal_mirror:1;
--			uint32_t reserved:30;
--		} bits;
--		uint32_t value;
--	};
--};
--
--/* Note some combinations are mutually exclusive*/
--struct plane_blend_flags {
--	union {
--	struct {
--		uint32_t PER_PIXEL_ALPHA_BLEND:1;
--		uint32_t GLOBAL_ALPHA_BLEND:1;
--		uint32_t RESERVED:30;
--	} bits;
--	uint32_t value;
--	};
--};
--
--enum plane_vid_scan_fmt {
--	PLANE_VID_SCAN_FMT_PROGRESSIVE = 0,
--	PLANE_VID_SCAN_FMT_INTERLACED_TOP_FIRST = 1,
--	PLANE_VID_SCAN_FMT_INTERLACED_BOTTOM_FIRST = 2
--};
--
--
--struct plane_attributes {
--	/*mirror options  */
--	struct plane_mirror_flags mirror_flags;
--	/*blending options*/
--	struct plane_blend_flags blend_flags;
--	/*color space */
--	struct plane_colorimetry colorimetry;
--
--	struct rect src_rect;
--	struct rect dst_rect;
--	struct rect clip_rect;
--	struct scaling_taps scaling_quality;
--	/*progressive, interlaced*/
--	enum plane_vid_scan_fmt video_scan_format;
--	enum plane_stereo_format stereo_format;
--};
--
--union address_flags {
--	struct {
--		/* always 1 for primary surface, used in get operation*/
--		uint32_t ENABLE:1;
--		/* set 1 if returned address is from cache*/
--		uint32_t ADDR_IS_PENDING:1;
--		/* currentFrameIsRightEye for stereo only*/
--		uint32_t CURRENT_FRAME_IS_RIGHT_EYE:1;
--		uint32_t RESERVED:29;
--	} bits;
--
--	uint32_t value;
--};
--
--struct address_info {
--	/* primary surface will be DAL_LAYER_INDEX_PRIMARY*/
--	int32_t layer_index;
--	/*the flags to describe the address info*/
--	union address_flags flags;
--	struct dc_plane_address address;
--};
--
--union plane_valid_mask {
--	struct {
--		/* set 1 if config is valid in DalPlane*/
--		uint32_t SURFACE_CONFIG_IS_VALID:1;
--		/* set 1 if plane_attributes  is valid in plane*/
--		uint32_t PLANE_ATTRIBUTE_IS_VALID:1;
--		uint32_t RESERVED:30;
--	} bits;
--	uint32_t value;
--};
--
--union flip_valid_mask {
--	struct {
--		/* set 1 if flip_immediate is
--		 * valid in plane_addr_flip_info
--		 */
--		uint32_t FLIP_VALID:1;
--		/* set 1 if addressInfo is
--		 * valid in plane_addr_flip_info
--		 */
--		uint32_t ADDRESS_VALID:1;
--		uint32_t RESERVED:30;
--	} bits;
--	uint32_t value;
--};
--
--struct plane_addr_flip_info {
--	uint32_t display_index;
--	struct address_info address_info;
--	/* flip on vsync if false . When
--	 * flip_immediate is true then
--	 * update_duration is unused
--	 */
--	bool flip_immediate;
--	/* 48 Hz support for single and
--	 * multi plane cases  ,set 0 when
--	 * it is unused.
--	 */
--	uint32_t update_duration;
--	union flip_valid_mask mask;
--};
--
--struct plane_config {
--	union plane_valid_mask mask;
--	uint32_t display_index;
--	struct plane_surface_config config;
--	struct plane_attributes attributes;
--	struct mp_scaling_data mp_scaling_data;
--	union plane_config_change_flags plane_change_flags;
--};
--
--struct plane_validate_config {
--	uint32_t display_index;
--	bool flip_immediate;
--	struct plane_surface_config config;
--	struct plane_attributes attributes;
--};
--
--struct view_port {
--	uint32_t display_index;
--	struct rect view_port_rect;
--};
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_types.h b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-index a7d8119..97160fe 100644
---- a/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-@@ -26,7 +26,6 @@
- #ifndef __DAL_SET_MODE_TYPES_H__
- #define __DAL_SET_MODE_TYPES_H__
- 
--#include "include/plane_types.h"
- #include "dc_types.h"
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0731-drm-amd-dal-Add-DCE10-HW-Sequencer.patch b/common/recipes-kernel/linux/files/0731-drm-amd-dal-Add-DCE10-HW-Sequencer.patch
deleted file mode 100644
index d2f15351..00000000
--- a/common/recipes-kernel/linux/files/0731-drm-amd-dal-Add-DCE10-HW-Sequencer.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From 53b0f6f238dbacdf3e08344009d1d7622c5b5fb0 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Mon, 25 Jan 2016 14:03:52 -0500
-Subject: [PATCH 0731/1110] drm/amd/dal: Add DCE10 HW Sequencer.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |  5 ++-
- drivers/gpu/drm/amd/dal/dc/dce100/Makefile         |  2 +-
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    | 40 ++++++++++++++++++++++
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.h    | 36 +++++++++++++++++++
- 4 files changed, 81 insertions(+), 2 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-index 2cac267..df7e89f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -25,6 +25,9 @@
- #include "dc_services.h"
- #include "core_types.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+#include "dce100/dce100_hw_sequencer.h"
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/dce110_hw_sequencer.h"
- #endif
-@@ -39,7 +42,7 @@ bool dc_construct_hw_sequencer(
- 	{
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
--		return dce110_hw_sequencer_construct(dc);
-+		return dce100_hw_sequencer_construct(dc);
- #endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-index 4c0b4d5..656c38e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'controller' sub-component of DAL.
- # It provides the control and status of HW CRTC block.
- 
--DCE100 = dce100_resource.o
-+DCE100 = dce100_resource.o dce100_hw_sequencer.o
- 
- AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-new file mode 100644
-index 0000000..a235bb0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+
-+#include "resource.h"
-+#include "hw_sequencer.h"
-+#include "dce100_resource.h"
-+
-+bool dce100_hw_sequencer_construct(struct dc *dc)
-+{
-+	dce110_hw_sequencer_construct(dc);
-+	dc->hwss.construct_resource_pool = dce100_construct_resource_pool;
-+	dc->hwss.destruct_resource_pool = dce100_destruct_resource_pool;
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-new file mode 100644
-index 0000000..d52bfda
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE100_H__
-+#define __DC_HWSS_DCE100_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+bool dce100_hw_sequencer_construct(struct dc *dc);
-+
-+#endif /* __DC_HWSS_DCE110_H__ */
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0732-drm-amd-dal-dce-resoure-missing-register-instancee-m.patch b/common/recipes-kernel/linux/files/0732-drm-amd-dal-dce-resoure-missing-register-instancee-m.patch
deleted file mode 100644
index 92badb9d..00000000
--- a/common/recipes-kernel/linux/files/0732-drm-amd-dal-dce-resoure-missing-register-instancee-m.patch
+++ /dev/null
@@ -1,112 +0,0 @@
-From 1ad8ba32ffed2cae879b62c2cb42382bb33a980f Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Tue, 26 Jan 2016 09:59:27 -0500
-Subject: [PATCH 0732/1110] drm/amd/dal: dce resoure missing register instancee
- more than 4 for dce110 and dce100
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 17 ++++++++++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 29 +++++++++++++++-------
- 2 files changed, 34 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 2bf66c6..7ce1bb4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -208,7 +208,10 @@ static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
- static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
- 	aux_regs(0),
- 	aux_regs(1),
--	aux_regs(2)
-+	aux_regs(2),
-+	aux_regs(3),
-+	aux_regs(4),
-+	aux_regs(5)
- };
- 
- #define link_regs(id)\
-@@ -236,7 +239,11 @@ static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
- static const struct dce110_link_enc_registers link_enc_regs[] = {
- 	link_regs(0),
- 	link_regs(1),
--	link_regs(2)
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6)
- };
- 
- #define stream_enc_regs(id)\
-@@ -273,7 +280,11 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
- static const struct dce110_stream_enc_registers stream_enc_regs[] = {
- 	stream_enc_regs(0),
- 	stream_enc_regs(1),
--	stream_enc_regs(2)
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5),
-+	stream_enc_regs(6)
- };
- 
- #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 44558d5..bd9f311 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -170,9 +170,12 @@ static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
- }
- 
- static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
--	aux_regs(0),
--	aux_regs(1),
--	aux_regs(2)
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
- };
- 
- #define link_regs(id)\
-@@ -198,9 +201,13 @@ static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
- }
- 
- static const struct dce110_link_enc_registers link_enc_regs[] = {
--	link_regs(0),
--	link_regs(1),
--	link_regs(2)
-+		link_regs(0),
-+		link_regs(1),
-+		link_regs(2),
-+		link_regs(3),
-+		link_regs(4),
-+		link_regs(5),
-+		link_regs(6)
- };
- 
- #define stream_enc_regs(id)\
-@@ -235,9 +242,13 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
- }
- 
- static const struct dce110_stream_enc_registers stream_enc_regs[] = {
--	stream_enc_regs(0),
--	stream_enc_regs(1),
--	stream_enc_regs(2)
-+		stream_enc_regs(0),
-+		stream_enc_regs(1),
-+		stream_enc_regs(2),
-+		stream_enc_regs(3),
-+		stream_enc_regs(4),
-+		stream_enc_regs(5),
-+		stream_enc_regs(6)
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0733-drm-amd-dal-Disable-dithering-for-Diagnostics-enviro.patch b/common/recipes-kernel/linux/files/0733-drm-amd-dal-Disable-dithering-for-Diagnostics-enviro.patch
deleted file mode 100644
index a301c2dd..00000000
--- a/common/recipes-kernel/linux/files/0733-drm-amd-dal-Disable-dithering-for-Diagnostics-enviro.patch
+++ /dev/null
@@ -1,366 +0,0 @@
-From 0a6fcf118b9bfaeffd3ff647afafc14638f0ea3e Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Fri, 22 Jan 2016 15:38:15 -0500
-Subject: [PATCH 0733/1110] drm/amd/dal: Disable dithering for Diagnostics
- environment.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  6 +----
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        | 25 ++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 23 ++++++++++++++++++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  5 ++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  4 ++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |  3 ++-
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 27 +++++++++++++++-------
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |  5 +---
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |  5 +---
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |  5 +---
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |  3 ++-
- drivers/gpu/drm/amd/dal/include/dal_types.h        |  8 -------
- 13 files changed, 72 insertions(+), 49 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 66c5034..d0dd6c9 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -661,12 +661,8 @@ static struct hw_ctx_adapter_service *create_hw_ctx(
- 	enum dce_environment dce_environment,
- 	struct dc_context *ctx)
- {
--	switch (dce_environment) {
--	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+	if (IS_FPGA_MAXIMUS_DC(dce_environment))
- 		return dal_adapter_service_create_hw_ctx_diag(ctx);
--	default:
--		break;
--	}
- 
- 	switch (dce_version) {
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index 986368a..ab8999b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -41,26 +41,33 @@ struct stream {
- /*******************************************************************************
-  * Private functions
-  ******************************************************************************/
--
- static void build_bit_depth_reduction_params(
-+		const struct core_stream *stream,
- 		struct bit_depth_reduction_params *fmt_bit_depth)
- {
-+	dc_service_memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
-+
- 	/*TODO: Need to un-hardcode, refer to function with same name
- 	 * in dal2 hw_sequencer*/
- 
- 	fmt_bit_depth->flags.TRUNCATE_ENABLED = 0;
- 	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 0;
- 	fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 0;
--	fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
- 
--	fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
--	/* frame random is on by default */
--	fmt_bit_depth->flags.FRAME_RANDOM = 1;
--	/* apply RGB dithering */
--	fmt_bit_depth->flags.RGB_RANDOM = true;
-+	/* Diagnostics need consistent CRC of the image, that means
-+	 * dithering should not be enabled for Diagnostics. */
-+	if (IS_DIAG_DC(stream->ctx->dce_environment) == false) {
- 
--	return;
-+		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
-+		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
- 
-+		/* frame random is on by default */
-+		fmt_bit_depth->flags.FRAME_RANDOM = 1;
-+		/* apply RGB dithering */
-+		fmt_bit_depth->flags.RGB_RANDOM = true;
-+	}
-+
-+	return;
- }
- 
- static void setup_pixel_encoding(
-@@ -85,7 +92,7 @@ static bool construct(struct core_stream *stream,
- 
- 	dc_sink_retain(dc_sink_data);
- 
--	build_bit_depth_reduction_params(&stream->fmt_bit_depth);
-+	build_bit_depth_reduction_params(stream, &stream->bit_depth_params);
- 	setup_pixel_encoding(&stream->clamping);
- 
- 	/* Copy audio modes */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index b932ec1..18ecb0d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -39,6 +39,29 @@ struct dc_link;
- struct dc_sink;
- struct dal;
- 
-+/********************************
-+ * Environment definitions
-+ ********************************/
-+enum dce_environment {
-+	DCE_ENV_PRODUCTION_DRV = 0,
-+	/* Emulation on FPGA, in "Maximus" System.
-+	 * This environment enforces that *only* DC registers accessed.
-+	 * (access to non-DC registers will hang FPGA) */
-+	DCE_ENV_FPGA_MAXIMUS,
-+	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
-+	 * requirements of Diagnostics team. */
-+	DCE_ENV_DIAG
-+};
-+
-+/* Note: use these macro definitions instead of direct comparison! */
-+#define IS_FPGA_MAXIMUS_DC(dce_environment) \
-+	(dce_environment == DCE_ENV_FPGA_MAXIMUS)
-+
-+#define IS_DIAG_DC(dce_environment) \
-+	(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
-+
-+/********************************/
-+
- #define MAX_EDID_BUFFER_SIZE 512
- 
- /*Displayable pixel format in fb*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 1fc4c07..e716219 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -847,7 +847,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 			stream->public.timing.display_color_depth,
- 			stream->sink->public.sink_signal);
- 
--	program_fmt(opp, &stream->fmt_bit_depth, &stream->clamping);
-+	program_fmt(opp, &stream->bit_depth_params, &stream->clamping);
- 
- 	stream->sink->link->link_enc->funcs->setup(
- 		stream->sink->link->link_enc,
-@@ -1350,7 +1350,8 @@ static bool setup_line_buffer_pixel_depth(
- 		if (blank)
- 			tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
- 
--		return xfm->funcs->transform_set_pixel_storage_depth(xfm, depth);
-+		return xfm->funcs->transform_set_pixel_storage_depth(xfm, depth,
-+				&stream->bit_depth_params);
- 	}
- 
- 	return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 392a075..f5cf5ad 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -842,7 +842,7 @@ void dce110_mem_input_allocate_dmif_buffer(
- 	 * 02 - enable DMIF rdreq limit, disable by DMIF stall = 1
- 	 * 03 - force enable DMIF rdreq limit, ignore DMIF stall / urgent
- 	 */
--	if (!IS_DIAG_MAXIMUS_DC(mi->ctx)) {
-+	if (!IS_FPGA_MAXIMUS_DC(mi->ctx->dce_environment)) {
- 		addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
- 		value = dal_read_reg(mi->ctx, addr);
- 
-@@ -912,7 +912,7 @@ void dce110_mem_input_deallocate_dmif_buffer(
- 	 * 02 - enable dmif rdreq limit, disable by dmif stall=1
- 	 * 03 - force enable dmif rdreq limit, ignore dmif stall/urgent
- 	 * Stella Wong proposed this change. */
--	if (!IS_DIAG_MAXIMUS_DC(mi->ctx)) {
-+	if (!IS_FPGA_MAXIMUS_DC(mi->ctx->dce_environment)) {
- 		value = dal_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
- 		if (paths_num > 1)
- 			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index 229f588..117aca3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -76,7 +76,8 @@ void dce110_transform_set_gamut_remap(
- /* BIT DEPTH RELATED */
- bool dce110_transform_set_pixel_storage_depth(
- 	struct transform *xfm,
--	enum lb_pixel_depth depth);
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params);
- 
- bool dce110_transform_get_current_pixel_storage_depth(
- 	struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index 747f2c7..3e0d151 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -114,7 +114,8 @@ static bool set_dither(
-  */
- static bool program_bit_depth_reduction(
- 	struct dce110_transform *xfm110,
--	enum dc_color_depth depth)
-+	enum dc_color_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
- {
- 	enum dcp_bit_depth_reduction_mode depth_reduction_mode;
- 	enum dcp_spatial_dither_mode spatial_dither_mode;
-@@ -127,19 +128,27 @@ static bool program_bit_depth_reduction(
- 		return false;
- 	}
- 
--	depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
-+	if (bit_depth_params->flags.SPATIAL_DITHER_ENABLED) {
-+		depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
-+		frame_random_enable = true;
-+		rgb_random_enable = true;
-+		highpass_random_enable = true;
-+
-+	} else {
-+		depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED;
-+		frame_random_enable = false;
-+		rgb_random_enable = false;
-+		highpass_random_enable = false;
-+	}
- 
- 	spatial_dither_mode = DCP_SPATIAL_DITHER_MODE_A_AA_A;
- 
--	frame_random_enable = true;
--	rgb_random_enable = true;
--	highpass_random_enable = true;
--
- 	if (!set_clamp(xfm110, depth)) {
- 		/* Failure in set_clamp() */
- 		ASSERT_CRITICAL(false);
- 		return false;
- 	}
-+
- 	switch (depth_reduction_mode) {
- 	case DCP_BIT_DEPTH_REDUCTION_MODE_DITHER:
- 		/*  Spatial Dither: Set round/truncate to bypass (12bit),
-@@ -754,7 +763,8 @@ static void set_denormalization(
- 
- bool dce110_transform_set_pixel_storage_depth(
- 	struct transform *xfm,
--	enum lb_pixel_depth depth)
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
- {
- 	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- 	bool ret = true;
-@@ -792,7 +802,8 @@ bool dce110_transform_set_pixel_storage_depth(
- 
- 	if (ret == true) {
- 		set_denormalization(xfm110, color_depth);
--		ret = program_bit_depth_reduction(xfm110, color_depth);
-+		ret = program_bit_depth_reduction(xfm110, color_depth,
-+				bit_depth_params);
- 
- 		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
- 		dal_write_reg(
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index 7e93014..17b5fdf 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -56,12 +56,9 @@ bool dal_hw_factory_init(
- 	enum dce_version dce_version,
- 	enum dce_environment dce_environment)
- {
--	switch (dce_environment) {
--	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
- 		dal_hw_factory_diag_fpga_init(factory);
- 		return true;
--	default:
--		break;
- 	}
- 
- 	switch (dce_version) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index 0e768df..d22504f 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -56,12 +56,9 @@ bool dal_hw_translate_init(
- 	enum dce_version dce_version,
- 	enum dce_environment dce_environment)
- {
--	switch (dce_environment) {
--	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
- 		dal_hw_translate_diag_fpga_init(translate);
- 		return true;
--	default:
--		break;
- 	}
- 
- 	switch (dce_version) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 941213d..68409b3 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -75,11 +75,8 @@ struct i2caux *dal_i2caux_create(
- 	dce_version = dal_adapter_service_get_dce_version(as);
- 	dce_environment = dal_adapter_service_get_dce_environment(as);
- 
--	switch (dce_environment) {
--	case DCE_ENV_DIAG_FPGA_MAXIMUS:
-+	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
- 		return dal_i2caux_diag_fpga_create(as, ctx);
--	default:
--		break;
- 	}
- 
- 	switch (dce_version) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index b0654ca..8282f99 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -120,7 +120,7 @@ struct core_stream {
- 	/*fmt*/
- 	/*TODO: AUTO new codepath in apply_context to hw to
- 	 * generate these bw unrelated/no fail params*/
--	struct bit_depth_reduction_params fmt_bit_depth;
-+	struct bit_depth_reduction_params bit_depth_params;/* used by DCP and FMT */
- 	struct clamping_and_pixel_encoding_params clamping;
- 	struct hw_info_frame info_frame;
- 	struct encoder_info_frame encoder_info_frame;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 50dde2d..d453aac 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -204,7 +204,8 @@ struct transform_funcs {
- 
- 	bool (*transform_set_pixel_storage_depth)(
- 		struct transform *xfm,
--		enum lb_pixel_depth depth);
-+		enum lb_pixel_depth depth,
-+		const struct bit_depth_reduction_params *bit_depth_params);
- 
- 	bool (*transform_get_current_pixel_storage_depth)(
- 		struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 77bd09b..fe884da 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -44,12 +44,6 @@ enum dce_version {
- 	DCE_VERSION_MAX
- };
- 
--enum dce_environment {
--	DCE_ENV_PRODUCTION_DRV = 0,
--	DCE_ENV_DIAG_FPGA_MAXIMUS, /* Emulation on FPGA, in Maximus System. */
--	DCE_ENV_DIAG_SILICON, /* Emulation on real HW */
--};
--
- /*
-  * ASIC Runtime Flags
-  */
-@@ -183,8 +177,6 @@ struct dc_context {
- 	enum dce_environment dce_environment;
- };
- 
--#define IS_DIAG_MAXIMUS_DC(dcctx) ((dcctx)->dce_environment == DCE_ENV_DIAG_FPGA_MAXIMUS)
--
- /* Wireless display structs */
- 
- union dal_remote_display_cea_mode_bitmap {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0734-drm-amd-dal-Add-DCE10-config-option.patch b/common/recipes-kernel/linux/files/0734-drm-amd-dal-Add-DCE10-config-option.patch
deleted file mode 100644
index edcf8c80..00000000
--- a/common/recipes-kernel/linux/files/0734-drm-amd-dal-Add-DCE10-config-option.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 22377109c3033be6c96c18bd6ee2d57cb91ec47b Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 27 Jan 2016 18:04:20 -0500
-Subject: [PATCH 0734/1110] drm/amd/dal: Add DCE10 config option
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Jordan Lazare <jordan.lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/Kconfig | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
-index 14df02e..0dc6f86 100644
---- a/drivers/gpu/drm/amd/dal/Kconfig
-+++ b/drivers/gpu/drm/amd/dal/Kconfig
-@@ -28,6 +28,15 @@ config DRM_AMD_DAL_DCE11_0
- 	 CZ family
- 	 for display engine
- 
-+config DRM_AMD_DAL_DCE10_0
-+        bool "VI family"
-+        depends on DRM_AMD_DAL
-+        help
-+         Choose this option
-+	 if you want to have
-+	 VI family for display
-+	 engine.
-+
- config DEBUG_KERNEL_DAL
-         bool "Enable kgdb break in DAL"
-         depends on DRM_AMD_DAL
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0735-drm-amdgpu-remove-double-drm_vblank_init-call.patch b/common/recipes-kernel/linux/files/0735-drm-amdgpu-remove-double-drm_vblank_init-call.patch
deleted file mode 100644
index 5fe9851c..00000000
--- a/common/recipes-kernel/linux/files/0735-drm-amdgpu-remove-double-drm_vblank_init-call.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From aad14b2ed0cb158bbadf5cdd916c039de4e78f0c Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 31 Mar 2016 18:06:19 -0400
-Subject: [PATCH 0735/1110] drm/amdgpu: remove double drm_vblank_init call
-
-When DAL enabled, drm_vblank_init will be called
-from inside DM code, so guarding this one for
-the case when DAL is not enabled
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 4fe38d7..7ad2aed 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -219,11 +219,6 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
- 	int r = 0;
- 
- 	spin_lock_init(&adev->irq.lock);
--	r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
--	if (r) {
--		return r;
--	}
--	adev->ddev->vblank_disable_allowed = true;
- 
- 	/* enable msi */
- 	adev->irq.msi_enabled = false;
-@@ -237,10 +232,15 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
- 	}
- 
- 	if (!amdgpu_has_dal_support(adev)) {
-+		r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
-+		if (r)
-+			return r;
-+
- 		/* pre DCE11 */
- 		INIT_WORK(&adev->hotplug_work,
- 				amdgpu_hotplug_work_func);
- 	}
-+	adev->ddev->vblank_disable_allowed = true;
- 
- 	INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0736-drm-amd-dal-Block-commit-surfaces-to-targets-that-ha.patch b/common/recipes-kernel/linux/files/0736-drm-amd-dal-Block-commit-surfaces-to-targets-that-ha.patch
deleted file mode 100644
index 85c6f2bc..00000000
--- a/common/recipes-kernel/linux/files/0736-drm-amd-dal-Block-commit-surfaces-to-targets-that-ha.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From c15cfa53f73a5b75668d2376b8da55e8977b62a0 Mon Sep 17 00:00:00 2001
-From: Anthony Koo <Anthony.Koo@amd.com>
-Date: Tue, 26 Jan 2016 11:24:13 -0500
-Subject: [PATCH 0736/1110] drm/amd/dal: Block commit surfaces to targets that
- have not been committed
-
-[Description]
-If a target is not committed, it should be in powergated state.
-In which case we should program it.
-
-Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 7f4f2f3..8cb05b7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -236,10 +236,19 @@ bool dc_commit_surfaces_to_target(
- 	int new_enabled_surface_count = 0;
- 
- 	if (!dal_adapter_service_is_in_accelerated_mode(
--						dc->res_pool.adapter_srv)) {
-+						dc->res_pool.adapter_srv) ||
-+			dc->current_context.target_count == 0) {
- 		return false;
- 	}
- 
-+	for (i = 0; i < dc->current_context.target_count; i++)
-+		if (target == dc->current_context.targets[i])
-+			break;
-+
-+	/* Cannot commit surface to a target that is not commited */
-+	if (i == dc->current_context.target_count)
-+		return false;
-+
- 	for (i = 0; i < target->status.surface_count; i++)
- 		if (target->status.surfaces[i]->visible)
- 			current_enabled_surface_count++;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0737-drm-amd-dal-remove-dal_services.h.patch b/common/recipes-kernel/linux/files/0737-drm-amd-dal-remove-dal_services.h.patch
deleted file mode 100644
index dc60ad39..00000000
--- a/common/recipes-kernel/linux/files/0737-drm-amd-dal-remove-dal_services.h.patch
+++ /dev/null
@@ -1,2070 +0,0 @@
-From 865226c3f31b1d295bda429037245c09b378b6e7 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 25 Jan 2016 18:08:00 +0800
-Subject: [PATCH 0737/1110] drm/amd/dal: remove dal_services.h
-
-Also rename dal_services_types.h to dc_services_types.h
-Fix dependent components and DMs
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    |   2 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   2 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c  |   2 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |   2 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |   2 +-
- .../gpu/drm/amd/dal/dal_power_interface_types.h    |  76 -------
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   2 +-
- .../adapter/dce110/hw_ctx_adapter_service_dce110.c |   2 +-
- .../diagnostics/hw_ctx_adapter_service_diag.c      |   2 +-
- .../amd/dal/dc/adapter/hw_ctx_adapter_service.c    |   2 +-
- .../drm/amd/dal/dc/adapter/wireless_data_source.c  |   2 +-
- .../amd/dal/dc/asic_capability/asic_capability.c   |   2 +-
- .../dc/asic_capability/carrizo_asic_capability.c   |   2 +-
- .../dal/dc/asic_capability/tonga_asic_capability.c |   2 +-
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |   2 +-
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c |   2 +-
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/conversion.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         |   2 +-
- .../gpu/drm/amd/dal/dc/basics/register_logger.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/vector.c         |   2 +-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      |   2 +-
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    |   2 +-
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |   2 +-
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c |   2 +-
- .../dc/bios/dce110/command_table_helper_dce110.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc_services.h           | 227 ++++++++++++++++++++-
- drivers/gpu/drm/amd/dal/dc/dc_services_types.h     | 167 +++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   1 -
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |   2 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c  |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_opp_formatter.c   |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   |   2 +-
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_gamut.c |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c   |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_sclv.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c |   2 +-
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c       |   4 +-
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c |   2 +-
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c |   2 +-
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c |   2 +-
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.c              |   2 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c  |   2 +-
- .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c  |   2 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c  |   2 +-
- .../dal/dc/gpio/diagnostics/hw_translate_diag.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c        |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c           |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c          |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c      |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c      |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c           |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/irq.c              |   2 +-
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c      |   2 +-
- .../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c    |   2 +-
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c |   2 +-
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |   2 +-
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.c    |   2 +-
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.c    |   2 +-
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c     |   2 +-
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c   |   2 +-
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c    |   2 +-
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c    |   2 +-
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c   |   2 +-
- .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c     |   2 +-
- .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |   1 -
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |   1 -
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c |   2 +-
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |   2 +-
- drivers/gpu/drm/amd/dal/dc/irq_types.h             |   2 -
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.c  |   2 +
- .../amd/dal/dc/virtual/virtual_stream_encoder.c    |   3 +-
- drivers/gpu/drm/amd/dal/include/dal_types.h        |   1 -
- drivers/gpu/drm/amd/dal/include/fixed31_32.h       |   2 -
- drivers/gpu/drm/amd/dal/include/fixed32_32.h       |   3 -
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   |   2 -
- .../gpu/drm/amd/dal/include/link_service_types.h   |   2 -
- drivers/gpu/drm/amd/dal/include/signal_types.h     |   2 -
- 111 files changed, 492 insertions(+), 194 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dal_power_interface_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_services_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-index b67599d..eec5313 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-@@ -30,7 +30,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/amdgpu_drm.h>
- #include "amdgpu.h"
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "amdgpu_dm.h"
- #include "amdgpu_dm_irq.h"
- #include "amdgpu_dm_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 2cece0f..bb65892 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services_types.h"
-+#include "dc_services_types.h"
- #include "dc.h"
- 
- #include "vid.h"
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index 7cfb754..b624229 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -25,7 +25,7 @@
- 
- #include <drm/drmP.h>
- 
--#include "dal_services_types.h"
-+#include "dc_services_types.h"
- #include "dc.h"
- 
- #include "amdgpu.h"
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index fe5e366..f52b2f2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -24,7 +24,7 @@
-  */
- 
- #include <drm/drm_atomic_helper.h>
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "amdgpu.h"
- #include "amdgpu_dm_types.h"
- #include "amdgpu_dm_mst_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index c472530..5fe5ca4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services_types.h"
-+#include "dc_services_types.h"
- 
- #include <linux/types.h>
- #include <drm/drmP.h>
-diff --git a/drivers/gpu/drm/amd/dal/dal_power_interface_types.h b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
-deleted file mode 100644
-index 82e8ca2..0000000
---- a/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
-+++ /dev/null
-@@ -1,76 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_POWER_INTERFACE_TYPES_H__
--#define __DAL_POWER_INTERFACE_TYPES_H__
--
--enum dal_to_power_clocks_state {
--	PP_CLOCKS_STATE_INVALID,
--	PP_CLOCKS_STATE_ULTRA_LOW,
--	PP_CLOCKS_STATE_LOW,
--	PP_CLOCKS_STATE_NOMINAL,
--	PP_CLOCKS_STATE_PERFORMANCE
--};
--
--/* clocks in khz */
--struct dal_to_power_info {
--	enum dal_to_power_clocks_state required_clock;
--	uint32_t min_sclk;
--	uint32_t min_mclk;
--	uint32_t min_deep_sleep_sclk;
--};
--
--/* clocks in khz */
--struct power_to_dal_info {
--	uint32_t min_sclk;
--	uint32_t max_sclk;
--	uint32_t min_mclk;
--	uint32_t max_mclk;
--};
--
--/* clocks in khz */
--struct dal_system_clock_range {
--	uint32_t min_sclk;
--	uint32_t max_sclk;
--
--	uint32_t min_mclk;
--	uint32_t max_mclk;
--
--	uint32_t min_dclk;
--	uint32_t max_dclk;
--
--	/* Wireless Display */
--	uint32_t min_eclk;
--	uint32_t max_eclk;
--};
--
--/* clocks in khz */
--struct dal_to_power_dclk {
--	uint32_t optimal; /* input: best optimizes for stutter efficiency */
--	uint32_t minimal; /* input: the lowest clk that DAL can support */
--	uint32_t established; /* output: the actually set one */
--};
--
--#endif /* __DAL_POWER_INTERFACE_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index d0dd6c9..9fb1be8 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -24,7 +24,7 @@
-  */
- 
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dc_bios_types.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-index 31c2aab..98b1475 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "../hw_ctx_adapter_service.h"
- 
- #include "hw_ctx_adapter_service_dce110.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-index de45ce3..ba377f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-@@ -25,7 +25,7 @@
- 
- /* FPGA Diagnostics version of AS HW CTX. */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "../hw_ctx_adapter_service.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-index 5fa886f..0d13a90 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/adapter_service_types.h"
- #include "include/grph_object_id.h"
- #include "hw_ctx_adapter_service.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-index 0249829..122222e 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-@@ -24,7 +24,7 @@
-  */
- 
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "adapter_service.h"
- #include "wireless_data_source.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index b3eb665..05a92a4 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/logger_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-index b106ccc..1de790d 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/asic_capability_interface.h"
- #include "include/asic_capability_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-index 599c47d..7cd0b80 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/asic_capability_interface.h"
- #include "include/asic_capability_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index 2737851..2311f29 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/logger_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-index f284870..5927b12 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/logger_interface.h"
- 
- #include "audio_dce110.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-index a13b2ab..288f14f 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/logger_interface.h"
- #include "../hw_ctx_audio.h"
- #include "hw_ctx_audio_dce110.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-index f1f1298..a78ab79 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "hw_ctx_audio.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-index 8c38206..0eb7813 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #define DIVIDER 10000
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-index 6ce75b3..68626ba 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/fixed31_32.h"
- 
- static inline uint64_t abs_i64(
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-index 1140132..c52fe47 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/fixed32_32.h"
- 
- static uint64_t u64_div(uint64_t n, uint64_t d)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-index 8276f9d..714a571 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/grph_object_id.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index 9c2a889..49cef8a 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -23,7 +23,7 @@
-  *
-  */
- #include <stdarg.h>
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/dal_types.h"
- #include "include/logger_interface.h"
- #include "logger.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-index a3086a0..5dcf3fc 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/dal_types.h"
- #include "include/logger_interface.h"
- #include "logger.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/vector.c b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-index 2f932c0..ea682a7 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/vector.h"
- 
- bool dal_vector_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 8d675f0..2ef2543 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index da559b0..fe05df2 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index cba54f3..1a27bc8 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index 36d1240..d379496 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 2cc2d2d..f6c7df5 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-index 0319382..182029b 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "atom.h"
- 
- #include "include/bios_parser_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-index f8ee65e..3dd8781 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/fixed31_32.h"
- 
- #include "scaler_filter.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-index b8b8b20..fa1c39d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-@@ -31,16 +31,20 @@
- #define __DC_SERVICES_H__
- 
- /* TODO: remove when DC is complete. */
--#include "dal_services_types.h"
-+#include "dc_services_types.h"
- #include "logger_interface.h"
- #include "include/dal_types.h"
- #include "irq_types.h"
--#include "dal_power_interface_types.h"
- #include "link_service_types.h"
- 
-+#undef DEPRECATED
-+
- /* if the pointer is not NULL, the allocated memory is zeroed */
- void *dc_service_alloc(struct dc_context *ctx, uint32_t size);
- 
-+/* reallocate memory. The contents will remain unchanged.*/
-+void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
-+
- void dc_service_free(struct dc_context *ctx, void *p);
- 
- void dc_service_memset(void *p, int32_t c, uint32_t count);
-@@ -50,6 +54,8 @@ void dc_service_memmove(void *dst, const void *src, uint32_t size);
- /* TODO: rename to dc_memcmp*/
- int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
- 
-+int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
-+
- irq_handler_idx dc_service_register_interrupt(
- 	struct dc_context *ctx,
- 	struct dc_interrupt_params *int_params,
-@@ -61,10 +67,182 @@ void dc_service_unregister_interrupt(
- 	enum dc_irq_source irq_source,
- 	irq_handler_idx handler_idx);
- 
-+/*
-+ *
-+ * GPU registers access
-+ *
-+ */
-+static inline uint32_t dal_read_reg(
-+	const struct dc_context *ctx,
-+	uint32_t address)
-+{
-+	uint32_t value = cgs_read_register(ctx->cgs_device, address);
-+
-+#if defined(__DAL_REGISTER_LOGGER__)
-+	if (true == dal_reg_logger_should_dump_register()) {
-+		dal_reg_logger_rw_count_increment();
-+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+	}
-+#endif
-+	return value;
-+}
-+
-+static inline void dal_write_reg(
-+	const struct dc_context *ctx,
-+	uint32_t address,
-+	uint32_t value)
-+{
-+#if defined(__DAL_REGISTER_LOGGER__)
-+	if (true == dal_reg_logger_should_dump_register()) {
-+		dal_reg_logger_rw_count_increment();
-+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+	}
-+#endif
-+	cgs_write_register(ctx->cgs_device, address, value);
-+}
-+
-+static inline uint32_t dal_read_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index)
-+{
-+	return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
-+}
-+
-+static inline void dal_write_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index,
-+	uint32_t value)
-+{
-+	cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
-+}
-+
-+static inline uint32_t get_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (mask & reg_value) >> shift;
-+}
-+
-+#define get_reg_field_value(reg_value, reg_name, reg_field)\
-+	get_reg_field_value_ex(\
-+		(reg_value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline uint32_t set_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (reg_value & ~mask) | (mask & (value << shift));
-+}
-+
-+#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
-+	(reg_value) = set_reg_field_value_ex(\
-+		(reg_value),\
-+		(value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+/*
-+ * atombios services
-+ */
-+
-+bool dal_exec_bios_cmd_table(
-+	struct dc_context *ctx,
-+	uint32_t index,
-+	void *params);
-+
-+#ifdef BUILD_DAL_TEST
-+uint32_t dal_bios_cmd_table_para_revision(
-+struct dc_context *ctx,
-+	uint32_t index);
-+
-+bool dal_bios_cmd_table_revision(
-+	struct dc_context *ctx,
-+	uint32_t index,
-+	uint8_t *frev,
-+	uint8_t *crev);
-+#endif
-+
-+#ifndef BUILD_DAL_TEST
-+static inline uint32_t dal_bios_cmd_table_para_revision(
-+	struct dc_context *ctx,
-+	uint32_t index)
-+{
-+	uint8_t frev;
-+	uint8_t crev;
-+
-+	if (cgs_atom_get_cmd_table_revs(
-+			ctx->cgs_device,
-+			index,
-+			&frev,
-+			&crev) != 0)
-+		return 0;
-+
-+	return crev;
-+}
-+#else
-+uint32_t dal_bios_cmd_table_para_revision(
-+		struct dc_context *ctx,
-+		uint32_t index);
-+#endif
-+
- /**************************************
-  * Power Play (PP) interfaces
-  **************************************/
- 
-+enum dal_to_power_clocks_state {
-+	PP_CLOCKS_STATE_INVALID,
-+	PP_CLOCKS_STATE_ULTRA_LOW,
-+	PP_CLOCKS_STATE_LOW,
-+	PP_CLOCKS_STATE_NOMINAL,
-+	PP_CLOCKS_STATE_PERFORMANCE
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_info {
-+	enum dal_to_power_clocks_state required_clock;
-+	uint32_t min_sclk;
-+	uint32_t min_mclk;
-+	uint32_t min_deep_sleep_sclk;
-+};
-+
-+/* clocks in khz */
-+struct power_to_dal_info {
-+	uint32_t min_sclk;
-+	uint32_t max_sclk;
-+	uint32_t min_mclk;
-+	uint32_t max_mclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_system_clock_range {
-+	uint32_t min_sclk;
-+	uint32_t max_sclk;
-+
-+	uint32_t min_mclk;
-+	uint32_t max_mclk;
-+
-+	uint32_t min_dclk;
-+	uint32_t max_dclk;
-+
-+	/* Wireless Display */
-+	uint32_t min_eclk;
-+	uint32_t max_eclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_dclk {
-+	uint32_t optimal; /* input: best optimizes for stutter efficiency */
-+	uint32_t minimal; /* input: the lowest clk that DAL can support */
-+	uint32_t established; /* output: the actually set one */
-+};
-+
- /* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-  * This is done *before* it changes DCE clock.
-  *
-@@ -224,10 +402,51 @@ bool dc_service_pp_apply_display_requirements(
- 
- void dc_service_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
- 
--/* end of power component calls */
--
- void dc_service_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds);
- 
-+enum platform_method {
-+	PM_GET_AVAILABLE_METHODS = 1 << 0,
-+	PM_GET_LID_STATE = 1 << 1,
-+	PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2
-+};
-+
-+struct platform_info_params {
-+	enum platform_method method;
-+	void *data;
-+};
-+
-+struct platform_info_brightness_caps {
-+	uint8_t ac_level_percentage;
-+	uint8_t dc_level_percentage;
-+};
-+
-+struct platform_info_ext_brightness_caps {
-+	struct platform_info_brightness_caps basic_caps;
-+	struct data_point {
-+		uint8_t luminance;
-+		uint8_t	signal_level;
-+	} data_points[99];
-+
-+	uint8_t	data_points_num;
-+	uint8_t	min_input_signal;
-+	uint8_t	max_input_signal;
-+};
-+
-+bool dal_get_platform_info(
-+	struct dc_context *ctx,
-+	struct platform_info_params *params);
-+
-+/*
-+ *
-+ * print-out services
-+ *
-+ */
-+#define dal_log_to_buffer(buffer, size, fmt, args)\
-+	vsnprintf(buffer, size, fmt, args)
-+
-+long dal_get_pid(void);
-+long dal_get_tgid(void);
-+
- /*
-  *
-  * general debug capabilities
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services_types.h b/drivers/gpu/drm/amd/dal/dc/dc_services_types.h
-new file mode 100644
-index 0000000..aded7b1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_services_types.h
-@@ -0,0 +1,167 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_SERVICES_TYPES_H__
-+#define __DC_SERVICES_TYPES_H__
-+
-+#define INVALID_DISPLAY_INDEX 0xffffffff
-+
-+#if defined __KERNEL__
-+
-+#include <asm/byteorder.h>
-+#include <linux/types.h>
-+#include <drm/drmP.h>
-+
-+#include "cgs_linux.h"
-+
-+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
-+#define BIGENDIAN_CPU
-+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
-+#define LITTLEENDIAN_CPU
-+#endif
-+
-+#undef READ
-+#undef WRITE
-+#undef FRAME_SIZE
-+
-+#define dal_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
-+
-+#define dal_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-+
-+#define dal_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-+
-+#define dal_vlog(fmt, args) vprintk(fmt, args)
-+
-+#define dal_min(x, y) min(x, y)
-+#define dal_max(x, y) max(x, y)
-+
-+#elif defined BUILD_DAL_TEST
-+
-+#include <inttypes.h>
-+#include <stdlib.h>
-+#include <string.h>
-+
-+#include <stdio.h>
-+
-+#include <stdarg.h>
-+
-+#include "cgs_linux.h"
-+
-+#define LONG_MAX	((long)(~0UL>>1))
-+#define LONG_MIN	(-LONG_MAX - 1)
-+#define LLONG_MAX	((long long)(~0ULL>>1))
-+#define LLONG_MIN	(-LLONG_MAX - 1)
-+#define UINT_MAX	(~0U)
-+
-+typedef _Bool bool;
-+enum { false, true };
-+
-+#ifndef NULL
-+#define NULL ((void *)0)
-+#endif
-+
-+#define LITTLEENDIAN_CPU 1
-+
-+#include <test_context.h>
-+
-+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-+
-+#define container_of(ptr, type, member) \
-+	((type *)((char *)(ptr) - offsetof(type, member)))
-+
-+#define dal_test_not_implemented() \
-+	printf("[DAL_TEST_NOT_IMPL]:%s\n", __func__)
-+
-+#define dal_output_to_console(fmt, ...) do { \
-+	printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
-+	while (false)
-+
-+#define dal_error(fmt, ...) printf("[DAL_ERROR]" fmt, ##__VA_ARGS__)
-+
-+#define dal_output_to_console(fmt, ...) do { \
-+			printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
-+				while (false)
-+
-+
-+#define dal_debug(fmt, ...) printf("[DAL_DBG]" fmt, ##__VA_ARGS__)
-+
-+#define dal_vlog(fmt, args) vprintf(fmt, args)
-+
-+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-+
-+#define dal_min(x, y) ({\
-+	typeof(x) _min1 = (x);\
-+	typeof(y) _min2 = (y);\
-+	(void) (&_min1 == &_min2);\
-+	_min1 < _min2 ? _min1 : _min2; })
-+
-+#define dal_max(x, y) ({\
-+	typeof(x) _max1 = (x);\
-+	typeof(y) _max2 = (y);\
-+	(void) (&_max1 == &_max2);\
-+	_max1 > _max2 ? _max1 : _max2; })
-+
-+/* division functions */
-+
-+static inline int64_t div64_s64(int64_t x, int64_t y)
-+{
-+	return x / y;
-+}
-+
-+static inline uint64_t div64_u64(uint64_t x, uint64_t y)
-+{
-+	return x / y;
-+}
-+
-+static inline uint64_t div_u64(uint64_t x, uint32_t y)
-+{
-+	return x / y;
-+}
-+
-+static inline uint64_t div64_u64_rem(uint64_t x, uint64_t y, uint64_t *rem)
-+{
-+	if (rem)
-+		*rem = x % y;
-+	return x / y;
-+}
-+
-+static inline uint64_t div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem)
-+{
-+	if (rem)
-+		*rem = x % y;
-+	return x / y;
-+}
-+
-+#define cpu_to_le16(do_nothing) do_nothing
-+
-+#define le16_to_cpu(do_nothing) do_nothing
-+
-+#define cpu_to_le32(do_nothing) do_nothing
-+
-+#define le32_to_cpu(do_nothing) do_nothing
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 18ecb0d..c797642 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -25,7 +25,6 @@
- #ifndef DC_TYPES_H_
- #define DC_TYPES_H_
- 
--#include "dal_services_types.h"
- #include "fixed32_32.h"
- #include "fixed31_32.h"
- #include "irq_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index a235bb0..b37df4a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -23,6 +23,8 @@
-  *
-  */
- 
-+#include "dc_services.h"
-+
- #include "dce110/dce110_hw_sequencer.h"
- 
- #include "resource.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-index 7abb790..6761b4f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-index a29dc51..6cd80ae 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/logger_interface.h"
- 
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-index 08b7940..0569fbb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/logger_interface.h"
- 
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index b7186b1..2aa432a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/logger_interface.h"
- #include "include/fixed31_32.h"
- #include "basics/conversion.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 4a83e25..2396f15 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "core_types.h"
- #include "link_encoder.h"
- #include "stream_encoder.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index f5cf5ad..4e809b6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 5003c89..99163ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-index 91430c0..a96a72a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "dce110_opp.h"
- #include "basics/conversion.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-index fdf87bd..0224ade 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index cf116f1..dceba7d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 5b432d8..fadcc06 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "dc_bios_types.h"
- #include "dce110_stream_encoder.h"
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 1bb89d8..79e34dc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-index 5a87ded..16cddb5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index 3e0d151..d0e4b98 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-index 0dd4355..bb3b3cc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "dce110_transform.h"
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index f313d2c..4ba14c2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-index bcf20bb..9b25ed7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-index a4442d6..0af4df6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "ddc_i2caux_helper.h"
- #include "include/ddc_service_types.h"
- #include "include/vector.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-index 854ff3f..bbab51c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-@@ -23,7 +23,8 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
-+
- #include "include/adapter_service_interface.h"
- #include "include/i2caux_interface.h"
- #include "include/ddc_service_interface.h"
-@@ -33,7 +34,6 @@
- #include "include/logger_interface.h"
- #include "ddc_i2caux_helper.h"
- #include "ddc_service.h"
--#include "dal_services_types.h"
- 
- #define AUX_POWER_UP_WA_DELAY 500
- #define I2C_OVER_AUX_DEFER_WA_DELAY 70
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-index f026464..b8554aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-index 55d6986..6a9ee1a 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/gpio_types.h"
- #include "../hw_factory.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-index 34405e9..e427f2c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-index 38512fa..0c87515 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/gpio_types.h"
- #include "../hw_translate.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-index 548b1cf..ee6a0b0 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/gpio_interface.h"
- #include "include/ddc_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-index f566241..282f1fc 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-index 59503c4..2349bf7 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/gpio_types.h"
- #include "../hw_factory.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-index baf5caf..f47e56a 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-index 6d4da30..cfcd197 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-@@ -24,7 +24,7 @@
-  */
- 
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/gpio_types.h"
- 
- #include "../hw_translate.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-index 6115f59..9168b2c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/gpio_interface.h"
- #include "include/gpio_service_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-index 0920545..b79653c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/gpio_interface.h"
- #include "include/ddc_interface.h"
- #include "include/irq_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-index 0608f16..e15f3a2 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index 17b5fdf..a5fa3aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-index 2964d5d..9e231d3 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-index 057c439..52757ac 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-index 4ab1848..0d3f07f 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-index c09d74c..617d648 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index d22504f..4a894c8 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-index 382b89f..04bb69d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-index acc8838..4947d73 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "calc_pll_clock_source.h"
- #include "include/bios_parser_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-index a2e618e..73804cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/adapter_service_interface.h"
- #include "include/bios_parser_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-index f124dba..0ed4f06 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dc_clock_generator.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-index e2d4228..6edb5aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/logger_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 6cf3955..3e0e9b3 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-index ae70e41..fa3201b 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-index 019ea02..ba05597 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-index 0a0b516..249720f 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-@@ -21,7 +21,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "vce_clock_source_dce110.h"
- #include "include/clock_source_types.h"
- #include "include/bios_parser_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-index a11aa84..887bd74 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "display_clock.h"
- #include "adapter_service_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-index 3b04447..b4355f2 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "divider_range.h"
- 
- bool dal_divider_range_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-index 6cd0b3f..ec5b17d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/bios_parser_interface.h"
- #include "include/clock_source_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-index aa5a667..d00bb61 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/bios_parser_interface.h"
- #include "pll_clock_source.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-index 824ceec..b81fbdb 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-index 1b40a78..d0b8288 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-index 17e89ce..ce3cc4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- #include "include/logger_interface.h"
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-index c415a4e..2d5a318 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-index 05f5778..d2de0f2 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-index 86b606d..96b78e7 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c b/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-index 2f87a65..7a1c78c 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-index 78c7d61..c8ab1f8 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-index d91e259..61df97e 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-index 77f2b84..cd8aa44 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-index c253917..c14c5df 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 68409b3..68dff0e 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index 2d5644c..d794132 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -10,7 +10,6 @@
- 
- #include "core_types.h"
- #include "hw_sequencer.h"
--#include "dal_services.h"
- 
- struct dc {
- 	struct dc_context *ctx;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index df9019a..ab99b27 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -8,7 +8,6 @@
- #ifndef LINK_ENCODER_H_
- #define LINK_ENCODER_H_
- 
--#include "dal_services_types.h"
- #include "grph_object_defs.h"
- #include "signal_types.h"
- #include "dc_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-index 2a4f14c..3caeeed 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/logger_interface.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-index b54e813..6f625dd 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dal_services.h"
-+#include "dc_services.h"
- 
- #include "include/irq_service_interface.h"
- #include "include/logger_interface.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq_types.h b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-index f8f2395..35a0991 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-@@ -26,8 +26,6 @@
- #ifndef __DAL_IRQ_TYPES_H__
- #define __DAL_IRQ_TYPES_H__
- 
--#include "dal_services_types.h"
--
- struct dc_context;
- 
- typedef void (*interrupt_handler)(void *);
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-index 4d48daa..4880341 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -23,6 +23,8 @@
-  *
-  */
- 
-+#include "dc_services_types.h"
-+
- #include "virtual_link_encoder.h"
- 
- #define VIRTUAL_MAX_PIXEL_CLK_IN_KHZ 600000
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-index dcfda67..99784be 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-@@ -23,9 +23,10 @@
-  *
-  */
- 
--#include "virtual_stream_encoder.h"
- #include "dc_services.h"
- 
-+#include "virtual_stream_encoder.h"
-+
- static void virtual_stream_encoder_dp_set_stream_attribute(
- 	struct stream_encoder *enc,
- 	struct dc_crtc_timing *crtc_timing) {}
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index fe884da..3739776 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -26,7 +26,6 @@
- #ifndef __DAL_TYPES_H__
- #define __DAL_TYPES_H__
- 
--#include "dal_services_types.h"
- #include "signal_types.h"
- #include "dc_types.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed31_32.h b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-index 4577809..507f9f6 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-@@ -26,8 +26,6 @@
- #ifndef __DAL_FIXED31_32_H__
- #define __DAL_FIXED31_32_H__
- 
--#include "dal_services_types.h"
--
- /*
-  * @brief
-  * Arithmetic operations on real numbers
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-index 5291a30..5fca957 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -26,9 +26,6 @@
- #ifndef __DAL_FIXED32_32_H__
- #define __DAL_FIXED32_32_H__
- 
--#include "dal_services_types.h"
--
--
- struct fixed32_32 {
- 	uint64_t value;
- };
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-index 4938435..4c8079c 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -26,8 +26,6 @@
- #ifndef __DAL_GRPH_OBJECT_ID_H__
- #define __DAL_GRPH_OBJECT_ID_H__
- 
--#include "dal_services_types.h"
--
- /* Types of graphics objects */
- enum object_type {
- 	OBJECT_TYPE_UNKNOWN  = 0,
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 30fc6f0..d2e6256 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -26,8 +26,6 @@
- #ifndef __DAL_LINK_SERVICE_TYPES_H__
- #define __DAL_LINK_SERVICE_TYPES_H__
- 
--#include "dal_services_types.h"
--
- #include "grph_object_id.h"
- #include "dpcd_defs.h"
- #include "dal_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/include/signal_types.h b/drivers/gpu/drm/amd/dal/include/signal_types.h
-index 827c316..a50f7ed 100644
---- a/drivers/gpu/drm/amd/dal/include/signal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/signal_types.h
-@@ -26,8 +26,6 @@
- #ifndef __DC_SIGNAL_TYPES_H__
- #define __DC_SIGNAL_TYPES_H__
- 
--#include "dal_services_types.h"
--
- enum signal_type {
- 	SIGNAL_TYPE_NONE		= 0L,		/* no signal */
- 	SIGNAL_TYPE_DVI_SINGLE_LINK	= (1 << 0),
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0738-drm-amd-dal-refactor-clock-sources.patch b/common/recipes-kernel/linux/files/0738-drm-amd-dal-refactor-clock-sources.patch
deleted file mode 100644
index aa28f490..00000000
--- a/common/recipes-kernel/linux/files/0738-drm-amd-dal-refactor-clock-sources.patch
+++ /dev/null
@@ -1,4640 +0,0 @@
-From d881814e00bd5f40228ea222784cd0d19b5ed381 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 25 Jan 2016 16:21:37 -0500
-Subject: [PATCH 0738/1110] drm/amd/dal: refactor clock sources
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |    2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |    2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |    3 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |    1 +
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |   68 +-
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |   20 +-
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    | 1163 ++++++++++++++++++++
- .../drm/amd/dal/dc/dce110/dce110_clock_source.h    |   64 ++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   24 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |   67 +-
- drivers/gpu/drm/amd/dal/dc/gpu/Makefile            |    8 +-
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c |  407 -------
- .../gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h |   81 --
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h      |  141 ---
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.c    |  383 -------
- .../dal/dc/gpu/dce110/ext_clock_source_dce110.h    |   38 -
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.c    |  718 ------------
- .../dal/dc/gpu/dce110/pll_clock_source_dce110.h    |   55 -
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.c    |  193 ----
- .../dal/dc/gpu/dce110/vce_clock_source_dce110.h    |   32 -
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c  |  121 --
- drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h  |   47 -
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c  |  139 ---
- drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h  |   52 -
- drivers/gpu/drm/amd/dal/dc/inc/clock_source.h      |  176 +++
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |    2 +-
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |    1 +
- .../drm/amd/dal/include/clock_source_interface.h   |   89 --
- .../gpu/drm/amd/dal/include/clock_source_types.h   |  113 --
- 29 files changed, 1521 insertions(+), 2689 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/clock_source_interface.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/clock_source_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 0664af2..51a8589 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -33,7 +33,7 @@
- #include "resource.h"
- 
- #include "adapter_service_interface.h"
--#include "clock_source_interface.h"
-+#include "clock_source.h"
- #include "dc_bios_types.h"
- 
- #include "bandwidth_calcs.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index caba06e..a2879bb 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1215,7 +1215,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- 
- 	link->link_enc->funcs->enable_tmds_output(
- 			link->link_enc,
--			dal_clock_source_get_id(stream->clock_source),
-+			stream->clock_source->id,
- 			stream->public.timing.display_color_depth,
- 			stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
- 			stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 2aa8db1..52307cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -66,8 +66,7 @@ static bool is_sharable_clk_src(
- 	const struct core_stream *stream_with_clk_src,
- 	const struct core_stream *stream)
- {
--	enum clock_source_id id = dal_clock_source_get_id(
--					stream_with_clk_src->clock_source);
-+	enum clock_source_id id = stream_with_clk_src->clock_source->id;
- 
- 	if (stream_with_clk_src->clock_source == NULL)
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index c797642..60e5603 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -25,6 +25,7 @@
- #ifndef DC_TYPES_H_
- #define DC_TYPES_H_
- 
-+#include "dc_services_types.h"
- #include "fixed32_32.h"
- #include "fixed31_32.h"
- #include "irq_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 7ce1bb4..4027547 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -37,6 +37,7 @@
- #include "dce110/dce110_transform.h"
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
-+#include "dce110/dce110_clock_source.h"
- 
- #include "dce/dce_10_0_d.h"
- 
-@@ -134,6 +135,18 @@ static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
- 	}
- };
- 
-+
-+static const struct dce110_clk_src_reg_offsets dce100_clk_src_reg_offsets[] = {
-+	{
-+		.pll_cntl = mmBPHYC_PLL0_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK0_RESYNC_CNTL
-+	},
-+	{
-+		.pll_cntl = mmBPHYC_PLL1_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK1_RESYNC_CNTL
-+	}
-+};
-+
- static const struct dce110_transform_reg_offsets dce100_xfm_offsets[] = {
- {
- 	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
-@@ -486,6 +499,31 @@ void dce100_opp_destroy(struct output_pixel_processor **opp)
- 	*opp = NULL;
- }
- 
-+struct clock_source *dce100_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_reg_offsets *offsets)
-+{
-+	struct dce110_clk_src *clk_src =
-+		dc_service_alloc(ctx, sizeof(struct dce110_clk_src));
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id, offsets))
-+		return &clk_src->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce100_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	dc_service_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
- bool dce100_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
-@@ -493,7 +531,6 @@ bool dce100_construct_resource_pool(
- 	struct resource_pool *pool)
- {
- 	unsigned int i;
--	struct clock_source_init_data clk_src_init_data = { 0 };
- 	struct audio_init_data audio_init_data = { 0 };
- 	struct dc_context *ctx = dc->ctx;
- 
-@@ -506,22 +543,17 @@ bool dce100_construct_resource_pool(
- 	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
- 
--	clk_src_init_data.as = adapter_serv;
--	clk_src_init_data.ctx = ctx;
--	clk_src_init_data.clk_src_id.enum_id = ENUM_ID_1;
--	clk_src_init_data.clk_src_id.type = OBJECT_TYPE_CLOCK_SOURCE;
-+	pool->clock_sources[DCE100_CLK_SRC_PLL0] = dce100_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]);
-+	pool->clock_sources[DCE100_CLK_SRC_PLL1] = dce100_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]);
-+	pool->clock_sources[DCE100_CLK_SRC_EXT] =  dce100_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_EXTERNAL, &dce100_clk_src_reg_offsets[0]);
- 	pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
- 
--	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL0;
--	pool->clock_sources[DCE100_CLK_SRC_PLL0] = dal_clock_source_create(
--							&clk_src_init_data);
--	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL1;
--	pool->clock_sources[DCE100_CLK_SRC_PLL1] = dal_clock_source_create(
--							&clk_src_init_data);
--	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_EXTERNAL;
--	pool->clock_sources[DCE100_CLK_SRC_EXT] = dal_clock_source_create(
--							&clk_src_init_data);
--
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
- 			dal_error("DC: failed to create clock sources!\n");
-@@ -696,7 +728,7 @@ disp_clk_create_fail:
- clk_src_create_fail:
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] != NULL)
--			dal_clock_source_destroy(&pool->clock_sources[i]);
-+			dce100_clock_source_destroy(&pool->clock_sources[i]);
- 	}
- 	return false;
- }
-@@ -736,7 +768,7 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] != NULL)
--			dal_clock_source_destroy(&pool->clock_sources[i]);
-+			dce100_clock_source_destroy(&pool->clock_sources[i]);
- 	}
- 
- 	for (i = 0; i < pool->audio_count; i++)	{
-@@ -883,7 +915,7 @@ static enum dc_status build_stream_hw_param(struct core_stream *stream)
- 	stream->max_hdmi_pixel_clock = 600000;
- 
- 	get_pixel_clock_parameters(stream, &stream->pix_clk_params);
--	dal_clock_source_get_pix_clk_dividers(
-+	stream->clock_source->funcs->get_pix_clk_dividers(
- 		stream->clock_source,
- 		&stream->pix_clk_params,
- 		&stream->pll_settings);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-index 5bf9b56..ae9d2de 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -8,26 +8,8 @@ dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
- dce110_timing_generator.o dce110_transform.o dce110_transform_gamut.o \
- dce110_transform_scl.o dce110_transform_sclv.o dce110_opp_csc.o\
- dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
--dce110_resource.o dce110_transform_bit_depth.o
-+dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o
- 
- AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
- 
- AMD_DAL_FILES += $(AMD_DAL_DCE110)
--
--
--###############################################################################
--# DCE 11x
--###############################################################################
--ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
--TG_DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
--dce110_ipp_gamma.o dce110_timing_generator.o dce110_link_encoder.o \
--dce110_opp.o dce110_opp_regamma.o dce110_opp_formatter.o dce110_opp_csc.o \
--dce110_transform.o dce110_transform_gamut.o dce110_transform_bit_depth.o \
--dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o dce110_resource.o
--
--AMD_DAL_TG_DCE110 = $(addprefix \
--	$(AMDDALPATH)/dc/dce110/,$(TG_DCE110))
--
--AMD_DAL_FILES += $(AMD_DAL_TG_DCE110)
--endif
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-new file mode 100644
-index 0000000..b096444
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -0,0 +1,1163 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "core_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce110_clock_source.h"
-+
-+#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
-+#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
-+#define MAX_PLL_CALC_ERROR 0xFFFFFFFF
-+
-+static const struct spread_spectrum_data *get_ss_data_entry(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal,
-+		uint32_t pix_clk_khz)
-+{
-+
-+	uint32_t entrys_num;
-+	uint32_t i;
-+	struct spread_spectrum_data *ss_parm = NULL;
-+	struct spread_spectrum_data *ret = NULL;
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		ss_parm = clk_src->dvi_ss_params;
-+		entrys_num = clk_src->dvi_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		ss_parm = clk_src->hdmi_ss_params;
-+		entrys_num = clk_src->hdmi_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		ss_parm = clk_src->dp_ss_params;
-+		entrys_num = clk_src->dp_ss_params_cnt;
-+		break;
-+
-+	default:
-+		ss_parm = NULL;
-+		entrys_num = 0;
-+		break;
-+	}
-+
-+	if (ss_parm == NULL)
-+		return ret;
-+
-+	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
-+		if (ss_parm->freq_range_khz >= pix_clk_khz) {
-+			ret = ss_parm;
-+			break;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+* Function: calculate_fb_and_fractional_fb_divider
-+*
-+* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
-+*
-+*PARAMETERS:
-+* targetPixelClock             Desired frequency in 10 KHz
-+* ref_divider                  Reference divider (already known)
-+* postDivider                  Post Divider (already known)
-+* feedback_divider_param       Pointer where to store
-+*					calculated feedback divider value
-+* fract_feedback_divider_param Pointer where to store
-+*					calculated fract feedback divider value
-+*
-+*RETURNS:
-+* It fills the locations pointed by feedback_divider_param
-+*					and fract_feedback_divider_param
-+* It returns	- true if feedback divider not 0
-+*		- false should never happen)
-+*/
-+static bool calculate_fb_and_fractional_fb_divider(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		uint32_t target_pix_clk_khz,
-+		uint32_t ref_divider,
-+		uint32_t post_divider,
-+		uint32_t *feedback_divider_param,
-+		uint32_t *fract_feedback_divider_param)
-+{
-+	uint64_t feedback_divider;
-+
-+	feedback_divider =
-+		(uint64_t)(target_pix_clk_khz * ref_divider * post_divider);
-+	feedback_divider *= 10;
-+	/* additional factor, since we divide by 10 afterwards */
-+	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
-+	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
-+
-+/*Round to the number of precision
-+ * The following code replace the old code (ullfeedbackDivider + 5)/10
-+ * for example if the difference between the number
-+ * of fractional feedback decimal point and the fractional FB Divider precision
-+ * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
-+
-+	feedback_divider += (uint64_t)
-+			(5 * calc_pll_cs->fract_fb_divider_precision_factor);
-+	feedback_divider =
-+		div_u64(feedback_divider,
-+			calc_pll_cs->fract_fb_divider_precision_factor * 10);
-+	feedback_divider *= (uint64_t)
-+			(calc_pll_cs->fract_fb_divider_precision_factor);
-+
-+	*feedback_divider_param =
-+		div_u64_rem(
-+			feedback_divider,
-+			calc_pll_cs->fract_fb_divider_factor,
-+			fract_feedback_divider_param);
-+
-+	if (*feedback_divider_param != 0)
-+		return true;
-+	return false;
-+}
-+
-+/**
-+*calc_fb_divider_checking_tolerance
-+*
-+*DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
-+*		for passed Reference and Post divider, checking for tolerance.
-+*PARAMETERS:
-+* pll_settings		Pointer to structure
-+* ref_divider		Reference divider (already known)
-+* postDivider		Post Divider (already known)
-+* tolerance		Tolerance for Calculated Pixel Clock to be within
-+*
-+*RETURNS:
-+* It fills the PLLSettings structure with PLL Dividers values
-+* if calculated values are within required tolerance
-+* It returns	- true if eror is within tolerance
-+*		- false if eror is not within tolerance
-+*/
-+static bool calc_fb_divider_checking_tolerance(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings,
-+		uint32_t ref_divider,
-+		uint32_t post_divider,
-+		uint32_t tolerance)
-+{
-+	uint32_t feedback_divider;
-+	uint32_t fract_feedback_divider;
-+	uint32_t actual_calculated_clock_khz;
-+	uint32_t abs_err;
-+	uint64_t actual_calc_clk_khz;
-+
-+	calculate_fb_and_fractional_fb_divider(
-+			calc_pll_cs,
-+			pll_settings->adjusted_pix_clk,
-+			ref_divider,
-+			post_divider,
-+			&feedback_divider,
-+			&fract_feedback_divider);
-+
-+	/*Actual calculated value*/
-+	actual_calc_clk_khz = (uint64_t)(feedback_divider *
-+					calc_pll_cs->fract_fb_divider_factor) +
-+							fract_feedback_divider;
-+	actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
-+	actual_calc_clk_khz =
-+		div_u64(actual_calc_clk_khz,
-+			ref_divider * post_divider *
-+				calc_pll_cs->fract_fb_divider_factor);
-+
-+	actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
-+
-+	abs_err = (actual_calculated_clock_khz >
-+					pll_settings->adjusted_pix_clk)
-+			? actual_calculated_clock_khz -
-+					pll_settings->adjusted_pix_clk
-+			: pll_settings->adjusted_pix_clk -
-+						actual_calculated_clock_khz;
-+
-+	if (abs_err <= tolerance) {
-+		/*found good values*/
-+		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
-+		pll_settings->reference_divider = ref_divider;
-+		pll_settings->feedback_divider = feedback_divider;
-+		pll_settings->fract_feedback_divider = fract_feedback_divider;
-+		pll_settings->pix_clk_post_divider = post_divider;
-+		pll_settings->calculated_pix_clk =
-+			actual_calculated_clock_khz;
-+		pll_settings->vco_freq =
-+			actual_calculated_clock_khz * post_divider;
-+		return true;
-+	}
-+	return false;
-+}
-+
-+
-+static bool calc_pll_dividers_in_range(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings,
-+		uint32_t min_ref_divider,
-+		uint32_t max_ref_divider,
-+		uint32_t min_post_divider,
-+		uint32_t max_post_divider,
-+		uint32_t err_tolerance)
-+{
-+	uint32_t ref_divider;
-+	uint32_t post_divider;
-+	uint32_t tolerance;
-+
-+/* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
-+ * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
-+	tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
-+									10000;
-+	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
-+		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
-+
-+	for (
-+			post_divider = max_post_divider;
-+			post_divider >= min_post_divider;
-+			--post_divider) {
-+		for (
-+				ref_divider = min_ref_divider;
-+				ref_divider <= max_ref_divider;
-+				++ref_divider) {
-+			if (calc_fb_divider_checking_tolerance(
-+					calc_pll_cs,
-+					pll_settings,
-+					ref_divider,
-+					post_divider,
-+					tolerance)) {
-+				return true;
-+			}
-+		}
-+	}
-+
-+	return false;
-+}
-+
-+static uint32_t calculate_pixel_clock_pll_dividers(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings)
-+{
-+	uint32_t err_tolerance;
-+	uint32_t min_post_divider;
-+	uint32_t max_post_divider;
-+	uint32_t min_ref_divider;
-+	uint32_t max_ref_divider;
-+
-+	if (pll_settings->adjusted_pix_clk == 0) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s Bad requested pixel clock", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+/* 1) Find Post divider ranges */
-+	if (pll_settings->pix_clk_post_divider) {
-+		min_post_divider = pll_settings->pix_clk_post_divider;
-+		max_post_divider = pll_settings->pix_clk_post_divider;
-+	} else {
-+		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
-+		if (min_post_divider * pll_settings->adjusted_pix_clk <
-+						calc_pll_cs->min_vco_khz) {
-+			min_post_divider = calc_pll_cs->min_vco_khz /
-+					pll_settings->adjusted_pix_clk;
-+			if ((min_post_divider *
-+					pll_settings->adjusted_pix_clk) <
-+						calc_pll_cs->min_vco_khz)
-+				min_post_divider++;
-+		}
-+
-+		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
-+		if (max_post_divider * pll_settings->adjusted_pix_clk
-+				> calc_pll_cs->max_vco_khz)
-+			max_post_divider = calc_pll_cs->max_vco_khz /
-+					pll_settings->adjusted_pix_clk;
-+	}
-+
-+/* 2) Find Reference divider ranges
-+ * When SS is enabled, or for Display Port even without SS,
-+ * pll_settings->referenceDivider is not zero.
-+ * So calculate PPLL FB and fractional FB divider
-+ * using the passed reference divider*/
-+
-+	if (pll_settings->reference_divider) {
-+		min_ref_divider = pll_settings->reference_divider;
-+		max_ref_divider = pll_settings->reference_divider;
-+	} else {
-+		min_ref_divider = ((calc_pll_cs->ref_freq_khz
-+				/ calc_pll_cs->max_pll_input_freq_khz)
-+				> calc_pll_cs->min_pll_ref_divider)
-+			? calc_pll_cs->ref_freq_khz
-+					/ calc_pll_cs->max_pll_input_freq_khz
-+			: calc_pll_cs->min_pll_ref_divider;
-+
-+		max_ref_divider = ((calc_pll_cs->ref_freq_khz
-+				/ calc_pll_cs->min_pll_input_freq_khz)
-+				< calc_pll_cs->max_pll_ref_divider)
-+			? calc_pll_cs->ref_freq_khz /
-+					calc_pll_cs->min_pll_input_freq_khz
-+			: calc_pll_cs->max_pll_ref_divider;
-+	}
-+
-+/* If some parameters are invalid we could have scenario when  "min">"max"
-+ * which produced endless loop later.
-+ * We should investigate why we get the wrong parameters.
-+ * But to follow the similar logic when "adjustedPixelClock" is set to be 0
-+ * it is better to return here than cause system hang/watchdog timeout later.
-+ *  ## SVS Wed 15 Jul 2009 */
-+
-+	if (min_post_divider > max_post_divider) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s Post divider range is invalid", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+	if (min_ref_divider > max_ref_divider) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s Reference divider range is invalid", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+/* 3) Try to find PLL dividers given ranges
-+ * starting with minimal error tolerance.
-+ * Increase error tolerance until PLL dividers found*/
-+	err_tolerance = MAX_PLL_CALC_ERROR;
-+
-+	while (!calc_pll_dividers_in_range(
-+			calc_pll_cs,
-+			pll_settings,
-+			min_ref_divider,
-+			max_ref_divider,
-+			min_post_divider,
-+			max_post_divider,
-+			err_tolerance))
-+		err_tolerance += (err_tolerance > 10)
-+				? (err_tolerance / 10)
-+				: 1;
-+
-+	return err_tolerance;
-+}
-+
-+static bool pll_adjust_pix_clk(
-+		struct dce110_clk_src *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	uint32_t actual_pix_clk_khz = 0;
-+	uint32_t requested_clk_khz = 0;
-+	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
-+							0 };
-+	enum bp_result bp_result;
-+
-+	switch (pix_clk_params->signal_type) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A: {
-+		requested_clk_khz = pix_clk_params->requested_pix_clk;
-+
-+		switch (pix_clk_params->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			requested_clk_khz = (requested_clk_khz * 5) >> 2;
-+			break; /* x1.25*/
-+		case COLOR_DEPTH_121212:
-+			requested_clk_khz = (requested_clk_khz * 6) >> 2;
-+			break; /* x1.5*/
-+		case COLOR_DEPTH_161616:
-+			requested_clk_khz = requested_clk_khz * 2;
-+			break; /* x2.0*/
-+		default:
-+			break;
-+		}
-+
-+		actual_pix_clk_khz = requested_clk_khz;
-+	}
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		requested_clk_khz = pix_clk_params->requested_sym_clk;
-+		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
-+		break;
-+
-+	default:
-+		requested_clk_khz = pix_clk_params->requested_pix_clk;
-+		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
-+		break;
-+	}
-+
-+	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
-+	bp_adjust_pixel_clock_params.
-+		encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
-+	bp_adjust_pixel_clock_params.
-+		ss_enable = pix_clk_params->flags.ENABLE_SS;
-+	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
-+			clk_src->bios, &bp_adjust_pixel_clock_params);
-+	if (bp_result == BP_RESULT_OK) {
-+		pll_settings->actual_pix_clk = actual_pix_clk_khz;
-+		pll_settings->adjusted_pix_clk =
-+			bp_adjust_pixel_clock_params.adjusted_pixel_clock;
-+		pll_settings->reference_divider =
-+			bp_adjust_pixel_clock_params.reference_divider;
-+		pll_settings->pix_clk_post_divider =
-+			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+/**
-+ * Calculate PLL Dividers for given Clock Value.
-+ * First will call VBIOS Adjust Exec table to check if requested Pixel clock
-+ * will be Adjusted based on usage.
-+ * Then it will calculate PLL Dividers for this Adjusted clock using preferred
-+ * method (Maximum VCO frequency).
-+ *
-+ * \return
-+ *     Calculation error in units of 0.01%
-+ */
-+static uint32_t dce110_get_pix_clk_dividers(
-+		struct clock_source *cs,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
-+	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	if (pix_clk_params == NULL || pll_settings == NULL
-+			|| pix_clk_params->requested_pix_clk == 0) {
-+		dal_logger_write(clk_src->base.ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid parameters!!\n", __func__);
-+		return pll_calc_error;
-+	}
-+
-+	dc_service_memset(pll_settings, 0, sizeof(*pll_settings));
-+
-+	if (cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
-+		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-+		pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
-+		pll_settings->actual_pix_clk =
-+					pix_clk_params->requested_pix_clk;
-+		return 0;
-+	}
-+	/* PLL only after this point */
-+
-+	/* Check if reference clock is external (not pcie/xtalin)
-+	* HW Dce80 spec:
-+	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
-+	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
-+	addr = clk_src->offsets.pll_cntl;
-+	value = dal_read_reg(clk_src->base.ctx, addr);
-+	field = get_reg_field_value(value, PLL_CNTL, PLL_REF_DIV_SRC);
-+	pll_settings->use_external_clk = (field > 1);
-+
-+	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
-+	 * (we do not care any more from SI for some older DP Sink which
-+	 * does not report SS support, no known issues) */
-+	if ((pix_clk_params->flags.ENABLE_SS) ||
-+			(dc_is_dp_signal(pix_clk_params->signal_type))) {
-+
-+		const struct spread_spectrum_data *ss_data = get_ss_data_entry(
-+					clk_src,
-+					pix_clk_params->signal_type,
-+					pll_settings->adjusted_pix_clk);
-+
-+		if (NULL != ss_data)
-+			pll_settings->ss_percentage = ss_data->percentage;
-+	}
-+
-+	/* Check VBIOS AdjustPixelClock Exec table */
-+	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
-+		/* Should never happen, ASSERT and fill up values to be able
-+		 * to continue. */
-+		dal_logger_write(clk_src->base.ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Failed to adjust pixel clock!!", __func__);
-+		pll_settings->actual_pix_clk =
-+				pix_clk_params->requested_pix_clk;
-+		pll_settings->adjusted_pix_clk =
-+				pix_clk_params->requested_pix_clk;
-+
-+		if (dc_is_dp_signal(pix_clk_params->signal_type))
-+			pll_settings->adjusted_pix_clk = 100000;
-+	}
-+
-+	/* Calculate Dividers */
-+	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
-+		/*Calculate Dividers by HDMI object, no SS case or SS case */
-+		pll_calc_error =
-+			calculate_pixel_clock_pll_dividers(
-+					&clk_src->calc_pll_hdmi,
-+					pll_settings);
-+	else
-+		/*Calculate Dividers by default object, no SS case or SS case */
-+		pll_calc_error =
-+			calculate_pixel_clock_pll_dividers(
-+					&clk_src->calc_pll,
-+					pll_settings);
-+
-+	return pll_calc_error;
-+}
-+
-+static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
-+{
-+	enum bp_result result;
-+	struct bp_spread_spectrum_parameters bp_ss_params = {0};
-+
-+	bp_ss_params.pll_id = clk_src->base.id;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
-+			clk_src->bios,
-+			&bp_ss_params,
-+			false);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+static bool calculate_ss(
-+		const struct pll_settings *pll_settings,
-+		const struct spread_spectrum_data *ss_data,
-+		struct delta_sigma_data *ds_data)
-+{
-+	struct fixed32_32 fb_div;
-+	struct fixed32_32 ss_amount;
-+	struct fixed32_32 ss_nslip_amount;
-+	struct fixed32_32 ss_ds_frac_amount;
-+	struct fixed32_32 ss_step_size;
-+	struct fixed32_32 modulation_time;
-+
-+	if (ds_data == NULL)
-+		return false;
-+	if (ss_data == NULL)
-+		return false;
-+	if (ss_data->percentage == 0)
-+		return false;
-+	if (pll_settings == NULL)
-+		return false;
-+
-+
-+	dc_service_memset(ds_data, 0, sizeof(struct delta_sigma_data));
-+
-+
-+
-+	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
-+	/* 6 decimal point support in fractional feedback divider */
-+	fb_div  = dal_fixed32_32_from_fraction(
-+		pll_settings->fract_feedback_divider, 1000000);
-+	fb_div = dal_fixed32_32_add_int(fb_div, pll_settings->feedback_divider);
-+
-+	ds_data->ds_frac_amount = 0;
-+	/*spreadSpectrumPercentage is in the unit of .01%,
-+	 * so have to divided by 100 * 100*/
-+	ss_amount = dal_fixed32_32_mul(
-+		fb_div, dal_fixed32_32_from_fraction(ss_data->percentage,
-+					100 * ss_data->percentage_divider));
-+	ds_data->feedback_amount = dal_fixed32_32_floor(ss_amount);
-+
-+	ss_nslip_amount = dal_fixed32_32_sub(ss_amount,
-+		dal_fixed32_32_from_int(ds_data->feedback_amount));
-+	ss_nslip_amount = dal_fixed32_32_mul_int(ss_nslip_amount, 10);
-+	ds_data->nfrac_amount = dal_fixed32_32_floor(ss_nslip_amount);
-+
-+	ss_ds_frac_amount = dal_fixed32_32_sub(ss_nslip_amount,
-+		dal_fixed32_32_from_int(ds_data->nfrac_amount));
-+	ss_ds_frac_amount = dal_fixed32_32_mul_int(ss_ds_frac_amount, 65536);
-+	ds_data->ds_frac_amount = dal_fixed32_32_floor(ss_ds_frac_amount);
-+
-+	/* compute SS_STEP_SIZE_DSFRAC */
-+	modulation_time = dal_fixed32_32_from_fraction(
-+		pll_settings->reference_freq * 1000,
-+		pll_settings->reference_divider * ss_data->modulation_freq_hz);
-+
-+
-+	if (ss_data->flags.CENTER_SPREAD)
-+		modulation_time = dal_fixed32_32_div_int(modulation_time, 4);
-+	else
-+		modulation_time = dal_fixed32_32_div_int(modulation_time, 2);
-+
-+	ss_step_size = dal_fixed32_32_div(ss_amount, modulation_time);
-+	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
-+	ss_step_size = dal_fixed32_32_mul_int(ss_step_size, 65536 * 10);
-+	ds_data->ds_frac_size =  dal_fixed32_32_floor(ss_step_size);
-+
-+	return true;
-+}
-+
-+static bool enable_spread_spectrum(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal, struct pll_settings *pll_settings)
-+{
-+	struct bp_spread_spectrum_parameters bp_params = {0};
-+	struct delta_sigma_data d_s_data;
-+	const struct spread_spectrum_data *ss_data = NULL;
-+
-+	ss_data = get_ss_data_entry(
-+			clk_src,
-+			signal,
-+			pll_settings->calculated_pix_clk);
-+
-+/* Pixel clock PLL has been programmed to generate desired pixel clock,
-+ * now enable SS on pixel clock */
-+/* TODO is it OK to return true not doing anything ??*/
-+	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
-+		if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
-+			bp_params.ds.feedback_amount =
-+					d_s_data.feedback_amount;
-+			bp_params.ds.nfrac_amount =
-+					d_s_data.nfrac_amount;
-+			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
-+			bp_params.ds_frac_amount =
-+					d_s_data.ds_frac_amount;
-+			bp_params.flags.DS_TYPE = 1;
-+			bp_params.pll_id = clk_src->base.id;
-+			bp_params.percentage = ss_data->percentage;
-+			if (ss_data->flags.CENTER_SPREAD)
-+				bp_params.flags.CENTER_SPREAD = 1;
-+			if (ss_data->flags.EXTERNAL_SS)
-+				bp_params.flags.EXTERNAL_SS = 1;
-+
-+			if (BP_RESULT_OK !=
-+				clk_src->bios->funcs->
-+					enable_spread_spectrum_on_ppll(
-+							clk_src->bios,
-+							&bp_params,
-+							true))
-+				return false;
-+		} else
-+			return false;
-+	}
-+	return true;
-+}
-+
-+static void program_pixel_clk_resync(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal_type,
-+		enum dc_color_depth colordepth)
-+{
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(clk_src->base.ctx, clk_src->offsets.pixclk_resync_cntl);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		PIXCLK1_RESYNC_CNTL,
-+		DCCG_DEEP_COLOR_CNTL1);
-+
-+	/*
-+	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
-+	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
-+	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
-+	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
-+	 */
-+	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return;
-+
-+	switch (colordepth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			0,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			1,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			2,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	case COLOR_DEPTH_161616:
-+		set_reg_field_value(
-+			value,
-+			3,
-+			PIXCLK1_RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dal_write_reg(
-+		clk_src->base.ctx,
-+		clk_src->offsets.pixclk_resync_cntl,
-+		value);
-+}
-+
-+static bool dce110_program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
-+	struct bp_pixel_clock_parameters bp_pc_params = {0};
-+
-+	/* First disable SS
-+	 * ATOMBIOS will enable by default SS on PLL for DP,
-+	 * do not disable it here
-+	 */
-+	if (clk_src->id != CLOCK_SOURCE_ID_EXTERNAL &&
-+			!dc_is_dp_signal(pix_clk_params->signal_type))
-+		disable_spread_spectrum(dce110_clk_src);
-+
-+	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
-+	bp_pc_params.controller_id = pix_clk_params->controller_id;
-+	bp_pc_params.pll_id = clk_src->id;
-+	bp_pc_params.target_pixel_clock =
-+			pll_settings->actual_pix_clk;
-+	bp_pc_params.reference_divider = pll_settings->reference_divider;
-+	bp_pc_params.feedback_divider = pll_settings->feedback_divider;
-+	bp_pc_params.fractional_feedback_divider =
-+			pll_settings->fract_feedback_divider;
-+	bp_pc_params.pixel_clock_post_divider =
-+			pll_settings->pix_clk_post_divider;
-+	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_pc_params.signal_type = pix_clk_params->signal_type;
-+	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
-+					pll_settings->use_external_clk;
-+
-+	if (dce110_clk_src->bios->funcs->set_pixel_clock(
-+			dce110_clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+		return false;
-+
-+/* Enable SS
-+ * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
-+ * based on HW display PLL team, SS control settings should be programmed
-+ * during PLL Reset, but they do not have effect
-+ * until SS_EN is asserted.*/
-+	if (clk_src->id != CLOCK_SOURCE_ID_EXTERNAL
-+		&& pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal(
-+						pix_clk_params->signal_type))
-+		if (!enable_spread_spectrum(dce110_clk_src,
-+						pix_clk_params->signal_type,
-+						pll_settings))
-+			return false;
-+
-+/* Resync deep color DTO */
-+	if (clk_src->id != CLOCK_SOURCE_ID_EXTERNAL)
-+		program_pixel_clk_resync(dce110_clk_src,
-+					pix_clk_params->signal_type,
-+					pix_clk_params->color_depth);
-+
-+	return true;
-+}
-+
-+static bool dce110_clock_source_power_down(
-+		struct clock_source *clk_src, enum controller_id controller_id)
-+{
-+	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
-+	enum bp_result bp_result;
-+	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
-+
-+	if (clk_src->id == CLOCK_SOURCE_ID_EXTERNAL)
-+		return true;
-+
-+	/* If Pixel Clock is 0 it means Power Down Pll*/
-+	bp_pixel_clock_params.controller_id = controller_id;
-+	bp_pixel_clock_params.pll_id = clk_src->id;
-+	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
-+			dce110_clk_src->bios,
-+			&bp_pixel_clock_params);
-+
-+	return bp_result == BP_RESULT_OK;
-+}
-+
-+
-+/*****************************************/
-+/* Constructor                           */
-+/*****************************************/
-+static struct clock_source_funcs dce110_clk_src_funcs = {
-+	.cs_power_down = dce110_clock_source_power_down,
-+	.program_pix_clk = dce110_program_pix_clk,
-+	.get_pix_clk_dividers = dce110_get_pix_clk_dividers
-+};
-+
-+
-+static void get_ss_info_from_atombios(
-+		struct dce110_clk_src *clk_src,
-+		enum as_signal_type as_signal,
-+		struct spread_spectrum_data *spread_spectrum_data[],
-+		uint32_t *ss_entries_num)
-+{
-+	enum bp_result bp_result = BP_RESULT_FAILURE;
-+	struct spread_spectrum_info *ss_info;
-+	struct spread_spectrum_data *ss_data;
-+	struct spread_spectrum_info *ss_info_cur;
-+	struct spread_spectrum_data *ss_data_cur;
-+	uint32_t i;
-+
-+	if (ss_entries_num == NULL) {
-+		dal_logger_write(clk_src->base.ctx->logger,
-+			LOG_MAJOR_SYNC,
-+			LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+			"Invalid entry !!!\n");
-+		return;
-+	}
-+	if (spread_spectrum_data == NULL) {
-+		dal_logger_write(clk_src->base.ctx->logger,
-+			LOG_MAJOR_SYNC,
-+			LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+			"Invalid array pointer!!!\n");
-+		return;
-+	}
-+
-+	spread_spectrum_data[0] = NULL;
-+	*ss_entries_num = 0;
-+
-+	*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
-+			clk_src->bios,
-+			as_signal);
-+
-+	if (*ss_entries_num == 0)
-+		return;
-+
-+	ss_info = dc_service_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_info)
-+				* (*ss_entries_num));
-+	ss_info_cur = ss_info;
-+	if (ss_info == NULL)
-+		return;
-+
-+	ss_data = dc_service_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_data) *
-+							(*ss_entries_num));
-+	if (ss_data == NULL)
-+		goto out_free_info;
-+
-+	for (i = 0, ss_info_cur = ss_info;
-+		i < (*ss_entries_num);
-+		++i, ++ss_info_cur) {
-+
-+		bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
-+				clk_src->bios,
-+				as_signal,
-+				i,
-+				ss_info_cur);
-+
-+		if (bp_result != BP_RESULT_OK)
-+			goto out_free_data;
-+	}
-+
-+	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
-+		i < (*ss_entries_num);
-+		++i, ++ss_info_cur, ++ss_data_cur) {
-+
-+		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
-+			dal_logger_write(clk_src->base.ctx->logger,
-+				LOG_MAJOR_SYNC,
-+				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+				"Invalid ATOMBIOS SS Table!!!\n");
-+			goto out_free_data;
-+		}
-+
-+		/* for HDMI check SS percentage,
-+		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
-+		if (as_signal == AS_SIGNAL_TYPE_HDMI
-+				&& ss_info_cur->spread_spectrum_percentage > 6){
-+			/* invalid input, do nothing */
-+			dal_logger_write(clk_src->base.ctx->logger,
-+				LOG_MAJOR_SYNC,
-+				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+				"Invalid SS percentage ");
-+			dal_logger_write(clk_src->base.ctx->logger,
-+				LOG_MAJOR_SYNC,
-+				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
-+				"for HDMI in ATOMBIOS info Table!!!\n");
-+			continue;
-+		}
-+		if (ss_info_cur->spread_percentage_divider == 1000) {
-+			/* Keep previous precision from ATOMBIOS for these
-+			* in case new precision set by ATOMBIOS for these
-+			* (otherwise all code in DCE specific classes
-+			* for all previous ASICs would need
-+			* to be updated for SS calculations,
-+			* Audio SS compensation and DP DTO SS compensation
-+			* which assumes fixed SS percentage Divider = 100)*/
-+			ss_info_cur->spread_spectrum_percentage /= 10;
-+			ss_info_cur->spread_percentage_divider = 100;
-+		}
-+
-+		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
-+		ss_data_cur->percentage =
-+				ss_info_cur->spread_spectrum_percentage;
-+		ss_data_cur->percentage_divider =
-+				ss_info_cur->spread_percentage_divider;
-+		ss_data_cur->modulation_freq_hz =
-+				ss_info_cur->spread_spectrum_range;
-+
-+		if (ss_info_cur->type.CENTER_MODE)
-+			ss_data_cur->flags.CENTER_SPREAD = 1;
-+
-+		if (ss_info_cur->type.EXTERNAL)
-+			ss_data_cur->flags.EXTERNAL_SS = 1;
-+
-+	}
-+
-+	*spread_spectrum_data = ss_data;
-+	dc_service_free(clk_src->base.ctx, ss_info);
-+	return;
-+
-+out_free_data:
-+	dc_service_free(clk_src->base.ctx, ss_data);
-+	*ss_entries_num = 0;
-+out_free_info:
-+	dc_service_free(clk_src->base.ctx, ss_info);
-+}
-+
-+static void ss_info_from_atombios_create(
-+	struct dce110_clk_src *clk_src)
-+{
-+	get_ss_info_from_atombios(
-+		clk_src,
-+		AS_SIGNAL_TYPE_DISPLAY_PORT,
-+		&clk_src->dp_ss_params,
-+		&clk_src->dp_ss_params_cnt);
-+	get_ss_info_from_atombios(
-+		clk_src,
-+		AS_SIGNAL_TYPE_HDMI,
-+		&clk_src->hdmi_ss_params,
-+		&clk_src->hdmi_ss_params_cnt);
-+	get_ss_info_from_atombios(
-+		clk_src,
-+		AS_SIGNAL_TYPE_DVI,
-+		&clk_src->dvi_ss_params,
-+		&clk_src->dvi_ss_params_cnt);
-+}
-+
-+static bool calc_pll_max_vco_construct(
-+			struct calc_pll_clock_source *calc_pll_cs,
-+			struct calc_pll_clock_source_init_data *init_data)
-+{
-+	uint32_t i;
-+	struct firmware_info fw_info = { { 0 } };
-+	if (calc_pll_cs == NULL ||
-+			init_data == NULL ||
-+			init_data->bp == NULL)
-+		return false;
-+
-+	if (init_data->bp->funcs->get_firmware_info(
-+				init_data->bp,
-+				&fw_info) != BP_RESULT_OK)
-+		return false;
-+
-+	calc_pll_cs->ctx = init_data->ctx;
-+	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+	calc_pll_cs->min_vco_khz =
-+			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
-+	calc_pll_cs->max_vco_khz =
-+			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
-+
-+	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
-+		calc_pll_cs->max_pll_input_freq_khz =
-+			init_data->max_override_input_pxl_clk_pll_freq_khz;
-+	else
-+		calc_pll_cs->max_pll_input_freq_khz =
-+			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
-+
-+	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
-+		calc_pll_cs->min_pll_input_freq_khz =
-+			init_data->min_override_input_pxl_clk_pll_freq_khz;
-+	else
-+		calc_pll_cs->min_pll_input_freq_khz =
-+			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
-+
-+	calc_pll_cs->min_pix_clock_pll_post_divider =
-+			init_data->min_pix_clk_pll_post_divider;
-+	calc_pll_cs->max_pix_clock_pll_post_divider =
-+			init_data->max_pix_clk_pll_post_divider;
-+	calc_pll_cs->min_pll_ref_divider =
-+			init_data->min_pll_ref_divider;
-+	calc_pll_cs->max_pll_ref_divider =
-+			init_data->max_pll_ref_divider;
-+
-+	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
-+		init_data->num_fract_fb_divider_decimal_point_precision >
-+				init_data->num_fract_fb_divider_decimal_point) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"The dec point num or precision is incorrect!");
-+		return false;
-+	}
-+	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
-+		dal_logger_write(calc_pll_cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Incorrect fract feedback divider precision num!");
-+		return false;
-+	}
-+
-+	calc_pll_cs->fract_fb_divider_decimal_points_num =
-+				init_data->num_fract_fb_divider_decimal_point;
-+	calc_pll_cs->fract_fb_divider_precision =
-+			init_data->num_fract_fb_divider_decimal_point_precision;
-+	calc_pll_cs->fract_fb_divider_factor = 1;
-+	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
-+		calc_pll_cs->fract_fb_divider_factor *= 10;
-+
-+	calc_pll_cs->fract_fb_divider_precision_factor = 1;
-+	for (
-+		i = 0;
-+		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
-+				calc_pll_cs->fract_fb_divider_precision);
-+		++i)
-+		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
-+
-+	return true;
-+}
-+
-+bool dce110_clk_src_construct(
-+	struct dce110_clk_src *clk_src,
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_reg_offsets *reg_offsets)
-+{
-+	struct firmware_info fw_info = { { 0 } };
-+/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
-+	struct calc_pll_clock_source_init_data calc_pll_cs_init_data = {
-+		bios,
-+		1, /* minPixelClockPLLPostDivider */
-+		PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK,
-+		/* maxPixelClockPLLPostDivider*/
-+		1,/* minPLLRefDivider*/
-+		PLL_REF_DIV__PLL_REF_DIV_MASK,/* maxPLLRefDivider*/
-+		0,
-+/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		0,
-+/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+/*numberOfFractFBDividerDecimalPoints*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+/*number of decimal point to round off for fractional feedback divider value*/
-+		ctx
-+	};
-+/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
-+	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi = {
-+		bios,
-+		1, /* minPixelClockPLLPostDivider */
-+		PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK,
-+		/* maxPixelClockPLLPostDivider*/
-+		1,/* minPLLRefDivider*/
-+		PLL_REF_DIV__PLL_REF_DIV_MASK,/* maxPLLRefDivider*/
-+		13500,
-+	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		27000,
-+	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+		/*numberOfFractFBDividerDecimalPoints*/
-+		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
-+/*number of decimal point to round off for fractional feedback divider value*/
-+		ctx
-+	};
-+
-+	clk_src->base.ctx = ctx;
-+	clk_src->bios = bios;
-+	clk_src->base.id = id;
-+	clk_src->base.funcs = &dce110_clk_src_funcs;
-+	clk_src->offsets = *reg_offsets;
-+
-+	if (clk_src->bios->funcs->get_firmware_info(
-+			clk_src->bios, &fw_info) != BP_RESULT_OK) {
-+		ASSERT_CRITICAL(false);
-+		goto unexpected_failure;
-+	}
-+
-+	clk_src->ext_clk_khz =
-+			fw_info.external_clock_source_frequency_for_dp;
-+	clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+
-+	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
-+		return true;
-+
-+	/* PLL only from here on */
-+	ss_info_from_atombios_create(clk_src);
-+
-+	if (!calc_pll_max_vco_construct(
-+			&clk_src->calc_pll,
-+			&calc_pll_cs_init_data)) {
-+		ASSERT_CRITICAL(false);
-+		goto unexpected_failure;
-+	}
-+
-+	if (clk_src->ref_freq_khz == 48000) {
-+		calc_pll_cs_init_data_hdmi.
-+			min_override_input_pxl_clk_pll_freq_khz = 24000;
-+		calc_pll_cs_init_data_hdmi.
-+			max_override_input_pxl_clk_pll_freq_khz = 48000;
-+	} else if (clk_src->ref_freq_khz == 100000) {
-+		calc_pll_cs_init_data_hdmi.
-+			min_override_input_pxl_clk_pll_freq_khz = 25000;
-+		calc_pll_cs_init_data_hdmi.
-+			max_override_input_pxl_clk_pll_freq_khz = 50000;
-+	}
-+
-+	if (!calc_pll_max_vco_construct(
-+			&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
-+		ASSERT_CRITICAL(false);
-+		goto unexpected_failure;
-+	}
-+
-+	return true;
-+
-+unexpected_failure:
-+	return false;
-+}
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.h
-new file mode 100644
-index 0000000..4fa82da
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.h
-@@ -0,0 +1,64 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_CLOCK_SOURCE_DCE110_H__
-+#define __DC_CLOCK_SOURCE_DCE110_H__
-+
-+#include "../inc/clock_source.h"
-+
-+#define TO_DCE110_CLK_SRC(clk_src)\
-+	container_of(clk_src, struct dce110_clk_src, base)
-+
-+struct dce110_clk_src_reg_offsets {
-+	uint32_t pll_cntl;
-+	uint32_t pixclk_resync_cntl;
-+};
-+
-+struct dce110_clk_src {
-+	struct clock_source base;
-+	struct dce110_clk_src_reg_offsets offsets;
-+	struct dc_bios *bios;
-+
-+	struct spread_spectrum_data *dp_ss_params;
-+	uint32_t dp_ss_params_cnt;
-+	struct spread_spectrum_data *hdmi_ss_params;
-+	uint32_t hdmi_ss_params_cnt;
-+	struct spread_spectrum_data *dvi_ss_params;
-+	uint32_t dvi_ss_params_cnt;
-+
-+	uint32_t ext_clk_khz;
-+	uint32_t ref_freq_khz;
-+
-+	struct calc_pll_clock_source calc_pll;
-+	struct calc_pll_clock_source calc_pll_hdmi;
-+};
-+
-+bool dce110_clk_src_construct(
-+	struct dce110_clk_src *clk_src,
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id,
-+	const struct dce110_clk_src_reg_offsets *reg_offsets);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index e716219..af7cf0d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -33,13 +33,14 @@
- 
- #include "dce110/dce110_resource.h"
- #include "dce110/dce110_timing_generator.h"
--#include "dce110/dce110_link_encoder.h"
--#include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_mem_input.h"
--#include "dce110/dce110_ipp.h"
--#include "dce110/dce110_transform.h"
- #include "dce110/dce110_opp.h"
- #include "gpu/dce110/dc_clock_gating_dce110.h"
-+#include "ipp.h"
-+#include "transform.h"
-+#include "stream_encoder.h"
-+#include "link_encoder.h"
-+#include "inc/clock_source.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -806,7 +807,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		core_link_disable_stream(stream->sink->link, stream);
- 
- 		/*TODO: AUTO check if timing changed*/
--		if (false == dal_clock_source_program_pix_clk(
-+		if (false == stream->clock_source->funcs->program_pix_clk(
- 				stream->clock_source,
- 				&stream->pix_clk_params,
- 				&stream->pll_settings)) {
-@@ -932,13 +933,9 @@ static void power_down_clock_sources(struct dc *dc)
- 	int i;
- 
- 	for (i = 0; i < dc->res_pool.clk_src_count; i++) {
--		if (false == dal_clock_source_power_down_pll(
--				dc->res_pool.clock_sources[i],
--				i+1)) {
--			dal_error(
--				"Failed to power down pll! (clk src index=%d)\n",
--				i);
--		}
-+		if (dc->res_pool.clock_sources[i]->funcs->cs_power_down(
-+				dc->res_pool.clock_sources[i], i+1) == false)
-+			dal_error("Failed to power down pll! (clk src index=%d)\n", i);
- 	}
- }
- 
-@@ -1200,7 +1197,7 @@ static void dce110_switch_dp_clk_src(
- {
- 	uint32_t pixel_rate_cntl_value;
- 	uint32_t addr;
--	enum clock_source_id id = dal_clock_source_get_id(stream->clock_source);
-+	enum clock_source_id id = stream->clock_source->id;
- 
- 	/*TODO: proper offset*/
- 	addr = mmCRTC0_PIXEL_RATE_CNTL + stream->controller_idx *
-@@ -1761,7 +1758,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.encoder_create = dce110_link_encoder_create,
- 	.encoder_destroy = dce110_link_encoder_destroy,
- 	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
--	.transform_power_up = dce110_transform_power_up,
- 	.construct_resource_pool = dce110_construct_resource_pool,
- 	.destruct_resource_pool = dce110_destruct_resource_pool,
- 	.validate_with_context = dce110_validate_with_context,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index bd9f311..41717eb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -39,6 +39,7 @@
- #include "dce110/dce110_transform.h"
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
-+#include "dce110/dce110_clock_source.h"
- 
- #include "dce/dce_11_0_d.h"
- 
-@@ -283,6 +284,17 @@ static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = {
- };
- 
- 
-+static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = {
-+	{
-+		.pll_cntl = mmBPHYC_PLL0_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK0_RESYNC_CNTL
-+	},
-+	{
-+		.pll_cntl = mmBPHYC_PLL1_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK1_RESYNC_CNTL
-+	}
-+};
-+
- static struct timing_generator *dce110_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -438,6 +450,31 @@ static struct output_pixel_processor *dce110_opp_create(
- 	return NULL;
- }
- 
-+struct clock_source *dce110_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_reg_offsets *offsets)
-+{
-+	struct dce110_clk_src *clk_src =
-+		dc_service_alloc(ctx, sizeof(struct dce110_clk_src));
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id, offsets))
-+		return &clk_src->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce110_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	dc_service_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
-@@ -445,7 +482,6 @@ bool dce110_construct_resource_pool(
- 	struct resource_pool *pool)
- {
- 	unsigned int i;
--	struct clock_source_init_data clk_src_init_data = { 0 };
- 	struct audio_init_data audio_init_data = { 0 };
- 	struct dc_context *ctx = dc->ctx;
- 	pool->adapter_srv = adapter_serv;
-@@ -457,22 +493,17 @@ bool dce110_construct_resource_pool(
- 	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
- 
--	clk_src_init_data.as = adapter_serv;
--	clk_src_init_data.ctx = ctx;
--	clk_src_init_data.clk_src_id.enum_id = ENUM_ID_1;
--	clk_src_init_data.clk_src_id.type = OBJECT_TYPE_CLOCK_SOURCE;
-+	pool->clock_sources[DCE110_CLK_SRC_PLL0] = dce110_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL0, &dce110_clk_src_reg_offsets[0]);
-+	pool->clock_sources[DCE110_CLK_SRC_PLL1] = dce110_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL1, &dce110_clk_src_reg_offsets[1]);
-+	pool->clock_sources[DCE110_CLK_SRC_EXT] =  dce110_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_EXTERNAL, &dce110_clk_src_reg_offsets[0]);
- 	pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
- 
--	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL0;
--	pool->clock_sources[DCE110_CLK_SRC_PLL0] = dal_clock_source_create(
--							&clk_src_init_data);
--	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_PLL1;
--	pool->clock_sources[DCE110_CLK_SRC_PLL1] = dal_clock_source_create(
--							&clk_src_init_data);
--	clk_src_init_data.clk_src_id.id = CLOCK_SOURCE_ID_EXTERNAL;
--	pool->clock_sources[DCE110_CLK_SRC_EXT] = dal_clock_source_create(
--							&clk_src_init_data);
--
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
- 			dal_error("DC: failed to create clock sources!\n");
-@@ -658,7 +689,7 @@ disp_clk_create_fail:
- clk_src_create_fail:
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] != NULL)
--			dal_clock_source_destroy(&pool->clock_sources[i]);
-+			dce110_clock_source_destroy(&pool->clock_sources[i]);
- 	}
- 	return false;
- }
-@@ -697,7 +728,7 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] != NULL) {
--			dal_clock_source_destroy(&pool->clock_sources[i]);
-+			dce110_clock_source_destroy(&pool->clock_sources[i]);
- 		}
- 	}
- 
-@@ -846,7 +877,7 @@ static enum dc_status build_stream_hw_param(struct core_stream *stream)
- 	stream->max_hdmi_pixel_clock = 600000;
- 
- 	get_pixel_clock_parameters(stream, &stream->pix_clk_params);
--	dal_clock_source_get_pix_clk_dividers(
-+	stream->clock_source->funcs->get_pix_clk_dividers(
- 		stream->clock_source,
- 		&stream->pix_clk_params,
- 		&stream->pll_settings);
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-index d3d6faf..b481a6d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-@@ -3,9 +3,7 @@
- # It provides the control and status of HW adapter resources,
- # that are global for the ASIC and sharable between pipes.
- 
--GPU = calc_pll_clock_source.o clock_source.o \
--dc_clock_generator.o display_clock.o divider_range.o \
--ext_clock_source.o pll_clock_source.o
-+GPU = dc_clock_generator.o display_clock.o divider_range.o
- 
- AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
- 
-@@ -16,9 +14,7 @@ AMD_DAL_FILES += $(AMD_DAL_GPU)
- # DCE 110 family
- ###############################################################################
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
--GPU_DCE110 = display_clock_dce110.o \
--	pll_clock_source_dce110.o ext_clock_source_dce110.o \
--	vce_clock_source_dce110.o dc_clock_gating_dce110.o
-+GPU_DCE110 = display_clock_dce110.o dc_clock_gating_dce110.o
- 
- AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-deleted file mode 100644
-index 4947d73..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.c
-+++ /dev/null
-@@ -1,407 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--
--#include "calc_pll_clock_source.h"
--#include "include/bios_parser_interface.h"
--#include "include/logger_interface.h"
--
--/**
--* Function: calculate_fb_and_fractional_fb_divider
--*
--* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
--*
--*PARAMETERS:
--* targetPixelClock             Desired frequency in 10 KHz
--* ref_divider                  Reference divider (already known)
--* postDivider                  Post Divider (already known)
--* feedback_divider_param       Pointer where to store
--*					calculated feedback divider value
--* fract_feedback_divider_param Pointer where to store
--*					calculated fract feedback divider value
--*
--*RETURNS:
--* It fills the locations pointed by feedback_divider_param
--*					and fract_feedback_divider_param
--* It returns	- true if feedback divider not 0
--*		- false should never happen)
--*/
--static bool calculate_fb_and_fractional_fb_divider(
--		struct calc_pll_clock_source *calc_pll_cs,
--		uint32_t target_pix_clk_khz,
--		uint32_t ref_divider,
--		uint32_t post_divider,
--		uint32_t *feedback_divider_param,
--		uint32_t *fract_feedback_divider_param)
--{
--	uint64_t feedback_divider;
--
--	feedback_divider =
--		(uint64_t)(target_pix_clk_khz * ref_divider * post_divider);
--	feedback_divider *= 10;
--	/* additional factor, since we divide by 10 afterwards */
--	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
--	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
--
--/*Round to the number of precision
-- * The following code replace the old code (ullfeedbackDivider + 5)/10
-- * for example if the difference between the number
-- * of fractional feedback decimal point and the fractional FB Divider precision
-- * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
--
--	feedback_divider += (uint64_t)
--			(5 * calc_pll_cs->fract_fb_divider_precision_factor);
--	feedback_divider =
--		div_u64(feedback_divider,
--			calc_pll_cs->fract_fb_divider_precision_factor * 10);
--	feedback_divider *= (uint64_t)
--			(calc_pll_cs->fract_fb_divider_precision_factor);
--
--	*feedback_divider_param =
--		div_u64_rem(
--			feedback_divider,
--			calc_pll_cs->fract_fb_divider_factor,
--			fract_feedback_divider_param);
--
--	if (*feedback_divider_param != 0)
--		return true;
--	return false;
--}
--
--/**
--*calc_fb_divider_checking_tolerance
--*
--*DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
--*		for passed Reference and Post divider, checking for tolerance.
--*PARAMETERS:
--* pll_settings		Pointer to structure
--* ref_divider		Reference divider (already known)
--* postDivider		Post Divider (already known)
--* tolerance		Tolerance for Calculated Pixel Clock to be within
--*
--*RETURNS:
--* It fills the PLLSettings structure with PLL Dividers values
--* if calculated values are within required tolerance
--* It returns	- true if eror is within tolerance
--*		- false if eror is not within tolerance
--*/
--static bool calc_fb_divider_checking_tolerance(
--		struct calc_pll_clock_source *calc_pll_cs,
--		struct pll_settings *pll_settings,
--		uint32_t ref_divider,
--		uint32_t post_divider,
--		uint32_t tolerance)
--{
--	uint32_t feedback_divider;
--	uint32_t fract_feedback_divider;
--	uint32_t actual_calculated_clock_khz;
--	uint32_t abs_err;
--	uint64_t actual_calc_clk_khz;
--
--	calculate_fb_and_fractional_fb_divider(
--			calc_pll_cs,
--			pll_settings->adjusted_pix_clk,
--			ref_divider,
--			post_divider,
--			&feedback_divider,
--			&fract_feedback_divider);
--
--	/*Actual calculated value*/
--	actual_calc_clk_khz = (uint64_t)(feedback_divider *
--					calc_pll_cs->fract_fb_divider_factor) +
--							fract_feedback_divider;
--	actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
--	actual_calc_clk_khz =
--		div_u64(actual_calc_clk_khz,
--			ref_divider * post_divider *
--				calc_pll_cs->fract_fb_divider_factor);
--
--	actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
--
--	abs_err = (actual_calculated_clock_khz >
--					pll_settings->adjusted_pix_clk)
--			? actual_calculated_clock_khz -
--					pll_settings->adjusted_pix_clk
--			: pll_settings->adjusted_pix_clk -
--						actual_calculated_clock_khz;
--
--	if (abs_err <= tolerance) {
--		/*found good values*/
--		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
--		pll_settings->reference_divider = ref_divider;
--		pll_settings->feedback_divider = feedback_divider;
--		pll_settings->fract_feedback_divider = fract_feedback_divider;
--		pll_settings->pix_clk_post_divider = post_divider;
--		pll_settings->calculated_pix_clk =
--			actual_calculated_clock_khz;
--		pll_settings->vco_freq =
--			actual_calculated_clock_khz * post_divider;
--		return true;
--	}
--	return false;
--}
--
--static bool calc_pll_dividers_in_range(
--		struct calc_pll_clock_source *calc_pll_cs,
--		struct pll_settings *pll_settings,
--		uint32_t min_ref_divider,
--		uint32_t max_ref_divider,
--		uint32_t min_post_divider,
--		uint32_t max_post_divider,
--		uint32_t err_tolerance)
--{
--	uint32_t ref_divider;
--	uint32_t post_divider;
--	uint32_t tolerance;
--
--/* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
-- * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
--	tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
--									10000;
--	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
--		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
--
--	for (
--			post_divider = max_post_divider;
--			post_divider >= min_post_divider;
--			--post_divider) {
--		for (
--				ref_divider = min_ref_divider;
--				ref_divider <= max_ref_divider;
--				++ref_divider) {
--			if (calc_fb_divider_checking_tolerance(
--					calc_pll_cs,
--					pll_settings,
--					ref_divider,
--					post_divider,
--					tolerance)) {
--				return true;
--			}
--		}
--	}
--
--	return false;
--}
--
--uint32_t dal_clock_source_calculate_pixel_clock_pll_dividers(
--		struct calc_pll_clock_source *calc_pll_cs,
--		struct pll_settings *pll_settings)
--{
--	uint32_t err_tolerance;
--	uint32_t min_post_divider;
--	uint32_t max_post_divider;
--	uint32_t min_ref_divider;
--	uint32_t max_ref_divider;
--
--	if (pll_settings->adjusted_pix_clk == 0) {
--		dal_logger_write(calc_pll_cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s Bad requested pixel clock", __func__);
--		return MAX_PLL_CALC_ERROR;
--	}
--
--/* 1) Find Post divider ranges */
--	if (pll_settings->pix_clk_post_divider) {
--		min_post_divider = pll_settings->pix_clk_post_divider;
--		max_post_divider = pll_settings->pix_clk_post_divider;
--	} else {
--		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
--		if (min_post_divider * pll_settings->adjusted_pix_clk <
--						calc_pll_cs->min_vco_khz) {
--			min_post_divider = calc_pll_cs->min_vco_khz /
--					pll_settings->adjusted_pix_clk;
--			if ((min_post_divider *
--					pll_settings->adjusted_pix_clk) <
--						calc_pll_cs->min_vco_khz)
--				min_post_divider++;
--		}
--
--		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
--		if (max_post_divider * pll_settings->adjusted_pix_clk
--				> calc_pll_cs->max_vco_khz)
--			max_post_divider = calc_pll_cs->max_vco_khz /
--					pll_settings->adjusted_pix_clk;
--	}
--
--/* 2) Find Reference divider ranges
-- * When SS is enabled, or for Display Port even without SS,
-- * pll_settings->referenceDivider is not zero.
-- * So calculate PPLL FB and fractional FB divider
-- * using the passed reference divider*/
--
--	if (pll_settings->reference_divider) {
--		min_ref_divider = pll_settings->reference_divider;
--		max_ref_divider = pll_settings->reference_divider;
--	} else {
--		min_ref_divider = ((calc_pll_cs->ref_freq_khz
--				/ calc_pll_cs->max_pll_input_freq_khz)
--				> calc_pll_cs->min_pll_ref_divider)
--			? calc_pll_cs->ref_freq_khz
--					/ calc_pll_cs->max_pll_input_freq_khz
--			: calc_pll_cs->min_pll_ref_divider;
--
--		max_ref_divider = ((calc_pll_cs->ref_freq_khz
--				/ calc_pll_cs->min_pll_input_freq_khz)
--				< calc_pll_cs->max_pll_ref_divider)
--			? calc_pll_cs->ref_freq_khz /
--					calc_pll_cs->min_pll_input_freq_khz
--			: calc_pll_cs->max_pll_ref_divider;
--	}
--
--/* If some parameters are invalid we could have scenario when  "min">"max"
-- * which produced endless loop later.
-- * We should investigate why we get the wrong parameters.
-- * But to follow the similar logic when "adjustedPixelClock" is set to be 0
-- * it is better to return here than cause system hang/watchdog timeout later.
-- *  ## SVS Wed 15 Jul 2009 */
--
--	if (min_post_divider > max_post_divider) {
--		dal_logger_write(calc_pll_cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s Post divider range is invalid", __func__);
--		return MAX_PLL_CALC_ERROR;
--	}
--
--	if (min_ref_divider > max_ref_divider) {
--		dal_logger_write(calc_pll_cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s Reference divider range is invalid", __func__);
--		return MAX_PLL_CALC_ERROR;
--	}
--
--/* 3) Try to find PLL dividers given ranges
-- * starting with minimal error tolerance.
-- * Increase error tolerance until PLL dividers found*/
--	err_tolerance = MAX_PLL_CALC_ERROR;
--
--	while (!calc_pll_dividers_in_range(
--			calc_pll_cs,
--			pll_settings,
--			min_ref_divider,
--			max_ref_divider,
--			min_post_divider,
--			max_post_divider,
--			err_tolerance))
--		err_tolerance += (err_tolerance > 10)
--				? (err_tolerance / 10)
--				: 1;
--
--	return err_tolerance;
--}
--
--static bool calc_pll_clock_source_max_vco_construct(
--			struct calc_pll_clock_source *calc_pll_cs,
--			struct calc_pll_clock_source_init_data *init_data)
--{
--
--	uint32_t i;
--	struct firmware_info fw_info = { { 0 } };
--	if (calc_pll_cs == NULL ||
--			init_data == NULL ||
--			init_data->bp == NULL)
--		return false;
--
--	if (init_data->bp->funcs->get_firmware_info(
--				init_data->bp,
--				&fw_info) != BP_RESULT_OK)
--		return false;
--
--	calc_pll_cs->ctx = init_data->ctx;
--	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
--	calc_pll_cs->min_vco_khz =
--			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
--	calc_pll_cs->max_vco_khz =
--			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
--
--	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
--		calc_pll_cs->max_pll_input_freq_khz =
--			init_data->max_override_input_pxl_clk_pll_freq_khz;
--	else
--		calc_pll_cs->max_pll_input_freq_khz =
--			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
--
--	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
--		calc_pll_cs->min_pll_input_freq_khz =
--			init_data->min_override_input_pxl_clk_pll_freq_khz;
--	else
--		calc_pll_cs->min_pll_input_freq_khz =
--			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
--
--	calc_pll_cs->min_pix_clock_pll_post_divider =
--			init_data->min_pix_clk_pll_post_divider;
--	calc_pll_cs->max_pix_clock_pll_post_divider =
--			init_data->max_pix_clk_pll_post_divider;
--	calc_pll_cs->min_pll_ref_divider =
--			init_data->min_pll_ref_divider;
--	calc_pll_cs->max_pll_ref_divider =
--			init_data->max_pll_ref_divider;
--
--	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
--		init_data->num_fract_fb_divider_decimal_point_precision >
--				init_data->num_fract_fb_divider_decimal_point) {
--		dal_logger_write(calc_pll_cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"The dec point num or precision is incorrect!");
--		return false;
--	}
--	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
--		dal_logger_write(calc_pll_cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"Incorrect fract feedback divider precision num!");
--		return false;
--	}
--
--	calc_pll_cs->fract_fb_divider_decimal_points_num =
--				init_data->num_fract_fb_divider_decimal_point;
--	calc_pll_cs->fract_fb_divider_precision =
--			init_data->num_fract_fb_divider_decimal_point_precision;
--	calc_pll_cs->fract_fb_divider_factor = 1;
--	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
--		calc_pll_cs->fract_fb_divider_factor *= 10;
--
--	calc_pll_cs->fract_fb_divider_precision_factor = 1;
--	for (
--		i = 0;
--		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
--				calc_pll_cs->fract_fb_divider_precision);
--		++i)
--		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
--
--	return true;
--}
--
--bool dal_calc_pll_clock_source_max_vco_init(
--		struct calc_pll_clock_source *calc_pll_cs,
--		struct calc_pll_clock_source_init_data *init_data)
--{
--	return calc_pll_clock_source_max_vco_construct(
--			calc_pll_cs, init_data);
--}
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-deleted file mode 100644
-index 48db3d6..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/calc_pll_clock_source.h
-+++ /dev/null
-@@ -1,81 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_CALC_PLL_CLOCK_SOURCE_H__
--#define __DAL_CALC_PLL_CLOCK_SOURCE_H__
--
--#include "dc_bios_types.h"
--
--#include "include/clock_source_types.h"
--
--struct calc_pll_clock_source_init_data {
--	struct dc_bios *bp;
--	uint32_t min_pix_clk_pll_post_divider;
--	uint32_t max_pix_clk_pll_post_divider;
--	uint32_t min_pll_ref_divider;
--	uint32_t max_pll_ref_divider;
--	uint32_t min_override_input_pxl_clk_pll_freq_khz;
--/* if not 0, override the firmware info */
--
--	uint32_t max_override_input_pxl_clk_pll_freq_khz;
--/* if not 0, override the firmware info */
--
--	uint32_t num_fract_fb_divider_decimal_point;
--/* number of decimal point for fractional feedback divider value */
--
--	uint32_t num_fract_fb_divider_decimal_point_precision;
--/* number of decimal point to round off for fractional feedback divider value*/
--	struct dc_context *ctx;
--
--};
--#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
--struct calc_pll_clock_source {
--	uint32_t ref_freq_khz;
--	uint32_t min_pix_clock_pll_post_divider;
--	uint32_t max_pix_clock_pll_post_divider;
--	uint32_t min_pll_ref_divider;
--	uint32_t max_pll_ref_divider;
--
--	uint32_t max_vco_khz;
--	uint32_t min_vco_khz;
--	uint32_t min_pll_input_freq_khz;
--	uint32_t max_pll_input_freq_khz;
--
--	uint32_t fract_fb_divider_decimal_points_num;
--	uint32_t fract_fb_divider_factor;
--	uint32_t fract_fb_divider_precision;
--	uint32_t fract_fb_divider_precision_factor;
--	struct dc_context *ctx;
--};
--
--
--bool dal_calc_pll_clock_source_max_vco_init(
--		struct calc_pll_clock_source *calc_pll_cs,
--		struct calc_pll_clock_source_init_data *init_data);
--
--uint32_t dal_clock_source_calculate_pixel_clock_pll_dividers(
--		struct calc_pll_clock_source *calc_pll_cs,
--		struct pll_settings *pll_settings);
--
--
--#endif /*__DAL_CALC_PLL_CLOCK_SOURCE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-deleted file mode 100644
-index a7863cd..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.h
-+++ /dev/null
-@@ -1,141 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_CLOCK_SOURCE_H__
--#define __DAL_CLOCK_SOURCE_H__
--
--#include "include/adapter_service_types.h"
--#include "include/bios_parser_types.h"
--#include "include/clock_source_interface.h"
--#include "include/clock_source_types.h"
--
--struct spread_spectrum_data {
--	uint32_t percentage;		/*> In unit of 0.01% or 0.001%*/
--	uint32_t percentage_divider;	/*> 100 or 1000	*/
--	uint32_t freq_range_khz;
--	uint32_t modulation_freq_hz;
--
--	struct spread_spectrum_flags flags;
--};
--
--struct clock_source_impl {
--	bool (*switch_dp_clock_source)(
--			struct clock_source *clk_src,
--			enum controller_id,
--			enum clock_source_id);
--	bool (*adjust_pll_pixel_rate)(
--			struct clock_source *clk_src,
--			struct pixel_clk_params *pix_clk_params,
--			uint32_t requested_pix_clk_hz);
--	bool (*adjust_dto_pixel_rate)(
--			struct clock_source *clk_src,
--			struct pixel_clk_params *pix_clk_params,
--			uint32_t requested_clk_freq_hz);
--	uint32_t (*retrieve_dto_pix_rate_hz)(
--			struct clock_source *clk_src,
--			struct pixel_clk_params *pix_clk_params);
--	uint32_t (*retrieve_pll_pix_rate_hz)(
--			struct clock_source *clk_src,
--			struct pixel_clk_params *pix_clk_params);
--
--	uint32_t (*get_pix_clk_dividers)(struct clock_source *clk_src,
--			struct pixel_clk_params *pix_clk_params,
--			struct pll_settings *pll_settings);
--	bool (*program_pix_clk)(struct clock_source *clk_src,
--			struct pixel_clk_params *pix_clk_params,
--			struct pll_settings *pll_settings);
--	bool (*power_down_pll)(struct clock_source *clk_src,
--			enum controller_id);
--	void (*destroy)(struct clock_source **clk_src);
--};
--
--void dal_clock_source_get_ss_info_from_atombios(
--		struct clock_source *clk_src,
--		enum as_signal_type as_signal,
--		struct spread_spectrum_data *ss_data[],
--		uint32_t *ss_entries_num);
--uint32_t dal_clock_source_base_retrieve_dto_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params);
--const struct spread_spectrum_data *dal_clock_source_get_ss_data_entry(
--		struct clock_source *clk_src,
--		enum signal_type signal,
--		uint32_t pix_clk_khz);
--/* for PLL and EXT clock sources */
--struct registers {
--	uint32_t dp_dtox_phase;
--	uint32_t dp_dtox_modulo;
--	uint32_t crtcx_pixel_rate_cntl;
--	uint32_t crtcx_phypll_pixel_rate_cntl;
--	uint32_t combophyx_pll_wrap_cntl;
--	uint32_t combophyx_freq_cntl0;
--	uint32_t combophyx_freq_cntl2;
--	uint32_t combophyx_freq_cntl3;
--};
--
--struct clock_source {
--	const struct clock_source_impl *funcs;
--	struct graphics_object_id id;
--	enum clock_source_id clk_src_id;
--	struct adapter_service *adapter_service;
--	struct dc_bios *bios_parser;
--
--	struct spread_spectrum_data *ep_ss_params;
--	uint32_t ep_ss_params_cnt;
--	struct spread_spectrum_data *dp_ss_params;
--	uint32_t dp_ss_params_cnt;
--
--	struct spread_spectrum_data *hdmi_ss_params;
--	uint32_t hdmi_ss_params_cnt;
--
--	struct spread_spectrum_data *dvi_ss_params;
--	uint32_t dvi_ss_params_cnt;
--
--	uint32_t output_signals;
--	uint32_t input_signals;
--
--	bool turn_off_ds;
--	bool is_gen_lock_capable; /*replacement for virtual method*/
--	bool is_clock_source_with_fixed_freq; /*replacement for virtual method*/
--	enum clock_sharing_level clk_sharing_lvl;
--	struct dc_context *ctx;
--};
--
--bool dal_clock_source_construct(
--			struct clock_source *clk_src,
--			struct clock_source_init_data *clk_src_init_data);
--bool dal_clock_source_base_adjust_pll_pixel_rate(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		uint32_t requested_pix_clk_hz);
--bool dal_clock_source_base_adjust_dto_pix_rate(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		uint32_t requested_pix_clk_hz);
--uint32_t dal_clock_source_base_retrieve_pll_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params);
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-deleted file mode 100644
-index fa3201b..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.c
-+++ /dev/null
-@@ -1,383 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--
--#include "dce/dce_11_0_d.h"
--#include "dce/dce_11_0_sh_mask.h"
--
--#include "include/logger_interface.h"
--#include "include/adapter_service_interface.h"
--#include "include/fixed32_32.h"
--
--#include "ext_clock_source_dce110.h"
--
--/**
-- * In this file ECS stands for External Clock Source.
-- */
--
--#define ECS110_FROM_BASE(clk_src_ptr)\
--	container_of(\
--		container_of((clk_src_ptr), struct ext_clock_source, base), \
--			struct ext_clock_source_dce110, base)
--
--#define ECS_WARNING(...) \
--	dal_logger_write(ctx->logger, LOG_MAJOR_WARNING, \
--			LOG_MINOR_COMPONENT_GPU, __VA_ARGS__)
--
--#define ECS_ERROR(...) \
--	dal_logger_write(ctx->logger, LOG_MAJOR_ERROR, \
--			LOG_MINOR_COMPONENT_GPU, __VA_ARGS__)
--
--/******************************************************************************
-- * implementation functions
-- *****************************************************************************/
--
--static uint32_t controller_id_to_index(
--		struct clock_source *clk_src,
--		enum controller_id controller_id)
--{
--	struct dc_context *ctx = clk_src->ctx;
--	uint32_t index = 0;
--
--	switch (controller_id) {
--	case CONTROLLER_ID_D0:
--		index = 0;
--		break;
--	case CONTROLLER_ID_D1:
--		index = 1;
--		break;
--	case CONTROLLER_ID_D2:
--		index = 2;
--		break;
--	default:
--		ECS_ERROR("%s: invalid input controller_id = %d!\n",
--				__func__, controller_id);
--		break;
--	}
--
--	return index;
--}
--
--/* Adjust pixel rate by DTO programming (used for DisplayPort) */
--static bool adjust_dto_pixel_rate(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		uint32_t requested_pix_clk_hz)
--{
--	struct ext_clock_source_dce110 *ecs110 =
--			ECS110_FROM_BASE(clk_src);
--	struct dc_context *ctx = clk_src->ctx;
--	uint32_t index;
--	uint32_t dto_phase_reg;
--	uint32_t dto_modulo_reg;
--	uint32_t dto_phase_rnd;
--	uint32_t addr;
--	uint32_t value;
--	struct fixed32_32 dto_phase;
--
--	if (NULL == pix_clk_params) {
--		ECS_WARNING("%s: invalid input!\n", __func__);
--		return false;
--	}
--
--	index = controller_id_to_index(clk_src, pix_clk_params->controller_id);
--
--	addr = ecs110->registers[index].dp_dtox_phase;
--	dto_phase_reg = dal_read_reg(ctx, addr);
--
--	addr = ecs110->registers[index].dp_dtox_modulo;
--	dto_modulo_reg = dal_read_reg(ctx, addr);
--
--	if (!dto_modulo_reg) {
--		ECS_WARNING("%s: current modulo is zero!\n", __func__);
--		return false;
--	}
--
--	dto_phase = dal_fixed32_32_from_int(requested_pix_clk_hz);
--
--	dto_phase = dal_fixed32_32_mul_int(dto_phase, dto_modulo_reg);
--
--	dto_phase = dal_fixed32_32_div_int(dto_phase,
--			pix_clk_params->dp_ref_clk * 1000);
--
--	dto_phase_rnd = dal_fixed32_32_round(dto_phase);
--
--	/* Program DTO Phase */
--	if (dto_phase_reg != dto_phase_rnd) {
--		/* If HW De-Spreading enabled on DP REF clock and if there will
--		 * be case when Pixel rate > average DP Ref Clock, then need to
--		 * disable de-spread for DP DTO (ATOMBIOS will program MODULO
--		 * for average DP REF clock so no further SW adjustment
--		 * needed) */
--		if (pix_clk_params->de_spread_params.hw_dso_n_dp_ref_clk) {
--
--			addr = ecs110->registers[index].crtcx_pixel_rate_cntl;
--			value = dal_read_reg(ctx, addr);
--
--			if (requested_pix_clk_hz / 1000 >
--				pix_clk_params->
--					de_spread_params.avg_dp_ref_clk_khz) {
--
--				set_reg_field_value(value, 1,
--						CRTC0_PIXEL_RATE_CNTL,
--						DP_DTO0_DS_DISABLE);
--			} else {
--				set_reg_field_value(value, 0,
--						CRTC0_PIXEL_RATE_CNTL,
--						DP_DTO0_DS_DISABLE);
--			}
--
--			dal_write_reg(ctx, addr, value);
--		}
--
--		value = 0;
--		addr = ecs110->registers[index].dp_dtox_phase;
--
--		set_reg_field_value(value, dto_phase_rnd,
--				DP_DTO0_PHASE,
--				DP_DTO0_PHASE);
--
--		dal_write_reg(ctx, addr, value);
--	}
--
--	return true;
--}
--
--/**
-- * Retrieve Pixel Rate (in Hz) from HW registers already programmed.
-- */
--static uint32_t retrieve_dp_pixel_rate_from_display_pll(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *params)
--{
--	struct dc_context *ctx = clk_src->ctx;
--
--	/* TODO: update when DAL2 implements  this function. */
--	DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_GPU, "%s\n", __func__);
--	return 0;
--}
--
--static uint32_t retrieve_dto_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *params)
--{
--	struct ext_clock_source_dce110 *ecs110 =
--			ECS110_FROM_BASE(clk_src);
--	struct dc_context *ctx = clk_src->ctx;
--	uint32_t index;
--	uint32_t dto_phase_reg;
--	uint32_t dto_modulo_reg;
--	uint32_t addr;
--	uint32_t value;
--	uint32_t pix_rate_hz;
--	struct fixed32_32 p_clk;
--
--	if (params == NULL)
--		return 0;
--
--	if (NULL == params) {
--		ECS_WARNING("%s: invalid input!\n", __func__);
--		return false;
--	}
--
--	index = controller_id_to_index(clk_src, params->controller_id);
--
--	addr = ecs110->registers[index].crtcx_pixel_rate_cntl;
--	value = dal_read_reg(ctx, addr);
--
--	if (get_reg_field_value(value, CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE)
--			== 1) {
--
--		addr = ecs110->registers[index].dp_dtox_phase;
--		dto_phase_reg = dal_read_reg(ctx, addr);
--
--		addr = ecs110->registers[index].dp_dtox_modulo;
--		dto_modulo_reg = dal_read_reg(ctx, addr);
--
--		if (!dto_modulo_reg) {
--			ECS_WARNING("%s: current modulo is zero!\n", __func__);
--			return 0;
--		}
--
--		/* Calculate pixel clock from DTO Phase & Modulo*/
--		p_clk = dal_fixed32_32_from_int(params->dp_ref_clk * 1000);
--
--		p_clk = dal_fixed32_32_mul_int(p_clk, dto_phase_reg);
--
--		p_clk = dal_fixed32_32_div_int(p_clk, dto_modulo_reg);
--
--		pix_rate_hz = dal_fixed32_32_round(p_clk);
--	} else {
--		pix_rate_hz = retrieve_dp_pixel_rate_from_display_pll(clk_src,
--				params);
--	}
--
--	return pix_rate_hz;
--}
--
--/******************************************************************************
-- * create/destroy functions
-- *****************************************************************************/
--
--static void destruct(struct ext_clock_source_dce110 *ecs110)
--{
--	struct ext_clock_source *ext_cs = &ecs110->base;
--	struct clock_source *base = &ext_cs->base;
--
--	if (NULL != base->dp_ss_params) {
--		dc_service_free(base->ctx, base->dp_ss_params);
--		base->dp_ss_params = NULL;
--	}
--
--	dc_service_free(base->ctx, ecs110->registers);
--	ecs110->registers = NULL;
--}
--
--
--static void destroy(struct clock_source **clk_src)
--{
--	struct ext_clock_source_dce110 *ecs110;
--
--	ecs110 = ECS110_FROM_BASE(*clk_src);
--
--	destruct(ecs110);
--
--	dc_service_free((*clk_src)->ctx, ecs110);
--
--	*clk_src = NULL;
--}
--
--static const struct clock_source_impl funcs = {
--	.program_pix_clk = dal_ext_clock_source_program_pix_clk,
--	.adjust_pll_pixel_rate = dal_clock_source_base_adjust_pll_pixel_rate,
--	.adjust_dto_pixel_rate = adjust_dto_pixel_rate,
--	.retrieve_pll_pix_rate_hz =
--			dal_clock_source_base_retrieve_pll_pix_rate_hz,
--	.get_pix_clk_dividers = dal_ext_clock_source_get_pix_clk_dividers,
--	.destroy = destroy,
--	.retrieve_dto_pix_rate_hz = retrieve_dto_pix_rate_hz,
--	.power_down_pll = dal_ext_clock_source_power_down_pll
--};
--
--static bool construct(
--		struct ext_clock_source_dce110 *ecs110,
--		struct clock_source_init_data *clk_src_init_data)
--{
--	struct dc_context *ctx = clk_src_init_data->ctx;
--	struct ext_clock_source *ext_cs = &ecs110->base;
--	struct clock_source *base = &ext_cs->base;
--	uint32_t controllers_num;
--	struct registers *registers;
--
--	/* None of the base construct() functions allocates memory.
--	 * That means, in case of error, we don't have to free memory
--	 * allocated by base. */
--	if (!dal_ext_clock_source_construct(ext_cs, clk_src_init_data))
--		return false;
--
--	base->funcs = &funcs;
--
--	base->is_gen_lock_capable = false;
--	base->dp_ss_params = NULL;
--	base->dp_ss_params_cnt = 0;
--
--	ecs110->registers = NULL;
--
--	if (base->clk_src_id != CLOCK_SOURCE_ID_EXTERNAL) {
--		ECS_ERROR("ECS110:Invalid ClockSourceId = %d!\n",
--				base->clk_src_id);
--		return false;
--	}
--
--	controllers_num = dal_adapter_service_get_controllers_num(
--			base->adapter_service);
--
--	if (controllers_num <= 0 || controllers_num > 6) {
--		ECS_ERROR("ECS110:Invalid number of controllers = %d!\n",
--				controllers_num);
--		return false;
--	}
--
--	ecs110->registers = (struct registers *)
--		(dc_service_alloc(clk_src_init_data->ctx, sizeof(struct registers) * controllers_num));
--
--	if (ecs110->registers == NULL) {
--		ECS_ERROR("ECS110:Failed to allocate 'registers'!\n");
--		return false;
--	}
--
--	registers = ecs110->registers;
--
--	/* Assign register address. No break between cases */
--	switch (controllers_num) {
--	case 3:
--		registers[2].dp_dtox_phase = mmDP_DTO2_PHASE;
--		registers[2].dp_dtox_modulo = mmDP_DTO2_MODULO;
--		registers[2].crtcx_pixel_rate_cntl = mmCRTC2_PIXEL_RATE_CNTL;
--		/* fallthrough */
--	case 2:
--		registers[1].dp_dtox_phase = mmDP_DTO1_PHASE;
--		registers[1].dp_dtox_modulo = mmDP_DTO1_MODULO;
--		registers[1].crtcx_pixel_rate_cntl = mmCRTC1_PIXEL_RATE_CNTL;
--		/* fallthrough */
--	case 1:
--		registers[0].dp_dtox_phase = mmDP_DTO0_PHASE;
--		registers[0].dp_dtox_modulo = mmDP_DTO0_MODULO;
--		registers[0].crtcx_pixel_rate_cntl = mmCRTC0_PIXEL_RATE_CNTL;
--		break;
--
--	default:
--		/* We can not get here because we checked number of
--		 * controllers already. */
--		break;
--	}
--
--	dal_clock_source_get_ss_info_from_atombios(
--			base,
--			AS_SIGNAL_TYPE_DISPLAY_PORT,
--			&base->dp_ss_params,
--			&base->dp_ss_params_cnt);
--
--	return true;
--}
--
--
--struct clock_source *dal_ext_clock_source_dce110_create(
--		struct clock_source_init_data *clk_src_init_data)
--{
--	struct ext_clock_source_dce110 *ecs110;
--
--	ecs110 = dc_service_alloc(clk_src_init_data->ctx, sizeof(struct ext_clock_source_dce110));
--
--	if (ecs110 == NULL)
--		return NULL;
--
--	if (!construct(ecs110, clk_src_init_data)) {
--		dc_service_free(clk_src_init_data->ctx, ecs110);
--		return NULL;
--	}
--
--	return &ecs110->base.base;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
-deleted file mode 100644
-index 4ea2ae2..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/ext_clock_source_dce110.h
-+++ /dev/null
-@@ -1,38 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_EXT_CLOCK_SOURCE_DCE110__
--#define __DAL_EXT_CLOCK_SOURCE_DCE110__
--
--#include "../ext_clock_source.h"
--
--struct ext_clock_source_dce110 {
--	struct ext_clock_source base;
--	struct registers *registers;
--};
--
--struct clock_source *dal_ext_clock_source_dce110_create(
--		struct clock_source_init_data *clk_src_init_data);
--
--#endif /*__DAL_EXT_CLOCK_SOURCE_DCE110__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-deleted file mode 100644
-index ba05597..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.c
-+++ /dev/null
-@@ -1,718 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--
--#include "dce/dce_11_0_d.h"
--#include "dce/dce_11_0_sh_mask.h"
--
--#include "include/logger_interface.h"
--#include "include/bios_parser_interface.h"
--#include "include/adapter_service_interface.h"
--#include "include/fixed32_32.h"
--#include "gpu/calc_pll_clock_source.h"
--#include "gpu/clock_source.h"
--#include "gpu/pll_clock_source.h"
--
--#include "gpu/dce110/pll_clock_source_dce110.h"
--
--enum fract_fb_divider_dec_points {
--	FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM = 6,
--	FRACT_FB_DIVIDER_DEC_POINTS_NO_DS_NUM = 1,
--};
--
--#define FROM_CLK_SRC(clk_src_ptr)\
--	container_of(\
--		container_of((clk_src_ptr), struct pll_clock_source, base), \
--			struct pll_clock_source_dce110, base)
--
--static bool calculate_ss(
--		struct pll_clock_source_dce110 *clk_src,
--		struct pll_settings *pll_settings,
--		const struct spread_spectrum_data *ss_data,
--		struct delta_sigma_data *ds_data)
--{
--	struct fixed32_32 fb_div;
--	struct fixed32_32 ss_amount;
--	struct fixed32_32 ss_nslip_amount;
--	struct fixed32_32 ss_ds_frac_amount;
--	struct fixed32_32 ss_step_size;
--	struct fixed32_32 modulation_time;
--
--	if (ds_data == NULL)
--		return false;
--	if (ss_data == NULL)
--		return false;
--	if (ss_data->percentage == 0)
--		return false;
--	if (pll_settings == NULL)
--		return false;
--
--
--	dc_service_memset(ds_data, 0, sizeof(struct delta_sigma_data));
--
--
--
--	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
--	/* 6 decimal point support in fractional feedback divider */
--	fb_div  = dal_fixed32_32_from_fraction(
--		pll_settings->fract_feedback_divider, 1000000);
--	fb_div = dal_fixed32_32_add_int(fb_div, pll_settings->feedback_divider);
--
--	ds_data->ds_frac_amount = 0;
--	/*spreadSpectrumPercentage is in the unit of .01%,
--	 * so have to divided by 100 * 100*/
--	ss_amount = dal_fixed32_32_mul(
--		fb_div, dal_fixed32_32_from_fraction(ss_data->percentage,
--					100 * ss_data->percentage_divider));
--	ds_data->feedback_amount = dal_fixed32_32_floor(ss_amount);
--
--	ss_nslip_amount = dal_fixed32_32_sub(ss_amount,
--		dal_fixed32_32_from_int(ds_data->feedback_amount));
--	ss_nslip_amount = dal_fixed32_32_mul_int(ss_nslip_amount, 10);
--	ds_data->nfrac_amount = dal_fixed32_32_floor(ss_nslip_amount);
--
--	ss_ds_frac_amount = dal_fixed32_32_sub(ss_nslip_amount,
--		dal_fixed32_32_from_int(ds_data->nfrac_amount));
--	ss_ds_frac_amount = dal_fixed32_32_mul_int(ss_ds_frac_amount, 65536);
--	ds_data->ds_frac_amount = dal_fixed32_32_floor(ss_ds_frac_amount);
--
--	/* compute SS_STEP_SIZE_DSFRAC */
--	modulation_time = dal_fixed32_32_from_fraction(
--		pll_settings->reference_freq * 1000,
--		pll_settings->reference_divider * ss_data->modulation_freq_hz);
--
--
--	if (ss_data->flags.CENTER_SPREAD)
--		modulation_time = dal_fixed32_32_div_int(modulation_time, 4);
--	else
--		modulation_time = dal_fixed32_32_div_int(modulation_time, 2);
--
--	ss_step_size = dal_fixed32_32_div(ss_amount, modulation_time);
--	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
--	ss_step_size = dal_fixed32_32_mul_int(ss_step_size, 65536 * 10);
--	ds_data->ds_frac_size =  dal_fixed32_32_floor(ss_step_size);
--
--	return true;
--}
--
--static bool disable_spread_spectrum(struct pll_clock_source_dce110 *clk_src)
--{
--	enum bp_result result;
--	struct bp_spread_spectrum_parameters bp_ss_params = {0};
--	struct clock_source *clock_source = NULL;
--
--	clock_source = &clk_src->base.base;
--	bp_ss_params.pll_id = clock_source->clk_src_id;
--
--	/*Call ASICControl to process ATOMBIOS Exec table*/
--	result = clock_source->bios_parser->funcs->enable_spread_spectrum_on_ppll(
--			clock_source->bios_parser,
--			&bp_ss_params,
--			false);
--
--	return result == BP_RESULT_OK;
--}
--
--static bool enable_spread_spectrum(
--		struct pll_clock_source_dce110 *clk_src,
--		enum signal_type signal, struct pll_settings *pll_settings)
--{
--	struct bp_spread_spectrum_parameters bp_params = {0};
--	struct delta_sigma_data d_s_data;
--	struct clock_source *clock_source = NULL;
--	const struct spread_spectrum_data *ss_data = NULL;
--
--	clock_source = &clk_src->base.base;
--	ss_data = dal_clock_source_get_ss_data_entry(
--			clock_source,
--			signal,
--			pll_settings->calculated_pix_clk);
--
--/* Pixel clock PLL has been programmed to generate desired pixel clock,
-- * now enable SS on pixel clock */
--/* TODO is it OK to return true not doing anything ??*/
--	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
--		if (calculate_ss(clk_src, pll_settings, ss_data, &d_s_data)) {
--			bp_params.ds.feedback_amount =
--					d_s_data.feedback_amount;
--			bp_params.ds.nfrac_amount =
--					d_s_data.nfrac_amount;
--			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
--			bp_params.ds_frac_amount =
--					d_s_data.ds_frac_amount;
--			bp_params.flags.DS_TYPE = 1;
--			bp_params.pll_id = clock_source->clk_src_id;
--			bp_params.percentage = ss_data->percentage;
--			if (ss_data->flags.CENTER_SPREAD)
--				bp_params.flags.CENTER_SPREAD = 1;
--			if (ss_data->flags.EXTERNAL_SS)
--				bp_params.flags.EXTERNAL_SS = 1;
--
--			if (BP_RESULT_OK !=
--				clock_source->bios_parser->funcs->enable_spread_spectrum_on_ppll(
--						clock_source->bios_parser,
--						&bp_params,
--						true))
--				return false;
--		} else
--			return false;
--	}
--	return true;
--}
--
--static void program_pixel_clk_resync(
--		struct pll_clock_source_dce110 *clk_src,
--		enum signal_type signal_type,
--		enum dc_color_depth colordepth)
--{
--	struct clock_source *clock_source = NULL;
--	uint32_t value = 0;
--
--	clock_source = &clk_src->base.base;
--
--	value = dal_read_reg(
--		clock_source->ctx,
--		clk_src->pixclkx_resync_cntl);
--
--	set_reg_field_value(
--		value,
--		0,
--		PIXCLK1_RESYNC_CNTL,
--		DCCG_DEEP_COLOR_CNTL1);
--
--	/*
--	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
--	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
--	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
--	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
--	 */
--	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
--		return;
--
--	switch (colordepth) {
--	case COLOR_DEPTH_888:
--		set_reg_field_value(
--			value,
--			0,
--			PIXCLK1_RESYNC_CNTL,
--			DCCG_DEEP_COLOR_CNTL1);
--		break;
--	case COLOR_DEPTH_101010:
--		set_reg_field_value(
--			value,
--			1,
--			PIXCLK1_RESYNC_CNTL,
--			DCCG_DEEP_COLOR_CNTL1);
--		break;
--	case COLOR_DEPTH_121212:
--		set_reg_field_value(
--			value,
--			2,
--			PIXCLK1_RESYNC_CNTL,
--			DCCG_DEEP_COLOR_CNTL1);
--		break;
--	case COLOR_DEPTH_161616:
--		set_reg_field_value(
--			value,
--			3,
--			PIXCLK1_RESYNC_CNTL,
--			DCCG_DEEP_COLOR_CNTL1);
--		break;
--	default:
--		break;
--	}
--
--	dal_write_reg(
--		clock_source->ctx,
--		clk_src->pixclkx_resync_cntl,
--		value);
--}
--
--static bool program_pix_clk(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	struct pll_clock_source_dce110 *pll_clk_src_dce110 =
--						FROM_CLK_SRC(clk_src);
--	struct bp_pixel_clock_parameters bp_pc_params = {0};
--
--	/* First disable SS
--	 * ATOMBIOS will enable by default SS on PLL for DP,
--	 * do not disable it here
--	 */
--	if (!dc_is_dp_signal(pix_clk_params->signal_type))
--		disable_spread_spectrum(pll_clk_src_dce110);
--
--	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
--	bp_pc_params.controller_id = pix_clk_params->controller_id;
--	bp_pc_params.pll_id = clk_src->clk_src_id;
--	bp_pc_params.target_pixel_clock =
--			pll_settings->actual_pix_clk;
--	bp_pc_params.reference_divider = pll_settings->reference_divider;
--	bp_pc_params.feedback_divider = pll_settings->feedback_divider;
--	bp_pc_params.fractional_feedback_divider =
--			pll_settings->fract_feedback_divider;
--	bp_pc_params.pixel_clock_post_divider =
--			pll_settings->pix_clk_post_divider;
--	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
--	bp_pc_params.signal_type = pix_clk_params->signal_type;
--	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
--					pll_settings->use_external_clk;
--
--	if (clk_src->bios_parser->funcs->set_pixel_clock(clk_src->bios_parser,
--						&bp_pc_params) != BP_RESULT_OK)
--		return false;
--
--/* Enable SS
-- * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
-- * based on HW display PLL team, SS control settings should be programmed
-- * during PLL Reset, but they do not have effect
-- * until SS_EN is asserted.*/
--	if (pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal(
--					pix_clk_params->signal_type))
--		if (!enable_spread_spectrum(pll_clk_src_dce110,
--						pix_clk_params->signal_type,
--						pll_settings))
--			return false;
--
--/* Resync deep color DTO */
--	program_pixel_clk_resync(pll_clk_src_dce110,
--				pix_clk_params->signal_type,
--				pix_clk_params->color_depth);
--
--	return true;
--}
--
--static void ss_info_from_atombios_destroy(
--	struct pll_clock_source_dce110 *clk_src)
--{
--	struct clock_source *cs = &clk_src->base.base;
--
--	if (NULL != cs->ep_ss_params) {
--		dc_service_free(cs->ctx, cs->ep_ss_params);
--		cs->ep_ss_params = NULL;
--	}
--
--	if (NULL != cs->dp_ss_params) {
--		dc_service_free(cs->ctx, cs->dp_ss_params);
--		cs->dp_ss_params = NULL;
--	}
--
--	if (NULL != cs->hdmi_ss_params) {
--		dc_service_free(cs->ctx, cs->hdmi_ss_params);
--		cs->hdmi_ss_params = NULL;
--	}
--
--	if (NULL != cs->dvi_ss_params) {
--		dc_service_free(cs->ctx, cs->dvi_ss_params);
--		cs->dvi_ss_params = NULL;
--	}
--}
--
--static void destruct(
--	struct pll_clock_source_dce110 *pll_cs)
--{
--	ss_info_from_atombios_destroy(pll_cs);
--
--	if (NULL != pll_cs->registers) {
--		dc_service_free(pll_cs->base.base.ctx, pll_cs->registers);
--		pll_cs->registers = NULL;
--	}
--}
--
--static void destroy(struct clock_source **clk_src)
--{
--	struct pll_clock_source_dce110 *pll_clk_src;
--
--	pll_clk_src = FROM_CLK_SRC(*clk_src);
--
--	destruct(pll_clk_src);
--	dc_service_free((*clk_src)->ctx, pll_clk_src);
--
--	*clk_src = NULL;
--}
--
--/**
-- * Calculate PLL Dividers for given Clock Value.
-- * First will call VBIOS Adjust Exec table to check if requested Pixel clock
-- * will be Adjusted based on usage.
-- * Then it will calculate PLL Dividers for this Adjusted clock using preferred
-- * method (Maximum VCO frequency).
-- *
-- * \return
-- *     Calculation error in units of 0.01%
-- */
--static uint32_t get_pix_clk_dividers(
--		struct clock_source *cs,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	struct pll_clock_source_dce110 *pll_cs_110 = FROM_CLK_SRC(cs);
--	struct pll_clock_source *pll_base = &pll_cs_110->base;
--	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
--	uint32_t addr = 0;
--	uint32_t value = 0;
--	uint32_t field = 0;
--
--	if (pix_clk_params == NULL || pll_settings == NULL
--			|| pix_clk_params->requested_pix_clk == 0) {
--		dal_logger_write(cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s: Invalid parameters!!\n", __func__);
--		return pll_calc_error;
--	}
--
--	dc_service_memset(pll_settings, 0, sizeof(*pll_settings));
--
--	/* Check if reference clock is external (not pcie/xtalin)
--	* HW Dce80 spec:
--	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
--	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK
--	*/
--	addr = pll_cs_110->pxpll_cntl;
--	value = dal_read_reg(cs->ctx, addr);
--	field = get_reg_field_value(value, PLL_CNTL, PLL_REF_DIV_SRC);
--	pll_settings->use_external_clk = (field > 1);
--
--	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
--	 * (we do not care any more from SI for some older DP Sink which
--	 * does not report SS support, no known issues) */
--	if ((pix_clk_params->flags.ENABLE_SS) ||
--			(dc_is_dp_signal(pix_clk_params->signal_type))) {
--
--		const struct spread_spectrum_data *ss_data =
--				dal_clock_source_get_ss_data_entry(
--					cs,
--					pix_clk_params->signal_type,
--					pll_settings->adjusted_pix_clk);
--
--		if (NULL != ss_data)
--			pll_settings->ss_percentage = ss_data->percentage;
--	}
--
--	/* Check VBIOS AdjustPixelClock Exec table */
--	if (!dal_pll_clock_source_adjust_pix_clk(pll_base,
--			pix_clk_params, pll_settings)) {
--		/* Should never happen, ASSERT and fill up values to be able
--		 * to continue. */
--		dal_logger_write(cs->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s: Failed to adjust pixel clock!!", __func__);
--		pll_settings->actual_pix_clk =
--				pix_clk_params->requested_pix_clk;
--		pll_settings->adjusted_pix_clk =
--				pix_clk_params->requested_pix_clk;
--
--		if (dc_is_dp_signal(pix_clk_params->signal_type))
--			pll_settings->adjusted_pix_clk = 100000;
--	}
--
--	/* Calculate Dividers */
--	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
--		/*Calculate Dividers by HDMI object, no SS case or SS case */
--		pll_calc_error =
--			dal_clock_source_calculate_pixel_clock_pll_dividers(
--					&pll_cs_110->calc_pll_clock_source_hdmi,
--					pll_settings);
--	else
--		/*Calculate Dividers by default object, no SS case or SS case */
--		pll_calc_error =
--			dal_clock_source_calculate_pixel_clock_pll_dividers(
--					&pll_cs_110->calc_pll_clock_source,
--					pll_settings);
--
--	return pll_calc_error;
--}
--
--static const struct clock_source_impl funcs = {
--	.program_pix_clk = program_pix_clk,
--	.adjust_pll_pixel_rate = NULL,
--	.adjust_dto_pixel_rate = NULL,
--	.retrieve_pll_pix_rate_hz = NULL,
--	.get_pix_clk_dividers = get_pix_clk_dividers,
--	.destroy = destroy,
--	.retrieve_dto_pix_rate_hz = NULL,
--	.power_down_pll = dal_pll_clock_source_power_down_pll,
--};
--
--static void ss_info_from_atombios_create(
--	struct pll_clock_source_dce110 *clk_src)
--{
--	struct clock_source *base = &clk_src->base.base;
--
--	dal_clock_source_get_ss_info_from_atombios(
--		base,
--		AS_SIGNAL_TYPE_DISPLAY_PORT,
--		&base->dp_ss_params,
--		&base->dp_ss_params_cnt);
--	dal_clock_source_get_ss_info_from_atombios(
--		base,
--		AS_SIGNAL_TYPE_LVDS,
--		&base->ep_ss_params,
--		&base->ep_ss_params_cnt);
--	dal_clock_source_get_ss_info_from_atombios(
--		base,
--		AS_SIGNAL_TYPE_HDMI,
--		&base->hdmi_ss_params,
--		&base->hdmi_ss_params_cnt);
--	dal_clock_source_get_ss_info_from_atombios(
--		base,
--		AS_SIGNAL_TYPE_DVI,
--		&base->dvi_ss_params,
--		&base->dvi_ss_params_cnt);
--}
--
--
--static bool construct(
--		struct pll_clock_source_dce110 *pll_cs_dce110,
--		struct clock_source_init_data *clk_src_init_data)
--{
--	uint32_t controllers_num = 1;
--
--/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
--	struct calc_pll_clock_source_init_data calc_pll_cs_init_data = {
--		dal_adapter_service_get_bios_parser(clk_src_init_data->as),
--		1, /* minPixelClockPLLPostDivider */
--		PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK,
--		/* maxPixelClockPLLPostDivider*/
--		1,/* minPLLRefDivider*/
--		PLL_REF_DIV__PLL_REF_DIV_MASK,/* maxPLLRefDivider*/
--		0,
--/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
--		0,
--/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
--		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
--/*numberOfFractFBDividerDecimalPoints*/
--		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
--/*number of decimal point to round off for fractional feedback divider value*/
--		clk_src_init_data->ctx
--	};
--/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
--	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi = {
--		dal_adapter_service_get_bios_parser(clk_src_init_data->as),
--		1, /* minPixelClockPLLPostDivider */
--		PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK,
--		/* maxPixelClockPLLPostDivider*/
--		1,/* minPLLRefDivider*/
--		PLL_REF_DIV__PLL_REF_DIV_MASK,/* maxPLLRefDivider*/
--		13500,
--	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
--		27000,
--	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
--		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
--		/*numberOfFractFBDividerDecimalPoints*/
--		FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM,
--/*number of decimal point to round off for fractional feedback divider value*/
--		clk_src_init_data->ctx
--	};
--
--	struct pll_clock_source *base = &pll_cs_dce110->base;
--	struct clock_source *superbase = &base->base;
--
--	if (!dal_pll_clock_source_construct(base, clk_src_init_data)) {
--		ASSERT_CRITICAL(false);
--		return false;
--	}
--
--	superbase->funcs = &funcs;
--
--	superbase->is_clock_source_with_fixed_freq = false;
--	superbase->clk_sharing_lvl = CLOCK_SHARING_LEVEL_DISPLAY_PORT_SHAREABLE;
--
--	pll_cs_dce110->registers = NULL;
--
--/* PLL3 should not be used although it is available in online register spec */
--	if ((superbase->clk_src_id != CLOCK_SOURCE_ID_PLL1)
--		&& (superbase->clk_src_id != CLOCK_SOURCE_ID_PLL0)) {
--
--
--		ASSERT_CRITICAL(false);
--		goto failure;
--	}
--
--/* From Driver side PLL0 is now used for non DP timing also,
-- * so it supports all signals except Wireless.
-- * Wireless signal type does not require a PLL clock source,
-- * so we will not waste a clock on it.
--*/
--	superbase->output_signals &= ~SIGNAL_TYPE_WIRELESS;
--
--	if (!dal_calc_pll_clock_source_max_vco_init(
--		&pll_cs_dce110->calc_pll_clock_source,
--		&calc_pll_cs_init_data)) {
--		ASSERT_CRITICAL(false);
--		goto failure;
--	}
--
--	if (base->ref_freq_khz == 48000) {
--		calc_pll_cs_init_data_hdmi.
--			min_override_input_pxl_clk_pll_freq_khz = 24000;
--		calc_pll_cs_init_data_hdmi.
--			max_override_input_pxl_clk_pll_freq_khz = 48000;
--	} else if (base->ref_freq_khz == 100000) {
--		calc_pll_cs_init_data_hdmi.
--			min_override_input_pxl_clk_pll_freq_khz = 25000;
--		calc_pll_cs_init_data_hdmi.
--			max_override_input_pxl_clk_pll_freq_khz = 50000;
--	}
--
--	if (!dal_calc_pll_clock_source_max_vco_init(
--			&pll_cs_dce110->calc_pll_clock_source_hdmi,
--			&calc_pll_cs_init_data_hdmi)) {
--		ASSERT_CRITICAL(false);
--		goto failure;
--	}
--
--	switch (superbase->clk_src_id) {
--	case CLOCK_SOURCE_ID_PLL0:
--		pll_cs_dce110->pixclkx_resync_cntl = mmPIXCLK0_RESYNC_CNTL;
--		pll_cs_dce110->ppll_fb_div = mmBPHYC_PLL0_PLL_FB_DIV;
--		pll_cs_dce110->ppll_ref_div = mmBPHYC_PLL0_PLL_REF_DIV;
--		pll_cs_dce110->ppll_post_div = mmBPHYC_PLL0_PLL_POST_DIV;
--		pll_cs_dce110->pxpll_ds_cntl = mmBPHYC_PLL0_PLL_DS_CNTL;
--		pll_cs_dce110->pxpll_ss_cntl = mmBPHYC_PLL0_PLL_SS_CNTL;
--		pll_cs_dce110->pxpll_ss_dsfrac =
--				mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC;
--		pll_cs_dce110->pxpll_cntl = mmBPHYC_PLL0_PLL_CNTL;
--		break;
--	case CLOCK_SOURCE_ID_PLL1:
--		pll_cs_dce110->pixclkx_resync_cntl = mmPIXCLK1_RESYNC_CNTL;
--		pll_cs_dce110->ppll_fb_div = mmBPHYC_PLL1_PLL_FB_DIV;
--		pll_cs_dce110->ppll_ref_div = mmBPHYC_PLL1_PLL_REF_DIV;
--		pll_cs_dce110->ppll_post_div = mmBPHYC_PLL1_PLL_POST_DIV;
--		pll_cs_dce110->pxpll_ds_cntl = mmBPHYC_PLL1_PLL_DS_CNTL;
--		pll_cs_dce110->pxpll_ss_cntl = mmBPHYC_PLL1_PLL_SS_CNTL;
--		pll_cs_dce110->pxpll_ss_dsfrac =
--				mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC;
--		pll_cs_dce110->pxpll_cntl = mmBPHYC_PLL1_PLL_CNTL;
--		break;
--	case CLOCK_SOURCE_ID_PLL2:
--	/* PLL2 is not supported */
--	default:
--		break;
--	}
--
--	controllers_num = dal_adapter_service_get_controllers_num(
--		superbase->adapter_service);
--
--	pll_cs_dce110->registers = dc_service_alloc(
--		clk_src_init_data->ctx,
--		sizeof(struct registers) * controllers_num);
--
--	if (pll_cs_dce110->registers == NULL) {
--		ASSERT_CRITICAL(false);
--		goto failure;
--	}
--
--	/* Assign register address. No break between cases */
--	switch (controllers_num) {
--	case 6:
--		pll_cs_dce110->registers[5].dp_dtox_phase =
--				mmDP_DTO5_PHASE;
--		pll_cs_dce110->registers[5].dp_dtox_modulo =
--				mmDP_DTO5_MODULO;
--		pll_cs_dce110->registers[5].crtcx_pixel_rate_cntl =
--				mmCRTC5_PIXEL_RATE_CNTL;
--		/* fall through*/
--
--	case 5:
--		pll_cs_dce110->registers[4].dp_dtox_phase =
--				mmDP_DTO4_PHASE;
--		pll_cs_dce110->registers[4].dp_dtox_modulo =
--				mmDP_DTO4_MODULO;
--		pll_cs_dce110->registers[4].crtcx_pixel_rate_cntl =
--				mmCRTC4_PIXEL_RATE_CNTL;
--		/* fall through*/
--
--	case 4:
--		pll_cs_dce110->registers[3].dp_dtox_phase =
--				mmDP_DTO3_PHASE;
--		pll_cs_dce110->registers[3].dp_dtox_modulo =
--				mmDP_DTO3_MODULO;
--		pll_cs_dce110->registers[3].crtcx_pixel_rate_cntl =
--				mmCRTC3_PIXEL_RATE_CNTL;
--		/* fall through*/
--
--	case 3:
--		pll_cs_dce110->registers[2].dp_dtox_phase =
--				mmDP_DTO2_PHASE;
--		pll_cs_dce110->registers[2].dp_dtox_modulo =
--				mmDP_DTO2_MODULO;
--		pll_cs_dce110->registers[2].crtcx_pixel_rate_cntl =
--				mmCRTC2_PIXEL_RATE_CNTL;
--		/* fall through*/
--
--	case 2:
--		pll_cs_dce110->registers[1].dp_dtox_phase =
--				mmDP_DTO1_PHASE;
--		pll_cs_dce110->registers[1].dp_dtox_modulo =
--				mmDP_DTO1_MODULO;
--		pll_cs_dce110->registers[1].crtcx_pixel_rate_cntl =
--				mmCRTC1_PIXEL_RATE_CNTL;
--		/* fall through*/
--
--	case 1:
--		pll_cs_dce110->registers[0].dp_dtox_phase =
--				mmDP_DTO0_PHASE;
--		pll_cs_dce110->registers[0].dp_dtox_modulo =
--				mmDP_DTO0_MODULO;
--		pll_cs_dce110->registers[0].crtcx_pixel_rate_cntl =
--				mmCRTC0_PIXEL_RATE_CNTL;
--
--		break;
--
--	default:
--		ASSERT_CRITICAL(false);
--		goto failure;
--	}
--
--	ss_info_from_atombios_create(pll_cs_dce110);
--
--	return true;
--
--failure:
--	destruct(pll_cs_dce110);
--
--	return false;
--}
--
--struct clock_source *dal_pll_clock_source_dce110_create(
--		struct clock_source_init_data *clk_src_init_data)
--{
--	struct pll_clock_source_dce110 *clk_src =
--		dc_service_alloc(clk_src_init_data->ctx, sizeof(struct pll_clock_source_dce110));
--
--	if (clk_src == NULL)
--		return NULL;
--
--	if (!construct(clk_src, clk_src_init_data)) {
--		dc_service_free(clk_src_init_data->ctx, clk_src);
--		return NULL;
--	}
--	return &(clk_src->base.base);
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
-deleted file mode 100644
-index 166b29a..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/pll_clock_source_dce110.h
-+++ /dev/null
-@@ -1,55 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_PLL_CLOCK_SOURCE_DCE110_H__
--#define __DAL_PLL_CLOCK_SOURCE_DCE110_H__
--
--#include "../pll_clock_source.h"
--#include "../calc_pll_clock_source.h"
--
--struct pll_clock_source_dce110 {
--	struct pll_clock_source base;
--
--	struct calc_pll_clock_source calc_pll_clock_source;
--/* object for normal circumstances, SS = 0 or SS >= 0.2% (LVDS or DP)
-- * or even for SS =~0.02 (DVI) */
--
--	struct calc_pll_clock_source calc_pll_clock_source_hdmi;
--/* object for HDMI no SS or SS <= 0.06% */
--
--	struct registers *registers;
--
--	uint32_t pixclkx_resync_cntl;
--	uint32_t ppll_fb_div;
--	uint32_t ppll_ref_div;
--	uint32_t ppll_post_div;
--	uint32_t pxpll_ds_cntl;
--	uint32_t pxpll_ss_cntl;
--	uint32_t pxpll_ss_dsfrac;
--	uint32_t pxpll_cntl;
--};
--
--struct clock_source *dal_pll_clock_source_dce110_create(
--		struct clock_source_init_data *clk_src_init_data);
--
--#endif /*__DAL_PLL_CLOCK_SOURCE_DCE110__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-deleted file mode 100644
-index 249720f..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.c
-+++ /dev/null
-@@ -1,193 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#include "dc_services.h"
--#include "vce_clock_source_dce110.h"
--#include "include/clock_source_types.h"
--#include "include/bios_parser_interface.h"
--#include "include/logger_interface.h"
--
--struct vce_clock_source_dce110 {
--	struct clock_source base;
--	uint32_t ref_freq_khz;
--};
--
--static uint32_t get_pix_clk_dividers(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	struct vce_clock_source_dce110 *vce_clk_src_dce110 =
--			container_of(
--					clk_src,
--					struct vce_clock_source_dce110,
--					base);
--	if (pix_clk_params == NULL ||
--			pll_settings == NULL ||
--			pix_clk_params->requested_pix_clk == 0) {
--		dal_logger_write(clk_src->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s: Invalid parameters!!", __func__);
--		return MAX_PLL_CALC_ERROR;
--	}
--
--	dc_service_memset(pll_settings, 0, sizeof(struct pll_settings));
--	pll_settings->reference_freq = vce_clk_src_dce110->ref_freq_khz;
--	pll_settings->actual_pix_clk =
--			pix_clk_params->requested_pix_clk;
--	pll_settings->adjusted_pix_clk =
--			pix_clk_params->requested_pix_clk;
--	pll_settings->calculated_pix_clk =
--			pix_clk_params->requested_pix_clk;
--
--	return 0;
--}
--static bool program_pix_clk(struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	struct bp_pixel_clock_parameters bp_pix_clk_params = { 0 };
--
--	if (pll_settings->actual_pix_clk == 0)
--		return false;
--	/* this is SimNow for Nutmeg*/
--
--	bp_pix_clk_params.controller_id = pix_clk_params->controller_id;
--	bp_pix_clk_params.pll_id = clk_src->clk_src_id;
--	bp_pix_clk_params.target_pixel_clock = pll_settings->actual_pix_clk;
--	bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
--	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
--
--	if (clk_src->bios_parser->funcs->set_pixel_clock(clk_src->bios_parser,
--			&bp_pix_clk_params) == BP_RESULT_OK)
--		return true;
--
--	return false;
--}
--
--static bool power_down_pll(struct clock_source *clk_src,
--		enum controller_id controller_id)
--{
--	return true;
--}
--
--static void destruct(
--	struct vce_clock_source_dce110 *vce_clk_src)
--{
--
--}
--
--static void destroy(
--	struct clock_source **clk_src)
--{
--	struct vce_clock_source_dce110 *vce_clk_src;
--
--	vce_clk_src =
--		container_of(*clk_src, struct vce_clock_source_dce110, base);
--
--	destruct(vce_clk_src);
--	dc_service_free((*clk_src)->ctx, vce_clk_src);
--
--	*clk_src = NULL;
--}
--
--static const struct clock_source_impl funcs = {
--	.program_pix_clk = program_pix_clk,
--	.adjust_pll_pixel_rate = dal_clock_source_base_adjust_pll_pixel_rate,
--	.adjust_dto_pixel_rate = dal_clock_source_base_adjust_dto_pix_rate,
--	.retrieve_pll_pix_rate_hz =
--		dal_clock_source_base_retrieve_pll_pix_rate_hz,
--	.get_pix_clk_dividers = get_pix_clk_dividers,
--	.destroy = destroy,
--	.retrieve_dto_pix_rate_hz =
--		dal_clock_source_base_retrieve_dto_pix_rate_hz,
--	.power_down_pll = power_down_pll,
--};
--
--static bool construct(
--			struct vce_clock_source_dce110 *vce_clk_src,
--			struct clock_source_init_data *clk_src_init_data)
--{
--	struct firmware_info fw_info = { { 0 } };
--
--	if (!dal_clock_source_construct(
--		&vce_clk_src->base, clk_src_init_data)) {
--		ASSERT_CRITICAL(false);
--		return false;
--	}
--
--	if (vce_clk_src->base.clk_src_id != CLOCK_SOURCE_ID_VCE) {
--		dal_logger_write(clk_src_init_data->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"Invalid ClockSourceId = %d!\n",
--			vce_clk_src->base.clk_src_id);
--		ASSERT_CRITICAL(false);
--		dal_logger_write(clk_src_init_data->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"Failed to create DCE110VceClockSource.\n");
--		return false;
--	}
--
--	vce_clk_src->base.funcs = &funcs;
--	vce_clk_src->base.clk_sharing_lvl = CLOCK_SHARING_LEVEL_NOT_SHAREABLE;
--	vce_clk_src->base.is_clock_source_with_fixed_freq = false;
--
--
--	/*VCE clock source only supports SignalType_Wireless*/
--	vce_clk_src->base.output_signals |= SIGNAL_TYPE_WIRELESS;
--
--	/*Get Reference frequency, Input frequency range into PLL
--	 * and Output frequency range of the PLL
--	 * from ATOMBIOS Data table */
--	if (vce_clk_src->base.bios_parser->funcs->get_firmware_info(
--			vce_clk_src->base.bios_parser,
--			&fw_info) != BP_RESULT_OK)
--		return false;
--
--	vce_clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
--
--	return true;
--}
--
--
--struct clock_source *dal_vce_clock_source_dce110_create(
--		struct clock_source_init_data *clk_src_init_data)
--
--{
--	struct vce_clock_source_dce110 *clk_src;
--
--	clk_src = dc_service_alloc(clk_src_init_data->ctx, sizeof(struct vce_clock_source_dce110));
--
--	if (clk_src == NULL)
--		return NULL;
--
--	if (!construct(clk_src, clk_src_init_data)) {
--		dc_service_free(clk_src_init_data->ctx, clk_src);
--		return NULL;
--	}
--
--	return &clk_src->base;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
-deleted file mode 100644
-index 227b169..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/vce_clock_source_dce110.h
-+++ /dev/null
-@@ -1,32 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_VCE_CLOCK_SOURCE_DCE110__
--#define __DAL_VCE_CLOCK_SOURCE_DCE110__
--
--#include "../clock_source.h"
--
--struct clock_source *dal_vce_clock_source_dce110_create(
--		struct clock_source_init_data *clk_src_init_data);
--
--#endif /*__DAL_VCE_CLOCK_SOURCE_DCE110__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-deleted file mode 100644
-index ec5b17d..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.c
-+++ /dev/null
-@@ -1,121 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--
--#include "include/bios_parser_interface.h"
--#include "include/clock_source_types.h"
--#include "include/logger_interface.h"
--#include "ext_clock_source.h"
--
--uint32_t dal_ext_clock_source_get_pix_clk_dividers(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	struct ext_clock_source *ext_clk_src = container_of(
--			clk_src,
--			struct ext_clock_source,
--			base);
--
--	if (pix_clk_params == NULL ||
--			pll_settings == NULL ||
--			pix_clk_params->requested_pix_clk == 0) {
--		dal_logger_write(clk_src->ctx->logger,
--			LOG_MAJOR_WARNING,
--			LOG_MINOR_COMPONENT_GPU,
--			"%s: Invalid parameters!!", __func__);
--		return MAX_PLL_CALC_ERROR;
--	}
--
--	dc_service_memset(pll_settings, 0, sizeof(struct pll_settings));
--	pll_settings->adjusted_pix_clk = ext_clk_src->ext_clk_freq_khz;
--	pll_settings->calculated_pix_clk = ext_clk_src->ext_clk_freq_khz;
--	pll_settings->actual_pix_clk =
--			pix_clk_params->requested_pix_clk;
--	return 0;
--}
--
--bool dal_ext_clock_source_program_pix_clk(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	struct bp_pixel_clock_parameters bp_pix_clk_params = {0};
--
--	bp_pix_clk_params.controller_id = pix_clk_params->controller_id;
--	bp_pix_clk_params.pll_id = clk_src->clk_src_id;
--	bp_pix_clk_params.target_pixel_clock =
--			pix_clk_params->requested_pix_clk;
--	bp_pix_clk_params.encoder_object_id = pix_clk_params->encoder_object_id;
--	bp_pix_clk_params.signal_type = pix_clk_params->signal_type;
--
--	if (clk_src->bios_parser->funcs->set_pixel_clock(
--					clk_src->bios_parser,
--					&bp_pix_clk_params) == BP_RESULT_OK)
--		return true;
--
--	return false;
--
--}
--
--bool dal_ext_clock_source_power_down_pll(struct clock_source *clk_src,
--		enum controller_id controller_id)
--{
--	return true;
--}
--
--bool dal_ext_clock_source_construct(
--		struct ext_clock_source *ext_clk_src,
--		struct clock_source_init_data *clk_src_init_data)
--{
--	struct firmware_info fw_info = { { 0 } };
--
--	if (!dal_clock_source_construct(
--		&ext_clk_src->base, clk_src_init_data)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	ext_clk_src->base.clk_sharing_lvl =
--			CLOCK_SHARING_LEVEL_DISPLAY_PORT_SHAREABLE;
--	ext_clk_src->base.is_clock_source_with_fixed_freq = true;
--	/*  ExtClock has fixed frequency,
--	 * so it supports only DisplayPort signals.*/
--	ext_clk_src->base.output_signals =
--			SIGNAL_TYPE_DISPLAY_PORT |
--			SIGNAL_TYPE_DISPLAY_PORT_MST |
--			SIGNAL_TYPE_EDP;
--
--
--	/*Get External clock frequency from ATOMBIOS Data table */
--	if (ext_clk_src->base.bios_parser->funcs->get_firmware_info(
--			ext_clk_src->base.bios_parser,
--			&fw_info) != BP_RESULT_OK)
--		return false;
--
--	ext_clk_src->ext_clk_freq_khz = fw_info.
--			external_clock_source_frequency_for_dp;
--	return true;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
-deleted file mode 100644
-index bef1dc4..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/ext_clock_source.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_EXT_CLOCK_SOURCE_H__
--#define __DAL_EXT_CLOCK_SOURCE_H__
--
--#include "clock_source.h"
--
--struct ext_clock_source {
--	struct clock_source base;
--	uint32_t ext_clk_freq_khz;
--};
--
--bool dal_ext_clock_source_construct(
--		struct ext_clock_source *ext_cs,
--		struct clock_source_init_data *clk_src_init_data);
--bool dal_ext_clock_source_power_down_pll(struct clock_source *clk_src,
--		enum controller_id controller_id);
--uint32_t dal_ext_clock_source_get_pix_clk_dividers(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings);
--bool dal_ext_clock_source_program_pix_clk(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings);
--#endif /*__DAL_EXT_CLOCK_SOURCE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-deleted file mode 100644
-index d00bb61..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.c
-+++ /dev/null
-@@ -1,139 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--#include "include/bios_parser_interface.h"
--#include "pll_clock_source.h"
--
--bool dal_pll_clock_source_power_down_pll(
--		struct clock_source *clk_src,
--		enum controller_id controller_id)
--{
--
--	enum bp_result bp_result;
--	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
--
--	/* If Pixel Clock is 0 it means Power Down Pll*/
--	bp_pixel_clock_params.controller_id = controller_id;
--	bp_pixel_clock_params.pll_id = clk_src->clk_src_id;
--	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
--
--	/*Call ASICControl to process ATOMBIOS Exec table*/
--	bp_result = clk_src->bios_parser->funcs->set_pixel_clock(
--			clk_src->bios_parser,
--			&bp_pixel_clock_params);
--
--	return bp_result == BP_RESULT_OK;
--}
--
--bool dal_pll_clock_source_adjust_pix_clk(
--		struct pll_clock_source *pll_clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	uint32_t actual_pix_clk_khz = 0;
--	uint32_t requested_clk_khz = 0;
--	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
--							0 };
--	enum bp_result bp_result;
--
--	switch (pix_clk_params->signal_type) {
--	case SIGNAL_TYPE_HDMI_TYPE_A: {
--		requested_clk_khz = pix_clk_params->requested_pix_clk;
--
--		switch (pix_clk_params->color_depth) {
--		case COLOR_DEPTH_101010:
--			requested_clk_khz = (requested_clk_khz * 5) >> 2;
--			break; /* x1.25*/
--		case COLOR_DEPTH_121212:
--			requested_clk_khz = (requested_clk_khz * 6) >> 2;
--			break; /* x1.5*/
--		case COLOR_DEPTH_161616:
--			requested_clk_khz = requested_clk_khz * 2;
--			break; /* x2.0*/
--		default:
--			break;
--		}
--
--		actual_pix_clk_khz = requested_clk_khz;
--	}
--		break;
--
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		requested_clk_khz = pix_clk_params->requested_sym_clk;
--		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
--		break;
--
--	default:
--		requested_clk_khz = pix_clk_params->requested_pix_clk;
--		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
--		break;
--	}
--
--	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
--	bp_adjust_pixel_clock_params.
--		encoder_object_id = pix_clk_params->encoder_object_id;
--	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
--	bp_adjust_pixel_clock_params.
--		ss_enable = pix_clk_params->flags.ENABLE_SS;
--	bp_result = pll_clk_src->base.bios_parser->funcs->adjust_pixel_clock(
--			pll_clk_src->base.bios_parser,
--			&bp_adjust_pixel_clock_params);
--	if (bp_result == BP_RESULT_OK) {
--		pll_settings->actual_pix_clk = actual_pix_clk_khz;
--		pll_settings->adjusted_pix_clk =
--			bp_adjust_pixel_clock_params.adjusted_pixel_clock;
--		pll_settings->reference_divider =
--			bp_adjust_pixel_clock_params.reference_divider;
--		pll_settings->pix_clk_post_divider =
--			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
--
--		return true;
--	}
--
--	return false;
--}
--
--bool dal_pll_clock_source_construct(
--		struct pll_clock_source *pll_clk_src,
--		struct clock_source_init_data *clk_src_init_data)
--{
--	struct firmware_info fw_info = { { 0 } };
--
--	if (!dal_clock_source_construct(
--			&pll_clk_src->base,
--			clk_src_init_data))
--		return false;
--
--	if (pll_clk_src->base.bios_parser->funcs->get_firmware_info(
--			pll_clk_src->base.bios_parser,
--			&fw_info) != BP_RESULT_OK)
--		return false;
--
--	pll_clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
--
--	return true;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h b/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
-deleted file mode 100644
-index 8339e1f..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/pll_clock_source.h
-+++ /dev/null
-@@ -1,52 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_PLL_CLOCK_SOURCE_H__
--#define __DAL_PLL_CLOCK_SOURCE_H__
--
--#include "gpu/clock_source.h"
--
--struct pll_clock_source {
--	struct clock_source base;
--	uint32_t ref_freq_khz;
--};
--
--struct delta_sigma_data {
--	uint32_t feedback_amount;
--	uint32_t nfrac_amount;
--	uint32_t ds_frac_size;
--	uint32_t ds_frac_amount;
--};
--
--bool dal_pll_clock_source_construct(
--		struct pll_clock_source *pll_clk_src,
--		struct clock_source_init_data *clk_src_init_data);
--
--bool dal_pll_clock_source_adjust_pix_clk(
--		struct pll_clock_source *pll_clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings);
--bool dal_pll_clock_source_power_down_pll(
--		struct clock_source *clk_src,
--		enum controller_id controller_id);
--#endif /*__DAL_PLL_CLOCK_SOURCE_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
-new file mode 100644
-index 0000000..d7a9a0c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
-@@ -0,0 +1,176 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_CLOCK_SOURCE_H__
-+#define __DC_CLOCK_SOURCE_H__
-+
-+#include "dc_types.h"
-+#include "include/grph_object_id.h"
-+#include "include/bios_parser_types.h"
-+
-+struct clock_source;
-+
-+struct spread_spectrum_data {
-+	uint32_t percentage;		/*> In unit of 0.01% or 0.001%*/
-+	uint32_t percentage_divider;	/*> 100 or 1000	*/
-+	uint32_t freq_range_khz;
-+	uint32_t modulation_freq_hz;
-+
-+	struct spread_spectrum_flags flags;
-+};
-+
-+struct delta_sigma_data {
-+	uint32_t feedback_amount;
-+	uint32_t nfrac_amount;
-+	uint32_t ds_frac_size;
-+	uint32_t ds_frac_amount;
-+};
-+
-+/**
-+ *  Pixel Clock Parameters structure
-+ *  These parameters are required as input
-+ *  when calculating Pixel Clock Dividers for requested Pixel Clock
-+ */
-+struct pixel_clk_flags {
-+	uint32_t ENABLE_SS:1;
-+	uint32_t DISPLAY_BLANKED:1;
-+	uint32_t PROGRAM_PIXEL_CLOCK:1;
-+	uint32_t PROGRAM_ID_CLOCK:1;
-+};
-+
-+/**
-+ *  Display Port HW De spread of Reference Clock related Parameters structure
-+ *  Store it once at boot for later usage
-+  */
-+struct csdp_ref_clk_ds_params {
-+	bool hw_dso_n_dp_ref_clk;
-+/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
-+	uint32_t avg_dp_ref_clk_khz;
-+/* Average DP Reference clock (in KHz)*/
-+	uint32_t ss_percentage_on_dp_ref_clk;
-+/* DP Reference clock SS percentage
-+ * (not to be mixed with DP IDCLK SS from PLL Settings)*/
-+	uint32_t ss_percentage_divider;
-+/* DP Reference clock SS percentage divider */
-+};
-+
-+struct pixel_clk_params {
-+	uint32_t requested_pix_clk; /* in KHz */
-+/*> Requested Pixel Clock
-+ * (based on Video Timing standard used for requested mode)*/
-+	uint32_t requested_sym_clk; /* in KHz */
-+/*> Requested Sym Clock (relevant only for display port)*/
-+	uint32_t dp_ref_clk; /* in KHz */
-+/*> DP reference clock - calculated only for DP signal for specific cases*/
-+	struct graphics_object_id encoder_object_id;
-+/*> Encoder object Id - needed by VBIOS Exec table*/
-+	enum signal_type signal_type;
-+/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
-+	enum controller_id controller_id;
-+/*> ControllerId - which controller using this PLL*/
-+	enum dc_color_depth color_depth;
-+	struct csdp_ref_clk_ds_params de_spread_params;
-+/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
-+
-+	struct pixel_clk_flags flags;
-+};
-+
-+/**
-+ *  Pixel Clock Dividers structure with desired Pixel Clock
-+ *  (adjusted after VBIOS exec table),
-+ *  with actually calculated Clock and reference Crystal frequency
-+ */
-+struct pll_settings {
-+	uint32_t actual_pix_clk;
-+	uint32_t adjusted_pix_clk;
-+	uint32_t calculated_pix_clk;
-+	uint32_t vco_freq;
-+	uint32_t reference_freq;
-+	uint32_t reference_divider;
-+	uint32_t feedback_divider;
-+	uint32_t fract_feedback_divider;
-+	uint32_t pix_clk_post_divider;
-+	uint32_t ss_percentage;
-+	bool use_external_clk;
-+};
-+
-+struct calc_pll_clock_source_init_data {
-+	struct dc_bios *bp;
-+	uint32_t min_pix_clk_pll_post_divider;
-+	uint32_t max_pix_clk_pll_post_divider;
-+	uint32_t min_pll_ref_divider;
-+	uint32_t max_pll_ref_divider;
-+	uint32_t min_override_input_pxl_clk_pll_freq_khz;
-+/* if not 0, override the firmware info */
-+
-+	uint32_t max_override_input_pxl_clk_pll_freq_khz;
-+/* if not 0, override the firmware info */
-+
-+	uint32_t num_fract_fb_divider_decimal_point;
-+/* number of decimal point for fractional feedback divider value */
-+
-+	uint32_t num_fract_fb_divider_decimal_point_precision;
-+/* number of decimal point to round off for fractional feedback divider value*/
-+	struct dc_context *ctx;
-+
-+};
-+
-+struct calc_pll_clock_source {
-+	uint32_t ref_freq_khz;
-+	uint32_t min_pix_clock_pll_post_divider;
-+	uint32_t max_pix_clock_pll_post_divider;
-+	uint32_t min_pll_ref_divider;
-+	uint32_t max_pll_ref_divider;
-+
-+	uint32_t max_vco_khz;
-+	uint32_t min_vco_khz;
-+	uint32_t min_pll_input_freq_khz;
-+	uint32_t max_pll_input_freq_khz;
-+
-+	uint32_t fract_fb_divider_decimal_points_num;
-+	uint32_t fract_fb_divider_factor;
-+	uint32_t fract_fb_divider_precision;
-+	uint32_t fract_fb_divider_precision_factor;
-+	struct dc_context *ctx;
-+};
-+
-+struct clock_source_funcs {
-+	bool (*cs_power_down)(
-+			struct clock_source *, enum controller_id);
-+	bool (*program_pix_clk)(struct clock_source *,
-+			struct pixel_clk_params *, struct pll_settings *);
-+	uint32_t (*get_pix_clk_dividers)(
-+			struct clock_source *,
-+			struct pixel_clk_params *,
-+			struct pll_settings *);
-+};
-+
-+struct clock_source {
-+	struct clock_source_funcs *funcs;
-+	struct dc_context *ctx;
-+	enum clock_source_id id;
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 8282f99..d075de1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -66,7 +66,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- #include "grph_object_id.h"
- #include "link_encoder.h"
- #include "stream_encoder.h"
--#include "clock_source_interface.h"
-+#include "clock_source.h"
- #include "audio_interface.h"
- #include "scaler_types.h"
- #include "hw_sequencer_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index 6f72e25..6791866 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -26,6 +26,7 @@
- #ifndef __DAL_BIOS_PARSER_TYPES_H__
- #define __DAL_BIOS_PARSER_TYPES_H__
- 
-+#include "dc_services.h"
- #include "include/signal_types.h"
- #include "include/grph_object_ctrl_defs.h"
- #include "include/gpio_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/include/clock_source_interface.h b/drivers/gpu/drm/amd/dal/include/clock_source_interface.h
-deleted file mode 100644
-index bea4c2b..0000000
---- a/drivers/gpu/drm/amd/dal/include/clock_source_interface.h
-+++ /dev/null
-@@ -1,89 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_CLOCK_SOURCE_INTERFACE__
--#define __DAL_CLOCK_SOURCE_INTERFACE__
--
--#include "include/clock_source_types.h"
--
--struct clock_source;
--struct clock_source_init_data {
--	struct adapter_service *as;
--	struct graphics_object_id clk_src_id;
--	struct dc_context *ctx;
--};
--
--struct clock_source *dal_clock_source_create(struct clock_source_init_data *);
--
--void dal_clock_source_destroy(struct clock_source **clk_src);
--
--enum clock_source_id dal_clock_source_get_id(
--		const struct clock_source *clk_src);
--
--bool dal_clock_source_is_clk_src_with_fixed_freq(
--		const struct clock_source *clk_src);
--
--const struct graphics_object_id dal_clock_source_get_graphics_object_id(
--		const struct clock_source *clk_src);
--
--enum clock_sharing_level dal_clock_souce_get_clk_sharing_lvl(
--		const struct clock_source *clk_src);
--
--uint32_t dal_clock_source_get_pix_clk_dividers(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings);
--
--bool dal_clock_source_program_pix_clk(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings);
--
--bool dal_clock_source_adjust_pxl_clk_by_ref_pixel_rate(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		uint32_t pix_clk_hz);
--
--bool dal_clock_source_adjust_pxl_clk_by_pix_amount(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		int32_t pix_num);
--
--uint32_t dal_clock_source_retreive_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params);
--
--bool dal_clock_source_power_down_pll(struct clock_source *clk_src,
--		enum controller_id);
--
--bool dal_clock_source_is_clk_in_reset(struct clock_source *clk_src);
--
--bool dal_clock_source_is_gen_lock_capable(struct clock_source *clk_src);
--
--bool dal_clock_source_is_output_signal_supported(
--		const struct clock_source *clk_src,
--		enum signal_type signal_type);
--
--#endif /*__DAL_CLOCK_SOURCE_INTERFACE__*/
-diff --git a/drivers/gpu/drm/amd/dal/include/clock_source_types.h b/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-deleted file mode 100644
-index 4c323a9..0000000
---- a/drivers/gpu/drm/amd/dal/include/clock_source_types.h
-+++ /dev/null
-@@ -1,113 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_CLOCK_SOURCE_TYPES_H__
--#define __DAL_CLOCK_SOURCE_TYPES_H__
--
--#include "include/signal_types.h"
--#include "include/grph_object_ctrl_defs.h"
--
--/**
-- *  ClockSharingLevel
-- *  Enumeration for clock sharing support.
-- *  Level <x> means sharing supported on all levels below and including <x>
-- */
--enum clock_sharing_level {
--	CLOCK_SHARING_LEVEL_NOT_SHAREABLE = 0,
--	CLOCK_SHARING_LEVEL_DP_MST_SHAREABLE,
--	CLOCK_SHARING_LEVEL_DISPLAY_PORT_SHAREABLE
--};
--
--/**
-- *  Display Port HW De spread of Reference Clock related Parameters structure
-- *  Store it once at boot for later usage
--  */
--struct csdp_ref_clk_ds_params {
--	bool hw_dso_n_dp_ref_clk;
--/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
--	uint32_t avg_dp_ref_clk_khz;
--/* Average DP Reference clock (in KHz)*/
--	uint32_t ss_percentage_on_dp_ref_clk;
--/* DP Reference clock SS percentage
-- * (not to be mixed with DP IDCLK SS from PLL Settings)*/
--	uint32_t ss_percentage_divider;
--/* DP Reference clock SS percentage divider */
--};
--
--/**
-- *  Pixel Clock Parameters structure
-- *  These parameters are required as input
-- *  when calculating Pixel Clock Dividers for requested Pixel Clock
-- */
--struct pixel_clk_flags {
--	uint32_t ENABLE_SS:1;
--	uint32_t DISPLAY_BLANKED:1;
--	uint32_t PROGRAM_PIXEL_CLOCK:1;
--	uint32_t PROGRAM_ID_CLOCK:1;
--};
--
--struct pixel_clk_params {
--	uint32_t requested_pix_clk; /* in KHz */
--/*> Requested Pixel Clock
-- * (based on Video Timing standard used for requested mode)*/
--	uint32_t requested_sym_clk; /* in KHz */
--/*> Requested Sym Clock (relevant only for display port)*/
--	uint32_t dp_ref_clk; /* in KHz */
--/*> DP reference clock - calculated only for DP signal for specific cases*/
--	struct graphics_object_id encoder_object_id;
--/*> Encoder object Id - needed by VBIOS Exec table*/
--	enum signal_type signal_type;
--/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
--	enum controller_id controller_id;
--/*> ControllerId - which controller using this PLL*/
--	enum dc_color_depth color_depth;
--	struct csdp_ref_clk_ds_params de_spread_params;
--/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
--
--	struct pixel_clk_flags flags;
--};
--
--/**
-- *  Pixel Clock Dividers structure with desired Pixel Clock
-- *  (adjusted after VBIOS exec table),
-- *  with actually calculated Clock and reference Crystal frequency
-- */
--struct pll_settings {
--	uint32_t actual_pix_clk;
--	uint32_t adjusted_pix_clk;
--	uint32_t calculated_pix_clk;
--	uint32_t vco_freq;
--	uint32_t reference_freq;
--	uint32_t reference_divider;
--	uint32_t feedback_divider;
--	uint32_t fract_feedback_divider;
--	uint32_t pix_clk_post_divider;
--	uint32_t ss_percentage;
--	bool use_external_clk;
--};
--
--#define MAX_PLL_CALC_ERROR 0xFFFFFFFF
--
--#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch b/common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch
deleted file mode 100644
index c19661c4..00000000
--- a/common/recipes-kernel/linux/files/0739-drm-amd-dal-Clean-up-dc_temp.h.patch
+++ /dev/null
@@ -1,1390 +0,0 @@
-From 7aaf1d3c2261a553a0d07b48afd1666475344727 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 25 Jan 2016 17:55:30 -0500
-Subject: [PATCH 0739/1110] drm/amd/dal: Clean up dc_temp.h
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  10 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  45 --
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  12 +-
- drivers/gpu/drm/amd/dal/dc/dc_temp.h               | 507 ---------------------
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 257 ++++++++++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     |   4 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   |   1 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |   4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |   1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |   2 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c |   1 +
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   1 +
- drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h       | 117 +++++
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   9 +
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |   1 +
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               |  62 ++-
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |   2 +
- drivers/gpu/drm/amd/dal/include/fixed32_32.h       |   2 +
- .../gpu/drm/amd/dal/include/video_gamma_types.h    |   1 +
- 23 files changed, 474 insertions(+), 572 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dc_temp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 5fe5ca4..70d5dae 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -59,6 +59,7 @@ struct dm_connector_state {
- 	container_of((x), struct dm_connector_state, base)
- 
- #define AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET 1
-+#define MAX_TARGET_NUM 6
- 
- void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
- {
-@@ -314,15 +315,6 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc,
- 		return -EINVAL;
- 	}
- 
--#if BUILD_FEATURE_TIMING_SYNC
--	{
--		struct drm_device *dev = crtc->dev;
--		struct amdgpu_device *adev = dev->dev_private;
--		struct amdgpu_display_manager *dm = &adev->dm;
--
--		dc_print_sync_report(dm->dc);
--	}
--#endif
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 51a8589..1a17090 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -55,11 +55,6 @@ struct dc_target_sync_report {
- 	uint32_t v_count;
- };
- 
--struct dc_sync_report {
--	uint32_t targets_num;
--	struct dc_target_sync_report trg_reports[MAX_TARGET_NUM];
--};
--
- /*******************************************************************************
-  * Private functions
-  ******************************************************************************/
-@@ -794,46 +789,6 @@ void dc_resume(const struct dc *dc)
- 		core_link_resume(dc->links[i]);
- }
- 
--void dc_print_sync_report(
--	const struct dc *dc)
--{
--	uint32_t i;
--	const struct core_target *core_target;
--	const struct core_stream *core_stream;
--	struct dc_context *dc_ctx = dc->ctx;
--	struct dc_target_sync_report *target_sync_report;
--	struct dc_sync_report sync_report = { 0 };
--
--	if (dc->current_context.target_count > MAX_TARGET_NUM) {
--		DC_ERROR("Target count: %d > %d!\n",
--			dc->current_context.target_count,
--			MAX_TARGET_NUM);
--		return;
--	}
--
--	sync_report.targets_num = dc->current_context.target_count;
--
--	/* Step 1: get data for sync validation */
--	for (i = 0; i < dc->current_context.target_count; i++) {
--
--		core_target = dc->current_context.targets[i];
--		target_sync_report = &sync_report.trg_reports[i];
--		core_stream = DC_STREAM_TO_CORE(core_target->public.streams[0]);
--
--		dc->hwss.get_crtc_positions(
--			core_stream->tg,
--			&target_sync_report->h_count,
--			&target_sync_report->v_count);
--
--		DC_SYNC_INFO("GSL:target[%d]: h: %d\t v: %d\n",
--				i,
--				target_sync_report->h_count,
--				target_sync_report->v_count);
--	}
--
--	/* Step 2: validate that display pipes are synchronized (based on
--	 * data from Step 1). */
--}
- 
- bool dc_read_dpcd(
- 		struct dc *dc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index a06a8a7..fcc79ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -68,7 +68,7 @@ struct dc_surface {
- 	struct rect clip_rect;
- 
- 	union plane_size plane_size;
--	union plane_tiling_info tiling_info;
-+	union dc_tiling_info tiling_info;
- 	struct plane_colorimetry colorimetry;
- 
- 	enum surface_pixel_format format;
-@@ -351,6 +351,16 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
- /*******************************************************************************
-  * Cursor interfaces - To manages the cursor within a target
-  ******************************************************************************/
-+/* TODO: Deprecated once we switch to dc_set_cursor_position */
-+bool dc_target_set_cursor_attributes(
-+	struct dc_target *dc_target,
-+	const struct dc_cursor_attributes *attributes);
-+
-+bool dc_target_set_cursor_position(
-+	struct dc_target *dc_target,
-+	const struct dc_cursor_position *position);
-+
-+/* Newer interfaces  */
- struct dc_cursor {
- 	struct dc_plane_address address;
- 	struct dc_cursor_attributes attributes;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_temp.h b/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-deleted file mode 100644
-index fc5b810..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dc_temp.h
-+++ /dev/null
-@@ -1,507 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef DC_TEMP_H_
--#define DC_TEMP_H_
--
--#include "dc_types.h"
--
--#define MAX_SURFACE_NUM 2
--
--enum clamping_range {
--	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
--	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
--	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
--	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
--	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
--	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
--};
--
--struct clamping_and_pixel_encoding_params {
--	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
--	enum clamping_range clamping_level; /* Clamping identifier */
--	enum dc_color_depth c_depth; /* Deep color use. */
--};
--
--struct bit_depth_reduction_params {
--	struct {
--		/* truncate/round */
--		/* trunc/round enabled*/
--		uint32_t TRUNCATE_ENABLED:1;
--		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
--		uint32_t TRUNCATE_DEPTH:2;
--		/* truncate or round*/
--		uint32_t TRUNCATE_MODE:1;
--
--		/* spatial dither */
--		/* Spatial Bit Depth Reduction enabled*/
--		uint32_t SPATIAL_DITHER_ENABLED:1;
--		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
--		uint32_t SPATIAL_DITHER_DEPTH:2;
--		/* 0-3 to select patterns*/
--		uint32_t SPATIAL_DITHER_MODE:2;
--		/* Enable RGB random dithering*/
--		uint32_t RGB_RANDOM:1;
--		/* Enable Frame random dithering*/
--		uint32_t FRAME_RANDOM:1;
--		/* Enable HighPass random dithering*/
--		uint32_t HIGHPASS_RANDOM:1;
--
--		/* temporal dither*/
--		 /* frame modulation enabled*/
--		uint32_t FRAME_MODULATION_ENABLED:1;
--		/* same as for trunc/spatial*/
--		uint32_t FRAME_MODULATION_DEPTH:2;
--		/* 2/4 gray levels*/
--		uint32_t TEMPORAL_LEVEL:1;
--		uint32_t FRC25:2;
--		uint32_t FRC50:2;
--		uint32_t FRC75:2;
--	} flags;
--
--	uint32_t r_seed_value;
--	uint32_t b_seed_value;
--	uint32_t g_seed_value;
--};
--
--enum pipe_gating_control {
--	PIPE_GATING_CONTROL_DISABLE = 0,
--	PIPE_GATING_CONTROL_ENABLE,
--	PIPE_GATING_CONTROL_INIT
--};
--
--enum surface_color_space {
--	SURFACE_COLOR_SPACE_SRGB = 0x0000,
--	SURFACE_COLOR_SPACE_BT601 = 0x0001,
--	SURFACE_COLOR_SPACE_BT709 = 0x0002,
--	SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004,
--	SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008,
--	SURFACE_COLOR_SPACE_XRRGB = 0x0010
--};
--
--enum {
--    MAX_LANES = 2,
--    MAX_COFUNC_PATH = 6,
--    LAYER_INDEX_PRIMARY = -1,
--};
--
--/* Scaling format */
--enum scaling_transformation {
--    SCALING_TRANSFORMATION_UNINITIALIZED,
--    SCALING_TRANSFORMATION_IDENTITY = 0x0001,
--    SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
--    SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
--    SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
--    SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
--    SCALING_TRANSFORMATION_INVALID = 0x80000000,
--
--    /* Flag the first and last */
--    SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
--    SCALING_TRANSFORMATION_END =
--            SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
--};
--
--struct view_stereo_3d_support {
--    enum view_3d_format format;
--    struct {
--        uint32_t CLONE_MODE:1;
--        uint32_t SCALING:1;
--        uint32_t SINGLE_FRAME_SW_PACKED:1;
--    } features;
--};
--
--struct plane_colorimetry {
--	enum surface_color_space color_space;
--	bool limited_range;
--};
--
--enum tiling_mode {
--    TILING_MODE_INVALID,
--    TILING_MODE_LINEAR,
--    TILING_MODE_TILED,
--    TILING_MODE_COUNT
--};
--
--struct view_position {
--    uint32_t x;
--    uint32_t y;
--};
--
--union plane_tiling_info {
--
--	struct {
--		/* Specifies the number of memory banks for tiling
--		 *	purposes.
--		 * Only applies to 2D and 3D tiling modes.
--		 *	POSSIBLE VALUES: 2,4,8,16
--		 */
--		uint32_t NUM_BANKS:5;
--		/* Specifies the number of tiles in the x direction
--		 *	to be incorporated into the same bank.
--		 * Only applies to 2D and 3D tiling modes.
--		 *	POSSIBLE VALUES: 1,2,4,8
--		 */
--		uint32_t BANK_WIDTH:4;
--		/* Specifies the number of tiles in the y direction to
--		 *	be incorporated into the same bank.
--		 * Only applies to 2D and 3D tiling modes.
--		 *	POSSIBLE VALUES: 1,2,4,8
--		 */
--		uint32_t BANK_HEIGHT:4;
--		/* Specifies the macro tile aspect ratio. Only applies
--		 * to 2D and 3D tiling modes.
--		 */
--		uint32_t TILE_ASPECT:3;
--		/* Specifies the number of bytes that will be stored
--		 *	contiguously for each tile.
--		 * If the tile data requires more storage than this
--		 *	amount, it is split into multiple slices.
--		 * This field must not be larger than
--		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
--		 * Only applies to 2D and 3D tiling modes.
--		 * For color render targets, TILE_SPLIT >= 256B.
--		 */
--		uint32_t TILE_SPLIT:3;
--		/* Specifies the addressing within a tile.
--		 *	0x0 - DISPLAY_MICRO_TILING
--		 *	0x1 - THIN_MICRO_TILING
--		 *	0x2 - DEPTH_MICRO_TILING
--		 *	0x3 - ROTATED_MICRO_TILING
--		 */
--		uint32_t TILE_MODE:2;
--		/* Specifies the number of pipes and how they are
--		 *	interleaved in the surface.
--		 * Refer to memory addressing document for complete
--		 *	details and constraints.
--		 */
--		uint32_t PIPE_CONFIG:5;
--		/* Specifies the tiling mode of the surface.
--		 * THIN tiles use an 8x8x1 tile size.
--		 * THICK tiles use an 8x8x4 tile size.
--		 * 2D tiling modes rotate banks for successive Z slices
--		 * 3D tiling modes rotate pipes and banks for Z slices
--		 * Refer to memory addressing document for complete
--		 *	details and constraints.
--		 */
--		uint32_t ARRAY_MODE:4;
--	} grph;
--
--
--	struct {
--		/*possible values: 2,4,8,16*/
--		uint32_t NUM_BANKS:5;
--		/*must use enum video_array_mode*/
--		uint32_t ARRAY_MODE:4;
--		/*must use enum addr_pipe_config*/
--		uint32_t PIPE_CONFIG:5;
--		/*possible values 1,2,4,8 */
--		uint32_t BANK_WIDTH_LUMA:4;
--		/*possible values 1,2,4,8 */
--		uint32_t BANK_HEIGHT_LUMA:4;
--		/*must use enum macro_tile_aspect*/
--		uint32_t TILE_ASPECT_LUMA:3;
--		/*must use enum tile_split*/
--		uint32_t TILE_SPLIT_LUMA:3;
--		/*must use micro_tile_mode */
--		uint32_t TILE_MODE_LUMA:2;
--		/*possible values: 1,2,4,8*/
--		uint32_t BANK_WIDTH_CHROMA:4;
--		/*possible values: 1,2,4,8*/
--		uint32_t BANK_HEIGHT_CHROMA:4;
--		/*must use enum macro_tile_aspect*/
--		uint32_t TILE_ASPECT_CHROMA:3;
--		/*must use enum tile_split*/
--		uint32_t TILE_SPLIT_CHROMA:3;
--		/*must use enum micro_tile_mode*/
--		uint32_t TILE_MODE_CHROMA:2;
--
--	} video;
--
--	uint64_t value;
--};
--
--union plane_size {
--	/* Grph or Video will be selected
--	 * based on format above:
--	 * Use Video structure if
--	 * format >= DalPixelFormat_VideoBegin
--	 * else use Grph structure
--	 */
--	struct {
--		struct rect surface_size;
--		/* Graphic surface pitch in pixels.
--		 * In LINEAR_GENERAL mode, pitch
--		 * is 32 pixel aligned.
--		 */
--		uint32_t surface_pitch;
--	} grph;
--
--	struct {
--		struct rect luma_size;
--		/* Graphic surface pitch in pixels.
--		 * In LINEAR_GENERAL mode, pitch is
--		 * 32 pixel aligned.
--		 */
--		uint32_t luma_pitch;
--
--		struct rect chroma_size;
--		/* Graphic surface pitch in pixels.
--		 * In LINEAR_GENERAL mode, pitch is
--		 * 32 pixel aligned.
--		 */
--		uint32_t chroma_pitch;
--	} video;
--};
--
--enum dc_scaling_transform {
--	SCL_TRANS_CENTERED = 0,
--	SCL_TRANS_ASPECT_RATIO,
--	SCL_TRANS_FULL
--};
--
--struct dev_c_lut {
--	uint8_t red;
--	uint8_t green;
--	uint8_t blue;
--};
--
--struct dev_c_lut16 {
--	uint16_t red;
--	uint16_t green;
--	uint16_t blue;
--};
--
--enum gamma_ramp_type {
--	GAMMA_RAMP_UNINITIALIZED = 0,
--	GAMMA_RAMP_DEFAULT,
--	GAMMA_RAMP_RBG256X3X16,
--	GAMMA_RAMP_DXGI_1,
--};
--
--enum surface_type {
--	OVERLAY_SURFACE = 1, GRAPHIC_SURFACE
--};
--
--#define CONST_RGB_GAMMA_VALUE 2400
--
--enum {
--	RGB_256X3X16 = 256, DX_GAMMA_RAMP_MAX = 1025
--};
--
--struct gamma_ramp_rgb256x3x16 {
--	uint16_t red[RGB_256X3X16];
--	uint16_t green[RGB_256X3X16];
--	uint16_t blue[RGB_256X3X16];
--};
--
--struct dxgi_rgb {
--	struct fixed32_32 red;
--	struct fixed32_32 green;
--	struct fixed32_32 blue;
--};
--
--struct gamma_ramp_dxgi_1 {
--	struct dxgi_rgb scale;
--	struct dxgi_rgb offset;
--	struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX];
--};
--
--struct gamma_ramp {
--	enum gamma_ramp_type type;
--	union {
--		struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
--		struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1;
--	};
--	uint32_t size;
--};
--
--struct regamma_ramp {
--	uint16_t gamma[RGB_256X3X16 * 3];
--};
--
--/* used by Graphics and Overlay gamma */
--struct gamma_coeff {
--	int32_t gamma[3];
--	int32_t a0[3]; /* index 0 for red, 1 for green, 2 for blue */
--	int32_t a1[3];
--	int32_t a2[3];
--	int32_t a3[3];
--};
--
--struct regamma_lut {
--	union {
--		struct {
--			uint32_t GRAPHICS_DEGAMMA_SRGB :1;
--			uint32_t OVERLAY_DEGAMMA_SRGB :1;
--			uint32_t GAMMA_RAMP_ARRAY :1;
--			uint32_t APPLY_DEGAMMA :1;
--			uint32_t RESERVED :28;
--		} bits;
--		uint32_t value;
--	} features;
--
--	union {
--		struct regamma_ramp regamma_ramp;
--		struct gamma_coeff gamma_coeff;
--	};
--};
--
--union gamma_flag {
--	struct {
--		uint32_t config_is_changed :1;
--		uint32_t both_pipe_req :1;
--		uint32_t regamma_update :1;
--		uint32_t gamma_update :1;
--		uint32_t reserved :28;
--	} bits;
--	uint32_t u_all;
--};
--
--enum graphics_regamma_adjust {
--	GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */
--	GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */
--};
--
--enum graphics_gamma_lut {
--	GRAPHICS_GAMMA_LUT_LEGACY = 0, /* use only legacy LUT */
--	GRAPHICS_GAMMA_LUT_REGAMMA, /* use only regamma LUT */
--	GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA /* use legacy & regamma LUT's */
--};
--
--enum graphics_degamma_adjust {
--	GRAPHICS_DEGAMMA_ADJUST_BYPASS = 0, GRAPHICS_DEGAMMA_ADJUST_HW, /*without adjustments */
--	GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */
--};
--
--struct gamma_parameters {
--	union gamma_flag flag;
--	enum pixel_format surface_pixel_format; /*OS surface pixel format*/
--	struct regamma_lut regamma;
--
--	enum graphics_regamma_adjust regamma_adjust_type;
--	enum graphics_degamma_adjust degamma_adjust_type;
--
--	enum graphics_gamma_lut selected_gamma_lut;
--
--	bool disable_adjustments;
--
--	/* here we grow with parameters if necessary */
--};
--
--struct pixel_format_support {
--	bool INDEX8 :1;
--	bool RGB565 :1;
--	bool ARGB8888 :1;
--	bool ARGB2101010 :1;
--	bool ARGB2101010_XRBIAS :1;
--	bool FP16 :1;
--};
--
--struct render_mode {
--	struct view view;
--	enum pixel_format pixel_format;
--};
--
--struct refresh_rate {
--	uint32_t field_rate;
--	bool INTERLACED :1;
--	bool VIDEO_OPTIMIZED_RATE :1;
--};
--
--struct stereo_3d_view {
--	enum view_3d_format view_3d_format;
--	union {
--		uint32_t raw;
--		struct /*stereo_3d_view_flags*/
--		{
--			bool SINGLE_FRAME_SW_PACKED :1;
--			bool EXCLUSIVE_3D :1;
--		} bits;
--	} flags;
--};
--
--enum solution_importance {
--	SOLUTION_IMPORTANCE_PREFERRED = 1,
--	/* Means we want to use this solution
--	 * even in wide topology configurations*/
--	SOLUTION_IMPORTANCE_SAFE,
--	SOLUTION_IMPORTANCE_UNSAFE,
--	SOLUTION_IMPORTANCE_DEFAULT
--/* Temporary state , means Solution object
-- * should define importance by itself
-- */
--};
--
--struct solution {
--	const struct dc_mode_timing *dc_mode_timing;
--	enum solution_importance importance;
--	bool is_custom_mode;
--	uint32_t scl_support[NUM_PIXEL_FORMATS];
--	/* bit vector of the scaling that can be supported on the timing */
--	uint32_t scl_support_guaranteed[NUM_PIXEL_FORMATS];
--	/* subset of m_sclSupport that can be guaranteed supported */
--};
--
--enum timing_select {
--	TIMING_SELECT_DEFAULT,
--	TIMING_SELECT_NATIVE_ONLY,
--	TIMING_SELECT_PRESERVE_ASPECT
--};
--
--enum downscale_state {
--	DOWNSCALESTATE_DEFAULT,     // Disabled, but not user selected
--	DOWNSCALESTATE_DISABLED,    // User disabled through CCC
--	DOWNSCALESTATE_ENABLED      // User enabled through CCC
--};
--struct scaling_support {
--	bool IDENTITY :1;
--	bool FULL_SCREEN_SCALE :1;
--	bool PRESERVE_ASPECT_RATIO_SCALE :1;
--	bool CENTER_TIMING :1;
--};
--
--
--/* TODO: combine the two cursor functions into one to make cursor
-- * programming resistant to changes in OS call sequence. */
--bool dc_target_set_cursor_attributes(
--	struct dc_target *dc_target,
--	const struct dc_cursor_attributes *attributes);
--
--bool dc_target_set_cursor_position(
--	struct dc_target *dc_target,
--	const struct dc_cursor_position *position);
--
--/******************************************************************************
-- * TODO: these definitions only for Timing Sync feature bring-up. Remove
-- * when the feature is complete.
-- *****************************************************************************/
--
--#define MAX_TARGET_NUM 6
--
--void dc_print_sync_report(
--	const struct dc *dc);
--
--/******************************************************************************/
--
--#endif /* DC_TEMP_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 60e5603..fe7046f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -63,6 +63,17 @@ enum dce_environment {
- /********************************/
- 
- #define MAX_EDID_BUFFER_SIZE 512
-+#define MAX_SURFACE_NUM 2
-+#define NUM_PIXEL_FORMATS 10
-+
-+enum surface_color_space {
-+	SURFACE_COLOR_SPACE_SRGB = 0x0000,
-+	SURFACE_COLOR_SPACE_BT601 = 0x0001,
-+	SURFACE_COLOR_SPACE_BT709 = 0x0002,
-+	SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004,
-+	SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008,
-+	SURFACE_COLOR_SPACE_XRRGB = 0x0010
-+};
- 
- /*Displayable pixel format in fb*/
- enum surface_pixel_format {
-@@ -174,9 +185,6 @@ enum dc_pixel_encoding {
-  *  Please increase if pixel_format enum increases
-  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-  */
--#define NUM_PIXEL_FORMATS 10
--
--
- 
- union large_integer {
- 	struct {
-@@ -211,6 +219,11 @@ enum dc_edid_status {
- 	EDID_BAD_CHECKSUM,
- };
- 
-+struct plane_colorimetry {
-+	enum surface_color_space color_space;
-+	bool limited_range;
-+};
-+
- /* audio capability from EDID*/
- struct dc_cea_audio_mode {
- 	uint8_t format_code; /* ucData[0] [6:3]*/
-@@ -710,6 +723,47 @@ enum dc_connection_type {
-  * returns 0.
-  *
-  */
-+/* TODO: Deprecated */
-+enum {
-+	RGB_256X3X16 = 256,
-+	DX_GAMMA_RAMP_MAX = 1025
-+};
-+
-+enum gamma_ramp_type {
-+	GAMMA_RAMP_UNINITIALIZED = 0,
-+	GAMMA_RAMP_DEFAULT,
-+	GAMMA_RAMP_RBG256X3X16,
-+	GAMMA_RAMP_DXGI_1,
-+};
-+
-+struct dxgi_rgb {
-+	struct fixed32_32 red;
-+	struct fixed32_32 green;
-+	struct fixed32_32 blue;
-+};
-+
-+struct gamma_ramp_dxgi_1 {
-+	struct dxgi_rgb scale;
-+	struct dxgi_rgb offset;
-+	struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX];
-+};
-+
-+struct gamma_ramp_rgb256x3x16 {
-+	uint16_t red[RGB_256X3X16];
-+	uint16_t green[RGB_256X3X16];
-+	uint16_t blue[RGB_256X3X16];
-+};
-+
-+struct gamma_ramp {
-+	enum gamma_ramp_type type;
-+	union {
-+		struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
-+		struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1;
-+	};
-+	uint32_t size;
-+};
-+
-+
- struct dc_gamma_ramp {
- 	uint32_t (*get_gamma_value) (
- 			void *context,
-@@ -728,6 +782,201 @@ struct dc_csc_adjustments {
- 	struct fixed31_32 hue;
- };
- 
--#include "dc_temp.h"
-+
-+enum {
-+	MAX_LANES = 2,
-+	MAX_COFUNC_PATH = 6,
-+	LAYER_INDEX_PRIMARY = -1,
-+};
-+
-+/* Scaling format */
-+enum scaling_transformation {
-+	SCALING_TRANSFORMATION_UNINITIALIZED,
-+	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
-+	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
-+	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
-+	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
-+	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
-+	SCALING_TRANSFORMATION_INVALID = 0x80000000,
-+
-+	/* Flag the first and last */
-+	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
-+	SCALING_TRANSFORMATION_END =
-+		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
-+};
-+
-+struct view_stereo_3d_support {
-+	enum view_3d_format format;
-+	struct {
-+		uint32_t CLONE_MODE:1;
-+		uint32_t SCALING:1;
-+		uint32_t SINGLE_FRAME_SW_PACKED:1;
-+	} features;
-+};
-+
-+enum tiling_mode {
-+	TILING_MODE_INVALID,
-+	TILING_MODE_LINEAR,
-+	TILING_MODE_TILED,
-+	TILING_MODE_COUNT
-+};
-+
-+struct view_position {
-+	uint32_t x;
-+	uint32_t y;
-+};
-+
-+struct render_mode {
-+	struct view view;
-+	enum pixel_format pixel_format;
-+};
-+
-+struct pixel_format_support {
-+	bool INDEX8 :1;
-+	bool RGB565 :1;
-+	bool ARGB8888 :1;
-+	bool ARGB2101010 :1;
-+	bool ARGB2101010_XRBIAS :1;
-+	bool FP16 :1;
-+};
-+
-+struct stereo_3d_view {
-+	enum view_3d_format view_3d_format;
-+	union {
-+		uint32_t raw;
-+		struct /*stereo_3d_view_flags*/
-+		{
-+			bool SINGLE_FRAME_SW_PACKED :1;
-+			bool EXCLUSIVE_3D :1;
-+		} bits;
-+	} flags;
-+};
-+
-+/* TODO: Rename to dc_tiling_info */
-+union dc_tiling_info {
-+
-+	struct {
-+		/* Specifies the number of memory banks for tiling
-+		 *	purposes.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 2,4,8,16
-+		 */
-+		uint32_t NUM_BANKS:5;
-+		/* Specifies the number of tiles in the x direction
-+		 *	to be incorporated into the same bank.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 1,2,4,8
-+		 */
-+		uint32_t BANK_WIDTH:4;
-+		/* Specifies the number of tiles in the y direction to
-+		 *	be incorporated into the same bank.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 1,2,4,8
-+		 */
-+		uint32_t BANK_HEIGHT:4;
-+		/* Specifies the macro tile aspect ratio. Only applies
-+		 * to 2D and 3D tiling modes.
-+		 */
-+		uint32_t TILE_ASPECT:3;
-+		/* Specifies the number of bytes that will be stored
-+		 *	contiguously for each tile.
-+		 * If the tile data requires more storage than this
-+		 *	amount, it is split into multiple slices.
-+		 * This field must not be larger than
-+		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 * For color render targets, TILE_SPLIT >= 256B.
-+		 */
-+		uint32_t TILE_SPLIT:3;
-+		/* Specifies the addressing within a tile.
-+		 *	0x0 - DISPLAY_MICRO_TILING
-+		 *	0x1 - THIN_MICRO_TILING
-+		 *	0x2 - DEPTH_MICRO_TILING
-+		 *	0x3 - ROTATED_MICRO_TILING
-+		 */
-+		uint32_t TILE_MODE:2;
-+		/* Specifies the number of pipes and how they are
-+		 *	interleaved in the surface.
-+		 * Refer to memory addressing document for complete
-+		 *	details and constraints.
-+		 */
-+		uint32_t PIPE_CONFIG:5;
-+		/* Specifies the tiling mode of the surface.
-+		 * THIN tiles use an 8x8x1 tile size.
-+		 * THICK tiles use an 8x8x4 tile size.
-+		 * 2D tiling modes rotate banks for successive Z slices
-+		 * 3D tiling modes rotate pipes and banks for Z slices
-+		 * Refer to memory addressing document for complete
-+		 *	details and constraints.
-+		 */
-+		uint32_t ARRAY_MODE:4;
-+	} grph;
-+
-+
-+	struct {
-+		/*possible values: 2,4,8,16*/
-+		uint32_t NUM_BANKS:5;
-+		/*must use enum video_array_mode*/
-+		uint32_t ARRAY_MODE:4;
-+		/*must use enum addr_pipe_config*/
-+		uint32_t PIPE_CONFIG:5;
-+		/*possible values 1,2,4,8 */
-+		uint32_t BANK_WIDTH_LUMA:4;
-+		/*possible values 1,2,4,8 */
-+		uint32_t BANK_HEIGHT_LUMA:4;
-+		/*must use enum macro_tile_aspect*/
-+		uint32_t TILE_ASPECT_LUMA:3;
-+		/*must use enum tile_split*/
-+		uint32_t TILE_SPLIT_LUMA:3;
-+		/*must use micro_tile_mode */
-+		uint32_t TILE_MODE_LUMA:2;
-+		/*possible values: 1,2,4,8*/
-+		uint32_t BANK_WIDTH_CHROMA:4;
-+		/*possible values: 1,2,4,8*/
-+		uint32_t BANK_HEIGHT_CHROMA:4;
-+		/*must use enum macro_tile_aspect*/
-+		uint32_t TILE_ASPECT_CHROMA:3;
-+		/*must use enum tile_split*/
-+		uint32_t TILE_SPLIT_CHROMA:3;
-+		/*must use enum micro_tile_mode*/
-+		uint32_t TILE_MODE_CHROMA:2;
-+
-+	} video;
-+
-+	uint64_t value;
-+};
-+
-+union plane_size {
-+	/* Grph or Video will be selected
-+	 * based on format above:
-+	 * Use Video structure if
-+	 * format >= DalPixelFormat_VideoBegin
-+	 * else use Grph structure
-+	 */
-+	struct {
-+		struct rect surface_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch
-+		 * is 32 pixel aligned.
-+		 */
-+		uint32_t surface_pitch;
-+	} grph;
-+
-+	struct {
-+		struct rect luma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		uint32_t luma_pitch;
-+
-+		struct rect chroma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		uint32_t chroma_pitch;
-+	} video;
-+};
- 
- #endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index af7cf0d..046a9a5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -30,6 +30,7 @@
- #include "resource.h"
- #include "hw_sequencer.h"
- #include "dc_helpers.h"
-+#include "gamma_types.h"
- 
- #include "dce110/dce110_resource.h"
- #include "dce110/dce110_timing_generator.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index f0e9e7d..709906f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -28,6 +28,10 @@
- 
- #include "inc/ipp.h"
- 
-+
-+struct gamma_parameters;
-+struct dev_c_lut;
-+
- #define TO_DCE110_IPP(input_pixel_processor)\
- 	container_of(input_pixel_processor, struct dce110_ipp, base)
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index 2aa432a..a30c0da 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -32,6 +32,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dce110_ipp.h"
-+#include "gamma_types.h"
- 
- #define DCP_REG(reg)\
- 	(reg + ipp110->offsets.dcp_offset)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 4e809b6..b70c8e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -179,7 +179,7 @@ static void enable(struct dce110_mem_input *mem_input110)
- 
- static void program_tiling(
- 	struct dce110_mem_input *mem_input110,
--	const union plane_tiling_info *info,
-+	const union dc_tiling_info *info,
- 	const enum surface_pixel_format pixel_format)
- {
- 	uint32_t value = 0;
-@@ -458,7 +458,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- bool dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
- 	enum surface_pixel_format format,
--	union plane_tiling_info *tiling_info,
-+	union dc_tiling_info *tiling_info,
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 997070b..cd19169 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -109,7 +109,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- bool  dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
- 	enum surface_pixel_format format,
--	union plane_tiling_info *tiling_info,
-+	union dc_tiling_info *tiling_info,
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 99163ee..7dcfd2e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -30,6 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dce110_opp.h"
-+#include "gamma_types.h"
- 
- enum {
- 	MAX_LUT_ENTRY = 256,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index f9b828c..e53eb74 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -27,7 +27,9 @@
- 
- #include "dc_types.h"
- #include "inc/opp.h"
-+#include "gamma_types.h"
- 
-+struct gamma_parameters;
- 
- #define FROM_DCE11_OPP(opp)\
- 	container_of(opp, struct dce110_opp, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index dceba7d..f589025 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -30,6 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dce110_opp.h"
-+#include "gamma_types.h"
- 
- #define DCP_REG(reg)\
- 	(reg + opp110->offsets.dcp_offset)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index d0e4b98..a64a507 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -30,7 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dce110_transform.h"
--
-+#include "opp.h"
- #include "include/logger_interface.h"
- #include "include/fixed32_32.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index d075de1..e3b5918 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -70,6 +70,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- #include "audio_interface.h"
- #include "scaler_types.h"
- #include "hw_sequencer_types.h"
-+#include "opp.h"
- 
- #define DC_STREAM_TO_CORE(dc_stream) container_of( \
- 	dc_stream, struct core_stream, public)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-new file mode 100644
-index 0000000..048303e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-@@ -0,0 +1,117 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef GAMMA_TYPES_H_
-+#define GAMMA_TYPES_H_
-+
-+#include "dc_types.h"
-+#include "dc_services_types.h"
-+
-+/* TODO: Used in IPP and OPP */
-+struct dev_c_lut {
-+	uint8_t red;
-+	uint8_t green;
-+	uint8_t blue;
-+};
-+
-+struct dev_c_lut16 {
-+	uint16_t red;
-+	uint16_t green;
-+	uint16_t blue;
-+};
-+
-+struct regamma_ramp {
-+	uint16_t gamma[RGB_256X3X16 * 3];
-+};
-+
-+/* used by Graphics and Overlay gamma */
-+struct gamma_coeff {
-+	int32_t gamma[3];
-+	int32_t a0[3]; /* index 0 for red, 1 for green, 2 for blue */
-+	int32_t a1[3];
-+	int32_t a2[3];
-+	int32_t a3[3];
-+};
-+
-+struct regamma_lut {
-+	union {
-+		struct {
-+			uint32_t GRAPHICS_DEGAMMA_SRGB :1;
-+			uint32_t OVERLAY_DEGAMMA_SRGB :1;
-+			uint32_t GAMMA_RAMP_ARRAY :1;
-+			uint32_t APPLY_DEGAMMA :1;
-+			uint32_t RESERVED :28;
-+		} bits;
-+		uint32_t value;
-+	} features;
-+
-+	union {
-+		struct regamma_ramp regamma_ramp;
-+		struct gamma_coeff gamma_coeff;
-+	};
-+};
-+
-+union gamma_flag {
-+	struct {
-+		uint32_t config_is_changed :1;
-+		uint32_t both_pipe_req :1;
-+		uint32_t regamma_update :1;
-+		uint32_t gamma_update :1;
-+		uint32_t reserved :28;
-+	} bits;
-+	uint32_t u_all;
-+};
-+
-+enum graphics_regamma_adjust {
-+	GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */
-+	GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */
-+};
-+
-+enum graphics_gamma_lut {
-+	GRAPHICS_GAMMA_LUT_LEGACY = 0, /* use only legacy LUT */
-+	GRAPHICS_GAMMA_LUT_REGAMMA, /* use only regamma LUT */
-+	GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA /* use legacy & regamma LUT's */
-+};
-+
-+enum graphics_degamma_adjust {
-+	GRAPHICS_DEGAMMA_ADJUST_BYPASS = 0, GRAPHICS_DEGAMMA_ADJUST_HW, /*without adjustments */
-+	GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */
-+};
-+
-+struct gamma_parameters {
-+	union gamma_flag flag;
-+	enum pixel_format surface_pixel_format; /*OS surface pixel format*/
-+	struct regamma_lut regamma;
-+
-+	enum graphics_regamma_adjust regamma_adjust_type;
-+	enum graphics_degamma_adjust degamma_adjust_type;
-+
-+	enum graphics_gamma_lut selected_gamma_lut;
-+
-+	bool disable_adjustments;
-+
-+	/* here we grow with parameters if necessary */
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 0bbf9b5..1dedf7c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -27,6 +27,15 @@
- #define __DC_HW_SEQUENCER_H__
- #include "core_types.h"
- 
-+struct gamma_parameters;
-+
-+enum pipe_gating_control {
-+	PIPE_GATING_CONTROL_DISABLE = 0,
-+	PIPE_GATING_CONTROL_ENABLE,
-+	PIPE_GATING_CONTROL_INIT
-+};
-+
-+
- struct hw_sequencer_funcs {
- 
- 	enum dc_status (*apply_ctx_to_hw)(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index e7151cd..8e7cc31 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -32,6 +32,7 @@
- #include "include/video_csc_types.h"
- #include "include/hw_sequencer_types.h"
- 
-+struct dev_c_lut;
- 
- #define MAXTRIX_COEFFICIENTS_NUMBER 12
- #define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 2647f84..4d653ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -57,7 +57,7 @@ struct mem_input_funcs {
- 	bool (*mem_input_program_surface_config)(
- 		struct mem_input *mem_input,
- 		enum surface_pixel_format format,
--		union plane_tiling_info *tiling_info,
-+		union dc_tiling_info *tiling_info,
- 		union plane_size *plane_size,
- 		enum dc_rotation_angle rotation);
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 543848a..f2171de 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -26,14 +26,74 @@
- #ifndef __DAL_OPP_H__
- #define __DAL_OPP_H__
- 
--#include "dc_temp.h"
-+#include "dc_types.h"
- #include "grph_object_id.h"
- #include "grph_csc_types.h"
-+#include "dc_services_types.h"
- 
- struct fixed31_32;
-+struct gamma_parameters;
- 
- /* TODO: Need cleanup */
- 
-+enum clamping_range {
-+	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
-+	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
-+	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
-+	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
-+	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
-+	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
-+};
-+
-+struct clamping_and_pixel_encoding_params {
-+	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
-+	enum clamping_range clamping_level; /* Clamping identifier */
-+	enum dc_color_depth c_depth; /* Deep color use. */
-+};
-+
-+struct bit_depth_reduction_params {
-+	struct {
-+		/* truncate/round */
-+		/* trunc/round enabled*/
-+		uint32_t TRUNCATE_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
-+		uint32_t TRUNCATE_DEPTH:2;
-+		/* truncate or round*/
-+		uint32_t TRUNCATE_MODE:1;
-+
-+		/* spatial dither */
-+		/* Spatial Bit Depth Reduction enabled*/
-+		uint32_t SPATIAL_DITHER_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
-+		uint32_t SPATIAL_DITHER_DEPTH:2;
-+		/* 0-3 to select patterns*/
-+		uint32_t SPATIAL_DITHER_MODE:2;
-+		/* Enable RGB random dithering*/
-+		uint32_t RGB_RANDOM:1;
-+		/* Enable Frame random dithering*/
-+		uint32_t FRAME_RANDOM:1;
-+		/* Enable HighPass random dithering*/
-+		uint32_t HIGHPASS_RANDOM:1;
-+
-+		/* temporal dither*/
-+		 /* frame modulation enabled*/
-+		uint32_t FRAME_MODULATION_ENABLED:1;
-+		/* same as for trunc/spatial*/
-+		uint32_t FRAME_MODULATION_DEPTH:2;
-+		/* 2/4 gray levels*/
-+		uint32_t TEMPORAL_LEVEL:1;
-+		uint32_t FRC25:2;
-+		uint32_t FRC50:2;
-+		uint32_t FRC75:2;
-+	} flags;
-+
-+	uint32_t r_seed_value;
-+	uint32_t b_seed_value;
-+	uint32_t g_seed_value;
-+};
-+
-+
-+
- enum wide_gamut_regamma_mode {
- 	/*  0x0  - BITS2:0 Bypass */
- 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index d453aac..2280357 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -31,6 +31,8 @@
- #include "calcs/scaler_filter.h"
- #include "grph_object_id.h"
- 
-+struct bit_depth_reduction_params;
-+
- enum scaling_type {
- 	SCALING_TYPE_NO_SCALING = 0,
- 	SCALING_TYPE_UPSCALING,
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-index 5fca957..1a26eea 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -26,6 +26,8 @@
- #ifndef __DAL_FIXED32_32_H__
- #define __DAL_FIXED32_32_H__
- 
-+#include "dc_services_types.h"
-+
- struct fixed32_32 {
- 	uint64_t value;
- };
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-index dc294b6..6f9cd3f 100644
---- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -27,6 +27,7 @@
- #define __DAL_VIDEO_GAMMA_TYPES_H__
- 
- #include "set_mode_types.h"
-+#include "gamma_types.h"
- 
- enum overlay_gamma_adjust {
- 	OVERLAY_GAMMA_ADJUST_BYPASS,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0740-drm-amd-dal-Fixed-page-flip-handle-issue.patch b/common/recipes-kernel/linux/files/0740-drm-amd-dal-Fixed-page-flip-handle-issue.patch
deleted file mode 100644
index 87677ca2..00000000
--- a/common/recipes-kernel/linux/files/0740-drm-amd-dal-Fixed-page-flip-handle-issue.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 873cc693318ef0ed872f083a59e8e1a46b340b18 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Mon, 25 Jan 2016 10:58:47 -0500
-Subject: [PATCH 0740/1110] drm/amd/dal: Fixed page flip handle issue.
-
-Change atomic commit processing for page flip and
-surface creationi.
-
-surface are created under two scenarios.
-1. This commit is not a page flip.
-2. This commit is a page flip, and targets are created.
-
-After surface creation and vblank irq enabled, if page
-flip needed, just do page flip.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 40 ++++++++++++++++------
- 1 file changed, 30 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 70d5dae..6792aea 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2235,24 +2235,26 @@ int amdgpu_dm_atomic_commit(
- 		struct drm_framebuffer *fb = plane_state->fb;
- 		struct drm_connector *connector;
- 		struct dm_connector_state *dm_state = NULL;
-+		enum dm_commit_action action;
- 
- 		if (!fb || !crtc || !crtc->state->planes_changed ||
- 			!crtc->state->active)
- 			continue;
- 
--		if (page_flip_needed(
--			plane_state,
--			old_plane_state))
--			amdgpu_crtc_page_flip(
--				crtc,
--				fb,
--				crtc->state->event,
--				0);
--		else {
-+		action = get_dm_commit_action(crtc->state);
-+
-+		/* Surfaces are created under two scenarios:
-+		 * 1. This commit is not a page flip.
-+		 * 2. This commit is a page flip, and targets are created.
-+		 */
-+		if (!page_flip_needed(plane_state, old_plane_state) ||
-+				action == DM_COMMIT_ACTION_DPMS_ON ||
-+				action == DM_COMMIT_ACTION_SET) {
- 			list_for_each_entry(connector,
- 				&dev->mode_config.connector_list, head)	{
- 				if (connector->state->crtc == crtc) {
--					dm_state = to_dm_connector_state(connector->state);
-+					dm_state = to_dm_connector_state(
-+						connector->state);
- 					break;
- 				}
- 			}
-@@ -2292,6 +2294,24 @@ int amdgpu_dm_atomic_commit(
- 
- 	}
- 
-+	/* Page flip if needed */
-+	for_each_plane_in_state(state, plane, old_plane_state, i) {
-+		struct drm_plane_state *plane_state = plane->state;
-+		struct drm_crtc *crtc = plane_state->crtc;
-+		struct drm_framebuffer *fb = plane_state->fb;
-+
-+		if (!fb || !crtc || !crtc->state->planes_changed ||
-+			!crtc->state->active)
-+			continue;
-+
-+		if (page_flip_needed(plane_state, old_plane_state))
-+			amdgpu_crtc_page_flip(
-+				crtc,
-+				fb,
-+				crtc->state->event,
-+				0);
-+	}
-+
- 	drm_atomic_helper_wait_for_vblanks(dev, state);
- 
- 	/* In this state all old framebuffers would be unpinned */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0741-drm-amd-dal-refactor-hw_sequencer.patch b/common/recipes-kernel/linux/files/0741-drm-amd-dal-refactor-hw_sequencer.patch
deleted file mode 100644
index b9c8fa93..00000000
--- a/common/recipes-kernel/linux/files/0741-drm-amd-dal-refactor-hw_sequencer.patch
+++ /dev/null
@@ -1,3195 +0,0 @@
-From 8aa635d8c08f9736593d3e8896094481c6da174a Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 27 Jan 2016 16:03:57 -0500
-Subject: [PATCH 0741/1110] drm/amd/dal: refactor hw_sequencer
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  65 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  12 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  28 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  16 +-
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    | 326 ++++++++++-
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.h    |   2 +-
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 445 ++++++++-------
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    |   1 -
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 630 +++++++++------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 452 +++++++--------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.h    |  15 -
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |   2 -
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  21 +
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      | 110 ++--
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |   4 +
- drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h  | 155 +++++
- .../drm/amd/dal/dc/inc/timing_generator_types.h    | 155 -----
- 19 files changed, 1333 insertions(+), 1110 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 1a17090..b3c919c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -38,8 +38,9 @@
- 
- #include "bandwidth_calcs.h"
- #include "include/irq_service_interface.h"
--#include "inc/transform.h"
--#include "../virtual/virtual_link_encoder.h"
-+#include "transform.h"
-+#include "timing_generator.h"
-+#include "virtual/virtual_link_encoder.h"
- 
- #include "link_hwss.h"
- #include "link_encoder.h"
-@@ -63,13 +64,11 @@ static void destroy_links(struct dc *dc)
- 	uint32_t i;
- 
- 	for (i = 0; i < dc->link_count; i++) {
--
- 		if (NULL != dc->links[i])
- 			link_destroy(&dc->links[i]);
- 	}
- }
- 
--
- static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- {
- 	int i;
-@@ -83,8 +82,10 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 	connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
- 	if (connectors_num > ENUM_ID_COUNT) {
--		dal_error("DC: Number of connectors %d exceeds maximum of %d!\n",
--				connectors_num, ENUM_ID_COUNT);
-+		dal_error(
-+			"DC: Number of connectors %d exceeds maximum of %d!\n",
-+			connectors_num,
-+			ENUM_ID_COUNT);
- 		return false;
- 	}
- 
-@@ -93,8 +94,11 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 		return false;
- 	}
- 
--	dal_output_to_console("DC: %s: connectors_num: physical:%d, virtual:%d\n",
--			__func__, connectors_num, init_params->num_virtual_links);
-+	dal_output_to_console(
-+		"DC: %s: connectors_num: physical:%d, virtual:%d\n",
-+		__func__,
-+		connectors_num,
-+		init_params->num_virtual_links);
- 
- 	for (i = 0; i < connectors_num; i++) {
- 		struct link_init_data link_init_params = {0};
-@@ -105,22 +109,22 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 		link_init_params.connector_index = i;
- 		link_init_params.link_index = dc->link_count;
- 		link_init_params.dc = dc;
--		link =  link_create(&link_init_params);
-+		link = link_create(&link_init_params);
- 
- 		if (link) {
- 			dc->links[dc->link_count] = link;
- 			link->dc = dc;
- 			++dc->link_count;
--		}
--		else {
-+		} else {
- 			dal_error("DC: failed to create link!\n");
- 		}
- 	}
- 
- 	for (i = 0; i < init_params->num_virtual_links; i++) {
--		struct core_link *link =
--			dc_service_alloc(dc->ctx, sizeof(*link));
--		struct encoder_init_data enc_init = { 0 };
-+		struct core_link *link = dc_service_alloc(
-+			dc->ctx,
-+			sizeof(*link));
-+		struct encoder_init_data enc_init = {0};
- 
- 		if (link == NULL) {
- 			BREAK_TO_DEBUGGER();
-@@ -134,8 +138,9 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 		link->link_id.type = OBJECT_TYPE_CONNECTOR;
- 		link->link_id.id = CONNECTOR_ID_VIRTUAL;
- 		link->link_id.enum_id = ENUM_ID_1;
--		link->link_enc =
--			dc_service_alloc(dc->ctx, sizeof(*link->link_enc));
-+		link->link_enc = dc_service_alloc(
-+			dc->ctx,
-+			sizeof(*link->link_enc));
- 
- 		enc_init.adapter_service = init_params->adapter_srv;
- 		enc_init.ctx = init_params->ctx;
-@@ -159,6 +164,7 @@ failed_alloc:
- 	return false;
- }
- 
-+
- static void init_hw(struct dc *dc)
- {
- 	int i;
-@@ -198,11 +204,11 @@ static void init_hw(struct dc *dc)
- 	for(i = 0; i < dc->res_pool.controller_count; i++) {
- 		struct timing_generator *tg = dc->res_pool.timing_generators[i];
- 
--		dc->hwss.disable_vga(tg);
-+		tg->funcs->disable_vga(tg);
- 
- 		/* Blank controller using driver code instead of
- 		 * command table. */
--		dc->hwss.disable_memory_requests(tg);
-+		tg->funcs->set_blank(tg, true);
- 	}
- 
- 	for(i = 0; i < dc->res_pool.audio_count; i++) {
-@@ -359,18 +365,12 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 	if (!dc_construct_hw_sequencer(dc_init_data.adapter_srv, dc))
- 		goto hwss_fail;
- 
--
--	/* TODO: create all the sub-objects of DC. */
--	if (false == create_links(dc, &dc_init_data))
--		goto create_links_fail;
--
--	if (!dc->hwss.construct_resource_pool(
--			dc_init_data.adapter_srv,
--			dc_init_data.num_virtual_links,
--			dc,
--			&dc->res_pool))
-+	if (!dc_construct_resource_pool(
-+		dc_init_data.adapter_srv, dc, dc_init_data.num_virtual_links))
- 		goto construct_resource_fail;
- 
-+	if (!create_links(dc, &dc_init_data))
-+		goto create_links_fail;
- 
- 	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
- 
-@@ -393,7 +393,7 @@ ctx_fail:
- static void destruct(struct dc *dc)
- {
- 	destroy_links(dc);
--	dc->hwss.destruct_resource_pool(&dc->res_pool);
-+	dc->res_pool.funcs->destruct(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
- 	dc_service_free(dc->ctx, dc->ctx);
- }
-@@ -449,7 +449,8 @@ bool dc_validate_resources(
- 	if(context == NULL)
- 		goto context_alloc_fail;
- 
--	result = dc->hwss.validate_with_context(dc, set, set_count, context);
-+	result = dc->res_pool.funcs->validate_with_context(
-+						dc, set, set_count, context);
- 
- 	dc_service_free(dc->ctx, context);
- context_alloc_fail:
-@@ -559,7 +560,7 @@ bool dc_commit_targets(
- 	if (context == NULL)
- 		goto context_alloc_fail;
- 
--	result = dc->hwss.validate_with_context(dc, set, target_count, context);
-+	result = dc->res_pool.funcs->validate_with_context(dc, set, target_count, context);
- 	if (result != DC_OK){
- 		BREAK_TO_DEBUGGER();
- 		goto fail;
-@@ -679,6 +680,7 @@ void dc_flip_surface_addrs(struct dc* dc,
- 		surface->public.flip_immediate = flip_addrs[i].flip_immediate;
- 
- 		dc->hwss.update_plane_address(
-+			dc,
- 			surface,
- 			DC_TARGET_TO_CORE(surface->status.dc_target));
- 	}
-@@ -789,7 +791,6 @@ void dc_resume(const struct dc *dc)
- 		core_link_resume(dc->links[i]);
- }
- 
--
- bool dc_read_dpcd(
- 		struct dc *dc,
- 		uint32_t link_index,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index a2879bb..c81f4a2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -67,7 +67,7 @@ static void destruct(struct core_link *link)
- 		dal_ddc_service_destroy(&link->ddc);
- 
- 	if(link->link_enc)
--		link->ctx->dc->hwss.encoder_destroy(&link->link_enc);
-+		link->ctx->dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
- }
- 
- /*
-@@ -988,7 +988,8 @@ static bool construct(
- 	enc_init_data.hpd_source = get_hpd_line(link, as);
- 	enc_init_data.transmitter =
- 			translate_encoder_to_transmitter(enc_init_data.encoder);
--	link->link_enc = dc_ctx->dc->hwss.encoder_create(&enc_init_data);
-+	link->link_enc = dc_ctx->dc->res_pool.funcs->link_enc_create(
-+								&enc_init_data);
- 
- 	if( link->link_enc == NULL) {
- 		DC_ERROR("Failed to create link encoder!\n");
-@@ -1449,7 +1450,6 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
- 	struct dp_mst_stream_allocation_table proposed_table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp;
--	struct dc *dc = stream->ctx->dc;
- 	struct fixed31_32 pbn;
- 	struct fixed31_32 pbn_per_slot;
- 	uint8_t i;
-@@ -1524,7 +1524,8 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
- 
- 
--	dc->hwss.set_mst_bandwidth(
-+
-+	stream_encoder->funcs->set_mst_bandwidth(
- 		stream_encoder,
- 		avg_time_slots_per_mtp);
- 
-@@ -1539,7 +1540,6 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	struct stream_encoder *stream_encoder = stream->stream_enc;
- 	struct dp_mst_stream_allocation_table proposed_table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
--	struct dc *dc = stream->ctx->dc;
- 	uint8_t i;
- 	bool mst_mode = (link->public.type == dc_connection_mst_branch);
- 
-@@ -1551,7 +1551,7 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	 */
- 
- 	/* slot X.Y */
--	dc->hwss.set_mst_bandwidth(
-+	stream_encoder->funcs->set_mst_bandwidth(
- 		stream_encoder,
- 		avg_time_slots_per_mtp);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 52307cb..fcda0cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -31,6 +31,33 @@
- #include "opp.h"
- #include "transform.h"
- 
-+#include "dce100/dce100_resource.h"
-+#include "dce110/dce110_resource.h"
-+
-+bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
-+				struct dc *dc,
-+				uint8_t num_virtual_links)
-+{
-+	enum dce_version dce_ver = dal_adapter_service_get_dce_version(adapter_serv);
-+
-+	switch (dce_ver) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case DCE_VERSION_10_0:
-+		return dce100_construct_resource_pool(
-+			adapter_serv, num_virtual_links, dc, &dc->res_pool);
-+#endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+		return dce110_construct_resource_pool(
-+			adapter_serv, num_virtual_links, dc, &dc->res_pool);
-+#endif
-+	default:
-+		break;
-+	}
-+
-+	return false;
-+}
-+
- void unreference_clock_source(
- 		struct resource_context *res_ctx,
- 		struct clock_source *clock_source)
-@@ -512,7 +539,6 @@ void pplib_apply_display_requirements(
- 
- 	pp_display_cfg.avail_mclk_switch_time_us =
- 						get_min_vblank_time_us(context);
--	/* TODO: dce11.2*/
- 	pp_display_cfg.avail_mclk_switch_time_in_disp_active_us = 0;
- 
- 	pp_display_cfg.disp_clk_khz = context->bw_results.dispclk_khz;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 8cb05b7..2756e7b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -27,6 +27,7 @@
- #include "hw_sequencer.h"
- #include "resource.h"
- #include "ipp.h"
-+#include "timing_generator.h"
- 
- #define COEFF_RANGE	3
- #define REGAMMA_COEFF_A0	31308
-@@ -280,7 +281,8 @@ bool dc_commit_surfaces_to_target(
- 				new_surfaces[i],
- 				DC_STREAM_TO_CORE(target->public.streams[j]));
- 
--	if (dc->hwss.validate_bandwidth(dc, &dc->current_context) != DC_OK) {
-+	if (dc->res_pool.funcs->validate_bandwidth(dc, &dc->current_context)
-+								!= DC_OK) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
- 	}
-@@ -309,12 +311,10 @@ bool dc_commit_surfaces_to_target(
- 			DC_STREAM_TO_CORE(target->public.streams[0])->ipp,
- 			DC_STREAM_TO_CORE(target->public.streams[0])->opp);
- 
--		dc->hwss.set_plane_config(
--			core_surface,
--			target);
-+		dc->hwss.set_plane_config(dc, core_surface, target);
- 
- 		if (is_valid_address)
--			dc->hwss.update_plane_address(core_surface, target);
-+			dc->hwss.update_plane_address(dc, core_surface, target);
- 	}
- 
- 	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
-@@ -358,7 +358,7 @@ void dc_target_enable_memory_requests(struct dc_target *target)
- 		struct timing_generator *tg =
- 			DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
- 
--		if (!core_target->ctx->dc->hwss.enable_memory_requests(tg)) {
-+		if (!tg->funcs->set_blank(tg, false)) {
- 			dal_error("DC: failed to unblank crtc!\n");
- 			BREAK_TO_DEBUGGER();
- 		}
-@@ -379,7 +379,7 @@ void dc_target_disable_memory_requests(struct dc_target *target)
- 			continue;
- 		}
- 
--		if (false == core_target->ctx->dc->hwss.disable_memory_requests(tg)) {
-+		if (false == tg->funcs->set_blank(tg, true)) {
- 			dal_error("DC: failed to blank crtc!\n");
- 			BREAK_TO_DEBUGGER();
- 		}
-@@ -464,7 +464,7 @@ uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- 	struct timing_generator *tg =
- 		DC_STREAM_TO_CORE(core_target->public.streams[0])->tg;
- 
--	return core_target->ctx->dc->hwss.get_vblank_counter(tg);
-+	return tg->funcs->get_frame_count(tg);
- }
- 
- enum dc_irq_source dc_target_get_irq_src(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index b37df4a..b76c8ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -22,20 +22,332 @@
-  * Authors: AMD
-  *
-  */
--
- #include "dc_services.h"
--
-+#include "dc.h"
-+#include "core_dc.h"
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+#include "dce100_hw_sequencer.h"
- #include "dce110/dce110_hw_sequencer.h"
- 
--#include "resource.h"
--#include "hw_sequencer.h"
--#include "dce100_resource.h"
-+/* include DCE10 register header files */
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+struct dce100_hw_seq_reg_offsets {
-+	uint32_t blnd;
-+	uint32_t crtc;
-+};
-+
-+enum pipe_lock_control {
-+	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
-+	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
-+	PIPE_LOCK_CONTROL_SCL = 1 << 2,
-+	PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
-+	PIPE_LOCK_CONTROL_MODE = 1 << 4
-+};
-+
-+enum blender_mode {
-+	BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
-+	BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
-+	BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
-+	BLENDER_MODE_STEREO
-+};
-+
-+static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_BLND(reg, id)\
-+	(reg + reg_offsets[id].blnd)
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+/***************************PIPE_CONTROL***********************************/
-+static void dce100_enable_fe_clock(
-+	struct dc_context *ctx, uint8_t controller_id, bool enable)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	addr = HW_REG_CRTC(mmDCFE_CLOCK_CONTROL, controller_id);
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		enable,
-+		DCFE_CLOCK_CONTROL,
-+		DCFE_CLOCK_ENABLE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static bool dce100_pipe_control_lock(
-+	struct dc_context *ctx,
-+	uint8_t controller_idx,
-+	uint32_t control_mask,
-+	bool lock)
-+{
-+	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
-+	uint32_t value = dal_read_reg(ctx, addr);
-+	bool need_to_wait = false;
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SCL)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_SCL_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_BLND_V_UPDATE_LOCK);
-+		need_to_wait = true;
-+	}
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_V_UPDATE_LOCK_MODE);
-+
-+	dal_write_reg(ctx, addr, value);
-+
-+	if (!lock && need_to_wait) {
-+		uint8_t counter = 0;
-+		const uint8_t counter_limit = 100;
-+		const uint16_t delay_us = 1000;
-+
-+		uint8_t pipe_pending;
-+
-+		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
-+				controller_idx);
-+
-+		while (counter < counter_limit) {
-+			value = dal_read_reg(ctx, addr);
-+
-+			pipe_pending = 0;
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						BLND_BLNDC_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					BLND_BLNDO_UPDATE_PENDING);
-+			}
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDC_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDO_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDC_GRPH_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDO_GRPH_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDC_GRPH_SURF_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDO_GRPH_SURF_UPDATE_PENDING);
-+			}
-+
-+			if (pipe_pending == 0)
-+				break;
-+
-+			counter++;
-+			dc_service_delay_in_microseconds(ctx, delay_us);
-+		}
-+
-+		if (counter == counter_limit) {
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: wait for update exceeded (wait %d us)\n",
-+				__func__,
-+				counter * delay_us);
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: control %d, remain value %x\n",
-+				__func__,
-+				control_mask,
-+				value);
-+		} else {
-+			/* OK. */
-+		}
-+	}
-+
-+	return true;
-+}
-+
-+static void dce100_set_blender_mode(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	uint32_t mode)
-+{
-+	uint32_t value;
-+	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-+	uint32_t blnd_mode;
-+	uint32_t feedthrough = 0;
-+
-+	switch (mode) {
-+	case BLENDER_MODE_OTHER_PIPE:
-+		feedthrough = 0;
-+		blnd_mode = 1;
-+		break;
-+	case BLENDER_MODE_BLENDING:
-+		feedthrough = 0;
-+		blnd_mode = 2;
-+		break;
-+	case BLENDER_MODE_CURRENT_PIPE:
-+	default:
-+		feedthrough = 1;
-+		blnd_mode = 0;
-+		break;
-+	}
-+
-+	value = dal_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		feedthrough,
-+		BLND_CONTROL,
-+		BLND_FEEDTHROUGH_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		blnd_mode,
-+		BLND_CONTROL,
-+		BLND_MODE);
-+
-+	dal_write_reg(ctx, addr, value);
-+}
-+
-+static bool dce100_enable_display_power_gating(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0))
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static void enable_hw_base_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+static void disable_sw_manual_control_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+static void enable_sw_manual_control_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool enable)
-+{
-+	if (enable) {
-+		enable_hw_base_light_sleep();
-+		disable_sw_manual_control_light_sleep();
-+	} else {
-+		enable_sw_manual_control_light_sleep();
-+	}
-+}
-+
-+/**************************************************************************/
- 
- bool dce100_hw_sequencer_construct(struct dc *dc)
- {
- 	dce110_hw_sequencer_construct(dc);
--	dc->hwss.construct_resource_pool = dce100_construct_resource_pool;
--	dc->hwss.destruct_resource_pool = dce100_destruct_resource_pool;
-+
-+	/* TODO: dce80 is empty implementation at the moment*/
-+	dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce100_power_up;
-+
-+	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
-+	dc->hwss.enable_fe_clock = dce100_enable_fe_clock;
-+	dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
-+	dc->hwss.set_blender_mode = dce100_set_blender_mode;
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-index d52bfda..0ce637e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-@@ -32,5 +32,5 @@ struct dc;
- 
- bool dce100_hw_sequencer_construct(struct dc *dc);
- 
--#endif /* __DC_HWSS_DCE110_H__ */
-+#endif /* __DC_HWSS_DCE100_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 4027547..0c1757b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -30,6 +30,8 @@
- #include "resource.h"
- #include "include/irq_service_interface.h"
- 
-+#include "../virtual/virtual_stream_encoder.h"
-+#include "dce110/dce110_resource.h"
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_mem_input.h"
-@@ -41,7 +43,6 @@
- 
- #include "dce/dce_10_0_d.h"
- 
--/* TODO remove these defines */
- #ifndef mmDP_DPHY_INTERNAL_CTRL
- 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
- 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-@@ -524,215 +525,6 @@ void dce100_clock_source_destroy(struct clock_source **clk_src)
- 	*clk_src = NULL;
- }
- 
--bool dce100_construct_resource_pool(
--	struct adapter_service *adapter_serv,
--	uint8_t num_virtual_links,
--	struct dc *dc,
--	struct resource_pool *pool)
--{
--	unsigned int i;
--	struct audio_init_data audio_init_data = { 0 };
--	struct dc_context *ctx = dc->ctx;
--
--	pool->adapter_srv = adapter_serv;
--
--	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
--
--	pool->clock_sources[DCE100_CLK_SRC_PLL0] = dce100_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]);
--	pool->clock_sources[DCE100_CLK_SRC_PLL1] = dce100_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]);
--	pool->clock_sources[DCE100_CLK_SRC_EXT] =  dce100_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_EXTERNAL, &dce100_clk_src_reg_offsets[0]);
--	pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
--
--	for (i = 0; i < pool->clk_src_count; i++) {
--		if (pool->clock_sources[i] == NULL) {
--			dal_error("DC: failed to create clock sources!\n");
--			BREAK_TO_DEBUGGER();
--			goto clk_src_create_fail;
--		}
--	}
--
--	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
--	if (pool->display_clock == NULL) {
--		dal_error("DC: failed to create display clock!\n");
--		BREAK_TO_DEBUGGER();
--		goto disp_clk_create_fail;
--	}
--
--	{
--		struct irq_service_init_data init_data;
--
--		init_data.ctx = dc->ctx;
--		pool->irqs = dal_irq_service_create(
--				dal_adapter_service_get_dce_version(
--					dc->res_pool.adapter_srv),
--				&init_data);
--		if (!pool->irqs)
--			goto irqs_create_fail;
--
--	}
--
--	pool->controller_count =
--		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
--			adapter_serv);
--	pool->scaler_filter = dal_scaler_filter_create(ctx);
--	if (pool->scaler_filter == NULL) {
--		BREAK_TO_DEBUGGER();
--		dal_error("DC: failed to create filter!\n");
--		goto filter_create_fail;
--	}
--
--	for (i = 0; i < pool->controller_count; i++) {
--		pool->timing_generators[i] = dce100_timing_generator_create(
--				adapter_serv, ctx, i, &dce100_tg_offsets[i]);
--		if (pool->timing_generators[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create tg!\n");
--			goto controller_create_fail;
--		}
--
--		pool->mis[i] = dce100_mem_input_create(ctx, i,
--				&dce100_mi_reg_offsets[i]);
--		if (pool->mis[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create memory input!\n");
--			goto controller_create_fail;
--		}
--
--		pool->ipps[i] = dce100_ipp_create(ctx, i,
--				&dce100_ipp_reg_offsets[i]);
--		if (pool->ipps[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create input pixel processor!\n");
--			goto controller_create_fail;
--		}
--
--		pool->transforms[i] = dce100_transform_create(
--					ctx, i, &dce100_xfm_offsets[i]);
--		if (pool->transforms[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create transform!\n");
--			goto controller_create_fail;
--		}
--		pool->transforms[i]->funcs->transform_set_scaler_filter(
--				pool->transforms[i],
--				pool->scaler_filter);
--
--		pool->opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]);
--		if (pool->opps[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create output pixel processor!\n");
--			goto controller_create_fail;
--		}
--	}
--
--	audio_init_data.as = adapter_serv;
--	audio_init_data.ctx = ctx;
--	pool->audio_count = 0;
--	for (i = 0; i < pool->controller_count; i++) {
--		struct graphics_object_id obj_id;
--
--		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
--		if (false == dal_graphics_object_id_is_valid(obj_id)) {
--			/* no more valid audio objects */
--			break;
--		}
--
--		audio_init_data.audio_stream_id = obj_id;
--		pool->audios[i] = dal_audio_create(&audio_init_data);
--		if (pool->audios[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create DPPs!\n");
--			goto audio_create_fail;
--		}
--		pool->audio_count++;
--	}
--
--	for (i = 0; i < pool->stream_enc_count; i++) {
--		/* TODO: rework fragile code*/
--		if (pool->stream_engines.u_all & 1 << i) {
--			pool->stream_enc[i] = dce100_stream_encoder_create(
--				i, dc->ctx,
--				dal_adapter_service_get_bios_parser(
--					adapter_serv),
--				&stream_enc_regs[i]);
--			if (pool->stream_enc[i] == NULL) {
--				BREAK_TO_DEBUGGER();
--				dal_error("DC: failed to create stream_encoder!\n");
--				goto stream_enc_create_fail;
--			}
--		}
--	}
--
--	return true;
--
--stream_enc_create_fail:
--	for (i = 0; i < pool->stream_enc_count; i++) {
--		if (pool->stream_enc[i] != NULL)
--			dc_service_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
--	}
--
--audio_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
--		if (pool->audios[i] != NULL)
--			dal_audio_destroy(&pool->audios[i]);
--	}
--
--controller_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
--		if (pool->opps[i] != NULL)
--			dce100_opp_destroy(&pool->opps[i]);
--
--		if (pool->transforms[i] != NULL)
--			dce100_transform_destroy(&pool->transforms[i]);
--
--		if (pool->ipps[i] != NULL)
--			dce110_ipp_destroy(&pool->ipps[i]);
--
--		if (pool->mis[i] != NULL) {
--			dc_service_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
--			pool->mis[i] = NULL;
--		}
--
--		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx,
--				DCE110TG_FROM_TG(pool->timing_generators[i]));
--			pool->timing_generators[i] = NULL;
--		}
--	}
--
--filter_create_fail:
--	dal_irq_service_destroy(&pool->irqs);
--
--irqs_create_fail:
--	dal_display_clock_destroy(&pool->display_clock);
--
--disp_clk_create_fail:
--clk_src_create_fail:
--	for (i = 0; i < pool->clk_src_count; i++) {
--		if (pool->clock_sources[i] != NULL)
--			dce100_clock_source_destroy(&pool->clock_sources[i]);
--	}
--	return false;
--}
--
- void dce100_destruct_resource_pool(struct resource_pool *pool)
- {
- 	unsigned int i;
-@@ -775,6 +567,7 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 		if (pool->audios[i] != NULL)
- 			dal_audio_destroy(&pool->audios[i]);
- 	}
-+
- 	if (pool->display_clock != NULL)
- 		dal_display_clock_destroy(&pool->display_clock);
- 
-@@ -1273,3 +1066,235 @@ enum dc_status dce100_validate_with_context(
- 
- 	return result;
- }
-+
-+static struct resource_funcs dce100_res_pool_funcs = {
-+	.destruct = dce100_destruct_resource_pool,
-+	.link_enc_create = dce100_link_encoder_create,
-+	.link_enc_destroy = dce110_link_encoder_destroy,
-+	.validate_with_context = dce100_validate_with_context,
-+	.validate_bandwidth = dce100_validate_bandwidth
-+};
-+
-+bool dce100_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct audio_init_data audio_init_data = { 0 };
-+	struct dc_context *ctx = dc->ctx;
-+
-+	pool->adapter_srv = adapter_serv;
-+	pool->funcs = &dce100_res_pool_funcs;
-+
-+	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
-+
-+	pool->clock_sources[DCE100_CLK_SRC_PLL0] = dce100_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]);
-+	pool->clock_sources[DCE100_CLK_SRC_PLL1] = dce100_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]);
-+	pool->clock_sources[DCE100_CLK_SRC_EXT] =  dce100_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_EXTERNAL, &dce100_clk_src_reg_offsets[0]);
-+	pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] == NULL) {
-+			dal_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
-+	if (pool->display_clock == NULL) {
-+		dal_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+
-+		init_data.ctx = dc->ctx;
-+		pool->irqs = dal_irq_service_create(
-+				dal_adapter_service_get_dce_version(
-+					dc->res_pool.adapter_srv),
-+				&init_data);
-+		if (!pool->irqs)
-+			goto irqs_create_fail;
-+
-+	}
-+
-+	pool->controller_count =
-+		dal_adapter_service_get_func_controllers_num(adapter_serv);
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
-+			adapter_serv);
-+	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+	if (pool->scaler_filter == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dal_error("DC: failed to create filter!\n");
-+		goto filter_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		pool->timing_generators[i] = dce100_timing_generator_create(
-+				adapter_serv, ctx, i, &dce100_tg_offsets[i]);
-+		if (pool->timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->mis[i] = dce100_mem_input_create(ctx, i,
-+				&dce100_mi_reg_offsets[i]);
-+		if (pool->mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->ipps[i] = dce100_ipp_create(ctx, i,
-+				&dce100_ipp_reg_offsets[i]);
-+		if (pool->ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->transforms[i] = dce100_transform_create(
-+					ctx, i, &dce100_xfm_offsets[i]);
-+		if (pool->transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create transform!\n");
-+			goto controller_create_fail;
-+		}
-+		pool->transforms[i]->funcs->transform_set_scaler_filter(
-+				pool->transforms[i],
-+				pool->scaler_filter);
-+
-+		pool->opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]);
-+		if (pool->opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+	}
-+
-+	audio_init_data.as = adapter_serv;
-+	audio_init_data.ctx = ctx;
-+	pool->audio_count = 0;
-+	for (i = 0; i < pool->controller_count; i++) {
-+		struct graphics_object_id obj_id;
-+
-+		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		if (false == dal_graphics_object_id_is_valid(obj_id)) {
-+			/* no more valid audio objects */
-+			break;
-+		}
-+
-+		audio_init_data.audio_stream_id = obj_id;
-+		pool->audios[i] = dal_audio_create(&audio_init_data);
-+		if (pool->audios[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create DPPs!\n");
-+			goto audio_create_fail;
-+		}
-+		pool->audio_count++;
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		/* TODO: rework fragile code*/
-+		if (pool->stream_engines.u_all & 1 << i) {
-+			pool->stream_enc[i] = dce100_stream_encoder_create(
-+				i, dc->ctx,
-+				dal_adapter_service_get_bios_parser(
-+					adapter_serv),
-+				&stream_enc_regs[i]);
-+			if (pool->stream_enc[i] == NULL) {
-+				BREAK_TO_DEBUGGER();
-+				dal_error("DC: failed to create stream_encoder!\n");
-+				goto stream_enc_create_fail;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < num_virtual_links; i++) {
-+		pool->stream_enc[pool->stream_enc_count] =
-+			virtual_stream_encoder_create(
-+				dc->ctx, dal_adapter_service_get_bios_parser(
-+								adapter_serv));
-+		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create stream_encoder!\n");
-+			goto stream_enc_create_fail;
-+		}
-+		pool->stream_enc_count++;
-+	}
-+
-+	return true;
-+
-+stream_enc_create_fail:
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dc_service_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+audio_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+
-+controller_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce100_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce100_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce110_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dc_service_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL)	{
-+			dc_service_free(pool->timing_generators[i]->ctx,
-+				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+filter_create_fail:
-+	dal_irq_service_destroy(&pool->irqs);
-+
-+irqs_create_fail:
-+	dal_display_clock_destroy(&pool->display_clock);
-+
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dce100_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+
-+	return false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index b096444..c5a081a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -820,7 +820,6 @@ static bool dce110_clock_source_power_down(
- 	return bp_result == BP_RESULT_OK;
- }
- 
--
- /*****************************************/
- /* Constructor                           */
- /*****************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 046a9a5..9158955 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -30,18 +30,18 @@
- #include "resource.h"
- #include "hw_sequencer.h"
- #include "dc_helpers.h"
--#include "gamma_types.h"
-+#include "dce110_hw_sequencer.h"
- 
--#include "dce110/dce110_resource.h"
--#include "dce110/dce110_timing_generator.h"
--#include "dce110/dce110_mem_input.h"
--#include "dce110/dce110_opp.h"
- #include "gpu/dce110/dc_clock_gating_dce110.h"
-+
-+#include "timing_generator.h"
-+#include "mem_input.h"
-+#include "opp.h"
- #include "ipp.h"
- #include "transform.h"
- #include "stream_encoder.h"
- #include "link_encoder.h"
--#include "inc/clock_source.h"
-+#include "clock_source.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -51,20 +51,6 @@ struct dce110_hw_seq_reg_offsets {
- 	uint32_t dcfe;
- 	uint32_t blnd;
- 	uint32_t crtc;
--	uint32_t dcp;
--};
--
--enum crtc_stereo_mixer_mode {
--	HW_STEREO_MIXER_MODE_INACTIVE,
--	HW_STEREO_MIXER_MODE_ROW_INTERLEAVE,
--	HW_STEREO_MIXER_MODE_COLUMN_INTERLEAVE,
--	HW_STEREO_MIXER_MODE_PIXEL_INTERLEAVE,
--	HW_STEREO_MIXER_MODE_BLENDER
--};
--
--struct crtc_mixer_params {
--	bool sub_sampling;
--	enum crtc_stereo_mixer_mode mode;
- };
- 
- enum pipe_lock_control {
-@@ -82,41 +68,21 @@ enum blender_mode {
- 	BLENDER_MODE_STEREO
- };
- 
--enum blender_type {
--	BLENDER_TYPE_NON_SINGLE_PIPE = 0,
--	BLENDER_TYPE_SB_SINGLE_PIPE,
--	BLENDER_TYPE_TB_SINGLE_PIPE
--};
--
--enum dc_memory_sleep_state {
--	DC_MEMORY_SLEEP_DISABLE = 0,
--	DC_MEMORY_LIGHT_SLEEP,
--	DC_MEMORY_DEEP_SLEEP,
--	DC_MEMORY_SHUTDOWN
--};
--enum {
--	DCE110_PIPE_UPDATE_PENDING_DELAY = 1000,
--	DCE110_PIPE_UPDATE_PENDING_CHECKCOUNT = 5000
--};
--
- static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- {
- 	.dcfe = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- 	.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
--	.dcp = (mmDCP0_DVMM_PTE_CONTROL - mmDVMM_PTE_CONTROL),
- },
- {
--	.dcfe = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.blnd = (mmBLND1_BLND_CONTROL - mmBLND0_BLND_CONTROL),
--	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
--	.dcp = (mmDCP1_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+	.dcfe = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- },
- {
--	.dcfe = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
--	.blnd = (mmBLND2_BLND_CONTROL - mmBLND0_BLND_CONTROL),
--	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
--	.dcp = (mmDCP2_DVMM_PTE_CONTROL - mmDCP0_DVMM_PTE_CONTROL),
-+	.dcfe = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- }
- };
- 
-@@ -129,192 +95,12 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- #define HW_REG_CRTC(reg, id)\
- 	(reg + reg_offsets[id].crtc)
- 
--#define HW_REG_DCP(reg, id)\
--	(reg + reg_offsets[id].dcp)
--
--
--static void init_pte(struct dc_context *ctx);
- 
- /*******************************************************************************
-  * Private definitions
-  ******************************************************************************/
--
--static void dce110_enable_display_pipe_clock_gating(
--	struct dc_context *ctx,
--	bool clock_gating)
--{
--	/*TODO*/
--}
--
--static bool dce110_enable_display_power_gating(
--	struct dc_context *ctx,
--	uint8_t controller_id,
--	struct dc_bios *dcb,
--	enum pipe_gating_control power_gating)
--{
--	enum bp_result bp_result = BP_RESULT_OK;
--	enum bp_pipe_control_action cntl;
--
--	if (power_gating == PIPE_GATING_CONTROL_INIT)
--		cntl = ASIC_PIPE_INIT;
--	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
--		cntl = ASIC_PIPE_ENABLE;
--	else
--		cntl = ASIC_PIPE_DISABLE;
--
--	if (!(power_gating == PIPE_GATING_CONTROL_INIT &&
--					(controller_id + 1) != CONTROLLER_ID_D0))
--		bp_result = dcb->funcs->enable_disp_power_gating(
--						dcb, controller_id + 1, cntl);
--
--	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
--		init_pte(ctx);
--
--	if (bp_result == BP_RESULT_OK)
--		return true;
--	else
--		return false;
--}
--
--
--static bool set_gamma_ramp(
--	struct input_pixel_processor *ipp,
--	struct output_pixel_processor *opp,
--	const struct gamma_ramp *ramp,
--	const struct gamma_parameters *params)
--{
--	/*Power on LUT memory*/
--	opp->funcs->opp_power_on_regamma_lut(opp, true);
--
--
--	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
--		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
--		/* do legacy DCP for 256 colors if we are requested to do so */
--		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
--			ipp, ramp, params);
--
--		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
--
--		/* set bypass */
--		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
--
--		ipp->funcs->ipp_set_degamma(ipp, params, true);
--
--		opp->funcs->opp_set_regamma(opp, ramp, params, true);
--	} else if (params->selected_gamma_lut ==
--			GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA) {
--		if (!opp->funcs->opp_map_legacy_and_regamma_hw_to_x_user(
--			opp, ramp, params)) {
--			BREAK_TO_DEBUGGER();
--			/* invalid parameters or bug */
--			return false;
--		}
--
--		/* do legacy DCP for 256 colors if we are requested to do so */
--		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
--			ipp, ramp, params);
--
--		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
--
--		/* set bypass */
--		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
--	} else {
--		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, false);
--
--		ipp->funcs->ipp_program_prescale(ipp, params->surface_pixel_format);
--
--		/* Do degamma step : remove the given gamma value from FB.
--		 * For FP16 or no degamma do by pass */
--		ipp->funcs->ipp_set_degamma(ipp, params, false);
--
--		opp->funcs->opp_set_regamma(opp, ramp, params, false);
--	}
--
--	/*re-enable low power mode for LUT memory*/
--	opp->funcs->opp_power_on_regamma_lut(opp, false);
--
--	return true;
--}
--
--static enum dc_status bios_parser_crtc_source_select(
--		struct core_stream *stream)
--{
--	struct dc_bios *dcb;
--	/* call VBIOS table to set CRTC source for the HW
--	 * encoder block
--	 * note: video bios clears all FMT setting here. */
--	struct bp_crtc_source_select crtc_source_select = {0};
--	const struct core_sink *sink = stream->sink;
--
--	crtc_source_select.engine_id = stream->stream_enc->id;
--	crtc_source_select.controller_id = stream->controller_idx + 1;
--	/*TODO: Need to un-hardcode color depth, dp_audio and account for
--	 * the case where signal and sink signal is different (translator
--	 * encoder)*/
--	crtc_source_select.signal = sink->public.sink_signal;
--	crtc_source_select.enable_dp_audio = false;
--	crtc_source_select.sink_signal = sink->public.sink_signal;
--	crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
--
--	dcb = dal_adapter_service_get_bios_parser(sink->link->adapter_srv);
--
--	if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
--		dcb,
--		&crtc_source_select)) {
--		return DC_ERROR_UNEXPECTED;
--	}
--
--	return DC_OK;
--}
--
--static enum color_space surface_color_to_color_space(
--	struct plane_colorimetry *colorimetry)
--{
--	enum color_space color_space = COLOR_SPACE_UNKNOWN;
--
--	switch (colorimetry->color_space) {
--	case SURFACE_COLOR_SPACE_SRGB:
--	case SURFACE_COLOR_SPACE_XRRGB:
--		if (colorimetry->limited_range)
--			color_space = COLOR_SPACE_SRGB_LIMITED_RANGE;
--		else
--			color_space = COLOR_SPACE_SRGB_FULL_RANGE;
--		break;
--	case SURFACE_COLOR_SPACE_BT601:
--	case SURFACE_COLOR_SPACE_XVYCC_BT601:
--		color_space = COLOR_SPACE_YCBCR601;
--		break;
--	case SURFACE_COLOR_SPACE_BT709:
--	case SURFACE_COLOR_SPACE_XVYCC_BT709:
--		color_space = COLOR_SPACE_YCBCR709;
--		break;
--	}
--
--	return color_space;
--}
--
--/*******************************FMT**************************************/
--static void program_fmt(
--		struct output_pixel_processor *opp,
--		struct bit_depth_reduction_params *fmt_bit_depth,
--		struct clamping_and_pixel_encoding_params *clamping)
--{
--	/* dithering is affected by <CrtcSourceSelect>, hence should be
--	 * programmed afterwards */
--
--	opp->funcs->opp_program_bit_depth_reduction(
--		opp,
--		fmt_bit_depth);
--
--	opp->funcs->opp_program_clamping_and_pixel_encoding(
--		opp,
--		clamping);
--
--	return;
--}
--
- /***************************PIPE_CONTROL***********************************/
--static void enable_fe_clock(
-+static void dce110_enable_fe_clock(
- 	struct dc_context *ctx, uint8_t controller_id, bool enable)
- {
- 	uint32_t value = 0;
-@@ -333,21 +119,8 @@ static void enable_fe_clock(
- 
- 	dal_write_reg(ctx, addr, value);
- }
--/*
--static void enable_stereo_mixer(
--	struct dc_context *ctx,
--	const struct crtc_mixer_params *params)
--{
--	TODO
--}
--*/
--static void disable_stereo_mixer(
--	struct dc_context *ctx)
--{
--	/*TODO*/
--}
- 
--static void init_pte(struct dc_context *ctx)
-+static void dce110_init_pte(struct dc_context *ctx)
- {
- 	uint32_t addr;
- 	uint32_t value = 0;
-@@ -414,21 +187,7 @@ static void init_pte(struct dc_context *ctx)
- 	}
- }
- 
--/**
-- *****************************************************************************
-- *  Function: enable_disp_power_gating
-- *
-- *  @brief
-- *     enable or disable power gating
-- *
-- *  @param [in] enum pipe_gating_control power_gating true - power down,
-- *  false - power up
-- *****************************************************************************
-- */
--
--
- /* this is a workaround for hw bug - it is a trigger on r/w */
--
- static void trigger_write_crtc_h_blank_start_end(
- 	struct dc_context *ctx,
- 	uint8_t controller_id)
-@@ -441,7 +200,7 @@ static void trigger_write_crtc_h_blank_start_end(
- 	dal_write_reg(ctx, addr, value);
- }
- 
--static bool pipe_control_lock(
-+static bool dce110_pipe_control_lock(
- 	struct dc_context *ctx,
- 	uint8_t controller_idx,
- 	uint32_t control_mask,
-@@ -586,10 +345,10 @@ static bool pipe_control_lock(
- 	return true;
- }
- 
--static void set_blender_mode(
-+static void dce110_set_blender_mode(
- 	struct dc_context *ctx,
- 	uint8_t controller_id,
--	enum blender_mode mode)
-+	uint32_t mode)
- {
- 	uint32_t value;
- 	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-@@ -628,7 +387,209 @@ static void set_blender_mode(
- 
- 	dal_write_reg(ctx, addr, value);
- }
-+
-+static void dce110_crtc_switch_to_clk_src(
-+				struct clock_source *clk_src, uint8_t crtc_inst)
-+{
-+	uint32_t pixel_rate_cntl_value;
-+	uint32_t addr;
-+
-+	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
-+			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-+
-+	pixel_rate_cntl_value = dal_read_reg(clk_src->ctx, addr);
-+
-+	if (clk_src->id == CLOCK_SOURCE_ID_EXTERNAL)
-+		set_reg_field_value(pixel_rate_cntl_value, 1,
-+			CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
-+	else {
-+		set_reg_field_value(pixel_rate_cntl_value,
-+				0,
-+				CRTC0_PIXEL_RATE_CNTL,
-+				DP_DTO0_ENABLE);
-+
-+		set_reg_field_value(pixel_rate_cntl_value,
-+				clk_src->id - 1,
-+				CRTC0_PIXEL_RATE_CNTL,
-+				CRTC0_PIXEL_RATE_SOURCE);
-+	}
-+	dal_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-+}
- /**************************************************************************/
-+
-+static void enable_display_pipe_clock_gating(
-+	struct dc_context *ctx,
-+	bool clock_gating)
-+{
-+	/*TODO*/
-+}
-+
-+static bool dce110_enable_display_power_gating(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0))
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-+		dce110_init_pte(ctx);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+
-+static bool set_gamma_ramp(
-+	struct input_pixel_processor *ipp,
-+	struct output_pixel_processor *opp,
-+	const struct gamma_ramp *ramp,
-+	const struct gamma_parameters *params)
-+{
-+	/*Power on LUT memory*/
-+	opp->funcs->opp_power_on_regamma_lut(opp, true);
-+
-+
-+	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
-+		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
-+		/* do legacy DCP for 256 colors if we are requested to do so */
-+		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
-+			ipp, ramp, params);
-+
-+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
-+
-+		/* set bypass */
-+		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+
-+		ipp->funcs->ipp_set_degamma(ipp, params, true);
-+
-+		opp->funcs->opp_set_regamma(opp, ramp, params, true);
-+	} else if (params->selected_gamma_lut ==
-+			GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA) {
-+		if (!opp->funcs->opp_map_legacy_and_regamma_hw_to_x_user(
-+			opp, ramp, params)) {
-+			BREAK_TO_DEBUGGER();
-+			/* invalid parameters or bug */
-+			return false;
-+		}
-+
-+		/* do legacy DCP for 256 colors if we are requested to do so */
-+		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
-+			ipp, ramp, params);
-+
-+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
-+
-+		/* set bypass */
-+		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+	} else {
-+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, false);
-+
-+		ipp->funcs->ipp_program_prescale(ipp, params->surface_pixel_format);
-+
-+		/* Do degamma step : remove the given gamma value from FB.
-+		 * For FP16 or no degamma do by pass */
-+		ipp->funcs->ipp_set_degamma(ipp, params, false);
-+
-+		opp->funcs->opp_set_regamma(opp, ramp, params, false);
-+	}
-+
-+	/*re-enable low power mode for LUT memory*/
-+	opp->funcs->opp_power_on_regamma_lut(opp, false);
-+
-+	return true;
-+}
-+
-+static enum dc_status bios_parser_crtc_source_select(
-+		struct core_stream *stream)
-+{
-+	struct dc_bios *dcb;
-+	/* call VBIOS table to set CRTC source for the HW
-+	 * encoder block
-+	 * note: video bios clears all FMT setting here. */
-+	struct bp_crtc_source_select crtc_source_select = {0};
-+	const struct core_sink *sink = stream->sink;
-+
-+	crtc_source_select.engine_id = stream->stream_enc->id;
-+	crtc_source_select.controller_id = stream->controller_idx + 1;
-+	/*TODO: Need to un-hardcode color depth, dp_audio and account for
-+	 * the case where signal and sink signal is different (translator
-+	 * encoder)*/
-+	crtc_source_select.signal = sink->public.sink_signal;
-+	crtc_source_select.enable_dp_audio = false;
-+	crtc_source_select.sink_signal = sink->public.sink_signal;
-+	crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
-+
-+	dcb = dal_adapter_service_get_bios_parser(sink->link->adapter_srv);
-+
-+	if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
-+		dcb,
-+		&crtc_source_select)) {
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	return DC_OK;
-+}
-+
-+static enum color_space surface_color_to_color_space(
-+	struct plane_colorimetry *colorimetry)
-+{
-+	enum color_space color_space = COLOR_SPACE_UNKNOWN;
-+
-+	switch (colorimetry->color_space) {
-+	case SURFACE_COLOR_SPACE_SRGB:
-+	case SURFACE_COLOR_SPACE_XRRGB:
-+		if (colorimetry->limited_range)
-+			color_space = COLOR_SPACE_SRGB_LIMITED_RANGE;
-+		else
-+			color_space = COLOR_SPACE_SRGB_FULL_RANGE;
-+		break;
-+	case SURFACE_COLOR_SPACE_BT601:
-+	case SURFACE_COLOR_SPACE_XVYCC_BT601:
-+		color_space = COLOR_SPACE_YCBCR601;
-+		break;
-+	case SURFACE_COLOR_SPACE_BT709:
-+	case SURFACE_COLOR_SPACE_XVYCC_BT709:
-+		color_space = COLOR_SPACE_YCBCR709;
-+		break;
-+	}
-+
-+	return color_space;
-+}
-+
-+/*******************************FMT**************************************/
-+static void program_fmt(
-+		struct output_pixel_processor *opp,
-+		struct bit_depth_reduction_params *fmt_bit_depth,
-+		struct clamping_and_pixel_encoding_params *clamping)
-+{
-+	/* dithering is affected by <CrtcSourceSelect>, hence should be
-+	 * programmed afterwards */
-+
-+	opp->funcs->opp_program_bit_depth_reduction(
-+		opp,
-+		fmt_bit_depth);
-+
-+	opp->funcs->opp_program_clamping_and_pixel_encoding(
-+		opp,
-+		clamping);
-+
-+	return;
-+}
-+
- static void update_bios_scratch_critical_state(struct adapter_service *as,
- 		bool state)
- {
-@@ -968,9 +929,9 @@ static void disable_vga_and_power_gate_all_controllers(
- 
- 		/* Enable CLOCK gating for each pipe BEFORE controller
- 		 * powergating. */
--		dce110_enable_display_pipe_clock_gating(ctx,
-+		enable_display_pipe_clock_gating(ctx,
- 				true);
--		dce110_enable_display_power_gating(ctx, i, dcb,
-+		dc->hwss.enable_display_power_gating(ctx, i, dcb,
- 				PIPE_GATING_CONTROL_ENABLE);
- 	}
- }
-@@ -1181,7 +1142,7 @@ static void set_safe_displaymarks(struct validate_context *context)
- 	}
- }
- 
--static void dce110_program_bw(struct dc *dc, struct validate_context *context)
-+static void program_bw(struct dc *dc, struct validate_context *context)
- {
- 	set_safe_displaymarks(context);
- 	/*TODO: when pplib works*/
-@@ -1191,46 +1152,8 @@ static void dce110_program_bw(struct dc *dc, struct validate_context *context)
- 	set_displaymarks(dc, context);
- }
- 
--/*TODO: break out clock sources like timing gen/ encoder*/
--static void dce110_switch_dp_clk_src(
--	const struct dc_context *ctx,
--	const struct core_stream *stream)
--{
--	uint32_t pixel_rate_cntl_value;
--	uint32_t addr;
--	enum clock_source_id id = stream->clock_source->id;
--
--	/*TODO: proper offset*/
--	addr = mmCRTC0_PIXEL_RATE_CNTL + stream->controller_idx *
--			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
--
--	pixel_rate_cntl_value = dal_read_reg(ctx, addr);
--
--	if (id == CLOCK_SOURCE_ID_EXTERNAL) {
--
--		if (!get_reg_field_value(pixel_rate_cntl_value,
--				CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE)) {
--
--			set_reg_field_value(pixel_rate_cntl_value, 1,
--				CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
--		}
--
--	} else {
--		set_reg_field_value(pixel_rate_cntl_value,
--				0,
--				CRTC0_PIXEL_RATE_CNTL,
--				DP_DTO0_ENABLE);
--
--		set_reg_field_value(pixel_rate_cntl_value,
--				id - 1,
--				CRTC0_PIXEL_RATE_CNTL,
--				CRTC0_PIXEL_RATE_SOURCE);
--	}
--	dal_write_reg(ctx, addr, pixel_rate_cntl_value);
--}
--
- static void switch_dp_clock_sources(
--	const struct dc_context *ctx,
-+	const struct dc *dc,
- 	struct validate_context *val_context)
- {
- 	uint8_t i, j;
-@@ -1253,7 +1176,8 @@ static void switch_dp_clock_sources(
- 					stream->clock_source = clk_src;
- 					reference_clock_source(
- 						&val_context->res_ctx, clk_src);
--					dce110_switch_dp_clk_src(ctx, stream);
-+					dc->hwss.crtc_switch_to_clk_src(
-+						clk_src, stream->opp->inst);
- 				}
- 			}
- 		}
-@@ -1287,7 +1211,7 @@ static enum dc_status apply_ctx_to_hw(
- 		dcb = dal_adapter_service_get_bios_parser(
- 				context->res_ctx.pool.adapter_srv);
- 
--		dce110_enable_display_power_gating(
-+		dc->hwss.enable_display_power_gating(
- 				dc->ctx, i, dcb,
- 				PIPE_GATING_CONTROL_DISABLE);
- 	}
-@@ -1319,7 +1243,7 @@ static enum dc_status apply_ctx_to_hw(
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
- 			false);
- 
--	switch_dp_clock_sources(dc->ctx, context);
-+	switch_dp_clock_sources(dc, context);
- 
- 	return DC_OK;
- }
-@@ -1442,23 +1366,12 @@ static void program_scaler(
- 			false);
- }
- 
--static void configure_locking(struct dc_context *ctx, uint8_t controller_id)
--{
--	/* main controller should be in mode 0 (master pipe) */
--	pipe_control_lock(
--			ctx,
--			controller_id,
--			PIPE_LOCK_CONTROL_MODE,
--			false);
--
--	/* TODO: for MPO finish the non-root controllers */
--}
--
- /**
-  * Program the Front End of the Pipe.
-  * The Back End was already programmed by Set Mode.
-  */
- static bool set_plane_config(
-+	const struct dc *dc,
- 	struct core_surface *surface,
- 	struct core_target *target)
- {
-@@ -1478,11 +1391,15 @@ static bool set_plane_config(
- 	enum color_space input_color_space =
- 					surface_color_to_color_space(&(surface->public.colorimetry));
- 
--	configure_locking(ctx, controller_idx);
-+	dc->hwss.pipe_control_lock(
-+			ctx,
-+			controller_idx,
-+			PIPE_LOCK_CONTROL_MODE,
-+			false);
- 
- 	/* While a non-root controller is programmed we
- 	 * have to lock the root controller. */
--	pipe_control_lock(
-+	dc->hwss.pipe_control_lock(
- 			ctx,
- 			controller_idx,
- 			PIPE_LOCK_CONTROL_GRAPHICS |
-@@ -1493,7 +1410,7 @@ static bool set_plane_config(
- 
- 	tg->funcs->program_timing(tg, dc_crtc_timing, false);
- 
--	enable_fe_clock(ctx, controller_idx, true);
-+	dc->hwss.enable_fe_clock(ctx, controller_idx, true);
- 
- 	set_default_colors(
- 			ipp,
-@@ -1507,7 +1424,7 @@ static bool set_plane_config(
- 	program_scaler(
- 		controller_idx, tg, xfm, surface, core_stream);
- 
--	set_blender_mode(
-+	dc->hwss.set_blender_mode(
- 			ctx,
- 			controller_idx,
- 			BLENDER_MODE_CURRENT_PIPE);
-@@ -1519,7 +1436,7 @@ static bool set_plane_config(
- 			&surface->public.plane_size,
- 			surface->public.rotation);
- 
--	pipe_control_lock(
-+	dc->hwss.pipe_control_lock(
- 			ctx,
- 			controller_idx,
- 			PIPE_LOCK_CONTROL_GRAPHICS |
-@@ -1532,6 +1449,7 @@ static bool set_plane_config(
- }
- 
- static bool update_plane_address(
-+	const struct dc *dc,
- 	const struct core_surface *surface,
- 	struct core_target *target)
- {
-@@ -1542,7 +1460,7 @@ static bool update_plane_address(
- 	uint8_t controller_id = core_stream->controller_idx;
- 
- 	/* TODO: crtc should be per surface, NOT per-target */
--	pipe_control_lock(
-+	dc->hwss.pipe_control_lock(
- 		ctx,
- 		controller_id,
- 		PIPE_LOCK_CONTROL_SURFACE,
-@@ -1553,7 +1471,7 @@ static bool update_plane_address(
- 		mi, &surface->public.address, surface->public.flip_immediate))
- 		return false;
- 
--	pipe_control_lock(
-+	dc->hwss.pipe_control_lock(
- 		ctx,
- 		controller_id,
- 		PIPE_LOCK_CONTROL_SURFACE,
-@@ -1562,7 +1480,9 @@ static bool update_plane_address(
- 	return true;
- }
- 
--static void reset_single_stream_hw_ctx(struct core_stream *stream,
-+static void reset_single_stream_hw_ctx(
-+		const struct dc *dc,
-+		struct core_stream *stream,
- 		struct validate_context *context)
- {
- 	struct dc_bios *dcb;
-@@ -1583,9 +1503,8 @@ static void reset_single_stream_hw_ctx(struct core_stream *stream,
- 	stream->mi->funcs->mem_input_deallocate_dmif_buffer(
- 			stream->mi, context->target_count);
- 	stream->xfm->funcs->transform_set_scaler_bypass(stream->xfm);
--	disable_stereo_mixer(stream->ctx);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
--	dce110_enable_display_power_gating(
-+	dc->hwss.enable_display_power_gating(
- 			stream->ctx, stream->controller_idx, dcb,
- 			PIPE_GATING_CONTROL_ENABLE);
- }
-@@ -1608,7 +1527,7 @@ static void reset_hw_ctx(struct dc *dc,
- 				.flags.timing_changed)
- 			continue;
- 
--		reset_single_stream_hw_ctx(core_stream, &dc->current_context);
-+		reset_single_stream_hw_ctx(dc, core_stream, &dc->current_context);
- 	}
- }
- 
-@@ -1708,68 +1627,25 @@ static void enable_timing_synchronization(
- 	DC_SYNC_INFO("GSL: Set-up complete.\n");
- }
- 
--static void get_crtc_positions(struct timing_generator *tg,
--		int32_t *h_position, int32_t *v_position)
--{
--	tg->funcs->get_position(tg, h_position, v_position);
--}
--
--static bool enable_memory_request(struct timing_generator *tg)
--{
--	return tg->funcs->set_blank(tg, false);
--}
--
--static bool disable_memory_requests(struct timing_generator *tg)
--{
--	return tg->funcs->set_blank(tg, true);
--}
--
--static uint32_t get_vblank_counter(struct timing_generator *tg)
--{
--	return tg->funcs->get_frame_count(tg);
--}
--
--static void disable_vga(struct timing_generator *tg)
--{
--	tg->funcs->disable_vga(tg);
--}
--
--static void set_mst_bandwidth(struct stream_encoder *stream_enc,
--	struct fixed31_32 avg_time_slots_per_mtp)
--{
--	stream_enc->funcs->set_mst_bandwidth(stream_enc,
--		avg_time_slots_per_mtp);
--}
--
--
- static const struct hw_sequencer_funcs dce110_funcs = {
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
- 	.reset_hw_ctx = reset_hw_ctx,
- 	.set_plane_config = set_plane_config,
- 	.update_plane_address = update_plane_address,
--	.enable_memory_requests = enable_memory_request,
--	.disable_memory_requests = disable_memory_requests,
- 	.set_gamma_ramp = set_gamma_ramp,
- 	.power_down = power_down,
- 	.enable_accelerated_mode = enable_accelerated_mode,
--	.get_crtc_positions = get_crtc_positions,
--	.get_vblank_counter = get_vblank_counter,
- 	.enable_timing_synchronization = enable_timing_synchronization,
--	.disable_vga = disable_vga,
--	.encoder_create = dce110_link_encoder_create,
--	.encoder_destroy = dce110_link_encoder_destroy,
--	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
--	.construct_resource_pool = dce110_construct_resource_pool,
--	.destruct_resource_pool = dce110_destruct_resource_pool,
--	.validate_with_context = dce110_validate_with_context,
--	.validate_bandwidth = dce110_validate_bandwidth,
--	.enable_display_pipe_clock_gating =
--		dce110_enable_display_pipe_clock_gating,
--	.enable_display_power_gating = dce110_enable_display_power_gating,
--	.program_bw = dce110_program_bw,
-+	.program_bw = program_bw,
- 	.enable_stream = enable_stream,
- 	.disable_stream = disable_stream,
--	.set_mst_bandwidth = set_mst_bandwidth,
-+	.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
-+	.crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
-+	.enable_display_power_gating = dce110_enable_display_power_gating,
-+	.enable_fe_clock = dce110_enable_fe_clock,
-+	.pipe_control_lock = dce110_pipe_control_lock,
-+	.set_blender_mode = dce110_set_blender_mode,
-+	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,/*todo*/
- };
- 
- bool dce110_hw_sequencer_construct(struct dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 41717eb..8f5acbd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -30,8 +30,6 @@
- #include "resource.h"
- #include "include/irq_service_interface.h"
- #include "../virtual/virtual_stream_encoder.h"
--#include "inc/timing_generator_types.h"
--
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_mem_input.h"
-@@ -43,7 +41,6 @@
- 
- #include "dce/dce_11_0_d.h"
- 
--/* TODO remove these defines */
- #ifndef mmDP_DPHY_INTERNAL_CTRL
- 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
- 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-@@ -475,225 +472,6 @@ void dce110_clock_source_destroy(struct clock_source **clk_src)
- 	*clk_src = NULL;
- }
- 
--bool dce110_construct_resource_pool(
--	struct adapter_service *adapter_serv,
--	uint8_t num_virtual_links,
--	struct dc *dc,
--	struct resource_pool *pool)
--{
--	unsigned int i;
--	struct audio_init_data audio_init_data = { 0 };
--	struct dc_context *ctx = dc->ctx;
--	pool->adapter_srv = adapter_serv;
--
--	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
--	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
--
--	pool->clock_sources[DCE110_CLK_SRC_PLL0] = dce110_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL0, &dce110_clk_src_reg_offsets[0]);
--	pool->clock_sources[DCE110_CLK_SRC_PLL1] = dce110_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL1, &dce110_clk_src_reg_offsets[1]);
--	pool->clock_sources[DCE110_CLK_SRC_EXT] =  dce110_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_EXTERNAL, &dce110_clk_src_reg_offsets[0]);
--	pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
--
--	for (i = 0; i < pool->clk_src_count; i++) {
--		if (pool->clock_sources[i] == NULL) {
--			dal_error("DC: failed to create clock sources!\n");
--			BREAK_TO_DEBUGGER();
--			goto clk_src_create_fail;
--		}
--	}
--
--	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
--	if (pool->display_clock == NULL) {
--		dal_error("DC: failed to create display clock!\n");
--		BREAK_TO_DEBUGGER();
--		goto disp_clk_create_fail;
--	}
--
--	{
--		struct irq_service_init_data init_data;
--		init_data.ctx = dc->ctx;
--		pool->irqs = dal_irq_service_create(
--				dal_adapter_service_get_dce_version(
--					dc->res_pool.adapter_srv),
--				&init_data);
--		if (!pool->irqs)
--			goto irqs_create_fail;
--
--	}
--
--	pool->controller_count =
--		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
--			adapter_serv);
--	pool->scaler_filter = dal_scaler_filter_create(ctx);
--	if (pool->scaler_filter == NULL) {
--		BREAK_TO_DEBUGGER();
--		dal_error("DC: failed to create filter!\n");
--		goto filter_create_fail;
--	}
--
--	for (i = 0; i < pool->controller_count; i++) {
--		pool->timing_generators[i] = dce110_timing_generator_create(
--				adapter_serv, ctx, i, &dce110_tg_offsets[i]);
--		if (pool->timing_generators[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create tg!\n");
--			goto controller_create_fail;
--		}
--
--		pool->mis[i] = dce110_mem_input_create(ctx, i,
--				&dce110_mi_reg_offsets[i]);
--		if (pool->mis[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create memory input!\n");
--			goto controller_create_fail;
--		}
--
--		pool->ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]);
--		if (pool->ipps[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create input pixel processor!\n");
--			goto controller_create_fail;
--		}
--
--		pool->transforms[i] = dce110_transform_create(
--					ctx, i, &dce110_xfm_offsets[i]);
--		if (pool->transforms[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create transform!\n");
--			goto controller_create_fail;
--		}
--		pool->transforms[i]->funcs->transform_set_scaler_filter(
--				pool->transforms[i],
--				pool->scaler_filter);
--
--		pool->opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]);
--		if (pool->opps[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error(
--				"DC: failed to create output pixel processor!\n");
--			goto controller_create_fail;
--		}
--	}
--
--	audio_init_data.as = adapter_serv;
--	audio_init_data.ctx = ctx;
--	pool->audio_count = 0;
--	for (i = 0; i < pool->controller_count; i++) {
--		struct graphics_object_id obj_id;
--
--		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
--		if (false == dal_graphics_object_id_is_valid(obj_id)) {
--			/* no more valid audio objects */
--			break;
--		}
--
--		audio_init_data.audio_stream_id = obj_id;
--		pool->audios[i] = dal_audio_create(&audio_init_data);
--		if (pool->audios[i] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create DPPs!\n");
--			goto audio_create_fail;
--		}
--		pool->audio_count++;
--	}
--
--	for (i = 0; i < pool->stream_enc_count; i++) {
--		/* TODO: rework fragile code*/
--		if (pool->stream_engines.u_all & 1 << i) {
--			pool->stream_enc[i] = dce110_stream_encoder_create(
--				i, dc->ctx,
--				dal_adapter_service_get_bios_parser(
--					adapter_serv),
--				&stream_enc_regs[i]);
--			if (pool->stream_enc[i] == NULL) {
--				BREAK_TO_DEBUGGER();
--				dal_error("DC: failed to create stream_encoder!\n");
--				goto stream_enc_create_fail;
--			}
--		}
--	}
--
--	for (i = 0; i < num_virtual_links; i++) {
--		pool->stream_enc[pool->stream_enc_count] =
--			virtual_stream_encoder_create(
--				dc->ctx, dal_adapter_service_get_bios_parser(
--								adapter_serv));
--		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
--			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create stream_encoder!\n");
--			goto stream_enc_create_fail;
--		}
--		pool->stream_enc_count++;
--	}
--
--	return true;
--
--stream_enc_create_fail:
--	for (i = 0; i < pool->stream_enc_count; i++) {
--		if (pool->stream_enc[i] != NULL)
--			dc_service_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
--	}
--
--audio_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
--		if (pool->audios[i] != NULL)
--			dal_audio_destroy(&pool->audios[i]);
--	}
--
--controller_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
--		if (pool->opps[i] != NULL)
--			dce110_opp_destroy(&pool->opps[i]);
--
--		if (pool->transforms[i] != NULL)
--			dce110_transform_destroy(&pool->transforms[i]);
--
--		if (pool->ipps[i] != NULL)
--			dce110_ipp_destroy(&pool->ipps[i]);
--
--		if (pool->mis[i] != NULL) {
--			dc_service_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
--			pool->mis[i] = NULL;
--		}
--
--		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx,
--				DCE110TG_FROM_TG(pool->timing_generators[i]));
--			pool->timing_generators[i] = NULL;
--		}
--	}
--
--filter_create_fail:
--	dal_irq_service_destroy(&pool->irqs);
--
--irqs_create_fail:
--	dal_display_clock_destroy(&pool->display_clock);
--
--disp_clk_create_fail:
--clk_src_create_fail:
--	for (i = 0; i < pool->clk_src_count; i++) {
--		if (pool->clock_sources[i] != NULL)
--			dce110_clock_source_destroy(&pool->clock_sources[i]);
--	}
--	return false;
--}
--
- void dce110_destruct_resource_pool(struct resource_pool *pool)
- {
- 	unsigned int i;
-@@ -737,6 +515,7 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 			dal_audio_destroy(&pool->audios[i]);
- 		}
- 	}
-+
- 	if (pool->display_clock != NULL) {
- 		dal_display_clock_destroy(&pool->display_clock);
- 	}
-@@ -1227,3 +1006,232 @@ enum dc_status dce110_validate_with_context(
- 
- 	return result;
- }
-+
-+static struct resource_funcs dce110_res_pool_funcs = {
-+	.destruct = dce110_destruct_resource_pool,
-+	.link_enc_create = dce110_link_encoder_create,
-+	.link_enc_destroy = dce110_link_encoder_destroy,
-+	.validate_with_context = dce110_validate_with_context,
-+	.validate_bandwidth = dce110_validate_bandwidth
-+};
-+
-+bool dce110_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct audio_init_data audio_init_data = { 0 };
-+	struct dc_context *ctx = dc->ctx;
-+	pool->adapter_srv = adapter_serv;
-+	pool->funcs = &dce110_res_pool_funcs;
-+
-+	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
-+
-+	pool->clock_sources[DCE110_CLK_SRC_PLL0] = dce110_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL0, &dce110_clk_src_reg_offsets[0]);
-+	pool->clock_sources[DCE110_CLK_SRC_PLL1] = dce110_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL1, &dce110_clk_src_reg_offsets[1]);
-+	pool->clock_sources[DCE110_CLK_SRC_EXT] =  dce110_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_EXTERNAL, &dce110_clk_src_reg_offsets[0]);
-+	pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] == NULL) {
-+			dal_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
-+	if (pool->display_clock == NULL) {
-+		dal_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->irqs = dal_irq_service_create(
-+				dal_adapter_service_get_dce_version(
-+					dc->res_pool.adapter_srv),
-+				&init_data);
-+		if (!pool->irqs)
-+			goto irqs_create_fail;
-+
-+	}
-+
-+	pool->controller_count =
-+		dal_adapter_service_get_func_controllers_num(adapter_serv);
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
-+			adapter_serv);
-+	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+	if (pool->scaler_filter == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dal_error("DC: failed to create filter!\n");
-+		goto filter_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->controller_count; i++) {
-+		pool->timing_generators[i] = dce110_timing_generator_create(
-+				adapter_serv, ctx, i, &dce110_tg_offsets[i]);
-+		if (pool->timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->mis[i] = dce110_mem_input_create(ctx, i,
-+				&dce110_mi_reg_offsets[i]);
-+		if (pool->mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]);
-+		if (pool->ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->transforms[i] = dce110_transform_create(
-+					ctx, i, &dce110_xfm_offsets[i]);
-+		if (pool->transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create transform!\n");
-+			goto controller_create_fail;
-+		}
-+		pool->transforms[i]->funcs->transform_set_scaler_filter(
-+				pool->transforms[i],
-+				pool->scaler_filter);
-+
-+		pool->opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]);
-+		if (pool->opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+	}
-+
-+	audio_init_data.as = adapter_serv;
-+	audio_init_data.ctx = ctx;
-+	pool->audio_count = 0;
-+	for (i = 0; i < pool->controller_count; i++) {
-+		struct graphics_object_id obj_id;
-+
-+		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		if (false == dal_graphics_object_id_is_valid(obj_id)) {
-+			/* no more valid audio objects */
-+			break;
-+		}
-+
-+		audio_init_data.audio_stream_id = obj_id;
-+		pool->audios[i] = dal_audio_create(&audio_init_data);
-+		if (pool->audios[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create DPPs!\n");
-+			goto audio_create_fail;
-+		}
-+		pool->audio_count++;
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		/* TODO: rework fragile code*/
-+		if (pool->stream_engines.u_all & 1 << i) {
-+			pool->stream_enc[i] = dce110_stream_encoder_create(
-+				i, dc->ctx,
-+				dal_adapter_service_get_bios_parser(
-+					adapter_serv),
-+				&stream_enc_regs[i]);
-+			if (pool->stream_enc[i] == NULL) {
-+				BREAK_TO_DEBUGGER();
-+				dal_error("DC: failed to create stream_encoder!\n");
-+				goto stream_enc_create_fail;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < num_virtual_links; i++) {
-+		pool->stream_enc[pool->stream_enc_count] =
-+			virtual_stream_encoder_create(
-+				dc->ctx, dal_adapter_service_get_bios_parser(
-+								adapter_serv));
-+		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dal_error("DC: failed to create stream_encoder!\n");
-+			goto stream_enc_create_fail;
-+		}
-+		pool->stream_enc_count++;
-+	}
-+
-+	return true;
-+
-+stream_enc_create_fail:
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dc_service_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+audio_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+
-+controller_create_fail:
-+	for (i = 0; i < pool->controller_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce110_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce110_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce110_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dc_service_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL)	{
-+			dc_service_free(pool->timing_generators[i]->ctx,
-+				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+filter_create_fail:
-+	dal_irq_service_destroy(&pool->irqs);
-+
-+irqs_create_fail:
-+	dal_display_clock_destroy(&pool->display_clock);
-+
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dce110_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+
-+	return false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-index 5f00a3c..5d60df2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-@@ -31,8 +31,6 @@
- struct adapter_service;
- struct dc;
- struct resource_pool;
--struct dc_validation_set;
--
- 
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
-@@ -42,19 +40,6 @@ bool dce110_construct_resource_pool(
- 
- void dce110_destruct_resource_pool(struct resource_pool *pool);
- 
--enum dc_status dce110_validate_with_context(
--		const struct dc *dc,
--		const struct dc_validation_set set[],
--		uint8_t set_count,
--		struct validate_context *context);
--
--enum dc_status dce110_validate_bandwidth(
--		const struct dc *dc,
--		struct validate_context *context);
--
--struct link_encoder *dce110_link_encoder_create(
--	const struct encoder_init_data *enc_init_data);
--
- void dce110_link_encoder_destroy(struct link_encoder **enc);
- 
- #endif /* __DC_RESOURCE_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 79e34dc..50b7c70 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -35,8 +35,8 @@
- #include "include/grph_object_id.h"
- #include "include/adapter_service_interface.h"
- #include "include/logger_interface.h"
--#include "inc/timing_generator_types.h"
- #include "dce110_timing_generator.h"
-+#include "../inc/timing_generator.h"
- 
- enum black_color_format {
- 	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 0a57052..163fadd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -27,7 +27,7 @@
- #define __DC_TIMING_GENERATOR_DCE110_H__
- 
- 
--#include "inc/timing_generator_types.h"
-+#include "../inc/timing_generator.h"
- #include "../include/grph_object_id.h"
- #include "../include/hw_sequencer_types.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index d794132..4d4fd0c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -14,10 +14,8 @@
- struct dc {
- 	struct dc_context *ctx;
- 
--	/** link-related data - begin **/
- 	uint8_t link_count;
- 	struct core_link *links[MAX_PIPES * 2];
--	/** link-related data - end **/
- 
- 	/* TODO: determine max number of targets*/
- 	struct validate_context current_context;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index e3b5918..7d63ebb 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -273,6 +273,25 @@ void core_link_disable_stream(
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
- 
-+struct resource_pool;
-+struct validate_context;
-+
-+struct resource_funcs {
-+	void (*destruct)(struct resource_pool *pool);
-+	struct link_encoder *(*link_enc_create)(
-+			const struct encoder_init_data *init);
-+	void (*link_enc_destroy)(struct link_encoder **enc);
-+	enum dc_status (*validate_with_context)(
-+					const struct dc *dc,
-+					const struct dc_validation_set set[],
-+					uint8_t set_count,
-+					struct validate_context *context);
-+
-+	enum dc_status (*validate_bandwidth)(
-+					const struct dc *dc,
-+					struct validate_context *context);
-+};
-+
- struct resource_pool {
- 	struct scaler_filter * scaler_filter;
- 
-@@ -297,6 +316,8 @@ struct resource_pool {
- 	struct display_clock *display_clock;
- 	struct adapter_service *adapter_srv;
- 	struct irq_service *irqs;
-+
-+	struct resource_funcs *funcs;
- };
- 
- struct controller_ctx {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 1dedf7c..bbb39e4 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -39,68 +39,47 @@ enum pipe_gating_control {
- struct hw_sequencer_funcs {
- 
- 	enum dc_status (*apply_ctx_to_hw)(
--					const struct dc *dc,
--					struct validate_context *context);
-+			const struct dc *dc, struct validate_context *context);
- 
--	void (*reset_hw_ctx)(struct dc *dc,
--					struct validate_context *context,
--					uint8_t target_count);
-+	void (*reset_hw_ctx)(
-+				struct dc *dc,
-+				struct validate_context *context,
-+				uint8_t target_count);
- 
- 	bool (*set_plane_config)(
--					struct core_surface *surface,
--					struct core_target *target);
-+				const struct dc *dc,
-+				struct core_surface *surface,
-+				struct core_target *target);
- 
- 	bool (*update_plane_address)(
--					const struct core_surface *surface,
--					struct core_target *target);
--
--	bool (*enable_memory_requests)(struct timing_generator *tg);
--
--	bool (*disable_memory_requests)(struct timing_generator *tg);
--
--	bool (*transform_power_up)(struct transform *xfm);
-+				const struct dc *dc,
-+				const struct core_surface *surface,
-+				struct core_target *target);
- 
- 	bool (*set_gamma_ramp)(
--					struct input_pixel_processor *ipp,
--					struct output_pixel_processor *opp,
--					const struct gamma_ramp *ramp,
--					const struct gamma_parameters *params);
-+				struct input_pixel_processor *ipp,
-+				struct output_pixel_processor *opp,
-+				const struct gamma_ramp *ramp,
-+				const struct gamma_parameters *params);
- 
- 	void (*power_down)(struct dc *dc);
- 
- 	void (*enable_accelerated_mode)(struct dc *dc);
- 
--	void (*get_crtc_positions)(
--					struct timing_generator *tg,
--					int32_t *h_position,
--					int32_t *v_position);
--
--	uint32_t (*get_vblank_counter)(struct timing_generator *tg);
--
- 	void (*enable_timing_synchronization)(
- 					struct dc_context *dc_ctx,
- 					uint32_t timing_generator_num,
- 					struct timing_generator *tgs[]);
- 
--	void (*disable_vga)(struct timing_generator *tg);
--
--
--
--	/* link encoder sequences */
--	struct link_encoder *(*encoder_create)(
--			const struct encoder_init_data *init);
--
--	void (*encoder_destroy)(struct link_encoder **enc);
--
- 	/* backlight control */
--	void (*encoder_set_lcd_backlight_level)(struct link_encoder *enc,
--					uint32_t level);
-+	void (*encoder_set_lcd_backlight_level)(
-+		struct link_encoder *enc, uint32_t level);
-+
- 
-+	void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t);
- 
- 	/* power management */
--	void (*clock_gating_power_up)(
--					struct dc_context *ctx,
--					bool enable);
-+	void (*clock_gating_power_up)(struct dc_context *ctx, bool enable);
- 
- 	void (*enable_display_pipe_clock_gating)(
- 					struct dc_context *ctx,
-@@ -112,36 +91,25 @@ struct hw_sequencer_funcs {
- 					struct dc_bios *dcb,
- 					enum pipe_gating_control power_gating);
- 
--	/* resource management and validation*/
--	bool (*construct_resource_pool)(
--					struct adapter_service *adapter_serv,
--					uint8_t num_virtual_links,
--					struct dc *dc,
--					struct resource_pool *pool);
--
--	void (*destruct_resource_pool)(struct resource_pool *pool);
--
--	enum dc_status (*validate_with_context)(
--					const struct dc *dc,
--					const struct dc_validation_set set[],
--					uint8_t set_count,
--					struct validate_context *context);
--
--	enum dc_status (*validate_bandwidth)(
--					const struct dc *dc,
--					struct validate_context *context);
--	void (*program_bw)(
--					struct dc *dc,
--					struct validate_context *context);
--	void (*enable_stream)(
--					struct core_stream *stream);
--
--	void (*disable_stream)(
--					struct core_stream *stream);
--
--	void (*set_mst_bandwidth)(
--					struct stream_encoder *enc,
--					struct fixed31_32 avg_time_slots_per_mtp);
-+	void (*program_bw)(struct dc *dc, struct validate_context *context);
-+
-+	void (*enable_stream)(struct core_stream *stream);
-+
-+	void (*disable_stream)(struct core_stream *stream);
-+
-+	void (*enable_fe_clock)(
-+		struct dc_context *ctx, uint8_t controller_id, bool enable);
-+
-+	bool (*pipe_control_lock)(
-+				struct dc_context *ctx,
-+				uint8_t controller_idx,
-+				uint32_t control_mask,
-+				bool lock);
-+
-+	void (*set_blender_mode)(
-+				struct dc_context *ctx,
-+				uint8_t controller_id,
-+				uint32_t mode);
- };
- 
- bool dc_construct_hw_sequencer(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index ea6be75..bda92e3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -32,6 +32,10 @@
- /* TODO unhardcode, 4 for CZ*/
- #define MEMORY_TYPE_MULTIPLIER 4
- 
-+bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
-+				struct dc *dc,
-+				uint8_t num_virtual_links);
-+
- void build_scaling_params(
- 	const struct dc_surface *surface,
- 	struct core_stream *stream);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-new file mode 100644
-index 0000000..e9ca169
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-@@ -0,0 +1,155 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
-+#define __DAL_TIMING_GENERATOR_TYPES_H__
-+
-+#include "include/grph_csc_types.h"
-+
-+struct dc_bios;
-+
-+/**
-+ *  These parameters are required as input when doing blanking/Unblanking
-+*/
-+struct crtc_black_color {
-+	uint32_t black_color_r_cr;
-+	uint32_t black_color_g_y;
-+	uint32_t black_color_b_cb;
-+};
-+
-+/* Contains CRTC vertical/horizontal pixel counters */
-+struct crtc_position {
-+	uint32_t vertical_count;
-+	uint32_t horizontal_count;
-+	uint32_t nominal_vcount;
-+};
-+
-+
-+enum dcp_gsl_purpose {
-+	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
-+	DCP_GSL_PURPOSE_STEREO3D_PHASE,
-+	DCP_GSL_PURPOSE_UNDEFINED
-+};
-+
-+struct dcp_gsl_params {
-+	enum sync_source gsl_group;
-+	enum dcp_gsl_purpose gsl_purpose;
-+	bool timing_server;
-+	bool overlay_present;
-+	bool gsl_paused;
-+};
-+
-+#define LEFT_EYE_3D_PRIMARY_SURFACE 1
-+#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
-+
-+enum test_pattern_dyn_range {
-+	TEST_PATTERN_DYN_RANGE_VESA = 0,
-+	TEST_PATTERN_DYN_RANGE_CEA
-+};
-+
-+enum test_pattern_mode {
-+	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
-+	TEST_PATTERN_MODE_VERTICALBARS,
-+	TEST_PATTERN_MODE_HORIZONTALBARS,
-+	TEST_PATTERN_MODE_SINGLERAMP_RGB,
-+	TEST_PATTERN_MODE_DUALRAMP_RGB
-+};
-+
-+enum test_pattern_color_format {
-+	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_8,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_10,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_12
-+};
-+
-+enum controller_dp_test_pattern {
-+	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
-+	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
-+	CONTROLLER_DP_TEST_PATTERN_PRBS7,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
-+	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
-+	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-+};
-+
-+enum crtc_state {
-+	CRTC_STATE_VBLANK = 0,
-+	CRTC_STATE_VACTIVE
-+};
-+
-+struct timing_generator {
-+	struct timing_generator_funcs *funcs;
-+	struct dc_bios *bp;
-+	struct dc_context *ctx;
-+};
-+
-+
-+struct dc_crtc_timing;
-+
-+struct timing_generator_funcs {
-+	bool (*validate_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing);
-+	void (*program_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing,
-+							bool use_vbios);
-+	bool (*enable_crtc)(struct timing_generator *tg);
-+	bool (*disable_crtc)(struct timing_generator *tg);
-+	bool (*is_counter_moving)(struct timing_generator *tg);
-+	void (*get_position)(struct timing_generator *tg,
-+								int32_t *h_position,
-+								int32_t *v_position);
-+	uint32_t (*get_frame_count)(struct timing_generator *tg);
-+	void (*set_early_control)(struct timing_generator *tg,
-+							   uint32_t early_cntl);
-+	void (*wait_for_state)(struct timing_generator *tg,
-+							enum crtc_state state);
-+	bool (*set_blank)(struct timing_generator *tg,
-+					   bool enable_blanking);
-+	void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color);
-+	void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color);
-+	void (*set_colors)(struct timing_generator *tg,
-+						const struct crtc_black_color *blank_color,
-+						const struct crtc_black_color *overscan_color);
-+
-+	void (*disable_vga)(struct timing_generator *tg);
-+	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
-+	void (*setup_global_swap_lock)(struct timing_generator *tg,
-+							const struct dcp_gsl_params *gsl_params);
-+	void (*enable_reset_trigger)(struct timing_generator *tg,
-+						const struct trigger_params *trigger_params);
-+	void (*disable_reset_trigger)(struct timing_generator *tg);
-+	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
-+	void (*enable_advanced_request)(struct timing_generator *tg,
-+					bool enable, const struct dc_crtc_timing *timing);
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h
-deleted file mode 100644
-index e9ca169..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator_types.h
-+++ /dev/null
-@@ -1,155 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
--#define __DAL_TIMING_GENERATOR_TYPES_H__
--
--#include "include/grph_csc_types.h"
--
--struct dc_bios;
--
--/**
-- *  These parameters are required as input when doing blanking/Unblanking
--*/
--struct crtc_black_color {
--	uint32_t black_color_r_cr;
--	uint32_t black_color_g_y;
--	uint32_t black_color_b_cb;
--};
--
--/* Contains CRTC vertical/horizontal pixel counters */
--struct crtc_position {
--	uint32_t vertical_count;
--	uint32_t horizontal_count;
--	uint32_t nominal_vcount;
--};
--
--
--enum dcp_gsl_purpose {
--	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
--	DCP_GSL_PURPOSE_STEREO3D_PHASE,
--	DCP_GSL_PURPOSE_UNDEFINED
--};
--
--struct dcp_gsl_params {
--	enum sync_source gsl_group;
--	enum dcp_gsl_purpose gsl_purpose;
--	bool timing_server;
--	bool overlay_present;
--	bool gsl_paused;
--};
--
--#define LEFT_EYE_3D_PRIMARY_SURFACE 1
--#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
--
--enum test_pattern_dyn_range {
--	TEST_PATTERN_DYN_RANGE_VESA = 0,
--	TEST_PATTERN_DYN_RANGE_CEA
--};
--
--enum test_pattern_mode {
--	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
--	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
--	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
--	TEST_PATTERN_MODE_VERTICALBARS,
--	TEST_PATTERN_MODE_HORIZONTALBARS,
--	TEST_PATTERN_MODE_SINGLERAMP_RGB,
--	TEST_PATTERN_MODE_DUALRAMP_RGB
--};
--
--enum test_pattern_color_format {
--	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
--	TEST_PATTERN_COLOR_FORMAT_BPC_8,
--	TEST_PATTERN_COLOR_FORMAT_BPC_10,
--	TEST_PATTERN_COLOR_FORMAT_BPC_12
--};
--
--enum controller_dp_test_pattern {
--	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
--	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
--	CONTROLLER_DP_TEST_PATTERN_PRBS7,
--	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
--	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
--	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
--	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
--	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
--	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
--};
--
--enum crtc_state {
--	CRTC_STATE_VBLANK = 0,
--	CRTC_STATE_VACTIVE
--};
--
--struct timing_generator {
--	struct timing_generator_funcs *funcs;
--	struct dc_bios *bp;
--	struct dc_context *ctx;
--};
--
--
--struct dc_crtc_timing;
--
--struct timing_generator_funcs {
--	bool (*validate_timing)(struct timing_generator *tg,
--							const struct dc_crtc_timing *timing);
--	void (*program_timing)(struct timing_generator *tg,
--							const struct dc_crtc_timing *timing,
--							bool use_vbios);
--	bool (*enable_crtc)(struct timing_generator *tg);
--	bool (*disable_crtc)(struct timing_generator *tg);
--	bool (*is_counter_moving)(struct timing_generator *tg);
--	void (*get_position)(struct timing_generator *tg,
--								int32_t *h_position,
--								int32_t *v_position);
--	uint32_t (*get_frame_count)(struct timing_generator *tg);
--	void (*set_early_control)(struct timing_generator *tg,
--							   uint32_t early_cntl);
--	void (*wait_for_state)(struct timing_generator *tg,
--							enum crtc_state state);
--	bool (*set_blank)(struct timing_generator *tg,
--					   bool enable_blanking);
--	void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color);
--	void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color);
--	void (*set_colors)(struct timing_generator *tg,
--						const struct crtc_black_color *blank_color,
--						const struct crtc_black_color *overscan_color);
--
--	void (*disable_vga)(struct timing_generator *tg);
--	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
--	void (*setup_global_swap_lock)(struct timing_generator *tg,
--							const struct dcp_gsl_params *gsl_params);
--	void (*enable_reset_trigger)(struct timing_generator *tg,
--						const struct trigger_params *trigger_params);
--	void (*disable_reset_trigger)(struct timing_generator *tg);
--	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
--	void (*enable_advanced_request)(struct timing_generator *tg,
--					bool enable, const struct dc_crtc_timing *timing);
--};
--
--#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0742-drm-amd-dal-Fixed-DCE100-audio-issue.patch b/common/recipes-kernel/linux/files/0742-drm-amd-dal-Fixed-DCE100-audio-issue.patch
deleted file mode 100644
index 95f84ab5..00000000
--- a/common/recipes-kernel/linux/files/0742-drm-amd-dal-Fixed-DCE100-audio-issue.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From f835841f199a37e0f0c8744b434c49556bc97306 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 27 Jan 2016 16:45:57 -0500
-Subject: [PATCH 0742/1110] drm/amd/dal: Fixed DCE100 audio issue.
-
-DP audio doesn't work on DCE100 due to wrong clock
-value get from integrated info. For desktop cpu, integrated info
-couldn't get from vbios, value can be hardcode.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c | 10 +++++++---
- 1 file changed, 7 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 3e0e9b3..9252b5c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -648,11 +648,12 @@ static bool display_clock_integrated_info_construct(
- {
- 	struct integrated_info info;
- 	uint32_t i;
--
- 	struct display_clock *base = &disp_clk->disp_clk_base;
-+	bool res;
- 
--	if (!dal_adapter_service_get_integrated_info(as, &info))
--		return false;
-+	dc_service_memset(&info, 0, sizeof(struct integrated_info));
-+
-+	res = dal_adapter_service_get_integrated_info(as, &info);
- 
- 	disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
- 	if (disp_clk->dentist_vco_freq_khz == 0)
-@@ -661,6 +662,9 @@ static bool display_clock_integrated_info_construct(
- 	base->min_display_clk_threshold_khz =
- 		disp_clk->dentist_vco_freq_khz / 64;
- 
-+	if (!res)
-+		return false;
-+
- 	/*update the maximum display clock for each power state*/
- 	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- 		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0743-drm-amd-dal-remove-warning-in-bios-makefile.patch b/common/recipes-kernel/linux/files/0743-drm-amd-dal-remove-warning-in-bios-makefile.patch
deleted file mode 100644
index bc705741..00000000
--- a/common/recipes-kernel/linux/files/0743-drm-amd-dal-remove-warning-in-bios-makefile.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 00d705afec8bfc7423772b4d8b94dc3b74e0d46a Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 28 Jan 2016 18:12:03 +0800
-Subject: [PATCH 0743/1110] drm/amd/dal: remove warning in bios makefile
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-index 75bb892..ddfe457 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-@@ -11,7 +11,6 @@ AMD_DAL_FILES += $(AMD_DAL_BIOS)
- ifndef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- AMD_DAL_FILES := $(filter-out $(AMDDALPATH)/dc/bios/bios_parser_helper.o,$(AMD_DAL_FILES))
- endif
--$(warning AMD_DAL_FILES=$(AMD_DAL_FILES))
- 
- 
- ###############################################################################
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0744-drm-amd-dal-small-clean-up-in-cursor-code.patch b/common/recipes-kernel/linux/files/0744-drm-amd-dal-small-clean-up-in-cursor-code.patch
deleted file mode 100644
index 5948d1be..00000000
--- a/common/recipes-kernel/linux/files/0744-drm-amd-dal-small-clean-up-in-cursor-code.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From ab37a6189bf187cc0d7b1c2972830bd4e59b0017 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 28 Jan 2016 18:24:27 +0800
-Subject: [PATCH 0744/1110] drm/amd/dal: small clean-up in cursor code
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 6792aea..af71e87 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -107,7 +107,7 @@ static int dm_crtc_unpin_cursor_bo_old(
- 	if (NULL != amdgpu_crtc && NULL != amdgpu_crtc->cursor_bo) {
- 		robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
- 
--		ret  = amdgpu_bo_reserve(robj, false);
-+		ret = amdgpu_bo_reserve(robj, false);
- 
- 		if (likely(ret == 0)) {
- 			ret = amdgpu_bo_unpin(robj);
-@@ -128,10 +128,10 @@ static int dm_crtc_unpin_cursor_bo_old(
- 				ret,
- 				amdgpu_crtc->cursor_bo);
- 		}
--	}
- 
--	drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
--	amdgpu_crtc->cursor_bo = NULL;
-+		drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
-+		amdgpu_crtc->cursor_bo = NULL;
-+	}
- 
- 	return ret;
- }
-@@ -145,7 +145,7 @@ static int dm_crtc_pin_cursor_bo_new(
- 	struct amdgpu_crtc *amdgpu_crtc;
- 	struct amdgpu_bo *robj;
- 	struct drm_gem_object *obj;
--	int ret = EINVAL;
-+	int ret = -EINVAL;
- 
- 	if (NULL != crtc) {
- 		struct drm_device *dev = crtc->dev;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0745-drm-amd-dal-Relocate-dcs-to-core.patch b/common/recipes-kernel/linux/files/0745-drm-amd-dal-Relocate-dcs-to-core.patch
deleted file mode 100644
index 676b4d66..00000000
--- a/common/recipes-kernel/linux/files/0745-drm-amd-dal-Relocate-dcs-to-core.patch
+++ /dev/null
@@ -1,2876 +0,0 @@
-From c342d6c1517ab16a7ac2c2e1211249339d8b6929 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Wed, 27 Jan 2016 16:14:24 -0500
-Subject: [PATCH 0745/1110] drm/amd/dal: Relocate dcs to core
-
-Ddc service and I2caux helper moved to dc_link_ddc.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |    4 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |    2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |    2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      | 1151 ++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       |    2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |    2 +-
- drivers/gpu/drm/amd/dal/dc/dcs/Makefile            |   10 -
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c |  159 ---
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h |   60 -
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c       | 1036 ------------------
- drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h       |   49 -
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h       |  151 +++
- .../drm/amd/dal/include/ddc_service_interface.h    |  100 --
- 13 files changed, 1308 insertions(+), 1420 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/Makefile
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
- delete mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index 4396203..aed26ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -3,7 +3,7 @@
- #
- 
- DC_LIBS = adapter asic_capability audio basics bios calcs \
--dcs gpio gpu i2caux irq virtual
-+gpio gpu i2caux irq virtual
- 
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- DC_LIBS += dce110
-@@ -18,7 +18,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS))
- include $(AMD_DC)
- 
- DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_target.o dc_sink.o dc_stream.o \
--dc_hw_sequencer.o dc_surface.o dc_link_hwss.o dc_link_dp.o
-+dc_hw_sequencer.o dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o
- 
- AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index b3c919c..770a66c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -45,7 +45,7 @@
- #include "link_hwss.h"
- #include "link_encoder.h"
- 
--#include "dcs/ddc_service.h"
-+#include "dc_link_ddc.h"
- 
- /*******************************************************************************
-  * Private structures
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index c81f4a2..71653fa 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -30,9 +30,9 @@
- #include "adapter_service_interface.h"
- #include "grph_object_id.h"
- #include "gpio_service_interface.h"
--#include "ddc_service_interface.h"
- #include "core_status.h"
- #include "dc_link_dp.h"
-+#include "dc_link_ddc.h"
- #include "link_hwss.h"
- #include "stream_encoder.h"
- #include "link_encoder.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-new file mode 100644
-index 0000000..60fc743
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -0,0 +1,1151 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_services.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/ddc_service_types.h"
-+#include "include/grph_object_id.h"
-+#include "include/dpcd_defs.h"
-+#include "include/logger_interface.h"
-+#include "include/vector.h"
-+
-+#include "dc_link_ddc.h"
-+
-+#define AUX_POWER_UP_WA_DELAY 500
-+#define I2C_OVER_AUX_DEFER_WA_DELAY 70
-+
-+/* CV smart dongle slave address for retrieving supported HDTV modes*/
-+#define CV_SMART_DONGLE_ADDRESS 0x20
-+/* DVI-HDMI dongle slave address for retrieving dongle signature*/
-+#define DVI_HDMI_DONGLE_ADDRESS 0x68
-+static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
-+struct dvi_hdmi_dongle_signature_data {
-+	int8_t vendor[3];/* "AMD" */
-+	uint8_t version[2];
-+	uint8_t size;
-+	int8_t id[11];/* "6140063500G"*/
-+};
-+/* DP-HDMI dongle slave address for retrieving dongle signature*/
-+#define DP_HDMI_DONGLE_ADDRESS 0x40
-+static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
-+#define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
-+
-+struct dp_hdmi_dongle_signature_data {
-+	int8_t id[15];/* "DP-HDMI ADAPTOR"*/
-+	uint8_t eot;/* end of transmition '\x4' */
-+};
-+
-+/* Address range from 0x00 to 0x1F.*/
-+#define DP_ADAPTOR_TYPE2_SIZE 0x20
-+#define DP_ADAPTOR_TYPE2_REG_ID 0x10
-+#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
-+/* Identifies adaptor as Dual-mode adaptor */
-+#define DP_ADAPTOR_TYPE2_ID 0xA0
-+/* MHz*/
-+#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
-+/* MHz*/
-+#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
-+/* kHZ*/
-+#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
-+/* kHZ*/
-+#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000
-+
-+#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
-+
-+enum edid_read_result {
-+	EDID_READ_RESULT_EDID_MATCH = 0,
-+	EDID_READ_RESULT_EDID_MISMATCH,
-+	EDID_READ_RESULT_CHECKSUM_READ_ERR,
-+	EDID_READ_RESULT_VENDOR_READ_ERR
-+};
-+
-+/* SCDC Address defines (HDMI 2.0)*/
-+#define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
-+#define HDMI_SCDC_ADDRESS  0x54
-+#define HDMI_SCDC_SINK_VERSION 0x01
-+#define HDMI_SCDC_SOURCE_VERSION 0x02
-+#define HDMI_SCDC_UPDATE_0 0x10
-+#define HDMI_SCDC_TMDS_CONFIG 0x20
-+#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
-+#define HDMI_SCDC_CONFIG_0 0x30
-+#define HDMI_SCDC_STATUS_FLAGS 0x40
-+#define HDMI_SCDC_ERR_DETECT 0x50
-+#define HDMI_SCDC_TEST_CONFIG 0xC0
-+
-+
-+union hdmi_scdc_update_read_data {
-+	uint8_t byte[2];
-+	struct {
-+		uint8_t STATUS_UPDATE:1;
-+		uint8_t CED_UPDATE:1;
-+		uint8_t RR_TEST:1;
-+		uint8_t RESERVED:5;
-+		uint8_t RESERVED2:8;
-+	} fields;
-+};
-+
-+union hdmi_scdc_status_flags_data {
-+	uint8_t byte[2];
-+	struct {
-+		uint8_t CLOCK_DETECTED:1;
-+		uint8_t CH0_LOCKED:1;
-+		uint8_t CH1_LOCKED:1;
-+		uint8_t CH2_LOCKED:1;
-+		uint8_t RESERVED:4;
-+		uint8_t RESERVED2:8;
-+	} fields;
-+};
-+
-+union hdmi_scdc_ced_data {
-+	uint8_t byte[7];
-+	struct {
-+		uint8_t CH0_8LOW:8;
-+		uint8_t CH0_7HIGH:7;
-+		uint8_t CH0_VALID:1;
-+		uint8_t CH1_8LOW:8;
-+		uint8_t CH1_7HIGH:7;
-+		uint8_t CH1_VALID:1;
-+		uint8_t CH2_8LOW:8;
-+		uint8_t CH2_7HIGH:7;
-+		uint8_t CH2_VALID:1;
-+		uint8_t CHECKSUM:8;
-+	} fields;
-+};
-+
-+union hdmi_scdc_test_config_Data {
-+	uint8_t byte;
-+	struct {
-+		uint8_t TEST_READ_REQUEST_DELAY:7;
-+		uint8_t TEST_READ_REQUEST: 1;
-+	} fields;
-+};
-+
-+
-+
-+union ddc_wa {
-+	struct {
-+		uint32_t DP_SKIP_POWER_OFF:1;
-+		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct ddc_flags {
-+	uint8_t EDID_QUERY_DONE_ONCE:1;
-+	uint8_t IS_INTERNAL_DISPLAY:1;
-+	uint8_t FORCE_READ_REPEATED_START:1;
-+	uint8_t EDID_STRESS_READ:1;
-+
-+};
-+
-+struct ddc_service {
-+	struct ddc *ddc_pin;
-+	struct ddc_flags flags;
-+	union ddc_wa wa;
-+	enum ddc_transaction_type transaction_type;
-+	enum display_dongle_type dongle_type;
-+	struct dp_receiver_id_info dp_receiver_id_info;
-+	struct adapter_service *as;
-+	struct dc_context *ctx;
-+
-+	uint32_t address;
-+	uint32_t edid_buf_len;
-+	uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
-+};
-+
-+struct i2c_payloads {
-+	struct vector payloads;
-+};
-+
-+struct aux_payloads {
-+	struct vector payloads;
-+};
-+
-+struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count)
-+{
-+	struct i2c_payloads *payloads;
-+
-+	payloads = dc_service_alloc(ctx, sizeof(struct i2c_payloads));
-+
-+	if (!payloads)
-+		return NULL;
-+
-+	if (dal_vector_construct(
-+		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
-+		return payloads;
-+
-+	dc_service_free(ctx, payloads);
-+	return NULL;
-+
-+}
-+
-+struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
-+{
-+	return (struct i2c_payload *)p->payloads.container;
-+}
-+
-+uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
-+{
-+	return p->payloads.count;
-+}
-+
-+void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
-+{
-+	if (!p || !*p)
-+		return;
-+	dal_vector_destruct(&(*p)->payloads);
-+	dc_service_free((*p)->payloads.ctx, *p);
-+	*p = NULL;
-+
-+}
-+
-+struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
-+{
-+	struct aux_payloads *payloads;
-+
-+	payloads = dc_service_alloc(ctx, sizeof(struct aux_payloads));
-+
-+	if (!payloads)
-+		return NULL;
-+
-+	if (dal_vector_construct(
-+		&payloads->payloads, ctx, count, sizeof(struct aux_payloads)))
-+		return payloads;
-+
-+	dc_service_free(ctx, payloads);
-+	return NULL;
-+}
-+
-+struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
-+{
-+	return (struct aux_payload *)p->payloads.container;
-+}
-+
-+uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
-+{
-+	return p->payloads.count;
-+}
-+
-+
-+void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
-+{
-+	if (!p || !*p)
-+		return;
-+
-+	dal_vector_destruct(&(*p)->payloads);
-+	dc_service_free((*p)->payloads.ctx, *p);
-+	*p = NULL;
-+}
-+
-+#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
-+
-+void dal_ddc_i2c_payloads_add(
-+	struct i2c_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write)
-+{
-+	uint32_t payload_size = EDID_SEGMENT_SIZE;
-+	uint32_t pos;
-+
-+	for (pos = 0; pos < len; pos += payload_size) {
-+		struct i2c_payload payload = {
-+			.write = write,
-+			.address = address,
-+			.length = DDC_MIN(payload_size, len - pos),
-+			.data = data + pos };
-+		dal_vector_append(&payloads->payloads, &payload);
-+	}
-+
-+}
-+
-+void dal_ddc_aux_payloads_add(
-+	struct aux_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write)
-+{
-+	uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
-+	uint32_t pos;
-+
-+	for (pos = 0; pos < len; pos += payload_size) {
-+		struct aux_payload payload = {
-+			.i2c_over_aux = true,
-+			.write = write,
-+			.address = address,
-+			.length = DDC_MIN(payload_size, len - pos),
-+			.data = data + pos };
-+		dal_vector_append(&payloads->payloads, &payload);
-+	}
-+}
-+
-+
-+static bool construct(
-+	struct ddc_service *ddc_service,
-+	struct ddc_service_init_data *init_data)
-+{
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(init_data->id);
-+
-+	ddc_service->ctx = init_data->ctx;
-+	ddc_service->as = init_data->as;
-+	ddc_service->ddc_pin = dal_adapter_service_obtain_ddc(
-+			init_data->as, init_data->id);
-+
-+	ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
-+
-+	ddc_service->flags.FORCE_READ_REPEATED_START =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_DDC_READ_FORCE_REPEATED_START);
-+
-+	ddc_service->flags.EDID_STRESS_READ =
-+			dal_adapter_service_is_feature_supported(
-+				FEATURE_EDID_STRESS_READ);
-+
-+
-+	ddc_service->flags.IS_INTERNAL_DISPLAY =
-+		connector_id == CONNECTOR_ID_EDP ||
-+		connector_id == CONNECTOR_ID_LVDS;
-+
-+	ddc_service->wa.raw = 0;
-+	return true;
-+}
-+
-+struct ddc_service *dal_ddc_service_create(
-+	struct ddc_service_init_data *init_data)
-+{
-+	struct ddc_service *ddc_service;
-+
-+	ddc_service = dc_service_alloc(init_data->ctx, sizeof(struct ddc_service));
-+
-+	if (!ddc_service)
-+		return NULL;
-+
-+	if (construct(ddc_service, init_data))
-+		return ddc_service;
-+
-+	dc_service_free(init_data->ctx, ddc_service);
-+	return NULL;
-+}
-+
-+static void destruct(struct ddc_service *ddc)
-+{
-+	if (ddc->ddc_pin)
-+		dal_adapter_service_release_ddc(ddc->as, ddc->ddc_pin);
-+}
-+
-+void dal_ddc_service_destroy(struct ddc_service **ddc)
-+{
-+	if (!ddc || !*ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+	destruct(*ddc);
-+	dc_service_free((*ddc)->ctx, *ddc);
-+	*ddc = NULL;
-+}
-+
-+enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
-+{
-+	return DDC_SERVICE_TYPE_CONNECTOR;
-+}
-+
-+void dal_ddc_service_set_transaction_type(
-+	struct ddc_service *ddc,
-+	enum ddc_transaction_type type)
-+{
-+	ddc->transaction_type = type;
-+}
-+
-+bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
-+{
-+	switch (ddc->transaction_type) {
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
-+		return true;
-+	default:
-+		break;
-+	}
-+	return false;
-+}
-+
-+void ddc_service_set_dongle_type(struct ddc_service *ddc,
-+		enum display_dongle_type dongle_type)
-+{
-+	ddc->dongle_type = dongle_type;
-+}
-+
-+static uint32_t defer_delay_converter_wa(
-+	struct ddc_service *ddc,
-+	uint32_t defer_delay)
-+{
-+	struct dp_receiver_id_info dp_rec_info = {0};
-+
-+	if (dal_ddc_service_get_dp_receiver_id_info(ddc, &dp_rec_info) &&
-+		(dp_rec_info.branch_id == DP_BRANCH_DEVICE_ID_4) &&
-+		!dal_strncmp(dp_rec_info.branch_name,
-+			DP_DVI_CONVERTER_ID_4,
-+			sizeof(dp_rec_info.branch_name)))
-+		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
-+			defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
-+
-+	return defer_delay;
-+
-+}
-+
-+#define DP_TRANSLATOR_DELAY 5
-+
-+static uint32_t get_defer_delay(struct ddc_service *ddc)
-+{
-+	uint32_t defer_delay = 0;
-+
-+	switch (ddc->transaction_type) {
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
-+		if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
-+			(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
-+			(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
-+				ddc->dongle_type)) {
-+
-+			defer_delay = DP_TRANSLATOR_DELAY;
-+
-+			defer_delay =
-+				defer_delay_converter_wa(ddc, defer_delay);
-+
-+		} else /*sink has a delay different from an Active Converter*/
-+			defer_delay = 0;
-+		break;
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
-+		defer_delay = DP_TRANSLATOR_DELAY;
-+		break;
-+	default:
-+		break;
-+	}
-+	return defer_delay;
-+}
-+
-+static bool i2c_read(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *buffer,
-+	uint32_t len)
-+{
-+	uint8_t offs_data = 0;
-+	struct i2c_payload payloads[2] = {
-+		{
-+		.write = true,
-+		.address = address,
-+		.length = 1,
-+		.data = &offs_data },
-+		{
-+		.write = false,
-+		.address = address,
-+		.length = len,
-+		.data = buffer } };
-+
-+	struct i2c_command command = {
-+		.payloads = payloads,
-+		.number_of_payloads = 2,
-+		.engine = DDC_I2C_COMMAND_ENGINE,
-+		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
-+
-+	return dal_i2caux_submit_i2c_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		&command);
-+}
-+
-+static uint8_t aux_read_edid_block(
-+	struct ddc_service *ddc,
-+	uint8_t address,
-+	uint8_t index,
-+	uint8_t *buf)
-+{
-+	struct aux_command cmd = {
-+		.payloads = NULL,
-+		.number_of_payloads = 0,
-+		.defer_delay = get_defer_delay(ddc),
-+		.max_defer_write_retry = 0 };
-+
-+	uint8_t retrieved = 0;
-+	uint8_t base_offset =
-+		(index % DDC_EDID_BLOCKS_PER_SEGMENT) * DDC_EDID_BLOCK_SIZE;
-+	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
-+
-+	for (retrieved = 0; retrieved < DDC_EDID_BLOCK_SIZE;
-+		retrieved += DEFAULT_AUX_MAX_DATA_SIZE) {
-+
-+		uint8_t offset = base_offset + retrieved;
-+
-+		struct aux_payload payloads[3] = {
-+			{
-+			.i2c_over_aux = true,
-+			.write = true,
-+			.address = DDC_EDID_SEGMENT_ADDRESS,
-+			.length = 1,
-+			.data = &segment },
-+			{
-+			.i2c_over_aux = true,
-+			.write = true,
-+			.address = address,
-+			.length = 1,
-+			.data = &offset },
-+			{
-+			.i2c_over_aux = true,
-+			.write = false,
-+			.address = address,
-+			.length = DEFAULT_AUX_MAX_DATA_SIZE,
-+			.data = &buf[retrieved] } };
-+
-+		if (segment == 0) {
-+			cmd.payloads = &payloads[1];
-+			cmd.number_of_payloads = 2;
-+		} else {
-+			cmd.payloads = payloads;
-+			cmd.number_of_payloads = 3;
-+		}
-+
-+		if (!dal_i2caux_submit_aux_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd))
-+			/* cannot read, break*/
-+			break;
-+	}
-+
-+	/* Reset segment to 0. Needed by some panels */
-+	if (0 != segment) {
-+		struct aux_payload payloads[1] = { {
-+			.i2c_over_aux = true,
-+			.write = true,
-+			.address = DDC_EDID_SEGMENT_ADDRESS,
-+			.length = 1,
-+			.data = &segment } };
-+		bool result = false;
-+
-+		segment = 0;
-+
-+		cmd.number_of_payloads = ARRAY_SIZE(payloads);
-+		cmd.payloads = payloads;
-+
-+		result = dal_i2caux_submit_aux_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd);
-+
-+		if (false == result)
-+			dal_logger_write(
-+				ddc->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
-+				"%s: Writing of EDID Segment (0x30) failed!\n",
-+				__func__);
-+	}
-+
-+	return retrieved;
-+}
-+
-+static uint8_t i2c_read_edid_block(
-+	struct ddc_service *ddc,
-+	uint8_t address,
-+	uint8_t index,
-+	uint8_t *buf)
-+{
-+	bool ret = false;
-+	uint8_t offset = (index % DDC_EDID_BLOCKS_PER_SEGMENT) *
-+		DDC_EDID_BLOCK_SIZE;
-+	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
-+
-+	struct i2c_command cmd = {
-+		.payloads = NULL,
-+		.number_of_payloads = 0,
-+		.engine = DDC_I2C_COMMAND_ENGINE,
-+		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
-+
-+	struct i2c_payload payloads[3] = {
-+		{
-+		.write = true,
-+		.address = DDC_EDID_SEGMENT_ADDRESS,
-+		.length = 1,
-+		.data = &segment },
-+		{
-+		.write = true,
-+		.address = address,
-+		.length = 1,
-+		.data = &offset },
-+		{
-+		.write = false,
-+		.address = address,
-+		.length = DDC_EDID_BLOCK_SIZE,
-+		.data = buf } };
-+/*
-+ * Some I2C engines don't handle stop/start between write-offset and read-data
-+ * commands properly. For those displays, we have to force the newer E-DDC
-+ * behavior of repeated-start which can be enabled by runtime parameter. */
-+/* Originally implemented for OnLive using NXP receiver chip */
-+
-+	if (index == 0 && !ddc->flags.FORCE_READ_REPEATED_START) {
-+		/* base block, use use DDC2B, submit as 2 commands */
-+		cmd.payloads = &payloads[1];
-+		cmd.number_of_payloads = 1;
-+
-+		if (dal_i2caux_submit_i2c_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd)) {
-+
-+			cmd.payloads = &payloads[2];
-+			cmd.number_of_payloads = 1;
-+
-+			ret = dal_i2caux_submit_i2c_command(
-+				dal_adapter_service_get_i2caux(ddc->as),
-+				ddc->ddc_pin,
-+				&cmd);
-+		}
-+
-+	} else {
-+		/*
-+		 * extension block use E-DDC, submit as 1 command
-+		 * or if repeated-start is forced by runtime parameter
-+		 */
-+		if (segment != 0) {
-+			/* include segment offset in command*/
-+			cmd.payloads = payloads;
-+			cmd.number_of_payloads = 3;
-+		} else {
-+			/* we are reading first segment,
-+			 * segment offset is not required */
-+			cmd.payloads = &payloads[1];
-+			cmd.number_of_payloads = 2;
-+		}
-+
-+		ret = dal_i2caux_submit_i2c_command(
-+			dal_adapter_service_get_i2caux(ddc->as),
-+			ddc->ddc_pin,
-+			&cmd);
-+	}
-+
-+	return ret ? DDC_EDID_BLOCK_SIZE : 0;
-+}
-+
-+static uint32_t query_edid_block(
-+	struct ddc_service *ddc,
-+	uint8_t address,
-+	uint8_t index,
-+	uint8_t *buf,
-+	uint32_t size)
-+{
-+	uint32_t size_retrieved = 0;
-+
-+	if (size < DDC_EDID_BLOCK_SIZE)
-+		return 0;
-+
-+	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-+
-+		ASSERT(index < 2);
-+		size_retrieved =
-+			aux_read_edid_block(ddc, address, index, buf);
-+	} else {
-+		size_retrieved =
-+			i2c_read_edid_block(ddc, address, index, buf);
-+	}
-+
-+	return size_retrieved;
-+}
-+
-+#define DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS 0x261
-+#define DDC_TEST_ACK_ADDRESS 0x260
-+#define DDC_DPCD_EDID_TEST_ACK 0x04
-+#define DDC_DPCD_EDID_TEST_MASK 0x04
-+#define DDC_DPCD_TEST_REQUEST_ADDRESS 0x218
-+
-+/* AG TODO GO throug DM callback here like for DPCD */
-+
-+static void write_dp_edid_checksum(
-+	struct ddc_service *ddc,
-+	uint8_t checksum)
-+{
-+	uint8_t dpcd_data;
-+
-+	dal_ddc_service_read_dpcd_data(
-+		ddc,
-+		DDC_DPCD_TEST_REQUEST_ADDRESS,
-+		&dpcd_data,
-+		1);
-+
-+	if (dpcd_data & DDC_DPCD_EDID_TEST_MASK) {
-+
-+		dal_ddc_service_write_dpcd_data(
-+			ddc,
-+			DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS,
-+			&checksum,
-+			1);
-+
-+		dpcd_data = DDC_DPCD_EDID_TEST_ACK;
-+
-+		dal_ddc_service_write_dpcd_data(
-+			ddc,
-+			DDC_TEST_ACK_ADDRESS,
-+			&dpcd_data,
-+			1);
-+	}
-+}
-+
-+uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc)
-+{
-+	uint32_t bytes_read = 0;
-+	uint32_t ext_cnt = 0;
-+
-+	uint8_t address;
-+	uint32_t i;
-+
-+	for (address = DDC_EDID_ADDRESS_START;
-+		address <= DDC_EDID_ADDRESS_END; ++address) {
-+
-+		bytes_read = query_edid_block(
-+			ddc,
-+			address,
-+			0,
-+			ddc->edid_buf,
-+			sizeof(ddc->edid_buf) - bytes_read);
-+
-+		if (bytes_read != DDC_EDID_BLOCK_SIZE)
-+			continue;
-+
-+		/* get the number of ext blocks*/
-+		ext_cnt = ddc->edid_buf[DDC_EDID_EXT_COUNT_OFFSET];
-+
-+		/* EDID 2.0, need to read 1 more block because EDID2.0 is
-+		 * 256 byte in size*/
-+		if (ddc->edid_buf[DDC_EDID_20_SIGNATURE_OFFSET] ==
-+			DDC_EDID_20_SIGNATURE)
-+				ext_cnt = 1;
-+
-+		for (i = 0; i < ext_cnt; i++) {
-+			/* read additional ext blocks accordingly */
-+			bytes_read += query_edid_block(
-+					ddc,
-+					address,
-+					i+1,
-+					&ddc->edid_buf[bytes_read],
-+					sizeof(ddc->edid_buf) - bytes_read);
-+		}
-+
-+		/*this is special code path for DP compliance*/
-+		if (DDC_TRANSACTION_TYPE_I2C_OVER_AUX == ddc->transaction_type)
-+			write_dp_edid_checksum(
-+				ddc,
-+				ddc->edid_buf[(ext_cnt * DDC_EDID_BLOCK_SIZE) +
-+				DDC_EDID1X_CHECKSUM_OFFSET]);
-+
-+		/*remembers the address where we fetch the EDID from
-+		 * for later signature check use */
-+		ddc->address = address;
-+
-+		break;/* already read edid, done*/
-+	}
-+
-+	ddc->edid_buf_len = bytes_read;
-+	return bytes_read;
-+}
-+
-+uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc)
-+{
-+	return ddc->edid_buf_len;
-+}
-+
-+void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf)
-+{
-+	dc_service_memmove(edid_buf,
-+			ddc->edid_buf, ddc->edid_buf_len);
-+}
-+
-+void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+	struct ddc_service *ddc,
-+	struct display_sink_capability *sink_cap)
-+{
-+	uint8_t i;
-+	bool is_valid_hdmi_signature;
-+	enum display_dongle_type *dongle = &sink_cap->dongle_type;
-+	uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
-+	bool is_type2_dongle = false;
-+	struct dp_hdmi_dongle_signature_data *dongle_signature;
-+
-+	/* Assume we have no valid DP passive dongle connected */
-+	*dongle = DISPLAY_DONGLE_NONE;
-+	sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
-+
-+	/* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
-+	if (!i2c_read(
-+		ddc,
-+		DP_HDMI_DONGLE_ADDRESS,
-+		type2_dongle_buf,
-+		sizeof(type2_dongle_buf))) {
-+		dal_logger_write(ddc->ctx->logger,
-+			LOG_MAJOR_DCS,
-+			LOG_MINOR_DCS_DONGLE_DETECTION,
-+			"Detected DP-DVI dongle.\n");
-+		*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+		sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
-+		return;
-+	}
-+
-+	/* Check if Type 2 dongle.*/
-+	if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
-+		is_type2_dongle = true;
-+
-+	dongle_signature =
-+		(struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
-+
-+	is_valid_hdmi_signature = true;
-+
-+	/* Check EOT */
-+	if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
-+		is_valid_hdmi_signature = false;
-+	}
-+
-+	/* Check signature */
-+	for (i = 0; i < sizeof(dongle_signature->id); ++i) {
-+		/* If its not the right signature,
-+		 * skip mismatch in subversion byte.*/
-+		if (dongle_signature->id[i] !=
-+			dp_hdmi_dongle_signature_str[i] && i != 3) {
-+
-+			if (is_type2_dongle) {
-+				is_valid_hdmi_signature = false;
-+				break;
-+			}
-+
-+		}
-+	}
-+
-+	if (is_type2_dongle) {
-+		uint32_t max_tmds_clk =
-+			type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
-+
-+		max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
-+
-+		if (0 == max_tmds_clk ||
-+				max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
-+				max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
-+			dal_logger_write(ddc->ctx->logger,
-+				LOG_MAJOR_DCS,
-+				LOG_MINOR_DCS_DONGLE_DETECTION,
-+				"Invalid Maximum TMDS clock");
-+			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+		} else {
-+			if (is_valid_hdmi_signature == true) {
-+				*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
-+				dal_logger_write(ddc->ctx->logger,
-+					LOG_MAJOR_DCS,
-+					LOG_MINOR_DCS_DONGLE_DETECTION,
-+					"Detected Type 2 DP-HDMI Maximum TMDS "
-+					"clock, max TMDS clock: %d MHz",
-+					max_tmds_clk);
-+			} else {
-+				*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+				dal_logger_write(ddc->ctx->logger,
-+					LOG_MAJOR_DCS,
-+					LOG_MINOR_DCS_DONGLE_DETECTION,
-+					"Detected Type 2 DP-HDMI (no valid HDMI"
-+					" signature) Maximum TMDS clock, max "
-+					"TMDS clock: %d MHz",
-+					max_tmds_clk);
-+			}
-+
-+			/* Multiply by 1000 to convert to kHz. */
-+			sink_cap->max_hdmi_pixel_clock =
-+				max_tmds_clk * 1000;
-+		}
-+
-+	} else {
-+		if (is_valid_hdmi_signature == true) {
-+			dal_logger_write(ddc->ctx->logger,
-+				LOG_MAJOR_DCS,
-+				LOG_MINOR_DCS_DONGLE_DETECTION,
-+				"Detected Type 1 DP-HDMI dongle.\n");
-+			*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
-+		} else {
-+			dal_logger_write(ddc->ctx->logger,
-+				LOG_MAJOR_DCS,
-+				LOG_MINOR_DCS_DONGLE_DETECTION,
-+				"Detected Type 1 DP-HDMI dongle (no valid HDMI "
-+				"signature).\n");
-+
-+			*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+		}
-+	}
-+
-+	return;
-+}
-+
-+enum {
-+	DP_SINK_CAP_SIZE =
-+		DPCD_ADDRESS_EDP_CONFIG_CAP - DPCD_ADDRESS_DPCD_REV + 1
-+};
-+
-+bool dal_ddc_service_query_ddc_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *write_buf,
-+	uint32_t write_size,
-+	uint8_t *read_buf,
-+	uint32_t read_size)
-+{
-+	bool ret;
-+	uint32_t payload_size =
-+		dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
-+			DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
-+
-+	uint32_t write_payloads =
-+		(write_size + payload_size - 1) / payload_size;
-+
-+	uint32_t read_payloads =
-+		(read_size + payload_size - 1) / payload_size;
-+
-+	uint32_t payloads_num = write_payloads + read_payloads;
-+
-+	if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
-+		return false;
-+
-+	/*TODO: len of payload data for i2c and aux is uint8!!!!,
-+	 *  but we want to read 256 over i2c!!!!*/
-+	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-+
-+		struct aux_payloads *payloads =
-+			dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
-+
-+		struct aux_command command = {
-+			.payloads = dal_ddc_aux_payloads_get(payloads),
-+			.number_of_payloads = 0,
-+			.defer_delay = get_defer_delay(ddc),
-+			.max_defer_write_retry = 0 };
-+
-+		dal_ddc_aux_payloads_add(
-+			payloads, address, write_size, write_buf, true);
-+
-+		dal_ddc_aux_payloads_add(
-+			payloads, address, read_size, read_buf, false);
-+
-+		command.number_of_payloads =
-+			dal_ddc_aux_payloads_get_count(payloads);
-+
-+		ret = dal_i2caux_submit_aux_command(
-+				dal_adapter_service_get_i2caux(ddc->as),
-+				ddc->ddc_pin,
-+				&command);
-+
-+		dal_ddc_aux_payloads_destroy(&payloads);
-+
-+	} else {
-+		struct i2c_payloads *payloads =
-+			dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
-+
-+		struct i2c_command command = {
-+			.payloads = dal_ddc_i2c_payloads_get(payloads),
-+			.number_of_payloads = 0,
-+			.engine = DDC_I2C_COMMAND_ENGINE,
-+			.speed =
-+				dal_adapter_service_get_sw_i2c_speed(ddc->as) };
-+
-+		dal_ddc_i2c_payloads_add(
-+			payloads, address, write_size, write_buf, true);
-+
-+		dal_ddc_i2c_payloads_add(
-+			payloads, address, read_size, read_buf, false);
-+
-+		command.number_of_payloads =
-+			dal_ddc_i2c_payloads_get_count(payloads);
-+
-+		ret = dal_i2caux_submit_i2c_command(
-+				dal_adapter_service_get_i2caux(ddc->as),
-+				ddc->ddc_pin,
-+				&command);
-+
-+		dal_ddc_i2c_payloads_destroy(&payloads);
-+	}
-+
-+	return ret;
-+}
-+
-+bool dal_ddc_service_get_dp_receiver_id_info(
-+	struct ddc_service *ddc,
-+	struct dp_receiver_id_info *info)
-+{
-+	if (!info)
-+		return false;
-+
-+	*info = ddc->dp_receiver_id_info;
-+	return true;
-+}
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t len)
-+{
-+	struct aux_payload read_payload = {
-+		.i2c_over_aux = false,
-+		.write = false,
-+		.address = address,
-+		.length = len,
-+		.data = data,
-+	};
-+	struct aux_command command = {
-+		.payloads = &read_payload,
-+		.number_of_payloads = 1,
-+		.defer_delay = 0,
-+		.max_defer_write_retry = 0,
-+	};
-+
-+	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
-+		BREAK_TO_DEBUGGER();
-+		return DDC_RESULT_FAILED_INVALID_OPERATION;
-+	}
-+
-+	if (dal_i2caux_submit_aux_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		&command))
-+		return DDC_RESULT_SUCESSFULL;
-+
-+	return DDC_RESULT_FAILED_OPERATION;
-+}
-+
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t len)
-+{
-+	struct aux_payload write_payload = {
-+		.i2c_over_aux = false,
-+		.write = true,
-+		.address = address,
-+		.length = len,
-+		.data = (uint8_t *)data,
-+	};
-+	struct aux_command command = {
-+		.payloads = &write_payload,
-+		.number_of_payloads = 1,
-+		.defer_delay = 0,
-+		.max_defer_write_retry = 0,
-+	};
-+
-+	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
-+		BREAK_TO_DEBUGGER();
-+		return DDC_RESULT_FAILED_INVALID_OPERATION;
-+	}
-+
-+	if (dal_i2caux_submit_aux_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		&command))
-+		return DDC_RESULT_SUCESSFULL;
-+
-+	return DDC_RESULT_FAILED_OPERATION;
-+}
-+
-+/*test only function*/
-+void dal_ddc_service_set_ddc_pin(
-+	struct ddc_service *ddc_service,
-+	struct ddc *ddc)
-+{
-+	ddc_service->ddc_pin = ddc;
-+}
-+
-+struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
-+{
-+	return ddc_service->ddc_pin;
-+}
-+
-+
-+void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
-+{
-+	dc_service_memset(&ddc_service->dp_receiver_id_info,
-+		0, sizeof(struct dp_receiver_id_info));
-+}
-+
-+void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
-+		uint32_t pix_clk,
-+		bool lte_340_scramble)
-+{
-+	bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
-+	uint8_t slave_address = HDMI_SCDC_ADDRESS;
-+	uint8_t offset = HDMI_SCDC_SINK_VERSION;
-+	uint8_t sink_version = 0;
-+	uint8_t write_buffer[2] = {0};
-+	/*Lower than 340 Scramble bit from SCDC caps*/
-+
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
-+			sizeof(offset), &sink_version, sizeof(sink_version));
-+	if (sink_version == 1) {
-+		/*Source Version = 1*/
-+		write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
-+		write_buffer[1] = 1;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				write_buffer, sizeof(write_buffer), NULL, 0);
-+		/*Read Request from SCDC caps*/
-+	}
-+	write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
-+
-+	if (over_340_mhz) {
-+		write_buffer[1] = 3;
-+	} else if (lte_340_scramble) {
-+		write_buffer[1] = 1;
-+	} else {
-+		write_buffer[1] = 0;
-+	}
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
-+			sizeof(write_buffer), NULL, 0);
-+}
-+
-+void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
-+{
-+	uint8_t slave_address = HDMI_SCDC_ADDRESS;
-+	uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
-+	uint8_t tmds_config = 0;
-+
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
-+			sizeof(offset), &tmds_config, sizeof(tmds_config));
-+	if (tmds_config & 0x1) {
-+		union hdmi_scdc_status_flags_data status_data = { {0} };
-+		uint8_t scramble_status = 0;
-+
-+		offset = HDMI_SCDC_SCRAMBLER_STATUS;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				&offset, sizeof(offset), &scramble_status,
-+				sizeof(scramble_status));
-+		offset = HDMI_SCDC_STATUS_FLAGS;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				&offset, sizeof(offset), status_data.byte,
-+				sizeof(status_data.byte));
-+	}
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index c4cbede..96ba910 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -5,7 +5,7 @@
- #include "dc_helpers.h"
- #include "inc/core_types.h"
- #include "link_hwss.h"
--#include "ddc_service_interface.h"
-+#include "dc_link_ddc.h"
- #include "core_status.h"
- #include "dpcd_defs.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 2ed9eb8..656ec71 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -7,7 +7,7 @@
- #include "include/i2caux_interface.h"
- #include "link_hwss.h"
- #include "hw_sequencer.h"
--#include "include/ddc_service_interface.h"
-+#include "dc_link_ddc.h"
- #include "dc_helpers.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_stream_encoder.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/Makefile b/drivers/gpu/drm/amd/dal/dc/dcs/Makefile
-deleted file mode 100644
-index a266942..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dcs/Makefile
-+++ /dev/null
-@@ -1,10 +0,0 @@
--#
--# Makefile for the 'gpu' sub-component of DAL.
--# It provides the control and status of HW adapter resources,
--# that are global for the ASIC and sharable between pipes.
--
--DCS = ddc_service.o ddc_i2caux_helper.o
--
--AMD_DAL_DCS = $(addprefix $(AMDDALPATH)/dc/dcs/,$(DCS))
--
--AMD_DAL_FILES += $(AMD_DAL_DCS)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-deleted file mode 100644
-index 0af4df6..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.c
-+++ /dev/null
-@@ -1,159 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--#include "ddc_i2caux_helper.h"
--#include "include/ddc_service_types.h"
--#include "include/vector.h"
--
--struct i2c_payloads {
--	struct vector payloads;
--};
--
--struct aux_payloads {
--	struct vector payloads;
--};
--
--struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count)
--{
--	struct i2c_payloads *payloads;
--
--	payloads = dc_service_alloc(ctx, sizeof(struct i2c_payloads));
--
--	if (!payloads)
--		return NULL;
--
--	if (dal_vector_construct(
--		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
--		return payloads;
--
--	dc_service_free(ctx, payloads);
--	return NULL;
--
--}
--
--struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
--{
--	return (struct i2c_payload *)p->payloads.container;
--}
--
--uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
--{
--	return p->payloads.count;
--}
--
--void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
--{
--	if (!p || !*p)
--		return;
--	dal_vector_destruct(&(*p)->payloads);
--	dc_service_free((*p)->payloads.ctx, *p);
--	*p = NULL;
--
--}
--
--struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
--{
--	struct aux_payloads *payloads;
--
--	payloads = dc_service_alloc(ctx, sizeof(struct aux_payloads));
--
--	if (!payloads)
--		return NULL;
--
--	if (dal_vector_construct(
--		&payloads->payloads, ctx, count, sizeof(struct aux_payloads)))
--		return payloads;
--
--	dc_service_free(ctx, payloads);
--	return NULL;
--}
--
--struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
--{
--	return (struct aux_payload *)p->payloads.container;
--}
--
--uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
--{
--	return p->payloads.count;
--}
--
--
--void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
--{
--	if (!p || !*p)
--		return;
--
--	dal_vector_destruct(&(*p)->payloads);
--	dc_service_free((*p)->payloads.ctx, *p);
--	*p = NULL;
--}
--
--#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
--
--void dal_ddc_i2c_payloads_add(
--	struct i2c_payloads *payloads,
--	uint32_t address,
--	uint32_t len,
--	uint8_t *data,
--	bool write)
--{
--	uint32_t payload_size = EDID_SEGMENT_SIZE;
--	uint32_t pos;
--
--	for (pos = 0; pos < len; pos += payload_size) {
--		struct i2c_payload payload = {
--			.write = write,
--			.address = address,
--			.length = DDC_MIN(payload_size, len - pos),
--			.data = data + pos };
--		dal_vector_append(&payloads->payloads, &payload);
--	}
--
--}
--
--void dal_ddc_aux_payloads_add(
--	struct aux_payloads *payloads,
--	uint32_t address,
--	uint32_t len,
--	uint8_t *data,
--	bool write)
--{
--	uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
--	uint32_t pos;
--
--	for (pos = 0; pos < len; pos += payload_size) {
--		struct aux_payload payload = {
--			.i2c_over_aux = true,
--			.write = write,
--			.address = address,
--			.length = DDC_MIN(payload_size, len - pos),
--			.data = data + pos };
--		dal_vector_append(&payloads->payloads, &payload);
--	}
--}
--
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
-deleted file mode 100644
-index bb628cd..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_i2caux_helper.h
-+++ /dev/null
-@@ -1,60 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_I2CAUX_HELPER_H__
--#define __DAL_I2CAUX_HELPER_H__
--
--#include "include/i2caux_interface.h"
--
--#define EDID_SEGMENT_SIZE 256
--
--struct i2c_payloads;
--struct aux_payloads;
--
--struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count);
--struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p);
--uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p);
--void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p);
--
--struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count);
--struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p);
--uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p);
--void dal_ddc_aux_payloads_destroy(struct aux_payloads **p);
--
--void dal_ddc_i2c_payloads_add(
--	struct i2c_payloads *payloads,
--	uint32_t address,
--	uint32_t len,
--	uint8_t *data,
--	bool write);
--
--void dal_ddc_aux_payloads_add(
--	struct aux_payloads *payloads,
--	uint32_t address,
--	uint32_t len,
--	uint8_t *data,
--	bool write);
--
--#endif /* __DAL_I2CAUX_HELPER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-deleted file mode 100644
-index bbab51c..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.c
-+++ /dev/null
-@@ -1,1036 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--
--#include "include/adapter_service_interface.h"
--#include "include/i2caux_interface.h"
--#include "include/ddc_service_interface.h"
--#include "include/ddc_service_types.h"
--#include "include/grph_object_id.h"
--#include "include/dpcd_defs.h"
--#include "include/logger_interface.h"
--#include "ddc_i2caux_helper.h"
--#include "ddc_service.h"
--
--#define AUX_POWER_UP_WA_DELAY 500
--#define I2C_OVER_AUX_DEFER_WA_DELAY 70
--
--/* CV smart dongle slave address for retrieving supported HDTV modes*/
--#define CV_SMART_DONGLE_ADDRESS 0x20
--/* DVI-HDMI dongle slave address for retrieving dongle signature*/
--#define DVI_HDMI_DONGLE_ADDRESS 0x68
--static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
--struct dvi_hdmi_dongle_signature_data {
--	int8_t vendor[3];/* "AMD" */
--	uint8_t version[2];
--	uint8_t size;
--	int8_t id[11];/* "6140063500G"*/
--};
--/* DP-HDMI dongle slave address for retrieving dongle signature*/
--#define DP_HDMI_DONGLE_ADDRESS 0x40
--static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
--#define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
--
--struct dp_hdmi_dongle_signature_data {
--	int8_t id[15];/* "DP-HDMI ADAPTOR"*/
--	uint8_t eot;/* end of transmition '\x4' */
--};
--
--/* Address range from 0x00 to 0x1F.*/
--#define DP_ADAPTOR_TYPE2_SIZE 0x20
--#define DP_ADAPTOR_TYPE2_REG_ID 0x10
--#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
--/* Identifies adaptor as Dual-mode adaptor */
--#define DP_ADAPTOR_TYPE2_ID 0xA0
--/* MHz*/
--#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
--/* MHz*/
--#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
--/* kHZ*/
--#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
--/* kHZ*/
--#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000
--
--#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
--
--enum edid_read_result {
--	EDID_READ_RESULT_EDID_MATCH = 0,
--	EDID_READ_RESULT_EDID_MISMATCH,
--	EDID_READ_RESULT_CHECKSUM_READ_ERR,
--	EDID_READ_RESULT_VENDOR_READ_ERR
--};
--
--/* SCDC Address defines (HDMI 2.0)*/
--#define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
--#define HDMI_SCDC_ADDRESS  0x54
--#define HDMI_SCDC_SINK_VERSION 0x01
--#define HDMI_SCDC_SOURCE_VERSION 0x02
--#define HDMI_SCDC_UPDATE_0 0x10
--#define HDMI_SCDC_TMDS_CONFIG 0x20
--#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
--#define HDMI_SCDC_CONFIG_0 0x30
--#define HDMI_SCDC_STATUS_FLAGS 0x40
--#define HDMI_SCDC_ERR_DETECT 0x50
--#define HDMI_SCDC_TEST_CONFIG 0xC0
--
--
--union hdmi_scdc_update_read_data
--{
--	uint8_t byte[2];
--    struct
--    {
--        uint8_t STATUS_UPDATE:1;
--        uint8_t CED_UPDATE:1;
--        uint8_t RR_TEST:1;
--        uint8_t RESERVED:5;
--		uint8_t RESERVED2:8;
--    } fields; 
--};
--
--union hdmi_scdc_status_flags_data
--{
--    uint8_t byte[2];
--    struct
--    {
--        uint8_t CLOCK_DETECTED:1;
--        uint8_t CH0_LOCKED:1;
--        uint8_t CH1_LOCKED:1;
--        uint8_t CH2_LOCKED:1;
--        uint8_t RESERVED:4;
--		uint8_t RESERVED2:8;
--    } fields;
--};
--
--union hdmi_scdc_ced_data
--{
--    uint8_t byte[7];
--    struct
--    {
--        uint8_t CH0_8LOW:8;
--        uint8_t CH0_7HIGH:7;
--        uint8_t CH0_VALID:1;
--        uint8_t CH1_8LOW:8;
--        uint8_t CH1_7HIGH:7;
--        uint8_t CH1_VALID:1;
--        uint8_t CH2_8LOW:8;
--        uint8_t CH2_7HIGH:7;
--        uint8_t CH2_VALID:1;
--        uint8_t CHECKSUM:8;
--    } fields;
--};
--
--union hdmi_scdc_test_config_Data
--{
--    uint8_t byte;
--    struct
--    {
--        uint8_t TEST_READ_REQUEST_DELAY:7;
--        uint8_t TEST_READ_REQUEST: 1;
--    } fields;
--};
--
--
--
--union ddc_wa {
--	struct {
--		uint32_t DP_SKIP_POWER_OFF:1;
--		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
--	} bits;
--	uint32_t raw;
--};
--
--struct ddc_flags {
--	uint8_t EDID_QUERY_DONE_ONCE:1;
--	uint8_t IS_INTERNAL_DISPLAY:1;
--	uint8_t FORCE_READ_REPEATED_START:1;
--	uint8_t EDID_STRESS_READ:1;
--
--};
--
--struct ddc_service {
--	struct ddc *ddc_pin;
--	struct ddc_flags flags;
--	union ddc_wa wa;
--	enum ddc_transaction_type transaction_type;
--	enum display_dongle_type dongle_type;
--	struct dp_receiver_id_info dp_receiver_id_info;
--	struct adapter_service *as;
--	struct dc_context *ctx;
--
--	uint32_t address;
--	uint32_t edid_buf_len;
--	uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
--};
--
--static bool construct(
--	struct ddc_service *ddc_service,
--	struct ddc_service_init_data *init_data)
--{
--	enum connector_id connector_id =
--		dal_graphics_object_id_get_connector_id(init_data->id);
--
--	ddc_service->ctx = init_data->ctx;
--	ddc_service->as = init_data->as;
--	ddc_service->ddc_pin = dal_adapter_service_obtain_ddc(
--			init_data->as, init_data->id);
--
--	ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
--
--	ddc_service->flags.FORCE_READ_REPEATED_START =
--		dal_adapter_service_is_feature_supported(
--			FEATURE_DDC_READ_FORCE_REPEATED_START);
--
--	ddc_service->flags.EDID_STRESS_READ =
--			dal_adapter_service_is_feature_supported(
--				FEATURE_EDID_STRESS_READ);
--
--
--	ddc_service->flags.IS_INTERNAL_DISPLAY =
--		connector_id == CONNECTOR_ID_EDP ||
--		connector_id == CONNECTOR_ID_LVDS;
--
--	ddc_service->wa.raw = 0;
--	return true;
--}
--
--struct ddc_service *dal_ddc_service_create(
--	struct ddc_service_init_data *init_data)
--{
--	struct ddc_service *ddc_service;
--
--	ddc_service = dc_service_alloc(init_data->ctx, sizeof(struct ddc_service));
--
--	if (!ddc_service)
--		return NULL;
--
--	if (construct(ddc_service, init_data))
--		return ddc_service;
--
--	dc_service_free(init_data->ctx, ddc_service);
--	return NULL;
--}
--
--static void destruct(struct ddc_service *ddc)
--{
--	if (ddc->ddc_pin)
--		dal_adapter_service_release_ddc(ddc->as, ddc->ddc_pin);
--}
--
--void dal_ddc_service_destroy(struct ddc_service **ddc)
--{
--	if (!ddc || !*ddc) {
--		BREAK_TO_DEBUGGER();
--		return;
--	}
--	destruct(*ddc);
--	dc_service_free((*ddc)->ctx, *ddc);
--	*ddc = NULL;
--}
--
--enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
--{
--	return DDC_SERVICE_TYPE_CONNECTOR;
--}
--
--void dal_ddc_service_set_transaction_type(
--	struct ddc_service *ddc,
--	enum ddc_transaction_type type)
--{
--	ddc->transaction_type = type;
--}
--
--bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
--{
--	switch (ddc->transaction_type) {
--	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
--	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
--	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
--		return true;
--	default:
--		break;
--	}
--	return false;
--}
--
--void ddc_service_set_dongle_type(struct ddc_service *ddc,
--		enum display_dongle_type dongle_type)
--{
--	ddc->dongle_type = dongle_type;
--}
--
--static uint32_t defer_delay_converter_wa(
--	struct ddc_service *ddc,
--	uint32_t defer_delay)
--{
--	struct dp_receiver_id_info dp_rec_info = {0};
--
--	if (dal_ddc_service_get_dp_receiver_id_info(ddc, &dp_rec_info) &&
--		(dp_rec_info.branch_id == DP_BRANCH_DEVICE_ID_4) &&
--		!dal_strncmp(dp_rec_info.branch_name,
--			DP_DVI_CONVERTER_ID_4,
--			sizeof(dp_rec_info.branch_name)))
--		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
--			defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
--
--	return defer_delay;
--
--}
--
--#define DP_TRANSLATOR_DELAY 5
--
--static uint32_t get_defer_delay(struct ddc_service *ddc)
--{
--	uint32_t defer_delay = 0;
--
--	switch (ddc->transaction_type) {
--	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
--		if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
--			(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
--			(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
--				ddc->dongle_type)) {
--
--			defer_delay = DP_TRANSLATOR_DELAY;
--
--			defer_delay =
--				defer_delay_converter_wa(ddc, defer_delay);
--
--		} else /*sink has a delay different from an Active Converter*/
--			defer_delay = 0;
--		break;
--	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
--		defer_delay = DP_TRANSLATOR_DELAY;
--		break;
--	default:
--		break;
--	}
--	return defer_delay;
--}
--
--static bool i2c_read(
--	struct ddc_service *ddc,
--	uint32_t address,
--	uint8_t *buffer,
--	uint32_t len)
--{
--	uint8_t offs_data = 0;
--	struct i2c_payload payloads[2] = {
--		{
--		.write = true,
--		.address = address,
--		.length = 1,
--		.data = &offs_data },
--		{
--		.write = false,
--		.address = address,
--		.length = len,
--		.data = buffer } };
--
--	struct i2c_command command = {
--		.payloads = payloads,
--		.number_of_payloads = 2,
--		.engine = DDC_I2C_COMMAND_ENGINE,
--		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
--
--	return dal_i2caux_submit_i2c_command(
--		dal_adapter_service_get_i2caux(ddc->as),
--		ddc->ddc_pin,
--		&command);
--}
--
--static uint8_t aux_read_edid_block(
--	struct ddc_service *ddc,
--	uint8_t address,
--	uint8_t index,
--	uint8_t *buf)
--{
--	struct aux_command cmd = {
--		.payloads = NULL,
--		.number_of_payloads = 0,
--		.defer_delay = get_defer_delay(ddc),
--		.max_defer_write_retry = 0 };
--
--	uint8_t retrieved = 0;
--	uint8_t base_offset =
--		(index % DDC_EDID_BLOCKS_PER_SEGMENT) * DDC_EDID_BLOCK_SIZE;
--	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
--
--	for (retrieved = 0; retrieved < DDC_EDID_BLOCK_SIZE;
--		retrieved += DEFAULT_AUX_MAX_DATA_SIZE) {
--
--		uint8_t offset = base_offset + retrieved;
--
--		struct aux_payload payloads[3] = {
--			{
--			.i2c_over_aux = true,
--			.write = true,
--			.address = DDC_EDID_SEGMENT_ADDRESS,
--			.length = 1,
--			.data = &segment },
--			{
--			.i2c_over_aux = true,
--			.write = true,
--			.address = address,
--			.length = 1,
--			.data = &offset },
--			{
--			.i2c_over_aux = true,
--			.write = false,
--			.address = address,
--			.length = DEFAULT_AUX_MAX_DATA_SIZE,
--			.data = &buf[retrieved] } };
--
--		if (segment == 0) {
--			cmd.payloads = &payloads[1];
--			cmd.number_of_payloads = 2;
--		} else {
--			cmd.payloads = payloads;
--			cmd.number_of_payloads = 3;
--		}
--
--		if (!dal_i2caux_submit_aux_command(
--			dal_adapter_service_get_i2caux(ddc->as),
--			ddc->ddc_pin,
--			&cmd))
--			/* cannot read, break*/
--			break;
--	}
--
--	/* Reset segment to 0. Needed by some panels */
--	if (0 != segment) {
--		struct aux_payload payloads[1] = { {
--			.i2c_over_aux = true,
--			.write = true,
--			.address = DDC_EDID_SEGMENT_ADDRESS,
--			.length = 1,
--			.data = &segment } };
--		bool result = false;
--
--		segment = 0;
--
--		cmd.number_of_payloads = ARRAY_SIZE(payloads);
--		cmd.payloads = payloads;
--
--		result = dal_i2caux_submit_aux_command(
--			dal_adapter_service_get_i2caux(ddc->as),
--			ddc->ddc_pin,
--			&cmd);
--
--		if (false == result)
--			dal_logger_write(
--				ddc->ctx->logger,
--				LOG_MAJOR_ERROR,
--				LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
--				"%s: Writing of EDID Segment (0x30) failed!\n",
--				__func__);
--	}
--
--	return retrieved;
--}
--
--static uint8_t i2c_read_edid_block(
--	struct ddc_service *ddc,
--	uint8_t address,
--	uint8_t index,
--	uint8_t *buf)
--{
--	bool ret = false;
--	uint8_t offset = (index % DDC_EDID_BLOCKS_PER_SEGMENT) *
--		DDC_EDID_BLOCK_SIZE;
--	uint8_t segment = index / DDC_EDID_BLOCKS_PER_SEGMENT;
--
--	struct i2c_command cmd = {
--		.payloads = NULL,
--		.number_of_payloads = 0,
--		.engine = DDC_I2C_COMMAND_ENGINE,
--		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
--
--	struct i2c_payload payloads[3] = {
--		{
--		.write = true,
--		.address = DDC_EDID_SEGMENT_ADDRESS,
--		.length = 1,
--		.data = &segment },
--		{
--		.write = true,
--		.address = address,
--		.length = 1,
--		.data = &offset },
--		{
--		.write = false,
--		.address = address,
--		.length = DDC_EDID_BLOCK_SIZE,
--		.data = buf } };
--/*
-- * Some I2C engines don't handle stop/start between write-offset and read-data
-- * commands properly. For those displays, we have to force the newer E-DDC
-- * behavior of repeated-start which can be enabled by runtime parameter. */
--/* Originally implemented for OnLive using NXP receiver chip */
--
--	if (index == 0 && !ddc->flags.FORCE_READ_REPEATED_START) {
--		/* base block, use use DDC2B, submit as 2 commands */
--		cmd.payloads = &payloads[1];
--		cmd.number_of_payloads = 1;
--
--		if (dal_i2caux_submit_i2c_command(
--			dal_adapter_service_get_i2caux(ddc->as),
--			ddc->ddc_pin,
--			&cmd)) {
--
--			cmd.payloads = &payloads[2];
--			cmd.number_of_payloads = 1;
--
--			ret = dal_i2caux_submit_i2c_command(
--				dal_adapter_service_get_i2caux(ddc->as),
--				ddc->ddc_pin,
--				&cmd);
--		}
--
--	} else {
--		/*
--		 * extension block use E-DDC, submit as 1 command
--		 * or if repeated-start is forced by runtime parameter
--		 */
--		if (segment != 0) {
--			/* include segment offset in command*/
--			cmd.payloads = payloads;
--			cmd.number_of_payloads = 3;
--		} else {
--			/* we are reading first segment,
--			 * segment offset is not required */
--			cmd.payloads = &payloads[1];
--			cmd.number_of_payloads = 2;
--		}
--
--		ret = dal_i2caux_submit_i2c_command(
--			dal_adapter_service_get_i2caux(ddc->as),
--			ddc->ddc_pin,
--			&cmd);
--	}
--
--	return ret ? DDC_EDID_BLOCK_SIZE : 0;
--}
--
--static uint32_t query_edid_block(
--	struct ddc_service *ddc,
--	uint8_t address,
--	uint8_t index,
--	uint8_t *buf,
--	uint32_t size)
--{
--	uint32_t size_retrieved = 0;
--
--	if (size < DDC_EDID_BLOCK_SIZE)
--		return 0;
--
--	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
--
--		ASSERT(index < 2);
--		size_retrieved =
--			aux_read_edid_block(ddc, address, index, buf);
--	} else {
--		size_retrieved =
--			i2c_read_edid_block(ddc, address, index, buf);
--	}
--
--	return size_retrieved;
--}
--
--#define DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS 0x261
--#define DDC_TEST_ACK_ADDRESS 0x260
--#define DDC_DPCD_EDID_TEST_ACK 0x04
--#define DDC_DPCD_EDID_TEST_MASK 0x04
--#define DDC_DPCD_TEST_REQUEST_ADDRESS 0x218
--
--/* AG TODO GO throug DM callback here like for DPCD */
--
--static void write_dp_edid_checksum(
--	struct ddc_service *ddc,
--	uint8_t checksum)
--{
--	uint8_t dpcd_data;
--
--	dal_ddc_service_read_dpcd_data(
--		ddc,
--		DDC_DPCD_TEST_REQUEST_ADDRESS,
--		&dpcd_data,
--		1);
--
--	if (dpcd_data & DDC_DPCD_EDID_TEST_MASK) {
--
--		dal_ddc_service_write_dpcd_data(
--			ddc,
--			DDC_DPCD_EDID_CHECKSUM_WRITE_ADDRESS,
--			&checksum,
--			1);
--
--		dpcd_data = DDC_DPCD_EDID_TEST_ACK;
--
--		dal_ddc_service_write_dpcd_data(
--			ddc,
--			DDC_TEST_ACK_ADDRESS,
--			&dpcd_data,
--			1);
--	}
--}
--
--uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc)
--{
--	uint32_t bytes_read = 0;
--	uint32_t ext_cnt = 0;
--
--	uint8_t address;
--	uint32_t i;
--
--	for (address = DDC_EDID_ADDRESS_START;
--		address <= DDC_EDID_ADDRESS_END; ++address) {
--
--		bytes_read = query_edid_block(
--			ddc,
--			address,
--			0,
--			ddc->edid_buf,
--			sizeof(ddc->edid_buf) - bytes_read);
--
--		if (bytes_read != DDC_EDID_BLOCK_SIZE)
--			continue;
--
--		/* get the number of ext blocks*/
--		ext_cnt = ddc->edid_buf[DDC_EDID_EXT_COUNT_OFFSET];
--
--		/* EDID 2.0, need to read 1 more block because EDID2.0 is
--		 * 256 byte in size*/
--		if (ddc->edid_buf[DDC_EDID_20_SIGNATURE_OFFSET] ==
--			DDC_EDID_20_SIGNATURE)
--				ext_cnt = 1;
--
--		for (i = 0; i < ext_cnt; i++) {
--			/* read additional ext blocks accordingly */
--			bytes_read += query_edid_block(
--					ddc,
--					address,
--					i+1,
--					&ddc->edid_buf[bytes_read],
--					sizeof(ddc->edid_buf) - bytes_read);
--		}
--
--		/*this is special code path for DP compliance*/
--		if (DDC_TRANSACTION_TYPE_I2C_OVER_AUX == ddc->transaction_type)
--			write_dp_edid_checksum(
--				ddc,
--				ddc->edid_buf[(ext_cnt * DDC_EDID_BLOCK_SIZE) +
--				DDC_EDID1X_CHECKSUM_OFFSET]);
--
--		/*remembers the address where we fetch the EDID from
--		 * for later signature check use */
--		ddc->address = address;
--
--		break;/* already read edid, done*/
--	}
--
--	ddc->edid_buf_len = bytes_read;
--	return bytes_read;
--}
--
--uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc)
--{
--	return ddc->edid_buf_len;
--}
--
--void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf)
--{
--	dc_service_memmove(edid_buf,
--			ddc->edid_buf, ddc->edid_buf_len);
--}
--
--void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
--	struct ddc_service *ddc,
--	struct display_sink_capability *sink_cap)
--{
--	uint8_t i;
--	bool is_valid_hdmi_signature;
--	enum display_dongle_type *dongle = &sink_cap->dongle_type;
--	uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
--	bool is_type2_dongle = false;
--	struct dp_hdmi_dongle_signature_data *dongle_signature;
--
--	/* Assume we have no valid DP passive dongle connected */
--	*dongle = DISPLAY_DONGLE_NONE;
--	sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
--
--	/* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
--	if (!i2c_read(
--		ddc,
--		DP_HDMI_DONGLE_ADDRESS,
--		type2_dongle_buf,
--		sizeof(type2_dongle_buf))) {
--		dal_logger_write(ddc->ctx->logger,
--			LOG_MAJOR_DCS,
--			LOG_MINOR_DCS_DONGLE_DETECTION,
--			"Detected DP-DVI dongle.\n");
--		*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
--		sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
--		return;
--	}
--
--	/* Check if Type 2 dongle.*/
--	if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
--		is_type2_dongle = true;
--
--	dongle_signature =
--		(struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
--
--	is_valid_hdmi_signature = true;
--
--	/* Check EOT */
--	if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
--		is_valid_hdmi_signature = false;
--	}
--
--	/* Check signature */
--	for (i = 0; i < sizeof(dongle_signature->id); ++i) {
--		/* If its not the right signature,
--		 * skip mismatch in subversion byte.*/
--		if (dongle_signature->id[i] !=
--			dp_hdmi_dongle_signature_str[i] && i != 3) {
--
--			if (is_type2_dongle) {
--				is_valid_hdmi_signature = false;
--				break;
--			}
--
--		}
--	}
--
--	if (is_type2_dongle) {
--		uint32_t max_tmds_clk =
--			type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
--
--		max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
--
--		if (0 == max_tmds_clk ||
--				max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
--				max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
--			dal_logger_write(ddc->ctx->logger,
--				LOG_MAJOR_DCS,
--				LOG_MINOR_DCS_DONGLE_DETECTION,
--				"Invalid Maximum TMDS clock");
--			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
--		} else {
--			if (is_valid_hdmi_signature == true) {
--				*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
--				dal_logger_write(ddc->ctx->logger,
--					LOG_MAJOR_DCS,
--					LOG_MINOR_DCS_DONGLE_DETECTION,
--					"Detected Type 2 DP-HDMI Maximum TMDS "
--					"clock, max TMDS clock: %d MHz",
--					max_tmds_clk);
--			} else {
--				*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
--				dal_logger_write(ddc->ctx->logger,
--					LOG_MAJOR_DCS,
--					LOG_MINOR_DCS_DONGLE_DETECTION,
--					"Detected Type 2 DP-HDMI (no valid HDMI"
--					" signature) Maximum TMDS clock, max "
--					"TMDS clock: %d MHz",
--					max_tmds_clk);
--			}
--
--			/* Multiply by 1000 to convert to kHz. */
--			sink_cap->max_hdmi_pixel_clock =
--				max_tmds_clk * 1000;
--		}
--
--	} else {
--		if (is_valid_hdmi_signature == true) {
--			dal_logger_write(ddc->ctx->logger,
--				LOG_MAJOR_DCS,
--				LOG_MINOR_DCS_DONGLE_DETECTION,
--				"Detected Type 1 DP-HDMI dongle.\n");
--			*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
--		}
--		else {
--			dal_logger_write(ddc->ctx->logger,
--				LOG_MAJOR_DCS,
--				LOG_MINOR_DCS_DONGLE_DETECTION,
--				"Detected Type 1 DP-HDMI dongle (no valid HDMI "
--				"signature).\n");
--
--			*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
--		}
--	}
--
--	return;
--}
--
--enum {
--	DP_SINK_CAP_SIZE =
--		DPCD_ADDRESS_EDP_CONFIG_CAP - DPCD_ADDRESS_DPCD_REV + 1
--};
--
--bool dal_ddc_service_query_ddc_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	uint8_t *write_buf,
--	uint32_t write_size,
--	uint8_t *read_buf,
--	uint32_t read_size)
--{
--	bool ret;
--	uint32_t payload_size =
--		dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
--			DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
--
--	uint32_t write_payloads =
--		(write_size + payload_size - 1) / payload_size;
--
--	uint32_t read_payloads =
--		(read_size + payload_size - 1) / payload_size;
--
--	uint32_t payloads_num = write_payloads + read_payloads;
--
--	if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
--		return false;
--
--	/*TODO: len of payload data for i2c and aux is uint8!!!!,
--	 *  but we want to read 256 over i2c!!!!*/
--	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
--
--		struct aux_payloads *payloads =
--			dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
--
--		struct aux_command command = {
--			.payloads = dal_ddc_aux_payloads_get(payloads),
--			.number_of_payloads = 0,
--			.defer_delay = get_defer_delay(ddc),
--			.max_defer_write_retry = 0 };
--
--		dal_ddc_aux_payloads_add(
--			payloads, address, write_size, write_buf, true);
--
--		dal_ddc_aux_payloads_add(
--			payloads, address, read_size, read_buf, false);
--
--		command.number_of_payloads =
--			dal_ddc_aux_payloads_get_count(payloads);
--
--		ret = dal_i2caux_submit_aux_command(
--				dal_adapter_service_get_i2caux(ddc->as),
--				ddc->ddc_pin,
--				&command);
--
--		dal_ddc_aux_payloads_destroy(&payloads);
--
--	} else {
--		struct i2c_payloads *payloads =
--			dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
--
--		struct i2c_command command = {
--			.payloads = dal_ddc_i2c_payloads_get(payloads),
--			.number_of_payloads = 0,
--			.engine = DDC_I2C_COMMAND_ENGINE,
--			.speed =
--				dal_adapter_service_get_sw_i2c_speed(ddc->as) };
--
--		dal_ddc_i2c_payloads_add(
--			payloads, address, write_size, write_buf, true);
--
--		dal_ddc_i2c_payloads_add(
--			payloads, address, read_size, read_buf, false);
--
--		command.number_of_payloads =
--			dal_ddc_i2c_payloads_get_count(payloads);
--
--		ret = dal_i2caux_submit_i2c_command(
--				dal_adapter_service_get_i2caux(ddc->as),
--				ddc->ddc_pin,
--				&command);
--
--		dal_ddc_i2c_payloads_destroy(&payloads);
--	}
--
--	return ret;
--}
--
--bool dal_ddc_service_get_dp_receiver_id_info(
--	struct ddc_service *ddc,
--	struct dp_receiver_id_info *info)
--{
--	if (!info)
--		return false;
--
--	*info = ddc->dp_receiver_id_info;
--	return true;
--}
--
--enum ddc_result dal_ddc_service_read_dpcd_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	uint8_t *data,
--	uint32_t len)
--{
--	struct aux_payload read_payload = {
--		.i2c_over_aux = false,
--		.write = false,
--		.address = address,
--		.length = len,
--		.data = data,
--	};
--	struct aux_command command = {
--		.payloads = &read_payload,
--		.number_of_payloads = 1,
--		.defer_delay = 0,
--		.max_defer_write_retry = 0,
--	};
--
--	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
--		BREAK_TO_DEBUGGER();
--		return DDC_RESULT_FAILED_INVALID_OPERATION;
--	}
--
--	if (dal_i2caux_submit_aux_command(
--		dal_adapter_service_get_i2caux(ddc->as),
--		ddc->ddc_pin,
--		&command))
--		return DDC_RESULT_SUCESSFULL;
--
--	return DDC_RESULT_FAILED_OPERATION;
--}
--
--enum ddc_result dal_ddc_service_write_dpcd_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	const uint8_t *data,
--	uint32_t len)
--{
--	struct aux_payload write_payload = {
--		.i2c_over_aux = false,
--		.write = true,
--		.address = address,
--		.length = len,
--		.data = (uint8_t *)data,
--	};
--	struct aux_command command = {
--		.payloads = &write_payload,
--		.number_of_payloads = 1,
--		.defer_delay = 0,
--		.max_defer_write_retry = 0,
--	};
--
--	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
--		BREAK_TO_DEBUGGER();
--		return DDC_RESULT_FAILED_INVALID_OPERATION;
--	}
--
--	if (dal_i2caux_submit_aux_command(
--		dal_adapter_service_get_i2caux(ddc->as),
--		ddc->ddc_pin,
--		&command))
--		return DDC_RESULT_SUCESSFULL;
--
--	return DDC_RESULT_FAILED_OPERATION;
--}
--
--/*test only function*/
--void dal_ddc_service_set_ddc_pin(
--	struct ddc_service *ddc_service,
--	struct ddc *ddc)
--{
--	ddc_service->ddc_pin = ddc;
--}
--
--struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
--{
--	return ddc_service->ddc_pin;
--}
--
--
--void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
--{
--	dc_service_memset(&ddc_service->dp_receiver_id_info,
--		0, sizeof(struct dp_receiver_id_info));
--}
--
--void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
--		uint32_t pix_clk,
--		bool lte_340_scramble)
--{
--	bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
--	uint8_t slave_address = HDMI_SCDC_ADDRESS;
--	uint8_t offset = HDMI_SCDC_SINK_VERSION;
--	uint8_t sink_version = 0;
--	uint8_t write_buffer[2] = {0};
--	/*Lower than 340 Scramble bit from SCDC caps*/
--
--	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
--			sizeof(offset), &sink_version, sizeof(sink_version));
--	if (sink_version == 1) {
--		/*Source Version = 1*/
--		write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
--		write_buffer[1] = 1;
--		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
--				write_buffer, sizeof(write_buffer), NULL, 0);
--		/*Read Request from SCDC caps*/
--	}
--	write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
--
--	if (over_340_mhz)
--	{
--		write_buffer[1] = 3;
--	}
--	else if (lte_340_scramble)
--	{
--		write_buffer[1] = 1;
--	}
--	else
--	{
--		write_buffer[1] = 0;
--	}
--	dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
--			sizeof(write_buffer), NULL, 0);
--}
--
--void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
--{
--	uint8_t slave_address = HDMI_SCDC_ADDRESS;
--	uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
--	uint8_t tmds_config = 0;
--
--	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
--			sizeof(offset), &tmds_config, sizeof(tmds_config));
--	if (tmds_config & 0x1){
--		union hdmi_scdc_status_flags_data status_data = {{0}};
--		uint8_t scramble_status = 0;
--
--		offset = HDMI_SCDC_SCRAMBLER_STATUS;
--		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
--				&offset, sizeof(offset),&scramble_status,
--				sizeof(scramble_status));
--		offset = HDMI_SCDC_STATUS_FLAGS;
--		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
--				&offset, sizeof(offset),status_data.byte,
--				sizeof(status_data.byte));
--	}
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h b/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-deleted file mode 100644
-index 3bf2a9e..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dcs/ddc_service.h
-+++ /dev/null
-@@ -1,49 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_DDC_SERVICE_H__
--#define __DAL_DDC_SERVICE_H__
--
--#include "include/ddc_service_types.h"
--
--void dal_ddc_service_set_ddc_pin(
--	struct ddc_service *ddc_service,
--	struct ddc *ddc);
--
--struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service);
--void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service);
--
--enum ddc_result dal_ddc_service_read_dpcd_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	uint8_t *data,
--	uint32_t len);
--enum ddc_result dal_ddc_service_write_dpcd_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	const uint8_t *data,
--	uint32_t len);
--
--#endif /* __DAL_DDC_SERVICE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
-new file mode 100644
-index 0000000..18104d6
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
-@@ -0,0 +1,151 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DDC_SERVICE_H__
-+#define __DAL_DDC_SERVICE_H__
-+
-+#include "include/ddc_service_types.h"
-+#include "include/i2caux_interface.h"
-+
-+#define EDID_SEGMENT_SIZE 256
-+
-+struct ddc_service;
-+struct adapter_service;
-+struct graphics_object_id;
-+enum ddc_result;
-+struct av_sync_data;
-+struct dp_receiver_id_info;
-+
-+struct i2c_payloads;
-+struct aux_payloads;
-+
-+struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count);
-+struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p);
-+uint32_t  dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p);
-+void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p);
-+
-+struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count);
-+struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p);
-+uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p);
-+void dal_ddc_aux_payloads_destroy(struct aux_payloads **p);
-+
-+void dal_ddc_i2c_payloads_add(
-+		struct i2c_payloads *payloads,
-+		uint32_t address,
-+		uint32_t len,
-+		uint8_t *data,
-+		bool write);
-+
-+void dal_ddc_aux_payloads_add(
-+		struct aux_payloads *payloads,
-+		uint32_t address,
-+		uint32_t len,
-+		uint8_t *data,
-+		bool write);
-+
-+struct ddc_service_init_data {
-+	struct adapter_service *as;
-+	struct graphics_object_id id;
-+	struct dc_context *ctx;
-+};
-+
-+struct ddc_service *dal_ddc_service_create(
-+		struct ddc_service_init_data *ddc_init_data);
-+
-+void dal_ddc_service_destroy(struct ddc_service **ddc);
-+
-+enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
-+
-+void dal_ddc_service_set_transaction_type(
-+		struct ddc_service *ddc,
-+		enum ddc_transaction_type type);
-+
-+bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
-+
-+uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc);
-+
-+uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc);
-+
-+void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf);
-+
-+void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+		struct ddc_service *ddc,
-+		struct display_sink_capability *sink_cap);
-+
-+bool dal_ddc_service_query_ddc_data(
-+		struct ddc_service *ddc,
-+		uint32_t address,
-+		uint8_t *write_buf,
-+		uint32_t write_size,
-+		uint8_t *read_buf,
-+		uint32_t read_size);
-+
-+bool dal_ddc_service_get_dp_receiver_id_info(
-+		struct ddc_service *ddc,
-+		struct dp_receiver_id_info *info);
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+		struct ddc_service *ddc,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t len);
-+
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+		struct ddc_service *ddc,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t len);
-+
-+void dal_ddc_service_write_scdc_data(
-+		struct ddc_service *ddc_service,
-+		uint32_t pix_clk,
-+		bool lte_340_scramble);
-+
-+void dal_ddc_service_read_scdc_data(
-+		struct ddc_service *ddc_service);
-+
-+void ddc_service_set_dongle_type(struct ddc_service *ddc,
-+		enum display_dongle_type dongle_type);
-+
-+void dal_ddc_service_set_ddc_pin(
-+		struct ddc_service *ddc_service,
-+		struct ddc *ddc);
-+
-+struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service);
-+void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service);
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+		struct ddc_service *ddc,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t len);
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+		struct ddc_service *ddc,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t len);
-+
-+#endif /* __DAL_DDC_SERVICE_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_interface.h b/drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
-deleted file mode 100644
-index ca3e6ce..0000000
---- a/drivers/gpu/drm/amd/dal/include/ddc_service_interface.h
-+++ /dev/null
-@@ -1,100 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_DDC_SERVICE_INTERFACE_H__
--#define __DAL_DDC_SERVICE_INTERFACE_H__
--
--#include "ddc_service_types.h"
--
--struct ddc_service;
--struct adapter_service;
--struct graphics_object_id;
--enum ddc_result;
--struct av_sync_data;
--struct dp_receiver_id_info;
--
--struct ddc_service_init_data {
--	struct adapter_service *as;
--	struct graphics_object_id id;
--	struct dc_context *ctx;
--};
--struct ddc_service *dal_ddc_service_create(
--	struct ddc_service_init_data *ddc_init_data);
--
--void dal_ddc_service_destroy(struct ddc_service **ddc);
--
--enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
--
--void dal_ddc_service_set_transaction_type(
--	struct ddc_service *ddc,
--	enum ddc_transaction_type type);
--
--bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
--
--uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc);
--
--uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc);
--
--void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf);
--
--void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
--	struct ddc_service *ddc,
--	struct display_sink_capability *sink_cap);
--
--bool dal_ddc_service_query_ddc_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	uint8_t *write_buf,
--	uint32_t write_size,
--	uint8_t *read_buf,
--	uint32_t read_size);
--
--bool dal_ddc_service_get_dp_receiver_id_info(
--	struct ddc_service *ddc,
--	struct dp_receiver_id_info *info);
--
--enum ddc_result dal_ddc_service_read_dpcd_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	uint8_t *data,
--	uint32_t len);
--
--enum ddc_result dal_ddc_service_write_dpcd_data(
--	struct ddc_service *ddc,
--	uint32_t address,
--	const uint8_t *data,
--	uint32_t len);
--
--void dal_ddc_service_write_scdc_data(
--	struct ddc_service *ddc_service,
--	uint32_t pix_clk,
--	bool lte_340_scramble);
--
--void dal_ddc_service_read_scdc_data(
--	struct ddc_service *ddc_service);
--
--void ddc_service_set_dongle_type(struct ddc_service *ddc,
--		enum display_dongle_type dongle_type);
--
--#endif /* __DAL_DDC_SERVICE_INTERFACE_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0746-drm-amd-dal-Use-max-clocks-safemarks-for-dce10.patch b/common/recipes-kernel/linux/files/0746-drm-amd-dal-Use-max-clocks-safemarks-for-dce10.patch
deleted file mode 100644
index 5fff1736..00000000
--- a/common/recipes-kernel/linux/files/0746-drm-amd-dal-Use-max-clocks-safemarks-for-dce10.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 6c1d0e9992aea089e866a3fa1e4e6c1cfa08de1a Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 28 Jan 2016 14:06:37 -0500
-Subject: [PATCH 0746/1110] drm/amd/dal: Use max clocks/safemarks for dce10
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    | 36 +++++++++++++++++++++-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  8 +++--
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  6 ++++
- 3 files changed, 46 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index b76c8ee..75aff2a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -335,6 +335,39 @@ static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool ena
- 	}
- }
- 
-+/**
-+ * Call display_engine_clock_dce80 to perform the Dclk programming.
-+ */
-+static void set_display_clock(struct validate_context *context)
-+{
-+	/* Program the display engine clock.
-+	 * Check DFS bypass mode support or not. DFSbypass feature is only when
-+	 * BIOS GPU info table reports support. */
-+
-+	if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
-+		/*TODO: set_display_clock_dfs_bypass(
-+				hws,
-+				path_set,
-+				context->res_ctx.pool.display_clock,
-+				context->res_ctx.min_clocks.min_dclk_khz);*/
-+	} else
-+		dal_display_clock_set_clock(context->res_ctx.pool.display_clock,
-+				681000);
-+
-+	/* TODO: When changing display engine clock, DMCU WaitLoop must be
-+	 * reconfigured in order to maintain the same delays within DMCU
-+	 * programming sequences. */
-+
-+	/* TODO: Start GTC counter */
-+}
-+
-+
-+static void set_displaymarks(
-+		const struct dc *dc, struct validate_context *context)
-+{
-+	/* Do nothing until we have proper bandwitdth calcs */
-+}
-+
- /**************************************************************************/
- 
- bool dce100_hw_sequencer_construct(struct dc *dc)
-@@ -348,7 +381,8 @@ bool dce100_hw_sequencer_construct(struct dc *dc)
- 	dc->hwss.enable_fe_clock = dce100_enable_fe_clock;
- 	dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
- 	dc->hwss.set_blender_mode = dce100_set_blender_mode;
--
-+	dc->hwss.set_display_clock = set_display_clock;
-+	dc->hwss.set_displaymarks = set_displaymarks;
- 	return true;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 9158955..2981307 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1148,8 +1148,8 @@ static void program_bw(struct dc *dc, struct validate_context *context)
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
--	set_display_clock(context);
--	set_displaymarks(dc, context);
-+	dc->hwss.set_display_clock(context);
-+	dc->hwss.set_displaymarks(dc, context);
- }
- 
- static void switch_dp_clock_sources(
-@@ -1238,7 +1238,7 @@ static enum dc_status apply_ctx_to_hw(
- 		if (DC_OK != status)
- 			return status;
- 	}
--	set_displaymarks(dc, context);
-+	dc->hwss.set_displaymarks(dc, context);
- 
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
- 			false);
-@@ -1646,6 +1646,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.pipe_control_lock = dce110_pipe_control_lock,
- 	.set_blender_mode = dce110_set_blender_mode,
- 	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,/*todo*/
-+	.set_display_clock = set_display_clock,
-+	.set_displaymarks = set_displaymarks,
- };
- 
- bool dce110_hw_sequencer_construct(struct dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index bbb39e4..8460dd7 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -110,6 +110,12 @@ struct hw_sequencer_funcs {
- 				struct dc_context *ctx,
- 				uint8_t controller_id,
- 				uint32_t mode);
-+
-+	void (*set_displaymarks)(
-+				const struct dc *dc,
-+				struct validate_context *context);
-+
-+	void (*set_display_clock)(struct validate_context *context);
- };
- 
- bool dc_construct_hw_sequencer(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch b/common/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch
deleted file mode 100644
index 0fcef70a..00000000
--- a/common/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch
+++ /dev/null
@@ -1,440 +0,0 @@
-From c3c479b7aa28af6851b5870e7e02209d575dd87c Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 28 Jan 2016 12:23:23 -0500
-Subject: [PATCH 0747/1110] drm/amd/dal: Abstract tiling_info params
-
-Also cleaned up unused plane types
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  34 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |   4 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 192 ++++++++-------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  23 ++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |   2 +-
- 7 files changed, 102 insertions(+), 157 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index af71e87..d09f0ad 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -37,10 +37,6 @@
- #undef FRAME_SIZE
- #undef DEPRECATED
- 
--#include "dce/dce_11_0_d.h"
--#include "dce/dce_11_0_sh_mask.h"
--#include "dce/dce_11_0_enum.h"
--
- #include "dc.h"
- 
- #include "amdgpu_dm_types.h"
-@@ -442,9 +438,9 @@ static void fill_plane_attributes_from_fb(
- 		return;
- 	}
- 
--	surface->tiling_info.value = 0;
-+	memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
- 
--	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1)
-+	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
- 	{
- 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
- 
-@@ -456,21 +452,21 @@ static void fill_plane_attributes_from_fb(
- 
- 
- 		/* XXX fix me for VI */
--		surface->tiling_info.grph.NUM_BANKS = num_banks;
--		surface->tiling_info.grph.ARRAY_MODE =
--						ARRAY_2D_TILED_THIN1;
--		surface->tiling_info.grph.TILE_SPLIT = tile_split;
--		surface->tiling_info.grph.BANK_WIDTH = bankw;
--		surface->tiling_info.grph.BANK_HEIGHT = bankh;
--		surface->tiling_info.grph.TILE_ASPECT = mtaspect;
--		surface->tiling_info.grph.TILE_MODE =
--				ADDR_SURF_MICRO_TILING_DISPLAY;
-+		surface->tiling_info.num_banks = num_banks;
-+		surface->tiling_info.array_mode =
-+				DC_ARRAY_2D_TILED_THIN1;
-+		surface->tiling_info.tile_split = tile_split;
-+		surface->tiling_info.bank_width = bankw;
-+		surface->tiling_info.bank_height = bankh;
-+		surface->tiling_info.tile_aspect = mtaspect;
-+		surface->tiling_info.tile_mode =
-+				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
- 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
--			== ARRAY_1D_TILED_THIN1) {
--		surface->tiling_info.grph.ARRAY_MODE = ARRAY_1D_TILED_THIN1;
-+			== DC_ARRAY_1D_TILED_THIN1) {
-+		surface->tiling_info.array_mode = DC_ARRAY_1D_TILED_THIN1;
- 	}
- 
--	surface->tiling_info.grph.PIPE_CONFIG =
-+	surface->tiling_info.pipe_config =
- 			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
- 
- 	surface->plane_size.grph.surface_size.x = 0;
-@@ -484,7 +480,7 @@ static void fill_plane_attributes_from_fb(
- 	surface->scaling_quality.h_taps_c = 2;
- 	surface->scaling_quality.v_taps_c = 2;
- 
--/* TODO: unhardcode */
-+	/* TODO: unhardcode */
- 	surface->colorimetry.limited_range = false;
- 	surface->colorimetry.color_space = SURFACE_COLOR_SPACE_SRGB;
- 	surface->scaling_quality.h_taps = 2;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 2756e7b..f114fc4 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -211,12 +211,10 @@ static bool validate_surface_address(
- 		}
- 		break;
- 	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
--	case PLN_ADDR_TYPE_VIDEO_INTERLACED:
--	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO:
--	case PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO:
- 	default:
- 		/* not supported */
- 		BREAK_TO_DEBUGGER();
-+		break;
- 	}
- 
- 	return is_valid_address;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index fcc79ed..1cd0883 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -68,7 +68,7 @@ struct dc_surface {
- 	struct rect clip_rect;
- 
- 	union plane_size plane_size;
--	union dc_tiling_info tiling_info;
-+	struct dc_tiling_info tiling_info;
- 	struct plane_colorimetry colorimetry;
- 
- 	enum surface_pixel_format format;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index fe7046f..0a48ef4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -605,9 +605,6 @@ enum dc_plane_addr_type {
- 	PLN_ADDR_TYPE_GRAPHICS = 0,
- 	PLN_ADDR_TYPE_GRPH_STEREO,
- 	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
--	PLN_ADDR_TYPE_VIDEO_INTERLACED,
--	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO,
--	PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO
- };
- 
- struct dc_plane_address {
-@@ -628,35 +625,6 @@ struct dc_plane_address {
- 			PHYSICAL_ADDRESS_LOC chroma_addr;
- 			PHYSICAL_ADDRESS_LOC luma_addr;
- 		} video_progressive;
--
--		/*video interlaced*/
--		struct {
--			PHYSICAL_ADDRESS_LOC chroma_addr;
--			PHYSICAL_ADDRESS_LOC luma_addr;
--			PHYSICAL_ADDRESS_LOC chroma_bottom_addr;
--			PHYSICAL_ADDRESS_LOC luma_bottom_addr;
--		} video_interlaced;
--
--		/*video Progressive Stereo*/
--		struct {
--			PHYSICAL_ADDRESS_LOC left_chroma_addr;
--			PHYSICAL_ADDRESS_LOC left_luma_addr;
--			PHYSICAL_ADDRESS_LOC right_chroma_addr;
--			PHYSICAL_ADDRESS_LOC right_luma_addr;
--		} video_progressive_stereo;
--
--		/*video  interlaced stereo*/
--		struct {
--			PHYSICAL_ADDRESS_LOC left_chroma_addr;
--			PHYSICAL_ADDRESS_LOC left_luma_addr;
--			PHYSICAL_ADDRESS_LOC left_chroma_bottom_addr;
--			PHYSICAL_ADDRESS_LOC left_luma_bottom_addr;
--
--			PHYSICAL_ADDRESS_LOC right_chroma_addr;
--			PHYSICAL_ADDRESS_LOC right_luma_addr;
--			PHYSICAL_ADDRESS_LOC right_chroma_bottom_addr;
--			PHYSICAL_ADDRESS_LOC right_luma_bottom_addr;
--		} video_interlaced_stereo;
- 	};
- };
- 
-@@ -852,98 +820,84 @@ struct stereo_3d_view {
- 	} flags;
- };
- 
--/* TODO: Rename to dc_tiling_info */
--union dc_tiling_info {
-+/* TODO: These values come from hardware spec. We need to readdress this
-+ * if they ever change.
-+ */
-+enum array_mode_values {
-+	DC_ARRAY_UNDEFINED = 0,
-+	DC_ARRAY_1D_TILED_THIN1 = 0x2,
-+	DC_ARRAY_2D_TILED_THIN1 = 0x4,
-+};
- 
--	struct {
--		/* Specifies the number of memory banks for tiling
--		 *	purposes.
--		 * Only applies to 2D and 3D tiling modes.
--		 *	POSSIBLE VALUES: 2,4,8,16
--		 */
--		uint32_t NUM_BANKS:5;
--		/* Specifies the number of tiles in the x direction
--		 *	to be incorporated into the same bank.
--		 * Only applies to 2D and 3D tiling modes.
--		 *	POSSIBLE VALUES: 1,2,4,8
--		 */
--		uint32_t BANK_WIDTH:4;
--		/* Specifies the number of tiles in the y direction to
--		 *	be incorporated into the same bank.
--		 * Only applies to 2D and 3D tiling modes.
--		 *	POSSIBLE VALUES: 1,2,4,8
--		 */
--		uint32_t BANK_HEIGHT:4;
--		/* Specifies the macro tile aspect ratio. Only applies
--		 * to 2D and 3D tiling modes.
--		 */
--		uint32_t TILE_ASPECT:3;
--		/* Specifies the number of bytes that will be stored
--		 *	contiguously for each tile.
--		 * If the tile data requires more storage than this
--		 *	amount, it is split into multiple slices.
--		 * This field must not be larger than
--		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
--		 * Only applies to 2D and 3D tiling modes.
--		 * For color render targets, TILE_SPLIT >= 256B.
--		 */
--		uint32_t TILE_SPLIT:3;
--		/* Specifies the addressing within a tile.
--		 *	0x0 - DISPLAY_MICRO_TILING
--		 *	0x1 - THIN_MICRO_TILING
--		 *	0x2 - DEPTH_MICRO_TILING
--		 *	0x3 - ROTATED_MICRO_TILING
--		 */
--		uint32_t TILE_MODE:2;
--		/* Specifies the number of pipes and how they are
--		 *	interleaved in the surface.
--		 * Refer to memory addressing document for complete
--		 *	details and constraints.
--		 */
--		uint32_t PIPE_CONFIG:5;
--		/* Specifies the tiling mode of the surface.
--		 * THIN tiles use an 8x8x1 tile size.
--		 * THICK tiles use an 8x8x4 tile size.
--		 * 2D tiling modes rotate banks for successive Z slices
--		 * 3D tiling modes rotate pipes and banks for Z slices
--		 * Refer to memory addressing document for complete
--		 *	details and constraints.
--		 */
--		uint32_t ARRAY_MODE:4;
--	} grph;
- 
-+enum tile_mode_values {
-+	DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
-+	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-+};
- 
--	struct {
--		/*possible values: 2,4,8,16*/
--		uint32_t NUM_BANKS:5;
--		/*must use enum video_array_mode*/
--		uint32_t ARRAY_MODE:4;
--		/*must use enum addr_pipe_config*/
--		uint32_t PIPE_CONFIG:5;
--		/*possible values 1,2,4,8 */
--		uint32_t BANK_WIDTH_LUMA:4;
--		/*possible values 1,2,4,8 */
--		uint32_t BANK_HEIGHT_LUMA:4;
--		/*must use enum macro_tile_aspect*/
--		uint32_t TILE_ASPECT_LUMA:3;
--		/*must use enum tile_split*/
--		uint32_t TILE_SPLIT_LUMA:3;
--		/*must use micro_tile_mode */
--		uint32_t TILE_MODE_LUMA:2;
--		/*possible values: 1,2,4,8*/
--		uint32_t BANK_WIDTH_CHROMA:4;
--		/*possible values: 1,2,4,8*/
--		uint32_t BANK_HEIGHT_CHROMA:4;
--		/*must use enum macro_tile_aspect*/
--		uint32_t TILE_ASPECT_CHROMA:3;
--		/*must use enum tile_split*/
--		uint32_t TILE_SPLIT_CHROMA:3;
--		/*must use enum micro_tile_mode*/
--		uint32_t TILE_MODE_CHROMA:2;
-+enum tile_split_values {
-+	DC_DISPLAY_MICRO_TILING = 0x0,
-+	DC_THIN_MICRO_TILING = 0x1,
-+	DC_DEPTH_MICRO_TILING = 0x2,
-+	DC_ROTATED_MICRO_TILING = 0x3,
-+};
- 
--	} video;
-+struct dc_tiling_info {
- 
--	uint64_t value;
-+	/* Specifies the number of memory banks for tiling
-+	 *	purposes.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 *	POSSIBLE VALUES: 2,4,8,16
-+	 */
-+	unsigned int num_banks;
-+	/* Specifies the number of tiles in the x direction
-+	 *	to be incorporated into the same bank.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 *	POSSIBLE VALUES: 1,2,4,8
-+	 */
-+	unsigned int bank_width;
-+	/* Specifies the number of tiles in the y direction to
-+	 *	be incorporated into the same bank.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 *	POSSIBLE VALUES: 1,2,4,8
-+	 */
-+	unsigned int bank_height;
-+	/* Specifies the macro tile aspect ratio. Only applies
-+	 * to 2D and 3D tiling modes.
-+	 */
-+	unsigned int tile_aspect;
-+	/* Specifies the number of bytes that will be stored
-+	 *	contiguously for each tile.
-+	 * If the tile data requires more storage than this
-+	 *	amount, it is split into multiple slices.
-+	 * This field must not be larger than
-+	 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 * For color render targets, TILE_SPLIT >= 256B.
-+	 */
-+	enum tile_split_values tile_split;
-+	/* Specifies the addressing within a tile.
-+	 *	0x0 - DISPLAY_MICRO_TILING
-+	 *	0x1 - THIN_MICRO_TILING
-+	 *	0x2 - DEPTH_MICRO_TILING
-+	 *	0x3 - ROTATED_MICRO_TILING
-+	 */
-+	enum tile_mode_values tile_mode;
-+	/* Specifies the number of pipes and how they are
-+	 *	interleaved in the surface.
-+	 * Refer to memory addressing document for complete
-+	 *	details and constraints.
-+	 */
-+	unsigned int pipe_config;
-+	/* Specifies the tiling mode of the surface.
-+	 * THIN tiles use an 8x8x1 tile size.
-+	 * THICK tiles use an 8x8x4 tile size.
-+	 * 2D tiling modes rotate banks for successive Z slices
-+	 * 3D tiling modes rotate pipes and banks for Z slices
-+	 * Refer to memory addressing document for complete
-+	 *	details and constraints.
-+	 */
-+	enum array_mode_values array_mode;
- };
- 
- union plane_size {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index b70c8e1..5d3d0f7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -157,9 +157,6 @@ static void program_addr(
- 			addr->grph_stereo.right_addr);
- 		break;
- 	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
--	case PLN_ADDR_TYPE_VIDEO_INTERLACED:
--	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO:
--	case PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO:
- 	default:
- 		/* not supported */
- 		BREAK_TO_DEBUGGER();
-@@ -179,7 +176,7 @@ static void enable(struct dce110_mem_input *mem_input110)
- 
- static void program_tiling(
- 	struct dce110_mem_input *mem_input110,
--	const union dc_tiling_info *info,
-+	const struct dc_tiling_info *info,
- 	const enum surface_pixel_format pixel_format)
- {
- 	uint32_t value = 0;
-@@ -188,28 +185,28 @@ static void program_tiling(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_CONTROL));
- 
--	set_reg_field_value(value, info->grph.NUM_BANKS,
-+	set_reg_field_value(value, info->num_banks,
- 		GRPH_CONTROL, GRPH_NUM_BANKS);
- 
--	set_reg_field_value(value, info->grph.BANK_WIDTH,
-+	set_reg_field_value(value, info->bank_width,
- 		GRPH_CONTROL, GRPH_BANK_WIDTH);
- 
--	set_reg_field_value(value, info->grph.BANK_HEIGHT,
-+	set_reg_field_value(value, info->bank_height,
- 		GRPH_CONTROL, GRPH_BANK_HEIGHT);
- 
--	set_reg_field_value(value, info->grph.TILE_ASPECT,
-+	set_reg_field_value(value, info->tile_aspect,
- 		GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT);
- 
--	set_reg_field_value(value, info->grph.TILE_SPLIT,
-+	set_reg_field_value(value, info->tile_split,
- 		GRPH_CONTROL, GRPH_TILE_SPLIT);
- 
--	set_reg_field_value(value, info->grph.TILE_MODE,
-+	set_reg_field_value(value, info->tile_mode,
- 		GRPH_CONTROL, GRPH_MICRO_TILE_MODE);
- 
--	set_reg_field_value(value, info->grph.PIPE_CONFIG,
-+	set_reg_field_value(value, info->pipe_config,
- 		GRPH_CONTROL, GRPH_PIPE_CONFIG);
- 
--	set_reg_field_value(value, info->grph.ARRAY_MODE,
-+	set_reg_field_value(value, info->array_mode,
- 		GRPH_CONTROL, GRPH_ARRAY_MODE);
- 
- 	set_reg_field_value(value, 1,
-@@ -458,7 +455,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- bool dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
- 	enum surface_pixel_format format,
--	union dc_tiling_info *tiling_info,
-+	struct dc_tiling_info *tiling_info,
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index cd19169..5a4e5fe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -109,7 +109,7 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- bool  dce110_mem_input_program_surface_config(
- 	struct mem_input *mem_input,
- 	enum surface_pixel_format format,
--	union dc_tiling_info *tiling_info,
-+	struct dc_tiling_info *tiling_info,
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 4d653ab..7d6335d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -57,7 +57,7 @@ struct mem_input_funcs {
- 	bool (*mem_input_program_surface_config)(
- 		struct mem_input *mem_input,
- 		enum surface_pixel_format format,
--		union dc_tiling_info *tiling_info,
-+		struct dc_tiling_info *tiling_info,
- 		union plane_size *plane_size,
- 		enum dc_rotation_angle rotation);
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0748-drm-amd-dal-Reset-clock-when-refcount-drops-to-0.patch b/common/recipes-kernel/linux/files/0748-drm-amd-dal-Reset-clock-when-refcount-drops-to-0.patch
deleted file mode 100644
index 107cd81f..00000000
--- a/common/recipes-kernel/linux/files/0748-drm-amd-dal-Reset-clock-when-refcount-drops-to-0.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 956addaed13b272c5129c2e6be79ccdacb89d04d Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Thu, 28 Jan 2016 11:25:57 -0500
-Subject: [PATCH 0748/1110] drm/amd/dal: Reset clock when refcount drops to 0.
-
-Also, don't share PLL for 2 dual link DVIs and set
-0xff mask for controlers when power down pll by BIOS table.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c           | 10 ++++++++++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c |  4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/clock_source.h           |  2 +-
- 4 files changed, 14 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index fcda0cb..65523e3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -66,8 +66,13 @@ void unreference_clock_source(
- 	for (i = 0; i < res_ctx->pool.clk_src_count; i++) {
- 		if (res_ctx->pool.clock_sources[i] == clock_source) {
- 			res_ctx->clock_source_ref_count[i]--;
-+
-+		if (res_ctx->clock_source_ref_count[i] == 0)
-+			clock_source->funcs->cs_power_down(clock_source);
- 		}
- 	}
-+
-+
- }
- 
- void reference_clock_source(
-@@ -101,6 +106,11 @@ static bool is_sharable_clk_src(
- 	if (id == CLOCK_SOURCE_ID_EXTERNAL)
- 		return false;
- 
-+	/* Sharing dual link is not working */
-+	if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK ||
-+			stream_with_clk_src->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-+			return false;
-+
- 	if(!is_same_timing(
- 		&stream_with_clk_src->public.timing, &stream->public.timing))
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index c5a081a..f0cf18f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -798,7 +798,7 @@ static bool dce110_program_pix_clk(
- }
- 
- static bool dce110_clock_source_power_down(
--		struct clock_source *clk_src, enum controller_id controller_id)
-+		struct clock_source *clk_src)
- {
- 	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
- 	enum bp_result bp_result;
-@@ -808,7 +808,7 @@ static bool dce110_clock_source_power_down(
- 		return true;
- 
- 	/* If Pixel Clock is 0 it means Power Down Pll*/
--	bp_pixel_clock_params.controller_id = controller_id;
-+	bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
- 	bp_pixel_clock_params.pll_id = clk_src->id;
- 	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 2981307..e1ed527 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -896,7 +896,7 @@ static void power_down_clock_sources(struct dc *dc)
- 
- 	for (i = 0; i < dc->res_pool.clk_src_count; i++) {
- 		if (dc->res_pool.clock_sources[i]->funcs->cs_power_down(
--				dc->res_pool.clock_sources[i], i+1) == false)
-+				dc->res_pool.clock_sources[i]) == false)
- 			dal_error("Failed to power down pll! (clk src index=%d)\n", i);
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
-index d7a9a0c..0120ee2 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
-@@ -158,7 +158,7 @@ struct calc_pll_clock_source {
- 
- struct clock_source_funcs {
- 	bool (*cs_power_down)(
--			struct clock_source *, enum controller_id);
-+			struct clock_source *);
- 	bool (*program_pix_clk)(struct clock_source *,
- 			struct pixel_clk_params *, struct pll_settings *);
- 	uint32_t (*get_pix_clk_dividers)(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0749-drm-amd-dal-Don-t-try-to-do-bandwidth-validation-on-.patch b/common/recipes-kernel/linux/files/0749-drm-amd-dal-Don-t-try-to-do-bandwidth-validation-on-.patch
deleted file mode 100644
index e1d75f2d..00000000
--- a/common/recipes-kernel/linux/files/0749-drm-amd-dal-Don-t-try-to-do-bandwidth-validation-on-.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From c236b72b86f24d361b03e203998bc69c74f295a1 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 28 Jan 2016 16:26:18 -0500
-Subject: [PATCH 0749/1110] drm/amd/dal: Don't try to do bandwidth validation
- on DCE 10
-
-Currently bandwidth calculation isn't implemented for DCE 10.
-Make sure we're not calling wrong bandwidth calc code.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 170 +--------------------
- 1 file changed, 2 insertions(+), 168 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 0c1757b..9d438a9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -772,176 +772,10 @@ enum dc_status dce100_validate_bandwidth(
- 	const struct dc *dc,
- 	struct validate_context *context)
- {
--	uint8_t i, j;
--	enum dc_status result = DC_ERROR_UNEXPECTED;
--	uint8_t number_of_displays = 0;
--	uint8_t max_htaps = 1;
--	uint8_t max_vtaps = 1;
--	bool all_displays_in_sync = true;
--	struct dc_crtc_timing prev_timing;
--
--	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
-+	/* TODO implement when needed */
- 
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct bw_calcs_input_single_display *disp = &context->
--				bw_mode_data.displays_data[number_of_displays];
--
--			if (target->status.surface_count == 0) {
--				disp->graphics_scale_ratio = bw_int_to_fixed(1);
--				disp->graphics_h_taps = 2;
--				disp->graphics_v_taps = 2;
--
--				/* TODO: remove when bw formula accepts taps per
--				 * display
--				 */
--				if (max_vtaps < 2)
--					max_vtaps = 2;
--				if (max_htaps < 2)
--					max_htaps = 2;
--
--			} else {
--				disp->graphics_scale_ratio =
--					fixed31_32_to_bw_fixed(
--						stream->ratios.vert.value);
--				disp->graphics_h_taps = stream->taps.h_taps;
--				disp->graphics_v_taps = stream->taps.v_taps;
--
--				/* TODO: remove when bw formula accepts taps per
--				 * display
--				 */
--				if (max_vtaps < stream->taps.v_taps)
--					max_vtaps = stream->taps.v_taps;
--				if (max_htaps < stream->taps.h_taps)
--					max_htaps = stream->taps.h_taps;
--			}
--
--			disp->graphics_src_width =
--					stream->public.timing.h_addressable;
--			disp->graphics_src_height =
--					stream->public.timing.v_addressable;
--			disp->h_total = stream->public.timing.h_total;
--			disp->pixel_rate = bw_frc_to_fixed(
--				stream->public.timing.pix_clk_khz, 1000);
--
--			/*TODO: get from surface*/
--			disp->graphics_bytes_per_pixel = 4;
--			disp->graphics_tiling_mode = bw_def_tiled;
--
--			/* DCE11 defaults*/
--			disp->graphics_lb_bpc = 10;
--			disp->graphics_interlace_mode = false;
--			disp->fbc_enable = false;
--			disp->lpt_enable = false;
--			disp->graphics_stereo_mode = bw_def_mono;
--			disp->underlay_mode = bw_def_none;
--
--			/*All displays will be synchronized if timings are all
--			 * the same
--			 */
--			if (number_of_displays != 0 && all_displays_in_sync)
--				if (dal_memcmp(&prev_timing,
--					&stream->public.timing,
--					sizeof(struct dc_crtc_timing)) != 0)
--					all_displays_in_sync = false;
--			if (number_of_displays == 0)
--				prev_timing = stream->public.timing;
--
--			number_of_displays++;
--		}
--	}
-+	return DC_OK;
- 
--	/* TODO: remove when bw formula accepts taps per
--	 * display
--	 */
--	context->bw_mode_data.displays_data[0].graphics_v_taps = max_vtaps;
--	context->bw_mode_data.displays_data[0].graphics_h_taps = max_htaps;
--
--	context->bw_mode_data.number_of_displays = number_of_displays;
--	context->bw_mode_data.display_synchronization_enabled =
--							all_displays_in_sync;
--
--	dal_logger_write(
--		dc->ctx->logger,
--		LOG_MAJOR_BWM,
--		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
--		"%s: start\n",
--		__func__);
--
--	if (!bw_calcs(
--			dc->ctx,
--			&dc->bw_dceip,
--			&dc->bw_vbios,
--			&context->bw_mode_data,
--			&context->bw_results))
--		result =  DC_FAIL_BANDWIDTH_VALIDATE;
--	else
--		result =  DC_OK;
--
--	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
--		dal_logger_write(dc->ctx->logger,
--			LOG_MAJOR_BWM,
--			LOG_MINOR_BWM_MODE_VALIDATION,
--			"%s: Bandwidth validation failed!",
--			__func__);
--
--	if (dal_memcmp(&dc->current_context.bw_results,
--			&context->bw_results, sizeof(context->bw_results))) {
--		struct log_entry log_entry;
--
--		dal_logger_open(
--			dc->ctx->logger,
--			&log_entry,
--			LOG_MAJOR_BWM,
--			LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
--		dal_logger_append(&log_entry, "%s: finish, numDisplays: %d\n"
--			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
--			"stutMark_b: %d stutMark_a: %d\n",
--			__func__, number_of_displays,
--			context->bw_results.nbp_state_change_wm_ns[0].b_mark,
--			context->bw_results.nbp_state_change_wm_ns[0].a_mark,
--			context->bw_results.urgent_wm_ns[0].b_mark,
--			context->bw_results.urgent_wm_ns[0].a_mark,
--			context->bw_results.stutter_exit_wm_ns[0].b_mark,
--			context->bw_results.stutter_exit_wm_ns[0].a_mark);
--		dal_logger_append(&log_entry,
--			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
--			"stutMark_b: %d stutMark_a: %d\n",
--			context->bw_results.nbp_state_change_wm_ns[1].b_mark,
--			context->bw_results.nbp_state_change_wm_ns[1].a_mark,
--			context->bw_results.urgent_wm_ns[1].b_mark,
--			context->bw_results.urgent_wm_ns[1].a_mark,
--			context->bw_results.stutter_exit_wm_ns[1].b_mark,
--			context->bw_results.stutter_exit_wm_ns[1].a_mark);
--		dal_logger_append(&log_entry,
--			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
--			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
--			context->bw_results.nbp_state_change_wm_ns[2].b_mark,
--			context->bw_results.nbp_state_change_wm_ns[2].a_mark,
--			context->bw_results.urgent_wm_ns[2].b_mark,
--			context->bw_results.urgent_wm_ns[2].a_mark,
--			context->bw_results.stutter_exit_wm_ns[2].b_mark,
--			context->bw_results.stutter_exit_wm_ns[2].a_mark,
--			context->bw_results.stutter_mode_enable);
--		dal_logger_append(&log_entry,
--			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
--			"sclk: %d sclk_sleep: %d yclk: %d blackout_duration: %d\n",
--			context->bw_results.cpuc_state_change_enable,
--			context->bw_results.cpup_state_change_enable,
--			context->bw_results.nbp_state_change_enable,
--			context->bw_results.all_displays_in_sync,
--			context->bw_results.dispclk_khz,
--			context->bw_results.required_sclk,
--			context->bw_results.required_sclk_deep_sleep,
--			context->bw_results.required_yclk,
--			context->bw_results.required_blackout_duration_us);
--		dal_logger_close(&log_entry);
--	}
--	return result;
- }
- 
- static void set_target_unchanged(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0750-drm-amd-dal-Set-correct-dentist-clock-value.patch b/common/recipes-kernel/linux/files/0750-drm-amd-dal-Set-correct-dentist-clock-value.patch
deleted file mode 100644
index 166d2725..00000000
--- a/common/recipes-kernel/linux/files/0750-drm-amd-dal-Set-correct-dentist-clock-value.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 07eb3e80e61e0fbe10f8df3158895ab785ec42aa Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Thu, 28 Jan 2016 18:49:24 -0500
-Subject: [PATCH 0750/1110] drm/amd/dal: Set correct dentist clock value
-
-Dentist VCO Frequency Clock
-APU uses Integrated Info Table.
-Discrete uses Frimware Info Table.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c | 11 +++++++++--
- 1 file changed, 9 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 9252b5c..7ff8a74 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -647,17 +647,24 @@ static bool display_clock_integrated_info_construct(
- 	struct adapter_service *as)
- {
- 	struct integrated_info info;
-+	struct firmware_info fw_info;
- 	uint32_t i;
- 	struct display_clock *base = &disp_clk->disp_clk_base;
- 	bool res;
- 
- 	dc_service_memset(&info, 0, sizeof(struct integrated_info));
-+	dc_service_memset(&fw_info, 0, sizeof(struct firmware_info));
- 
- 	res = dal_adapter_service_get_integrated_info(as, &info);
- 
- 	disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
--	if (disp_clk->dentist_vco_freq_khz == 0)
--		disp_clk->dentist_vco_freq_khz = 3600000;
-+	if (disp_clk->dentist_vco_freq_khz == 0) {
-+		dal_adapter_service_get_firmware_info(as, &fw_info);
-+		disp_clk->dentist_vco_freq_khz =
-+			fw_info.smu_gpu_pll_output_freq;
-+		if (disp_clk->dentist_vco_freq_khz == 0)
-+			disp_clk->dentist_vco_freq_khz = 3600000;
-+	}
- 
- 	base->min_display_clk_threshold_khz =
- 		disp_clk->dentist_vco_freq_khz / 64;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0751-drm-amd-dal-Rename-dc_services-helpers-to-dm_service.patch b/common/recipes-kernel/linux/files/0751-drm-amd-dal-Rename-dc_services-helpers-to-dm_service.patch
deleted file mode 100644
index ddba4f0a..00000000
--- a/common/recipes-kernel/linux/files/0751-drm-amd-dal-Rename-dc_services-helpers-to-dm_service.patch
+++ /dev/null
@@ -1,15053 +0,0 @@
-From 48a216deab451d0091b8b90f64e66275f6e99bba Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 29 Jan 2016 12:02:29 -0500
-Subject: [PATCH 0751/1110] drm/amd/dal: Rename dc_services/helpers to
- dm_services/helpers
-
-Also renaming functions to keep consistency.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile         |   2 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c    | 457 -------------------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c  | 474 --------------------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   6 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  | 473 ++++++++++++++++++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c  |   2 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |   9 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 457 +++++++++++++++++++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  11 +-
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  20 +-
- .../adapter/dce110/hw_ctx_adapter_service_dce110.c |  19 +-
- .../diagnostics/hw_ctx_adapter_service_diag.c      |   6 +-
- .../amd/dal/dc/adapter/hw_ctx_adapter_service.c    |   2 +-
- .../drm/amd/dal/dc/adapter/wireless_data_source.c  |   2 +-
- .../amd/dal/dc/asic_capability/asic_capability.c   |  10 +-
- .../dc/asic_capability/carrizo_asic_capability.c   |   6 +-
- .../dal/dc/asic_capability/tonga_asic_capability.c |   5 +-
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |   4 +-
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c |   9 +-
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c  | 155 +++----
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/conversion.c     |   3 +-
- drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c |   7 +-
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         |  44 +-
- .../gpu/drm/amd/dal/dc/basics/register_logger.c    |  28 +-
- drivers/gpu/drm/amd/dal/dc/basics/signal_types.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/basics/vector.c         |  32 +-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      |  48 +-
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    |  46 +-
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |   2 +-
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c |  34 +-
- .../dc/bios/dce110/command_table_helper_dce110.c   |   3 +-
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c |  11 +-
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        |   2 +-
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c   |  50 +--
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  56 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  38 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      |  26 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       |  29 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  10 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  22 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_sink.c          |  10 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |  13 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |   8 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  27 +-
- drivers/gpu/drm/amd/dal/dc/dc_helpers.h            |  98 -----
- drivers/gpu/drm/amd/dal/dc/dc_services.h           | 490 ---------------------
- drivers/gpu/drm/amd/dal/dc/dc_services_types.h     | 167 -------
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   2 +-
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |  18 +-
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  94 ++--
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    |  22 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c  | 108 ++---
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  44 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     |   4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c  |  32 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   |  96 ++--
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 123 +++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 132 +++---
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  63 +--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c |  24 +-
- .../drm/amd/dal/dc/dce110/dce110_opp_formatter.c   |  54 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c |  62 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  77 ++--
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  | 147 ++++---
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 147 ++++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   |   3 +-
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c |  32 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_gamut.c |  18 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c   |  80 ++--
- .../drm/amd/dal/dc/dce110/dce110_transform_sclv.c  |  50 +--
- drivers/gpu/drm/amd/dal/dc/dm_helpers.h            |  98 +++++
- drivers/gpu/drm/amd/dal/dc/dm_services.h           | 476 ++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h     | 167 +++++++
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c |  35 +-
- .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c |   3 +-
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c |  15 +-
- .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c   |   2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.c              |   8 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c  |   9 +-
- .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c  |   2 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c  |   9 +-
- .../dal/dc/gpio/diagnostics/hw_translate_diag.c    |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c        |   6 +-
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     |  14 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c           |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |   5 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c          |   9 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c      |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c      |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c           |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpio/irq.c              |   9 +-
- .../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c    |   2 +-
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c |   6 +-
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |  22 +-
- drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c     |   3 +-
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c     |  15 +-
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c   | 103 +++--
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c    |  76 ++--
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c    |  10 +-
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c   |  10 +-
- .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c    |   9 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c    |   3 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c     |   5 +-
- .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c  |   3 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c  |   5 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c  |  49 +--
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |   3 +-
- drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h       |   3 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               |   2 +-
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c |  12 +-
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |  12 +-
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.c  |   2 +-
- .../amd/dal/dc/virtual/virtual_stream_encoder.c    |   7 +-
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |   3 +-
- drivers/gpu/drm/amd/dal/include/fixed32_32.h       |   2 +-
- 122 files changed, 3055 insertions(+), 3076 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
- delete mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
- create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dc_helpers.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dc_services.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dc_services_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dm_helpers.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dm_services.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
-index 65ad370..0f365c6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
-@@ -7,7 +7,7 @@
- AMDGPUDM = amdgpu_dm_types.o amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o
- 
- ifneq ($(CONFIG_DRM_AMD_DAL),)
--AMDGPUDM += amdgpu_dal_services.o amdgpu_dc_helpers.o
-+AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o
- endif
- 
- subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-deleted file mode 100644
-index eec5313..0000000
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
-+++ /dev/null
-@@ -1,457 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include <linux/string.h>
--#include <linux/acpi.h>
--
--#include <drm/drmP.h>
--#include <drm/drm_crtc_helper.h>
--#include <drm/amdgpu_drm.h>
--#include "amdgpu.h"
--#include "dc_services.h"
--#include "amdgpu_dm.h"
--#include "amdgpu_dm_irq.h"
--#include "amdgpu_dm_types.h"
--#include "amdgpu_pm.h"
--
--/*
--#include "logger_interface.h"
--#include "acpimethod_atif.h"
--#include "amdgpu_powerplay.h"
--#include "amdgpu_notifications.h"
--*/
--
--/* if the pointer is not NULL, the allocated memory is zeroed */
--void *dc_service_alloc(struct dc_context *ctx, uint32_t size)
--{
--	return kzalloc(size, GFP_KERNEL);
--}
--
--/* Reallocate memory. The contents will remain unchanged.*/
--void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size)
--{
--	return krealloc(ptr, size, GFP_KERNEL);
--}
--
--void dc_service_memmove(void *dst, const void *src, uint32_t size)
--{
--	memmove(dst, src, size);
--}
--
--void dc_service_free(struct dc_context *ctx, void *p)
--{
--	kfree(p);
--}
--
--void dc_service_memset(void *p, int32_t c, uint32_t count)
--{
--	memset(p, c, count);
--}
--
--int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count)
--{
--	return memcmp(p1, p2, count);
--}
--
--int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count)
--{
--	return strncmp(p1, p2, count);
--}
--
--void dc_service_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
--{
--	if (milliseconds >= 20)
--		msleep(milliseconds);
--	else
--		usleep_range(milliseconds*1000, milliseconds*1000+1);
--}
--
--void dal_delay_in_nanoseconds(uint32_t nanoseconds)
--{
--	ndelay(nanoseconds);
--}
--
--void dc_service_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds)
--{
--	udelay(microseconds);
--}
--
--/******************************************************************************
-- * IRQ Interfaces.
-- *****************************************************************************/
--
--void dal_register_timer_interrupt(
--	struct dc_context *ctx,
--	struct dc_timer_interrupt_params *int_params,
--	interrupt_handler ih,
--	void *args)
--{
--	struct amdgpu_device *adev = ctx->driver_context;
--
--	if (!adev || !int_params) {
--		DRM_ERROR("DM_IRQ: invalid input!\n");
--		return;
--	}
--
--	if (int_params->int_context != INTERRUPT_LOW_IRQ_CONTEXT) {
--		/* only low irq ctx is supported. */
--		DRM_ERROR("DM_IRQ: invalid context: %d!\n",
--				int_params->int_context);
--		return;
--	}
--
--	amdgpu_dm_irq_register_timer(adev, int_params, ih, args);
--}
--
--void dal_isr_acquire_lock(struct dc_context *ctx)
--{
--	/*TODO*/
--}
--
--void dal_isr_release_lock(struct dc_context *ctx)
--{
--	/*TODO*/
--}
--
--/******************************************************************************
-- * End-of-IRQ Interfaces.
-- *****************************************************************************/
--
--bool dal_get_platform_info(struct dc_context *ctx,
--			struct platform_info_params *params)
--{
--	/*TODO*/
--	return false;
--}
--
--/**** power component interfaces ****/
--
--bool dc_service_pp_pre_dce_clock_change(
--		struct dc_context *ctx,
--		struct dal_to_power_info *input,
--		struct power_to_dal_info *output)
--{
--	/*TODO*/
--	return false;
--}
--
--bool dc_service_pp_apply_safe_state(
--		const struct dc_context *ctx)
--{
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--	struct amdgpu_device *adev = ctx->driver_context;
--
--	if (adev->pm.dpm_enabled) {
--		/* TODO: Does this require PreModeChange event to PPLIB? */
--	}
--
--	return true;
--#else
--	return false;
--#endif
--}
--
--bool dc_service_pp_apply_display_requirements(
--		const struct dc_context *ctx,
--		const struct dc_pp_display_configuration *pp_display_cfg)
--{
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--	struct amdgpu_device *adev = ctx->driver_context;
--
--	if (adev->pm.dpm_enabled) {
--
--		memset(&adev->pm.pm_display_cfg, 0,
--				sizeof(adev->pm.pm_display_cfg));
--
--		adev->pm.pm_display_cfg.cpu_cc6_disable =
--			pp_display_cfg->cpu_cc6_disable;
--
--		adev->pm.pm_display_cfg.cpu_pstate_disable =
--			pp_display_cfg->cpu_pstate_disable;
--
--		adev->pm.pm_display_cfg.cpu_pstate_separation_time =
--			pp_display_cfg->cpu_pstate_separation_time;
--
--		adev->pm.pm_display_cfg.nb_pstate_switch_disable =
--			pp_display_cfg->nb_pstate_switch_disable;
--
--		adev->pm.pm_display_cfg.num_display =
--				pp_display_cfg->display_count;
--		adev->pm.pm_display_cfg.num_path_including_non_display =
--				pp_display_cfg->display_count;
--
--		adev->pm.pm_display_cfg.min_core_set_clock =
--				pp_display_cfg->min_engine_clock_khz/10;
--		adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
--				pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
--		adev->pm.pm_display_cfg.min_mem_set_clock =
--				pp_display_cfg->min_memory_clock_khz/10;
--
--		adev->pm.pm_display_cfg.multi_monitor_in_sync =
--				pp_display_cfg->all_displays_in_sync;
--		adev->pm.pm_display_cfg.min_vblank_time =
--				pp_display_cfg->avail_mclk_switch_time_us;
--
--		adev->pm.pm_display_cfg.display_clk =
--				pp_display_cfg->disp_clk_khz/10;
--
--		adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
--				pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
--
--		adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
--		adev->pm.pm_display_cfg.line_time_in_us =
--				pp_display_cfg->line_time_in_us;
--
--		adev->pm.pm_display_cfg.crossfire_display_index = -1;
--		adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
--
--		/* TODO: complete implementation of
--		 * amd_powerplay_display_configuration_change().
--		 * Follow example of:
--		 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
--		 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
--		amd_powerplay_display_configuration_change(
--				adev->powerplay.pp_handle,
--				&adev->pm.pm_display_cfg);
--
--		/* TODO: replace by a separate call to 'apply display cfg'? */
--		amdgpu_pm_compute_clocks(adev);
--	}
--
--	return true;
--#else
--	return false;
--#endif
--}
--
--bool dc_service_get_system_clocks_range(
--		const struct dc_context *ctx,
--		struct dal_system_clock_range *sys_clks)
--{
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--	struct amdgpu_device *adev = ctx->driver_context;
--#endif
--
--	/* Default values, in case PPLib is not compiled-in. */
--	sys_clks->max_mclk = 80000;
--	sys_clks->min_mclk = 80000;
--
--	sys_clks->max_sclk = 60000;
--	sys_clks->min_sclk = 30000;
--
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--	if (adev->pm.dpm_enabled) {
--		sys_clks->max_mclk = amdgpu_dpm_get_mclk(adev, false);
--		sys_clks->min_mclk = amdgpu_dpm_get_mclk(adev, true);
--
--		sys_clks->max_sclk = amdgpu_dpm_get_sclk(adev, false);
--		sys_clks->min_sclk = amdgpu_dpm_get_sclk(adev, true);
--	}
--#endif
--
--	return true;
--}
--
--static void get_default_clock_levels(
--		enum dc_pp_clock_type clk_type,
--		struct dc_pp_clock_levels *clks)
--{
--	uint32_t disp_clks_in_khz[6] = {
--			300000, 400000, 496560, 626090, 685720, 757900 };
--	uint32_t sclks_in_khz[6] = {
--			300000, 360000, 423530, 514290, 626090, 720000 };
--	uint32_t mclks_in_khz[2] = { 333000, 800000 };
--
--	switch (clk_type) {
--	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
--		clks->num_levels = 6;
--		dc_service_memmove(clks->clocks_in_khz, disp_clks_in_khz,
--				sizeof(disp_clks_in_khz));
--		break;
--	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
--		clks->num_levels = 6;
--		dc_service_memmove(clks->clocks_in_khz, sclks_in_khz,
--				sizeof(sclks_in_khz));
--		break;
--	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
--		clks->num_levels = 2;
--		dc_service_memmove(clks->clocks_in_khz, mclks_in_khz,
--				sizeof(mclks_in_khz));
--		break;
--	default:
--		clks->num_levels = 0;
--		break;
--	}
--}
--
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--static enum amd_pp_clock_type dc_to_pp_clock_type(
--		enum dc_pp_clock_type dc_pp_clk_type)
--{
--	enum amd_pp_clock_type amd_pp_clk_type = 0;
--
--	switch (dc_pp_clk_type) {
--	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
--		amd_pp_clk_type = amd_pp_disp_clock;
--		break;
--	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
--		amd_pp_clk_type = amd_pp_sys_clock;
--		break;
--	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
--		amd_pp_clk_type = amd_pp_mem_clock;
--		break;
--	default:
--		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
--				dc_pp_clk_type);
--		break;
--	}
--
--	return amd_pp_clk_type;
--}
--
--static void pp_to_dc_clock_levels(
--		const struct amd_pp_clocks *pp_clks,
--		struct dc_pp_clock_levels *dc_clks,
--		enum dc_pp_clock_type dc_clk_type)
--{
--	uint32_t i;
--
--	if (pp_clks->count > DC_PP_MAX_CLOCK_LEVELS) {
--		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
--				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
--				pp_clks->count,
--				DC_PP_MAX_CLOCK_LEVELS);
--
--		dc_clks->num_levels = DC_PP_MAX_CLOCK_LEVELS;
--	} else
--		dc_clks->num_levels = pp_clks->count;
--
--	DRM_INFO("DM_PPLIB: values for %s clock\n",
--			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
--
--	for (i = 0; i < dc_clks->num_levels; i++) {
--		DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
--		/* translate 10kHz to kHz */
--		dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
--	}
--}
--#endif
--
--bool dc_service_pp_get_clock_levels_by_type(
--		const struct dc_context *ctx,
--		enum dc_pp_clock_type clk_type,
--		struct dc_pp_clock_levels *dc_clks)
--{
--#ifdef CONFIG_DRM_AMD_POWERPLAY
--	struct amdgpu_device *adev = ctx->driver_context;
--	void *pp_handle = adev->powerplay.pp_handle;
--	struct amd_pp_clocks pp_clks = { 0 };
--	struct amd_pp_simple_clock_info validation_clks = { 0 };
--	uint32_t i;
--
--	if (amd_powerplay_get_clock_by_type(pp_handle,
--			dc_to_pp_clock_type(clk_type), &pp_clks)) {
--		/* Error in pplib. Provide default values. */
--		get_default_clock_levels(clk_type, dc_clks);
--		return true;
--	}
--
--	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
--
--	if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
--			&validation_clks)) {
--		/* Error in pplib. Provide default values. */
--		DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
--		validation_clks.engine_max_clock = 72000;
--		validation_clks.memory_max_clock = 80000;
--		validation_clks.level = 0;
--	}
--
--	DRM_INFO("DM_PPLIB: Validation clocks:\n");
--	DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
--			validation_clks.engine_max_clock);
--	DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
--			validation_clks.memory_max_clock);
--	DRM_INFO("DM_PPLIB:    level           : %d\n",
--			validation_clks.level);
--
--	/* Translate 10 kHz to kHz. */
--	validation_clks.engine_max_clock *= 10;
--	validation_clks.memory_max_clock *= 10;
--
--	/* Determine the highest non-boosted level from the Validation Clocks */
--	if (clk_type == DC_PP_CLOCK_TYPE_ENGINE_CLK) {
--		for (i = 0; i < dc_clks->num_levels; i++) {
--			if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
--				/* This clock is higher the validation clock.
--				 * Than means the previous one is the highest
--				 * non-boosted one. */
--				DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
--						dc_clks->num_levels, i + 1);
--				dc_clks->num_levels = i;
--				break;
--			}
--		}
--	} else if (clk_type == DC_PP_CLOCK_TYPE_MEMORY_CLK) {
--		for (i = 0; i < dc_clks->num_levels; i++) {
--			if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
--				DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
--						dc_clks->num_levels, i + 1);
--				dc_clks->num_levels = i;
--				break;
--			}
--		}
--	}
--#else
--	get_default_clock_levels(clk_type, dc_clks);
--#endif
--	return true;
--}
--
--/**** end of power component interfaces ****/
--
--
--/* Calls to notification */
--
--void dal_notify_setmode_complete(struct dc_context *ctx,
--	uint32_t h_total,
--	uint32_t v_total,
--	uint32_t h_active,
--	uint32_t v_active,
--	uint32_t pix_clk_in_khz)
--{
--	/*TODO*/
--}
--/* End of calls to notification */
--
--long dal_get_pid(void)
--{
--	return current->pid;
--}
--
--long dal_get_tgid(void)
--{
--	return current->tgid;
--}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-deleted file mode 100644
-index ab426e3..0000000
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dc_helpers.c
-+++ /dev/null
-@@ -1,474 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include <linux/string.h>
--#include <linux/acpi.h>
--
--#include <drm/drmP.h>
--#include <drm/drm_crtc_helper.h>
--#include <drm/amdgpu_drm.h>
--#include <drm/drm_edid.h>
--
--#include "amdgpu.h"
--#include "dc.h"
--#include "dc_services.h"
--
--#include "amdgpu_dm.h"
--#include "amdgpu_dm_irq.h"
--#include "amdgpu_dm_types.h"
--
--/* dc_helpers_parse_edid_caps
-- *
-- * Parse edid caps
-- *
-- * @edid:	[in] pointer to edid
-- *  edid_caps:	[in] pointer to edid caps
-- * @return
-- *	void
-- * */
--enum dc_edid_status dc_helpers_parse_edid_caps(
--		struct dc_context *ctx,
--		const struct dc_edid *edid,
--		struct dc_edid_caps *edid_caps)
--{
--	struct edid *edid_buf = (struct edid *) edid->raw_edid;
--	struct cea_sad *sads;
--	int sad_count = -1;
--	int sadb_count = -1;
--	int i = 0;
--	int j = 0;
--	uint8_t *sadb = NULL;
--
--	enum dc_edid_status result = EDID_OK;
--
--	if (!edid_caps || !edid)
--		return EDID_BAD_INPUT;
--
--	if (!drm_edid_is_valid(edid_buf))
--		result = EDID_BAD_CHECKSUM;
--
--	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
--					((uint16_t) edid_buf->mfg_id[1])<<8;
--	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
--					((uint16_t) edid_buf->prod_code[1])<<8;
--	edid_caps->serial_number = edid_buf->serial;
--	edid_caps->manufacture_week = edid_buf->mfg_week;
--	edid_caps->manufacture_year = edid_buf->mfg_year;
--
--	/* One of the four detailed_timings stores the monitor name. It's
--	 * stored in an array of length 13. */
--	for (i = 0; i < 4; i++) {
--		if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
--			while (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] && j < 13) {
--				if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
--					break;
--
--				edid_caps->display_name[j] =
--					edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
--				j++;
--			}
--		}
--	}
--
--	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
--	if (sad_count <= 0) {
--		DRM_INFO("SADs count is: %d, don't need to read it\n",
--				sad_count);
--		return result;
--	}
--
--	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
--	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
--		struct cea_sad *sad = &sads[i];
--
--		edid_caps->audio_modes[i].format_code = sad->format;
--		edid_caps->audio_modes[i].channel_count = sad->channels;
--		edid_caps->audio_modes[i].sample_rate = sad->freq;
--		edid_caps->audio_modes[i].sample_size = sad->byte2;
--	}
--
--	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
--
--	if (sadb_count < 0) {
--		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
--		sadb_count = 0;
--	}
--
--	if (sadb_count)
--		edid_caps->speaker_flags = sadb[0];
--	else
--		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
--
--	kfree(sads);
--	kfree(sadb);
--
--	return result;
--}
--
--
--static struct amdgpu_connector *get_connector_for_sink(
--	struct drm_device *dev,
--	const struct dc_sink *sink)
--{
--	struct drm_connector *connector;
--	struct amdgpu_connector *aconnector = NULL;
--
--	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--		aconnector = to_amdgpu_connector(connector);
--		if (aconnector->dc_sink == sink)
--			break;
--	}
--
--	return aconnector;
--}
--
--static struct amdgpu_connector *get_connector_for_link(
--	struct drm_device *dev,
--	const struct dc_link *link)
--{
--	struct drm_connector *connector;
--	struct amdgpu_connector *aconnector = NULL;
--
--	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--		aconnector = to_amdgpu_connector(connector);
--		if (aconnector->dc_link == link)
--			break;
--	}
--
--	return aconnector;
--}
--
--static void get_payload_table(
--		struct amdgpu_connector *aconnector,
--		struct dp_mst_stream_allocation_table *proposed_table)
--{
--	int i;
--	struct drm_dp_mst_topology_mgr *mst_mgr =
--			&aconnector->mst_port->mst_mgr;
--
--	mutex_lock(&mst_mgr->payload_lock);
--
--	proposed_table->stream_count = 0;
--
--	/* number of active streams */
--	for (i = 0; i < mst_mgr->max_payloads; i++) {
--		if (mst_mgr->payloads[i].num_slots == 0)
--			break; /* end of vcp_id table */
--
--		ASSERT(mst_mgr->payloads[i].payload_state !=
--				DP_PAYLOAD_DELETE_LOCAL);
--
--		if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
--			mst_mgr->payloads[i].payload_state ==
--					DP_PAYLOAD_REMOTE) {
--
--			struct dp_mst_stream_allocation *sa =
--					&proposed_table->stream_allocations[
--						proposed_table->stream_count];
--
--			sa->slot_count = mst_mgr->payloads[i].num_slots;
--			sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
--			proposed_table->stream_count++;
--		}
--	}
--
--	mutex_unlock(&mst_mgr->payload_lock);
--}
--
--/*
-- * Writes payload allocation table in immediate downstream device.
-- */
--bool dc_helpers_dp_mst_write_payload_allocation_table(
--		struct dc_context *ctx,
--		const struct dc_stream *stream,
--		struct dp_mst_stream_allocation_table *proposed_table,
--		bool enable)
--{
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector;
--	struct drm_dp_mst_topology_mgr *mst_mgr;
--	struct drm_dp_mst_port *mst_port;
--	int slots = 0;
--	bool ret;
--	int clock;
--	int bpp = 0;
--	int pbn = 0;
--
--	aconnector = get_connector_for_sink(dev, stream->sink);
--
--	if (!aconnector->mst_port)
--		return false;
--
--	mst_mgr = &aconnector->mst_port->mst_mgr;
--
--	if (!mst_mgr->mst_state)
--		return false;
--
--	mst_port = aconnector->port;
--
--	if (enable) {
--		clock = stream->timing.pix_clk_khz;
--
--		switch (stream->timing.display_color_depth) {
--
--		case COLOR_DEPTH_666:
--			bpp = 6;
--			break;
--		case COLOR_DEPTH_888:
--			bpp = 8;
--			break;
--		case COLOR_DEPTH_101010:
--			bpp = 10;
--			break;
--		case COLOR_DEPTH_121212:
--			bpp = 12;
--			break;
--		case COLOR_DEPTH_141414:
--			bpp = 14;
--			break;
--		case COLOR_DEPTH_161616:
--			bpp = 16;
--			break;
--		default:
--			ASSERT(bpp != 0);
--			break;
--		}
--
--		bpp = bpp * 3;
--
--		/* TODO need to know link rate */
--
--		pbn = drm_dp_calc_pbn_mode(clock, bpp);
--
--		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, &slots);
--
--		if (!ret)
--			return false;
--
--	} else {
--		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
--	}
--
--	ret = drm_dp_update_payload_part1(mst_mgr);
--
--	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
--	 * AUX message. The sequence is slot 1-63 allocated sequence for each
--	 * stream. AMD ASIC stream slot allocation should follow the same
--	 * sequence. copy DRM MST allocation to dc */
--
--	get_payload_table(aconnector, proposed_table);
--
--	if (ret)
--		return false;
--
--	return true;
--}
--
--/*
-- * Polls for ACT (allocation change trigger) handled and sends
-- * ALLOCATE_PAYLOAD message.
-- */
--bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
--		struct dc_context *ctx,
--		const struct dc_stream *stream)
--{
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector;
--	struct drm_dp_mst_topology_mgr *mst_mgr;
--	int ret;
--
--	aconnector = get_connector_for_sink(dev, stream->sink);
--
--	if (!aconnector->mst_port)
--		return false;
--
--	mst_mgr = &aconnector->mst_port->mst_mgr;
--
--	if (!mst_mgr->mst_state)
--		return false;
--
--	ret = drm_dp_check_act_status(mst_mgr);
--
--	if (ret)
--		return false;
--
--	return true;
--}
--
--bool dc_helpers_dp_mst_send_payload_allocation(
--		struct dc_context *ctx,
--		const struct dc_stream *stream,
--		bool enable)
--{
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector;
--	struct drm_dp_mst_topology_mgr *mst_mgr;
--	struct drm_dp_mst_port *mst_port;
--	int ret;
--
--	aconnector = get_connector_for_sink(dev, stream->sink);
--
--	mst_port = aconnector->port;
--
--	if (!aconnector->mst_port)
--		return false;
--
--	mst_mgr = &aconnector->mst_port->mst_mgr;
--
--	if (!mst_mgr->mst_state)
--		return false;
--
--	ret = drm_dp_update_payload_part2(mst_mgr);
--
--	if (ret)
--		return false;
--
--	if (!enable)
--		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
--
--	return true;
--}
--
--void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
--{
--	uint8_t esi[8] = { 0 };
--	uint8_t dret;
--	bool new_irq_handled = true;
--	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
--
--	/* DPCD 0x2002 - 0x2008 for down stream IRQ from MST, eDP etc. */
--	dret = drm_dp_dpcd_read(
--		&aconnector->dm_dp_aux.aux,
--		DP_SINK_COUNT_ESI, esi, 8);
--
--	while ((dret == 8) && new_irq_handled) {
--		uint8_t retry;
--
--		DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
--
--		/* handle HPD short pulse irq */
--		drm_dp_mst_hpd_irq(&aconnector->mst_mgr, esi, &new_irq_handled);
--
--		if (new_irq_handled) {
--			/* ACK at DPCD to notify down stream */
--			for (retry = 0; retry < 3; retry++) {
--				uint8_t wret;
--
--				wret = drm_dp_dpcd_write(
--					&aconnector->dm_dp_aux.aux,
--					DP_SINK_COUNT_ESI + 1,
--					&esi[1],
--					3);
--				if (wret == 3)
--					break;
--			}
--
--			/* check if there is new irq to be handle */
--			dret = drm_dp_dpcd_read(
--				&aconnector->dm_dp_aux.aux,
--				DP_SINK_COUNT_ESI, esi, 8);
--		}
--	}
--}
--
--bool dc_helpers_dp_mst_start_top_mgr(
--		struct dc_context *ctx,
--		const struct dc_link *link,
--		bool boot)
--{
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
--
--	if (boot) {
--		DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
--					aconnector, aconnector->base.base.id);
--		return true;
--	}
--
--	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
--			aconnector, aconnector->base.base.id);
--
--	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
--}
--
--void dc_helpers_dp_mst_stop_top_mgr(
--		struct dc_context *ctx,
--		const struct dc_link *link)
--{
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
--
--	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
--			aconnector, aconnector->base.base.id);
--
--	if (aconnector->mst_mgr.mst_state == true)
--		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
--}
--
--bool dc_helper_dp_read_dpcd(
--		struct dc_context *ctx,
--		const struct dc_link *link,
--		uint32_t address,
--		uint8_t *data,
--		uint32_t size) {
--
--
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
--
--	if (!aconnector) {
--		DRM_ERROR("Failed to found connector for link!");
--		return false;
--	}
--
--	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
--			data, size) > 0;
--}
--
--bool dc_helper_dp_write_dpcd(
--		struct dc_context *ctx,
--		const struct dc_link *link,
--		uint32_t address,
--		const uint8_t *data,
--		uint32_t size) {
--
--	struct amdgpu_device *adev = ctx->driver_context;
--	struct drm_device *dev = adev->ddev;
--	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
--
--	if (!aconnector) {
--		DRM_ERROR("Failed to found connector for link!");
--		return false;
--	}
--
--	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
--			address, (uint8_t *)data, size) > 0;
--}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index bb65892..47de461 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- #include "dc.h"
- 
- #include "vid.h"
-@@ -34,7 +34,7 @@
- 
- #include "amd_shared.h"
- #include "amdgpu_dm_irq.h"
--#include "dc_helpers.h"
-+#include "dm_helpers.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -939,7 +939,7 @@ static void handle_hpd_rx_irq(void *param)
- 	}
- 
- 	if (is_mst_root_connector)
--		dc_helpers_dp_mst_handle_mst_hpd_rx_irq(param);
-+		dm_helpers_dp_mst_handle_mst_hpd_rx_irq(param);
- }
- 
- static void register_hpd_handlers(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-new file mode 100644
-index 0000000..e2c68fd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -0,0 +1,473 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/string.h>
-+#include <linux/acpi.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/amdgpu_drm.h>
-+#include <drm/drm_edid.h>
-+
-+#include "dm_services.h"
-+#include "amdgpu.h"
-+#include "dc.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+#include "amdgpu_dm_types.h"
-+
-+/* dm_helpers_parse_edid_caps
-+ *
-+ * Parse edid caps
-+ *
-+ * @edid:	[in] pointer to edid
-+ *  edid_caps:	[in] pointer to edid caps
-+ * @return
-+ *	void
-+ * */
-+enum dc_edid_status dm_helpers_parse_edid_caps(
-+		struct dc_context *ctx,
-+		const struct dc_edid *edid,
-+		struct dc_edid_caps *edid_caps)
-+{
-+	struct edid *edid_buf = (struct edid *) edid->raw_edid;
-+	struct cea_sad *sads;
-+	int sad_count = -1;
-+	int sadb_count = -1;
-+	int i = 0;
-+	int j = 0;
-+	uint8_t *sadb = NULL;
-+
-+	enum dc_edid_status result = EDID_OK;
-+
-+	if (!edid_caps || !edid)
-+		return EDID_BAD_INPUT;
-+
-+	if (!drm_edid_is_valid(edid_buf))
-+		result = EDID_BAD_CHECKSUM;
-+
-+	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
-+					((uint16_t) edid_buf->mfg_id[1])<<8;
-+	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
-+					((uint16_t) edid_buf->prod_code[1])<<8;
-+	edid_caps->serial_number = edid_buf->serial;
-+	edid_caps->manufacture_week = edid_buf->mfg_week;
-+	edid_caps->manufacture_year = edid_buf->mfg_year;
-+
-+	/* One of the four detailed_timings stores the monitor name. It's
-+	 * stored in an array of length 13. */
-+	for (i = 0; i < 4; i++) {
-+		if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
-+			while (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] && j < 13) {
-+				if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
-+					break;
-+
-+				edid_caps->display_name[j] =
-+					edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
-+				j++;
-+			}
-+		}
-+	}
-+
-+	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
-+	if (sad_count <= 0) {
-+		DRM_INFO("SADs count is: %d, don't need to read it\n",
-+				sad_count);
-+		return result;
-+	}
-+
-+	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
-+	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
-+		struct cea_sad *sad = &sads[i];
-+
-+		edid_caps->audio_modes[i].format_code = sad->format;
-+		edid_caps->audio_modes[i].channel_count = sad->channels;
-+		edid_caps->audio_modes[i].sample_rate = sad->freq;
-+		edid_caps->audio_modes[i].sample_size = sad->byte2;
-+	}
-+
-+	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
-+
-+	if (sadb_count < 0) {
-+		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
-+		sadb_count = 0;
-+	}
-+
-+	if (sadb_count)
-+		edid_caps->speaker_flags = sadb[0];
-+	else
-+		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
-+
-+	kfree(sads);
-+	kfree(sadb);
-+
-+	return result;
-+}
-+
-+
-+static struct amdgpu_connector *get_connector_for_sink(
-+	struct drm_device *dev,
-+	const struct dc_sink *sink)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector = NULL;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (aconnector->dc_sink == sink)
-+			break;
-+	}
-+
-+	return aconnector;
-+}
-+
-+static struct amdgpu_connector *get_connector_for_link(
-+	struct drm_device *dev,
-+	const struct dc_link *link)
-+{
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector = NULL;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (aconnector->dc_link == link)
-+			break;
-+	}
-+
-+	return aconnector;
-+}
-+
-+static void get_payload_table(
-+		struct amdgpu_connector *aconnector,
-+		struct dp_mst_stream_allocation_table *proposed_table)
-+{
-+	int i;
-+	struct drm_dp_mst_topology_mgr *mst_mgr =
-+			&aconnector->mst_port->mst_mgr;
-+
-+	mutex_lock(&mst_mgr->payload_lock);
-+
-+	proposed_table->stream_count = 0;
-+
-+	/* number of active streams */
-+	for (i = 0; i < mst_mgr->max_payloads; i++) {
-+		if (mst_mgr->payloads[i].num_slots == 0)
-+			break; /* end of vcp_id table */
-+
-+		ASSERT(mst_mgr->payloads[i].payload_state !=
-+				DP_PAYLOAD_DELETE_LOCAL);
-+
-+		if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
-+			mst_mgr->payloads[i].payload_state ==
-+					DP_PAYLOAD_REMOTE) {
-+
-+			struct dp_mst_stream_allocation *sa =
-+					&proposed_table->stream_allocations[
-+						proposed_table->stream_count];
-+
-+			sa->slot_count = mst_mgr->payloads[i].num_slots;
-+			sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
-+			proposed_table->stream_count++;
-+		}
-+	}
-+
-+	mutex_unlock(&mst_mgr->payload_lock);
-+}
-+
-+/*
-+ * Writes payload allocation table in immediate downstream device.
-+ */
-+bool dm_helpers_dp_mst_write_payload_allocation_table(
-+		struct dc_context *ctx,
-+		const struct dc_stream *stream,
-+		struct dp_mst_stream_allocation_table *proposed_table,
-+		bool enable)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	struct drm_dp_mst_port *mst_port;
-+	int slots = 0;
-+	bool ret;
-+	int clock;
-+	int bpp = 0;
-+	int pbn = 0;
-+
-+	aconnector = get_connector_for_sink(dev, stream->sink);
-+
-+	if (!aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
-+	mst_port = aconnector->port;
-+
-+	if (enable) {
-+		clock = stream->timing.pix_clk_khz;
-+
-+		switch (stream->timing.display_color_depth) {
-+
-+		case COLOR_DEPTH_666:
-+			bpp = 6;
-+			break;
-+		case COLOR_DEPTH_888:
-+			bpp = 8;
-+			break;
-+		case COLOR_DEPTH_101010:
-+			bpp = 10;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			bpp = 12;
-+			break;
-+		case COLOR_DEPTH_141414:
-+			bpp = 14;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			bpp = 16;
-+			break;
-+		default:
-+			ASSERT(bpp != 0);
-+			break;
-+		}
-+
-+		bpp = bpp * 3;
-+
-+		/* TODO need to know link rate */
-+
-+		pbn = drm_dp_calc_pbn_mode(clock, bpp);
-+
-+		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, &slots);
-+
-+		if (!ret)
-+			return false;
-+
-+	} else {
-+		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
-+	}
-+
-+	ret = drm_dp_update_payload_part1(mst_mgr);
-+
-+	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
-+	 * AUX message. The sequence is slot 1-63 allocated sequence for each
-+	 * stream. AMD ASIC stream slot allocation should follow the same
-+	 * sequence. copy DRM MST allocation to dc */
-+
-+	get_payload_table(aconnector, proposed_table);
-+
-+	if (ret)
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * Polls for ACT (allocation change trigger) handled and sends
-+ * ALLOCATE_PAYLOAD message.
-+ */
-+bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		struct dc_context *ctx,
-+		const struct dc_stream *stream)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	int ret;
-+
-+	aconnector = get_connector_for_sink(dev, stream->sink);
-+
-+	if (!aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
-+	ret = drm_dp_check_act_status(mst_mgr);
-+
-+	if (ret)
-+		return false;
-+
-+	return true;
-+}
-+
-+bool dm_helpers_dp_mst_send_payload_allocation(
-+		struct dc_context *ctx,
-+		const struct dc_stream *stream,
-+		bool enable)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	struct drm_dp_mst_port *mst_port;
-+	int ret;
-+
-+	aconnector = get_connector_for_sink(dev, stream->sink);
-+
-+	mst_port = aconnector->port;
-+
-+	if (!aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
-+	ret = drm_dp_update_payload_part2(mst_mgr);
-+
-+	if (ret)
-+		return false;
-+
-+	if (!enable)
-+		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
-+
-+	return true;
-+}
-+
-+void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
-+{
-+	uint8_t esi[8] = { 0 };
-+	uint8_t dret;
-+	bool new_irq_handled = true;
-+	struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
-+
-+	/* DPCD 0x2002 - 0x2008 for down stream IRQ from MST, eDP etc. */
-+	dret = drm_dp_dpcd_read(
-+		&aconnector->dm_dp_aux.aux,
-+		DP_SINK_COUNT_ESI, esi, 8);
-+
-+	while ((dret == 8) && new_irq_handled) {
-+		uint8_t retry;
-+
-+		DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
-+
-+		/* handle HPD short pulse irq */
-+		drm_dp_mst_hpd_irq(&aconnector->mst_mgr, esi, &new_irq_handled);
-+
-+		if (new_irq_handled) {
-+			/* ACK at DPCD to notify down stream */
-+			for (retry = 0; retry < 3; retry++) {
-+				uint8_t wret;
-+
-+				wret = drm_dp_dpcd_write(
-+					&aconnector->dm_dp_aux.aux,
-+					DP_SINK_COUNT_ESI + 1,
-+					&esi[1],
-+					3);
-+				if (wret == 3)
-+					break;
-+			}
-+
-+			/* check if there is new irq to be handle */
-+			dret = drm_dp_dpcd_read(
-+				&aconnector->dm_dp_aux.aux,
-+				DP_SINK_COUNT_ESI, esi, 8);
-+		}
-+	}
-+}
-+
-+bool dm_helpers_dp_mst_start_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		bool boot)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (boot) {
-+		DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
-+					aconnector, aconnector->base.base.id);
-+		return true;
-+	}
-+
-+	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
-+			aconnector, aconnector->base.base.id);
-+
-+	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
-+}
-+
-+void dm_helpers_dp_mst_stop_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
-+			aconnector, aconnector->base.base.id);
-+
-+	if (aconnector->mst_mgr.mst_state == true)
-+		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+}
-+
-+bool dm_helper_dp_read_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size) {
-+
-+
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
-+			data, size) > 0;
-+}
-+
-+bool dm_helper_dp_write_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t size) {
-+
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
-+			address, (uint8_t *)data, size) > 0;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index b624229..9b5fd70 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -25,7 +25,7 @@
- 
- #include <drm/drmP.h>
- 
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- #include "dc.h"
- 
- #include "amdgpu.h"
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index f52b2f2..3f1d545 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -24,12 +24,13 @@
-  */
- 
- #include <drm/drm_atomic_helper.h>
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "amdgpu.h"
- #include "amdgpu_dm_types.h"
- #include "amdgpu_dm_mst_types.h"
-+
- #include "dc.h"
--#include "dc_helpers.h"
-+#include "dm_helpers.h"
- 
- /* #define TRACE_DPCD */
- 
-@@ -195,7 +196,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 	if (!dc_sink)
- 		return NULL;
- 
--	dc_service_memmove(dc_sink->dc_edid.raw_edid, edid, len);
-+	dm_memmove(dc_sink->dc_edid.raw_edid, edid, len);
- 	dc_sink->dc_edid.length = len;
- 
- 	if (!dc_link_add_remote_sink(
-@@ -203,7 +204,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 			dc_sink))
- 		goto fail_add_sink;
- 
--	edid_status = dc_helpers_parse_edid_caps(
-+	edid_status = dm_helpers_parse_edid_caps(
- 			NULL,
- 			&dc_sink->dc_edid,
- 			&dc_sink->edid_caps);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-new file mode 100644
-index 0000000..b155270
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -0,0 +1,457 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/string.h>
-+#include <linux/acpi.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/amdgpu_drm.h>
-+#include "dm_services.h"
-+#include "amdgpu.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+#include "amdgpu_dm_types.h"
-+#include "amdgpu_pm.h"
-+
-+/*
-+#include "logger_interface.h"
-+#include "acpimethod_atif.h"
-+#include "amdgpu_powerplay.h"
-+#include "amdgpu_notifications.h"
-+*/
-+
-+/* if the pointer is not NULL, the allocated memory is zeroed */
-+void *dm_alloc(struct dc_context *ctx, uint32_t size)
-+{
-+	return kzalloc(size, GFP_KERNEL);
-+}
-+
-+/* Reallocate memory. The contents will remain unchanged.*/
-+void *dm_realloc(struct dc_context *ctx, const void *ptr, uint32_t size)
-+{
-+	return krealloc(ptr, size, GFP_KERNEL);
-+}
-+
-+void dm_memmove(void *dst, const void *src, uint32_t size)
-+{
-+	memmove(dst, src, size);
-+}
-+
-+void dm_free(struct dc_context *ctx, void *p)
-+{
-+	kfree(p);
-+}
-+
-+void dm_memset(void *p, int32_t c, uint32_t count)
-+{
-+	memset(p, c, count);
-+}
-+
-+int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
-+{
-+	return memcmp(p1, p2, count);
-+}
-+
-+int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count)
-+{
-+	return strncmp(p1, p2, count);
-+}
-+
-+void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
-+{
-+	if (milliseconds >= 20)
-+		msleep(milliseconds);
-+	else
-+		usleep_range(milliseconds*1000, milliseconds*1000+1);
-+}
-+
-+void dal_delay_in_nanoseconds(uint32_t nanoseconds)
-+{
-+	ndelay(nanoseconds);
-+}
-+
-+void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds)
-+{
-+	udelay(microseconds);
-+}
-+
-+/******************************************************************************
-+ * IRQ Interfaces.
-+ *****************************************************************************/
-+
-+void dal_register_timer_interrupt(
-+	struct dc_context *ctx,
-+	struct dc_timer_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *args)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (!adev || !int_params) {
-+		DRM_ERROR("DM_IRQ: invalid input!\n");
-+		return;
-+	}
-+
-+	if (int_params->int_context != INTERRUPT_LOW_IRQ_CONTEXT) {
-+		/* only low irq ctx is supported. */
-+		DRM_ERROR("DM_IRQ: invalid context: %d!\n",
-+				int_params->int_context);
-+		return;
-+	}
-+
-+	amdgpu_dm_irq_register_timer(adev, int_params, ih, args);
-+}
-+
-+void dal_isr_acquire_lock(struct dc_context *ctx)
-+{
-+	/*TODO*/
-+}
-+
-+void dal_isr_release_lock(struct dc_context *ctx)
-+{
-+	/*TODO*/
-+}
-+
-+/******************************************************************************
-+ * End-of-IRQ Interfaces.
-+ *****************************************************************************/
-+
-+bool dm_get_platform_info(struct dc_context *ctx,
-+			struct platform_info_params *params)
-+{
-+	/*TODO*/
-+	return false;
-+}
-+
-+/**** power component interfaces ****/
-+
-+bool dm_pp_pre_dce_clock_change(
-+		struct dc_context *ctx,
-+		struct dal_to_power_info *input,
-+		struct power_to_dal_info *output)
-+{
-+	/*TODO*/
-+	return false;
-+}
-+
-+bool dm_pp_apply_safe_state(
-+		const struct dc_context *ctx)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (adev->pm.dpm_enabled) {
-+		/* TODO: Does this require PreModeChange event to PPLIB? */
-+	}
-+
-+	return true;
-+#else
-+	return false;
-+#endif
-+}
-+
-+bool dm_pp_apply_display_requirements(
-+		const struct dc_context *ctx,
-+		const struct dc_pp_display_configuration *pp_display_cfg)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (adev->pm.dpm_enabled) {
-+
-+		memset(&adev->pm.pm_display_cfg, 0,
-+				sizeof(adev->pm.pm_display_cfg));
-+
-+		adev->pm.pm_display_cfg.cpu_cc6_disable =
-+			pp_display_cfg->cpu_cc6_disable;
-+
-+		adev->pm.pm_display_cfg.cpu_pstate_disable =
-+			pp_display_cfg->cpu_pstate_disable;
-+
-+		adev->pm.pm_display_cfg.cpu_pstate_separation_time =
-+			pp_display_cfg->cpu_pstate_separation_time;
-+
-+		adev->pm.pm_display_cfg.nb_pstate_switch_disable =
-+			pp_display_cfg->nb_pstate_switch_disable;
-+
-+		adev->pm.pm_display_cfg.num_display =
-+				pp_display_cfg->display_count;
-+		adev->pm.pm_display_cfg.num_path_including_non_display =
-+				pp_display_cfg->display_count;
-+
-+		adev->pm.pm_display_cfg.min_core_set_clock =
-+				pp_display_cfg->min_engine_clock_khz/10;
-+		adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
-+				pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
-+		adev->pm.pm_display_cfg.min_mem_set_clock =
-+				pp_display_cfg->min_memory_clock_khz/10;
-+
-+		adev->pm.pm_display_cfg.multi_monitor_in_sync =
-+				pp_display_cfg->all_displays_in_sync;
-+		adev->pm.pm_display_cfg.min_vblank_time =
-+				pp_display_cfg->avail_mclk_switch_time_us;
-+
-+		adev->pm.pm_display_cfg.display_clk =
-+				pp_display_cfg->disp_clk_khz/10;
-+
-+		adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
-+				pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
-+
-+		adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
-+		adev->pm.pm_display_cfg.line_time_in_us =
-+				pp_display_cfg->line_time_in_us;
-+
-+		adev->pm.pm_display_cfg.crossfire_display_index = -1;
-+		adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
-+
-+		/* TODO: complete implementation of
-+		 * amd_powerplay_display_configuration_change().
-+		 * Follow example of:
-+		 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
-+		 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
-+		amd_powerplay_display_configuration_change(
-+				adev->powerplay.pp_handle,
-+				&adev->pm.pm_display_cfg);
-+
-+		/* TODO: replace by a separate call to 'apply display cfg'? */
-+		amdgpu_pm_compute_clocks(adev);
-+	}
-+
-+	return true;
-+#else
-+	return false;
-+#endif
-+}
-+
-+bool dc_service_get_system_clocks_range(
-+		const struct dc_context *ctx,
-+		struct dal_system_clock_range *sys_clks)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+#endif
-+
-+	/* Default values, in case PPLib is not compiled-in. */
-+	sys_clks->max_mclk = 80000;
-+	sys_clks->min_mclk = 80000;
-+
-+	sys_clks->max_sclk = 60000;
-+	sys_clks->min_sclk = 30000;
-+
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (adev->pm.dpm_enabled) {
-+		sys_clks->max_mclk = amdgpu_dpm_get_mclk(adev, false);
-+		sys_clks->min_mclk = amdgpu_dpm_get_mclk(adev, true);
-+
-+		sys_clks->max_sclk = amdgpu_dpm_get_sclk(adev, false);
-+		sys_clks->min_sclk = amdgpu_dpm_get_sclk(adev, true);
-+	}
-+#endif
-+
-+	return true;
-+}
-+
-+static void get_default_clock_levels(
-+		enum dc_pp_clock_type clk_type,
-+		struct dc_pp_clock_levels *clks)
-+{
-+	uint32_t disp_clks_in_khz[6] = {
-+			300000, 400000, 496560, 626090, 685720, 757900 };
-+	uint32_t sclks_in_khz[6] = {
-+			300000, 360000, 423530, 514290, 626090, 720000 };
-+	uint32_t mclks_in_khz[2] = { 333000, 800000 };
-+
-+	switch (clk_type) {
-+	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		clks->num_levels = 6;
-+		dm_memmove(clks->clocks_in_khz, disp_clks_in_khz,
-+				sizeof(disp_clks_in_khz));
-+		break;
-+	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+		clks->num_levels = 6;
-+		dm_memmove(clks->clocks_in_khz, sclks_in_khz,
-+				sizeof(sclks_in_khz));
-+		break;
-+	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+		clks->num_levels = 2;
-+		dm_memmove(clks->clocks_in_khz, mclks_in_khz,
-+				sizeof(mclks_in_khz));
-+		break;
-+	default:
-+		clks->num_levels = 0;
-+		break;
-+	}
-+}
-+
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+static enum amd_pp_clock_type dc_to_pp_clock_type(
-+		enum dc_pp_clock_type dc_pp_clk_type)
-+{
-+	enum amd_pp_clock_type amd_pp_clk_type = 0;
-+
-+	switch (dc_pp_clk_type) {
-+	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		amd_pp_clk_type = amd_pp_disp_clock;
-+		break;
-+	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+		amd_pp_clk_type = amd_pp_sys_clock;
-+		break;
-+	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+		amd_pp_clk_type = amd_pp_mem_clock;
-+		break;
-+	default:
-+		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
-+				dc_pp_clk_type);
-+		break;
-+	}
-+
-+	return amd_pp_clk_type;
-+}
-+
-+static void pp_to_dc_clock_levels(
-+		const struct amd_pp_clocks *pp_clks,
-+		struct dc_pp_clock_levels *dc_clks,
-+		enum dc_pp_clock_type dc_clk_type)
-+{
-+	uint32_t i;
-+
-+	if (pp_clks->count > DC_PP_MAX_CLOCK_LEVELS) {
-+		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
-+				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
-+				pp_clks->count,
-+				DC_PP_MAX_CLOCK_LEVELS);
-+
-+		dc_clks->num_levels = DC_PP_MAX_CLOCK_LEVELS;
-+	} else
-+		dc_clks->num_levels = pp_clks->count;
-+
-+	DRM_INFO("DM_PPLIB: values for %s clock\n",
-+			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
-+
-+	for (i = 0; i < dc_clks->num_levels; i++) {
-+		DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
-+		/* translate 10kHz to kHz */
-+		dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
-+	}
-+}
-+#endif
-+
-+bool dm_pp_get_clock_levels_by_type(
-+		const struct dc_context *ctx,
-+		enum dc_pp_clock_type clk_type,
-+		struct dc_pp_clock_levels *dc_clks)
-+{
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	void *pp_handle = adev->powerplay.pp_handle;
-+	struct amd_pp_clocks pp_clks = { 0 };
-+	struct amd_pp_simple_clock_info validation_clks = { 0 };
-+	uint32_t i;
-+
-+	if (amd_powerplay_get_clock_by_type(pp_handle,
-+			dc_to_pp_clock_type(clk_type), &pp_clks)) {
-+		/* Error in pplib. Provide default values. */
-+		get_default_clock_levels(clk_type, dc_clks);
-+		return true;
-+	}
-+
-+	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
-+
-+	if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
-+			&validation_clks)) {
-+		/* Error in pplib. Provide default values. */
-+		DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
-+		validation_clks.engine_max_clock = 72000;
-+		validation_clks.memory_max_clock = 80000;
-+		validation_clks.level = 0;
-+	}
-+
-+	DRM_INFO("DM_PPLIB: Validation clocks:\n");
-+	DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
-+			validation_clks.engine_max_clock);
-+	DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
-+			validation_clks.memory_max_clock);
-+	DRM_INFO("DM_PPLIB:    level           : %d\n",
-+			validation_clks.level);
-+
-+	/* Translate 10 kHz to kHz. */
-+	validation_clks.engine_max_clock *= 10;
-+	validation_clks.memory_max_clock *= 10;
-+
-+	/* Determine the highest non-boosted level from the Validation Clocks */
-+	if (clk_type == DC_PP_CLOCK_TYPE_ENGINE_CLK) {
-+		for (i = 0; i < dc_clks->num_levels; i++) {
-+			if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
-+				/* This clock is higher the validation clock.
-+				 * Than means the previous one is the highest
-+				 * non-boosted one. */
-+				DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
-+						dc_clks->num_levels, i + 1);
-+				dc_clks->num_levels = i;
-+				break;
-+			}
-+		}
-+	} else if (clk_type == DC_PP_CLOCK_TYPE_MEMORY_CLK) {
-+		for (i = 0; i < dc_clks->num_levels; i++) {
-+			if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
-+				DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
-+						dc_clks->num_levels, i + 1);
-+				dc_clks->num_levels = i;
-+				break;
-+			}
-+		}
-+	}
-+#else
-+	get_default_clock_levels(clk_type, dc_clks);
-+#endif
-+	return true;
-+}
-+
-+/**** end of power component interfaces ****/
-+
-+
-+/* Calls to notification */
-+
-+void dal_notify_setmode_complete(struct dc_context *ctx,
-+	uint32_t h_total,
-+	uint32_t v_total,
-+	uint32_t h_active,
-+	uint32_t v_active,
-+	uint32_t pix_clk_in_khz)
-+{
-+	/*TODO*/
-+}
-+/* End of calls to notification */
-+
-+long dm_get_pid(void)
-+{
-+	return current->pid;
-+}
-+
-+long dm_get_tgid(void)
-+{
-+	return current->tgid;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index d09f0ad..a8350e6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -23,15 +23,16 @@
-  *
-  */
- 
--#include "dc_services_types.h"
--
- #include <linux/types.h>
- #include <drm/drmP.h>
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_atomic.h>
-+
- #include "amdgpu.h"
- #include "amdgpu_pm.h"
-+#include "dm_services_types.h"
-+
- // We need to #undef FRAME_SIZE and DEPRECATED because they conflict
- // with ptrace-abi.h's #define's of them.
- #undef FRAME_SIZE
-@@ -625,7 +626,7 @@ static void dm_dc_surface_commit(
- 	struct dc_target *dc_target = acrtc->target;
- 
- 	if (!dc_target) {
--		dal_error(
-+		dm_error(
- 			"%s: Failed to obtain target on crtc (%d)!\n",
- 			__func__,
- 			acrtc->crtc_id);
-@@ -635,7 +636,7 @@ static void dm_dc_surface_commit(
- 	dc_surface = dc_create_surface(dc);
- 
- 	if (!dc_surface) {
--		dal_error(
-+		dm_error(
- 			"%s: Failed to create a surface!\n",
- 			__func__);
- 		goto fail;
-@@ -659,7 +660,7 @@ static void dm_dc_surface_commit(
- 			&dc_surface,
- 			1,
- 			dc_target)) {
--		dal_error(
-+		dm_error(
- 			"%s: Failed to attach surface!\n",
- 			__func__);
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 9fb1be8..73bfd4e 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -23,8 +23,7 @@
-  *
-  */
- 
--
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dc_bios_types.h"
- 
-@@ -36,6 +35,7 @@
- #include "include/logger_interface.h"
- 
- #include "adapter_service.h"
-+
- #include "hw_ctx_adapter_service.h"
- #include "wireless_data_source.h"
- 
-@@ -203,7 +203,7 @@ static void get_platform_info_methods(
- 	params.data = &mask;
- 	params.method = PM_GET_AVAILABLE_METHODS;
- 
--	if (dal_get_platform_info(as->ctx, &params))
-+	if (dm_get_platform_info(as->ctx, &params))
- 		as->platform_methods_mask = mask;
- 
- 
-@@ -235,7 +235,7 @@ static void initialize_backlight_caps(
- 	params.data = &caps;
- 	params.method = PM_GET_EXTENDED_BRIGHNESS_CAPS;
- 
--	if (dal_get_platform_info(as->ctx, &params)) {
-+	if (dm_get_platform_info(as->ctx, &params)) {
- 		as->ac_level_percentage = caps.basic_caps.ac_level_percentage;
- 		as->dc_level_percentage = caps.basic_caps.dc_level_percentage;
- 		custom_curve_present = (caps.data_points_num > 0);
-@@ -608,7 +608,7 @@ static bool generate_feature_set(
- 	uint32_t entry_num = 0;
- 	const struct feature_source_entry *entry = NULL;
- 
--	dc_service_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
-+	dm_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
- 	entry_num = get_feature_entries_num();
- 
- 
-@@ -850,7 +850,7 @@ struct adapter_service *dal_adapter_service_create(
- {
- 	struct adapter_service *as;
- 
--	as = dc_service_alloc(init_data->ctx, sizeof(struct adapter_service));
-+	as = dm_alloc(init_data->ctx, sizeof(struct adapter_service));
- 
- 	if (!as) {
- 		ASSERT_CRITICAL(false);
-@@ -862,7 +862,7 @@ struct adapter_service *dal_adapter_service_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(init_data->ctx, as);
-+	dm_free(init_data->ctx, as);
- 
- 	return NULL;
- }
-@@ -887,7 +887,7 @@ void dal_adapter_service_destroy(
- 
- 	adapter_service_destruct(*as);
- 
--	dc_service_free((*as)->ctx, *as);
-+	dm_free((*as)->ctx, *as);
- 
- 	*as = NULL;
- }
-@@ -1367,7 +1367,7 @@ bool dal_adapter_service_get_integrated_info(
- 	if (info == NULL || as->integrated_info == NULL)
- 		return false;
- 
--	dc_service_memmove(info, as->integrated_info, sizeof(struct integrated_info));
-+	dm_memmove(info, as->integrated_info, sizeof(struct integrated_info));
- 
- 	return true;
- }
-@@ -1974,7 +1974,7 @@ bool dal_adapter_service_is_lid_open(struct adapter_service *as)
- 	params.method = PM_GET_LID_STATE;
- 
- 	if ((PM_GET_LID_STATE & as->platform_methods_mask) &&
--		dal_get_platform_info(as->ctx, &params))
-+		dm_get_platform_info(as->ctx, &params))
- 		return is_lid_open;
- 
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-index 98b1475..f10bee6 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-@@ -23,7 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
-+
- #include "../hw_ctx_adapter_service.h"
- 
- #include "hw_ctx_adapter_service_dce110.h"
-@@ -86,7 +87,7 @@ static void destroy(
- 
- 	destruct(hw_ctx);
- 
--	dc_service_free(ptr->ctx, hw_ctx);
-+	dm_free(ptr->ctx, hw_ctx);
- }
- 
- /*
-@@ -141,10 +142,10 @@ static uint32_t get_number_of_connected_audio_endpoints_multistream(
- 			AZALIA_F0_CODEC_ENDPOINT_INDEX,
- 			AZALIA_ENDPOINT_REG_INDEX);
- 
--		dal_write_reg(ctx, audio_index_reg_offset[i], value);
-+		dm_write_reg(ctx, audio_index_reg_offset[i], value);
- 
- 		value = 0;
--		value = dal_read_reg(ctx, audio_data_reg_offset[i]);
-+		value = dm_read_reg(ctx, audio_data_reg_offset[i]);
- 
- 		/* 1 means not supported*/
- 		if (get_reg_field_value(value,
-@@ -173,7 +174,7 @@ static uint32_t get_number_of_connected_audio_endpoints(
- 		/* audio straps indicate no audio supported */
- 		return 0;
- 
--	value = dal_read_reg(hw_ctx->ctx, addr);
-+	value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 	field = get_reg_field_value(
- 			value, CC_DC_HDMI_STRAPS, AUDIO_STREAM_NUMBER);
-@@ -216,14 +217,14 @@ static bool power_up(
- 		uint32_t value = 0;
- 		uint32_t field = 0;
- 
--		value = dal_read_reg(hw_ctx->ctx, mmCC_DC_HDMI_STRAPS);
-+		value = dm_read_reg(hw_ctx->ctx, mmCC_DC_HDMI_STRAPS);
- 		field = get_reg_field_value(
- 				value, CC_DC_HDMI_STRAPS, HDMI_DISABLE);
- 
- 		if (field == 0) {
- 			hw_ctx->cached_audio_straps = AUDIO_STRAPS_DP_HDMI_AUDIO;
- 		} else {
--			value = dal_read_reg(
-+			value = dm_read_reg(
- 					hw_ctx->ctx, mmDC_PINSTRAPS);
- 			field = get_reg_field_value(
- 						value,
-@@ -285,7 +286,7 @@ struct hw_ctx_adapter_service *
- 			struct dc_context *ctx)
- {
- 	struct hw_ctx_adapter_service_dce110 *hw_ctx =
--			dc_service_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce110));
-+			dm_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce110));
- 
- 	if (!hw_ctx) {
- 		ASSERT_CRITICAL(false);
-@@ -297,7 +298,7 @@ struct hw_ctx_adapter_service *
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, hw_ctx);
-+	dm_free(ctx, hw_ctx);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-index ba377f4..4f5f040 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-@@ -25,7 +25,7 @@
- 
- /* FPGA Diagnostics version of AS HW CTX. */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "../hw_ctx_adapter_service.h"
- 
-@@ -112,7 +112,7 @@ static bool construct(
- struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
- 	struct dc_context *ctx)
- {
--	struct hw_ctx_adapter_service *hw_ctx = dc_service_alloc(ctx,
-+	struct hw_ctx_adapter_service *hw_ctx = dm_alloc(ctx,
- 			sizeof(*hw_ctx));
- 
- 	if (!hw_ctx) {
-@@ -125,7 +125,7 @@ struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, hw_ctx);
-+	dm_free(ctx, hw_ctx);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-index 0d13a90..12eabe0 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/adapter_service_types.h"
- #include "include/grph_object_id.h"
- #include "hw_ctx_adapter_service.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-index 122222e..0b1151e 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-@@ -24,7 +24,7 @@
-  */
- 
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "adapter_service.h"
- #include "wireless_data_source.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index 05a92a4..7a905f5 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/logger_interface.h"
- 
-@@ -51,7 +51,7 @@ static bool construct(
- 	bool asic_supported = false;
- 
- 	cap->ctx = ctx;
--	dc_service_memset(cap->data, 0, sizeof(cap->data));
-+	dm_memset(cap->data, 0, sizeof(cap->data));
- 
- 	/* ASIC data */
- 	cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
-@@ -147,7 +147,7 @@ struct asic_capability *dal_asic_capability_create(
- 		return NULL;
- 	}
- 
--	cap = dc_service_alloc(ctx, sizeof(struct asic_capability));
-+	cap = dm_alloc(ctx, sizeof(struct asic_capability));
- 
- 	if (!cap) {
- 		BREAK_TO_DEBUGGER();
-@@ -159,7 +159,7 @@ struct asic_capability *dal_asic_capability_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dc_service_free(ctx, cap);
-+	dm_free(ctx, cap);
- 
- 	return NULL;
- }
-@@ -184,7 +184,7 @@ void dal_asic_capability_destroy(
- 
- 	destruct(*cap);
- 
--	dc_service_free((*cap)->ctx, *cap);
-+	dm_free((*cap)->ctx, *cap);
- 
- 	*cap = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-index 1de790d..4aa8c30 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/asic_capability_interface.h"
- #include "include/asic_capability_types.h"
-@@ -36,7 +36,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- #include "dal_asic_id.h"
- 
--#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS     0xC0014074
-+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
- 
- /*
-  * carrizo_asic_capability_create
-@@ -85,7 +85,7 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
- 	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
- 	cap->stereo_3d_caps.INTERLEAVE = true;
- 
--    e_fuse_setting = dal_read_index_reg(cap->ctx,CGS_IND_REG__SMC,ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-+	e_fuse_setting = dm_read_index_reg(cap->ctx,CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
- 
- 	/* Bits [28:27]*/
- 	switch ((e_fuse_setting >> 27) & 0x3) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-index 7cd0b80..af669c8 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/asic_capability_interface.h"
- #include "include/asic_capability_types.h"
-@@ -90,8 +90,7 @@ void tonga_asic_capability_create(struct asic_capability *cap,
- 	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
- 	cap->stereo_3d_caps.INTERLEAVE = true;
- 
--	e_fuse_setting = dal_read_index_reg(cap->ctx, CGS_IND_REG__SMC,
--			ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-+	e_fuse_setting = dm_read_index_reg(cap->ctx, CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
- 
- 	/* Bits [28:27]*/
- 	switch ((e_fuse_setting >> 27) & 0x3) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index 2311f29..bfd6725 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/logger_interface.h"
- 
-@@ -152,7 +152,7 @@ static struct audio_feature_support get_supported_features(struct audio *audio)
- 	/*DCE specific, must be implemented in derived*/
- 	struct audio_feature_support features;
- 
--	dc_service_memset(&features, 0, sizeof(features));
-+	dm_memset(&features, 0, sizeof(features));
- 
- 	features.ENGINE_DIGA = 1;
- 	features.ENGINE_DIGB = 1;
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-index 5927b12..1aa0c1e 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-@@ -23,7 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
-+
- #include "include/logger_interface.h"
- 
- #include "audio_dce110.h"
-@@ -52,7 +53,7 @@ static void destroy(struct audio **ptr)
- 	destruct(audio);
- 
- 	/* release memory allocated for audio_dce110*/
--	dc_service_free((*ptr)->ctx, audio);
-+	dm_free((*ptr)->ctx, audio);
- 	*ptr = NULL;
- }
- 
-@@ -425,7 +426,7 @@ struct audio *dal_audio_create_dce110(
- 	const struct audio_init_data *init_data)
- {
- 	/*allocate memory for audio_dce110 */
--	struct audio_dce110 *audio = dc_service_alloc(init_data->ctx, sizeof(*audio));
-+	struct audio_dce110 *audio = dm_alloc(init_data->ctx, sizeof(*audio));
- 
- 	if (audio == NULL) {
- 		ASSERT_CRITICAL(audio);
-@@ -442,7 +443,7 @@ struct audio *dal_audio_create_dce110(
- 		"Failed to create audio object for DCE11\n");
- 
- 	 /*release memory allocated if fail */
--	dc_service_free(init_data->ctx, audio);
-+	dm_free(init_data->ctx, audio);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-index 288f14f..f24b964 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -23,7 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
-+
- #include "include/logger_interface.h"
- #include "../hw_ctx_audio.h"
- #include "hw_ctx_audio_dce110.h"
-@@ -70,7 +71,7 @@ static void destroy(
- 
- 	destruct(hw_ctx_dce110);
- 	/* release memory allocated for struct hw_ctx_audio_dce110 */
--	dc_service_free((*ptr)->ctx, hw_ctx_dce110);
-+	dm_free((*ptr)->ctx, hw_ctx_dce110);
- 
- 	*ptr = NULL;
- }
-@@ -93,7 +94,7 @@ static void write_indirect_azalia_reg(
- 			AZALIA_F0_CODEC_ENDPOINT_INDEX,
- 			AZALIA_ENDPOINT_REG_INDEX);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-@@ -106,7 +107,7 @@ static void write_indirect_azalia_reg(
- 		set_reg_field_value(value, reg_data,
- 			AZALIA_F0_CODEC_ENDPOINT_DATA,
- 			AZALIA_ENDPOINT_REG_DATA);
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	dal_logger_write(
-@@ -136,7 +137,7 @@ static uint32_t read_indirect_azalia_reg(
- 			AZALIA_F0_CODEC_ENDPOINT_INDEX,
- 			AZALIA_ENDPOINT_REG_INDEX);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-@@ -145,7 +146,7 @@ static uint32_t read_indirect_azalia_reg(
- 			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
- 			azf0endpointx_azalia_f0_codec_endpoint_data;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		ret_val = value;
- 	}
- 
-@@ -349,7 +350,7 @@ static void setup_audio_wall_dto(
- {
- 	struct azalia_clock_info clock_info = { 0 };
- 
--	uint32_t value = dal_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
-+	uint32_t value = dm_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
- 
- 	/* TODO: GraphicsObject\inc\GraphicsObjectDefs.hpp(131):
- 	 *inline bool isHdmiSignal(SignalType signal)
-@@ -387,19 +388,19 @@ static void setup_audio_wall_dto(
- 				DCCG_AUDIO_DTO_SOURCE,
- 				DCCG_AUDIO_DTO_SEL);
- 
--			dal_write_reg(hw_ctx->ctx,
-+			dm_write_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO_SOURCE, value);
- 		}
- 
- 		/* module */
- 		{
--			value = dal_read_reg(hw_ctx->ctx,
-+			value = dm_read_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO0_MODULE);
- 			set_reg_field_value(value,
- 				clock_info.audio_dto_module,
- 				DCCG_AUDIO_DTO0_MODULE,
- 				DCCG_AUDIO_DTO0_MODULE);
--			dal_write_reg(hw_ctx->ctx,
-+			dm_write_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO0_MODULE, value);
- 		}
- 
-@@ -407,14 +408,14 @@ static void setup_audio_wall_dto(
- 		{
- 			value = 0;
- 
--			value = dal_read_reg(hw_ctx->ctx,
-+			value = dm_read_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO0_PHASE);
- 			set_reg_field_value(value,
- 				clock_info.audio_dto_phase,
- 				DCCG_AUDIO_DTO0_PHASE,
- 				DCCG_AUDIO_DTO0_PHASE);
- 
--			dal_write_reg(hw_ctx->ctx,
-+			dm_write_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO0_PHASE, value);
- 		}
- 
-@@ -448,7 +449,7 @@ static void setup_audio_wall_dto(
- 				DCCG_AUDIO_DTO2_USE_512FBR_DTO);
- 			*/
- 
--			dal_write_reg(hw_ctx->ctx,
-+			dm_write_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO_SOURCE, value);
- 		}
- 
-@@ -456,7 +457,7 @@ static void setup_audio_wall_dto(
- 		{
- 			value = 0;
- 
--			value = dal_read_reg(hw_ctx->ctx,
-+			value = dm_read_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO1_MODULE);
- 
- 			set_reg_field_value(value,
-@@ -464,7 +465,7 @@ static void setup_audio_wall_dto(
- 				DCCG_AUDIO_DTO1_MODULE,
- 				DCCG_AUDIO_DTO1_MODULE);
- 
--			dal_write_reg(hw_ctx->ctx,
-+			dm_write_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO1_MODULE, value);
- 		}
- 
-@@ -472,7 +473,7 @@ static void setup_audio_wall_dto(
- 		{
- 			value = 0;
- 
--			value = dal_read_reg(hw_ctx->ctx,
-+			value = dm_read_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO1_PHASE);
- 
- 			set_reg_field_value(value,
-@@ -480,7 +481,7 @@ static void setup_audio_wall_dto(
- 				DCCG_AUDIO_DTO1_PHASE,
- 				DCCG_AUDIO_DTO1_PHASE);
- 
--			dal_write_reg(hw_ctx->ctx,
-+			dm_write_reg(hw_ctx->ctx,
- 					mmDCCG_AUDIO_DTO1_PHASE, value);
- 		}
- 
-@@ -515,7 +516,7 @@ static void setup_hdmi_audio(
- 		addr =
- 			mmHDMI_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value, max_packets_per_line,
- 			HDMI_AUDIO_PACKET_CONTROL,
-@@ -525,27 +526,27 @@ static void setup_hdmi_audio(
- 			HDMI_AUDIO_PACKET_CONTROL,
- 			HDMI_AUDIO_DELAY_EN);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AFMT_AUDIO_PACKET_CONTROL */
- 	{
- 		addr = mmAFMT_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value, 1,
- 			AFMT_AUDIO_PACKET_CONTROL,
- 			AFMT_60958_CS_UPDATE);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AFMT_AUDIO_PACKET_CONTROL2 */
- 	{
- 		addr = mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value, 0,
- 				AFMT_AUDIO_PACKET_CONTROL2,
-@@ -556,14 +557,14 @@ static void setup_hdmi_audio(
- 			AFMT_AUDIO_PACKET_CONTROL2,
- 			AFMT_60958_OSF_OVRD);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* HDMI_ACR_PACKET_CONTROL */
- 	{
- 		addr = mmHDMI_ACR_PACKET_CONTROL + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value, 1,
- 			HDMI_ACR_PACKET_CONTROL,
- 			HDMI_ACR_AUTO_SEND);
-@@ -580,7 +581,7 @@ static void setup_hdmi_audio(
- 			HDMI_ACR_PACKET_CONTROL,
- 			HDMI_ACR_AUDIO_PRIORITY);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* Program audio clock sample/regeneration parameters */
-@@ -595,73 +596,73 @@ static void setup_hdmi_audio(
- 		{
- 			addr = mmHDMI_ACR_32_0 + engine_offset[engine_id];
- 
--			value = dal_read_reg(hw_ctx->ctx, addr);
-+			value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 			set_reg_field_value(value, audio_clock_info.cts_32khz,
- 				HDMI_ACR_32_0,
- 				HDMI_ACR_CTS_32);
- 
--			dal_write_reg(hw_ctx->ctx, addr, value);
-+			dm_write_reg(hw_ctx->ctx, addr, value);
- 		}
- 
- 		/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
- 		{
- 			addr = mmHDMI_ACR_32_1 + engine_offset[engine_id];
- 
--			value = dal_read_reg(hw_ctx->ctx, addr);
-+			value = dm_read_reg(hw_ctx->ctx, addr);
- 			set_reg_field_value(value, audio_clock_info.n_32khz,
- 				HDMI_ACR_32_1,
- 				HDMI_ACR_N_32);
- 
--			dal_write_reg(hw_ctx->ctx, addr, value);
-+			dm_write_reg(hw_ctx->ctx, addr, value);
- 		}
- 
- 		/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
- 		{
- 			addr = mmHDMI_ACR_44_0 + engine_offset[engine_id];
- 
--			value = dal_read_reg(hw_ctx->ctx, addr);
-+			value = dm_read_reg(hw_ctx->ctx, addr);
- 			set_reg_field_value(value, audio_clock_info.cts_44khz,
- 				HDMI_ACR_44_0,
- 				HDMI_ACR_CTS_44);
- 
--			dal_write_reg(hw_ctx->ctx, addr, value);
-+			dm_write_reg(hw_ctx->ctx, addr, value);
- 		}
- 
- 		/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
- 		{
- 			addr = mmHDMI_ACR_44_1 + engine_offset[engine_id];
- 
--			value = dal_read_reg(hw_ctx->ctx, addr);
-+			value = dm_read_reg(hw_ctx->ctx, addr);
- 			set_reg_field_value(value, audio_clock_info.n_44khz,
- 				HDMI_ACR_44_1,
- 				HDMI_ACR_N_44);
- 
--			dal_write_reg(hw_ctx->ctx, addr, value);
-+			dm_write_reg(hw_ctx->ctx, addr, value);
- 		}
- 
- 		/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
- 		{
- 			addr = mmHDMI_ACR_48_0 + engine_offset[engine_id];
- 
--			value = dal_read_reg(hw_ctx->ctx, addr);
-+			value = dm_read_reg(hw_ctx->ctx, addr);
- 			set_reg_field_value(value, audio_clock_info.cts_48khz,
- 				HDMI_ACR_48_0,
- 				HDMI_ACR_CTS_48);
- 
--			dal_write_reg(hw_ctx->ctx, addr, value);
-+			dm_write_reg(hw_ctx->ctx, addr, value);
- 		}
- 
- 		/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
- 		{
- 			addr = mmHDMI_ACR_48_1 + engine_offset[engine_id];
- 
--			value = dal_read_reg(hw_ctx->ctx, addr);
-+			value = dm_read_reg(hw_ctx->ctx, addr);
- 			set_reg_field_value(value, audio_clock_info.n_48khz,
- 				HDMI_ACR_48_1,
- 				HDMI_ACR_N_48);
- 
--			dal_write_reg(hw_ctx->ctx, addr, value);
-+			dm_write_reg(hw_ctx->ctx, addr, value);
- 		}
- 
- 		/* Video driver cannot know in advance which sample rate will
-@@ -675,7 +676,7 @@ static void setup_hdmi_audio(
- 	{
- 		addr = mmAFMT_60958_0 + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value, 1,
- 			AFMT_60958_0,
- 			AFMT_60958_CS_CHANNEL_NUMBER_L);
-@@ -685,19 +686,19 @@ static void setup_hdmi_audio(
- 			AFMT_60958_0,
- 			AFMT_60958_CS_CLOCK_ACCURACY);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
- 	{
- 		addr = mmAFMT_60958_1 + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value, 2,
- 			AFMT_60958_1,
- 			AFMT_60958_CS_CHANNEL_NUMBER_R);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/*AFMT_60958_2 now keep this settings until
-@@ -705,7 +706,7 @@ static void setup_hdmi_audio(
- 	{
- 		addr = mmAFMT_60958_2 + engine_offset[engine_id];
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value, 3,
- 			AFMT_60958_2,
- 			AFMT_60958_CS_CHANNEL_NUMBER_2);
-@@ -730,7 +731,7 @@ static void setup_hdmi_audio(
- 			AFMT_60958_2,
- 			AFMT_60958_CS_CHANNEL_NUMBER_7);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- }
- 
-@@ -751,7 +752,7 @@ static void setup_dp_audio(
- 			DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT,
- 			DP_SEC_AUD_N,
- 			DP_SEC_AUD_N);
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* Async/auto-calc timestamp mode */
-@@ -766,7 +767,7 @@ static void setup_dp_audio(
- 			DP_SEC_TIMESTAMP,
- 			DP_SEC_TIMESTAMP_MODE);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* --- The following are the registers
-@@ -780,13 +781,13 @@ static void setup_dp_audio(
- 
- 		value = 0;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value,
- 			1,
- 			AFMT_AUDIO_PACKET_CONTROL,
- 			AFMT_60958_CS_UPDATE);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AFMT_AUDIO_PACKET_CONTROL2 */
-@@ -796,7 +797,7 @@ static void setup_dp_audio(
- 
- 		value = 0;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value,
- 			0,
- 			AFMT_AUDIO_PACKET_CONTROL2,
-@@ -807,7 +808,7 @@ static void setup_dp_audio(
- 			AFMT_AUDIO_PACKET_CONTROL2,
- 			AFMT_60958_OSF_OVRD);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AFMT_INFOFRAME_CONTROL0 */
-@@ -817,14 +818,14 @@ static void setup_dp_audio(
- 
- 		value = 0;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value,
- 			1,
- 			AFMT_INFOFRAME_CONTROL0,
- 			AFMT_AUDIO_INFO_UPDATE);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-@@ -833,13 +834,13 @@ static void setup_dp_audio(
- 
- 		value = 0;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 		set_reg_field_value(value,
- 			0,
- 			AFMT_60958_0,
- 			AFMT_60958_CS_CLOCK_ACCURACY);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- }
- 
-@@ -878,12 +879,12 @@ static void enable_afmt_clock(
- 	uint32_t enable = enable_flag ? 1:0;
- 
- 	/* Enable Audio packets*/
--	value = dal_read_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs);
-+	value = dm_read_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs);
- 
- 	/*enable AFMT clock*/
- 	set_reg_field_value(value, enable,
- 		AFMT_CNTL, AFMT_AUDIO_CLOCK_EN);
--	dal_write_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs, value);
-+	dm_write_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs, value);
- 
- 	/*wait for AFMT clock to turn on,
- 	 * the expectation is that this
-@@ -891,8 +892,8 @@ static void enable_afmt_clock(
- 	 */
- 	do {
- 		/* Wait for 1us between subsequent register reads.*/
--		dc_service_delay_in_microseconds(hw_ctx->ctx, 1);
--		value = dal_read_reg(hw_ctx->ctx,
-+		dm_delay_in_microseconds(hw_ctx->ctx, 1);
-+		value = dm_read_reg(hw_ctx->ctx,
- 				mmAFMT_CNTL + engine_offs);
- 	} while (get_reg_field_value(value,
- 				AFMT_CNTL, AFMT_AUDIO_CLOCK_ON) !=
-@@ -954,12 +955,12 @@ static void enable_dp_audio(
- 	uint32_t value;
- 
- 	/* Enable Audio packets */
--	value = dal_read_reg(hw_ctx->ctx, addr);
-+	value = dm_read_reg(hw_ctx->ctx, addr);
- 	set_reg_field_value(value, 1,
- 		DP_SEC_CNTL,
- 		DP_SEC_ASP_ENABLE);
- 
--	dal_write_reg(hw_ctx->ctx, addr, value);
-+	dm_write_reg(hw_ctx->ctx, addr, value);
- 
- 	/* Program the ATP and AIP next */
- 	set_reg_field_value(value, 1,
-@@ -970,14 +971,14 @@ static void enable_dp_audio(
- 		DP_SEC_CNTL,
- 		DP_SEC_AIP_ENABLE);
- 
--	dal_write_reg(hw_ctx->ctx, addr, value);
-+	dm_write_reg(hw_ctx->ctx, addr, value);
- 
- 	/* Program STREAM_ENABLE after all the other enables. */
- 	set_reg_field_value(value, 1,
- 		DP_SEC_CNTL,
- 		DP_SEC_STREAM_ENABLE);
- 
--	dal_write_reg(hw_ctx->ctx, addr, value);
-+	dm_write_reg(hw_ctx->ctx, addr, value);
- }
- 
- /* disable DP audio */
-@@ -990,7 +991,7 @@ static void disable_dp_audio(
- 	uint32_t value;
- 
- 	/* Disable Audio packets */
--	value = dal_read_reg(hw_ctx->ctx, addr);
-+	value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 	set_reg_field_value(value, 0,
- 		DP_SEC_CNTL,
-@@ -1019,7 +1020,7 @@ static void disable_dp_audio(
- 			DP_SEC_CNTL,
- 			DP_SEC_STREAM_ENABLE);
- 
--	dal_write_reg(hw_ctx->ctx, addr, value);
-+	dm_write_reg(hw_ctx->ctx, addr, value);
- }
- 
- static void configure_azalia(
-@@ -1232,7 +1233,7 @@ static void configure_azalia(
- 	} /* for */
- 
- 	if (is_ac3_supported)
--		dal_write_reg(hw_ctx->ctx,
-+		dm_write_reg(hw_ctx->ctx,
- 		mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
- 		0x05);
- 
-@@ -1454,21 +1455,21 @@ static void setup_azalia(
- 			AFMT_AUDIO_SRC_CONTROL,
- 			AFMT_AUDIO_SRC_SELECT);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/* Channel allocation */
- 	{
- 		const uint32_t addr =
- 			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
--		uint32_t value = dal_read_reg(hw_ctx->ctx, addr);
-+		uint32_t value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value,
- 			channels,
- 			AFMT_AUDIO_PACKET_CONTROL2,
- 			AFMT_AUDIO_CHANNEL_ENABLE);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	configure_azalia(hw_ctx, signal, crtc_info, audio_info);
-@@ -1484,12 +1485,12 @@ static void unmute_azalia_audio(
- 
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(hw_ctx->ctx, addr);
-+	value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 	set_reg_field_value(value, 1,
- 		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
- 
--	dal_write_reg(hw_ctx->ctx, addr, value);
-+	dm_write_reg(hw_ctx->ctx, addr, value);
- }
- 
- /* mute audio */
-@@ -1502,12 +1503,12 @@ static void mute_azalia_audio(
- 
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(hw_ctx->ctx, addr);
-+	value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 	set_reg_field_value(value, 0,
- 		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
- 
--	dal_write_reg(hw_ctx->ctx, addr, value);
-+	dm_write_reg(hw_ctx->ctx, addr, value);
- }
- 
- /* enable channel splitting mapping */
-@@ -1646,13 +1647,13 @@ static void hw_initialize(
- 	{
- 		uint32_t value;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value, 0x70,
- 		AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
- 		AUDIO_RATE_CAPABILITIES);
- 
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- 
- 	/*Keep alive bit to verify HW block in BU. */
-@@ -1660,7 +1661,7 @@ static void hw_initialize(
- 	{
- 		uint32_t value;
- 
--		value = dal_read_reg(hw_ctx->ctx, addr);
-+		value = dm_read_reg(hw_ctx->ctx, addr);
- 
- 		set_reg_field_value(value, 1,
- 		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-@@ -1669,7 +1670,7 @@ static void hw_initialize(
- 		set_reg_field_value(value, 1,
- 		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
- 		EPSS);
--		dal_write_reg(hw_ctx->ctx, addr, value);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
- 	}
- }
- 
-@@ -1904,7 +1905,7 @@ struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
- {
- 	/* allocate memory for struc hw_ctx_audio_dce110 */
- 	struct hw_ctx_audio_dce110 *hw_ctx_dce110 =
--			dc_service_alloc(ctx, sizeof(struct hw_ctx_audio_dce110));
-+			dm_alloc(ctx, sizeof(struct hw_ctx_audio_dce110));
- 
- 	if (!hw_ctx_dce110) {
- 		ASSERT_CRITICAL(hw_ctx_dce110);
-@@ -1923,7 +1924,7 @@ struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
- 		"Failed to create hw_ctx_audio for DCE11\n");
- 
- 
--	dc_service_free(ctx, hw_ctx_dce110);
-+	dm_free(ctx, hw_ctx_dce110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-index a78ab79..58207f5 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "hw_ctx_audio.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-index 0eb7813..2f1f3d4 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-@@ -23,7 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
-+
-+#include "dm_services.h"
- 
- #define DIVIDER 10000
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-index 68626ba..9f93b3b 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/fixed31_32.h"
- 
- static inline uint64_t abs_i64(
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-index c52fe47..74e6d75 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/fixed32_32.h"
- 
- static uint64_t u64_div(uint64_t n, uint64_t d)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-index 714a571..9c80847 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c
-@@ -23,8 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
--
-+#include "dm_services.h"
- #include "include/grph_object_id.h"
- 
- bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
-@@ -55,13 +54,13 @@ bool dal_graphics_object_id_is_equal(
- 	struct graphics_object_id id2)
- {
- 	if (false == dal_graphics_object_id_is_valid(id1)) {
--		dal_output_to_console(
-+		dm_output_to_console(
- 		"%s: Warning: comparing invalid object 'id1'!\n", __func__);
- 		return false;
- 	}
- 
- 	if (false == dal_graphics_object_id_is_valid(id2)) {
--		dal_output_to_console(
-+		dm_output_to_console(
- 		"%s: Warning: comparing invalid object 'id2'!\n", __func__);
- 		return false;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index 49cef8a..e7938ec 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -23,7 +23,7 @@
-  *
-  */
- #include <stdarg.h>
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/dal_types.h"
- #include "include/logger_interface.h"
- #include "logger.h"
-@@ -283,7 +283,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
- 	/* malloc buffer and init offsets */
- 
- 	logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
--	logger->log_buffer = (char *)dc_service_alloc(ctx,
-+	logger->log_buffer = (char *)dm_alloc(ctx,
- 		logger->log_buffer_size *
- 		sizeof(char));
- 
-@@ -307,7 +307,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
- 
- 	/* malloc and init minor mask array */
- 	logger->log_enable_mask_minors =
--			(uint32_t *)dc_service_alloc(
-+			(uint32_t *)dm_alloc(
- 				ctx,
- 				NUM_ELEMENTS(log_major_mask_info_tbl)
- 				* sizeof(uint32_t));
-@@ -329,12 +329,12 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
- static void destruct(struct dal_logger *logger)
- {
- 	if (logger->log_buffer) {
--		dc_service_free(logger->ctx, logger->log_buffer);
-+		dm_free(logger->ctx, logger->log_buffer);
- 		logger->log_buffer = NULL;
- 	}
- 
- 	if (logger->log_enable_mask_minors) {
--		dc_service_free(logger->ctx, logger->log_enable_mask_minors);
-+		dm_free(logger->ctx, logger->log_enable_mask_minors);
- 		logger->log_enable_mask_minors = NULL;
- 	}
- }
-@@ -342,12 +342,12 @@ static void destruct(struct dal_logger *logger)
- struct dal_logger *dal_logger_create(struct dc_context *ctx)
- {
- 	/* malloc struct */
--	struct dal_logger *logger = dc_service_alloc(ctx, sizeof(struct dal_logger));
-+	struct dal_logger *logger = dm_alloc(ctx, sizeof(struct dal_logger));
- 
- 	if (!logger)
- 		return NULL;
- 	if (!construct(ctx, logger)) {
--		dc_service_free(ctx, logger);
-+		dm_free(ctx, logger);
- 		return NULL;
- 	}
- 
-@@ -359,7 +359,7 @@ uint32_t dal_logger_destroy(struct dal_logger **logger)
- 	if (logger == NULL || *logger == NULL)
- 		return 1;
- 	destruct(*logger);
--	dc_service_free((*logger)->ctx, *logger);
-+	dm_free((*logger)->ctx, *logger);
- 	*logger = NULL;
- 
- 	return 0;
-@@ -403,10 +403,10 @@ static void log_to_debug_console(struct log_entry *entry)
- 	if (entry->buf_offset) {
- 		switch (entry->major) {
- 		case LOG_MAJOR_ERROR:
--			dal_error("%s", entry->buf);
-+			dm_error("%s", entry->buf);
- 			break;
- 		default:
--			dal_output_to_console("%s", entry->buf);
-+			dm_output_to_console("%s", entry->buf);
- 			break;
- 		}
- 	}
-@@ -418,17 +418,17 @@ static void flush_to_debug_console(struct dal_logger *logger)
- 	int i = logger->buffer_read_offset;
- 	char *string_start = &logger->log_buffer[i];
- 
--	dal_output_to_console(
-+	dm_output_to_console(
- 		"---------------- FLUSHING LOG BUFFER ----------------\n");
- 	while (i < logger->buffer_write_offset)	{
- 
- 		if (logger->log_buffer[i] == '\0') {
--			dal_output_to_console("%s", string_start);
-+			dm_output_to_console("%s", string_start);
- 			string_start = (char *)logger->log_buffer + i + 1;
- 		}
- 		i++;
- 	}
--	dal_output_to_console(
-+	dm_output_to_console(
- 		"-------------- END FLUSHING LOG BUFFER --------------\n\n");
- }
- 
-@@ -481,7 +481,7 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			/* No wrap around, copy 'size' bytes
- 			 * from 'entry->buf' to 'log_buffer'
- 			 */
--			dc_service_memmove(logger->log_buffer +
-+			dm_memmove(logger->log_buffer +
- 					logger->buffer_write_offset,
- 					entry->buf, size);
- 			logger->buffer_write_offset += size;
-@@ -493,10 +493,10 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			int space_after_wrap = total_free_space -
- 					space_before_wrap;
- 
--			dc_service_memmove(logger->log_buffer +
-+			dm_memmove(logger->log_buffer +
- 					logger->buffer_write_offset,
- 					entry->buf, space_before_wrap);
--			dc_service_memmove(logger->log_buffer, entry->buf +
-+			dm_memmove(logger->log_buffer, entry->buf +
- 					space_before_wrap, space_after_wrap);
- 
- 			logger->buffer_write_offset = space_after_wrap;
-@@ -510,7 +510,7 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			flush_to_debug_console(logger);
- 
- 			/* Start writing to beginning of buffer */
--			dc_service_memmove(logger->log_buffer, entry->buf, size);
-+			dm_memmove(logger->log_buffer, entry->buf, size);
- 			logger->buffer_write_offset = size;
- 			logger->buffer_read_offset = 0;
- 		}
-@@ -581,7 +581,7 @@ static void append_entry(
- 	}
- 
- 	/* Todo: check if off by 1 byte due to \0 anywhere */
--	dc_service_memmove(entry->buf + entry->buf_offset, buffer, buf_size);
-+	dm_memmove(entry->buf + entry->buf_offset, buffer, buf_size);
- 	entry->buf_offset += buf_size;
- }
- 
-@@ -609,7 +609,7 @@ void dal_logger_write(
- 		dal_logger_open(logger, &entry, major, minor);
- 
- 
--		size = dal_log_to_buffer(
-+		size = dm_log_to_buffer(
- 			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
- 
- 		if (size > 0 && size <
-@@ -658,7 +658,7 @@ void dal_logger_append(
- 
- 		va_start(args, msg);
- 
--		size = dal_log_to_buffer(
-+		size = dm_log_to_buffer(
- 			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
- 
- 		if (size < DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE - 1) {
-@@ -763,7 +763,7 @@ void dal_logger_open(
- 	entry->minor = 0;
- 	entry->logger = logger;
- 
--	entry->buf = dc_service_alloc(
-+	entry->buf = dm_alloc(
- 		logger->ctx,
- 		DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char));
- 
-@@ -799,7 +799,7 @@ void dal_logger_close(struct log_entry *entry)
- 
- cleanup:
- 	if (entry->buf) {
--		dc_service_free(entry->logger->ctx, entry->buf);
-+		dm_free(entry->logger->ctx, entry->buf);
- 		entry->buf = NULL;
- 		entry->buf_offset = 0;
- 		entry->max_buf_bytes = 0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-index 5dcf3fc..6d32b1b 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/dal_types.h"
- #include "include/logger_interface.h"
- #include "logger.h"
-@@ -74,8 +74,8 @@ static bool is_reg_dump_process(void)
- 		struct dal_reg_dump_stack_location *stack_location
- 					= &reg_dump_stack.stack_locations[i];
- 
--		if (stack_location->current_pid == dal_get_pid()
--			&& stack_location->current_tgid == dal_get_tgid())
-+		if (stack_location->current_pid == dm_get_pid()
-+			&& stack_location->current_tgid == dm_get_tgid())
- 			return true;
- 	}
- 
-@@ -96,7 +96,7 @@ static struct dal_reg_dump_stack_location *dal_reg_dump_stack_push(void)
- 
- 	if (reg_dump_stack.stack_pointer >= DAL_REG_DUMP_STACK_MAX_SIZE) {
- 		/* stack is full */
--		dal_output_to_console("[REG_DUMP]: %s: stack is full!\n",
-+		dm_output_to_console("[REG_DUMP]: %s: stack is full!\n",
- 				__func__);
- 	} else {
- 		current_location =
-@@ -113,7 +113,7 @@ static struct dal_reg_dump_stack_location *dal_reg_dump_stack_pop(void)
- 
- 	if (dal_reg_dump_stack_is_empty()) {
- 		/* stack is empty */
--		dal_output_to_console("[REG_DUMP]: %s: stack is empty!\n",
-+		dm_output_to_console("[REG_DUMP]: %s: stack is empty!\n",
- 				__func__);
- 	} else {
- 		--reg_dump_stack.stack_pointer;
-@@ -137,13 +137,13 @@ void dal_reg_logger_push(const char *caller_func)
- 	if (NULL == free_stack_location)
- 		return;
- 
--	dc_service_memset(free_stack_location, 0, sizeof(*free_stack_location));
-+	dm_memset(free_stack_location, 0, sizeof(*free_stack_location));
- 
- 	free_stack_location->current_caller_func = caller_func;
--	free_stack_location->current_pid = dal_get_pid();
--	free_stack_location->current_tgid = dal_get_tgid();
-+	free_stack_location->current_pid = dm_get_pid();
-+	free_stack_location->current_tgid = dm_get_tgid();
- 
--	dal_output_to_console("[REG_DUMP]:%s - start (pid:%ld, tgid:%ld)\n",
-+	dm_output_to_console("[REG_DUMP]:%s - start (pid:%ld, tgid:%ld)\n",
- 		caller_func,
- 		free_stack_location->current_pid,
- 		free_stack_location->current_tgid);
-@@ -156,21 +156,21 @@ void dal_reg_logger_pop(void)
- 	top_stack_location = dal_reg_dump_stack_pop();
- 
- 	if (NULL == top_stack_location) {
--		dal_output_to_console("[REG_DUMP]:%s - Stack is Empty!\n",
-+		dm_output_to_console("[REG_DUMP]:%s - Stack is Empty!\n",
- 				__func__);
- 		return;
- 	}
- 
--	dal_output_to_console(
-+	dm_output_to_console(
- 	"[REG_DUMP]:%s - end."\
- 	" Reg R/W Count: Total=%d Function=%d. (pid:%ld, tgid:%ld)\n",
- 			top_stack_location->current_caller_func,
- 			reg_dump_stack.total_rw_count,
- 			top_stack_location->rw_count,
--			dal_get_pid(),
--			dal_get_tgid());
-+			dm_get_pid(),
-+			dm_get_tgid());
- 
--	dc_service_memset(top_stack_location, 0, sizeof(*top_stack_location));
-+	dm_memset(top_stack_location, 0, sizeof(*top_stack_location));
- }
- 
- void dal_reg_logger_rw_count_increment(void)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c b/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-index f589091..44447e0 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/signal_types.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/signal_types.h"
- 
- bool dc_is_hdmi_signal(enum signal_type signal)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/vector.c b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-index ea682a7..32ca6b1 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/vector.h"
- 
- bool dal_vector_construct(
-@@ -40,7 +40,7 @@ bool dal_vector_construct(
- 		return false;
- 	}
- 
--	vector->container = dc_service_alloc(ctx, struct_size * capacity);
-+	vector->container = dm_alloc(ctx, struct_size * capacity);
- 	if (vector->container == NULL)
- 		return false;
- 	vector->capacity = capacity;
-@@ -67,7 +67,7 @@ bool dal_vector_presized_costruct(
- 		return false;
- 	}
- 
--	vector->container = dc_service_alloc(ctx, struct_size * count);
-+	vector->container = dm_alloc(ctx, struct_size * count);
- 
- 	if (vector->container == NULL)
- 		return false;
-@@ -77,7 +77,7 @@ bool dal_vector_presized_costruct(
- 	 * initialises the memory to. */
- 	if (NULL != initial_value) {
- 		for (i = 0; i < count; ++i)
--			dc_service_memmove(
-+			dm_memmove(
- 				vector->container + i * struct_size,
- 				initial_value,
- 				struct_size);
-@@ -95,7 +95,7 @@ struct vector *dal_vector_presized_create(
- 	void *initial_value,
- 	uint32_t struct_size)
- {
--	struct vector *vector = dc_service_alloc(ctx, sizeof(struct vector));
-+	struct vector *vector = dm_alloc(ctx, sizeof(struct vector));
- 
- 	if (vector == NULL)
- 		return NULL;
-@@ -105,7 +105,7 @@ struct vector *dal_vector_presized_create(
- 		return vector;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, vector);
-+	dm_free(ctx, vector);
- 	return NULL;
- }
- 
-@@ -114,7 +114,7 @@ struct vector *dal_vector_create(
- 	uint32_t capacity,
- 	uint32_t struct_size)
- {
--	struct vector *vector = dc_service_alloc(ctx, sizeof(struct vector));
-+	struct vector *vector = dm_alloc(ctx, sizeof(struct vector));
- 
- 	if (vector == NULL)
- 		return NULL;
-@@ -124,7 +124,7 @@ struct vector *dal_vector_create(
- 
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, vector);
-+	dm_free(ctx, vector);
- 	return NULL;
- }
- 
-@@ -132,7 +132,7 @@ void dal_vector_destruct(
- 	struct vector *vector)
- {
- 	if (vector->container != NULL)
--		dc_service_free(vector->ctx, vector->container);
-+		dm_free(vector->ctx, vector->container);
- 	vector->count = 0;
- 	vector->capacity = 0;
- }
-@@ -143,7 +143,7 @@ void dal_vector_destroy(
- 	if (vector == NULL || *vector == NULL)
- 		return;
- 	dal_vector_destruct(*vector);
--	dc_service_free((*vector)->ctx, *vector);
-+	dm_free((*vector)->ctx, *vector);
- 	*vector = NULL;
- }
- 
-@@ -170,7 +170,7 @@ bool dal_vector_remove_at_index(
- 		return false;
- 
- 	if (index != vector->count - 1)
--		dc_service_memmove(
-+		dm_memmove(
- 			vector->container + (index * vector->struct_size),
- 			vector->container + ((index + 1) * vector->struct_size),
- 			(vector->count - index - 1) * vector->struct_size);
-@@ -190,7 +190,7 @@ void dal_vector_set_at_index(
- 		BREAK_TO_DEBUGGER();
- 		return;
- 	}
--	dc_service_memmove(
-+	dm_memmove(
- 		where,
- 		what,
- 		vector->struct_size);
-@@ -219,12 +219,12 @@ bool dal_vector_insert_at(
- 	insert_address = vector->container + (vector->struct_size * position);
- 
- 	if (vector->count && position < vector->count)
--		dc_service_memmove(
-+		dm_memmove(
- 			insert_address + vector->struct_size,
- 			insert_address,
- 			vector->struct_size * (vector->count - position));
- 
--	dc_service_memmove(
-+	dm_memmove(
- 		insert_address,
- 		what,
- 		vector->struct_size);
-@@ -273,7 +273,7 @@ struct vector *dal_vector_clone(
- 	}
- 
- 	/* copy vector's data */
--	dc_service_memmove(vec_cloned->container, vector->container,
-+	dm_memmove(vec_cloned->container, vector->container,
- 			vec_cloned->struct_size * vec_cloned->capacity);
- 
- 	return vec_cloned;
-@@ -291,7 +291,7 @@ bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
- 	if (capacity <= vector->capacity)
- 		return true;
- 
--	new_container = dc_service_realloc(vector->ctx, vector->container,
-+	new_container = dm_realloc(vector->ctx, vector->container,
- 		capacity * vector->struct_size);
- 
- 	if (new_container) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 2ef2543..4ce5f9f 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "atom.h"
- 
-@@ -120,14 +120,14 @@ struct dc_bios *dal_bios_parser_create(
- {
- 	struct bios_parser *bp = NULL;
- 
--	bp = dc_service_alloc(init->ctx, sizeof(struct bios_parser));
-+	bp = dm_alloc(init->ctx, sizeof(struct bios_parser));
- 	if (!bp)
- 		return NULL;
- 
- 	if (bios_parser_construct(bp, init, as))
- 		return &bp->base;
- 
--	dc_service_free(init->ctx, bp);
-+	dm_free(init->ctx, bp);
- 	BREAK_TO_DEBUGGER();
- 	return NULL;
- }
-@@ -135,7 +135,7 @@ struct dc_bios *dal_bios_parser_create(
- static void destruct(struct bios_parser *bp)
- {
- 	if (bp->bios_local_image)
--		dc_service_free(bp->ctx, bp->bios_local_image);
-+		dm_free(bp->ctx, bp->bios_local_image);
- }
- 
- void dal_bios_parser_destroy(struct dc_bios **dcb)
-@@ -149,7 +149,7 @@ void dal_bios_parser_destroy(struct dc_bios **dcb)
- 
- 	destruct(bp);
- 
--	dc_service_free((bp)->ctx, bp);
-+	dm_free((bp)->ctx, bp);
- 	*dcb = NULL;
- }
- 
-@@ -378,7 +378,7 @@ static enum bp_result bios_parser_get_oem_ddc_info(struct dc_bios *dcb,
- 			ATOM_I2C_RECORD record;
- 			ATOM_I2C_ID_CONFIG_ACCESS *config;
- 
--			dc_service_memset(&record, 0, sizeof(record));
-+			dm_memset(&record, 0, sizeof(record));
- 
- 			config = &tbl->sucI2cId + index - 1;
- 
-@@ -875,7 +875,7 @@ static enum bp_result get_firmware_info_v1_4(
- 	if (!firmware_info)
- 		return BP_RESULT_BADBIOSTABLE;
- 
--	dc_service_memset(info, 0, sizeof(*info));
-+	dm_memset(info, 0, sizeof(*info));
- 
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
-@@ -926,7 +926,7 @@ static enum bp_result get_firmware_info_v2_1(
- 	if (!firmwareInfo)
- 		return BP_RESULT_BADBIOSTABLE;
- 
--	dc_service_memset(info, 0, sizeof(*info));
-+	dm_memset(info, 0, sizeof(*info));
- 
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
-@@ -1012,7 +1012,7 @@ static enum bp_result get_firmware_info_v2_2(
- 	if (!firmware_info)
- 		return BP_RESULT_BADBIOSTABLE;
- 
--	dc_service_memset(info, 0, sizeof(*info));
-+	dm_memset(info, 0, sizeof(*info));
- 
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
-@@ -1117,7 +1117,7 @@ static enum bp_result get_ss_info_v3_1(
- 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
- 				&ss_table_header_include->asSpreadSpectrum[0];
- 
--	dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+	dm_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
- 
- 	for (i = 0; i < table_size; i++) {
- 		if (tbl[i].ucClockIndication != (uint8_t) id)
-@@ -1664,7 +1664,7 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
- 	header = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
- 		DATA_TABLES(ASIC_InternalSS_Info));
- 
--	dc_service_memset(info, 0, sizeof(struct spread_spectrum_info));
-+	dm_memset(info, 0, sizeof(struct spread_spectrum_info));
- 
- 	tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
- 			- sizeof(ATOM_COMMON_TABLE_HEADER))
-@@ -1768,7 +1768,7 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 		if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
- 			continue;
- 
--		dc_service_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+		dm_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
- 
- 		if (ATOM_EXTERNAL_SS_MASK &
- 				tbl->asSS_Info[i].ucSpreadSpectrumType)
-@@ -1860,7 +1860,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
- 		|| 2 > lvds->sHeader.ucTableContentRevision)
- 		return BP_RESULT_UNSUPPORTED;
- 
--	dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
-+	dm_memset(info, 0, sizeof(struct embedded_panel_info));
- 
- 	/* We need to convert from 10KHz units into KHz units*/
- 	info->lcd_timing.pixel_clk =
-@@ -1978,7 +1978,7 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 			&& (3 <= lvds->sHeader.ucTableContentRevision)))
- 		return BP_RESULT_UNSUPPORTED;
- 
--	dc_service_memset(info, 0, sizeof(struct embedded_panel_info));
-+	dm_memset(info, 0, sizeof(struct embedded_panel_info));
- 
- 	/* We need to convert from 10KHz units into KHz units */
- 	info->lcd_timing.pixel_clk =
-@@ -2551,7 +2551,7 @@ static enum bp_result bios_parser_get_faked_edid_buf(
- 	if (len < edid_size)
- 		return BP_RESULT_BADINPUT; /* buffer not big enough to fill */
- 
--	dc_service_memmove(buff, &edid_record->ucFakeEDIDString, edid_size);
-+	dm_memmove(buff, &edid_record->ucFakeEDIDString, edid_size);
- 
- 	return BP_RESULT_OK;
- }
-@@ -3540,7 +3540,7 @@ static uint32_t enum_first_device_id(uint32_t dev_id)
- 
- 	/* No group found for this device ID. */
- 
--	dal_error("%s: incorrect input %d\n", __func__, dev_id);
-+	dm_error("%s: incorrect input %d\n", __func__, dev_id);
- 	/* No matching support flag for given device ID */
- 	return 0;
- }
-@@ -3830,7 +3830,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 	if (!opm_object)
- 		return BP_RESULT_UNSUPPORTED;
- 
--	dc_service_memset(&ext_display_connection_info_tbl, 0,
-+	dm_memset(&ext_display_connection_info_tbl, 0,
- 			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
- 
- 	connector_tbl_offset = bp->object_info_tbl_offset
-@@ -4088,14 +4088,14 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 		uint8_t *original_bios;
- 		/* Step 1: Replace bios image with the new copy which will be
- 		 * patched */
--		bp->bios_local_image = dc_service_alloc(bp->ctx, bp->bios_size);
-+		bp->bios_local_image = dm_alloc(bp->ctx, bp->bios_size);
- 		if (bp->bios_local_image == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			/* Failed to alloc bp->bios_local_image */
- 			return;
- 		}
- 
--		dc_service_memmove(bp->bios_local_image, bp->bios, bp->bios_size);
-+		dm_memmove(bp->bios_local_image, bp->bios, bp->bios_size);
- 		original_bios = bp->bios;
- 		bp->bios = bp->bios_local_image;
- 		connector_tbl =
-@@ -4109,7 +4109,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 			/* Patching the bios image has failed. We will copy
- 			 * again original image provided and afterwards
- 			 * only remove null entries */
--			dc_service_memmove(
-+			dm_memmove(
- 					bp->bios_local_image,
- 					original_bios,
- 					bp->bios_size);
-@@ -4126,7 +4126,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 				continue;
- 
- 			if (i != connectors_num) {
--				dc_service_memmove(
-+				dm_memmove(
- 						&connector_tbl->
- 						asObjects[connectors_num],
- 						object,
-@@ -4673,7 +4673,7 @@ static struct integrated_info *bios_parser_create_integrated_info(
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct integrated_info *info = NULL;
- 
--	info = dc_service_alloc(bp->ctx, sizeof(struct integrated_info));
-+	info = dm_alloc(bp->ctx, sizeof(struct integrated_info));
- 
- 	if (info == NULL) {
- 		ASSERT_CRITICAL(0);
-@@ -4683,7 +4683,7 @@ static struct integrated_info *bios_parser_create_integrated_info(
- 	if (construct_integrated_info(bp, info) == BP_RESULT_OK)
- 		return info;
- 
--	dc_service_free(bp->ctx, info);
-+	dm_free(bp->ctx, info);
- 
- 	return NULL;
- }
-@@ -4700,7 +4700,7 @@ static void bios_parser_destroy_integrated_info(
- 	}
- 
- 	if (*info != NULL) {
--		dc_service_free(bp->ctx, *info);
-+		dm_free(bp->ctx, *info);
- 		*info = NULL;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index fe05df2..0aa227a 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index 1a27bc8..3bc52f5 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "atom.h"
- 
-@@ -44,7 +44,7 @@
- 		GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
- 
- #define BIOS_CMD_TABLE_PARA_REVISION(command)\
--	dal_bios_cmd_table_para_revision(bp->ctx, \
-+	dm_bios_cmd_table_para_revision(bp->ctx, \
- 		GetIndexIntoMasterTable(COMMAND, command))
- 
- 
-@@ -367,7 +367,7 @@ static enum bp_result transmitter_control_v2(
- 	enum connector_id connector_id =
- 		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	switch (cntl->transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -491,7 +491,7 @@ static enum bp_result transmitter_control_v3(
- 	bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
- 					|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	switch (cntl->transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -640,7 +640,7 @@ static enum bp_result transmitter_control_v4(
- 			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	switch (cntl->transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -778,7 +778,7 @@ static enum bp_result transmitter_control_v1_5(
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 params;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
- 	params.ucAction = (uint8_t)cntl->action;
- 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-@@ -844,7 +844,7 @@ static enum bp_result transmitter_control_v1_6(
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 params;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
- 	params.ucAction = (uint8_t)cntl->action;
- 
-@@ -948,7 +948,7 @@ static enum bp_result set_pixel_clock_v3(
- 	PIXEL_CLOCK_PARAMETERS_V3 *params;
- 	SET_PIXEL_CLOCK_PS_ALLOCATION allocation;
- 
--	dc_service_memset(&allocation, 0, sizeof(allocation));
-+	dm_memset(&allocation, 0, sizeof(allocation));
- 
- 	if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
- 		allocation.sPCLKInput.ucPpll = ATOM_PPLL1;
-@@ -1021,7 +1021,7 @@ static enum bp_result set_pixel_clock_v5(
- 	uint8_t controller_id;
- 	uint32_t pll_id;
- 
--	dc_service_memset(&clk, 0, sizeof(clk));
-+	dm_memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
- 			&& bp->cmd_helper->controller_id_to_atom(
-@@ -1078,7 +1078,7 @@ static enum bp_result set_pixel_clock_v6(
- 	uint8_t controller_id;
- 	uint32_t pll_id;
- 
--	dc_service_memset(&clk, 0, sizeof(clk));
-+	dm_memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
- 			&& bp->cmd_helper->controller_id_to_atom(
-@@ -1157,7 +1157,7 @@ static enum bp_result set_pixel_clock_v7(
- 	uint8_t controller_id;
- 	uint32_t pll_id;
- 
--	dc_service_memset(&clk, 0, sizeof(clk));
-+	dm_memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
- 			&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
-@@ -1267,7 +1267,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v1(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	ENABLE_SPREAD_SPECTRUM_ON_PPLL params;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	if ((enable == true) && (bp_params->percentage > 0))
- 		params.ucEnable = ATOM_ENABLE;
-@@ -1311,7 +1311,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v2(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 params;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
- 		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P1PLL;
-@@ -1363,7 +1363,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v3(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 params;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	switch (bp_params->pll_id) {
- 	case CLOCK_SOURCE_ID_PLL0:
-@@ -1484,7 +1484,7 @@ static enum bp_result adjust_display_pll_v3(
- 	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 params;
- 	uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	/* We need to convert from KHz units into 10KHz units and then convert
- 	 * output pixel clock back 10KHz-->KHz */
-@@ -1731,7 +1731,7 @@ static enum signal_type dac_load_detection_v3(
- 	DAC_LOAD_DETECTION_PS_ALLOCATION params;
- 	enum signal_type signal = SIGNAL_TYPE_NONE;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	/* load detection is cupported for CRT, TV and CV */
- 	switch (display_signal) {
-@@ -2135,7 +2135,7 @@ static enum bp_result select_crtc_source_v2(
- 	uint32_t atom_engine_id;
- 	enum signal_type s = bp_params->signal;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	/* set controller id */
- 	if (bp->cmd_helper->controller_id_to_atom(
-@@ -2176,7 +2176,7 @@ static enum bp_result select_crtc_source_v3(
- 	uint32_t atom_engine_id;
- 	enum signal_type s = bp_params->signal;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
- 			&atom_controller_id))
-@@ -2347,7 +2347,7 @@ static enum bp_result program_clock_v5(
- 	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 params;
- 	uint32_t atom_pll_id;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 	if (!bp->cmd_helper->clock_source_id_to_atom(
- 			bp_params->pll_id, &atom_pll_id)) {
- 		BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
-@@ -2378,7 +2378,7 @@ static enum bp_result program_clock_v6(
- 	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 params;
- 	uint32_t atom_pll_id;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	if (!bp->cmd_helper->clock_source_id_to_atom(
- 			bp_params->pll_id, &atom_pll_id)) {
-@@ -2437,7 +2437,7 @@ static enum bp_result compute_memore_engine_pll_v4(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
- 
-@@ -2493,7 +2493,7 @@ static enum bp_result external_encoder_control_v3(
- 	struct graphics_object_id encoder;
- 	bool is_input_signal_dp = false;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	cntl_params = &params.sExtEncoder;
- 
-@@ -2692,7 +2692,7 @@ static enum bp_result set_dce_clock_v2_1(
- 	uint32_t atom_clock_type;
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 
--	dc_service_memset(&params, 0, sizeof(params));
-+	dm_memset(&params, 0, sizeof(params));
- 
- 	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
- 			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index d379496..566604e 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "atom.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index f6c7df5..85d3103 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "atom.h"
- 
-@@ -52,11 +52,11 @@ static void set_scratch_acc_mode_change(
- 	uint32_t addr = mmBIOS_SCRATCH_6;
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	value |= ATOM_S6_ACC_MODE;
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- /*
-@@ -79,32 +79,32 @@ static void set_scratch_active_and_requested(
- 	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
- 	addr = mmBIOS_SCRATCH_3;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
- 	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
- 	addr = mmBIOS_SCRATCH_6;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	value &= ~ATOM_S6_ACC_REQ_MASK;
- 	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
- 	addr = mmBIOS_SCRATCH_5;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
- 	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	d->active = 0;
- 	d->requested = 0;
-@@ -119,7 +119,7 @@ static enum lcd_scale get_scratch_lcd_scale(
- 	uint32_t addr = mmBIOS_SCRATCH_6;
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	if (value & ATOM_S6_REQ_LCD_EXPANSION_FULL)
- 		return LCD_SCALE_FULLPANEL;
-@@ -235,7 +235,7 @@ static bool is_accelerated_mode(
- 	struct dc_context *ctx)
- {
- 	uint32_t addr = mmBIOS_SCRATCH_6;
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	return (value & ATOM_S6_ACC_MODE) ? true : false;
- }
-@@ -275,7 +275,7 @@ static enum signal_type detect_sink(
- 		return SIGNAL_TYPE_NONE;
- 	}
- 
--	bios_scratch0 = dal_read_reg(ctx,
-+	bios_scratch0 = dm_read_reg(ctx,
- 		mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF);
- 
- 	/* In further processing we use DACB masks. If we want detect load on
-@@ -390,14 +390,14 @@ static void set_scratch_connected(
- 	/* update scratch register */
- 	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	if (connected)
- 		value |= update;
- 	else
- 		value &= ~update;
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void set_scratch_critical_state(
-@@ -405,14 +405,14 @@ static void set_scratch_critical_state(
- 	bool state)
- {
- 	uint32_t addr = mmBIOS_SCRATCH_6;
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	if (state)
- 		value |= ATOM_S6_CRITICAL_STATE;
- 	else
- 		value &= ~ATOM_S6_CRITICAL_STATE;
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void set_scratch_lcd_scale(
-@@ -430,7 +430,7 @@ static bool is_lid_open(struct dc_context *ctx)
- 	uint32_t bios_scratch6;
- 
- 	bios_scratch6 =
--		dal_read_reg(
-+		dm_read_reg(
- 			ctx,
- 			mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-index 182029b..614ba94 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-@@ -23,7 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
-+
- #include "atom.h"
- 
- #include "include/bios_parser_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 3cbf6f8..8faabbc 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -23,8 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
--
-+#include "dm_services.h"
- #include "bandwidth_calcs.h"
- 
- /*******************************************************************************
-@@ -3704,10 +3703,10 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 	const struct bw_calcs_mode_data *mode_data,
- 	struct bw_calcs_output *calcs_output)
- {
--	struct bw_calcs_results *bw_results_internal = dc_service_alloc(
-+	struct bw_calcs_results *bw_results_internal = dm_alloc(
- 				ctx, sizeof(struct bw_calcs_results));
- 	struct bw_calcs_mode_data_internal *bw_data_internal =
--		dc_service_alloc(
-+		dm_alloc(
- 			ctx, sizeof(struct bw_calcs_mode_data_internal));
- 	switch (mode_data->number_of_displays) {
- 	case (3):
-@@ -3935,8 +3934,8 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->required_sclk = 0;
- 	}
- 
--	dc_service_free(ctx, bw_data_internal);
--	dc_service_free(ctx, bw_results_internal);
-+	dm_free(ctx, bw_data_internal);
-+	dm_free(ctx, bw_results_internal);
- 
- 	return is_display_configuration_supported(vbios, calcs_output);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index b076bec..8a7a4c9 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "bw_fixed.h"
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-index 3dd8781..64ca203 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/fixed31_32.h"
- 
- #include "scaler_filter.h"
-@@ -1099,7 +1099,7 @@ static bool allocate_3d_storage(
- 	int32_t indexof_table = 0;
- 	int32_t indexof_row = 0;
- 
--	struct fixed31_32 ***tables = dc_service_alloc(
-+	struct fixed31_32 ***tables = dm_alloc(
- 		ctx,
- 		numberof_tables * sizeof(struct fixed31_32 **));
- 
-@@ -1109,7 +1109,7 @@ static bool allocate_3d_storage(
- 	}
- 
- 	while (indexof_table != numberof_tables) {
--		struct fixed31_32 **rows = dc_service_alloc(
-+		struct fixed31_32 **rows = dm_alloc(
- 			ctx,
- 			numberof_rows * sizeof(struct fixed31_32 *));
- 
-@@ -1122,7 +1122,7 @@ static bool allocate_3d_storage(
- 		tables[indexof_table] = rows;
- 
- 		while (indexof_row != numberof_rows) {
--			struct fixed31_32 *columns = dc_service_alloc(
-+			struct fixed31_32 *columns = dm_alloc(
- 				ctx,
- 				numberof_columns * sizeof(struct fixed31_32));
- 
-@@ -1150,19 +1150,19 @@ failure:
- 
- 	while (indexof_table >= 0) {
- 		while (indexof_row >= 0) {
--			dc_service_free(ctx, tables[indexof_table][indexof_row]);
-+			dm_free(ctx, tables[indexof_table][indexof_row]);
- 
- 			--indexof_row;
- 		}
- 
- 		indexof_row = numberof_rows - 1;
- 
--		dc_service_free(ctx, tables[indexof_table]);
-+		dm_free(ctx, tables[indexof_table]);
- 
- 		--indexof_table;
- 	}
- 
--	dc_service_free(ctx, tables);
-+	dm_free(ctx, tables);
- 
- 	return false;
- }
-@@ -1184,18 +1184,18 @@ static void destroy_3d_storage(
- 		uint32_t indexof_row = 0;
- 
- 		while (indexof_row != numberof_rows) {
--			dc_service_free(
-+			dm_free(
- 				ctx, tables[indexof_table][indexof_row]);
- 
- 			++indexof_row;
- 		};
- 
--		dc_service_free(ctx, tables[indexof_table]);
-+		dm_free(ctx, tables[indexof_table]);
- 
- 		++indexof_table;
- 	};
- 
--	dc_service_free(ctx, tables);
-+	dm_free(ctx, tables);
- 
- 	*ptr = NULL;
- }
-@@ -1627,13 +1627,13 @@ static bool generate_filter(
- 
- 	if (filter->coefficients_quantity < coefficients_quantity) {
- 		if (filter->coefficients) {
--			dc_service_free(filter->ctx, filter->coefficients);
-+			dm_free(filter->ctx, filter->coefficients);
- 
- 			filter->coefficients = NULL;
- 			filter->coefficients_quantity = 0;
- 		}
- 
--		filter->coefficients = dc_service_alloc(
-+		filter->coefficients = dm_alloc(
- 			filter->ctx,
- 			coefficients_quantity * sizeof(struct fixed31_32));
- 
-@@ -1655,13 +1655,13 @@ static bool generate_filter(
- 
- 	if (filter->coefficients_sum_quantity < coefficients_sum_quantity) {
- 		if (filter->coefficients_sum) {
--			dc_service_free(filter->ctx, filter->coefficients_sum);
-+			dm_free(filter->ctx, filter->coefficients_sum);
- 
- 			filter->coefficients_sum = NULL;
- 			filter->coefficients_sum_quantity = 0;
- 		}
- 
--		filter->coefficients_sum = dc_service_alloc(
-+		filter->coefficients_sum = dm_alloc(
- 			filter->ctx,
- 			coefficients_sum_quantity * sizeof(struct fixed31_32));
- 
-@@ -1831,16 +1831,16 @@ static void destruct_scaler_filter(
- 	struct scaler_filter *filter)
- {
- 	if (filter->coefficients_sum)
--		dc_service_free(filter->ctx, filter->coefficients_sum);
-+		dm_free(filter->ctx, filter->coefficients_sum);
- 
- 	if (filter->coefficients)
--		dc_service_free(filter->ctx, filter->coefficients);
-+		dm_free(filter->ctx, filter->coefficients);
- 
- 	if (filter->integer_filter)
--		dc_service_free(filter->ctx, filter->integer_filter);
-+		dm_free(filter->ctx, filter->integer_filter);
- 
- 	if (filter->filter)
--		dc_service_free(filter->ctx, filter->filter);
-+		dm_free(filter->ctx, filter->filter);
- 
- 	destroy_upscaling_table(filter);
- 
-@@ -1850,7 +1850,7 @@ static void destruct_scaler_filter(
- struct scaler_filter *dal_scaler_filter_create(struct dc_context *ctx)
- {
- 	struct scaler_filter *filter =
--		dc_service_alloc(ctx, sizeof(struct scaler_filter));
-+		dm_alloc(ctx, sizeof(struct scaler_filter));
- 
- 	if (!filter) {
- 		BREAK_TO_DEBUGGER();
-@@ -1862,7 +1862,7 @@ struct scaler_filter *dal_scaler_filter_create(struct dc_context *ctx)
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dc_service_free(ctx, filter);
-+	dm_free(ctx, filter);
- 
- 	return NULL;
- }
-@@ -1902,13 +1902,13 @@ bool dal_scaler_filter_generate(
- 
- 	if (filter_size_required > filter->filter_size_allocated) {
- 		if (filter->filter) {
--			dc_service_free(filter->ctx, filter->filter);
-+			dm_free(filter->ctx, filter->filter);
- 
- 			filter->filter = 0;
- 			filter->filter_size_allocated = 0;
- 		}
- 
--		filter->filter = dc_service_alloc(
-+		filter->filter = dm_alloc(
- 			filter->ctx,
- 			filter_size_required * sizeof(struct fixed31_32));
- 
-@@ -1918,12 +1918,12 @@ bool dal_scaler_filter_generate(
- 		}
- 
- 		if (filter->integer_filter) {
--			dc_service_free(filter->ctx, filter->integer_filter);
-+			dm_free(filter->ctx, filter->integer_filter);
- 
- 			filter->integer_filter = 0;
- 		}
- 
--		filter->integer_filter = dc_service_alloc(
-+		filter->integer_filter = dm_alloc(
- 			filter->ctx,
- 			filter_size_required * sizeof(uint32_t));
- 
-@@ -1986,7 +1986,7 @@ void dal_scaler_filter_destroy(
- 
- 	destruct_scaler_filter(*filter);
- 
--	dc_service_free((*filter)->ctx, *filter);
-+	dm_free((*filter)->ctx, *filter);
- 
- 	*filter = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 770a66c..e6c7cac 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dc.h"
- 
-@@ -82,7 +82,7 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 	connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
- 	if (connectors_num > ENUM_ID_COUNT) {
--		dal_error(
-+		dm_error(
- 			"DC: Number of connectors %d exceeds maximum of %d!\n",
- 			connectors_num,
- 			ENUM_ID_COUNT);
-@@ -90,11 +90,11 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 	}
- 
- 	if (connectors_num == 0 && init_params->num_virtual_links == 0) {
--		dal_error("DC: Number of connectors can not be zero!\n");
-+		dm_error("DC: Number of connectors can not be zero!\n");
- 		return false;
- 	}
- 
--	dal_output_to_console(
-+	dm_output_to_console(
- 		"DC: %s: connectors_num: physical:%d, virtual:%d\n",
- 		__func__,
- 		connectors_num,
-@@ -116,12 +116,12 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 			link->dc = dc;
- 			++dc->link_count;
- 		} else {
--			dal_error("DC: failed to create link!\n");
-+			dm_error("DC: failed to create link!\n");
- 		}
- 	}
- 
- 	for (i = 0; i < init_params->num_virtual_links; i++) {
--		struct core_link *link = dc_service_alloc(
-+		struct core_link *link = dm_alloc(
- 			dc->ctx,
- 			sizeof(*link));
- 		struct encoder_init_data enc_init = {0};
-@@ -138,7 +138,7 @@ static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
- 		link->link_id.type = OBJECT_TYPE_CONNECTOR;
- 		link->link_id.id = CONNECTOR_ID_VIRTUAL;
- 		link->link_id.enum_id = ENUM_ID_1;
--		link->link_enc = dc_service_alloc(
-+		link->link_enc = dm_alloc(
- 			dc->ctx,
- 			sizeof(*link->link_enc));
- 
-@@ -215,7 +215,7 @@ static void init_hw(struct dc *dc)
- 		struct audio *audio = dc->res_pool.audios[i];
- 
- 		if (dal_audio_power_up(audio) != AUDIO_RESULT_OK)
--			dal_error("Failed audio power up!\n");
-+			dm_error("Failed audio power up!\n");
- 	}
- 
- }
-@@ -227,7 +227,7 @@ static struct adapter_service *create_as(
- 	struct adapter_service *as = NULL;
- 	struct as_init_data init_data;
- 
--	dc_service_memset(&init_data, 0, sizeof(init_data));
-+	dm_memset(&init_data, 0, sizeof(init_data));
- 
- 	init_data.ctx = dc_init_data->ctx;
- 
-@@ -263,7 +263,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 	struct dc_pp_clock_levels clks = {0};
- 
- 	/*do system clock*/
--	dc_service_pp_get_clock_levels_by_type(
-+	dm_pp_get_clock_levels_by_type(
- 			dc->ctx,
- 			DC_PP_CLOCK_TYPE_ENGINE_CLK,
- 			&clks);
-@@ -276,7 +276,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			clks.clocks_in_khz[0], 1000);
- 
- 	/*do display clock*/
--	dc_service_pp_get_clock_levels_by_type(
-+	dm_pp_get_clock_levels_by_type(
- 			dc->ctx,
- 			DC_PP_CLOCK_TYPE_DISPLAY_CLK,
- 			&clks);
-@@ -289,7 +289,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 			clks.clocks_in_khz[0], 1000);
- 
- 	/*do memory clock*/
--	dc_service_pp_get_clock_levels_by_type(
-+	dm_pp_get_clock_levels_by_type(
- 			dc->ctx,
- 			DC_PP_CLOCK_TYPE_MEMORY_CLK,
- 			&clks);
-@@ -319,9 +319,9 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 	ctx.cgs_device = init_params->cgs_device;
- 	ctx.dc = dc;
- 
--	dc_init_data.ctx = dc_service_alloc(&ctx, sizeof(*dc_init_data.ctx));
-+	dc_init_data.ctx = dm_alloc(&ctx, sizeof(*dc_init_data.ctx));
- 	if (!dc_init_data.ctx) {
--		dal_error("%s: failed to create ctx\n", __func__);
-+		dm_error("%s: failed to create ctx\n", __func__);
- 		goto ctx_fail;
- 	}
- 	dc_init_data.ctx->driver_context = init_params->driver;
-@@ -334,7 +334,7 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 
- 	if (!logger) {
- 		/* can *not* call logger. call base driver 'print error' */
--		dal_error("%s: failed to create Logger!\n", __func__);
-+		dm_error("%s: failed to create Logger!\n", __func__);
- 		goto logger_fail;
- 	}
- 	dc_init_data.ctx->logger = logger;
-@@ -343,14 +343,14 @@ static bool construct(struct dc *dc, const struct dal_init_data *init_params)
- 	dc_init_data.adapter_srv = create_as(&dc_init_data, init_params);
- 
- 	if (!dc_init_data.adapter_srv) {
--		dal_error("%s: create_as() failed!\n", __func__);
-+		dm_error("%s: create_as() failed!\n", __func__);
- 		goto as_fail;
- 	}
- 
- 	/* Initialize HW controlled by Adapter Service */
- 	if (false == dal_adapter_service_initialize_hw_data(
- 			dc_init_data.adapter_srv)) {
--		dal_error("%s: dal_adapter_service_initialize_hw_data()"\
-+		dm_error("%s: dal_adapter_service_initialize_hw_data()"\
- 				"  failed!\n", __func__);
- 		/* Note that AS exist, so have to destroy it.*/
- 		goto as_fail;
-@@ -385,7 +385,7 @@ as_fail:
- 	dal_logger_destroy(&dc_init_data.ctx->logger);
- logger_fail:
- hwss_fail:
--	dc_service_free(&ctx, dc_init_data.ctx);
-+	dm_free(&ctx, dc_init_data.ctx);
- ctx_fail:
- 	return false;
- }
-@@ -395,7 +395,7 @@ static void destruct(struct dc *dc)
- 	destroy_links(dc);
- 	dc->res_pool.funcs->destruct(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
--	dc_service_free(dc->ctx, dc->ctx);
-+	dm_free(dc->ctx, dc->ctx);
- }
- 
- /*******************************************************************************
-@@ -408,7 +408,7 @@ struct dc *dc_create(const struct dal_init_data *init_params)
- 		.driver_context = init_params->driver,
- 		.cgs_device = init_params->cgs_device
- 	};
--	struct dc *dc = dc_service_alloc(&ctx, sizeof(*dc));
-+	struct dc *dc = dm_alloc(&ctx, sizeof(*dc));
- 
- 	if (NULL == dc)
- 		goto alloc_fail;
-@@ -423,7 +423,7 @@ struct dc *dc_create(const struct dal_init_data *init_params)
- 	return dc;
- 
- construct_fail:
--	dc_service_free(&ctx, dc);
-+	dm_free(&ctx, dc);
- 
- alloc_fail:
- 	return NULL;
-@@ -433,7 +433,7 @@ void dc_destroy(struct dc **dc)
- {
- 	struct dc_context ctx = *(*dc)->ctx;
- 	destruct(*dc);
--	dc_service_free(&ctx, *dc);
-+	dm_free(&ctx, *dc);
- 	*dc = NULL;
- }
- 
-@@ -445,14 +445,14 @@ bool dc_validate_resources(
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	struct validate_context *context;
- 
--	context = dc_service_alloc(dc->ctx, sizeof(struct validate_context));
-+	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
- 	if(context == NULL)
- 		goto context_alloc_fail;
- 
- 	result = dc->res_pool.funcs->validate_with_context(
- 						dc, set, set_count, context);
- 
--	dc_service_free(dc->ctx, context);
-+	dm_free(dc->ctx, context);
- context_alloc_fail:
- 
- 	return (result == DC_OK);
-@@ -556,7 +556,7 @@ bool dc_commit_targets(
- 
- 	}
- 
--	context = dc_service_alloc(dc->ctx, sizeof(struct validate_context));
-+	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
- 	if (context == NULL)
- 		goto context_alloc_fail;
- 
-@@ -611,7 +611,7 @@ bool dc_commit_targets(
- 
- 	/* TODO: disable unused plls*/
- fail:
--	dc_service_free(dc->ctx, context);
-+	dm_free(dc->ctx, context);
- 
- context_alloc_fail:
- 	return (result == DC_OK);
-@@ -731,7 +731,7 @@ const struct dc_target *dc_get_target_on_irq_source(
- 		crtc_idx = src - DC_IRQ_SOURCE_PFLIP1;
- 		break;
- 	default:
--		dal_error("%s: invalid irq source: %d\n!",__func__, src);
-+		dm_error("%s: invalid irq source: %d\n!" ,__func__, src);
- 		return NULL;
- 	}
- 
-@@ -741,7 +741,7 @@ const struct dc_target *dc_get_target_on_irq_source(
- 		struct dc_target *dc_target;
- 
- 		if (NULL == target) {
--			dal_error("%s: 'dc_target' is NULL for irq source: %d\n!",
-+			dm_error("%s: 'dc_target' is NULL for irq source: %d\n!",
- 					__func__, src);
- 			continue;
- 		}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-index df7e89f..db4f131 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "core_types.h"
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 71653fa..b180cf6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -23,8 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
--#include "dc_helpers.h"
-+#include "dm_services.h"
-+#include "dm_helpers.h"
- #include "dc.h"
- #include "core_dc.h"
- #include "adapter_service_interface.h"
-@@ -449,7 +449,7 @@ static enum dc_edid_status read_edid(
- 
- 		dal_ddc_service_get_edid_buf(link->ddc,
- 				sink->public.dc_edid.raw_edid);
--		edid_status = dc_helpers_parse_edid_caps(
-+		edid_status = dm_helpers_parse_edid_caps(
- 				sink->ctx,
- 				&sink->public.dc_edid,
- 				&sink->public.edid_caps);
-@@ -524,7 +524,7 @@ static void detect_dp(
- 			 * TODO: s3 resume check
- 			 */
- 
--			if (dc_helpers_dp_mst_start_top_mgr(
-+			if (dm_helpers_dp_mst_start_top_mgr(
- 				link->ctx,
- 				&link->public, boot)) {
- 				link->public.type = dc_connection_mst_branch;
-@@ -718,7 +718,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 		if (link->public.type == dc_connection_mst_branch) {
- 			LINK_INFO("link=%d, mst branch is now Disconnected\n",
- 				link->public.link_index);
--			dc_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
-+			dm_helpers_dp_mst_stop_top_mgr(link->ctx, &link->public);
- 		}
- 
- 		link->public.type = dc_connection_none;
-@@ -905,7 +905,7 @@ static bool construct(
- 			init_params->connector_index);
- 
- 	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
--		dal_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d!\n",
-+		dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d!\n",
- 				__func__, init_params->connector_index);
- 		goto create_fail;
- 	}
-@@ -1057,7 +1057,7 @@ create_fail:
- struct core_link *link_create(const struct link_init_data *init_params)
- {
- 	struct core_link *link =
--			dc_service_alloc(init_params->ctx, sizeof(*link));
-+			dm_alloc(init_params->ctx, sizeof(*link));
- 
- 	if (NULL == link)
- 		goto alloc_fail;
-@@ -1068,7 +1068,7 @@ struct core_link *link_create(const struct link_init_data *init_params)
- 	return link;
- 
- construct_fail:
--	dc_service_free(init_params->ctx, link);
-+	dm_free(init_params->ctx, link);
- 
- alloc_fail:
- 	return NULL;
-@@ -1077,7 +1077,7 @@ alloc_fail:
- void link_destroy(struct core_link **link)
- {
- 	destruct(*link);
--	dc_service_free((*link)->ctx, *link);
-+	dm_free((*link)->ctx, *link);
- 	*link = NULL;
- }
- 
-@@ -1088,7 +1088,7 @@ static void dpcd_configure_panel_mode(
- 	union dpcd_edp_config edp_config_set;
- 	bool panel_mode_edp = false;
- 
--	dc_service_memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
-+	dm_memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
- 
- 	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
- 
-@@ -1211,7 +1211,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- 			normalized_pix_clk,
- 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
- 
--	dc_service_memset(&stream->sink->link->cur_link_settings, 0,
-+	dm_memset(&stream->sink->link->cur_link_settings, 0,
- 			sizeof(struct link_settings));
- 
- 	link->link_enc->funcs->enable_tmds_output(
-@@ -1237,7 +1237,7 @@ static enum dc_status enable_link(struct core_stream *stream)
- 		break;
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 		status = enable_link_dp_mst(stream);
--		dc_service_sleep_in_milliseconds(stream->ctx, 200);
-+		dm_sleep_in_milliseconds(stream->ctx, 200);
- 		break;
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
-@@ -1460,7 +1460,7 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 	 */
- 
- 	/* get calculate VC payload for stream: stream_alloc */
--	dc_helpers_dp_mst_write_payload_allocation_table(
-+	dm_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->public,
- 		&proposed_table,
-@@ -1509,11 +1509,11 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 		&link->mst_stream_alloc_table);
- 
- 	/* send down message */
--	dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+	dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
- 			&stream->public);
- 
--	dc_helpers_dp_mst_send_payload_allocation(
-+	dm_helpers_dp_mst_send_payload_allocation(
- 			stream->ctx,
- 			&stream->public,
- 			true);
-@@ -1557,12 +1557,12 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 
- 	/* TODO: which component is responsible for remove payload table? */
- 	if (mst_mode)
--		dc_helpers_dp_mst_write_payload_allocation_table(
-+		dm_helpers_dp_mst_write_payload_allocation_table(
- 				stream->ctx,
- 				&stream->public,
- 				&proposed_table,
- 				false);
--	dc_helpers_dp_mst_write_payload_allocation_table(
-+	dm_helpers_dp_mst_write_payload_allocation_table(
- 		stream->ctx,
- 		&stream->public,
- 		&proposed_table,
-@@ -1598,11 +1598,11 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 		&link->mst_stream_alloc_table);
- 
- 	if (mst_mode) {
--		dc_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 			stream->ctx,
- 			&stream->public);
- 
--		dc_helpers_dp_mst_send_payload_allocation(
-+		dm_helpers_dp_mst_send_payload_allocation(
- 			stream->ctx,
- 			&stream->public,
- 			false);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index 60fc743..62b8c26 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/adapter_service_interface.h"
- #include "include/ddc_service_types.h"
-@@ -188,7 +188,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_
- {
- 	struct i2c_payloads *payloads;
- 
--	payloads = dc_service_alloc(ctx, sizeof(struct i2c_payloads));
-+	payloads = dm_alloc(ctx, sizeof(struct i2c_payloads));
- 
- 	if (!payloads)
- 		return NULL;
-@@ -197,7 +197,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_
- 		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
- 		return payloads;
- 
--	dc_service_free(ctx, payloads);
-+	dm_free(ctx, payloads);
- 	return NULL;
- 
- }
-@@ -217,7 +217,7 @@ void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
- 	if (!p || !*p)
- 		return;
- 	dal_vector_destruct(&(*p)->payloads);
--	dc_service_free((*p)->payloads.ctx, *p);
-+	dm_free((*p)->payloads.ctx, *p);
- 	*p = NULL;
- 
- }
-@@ -226,7 +226,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_
- {
- 	struct aux_payloads *payloads;
- 
--	payloads = dc_service_alloc(ctx, sizeof(struct aux_payloads));
-+	payloads = dm_alloc(ctx, sizeof(struct aux_payloads));
- 
- 	if (!payloads)
- 		return NULL;
-@@ -235,7 +235,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_
- 		&payloads->payloads, ctx, count, sizeof(struct aux_payloads)))
- 		return payloads;
- 
--	dc_service_free(ctx, payloads);
-+	dm_free(ctx, payloads);
- 	return NULL;
- }
- 
-@@ -256,7 +256,7 @@ void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
- 		return;
- 
- 	dal_vector_destruct(&(*p)->payloads);
--	dc_service_free((*p)->payloads.ctx, *p);
-+	dm_free((*p)->payloads.ctx, *p);
- 	*p = NULL;
- }
- 
-@@ -341,7 +341,7 @@ struct ddc_service *dal_ddc_service_create(
- {
- 	struct ddc_service *ddc_service;
- 
--	ddc_service = dc_service_alloc(init_data->ctx, sizeof(struct ddc_service));
-+	ddc_service = dm_alloc(init_data->ctx, sizeof(struct ddc_service));
- 
- 	if (!ddc_service)
- 		return NULL;
-@@ -349,7 +349,7 @@ struct ddc_service *dal_ddc_service_create(
- 	if (construct(ddc_service, init_data))
- 		return ddc_service;
- 
--	dc_service_free(init_data->ctx, ddc_service);
-+	dm_free(init_data->ctx, ddc_service);
- 	return NULL;
- }
- 
-@@ -366,7 +366,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc)
- 		return;
- 	}
- 	destruct(*ddc);
--	dc_service_free((*ddc)->ctx, *ddc);
-+	dm_free((*ddc)->ctx, *ddc);
- 	*ddc = NULL;
- }
- 
-@@ -409,7 +409,7 @@ static uint32_t defer_delay_converter_wa(
- 
- 	if (dal_ddc_service_get_dp_receiver_id_info(ddc, &dp_rec_info) &&
- 		(dp_rec_info.branch_id == DP_BRANCH_DEVICE_ID_4) &&
--		!dal_strncmp(dp_rec_info.branch_name,
-+		!dm_strncmp(dp_rec_info.branch_name,
- 			DP_DVI_CONVERTER_ID_4,
- 			sizeof(dp_rec_info.branch_name)))
- 		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
-@@ -781,7 +781,7 @@ uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc)
- 
- void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf)
- {
--	dc_service_memmove(edid_buf,
-+	dm_memmove(edid_buf,
- 			ddc->edid_buf, ddc->edid_buf_len);
- }
- 
-@@ -1088,7 +1088,7 @@ struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
- 
- void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
- {
--	dc_service_memset(&ddc_service->dp_receiver_id_info,
-+	dm_memset(&ddc_service->dp_receiver_id_info,
- 		0, sizeof(struct dp_receiver_id_info));
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 96ba910..742ab75 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1,8 +1,9 @@
- /* Copyright 2015 Advanced Micro Devices, Inc. */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dc.h"
- #include "dc_link_dp.h"
--#include "dc_helpers.h"
-+#include "dm_helpers.h"
-+
- #include "inc/core_types.h"
- #include "link_hwss.h"
- #include "dc_link_ddc.h"
-@@ -69,7 +70,7 @@ static void wait_for_training_aux_rd_interval(
- 			default_wait_in_micro_secs;
- 	}
- 
--	dc_service_delay_in_microseconds(link->ctx, default_wait_in_micro_secs);
-+	dm_delay_in_microseconds(link->ctx, default_wait_in_micro_secs);
- 
- 	dal_logger_write(link->ctx->logger,
- 		LOG_MAJOR_HW_TRACE,
-@@ -231,7 +232,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 	size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
- 
- 	 // 0x00103 - 0x00102
--	dc_service_memmove(
-+	dm_memmove(
- 		&dpcd_lt_buffer[DPCD_ADDRESS_LANE0_SET - dpcd_base_lt_offset],
- 		dpcd_lane,
- 		size_in_bytes);
-@@ -458,7 +459,7 @@ static void get_lane_status_and_drive_settings(
- 	struct link_training_settings request_settings = {{0}};
- 	uint32_t lane;
- 
--	dc_service_memset(req_settings, '\0', sizeof(struct link_training_settings));
-+	dm_memset(req_settings, '\0', sizeof(struct link_training_settings));
- 
- 	core_link_read_dpcd(
- 		link,
-@@ -694,7 +695,7 @@ static bool perform_post_lt_adj_req_sequence(
- 				break;
- 			}
- 
--			dc_service_sleep_in_milliseconds(link->ctx, 1);
-+			dm_sleep_in_milliseconds(link->ctx, 1);
- 		}
- 
- 		if (!req_drv_setting_changed) {
-@@ -818,8 +819,8 @@ static bool perform_clock_recovery_sequence(
- 	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
- 	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
- 
--		dc_service_memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
--		dc_service_memset(&dpcd_lane_status_updated, '\0',
-+		dm_memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
-+		dm_memset(&dpcd_lane_status_updated, '\0',
- 		sizeof(dpcd_lane_status_updated));
- 
- 		/* 1. call HWSS to set lane settings*/
-@@ -908,7 +909,7 @@ static bool perform_clock_recovery_sequence(
- 	struct link_training_settings lt_settings;
- 
- 	status = false;
--	dc_service_memset(&lt_settings, '\0', sizeof(lt_settings));
-+	dm_memset(&lt_settings, '\0', sizeof(lt_settings));
- 
- 	lt_settings.link_settings.link_rate = link_setting->link_rate;
- 	lt_settings.link_settings.lane_count = link_setting->lane_count;
-@@ -1095,7 +1096,7 @@ bool dp_hbr_verify_link_cap(
- 				if (success)
- 					break;
- 
--				dc_service_sleep_in_milliseconds(
-+				dm_sleep_in_milliseconds(
- 					link->ctx,
- 					delay_between_retries);
- 
-@@ -1643,12 +1644,12 @@ static void retrieve_link_cap(struct core_link *link)
- 	union max_down_spread max_down_spread;
- 	union dp_downstream_port_present ds_port = { 0 };
- 
--	dc_service_memset(dpcd_data, '\0', sizeof(dpcd_data));
--	dc_service_memset(&down_strm_port_count,
-+	dm_memset(dpcd_data, '\0', sizeof(dpcd_data));
-+	dm_memset(&down_strm_port_count,
- 		'\0', sizeof(union down_stream_port_count));
--	dc_service_memset(&edp_config_cap, '\0',
-+	dm_memset(&edp_config_cap, '\0',
- 		sizeof(union edp_configuration_cap));
--	dc_service_memset(&max_down_spread, '\0',
-+	dm_memset(&max_down_spread, '\0',
- 		sizeof(union max_down_spread));
- 
- 	core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 656ec71..39aa734 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -1,6 +1,6 @@
- /* Copyright 2015 Advanced Micro Devices, Inc. */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dc.h"
- #include "inc/core_dc.h"
- #include "include/ddc_service_types.h"
-@@ -8,7 +8,7 @@
- #include "link_hwss.h"
- #include "hw_sequencer.h"
- #include "dc_link_ddc.h"
--#include "dc_helpers.h"
-+#include "dm_helpers.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_stream_encoder.h"
- 
-@@ -19,7 +19,7 @@ enum dc_status core_link_read_dpcd(
- 	uint8_t *data,
- 	uint32_t size)
- {
--	if (!dc_helper_dp_read_dpcd(link->ctx,
-+	if (!dm_helper_dp_read_dpcd(link->ctx,
- 			&link->public,
- 			address, data, size))
- 			return DC_ERROR_UNEXPECTED;
-@@ -33,7 +33,7 @@ enum dc_status core_link_write_dpcd(
- 	const uint8_t *data,
- 	uint32_t size)
- {
--	if (!dc_helper_dp_write_dpcd(link->ctx,
-+	if (!dm_helper_dp_write_dpcd(link->ctx,
- 			&link->public,
- 			address, data, size))
- 				return DC_ERROR_UNEXPECTED;
-@@ -89,7 +89,7 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 	link->link_enc->funcs->disable_output(link->link_enc, signal);
- 
- 	/* Clear current link setting.*/
--	dc_service_memset(&link->cur_link_settings, 0,
-+	dm_memset(&link->cur_link_settings, 0,
- 			sizeof(link->cur_link_settings));
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 65523e3..d166811 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "resource.h"
- #include "include/irq_service_interface.h"
-@@ -91,7 +91,7 @@ bool is_same_timing(
- 	const struct dc_crtc_timing *timing1,
- 	const struct dc_crtc_timing *timing2)
- {
--	return dal_memcmp(timing1, timing2, sizeof(struct dc_crtc_timing)) == 0;
-+	return dm_memcmp(timing1, timing2, sizeof(struct dc_crtc_timing)) == 0;
- }
- 
- static bool is_sharable_clk_src(
-@@ -425,7 +425,7 @@ bool logical_attach_surfaces_to_target(
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
- 
- 	if (surface_count > MAX_SURFACE_NUM) {
--		dal_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
-+		dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
- 			surface_count, MAX_SURFACE_NUM);
- 		return false;
- 	}
-@@ -521,7 +521,7 @@ static void fill_display_configs(
- void pplib_apply_safe_state(
- 	const struct dc *dc)
- {
--	dc_service_pp_apply_safe_state(dc->ctx);
-+	dm_pp_apply_safe_state(dc->ctx);
- }
- 
- void pplib_apply_display_requirements(
-@@ -566,7 +566,7 @@ void pplib_apply_display_requirements(
- 							/ timing->pix_clk_khz;
- 	}
- 
--	dc_service_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
-+	dm_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
- }
- 
- /* Maximum TMDS single link pixel clock 165MHz */
-@@ -872,7 +872,7 @@ static enum ds_color_space build_default_color_space(
- static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 	struct encoder_info_frame *encoder_info_frame)
- {
--	dc_service_memset(
-+	dm_memset(
- 		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
- 
- 	/* For gamut we recalc checksum */
-@@ -881,7 +881,7 @@ static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 		uint8_t *ptr;
- 		uint8_t i;
- 
--		dc_service_memmove(
-+		dm_memmove(
- 						&encoder_info_frame->gamut,
- 						&hw_info_frame->gamut_packet,
- 						sizeof(struct hw_info_packet));
-@@ -896,28 +896,28 @@ static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 	}
- 
- 	if (hw_info_frame->avi_info_packet.valid) {
--		dc_service_memmove(
-+		dm_memmove(
- 						&encoder_info_frame->avi,
- 						&hw_info_frame->avi_info_packet,
- 						sizeof(struct hw_info_packet));
- 	}
- 
- 	if (hw_info_frame->vendor_info_packet.valid) {
--		dc_service_memmove(
-+		dm_memmove(
- 						&encoder_info_frame->vendor,
- 						&hw_info_frame->vendor_info_packet,
- 						sizeof(struct hw_info_packet));
- 	}
- 
- 	if (hw_info_frame->spd_packet.valid) {
--		dc_service_memmove(
-+		dm_memmove(
- 						&encoder_info_frame->spd,
- 						&hw_info_frame->spd_packet,
- 						sizeof(struct hw_info_packet));
- 	}
- 
- 	if (hw_info_frame->vsc_packet.valid) {
--		dc_service_memmove(
-+		dm_memmove(
- 						&encoder_info_frame->vsc,
- 						&hw_info_frame->vsc_packet,
- 						sizeof(struct hw_info_packet));
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-index 608fb99..c5a770e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-@@ -23,8 +23,8 @@
-  *
-  */
- 
--#include "dc_services.h"
--#include "dc_helpers.h"
-+#include "dm_services.h"
-+#include "dm_helpers.h"
- #include "core_types.h"
- 
- /*******************************************************************************
-@@ -83,7 +83,7 @@ void dc_sink_release(const struct dc_sink *dc_sink)
- 
- 	if (sink->ref_count == 0) {
- 		destruct(sink);
--		dc_service_free(core_sink->ctx, sink);
-+		dm_free(core_sink->ctx, sink);
- 	}
- }
- 
-@@ -91,7 +91,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
- {
- 	struct core_link *core_link = DC_LINK_TO_LINK(init_params->link);
- 
--	struct sink *sink = dc_service_alloc(core_link->ctx, sizeof(*sink));
-+	struct sink *sink = dm_alloc(core_link->ctx, sizeof(*sink));
- 
- 	if (NULL == sink)
- 		goto alloc_fail;
-@@ -105,7 +105,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
- 	return &sink->protected.public;
- 
- construct_fail:
--	dc_service_free(core_link->ctx, sink);
-+	dm_free(core_link->ctx, sink);
- 
- alloc_fail:
- 	return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index ab8999b..d7012bc 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -22,7 +22,8 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+
-+#include "dm_services.h"
- #include "dc.h"
- #include "core_types.h"
- #include "resource.h"
-@@ -45,7 +46,7 @@ static void build_bit_depth_reduction_params(
- 		const struct core_stream *stream,
- 		struct bit_depth_reduction_params *fmt_bit_depth)
- {
--	dc_service_memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
-+	dm_memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
- 
- 	/*TODO: Need to un-hardcode, refer to function with same name
- 	 * in dal2 hw_sequencer*/
-@@ -107,7 +108,7 @@ static bool construct(struct core_stream *stream,
- 	stream->public.audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
- 	stream->public.audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
- 	stream->public.audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
--	dc_service_memmove(
-+	dm_memmove(
- 		stream->public.audio_info.display_name,
- 		dc_sink_data->edid_caps.display_name,
- 		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
-@@ -144,7 +145,7 @@ void dc_stream_release(struct dc_stream *public)
- 
- 	if (stream->ref_count == 0) {
- 		destruct(protected);
--		dc_service_free(ctx, stream);
-+		dm_free(ctx, stream);
- 	}
- }
- 
-@@ -156,7 +157,7 @@ struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink)
- 	if (sink == NULL)
- 		goto alloc_fail;
- 
--	stream = dc_service_alloc(sink->ctx, sizeof(struct stream));
-+	stream = dm_alloc(sink->ctx, sizeof(struct stream));
- 
- 	if (NULL == stream)
- 		goto alloc_fail;
-@@ -169,7 +170,7 @@ struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink)
- 	return &stream->protected.public;
- 
- construct_fail:
--	dc_service_free(sink->ctx, stream);
-+	dm_free(sink->ctx, stream);
- 
- alloc_fail:
- 	return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index ce60e9d..1a9ee8f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -24,7 +24,7 @@
-  */
- 
- /* DC interface (public) */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dc.h"
- 
- /* DC core (private) */
-@@ -85,7 +85,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 
- struct dc_surface *dc_create_surface(const struct dc *dc)
- {
--	struct surface *surface = dc_service_alloc(dc->ctx, sizeof(*surface));
-+	struct surface *surface = dm_alloc(dc->ctx, sizeof(*surface));
- 
- 	if (NULL == surface)
- 		goto alloc_fail;
-@@ -98,7 +98,7 @@ struct dc_surface *dc_create_surface(const struct dc *dc)
- 	return &surface->protected.public;
- 
- construct_fail:
--	dc_service_free(dc->ctx, surface);
-+	dm_free(dc->ctx, surface);
- 
- alloc_fail:
- 	return NULL;
-@@ -118,6 +118,6 @@ void dc_surface_release(const struct dc_surface *dc_surface)
- 
- 	if (surface->ref_count == 0) {
- 		destruct(surface);
--		dc_service_free(surface->protected.ctx, surface);
-+		dm_free(surface->protected.ctx, surface);
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index f114fc4..e93e73d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -22,7 +22,8 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+
-+#include "dm_services.h"
- #include "core_types.h"
- #include "hw_sequencer.h"
- #include "resource.h"
-@@ -93,7 +94,7 @@ void dc_target_release(struct dc_target *dc_target)
- 	target->ref_count--;
- 	if (target->ref_count == 0) {
- 		destruct(protected);
--		dc_service_free(protected->ctx, target);
-+		dm_free(protected->ctx, target);
- 	}
- }
- 
-@@ -116,7 +117,7 @@ struct dc_target *dc_create_target_for_streams(
- 
- 	stream = DC_STREAM_TO_CORE(dc_streams[0]);
- 
--	target = dc_service_alloc(stream->ctx, sizeof(struct target));
-+	target = dm_alloc(stream->ctx, sizeof(struct target));
- 
- 	if (NULL == target)
- 		goto target_alloc_fail;
-@@ -177,7 +178,7 @@ static bool program_gamma(
- 	struct gamma_parameters *gamma_param;
- 	bool result= false;
- 
--	gamma_param = dc_service_alloc(ctx, sizeof(struct gamma_parameters));
-+	gamma_param = dm_alloc(ctx, sizeof(struct gamma_parameters));
- 
- 	if (!gamma_param)
- 		goto gamma_param_fail;
-@@ -188,7 +189,7 @@ static bool program_gamma(
- 			&surface->gamma_correction,
- 			gamma_param);
- 
--	dc_service_free(ctx, gamma_param);
-+	dm_free(ctx, gamma_param);
- 
- gamma_param_fail:
- 	return result;
-@@ -357,7 +358,7 @@ void dc_target_enable_memory_requests(struct dc_target *target)
- 			DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
- 
- 		if (!tg->funcs->set_blank(tg, false)) {
--			dal_error("DC: failed to unblank crtc!\n");
-+			dm_error("DC: failed to unblank crtc!\n");
- 			BREAK_TO_DEBUGGER();
- 		}
- 	}
-@@ -372,13 +373,13 @@ void dc_target_disable_memory_requests(struct dc_target *target)
- 		DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
- 
- 		if (NULL == tg) {
--			dal_error("DC: timing generator is NULL!\n");
-+			dm_error("DC: timing generator is NULL!\n");
- 			BREAK_TO_DEBUGGER();
- 			continue;
- 		}
- 
- 		if (false == tg->funcs->set_blank(tg, true)) {
--			dal_error("DC: failed to blank crtc!\n");
-+			dm_error("DC: failed to blank crtc!\n");
- 			BREAK_TO_DEBUGGER();
- 		}
- 	}
-@@ -395,7 +396,7 @@ bool dc_target_set_cursor_attributes(
- 	struct input_pixel_processor *ipp;
- 
- 	if (NULL == dc_target) {
--		dal_error("DC: dc_target is NULL!\n");
-+		dm_error("DC: dc_target is NULL!\n");
- 			return false;
- 
- 	}
-@@ -404,7 +405,7 @@ bool dc_target_set_cursor_attributes(
- 	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
- 
- 	if (NULL == ipp) {
--		dal_error("DC: input pixel processor is NULL!\n");
-+		dm_error("DC: input pixel processor is NULL!\n");
- 		return false;
- 	}
- 
-@@ -422,12 +423,12 @@ bool dc_target_set_cursor_position(
- 	struct input_pixel_processor *ipp;
- 
- 	if (NULL == dc_target) {
--		dal_error("DC: dc_target is NULL!\n");
-+		dm_error("DC: dc_target is NULL!\n");
- 		return false;
- 	}
- 
- 	if (NULL == position) {
--		dal_error("DC: cursor position is NULL!\n");
-+		dm_error("DC: cursor position is NULL!\n");
- 		return false;
- 	}
- 
-@@ -435,7 +436,7 @@ bool dc_target_set_cursor_position(
- 	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
- 
- 	if (NULL == ipp) {
--		dal_error("DC: input pixel processor is NULL!\n");
-+		dm_error("DC: input pixel processor is NULL!\n");
- 		return false;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h b/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-deleted file mode 100644
-index 6bb1160..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dc_helpers.h
-+++ /dev/null
-@@ -1,98 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--/**
-- * This file defines helper functions provided by the Display Manager to
-- * Display Core.
-- */
--#ifndef __DC_HELPERS__
--#define __DC_HELPERS__
--
--#include "dc_types.h"
--#include "dc.h"
--
--struct dp_mst_stream_allocation_table;
--
--enum dc_edid_status dc_helpers_parse_edid_caps(
--	struct dc_context *ctx,
--	const struct dc_edid *edid,
--	struct dc_edid_caps *edid_caps);
--
--/*
-- * Writes payload allocation table in immediate downstream device.
-- */
--bool dc_helpers_dp_mst_write_payload_allocation_table(
--		struct dc_context *ctx,
--		const struct dc_stream *stream,
--		struct dp_mst_stream_allocation_table *proposed_table,
--		bool enable);
--
--/*
-- * Polls for ACT (allocation change trigger) handled and
-- */
--bool dc_helpers_dp_mst_poll_for_allocation_change_trigger(
--		struct dc_context *ctx,
--		const struct dc_stream *stream);
--/*
-- * Sends ALLOCATE_PAYLOAD message.
-- */
--bool dc_helpers_dp_mst_send_payload_allocation(
--		struct dc_context *ctx,
--		const struct dc_stream *stream,
--		bool enable);
--
--void dc_helpers_dp_mst_handle_mst_hpd_rx_irq(
--		void *param);
--
--bool dc_helpers_dp_mst_start_top_mgr(
--		struct dc_context *ctx,
--		const struct dc_link *link,
--		bool boot);
--
--void dc_helpers_dp_mst_stop_top_mgr(
--		struct dc_context *ctx,
--		const struct dc_link *link);
--
--/**
-- * OS specific aux read callback.
-- */
--bool dc_helper_dp_read_dpcd(
--		struct dc_context *ctx,
--		const struct dc_link *link,
--		uint32_t address,
--		uint8_t *data,
--		uint32_t size);
--
--/**
-- * OS specific aux write callback.
-- */
--bool dc_helper_dp_write_dpcd(
--		struct dc_context *ctx,
--		const struct dc_link *link,
--		uint32_t address,
--		const uint8_t *data,
--		uint32_t size);
--
--#endif /* __DC_HELPERS__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services.h b/drivers/gpu/drm/amd/dal/dc/dc_services.h
-deleted file mode 100644
-index fa1c39d..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dc_services.h
-+++ /dev/null
-@@ -1,490 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--/**
-- * This file defines external dependencies of Display Core.
-- */
--
--#ifndef __DC_SERVICES_H__
--#define __DC_SERVICES_H__
--
--/* TODO: remove when DC is complete. */
--#include "dc_services_types.h"
--#include "logger_interface.h"
--#include "include/dal_types.h"
--#include "irq_types.h"
--#include "link_service_types.h"
--
--#undef DEPRECATED
--
--/* if the pointer is not NULL, the allocated memory is zeroed */
--void *dc_service_alloc(struct dc_context *ctx, uint32_t size);
--
--/* reallocate memory. The contents will remain unchanged.*/
--void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
--
--void dc_service_free(struct dc_context *ctx, void *p);
--
--void dc_service_memset(void *p, int32_t c, uint32_t count);
--
--void dc_service_memmove(void *dst, const void *src, uint32_t size);
--
--/* TODO: rename to dc_memcmp*/
--int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
--
--int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
--
--irq_handler_idx dc_service_register_interrupt(
--	struct dc_context *ctx,
--	struct dc_interrupt_params *int_params,
--	interrupt_handler ih,
--	void *handler_args);
--
--void dc_service_unregister_interrupt(
--	struct dc_context *ctx,
--	enum dc_irq_source irq_source,
--	irq_handler_idx handler_idx);
--
--/*
-- *
-- * GPU registers access
-- *
-- */
--static inline uint32_t dal_read_reg(
--	const struct dc_context *ctx,
--	uint32_t address)
--{
--	uint32_t value = cgs_read_register(ctx->cgs_device, address);
--
--#if defined(__DAL_REGISTER_LOGGER__)
--	if (true == dal_reg_logger_should_dump_register()) {
--		dal_reg_logger_rw_count_increment();
--		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
--	}
--#endif
--	return value;
--}
--
--static inline void dal_write_reg(
--	const struct dc_context *ctx,
--	uint32_t address,
--	uint32_t value)
--{
--#if defined(__DAL_REGISTER_LOGGER__)
--	if (true == dal_reg_logger_should_dump_register()) {
--		dal_reg_logger_rw_count_increment();
--		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
--	}
--#endif
--	cgs_write_register(ctx->cgs_device, address, value);
--}
--
--static inline uint32_t dal_read_index_reg(
--	const struct dc_context *ctx,
--	enum cgs_ind_reg addr_space,
--	uint32_t index)
--{
--	return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
--}
--
--static inline void dal_write_index_reg(
--	const struct dc_context *ctx,
--	enum cgs_ind_reg addr_space,
--	uint32_t index,
--	uint32_t value)
--{
--	cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
--}
--
--static inline uint32_t get_reg_field_value_ex(
--	uint32_t reg_value,
--	uint32_t mask,
--	uint8_t shift)
--{
--	return (mask & reg_value) >> shift;
--}
--
--#define get_reg_field_value(reg_value, reg_name, reg_field)\
--	get_reg_field_value_ex(\
--		(reg_value),\
--		reg_name ## __ ## reg_field ## _MASK,\
--		reg_name ## __ ## reg_field ## __SHIFT)
--
--static inline uint32_t set_reg_field_value_ex(
--	uint32_t reg_value,
--	uint32_t value,
--	uint32_t mask,
--	uint8_t shift)
--{
--	return (reg_value & ~mask) | (mask & (value << shift));
--}
--
--#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
--	(reg_value) = set_reg_field_value_ex(\
--		(reg_value),\
--		(value),\
--		reg_name ## __ ## reg_field ## _MASK,\
--		reg_name ## __ ## reg_field ## __SHIFT)
--
--/*
-- * atombios services
-- */
--
--bool dal_exec_bios_cmd_table(
--	struct dc_context *ctx,
--	uint32_t index,
--	void *params);
--
--#ifdef BUILD_DAL_TEST
--uint32_t dal_bios_cmd_table_para_revision(
--struct dc_context *ctx,
--	uint32_t index);
--
--bool dal_bios_cmd_table_revision(
--	struct dc_context *ctx,
--	uint32_t index,
--	uint8_t *frev,
--	uint8_t *crev);
--#endif
--
--#ifndef BUILD_DAL_TEST
--static inline uint32_t dal_bios_cmd_table_para_revision(
--	struct dc_context *ctx,
--	uint32_t index)
--{
--	uint8_t frev;
--	uint8_t crev;
--
--	if (cgs_atom_get_cmd_table_revs(
--			ctx->cgs_device,
--			index,
--			&frev,
--			&crev) != 0)
--		return 0;
--
--	return crev;
--}
--#else
--uint32_t dal_bios_cmd_table_para_revision(
--		struct dc_context *ctx,
--		uint32_t index);
--#endif
--
--/**************************************
-- * Power Play (PP) interfaces
-- **************************************/
--
--enum dal_to_power_clocks_state {
--	PP_CLOCKS_STATE_INVALID,
--	PP_CLOCKS_STATE_ULTRA_LOW,
--	PP_CLOCKS_STATE_LOW,
--	PP_CLOCKS_STATE_NOMINAL,
--	PP_CLOCKS_STATE_PERFORMANCE
--};
--
--/* clocks in khz */
--struct dal_to_power_info {
--	enum dal_to_power_clocks_state required_clock;
--	uint32_t min_sclk;
--	uint32_t min_mclk;
--	uint32_t min_deep_sleep_sclk;
--};
--
--/* clocks in khz */
--struct power_to_dal_info {
--	uint32_t min_sclk;
--	uint32_t max_sclk;
--	uint32_t min_mclk;
--	uint32_t max_mclk;
--};
--
--/* clocks in khz */
--struct dal_system_clock_range {
--	uint32_t min_sclk;
--	uint32_t max_sclk;
--
--	uint32_t min_mclk;
--	uint32_t max_mclk;
--
--	uint32_t min_dclk;
--	uint32_t max_dclk;
--
--	/* Wireless Display */
--	uint32_t min_eclk;
--	uint32_t max_eclk;
--};
--
--/* clocks in khz */
--struct dal_to_power_dclk {
--	uint32_t optimal; /* input: best optimizes for stutter efficiency */
--	uint32_t minimal; /* input: the lowest clk that DAL can support */
--	uint32_t established; /* output: the actually set one */
--};
--
--/* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-- * This is done *before* it changes DCE clock.
-- *
-- * If required clock is higher than current, then PP will increase the voltage.
-- *
-- * If required clock is lower than current, then PP will defer reduction of
-- * voltage until the call to dc_service_pp_post_dce_clock_change().
-- *
-- * \input - Contains clocks needed for Mode Set.
-- *
-- * \output - Contains clocks adjusted by PP which DAL should use for Mode Set.
-- *		Valid only if function returns zero.
-- *
-- * \returns	true - call is successful
-- *		false - call failed
-- */
--bool dc_service_pp_pre_dce_clock_change(
--	struct dc_context *ctx,
--	struct dal_to_power_info *input,
--	struct power_to_dal_info *output);
--
--struct dc_pp_single_disp_config
--{
--	enum signal_type signal;
--	uint8_t transmitter;
--	uint8_t ddi_channel_mapping;
--	uint8_t pipe_idx;
--	uint32_t src_height;
--	uint32_t src_width;
--	uint32_t v_refresh;
--	uint32_t sym_clock; /* HDMI only */
--	struct link_settings link_settings; /* DP only */
--};
--
--struct dc_pp_display_configuration {
--	bool nb_pstate_switch_disable;/* controls NB PState switch */
--	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
--	bool cpu_pstate_disable;
--	uint32_t cpu_pstate_separation_time;
--
--	uint32_t min_memory_clock_khz;
--	uint32_t min_engine_clock_khz;
--	uint32_t min_engine_clock_deep_sleep_khz;
--
--	uint32_t avail_mclk_switch_time_us;
--	uint32_t avail_mclk_switch_time_in_disp_active_us;
--
--	uint32_t disp_clk_khz;
--
--	bool all_displays_in_sync;
--
--	uint8_t display_count;
--	struct dc_pp_single_disp_config disp_configs[3];
--
--	/*Controller Index of primary display - used in MCLK SMC switching hang
--	 * SW Workaround*/
--	uint8_t crtc_index;
--	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
--	uint32_t line_time_in_us;
--};
--
--enum dc_pp_clocks_state {
--	DC_PP_CLOCKS_STATE_INVALID = 0,
--	DC_PP_CLOCKS_STATE_ULTRA_LOW,
--	DC_PP_CLOCKS_STATE_LOW,
--	DC_PP_CLOCKS_STATE_NOMINAL,
--	DC_PP_CLOCKS_STATE_PERFORMANCE,
--
--	/* Starting from DCE11, Max 8 levels of DPM state supported. */
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DC_PP_CLOCKS_STATE_INVALID,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_0 = DC_PP_CLOCKS_STATE_ULTRA_LOW,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_1 = DC_PP_CLOCKS_STATE_LOW,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_2 = DC_PP_CLOCKS_STATE_NOMINAL,
--	/* to be backward compatible */
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_3 = DC_PP_CLOCKS_STATE_PERFORMANCE,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_4 = DC_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_5 = DC_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_6 = DC_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_7 = DC_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
--};
--
--struct dc_pp_static_clock_info {
--	uint32_t max_sclk_khz;
--	uint32_t max_mclk_khz;
--
--	 /* max possible display block clocks state */
--	enum dc_pp_clocks_state max_clocks_state;
--};
--
--/* The returned clocks range are 'static' system clocks which will be used for
-- * mode validation purposes.
-- *
-- * \returns	true - call is successful
-- *		false - call failed
-- */
--bool dc_service_get_system_clocks_range(
--	const struct dc_context *ctx,
--	struct dal_system_clock_range *sys_clks);
--
--enum dc_pp_clock_type {
--	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
--	DC_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
--	DC_PP_CLOCK_TYPE_MEMORY_CLK
--};
--
--#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
--	(clk_type) == DC_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
--	(clk_type) == DC_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
--	(clk_type) == DC_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
--
--#define DC_PP_MAX_CLOCK_LEVELS 8
--
--struct dc_pp_clock_levels {
--	uint32_t num_levels;
--	uint32_t clocks_in_khz[DC_PP_MAX_CLOCK_LEVELS];
--
--	/* TODO: add latency
--	 * do we need to know invalid (unsustainable boost) level for watermark
--	 * programming? if not we can just report less elements in array
--	 */
--};
--
--/* Gets valid clocks levels from pplib
-- *
-- * input: clk_type - display clk / sclk / mem clk
-- *
-- * output: array of valid clock levels for given type in ascending order,
-- * with invalid levels filtered out
-- *
-- */
--bool dc_service_pp_get_clock_levels_by_type(
--	const struct dc_context *ctx,
--	enum dc_pp_clock_type clk_type,
--	struct dc_pp_clock_levels *clk_level_info);
--
--
--bool dc_service_pp_apply_safe_state(
--		const struct dc_context *ctx);
--
--/* DAL calls this function to notify PP about completion of Mode Set.
-- * For PP it means that current DCE clocks are those which were returned
-- * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-- *
-- * If the clocks are higher than before, then PP does nothing.
-- *
-- * If the clocks are lower than before, then PP reduces the voltage.
-- *
-- * \returns	true - call is successful
-- *		false - call failed
-- */
--bool dc_service_pp_apply_display_requirements(
--	const struct dc_context *ctx,
--	const struct dc_pp_display_configuration *pp_display_cfg);
--
--
--/****** end of PP interfaces ******/
--
--void dc_service_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
--
--void dc_service_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds);
--
--enum platform_method {
--	PM_GET_AVAILABLE_METHODS = 1 << 0,
--	PM_GET_LID_STATE = 1 << 1,
--	PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2
--};
--
--struct platform_info_params {
--	enum platform_method method;
--	void *data;
--};
--
--struct platform_info_brightness_caps {
--	uint8_t ac_level_percentage;
--	uint8_t dc_level_percentage;
--};
--
--struct platform_info_ext_brightness_caps {
--	struct platform_info_brightness_caps basic_caps;
--	struct data_point {
--		uint8_t luminance;
--		uint8_t	signal_level;
--	} data_points[99];
--
--	uint8_t	data_points_num;
--	uint8_t	min_input_signal;
--	uint8_t	max_input_signal;
--};
--
--bool dal_get_platform_info(
--	struct dc_context *ctx,
--	struct platform_info_params *params);
--
--/*
-- *
-- * print-out services
-- *
-- */
--#define dal_log_to_buffer(buffer, size, fmt, args)\
--	vsnprintf(buffer, size, fmt, args)
--
--long dal_get_pid(void);
--long dal_get_tgid(void);
--
--/*
-- *
-- * general debug capabilities
-- *
-- */
--#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
--
--#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
--#define ASSERT_CRITICAL(expr) do {	\
--	if (WARN_ON(!(expr))) { \
--		kgdb_breakpoint(); \
--	} \
--} while (0)
--#else
--#define ASSERT_CRITICAL(expr) do {	\
--	if (WARN_ON(!(expr))) { \
--		; \
--	} \
--} while (0)
--#endif
--
--#if defined(CONFIG_DEBUG_KERNEL_DAL)
--#define ASSERT(expr) ASSERT_CRITICAL(expr)
--
--#else
--#define ASSERT(expr) WARN_ON(!(expr))
--#endif
--
--#define BREAK_TO_DEBUGGER() ASSERT(0)
--
--#else
--
--#define ASSERT_CRITICAL(expr)  do {if (expr)/* Do nothing */; } while (0)
--
--#define ASSERT(expr) do {if (expr)/* Do nothing */; } while (0)
--
--#define BREAK_TO_DEBUGGER() do {} while (0)
--
--#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
--
--#endif /* __DC_SERVICES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_services_types.h b/drivers/gpu/drm/amd/dal/dc/dc_services_types.h
-deleted file mode 100644
-index aded7b1..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dc_services_types.h
-+++ /dev/null
-@@ -1,167 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DC_SERVICES_TYPES_H__
--#define __DC_SERVICES_TYPES_H__
--
--#define INVALID_DISPLAY_INDEX 0xffffffff
--
--#if defined __KERNEL__
--
--#include <asm/byteorder.h>
--#include <linux/types.h>
--#include <drm/drmP.h>
--
--#include "cgs_linux.h"
--
--#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
--#define BIGENDIAN_CPU
--#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
--#define LITTLEENDIAN_CPU
--#endif
--
--#undef READ
--#undef WRITE
--#undef FRAME_SIZE
--
--#define dal_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
--
--#define dal_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
--
--#define dal_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
--
--#define dal_vlog(fmt, args) vprintk(fmt, args)
--
--#define dal_min(x, y) min(x, y)
--#define dal_max(x, y) max(x, y)
--
--#elif defined BUILD_DAL_TEST
--
--#include <inttypes.h>
--#include <stdlib.h>
--#include <string.h>
--
--#include <stdio.h>
--
--#include <stdarg.h>
--
--#include "cgs_linux.h"
--
--#define LONG_MAX	((long)(~0UL>>1))
--#define LONG_MIN	(-LONG_MAX - 1)
--#define LLONG_MAX	((long long)(~0ULL>>1))
--#define LLONG_MIN	(-LLONG_MAX - 1)
--#define UINT_MAX	(~0U)
--
--typedef _Bool bool;
--enum { false, true };
--
--#ifndef NULL
--#define NULL ((void *)0)
--#endif
--
--#define LITTLEENDIAN_CPU 1
--
--#include <test_context.h>
--
--#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
--
--#define container_of(ptr, type, member) \
--	((type *)((char *)(ptr) - offsetof(type, member)))
--
--#define dal_test_not_implemented() \
--	printf("[DAL_TEST_NOT_IMPL]:%s\n", __func__)
--
--#define dal_output_to_console(fmt, ...) do { \
--	printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
--	while (false)
--
--#define dal_error(fmt, ...) printf("[DAL_ERROR]" fmt, ##__VA_ARGS__)
--
--#define dal_output_to_console(fmt, ...) do { \
--			printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
--				while (false)
--
--
--#define dal_debug(fmt, ...) printf("[DAL_DBG]" fmt, ##__VA_ARGS__)
--
--#define dal_vlog(fmt, args) vprintf(fmt, args)
--
--#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
--
--#define dal_min(x, y) ({\
--	typeof(x) _min1 = (x);\
--	typeof(y) _min2 = (y);\
--	(void) (&_min1 == &_min2);\
--	_min1 < _min2 ? _min1 : _min2; })
--
--#define dal_max(x, y) ({\
--	typeof(x) _max1 = (x);\
--	typeof(y) _max2 = (y);\
--	(void) (&_max1 == &_max2);\
--	_max1 > _max2 ? _max1 : _max2; })
--
--/* division functions */
--
--static inline int64_t div64_s64(int64_t x, int64_t y)
--{
--	return x / y;
--}
--
--static inline uint64_t div64_u64(uint64_t x, uint64_t y)
--{
--	return x / y;
--}
--
--static inline uint64_t div_u64(uint64_t x, uint32_t y)
--{
--	return x / y;
--}
--
--static inline uint64_t div64_u64_rem(uint64_t x, uint64_t y, uint64_t *rem)
--{
--	if (rem)
--		*rem = x % y;
--	return x / y;
--}
--
--static inline uint64_t div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem)
--{
--	if (rem)
--		*rem = x % y;
--	return x / y;
--}
--
--#define cpu_to_le16(do_nothing) do_nothing
--
--#define le16_to_cpu(do_nothing) do_nothing
--
--#define cpu_to_le32(do_nothing) do_nothing
--
--#define le32_to_cpu(do_nothing) do_nothing
--
--#endif
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 0a48ef4..c238531 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -25,7 +25,7 @@
- #ifndef DC_TYPES_H_
- #define DC_TYPES_H_
- 
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- #include "fixed32_32.h"
- #include "fixed31_32.h"
- #include "irq_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index 75aff2a..82c5e15 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dc.h"
- #include "core_dc.h"
- #include "core_types.h"
-@@ -88,7 +88,7 @@ static void dce100_enable_fe_clock(
- 
- 	addr = HW_REG_CRTC(mmDCFE_CLOCK_CONTROL, controller_id);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -96,7 +96,7 @@ static void dce100_enable_fe_clock(
- 		DCFE_CLOCK_CONTROL,
- 		DCFE_CLOCK_ENABLE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static bool dce100_pipe_control_lock(
-@@ -106,7 +106,7 @@ static bool dce100_pipe_control_lock(
- 	bool lock)
- {
- 	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 	bool need_to_wait = false;
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-@@ -146,7 +146,7 @@ static bool dce100_pipe_control_lock(
- 			BLND_V_UPDATE_LOCK,
- 			BLND_V_UPDATE_LOCK_MODE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	if (!lock && need_to_wait) {
- 		uint8_t counter = 0;
-@@ -159,7 +159,7 @@ static bool dce100_pipe_control_lock(
- 				controller_idx);
- 
- 		while (counter < counter_limit) {
--			value = dal_read_reg(ctx, addr);
-+			value = dm_read_reg(ctx, addr);
- 
- 			pipe_pending = 0;
- 
-@@ -214,7 +214,7 @@ static bool dce100_pipe_control_lock(
- 				break;
- 
- 			counter++;
--			dc_service_delay_in_microseconds(ctx, delay_us);
-+			dm_delay_in_microseconds(ctx, delay_us);
- 		}
- 
- 		if (counter == counter_limit) {
-@@ -267,7 +267,7 @@ static void dce100_set_blender_mode(
- 		break;
- 	}
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -281,7 +281,7 @@ static void dce100_set_blender_mode(
- 		BLND_CONTROL,
- 		BLND_MODE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static bool dce100_enable_display_power_gating(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 9d438a9..e67ba81 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -22,7 +22,8 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+
-+#include "dm_services.h"
- 
- #include "link_encoder.h"
- #include "stream_encoder.h"
-@@ -340,7 +341,7 @@ static struct timing_generator *dce100_timing_generator_create(
- 		const struct dce110_timing_generator_offsets *offsets)
- {
- 	struct dce110_timing_generator *tg110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_timing_generator));
-+		dm_alloc(ctx, sizeof(struct dce110_timing_generator));
- 
- 	if (!tg110)
- 		return NULL;
-@@ -350,7 +351,7 @@ static struct timing_generator *dce100_timing_generator_create(
- 		return &tg110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, tg110);
-+	dm_free(ctx, tg110);
- 	return NULL;
- }
- 
-@@ -361,7 +362,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
- 	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+		dm_alloc(ctx, sizeof(struct dce110_stream_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -370,7 +371,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, enc110);
-+	dm_free(ctx, enc110);
- 	return NULL;
- }
- 
-@@ -380,7 +381,7 @@ static struct mem_input *dce100_mem_input_create(
- 	const struct dce110_mem_input_reg_offsets *offset)
- {
- 	struct dce110_mem_input *mem_input110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_mem_input));
-+		dm_alloc(ctx, sizeof(struct dce110_mem_input));
- 
- 	if (!mem_input110)
- 		return NULL;
-@@ -390,13 +391,13 @@ static struct mem_input *dce100_mem_input_create(
- 		return &mem_input110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, mem_input110);
-+	dm_free(ctx, mem_input110);
- 	return NULL;
- }
- 
- static void dce100_transform_destroy(struct transform **xfm)
- {
--	dc_service_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	dm_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
- 	*xfm = NULL;
- }
- 
-@@ -406,7 +407,7 @@ static struct transform *dce100_transform_create(
- 	const struct dce110_transform_reg_offsets *offsets)
- {
- 	struct dce110_transform *transform =
--		dc_service_alloc(ctx, sizeof(struct dce110_transform));
-+		dm_alloc(ctx, sizeof(struct dce110_transform));
- 
- 	if (!transform)
- 		return NULL;
-@@ -415,7 +416,7 @@ static struct transform *dce100_transform_create(
- 		return &transform->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, transform);
-+	dm_free(ctx, transform);
- 	return NULL;
- }
- 
-@@ -425,7 +426,7 @@ static struct input_pixel_processor *dce100_ipp_create(
- 	const struct dce110_ipp_reg_offsets *offsets)
- {
- 	struct dce110_ipp *ipp =
--		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
-+		dm_alloc(ctx, sizeof(struct dce110_ipp));
- 
- 	if (!ipp)
- 		return NULL;
-@@ -434,7 +435,7 @@ static struct input_pixel_processor *dce100_ipp_create(
- 		return &ipp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, ipp);
-+	dm_free(ctx, ipp);
- 	return NULL;
- }
- 
-@@ -442,7 +443,7 @@ struct link_encoder *dce100_link_encoder_create(
- 	const struct encoder_init_data *enc_init_data)
- {
- 	struct dce110_link_encoder *enc110 =
--		dc_service_alloc(
-+		dm_alloc(
- 			enc_init_data->ctx,
- 			sizeof(struct dce110_link_encoder));
- 
-@@ -458,7 +459,7 @@ struct link_encoder *dce100_link_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(enc_init_data->ctx, enc110);
-+	dm_free(enc_init_data->ctx, enc110);
- 	return NULL;
- }
- 
-@@ -469,7 +470,7 @@ struct output_pixel_processor *dce100_opp_create(
- 	const struct dce110_opp_reg_offsets *offset)
- {
- 	struct dce110_opp *opp =
--		dc_service_alloc(ctx, sizeof(struct dce110_opp));
-+		dm_alloc(ctx, sizeof(struct dce110_opp));
- 
- 	if (!opp)
- 		return NULL;
-@@ -479,24 +480,24 @@ struct output_pixel_processor *dce100_opp_create(
- 		return &opp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, opp);
-+	dm_free(ctx, opp);
- 	return NULL;
- }
- 
- 
- void dce100_opp_destroy(struct output_pixel_processor **opp)
- {
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
- 	*opp = NULL;
- }
- 
-@@ -507,7 +508,7 @@ struct clock_source *dce100_clock_source_create(
- 	const struct dce110_clk_src_reg_offsets *offsets)
- {
- 	struct dce110_clk_src *clk_src =
--		dc_service_alloc(ctx, sizeof(struct dce110_clk_src));
-+		dm_alloc(ctx, sizeof(struct dce110_clk_src));
- 
- 	if (!clk_src)
- 		return NULL;
-@@ -521,7 +522,7 @@ struct clock_source *dce100_clock_source_create(
- 
- void dce100_clock_source_destroy(struct clock_source **clk_src)
- {
--	dc_service_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	dm_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
- 	*clk_src = NULL;
- }
- 
-@@ -540,13 +541,13 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dc_service_free(pool->mis[i]->ctx,
-+			dm_free(pool->mis[i]->ctx,
- 					TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx,
-+			dm_free(pool->timing_generators[i]->ctx,
- 					DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
-@@ -554,7 +555,7 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dc_service_free(pool->stream_enc[i]->ctx,
-+			dm_free(pool->stream_enc[i]->ctx,
- 				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
-@@ -775,7 +776,6 @@ enum dc_status dce100_validate_bandwidth(
- 	/* TODO implement when needed */
- 
- 	return DC_OK;
--
- }
- 
- static void set_target_unchanged(
-@@ -942,7 +942,7 @@ bool dce100_construct_resource_pool(
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
--			dal_error("DC: failed to create clock sources!\n");
-+			dm_error("DC: failed to create clock sources!\n");
- 			BREAK_TO_DEBUGGER();
- 			goto clk_src_create_fail;
- 		}
-@@ -950,7 +950,7 @@ bool dce100_construct_resource_pool(
- 
- 	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
- 	if (pool->display_clock == NULL) {
--		dal_error("DC: failed to create display clock!\n");
-+		dm_error("DC: failed to create display clock!\n");
- 		BREAK_TO_DEBUGGER();
- 		goto disp_clk_create_fail;
- 	}
-@@ -975,7 +975,7 @@ bool dce100_construct_resource_pool(
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
--		dal_error("DC: failed to create filter!\n");
-+		dm_error("DC: failed to create filter!\n");
- 		goto filter_create_fail;
- 	}
- 
-@@ -984,7 +984,7 @@ bool dce100_construct_resource_pool(
- 				adapter_serv, ctx, i, &dce100_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create tg!\n");
-+			dm_error("DC: failed to create tg!\n");
- 			goto controller_create_fail;
- 		}
- 
-@@ -992,7 +992,7 @@ bool dce100_construct_resource_pool(
- 				&dce100_mi_reg_offsets[i]);
- 		if (pool->mis[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create memory input!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1001,7 +1001,7 @@ bool dce100_construct_resource_pool(
- 				&dce100_ipp_reg_offsets[i]);
- 		if (pool->ipps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create input pixel processor!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1010,7 +1010,7 @@ bool dce100_construct_resource_pool(
- 					ctx, i, &dce100_xfm_offsets[i]);
- 		if (pool->transforms[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create transform!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1021,7 +1021,7 @@ bool dce100_construct_resource_pool(
- 		pool->opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]);
- 		if (pool->opps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create output pixel processor!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1043,7 +1043,7 @@ bool dce100_construct_resource_pool(
- 		pool->audios[i] = dal_audio_create(&audio_init_data);
- 		if (pool->audios[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create DPPs!\n");
-+			dm_error("DC: failed to create DPPs!\n");
- 			goto audio_create_fail;
- 		}
- 		pool->audio_count++;
-@@ -1059,7 +1059,7 @@ bool dce100_construct_resource_pool(
- 				&stream_enc_regs[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
--				dal_error("DC: failed to create stream_encoder!\n");
-+				dm_error("DC: failed to create stream_encoder!\n");
- 				goto stream_enc_create_fail;
- 			}
- 		}
-@@ -1072,7 +1072,7 @@ bool dce100_construct_resource_pool(
- 								adapter_serv));
- 		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create stream_encoder!\n");
-+			dm_error("DC: failed to create stream_encoder!\n");
- 			goto stream_enc_create_fail;
- 		}
- 		pool->stream_enc_count++;
-@@ -1083,7 +1083,7 @@ bool dce100_construct_resource_pool(
- stream_enc_create_fail:
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dc_service_free(pool->stream_enc[i]->ctx,
-+			dm_free(pool->stream_enc[i]->ctx,
- 				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
-@@ -1105,13 +1105,13 @@ controller_create_fail:
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dc_service_free(pool->mis[i]->ctx,
-+			dm_free(pool->mis[i]->ctx,
- 					TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx,
-+			dm_free(pool->timing_generators[i]->ctx,
- 				DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index f0cf18f..e1bac1f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -476,7 +476,7 @@ static uint32_t dce110_get_pix_clk_dividers(
- 		return pll_calc_error;
- 	}
- 
--	dc_service_memset(pll_settings, 0, sizeof(*pll_settings));
-+	dm_memset(pll_settings, 0, sizeof(*pll_settings));
- 
- 	if (cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
- 		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-@@ -492,7 +492,7 @@ static uint32_t dce110_get_pix_clk_dividers(
- 	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
- 	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
- 	addr = clk_src->offsets.pll_cntl;
--	value = dal_read_reg(clk_src->base.ctx, addr);
-+	value = dm_read_reg(clk_src->base.ctx, addr);
- 	field = get_reg_field_value(value, PLL_CNTL, PLL_REF_DIV_SRC);
- 	pll_settings->use_external_clk = (field > 1);
- 
-@@ -583,7 +583,7 @@ static bool calculate_ss(
- 		return false;
- 
- 
--	dc_service_memset(ds_data, 0, sizeof(struct delta_sigma_data));
-+	dm_memset(ds_data, 0, sizeof(struct delta_sigma_data));
- 
- 
- 
-@@ -683,7 +683,7 @@ static void program_pixel_clk_resync(
- {
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(clk_src->base.ctx, clk_src->offsets.pixclk_resync_cntl);
-+	value = dm_read_reg(clk_src->base.ctx, clk_src->offsets.pixclk_resync_cntl);
- 
- 	set_reg_field_value(
- 		value,
-@@ -733,7 +733,7 @@ static void program_pixel_clk_resync(
- 		break;
- 	}
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		clk_src->base.ctx,
- 		clk_src->offsets.pixclk_resync_cntl,
- 		value);
-@@ -868,13 +868,13 @@ static void get_ss_info_from_atombios(
- 	if (*ss_entries_num == 0)
- 		return;
- 
--	ss_info = dc_service_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_info)
-+	ss_info = dm_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_info)
- 				* (*ss_entries_num));
- 	ss_info_cur = ss_info;
- 	if (ss_info == NULL)
- 		return;
- 
--	ss_data = dc_service_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_data) *
-+	ss_data = dm_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_data) *
- 							(*ss_entries_num));
- 	if (ss_data == NULL)
- 		goto out_free_info;
-@@ -949,14 +949,14 @@ static void get_ss_info_from_atombios(
- 	}
- 
- 	*spread_spectrum_data = ss_data;
--	dc_service_free(clk_src->base.ctx, ss_info);
-+	dm_free(clk_src->base.ctx, ss_info);
- 	return;
- 
- out_free_data:
--	dc_service_free(clk_src->base.ctx, ss_data);
-+	dm_free(clk_src->base.ctx, ss_data);
- 	*ss_entries_num = 0;
- out_free_info:
--	dc_service_free(clk_src->base.ctx, ss_info);
-+	dm_free(clk_src->base.ctx, ss_info);
- }
- 
- static void ss_info_from_atombios_create(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-index 6761b4f..285d544 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -313,13 +313,13 @@ static void wait_for_fbc_state_changed(
- 	uint32_t value;
- 
- 	while (counter < 10) {
--		value = dal_read_reg(cp110->base.ctx, addr);
-+		value = dm_read_reg(cp110->base.ctx, addr);
- 		if (get_reg_field_value(
- 			value,
- 			FBC_STATUS,
- 			FBC_ENABLE_STATUS) == enabled)
- 			break;
--		dc_service_delay_in_microseconds(cp110->base.ctx, 10);
-+		dm_delay_in_microseconds(cp110->base.ctx, 10);
- 		counter++;
- 	}
- 
-@@ -339,7 +339,7 @@ void dce110_compressor_power_up_fbc(struct compressor *compressor)
- 	uint32_t addr;
- 
- 	addr = mmFBC_CNTL;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
- 	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
- 	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-@@ -351,32 +351,32 @@ void dce110_compressor_power_up_fbc(struct compressor *compressor)
- 			FBC_CNTL,
- 			FBC_COMP_CLK_GATE_EN);
- 	}
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	addr = mmFBC_COMP_MODE;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
- 	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
- 	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	addr = mmFBC_COMP_CNTL;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
- 	/*                    1 ==> 4:1 */
- 	/*                    2 ==> 8:1 */
- 	/*                  0xF ==> 1:1 */
- 	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
- 
- 	value = 0;
--	dal_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
- 
- 	value = 0xFFFFFF;
--	dal_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
- }
- 
- void dce110_compressor_enable_fbc(
-@@ -408,13 +408,13 @@ void dce110_compressor_enable_fbc(
- 		}
- 
- 		addr = mmFBC_CNTL;
--		value = dal_read_reg(compressor->ctx, addr);
-+		value = dm_read_reg(compressor->ctx, addr);
- 		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
- 		set_reg_field_value(
- 			value,
- 			params->inst,
- 			FBC_CNTL, FBC_SRC_SEL);
--		dal_write_reg(compressor->ctx, addr, value);
-+		dm_write_reg(compressor->ctx, addr, value);
- 
- 		/* Keep track of enum controller_id FBC is attached to */
- 		compressor->is_enabled = true;
-@@ -423,9 +423,9 @@ void dce110_compressor_enable_fbc(
- 
- 		/*Toggle it as there is bug in HW */
- 		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
--		dal_write_reg(compressor->ctx, addr, value);
-+		dm_write_reg(compressor->ctx, addr, value);
- 		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
--		dal_write_reg(compressor->ctx, addr, value);
-+		dm_write_reg(compressor->ctx, addr, value);
- 
- 		wait_for_fbc_state_changed(cp110, true);
- 	}
-@@ -439,9 +439,9 @@ void dce110_compressor_disable_fbc(struct compressor *compressor)
- 		dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
- 		uint32_t reg_data;
- 		/* Turn off compression */
--		reg_data = dal_read_reg(compressor->ctx, mmFBC_CNTL);
-+		reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
- 		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
--		dal_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+		dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
- 
- 		/* Reset enum controller_id to undefined */
- 		compressor->attached_inst = 0;
-@@ -463,16 +463,16 @@ bool dce110_compressor_is_fbc_enabled_in_hw(
- 	/* Check the hardware register */
- 	uint32_t value;
- 
--	value = dal_read_reg(compressor->ctx, mmFBC_STATUS);
-+	value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
- 	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
- 		if (inst != NULL)
- 			*inst = compressor->attached_inst;
- 		return true;
- 	}
- 
--	value = dal_read_reg(compressor->ctx, mmFBC_MISC);
-+	value = dm_read_reg(compressor->ctx, mmFBC_MISC);
- 	if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
--		value = dal_read_reg(compressor->ctx, mmFBC_CNTL);
-+		value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
- 
- 		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
- 			if (inst != NULL)
-@@ -487,7 +487,7 @@ bool dce110_compressor_is_fbc_enabled_in_hw(
- bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
- {
- 	/* Check the hardware register */
--	uint32_t value = dal_read_reg(compressor->ctx,
-+	uint32_t value = dm_read_reg(compressor->ctx,
- 		mmLOW_POWER_TILING_CONTROL);
- 
- 	return get_reg_field_value(
-@@ -507,11 +507,11 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
- 		compressor->compr_surface_address.addr.low_part;
- 
- 	/* Clear content first. */
--	dal_write_reg(
-+	dm_write_reg(
- 		compressor->ctx,
- 		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
- 		0);
--	dal_write_reg(compressor->ctx,
-+	dm_write_reg(compressor->ctx,
- 		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
- 
- 	if (compressor->options.bits.LPT_SUPPORT) {
-@@ -526,10 +526,10 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
- 	}
- 
- 	/* Write address, HIGH has to be first. */
--	dal_write_reg(compressor->ctx,
-+	dm_write_reg(compressor->ctx,
- 		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
- 		compressor->compr_surface_address.addr.high_part);
--	dal_write_reg(compressor->ctx,
-+	dm_write_reg(compressor->ctx,
- 		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
- 		compressed_surf_address_low_part);
- 
-@@ -548,7 +548,7 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
- 			__func__);
- 
- 	/* Clear content first. */
--	dal_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
- 
- 	/* Write FBC Pitch. */
- 	set_reg_field_value(
-@@ -556,7 +556,7 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
- 		fbc_pitch,
- 		GRPH_COMPRESS_PITCH,
- 		GRPH_COMPRESS_PITCH);
--	dal_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
- 
- }
- 
-@@ -570,7 +570,7 @@ void dce110_compressor_disable_lpt(struct compressor *compressor)
- 	/* Disable all pipes LPT Stutter */
- 	for (inx = 0; inx < 3; inx++) {
- 		value =
--			dal_read_reg(
-+			dm_read_reg(
- 				compressor->ctx,
- 				DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
- 		set_reg_field_value(
-@@ -578,40 +578,40 @@ void dce110_compressor_disable_lpt(struct compressor *compressor)
- 			0,
- 			DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
- 			STUTTER_ENABLE_NONLPTCH);
--		dal_write_reg(
-+		dm_write_reg(
- 			compressor->ctx,
- 			DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
- 			value);
- 	}
- 	/* Disable Underlay pipe LPT Stutter */
- 	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		0,
- 		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
- 		STUTTER_ENABLE_NONLPTCH);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	/* Disable LPT */
- 	addr = mmLOW_POWER_TILING_CONTROL;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		0,
- 		LOW_POWER_TILING_CONTROL,
- 		LOW_POWER_TILING_ENABLE);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	/* Clear selection of Channel(s) containing Compressed Surface */
- 	addr = mmGMCON_LPT_TARGET;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		0xFFFFFFFF,
- 		GMCON_LPT_TARGET,
- 		STCTRL_LPT_TARGET);
--	dal_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
-+	dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
- }
- 
- void dce110_compressor_enable_lpt(struct compressor *compressor)
-@@ -623,54 +623,54 @@ void dce110_compressor_enable_lpt(struct compressor *compressor)
- 	uint32_t channels;
- 
- 	/* Enable LPT Stutter from Display pipe */
--	value = dal_read_reg(compressor->ctx,
-+	value = dm_read_reg(compressor->ctx,
- 		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
- 	set_reg_field_value(
- 		value,
- 		1,
- 		DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
- 		STUTTER_ENABLE_NONLPTCH);
--	dal_write_reg(compressor->ctx,
-+	dm_write_reg(compressor->ctx,
- 		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
- 
- 	/* Enable Underlay pipe LPT Stutter */
- 	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
- 		STUTTER_ENABLE_NONLPTCH);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	/* Selection of Channel(s) containing Compressed Surface: 0xfffffff
- 	 * will disable LPT.
- 	 * STCTRL_LPT_TARGETn corresponds to channel n. */
- 	addr = mmLOW_POWER_TILING_CONTROL;
--	value_control = dal_read_reg(compressor->ctx, addr);
-+	value_control = dm_read_reg(compressor->ctx, addr);
- 	channels = get_reg_field_value(value_control,
- 			LOW_POWER_TILING_CONTROL,
- 			LOW_POWER_TILING_MODE);
- 
- 	addr = mmGMCON_LPT_TARGET;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		channels + 1, /* not mentioned in programming guide,
- 				but follow DCE8.1 */
- 		GMCON_LPT_TARGET,
- 		STCTRL_LPT_TARGET);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	/* Enable LPT */
- 	addr = mmLOW_POWER_TILING_CONTROL;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		LOW_POWER_TILING_CONTROL,
- 		LOW_POWER_TILING_ENABLE);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- }
- 
- void dce110_compressor_program_lpt_control(
-@@ -687,7 +687,7 @@ void dce110_compressor_program_lpt_control(
- 	if (!compressor->options.bits.LPT_SUPPORT)
- 		return;
- 
--	lpt_control = dal_read_reg(compressor->ctx,
-+	lpt_control = dm_read_reg(compressor->ctx,
- 		mmLOW_POWER_TILING_CONTROL);
- 
- 	/* POSSIBLE VALUES for Low Power Tiling Mode:
-@@ -745,7 +745,7 @@ void dce110_compressor_program_lpt_control(
- 		LOW_POWER_TILING_CONTROL,
- 		LOW_POWER_TILING_ROWS_PER_CHAN);
- 
--	dal_write_reg(compressor->ctx,
-+	dm_write_reg(compressor->ctx,
- 		mmLOW_POWER_TILING_CONTROL, lpt_control);
- }
- 
-@@ -762,14 +762,14 @@ void dce110_compressor_set_fbc_invalidation_triggers(
- 	 * for DCE 11 regions cannot be used - does not work with S/G
- 	 */
- 	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
--	uint32_t value = dal_read_reg(compressor->ctx, addr);
-+	uint32_t value = dm_read_reg(compressor->ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
- 		0,
- 		FBC_CLIENT_REGION_MASK,
- 		FBC_MEMORY_REGION_MASK);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- 
- 	/* Setup events when to clear all CSM entries (effectively marking
- 	 * current compressed data invalid)
-@@ -796,7 +796,7 @@ void dce110_compressor_set_fbc_invalidation_triggers(
- 	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
- 	 */
- 	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
--	value = dal_read_reg(compressor->ctx, addr);
-+	value = dm_read_reg(compressor->ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		fbc_trigger |
-@@ -808,7 +808,7 @@ void dce110_compressor_set_fbc_invalidation_triggers(
- 		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
- 		FBC_IDLE_FORCE_CLEAR_MASK,
- 		FBC_IDLE_FORCE_CLEAR_MASK);
--	dal_write_reg(compressor->ctx, addr, value);
-+	dm_write_reg(compressor->ctx, addr, value);
- }
- 
- bool dce110_compressor_construct(struct dce110_compressor *compressor,
-@@ -866,7 +866,7 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx,
- 	struct adapter_service *as)
- {
- 	struct dce110_compressor *cp110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_compressor));
-+		dm_alloc(ctx, sizeof(struct dce110_compressor));
- 
- 	if (!cp110)
- 		return NULL;
-@@ -875,12 +875,12 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx,
- 		return &cp110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, cp110);
-+	dm_free(ctx, cp110);
- 	return NULL;
- }
- 
- void dce110_compressor_destroy(struct compressor **compressor)
- {
--	dc_service_free((*compressor)->ctx, TO_DCE110_COMPRESSOR(*compressor));
-+	dm_free((*compressor)->ctx, TO_DCE110_COMPRESSOR(*compressor));
- 	*compressor = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index e1ed527..89d5c65 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -22,14 +22,14 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dc.h"
- #include "dc_bios_types.h"
- #include "core_types.h"
- #include "core_status.h"
- #include "resource.h"
- #include "hw_sequencer.h"
--#include "dc_helpers.h"
-+#include "dm_helpers.h"
- #include "dce110_hw_sequencer.h"
- 
- #include "gpu/dce110/dc_clock_gating_dce110.h"
-@@ -109,7 +109,7 @@ static void dce110_enable_fe_clock(
- 	/*TODO: proper offset*/
- 	addr = HW_REG_DCFE(mmDCFE_CLOCK_CONTROL, controller_id);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -117,7 +117,7 @@ static void dce110_enable_fe_clock(
- 		DCFE_CLOCK_CONTROL,
- 		DCFE_CLOCK_ENABLE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void dce110_init_pte(struct dc_context *ctx)
-@@ -128,7 +128,7 @@ static void dce110_init_pte(struct dc_context *ctx)
- 	uint32_t chunk_mul = 0;
- 
- 	addr = mmUNP_DVMM_PTE_CONTROL;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -148,10 +148,10 @@ static void dce110_init_pte(struct dc_context *ctx)
- 		DVMM_PTE_CONTROL,
- 		DVMM_PTE_BUFFER_MODE1);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = mmDVMM_PTE_REQ;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	chunk_int = get_reg_field_value(
- 		value,
-@@ -183,7 +183,7 @@ static void dce110_init_pte(struct dc_context *ctx)
- 			DVMM_PTE_REQ,
- 			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- }
- 
-@@ -196,8 +196,8 @@ static void trigger_write_crtc_h_blank_start_end(
- 	uint32_t addr;
- 
- 	addr =  HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id);
--	value = dal_read_reg(ctx, addr);
--	dal_write_reg(ctx, addr, value);
-+	value = dm_read_reg(ctx, addr);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static bool dce110_pipe_control_lock(
-@@ -207,7 +207,7 @@ static bool dce110_pipe_control_lock(
- 	bool lock)
- {
- 	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 	bool need_to_wait = false;
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-@@ -247,7 +247,7 @@ static bool dce110_pipe_control_lock(
- 			BLND_V_UPDATE_LOCK,
- 			BLND_V_UPDATE_LOCK_MODE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	if (!lock && need_to_wait) {
- 		uint8_t counter = 0;
-@@ -260,7 +260,7 @@ static bool dce110_pipe_control_lock(
- 				controller_idx);
- 
- 		while (counter < counter_limit) {
--			value = dal_read_reg(ctx, addr);
-+			value = dm_read_reg(ctx, addr);
- 
- 			pipe_pending = 0;
- 
-@@ -315,7 +315,7 @@ static bool dce110_pipe_control_lock(
- 				break;
- 
- 			counter++;
--			dc_service_delay_in_microseconds(ctx, delay_us);
-+			dm_delay_in_microseconds(ctx, delay_us);
- 		}
- 
- 		if (counter == counter_limit) {
-@@ -371,7 +371,7 @@ static void dce110_set_blender_mode(
- 		break;
- 	}
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -385,7 +385,7 @@ static void dce110_set_blender_mode(
- 		BLND_CONTROL,
- 		BLND_MODE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void dce110_crtc_switch_to_clk_src(
-@@ -397,7 +397,7 @@ static void dce110_crtc_switch_to_clk_src(
- 	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
- 			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
- 
--	pixel_rate_cntl_value = dal_read_reg(clk_src->ctx, addr);
-+	pixel_rate_cntl_value = dm_read_reg(clk_src->ctx, addr);
- 
- 	if (clk_src->id == CLOCK_SOURCE_ID_EXTERNAL)
- 		set_reg_field_value(pixel_rate_cntl_value, 1,
-@@ -413,7 +413,7 @@ static void dce110_crtc_switch_to_clk_src(
- 				CRTC0_PIXEL_RATE_CNTL,
- 				CRTC0_PIXEL_RATE_SOURCE);
- 	}
--	dal_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-+	dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
- }
- /**************************************************************************/
- 
-@@ -897,7 +897,7 @@ static void power_down_clock_sources(struct dc *dc)
- 	for (i = 0; i < dc->res_pool.clk_src_count; i++) {
- 		if (dc->res_pool.clock_sources[i]->funcs->cs_power_down(
- 				dc->res_pool.clock_sources[i]) == false)
--			dal_error("Failed to power down pll! (clk src index=%d)\n", i);
-+			dm_error("Failed to power down pll! (clk src index=%d)\n", i);
- 	}
- }
- 
-@@ -1011,7 +1011,7 @@ static bool dc_pre_clock_change(
- 	}
- 
- 	if (!dc_service_pp_pre_dce_clock_change(ctx, &input, output)) {
--		dal_error("DC: dc_service_pp_pre_dce_clock_change failed!\n");
-+		dm_error("DC: dc_service_pp_pre_dce_clock_change failed!\n");
- 		return false;
- 	}
- 
-@@ -1051,7 +1051,7 @@ static bool dc_set_clocks_and_clock_state (
- 	if (!dal_display_clock_set_min_clocks_state(
- 			disp_clk, context->res_ctx.required_clocks_state)) {
- 		BREAK_TO_DEBUGGER();
--		dal_error("DC: failed to set minimum clock state!\n");
-+		dm_error("DC: failed to set minimum clock state!\n");
- 	}
- 
- 
-@@ -1601,7 +1601,7 @@ static void enable_timing_synchronization(
- 
- 	/* Reset slave controllers on master VSync */
- 	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
--	dc_service_memset(&trigger_params, 0, sizeof(trigger_params));
-+	dm_memset(&trigger_params, 0, sizeof(trigger_params));
- 
- 	trigger_params.edge = TRIGGER_EDGE_DEFAULT;
- 	trigger_params.source = SYNC_SOURCE_GSL_GROUP0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-index 6cd80ae..6ab3527 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/logger_interface.h"
- 
- #include "dce/dce_11_0_d.h"
-@@ -60,6 +60,6 @@ bool dce110_ipp_construct(
- 
- void dce110_ipp_destroy(struct input_pixel_processor **ipp)
- {
--	dc_service_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
-+	dm_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
- 	*ipp = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-index 0569fbb..ef91f2d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/logger_interface.h"
- 
- #include "dce/dce_11_0_d.h"
-@@ -137,9 +137,9 @@ static void enable(
- 	uint32_t value = 0;
- 	uint32_t addr = DCP_REG(mmCUR_CONTROL);
- 
--	value = dal_read_reg(ipp110->base.ctx, addr);
-+	value = dm_read_reg(ipp110->base.ctx, addr);
- 	set_reg_field_value(value, enable, CUR_CONTROL, CURSOR_EN);
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- static void lock(
-@@ -148,9 +148,9 @@ static void lock(
- 	uint32_t value = 0;
- 	uint32_t addr = DCP_REG(mmCUR_UPDATE);
- 
--	value = dal_read_reg(ipp110->base.ctx, addr);
-+	value = dm_read_reg(ipp110->base.ctx, addr);
- 	set_reg_field_value(value, lock, CUR_UPDATE, CURSOR_UPDATE_LOCK);
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- static void program_position(
-@@ -161,10 +161,10 @@ static void program_position(
- 	uint32_t value = 0;
- 	uint32_t addr = DCP_REG(mmCUR_POSITION);
- 
--	value = dal_read_reg(ipp110->base.ctx, addr);
-+	value = dm_read_reg(ipp110->base.ctx, addr);
- 	set_reg_field_value(value, x, CUR_POSITION, CURSOR_X_POSITION);
- 	set_reg_field_value(value, y, CUR_POSITION, CURSOR_Y_POSITION);
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- static bool program_control(
-@@ -199,13 +199,13 @@ static bool program_control(
- 			CUR_CONTROL, CURSOR_2X_MAGNIFY);
- 	set_reg_field_value(value, inverse_transparent_clamping,
- 			CUR_CONTROL, CUR_INV_TRANS_CLAMP);
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 	if (color_format == CURSOR_MODE_MONO) {
- 		addr = DCP_REG(mmCUR_COLOR1);
--		dal_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_BLACK);
-+		dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_BLACK);
- 		addr = DCP_REG(mmCUR_COLOR2);
--		dal_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_WHITE);
-+		dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_WHITE);
- 	}
- 	return true;
- }
-@@ -218,10 +218,10 @@ static void program_hotspot(
- 	uint32_t value = 0;
- 	uint32_t addr = DCP_REG(mmCUR_HOT_SPOT);
- 
--	value = dal_read_reg(ipp110->base.ctx, addr);
-+	value = dm_read_reg(ipp110->base.ctx, addr);
- 	set_reg_field_value(value, x, CUR_HOT_SPOT, CURSOR_HOT_SPOT_X);
- 	set_reg_field_value(value, y, CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y);
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- static void program_size(
-@@ -232,10 +232,10 @@ static void program_size(
- 	uint32_t value = 0;
- 	uint32_t addr = DCP_REG(mmCUR_SIZE);
- 
--	value = dal_read_reg(ipp110->base.ctx, addr);
-+	value = dm_read_reg(ipp110->base.ctx, addr);
- 	set_reg_field_value(value, width, CUR_SIZE, CURSOR_WIDTH);
- 	set_reg_field_value(value, height, CUR_SIZE, CURSOR_HEIGHT);
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- static void program_address(
-@@ -248,9 +248,9 @@ static void program_address(
- 	 * The correct way to program cursor surface address is to first write
- 	 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS */
- 
--	dal_write_reg(ipp110->base.ctx, addr, address.high_part);
-+	dm_write_reg(ipp110->base.ctx, addr, address.high_part);
- 
- 	addr = DCP_REG(mmCUR_SURFACE_ADDRESS);
--	dal_write_reg(ipp110->base.ctx, addr, address.low_part);
-+	dm_write_reg(ipp110->base.ctx, addr, address.low_part);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index a30c0da..fcf65f1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/logger_interface.h"
- #include "include/fixed31_32.h"
- #include "basics/conversion.h"
-@@ -200,7 +200,7 @@ static void set_lut_inc(
- {
- 	const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL);
- 
--	uint32_t value = dal_read_reg(ipp110->base.ctx, addr);
-+	uint32_t value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -256,7 +256,7 @@ static void set_lut_inc(
- 		DC_LUT_CONTROL,
- 		DC_LUT_DATA_B_SIGNED_EN);
- 
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- void dce110_helper_select_lut(struct dce110_ipp *ipp110)
-@@ -268,7 +268,7 @@ void dce110_helper_select_lut(struct dce110_ipp *ipp110)
- 	{
- 		const uint32_t addr = DCP_REG(mmDC_LUT_WRITE_EN_MASK);
- 
--		value = dal_read_reg(ipp110->base.ctx, addr);
-+		value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 		/* enable all */
- 		set_reg_field_value(
-@@ -277,13 +277,13 @@ void dce110_helper_select_lut(struct dce110_ipp *ipp110)
- 			DC_LUT_WRITE_EN_MASK,
- 			DC_LUT_WRITE_EN_MASK);
- 
--		dal_write_reg(ipp110->base.ctx, addr, value);
-+		dm_write_reg(ipp110->base.ctx, addr, value);
- 	}
- 
- 	{
- 		const uint32_t addr = DCP_REG(mmDC_LUT_RW_MODE);
- 
--		value = dal_read_reg(ipp110->base.ctx, addr);
-+		value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -291,13 +291,13 @@ void dce110_helper_select_lut(struct dce110_ipp *ipp110)
- 			DC_LUT_RW_MODE,
- 			DC_LUT_RW_MODE);
- 
--		dal_write_reg(ipp110->base.ctx, addr, value);
-+		dm_write_reg(ipp110->base.ctx, addr, value);
- 	}
- 
- 	{
- 		const uint32_t addr = DCP_REG(mmDC_LUT_CONTROL);
- 
--		value = dal_read_reg(ipp110->base.ctx, addr);
-+		value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 		/* 00 - new u0.12 */
- 		set_reg_field_value(
-@@ -318,13 +318,13 @@ void dce110_helper_select_lut(struct dce110_ipp *ipp110)
- 			DC_LUT_CONTROL,
- 			DC_LUT_DATA_B_FORMAT);
- 
--		dal_write_reg(ipp110->base.ctx, addr, value);
-+		dm_write_reg(ipp110->base.ctx, addr, value);
- 	}
- 
- 	{
- 		const uint32_t addr = DCP_REG(mmDC_LUT_RW_INDEX);
- 
--		value = dal_read_reg(ipp110->base.ctx, addr);
-+		value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -332,7 +332,7 @@ void dce110_helper_select_lut(struct dce110_ipp *ipp110)
- 			DC_LUT_RW_INDEX,
- 			DC_LUT_RW_INDEX);
- 
--		dal_write_reg(ipp110->base.ctx, addr, value);
-+		dm_write_reg(ipp110->base.ctx, addr, value);
- 	}
- }
- 
-@@ -340,13 +340,13 @@ static void program_black_offsets(
- 	struct dce110_ipp *ipp110,
- 	struct dev_c_lut16 *offset)
- {
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		DCP_REG(mmDC_LUT_BLACK_OFFSET_RED),
- 		offset->red);
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		DCP_REG(mmDC_LUT_BLACK_OFFSET_GREEN),
- 		offset->green);
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		DCP_REG(mmDC_LUT_BLACK_OFFSET_BLUE),
- 		offset->blue);
- }
-@@ -355,13 +355,13 @@ static void program_white_offsets(
- 	struct dce110_ipp *ipp110,
- 	struct dev_c_lut16 *offset)
- {
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		DCP_REG(mmDC_LUT_WHITE_OFFSET_RED),
- 		offset->red);
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		DCP_REG(mmDC_LUT_WHITE_OFFSET_GREEN),
- 		offset->green);
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		DCP_REG(mmDC_LUT_WHITE_OFFSET_BLUE),
- 		offset->blue);
- }
-@@ -441,7 +441,7 @@ static void program_lut_gamma(
- 		uint8_t counter = 0;
- 
- 		/* Power on LUT memory */
--		value = dal_read_reg(
-+		value = dm_read_reg(
- 				ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
- 
- 		set_reg_field_value(
-@@ -450,12 +450,12 @@ static void program_lut_gamma(
- 			DCFE_MEM_PWR_CTRL,
- 			DCP_REGAMMA_MEM_PWR_DIS);
- 
--		dal_write_reg(
-+		dm_write_reg(
- 			ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
- 
- 		while (counter < max_tries) {
- 			value =
--				dal_read_reg(
-+				dm_read_reg(
- 					ipp110->base.ctx,
- 					DCP_REG(mmDCFE_MEM_PWR_STATUS));
- 
-@@ -493,7 +493,7 @@ static void program_lut_gamma(
- 				gamma[index->red].red,
- 				DC_LUT_SEQ_COLOR,
- 				DC_LUT_SEQ_COLOR);
--			dal_write_reg(ipp110->base.ctx, addr, value);
-+			dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 
- 			set_reg_field_value(
-@@ -501,7 +501,7 @@ static void program_lut_gamma(
- 				gamma[index->green].green,
- 				DC_LUT_SEQ_COLOR,
- 				DC_LUT_SEQ_COLOR);
--			dal_write_reg(ipp110->base.ctx, addr, value);
-+			dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 
- 			set_reg_field_value(
-@@ -509,7 +509,7 @@ static void program_lut_gamma(
- 				gamma[index->blue].blue,
- 				DC_LUT_SEQ_COLOR,
- 				DC_LUT_SEQ_COLOR);
--			dal_write_reg(ipp110->base.ctx, addr, value);
-+			dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 			++i;
- 		} while (i != RGB_256X3X16);
-@@ -522,7 +522,7 @@ static void program_lut_gamma(
- 				gamma[i].red,
- 				DC_LUT_SEQ_COLOR,
- 				DC_LUT_SEQ_COLOR);
--			dal_write_reg(ipp110->base.ctx, addr, value);
-+			dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 
- 			set_reg_field_value(
-@@ -530,7 +530,7 @@ static void program_lut_gamma(
- 				gamma[i].green,
- 				DC_LUT_SEQ_COLOR,
- 				DC_LUT_SEQ_COLOR);
--			dal_write_reg(ipp110->base.ctx, addr, value);
-+			dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 
- 			set_reg_field_value(
-@@ -538,14 +538,14 @@ static void program_lut_gamma(
- 				gamma[i].blue,
- 				DC_LUT_SEQ_COLOR,
- 				DC_LUT_SEQ_COLOR);
--			dal_write_reg(ipp110->base.ctx, addr, value);
-+			dm_write_reg(ipp110->base.ctx, addr, value);
- 
- 			++i;
- 		} while (i != RGB_256X3X16);
- 	}
- 
- 	/*  we are done with DCP LUT memory; re-enable low power mode */
--	value = dal_read_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
-+	value = dm_read_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
- 
- 	set_reg_field_value(
- 		value,
-@@ -553,7 +553,7 @@ static void program_lut_gamma(
- 		DCFE_MEM_PWR_CTRL,
- 		DCP_REGAMMA_MEM_PWR_DIS);
- 
--	dal_write_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
-+	dm_write_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
- 
- static void program_prescale(
-@@ -574,7 +574,7 @@ static void program_prescale(
- 
- 	const uint32_t addr_control = DCP_REG(mmPRESCALE_GRPH_CONTROL);
- 
--	prescale_control = dal_read_reg(ipp110->base.ctx, addr_control);
-+	prescale_control = dm_read_reg(ipp110->base.ctx, addr_control);
- 
- 	set_reg_field_value(
- 		prescale_control,
-@@ -670,23 +670,23 @@ static void program_prescale(
- 		PRESCALE_VALUES_GRPH_B,
- 		GRPH_PRESCALE_BIAS_B);
- 
--	dal_write_reg(ipp110->base.ctx,
-+	dm_write_reg(ipp110->base.ctx,
- 		addr_control, prescale_control);
- 
- 	{
--		dal_write_reg(ipp110->base.ctx,
-+		dm_write_reg(ipp110->base.ctx,
- 				DCP_REG(mmPRESCALE_VALUES_GRPH_R),
- 				prescale_values_grph_r);
- 	}
- 
- 	{
--		dal_write_reg(ipp110->base.ctx,
-+		dm_write_reg(ipp110->base.ctx,
- 				DCP_REG(mmPRESCALE_VALUES_GRPH_G),
- 				prescale_values_grph_g);
- 	}
- 
- 	{
--		dal_write_reg(ipp110->base.ctx,
-+		dm_write_reg(ipp110->base.ctx,
- 				DCP_REG(mmPRESCALE_VALUES_GRPH_B),
- 				prescale_values_grph_b);
- 	}
-@@ -697,7 +697,7 @@ static void set_legacy_input_gamma_mode(
- 	bool is_legacy)
- {
- 	const uint32_t addr = DCP_REG(mmINPUT_GAMMA_CONTROL);
--	uint32_t value = dal_read_reg(ipp110->base.ctx, addr);
-+	uint32_t value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -705,7 +705,7 @@ static void set_legacy_input_gamma_mode(
- 		INPUT_GAMMA_CONTROL,
- 		GRPH_INPUT_GAMMA_MODE);
- 
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
- static bool set_legacy_input_gamma_ramp_rgb256x3x16(
-@@ -714,7 +714,7 @@ static bool set_legacy_input_gamma_ramp_rgb256x3x16(
- 	const struct gamma_parameters *params)
- {
- 	struct dev_c_lut16 *gamma16 =
--		dc_service_alloc(
-+		dm_alloc(
- 			ipp110->base.ctx,
- 			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
- 
-@@ -729,12 +729,12 @@ static bool set_legacy_input_gamma_ramp_rgb256x3x16(
- 			PIXEL_FORMAT_ARGB2101010_XRBIAS) &&
- 		(params->surface_pixel_format != PIXEL_FORMAT_FP16)) {
- 		program_lut_gamma(ipp110, gamma16, params);
--		dc_service_free(ipp110->base.ctx, gamma16);
-+		dm_free(ipp110->base.ctx, gamma16);
- 		return true;
- 	}
- 
- 	/* TODO process DirectX-specific formats*/
--	dc_service_free(ipp110->base.ctx, gamma16);
-+	dm_free(ipp110->base.ctx, gamma16);
- 	return false;
- }
- 
-@@ -744,7 +744,7 @@ static bool set_legacy_input_gamma_ramp_dxgi1(
- 	const struct gamma_parameters *params)
- {
- 	struct dev_c_lut16 *gamma16 =
--		dc_service_alloc(
-+		dm_alloc(
- 			ipp110->base.ctx,
- 			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
- 
-@@ -759,12 +759,12 @@ static bool set_legacy_input_gamma_ramp_dxgi1(
- 			PIXEL_FORMAT_ARGB2101010_XRBIAS) &&
- 		(params->surface_pixel_format != PIXEL_FORMAT_FP16)) {
- 		program_lut_gamma(ipp110, gamma16, params);
--		dc_service_free(ipp110->base.ctx, gamma16);
-+		dm_free(ipp110->base.ctx, gamma16);
- 		return true;
- 	}
- 
- 	/* TODO process DirectX-specific formats*/
--	dc_service_free(ipp110->base.ctx, gamma16);
-+	dm_free(ipp110->base.ctx, gamma16);
- 	return false;
- }
- 
-@@ -777,17 +777,17 @@ static bool set_default_gamma(
- 	struct dev_c_lut16 *gamma16 = NULL;
- 	struct gamma_parameters *params = NULL;
- 
--	gamma16 = dc_service_alloc(
-+	gamma16 = dm_alloc(
- 			ipp110->base.ctx,
- 			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
- 
- 	if (!gamma16)
- 		return false;
- 
--	params = dc_service_alloc(ipp110->base.ctx, sizeof(*params));
-+	params = dm_alloc(ipp110->base.ctx, sizeof(*params));
- 
- 	if (!params) {
--		dc_service_free(ipp110->base.ctx, gamma16);
-+		dm_free(ipp110->base.ctx, gamma16);
- 		return false;
- 	}
- 
-@@ -819,8 +819,8 @@ static bool set_default_gamma(
- 
- 	program_lut_gamma(ipp110, gamma16, params);
- 
--	dc_service_free(ipp110->base.ctx, gamma16);
--	dc_service_free(ipp110->base.ctx, params);
-+	dm_free(ipp110->base.ctx, gamma16);
-+	dm_free(ipp110->base.ctx, params);
- 
- 	return true;
- }
-@@ -836,7 +836,7 @@ static void set_degamma(
- 		params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB == 1 ?
- 			1 : 2;
- 
--	value = dal_read_reg(ipp110->base.ctx, addr);
-+	value = dm_read_reg(ipp110->base.ctx, addr);
- 
- 	/* if by pass - no degamma
- 	 * when legacy and regamma LUT's we do degamma */
-@@ -867,6 +867,6 @@ static void set_degamma(
- 		DEGAMMA_CONTROL,
- 		CURSOR2_DEGAMMA_MODE);
- 
--	dal_write_reg(ipp110->base.ctx, addr, value);
-+	dm_write_reg(ipp110->base.ctx, addr, value);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 2396f15..f714215 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -23,11 +23,12 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "core_types.h"
- #include "link_encoder.h"
- #include "stream_encoder.h"
- #include "dce110_link_encoder.h"
-+
- #include "i2caux_interface.h"
- #include "dc_bios_types.h"
- 
-@@ -130,11 +131,11 @@ static void enable_phy_bypass_mode(
- 
- 	const uint32_t addr = LINK_REG(DP_DPHY_CNTL);
- 
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, enable, DP_DPHY_CNTL, DPHY_BYPASS);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void disable_prbs_symbols(
-@@ -147,7 +148,7 @@ static void disable_prbs_symbols(
- 
- 	const uint32_t addr = LINK_REG(DP_DPHY_CNTL);
- 
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, disable,
- 			DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0);
-@@ -161,7 +162,7 @@ static void disable_prbs_symbols(
- 	set_reg_field_value(value, disable,
- 			DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void disable_prbs_mode(
-@@ -174,11 +175,11 @@ static void disable_prbs_mode(
- 	const uint32_t addr = LINK_REG(DP_DPHY_PRBS_CNTL);
- 	uint32_t value;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0, DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void program_pattern_symbols(
-@@ -201,7 +202,7 @@ static void program_pattern_symbols(
- 			DP_DPHY_SYM0, DPHY_SYM2);
- 	set_reg_field_value(value, pattern_symbols[2],
- 			DP_DPHY_SYM0, DPHY_SYM3);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
-@@ -215,7 +216,7 @@ static void program_pattern_symbols(
- 			DP_DPHY_SYM1, DPHY_SYM5);
- 	set_reg_field_value(value, pattern_symbols[5],
- 			DP_DPHY_SYM1, DPHY_SYM6);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* This register resides in DP back end block;
- 	 * transmitter is used for the offset */
-@@ -226,7 +227,7 @@ static void program_pattern_symbols(
- 	set_reg_field_value(value, pattern_symbols[6],
- 			DP_DPHY_SYM2, DPHY_SYM8);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void set_dp_phy_pattern_d102(
-@@ -270,12 +271,12 @@ static void set_link_training_complete(
- 	 * transmitter is used for the offset */
- 	struct dc_context *ctx = enc110->base.ctx;
- 	const uint32_t addr = LINK_REG(DP_LINK_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, complete,
- 			DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void set_dp_phy_pattern_training_pattern(
-@@ -286,7 +287,7 @@ static void set_dp_phy_pattern_training_pattern(
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = LINK_REG(DP_DPHY_TRAINING_PATTERN_SEL);
- 
--	dal_write_reg(ctx, addr, index);
-+	dm_write_reg(ctx, addr, index);
- 
- 	/* Set HW Register Training Complete to false */
- 
-@@ -314,7 +315,7 @@ static void set_dp_phy_pattern_symbol_error(
- 	{
- 		const uint32_t addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 		uint32_t value = 0x0;
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* A PRBS23 pattern is used for most DP electrical measurements. */
-@@ -326,13 +327,13 @@ static void set_dp_phy_pattern_symbol_error(
- 	/* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
- 	{
- 		const uint32_t addr = LINK_REG(DP_DPHY_PRBS_CNTL);
--		uint32_t value = dal_read_reg(ctx, addr);
-+		uint32_t value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(value, 1,
- 				DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL);
- 		set_reg_field_value(value, 1,
- 				DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* Enable phy bypass mode to enable the test pattern */
-@@ -358,7 +359,7 @@ static void set_dp_phy_pattern_prbs7(
- 	{
- 		const uint32_t addr = LINK_REG(DP_DPHY_PRBS_CNTL);
- 
--		uint32_t value = dal_read_reg(ctx, addr);
-+		uint32_t value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(value, 0,
- 				DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL);
-@@ -366,7 +367,7 @@ static void set_dp_phy_pattern_prbs7(
- 		set_reg_field_value(value, 1,
- 				DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* Enable phy bypass mode to enable the test pattern */
-@@ -446,7 +447,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	{
- 		const uint32_t addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 		uint32_t value = 0x0;
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* no vbid after BS (SR)
-@@ -462,7 +463,7 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	/* TODO: do we still need this, find out at compliance test
- 	addr = mmDP_LINK_FRAMING_CNTL + fe_addr_offset;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = (ctx, addr);
- 
- 	set_reg_field_value(value, 0xFC,
- 			DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL);
-@@ -483,11 +484,11 @@ static void set_dp_phy_pattern_hbr2_compliance(
- 	/* do not enable video stream */
- 	addr = LINK_REG(DP_VID_STREAM_CNTL);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* Disable PHY Bypass mode to setup the test pattern */
- 
-@@ -506,7 +507,7 @@ static void set_dp_phy_pattern_passthrough_mode(
- 
- 		uint32_t value;
- 
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		switch (panel_mode) {
- 		case DP_PANEL_MODE_EDP:
-@@ -520,7 +521,7 @@ static void set_dp_phy_pattern_passthrough_mode(
- 			break;
- 		}
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* set link training complete */
-@@ -570,10 +571,10 @@ static void configure_encoder(
- 
- 	/* set number of lanes */
- 	addr = LINK_REG(DP_CONFIG);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
- 			DP_CONFIG, DP_UDI_LANES);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- }
- 
-@@ -583,7 +584,7 @@ static bool is_panel_powered_on(struct dce110_link_encoder *enc110)
- 	uint32_t value;
- 	bool ret;
- 
--	value = dal_read_reg(ctx,
-+	value = dm_read_reg(ctx,
- 			BL_REG(LVTMA_PWRSEQ_STATE));
- 
- 	ret = get_reg_field_value(value,
-@@ -647,7 +648,7 @@ static void link_encoder_edp_wait_for_hpd_ready(
- 			break;
- 		}
- 
--		dc_service_sleep_in_milliseconds(ctx, HPD_CHECK_INTERVAL);
-+		dm_sleep_in_milliseconds(ctx, HPD_CHECK_INTERVAL);
- 
- 		time_elapsed += HPD_CHECK_INTERVAL;
- 	} while (time_elapsed < timeout);
-@@ -730,19 +731,19 @@ static void aux_initialize(
- 	struct dc_context *ctx = enc110->base.ctx;
- 	enum hpd_source_id hpd_source = enc110->base.hpd_source;
- 	uint32_t addr = AUX_REG(AUX_CONTROL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
- 	set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	/* 1/4 window (the maximum allowed) */
- 	set_reg_field_value(value, 1,
- 			AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- }
- 
-@@ -752,7 +753,7 @@ static bool is_panel_backlight_on(struct dce110_link_encoder *enc110)
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 
--	value = dal_read_reg(ctx, BL_REG(LVTMA_PWRSEQ_CNTL));
-+	value = dm_read_reg(ctx, BL_REG(LVTMA_PWRSEQ_CNTL));
- 
- 	return get_reg_field_value(value, LVTMA_PWRSEQ_CNTL, LVTMA_BLON);
- }
-@@ -831,7 +832,7 @@ static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t value;
- 
--	value = dal_read_reg(ctx, LINK_REG(DIG_BE_EN_CNTL));
-+	value = dm_read_reg(ctx, LINK_REG(DIG_BE_EN_CNTL));
- 
- 	return get_reg_field_value(value, DIG_BE_EN_CNTL, DIG_ENABLE);
- }
-@@ -844,22 +845,22 @@ static void link_encoder_disable(struct dce110_link_encoder *enc110)
- 
- 	/* reset training pattern */
- 	addr = LINK_REG(DP_DPHY_TRAINING_PATTERN_SEL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0,
- 			DP_DPHY_TRAINING_PATTERN_SEL,
- 			DPHY_TRAINING_PATTERN_SEL);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* reset training complete */
- 	addr = LINK_REG(DP_LINK_CNTL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* reset panel mode */
- 	addr = LINK_REG(DP_DPHY_INTERNAL_CTRL);
- 	value = 0;
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void hpd_initialize(
-@@ -869,10 +870,10 @@ static void hpd_initialize(
- 	struct dc_context *ctx = enc110->base.ctx;
- 	enum hpd_source_id hpd_source = enc110->base.hpd_source;
- 	const uint32_t addr = LINK_REG(DIG_BE_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, hpd_source, DIG_BE_CNTL, DIG_HPD_SELECT);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static bool validate_dvi_output(
-@@ -1265,7 +1266,7 @@ void dce110_link_encoder_setup(
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	const uint32_t addr = LINK_REG(DIG_BE_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	switch (signal) {
- 	case SIGNAL_TYPE_EDP:
-@@ -1296,7 +1297,7 @@ void dce110_link_encoder_setup(
- 		break;
- 	}
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- /* TODO: still need depth or just pass in adjusted pixel clock? */
-@@ -1629,8 +1630,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * to commit payload on both tx and rx side */
- 
- 	/* we should clean-up table each time */
--	value0 = dal_read_reg(ctx, LINK_REG(DP_MSE_SAT0));
--	value1 = dal_read_reg(ctx, LINK_REG(DP_MSE_SAT1));
-+	value0 = dm_read_reg(ctx, LINK_REG(DP_MSE_SAT0));
-+	value1 = dm_read_reg(ctx, LINK_REG(DP_MSE_SAT1));
- 
- 	if (table->stream_count >= 1) {
- 		fill_stream_allocation_row_info(
-@@ -1699,8 +1700,8 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_SLOT_COUNT2);
- 
- 	/* update ASIC MSE stream allocation table */
--	dal_write_reg(ctx, LINK_REG(DP_MSE_SAT0), value0);
--	dal_write_reg(ctx, LINK_REG(DP_MSE_SAT1), value1);
-+	dm_write_reg(ctx, LINK_REG(DP_MSE_SAT0), value0);
-+	dm_write_reg(ctx, LINK_REG(DP_MSE_SAT1), value1);
- 
- 	/* --- wait for transaction finish */
- 
-@@ -1709,7 +1710,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * then double buffers the SAT into the hardware
- 	 * making the new allocation active on the DP MST mode link */
- 
--	value0 = dal_read_reg(ctx, LINK_REG(DP_MSE_SAT_UPDATE));
-+	value0 = dm_read_reg(ctx, LINK_REG(DP_MSE_SAT_UPDATE));
- 
- 	/* DP_MSE_SAT_UPDATE:
- 	 * 0 - No Action
-@@ -1722,7 +1723,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 		DP_MSE_SAT_UPDATE,
- 		DP_MSE_SAT_UPDATE);
- 
--	dal_write_reg(ctx, LINK_REG(DP_MSE_SAT_UPDATE), value0);
-+	dm_write_reg(ctx, LINK_REG(DP_MSE_SAT_UPDATE), value0);
- 
- 	/* wait for update to complete
- 	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
-@@ -1735,9 +1736,9 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * after this bit is cleared */
- 
- 	do {
--		dc_service_delay_in_microseconds(ctx, 10);
-+		dm_delay_in_microseconds(ctx, 10);
- 
--		value0 = dal_read_reg(ctx,
-+		value0 = dm_read_reg(ctx,
- 				LINK_REG(DP_MSE_SAT_UPDATE));
- 
- 		value1 = get_reg_field_value(
-@@ -1779,9 +1780,9 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 	uint8_t bit_count;
- 	uint64_t active_duty_cycle;
- 
--	backlight = dal_read_reg(ctx, BL_REG(BL_PWM_CNTL));
--	backlight_period = dal_read_reg(ctx, BL_REG(BL_PWM_PERIOD_CNTL));
--	backlight_lock = dal_read_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK));
-+	backlight = dm_read_reg(ctx, BL_REG(BL_PWM_CNTL));
-+	backlight_period = dm_read_reg(ctx, BL_REG(BL_PWM_PERIOD_CNTL));
-+	backlight_lock = dm_read_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK));
- 
- 	/*
- 	 * 1. Convert 8-bit value to 17 bit U1.16 format
-@@ -1864,10 +1865,10 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 		1,
- 		BL_PWM_GRP1_REG_LOCK,
- 		BL_PWM_GRP1_REG_LOCK);
--	dal_write_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK), backlight_lock);
-+	dm_write_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK), backlight_lock);
- 
- 	/* 3.2 Write new active duty cycle */
--	dal_write_reg(ctx, BL_REG(BL_PWM_CNTL), backlight);
-+	dm_write_reg(ctx, BL_REG(BL_PWM_CNTL), backlight);
- 
- 	/* 3.3 Unlock group 2 backlight registers */
- 	set_reg_field_value(
-@@ -1875,18 +1876,18 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 		0,
- 		BL_PWM_GRP1_REG_LOCK,
- 		BL_PWM_GRP1_REG_LOCK);
--	dal_write_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK), backlight_lock);
-+	dm_write_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK), backlight_lock);
- 
- 	/* 5.4.4 Wait for pending bit to be cleared */
- 	for (i = 0; i < backlight_update_pending_max_retry; ++i) {
--		backlight_lock = dal_read_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK));
-+		backlight_lock = dm_read_reg(ctx, BL_REG(BL_PWM_GRP1_REG_LOCK));
- 		if (!get_reg_field_value(
- 			backlight_lock,
- 			BL_PWM_GRP1_REG_LOCK,
- 			BL_PWM_GRP1_REG_UPDATE_PENDING))
- 			break;
- 
--		dc_service_delay_in_microseconds(ctx, 10);
-+		dm_delay_in_microseconds(ctx, 10);
- 	}
- }
- 
-@@ -1903,7 +1904,7 @@ void dce110_link_encoder_connect_dig_be_to_fe(
- 
- 	if (engine != ENGINE_ID_UNKNOWN) {
- 		addr = LINK_REG(DIG_BE_CNTL);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		field = get_reg_field_value(
- 				value,
-@@ -1920,7 +1921,7 @@ void dce110_link_encoder_connect_dig_be_to_fe(
- 			field,
- 			DIG_BE_CNTL,
- 			DIG_FE_SOURCE_SELECT);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 5d3d0f7..3a928e6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -49,7 +49,7 @@ static void set_flip_control(
- {
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(
-+	value = dm_read_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_FLIP_CONTROL));
- 	set_reg_field_value(value, 0,
-@@ -63,7 +63,7 @@ static void set_flip_control(
- 			GRPH_FLIP_CONTROL,
- 			GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_FLIP_CONTROL),
- 		value);
-@@ -83,7 +83,7 @@ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
- 		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
- 		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH),
- 			value);
-@@ -97,7 +97,7 @@ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
- 		GRPH_SECONDARY_SURFACE_ADDRESS,
- 		GRPH_SECONDARY_SURFACE_ADDRESS);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS),
- 			value);
-@@ -118,7 +118,7 @@ GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
- 		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- 		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH),
- 		value);
-@@ -132,7 +132,7 @@ GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
- 		GRPH_PRIMARY_SURFACE_ADDRESS,
- 		GRPH_PRIMARY_SURFACE_ADDRESS);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS),
- 		value);
-@@ -167,9 +167,9 @@ static void enable(struct dce110_mem_input *mem_input110)
- {
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_ENABLE));
-+	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_ENABLE));
- 	set_reg_field_value(value, 1, GRPH_ENABLE, GRPH_ENABLE);
--	dal_write_reg(mem_input110->base.ctx,
-+	dm_write_reg(mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_ENABLE),
- 		value);
- }
-@@ -181,7 +181,7 @@ static void program_tiling(
- {
- 	uint32_t value = 0;
- 
--	value = dal_read_reg(
-+	value = dm_read_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_CONTROL));
- 
-@@ -215,7 +215,7 @@ static void program_tiling(
- 	set_reg_field_value(value, 0,
- 		GRPH_CONTROL, GRPH_Z);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_CONTROL),
- 		value);
-@@ -247,7 +247,7 @@ static void program_size_and_rotation(
- 
- 	set_reg_field_value(value, local_size.grph.surface_size.x,
- 			GRPH_X_START, GRPH_X_START);
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_X_START),
- 		value);
-@@ -255,7 +255,7 @@ static void program_size_and_rotation(
- 	value = 0;
- 	set_reg_field_value(value, local_size.grph.surface_size.y,
- 			GRPH_Y_START, GRPH_Y_START);
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_Y_START),
- 		value);
-@@ -263,7 +263,7 @@ static void program_size_and_rotation(
- 	value = 0;
- 	set_reg_field_value(value, local_size.grph.surface_size.width,
- 			GRPH_X_END, GRPH_X_END);
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_X_END),
- 		value);
-@@ -271,7 +271,7 @@ static void program_size_and_rotation(
- 	value = 0;
- 	set_reg_field_value(value, local_size.grph.surface_size.height,
- 			GRPH_Y_END, GRPH_Y_END);
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_Y_END),
- 		value);
-@@ -279,7 +279,7 @@ static void program_size_and_rotation(
- 	value = 0;
- 	set_reg_field_value(value, local_size.grph.surface_pitch,
- 			GRPH_PITCH, GRPH_PITCH);
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmGRPH_PITCH),
- 		value);
-@@ -304,7 +304,7 @@ static void program_size_and_rotation(
- 			HW_ROTATION, GRPH_ROTATION_ANGLE);
- 		break;
- 	}
--	dal_write_reg(
-+	dm_write_reg(
- 		mem_input110->base.ctx,
- 		DCP_REG(mmHW_ROTATION),
- 		value);
-@@ -330,13 +330,13 @@ static void program_pixel_format(
- 				value, 2, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR);
- 		}
- 
--		dal_write_reg(
-+		dm_write_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_SWAP_CNTL),
- 			value);
- 
- 
--		value =	dal_read_reg(
-+		value =	dm_read_reg(
- 				mem_input110->base.ctx,
- 				DCP_REG(mmGRPH_CONTROL));
- 
-@@ -378,13 +378,13 @@ static void program_pixel_format(
- 		default:
- 			break;
- 		}
--		dal_write_reg(
-+		dm_write_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmGRPH_CONTROL),
- 			value);
- 
- 		/*TODO [hwentlan] MOVE THIS TO CONTROLLER GAMMA!!!!!*/
--		value = dal_read_reg(
-+		value = dm_read_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmPRESCALE_GRPH_CONTROL));
- 
-@@ -415,7 +415,7 @@ static void program_pixel_format(
- 				value, 0, PRESCALE_GRPH_CONTROL,
- 				GRPH_PRESCALE_B_SIGN);
- 		}
--		dal_write_reg(
-+		dm_write_reg(
- 			mem_input110->base.ctx,
- 			DCP_REG(mmPRESCALE_GRPH_CONTROL),
- 			value);
-@@ -428,7 +428,7 @@ static void wait_for_no_surface_update_pending(
- 	uint32_t value;
- 
- 	do  {
--		value = dal_read_reg(mem_input110->base.ctx,
-+		value = dm_read_reg(mem_input110->base.ctx,
- 				DCP_REG(mmGRPH_UPDATE));
- 
- 	} while (get_reg_field_value(value, GRPH_UPDATE,
-@@ -483,14 +483,14 @@ static void program_urgency_watermark(
- 	uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
- 
- 	/*Write mask to enable reading/writing of watermark set A*/
--	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- 	set_reg_field_value(wm_mask_cntl,
- 			1,
- 			DPG_WATERMARK_MASK_CONTROL,
- 			URGENCY_WATERMARK_MASK);
--	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
- 
--	urgency_cntl = dal_read_reg(ctx, urgency_addr);
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
- 
- 	set_reg_field_value(
- 		urgency_cntl,
-@@ -503,18 +503,18 @@ static void program_urgency_watermark(
- 		total_dest_line_time_ns,
- 		DPG_PIPE_URGENCY_CONTROL,
- 		URGENCY_HIGH_WATERMARK);
--	dal_write_reg(ctx, urgency_addr, urgency_cntl);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
- 
- 
- 	/*Write mask to enable reading/writing of watermark set B*/
--	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- 	set_reg_field_value(wm_mask_cntl,
- 			2,
- 			DPG_WATERMARK_MASK_CONTROL,
- 			URGENCY_WATERMARK_MASK);
--	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
- 
--	urgency_cntl = dal_read_reg(ctx, urgency_addr);
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
- 
- 	set_reg_field_value(urgency_cntl,
- 		marks_low.b_mark,
-@@ -525,7 +525,7 @@ static void program_urgency_watermark(
- 		total_dest_line_time_ns,
- 		DPG_PIPE_URGENCY_CONTROL,
- 		URGENCY_HIGH_WATERMARK);
--	dal_write_reg(ctx, urgency_addr, urgency_cntl);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
- }
- 
- static void program_stutter_watermark(
-@@ -542,14 +542,14 @@ static void program_stutter_watermark(
- 
- 	/*Write mask to enable reading/writing of watermark set A*/
- 
--	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- 	set_reg_field_value(wm_mask_cntl,
- 		1,
- 		DPG_WATERMARK_MASK_CONTROL,
- 		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
--	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
- 
--	stutter_cntl = dal_read_reg(ctx, stutter_addr);
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
- 
- 	set_reg_field_value(stutter_cntl,
- 		1,
-@@ -565,17 +565,17 @@ static void program_stutter_watermark(
- 		marks.a_mark,
- 		DPG_PIPE_STUTTER_CONTROL,
- 		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
--	dal_write_reg(ctx, stutter_addr, stutter_cntl);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
- 
- 	/*Write mask to enable reading/writing of watermark set B*/
--	wm_mask_cntl = dal_read_reg(ctx, wm_addr);
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- 	set_reg_field_value(wm_mask_cntl,
- 		2,
- 		DPG_WATERMARK_MASK_CONTROL,
- 		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
--	dal_write_reg(ctx, wm_addr, wm_mask_cntl);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
- 
--	stutter_cntl = dal_read_reg(ctx, stutter_addr);
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
- 	set_reg_field_value(stutter_cntl,
- 		1,
- 		DPG_PIPE_STUTTER_CONTROL,
-@@ -590,7 +590,7 @@ static void program_stutter_watermark(
- 		marks.b_mark,
- 		DPG_PIPE_STUTTER_CONTROL,
- 		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
--	dal_write_reg(ctx, stutter_addr, stutter_cntl);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
- }
- 
- static void program_nbp_watermark(
-@@ -602,16 +602,16 @@ static void program_nbp_watermark(
- 	uint32_t addr;
- 	/* Write mask to enable reading/writing of watermark set A */
- 	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		DPG_WATERMARK_MASK_CONTROL,
- 		NB_PSTATE_CHANGE_WATERMARK_MASK);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
-@@ -627,29 +627,29 @@ static void program_nbp_watermark(
- 		1,
- 		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- 		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* Write watermark set A */
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		marks.a_mark,
- 		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- 		NB_PSTATE_CHANGE_WATERMARK);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* Write mask to enable reading/writing of watermark set B */
- 	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		2,
- 		DPG_WATERMARK_MASK_CONTROL,
- 		NB_PSTATE_CHANGE_WATERMARK_MASK);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
-@@ -665,16 +665,16 @@ static void program_nbp_watermark(
- 		1,
- 		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- 		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* Write watermark set B */
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		marks.b_mark,
- 		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- 		NB_PSTATE_CHANGE_WATERMARK);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_mem_input_program_safe_display_marks(struct mem_input *mi)
-@@ -779,7 +779,7 @@ void dce110_mem_input_allocate_dmif_buffer(
- 		goto register_underflow_int;
- 
- 	/*Allocate DMIF buffer*/
--	value = dal_read_reg(mi->ctx, addr);
-+	value = dm_read_reg(mi->ctx, addr);
- 	field = get_reg_field_value(
- 		value, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED);
- 	if (field == 2)
-@@ -791,10 +791,10 @@ void dce110_mem_input_allocate_dmif_buffer(
- 			PIPE0_DMIF_BUFFER_CONTROL,
- 			DMIF_BUFFERS_ALLOCATED);
- 
--	dal_write_reg(mi->ctx, addr, value);
-+	dm_write_reg(mi->ctx, addr, value);
- 
- 	do {
--		value = dal_read_reg(mi->ctx, addr);
-+		value = dm_read_reg(mi->ctx, addr);
- 		field = get_reg_field_value(
- 			value,
- 			PIPE0_DMIF_BUFFER_CONTROL,
-@@ -803,7 +803,7 @@ void dce110_mem_input_allocate_dmif_buffer(
- 		if (field)
- 			break;
- 
--		dc_service_delay_in_microseconds(mi->ctx, retry_delay);
-+		dm_delay_in_microseconds(mi->ctx, retry_delay);
- 		retry_count--;
- 
- 	} while (retry_count > 0);
-@@ -818,7 +818,7 @@ void dce110_mem_input_allocate_dmif_buffer(
- 
- 	if (timing->pix_clk_khz != 0) {
- 		addr = mmDPG_PIPE_ARBITRATION_CONTROL1 + bm110->offsets.dmif;
--		value = dal_read_reg(mi->ctx, addr);
-+		value = dm_read_reg(mi->ctx, addr);
- 		pix_dur = 1000000000ULL / timing->pix_clk_khz;
- 
- 		set_reg_field_value(
-@@ -827,7 +827,7 @@ void dce110_mem_input_allocate_dmif_buffer(
- 			DPG_PIPE_ARBITRATION_CONTROL1,
- 			PIXEL_DURATION);
- 
--		dal_write_reg(mi->ctx, addr, value);
-+		dm_write_reg(mi->ctx, addr, value);
- 	}
- 
- 	/*
-@@ -841,13 +841,13 @@ void dce110_mem_input_allocate_dmif_buffer(
- 	 */
- 	if (!IS_FPGA_MAXIMUS_DC(mi->ctx->dce_environment)) {
- 		addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
--		value = dal_read_reg(mi->ctx, addr);
-+		value = dm_read_reg(mi->ctx, addr);
- 
- 		if (paths_num > 1)
- 			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
- 		else
- 			set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
--		dal_write_reg(mi->ctx, addr, value);
-+		dm_write_reg(mi->ctx, addr, value);
- 	}
- 
- register_underflow_int:
-@@ -861,7 +861,7 @@ static void deallocate_dmif_buffer_helper(
- 	uint32_t value;
- 	uint32_t count = 0xBB8; /* max retry count */
- 
--	value = dal_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
-+	value = dm_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
- 
- 	if (!get_reg_field_value(
- 		value, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED))
-@@ -870,12 +870,12 @@ static void deallocate_dmif_buffer_helper(
- 	set_reg_field_value(
- 		value, 0, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset, value);
- 
- 	do {
--		value = dal_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
--		dc_service_delay_in_microseconds(ctx, 10);
-+		value = dm_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
-+		dm_delay_in_microseconds(ctx, 10);
- 		count--;
- 	} while (count > 0 &&
- 		!get_reg_field_value(
-@@ -910,13 +910,13 @@ void dce110_mem_input_deallocate_dmif_buffer(
- 	 * 03 - force enable dmif rdreq limit, ignore dmif stall/urgent
- 	 * Stella Wong proposed this change. */
- 	if (!IS_FPGA_MAXIMUS_DC(mi->ctx->dce_environment)) {
--		value = dal_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
-+		value = dm_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
- 		if (paths_num > 1)
- 			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
- 		else
- 			set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
- 
--		dal_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
-+		dm_write_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT, value);
- 	}
- }
- 
-@@ -960,6 +960,6 @@ bool dce110_mem_input_construct(
- 
- void dce110_mem_input_destroy(struct mem_input **mem_input)
- {
--	dc_service_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
-+	dm_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
- 	*mem_input = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 7dcfd2e..acb405e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -23,13 +23,14 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dce110_opp.h"
-+
- #include "gamma_types.h"
- 
- enum {
-@@ -129,70 +130,70 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
- 	opp110->regamma.divider2 = dal_fixed31_32_from_int(2);
- 	opp110->regamma.divider3 = dal_fixed31_32_from_fraction(5, 2);
- 
--	opp110->regamma.rgb_user = dc_service_alloc(
-+	opp110->regamma.rgb_user = dm_alloc(
- 		ctx,
- 		sizeof(struct pwl_float_data) *
- 		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
- 	if (!opp110->regamma.rgb_user)
- 		goto failure_1;
- 
--	opp110->regamma.rgb_oem = dc_service_alloc(
-+	opp110->regamma.rgb_oem = dm_alloc(
- 		ctx,
- 		sizeof(struct pwl_float_data) *
- 		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
- 	if (!opp110->regamma.rgb_oem)
- 		goto failure_2;
- 
--	opp110->regamma.rgb_resulted = dc_service_alloc(
-+	opp110->regamma.rgb_resulted = dm_alloc(
- 		ctx,
- 		sizeof(struct pwl_result_data) *
- 		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
- 	if (!opp110->regamma.rgb_resulted)
- 		goto failure_3;
- 
--	opp110->regamma.rgb_regamma = dc_service_alloc(
-+	opp110->regamma.rgb_regamma = dm_alloc(
- 		ctx,
- 		sizeof(struct pwl_float_data_ex) *
- 		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
- 	if (!opp110->regamma.rgb_regamma)
- 		goto failure_4;
- 
--	opp110->regamma.coordinates_x = dc_service_alloc(
-+	opp110->regamma.coordinates_x = dm_alloc(
- 		ctx,
- 		sizeof(struct hw_x_point) *
- 		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
- 	if (!opp110->regamma.coordinates_x)
- 		goto failure_5;
- 
--	opp110->regamma.axis_x_256 = dc_service_alloc(
-+	opp110->regamma.axis_x_256 = dm_alloc(
- 		ctx,
- 		sizeof(struct gamma_pixel) *
- 		(MAX_LUT_ENTRY + opp110->regamma.extra_points));
- 	if (!opp110->regamma.axis_x_256)
- 		goto failure_6;
- 
--	opp110->regamma.axis_x_1025 = dc_service_alloc(
-+	opp110->regamma.axis_x_1025 = dm_alloc(
- 		ctx,
- 		sizeof(struct gamma_pixel) *
- 		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
- 	if (!opp110->regamma.axis_x_1025)
- 		goto failure_7;
- 
--	opp110->regamma.coeff128 = dc_service_alloc(
-+	opp110->regamma.coeff128 = dm_alloc(
- 		ctx,
- 		sizeof(struct pixel_gamma_point) *
- 		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
- 	if (!opp110->regamma.coeff128)
- 		goto failure_8;
- 
--	opp110->regamma.coeff128_oem = dc_service_alloc(
-+	opp110->regamma.coeff128_oem = dm_alloc(
- 		ctx,
- 		sizeof(struct pixel_gamma_point) *
- 		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
- 	if (!opp110->regamma.coeff128_oem)
- 		goto failure_9;
- 
--	opp110->regamma.coeff128_dx = dc_service_alloc(
-+	opp110->regamma.coeff128_dx = dm_alloc(
- 		ctx,
- 		sizeof(struct pixel_gamma_point) *
- 		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
-@@ -231,23 +232,23 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
- 	return true;
- 
- failure_10:
--	dc_service_free(ctx, opp110->regamma.coeff128_oem);
-+	dm_free(ctx, opp110->regamma.coeff128_oem);
- failure_9:
--	dc_service_free(ctx, opp110->regamma.coeff128);
-+	dm_free(ctx, opp110->regamma.coeff128);
- failure_8:
--	dc_service_free(ctx, opp110->regamma.axis_x_1025);
-+	dm_free(ctx, opp110->regamma.axis_x_1025);
- failure_7:
--	dc_service_free(ctx, opp110->regamma.axis_x_256);
-+	dm_free(ctx, opp110->regamma.axis_x_256);
- failure_6:
--	dc_service_free(ctx, opp110->regamma.coordinates_x);
-+	dm_free(ctx, opp110->regamma.coordinates_x);
- failure_5:
--	dc_service_free(ctx, opp110->regamma.rgb_regamma);
-+	dm_free(ctx, opp110->regamma.rgb_regamma);
- failure_4:
--	dc_service_free(ctx, opp110->regamma.rgb_resulted);
-+	dm_free(ctx, opp110->regamma.rgb_resulted);
- failure_3:
--	dc_service_free(ctx, opp110->regamma.rgb_oem);
-+	dm_free(ctx, opp110->regamma.rgb_oem);
- failure_2:
--	dc_service_free(ctx, opp110->regamma.rgb_user);
-+	dm_free(ctx, opp110->regamma.rgb_user);
- failure_1:
- 
- 	return true;
-@@ -255,17 +256,17 @@ failure_1:
- 
- void dce110_opp_destroy(struct output_pixel_processor **opp)
- {
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
--	dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
-+	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
- 	*opp = NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-index a96a72a..8f651e9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dce110_opp.h"
- #include "basics/conversion.h"
- 
-@@ -91,7 +91,7 @@ static void program_color_matrix(
- 			OUTPUT_CSC_C11_C12,
- 			OUTPUT_CSC_C12);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		uint32_t value = 0;
-@@ -109,7 +109,7 @@ static void program_color_matrix(
- 			OUTPUT_CSC_C13_C14,
- 			OUTPUT_CSC_C14);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		uint32_t value = 0;
-@@ -127,7 +127,7 @@ static void program_color_matrix(
- 			OUTPUT_CSC_C21_C22,
- 			OUTPUT_CSC_C22);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		uint32_t value = 0;
-@@ -145,7 +145,7 @@ static void program_color_matrix(
- 			OUTPUT_CSC_C23_C24,
- 			OUTPUT_CSC_C24);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		uint32_t value = 0;
-@@ -163,7 +163,7 @@ static void program_color_matrix(
- 			OUTPUT_CSC_C31_C32,
- 			OUTPUT_CSC_C32);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		uint32_t value = 0;
-@@ -181,7 +181,7 @@ static void program_color_matrix(
- 			OUTPUT_CSC_C33_C34,
- 			OUTPUT_CSC_C34);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- }
- 
-@@ -598,7 +598,7 @@ static void set_rgb_limited_range_adjustment(
- 
- 	calculate_adjustments(ideals, &adjustments, matrix);
- 
--	dc_service_memmove(change_matrix, matrix, sizeof(matrix));
-+	dm_memmove(change_matrix, matrix, sizeof(matrix));
- 
- 	/* from 1 -> 3 */
- 	matrix[8] = change_matrix[0];
-@@ -618,7 +618,7 @@ static void set_rgb_limited_range_adjustment(
- 	matrix[6] = change_matrix[10];
- 	matrix[7] = change_matrix[11];
- 
--	dc_service_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-@@ -692,7 +692,7 @@ static void set_yuv_adjustment(
- 		calculate_adjustments(
- 			ideals, &adjustments, matrix);
- 
--	dc_service_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-@@ -707,7 +707,7 @@ static bool configure_graphics_mode(
- {
- 	struct dc_context *ctx = opp110->base.ctx;
- 	uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -816,7 +816,7 @@ static bool configure_graphics_mode(
- 			OUTPUT_CSC_GRPH_MODE);
- 
- 	addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-index 0224ade..235b92e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -47,7 +47,7 @@ static void set_truncation(
- 	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
- 
- 	/*Disable truncation*/
--	value = dal_read_reg(opp110->base.ctx, addr);
-+	value = dm_read_reg(opp110->base.ctx, addr);
- 	set_reg_field_value(value, 0,
- 		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN);
- 	set_reg_field_value(value, 0,
-@@ -55,7 +55,7 @@ static void set_truncation(
- 	set_reg_field_value(value, 0,
- 		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE);
- 
--	dal_write_reg(opp110->base.ctx, addr, value);
-+	dm_write_reg(opp110->base.ctx, addr, value);
- 
- 	/* no 10bpc trunc on DCE11*/
- 	if (params->flags.TRUNCATE_ENABLED == 0 ||
-@@ -70,7 +70,7 @@ static void set_truncation(
- 	set_reg_field_value(value, params->flags.TRUNCATE_DEPTH,
- 		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH);
- 
--	dal_write_reg(opp110->base.ctx, addr, value);
-+	dm_write_reg(opp110->base.ctx, addr, value);
- 
- }
- 
-@@ -101,7 +101,7 @@ static void set_spatial_dither(
- 	uint32_t dither_b_value = 0;
- 
- 	/*Disable spatial (random) dithering*/
--	depth_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+	depth_cntl_value = dm_read_reg(opp110->base.ctx, addr);
- 	set_reg_field_value(depth_cntl_value, 0,
- 		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN);
- 	set_reg_field_value(depth_cntl_value, 0,
-@@ -117,7 +117,7 @@ static void set_spatial_dither(
- 	set_reg_field_value(depth_cntl_value, 0,
- 		FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE);
- 
--	dal_write_reg(opp110->base.ctx, addr, depth_cntl_value);
-+	dm_write_reg(opp110->base.ctx, addr, depth_cntl_value);
- 
- 	/* no 10bpc on DCE11*/
- 	if (params->flags.SPATIAL_DITHER_ENABLED == 0 ||
-@@ -125,7 +125,7 @@ static void set_spatial_dither(
- 		return;
- 
- 	addr = FMT_REG(mmFMT_CONTROL);
--	fmt_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+	fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr);
- 	/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
- 	if (params->flags.FRAME_RANDOM == 1) {
- 		if (params->flags.SPATIAL_DITHER_DEPTH == 0 ||
-@@ -154,7 +154,7 @@ static void set_spatial_dither(
- 			FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP);
- 	}
- 
--	dal_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
-+	dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
- 
- 	/*Set seed for random values for
- 	 * spatial dithering for R,G,B channels*/
-@@ -162,20 +162,20 @@ static void set_spatial_dither(
- 	set_reg_field_value(dither_r_value, params->r_seed_value,
- 		FMT_DITHER_RAND_R_SEED,
- 		FMT_RAND_R_SEED);
--	dal_write_reg(opp110->base.ctx, addr, dither_r_value);
-+	dm_write_reg(opp110->base.ctx, addr, dither_r_value);
- 
- 	addr = FMT_REG(mmFMT_DITHER_RAND_G_SEED);
- 	set_reg_field_value(dither_g_value,
- 		params->g_seed_value,
- 		FMT_DITHER_RAND_G_SEED,
- 		FMT_RAND_G_SEED);
--	dal_write_reg(opp110->base.ctx, addr, dither_g_value);
-+	dm_write_reg(opp110->base.ctx, addr, dither_g_value);
- 
- 	addr = FMT_REG(mmFMT_DITHER_RAND_B_SEED);
- 	set_reg_field_value(dither_b_value, params->b_seed_value,
- 		FMT_DITHER_RAND_B_SEED,
- 		FMT_RAND_B_SEED);
--	dal_write_reg(opp110->base.ctx, addr, dither_b_value);
-+	dm_write_reg(opp110->base.ctx, addr, dither_b_value);
- 
- 	/* FMT_OFFSET_R_Cr  31:16 0x0 Setting the zero
- 	 * offset for the R/Cr channel, lower 4LSB
-@@ -232,7 +232,7 @@ static void set_spatial_dither(
- 		FMT_SPATIAL_DITHER_EN);
- 
- 	addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
--	dal_write_reg(opp110->base.ctx, addr, depth_cntl_value);
-+	dm_write_reg(opp110->base.ctx, addr, depth_cntl_value);
- 
- }
- 
-@@ -254,7 +254,7 @@ static void set_temporal_dither(
- 	uint32_t value;
- 
- 	/*Disable temporal (frame modulation) dithering first*/
--	value = dal_read_reg(opp110->base.ctx, addr);
-+	value = dm_read_reg(opp110->base.ctx, addr);
- 
- 	set_reg_field_value(value,
- 		0,
-@@ -292,7 +292,7 @@ static void set_temporal_dither(
- 		FMT_BIT_DEPTH_CONTROL,
- 		FMT_75FRC_SEL);
- 
--	dal_write_reg(opp110->base.ctx, addr, value);
-+	dm_write_reg(opp110->base.ctx, addr, value);
- 
- 	/* no 10bpc dither on DCE11*/
- 	if (params->flags.FRAME_MODULATION_ENABLED == 0 ||
-@@ -317,15 +317,15 @@ static void set_temporal_dither(
- 
- 	/*Select legacy pattern based on FRC and Temporal level*/
- 	addr = FMT_REG(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL);
--	dal_write_reg(opp110->base.ctx, addr, 0);
-+	dm_write_reg(opp110->base.ctx, addr, 0);
- 	/*Set s matrix*/
- 	addr = FMT_REG(
- 		mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX);
--	dal_write_reg(opp110->base.ctx, addr, 0);
-+	dm_write_reg(opp110->base.ctx, addr, 0);
- 	/*Set t matrix*/
- 	addr = FMT_REG(
- 		mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX);
--	dal_write_reg(opp110->base.ctx, addr, 0);
-+	dm_write_reg(opp110->base.ctx, addr, 0);
- 
- 	/*Select patterns for 0.25, 0.5 and 0.75 grey level*/
- 	set_reg_field_value(value,
-@@ -355,7 +355,7 @@ static void set_temporal_dither(
- 		FMT_TEMPORAL_DITHER_EN);
- 
- 	addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
--	dal_write_reg(opp110->base.ctx, addr, value);
-+	dm_write_reg(opp110->base.ctx, addr, value);
- 
- }
- 
-@@ -378,7 +378,7 @@ static void set_clamping(
- 	uint32_t blue_clamp_value = 0;
- 	uint32_t addr = FMT_REG(mmFMT_CLAMP_CNTL);
- 
--	clamp_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+	clamp_cntl_value = dm_read_reg(opp110->base.ctx, addr);
- 
- 	set_reg_field_value(clamp_cntl_value,
- 		0,
-@@ -454,7 +454,7 @@ static void set_clamping(
- 			FMT_CLAMP_UPPER_R);
- 
- 		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_R);
--		dal_write_reg(opp110->base.ctx, addr, red_clamp_value);
-+		dm_write_reg(opp110->base.ctx, addr, red_clamp_value);
- 
- 		set_reg_field_value(green_clamp_value,
- 			0x10,
-@@ -467,7 +467,7 @@ static void set_clamping(
- 			FMT_CLAMP_UPPER_G);
- 
- 		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_G);
--		dal_write_reg(opp110->base.ctx, addr, green_clamp_value);
-+		dm_write_reg(opp110->base.ctx, addr, green_clamp_value);
- 
- 		set_reg_field_value(blue_clamp_value,
- 			0x10,
-@@ -480,7 +480,7 @@ static void set_clamping(
- 			FMT_CLAMP_UPPER_B);
- 
- 		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_B);
--		dal_write_reg(opp110->base.ctx, addr, blue_clamp_value);
-+		dm_write_reg(opp110->base.ctx, addr, blue_clamp_value);
- 
- 		break;
- 
-@@ -490,7 +490,7 @@ static void set_clamping(
- 
- 	addr = FMT_REG(mmFMT_CLAMP_CNTL);
- 	/*Set clamp control*/
--	dal_write_reg(opp110->base.ctx, addr, clamp_cntl_value);
-+	dm_write_reg(opp110->base.ctx, addr, clamp_cntl_value);
- 
- }
- 
-@@ -509,7 +509,7 @@ static void set_pixel_encoding(
- 	uint32_t addr = FMT_REG(mmFMT_CONTROL);
- 
- 	/*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/
--	fmt_cntl_value = dal_read_reg(opp110->base.ctx, addr);
-+	fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr);
- 
- 	set_reg_field_value(fmt_cntl_value,
- 		0,
-@@ -534,7 +534,7 @@ static void set_pixel_encoding(
- 			FMT_CONTROL,
- 			FMT_SUBSAMPLING_ORDER);
- 	}
--	dal_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
-+	dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
- 
- }
- 
-@@ -570,7 +570,7 @@ void dce110_opp_set_dyn_expansion(
- 	bool enable_dyn_exp = false;
- 	uint32_t addr = FMT_REG(mmFMT_DYNAMIC_EXP_CNTL);
- 
--	value = dal_read_reg(opp->ctx, addr);
-+	value = dm_read_reg(opp->ctx, addr);
- 
- 	set_reg_field_value(value, 0,
- 		FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-@@ -606,5 +606,5 @@ void dce110_opp_set_dyn_expansion(
- 		}
- 	}
- 
--	dal_write_reg(opp->ctx, addr, value);
-+	dm_write_reg(opp->ctx, addr, value);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index f589025..32cf57d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -1797,7 +1797,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_START_CNTL,
- 			REGAMMA_CNTLA_EXP_REGION_START_SEGMENT);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 				DCP_REG(mmREGAMMA_CNTLA_START_CNTL),
- 				value);
- 	}
-@@ -1809,7 +1809,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_SLOPE_CNTL,
- 			REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_SLOPE_CNTL), value);
- 	}
- 	{
-@@ -1820,7 +1820,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_END_CNTL1,
- 			REGAMMA_CNTLA_EXP_REGION_END);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_END_CNTL1), value);
- 	}
- 	{
-@@ -1837,7 +1837,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_END_CNTL2,
- 			REGAMMA_CNTLA_EXP_REGION_END_SLOPE);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value);
- 	}
- 
-@@ -1869,7 +1869,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_0_1,
- 			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS);
- 
--		dal_write_reg(
-+		dm_write_reg(
- 			opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_0_1),
- 			value);
-@@ -1902,7 +1902,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_2_3,
- 			REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_2_3),
- 			value);
- 	}
-@@ -1934,7 +1934,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_4_5,
- 			REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_4_5),
- 			value);
- 	}
-@@ -1966,7 +1966,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_6_7,
- 			REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_6_7),
- 			value);
- 	}
-@@ -1998,7 +1998,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_8_9,
- 			REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_8_9),
- 			value);
- 	}
-@@ -2030,7 +2030,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_10_11,
- 			REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_10_11),
- 			value);
- 	}
-@@ -2062,7 +2062,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_12_13,
- 			REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_12_13),
- 			value);
- 	}
-@@ -2094,7 +2094,7 @@ static void regamma_config_regions_and_segments(
- 			REGAMMA_CNTLA_REGION_14_15,
- 			REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 			DCP_REG(mmREGAMMA_CNTLA_REGION_14_15),
- 			value);
- 	}
-@@ -2111,7 +2111,7 @@ static void program_pwl(
- 		uint8_t counter = 0;
- 
- 		/* Power on LUT memory */
--		value = dal_read_reg(opp110->base.ctx,
-+		value = dm_read_reg(opp110->base.ctx,
- 				DCFE_REG(mmDCFE_MEM_PWR_CTRL));
- 
- 		set_reg_field_value(
-@@ -2120,12 +2120,12 @@ static void program_pwl(
- 			DCFE_MEM_PWR_CTRL,
- 			DCP_REGAMMA_MEM_PWR_DIS);
- 
--		dal_write_reg(opp110->base.ctx,
-+		dm_write_reg(opp110->base.ctx,
- 				DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- 
- 		while (counter < max_tries) {
- 			value =
--				dal_read_reg(
-+				dm_read_reg(
- 					opp110->base.ctx,
- 					DCFE_REG(mmDCFE_MEM_PWR_STATUS));
- 
-@@ -2157,9 +2157,9 @@ static void program_pwl(
- 		REGAMMA_LUT_WRITE_EN_MASK,
- 		REGAMMA_LUT_WRITE_EN_MASK);
- 
--	dal_write_reg(opp110->base.ctx,
-+	dm_write_reg(opp110->base.ctx,
- 		DCP_REG(mmREGAMMA_LUT_WRITE_EN_MASK), value);
--	dal_write_reg(opp110->base.ctx,
-+	dm_write_reg(opp110->base.ctx,
- 		DCP_REG(mmREGAMMA_LUT_INDEX), 0);
- 
- 	/* Program REGAMMA_LUT_DATA */
-@@ -2172,15 +2172,15 @@ static void program_pwl(
- 				opp110->regamma.rgb_resulted;
- 
- 		while (i != opp110->regamma.hw_points_num) {
--			dal_write_reg(opp110->base.ctx, addr, rgb->red_reg);
--			dal_write_reg(opp110->base.ctx, addr, rgb->green_reg);
--			dal_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
-+			dm_write_reg(opp110->base.ctx, addr, rgb->red_reg);
-+			dm_write_reg(opp110->base.ctx, addr, rgb->green_reg);
-+			dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
- 
--			dal_write_reg(opp110->base.ctx, addr,
-+			dm_write_reg(opp110->base.ctx, addr,
- 				rgb->delta_red_reg);
--			dal_write_reg(opp110->base.ctx, addr,
-+			dm_write_reg(opp110->base.ctx, addr,
- 				rgb->delta_green_reg);
--			dal_write_reg(opp110->base.ctx, addr,
-+			dm_write_reg(opp110->base.ctx, addr,
- 				rgb->delta_blue_reg);
- 
- 			++rgb;
-@@ -2189,7 +2189,7 @@ static void program_pwl(
- 	}
- 
- 	/*  we are done with DCP LUT memory; re-enable low power mode */
--	value = dal_read_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-+	value = dm_read_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
- 
- 	set_reg_field_value(
- 		value,
-@@ -2197,7 +2197,7 @@ static void program_pwl(
- 		DCFE_MEM_PWR_CTRL,
- 		DCP_REGAMMA_MEM_PWR_DIS);
- 
--	dal_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
-+	dm_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
- 
- void dce110_opp_power_on_regamma_lut(
-@@ -2207,7 +2207,7 @@ void dce110_opp_power_on_regamma_lut(
- 	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
- 
- 	uint32_t value =
--		dal_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-+		dm_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL));
- 
- 	set_reg_field_value(
- 		value,
-@@ -2221,7 +2221,7 @@ void dce110_opp_power_on_regamma_lut(
- 		DCFE_MEM_PWR_CTRL,
- 		DCP_LUT_MEM_PWR_DIS);
- 
--	dal_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
-+	dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
- 
- static bool scale_gamma(
-@@ -2328,7 +2328,7 @@ static void configure_regamma_mode(
- 	enum wide_gamut_regamma_mode mode =
- 		WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A;
- 
--	uint32_t value = dal_read_reg(opp110->base.ctx, addr);
-+	uint32_t value = dm_read_reg(opp110->base.ctx, addr);
- 
- 	if (force_bypass) {
- 
-@@ -2338,7 +2338,7 @@ static void configure_regamma_mode(
- 			REGAMMA_CONTROL,
- 			GRPH_REGAMMA_MODE);
- 
--		dal_write_reg(opp110->base.ctx, addr, value);
-+		dm_write_reg(opp110->base.ctx, addr, value);
- 
- 		return;
- 	}
-@@ -2392,7 +2392,7 @@ static void configure_regamma_mode(
- 		break;
- 	}
- 
--	dal_write_reg(opp110->base.ctx, addr, value);
-+	dm_write_reg(opp110->base.ctx, addr, value);
- }
- 
- bool dce110_opp_set_regamma(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 8f5acbd..9e2b5d9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -22,7 +22,8 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+
-+#include "dm_services.h"
- 
- #include "link_encoder.h"
- #include "stream_encoder.h"
-@@ -299,7 +300,7 @@ static struct timing_generator *dce110_timing_generator_create(
- 		const struct dce110_timing_generator_offsets *offsets)
- {
- 	struct dce110_timing_generator *tg110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_timing_generator));
-+		dm_alloc(ctx, sizeof(struct dce110_timing_generator));
- 
- 	if (!tg110)
- 		return NULL;
-@@ -308,7 +309,7 @@ static struct timing_generator *dce110_timing_generator_create(
- 		return &tg110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, tg110);
-+	dm_free(ctx, tg110);
- 	return NULL;
- }
- 
-@@ -319,7 +320,7 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+		dm_alloc(ctx, sizeof(struct dce110_stream_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -328,7 +329,7 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, enc110);
-+	dm_free(ctx, enc110);
- 	return NULL;
- }
- 
-@@ -338,7 +339,7 @@ static struct mem_input *dce110_mem_input_create(
- 	const struct dce110_mem_input_reg_offsets *offset)
- {
- 	struct dce110_mem_input *mem_input110 =
--		dc_service_alloc(ctx, sizeof(struct dce110_mem_input));
-+		dm_alloc(ctx, sizeof(struct dce110_mem_input));
- 
- 	if (!mem_input110)
- 		return NULL;
-@@ -348,13 +349,13 @@ static struct mem_input *dce110_mem_input_create(
- 		return &mem_input110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, mem_input110);
-+	dm_free(ctx, mem_input110);
- 	return NULL;
- }
- 
- static void dce110_transform_destroy(struct transform **xfm)
- {
--	dc_service_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	dm_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
- 	*xfm = NULL;
- }
- 
-@@ -364,7 +365,7 @@ static struct transform *dce110_transform_create(
- 	const struct dce110_transform_reg_offsets *offsets)
- {
- 	struct dce110_transform *transform =
--		dc_service_alloc(ctx, sizeof(struct dce110_transform));
-+		dm_alloc(ctx, sizeof(struct dce110_transform));
- 
- 	if (!transform)
- 		return NULL;
-@@ -373,7 +374,7 @@ static struct transform *dce110_transform_create(
- 		return &transform->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, transform);
-+	dm_free(ctx, transform);
- 	return NULL;
- }
- 
-@@ -383,7 +384,7 @@ static struct input_pixel_processor *dce110_ipp_create(
- 	const struct dce110_ipp_reg_offsets *offsets)
- {
- 	struct dce110_ipp *ipp =
--		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
-+		dm_alloc(ctx, sizeof(struct dce110_ipp));
- 
- 	if (!ipp)
- 		return NULL;
-@@ -392,7 +393,7 @@ static struct input_pixel_processor *dce110_ipp_create(
- 		return &ipp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, ipp);
-+	dm_free(ctx, ipp);
- 	return NULL;
- }
- 
-@@ -400,7 +401,7 @@ struct link_encoder *dce110_link_encoder_create(
- 	const struct encoder_init_data *enc_init_data)
- {
- 	struct dce110_link_encoder *enc110 =
--		dc_service_alloc(
-+		dm_alloc(
- 			enc_init_data->ctx,
- 			sizeof(struct dce110_link_encoder));
- 
-@@ -416,13 +417,13 @@ struct link_encoder *dce110_link_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(enc_init_data->ctx, enc110);
-+	dm_free(enc_init_data->ctx, enc110);
- 	return NULL;
- }
- 
- void dce110_link_encoder_destroy(struct link_encoder **enc)
- {
--	dc_service_free((*enc)->ctx, TO_DCE110_LINK_ENC(*enc));
-+	dm_free((*enc)->ctx, TO_DCE110_LINK_ENC(*enc));
- 	*enc = NULL;
- }
- 
-@@ -433,7 +434,7 @@ static struct output_pixel_processor *dce110_opp_create(
- 	const struct dce110_opp_reg_offsets *offsets)
- {
- 	struct dce110_opp *opp =
--		dc_service_alloc(ctx, sizeof(struct dce110_opp));
-+		dm_alloc(ctx, sizeof(struct dce110_opp));
- 
- 	if (!opp)
- 		return NULL;
-@@ -443,7 +444,7 @@ static struct output_pixel_processor *dce110_opp_create(
- 		return &opp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, opp);
-+	dm_free(ctx, opp);
- 	return NULL;
- }
- 
-@@ -454,7 +455,7 @@ struct clock_source *dce110_clock_source_create(
- 	const struct dce110_clk_src_reg_offsets *offsets)
- {
- 	struct dce110_clk_src *clk_src =
--		dc_service_alloc(ctx, sizeof(struct dce110_clk_src));
-+		dm_alloc(ctx, sizeof(struct dce110_clk_src));
- 
- 	if (!clk_src)
- 		return NULL;
-@@ -468,7 +469,7 @@ struct clock_source *dce110_clock_source_create(
- 
- void dce110_clock_source_destroy(struct clock_source **clk_src)
- {
--	dc_service_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	dm_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
- 	*clk_src = NULL;
- }
- 
-@@ -487,20 +488,20 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dc_service_free(pool->mis[i]->ctx,
-+			dm_free(pool->mis[i]->ctx,
- 					TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dc_service_free(pool->stream_enc[i]->ctx,
-+			dm_free(pool->stream_enc[i]->ctx,
- 				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
-@@ -787,7 +788,7 @@ enum dc_status dce110_validate_bandwidth(
- 			 * the same
- 			 */
- 			if (number_of_displays != 0 && all_displays_in_sync)
--				if (dal_memcmp(&prev_timing,
-+				if (dm_memcmp(&prev_timing,
- 					&stream->public.timing,
- 					sizeof(struct dc_crtc_timing))!= 0)
- 					all_displays_in_sync = false;
-@@ -832,7 +833,7 @@ enum dc_status dce110_validate_bandwidth(
- 			"%s: Bandwidth validation failed!",
- 			__func__);
- 
--	if (dal_memcmp(&dc->current_context.bw_results,
-+	if (dm_memcmp(&dc->current_context.bw_results,
- 			&context->bw_results, sizeof(context->bw_results))) {
- 		struct log_entry log_entry;
- 		dal_logger_open(
-@@ -1047,7 +1048,7 @@ bool dce110_construct_resource_pool(
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
--			dal_error("DC: failed to create clock sources!\n");
-+			dm_error("DC: failed to create clock sources!\n");
- 			BREAK_TO_DEBUGGER();
- 			goto clk_src_create_fail;
- 		}
-@@ -1055,7 +1056,7 @@ bool dce110_construct_resource_pool(
- 
- 	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
- 	if (pool->display_clock == NULL) {
--		dal_error("DC: failed to create display clock!\n");
-+		dm_error("DC: failed to create display clock!\n");
- 		BREAK_TO_DEBUGGER();
- 		goto disp_clk_create_fail;
- 	}
-@@ -1079,7 +1080,7 @@ bool dce110_construct_resource_pool(
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
--		dal_error("DC: failed to create filter!\n");
-+		dm_error("DC: failed to create filter!\n");
- 		goto filter_create_fail;
- 	}
- 
-@@ -1088,7 +1089,7 @@ bool dce110_construct_resource_pool(
- 				adapter_serv, ctx, i, &dce110_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create tg!\n");
-+			dm_error("DC: failed to create tg!\n");
- 			goto controller_create_fail;
- 		}
- 
-@@ -1096,7 +1097,7 @@ bool dce110_construct_resource_pool(
- 				&dce110_mi_reg_offsets[i]);
- 		if (pool->mis[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create memory input!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1104,7 +1105,7 @@ bool dce110_construct_resource_pool(
- 		pool->ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]);
- 		if (pool->ipps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create input pixel processor!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1113,7 +1114,7 @@ bool dce110_construct_resource_pool(
- 					ctx, i, &dce110_xfm_offsets[i]);
- 		if (pool->transforms[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create transform!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1124,7 +1125,7 @@ bool dce110_construct_resource_pool(
- 		pool->opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]);
- 		if (pool->opps[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error(
-+			dm_error(
- 				"DC: failed to create output pixel processor!\n");
- 			goto controller_create_fail;
- 		}
-@@ -1146,7 +1147,7 @@ bool dce110_construct_resource_pool(
- 		pool->audios[i] = dal_audio_create(&audio_init_data);
- 		if (pool->audios[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create DPPs!\n");
-+			dm_error("DC: failed to create DPPs!\n");
- 			goto audio_create_fail;
- 		}
- 		pool->audio_count++;
-@@ -1162,7 +1163,7 @@ bool dce110_construct_resource_pool(
- 				&stream_enc_regs[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
--				dal_error("DC: failed to create stream_encoder!\n");
-+				dm_error("DC: failed to create stream_encoder!\n");
- 				goto stream_enc_create_fail;
- 			}
- 		}
-@@ -1175,7 +1176,7 @@ bool dce110_construct_resource_pool(
- 								adapter_serv));
- 		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
- 			BREAK_TO_DEBUGGER();
--			dal_error("DC: failed to create stream_encoder!\n");
-+			dm_error("DC: failed to create stream_encoder!\n");
- 			goto stream_enc_create_fail;
- 		}
- 		pool->stream_enc_count++;
-@@ -1186,7 +1187,7 @@ bool dce110_construct_resource_pool(
- stream_enc_create_fail:
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dc_service_free(pool->stream_enc[i]->ctx,
-+			dm_free(pool->stream_enc[i]->ctx,
- 				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
-@@ -1208,13 +1209,13 @@ controller_create_fail:
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dc_service_free(pool->mis[i]->ctx,
-+			dm_free(pool->mis[i]->ctx,
- 					TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dc_service_free(pool->timing_generators[i]->ctx,
-+			dm_free(pool->timing_generators[i]->ctx,
- 				DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index fadcc06..2107309 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -23,9 +23,10 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dc_bios_types.h"
- #include "dce110_stream_encoder.h"
-+
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
- #include "dce/dce_11_0_enum.h"
-@@ -81,7 +82,7 @@ static void dce110_update_generic_info_packet(
- 	{
- 		addr = LINK_REG(AFMT_VBI_PACKET_CONTROL);
- 
--		regval = dal_read_reg(ctx, addr);
-+		regval = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			regval,
-@@ -89,7 +90,7 @@ static void dce110_update_generic_info_packet(
- 			AFMT_VBI_PACKET_CONTROL,
- 			AFMT_GENERIC_INDEX);
- 
--		dal_write_reg(ctx, addr, regval);
-+		dm_write_reg(ctx, addr, regval);
- 	}
- 
- 	/* write generic packet header
-@@ -123,7 +124,7 @@ static void dce110_update_generic_info_packet(
- 			AFMT_GENERIC_HDR,
- 			AFMT_GENERIC_HB3);
- 
--		dal_write_reg(ctx, addr, regval);
-+		dm_write_reg(ctx, addr, regval);
- 	}
- 
- 	/* write generic packet contents
-@@ -138,7 +139,7 @@ static void dce110_update_generic_info_packet(
- 		addr = LINK_REG(AFMT_GENERIC_0);
- 
- 		do {
--			dal_write_reg(ctx, addr++, *content++);
-+			dm_write_reg(ctx, addr++, *content++);
- 
- 			++counter;
- 		} while (counter < 7);
-@@ -146,7 +147,7 @@ static void dce110_update_generic_info_packet(
- 
- 	addr = LINK_REG(AFMT_GENERIC_7);
- 
--	dal_write_reg(
-+	dm_write_reg(
- 		ctx,
- 		addr,
- 		0);
-@@ -155,7 +156,7 @@ static void dce110_update_generic_info_packet(
- 	{
- 		addr = LINK_REG(AFMT_VBI_PACKET_CONTROL);
- 
--		regval = dal_read_reg(ctx, addr);
-+		regval = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			regval,
-@@ -169,7 +170,7 @@ static void dce110_update_generic_info_packet(
- 			AFMT_VBI_PACKET_CONTROL,
- 			AFMT_GENERIC2_UPDATE);
- 
--		dal_write_reg(ctx, addr, regval);
-+		dm_write_reg(ctx, addr, regval);
- 	}
- }
- 
-@@ -224,7 +225,7 @@ static void dce110_update_hdmi_info_packet(
- 		return;
- 	}
- 
--	regval = dal_read_reg(ctx, addr);
-+	regval = dm_read_reg(ctx, addr);
- 
- 	switch (packet_index) {
- 	case 0:
-@@ -274,7 +275,7 @@ static void dce110_update_hdmi_info_packet(
- 		return;
- 	}
- 
--	dal_write_reg(ctx, addr, regval);
-+	dm_write_reg(ctx, addr, regval);
- }
- 
- bool dce110_stream_encoder_construct(
-@@ -306,7 +307,7 @@ void dce110_stream_encoder_dp_set_stream_attribute(
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	const uint32_t addr = LINK_REG(DP_PIXEL_FORMAT);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	/* set pixel encoding */
- 	switch (crtc_timing->pixel_encoding) {
-@@ -385,7 +386,7 @@ void dce110_stream_encoder_dp_set_stream_attribute(
- 	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_DYN_RANGE);
- 	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_YCBCR_RANGE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- /* setup stream encoder in hdmi mode */
-@@ -414,7 +415,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 		return;
- 
- 	addr = LINK_REG(DIG_FE_CNTL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	switch (crtc_timing->pixel_encoding) {
- 	case PIXEL_ENCODING_YCBCR422:
-@@ -425,11 +426,11 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 		break;
- 	}
- 	set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* setup HDMI engine */
- 	addr = LINK_REG(HDMI_CONTROL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_PACKET_GEN_VERSION);
- 	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_KEEPOUT_MODE);
- 	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE);
-@@ -523,48 +524,48 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 			HDMI_CLOCK_CHANNEL_RATE);
- 	}
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = LINK_REG(HDMI_VBI_PACKET_CONTROL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND);
- 	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* following belongs to audio */
- 	addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		HDMI_INFOFRAME_CONTROL0,
- 		HDMI_AUDIO_INFO_SEND);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = LINK_REG(AFMT_INFOFRAME_CONTROL0);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		1,
- 		AFMT_INFOFRAME_CONTROL0,
- 		AFMT_AUDIO_INFO_UPDATE);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = LINK_REG(HDMI_INFOFRAME_CONTROL1);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		VBI_LINE_0 + 2,
- 		HDMI_INFOFRAME_CONTROL1,
- 		HDMI_AUDIO_INFO_LINE);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = LINK_REG(HDMI_GC);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, HDMI_GC, HDMI_GC_AVMUTE);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- /* setup stream encoder in dvi mode */
-@@ -576,7 +577,7 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = LINK_REG(DIG_FE_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 	struct bp_encoder_control cntl = {0};
- 
- 	cntl.action = ENCODER_CONTROL_SETUP;
-@@ -622,7 +623,7 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 		set_reg_field_value(value, 0, DIG_FE_CNTL, TMDS_COLOR_FORMAT);
- 		break;
- 	}
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_stream_encoder_set_mst_bandwidth(
-@@ -646,7 +647,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 
- 	{
- 		addr = LINK_REG(DP_MSE_RATE_CNTL);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -660,7 +661,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 			DP_MSE_RATE_CNTL,
- 			DP_MSE_RATE_Y);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* wait for update to be completed on the link */
-@@ -670,7 +671,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 		addr = LINK_REG(DP_MSE_RATE_UPDATE);
- 
- 		do {
--			value = dal_read_reg(ctx, addr);
-+			value = dm_read_reg(ctx, addr);
- 
- 			field = get_reg_field_value(
- 					value,
-@@ -681,7 +682,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
- 				break;
- 
--			dc_service_delay_in_microseconds(ctx, 10);
-+			dm_delay_in_microseconds(ctx, 10);
- 
- 			++retries;
- 		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-@@ -705,21 +706,21 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 
- 		addr = LINK_REG(AFMT_AVI_INFO0);
- 		regval = content[0];
--		dal_write_reg(
-+		dm_write_reg(
- 			ctx,
- 			addr,
- 			regval);
- 		regval = content[1];
- 
- 		addr = LINK_REG(AFMT_AVI_INFO1);
--		dal_write_reg(
-+		dm_write_reg(
- 			ctx,
- 			addr,
- 			regval);
- 		regval = content[2];
- 
- 		addr = LINK_REG(AFMT_AVI_INFO2);
--		dal_write_reg(
-+		dm_write_reg(
- 			ctx,
- 			addr,
- 			regval);
-@@ -733,14 +734,14 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 			AFMT_AVI_INFO3,
- 			AFMT_AVI_INFO_VERSION);
- 
--		dal_write_reg(
-+		dm_write_reg(
- 			ctx,
- 			addr,
- 			regval);
- 
- 		addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 
--		control0val = dal_read_reg(ctx, addr);
-+		control0val = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			control0val,
-@@ -754,11 +755,11 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 			HDMI_INFOFRAME_CONTROL0,
- 			HDMI_AVI_INFO_CONT);
- 
--		dal_write_reg(ctx, addr, control0val);
-+		dm_write_reg(ctx, addr, control0val);
- 
- 		addr = LINK_REG(HDMI_INFOFRAME_CONTROL1);
- 
--		control1val = dal_read_reg(ctx, addr);
-+		control1val = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			control1val,
-@@ -766,11 +767,11 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 			HDMI_INFOFRAME_CONTROL1,
- 			HDMI_AVI_INFO_LINE);
- 
--		dal_write_reg(ctx, addr, control1val);
-+		dm_write_reg(ctx, addr, control1val);
- 	} else {
- 		addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 
--		regval = dal_read_reg(ctx, addr);
-+		regval = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			regval,
-@@ -784,7 +785,7 @@ void dce110_stream_encoder_update_hdmi_info_packets(
- 			HDMI_INFOFRAME_CONTROL0,
- 			HDMI_AVI_INFO_CONT);
- 
--		dal_write_reg(ctx, addr, regval);
-+		dm_write_reg(ctx, addr, regval);
- 	}
- 
- 	dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
-@@ -803,7 +804,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 	/* stop generic packets 0 & 1 on HDMI */
- 	addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL0);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -836,12 +837,12 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 		HDMI_GENERIC_PACKET_CONTROL0,
- 		HDMI_GENERIC0_SEND);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* stop generic packets 2 & 3 on HDMI */
- 	addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL1);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -874,12 +875,12 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 		HDMI_GENERIC_PACKET_CONTROL1,
- 		HDMI_GENERIC3_SEND);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* stop AVI packet on HDMI */
- 	addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -892,7 +893,7 @@ void dce110_stream_encoder_stop_hdmi_info_packets(
- 		HDMI_INFOFRAME_CONTROL0,
- 		HDMI_AVI_INFO_CONT);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- void dce110_stream_encoder_update_dp_info_packets(
- 	struct stream_encoder *enc,
-@@ -913,7 +914,7 @@ void dce110_stream_encoder_update_dp_info_packets(
- 	*  If enabled, packet transmission begins on the next frame
- 	*/
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -934,7 +935,7 @@ void dce110_stream_encoder_update_dp_info_packets(
- 			DP_SEC_CNTL,
- 			DP_SEC_STREAM_ENABLE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_stream_encoder_stop_dp_info_packets(
-@@ -944,7 +945,7 @@ void dce110_stream_encoder_stop_dp_info_packets(
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = LINK_REG(DP_SEC_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
- 	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP1_ENABLE);
-@@ -965,7 +966,7 @@ void dce110_stream_encoder_stop_dp_info_packets(
- 			DP_SEC_CNTL,
- 			DP_SEC_STREAM_ENABLE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_stream_encoder_dp_blank(
-@@ -974,7 +975,7 @@ void dce110_stream_encoder_dp_blank(
- 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr = LINK_REG(DP_VID_STREAM_CNTL);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 	uint32_t retries = 0;
- 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
- 
-@@ -1000,7 +1001,7 @@ void dce110_stream_encoder_dp_blank(
- 
- 	/* disable DP stream */
- 	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* the encoder stops sending the video stream
- 	* at the start of the vertical blanking.
-@@ -1008,7 +1009,7 @@ void dce110_stream_encoder_dp_blank(
- 	*/
- 
- 	do {
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		if (!get_reg_field_value(
- 			value,
-@@ -1016,7 +1017,7 @@ void dce110_stream_encoder_dp_blank(
- 			DP_VID_STREAM_STATUS))
- 			break;
- 
--		dc_service_delay_in_microseconds(ctx, 10);
-+		dm_delay_in_microseconds(ctx, 10);
- 
- 		++retries;
- 	} while (retries < max_retries);
-@@ -1029,9 +1030,9 @@ void dce110_stream_encoder_dp_blank(
- 	* i.e. DP_VID_STREAM_STATUS stuck at 1.
- 	*/
- 	addr = LINK_REG(DP_STEER_FIFO);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, true, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- /* output video stream to link encoder */
-@@ -1063,45 +1064,45 @@ void dce110_stream_encoder_dp_unblank(
- 
- 		/* enable auto measurement */
- 		addr = LINK_REG(DP_VID_TIMING);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 		set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 
- 		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
- 		* therefore program initial value for Mvid and Nvid
- 		*/
- 		addr = LINK_REG(DP_VID_N);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 		set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 
- 		addr = LINK_REG(DP_VID_M);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 		set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 
- 		addr = LINK_REG(DP_VID_TIMING);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 		set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* set DIG_START to 0x1 to resync FIFO */
- 	addr = LINK_REG(DIG_FE_CNTL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* switch DP encoder to CRTC data */
- 	addr = LINK_REG(DP_STEER_FIFO);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, 0, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* wait 100us for DIG/DP logic to prime
- 	* (i.e. a few video lines)
- 	*/
--	dc_service_delay_in_microseconds(ctx, 100);
-+	dm_delay_in_microseconds(ctx, 100);
- 
- 	/* the hardware would start sending video at the start of the next DP
- 	* frame (i.e. rising edge of the vblank).
-@@ -1111,12 +1112,12 @@ void dce110_stream_encoder_dp_unblank(
- 	* programmable
- 	*/
- 	addr = LINK_REG(DP_VID_STREAM_CNTL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		true,
- 		DP_VID_STREAM_CNTL,
- 		DP_VID_STREAM_ENABLE);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 50b7c70..d7cdd91 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -36,6 +36,7 @@
- #include "include/adapter_service_interface.h"
- #include "include/logger_interface.h"
- #include "dce110_timing_generator.h"
-+
- #include "../inc/timing_generator.h"
- 
- enum black_color_format {
-@@ -250,7 +251,7 @@ static bool dce110_timing_generator_is_in_vertical_blank(
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	addr = CRTC_REG(mmCRTC_STATUS);
--	value = dal_read_reg(tg->ctx, addr);
-+	value = dm_read_reg(tg->ctx, addr);
- 	field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
- 	return field == 1;
- }
-@@ -263,10 +264,10 @@ void dce110_timing_generator_set_early_control(
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t address = CRTC_REG(mmCRTC_CONTROL);
- 
--	regval = dal_read_reg(tg->ctx, address);
-+	regval = dm_read_reg(tg->ctx, address);
- 	set_reg_field_value(regval, early_cntl,
- 			CRTC_CONTROL, CRTC_HBLANK_EARLY_CONTROL);
--	dal_write_reg(tg->ctx, address, regval);
-+	dm_write_reg(tg->ctx, address, regval);
- }
- 
- /**
-@@ -282,11 +283,11 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	uint32_t value;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	value = dal_read_reg(tg->ctx,
-+	value = dm_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
- 	set_reg_field_value(value, 3,
- 			CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
--	dal_write_reg(tg->ctx,
-+	dm_write_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
- 	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
-@@ -301,7 +302,7 @@ void dce110_timing_generator_program_blank_color(
- 	struct crtc_black_color black_color;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
--	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
- 	dce110_timing_generator_color_space_to_black_color(
- 		color_space,
-@@ -323,7 +324,7 @@ void dce110_timing_generator_program_blank_color(
- 		CRTC_BLACK_COLOR,
- 		CRTC_BLACK_COLOR_R_CR);
- 
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- }
- 
- /**
-@@ -335,7 +336,7 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLANK_CONTROL);
--	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
- 	uint8_t counter = 100;
- 
- 	set_reg_field_value(
-@@ -350,10 +351,10 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- 		CRTC_BLANK_CONTROL,
- 		CRTC_BLANK_DE_MODE);
- 
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- 
- 	while (counter > 0) {
--		value = dal_read_reg(tg->ctx, addr);
-+		value = dm_read_reg(tg->ctx, addr);
- 
- 		if (get_reg_field_value(
- 			value,
-@@ -365,7 +366,7 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- 			CRTC_CURRENT_BLANK_STATE) == 1)
- 			break;
- 
--		dc_service_sleep_in_milliseconds(tg->ctx, 1);
-+		dm_sleep_in_milliseconds(tg->ctx, 1);
- 		counter--;
- 	}
- 
-@@ -388,7 +389,7 @@ bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLANK_CONTROL);
--	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -402,7 +403,7 @@ bool dce110_timing_generator_unblank_crtc(struct timing_generator *tg)
- 		CRTC_BLANK_CONTROL,
- 		CRTC_BLANK_DE_MODE);
- 
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- 
- 	return true;
- }
-@@ -428,7 +429,7 @@ static void disable_stereo(struct timing_generator *tg)
- 	uint32_t struc_en = 0;
- 	uint32_t struc_stereo_sel_ovr = 0;
- 
--	value = dal_read_reg(tg->ctx, addr);
-+	value = dm_read_reg(tg->ctx, addr);
- 	struc_en = get_reg_field_value(
- 			value,
- 			CRTC_3D_STRUCTURE_CONTROL,
-@@ -451,11 +452,11 @@ static void disable_stereo(struct timing_generator *tg)
- 	}
- 
- 	value = 0;
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- 
- 
- 	addr = tg->regs[IDX_CRTC_STEREO_CONTROL];
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- }
- #endif
- 
-@@ -492,7 +493,7 @@ static void program_horz_count_by_2(
- 	uint32_t regval;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	regval = dal_read_reg(tg->ctx,
-+	regval = dm_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_COUNT_CONTROL));
- 
- 	set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,
-@@ -502,7 +503,7 @@ static void program_horz_count_by_2(
- 		set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL,
- 					CRTC_HORZ_COUNT_BY2_EN);
- 
--	dal_write_reg(tg->ctx,
-+	dm_write_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_COUNT_CONTROL), regval);
- }
- 
-@@ -528,7 +529,7 @@ bool dce110_timing_generator_program_timing_generator(
- 			dc_crtc_timing->h_front_porch;
- 	uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;
- 
--	dc_service_memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
-+	dm_memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
- 
- 	/* Due to an asic bug we need to apply the Front Porch workaround prior
- 	 * to programming the timing.
-@@ -610,16 +611,16 @@ void dce110_timing_generator_program_drr(
- 	uint32_t addr = 0;
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
--	v_total_min = dal_read_reg(tg->ctx, addr);
-+	v_total_min = dm_read_reg(tg->ctx, addr);
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
--	v_total_max = dal_read_reg(tg->ctx, addr);
-+	v_total_max = dm_read_reg(tg->ctx, addr);
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL);
--	v_total_cntl = dal_read_reg(tg->ctx, addr);
-+	v_total_cntl = dm_read_reg(tg->ctx, addr);
- 
- 	addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL);
--	static_screen_cntl = dal_read_reg(tg->ctx, addr);
-+	static_screen_cntl = dm_read_reg(tg->ctx, addr);
- 
- 	if (timing != NULL) {
- 		/* Set Static Screen trigger events
-@@ -741,16 +742,16 @@ void dce110_timing_generator_program_drr(
- 	}
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
--	dal_write_reg(tg->ctx, addr, v_total_min);
-+	dm_write_reg(tg->ctx, addr, v_total_min);
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
--	dal_write_reg(tg->ctx, addr, v_total_max);
-+	dm_write_reg(tg->ctx, addr, v_total_max);
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL);
--	dal_write_reg(tg->ctx, addr, v_total_cntl);
-+	dm_write_reg(tg->ctx, addr, v_total_cntl);
- 
- 	addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL);
--	dal_write_reg(tg->ctx, addr, static_screen_cntl);
-+	dm_write_reg(tg->ctx, addr, static_screen_cntl);
- }
- 
- /*
-@@ -771,7 +772,7 @@ uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT);
--	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
- 	uint32_t field = get_reg_field_value(
- 			value, CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
- 
-@@ -797,7 +798,7 @@ void dce110_timing_generator_get_crtc_positions(
- 	uint32_t value;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION));
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION));
- 
- 	*h_position = get_reg_field_value(
- 			value,
-@@ -834,10 +835,10 @@ uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 
- 	/* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */
- 
--	*vbl = dal_read_reg(tg->ctx,
-+	*vbl = dm_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_V_BLANK_START_END));
- 
--	*position = dal_read_reg(tg->ctx,
-+	*position = dm_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_STATUS_POSITION));
- 
- 	/* @TODO: return value should indicate if current
-@@ -868,25 +869,25 @@ void dce110_timing_generator_program_blanking(
- 	uint32_t tmp = 0;
- 
- 	addr = CRTC_REG(mmCRTC_H_TOTAL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		timing->h_total - 1,
- 		CRTC_H_TOTAL,
- 		CRTC_H_TOTAL);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = CRTC_REG(mmCRTC_V_TOTAL);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		timing->v_total - 1,
- 		CRTC_V_TOTAL,
- 		CRTC_V_TOTAL);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	tmp = timing->h_total -
- 		(h_sync_start + timing->h_border_left);
-@@ -906,10 +907,10 @@ void dce110_timing_generator_program_blanking(
- 		CRTC_H_BLANK_START_END,
- 		CRTC_H_BLANK_START);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = CRTC_REG(mmCRTC_V_BLANK_START_END);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	tmp = timing->v_total - (v_sync_start + timing->v_border_top);
- 
-@@ -928,7 +929,7 @@ void dce110_timing_generator_program_blanking(
- 		CRTC_V_BLANK_START_END,
- 		CRTC_V_BLANK_START);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_timing_generator_set_test_pattern(
-@@ -961,7 +962,7 @@ void dce110_timing_generator_set_test_pattern(
- 			CRTC_TEST_PATTERN_PARAMETERS,
- 			CRTC_TEST_PATTERN_HRES);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 
- 		addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL);
- 		value = 0;
-@@ -989,7 +990,7 @@ void dce110_timing_generator_set_test_pattern(
- 			1,
- 			CRTC_TEST_PATTERN_CONTROL,
- 			CRTC_TEST_PATTERN_COLOR_FORMAT);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 		break;
- 	} /* switch() */
- }
-@@ -1136,7 +1137,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
- 	uint32_t check_point = FLIP_READY_BACK_LOOKUP;
- 
--	value = dal_read_reg(tg->ctx, address);
-+	value = dm_read_reg(tg->ctx, address);
- 
- 	/* This pipe will belong to GSL Group zero. */
- 	set_reg_field_value(value,
-@@ -1165,7 +1166,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	{
- 		uint32_t value_crtc_vtotal;
- 
--		value_crtc_vtotal = dal_read_reg(tg->ctx,
-+		value_crtc_vtotal = dm_read_reg(tg->ctx,
- 				CRTC_REG(mmCRTC_V_TOTAL));
- 
- 		set_reg_field_value(value,
-@@ -1178,7 +1179,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 				CRTC_V_TOTAL,
- 				CRTC_V_TOTAL);
- 
--		dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0);
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0);
- 	}
- 
- 	set_reg_field_value(value,
-@@ -1186,7 +1187,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 			DCP_GSL_CONTROL,
- 			DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
- 
--	dal_write_reg(tg->ctx, address, value);
-+	dm_write_reg(tg->ctx, address, value);
- 
- 	/********************************************************************/
- 	address = CRTC_REG(mmCRTC_GSL_CONTROL);
-@@ -1202,7 +1203,7 @@ void dce110_timing_generator_setup_global_swap_lock(
- 			CRTC_GSL_CONTROL,
- 			CRTC_GSL_FORCE_DELAY);
- 
--	dal_write_reg(tg->ctx, address, value);
-+	dm_write_reg(tg->ctx, address, value);
- }
- 
- 
-@@ -1246,7 +1247,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 	{
- 		uint32_t value_crtc_vtotal;
- 
--		value_crtc_vtotal = dal_read_reg(tg->ctx,
-+		value_crtc_vtotal = dm_read_reg(tg->ctx,
- 				CRTC_REG(mmCRTC_V_TOTAL));
- 
- 		set_reg_field_value(value,
-@@ -1260,7 +1261,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 			DCP_GSL_CONTROL,
- 			DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
- 
--	dal_write_reg(tg->ctx, address, value);
-+	dm_write_reg(tg->ctx, address, value);
- 
- 	/********************************************************************/
- 	address = CRTC_REG(mmCRTC_GSL_CONTROL);
-@@ -1276,7 +1277,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 			CRTC_GSL_CONTROL,
- 			CRTC_GSL_FORCE_DELAY);
- 
--	dal_write_reg(tg->ctx, address, value);
-+	dm_write_reg(tg->ctx, address, value);
- }
- /**
-  *****************************************************************************
-@@ -1313,7 +1314,7 @@ void dce110_timing_generator_enable_advanced_request(
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
--	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
- 	if (enable && !DCE110TG_FROM_TG(tg)->disable_advanced_request) {
- 		set_reg_field_value(
-@@ -1365,7 +1366,7 @@ void dce110_timing_generator_enable_advanced_request(
- 		CRTC_START_LINE_CONTROL,
- 		CRTC_INTERLACE_START_LINE_EARLY);
- 
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- }
- 
- /*TODO: Figure out if we need this function. */
-@@ -1375,7 +1376,7 @@ void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
- 	struct dc_context *ctx = tg->ctx;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK);
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -1383,7 +1384,7 @@ void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
- 		CRTC_MASTER_UPDATE_LOCK,
- 		MASTER_UPDATE_LOCK);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_timing_generator_enable_reset_trigger(
-@@ -1402,7 +1403,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 	/* Default = based on current timing polarity */
- 	case TRIGGER_EDGE_DEFAULT:
- 		{
--			uint32_t pol_value = dal_read_reg(tg->ctx,
-+			uint32_t pol_value = dm_read_reg(tg->ctx,
- 					CRTC_REG(mmCRTC_V_SYNC_A_CNTL));
- 
- 			/* Register spec has reversed definition:
-@@ -1431,7 +1432,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 		return;
- 	}
- 
--	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
- 
- 	switch(trigger_params->source) {
- 	/* Currently supporting only a single group, the group zero. */
-@@ -1478,11 +1479,11 @@ void dce110_timing_generator_enable_reset_trigger(
- 			CRTC_TRIGB_CNTL,
- 			CRTC_TRIGB_CLEAR);
- 
--	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
- 
- 	/**************************************************************/
- 
--	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
- 	set_reg_field_value(value,
- 			2, /* force H count to H_TOTAL and V count to V_TOTAL */
-@@ -1499,7 +1500,7 @@ void dce110_timing_generator_enable_reset_trigger(
- 			CRTC_FORCE_COUNT_NOW_CNTL,
- 			CRTC_FORCE_COUNT_NOW_CLEAR);
- 
--	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
- }
- 
- void dce110_timing_generator_disable_reset_trigger(
-@@ -1508,7 +1509,7 @@ void dce110_timing_generator_disable_reset_trigger(
- 	uint32_t value;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
- 	set_reg_field_value(value,
- 			0, /* force counter now mode is disabled */
-@@ -1520,10 +1521,10 @@ void dce110_timing_generator_disable_reset_trigger(
- 			CRTC_FORCE_COUNT_NOW_CNTL,
- 			CRTC_FORCE_COUNT_NOW_CLEAR);
- 
--	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
- 
- 	/********************************************************************/
--	value = dal_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
- 
- 	set_reg_field_value(value,
- 			TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
-@@ -1540,7 +1541,7 @@ void dce110_timing_generator_disable_reset_trigger(
- 			CRTC_TRIGB_CNTL,
- 			CRTC_TRIGB_CLEAR);
- 
--	dal_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
- }
- 
- /**
-@@ -1556,7 +1557,7 @@ bool dce110_timing_generator_did_triggered_reset_occur(
- 	struct timing_generator *tg)
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
--	uint32_t value = dal_read_reg(tg->ctx,
-+	uint32_t value = dm_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
- 
- 	return get_reg_field_value(value,
-@@ -1599,7 +1600,7 @@ void dce110_timing_generator_disable_vga(
- 	default:
- 		break;
- 	}
--	value = dal_read_reg(tg->ctx, addr);
-+	value = dm_read_reg(tg->ctx, addr);
- 
- 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
- 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
-@@ -1607,7 +1608,7 @@ void dce110_timing_generator_disable_vga(
- 			value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
- 	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
- 
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- }
- 
- /**
-@@ -1724,15 +1725,15 @@ void dce110_timing_generator_set_overscan_color_black(
- 		break;
- 	}
- 	addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 	addr = CRTC_REG(mmCRTC_BLACK_COLOR);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 	/* This is desirable to have a constant DAC output voltage during the
- 	 * blank time that is higher than the 0 volt reference level that the
- 	 * DAC outputs when the NBLANK signal
- 	 * is asserted low, such as for output to an analog TV. */
- 	addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* TO DO we have to program EXT registers and we need to know LB DATA
- 	 * format because it is used when more 10 , i.e. 12 bits per color
-@@ -1749,7 +1750,7 @@ void dce110_tg_program_blank_color(struct timing_generator *tg,
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
--	uint32_t value = dal_read_reg(tg->ctx, addr);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -1767,10 +1768,10 @@ void dce110_tg_program_blank_color(struct timing_generator *tg,
- 		CRTC_BLACK_COLOR,
- 		CRTC_BLACK_COLOR_R_CR);
- 
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- 
- 	addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR);
--	dal_write_reg(tg->ctx, addr, value);
-+	dm_write_reg(tg->ctx, addr, value);
- }
- 
- void dce110_tg_set_overscan_color(struct timing_generator *tg,
-@@ -1800,7 +1801,7 @@ void dce110_tg_set_overscan_color(struct timing_generator *tg,
- 		CRTC_OVERSCAN_COLOR_RED);
- 
- 	addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_tg_get_position(struct timing_generator *tg,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-index 16cddb5..2654a96 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -37,6 +37,7 @@
- #include "include/logger_interface.h"
- 
- #include "dce110_transform.h"
-+
- #include "dce110_transform_bit_depth.h"
- 
- static struct transform_funcs dce110_transform_funcs = {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index a64a507..fb5ef6d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -264,7 +264,7 @@ static bool set_clamp(
- 			OUT_CLAMP_CONTROL_B_CB,
- 			OUT_CLAMP_MAX_B_CB);
- 
--		dal_write_reg(xfm110->base.ctx,
-+		dm_write_reg(xfm110->base.ctx,
- 			DCP_REG(mmOUT_CLAMP_CONTROL_B_CB),
- 			value);
- 	}
-@@ -284,7 +284,7 @@ static bool set_clamp(
- 			OUT_CLAMP_CONTROL_G_Y,
- 			OUT_CLAMP_MAX_G_Y);
- 
--		dal_write_reg(xfm110->base.ctx,
-+		dm_write_reg(xfm110->base.ctx,
- 			DCP_REG(mmOUT_CLAMP_CONTROL_G_Y),
- 			value);
- 	}
-@@ -304,7 +304,7 @@ static bool set_clamp(
- 			OUT_CLAMP_CONTROL_R_CR,
- 			OUT_CLAMP_MAX_R_CR);
- 
--		dal_write_reg(xfm110->base.ctx,
-+		dm_write_reg(xfm110->base.ctx,
- 			DCP_REG(mmOUT_CLAMP_CONTROL_R_CR),
- 			value);
- 	}
-@@ -416,7 +416,7 @@ static bool set_round(
- 		OUT_ROUND_TRUNC_MODE);
- 
- 	/*  write the register */
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 				DCP_REG(mmOUT_ROUND_CONTROL),
- 				value);
- 
-@@ -530,7 +530,7 @@ static bool set_dither(
- 			DCP_HIGHPASS_RANDOM_ENABLE);
- 
- 	/*  write the register */
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 				DCP_REG(mmDCP_SPATIAL_DITHER_CNTL),
- 				value);
- 
-@@ -595,7 +595,7 @@ void dce110_transform_enable_alpha(
- 	uint32_t value;
- 	uint32_t addr = LB_REG(mmLB_DATA_FORMAT);
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	if (enable == 1)
- 		set_reg_field_value(
-@@ -610,7 +610,7 @@ void dce110_transform_enable_alpha(
- 				LB_DATA_FORMAT,
- 				ALPHA_EN);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static enum lb_pixel_depth translate_display_bpp_to_lb_depth(
-@@ -658,7 +658,7 @@ bool dce110_transform_get_next_lower_pixel_storage_depth(
- bool dce110_transform_is_prefetch_enabled(
- 	struct dce110_transform *xfm110)
- {
--	uint32_t value = dal_read_reg(
-+	uint32_t value = dm_read_reg(
- 			xfm110->base.ctx, LB_REG(mmLB_DATA_FORMAT));
- 
- 	if (get_reg_field_value(value, LB_DATA_FORMAT, PREFETCH) == 1)
-@@ -677,7 +677,7 @@ bool dce110_transform_get_current_pixel_storage_depth(
- 	if (depth == NULL)
- 		return false;
- 
--	value = dal_read_reg(
-+	value = dm_read_reg(
- 			xfm->ctx,
- 			LB_REG(mmLB_DATA_FORMAT));
- 
-@@ -711,7 +711,7 @@ static void set_denormalization(
- 	struct dce110_transform *xfm110,
- 	enum dc_color_depth depth)
- {
--	uint32_t value = dal_read_reg(xfm110->base.ctx,
-+	uint32_t value = dm_read_reg(xfm110->base.ctx,
- 			DCP_REG(mmDENORM_CONTROL));
- 
- 	switch (depth) {
-@@ -755,7 +755,7 @@ static void set_denormalization(
- 		break;
- 	}
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			DCP_REG(mmDENORM_CONTROL),
- 			value);
- 
-@@ -771,7 +771,7 @@ bool dce110_transform_set_pixel_storage_depth(
- 	uint32_t value;
- 	enum dc_color_depth color_depth;
- 
--	value = dal_read_reg(
-+	value = dm_read_reg(
- 			xfm->ctx,
- 			LB_REG(mmLB_DATA_FORMAT));
- 	switch (depth) {
-@@ -806,7 +806,7 @@ bool dce110_transform_set_pixel_storage_depth(
- 				bit_depth_params);
- 
- 		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
--		dal_write_reg(
-+		dm_write_reg(
- 				xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
- 		if (!(xfm110->lb_pixel_depth_supported & depth)) {
- 			/*we should use unsupported capabilities
-@@ -836,7 +836,7 @@ bool dce110_transform_power_up_line_buffer(struct transform *xfm)
- 	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- 	uint32_t value;
- 
--	value = dal_read_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-+	value = dm_read_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
- 
- 	/*Use all three pieces of memory always*/
- 	set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
-@@ -844,7 +844,7 @@ bool dce110_transform_power_up_line_buffer(struct transform *xfm)
- 	set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LB_MEMORY_CTRL,
- 			LB_MEMORY_SIZE);
- 
--	dal_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-+	dm_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-index bb3b3cc..05309c9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "dce110_transform.h"
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -76,7 +76,7 @@ static void program_gamut_remap(
- 	uint32_t addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
- 
- 	/* the register controls ovl also */
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	if (reg_val) {
- 		{
-@@ -96,7 +96,7 @@ static void program_gamut_remap(
- 				GAMUT_REMAP_C11_C12,
- 				GAMUT_REMAP_C12);
- 
--			dal_write_reg(ctx, addr, reg_data);
-+			dm_write_reg(ctx, addr, reg_data);
- 		}
- 		{
- 			uint32_t reg_data = 0;
-@@ -116,7 +116,7 @@ static void program_gamut_remap(
- 				GAMUT_REMAP_C13_C14,
- 				GAMUT_REMAP_C14);
- 
--			dal_write_reg(ctx, addr, reg_data);
-+			dm_write_reg(ctx, addr, reg_data);
- 		}
- 		{
- 			uint32_t reg_data = 0;
-@@ -136,7 +136,7 @@ static void program_gamut_remap(
- 				GAMUT_REMAP_C21_C22,
- 				GAMUT_REMAP_C22);
- 
--			dal_write_reg(ctx, addr, reg_data);
-+			dm_write_reg(ctx, addr, reg_data);
- 		}
- 		{
- 			uint32_t reg_data = 0;
-@@ -156,7 +156,7 @@ static void program_gamut_remap(
- 				GAMUT_REMAP_C23_C24,
- 				GAMUT_REMAP_C24);
- 
--			dal_write_reg(ctx, addr, reg_data);
-+			dm_write_reg(ctx, addr, reg_data);
- 		}
- 		{
- 			uint32_t reg_data = 0;
-@@ -176,7 +176,7 @@ static void program_gamut_remap(
- 				GAMUT_REMAP_C31_C32,
- 				GAMUT_REMAP_C32);
- 
--			dal_write_reg(ctx, addr, reg_data);
-+			dm_write_reg(ctx, addr, reg_data);
- 		}
- 		{
- 			uint32_t reg_data = 0;
-@@ -196,7 +196,7 @@ static void program_gamut_remap(
- 				GAMUT_REMAP_C33_C34,
- 				GAMUT_REMAP_C34);
- 
--			dal_write_reg(ctx, addr, reg_data);
-+			dm_write_reg(ctx, addr, reg_data);
- 		}
- 
- 		set_reg_field_value(
-@@ -213,7 +213,7 @@ static void program_gamut_remap(
- 			GRPH_GAMUT_REMAP_MODE);
- 
- 	addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index 4ba14c2..7c15a13 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -45,7 +45,7 @@ static void disable_enhanced_sharpness(struct dce110_transform *xfm110)
- {
- 	uint32_t  value;
- 
--	value = dal_read_reg(xfm110->base.ctx,
-+	value = dm_read_reg(xfm110->base.ctx,
- 			SCL_REG(mmSCL_F_SHARP_CONTROL));
- 
- 	set_reg_field_value(value, 0,
-@@ -60,7 +60,7 @@ static void disable_enhanced_sharpness(struct dce110_transform *xfm110)
- 	set_reg_field_value(value, 0,
- 			SCL_F_SHARP_CONTROL, SCL_VF_SHARP_SCALE_FACTOR);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			SCL_REG(mmSCL_F_SHARP_CONTROL), value);
- }
- 
-@@ -89,7 +89,7 @@ static bool setup_scaling_configuration(
- 
- 	{
- 		addr = SCL_REG(mmSCL_MODE);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		if (data->dal_pixel_format <= PIXEL_FORMAT_GRPH_END)
- 			set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
-@@ -98,11 +98,11 @@ static bool setup_scaling_configuration(
- 
- 		set_reg_field_value(value, 1, SCL_MODE, SCL_PSCL_EN);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		addr = SCL_REG(mmSCL_TAP_CONTROL);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(value, data->taps.h_taps - 1,
- 				SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-@@ -110,16 +110,16 @@ static bool setup_scaling_configuration(
- 		set_reg_field_value(value, data->taps.v_taps - 1,
- 				SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	{
- 		addr = SCL_REG(mmSCL_CONTROL);
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 		 /* 1 - Replaced out of bound pixels with edge */
- 		set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
- 
- 		/* 1 - Replaced out of bound pixels with the edge pixel. */
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	return true;
-@@ -154,11 +154,11 @@ static void program_overscan(
- 	set_reg_field_value(overscan_top_bottom, overscan->bottom,
- 			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			SCL_REG(mmEXT_OVERSCAN_LEFT_RIGHT),
- 			overscan_left_right);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			SCL_REG(mmEXT_OVERSCAN_TOP_BOTTOM),
- 			overscan_top_bottom);
- }
-@@ -175,7 +175,7 @@ static void program_two_taps_filter(
- 	 */
- 	if (vertical) {
- 		addr = SCL_REG(mmSCL_VERT_FILTER_CONTROL);
--		value = dal_read_reg(xfm110->base.ctx, addr);
-+		value = dm_read_reg(xfm110->base.ctx, addr);
- 		set_reg_field_value(
- 			value,
- 			enable ? 1 : 0,
-@@ -184,7 +184,7 @@ static void program_two_taps_filter(
- 
- 	} else {
- 		addr = SCL_REG(mmSCL_HORZ_FILTER_CONTROL);
--		value = dal_read_reg(xfm110->base.ctx, addr);
-+		value = dm_read_reg(xfm110->base.ctx, addr);
- 		set_reg_field_value(
- 			value,
- 			enable ? 1 : 0,
-@@ -192,7 +192,7 @@ static void program_two_taps_filter(
- 			SCL_H_2TAP_HARDCODE_COEF_EN);
- 	}
- 
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- }
- 
- static void set_coeff_update_complete(struct dce110_transform *xfm110)
-@@ -200,10 +200,10 @@ static void set_coeff_update_complete(struct dce110_transform *xfm110)
- 	uint32_t value;
- 	uint32_t addr = SCL_REG(mmSCL_UPDATE);
- 
--	value = dal_read_reg(xfm110->base.ctx, addr);
-+	value = dm_read_reg(xfm110->base.ctx, addr);
- 	set_reg_field_value(value, 1,
- 			SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- }
- 
- static void program_filter(
-@@ -231,30 +231,30 @@ static void program_filter(
- 	uint32_t pwr_ctrl_off;
- 
- 	addr = DCFE_REG(mmDCFE_MEM_PWR_CTRL);
--	pwr_ctrl_orig = dal_read_reg(xfm110->base.ctx, addr);
-+	pwr_ctrl_orig = dm_read_reg(xfm110->base.ctx, addr);
- 	pwr_ctrl_off = pwr_ctrl_orig;
- 	set_reg_field_value(
- 		pwr_ctrl_off,
- 		1,
- 		DCFE_MEM_PWR_CTRL,
- 		SCL_COEFF_MEM_PWR_DIS);
--	dal_write_reg(xfm110->base.ctx, addr, pwr_ctrl_off);
-+	dm_write_reg(xfm110->base.ctx, addr, pwr_ctrl_off);
- 
- 	addr = DCFE_REG(mmDCFE_MEM_PWR_STATUS);
- 	/* Wait to disable gating: */
- 	for (i = 0;
- 		i < 10 &&
- 		get_reg_field_value(
--			dal_read_reg(xfm110->base.ctx, addr),
-+			dm_read_reg(xfm110->base.ctx, addr),
- 			DCFE_MEM_PWR_STATUS,
- 			SCL_COEFF_MEM_PWR_STATE);
- 		i++)
--		dc_service_delay_in_microseconds(xfm110->base.ctx, 1);
-+		dm_delay_in_microseconds(xfm110->base.ctx, 1);
- 
- 	ASSERT(i < 10);
- 
- 	select_addr = SCL_REG(mmSCL_COEF_RAM_SELECT);
--	select = dal_read_reg(xfm110->base.ctx, select_addr);
-+	select = dm_read_reg(xfm110->base.ctx, select_addr);
- 
- 	set_reg_field_value(
- 		select,
-@@ -292,7 +292,7 @@ static void program_filter(
- 				pair,
- 				SCL_COEF_RAM_SELECT,
- 				SCL_C_RAM_TAP_PAIR_IDX);
--			dal_write_reg(xfm110->base.ctx, select_addr, select);
-+			dm_write_reg(xfm110->base.ctx, select_addr, select);
- 
- 			/* even tap write enable */
- 			set_reg_field_value(
-@@ -341,7 +341,7 @@ static void program_filter(
- 				array_idx += 2;
- 			}
- 
--			dal_write_reg(
-+			dm_write_reg(
- 				xfm110->base.ctx,
- 				SCL_REG(mmSCL_COEF_RAM_TAP_DATA),
- 				data);
-@@ -351,7 +351,7 @@ static void program_filter(
- 	ASSERT(coeffs_num == array_idx);
- 
- 	/* reset the power gating register */
--	dal_write_reg(
-+	dm_write_reg(
- 		xfm110->base.ctx,
- 		DCFE_REG(mmDCFE_MEM_PWR_CTRL),
- 		pwr_ctrl_orig);
-@@ -505,7 +505,7 @@ static void program_viewport(
- 	uint32_t addr = 0;
- 
- 	addr = SCL_REG(mmVIEWPORT_START);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		view_port->x,
-@@ -516,10 +516,10 @@ static void program_viewport(
- 		view_port->y,
- 		VIEWPORT_START,
- 		VIEWPORT_Y_START);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = SCL_REG(mmVIEWPORT_SIZE);
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		view_port->height,
-@@ -530,7 +530,7 @@ static void program_viewport(
- 		view_port->width,
- 		VIEWPORT_SIZE,
- 		VIEWPORT_WIDTH);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	/* TODO: add stereo support */
- }
-@@ -598,7 +598,7 @@ static void program_scl_ratios_inits(
- 		inits->h_int_scale_ratio,
- 		SCL_HORZ_FILTER_SCALE_RATIO,
- 		SCL_H_SCALE_RATIO);
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- 
- 	addr = SCL_REG(mmSCL_VERT_FILTER_SCALE_RATIO);
- 	value = 0;
-@@ -607,7 +607,7 @@ static void program_scl_ratios_inits(
- 		inits->v_int_scale_ratio,
- 		SCL_VERT_FILTER_SCALE_RATIO,
- 		SCL_V_SCALE_RATIO);
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- 
- 	addr = SCL_REG(mmSCL_HORZ_FILTER_INIT);
- 	value = 0;
-@@ -621,7 +621,7 @@ static void program_scl_ratios_inits(
- 		inits->h_init.fraction,
- 		SCL_HORZ_FILTER_INIT,
- 		SCL_H_INIT_FRAC);
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- 
- 	addr = SCL_REG(mmSCL_VERT_FILTER_INIT);
- 	value = 0;
-@@ -635,7 +635,7 @@ static void program_scl_ratios_inits(
- 		inits->v_init.fraction,
- 		SCL_VERT_FILTER_INIT,
- 		SCL_V_INIT_FRAC);
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- 
- 	if (inits->bottom_enable) {
- 		addr = SCL_REG(mmSCL_VERT_FILTER_INIT_BOT);
-@@ -650,7 +650,7 @@ static void program_scl_ratios_inits(
- 			inits->v_init_bottom.fraction,
- 			SCL_VERT_FILTER_INIT_BOT,
- 			SCL_V_INIT_FRAC_BOT);
--		dal_write_reg(xfm110->base.ctx, addr, value);
-+		dm_write_reg(xfm110->base.ctx, addr, value);
- 	}
- 
- 	addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
-@@ -665,7 +665,7 @@ static void program_scl_ratios_inits(
- 		0,
- 		SCL_AUTOMATIC_MODE_CONTROL,
- 		SCL_H_CALC_AUTO_RATIO_EN);
--	dal_write_reg(xfm110->base.ctx, addr, value);
-+	dm_write_reg(xfm110->base.ctx, addr, value);
- }
- 
- static void get_viewport(
-@@ -678,8 +678,8 @@ static void get_viewport(
- 	if (current_view_port == NULL)
- 		return;
- 
--	value_start = dal_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_START));
--	value_size = dal_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_SIZE));
-+	value_start = dm_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_START));
-+	value_size = dm_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_SIZE));
- 
- 	current_view_port->x = get_reg_field_value(
- 			value_start,
-@@ -710,14 +710,14 @@ bool dce110_transform_set_scaler(
- 
- 	{
- 		uint32_t addr = SCL_REG(mmSCL_BYPASS_CONTROL);
--		uint32_t value = dal_read_reg(xfm->ctx, addr);
-+		uint32_t value = dm_read_reg(xfm->ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
- 			0,
- 			SCL_BYPASS_CONTROL,
- 			SCL_BYPASS_MODE);
--		dal_write_reg(xfm->ctx, addr, value);
-+		dm_write_reg(xfm->ctx, addr, value);
- 	}
- 
- 	disable_enhanced_sharpness(xfm110);
-@@ -774,10 +774,10 @@ void dce110_transform_set_scaler_bypass(struct transform *xfm)
- 
- 	disable_enhanced_sharpness(xfm110);
- 
--	sclv_mode = dal_read_reg(xfm->ctx, SCL_REG(mmSCL_MODE));
-+	sclv_mode = dm_read_reg(xfm->ctx, SCL_REG(mmSCL_MODE));
- 	set_reg_field_value(sclv_mode, 0, SCL_MODE, SCL_MODE);
- 	set_reg_field_value(sclv_mode, 0, SCL_MODE, SCL_PSCL_EN);
--	dal_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
-+	dm_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
- }
- 
- bool dce110_transform_update_viewport(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-index 9b25ed7..1968296 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-@@ -22,7 +22,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -101,7 +101,7 @@ static void program_viewport(
- 			luma_view_port->y,
- 			SCLV_VIEWPORT_START,
- 			VIEWPORT_Y_START);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 
- 		addr = mmSCLV_VIEWPORT_SIZE;
- 		value = 0;
-@@ -115,7 +115,7 @@ static void program_viewport(
- 			luma_view_port->width,
- 			SCLV_VIEWPORT_SIZE,
- 			VIEWPORT_WIDTH);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	if (chroma_view_port->width != 0 && chroma_view_port->height != 0) {
-@@ -131,7 +131,7 @@ static void program_viewport(
- 			chroma_view_port->y,
- 			SCLV_VIEWPORT_START_C,
- 			VIEWPORT_Y_START_C);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 
- 		addr = mmSCLV_VIEWPORT_SIZE_C;
- 		value = 0;
-@@ -145,7 +145,7 @@ static void program_viewport(
- 			chroma_view_port->width,
- 			SCLV_VIEWPORT_SIZE_C,
- 			VIEWPORT_WIDTH_C);
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 	/* TODO: add stereo support */
- }
-@@ -211,10 +211,10 @@ static bool setup_scaling_configuration(
- 		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
- 		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
- 	}
--	dal_write_reg(ctx, mmSCLV_MODE, value);
-+	dm_write_reg(ctx, mmSCLV_MODE, value);
- 
- 	{
--		value = dal_read_reg(ctx, mmSCLV_TAP_CONTROL);
-+		value = dm_read_reg(ctx, mmSCLV_TAP_CONTROL);
- 
- 		set_reg_field_value(value, data->taps.h_taps - 1,
- 				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-@@ -228,19 +228,19 @@ static bool setup_scaling_configuration(
- 		set_reg_field_value(value, data->taps.v_taps_c - 1,
- 				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
- 
--		dal_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
-+		dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
- 	}
- 
- 	{
- 		/* we can ignore this register because we are ok with hw
- 		 * default 0 -- change to 1 according to dal2 code*/
--		value = dal_read_reg(ctx, mmSCLV_CONTROL);
-+		value = dm_read_reg(ctx, mmSCLV_CONTROL);
- 		 /* 0 - Replaced out of bound pixels with black pixel
- 		  * (or any other required color) */
- 		set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
- 
- 		/* 1 - Replaced out of bound pixels with the edge pixel. */
--		dal_write_reg(ctx, mmSCLV_CONTROL, value);
-+		dm_write_reg(ctx, mmSCLV_CONTROL, value);
- 	}
- 
- 	return is_scaling_needed;
-@@ -275,11 +275,11 @@ static void program_overscan(
- 	set_reg_field_value(overscan_top_bottom, overscan->bottom,
- 		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			mmSCLV_EXT_OVERSCAN_LEFT_RIGHT,
- 			overscan_left_right);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			mmSCLV_EXT_OVERSCAN_TOP_BOTTOM,
- 			overscan_top_bottom);
- }
-@@ -310,7 +310,7 @@ static void program_two_taps_filter_horz(
- 				SCLV_HORZ_FILTER_CONTROL,
- 				SCL_H_2TAP_HARDCODE_COEF_EN);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			mmSCLV_HORZ_FILTER_CONTROL,
- 			value);
- }
-@@ -325,7 +325,7 @@ static void program_two_taps_filter_vert(
- 		set_reg_field_value(value, 1, SCLV_VERT_FILTER_CONTROL,
- 				SCL_V_2TAP_HARDCODE_COEF_EN);
- 
--	dal_write_reg(xfm110->base.ctx,
-+	dm_write_reg(xfm110->base.ctx,
- 			mmSCLV_VERT_FILTER_CONTROL,
- 			value);
- }
-@@ -384,58 +384,58 @@ static void program_scl_ratios_inits(
- {
- 	struct dc_context *ctx = xfm110->base.ctx;
- 	uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;
--	uint32_t value = dal_read_reg(ctx, addr);
-+	uint32_t value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
- 		inits->h_int_scale_ratio_luma,
- 		SCLV_HORZ_FILTER_SCALE_RATIO,
- 		SCL_H_SCALE_RATIO);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = mmSCLV_VERT_FILTER_SCALE_RATIO;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		inits->v_int_scale_ratio_luma,
- 		SCLV_VERT_FILTER_SCALE_RATIO,
- 		SCL_V_SCALE_RATIO);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		inits->h_int_scale_ratio_chroma,
- 		SCLV_HORZ_FILTER_SCALE_RATIO_C,
- 		SCL_H_SCALE_RATIO_C);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- 	addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C;
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
- 		inits->v_int_scale_ratio_chroma,
- 		SCLV_VERT_FILTER_SCALE_RATIO_C,
- 		SCL_V_SCALE_RATIO_C);
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- void dce110_transform_underlay_set_scalerv_bypass(struct transform *xfm)
- {
- 	uint32_t addr = mmSCLV_MODE;
--	uint32_t value = dal_read_reg(xfm->ctx, addr);
-+	uint32_t value = dm_read_reg(xfm->ctx, addr);
- 
- 	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
- 	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
- 	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
- 	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
--	dal_write_reg(xfm->ctx, addr, value);
-+	dm_write_reg(xfm->ctx, addr, value);
- }
- 
- bool dce110_transform_underlay_is_scaling_enabled(struct transform *xfm)
- {
--	uint32_t value = dal_read_reg(xfm->ctx, mmSCLV_MODE);
-+	uint32_t value = dm_read_reg(xfm->ctx, mmSCLV_MODE);
- 	uint8_t scl_mode = get_reg_field_value(value, SCLV_MODE, SCL_MODE);
- 
- 	return scl_mode == 0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-new file mode 100644
-index 0000000..b6ce510
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * This file defines helper functions provided by the Display Manager to
-+ * Display Core.
-+ */
-+#ifndef __DM_HELPERS__
-+#define __DM_HELPERS__
-+
-+#include "dc_types.h"
-+#include "dc.h"
-+
-+struct dp_mst_stream_allocation_table;
-+
-+enum dc_edid_status dm_helpers_parse_edid_caps(
-+	struct dc_context *ctx,
-+	const struct dc_edid *edid,
-+	struct dc_edid_caps *edid_caps);
-+
-+/*
-+ * Writes payload allocation table in immediate downstream device.
-+ */
-+bool dm_helpers_dp_mst_write_payload_allocation_table(
-+		struct dc_context *ctx,
-+		const struct dc_stream *stream,
-+		struct dp_mst_stream_allocation_table *proposed_table,
-+		bool enable);
-+
-+/*
-+ * Polls for ACT (allocation change trigger) handled and
-+ */
-+bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		struct dc_context *ctx,
-+		const struct dc_stream *stream);
-+/*
-+ * Sends ALLOCATE_PAYLOAD message.
-+ */
-+bool dm_helpers_dp_mst_send_payload_allocation(
-+		struct dc_context *ctx,
-+		const struct dc_stream *stream,
-+		bool enable);
-+
-+void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(
-+		void *param);
-+
-+bool dm_helpers_dp_mst_start_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		bool boot);
-+
-+void dm_helpers_dp_mst_stop_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link);
-+
-+/**
-+ * OS specific aux read callback.
-+ */
-+bool dm_helper_dp_read_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size);
-+
-+/**
-+ * OS specific aux write callback.
-+ */
-+bool dm_helper_dp_write_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t size);
-+
-+#endif /* __DM_HELPERS__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-new file mode 100644
-index 0000000..4112eda
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -0,0 +1,476 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * This file defines external dependencies of Display Core.
-+ */
-+
-+#ifndef __DM_SERVICES_H__
-+
-+#define __DM_SERVICES_H__
-+
-+/* TODO: remove when DC is complete. */
-+#include "dm_services_types.h"
-+#include "logger_interface.h"
-+#include "include/dal_types.h"
-+#include "irq_types.h"
-+#include "link_service_types.h"
-+
-+#undef DEPRECATED
-+
-+/* if the pointer is not NULL, the allocated memory is zeroed */
-+void *dm_alloc(struct dc_context *ctx, uint32_t size);
-+
-+/* reallocate memory. The contents will remain unchanged.*/
-+void *dm_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
-+
-+void dm_free(struct dc_context *ctx, void *p);
-+
-+void dm_memset(void *p, int32_t c, uint32_t count);
-+
-+void dm_memmove(void *dst, const void *src, uint32_t size);
-+
-+int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
-+
-+int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
-+
-+irq_handler_idx dm_register_interrupt(
-+	struct dc_context *ctx,
-+	struct dc_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *handler_args);
-+
-+void dm_unregister_interrupt(
-+	struct dc_context *ctx,
-+	enum dc_irq_source irq_source,
-+	irq_handler_idx handler_idx);
-+
-+/*
-+ *
-+ * GPU registers access
-+ *
-+ */
-+static inline uint32_t dm_read_reg(
-+	const struct dc_context *ctx,
-+	uint32_t address)
-+{
-+	uint32_t value = cgs_read_register(ctx->cgs_device, address);
-+
-+#if defined(__DAL_REGISTER_LOGGER__)
-+	if (true == dal_reg_logger_should_dump_register()) {
-+		dal_reg_logger_rw_count_increment();
-+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+	}
-+#endif
-+	return value;
-+}
-+
-+static inline void dm_write_reg(
-+	const struct dc_context *ctx,
-+	uint32_t address,
-+	uint32_t value)
-+{
-+#if defined(__DAL_REGISTER_LOGGER__)
-+	if (true == dal_reg_logger_should_dump_register()) {
-+		dal_reg_logger_rw_count_increment();
-+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+	}
-+#endif
-+	cgs_write_register(ctx->cgs_device, address, value);
-+}
-+
-+static inline uint32_t dm_read_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index)
-+{
-+	return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
-+}
-+
-+static inline void dm_write_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index,
-+	uint32_t value)
-+{
-+	cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
-+}
-+
-+static inline uint32_t get_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (mask & reg_value) >> shift;
-+}
-+
-+#define get_reg_field_value(reg_value, reg_name, reg_field)\
-+	get_reg_field_value_ex(\
-+		(reg_value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline uint32_t set_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (reg_value & ~mask) | (mask & (value << shift));
-+}
-+
-+#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
-+	(reg_value) = set_reg_field_value_ex(\
-+		(reg_value),\
-+		(value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+/*
-+ * atombios services
-+ */
-+
-+bool dm_exec_bios_cmd_table(
-+	struct dc_context *ctx,
-+	uint32_t index,
-+	void *params);
-+
-+#ifdef BUILD_DAL_TEST
-+uint32_t dm_bios_cmd_table_para_revision(
-+struct dc_context *ctx,
-+	uint32_t index);
-+
-+bool dm_bios_cmd_table_revision(
-+	struct dc_context *ctx,
-+	uint32_t index,
-+	uint8_t *frev,
-+	uint8_t *crev);
-+#endif
-+
-+#ifndef BUILD_DAL_TEST
-+static inline uint32_t dm_bios_cmd_table_para_revision(
-+	struct dc_context *ctx,
-+	uint32_t index)
-+{
-+	uint8_t frev;
-+	uint8_t crev;
-+
-+	if (cgs_atom_get_cmd_table_revs(
-+			ctx->cgs_device,
-+			index,
-+			&frev,
-+			&crev) != 0)
-+		return 0;
-+
-+	return crev;
-+}
-+#else
-+uint32_t dm_bios_cmd_table_para_revision(
-+		struct dc_context *ctx,
-+		uint32_t index);
-+#endif
-+
-+/**************************************
-+ * Power Play (PP) interfaces
-+ **************************************/
-+
-+enum dal_to_power_clocks_state {
-+	PP_CLOCKS_STATE_INVALID,
-+	PP_CLOCKS_STATE_ULTRA_LOW,
-+	PP_CLOCKS_STATE_LOW,
-+	PP_CLOCKS_STATE_NOMINAL,
-+	PP_CLOCKS_STATE_PERFORMANCE
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_info {
-+	enum dal_to_power_clocks_state required_clock;
-+	uint32_t min_sclk;
-+	uint32_t min_mclk;
-+	uint32_t min_deep_sleep_sclk;
-+};
-+
-+/* clocks in khz */
-+struct power_to_dal_info {
-+	uint32_t min_sclk;
-+	uint32_t max_sclk;
-+	uint32_t min_mclk;
-+	uint32_t max_mclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_system_clock_range {
-+	uint32_t min_sclk;
-+	uint32_t max_sclk;
-+
-+	uint32_t min_mclk;
-+	uint32_t max_mclk;
-+
-+	uint32_t min_dclk;
-+	uint32_t max_dclk;
-+
-+	/* Wireless Display */
-+	uint32_t min_eclk;
-+	uint32_t max_eclk;
-+};
-+
-+/* clocks in khz */
-+struct dal_to_power_dclk {
-+	uint32_t optimal; /* input: best optimizes for stutter efficiency */
-+	uint32_t minimal; /* input: the lowest clk that DAL can support */
-+	uint32_t established; /* output: the actually set one */
-+};
-+
-+/* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-+ * This is done *before* it changes DCE clock.
-+ *
-+ * If required clock is higher than current, then PP will increase the voltage.
-+ *
-+ * If required clock is lower than current, then PP will defer reduction of
-+ * voltage until the call to dc_service_pp_post_dce_clock_change().
-+ *
-+ * \input - Contains clocks needed for Mode Set.
-+ *
-+ * \output - Contains clocks adjusted by PP which DAL should use for Mode Set.
-+ *		Valid only if function returns zero.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dm_pp_pre_dce_clock_change(
-+	struct dc_context *ctx,
-+	struct dal_to_power_info *input,
-+	struct power_to_dal_info *output);
-+
-+struct dc_pp_single_disp_config {
-+	enum signal_type signal;
-+	uint8_t transmitter;
-+	uint8_t ddi_channel_mapping;
-+	uint8_t pipe_idx;
-+	uint32_t src_height;
-+	uint32_t src_width;
-+	uint32_t v_refresh;
-+	uint32_t sym_clock; /* HDMI only */
-+	struct link_settings link_settings; /* DP only */
-+};
-+
-+struct dc_pp_display_configuration {
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+
-+	uint32_t min_memory_clock_khz;
-+	uint32_t min_engine_clock_khz;
-+	uint32_t min_engine_clock_deep_sleep_khz;
-+
-+	uint32_t avail_mclk_switch_time_us;
-+	uint32_t avail_mclk_switch_time_in_disp_active_us;
-+
-+	uint32_t disp_clk_khz;
-+
-+	bool all_displays_in_sync;
-+
-+	uint8_t display_count;
-+	struct dc_pp_single_disp_config disp_configs[3];
-+
-+	/*Controller Index of primary display - used in MCLK SMC switching hang
-+	 * SW Workaround*/
-+	uint8_t crtc_index;
-+	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+	uint32_t line_time_in_us;
-+};
-+
-+enum dc_pp_clocks_state {
-+	DC_PP_CLOCKS_STATE_INVALID = 0,
-+	DC_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DC_PP_CLOCKS_STATE_LOW,
-+	DC_PP_CLOCKS_STATE_NOMINAL,
-+	DC_PP_CLOCKS_STATE_PERFORMANCE,
-+
-+	/* Starting from DCE11, Max 8 levels of DPM state supported. */
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DC_PP_CLOCKS_STATE_INVALID,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_0 = DC_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_1 = DC_PP_CLOCKS_STATE_LOW,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_2 = DC_PP_CLOCKS_STATE_NOMINAL,
-+	/* to be backward compatible */
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_3 = DC_PP_CLOCKS_STATE_PERFORMANCE,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_4 = DC_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_5 = DC_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_6 = DC_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
-+	DC_PP_CLOCKS_DPM_STATE_LEVEL_7 = DC_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
-+};
-+
-+struct dc_pp_static_clock_info {
-+	uint32_t max_sclk_khz;
-+	uint32_t max_mclk_khz;
-+
-+	 /* max possible display block clocks state */
-+	enum dc_pp_clocks_state max_clocks_state;
-+};
-+
-+/* The returned clocks range are 'static' system clocks which will be used for
-+ * mode validation purposes.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dc_service_get_system_clocks_range(
-+	const struct dc_context *ctx,
-+	struct dal_system_clock_range *sys_clks);
-+
-+enum dc_pp_clock_type {
-+	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-+	DC_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
-+	DC_PP_CLOCK_TYPE_MEMORY_CLK
-+};
-+
-+#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
-+	(clk_type) == DC_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
-+	(clk_type) == DC_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-+	(clk_type) == DC_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
-+
-+#define DC_PP_MAX_CLOCK_LEVELS 8
-+
-+struct dc_pp_clock_levels {
-+	uint32_t num_levels;
-+	uint32_t clocks_in_khz[DC_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+/* Gets valid clocks levels from pplib
-+ *
-+ * input: clk_type - display clk / sclk / mem clk
-+ *
-+ * output: array of valid clock levels for given type in ascending order,
-+ * with invalid levels filtered out
-+ *
-+ */
-+bool dm_pp_get_clock_levels_by_type(
-+	const struct dc_context *ctx,
-+	enum dc_pp_clock_type clk_type,
-+	struct dc_pp_clock_levels *clk_level_info);
-+
-+
-+bool dm_pp_apply_safe_state(
-+		const struct dc_context *ctx);
-+
-+/* DAL calls this function to notify PP about completion of Mode Set.
-+ * For PP it means that current DCE clocks are those which were returned
-+ * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-+ *
-+ * If the clocks are higher than before, then PP does nothing.
-+ *
-+ * If the clocks are lower than before, then PP reduces the voltage.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dm_pp_apply_display_requirements(
-+	const struct dc_context *ctx,
-+	const struct dc_pp_display_configuration *pp_display_cfg);
-+
-+
-+/****** end of PP interfaces ******/
-+
-+void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
-+
-+void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds);
-+
-+enum platform_method {
-+	PM_GET_AVAILABLE_METHODS = 1 << 0,
-+	PM_GET_LID_STATE = 1 << 1,
-+	PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2
-+};
-+
-+struct platform_info_params {
-+	enum platform_method method;
-+	void *data;
-+};
-+
-+struct platform_info_brightness_caps {
-+	uint8_t ac_level_percentage;
-+	uint8_t dc_level_percentage;
-+};
-+
-+struct platform_info_ext_brightness_caps {
-+	struct platform_info_brightness_caps basic_caps;
-+	struct data_point {
-+		uint8_t luminance;
-+		uint8_t	signal_level;
-+	} data_points[99];
-+
-+	uint8_t	data_points_num;
-+	uint8_t	min_input_signal;
-+	uint8_t	max_input_signal;
-+};
-+
-+bool dm_get_platform_info(
-+	struct dc_context *ctx,
-+	struct platform_info_params *params);
-+
-+/*
-+ *
-+ * print-out services
-+ *
-+ */
-+#define dm_log_to_buffer(buffer, size, fmt, args)\
-+	vsnprintf(buffer, size, fmt, args)
-+
-+long dm_get_pid(void);
-+long dm_get_tgid(void);
-+
-+/*
-+ *
-+ * general debug capabilities
-+ *
-+ */
-+#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
-+
-+#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
-+#define ASSERT_CRITICAL(expr) do {	\
-+	if (WARN_ON(!(expr))) { \
-+		kgdb_breakpoint(); \
-+	} \
-+} while (0)
-+#else
-+#define ASSERT_CRITICAL(expr) do {	\
-+	if (WARN_ON(!(expr))) { \
-+		; \
-+	} \
-+} while (0)
-+#endif
-+
-+#if defined(CONFIG_DEBUG_KERNEL_DAL)
-+#define ASSERT(expr) ASSERT_CRITICAL(expr)
-+
-+#else
-+#define ASSERT(expr) WARN_ON(!(expr))
-+#endif
-+
-+#define BREAK_TO_DEBUGGER() ASSERT(0)
-+
-+#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
-+
-+#endif /* __DM_SERVICES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-new file mode 100644
-index 0000000..bc458aa
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -0,0 +1,167 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DM_SERVICES_TYPES_H__
-+#define __DM_SERVICES_TYPES_H__
-+
-+#define INVALID_DISPLAY_INDEX 0xffffffff
-+
-+#if defined __KERNEL__
-+
-+#include <asm/byteorder.h>
-+#include <linux/types.h>
-+#include <drm/drmP.h>
-+
-+#include "cgs_linux.h"
-+
-+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
-+#define BIGENDIAN_CPU
-+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
-+#define LITTLEENDIAN_CPU
-+#endif
-+
-+#undef READ
-+#undef WRITE
-+#undef FRAME_SIZE
-+
-+#define dm_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
-+
-+#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-+
-+#define dm_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-+
-+#define dm_vlog(fmt, args) vprintk(fmt, args)
-+
-+#define dm_min(x, y) min(x, y)
-+#define dm_max(x, y) max(x, y)
-+
-+#elif defined BUILD_DAL_TEST
-+
-+#include <inttypes.h>
-+#include <stdlib.h>
-+#include <string.h>
-+
-+#include <stdio.h>
-+
-+#include <stdarg.h>
-+
-+#include "cgs_linux.h"
-+
-+#define LONG_MAX	((long)(~0UL>>1))
-+#define LONG_MIN	(-LONG_MAX - 1)
-+#define LLONG_MAX	((long long)(~0ULL>>1))
-+#define LLONG_MIN	(-LLONG_MAX - 1)
-+#define UINT_MAX	(~0U)
-+
-+typedef _Bool bool;
-+enum { false, true };
-+
-+#ifndef NULL
-+#define NULL ((void *)0)
-+#endif
-+
-+#define LITTLEENDIAN_CPU 1
-+
-+#include <test_context.h>
-+
-+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-+
-+#define container_of(ptr, type, member) \
-+	((type *)((char *)(ptr) - offsetof(type, member)))
-+
-+#define dal_test_not_implemented() \
-+	printf("[DAL_TEST_NOT_IMPL]:%s\n", __func__)
-+
-+#define dm_output_to_console(fmt, ...) do { \
-+	printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
-+	while (false)
-+
-+#define dm_error(fmt, ...) printf("[DAL_ERROR]" fmt, ##__VA_ARGS__)
-+
-+#define dm_output_to_console(fmt, ...) do { \
-+			printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
-+				while (false)
-+
-+
-+#define dm_debug(fmt, ...) printf("[DAL_DBG]" fmt, ##__VA_ARGS__)
-+
-+#define dm_vlog(fmt, args) vprintf(fmt, args)
-+
-+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-+
-+#define dm_min(x, y) ({\
-+	typeof(x) _min1 = (x);\
-+	typeof(y) _min2 = (y);\
-+	(void) (&_min1 == &_min2);\
-+	_min1 < _min2 ? _min1 : _min2; })
-+
-+#define dm_max(x, y) ({\
-+	typeof(x) _max1 = (x);\
-+	typeof(y) _max2 = (y);\
-+	(void) (&_max1 == &_max2);\
-+	_max1 > _max2 ? _max1 : _max2; })
-+
-+/* division functions */
-+
-+static inline int64_t div64_s64(int64_t x, int64_t y)
-+{
-+	return x / y;
-+}
-+
-+static inline uint64_t div64_u64(uint64_t x, uint64_t y)
-+{
-+	return x / y;
-+}
-+
-+static inline uint64_t div_u64(uint64_t x, uint32_t y)
-+{
-+	return x / y;
-+}
-+
-+static inline uint64_t div64_u64_rem(uint64_t x, uint64_t y, uint64_t *rem)
-+{
-+	if (rem)
-+		*rem = x % y;
-+	return x / y;
-+}
-+
-+static inline uint64_t div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem)
-+{
-+	if (rem)
-+		*rem = x % y;
-+	return x / y;
-+}
-+
-+#define cpu_to_le16(do_nothing) do_nothing
-+
-+#define le16_to_cpu(do_nothing) do_nothing
-+
-+#define cpu_to_le32(do_nothing) do_nothing
-+
-+#define le32_to_cpu(do_nothing) do_nothing
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-index b8554aa..8ff899c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "../hw_gpio_pin.h"
- #include "../hw_gpio.h"
-@@ -63,7 +62,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dc_service_free((*ptr)->ctx, pin);
-+	dm_free((*ptr)->ctx, pin);
- 
- 	*ptr = NULL;
- }
-@@ -602,7 +601,7 @@ static void setup_i2c_polling(
- {
- 	uint32_t value;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -623,7 +622,7 @@ static void setup_i2c_polling(
- 			DC_I2C_DDC1_SETUP,
- 			DC_I2C_DDC1_EDID_DETECT_MODE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static enum gpio_result set_config(
-@@ -649,7 +648,7 @@ static enum gpio_result set_config(
- 
- 	addr = hw_gpio->pin_reg.DC_GPIO_DATA_MASK.addr;
- 
--	regval = dal_read_reg(ptr->ctx, addr);
-+	regval = dm_read_reg(ptr->ctx, addr);
- 
- 	ddc_data_pd_en = get_reg_field_value(
- 			regval,
-@@ -686,14 +685,14 @@ static enum gpio_result set_config(
- 					DC_GPIO_DDC1_MASK,
- 					DC_GPIO_DDC1CLK_PD_EN);
- 
--				dal_write_reg(ptr->ctx, addr, regval);
-+				dm_write_reg(ptr->ctx, addr, regval);
- 
- 				if (config_data->type ==
- 					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dc_service_sleep_in_milliseconds(ptr->ctx, 3);
-+					dm_sleep_in_milliseconds(ptr->ctx, 3);
- 			}
- 		} else {
- 			uint32_t reg2 = regval;
-@@ -713,27 +712,27 @@ static enum gpio_result set_config(
- 			if (sda_pd_dis) {
- 				sda_pd_dis = 0;
- 
--				dal_write_reg(ptr->ctx, addr, reg2);
-+				dm_write_reg(ptr->ctx, addr, reg2);
- 
- 				if (config_data->type ==
- 					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dc_service_sleep_in_milliseconds(ptr->ctx, 3);
-+					dm_sleep_in_milliseconds(ptr->ctx, 3);
- 			}
- 
- 			if (!scl_pd_dis) {
- 				scl_pd_dis = 1;
- 
--				dal_write_reg(ptr->ctx, addr, reg2);
-+				dm_write_reg(ptr->ctx, addr, reg2);
- 
- 				if (config_data->type ==
- 					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dc_service_sleep_in_milliseconds(ptr->ctx, 3);
-+					dm_sleep_in_milliseconds(ptr->ctx, 3);
- 			}
- 		}
- 
-@@ -744,12 +743,12 @@ static enum gpio_result set_config(
- 				config_data->config.ddc.clock_en_bit_present)
- 				/* [anaumov] in DAL2, there was
- 				 * dc_service_delay_in_microseconds(2000); */
--				dc_service_sleep_in_milliseconds(ptr->ctx, 2);
-+				dm_sleep_in_milliseconds(ptr->ctx, 2);
- 
- 			/* set the I2C pad mode */
- 			/* read the register again,
- 			 * some bits may have been changed */
--			regval = dal_read_reg(ptr->ctx, addr);
-+			regval = dm_read_reg(ptr->ctx, addr);
- 
- 			set_reg_field_value(
- 				regval,
-@@ -757,7 +756,7 @@ static enum gpio_result set_config(
- 				DC_GPIO_DDC1_MASK,
- 				AUX_PAD1_MODE);
- 
--			dal_write_reg(ptr->ctx, addr, regval);
-+			dm_write_reg(ptr->ctx, addr, regval);
- 		}
- 
- 		return GPIO_RESULT_OK;
-@@ -770,7 +769,7 @@ static enum gpio_result set_config(
- 				DC_GPIO_DDC1_MASK,
- 				AUX_PAD1_MODE);
- 
--			dal_write_reg(ptr->ctx, addr, regval);
-+			dm_write_reg(ptr->ctx, addr, regval);
- 		}
- 
- 		return GPIO_RESULT_OK;
-@@ -865,7 +864,7 @@ struct hw_gpio_pin *dal_hw_ddc_dce110_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_ddc_dce110 *pin = dc_service_alloc(ctx, sizeof(struct hw_ddc_dce110));
-+	struct hw_ddc_dce110 *pin = dm_alloc(ctx, sizeof(struct hw_ddc_dce110));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -877,7 +876,7 @@ struct hw_gpio_pin *dal_hw_ddc_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, pin);
-+	dm_free(ctx, pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-index 6a9ee1a..bdeb601 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/gpio_types.h"
- #include "../hw_factory.h"
- 
-@@ -41,6 +41,7 @@
- #include "../hw_hpd.h"
- 
- #include "hw_factory_dce110.h"
-+
- #include "hw_hpd_dce110.h"
- #include "hw_ddc_dce110.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-index e427f2c..a90115c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "../hw_gpio_pin.h"
- #include "../hw_gpio.h"
-@@ -62,7 +61,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dc_service_free((*ptr)->ctx, pin);
-+	dm_free((*ptr)->ctx, pin);
- 
- 	*ptr = NULL;
- }
-@@ -239,7 +238,7 @@ static enum gpio_result get_value(
- 		uint32_t hpd_delayed = 0;
- 		uint32_t hpd_sense = 0;
- 
--		regval = dal_read_reg(
-+		regval = dm_read_reg(
- 				ptr->ctx,
- 				pin->addr.DC_HPD_INT_STATUS);
- 
-@@ -274,7 +273,7 @@ static enum gpio_result set_config(
- 	{
- 		uint32_t value;
- 
--		value = dal_read_reg(
-+		value = dm_read_reg(
- 			ptr->ctx,
- 			pin->addr.DC_HPD_TOGGLE_FILT_CNTL);
- 
-@@ -290,7 +289,7 @@ static enum gpio_result set_config(
- 			DC_HPD_TOGGLE_FILT_CNTL,
- 			DC_HPD_DISCONNECT_INT_DELAY);
- 
--		dal_write_reg(
-+		dm_write_reg(
- 			ptr->ctx,
- 			pin->addr.DC_HPD_TOGGLE_FILT_CNTL,
- 			value);
-@@ -349,7 +348,7 @@ struct hw_gpio_pin *dal_hw_hpd_dce110_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_hpd_dce110 *pin = dc_service_alloc(ctx, sizeof(struct hw_hpd_dce110));
-+	struct hw_hpd_dce110 *pin = dm_alloc(ctx, sizeof(struct hw_hpd_dce110));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -361,7 +360,7 @@ struct hw_gpio_pin *dal_hw_hpd_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, pin);
-+	dm_free(ctx, pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-index 0c87515..b058f4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/gpio_types.h"
- #include "../hw_translate.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-index ee6a0b0..c3d8cdb 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/gpio_interface.h"
- #include "include/ddc_interface.h"
-@@ -229,7 +229,7 @@ struct ddc *dal_gpio_create_ddc(
- 	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en))
- 		return NULL;
- 
--	ddc = dc_service_alloc(service->ctx, sizeof(struct ddc));
-+	ddc = dm_alloc(service->ctx, sizeof(struct ddc));
- 
- 	if (!ddc) {
- 		BREAK_TO_DEBUGGER();
-@@ -262,7 +262,7 @@ failure_2:
- 	dal_gpio_service_destroy_gpio(&ddc->pin_data);
- 
- failure_1:
--	dc_service_free(service->ctx, ddc);
-+	dm_free(service->ctx, ddc);
- 
- 	return NULL;
- }
-@@ -284,7 +284,7 @@ void dal_gpio_destroy_ddc(
- 	}
- 
- 	destruct(*ddc);
--	dc_service_free((*ddc)->ctx, *ddc);
-+	dm_free((*ddc)->ctx, *ddc);
- 
- 	*ddc = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-index 282f1fc..1dd31d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "../hw_gpio_pin.h"
- #include "../hw_gpio.h"
-@@ -50,7 +49,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dc_service_free((*ptr)->ctx, pin);
-+	dm_free((*ptr)->ctx, pin);
- 
- 	*ptr = NULL;
- }
-@@ -80,7 +79,7 @@ struct hw_gpio_pin *dal_hw_ddc_diag_fpga_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_ddc *pin = dc_service_alloc(ctx, sizeof(struct hw_ddc));
-+	struct hw_ddc *pin = dm_alloc(ctx, sizeof(struct hw_ddc));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -92,7 +91,7 @@ struct hw_gpio_pin *dal_hw_ddc_diag_fpga_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, pin);
-+	dm_free(ctx, pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-index 2349bf7..0690b42 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/gpio_types.h"
- #include "../hw_factory.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-index f47e56a..019e810 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "../hw_gpio_pin.h"
- #include "../hw_gpio.h"
-@@ -48,7 +47,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dc_service_free((*ptr)->ctx, pin);
-+	dm_free((*ptr)->ctx, pin);
- 
- 	*ptr = NULL;
- }
-@@ -84,7 +83,7 @@ struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_hpd *pin = dc_service_alloc(ctx, sizeof(struct hw_hpd));
-+	struct hw_hpd *pin = dm_alloc(ctx, sizeof(struct hw_hpd));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -96,7 +95,7 @@ struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, pin);
-+	dm_free(ctx, pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-index cfcd197..177330a 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-@@ -23,8 +23,7 @@
-  *
-  */
- 
--
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/gpio_types.h"
- 
- #include "../hw_translate.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-index 9168b2c..7e16d63 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/gpio_interface.h"
- #include "include/gpio_service_interface.h"
-@@ -246,7 +246,7 @@ struct gpio *dal_gpio_create(
- 	uint32_t en,
- 	enum gpio_pin_output_state output_state)
- {
--	struct gpio *gpio = dc_service_alloc(service->ctx, sizeof(struct gpio));
-+	struct gpio *gpio = dm_alloc(service->ctx, sizeof(struct gpio));
- 
- 	if (!gpio) {
- 		ASSERT_CRITICAL(false);
-@@ -273,7 +273,7 @@ void dal_gpio_destroy(
- 
- 	dal_gpio_close(*gpio);
- 
--	dc_service_free((*gpio)->service->ctx, *gpio);
-+	dm_free((*gpio)->service->ctx, *gpio);
- 
- 	*gpio = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-index b79653c..6837898 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -27,7 +27,7 @@
-  * Pre-requisites: headers required by header of this unit
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/gpio_interface.h"
- #include "include/ddc_interface.h"
- #include "include/irq_interface.h"
-@@ -68,7 +68,7 @@ struct gpio_service *dal_gpio_service_create(
- 
- 	uint32_t index_of_id;
- 
--	service = dc_service_alloc(ctx, sizeof(struct gpio_service));
-+	service = dm_alloc(ctx, sizeof(struct gpio_service));
- 
- 	if (!service) {
- 		BREAK_TO_DEBUGGER();
-@@ -107,7 +107,7 @@ struct gpio_service *dal_gpio_service_create(
- 			if (number_of_bits) {
- 				uint32_t index_of_uint = 0;
- 
--				slot = dc_service_alloc(
-+				slot = dm_alloc(
- 					ctx,
- 					number_of_uints * sizeof(uint32_t));
- 
-@@ -141,11 +141,11 @@ failure_2:
- 		slot = service->busyness[index_of_id];
- 
- 		if (slot)
--			dc_service_free(ctx, slot);
-+			dm_free(ctx, slot);
- 	};
- 
- failure_1:
--	dc_service_free(ctx, service);
-+	dm_free(ctx, service);
- 
- 	return NULL;
- }
-@@ -243,13 +243,13 @@ void dal_gpio_service_destroy(
- 			uint32_t *slot = (*ptr)->busyness[index_of_id];
- 
- 			if (slot)
--				dc_service_free((*ptr)->ctx, slot);
-+				dm_free((*ptr)->ctx, slot);
- 
- 			++index_of_id;
- 		} while (index_of_id < GPIO_ID_COUNT);
- 	}
- 
--	dc_service_free((*ptr)->ctx, *ptr);
-+	dm_free((*ptr)->ctx, *ptr);
- 
- 	*ptr = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-index e15f3a2..41e46a7 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "hw_gpio_pin.h"
- #include "hw_gpio.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index a5fa3aa..e0f6ecf 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- 
- /*
-@@ -88,7 +87,7 @@ void dal_hw_factory_destroy(
- 		return;
- 	}
- 
--	dc_service_free(ctx, *factory);
-+	dm_free(ctx, *factory);
- 
- 	*factory = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-index 9e231d3..2a2262c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "hw_gpio_pin.h"
- 
-@@ -51,7 +50,7 @@ enum gpio_result dal_hw_gpio_get_reg_value(
- 	const struct addr_mask *reg,
- 	uint32_t *value)
- {
--	*value = dal_read_reg(ctx, reg->addr);
-+	*value = dm_read_reg(ctx, reg->addr);
- 
- 	*value &= reg->mask;
- 
-@@ -70,12 +69,12 @@ enum gpio_result dal_hw_gpio_set_reg_value(
- 		return GPIO_RESULT_INVALID_DATA;
- 	}
- 
--	prev_value = dal_read_reg(ctx, reg->addr);
-+	prev_value = dm_read_reg(ctx, reg->addr);
- 
- 	prev_value &= ~reg->mask;
- 	prev_value |= (value & reg->mask);
- 
--	dal_write_reg(ctx, reg->addr, prev_value);
-+	dm_write_reg(ctx, reg->addr, prev_value);
- 
- 	return GPIO_RESULT_OK;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-index 52757ac..2392f2c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "hw_gpio_pin.h"
- #include "hw_gpio.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-index 0d3f07f..411ad89 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-index 617d648..f072fd5 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- #include "hw_gpio_pin.h"
- #include "hw_gpio.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index 4a894c8..215322e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_types.h"
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-index 04bb69d..debc2ea 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/gpio_interface.h"
- #include "include/irq_interface.h"
- #include "include/gpio_service_interface.h"
-@@ -138,7 +137,7 @@ struct irq *dal_gpio_create_irq(
- 		return NULL;
- 	}
- 
--	irq = dc_service_alloc(service->ctx, sizeof(struct irq));
-+	irq = dm_alloc(service->ctx, sizeof(struct irq));
- 
- 	if (!irq) {
- 		ASSERT_CRITICAL(false);
-@@ -154,7 +153,7 @@ struct irq *dal_gpio_create_irq(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(service->ctx, irq);
-+	dm_free(service->ctx, irq);
- 
- 	return NULL;
- }
-@@ -175,7 +174,7 @@ void dal_gpio_destroy_irq(
- 	}
- 
- 	destruct(*irq);
--	dc_service_free((*irq)->ctx, *irq);
-+	dm_free((*irq)->ctx, *irq);
- 
- 	*irq = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-index 0ed4f06..b3b0f99 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dc_clock_generator.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-index 6edb5aa..4c307f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/logger_interface.h"
- 
-@@ -50,7 +50,7 @@ static void force_hw_base_light_sleep(struct dc_context *ctx)
- 	addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
- 	/* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
- 	 * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 			value,
-@@ -58,7 +58,7 @@ static void force_hw_base_light_sleep(struct dc_context *ctx)
- 			DC_MEM_GLOBAL_PWR_REQ_CNTL,
- 			DC_MEM_GLOBAL_PWR_REQ_DIS);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- 
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 7ff8a74..15243de 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "dce/dce_11_0_d.h"
- #include "dce/dce_11_0_sh_mask.h"
-@@ -165,7 +165,7 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
- 	struct display_clock_dce110 *disp_clk = FROM_DISPLAY_CLOCK(dc);
- 
- 	/* ASSERT DP Reference Clock source is from DFS*/
--	dp_ref_clk_cntl_value = dal_read_reg(dc->ctx,
-+	dp_ref_clk_cntl_value = dm_read_reg(dc->ctx,
- 			mmDPREFCLK_CNTL);
- 
- 	dp_ref_clk_cntl_src_sel_value =
-@@ -177,7 +177,7 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
- 
- 	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
- 	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
--	dispclk_cntl_value = dal_read_reg(dc->ctx,
-+	dispclk_cntl_value = dm_read_reg(dc->ctx,
- 			mmDENTIST_DISPCLK_CNTL);
- 
- 	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
-@@ -233,7 +233,7 @@ static void destroy(struct display_clock **base)
- 
- 	dc110 = DCLCK110_FROM_BASE(*base);
- 
--	dc_service_free((*base)->ctx, dc110);
-+	dm_free((*base)->ctx, dc110);
- 
- 	*base = NULL;
- }
-@@ -652,8 +652,8 @@ static bool display_clock_integrated_info_construct(
- 	struct display_clock *base = &disp_clk->disp_clk_base;
- 	bool res;
- 
--	dc_service_memset(&info, 0, sizeof(struct integrated_info));
--	dc_service_memset(&fw_info, 0, sizeof(struct firmware_info));
-+	dm_memset(&info, 0, sizeof(struct integrated_info));
-+	dm_memset(&fw_info, 0, sizeof(struct firmware_info));
- 
- 	res = dal_adapter_service_get_integrated_info(as, &info);
- 
-@@ -728,7 +728,7 @@ static uint32_t get_clock(struct display_clock *dc)
- 
- 	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
- 	 DID DENTIST_DISPCLK_WDIVIDER.*/
--	value = dal_read_reg(dc->ctx, addr);
-+	value = dm_read_reg(dc->ctx, addr);
- 	field = get_reg_field_value(
- 			value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
- 
-@@ -787,7 +787,7 @@ static void set_clock(
- 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(base->as);
- 
- 	/* Prepare to program display clock*/
--	dc_service_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-+	dm_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
- 
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = base->id;
-@@ -910,7 +910,7 @@ static bool dal_display_clock_dce110_construct(
- 			struct spread_spectrum_info info;
- 			bool result;
- 
--			dc_service_memset(&info, 0, sizeof(info));
-+			dm_memset(&info, 0, sizeof(info));
- 
- 			result =
- 				dal_adapter_service_get_ss_info(
-@@ -954,7 +954,7 @@ struct display_clock *dal_display_clock_dce110_create(
- {
- 	struct display_clock_dce110 *dc110;
- 
--	dc110 = dc_service_alloc(ctx, sizeof(struct display_clock_dce110));
-+	dc110 = dm_alloc(ctx, sizeof(struct display_clock_dce110));
- 
- 	if (dc110 == NULL)
- 		return NULL;
-@@ -962,7 +962,7 @@ struct display_clock *dal_display_clock_dce110_create(
- 	if (dal_display_clock_dce110_construct(dc110, ctx, as))
- 		return &dc110->disp_clk_base;
- 
--	dc_service_free(ctx, dc110);
-+	dm_free(ctx, dc110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-index 887bd74..1319248 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
-@@ -23,8 +23,9 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "display_clock.h"
-+
- #include "adapter_service_interface.h"
- 
- void dal_display_clock_base_set_dp_ref_clock_source(
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-index b4355f2..59d4400 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "divider_range.h"
- 
- bool dal_divider_range_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-index b81fbdb..7042d10 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "engine.h"
- 
-@@ -204,7 +203,7 @@ static void process_read_request(
- 				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- 			ctx->operation_succeeded = false;
- 		} else
--			dc_service_delay_in_microseconds(engine->base.ctx, 400);
-+			dm_delay_in_microseconds(engine->base.ctx, 400);
- 	break;
- 	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
- 		++ctx->timed_out_retry_aux;
-@@ -265,7 +264,7 @@ static bool read_command(
- 	ctx.request.delay = 0;
- 
- 	do {
--		dc_service_memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-+		dm_memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
- 
- 		ctx.request.data = ctx.buffer + ctx.offset;
- 		ctx.request.length = ctx.current_read_length;
-@@ -276,7 +275,7 @@ static bool read_command(
- 
- 		if (ctx.operation_succeeded && !ctx.transaction_complete)
- 			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
--				dc_service_sleep_in_milliseconds(engine->base.ctx, engine->delay);
-+				dm_sleep_in_milliseconds(engine->base.ctx, engine->delay);
- 	} while (ctx.operation_succeeded && !ctx.transaction_complete);
- 
- 	return ctx.operation_succeeded;
-@@ -331,7 +330,7 @@ static void process_write_reply(
- 				I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- 				ctx->operation_succeeded = false;
- 			} else
--				dc_service_delay_in_microseconds(engine->base.ctx, 300);
-+				dm_delay_in_microseconds(engine->base.ctx, 300);
- 		} else {
- 			ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- 			ctx->defer_retry_aux = 0;
-@@ -402,7 +401,7 @@ static void process_write_request(
- 				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- 			ctx->operation_succeeded = false;
- 		} else
--			dc_service_delay_in_microseconds(engine->base.ctx, 400);
-+			dm_delay_in_microseconds(engine->base.ctx, 400);
- 	break;
- 	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
- 		++ctx->timed_out_retry_aux;
-@@ -476,7 +475,7 @@ static bool write_command(
- 
- 		if (ctx.operation_succeeded && !ctx.transaction_complete)
- 			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
--				dc_service_sleep_in_milliseconds(engine->base.ctx, engine->delay);
-+				dm_sleep_in_milliseconds(engine->base.ctx, engine->delay);
- 	} while (ctx.operation_succeeded && !ctx.transaction_complete);
- 
- 	return ctx.operation_succeeded;
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-index d0b8288..f9c5543 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "../engine.h"
- #include "../aux_engine.h"
-@@ -72,7 +71,7 @@ static void release_engine(
- 
- 	const uint32_t addr = aux_engine->addr.aux_arb_control;
- 
--	uint32_t value = dal_read_reg(engine->ctx, addr);
-+	uint32_t value = dm_read_reg(engine->ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -80,7 +79,7 @@ static void release_engine(
- 		AUX_ARB_CONTROL,
- 		AUX_SW_DONE_USING_AUX_REG);
- 
--	dal_write_reg(engine->ctx, addr, value);
-+	dm_write_reg(engine->ctx, addr, value);
- }
- 
- static void destruct(
-@@ -93,7 +92,7 @@ static void destroy(
- 
- 	destruct(engine);
- 
--	dc_service_free((*aux_engine)->base.ctx, engine);
-+	dm_free((*aux_engine)->base.ctx, engine);
- 
- 	*aux_engine = NULL;
- }
-@@ -111,7 +110,7 @@ static bool acquire_engine(
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_control;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		field = get_reg_field_value(
- 				value,
-@@ -134,13 +133,13 @@ static bool acquire_engine(
- 				AUX_CONTROL,
- 				AUX_RESET);
- 
--			dal_write_reg(engine->base.ctx, addr, value);
-+			dm_write_reg(engine->base.ctx, addr, value);
- 
- 			/*poll HW to make sure reset it done*/
- 			do {
--				dc_service_delay_in_microseconds(engine->base.ctx, 1);
-+				dm_delay_in_microseconds(engine->base.ctx, 1);
- 
--				value = dal_read_reg(engine->base.ctx, addr);
-+				value = dm_read_reg(engine->base.ctx, addr);
- 
- 				field = get_reg_field_value(
- 						value,
-@@ -157,14 +156,14 @@ static bool acquire_engine(
- 				AUX_CONTROL,
- 				AUX_RESET);
- 
--			dal_write_reg(engine->base.ctx, addr, value);
-+			dm_write_reg(engine->base.ctx, addr, value);
- 
- 			counter = 0;
- 
- 			do {
--				dc_service_delay_in_microseconds(engine->base.ctx, 1);
-+				dm_delay_in_microseconds(engine->base.ctx, 1);
- 
--				value = dal_read_reg(engine->base.ctx, addr);
-+				value = dm_read_reg(engine->base.ctx, addr);
- 
- 				field = get_reg_field_value(
- 						value,
-@@ -181,7 +180,7 @@ static bool acquire_engine(
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_arb_control;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -189,9 +188,9 @@ static bool acquire_engine(
- 			AUX_ARB_CONTROL,
- 			AUX_SW_USE_AUX_REG_REQ);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		field = get_reg_field_value(
- 				value,
-@@ -210,7 +209,7 @@ static void configure(
- 
- 	const uint32_t addr = aux_engine->addr.aux_control;
- 
--	uint32_t value = dal_read_reg(engine->base.ctx, addr);
-+	uint32_t value = dm_read_reg(engine->base.ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -218,7 +217,7 @@ static void configure(
- 		AUX_CONTROL,
- 		AUX_IGNORE_HPD_DISCON);
- 
--	dal_write_reg(engine->base.ctx, addr, value);
-+	dm_write_reg(engine->base.ctx, addr, value);
- }
- 
- static bool start_gtc_sync(
-@@ -262,7 +261,7 @@ static void submit_channel_request(
- 	{
- 		const uint32_t addr = mmAUXN_IMPCAL;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -270,7 +269,7 @@ static void submit_channel_request(
- 			AUXN_IMPCAL,
- 			AUXN_CALOUT_ERROR_AK);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -278,12 +277,12 @@ static void submit_channel_request(
- 			AUXN_IMPCAL,
- 			AUXN_CALOUT_ERROR_AK);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- 	{
- 		const uint32_t addr = mmAUXP_IMPCAL;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -291,7 +290,7 @@ static void submit_channel_request(
- 			AUXP_IMPCAL,
- 			AUXP_CALOUT_ERROR_AK);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -299,14 +298,14 @@ static void submit_channel_request(
- 			AUXP_IMPCAL,
- 			AUXP_CALOUT_ERROR_AK);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- 
- 	/* force_default_calibrate */
- 	{
- 		const uint32_t addr = mmAUXN_IMPCAL;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -314,7 +313,7 @@ static void submit_channel_request(
- 			AUXN_IMPCAL,
- 			AUXN_IMPCAL_ENABLE);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -322,12 +321,12 @@ static void submit_channel_request(
- 			AUXN_IMPCAL,
- 			AUXN_IMPCAL_OVERRIDE_ENABLE);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- 	{
- 		const uint32_t addr = mmAUXP_IMPCAL;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -335,7 +334,7 @@ static void submit_channel_request(
- 			AUXP_IMPCAL,
- 			AUXP_IMPCAL_OVERRIDE_ENABLE);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -343,14 +342,14 @@ static void submit_channel_request(
- 			AUXP_IMPCAL,
- 			AUXP_IMPCAL_OVERRIDE_ENABLE);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- 
- 	/* set the delay and the number of bytes to write */
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_sw_control;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -374,14 +373,14 @@ static void submit_channel_request(
- 			AUX_SW_CONTROL,
- 			AUX_SW_WR_BYTES);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- 
- 	/* program action and address and payload data (if 'is_write') */
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_sw_data;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -408,7 +407,7 @@ static void submit_channel_request(
- 			AUX_SW_DATA,
- 			AUX_SW_DATA);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -422,7 +421,7 @@ static void submit_channel_request(
- 			AUX_SW_DATA,
- 			AUX_SW_DATA);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -430,7 +429,7 @@ static void submit_channel_request(
- 			AUX_SW_DATA,
- 			AUX_SW_DATA);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		if (request->length) {
- 			set_reg_field_value(
-@@ -439,7 +438,7 @@ static void submit_channel_request(
- 				AUX_SW_DATA,
- 				AUX_SW_DATA);
- 
--			dal_write_reg(engine->base.ctx, addr, value);
-+			dm_write_reg(engine->base.ctx, addr, value);
- 		}
- 
- 		if (is_write) {
-@@ -457,7 +456,7 @@ static void submit_channel_request(
- 					AUX_SW_DATA,
- 					AUX_SW_DATA);
- 
--				dal_write_reg(
-+				dm_write_reg(
- 					engine->base.ctx, addr, value);
- 
- 				++i;
-@@ -468,7 +467,7 @@ static void submit_channel_request(
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_interrupt_control;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -476,13 +475,13 @@ static void submit_channel_request(
- 			AUX_INTERRUPT_CONTROL,
- 			AUX_SW_DONE_ACK);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- 
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_sw_control;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -490,7 +489,7 @@ static void submit_channel_request(
- 			AUX_SW_CONTROL,
- 			AUX_SW_GO);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 	}
- }
- 
-@@ -510,7 +509,7 @@ static void process_channel_reply(
- 	{
- 		const uint32_t addr = aux_engine->addr.aux_sw_status;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		bytes_replied = get_reg_field_value(
- 				value,
-@@ -523,7 +522,7 @@ static void process_channel_reply(
- 
- 		const uint32_t addr = aux_engine->addr.aux_sw_data;
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -531,7 +530,7 @@ static void process_channel_reply(
- 			AUX_SW_DATA,
- 			AUX_SW_INDEX);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -539,7 +538,7 @@ static void process_channel_reply(
- 			AUX_SW_DATA,
- 			AUX_SW_AUTOINCREMENT_DISABLE);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
- 		set_reg_field_value(
- 			value,
-@@ -547,9 +546,9 @@ static void process_channel_reply(
- 			AUX_SW_DATA,
- 			AUX_SW_DATA_RW);
- 
--		dal_write_reg(engine->base.ctx, addr, value);
-+		dm_write_reg(engine->base.ctx, addr, value);
- 
--		value = dal_read_reg(engine->base.ctx, addr);
-+		value = dm_read_reg(engine->base.ctx, addr);
- 
- 		reply_result = get_reg_field_value(
- 				value,
-@@ -567,7 +566,7 @@ static void process_channel_reply(
- 			--bytes_replied;
- 
- 			while (i < bytes_replied) {
--				value = dal_read_reg(
-+				value = dm_read_reg(
- 					engine->base.ctx, addr);
- 
- 				reply->data[i] = get_reg_field_value(
-@@ -631,7 +630,7 @@ static enum aux_channel_operation_result get_channel_status(
- 		uint32_t time_elapsed = 0;
- 
- 		do {
--			value = dal_read_reg(engine->base.ctx, addr);
-+			value = dm_read_reg(engine->base.ctx, addr);
- 
- 			aux_sw_done = get_reg_field_value(
- 					value,
-@@ -641,7 +640,7 @@ static enum aux_channel_operation_result get_channel_status(
- 			if (aux_sw_done)
- 				break;
- 
--			dc_service_delay_in_microseconds(engine->base.ctx, 10);
-+			dm_delay_in_microseconds(engine->base.ctx, 10);
- 
- 			time_elapsed += 10;
- 		} while (time_elapsed < aux_engine->timeout_period);
-@@ -771,7 +770,7 @@ struct aux_engine *dal_aux_engine_dce110_create(
- 		return NULL;
- 	}
- 
--	engine = dc_service_alloc(aux_init_data->ctx, sizeof(*engine));
-+	engine = dm_alloc(aux_init_data->ctx, sizeof(*engine));
- 
- 	if (!engine) {
- 		ASSERT_CRITICAL(false);
-@@ -783,7 +782,7 @@ struct aux_engine *dal_aux_engine_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(aux_init_data->ctx, engine);
-+	dm_free(aux_init_data->ctx, engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-index ce3cc4d..2517f44 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/logger_interface.h"
- /*
-  * Pre-requisites: headers required by header of this unit
-@@ -102,7 +102,7 @@ static void disable_i2c_hw_engine(
- 
- 	ctx = engine->base.base.base.ctx;
- 
--	value = dal_read_reg(ctx, addr);
-+	value = dm_read_reg(ctx, addr);
- 
- 	set_reg_field_value(
- 		value,
-@@ -110,7 +110,7 @@ static void disable_i2c_hw_engine(
- 		DC_I2C_DDC1_SETUP,
- 		DC_I2C_DDC1_ENABLE);
- 
--	dal_write_reg(ctx, addr, value);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void release_engine(
-@@ -130,7 +130,7 @@ static void release_engine(
- 
- 	/* Release I2C */
- 	{
--		value = dal_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
- 
- 		set_reg_field_value(
- 				value,
-@@ -138,14 +138,14 @@ static void release_engine(
- 				DC_I2C_ARBITRATION,
- 				DC_I2C_SW_DONE_USING_I2C_REG);
- 
--		dal_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
-+		dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
- 	}
- 
- 	/* Reset HW engine */
- 	{
- 		uint32_t i2c_sw_status = 0;
- 
--		value = dal_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
- 
- 		i2c_sw_status = get_reg_field_value(
- 				value,
-@@ -155,7 +155,7 @@ static void release_engine(
- 		safe_to_reset = (i2c_sw_status == 1);
- 	}
- 	{
--		value = dal_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
- 
- 		if (safe_to_reset)
- 			set_reg_field_value(
-@@ -170,7 +170,7 @@ static void release_engine(
- 			DC_I2C_CONTROL,
- 			DC_I2C_SW_STATUS_RESET);
- 
--		dal_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+		dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
- 	}
- 
- 	/* HW I2c engine - clock gating feature */
-@@ -204,7 +204,7 @@ static bool setup_engine(
- 	{
- 		const uint32_t addr = mmDC_I2C_CONTROL;
- 
--		value = dal_read_reg(i2c_engine->base.ctx, addr);
-+		value = dm_read_reg(i2c_engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -243,14 +243,14 @@ static bool setup_engine(
- 			DC_I2C_DDC_SELECT);
- 
- 
--		dal_write_reg(i2c_engine->base.ctx, addr, value);
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
- 	}
- 
- 	/* Program time limit */
- 	{
- 		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
- 
--		value = dal_read_reg(i2c_engine->base.ctx, addr);
-+		value = dm_read_reg(i2c_engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -264,7 +264,7 @@ static bool setup_engine(
- 			DC_I2C_DDC1_SETUP,
- 			DC_I2C_DDC1_ENABLE);
- 
--		dal_write_reg(i2c_engine->base.ctx, addr, value);
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
- 	}
- 
- 	/* Program HW priority
-@@ -272,7 +272,7 @@ static bool setup_engine(
- 	 * Enable restart of SW I2C that was interrupted by HW
- 	 * disable queuing of software while I2C is in use by HW */
- 	{
--		value = dal_read_reg(i2c_engine->base.ctx,
-+		value = dm_read_reg(i2c_engine->base.ctx,
- 				mmDC_I2C_ARBITRATION);
- 
- 		set_reg_field_value(
-@@ -287,7 +287,7 @@ static bool setup_engine(
- 			DC_I2C_ARBITRATION,
- 			DC_I2C_SW_PRIORITY);
- 
--		dal_write_reg(i2c_engine->base.ctx,
-+		dm_write_reg(i2c_engine->base.ctx,
- 				mmDC_I2C_ARBITRATION, value);
- 	}
- 
-@@ -303,7 +303,7 @@ static uint32_t get_speed(
- 
- 	uint32_t pre_scale = 0;
- 
--	uint32_t value = dal_read_reg(i2c_engine->base.ctx, addr);
-+	uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
- 
- 	pre_scale = get_reg_field_value(
- 			value,
-@@ -327,7 +327,7 @@ static void set_speed(
- 	if (speed) {
- 		const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
- 
--		uint32_t value = dal_read_reg(i2c_engine->base.ctx, addr);
-+		uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -356,13 +356,13 @@ static void set_speed(
- 				DC_I2C_DDC1_START_STOP_TIMING_CNTL);
- 		}
- 
--		dal_write_reg(i2c_engine->base.ctx, addr, value);
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
- 	}
- }
- 
- static inline void reset_hw_engine(struct engine *engine)
- {
--	uint32_t value = dal_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
- 
- 	set_reg_field_value(
- 		value,
-@@ -376,14 +376,14 @@ static inline void reset_hw_engine(struct engine *engine)
- 		DC_I2C_CONTROL,
- 		DC_I2C_SW_STATUS_RESET);
- 
--	dal_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+	dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
- }
- 
- static bool is_hw_busy(struct engine *engine)
- {
- 	uint32_t i2c_sw_status = 0;
- 
--	uint32_t value = dal_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
- 
- 	i2c_sw_status = get_reg_field_value(
- 			value,
-@@ -395,7 +395,7 @@ static bool is_hw_busy(struct engine *engine)
- 
- 	reset_hw_engine(engine);
- 
--	value = dal_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+	value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
- 
- 	i2c_sw_status = get_reg_field_value(
- 			value,
-@@ -434,7 +434,7 @@ static bool process_transaction(
- 		const uint32_t addr =
- 			transaction_addr[engine->transaction_count];
- 
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -480,7 +480,7 @@ static bool process_transaction(
- 			DC_I2C_TRANSACTION0,
- 			DC_I2C_COUNT0);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* Write the I2C address and I2C data
-@@ -522,7 +522,7 @@ static bool process_transaction(
- 			engine->buffer_used_write = 0;
- 		}
- 
--		dal_write_reg(ctx, mmDC_I2C_DATA, value);
-+		dm_write_reg(ctx, mmDC_I2C_DATA, value);
- 
- 		engine->buffer_used_write++;
- 
-@@ -542,7 +542,7 @@ static bool process_transaction(
- 					DC_I2C_DATA,
- 					DC_I2C_DATA);
- 
--				dal_write_reg(ctx, mmDC_I2C_DATA, value);
-+				dm_write_reg(ctx, mmDC_I2C_DATA, value);
- 
- 				engine->buffer_used_write++;
- 				--length;
-@@ -567,7 +567,7 @@ static void execute_transaction(
- 	{
- 		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
- 
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -599,13 +599,13 @@ static void execute_transaction(
- 			DC_I2C_DDC1_SETUP,
- 			DC_I2C_DDC1_INTRA_BYTE_DELAY);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	{
- 		const uint32_t addr = mmDC_I2C_CONTROL;
- 
--		value = dal_read_reg(ctx, addr);
-+		value = dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -637,14 +637,14 @@ static void execute_transaction(
- 			DC_I2C_CONTROL,
- 			DC_I2C_TRANSACTION_COUNT);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* start I2C transfer */
- 	{
- 		const uint32_t addr = mmDC_I2C_CONTROL;
- 
--		value	= dal_read_reg(ctx, addr);
-+		value	= dm_read_reg(ctx, addr);
- 
- 		set_reg_field_value(
- 			value,
-@@ -652,7 +652,7 @@ static void execute_transaction(
- 			DC_I2C_CONTROL,
- 			DC_I2C_GO);
- 
--		dal_write_reg(ctx, addr, value);
-+		dm_write_reg(ctx, addr, value);
- 	}
- 
- 	/* all transactions were executed and HW buffer became empty
-@@ -709,7 +709,7 @@ static void process_channel_reply(
- 		DC_I2C_DATA,
- 		DC_I2C_INDEX_WRITE);
- 
--	dal_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
-+	dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
- 
- 	while (length) {
- 		/* after reading the status,
-@@ -717,7 +717,7 @@ static void process_channel_reply(
- 		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
- 		 * should read data bytes from I2C circular data buffer */
- 
--		value = dal_read_reg(engine->base.ctx, mmDC_I2C_DATA);
-+		value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
- 
- 		*buffer++ = get_reg_field_value(
- 				value,
-@@ -733,7 +733,7 @@ static enum i2c_channel_operation_result get_channel_status(
- 	uint8_t *returned_bytes)
- {
- 	uint32_t i2c_sw_status = 0;
--	uint32_t value = dal_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
-+	uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
- 
- 	i2c_sw_status = get_reg_field_value(
- 			value,
-@@ -792,7 +792,7 @@ static void destroy(
- 
- 	dal_i2c_hw_engine_destruct(&engine_dce110->base);
- 
--	dc_service_free((*i2c_engine)->base.ctx, engine_dce110);
-+	dm_free((*i2c_engine)->base.ctx, engine_dce110);
- 
- 	*i2c_engine = NULL;
- }
-@@ -893,7 +893,7 @@ static bool construct(
- 		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
- 
- 
--	value = dal_read_reg(
-+	value = dm_read_reg(
- 		engine_dce110->base.base.base.ctx,
- 		mmMICROSECOND_TIME_BASE_DIV);
- 
-@@ -936,7 +936,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create(
- 		return NULL;
- 	}
- 
--	engine_dce10 = dc_service_alloc(arg->ctx, sizeof(struct i2c_hw_engine_dce110));
-+	engine_dce10 = dm_alloc(arg->ctx, sizeof(struct i2c_hw_engine_dce110));
- 
- 	if (!engine_dce10) {
- 		ASSERT_CRITICAL(false);
-@@ -948,7 +948,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(arg->ctx, engine_dce10);
-+	dm_free(arg->ctx, engine_dce10);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-index 2d5a318..f060b25 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "../engine.h"
- #include "../i2c_engine.h"
-@@ -39,6 +38,7 @@
-  */
- 
- #include "i2c_sw_engine_dce110.h"
-+
- /*
-  * Post-requisites: headers required by this unit
-  */
-@@ -88,7 +88,7 @@ static void destroy(
- 
- 	destruct(sw_engine);
- 
--	dc_service_free((*engine)->base.ctx, sw_engine);
-+	dm_free((*engine)->base.ctx, sw_engine);
- 
- 	*engine = NULL;
- }
-@@ -154,7 +154,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create(
- 		return NULL;
- 	}
- 
--	engine_dce110 = dc_service_alloc(arg->ctx, sizeof(struct i2c_sw_engine_dce110));
-+	engine_dce110 = dm_alloc(arg->ctx, sizeof(struct i2c_sw_engine_dce110));
- 
- 	if (!engine_dce110) {
- 		ASSERT_CRITICAL(false);
-@@ -166,7 +166,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(arg->ctx, engine_dce110);
-+	dm_free(arg->ctx, engine_dce110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-index d2de0f2..9c88762 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "../i2caux.h"
- #include "../engine.h"
-@@ -40,6 +39,7 @@
-  * Header of this unit
-  */
- #include "i2caux_dce110.h"
-+
- #include "i2c_sw_engine_dce110.h"
- #include "i2c_hw_engine_dce110.h"
- #include "aux_engine_dce110.h"
-@@ -68,7 +68,7 @@ static void destroy(
- 
- 	destruct(i2caux_dce110);
- 
--	dc_service_free((*i2c_engine)->ctx, i2caux_dce110);
-+	dm_free((*i2c_engine)->ctx, i2caux_dce110);
- 
- 	*i2c_engine = NULL;
- }
-@@ -248,7 +248,7 @@ struct i2caux *dal_i2caux_dce110_create(
- 	struct dc_context *ctx)
- {
- 	struct i2caux_dce110 *i2caux_dce110 =
--		dc_service_alloc(ctx, sizeof(struct i2caux_dce110));
-+		dm_alloc(ctx, sizeof(struct i2caux_dce110));
- 
- 	if (!i2caux_dce110) {
- 		ASSERT_CRITICAL(false);
-@@ -260,7 +260,7 @@ struct i2caux *dal_i2caux_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, i2caux_dce110);
-+	dm_free(ctx, i2caux_dce110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-index 96b78e7..f4bc39d 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "../i2caux.h"
- #include "../engine.h"
-@@ -60,7 +59,7 @@ static void destroy(
- {
- 	destruct(*i2c_engine);
- 
--	dc_service_free((*i2c_engine)->ctx, *i2c_engine);
-+	dm_free((*i2c_engine)->ctx, *i2c_engine);
- 
- 	*i2c_engine = NULL;
- }
-@@ -95,7 +94,7 @@ struct i2caux *dal_i2caux_diag_fpga_create(
- 	struct adapter_service *as,
- 	struct dc_context *ctx)
- {
--	struct i2caux *i2caux =	dc_service_alloc(ctx, sizeof(struct i2caux));
-+	struct i2caux *i2caux =	dm_alloc(ctx, sizeof(struct i2caux));
- 
- 	if (!i2caux) {
- 		ASSERT_CRITICAL(false);
-@@ -107,7 +106,7 @@ struct i2caux *dal_i2caux_diag_fpga_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dc_service_free(ctx, i2caux);
-+	dm_free(ctx, i2caux);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c b/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-index 7a1c78c..9c472b9 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-index c8ab1f8..dccb1c5 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "engine.h"
- 
-@@ -67,7 +66,7 @@ bool dal_i2c_engine_acquire(
- 
- 		/* i2c_engine is busy by VBios, lets wait and retry */
- 
--		dc_service_delay_in_microseconds(engine->ctx, 10);
-+		dm_delay_in_microseconds(engine->ctx, 10);
- 
- 		++counter;
- 	} while (counter < 2);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-index 61df97e..6429b55 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "engine.h"
- #include "i2c_engine.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-index cd8aa44..b02ba79 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "engine.h"
- #include "i2c_engine.h"
-@@ -221,7 +220,7 @@ enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
- 		if (result != expected_result)
- 			break;
- 
--		dc_service_delay_in_microseconds(engine->base.base.ctx, 1);
-+		dm_delay_in_microseconds(engine->base.base.ctx, 1);
- 
- 		++i;
- 	} while (i < timeout);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-index c14c5df..21e8fa2 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- #include "engine.h"
- #include "i2c_engine.h"
-@@ -85,7 +84,7 @@ static bool wait_for_scl_high(
- 	uint32_t scl_retry = 0;
- 	uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	/* 3 milliseconds delay
- 	 * to wake up some displays from "low power" state.
-@@ -95,7 +94,7 @@ static bool wait_for_scl_high(
- 		if (read_bit_from_ddc(ddc, SCL))
- 			return true;
- 
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		++scl_retry;
- 	} while (scl_retry <= scl_retry_max);
-@@ -115,7 +114,7 @@ static bool start_sync(
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	do {
- 		write_bit_to_ddc(ddc_handle, SDA, true);
-@@ -125,7 +124,7 @@ static bool start_sync(
- 			continue;
- 		}
- 
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -134,11 +133,11 @@ static bool start_sync(
- 
- 		write_bit_to_ddc(ddc_handle, SDA, false);
- 
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SCL, false);
- 
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		return true;
- 	} while (retry <= I2C_SW_RETRIES);
-@@ -158,11 +157,11 @@ static bool stop_sync(
- 
- 	write_bit_to_ddc(ddc_handle, SCL, false);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SDA, false);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -172,7 +171,7 @@ static bool stop_sync(
- 	write_bit_to_ddc(ddc_handle, SDA, true);
- 
- 	do {
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		if (read_bit_from_ddc(ddc_handle, SDA))
- 			return true;
-@@ -195,11 +194,11 @@ static bool write_byte(
- 	/* bits are transmitted serially, starting from MSB */
- 
- 	do {
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
- 
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -215,11 +214,11 @@ static bool write_byte(
- 	 * after the SCL pulse we use to send our last data bit.
- 	 * If the SDA goes high after that bit, it's a NACK */
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SDA, true);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -230,11 +229,11 @@ static bool write_byte(
- 
- 	ack = !read_bit_from_ddc(ddc_handle, SDA);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, false);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
- 
- 	return ack;
- }
-@@ -264,7 +263,7 @@ static bool read_byte(
- 
- 		write_bit_to_ddc(ddc_handle, SCL, false);
- 
--		dc_service_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+		dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
- 
- 		--shift;
- 	} while (shift >= 0);
-@@ -273,14 +272,14 @@ static bool read_byte(
- 
- 	*byte = data;
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	/* send the acknowledge bit:
- 	 * SDA low means ACK, SDA high means NACK */
- 
- 	write_bit_to_ddc(ddc_handle, SDA, !more);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -289,11 +288,11 @@ static bool read_byte(
- 
- 	write_bit_to_ddc(ddc_handle, SCL, false);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SDA, true);
- 
--	dc_service_delay_in_microseconds(ctx, clock_delay_div_4);
-+	dm_delay_in_microseconds(ctx, clock_delay_div_4);
- 
- 	return true;
- }
-@@ -543,7 +542,7 @@ static void destroy(
- {
- 	dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
- 
--	dc_service_free((*ptr)->base.ctx, *ptr);
-+	dm_free((*ptr)->base.ctx, *ptr);
- 	*ptr = NULL;
- }
- 
-@@ -597,7 +596,7 @@ struct i2c_engine *dal_i2c_sw_engine_create(
- 		return NULL;
- 	}
- 
--	engine = dc_service_alloc(arg->ctx, sizeof(struct i2c_sw_engine));
-+	engine = dm_alloc(arg->ctx, sizeof(struct i2c_sw_engine));
- 
- 	if (!engine) {
- 		BREAK_TO_DEBUGGER();
-@@ -609,7 +608,7 @@ struct i2c_engine *dal_i2c_sw_engine_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dc_service_free(arg->ctx, engine);
-+	dm_free(arg->ctx, engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 68dff0e..4c2f2cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -23,12 +23,11 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- /*
-  * Pre-requisites: headers required by header of this unit
-  */
--
- #include "include/i2caux_interface.h"
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-index 048303e..17cb10f 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-@@ -23,10 +23,11 @@
-  *
-  */
- #ifndef GAMMA_TYPES_H_
-+
- #define GAMMA_TYPES_H_
- 
- #include "dc_types.h"
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- 
- /* TODO: Used in IPP and OPP */
- struct dev_c_lut {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index f2171de..b097983 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -29,7 +29,7 @@
- #include "dc_types.h"
- #include "grph_object_id.h"
- #include "grph_csc_types.h"
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- 
- struct fixed31_32;
- struct gamma_parameters;
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-index 3caeeed..4085b6f 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/logger_interface.h"
- 
-@@ -38,7 +38,7 @@ static bool hpd_ack(
- 	const struct irq_source_info *info)
- {
- 	uint32_t addr = info->status_reg;
--	uint32_t value = dal_read_reg(irq_service->ctx, addr);
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
- 	uint32_t current_status =
- 		get_reg_field_value(
- 			value,
-@@ -47,7 +47,7 @@ static bool hpd_ack(
- 
- 	dal_irq_service_ack_generic(irq_service, info);
- 
--	value = dal_read_reg(irq_service->ctx, info->enable_reg);
-+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
- 
- 	set_reg_field_value(
- 		value,
-@@ -55,7 +55,7 @@ static bool hpd_ack(
- 		DC_HPD_INT_CONTROL,
- 		DC_HPD_INT_POLARITY);
- 
--	dal_write_reg(irq_service->ctx, info->enable_reg, value);
-+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
- 
- 	return true;
- }
-@@ -376,7 +376,7 @@ bool construct(
- struct irq_service *dal_irq_service_dce110_create(
- 	struct irq_service_init_data *init_data)
- {
--	struct irq_service *irq_service = dc_service_alloc(init_data->ctx, sizeof(*irq_service));
-+	struct irq_service *irq_service = dm_alloc(init_data->ctx, sizeof(*irq_service));
- 
- 	if (!irq_service)
- 		return NULL;
-@@ -384,6 +384,6 @@ struct irq_service *dal_irq_service_dce110_create(
- 	if (construct(irq_service, init_data))
- 		return irq_service;
- 
--	dc_service_free(init_data->ctx, irq_service);
-+	dm_free(init_data->ctx, irq_service);
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-index 6f625dd..1372331 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- 
- #include "include/irq_service_interface.h"
- #include "include/logger_interface.h"
-@@ -70,7 +70,7 @@ void dal_irq_service_destroy(struct irq_service **irq_service)
- 		return;
- 	}
- 
--	dc_service_free((*irq_service)->ctx, *irq_service);
-+	dm_free((*irq_service)->ctx, *irq_service);
- 
- 	*irq_service = NULL;
- }
-@@ -91,11 +91,11 @@ void dal_irq_service_set_generic(
- 	bool enable)
- {
- 	uint32_t addr = info->enable_reg;
--	uint32_t value = dal_read_reg(irq_service->ctx, addr);
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
- 
- 	value = (value & ~info->enable_mask) |
- 		(info->enable_value[enable ? 0 : 1] & info->enable_mask);
--	dal_write_reg(irq_service->ctx, addr, value);
-+	dm_write_reg(irq_service->ctx, addr, value);
- }
- 
- bool dal_irq_service_set(
-@@ -132,11 +132,11 @@ void dal_irq_service_ack_generic(
- 	const struct irq_source_info *info)
- {
- 	uint32_t addr = info->ack_reg;
--	uint32_t value = dal_read_reg(irq_service->ctx, addr);
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
- 
- 	value = (value & ~info->ack_mask) |
- 		(info->ack_value & info->ack_mask);
--	dal_write_reg(irq_service->ctx, addr, value);
-+	dm_write_reg(irq_service->ctx, addr, value);
- }
- 
- bool dal_irq_service_ack(
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-index 4880341..ade443d 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- 
- #include "virtual_link_encoder.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-index 99784be..4f5271b 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-@@ -23,8 +23,7 @@
-  *
-  */
- 
--#include "dc_services.h"
--
-+#include "dm_services.h"
- #include "virtual_stream_encoder.h"
- 
- static void virtual_stream_encoder_dp_set_stream_attribute(
-@@ -110,7 +109,7 @@ bool virtual_stream_encoder_construct(
- struct stream_encoder *virtual_stream_encoder_create(
- 	struct dc_context *ctx, struct dc_bios *bp)
- {
--	struct stream_encoder *enc = dc_service_alloc(ctx, sizeof(*enc));
-+	struct stream_encoder *enc = dm_alloc(ctx, sizeof(*enc));
- 
- 	if (!enc)
- 		return NULL;
-@@ -119,7 +118,7 @@ struct stream_encoder *virtual_stream_encoder_create(
- 		return enc;
- 
- 	BREAK_TO_DEBUGGER();
--	dc_service_free(ctx, enc);
-+	dm_free(ctx, enc);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index 6791866..550ac87 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -24,9 +24,10 @@
-  */
- 
- #ifndef __DAL_BIOS_PARSER_TYPES_H__
-+
- #define __DAL_BIOS_PARSER_TYPES_H__
- 
--#include "dc_services.h"
-+#include "dm_services.h"
- #include "include/signal_types.h"
- #include "include/grph_object_ctrl_defs.h"
- #include "include/gpio_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-index 1a26eea..f393e95 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -26,7 +26,7 @@
- #ifndef __DAL_FIXED32_32_H__
- #define __DAL_FIXED32_32_H__
- 
--#include "dc_services_types.h"
-+#include "dm_services_types.h"
- 
- struct fixed32_32 {
- 	uint64_t value;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0752-drm-amd-dal-reg-logger-trace-caller.patch b/common/recipes-kernel/linux/files/0752-drm-amd-dal-reg-logger-trace-caller.patch
deleted file mode 100644
index b9e84540..00000000
--- a/common/recipes-kernel/linux/files/0752-drm-amd-dal-reg-logger-trace-caller.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 153a8df3efea2e0d220b92d587a4500f0dc7ffe3 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Mon, 1 Feb 2016 10:56:17 -0500
-Subject: [PATCH 0752/1110] drm/amd/dal: reg logger - trace caller.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dm_services.h | 21 +++++++++++++++------
- 1 file changed, 15 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 4112eda..206c0b7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -72,30 +72,39 @@ void dm_unregister_interrupt(
-  * GPU registers access
-  *
-  */
--static inline uint32_t dm_read_reg(
-+
-+#define dm_read_reg(ctx, address)	\
-+		dm_read_reg_func(ctx, address, __func__)
-+
-+static inline uint32_t dm_read_reg_func(
- 	const struct dc_context *ctx,
--	uint32_t address)
-+	uint32_t address,
-+	const char *func_name)
- {
- 	uint32_t value = cgs_read_register(ctx->cgs_device, address);
- 
- #if defined(__DAL_REGISTER_LOGGER__)
- 	if (true == dal_reg_logger_should_dump_register()) {
- 		dal_reg_logger_rw_count_increment();
--		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+		DRM_INFO("%s DC_READ_REG: 0x%x 0x%x\n", func_name, address, value);
- 	}
- #endif
- 	return value;
- }
- 
--static inline void dm_write_reg(
-+#define dm_write_reg(ctx, address, value)	\
-+	dm_write_reg_func(ctx, address, value, __func__)
-+
-+static inline void dm_write_reg_func(
- 	const struct dc_context *ctx,
- 	uint32_t address,
--	uint32_t value)
-+	uint32_t value,
-+	const char *func_name)
- {
- #if defined(__DAL_REGISTER_LOGGER__)
- 	if (true == dal_reg_logger_should_dump_register()) {
- 		dal_reg_logger_rw_count_increment();
--		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
-+		DRM_INFO("%s DC_WRITE_REG: 0x%x 0x%x\n", func_name, address, value);
- 	}
- #endif
- 	cgs_write_register(ctx->cgs_device, address, value);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0753-drm-amd-dal-Make-DCE-10-HWSS-independent-of-DCE-8.patch b/common/recipes-kernel/linux/files/0753-drm-amd-dal-Make-DCE-10-HWSS-independent-of-DCE-8.patch
deleted file mode 100644
index 81397ead..00000000
--- a/common/recipes-kernel/linux/files/0753-drm-amd-dal-Make-DCE-10-HWSS-independent-of-DCE-8.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From a9c18a9fc4984ad185b4a6f2536ec0fc908ad2e1 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Mon, 1 Feb 2016 14:32:43 -0500
-Subject: [PATCH 0753/1110] drm/amd/dal: Make DCE 10 HWSS independent of DCE 8
-
-Currently Linux kernel tree doesn't have dce 8 code so
-we can't reference it from dce 10 hardware sequencer.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index d166811..8cb756e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -31,8 +31,12 @@
- #include "opp.h"
- #include "transform.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce100/dce100_resource.h"
-+#endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/dce110_resource.h"
-+#endif
- 
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 				struct dc *dc,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0754-drm-amd-dal-Clean-up-MST-stream-on-our-ASIC.patch b/common/recipes-kernel/linux/files/0754-drm-amd-dal-Clean-up-MST-stream-on-our-ASIC.patch
deleted file mode 100644
index a71d6ce0..00000000
--- a/common/recipes-kernel/linux/files/0754-drm-amd-dal-Clean-up-MST-stream-on-our-ASIC.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From c98fdd2d0fd1255d6c921999155aea1f0cfd423f Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Mon, 1 Feb 2016 16:15:36 -0500
-Subject: [PATCH 0754/1110] drm/amd/dal: Clean up MST stream on our ASIC
-
-Make sure we call HWSS to clean up our ASIC's MST
-registers. deallocate_mst_payload will guard calls
-into drm_mst.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index b180cf6..2928724 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1634,8 +1634,7 @@ void core_link_disable_stream(
- {
- 	struct dc *dc = stream->ctx->dc;
- 
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST &&
--		link->public.type == dc_connection_mst_branch)
-+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		deallocate_mst_payload(stream);
- 
- 	dc->hwss.disable_stream(stream);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0755-drm-amd-dal-add-kernel-version-control-for-mst.patch b/common/recipes-kernel/linux/files/0755-drm-amd-dal-add-kernel-version-control-for-mst.patch
deleted file mode 100644
index 28ea6eb1..00000000
--- a/common/recipes-kernel/linux/files/0755-drm-amd-dal-add-kernel-version-control-for-mst.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From 0bbf8cfd004910d6cdb502c3147d3a4acac0bf52 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 1 Feb 2016 16:32:21 -0500
-Subject: [PATCH 0755/1110] drm/amd/dal: add kernel version control for mst
-
-resolve 4.2 dependencies when using dkms
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |  2 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  | 29 +++++++++++++++++++++-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 11 ++++++--
- 3 files changed, 38 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 47de461..c758fc6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -608,7 +608,7 @@ static void detect_link_for_all_connectors(struct drm_device *dev)
- 
- 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
- 
--	drm_for_each_connector(connector, dev) {
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- 		   aconnector = to_amdgpu_connector(connector);
- 		   if (aconnector->dc_link->type == dc_connection_mst_branch) {
- 			   DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index e2c68fd..bbc60a6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -25,6 +25,7 @@
- 
- #include <linux/string.h>
- #include <linux/acpi.h>
-+#include <linux/version.h>
- 
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
-@@ -126,7 +127,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
- 	return result;
- }
- 
--
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static struct amdgpu_connector *get_connector_for_sink(
- 	struct drm_device *dev,
- 	const struct dc_sink *sink)
-@@ -142,6 +143,7 @@ static struct amdgpu_connector *get_connector_for_sink(
- 
- 	return aconnector;
- }
-+#endif
- 
- static struct amdgpu_connector *get_connector_for_link(
- 	struct drm_device *dev,
-@@ -159,6 +161,8 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static void get_payload_table(
- 		struct amdgpu_connector *aconnector,
- 		struct dp_mst_stream_allocation_table *proposed_table)
-@@ -195,6 +199,7 @@ static void get_payload_table(
- 
- 	mutex_unlock(&mst_mgr->payload_lock);
- }
-+#endif
- 
- /*
-  * Writes payload allocation table in immediate downstream device.
-@@ -205,6 +210,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
- 		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -284,6 +290,9 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
- 		return false;
- 
- 	return true;
-+#else
-+	return false;
-+#endif
- }
- 
- /*
-@@ -294,6 +303,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -316,6 +326,9 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		return false;
- 
- 	return true;
-+#else
-+	return false;
-+#endif
- }
- 
- bool dm_helpers_dp_mst_send_payload_allocation(
-@@ -323,6 +336,7 @@ bool dm_helpers_dp_mst_send_payload_allocation(
- 		const struct dc_stream *stream,
- 		bool enable)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -351,10 +365,14 @@ bool dm_helpers_dp_mst_send_payload_allocation(
- 		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
- 
- 	return true;
-+#else
-+	return false;
-+#endif
- }
- 
- void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	uint8_t esi[8] = { 0 };
- 	uint8_t dret;
- 	bool new_irq_handled = true;
-@@ -393,6 +411,9 @@ void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- 				DP_SINK_COUNT_ESI, esi, 8);
- 		}
- 	}
-+#else
-+	return false;
-+#endif
- }
- 
- bool dm_helpers_dp_mst_start_top_mgr(
-@@ -400,6 +421,7 @@ bool dm_helpers_dp_mst_start_top_mgr(
- 		const struct dc_link *link,
- 		bool boot)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-@@ -414,12 +436,16 @@ bool dm_helpers_dp_mst_start_top_mgr(
- 			aconnector, aconnector->base.base.id);
- 
- 	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
-+#else
-+	return false;
-+#endif
- }
- 
- void dm_helpers_dp_mst_stop_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-@@ -429,6 +455,7 @@ void dm_helpers_dp_mst_stop_top_mgr(
- 
- 	if (aconnector->mst_mgr.mst_state == true)
- 		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+#endif
- }
- 
- bool dm_helper_dp_read_dpcd(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 3f1d545..2362003 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -23,6 +23,7 @@
-  *
-  */
- 
-+#include <linux/version.h>
- #include <drm/drm_atomic_helper.h>
- #include "dm_services.h"
- #include "amdgpu.h"
-@@ -32,6 +33,7 @@
- #include "dc.h"
- #include "dm_helpers.h"
- 
-+
- /* #define TRACE_DPCD */
- 
- #ifdef TRACE_DPCD
-@@ -114,6 +116,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 	return msg->size;
- }
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static enum drm_connector_status
- dm_dp_mst_detect(struct drm_connector *connector, bool force)
- {
-@@ -323,7 +326,7 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	struct drm_connector *connector;
- 
- 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
--	drm_for_each_connector(connector, dev) {
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- 		aconnector = to_amdgpu_connector(connector);
- 		if (aconnector->mst_port == master
- 				&& !aconnector->port) {
-@@ -454,6 +457,8 @@ struct drm_dp_mst_topology_cbs dm_mst_cbs = {
- 	.hotplug = dm_dp_mst_hotplug,
- 	.register_connector = dm_dp_mst_register_connector
- };
-+#endif
-+
- 
- void amdgpu_dm_initialize_mst_connector(
- 	struct amdgpu_display_manager *dm,
-@@ -465,7 +470,7 @@ void amdgpu_dm_initialize_mst_connector(
- 	aconnector->dm_dp_aux.link_index = aconnector->connector_id;
- 
- 	drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
--
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	aconnector->mst_mgr.cbs = &dm_mst_cbs;
- 	drm_dp_mst_topology_mgr_init(
- 		&aconnector->mst_mgr,
-@@ -474,4 +479,6 @@ void amdgpu_dm_initialize_mst_connector(
- 		16,
- 		4,
- 		aconnector->connector_id);
-+#endif
- }
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0756-drm-amd-dal-Delete-unused-clock-source-file.patch b/common/recipes-kernel/linux/files/0756-drm-amd-dal-Delete-unused-clock-source-file.patch
deleted file mode 100644
index b289b65b..00000000
--- a/common/recipes-kernel/linux/files/0756-drm-amd-dal-Delete-unused-clock-source-file.patch
+++ /dev/null
@@ -1,677 +0,0 @@
-From cb6247c99a6d559a0c1fbb815363849fe6c5d77f Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 2 Feb 2016 10:21:26 -0500
-Subject: [PATCH 0756/1110] drm/amd/dal: Delete unused clock source file
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c | 656 --------------------------
- 1 file changed, 656 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c b/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-deleted file mode 100644
-index 73804cd..0000000
---- a/drivers/gpu/drm/amd/dal/dc/gpu/clock_source.c
-+++ /dev/null
-@@ -1,656 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dc_services.h"
--
--#include "include/adapter_service_interface.h"
--#include "include/bios_parser_interface.h"
--#include "include/grph_object_id.h"
--#include "include/clock_source_interface.h"
--#include "include/logger_interface.h"
--
--#include "clock_source.h"
--#include "pll_clock_source.h"
--
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
--#include "dce110/ext_clock_source_dce110.h"
--#include "dce110/pll_clock_source_dce110.h"
--#include "dce110/vce_clock_source_dce110.h"
--#endif
--
--
--struct clock_source *dal_clock_source_create(
--		struct clock_source_init_data *clk_src_init_data)
--{
--	enum dce_version dce_ver =
--		dal_adapter_service_get_dce_version(clk_src_init_data->as);
--	enum clock_source_id clk_src_id =
--		dal_graphics_object_id_get_clock_source_id(
--			clk_src_init_data->clk_src_id);
--	switch (dce_ver) {
--
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
--	break;
--#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
--	case DCE_VERSION_10_0:
--#endif
--	case DCE_VERSION_11_0:
--	{
--		switch (clk_src_id) {
--		case CLOCK_SOURCE_ID_PLL0:
--		/* fall through */
--		case CLOCK_SOURCE_ID_PLL1:
--		/* fall through */
--		case CLOCK_SOURCE_ID_PLL2:
--			return dal_pll_clock_source_dce110_create(
--					clk_src_init_data);
--		case CLOCK_SOURCE_ID_EXTERNAL:
--			return dal_ext_clock_source_dce110_create(
--					clk_src_init_data);
--		case CLOCK_SOURCE_ID_VCE:
--			return dal_vce_clock_source_dce110_create(
--					clk_src_init_data);
--		default:
--			return NULL;
--		}
--	}
--	break;
--#endif
--
--	default:
--		dal_logger_write(clk_src_init_data->ctx->logger,
--			LOG_MAJOR_ERROR,
--			LOG_MINOR_COMPONENT_GPU,
--			"Clock Source (id %d): not supported DCE version %d",
--			clk_src_id,
--			dce_ver);
--		ASSERT_CRITICAL(false);
--	break;
--	}
--	return NULL;
--}
--
--const struct spread_spectrum_data *dal_clock_source_get_ss_data_entry(
--		struct clock_source *clk_src,
--		enum signal_type signal,
--		uint32_t pix_clk_khz)
--{
--
--	uint32_t entrys_num;
--	uint32_t i;
--	struct spread_spectrum_data *ss_parm = NULL;
--	struct spread_spectrum_data *ret = NULL;
--
--	switch (signal) {
--	case SIGNAL_TYPE_DVI_SINGLE_LINK:
--	case SIGNAL_TYPE_DVI_DUAL_LINK:
--		ss_parm = clk_src->dvi_ss_params;
--		entrys_num = clk_src->dvi_ss_params_cnt;
--		break;
--
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--		ss_parm = clk_src->hdmi_ss_params;
--		entrys_num = clk_src->hdmi_ss_params_cnt;
--		break;
--
--	case SIGNAL_TYPE_LVDS:
--		ss_parm = clk_src->ep_ss_params;
--		entrys_num = clk_src->ep_ss_params_cnt;
--		break;
--
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		ss_parm = clk_src->dp_ss_params;
--		entrys_num = clk_src->dp_ss_params_cnt;
--		break;
--
--	default:
--		ss_parm = NULL;
--		entrys_num = 0;
--		break;
--	}
--
--	if (ss_parm == NULL)
--		return ret;
--
--	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
--		if (ss_parm->freq_range_khz >= pix_clk_khz) {
--			ret = ss_parm;
--			break;
--		}
--	}
--
--	return ret;
--}
--
--bool dal_clock_source_base_adjust_dto_pix_rate(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		uint32_t requested_pix_clk_hz)
--{
--	return false;
--}
--
--/* Adjust clock to match given pixel rate (SS/DeepColor compensated)*/
--bool dal_clock_source_base_adjust_pll_pixel_rate(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		uint32_t requestedPixelClockInHz)
--{
--	return false;
--}
--
--static uint32_t retrieve_raw_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params)
--{
--	if (dc_is_dp_signal(pix_clk_params->signal_type))
--		return clk_src->funcs->retrieve_dto_pix_rate_hz(
--				clk_src,
--				pix_clk_params);
--	else
--		return clk_src->funcs->retrieve_pll_pix_rate_hz(
--				clk_src,
--				pix_clk_params);
--}
--
--
--
--bool dal_clock_source_adjust_pxl_clk_by_pxl_amount(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		int32_t pix_num)
--{
--
--	uint32_t cur_pix_rate_hz;
--	uint32_t reqested_pix_rate_hz;
--	bool success = false;
--
--	if (pix_clk_params == NULL)
--			return false;
--
--	cur_pix_rate_hz = retrieve_raw_pix_rate_hz(clk_src, pix_clk_params);
--	reqested_pix_rate_hz = cur_pix_rate_hz + pix_num;
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[start]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n",
--		__func__,
--		(cur_pix_rate_hz / 1000000),
--		(cur_pix_rate_hz / 1000) % 1000,
--		(cur_pix_rate_hz % 1000),
--		(reqested_pix_rate_hz / 1000000),
--		(reqested_pix_rate_hz / 1000) % 1000,
--		(reqested_pix_rate_hz % 1000));
--
--	if (dc_is_dp_signal(pix_clk_params->signal_type))
--		success = clk_src->funcs->adjust_dto_pixel_rate(clk_src,
--				pix_clk_params,
--				reqested_pix_rate_hz);
--	else
--		success = clk_src->funcs->adjust_pll_pixel_rate(
--				clk_src,
--				pix_clk_params,
--				reqested_pix_rate_hz);
--
--	cur_pix_rate_hz = retrieve_raw_pix_rate_hz(clk_src, pix_clk_params);
--
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[end]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n\n",
--		__func__,
--		(cur_pix_rate_hz / 1000000),
--		(cur_pix_rate_hz / 1000) % 1000,
--		(cur_pix_rate_hz % 1000),
--		(reqested_pix_rate_hz / 1000000),
--		(reqested_pix_rate_hz / 1000) % 1000,
--		(reqested_pix_rate_hz % 1000));
--
--	return success;
--}
--
--/***************************/
--/* private methods section */
--/***************************/
--
--void dal_clock_source_get_ss_info_from_atombios(
--		struct clock_source *clk_src,
--		enum as_signal_type as_signal,
--		struct spread_spectrum_data *spread_spectrum_data[],
--		uint32_t *ss_entries_num)
--{
--	enum bp_result bp_result = BP_RESULT_FAILURE;
--	struct spread_spectrum_info *ss_info;
--	struct spread_spectrum_data *ss_data;
--	struct spread_spectrum_info *ss_info_cur;
--	struct spread_spectrum_data *ss_data_cur;
--	uint32_t i;
--
--	if (ss_entries_num == NULL) {
--		dal_logger_write(clk_src->ctx->logger,
--			LOG_MAJOR_SYNC,
--			LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--			"Invalid entry !!!\n");
--		return;
--	}
--	if (spread_spectrum_data == NULL) {
--		dal_logger_write(clk_src->ctx->logger,
--			LOG_MAJOR_SYNC,
--			LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--			"Invalid array pointer!!!\n");
--		return;
--	}
--
--	spread_spectrum_data[0] = NULL;
--	*ss_entries_num = 0;
--
--	*ss_entries_num = clk_src->bios_parser->funcs->get_ss_entry_number(
--			clk_src->bios_parser,
--			as_signal);
--
--	if (*ss_entries_num == 0)
--		return;
--
--	ss_info = dc_service_alloc(clk_src->ctx, sizeof(struct spread_spectrum_info)
--				* (*ss_entries_num));
--	ss_info_cur = ss_info;
--	if (ss_info == NULL)
--		return;
--
--	ss_data = dc_service_alloc(clk_src->ctx, sizeof(struct spread_spectrum_data) *
--							(*ss_entries_num));
--	if (ss_data == NULL)
--		goto out_free_info;
--
--	for (i = 0, ss_info_cur = ss_info;
--		i < (*ss_entries_num);
--		++i, ++ss_info_cur) {
--
--		bp_result = clk_src->bios_parser->funcs->get_spread_spectrum_info(
--				clk_src->bios_parser,
--				as_signal,
--				i,
--				ss_info_cur);
--
--		if (bp_result != BP_RESULT_OK)
--			goto out_free_data;
--	}
--
--	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
--		i < (*ss_entries_num);
--		++i, ++ss_info_cur, ++ss_data_cur) {
--
--		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
--			dal_logger_write(clk_src->ctx->logger,
--				LOG_MAJOR_SYNC,
--				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--				"Invalid ATOMBIOS SS Table!!!\n");
--			goto out_free_data;
--		}
--
--		/* for HDMI check SS percentage,
--		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
--		if (as_signal == AS_SIGNAL_TYPE_HDMI
--				&& ss_info_cur->spread_spectrum_percentage > 6){
--			/* invalid input, do nothing */
--			dal_logger_write(clk_src->ctx->logger,
--				LOG_MAJOR_SYNC,
--				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--				"Invalid SS percentage ");
--			dal_logger_write(clk_src->ctx->logger,
--				LOG_MAJOR_SYNC,
--				LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--				"for HDMI in ATOMBIOS info Table!!!\n");
--			continue;
--		}
--		if (ss_info_cur->spread_percentage_divider == 1000) {
--			/* Keep previous precision from ATOMBIOS for these
--			* in case new precision set by ATOMBIOS for these
--			* (otherwise all code in DCE specific classes
--			* for all previous ASICs would need
--			* to be updated for SS calculations,
--			* Audio SS compensation and DP DTO SS compensation
--			* which assumes fixed SS percentage Divider = 100)*/
--			ss_info_cur->spread_spectrum_percentage /= 10;
--			ss_info_cur->spread_percentage_divider = 100;
--		}
--
--		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
--		ss_data_cur->percentage =
--				ss_info_cur->spread_spectrum_percentage;
--		ss_data_cur->percentage_divider =
--				ss_info_cur->spread_percentage_divider;
--		ss_data_cur->modulation_freq_hz =
--				ss_info_cur->spread_spectrum_range;
--
--		if (ss_info_cur->type.CENTER_MODE)
--			ss_data_cur->flags.CENTER_SPREAD = 1;
--
--		if (ss_info_cur->type.EXTERNAL)
--			ss_data_cur->flags.EXTERNAL_SS = 1;
--
--	}
--
--	*spread_spectrum_data = ss_data;
--	dc_service_free(clk_src->ctx, ss_info);
--	return;
--
--out_free_data:
--	dc_service_free(clk_src->ctx, ss_data);
--	*ss_entries_num = 0;
--out_free_info:
--	dc_service_free(clk_src->ctx, ss_info);
--}
--
--uint32_t dal_clock_source_base_retrieve_dto_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params)
--{
--	return 0;
--}
--
--
--uint32_t dal_clock_source_base_retrieve_pll_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params)
--{
--	return 0;
--}
--
--/*****************************/
--/* interface methods section */
--/*****************************/
--
--enum clock_source_id dal_clock_source_get_id(
--		const struct clock_source *clk_src)
--{
--	return clk_src->clk_src_id;
--}
--
--bool dal_clock_source_is_clk_src_with_fixed_freq(
--		const struct clock_source *clk_src)
--{
--	return clk_src->is_clock_source_with_fixed_freq;
--}
--
--const struct graphics_object_id dal_clock_source_get_graphics_object_id(
--		const struct clock_source *clk_src)
--{
--	return clk_src->id;
--}
--
--enum clock_sharing_level dal_clock_souce_get_clk_sharing_lvl(
--		const struct clock_source *clk_src)
--{
--	return clk_src->clk_sharing_lvl;
--}
--
--uint32_t dal_clock_source_get_pix_clk_dividers(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	return clk_src->funcs->
--		get_pix_clk_dividers(clk_src, pix_clk_params, pll_settings);
--}
--
--bool dal_clock_source_program_pix_clk(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params,
--		struct pll_settings *pll_settings)
--{
--	return clk_src->funcs->
--			program_pix_clk(clk_src, pix_clk_params, pll_settings);
--}
--
--/* TODO save/restore FP was here */
--bool dal_clock_source_adjust_pxl_clk_by_ref_pixel_rate(
--					struct clock_source *clk_src,
--					struct pixel_clk_params *pix_clk_params,
--					uint32_t pix_rate_hz)
--{
--	uint32_t current_pix_rate_hz = 0;
--	uint32_t raw_cur_pix_rate_hz = 0;
--	uint32_t raw_pix_rate_hz = pix_rate_hz;
--	bool success = false;
--
--	if (pix_clk_params == NULL || pix_rate_hz == 0)
--		return false;
--
--	current_pix_rate_hz = retrieve_raw_pix_rate_hz(
--				clk_src,
--				pix_clk_params);
--	raw_cur_pix_rate_hz = current_pix_rate_hz;
--
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[start]: Current: %u,%03u,%03uHz, Requested: %u,%03u,%03uHz\n",
--		__func__,
--		(current_pix_rate_hz / 1000000),
--		(current_pix_rate_hz / 1000) % 1000,
--		(current_pix_rate_hz % 1000),
--		(pix_rate_hz / 1000000),
--		(pix_rate_hz / 1000) % 1000,
--		(pix_rate_hz % 1000));
--
--	if (dc_is_dp_signal(pix_clk_params->signal_type))
--		success = clk_src->funcs->adjust_dto_pixel_rate(
--				clk_src,
--				pix_clk_params,
--				raw_pix_rate_hz);
--	else
--		success = clk_src->funcs->adjust_pll_pixel_rate(
--				clk_src,
--				pix_clk_params,
--				raw_pix_rate_hz);
--
--	if (dc_is_dp_signal(pix_clk_params->signal_type))
--		raw_cur_pix_rate_hz = clk_src->funcs->
--				retrieve_dto_pix_rate_hz(
--						clk_src,
--						pix_clk_params);
--	else
--		raw_cur_pix_rate_hz = clk_src->funcs->
--				retrieve_pll_pix_rate_hz(
--						clk_src,
--						pix_clk_params);
--
--	current_pix_rate_hz = raw_cur_pix_rate_hz;
--
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[end]: Current: %u,%03u,%03uHz, Requested: %u,%03u,%03uHz\n",
--		__func__,
--		(current_pix_rate_hz / 1000000),
--		(current_pix_rate_hz / 1000) % 1000,
--		(current_pix_rate_hz % 1000),
--		(pix_rate_hz / 1000000),
--		(pix_rate_hz / 1000) % 1000,
--		(pix_rate_hz % 1000));
--
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[end]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n\n",
--		__func__,
--		(raw_cur_pix_rate_hz / 1000000),
--		(raw_cur_pix_rate_hz / 1000) % 1000,
--		(raw_cur_pix_rate_hz % 1000),
--		(raw_pix_rate_hz / 1000000),
--		(raw_pix_rate_hz / 1000) % 1000,
--		(raw_pix_rate_hz % 1000));
--
--	return success;
--}
--
--/* TODO store/restore FP was here*/
--bool dal_clock_source_adjust_pxl_clk_by_pix_amount(
--					struct clock_source *clk_src,
--					struct pixel_clk_params *pix_clk_params,
--					int32_t pix_num)
--{
--	bool success = false;
--	uint32_t requested_pix_rate_hz;
--	uint32_t cur_pix_rate_hz = retrieve_raw_pix_rate_hz(
--			clk_src,
--			pix_clk_params);
--	requested_pix_rate_hz = cur_pix_rate_hz + pix_num;
--
--	if (pix_clk_params == NULL)
--		return false;
--
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[start]: Current(Raw): %u,%03u,%03uHz, Requested(Raw): %u,%03u,%03uHz\n",
--		__func__,
--		(cur_pix_rate_hz / 1000000),
--		(cur_pix_rate_hz / 1000) % 1000,
--		(cur_pix_rate_hz % 1000),
--		(requested_pix_rate_hz / 1000000),
--		(requested_pix_rate_hz / 1000) % 1000,
--		(requested_pix_rate_hz % 1000));
--
--	if (dc_is_dp_signal(pix_clk_params->signal_type))
--		success = clk_src->funcs->adjust_dto_pixel_rate(
--				clk_src,
--				pix_clk_params,
--				requested_pix_rate_hz);
--	else
--		success = clk_src->funcs->adjust_pll_pixel_rate(
--				clk_src,
--				pix_clk_params,
--				requested_pix_rate_hz);
--
--	cur_pix_rate_hz = retrieve_raw_pix_rate_hz(clk_src, pix_clk_params);
--
--	dal_logger_write(clk_src->ctx->logger,
--		LOG_MAJOR_SYNC,
--		LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
--		"%s[end]: Current(Raw): %u,%03u,%03uHz,Requested(Raw): %u,%03u,%03uHz\n\n",
--		__func__,
--		(cur_pix_rate_hz / 1000000),
--		(cur_pix_rate_hz / 1000) % 1000,
--		(cur_pix_rate_hz % 1000),
--		(requested_pix_rate_hz / 1000000),
--		(requested_pix_rate_hz / 1000) % 1000,
--		(requested_pix_rate_hz % 1000));
--
--	return success;
--}
--
--/* TODO save/restore FP was here*/
--uint32_t dal_clock_source_retrieve_pix_rate_hz(
--		struct clock_source *clk_src,
--		struct pixel_clk_params *pix_clk_params)
--{
--	uint32_t pixel_rate_hz = 0;
--
--	if (pix_clk_params == NULL)
--		return pixel_rate_hz;
--
--	if (dc_is_dp_signal(pix_clk_params->signal_type))
--		pixel_rate_hz = clk_src->funcs->retrieve_dto_pix_rate_hz(
--							clk_src,
--							pix_clk_params);
--	else
--		pixel_rate_hz = clk_src->funcs->retrieve_pll_pix_rate_hz(
--							clk_src,
--							pix_clk_params);
--
--
--	return pixel_rate_hz;
--}
--
--bool dal_clock_source_construct(
--			struct clock_source *clk_src,
--			struct clock_source_init_data *clk_src_init_data)
--{
--	if (clk_src_init_data == NULL || clk_src_init_data->as == NULL)
--		return false;
--	clk_src->ctx = clk_src_init_data->ctx;
--	clk_src->id = clk_src_init_data->clk_src_id;
--	clk_src->adapter_service = clk_src_init_data->as;
--	clk_src->bios_parser = dal_adapter_service_get_bios_parser(
--			clk_src_init_data->as);
--	clk_src->turn_off_ds = false;
--	clk_src->clk_src_id = dal_graphics_object_id_get_clock_source_id(
--						clk_src_init_data->clk_src_id);
--	clk_src->is_gen_lock_capable = true;
--/*NOTE is_gen_lock_capable is false only for ext clock source dce80 */
--
--	clk_src->ep_ss_params = NULL;
--	clk_src->dp_ss_params = NULL;
--	clk_src->hdmi_ss_params = NULL;
--	clk_src->hdmi_ss_params = NULL;
--	clk_src->ep_ss_params_cnt = 0;
--	clk_src->dp_ss_params_cnt = 0;
--	clk_src->hdmi_ss_params_cnt = 0;
--	clk_src->dvi_ss_params_cnt = 0;
--	clk_src->output_signals = SIGNAL_TYPE_ALL;
--	clk_src->input_signals = SIGNAL_TYPE_ALL;
--
--	return true;
--}
--
--void dal_clock_source_destroy(struct clock_source **clk_src)
--{
--	if (!clk_src || !(*clk_src))
--		return;
--
--	(*clk_src)->funcs->destroy(clk_src);
--
--	*clk_src = NULL;
--}
--
--bool dal_clock_source_is_input_signal_supported(
--		struct clock_source *clk_src,
--		enum signal_type signal_type)
--{
--	/* TODO do we need this in clock_source ?? */
--	return (clk_src->input_signals & signal_type) != 0;
--}
--
--bool dal_clock_source_is_output_signal_supported(
--		const struct clock_source *clk_src,
--		enum signal_type signal_type)
--{
--	return (clk_src->output_signals & signal_type) != 0;
--}
--
--bool dal_clock_source_is_gen_lock_capable(struct clock_source *clk_src)
--{
--	return clk_src->is_gen_lock_capable;
--}
--
--bool dal_clock_source_power_down_pll(struct clock_source *clk_src,
--		enum controller_id controller_id)
--{
--	return clk_src->funcs->power_down_pll(clk_src, controller_id);
--}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0757-drm-amd-dal-Fix-building-with-C-compiler.patch b/common/recipes-kernel/linux/files/0757-drm-amd-dal-Fix-building-with-C-compiler.patch
deleted file mode 100644
index f633733e..00000000
--- a/common/recipes-kernel/linux/files/0757-drm-amd-dal-Fix-building-with-C-compiler.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From ea66a4b86b52bdf258a30c0a0d6e5abdbe405093 Mon Sep 17 00:00:00 2001
-From: Ken Chalmers <ken.chalmers@amd.com>
-Date: Mon, 1 Feb 2016 09:46:38 -0500
-Subject: [PATCH 0757/1110] drm/amd/dal: Fix building with C++ compiler.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Move struct definitions outside anonymous unions.  Without this,
-including these files from a C++ source file causes an error from g++:
-
-../../include/audio_types.h:134:10: error: ‘struct
-audio_info_flags::<anonymous union>::audio_speaker_flags’ invalid; an
-anonymous union can only have non-static data members [-fpermissive]
-
-Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/include/audio_types.h      | 33 ++++++++++++----------
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    | 12 ++++----
- 2 files changed, 25 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h
-index 204c5d8..54f5546 100644
---- a/drivers/gpu/drm/amd/dal/include/audio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/audio_types.h
-@@ -127,25 +127,28 @@ struct audio_mode {
- 	};
- };
- 
-+struct audio_speaker_flags {
-+    uint32_t FL_FR:1;
-+    uint32_t LFE:1;
-+    uint32_t FC:1;
-+    uint32_t RL_RR:1;
-+    uint32_t RC:1;
-+    uint32_t FLC_FRC:1;
-+    uint32_t RLC_RRC:1;
-+    uint32_t SUPPORT_AI:1;
-+};
-+
-+struct audio_speaker_info {
-+    uint32_t ALLSPEAKERS:7;
-+    uint32_t SUPPORT_AI:1;
-+};
-+
- struct audio_info_flags {
- 
- 	union {
- 
--		struct audio_speaker_flags {
--			uint32_t FL_FR:1;
--			uint32_t LFE:1;
--			uint32_t FC:1;
--			uint32_t RL_RR:1;
--			uint32_t RC:1;
--			uint32_t FLC_FRC:1;
--			uint32_t RLC_RRC:1;
--			uint32_t SUPPORT_AI:1;
--		} speaker_flags;
--
--		struct audio_speaker_info {
--			uint32_t ALLSPEAKERS:7;
--			uint32_t SUPPORT_AI:1;
--		} info;
-+		struct audio_speaker_flags speaker_flags;
-+		struct audio_speaker_info   info;
- 
- 		uint8_t all;
- 	};
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index c6de837..2ed01bd 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -259,6 +259,12 @@ struct analog_tv_info {
- 	union tv_standard_support tv_boot_up_default;
- };
- 
-+struct step_and_delay_info {
-+    uint32_t step;
-+    uint32_t delay;
-+    uint32_t recommended_ref_div;
-+};
-+
- struct spread_spectrum_info {
- 	struct spread_spectrum_type {
- 		bool CENTER_MODE:1;
-@@ -273,11 +279,7 @@ struct spread_spectrum_info {
- 	uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
- 
- 	union {
--		struct step_and_delay_info {
--			uint32_t step;
--			uint32_t delay;
--			uint32_t recommended_ref_div;
--		} step_and_delay_info;
-+		struct step_and_delay_info step_and_delay_info;
- 		/* For mem/engine/uvd, Clock Out frequence (VCO ),
- 		in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
- 		for DP, it is link clock ( 270000 or 162000 ) */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0758-drm-amd-dal-Prevent-access-to-PTE-registers-for-FPGA.patch b/common/recipes-kernel/linux/files/0758-drm-amd-dal-Prevent-access-to-PTE-registers-for-FPGA.patch
deleted file mode 100644
index d2a0e7de..00000000
--- a/common/recipes-kernel/linux/files/0758-drm-amd-dal-Prevent-access-to-PTE-registers-for-FPGA.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 743015c813e793b24c7607975ec2b31d68e68efd Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Fri, 29 Jan 2016 16:52:32 -0500
-Subject: [PATCH 0758/1110] drm/amd/dal: Prevent access to PTE registers for
- FPGA/Diag environment.
-
-This fixes a regression caused by recent refactoring.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 89d5c65..71fa7b1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -433,6 +433,9 @@ static bool dce110_enable_display_power_gating(
- 	enum bp_result bp_result = BP_RESULT_OK;
- 	enum bp_pipe_control_action cntl;
- 
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
-+		return true;
-+
- 	if (power_gating == PIPE_GATING_CONTROL_INIT)
- 		cntl = ASIC_PIPE_INIT;
- 	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-@@ -755,10 +758,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
- 			.flags.timing_changed;
- 	enum color_space color_space;
--	struct dc_bios *dcb;
--
--	dcb = dal_adapter_service_get_bios_parser(
--			context->res_ctx.pool.adapter_srv);
- 
- 	if (timing_changed) {
- 		/* Must blank CRTC after disabling power gating and before any
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0759-drm-amd-dal-Remove-double-call-to-write-payload-allo.patch b/common/recipes-kernel/linux/files/0759-drm-amd-dal-Remove-double-call-to-write-payload-allo.patch
deleted file mode 100644
index af023b23..00000000
--- a/common/recipes-kernel/linux/files/0759-drm-amd-dal-Remove-double-call-to-write-payload-allo.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 0b3ab7d432703155145e0b9d41d7f618b7cd25e3 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 2 Feb 2016 11:28:08 -0500
-Subject: [PATCH 0759/1110] drm/amd/dal: Remove double call to write payload
- allocation table
-
-This was missed in previous change to only call payload
-allocation table when in mst_mode.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 2928724..2db5147 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1562,11 +1562,6 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 				&stream->public,
- 				&proposed_table,
- 				false);
--	dm_helpers_dp_mst_write_payload_allocation_table(
--		stream->ctx,
--		&stream->public,
--		&proposed_table,
--		false);
- 
- 	update_mst_stream_alloc_table(link, stream, &proposed_table);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0760-drm-amd-dal-Fix-DKMS-compilation-for-kernel-3.19.patch b/common/recipes-kernel/linux/files/0760-drm-amd-dal-Fix-DKMS-compilation-for-kernel-3.19.patch
deleted file mode 100644
index a7f34f03..00000000
--- a/common/recipes-kernel/linux/files/0760-drm-amd-dal-Fix-DKMS-compilation-for-kernel-3.19.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From a59f02e7431ac86a8ddd0f69ba0cb7e8b601855e Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <david.rokhvarg@amd.com>
-Date: Tue, 2 Feb 2016 13:35:35 -0500
-Subject: [PATCH 0760/1110] drm/amd/dal: Fix DKMS compilation for kernel 3.19.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a8350e6..3f80880 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -24,6 +24,8 @@
-  */
- 
- #include <linux/types.h>
-+#include <linux/version.h>
-+
- #include <drm/drmP.h>
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_fb_helper.h>
-@@ -1536,8 +1538,10 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 	if (!primary_plane)
- 		goto fail_plane;
- 
--	/* this flag is used in legacy code only */
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
-+	/* this flag doesn't exist in older kernels */
- 	primary_plane->format_default = true;
-+#endif
- 
- 	res = drm_universal_plane_init(
- 		dm->adev->ddev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0761-drm-amd-dal-Add-dce10-in-dal_adapter_service_get_dce.patch b/common/recipes-kernel/linux/files/0761-drm-amd-dal-Add-dce10-in-dal_adapter_service_get_dce.patch
deleted file mode 100644
index 03c00f2d..00000000
--- a/common/recipes-kernel/linux/files/0761-drm-amd-dal-Add-dce10-in-dal_adapter_service_get_dce.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c776878fa10d0cc132b0ac5850909c148bee7f99 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 2 Feb 2016 15:33:41 -0500
-Subject: [PATCH 0761/1110] drm/amd/dal: Add dce10 in
- dal_adapter_service_get_dce_version
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Eagle Yeh <eagle.yeh@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 73bfd4e..3e07408 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -903,6 +903,10 @@ enum dce_version dal_adapter_service_get_dce_version(
- 	uint32_t version = as->asic_cap->data[ASIC_DATA_DCE_VERSION];
- 
- 	switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	case 0x100:
-+		return DCE_VERSION_10_0;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case 0x110:
- 		return DCE_VERSION_11_0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0762-drm-amd-dal-Expose-dig-index-display_signal-and-ddc-.patch b/common/recipes-kernel/linux/files/0762-drm-amd-dal-Expose-dig-index-display_signal-and-ddc-.patch
deleted file mode 100644
index 4e966c54..00000000
--- a/common/recipes-kernel/linux/files/0762-drm-amd-dal-Expose-dig-index-display_signal-and-ddc-.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 9783c01cb969c1c5310d2ceda0a62ea7d20a3f10 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 2 Feb 2016 14:32:29 -0500
-Subject: [PATCH 0762/1110] drm/amd/dal: Expose dig index, display_signal and
- ddc to amdgpu
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 44 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc.h                    | 26 ++++++-------
- 3 files changed, 58 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 3e07408..dd2f931 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -92,7 +92,7 @@ static struct feature_source_entry feature_entry_table[] = {
- 	 * Driver uses SW I2C.
- 	 * Make Test uses HW I2C.
- 	 */
--	{FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, true, true},
-+	{FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, false, true},
- 	{FEATURE_USE_MAX_DISPLAY_CLK, false, true},
- 	{FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
- 	{FEATURE_SUPPORT_DP_YUV, false, true},
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e6c7cac..0b8f158 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -886,3 +886,47 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink
- 		}
- 	}
- }
-+
-+uint8_t dc_get_dig_index(const struct dc_stream *stream)
-+{
-+
-+	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
-+
-+	switch (core_stream->stream_enc->id) {
-+	case ENGINE_ID_DIGA:
-+		return 0;
-+	case ENGINE_ID_DIGB:
-+		return 1;
-+	case ENGINE_ID_DIGC:
-+		return 2;
-+	case ENGINE_ID_DIGD:
-+		return 3;
-+	case ENGINE_ID_DIGE:
-+		return 4;
-+	case ENGINE_ID_DIGF:
-+		return 5;
-+	case ENGINE_ID_DIGG:
-+		return 6;
-+	default:
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+enum gpio_ddc_line dc_get_ddc_line(
-+		const struct dc_stream *stream)
-+{
-+
-+	struct core_sink *core_sink = DC_SINK_TO_CORE(stream->sink);
-+	struct ddc *ddc_line = dal_ddc_service_get_ddc_pin(
-+			core_sink->link->ddc);
-+
-+	return dal_ddc_get_line(ddc_line);
-+}
-+
-+enum signal_type dc_get_display_signal(
-+		const struct dc_stream *stream)
-+{
-+	return stream->sink->sink_signal;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 1cd0883..61f13bd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -430,20 +430,10 @@ void dc_resume(const struct dc *dc);
- 
- const struct ddc_service *dc_get_ddc_at_index(
- 		struct dc *dc, uint32_t link_index);
--const struct dc_ddc* dc_get_ddc_from_sink(const struct dc_sink* sink);
--const struct dc_ddc* dc_get_ddc_from_link(const struct dc_link* link);
--bool dc_ddc_query_i2c(const struct dc_ddc* ddc,
--		uint32_t address,
--		uint8_t* write_buf,
--		uint32_t write_size,
--		uint8_t* read_buf,
--		uint32_t read_size);
--bool dc_ddc_dpcd_read(const struct dc_ddc* ddc, uint32_t address,
--		uint8_t* data, uint32_t len);
--bool dc_ddc_dpcd_write(const struct dc_ddc* ddc, uint32_t address,
--		const uint8_t* data, uint32_t len);
--
- 
-+/*
-+ * DPCD access interfaces
-+ */
- 
- bool dc_read_dpcd(
- 		struct dc *dc,
-@@ -459,4 +449,14 @@ bool dc_write_dpcd(
- 		const uint8_t *data,
- 	uint32_t size);
- 
-+
-+uint8_t dc_get_dig_index(const struct dc_stream *stream);
-+
-+enum signal_type  dc_get_display_signal(
-+		const struct dc_stream *stream);
-+
-+enum gpio_ddc_line dc_get_ddc_line(
-+		const struct dc_stream *stream);
-+
-+
- #endif /* DC_INTERFACE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0763-drm-amd-dal-Add-hpd-filter-delay-for-DP-hotplug.patch b/common/recipes-kernel/linux/files/0763-drm-amd-dal-Add-hpd-filter-delay-for-DP-hotplug.patch
deleted file mode 100644
index ccec282a..00000000
--- a/common/recipes-kernel/linux/files/0763-drm-amd-dal-Add-hpd-filter-delay-for-DP-hotplug.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 0fda37e836873f9f2e2cbaa244d43d929d20a760 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 2 Feb 2016 17:28:12 -0500
-Subject: [PATCH 0763/1110] drm/amd/dal: Add hpd filter delay for DP hotplug
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 25 ++++++++++++++-----------
- 1 file changed, 14 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 2db5147..b0ef028 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -45,9 +45,6 @@
- 		LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_HOTPLUG, \
- 		__VA_ARGS__)
- 
--#define DELAY_ON_CONNECT_IN_MS 500
--#define DELAY_ON_DISCONNECT_IN_MS 100
--
- 
- /*******************************************************************************
-  * Private structures
-@@ -89,20 +86,28 @@ static bool program_hpd_filter(
- 
- 	struct irq *hpd;
- 
--	/* Verify feature is supported */
-+	int delay_on_connect_in_ms = 0;
-+	int delay_on_disconnect_in_ms = 0;
- 
-+	/* Verify feature is supported */
- 	switch (link->public.connector_signal) {
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
--		/* program hpd filter */
-+		/* Program hpd filter */
-+		delay_on_connect_in_ms = 500;
-+		delay_on_disconnect_in_ms = 100;
- 		break;
--	case SIGNAL_TYPE_LVDS:
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* Program hpd filter to allow DP signal to settle */
-+		delay_on_connect_in_ms = 20;
-+		delay_on_disconnect_in_ms = 0;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
- 	case SIGNAL_TYPE_EDP:
- 	default:
--		/* don't program hpd filter */
-+		/* Don't program hpd filter */
- 		return false;
- 	}
- 
-@@ -114,12 +119,11 @@ static bool program_hpd_filter(
- 		return result;
- 
- 	/* Setup HPD filtering */
--
- 	if (dal_irq_open(hpd) == GPIO_RESULT_OK) {
- 		struct gpio_hpd_config config;
- 
--		config.delay_on_connect = DELAY_ON_CONNECT_IN_MS;
--		config.delay_on_disconnect = DELAY_ON_DISCONNECT_IN_MS;
-+		config.delay_on_connect = delay_on_connect_in_ms;
-+		config.delay_on_disconnect = delay_on_disconnect_in_ms;
- 
- 		dal_irq_setup_hpd_filter(hpd, &config);
- 
-@@ -131,7 +135,6 @@ static bool program_hpd_filter(
- 	}
- 
- 	/* Release HPD handle */
--
- 	dal_adapter_service_release_irq(link->adapter_srv, hpd);
- 
- 	return result;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0764-drm-amd-dal-Add-gpio-types-compile-dependency-on-in-.patch b/common/recipes-kernel/linux/files/0764-drm-amd-dal-Add-gpio-types-compile-dependency-on-in-.patch
deleted file mode 100644
index aaa6e430..00000000
--- a/common/recipes-kernel/linux/files/0764-drm-amd-dal-Add-gpio-types-compile-dependency-on-in-.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From d490d8285eeb61e29c0fc70a4661107e71931e25 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Wed, 3 Feb 2016 11:56:21 -0500
-Subject: [PATCH 0764/1110] drm/amd/dal: Add gpio types compile dependency on
- in dc.h.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 61f13bd..70fd7d2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -30,6 +30,7 @@
- #include "dal_types.h"
- #include "audio_types.h"
- #include "logger_types.h"
-+#include "gpio_types.h"
- 
- #define MAX_SINKS_PER_LINK 4
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0765-drm-amd-dal-only-poll-for-ACT-when-needed.patch b/common/recipes-kernel/linux/files/0765-drm-amd-dal-only-poll-for-ACT-when-needed.patch
deleted file mode 100644
index 23a9f4b0..00000000
--- a/common/recipes-kernel/linux/files/0765-drm-amd-dal-only-poll-for-ACT-when-needed.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 7157a789df9f56b32ee4591bb6a07f4740d2c662 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 3 Feb 2016 17:09:35 -0500
-Subject: [PATCH 0765/1110] drm/amd/dal: only poll for ACT when needed
-
-Should not poll for ACT change state when nothing
-changed actually, because ACT will not change
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 71fa7b1..2a92cfd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -753,6 +753,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- {
- 	struct core_stream *stream =
- 			context->res_ctx.controller_ctx[controller_idx].stream;
-+	struct core_stream *old_stream =
-+		dc->current_context.res_ctx.controller_ctx[controller_idx].stream;
- 	struct output_pixel_processor *opp =
- 		context->res_ctx.pool.opps[controller_idx];
- 	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
-@@ -765,7 +767,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		 */
- 		stream->tg->funcs->set_blank(stream->tg, true);
- 
--		core_link_disable_stream(stream->sink->link, stream);
-+		/*
-+		 * only disable stream in case it was ever enabled
-+		 */
-+		if (old_stream)
-+			core_link_disable_stream(
-+				old_stream->sink->link,
-+				old_stream);
- 
- 		/*TODO: AUTO check if timing changed*/
- 		if (false == stream->clock_source->funcs->program_pix_clk(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch b/common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch
deleted file mode 100644
index 0d3317d8..00000000
--- a/common/recipes-kernel/linux/files/0766-drm-amd-dal-add-HBR3-definitions.patch
+++ /dev/null
@@ -1,305 +0,0 @@
-From 9dc947a01ca2df8de3acaabca5af1f5e037356bb Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 3 Feb 2016 17:20:29 -0500
-Subject: [PATCH 0766/1110] drm/amd/dal: add HBR3 definitions
-
-Also enable TP3 usage during link training
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 50 ++++++++++++++++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  3 ++
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 13 +++---
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  4 ++
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  1 +
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |  2 +
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h        |  8 ++--
- .../gpu/drm/amd/dal/include/link_service_types.h   |  8 +++-
- 8 files changed, 70 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 742ab75..83d5e03 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -162,6 +162,9 @@ static enum dpcd_training_patterns
- 	case HW_DP_TRAINING_PATTERN_3:
- 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
- 		break;
-+	case HW_DP_TRAINING_PATTERN_4:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
-+		break;
- 	default:
- 		ASSERT(0);
- 		dal_logger_write(link->ctx->logger,
-@@ -720,6 +723,29 @@ static bool perform_post_lt_adj_req_sequence(
- 
- }
- 
-+static enum hw_dp_training_pattern get_supported_tp(struct core_link *link)
-+{
-+	enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
-+	struct encoder_feature_support *features = &link->link_enc->features;
-+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
-+
-+	if (features->flags.bits.IS_TPS3_CAPABLE)
-+		highest_tp = HW_DP_TRAINING_PATTERN_3;
-+
-+	if (features->flags.bits.IS_TPS4_CAPABLE)
-+		highest_tp = HW_DP_TRAINING_PATTERN_4;
-+
-+	if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
-+		highest_tp >= HW_DP_TRAINING_PATTERN_4)
-+		return HW_DP_TRAINING_PATTERN_4;
-+
-+	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
-+		highest_tp >= HW_DP_TRAINING_PATTERN_3)
-+		return HW_DP_TRAINING_PATTERN_3;
-+
-+	return HW_DP_TRAINING_PATTERN_2;
-+}
-+
- static bool perform_channel_equalization_sequence(
- 	struct core_link *link,
- 	struct link_training_settings *lt_settings)
-@@ -731,8 +757,7 @@ static bool perform_channel_equalization_sequence(
- 	union lane_align_status_updated dpcd_lane_status_updated = {{0}};
- 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
- 
--	/*TODO hw_tr_pattern = HW_DP_TRAINING_PATTERN_3;*/
--	hw_tr_pattern = HW_DP_TRAINING_PATTERN_2;
-+	hw_tr_pattern = get_supported_tp(link);
- 
- 	dp_set_hw_training_pattern(link, hw_tr_pattern);
- 
-@@ -1031,6 +1056,18 @@ static bool exceeded_limit_link_setting(const struct link_settings *link_setting
- 				 true : false);
- }
- 
-+static enum link_rate get_max_link_rate(struct core_link *link)
-+{
-+	enum link_rate max_link_rate = LINK_RATE_HIGH;
-+
-+	if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
-+		max_link_rate = LINK_RATE_HIGH2;
-+
-+	if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
-+		max_link_rate = LINK_RATE_HIGH3;
-+
-+	return max_link_rate;
-+}
- 
- bool dp_hbr_verify_link_cap(
- 	struct core_link *link,
-@@ -1048,7 +1085,7 @@ bool dp_hbr_verify_link_cap(
- 
- 	/* TODO confirm this is correct for cz */
- 	max_link_cap.lane_count = LANE_COUNT_FOUR;
--	max_link_cap.link_rate = LINK_RATE_HIGH2;
-+	max_link_cap.link_rate = get_max_link_rate(link);
- 	max_link_cap.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
- 
- 	/* TODO implement override and monitor patch later */
-@@ -1641,7 +1678,6 @@ static void retrieve_link_cap(struct core_link *link)
- 
- 	union down_stream_port_count down_strm_port_count;
- 	union edp_configuration_cap edp_config_cap;
--	union max_down_spread max_down_spread;
- 	union dp_downstream_port_present ds_port = { 0 };
- 
- 	dm_memset(dpcd_data, '\0', sizeof(dpcd_data));
-@@ -1649,8 +1685,6 @@ static void retrieve_link_cap(struct core_link *link)
- 		'\0', sizeof(union down_stream_port_count));
- 	dm_memset(&edp_config_cap, '\0',
- 		sizeof(union edp_configuration_cap));
--	dm_memset(&max_down_spread, '\0',
--		sizeof(union max_down_spread));
- 
- 	core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV,
- 			dpcd_data, sizeof(dpcd_data));
-@@ -1671,7 +1705,7 @@ static void retrieve_link_cap(struct core_link *link)
- 	link->dpcd_caps.max_ln_count.raw = dpcd_data[
- 		DPCD_ADDRESS_MAX_LANE_COUNT - DPCD_ADDRESS_DPCD_REV];
- 
--	max_down_spread.raw = dpcd_data[
-+	link->dpcd_caps.max_down_spread.raw = dpcd_data[
- 		DPCD_ADDRESS_MAX_DOWNSPREAD - DPCD_ADDRESS_DPCD_REV];
- 
- 	link->reported_link_cap.lane_count =
-@@ -1679,7 +1713,7 @@ static void retrieve_link_cap(struct core_link *link)
- 	link->reported_link_cap.link_rate = dpcd_data[
- 		DPCD_ADDRESS_MAX_LINK_RATE - DPCD_ADDRESS_DPCD_REV];
- 	link->reported_link_cap.link_spread =
--		max_down_spread.bits.MAX_DOWN_SPREAD ?
-+		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
- 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
- 
- 	edp_config_cap.raw = dpcd_data[
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 39aa734..e8f4ec8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -120,6 +120,9 @@ bool dp_set_hw_training_pattern(
- 	case HW_DP_TRAINING_PATTERN_3:
- 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
- 		break;
-+	case HW_DP_TRAINING_PATTERN_4:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
-+		break;
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index f714215..78460fc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -279,12 +279,13 @@ static void set_link_training_complete(
- 	dm_write_reg(ctx, addr, value);
- }
- 
--static void set_dp_phy_pattern_training_pattern(
--	struct dce110_link_encoder *enc110,
-+void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
-+	struct link_encoder *enc,
- 	uint32_t index)
- {
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	/* Write Training Pattern */
--	struct dc_context *ctx = enc110->base.ctx;
-+	struct dc_context *ctx = enc->ctx;
- 	uint32_t addr = LINK_REG(DP_DPHY_TRAINING_PATTERN_SEL);
- 
- 	dm_write_reg(ctx, addr, index);
-@@ -1555,13 +1556,13 @@ void dce110_link_encoder_dp_set_phy_pattern(
- 
- 	switch (param->dp_phy_pattern) {
- 	case DP_TEST_PATTERN_TRAINING_PATTERN1:
--		set_dp_phy_pattern_training_pattern(enc110, 0);
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
- 		break;
- 	case DP_TEST_PATTERN_TRAINING_PATTERN2:
--		set_dp_phy_pattern_training_pattern(enc110, 1);
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
- 		break;
- 	case DP_TEST_PATTERN_TRAINING_PATTERN3:
--		set_dp_phy_pattern_training_pattern(enc110, 2);
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
- 		break;
- 	case DP_TEST_PATTERN_D102:
- 		set_dp_phy_pattern_d102(enc110);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 46e2971..1269833 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -152,5 +152,9 @@ void dce110_link_encoder_connect_dig_be_to_fe(
- 	enum engine_id engine,
- 	bool connect);
- 
-+void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
-+	struct link_encoder *enc,
-+	uint32_t index);
-+
- 
- #endif /* __DC_LINK_ENCODER__DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 7d63ebb..17155e3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -174,6 +174,7 @@ struct link_caps {
- struct dpcd_caps {
- 	union dpcd_rev dpcd_rev;
- 	union max_lane_count max_ln_count;
-+	union max_down_spread max_down_spread;
- 
- 	/* dongle type (DP converter, CV smart dongle) */
- 	enum display_dongle_type dongle_type;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index ab99b27..1f53c8f 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -45,8 +45,10 @@ struct encoder_feature_support {
- 			 * for external DP chip supported */
- 			uint32_t CPLIB_DP_AUTHENTICATION:1;
- 			uint32_t IS_HBR2_CAPABLE:1;
-+			uint32_t IS_HBR3_CAPABLE:1;
- 			uint32_t IS_HBR2_VALIDATED:1;
- 			uint32_t IS_TPS3_CAPABLE:1;
-+			uint32_t IS_TPS4_CAPABLE:1;
- 			uint32_t IS_AUDIO_CAPABLE:1;
- 			uint32_t IS_VCE_SUPPORTED:1;
- 			uint32_t IS_CONVERTER:1;
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index bd410cc..deaf506 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -241,7 +241,8 @@ enum dpcd_address {
- enum dpcd_revision {
- 	DPCD_REV_10 = 0x10,
- 	DPCD_REV_11 = 0x11,
--	DPCD_REV_12 = 0x12
-+	DPCD_REV_12 = 0x12,
-+	DPCD_REV_13 = 0x13
- };
- 
- enum dp_pwr_state {
-@@ -341,7 +342,8 @@ enum dpcd_training_patterns {
- 	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
- 	DPCD_TRAINING_PATTERN_1,
- 	DPCD_TRAINING_PATTERN_2,
--	DPCD_TRAINING_PATTERN_3
-+	DPCD_TRAINING_PATTERN_3,
-+	DPCD_TRAINING_PATTERN_4 = 7
- };
- 
- /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
-@@ -394,7 +396,7 @@ union max_down_spread {
- 		uint8_t MAX_DOWN_SPREAD:1;
- 		uint8_t RESERVED:5;
- 		uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
--		uint8_t RESERVED1:1;
-+		uint8_t TPS4_SUPPORTED:1;
- 	} bits;
- 	uint8_t raw;
- };
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index d2e6256..7db598b 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -123,13 +123,15 @@ enum lane_count {
-  * 270MBps for 2.70GHz,
-  * 324MBps for 3.24Ghz,
-  * 540MBps for 5.40GHz
-+ * 810MBps for 8.10GHz
-  */
- enum link_rate {
- 	LINK_RATE_UNKNOWN = 0,
- 	LINK_RATE_LOW = 0x06,
- 	LINK_RATE_HIGH = 0x0A,
- 	LINK_RATE_RBR2 = 0x0C,
--	LINK_RATE_HIGH2 = 0x14
-+	LINK_RATE_HIGH2 = 0x14,
-+	LINK_RATE_HIGH3 = 0x1E
- };
- 
- enum {
-@@ -205,7 +207,8 @@ struct link_training_settings {
- enum hw_dp_training_pattern {
- 	HW_DP_TRAINING_PATTERN_1 = 0,
- 	HW_DP_TRAINING_PATTERN_2,
--	HW_DP_TRAINING_PATTERN_3
-+	HW_DP_TRAINING_PATTERN_3,
-+	HW_DP_TRAINING_PATTERN_4
- };
- 
- /*TODO: Move this enum test harness*/
-@@ -226,6 +229,7 @@ enum dp_test_pattern {
- 	DP_TEST_PATTERN_TRAINING_PATTERN1,
- 	DP_TEST_PATTERN_TRAINING_PATTERN2,
- 	DP_TEST_PATTERN_TRAINING_PATTERN3,
-+	DP_TEST_PATTERN_TRAINING_PATTERN4,
- 
- 	/* link test patterns*/
- 	DP_TEST_PATTERN_COLOR_SQUARES,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0767-drm-amd-dal-Rename-allocate-mem-input-interface.patch b/common/recipes-kernel/linux/files/0767-drm-amd-dal-Rename-allocate-mem-input-interface.patch
deleted file mode 100644
index 0642c9e7..00000000
--- a/common/recipes-kernel/linux/files/0767-drm-amd-dal-Rename-allocate-mem-input-interface.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 3d99b4a3d41a066425d17e4d4b50ea96fce13248 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 3 Feb 2016 11:48:01 -0500
-Subject: [PATCH 0767/1110] drm/amd/dal: Rename allocate mem input interface.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c    | 9 ++++-----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h    | 8 ++++----
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h              | 4 ++--
- 4 files changed, 12 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 2a92cfd..6ae14d9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -791,7 +791,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	}
- 
- 	/*TODO: mst support - use total stream count*/
--	stream->mi->funcs->mem_input_allocate_dmif_buffer(
-+	stream->mi->funcs->allocate_mem_input(
- 					stream->mi,
- 					&stream->public.timing,
- 					context->target_count);
-@@ -1507,7 +1507,7 @@ static void reset_single_stream_hw_ctx(
- 
- 	stream->tg->funcs->set_blank(stream->tg, true);
- 	stream->tg->funcs->disable_crtc(stream->tg);
--	stream->mi->funcs->mem_input_deallocate_dmif_buffer(
-+	stream->mi->funcs->free_mem_input(
- 			stream->mi, context->target_count);
- 	stream->xfm->funcs->transform_set_scaler_bypass(stream->xfm);
- 	unreference_clock_source(&context->res_ctx, stream->clock_source);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 3a928e6..6d88afe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -760,7 +760,7 @@ static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
- 	return frame_time;
- }
- 
--void dce110_mem_input_allocate_dmif_buffer(
-+void dce110_allocate_mem_input(
- 		struct mem_input *mi,
- 		struct dc_crtc_timing *timing,
- 		uint32_t paths_num)
-@@ -884,7 +884,7 @@ static void deallocate_dmif_buffer_helper(
- 			DMIF_BUFFERS_ALLOCATION_COMPLETED));
- }
- 
--void dce110_mem_input_deallocate_dmif_buffer(
-+void dce110_free_mem_input(
- 	struct mem_input *mi, uint32_t paths_num)
- {
- 	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
-@@ -925,9 +925,8 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
- 			dce110_mem_input_program_safe_display_marks,
- 	.mem_input_program_display_marks =
- 			dce110_mem_input_program_display_marks,
--	.mem_input_allocate_dmif_buffer = dce110_mem_input_allocate_dmif_buffer,
--	.mem_input_deallocate_dmif_buffer =
--			dce110_mem_input_deallocate_dmif_buffer,
-+	.allocate_mem_input = dce110_allocate_mem_input,
-+	.free_mem_input = dce110_free_mem_input,
- 	.mem_input_program_surface_flip_and_addr =
- 			dce110_mem_input_program_surface_flip_and_addr,
- 	.mem_input_program_surface_config =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 5a4e5fe..ec83ee1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -72,22 +72,22 @@ void dce110_mem_input_program_display_marks(
- 	uint32_t pstate_blackout_duration_ns);
- 
- /*
-- * dce110_mem_input_allocate_dmif_buffer
-+ * dce110_allocate_mem_input
-  *
-  * This function will allocate a dmif buffer and program required
-  * pixel duration for pipe
-  */
--void dce110_mem_input_allocate_dmif_buffer(
-+void dce110_allocate_mem_input(
- 		struct mem_input *mem_input,
- 		struct dc_crtc_timing *timing,
- 		uint32_t paths_num);
- 
- /*
-- * dce110_mem_input_deallocate_dmif_buffer
-+ * dce110_free_mem_input
-  *
-  * This function will deallocate a dmif buffer from pipe
-  */
--void dce110_mem_input_deallocate_dmif_buffer(
-+void dce110_free_mem_input(
- 	struct mem_input *mem_input, uint32_t paths_num);
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 7d6335d..cace055 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -44,11 +44,11 @@ struct mem_input_funcs {
- 		uint32_t h_total,
- 		uint32_t pixel_clk_in_khz,
- 		uint32_t pstate_blackout_duration_ns);
--	void (*mem_input_allocate_dmif_buffer)(
-+	void (*allocate_mem_input)(
- 			struct mem_input *mem_input,
- 			struct dc_crtc_timing *timing,
- 			uint32_t paths_num);
--	void (*mem_input_deallocate_dmif_buffer)(
-+	void (*free_mem_input)(
- 		struct mem_input *mem_input, uint32_t paths_num);
- 	bool (*mem_input_program_surface_flip_and_addr)(
- 		struct mem_input *mem_input,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0768-drm-amd-dal-fix-azalia-audio-does-not-work-on-some-b.patch b/common/recipes-kernel/linux/files/0768-drm-amd-dal-fix-azalia-audio-does-not-work-on-some-b.patch
deleted file mode 100644
index 0d94586a..00000000
--- a/common/recipes-kernel/linux/files/0768-drm-amd-dal-fix-azalia-audio-does-not-work-on-some-b.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From b6470ff3cf154a15bdfbfac7204f3de1840f881a Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Tue, 2 Feb 2016 12:36:40 -0500
-Subject: [PATCH 0768/1110] drm/amd/dal: fix azalia audio does not work on some
- board configuration
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-index f24b964..50f2e66 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -52,7 +52,9 @@ static const uint32_t engine_offset[] = {
- 	0,
- 	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
- 	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
--	mmDIG3_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
-+	mmDIG3_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG4_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG5_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
- };
- 
- static void destruct(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0769-drm-amd-dal-Use-ENGINE_ID_UNKNOWN-for-engine_id.patch b/common/recipes-kernel/linux/files/0769-drm-amd-dal-Use-ENGINE_ID_UNKNOWN-for-engine_id.patch
deleted file mode 100644
index d5e7927f..00000000
--- a/common/recipes-kernel/linux/files/0769-drm-amd-dal-Use-ENGINE_ID_UNKNOWN-for-engine_id.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 4212bae06733b42b07ec93c6a7e8ba41293741bb Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Fri, 5 Feb 2016 09:56:10 -0500
-Subject: [PATCH 0769/1110] drm/amd/dal: Use ENGINE_ID_UNKNOWN for engine_id
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 78460fc..7f663de 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1368,7 +1368,7 @@ void dce110_link_encoder_enable_dp_output(
- 	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = enc->preferred_engine;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
-@@ -1411,7 +1411,7 @@ void dce110_link_encoder_enable_dp_mst_output(
- 	configure_encoder(enc110, link_settings);
- 
- 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
--	cntl.engine_id = enc->preferred_engine;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
- 	cntl.transmitter = enc110->base.transmitter;
- 	cntl.pll_id = clock_source;
- 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch b/common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch
deleted file mode 100644
index 0f8a5d26..00000000
--- a/common/recipes-kernel/linux/files/0770-drm-amd-dal-Force-bw-programming-for-DCE-10-until-we.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 8d6ca8f203b0911f9916825d80a98cf5a57fa859 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Thu, 4 Feb 2016 18:04:18 -0500
-Subject: [PATCH 0770/1110] drm/amd/dal: Force bw programming for DCE 10 until
- we start calculate BW.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    | 28 ----------------------
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  3 ++-
- 2 files changed, 2 insertions(+), 29 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index 82c5e15..a1dbac4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -335,33 +335,6 @@ static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool ena
- 	}
- }
- 
--/**
-- * Call display_engine_clock_dce80 to perform the Dclk programming.
-- */
--static void set_display_clock(struct validate_context *context)
--{
--	/* Program the display engine clock.
--	 * Check DFS bypass mode support or not. DFSbypass feature is only when
--	 * BIOS GPU info table reports support. */
--
--	if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
--		/*TODO: set_display_clock_dfs_bypass(
--				hws,
--				path_set,
--				context->res_ctx.pool.display_clock,
--				context->res_ctx.min_clocks.min_dclk_khz);*/
--	} else
--		dal_display_clock_set_clock(context->res_ctx.pool.display_clock,
--				681000);
--
--	/* TODO: When changing display engine clock, DMCU WaitLoop must be
--	 * reconfigured in order to maintain the same delays within DMCU
--	 * programming sequences. */
--
--	/* TODO: Start GTC counter */
--}
--
--
- static void set_displaymarks(
- 		const struct dc *dc, struct validate_context *context)
- {
-@@ -381,7 +354,6 @@ bool dce100_hw_sequencer_construct(struct dc *dc)
- 	dc->hwss.enable_fe_clock = dce100_enable_fe_clock;
- 	dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
- 	dc->hwss.set_blender_mode = dce100_set_blender_mode;
--	dc->hwss.set_display_clock = set_display_clock;
- 	dc->hwss.set_displaymarks = set_displaymarks;
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index e67ba81..783d47e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -773,7 +773,8 @@ enum dc_status dce100_validate_bandwidth(
- 	const struct dc *dc,
- 	struct validate_context *context)
- {
--	/* TODO implement when needed */
-+	/* TODO implement when needed but for now hardcode max value*/
-+	context->bw_results.dispclk_khz = 681000;
- 
- 	return DC_OK;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0771-drm-amd-dal-remove-dm_services_types.h-from-DC-heade.patch b/common/recipes-kernel/linux/files/0771-drm-amd-dal-remove-dm_services_types.h-from-DC-heade.patch
deleted file mode 100644
index a47e7826..00000000
--- a/common/recipes-kernel/linux/files/0771-drm-amd-dal-remove-dm_services_types.h-from-DC-heade.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 4c9385a12361d3edaeddc4d90d92d1ea7ee75a9f Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 5 Feb 2016 10:03:23 -0500
-Subject: [PATCH 0771/1110] drm/amd/dal: remove dm_services_types.h from DC
- headers
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_types.h        | 1 -
- drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h | 1 -
- drivers/gpu/drm/amd/dal/dc/inc/opp.h         | 1 -
- drivers/gpu/drm/amd/dal/include/fixed32_32.h | 2 --
- 4 files changed, 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index c238531..21aad94 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -25,7 +25,6 @@
- #ifndef DC_TYPES_H_
- #define DC_TYPES_H_
- 
--#include "dm_services_types.h"
- #include "fixed32_32.h"
- #include "fixed31_32.h"
- #include "irq_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-index 17cb10f..ad21db5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-@@ -27,7 +27,6 @@
- #define GAMMA_TYPES_H_
- 
- #include "dc_types.h"
--#include "dm_services_types.h"
- 
- /* TODO: Used in IPP and OPP */
- struct dev_c_lut {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index b097983..3071df6 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -29,7 +29,6 @@
- #include "dc_types.h"
- #include "grph_object_id.h"
- #include "grph_csc_types.h"
--#include "dm_services_types.h"
- 
- struct fixed31_32;
- struct gamma_parameters;
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-index f393e95..5fca957 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
-@@ -26,8 +26,6 @@
- #ifndef __DAL_FIXED32_32_H__
- #define __DAL_FIXED32_32_H__
- 
--#include "dm_services_types.h"
--
- struct fixed32_32 {
- 	uint64_t value;
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0772-drm-amd-dal-Move-link-settings-to-public-interface.patch b/common/recipes-kernel/linux/files/0772-drm-amd-dal-Move-link-settings-to-public-interface.patch
deleted file mode 100644
index 399d87e3..00000000
--- a/common/recipes-kernel/linux/files/0772-drm-amd-dal-Move-link-settings-to-public-interface.patch
+++ /dev/null
@@ -1,332 +0,0 @@
-From 5f22fe3b2e8832d59299095cd32be5a95ebe8bea Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Fri, 5 Feb 2016 12:43:22 -0500
-Subject: [PATCH 0772/1110] drm/amd/dal: Move link settings to public interface
-
-DC to move lane_settings to public
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  8 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 55 +++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  4 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  2 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  9 ++++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  5 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  7 ---
- 7 files changed, 47 insertions(+), 43 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index b0ef028..c1e3d33 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1160,7 +1160,7 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 			skip_video_pattern = false;
- 
- 	if (perform_link_training(link, &link_settings, skip_video_pattern)) {
--		link->cur_link_settings = link_settings;
-+		link->public.cur_link_settings = link_settings;
- 		status = DC_OK;
- 	}
- 	else
-@@ -1176,7 +1176,7 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- 	/* sink signal type after MST branch is MST. Multiple MST sinks
- 	 * share one link. Link DP PHY is enable or training only once.
- 	 */
--	if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
-+	if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
- 		return DC_OK;
- 
- 	return enable_link_dp(stream);
-@@ -1214,7 +1214,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- 			normalized_pix_clk,
- 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
- 
--	dm_memset(&stream->sink->link->cur_link_settings, 0,
-+	dm_memset(&stream->sink->link->public.cur_link_settings, 0,
- 			sizeof(struct link_settings));
- 
- 	link->link_enc->funcs->enable_tmds_output(
-@@ -1342,7 +1342,7 @@ void core_link_resume(struct core_link *link)
- static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
- {
- 	struct link_settings *link_settings =
--			&stream->sink->link->cur_link_settings;
-+			&stream->sink->link->public.cur_link_settings;
- 	uint32_t link_rate_in_mbps =
- 			link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
- 	struct fixed31_32 mbps = dal_fixed31_32_from_int(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 83d5e03..54d1f9f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -277,7 +277,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 				dpcd_lt_buffer,
- 				size_in_bytes + sizeof(dpcd_pattern.raw) );
- 
--	link->ln_setting = lt_settings->lane_settings[0];
-+	link->public.ln_setting = lt_settings->lane_settings[0];
- }
- 
- static bool is_cr_done(enum lane_count ln_count,
-@@ -599,7 +599,7 @@ static void dpcd_set_lane_settings(
- 		dpcd_lane[0].bits.MAX_SWING_REACHED,
- 		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
- 
--	link->ln_setting = link_training_setting->lane_settings[0];
-+	link->public.ln_setting = link_training_setting->lane_settings[0];
- 
- }
- 
-@@ -1142,7 +1142,7 @@ bool dp_hbr_verify_link_cap(
- 		}
- 
- 		if (success)
--			link->verified_link_cap = *cur;
-+			link->public.verified_link_cap = *cur;
- 
- 		/* always disable the link before trying another
- 		 * setting or before returning we'll enable it later
-@@ -1158,14 +1158,14 @@ bool dp_hbr_verify_link_cap(
- 		/* If all LT fails for all settings,
- 		 * set verified = failed safe (1 lane low)
- 		 */
--		link->verified_link_cap.lane_count = LANE_COUNT_ONE;
--		link->verified_link_cap.link_rate = LINK_RATE_LOW;
-+		link->public.verified_link_cap.lane_count = LANE_COUNT_ONE;
-+		link->public.verified_link_cap.link_rate = LINK_RATE_LOW;
- 
--		link->verified_link_cap.link_spread =
-+		link->public.verified_link_cap.link_spread =
- 		LINK_SPREAD_DISABLED;
- 	}
- 
--	link->max_link_setting = link->verified_link_cap;
-+	link->public.max_link_setting = link->public.verified_link_cap;
- 
- 	return success;
- }
-@@ -1244,12 +1244,12 @@ bool dp_validate_mode_timing(
- 	/* For static validation we always use reported
- 	 * link settings for other cases, when no modelist
- 	 * changed we can use verified link setting*/
--	link_setting = &link->reported_link_cap;
-+	link_setting = &link->public.reported_link_cap;
- 
- 	/* TODO: DYNAMIC_VALIDATION needs to be implemented */
- 	/*if (flags.DYNAMIC_VALIDATION == 1 &&
--		link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
--		link_setting = &link->verified_link_cap;
-+		link->public.verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
-+		link_setting = &link->public.verified_link_cap;
- 	*/
- 
- 	req_bw = bandwidth_in_kbps_from_timing(timing);
-@@ -1292,15 +1292,15 @@ void decide_link_settings(struct core_stream *stream,
- 	 */
- 	link = stream->sink->link;
- 
--	if ((link->reported_link_cap.lane_count != LANE_COUNT_UNKNOWN) &&
--		(link->reported_link_cap.link_rate <=
--				link->verified_link_cap.link_rate)) {
-+	if ((link->public.reported_link_cap.lane_count != LANE_COUNT_UNKNOWN) &&
-+		(link->public.reported_link_cap.link_rate <=
-+				link->public.verified_link_cap.link_rate)) {
- 
- 		link_bw = bandwidth_in_kbps_from_link_settings(
--				&link->reported_link_cap);
-+				&link->public.reported_link_cap);
- 
- 		if (req_bw < link_bw) {
--			*link_setting = link->reported_link_cap;
-+			*link_setting = link->public.reported_link_cap;
- 			return;
- 		}
- 	}
-@@ -1319,7 +1319,7 @@ void decide_link_settings(struct core_stream *stream,
- 		if (req_bw < link_bw) {
- 			if (is_link_setting_supported(
- 				cur_ls,
--				&link->max_link_setting)) {
-+				&link->public.max_link_setting)) {
- 				*link_setting = *cur_ls;
- 				return;
- 			}
-@@ -1327,10 +1327,10 @@ void decide_link_settings(struct core_stream *stream,
- 	}
- 
- 	BREAK_TO_DEBUGGER();
--	ASSERT(link->verified_link_cap.lane_count !=
-+	ASSERT(link->public.verified_link_cap.lane_count !=
- 		LANE_COUNT_UNKNOWN);
- 
--	*link_setting = link->verified_link_cap;
-+	*link_setting = link->public.verified_link_cap;
- }
- 
- /*************************Short Pulse IRQ***************************/
-@@ -1349,7 +1349,7 @@ static bool hpd_rx_irq_check_link_loss_status(
- 	sink_status_changed = false;
- 	return_code = false;
- 
--	if (link->cur_link_settings.lane_count == 0)
-+	if (link->public.cur_link_settings.lane_count == 0)
- 		return return_code;
- 	/*1. Check that we can handle interrupt: Not in FS DOS,
- 	 *  Not in "Display Timeout" state, Link is trained.
-@@ -1375,7 +1375,7 @@ static bool hpd_rx_irq_check_link_loss_status(
- 
- 		/*parse lane status*/
- 		for (lane = 0;
--			lane < link->cur_link_settings.lane_count;
-+			lane < link->public.cur_link_settings.lane_count;
- 			lane++) {
- 
- 			/* check status of lanes 0,1
-@@ -1441,7 +1441,7 @@ static bool allow_hpd_rx_irq(const struct core_link *link)
- 	 * 3) We know we're dealing with an active dongle
- 	 */
- 
--	if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
-+	if ((link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
- 		(link->public.type == dc_connection_mst_branch) ||
- 		is_dp_active_dongle(link))
- 		return true;
-@@ -1502,7 +1502,8 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 	if (hpd_rx_irq_check_link_loss_status(
- 		link,
- 		&hpd_irq_dpcd_data)) {
--		perform_link_training(link, &link->cur_link_settings, true);
-+		perform_link_training(link,
-+			&link->public.cur_link_settings, true);
- 		status = false;
- 	}
- 
-@@ -1708,11 +1709,11 @@ static void retrieve_link_cap(struct core_link *link)
- 	link->dpcd_caps.max_down_spread.raw = dpcd_data[
- 		DPCD_ADDRESS_MAX_DOWNSPREAD - DPCD_ADDRESS_DPCD_REV];
- 
--	link->reported_link_cap.lane_count =
-+	link->public.reported_link_cap.lane_count =
- 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
--	link->reported_link_cap.link_rate = dpcd_data[
-+	link->public.reported_link_cap.link_rate = dpcd_data[
- 		DPCD_ADDRESS_MAX_LINK_RATE - DPCD_ADDRESS_DPCD_REV];
--	link->reported_link_cap.link_spread =
-+	link->public.reported_link_cap.link_spread =
- 		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
- 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
- 
-@@ -1753,10 +1754,10 @@ void detect_dp_sink_caps(struct core_link *link)
- 	 */
- 
- 	if (is_mst_supported(link)) {
--		link->verified_link_cap = link->reported_link_cap;
-+		link->public.verified_link_cap = link->public.reported_link_cap;
- 	} else {
- 		dp_hbr_verify_link_cap(link,
--			&link->reported_link_cap);
-+			&link->public.reported_link_cap);
- 	}
- 	/* TODO save sink caps in link->sink */
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index e8f4ec8..2d78e52 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -89,8 +89,8 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 	link->link_enc->funcs->disable_output(link->link_enc, signal);
- 
- 	/* Clear current link setting.*/
--	dm_memset(&link->cur_link_settings, 0,
--			sizeof(link->cur_link_settings));
-+	dm_memset(&link->public.cur_link_settings, 0,
-+			sizeof(link->public.cur_link_settings));
- }
- 
- void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 8cb756e..6375678 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -500,7 +500,7 @@ static void fill_display_configs(
- 			cfg->transmitter =
- 				stream->sink->link->link_enc->transmitter;
- 			cfg->link_settings =
--					stream->sink->link->cur_link_settings;
-+				stream->sink->link->public.cur_link_settings;
- 			cfg->sym_clock = stream->public.timing.pix_clk_khz;
- 			switch (stream->public.timing.display_color_depth) {
- 			case COLOR_DEPTH_101010:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 70fd7d2..45d39c7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -31,6 +31,7 @@
- #include "audio_types.h"
- #include "logger_types.h"
- #include "gpio_types.h"
-+#include "link_service_types.h"
- 
- #define MAX_SINKS_PER_LINK 4
- 
-@@ -280,6 +281,14 @@ struct dc_link {
- 	enum signal_type connector_signal;
- 	enum dc_irq_source irq_source_hpd;
- 	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
-+	/* caps is the same as reported_link_cap. link_traing use
-+	 * reported_link_cap. Will clean up.  TODO
-+	 */
-+	struct link_settings reported_link_cap;
-+	struct link_settings verified_link_cap;
-+	struct link_settings max_link_setting;
-+	struct link_settings cur_link_settings;
-+	struct lane_settings ln_setting;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 6ae14d9..e721398 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -617,7 +617,7 @@ static void update_info_frame(struct core_stream *stream)
- static void enable_stream(struct core_stream *stream)
- {
- 	enum lane_count lane_count =
--			stream->sink->link->cur_link_settings.lane_count;
-+			stream->sink->link->public.cur_link_settings.lane_count;
- 
- 	struct dc_crtc_timing *timing = &stream->public.timing;
- 	struct core_link *link = stream->sink->link;
-@@ -869,7 +869,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 		core_link_enable_stream(stream->sink->link, stream);
- 
- 	if (dc_is_dp_signal(stream->signal))
--		unblank_stream(stream, &stream->sink->link->cur_link_settings);
-+		unblank_stream(stream,
-+			&stream->sink->link->public.cur_link_settings);
- 
- 	return DC_OK;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 17155e3..6a81518 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -232,13 +232,6 @@ struct core_link {
- 	struct graphics_object_id link_id;
- 	union ddi_channel_mapping ddi_channel_mapping;
- 	struct connector_device_tag_info device_tag;
--	/* caps is the same as reported_link_cap. link_traing use
--	 * reported_link_cap. Will clean up.  TODO */
--	struct link_settings reported_link_cap;
--	struct link_settings verified_link_cap;
--	struct link_settings max_link_setting;
--	struct link_settings cur_link_settings;
--	struct lane_settings ln_setting;
- 	struct dpcd_caps dpcd_caps;
- 	unsigned int dpcd_sink_count;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0773-drm-amd-dal-Create-transform-for-underlay-pipe.patch b/common/recipes-kernel/linux/files/0773-drm-amd-dal-Create-transform-for-underlay-pipe.patch
deleted file mode 100644
index 7e4c61d8..00000000
--- a/common/recipes-kernel/linux/files/0773-drm-amd-dal-Create-transform-for-underlay-pipe.patch
+++ /dev/null
@@ -1,1433 +0,0 @@
-From 0caa42dd0f4b24160cda117448794f3fef427b32 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 3 Feb 2016 15:02:13 -0500
-Subject: [PATCH 0773/1110] drm/amd/dal: Create transform for underlay pipe
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |   4 +-
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 115 ++++
- .../drm/amd/dal/dc/dce110/dce110_transform_sclv.c  | 531 ----------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 674 +++++++++++++++++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h |  44 ++
- 5 files changed, 835 insertions(+), 533 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-index ae9d2de..2d0007b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -5,8 +5,8 @@
- DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
- dce110_ipp_gamma.o dce110_link_encoder.o dce110_opp.o \
- dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
--dce110_timing_generator.o dce110_transform.o dce110_transform_gamut.o \
--dce110_transform_scl.o dce110_transform_sclv.o dce110_opp_csc.o\
-+dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
-+dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
- dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
- dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index fb5ef6d..70dedbc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -30,6 +30,7 @@
- #include "dce/dce_11_0_sh_mask.h"
- 
- #include "dce110_transform.h"
-+#include "dce110_transform_v.h"
- #include "opp.h"
- #include "include/logger_interface.h"
- #include "include/fixed32_32.h"
-@@ -849,3 +850,117 @@ bool dce110_transform_power_up_line_buffer(struct transform *xfm)
- 	return true;
- }
- 
-+/* Underlay pipe functions*/
-+
-+bool dce110_transform_v_get_current_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth *depth)
-+{
-+	uint32_t value = 0;
-+
-+	if (depth == NULL)
-+		return false;
-+
-+	value = dm_read_reg(
-+			xfm->ctx,
-+			mmLBV_DATA_FORMAT);
-+
-+	switch (get_reg_field_value(value, LBV_DATA_FORMAT, PIXEL_DEPTH)) {
-+	case 0:
-+		*depth = LB_PIXEL_DEPTH_30BPP;
-+		break;
-+	case 1:
-+		*depth = LB_PIXEL_DEPTH_24BPP;
-+		break;
-+	case 2:
-+		*depth = LB_PIXEL_DEPTH_18BPP;
-+		break;
-+	case 3:
-+		*depth = LB_PIXEL_DEPTH_36BPP;
-+		break;
-+	default:
-+		dal_logger_write(xfm->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid LB pixel depth",
-+			__func__);
-+		*depth = LB_PIXEL_DEPTH_30BPP;
-+		break;
-+	}
-+	return true;
-+
-+}
-+
-+bool dce110_transform_v_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool ret = true;
-+	uint32_t value;
-+	enum dc_color_depth color_depth;
-+
-+	value = dm_read_reg(
-+			xfm->ctx,
-+			LB_REG(mmLBV_DATA_FORMAT));
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		color_depth = COLOR_DEPTH_666;
-+		set_reg_field_value(value, 2, LBV_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_REDUCE_MODE);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, DITHER_EN);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, DOWNSCALE_PREFETCH_EN);
-+		break;
-+	case LB_PIXEL_DEPTH_24BPP:
-+		color_depth = COLOR_DEPTH_888;
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_REDUCE_MODE);
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, DITHER_EN);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, DOWNSCALE_PREFETCH_EN);
-+		break;
-+	case LB_PIXEL_DEPTH_30BPP:
-+		color_depth = COLOR_DEPTH_101010;
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, PIXEL_REDUCE_MODE);
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, DITHER_EN);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, DOWNSCALE_PREFETCH_EN);
-+		break;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		color_depth = COLOR_DEPTH_121212;
-+		set_reg_field_value(value, 3, LBV_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, PIXEL_REDUCE_MODE);
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, DITHER_EN);
-+		set_reg_field_value(value, 1, LBV_DATA_FORMAT, DOWNSCALE_PREFETCH_EN);
-+		break;
-+	default:
-+		ret = false;
-+		break;
-+	}
-+
-+	if (ret == true) {
-+		set_denormalization(xfm110, color_depth);
-+		ret = program_bit_depth_reduction(xfm110, color_depth,
-+				bit_depth_params);
-+
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
-+		dm_write_reg(
-+				xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
-+		if (!(xfm110->lb_pixel_depth_supported & depth)) {
-+			/*we should use unsupported capabilities
-+			 *  unless it is required by w/a*/
-+			dal_logger_write(xfm->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: Capability not supported",
-+				__func__);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-deleted file mode 100644
-index 1968296..0000000
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
-+++ /dev/null
-@@ -1,531 +0,0 @@
--/* Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dm_services.h"
--
--#include "dce/dce_11_0_d.h"
--#include "dce/dce_11_0_sh_mask.h"
--
--#include "dce110_transform.h"
--
--#define NOT_IMPLEMENTED()  DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_CONTROLLER,\
--			"TRANSFORM SCALER:%s()\n", __func__)
--
--/*
--*****************************************************************************
--*  Function: calculateViewport
--*
--*  @brief
--*     Calculates all of the data required to set the viewport
--*
--*  @param [in]  pData:      scaler settings data
--*  @param [out] pLumaVp:    luma viewport information
--*  @param [out] pChromaVp:  chroma viewport information
--*  @param [out] srcResCx2:  source chroma resolution times 2  - for multi-taps
--*
--*****************************************************************************
--*/
--static void calculate_viewport(
--		const struct scaler_data *scl_data,
--		struct rect *luma_viewport,
--		struct rect *chroma_viewport)
--{
--	/*Do not set chroma vp for rgb444 pixel format*/
--	luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2;
--	luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2;
--	luma_viewport->width =
--		scl_data->viewport.width - scl_data->viewport.width % 2;
--	luma_viewport->height =
--		scl_data->viewport.height - scl_data->viewport.height % 2;
--
--
--	if (scl_data->dal_pixel_format == PIXEL_FORMAT_422BPP16) {
--		luma_viewport->width += luma_viewport->width % 2;
--
--		chroma_viewport->x = luma_viewport->x / 2;
--		chroma_viewport->width = luma_viewport->width / 2;
--	} else if (scl_data->dal_pixel_format == PIXEL_FORMAT_420BPP12) {
--		luma_viewport->height += luma_viewport->height % 2;
--		luma_viewport->width += luma_viewport->width % 2;
--		/*for 420 video chroma is 1/4 the area of luma, scaled
--		 *vertically and horizontally
--		 */
--		chroma_viewport->x = luma_viewport->x / 2;
--		chroma_viewport->y = luma_viewport->y / 2;
--		chroma_viewport->height = luma_viewport->height / 2;
--		chroma_viewport->width = luma_viewport->width / 2;
--	}
--}
--
--
--static void program_viewport(
--	struct dce110_transform *xfm110,
--	struct rect *luma_view_port,
--	struct rect *chroma_view_port)
--{
--	struct dc_context *ctx = xfm110->base.ctx;
--	uint32_t value = 0;
--	uint32_t addr = 0;
--
--	if (luma_view_port->width != 0 && luma_view_port->height != 0) {
--		addr = mmSCLV_VIEWPORT_START;
--		value = 0;
--		set_reg_field_value(
--			value,
--			luma_view_port->x,
--			SCLV_VIEWPORT_START,
--			VIEWPORT_X_START);
--		set_reg_field_value(
--			value,
--			luma_view_port->y,
--			SCLV_VIEWPORT_START,
--			VIEWPORT_Y_START);
--		dm_write_reg(ctx, addr, value);
--
--		addr = mmSCLV_VIEWPORT_SIZE;
--		value = 0;
--		set_reg_field_value(
--			value,
--			luma_view_port->height,
--			SCLV_VIEWPORT_SIZE,
--			VIEWPORT_HEIGHT);
--		set_reg_field_value(
--			value,
--			luma_view_port->width,
--			SCLV_VIEWPORT_SIZE,
--			VIEWPORT_WIDTH);
--		dm_write_reg(ctx, addr, value);
--	}
--
--	if (chroma_view_port->width != 0 && chroma_view_port->height != 0) {
--		addr = mmSCLV_VIEWPORT_START_C;
--		value = 0;
--		set_reg_field_value(
--			value,
--			chroma_view_port->x,
--			SCLV_VIEWPORT_START_C,
--			VIEWPORT_X_START_C);
--		set_reg_field_value(
--			value,
--			chroma_view_port->y,
--			SCLV_VIEWPORT_START_C,
--			VIEWPORT_Y_START_C);
--		dm_write_reg(ctx, addr, value);
--
--		addr = mmSCLV_VIEWPORT_SIZE_C;
--		value = 0;
--		set_reg_field_value(
--			value,
--			chroma_view_port->height,
--			SCLV_VIEWPORT_SIZE_C,
--			VIEWPORT_HEIGHT_C);
--		set_reg_field_value(
--			value,
--			chroma_view_port->width,
--			SCLV_VIEWPORT_SIZE_C,
--			VIEWPORT_WIDTH_C);
--		dm_write_reg(ctx, addr, value);
--	}
--	/* TODO: add stereo support */
--}
--
--
--/* Until and For MPO video play story, to reduce time for implementation,
-- * below limits are applied for now: 2_TAPS only
-- * Use auto-calculated filter values
-- * Following routines will be empty for now:
-- *
-- * programSclRatiosInits -- calcualate scaler ratio manually
-- * calculateInits --- calcualate scaler ratio manually
-- * programFilter -- multi-taps
-- * GetOptimalNumberOfTaps -- will hard coded to 2 TAPS
-- * GetNextLowerNumberOfTaps -- will hard coded to 2TAPS
-- * validateRequestedScaleRatio - used by GetOptimalNumberOfTaps internally
-- */
--
--/**
--* Function:
--* void setup_scaling_configuration
--*
--* Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
--* Input:   data
--*
--* Output:
--   void
--*/
--static bool setup_scaling_configuration(
--	struct dce110_transform *xfm110,
--	const struct scaler_data *data)
--{
--	bool is_scaling_needed = false;
--	struct dc_context *ctx = xfm110->base.ctx;
--	uint32_t value = 0;
--
--	if (data->taps.h_taps + data->taps.v_taps > 2) {
--		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE);
--		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN);
--		is_scaling_needed = true;
--	} else {
--		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
--		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
--	}
--
--	if (data->taps.h_taps_c + data->taps.v_taps_c > 2) {
--		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C);
--		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C);
--		is_scaling_needed = true;
--	} else if (data->dal_pixel_format != PIXEL_FORMAT_420BPP12 &&
--		data->dal_pixel_format != PIXEL_FORMAT_422BPP16) {
--		set_reg_field_value(
--			value,
--			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
--			SCLV_MODE,
--			SCL_MODE_C);
--		set_reg_field_value(
--			value,
--			get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN),
--			SCLV_MODE,
--			SCL_PSCL_EN_C);
--	} else {
--		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
--		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
--	}
--	dm_write_reg(ctx, mmSCLV_MODE, value);
--
--	{
--		value = dm_read_reg(ctx, mmSCLV_TAP_CONTROL);
--
--		set_reg_field_value(value, data->taps.h_taps - 1,
--				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
--
--		set_reg_field_value(value, data->taps.v_taps - 1,
--				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
--
--		set_reg_field_value(value, data->taps.h_taps_c - 1,
--				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C);
--
--		set_reg_field_value(value, data->taps.v_taps_c - 1,
--				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
--
--		dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
--	}
--
--	{
--		/* we can ignore this register because we are ok with hw
--		 * default 0 -- change to 1 according to dal2 code*/
--		value = dm_read_reg(ctx, mmSCLV_CONTROL);
--		 /* 0 - Replaced out of bound pixels with black pixel
--		  * (or any other required color) */
--		set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
--
--		/* 1 - Replaced out of bound pixels with the edge pixel. */
--		dm_write_reg(ctx, mmSCLV_CONTROL, value);
--	}
--
--	return is_scaling_needed;
--}
--
--/**
--* Function:
--* void program_overscan
--*
--* Purpose: Programs overscan border
--* Input:   overscan
--*
--* Output:
--   void
--*/
--static void program_overscan(
--		struct dce110_transform *xfm110,
--		const struct overscan_info *overscan)
--{
--	uint32_t overscan_left_right = 0;
--	uint32_t overscan_top_bottom = 0;
--
--	set_reg_field_value(overscan_left_right, overscan->left,
--		SCLV_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
--
--	set_reg_field_value(overscan_left_right, overscan->right,
--		SCLV_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
--
--	set_reg_field_value(overscan_top_bottom, overscan->top,
--		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
--
--	set_reg_field_value(overscan_top_bottom, overscan->bottom,
--		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
--
--	dm_write_reg(xfm110->base.ctx,
--			mmSCLV_EXT_OVERSCAN_LEFT_RIGHT,
--			overscan_left_right);
--
--	dm_write_reg(xfm110->base.ctx,
--			mmSCLV_EXT_OVERSCAN_TOP_BOTTOM,
--			overscan_top_bottom);
--}
--/*
--static void setup_auto_scaling(struct dce110_transform *xfm110)
--{
--	uint32_t value = 0;
--	set_reg_field_value(value, 1, SCLV_AUTOMATIC_MODE_CONTROL,
--			SCL_V_CALC_AUTO_RATIO_EN);
--	set_reg_field_value(value, 1, SCLV_AUTOMATIC_MODE_CONTROL,
--			SCL_H_CALC_AUTO_RATIO_EN);
--	dal_write_reg(xfm->ctx,
--			xfm->regs[IDX_SCL_AUTOMATIC_MODE_CONTROL],
--			value);
--}
--*/
--
--static void program_two_taps_filter_horz(
--	struct dce110_transform *xfm110,
--	bool hardcode_coff)
--{
--	uint32_t value = 0;
--
--	if (hardcode_coff)
--		set_reg_field_value(
--				value,
--				1,
--				SCLV_HORZ_FILTER_CONTROL,
--				SCL_H_2TAP_HARDCODE_COEF_EN);
--
--	dm_write_reg(xfm110->base.ctx,
--			mmSCLV_HORZ_FILTER_CONTROL,
--			value);
--}
--
--static void program_two_taps_filter_vert(
--	struct dce110_transform *xfm110,
--	bool hardcode_coff)
--{
--	uint32_t value = 0;
--
--	if (hardcode_coff)
--		set_reg_field_value(value, 1, SCLV_VERT_FILTER_CONTROL,
--				SCL_V_2TAP_HARDCODE_COEF_EN);
--
--	dm_write_reg(xfm110->base.ctx,
--			mmSCLV_VERT_FILTER_CONTROL,
--			value);
--}
--
--static void set_coeff_update_complete(
--		struct dce110_transform *xfm110)
--{
--	/*TODO: Until now, only scaler bypass, up-scaler 2 -TAPS coeff auto
--	 * calculation are implemented. Coefficient RAM is not used
--	 * Do not check this flag yet
--	 */
--
--	/*uint32_t value;
--	uint32_t addr = xfm->regs[IDX_SCL_UPDATE];
--
--	value = dal_read_reg(xfm->ctx, addr);
--	set_reg_field_value(value, 0,
--			SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
--	dal_write_reg(xfm->ctx, addr, value);*/
--}
--
--static bool program_multi_taps_filter(
--	struct dce110_transform *xfm110,
--	const struct scaler_data *data,
--	bool horizontal)
--{
--	struct dc_context *ctx = xfm110->base.ctx;
--
--	NOT_IMPLEMENTED();
--	return false;
--}
--
--static void calculate_inits(
--	struct dce110_transform *xfm110,
--	const struct scaler_data *data,
--	struct sclv_ratios_inits *inits,
--	struct rect *luma_viewport,
--	struct rect *chroma_viewport)
--{
--	if (data->dal_pixel_format == PIXEL_FORMAT_420BPP12 ||
--		data->dal_pixel_format == PIXEL_FORMAT_422BPP16)
--		inits->chroma_enable = true;
--
--	/* TODO: implement rest of this function properly */
--	if (inits->chroma_enable) {
--		inits->h_int_scale_ratio_luma = 0x1000000;
--		inits->v_int_scale_ratio_luma = 0x1000000;
--		inits->h_int_scale_ratio_chroma = 0x800000;
--		inits->v_int_scale_ratio_chroma = 0x800000;
--	}
--}
--
--static void program_scl_ratios_inits(
--	struct dce110_transform *xfm110,
--	struct sclv_ratios_inits *inits)
--{
--	struct dc_context *ctx = xfm110->base.ctx;
--	uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;
--	uint32_t value = dm_read_reg(ctx, addr);
--
--	set_reg_field_value(
--		value,
--		inits->h_int_scale_ratio_luma,
--		SCLV_HORZ_FILTER_SCALE_RATIO,
--		SCL_H_SCALE_RATIO);
--	dm_write_reg(ctx, addr, value);
--
--	addr = mmSCLV_VERT_FILTER_SCALE_RATIO;
--	value = dm_read_reg(ctx, addr);
--	set_reg_field_value(
--		value,
--		inits->v_int_scale_ratio_luma,
--		SCLV_VERT_FILTER_SCALE_RATIO,
--		SCL_V_SCALE_RATIO);
--	dm_write_reg(ctx, addr, value);
--
--	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
--	value = dm_read_reg(ctx, addr);
--	set_reg_field_value(
--		value,
--		inits->h_int_scale_ratio_chroma,
--		SCLV_HORZ_FILTER_SCALE_RATIO_C,
--		SCL_H_SCALE_RATIO_C);
--	dm_write_reg(ctx, addr, value);
--
--	addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C;
--	value = dm_read_reg(ctx, addr);
--	set_reg_field_value(
--		value,
--		inits->v_int_scale_ratio_chroma,
--		SCLV_VERT_FILTER_SCALE_RATIO_C,
--		SCL_V_SCALE_RATIO_C);
--	dm_write_reg(ctx, addr, value);
--}
--
--void dce110_transform_underlay_set_scalerv_bypass(struct transform *xfm)
--{
--	uint32_t addr = mmSCLV_MODE;
--	uint32_t value = dm_read_reg(xfm->ctx, addr);
--
--	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
--	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
--	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
--	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
--	dm_write_reg(xfm->ctx, addr, value);
--}
--
--bool dce110_transform_underlay_is_scaling_enabled(struct transform *xfm)
--{
--	uint32_t value = dm_read_reg(xfm->ctx, mmSCLV_MODE);
--	uint8_t scl_mode = get_reg_field_value(value, SCLV_MODE, SCL_MODE);
--
--	return scl_mode == 0;
--}
--
--/* TODO: sync this one with DAL2 */
--bool dce110_transform_underlay_set_scaler(
--	struct transform *xfm,
--	const struct scaler_data *data)
--{
--	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
--	bool is_scaling_required;
--	struct rect luma_viewport = {0};
--	struct rect chroma_viewport = {0};
--	struct dc_context *ctx = xfm->ctx;
--
--	/* 1. Lock Scaler TODO: enable?*/
--	/*set_scaler_update_lock(xfm, true);*/
--
--	/* 2. Calculate viewport, viewport programming should happen after init
--	 * calculations as they may require an adjustment in the viewport.
--	 */
--
--	calculate_viewport(data, &luma_viewport, &chroma_viewport);
--
--	/* 3. Program overscan */
--	program_overscan(xfm110, &data->overscan);
--
--	/* 4. Program taps and configuration */
--	is_scaling_required = setup_scaling_configuration(xfm110, data);
--
--	if (is_scaling_required) {
--		/* 5. Calculate and program ratio, filter initialization */
--
--		struct sclv_ratios_inits inits = { 0 };
--
--		calculate_inits(
--			xfm110,
--			data,
--			&inits,
--			&luma_viewport,
--			&chroma_viewport);
--
--		program_scl_ratios_inits(xfm110, &inits);
--
--		/*scaler coeff of 2-TAPS use hardware auto calculated value*/
--
--		/* 6. Program vertical filters */
--		if (data->taps.v_taps > 2) {
--			program_two_taps_filter_vert(xfm110, false);
--
--			if (!program_multi_taps_filter(xfm110, data, false)) {
--				dal_logger_write(ctx->logger,
--					LOG_MAJOR_DCP,
--					LOG_MINOR_DCP_SCALER,
--					"Failed vertical taps programming\n");
--				return false;
--			}
--		} else
--			program_two_taps_filter_vert(xfm110, true);
--
--		/* 7. Program horizontal filters */
--		if (data->taps.h_taps > 2) {
--			program_two_taps_filter_horz(xfm110, false);
--
--			if (!program_multi_taps_filter(xfm110, data, true)) {
--				dal_logger_write(ctx->logger,
--					LOG_MAJOR_DCP,
--					LOG_MINOR_DCP_SCALER,
--					"Failed horizontal taps programming\n");
--				return false;
--			}
--		} else
--			program_two_taps_filter_horz(xfm110, true);
--	}
--
--	/* 8. Program the viewport */
--	if (data->flags.bits.SHOULD_PROGRAM_VIEWPORT)
--		program_viewport(xfm110, &luma_viewport, &chroma_viewport);
--
--	/* 9. Unlock the Scaler TODO: enable?*/
--	/* Every call to "set_scaler_update_lock(xfm, TRUE)"
--	 * must have a corresponding call to
--	 * "set_scaler_update_lock(xfm, FALSE)" */
--	/*set_scaler_update_lock(xfm, false);*/
--
--	/* TODO: investigate purpose/need of SHOULD_UNLOCK */
--	if (data->flags.bits.SHOULD_UNLOCK == false)
--		set_coeff_update_complete(xfm110);
--
--	return true;
--}
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-new file mode 100644
-index 0000000..a7c62e0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -0,0 +1,674 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#include "dc_types.h"
-+#include "core_types.h"
-+
-+#include "dce110_transform.h"
-+#include "dce110_transform_v.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define NOT_IMPLEMENTED()  DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_CONTROLLER,\
-+			"TRANSFORM SCALER:%s()\n", __func__)
-+#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-+/*
-+*****************************************************************************
-+*  Function: calculateViewport
-+*
-+*  @brief
-+*     Calculates all of the data required to set the viewport
-+*
-+*  @param [in]  pData:      scaler settings data
-+*  @param [out] pLumaVp:    luma viewport information
-+*  @param [out] pChromaVp:  chroma viewport information
-+*  @param [out] srcResCx2:  source chroma resolution times 2  - for multi-taps
-+*
-+*****************************************************************************
-+*/
-+static void calculate_viewport(
-+		const struct scaler_data *scl_data,
-+		struct rect *luma_viewport,
-+		struct rect *chroma_viewport)
-+{
-+	/*Do not set chroma vp for rgb444 pixel format*/
-+	luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2;
-+	luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2;
-+	luma_viewport->width =
-+		scl_data->viewport.width - scl_data->viewport.width % 2;
-+	luma_viewport->height =
-+		scl_data->viewport.height - scl_data->viewport.height % 2;
-+
-+
-+	if (scl_data->dal_pixel_format == PIXEL_FORMAT_422BPP16) {
-+		luma_viewport->width += luma_viewport->width % 2;
-+
-+		chroma_viewport->x = luma_viewport->x / 2;
-+		chroma_viewport->width = luma_viewport->width / 2;
-+	} else if (scl_data->dal_pixel_format == PIXEL_FORMAT_420BPP12) {
-+		luma_viewport->height += luma_viewport->height % 2;
-+		luma_viewport->width += luma_viewport->width % 2;
-+		/*for 420 video chroma is 1/4 the area of luma, scaled
-+		 *vertically and horizontally
-+		 */
-+		chroma_viewport->x = luma_viewport->x / 2;
-+		chroma_viewport->y = luma_viewport->y / 2;
-+		chroma_viewport->height = luma_viewport->height / 2;
-+		chroma_viewport->width = luma_viewport->width / 2;
-+	}
-+}
-+
-+
-+static void program_viewport(
-+	struct dce110_transform *xfm110,
-+	struct rect *luma_view_port,
-+	struct rect *chroma_view_port)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+
-+	if (luma_view_port->width != 0 && luma_view_port->height != 0) {
-+		addr = mmSCLV_VIEWPORT_START;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->x,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_X_START);
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->y,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_Y_START);
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = mmSCLV_VIEWPORT_SIZE;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->height,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_HEIGHT);
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->width,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_WIDTH);
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	if (chroma_view_port->width != 0 && chroma_view_port->height != 0) {
-+		addr = mmSCLV_VIEWPORT_START_C;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->x,
-+			SCLV_VIEWPORT_START_C,
-+			VIEWPORT_X_START_C);
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->y,
-+			SCLV_VIEWPORT_START_C,
-+			VIEWPORT_Y_START_C);
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = mmSCLV_VIEWPORT_SIZE_C;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->height,
-+			SCLV_VIEWPORT_SIZE_C,
-+			VIEWPORT_HEIGHT_C);
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->width,
-+			SCLV_VIEWPORT_SIZE_C,
-+			VIEWPORT_WIDTH_C);
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	/* TODO: add stereo support */
-+}
-+
-+
-+/*
-+ * Until and For MPO video play story, to reduce time for implementation,
-+ * below limits are applied for now: 2_TAPS only
-+ * Use auto-calculated filter values
-+ * Following routines will be empty for now:
-+ *
-+ * programSclRatiosInits -- calcualate scaler ratio manually
-+ * calculateInits --- calcualate scaler ratio manually
-+ * programFilter -- multi-taps
-+ * GetOptimalNumberOfTaps -- will hard coded to 2 TAPS
-+ * GetNextLowerNumberOfTaps -- will hard coded to 2TAPS
-+ * validateRequestedScaleRatio - used by GetOptimalNumberOfTaps internally
-+ */
-+
-+/*
-+ * Function:
-+ * void setup_scaling_configuration
-+ *
-+ * Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
-+ * Input:   data
-+ *
-+ * Output:
-+ *  void
-+ */
-+static bool setup_scaling_configuration(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data)
-+{
-+	bool is_scaling_needed = false;
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+
-+	if (data->taps.h_taps + data->taps.v_taps > 2) {
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE);
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN);
-+		is_scaling_needed = true;
-+	} else {
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
-+	}
-+
-+	if (data->taps.h_taps_c + data->taps.v_taps_c > 2) {
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C);
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C);
-+		is_scaling_needed = true;
-+	} else if (data->dal_pixel_format != PIXEL_FORMAT_420BPP12 &&
-+		data->dal_pixel_format != PIXEL_FORMAT_422BPP16) {
-+		set_reg_field_value(
-+			value,
-+			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
-+			SCLV_MODE,
-+			SCL_MODE_C);
-+		set_reg_field_value(
-+			value,
-+			get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN),
-+			SCLV_MODE,
-+			SCL_PSCL_EN_C);
-+	} else {
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
-+	}
-+	dm_write_reg(ctx, mmSCLV_MODE, value);
-+
-+	{
-+		value = dm_read_reg(ctx, mmSCLV_TAP_CONTROL);
-+
-+		set_reg_field_value(value, data->taps.h_taps - 1,
-+				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+
-+		set_reg_field_value(value, data->taps.v_taps - 1,
-+				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+
-+		set_reg_field_value(value, data->taps.h_taps_c - 1,
-+				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C);
-+
-+		set_reg_field_value(value, data->taps.v_taps_c - 1,
-+				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
-+
-+		dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
-+	}
-+
-+	{
-+		/*
-+		 * we can ignore this register because we are ok with hw
-+		 * default 0 -- change to 1 according to dal2 code
-+		 */
-+		value = dm_read_reg(ctx, mmSCLV_CONTROL);
-+		 /*
-+		  * 0 - Replaced out of bound pixels with black pixel
-+		  * (or any other required color)
-+		  */
-+		set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
-+
-+		/* 1 - Replaced out of bound pixels with the edge pixel. */
-+		dm_write_reg(ctx, mmSCLV_CONTROL, value);
-+	}
-+
-+	return is_scaling_needed;
-+}
-+
-+/**
-+* Function:
-+* void program_overscan
-+*
-+* Purpose: Programs overscan border
-+* Input:   overscan
-+*
-+* Output:
-+   void
-+*/
-+static void program_overscan(
-+		struct dce110_transform *xfm110,
-+		const struct overscan_info *overscan)
-+{
-+	uint32_t overscan_left_right = 0;
-+	uint32_t overscan_top_bottom = 0;
-+
-+	set_reg_field_value(overscan_left_right, overscan->left,
-+		SCLV_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-+
-+	set_reg_field_value(overscan_left_right, overscan->right,
-+		SCLV_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->top,
-+		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->bottom,
-+		SCLV_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-+
-+	dm_write_reg(xfm110->base.ctx,
-+			mmSCLV_EXT_OVERSCAN_LEFT_RIGHT,
-+			overscan_left_right);
-+
-+	dm_write_reg(xfm110->base.ctx,
-+			mmSCLV_EXT_OVERSCAN_TOP_BOTTOM,
-+			overscan_top_bottom);
-+}
-+
-+static void program_two_taps_filter_horz(
-+	struct dce110_transform *xfm110,
-+	bool hardcode_coff)
-+{
-+	uint32_t value = 0;
-+
-+	if (hardcode_coff)
-+		set_reg_field_value(
-+				value,
-+				1,
-+				SCLV_HORZ_FILTER_CONTROL,
-+				SCL_H_2TAP_HARDCODE_COEF_EN);
-+
-+	dm_write_reg(xfm110->base.ctx,
-+			mmSCLV_HORZ_FILTER_CONTROL,
-+			value);
-+}
-+
-+static void program_two_taps_filter_vert(
-+	struct dce110_transform *xfm110,
-+	bool hardcode_coff)
-+{
-+	uint32_t value = 0;
-+
-+	if (hardcode_coff)
-+		set_reg_field_value(value, 1, SCLV_VERT_FILTER_CONTROL,
-+				SCL_V_2TAP_HARDCODE_COEF_EN);
-+
-+	dm_write_reg(xfm110->base.ctx,
-+			mmSCLV_VERT_FILTER_CONTROL,
-+			value);
-+}
-+
-+static void set_coeff_update_complete(
-+		struct dce110_transform *xfm110)
-+{
-+	/*TODO: Until now, only scaler bypass, up-scaler 2 -TAPS coeff auto
-+	 * calculation are implemented. Coefficient RAM is not used
-+	 * Do not check this flag yet
-+	 */
-+
-+	/*uint32_t value;
-+	uint32_t addr = xfm->regs[IDX_SCL_UPDATE];
-+
-+	value = dal_read_reg(xfm->ctx, addr);
-+	set_reg_field_value(value, 0,
-+			SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
-+	dal_write_reg(xfm->ctx, addr, value);*/
-+}
-+
-+static bool program_multi_taps_filter(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data,
-+	bool horizontal)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+
-+	NOT_IMPLEMENTED();
-+	return false;
-+}
-+
-+static void calculate_inits(
-+	struct dce110_transform *xfm110,
-+	const struct scaler_data *data,
-+	struct sclv_ratios_inits *inits,
-+	struct rect *luma_viewport,
-+	struct rect *chroma_viewport)
-+{
-+	if (data->dal_pixel_format == PIXEL_FORMAT_420BPP12 ||
-+		data->dal_pixel_format == PIXEL_FORMAT_422BPP16)
-+		inits->chroma_enable = true;
-+
-+	/* TODO: implement rest of this function properly */
-+	if (inits->chroma_enable) {
-+		inits->h_int_scale_ratio_luma = 0x1000000;
-+		inits->v_int_scale_ratio_luma = 0x1000000;
-+		inits->h_int_scale_ratio_chroma = 0x800000;
-+		inits->v_int_scale_ratio_chroma = 0x800000;
-+	}
-+}
-+
-+static void program_scl_ratios_inits(
-+	struct dce110_transform *xfm110,
-+	struct sclv_ratios_inits *inits)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio_luma,
-+		SCLV_HORZ_FILTER_SCALE_RATIO,
-+		SCL_H_SCALE_RATIO);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_SCALE_RATIO;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio_luma,
-+		SCLV_VERT_FILTER_SCALE_RATIO,
-+		SCL_V_SCALE_RATIO);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio_chroma,
-+		SCLV_HORZ_FILTER_SCALE_RATIO_C,
-+		SCL_H_SCALE_RATIO_C);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio_chroma,
-+		SCLV_VERT_FILTER_SCALE_RATIO_C,
-+		SCL_V_SCALE_RATIO_C);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void dce110_transform_v_set_scalerv_bypass(struct transform *xfm)
-+{
-+	uint32_t addr = mmSCLV_MODE;
-+	uint32_t value = dm_read_reg(xfm->ctx, addr);
-+
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
-+	set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
-+	dm_write_reg(xfm->ctx, addr, value);
-+}
-+
-+/* TODO: sync this one with DAL2 */
-+static bool dce110_transform_v_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool is_scaling_required;
-+	struct rect luma_viewport = {0};
-+	struct rect chroma_viewport = {0};
-+	struct dc_context *ctx = xfm->ctx;
-+
-+	/* 1. Lock Scaler TODO: enable?*/
-+	/*set_scaler_update_lock(xfm, true);*/
-+
-+	/* 2. Calculate viewport, viewport programming should happen after init
-+	 * calculations as they may require an adjustment in the viewport.
-+	 */
-+
-+	calculate_viewport(data, &luma_viewport, &chroma_viewport);
-+
-+	/* 3. Program overscan */
-+	program_overscan(xfm110, &data->overscan);
-+
-+	/* 4. Program taps and configuration */
-+	is_scaling_required = setup_scaling_configuration(xfm110, data);
-+
-+	if (is_scaling_required) {
-+		/* 5. Calculate and program ratio, filter initialization */
-+
-+		struct sclv_ratios_inits inits = { 0 };
-+
-+		calculate_inits(
-+			xfm110,
-+			data,
-+			&inits,
-+			&luma_viewport,
-+			&chroma_viewport);
-+
-+		program_scl_ratios_inits(xfm110, &inits);
-+
-+		/*scaler coeff of 2-TAPS use hardware auto calculated value*/
-+
-+		/* 6. Program vertical filters */
-+		if (data->taps.v_taps > 2) {
-+			program_two_taps_filter_vert(xfm110, false);
-+
-+			if (!program_multi_taps_filter(xfm110, data, false)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed vertical taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter_vert(xfm110, true);
-+
-+		/* 7. Program horizontal filters */
-+		if (data->taps.h_taps > 2) {
-+			program_two_taps_filter_horz(xfm110, false);
-+
-+			if (!program_multi_taps_filter(xfm110, data, true)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed horizontal taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter_horz(xfm110, true);
-+	}
-+
-+	/* 8. Program the viewport */
-+	if (data->flags.bits.SHOULD_PROGRAM_VIEWPORT)
-+		program_viewport(xfm110, &luma_viewport, &chroma_viewport);
-+
-+	/* 9. Unlock the Scaler TODO: enable?
-+	 * Every call to "set_scaler_update_lock(xfm, TRUE)"
-+	 * must have a corresponding call to
-+	 * "set_scaler_update_lock(xfm, FALSE)" */
-+
-+	/*set_scaler_update_lock(xfm, false);*/
-+
-+	/* TODO: investigate purpose/need of SHOULD_UNLOCK */
-+	if (data->flags.bits.SHOULD_UNLOCK == false)
-+		set_coeff_update_complete(xfm110);
-+
-+	return true;
-+}
-+
-+static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	uint32_t value;
-+
-+	value = dm_read_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL);
-+
-+	/*Use all three pieces of memory always*/
-+	set_reg_field_value(value, 0, LBV_MEMORY_CTRL, LB_MEMORY_CONFIG);
-+	/*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
-+	set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LBV_MEMORY_CTRL,
-+			LB_MEMORY_SIZE);
-+
-+	dm_write_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL, value);
-+
-+	return true;
-+}
-+
-+static void get_viewport(
-+		struct dce110_transform *xfm110,
-+		struct rect *current_view_port)
-+{
-+	uint32_t value_start;
-+	uint32_t value_size;
-+
-+	if (current_view_port == NULL)
-+		return;
-+
-+	value_start = dm_read_reg(xfm110->base.ctx, mmSCLV_VIEWPORT_START);
-+	value_size = dm_read_reg(xfm110->base.ctx, mmSCLV_VIEWPORT_SIZE);
-+
-+	current_view_port->x = get_reg_field_value(
-+			value_start,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_X_START);
-+	current_view_port->y = get_reg_field_value(
-+			value_start,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_Y_START);
-+	current_view_port->height = get_reg_field_value(
-+			value_size,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_HEIGHT);
-+	current_view_port->width = get_reg_field_value(
-+			value_size,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_WIDTH);
-+}
-+
-+static void program_luma_viewport(
-+	struct dce110_transform *xfm110,
-+	const struct rect *view_port)
-+{
-+	struct dc_context *ctx = xfm110->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+
-+	addr = mmSCLV_VIEWPORT_START;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		view_port->x,
-+		SCLV_VIEWPORT_START,
-+		VIEWPORT_X_START);
-+	set_reg_field_value(
-+		value,
-+		view_port->y,
-+		SCLV_VIEWPORT_START,
-+		VIEWPORT_Y_START);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VIEWPORT_SIZE;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		view_port->height,
-+		SCLV_VIEWPORT_SIZE,
-+		VIEWPORT_HEIGHT);
-+	set_reg_field_value(
-+		value,
-+		view_port->width,
-+		SCLV_VIEWPORT_SIZE,
-+		VIEWPORT_WIDTH);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* TODO: add stereo support */
-+}
-+
-+static bool dce110_transform_v_update_viewport(
-+	struct transform *xfm,
-+	const struct rect *view_port,
-+	bool is_fbc_attached)
-+{
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	bool program_req = false;
-+	struct rect current_view_port;
-+
-+	if (view_port == NULL)
-+		return program_req;
-+
-+	get_viewport(xfm110, &current_view_port);
-+
-+	if (current_view_port.x != view_port->x ||
-+			current_view_port.y != view_port->y ||
-+			current_view_port.height != view_port->height ||
-+			current_view_port.width != view_port->width)
-+		program_req = true;
-+
-+	if (program_req) {
-+		/*underlay viewport is programmed with scaler
-+		 *program_viewport function pointer is not exposed*/
-+		program_luma_viewport(xfm110, view_port);
-+	}
-+
-+	return program_req;
-+}
-+
-+static struct transform_funcs dce110_transform_v_funcs = {
-+	.transform_power_up =
-+		dce110_transform_v_power_up_line_buffer,
-+	.transform_set_scaler =
-+		dce110_transform_v_set_scaler,
-+	.transform_set_scaler_bypass =
-+		dce110_transform_v_set_scalerv_bypass,
-+	.transform_update_viewport =
-+		dce110_transform_v_update_viewport,
-+	.transform_set_scaler_filter =
-+		dce110_transform_set_scaler_filter,
-+	.transform_set_gamut_remap =
-+		dce110_transform_set_gamut_remap,
-+	.transform_set_pixel_storage_depth =
-+		dce110_transform_v_set_pixel_storage_depth,
-+	.transform_get_current_pixel_storage_depth =
-+		dce110_transform_v_get_current_pixel_storage_depth
-+};
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce110_transform_v_construct(
-+	struct dce110_transform *xfm110,
-+	struct dc_context *ctx)
-+{
-+	xfm110->base.ctx = ctx;
-+
-+	xfm110->base.funcs = &dce110_transform_v_funcs;
-+
-+	xfm110->lb_pixel_depth_supported =
-+			LB_PIXEL_DEPTH_18BPP |
-+			LB_PIXEL_DEPTH_24BPP |
-+			LB_PIXEL_DEPTH_30BPP;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-new file mode 100644
-index 0000000..b51bd78
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-@@ -0,0 +1,44 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_V_DCE110_H__
-+#define __DAL_TRANSFORM_V_DCE110_H__
-+
-+#include "inc/transform.h"
-+#include "include/grph_csc_types.h"
-+
-+bool dce110_transform_v_construct(
-+	struct dce110_transform *xfm110,
-+	struct dc_context *ctx);
-+
-+bool dce110_transform_v_get_current_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth *depth);
-+
-+bool dce110_transform_v_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params);
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0774-drm-amd-dal-Fix-Bandwidth-Calculations-for-up-to-6-d.patch b/common/recipes-kernel/linux/files/0774-drm-amd-dal-Fix-Bandwidth-Calculations-for-up-to-6-d.patch
deleted file mode 100644
index 8d4160b5..00000000
--- a/common/recipes-kernel/linux/files/0774-drm-amd-dal-Fix-Bandwidth-Calculations-for-up-to-6-d.patch
+++ /dev/null
@@ -1,248 +0,0 @@
-From 86458ff9af0967a0a9290c5093e9d97149a895ea Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Fri, 5 Feb 2016 14:07:16 -0500
-Subject: [PATCH 0774/1110] drm/amd/dal: Fix Bandwidth Calculations for up-to 6
- displays.
-
-Also, fix stack overflow by using a realistic max number of displays,
-instead of the magic number of 3 (PPLib input was overwritten
-when 4th display was pluggedin).
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 15 ++++++---
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 38 +++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  6 ++--
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  1 -
- drivers/gpu/drm/amd/dal/dc/dm_services.h           |  2 +-
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h     |  2 --
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  2 ++
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  3 +-
- 9 files changed, 40 insertions(+), 31 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 8faabbc..2b69536 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3706,9 +3706,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 	struct bw_calcs_results *bw_results_internal = dm_alloc(
- 				ctx, sizeof(struct bw_calcs_results));
- 	struct bw_calcs_mode_data_internal *bw_data_internal =
--		dm_alloc(
--			ctx, sizeof(struct bw_calcs_mode_data_internal));
-+		dm_alloc(ctx, sizeof(struct bw_calcs_mode_data_internal));
-+
- 	switch (mode_data->number_of_displays) {
-+	case (6):
-+		/* fall through */
-+	case (5):
-+		/* fall through */
-+	case (4):
-+		/* fall through */
- 	case (3):
- 		bw_data_internal->d2_htotal =
- 			mode_data->displays_data[2].h_total;
-@@ -3722,6 +3728,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 			mode_data->displays_data[2].graphics_scale_ratio;
- 		bw_data_internal->d2_graphics_stereo_mode =
- 			mode_data->displays_data[2].graphics_stereo_mode;
-+		/* fall through */
- 	case (2):
- 		bw_data_internal->d1_display_write_back_dwb_enable = false;
- 		bw_data_internal->d1_underlay_mode = bw_def_none;
-@@ -3738,7 +3745,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 			mode_data->displays_data[1].graphics_scale_ratio;
- 		bw_data_internal->d1_graphics_stereo_mode =
- 			mode_data->displays_data[1].graphics_stereo_mode;
--
-+		/* fall through */
- 	case (1):
- 		bw_data_internal->d0_fbc_enable =
- 			mode_data->displays_data[0].fbc_enable;
-@@ -3759,7 +3766,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 			mode_data->displays_data[0].graphics_scale_ratio;
- 		bw_data_internal->d0_graphics_stereo_mode =
- 			mode_data->displays_data[0].graphics_stereo_mode;
--
-+		/* fall through */
- 	default:
- 		/* data for all displays */
- 		bw_data_internal->number_of_displays =
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 0b8f158..0af63f8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -607,7 +607,7 @@ bool dc_commit_targets(
- 
- 	program_timing_sync(dc->ctx, context);
- 
--	pplib_apply_display_requirements(dc, context);
-+	pplib_apply_display_requirements(dc, context, &context->pp_display_cfg);
- 
- 	/* TODO: disable unused plls*/
- fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 6375678..eea4eec 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -530,47 +530,47 @@ void pplib_apply_safe_state(
- 
- void pplib_apply_display_requirements(
- 	const struct dc *dc,
--	const struct validate_context *context)
-+	const struct validate_context *context,
-+	struct dc_pp_display_configuration *pp_display_cfg)
- {
--	struct dc_pp_display_configuration pp_display_cfg = { 0 };
- 
--	pp_display_cfg.all_displays_in_sync =
-+	pp_display_cfg->all_displays_in_sync =
- 		context->bw_results.all_displays_in_sync;
--	pp_display_cfg.nb_pstate_switch_disable =
-+	pp_display_cfg->nb_pstate_switch_disable =
- 			context->bw_results.nbp_state_change_enable == false;
--	pp_display_cfg.cpu_cc6_disable =
-+	pp_display_cfg->cpu_cc6_disable =
- 			context->bw_results.cpuc_state_change_enable == false;
--	pp_display_cfg.cpu_pstate_disable =
-+	pp_display_cfg->cpu_pstate_disable =
- 			context->bw_results.cpup_state_change_enable == false;
--	pp_display_cfg.cpu_pstate_separation_time =
-+	pp_display_cfg->cpu_pstate_separation_time =
- 			context->bw_results.required_blackout_duration_us;
- 
--	pp_display_cfg.min_memory_clock_khz = context->bw_results.required_yclk
-+	pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
- 		/ MEMORY_TYPE_MULTIPLIER;
--	pp_display_cfg.min_engine_clock_khz = context->bw_results.required_sclk;
--	pp_display_cfg.min_engine_clock_deep_sleep_khz
-+	pp_display_cfg->min_engine_clock_khz = context->bw_results.required_sclk;
-+	pp_display_cfg->min_engine_clock_deep_sleep_khz
- 			= context->bw_results.required_sclk_deep_sleep;
- 
--	pp_display_cfg.avail_mclk_switch_time_us =
-+	pp_display_cfg->avail_mclk_switch_time_us =
- 						get_min_vblank_time_us(context);
--	pp_display_cfg.avail_mclk_switch_time_in_disp_active_us = 0;
-+	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
- 
--	pp_display_cfg.disp_clk_khz = context->bw_results.dispclk_khz;
-+	pp_display_cfg->disp_clk_khz = context->bw_results.dispclk_khz;
- 
--	fill_display_configs(context, &pp_display_cfg);
-+	fill_display_configs(context, pp_display_cfg);
- 
- 	/* TODO: is this still applicable?*/
--	if (pp_display_cfg.display_count == 1) {
-+	if (pp_display_cfg->display_count == 1) {
- 		const struct dc_crtc_timing *timing =
- 			&context->targets[0]->public.streams[0]->timing;
- 
--		pp_display_cfg.crtc_index =
--			pp_display_cfg.disp_configs[0].pipe_idx;
--		pp_display_cfg.line_time_in_us = timing->h_total * 1000
-+		pp_display_cfg->crtc_index =
-+			pp_display_cfg->disp_configs[0].pipe_idx;
-+		pp_display_cfg->line_time_in_us = timing->h_total * 1000
- 							/ timing->pix_clk_khz;
- 	}
- 
--	dm_pp_apply_display_requirements(dc->ctx, &pp_display_cfg);
-+	dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
- }
- 
- /* Maximum TMDS single link pixel clock 165MHz */
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index e93e73d..7980e9f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -288,7 +288,8 @@ bool dc_commit_surfaces_to_target(
- 
- 	if (prev_disp_clk < dc->current_context.bw_results.dispclk_khz) {
- 		dc->hwss.program_bw(dc, &dc->current_context);
--		pplib_apply_display_requirements(dc, &dc->current_context);
-+		pplib_apply_display_requirements(dc, &dc->current_context,
-+				&dc->current_context.pp_display_cfg);
- 	}
- 
- 	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
-@@ -322,7 +323,8 @@ bool dc_commit_surfaces_to_target(
- 	/* Lower display clock if necessary */
- 	if (prev_disp_clk > dc->current_context.bw_results.dispclk_khz) {
- 		dc->hwss.program_bw(dc, &dc->current_context);
--		pplib_apply_display_requirements(dc, &dc->current_context);
-+		pplib_apply_display_requirements(dc, &dc->current_context,
-+				&dc->current_context.pp_display_cfg);
- 	}
- 
- 	return true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 21aad94..2abdda7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -749,7 +749,6 @@ struct dc_csc_adjustments {
- 	struct fixed31_32 hue;
- };
- 
--
- enum {
- 	MAX_LANES = 2,
- 	MAX_COFUNC_PATH = 6,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 206c0b7..33f700e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -303,7 +303,7 @@ struct dc_pp_display_configuration {
- 	bool all_displays_in_sync;
- 
- 	uint8_t display_count;
--	struct dc_pp_single_disp_config disp_configs[3];
-+	struct dc_pp_single_disp_config disp_configs[MAX_COFUNC_PATH];
- 
- 	/*Controller Index of primary display - used in MCLK SMC switching hang
- 	 * SW Workaround*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index bc458aa..7c8b31f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -26,8 +26,6 @@
- #ifndef __DM_SERVICES_TYPES_H__
- #define __DM_SERVICES_TYPES_H__
- 
--#define INVALID_DISPLAY_INDEX 0xffffffff
--
- #if defined __KERNEL__
- 
- #include <asm/byteorder.h>
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 6a81518..bd7bd2b 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -345,6 +345,8 @@ struct validate_context {
- 	struct bw_calcs_mode_data bw_mode_data;
- 	/* The output from BW and WM calculations. */
- 	struct bw_calcs_output bw_results;
-+	/* Note: this is a big structure, do *not* put on stack! */
-+	struct dc_pp_display_configuration pp_display_cfg;
- };
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index bda92e3..b4936b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -69,7 +69,8 @@ void pplib_apply_safe_state(const struct dc *dc);
- 
- void pplib_apply_display_requirements(
- 	const struct dc *dc,
--	const struct validate_context *context);
-+	const struct validate_context *context,
-+	struct dc_pp_display_configuration *pp_display_cfg);
- 
- void build_info_frame(struct core_stream *stream);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0775-drm-amd-dal-fix-build-breakage-due-to-rebase.patch b/common/recipes-kernel/linux/files/0775-drm-amd-dal-fix-build-breakage-due-to-rebase.patch
deleted file mode 100644
index 63ede856..00000000
--- a/common/recipes-kernel/linux/files/0775-drm-amd-dal-fix-build-breakage-due-to-rebase.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 707ebc42e302f482b32d269fd45967217511d47b Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 5 Feb 2016 16:37:01 -0500
-Subject: [PATCH 0775/1110] drm/amd/dal: fix build breakage due to rebase
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index a7c62e0..34fedc5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -22,7 +22,7 @@
-  * Authors: AMD
-  *
-  */
--
-+#include "dm_services.h"
- 
- #include "dc_types.h"
- #include "core_types.h"
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch b/common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch
deleted file mode 100644
index f1be2b5e..00000000
--- a/common/recipes-kernel/linux/files/0776-drm-amd-dal-Refactor-link_settings-to-public.patch
+++ /dev/null
@@ -1,760 +0,0 @@
-From 7630cf685d14c02a4e783d194c4f4c0918101b73 Mon Sep 17 00:00:00 2001
-From: Chris Park <Chris.Park@amd.com>
-Date: Fri, 5 Feb 2016 15:52:42 -0500
-Subject: [PATCH 0776/1110] drm/amd/dal: Refactor link_settings to public
-
-Definition is moved from link_service_types.h to dc_types.h.
-Given dc_ prefix for public struct.
-
-Signed-off-by: Chris Park <Chris.Park@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   6 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       |  61 ++++++-------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  10 +--
- drivers/gpu/drm/amd/dal/dc/dc_dp_types.h           | 100 +++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   1 +
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   4 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   6 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |   4 +-
- drivers/gpu/drm/amd/dal/dc/dm_services.h           |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h        |   8 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |   6 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h         |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h    |   2 +-
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.c  |   4 +-
- .../gpu/drm/amd/dal/include/bios_parser_types.h    |   8 +-
- .../gpu/drm/amd/dal/include/link_service_types.h   |  80 +----------------
- 17 files changed, 168 insertions(+), 138 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_dp_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index c1e3d33..9e04b45 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1141,7 +1141,7 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 	enum dc_status status;
- 	bool skip_video_pattern;
- 	struct core_link *link = stream->sink->link;
--	struct link_settings link_settings = {0};
-+	struct dc_link_settings link_settings = {0};
- 	enum dp_panel_mode panel_mode;
- 
- 	/* get link settings for video mode timing */
-@@ -1215,7 +1215,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
- 
- 	dm_memset(&stream->sink->link->public.cur_link_settings, 0,
--			sizeof(struct link_settings));
-+			sizeof(struct dc_link_settings));
- 
- 	link->link_enc->funcs->enable_tmds_output(
- 			link->link_enc,
-@@ -1341,7 +1341,7 @@ void core_link_resume(struct core_link *link)
- 
- static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
- {
--	struct link_settings *link_settings =
-+	struct dc_link_settings *link_settings =
- 			&stream->sink->link->public.cur_link_settings;
- 	uint32_t link_rate_in_mbps =
- 			link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 54d1f9f..f69743a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -11,7 +11,7 @@
- #include "dpcd_defs.h"
- 
- /* maximum pre emphasis level allowed for each voltage swing level*/
--static const enum pre_emphasis voltage_swing_to_pre_emphasis[] = {
-+static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
- 		PRE_EMPHASIS_LEVEL3,
- 		PRE_EMPHASIS_LEVEL2,
- 		PRE_EMPHASIS_LEVEL1,
-@@ -30,7 +30,7 @@ enum {
- 	LINK_TRAINING_MAX_CR_RETRY = 100
- };
- 
--static const struct link_settings link_training_fallback_table[] = {
-+static const struct dc_link_settings link_training_fallback_table[] = {
- /* 2160 Mbytes/sec*/
- { LANE_COUNT_FOUR, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
- /* 1080 Mbytes/sec*/
-@@ -277,10 +277,10 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 				dpcd_lt_buffer,
- 				size_in_bytes + sizeof(dpcd_pattern.raw) );
- 
--	link->public.ln_setting = lt_settings->lane_settings[0];
-+	link->public.cur_lane_setting = lt_settings->lane_settings[0];
- }
- 
--static bool is_cr_done(enum lane_count ln_count,
-+static bool is_cr_done(enum dc_lane_count ln_count,
- 	union lane_status *dpcd_lane_status)
- {
- 	bool done = true;
-@@ -294,7 +294,7 @@ static bool is_cr_done(enum lane_count ln_count,
- 
- }
- 
--static bool is_ch_eq_done(enum lane_count ln_count,
-+static bool is_ch_eq_done(enum dc_lane_count ln_count,
- 	union lane_status *dpcd_lane_status,
- 	union lane_align_status_updated *lane_status_updated)
- {
-@@ -342,10 +342,10 @@ static uint8_t get_nibble_at_index(const uint8_t *buf,
- 	return nibble;
- }
- 
--static enum pre_emphasis get_max_pre_emphasis_for_voltage_swing(
--	enum voltage_swing voltage)
-+static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
-+	enum dc_voltage_swing voltage)
- {
--	enum pre_emphasis pre_emphasis;
-+	enum dc_pre_emphasis pre_emphasis;
- 	pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
- 
- 	if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
-@@ -360,7 +360,7 @@ static void find_max_drive_settings(
- 	struct link_training_settings *max_lt_setting)
- {
- 	uint32_t lane;
--	struct lane_settings max_requested;
-+	struct dc_lane_settings max_requested;
- 
- 	max_requested.VOLTAGE_SWING =
- 		link_training_setting->
-@@ -514,10 +514,10 @@ static void get_lane_status_and_drive_settings(
- 		lane++) {
- 
- 		request_settings.lane_settings[lane].VOLTAGE_SWING =
--			(enum voltage_swing)(dpcd_lane_adjust[lane].bits.
-+			(enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
- 				VOLTAGE_SWING_LANE);
- 		request_settings.lane_settings[lane].PRE_EMPHASIS =
--			(enum pre_emphasis)(dpcd_lane_adjust[lane].bits.
-+			(enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
- 				PRE_EMPHASIS_LANE);
- 	}
- 
-@@ -599,7 +599,7 @@ static void dpcd_set_lane_settings(
- 		dpcd_lane[0].bits.MAX_SWING_REACHED,
- 		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
- 
--	link->public.ln_setting = link_training_setting->lane_settings[0];
-+	link->public.cur_lane_setting = link_training_setting->lane_settings[0];
- 
- }
- 
-@@ -633,7 +633,7 @@ static bool perform_post_lt_adj_req_sequence(
- 	struct core_link *link,
- 	struct link_training_settings *lt_settings)
- {
--	enum lane_count lane_count =
-+	enum dc_lane_count lane_count =
- 	lt_settings->link_settings.lane_count;
- 
- 	uint32_t adj_req_count;
-@@ -753,7 +753,7 @@ static bool perform_channel_equalization_sequence(
- 	struct link_training_settings req_settings;
- 	enum hw_dp_training_pattern hw_tr_pattern;
- 	uint32_t retries_ch_eq;
--	enum lane_count lane_count = lt_settings->link_settings.lane_count;
-+	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
- 	union lane_align_status_updated dpcd_lane_status_updated = {{0}};
- 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
- 
-@@ -816,7 +816,7 @@ static bool perform_clock_recovery_sequence(
- 	uint32_t retry_count;
- 	uint32_t lane;
- 	struct link_training_settings req_settings;
--	enum lane_count lane_count =
-+	enum dc_lane_count lane_count =
- 	lt_settings->link_settings.lane_count;
- 	enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
- 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
-@@ -924,7 +924,7 @@ static bool perform_clock_recovery_sequence(
- 
-  bool perform_link_training(
- 	struct core_link *link,
--	const struct link_settings *link_setting,
-+	const struct dc_link_settings *link_setting,
- 	bool skip_video_pattern)
- {
- 	bool status;
-@@ -1027,8 +1027,8 @@ static bool perform_clock_recovery_sequence(
- 
- /*TODO add more check to see if link support request link configuration */
- static bool is_link_setting_supported(
--	const struct link_settings *link_setting,
--	const struct link_settings *max_link_setting)
-+	const struct dc_link_settings *link_setting,
-+	const struct dc_link_settings *max_link_setting)
- {
- 	if (link_setting->lane_count > max_link_setting->lane_count ||
- 		link_setting->link_rate > max_link_setting->link_rate)
-@@ -1042,23 +1042,24 @@ static const uint32_t get_link_training_fallback_table_len(
- 	return ARRAY_SIZE(link_training_fallback_table);
- }
- 
--static const struct link_settings *get_link_training_fallback_table(
-+static const struct dc_link_settings *get_link_training_fallback_table(
- 	struct core_link *link, uint32_t i)
- {
- 	return &link_training_fallback_table[i];
- }
- 
--static bool exceeded_limit_link_setting(const struct link_settings *link_setting,
--			const struct link_settings *limit_link_setting)
-+static bool exceeded_limit_link_setting(
-+	const struct dc_link_settings *link_setting,
-+	const struct dc_link_settings *limit_link_setting)
- {
- 	return (link_setting->lane_count * link_setting->link_rate
- 		 > limit_link_setting->lane_count * limit_link_setting->link_rate ?
- 				 true : false);
- }
- 
--static enum link_rate get_max_link_rate(struct core_link *link)
-+static enum dc_link_rate get_max_link_rate(struct core_link *link)
- {
--	enum link_rate max_link_rate = LINK_RATE_HIGH;
-+	enum dc_link_rate max_link_rate = LINK_RATE_HIGH;
- 
- 	if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
- 		max_link_rate = LINK_RATE_HIGH2;
-@@ -1071,12 +1072,12 @@ static enum link_rate get_max_link_rate(struct core_link *link)
- 
- bool dp_hbr_verify_link_cap(
- 	struct core_link *link,
--	struct link_settings *known_limit_link_setting)
-+	struct dc_link_settings *known_limit_link_setting)
- {
--	struct link_settings max_link_cap = {0};
-+	struct dc_link_settings max_link_cap = {0};
- 	bool success;
- 	bool skip_link_training;
--	const struct link_settings *cur;
-+	const struct dc_link_settings *cur;
- 	bool skip_video_pattern;
- 	uint32_t i;
- 
-@@ -1212,7 +1213,7 @@ static uint32_t bandwidth_in_kbps_from_timing(
- }
- 
- static uint32_t bandwidth_in_kbps_from_link_settings(
--	const struct link_settings *link_setting)
-+	const struct dc_link_settings *link_setting)
- {
- 	uint32_t link_rate_in_kbps = link_setting->link_rate *
- 		LINK_RATE_REF_FREQ_IN_KHZ;
-@@ -1233,7 +1234,7 @@ bool dp_validate_mode_timing(
- 	uint32_t req_bw;
- 	uint32_t max_bw;
- 
--	const struct link_settings *link_setting;
-+	const struct dc_link_settings *link_setting;
- 
- 	/*always DP fail safe mode*/
- 	if (timing->pix_clk_khz == (uint32_t)25175 &&
-@@ -1275,10 +1276,10 @@ bool dp_validate_mode_timing(
- }
- 
- void decide_link_settings(struct core_stream *stream,
--	struct link_settings *link_setting)
-+	struct dc_link_settings *link_setting)
- {
- 
--	const struct link_settings *cur_ls;
-+	const struct dc_link_settings *cur_ls;
- 	struct core_link* link;
- 	uint32_t req_bw;
- 	uint32_t link_bw;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 2d78e52..a3e0da9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -54,7 +54,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
- void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
--	const struct link_settings *link_settings)
-+	const struct dc_link_settings *link_settings)
- {
- 	struct link_encoder *link_enc = link->link_enc;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 45d39c7..c09af66 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -284,11 +284,11 @@ struct dc_link {
- 	/* caps is the same as reported_link_cap. link_traing use
- 	 * reported_link_cap. Will clean up.  TODO
- 	 */
--	struct link_settings reported_link_cap;
--	struct link_settings verified_link_cap;
--	struct link_settings max_link_setting;
--	struct link_settings cur_link_settings;
--	struct lane_settings ln_setting;
-+	struct dc_link_settings reported_link_cap;
-+	struct dc_link_settings verified_link_cap;
-+	struct dc_link_settings max_link_setting;
-+	struct dc_link_settings cur_link_settings;
-+	struct dc_lane_settings cur_lane_setting;
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_dp_types.h b/drivers/gpu/drm/amd/dal/dc/dc_dp_types.h
-new file mode 100644
-index 0000000..e271ea9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_dp_types.h
-@@ -0,0 +1,100 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_DP_TYPES_H
-+#define DC_DP_TYPES_H
-+
-+enum dc_lane_count {
-+	LANE_COUNT_UNKNOWN = 0,
-+	LANE_COUNT_ONE = 1,
-+	LANE_COUNT_TWO = 2,
-+	LANE_COUNT_FOUR = 4,
-+	LANE_COUNT_EIGHT = 8,
-+	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
-+};
-+
-+/* This is actually a reference clock (27MHz) multiplier
-+ * 162MBps bandwidth for 1.62GHz like rate,
-+ * 270MBps for 2.70GHz,
-+ * 324MBps for 3.24Ghz,
-+ * 540MBps for 5.40GHz
-+ * 810MBps for 8.10GHz
-+ */
-+enum dc_link_rate {
-+	LINK_RATE_UNKNOWN = 0,
-+	LINK_RATE_LOW = 0x06,
-+	LINK_RATE_HIGH = 0x0A,
-+	LINK_RATE_RBR2 = 0x0C,
-+	LINK_RATE_HIGH2 = 0x14,
-+	LINK_RATE_HIGH3 = 0x1E
-+};
-+
-+enum dc_link_spread {
-+	LINK_SPREAD_DISABLED = 0x00,
-+	/* 0.5 % downspread 30 kHz */
-+	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
-+	/* 0.5 % downspread 33 kHz */
-+	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
-+};
-+
-+enum dc_voltage_swing {
-+	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
-+	VOLTAGE_SWING_LEVEL1,
-+	VOLTAGE_SWING_LEVEL2,
-+	VOLTAGE_SWING_LEVEL3,
-+	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
-+};
-+
-+enum dc_pre_emphasis {
-+	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
-+	PRE_EMPHASIS_LEVEL1,
-+	PRE_EMPHASIS_LEVEL2,
-+	PRE_EMPHASIS_LEVEL3,
-+	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
-+};
-+/* Post Cursor 2 is optional for transmitter
-+ * and it applies only to the main link operating at HBR2
-+ */
-+enum dc_post_cursor2 {
-+	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
-+	POST_CURSOR2_LEVEL1,
-+	POST_CURSOR2_LEVEL2,
-+	POST_CURSOR2_LEVEL3,
-+	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
-+};
-+
-+struct dc_link_settings {
-+	enum dc_lane_count lane_count;
-+	enum dc_link_rate link_rate;
-+	enum dc_link_spread link_spread;
-+};
-+
-+struct dc_lane_settings {
-+	enum dc_voltage_swing VOLTAGE_SWING;
-+	enum dc_pre_emphasis PRE_EMPHASIS;
-+	enum dc_post_cursor2 POST_CURSOR2;
-+};
-+
-+#endif /* DC_DP_TYPES_H */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 2abdda7..1701953 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -28,6 +28,7 @@
- #include "fixed32_32.h"
- #include "fixed31_32.h"
- #include "irq_types.h"
-+#include "dc_dp_types.h"
- 
- /* forward declarations */
- struct dc;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index e721398..cee25d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -616,7 +616,7 @@ static void update_info_frame(struct core_stream *stream)
- 
- static void enable_stream(struct core_stream *stream)
- {
--	enum lane_count lane_count =
-+	enum dc_lane_count lane_count =
- 			stream->sink->link->public.cur_link_settings.lane_count;
- 
- 	struct dc_crtc_timing *timing = &stream->public.timing;
-@@ -697,7 +697,7 @@ static void disable_stream(struct core_stream *stream)
- }
- 
- static void unblank_stream(struct core_stream *stream,
--		struct link_settings *link_settings)
-+		struct dc_link_settings *link_settings)
- {
- 	struct encoder_unblank_param params = { { 0 } };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 7f663de..3c78431 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -564,7 +564,7 @@ static uint8_t get_frontend_source(
- 
- static void configure_encoder(
- 	struct dce110_link_encoder *enc110,
--	const struct link_settings *link_settings)
-+	const struct dc_link_settings *link_settings)
- {
- 	struct dc_context *ctx = enc110->base.ctx;
- 	uint32_t addr;
-@@ -1351,7 +1351,7 @@ void dce110_link_encoder_enable_tmds_output(
- /* enables DP PHY output */
- void dce110_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
-+	const struct dc_link_settings *link_settings,
- 	enum clock_source_id clock_source)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-@@ -1394,7 +1394,7 @@ void dce110_link_encoder_enable_dp_output(
- /* enables DP PHY output in MST mode */
- void dce110_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
-+	const struct dc_link_settings *link_settings,
- 	enum clock_source_id clock_source)
- {
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 1269833..64a81f2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -107,13 +107,13 @@ void dce110_link_encoder_enable_tmds_output(
- /* enables DP PHY output */
- void dce110_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
-+	const struct dc_link_settings *link_settings,
- 	enum clock_source_id clock_source);
- 
- /* enables DP PHY output in MST mode */
- void dce110_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
-+	const struct dc_link_settings *link_settings,
- 	enum clock_source_id clock_source);
- 
- /* disable PHY output */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 33f700e..604aa43 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -282,7 +282,7 @@ struct dc_pp_single_disp_config {
- 	uint32_t src_width;
- 	uint32_t v_refresh;
- 	uint32_t sym_clock; /* HDMI only */
--	struct link_settings link_settings; /* DP only */
-+	struct dc_link_settings link_settings; /* DP only */
- };
- 
- struct dc_pp_display_configuration {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-index 682c0b4..a0ab6b3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-@@ -28,11 +28,11 @@
- 
- struct core_link;
- struct core_stream;
--struct link_settings;
-+struct dc_link_settings;
- 
- bool dp_hbr_verify_link_cap(
- 	struct core_link *link,
--	struct link_settings *known_limit_link_setting);
-+	struct dc_link_settings *known_limit_link_setting);
- 
- bool dp_validate_mode_timing(
- 	struct core_link *link,
-@@ -40,11 +40,11 @@ bool dp_validate_mode_timing(
- 
- void decide_link_settings(
- 	struct core_stream *stream,
--	struct link_settings *link_setting);
-+	struct dc_link_settings *link_setting);
- 
- bool perform_link_training(
- 	struct core_link *link,
--	const struct link_settings *link_setting,
-+	const struct dc_link_settings *link_setting,
- 	bool skip_video_pattern);
- 
- bool is_mst_supported(struct core_link *link);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index 1f53c8f..54e75dc 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -16,7 +16,7 @@ struct dc_context;
- struct adapter_service;
- struct encoder_set_dp_phy_pattern_param;
- struct link_mst_stream_allocation_table;
--struct link_settings;
-+struct dc_link_settings;
- struct link_training_settings;
- struct core_stream;
- 
-@@ -94,10 +94,10 @@ struct link_encoder_funcs {
- 		bool dual_link,
- 		uint32_t pixel_clock);
- 	void (*enable_dp_output)(struct link_encoder *enc,
--		const struct link_settings *link_settings,
-+		const struct dc_link_settings *link_settings,
- 		enum clock_source_id clock_source);
- 	void (*enable_dp_mst_output)(struct link_encoder *enc,
--		const struct link_settings *link_settings,
-+		const struct dc_link_settings *link_settings,
- 		enum clock_source_id clock_source);
- 	void (*disable_output)(struct link_encoder *link_enc,
- 		enum signal_type signal);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index d9a48c0..551caa3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -43,7 +43,7 @@ enum dc_status core_link_write_dpcd(
- void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
--	const struct link_settings *link_settings);
-+	const struct dc_link_settings *link_settings);
- 
- void dp_receiver_power_ctrl(struct core_link *link, bool on);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-index 6bb1d00..47cf6de 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-@@ -35,7 +35,7 @@ struct encoder_info_frame {
- 
- struct encoder_unblank_param {
- 	struct hw_crtc_timing crtc_timing;
--	struct link_settings link_settings;
-+	struct dc_link_settings link_settings;
- };
- 
- struct encoder_set_dp_phy_pattern_param {
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-index ade443d..36886a4 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -49,12 +49,12 @@ static void virtual_link_encoder_enable_tmds_output(
- 
- static void virtual_link_encoder_enable_dp_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
-+	const struct dc_link_settings *link_settings,
- 	enum clock_source_id clock_source) {}
- 
- static void virtual_link_encoder_enable_dp_mst_output(
- 	struct link_encoder *enc,
--	const struct link_settings *link_settings,
-+	const struct dc_link_settings *link_settings,
- 	enum clock_source_id clock_source) {}
- 
- static void virtual_link_encoder_disable_output(
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-index 550ac87..83766fe 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h
-@@ -96,7 +96,7 @@ struct bp_encoder_control {
- 	enum engine_id engine_id;
- 	enum transmitter transmitter;
- 	enum signal_type signal;
--	enum lane_count lanes_number;
-+	enum dc_lane_count lanes_number;
- 	enum dc_color_depth color_depth;
- 	bool enable_dp_audio;
- 	uint32_t pixel_clock; /* khz */
-@@ -105,8 +105,8 @@ struct bp_encoder_control {
- struct bp_external_encoder_control {
- 	enum bp_external_encoder_control_action action;
- 	enum engine_id engine_id;
--	enum link_rate link_rate;
--	enum lane_count lanes_number;
-+	enum dc_link_rate link_rate;
-+	enum dc_lane_count lanes_number;
- 	enum signal_type signal;
- 	enum dc_color_depth color_depth;
- 	bool coherent;
-@@ -130,7 +130,7 @@ struct bp_transmitter_control {
- 	enum bp_transmitter_control_action action;
- 	enum engine_id engine_id;
- 	enum transmitter transmitter; /* PhyId */
--	enum lane_count lanes_number;
-+	enum dc_lane_count lanes_number;
- 	enum clock_source_id pll_id; /* needed for DCE 4.0 */
- 	enum signal_type signal;
- 	enum dc_color_depth color_depth; /* not used for DCE6.0 */
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 7db598b..a14c4af 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -52,33 +52,6 @@ struct link_validation_flags {
- 	uint32_t START_OF_VALIDATION:1;
- };
- 
--/* Post Cursor 2 is optional for transmitter
-- * and it applies only to the main link operating at HBR2
-- */
--enum post_cursor2 {
--	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
--	POST_CURSOR2_LEVEL1,
--	POST_CURSOR2_LEVEL2,
--	POST_CURSOR2_LEVEL3,
--	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
--};
--
--enum voltage_swing {
--	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
--	VOLTAGE_SWING_LEVEL1,
--	VOLTAGE_SWING_LEVEL2,
--	VOLTAGE_SWING_LEVEL3,
--	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
--};
--
--enum pre_emphasis {
--	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
--	PRE_EMPHASIS_LEVEL1,
--	PRE_EMPHASIS_LEVEL2,
--	PRE_EMPHASIS_LEVEL3,
--	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
--};
--
- enum dpcd_value_mask {
- 	DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F,
- 	DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40,
-@@ -109,43 +82,6 @@ enum edp_revision {
- 	EDP_REVISION_13 = 0x02
- };
- 
--enum lane_count {
--	LANE_COUNT_UNKNOWN = 0,
--	LANE_COUNT_ONE = 1,
--	LANE_COUNT_TWO = 2,
--	LANE_COUNT_FOUR = 4,
--	LANE_COUNT_EIGHT = 8,
--	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
--};
--
--/* This is actually a reference clock (27MHz) multiplier
-- * 162MBps bandwidth for 1.62GHz like rate,
-- * 270MBps for 2.70GHz,
-- * 324MBps for 3.24Ghz,
-- * 540MBps for 5.40GHz
-- * 810MBps for 8.10GHz
-- */
--enum link_rate {
--	LINK_RATE_UNKNOWN = 0,
--	LINK_RATE_LOW = 0x06,
--	LINK_RATE_HIGH = 0x0A,
--	LINK_RATE_RBR2 = 0x0C,
--	LINK_RATE_HIGH2 = 0x14,
--	LINK_RATE_HIGH3 = 0x1E
--};
--
--enum {
--	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
--};
--
--enum link_spread {
--	LINK_SPREAD_DISABLED = 0x00,
--	/* 0.5 % downspread 30 kHz */
--	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
--	/* 0.5 % downspread 33 kHz */
--	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
--};
--
- /* DPCD_ADDR_DOWNSTREAM_PORT_PRESENT register value */
- union dpcd_downstream_port {
- 	struct {
-@@ -186,21 +122,13 @@ union dpcd_sink_count {
- 	uint8_t raw;
- };
- 
--struct link_settings {
--	enum lane_count lane_count;
--	enum link_rate link_rate;
--	enum link_spread link_spread;
--};
--
--struct lane_settings {
--	enum voltage_swing VOLTAGE_SWING;
--	enum pre_emphasis PRE_EMPHASIS;
--	enum post_cursor2 POST_CURSOR2;
-+enum {
-+	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
- };
- 
- struct link_training_settings {
--	struct link_settings link_settings;
--	struct lane_settings lane_settings[LANE_COUNT_DP_MAX];
-+	struct dc_link_settings link_settings;
-+	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
- 	bool allow_invalid_msa_timing_param;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0777-drm-amd-dal-fix-dependency-on-DC.patch b/common/recipes-kernel/linux/files/0777-drm-amd-dal-fix-dependency-on-DC.patch
deleted file mode 100644
index 55060865..00000000
--- a/common/recipes-kernel/linux/files/0777-drm-amd-dal-fix-dependency-on-DC.patch
+++ /dev/null
@@ -1,194 +0,0 @@
-From 7030579959edecd65fd7b6986191438cfcf0c8e6 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 5 Feb 2016 09:35:55 -0500
-Subject: [PATCH 0777/1110] drm/amd/dal: fix dependency on DC
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c |  2 ++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h |  1 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c          | 44 +++------------------------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c     |  8 +++++
- drivers/gpu/drm/amd/dal/dc/dc.h               | 22 ++++++++------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h   |  2 ++
- 6 files changed, 30 insertions(+), 49 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index c758fc6..6329658 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1474,3 +1474,5 @@ bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm)
- 	/* TODO */
- 	return true;
- }
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index c4ae90b..4a9b1c3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -47,6 +47,7 @@
- */
- 
- #include "irq_types.h"
-+#include "signal_types.h"
- 
- /* Forward declarations */
- struct amdgpu_device;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 0af63f8..d788917 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -887,46 +887,10 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink
- 	}
- }
- 
--uint8_t dc_get_dig_index(const struct dc_stream *stream)
--{
--
--	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
--
--	switch (core_stream->stream_enc->id) {
--	case ENGINE_ID_DIGA:
--		return 0;
--	case ENGINE_ID_DIGB:
--		return 1;
--	case ENGINE_ID_DIGC:
--		return 2;
--	case ENGINE_ID_DIGD:
--		return 3;
--	case ENGINE_ID_DIGE:
--		return 4;
--	case ENGINE_ID_DIGF:
--		return 5;
--	case ENGINE_ID_DIGG:
--		return 6;
--	default:
--		return -1;
--	}
--
--	return 0;
--}
--
--enum gpio_ddc_line dc_get_ddc_line(
--		const struct dc_stream *stream)
-+const struct dc_stream_status *dc_stream_get_status(
-+	const struct dc_stream *dc_stream)
- {
-+	struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
- 
--	struct core_sink *core_sink = DC_SINK_TO_CORE(stream->sink);
--	struct ddc *ddc_line = dal_ddc_service_get_ddc_pin(
--			core_sink->link->ddc);
--
--	return dal_ddc_get_line(ddc_line);
--}
--
--enum signal_type dc_get_display_signal(
--		const struct dc_stream *stream)
--{
--	return stream->sink->sink_signal;
-+	return &stream->status;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 9e04b45..84ee1b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -977,6 +977,10 @@ static bool construct(
- 	ddc_service_init_data.id = link->link_id;
- 	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
- 
-+	link->public.ddc_hw_inst =
-+		dal_ddc_get_line(
-+			dal_ddc_service_get_ddc_pin(link->ddc));
-+
- 	if (NULL == link->ddc) {
- 		DC_ERROR("Failed to create ddc_service!\n");
- 		goto create_fail;
-@@ -999,6 +1003,8 @@ static bool construct(
- 		goto create_fail;
- 	}
- 
-+	link->public.link_enc_hw_inst = link->link_enc->transmitter;
-+
- 	dal_adapter_service_get_integrated_info(as, &info);
- 
- 	for (i = 0; ; i++) {
-@@ -1621,6 +1627,7 @@ void core_link_enable_stream(
- 	}
- 
- 	dc->hwss.enable_stream(stream);
-+	stream->status.link = &link->public;
- 
- 	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		allocate_mst_payload(stream);
-@@ -1635,6 +1642,7 @@ void core_link_disable_stream(
- 	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		deallocate_mst_payload(stream);
- 
-+	stream->status.link = NULL;
- 	dc->hwss.disable_stream(stream);
- 
- 	disable_link(stream);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index c09af66..cc3395d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -264,6 +264,16 @@ void dc_stream_release(struct dc_stream *dc_stream);
- void dc_update_stream(const struct dc_stream *dc_stream,
- 		struct rect *src, struct rect *dst);
- 
-+struct dc_stream_status {
-+	/*
-+	 * link this stream passes through
-+	 */
-+	const struct dc_link *link;
-+};
-+
-+const struct dc_stream_status *dc_stream_get_status(
-+	const struct dc_stream *dc_stream);
-+
- /*******************************************************************************
-  * Link Interfaces
-  ******************************************************************************/
-@@ -289,6 +299,9 @@ struct dc_link {
- 	struct dc_link_settings max_link_setting;
- 	struct dc_link_settings cur_link_settings;
- 	struct dc_lane_settings cur_lane_setting;
-+
-+	uint8_t ddc_hw_inst;
-+	uint8_t link_enc_hw_inst;
- };
- 
- /*
-@@ -460,13 +473,4 @@ bool dc_write_dpcd(
- 	uint32_t size);
- 
- 
--uint8_t dc_get_dig_index(const struct dc_stream *stream);
--
--enum signal_type  dc_get_display_signal(
--		const struct dc_stream *stream);
--
--enum gpio_ddc_line dc_get_ddc_line(
--		const struct dc_stream *stream);
--
--
- #endif /* DC_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index bd7bd2b..866853b 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -128,6 +128,8 @@ struct core_stream {
- 
- 	struct audio_output audio_output;
- 	struct dc_context *ctx;
-+
-+	struct dc_stream_status status;
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0778-drm-amd-dal-Add-timing-generator-for-underlay-pipe.patch b/common/recipes-kernel/linux/files/0778-drm-amd-dal-Add-timing-generator-for-underlay-pipe.patch
deleted file mode 100644
index 93b86f71..00000000
--- a/common/recipes-kernel/linux/files/0778-drm-amd-dal-Add-timing-generator-for-underlay-pipe.patch
+++ /dev/null
@@ -1,877 +0,0 @@
-From 7da2abf1b61ca0b039d2d1683aff6cef8f086934 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 3 Feb 2016 16:13:11 -0500
-Subject: [PATCH 0778/1110] drm/amd/dal: Add timing generator for underlay pipe
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   3 +
- .../amd/dal/dc/dce110/dce110_timing_generator_v.c  | 785 +++++++++++++++++++++
- .../amd/dal/dc/dce110/dce110_timing_generator_v.h  |  34 +
- 4 files changed, 823 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index d7cdd91..8fb90c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -190,7 +190,7 @@ static void dce110_timing_generator_apply_front_porch_workaround(
- 	}
- }
- 
--static void dce110_timing_generator_color_space_to_black_color(
-+void dce110_timing_generator_color_space_to_black_color(
- 		enum color_space colorspace,
- 	struct crtc_black_color *black_color)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 163fadd..3579736 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -175,6 +175,9 @@ void dce110_timing_generator_program_blank_color(
- void dce110_timing_generator_set_overscan_color_black(
- 	struct timing_generator *tg,
- 	enum color_space black_color);
-+void dce110_timing_generator_color_space_to_black_color(
-+		enum color_space colorspace,
-+	struct crtc_black_color *black_color);
- /*************** End-of-move ********************/
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-new file mode 100644
-index 0000000..722f636
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -0,0 +1,785 @@
-+
-+
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "dc_bios_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/adapter_service_interface.h"
-+#include "include/logger_interface.h"
-+#include "dce110_timing_generator.h"
-+#include "dce110_timing_generator_v.h"
-+
-+#include "../inc/timing_generator.h"
-+
-+
-+/** ********************************************************************************
-+ *
-+ * DCE11 Timing Generator Implementation
-+ *
-+ **********************************************************************************/
-+
-+/**
-+* Enable CRTCV
-+*/
-+
-+static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
-+{
-+    /*
-+     * Set MASTER_UPDATE_MODE to 0
-+     * This is needed for DRR, and also suggested to be default value by Syed.
-+     */
-+
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	value = dm_read_reg(tg->ctx,
-+			mmCRTCV_MASTER_UPDATE_MODE);
-+	set_reg_field_value(value, 0,
-+			CRTCV_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
-+	dm_write_reg(tg->ctx,
-+			mmCRTCV_MASTER_UPDATE_MODE, value);
-+
-+	value = dm_read_reg(tg->ctx,
-+			mmCRTCV_MASTER_EN);
-+	set_reg_field_value(value, 1,
-+			CRTCV_MASTER_EN, CRTC_MASTER_EN);
-+	dm_write_reg(tg->ctx,
-+			mmCRTCV_MASTER_EN, value);
-+
-+	return true;
-+}
-+
-+static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	value = dm_read_reg(tg->ctx,
-+			mmCRTCV_CONTROL);
-+	set_reg_field_value(value, 0,
-+			CRTCV_CONTROL, CRTC_DISABLE_POINT_CNTL);
-+	set_reg_field_value(value, 0,
-+				CRTCV_CONTROL, CRTC_MASTER_EN);
-+	dm_write_reg(tg->ctx,
-+			mmCRTCV_CONTROL, value);
-+	/*
-+	 * TODO: call this when adding stereo support
-+	 * tg->funcs->disable_stereo(tg);
-+	 */
-+	return true;
-+}
-+
-+static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = mmCRTCV_BLANK_CONTROL;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+	uint8_t counter = 100;
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DE_MODE);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+
-+	while (counter > 0) {
-+		value = dm_read_reg(tg->ctx, addr);
-+
-+		if (get_reg_field_value(
-+			value,
-+			CRTCV_BLANK_CONTROL,
-+			CRTC_BLANK_DATA_EN) == 1 &&
-+			get_reg_field_value(
-+			value,
-+			CRTCV_BLANK_CONTROL,
-+			CRTC_CURRENT_BLANK_STATE) == 1)
-+			break;
-+
-+		dm_sleep_in_milliseconds(tg->ctx, 1);
-+		counter--;
-+	}
-+
-+	if (!counter) {
-+		dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"timing generator %d blank timing out.\n",
-+				tg110->controller_id);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = mmCRTCV_BLANK_CONTROL;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DE_MODE);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+
-+	return true;
-+}
-+
-+static bool dce110_timing_generator_v_is_in_vertical_blank(
-+		struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	addr = mmCRTCV_STATUS;
-+	value = dm_read_reg(tg->ctx, addr);
-+	field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK);
-+	return field == 1;
-+}
-+
-+static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	uint32_t h1 = 0;
-+	uint32_t h2 = 0;
-+	uint32_t v1 = 0;
-+	uint32_t v2 = 0;
-+
-+	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
-+
-+	h1 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	v1 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+
-+	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
-+
-+	h2 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	v2 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+
-+	if (h1 == h2 && v1 == v2)
-+		return false;
-+	else
-+		return true;
-+}
-+
-+static void dce110_timing_generator_v_wait_for_vblank(struct timing_generator *tg)
-+{
-+	/* We want to catch beginning of VBlank here, so if the first try are
-+	 * in VBlank, we might be very close to Active, in this case wait for
-+	 * another frame
-+	 */
-+	while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_v_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+
-+	while (!dce110_timing_generator_v_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_v_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/**
-+* Wait till we are in VActive (anywhere in VActive)
-+*/
-+static void dce110_timing_generator_v_wait_for_vactive(struct timing_generator *tg)
-+{
-+	while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_v_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+static void dce110_timing_generator_v_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state)
-+{
-+	switch (state) {
-+	case CRTC_STATE_VBLANK:
-+		dce110_timing_generator_v_wait_for_vblank(tg);
-+		break;
-+
-+	case CRTC_STATE_VACTIVE:
-+		dce110_timing_generator_v_wait_for_vactive(tg);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+static void dce110_timing_generator_v_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t vsync_offset = timing->v_border_bottom +
-+			timing->v_front_porch;
-+	uint32_t v_sync_start = timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+	uint32_t tmp = 0;
-+
-+	addr = mmCRTCV_H_TOTAL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->h_total - 1,
-+		CRTCV_H_TOTAL,
-+		CRTC_H_TOTAL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_V_TOTAL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->v_total - 1,
-+		CRTCV_V_TOTAL,
-+		CRTC_V_TOTAL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_H_BLANK_START_END;
-+	value = dm_read_reg(ctx, addr);
-+
-+	tmp = timing->h_total -
-+		(h_sync_start + timing->h_border_left);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_H_BLANK_START_END,
-+		CRTC_H_BLANK_END);
-+
-+	tmp = tmp + timing->h_addressable +
-+		timing->h_border_left + timing->h_border_right;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_H_BLANK_START_END,
-+		CRTC_H_BLANK_START);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_V_BLANK_START_END;
-+	value = dm_read_reg(ctx, addr);
-+
-+	tmp = timing->v_total - (v_sync_start + timing->v_border_top);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_V_BLANK_START_END,
-+		CRTC_V_BLANK_END);
-+
-+	tmp = tmp + timing->v_addressable + timing->v_border_top +
-+		timing->v_border_bottom;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_V_BLANK_START_END,
-+		CRTC_V_BLANK_START);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = mmCRTCV_START_LINE_CONTROL;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (enable) {
-+		if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
-+			set_reg_field_value(
-+				value,
-+				3,
-+				CRTCV_START_LINE_CONTROL,
-+				CRTC_ADVANCED_START_LINE_POSITION);
-+		} else {
-+			set_reg_field_value(
-+				value,
-+				4,
-+				CRTCV_START_LINE_CONTROL,
-+				CRTC_ADVANCED_START_LINE_POSITION);
-+		}
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTCV_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			2,
-+			CRTCV_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTCV_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	}
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static bool dce110_timing_generator_v_set_blank(struct timing_generator *tg,
-+		bool enable_blanking)
-+{
-+	if (enable_blanking)
-+		return dce110_timing_generator_v_blank_crtc(tg);
-+	else
-+		return dce110_timing_generator_v_unblank_crtc(tg);
-+}
-+
-+static void dce110_timing_generator_v_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (use_vbios)
-+		dce110_timing_generator_program_timing_generator(tg, timing);
-+	else
-+		dce110_timing_generator_v_program_blanking(tg, timing);
-+}
-+
-+static void dce110_timing_generator_v_program_blank_color(
-+		struct timing_generator *tg,
-+		enum color_space color_space)
-+{
-+	struct crtc_black_color black_color;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = mmCRTCV_BLACK_COLOR;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	dce110_timing_generator_color_space_to_black_color(
-+		color_space,
-+		&black_color);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color.black_color_b_cb,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color.black_color_g_y,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color.black_color_r_cr,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	enum color_space black_color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	/* Overscan Color for YUV display modes:
-+	 * to achieve a black color for both the explicit and implicit overscan,
-+	 * the overscan color registers should be programmed to: */
-+
-+	switch (black_color) {
-+	case COLOR_SPACE_YPBPR601:
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4TV,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4TV,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4TV,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	case COLOR_SPACE_YPBPR709:
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_YONLY:
-+	case COLOR_SPACE_YCBCR709_YONLY:
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4TV,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4CV,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	case COLOR_SPACE_N_MVPU_SUPER_AA:
-+		/* In crossfire SuperAA mode, the slave overscan data is forced
-+		 * to 0 in the pixel mixer on the master.  As a result, we need
-+		 * to adjust the blank color so that after blending the
-+		 * master+slave, it will appear black */
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4SUPERAA,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4SUPERAA,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_RGB_LIMITED_RANGE,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_RGB_LIMITED_RANGE,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+		set_reg_field_value(
-+			value,
-+			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_RGB_LIMITED_RANGE,
-+			CRTCV_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+		break;
-+
-+	default:
-+		/* default is sRGB black 0. */
-+		break;
-+	}
-+	addr = mmCRTCV_OVERSCAN_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+	addr = mmCRTCV_BLACK_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+	/* This is desirable to have a constant DAC output voltage during the
-+	 * blank time that is higher than the 0 volt reference level that the
-+	 * DAC outputs when the NBLANK signal
-+	 * is asserted low, such as for output to an analog TV. */
-+	addr = mmCRTCV_BLANK_DATA_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* TO DO we have to program EXT registers and we need to know LB DATA
-+	 * format because it is used when more 10 , i.e. 12 bits per color
-+	 *
-+	 * m_mmDxCRTC_OVERSCAN_COLOR_EXT
-+	 * m_mmDxCRTC_BLACK_COLOR_EXT
-+	 * m_mmDxCRTC_BLANK_DATA_COLOR_EXT
-+	 */
-+
-+}
-+
-+static void dce110_tg_v_program_blank_color(struct timing_generator *tg,
-+		const struct crtc_black_color *black_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = mmCRTCV_BLACK_COLOR;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color->black_color_b_cb,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color->black_color_g_y,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color->black_color_r_cr,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+
-+	addr = mmCRTCV_BLANK_DATA_COLOR;
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_overscan_color(struct timing_generator *tg,
-+	const struct crtc_black_color *overscan_color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->black_color_b_cb,
-+		CRTCV_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_BLUE);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->black_color_g_y,
-+		CRTCV_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_GREEN);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->black_color_r_cr,
-+		CRTCV_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_RED);
-+
-+	addr = mmCRTCV_OVERSCAN_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_colors(struct timing_generator *tg,
-+	const struct crtc_black_color *blank_color,
-+	const struct crtc_black_color *overscan_color)
-+{
-+	if (blank_color != NULL)
-+		dce110_tg_v_program_blank_color(tg, blank_color);
-+	if (overscan_color != NULL)
-+		dce110_timing_generator_v_set_overscan_color(tg, overscan_color);
-+}
-+
-+
-+static void dce110_timing_generator_v_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl)
-+{
-+	uint32_t regval;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t address = mmCRTC_CONTROL;
-+
-+	regval = dm_read_reg(tg->ctx, address);
-+	set_reg_field_value(regval, early_cntl,
-+			CRTCV_CONTROL, CRTC_HBLANK_EARLY_CONTROL);
-+	dm_write_reg(tg->ctx, address, regval);
-+}
-+
-+static void dce110_timing_generator_v_get_crtc_positions(
-+	struct timing_generator *tg,
-+	int32_t *h_position,
-+	int32_t *v_position)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
-+
-+	*h_position = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	*v_position = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+}
-+
-+static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+	uint32_t field = get_reg_field_value(
-+			value, CRTCV_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
-+
-+	return field;
-+}
-+
-+static bool dce110_timing_generator_v_did_triggered_reset_occur(
-+	struct timing_generator *tg)
-+{
-+	dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+					LOG_MINOR_COMPONENT_CONTROLLER,
-+					"Timing Sync not supported on underlay pipe\n");
-+	return false;
-+}
-+
-+static void dce110_timing_generator_v_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params)
-+{
-+	dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+					LOG_MINOR_COMPONENT_CONTROLLER,
-+					"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	const struct trigger_params *trigger_params)
-+{
-+	dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+					LOG_MINOR_COMPONENT_CONTROLLER,
-+					"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_disable_reset_trigger(
-+	struct timing_generator *tg)
-+{
-+	dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+						LOG_MINOR_COMPONENT_CONTROLLER,
-+						"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_tear_down_global_swap_lock(
-+	struct timing_generator *tg)
-+{
-+	dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
-+						LOG_MINOR_COMPONENT_CONTROLLER,
-+						"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_disable_vga(
-+	struct timing_generator *tg)
-+{
-+	return;
-+}
-+/** ********************************************************************************************
-+ *
-+ * DCE11 Timing Generator Constructor / Destructor
-+ *
-+ *********************************************************************************************/
-+static struct timing_generator_funcs dce110_tg_v_funcs = {
-+		.validate_timing = dce110_tg_validate_timing,
-+		.program_timing = dce110_timing_generator_v_program_timing,
-+		.enable_crtc = dce110_timing_generator_v_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_v_disable_crtc,
-+		.is_counter_moving = dce110_timing_generator_v_is_counter_moving,
-+		.get_position = dce110_timing_generator_v_get_crtc_positions,
-+		.get_frame_count = dce110_timing_generator_v_get_vblank_counter,
-+		.set_early_control = dce110_timing_generator_v_set_early_control,
-+		.wait_for_state = dce110_timing_generator_v_wait_for_state,
-+		.set_blank = dce110_timing_generator_v_set_blank,
-+		.set_colors = dce110_timing_generator_v_set_colors,
-+		.set_overscan_blank_color =
-+				dce110_timing_generator_v_set_overscan_color_black,
-+		.set_blank_color = dce110_timing_generator_v_program_blank_color,
-+		.disable_vga = dce110_timing_generator_v_disable_vga,
-+		.did_triggered_reset_occur =
-+				dce110_timing_generator_v_did_triggered_reset_occur,
-+		.setup_global_swap_lock =
-+				dce110_timing_generator_v_setup_global_swap_lock,
-+		.enable_reset_trigger = dce110_timing_generator_v_enable_reset_trigger,
-+		.disable_reset_trigger = dce110_timing_generator_v_disable_reset_trigger,
-+		.tear_down_global_swap_lock =
-+				dce110_timing_generator_v_tear_down_global_swap_lock,
-+		.enable_advanced_request =
-+				dce110_timing_generator_v_enable_advanced_request
-+};
-+
-+bool dce110_timing_generator_v_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	if (!tg110)
-+		return false;
-+
-+	if (!as)
-+		return false;
-+
-+	tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
-+
-+	tg110->base.funcs = &dce110_tg_v_funcs;
-+
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = dal_adapter_service_get_bios_parser(as);
-+
-+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	tg110->min_h_blank = 56;
-+	tg110->min_h_front_porch = 4;
-+	tg110->min_h_back_porch = 4;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h
-new file mode 100644
-index 0000000..fe3fb81
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_V_DCE110_H__
-+#define __DC_TIMING_GENERATOR_V_DCE110_H__
-+
-+bool dce110_timing_generator_v_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct adapter_service *as,
-+	struct dc_context *ctx);
-+
-+#endif /* __DC_TIMING_GENERATOR_V_DCE110_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0779-drm-amd-dal-Remove-unused-definitions-from-Transform.patch b/common/recipes-kernel/linux/files/0779-drm-amd-dal-Remove-unused-definitions-from-Transform.patch
deleted file mode 100644
index a4d6c492..00000000
--- a/common/recipes-kernel/linux/files/0779-drm-amd-dal-Remove-unused-definitions-from-Transform.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From df2dc58e3e455f9f6e4ef3cb8c8a91734168fb75 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Fri, 5 Feb 2016 17:29:08 -0500
-Subject: [PATCH 0779/1110] drm/amd/dal: Remove unused definitions from
- Transform interface - part 1.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 18 +++++++
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         | 60 ----------------------
- 2 files changed, 18 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index 34fedc5..6491435 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -36,6 +36,24 @@
- #define NOT_IMPLEMENTED()  DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_CONTROLLER,\
- 			"TRANSFORM SCALER:%s()\n", __func__)
- #define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-+
-+
-+struct sclv_ratios_inits {
-+	uint32_t chroma_enable;
-+	uint32_t h_int_scale_ratio_luma;
-+	uint32_t h_int_scale_ratio_chroma;
-+	uint32_t v_int_scale_ratio_luma;
-+	uint32_t v_int_scale_ratio_chroma;
-+	struct init_int_and_frac h_init_luma;
-+	struct init_int_and_frac h_init_chroma;
-+	struct init_int_and_frac v_init_luma;
-+	struct init_int_and_frac v_init_chroma;
-+	struct init_int_and_frac h_init_lumabottom;
-+	struct init_int_and_frac h_init_chromabottom;
-+	struct init_int_and_frac v_init_lumabottom;
-+	struct init_int_and_frac v_init_chromabottom;
-+};
-+
- /*
- *****************************************************************************
- *  Function: calculateViewport
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 2280357..e3fb79c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -33,12 +33,6 @@
- 
- struct bit_depth_reduction_params;
- 
--enum scaling_type {
--	SCALING_TYPE_NO_SCALING = 0,
--	SCALING_TYPE_UPSCALING,
--	SCALING_TYPE_DOWNSCALING
--};
--
- struct transform {
- 	struct transform_funcs *funcs;
- 	struct dc_context *ctx;
-@@ -46,35 +40,6 @@ struct transform {
- 	struct scaler_filter *filter;
- };
- 
--
--struct scaler_taps_and_ratio {
--	uint32_t h_tap;
--	uint32_t v_tap;
--	uint32_t lo_ratio;
--	uint32_t hi_ratio;
--};
--
--struct scaler_taps {
--	uint32_t h_tap;
--	uint32_t v_tap;
--};
--
--struct sclv_ratios_inits {
--	uint32_t chroma_enable;
--	uint32_t h_int_scale_ratio_luma;
--	uint32_t h_int_scale_ratio_chroma;
--	uint32_t v_int_scale_ratio_luma;
--	uint32_t v_int_scale_ratio_chroma;
--	struct init_int_and_frac h_init_luma;
--	struct init_int_and_frac h_init_chroma;
--	struct init_int_and_frac v_init_luma;
--	struct init_int_and_frac v_init_chroma;
--	struct init_int_and_frac h_init_lumabottom;
--	struct init_int_and_frac h_init_chromabottom;
--	struct init_int_and_frac v_init_lumabottom;
--	struct init_int_and_frac v_init_chromabottom;
--};
--
- enum lb_pixel_depth {
- 	/* do not change the values because it is used as bit vector */
- 	LB_PIXEL_DEPTH_18BPP = 1,
-@@ -84,12 +49,6 @@ enum lb_pixel_depth {
- };
- 
- 
--struct raw_gamma_ramp_rgb {
--       uint32_t red;
--       uint32_t green;
--       uint32_t blue;
--};
--
- enum raw_gamma_ramp_type {
-        GAMMA_RAMP_TYPE_UNINITIALIZED,
-        GAMMA_RAMP_TYPE_DEFAULT,
-@@ -98,12 +57,6 @@ enum raw_gamma_ramp_type {
- };
- 
- #define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
--struct raw_gamma_ramp {
--       enum raw_gamma_ramp_type type;
--       struct raw_gamma_ramp_rgb rgb_256[NUM_OF_RAW_GAMMA_RAMP_RGB_256];
--       uint32_t size;
--};
--
- 
- /* Colorimetry */
- enum colorimetry {
-@@ -113,18 +66,6 @@ enum colorimetry {
-        COLORIMETRY_EXTENDED = 3
- };
- 
--/* ColorimetryEx */
--enum colorimetry_ex {
--       COLORIMETRY_EX_XVYCC601 = 0,
--       COLORIMETRY_EX_XVYCC709 = 1,
--       COLORIMETRY_EX_SYCC601 = 2,
--       COLORIMETRY_EX_ADOBEYCC601 = 3,
--       COLORIMETRY_EX_ADOBERGB = 4,
--       COLORIMETRY_EX_RESERVED5 = 5,
--       COLORIMETRY_EX_RESERVED6 = 6,
--       COLORIMETRY_EX_RESERVED7 = 7
--};
--
- enum ds_color_space {
-        DS_COLOR_SPACE_UNKNOWN = 0,
-        DS_COLOR_SPACE_SRGB_FULLRANGE = 1,
-@@ -138,7 +79,6 @@ enum ds_color_space {
-        DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/
- };
- 
--
- enum active_format_info {
-        ACTIVE_FORMAT_NO_DATA = 0,
-        ACTIVE_FORMAT_VALID = 1
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0780-drm-amd-dal-enable-HBR3-link-training.patch b/common/recipes-kernel/linux/files/0780-drm-amd-dal-enable-HBR3-link-training.patch
deleted file mode 100644
index b4101785..00000000
--- a/common/recipes-kernel/linux/files/0780-drm-amd-dal-enable-HBR3-link-training.patch
+++ /dev/null
@@ -1,361 +0,0 @@
-From 8d6e803a45354f029da49dc60eb2d3669859a4ea Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 8 Feb 2016 13:39:40 -0500
-Subject: [PATCH 0780/1110] drm/amd/dal: enable HBR3 link training
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   5 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 131 +++++++++++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |   9 +-
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h        |  29 ++++-
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    |   3 +
- 5 files changed, 112 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 84ee1b4..9a5eadf 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1276,7 +1276,10 @@ static enum dc_status enable_link(struct core_stream *stream)
- 
- static void disable_link(struct core_stream *stream)
- {
--	/* TODO  dp_set_hw_test_pattern */
-+	/*
-+	 * TODO: implement call for dp_set_hw_test_pattern
-+	 * it is needed for compliance testing
-+	 */
- 
- 	/* here we need to specify that encoder output settings
- 	 * need to be calculated as for the set mode,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index f69743a..1cf7ca2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -54,7 +54,7 @@ static void wait_for_training_aux_rd_interval(
- 	struct core_link* link,
- 	uint32_t default_wait_in_micro_secs)
- {
--	uint8_t training_rd_interval;
-+	union training_aux_rd_interval training_rd_interval;
- 
- 	/* overwrite the delay if rev > 1.1*/
- 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
-@@ -63,11 +63,12 @@ static void wait_for_training_aux_rd_interval(
- 		core_link_read_dpcd(
- 			link,
- 			DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL,
--			&training_rd_interval,
-+			(uint8_t *)&training_rd_interval,
- 			sizeof(training_rd_interval));
--		default_wait_in_micro_secs = training_rd_interval ?
--			(training_rd_interval * 4000) :
--			default_wait_in_micro_secs;
-+
-+		if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
-+			default_wait_in_micro_secs =
-+				training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
- 	}
- 
- 	dm_delay_in_microseconds(link->ctx, default_wait_in_micro_secs);
-@@ -96,7 +97,7 @@ static void dpcd_set_training_pattern(
- 		"%s\n %x pattern = %x\n",
- 		__func__,
- 		DPCD_ADDRESS_TRAINING_PATTERN_SET,
--		dpcd_pattern.bits.TRAINING_PATTERN_SET);
-+		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
- }
- 
- static void dpcd_set_link_settings(
-@@ -196,7 +197,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 	/*****************************************************************
- 	* DpcdAddress_TrainingPatternSet
- 	*****************************************************************/
--	dpcd_pattern.bits.TRAINING_PATTERN_SET =
-+	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
- 		hw_training_pattern_to_dpcd_training_pattern(link, pattern);
- 
- 	dpcd_lt_buffer[DPCD_ADDRESS_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
-@@ -208,7 +209,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 		"%s\n %x pattern = %x\n",
- 		__func__,
- 		DPCD_ADDRESS_TRAINING_PATTERN_SET,
--		dpcd_pattern.bits.TRAINING_PATTERN_SET);
-+		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
- 
- 
- 	/*****************************************************************
-@@ -922,14 +923,54 @@ static bool perform_clock_recovery_sequence(
- 	return false;
- }
- 
-- bool perform_link_training(
-+static inline bool perform_link_training_int(
-+	struct core_link *link,
-+	struct link_training_settings *lt_settings,
-+	bool status)
-+{
-+	union lane_count_set lane_count_set = { {0} };
-+	union dpcd_training_pattern dpcd_pattern = { {0} };
-+
-+	/* 3. set training not in progress*/
-+	dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
-+	dpcd_set_training_pattern(link, dpcd_pattern);
-+
-+	/* 4. mainlink output idle pattern*/
-+	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE);
-+
-+	/*
-+	 * 5. post training adjust if required
-+	 * If the upstream DPTX and downstream DPRX both support TPS4,
-+	 * TPS4 must be used instead of POST_LT_ADJ_REQ.
-+	 */
-+	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 &&
-+		get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
-+		return status;
-+
-+	if (status &&
-+		perform_post_lt_adj_req_sequence(link, lt_settings) == false)
-+		status = false;
-+
-+	lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
-+	lane_count_set.bits.ENHANCED_FRAMING = 1;
-+	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
-+
-+	core_link_write_dpcd(
-+		link,
-+		DPCD_ADDRESS_LANE_COUNT_SET,
-+		&lane_count_set.raw,
-+		sizeof(lane_count_set));
-+
-+	return status;
-+}
-+
-+bool perform_link_training(
- 	struct core_link *link,
- 	const struct dc_link_settings *link_setting,
- 	bool skip_video_pattern)
- {
- 	bool status;
--	union dpcd_training_pattern dpcd_pattern = {{0}};
--	union lane_count_set lane_count_set = {{0}};
-+
- 	const int8_t *link_rate = "Unknown";
- 	struct link_training_settings lt_settings;
- 
-@@ -961,37 +1002,8 @@ static bool perform_clock_recovery_sequence(
- 			status = true;
- 	}
- 
--	if (status || !skip_video_pattern) {
--
--		/* 3. set training not in progress*/
--		dpcd_pattern.bits.TRAINING_PATTERN_SET =
--			DPCD_TRAINING_PATTERN_VIDEOIDLE;
--		dpcd_set_training_pattern(link, dpcd_pattern);
--
--		/* 4. mainlink output idle pattern*/
--		dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE);
--
--		/* 5. post training adjust if required*/
--		if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED
--			== 1) {
--			if (status == true) {
--				if (perform_post_lt_adj_req_sequence(
--					link, &lt_settings) == false)
--					status = false;
--			}
--
--			lane_count_set.bits.LANE_COUNT_SET =
--				lt_settings.link_settings.lane_count;
--			lane_count_set.bits.ENHANCED_FRAMING = 1;
--			lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
--
--			core_link_write_dpcd(
--				link,
--				DPCD_ADDRESS_LANE_COUNT_SET,
--				&lane_count_set.raw,
--				sizeof(lane_count_set));
--		}
--	}
-+	if (status || !skip_video_pattern)
-+		status = perform_link_training_int(link, &lt_settings, status);
- 
- 	/* 6. print status message*/
- 	switch (lt_settings.link_settings.link_rate) {
-@@ -1008,6 +1020,9 @@ static bool perform_clock_recovery_sequence(
- 	case LINK_RATE_RBR2:
- 		link_rate = "RBR2";
- 		break;
-+	case LINK_RATE_HIGH3:
-+		link_rate = "High3";
-+		break;
- 	default:
- 		break;
- 	}
-@@ -1674,9 +1689,7 @@ static void dp_wa_power_up_0010FA(struct core_link *link, uint8_t *dpcd_data,
- 
- static void retrieve_link_cap(struct core_link *link)
- {
--	uint8_t dpcd_data[
--			DPCD_ADDRESS_EDP_CONFIG_CAP -
--			DPCD_ADDRESS_DPCD_REV + 1];
-+	uint8_t dpcd_data[DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL - DPCD_ADDRESS_DPCD_REV + 1];
- 
- 	union down_stream_port_count down_strm_port_count;
- 	union edp_configuration_cap edp_config_cap;
-@@ -1688,11 +1701,29 @@ static void retrieve_link_cap(struct core_link *link)
- 	dm_memset(&edp_config_cap, '\0',
- 		sizeof(union edp_configuration_cap));
- 
--	core_link_read_dpcd(link, DPCD_ADDRESS_DPCD_REV,
--			dpcd_data, sizeof(dpcd_data));
--	link->dpcd_caps.dpcd_rev.raw = dpcd_data[
--		DPCD_ADDRESS_DPCD_REV -
--		DPCD_ADDRESS_DPCD_REV];
-+	core_link_read_dpcd(
-+		link,
-+		DPCD_ADDRESS_DPCD_REV,
-+		dpcd_data,
-+		sizeof(dpcd_data));
-+
-+	link->dpcd_caps.dpcd_rev.raw =
-+		dpcd_data[DPCD_ADDRESS_DPCD_REV - DPCD_ADDRESS_DPCD_REV];
-+
-+	{
-+		union training_aux_rd_interval aux_rd_interval;
-+
-+		aux_rd_interval.raw =
-+			dpcd_data[DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL];
-+
-+		if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
-+			core_link_read_dpcd(
-+				link,
-+				DPCD_ADDRESS_DP13_DPCD_REV,
-+				dpcd_data,
-+				sizeof(dpcd_data));
-+		}
-+	}
- 
- 	ds_port.byte = dpcd_data[DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT -
- 				 DPCD_ADDRESS_DPCD_REV];
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index a3e0da9..92d70ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -107,8 +107,6 @@ bool dp_set_hw_training_pattern(
- 	enum hw_dp_training_pattern pattern)
- {
- 	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
--	struct encoder_set_dp_phy_pattern_param pattern_param = {0};
--	struct link_encoder *encoder = link->link_enc;
- 
- 	switch (pattern) {
- 	case HW_DP_TRAINING_PATTERN_1:
-@@ -127,12 +125,7 @@ bool dp_set_hw_training_pattern(
- 		break;
- 	}
- 
--	pattern_param.dp_phy_pattern = test_pattern;
--	pattern_param.custom_pattern = NULL;
--	pattern_param.custom_pattern_size = 0;
--	pattern_param.dp_panel_mode = dp_get_panel_mode(link);
--
--	encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
-+	dp_set_hw_test_pattern(link, test_pattern);
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index deaf506..2e9672b 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -188,6 +188,7 @@ enum dpcd_address {
- 	DPCD_ADDRESS_EDP_GENERAL_CAP2 = 0x0703,
- 
- 	DPCD_ADDRESS_EDP_DISPLAY_CONTROL = 0x0720,
-+	DPCD_ADDRESS_SUPPORTED_LINK_RATES = 0x00010, /* edp 1.4 */
- 	DPCD_ADDRESS_EDP_BACKLIGHT_SET = 0x0721,
- 	DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_MSB = 0x0722,
- 	DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_LSB = 0x0723,
-@@ -232,6 +233,9 @@ enum dpcd_address {
- 	DPCD_ADDRESS_PSR_DBG_REGISTER0 = 0x2009,
- 	DPCD_ADDRESS_PSR_DBG_REGISTER1 = 0x200A,
- 
-+	DPCD_ADDRESS_DP13_DPCD_REV = 0x2200,
-+	DPCD_ADDRESS_DP13_MAX_LINK_RATE = 0x2201,
-+
- 	/* Travis specific addresses */
- 	DPCD_ADDRESS_TRAVIS_SINK_DEV_SEL = 0x5f0,
- 	DPCD_ADDRESS_TRAVIS_SINK_ACCESS_OFFSET	= 0x5f1,
-@@ -242,7 +246,8 @@ enum dpcd_revision {
- 	DPCD_REV_10 = 0x10,
- 	DPCD_REV_11 = 0x11,
- 	DPCD_REV_12 = 0x12,
--	DPCD_REV_13 = 0x13
-+	DPCD_REV_13 = 0x13,
-+	DPCD_REV_14 = 0x14
- };
- 
- enum dp_pwr_state {
-@@ -595,7 +600,7 @@ union audio_test_mode {
- 	uint8_t raw;
- };
- 
--union audio_tes_tpattern_period {
-+union audio_test_pattern_period {
- 	struct {
- 		uint8_t PATTERN_PERIOD:4;
- 		uint8_t RESERVED:4;
-@@ -609,12 +614,16 @@ struct audio_test_pattern_type {
- 
- union dpcd_training_pattern {
- 	struct {
--		uint8_t TRAINING_PATTERN_SET:2;
--		uint8_t LINK_QUAL_PATTERN_SET:2;
-+		uint8_t TRAINING_PATTERN_SET:4;
- 		uint8_t RECOVERED_CLOCK_OUT_EN:1;
- 		uint8_t SCRAMBLING_DISABLE:1;
--		uint8_t RESERVED:2;
--	} bits;
-+		uint8_t SYMBOL_ERROR_COUNT_SEL:2;
-+	} v1_4;
-+	struct {
-+		uint8_t TRAINING_PATTERN_SET:2;
-+		uint8_t LINK_QUAL_PATTERN_SET:2;
-+		uint8_t RESERVED:4;
-+	} v1_3;
- 	uint8_t raw;
- };
- 
-@@ -872,4 +881,12 @@ union psr_capabilities {
- 	uint8_t raw;
- };
- 
-+union training_aux_rd_interval {
-+	struct {
-+		uint8_t TRAINIG_AUX_RD_INTERVAL:7;
-+		uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
- #endif /* __DAL_DPCD_DEFS_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index 2ed01bd..fe65b18 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -291,6 +291,9 @@ struct spread_spectrum_info {
- struct graphics_object_encoder_cap_info {
- 	uint32_t dp_hbr2_cap:1;
- 	uint32_t dp_hbr2_validated:1;
-+	/*
-+	 * TODO: added MST and HDMI 6G capable flags
-+	 */
- 	uint32_t reserved:15;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0781-drm-amd-dal-Create-interface-for-Virtual-HW-programm.patch b/common/recipes-kernel/linux/files/0781-drm-amd-dal-Create-interface-for-Virtual-HW-programm.patch
deleted file mode 100644
index 2d92f2fe..00000000
--- a/common/recipes-kernel/linux/files/0781-drm-amd-dal-Create-interface-for-Virtual-HW-programm.patch
+++ /dev/null
@@ -1,914 +0,0 @@
-From fc9ff27e7e072eaadd0604c99d1f2fe4b78c8dc3 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Mon, 8 Feb 2016 12:02:53 -0500
-Subject: [PATCH 0781/1110] drm/amd/dal: Create interface for Virtual HW
- programming.
-
-These are the data types for Virtual HW Layer of DAL3.
-
-The intended uses are:
-1. Generation pseudocode sequences for HW programming.
-2. Implementation of real HW programming by HW Sequencer of DAL3.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           | 282 +++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 313 ++-------------------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  35 ++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |  11 +-
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |  19 +-
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |   6 +-
- 7 files changed, 358 insertions(+), 312 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-new file mode 100644
-index 0000000..71d6301
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -0,0 +1,282 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_HW_TYPES_H
-+#define DC_HW_TYPES_H
-+
-+/******************************************************************************
-+ * Data types for Virtual HW Layer of DAL3.
-+ * (see DAL3 design documents for HW Layer definition)
-+ *
-+ * The intended uses are:
-+ * 1. Generation pseudocode sequences for HW programming.
-+ * 2. Implementation of real HW programming by HW Sequencer of DAL3.
-+ *
-+ * Note: do *not* add any types which are *not* used for HW programming - this
-+ * will ensure separation of Logic layer from HW layer.
-+ ******************************************************************************/
-+
-+union large_integer {
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	};
-+
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	} u;
-+
-+	int64_t quad_part;
-+};
-+
-+#define PHYSICAL_ADDRESS_LOC union large_integer
-+
-+enum dc_plane_addr_type {
-+	PLN_ADDR_TYPE_GRAPHICS = 0,
-+	PLN_ADDR_TYPE_GRPH_STEREO,
-+	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
-+};
-+
-+struct dc_plane_address {
-+	enum dc_plane_addr_type type;
-+	union {
-+		struct{
-+			PHYSICAL_ADDRESS_LOC addr;
-+		} grph;
-+
-+		/*stereo*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC left_addr;
-+			PHYSICAL_ADDRESS_LOC right_addr;
-+		} grph_stereo;
-+
-+		/*video  progressive*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC chroma_addr;
-+			PHYSICAL_ADDRESS_LOC luma_addr;
-+		} video_progressive;
-+	};
-+};
-+
-+struct rect {
-+	uint32_t x;
-+	uint32_t y;
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+union plane_size {
-+	/* Grph or Video will be selected
-+	 * based on format above:
-+	 * Use Video structure if
-+	 * format >= DalPixelFormat_VideoBegin
-+	 * else use Grph structure
-+	 */
-+	struct {
-+		struct rect surface_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch
-+		 * is 32 pixel aligned.
-+		 */
-+		uint32_t surface_pitch;
-+	} grph;
-+
-+	struct {
-+		struct rect luma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		uint32_t luma_pitch;
-+
-+		struct rect chroma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		uint32_t chroma_pitch;
-+	} video;
-+};
-+
-+/*Displayable pixel format in fb*/
-+enum surface_pixel_format {
-+	SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
-+	/*TOBE REMOVED paletta 256 colors*/
-+	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
-+		SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
-+	/*16 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
-+	/*16 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_RGB565,
-+	/*32 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
-+	/*32 bpp swaped*/
-+	SURFACE_PIXEL_FORMAT_GRPH_BGRA8888,
-+
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
-+	/*swaped*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
-+	/*TOBE REMOVED swaped, XR_BIAS has no differance
-+	 * for pixel layout than previous and we can
-+	 * delete this after discusion*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
-+	/*64 bpp */
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
-+	/*swaped & float*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
-+	/*grow graphics here if necessary */
-+
-+	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
-+		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_YCb,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_YCr,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_CbY,
-+	SURFACE_PIXEL_FORMAT_VIDEO_422_CrY,
-+	/*grow 422/420 video here if necessary */
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 =
-+		SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010,
-+	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102
-+	/*grow 444 video here if necessary */
-+};
-+
-+enum tile_split_values {
-+	DC_DISPLAY_MICRO_TILING = 0x0,
-+	DC_THIN_MICRO_TILING = 0x1,
-+	DC_DEPTH_MICRO_TILING = 0x2,
-+	DC_ROTATED_MICRO_TILING = 0x3,
-+};
-+
-+/* TODO: These values come from hardware spec. We need to readdress this
-+ * if they ever change.
-+ */
-+enum array_mode_values {
-+	DC_ARRAY_UNDEFINED = 0,
-+	DC_ARRAY_1D_TILED_THIN1 = 0x2,
-+	DC_ARRAY_2D_TILED_THIN1 = 0x4,
-+};
-+
-+enum tile_mode_values {
-+	DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
-+	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-+};
-+
-+struct dc_tiling_info {
-+
-+	/* Specifies the number of memory banks for tiling
-+	 *	purposes.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 *	POSSIBLE VALUES: 2,4,8,16
-+	 */
-+	unsigned int num_banks;
-+	/* Specifies the number of tiles in the x direction
-+	 *	to be incorporated into the same bank.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 *	POSSIBLE VALUES: 1,2,4,8
-+	 */
-+	unsigned int bank_width;
-+	/* Specifies the number of tiles in the y direction to
-+	 *	be incorporated into the same bank.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 *	POSSIBLE VALUES: 1,2,4,8
-+	 */
-+	unsigned int bank_height;
-+	/* Specifies the macro tile aspect ratio. Only applies
-+	 * to 2D and 3D tiling modes.
-+	 */
-+	unsigned int tile_aspect;
-+	/* Specifies the number of bytes that will be stored
-+	 *	contiguously for each tile.
-+	 * If the tile data requires more storage than this
-+	 *	amount, it is split into multiple slices.
-+	 * This field must not be larger than
-+	 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-+	 * Only applies to 2D and 3D tiling modes.
-+	 * For color render targets, TILE_SPLIT >= 256B.
-+	 */
-+	enum tile_split_values tile_split;
-+	/* Specifies the addressing within a tile.
-+	 *	0x0 - DISPLAY_MICRO_TILING
-+	 *	0x1 - THIN_MICRO_TILING
-+	 *	0x2 - DEPTH_MICRO_TILING
-+	 *	0x3 - ROTATED_MICRO_TILING
-+	 */
-+	enum tile_mode_values tile_mode;
-+	/* Specifies the number of pipes and how they are
-+	 *	interleaved in the surface.
-+	 * Refer to memory addressing document for complete
-+	 *	details and constraints.
-+	 */
-+	unsigned int pipe_config;
-+	/* Specifies the tiling mode of the surface.
-+	 * THIN tiles use an 8x8x1 tile size.
-+	 * THICK tiles use an 8x8x4 tile size.
-+	 * 2D tiling modes rotate banks for successive Z slices
-+	 * 3D tiling modes rotate pipes and banks for Z slices
-+	 * Refer to memory addressing document for complete
-+	 *	details and constraints.
-+	 */
-+	enum array_mode_values array_mode;
-+};
-+
-+/* Rotation angle */
-+enum dc_rotation_angle {
-+	ROTATION_ANGLE_0 = 0,
-+	ROTATION_ANGLE_90,
-+	ROTATION_ANGLE_180,
-+	ROTATION_ANGLE_270,
-+	ROTATION_ANGLE_COUNT
-+};
-+
-+
-+struct dc_cursor_position {
-+	uint32_t x;
-+	uint32_t y;
-+
-+	uint32_t x_origin;
-+	uint32_t y_origin;
-+
-+	/*
-+	 * This parameter indicates whether HW cursor should be enabled
-+	 */
-+	bool enable;
-+
-+	/*
-+	 * This parameter indicates whether cursor hot spot should be
-+	 * programmed
-+	 */
-+	bool hot_spot_enable;
-+};
-+
-+#endif /* DC_HW_TYPES_H */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 1701953..67e62c3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -29,6 +29,7 @@
- #include "fixed31_32.h"
- #include "irq_types.h"
- #include "dc_dp_types.h"
-+#include "dc_hw_types.h"
- 
- /* forward declarations */
- struct dc;
-@@ -75,54 +76,6 @@ enum surface_color_space {
- 	SURFACE_COLOR_SPACE_XRRGB = 0x0010
- };
- 
--/*Displayable pixel format in fb*/
--enum surface_pixel_format {
--	SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
--	/*TOBE REMOVED paletta 256 colors*/
--	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
--		SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
--	/*16 bpp*/
--	SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
--	/*16 bpp*/
--	SURFACE_PIXEL_FORMAT_GRPH_RGB565,
--	/*32 bpp*/
--	SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
--	/*32 bpp swaped*/
--	SURFACE_PIXEL_FORMAT_GRPH_BGRA8888,
--
--	SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
--	/*swaped*/
--	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
--	/*TOBE REMOVED swaped, XR_BIAS has no differance
--	 * for pixel layout than previous and we can
--	 * delete this after discusion*/
--	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
--	/*64 bpp */
--	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
--	/*swaped & float*/
--	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
--	/*grow graphics here if necessary */
--
--	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
--	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
--		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
--	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_YCb,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_YCr,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_CbY,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_CrY,
--	/*grow 422/420 video here if necessary */
--	SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 =
--		SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102
--	/*grow 444 video here if necessary */
--};
- 
- 
- /* Pixel format */
-@@ -150,19 +103,13 @@ enum pixel_format {
- 	PIXEL_FORMAT_UNKNOWN
- };
- 
--enum plane_stereo_format {
--	PLANE_STEREO_FORMAT_NONE = 0,
--	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
--	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
--	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
--	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
--	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
--	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
-+enum tiling_mode {
-+	TILING_MODE_INVALID,
-+	TILING_MODE_LINEAR,
-+	TILING_MODE_TILED,
-+	TILING_MODE_COUNT
- };
- 
--/* 3D format for view, typically define how L/R eye surface is arranged within
-- * frames
-- */
- enum view_3d_format {
- 	VIEW_3D_FORMAT_NONE = 0,
- 	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
-@@ -172,6 +119,25 @@ enum view_3d_format {
- 	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
- };
- 
-+struct view_stereo_3d_support {
-+	enum view_3d_format format;
-+	struct {
-+		uint32_t CLONE_MODE :1;
-+		uint32_t SCALING :1;
-+		uint32_t SINGLE_FRAME_SW_PACKED :1;
-+	} features;
-+};
-+
-+enum plane_stereo_format {
-+	PLANE_STEREO_FORMAT_NONE = 0,
-+	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
-+	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
-+	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
-+	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
-+	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
-+	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
-+};
-+
- enum dc_pixel_encoding {
- 	PIXEL_ENCODING_UNDEFINED,
- 	PIXEL_ENCODING_RGB,
-@@ -186,21 +152,6 @@ enum dc_pixel_encoding {
-  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-  */
- 
--union large_integer {
--	struct {
--		uint32_t low_part;
--		int32_t high_part;
--	};
--
--	struct {
--		uint32_t low_part;
--		int32_t high_part;
--	} u;
--
--	int64_t quad_part;
--};
--
--#define PHYSICAL_ADDRESS_LOC union large_integer
- 
- enum dc_edid_connector_type {
- 	EDID_CONNECTOR_UNKNOWN = 0,
-@@ -285,13 +236,6 @@ struct scaling_ratios {
- 	struct fixed31_32 vert_c;
- };
- 
--struct rect {
--	uint32_t x;
--	uint32_t y;
--	uint32_t width;
--	uint32_t height;
--};
--
- struct view {
- 	uint32_t width;
- 	uint32_t height;
-@@ -495,6 +439,7 @@ enum scanning_type {
- };
- 
- struct dc_crtc_timing {
-+
- 	uint32_t h_total;
- 	uint32_t h_border_left;
- 	uint32_t h_addressable;
-@@ -528,34 +473,6 @@ struct dc_mode_timing {
- 	struct dc_crtc_timing crtc_timing;
- };
- 
--/* Rotation angle */
--enum dc_rotation_angle {
--	ROTATION_ANGLE_0 = 0,
--	ROTATION_ANGLE_90,
--	ROTATION_ANGLE_180,
--	ROTATION_ANGLE_270,
--	ROTATION_ANGLE_COUNT
--};
--
--struct dc_cursor_position {
--	uint32_t x;
--	uint32_t y;
--
--	uint32_t x_origin;
--	uint32_t y_origin;
--
--	/*
--	 * This parameter indicates whether HW cursor should be enabled
--	 */
--	bool enable;
--
--	/*
--	 * This parameter indicates whether cursor hot spot should be
--	 * programmed
--	 */
--	bool hot_spot_enable;
--};
--
- /* This enum is for programming CURSOR_MODE register field. */
- /* What this register should be programmed to depends on */
- /* OS requested cursor shape flags */
-@@ -600,34 +517,6 @@ struct dc_cursor_attributes {
- 
- };
- 
--
--enum dc_plane_addr_type {
--	PLN_ADDR_TYPE_GRAPHICS = 0,
--	PLN_ADDR_TYPE_GRPH_STEREO,
--	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
--};
--
--struct dc_plane_address {
--	enum dc_plane_addr_type type;
--	union {
--		struct{
--			PHYSICAL_ADDRESS_LOC addr;
--		} grph;
--
--		/*stereo*/
--		struct {
--			PHYSICAL_ADDRESS_LOC left_addr;
--			PHYSICAL_ADDRESS_LOC right_addr;
--		} grph_stereo;
--
--		/*video  progressive*/
--		struct {
--			PHYSICAL_ADDRESS_LOC chroma_addr;
--			PHYSICAL_ADDRESS_LOC luma_addr;
--		} video_progressive;
--	};
--};
--
- enum dc_power_state {
- 	DC_POWER_STATE_ON = 1,
- 	DC_POWER_STATE_STANDBY,
-@@ -772,22 +661,6 @@ enum scaling_transformation {
- 		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
- };
- 
--struct view_stereo_3d_support {
--	enum view_3d_format format;
--	struct {
--		uint32_t CLONE_MODE:1;
--		uint32_t SCALING:1;
--		uint32_t SINGLE_FRAME_SW_PACKED:1;
--	} features;
--};
--
--enum tiling_mode {
--	TILING_MODE_INVALID,
--	TILING_MODE_LINEAR,
--	TILING_MODE_TILED,
--	TILING_MODE_COUNT
--};
--
- struct view_position {
- 	uint32_t x;
- 	uint32_t y;
-@@ -798,138 +671,4 @@ struct render_mode {
- 	enum pixel_format pixel_format;
- };
- 
--struct pixel_format_support {
--	bool INDEX8 :1;
--	bool RGB565 :1;
--	bool ARGB8888 :1;
--	bool ARGB2101010 :1;
--	bool ARGB2101010_XRBIAS :1;
--	bool FP16 :1;
--};
--
--struct stereo_3d_view {
--	enum view_3d_format view_3d_format;
--	union {
--		uint32_t raw;
--		struct /*stereo_3d_view_flags*/
--		{
--			bool SINGLE_FRAME_SW_PACKED :1;
--			bool EXCLUSIVE_3D :1;
--		} bits;
--	} flags;
--};
--
--/* TODO: These values come from hardware spec. We need to readdress this
-- * if they ever change.
-- */
--enum array_mode_values {
--	DC_ARRAY_UNDEFINED = 0,
--	DC_ARRAY_1D_TILED_THIN1 = 0x2,
--	DC_ARRAY_2D_TILED_THIN1 = 0x4,
--};
--
--
--enum tile_mode_values {
--	DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
--	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
--};
--
--enum tile_split_values {
--	DC_DISPLAY_MICRO_TILING = 0x0,
--	DC_THIN_MICRO_TILING = 0x1,
--	DC_DEPTH_MICRO_TILING = 0x2,
--	DC_ROTATED_MICRO_TILING = 0x3,
--};
--
--struct dc_tiling_info {
--
--	/* Specifies the number of memory banks for tiling
--	 *	purposes.
--	 * Only applies to 2D and 3D tiling modes.
--	 *	POSSIBLE VALUES: 2,4,8,16
--	 */
--	unsigned int num_banks;
--	/* Specifies the number of tiles in the x direction
--	 *	to be incorporated into the same bank.
--	 * Only applies to 2D and 3D tiling modes.
--	 *	POSSIBLE VALUES: 1,2,4,8
--	 */
--	unsigned int bank_width;
--	/* Specifies the number of tiles in the y direction to
--	 *	be incorporated into the same bank.
--	 * Only applies to 2D and 3D tiling modes.
--	 *	POSSIBLE VALUES: 1,2,4,8
--	 */
--	unsigned int bank_height;
--	/* Specifies the macro tile aspect ratio. Only applies
--	 * to 2D and 3D tiling modes.
--	 */
--	unsigned int tile_aspect;
--	/* Specifies the number of bytes that will be stored
--	 *	contiguously for each tile.
--	 * If the tile data requires more storage than this
--	 *	amount, it is split into multiple slices.
--	 * This field must not be larger than
--	 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
--	 * Only applies to 2D and 3D tiling modes.
--	 * For color render targets, TILE_SPLIT >= 256B.
--	 */
--	enum tile_split_values tile_split;
--	/* Specifies the addressing within a tile.
--	 *	0x0 - DISPLAY_MICRO_TILING
--	 *	0x1 - THIN_MICRO_TILING
--	 *	0x2 - DEPTH_MICRO_TILING
--	 *	0x3 - ROTATED_MICRO_TILING
--	 */
--	enum tile_mode_values tile_mode;
--	/* Specifies the number of pipes and how they are
--	 *	interleaved in the surface.
--	 * Refer to memory addressing document for complete
--	 *	details and constraints.
--	 */
--	unsigned int pipe_config;
--	/* Specifies the tiling mode of the surface.
--	 * THIN tiles use an 8x8x1 tile size.
--	 * THICK tiles use an 8x8x4 tile size.
--	 * 2D tiling modes rotate banks for successive Z slices
--	 * 3D tiling modes rotate pipes and banks for Z slices
--	 * Refer to memory addressing document for complete
--	 *	details and constraints.
--	 */
--	enum array_mode_values array_mode;
--};
--
--union plane_size {
--	/* Grph or Video will be selected
--	 * based on format above:
--	 * Use Video structure if
--	 * format >= DalPixelFormat_VideoBegin
--	 * else use Grph structure
--	 */
--	struct {
--		struct rect surface_size;
--		/* Graphic surface pitch in pixels.
--		 * In LINEAR_GENERAL mode, pitch
--		 * is 32 pixel aligned.
--		 */
--		uint32_t surface_pitch;
--	} grph;
--
--	struct {
--		struct rect luma_size;
--		/* Graphic surface pitch in pixels.
--		 * In LINEAR_GENERAL mode, pitch is
--		 * 32 pixel aligned.
--		 */
--		uint32_t luma_pitch;
--
--		struct rect chroma_size;
--		/* Graphic surface pitch in pixels.
--		 * In LINEAR_GENERAL mode, pitch is
--		 * 32 pixel aligned.
--		 */
--		uint32_t chroma_pitch;
--	} video;
--};
--
- #endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index cee25d8..bacf88d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -793,7 +793,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	/*TODO: mst support - use total stream count*/
- 	stream->mi->funcs->allocate_mem_input(
- 					stream->mi,
--					&stream->public.timing,
-+					stream->public.timing.h_total,
-+					stream->public.timing.v_total,
-+					stream->public.timing.pix_clk_khz,
- 					context->target_count);
- 
- 	if (timing_changed) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 6d88afe..b718ac1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -717,7 +717,10 @@ void dce110_mem_input_program_display_marks(
- 		stutter);
- }
- 
--static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
-+static uint32_t get_dmif_switch_time_us(
-+	uint32_t h_total,
-+	uint32_t v_total,
-+	uint32_t pix_clk_khz)
- {
- 	uint32_t frame_time;
- 	uint32_t pixels_per_second;
-@@ -728,12 +731,12 @@ static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
- 	/*return double of frame time*/
- 	const uint32_t single_frame_time_multiplier = 2;
- 
--	if (timing == NULL)
-+	if (!h_total || v_total || !pix_clk_khz)
- 		return single_frame_time_multiplier * min_single_frame_time_us;
- 
- 	/*TODO: should we use pixel format normalized pixel clock here?*/
--	pixels_per_second = timing->pix_clk_khz * 1000;
--	pixels_per_frame = timing->h_total * timing->v_total;
-+	pixels_per_second = pix_clk_khz * 1000;
-+	pixels_per_frame = h_total * v_total;
- 
- 	if (!pixels_per_second || !pixels_per_frame) {
- 		/* avoid division by zero */
-@@ -761,12 +764,17 @@ static uint32_t get_dmif_switch_time_us(struct dc_crtc_timing *timing)
- }
- 
- void dce110_allocate_mem_input(
--		struct mem_input *mi,
--		struct dc_crtc_timing *timing,
--		uint32_t paths_num)
-+	struct mem_input *mi,
-+	uint32_t h_total,/* for current stream */
-+	uint32_t v_total,/* for current stream */
-+	uint32_t pix_clk_khz,/* for current stream */
-+	uint32_t total_stream_num)
- {
- 	const uint32_t retry_delay = 10;
--	uint32_t retry_count = get_dmif_switch_time_us(timing) / retry_delay;
-+	uint32_t retry_count = get_dmif_switch_time_us(
-+			h_total,
-+			v_total,
-+			pix_clk_khz) / retry_delay;
- 
- 	struct dce110_mem_input *bm110 = TO_DCE110_MEM_INPUT(mi);
- 	uint32_t addr = bm110->offsets.pipe + mmPIPE0_DMIF_BUFFER_CONTROL;
-@@ -816,10 +824,10 @@ void dce110_allocate_mem_input(
- 				__func__);
- 
- 
--	if (timing->pix_clk_khz != 0) {
-+	if (pix_clk_khz != 0) {
- 		addr = mmDPG_PIPE_ARBITRATION_CONTROL1 + bm110->offsets.dmif;
- 		value = dm_read_reg(mi->ctx, addr);
--		pix_dur = 1000000000ULL / timing->pix_clk_khz;
-+		pix_dur = 1000000000ULL / pix_clk_khz;
- 
- 		set_reg_field_value(
- 			value,
-@@ -843,7 +851,7 @@ void dce110_allocate_mem_input(
- 		addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
- 		value = dm_read_reg(mi->ctx, addr);
- 
--		if (paths_num > 1)
-+		if (total_stream_num > 1)
- 			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
- 		else
- 			set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-@@ -885,7 +893,8 @@ static void deallocate_dmif_buffer_helper(
- }
- 
- void dce110_free_mem_input(
--	struct mem_input *mi, uint32_t paths_num)
-+	struct mem_input *mi,
-+	uint32_t total_stream_num)
- {
- 	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
- 	uint32_t value;
-@@ -911,7 +920,7 @@ void dce110_free_mem_input(
- 	 * Stella Wong proposed this change. */
- 	if (!IS_FPGA_MAXIMUS_DC(mi->ctx->dce_environment)) {
- 		value = dm_read_reg(mi->ctx, mmMC_HUB_RDREQ_DMIF_LIMIT);
--		if (paths_num > 1)
-+		if (total_stream_num > 1)
- 			set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
- 		else
- 			set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index ec83ee1..232d7fb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -78,9 +78,11 @@ void dce110_mem_input_program_display_marks(
-  * pixel duration for pipe
-  */
- void dce110_allocate_mem_input(
--		struct mem_input *mem_input,
--		struct dc_crtc_timing *timing,
--		uint32_t paths_num);
-+	struct mem_input *mem_input,
-+	uint32_t h_total,/* for current stream */
-+	uint32_t v_total,/* for current stream */
-+	uint32_t pix_clk_khz,/* for current stream */
-+	uint32_t total_stream_num);
- 
- /*
-  * dce110_free_mem_input
-@@ -88,7 +90,8 @@ void dce110_allocate_mem_input(
-  * This function will deallocate a dmif buffer from pipe
-  */
- void dce110_free_mem_input(
--	struct mem_input *mem_input, uint32_t paths_num);
-+	struct mem_input *mem_input,
-+	uint32_t total_stream_num);
- 
- /*
-  * dce110_mem_input_program_surface_flip_and_addr
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index cace055..747e5dc 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -35,7 +35,9 @@ struct mem_input {
- };
- 
- struct mem_input_funcs {
--	void (*mem_input_program_safe_display_marks)(struct mem_input *mi);
-+	void (*mem_input_program_safe_display_marks)(
-+		struct mem_input *mi);
-+
- 	void (*mem_input_program_display_marks)(
- 		struct mem_input *mem_input,
- 		struct bw_watermarks nbp,
-@@ -44,16 +46,23 @@ struct mem_input_funcs {
- 		uint32_t h_total,
- 		uint32_t pixel_clk_in_khz,
- 		uint32_t pstate_blackout_duration_ns);
-+
- 	void (*allocate_mem_input)(
--			struct mem_input *mem_input,
--			struct dc_crtc_timing *timing,
--			uint32_t paths_num);
-+		struct mem_input *mem_input,
-+		uint32_t h_total,/* for current target */
-+		uint32_t v_total,/* for current target */
-+		uint32_t pix_clk_khz,/* for current target */
-+		uint32_t total_streams_num);
-+
- 	void (*free_mem_input)(
--		struct mem_input *mem_input, uint32_t paths_num);
-+		struct mem_input *mem_input,
-+		uint32_t paths_num);
-+
- 	bool (*mem_input_program_surface_flip_and_addr)(
- 		struct mem_input *mem_input,
- 		const struct dc_plane_address *address,
- 		bool flip_immediate);
-+
- 	bool (*mem_input_program_surface_config)(
- 		struct mem_input *mem_input,
- 		enum surface_pixel_format format,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index e3fb79c..1e5467c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -123,13 +123,15 @@ enum yyc_quantization_range {
- };
- 
- struct transform_funcs {
--	bool (*transform_power_up)(struct transform *xfm);
-+	bool (*transform_power_up)(
-+		struct transform *xfm);
- 
- 	bool (*transform_set_scaler)(
- 		struct transform *xfm,
- 		const struct scaler_data *data);
- 
--	void (*transform_set_scaler_bypass)(struct transform *xfm);
-+	void (*transform_set_scaler_bypass)(
-+		struct transform *xfm);
- 
- 	bool (*transform_update_viewport)(
- 		struct transform *xfm,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0782-drm-amd-dal-Temporary-disable-PLL-sharing-for-DCE-10.patch b/common/recipes-kernel/linux/files/0782-drm-amd-dal-Temporary-disable-PLL-sharing-for-DCE-10.patch
deleted file mode 100644
index e140467a..00000000
--- a/common/recipes-kernel/linux/files/0782-drm-amd-dal-Temporary-disable-PLL-sharing-for-DCE-10.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 0a4fa31afa57a5ed03f3574771e941ba63d30c79 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 9 Feb 2016 11:58:59 -0500
-Subject: [PATCH 0782/1110] drm/amd/dal: Temporary disable PLL sharing for DCE
- 10.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index eea4eec..ec6db8d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -103,6 +103,16 @@ static bool is_sharable_clk_src(
- 	const struct core_stream *stream)
- {
- 	enum clock_source_id id = stream_with_clk_src->clock_source->id;
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+	enum dce_version dce_ver = dal_adapter_service_get_dce_version(
-+			stream->sink->link->adapter_srv);
-+
-+	/* Currently no clocks are shared for DCE 10 until VBIOS behaviour
-+	 * is verified for this use case
-+	 */
-+	if (dce_ver == DCE_VERSION_10_0)
-+		return false;
-+#endif
- 
- 	if (stream_with_clk_src->clock_source == NULL)
- 		return false;
-@@ -110,10 +120,6 @@ static bool is_sharable_clk_src(
- 	if (id == CLOCK_SOURCE_ID_EXTERNAL)
- 		return false;
- 
--	/* Sharing dual link is not working */
--	if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK ||
--			stream_with_clk_src->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
--			return false;
- 
- 	if(!is_same_timing(
- 		&stream_with_clk_src->public.timing, &stream->public.timing))
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0783-drm-amd-dal-Add-set_blender_mode-handling-for-underl.patch b/common/recipes-kernel/linux/files/0783-drm-amd-dal-Add-set_blender_mode-handling-for-underl.patch
deleted file mode 100644
index 0bf731a4..00000000
--- a/common/recipes-kernel/linux/files/0783-drm-amd-dal-Add-set_blender_mode-handling-for-underl.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 3a72181cdcda5e7219cf6d0a4ef5f588f3848ed5 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 8 Feb 2016 14:36:05 -0500
-Subject: [PATCH 0783/1110] drm/amd/dal: Add set_blender_mode handling for
- underlay pipe
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 44 ++++++++++++++++------
- 1 file changed, 32 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index bacf88d..754e81d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -351,7 +351,7 @@ static void dce110_set_blender_mode(
- 	uint32_t mode)
- {
- 	uint32_t value;
--	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-+	uint32_t addr = 0;
- 	uint32_t blnd_mode;
- 	uint32_t feedthrough = 0;
- 
-@@ -371,19 +371,39 @@ static void dce110_set_blender_mode(
- 		break;
- 	}
- 
--	value = dm_read_reg(ctx, addr);
-+	if (controller_id == CONTROLLER_ID_UNDERLAY0) {
-+		addr = mmBLNDV_CONTROL;
-+		value = dm_read_reg(ctx, addr);
- 
--	set_reg_field_value(
--		value,
--		feedthrough,
--		BLND_CONTROL,
--		BLND_FEEDTHROUGH_EN);
-+			set_reg_field_value(
-+				value,
-+				feedthrough,
-+				BLNDV_CONTROL,
-+				BLND_FEEDTHROUGH_EN);
- 
--	set_reg_field_value(
--		value,
--		blnd_mode,
--		BLND_CONTROL,
--		BLND_MODE);
-+			set_reg_field_value(
-+				value,
-+				blnd_mode,
-+				BLNDV_CONTROL,
-+				BLND_MODE);
-+
-+
-+	} else {
-+		addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			feedthrough,
-+			BLND_CONTROL,
-+			BLND_FEEDTHROUGH_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			blnd_mode,
-+			BLND_CONTROL,
-+			BLND_MODE);
-+	}
- 
- 	dm_write_reg(ctx, addr, value);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0784-drm-amd-dal-Refactor-opp-gamma-related.patch b/common/recipes-kernel/linux/files/0784-drm-amd-dal-Refactor-opp-gamma-related.patch
deleted file mode 100644
index 7de664f1..00000000
--- a/common/recipes-kernel/linux/files/0784-drm-amd-dal-Refactor-opp-gamma-related.patch
+++ /dev/null
@@ -1,5401 +0,0 @@
-From f250ee01f34b61d29f2e8ffd841555fe716f1fb8 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Thu, 4 Feb 2016 10:42:38 -0500
-Subject: [PATCH 0784/1110] drm/amd/dal: Refactor opp gamma related.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |   10 +-
- drivers/gpu/drm/amd/dal/dc/calcs/Makefile          |    2 +-
- drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c     | 1342 +++++++++++++
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |   80 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |   77 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   43 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   73 -
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |   98 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h    |    1 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     |    3 -
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     |   23 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   |  639 +------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  196 --
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |   13 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 2019 +-------------------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h   |   58 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |    9 +
- drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h       |   31 +
- drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h       |   48 -
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |    6 +-
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |   33 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               |   17 +-
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  |    1 -
- .../gpu/drm/amd/dal/include/video_gamma_types.h    |    1 -
- 24 files changed, 1790 insertions(+), 3033 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 3f80880..2cb445d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -499,16 +499,20 @@ static void fill_gamma_from_crtc(
- 	struct dc_surface *dc_surface)
- {
- 	int i;
--	struct gamma_ramp *gamma;
-+	struct dc_gamma *gamma;
- 	uint16_t *red, *green, *blue;
- 	int end = (crtc->gamma_size > NUM_OF_RAW_GAMMA_RAMP_RGB_256) ?
- 			NUM_OF_RAW_GAMMA_RAMP_RGB_256 : crtc->gamma_size;
-+	struct amdgpu_device *adev = crtc->dev->dev_private;
- 
- 	red = crtc->gamma_store;
- 	green = red + crtc->gamma_size;
- 	blue = green + crtc->gamma_size;
- 
--	gamma = &dc_surface->gamma_correction;
-+	gamma = dc_create_gamma(adev->dm.dc);
-+
-+	if (gamma == NULL)
-+		return;
- 
- 	for (i = 0; i < end; i++) {
- 		gamma->gamma_ramp_rgb256x3x16.red[i] =
-@@ -521,6 +525,8 @@ static void fill_gamma_from_crtc(
- 
- 	gamma->type = GAMMA_RAMP_RBG256X3X16;
- 	gamma->size = sizeof(gamma->gamma_ramp_rgb256x3x16);
-+
-+	dc_surface->gamma_correction = gamma;
- }
- 
- static void fill_plane_attributes(
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/Makefile b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
-index 7f1916b..9ac4ad1 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
-@@ -3,7 +3,7 @@
- # It calculates Bandwidth and Watermarks values for HW programming
- #
- 
--BW_CALCS = bandwidth_calcs.o bw_fixed.o scaler_filter.o
-+BW_CALCS = bandwidth_calcs.o bw_fixed.o scaler_filter.o gamma_calcs.o
- 
- AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-new file mode 100644
-index 0000000..e3a41b3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-@@ -0,0 +1,1342 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "gamma_calcs.h"
-+#include "core_types.h"
-+
-+struct curve_config {
-+	uint32_t offset;
-+	int8_t segments[16];
-+	int8_t begin;
-+};
-+
-+static bool build_custom_float(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	bool *negative,
-+	uint32_t *mantissa,
-+	uint32_t *exponenta)
-+{
-+	uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
-+
-+	const struct fixed31_32 mantissa_constant_plus_max_fraction =
-+		dal_fixed31_32_from_fraction(
-+			(1LL << (format->mantissa_bits + 1)) - 1,
-+			1LL << format->mantissa_bits);
-+
-+	struct fixed31_32 mantiss;
-+
-+	if (dal_fixed31_32_eq(
-+		value,
-+		dal_fixed31_32_zero)) {
-+		*negative = false;
-+		*mantissa = 0;
-+		*exponenta = 0;
-+		return true;
-+	}
-+
-+	if (dal_fixed31_32_lt(
-+		value,
-+		dal_fixed31_32_zero)) {
-+		*negative = format->sign;
-+		value = dal_fixed31_32_neg(value);
-+	} else {
-+		*negative = false;
-+	}
-+
-+	if (dal_fixed31_32_lt(
-+		value,
-+		dal_fixed31_32_one)) {
-+		uint32_t i = 1;
-+
-+		do {
-+			value = dal_fixed31_32_shl(value, 1);
-+			++i;
-+		} while (dal_fixed31_32_lt(
-+			value,
-+			dal_fixed31_32_one));
-+
-+		--i;
-+
-+		if (exp_offset <= i) {
-+			*mantissa = 0;
-+			*exponenta = 0;
-+			return true;
-+		}
-+
-+		*exponenta = exp_offset - i;
-+	} else if (dal_fixed31_32_le(
-+		mantissa_constant_plus_max_fraction,
-+		value)) {
-+		uint32_t i = 1;
-+
-+		do {
-+			value = dal_fixed31_32_shr(value, 1);
-+			++i;
-+		} while (dal_fixed31_32_lt(
-+			mantissa_constant_plus_max_fraction,
-+			value));
-+
-+		*exponenta = exp_offset + i - 1;
-+	} else {
-+		*exponenta = exp_offset;
-+	}
-+
-+	mantiss = dal_fixed31_32_sub(
-+		value,
-+		dal_fixed31_32_one);
-+
-+	if (dal_fixed31_32_lt(
-+			mantiss,
-+			dal_fixed31_32_zero) ||
-+		dal_fixed31_32_lt(
-+			dal_fixed31_32_one,
-+			mantiss))
-+		mantiss = dal_fixed31_32_zero;
-+	else
-+		mantiss = dal_fixed31_32_shl(
-+			mantiss,
-+			format->mantissa_bits);
-+
-+	*mantissa = dal_fixed31_32_floor(mantiss);
-+
-+	return true;
-+}
-+
-+static bool setup_custom_float(
-+	const struct custom_float_format *format,
-+	bool negative,
-+	uint32_t mantissa,
-+	uint32_t exponenta,
-+	uint32_t *result)
-+{
-+	uint32_t i = 0;
-+	uint32_t j = 0;
-+
-+	uint32_t value = 0;
-+
-+	/* verification code:
-+	 * once calculation is ok we can remove it
-+	 */
-+
-+	const uint32_t mantissa_mask =
-+		(1 << (format->mantissa_bits + 1)) - 1;
-+
-+	const uint32_t exponenta_mask =
-+		(1 << (format->exponenta_bits + 1)) - 1;
-+
-+	if (mantissa & ~mantissa_mask) {
-+		BREAK_TO_DEBUGGER();
-+		mantissa = mantissa_mask;
-+	}
-+
-+	if (exponenta & ~exponenta_mask) {
-+		BREAK_TO_DEBUGGER();
-+		exponenta = exponenta_mask;
-+	}
-+
-+	/* end of verification code */
-+
-+	while (i < format->mantissa_bits) {
-+		uint32_t mask = 1 << i;
-+
-+		if (mantissa & mask)
-+			value |= mask;
-+
-+		++i;
-+	}
-+
-+	while (j < format->exponenta_bits) {
-+		uint32_t mask = 1 << j;
-+
-+		if (exponenta & mask)
-+			value |= mask << i;
-+
-+		++j;
-+	}
-+
-+	if (negative && format->sign)
-+		value |= 1 << (i + j);
-+
-+	*result = value;
-+
-+	return true;
-+}
-+
-+
-+static bool convert_to_custom_float_format_ex(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	struct custom_float_value *result)
-+{
-+	return build_custom_float(
-+		value, format,
-+		&result->negative, &result->mantissa, &result->exponenta) &&
-+	setup_custom_float(
-+		format, result->negative, result->mantissa, result->exponenta,
-+		&result->value);
-+}
-+
-+static bool round_custom_float_6_12(
-+	struct hw_x_point *x)
-+{
-+	struct custom_float_format fmt;
-+
-+	struct custom_float_value value;
-+
-+	fmt.exponenta_bits = 6;
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	if (!convert_to_custom_float_format_ex(
-+		x->x, &fmt, &value))
-+		return false;
-+
-+	x->adjusted_x = x->x;
-+
-+	if (value.mantissa) {
-+		BREAK_TO_DEBUGGER();
-+
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool build_hw_curve_configuration(
-+	const struct curve_config *curve_config,
-+	struct gamma_curve *gamma_curve,
-+	struct curve_points *curve_points,
-+	struct hw_x_point *points,
-+	uint32_t *number_of_points)
-+{
-+	const int8_t max_regions_number = ARRAY_SIZE(curve_config->segments);
-+
-+	int8_t i;
-+
-+	uint8_t segments_calculation[8] = { 0 };
-+
-+	struct fixed31_32 region1 = dal_fixed31_32_zero;
-+	struct fixed31_32 region2;
-+	struct fixed31_32 increment;
-+
-+	uint32_t index = 0;
-+	uint32_t segments = 0;
-+	uint32_t max_number;
-+
-+	bool result = false;
-+
-+	if (!number_of_points) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	max_number = *number_of_points;
-+
-+	i = 0;
-+
-+	while (i != max_regions_number) {
-+		gamma_curve[i].offset = 0;
-+		gamma_curve[i].segments_num = 0;
-+
-+		++i;
-+	}
-+
-+	i = 0;
-+
-+	while (i != max_regions_number) {
-+		/* number should go in uninterruptible sequence */
-+		if (curve_config->segments[i] == -1)
-+			break;
-+
-+		ASSERT(curve_config->segments[i] >= 0);
-+
-+		segments += (1 << curve_config->segments[i]);
-+
-+		++i;
-+	}
-+
-+	if (segments > max_number) {
-+		BREAK_TO_DEBUGGER();
-+	} else {
-+		int32_t divisor;
-+		uint32_t offset = 0;
-+		int8_t begin = curve_config->begin;
-+		int32_t region_number = 0;
-+
-+		i = begin;
-+
-+		while ((index < max_number) &&
-+			(region_number < max_regions_number) &&
-+			(i <= 1)) {
-+			int32_t j = 0;
-+
-+			segments = curve_config->segments[region_number];
-+			divisor = 1 << segments;
-+
-+			if (segments == -1) {
-+				if (i > 0) {
-+					region1 = dal_fixed31_32_shl(
-+						dal_fixed31_32_one,
-+						i - 1);
-+					region2 = dal_fixed31_32_shl(
-+						dal_fixed31_32_one,
-+						i);
-+				} else {
-+					region1 = dal_fixed31_32_shr(
-+						dal_fixed31_32_one,
-+						-(i - 1));
-+					region2 = dal_fixed31_32_shr(
-+						dal_fixed31_32_one,
-+						-i);
-+				}
-+
-+				break;
-+			}
-+
-+			if (i > -1) {
-+				region1 = dal_fixed31_32_shl(
-+					dal_fixed31_32_one,
-+					i);
-+				region2 = dal_fixed31_32_shl(
-+					dal_fixed31_32_one,
-+					i + 1);
-+			} else {
-+				region1 = dal_fixed31_32_shr(
-+					dal_fixed31_32_one,
-+					-i);
-+				region2 = dal_fixed31_32_shr(
-+					dal_fixed31_32_one,
-+					-(i + 1));
-+			}
-+
-+			gamma_curve[region_number].offset = offset;
-+			gamma_curve[region_number].segments_num = segments;
-+
-+			offset += divisor;
-+
-+			++segments_calculation[segments];
-+
-+			increment = dal_fixed31_32_div_int(
-+				dal_fixed31_32_sub(
-+					region2,
-+					region1),
-+				divisor);
-+
-+			points[index].x = region1;
-+
-+			round_custom_float_6_12(points + index);
-+
-+			++index;
-+			++region_number;
-+
-+			while ((index < max_number) && (j < divisor - 1)) {
-+				region1 = dal_fixed31_32_add(
-+					region1,
-+					increment);
-+
-+				points[index].x = region1;
-+				points[index].adjusted_x = region1;
-+
-+				++index;
-+				++j;
-+			}
-+
-+			++i;
-+		}
-+
-+		points[index].x = region1;
-+
-+		round_custom_float_6_12(points + index);
-+
-+		*number_of_points = index;
-+
-+		result = true;
-+	}
-+
-+	curve_points[0].x = points[0].adjusted_x;
-+	curve_points[0].offset = dal_fixed31_32_zero;
-+
-+	curve_points[1].x = points[index - 1].adjusted_x;
-+	curve_points[1].offset = dal_fixed31_32_zero;
-+
-+	curve_points[2].x = points[index].adjusted_x;
-+	curve_points[2].offset = dal_fixed31_32_zero;
-+
-+	return result;
-+}
-+
-+static bool setup_distribution_points(
-+		struct gamma_curve *arr_curve_points,
-+		struct curve_points *arr_points,
-+		uint32_t *hw_points_num,
-+		struct hw_x_point *coordinates_x)
-+{
-+	struct curve_config cfg;
-+
-+	cfg.offset = 0;
-+	cfg.segments[0] = 3;
-+	cfg.segments[1] = 4;
-+	cfg.segments[2] = 4;
-+	cfg.segments[3] = 4;
-+	cfg.segments[4] = 4;
-+	cfg.segments[5] = 4;
-+	cfg.segments[6] = 4;
-+	cfg.segments[7] = 4;
-+	cfg.segments[8] = 5;
-+	cfg.segments[9] = 5;
-+	cfg.segments[10] = 0;
-+	cfg.segments[11] = -1;
-+	cfg.segments[12] = -1;
-+	cfg.segments[13] = -1;
-+	cfg.segments[14] = -1;
-+	cfg.segments[15] = -1;
-+
-+	cfg.begin = -10;
-+
-+	if (!build_hw_curve_configuration(
-+		&cfg, arr_curve_points,
-+		arr_points,
-+		coordinates_x, hw_points_num)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+	return true;
-+}
-+
-+struct dividers {
-+	struct fixed31_32 divider1;
-+	struct fixed31_32 divider2;
-+	struct fixed31_32 divider3;
-+};
-+
-+
-+static void build_regamma_coefficients(struct gamma_coefficients *coefficients)
-+{
-+	/* sRGB should apply 2.4 */
-+	static const int32_t numerator01[3] = { 31308, 31308, 31308 };
-+	static const int32_t numerator02[3] = { 12920, 12920, 12920 };
-+	static const int32_t numerator03[3] = { 55, 55, 55 };
-+	static const int32_t numerator04[3] = { 55, 55, 55 };
-+	static const int32_t numerator05[3] = { 2400, 2400, 2400 };
-+
-+	const int32_t *numerator1;
-+	const int32_t *numerator2;
-+	const int32_t *numerator3;
-+	const int32_t *numerator4;
-+	const int32_t *numerator5;
-+
-+	uint32_t i = 0;
-+
-+	numerator1 = numerator01;
-+	numerator2 = numerator02;
-+	numerator3 = numerator03;
-+	numerator4 = numerator04;
-+	numerator5 = numerator05;
-+
-+	do {
-+		coefficients->a0[i] = dal_fixed31_32_from_fraction(
-+			numerator1[i], 10000000);
-+		coefficients->a1[i] = dal_fixed31_32_from_fraction(
-+			numerator2[i], 1000);
-+		coefficients->a2[i] = dal_fixed31_32_from_fraction(
-+			numerator3[i], 1000);
-+		coefficients->a3[i] = dal_fixed31_32_from_fraction(
-+			numerator4[i], 1000);
-+		coefficients->user_gamma[i] = dal_fixed31_32_from_fraction(
-+			numerator5[i], 1000);
-+
-+		++i;
-+	} while (i != ARRAY_SIZE(coefficients->a0));
-+}
-+
-+static struct fixed31_32 translate_from_linear_space(
-+	struct fixed31_32 arg,
-+	struct fixed31_32 a0,
-+	struct fixed31_32 a1,
-+	struct fixed31_32 a2,
-+	struct fixed31_32 a3,
-+	struct fixed31_32 gamma)
-+{
-+	const struct fixed31_32 one = dal_fixed31_32_from_int(1);
-+
-+	if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0)))
-+		return dal_fixed31_32_sub(
-+			a2,
-+			dal_fixed31_32_mul(
-+				dal_fixed31_32_add(
-+					one,
-+					a3),
-+				dal_fixed31_32_pow(
-+					dal_fixed31_32_neg(arg),
-+					dal_fixed31_32_recip(gamma))));
-+	else if (dal_fixed31_32_le(a0, arg))
-+		return dal_fixed31_32_sub(
-+			dal_fixed31_32_mul(
-+				dal_fixed31_32_add(
-+					one,
-+					a3),
-+				dal_fixed31_32_pow(
-+					arg,
-+					dal_fixed31_32_recip(gamma))),
-+			a2);
-+	else
-+		return dal_fixed31_32_mul(
-+			arg,
-+			a1);
-+}
-+
-+static inline struct fixed31_32 translate_from_linear_space_ex(
-+	struct fixed31_32 arg,
-+	struct gamma_coefficients *coeff,
-+	uint32_t color_index)
-+{
-+	return translate_from_linear_space(
-+		arg,
-+		coeff->a0[color_index],
-+		coeff->a1[color_index],
-+		coeff->a2[color_index],
-+		coeff->a3[color_index],
-+		coeff->user_gamma[color_index]);
-+}
-+
-+static bool find_software_points(
-+	const struct gamma_pixel *axis_x_256,
-+	struct fixed31_32 hw_point,
-+	enum channel_name channel,
-+	uint32_t *index_to_start,
-+	uint32_t *index_left,
-+	uint32_t *index_right,
-+	enum hw_point_position *pos)
-+{
-+	const uint32_t max_number = RGB_256X3X16 + 3;
-+
-+	struct fixed31_32 left, right;
-+
-+	uint32_t i = *index_to_start;
-+
-+	while (i < max_number) {
-+		if (channel == CHANNEL_NAME_RED) {
-+			left = axis_x_256[i].r;
-+
-+			if (i < max_number - 1)
-+				right = axis_x_256[i + 1].r;
-+			else
-+				right = axis_x_256[max_number - 1].r;
-+		} else if (channel == CHANNEL_NAME_GREEN) {
-+			left = axis_x_256[i].g;
-+
-+			if (i < max_number - 1)
-+				right = axis_x_256[i + 1].g;
-+			else
-+				right = axis_x_256[max_number - 1].g;
-+		} else {
-+			left = axis_x_256[i].b;
-+
-+			if (i < max_number - 1)
-+				right = axis_x_256[i + 1].b;
-+			else
-+				right = axis_x_256[max_number - 1].b;
-+		}
-+
-+		if (dal_fixed31_32_le(left, hw_point) &&
-+			dal_fixed31_32_le(hw_point, right)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+
-+			if (i < max_number - 1)
-+				*index_right = i + 1;
-+			else
-+				*index_right = max_number - 1;
-+
-+			*pos = HW_POINT_POSITION_MIDDLE;
-+
-+			return true;
-+		} else if ((i == *index_to_start) &&
-+			dal_fixed31_32_le(hw_point, left)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+			*index_right = i;
-+
-+			*pos = HW_POINT_POSITION_LEFT;
-+
-+			return true;
-+		} else if ((i == max_number - 1) &&
-+			dal_fixed31_32_le(right, hw_point)) {
-+			*index_to_start = i;
-+			*index_left = i;
-+			*index_right = i;
-+
-+			*pos = HW_POINT_POSITION_RIGHT;
-+
-+			return true;
-+		}
-+
-+		++i;
-+	}
-+
-+	return false;
-+}
-+
-+static bool build_custom_gamma_mapping_coefficients_worker(
-+	struct pixel_gamma_point *coeff,
-+	const struct hw_x_point *coordinates_x,
-+	const struct gamma_pixel *axis_x_256,
-+	enum channel_name channel,
-+	uint32_t number_of_points,
-+	enum surface_pixel_format pixel_format)
-+{
-+	uint32_t i = 0;
-+
-+	while (i <= number_of_points) {
-+		struct fixed31_32 coord_x;
-+
-+		uint32_t index_to_start = 0;
-+		uint32_t index_left = 0;
-+		uint32_t index_right = 0;
-+
-+		enum hw_point_position hw_pos;
-+
-+		struct gamma_point *point;
-+
-+		struct fixed31_32 left_pos;
-+		struct fixed31_32 right_pos;
-+
-+		/*
-+		 * TODO: confirm enum in surface_pixel_format
-+		 * if (pixel_format == PIXEL_FORMAT_FP16)
-+		 *coord_x = coordinates_x[i].adjusted_x;
-+		 *else
-+		 */
-+		if (channel == CHANNEL_NAME_RED)
-+			coord_x = coordinates_x[i].regamma_y_red;
-+		else if (channel == CHANNEL_NAME_GREEN)
-+			coord_x = coordinates_x[i].regamma_y_green;
-+		else
-+			coord_x = coordinates_x[i].regamma_y_blue;
-+
-+		if (!find_software_points(
-+			axis_x_256, coord_x, channel,
-+			&index_to_start, &index_left, &index_right, &hw_pos)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (index_left >= RGB_256X3X16 + 3) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (index_right >= RGB_256X3X16 + 3) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (channel == CHANNEL_NAME_RED) {
-+			point = &coeff[i].r;
-+
-+			left_pos = axis_x_256[index_left].r;
-+			right_pos = axis_x_256[index_right].r;
-+		} else if (channel == CHANNEL_NAME_GREEN) {
-+			point = &coeff[i].g;
-+
-+			left_pos = axis_x_256[index_left].g;
-+			right_pos = axis_x_256[index_right].g;
-+		} else {
-+			point = &coeff[i].b;
-+
-+			left_pos = axis_x_256[index_left].b;
-+			right_pos = axis_x_256[index_right].b;
-+		}
-+
-+		if (hw_pos == HW_POINT_POSITION_MIDDLE)
-+			point->coeff = dal_fixed31_32_div(
-+				dal_fixed31_32_sub(
-+					coord_x,
-+					left_pos),
-+				dal_fixed31_32_sub(
-+					right_pos,
-+					left_pos));
-+		else if (hw_pos == HW_POINT_POSITION_LEFT)
-+			point->coeff = dal_fixed31_32_zero;
-+		else if (hw_pos == HW_POINT_POSITION_RIGHT)
-+			point->coeff = dal_fixed31_32_from_int(2);
-+		else {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		point->left_index = index_left;
-+		point->right_index = index_right;
-+		point->pos = hw_pos;
-+
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static inline bool build_oem_custom_gamma_mapping_coefficients(
-+	struct pixel_gamma_point *coeff128_oem,
-+	const struct hw_x_point *coordinates_x,
-+	const struct gamma_pixel *axis_x_256,
-+	uint32_t number_of_points,
-+	enum surface_pixel_format pixel_format)
-+{
-+	int i;
-+
-+	for (i = 0; i < 3; i++) {
-+		if (!build_custom_gamma_mapping_coefficients_worker(
-+				coeff128_oem, coordinates_x, axis_x_256, i,
-+				number_of_points, pixel_format))
-+			return false;
-+	}
-+	return true;
-+}
-+
-+static struct fixed31_32 calculate_mapped_value(
-+	struct pwl_float_data *rgb,
-+	const struct pixel_gamma_point *coeff,
-+	enum channel_name channel,
-+	uint32_t max_index)
-+{
-+	const struct gamma_point *point;
-+
-+	struct fixed31_32 result;
-+
-+	if (channel == CHANNEL_NAME_RED)
-+		point = &coeff->r;
-+	else if (channel == CHANNEL_NAME_GREEN)
-+		point = &coeff->g;
-+	else
-+		point = &coeff->b;
-+
-+	if ((point->left_index < 0) || (point->left_index > max_index)) {
-+		BREAK_TO_DEBUGGER();
-+		return dal_fixed31_32_zero;
-+	}
-+
-+	if ((point->right_index < 0) || (point->right_index > max_index)) {
-+		BREAK_TO_DEBUGGER();
-+		return dal_fixed31_32_zero;
-+	}
-+
-+	if (point->pos == HW_POINT_POSITION_MIDDLE)
-+		if (channel == CHANNEL_NAME_RED)
-+			result = dal_fixed31_32_add(
-+				dal_fixed31_32_mul(
-+					point->coeff,
-+					dal_fixed31_32_sub(
-+						rgb[point->right_index].r,
-+						rgb[point->left_index].r)),
-+				rgb[point->left_index].r);
-+		else if (channel == CHANNEL_NAME_GREEN)
-+			result = dal_fixed31_32_add(
-+				dal_fixed31_32_mul(
-+					point->coeff,
-+					dal_fixed31_32_sub(
-+						rgb[point->right_index].g,
-+						rgb[point->left_index].g)),
-+				rgb[point->left_index].g);
-+		else
-+			result = dal_fixed31_32_add(
-+				dal_fixed31_32_mul(
-+					point->coeff,
-+					dal_fixed31_32_sub(
-+						rgb[point->right_index].b,
-+						rgb[point->left_index].b)),
-+				rgb[point->left_index].b);
-+	else if (point->pos == HW_POINT_POSITION_LEFT) {
-+		BREAK_TO_DEBUGGER();
-+		result = dal_fixed31_32_zero;
-+	} else {
-+		BREAK_TO_DEBUGGER();
-+		result = dal_fixed31_32_one;
-+	}
-+
-+	return result;
-+}
-+
-+static inline struct fixed31_32 calculate_oem_mapped_value(
-+	struct pwl_float_data *rgb_oem,
-+	const struct pixel_gamma_point *coeff,
-+	uint32_t index,
-+	enum channel_name channel,
-+	uint32_t max_index)
-+{
-+	return calculate_mapped_value(
-+			rgb_oem,
-+			coeff + index,
-+			channel,
-+			max_index);
-+}
-+
-+static void build_regamma_curve(struct pwl_float_data_ex *rgb_regamma,
-+		struct pwl_float_data *rgb_oem,
-+		struct pixel_gamma_point *coeff128_oem,
-+		const struct core_gamma *ramp,
-+		const struct core_surface *surface,
-+		uint32_t hw_points_num,
-+		const struct hw_x_point *coordinate_x,
-+		const struct gamma_pixel *axis_x,
-+		struct dividers dividers)
-+{
-+	uint32_t i;
-+
-+	struct gamma_coefficients coeff;
-+	struct pwl_float_data_ex *rgb = rgb_regamma;
-+	const struct hw_x_point *coord_x = coordinate_x;
-+
-+	build_regamma_coefficients(&coeff);
-+
-+	/* Use opp110->regamma.coordinates_x to retrieve
-+	 * coordinates chosen base on given user curve (future task).
-+	 * The x values are exponentially distributed and currently
-+	 * it is hard-coded, the user curve shape is ignored.
-+	 * The future task is to recalculate opp110-
-+	 * regamma.coordinates_x based on input/user curve,
-+	 * translation from 256/1025 to 128 pwl points.
-+	 */
-+
-+	i = 0;
-+
-+	while (i != hw_points_num + 1) {
-+		rgb->r = translate_from_linear_space_ex(
-+			coord_x->adjusted_x, &coeff, 0);
-+		rgb->g = translate_from_linear_space_ex(
-+			coord_x->adjusted_x, &coeff, 1);
-+		rgb->b = translate_from_linear_space_ex(
-+			coord_x->adjusted_x, &coeff, 2);
-+
-+		++coord_x;
-+		++rgb;
-+		++i;
-+	}
-+}
-+
-+static bool scale_gamma(struct pwl_float_data *pwl_rgb,
-+		const struct core_gamma *ramp,
-+		struct dividers dividers)
-+{
-+	const struct dc_gamma_ramp_rgb256x3x16 *gamma;
-+	const uint16_t max_driver = 0xFFFF;
-+	const uint16_t max_os = 0xFF00;
-+	uint16_t scaler = max_os;
-+	uint32_t i;
-+	struct pwl_float_data *rgb = pwl_rgb;
-+	struct pwl_float_data *rgb_last = rgb + RGB_256X3X16 - 1;
-+
-+	if (ramp->public.type == GAMMA_RAMP_RBG256X3X16)
-+		gamma = &ramp->public.gamma_ramp_rgb256x3x16;
-+	else
-+		return false; /* invalid option */
-+
-+	i = 0;
-+
-+	do {
-+		if ((gamma->red[i] > max_os) ||
-+			(gamma->green[i] > max_os) ||
-+			(gamma->blue[i] > max_os)) {
-+			scaler = max_driver;
-+			break;
-+		}
-+		++i;
-+	} while (i != RGB_256X3X16);
-+
-+	i = 0;
-+
-+	do {
-+		rgb->r = dal_fixed31_32_from_fraction(
-+			gamma->red[i], scaler);
-+		rgb->g = dal_fixed31_32_from_fraction(
-+			gamma->green[i], scaler);
-+		rgb->b = dal_fixed31_32_from_fraction(
-+			gamma->blue[i], scaler);
-+
-+		++rgb;
-+		++i;
-+	} while (i != RGB_256X3X16);
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			dividers.divider1);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			dividers.divider1);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			dividers.divider1);
-+
-+	++rgb;
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			dividers.divider2);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			dividers.divider2);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			dividers.divider2);
-+
-+	++rgb;
-+
-+	rgb->r = dal_fixed31_32_mul(rgb_last->r,
-+			dividers.divider3);
-+	rgb->g = dal_fixed31_32_mul(rgb_last->g,
-+			dividers.divider3);
-+	rgb->b = dal_fixed31_32_mul(rgb_last->b,
-+			dividers.divider3);
-+
-+	return true;
-+}
-+
-+static void build_evenly_distributed_points(
-+	struct gamma_pixel *points,
-+	uint32_t numberof_points,
-+	struct fixed31_32 max_value,
-+	struct dividers dividers)
-+{
-+	struct gamma_pixel *p = points;
-+	struct gamma_pixel *p_last = p + numberof_points - 1;
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		struct fixed31_32 value = dal_fixed31_32_div_int(
-+			dal_fixed31_32_mul_int(max_value, i),
-+			numberof_points - 1);
-+
-+		p->r = value;
-+		p->g = value;
-+		p->b = value;
-+
-+		++p;
-+		++i;
-+	} while (i != numberof_points);
-+
-+	p->r = dal_fixed31_32_div(p_last->r, dividers.divider1);
-+	p->g = dal_fixed31_32_div(p_last->g, dividers.divider1);
-+	p->b = dal_fixed31_32_div(p_last->b, dividers.divider1);
-+
-+	++p;
-+
-+	p->r = dal_fixed31_32_div(p_last->r, dividers.divider2);
-+	p->g = dal_fixed31_32_div(p_last->g, dividers.divider2);
-+	p->b = dal_fixed31_32_div(p_last->b, dividers.divider2);
-+
-+	++p;
-+
-+	p->r = dal_fixed31_32_div(p_last->r, dividers.divider3);
-+	p->g = dal_fixed31_32_div(p_last->g, dividers.divider3);
-+	p->b = dal_fixed31_32_div(p_last->b, dividers.divider3);
-+}
-+
-+static inline void copy_rgb_regamma_to_coordinates_x(
-+		struct hw_x_point *coordinates_x,
-+		uint32_t hw_points_num,
-+		const struct pwl_float_data_ex *rgb_ex)
-+{
-+	struct hw_x_point *coords = coordinates_x;
-+	uint32_t i = 0;
-+	const struct pwl_float_data_ex *rgb_regamma = rgb_ex;
-+
-+	while (i <= hw_points_num) {
-+		coords->regamma_y_red = rgb_regamma->r;
-+		coords->regamma_y_green = rgb_regamma->g;
-+		coords->regamma_y_blue = rgb_regamma->b;
-+
-+		++coords;
-+		++rgb_regamma;
-+		++i;
-+	}
-+}
-+
-+static bool calculate_interpolated_hardware_curve(
-+	struct pwl_result_data *rgb,
-+	struct pixel_gamma_point *coeff128,
-+	struct pwl_float_data *rgb_user,
-+	const struct hw_x_point *coordinates_x,
-+	const struct gamma_pixel *axis_x_256,
-+	uint32_t number_of_points,
-+	enum surface_pixel_format pixel_format)
-+{
-+
-+	const struct pixel_gamma_point *coeff;
-+	struct pixel_gamma_point *coeff_128 = coeff128;
-+	uint32_t max_entries = 3 - 1;
-+	struct pwl_result_data *rgb_resulted = rgb;
-+
-+	uint32_t i = 0;
-+
-+	if (!build_oem_custom_gamma_mapping_coefficients(
-+			coeff_128, coordinates_x, axis_x_256,
-+			number_of_points,
-+			pixel_format))
-+		return false;
-+
-+	coeff = coeff128;
-+	max_entries += RGB_256X3X16;
-+
-+	/* TODO: float point case */
-+
-+	while (i <= number_of_points) {
-+		rgb_resulted->red = calculate_mapped_value(
-+			rgb_user, coeff, CHANNEL_NAME_RED, max_entries);
-+		rgb_resulted->green = calculate_mapped_value(
-+			rgb_user, coeff, CHANNEL_NAME_GREEN, max_entries);
-+		rgb_resulted->blue = calculate_mapped_value(
-+			rgb_user, coeff, CHANNEL_NAME_BLUE, max_entries);
-+
-+		++coeff;
-+		++rgb_resulted;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static bool map_regamma_hw_to_x_user(
-+	struct pixel_gamma_point *coeff128,
-+	struct pwl_float_data *rgb_oem,
-+	struct pwl_result_data *rgb_resulted,
-+	struct pwl_float_data *rgb_user,
-+	struct hw_x_point *coords_x,
-+	const struct gamma_pixel *axis_x,
-+	const struct dc_gamma *gamma,
-+	const struct pwl_float_data_ex *rgb_regamma,
-+	struct dividers dividers,
-+	uint32_t hw_points_num,
-+	const struct core_surface *surface)
-+{
-+	/* setup to spare calculated ideal regamma values */
-+
-+	struct pixel_gamma_point *coeff = coeff128;
-+
-+	struct hw_x_point *coords = coords_x;
-+
-+	copy_rgb_regamma_to_coordinates_x(coords, hw_points_num, rgb_regamma);
-+
-+	return calculate_interpolated_hardware_curve(
-+			rgb_resulted, coeff, rgb_user, coords, axis_x,
-+			hw_points_num, surface->public.format);
-+}
-+
-+static void build_new_custom_resulted_curve(
-+	struct pwl_result_data *rgb_resulted,
-+	uint32_t hw_points_num)
-+{
-+	struct pwl_result_data *rgb = rgb_resulted;
-+	struct pwl_result_data *rgb_plus_1 = rgb + 1;
-+
-+	uint32_t i;
-+
-+	i = 0;
-+
-+	while (i != hw_points_num + 1) {
-+		rgb->red = dal_fixed31_32_clamp(
-+			rgb->red, dal_fixed31_32_zero,
-+			dal_fixed31_32_one);
-+		rgb->green = dal_fixed31_32_clamp(
-+			rgb->green, dal_fixed31_32_zero,
-+			dal_fixed31_32_one);
-+		rgb->blue = dal_fixed31_32_clamp(
-+			rgb->blue, dal_fixed31_32_zero,
-+			dal_fixed31_32_one);
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	rgb = rgb_resulted;
-+
-+	i = 1;
-+
-+	while (i != hw_points_num + 1) {
-+		if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
-+			rgb_plus_1->red = rgb->red;
-+		if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
-+			rgb_plus_1->green = rgb->green;
-+		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
-+			rgb_plus_1->blue = rgb->blue;
-+
-+		rgb->delta_red = dal_fixed31_32_sub(
-+			rgb_plus_1->red,
-+			rgb->red);
-+		rgb->delta_green = dal_fixed31_32_sub(
-+			rgb_plus_1->green,
-+			rgb->green);
-+		rgb->delta_blue = dal_fixed31_32_sub(
-+			rgb_plus_1->blue,
-+			rgb->blue);
-+
-+		++rgb_plus_1;
-+		++rgb;
-+		++i;
-+	}
-+}
-+
-+static void rebuild_curve_configuration_magic(
-+		struct curve_points *arr_points,
-+		struct pwl_result_data *rgb_resulted,
-+		const struct hw_x_point *coordinates_x,
-+		uint32_t hw_points_num)
-+{
-+	const struct fixed31_32 magic_number =
-+		dal_fixed31_32_from_fraction(249, 1000);
-+
-+	struct fixed31_32 y_r;
-+	struct fixed31_32 y_g;
-+	struct fixed31_32 y_b;
-+
-+	struct fixed31_32 y1_min;
-+	struct fixed31_32 y2_max;
-+	struct fixed31_32 y3_max;
-+
-+	y_r = rgb_resulted[0].red;
-+	y_g = rgb_resulted[0].green;
-+	y_b = rgb_resulted[0].blue;
-+
-+	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
-+
-+	arr_points[0].x = coordinates_x[0].adjusted_x;
-+	arr_points[0].y = y1_min;
-+	arr_points[0].slope = dal_fixed31_32_div(
-+					arr_points[0].y,
-+					arr_points[0].x);
-+
-+	arr_points[1].x = dal_fixed31_32_add(
-+			coordinates_x[hw_points_num - 1].adjusted_x,
-+			magic_number);
-+
-+	arr_points[2].x = arr_points[1].x;
-+
-+	y_r = rgb_resulted[hw_points_num - 1].red;
-+	y_g = rgb_resulted[hw_points_num - 1].green;
-+	y_b = rgb_resulted[hw_points_num - 1].blue;
-+
-+	y2_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-+
-+	arr_points[1].y = y2_max;
-+
-+	y_r = rgb_resulted[hw_points_num].red;
-+	y_g = rgb_resulted[hw_points_num].green;
-+	y_b = rgb_resulted[hw_points_num].blue;
-+
-+	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-+
-+	arr_points[2].y = y3_max;
-+
-+	arr_points[2].slope = dal_fixed31_32_one;
-+}
-+
-+static bool convert_to_custom_float_format(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	uint32_t *result)
-+{
-+	uint32_t mantissa;
-+	uint32_t exponenta;
-+	bool negative;
-+
-+	return build_custom_float(
-+		value, format, &negative, &mantissa, &exponenta) &&
-+	setup_custom_float(
-+		format, negative, mantissa, exponenta, result);
-+}
-+
-+static bool convert_to_custom_float(
-+		struct pwl_result_data *rgb_resulted,
-+		struct curve_points *arr_points,
-+		uint32_t hw_points_num)
-+{
-+	struct custom_float_format fmt;
-+
-+	struct pwl_result_data *rgb = rgb_resulted;
-+
-+	uint32_t i = 0;
-+
-+	fmt.exponenta_bits = 6;
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	if (!convert_to_custom_float_format(
-+		arr_points[0].x,
-+		&fmt,
-+		&arr_points[0].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		arr_points[0].offset,
-+		&fmt,
-+		&arr_points[0].custom_float_offset)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		arr_points[0].slope,
-+		&fmt,
-+		&arr_points[0].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 10;
-+	fmt.sign = false;
-+
-+	if (!convert_to_custom_float_format(
-+		arr_points[1].x,
-+		&fmt,
-+		&arr_points[1].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		arr_points[1].y,
-+		&fmt,
-+		&arr_points[1].custom_float_y)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(
-+		arr_points[2].slope,
-+		&fmt,
-+		&arr_points[2].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	while (i != hw_points_num) {
-+		if (!convert_to_custom_float_format(
-+			rgb->red,
-+			&fmt,
-+			&rgb->red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->green,
-+			&fmt,
-+			&rgb->green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->blue,
-+			&fmt,
-+			&rgb->blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->delta_red,
-+			&fmt,
-+			&rgb->delta_red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->delta_green,
-+			&fmt,
-+			&rgb->delta_green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(
-+			rgb->delta_blue,
-+			&fmt,
-+			&rgb->delta_blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+void calculate_regamma_params(struct regamma_params *params,
-+		struct temp_params *temp_params,
-+		const struct core_gamma *ramp,
-+		const struct core_surface *surface)
-+{
-+	struct gamma_curve *arr_curve_points = params->arr_curve_points;
-+	struct curve_points *arr_points = params->arr_points;
-+	struct hw_x_point *coordinates_x = temp_params->coordinates_x;
-+	struct pwl_float_data *rgb_user = temp_params->rgb_user;
-+	struct pwl_float_data_ex *rgb_regamma = temp_params->rgb_regamma;
-+	struct pwl_float_data *rgb_oem = temp_params->rgb_oem;
-+	struct pwl_result_data *rgb_resulted = params->rgb_resulted;
-+	struct dividers dividers;
-+	struct gamma_pixel *axix_x_256 = temp_params->axix_x_256;
-+	struct pixel_gamma_point *coeff128_oem = temp_params->coeff128_oem;
-+	struct pixel_gamma_point *coeff128 = temp_params->coeff128;
-+
-+	dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
-+	dividers.divider2 = dal_fixed31_32_from_int(2);
-+	dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
-+
-+	build_evenly_distributed_points(
-+			axix_x_256,
-+			256,
-+			dal_fixed31_32_one,
-+			dividers);
-+
-+	scale_gamma(rgb_user, ramp, dividers);
-+
-+	setup_distribution_points(arr_curve_points, arr_points,
-+			&params->hw_points_num, coordinates_x);
-+
-+	build_regamma_curve(rgb_regamma, rgb_oem, coeff128_oem,
-+			ramp, surface, params->hw_points_num,
-+			coordinates_x, axix_x_256, dividers);
-+
-+	map_regamma_hw_to_x_user(coeff128, rgb_oem, rgb_resulted, rgb_user,
-+			coordinates_x, axix_x_256, &ramp->public, rgb_regamma,
-+			dividers, params->hw_points_num, surface);
-+
-+	build_new_custom_resulted_curve(rgb_resulted, params->hw_points_num);
-+
-+	rebuild_curve_configuration_magic(
-+			arr_points,
-+			rgb_resulted,
-+			coordinates_x,
-+			params->hw_points_num);
-+
-+	convert_to_custom_float(rgb_resulted, arr_points,
-+			params->hw_points_num);
-+}
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 1a9ee8f..3878a61 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -40,36 +40,33 @@ struct surface {
- 	int ref_count;
- };
- 
-+struct gamma {
-+	struct core_gamma protected;
-+	int ref_count;
-+};
-+
- #define DC_SURFACE_TO_SURFACE(dc_surface) container_of(dc_surface, struct surface, protected.public)
- #define CORE_SURFACE_TO_SURFACE(core_surface) container_of(core_surface, struct surface, protected)
- 
-+#define DC_GAMMA_TO_GAMMA(dc_gamma) \
-+	container_of(dc_gamma, struct gamma, protected.public)
-+#define CORE_GAMMA_TO_GAMMA(core_gamma) \
-+	container_of(core_gamma, struct gamma, protected)
-+
-+
- /*******************************************************************************
-  * Private functions
-  ******************************************************************************/
- static bool construct(struct dc_context *ctx, struct surface *surface)
- {
--	uint32_t i;
--	struct gamma_ramp *gamma =
--			&surface->protected.public.gamma_correction;
--
--	/* construct gamma default value. */
--	for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
--		gamma->gamma_ramp_rgb256x3x16.red[i] =
--				(unsigned short) (i << 8);
--		gamma->gamma_ramp_rgb256x3x16.green[i] =
--				(unsigned short) (i << 8);
--		gamma->gamma_ramp_rgb256x3x16.blue[i] =
--				(unsigned short) (i << 8);
--	}
--	gamma->type = GAMMA_RAMP_TYPE_RGB256;
--	gamma->size = sizeof(gamma->gamma_ramp_rgb256x3x16);
--
- 	surface->protected.ctx = ctx;
- 	return true;
- }
- 
- static void destruct(struct surface *surface)
- {
-+	if (surface->protected.public.gamma_correction)
-+		dc_gamma_release(surface->protected.public.gamma_correction);
- }
- 
- /*******************************************************************************
-@@ -121,3 +118,54 @@ void dc_surface_release(const struct dc_surface *dc_surface)
- 		dm_free(surface->protected.ctx, surface);
- 	}
- }
-+
-+static bool construct_gamma(struct dc_context *ctx, struct gamma *gamma)
-+{
-+	return true;
-+}
-+
-+static void destruct_gamma(struct gamma *gamma)
-+{
-+
-+}
-+
-+void dc_gamma_retain(const struct dc_gamma *dc_gamma)
-+{
-+	struct gamma *gamma = DC_GAMMA_TO_GAMMA(dc_gamma);
-+
-+	++gamma->ref_count;
-+}
-+
-+void dc_gamma_release(const struct dc_gamma *dc_gamma)
-+{
-+	struct gamma *gamma = DC_GAMMA_TO_GAMMA(dc_gamma);
-+	--gamma->ref_count;
-+
-+	if (gamma->ref_count == 0) {
-+		destruct_gamma(gamma);
-+		dm_free(gamma->protected.ctx, gamma);
-+	}
-+}
-+
-+
-+struct dc_gamma *dc_create_gamma(const struct dc *dc)
-+{
-+	struct gamma *gamma = dm_alloc(dc->ctx, sizeof(*gamma));
-+
-+	if (gamma == NULL)
-+		goto alloc_fail;
-+
-+	if (false == construct_gamma(dc->ctx, gamma))
-+		goto construct_fail;
-+
-+	dc_gamma_retain(&gamma->protected.public);
-+
-+	return &gamma->protected.public;
-+
-+construct_fail:
-+	dm_free(dc->ctx, gamma);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 7980e9f..e8579bc 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -133,68 +133,6 @@ target_alloc_fail:
- 	return NULL;
- }
- 
--static void build_gamma_params(
--		enum pixel_format pixel_format,
--		struct gamma_parameters *gamma_param)
--{
--	uint32_t i;
--
--	/* translate parameters */
--	gamma_param->surface_pixel_format = pixel_format;
--
--	gamma_param->regamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_SW;
--	gamma_param->degamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_SW;
--
--	gamma_param->selected_gamma_lut = GRAPHICS_GAMMA_LUT_REGAMMA;
--
--	/* TODO support non-legacy gamma */
--	gamma_param->disable_adjustments = false;
--	gamma_param->flag.bits.config_is_changed = 0;
--	gamma_param->flag.bits.regamma_update = 1;
--	gamma_param->flag.bits.gamma_update = 1;
--
--	/* Set regamma */
--	gamma_param->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB = 1;
--	gamma_param->regamma.features.bits.OVERLAY_DEGAMMA_SRGB = 1;
--	gamma_param->regamma.features.bits.GAMMA_RAMP_ARRAY = 0;
--	gamma_param->regamma.features.bits.APPLY_DEGAMMA = 0;
--
--	for (i = 0; i < COEFF_RANGE; i++) {
--		gamma_param->regamma.gamma_coeff.a0[i] = REGAMMA_COEFF_A0;
--		gamma_param->regamma.gamma_coeff.a1[i] = REGAMMA_COEFF_A1;
--		gamma_param->regamma.gamma_coeff.a2[i] = REGAMMA_COEFF_A2;
--		gamma_param->regamma.gamma_coeff.a3[i] = REGAMMA_COEFF_A3;
--		gamma_param->regamma.gamma_coeff.gamma[i] = REGAMMA_COEFF_GAMMA;
--	}
--}
--
--
--static bool program_gamma(
--		struct dc_context *ctx,
--		struct dc_surface *surface,
--		struct input_pixel_processor *ipp,
--		struct output_pixel_processor *opp)
--{
--	struct gamma_parameters *gamma_param;
--	bool result= false;
--
--	gamma_param = dm_alloc(ctx, sizeof(struct gamma_parameters));
--
--	if (!gamma_param)
--		goto gamma_param_fail;
--
--	build_gamma_params(surface->format, gamma_param);
--
--	result = ctx->dc->hwss.set_gamma_ramp(ipp, opp,
--			&surface->gamma_correction,
--			gamma_param);
--
--	dm_free(ctx, gamma_param);
--
--gamma_param_fail:
--	return result;
--}
--
- static bool validate_surface_address(
- 		struct dc_plane_address address)
- {
-@@ -298,18 +236,27 @@ bool dc_commit_surfaces_to_target(
- 	for (i = 0; i < new_surface_count; i++) {
- 		struct dc_surface *surface = new_surfaces[i];
- 		struct core_surface *core_surface = DC_SURFACE_TO_CORE(surface);
-+		struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[0]);
- 		bool is_valid_address =
- 				validate_surface_address(surface->address);
- 
-+
- 		dal_logger_write(dc->ctx->logger,
- 					LOG_MAJOR_INTERFACE_TRACE,
- 					LOG_MINOR_COMPONENT_DC,
- 					"0x%x:",
- 					surface);
- 
--		program_gamma(dc->ctx, surface,
--			DC_STREAM_TO_CORE(target->public.streams[0])->ipp,
--			DC_STREAM_TO_CORE(target->public.streams[0])->opp);
-+		if (surface->gamma_correction) {
-+			struct core_gamma *gamma = DC_GAMMA_TO_CORE(
-+						surface->gamma_correction);
-+
-+			dc->hwss.set_gamma_correction(
-+					stream->ipp,
-+					stream->opp,
-+					gamma, core_surface);
-+		}
- 
- 		dc->hwss.set_plane_config(dc, core_surface, target);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index cc3395d..901c8c4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -59,6 +59,43 @@ void dc_destroy(struct dc **dc);
-  * Surface Interfaces
-  ******************************************************************************/
- 
-+enum {
-+	RGB_256X3X16 = 256,
-+	FLOAT_GAMMA_RAMP_MAX = 1025
-+};
-+
-+enum dc_gamma_ramp_type {
-+	GAMMA_RAMP_RBG256X3X16,
-+	GAMMA_RAMP_FLOAT,
-+};
-+
-+struct float_rgb {
-+	struct fixed32_32 red;
-+	struct fixed32_32 green;
-+	struct fixed32_32 blue;
-+};
-+
-+struct dc_gamma_ramp_float {
-+	struct float_rgb scale;
-+	struct float_rgb offset;
-+	struct float_rgb gamma_curve[FLOAT_GAMMA_RAMP_MAX];
-+};
-+
-+struct dc_gamma_ramp_rgb256x3x16 {
-+	uint16_t red[RGB_256X3X16];
-+	uint16_t green[RGB_256X3X16];
-+	uint16_t blue[RGB_256X3X16];
-+};
-+
-+struct dc_gamma {
-+	enum dc_gamma_ramp_type type;
-+	union {
-+		struct dc_gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
-+		struct dc_gamma_ramp_float gamma_ramp_float;
-+	};
-+	uint32_t size;
-+};
-+
- struct dc_surface {
- 	bool visible;
- 	bool flip_immediate;
-@@ -77,8 +114,7 @@ struct dc_surface {
- 	enum dc_rotation_angle rotation;
- 	enum plane_stereo_format stereo_format;
- 
--	struct gamma_ramp gamma_correction; /* deprecated */
--	struct dc_gamma_ramp gamma;
-+	struct dc_gamma *gamma_correction;
- };
- 
- /*
-@@ -102,6 +138,9 @@ const struct dc_surface_status* dc_surface_get_status(
- void dc_surface_retain(const struct dc_surface *dc_surface);
- void dc_surface_release(const struct dc_surface *dc_surface);
- 
-+void dc_gamma_release(const struct dc_gamma *dc_gamma);
-+struct dc_gamma *dc_create_gamma(const struct dc *dc);
-+
- /*
-  * This structure holds a surface address.  There could be multiple addresses
-  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 67e62c3..5593c17 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -559,79 +559,6 @@ enum dc_connection_type {
- 	dc_connection_active_dongle
- };
- 
--/*
-- * Gamma ramp representation in DC
-- *
-- * A gamma ramp is just a curve defined within the range of [min, max] with
-- * arbitrary precision.
-- *
-- * DM is responsible for providing DC with an interface to obtain any y value
-- * within that range with a selected precision.
-- *
-- * bit32 ------------------------------------------------- bit 0
-- *       [  padding  ][ exponent bits ][  fraction bits  ]
-- *
-- * DC specifies the input x value and precision to the callback function
-- * get_gamma_value as well as providing the context and DM returns the y
-- * value.
-- *
-- * If fraction_bits + exponent_bits exceed width of 32 bits, get_gamma_value
-- * returns 0.  If x is outside the bounds of [min, max], get_gamma_value
-- * returns 0.
-- *
-- */
--/* TODO: Deprecated */
--enum {
--	RGB_256X3X16 = 256,
--	DX_GAMMA_RAMP_MAX = 1025
--};
--
--enum gamma_ramp_type {
--	GAMMA_RAMP_UNINITIALIZED = 0,
--	GAMMA_RAMP_DEFAULT,
--	GAMMA_RAMP_RBG256X3X16,
--	GAMMA_RAMP_DXGI_1,
--};
--
--struct dxgi_rgb {
--	struct fixed32_32 red;
--	struct fixed32_32 green;
--	struct fixed32_32 blue;
--};
--
--struct gamma_ramp_dxgi_1 {
--	struct dxgi_rgb scale;
--	struct dxgi_rgb offset;
--	struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX];
--};
--
--struct gamma_ramp_rgb256x3x16 {
--	uint16_t red[RGB_256X3X16];
--	uint16_t green[RGB_256X3X16];
--	uint16_t blue[RGB_256X3X16];
--};
--
--struct gamma_ramp {
--	enum gamma_ramp_type type;
--	union {
--		struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16;
--		struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1;
--	};
--	uint32_t size;
--};
--
--
--struct dc_gamma_ramp {
--	uint32_t (*get_gamma_value) (
--			void *context,
--			uint8_t exponent_bits,
--			uint8_t fraction_bits,
--			uint32_t x);
--	void *context;
--	uint32_t min;
--	uint32_t max;
--};
--
- struct dc_csc_adjustments {
- 	struct fixed31_32 contrast;
- 	struct fixed31_32 saturation;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 754e81d..946e42f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -42,6 +42,7 @@
- #include "stream_encoder.h"
- #include "link_encoder.h"
- #include "clock_source.h"
-+#include "gamma_calcs.h"
- 
- /* include DCE11 register header files */
- #include "dce/dce_11_0_d.h"
-@@ -476,64 +477,83 @@ static bool dce110_enable_display_power_gating(
- 		return false;
- }
- 
-+static void build_prescale_params(struct ipp_prescale_params *prescale_params,
-+		const struct core_surface *surface)
-+{
-+	prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
-+
-+	switch (surface->public.format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
-+		prescale_params->scale = 0x2000;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		/* TODO */
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		/* TODO */
-+		break;
-+	default:
-+		ASSERT(false);
-+	}
-+}
-+
- 
- static bool set_gamma_ramp(
- 	struct input_pixel_processor *ipp,
- 	struct output_pixel_processor *opp,
--	const struct gamma_ramp *ramp,
--	const struct gamma_parameters *params)
-+	const struct core_gamma *ramp,
-+	const struct core_surface *surface)
- {
--	/*Power on LUT memory*/
--	opp->funcs->opp_power_on_regamma_lut(opp, true);
-+	struct ipp_prescale_params *prescale_params;
-+	struct regamma_params *regamma_params;
-+	struct temp_params *temp_params;
-+	bool result = false;
- 
-+	prescale_params = dm_alloc(opp->ctx,
-+			sizeof(struct ipp_prescale_params));
- 
--	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
--		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
--		/* do legacy DCP for 256 colors if we are requested to do so */
--		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
--			ipp, ramp, params);
-+	if (prescale_params == NULL)
-+		goto prescale_alloc_fail;
- 
--		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
-+	regamma_params = dm_alloc(opp->ctx,
-+			sizeof(struct regamma_params));
-+	if (regamma_params == NULL)
-+		goto regamma_alloc_fail;
- 
--		/* set bypass */
--		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
-+	temp_params = dm_alloc(opp->ctx, sizeof(struct temp_params));
- 
--		ipp->funcs->ipp_set_degamma(ipp, params, true);
-+	if (temp_params == NULL)
-+		goto temp_alloc_fail;
- 
--		opp->funcs->opp_set_regamma(opp, ramp, params, true);
--	} else if (params->selected_gamma_lut ==
--			GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA) {
--		if (!opp->funcs->opp_map_legacy_and_regamma_hw_to_x_user(
--			opp, ramp, params)) {
--			BREAK_TO_DEBUGGER();
--			/* invalid parameters or bug */
--			return false;
--		}
-+	regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM;
- 
--		/* do legacy DCP for 256 colors if we are requested to do so */
--		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
--			ipp, ramp, params);
-+	opp->funcs->opp_power_on_regamma_lut(opp, true);
- 
--		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
-+	build_prescale_params(prescale_params, surface);
- 
--		/* set bypass */
--		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
--	} else {
--		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, false);
-+	ipp->funcs->ipp_program_prescale(ipp, prescale_params);
- 
--		ipp->funcs->ipp_program_prescale(ipp, params->surface_pixel_format);
-+	ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_sRGB);
- 
--		/* Do degamma step : remove the given gamma value from FB.
--		 * For FP16 or no degamma do by pass */
--		ipp->funcs->ipp_set_degamma(ipp, params, false);
-+	calculate_regamma_params(regamma_params, temp_params, ramp, surface);
- 
--		opp->funcs->opp_set_regamma(opp, ramp, params, false);
--	}
-+	opp->funcs->opp_set_regamma(opp, regamma_params);
- 
--	/*re-enable low power mode for LUT memory*/
- 	opp->funcs->opp_power_on_regamma_lut(opp, false);
- 
--	return true;
-+	dm_free(opp->ctx, temp_params);
-+
-+	result = true;
-+
-+temp_alloc_fail:
-+	dm_free(opp->ctx, regamma_params);
-+regamma_alloc_fail:
-+	dm_free(opp->ctx, prescale_params);
-+prescale_alloc_fail:
-+	return result;
- }
- 
- static enum dc_status bios_parser_crtc_source_select(
-@@ -1662,7 +1682,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.reset_hw_ctx = reset_hw_ctx,
- 	.set_plane_config = set_plane_config,
- 	.update_plane_address = update_plane_address,
--	.set_gamma_ramp = set_gamma_ramp,
-+	.set_gamma_correction = set_gamma_ramp,
- 	.power_down = power_down,
- 	.enable_accelerated_mode = enable_accelerated_mode,
- 	.enable_timing_synchronization = enable_timing_synchronization,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-index def54df..eafa345 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-@@ -28,6 +28,7 @@
- 
- #include "core_types.h"
- 
-+#define GAMMA_HW_POINTS_NUM 256
- struct dc;
- 
- bool dce110_hw_sequencer_construct(struct dc *dc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-index 6ab3527..e67b7e6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -36,9 +36,6 @@ static struct ipp_funcs funcs = {
- 		.ipp_cursor_set_position = dce110_ipp_cursor_set_position,
- 		.ipp_program_prescale = dce110_ipp_program_prescale,
- 		.ipp_set_degamma = dce110_ipp_set_degamma,
--		.ipp_set_legacy_input_gamma_mode = dce110_ipp_set_legacy_input_gamma_mode,
--		.ipp_set_legacy_input_gamma_ramp = dce110_ipp_set_legacy_input_gamma_ramp,
--		.ipp_set_palette = dce110_ipp_set_palette,
- };
- 
- bool dce110_ipp_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index 709906f..dde138c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -42,7 +42,6 @@ struct dce110_ipp_reg_offsets {
- struct dce110_ipp {
- 	struct input_pixel_processor base;
- 	struct dce110_ipp_reg_offsets offsets;
--	struct dev_c_lut saved_palette[RGB_256X3X16];
- };
- 
- bool dce110_ipp_construct(
-@@ -65,29 +64,11 @@ bool dce110_ipp_cursor_set_attributes(
- /* DEGAMMA RELATED */
- bool dce110_ipp_set_degamma(
- 	struct input_pixel_processor *ipp,
--	const struct gamma_parameters *params,
--	bool force_bypass);
-+	enum ipp_degamma_mode mode);
- 
- void dce110_ipp_program_prescale(
- 	struct input_pixel_processor *ipp,
--	enum pixel_format pixel_format);
--
--void dce110_ipp_set_legacy_input_gamma_mode(
--		struct input_pixel_processor *ipp,
--		bool is_legacy);
--
--bool dce110_ipp_set_legacy_input_gamma_ramp(
--	struct input_pixel_processor *ipp,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params);
--
--bool dce110_ipp_set_palette(
--	struct input_pixel_processor *ipp,
--	const struct dev_c_lut *palette,
--	uint32_t start,
--	uint32_t length,
--	enum pixel_format surface_pixel_format);
--
-+	struct ipp_prescale_params *params);
- /*
-  * Helper functions to be resused in other ASICs
-  */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index fcf65f1..dc0ccbb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -41,35 +41,6 @@ enum {
- 	MAX_INPUT_LUT_ENTRY = 256
- };
- 
--/* CALCULATION OPERATIONS*/
--static void convert_256_lut_entries_to_gxo_format(
--	const struct gamma_ramp_rgb256x3x16 *lut,
--	struct dev_c_lut16 *gamma)
--{
--	uint32_t i = 0;
--
--	ASSERT(lut);
--	ASSERT(gamma);
--
--	do {
--		gamma->red = lut->red[i];
--		gamma->green = lut->green[i];
--		gamma->blue = lut->blue[i];
--
--		++gamma;
--		++i;
--	} while (i != MAX_INPUT_LUT_ENTRY);
--}
--
--static void convert_udx_gamma_entries_to_gxo_format(
--	const struct gamma_ramp_dxgi_1 *lut,
--	struct dev_c_lut16 *gamma)
--{
--	/* TODO here we deal with DXGI gamma table,
--	 * originally, values was expressed as 'float',
--	 * now values expressed as 'dal_fixed20_12'. */
--}
--
- /*PROTOTYPE DECLARATIONS*/
- static void set_lut_inc(
- 	struct dce110_ipp *ipp110,
-@@ -85,111 +56,111 @@ static void program_white_offsets(
- 	struct dce110_ipp *ipp110,
- 	struct dev_c_lut16 *offset);
- 
--static void program_lut_gamma(
--	struct dce110_ipp *ipp110,
--	const struct dev_c_lut16 *gamma,
--	const struct gamma_parameters *params);
--
--static void program_prescale(
--	struct dce110_ipp *ipp110,
--	enum pixel_format pixel_format);
-+bool dce110_ipp_set_degamma(
-+	struct input_pixel_processor *ipp,
-+	enum ipp_degamma_mode mode)
-+{
-+	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
- 
--static void set_legacy_input_gamma_mode(
--	struct dce110_ipp *ipp110,
--	bool is_legacy);
-+	uint32_t value = 0;
- 
--static bool set_legacy_input_gamma_ramp_rgb256x3x16(
--	struct dce110_ipp *ipp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params);
-+	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_sRGB) ? 1 : 0;
- 
--static bool set_legacy_input_gamma_ramp_dxgi1(
--	struct dce110_ipp *ipp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params);
-+	set_reg_field_value(
-+		value,
-+		degamma_type,
-+		DEGAMMA_CONTROL,
-+		GRPH_DEGAMMA_MODE);
- 
--static bool set_default_gamma(
--	struct dce110_ipp *ipp110,
--	enum pixel_format surface_pixel_format);
-+	set_reg_field_value(
-+		value,
-+		degamma_type,
-+		DEGAMMA_CONTROL,
-+		CURSOR_DEGAMMA_MODE);
- 
--static void set_degamma(
--	struct dce110_ipp *ipp110,
--	const struct gamma_parameters *params,
--	bool force_bypass);
-+	set_reg_field_value(
-+		value,
-+		degamma_type,
-+		DEGAMMA_CONTROL,
-+		CURSOR2_DEGAMMA_MODE);
- 
--bool dce110_ipp_set_legacy_input_gamma_ramp(
--	struct input_pixel_processor *ipp,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+	dm_write_reg(ipp110->base.ctx, DCP_REG(mmDEGAMMA_CONTROL), value);
- 
--	switch (gamma_ramp->type) {
--	case GAMMA_RAMP_RBG256X3X16:
--		return set_legacy_input_gamma_ramp_rgb256x3x16(
--				ipp110, gamma_ramp, params);
--	case GAMMA_RAMP_DXGI_1:
--		return set_legacy_input_gamma_ramp_dxgi1(
--				ipp110, gamma_ramp, params);
--	default:
--		ASSERT_CRITICAL(false);
--		return false;
--	}
-+	return true;
- }
- 
--bool dce110_ipp_set_palette(
-+void dce110_ipp_program_prescale(
- 	struct input_pixel_processor *ipp,
--	const struct dev_c_lut *palette,
--	uint32_t start,
--	uint32_t length,
--	enum pixel_format surface_pixel_format)
-+	struct ipp_prescale_params *params)
- {
- 	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
--	uint32_t i;
- 
--	if (((start + length) > MAX_INPUT_LUT_ENTRY) || (NULL == palette)) {
--		BREAK_TO_DEBUGGER();
--		/* wrong input */
--		return false;
--	}
-+	uint32_t prescale_control = 0;
-+	uint32_t prescale_value = 0;
-+	uint32_t legacy_lut_control = 0;
- 
--	for (i = start; i < start + length; i++) {
--		ipp110->saved_palette[i] = palette[i];
--		ipp110->saved_palette[i] = palette[i];
--		ipp110->saved_palette[i] = palette[i];
--	}
-+	prescale_control = dm_read_reg(ipp110->base.ctx,
-+			DCP_REG(mmPRESCALE_GRPH_CONTROL));
- 
--	return set_default_gamma(ipp110, surface_pixel_format);
--}
-+	if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
- 
--bool dce110_ipp_set_degamma(
--	struct input_pixel_processor *ipp,
--	const struct gamma_parameters *params,
--	bool force_bypass)
--{
--	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+		set_reg_field_value(
-+			prescale_control,
-+			0,
-+			PRESCALE_GRPH_CONTROL,
-+			GRPH_PRESCALE_BYPASS);
- 
--	set_degamma(ipp110, params, force_bypass);
-+		/*
-+		 * If prescale is in use, then legacy lut should
-+		 * be bypassed
-+		 */
-+		legacy_lut_control = dm_read_reg(ipp110->base.ctx,
-+			DCP_REG(mmINPUT_GAMMA_CONTROL));
- 
--	return true;
--}
-+		set_reg_field_value(
-+			legacy_lut_control,
-+			1,
-+			INPUT_GAMMA_CONTROL,
-+			GRPH_INPUT_GAMMA_MODE);
- 
--void dce110_ipp_program_prescale(
--	struct input_pixel_processor *ipp,
--	enum pixel_format pixel_format)
--{
--	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+		dm_write_reg(ipp110->base.ctx,
-+			DCP_REG(mmINPUT_GAMMA_CONTROL),
-+			legacy_lut_control);
-+	} else {
-+		set_reg_field_value(
-+			prescale_control,
-+			1,
-+			PRESCALE_GRPH_CONTROL,
-+			GRPH_PRESCALE_BYPASS);
-+	}
- 
--	program_prescale(ipp110, pixel_format);
--}
-+	set_reg_field_value(
-+		prescale_value,
-+		params->scale,
-+		PRESCALE_VALUES_GRPH_R,
-+		GRPH_PRESCALE_SCALE_R);
- 
--void dce110_ipp_set_legacy_input_gamma_mode(
--		struct input_pixel_processor *ipp,
--		bool is_legacy)
--{
--	struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp);
-+	set_reg_field_value(
-+		prescale_value,
-+		params->bias,
-+		PRESCALE_VALUES_GRPH_R,
-+		GRPH_PRESCALE_BIAS_R);
-+
-+	dm_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmPRESCALE_GRPH_CONTROL),
-+		prescale_control);
-+
-+	dm_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmPRESCALE_VALUES_GRPH_R),
-+		prescale_value);
-+
-+	dm_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmPRESCALE_VALUES_GRPH_G),
-+		prescale_value);
- 
--	set_legacy_input_gamma_mode(ipp110, is_legacy);
-+	dm_write_reg(ipp110->base.ctx,
-+		DCP_REG(mmPRESCALE_VALUES_GRPH_B),
-+		prescale_value);
- }
- 
- static void set_lut_inc(
-@@ -426,447 +397,3 @@ void dce110_helper_program_black_white_offset(
- 	program_black_offsets(ipp110, &black_offset);
- 	program_white_offsets(ipp110, &white_offset);
- }
--
--static void program_lut_gamma(
--	struct dce110_ipp *ipp110,
--	const struct dev_c_lut16 *gamma,
--	const struct gamma_parameters *params)
--{
--	uint32_t i = 0;
--	uint32_t value = 0;
--	uint32_t addr;
--
--	{
--		uint8_t max_tries = 10;
--		uint8_t counter = 0;
--
--		/* Power on LUT memory */
--		value = dm_read_reg(
--				ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
--
--		set_reg_field_value(
--			value,
--			1,
--			DCFE_MEM_PWR_CTRL,
--			DCP_REGAMMA_MEM_PWR_DIS);
--
--		dm_write_reg(
--			ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
--
--		while (counter < max_tries) {
--			value =
--				dm_read_reg(
--					ipp110->base.ctx,
--					DCP_REG(mmDCFE_MEM_PWR_STATUS));
--
--			if (get_reg_field_value(
--				value,
--				DCFE_MEM_PWR_STATUS,
--				DCP_REGAMMA_MEM_PWR_STATE) == 0)
--				break;
--
--			++counter;
--		}
--
--		if (counter == max_tries) {
--			dal_logger_write(ipp110->base.ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: regamma lut was not powered on in a timely manner, programming still proceeds\n",
--				__func__);
--		}
--	}
--
--	dce110_helper_program_black_white_offset(ipp110, params->surface_pixel_format);
--
--	dce110_helper_select_lut(ipp110);
--
--	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8) {
--		addr = DCP_REG(mmDC_LUT_SEQ_COLOR);
--
--		do {
--			struct dev_c_lut *index =
--				ipp110->saved_palette + i;
--
--			set_reg_field_value(
--				value,
--				gamma[index->red].red,
--				DC_LUT_SEQ_COLOR,
--				DC_LUT_SEQ_COLOR);
--			dm_write_reg(ipp110->base.ctx, addr, value);
--
--
--			set_reg_field_value(
--				value,
--				gamma[index->green].green,
--				DC_LUT_SEQ_COLOR,
--				DC_LUT_SEQ_COLOR);
--			dm_write_reg(ipp110->base.ctx, addr, value);
--
--
--			set_reg_field_value(
--				value,
--				gamma[index->blue].blue,
--				DC_LUT_SEQ_COLOR,
--				DC_LUT_SEQ_COLOR);
--			dm_write_reg(ipp110->base.ctx, addr, value);
--
--			++i;
--		} while (i != RGB_256X3X16);
--	} else {
--		addr = DCP_REG(mmDC_LUT_SEQ_COLOR);
--
--		do {
--			set_reg_field_value(
--				value,
--				gamma[i].red,
--				DC_LUT_SEQ_COLOR,
--				DC_LUT_SEQ_COLOR);
--			dm_write_reg(ipp110->base.ctx, addr, value);
--
--
--			set_reg_field_value(
--				value,
--				gamma[i].green,
--				DC_LUT_SEQ_COLOR,
--				DC_LUT_SEQ_COLOR);
--			dm_write_reg(ipp110->base.ctx, addr, value);
--
--
--			set_reg_field_value(
--				value,
--				gamma[i].blue,
--				DC_LUT_SEQ_COLOR,
--				DC_LUT_SEQ_COLOR);
--			dm_write_reg(ipp110->base.ctx, addr, value);
--
--			++i;
--		} while (i != RGB_256X3X16);
--	}
--
--	/*  we are done with DCP LUT memory; re-enable low power mode */
--	value = dm_read_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL));
--
--	set_reg_field_value(
--		value,
--		0,
--		DCFE_MEM_PWR_CTRL,
--		DCP_REGAMMA_MEM_PWR_DIS);
--
--	dm_write_reg(ipp110->base.ctx, DCP_REG(mmDCFE_MEM_PWR_CTRL), value);
--}
--
--static void program_prescale(
--	struct dce110_ipp *ipp110,
--	enum pixel_format pixel_format)
--{
--	uint32_t prescale_control;
--	uint32_t prescale_values_grph_r = 0;
--	uint32_t prescale_values_grph_g = 0;
--	uint32_t prescale_values_grph_b = 0;
--
--	uint32_t prescale_num;
--	uint32_t prescale_denom = 1;
--	uint16_t prescale_hw;
--	uint32_t bias_num = 0;
--	uint32_t bias_denom = 1;
--	uint16_t bias_hw;
--
--	const uint32_t addr_control = DCP_REG(mmPRESCALE_GRPH_CONTROL);
--
--	prescale_control = dm_read_reg(ipp110->base.ctx, addr_control);
--
--	set_reg_field_value(
--		prescale_control,
--		0,
--		PRESCALE_GRPH_CONTROL,
--		GRPH_PRESCALE_BYPASS);
--
--	switch (pixel_format) {
--	case PIXEL_FORMAT_RGB565:
--		prescale_num = 64;
--		prescale_denom = 63;
--	break;
--
--	case PIXEL_FORMAT_ARGB8888:
--		/* This function should only be called when using regamma
--		 * and bypassing legacy INPUT GAMMA LUT (function name is
--		 * misleading)
--		 */
--		prescale_num = 256;
--		prescale_denom = 255;
--	break;
--
--	case PIXEL_FORMAT_ARGB2101010:
--		prescale_num = 1024;
--		prescale_denom = 1023;
--	break;
--
--	case PIXEL_FORMAT_ARGB2101010_XRBIAS:
--		prescale_num = 1024;
--		prescale_denom = 510;
--		bias_num = 384;
--		bias_denom = 1024;
--	break;
--
--	case PIXEL_FORMAT_FP16:
--		prescale_num = 1;
--	break;
--
--	default:
--		prescale_num = 1;
--
--		set_reg_field_value(
--			prescale_control,
--			1,
--			PRESCALE_GRPH_CONTROL,
--			GRPH_PRESCALE_BYPASS);
--	}
--
--	prescale_hw = fixed_point_to_int_frac(
--		dal_fixed31_32_from_fraction(prescale_num, prescale_denom),
--		2, 13);
--
--	bias_hw = fixed_point_to_int_frac(
--		dal_fixed31_32_from_fraction(bias_num, bias_denom),
--		2, 13);
--
--
--	set_reg_field_value(
--		prescale_values_grph_r,
--		prescale_hw,
--		PRESCALE_VALUES_GRPH_R,
--		GRPH_PRESCALE_SCALE_R);
--
--	set_reg_field_value(
--		prescale_values_grph_r,
--		bias_hw,
--		PRESCALE_VALUES_GRPH_R,
--		GRPH_PRESCALE_BIAS_R);
--
--
--	set_reg_field_value(
--		prescale_values_grph_g,
--		prescale_hw,
--		PRESCALE_VALUES_GRPH_G,
--		GRPH_PRESCALE_SCALE_G);
--
--	set_reg_field_value(
--		prescale_values_grph_g,
--		bias_hw,
--		PRESCALE_VALUES_GRPH_G,
--		GRPH_PRESCALE_BIAS_G);
--
--
--	set_reg_field_value(
--		prescale_values_grph_b,
--		prescale_hw,
--		PRESCALE_VALUES_GRPH_B,
--		GRPH_PRESCALE_SCALE_B);
--
--	set_reg_field_value(
--		prescale_values_grph_b,
--		bias_hw,
--		PRESCALE_VALUES_GRPH_B,
--		GRPH_PRESCALE_BIAS_B);
--
--	dm_write_reg(ipp110->base.ctx,
--		addr_control, prescale_control);
--
--	{
--		dm_write_reg(ipp110->base.ctx,
--				DCP_REG(mmPRESCALE_VALUES_GRPH_R),
--				prescale_values_grph_r);
--	}
--
--	{
--		dm_write_reg(ipp110->base.ctx,
--				DCP_REG(mmPRESCALE_VALUES_GRPH_G),
--				prescale_values_grph_g);
--	}
--
--	{
--		dm_write_reg(ipp110->base.ctx,
--				DCP_REG(mmPRESCALE_VALUES_GRPH_B),
--				prescale_values_grph_b);
--	}
--}
--
--static void set_legacy_input_gamma_mode(
--	struct dce110_ipp *ipp110,
--	bool is_legacy)
--{
--	const uint32_t addr = DCP_REG(mmINPUT_GAMMA_CONTROL);
--	uint32_t value = dm_read_reg(ipp110->base.ctx, addr);
--
--	set_reg_field_value(
--		value,
--		!is_legacy,
--		INPUT_GAMMA_CONTROL,
--		GRPH_INPUT_GAMMA_MODE);
--
--	dm_write_reg(ipp110->base.ctx, addr, value);
--}
--
--static bool set_legacy_input_gamma_ramp_rgb256x3x16(
--	struct dce110_ipp *ipp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	struct dev_c_lut16 *gamma16 =
--		dm_alloc(
--			ipp110->base.ctx,
--			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
--
--	if (!gamma16)
--		return false;
--
--	convert_256_lut_entries_to_gxo_format(
--		&gamma_ramp->gamma_ramp_rgb256x3x16, gamma16);
--
--	if ((params->surface_pixel_format != PIXEL_FORMAT_ARGB2101010) &&
--		(params->surface_pixel_format !=
--			PIXEL_FORMAT_ARGB2101010_XRBIAS) &&
--		(params->surface_pixel_format != PIXEL_FORMAT_FP16)) {
--		program_lut_gamma(ipp110, gamma16, params);
--		dm_free(ipp110->base.ctx, gamma16);
--		return true;
--	}
--
--	/* TODO process DirectX-specific formats*/
--	dm_free(ipp110->base.ctx, gamma16);
--	return false;
--}
--
--static bool set_legacy_input_gamma_ramp_dxgi1(
--	struct dce110_ipp *ipp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	struct dev_c_lut16 *gamma16 =
--		dm_alloc(
--			ipp110->base.ctx,
--			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
--
--	if (!gamma16)
--		return false;
--
--	convert_udx_gamma_entries_to_gxo_format(
--		&gamma_ramp->gamma_ramp_dxgi1, gamma16);
--
--	if ((params->surface_pixel_format != PIXEL_FORMAT_ARGB2101010) &&
--		(params->surface_pixel_format !=
--			PIXEL_FORMAT_ARGB2101010_XRBIAS) &&
--		(params->surface_pixel_format != PIXEL_FORMAT_FP16)) {
--		program_lut_gamma(ipp110, gamma16, params);
--		dm_free(ipp110->base.ctx, gamma16);
--		return true;
--	}
--
--	/* TODO process DirectX-specific formats*/
--	dm_free(ipp110->base.ctx, gamma16);
--	return false;
--}
--
--static bool set_default_gamma(
--	struct dce110_ipp *ipp110,
--	enum pixel_format surface_pixel_format)
--{
--	uint32_t i;
--
--	struct dev_c_lut16 *gamma16 = NULL;
--	struct gamma_parameters *params = NULL;
--
--	gamma16 = dm_alloc(
--			ipp110->base.ctx,
--			sizeof(struct dev_c_lut16) * MAX_INPUT_LUT_ENTRY);
--
--	if (!gamma16)
--		return false;
--
--	params = dm_alloc(ipp110->base.ctx, sizeof(*params));
--
--	if (!params) {
--		dm_free(ipp110->base.ctx, gamma16);
--		return false;
--	}
--
--	for (i = 0; i < MAX_INPUT_LUT_ENTRY; i++) {
--		gamma16[i].red = gamma16[i].green =
--			gamma16[i].blue = (uint16_t) (i << 8);
--	}
--
--	params->surface_pixel_format = surface_pixel_format;
--	params->regamma_adjust_type = GRAPHICS_REGAMMA_ADJUST_HW;
--	params->degamma_adjust_type = GRAPHICS_DEGAMMA_ADJUST_HW;
--	params->selected_gamma_lut = GRAPHICS_GAMMA_LUT_REGAMMA;
--	params->disable_adjustments = false;
--
--	params->regamma.features.value = 0;
--
--	params->regamma.features.bits.GAMMA_RAMP_ARRAY = 0;
--	params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB = 1;
--	params->regamma.features.bits.OVERLAY_DEGAMMA_SRGB = 1;
--
--	for (i = 0; i < 3; i++) {
--		params->regamma.gamma_coeff.a0[i] = 31308;
--		params->regamma.gamma_coeff.a1[i] = 12920;
--		params->regamma.gamma_coeff.a2[i] = 55;
--		params->regamma.gamma_coeff.a3[i] = 55;
--		params->regamma.gamma_coeff.gamma[i] = 2400;
--
--	}
--
--	program_lut_gamma(ipp110, gamma16, params);
--
--	dm_free(ipp110->base.ctx, gamma16);
--	dm_free(ipp110->base.ctx, params);
--
--	return true;
--}
--
--static void set_degamma(
--	struct dce110_ipp *ipp110,
--	const struct gamma_parameters *params,
--	bool force_bypass)
--{
--	uint32_t value;
--	const uint32_t addr = DCP_REG(mmDEGAMMA_CONTROL);
--	uint32_t degamma_type =
--		params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB == 1 ?
--			1 : 2;
--
--	value = dm_read_reg(ipp110->base.ctx, addr);
--
--	/* if by pass - no degamma
--	 * when legacy and regamma LUT's we do degamma */
--	if (params->degamma_adjust_type == GRAPHICS_DEGAMMA_ADJUST_BYPASS ||
--		(params->surface_pixel_format == PIXEL_FORMAT_FP16 &&
--			params->selected_gamma_lut ==
--				GRAPHICS_GAMMA_LUT_REGAMMA))
--		degamma_type = 0;
--
--	if (force_bypass)
--		degamma_type = 0;
--
--	set_reg_field_value(
--		value,
--		degamma_type,
--		DEGAMMA_CONTROL,
--		GRPH_DEGAMMA_MODE);
--
--	set_reg_field_value(
--		value,
--		degamma_type,
--		DEGAMMA_CONTROL,
--		CURSOR_DEGAMMA_MODE);
--
--	set_reg_field_value(
--		value,
--		degamma_type,
--		DEGAMMA_CONTROL,
--		CURSOR2_DEGAMMA_MODE);
--
--	dm_write_reg(ipp110->base.ctx, addr, value);
--}
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index acb405e..394f187 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -38,55 +38,11 @@ enum {
- 	MAX_NUMBER_OF_ENTRIES = 256
- };
- 
--static void build_evenly_distributed_points(
--	struct gamma_pixel *points,
--	uint32_t numberof_points,
--	struct fixed31_32 max_value,
--	struct fixed31_32 divider1,
--	struct fixed31_32 divider2,
--	struct fixed31_32 divider3)
--{
--	struct gamma_pixel *p = points;
--	struct gamma_pixel *p_last = p + numberof_points - 1;
--
--	uint32_t i = 0;
--
--	do {
--		struct fixed31_32 value = dal_fixed31_32_div_int(
--			dal_fixed31_32_mul_int(max_value, i),
--			numberof_points - 1);
--
--		p->r = value;
--		p->g = value;
--		p->b = value;
--
--		++p;
--		++i;
--	} while (i != numberof_points);
--
--	p->r = dal_fixed31_32_div(p_last->r, divider1);
--	p->g = dal_fixed31_32_div(p_last->g, divider1);
--	p->b = dal_fixed31_32_div(p_last->b, divider1);
--
--	++p;
--
--	p->r = dal_fixed31_32_div(p_last->r, divider2);
--	p->g = dal_fixed31_32_div(p_last->g, divider2);
--	p->b = dal_fixed31_32_div(p_last->b, divider2);
--
--	++p;
--
--	p->r = dal_fixed31_32_div(p_last->r, divider3);
--	p->g = dal_fixed31_32_div(p_last->g, divider3);
--	p->b = dal_fixed31_32_div(p_last->b, divider3);
--}
--
- /*****************************************/
- /* Constructor, Destructor               */
- /*****************************************/
- 
- struct opp_funcs funcs = {
--		.opp_map_legacy_and_regamma_hw_to_x_user = dce110_opp_map_legacy_and_regamma_hw_to_x_user,
- 		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
- 		.opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction,
- 		.opp_program_clamping_and_pixel_encoding = dce110_opp_program_clamping_and_pixel_encoding,
-@@ -101,7 +57,6 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
- 	uint32_t inst,
- 	const struct dce110_opp_reg_offsets *offsets)
- {
--
- 	opp110->base.funcs = &funcs;
- 
- 	opp110->base.ctx = ctx;
-@@ -110,162 +65,11 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
- 
- 	opp110->offsets = *offsets;
- 
--	opp110->regamma.hw_points_num = 128;
--	opp110->regamma.coordinates_x = NULL;
--	opp110->regamma.rgb_resulted = NULL;
--	opp110->regamma.rgb_regamma = NULL;
--	opp110->regamma.coeff128 = NULL;
--	opp110->regamma.coeff128_oem = NULL;
--	opp110->regamma.coeff128_dx = NULL;
--	opp110->regamma.axis_x_256 = NULL;
--	opp110->regamma.axis_x_1025 = NULL;
--	opp110->regamma.rgb_oem = NULL;
--	opp110->regamma.rgb_user = NULL;
--	opp110->regamma.extra_points = 3;
--	opp110->regamma.use_half_points = false;
--	opp110->regamma.x_max1 = dal_fixed31_32_one;
--	opp110->regamma.x_max2 = dal_fixed31_32_from_int(2);
--	opp110->regamma.x_min = dal_fixed31_32_zero;
--	opp110->regamma.divider1 = dal_fixed31_32_from_fraction(3, 2);
--	opp110->regamma.divider2 = dal_fixed31_32_from_int(2);
--	opp110->regamma.divider3 = dal_fixed31_32_from_fraction(5, 2);
--
--	opp110->regamma.rgb_user = dm_alloc(
--		ctx,
--		sizeof(struct pwl_float_data) *
--		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
--	if (!opp110->regamma.rgb_user)
--		goto failure_1;
--
--	opp110->regamma.rgb_oem = dm_alloc(
--		ctx,
--		sizeof(struct pwl_float_data) *
--		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
--	if (!opp110->regamma.rgb_oem)
--		goto failure_2;
--
--	opp110->regamma.rgb_resulted = dm_alloc(
--		ctx,
--		sizeof(struct pwl_result_data) *
--		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
--	if (!opp110->regamma.rgb_resulted)
--		goto failure_3;
--
--	opp110->regamma.rgb_regamma = dm_alloc(
--		ctx,
--		sizeof(struct pwl_float_data_ex) *
--		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
--	if (!opp110->regamma.rgb_regamma)
--		goto failure_4;
--
--	opp110->regamma.coordinates_x = dm_alloc(
--		ctx,
--		sizeof(struct hw_x_point) *
--		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
--	if (!opp110->regamma.coordinates_x)
--		goto failure_5;
--
--	opp110->regamma.axis_x_256 = dm_alloc(
--		ctx,
--		sizeof(struct gamma_pixel) *
--		(MAX_LUT_ENTRY + opp110->regamma.extra_points));
--	if (!opp110->regamma.axis_x_256)
--		goto failure_6;
--
--	opp110->regamma.axis_x_1025 = dm_alloc(
--		ctx,
--		sizeof(struct gamma_pixel) *
--		(DX_GAMMA_RAMP_MAX + opp110->regamma.extra_points));
--	if (!opp110->regamma.axis_x_1025)
--		goto failure_7;
--
--	opp110->regamma.coeff128 = dm_alloc(
--		ctx,
--		sizeof(struct pixel_gamma_point) *
--		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
--	if (!opp110->regamma.coeff128)
--		goto failure_8;
--
--	opp110->regamma.coeff128_oem = dm_alloc(
--		ctx,
--		sizeof(struct pixel_gamma_point) *
--		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
--	if (!opp110->regamma.coeff128_oem)
--		goto failure_9;
--
--	opp110->regamma.coeff128_dx = dm_alloc(
--		ctx,
--		sizeof(struct pixel_gamma_point) *
--		(MAX_NUMBER_OF_ENTRIES + opp110->regamma.extra_points));
--	if (!opp110->regamma.coeff128_dx)
--		goto failure_10;
--
--	/* init palette */
--	{
--		uint32_t i = 0;
--
--		do {
--			opp110->regamma.saved_palette[i].red = (uint8_t)i;
--			opp110->regamma.saved_palette[i].green = (uint8_t)i;
--			opp110->regamma.saved_palette[i].blue = (uint8_t)i;
--
--			++i;
--		} while (i != MAX_LUT_ENTRY);
--	}
--
--	build_evenly_distributed_points(
--		opp110->regamma.axis_x_256,
--		MAX_LUT_ENTRY,
--		opp110->regamma.x_max1,
--		opp110->regamma.divider1,
--		opp110->regamma.divider2,
--		opp110->regamma.divider3);
--
--	build_evenly_distributed_points(
--		opp110->regamma.axis_x_1025,
--		DX_GAMMA_RAMP_MAX,
--		opp110->regamma.x_max1,
--		opp110->regamma.divider1,
--		opp110->regamma.divider2,
--		opp110->regamma.divider3);
--
--	return true;
--
--failure_10:
--	dm_free(ctx, opp110->regamma.coeff128_oem);
--failure_9:
--	dm_free(ctx, opp110->regamma.coeff128);
--failure_8:
--	dm_free(ctx, opp110->regamma.axis_x_1025);
--failure_7:
--	dm_free(ctx, opp110->regamma.axis_x_256);
--failure_6:
--	dm_free(ctx, opp110->regamma.coordinates_x);
--failure_5:
--	dm_free(ctx, opp110->regamma.rgb_regamma);
--failure_4:
--	dm_free(ctx, opp110->regamma.rgb_resulted);
--failure_3:
--	dm_free(ctx, opp110->regamma.rgb_oem);
--failure_2:
--	dm_free(ctx, opp110->regamma.rgb_user);
--failure_1:
--
- 	return true;
- }
- 
- void dce110_opp_destroy(struct output_pixel_processor **opp)
- {
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
- 	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
- 	*opp = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index e53eb74..3460e18 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -27,7 +27,9 @@
- 
- #include "dc_types.h"
- #include "inc/opp.h"
--#include "gamma_types.h"
-+#include "core_types.h"
-+
-+#include "gamma_types.h" /* decprecated */
- 
- struct gamma_parameters;
- 
-@@ -107,14 +109,11 @@ void dce110_opp_power_on_regamma_lut(
- 
- bool dce110_opp_set_regamma(
- 	struct output_pixel_processor *opp,
--	const struct gamma_ramp *ramp,
--	const struct gamma_parameters *params,
--	bool force_bypass);
-+	const struct regamma_params *params);
- 
--bool dce110_opp_map_legacy_and_regamma_hw_to_x_user(
-+void dce110_opp_power_on_regamma_lut(
- 	struct output_pixel_processor *opp,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params);
-+	bool power_on);
- 
- void dce110_opp_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index 32cf57d..f7a4bc2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -44,1724 +44,6 @@ enum {
- 
- };
- 
--struct curve_config {
--	uint32_t offset;
--	int8_t segments[MAX_REGIONS_NUMBER];
--	int8_t begin;
--};
--
--/* BASE */
--static bool find_software_points(
--	struct dce110_opp *opp110,
--	struct fixed31_32 hw_point,
--	enum channel_name channel,
--	uint32_t *index_to_start,
--	uint32_t *index_left,
--	uint32_t *index_right,
--	enum hw_point_position *pos)
--{
--	const uint32_t max_number =
--			RGB_256X3X16 + opp110->regamma.extra_points;
--
--	struct fixed31_32 left, right;
--
--	uint32_t i = *index_to_start;
--
--	while (i < max_number) {
--		if (channel == CHANNEL_NAME_RED) {
--			left = opp110->
--					regamma.axis_x_256[i].r;
--
--			if (i < max_number - 1)
--				right = opp110->
--					regamma.axis_x_256[i + 1].r;
--			else
--				right = opp110->
--					regamma.axis_x_256[max_number - 1].r;
--		} else if (channel == CHANNEL_NAME_GREEN) {
--			left = opp110->regamma.axis_x_256[i].g;
--
--			if (i < max_number - 1)
--				right = opp110->
--					regamma.axis_x_256[i + 1].g;
--			else
--				right = opp110->
--					regamma.axis_x_256[max_number - 1].g;
--		} else {
--			left = opp110->regamma.axis_x_256[i].b;
--
--			if (i < max_number - 1)
--				right = opp110->
--					regamma.axis_x_256[i + 1].b;
--			else
--				right = opp110->
--					regamma.axis_x_256[max_number - 1].b;
--		}
--
--		if (dal_fixed31_32_le(left, hw_point) &&
--			dal_fixed31_32_le(hw_point, right)) {
--			*index_to_start = i;
--			*index_left = i;
--
--			if (i < max_number - 1)
--				*index_right = i + 1;
--			else
--				*index_right = max_number - 1;
--
--			*pos = HW_POINT_POSITION_MIDDLE;
--
--			return true;
--		} else if ((i == *index_to_start) &&
--			dal_fixed31_32_le(hw_point, left)) {
--			*index_to_start = i;
--			*index_left = i;
--			*index_right = i;
--
--			*pos = HW_POINT_POSITION_LEFT;
--
--			return true;
--		} else if ((i == max_number - 1) &&
--			dal_fixed31_32_le(right, hw_point)) {
--			*index_to_start = i;
--			*index_left = i;
--			*index_right = i;
--
--			*pos = HW_POINT_POSITION_RIGHT;
--
--			return true;
--		}
--
--		++i;
--	}
--
--	return false;
--}
--
--static bool find_software_points_dx(
--	struct dce110_opp *opp110,
--	struct fixed31_32 hw_point,
--	enum channel_name channel,
--	uint32_t *index_to_start,
--	uint32_t *index_left,
--	uint32_t *index_right,
--	enum hw_point_position *pos)
--{
--	const uint32_t max_number = DX_GAMMA_RAMP_MAX +
--					opp110->regamma.extra_points;
--
--	struct fixed31_32 left, right;
--
--	uint32_t i = *index_to_start;
--
--	while (i < max_number) {
--		if (channel == CHANNEL_NAME_RED) {
--			left = opp110->regamma.axis_x_1025[i].r;
--
--			if (i < DX_GAMMA_RAMP_MAX - 1)
--				right = opp110->
--					regamma.axis_x_1025[i + 1].r;
--			else
--				right = opp110->
--				regamma.axis_x_1025[DX_GAMMA_RAMP_MAX-1].r;
--		} else if (channel == CHANNEL_NAME_GREEN) {
--			left = opp110->regamma.axis_x_1025[i].g;
--
--			if (i < DX_GAMMA_RAMP_MAX - 1)
--				right = opp110->
--					regamma.axis_x_1025[i + 1].g;
--			else
--				right = opp110->
--				regamma.axis_x_1025[DX_GAMMA_RAMP_MAX-1].g;
--		} else {
--			left = opp110->regamma.axis_x_1025[i].b;
--
--			if (i < DX_GAMMA_RAMP_MAX - 1)
--				right = opp110->
--					regamma.axis_x_1025[i + 1].b;
--			else
--				right = opp110->
--				regamma.axis_x_1025[DX_GAMMA_RAMP_MAX-1].b;
--		}
--
--		if (dal_fixed31_32_le(left, hw_point) &&
--			dal_fixed31_32_le(hw_point, right)) {
--			*index_to_start = i;
--			*index_left = i;
--
--			if (i < DX_GAMMA_RAMP_MAX - 1)
--				*index_right = i + 1;
--			else
--				*index_right = DX_GAMMA_RAMP_MAX - 1;
--
--			*pos = HW_POINT_POSITION_MIDDLE;
--
--			return true;
--		} else if ((i == *index_to_start) &&
--			dal_fixed31_32_le(hw_point, left)) {
--			*index_to_start = i;
--			*index_left = i;
--			*index_right = i;
--
--			*pos = HW_POINT_POSITION_LEFT;
--
--			return true;
--		} else if ((i == max_number - 1) &&
--			dal_fixed31_32_le(right, hw_point)) {
--			*index_to_start = i;
--			*index_left = i;
--			*index_right = i;
--
--			*pos = HW_POINT_POSITION_RIGHT;
--
--			return true;
--		}
--
--		++i;
--	}
--
--	return false;
--}
--
--static bool build_custom_gamma_mapping_coefficients_worker(
--	struct dce110_opp *opp110,
--	struct pixel_gamma_point *coeff,
--	enum channel_name channel,
--	uint32_t number_of_points,
--	enum pixel_format pixel_format)
--{
--	uint32_t i = 0;
--
--	while (i <= number_of_points) {
--		struct fixed31_32 coord_x;
--
--		uint32_t index_to_start = 0;
--		uint32_t index_left = 0;
--		uint32_t index_right = 0;
--
--		enum hw_point_position hw_pos;
--
--		struct gamma_point *point;
--
--		struct fixed31_32 left_pos;
--		struct fixed31_32 right_pos;
--
--		if (pixel_format == PIXEL_FORMAT_FP16)
--			coord_x = opp110->
--				regamma.coordinates_x[i].adjusted_x;
--		else if (channel == CHANNEL_NAME_RED)
--			coord_x = opp110->
--				regamma.coordinates_x[i].regamma_y_red;
--		else if (channel == CHANNEL_NAME_GREEN)
--			coord_x = opp110->
--				regamma.coordinates_x[i].regamma_y_green;
--		else
--			coord_x = opp110->
--				regamma.coordinates_x[i].regamma_y_blue;
--
--		if (!find_software_points(
--			opp110, coord_x, channel,
--			&index_to_start, &index_left, &index_right, &hw_pos)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (index_left >= RGB_256X3X16 +
--				opp110->regamma.extra_points) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (index_right >= RGB_256X3X16 +
--				opp110->regamma.extra_points) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (channel == CHANNEL_NAME_RED) {
--			point = &coeff[i].r;
--
--			left_pos = opp110->
--					regamma.axis_x_256[index_left].r;
--			right_pos = opp110->
--					regamma.axis_x_256[index_right].r;
--		} else if (channel == CHANNEL_NAME_GREEN) {
--			point = &coeff[i].g;
--
--			left_pos = opp110->
--					regamma.axis_x_256[index_left].g;
--			right_pos = opp110->
--					regamma.axis_x_256[index_right].g;
--		} else {
--			point = &coeff[i].b;
--
--			left_pos = opp110->
--					regamma.axis_x_256[index_left].b;
--			right_pos = opp110->
--					regamma.axis_x_256[index_right].b;
--		}
--
--		if (hw_pos == HW_POINT_POSITION_MIDDLE)
--			point->coeff = dal_fixed31_32_div(
--				dal_fixed31_32_sub(
--					coord_x,
--					left_pos),
--				dal_fixed31_32_sub(
--					right_pos,
--					left_pos));
--		else if (hw_pos == HW_POINT_POSITION_LEFT)
--			point->coeff = opp110->regamma.x_min;
--		else if (hw_pos == HW_POINT_POSITION_RIGHT)
--			point->coeff = opp110->regamma.x_max2;
--		else {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		point->left_index = index_left;
--		point->right_index = index_right;
--		point->pos = hw_pos;
--
--		++i;
--	}
--
--	return true;
--}
--
--static inline bool build_custom_gamma_mapping_coefficients(
--	struct dce110_opp *opp110,
--	enum channel_name channel,
--	uint32_t number_of_points,
--	enum pixel_format pixel_format)
--{
--	return build_custom_gamma_mapping_coefficients_worker(
--		opp110, opp110->regamma.coeff128, channel,
--		number_of_points, pixel_format);
--}
--
--static inline bool build_oem_custom_gamma_mapping_coefficients(
--	struct dce110_opp *opp110,
--	enum channel_name channel,
--	uint32_t number_of_points,
--	enum pixel_format pixel_format)
--{
--	return build_custom_gamma_mapping_coefficients_worker(
--		opp110, opp110->regamma.coeff128_oem, channel,
--		number_of_points, pixel_format);
--}
--
--static bool build_custom_dx_gamma_mapping_coefficients(
--	struct dce110_opp *opp110,
--	enum channel_name channel,
--	uint32_t number_of_points,
--	enum pixel_format pixel_format)
--{
--	uint32_t i = 0;
--
--	while (i <= number_of_points) {
--		struct fixed31_32 coord_x;
--
--		uint32_t index_to_start = 0;
--		uint32_t index_left = 0;
--		uint32_t index_right = 0;
--
--		enum hw_point_position hw_pos;
--
--		struct gamma_point *point;
--
--		struct fixed31_32 left_pos;
--		struct fixed31_32 right_pos;
--
--		if (pixel_format == PIXEL_FORMAT_FP16)
--			coord_x = opp110->
--			regamma.coordinates_x[i].adjusted_x;
--		else if (channel == CHANNEL_NAME_RED)
--			coord_x = opp110->
--			regamma.coordinates_x[i].regamma_y_red;
--		else if (channel == CHANNEL_NAME_GREEN)
--			coord_x = opp110->
--			regamma.coordinates_x[i].regamma_y_green;
--		else
--			coord_x = opp110->
--			regamma.coordinates_x[i].regamma_y_blue;
--
--		if (!find_software_points_dx(
--			opp110, coord_x, channel,
--			&index_to_start, &index_left, &index_right, &hw_pos)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (index_left >= DX_GAMMA_RAMP_MAX +
--				opp110->regamma.extra_points) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (index_right >= DX_GAMMA_RAMP_MAX +
--				opp110->regamma.extra_points) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (channel == CHANNEL_NAME_RED) {
--			point = &opp110->regamma.coeff128_dx[i].r;
--
--			left_pos = opp110->
--					regamma.axis_x_1025[index_left].r;
--			right_pos = opp110->
--					regamma.axis_x_1025[index_right].r;
--		} else if (channel == CHANNEL_NAME_GREEN) {
--			point = &opp110->regamma.coeff128_dx[i].g;
--
--			left_pos = opp110->
--					regamma.axis_x_1025[index_left].g;
--			right_pos = opp110->
--					regamma.axis_x_1025[index_right].g;
--		} else {
--			point = &opp110->regamma.coeff128_dx[i].b;
--
--			left_pos = opp110->
--					regamma.axis_x_1025[index_left].b;
--			right_pos = opp110->
--					regamma.axis_x_1025[index_right].b;
--		}
--
--		if (hw_pos == HW_POINT_POSITION_MIDDLE)
--			point->coeff = dal_fixed31_32_div(
--				dal_fixed31_32_sub(
--					coord_x,
--					left_pos),
--				dal_fixed31_32_sub(
--					right_pos,
--					left_pos));
--		else if (hw_pos == HW_POINT_POSITION_LEFT)
--			point->coeff = opp110->regamma.x_min;
--		else if (hw_pos == HW_POINT_POSITION_RIGHT)
--			point->coeff = opp110->regamma.x_max2;
--		else {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		point->left_index = index_left;
--		point->right_index = index_right;
--		point->pos = hw_pos;
--
--		++i;
--	}
--
--	return true;
--}
--
--static struct fixed31_32 calculate_mapped_value(
--	struct dce110_opp *opp110,
--	struct pwl_float_data *rgb,
--	const struct pixel_gamma_point *coeff,
--	enum channel_name channel,
--	uint32_t max_index)
--{
--	const struct gamma_point *point;
--
--	struct fixed31_32 result;
--
--	if (channel == CHANNEL_NAME_RED)
--		point = &coeff->r;
--	else if (channel == CHANNEL_NAME_GREEN)
--		point = &coeff->g;
--	else
--		point = &coeff->b;
--
--	if ((point->left_index < 0) || (point->left_index > max_index)) {
--		BREAK_TO_DEBUGGER();
--		return dal_fixed31_32_zero;
--	}
--
--	if ((point->right_index < 0) || (point->right_index > max_index)) {
--		BREAK_TO_DEBUGGER();
--		return dal_fixed31_32_zero;
--	}
--
--	if (point->pos == HW_POINT_POSITION_MIDDLE)
--		if (channel == CHANNEL_NAME_RED)
--			result = dal_fixed31_32_add(
--				dal_fixed31_32_mul(
--					point->coeff,
--					dal_fixed31_32_sub(
--						rgb[point->right_index].r,
--						rgb[point->left_index].r)),
--				rgb[point->left_index].r);
--		else if (channel == CHANNEL_NAME_GREEN)
--			result = dal_fixed31_32_add(
--				dal_fixed31_32_mul(
--					point->coeff,
--					dal_fixed31_32_sub(
--						rgb[point->right_index].g,
--						rgb[point->left_index].g)),
--				rgb[point->left_index].g);
--		else
--			result = dal_fixed31_32_add(
--				dal_fixed31_32_mul(
--					point->coeff,
--					dal_fixed31_32_sub(
--						rgb[point->right_index].b,
--						rgb[point->left_index].b)),
--				rgb[point->left_index].b);
--	else if (point->pos == HW_POINT_POSITION_LEFT) {
--		BREAK_TO_DEBUGGER();
--		result = opp110->regamma.x_min;
--	} else {
--		BREAK_TO_DEBUGGER();
--		result = opp110->regamma.x_max1;
--	}
--
--	return result;
--}
--
--static inline struct fixed31_32 calculate_regamma_user_mapped_value(
--	struct dce110_opp *opp110,
--	const struct pixel_gamma_point *coeff,
--	enum channel_name channel,
--	uint32_t max_index)
--{
--	return calculate_mapped_value(
--		opp110, opp110->regamma.rgb_oem,
--		coeff, channel, max_index);
--}
--
--static inline struct fixed31_32 calculate_user_mapped_value(
--	struct dce110_opp *opp110,
--	const struct pixel_gamma_point *coeff,
--	enum channel_name channel,
--	uint32_t max_index)
--{
--	return calculate_mapped_value(
--		opp110, opp110->regamma.rgb_user,
--		coeff, channel, max_index);
--}
--
--static inline struct fixed31_32 calculate_oem_mapped_value(
--	struct dce110_opp *opp110,
--	uint32_t index,
--	enum channel_name channel,
--	uint32_t max_index)
--{
--	return calculate_regamma_user_mapped_value(
--		opp110, opp110->regamma.coeff128_oem +
--		index, channel, max_index);
--}
--
--static void scale_oem_gamma(
--	struct dce110_opp *opp110,
--	const struct regamma_ramp *regamma_ramp)
--{
--	const uint16_t max_driver = 0xFFFF;
--	const uint16_t max_os = 0xFF00;
--
--	uint16_t scale = max_os;
--
--	uint32_t i;
--
--	struct pwl_float_data *rgb = opp110->regamma.rgb_oem;
--	struct pwl_float_data *rgb_last = rgb + RGB_256X3X16 - 1;
--
--	/* find OEM maximum */
--
--	i = 0;
--
--	do {
--		if ((regamma_ramp->gamma[i] > max_os) ||
--			(regamma_ramp->gamma[i + RGB_256X3X16] > max_os) ||
--			(regamma_ramp->gamma[i + 2 * RGB_256X3X16] > max_os)) {
--			scale = max_driver;
--			break;
--		}
--
--		++i;
--	} while (i != RGB_256X3X16);
--
--	/* scale */
--
--	i = 0;
--
--	do {
--		rgb->r = dal_fixed31_32_div_int(
--			dal_fixed31_32_from_int(
--				regamma_ramp->gamma[i]),
--			scale);
--		rgb->g = dal_fixed31_32_div_int(
--			dal_fixed31_32_from_int(
--				regamma_ramp->gamma[i + RGB_256X3X16]),
--			scale);
--		rgb->b = dal_fixed31_32_div_int(
--			dal_fixed31_32_from_int(
--				regamma_ramp->gamma[i + 2 * RGB_256X3X16]),
--			scale);
--
--		++rgb;
--		++i;
--	} while (i != RGB_256X3X16);
--
--	/* add 3 extra points, 2 physical plus 1 virtual */
--
--	rgb->r = dal_fixed31_32_mul(rgb_last->r,
--			opp110->regamma.divider1);
--	rgb->g = dal_fixed31_32_mul(rgb_last->g,
--			opp110->regamma.divider1);
--	rgb->b = dal_fixed31_32_mul(rgb_last->b,
--			opp110->regamma.divider1);
--
--	++rgb;
--
--	rgb->r = dal_fixed31_32_mul(rgb_last->r,
--			opp110->regamma.divider2);
--	rgb->g = dal_fixed31_32_mul(rgb_last->g,
--			opp110->regamma.divider2);
--	rgb->b = dal_fixed31_32_mul(rgb_last->b,
--			opp110->regamma.divider2);
--
--	++rgb;
--
--	rgb->r = dal_fixed31_32_mul(rgb_last->r,
--			opp110->regamma.divider3);
--	rgb->g = dal_fixed31_32_mul(rgb_last->g,
--			opp110->regamma.divider3);
--	rgb->b = dal_fixed31_32_mul(rgb_last->b,
--			opp110->regamma.divider3);
--}
--
--static inline void copy_rgb_regamma_to_coordinates_x(
--	struct dce110_opp *opp110)
--{
--	struct hw_x_point *coords = opp110->regamma.coordinates_x;
--	const struct pwl_float_data_ex *rgb_regamma =
--			opp110->regamma.rgb_regamma;
--
--	uint32_t i = 0;
--
--	while (i <= opp110->regamma.hw_points_num) {
--		coords->regamma_y_red = rgb_regamma->r;
--		coords->regamma_y_green = rgb_regamma->g;
--		coords->regamma_y_blue = rgb_regamma->b;
--
--		++coords;
--		++rgb_regamma;
--		++i;
--	}
--}
--
--static bool calculate_interpolated_hardware_curve(
--	struct dce110_opp *opp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	struct pwl_result_data *rgb_resulted =
--			opp110->regamma.rgb_resulted;
--
--	const struct pixel_gamma_point *coeff;
--	uint32_t max_entries = opp110->regamma.extra_points - 1;
--
--	uint32_t i = 0;
--
--	if (gamma_ramp->type == GAMMA_RAMP_RBG256X3X16) {
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_RED,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_GREEN,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_BLUE,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		coeff = opp110->regamma.coeff128;
--		max_entries += RGB_256X3X16;
--	} else if (gamma_ramp->type == GAMMA_RAMP_DXGI_1) {
--		if (!build_custom_dx_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_RED,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_dx_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_GREEN,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_dx_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_BLUE,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		coeff = opp110->regamma.coeff128_dx;
--		max_entries += DX_GAMMA_RAMP_MAX;
--	} else {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	while (i <= opp110->regamma.hw_points_num) {
--		rgb_resulted->red = calculate_user_mapped_value(
--			opp110, coeff, CHANNEL_NAME_RED, max_entries);
--		rgb_resulted->green = calculate_user_mapped_value(
--			opp110, coeff, CHANNEL_NAME_GREEN, max_entries);
--		rgb_resulted->blue = calculate_user_mapped_value(
--			opp110, coeff, CHANNEL_NAME_BLUE, max_entries);
--
--		++coeff;
--		++rgb_resulted;
--		++i;
--	}
--
--	return true;
--}
--
--static void map_standard_regamma_hw_to_x_user(
--	struct dce110_opp *opp110,
--	enum gamma_ramp_type type,
--	const struct gamma_parameters *params)
--{
--	struct pwl_result_data *rgb_resulted =
--			opp110->regamma.rgb_resulted;
--	const struct pwl_float_data_ex *rgb_regamma =
--			opp110->regamma.rgb_regamma;
--
--	uint32_t i = 0;
--
--	while (i <= opp110->regamma.hw_points_num) {
--		rgb_resulted->red = rgb_regamma->r;
--		rgb_resulted->green = rgb_regamma->g;
--		rgb_resulted->blue = rgb_regamma->b;
--
--		++rgb_resulted;
--		++rgb_regamma;
--		++i;
--	}
--}
--
--bool dce110_opp_map_legacy_and_regamma_hw_to_x_user(
--	struct output_pixel_processor *opp,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
--
--	if (params->regamma.features.bits.GAMMA_RAMP_ARRAY ||
--		params->regamma.features.bits.APPLY_DEGAMMA) {
--
--		const uint32_t max_entries =
--			RGB_256X3X16 + opp110->regamma.extra_points - 1;
--
--		const struct pixel_gamma_point *coeff =
--				opp110->regamma.coeff128;
--		struct pwl_result_data *rgb_resulted =
--				opp110->regamma.rgb_resulted;
--
--		uint32_t i = 0;
--
--		scale_oem_gamma(opp110, &params->regamma.regamma_ramp);
--
--		copy_rgb_regamma_to_coordinates_x(opp110);
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_RED,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_GREEN,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_BLUE,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		while (i <= opp110->regamma.hw_points_num) {
--			rgb_resulted->red =
--				calculate_regamma_user_mapped_value(opp110,
--					coeff,
--					CHANNEL_NAME_RED, max_entries);
--			rgb_resulted->green =
--				calculate_regamma_user_mapped_value(opp110,
--					coeff,
--					CHANNEL_NAME_GREEN, max_entries);
--			rgb_resulted->blue =
--				calculate_regamma_user_mapped_value(opp110,
--					coeff,
--					CHANNEL_NAME_BLUE, max_entries);
--
--			++coeff;
--			++rgb_resulted;
--			++i;
--		}
--	} else
--		map_standard_regamma_hw_to_x_user(opp110,
--				gamma_ramp->type,
--				params);
--
--	return true;
--}
--
--static bool map_regamma_hw_to_x_user(
--	struct dce110_opp *opp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	/* setup to spare calculated ideal regamma values */
--	if (params->regamma.features.bits.GAMMA_RAMP_ARRAY ||
--		params->regamma.features.bits.APPLY_DEGAMMA) {
--
--		const uint32_t max_entries =
--			RGB_256X3X16 + opp110->regamma.extra_points - 1;
--
--		const struct pixel_gamma_point *coeff =
--				opp110->regamma.coeff128;
--		struct hw_x_point *coords =
--				opp110->regamma.coordinates_x;
--
--		uint32_t i = 0;
--
--		scale_oem_gamma(opp110, &params->regamma.regamma_ramp);
--
--		copy_rgb_regamma_to_coordinates_x(opp110);
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_RED,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_GREEN,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_BLUE,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		while (i <= opp110->regamma.hw_points_num) {
--			coords->regamma_y_red =
--				calculate_regamma_user_mapped_value(opp110,
--					coeff,
--					CHANNEL_NAME_RED, max_entries);
--			coords->regamma_y_green =
--				calculate_regamma_user_mapped_value(opp110,
--					coeff,
--					CHANNEL_NAME_GREEN, max_entries);
--			coords->regamma_y_blue =
--				calculate_regamma_user_mapped_value(opp110,
--					coeff,
--					CHANNEL_NAME_BLUE, max_entries);
--
--			++coeff;
--			++coords;
--			++i;
--		}
--	} else {
--		copy_rgb_regamma_to_coordinates_x(opp110);
--	}
--
--	return calculate_interpolated_hardware_curve(opp110, gamma_ramp,
--		params);
--}
--
--static void build_regamma_coefficients(
--	const struct regamma_lut *regamma,
--	bool is_degamma_srgb,
--	struct gamma_coefficients *coefficients)
--{
--	/* sRGB should apply 2.4 */
--	static const int32_t numerator01[3] = { 31308, 31308, 31308 };
--	static const int32_t numerator02[3] = { 12920, 12920, 12920 };
--	static const int32_t numerator03[3] = { 55, 55, 55 };
--	static const int32_t numerator04[3] = { 55, 55, 55 };
--	static const int32_t numerator05[3] = { 2400, 2400, 2400 };
--
--	/* Non-sRGB should apply 2.2 */
--	static const int32_t numerator11[3] = { 180000, 180000, 180000 };
--	static const int32_t numerator12[3] = { 4500, 4500, 4500 };
--	static const int32_t numerator13[3] = { 99, 99, 99 };
--	static const int32_t numerator14[3] = { 99, 99, 99 };
--	static const int32_t numerator15[3] = { 2200, 2200, 2200 };
--
--	const int32_t *numerator1;
--	const int32_t *numerator2;
--	const int32_t *numerator3;
--	const int32_t *numerator4;
--	const int32_t *numerator5;
--
--	uint32_t i = 0;
--
--	if (!regamma->features.bits.GAMMA_RAMP_ARRAY) {
--		numerator1 = regamma->gamma_coeff.a0;
--		numerator2 = regamma->gamma_coeff.a1;
--		numerator3 = regamma->gamma_coeff.a2;
--		numerator4 = regamma->gamma_coeff.a3;
--		numerator5 = regamma->gamma_coeff.gamma;
--	} else if (is_degamma_srgb) {
--		numerator1 = numerator01;
--		numerator2 = numerator02;
--		numerator3 = numerator03;
--		numerator4 = numerator04;
--		numerator5 = numerator05;
--	} else {
--		numerator1 = numerator11;
--		numerator2 = numerator12;
--		numerator3 = numerator13;
--		numerator4 = numerator14;
--		numerator5 = numerator15;
--	}
--
--	do {
--		coefficients->a0[i] = dal_fixed31_32_from_fraction(
--			numerator1[i], 10000000);
--		coefficients->a1[i] = dal_fixed31_32_from_fraction(
--			numerator2[i], 1000);
--		coefficients->a2[i] = dal_fixed31_32_from_fraction(
--			numerator3[i], 1000);
--		coefficients->a3[i] = dal_fixed31_32_from_fraction(
--			numerator4[i], 1000);
--		coefficients->user_gamma[i] = dal_fixed31_32_from_fraction(
--			numerator5[i], 1000);
--
--		++i;
--	} while (i != ARRAY_SIZE(regamma->gamma_coeff.a0));
--}
--
--static struct fixed31_32 translate_from_linear_space(
--	struct fixed31_32 arg,
--	struct fixed31_32 a0,
--	struct fixed31_32 a1,
--	struct fixed31_32 a2,
--	struct fixed31_32 a3,
--	struct fixed31_32 gamma)
--{
--	const struct fixed31_32 one = dal_fixed31_32_from_int(1);
--
--	if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0)))
--		return dal_fixed31_32_sub(
--			a2,
--			dal_fixed31_32_mul(
--				dal_fixed31_32_add(
--					one,
--					a3),
--				dal_fixed31_32_pow(
--					dal_fixed31_32_neg(arg),
--					dal_fixed31_32_recip(gamma))));
--	else if (dal_fixed31_32_le(a0, arg))
--		return dal_fixed31_32_sub(
--			dal_fixed31_32_mul(
--				dal_fixed31_32_add(
--					one,
--					a3),
--				dal_fixed31_32_pow(
--					arg,
--					dal_fixed31_32_recip(gamma))),
--			a2);
--	else
--		return dal_fixed31_32_mul(
--			arg,
--			a1);
--}
--
--static inline struct fixed31_32 translate_from_linear_space_ex(
--	struct fixed31_32 arg,
--	struct gamma_coefficients *coeff,
--	uint32_t color_index)
--{
--	return translate_from_linear_space(
--		arg,
--		coeff->a0[color_index],
--		coeff->a1[color_index],
--		coeff->a2[color_index],
--		coeff->a3[color_index],
--		coeff->user_gamma[color_index]);
--}
--
--static bool build_regamma_curve(
--	struct dce110_opp *opp110,
--	const struct gamma_parameters *params)
--{
--	struct pwl_float_data_ex *rgb = opp110->regamma.rgb_regamma;
--
--	uint32_t i;
--
--	struct gamma_coefficients coeff;
--
--	struct hw_x_point *coord_x =
--		opp110->regamma.coordinates_x;
--
--	build_regamma_coefficients(
--		&params->regamma,
--		params->regamma.features.bits.GRAPHICS_DEGAMMA_SRGB,
--		&coeff);
--
--	/* Use opp110->regamma.coordinates_x to retrieve
--	 * coordinates chosen base on given user curve (future task).
--	 * The x values are exponentially distributed and currently
--	 * it is hard-coded, the user curve shape is ignored.
--	 * The future task is to recalculate opp110-
--	 * regamma.coordinates_x based on input/user curve,
--	 * translation from 256/1025 to 128 pwl points.
--	 */
--
--	i = 0;
--
--	while (i != opp110->regamma.hw_points_num + 1) {
--		rgb->r = translate_from_linear_space_ex(
--			coord_x->adjusted_x, &coeff, 0);
--		rgb->g = translate_from_linear_space_ex(
--			coord_x->adjusted_x, &coeff, 1);
--		rgb->b = translate_from_linear_space_ex(
--			coord_x->adjusted_x, &coeff, 2);
--
--		++coord_x;
--		++rgb;
--		++i;
--	}
--
--	if (params->regamma.features.bits.GAMMA_RAMP_ARRAY &&
--			!params->regamma.features.bits.APPLY_DEGAMMA) {
--		const uint32_t max_entries =
--			RGB_256X3X16 + opp110->regamma.extra_points - 1;
--
--		/* interpolate between 256 input points and output 185 points */
--
--		scale_oem_gamma(opp110, &params->regamma.regamma_ramp);
--
--		if (!build_oem_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_RED,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_oem_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_GREEN,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!build_oem_custom_gamma_mapping_coefficients(
--			opp110, CHANNEL_NAME_BLUE,
--			opp110->regamma.hw_points_num,
--			params->surface_pixel_format)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		i = 0;
--
--		while (i != opp110->regamma.hw_points_num + 1) {
--			rgb->r = calculate_oem_mapped_value(
--				opp110, i, CHANNEL_NAME_RED, max_entries);
--			rgb->g = calculate_oem_mapped_value(
--				opp110, i, CHANNEL_NAME_GREEN, max_entries);
--			rgb->b = calculate_oem_mapped_value(
--				opp110, i, CHANNEL_NAME_BLUE, max_entries);
--			++rgb;
--			++i;
--		}
--	}
--
--	return true;
--}
--
--static void build_new_custom_resulted_curve(
--	struct dce110_opp *opp110,
--	const struct gamma_parameters *params)
--{
--	struct pwl_result_data *rgb = opp110->regamma.rgb_resulted;
--	struct pwl_result_data *rgb_plus_1 = rgb + 1;
--
--	uint32_t i;
--
--	i = 0;
--
--	while (i != opp110->regamma.hw_points_num + 1) {
--		rgb->red = dal_fixed31_32_clamp(
--			rgb->red, opp110->regamma.x_min,
--			opp110->regamma.x_max1);
--		rgb->green = dal_fixed31_32_clamp(
--			rgb->green, opp110->regamma.x_min,
--			opp110->regamma.x_max1);
--		rgb->blue = dal_fixed31_32_clamp(
--			rgb->blue, opp110->regamma.x_min,
--			opp110->regamma.x_max1);
--
--		++rgb;
--		++i;
--	}
--
--	rgb = opp110->regamma.rgb_resulted;
--
--	i = 1;
--
--	while (i != opp110->regamma.hw_points_num + 1) {
--		if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
--			rgb_plus_1->red = rgb->red;
--		if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
--			rgb_plus_1->green = rgb->green;
--		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
--			rgb_plus_1->blue = rgb->blue;
--
--		rgb->delta_red = dal_fixed31_32_sub(
--			rgb_plus_1->red,
--			rgb->red);
--		rgb->delta_green = dal_fixed31_32_sub(
--			rgb_plus_1->green,
--			rgb->green);
--		rgb->delta_blue = dal_fixed31_32_sub(
--			rgb_plus_1->blue,
--			rgb->blue);
--
--		++rgb_plus_1;
--		++rgb;
--		++i;
--	}
--}
--
--static bool rebuild_curve_configuration_magic(
--	struct dce110_opp *opp110)
--{
--	const struct fixed31_32 magic_number =
--		dal_fixed31_32_from_fraction(249, 1000);
--
--	struct fixed31_32 y_r;
--	struct fixed31_32 y_g;
--	struct fixed31_32 y_b;
--
--	struct fixed31_32 y1_min;
--	struct fixed31_32 y2_max;
--	struct fixed31_32 y3_max;
--
--	y_r = opp110->regamma.rgb_resulted[0].red;
--	y_g = opp110->regamma.rgb_resulted[0].green;
--	y_b = opp110->regamma.rgb_resulted[0].blue;
--
--	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
--
--	opp110->regamma.arr_points[0].x =
--			opp110->regamma.coordinates_x[0].adjusted_x;
--	opp110->regamma.arr_points[0].y = y1_min;
--	opp110->regamma.arr_points[0].slope = dal_fixed31_32_div(
--		opp110->regamma.arr_points[0].y,
--		opp110->regamma.arr_points[0].x);
--
--	opp110->regamma.arr_points[1].x = dal_fixed31_32_add(
--		opp110->regamma.coordinates_x
--		[opp110->regamma.hw_points_num - 1].adjusted_x,
--		magic_number);
--
--	opp110->regamma.arr_points[2].x =
--			opp110->regamma.arr_points[1].x;
--
--	y_r = opp110->regamma.rgb_resulted
--			[opp110->regamma.hw_points_num - 1].red;
--	y_g = opp110->regamma.rgb_resulted
--			[opp110->regamma.hw_points_num - 1].green;
--	y_b = opp110->regamma.rgb_resulted
--			[opp110->regamma.hw_points_num - 1].blue;
--
--	y2_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
--
--	opp110->regamma.arr_points[1].y = y2_max;
--
--	y_r = opp110->regamma.rgb_resulted
--			[opp110->regamma.hw_points_num].red;
--	y_g = opp110->regamma.rgb_resulted
--			[opp110->regamma.hw_points_num].green;
--	y_b = opp110->regamma.rgb_resulted
--			[opp110->regamma.hw_points_num].blue;
--
--	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
--
--	opp110->regamma.arr_points[2].y = y3_max;
--
--	opp110->regamma.arr_points[2].slope = dal_fixed31_32_one;
--
--	return true;
--}
--
--static bool build_custom_float(
--	struct fixed31_32 value,
--	const struct custom_float_format *format,
--	bool *negative,
--	uint32_t *mantissa,
--	uint32_t *exponenta)
--{
--	uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
--
--	const struct fixed31_32 mantissa_constant_plus_max_fraction =
--		dal_fixed31_32_from_fraction(
--			(1LL << (format->mantissa_bits + 1)) - 1,
--			1LL << format->mantissa_bits);
--
--	struct fixed31_32 mantiss;
--
--	if (dal_fixed31_32_eq(
--		value,
--		dal_fixed31_32_zero)) {
--		*negative = false;
--		*mantissa = 0;
--		*exponenta = 0;
--		return true;
--	}
--
--	if (dal_fixed31_32_lt(
--		value,
--		dal_fixed31_32_zero)) {
--		*negative = format->sign;
--		value = dal_fixed31_32_neg(value);
--	} else {
--		*negative = false;
--	}
--
--	if (dal_fixed31_32_lt(
--		value,
--		dal_fixed31_32_one)) {
--		uint32_t i = 1;
--
--		do {
--			value = dal_fixed31_32_shl(value, 1);
--			++i;
--		} while (dal_fixed31_32_lt(
--			value,
--			dal_fixed31_32_one));
--
--		--i;
--
--		if (exp_offset <= i) {
--			*mantissa = 0;
--			*exponenta = 0;
--			return true;
--		}
--
--		*exponenta = exp_offset - i;
--	} else if (dal_fixed31_32_le(
--		mantissa_constant_plus_max_fraction,
--		value)) {
--		uint32_t i = 1;
--
--		do {
--			value = dal_fixed31_32_shr(value, 1);
--			++i;
--		} while (dal_fixed31_32_lt(
--			mantissa_constant_plus_max_fraction,
--			value));
--
--		*exponenta = exp_offset + i - 1;
--	} else {
--		*exponenta = exp_offset;
--	}
--
--	mantiss = dal_fixed31_32_sub(
--		value,
--		dal_fixed31_32_one);
--
--	if (dal_fixed31_32_lt(
--			mantiss,
--			dal_fixed31_32_zero) ||
--		dal_fixed31_32_lt(
--			dal_fixed31_32_one,
--			mantiss))
--		mantiss = dal_fixed31_32_zero;
--	else
--		mantiss = dal_fixed31_32_shl(
--			mantiss,
--			format->mantissa_bits);
--
--	*mantissa = dal_fixed31_32_floor(mantiss);
--
--	return true;
--}
--
--static bool setup_custom_float(
--	const struct custom_float_format *format,
--	bool negative,
--	uint32_t mantissa,
--	uint32_t exponenta,
--	uint32_t *result)
--{
--	uint32_t i = 0;
--	uint32_t j = 0;
--
--	uint32_t value = 0;
--
--	/* verification code:
--	 * once calculation is ok we can remove it */
--
--	const uint32_t mantissa_mask =
--		(1 << (format->mantissa_bits + 1)) - 1;
--
--	const uint32_t exponenta_mask =
--		(1 << (format->exponenta_bits + 1)) - 1;
--
--	if (mantissa & ~mantissa_mask) {
--		BREAK_TO_DEBUGGER();
--		mantissa = mantissa_mask;
--	}
--
--	if (exponenta & ~exponenta_mask) {
--		BREAK_TO_DEBUGGER();
--		exponenta = exponenta_mask;
--	}
--
--	/* end of verification code */
--
--	while (i < format->mantissa_bits) {
--		uint32_t mask = 1 << i;
--
--		if (mantissa & mask)
--			value |= mask;
--
--		++i;
--	}
--
--	while (j < format->exponenta_bits) {
--		uint32_t mask = 1 << j;
--
--		if (exponenta & mask)
--			value |= mask << i;
--
--		++j;
--	}
--
--	if (negative && format->sign)
--		value |= 1 << (i + j);
--
--	*result = value;
--
--	return true;
--}
--
--static bool convert_to_custom_float_format(
--	struct fixed31_32 value,
--	const struct custom_float_format *format,
--	uint32_t *result)
--{
--	uint32_t mantissa;
--	uint32_t exponenta;
--	bool negative;
--
--	return build_custom_float(
--		value, format, &negative, &mantissa, &exponenta) &&
--	setup_custom_float(
--		format, negative, mantissa, exponenta, result);
--}
--
--static bool convert_to_custom_float_format_ex(
--	struct fixed31_32 value,
--	const struct custom_float_format *format,
--	struct custom_float_value *result)
--{
--	return build_custom_float(
--		value, format,
--		&result->negative, &result->mantissa, &result->exponenta) &&
--	setup_custom_float(
--		format, result->negative, result->mantissa, result->exponenta,
--		&result->value);
--}
--
--static bool convert_to_custom_float(
--	struct dce110_opp *opp110)
--{
--	struct custom_float_format fmt;
--
--	struct pwl_result_data *rgb = opp110->regamma.rgb_resulted;
--
--	uint32_t i = 0;
--
--	fmt.exponenta_bits = 6;
--	fmt.mantissa_bits = 12;
--	fmt.sign = true;
--
--	if (!convert_to_custom_float_format(
--		opp110->regamma.arr_points[0].x,
--		&fmt,
--		&opp110->regamma.arr_points[0].custom_float_x)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	if (!convert_to_custom_float_format(
--		opp110->regamma.arr_points[0].offset,
--		&fmt,
--		&opp110->regamma.arr_points[0].custom_float_offset)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	if (!convert_to_custom_float_format(
--		opp110->regamma.arr_points[0].slope,
--		&fmt,
--		&opp110->regamma.arr_points[0].custom_float_slope)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	fmt.mantissa_bits = 10;
--	fmt.sign = false;
--
--	if (!convert_to_custom_float_format(
--		opp110->regamma.arr_points[1].x,
--		&fmt,
--		&opp110->regamma.arr_points[1].custom_float_x)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	if (!convert_to_custom_float_format(
--		opp110->regamma.arr_points[1].y,
--		&fmt,
--		&opp110->regamma.arr_points[1].custom_float_y)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	if (!convert_to_custom_float_format(
--		opp110->regamma.arr_points[2].slope,
--		&fmt,
--		&opp110->regamma.arr_points[2].custom_float_slope)) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	fmt.mantissa_bits = 12;
--	fmt.sign = true;
--
--	while (i != opp110->regamma.hw_points_num) {
--		if (!convert_to_custom_float_format(
--			rgb->red,
--			&fmt,
--			&rgb->red_reg)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!convert_to_custom_float_format(
--			rgb->green,
--			&fmt,
--			&rgb->green_reg)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!convert_to_custom_float_format(
--			rgb->blue,
--			&fmt,
--			&rgb->blue_reg)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!convert_to_custom_float_format(
--			rgb->delta_red,
--			&fmt,
--			&rgb->delta_red_reg)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!convert_to_custom_float_format(
--			rgb->delta_green,
--			&fmt,
--			&rgb->delta_green_reg)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		if (!convert_to_custom_float_format(
--			rgb->delta_blue,
--			&fmt,
--			&rgb->delta_blue_reg)) {
--			BREAK_TO_DEBUGGER();
--			return false;
--		}
--
--		++rgb;
--		++i;
--	}
--
--	return true;
--}
--
--static bool round_custom_float_6_12(
--	struct hw_x_point *x)
--{
--	struct custom_float_format fmt;
--
--	struct custom_float_value value;
--
--	fmt.exponenta_bits = 6;
--	fmt.mantissa_bits = 12;
--	fmt.sign = true;
--
--	if (!convert_to_custom_float_format_ex(
--		x->x, &fmt, &value))
--		return false;
--
--	x->adjusted_x = x->x;
--
--	if (value.mantissa) {
--		BREAK_TO_DEBUGGER();
--
--		return false;
--	}
--
--	return true;
--}
--
--static bool build_hw_curve_configuration(
--	const struct curve_config *curve_config,
--	struct gamma_curve *gamma_curve,
--	struct curve_points *curve_points,
--	struct hw_x_point *points,
--	uint32_t *number_of_points)
--{
--	const int8_t max_regions_number = ARRAY_SIZE(curve_config->segments);
--
--	int8_t i;
--
--	uint8_t segments_calculation[8] = { 0 };
--
--	struct fixed31_32 region1 = dal_fixed31_32_zero;
--	struct fixed31_32 region2;
--	struct fixed31_32 increment;
--
--	uint32_t index = 0;
--	uint32_t segments = 0;
--	uint32_t max_number;
--
--	bool result = false;
--
--	if (!number_of_points) {
--		BREAK_TO_DEBUGGER();
--		return false;
--	}
--
--	max_number = *number_of_points;
--
--	i = 0;
--
--	while (i != max_regions_number) {
--		gamma_curve[i].offset = 0;
--		gamma_curve[i].segments_num = 0;
--
--		++i;
--	}
--
--	i = 0;
--
--	while (i != max_regions_number) {
--		/* number should go in uninterruptible sequence */
--		if (curve_config->segments[i] == -1)
--			break;
--
--		ASSERT(curve_config->segments[i] >= 0);
--
--		segments += (1 << curve_config->segments[i]);
--
--		++i;
--	}
--
--	if (segments > max_number) {
--		BREAK_TO_DEBUGGER();
--	} else {
--		int32_t divisor;
--		uint32_t offset = 0;
--		int8_t begin = curve_config->begin;
--		int32_t region_number = 0;
--
--		i = begin;
--
--		while ((index < max_number) &&
--			(region_number < max_regions_number) &&
--			(i <= 1)) {
--			int32_t j = 0;
--
--			segments = curve_config->segments[region_number];
--			divisor = 1 << segments;
--
--			if (segments == -1) {
--				if (i > 0) {
--					region1 = dal_fixed31_32_shl(
--						dal_fixed31_32_one,
--						i - 1);
--					region2 = dal_fixed31_32_shl(
--						dal_fixed31_32_one,
--						i);
--				} else {
--					region1 = dal_fixed31_32_shr(
--						dal_fixed31_32_one,
--						-(i - 1));
--					region2 = dal_fixed31_32_shr(
--						dal_fixed31_32_one,
--						-i);
--				}
--
--				break;
--			}
--
--			if (i > -1) {
--				region1 = dal_fixed31_32_shl(
--					dal_fixed31_32_one,
--					i);
--				region2 = dal_fixed31_32_shl(
--					dal_fixed31_32_one,
--					i + 1);
--			} else {
--				region1 = dal_fixed31_32_shr(
--					dal_fixed31_32_one,
--					-i);
--				region2 = dal_fixed31_32_shr(
--					dal_fixed31_32_one,
--					-(i + 1));
--			}
--
--			gamma_curve[region_number].offset = offset;
--			gamma_curve[region_number].segments_num = segments;
--
--			offset += divisor;
--
--			++segments_calculation[segments];
--
--			increment = dal_fixed31_32_div_int(
--				dal_fixed31_32_sub(
--					region2,
--					region1),
--				divisor);
--
--			points[index].x = region1;
--
--			round_custom_float_6_12(points + index);
--
--			++index;
--			++region_number;
--
--			while ((index < max_number) && (j < divisor - 1)) {
--				region1 = dal_fixed31_32_add(
--					region1,
--					increment);
--
--				points[index].x = region1;
--				points[index].adjusted_x = region1;
--
--				++index;
--				++j;
--			}
--
--			++i;
--		}
--
--		points[index].x = region1;
--
--		round_custom_float_6_12(points + index);
--
--		*number_of_points = index;
--
--		result = true;
--	}
--
--	curve_points[0].x = points[0].adjusted_x;
--	curve_points[0].offset = dal_fixed31_32_zero;
--
--	curve_points[1].x = points[index - 1].adjusted_x;
--	curve_points[1].offset = dal_fixed31_32_zero;
--
--	curve_points[2].x = points[index].adjusted_x;
--	curve_points[2].offset = dal_fixed31_32_zero;
--
--	return result;
--}
--
--static bool setup_distribution_points(
--	struct dce110_opp *opp110)
--{
--	uint32_t hw_points_num = MAX_PWL_ENTRY * 2;
--
--	struct curve_config cfg;
--
--	cfg.offset = 0;
--
--		cfg.segments[0] = 3;
--		cfg.segments[1] = 4;
--		cfg.segments[2] = 4;
--		cfg.segments[3] = 4;
--		cfg.segments[4] = 4;
--		cfg.segments[5] = 4;
--		cfg.segments[6] = 4;
--		cfg.segments[7] = 4;
--		cfg.segments[8] = 5;
--		cfg.segments[9] = 5;
--		cfg.segments[10] = 0;
--		cfg.segments[11] = -1;
--		cfg.segments[12] = -1;
--		cfg.segments[13] = -1;
--		cfg.segments[14] = -1;
--		cfg.segments[15] = -1;
--
--	cfg.begin = -10;
--
--	if (!build_hw_curve_configuration(
--		&cfg, opp110->regamma.arr_curve_points,
--		opp110->regamma.arr_points,
--		opp110->regamma.coordinates_x, &hw_points_num)) {
--		ASSERT_CRITICAL(false);
--		return false;
--	}
--
--	opp110->regamma.hw_points_num = hw_points_num;
--
--	return true;
--}
--
--
- /*
-  *****************************************************************************
-  *  Function: regamma_config_regions_and_segments
-@@ -1779,15 +61,16 @@ static bool setup_distribution_points(
-  *****************************************************************************
-  */
- static void regamma_config_regions_and_segments(
--	struct dce110_opp *opp110)
-+	struct dce110_opp *opp110,
-+	const struct regamma_params *params)
- {
--	struct gamma_curve *curve;
-+	const struct gamma_curve *curve;
- 	uint32_t value = 0;
- 
- 	{
- 		set_reg_field_value(
- 			value,
--			opp110->regamma.arr_points[0].custom_float_x,
-+			params->arr_points[0].custom_float_x,
- 			REGAMMA_CNTLA_START_CNTL,
- 			REGAMMA_CNTLA_EXP_REGION_START);
- 
-@@ -1805,7 +88,7 @@ static void regamma_config_regions_and_segments(
- 		value = 0;
- 		set_reg_field_value(
- 			value,
--			opp110->regamma.arr_points[0].custom_float_slope,
-+			params->arr_points[0].custom_float_slope,
- 			REGAMMA_CNTLA_SLOPE_CNTL,
- 			REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE);
- 
-@@ -1816,7 +99,7 @@ static void regamma_config_regions_and_segments(
- 		value = 0;
- 		set_reg_field_value(
- 			value,
--			opp110->regamma.arr_points[1].custom_float_x,
-+			params->arr_points[1].custom_float_x,
- 			REGAMMA_CNTLA_END_CNTL1,
- 			REGAMMA_CNTLA_EXP_REGION_END);
- 
-@@ -1827,13 +110,13 @@ static void regamma_config_regions_and_segments(
- 		value = 0;
- 		set_reg_field_value(
- 			value,
--			opp110->regamma.arr_points[2].custom_float_slope,
-+			params->arr_points[2].custom_float_slope,
- 			REGAMMA_CNTLA_END_CNTL2,
- 			REGAMMA_CNTLA_EXP_REGION_END_BASE);
- 
- 		set_reg_field_value(
- 			value,
--			opp110->regamma.arr_points[1].custom_float_y,
-+			params->arr_points[1].custom_float_y,
- 			REGAMMA_CNTLA_END_CNTL2,
- 			REGAMMA_CNTLA_EXP_REGION_END_SLOPE);
- 
-@@ -1841,7 +124,7 @@ static void regamma_config_regions_and_segments(
- 			DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value);
- 	}
- 
--	curve = opp110->regamma.arr_curve_points;
-+	curve = params->arr_curve_points;
- 
- 	{
- 		value = 0;
-@@ -2102,7 +385,7 @@ static void regamma_config_regions_and_segments(
- 
- static void program_pwl(
- 	struct dce110_opp *opp110,
--	const struct gamma_parameters *params)
-+	const struct regamma_params *params)
- {
- 	uint32_t value;
- 
-@@ -2110,6 +393,18 @@ static void program_pwl(
- 		uint8_t max_tries = 10;
- 		uint8_t counter = 0;
- 
-+		value = dm_read_reg(opp110->base.ctx,
-+				DCP_REG(mmREGAMMA_CONTROL));
-+
-+		set_reg_field_value(
-+			value,
-+			3,
-+			REGAMMA_CONTROL,
-+			GRPH_REGAMMA_MODE);
-+
-+		dm_write_reg(opp110->base.ctx, DCP_REG(mmREGAMMA_CONTROL),
-+				value);
-+
- 		/* Power on LUT memory */
- 		value = dm_read_reg(opp110->base.ctx,
- 				DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-@@ -2168,10 +463,9 @@ static void program_pwl(
- 
- 		uint32_t i = 0;
- 
--		struct pwl_result_data *rgb =
--				opp110->regamma.rgb_resulted;
-+		const struct pwl_result_data *rgb = params->rgb_resulted;
- 
--		while (i != opp110->regamma.hw_points_num) {
-+		while (i != params->hw_points_num) {
- 			dm_write_reg(opp110->base.ctx, addr, rgb->red_reg);
- 			dm_write_reg(opp110->base.ctx, addr, rgb->green_reg);
- 			dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
-@@ -2200,6 +494,22 @@ static void program_pwl(
- 	dm_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
- 
-+
-+bool dce110_opp_set_regamma(
-+	struct output_pixel_processor *opp,
-+	const struct regamma_params *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	/* Setup regions */
-+	regamma_config_regions_and_segments(opp110, params);
-+
-+	/* Program PWL */
-+	program_pwl(opp110, params);
-+
-+	return true;
-+}
-+
- void dce110_opp_power_on_regamma_lut(
- 	struct output_pixel_processor *opp,
- 	bool power_on)
-@@ -2223,252 +533,3 @@ void dce110_opp_power_on_regamma_lut(
- 
- 	dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
--
--static bool scale_gamma(
--	struct dce110_opp *opp110,
--	const struct gamma_ramp *gamma_ramp,
--	const struct gamma_parameters *params)
--{
--	const struct gamma_ramp_rgb256x3x16 *gamma;
--	bool use_palette = params->surface_pixel_format == PIXEL_FORMAT_INDEX8;
--
--	const uint16_t max_driver = 0xFFFF;
--	const uint16_t max_os = 0xFF00;
--
--	uint16_t scaler = max_os;
--
--	uint32_t i;
--
--	struct dev_c_lut *palette = opp110->regamma.saved_palette;
--
--	struct pwl_float_data *rgb = opp110->regamma.rgb_user;
--	struct pwl_float_data *rgb_last = rgb + RGB_256X3X16 - 1;
--
--	if (gamma_ramp->type == GAMMA_RAMP_RBG256X3X16)
--		gamma = &gamma_ramp->gamma_ramp_rgb256x3x16;
--	else
--		return false; /* invalid option */
--
--	i = 0;
--
--	do {
--		if ((gamma->red[i] > max_os) ||
--			(gamma->green[i] > max_os) ||
--			(gamma->blue[i] > max_os)) {
--			scaler = max_driver;
--			break;
--		}
--		++i;
--	} while (i != RGB_256X3X16);
--
--	i = 0;
--
--	if (use_palette)
--		do {
--			rgb->r = dal_fixed31_32_from_fraction(
--				gamma->red[palette->red], scaler);
--			rgb->g = dal_fixed31_32_from_fraction(
--				gamma->green[palette->green], scaler);
--			rgb->b = dal_fixed31_32_from_fraction(
--				gamma->blue[palette->blue], scaler);
--
--			++palette;
--			++rgb;
--			++i;
--		} while (i != RGB_256X3X16);
--	else
--		do {
--			rgb->r = dal_fixed31_32_from_fraction(
--				gamma->red[i], scaler);
--			rgb->g = dal_fixed31_32_from_fraction(
--				gamma->green[i], scaler);
--			rgb->b = dal_fixed31_32_from_fraction(
--				gamma->blue[i], scaler);
--
--			++rgb;
--			++i;
--		} while (i != RGB_256X3X16);
--
--	rgb->r = dal_fixed31_32_mul(rgb_last->r,
--			opp110->regamma.divider1);
--	rgb->g = dal_fixed31_32_mul(rgb_last->g,
--			opp110->regamma.divider1);
--	rgb->b = dal_fixed31_32_mul(rgb_last->b,
--			opp110->regamma.divider1);
--
--	++rgb;
--
--	rgb->r = dal_fixed31_32_mul(rgb_last->r,
--			opp110->regamma.divider2);
--	rgb->g = dal_fixed31_32_mul(rgb_last->g,
--			opp110->regamma.divider2);
--	rgb->b = dal_fixed31_32_mul(rgb_last->b,
--			opp110->regamma.divider2);
--
--	++rgb;
--
--	rgb->r = dal_fixed31_32_mul(rgb_last->r,
--			opp110->regamma.divider3);
--	rgb->g = dal_fixed31_32_mul(rgb_last->g,
--			opp110->regamma.divider3);
--	rgb->b = dal_fixed31_32_mul(rgb_last->b,
--			opp110->regamma.divider3);
--
--	return true;
--}
--
--
--static void configure_regamma_mode(
--	struct dce110_opp *opp110,
--	const struct gamma_parameters *params,
--	bool force_bypass)
--{
--	const uint32_t addr = DCP_REG(mmREGAMMA_CONTROL);
--
--	enum wide_gamut_regamma_mode mode =
--		WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A;
--
--	uint32_t value = dm_read_reg(opp110->base.ctx, addr);
--
--	if (force_bypass) {
--
--		set_reg_field_value(
--			value,
--			0,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--
--		dm_write_reg(opp110->base.ctx, addr, value);
--
--		return;
--	}
--
--	if (params->regamma_adjust_type == GRAPHICS_REGAMMA_ADJUST_BYPASS)
--		mode = WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS;
--	else if (params->regamma_adjust_type == GRAPHICS_REGAMMA_ADJUST_HW) {
--		if (params->surface_pixel_format == PIXEL_FORMAT_FP16)
--			mode = WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS;
--		else
--			mode = WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24;
--	}
--
--	switch (mode) {
--	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS:
--		set_reg_field_value(
--			value,
--			0,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--		break;
--	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24:
--		set_reg_field_value(
--			value,
--			1,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--		break;
--	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22:
--		set_reg_field_value(
--			value,
--			2,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--		break;
--	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A:
--		set_reg_field_value(
--			value,
--			3,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--		break;
--	case WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B:
--		set_reg_field_value(
--			value,
--			4,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--		break;
--	default:
--		break;
--	}
--
--	dm_write_reg(opp110->base.ctx, addr, value);
--}
--
--bool dce110_opp_set_regamma(
--	struct output_pixel_processor *opp,
--	const struct gamma_ramp *ramp,
--	const struct gamma_parameters *params,
--	bool force_bypass)
--{
--	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
--
--	if (force_bypass) {
--		configure_regamma_mode(opp110, params, true);
--	} else {
--		/* 1. Scale gamma to 0 - 1 to m_pRgbUser */
--		if (!scale_gamma(opp110, ramp, params)) {
--			ASSERT_CRITICAL(false);
--			/* invalid option */
--			return false;
--		}
--
--		/* 2. Configure regamma curve without analysis (future task) */
--		/*    and program the PWL regions and segments */
--		if (params->regamma_adjust_type == GRAPHICS_REGAMMA_ADJUST_SW ||
--			params->surface_pixel_format == PIXEL_FORMAT_FP16) {
--
--			/* 3. Setup x exponentially distributed points */
--			if (!setup_distribution_points(opp110)) {
--				ASSERT_CRITICAL(false);
--				/* invalid option */
--				return false;
--			}
--
--			/* 4. Build ideal regamma curve */
--			if (!build_regamma_curve(opp110, params)) {
--				ASSERT_CRITICAL(false);
--				/* invalid parameters or bug */
--				return false;
--			}
--
--			/* 5. Map user gamma (evenly distributed x points) to
--			 * new curve when x is y from ideal regamma , step 5 */
--			if (!map_regamma_hw_to_x_user(
--				opp110, ramp, params)) {
--				ASSERT_CRITICAL(false);
--				/* invalid parameters or bug */
--				return false;
--			}
--
--			/* 6.Build and verify resulted curve */
--			build_new_custom_resulted_curve(opp110, params);
--
--			/* 7. Build and translate x to hw format */
--			if (!rebuild_curve_configuration_magic(opp110)) {
--				ASSERT_CRITICAL(false);
--				/* invalid parameters or bug */
--				return false;
--			}
--
--			/* 8. convert all params to the custom float format */
--			if (!convert_to_custom_float(opp110)) {
--				ASSERT_CRITICAL(false);
--				/* invalid parameters or bug */
--				return false;
--			}
--
--			/* 9. program regamma curve configuration */
--			regamma_config_regions_and_segments(opp110);
--
--			/* 10. Program PWL */
--			program_pwl(opp110, params);
--		}
--
--		/*
--		 * 11. program regamma config
--		 */
--		configure_regamma_mode(opp110, params, false);
--	}
--	return true;
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-new file mode 100644
-index 0000000..e61a494
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-@@ -0,0 +1,58 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _DCE110_TYPES_H_
-+#define __DCE110_TYPES_H_
-+
-+#define GAMMA_SEGMENTS_NUM 16
-+struct end_point {
-+	uint32_t x_value;
-+	uint32_t y_value;
-+	uint32_t slope;
-+};
-+
-+struct pwl_segment {
-+	uint32_t r_value;
-+	uint32_t g_value;
-+	uint32_t b_value;
-+	uint32_t r_delta;
-+	uint32_t g_delta;
-+	uint32_t b_delta;
-+};
-+
-+struct dce110_opp_regamma_params {
-+	struct {
-+		uint8_t num_segments[GAMMA_SEGMENTS_NUM];
-+		uint16_t offsets[GAMMA_SEGMENTS_NUM];
-+		struct end_point first;
-+		struct end_point last;
-+	} region_config;
-+
-+	struct {
-+		struct pwl_segment *segments;
-+		int num_pwl_segments;
-+	} pwl_config;
-+};
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_DCE110_DCE110_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 866853b..e3dbaeb 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -53,12 +53,21 @@ struct core_target {
- #define DC_SURFACE_TO_CORE(dc_surface) \
- 	container_of(dc_surface, struct core_surface, public)
- 
-+#define DC_GAMMA_TO_CORE(dc_gamma) \
-+	container_of(dc_gamma, struct core_gamma, public)
-+
-+
- struct core_surface {
- 	struct dc_surface public;
- 	struct dc_surface_status status;
- 	struct dc_context *ctx;
- };
- 
-+struct core_gamma {
-+	struct dc_gamma public;
-+	struct dc_context *ctx;
-+};
-+
- void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 		uint32_t controller_id);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-new file mode 100644
-index 0000000..4e35960
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-@@ -0,0 +1,31 @@
-+/*
-+ * gamma_calcs.h
-+ *
-+ *  Created on: Feb 9, 2016
-+ *      Author: yonsun
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_GAMMA_CALCS_H_
-+#define DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_GAMMA_CALCS_H_
-+
-+#include "opp.h"
-+#include "core_types.h"
-+#include "dc.h"
-+
-+struct temp_params {
-+	struct hw_x_point coordinates_x[256 + 3];
-+	struct pwl_float_data rgb_user[FLOAT_GAMMA_RAMP_MAX + 3];
-+	struct pwl_float_data_ex rgb_regamma[256 + 3];
-+	struct pwl_float_data rgb_oem[FLOAT_GAMMA_RAMP_MAX + 3];
-+	struct gamma_pixel axix_x_256[256];
-+	struct pixel_gamma_point coeff128_oem[256 + 3];
-+	struct pixel_gamma_point coeff128[256 + 3];
-+
-+};
-+
-+void calculate_regamma_params(struct regamma_params *params,
-+		struct temp_params *temp_params,
-+		const struct core_gamma *ramp,
-+		const struct core_surface *surface);
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_GAMMA_CALCS_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-index ad21db5..ca23e1b 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-@@ -41,10 +41,6 @@ struct dev_c_lut16 {
- 	uint16_t blue;
- };
- 
--struct regamma_ramp {
--	uint16_t gamma[RGB_256X3X16 * 3];
--};
--
- /* used by Graphics and Overlay gamma */
- struct gamma_coeff {
- 	int32_t gamma[3];
-@@ -54,35 +50,6 @@ struct gamma_coeff {
- 	int32_t a3[3];
- };
- 
--struct regamma_lut {
--	union {
--		struct {
--			uint32_t GRAPHICS_DEGAMMA_SRGB :1;
--			uint32_t OVERLAY_DEGAMMA_SRGB :1;
--			uint32_t GAMMA_RAMP_ARRAY :1;
--			uint32_t APPLY_DEGAMMA :1;
--			uint32_t RESERVED :28;
--		} bits;
--		uint32_t value;
--	} features;
--
--	union {
--		struct regamma_ramp regamma_ramp;
--		struct gamma_coeff gamma_coeff;
--	};
--};
--
--union gamma_flag {
--	struct {
--		uint32_t config_is_changed :1;
--		uint32_t both_pipe_req :1;
--		uint32_t regamma_update :1;
--		uint32_t gamma_update :1;
--		uint32_t reserved :28;
--	} bits;
--	uint32_t u_all;
--};
--
- enum graphics_regamma_adjust {
- 	GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */
- 	GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */
-@@ -99,19 +66,4 @@ enum graphics_degamma_adjust {
- 	GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */
- };
- 
--struct gamma_parameters {
--	union gamma_flag flag;
--	enum pixel_format surface_pixel_format; /*OS surface pixel format*/
--	struct regamma_lut regamma;
--
--	enum graphics_regamma_adjust regamma_adjust_type;
--	enum graphics_degamma_adjust degamma_adjust_type;
--
--	enum graphics_gamma_lut selected_gamma_lut;
--
--	bool disable_adjustments;
--
--	/* here we grow with parameters if necessary */
--};
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 8460dd7..5dd16dc 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -56,11 +56,11 @@ struct hw_sequencer_funcs {
- 				const struct core_surface *surface,
- 				struct core_target *target);
- 
--	bool (*set_gamma_ramp)(
-+	bool (*set_gamma_correction)(
- 				struct input_pixel_processor *ipp,
- 				struct output_pixel_processor *opp,
--				const struct gamma_ramp *ramp,
--				const struct gamma_parameters *params);
-+				const struct core_gamma *ramp,
-+				const struct core_surface *surface);
- 
- 	void (*power_down)(struct dc *dc);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index 8e7cc31..c98102f 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -45,6 +45,25 @@ struct input_pixel_processor {
- 	struct ipp_funcs *funcs;
- };
- 
-+enum ipp_prescale_mode {
-+	IPP_PRESCALE_MODE_BYPASS,
-+	IPP_PRESCALE_MODE_FIXED_SIGNED,
-+	IPP_PRESCALE_MODE_FLOAT_SIGNED,
-+	IPP_PRESCALE_MODE_FIXED_UNSIGNED,
-+	IPP_PRESCALE_MODE_FLOAT_UNSIGNED
-+};
-+
-+struct ipp_prescale_params {
-+	enum ipp_prescale_mode mode;
-+	uint16_t bias;
-+	uint16_t scale;
-+};
-+
-+enum ipp_degamma_mode {
-+	IPP_DEGAMMA_MODE_BYPASS,
-+	IPP_DEGAMMA_MODE_sRGB
-+};
-+
- enum wide_gamut_degamma_mode {
- 	/*  00  - BITS1:0 Bypass */
- 	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_BYPASS,
-@@ -79,21 +98,11 @@ struct ipp_funcs {
- 	/* DEGAMMA RELATED */
- 	bool (*ipp_set_degamma)(
- 		struct input_pixel_processor *ipp,
--		const struct gamma_parameters *params,
--		bool force_bypass);
-+		enum ipp_degamma_mode mode);
- 
- 	void (*ipp_program_prescale)(
- 		struct input_pixel_processor *ipp,
--		enum pixel_format pixel_format);
--
--	void (*ipp_set_legacy_input_gamma_mode)(
--			struct input_pixel_processor *ipp,
--			bool is_legacy);
--
--	bool (*ipp_set_legacy_input_gamma_ramp)(
--		struct input_pixel_processor *ipp,
--		const struct gamma_ramp *gamma_ramp,
--		const struct gamma_parameters *params);
-+		struct ipp_prescale_params *params);
- 
- 	bool (*ipp_set_palette)(
- 		struct input_pixel_processor *ipp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 3071df6..307184a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -263,6 +263,14 @@ enum fmt_stereo_action {
- 	FMT_STEREO_ACTION_UPDATE_POLARITY
- };
- 
-+struct regamma_params {
-+	uint32_t *data;
-+	struct gamma_curve arr_curve_points[16];
-+	struct curve_points arr_points[3];
-+	struct pwl_result_data rgb_resulted[256 + 3];
-+	uint32_t hw_points_num;
-+};
-+
- struct opp_funcs {
- 	void (*opp_power_on_regamma_lut)(
- 		struct output_pixel_processor *opp,
-@@ -270,14 +278,7 @@ struct opp_funcs {
- 
- 	bool (*opp_set_regamma)(
- 		struct output_pixel_processor *opp,
--		const struct gamma_ramp *ramp,
--		const struct gamma_parameters *params,
--		bool force_bypass);
--
--	bool (*opp_map_legacy_and_regamma_hw_to_x_user)(
--		struct output_pixel_processor *opp,
--		const struct gamma_ramp *gamma_ramp,
--		const struct gamma_parameters *params);
-+		const struct regamma_params *params);
- 
- 	void (*opp_set_csc_adjustment)(
- 		struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index c229f5a..e2a9343 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -108,7 +108,6 @@ struct ovl_csc_adjustment {
- 	uint32_t matrix_divider;
- 
- 	/* DCE50 parameters */
--	struct regamma_lut regamma;
- 	enum overlay_gamma_adjust adjust_gamma_type;
- 	enum overlay_csc_adjust_type adjust_csc_type;
- 	enum overlay_gamut_adjust_type adjust_gamut_type;
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-index 6f9cd3f..e910711 100644
---- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -49,7 +49,6 @@ struct overlay_gamma_parameters {
- 	int32_t ovl_gamma_cont;
- 	enum overlay_gamma_adjust adjust_type;
- 	enum pixel_format desktop_surface;
--	struct regamma_lut regamma;
- 
- 	/* here we grow with parameters if necessary */
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0785-drm-amd-dal-Use-reg-offset-to-handle-blndv-programmi.patch b/common/recipes-kernel/linux/files/0785-drm-amd-dal-Use-reg-offset-to-handle-blndv-programmi.patch
deleted file mode 100644
index 7e442e4e..00000000
--- a/common/recipes-kernel/linux/files/0785-drm-amd-dal-Use-reg-offset-to-handle-blndv-programmi.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 4f990cdc9179309c2e03d6a978a179b791c284fb Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 9 Feb 2016 16:03:42 -0500
-Subject: [PATCH 0785/1110] drm/amd/dal: Use reg offset to handle blndv
- programming
-
-Using offsets to handle blndv programming, leaving the
-code path generic
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 48 ++++++++--------------
- 1 file changed, 17 insertions(+), 31 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 946e42f..43840c1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -84,6 +84,11 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- 	.dcfe = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
- 	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.dcfe = (mmDCFEV_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.blnd = (mmBLNDV_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- }
- };
- 
-@@ -352,7 +357,7 @@ static void dce110_set_blender_mode(
- 	uint32_t mode)
- {
- 	uint32_t value;
--	uint32_t addr = 0;
-+	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- 	uint32_t blnd_mode;
- 	uint32_t feedthrough = 0;
- 
-@@ -372,39 +377,20 @@ static void dce110_set_blender_mode(
- 		break;
- 	}
- 
--	if (controller_id == CONTROLLER_ID_UNDERLAY0) {
--		addr = mmBLNDV_CONTROL;
--		value = dm_read_reg(ctx, addr);
--
--			set_reg_field_value(
--				value,
--				feedthrough,
--				BLNDV_CONTROL,
--				BLND_FEEDTHROUGH_EN);
--
--			set_reg_field_value(
--				value,
--				blnd_mode,
--				BLNDV_CONTROL,
--				BLND_MODE);
--
-+	value = dm_read_reg(ctx, addr);
- 
--	} else {
--		addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
--		value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		feedthrough,
-+		BLND_CONTROL,
-+		BLND_FEEDTHROUGH_EN);
- 
--		set_reg_field_value(
--			value,
--			feedthrough,
--			BLND_CONTROL,
--			BLND_FEEDTHROUGH_EN);
-+	set_reg_field_value(
-+		value,
-+		blnd_mode,
-+		BLND_CONTROL,
-+		BLND_MODE);
- 
--		set_reg_field_value(
--			value,
--			blnd_mode,
--			BLND_CONTROL,
--			BLND_MODE);
--	}
- 
- 	dm_write_reg(ctx, addr, value);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch b/common/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch
deleted file mode 100644
index 006b9bd8..00000000
--- a/common/recipes-kernel/linux/files/0786-drm-amd-dal-Consolidate-safe-and-generic-watermark-p.patch
+++ /dev/null
@@ -1,261 +0,0 @@
-From dfb0581b9d72f656d93249b3e92b39b719410139 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Tue, 9 Feb 2016 14:28:31 -0500
-Subject: [PATCH 0786/1110] drm/amd/dal: Consolidate "safe" and "generic"
- watermark programming.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 64 ++++++++++++++++------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 24 +-------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   | 12 +---
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |  7 +--
- 4 files changed, 52 insertions(+), 55 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 43840c1..a815a6d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -102,6 +102,9 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- 	(reg + reg_offsets[id].crtc)
- 
- 
-+#define MAX_WATERMARK 0xFFFF
-+#define SAFE_NBP_MARK 0x7FFF
-+
- /*******************************************************************************
-  * Private definitions
-  ******************************************************************************/
-@@ -1129,41 +1132,64 @@ static void set_display_clock(struct validate_context *context)
- 	/* TODO: Start GTC counter */
- }
- 
-+static uint32_t compute_pstate_blackout_duration(
-+	const struct dc *dc,
-+	const struct core_stream *stream)
-+{
-+	uint32_t total_dest_line_time_ns;
-+	uint32_t pstate_blackout_duration_ns;
-+
-+	pstate_blackout_duration_ns = 1000 *
-+		dc->bw_vbios.blackout_duration.value >> 24;
-+
-+	total_dest_line_time_ns = 1000000UL *
-+		stream->public.timing.h_total /
-+		stream->public.timing.pix_clk_khz +
-+		pstate_blackout_duration_ns;
-+
-+	return total_dest_line_time_ns;
-+}
-+
- static void set_displaymarks(
--	const struct dc *dc, struct validate_context *context)
-+	const struct dc *dc,
-+	struct validate_context *context)
- {
- 	uint8_t i, j;
- 	uint8_t total_streams = 0;
- 	uint8_t target_count = context->target_count;
-+	uint32_t pstate_blackout_duration_ns;
- 
- 	for (i = 0; i < target_count; i++) {
--		struct core_target *target = context->targets[i];
-+		const struct core_target *target = context->targets[i];
- 
- 		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
-+			const struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
-+			pstate_blackout_duration_ns =
-+				compute_pstate_blackout_duration(dc, stream);
-+
- 			stream->mi->funcs->mem_input_program_display_marks(
- 				stream->mi,
- 				context->bw_results
--				.nbp_state_change_wm_ns[total_streams],
-+					.nbp_state_change_wm_ns[total_streams],
- 				context->bw_results
- 					.stutter_exit_wm_ns[total_streams],
--				context->bw_results
--					.urgent_wm_ns[total_streams],
--				stream->public.timing.h_total,
--				stream->public.timing.pix_clk_khz,
--				1000 * dc->bw_vbios.blackout_duration
--								.value >> 24);
-+				context->bw_results.
-+					urgent_wm_ns[total_streams],
-+				pstate_blackout_duration_ns);
-+
- 			total_streams++;
--		}
--	}
-+		} /* for ()*/
-+	} /* for() */
- }
- 
--static void set_safe_displaymarks(struct validate_context *context)
-+static void set_safe_displaymarks(const struct dc *dc, struct validate_context *context)
- {
- 	uint8_t i, j;
- 	uint8_t target_count = context->target_count;
-+	struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
-+	struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
- 
- 	for (i = 0; i < target_count; i++) {
- 		struct core_target *target = context->targets[i];
-@@ -1172,15 +1198,19 @@ static void set_safe_displaymarks(struct validate_context *context)
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			stream->mi->funcs->mem_input_program_safe_display_marks(
--					stream->mi);
-+			stream->mi->funcs->mem_input_program_display_marks(
-+				stream->mi,
-+				nbp_marks,
-+				max_marks,
-+				max_marks,
-+				MAX_WATERMARK);
- 		}
- 	}
- }
- 
- static void program_bw(struct dc *dc, struct validate_context *context)
- {
--	set_safe_displaymarks(context);
-+	set_safe_displaymarks(dc, context);
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
-@@ -1252,7 +1282,7 @@ static enum dc_status apply_ctx_to_hw(
- 				PIPE_GATING_CONTROL_DISABLE);
- 	}
- 
--	set_safe_displaymarks(context);
-+	set_safe_displaymarks(dc, context);
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index b718ac1..f640552 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -36,8 +36,6 @@
- 
- #include "dce110_mem_input.h"
- 
--#define MAX_WATERMARK 0xFFFF
--#define SAFE_NBP_MARK 0x7FFF
- 
- #define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
- #define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
-@@ -677,40 +675,26 @@ static void program_nbp_watermark(
- 	dm_write_reg(ctx, addr, value);
- }
- 
--void dce110_mem_input_program_safe_display_marks(struct mem_input *mi)
--{
--	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
--	struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
--	struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
--
--	program_urgency_watermark(
--		mi->ctx, bm_dce110->offsets.dmif, max_marks, MAX_WATERMARK);
--	program_stutter_watermark(mi->ctx, bm_dce110->offsets.dmif, max_marks);
--	program_nbp_watermark(mi->ctx, bm_dce110->offsets.dmif, nbp_marks);
--}
--
- void dce110_mem_input_program_display_marks(
- 	struct mem_input *mem_input,
- 	struct bw_watermarks nbp,
- 	struct bw_watermarks stutter,
- 	struct bw_watermarks urgent,
--	uint32_t h_total,
--	uint32_t pixel_clk_in_khz,
--	uint32_t pstate_blackout_duration_ns)
-+	uint32_t total_dest_line_time_ns)
- {
- 	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input);
--	uint32_t total_dest_line_time_ns = 1000000UL * h_total
--		/ pixel_clk_in_khz + pstate_blackout_duration_ns;
- 
- 	program_urgency_watermark(
- 		mem_input->ctx,
- 		bm_dce110->offsets.dmif,
- 		urgent,
- 		total_dest_line_time_ns);
-+
- 	program_nbp_watermark(
- 		mem_input->ctx,
- 		bm_dce110->offsets.dmif,
- 		nbp);
-+
- 	program_stutter_watermark(
- 		mem_input->ctx,
- 		bm_dce110->offsets.dmif,
-@@ -930,8 +914,6 @@ void dce110_free_mem_input(
- }
- 
- static struct mem_input_funcs dce110_mem_input_funcs = {
--	.mem_input_program_safe_display_marks =
--			dce110_mem_input_program_safe_display_marks,
- 	.mem_input_program_display_marks =
- 			dce110_mem_input_program_display_marks,
- 	.allocate_mem_input = dce110_allocate_mem_input,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 232d7fb..a0db7aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -51,14 +51,6 @@ bool dce110_mem_input_construct(
- /*
-  * dce110_mem_input_program_display_marks
-  *
-- * This function will program nbp stutter and urgency watermarks to maximum
-- * safe values
-- */
--void dce110_mem_input_program_safe_display_marks(struct mem_input *mi);
--
--/*
-- * dce110_mem_input_program_display_marks
-- *
-  * This function will program nbp stutter and urgency watermarks to minimum
-  * allowable values
-  */
-@@ -67,9 +59,7 @@ void dce110_mem_input_program_display_marks(
- 	struct bw_watermarks nbp,
- 	struct bw_watermarks stutter,
- 	struct bw_watermarks urgent,
--	uint32_t h_total,
--	uint32_t pixel_clk_in_khz,
--	uint32_t pstate_blackout_duration_ns);
-+	uint32_t total_dest_line_time_ns);
- 
- /*
-  * dce110_allocate_mem_input
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 747e5dc..9cd9905 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -35,17 +35,12 @@ struct mem_input {
- };
- 
- struct mem_input_funcs {
--	void (*mem_input_program_safe_display_marks)(
--		struct mem_input *mi);
--
- 	void (*mem_input_program_display_marks)(
- 		struct mem_input *mem_input,
- 		struct bw_watermarks nbp,
- 		struct bw_watermarks stutter,
- 		struct bw_watermarks urgent,
--		uint32_t h_total,
--		uint32_t pixel_clk_in_khz,
--		uint32_t pstate_blackout_duration_ns);
-+		uint32_t total_dest_line_time_ns);
- 
- 	void (*allocate_mem_input)(
- 		struct mem_input *mem_input,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0787-drm-amd-amdgpu-Fall-back-to-non-dal-driver-on-Bonair.patch b/common/recipes-kernel/linux/files/0787-drm-amd-amdgpu-Fall-back-to-non-dal-driver-on-Bonair.patch
deleted file mode 100644
index be38bb86..00000000
--- a/common/recipes-kernel/linux/files/0787-drm-amd-amdgpu-Fall-back-to-non-dal-driver-on-Bonair.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 583d7a302b73be5fe65ec359dfc9f12eca9928c2 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 9 Feb 2016 16:19:06 -0500
-Subject: [PATCH 0787/1110] drm/amd/amdgpu: Fall back to non-dal driver on
- Bonaire
-
-Since DAL support for Bonaire isn't ready yet don't try
-to enable DAL for Bonaire yet.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 3de29d9..aba8b80 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1389,11 +1389,6 @@ static int amdgpu_resume(struct amdgpu_device *adev)
- bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- {
- 	switch(adev->asic_type) {
--#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE8_0)
--	case CHIP_BONAIRE:
--	case CHIP_HAWAII:
--		return true;
--#endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case CHIP_CARRIZO:
- 		return true;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0788-drm-amd-amdgpu-Remove-has_dal_support-macro.patch b/common/recipes-kernel/linux/files/0788-drm-amd-amdgpu-Remove-has_dal_support-macro.patch
deleted file mode 100644
index 1fe04c2a..00000000
--- a/common/recipes-kernel/linux/files/0788-drm-amd-amdgpu-Remove-has_dal_support-macro.patch
+++ /dev/null
@@ -1,132 +0,0 @@
-From 075f787e0d3d05055da45f1905605e6d3f4b4a72 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 27 Sep 2016 14:29:21 +0530
-Subject: [PATCH] drm/amd/amdgpu: Remove has_dal_support macro
-
-Moving this into the amdgpu_device_has_dal_support function
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  2 --
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    |  4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c    |  2 +-
- 4 files changed, 10 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 66e91c5..2308eea 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2331,8 +2331,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- 
- #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
- 
--#define amdgpu_has_dal_support(adev) (amdgpu_dal && amdgpu_device_has_dal_support(adev))
--
- /* Common functions */
- int amdgpu_gpu_reset(struct amdgpu_device *adev);
- void amdgpu_pci_config_reset(struct amdgpu_device *adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index e523c74..dfb7500 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1391,12 +1391,12 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- 	switch(adev->asic_type) {
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case CHIP_CARRIZO:
--		return true;
-+		return amdgpu_dal != 0;
- #endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
--		return true;
-+		return amdgpu_dal != 0;
- #endif
- 	default:
- 		return false;
-@@ -1557,7 +1557,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	}
- 
- 	/* init i2c buses */
--	if (!amdgpu_has_dal_support(adev))
-+	if (!amdgpu_device_has_dal_support(adev))
- 		amdgpu_atombios_i2c_init(adev);
- 
- 	/* Fence driver */
-@@ -1658,7 +1658,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
- 	adev->ip_block_status = NULL;
- 	adev->accel_working = false;
- 	/* free i2c buses */
--	if (!amdgpu_has_dal_support(adev))
-+	if (!amdgpu_device_has_dal_support(adev))
- 		amdgpu_i2c_fini(adev);
- 	amdgpu_atombios_fini(adev);
- 	kfree(adev->bios);
-@@ -1707,7 +1707,7 @@ int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
- 
- 	drm_kms_helper_poll_disable(dev);
- 
--	if (!amdgpu_has_dal_support(adev)) {
-+	if (!amdgpu_device_has_dal_support(adev)) {
- 		/* turn off display hw */
- 		drm_modeset_lock_all(dev);
- 		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-@@ -1844,7 +1844,7 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- 
- 	/* blat the mode back in */
- 	if (fbcon) {
--		if (!amdgpu_has_dal_support(adev)) {
-+		if (!amdgpu_device_has_dal_support(adev)) {
- 			/* pre DCE11 */
- 			drm_helper_resume_force_mode(dev);
- 
-@@ -1872,7 +1872,7 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- 	dev->dev->power.disable_depth++;
- #endif
- 
--	if (!amdgpu_has_dal_support(adev))
-+	if (!amdgpu_device_has_dal_support(adev))
- 		drm_helper_hpd_irq_event(dev);
- 	else
- 		drm_kms_helper_hotplug_event(dev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 97e5b69..3dc354b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -77,7 +77,7 @@ int amdgpu_vm_block_size = -1;
- int amdgpu_vm_fault_stop = 0;
- int amdgpu_vm_debug = 0;
- int amdgpu_exp_hw_support = 0;
--int amdgpu_dal = 1;
-+int amdgpu_dal = -1;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_powerplay = -1;
-@@ -150,7 +150,7 @@ module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
- MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
- module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
- 
--MODULE_PARM_DESC(dal, "DAL display driver (1 = enable (default), 0 = disable)");
-+MODULE_PARM_DESC(dal, "DAL display driver (1 = enable, 0 = disable, -1 = auto (default))");
- module_param_named(dal, amdgpu_dal, int, 0444);
- 
- MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 7ad2aed..8d34ccd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -231,7 +231,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
- 		}
- 	}
- 
--	if (!amdgpu_has_dal_support(adev)) {
-+	if (!amdgpu_device_has_dal_support(adev)) {
- 		r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
- 		if (r)
- 			return r;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0789-drm-amd-dal-non-destructive-validate.patch b/common/recipes-kernel/linux/files/0789-drm-amd-dal-non-destructive-validate.patch
deleted file mode 100644
index 5d834481..00000000
--- a/common/recipes-kernel/linux/files/0789-drm-amd-dal-non-destructive-validate.patch
+++ /dev/null
@@ -1,4120 +0,0 @@
-From c49d3cd9af2452b28e673fa354f057989062011e Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Fri, 5 Feb 2016 11:41:55 -0500
-Subject: [PATCH 0789/1110] drm/amd/dal: non destructive validate
-
-This changes the way resources are handled to make validate non
-destructive to current state and allow allocating mpo resources
-if needed.
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c  |   2 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |   3 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  46 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 133 +++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |   4 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 398 +++++++-------
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 350 +++++++-----
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   8 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  23 +-
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 210 ++++----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 586 +++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |  13 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 345 ++++++------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        | 107 ++--
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  23 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      |   5 +-
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h         |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  13 +-
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.c  |   2 +-
- drivers/gpu/drm/amd/dal/include/grph_csc_types.h   |  13 -
- 21 files changed, 1145 insertions(+), 1143 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index 9b5fd70..2ba79ab 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -688,7 +688,7 @@ static inline int dm_irq_state(
- 		return 0;
- 	}
- 
--	irq_source = dc_target_get_irq_src(acrtc->target, dal_irq_type);
-+	irq_source = dc_target_get_irq_src(adev->dm.dc, acrtc->target, dal_irq_type);
- 
- 	st = (state == AMDGPU_IRQ_STATE_ENABLE);
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 2cb445d..39490bf 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -484,8 +484,7 @@ static void fill_plane_attributes_from_fb(
- 	surface->scaling_quality.v_taps_c = 2;
- 
- 	/* TODO: unhardcode */
--	surface->colorimetry.limited_range = false;
--	surface->colorimetry.color_space = SURFACE_COLOR_SPACE_SRGB;
-+	surface->color_space = COLOR_SPACE_SRGB_FULL_RANGE;
- 	surface->scaling_quality.h_taps = 2;
- 	surface->scaling_quality.v_taps = 2;
- 	surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index d788917..bcc6f68 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -172,7 +172,7 @@ static void init_hw(struct dc *dc)
- 	struct transform *xfm;
- 
- 	bp = dal_adapter_service_get_bios_parser(dc->res_pool.adapter_srv);
--	for(i = 0; i < dc->res_pool.controller_count; i++) {
-+	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		xfm = dc->res_pool.transforms[i];
- 
- 		dc->hwss.enable_display_power_gating(
-@@ -201,7 +201,7 @@ static void init_hw(struct dc *dc)
- 		link->link_enc->funcs->hw_init(link->link_enc);
- 	}
- 
--	for(i = 0; i < dc->res_pool.controller_count; i++) {
-+	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		struct timing_generator *tg = dc->res_pool.timing_generators[i];
- 
- 		tg->funcs->disable_vga(tg);
-@@ -466,11 +466,11 @@ static void program_timing_sync(
- 	uint8_t i;
- 	uint8_t j;
- 	uint8_t group_size = 0;
--	uint8_t tg_count = ctx->res_ctx.pool.controller_count;
-+	uint8_t tg_count = ctx->res_ctx.pool.pipe_count;
- 	struct timing_generator *tg_set[3];
- 
- 	for (i = 0; i < tg_count; i++) {
--		if (!ctx->res_ctx.controller_ctx[i].stream)
-+		if (!ctx->res_ctx.pipe_ctx[i].stream)
- 			continue;
- 
- 		tg_set[0] = ctx->res_ctx.pool.timing_generators[i];
-@@ -480,13 +480,13 @@ static void program_timing_sync(
- 		 * same timing, add all tgs with same timing to the group
- 		 */
- 		for (j = i + 1; j < tg_count; j++) {
--			if (!ctx->res_ctx.controller_ctx[j].stream)
-+			if (!ctx->res_ctx.pipe_ctx[j].stream)
- 				continue;
- 
- 			if (is_same_timing(
--				&ctx->res_ctx.controller_ctx[j].stream->public
-+				&ctx->res_ctx.pipe_ctx[j].stream->public
- 								.timing,
--				&ctx->res_ctx.controller_ctx[i].stream->public
-+				&ctx->res_ctx.pipe_ctx[i].stream->public
- 								.timing)) {
- 				tg_set[group_size] =
- 					ctx->res_ctx.pool.timing_generators[j];
-@@ -580,7 +580,7 @@ bool dc_commit_targets(
- 	}
- 
- 	if (result == DC_OK) {
--		dc->hwss.reset_hw_ctx(dc, context, target_count);
-+		dc->hwss.reset_hw_ctx(dc, context);
- 
- 		if (context->target_count > 0)
- 			result = dc->hwss.apply_ctx_to_hw(dc, context);
-@@ -588,7 +588,7 @@ bool dc_commit_targets(
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		struct dc_target *dc_target = &context->targets[i]->public;
--		if (context->targets[i]->status.surface_count > 0)
-+		if (context->target_status[i].surface_count > 0)
- 			dc_target_enable_memory_requests(dc_target);
- 	}
- 
-@@ -609,7 +609,6 @@ bool dc_commit_targets(
- 
- 	pplib_apply_display_requirements(dc, context, &context->pp_display_cfg);
- 
--	/* TODO: disable unused plls*/
- fail:
- 	dm_free(dc->ctx, context);
- 
-@@ -659,12 +658,13 @@ const struct audio **dc_get_audios(struct dc *dc)
- 
- void dc_get_caps(const struct dc *dc, struct dc_caps *caps)
- {
--	caps->max_targets = dc->res_pool.controller_count;
-+	caps->max_targets = dc->res_pool.pipe_count;
- 	caps->max_links = dc->link_count;
- 	caps->max_audios = dc->res_pool.audio_count;
- }
- 
--void dc_flip_surface_addrs(struct dc* dc,
-+void dc_flip_surface_addrs(
-+		struct dc *dc,
- 		const struct dc_surface *const surfaces[],
- 		struct dc_flip_addrs flip_addrs[],
- 		uint32_t count)
-@@ -679,10 +679,8 @@ void dc_flip_surface_addrs(struct dc* dc,
- 		surface->public.address = flip_addrs[i].address;
- 		surface->public.flip_immediate = flip_addrs[i].flip_immediate;
- 
--		dc->hwss.update_plane_address(
--			dc,
--			surface,
--			DC_TARGET_TO_CORE(surface->status.dc_target));
-+		dc->hwss.update_plane_addrs(
-+				dc, &dc->current_context.res_ctx, surface);
- 	}
- }
- 
-@@ -737,27 +735,19 @@ const struct dc_target *dc_get_target_on_irq_source(
- 
- 	for (i = 0; i < dc->current_context.target_count; i++) {
- 		struct core_target *target = dc->current_context.targets[i];
--
--		struct dc_target *dc_target;
--
--		if (NULL == target) {
--			dm_error("%s: 'dc_target' is NULL for irq source: %d\n!",
--					__func__, src);
--			continue;
--		}
--
--		dc_target = &target->public;
-+		struct dc_target *dc_target = &target->public;
- 
- 		for (j = 0; j < target->public.stream_count; j++) {
- 			const struct core_stream *stream =
- 				DC_STREAM_TO_CORE(dc_target->streams[j]);
--			const uint8_t controller_idx = stream->controller_idx;
- 
--			if (controller_idx == crtc_idx)
-+			if (dc->current_context.res_ctx.
-+					pipe_ctx[crtc_idx].stream == stream)
- 				return dc_target;
- 		}
- 	}
- 
-+	dm_error("%s: 'dc_target' is NULL for irq source: %d\n!", __func__, src);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 9a5eadf..5fd5800 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1142,8 +1142,9 @@ static void dpcd_configure_panel_mode(
- 			panel_mode_edp);
- }
- 
--static enum dc_status enable_link_dp(struct core_stream *stream)
-+static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	enum dc_status status;
- 	bool skip_video_pattern;
- 	struct core_link *link = stream->sink->link;
-@@ -1154,7 +1155,7 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 	decide_link_settings(stream, &link_settings);
- 	dp_enable_link_phy(
- 		stream->sink->link,
--		stream->signal,
-+		pipe_ctx->signal,
- 		&link_settings);
- 
- 	panel_mode = dp_get_panel_mode(link);
-@@ -1175,9 +1176,9 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
- 	return status;
- }
- 
--static enum dc_status enable_link_dp_mst(struct core_stream *stream)
-+static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx)
- {
--	struct core_link *link = stream->sink->link;
-+	struct core_link *link = pipe_ctx->stream->sink->link;
- 
- 	/* sink signal type after MST branch is MST. Multiple MST sinks
- 	 * share one link. Link DP PHY is enable or training only once.
-@@ -1185,11 +1186,12 @@ static enum dc_status enable_link_dp_mst(struct core_stream *stream)
- 	if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
- 		return DC_OK;
- 
--	return enable_link_dp(stream);
-+	return enable_link_dp(pipe_ctx);
- }
- 
--static void enable_link_hdmi(struct core_stream *stream)
-+static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	struct core_link *link = stream->sink->link;
- 
- 	/* enable video output */
-@@ -1214,7 +1216,7 @@ static void enable_link_hdmi(struct core_stream *stream)
- 		break;
- 	}
- 
--	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+	if (pipe_ctx->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 		dal_ddc_service_write_scdc_data(
- 			stream->sink->link->ddc,
- 			normalized_pix_clk,
-@@ -1225,33 +1227,33 @@ static void enable_link_hdmi(struct core_stream *stream)
- 
- 	link->link_enc->funcs->enable_tmds_output(
- 			link->link_enc,
--			stream->clock_source->id,
-+			pipe_ctx->clock_source->id,
- 			stream->public.timing.display_color_depth,
--			stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
--			stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
-+			pipe_ctx->signal == SIGNAL_TYPE_HDMI_TYPE_A,
-+			pipe_ctx->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
- 			stream->public.timing.pix_clk_khz);
- 
--	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+	if (pipe_ctx->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- 		dal_ddc_service_read_scdc_data(link->ddc);
- }
- 
- /****************************enable_link***********************************/
--static enum dc_status enable_link(struct core_stream *stream)
-+static enum dc_status enable_link(struct pipe_ctx *pipe_ctx)
- {
- 	enum dc_status status = DC_ERROR_UNEXPECTED;
--	switch (stream->signal) {
-+	switch (pipe_ctx->signal) {
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_EDP:
--		status = enable_link_dp(stream);
-+		status = enable_link_dp(pipe_ctx);
- 		break;
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--		status = enable_link_dp_mst(stream);
--		dm_sleep_in_milliseconds(stream->ctx, 200);
-+		status = enable_link_dp_mst(pipe_ctx);
-+		dm_sleep_in_milliseconds(pipe_ctx->stream->ctx, 200);
- 		break;
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
--		enable_link_hdmi(stream);
-+		enable_link_hdmi(pipe_ctx);
- 		status = DC_OK;
- 		break;
- 	case SIGNAL_TYPE_VIRTUAL:
-@@ -1261,20 +1263,20 @@ static enum dc_status enable_link(struct core_stream *stream)
- 		break;
- 	}
- 
--	if (stream->audio && status == DC_OK) {
-+	if (pipe_ctx->audio && status == DC_OK) {
- 		/* notify audio driver for audio modes of monitor */
--		dal_audio_enable_azalia_audio_jack_presence(stream->audio,
--				stream->stream_enc->id);
-+		dal_audio_enable_azalia_audio_jack_presence(pipe_ctx->audio,
-+				pipe_ctx->stream_enc->id);
- 
- 		/* un-mute audio */
--		dal_audio_unmute(stream->audio, stream->stream_enc->id,
--				stream->signal);
-+		dal_audio_unmute(pipe_ctx->audio, pipe_ctx->stream_enc->id,
-+				pipe_ctx->signal);
- 	}
- 
- 	return status;
- }
- 
--static void disable_link(struct core_stream *stream)
-+static void disable_link(struct core_link *link, enum signal_type signal)
- {
- 	/*
- 	 * TODO: implement call for dp_set_hw_test_pattern
-@@ -1286,21 +1288,14 @@ static void disable_link(struct core_stream *stream)
- 	 * it will lead to querying dynamic link capabilities
- 	 * which should be done before enable output */
- 
--	if (dc_is_dp_signal(stream->signal)) {
-+	if (dc_is_dp_signal(signal)) {
- 		/* SST DP, eDP */
--		if (dc_is_dp_sst_signal(stream->signal))
--			dp_disable_link_phy(
--					stream->sink->link, stream->signal);
--		else {
--			dp_disable_link_phy_mst(
--					stream->sink->link, stream);
--		}
--	} else {
--		struct link_encoder *encoder =
--				stream->sink->link->link_enc;
--
--		encoder->funcs->disable_output(encoder, stream->signal);
--	}
-+		if (dc_is_dp_sst_signal(signal))
-+			dp_disable_link_phy(link, signal);
-+		else
-+			dp_disable_link_phy_mst(link, signal);
-+	} else
-+		link->link_enc->funcs->disable_output(link->link_enc, signal);
- }
- 
- enum dc_status dc_link_validate_mode_timing(
-@@ -1360,9 +1355,9 @@ static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
- 	return dal_fixed31_32_div_int(mbps, 54);
- }
- 
--static int get_color_depth(struct core_stream *stream)
-+static int get_color_depth(enum dc_color_depth color_depth)
- {
--	switch (stream->pix_clk_params.color_depth) {
-+	switch (color_depth) {
- 	case COLOR_DEPTH_666: return 6;
- 	case COLOR_DEPTH_888: return 8;
- 	case COLOR_DEPTH_101010: return 10;
-@@ -1373,7 +1368,7 @@ static int get_color_depth(struct core_stream *stream)
- 	}
- }
- 
--static struct fixed31_32 get_pbn_from_timing(struct core_stream *stream)
-+static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
- {
- 	uint32_t bpc;
- 	uint64_t kbps;
-@@ -1381,8 +1376,8 @@ static struct fixed31_32 get_pbn_from_timing(struct core_stream *stream)
- 	uint32_t numerator;
- 	uint32_t denominator;
- 
--	bpc = get_color_depth(stream);
--	kbps = stream->pix_clk_params.requested_pix_clk * bpc * 3;
-+	bpc = get_color_depth(pipe_ctx->pix_clk_params.color_depth);
-+	kbps = pipe_ctx->pix_clk_params.requested_pix_clk * bpc * 3;
- 
- 	/*
- 	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
-@@ -1405,7 +1400,7 @@ static struct fixed31_32 get_pbn_from_timing(struct core_stream *stream)
- 
- static void update_mst_stream_alloc_table(
- 	struct core_link *link,
--	struct core_stream *stream,
-+	struct stream_encoder *stream_enc,
- 	const struct dp_mst_stream_allocation_table *proposed_table)
- {
- 	struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
-@@ -1440,7 +1435,7 @@ static void update_mst_stream_alloc_table(
- 				proposed_table->stream_allocations[i].vcp_id;
- 			work_table[i].slot_count =
- 				proposed_table->stream_allocations[i].slot_count;
--			work_table[i].stream_enc = stream->stream_enc;
-+			work_table[i].stream_enc = stream_enc;
- 		}
- 	}
- 
-@@ -1455,11 +1450,12 @@ static void update_mst_stream_alloc_table(
- /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
-  * because stream_encoder is not exposed to dm
-  */
--static enum dc_status allocate_mst_payload(struct core_stream *stream)
-+static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	struct core_link *link = stream->sink->link;
- 	struct link_encoder *link_encoder = link->link_enc;
--	struct stream_encoder *stream_encoder = stream->stream_enc;
-+	struct stream_encoder *stream_encoder = pipe_ctx->stream_enc;
- 	struct dp_mst_stream_allocation_table proposed_table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp;
- 	struct fixed31_32 pbn;
-@@ -1478,7 +1474,8 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 		&proposed_table,
- 		true);
- 
--	update_mst_stream_alloc_table(link, stream, &proposed_table);
-+	update_mst_stream_alloc_table(
-+				link, pipe_ctx->stream_enc, &proposed_table);
- 
- 	dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_MST,
-@@ -1532,7 +1529,7 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 
- 	/* slot X.Y for only current stream */
- 	pbn_per_slot = get_pbn_per_slot(stream);
--	pbn = get_pbn_from_timing(stream);
-+	pbn = get_pbn_from_timing(pipe_ctx);
- 	avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
- 
- 
-@@ -1545,11 +1542,12 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream)
- 
- }
- 
--static enum dc_status deallocate_mst_payload(struct core_stream *stream)
-+static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	struct core_link *link = stream->sink->link;
- 	struct link_encoder *link_encoder = link->link_enc;
--	struct stream_encoder *stream_encoder = stream->stream_enc;
-+	struct stream_encoder *stream_encoder = pipe_ctx->stream_enc;
- 	struct dp_mst_stream_allocation_table proposed_table = {0};
- 	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
- 	uint8_t i;
-@@ -1575,7 +1573,8 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 				&proposed_table,
- 				false);
- 
--	update_mst_stream_alloc_table(link, stream, &proposed_table);
-+	update_mst_stream_alloc_table(
-+		link, pipe_ctx->stream_enc, &proposed_table);
- 
- 	dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_MST,
-@@ -1618,38 +1617,32 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream)
- 	return DC_OK;
- }
- 
--void core_link_enable_stream(
--		struct core_link *link,
--		struct core_stream *stream)
-+void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- {
--	struct dc *dc = stream->ctx->dc;
-+	struct dc *dc = pipe_ctx->stream->ctx->dc;
- 
--	if (DC_OK != enable_link(stream)) {
-+	if (DC_OK != enable_link(pipe_ctx)) {
- 			BREAK_TO_DEBUGGER();
- 			return;
- 	}
- 
--	dc->hwss.enable_stream(stream);
--	stream->status.link = &link->public;
-+	dc->hwss.enable_stream(pipe_ctx);
- 
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
--		allocate_mst_payload(stream);
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		allocate_mst_payload(pipe_ctx);
- }
- 
--void core_link_disable_stream(
--		struct core_link *link,
--		struct core_stream *stream)
-+void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
- {
--	struct dc *dc = stream->ctx->dc;
--
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
--		deallocate_mst_payload(stream);
-+	struct dc *dc = pipe_ctx->stream->ctx->dc;
- 
--	stream->status.link = NULL;
--	dc->hwss.disable_stream(stream);
-+	pipe_ctx->stream->status.link = NULL;
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		deallocate_mst_payload(pipe_ctx);
- 
--	disable_link(stream);
-+	dc->hwss.disable_stream(pipe_ctx);
- 
-+	disable_link(pipe_ctx->stream->sink->link, pipe_ctx->signal);
- }
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 92d70ed..04a0c17 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -93,13 +93,13 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 			sizeof(link->public.cur_link_settings));
- }
- 
--void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream)
-+void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal)
- {
- 	/* MST disable link only when no stream use the link */
- 	if (link->mst_stream_alloc_table.stream_count > 0)
- 		return;
- 
--	dp_disable_link_phy(link, stream->signal);
-+	dp_disable_link_phy(link, signal);
- }
- 
- bool dp_set_hw_training_pattern(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index ec6db8d..70bf935 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -99,13 +99,13 @@ bool is_same_timing(
- }
- 
- static bool is_sharable_clk_src(
--	const struct core_stream *stream_with_clk_src,
--	const struct core_stream *stream)
-+	const struct pipe_ctx *pipe_with_clk_src,
-+	const struct pipe_ctx *pipe)
- {
--	enum clock_source_id id = stream_with_clk_src->clock_source->id;
-+	enum clock_source_id id = pipe_with_clk_src->clock_source->id;
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	enum dce_version dce_ver = dal_adapter_service_get_dce_version(
--			stream->sink->link->adapter_srv);
-+		pipe->stream->sink->link->adapter_srv);
- 
- 	/* Currently no clocks are shared for DCE 10 until VBIOS behaviour
- 	 * is verified for this use case
-@@ -114,37 +114,32 @@ static bool is_sharable_clk_src(
- 		return false;
- #endif
- 
--	if (stream_with_clk_src->clock_source == NULL)
-+	if (pipe_with_clk_src->clock_source == NULL)
- 		return false;
- 
- 	if (id == CLOCK_SOURCE_ID_EXTERNAL)
- 		return false;
- 
--
- 	if(!is_same_timing(
--		&stream_with_clk_src->public.timing, &stream->public.timing))
-+		&pipe_with_clk_src->stream->public.timing,
-+		&pipe->stream->public.timing))
- 		return false;
- 
- 	return true;
- }
- 
- struct clock_source *find_used_clk_src_for_sharing(
--					struct validate_context *context,
--					struct core_stream *stream)
-+					struct resource_context *res_ctx,
-+					struct pipe_ctx *pipe_ctx)
- {
--	uint8_t i, j;
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *clock_source_stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
-+	uint8_t i;
- 
--			if (clock_source_stream->clock_source == NULL)
--				continue;
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (res_ctx->pipe_ctx[i].clock_source == NULL)
-+			continue;
- 
--			if (is_sharable_clk_src(clock_source_stream, stream))
--				return clock_source_stream->clock_source;
--		}
-+		if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
-+			return res_ctx->pipe_ctx[i].clock_source;
- 	}
- 
- 	return NULL;
-@@ -236,7 +231,7 @@ static enum pixel_format convert_pixel_format_to_dalsurface(
- 
- static void calculate_viewport(
- 		const struct dc_surface *surface,
--		struct core_stream *stream)
-+		struct pipe_ctx *pipe_ctx)
- {
- 	const struct rect src = surface->src_rect;
- 	const struct rect clip = surface->clip_rect;
-@@ -245,61 +240,59 @@ static void calculate_viewport(
- 	/* offset = src.ofs + (clip.ofs - dst.ofs) * scl_ratio
- 	 * num_pixels = clip.num_pix * scl_ratio
- 	 */
--	stream->viewport.x = src.x + (clip.x - dst.x) * src.width / dst.width;
--	stream->viewport.width = clip.width * src.width / dst.width;
-+	pipe_ctx->viewport.x = src.x + (clip.x - dst.x) * src.width / dst.width;
-+	pipe_ctx->viewport.width = clip.width * src.width / dst.width;
- 
--	stream->viewport.y = src.y + (clip.y - dst.y) * src.height / dst.height;
--	stream->viewport.height = clip.height * src.height / dst.height;
-+	pipe_ctx->viewport.y = src.y + (clip.y - dst.y) * src.height / dst.height;
-+	pipe_ctx->viewport.height = clip.height * src.height / dst.height;
- 
- 	/* Minimum viewport such that 420/422 chroma vp is non 0 */
--	if (stream->viewport.width < 2)
--	{
--		stream->viewport.width = 2;
--	}
--	if (stream->viewport.height < 2)
--	{
--		stream->viewport.height = 2;
--	}
-+	if (pipe_ctx->viewport.width < 2)
-+		pipe_ctx->viewport.width = 2;
-+	if (pipe_ctx->viewport.height < 2)
-+		pipe_ctx->viewport.height = 2;
- }
- 
- static void calculate_overscan(
- 		const struct dc_surface *surface,
--		struct core_stream *stream)
-+		struct pipe_ctx *pipe_ctx)
- {
--	stream->overscan.left = stream->public.dst.x;
-+	struct core_stream *stream = pipe_ctx->stream;
-+
-+	pipe_ctx->overscan.left = stream->public.dst.x;
- 	if (stream->public.src.x < surface->clip_rect.x)
--		stream->overscan.left += (surface->clip_rect.x
-+		pipe_ctx->overscan.left += (surface->clip_rect.x
- 			- stream->public.src.x) * stream->public.dst.width
- 			/ stream->public.src.width;
- 
--	stream->overscan.right = stream->public.timing.h_addressable
-+	pipe_ctx->overscan.right = stream->public.timing.h_addressable
- 		- stream->public.dst.x - stream->public.dst.width;
- 	if (stream->public.src.x + stream->public.src.width
- 		> surface->clip_rect.x + surface->clip_rect.width)
--		stream->overscan.right = stream->public.timing.h_addressable -
-+		pipe_ctx->overscan.right = stream->public.timing.h_addressable -
- 			dal_fixed31_32_floor(dal_fixed31_32_div(
- 				dal_fixed31_32_from_int(
--						stream->viewport.width),
--						stream->ratios.horz)) -
--						stream->overscan.left;
-+						pipe_ctx->viewport.width),
-+						pipe_ctx->ratios.horz)) -
-+						pipe_ctx->overscan.left;
- 
- 
--	stream->overscan.top = stream->public.dst.y;
-+	pipe_ctx->overscan.top = stream->public.dst.y;
- 	if (stream->public.src.y < surface->clip_rect.y)
--		stream->overscan.top += (surface->clip_rect.y
-+		pipe_ctx->overscan.top += (surface->clip_rect.y
- 			- stream->public.src.y) * stream->public.dst.height
- 			/ stream->public.src.height;
- 
--	stream->overscan.bottom = stream->public.timing.v_addressable
-+	pipe_ctx->overscan.bottom = stream->public.timing.v_addressable
- 		- stream->public.dst.y - stream->public.dst.height;
- 	if (stream->public.src.y + stream->public.src.height
- 		> surface->clip_rect.y + surface->clip_rect.height)
--		stream->overscan.bottom = stream->public.timing.v_addressable -
-+		pipe_ctx->overscan.bottom = stream->public.timing.v_addressable -
- 			dal_fixed31_32_floor(dal_fixed31_32_div(
- 				dal_fixed31_32_from_int(
--						stream->viewport.height),
--						stream->ratios.vert)) -
--						stream->overscan.top;
-+						pipe_ctx->viewport.height),
-+						pipe_ctx->ratios.vert)) -
-+						pipe_ctx->overscan.top;
- 
- 
- 	/* TODO: Add timing overscan to finalize overscan calculation*/
-@@ -307,81 +300,81 @@ static void calculate_overscan(
- 
- static void calculate_scaling_ratios(
- 		const struct dc_surface *surface,
--		struct core_stream *stream)
-+		struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	const uint32_t in_w = stream->public.src.width;
- 	const uint32_t in_h = stream->public.src.height;
- 	const uint32_t out_w = stream->public.dst.width;
- 	const uint32_t out_h = stream->public.dst.height;
- 
--	stream->ratios.horz = dal_fixed31_32_from_fraction(
-+	pipe_ctx->ratios.horz = dal_fixed31_32_from_fraction(
- 					surface->src_rect.width,
- 					surface->dst_rect.width);
--	stream->ratios.vert = dal_fixed31_32_from_fraction(
-+	pipe_ctx->ratios.vert = dal_fixed31_32_from_fraction(
- 					surface->src_rect.height,
- 					surface->dst_rect.height);
- 
- 	if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
--		stream->ratios.horz.value *= 2;
-+		pipe_ctx->ratios.horz.value *= 2;
- 	else if (surface->stereo_format
- 					== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
--		stream->ratios.vert.value *= 2;
-+		pipe_ctx->ratios.vert.value *= 2;
- 
--	stream->ratios.vert.value = div64_s64(stream->ratios.vert.value * in_h,
-+	pipe_ctx->ratios.vert.value = div64_s64(pipe_ctx->ratios.vert.value * in_h,
- 			out_h);
--	stream->ratios.horz.value = div64_s64(stream->ratios.horz.value * in_w ,
-+	pipe_ctx->ratios.horz.value = div64_s64(pipe_ctx->ratios.horz.value * in_w,
- 			out_w);
- 
--	stream->ratios.horz_c = stream->ratios.horz;
--	stream->ratios.vert_c = stream->ratios.vert;
-+	pipe_ctx->ratios.horz_c = pipe_ctx->ratios.horz;
-+	pipe_ctx->ratios.vert_c = pipe_ctx->ratios.vert;
- 
--	if (stream->format == PIXEL_FORMAT_420BPP12) {
--		stream->ratios.horz_c.value /= 2;
--		stream->ratios.vert_c.value /= 2;
--	} else if (stream->format == PIXEL_FORMAT_422BPP16) {
--		stream->ratios.horz_c.value /= 2;
-+	if (pipe_ctx->format == PIXEL_FORMAT_420BPP12) {
-+		pipe_ctx->ratios.horz_c.value /= 2;
-+		pipe_ctx->ratios.vert_c.value /= 2;
-+	} else if (pipe_ctx->format == PIXEL_FORMAT_422BPP16) {
-+		pipe_ctx->ratios.horz_c.value /= 2;
- 	}
- }
- 
--/*TODO: per pipe not per stream*/
- void build_scaling_params(
- 	const struct dc_surface *surface,
--	struct core_stream *stream)
-+	struct pipe_ctx *pipe_ctx)
- {
- 	/* Important: scaling ratio calculation requires pixel format,
- 	 * overscan calculation requires scaling ratios and viewport
- 	 * and lb depth/taps calculation requires overscan. Call sequence
- 	 * is therefore important */
--	stream->format = convert_pixel_format_to_dalsurface(surface->format);
-+	pipe_ctx->format = convert_pixel_format_to_dalsurface(surface->format);
- 
--	calculate_viewport(surface, stream);
-+	calculate_viewport(surface, pipe_ctx);
- 
--	calculate_scaling_ratios(surface, stream);
-+	calculate_scaling_ratios(surface, pipe_ctx);
- 
--	calculate_overscan(surface, stream);
-+	calculate_overscan(surface, pipe_ctx);
- 
- 	/* Check if scaling is required update taps if not */
--	if (dal_fixed31_32_u2d19(stream->ratios.horz) == 1 << 19)
--		stream->taps.h_taps = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.horz) == 1 << 19)
-+		pipe_ctx->taps.h_taps = 1;
- 	else
--		stream->taps.h_taps = surface->scaling_quality.h_taps;
-+		pipe_ctx->taps.h_taps = surface->scaling_quality.h_taps;
- 
--	if (dal_fixed31_32_u2d19(stream->ratios.horz_c) == 1 << 19)
--		stream->taps.h_taps_c = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.horz_c) == 1 << 19)
-+		pipe_ctx->taps.h_taps_c = 1;
- 	else
--		stream->taps.h_taps_c = surface->scaling_quality.h_taps_c;
-+		pipe_ctx->taps.h_taps_c = surface->scaling_quality.h_taps_c;
- 
--	if (dal_fixed31_32_u2d19(stream->ratios.vert) == 1 << 19)
--		stream->taps.v_taps = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.vert) == 1 << 19)
-+		pipe_ctx->taps.v_taps = 1;
- 	else
--		stream->taps.v_taps = surface->scaling_quality.v_taps;
-+		pipe_ctx->taps.v_taps = surface->scaling_quality.v_taps;
- 
--	if (dal_fixed31_32_u2d19(stream->ratios.vert_c) == 1 << 19)
--		stream->taps.v_taps_c = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.vert_c) == 1 << 19)
-+		pipe_ctx->taps.v_taps_c = 1;
- 	else
--		stream->taps.v_taps_c = surface->scaling_quality.v_taps_c;
-+		pipe_ctx->taps.v_taps_c = surface->scaling_quality.v_taps_c;
- 
--	dal_logger_write(stream->ctx->logger,
-+	dal_logger_write(pipe_ctx->stream->ctx->logger,
- 				LOG_MAJOR_DCP,
- 				LOG_MINOR_DCP_SCALER,
- 				"%s: Overscan:\n bot:%d left:%d right:%d "
-@@ -389,14 +382,14 @@ void build_scaling_params(
- 				"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
- 				"y:%d\n",
- 				__func__,
--				stream->overscan.bottom,
--				stream->overscan.left,
--				stream->overscan.right,
--				stream->overscan.top,
--				stream->viewport.height,
--				stream->viewport.width,
--				stream->viewport.x,
--				stream->viewport.y,
-+				pipe_ctx->overscan.bottom,
-+				pipe_ctx->overscan.left,
-+				pipe_ctx->overscan.right,
-+				pipe_ctx->overscan.top,
-+				pipe_ctx->viewport.height,
-+				pipe_ctx->viewport.width,
-+				pipe_ctx->viewport.x,
-+				pipe_ctx->viewport.y,
- 				surface->dst_rect.height,
- 				surface->dst_rect.width,
- 				surface->dst_rect.x,
-@@ -407,32 +400,25 @@ void build_scaling_params_for_context(
- 	const struct dc *dc,
- 	struct validate_context *context)
- {
--	uint8_t i, j, k;
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--		if (context->target_flags[i].unchanged)
--			continue;
--		for (j = 0; j < target->status.surface_count; j++) {
--			const struct dc_surface *surface =
--				target->status.surfaces[j];
--			for (k = 0; k < target->public.stream_count; k++) {
--				struct core_stream *stream =
--					DC_STREAM_TO_CORE(
--						target->public.streams[k]);
--
--				build_scaling_params(surface, stream);
--			}
--		}
-+	uint8_t i;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (context->res_ctx.pipe_ctx[i].surface != NULL &&
-+				context->res_ctx.pipe_ctx[i].stream != NULL)
-+			build_scaling_params(
-+				&context->res_ctx.pipe_ctx[i].surface->public,
-+				&context->res_ctx.pipe_ctx[i]);
- 	}
- }
- 
--bool logical_attach_surfaces_to_target(
-+bool attach_surfaces_to_context(
- 		struct dc_surface *surfaces[],
- 		uint8_t surface_count,
--		struct dc_target *dc_target)
-+		struct dc_target *dc_target,
-+		struct validate_context *context)
- {
--	uint8_t i;
--	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	uint8_t i, j, k;
-+	struct dc_target_status *target_status = NULL;
- 
- 	if (surface_count > MAX_SURFACE_NUM) {
- 		dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n",
-@@ -440,16 +426,46 @@ bool logical_attach_surfaces_to_target(
- 		return false;
- 	}
- 
--	for (i = 0; i < target->status.surface_count; i++)
--		dc_surface_release(target->status.surfaces[i]);
-+	for (i = 0; i < context->target_count; i++)
-+		if (&context->targets[i]->public == dc_target) {
-+			target_status = &context->target_status[i];
-+			break;
-+		}
-+	if (target_status == NULL) {
-+		dm_error("Existing target not found; failed to attach surfaces\n");
-+		return false;
-+	}
-+
-+	for (i = 0; i < target_status->surface_count; i++)
-+		dc_surface_release(target_status->surfaces[i]);
- 
- 	for (i = 0; i < surface_count; i++) {
--		struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
--		surface->status.dc_target = &target->public;
--		target->status.surfaces[i] = surfaces[i];
--		dc_surface_retain(target->status.surfaces[i]);
-+		target_status->surfaces[i] = surfaces[i];
-+		dc_surface_retain(target_status->surfaces[i]);
-+	}
-+	target_status->surface_count = surface_count;
-+
-+	for (i = 0; i < dc_target->stream_count; i++) {
-+		k = 0;
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct core_surface *surface =
-+					DC_SURFACE_TO_CORE(surfaces[k]);
-+
-+			if (context->res_ctx.pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(dc_target->streams[i]))
-+				continue;
-+			if (k == surface_count) {
-+				/* this means there are more pipes per stream
-+				 * than there are planes and makes no sense
-+				 */
-+				BREAK_TO_DEBUGGER();
-+				continue;
-+			}
-+
-+			context->res_ctx.pipe_ctx[j].surface = surface;
-+			k++;
-+		}
- 	}
--	target->status.surface_count = surface_count;
- 
- 	return true;
- }
-@@ -492,13 +508,21 @@ static void fill_display_configs(
- 
- 		for (j = 0; j < target->public.stream_count; j++) {
- 			const struct core_stream *stream =
--			DC_STREAM_TO_CORE(target->public.streams[j]);
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct dc_pp_single_disp_config *cfg =
- 					&pp_display_cfg->disp_configs[num_cfgs];
-+			const struct pipe_ctx *pipe_ctx = NULL;
-+
-+			for (j = 0; j < MAX_PIPES; j++)
-+				if (stream ==
-+					context->res_ctx.pipe_ctx[j].stream) {
-+					pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+					break;
-+				}
- 
- 			num_cfgs++;
--			cfg->signal = stream->signal;
--			cfg->pipe_idx = stream->opp->inst;
-+			cfg->signal = pipe_ctx->signal;
-+			cfg->pipe_idx = pipe_ctx->pipe_idx;
- 			cfg->src_height = stream->public.src.height;
- 			cfg->src_width = stream->public.src.width;
- 			cfg->ddi_channel_mapping =
-@@ -582,13 +606,6 @@ void pplib_apply_display_requirements(
- /* Maximum TMDS single link pixel clock 165MHz */
- #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
- 
--static void attach_stream_to_controller(
--		struct resource_context *res_ctx,
--		struct core_stream *stream)
--{
--	res_ctx->controller_ctx[stream->controller_idx].stream = stream;
--}
--
- static void set_stream_engine_in_use(
- 		struct resource_context *res_ctx,
- 		struct stream_encoder *stream_enc)
-@@ -614,24 +631,28 @@ static void set_audio_in_use(
- 	}
- }
- 
--static bool assign_first_free_controller(
-+static int8_t acquire_first_free_pipe(
- 		struct resource_context *res_ctx,
- 		struct core_stream *stream)
- {
- 	uint8_t i;
--	for (i = 0; i < res_ctx->pool.controller_count; i++) {
--		if (!res_ctx->controller_ctx[i].stream) {
--			stream->tg = res_ctx->pool.timing_generators[i];
--			stream->mi = res_ctx->pool.mis[i];
--			stream->ipp = res_ctx->pool.ipps[i];
--			stream->xfm = res_ctx->pool.transforms[i];
--			stream->opp = res_ctx->pool.opps[i];
--			stream->controller_idx = i;
--			stream->dis_clk = res_ctx->pool.display_clock;
--			return true;
-+	for (i = 0; i < res_ctx->pool.pipe_count; i++) {
-+		if (!res_ctx->pipe_ctx[i].stream) {
-+			struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+
-+			pipe_ctx->tg = res_ctx->pool.timing_generators[i];
-+			pipe_ctx->mi = res_ctx->pool.mis[i];
-+			pipe_ctx->ipp = res_ctx->pool.ipps[i];
-+			pipe_ctx->xfm = res_ctx->pool.transforms[i];
-+			pipe_ctx->opp = res_ctx->pool.opps[i];
-+			pipe_ctx->dis_clk = res_ctx->pool.display_clock;
-+			pipe_ctx->pipe_idx = i;
-+
-+			pipe_ctx->stream = stream;
-+			return i;
- 		}
- 	}
--	return false;
-+	return -1;
- }
- 
- static struct stream_encoder *find_first_free_match_stream_enc_for_link(
-@@ -704,9 +725,10 @@ static bool check_timing_change(struct core_stream *cur_stream,
- 					&new_stream->public.timing);
- }
- 
--static void set_stream_signal(struct core_stream *stream)
-+static void set_stream_signal(struct pipe_ctx *pipe_ctx)
- {
--	struct dc_sink *dc_sink = (struct dc_sink *)stream->public.sink;
-+	struct dc_sink *dc_sink =
-+		(struct dc_sink *) pipe_ctx->stream->public.sink;
- 
- 	/* For asic supports dual link DVI, we should adjust signal type
- 	 * based on timing pixel clock. If pixel clock more than 165Mhz,
-@@ -714,21 +736,21 @@ static void set_stream_signal(struct core_stream *stream)
- 	 */
- 	if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
- 			dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK) {
--		if (stream->public.timing.pix_clk_khz >
--			TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
-+		if (pipe_ctx->stream->public.timing.pix_clk_khz >
-+						TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
- 			dc_sink->sink_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
- 		else
- 			dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- 	}
- 
--	stream->signal = dc_sink->sink_signal;
-+	pipe_ctx->signal = dc_sink->sink_signal;
- }
- 
- enum dc_status map_resources(
- 		const struct dc *dc,
- 		struct validate_context *context)
- {
--	uint8_t i, j;
-+	uint8_t i, j, k;
- 
- 	/* mark resources used for targets that are already active */
- 	for (i = 0; i < context->target_count; i++) {
-@@ -741,21 +763,29 @@ enum dc_status map_resources(
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			attach_stream_to_controller(
--				&context->res_ctx,
--				stream);
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
- 
--			set_stream_engine_in_use(
--				&context->res_ctx,
--				stream->stream_enc);
-+				if (dc->current_context.res_ctx.pipe_ctx[k].stream
-+					!= stream)
-+					continue;
- 
--			reference_clock_source(
--				&context->res_ctx,
--				stream->clock_source);
-+				*pipe_ctx =
-+					dc->current_context.res_ctx.pipe_ctx[k];
-+				pipe_ctx->flags.timing_changed = false;
-+				pipe_ctx->flags.unchanged = true;
-+
-+				set_stream_engine_in_use(
-+					&context->res_ctx,
-+					pipe_ctx->stream_enc);
-+
-+				reference_clock_source(
-+					&context->res_ctx,
-+					pipe_ctx->clock_source);
- 
--			if (stream->audio) {
- 				set_audio_in_use(&context->res_ctx,
--					stream->audio);
-+					pipe_ctx->audio);
- 			}
- 		}
- 	}
-@@ -768,49 +798,48 @@ enum dc_status map_resources(
- 			continue;
- 
- 		for (j = 0; j < target->public.stream_count; j++) {
-+			struct pipe_ctx *pipe_ctx = NULL;
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct core_stream *curr_stream;
- 
--			if (!assign_first_free_controller(
--					&context->res_ctx, stream))
-+			int8_t pipe_idx = acquire_first_free_pipe(
-+						&context->res_ctx, stream);
-+			if (pipe_idx < 0)
- 				return DC_NO_CONTROLLER_RESOURCE;
- 
--			attach_stream_to_controller(&context->res_ctx, stream);
--
--			set_stream_signal(stream);
-+			pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
-+			set_stream_signal(pipe_ctx);
- 
- 			curr_stream =
--				dc->current_context.res_ctx.controller_ctx
--				[stream->controller_idx].stream;
--			context->res_ctx.controller_ctx[stream->controller_idx]
--			.flags.timing_changed =
-+				dc->current_context.res_ctx.pipe_ctx[pipe_idx].stream;
-+			context->res_ctx.pipe_ctx[pipe_idx].flags.timing_changed =
- 				check_timing_change(curr_stream, stream);
- 
--			stream->stream_enc =
-+			pipe_ctx->stream_enc =
- 				find_first_free_match_stream_enc_for_link(
- 					&context->res_ctx,
- 					stream->sink->link);
- 
--			if (!stream->stream_enc)
-+			if (!pipe_ctx->stream_enc)
- 				return DC_NO_STREAM_ENG_RESOURCE;
- 
- 			set_stream_engine_in_use(
- 					&context->res_ctx,
--					stream->stream_enc);
-+					pipe_ctx->stream_enc);
- 
- 			/* TODO: Add check if ASIC support and EDID audio */
- 			if (!stream->sink->converter_disable_audio &&
- 						dc_is_audio_capable_signal(
--						stream->signal)) {
--				stream->audio = find_first_free_audio(
-+						pipe_ctx->signal)) {
-+				pipe_ctx->audio = find_first_free_audio(
- 						&context->res_ctx);
- 
--				if (!stream->audio)
-+				if (!pipe_ctx->audio)
- 					return DC_NO_STREAM_AUDIO_RESOURCE;
- 
- 				set_audio_in_use(&context->res_ctx,
--						stream->audio);
-+						pipe_ctx->audio);
- 			}
- 		}
- 	}
-@@ -819,13 +848,13 @@ enum dc_status map_resources(
- }
- 
- static enum ds_color_space build_default_color_space(
--		struct core_stream *stream)
-+		struct pipe_ctx *pipe_ctx)
- {
- 	enum ds_color_space color_space =
- 			DS_COLOR_SPACE_SRGB_FULLRANGE;
--	struct dc_crtc_timing *timing = &stream->public.timing;
-+	struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
- 
--	switch (stream->signal) {
-+	switch (pipe_ctx->signal) {
- 	/* TODO: implement other signal color space setting */
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-@@ -934,9 +963,11 @@ static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 	}
- }
- 
--static void set_avi_info_frame(struct hw_info_packet *info_packet,
--		struct core_stream *stream)
-+static void set_avi_info_frame(
-+	struct hw_info_packet *info_packet,
-+		struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	enum ds_color_space color_space = DS_COLOR_SPACE_UNKNOWN;
- 	struct info_frame info_frame = { {0} };
- 	uint32_t pixel_encoding = 0;
-@@ -950,7 +981,7 @@ static void set_avi_info_frame(struct hw_info_packet *info_packet,
- 	if (info_packet == NULL)
- 		return;
- 
--	color_space = build_default_color_space(stream);
-+	color_space = build_default_color_space(pipe_ctx);
- 
- 	/* Initialize header */
- 	info_frame.avi_info_packet.info_packet_hdmi.bits.header.
-@@ -1223,7 +1254,7 @@ static void set_vendor_info_packet(struct core_stream *stream,
- 	info_packet->valid = true;
- }
- 
--void build_info_frame(struct core_stream *stream)
-+void build_info_frame(struct pipe_ctx *pipe_ctx)
- {
- 	enum signal_type signal = SIGNAL_TYPE_NONE;
- 	struct hw_info_frame info_frame = { { 0 } };
-@@ -1235,15 +1266,16 @@ void build_info_frame(struct core_stream *stream)
- 	info_frame.spd_packet.valid = false;
- 	info_frame.vsc_packet.valid = false;
- 
--	signal = stream->sink->public.sink_signal;
-+	signal = pipe_ctx->stream->sink->public.sink_signal;
- 
- 	/* HDMi and DP have different info packets*/
- 	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
--		set_avi_info_frame(&info_frame.avi_info_packet,
--				stream);
--		set_vendor_info_packet(stream, &info_frame.vendor_info_packet);
-+		set_avi_info_frame(
-+			&info_frame.avi_info_packet, pipe_ctx);
-+		set_vendor_info_packet(
-+			pipe_ctx->stream, &info_frame.vendor_info_packet);
- 	}
- 
- 	translate_info_frame(&info_frame,
--			&stream->encoder_info_frame);
-+			&pipe_ctx->encoder_info_frame);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index e8579bc..f00b5af 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -65,12 +65,20 @@ static void construct(
- 
- static void destruct(struct core_target *core_target)
- {
--	int i;
-+	int i, j;
-+	struct validate_context *context =
-+				&core_target->ctx->dc->current_context;
- 
--	for (i = 0; i < core_target->status.surface_count; i++) {
--		dc_surface_release(core_target->status.surfaces[i]);
--		core_target->status.surfaces[i] = NULL;
-+	for (i = 0; i < context->target_count; i++) {
-+		if (context->targets[i] != core_target)
-+			continue;
-+		for (j = 0; j < context->target_status[i].surface_count; j++)
-+			dc_surface_release(
-+				context->target_status[i].surfaces[j]);
-+		context->target_status[i].surface_count = 0;
-+		break;
- 	}
-+
- 	for (i = 0; i < core_target->public.stream_count; i++) {
- 		dc_stream_release(
- 			(struct dc_stream *)core_target->public.streams[i]);
-@@ -101,8 +109,15 @@ void dc_target_release(struct dc_target *dc_target)
- const struct dc_target_status *dc_target_get_status(
- 					const struct dc_target* dc_target)
- {
-+	uint8_t i;
- 	struct core_target* target = DC_TARGET_TO_CORE(dc_target);
--	return &target->status;
-+	struct dc *dc = target->ctx->dc;
-+
-+	for (i = 0; i < dc->current_context.target_count; i++)
-+		if (target == dc->current_context.targets[i])
-+			return &dc->current_context.target_status[i];
-+
-+	return NULL;
- }
- 
- struct dc_target *dc_create_target_for_streams(
-@@ -169,26 +184,28 @@ bool dc_commit_surfaces_to_target(
- 	int i, j;
- 	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--
-+	struct dc_target_status *status = NULL;
-+	struct validate_context *context;
- 	int current_enabled_surface_count = 0;
- 	int new_enabled_surface_count = 0;
- 
--	if (!dal_adapter_service_is_in_accelerated_mode(
--						dc->res_pool.adapter_srv) ||
--			dc->current_context.target_count == 0) {
--		return false;
--	}
--
--	for (i = 0; i < dc->current_context.target_count; i++)
--		if (target == dc->current_context.targets[i])
--			break;
-+	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
-+	*context = dc->current_context;
- 
- 	/* Cannot commit surface to a target that is not commited */
--	if (i == dc->current_context.target_count)
--		return false;
-+	for (i = 0; i < context->target_count; i++)
-+		if (target == context->targets[i])
-+			break;
-+	status = &context->target_status[i];
-+	if (!dal_adapter_service_is_in_accelerated_mode(
-+						dc->res_pool.adapter_srv)
-+		|| i == context->target_count) {
-+		BREAK_TO_DEBUGGER();
-+		goto unexpected_fail;
-+	}
- 
--	for (i = 0; i < target->status.surface_count; i++)
--		if (target->status.surfaces[i]->visible)
-+	for (i = 0; i < status->surface_count; i++)
-+		if (status->surfaces[i]->visible)
- 			current_enabled_surface_count++;
- 
- 	for (i = 0; i < new_surface_count; i++)
-@@ -204,83 +221,100 @@ bool dc_commit_surfaces_to_target(
- 				dc_target);
- 
- 
--	if (!logical_attach_surfaces_to_target(
--						new_surfaces,
--						new_surface_count,
--						dc_target)) {
-+	if (!attach_surfaces_to_context(
-+			new_surfaces, new_surface_count, dc_target, context)) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
- 	}
- 
- 	for (i = 0; i < new_surface_count; i++)
--		for (j = 0; j < target->public.stream_count; j++)
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (context->res_ctx.pipe_ctx[j].surface !=
-+					DC_SURFACE_TO_CORE(new_surfaces[i]))
-+				continue;
-+
- 			build_scaling_params(
--				new_surfaces[i],
--				DC_STREAM_TO_CORE(target->public.streams[j]));
-+				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
-+		}
- 
--	if (dc->res_pool.funcs->validate_bandwidth(dc, &dc->current_context)
--								!= DC_OK) {
-+	if (dc->res_pool.funcs->validate_bandwidth(dc, context) != DC_OK) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
- 	}
- 
--	if (prev_disp_clk < dc->current_context.bw_results.dispclk_khz) {
--		dc->hwss.program_bw(dc, &dc->current_context);
--		pplib_apply_display_requirements(dc, &dc->current_context,
--				&dc->current_context.pp_display_cfg);
-+	if (prev_disp_clk < context->bw_results.dispclk_khz) {
-+		dc->hwss.program_bw(dc, context);
-+		pplib_apply_display_requirements(dc, context,
-+						&context->pp_display_cfg);
- 	}
- 
- 	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
- 		dc_target_disable_memory_requests(dc_target);
- 
--	for (i = 0; i < new_surface_count; i++) {
--		struct dc_surface *surface = new_surfaces[i];
--		struct core_surface *core_surface = DC_SURFACE_TO_CORE(surface);
--		struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[0]);
--		bool is_valid_address =
--				validate_surface_address(surface->address);
--
--
--		dal_logger_write(dc->ctx->logger,
--					LOG_MAJOR_INTERFACE_TRACE,
--					LOG_MINOR_COMPONENT_DC,
--					"0x%x:",
--					surface);
--
--		if (surface->gamma_correction) {
--			struct core_gamma *gamma = DC_GAMMA_TO_CORE(
--						surface->gamma_correction);
--
--			dc->hwss.set_gamma_correction(
--					stream->ipp,
--					stream->opp,
--					gamma, core_surface);
-+	for (i = 0; i < new_surface_count; i++)
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct dc_surface *dc_surface = new_surfaces[i];
-+			struct core_surface *surface =
-+						DC_SURFACE_TO_CORE(dc_surface);
-+			struct pipe_ctx *pipe_ctx =
-+						&context->res_ctx.pipe_ctx[j];
-+
-+			if (pipe_ctx->surface !=
-+					DC_SURFACE_TO_CORE(new_surfaces[i]))
-+				continue;
-+
-+			dal_logger_write(dc->ctx->logger,
-+						LOG_MAJOR_INTERFACE_TRACE,
-+						LOG_MINOR_COMPONENT_DC,
-+						"Pipe:%d 0x%x: src: %d, %d, %d,"
-+						" %d; dst: %d, %d, %d, %d;\n",
-+						pipe_ctx->pipe_idx,
-+						dc_surface,
-+						dc_surface->src_rect.x,
-+						dc_surface->src_rect.y,
-+						dc_surface->src_rect.width,
-+						dc_surface->src_rect.height,
-+						dc_surface->dst_rect.x,
-+						dc_surface->dst_rect.y,
-+						dc_surface->dst_rect.width,
-+						dc_surface->dst_rect.height);
-+
-+			if (dc_surface->gamma_correction) {
-+				struct core_gamma *gamma = DC_GAMMA_TO_CORE(
-+						dc_surface->gamma_correction);
-+
-+				dc->hwss.set_gamma_correction(
-+							pipe_ctx->ipp,
-+							pipe_ctx->opp,
-+							gamma, surface);
-+			}
-+
-+			dc->hwss.set_plane_config(dc, surface, pipe_ctx);
-+
-+			if (validate_surface_address(dc_surface->address))
-+				dc->hwss.update_plane_addrs(
-+					dc, &context->res_ctx, surface);
- 		}
- 
--		dc->hwss.set_plane_config(dc, core_surface, target);
--
--		if (is_valid_address)
--			dc->hwss.update_plane_address(dc, core_surface, target);
--	}
--
- 	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
- 		dc_target_enable_memory_requests(dc_target);
- 
- 	/* Lower display clock if necessary */
--	if (prev_disp_clk > dc->current_context.bw_results.dispclk_khz) {
--		dc->hwss.program_bw(dc, &dc->current_context);
--		pplib_apply_display_requirements(dc, &dc->current_context,
--				&dc->current_context.pp_display_cfg);
-+	if (prev_disp_clk > context->bw_results.dispclk_khz) {
-+		dc->hwss.program_bw(dc, context);
-+		pplib_apply_display_requirements(dc, context,
-+						&context->pp_display_cfg);
- 	}
- 
-+	dc->current_context = *context;
-+	dm_free(dc->ctx, context);
- 	return true;
- 
- unexpected_fail:
- 	for (i = 0; i < new_surface_count; i++) {
--		target->status.surfaces[i] = NULL;
-+		status->surfaces[i] = NULL;
- 	}
--	target->status.surface_count = 0;
-+	status->surface_count = 0;
- 
- 	return false;
- }
-@@ -298,38 +332,48 @@ bool dc_target_is_connected_to_sink(
- 	return false;
- }
- 
--void dc_target_enable_memory_requests(struct dc_target *target)
-+void dc_target_enable_memory_requests(struct dc_target *dc_target)
- {
--	uint8_t i;
--	struct core_target *core_target = DC_TARGET_TO_CORE(target);
--	for (i = 0; i < core_target->public.stream_count; i++) {
--		struct timing_generator *tg =
--			DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct resource_context *res_ctx =
-+		&target->ctx->dc->current_context.res_ctx;
-+
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
- 
--		if (!tg->funcs->set_blank(tg, false)) {
--			dm_error("DC: failed to unblank crtc!\n");
--			BREAK_TO_DEBUGGER();
-+			if (!tg->funcs->set_blank(tg, false)) {
-+				dm_error("DC: failed to unblank crtc!\n");
-+				BREAK_TO_DEBUGGER();
-+			}
- 		}
- 	}
- }
- 
--void dc_target_disable_memory_requests(struct dc_target *target)
-+void dc_target_disable_memory_requests(struct dc_target *dc_target)
- {
--	uint8_t i;
--	struct core_target *core_target = DC_TARGET_TO_CORE(target);
--	for (i = 0; i < core_target->public.stream_count; i++) {
--	struct timing_generator *tg =
--		DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct resource_context *res_ctx =
-+		&target->ctx->dc->current_context.res_ctx;
- 
--		if (NULL == tg) {
--			dm_error("DC: timing generator is NULL!\n");
--			BREAK_TO_DEBUGGER();
--			continue;
--		}
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
- 
--		if (false == tg->funcs->set_blank(tg, true)) {
--			dm_error("DC: failed to blank crtc!\n");
--			BREAK_TO_DEBUGGER();
-+			if (!tg->funcs->set_blank(tg, true)) {
-+				dm_error("DC: failed to blank crtc!\n");
-+				BREAK_TO_DEBUGGER();
-+			}
- 		}
- 	}
- }
-@@ -341,25 +385,42 @@ bool dc_target_set_cursor_attributes(
- 	struct dc_target *dc_target,
- 	const struct dc_cursor_attributes *attributes)
- {
--	struct core_target *core_target;
--	struct input_pixel_processor *ipp;
-+	uint8_t i, j;
-+	struct core_target *target;
-+	struct resource_context *res_ctx;
- 
- 	if (NULL == dc_target) {
- 		dm_error("DC: dc_target is NULL!\n");
- 			return false;
- 
- 	}
-+	if (NULL == attributes) {
-+		dm_error("DC: attributes is NULL!\n");
-+			return false;
- 
--	core_target = DC_TARGET_TO_CORE(dc_target);
--	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
--
--	if (NULL == ipp) {
--		dm_error("DC: input pixel processor is NULL!\n");
--		return false;
- 	}
- 
--	if (true == ipp->funcs->ipp_cursor_set_attributes(ipp, attributes))
--		return true;
-+	target = DC_TARGET_TO_CORE(dc_target);
-+	res_ctx = &target->ctx->dc->current_context.res_ctx;
-+
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct input_pixel_processor *ipp =
-+						res_ctx->pipe_ctx[j].ipp;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
-+
-+			/* As of writing of this code cursor is on the top
-+			 * plane so we only need to set it on first pipe we
-+			 * find. May need to make this code dce specific later.
-+			 */
-+			if (ipp->funcs->ipp_cursor_set_attributes(
-+							ipp, attributes))
-+				return true;
-+		}
-+	}
- 
- 	return false;
- }
-@@ -368,8 +429,9 @@ bool dc_target_set_cursor_position(
- 	struct dc_target *dc_target,
- 	const struct dc_cursor_position *position)
- {
--	struct core_target *core_target;
--	struct input_pixel_processor *ipp;
-+	uint8_t i, j;
-+	struct core_target *target;
-+	struct resource_context *res_ctx;
- 
- 	if (NULL == dc_target) {
- 		dm_error("DC: dc_target is NULL!\n");
-@@ -381,62 +443,67 @@ bool dc_target_set_cursor_position(
- 		return false;
- 	}
- 
--	core_target = DC_TARGET_TO_CORE(dc_target);
--	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
-+	target = DC_TARGET_TO_CORE(dc_target);
-+	res_ctx = &target->ctx->dc->current_context.res_ctx;
- 
--	if (NULL == ipp) {
--		dm_error("DC: input pixel processor is NULL!\n");
--		return false;
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct input_pixel_processor *ipp =
-+						res_ctx->pipe_ctx[j].ipp;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
-+
-+			/* As of writing of this code cursor is on the top
-+			 * plane so we only need to set it on first pipe we
-+			 * find. May need to make this code dce specific later.
-+			 */
-+			if (ipp->funcs->ipp_cursor_set_position(ipp, position))
-+				return true;
-+		}
- 	}
- 
--
--	if (true == ipp->funcs->ipp_cursor_set_position(ipp, position))
--		return true;
--
- 	return false;
- }
- 
--/* TODO: #flip temporary to make flip work */
--uint8_t dc_target_get_link_index(const struct dc_target *dc_target)
-+uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- {
--	const struct core_target *target = CONST_DC_TARGET_TO_CORE(dc_target);
--	const struct core_sink *sink =
--		DC_SINK_TO_CORE(target->public.streams[0]->sink);
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct resource_context *res_ctx =
-+		&target->ctx->dc->current_context.res_ctx;
- 
--	return sink->link->public.link_index;
--}
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
- 
--uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
--{
--	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
--	struct timing_generator *tg =
--		DC_STREAM_TO_CORE(core_target->public.streams[0])->tg;
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
- 
--	return tg->funcs->get_frame_count(tg);
-+			return tg->funcs->get_frame_count(tg);
-+		}
-+	}
-+
-+	return 0;
- }
- 
- enum dc_irq_source dc_target_get_irq_src(
--	const struct dc_target *dc_target, const enum irq_type irq_type)
-+	const struct dc *dc,
-+	const struct dc_target *dc_target,
-+	const enum irq_type irq_type)
- {
-+	uint8_t i;
- 	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
--
--	/* #TODO - Remove the assumption that the controller is always in the
--	 * first stream of a core target */
- 	struct core_stream *stream =
--		DC_STREAM_TO_CORE(core_target->public.streams[0]);
--	uint8_t controller_idx = stream->controller_idx;
--
--	/* Get controller id */
--	enum controller_id crtc_id = controller_idx + 1;
--
--	/* Calculate controller offset */
--	unsigned int offset = crtc_id - CONTROLLER_ID_D0;
--	unsigned int base = irq_type;
-+			DC_STREAM_TO_CORE(core_target->public.streams[0]);
- 
--	/* Calculate irq source */
--	enum dc_irq_source src = base + offset;
-+	for (i = 0; i < MAX_PIPES; i++)
-+		if (dc->current_context.res_ctx.pipe_ctx[i].stream == stream)
-+			return irq_type + i;
- 
--	return src;
-+	return irq_type;
- }
- 
- void dc_target_log(
-@@ -453,9 +520,8 @@ void dc_target_log(
- 	dal_logger_write(dal_logger,
- 			log_major,
- 			log_minor,
--			"core_target 0x%x: surface_count=%d, stream_count=%d\n",
-+			"core_target 0x%x: stream_count=%d\n",
- 			core_target,
--			core_target->status.surface_count,
- 			core_target->public.stream_count);
- 
- 	for (i = 0; i < core_target->public.stream_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 901c8c4..9cd239c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -108,7 +108,7 @@ struct dc_surface {
- 
- 	union plane_size plane_size;
- 	struct dc_tiling_info tiling_info;
--	struct plane_colorimetry colorimetry;
-+	enum color_space color_space;
- 
- 	enum surface_pixel_format format;
- 	enum dc_rotation_angle rotation;
-@@ -125,7 +125,6 @@ struct dc_surface {
- struct dc_surface_status {
- 	struct dc_plane_address requested_address;
- 	struct dc_plane_address current_address;
--	const struct dc_target *dc_target;
- };
- 
- /*
-@@ -228,12 +227,13 @@ bool dc_target_is_connected_to_sink(
- 		const struct dc_target *dc_target,
- 		const struct dc_sink *dc_sink);
- 
--uint8_t dc_target_get_link_index(const struct dc_target *dc_target);
- uint8_t dc_target_get_controller_id(const struct dc_target *dc_target);
- 
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
- enum dc_irq_source dc_target_get_irq_src(
--	const struct dc_target *dc_target, const enum irq_type irq_type);
-+	const struct dc *dc,
-+	const struct dc_target *dc_target,
-+	const enum irq_type irq_type);
- 
- void dc_target_enable_memory_requests(struct dc_target *target);
- void dc_target_disable_memory_requests(struct dc_target *target);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 5593c17..863443b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -67,13 +67,17 @@ enum dce_environment {
- #define MAX_SURFACE_NUM 2
- #define NUM_PIXEL_FORMATS 10
- 
--enum surface_color_space {
--	SURFACE_COLOR_SPACE_SRGB = 0x0000,
--	SURFACE_COLOR_SPACE_BT601 = 0x0001,
--	SURFACE_COLOR_SPACE_BT709 = 0x0002,
--	SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004,
--	SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008,
--	SURFACE_COLOR_SPACE_XRRGB = 0x0010
-+enum color_space {
-+	COLOR_SPACE_UNKNOWN,
-+	COLOR_SPACE_SRGB_FULL_RANGE,
-+	COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	COLOR_SPACE_YPBPR601,
-+	COLOR_SPACE_YPBPR709,
-+	COLOR_SPACE_YCBCR601,
-+	COLOR_SPACE_YCBCR709,
-+	COLOR_SPACE_YCBCR601_YONLY,
-+	COLOR_SPACE_YCBCR709_YONLY,
-+	COLOR_SPACE_N_MVPU_SUPER_AA,
- };
- 
- 
-@@ -170,11 +174,6 @@ enum dc_edid_status {
- 	EDID_BAD_CHECKSUM,
- };
- 
--struct plane_colorimetry {
--	enum surface_color_space color_space;
--	bool limited_range;
--};
--
- /* audio capability from EDID*/
- struct dc_cea_audio_mode {
- 	uint8_t format_code; /* ucData[0] [6:3]*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 783d47e..efa592f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -530,7 +530,7 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- {
- 	unsigned int i;
- 
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->opps[i] != NULL)
- 			dce100_opp_destroy(&pool->opps[i]);
- 
-@@ -615,12 +615,13 @@ static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
- }
- 
- static void build_audio_output(
--	const struct core_stream *stream,
-+	const struct pipe_ctx *pipe_ctx,
- 	struct audio_output *audio_output)
- {
--	audio_output->engine_id = stream->stream_enc->id;
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	audio_output->engine_id = pipe_ctx->stream_enc->id;
- 
--	audio_output->signal = stream->signal;
-+	audio_output->signal = pipe_ctx->signal;
- 
- 	/* audio_crtc_info  */
- 
-@@ -654,44 +655,45 @@ static void build_audio_output(
- 		stream->public.timing.display_color_depth;
- 
- 	audio_output->crtc_info.requested_pixel_clock =
--			stream->pix_clk_params.requested_pix_clk;
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
- 
- 	/*
- 	 * TODO - Investigate why calculated pixel clk has to be
- 	 * requested pixel clk
- 	 */
- 	audio_output->crtc_info.calculated_pixel_clock =
--			stream->pix_clk_params.requested_pix_clk;
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
- 
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
--			stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
- 		audio_output->pll_info.dp_dto_source_clock_in_khz =
- 			dal_display_clock_get_dp_ref_clk_frequency(
--				stream->dis_clk);
-+				pipe_ctx->dis_clk);
- 	}
- 
- 	audio_output->pll_info.feed_back_divider =
--			stream->pll_settings.feedback_divider;
-+			pipe_ctx->pll_settings.feedback_divider;
- 
- 	audio_output->pll_info.dto_source =
- 		translate_to_dto_source(
--			stream->controller_idx + 1);
-+			pipe_ctx->pipe_idx + 1);
- 
- 	/* TODO hard code to enable for now. Need get from stream */
- 	audio_output->pll_info.ss_enabled = true;
- 
- 	audio_output->pll_info.ss_percentage =
--			stream->pll_settings.ss_percentage;
-+			pipe_ctx->pll_settings.ss_percentage;
- }
- 
- static void get_pixel_clock_parameters(
--	const struct core_stream *stream,
-+	const struct pipe_ctx *pipe_ctx,
- 	struct pixel_clk_params *pixel_clk_params)
- {
-+	const struct core_stream *stream = pipe_ctx->stream;
- 	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
- 	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
- 	pixel_clk_params->signal_type = stream->sink->public.sink_signal;
--	pixel_clk_params->controller_id = stream->controller_idx + 1;
-+	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
- 	/* TODO: un-hardcode*/
- 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
- 		LINK_RATE_REF_FREQ_IN_KHZ;
-@@ -701,20 +703,20 @@ static void get_pixel_clock_parameters(
- 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
- }
- 
--static enum dc_status build_stream_hw_param(struct core_stream *stream)
-+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- {
- 	/*TODO: unhardcode*/
--	stream->max_tmds_clk_from_edid_in_mhz = 0;
--	stream->max_hdmi_deep_color = COLOR_DEPTH_121212;
--	stream->max_hdmi_pixel_clock = 600000;
-+	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
-+	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	pipe_ctx->max_hdmi_pixel_clock = 600000;
- 
--	get_pixel_clock_parameters(stream, &stream->pix_clk_params);
--	stream->clock_source->funcs->get_pix_clk_dividers(
--		stream->clock_source,
--		&stream->pix_clk_params,
--		&stream->pll_settings);
-+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
-+	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-+		pipe_ctx->clock_source,
-+		&pipe_ctx->pix_clk_params,
-+		&pipe_ctx->pll_settings);
- 
--	build_audio_output(stream, &stream->audio_output);
-+	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
- 
- 	return DC_OK;
- }
-@@ -724,7 +726,7 @@ static enum dc_status validate_mapped_resource(
- 		struct validate_context *context)
- {
- 	enum dc_status status = DC_OK;
--	uint8_t i, j;
-+	uint8_t i, j, k;
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		struct core_target *target = context->targets[i];
-@@ -736,33 +738,44 @@ static enum dc_status validate_mapped_resource(
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct core_link *link = stream->sink->link;
- 
--			if (!stream->tg->funcs->validate_timing(
--					stream->tg, &stream->public.timing))
--				return DC_FAIL_CONTROLLER_VALIDATE;
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (!pipe_ctx->tg->funcs->validate_timing(
-+						pipe_ctx->tg, &stream->public.timing))
-+					return DC_FAIL_CONTROLLER_VALIDATE;
-+
-+				if (pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
-+					return status;
- 
--			if (stream->signal == SIGNAL_TYPE_VIRTUAL)
--				return status;
-+				status = build_pipe_hw_param(pipe_ctx);
- 
--			status = build_stream_hw_param(stream);
-+				if (status != DC_OK)
-+					return status;
- 
--			if (status != DC_OK)
--				return status;
-+				if (!link->link_enc->funcs->validate_output_with_stream(
-+						link->link_enc,
-+						pipe_ctx))
-+					return DC_FAIL_ENC_VALIDATE;
- 
--			if (!link->link_enc->funcs->validate_output_with_stream(
--					link->link_enc,
--					stream))
--				return DC_FAIL_ENC_VALIDATE;
-+				/* TODO: validate audio ASIC caps, encoder */
- 
--			/* TODO: validate audio ASIC caps, encoder */
-+				status = dc_link_validate_mode_timing(stream->sink,
-+						link,
-+						&stream->public.timing);
- 
--			status = dc_link_validate_mode_timing(stream->sink,
--					link,
--					&stream->public.timing);
-+				if (status != DC_OK)
-+					return status;
- 
--			if (status != DC_OK)
--				return status;
-+				build_info_frame(pipe_ctx);
- 
--			build_info_frame(stream);
-+				/* do not need to validate non root pipes */
-+				break;
-+			}
- 		}
- 	}
- 
-@@ -783,16 +796,17 @@ static void set_target_unchanged(
- 		struct validate_context *context,
- 		uint8_t target_idx)
- {
--	uint8_t i;
-+	uint8_t i, j;
- 	struct core_target *target = context->targets[target_idx];
--
- 	context->target_flags[target_idx].unchanged = true;
- 	for (i = 0; i < target->public.stream_count; i++) {
--		struct core_stream *core_stream =
-+		struct core_stream *stream =
- 			DC_STREAM_TO_CORE(target->public.streams[i]);
--		uint8_t index = core_stream->controller_idx;
--
--		context->res_ctx.controller_ctx[index].flags.unchanged = true;
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (context->res_ctx.pipe_ctx[j].stream == stream)
-+				context->res_ctx.pipe_ctx[j].flags.unchanged =
-+									true;
-+		}
- 	}
- }
- 
-@@ -800,24 +814,7 @@ static enum dc_status map_clock_resources(
- 		const struct dc *dc,
- 		struct validate_context *context)
- {
--	uint8_t i, j;
--
--	/* mark resources used for targets that are already active */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (!context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			reference_clock_source(
--				&context->res_ctx,
--				stream->clock_source);
--		}
--	}
-+	uint8_t i, j, k;
- 
- 	/* acquire new resources */
- 	for (i = 0; i < context->target_count; i++) {
-@@ -830,24 +827,35 @@ static enum dc_status map_clock_resources(
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			if (dc_is_dp_signal(stream->signal)
--				|| stream->signal == SIGNAL_TYPE_VIRTUAL)
--				stream->clock_source = context->res_ctx.
--					pool.clock_sources[DCE100_CLK_SRC_EXT];
--			else
--				stream->clock_source =
--					find_used_clk_src_for_sharing(
--							context, stream);
--			if (stream->clock_source == NULL)
--				stream->clock_source =
--					find_first_free_pll(&context->res_ctx);
--
--			if (stream->clock_source == NULL)
--				return DC_NO_CLOCK_SOURCE_RESOURCE;
--
--			reference_clock_source(
--					&context->res_ctx,
--					stream->clock_source);
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (dc_is_dp_signal(pipe_ctx->signal)
-+					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
-+					pipe_ctx->clock_source = context->res_ctx.
-+						pool.clock_sources[DCE100_CLK_SRC_EXT];
-+				else
-+					pipe_ctx->clock_source =
-+						find_used_clk_src_for_sharing(
-+							&context->res_ctx, pipe_ctx);
-+				if (pipe_ctx->clock_source == NULL)
-+					pipe_ctx->clock_source =
-+						find_first_free_pll(&context->res_ctx);
-+
-+				if (pipe_ctx->clock_source == NULL)
-+					return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+				reference_clock_source(
-+						&context->res_ctx,
-+						pipe_ctx->clock_source);
-+
-+				/* only one cs per stream regardless of mpo */
-+				break;
-+			}
- 		}
- 	}
- 
-@@ -865,24 +873,30 @@ enum dc_status dce100_validate_with_context(
- 	struct dc_context *dc_ctx = dc->ctx;
- 
- 	for (i = 0; i < set_count; i++) {
-+		bool unchanged = false;
-+
- 		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		context->target_count++;
- 
- 		for (j = 0; j < dc->current_context.target_count; j++)
--			if (dc->current_context.targets[j] == context->targets[i])
-+			if (dc->current_context.targets[j]
-+						== context->targets[i]) {
-+				unchanged = true;
- 				set_target_unchanged(context, i);
--
--		if (!context->target_flags[i].unchanged)
--			if (!logical_attach_surfaces_to_target(
-+				context->target_status[i] =
-+					dc->current_context.target_status[j];
-+			}
-+		if (!unchanged)
-+			if (!attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
--					&context->targets[i]->public)) {
-+					&context->targets[i]->public,
-+					context)) {
- 				DC_ERROR("Failed to attach surface to target!\n");
- 				return DC_FAIL_ATTACH_SURFACES;
- 			}
- 	}
- 
--	context->target_count = set_count;
--
- 	context->res_ctx.pool = dc->res_pool;
- 
- 	result = map_resources(dc, context);
-@@ -969,7 +983,7 @@ bool dce100_construct_resource_pool(
- 
- 	}
- 
--	pool->controller_count =
-+	pool->pipe_count =
- 		dal_adapter_service_get_func_controllers_num(adapter_serv);
- 	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
- 			adapter_serv);
-@@ -980,7 +994,7 @@ bool dce100_construct_resource_pool(
- 		goto filter_create_fail;
- 	}
- 
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		pool->timing_generators[i] = dce100_timing_generator_create(
- 				adapter_serv, ctx, i, &dce100_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
-@@ -1031,7 +1045,7 @@ bool dce100_construct_resource_pool(
- 	audio_init_data.as = adapter_serv;
- 	audio_init_data.ctx = ctx;
- 	pool->audio_count = 0;
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		struct graphics_object_id obj_id;
- 
- 		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-@@ -1089,13 +1103,13 @@ stream_enc_create_fail:
- 	}
- 
- audio_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->audios[i] != NULL)
- 			dal_audio_destroy(&pool->audios[i]);
- 	}
- 
- controller_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->opps[i] != NULL)
- 			dce100_opp_destroy(&pool->opps[i]);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index a815a6d..70349a0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -546,17 +546,17 @@ prescale_alloc_fail:
- }
- 
- static enum dc_status bios_parser_crtc_source_select(
--		struct core_stream *stream)
-+		struct pipe_ctx *pipe_ctx)
- {
- 	struct dc_bios *dcb;
- 	/* call VBIOS table to set CRTC source for the HW
- 	 * encoder block
- 	 * note: video bios clears all FMT setting here. */
- 	struct bp_crtc_source_select crtc_source_select = {0};
--	const struct core_sink *sink = stream->sink;
-+	const struct core_sink *sink = pipe_ctx->stream->sink;
- 
--	crtc_source_select.engine_id = stream->stream_enc->id;
--	crtc_source_select.controller_id = stream->controller_idx + 1;
-+	crtc_source_select.engine_id = pipe_ctx->stream_enc->id;
-+	crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
- 	/*TODO: Need to un-hardcode color depth, dp_audio and account for
- 	 * the case where signal and sink signal is different (translator
- 	 * encoder)*/
-@@ -576,32 +576,6 @@ static enum dc_status bios_parser_crtc_source_select(
- 	return DC_OK;
- }
- 
--static enum color_space surface_color_to_color_space(
--	struct plane_colorimetry *colorimetry)
--{
--	enum color_space color_space = COLOR_SPACE_UNKNOWN;
--
--	switch (colorimetry->color_space) {
--	case SURFACE_COLOR_SPACE_SRGB:
--	case SURFACE_COLOR_SPACE_XRRGB:
--		if (colorimetry->limited_range)
--			color_space = COLOR_SPACE_SRGB_LIMITED_RANGE;
--		else
--			color_space = COLOR_SPACE_SRGB_FULL_RANGE;
--		break;
--	case SURFACE_COLOR_SPACE_BT601:
--	case SURFACE_COLOR_SPACE_XVYCC_BT601:
--		color_space = COLOR_SPACE_YCBCR601;
--		break;
--	case SURFACE_COLOR_SPACE_BT709:
--	case SURFACE_COLOR_SPACE_XVYCC_BT709:
--		color_space = COLOR_SPACE_YCBCR709;
--		break;
--	}
--
--	return color_space;
--}
--
- /*******************************FMT**************************************/
- static void program_fmt(
- 		struct output_pixel_processor *opp,
-@@ -630,35 +604,35 @@ static void update_bios_scratch_critical_state(struct adapter_service *as,
- 	dcb->funcs->set_scratch_critical_state(dcb, state);
- }
- 
--static void update_info_frame(struct core_stream *stream)
-+static void update_info_frame(struct pipe_ctx *pipe_ctx)
- {
--	if (dc_is_hdmi_signal(stream->signal))
--		stream->stream_enc->funcs->update_hdmi_info_packets(
--			stream->stream_enc,
--			&stream->encoder_info_frame);
--	else if (dc_is_dp_signal(stream->signal))
--		stream->stream_enc->funcs->update_dp_info_packets(
--			stream->stream_enc,
--			&stream->encoder_info_frame);
-+	if (dc_is_hdmi_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
-+			pipe_ctx->stream_enc,
-+			&pipe_ctx->encoder_info_frame);
-+	else if (dc_is_dp_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->update_dp_info_packets(
-+			pipe_ctx->stream_enc,
-+			&pipe_ctx->encoder_info_frame);
- }
- 
- 
--static void enable_stream(struct core_stream *stream)
-+static void enable_stream(struct pipe_ctx *pipe_ctx)
- {
- 	enum dc_lane_count lane_count =
--			stream->sink->link->public.cur_link_settings.lane_count;
-+		pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count;
- 
--	struct dc_crtc_timing *timing = &stream->public.timing;
--	struct core_link *link = stream->sink->link;
-+	struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
-+	struct core_link *link = pipe_ctx->stream->sink->link;
- 
- 	/* 1. update AVI info frame (HDMI, DP)
- 	 * we always need to update info frame
- 	*/
- 	uint32_t active_total_with_borders;
- 	uint32_t early_control = 0;
--	struct timing_generator *tg = stream->tg;
-+	struct timing_generator *tg = pipe_ctx->tg;
- 
--	update_info_frame(stream);
-+	update_info_frame(pipe_ctx);
- 	/* enable early control to avoid corruption on DP monitor*/
- 	active_total_with_borders =
- 			timing->h_addressable
-@@ -674,11 +648,11 @@ static void enable_stream(struct core_stream *stream)
- 	tg->funcs->set_early_control(tg, early_control);
- 
- 	/* enable audio only within mode set */
--	if (stream->audio != NULL) {
-+	if (pipe_ctx->audio != NULL) {
- 		dal_audio_enable_output(
--			stream->audio,
--			stream->stream_enc->id,
--			stream->signal);
-+			pipe_ctx->audio,
-+			pipe_ctx->stream_enc->id,
-+			pipe_ctx->signal);
- 	}
- 
- 	/* For MST, there are multiply stream go to only one link.
-@@ -686,26 +660,27 @@ static void enable_stream(struct core_stream *stream)
- 	 * disconnect them during disable_stream
- 	 * BY this, it is logic clean to separate stream and link */
- 	 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
--			stream->stream_enc->id, true);
-+			pipe_ctx->stream_enc->id, true);
- 
- }
- 
--static void disable_stream(struct core_stream *stream)
-+static void disable_stream(struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	struct core_link *link = stream->sink->link;
- 
--	if (dc_is_hdmi_signal(stream->signal))
--		stream->stream_enc->funcs->stop_hdmi_info_packets(
--			stream->stream_enc);
-+	if (dc_is_hdmi_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->stop_hdmi_info_packets(
-+			pipe_ctx->stream_enc);
- 
--	if (dc_is_dp_signal(stream->signal))
--		stream->stream_enc->funcs->stop_dp_info_packets(
--			stream->stream_enc);
-+	if (dc_is_dp_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->stop_dp_info_packets(
-+			pipe_ctx->stream_enc);
- 
--	if (stream->audio) {
-+	if (pipe_ctx->audio) {
- 		/* mute audio */
--		dal_audio_mute(stream->audio, stream->stream_enc->id,
--				stream->signal);
-+		dal_audio_mute(pipe_ctx->audio, pipe_ctx->stream_enc->id,
-+				pipe_ctx->signal);
- 
- 		/* TODO: notify audio driver for if audio modes list changed
- 		 * add audio mode list change flag */
-@@ -715,27 +690,26 @@ static void disable_stream(struct core_stream *stream)
- 	}
- 
- 	/* blank at encoder level */
--	if (dc_is_dp_signal(stream->signal))
--		stream->stream_enc->funcs->dp_blank(stream->stream_enc);
-+	if (dc_is_dp_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->dp_blank(pipe_ctx->stream_enc);
- 
- 	link->link_enc->funcs->connect_dig_be_to_fe(
- 			link->link_enc,
--			stream->stream_enc->id,
-+			pipe_ctx->stream_enc->id,
- 			false);
- 
- }
- 
--static void unblank_stream(struct core_stream *stream,
-+static void unblank_stream(struct pipe_ctx *pipe_ctx,
- 		struct dc_link_settings *link_settings)
- {
- 	struct encoder_unblank_param params = { { 0 } };
- 
- 	/* only 3 items below are used by unblank */
- 	params.crtc_timing.pixel_clock =
--		stream->public.timing.pix_clk_khz;
-+		pipe_ctx->stream->public.timing.pix_clk_khz;
- 	params.link_settings.link_rate = link_settings->link_rate;
--	stream->stream_enc->funcs->dp_unblank(
--		stream->stream_enc, &params);
-+	pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, &params);
- }
- 
- static enum color_space get_output_color_space(
-@@ -776,106 +750,102 @@ static enum color_space get_output_color_space(
- 	return color_space;
- }
- 
--static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
-+static enum dc_status apply_single_controller_ctx_to_hw(
-+		struct pipe_ctx *pipe_ctx,
- 		struct validate_context *context,
--		const struct dc *dc)
-+		struct dc *dc)
- {
--	struct core_stream *stream =
--			context->res_ctx.controller_ctx[controller_idx].stream;
--	struct core_stream *old_stream =
--		dc->current_context.res_ctx.controller_ctx[controller_idx].stream;
--	struct output_pixel_processor *opp =
--		context->res_ctx.pool.opps[controller_idx];
--	bool timing_changed = context->res_ctx.controller_ctx[controller_idx]
--			.flags.timing_changed;
-+	struct core_stream *stream = pipe_ctx->stream;
-+	struct pipe_ctx *old_pipe_ctx =
-+		&dc->current_context.res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-+	bool timing_changed = context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]
-+							.flags.timing_changed;
- 	enum color_space color_space;
- 
- 	if (timing_changed) {
- 		/* Must blank CRTC after disabling power gating and before any
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
--		stream->tg->funcs->set_blank(stream->tg, true);
-+		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
- 
- 		/*
- 		 * only disable stream in case it was ever enabled
- 		 */
--		if (old_stream)
--			core_link_disable_stream(
--				old_stream->sink->link,
--				old_stream);
-+		if (old_pipe_ctx->stream)
-+			core_link_disable_stream(old_pipe_ctx);
- 
- 		/*TODO: AUTO check if timing changed*/
--		if (false == stream->clock_source->funcs->program_pix_clk(
--				stream->clock_source,
--				&stream->pix_clk_params,
--				&stream->pll_settings)) {
-+		if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
-+				pipe_ctx->clock_source,
-+				&pipe_ctx->pix_clk_params,
-+				&pipe_ctx->pll_settings)) {
- 			BREAK_TO_DEBUGGER();
- 			return DC_ERROR_UNEXPECTED;
- 		}
- 
--		stream->tg->funcs->program_timing(
--				stream->tg,
-+		pipe_ctx->tg->funcs->program_timing(
-+				pipe_ctx->tg,
- 				&stream->public.timing,
- 				true);
- 	}
- 
- 	/*TODO: mst support - use total stream count*/
--	stream->mi->funcs->allocate_mem_input(
--					stream->mi,
-+	pipe_ctx->mi->funcs->allocate_mem_input(
-+					pipe_ctx->mi,
- 					stream->public.timing.h_total,
- 					stream->public.timing.v_total,
- 					stream->public.timing.pix_clk_khz,
- 					context->target_count);
- 
- 	if (timing_changed) {
--		if (false == stream->tg->funcs->enable_crtc(
--				stream->tg)) {
-+		if (false == pipe_ctx->tg->funcs->enable_crtc(
-+				pipe_ctx->tg)) {
- 			BREAK_TO_DEBUGGER();
- 			return DC_ERROR_UNEXPECTED;
- 		}
- 	}
- 
- 	/* TODO: move to stream encoder */
--	if (stream->signal != SIGNAL_TYPE_VIRTUAL)
--		if (DC_OK != bios_parser_crtc_source_select(stream)) {
-+	if (pipe_ctx->signal != SIGNAL_TYPE_VIRTUAL)
-+		if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
- 			BREAK_TO_DEBUGGER();
- 			return DC_ERROR_UNEXPECTED;
- 		}
- 
--	opp->funcs->opp_set_dyn_expansion(
--			opp,
-+	pipe_ctx->opp->funcs->opp_set_dyn_expansion(
-+			pipe_ctx->opp,
- 			COLOR_SPACE_YCBCR601,
- 			stream->public.timing.display_color_depth,
- 			stream->sink->public.sink_signal);
- 
--	program_fmt(opp, &stream->bit_depth_params, &stream->clamping);
-+	program_fmt(pipe_ctx->opp, &stream->bit_depth_params, &stream->clamping);
- 
- 	stream->sink->link->link_enc->funcs->setup(
- 		stream->sink->link->link_enc,
--		stream->signal);
-+		pipe_ctx->signal);
- 
--	if (dc_is_dp_signal(stream->signal))
--		stream->stream_enc->funcs->dp_set_stream_attribute(
--			stream->stream_enc,
-+	if (dc_is_dp_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
-+			pipe_ctx->stream_enc,
- 			&stream->public.timing);
- 
--	if (dc_is_hdmi_signal(stream->signal))
--		stream->stream_enc->funcs->hdmi_set_stream_attribute(
--			stream->stream_enc,
-+	if (dc_is_hdmi_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute(
-+			pipe_ctx->stream_enc,
- 			&stream->public.timing,
--			stream->audio != NULL);
-+			pipe_ctx->audio != NULL);
- 
--	if (dc_is_dvi_signal(stream->signal))
--		stream->stream_enc->funcs->dvi_set_stream_attribute(
--			stream->stream_enc,
-+	if (dc_is_dvi_signal(pipe_ctx->signal))
-+		pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute(
-+			pipe_ctx->stream_enc,
- 			&stream->public.timing,
--			(stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+			(pipe_ctx->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
- 			true : false);
- 
--	if (stream->audio != NULL) {
-+	if (pipe_ctx->audio != NULL) {
- 		if (AUDIO_RESULT_OK != dal_audio_setup(
--				stream->audio,
--				&stream->audio_output,
-+				pipe_ctx->audio,
-+				&pipe_ctx->audio_output,
- 				&stream->public.audio_info)) {
- 			BREAK_TO_DEBUGGER();
- 			return DC_ERROR_UNEXPECTED;
-@@ -883,24 +853,24 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
- 	}
- 
- 	/* Setup audio rate clock source */
--	if (stream->audio != NULL)
-+	if (pipe_ctx->audio != NULL)
- 		dal_audio_setup_audio_wall_dto(
--				stream->audio,
--				stream->signal,
--				&stream->audio_output.crtc_info,
--				&stream->audio_output.pll_info);
-+				pipe_ctx->audio,
-+				pipe_ctx->signal,
-+				&pipe_ctx->audio_output.crtc_info,
-+				&pipe_ctx->audio_output.pll_info);
- 
- 	/* program blank color */
- 	color_space = get_output_color_space(&stream->public.timing);
--	stream->tg->funcs->set_blank_color(
--			context->res_ctx.pool.timing_generators[controller_idx],
-+	pipe_ctx->tg->funcs->set_blank_color(
-+			pipe_ctx->tg,
- 			color_space);
- 
- 	if (timing_changed)
--		core_link_enable_stream(stream->sink->link, stream);
-+		core_link_enable_stream(pipe_ctx);
- 
--	if (dc_is_dp_signal(stream->signal))
--		unblank_stream(stream,
-+	if (dc_is_dp_signal(pipe_ctx->signal))
-+		unblank_stream(pipe_ctx,
- 			&stream->sink->link->public.cur_link_settings);
- 
- 	return DC_OK;
-@@ -923,7 +893,7 @@ static void power_down_controllers(struct dc *dc)
- {
- 	int i;
- 
--	for (i = 0; i < dc->res_pool.controller_count; i++) {
-+	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		dc->res_pool.timing_generators[i]->funcs->disable_crtc(
- 				dc->res_pool.timing_generators[i]);
- 	}
-@@ -960,7 +930,7 @@ static void disable_vga_and_power_gate_all_controllers(
- 	dcb = dal_adapter_service_get_bios_parser(
- 			dc->res_pool.adapter_srv);
- 
--	for (i = 0; i < dc->res_pool.controller_count; i++) {
-+	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		tg = dc->res_pool.timing_generators[i];
- 		ctx = dc->ctx;
- 
-@@ -1133,14 +1103,13 @@ static void set_display_clock(struct validate_context *context)
- }
- 
- static uint32_t compute_pstate_blackout_duration(
--	const struct dc *dc,
-+	struct bw_fixed blackout_duration,
- 	const struct core_stream *stream)
- {
- 	uint32_t total_dest_line_time_ns;
- 	uint32_t pstate_blackout_duration_ns;
- 
--	pstate_blackout_duration_ns = 1000 *
--		dc->bw_vbios.blackout_duration.value >> 24;
-+	pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
- 
- 	total_dest_line_time_ns = 1000000UL *
- 		stream->public.timing.h_total /
-@@ -1154,63 +1123,50 @@ static void set_displaymarks(
- 	const struct dc *dc,
- 	struct validate_context *context)
- {
--	uint8_t i, j;
--	uint8_t total_streams = 0;
--	uint8_t target_count = context->target_count;
--	uint32_t pstate_blackout_duration_ns;
-+	uint8_t i, num_pipes;
-+
-+	for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		uint32_t total_dest_line_time_ns;
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
- 
--	for (i = 0; i < target_count; i++) {
--		const struct core_target *target = context->targets[i];
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			const struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			pstate_blackout_duration_ns =
--				compute_pstate_blackout_duration(dc, stream);
--
--			stream->mi->funcs->mem_input_program_display_marks(
--				stream->mi,
--				context->bw_results
--					.nbp_state_change_wm_ns[total_streams],
--				context->bw_results
--					.stutter_exit_wm_ns[total_streams],
--				context->bw_results.
--					urgent_wm_ns[total_streams],
--				pstate_blackout_duration_ns);
--
--			total_streams++;
--		} /* for ()*/
--	} /* for() */
-+		total_dest_line_time_ns = compute_pstate_blackout_duration(
-+			dc->bw_vbios.blackout_duration, pipe_ctx->stream);
-+		pipe_ctx->mi->funcs->mem_input_program_display_marks(
-+			pipe_ctx->mi,
-+			context->bw_results.nbp_state_change_wm_ns[num_pipes],
-+			context->bw_results.stutter_exit_wm_ns[num_pipes],
-+			context->bw_results.urgent_wm_ns[num_pipes],
-+			total_dest_line_time_ns);
-+		num_pipes++;
-+	}
- }
- 
--static void set_safe_displaymarks(const struct dc *dc, struct validate_context *context)
-+
-+static void set_safe_displaymarks(struct resource_context *res_ctx)
- {
--	uint8_t i, j;
--	uint8_t target_count = context->target_count;
-+	uint8_t i;
- 	struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
- 	struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
- 
--	for (i = 0; i < target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (res_ctx->pipe_ctx[i].stream == NULL)
-+			continue;
- 
--			stream->mi->funcs->mem_input_program_display_marks(
--				stream->mi,
-+		res_ctx->pipe_ctx[i].mi->funcs->mem_input_program_display_marks(
-+				res_ctx->pipe_ctx[i].mi,
- 				nbp_marks,
- 				max_marks,
- 				max_marks,
- 				MAX_WATERMARK);
--		}
- 	}
- }
- 
- static void program_bw(struct dc *dc, struct validate_context *context)
- {
--	set_safe_displaymarks(dc, context);
-+	set_safe_displaymarks(&context->res_ctx);
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
-@@ -1220,31 +1176,27 @@ static void program_bw(struct dc *dc, struct validate_context *context)
- 
- static void switch_dp_clock_sources(
- 	const struct dc *dc,
--	struct validate_context *val_context)
-+	struct resource_context *res_ctx)
- {
--	uint8_t i, j;
--	for (i = 0; i < val_context->target_count; i++) {
--		struct core_target *target = val_context->targets[i];
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			if (dc_is_dp_signal(stream->signal)) {
--				struct clock_source *clk_src =
--					find_used_clk_src_for_sharing(
--							val_context, stream);
--
--				if (clk_src &&
--					clk_src != stream->clock_source) {
--					unreference_clock_source(
--							&val_context->res_ctx,
--							stream->clock_source);
--					stream->clock_source = clk_src;
--					reference_clock_source(
--						&val_context->res_ctx, clk_src);
--					dc->hwss.crtc_switch_to_clk_src(
--						clk_src, stream->opp->inst);
--				}
-+	uint8_t i;
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (dc_is_dp_signal(pipe_ctx->signal)) {
-+			struct clock_source *clk_src =
-+				find_used_clk_src_for_sharing(
-+						res_ctx, pipe_ctx);
-+
-+			if (clk_src &&
-+				clk_src != pipe_ctx->clock_source) {
-+				unreference_clock_source(
-+					res_ctx, pipe_ctx->clock_source);
-+				pipe_ctx->clock_source = clk_src;
-+				reference_clock_source(res_ctx, clk_src);
-+				dc->hwss.crtc_switch_to_clk_src(clk_src, i);
- 			}
- 		}
- 	}
-@@ -1256,22 +1208,20 @@ static void switch_dp_clock_sources(
- 
- /*TODO: const validate_context*/
- static enum dc_status apply_ctx_to_hw(
--		const struct dc *dc,
-+		struct dc *dc,
- 		struct validate_context *context)
- {
- 	enum dc_status status;
- 	uint8_t i;
--	struct resource_pool *pool = &context->res_ctx.pool;
- 
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
- 			true);
- 
--	for (i = 0; i < pool->controller_count; i++) {
--		struct controller_ctx *ctlr_ctx
--			= &context->res_ctx.controller_ctx[i];
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- 		struct dc_bios *dcb;
- 
--		if (ctlr_ctx->flags.unchanged || !ctlr_ctx->stream)
-+		if (pipe_ctx->stream == NULL || pipe_ctx->flags.unchanged)
- 			continue;
- 
- 		dcb = dal_adapter_service_get_bios_parser(
-@@ -1282,7 +1232,7 @@ static enum dc_status apply_ctx_to_hw(
- 				PIPE_GATING_CONTROL_DISABLE);
- 	}
- 
--	set_safe_displaymarks(dc, context);
-+	set_safe_displaymarks(&context->res_ctx);
- 	/*TODO: when pplib works*/
- 	/*dc_set_clocks_and_clock_state(context);*/
- 
-@@ -1290,14 +1240,14 @@ static enum dc_status apply_ctx_to_hw(
- 		> dc->current_context.bw_results.dispclk_khz)
- 		set_display_clock(context);
- 
--	for (i = 0; i < pool->controller_count; i++) {
--		struct controller_ctx *ctlr_ctx
--			= &context->res_ctx.controller_ctx[i];
--		if (ctlr_ctx->flags.unchanged || !ctlr_ctx->stream)
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL || pipe_ctx->flags.unchanged)
- 			continue;
- 
- 		status = apply_single_controller_ctx_to_hw(
--				i,
-+				pipe_ctx,
- 				context,
- 				dc);
- 
-@@ -1309,7 +1259,7 @@ static enum dc_status apply_ctx_to_hw(
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
- 			false);
- 
--	switch_dp_clock_sources(dc, context);
-+	switch_dp_clock_sources(dc, &context->res_ctx);
- 
- 	return DC_OK;
- }
-@@ -1320,14 +1270,14 @@ static enum dc_status apply_ctx_to_hw(
-  ******************************************************************************/
- 
- static bool setup_line_buffer_pixel_depth(
--	const struct core_stream *stream,
-+	const struct pipe_ctx *pipe_ctx,
- 	enum lb_pixel_depth depth,
- 	bool blank)
- {
- 	enum lb_pixel_depth current_depth;
- 
--	struct timing_generator *tg = stream->tg;
--	struct transform *xfm = stream->xfm;
-+	struct timing_generator *tg = pipe_ctx->tg;
-+	struct transform *xfm = pipe_ctx->xfm;
- 
- 	if (!xfm->funcs->transform_get_current_pixel_storage_depth(
- 		xfm,
-@@ -1339,14 +1289,14 @@ static bool setup_line_buffer_pixel_depth(
- 			tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
- 
- 		return xfm->funcs->transform_set_pixel_storage_depth(xfm, depth,
--				&stream->bit_depth_params);
-+				&pipe_ctx->stream->bit_depth_params);
- 	}
- 
- 	return false;
- }
- 
- static void hw_sequencer_build_scaler_parameter_plane(
--		const struct core_stream *stream,
-+		const struct pipe_ctx *pipe_ctx,
- 		struct scaler_data *scaler_data)
- {
- 	/*TODO: per pipe not per stream*/
-@@ -1361,15 +1311,15 @@ static void hw_sequencer_build_scaler_parameter_plane(
- 
- 	scaler_data->flags.bits.INTERLACED = 0;
- 
--	scaler_data->dal_pixel_format = stream->format;
-+	scaler_data->dal_pixel_format = pipe_ctx->format;
- 
--	scaler_data->taps = stream->taps;
-+	scaler_data->taps = pipe_ctx->taps;
- 
--	scaler_data->viewport = stream->viewport;
-+	scaler_data->viewport = pipe_ctx->viewport;
- 
--	scaler_data->overscan = stream->overscan;
-+	scaler_data->overscan = pipe_ctx->overscan;
- 
--	scaler_data->ratios = &stream->ratios;
-+	scaler_data->ratios = &pipe_ctx->ratios;
- 
- 	/*TODO rotation and adjustment */
- 	scaler_data->h_sharpness = 0;
-@@ -1377,23 +1327,19 @@ static void hw_sequencer_build_scaler_parameter_plane(
- 
- }
- 
--static void set_default_colors(
--				struct input_pixel_processor *ipp,
--				struct output_pixel_processor *opp,
--				enum pixel_format format,
--				enum color_space input_color_space,
--				enum color_space output_color_space,
--				enum dc_color_depth color_depth)
-+static void set_default_colors(struct pipe_ctx *pipe_ctx)
- {
- 	struct default_adjustment default_adjust = { 0 };
- 
- 	default_adjust.force_hw_default = false;
--	default_adjust.color_space = output_color_space;
-+	default_adjust.color_space = get_output_color_space(
-+					&pipe_ctx->stream->public.timing);
- 	default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
--	default_adjust.surface_pixel_format = format;
-+	default_adjust.surface_pixel_format = pipe_ctx->format;
- 
- 	/* display color depth */
--	default_adjust.color_depth = color_depth;
-+	default_adjust.color_depth =
-+		pipe_ctx->stream->public.timing.display_color_depth;
- 
- 	/* Lb color depth */
- 	default_adjust.lb_color_depth = LB_PIXEL_DEPTH_24BPP;
-@@ -1401,99 +1347,74 @@ static void set_default_colors(
- 			build_params->
- 			line_buffer_params[path_id][plane_id].depth);*/
- 
--	opp->funcs->opp_set_csc_default(opp, &default_adjust);
-+	pipe_ctx->opp->funcs->opp_set_csc_default(
-+					pipe_ctx->opp, &default_adjust);
- }
- 
- static void program_scaler(
--	uint8_t controller_idx,
--	struct timing_generator *tg,
--	struct transform *xfm,
- 	const struct core_surface *surface,
--	const struct core_stream *stream)
-+	const struct pipe_ctx *pipe_ctx)
- {
- 	struct scaler_data scaler_data = { { 0 } };
- 
- 	hw_sequencer_build_scaler_parameter_plane(
--		stream,
-+		pipe_ctx,
- 		&scaler_data);
- 
- 	setup_line_buffer_pixel_depth(
--		stream,
-+		pipe_ctx,
- 		LB_PIXEL_DEPTH_24BPP,
- 		false);
- 
--	tg->funcs->set_overscan_blank_color(tg, surface->public.colorimetry.color_space);
-+	pipe_ctx->tg->funcs->set_overscan_blank_color(
-+		pipe_ctx->tg, surface->public.color_space);
- 
--	xfm->funcs->transform_set_scaler(xfm, &scaler_data);
-+	pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, &scaler_data);
- 
--	xfm->funcs->transform_update_viewport(
--			xfm,
--			&scaler_data.viewport,
--			false);
-+	pipe_ctx->xfm->funcs->transform_update_viewport(
-+			pipe_ctx->xfm, &scaler_data.viewport, false);
- }
- 
- /**
-  * Program the Front End of the Pipe.
-  * The Back End was already programmed by Set Mode.
-  */
--static bool set_plane_config(
-+static void set_plane_config(
- 	const struct dc *dc,
- 	struct core_surface *surface,
--	struct core_target *target)
-+	struct pipe_ctx *pipe_ctx)
- {
--	const struct core_stream *core_stream =
--		DC_STREAM_TO_CORE(target->public.streams[0]);
--	const struct dc_crtc_timing *dc_crtc_timing =
--			&target->public.streams[0]->timing;
--	struct mem_input *mi = core_stream->mi;
--	struct input_pixel_processor *ipp = core_stream->ipp;
--	struct timing_generator *tg = core_stream->tg;
--	struct transform *xfm = core_stream->xfm;
--	struct output_pixel_processor *opp = core_stream->opp;
--	struct dc_context *ctx = core_stream->ctx;
--	uint8_t controller_idx = core_stream->controller_idx;
--
--	/* TODO: Clean up change, possibly change to use same type */
--	enum color_space input_color_space =
--					surface_color_to_color_space(&(surface->public.colorimetry));
-+	const struct dc_crtc_timing *crtc_timing =
-+				&pipe_ctx->stream->public.timing;
-+	struct mem_input *mi = pipe_ctx->mi;
-+	struct timing_generator *tg = pipe_ctx->tg;
-+	struct dc_context *ctx = pipe_ctx->stream->ctx;
- 
- 	dc->hwss.pipe_control_lock(
--			ctx,
--			controller_idx,
--			PIPE_LOCK_CONTROL_MODE,
--			false);
-+		ctx, pipe_ctx->pipe_idx, PIPE_LOCK_CONTROL_MODE, false);
- 
- 	/* While a non-root controller is programmed we
- 	 * have to lock the root controller. */
- 	dc->hwss.pipe_control_lock(
- 			ctx,
--			controller_idx,
-+			pipe_ctx->pipe_idx,
- 			PIPE_LOCK_CONTROL_GRAPHICS |
- 			PIPE_LOCK_CONTROL_SCL |
- 			PIPE_LOCK_CONTROL_BLENDER |
- 			PIPE_LOCK_CONTROL_SURFACE,
- 			true);
- 
--	tg->funcs->program_timing(tg, dc_crtc_timing, false);
-+	tg->funcs->program_timing(tg, crtc_timing, false);
- 
--	dc->hwss.enable_fe_clock(ctx, controller_idx, true);
-+	dc->hwss.enable_fe_clock(ctx, pipe_ctx->pipe_idx, true);
- 
--	set_default_colors(
--			ipp,
--			opp,
--			core_stream->format,
--			input_color_space,
--			get_output_color_space(dc_crtc_timing),
--			dc_crtc_timing->display_color_depth);
-+	set_default_colors(pipe_ctx);
- 
- 	/* program Scaler */
--	program_scaler(
--		controller_idx, tg, xfm, surface, core_stream);
-+	program_scaler(surface, pipe_ctx);
- 
- 	dc->hwss.set_blender_mode(
--			ctx,
--			controller_idx,
--			BLENDER_MODE_CURRENT_PIPE);
-+		ctx, pipe_ctx->pipe_idx, BLENDER_MODE_CURRENT_PIPE);
- 
- 	mi->funcs->mem_input_program_surface_config(
- 			mi,
-@@ -1504,96 +1425,92 @@ static bool set_plane_config(
- 
- 	dc->hwss.pipe_control_lock(
- 			ctx,
--			controller_idx,
-+			pipe_ctx->pipe_idx,
- 			PIPE_LOCK_CONTROL_GRAPHICS |
- 			PIPE_LOCK_CONTROL_SCL |
- 			PIPE_LOCK_CONTROL_BLENDER |
- 			PIPE_LOCK_CONTROL_SURFACE,
- 			false);
--
--	return true;
- }
- 
--static bool update_plane_address(
--	const struct dc *dc,
--	const struct core_surface *surface,
--	struct core_target *target)
-+static void update_plane_addrs(
-+	struct dc *dc,
-+	struct resource_context *res_ctx,
-+	const struct core_surface *surface)
- {
--	const struct core_stream *core_stream =
--		DC_STREAM_TO_CORE(target->public.streams[0]);
--	struct dc_context *ctx = core_stream->ctx;
--	struct mem_input *mi = core_stream->mi;
--	uint8_t controller_id = core_stream->controller_idx;
-+	uint8_t j;
- 
--	/* TODO: crtc should be per surface, NOT per-target */
--	dc->hwss.pipe_control_lock(
--		ctx,
--		controller_id,
--		PIPE_LOCK_CONTROL_SURFACE,
--		true);
--
--	if (false ==
--		core_stream->mi->funcs->mem_input_program_surface_flip_and_addr(
--		mi, &surface->public.address, surface->public.flip_immediate))
--		return false;
-+	for (j = 0; j < MAX_PIPES; j++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j];
- 
--	dc->hwss.pipe_control_lock(
--		ctx,
--		controller_id,
--		PIPE_LOCK_CONTROL_SURFACE,
--		false);
-+		if (pipe_ctx->surface != surface)
-+			continue;
- 
--	return true;
-+		dc->hwss.pipe_control_lock(
-+			dc->ctx,
-+			j,
-+			PIPE_LOCK_CONTROL_SURFACE,
-+			true);
-+
-+		pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
-+			pipe_ctx->mi,
-+			&surface->public.address,
-+			surface->public.flip_immediate);
-+
-+		dc->hwss.pipe_control_lock(
-+			dc->ctx,
-+			j,
-+			PIPE_LOCK_CONTROL_SURFACE,
-+			false);
-+
-+		break;
-+	}
- }
- 
--static void reset_single_stream_hw_ctx(
-+static void reset_single_pipe_hw_ctx(
- 		const struct dc *dc,
--		struct core_stream *stream,
-+		struct pipe_ctx *pipe_ctx,
- 		struct validate_context *context)
- {
- 	struct dc_bios *dcb;
- 
- 	dcb = dal_adapter_service_get_bios_parser(
- 			context->res_ctx.pool.adapter_srv);
--	if (stream->audio) {
--		dal_audio_disable_output(stream->audio,
--				stream->stream_enc->id,
--				stream->signal);
--		stream->audio = NULL;
-+	if (pipe_ctx->audio) {
-+		dal_audio_disable_output(pipe_ctx->audio,
-+				pipe_ctx->stream_enc->id,
-+				pipe_ctx->signal);
-+		pipe_ctx->audio = NULL;
- 	}
- 
--	core_link_disable_stream(stream->sink->link, stream);
-+	core_link_disable_stream(pipe_ctx);
- 
--	stream->tg->funcs->set_blank(stream->tg, true);
--	stream->tg->funcs->disable_crtc(stream->tg);
--	stream->mi->funcs->free_mem_input(
--			stream->mi, context->target_count);
--	stream->xfm->funcs->transform_set_scaler_bypass(stream->xfm);
--	unreference_clock_source(&context->res_ctx, stream->clock_source);
-+	pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
-+	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
-+	pipe_ctx->mi->funcs->free_mem_input(
-+				pipe_ctx->mi, context->target_count);
-+	pipe_ctx->xfm->funcs->transform_set_scaler_bypass(pipe_ctx->xfm);
-+	unreference_clock_source(&context->res_ctx, pipe_ctx->clock_source);
- 	dc->hwss.enable_display_power_gating(
--			stream->ctx, stream->controller_idx, dcb,
-+		pipe_ctx->stream->ctx, pipe_ctx->pipe_idx, dcb,
- 			PIPE_GATING_CONTROL_ENABLE);
- }
- 
--static void reset_hw_ctx(struct dc *dc,
--		struct validate_context *context,
--		uint8_t target_count)
-+static void reset_hw_ctx(
-+		struct dc *dc,
-+		struct validate_context *new_context)
- {
- 	uint8_t i;
--	/* look up the targets that have been removed since last commit */
--	for (i = 0; i < dc->current_context.target_count; i++) {
--		const struct core_target *core_target =
--			dc->current_context.targets[i];
--		struct core_stream *core_stream =
--			DC_STREAM_TO_CORE(core_target->public.streams[0]);
--		uint8_t controller_idx = core_stream->controller_idx;
--
--		if (context->res_ctx.controller_ctx[controller_idx].stream &&
--				!context->res_ctx.controller_ctx[controller_idx]
--				.flags.timing_changed)
--			continue;
- 
--		reset_single_stream_hw_ctx(dc, core_stream, &dc->current_context);
-+	/* look up the targets that have been removed since last commit */
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+			&dc->current_context.res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &new_context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx_old->stream && !pipe_ctx->stream)
-+			reset_single_pipe_hw_ctx(
-+				dc, pipe_ctx_old, &dc->current_context);
- 	}
- }
- 
-@@ -1601,7 +1518,6 @@ static void power_down(struct dc *dc)
- {
- 	power_down_all_hw_blocks(dc);
- 	disable_vga_and_power_gate_all_controllers(dc);
--
- }
- 
- static bool wait_for_reset_trigger_to_occur(
-@@ -1697,7 +1613,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
- 	.reset_hw_ctx = reset_hw_ctx,
- 	.set_plane_config = set_plane_config,
--	.update_plane_address = update_plane_address,
-+	.update_plane_addrs = update_plane_addrs,
- 	.set_gamma_correction = set_gamma_ramp,
- 	.power_down = power_down,
- 	.enable_accelerated_mode = enable_accelerated_mode,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 3c78431..9efed4f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1168,27 +1168,28 @@ bool dce110_link_encoder_construct(
- 
- bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
--	struct core_stream *stream)
-+	struct pipe_ctx *pipe_ctx)
- {
-+	struct core_stream *stream = pipe_ctx->stream;
- 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- 	bool is_valid;
- 
--	switch (stream->signal) {
-+	switch (pipe_ctx->signal) {
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
- 		is_valid = validate_dvi_output(
- 			enc110,
- 			stream->sink->link->public.connector_signal,
--			stream->signal,
-+			pipe_ctx->signal,
- 			&stream->public.timing);
- 	break;
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
- 		is_valid = validate_hdmi_output(
- 				enc110,
- 				&stream->public.timing,
--				stream->max_tmds_clk_from_edid_in_mhz,
--				stream->max_hdmi_deep_color,
--				stream->max_hdmi_pixel_clock);
-+				pipe_ctx->max_tmds_clk_from_edid_in_mhz,
-+				pipe_ctx->max_hdmi_deep_color,
-+				pipe_ctx->max_hdmi_pixel_clock);
- 	break;
- 	case SIGNAL_TYPE_RGB:
- 		is_valid = validate_rgb_output(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index 64a81f2..bbddd0b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -81,7 +81,7 @@ bool dce110_link_encoder_construct(
- 
- bool dce110_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
--	struct core_stream *stream);
-+	struct pipe_ctx *pipe_ctx);
- 
- /****************** HW programming ************************/
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 9e2b5d9..4fdf1f0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -477,7 +477,7 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- {
- 	unsigned int i;
- 
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->opps[i] != NULL)
- 			dce110_opp_destroy(&pool->opps[i]);
- 
-@@ -567,12 +567,13 @@ static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
- }
- 
- static void build_audio_output(
--	const struct core_stream *stream,
-+	const struct pipe_ctx *pipe_ctx,
- 	struct audio_output *audio_output)
- {
--	audio_output->engine_id = stream->stream_enc->id;
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	audio_output->engine_id = pipe_ctx->stream_enc->id;
- 
--	audio_output->signal = stream->signal;
-+	audio_output->signal = pipe_ctx->signal;
- 
- 	/* audio_crtc_info  */
- 
-@@ -604,42 +605,43 @@ static void build_audio_output(
- 		stream->public.timing.display_color_depth;
- 
- 	audio_output->crtc_info.requested_pixel_clock =
--			stream->pix_clk_params.requested_pix_clk;
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
- 
- 	/* TODO - Investigate why calculated pixel clk has to be
- 	 * requested pixel clk */
- 	audio_output->crtc_info.calculated_pixel_clock =
--			stream->pix_clk_params.requested_pix_clk;
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
- 
--	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
--			stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
- 		audio_output->pll_info.dp_dto_source_clock_in_khz =
- 			dal_display_clock_get_dp_ref_clk_frequency(
--				stream->dis_clk);
-+				pipe_ctx->dis_clk);
- 	}
- 
- 	audio_output->pll_info.feed_back_divider =
--			stream->pll_settings.feedback_divider;
-+			pipe_ctx->pll_settings.feedback_divider;
- 
- 	audio_output->pll_info.dto_source =
- 		translate_to_dto_source(
--			stream->controller_idx + 1);
-+			pipe_ctx->pipe_idx + 1);
- 
- 	/* TODO hard code to enable for now. Need get from stream */
- 	audio_output->pll_info.ss_enabled = true;
- 
- 	audio_output->pll_info.ss_percentage =
--			stream->pll_settings.ss_percentage;
-+			pipe_ctx->pll_settings.ss_percentage;
- }
- 
- static void get_pixel_clock_parameters(
--	const struct core_stream *stream,
-+	const struct pipe_ctx *pipe_ctx,
- 	struct pixel_clk_params *pixel_clk_params)
- {
-+	const struct core_stream *stream = pipe_ctx->stream;
- 	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
- 	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
- 	pixel_clk_params->signal_type = stream->sink->public.sink_signal;
--	pixel_clk_params->controller_id = stream->controller_idx + 1;
-+	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
- 	/* TODO: un-hardcode*/
- 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
- 		LINK_RATE_REF_FREQ_IN_KHZ;
-@@ -649,20 +651,20 @@ static void get_pixel_clock_parameters(
- 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
- }
- 
--static enum dc_status build_stream_hw_param(struct core_stream *stream)
-+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- {
- 	/*TODO: unhardcode*/
--	stream->max_tmds_clk_from_edid_in_mhz = 0;
--	stream->max_hdmi_deep_color = COLOR_DEPTH_121212;
--	stream->max_hdmi_pixel_clock = 600000;
-+	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
-+	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	pipe_ctx->max_hdmi_pixel_clock = 600000;
- 
--	get_pixel_clock_parameters(stream, &stream->pix_clk_params);
--	stream->clock_source->funcs->get_pix_clk_dividers(
--		stream->clock_source,
--		&stream->pix_clk_params,
--		&stream->pll_settings);
-+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
-+	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-+		pipe_ctx->clock_source,
-+		&pipe_ctx->pix_clk_params,
-+		&pipe_ctx->pll_settings);
- 
--	build_audio_output(stream, &stream->audio_output);
-+	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
- 
- 	return DC_OK;
- }
-@@ -672,7 +674,7 @@ static enum dc_status validate_mapped_resource(
- 		struct validate_context *context)
- {
- 	enum dc_status status = DC_OK;
--	uint8_t i, j;
-+	uint8_t i, j, k;
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		struct core_target *target = context->targets[i];
-@@ -683,30 +685,41 @@ static enum dc_status validate_mapped_resource(
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 			struct core_link *link = stream->sink->link;
- 
--			if (!stream->tg->funcs->validate_timing(
--					stream->tg, &stream->public.timing))
--				return DC_FAIL_CONTROLLER_VALIDATE;
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (!pipe_ctx->tg->funcs->validate_timing(
-+						pipe_ctx->tg, &stream->public.timing))
-+					return DC_FAIL_CONTROLLER_VALIDATE;
- 
--			status = build_stream_hw_param(stream);
-+				status = build_pipe_hw_param(pipe_ctx);
- 
--			if (status != DC_OK)
--				return status;
-+				if (status != DC_OK)
-+					return status;
- 
--			if (!link->link_enc->funcs->validate_output_with_stream(
--					link->link_enc,
--					stream))
--				return DC_FAIL_ENC_VALIDATE;
-+				if (!link->link_enc->funcs->validate_output_with_stream(
-+						link->link_enc,
-+						pipe_ctx))
-+					return DC_FAIL_ENC_VALIDATE;
- 
--			/* TODO: validate audio ASIC caps, encoder */
-+				/* TODO: validate audio ASIC caps, encoder */
- 
--			status = dc_link_validate_mode_timing(stream->sink,
--					link,
--					&stream->public.timing);
-+				status = dc_link_validate_mode_timing(stream->sink,
-+						link,
-+						&stream->public.timing);
- 
--			if (status != DC_OK)
--				return status;
-+				if (status != DC_OK)
-+					return status;
- 
--			build_info_frame(stream);
-+				build_info_frame(pipe_ctx);
-+
-+				/* do not need to validate non root pipes */
-+				break;
-+			}
- 		}
- 	}
- 
-@@ -717,7 +730,7 @@ enum dc_status dce110_validate_bandwidth(
- 	const struct dc *dc,
- 	struct validate_context *context)
- {
--	uint8_t i, j;
-+	uint8_t i;
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	uint8_t number_of_displays = 0;
- 	uint8_t max_htaps = 1;
-@@ -727,76 +740,75 @@ enum dc_status dce110_validate_bandwidth(
- 
- 	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
- 
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct bw_calcs_input_single_display *disp = &context->
--				bw_mode_data.displays_data[number_of_displays];
--
--			if (target->status.surface_count == 0) {
--				disp->graphics_scale_ratio = bw_int_to_fixed(1);
--				disp->graphics_h_taps = 2;
--				disp->graphics_v_taps = 2;
--
--				/* TODO: remove when bw formula accepts taps per
--				 * display
--				 */
--				if (max_vtaps < 2)
--					max_vtaps = 2;
--				if (max_htaps < 2)
--					max_htaps = 2;
--
--			} else {
--				disp->graphics_scale_ratio =
--					fixed31_32_to_bw_fixed(
--						stream->ratios.vert.value);
--				disp->graphics_h_taps = stream->taps.h_taps;
--				disp->graphics_v_taps = stream->taps.v_taps;
--
--				/* TODO: remove when bw formula accepts taps per
--				 * display
--				 */
--				if (max_vtaps < stream->taps.v_taps)
--					max_vtaps = stream->taps.v_taps;
--				if (max_htaps < stream->taps.h_taps)
--					max_htaps = stream->taps.h_taps;
--			}
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct bw_calcs_input_single_display *disp = &context->
-+			bw_mode_data.displays_data[number_of_displays];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
- 
--			disp->graphics_src_width =
--					stream->public.timing.h_addressable;
--			disp->graphics_src_height =
--					stream->public.timing.v_addressable;
--			disp->h_total = stream->public.timing.h_total;
--			disp->pixel_rate = bw_frc_to_fixed(
--				stream->public.timing.pix_clk_khz, 1000);
--
--			/*TODO: get from surface*/
--			disp->graphics_bytes_per_pixel = 4;
--			disp->graphics_tiling_mode = bw_def_tiled;
--
--			/* DCE11 defaults*/
--			disp->graphics_lb_bpc = 10;
--			disp->graphics_interlace_mode = false;
--			disp->fbc_enable = false;
--			disp->lpt_enable = false;
--			disp->graphics_stereo_mode = bw_def_mono;
--			disp->underlay_mode = bw_def_none;
--
--			/*All displays will be synchronized if timings are all
--			 * the same
-+		if (pipe_ctx->ratios.vert.value == 0) {
-+			disp->graphics_scale_ratio = bw_int_to_fixed(1);
-+			disp->graphics_h_taps = 2;
-+			disp->graphics_v_taps = 2;
-+
-+			/* TODO: remove when bw formula accepts taps per
-+			 * display
-+			 */
-+			if (max_vtaps < 2)
-+				max_vtaps = 2;
-+			if (max_htaps < 2)
-+				max_htaps = 2;
-+
-+		} else {
-+			disp->graphics_scale_ratio =
-+				fixed31_32_to_bw_fixed(
-+					pipe_ctx->ratios.vert.value);
-+			disp->graphics_h_taps = pipe_ctx->taps.h_taps;
-+			disp->graphics_v_taps = pipe_ctx->taps.v_taps;
-+
-+			/* TODO: remove when bw formula accepts taps per
-+			 * display
- 			 */
--			if (number_of_displays != 0 && all_displays_in_sync)
--				if (dm_memcmp(&prev_timing,
--					&stream->public.timing,
--					sizeof(struct dc_crtc_timing))!= 0)
--					all_displays_in_sync = false;
--			if (number_of_displays == 0)
--				prev_timing = stream->public.timing;
--
--			number_of_displays++;
-+			if (max_vtaps < pipe_ctx->taps.v_taps)
-+				max_vtaps = pipe_ctx->taps.v_taps;
-+			if (max_htaps < pipe_ctx->taps.h_taps)
-+				max_htaps = pipe_ctx->taps.h_taps;
- 		}
-+
-+		disp->graphics_src_width =
-+			pipe_ctx->stream->public.timing.h_addressable;
-+		disp->graphics_src_height =
-+			pipe_ctx->stream->public.timing.v_addressable;
-+		disp->h_total = pipe_ctx->stream->public.timing.h_total;
-+		disp->pixel_rate = bw_frc_to_fixed(
-+			pipe_ctx->stream->public.timing.pix_clk_khz, 1000);
-+
-+		/*TODO: get from surface*/
-+		disp->graphics_bytes_per_pixel = 4;
-+		disp->graphics_tiling_mode = bw_def_tiled;
-+
-+		/* DCE11 defaults*/
-+		disp->graphics_lb_bpc = 10;
-+		disp->graphics_interlace_mode = false;
-+		disp->fbc_enable = false;
-+		disp->lpt_enable = false;
-+		disp->graphics_stereo_mode = bw_def_mono;
-+		disp->underlay_mode = bw_def_none;
-+
-+		/*All displays will be synchronized if timings are all
-+		 * the same
-+		 */
-+		if (number_of_displays != 0 && all_displays_in_sync)
-+			if (dm_memcmp(&prev_timing,
-+				&pipe_ctx->stream->public.timing,
-+				sizeof(struct dc_crtc_timing)) != 0)
-+				all_displays_in_sync = false;
-+		if (number_of_displays == 0)
-+			prev_timing = pipe_ctx->stream->public.timing;
-+
-+		number_of_displays++;
- 	}
- 
- 	/* TODO: remove when bw formula accepts taps per
-@@ -813,7 +825,7 @@ enum dc_status dce110_validate_bandwidth(
- 		dc->ctx->logger,
- 		LOG_MAJOR_BWM,
- 		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
--		"%s: start\n",
-+		"%s: start",
- 		__func__);
- 
- 	if (!bw_calcs(
-@@ -891,14 +903,17 @@ static void set_target_unchanged(
- 		struct validate_context *context,
- 		uint8_t target_idx)
- {
--	uint8_t i;
-+	uint8_t i, j;
- 	struct core_target *target = context->targets[target_idx];
- 	context->target_flags[target_idx].unchanged = true;
- 	for (i = 0; i < target->public.stream_count; i++) {
--		struct core_stream *core_stream =
-+		struct core_stream *stream =
- 			DC_STREAM_TO_CORE(target->public.streams[i]);
--		uint8_t index = core_stream->controller_idx;
--		context->res_ctx.controller_ctx[index].flags.unchanged = true;
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (context->res_ctx.pipe_ctx[j].stream == stream)
-+				context->res_ctx.pipe_ctx[j].flags.unchanged =
-+									true;
-+		}
- 	}
- }
- 
-@@ -906,24 +921,7 @@ static enum dc_status map_clock_resources(
- 		const struct dc *dc,
- 		struct validate_context *context)
- {
--	uint8_t i, j;
--
--	/* mark resources used for targets that are already active */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (!context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			reference_clock_source(
--				&context->res_ctx,
--				stream->clock_source);
--		}
--	}
-+	uint8_t i, j, k;
- 
- 	/* acquire new resources */
- 	for (i = 0; i < context->target_count; i++) {
-@@ -936,24 +934,35 @@ static enum dc_status map_clock_resources(
- 			struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
- 
--			if (dc_is_dp_signal(stream->signal)
--				|| stream->signal == SIGNAL_TYPE_VIRTUAL)
--				stream->clock_source = context->res_ctx.
--					pool.clock_sources[DCE110_CLK_SRC_EXT];
--			else
--				stream->clock_source =
--					find_used_clk_src_for_sharing(
--							context, stream);
--			if (stream->clock_source == NULL)
--				stream->clock_source =
--					find_first_free_pll(&context->res_ctx);
--
--			if (stream->clock_source == NULL)
--				return DC_NO_CLOCK_SOURCE_RESOURCE;
--
--			reference_clock_source(
--					&context->res_ctx,
--					stream->clock_source);
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (dc_is_dp_signal(pipe_ctx->signal)
-+					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
-+					pipe_ctx->clock_source = context->res_ctx.
-+						pool.clock_sources[DCE110_CLK_SRC_EXT];
-+				else
-+					pipe_ctx->clock_source =
-+						find_used_clk_src_for_sharing(
-+							&context->res_ctx, pipe_ctx);
-+				if (pipe_ctx->clock_source == NULL)
-+					pipe_ctx->clock_source =
-+						find_first_free_pll(&context->res_ctx);
-+
-+				if (pipe_ctx->clock_source == NULL)
-+					return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+				reference_clock_source(
-+						&context->res_ctx,
-+						pipe_ctx->clock_source);
-+
-+				/* only one cs per stream regardless of mpo */
-+				break;
-+			}
- 		}
- 	}
- 
-@@ -971,24 +980,30 @@ enum dc_status dce110_validate_with_context(
- 	struct dc_context *dc_ctx = dc->ctx;
- 
- 	for (i = 0; i < set_count; i++) {
-+		bool unchanged = false;
-+
- 		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		context->target_count++;
- 
- 		for (j = 0; j < dc->current_context.target_count; j++)
--			if (dc->current_context.targets[j] == context->targets[i])
-+			if (dc->current_context.targets[j]
-+						== context->targets[i]) {
-+				unchanged = true;
- 				set_target_unchanged(context, i);
--
--		if (!context->target_flags[i].unchanged)
--			if (!logical_attach_surfaces_to_target(
--							(struct dc_surface **)set[i].surfaces,
--							set[i].surface_count,
--							&context->targets[i]->public)) {
-+				context->target_status[i] =
-+					dc->current_context.target_status[j];
-+			}
-+		if (!unchanged)
-+			if (!attach_surfaces_to_context(
-+					(struct dc_surface **)set[i].surfaces,
-+					set[i].surface_count,
-+					&context->targets[i]->public,
-+					context)) {
- 				DC_ERROR("Failed to attach surface to target!\n");
- 				return DC_FAIL_ATTACH_SURFACES;
- 			}
- 	}
- 
--	context->target_count = set_count;
--
- 	context->res_ctx.pool = dc->res_pool;
- 
- 	result = map_resources(dc, context);
-@@ -1073,7 +1088,7 @@ bool dce110_construct_resource_pool(
- 
- 	}
- 
--	pool->controller_count =
-+	pool->pipe_count =
- 		dal_adapter_service_get_func_controllers_num(adapter_serv);
- 	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
- 			adapter_serv);
-@@ -1084,7 +1099,7 @@ bool dce110_construct_resource_pool(
- 		goto filter_create_fail;
- 	}
- 
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		pool->timing_generators[i] = dce110_timing_generator_create(
- 				adapter_serv, ctx, i, &dce110_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
-@@ -1134,7 +1149,7 @@ bool dce110_construct_resource_pool(
- 	audio_init_data.as = adapter_serv;
- 	audio_init_data.ctx = ctx;
- 	pool->audio_count = 0;
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		struct graphics_object_id obj_id;
- 
- 		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-@@ -1192,13 +1207,13 @@ stream_enc_create_fail:
- 	}
- 
- audio_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->audios[i] != NULL)
- 			dal_audio_destroy(&pool->audios[i]);
- 	}
- 
- controller_create_fail:
--	for (i = 0; i < pool->controller_count; i++) {
-+	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->opps[i] != NULL)
- 			dce110_opp_destroy(&pool->opps[i]);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index e3dbaeb..18bd2da 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -39,12 +39,10 @@ struct core_stream;
- 	container_of(dc_target, struct core_target, public)
- 
- #define MAX_PIPES 6
--#define MAX_STREAMS 6
- #define MAX_CLOCK_SOURCES 7
- 
- struct core_target {
- 	struct dc_target public;
--	struct dc_target_status status;
- 
- 	struct dc_context *ctx;
- };
-@@ -90,53 +88,12 @@ struct core_stream {
- 	struct dc_stream public;
- 
- 	/* field internal to DC */
-+	struct dc_context *ctx;
- 	const struct core_sink *sink;
- 
--	struct clock_source *clock_source;
--
--	struct mem_input *mi;
--	struct input_pixel_processor *ipp;
--	struct transform *xfm;
--	struct output_pixel_processor *opp;
--	struct timing_generator *tg;
--	struct stream_encoder *stream_enc;
--	struct display_clock *dis_clk;
--
--	struct overscan_info overscan;
--	struct scaling_ratios ratios;
--	struct rect viewport;
--	struct scaling_taps taps;
--	enum pixel_format format;
--
--	uint8_t controller_idx;
--
--	struct audio *audio;
--
--	enum signal_type signal;
--
--	/* TODO: move these members into appropriate places (work in progress)*/
--	/* timing validation (HDMI only) */
--	uint32_t max_tmds_clk_from_edid_in_mhz;
--	/* maximum supported deep color depth for HDMI */
--	enum dc_color_depth max_hdmi_deep_color;
--	/* maximum supported pixel clock for HDMI */
--	uint32_t max_hdmi_pixel_clock;
--	/* end of TODO */
--
--	/*TODO: AUTO merge if possible*/
--	struct pixel_clk_params pix_clk_params;
--	struct pll_settings pll_settings;
--
--	/*fmt*/
--	/*TODO: AUTO new codepath in apply_context to hw to
--	 * generate these bw unrelated/no fail params*/
--	struct bit_depth_reduction_params bit_depth_params;/* used by DCP and FMT */
-+	/* used by DCP and FMT */
-+	struct bit_depth_reduction_params bit_depth_params;
- 	struct clamping_and_pixel_encoding_params clamping;
--	struct hw_info_frame info_frame;
--	struct encoder_info_frame encoder_info_frame;
--
--	struct audio_output audio_output;
--	struct dc_context *ctx;
- 
- 	struct dc_stream_status status;
- };
-@@ -267,13 +224,9 @@ enum dc_status dc_link_validate_mode_timing(
- 
- void core_link_resume(struct core_link *link);
- 
--void core_link_enable_stream(
--		struct core_link *link,
--		struct core_stream *stream);
-+void core_link_enable_stream(struct pipe_ctx *pipe_ctx);
- 
--void core_link_disable_stream(
--		struct core_link *link,
--		struct core_stream *stream);
-+void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
- 
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
-@@ -304,10 +257,10 @@ struct resource_pool {
- 	struct input_pixel_processor *ipps[MAX_PIPES];
- 	struct transform *transforms[MAX_PIPES];
- 	struct output_pixel_processor *opps[MAX_PIPES];
--	struct timing_generator *timing_generators[MAX_STREAMS];
-+	struct timing_generator *timing_generators[MAX_PIPES];
- 	struct stream_encoder *stream_enc[MAX_PIPES * 2];
- 
--	uint8_t controller_count;
-+	uint8_t pipe_count;
- 	uint8_t stream_enc_count;
- 
- 	union supported_stream_engines stream_engines;
-@@ -315,7 +268,7 @@ struct resource_pool {
- 	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
- 	uint8_t clk_src_count;
- 
--	struct audio *audios[MAX_STREAMS];
-+	struct audio *audios[MAX_PIPES];
- 	uint8_t audio_count;
- 
- 	struct display_clock *display_clock;
-@@ -325,9 +278,46 @@ struct resource_pool {
- 	struct resource_funcs *funcs;
- };
- 
--struct controller_ctx {
-+struct pipe_ctx {
- 	struct core_surface *surface;
- 	struct core_stream *stream;
-+
-+	struct mem_input *mi;
-+	struct input_pixel_processor *ipp;
-+	struct transform *xfm;
-+	struct output_pixel_processor *opp;
-+	struct timing_generator *tg;
-+
-+	struct overscan_info overscan;
-+	struct scaling_ratios ratios;
-+	struct rect viewport;
-+	struct scaling_taps taps;
-+	enum pixel_format format;
-+
-+	struct stream_encoder *stream_enc;
-+	struct display_clock *dis_clk;
-+	struct clock_source *clock_source;
-+
-+	struct audio *audio;
-+	struct audio_output audio_output;
-+
-+	enum signal_type signal;
-+
-+	/* timing validation (HDMI only) */
-+	uint32_t max_tmds_clk_from_edid_in_mhz;
-+	/* maximum supported deep color depth for HDMI */
-+	enum dc_color_depth max_hdmi_deep_color;
-+	/* maximum supported pixel clock for HDMI */
-+	uint32_t max_hdmi_pixel_clock;
-+
-+	struct pixel_clk_params pix_clk_params;
-+	struct pll_settings pll_settings;
-+
-+	/*fmt*/
-+	struct encoder_info_frame encoder_info_frame;
-+
-+	uint8_t pipe_idx;
-+
- 	struct flags {
- 		bool unchanged;
- 		bool timing_changed;
-@@ -336,10 +326,10 @@ struct controller_ctx {
- 
- struct resource_context {
- 	struct resource_pool pool;
--	struct controller_ctx controller_ctx[MAX_PIPES];
-+	struct pipe_ctx pipe_ctx[MAX_PIPES];
- 	union supported_stream_engines used_stream_engines;
- 	bool is_stream_enc_acquired[MAX_PIPES * 2];
--	bool is_audio_acquired[MAX_STREAMS];
-+	bool is_audio_acquired[MAX_PIPES];
- 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
-  };
- 
-@@ -348,6 +338,7 @@ struct target_flags {
- };
- struct validate_context {
- 	struct core_target *targets[MAX_PIPES];
-+	struct dc_target_status target_status[MAX_PIPES];
- 	struct target_flags target_flags[MAX_PIPES];
- 	uint8_t target_count;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 5dd16dc..8b0afe1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -39,22 +39,19 @@ enum pipe_gating_control {
- struct hw_sequencer_funcs {
- 
- 	enum dc_status (*apply_ctx_to_hw)(
--			const struct dc *dc, struct validate_context *context);
-+			struct dc *dc, struct validate_context *context);
- 
--	void (*reset_hw_ctx)(
--				struct dc *dc,
--				struct validate_context *context,
--				uint8_t target_count);
-+	void (*reset_hw_ctx)(struct dc *dc, struct validate_context *context);
- 
--	bool (*set_plane_config)(
-+	void (*set_plane_config)(
- 				const struct dc *dc,
- 				struct core_surface *surface,
--				struct core_target *target);
-+				struct pipe_ctx *pipe_ctx);
- 
--	bool (*update_plane_address)(
--				const struct dc *dc,
--				const struct core_surface *surface,
--				struct core_target *target);
-+	void (*update_plane_addrs)(
-+		struct dc *dc,
-+		struct resource_context *res_ctx,
-+		const struct core_surface *surface);
- 
- 	bool (*set_gamma_correction)(
- 				struct input_pixel_processor *ipp,
-@@ -93,9 +90,9 @@ struct hw_sequencer_funcs {
- 
- 	void (*program_bw)(struct dc *dc, struct validate_context *context);
- 
--	void (*enable_stream)(struct core_stream *stream);
-+	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
- 
--	void (*disable_stream)(struct core_stream *stream);
-+	void (*disable_stream)(struct pipe_ctx *pipe_ctx);
- 
- 	void (*enable_fe_clock)(
- 		struct dc_context *ctx, uint8_t controller_id, bool enable);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-index 54e75dc..d11ef05 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-@@ -19,6 +19,7 @@ struct link_mst_stream_allocation_table;
- struct dc_link_settings;
- struct link_training_settings;
- struct core_stream;
-+struct pipe_ctx;
- 
- struct encoder_init_data {
- 	struct adapter_service *adapter_service;
-@@ -82,8 +83,8 @@ struct link_encoder {
- };
- 
- struct link_encoder_funcs {
--	bool (*validate_output_with_stream)(struct link_encoder *enc,
--		struct core_stream *stream);
-+	bool (*validate_output_with_stream)(
-+		struct link_encoder *enc, struct pipe_ctx *pipe_ctx);
- 	void (*hw_init)(struct link_encoder *enc);
- 	void (*setup)(struct link_encoder *enc,
- 		enum signal_type signal);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index 551caa3..d56b5d1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -49,7 +49,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on);
- 
- void dp_disable_link_phy(struct core_link *link, enum signal_type signal);
- 
--void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream);
-+void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal);
- 
- bool dp_set_hw_training_pattern(
- 	struct core_link *link,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index b4936b4..a7b0032 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -38,7 +38,7 @@ bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 
- void build_scaling_params(
- 	const struct dc_surface *surface,
--	struct core_stream *stream);
-+	struct pipe_ctx *pipe_ctx);
- 
- void build_scaling_params_for_context(
- 	const struct dc *dc,
-@@ -57,13 +57,14 @@ bool is_same_timing(
- 	const struct dc_crtc_timing *timing2);
- 
- struct clock_source *find_used_clk_src_for_sharing(
--		struct validate_context *context,
--		struct core_stream *stream);
-+	struct resource_context *res_ctx,
-+	struct pipe_ctx *pipe_ctx);
- 
--bool logical_attach_surfaces_to_target(
-+bool attach_surfaces_to_context(
- 		struct dc_surface *surfaces[],
- 		uint8_t surface_count,
--		struct dc_target *dc_target);
-+		struct dc_target *dc_target,
-+		struct validate_context *context);
- 
- void pplib_apply_safe_state(const struct dc *dc);
- 
-@@ -72,7 +73,7 @@ void pplib_apply_display_requirements(
- 	const struct validate_context *context,
- 	struct dc_pp_display_configuration *pp_display_cfg);
- 
--void build_info_frame(struct core_stream *stream);
-+void build_info_frame(struct pipe_ctx *pipe_ctx);
- 
- enum dc_status map_resources(
- 	const struct dc *dc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-index 36886a4..0b3b1b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -31,7 +31,7 @@
- 
- static bool virtual_link_encoder_validate_output_with_stream(
- 	struct link_encoder *enc,
--	struct core_stream *stream) { return true; }
-+	struct pipe_ctx *pipe_ctx) { return true; }
- 
- static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_csc_types.h b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-index 711b458..5927dd0 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-@@ -28,19 +28,6 @@
- 
- #include "set_mode_types.h"
- 
--enum color_space {
--	COLOR_SPACE_UNKNOWN,
--	COLOR_SPACE_SRGB_FULL_RANGE,
--	COLOR_SPACE_SRGB_LIMITED_RANGE,
--	COLOR_SPACE_YPBPR601,
--	COLOR_SPACE_YPBPR709,
--	COLOR_SPACE_YCBCR601,
--	COLOR_SPACE_YCBCR709,
--	COLOR_SPACE_YCBCR601_YONLY,
--	COLOR_SPACE_YCBCR709_YONLY,
--	COLOR_SPACE_N_MVPU_SUPER_AA,
--};
--
- enum grph_color_adjust_option {
- 	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
- 	GRPH_COLOR_MATRIX_SW
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0790-drm-amd-dal-Instantiate-Underlay-version-of-Timing-G.patch b/common/recipes-kernel/linux/files/0790-drm-amd-dal-Instantiate-Underlay-version-of-Timing-G.patch
deleted file mode 100644
index fc7b8581..00000000
--- a/common/recipes-kernel/linux/files/0790-drm-amd-dal-Instantiate-Underlay-version-of-Timing-G.patch
+++ /dev/null
@@ -1,200 +0,0 @@
-From d37689dccc3eddd13a101bf8739dc0491bd03533 Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Wed, 10 Feb 2016 15:12:56 -0500
-Subject: [PATCH 0790/1110] drm/amd/dal: Instantiate Underlay version of Timing
- Generator and Scaler.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |  3 ++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 22 ++++++++++++++++++----
- .../amd/dal/dc/dce110/dce110_timing_generator_v.c  | 16 +---------------
- 3 files changed, 21 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-index 2d0007b..71aa9d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -8,7 +8,8 @@ dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
- dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
- dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
- dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
--dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o
-+dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o \
-+dce110_timing_generator_v.o
- 
- AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 4fdf1f0..42e7306 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -32,10 +32,12 @@
- #include "include/irq_service_interface.h"
- #include "../virtual/virtual_stream_encoder.h"
- #include "dce110/dce110_timing_generator.h"
-+#include "dce110/dce110_timing_generator_v.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_mem_input.h"
- #include "dce110/dce110_ipp.h"
- #include "dce110/dce110_transform.h"
-+#include "dce110/dce110_transform_v.h"
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
- #include "dce110/dce110_clock_source.h"
-@@ -305,8 +307,14 @@ static struct timing_generator *dce110_timing_generator_create(
- 	if (!tg110)
- 		return NULL;
- 
--	if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
--		return &tg110->base;
-+	if (instance == 3) {
-+		/* This is the Underlay instance. */
-+		if (dce110_timing_generator_v_construct(tg110, as, ctx))
-+			return &tg110->base;
-+	} else {
-+		if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
-+			return &tg110->base;
-+	}
- 
- 	BREAK_TO_DEBUGGER();
- 	dm_free(ctx, tg110);
-@@ -370,8 +378,14 @@ static struct transform *dce110_transform_create(
- 	if (!transform)
- 		return NULL;
- 
--	if (dce110_transform_construct(transform, ctx, inst, offsets))
--		return &transform->base;
-+	if (inst == 3) {
-+		/* Underlay */
-+		if (dce110_transform_v_construct(transform, ctx))
-+			return &transform->base;
-+	} else {
-+		if (dce110_transform_construct(transform, ctx, inst, offsets))
-+			return &transform->base;
-+	}
- 
- 	BREAK_TO_DEBUGGER();
- 	dm_free(ctx, transform);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index 722f636..08588f7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -36,7 +36,6 @@ static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
-      */
- 
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	value = dm_read_reg(tg->ctx,
- 			mmCRTCV_MASTER_UPDATE_MODE);
-@@ -58,7 +57,6 @@ static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
- static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
- {
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	value = dm_read_reg(tg->ctx,
- 			mmCRTCV_CONTROL);
-@@ -126,7 +124,6 @@ static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
- 
- static bool dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = mmCRTCV_BLANK_CONTROL;
- 	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
-@@ -153,7 +150,6 @@ static bool dce110_timing_generator_v_is_in_vertical_blank(
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 	uint32_t field = 0;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	addr = mmCRTCV_STATUS;
- 	value = dm_read_reg(tg->ctx, addr);
-@@ -164,8 +160,6 @@ static bool dce110_timing_generator_v_is_in_vertical_blank(
- static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg)
- {
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
--
- 	uint32_t h1 = 0;
- 	uint32_t h2 = 0;
- 	uint32_t v1 = 0;
-@@ -263,7 +257,6 @@ static void dce110_timing_generator_v_program_blanking(
- 	uint32_t hsync_offset = timing->h_border_right +
- 			timing->h_front_porch;
- 	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
-@@ -339,7 +332,6 @@ static void dce110_timing_generator_v_enable_advanced_request(
- 	bool enable,
- 	const struct dc_crtc_timing *timing)
- {
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = mmCRTCV_START_LINE_CONTROL;
- 	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
-@@ -402,7 +394,6 @@ static void dce110_timing_generator_v_program_blank_color(
- 		enum color_space color_space)
- {
- 	struct crtc_black_color black_color;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = mmCRTCV_BLACK_COLOR;
- 	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
-@@ -436,7 +427,7 @@ static void dce110_timing_generator_v_set_overscan_color_black(
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
- 	uint32_t addr;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
- 	/* Overscan Color for YUV display modes:
- 	 * to achieve a black color for both the explicit and implicit overscan,
- 	 * the overscan color registers should be programmed to: */
-@@ -558,7 +549,6 @@ static void dce110_timing_generator_v_set_overscan_color_black(
- static void dce110_tg_v_program_blank_color(struct timing_generator *tg,
- 		const struct crtc_black_color *black_color)
- {
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = mmCRTCV_BLACK_COLOR;
- 	uint32_t value = dm_read_reg(tg->ctx, addr);
- 
-@@ -590,7 +580,6 @@ static void dce110_timing_generator_v_set_overscan_color(struct timing_generator
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
- 	uint32_t addr;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	set_reg_field_value(
- 		value,
-@@ -630,7 +619,6 @@ static void dce110_timing_generator_v_set_early_control(
- 		uint32_t early_cntl)
- {
- 	uint32_t regval;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t address = mmCRTC_CONTROL;
- 
- 	regval = dm_read_reg(tg->ctx, address);
-@@ -645,7 +633,6 @@ static void dce110_timing_generator_v_get_crtc_positions(
- 	int32_t *v_position)
- {
- 	uint32_t value;
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
- 	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
- 
-@@ -662,7 +649,6 @@ static void dce110_timing_generator_v_get_crtc_positions(
- 
- static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg)
- {
--	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT;
- 	uint32_t value = dm_read_reg(tg->ctx, addr);
- 	uint32_t field = get_reg_field_value(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0791-drm-amd-dal-opp-for-underlay.patch b/common/recipes-kernel/linux/files/0791-drm-amd-dal-opp-for-underlay.patch
deleted file mode 100644
index 21736168..00000000
--- a/common/recipes-kernel/linux/files/0791-drm-amd-dal-opp-for-underlay.patch
+++ /dev/null
@@ -1,1822 +0,0 @@
-From 4330564057ab3f66dd1d72284d99f15208b5c474 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Tue, 9 Feb 2016 16:47:42 -0500
-Subject: [PATCH 0791/1110] drm/amd/dal: opp for underlay.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |    2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |    3 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c   | 1050 ++++++++++++++++++++
- .../drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c   |  520 ++++++++++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c   |   75 ++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |   55 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |    2 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               |   15 +
- 8 files changed, 1719 insertions(+), 3 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-index 71aa9d8..deae715 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -9,7 +9,7 @@ dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
- dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
- dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
- dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o \
--dce110_timing_generator_v.o
-+dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o
- 
- AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 394f187..86bf8c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -49,7 +49,8 @@ struct opp_funcs funcs = {
- 		.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
- 		.opp_set_csc_default = dce110_opp_set_csc_default,
- 		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
--		.opp_set_regamma = dce110_opp_set_regamma
-+		.opp_set_regamma = dce110_opp_set_regamma,
-+		.opp_destroy = dce110_opp_destroy,
- };
- 
- bool dce110_opp_construct(struct dce110_opp *opp110,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-new file mode 100644
-index 0000000..6ca749e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-@@ -0,0 +1,1050 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dce110_opp.h"
-+#include "basics/conversion.h"
-+#include "video_csc_types.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+enum {
-+	OUTPUT_CSC_MATRIX_SIZE = 12
-+};
-+
-+/* constrast:0 - 2.0, default 1.0 */
-+#define UNDERLAY_CONTRAST_DEFAULT 100
-+#define UNDERLAY_CONTRAST_MAX     200
-+#define UNDERLAY_CONTRAST_MIN       0
-+#define UNDERLAY_CONTRAST_STEP      1
-+#define UNDERLAY_CONTRAST_DIVIDER 100
-+
-+/* Saturation: 0 - 2.0; default 1.0 */
-+#define UNDERLAY_SATURATION_DEFAULT   100 /*1.00*/
-+#define UNDERLAY_SATURATION_MIN         0
-+#define UNDERLAY_SATURATION_MAX       200 /* 2.00 */
-+#define UNDERLAY_SATURATION_STEP        1 /* 0.01 */
-+/*actual max overlay saturation
-+ * value = UNDERLAY_SATURATION_MAX /UNDERLAY_SATURATION_DIVIDER
-+ */
-+
-+/* Hue */
-+#define  UNDERLAY_HUE_DEFAULT      0
-+#define  UNDERLAY_HUE_MIN       -300
-+#define  UNDERLAY_HUE_MAX        300
-+#define  UNDERLAY_HUE_STEP         5
-+#define  UNDERLAY_HUE_DIVIDER   10 /* HW range: -30 ~ +30 */
-+#define UNDERLAY_SATURATION_DIVIDER   100
-+
-+/* Brightness: in DAL usually -.25 ~ .25.
-+ * In MMD is -100 to +100 in 16-235 range; which when scaled to full range is
-+ *  ~-116 to +116. When normalized this is about 0.4566.
-+ * With 100 divider this becomes 46, but we may use another for better precision
-+ * The ideal one is 100/219 ((100/255)*(255/219)),
-+ * i.e. min/max = +-100, divider = 219
-+ * default 0.0
-+ */
-+#define  UNDERLAY_BRIGHTNESS_DEFAULT    0
-+#define  UNDERLAY_BRIGHTNESS_MIN      -46 /* ~116/255 */
-+#define  UNDERLAY_BRIGHTNESS_MAX       46
-+#define  UNDERLAY_BRIGHTNESS_STEP       1 /*  .01 */
-+#define  UNDERLAY_BRIGHTNESS_DIVIDER  100
-+
-+struct out_csc_color_matrix {
-+	enum color_space color_space;
-+	uint16_t regval[OUTPUT_CSC_MATRIX_SIZE];
-+};
-+
-+static const struct out_csc_color_matrix global_color_matrix[] = {
-+{ COLOR_SPACE_SRGB_FULL_RANGE,
-+	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+{ COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
-+{ COLOR_SPACE_YCBCR601,
-+	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
-+		0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-+	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-+/*  YOnly same as YCbCr709 but Y in Full range -To do. */
-+{ COLOR_SPACE_YCBCR601_YONLY, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709_YONLY, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
-+};
-+
-+enum csc_color_mode {
-+	/* 00 - BITS2:0 Bypass */
-+	CSC_COLOR_MODE_GRAPHICS_BYPASS,
-+	/* 01 - hard coded coefficient TV RGB */
-+	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
-+	/* 04 - programmable OUTPUT CSC coefficient */
-+	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
-+};
-+
-+static void program_color_matrix_v(
-+	struct dce110_opp *opp110,
-+	const struct out_csc_color_matrix *tbl_entry,
-+	enum grph_color_adjust_option options)
-+{
-+	struct dc_context *ctx = opp110->base.ctx;
-+	uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);
-+	bool use_set_a = (get_reg_field_value(cntl_value,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE) != 4);
-+
-+	set_reg_field_value(
-+			cntl_value,
-+		0,
-+		COL_MAN_OUTPUT_CSC_CONTROL,
-+		OUTPUT_CSC_MODE);
-+
-+	if (use_set_a) {
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C11_C12_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[0],
-+				OUTPUT_CSC_C11_C12_A,
-+				OUTPUT_CSC_C11_A);
-+
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[1],
-+				OUTPUT_CSC_C11_C12_A,
-+				OUTPUT_CSC_C12_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C13_C14_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[2],
-+				OUTPUT_CSC_C13_C14_A,
-+				OUTPUT_CSC_C13_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[3],
-+				OUTPUT_CSC_C13_C14_A,
-+				OUTPUT_CSC_C14_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C21_C22_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[4],
-+				OUTPUT_CSC_C21_C22_A,
-+				OUTPUT_CSC_C21_A);
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[5],
-+				OUTPUT_CSC_C21_C22_A,
-+				OUTPUT_CSC_C22_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C23_C24_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[6],
-+				OUTPUT_CSC_C23_C24_A,
-+				OUTPUT_CSC_C23_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[7],
-+				OUTPUT_CSC_C23_C24_A,
-+				OUTPUT_CSC_C24_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C31_C32_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[8],
-+				OUTPUT_CSC_C31_C32_A,
-+				OUTPUT_CSC_C31_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[9],
-+				OUTPUT_CSC_C31_C32_A,
-+				OUTPUT_CSC_C32_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C33_C34_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[10],
-+				OUTPUT_CSC_C33_C34_A,
-+				OUTPUT_CSC_C33_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[11],
-+				OUTPUT_CSC_C33_C34_A,
-+				OUTPUT_CSC_C34_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		set_reg_field_value(
-+			cntl_value,
-+			4,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE);
-+	} else {
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C11_C12_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[0],
-+				OUTPUT_CSC_C11_C12_B,
-+				OUTPUT_CSC_C11_B);
-+
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[1],
-+				OUTPUT_CSC_C11_C12_B,
-+				OUTPUT_CSC_C12_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C13_C14_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[2],
-+				OUTPUT_CSC_C13_C14_B,
-+				OUTPUT_CSC_C13_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[3],
-+				OUTPUT_CSC_C13_C14_B,
-+				OUTPUT_CSC_C14_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C21_C22_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[4],
-+				OUTPUT_CSC_C21_C22_B,
-+				OUTPUT_CSC_C21_B);
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[5],
-+				OUTPUT_CSC_C21_C22_B,
-+				OUTPUT_CSC_C22_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C23_C24_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[6],
-+				OUTPUT_CSC_C23_C24_B,
-+				OUTPUT_CSC_C23_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[7],
-+				OUTPUT_CSC_C23_C24_B,
-+				OUTPUT_CSC_C24_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C31_C32_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[8],
-+				OUTPUT_CSC_C31_C32_B,
-+				OUTPUT_CSC_C31_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[9],
-+				OUTPUT_CSC_C31_C32_B,
-+				OUTPUT_CSC_C32_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C33_C34_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[10],
-+				OUTPUT_CSC_C33_C34_B,
-+				OUTPUT_CSC_C33_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[11],
-+				OUTPUT_CSC_C33_C34_B,
-+				OUTPUT_CSC_C34_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		set_reg_field_value(
-+			cntl_value,
-+			5,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE);
-+	}
-+
-+	dm_write_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL, cntl_value);
-+}
-+
-+/*
-+ * initialize_color_float_adj_reference_values
-+ * This initialize display color adjust input from API to HW range for later
-+ * calculation use. This is shared by all the display color adjustment.
-+ * @param :
-+ * @return None
-+ */
-+static void initialize_color_float_adj_reference_values(
-+	const struct grph_csc_adjustment *adjust,
-+	struct fixed31_32 *grph_cont,
-+	struct fixed31_32 *grph_sat,
-+	struct fixed31_32 *grph_bright,
-+	struct fixed31_32 *sin_grph_hue,
-+	struct fixed31_32 *cos_grph_hue)
-+{
-+	/* Hue adjustment could be negative. -45 ~ +45 */
-+	struct fixed31_32 hue =
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_from_fraction(adjust->grph_hue, 180),
-+			dal_fixed31_32_pi);
-+
-+	*sin_grph_hue = dal_fixed31_32_sin(hue);
-+	*cos_grph_hue = dal_fixed31_32_cos(hue);
-+
-+	if (adjust->adjust_divider) {
-+		*grph_cont =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_cont,
-+				adjust->adjust_divider);
-+		*grph_sat =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_sat,
-+				adjust->adjust_divider);
-+		*grph_bright =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_bright,
-+				adjust->adjust_divider);
-+	} else {
-+		*grph_cont = dal_fixed31_32_from_int(adjust->grph_cont);
-+		*grph_sat = dal_fixed31_32_from_int(adjust->grph_sat);
-+		*grph_bright = dal_fixed31_32_from_int(adjust->grph_bright);
-+	}
-+}
-+
-+static inline struct fixed31_32 fixed31_32_clamp(
-+	struct fixed31_32 value,
-+	int32_t min_numerator,
-+	int32_t max_numerator,
-+	int32_t denominator)
-+{
-+	return dal_fixed31_32_clamp(
-+		value,
-+		dal_fixed31_32_from_fraction(
-+			min_numerator,
-+			denominator),
-+		dal_fixed31_32_from_fraction(
-+			max_numerator,
-+			denominator));
-+}
-+
-+static void setup_reg_format(
-+	struct fixed31_32 *coefficients,
-+	uint16_t *reg_values)
-+{
-+	enum {
-+		LENGTH = 12,
-+		DENOMINATOR = 10000
-+	};
-+
-+	static const int32_t min_numerator[] = {
-+		-3 * DENOMINATOR,
-+		-DENOMINATOR
-+	};
-+
-+	static const int32_t max_numerator[] = {
-+		DENOMINATOR,
-+		DENOMINATOR
-+	};
-+
-+	static const uint8_t integer_bits[] = { 2, 0 };
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		const uint32_t index = (i % 4) == 3;
-+
-+		reg_values[i] = fixed_point_to_int_frac(
-+			fixed31_32_clamp(coefficients[(i + 8) % LENGTH],
-+				min_numerator[index],
-+				max_numerator[index],
-+				DENOMINATOR),
-+			integer_bits[index], 13);
-+
-+		++i;
-+	} while (i != LENGTH);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: setup_adjustments
-+ *  @note prepare to setup the values
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-+	struct dc_csc_adjustments *adjustments)
-+{
-+	if (adjust->adjust_divider != 0) {
-+		adjustments->brightness =
-+			dal_fixed31_32_from_fraction(adjust->grph_bright,
-+			adjust->adjust_divider);
-+		adjustments->contrast =
-+			dal_fixed31_32_from_fraction(adjust->grph_cont,
-+			adjust->adjust_divider);
-+		adjustments->saturation =
-+			dal_fixed31_32_from_fraction(adjust->grph_sat,
-+			adjust->adjust_divider);
-+	} else {
-+		adjustments->brightness =
-+			dal_fixed31_32_from_fraction(adjust->grph_bright, 1);
-+		adjustments->contrast =
-+			dal_fixed31_32_from_fraction(adjust->grph_cont, 1);
-+		adjustments->saturation =
-+			dal_fixed31_32_from_fraction(adjust->grph_sat, 1);
-+	}
-+
-+	/* convert degrees into radians */
-+	adjustments->hue =
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_from_fraction(adjust->grph_hue, 180),
-+			dal_fixed31_32_pi);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_rgb_adjustment_legacy
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for sRGB color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_rgb_adjustment_legacy(
-+	struct dce110_opp *opp110,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	const struct fixed31_32 k1 =
-+		dal_fixed31_32_from_fraction(701000, 1000000);
-+	const struct fixed31_32 k2 =
-+		dal_fixed31_32_from_fraction(236568, 1000000);
-+	const struct fixed31_32 k3 =
-+		dal_fixed31_32_from_fraction(-587000, 1000000);
-+	const struct fixed31_32 k4 =
-+		dal_fixed31_32_from_fraction(464432, 1000000);
-+	const struct fixed31_32 k5 =
-+		dal_fixed31_32_from_fraction(-114000, 1000000);
-+	const struct fixed31_32 k6 =
-+		dal_fixed31_32_from_fraction(-701000, 1000000);
-+	const struct fixed31_32 k7 =
-+		dal_fixed31_32_from_fraction(-299000, 1000000);
-+	const struct fixed31_32 k8 =
-+		dal_fixed31_32_from_fraction(-292569, 1000000);
-+	const struct fixed31_32 k9 =
-+		dal_fixed31_32_from_fraction(413000, 1000000);
-+	const struct fixed31_32 k10 =
-+		dal_fixed31_32_from_fraction(-92482, 1000000);
-+	const struct fixed31_32 k11 =
-+		dal_fixed31_32_from_fraction(-114000, 1000000);
-+	const struct fixed31_32 k12 =
-+		dal_fixed31_32_from_fraction(385051, 1000000);
-+	const struct fixed31_32 k13 =
-+		dal_fixed31_32_from_fraction(-299000, 1000000);
-+	const struct fixed31_32 k14 =
-+		dal_fixed31_32_from_fraction(886000, 1000000);
-+	const struct fixed31_32 k15 =
-+		dal_fixed31_32_from_fraction(-587000, 1000000);
-+	const struct fixed31_32 k16 =
-+		dal_fixed31_32_from_fraction(-741914, 1000000);
-+	const struct fixed31_32 k17 =
-+		dal_fixed31_32_from_fraction(886000, 1000000);
-+	const struct fixed31_32 k18 =
-+		dal_fixed31_32_from_fraction(-144086, 1000000);
-+
-+	const struct fixed31_32 luma_r =
-+		dal_fixed31_32_from_fraction(299, 1000);
-+	const struct fixed31_32 luma_g =
-+		dal_fixed31_32_from_fraction(587, 1000);
-+	const struct fixed31_32 luma_b =
-+		dal_fixed31_32_from_fraction(114, 1000);
-+
-+	struct out_csc_color_matrix tbl_entry;
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	struct fixed31_32 grph_cont;
-+	struct fixed31_32 grph_sat;
-+	struct fixed31_32 grph_bright;
-+	struct fixed31_32 sin_grph_hue;
-+	struct fixed31_32 cos_grph_hue;
-+
-+	initialize_color_float_adj_reference_values(
-+		adjust, &grph_cont, &grph_sat,
-+		&grph_bright, &sin_grph_hue, &cos_grph_hue);
-+
-+	/* COEF_1_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 +
-+	 * Sin(GrphHue) * K2))
-+	 * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)
-+	 */
-+	matrix[0] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k1),
-+			dal_fixed31_32_mul(sin_grph_hue, k2));
-+	/* GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2 */
-+	matrix[0] = dal_fixed31_32_mul(grph_sat, matrix[0]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)) */
-+	matrix[0] = dal_fixed31_32_add(luma_r, matrix[0]);
-+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) *
-+	 * K2))
-+	 */
-+	matrix[0] = dal_fixed31_32_mul(grph_cont, matrix[0]);
-+
-+	/* COEF_1_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 +
-+	 * Sin(GrphHue) * K4))
-+	 * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)
-+	 */
-+	matrix[1] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k3),
-+			dal_fixed31_32_mul(sin_grph_hue, k4));
-+	/* GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4) */
-+	matrix[1] = dal_fixed31_32_mul(grph_sat, matrix[1]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)) */
-+	matrix[1] = dal_fixed31_32_add(luma_g, matrix[1]);
-+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) *
-+	 * K4))
-+	 */
-+	matrix[1] = dal_fixed31_32_mul(grph_cont, matrix[1]);
-+
-+	/* COEF_1_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 +
-+	 * Sin(GrphHue) * K6))
-+	 * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)
-+	 */
-+	matrix[2] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k5),
-+			dal_fixed31_32_mul(sin_grph_hue, k6));
-+	/* GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] = dal_fixed31_32_mul(grph_sat, matrix[2]);
-+	/* LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] = dal_fixed31_32_add(luma_b, matrix[2]);
-+	/* GrphCont  * (LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) *
-+	 * K6))
-+	 */
-+	matrix[2] = dal_fixed31_32_mul(grph_cont, matrix[2]);
-+
-+	/* COEF_1_4 = GrphBright */
-+	matrix[3] = grph_bright;
-+
-+	/* COEF_2_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 +
-+	 * Sin(GrphHue) * K8))
-+	 * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)
-+	 */
-+	matrix[4] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k7),
-+			dal_fixed31_32_mul(sin_grph_hue, k8));
-+	/* GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8) */
-+	matrix[4] = dal_fixed31_32_mul(grph_sat, matrix[4]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)) */
-+	matrix[4] = dal_fixed31_32_add(luma_r, matrix[4]);
-+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) *
-+	 * K8))
-+	 */
-+	matrix[4] = dal_fixed31_32_mul(grph_cont, matrix[4]);
-+
-+	/* COEF_2_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 +
-+	 * Sin(GrphHue) * K10))
-+	 * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))
-+	 */
-+	matrix[5] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k9),
-+			dal_fixed31_32_mul(sin_grph_hue, k10));
-+	/* GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] = dal_fixed31_32_mul(grph_sat, matrix[5]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] = dal_fixed31_32_add(luma_g, matrix[5]);
-+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) *
-+	 * K10))
-+	 */
-+	matrix[5] = dal_fixed31_32_mul(grph_cont, matrix[5]);
-+
-+	/*  COEF_2_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 +
-+	 * Sin(GrphHue) * K12))
-+	 * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))
-+	 */
-+	matrix[6] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k11),
-+			dal_fixed31_32_mul(sin_grph_hue, k12));
-+	/* GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] = dal_fixed31_32_mul(grph_sat, matrix[6]);
-+	/*  (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] = dal_fixed31_32_add(luma_b, matrix[6]);
-+	/* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) *
-+	 * K12))
-+	 */
-+	matrix[6] = dal_fixed31_32_mul(grph_cont, matrix[6]);
-+
-+	/* COEF_2_4 = GrphBright */
-+	matrix[7] = grph_bright;
-+
-+	/* COEF_3_1 = GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 +
-+	 * Sin(GrphHue) * K14))
-+	 * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14))
-+	 */
-+	matrix[8] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k13),
-+			dal_fixed31_32_mul(sin_grph_hue, k14));
-+	/* GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] = dal_fixed31_32_mul(grph_sat, matrix[8]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] = dal_fixed31_32_add(luma_r, matrix[8]);
-+	/* GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) *
-+	 * K14))
-+	 */
-+	matrix[8] = dal_fixed31_32_mul(grph_cont, matrix[8]);
-+
-+	/* COEF_3_2    = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 +
-+	 * Sin(GrphHue) * K16))
-+	 * GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)
-+	 */
-+	matrix[9] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k15),
-+			dal_fixed31_32_mul(sin_grph_hue, k16));
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
-+	matrix[9] = dal_fixed31_32_mul(grph_sat, matrix[9]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
-+	matrix[9] = dal_fixed31_32_add(luma_g, matrix[9]);
-+	 /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) *
-+	  * K16))
-+	  */
-+	matrix[9] = dal_fixed31_32_mul(grph_cont, matrix[9]);
-+
-+	/*  COEF_3_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 +
-+	 * Sin(GrphHue) * K18))
-+	 * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18))
-+	 */
-+	matrix[10] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k17),
-+			dal_fixed31_32_mul(sin_grph_hue, k18));
-+	/*  GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] = dal_fixed31_32_mul(grph_sat, matrix[10]);
-+	/* (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] = dal_fixed31_32_add(luma_b, matrix[10]);
-+	 /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) *
-+	  * K18))
-+	  */
-+	matrix[10] = dal_fixed31_32_mul(grph_cont, matrix[10]);
-+
-+	/*  COEF_3_4    = GrphBright */
-+	matrix[11] = grph_bright;
-+
-+	tbl_entry.color_space = adjust->c_space;
-+
-+	convert_float_matrix(tbl_entry.regval, matrix, OUTPUT_CSC_MATRIX_SIZE);
-+
-+	program_color_matrix_v(
-+		opp110, &tbl_entry, adjust->color_adjust_option);
-+}
-+
-+static void prepare_yuv_ideal(
-+	bool b601,
-+	struct fixed31_32 *matrix)
-+{
-+	static const int32_t matrix_1[] = {
-+		25578516, 50216016, 9752344, 6250000,
-+		-14764391, -28985609, 43750000, 50000000,
-+		43750000, -36635164, -7114836, 50000000
-+	};
-+
-+	static const int32_t matrix_2[] = {
-+		18187266, 61183125, 6176484, 6250000,
-+		-10025059, -33724941, 43750000, 50000000,
-+		43750000, -39738379, -4011621, 50000000
-+	};
-+
-+	const int32_t *matrix_x = b601 ? matrix_1 : matrix_2;
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		matrix[i] = dal_fixed31_32_from_fraction(
-+			matrix_x[i],
-+			100000000);
-+		++i;
-+	} while (i != ARRAY_SIZE(matrix_1));
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_yuv_adjustment
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for YUV  color spaces
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_yuv_adjustment(
-+	struct dce110_opp *opp110,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR601_YONLY);
-+	struct out_csc_color_matrix reg_matrix;
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct dc_csc_adjustments adjustments;
-+	struct fixed31_32 ideals[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	prepare_yuv_ideal(b601, ideals);
-+
-+	setup_adjustments(adjust, &adjustments);
-+
-+	if ((adjust->c_space == COLOR_SPACE_YCBCR601_YONLY) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR709_YONLY))
-+		calculate_adjustments_y_only(
-+			ideals, &adjustments, matrix);
-+	else
-+		calculate_adjustments(
-+			ideals, &adjustments, matrix);
-+
-+	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+
-+	setup_reg_format(matrix, reg_matrix.regval);
-+
-+	program_color_matrix_v(opp110, &reg_matrix, GRPH_COLOR_MATRIX_SW);
-+}
-+
-+static bool configure_graphics_mode_v(
-+	struct dce110_opp *opp110,
-+	enum csc_color_mode config,
-+	enum graphics_csc_adjust_type csc_adjust_type,
-+	enum color_space color_space)
-+{
-+	struct dc_context *ctx = opp110->base.ctx;
-+	uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		COL_MAN_OUTPUT_CSC_CONTROL,
-+		OUTPUT_CSC_MODE);
-+
-+	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
-+		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC)
-+			return true;
-+
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB_FULL_RANGE:
-+			/* by pass */
-+			set_reg_field_value(
-+				value,
-+				0,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+			/* not supported for underlay on CZ */
-+			return false;
-+
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YPBPR601:
-+		case COLOR_SPACE_YCBCR601_YONLY:
-+			/* YCbCr601 */
-+			set_reg_field_value(
-+				value,
-+				2,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YPBPR709:
-+		case COLOR_SPACE_YCBCR709_YONLY:
-+			/* YCbCr709 */
-+			set_reg_field_value(
-+				value,
-+				3,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB_FULL_RANGE:
-+			/* by pass */
-+			set_reg_field_value(
-+				value,
-+				0,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+			/* not supported for underlay on CZ */
-+			return false;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YPBPR601:
-+		case COLOR_SPACE_YCBCR601_YONLY:
-+			/* YCbCr601 */
-+			set_reg_field_value(
-+				value,
-+				2,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YPBPR709:
-+		case COLOR_SPACE_YCBCR709_YONLY:
-+			 /* YCbCr709 */
-+			set_reg_field_value(
-+				value,
-+				3,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else
-+		/* by pass */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE);
-+
-+	addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
-+	dm_write_reg(ctx, addr, value);
-+
-+	return true;
-+}
-+
-+static void set_Denormalization(struct output_pixel_processor *opp,
-+		enum dc_color_depth color_depth)
-+{
-+	uint32_t value = dm_read_reg(opp->ctx, mmDENORM_CLAMP_CONTROL);
-+
-+	switch (color_depth) {
-+	case COLOR_DEPTH_888:
-+		/* 255/256 for 8 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DENORM_CLAMP_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 1023/1024 for 10 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			2,
-+			DENORM_CLAMP_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 4095/4096 for 12 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DENORM_CLAMP_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	default:
-+		/* not valid case */
-+		break;
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DENORM_CLAMP_CONTROL,
-+		DENORM_10BIT_OUT);
-+
-+	dm_write_reg(opp->ctx, mmDENORM_CLAMP_CONTROL, value);
-+}
-+
-+
-+void dce110_opp_v_set_csc_default(
-+	struct output_pixel_processor *opp,
-+	const struct default_adjustment *default_adjust)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
-+
-+	if (default_adjust->force_hw_default == false) {
-+		const struct out_csc_color_matrix *elm;
-+		/* currently parameter not in use */
-+		enum grph_color_adjust_option option =
-+			GRPH_COLOR_MATRIX_HW_DEFAULT;
-+		uint32_t i;
-+		/*
-+		 * HW default false we program locally defined matrix
-+		 * HW default true  we use predefined hw matrix and we
-+		 * do not need to program matrix
-+		 * OEM wants the HW default via runtime parameter.
-+		 */
-+		option = GRPH_COLOR_MATRIX_SW;
-+
-+		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
-+			elm = &global_color_matrix[i];
-+			if (elm->color_space != default_adjust->color_space)
-+				continue;
-+			/* program the matrix with default values from this
-+			 * file
-+			 */
-+			program_color_matrix_v(opp110, elm, option);
-+			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+			break;
-+		}
-+	}
-+
-+	/* configure the what we programmed :
-+	 * 1. Default values from this file
-+	 * 2. Use hardware default from ROM_A and we do not need to program
-+	 * matrix
-+	 */
-+
-+	configure_graphics_mode_v(opp110, config,
-+		default_adjust->csc_adjust_type,
-+		default_adjust->color_space);
-+
-+	set_Denormalization(opp, default_adjust->color_depth);
-+}
-+
-+void dce110_opp_v_set_csc_adjustment(
-+	struct output_pixel_processor *opp,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+
-+	/* Apply color adjustments: brightness, saturation, hue, contrast and
-+	 * CSC. No need for different color space routine, color space defines
-+	 * the ideal values only, but keep original design to allow quick switch
-+	 * to the old legacy routines
-+	 */
-+	switch (adjust->c_space) {
-+	case COLOR_SPACE_SRGB_FULL_RANGE:
-+		set_rgb_adjustment_legacy(opp110, adjust);
-+		break;
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_YONLY:
-+	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YPBPR601:
-+	case COLOR_SPACE_YPBPR709:
-+		set_yuv_adjustment(opp110, adjust);
-+		break;
-+	default:
-+		set_rgb_adjustment_legacy(opp110, adjust);
-+		break;
-+	}
-+
-+	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-+	configure_graphics_mode_v(opp110, config, adjust->csc_adjust_type,
-+		adjust->c_space);
-+
-+	set_Denormalization(opp, adjust->color_depth);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-new file mode 100644
-index 0000000..4f6cc9c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-@@ -0,0 +1,520 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_opp.h"
-+#include "gamma_types.h"
-+
-+static void power_on_lut(struct output_pixel_processor *opp,
-+	bool power_on, bool inputgamma, bool regamma)
-+{
-+	uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
-+	int i;
-+
-+	if (power_on) {
-+		if (inputgamma)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
-+		if (regamma)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
-+	} else {
-+		if (inputgamma)
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
-+		if (regamma)
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
-+	}
-+
-+	dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
-+
-+	for (i = 0; i < 3; i++) {
-+		value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
-+		if (get_reg_field_value(value,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS) &&
-+			get_reg_field_value(value,
-+					DCFEV_MEM_PWR_CTRL,
-+					COL_MAN_GAMMA_CORR_MEM_PWR_DIS))
-+			break;
-+
-+		dm_delay_in_microseconds(opp->ctx, 2);
-+	}
-+}
-+
-+static void set_bypass_input_gamma(struct dce110_opp *opp110)
-+{
-+	uint32_t value;
-+
-+	value = dm_read_reg(opp110->base.ctx,
-+			mmCOL_MAN_INPUT_GAMMA_CONTROL1);
-+
-+	set_reg_field_value(
-+				value,
-+				0,
-+				COL_MAN_INPUT_GAMMA_CONTROL1,
-+				INPUT_GAMMA_MODE);
-+
-+	dm_write_reg(opp110->base.ctx,
-+			mmCOL_MAN_INPUT_GAMMA_CONTROL1, value);
-+}
-+
-+static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
-+{
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+				value,
-+				mode,
-+				GAMMA_CORR_CONTROL,
-+				GAMMA_CORR_MODE);
-+
-+	dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CONTROL, 0);
-+}
-+
-+/*
-+ *****************************************************************************
-+ *  Function: regamma_config_regions_and_segments
-+ *
-+ *     build regamma curve by using predefined hw points
-+ *     uses interface parameters ,like EDID coeff.
-+ *
-+ * @param   : parameters   interface parameters
-+ *  @return void
-+ *
-+ *  @note
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void regamma_config_regions_and_segments(
-+	struct dce110_opp *opp110, const struct regamma_params *params)
-+{
-+	const struct gamma_curve *curve;
-+	uint32_t value = 0;
-+
-+	{
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[0].custom_float_x,
-+			GAMMA_CORR_CNTLA_START_CNTL,
-+			GAMMA_CORR_CNTLA_EXP_REGION_START);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			GAMMA_CORR_CNTLA_START_CNTL,
-+			GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT);
-+
-+		dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
-+				value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[0].custom_float_slope,
-+			GAMMA_CORR_CNTLA_SLOPE_CNTL,
-+			GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_SLOPE_CNTL, value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_x,
-+			GAMMA_CORR_CNTLA_END_CNTL1,
-+			GAMMA_CORR_CNTLA_EXP_REGION_END);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_END_CNTL1, value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[2].custom_float_slope,
-+			GAMMA_CORR_CNTLA_END_CNTL2,
-+			GAMMA_CORR_CNTLA_EXP_REGION_END_BASE);
-+
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_y,
-+			GAMMA_CORR_CNTLA_END_CNTL2,
-+			GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_END_CNTL2, value);
-+	}
-+
-+	curve = params->arr_curve_points;
-+
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS);
-+
-+		dm_write_reg(
-+			opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_0_1,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_2_3,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_4_5,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_6_7,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_8_9,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_10_11,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_12_13,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp110->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_14_15,
-+			value);
-+	}
-+}
-+
-+static void program_pwl(struct dce110_opp *opp110,
-+		const struct regamma_params *params)
-+{
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		7,
-+		GAMMA_CORR_LUT_WRITE_EN_MASK,
-+		GAMMA_CORR_LUT_WRITE_EN_MASK);
-+
-+	dm_write_reg(opp110->base.ctx,
-+		mmGAMMA_CORR_LUT_WRITE_EN_MASK, value);
-+
-+	dm_write_reg(opp110->base.ctx,
-+		mmGAMMA_CORR_LUT_INDEX, 0);
-+
-+	/* Program REGAMMA_LUT_DATA */
-+	{
-+		const uint32_t addr = mmGAMMA_CORR_LUT_DATA;
-+		uint32_t i = 0;
-+		const struct pwl_result_data *rgb =
-+				params->rgb_resulted;
-+
-+		while (i != params->hw_points_num) {
-+			dm_write_reg(opp110->base.ctx, addr, rgb->red_reg);
-+			dm_write_reg(opp110->base.ctx, addr, rgb->green_reg);
-+			dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
-+
-+			dm_write_reg(opp110->base.ctx, addr,
-+				rgb->delta_red_reg);
-+			dm_write_reg(opp110->base.ctx, addr,
-+				rgb->delta_green_reg);
-+			dm_write_reg(opp110->base.ctx, addr,
-+				rgb->delta_blue_reg);
-+
-+			++rgb;
-+			++i;
-+		}
-+	}
-+}
-+
-+bool dce110_opp_set_regamma_v(
-+	struct output_pixel_processor *opp,
-+	const struct regamma_params *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	/* Setup regions */
-+	regamma_config_regions_and_segments(opp110, params);
-+
-+	set_bypass_input_gamma(opp110);
-+
-+	/* Power on gamma LUT memory */
-+	power_on_lut(opp, true, false, true);
-+
-+	/* Program PWL */
-+	program_pwl(opp110, params);
-+
-+	/* program regamma config */
-+	configure_regamma_mode(opp110, 1);
-+
-+	/* Power return to auto back */
-+	power_on_lut(opp, false, false, true);
-+
-+	return true;
-+}
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-new file mode 100644
-index 0000000..9764940
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-@@ -0,0 +1,75 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_opp.h"
-+#include "dce110_opp_v.h"
-+
-+#include "gamma_types.h"
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+struct opp_funcs funcs = {
-+		.opp_set_regamma = dce110_opp_set_regamma_v,
-+
-+		.opp_set_csc_default = dce110_opp_v_set_csc_default,
-+
-+		.opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
-+
-+		.opp_program_bit_depth_reduction =
-+				dce110_opp_program_bit_depth_reduction,
-+		.opp_program_clamping_and_pixel_encoding =
-+				dce110_opp_program_clamping_and_pixel_encoding,
-+
-+		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-+		.opp_destroy = dce110_opp_destroy,
-+};
-+
-+bool dce110_opp_v_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offsets)
-+{
-+	opp110->base.funcs = &funcs;
-+
-+	opp110->base.ctx = ctx;
-+
-+	opp110->base.inst = inst;
-+
-+	opp110->offsets = *offsets;
-+
-+	return true;
-+}
-+
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-new file mode 100644
-index 0000000..56365aa
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -0,0 +1,55 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_OPP_DCE110_V_H__
-+#define __DC_OPP_DCE110_V_H__
-+
-+#include "dc_types.h"
-+#include "inc/opp.h"
-+#include "core_types.h"
-+
-+#include "gamma_types.h" /* decprecated */
-+
-+struct gamma_parameters;
-+
-+bool dce110_opp_v_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offsets);
-+
-+/* underlay callbacks */
-+void dce110_opp_v_set_csc_default(
-+	struct output_pixel_processor *opp,
-+	const struct default_adjustment *default_adjust);
-+
-+void dce110_opp_v_set_csc_adjustment(
-+	struct output_pixel_processor *opp,
-+	const struct grph_csc_adjustment *adjust);
-+
-+bool dce110_opp_set_regamma_v(
-+	struct output_pixel_processor *opp,
-+	const struct regamma_params *params);
-+
-+
-+#endif /* __DC_OPP_DCE110_V_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 42e7306..c65f401 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1229,7 +1229,7 @@ audio_create_fail:
- controller_create_fail:
- 	for (i = 0; i < pool->pipe_count; i++) {
- 		if (pool->opps[i] != NULL)
--			dce110_opp_destroy(&pool->opps[i]);
-+			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
- 
- 		if (pool->transforms[i] != NULL)
- 			dce110_transform_destroy(&pool->transforms[i]);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 307184a..74dbea9 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -29,6 +29,8 @@
- #include "dc_types.h"
- #include "grph_object_id.h"
- #include "grph_csc_types.h"
-+#include "video_csc_types.h"
-+#include "hw_sequencer_types.h"
- 
- struct fixed31_32;
- struct gamma_parameters;
-@@ -303,6 +305,19 @@ struct opp_funcs {
- 		enum color_space color_sp,
- 		enum dc_color_depth color_dpth,
- 		enum signal_type signal);
-+
-+	/* underlay related */
-+	void (*opp_get_underlay_adjustment_range)(
-+			struct output_pixel_processor *opp,
-+			enum ovl_csc_adjust_item overlay_adjust_item,
-+			struct hw_adjustment_range *range);
-+
-+	void (*opp_set_ovl_csc_adjustment)(
-+			struct output_pixel_processor *opp,
-+			const struct ovl_csc_adjustment *adjust,
-+			enum color_space c_space);
-+
-+	void (*opp_destroy)(struct output_pixel_processor **opp);
- };
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0792-drm-amd-dal-Instantiate-Underlay-version-of-Memory-I.patch b/common/recipes-kernel/linux/files/0792-drm-amd-dal-Instantiate-Underlay-version-of-Memory-I.patch
deleted file mode 100644
index 2da4f723..00000000
--- a/common/recipes-kernel/linux/files/0792-drm-amd-dal-Instantiate-Underlay-version-of-Memory-I.patch
+++ /dev/null
@@ -1,1041 +0,0 @@
-From 3534a935d81f0487de2dc4f45453578c1d224dde Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 11 Feb 2016 14:01:39 -0500
-Subject: [PATCH 0792/1110] drm/amd/dal: Instantiate Underlay version of Memory
- Input (surface).
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |   1 +
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |   3 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 899 +++++++++++++++++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h |  84 ++
- 4 files changed, 986 insertions(+), 1 deletion(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index efa592f..dcf44d4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -36,6 +36,7 @@
- #include "dce110/dce110_timing_generator.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_mem_input.h"
-+#include "dce110/dce110_mem_input_v.h"
- #include "dce110/dce110_ipp.h"
- #include "dce110/dce110_transform.h"
- #include "dce110/dce110_stream_encoder.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-index deae715..404b2bf 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -9,7 +9,8 @@ dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
- dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
- dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
- dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o \
--dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o
-+dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \
-+dce110_mem_input_v.o
- 
- AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-new file mode 100644
-index 0000000..8a211d8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-@@ -0,0 +1,899 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+/* TODO: this needs to be looked at, used by Stella's workaround*/
-+#include "gmc/gmc_8_2_d.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+
-+#include "include/logger_interface.h"
-+#include "adapter_service_interface.h"
-+#include "inc/bandwidth_calcs.h"
-+
-+#include "dce110_mem_input.h"
-+
-+
-+#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
-+/*#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)*/
-+/*#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)*/
-+
-+
-+static const struct dce110_mem_input_reg_offsets dce110_mi_v_reg_offsets[] = {
-+	{
-+		.dcp = 0,
-+		.dmif = 0,
-+		.pipe = 0,
-+	}
-+};
-+
-+static void set_flip_control(
-+	struct dce110_mem_input *mem_input110,
-+	bool immediate)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmUNP_FLIP_CONTROL));
-+
-+	set_reg_field_value(value, 1,
-+			UNP_FLIP_CONTROL,
-+			GRPH_SURFACE_UPDATE_PENDING_MODE);
-+
-+	dm_write_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmUNP_FLIP_CONTROL),
-+			value);
-+}
-+
-+/* chroma part */
-+static void program_pri_addr_c(
-+	struct dce110_mem_input *mem_input110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t value = 0;
-+	uint32_t temp = 0;
-+	/*high register MUST be programmed first*/
-+	temp = address.high_part &
-+UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C),
-+		value);
-+
-+	temp = 0;
-+	value = 0;
-+	temp = address.low_part >>
-+	UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_C);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C),
-+		value);
-+}
-+
-+/* luma part */
-+static void program_pri_addr_l(
-+	struct dce110_mem_input *mem_input110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t value = 0;
-+	uint32_t temp = 0;
-+
-+	/*high register MUST be programmed first*/
-+	temp = address.high_part &
-+UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L),
-+		value);
-+
-+	temp = 0;
-+	value = 0;
-+	temp = address.low_part >>
-+	UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_L);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L),
-+		value);
-+}
-+
-+static void program_addr(
-+	struct dce110_mem_input *mem_input110,
-+	const struct dc_plane_address *addr)
-+{
-+	switch (addr->type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		program_pri_addr_l(
-+			mem_input110,
-+			addr->grph.addr);
-+		break;
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
-+		program_pri_addr_l(
-+			mem_input110,
-+			addr->video_progressive.luma_addr);
-+		program_pri_addr_c(
-+			mem_input110,
-+			addr->video_progressive.chroma_addr);
-+		break;
-+	default:
-+		/* not supported */
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+static void enable(struct dce110_mem_input *mem_input110)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_ENABLE));
-+	set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE);
-+	dm_write_reg(mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_ENABLE),
-+		value);
-+}
-+
-+static void program_tiling(
-+	struct dce110_mem_input *mem_input110,
-+	const struct dc_tiling_info *info,
-+	const enum surface_pixel_format pixel_format)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(
-+			mem_input110->base.ctx,
-+			DCP_REG(mmUNP_GRPH_CONTROL));
-+
-+	set_reg_field_value(value, info->num_banks,
-+		UNP_GRPH_CONTROL, GRPH_NUM_BANKS);
-+
-+	set_reg_field_value(value, info->bank_width,
-+		UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L);
-+
-+	set_reg_field_value(value, info->bank_height,
-+		UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L);
-+
-+	set_reg_field_value(value, info->tile_aspect,
-+		UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L);
-+
-+	set_reg_field_value(value, info->tile_split,
-+		UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L);
-+
-+	set_reg_field_value(value, info->tile_mode,
-+		UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L);
-+
-+	set_reg_field_value(value, info->pipe_config,
-+		UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG);
-+
-+	set_reg_field_value(value, info->array_mode,
-+		UNP_GRPH_CONTROL, GRPH_ARRAY_MODE);
-+
-+	set_reg_field_value(value, 1,
-+		UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
-+
-+	set_reg_field_value(value, 0,
-+		UNP_GRPH_CONTROL, GRPH_Z);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_CONTROL),
-+		value);
-+}
-+
-+static void program_size_and_rotation(
-+	struct dce110_mem_input *mem_input110,
-+	enum dc_rotation_angle rotation,
-+	const union plane_size *plane_size)
-+{
-+	uint32_t value = 0;
-+	union plane_size local_size = *plane_size;
-+
-+	if (rotation == ROTATION_ANGLE_90 ||
-+		rotation == ROTATION_ANGLE_270) {
-+
-+		uint32_t swap;
-+		swap = local_size.video.luma_size.x;
-+		local_size.video.luma_size.x =
-+			local_size.video.luma_size.y;
-+		local_size.video.luma_size.y  = swap;
-+
-+		swap = local_size.video.luma_size.width;
-+		local_size.video.luma_size.width =
-+			local_size.video.luma_size.height;
-+		local_size.video.luma_size.height = swap;
-+
-+		swap = local_size.video.chroma_size.x;
-+		local_size.video.chroma_size.x =
-+			local_size.video.chroma_size.y;
-+		local_size.video.chroma_size.y  = swap;
-+
-+		swap = local_size.video.chroma_size.width;
-+		local_size.video.chroma_size.width =
-+			local_size.video.chroma_size.height;
-+		local_size.video.chroma_size.height = swap;
-+	}
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.luma_pitch,
-+			UNP_GRPH_PITCH_L, GRPH_PITCH_L);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_PITCH_L),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.chroma_pitch,
-+			UNP_GRPH_PITCH_C, GRPH_PITCH_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_PITCH_C),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_X_START_L, GRPH_X_START_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_X_START_L),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_X_START_C, GRPH_X_START_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_X_START_C),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_Y_START_L, GRPH_Y_START_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_Y_START_L),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_Y_START_C, GRPH_Y_START_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_Y_START_C),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.luma_size.x +
-+			local_size.video.luma_size.width,
-+			UNP_GRPH_X_END_L, GRPH_X_END_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_X_END_L),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.chroma_size.x +
-+			local_size.video.chroma_size.width,
-+			UNP_GRPH_X_END_C, GRPH_X_END_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_X_END_C),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.luma_size.y +
-+			local_size.video.luma_size.height,
-+			UNP_GRPH_Y_END_L, GRPH_Y_END_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_Y_END_L),
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.chroma_size.y +
-+			local_size.video.chroma_size.height,
-+			UNP_GRPH_Y_END_C, GRPH_Y_END_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_GRPH_Y_END_C),
-+		value);
-+
-+	value = 0;
-+	switch (rotation) {
-+	case ROTATION_ANGLE_90:
-+		set_reg_field_value(value, 3,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	case ROTATION_ANGLE_180:
-+		set_reg_field_value(value, 2,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	case ROTATION_ANGLE_270:
-+		set_reg_field_value(value, 1,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	}
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		DCP_REG(mmUNP_HW_ROTATION),
-+		value);
-+}
-+
-+static void program_pixel_format(
-+	struct dce110_mem_input *mem_input110,
-+	enum surface_pixel_format format)
-+{
-+	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN ||
-+			format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+		uint32_t value;
-+		uint8_t grph_depth;
-+		uint8_t grph_format;
-+
-+		value =	dm_read_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_CONTROL));
-+
-+		switch (format) {
-+		case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-+			grph_depth = 0;
-+			grph_format = 0;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+			grph_depth = 1;
-+			grph_format = 1;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+		case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
-+			grph_depth = 2;
-+			grph_format = 0;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+			grph_depth = 2;
-+			grph_format = 1;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+			grph_depth = 3;
-+			grph_format = 0;
-+			break;
-+		default:
-+			grph_depth = 2;
-+			grph_format = 0;
-+			break;
-+		}
-+
-+		set_reg_field_value(
-+				value,
-+				grph_depth,
-+				UNP_GRPH_CONTROL,
-+				GRPH_DEPTH);
-+		set_reg_field_value(
-+				value,
-+				grph_format,
-+				UNP_GRPH_CONTROL,
-+				GRPH_FORMAT);
-+
-+		dm_write_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_CONTROL),
-+				value);
-+
-+		value =	dm_read_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_CONTROL_EXP));
-+
-+		/* VIDEO FORMAT 0 */
-+		set_reg_field_value(
-+				value,
-+				0,
-+				UNP_GRPH_CONTROL_EXP,
-+				VIDEO_FORMAT);
-+		dm_write_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_CONTROL_EXP),
-+				value);
-+
-+	} else {
-+		/* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */
-+		uint32_t value;
-+		uint8_t video_format;
-+
-+		value =	dm_read_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_CONTROL_EXP));
-+
-+		switch (format) {
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+			video_format = 2;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+			video_format = 3;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_VIDEO_422_YCb:
-+			video_format = 4;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_VIDEO_422_YCr:
-+			video_format = 5;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_VIDEO_422_CbY:
-+			video_format = 6;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_VIDEO_422_CrY:
-+			video_format = 7;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		set_reg_field_value(
-+			value,
-+			video_format,
-+			UNP_GRPH_CONTROL_EXP,
-+			VIDEO_FORMAT);
-+
-+		dm_write_reg(
-+				mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_CONTROL_EXP),
-+				value);
-+	}
-+}
-+
-+static void wait_for_no_surface_update_pending(
-+				struct dce110_mem_input *mem_input110)
-+{
-+	uint32_t value;
-+
-+	do  {
-+		value = dm_read_reg(mem_input110->base.ctx,
-+				DCP_REG(mmUNP_GRPH_UPDATE));
-+
-+	} while (get_reg_field_value(value, UNP_GRPH_UPDATE,
-+			GRPH_SURFACE_UPDATE_PENDING));
-+}
-+
-+bool dce110_mem_input_v_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate)
-+{
-+	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-+
-+	set_flip_control(mem_input110, flip_immediate);
-+	program_addr(mem_input110,
-+		address);
-+
-+	if (flip_immediate)
-+		wait_for_no_surface_update_pending(mem_input110);
-+
-+	return true;
-+}
-+
-+bool dce110_mem_input_v_program_surface_config(
-+	struct mem_input *mem_input,
-+	enum surface_pixel_format format,
-+	struct dc_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation)
-+{
-+	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-+
-+	enable(mem_input110);
-+	program_tiling(mem_input110, tiling_info, format);
-+	program_size_and_rotation(mem_input110, rotation, plane_size);
-+	program_pixel_format(mem_input110, format);
-+
-+	return true;
-+}
-+
-+static void program_urgency_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t urgency_addr,
-+	const uint32_t wm_addr,
-+	struct bw_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	/* register value */
-+	uint32_t urgency_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			1,
-+			DPGV0_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		marks_low.a_mark,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			2,
-+			DPGV0_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(urgency_cntl,
-+		marks_low.b_mark,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+}
-+
-+static void program_urgency_watermark_l(
-+	const struct dc_context *ctx,
-+	struct bw_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark(
-+		ctx,
-+		mmDPGV0_PIPE_URGENCY_CONTROL,
-+		mmDPGV0_WATERMARK_MASK_CONTROL,
-+		marks_low,
-+		total_dest_line_time_ns);
-+}
-+
-+static void program_urgency_watermark_c(
-+	const struct dc_context *ctx,
-+	struct bw_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark(
-+		ctx,
-+		mmDPGV1_PIPE_URGENCY_CONTROL,
-+		mmDPGV1_WATERMARK_MASK_CONTROL,
-+		marks_low,
-+		total_dest_line_time_ns);
-+}
-+
-+static void program_stutter_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t stutter_addr,
-+	const uint32_t wm_addr,
-+	struct bw_watermarks marks)
-+{
-+	/* register value */
-+	uint32_t stutter_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		1,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set A*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.a_mark,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		2,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set B*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.b_mark,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+}
-+
-+static void program_stutter_watermark_l(
-+	const struct dc_context *ctx,
-+	struct bw_watermarks marks)
-+{
-+	program_stutter_watermark(ctx,
-+			mmDPGV0_PIPE_STUTTER_CONTROL,
-+			mmDPGV0_WATERMARK_MASK_CONTROL,
-+			marks);
-+}
-+
-+static void program_stutter_watermark_c(
-+	const struct dc_context *ctx,
-+	struct bw_watermarks marks)
-+{
-+	program_stutter_watermark(ctx,
-+			mmDPGV1_PIPE_STUTTER_CONTROL,
-+			mmDPGV1_WATERMARK_MASK_CONTROL,
-+			marks);
-+}
-+
-+static void program_nbp_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t wm_mask_ctrl_addr,
-+	const uint32_t nbp_pstate_ctrl_addr,
-+	struct bw_watermarks marks)
-+{
-+	uint32_t value;
-+
-+	/* Write mask to enable reading/writing of watermark set A */
-+
-+	value = dm_read_reg(ctx, wm_mask_ctrl_addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_mask_ctrl_addr, value);
-+
-+
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+
-+	/* Write watermark set A */
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		marks.a_mark,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+
-+	/* Write mask to enable reading/writing of watermark set B */
-+	value = dm_read_reg(ctx, wm_mask_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_mask_ctrl_addr, value);
-+
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+
-+	/* Write watermark set B */
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		marks.b_mark,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+}
-+
-+static void program_nbp_watermark_l(
-+	const struct dc_context *ctx,
-+	struct bw_watermarks marks)
-+{
-+	program_nbp_watermark(ctx,
-+			mmDPGV0_WATERMARK_MASK_CONTROL,
-+			mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+			marks);
-+}
-+
-+static void program_nbp_watermark_c(
-+	const struct dc_context *ctx,
-+	struct bw_watermarks marks)
-+{
-+	program_nbp_watermark(ctx,
-+			mmDPGV1_WATERMARK_MASK_CONTROL,
-+			mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+			marks);
-+}
-+
-+void dce110_mem_input_v_program_display_marks(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks nbp,
-+	struct bw_watermarks stutter,
-+	struct bw_watermarks urgent,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark_l(
-+		mem_input->ctx,
-+		urgent,
-+		total_dest_line_time_ns);
-+
-+	program_urgency_watermark_c(
-+		mem_input->ctx,
-+		urgent,
-+		total_dest_line_time_ns);
-+
-+	program_nbp_watermark_l(
-+		mem_input->ctx,
-+		nbp);
-+
-+	program_nbp_watermark_c(
-+		mem_input->ctx,
-+		nbp);
-+
-+	program_stutter_watermark_l(
-+		mem_input->ctx,
-+		stutter);
-+
-+	program_stutter_watermark_c(
-+		mem_input->ctx,
-+		stutter);
-+}
-+
-+
-+void dce110_allocate_mem_input_v(
-+	struct mem_input *mi,
-+	uint32_t h_total,/* for current stream */
-+	uint32_t v_total,/* for current stream */
-+	uint32_t pix_clk_khz,/* for current stream */
-+	uint32_t total_stream_num)
-+{
-+}
-+
-+void dce110_free_mem_input_v(
-+	struct mem_input *mi,
-+	uint32_t total_stream_num)
-+{
-+}
-+
-+static struct mem_input_funcs dce110_mem_input_v_funcs = {
-+	.mem_input_program_display_marks =
-+			dce110_mem_input_v_program_display_marks,
-+	.allocate_mem_input = dce110_allocate_mem_input_v,
-+	.free_mem_input = dce110_free_mem_input_v,
-+	.mem_input_program_surface_flip_and_addr =
-+			dce110_mem_input_v_program_surface_flip_and_addr,
-+	.mem_input_program_surface_config =
-+			dce110_mem_input_v_program_surface_config,
-+};
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce110_mem_input_v_construct(
-+	struct dce110_mem_input *mem_input110,
-+	struct dc_context *ctx)
-+{
-+	mem_input110->base.funcs = &dce110_mem_input_v_funcs;
-+	mem_input110->base.ctx = ctx;
-+
-+	mem_input110->base.inst = 0;
-+
-+	mem_input110->offsets = dce110_mi_v_reg_offsets[0];
-+
-+	mem_input110->supported_stutter_mode = 0;
-+	dal_adapter_service_get_feature_value(FEATURE_STUTTER_MODE,
-+			&(mem_input110->supported_stutter_mode),
-+			sizeof(mem_input110->supported_stutter_mode));
-+
-+	return true;
-+}
-+
-+#if 0
-+void dce110_mem_input_v_destroy(struct mem_input **mem_input)
-+{
-+	dm_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
-+	*mem_input = NULL;
-+}
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-new file mode 100644
-index 0000000..529aace
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-@@ -0,0 +1,84 @@
-+/* Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MEM_INPUT_V_DCE110_H__
-+#define __DC_MEM_INPUT_V_DCE110_H__
-+
-+#include "inc/mem_input.h"
-+#include "dce110_mem_input.h"
-+
-+bool dce110_mem_input_v_construct(
-+	struct dce110_mem_input *mem_input110,
-+	struct dc_context *ctx);
-+
-+/*
-+ * This function will program nbp stutter and urgency watermarks to minimum
-+ * allowable values
-+ */
-+void dce110_mem_input_v_program_display_marks(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks nbp,
-+	struct bw_watermarks stutter,
-+	struct bw_watermarks urgent,
-+	uint32_t total_dest_line_time_ns);
-+
-+/*
-+ * This function will allocate a dmif buffer and program required
-+ * pixel duration for pipe
-+ */
-+void dce110_allocate_mem_v_input(
-+	struct mem_input *mem_input,
-+	uint32_t h_total,/* for current stream */
-+	uint32_t v_total,/* for current stream */
-+	uint32_t pix_clk_khz,/* for current stream */
-+	uint32_t total_stream_num);
-+
-+/*
-+ * This function will deallocate a dmif buffer from pipe
-+ */
-+void dce110_free_mem_v_input(
-+	struct mem_input *mem_input,
-+	uint32_t total_stream_num);
-+
-+/*
-+ * This function programs hsync/vsync mode and surface address
-+ */
-+bool dce110_mem_input_v_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate);
-+
-+/*
-+ * This function will program surface tiling, size, rotation and pixel format
-+ * to corresponding dcp registers.
-+ */
-+bool  dce110_mem_input_v_program_surface_config(
-+	struct mem_input *mem_input,
-+	enum surface_pixel_format format,
-+	struct dc_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation);
-+
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0793-drm-amd-dal-implement-ipp-opp-bypass.patch b/common/recipes-kernel/linux/files/0793-drm-amd-dal-implement-ipp-opp-bypass.patch
deleted file mode 100644
index b601cf49..00000000
--- a/common/recipes-kernel/linux/files/0793-drm-amd-dal-implement-ipp-opp-bypass.patch
+++ /dev/null
@@ -1,265 +0,0 @@
-From 05558c0014a8623fa80476ead752aa294d14513f Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 10 Feb 2016 14:29:59 -0500
-Subject: [PATCH 0793/1110] drm/amd/dal: implement ipp opp bypass.
-
-If gamma pointer in surface is null, it means
-no gamma setting needed, in that case, set regamma_control
-mode to bypass.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 16 +++++------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 15 +++++++----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  3 ++-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |  7 +++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 31 +++++++++++++---------
- .../drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               | 12 ++++-----
- 9 files changed, 49 insertions(+), 41 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index f00b5af..6b778d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -258,6 +258,7 @@ bool dc_commit_surfaces_to_target(
- 						DC_SURFACE_TO_CORE(dc_surface);
- 			struct pipe_ctx *pipe_ctx =
- 						&context->res_ctx.pipe_ctx[j];
-+			struct core_gamma *gamma = NULL;
- 
- 			if (pipe_ctx->surface !=
- 					DC_SURFACE_TO_CORE(new_surfaces[i]))
-@@ -279,15 +280,14 @@ bool dc_commit_surfaces_to_target(
- 						dc_surface->dst_rect.width,
- 						dc_surface->dst_rect.height);
- 
--			if (dc_surface->gamma_correction) {
--				struct core_gamma *gamma = DC_GAMMA_TO_CORE(
--						dc_surface->gamma_correction);
-+		if (surface->public.gamma_correction)
-+			gamma = DC_GAMMA_TO_CORE(
-+					surface->public.gamma_correction);
- 
--				dc->hwss.set_gamma_correction(
--							pipe_ctx->ipp,
--							pipe_ctx->opp,
--							gamma, surface);
--			}
-+		dc->hwss.set_gamma_correction(
-+				pipe_ctx->ipp,
-+				pipe_ctx->opp,
-+			gamma, surface);
- 
- 			dc->hwss.set_plane_config(dc, surface, pipe_ctx);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 70349a0..810f6d5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -525,11 +525,16 @@ static bool set_gamma_ramp(
- 
- 	ipp->funcs->ipp_program_prescale(ipp, prescale_params);
- 
--	ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_sRGB);
--
--	calculate_regamma_params(regamma_params, temp_params, ramp, surface);
--
--	opp->funcs->opp_set_regamma(opp, regamma_params);
-+	if (ramp) {
-+		calculate_regamma_params(regamma_params,
-+				temp_params, ramp, surface);
-+		opp->funcs->opp_program_regamma_pwl(opp, regamma_params);
-+		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_sRGB);
-+		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
-+	} else {
-+		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
-+		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
-+	}
- 
- 	opp->funcs->opp_power_on_regamma_lut(opp, false);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index 86bf8c0..c06cf38 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -49,7 +49,8 @@ struct opp_funcs funcs = {
- 		.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
- 		.opp_set_csc_default = dce110_opp_set_csc_default,
- 		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
--		.opp_set_regamma = dce110_opp_set_regamma,
-+		.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
-+		.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
- 		.opp_destroy = dce110_opp_destroy,
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index 3460e18..a19e744 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -107,13 +107,12 @@ void dce110_opp_power_on_regamma_lut(
- 	struct output_pixel_processor *opp,
- 	bool power_on);
- 
--bool dce110_opp_set_regamma(
-+bool dce110_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
- 	const struct regamma_params *params);
- 
--void dce110_opp_power_on_regamma_lut(
--	struct output_pixel_processor *opp,
--	bool power_on);
-+void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
-+		enum opp_regamma mode);
- 
- void dce110_opp_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index f7a4bc2..88803eb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -393,18 +393,6 @@ static void program_pwl(
- 		uint8_t max_tries = 10;
- 		uint8_t counter = 0;
- 
--		value = dm_read_reg(opp110->base.ctx,
--				DCP_REG(mmREGAMMA_CONTROL));
--
--		set_reg_field_value(
--			value,
--			3,
--			REGAMMA_CONTROL,
--			GRPH_REGAMMA_MODE);
--
--		dm_write_reg(opp110->base.ctx, DCP_REG(mmREGAMMA_CONTROL),
--				value);
--
- 		/* Power on LUT memory */
- 		value = dm_read_reg(opp110->base.ctx,
- 				DCFE_REG(mmDCFE_MEM_PWR_CTRL));
-@@ -495,7 +483,7 @@ static void program_pwl(
- }
- 
- 
--bool dce110_opp_set_regamma(
-+bool dce110_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
- 	const struct regamma_params *params)
- {
-@@ -533,3 +521,20 @@ void dce110_opp_power_on_regamma_lut(
- 
- 	dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
-+
-+void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
-+		enum opp_regamma mode)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	uint32_t value = dm_read_reg(opp110->base.ctx,
-+				DCP_REG(mmREGAMMA_CONTROL));
-+
-+	set_reg_field_value(
-+		value,
-+		mode,
-+		REGAMMA_CONTROL,
-+		GRPH_REGAMMA_MODE);
-+
-+	dm_write_reg(opp110->base.ctx, DCP_REG(mmREGAMMA_CONTROL),
-+			value);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-index 4f6cc9c..b9d7eda 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-@@ -491,7 +491,7 @@ static void program_pwl(struct dce110_opp *opp110,
- 	}
- }
- 
--bool dce110_opp_set_regamma_v(
-+bool dce110_opp_program_regamma_pwl_v(
- 	struct output_pixel_processor *opp,
- 	const struct regamma_params *params)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-index 9764940..367325f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-@@ -39,7 +39,7 @@
- /*****************************************/
- 
- struct opp_funcs funcs = {
--		.opp_set_regamma = dce110_opp_set_regamma_v,
-+		.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
- 
- 		.opp_set_csc_default = dce110_opp_v_set_csc_default,
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-index 56365aa..3f2ed4a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -47,7 +47,7 @@ void dce110_opp_v_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
- 	const struct grph_csc_adjustment *adjust);
- 
--bool dce110_opp_set_regamma_v(
-+bool dce110_opp_program_regamma_pwl_v(
- 	struct output_pixel_processor *opp,
- 	const struct regamma_params *params);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 74dbea9..4924874 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -36,7 +36,6 @@ struct fixed31_32;
- struct gamma_parameters;
- 
- /* TODO: Need cleanup */
--
- enum clamping_range {
- 	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
- 	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
-@@ -243,14 +242,11 @@ struct pwl_float_data {
- 	struct fixed31_32 b;
- };
- 
--
--/* TODO: Use when we redefine the OPP interface */
- enum opp_regamma {
- 	OPP_REGAMMA_BYPASS = 0,
- 	OPP_REGAMMA_SRGB,
- 	OPP_REGAMMA_3_6,
--	OPP_REGAMMA_PQ,
--	OPP_REGAMMA_PQ_INTERIM,
-+	OPP_REGAMMA_USER,
- };
- 
- struct output_pixel_processor {
-@@ -278,10 +274,13 @@ struct opp_funcs {
- 		struct output_pixel_processor *opp,
- 		bool power_on);
- 
--	bool (*opp_set_regamma)(
-+	bool (*opp_program_regamma_pwl)(
- 		struct output_pixel_processor *opp,
- 		const struct regamma_params *params);
- 
-+	void (*opp_set_regamma_mode)(struct output_pixel_processor *opp,
-+			enum opp_regamma mode);
-+
- 	void (*opp_set_csc_adjustment)(
- 		struct output_pixel_processor *opp,
- 		const struct grph_csc_adjustment *adjust);
-@@ -299,7 +298,6 @@ struct opp_funcs {
- 		struct output_pixel_processor *opp,
- 		const struct clamping_and_pixel_encoding_params *params);
- 
--
- 	void (*opp_set_dyn_expansion)(
- 		struct output_pixel_processor *opp,
- 		enum color_space color_sp,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0794-drm-amd-dal-Correctly-interpret-rotation-as-bit-set.patch b/common/recipes-kernel/linux/files/0794-drm-amd-dal-Correctly-interpret-rotation-as-bit-set.patch
deleted file mode 100644
index 9151f573..00000000
--- a/common/recipes-kernel/linux/files/0794-drm-amd-dal-Correctly-interpret-rotation-as-bit-set.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 5c8e0a6508d058c945177effc67645bac34a9248 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 11 Feb 2016 11:48:46 -0500
-Subject: [PATCH 0794/1110] drm/amd/dal: Correctly interpret rotation as bit
- set
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 39490bf..7468990 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -366,16 +366,16 @@ static bool fill_rects_from_plane_state(
- 	surface->clip_rect = surface->dst_rect;
- 
- 	switch (state->rotation) {
--	case DRM_ROTATE_0:
-+	case BIT(DRM_ROTATE_0):
- 		surface->rotation = ROTATION_ANGLE_0;
- 		break;
--	case DRM_ROTATE_90:
-+	case BIT(DRM_ROTATE_90):
- 		surface->rotation = ROTATION_ANGLE_90;
- 		break;
--	case DRM_ROTATE_180:
-+	case BIT(DRM_ROTATE_180):
- 		surface->rotation = ROTATION_ANGLE_180;
- 		break;
--	case DRM_ROTATE_270:
-+	case BIT(DRM_ROTATE_270):
- 		surface->rotation = ROTATION_ANGLE_270;
- 		break;
- 	default:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0795-drm-amd-dal-fix-flip-clean-up-state.patch b/common/recipes-kernel/linux/files/0795-drm-amd-dal-fix-flip-clean-up-state.patch
deleted file mode 100644
index 73a072cf..00000000
--- a/common/recipes-kernel/linux/files/0795-drm-amd-dal-fix-flip-clean-up-state.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 36331681b029511df4aab4f24bed95fe12087a7b Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 6 Jan 2016 18:24:48 +0800
-Subject: [PATCH 0795/1110] drm/amd/dal: fix flip clean-up state
-
-Get on par with buffer management changes made in base driver
-(see fba4c336 base driver commit for reference).
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c       | 10 ++++------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 17 +++++++++++------
- 2 files changed, 15 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 6329658..0061b8c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1330,7 +1330,7 @@ void amdgpu_dm_flip_cleanup(
- 		} else
- 			DRM_ERROR("failed to reserve buffer after flip\n");
- 
--		drm_gem_object_unreference_unlocked(&works->old_rbo->gem_base);
-+		amdgpu_bo_unref(&works->old_rbo);
- 		kfree(works->shared);
- 		kfree(works);
- 	}
-@@ -1380,13 +1380,11 @@ static void dm_page_flip(struct amdgpu_device *adev,
- 	target = acrtc->target;
- 
- 	/*
--	 * Received a page flip call after the display has been reset. Make sure
--	 * we return the buffers.
-+	 * Received a page flip call after the display has been reset.
-+	 * Just return in this case. Everything should be clean-up on reset.
- 	 */
--	if (!target) {
--		amdgpu_dm_flip_cleanup(adev, acrtc);
-+	if (!target)
- 		return;
--	}
- 
- 	addr.address.grph.addr.low_part = lower_32_bits(crtc_base);
- 	addr.address.grph.addr.high_part = upper_32_bits(crtc_base);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 7468990..df7afc9 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1970,22 +1970,27 @@ static void manage_dm_interrupts(
- 	struct amdgpu_crtc *acrtc,
- 	bool enable)
- {
-+	/*
-+	 * this is not correct translation but will work as soon as VBLANK
-+	 * constant is the same as PFLIP
-+	 */
-+	int irq_type =
-+		amdgpu_crtc_idx_to_irq_type(
-+			adev,
-+			acrtc->crtc_id);
-+
- 	if (enable) {
- 		drm_crtc_vblank_on(&acrtc->base);
- 		amdgpu_irq_get(
- 			adev,
- 			&adev->pageflip_irq,
--			amdgpu_crtc_idx_to_irq_type(
--				adev,
--				acrtc->crtc_id));
-+			irq_type);
- 	} else {
- 		unsigned long flags;
- 		amdgpu_irq_put(
- 			adev,
- 			&adev->pageflip_irq,
--			amdgpu_crtc_idx_to_irq_type(
--				adev,
--				acrtc->crtc_id));
-+			irq_type);
- 		drm_crtc_vblank_off(&acrtc->base);
- 
- 		/*
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0796-drm-amd-dal-register-eDP-short-pulse-interrupt.patch b/common/recipes-kernel/linux/files/0796-drm-amd-dal-register-eDP-short-pulse-interrupt.patch
deleted file mode 100644
index dffda030..00000000
--- a/common/recipes-kernel/linux/files/0796-drm-amd-dal-register-eDP-short-pulse-interrupt.patch
+++ /dev/null
@@ -1,167 +0,0 @@
-From d96fb309addb53fbde1efb54dc233c6ac753d4d1 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 4 Jan 2016 14:46:01 +0800
-Subject: [PATCH 0796/1110] drm/amd/dal: register eDP short pulse interrupt
-
-Registration of short pulse interrupt was missed for eDP
-case, because of guard for HPD registration for embedded
-panels.
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c     | 12 ++++----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 15 +++-------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c         | 36 ++++++++++-------------
- 3 files changed, 27 insertions(+), 36 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 0061b8c..7a7f69e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -959,12 +959,14 @@ static void register_hpd_handlers(struct amdgpu_device *adev)
- 		aconnector = to_amdgpu_connector(connector);
- 		dc_link = aconnector->dc_link;
- 
--		int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
--		int_params.irq_source = dc_link->irq_source_hpd;
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
-+			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
-+			int_params.irq_source = dc_link->irq_source_hpd;
- 
--		amdgpu_dm_irq_register_interrupt(adev, &int_params,
--				handle_hpd_irq,
--				(void *) aconnector);
-+			amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+					handle_hpd_irq,
-+					(void *) aconnector);
-+		}
- 
- 		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index 2ba79ab..d04ed18 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -770,19 +770,12 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
- 
- 		const struct dc_link *dc_link = amdgpu_connector->dc_link;
- 
--		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
--			connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
--			/* don't try to enable hpd on eDP or LVDS avoid breaking
--			 * the aux dp channel on imac and help (but not
--			 * completely fix)
--			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
--			 * also avoid interrupt storms during dpms.
--			 */
--			continue;
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
-+			dc_interrupt_set(adev->dm.dc,
-+					dc_link->irq_source_hpd,
-+					true);
- 		}
- 
--		dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, true);
--
- 		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
- 			dc_interrupt_set(adev->dm.dc,
- 					dc_link->irq_source_hpd_rx,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 5fd5800..d9b76f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -885,7 +885,6 @@ static enum transmitter translate_encoder_to_transmitter(
- 	}
- }
- 
--
- static bool construct(
- 	struct core_link *link,
- 	const struct link_init_data *init_params)
-@@ -898,6 +897,9 @@ static bool construct(
- 	struct encoder_init_data enc_init_data = { 0 };
- 	struct integrated_info info = {{{ 0 }}};
- 
-+	link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID;
-+	link->public.irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
-+
- 	link->dc = init_params->dc;
- 	link->adapter_srv = as;
- 	link->ctx = dc_ctx;
-@@ -913,9 +915,15 @@ static bool construct(
- 		goto create_fail;
- 	}
- 
-+	hpd_gpio = dal_adapter_service_obtain_hpd_irq(as, link->link_id);
-+
-+	if (hpd_gpio != NULL)
-+		link->public.irq_source_hpd = dal_irq_get_source(hpd_gpio);
-+
- 	switch (link->link_id.id) {
- 	case CONNECTOR_ID_HDMI_TYPE_A:
- 		link->public.connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+
- 		break;
- 	case CONNECTOR_ID_SINGLE_LINK_DVID:
- 	case CONNECTOR_ID_SINGLE_LINK_DVII:
-@@ -927,29 +935,19 @@ static bool construct(
- 		break;
- 	case CONNECTOR_ID_DISPLAY_PORT:
- 		link->public.connector_signal =	SIGNAL_TYPE_DISPLAY_PORT;
--		hpd_gpio = dal_adapter_service_obtain_hpd_irq(
--					as,
--					link->link_id);
- 
--		if (hpd_gpio != NULL) {
-+		if (hpd_gpio != NULL)
- 			link->public.irq_source_hpd_rx =
- 					dal_irq_get_rx_source(hpd_gpio);
--			dal_adapter_service_release_irq(
--					as, hpd_gpio);
--		}
- 
- 		break;
- 	case CONNECTOR_ID_EDP:
- 		link->public.connector_signal = SIGNAL_TYPE_EDP;
--		hpd_gpio = dal_adapter_service_obtain_hpd_irq(
--					as,
--					link->link_id);
- 
- 		if (hpd_gpio != NULL) {
-+			link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID;
- 			link->public.irq_source_hpd_rx =
- 					dal_irq_get_rx_source(hpd_gpio);
--			dal_adapter_service_release_irq(
--					as, hpd_gpio);
- 		}
- 		break;
- 	default:
-@@ -959,19 +957,17 @@ static bool construct(
- 		goto create_fail;
- 	}
- 
-+	if (hpd_gpio != NULL) {
-+		dal_adapter_service_release_irq(
-+			as, hpd_gpio);
-+	}
-+
- 	/* TODO: #DAL3 Implement id to str function.*/
- 	LINK_INFO("Connector[%d] description:"
- 			"signal %d\n",
- 			init_params->connector_index,
- 			link->public.connector_signal);
- 
--	hpd_gpio = dal_adapter_service_obtain_hpd_irq(as, link->link_id);
--
--	if (hpd_gpio != NULL) {
--		link->public.irq_source_hpd = dal_irq_get_source(hpd_gpio);
--		dal_adapter_service_release_irq(as, hpd_gpio);
--	}
--
- 	ddc_service_init_data.as = as;
- 	ddc_service_init_data.ctx = link->ctx;
- 	ddc_service_init_data.id = link->link_id;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0797-drm-amd-dal-add-HIGH3-rates-to-fallback-table.patch b/common/recipes-kernel/linux/files/0797-drm-amd-dal-add-HIGH3-rates-to-fallback-table.patch
deleted file mode 100644
index 17702301..00000000
--- a/common/recipes-kernel/linux/files/0797-drm-amd-dal-add-HIGH3-rates-to-fallback-table.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 2064c076d525f0cddd6d44d817329ea4ec8fbe4f Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 11 Feb 2016 13:30:39 -0500
-Subject: [PATCH 0797/1110] drm/amd/dal: add HIGH3 rates to fallback table
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 1cf7ca2..2a5fee6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -31,18 +31,24 @@ enum {
- };
- 
- static const struct dc_link_settings link_training_fallback_table[] = {
-+/* 4320 Mbytes/sec*/
-+{ LANE_COUNT_FOUR, LINK_RATE_HIGH3, LINK_SPREAD_DISABLED },
- /* 2160 Mbytes/sec*/
- { LANE_COUNT_FOUR, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
- /* 1080 Mbytes/sec*/
- { LANE_COUNT_FOUR, LINK_RATE_HIGH, LINK_SPREAD_DISABLED },
- /* 648 Mbytes/sec*/
- { LANE_COUNT_FOUR, LINK_RATE_LOW, LINK_SPREAD_DISABLED },
-+/* 2160 Mbytes/sec*/
-+{ LANE_COUNT_TWO, LINK_RATE_HIGH3, LINK_SPREAD_DISABLED },
- /* 1080 Mbytes/sec*/
- { LANE_COUNT_TWO, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
- /* 540 Mbytes/sec*/
- { LANE_COUNT_TWO, LINK_RATE_HIGH, LINK_SPREAD_DISABLED },
- /* 324 Mbytes/sec*/
- { LANE_COUNT_TWO, LINK_RATE_LOW, LINK_SPREAD_DISABLED },
-+/* 1080 Mbytes/sec*/
-+{ LANE_COUNT_ONE, LINK_RATE_HIGH3, LINK_SPREAD_DISABLED },
- /* 540 Mbytes/sec*/
- { LANE_COUNT_ONE, LINK_RATE_HIGH2, LINK_SPREAD_DISABLED },
- /* 270 Mbytes/sec*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0798-drm-amd-dal-return-link-init-in-surface-status.patch b/common/recipes-kernel/linux/files/0798-drm-amd-dal-return-link-init-in-surface-status.patch
deleted file mode 100644
index 18d3e4c5..00000000
--- a/common/recipes-kernel/linux/files/0798-drm-amd-dal-return-link-init-in-surface-status.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 3ca4be4fb118e496012e25a331671c98dadd47fa Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 12 Feb 2016 09:31:29 -0500
-Subject: [PATCH 0798/1110] drm/amd/dal: return link init in surface status
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index d9b76f6..8203432 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1624,6 +1624,8 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- 
- 	dc->hwss.enable_stream(pipe_ctx);
- 
-+	pipe_ctx->stream->status.link = &pipe_ctx->stream->sink->link->public;
-+
- 	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		allocate_mst_payload(pipe_ctx);
- }
-@@ -1638,6 +1640,8 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
- 
- 	dc->hwss.disable_stream(pipe_ctx);
- 
-+	pipe_ctx->stream->status.link = NULL;
-+
- 	disable_link(pipe_ctx->stream->sink->link, pipe_ctx->signal);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0799-drm-amd-dal-Remove-generic-i2c-hw-engine.patch b/common/recipes-kernel/linux/files/0799-drm-amd-dal-Remove-generic-i2c-hw-engine.patch
deleted file mode 100644
index e68103ed..00000000
--- a/common/recipes-kernel/linux/files/0799-drm-amd-dal-Remove-generic-i2c-hw-engine.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 3908bc8845d0d991a82a8f9d07d18aa9d8775724 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 16 Feb 2016 15:29:03 -0500
-Subject: [PATCH 0799/1110] drm/amd/dal: Remove generic i2c hw engine
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
----
- .../i2caux/dce110/i2c_generic_hw_engine_dce110.h   | 25 ----------------------
- 1 file changed, 25 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
-deleted file mode 100644
-index e6b6a97..0000000
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h
-+++ /dev/null
-@@ -1,25 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0800-drm-amd-dal-fix-some-missing-hawaii-cases-in-dm.patch b/common/recipes-kernel/linux/files/0800-drm-amd-dal-fix-some-missing-hawaii-cases-in-dm.patch
deleted file mode 100644
index a7371831..00000000
--- a/common/recipes-kernel/linux/files/0800-drm-amd-dal-fix-some-missing-hawaii-cases-in-dm.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 1563050ee19a3f88d6df42250badd5b873a7e5f5 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 18 Feb 2016 15:20:27 -0500
-Subject: [PATCH 0800/1110] drm/amd/dal: fix some missing hawaii cases in dm
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 7a7f69e..5b65986 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1218,6 +1218,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 	/* Software is initialized. Now we can register interrupt handlers. */
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
- 	case CHIP_CARRIZO:
-@@ -1433,6 +1434,7 @@ static int dm_early_init(void *handle)
- 
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
- 		adev->mode_info.num_crtc = 6;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 6;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0801-drm-amdgpu-export-some-dce-functions-to-share-with-D.patch b/common/recipes-kernel/linux/files/0801-drm-amdgpu-export-some-dce-functions-to-share-with-D.patch
deleted file mode 100644
index 384fed9c..00000000
--- a/common/recipes-kernel/linux/files/0801-drm-amdgpu-export-some-dce-functions-to-share-with-D.patch
+++ /dev/null
@@ -1,187 +0,0 @@
-From b02a75a3e0fab415d09bbd38d4f04754f392d805 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 18 Feb 2016 16:01:27 -0500
-Subject: [PATCH 0801/1110] drm/amdgpu: export some dce functions to share with
- DAL (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Share some common DCE 8/10/11 functions with DAL.
-
-v2: drop extern
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 12 ++++++------
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.h |  7 +++++++
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 12 ++++++------
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.h |  7 +++++++
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  | 12 ++++++------
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.h  |  7 +++++++
- 6 files changed, 39 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 80261bc..2445c01 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -556,8 +556,8 @@ static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
- 	return true;
- }
- 
--static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
--				     struct amdgpu_mode_mc_save *save)
-+void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
-+			      struct amdgpu_mode_mc_save *save)
- {
- 	u32 crtc_enabled, tmp;
- 	int i;
-@@ -621,8 +621,8 @@ static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
- 	}
- }
- 
--static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
--				       struct amdgpu_mode_mc_save *save)
-+void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
-+				struct amdgpu_mode_mc_save *save)
- {
- 	u32 tmp, frame_count;
- 	int i, j;
-@@ -684,8 +684,8 @@ static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
- 	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
- }
- 
--static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
--					   bool render)
-+void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
-+				    bool render)
- {
- 	u32 tmp;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
-index 1bfa48d..3947956 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
-@@ -26,4 +26,11 @@
- 
- extern const struct amd_ip_funcs dce_v10_0_ip_funcs;
- 
-+void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
-+				    bool render);
-+void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
-+			      struct amdgpu_mode_mc_save *save);
-+void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
-+				struct amdgpu_mode_mc_save *save);
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index fd74bce..8a616a7 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -546,8 +546,8 @@ static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
- 	return true;
- }
- 
--static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
--				     struct amdgpu_mode_mc_save *save)
-+void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
-+			      struct amdgpu_mode_mc_save *save)
- {
- 	u32 crtc_enabled, tmp;
- 	int i;
-@@ -590,8 +590,8 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
- 	}
- }
- 
--static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
--				       struct amdgpu_mode_mc_save *save)
-+void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
-+				struct amdgpu_mode_mc_save *save)
- {
- 	u32 tmp;
- 	int i;
-@@ -619,8 +619,8 @@ static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
- 	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
- }
- 
--static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
--					   bool render)
-+void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
-+				    bool render)
- {
- 	u32 tmp;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
-index 84e4618..dc6ff04 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h
-@@ -26,4 +26,11 @@
- 
- extern const struct amd_ip_funcs dce_v11_0_ip_funcs;
- 
-+void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
-+				    bool render);
-+void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
-+			      struct amdgpu_mode_mc_save *save);
-+void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
-+				struct amdgpu_mode_mc_save *save);
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index b351e76..a42148f 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -504,8 +504,8 @@ static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
- 	return true;
- }
- 
--static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
--				    struct amdgpu_mode_mc_save *save)
-+void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
-+			     struct amdgpu_mode_mc_save *save)
- {
- 	u32 crtc_enabled, tmp;
- 	int i;
-@@ -569,8 +569,8 @@ static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
- 	}
- }
- 
--static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
--				      struct amdgpu_mode_mc_save *save)
-+void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
-+			       struct amdgpu_mode_mc_save *save)
- {
- 	u32 tmp, frame_count;
- 	int i, j;
-@@ -632,8 +632,8 @@ static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
- 	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
- }
- 
--static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
--					  bool render)
-+void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
-+				   bool render)
- {
- 	u32 tmp;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
-index 7701685..4bb72ab 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h
-@@ -26,4 +26,11 @@
- 
- extern const struct amd_ip_funcs dce_v8_0_ip_funcs;
- 
-+void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
-+				   bool render);
-+void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
-+			     struct amdgpu_mode_mc_save *save);
-+void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
-+			       struct amdgpu_mode_mc_save *save);
-+
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0802-drm-amd-dal-dm-use-existing-dce-functions-for-some-t.patch b/common/recipes-kernel/linux/files/0802-drm-amd-dal-dm-use-existing-dce-functions-for-some-t.patch
deleted file mode 100644
index 75ea8c90..00000000
--- a/common/recipes-kernel/linux/files/0802-drm-amd-dal-dm-use-existing-dce-functions-for-some-t.patch
+++ /dev/null
@@ -1,436 +0,0 @@
-From e93de9f5e91a535dd4431312b186834bf0f4750e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 18 Feb 2016 16:05:47 -0500
-Subject: [PATCH 0802/1110] drm/amd/dal/dm: use existing dce functions for some
- things (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-stop/resume MC access, disable render support
-
-v2: rebase on amd-staging-4.3
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 324 +++++---------------------
- 1 file changed, 63 insertions(+), 261 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 5b65986..aa78d6c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -36,15 +36,11 @@
- #include "amdgpu_dm_irq.h"
- #include "dm_helpers.h"
- 
--#include "dce/dce_11_0_d.h"
--#include "dce/dce_11_0_sh_mask.h"
--#include "dce/dce_11_0_enum.h"
--#include "ivsrcid/ivsrcid_vislands30.h"
-+#include "dce_v8_0.h"
-+#include "dce_v10_0.h"
-+#include "dce_v11_0.h"
- 
--#include "oss/oss_3_0_d.h"
--#include "oss/oss_3_0_sh_mask.h"
--#include "gmc/gmc_8_1_d.h"
--#include "gmc/gmc_8_1_sh_mask.h"
-+#include "ivsrcid/ivsrcid_vislands30.h"
- 
- #include <linux/module.h>
- #include <linux/moduleparam.h>
-@@ -53,19 +49,6 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_dp_mst_helper.h>
- 
--/* TODO: Remove when mc access work around is removed */
--static const u32 crtc_offsets[] =
--{
--	CRTC0_REGISTER_OFFSET,
--	CRTC1_REGISTER_OFFSET,
--	CRTC2_REGISTER_OFFSET,
--	CRTC3_REGISTER_OFFSET,
--	CRTC4_REGISTER_OFFSET,
--	CRTC5_REGISTER_OFFSET,
--	CRTC6_REGISTER_OFFSET
--};
--/* TODO: End of when Remove mc access work around is removed */
--
- /* Define variables here
-  * These values will be passed to DAL for feature enable purpose
-  * Disable ALL for HDMI light up
-@@ -122,184 +105,6 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
- 	return 0;
- }
- 
--static u32 dm_hpd_get_gpio_reg(struct amdgpu_device *adev)
--{
--	return mmDC_GPIO_HPD_A;
--}
--
--
--static bool dm_is_display_hung(struct amdgpu_device *adev)
--{
--	/* TODO: #DAL3 need to replace
--	u32 crtc_hung = 0;
--	u32 i, j, tmp;
--
--	crtc_hung = dal_get_connected_targets_vector(adev->dm.dal);
--
--	for (j = 0; j < 10; j++) {
--		for (i = 0; i < adev->mode_info.num_crtc; i++) {
--			if (crtc_hung & (1 << i)) {
--				int32_t vpos1, hpos1;
--				int32_t vpos2, hpos2;
--
--				tmp = dal_get_crtc_scanoutpos(
--					adev->dm.dal,
--					i,
--					&vpos1,
--					&hpos1);
--				udelay(10);
--				tmp = dal_get_crtc_scanoutpos(
--					adev->dm.dal,
--					i,
--					&vpos2,
--					&hpos2);
--
--				if (hpos1 != hpos2 && vpos1 != vpos2)
--					crtc_hung &= ~(1 << i);
--			}
--		}
--
--		if (crtc_hung == 0)
--			return false;
--	}
--*/
--	return true;
--}
--
--/* TODO: Remove mc access work around*/
--static void dm_stop_mc_access(struct amdgpu_device *adev,
--				     struct amdgpu_mode_mc_save *save)
--{
--
--	u32 crtc_enabled, tmp;
--	int i;
--
--	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
--	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
--
--	/* disable VGA render */
--	tmp = RREG32(mmVGA_RENDER_CONTROL);
--	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
--	WREG32(mmVGA_RENDER_CONTROL, tmp);
--
--	/* blank the display controllers */
--	for (i = 0; i < adev->mode_info.num_crtc; i++) {
--		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
--					     CRTC_CONTROL, CRTC_MASTER_EN);
--		if (crtc_enabled) {
--#if 0
--			u32 frame_count;
--			int j;
--
--			save->crtc_enabled[i] = true;
--			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
--				amdgpu_display_vblank_wait(adev, i);
--				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
--				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
--				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
--				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			}
--			/* wait for the next frame */
--			frame_count = amdgpu_display_vblank_get_counter(adev, i);
--			for (j = 0; j < adev->usec_timeout; j++) {
--				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
--					break;
--				udelay(1);
--			}
--			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
--				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
--				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
--				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
--				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
--			}
--#else
--			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
--			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
--			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
--			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			save->crtc_enabled[i] = false;
--			/* ***** */
--#endif
--		} else {
--			save->crtc_enabled[i] = false;
--		}
--	}
--}
--
--
--static void dm_resume_mc_access(struct amdgpu_device *adev,
--				       struct amdgpu_mode_mc_save *save)
--{
--
--	u32 tmp, frame_count;
--	int i, j;
--
--	/* update crtc base addresses */
--	for (i = 0; i < adev->mode_info.num_crtc; i++) {
--		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
--		       upper_32_bits(adev->mc.vram_start));
--		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
--		       upper_32_bits(adev->mc.vram_start));
--		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
--		       (u32)adev->mc.vram_start);
--		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
--		       (u32)adev->mc.vram_start);
--
--		if (save->crtc_enabled[i]) {
--			tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
--				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
--				WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
--				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
--				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
--				tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
--				WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
--			}
--			for (j = 0; j < adev->usec_timeout; j++) {
--				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
--					break;
--				udelay(1);
--			}
--			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
--			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
--			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			/* wait for the next frame */
--			frame_count = amdgpu_display_vblank_get_counter(adev, i);
--			for (j = 0; j < adev->usec_timeout; j++) {
--				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
--					break;
--				udelay(1);
--			}
--		}
--	}
--
--	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
--	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
--
--	/* Unlock vga access */
--	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
--	mdelay(1);
--	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
--}
--
--/* End of TODO: Remove mc access work around*/
--
- static bool dm_is_idle(void *handle)
- {
- 	/* XXX todo */
-@@ -315,37 +120,13 @@ static int dm_wait_for_idle(void *handle)
- static void dm_print_status(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	dev_info(adev->dev, "DCE 10.x registers\n");
-+	dev_info(adev->dev, "DCE registers\n");
- 	/* XXX todo */
- }
- 
- static int dm_soft_reset(void *handle)
- {
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	u32 srbm_soft_reset = 0, tmp;
--
--	if (dm_is_display_hung(adev))
--		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
--
--	if (srbm_soft_reset) {
--		dm_print_status(adev);
--
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--		tmp |= srbm_soft_reset;
--		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
--		WREG32(mmSRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--
--		udelay(50);
--
--		tmp &= ~srbm_soft_reset;
--		WREG32(mmSRBM_SOFT_RESET, tmp);
--		tmp = RREG32(mmSRBM_SOFT_RESET);
--
--		/* Wait a little for things to settle down */
--		udelay(50);
--		dm_print_status(adev);
--	}
-+	/* XXX todo */
- 	return 0;
- }
- 
-@@ -1253,29 +1034,6 @@ void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
-  * amdgpu_display_funcs functions
-  *****************************************************************************/
- 
--
--static void dm_set_vga_render_state(struct amdgpu_device *adev,
--					   bool render)
--{
--	u32 tmp;
--
--	/* Lockout access through VGA aperture*/
--	tmp = RREG32(mmVGA_HDP_CONTROL);
--	if (render)
--		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
--	else
--		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
--	WREG32(mmVGA_HDP_CONTROL, tmp);
--
--	/* disable VGA render */
--	tmp = RREG32(mmVGA_RENDER_CONTROL);
--	if (render)
--		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
--	else
--		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
--	WREG32(mmVGA_RENDER_CONTROL, tmp);
--}
--
- /**
-  * dm_bandwidth_update - program display watermarks
-  *
-@@ -1398,38 +1156,76 @@ static void dm_page_flip(struct amdgpu_device *adev,
- 			&addr, 1);
- }
- 
--static const struct amdgpu_display_funcs display_funcs = {
--	.set_vga_render_state = dm_set_vga_render_state,
-+static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = {
-+	.set_vga_render_state = dce_v8_0_set_vga_render_state,
- 	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
- 	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
--	.vblank_wait = NULL, /* not called anywhere */
--	.is_display_hung = dm_is_display_hung,/* called unconditionally */
-+	.vblank_wait = NULL,
-+	.is_display_hung = NULL, /* not called anywhere */
- 	.backlight_set_level =
- 		dm_set_backlight_level,/* called unconditionally */
- 	.backlight_get_level =
- 		dm_get_backlight_level,/* called unconditionally */
- 	.hpd_sense = NULL,/* called unconditionally */
- 	.hpd_set_polarity = NULL, /* called unconditionally */
--	.hpd_get_gpio_reg = dm_hpd_get_gpio_reg,/* called unconditionally */
-+	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
- 	.page_flip = dm_page_flip, /* called unconditionally */
- 	.page_flip_get_scanoutpos =
- 		dm_crtc_get_scanoutpos,/* called unconditionally */
- 	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
- 	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
--	.stop_mc_access = dm_stop_mc_access, /* called unconditionally */
--	.resume_mc_access = dm_resume_mc_access, /* called unconditionally */
-+	.stop_mc_access = dce_v8_0_stop_mc_access, /* called unconditionally */
-+	.resume_mc_access = dce_v8_0_resume_mc_access, /* called unconditionally */
- };
- 
--static void set_display_funcs(struct amdgpu_device *adev)
--{
--	if (adev->mode_info.funcs == NULL)
--		adev->mode_info.funcs = &display_funcs;
--}
-+static const struct amdgpu_display_funcs dm_dce_v10_0_display_funcs = {
-+	.set_vga_render_state = dce_v10_0_set_vga_render_state,
-+	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-+	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-+	.vblank_wait = NULL,
-+	.is_display_hung = NULL, /* not called anywhere */
-+	.backlight_set_level =
-+		dm_set_backlight_level,/* called unconditionally */
-+	.backlight_get_level =
-+		dm_get_backlight_level,/* called unconditionally */
-+	.hpd_sense = NULL,/* called unconditionally */
-+	.hpd_set_polarity = NULL, /* called unconditionally */
-+	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-+	.page_flip = dm_page_flip, /* called unconditionally */
-+	.page_flip_get_scanoutpos =
-+		dm_crtc_get_scanoutpos,/* called unconditionally */
-+	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-+	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
-+	.stop_mc_access = dce_v10_0_stop_mc_access, /* called unconditionally */
-+	.resume_mc_access = dce_v10_0_resume_mc_access, /* called unconditionally */
-+};
-+
-+static const struct amdgpu_display_funcs dm_dce_v11_0_display_funcs = {
-+	.set_vga_render_state = dce_v11_0_set_vga_render_state,
-+	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-+	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-+	.vblank_wait = NULL,
-+	.is_display_hung = NULL, /* not called anywhere */
-+	.backlight_set_level =
-+		dm_set_backlight_level,/* called unconditionally */
-+	.backlight_get_level =
-+		dm_get_backlight_level,/* called unconditionally */
-+	.hpd_sense = NULL,/* called unconditionally */
-+	.hpd_set_polarity = NULL, /* called unconditionally */
-+	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-+	.page_flip = dm_page_flip, /* called unconditionally */
-+	.page_flip_get_scanoutpos =
-+		dm_crtc_get_scanoutpos,/* called unconditionally */
-+	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-+	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
-+	.stop_mc_access = dce_v11_0_stop_mc_access, /* called unconditionally */
-+	.resume_mc_access = dce_v11_0_resume_mc_access, /* called unconditionally */
-+};
- 
- static int dm_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	set_display_funcs(adev);
-+
- 	amdgpu_dm_set_irq_funcs(adev);
- 
- 	switch (adev->asic_type) {
-@@ -1438,17 +1234,23 @@ static int dm_early_init(void *handle)
- 		adev->mode_info.num_crtc = 6;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 6;
-+		if (adev->mode_info.funcs == NULL)
-+			adev->mode_info.funcs = &dm_dce_v8_0_display_funcs;
- 		break;
- 	case CHIP_FIJI:
- 	case CHIP_TONGA:
- 		adev->mode_info.num_crtc = 6;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 7;
-+		if (adev->mode_info.funcs == NULL)
-+			adev->mode_info.funcs = &dm_dce_v10_0_display_funcs;
- 		break;
- 	case CHIP_CARRIZO:
- 		adev->mode_info.num_crtc = 3;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 9;
-+		if (adev->mode_info.funcs == NULL)
-+			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
- 		break;
- 	default:
- 		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0803-drm-amd-dal-Adding-Hawaii-and-Bonaire-support-to-DAL.patch b/common/recipes-kernel/linux/files/0803-drm-amd-dal-Adding-Hawaii-and-Bonaire-support-to-DAL.patch
deleted file mode 100644
index 0a8091e8..00000000
--- a/common/recipes-kernel/linux/files/0803-drm-amd-dal-Adding-Hawaii-and-Bonaire-support-to-DAL.patch
+++ /dev/null
@@ -1,19970 +0,0 @@
-From f916c629a50d432a9b9b46d859ddbc93e2ca1973 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 17 Feb 2016 10:41:59 -0500
-Subject: [PATCH 0803/1110] drm/amd/dal: Adding Hawaii and Bonaire support to
- DAL
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/dal/Kconfig                    |   17 +-
- drivers/gpu/drm/amd/dal/dc/Makefile                |    4 +
- drivers/gpu/drm/amd/dal/dc/adapter/Makefile        |    8 +
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   13 +
- .../adapter/dce80/hw_ctx_adapter_service_dce80.c   |  322 ++++
- .../adapter/dce80/hw_ctx_adapter_service_dce80.h   |   40 +
- .../gpu/drm/amd/dal/dc/asic_capability/Makefile    |   13 +
- .../amd/dal/dc/asic_capability/asic_capability.c   |    8 +
- .../dc/asic_capability/hawaii_asic_capability.c    |  151 ++
- .../dc/asic_capability/hawaii_asic_capability.h    |   37 +
- drivers/gpu/drm/amd/dal/dc/audio/Makefile          |   12 +
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |    9 +
- .../gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c   |  434 +++++
- .../gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h   |   41 +
- .../amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c    | 1926 ++++++++++++++++++++
- .../amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h    |   75 +
- drivers/gpu/drm/amd/dal/dc/bios/Makefile           |   13 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |    6 +-
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |    4 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |    5 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |    3 +
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   |  773 ++++++++
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.h   |   33 +
- .../dal/dc/bios/dce80/command_table_helper_dce80.c |  355 ++++
- .../dal/dc/bios/dce80/command_table_helper_dce80.h |   33 +
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |    7 +
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |    3 +
- drivers/gpu/drm/amd/dal/dc/dce80/Makefile          |   17 +
- .../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c    |  867 +++++++++
- .../gpu/drm/amd/dal/dc/dce80/dce80_compressor.h    |   84 +
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |  308 ++++
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h  |   36 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c       |   64 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h       |   49 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c |   85 +
- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c  |  329 ++++
- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h  |   39 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c |  217 +++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h |   41 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c       |  141 ++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h       |  130 ++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c   |  905 +++++++++
- .../gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c |  577 ++++++
- .../gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c   |  546 ++++++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 1267 +++++++++++++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h  |   42 +
- .../drm/amd/dal/dc/dce80/dce80_stream_encoder.c    | 1104 +++++++++++
- .../drm/amd/dal/dc/dce80/dce80_stream_encoder.h    |   85 +
- .../drm/amd/dal/dc/dce80/dce80_timing_generator.c  |  241 +++
- .../drm/amd/dal/dc/dce80/dce80_timing_generator.h  |   49 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c |   91 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h |   87 +
- .../amd/dal/dc/dce80/dce80_transform_bit_depth.c   |  841 +++++++++
- .../amd/dal/dc/dce80/dce80_transform_bit_depth.h   |   51 +
- .../drm/amd/dal/dc/dce80/dce80_transform_gamut.c   |  297 +++
- .../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c |  814 +++++++++
- drivers/gpu/drm/amd/dal/dc/gpio/Makefile           |   12 +
- .../gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c   |  893 +++++++++
- .../gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.h   |   46 +
- .../drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c   |   78 +
- .../drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.h   |   32 +
- .../gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c   |  378 ++++
- .../gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.h   |   44 +
- .../drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.c |  424 +++++
- .../drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.h |   32 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |    9 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |   10 +-
- drivers/gpu/drm/amd/dal/dc/gpu/Makefile            |   12 +
- .../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c   |   52 +
- .../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h   |   31 +
- .../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c |  925 ++++++++++
- .../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h |   58 +
- drivers/gpu/drm/amd/dal/dc/i2caux/Makefile         |   11 +
- .../drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c |  740 ++++++++
- .../drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.h |   54 +
- .../amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c  |  901 +++++++++
- .../amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.h  |   54 +
- .../amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c  |  187 ++
- .../amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.h  |   43 +
- .../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c |  264 +++
- .../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h |   39 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |    8 +
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |   11 +
- drivers/gpu/drm/amd/dal/include/dal_types.h        |    3 +
- .../drm/amd/dal/include/display_clock_interface.h  |    6 +
- 85 files changed, 19100 insertions(+), 6 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h
-
-diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
-index 0dc6f86..b108756 100644
---- a/drivers/gpu/drm/amd/dal/Kconfig
-+++ b/drivers/gpu/drm/amd/dal/Kconfig
-@@ -19,14 +19,14 @@ config DRM_AMD_DAL_VBIOS_PRESENT
- 	 x86 platforms and there is a VBIOS
- 	 present in the system
- 
--config DRM_AMD_DAL_DCE11_0
--        bool "Carrizo family"
-+config DRM_AMD_DAL_DCE8_0
-+        bool "CI family"
-         depends on DRM_AMD_DAL
-         help
-          Choose this option
- 	 if you want to have
--	 CZ family
--	 for display engine
-+	 CI family
-+	 for display engine.
- 
- config DRM_AMD_DAL_DCE10_0
-         bool "VI family"
-@@ -37,6 +37,15 @@ config DRM_AMD_DAL_DCE10_0
- 	 VI family for display
- 	 engine.
- 
-+config DRM_AMD_DAL_DCE11_0
-+        bool "Carrizo family"
-+        depends on DRM_AMD_DAL
-+        help
-+         Choose this option
-+	 if you want to have
-+	 CZ family
-+	 for display engine
-+
- config DEBUG_KERNEL_DAL
-         bool "Enable kgdb break in DAL"
-         depends on DRM_AMD_DAL
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index aed26ee..5112ec9 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -13,6 +13,10 @@ ifdef CONFIG_DRM_AMD_DAL_DCE10_0
- DC_LIBS += dce100
- endif
- 
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+DC_LIBS += dce80
-+endif
-+
- AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS)))
- 
- include $(AMD_DC)
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-index 2c6ca7a..db1f0e8 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-@@ -8,6 +8,14 @@ AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER))
- 
- AMD_DAL_FILES += $(AMD_DAL_ADAPTER)
- 
-+###############################################################################
-+# DCE 8x
-+###############################################################################
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce80/hw_ctx_adapter_service_dce80.o
-+endif
-+
- 
- ###############################################################################
- # DCE 11x
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index dd2f931..f914a8c 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -41,6 +41,10 @@
- 
- #include "atom.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/hw_ctx_adapter_service_dce80.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/hw_ctx_adapter_service_dce110.h"
- #endif
-@@ -665,6 +669,10 @@ static struct hw_ctx_adapter_service *create_hw_ctx(
- 		return dal_adapter_service_create_hw_ctx_diag(ctx);
- 
- 	switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		return dal_adapter_service_create_hw_ctx_dce80(ctx);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		return dal_adapter_service_create_hw_ctx_dce110(ctx);
-@@ -903,6 +911,11 @@ enum dce_version dal_adapter_service_get_dce_version(
- 	uint32_t version = as->asic_cap->data[ASIC_DATA_DCE_VERSION];
- 
- 	switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case 0x80:
-+		/* CI Bonaire */
-+		return DCE_VERSION_8_0;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case 0x100:
- 		return DCE_VERSION_10_0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c
-new file mode 100644
-index 0000000..9d6505c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c
-@@ -0,0 +1,322 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/adapter_service_types.h"
-+#include "include/grph_object_id.h"
-+#include "../hw_ctx_adapter_service.h"
-+
-+#include "hw_ctx_adapter_service_dce80.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x1918
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+enum {
-+	MAX_NUMBER_OF_AUDIO_PINS = 7
-+};
-+
-+static const uint32_t audio_index_reg_offset[] = {
-+	mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	/* TR, BN has 7 audio endpoints but 6 DIGs */
-+	mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
-+};
-+
-+static const uint32_t audio_data_reg_offset[] = {
-+	mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
-+};
-+
-+static const struct graphics_object_id invalid_go = {
-+	0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN
-+};
-+
-+#define FROM_HW_CTX(ptr) \
-+	container_of((ptr), struct hw_ctx_adapter_service_dce80, base)
-+
-+static void destruct(
-+	struct hw_ctx_adapter_service_dce80 *hw_ctx)
-+{
-+	/* There is nothing to destruct at the moment */
-+
-+	dal_adapter_service_destruct_hw_ctx(&hw_ctx->base);
-+}
-+
-+static void destroy(
-+	struct hw_ctx_adapter_service *ptr)
-+{
-+	struct hw_ctx_adapter_service_dce80 *hw_ctx =
-+		FROM_HW_CTX(ptr);
-+
-+	destruct(hw_ctx);
-+
-+	dm_free(ptr->ctx, hw_ctx);
-+}
-+
-+static uint32_t get_number_of_connected_audio_endpoints_multistream(
-+		struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	struct dc_context *ctx = hw_ctx->ctx;
-+	uint32_t num_connected_audio_endpoints = 0;
-+	uint32_t i;
-+	uint32_t default_config =
-+	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT;
-+
-+	/* find the total number of streams available via the
-+	 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
-+	 * registers (one for each pin) starting from pin 1
-+	 * up to the max number of audio pins.
-+	 * We stop on the first pin where
-+	 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
-+	 */
-+	for (i = 0; i < MAX_NUMBER_OF_AUDIO_PINS; i++) {
-+		uint32_t value = 0;
-+
-+		set_reg_field_value(value,
-+			default_config,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dm_write_reg(ctx, audio_index_reg_offset[i], value);
-+
-+		value = 0;
-+		value = dm_read_reg(ctx, audio_data_reg_offset[i]);
-+
-+		/* 1 means not supported*/
-+		if (get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
-+		PORT_CONNECTIVITY) == 1)
-+			break;
-+
-+		num_connected_audio_endpoints++;
-+	}
-+
-+	return num_connected_audio_endpoints;
-+}
-+
-+static uint32_t get_number_of_connected_audio_endpoints(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	uint32_t addr = mmCC_DC_HDMI_STRAPS;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	if (hw_ctx->cached_audio_straps == AUDIO_STRAPS_NOT_ALLOWED)
-+		/* audio straps indicate no audio supported */
-+		return 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	field = get_reg_field_value(
-+			value, CC_DC_HDMI_STRAPS, AUDIO_STREAM_NUMBER);
-+	if (field == 1)
-+		/* multi streams not supported */
-+		return 1;
-+	else if (field == 0)
-+		/* multi streams supported */
-+		return get_number_of_connected_audio_endpoints_multistream(
-+				hw_ctx);
-+
-+	/* unexpected value */
-+	ASSERT_CRITICAL(false);
-+	return field;
-+}
-+
-+static bool power_up(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, mmCC_DC_HDMI_STRAPS);
-+	field = get_reg_field_value(
-+			value, CC_DC_HDMI_STRAPS, HDMI_DISABLE);
-+
-+	if (field == 0) {
-+		hw_ctx->cached_audio_straps = AUDIO_STRAPS_DP_HDMI_AUDIO;
-+	} else {
-+		value = dm_read_reg(
-+				hw_ctx->ctx, mmDC_PINSTRAPS);
-+		field = get_reg_field_value(
-+					value,
-+					DC_PINSTRAPS,
-+					DC_PINSTRAPS_AUDIO);
-+	}
-+
-+	/* get the number of connected audio endpoints */
-+	FROM_HW_CTX(hw_ctx)->number_of_connected_audio_endpoints =
-+		get_number_of_connected_audio_endpoints(hw_ctx);
-+
-+	return true;
-+}
-+
-+static struct graphics_object_id enum_fake_path_resource(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	if (index == 0)
-+		return dal_graphics_object_id_init(
-+			CONNECTOR_ID_VGA,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_CONNECTOR);
-+	else if (index == 1)
-+		return dal_graphics_object_id_init(
-+			ENCODER_ID_INTERNAL_KLDSCP_DAC1,
-+			ENUM_ID_1,
-+			OBJECT_TYPE_ENCODER);
-+	else
-+		return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_stereo_sync_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_sync_output_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	return invalid_go;
-+}
-+
-+static struct graphics_object_id enum_audio_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	uint32_t number_of_connected_audio_endpoints =
-+		FROM_HW_CTX(hw_ctx)->number_of_connected_audio_endpoints;
-+
-+	if (index >= number_of_connected_audio_endpoints)
-+		return invalid_go;
-+	else
-+		return dal_graphics_object_id_init(
-+			AUDIO_ID_INTERNAL_AZALIA,
-+			(enum object_enum_id)(index + 1),
-+			OBJECT_TYPE_AUDIO);
-+}
-+
-+static void update_audio_connectivity(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t number_of_audio_capable_display_path,
-+	uint32_t number_of_controllers)
-+{
-+	uint32_t number_of_connected_audio_endpoints =
-+		FROM_HW_CTX(hw_ctx)->number_of_connected_audio_endpoints;
-+
-+	uint32_t co_func_audio_endpoint = number_of_connected_audio_endpoints;
-+	struct dc_context *ctx = hw_ctx->ctx;
-+
-+	if (co_func_audio_endpoint > number_of_audio_capable_display_path)
-+		co_func_audio_endpoint = number_of_audio_capable_display_path;
-+
-+	if (co_func_audio_endpoint > number_of_controllers)
-+		co_func_audio_endpoint = number_of_controllers;
-+
-+	if (co_func_audio_endpoint < number_of_connected_audio_endpoints) {
-+		const uint32_t addr = mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY;
-+
-+		uint32_t value;
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(value,
-+				7 - co_func_audio_endpoint,
-+				CC_RCU_DC_AUDIO_PORT_CONNECTIVITY,
-+				PORT_CONNECTIVITY);
-+		set_reg_field_value(value,
-+				1,
-+				CC_RCU_DC_AUDIO_PORT_CONNECTIVITY,
-+				PORT_CONNECTIVITY_OVERRIDE_ENABLE);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+	destroy,
-+	power_up,
-+	enum_fake_path_resource,
-+	enum_stereo_sync_object,
-+	enum_sync_output_object,
-+	enum_audio_object,
-+	update_audio_connectivity
-+};
-+
-+static bool construct(
-+	struct hw_ctx_adapter_service_dce80 *hw_ctx,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_adapter_service_construct_hw_ctx(&hw_ctx->base, ctx)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	hw_ctx->base.funcs = &funcs;
-+
-+	hw_ctx->number_of_connected_audio_endpoints = 0;
-+
-+	return true;
-+}
-+
-+struct hw_ctx_adapter_service *
-+	dal_adapter_service_create_hw_ctx_dce80(struct dc_context *ctx)
-+{
-+	struct hw_ctx_adapter_service_dce80 *hw_ctx =
-+			dm_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce80));
-+
-+	if (!hw_ctx) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(hw_ctx, ctx))
-+		return &hw_ctx->base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(ctx, hw_ctx);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h
-new file mode 100644
-index 0000000..a735eaf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_DCE80_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_DCE80_H__
-+
-+struct hw_ctx_adapter_service_dce80 {
-+	struct hw_ctx_adapter_service base;
-+	uint32_t number_of_connected_audio_endpoints;
-+};
-+
-+struct hw_ctx_adapter_service *
-+	dal_adapter_service_create_hw_ctx_dce80(
-+			struct dc_context *ctx);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DCE80_H__ */
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-index 8491b38..b243542 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-@@ -10,6 +10,19 @@ AMD_DAL_ASIC_CAPABILITY = \
- AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
- 
- ###############################################################################
-+# DCE 8x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+ASIC_CAPABILITY_DCE80 = hawaii_asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY_DCE80 = \
-+	$(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE80))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE80)
-+endif
-+
-+
-+###############################################################################
- # DCE 10x
- ###############################################################################
- ifdef CONFIG_DRM_AMD_DAL_DCE10_0
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index 7a905f5..69909dd 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -32,6 +32,10 @@
- #include "include/dal_types.h"
- #include "include/dal_asic_id.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "hawaii_asic_capability.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "tonga_asic_capability.h"
- #endif
-@@ -85,6 +89,10 @@ static bool construct(
- 
- 	switch (init->chip_family) {
- 	case FAMILY_CI:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+		dal_hawaii_asic_capability_create(cap, init);
-+		asic_supported = true;
-+#endif
- 		break;
- 
- 	case FAMILY_KV:
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
-new file mode 100644
-index 0000000..2745ac1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
-@@ -0,0 +1,151 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Includes
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+#include "include/dal_types.h"
-+#include "include/dal_asic_id.h"
-+#include "include/logger_interface.h"
-+#include "hawaii_asic_capability.h"
-+
-+#include "atom.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "gmc/gmc_7_1_d.h"
-+
-+
-+/*
-+ * Sea Islands (CI) ASIC capability.
-+ *
-+ * dal_hawaii_asic_capability_create
-+ *
-+ * Create and initiate hawaii capability.
-+ */
-+void dal_hawaii_asic_capability_create(struct asic_capability *cap,
-+		struct hw_asic_id *init)
-+{
-+	uint32_t mc_seq_misc0;
-+
-+	/* ASIC data */
-+	cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
-+	cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
-+	cap->data[ASIC_DATA_DIGFE_NUM] = 6;
-+	cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
-+	cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
-+	cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
-+
-+	cap->data[ASIC_DATA_DCE_VERSION] = 0x80; /* DCE 8.0 */
-+
-+	/* Pixel RAM is 1712 entries of 144 bits each or
-+	 * in other words 246528 bits. */
-+	cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
-+	cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
-+	cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
-+	cap->data[ASIC_DATA_MC_LATENCY] = 5000; /* units of ns */
-+
-+	/* StutterModeEnhanced; Quad DMIF Buffer */
-+	cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
-+	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
-+	cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-+
-+	/* 3 HDMI support by default */
-+	cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
-+
-+	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
-+
-+	mc_seq_misc0 = dm_read_reg(cap->ctx, mmMC_SEQ_MISC0);
-+
-+	switch (mc_seq_misc0 & MC_MISC0__MEMORY_TYPE_MASK) {
-+	case MC_MISC0__MEMORY_TYPE__GDDR1:
-+	case MC_MISC0__MEMORY_TYPE__DDR2:
-+	case MC_MISC0__MEMORY_TYPE__DDR3:
-+	case MC_MISC0__MEMORY_TYPE__GDDR3:
-+	case MC_MISC0__MEMORY_TYPE__GDDR4:
-+		cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
-+		break;
-+	case MC_MISC0__MEMORY_TYPE__GDDR5:
-+		cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
-+		break;
-+	default:
-+		dal_logger_write(cap->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_MASK_ALL,
-+			"%s:Unrecognized memory type!", __func__);
-+		cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
-+		break;
-+	}
-+
-+	/* ASIC stereo 3D capability */
-+	cap->stereo_3d_caps.INTERLEAVE = true;
-+	cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
-+	cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
-+	cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
-+
-+	/* ASIC basic capability */
-+	cap->caps.DP_MST_SUPPORTED = true;
-+	cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
-+
-+	cap->caps.MIRABILIS_SUPPORTED = true;
-+	cap->caps.MIRABILIS_ENABLED_BY_DEFAULT = true;
-+
-+	/* Remap device tag IDs when patching VBIOS. */
-+	cap->caps.DEVICE_TAG_REMAP_SUPPORTED = true;
-+
-+	/* Report headless if no OPM attached (with MXM connectors present). */
-+	cap->caps.HEADLESS_NO_OPM_SUPPORTED = true;
-+
-+
-+	cap->caps.HPD_CHECK_FOR_EDID = true;
-+	cap->caps.NO_VCC_OFF_HPD_POLLING = true;
-+
-+	/* true will hang the system! */
-+	cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = false;
-+
-+	/* Do w/a on CI A0 by default */
-+	if (init->hw_internal_rev == CI_BONAIRE_M_A0)
-+		cap->bugs.LB_WA_IS_SUPPORTED = true;
-+
-+	/* Apply MC Tuning for Hawaii */
-+	if (ASIC_REV_IS_HAWAII_P(init->hw_internal_rev))
-+		cap->caps.NEED_MC_TUNING = true;
-+
-+	/* DCE6.0 and DCE8.0 has a HW issue when accessing registers
-+	 * from ROM block. When there is a W access following R or W access
-+	 * right after (no more than couple of cycles)  the first W access
-+	 * sometimes is not executed (in rate of about once per 100K tries).
-+	 * It creates problems in different scenarios of FL setup. */
-+	cap->bugs.ROM_REGISTER_ACCESS = true;
-+
-+	/* VCE is supported */
-+	cap->caps.VCE_SUPPORTED = true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
-new file mode 100644
-index 0000000..191d9b2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BONAIRE_CAPABILITY_H__
-+#define __DAL_BONAIRE_CAPABILITY_H__
-+
-+/* Forward declaration */
-+struct asic_capability;
-+struct hw_asic_id;
-+
-+/* Create and initialise Bonaire data */
-+void dal_hawaii_asic_capability_create(struct asic_capability *cap,
-+		struct hw_asic_id *init);
-+
-+#endif /* __DAL_BONAIRE_CAPABILITY_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-index 0999372..2433d90 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-@@ -11,6 +11,18 @@ AMD_DAL_FILES += $(AMD_DAL_AUDIO)
- 
- 
- ###############################################################################
-+# DCE 8x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+AUDIO_DCE80 = audio_dce80.o hw_ctx_audio_dce80.o
-+
-+AMD_DAL_AUDIO_DCE80 = $(addprefix $(AMDDALPATH)/dc/audio/dce80/,$(AUDIO_DCE80))
-+
-+AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE80)
-+endif
-+
-+
-+###############################################################################
- # DCE 11x
- ###############################################################################
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index bfd6725..269c75d 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -30,6 +30,11 @@
- #include "audio.h"
- #include "hw_ctx_audio.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/audio_dce80.h"
-+#include "dce80/hw_ctx_audio_dce80.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/audio_dce110.h"
- #include "dce110/hw_ctx_audio_dce110.h"
-@@ -264,6 +269,10 @@ struct audio *dal_audio_create(
- 
- 	as = init_data->as;
- 	switch (dal_adapter_service_get_dce_version(as)) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		return dal_audio_create_dce80(init_data);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		return dal_audio_create_dce110(init_data);
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c
-new file mode 100644
-index 0000000..d6f437c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c
-@@ -0,0 +1,434 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "audio_dce80.h"
-+
-+/***** static functions  *****/
-+
-+static void destruct(struct audio_dce80 *audio)
-+{
-+	/*release memory allocated for hw_ctx -- allocated is initiated
-+	 *by audio_dce80 power_up
-+	 *audio->base->hw_ctx = NULL is done within hw-ctx->destroy
-+	 */
-+	if (audio->base.hw_ctx)
-+		audio->base.hw_ctx->funcs->destroy(&(audio->base.hw_ctx));
-+
-+	/* reset base_audio_block */
-+	dal_audio_destruct_base(&audio->base);
-+}
-+
-+static void destroy(struct audio **ptr)
-+{
-+	struct audio_dce80 *audio = NULL;
-+
-+	audio = container_of(*ptr, struct audio_dce80, base);
-+
-+	destruct(audio);
-+
-+	/* release memory allocated for audio_dce80*/
-+	dm_free(audio->base.ctx, audio);
-+	*ptr = NULL;
-+}
-+
-+
-+/* The inital call of hook function comes from audio object level.
-+ *The passing object handle "struct audio *audio" point to base object
-+ *already.There is not need to get base object from audio_dce80.
-+ */
-+
-+/**
-+* Setup
-+*
-+* @brief
-+*  setup Audio HW block, to be called by dal_audio_setup
-+*
-+* @param
-+*  engine_id         - HDMI engine id
-+*  pTiming          - CRTC timing
-+*  actualPixelClock - actual programmed pixel clock
-+*/
-+static enum audio_result setup(
-+	struct audio *audio,
-+	struct audio_output *output,
-+	struct audio_info *info)
-+{
-+	switch (output->signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* setup HDMI audio engine */
-+		audio->hw_ctx->funcs->setup_hdmi_audio(
-+			audio->hw_ctx, output->engine_id, &output->crtc_info);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* setup DP audio engine will be done at enable output */
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+
-+	/* setup Azalia block */
-+	audio->hw_ctx->funcs->setup_azalia(
-+		audio->hw_ctx,
-+		output->engine_id,
-+		output->signal,
-+		&output->crtc_info,
-+		&output->pll_info,
-+		info);
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* enable_output
-+*
-+* @brief
-+*  enable Audio HW block, to be called by dal_audio_enable_output
-+*
-+* @param
-+*  engine_id         - HDMI engine id
-+*/
-+static enum audio_result enable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/* enable audio output */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP: {
-+			/* setup DP audio engine */
-+			audio->hw_ctx->funcs->setup_dp_audio(
-+				audio->hw_ctx, engine_id);
-+			/* enabl DP audio packets will be done at unblank */
-+			audio->hw_ctx->funcs->enable_dp_audio(
-+				audio->hw_ctx, engine_id);
-+		}
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* route audio to VCE block */
-+		audio->hw_ctx->funcs->setup_vce_audio(audio->hw_ctx);
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* disable_output
-+*
-+* @brief
-+*  disable Audio HW block, to be called by dal_audio_disable_output
-+*
-+* @param
-+*  engine_id         - HDMI engine id
-+*/
-+static enum audio_result disable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* disable HDMI audio */
-+		audio->hw_ctx->
-+			funcs->disable_azalia_audio(
-+					audio->hw_ctx, engine_id);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP: {
-+			/* disable DP audio */
-+			audio->hw_ctx->funcs->disable_dp_audio(
-+				audio->hw_ctx, engine_id);
-+			audio->hw_ctx->funcs->disable_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		}
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* unmute
-+*
-+* @brief
-+*  unmute audio, to be called by dal_audio_unmute
-+*
-+* @param
-+*  engine_id         - engine id
-+*/
-+static enum audio_result unmute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_WIRELESS:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* unmute Azalia audio */
-+		audio->hw_ctx->funcs->unmute_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* mute
-+*
-+* @brief
-+*  mute audio, to be called  by dal_audio_nmute
-+*
-+* @param
-+*  engine_id         - engine id
-+*/
-+static enum audio_result mute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_WIRELESS:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* mute Azalia audio */
-+		audio->hw_ctx->funcs->mute_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* initialize
-+*
-+* @brief
-+*  Perform SW initialization - create audio hw context. Then do HW
-+*  initialization. this function is called at dal_audio_power_up.
-+*
-+* @param
-+*  NONE
-+*/
-+static enum audio_result initialize(
-+	struct audio *audio)
-+{
-+	uint8_t audio_endpoint_enum_id = 0;
-+
-+	audio_endpoint_enum_id = audio->id.enum_id;
-+
-+	/* HW CTX already create*/
-+	if (audio->hw_ctx != NULL)
-+		return AUDIO_RESULT_OK;
-+
-+	audio->hw_ctx = dal_audio_create_hw_ctx_audio_dce80(
-+			audio->ctx,
-+			audio_endpoint_enum_id);
-+
-+	if (audio->hw_ctx == NULL)
-+		return AUDIO_RESULT_ERROR;
-+
-+	/* override HW default settings */
-+	audio->hw_ctx->funcs->hw_initialize(audio->hw_ctx);
-+
-+	if (dal_adapter_service_is_feature_supported(FEATURE_LIGHT_SLEEP))
-+		audio->hw_ctx->funcs->disable_az_clock_gating(audio->hw_ctx);
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* enable multi channel split */
-+static void enable_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	audio->hw_ctx->funcs->setup_channel_splitting_mapping(
-+		audio->hw_ctx,
-+		engine_id,
-+		signal,
-+		audio_mapping, enable);
-+}
-+
-+/* get current multi channel split. */
-+static enum audio_result get_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	if (audio->hw_ctx->funcs->get_channel_splitting_mapping(
-+		audio->hw_ctx, engine_id, audio_mapping)) {
-+		return AUDIO_RESULT_OK;
-+	} else {
-+		return AUDIO_RESULT_ERROR;
-+	}
-+}
-+
-+/**
-+* SetUnsolicitedResponsePayload
-+*
-+* @brief
-+*  Set payload value for the unsolicited response
-+*/
-+static void set_unsolicited_response_payload(
-+	struct audio *audio,
-+	enum audio_payload payload)
-+{
-+	audio->hw_ctx->funcs->set_unsolicited_response_payload(
-+			audio->hw_ctx, payload);
-+}
-+
-+/**
-+* SetupAudioDTO
-+*
-+* @brief
-+*  Update audio source clock from hardware context.
-+*
-+* @param
-+*  determines if we have a HDMI link active
-+*  known pixel rate for HDMI
-+*  known DCPLL frequency
-+*/
-+static void setup_audio_wall_dto(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	audio->hw_ctx->funcs->setup_audio_wall_dto(
-+		audio->hw_ctx, signal, crtc_info, pll_info);
-+}
-+
-+/**
-+* GetSupportedFeatures
-+*
-+* @brief
-+*  options and features supported by Audio
-+*  returns supported engines, signals.
-+*  features are reported for HW audio/Azalia block rather then Audio object
-+*  itself the difference for DCE6.x is that MultiStream Audio is now supported
-+*
-+* @param
-+*  NONE
-+*/
-+static struct audio_feature_support get_supported_features(struct audio *audio)
-+{
-+	struct audio_feature_support afs = {0};
-+
-+	afs.ENGINE_DIGA = 1;
-+	afs.ENGINE_DIGB = 1;
-+	afs.ENGINE_DIGC = 1;
-+	afs.ENGINE_DIGD = 1;
-+	afs.ENGINE_DIGE = 1;
-+	afs.ENGINE_DIGF = 1;
-+	afs.ENGINE_DIGG = 1;
-+	afs.MULTISTREAM_AUDIO = 1;
-+
-+	return afs;
-+}
-+
-+static const struct audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup = setup,
-+	.enable_output = enable_output,
-+	.disable_output = disable_output,
-+	.unmute = unmute,
-+	.mute = mute,
-+	.initialize = initialize,
-+	.enable_channel_splitting_mapping =
-+		enable_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.setup_audio_wall_dto = setup_audio_wall_dto,
-+	.get_supported_features = get_supported_features,
-+};
-+
-+static bool construct(
-+	struct audio_dce80 *audio,
-+	const struct audio_init_data *init_data)
-+{
-+	struct audio *base = &audio->base;
-+
-+	/* base audio construct*/
-+	if (!dal_audio_construct_base(base, init_data))
-+		return false;
-+
-+	/*vtable methods*/
-+	base->funcs = &funcs;
-+	return true;
-+}
-+
-+
-+/* --- audio scope functions  --- */
-+
-+struct audio *dal_audio_create_dce80(
-+	const struct audio_init_data *init_data)
-+{
-+	/*allocate memory for audio_dce80 */
-+	struct audio_dce80 *audio = dm_alloc(init_data->ctx, sizeof(struct audio_dce80));
-+
-+	if (audio == NULL)
-+		return NULL;
-+
-+	/*pointer to base_audio_block of audio_dce80 ==> audio base object */
-+	if (construct(audio, init_data))
-+		return &audio->base;
-+
-+	 /*release memory allocated if fail */
-+	dm_free(init_data->ctx, audio);
-+	return NULL;
-+}
-+
-+/* Do not need expose construct_dce80 and destruct_dce80 becuase there is
-+ *derived object after dce80
-+ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h
-new file mode 100644
-index 0000000..4fef455
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h
-@@ -0,0 +1,41 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_AUDIO_80__
-+#define __DAL_AUDIO_80__
-+
-+#include "audio/audio.h"
-+#include "audio/hw_ctx_audio.h"
-+#include "audio/dce80/hw_ctx_audio_dce80.h"
-+
-+
-+struct audio_dce80 {
-+	struct audio base;
-+	/* dce-specific members are following */
-+	/* none */
-+};
-+
-+struct audio *dal_audio_create_dce80(const struct audio_init_data *init_data);
-+
-+#endif   /* __DAL_AUDIO_80__  */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-new file mode 100644
-index 0000000..521ad07
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-@@ -0,0 +1,1926 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+#include "../hw_ctx_audio.h"
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+#include "hw_ctx_audio_dce80.h"
-+
-+#define FROM_BASE(ptr) \
-+	container_of((ptr), struct hw_ctx_audio_dce80, base)
-+
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
-+#define DP_AUDIO_DTO_MODULE_WITHOUT_SS 360
-+#define DP_AUDIO_DTO_PHASE_WITHOUT_SS 24
-+
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUDIO_FRONT_END 0
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__REGISTER_PROGRAMMABLE 2
-+
-+#define FIRST_AUDIO_STREAM_ID 1
-+
-+static const uint32_t engine_offset[] = {
-+	0,
-+	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG3_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG4_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG5_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG6_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
-+};
-+/* --- static functions --- */
-+
-+/* static void dal_audio_destruct_hw_ctx_audio_dce80(
-+	struct hw_ctx_audio_dce80 *ctx);*/
-+
-+
-+static void destroy(
-+	struct hw_ctx_audio **ptr)
-+{
-+	struct hw_ctx_audio_dce80 *hw_ctx_dce80;
-+
-+	hw_ctx_dce80 = container_of(
-+		*ptr, struct hw_ctx_audio_dce80, base);
-+
-+	dal_audio_destruct_hw_ctx_audio_dce80(hw_ctx_dce80);
-+	/* release memory allocated for struct hw_ctx_audio_dce80 */
-+	dm_free((*ptr)->ctx, hw_ctx_dce80);
-+
-+	*ptr = NULL;
-+}
-+
-+
-+
-+/* ---  helpers --- */
-+
-+static void write_indirect_azalia_reg(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t reg_index,
-+	uint32_t reg_data)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+		set_reg_field_value(value, reg_index,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+		value = 0;
-+		set_reg_field_value(value, reg_data,
-+			AZALIA_F0_CODEC_ENDPOINT_DATA,
-+			AZALIA_ENDPOINT_REG_DATA);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	dal_logger_write(
-+		hw_ctx->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_AUDIO,
-+		"AUDIO:write_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, reg_data);
-+}
-+
-+static uint32_t read_indirect_azalia_reg(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t reg_index)
-+{
-+	uint32_t ret_val = 0;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+		set_reg_field_value(value, reg_index,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		ret_val = value;
-+	}
-+
-+	dal_logger_write(
-+		hw_ctx->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_AUDIO,
-+		"AUDIO:read_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, ret_val);
-+
-+	return ret_val;
-+}
-+
-+/* expose/not expose HBR capability to Audio driver */
-+static void set_high_bit_rate_capable(
-+	const struct hw_ctx_audio *hw_ctx,
-+	bool capable)
-+{
-+	uint32_t value = 0;
-+
-+	/* set high bit rate audio capable*/
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
-+
-+	set_reg_field_value(value, capable,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		HBR_CAPABLE);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		value);
-+}
-+
-+
-+
-+/* set HBR channnel count */
-+/*static void set_hbr_channel_count(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t hbr_channel_count)
-+{
-+	if (hbr_channel_count > 7)
-+		return;
-+
-+	{
-+		union AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL value;
-+
-+		value.u32All = dal_read_reg(
-+			mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+		value.bits.HBR_CHANNEL_COUNT = hbr_channel_count;
-+		dal_write_reg(
-+			mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL, value.u32All);
-+	}
-+}*/
-+
-+/* set compressed audio channel cound */
-+/*static void set_compressed_audio_channel_count(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t compressed_audio_ch_count)
-+{
-+	if (compressed_audio_ch_count > 7)
-+		return;
-+
-+	{
-+		union AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL value;
-+
-+		value.u32All = dal_read_reg(
-+			mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+		value.bits.COMPRESSED_CHANNEL_COUNT =
-+			compressed_audio_ch_count;
-+		dal_write_reg(
-+			mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+			value.u32All);
-+	}
-+}*/
-+
-+/* set video latency in in ms/2+1 */
-+static void set_video_latency(
-+	const struct hw_ctx_audio *hw_ctx,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if ((latency_in_ms < 0) || (latency_in_ms > 255))
-+		return;
-+
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		VIDEO_LIPSYNC);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+}
-+
-+
-+
-+
-+/* set audio latency in in ms/2+1 */
-+static void set_audio_latency(
-+	const struct hw_ctx_audio *hw_ctx,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if (latency_in_ms < 0)
-+		latency_in_ms = 0;
-+
-+	if (latency_in_ms > 255)
-+		latency_in_ms = 255;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		AUDIO_LIPSYNC);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+}
-+
-+
-+
-+/* enable HW/SW Sync */
-+/*static void enable_hw_sw_sync(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+		union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+	value.u32All = dal_read_reg(mmAZALIA_CYCLIC_BUFFER_SYNC);
-+	value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 1;
-+	dal_write_reg(mmAZALIA_CYCLIC_BUFFER_SYNC, value.u32All);
-+}*/
-+
-+
-+
-+/* disable HW/SW Sync */
-+/*static void disable_hw_sw_sync(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+	value.u32All = dal_read_reg(
-+		mmAZALIA_CYCLIC_BUFFER_SYNC);
-+	value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 0;
-+	dal_write_reg(
-+		mmAZALIA_CYCLIC_BUFFER_SYNC, value.u32All);
-+}*/
-+
-+
-+/* update hardware with software's current position in cyclic buffer */
-+/*static void update_sw_write_ptr(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t offset)
-+{
-+		union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER value;
-+
-+	value.u32All = dal_read_reg(
-+		mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER);
-+	value.bits.APPLICATION_POSITION_IN_CYCLIC_BUFFER = offset;
-+	dal_write_reg(
-+		mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER,
-+		value.u32All);
-+}*/
-+
-+
-+/* update Audio/Video association */
-+/*static void update_av_association(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	uint32_t displayId)
-+{
-+
-+}*/
-+
-+
-+
-+
-+
-+/* ---  hook functions --- */
-+
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info);
-+
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info);
-+
-+
-+
-+static void setup_audio_wall_dto(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	struct azalia_clock_info clock_info = { 0 };
-+
-+	uint32_t value = dm_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
-+
-+	/* TODO: GraphicsObject\inc\GraphicsObjectDefs.hpp(131):
-+	 *inline bool isHdmiSignal(SignalType signal)
-+	 *if (Signals::isHdmiSignal(signal))
-+	 */
-+	if (dc_is_hdmi_signal(signal)) {
-+		/*DTO0 Programming goal:
-+		-generate 24MHz, 128*Fs from 24MHz
-+		-use DTO0 when an active HDMI port is connected
-+		(optionally a DP is connected) */
-+
-+		/* calculate DTO settings */
-+		get_azalia_clock_info_hdmi(
-+			hw_ctx,
-+			crtc_info->requested_pixel_clock,
-+			crtc_info->calculated_pixel_clock,
-+			&clock_info);
-+
-+		/* On TN/SI, Program DTO source select and DTO select before
-+		programming DTO modulo and DTO phase. These bits must be
-+		programmed first, otherwise there will be no HDMI audio at boot
-+		up. This is a HW sequence change (different from old ASICs).
-+		Caution when changing this programming sequence.
-+
-+		HDMI enabled, using DTO0
-+		program master CRTC for DTO0 */
-+		{
-+			set_reg_field_value(value,
-+				pll_info->dto_source - DTO_SOURCE_ID0,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO0_SOURCE_SEL);
-+
-+			set_reg_field_value(value,
-+				0,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO_SOURCE, value);
-+		}
-+
-+		/* module */
-+		{
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_MODULE);
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_module,
-+				DCCG_AUDIO_DTO0_MODULE,
-+				DCCG_AUDIO_DTO0_MODULE);
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_MODULE, value);
-+		}
-+
-+		/* phase */
-+		{
-+			value = 0;
-+
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_PHASE);
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_phase,
-+				DCCG_AUDIO_DTO0_PHASE,
-+				DCCG_AUDIO_DTO0_PHASE);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_PHASE, value);
-+		}
-+
-+	} else {
-+		/*DTO1 Programming goal:
-+		-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-+		-default is to used DTO1, and switch to DTO0 when an audio
-+		master HDMI port is connected
-+		-use as default for DP
-+
-+		calculate DTO settings */
-+		get_azalia_clock_info_dp(
-+			hw_ctx,
-+			crtc_info->requested_pixel_clock,
-+			pll_info,
-+			&clock_info);
-+
-+		/* Program DTO select before programming DTO modulo and DTO
-+		phase. default to use DTO1 */
-+
-+		{
-+			set_reg_field_value(value, 1,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL);
-+			/*dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value)*/
-+
-+			/* Select 512fs for DP TODO: web register definition
-+			does not match register header file */
-+			set_reg_field_value(value, 1,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO2_USE_512FBR_DTO);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO_SOURCE, value);
-+		}
-+
-+		/* module */
-+		{
-+			value = 0;
-+
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_MODULE);
-+
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_module,
-+				DCCG_AUDIO_DTO1_MODULE,
-+				DCCG_AUDIO_DTO1_MODULE);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_MODULE, value);
-+		}
-+
-+		/* phase */
-+		{
-+			value = 0;
-+
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_PHASE);
-+
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_phase,
-+				DCCG_AUDIO_DTO1_PHASE,
-+				DCCG_AUDIO_DTO1_PHASE);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_PHASE, value);
-+		}
-+
-+		/* DAL2 code separate DCCG_AUDIO_DTO_SEL and
-+		DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different
-+		location. merge together should not hurt */
-+		/*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1;
-+		dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/
-+	}
-+}
-+
-+/* setup HDMI audio */
-+static void setup_hdmi_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	struct audio_clock_info audio_clock_info = {0};
-+	uint32_t max_packets_per_line;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* For now still do calculation, although this field is ignored when
-+	above HDMI_PACKET_GEN_VERSION set to 1 */
-+	max_packets_per_line =
-+		dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+			hw_ctx,
-+			crtc_info);
-+
-+	/* HDMI_AUDIO_PACKET_CONTROL */
-+	{
-+		addr =
-+			mmHDMI_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, max_packets_per_line,
-+			HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_PACKETS_PER_LINE);
-+		/* still apply RS600's default setting which is 1. */
-+		set_reg_field_value(value, 1,
-+			HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_DELAY_EN);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+			AFMT_AUDIO_PACKET_CONTROL,
-+			AFMT_60958_CS_UPDATE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 0,
-+				AFMT_AUDIO_PACKET_CONTROL2,
-+				AFMT_AUDIO_LAYOUT_OVRD);
-+
-+		/*Register field changed.*/
-+		set_reg_field_value(value, 0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_60958_OSF_OVRD);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* HDMI_ACR_PACKET_CONTROL */
-+	{
-+		addr = mmHDMI_ACR_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 1,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUTO_SEND);
-+
-+		/* Set HDMI_ACR_SOURCE to 0, to use hardwre
-+		 *  computed CTS values.*/
-+		set_reg_field_value(value, 0,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_SOURCE);
-+
-+		/* For now clear HDMI_ACR_AUDIO_PRIORITY =>ACR packet has
-+		higher priority over Audio Sample */
-+		set_reg_field_value(value, 0,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUDIO_PRIORITY);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Program audio clock sample/regeneration parameters */
-+	if (dal_audio_hw_ctx_get_audio_clock_info(
-+		hw_ctx,
-+		crtc_info->color_depth,
-+		crtc_info->requested_pixel_clock,
-+		crtc_info->calculated_pixel_clock,
-+		&audio_clock_info)) {
-+
-+		/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
-+		{
-+			addr = mmHDMI_ACR_32_0 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+			set_reg_field_value(value, audio_clock_info.cts_32khz,
-+				HDMI_ACR_32_0,
-+				HDMI_ACR_CTS_32);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
-+		{
-+			addr = mmHDMI_ACR_32_1 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_32khz,
-+				HDMI_ACR_32_1,
-+				HDMI_ACR_N_32);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
-+		{
-+			addr = mmHDMI_ACR_44_0 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.cts_44khz,
-+				HDMI_ACR_44_0,
-+				HDMI_ACR_CTS_44);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
-+		{
-+			addr = mmHDMI_ACR_44_1 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_44khz,
-+				HDMI_ACR_44_1,
-+				HDMI_ACR_N_44);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
-+		{
-+			addr = mmHDMI_ACR_48_0 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.cts_48khz,
-+				HDMI_ACR_48_0,
-+				HDMI_ACR_CTS_48);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
-+		{
-+			addr = mmHDMI_ACR_48_1 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_48khz,
-+				HDMI_ACR_48_1,
-+				HDMI_ACR_N_48);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* Video driver cannot know in advance which sample rate will
-+		be used by HD Audio driver
-+		HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
-+		programmed below in interruppt callback */
-+	} /* if */
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
-+	AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	{
-+		addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 1,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CHANNEL_NUMBER_L);
-+
-+		 /*HW default */
-+		set_reg_field_value(value, 0,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
-+	{
-+		addr = mmAFMT_60958_1 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 2,
-+			AFMT_60958_1,
-+			AFMT_60958_CS_CHANNEL_NUMBER_R);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/*AFMT_60958_2 now keep this settings until
-+	 *  Programming guide comes out*/
-+	{
-+		addr = mmAFMT_60958_2 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 3,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_2);
-+
-+		set_reg_field_value(value, 4,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_3);
-+
-+		set_reg_field_value(value, 5,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_4);
-+
-+		set_reg_field_value(value, 6,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_5);
-+
-+		set_reg_field_value(value, 7,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_6);
-+
-+		set_reg_field_value(value, 8,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_7);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+ /* setup DP audio */
-+static void setup_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/* --- DP Audio packet configurations --- */
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* ATP Configuration */
-+	{
-+		addr = mmDP_SEC_AUD_N + engine_offset[engine_id];
-+
-+		set_reg_field_value(value,
-+			DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT,
-+			DP_SEC_AUD_N,
-+			DP_SEC_AUD_N);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Async/auto-calc timestamp mode */
-+	{
-+		addr = mmDP_SEC_TIMESTAMP +
-+			engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		set_reg_field_value(value,
-+			DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC,
-+			DP_SEC_TIMESTAMP,
-+			DP_SEC_TIMESTAMP_MODE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* --- The following are the registers
-+	 *  copied from the SetupHDMI --- */
-+
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+			engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			1,
-+			AFMT_AUDIO_PACKET_CONTROL,
-+			AFMT_60958_CS_UPDATE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	{
-+		addr =
-+			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_LAYOUT_OVRD);
-+
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_60958_OSF_OVRD);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_INFOFRAME_CONTROL0 */
-+	{
-+		addr =
-+			mmAFMT_INFOFRAME_CONTROL0 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value,
-+			1,
-+			AFMT_INFOFRAME_CONTROL0,
-+			AFMT_AUDIO_INFO_UPDATE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	{
-+		addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+ /* setup VCE audio */
-+static void setup_vce_audio(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	/*TODO:
-+	const uint32_t addr = mmDOUT_DCE_VCE_CONTROL;
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+			addr);
-+
-+	set_reg_field_value(value,
-+		FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+		DOUT_DCE_VCE_CONTROL,
-+		DC_VCE_AUDIO_STREAM_SELECT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+			addr, value);*/
-+}
-+
-+/* enable Azalia audio */
-+static void enable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	uint32_t value;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	if (get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED) != 1)
-+		set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		value);
-+}
-+
-+
-+/* disable Azalia audio */
-+static void disable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	uint32_t value;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	set_reg_field_value(value, 0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		AUDIO_ENABLED);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		value);
-+}
-+
-+/* enable DP audio */
-+static void enable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+	uint32_t value;
-+
-+	/* Enable Audio packets */
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_ASP_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+
-+	/* Program the ATP and AIP next */
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_ATP_ENABLE);
-+
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_AIP_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+
-+	/* Program STREAM_ENABLE after all the other enables. */
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_STREAM_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* disable DP audio */
-+static void disable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+	uint32_t value;
-+
-+	/* Disable Audio packets */
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ASP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ATP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_AIP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ACM_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_STREAM_ENABLE);
-+
-+	/* This register shared with encoder info frame. Therefore we need to
-+	keep master enabled if at least on of the fields is not 0 */
-+	if (value != 0)
-+		set_reg_field_value(value, 1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+static void configure_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_info *audio_info)
-+{
-+	uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
-+	uint32_t value;
-+	uint32_t field = 0;
-+	enum audio_format_code audio_format_code;
-+	uint32_t format_index;
-+	uint32_t index;
-+	bool is_ac3_supported = false;
-+	bool is_audio_format_supported = false;
-+	union audio_sample_rates sample_rate;
-+	uint32_t strlen = 0;
-+
-+	/* Speaker Allocation */
-+	/*
-+	uint32_t value;
-+	uint32_t field = 0;*/
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
-+
-+	set_reg_field_value(value,
-+		speakers,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		SPEAKER_ALLOCATION);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		HDMI_CONNECTION);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		DP_CONNECTION);
-+
-+	field = get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+	field &= ~0x1;
-+
-+	set_reg_field_value(value,
-+		field,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+
-+	/* set audio for output signal */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		break;
-+	case SIGNAL_TYPE_WIRELESS: {
-+		/*LSB used for "is wireless" flag */
-+		field = 0;
-+		field = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+		field |= 0x1;
-+		set_reg_field_value(value,
-+			field,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		}
-+		break;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			DP_CONNECTION);
-+
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		value);
-+
-+	/*  Audio Descriptors   */
-+	/* pass through all formats */
-+	for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
-+			format_index++) {
-+		audio_format_code =
-+			(AUDIO_FORMAT_CODE_FIRST + format_index);
-+
-+		/* those are unsupported, skip programming */
-+		if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
-+			audio_format_code == AUDIO_FORMAT_CODE_DST)
-+			continue;
-+
-+		value = 0;
-+
-+		/* check if supported */
-+		is_audio_format_supported =
-+			dal_audio_hw_ctx_is_audio_format_supported(
-+				hw_ctx,
-+				audio_info,
-+				audio_format_code, &index);
-+
-+		if (is_audio_format_supported) {
-+			const struct audio_mode *audio_mode =
-+					&audio_info->modes[index];
-+			union audio_sample_rates sample_rates =
-+					audio_mode->sample_rates;
-+			uint8_t byte2 = audio_mode->max_bit_rate;
-+
-+			/* adjust specific properties */
-+			switch (audio_format_code) {
-+			case AUDIO_FORMAT_CODE_LINEARPCM: {
-+				dal_hw_ctx_audio_check_audio_bandwidth(
-+					hw_ctx,
-+					crtc_info,
-+					audio_mode->channel_count,
-+					signal,
-+					&sample_rates);
-+
-+				byte2 = audio_mode->sample_size;
-+
-+				set_reg_field_value(value,
-+				sample_rates.all,
-+		AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+				SUPPORTED_FREQUENCIES_STEREO);
-+
-+				}
-+				break;
-+			case AUDIO_FORMAT_CODE_AC3:
-+				is_ac3_supported = true;
-+				break;
-+			case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
-+			case AUDIO_FORMAT_CODE_DTS_HD:
-+			case AUDIO_FORMAT_CODE_MAT_MLP:
-+			case AUDIO_FORMAT_CODE_DST:
-+			case AUDIO_FORMAT_CODE_WMAPRO:
-+				byte2 = audio_mode->vendor_specific;
-+				break;
-+			default:
-+				break;
-+			}
-+
-+			/* fill audio format data */
-+			set_reg_field_value(value,
-+			audio_mode->channel_count - 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			MAX_CHANNELS);
-+
-+			set_reg_field_value(value,
-+			sample_rates.all,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			SUPPORTED_FREQUENCIES);
-+
-+			set_reg_field_value(value,
-+			byte2,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			DESCRIPTOR_BYTE_2);
-+
-+		} /* if */
-+
-+		write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +
-+		format_index,
-+		value);
-+	} /* for */
-+
-+	if (is_ac3_supported)
-+		dm_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
-+		0x05);
-+
-+	/* check for 192khz/8-Ch support for HBR requirements */
-+	sample_rate.all = 0;
-+	sample_rate.rate.RATE_192 = 1;
-+	dal_hw_ctx_audio_check_audio_bandwidth(
-+		hw_ctx,
-+		crtc_info,
-+		8,
-+		signal,
-+		&sample_rate);
-+
-+	set_high_bit_rate_capable(hw_ctx, sample_rate.rate.RATE_192);
-+
-+	/* Audio and Video Lipsync */
-+	set_video_latency(hw_ctx, audio_info->video_latency);
-+	set_audio_latency(hw_ctx, audio_info->audio_latency);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->manufacture_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		MANUFACTURER_ID);
-+
-+	set_reg_field_value(value, audio_info->product_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		PRODUCT_ID);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		value);
-+
-+
-+	value = 0;
-+
-+	/*get display name string length */
-+	while (audio_info->display_name[strlen++] != '\0') {
-+		if (strlen >=
-+		MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
-+			break;
-+		}
-+	set_reg_field_value(value, strlen,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		SINK_DESCRIPTION_LEN);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		value);
-+
-+
-+	/*
-+	*write the port ID:
-+	*PORT_ID0 = display index
-+	*PORT_ID1 = 16bit BDF
-+	*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
-+	*/
-+
-+	value = 0;
-+
-+	set_reg_field_value(value, audio_info->port_id[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		PORT_ID0);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->port_id[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		PORT_ID1);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		value);
-+
-+	/*write the 18 char monitor string */
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION0);
-+
-+	set_reg_field_value(value, audio_info->display_name[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION1);
-+
-+	set_reg_field_value(value, audio_info->display_name[2],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION2);
-+
-+	set_reg_field_value(value, audio_info->display_name[3],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION3);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		value);
-+
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[4],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION4);
-+
-+	set_reg_field_value(value, audio_info->display_name[5],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION5);
-+
-+	set_reg_field_value(value, audio_info->display_name[6],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION6);
-+
-+	set_reg_field_value(value, audio_info->display_name[7],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION7);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[8],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION8);
-+
-+	set_reg_field_value(value, audio_info->display_name[9],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION9);
-+
-+	set_reg_field_value(value, audio_info->display_name[10],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION10);
-+
-+	set_reg_field_value(value, audio_info->display_name[11],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION11);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[12],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION12);
-+
-+	set_reg_field_value(value, audio_info->display_name[13],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION13);
-+
-+	set_reg_field_value(value, audio_info->display_name[14],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION14);
-+
-+	set_reg_field_value(value, audio_info->display_name[15],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION15);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		value);
-+
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[16],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION16);
-+
-+	set_reg_field_value(value, audio_info->display_name[17],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION17);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		value);
-+
-+}
-+
-+/* setup Azalia HW block */
-+static void setup_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info,
-+	const struct audio_info *audio_info)
-+{
-+	uint32_t speakers = 0;
-+	uint32_t channels = 0;
-+
-+	if (audio_info == NULL)
-+		/* This should not happen.it does so we don't get BSOD*/
-+		return;
-+
-+	speakers = audio_info->flags.info.ALLSPEAKERS;
-+	channels = dal_audio_hw_ctx_speakers_to_channels(
-+		hw_ctx,
-+		audio_info->flags.speaker_flags).all;
-+
-+	/* setup the audio stream source select (audio -> dig mapping) */
-+	{
-+		const uint32_t addr =
-+			mmAFMT_AUDIO_SRC_CONTROL + engine_offset[engine_id];
-+
-+		uint32_t value = 0;
-+		/*convert one-based index to zero-based */
-+		set_reg_field_value(value,
-+			FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+			AFMT_AUDIO_SRC_CONTROL,
-+			AFMT_AUDIO_SRC_SELECT);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Channel allocation */
-+	{
-+		const uint32_t addr =
-+			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+		uint32_t value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value,
-+			channels,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_CHANNEL_ENABLE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	configure_azalia(hw_ctx, signal, crtc_info, audio_info);
-+}
-+
-+/* unmute audio */
-+static void unmute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+		engine_offset[engine_id];
-+
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 1,
-+		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* mute audio */
-+static void mute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+		engine_offset[engine_id];
-+
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* enable channel splitting mapping */
-+static void setup_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	uint32_t value = 0;
-+
-+	if ((audio_mapping == NULL || audio_mapping->u32all == 0) && enable)
-+		return;
-+
-+
-+	value = audio_mapping->u32all;
-+
-+	if (enable == false)
-+		/*0xFFFFFFFF;*/
-+		value = MULTI_CHANNEL_SPLIT_NO_ASSO_INFO;
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+		value);
-+}
-+
-+/* get current channel spliting */
-+static bool get_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	uint32_t value = 0;
-+
-+	if (audio_mapping == NULL)
-+		return false;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO);
-+
-+	/*0xFFFFFFFF*/
-+	if (get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+			ASSOCIATION_INFO) !=
-+			MULTI_CHANNEL_SPLIT_NO_ASSO_INFO) {
-+		uint32_t multi_channel01_enable = 0;
-+		uint32_t multi_channel23_enable = 0;
-+		uint32_t multi_channel45_enable = 0;
-+		uint32_t multi_channel67_enable = 0;
-+		/* get the one we set.*/
-+		audio_mapping->u32all = value;
-+
-+		/* check each enable status*/
-+		value = read_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE);
-+
-+		multi_channel01_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL01_ENABLE);
-+
-+		multi_channel23_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL23_ENABLE);
-+
-+		multi_channel45_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL45_ENABLE);
-+
-+		multi_channel67_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL67_ENABLE);
-+
-+		if (multi_channel01_enable == 0 &&
-+			multi_channel23_enable == 0 &&
-+			multi_channel45_enable == 0 &&
-+			multi_channel67_enable == 0)
-+			dal_logger_write(hw_ctx->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_COMPONENT_AUDIO,
-+				"Audio driver did not enable multi-channel\n");
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+/* set the payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum audio_payload payload)
-+{
-+	/* set the payload value for the unsolicited response
-+	 Jack presence is not required to be enabled */
-+	uint32_t value = 0;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE);
-+
-+	set_reg_field_value(value, payload,
-+		AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		UNSOLICITED_RESPONSE_PAYLOAD);
-+
-+	set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		UNSOLICITED_RESPONSE_FORCE);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		value);
-+}
-+
-+/* initialize HW state */
-+static void hw_initialize(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t stream_id = FROM_BASE(hw_ctx)->azalia_stream_id;
-+	uint32_t addr;
-+
-+	/* we only need to program the following registers once, so we only do
-+	it for the first audio stream.*/
-+	if (stream_id != FIRST_AUDIO_STREAM_ID)
-+		return;
-+
-+	/* Suport R5 - 32khz
-+	 * Suport R6 - 44.1khz
-+	 * Suport R7 - 48khz
-+	 */
-+	addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
-+	{
-+		uint32_t value;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 0x70,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
-+		AUDIO_RATE_CAPABILITIES);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/*Keep alive bit to verify HW block in BU. */
-+	addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
-+	{
-+		uint32_t value;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+		CLKSTOP);
-+
-+		set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+		EPSS);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+/* Assign GTC group and enable GTC value embedding */
-+static void enable_gtc_embedding_with_group(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t group_num,
-+	uint32_t audio_latency)
-+{
-+	/*need to replace the static number with variable */
-+	if (group_num <= 6) {
-+		uint32_t value = read_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+		set_reg_field_value(
-+			value,
-+			group_num,
-+			AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+		write_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			value);
-+
-+		/*update audio latency to LIPSYNC*/
-+		set_audio_latency(hw_ctx, audio_latency);
-+	} else {
-+		dal_logger_write(
-+			hw_ctx->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_COMPONENT_AUDIO,
-+			"GTC group number %d is too big",
-+			group_num);
-+	}
-+}
-+
-+ /* Disable GTC value embedding */
-+static void disable_gtc_embedding(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t value = 0;
-+
-+	value = read_indirect_azalia_reg(
-+	hw_ctx,
-+	ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+	set_reg_field_value(value, 0,
-+	AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+	PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+	AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+	PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+		value);
-+}
-+
-+ /* Disable Azalia Clock Gating Feature */
-+static void disable_az_clock_gating(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t value;
-+
-+	value = dm_read_reg(hw_ctx->ctx,
-+			mmAZALIA_CONTROLLER_CLOCK_GATING);
-+	set_reg_field_value(value, 0, AZALIA_CONTROLLER_CLOCK_GATING, ENABLE_CLOCK_GATING);
-+	dm_write_reg(hw_ctx->ctx,
-+			mmAZALIA_CONTROLLER_CLOCK_GATING, value);
-+}
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	if (azalia_clock_info == NULL)
-+		return false;
-+
-+	/* audio_dto_phase= 24 * 10,000;
-+	 *   24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase =
-+			24 * 10000;
-+
-+	/* audio_dto_module = PCLKFrequency * 10,000;
-+	 *  [khz] -> [100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+			actual_pixel_clock_in_khz * 10;
-+
-+	return true;
-+}
-+
-+
-+
-+/* search pixel clock value for Azalia DP Audio */
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	if (pll_info == NULL || azalia_clock_info == NULL)
-+		return false;
-+
-+	/* Reported dpDtoSourceClockInkhz value for
-+	 * DCE8 already adjusted for SS, do not need any
-+	 * adjustment here anymore
-+	 */
-+
-+	/*audio_dto_phase = 24 * 10,000;
-+	 * 24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase = 24 * 10000;
-+
-+	/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
-+	 *  [khz] ->[100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+		pll_info->dp_dto_source_clock_in_khz * 10;
-+
-+	return true;
-+}
-+
-+static const struct hw_ctx_audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup_audio_wall_dto =
-+		setup_audio_wall_dto,
-+	.setup_hdmi_audio =
-+		setup_hdmi_audio,
-+	.setup_dp_audio = setup_dp_audio,
-+	.setup_vce_audio = setup_vce_audio,
-+	.enable_azalia_audio =
-+		enable_azalia_audio,
-+	.disable_azalia_audio =
-+		disable_azalia_audio,
-+	.enable_dp_audio =
-+		enable_dp_audio,
-+	.disable_dp_audio =
-+		disable_dp_audio,
-+	.setup_azalia =
-+		setup_azalia,
-+	.disable_az_clock_gating =
-+		disable_az_clock_gating,
-+	.unmute_azalia_audio =
-+		unmute_azalia_audio,
-+	.mute_azalia_audio =
-+		mute_azalia_audio,
-+	.setup_channel_splitting_mapping =
-+		setup_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.hw_initialize =
-+		hw_initialize,
-+	.enable_gtc_embedding_with_group =
-+		enable_gtc_embedding_with_group,
-+	.disable_gtc_embedding =
-+		disable_gtc_embedding,
-+	.get_azalia_clock_info_hdmi =
-+		get_azalia_clock_info_hdmi,
-+	.get_azalia_clock_info_dp =
-+		get_azalia_clock_info_dp,
-+};
-+
-+bool dal_audio_construct_hw_ctx_audio_dce80(
-+	struct hw_ctx_audio_dce80 *hw_ctx,
-+	uint8_t azalia_stream_id,
-+	struct dc_context *ctx)
-+{
-+	struct hw_ctx_audio *base = &hw_ctx->base;
-+
-+	if (!dal_audio_construct_hw_ctx_audio(base))
-+		return false;
-+
-+	base->funcs = &funcs;
-+
-+	/* save audio endpoint or dig front for current dce80 audio object */
-+	hw_ctx->azalia_stream_id = azalia_stream_id;
-+	hw_ctx->base.ctx = ctx;
-+
-+	/* azalia audio endpoints register offsets. azalia is associated with
-+	DIG front. save AUDIO register offset */
-+	switch (azalia_stream_id) {
-+	case 1: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 2: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 3: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 4: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 5: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 6: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 7: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	default:
-+		/*DALASSERT_MSG(false,("Invalid Azalia stream ID!"));*/
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+
-+/* audio_dce80 is derived from audio directly, not via dce80  */
-+
-+void dal_audio_destruct_hw_ctx_audio_dce80(
-+	struct hw_ctx_audio_dce80 *hw_ctx_dce80)
-+{
-+	dal_audio_destruct_hw_ctx_audio(&hw_ctx_dce80->base);
-+}
-+
-+struct hw_ctx_audio *dal_audio_create_hw_ctx_audio_dce80(
-+	struct dc_context *ctx,
-+	uint32_t azalia_stream_id)
-+{
-+	/* allocate memory for struc hw_ctx_audio_dce80 */
-+	struct hw_ctx_audio_dce80 *hw_ctx_dce80 =
-+			dm_alloc(ctx, sizeof(struct hw_ctx_audio_dce80));
-+
-+	if (!hw_ctx_dce80) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	/*return pointer to hw_ctx_audio back to caller  -- audio object */
-+	if (dal_audio_construct_hw_ctx_audio_dce80(
-+			hw_ctx_dce80, azalia_stream_id, ctx))
-+		return &hw_ctx_dce80->base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(ctx, hw_ctx_dce80);
-+
-+	return NULL;
-+}
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h
-new file mode 100644
-index 0000000..1d0e00d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h
-@@ -0,0 +1,75 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_AUDIO_DCE80_H__
-+#define __DAL_HW_CTX_AUDIO_DCE80_H__
-+
-+#include "audio/hw_ctx_audio.h"
-+
-+struct hw_ctx_audio_dce80 {
-+	struct hw_ctx_audio base;
-+
-+	/* azalia stream id 1 based indexing, corresponding to audio GO enumId*/
-+	uint32_t azalia_stream_id;
-+
-+	/* azalia stream endpoint register offsets */
-+	struct azalia_reg_offsets az_mm_reg_offsets;
-+
-+	/* audio encoder block MM register offset -- associate with DIG FRONT */
-+};
-+
-+
-+/* ---  helpers ---  all static functions*/
-+/*set_high_bit_rate_capable
-+set_hbr_channel_count
-+set_compressed_audio_channel_count
-+set_video_latency
-+set_audio_latency
-+enable_hw_sw_sync
-+disable_hw_sw_sync
-+update_sw_write_ptr
-+update_av_association
-+write_indirect_azalia_reg
-+read_indirect_azalia_reg
-+*/
-+
-+/* in case dce83 may derived from dce80, expose dce80 constructor
-+*and destroy for derived */
-+bool dal_audio_construct_hw_ctx_audio_dce80(
-+	struct hw_ctx_audio_dce80 *hw_ctx,
-+	uint8_t azalia_stream_id,
-+	struct dc_context *ctx);
-+
-+void dal_audio_destruct_hw_ctx_audio_dce80(
-+	struct hw_ctx_audio_dce80 *hw_ctx);
-+
-+struct hw_ctx_audio *dal_audio_create_hw_ctx_audio_dce80(
-+	struct dc_context *ctx,
-+	uint32_t azalia_stream_id);
-+
-+#endif  /* __DAL_HW_CTX_AUDIO_DCE80_H__ */
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-index ddfe457..e5c8876 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-@@ -12,6 +12,19 @@ ifndef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- AMD_DAL_FILES := $(filter-out $(AMDDALPATH)/dc/bios/bios_parser_helper.o,$(AMD_DAL_FILES))
- endif
- 
-+###############################################################################
-+# DCE 8x
-+###############################################################################
-+# All DCE8.x are derived from DCE8.0, so 8.0 MUST be defined if ANY of
-+# DCE8.x is compiled.
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+
-+ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce80/bios_parser_helper_dce80.o
-+endif
-+
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o
-+endif
- 
- ###############################################################################
- # DCE 11x
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index 0aa227a..4e2bc90 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -38,7 +38,11 @@ bool dal_bios_parser_init_bios_helper(
- 	enum dce_version version)
- {
- 	switch (version) {
--
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		bp->bios_helper = dal_bios_parser_helper_dce80_get_table();
-+		return true;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index 1ad7455..c58b9bb 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -26,6 +26,10 @@
- #ifndef __DAL_BIOS_PARSER_HELPER_H__
- #define __DAL_BIOS_PARSER_HELPER_H__
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/bios_parser_helper_dce80.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/bios_parser_helper_dce110.h"
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index 566604e..85a5924 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -37,6 +37,11 @@ bool dal_bios_parser_init_cmd_tbl_helper(
- 	enum dce_version dce)
- {
- 	switch (dce) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		*h = dal_cmd_tbl_helper_dce80_get_table();
-+		return true;
-+#endif
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-index 4646cab..a462917 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-@@ -26,6 +26,9 @@
- #ifndef __DAL_COMMAND_TABLE_HELPER_H__
- #define __DAL_COMMAND_TABLE_HELPER_H__
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/command_table_helper_dce80.h"
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/command_table_helper_dce110.h"
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-new file mode 100644
-index 0000000..541a8c4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -0,0 +1,773 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "bif/bif_4_1_d.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/grph_object_defs.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+
-+#include "../bios_parser_helper.h"
-+
-+
-+static const uint8_t bios_scratch0_dacb_shift = 8;
-+
-+/**
-+ * detect_sink
-+ *
-+ * @brief
-+ *  read VBIOS scratch register to determine whether display for the specified
-+ *  signal is present and return the actual sink signal type
-+ *  For analog signals VBIOS load detection has to be called prior reading the
-+ *  register
-+ *
-+ * @param
-+ *  encoder - encoder id (to specify DAC)
-+ *  connector - connector id (to check CV on DIN)
-+ *  signal - signal (as display type) to check
-+ *
-+ * @return
-+ *  signal_type - actual (on the sink) signal type detected
-+ */
-+static enum signal_type detect_sink(
-+	struct dc_context *ctx,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type signal)
-+{
-+	enum signal_type sink = SIGNAL_TYPE_NONE;
-+	/* VBIOS does not provide bitfield definitions */
-+	uint32_t reg;
-+	/* DCE 8.0 does not support DAC2 */
-+	if (encoder.id == ENCODER_ID_INTERNAL_DAC2
-+		|| encoder.id == ENCODER_ID_INTERNAL_KLDSCP_DAC2) {
-+		BREAK_TO_DEBUGGER();
-+		/* TODO: DALASSERT_MSG(false, ("%s: DCE 8.0 Does not support
-+		 * DAC2!", __FUNCTION__)); */
-+		return SIGNAL_TYPE_NONE;
-+	}
-+
-+	reg = dm_read_reg(ctx,
-+			mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF);
-+
-+	/* In further processing we use DACB masks. If we want detect load on
-+	 * DACA, we need to shift
-+	 * the register so DACA bits will be in place of DACB bits
-+	 */
-+	if (encoder.id == ENCODER_ID_INTERNAL_DAC1
-+			|| encoder.id == ENCODER_ID_INTERNAL_KLDSCP_DAC1
-+			|| encoder.id == ENCODER_ID_EXTERNAL_NUTMEG
-+			|| encoder.id == ENCODER_ID_EXTERNAL_TRAVIS) {
-+		reg <<= bios_scratch0_dacb_shift;
-+	}
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_RGB:
-+		if (reg & ATOM_S0_CRT2_MASK)
-+			sink = SIGNAL_TYPE_RGB;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		if (reg & ATOM_S0_LCD1)
-+			sink = SIGNAL_TYPE_LVDS;
-+		break;
-+	case SIGNAL_TYPE_EDP:
-+		if (reg & ATOM_S0_LCD1)
-+			sink = SIGNAL_TYPE_EDP;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	return sink;
-+}
-+
-+static bool is_lid_open(struct dc_context *ctx)
-+{
-+	bool result = false;
-+
-+	/* VBIOS does not provide bitfield definitions */
-+	uint32_t reg;
-+
-+	reg = dm_read_reg(ctx,
-+		mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF);
-+
-+	/* lid is open if the bit is not set */
-+	result = !(reg & ATOM_S6_LID_STATE);
-+
-+	return result;
-+}
-+
-+static bool is_lid_status_changed(
-+	struct dc_context *ctx)
-+{
-+	bool result = false;
-+
-+	/* VBIOS does not provide bitfield definitions */
-+	uint32_t reg;
-+
-+	reg = dm_read_reg(ctx,
-+		mmBIOS_SCRATCH_6);
-+
-+	/* lid is open if the bit is not set */
-+	if (reg & ATOM_S6_LID_CHANGE) {
-+		reg &= ~ATOM_S6_LID_CHANGE;
-+		dm_write_reg(ctx,
-+				mmBIOS_SCRATCH_6, reg);
-+
-+		result = true;
-+	}
-+
-+	return result;
-+}
-+
-+static bool is_display_config_changed(
-+	struct dc_context *ctx)
-+{
-+	bool result = false;
-+
-+	/* VBIOS does not provide bitfield definitions */
-+	uint32_t reg;
-+
-+	reg = dm_read_reg(ctx,
-+		mmBIOS_SCRATCH_6);
-+
-+	/* lid is open if the bit is not set */
-+	if (reg & ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK) {
-+		reg &= ~ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK;
-+		dm_write_reg(ctx,
-+				mmBIOS_SCRATCH_6, reg);
-+
-+		result = true;
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * set_scratch_acc_mode_change
-+ *
-+ * @brief
-+ *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-+ *  VGA/non-Accelerated mode is set
-+ *
-+ * @param
-+ *  NONE
-+ */
-+static void set_scratch_acc_mode_change(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value |= ATOM_S6_ACC_MODE;
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+/**
-+ * is_accelerated_mode
-+ *
-+ * @brief
-+ *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-+ *  VGA/non-Accelerated mode is set
-+ *
-+ * @param
-+ *  NONE
-+ */
-+static bool is_accelerated_mode(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	return (value & ATOM_S6_ACC_MODE) ? true : false;
-+}
-+
-+static void set_scratch_critical_state(
-+	struct dc_context *ctx,
-+	bool state)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	if (state)
-+		value |= ATOM_S6_CRITICAL_STATE;
-+	else
-+		value &= ~ATOM_S6_CRITICAL_STATE;
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+/**
-+ * prepare_scratch_active_and_requested
-+ *
-+ * @brief
-+ *  prepare and update VBIOS scratch pad registers about active and requested
-+ *  displays
-+ *
-+ * @param
-+ * data - helper's shared data
-+ * enum controller_ild - controller Id
-+ * enum signal_type - signal type used on display
-+ * const struct connector_device_tag_info* - pointer to display type and enum id
-+ */
-+static void prepare_scratch_active_and_requested(
-+	struct dc_context *ctx,
-+	struct vbios_helper_data *data,
-+	enum controller_id id,
-+	enum signal_type s,
-+	const struct connector_device_tag_info *dev_tag)
-+{
-+	switch (s) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_DFP)
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP1;
-+				data->active |= ATOM_S3_DFP1_ACTIVE;
-+				break;
-+			case 2:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP2;
-+				data->active |= ATOM_S3_DFP2_ACTIVE;
-+				break;
-+			case 3:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP3;
-+				data->active |= ATOM_S3_DFP3_ACTIVE;
-+				break;
-+			case 4:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP4;
-+				data->active |= ATOM_S3_DFP4_ACTIVE;
-+				break;
-+			case 5:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP5;
-+				data->active |= ATOM_S3_DFP5_ACTIVE;
-+				break;
-+			case 6:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP6;
-+				data->active |= ATOM_S3_DFP6_ACTIVE;
-+				break;
-+			default:
-+				break;
-+			}
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_EDP:
-+		data->requested |= ATOM_S6_ACC_REQ_LCD1;
-+		data->active |= ATOM_S3_LCD1_ACTIVE;
-+		break;
-+	case SIGNAL_TYPE_RGB:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_CRT)
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				data->requested |= ATOM_S6_ACC_REQ_CRT1;
-+				data->active |= ATOM_S3_CRT1_ACTIVE;
-+				break;
-+			case 2:
-+				/* TODO: DALASSERT_MSG(false, ("%s: DCE 8.0 Does
-+				 *  not support DAC2!", __FUNCTION__));
-+				 */
-+			default:
-+				break;
-+			}
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+}
-+
-+static void set_scratch_active_and_requested(
-+	struct dc_context *ctx,
-+	struct vbios_helper_data *d)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_3;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
-+	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_6;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S6_ACC_REQ_MASK;
-+	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_5;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
-+	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	d->active = 0;
-+	d->requested = 0;
-+}
-+
-+/**
-+ * set_scratch_connected
-+ *
-+ * @brief
-+ *    update BIOS_SCRATCH_0 register about connected displays
-+ *
-+ * @param
-+ * bool - update scratch register or just prepare info to be updated
-+ * bool - connection state
-+ * const struct connector_device_tag_info * - pointer to device type and enum ID
-+ */
-+static void set_scratch_connected(
-+	struct dc_context *ctx,
-+	struct graphics_object_id id,
-+	bool connected,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t update = 0;
-+
-+	switch (device_tag->dev_id.device_type) {
-+	case DEVICE_TYPE_LCD:
-+		/* For LCD VBIOS will update LCD Panel connected bit always and
-+		 * Lid state bit based on SBIOS info do not do anything here
-+		 * for LCD
-+		 */
-+		break;
-+	case DEVICE_TYPE_CRT:
-+		switch (device_tag->dev_id.enum_id) {
-+		case 1:
-+			update |= ATOM_S0_CRT1_COLOR;
-+			break;
-+		case 2:
-+			update |= ATOM_S0_CRT2_COLOR;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_DFP:
-+		switch (device_tag->dev_id.enum_id) {
-+		case 1:
-+			update |= ATOM_S0_DFP1;
-+			break;
-+		case 2:
-+			update |= ATOM_S0_DFP2;
-+			break;
-+		case 3:
-+			update |= ATOM_S0_DFP3;
-+			break;
-+		case 4:
-+			update |= ATOM_S0_DFP4;
-+			break;
-+		case 5:
-+			update |= ATOM_S0_DFP5;
-+			break;
-+		case 6:
-+			update |= ATOM_S0_DFP6;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CV:
-+		/* DCE 8.0 does not support CV,
-+		 * so don't do anything */
-+		break;
-+
-+	case DEVICE_TYPE_TV:
-+		/* For TV VBIOS will update S-Video or
-+		 * Composite scratch bits on DAL_LoadDetect
-+		 * when called by driver, do not do anything
-+		 * here for TV
-+		 */
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+	/* update scratch register */
-+	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	if (connected)
-+		value |= update;
-+	else
-+		value &= ~update;
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void set_scratch_lcd_scale(
-+	struct dc_context *ctx,
-+	enum lcd_scale lcd_scale_request)
-+{
-+	uint32_t reg;
-+
-+	reg = dm_read_reg(ctx, mmBIOS_SCRATCH_6);
-+
-+	reg &= ~ATOM_S6_REQ_LCD_EXPANSION_FULL;
-+	reg &= ~ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO;
-+
-+	switch (lcd_scale_request) {
-+	case LCD_SCALE_FULLPANEL:
-+		/* set Lcd Scale to Full Panel Mode */
-+		reg |= ATOM_S6_REQ_LCD_EXPANSION_FULL;
-+		break;
-+	case LCD_SCALE_ASPECTRATIO:
-+		/* set Lcd Scale to Aspect-Ratio Mode */
-+		reg |= ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO;
-+		break;
-+	case LCD_SCALE_NONE:
-+	default:
-+		break;
-+	}
-+
-+	dm_write_reg(ctx, mmBIOS_SCRATCH_6, reg);
-+}
-+
-+static enum lcd_scale get_scratch_lcd_scale(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	if (value & ATOM_S6_REQ_LCD_EXPANSION_FULL)
-+		return LCD_SCALE_FULLPANEL;
-+	else if (value & ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO)
-+		return LCD_SCALE_ASPECTRATIO;
-+	else
-+		return LCD_SCALE_NONE;
-+}
-+
-+static uint32_t fmt_control(
-+	struct dc_context *ctx,
-+	enum controller_id id,
-+	uint32_t *value)
-+{
-+	uint32_t result = 0;
-+	uint32_t reg;
-+
-+	switch (id) {
-+	case CONTROLLER_ID_D0:
-+		reg = mmFMT0_FMT_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		reg = mmFMT1_FMT_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		reg = mmFMT2_FMT_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D3:
-+		reg = mmFMT3_FMT_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D4:
-+		reg = mmFMT4_FMT_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D5:
-+		reg = mmFMT5_FMT_CONTROL;
-+		break;
-+	default:
-+		return result;
-+	}
-+
-+	if (value != NULL)
-+		dm_write_reg(ctx, reg, *value);
-+	else
-+		result = dm_read_reg(ctx, reg);
-+
-+	return result;
-+}
-+
-+static uint32_t fmt_bit_depth_control(
-+	struct dc_context *ctx,
-+	enum controller_id id,
-+	uint32_t *value)
-+{
-+	uint32_t addr;
-+
-+	switch (id) {
-+	case CONTROLLER_ID_D0:
-+		addr = mmFMT0_FMT_BIT_DEPTH_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		addr = mmFMT1_FMT_BIT_DEPTH_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		addr = mmFMT2_FMT_BIT_DEPTH_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D3:
-+		addr = mmFMT3_FMT_BIT_DEPTH_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D4:
-+		addr = mmFMT4_FMT_BIT_DEPTH_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D5:
-+		addr = mmFMT5_FMT_BIT_DEPTH_CONTROL;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return 0;
-+	}
-+
-+	if (value != NULL) {
-+		dm_write_reg(ctx, addr, *value);
-+		return 0;
-+	} else {
-+		return dm_read_reg(ctx, addr);
-+	}
-+}
-+
-+/**
-+ * Read various BIOS Scratch registers and put the resulting information into a
-+ * PowerPlay internal structure (which is not dependent on register bit layout).
-+ */
-+static void get_bios_event_info(
-+	struct dc_context *ctx,
-+	struct bios_event_info *info)
-+{
-+	uint32_t s2, s6;
-+	uint32_t clear_mask;
-+
-+	dm_memset(info, 0, sizeof(struct bios_event_info));
-+
-+	/* Handle backlight event ONLY. PPLib still handling other events */
-+	s6 = dm_read_reg(ctx, mmBIOS_SCRATCH_6);
-+
-+	clear_mask = s6 & (ATOM_S6_VRI_BRIGHTNESS_CHANGE);
-+
-+	dm_write_reg(ctx,
-+			mmBIOS_SCRATCH_6, s6 & ~clear_mask);
-+
-+	s2 = dm_read_reg(ctx, mmBIOS_SCRATCH_2);
-+
-+	info->backlight_level = (s2 & ATOM_S2_CURRENT_BL_LEVEL_MASK)
-+		>> ATOM_S2_CURRENT_BL_LEVEL_SHIFT;
-+	info->backlight_changed = (0 != (s6 & ATOM_S6_VRI_BRIGHTNESS_CHANGE));
-+}
-+
-+static void take_backlight_control(
-+	struct dc_context *ctx,
-+	bool control)
-+{
-+	const uint32_t addr = mmBIOS_SCRATCH_2;
-+
-+	uint32_t s2;
-+
-+	s2 = dm_read_reg(ctx, addr);
-+
-+	if (control)
-+		s2 |= ATOM_S2_VRI_BRIGHT_ENABLE;
-+	else
-+		s2 &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
-+
-+	dm_write_reg(ctx, addr, s2);
-+}
-+
-+static uint32_t get_requested_backlight_level(
-+	struct dc_context *ctx)
-+{
-+	uint32_t s2;
-+
-+	s2 = dm_read_reg(ctx, mmBIOS_SCRATCH_2);
-+
-+	return (s2 & ATOM_S2_CURRENT_BL_LEVEL_MASK)
-+			>> ATOM_S2_CURRENT_BL_LEVEL_SHIFT;
-+}
-+
-+static void update_requested_backlight_level(
-+	struct dc_context *ctx,
-+	uint32_t backlight_8bit)
-+{
-+	const uint32_t addr = mmBIOS_SCRATCH_2;
-+
-+	uint32_t s2;
-+
-+	s2 = dm_read_reg(ctx, addr);
-+
-+	s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
-+	backlight_8bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK
-+			>> ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
-+	s2 |= (backlight_8bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
-+
-+	dm_write_reg(ctx, addr, s2);
-+}
-+
-+static bool is_active_display(
-+	struct dc_context *ctx,
-+	enum signal_type signal,
-+	const struct connector_device_tag_info *dev_tag)
-+{
-+	uint32_t active = 0;
-+
-+	uint32_t reg;
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_DFP) {
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				active = ATOM_S3_DFP1_ACTIVE;
-+				break;
-+			case 2:
-+				active = ATOM_S3_DFP2_ACTIVE;
-+				break;
-+			case 3:
-+				active = ATOM_S3_DFP3_ACTIVE;
-+				break;
-+			case 4:
-+				active = ATOM_S3_DFP4_ACTIVE;
-+				break;
-+			case 5:
-+				active = ATOM_S3_DFP5_ACTIVE;
-+				break;
-+
-+			case 6:
-+				active = ATOM_S3_DFP6_ACTIVE;
-+				break;
-+			default:
-+				break;
-+			}
-+		}
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_EDP:
-+		active = ATOM_S3_LCD1_ACTIVE;
-+		break;
-+	case SIGNAL_TYPE_RGB:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_CRT)
-+			active = ATOM_S3_CRT1_ACTIVE;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	reg = dm_read_reg(ctx, mmBIOS_SCRATCH_3);
-+	reg &= ATOM_S3_DEVICE_ACTIVE_MASK;
-+
-+	return 0 != (active & reg);
-+}
-+
-+static enum controller_id get_embedded_display_controller_id(
-+	struct dc_context *ctx)
-+{
-+	uint32_t reg;
-+
-+	reg = dm_read_reg(ctx, mmBIOS_SCRATCH_3);
-+
-+	if (ATOM_S3_LCD1_ACTIVE & reg)
-+		return (reg & ATOM_S3_LCD1_CRTC_ACTIVE) ?
-+			CONTROLLER_ID_D1 : CONTROLLER_ID_D0;
-+
-+	return CONTROLLER_ID_UNDEFINED;
-+}
-+
-+static uint32_t get_embedded_display_refresh_rate(
-+	struct dc_context *ctx)
-+{
-+	uint32_t result = 0;
-+
-+	uint32_t reg_3;
-+
-+	reg_3 = dm_read_reg(ctx, mmBIOS_SCRATCH_3);
-+
-+	if (ATOM_S3_LCD1_ACTIVE & reg_3) {
-+		uint32_t reg_4;
-+
-+		reg_4 = dm_read_reg(ctx,
-+				mmBIOS_SCRATCH_4);
-+
-+		result = (reg_4 & ATOM_S4_LCD1_REFRESH_MASK)
-+				>> ATOM_S4_LCD1_REFRESH_SHIFT;
-+	}
-+
-+	return result;
-+}
-+
-+static const struct bios_parser_helper bios_parser_helper_funcs = {
-+	.detect_sink = detect_sink,
-+	.fmt_bit_depth_control = fmt_bit_depth_control,
-+	.fmt_control = fmt_control,
-+	.get_bios_event_info = get_bios_event_info,
-+	.get_embedded_display_controller_id =
-+		get_embedded_display_controller_id,
-+	.get_embedded_display_refresh_rate =
-+		get_embedded_display_refresh_rate,
-+	.get_requested_backlight_level = get_requested_backlight_level,
-+	.get_scratch_lcd_scale = get_scratch_lcd_scale,
-+	.is_accelerated_mode = is_accelerated_mode,
-+	.is_active_display = is_active_display,
-+	.is_display_config_changed = is_display_config_changed,
-+	.is_lid_open = is_lid_open,
-+	.is_lid_status_changed = is_lid_status_changed,
-+	.prepare_scratch_active_and_requested =
-+		prepare_scratch_active_and_requested,
-+	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
-+	.set_scratch_active_and_requested = set_scratch_active_and_requested,
-+	.set_scratch_connected = set_scratch_connected,
-+	.set_scratch_critical_state = set_scratch_critical_state,
-+	.set_scratch_lcd_scale = set_scratch_lcd_scale,
-+	.take_backlight_control = take_backlight_control,
-+	.update_requested_backlight_level = update_requested_backlight_level,
-+};
-+
-+const struct bios_parser_helper *dal_bios_parser_helper_dce80_get_table()
-+{
-+	return &bios_parser_helper_funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h
-new file mode 100644
-index 0000000..db671be
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_HELPER_DCE80_H__
-+#define __DAL_BIOS_PARSER_HELPER_DCE80_H__
-+
-+struct bios_parser_helper;
-+
-+const struct bios_parser_helper *dal_bios_parser_helper_dce80_get_table(void);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.c
-new file mode 100644
-index 0000000..d725c4c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.c
-@@ -0,0 +1,355 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/grph_object_defs.h"
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+
-+#include "../command_table_helper.h"
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_ID_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL1:
-+			*atom_pll_id = ATOM_PPLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL2:
-+			*atom_pll_id = ATOM_PPLL2;
-+			break;
-+		case CLOCK_SOURCE_ID_EXTERNAL:
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_EXT_PLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			/* for VCE encoding,
-+			 * we need to pass in ATOM_PPLL_INVALID
-+			 */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			/* When programming DP DTO PLL ID should be invalid */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			BREAK_TO_DEBUGGER(); /* check when this will happen! */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel >> 4;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	}
-+
-+	return atom_dig_encoder_sel;
-+}
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+		clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.assign_control_parameter =
-+		dal_cmd_table_helper_assign_control_parameter,
-+	.clock_source_id_to_ref_clk_src =
-+		dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
-+	.transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
-+	.encoder_mode_bp_to_atom =
-+		dal_cmd_table_helper_encoder_mode_bp_to_atom,
-+};
-+
-+const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table()
-+{
-+	return &command_table_helper_funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.h b/drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.h
-new file mode 100644
-index 0000000..e675c35
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/command_table_helper_dce80.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE80_H__
-+#define __DAL_COMMAND_TABLE_HELPER_DCE80_H__
-+
-+struct command_table_helper;
-+
-+const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-index db4f131..133b174 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -25,6 +25,9 @@
- #include "dm_services.h"
- #include "core_types.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/dce80_hw_sequencer.h"
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce100/dce100_hw_sequencer.h"
- #endif
-@@ -40,6 +43,10 @@ bool dc_construct_hw_sequencer(
- 
- 	switch (dce_ver)
- 	{
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		return dce80_hw_sequencer_construct(dc);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		return dce100_hw_sequencer_construct(dc);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 70bf935..80fb823 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -31,6 +31,9 @@
- #include "opp.h"
- #include "transform.h"
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/dce80_resource.h"
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce100/dce100_resource.h"
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
-new file mode 100644
-index 0000000..efe001f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
-@@ -0,0 +1,17 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_link_encoder.o dce80_opp.o \
-+	dce80_opp_formatter.o dce80_opp_regamma.o dce80_stream_encoder.o \
-+	dce80_timing_generator.o dce80_transform.o dce80_transform_gamut.o \
-+	dce80_transform_scl.o dce80_opp_csc.o\
-+	dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \
-+	dce80_transform_bit_depth.o dce80_resource.o
-+
-+AMD_DAL_DCE80 = $(addprefix $(AMDDALPATH)/dc/dce80/,$(DCE80))
-+
-+AMD_DAL_FILES += $(AMD_DAL_DCE80)
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-new file mode 100644
-index 0000000..a3b767e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-@@ -0,0 +1,867 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+#include "gmc/gmc_7_1_sh_mask.h"
-+#include "gmc/gmc_7_1_d.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/adapter_service_interface.h"
-+
-+#include "dce80_compressor.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + cp80->offsets.dcp_offset)
-+#define DMIF_REG(reg)\
-+	(reg + cp80->offsets.dmif_offset)
-+
-+static const struct dce80_compressor_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG3_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG4_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG5_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+}
-+};
-+
-+static const uint32_t dce8_one_lpt_channel_max_resolution = 2048 * 1200;
-+
-+enum fbc_idle_force {
-+	/* Bit 0 - Display registers updated */
-+	FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
-+
-+	/* Bit 2 - FBC_GRPH_COMP_EN register updated */
-+	FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
-+	/* Bit 3 - FBC_SRC_SEL register updated */
-+	FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
-+	/* Bit 4 - FBC_MIN_COMPRESSION register updated */
-+	FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
-+	/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-+	FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
-+	/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-+	FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
-+	/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-+	FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
-+
-+	/* Bit 24 - Memory write to region 0 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
-+	/* Bit 25 - Memory write to region 1 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
-+	/* Bit 26 - Memory write to region 2 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
-+	/* Bit 27 - Memory write to region 3 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
-+
-+	/* Bit 28 - Memory write from any client other than MCIF */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
-+	/* Bit 29 - CG statics screen signal is inactive */
-+	FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
-+};
-+
-+static uint32_t lpt_size_alignment(struct dce80_compressor *cp80)
-+{
-+	/*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-+	return cp80->base.raw_size * cp80->base.banks_num *
-+		cp80->base.dram_channels_num;
-+}
-+
-+static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
-+	uint32_t lpt_control)
-+{
-+	/*LPT MC Config */
-+	if (cp80->base.options.bits.LPT_MC_CONFIG == 1) {
-+		/* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-+		 * 00 - 1 CHANNEL
-+		 * 01 - 2 CHANNELS
-+		 * 02 - 4 OR 6 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ)
-+		 * 03 - 8 OR 12 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ) */
-+		switch (cp80->base.dram_channels_num) {
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		case 1:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp80->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT NUM_PIPES!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LPT NUM_BANKS is in
-+		 * GRPH_CONTROL.GRPH_NUM_BANKS register field
-+		 * Specifies the number of memory banks for tiling
-+		 * purposes. Only applies to 2D and 3D tiling modes.
-+		 * POSSIBLE VALUES:
-+		 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-+		 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-+		 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-+		 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-+		switch (cp80->base.banks_num) {
-+		case 16:
-+			set_reg_field_value(
-+				lpt_control,
-+				3,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 8:
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 4:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp80->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT NUM_BANKS!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping is in DMIF_ADDR_CALC.
-+		 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-+		 * Carrizo specifies the memory interleave per pipe.
-+		 * It effectively specifies the location of pipe bits in
-+		 * the memory address.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
-+		 * interleave
-+		 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
-+		 * interleave
-+		 */
-+		switch (cp80->base.channel_interleave_size) {
-+		case 256: /*256B */
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		case 512: /*512B */
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp80->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT INTERLEAVE_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LOW_POWER_TILING_ROW_SIZE is in
-+		 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
-+		 * for Carrizo. Specifies the size of dram row in bytes.
-+		 * This should match up with NOOFCOLS field in
-+		 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
-+		 * This register DMIF_ADDR_CALC is not used by the
-+		 * hardware as it is only used for addrlib assertions.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
-+		 * boundary
-+		 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
-+		 * boundary
-+		 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
-+		 * boundary */
-+		switch (cp80->base.raw_size) {
-+		case 4096: /*4 KB */
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 2048:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 1024:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp80->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT ROW_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+	} else {
-+		dal_logger_write(
-+			cp80->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: LPT MC Configuration is not provided",
-+			__func__);
-+	}
-+
-+	return lpt_control;
-+}
-+
-+
-+
-+static bool is_source_bigger_than_epanel_size(
-+	struct dce80_compressor *cp80,
-+	uint32_t source_view_width,
-+	uint32_t source_view_height)
-+{
-+	if (cp80->base.embedded_panel_h_size != 0 &&
-+		cp80->base.embedded_panel_v_size != 0 &&
-+		((source_view_width * source_view_height) >
-+		(cp80->base.embedded_panel_h_size *
-+			cp80->base.embedded_panel_v_size)))
-+		return true;
-+
-+	return false;
-+}
-+
-+static uint32_t align_to_chunks_number_per_line(
-+	struct dce80_compressor *cp80,
-+	uint32_t pixels)
-+{
-+	return 256 * ((pixels + 255) / 256);
-+}
-+
-+static void wait_for_fbc_state_changed(
-+	struct dce80_compressor *cp80,
-+	bool enabled)
-+{
-+	uint8_t counter = 0;
-+	uint32_t addr = mmFBC_STATUS;
-+	uint32_t value;
-+
-+	while (counter < 10) {
-+		value = dm_read_reg(cp80->base.ctx, addr);
-+		if (get_reg_field_value(
-+			value,
-+			FBC_STATUS,
-+			FBC_ENABLE_STATUS) == enabled)
-+			break;
-+		dm_delay_in_microseconds(cp80->base.ctx, 10);
-+		counter++;
-+	}
-+
-+	if (counter == 10) {
-+		dal_logger_write(
-+			cp80->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: wait counter exceeded, changes to HW not applied",
-+			__func__);
-+	}
-+}
-+
-+void dce80_compressor_power_up_fbc(struct compressor *compressor)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmFBC_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
-+	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_MODE;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
-+	/*                    1 ==> 4:1 */
-+	/*                    2 ==> 8:1 */
-+	/*                  0xF ==> 1:1 */
-+	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
-+
-+	value = 0;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+
-+	value = 0xFFFFFF;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+}
-+
-+void dce80_compressor_enable_fbc(
-+	struct compressor *compressor,
-+	uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		(compressor->options.bits.DUMMY_BACKEND == 0) &&
-+		(!dce80_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
-+		(!is_source_bigger_than_epanel_size(
-+			cp80,
-+			params->source_view_width,
-+			params->source_view_height))) {
-+
-+		uint32_t addr;
-+		uint32_t value;
-+
-+		/* Before enabling FBC first need to enable LPT if applicable
-+		 * LPT state should always be changed (enable/disable) while FBC
-+		 * is disabled */
-+		if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
-+			(params->source_view_width *
-+				params->source_view_height <=
-+				dce8_one_lpt_channel_max_resolution)) {
-+			dce80_compressor_enable_lpt(compressor);
-+		}
-+
-+		addr = mmFBC_CNTL;
-+		value = dm_read_reg(compressor->ctx, addr);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		set_reg_field_value(
-+			value,
-+			params->inst,
-+			FBC_CNTL, FBC_SRC_SEL);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		/* Keep track of enum controller_id FBC is attached to */
-+		compressor->is_enabled = true;
-+		compressor->attached_inst = params->inst;
-+		cp80->offsets = reg_offsets[params->inst - 1];
-+
-+		/*Toggle it as there is bug in HW */
-+		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		wait_for_fbc_state_changed(cp80, true);
-+	}
-+}
-+
-+void dce80_compressor_disable_fbc(struct compressor *compressor)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		dce80_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
-+		uint32_t reg_data;
-+		/* Turn off compression */
-+		reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+
-+		/* Reset enum controller_id to undefined */
-+		compressor->attached_inst = 0;
-+		compressor->is_enabled = false;
-+
-+		/* Whenever disabling FBC make sure LPT is disabled if LPT
-+		 * supported */
-+		if (compressor->options.bits.LPT_SUPPORT)
-+			dce80_compressor_disable_lpt(compressor);
-+
-+		wait_for_fbc_state_changed(cp80, false);
-+	}
-+}
-+
-+bool dce80_compressor_is_fbc_enabled_in_hw(
-+	struct compressor *compressor,
-+	uint32_t *inst)
-+{
-+	/* Check the hardware register */
-+	uint32_t value;
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
-+	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
-+		if (inst != NULL)
-+			*inst = compressor->attached_inst;
-+		return true;
-+	}
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+	if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
-+		if (inst != NULL)
-+			*inst =	compressor->attached_inst;
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool dce80_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
-+{
-+	/* Check the hardware register */
-+	uint32_t value = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	return get_reg_field_value(
-+		value,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+}
-+
-+void dce80_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t value = 0;
-+	uint32_t fbc_pitch = 0;
-+	uint32_t compressed_surf_address_low_part =
-+		compressor->compr_surface_address.addr.low_part;
-+
-+	/* Clear content first. */
-+	dm_write_reg(
-+		compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		0);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
-+
-+	if (compressor->options.bits.LPT_SUPPORT) {
-+		uint32_t lpt_alignment = lpt_size_alignment(cp80);
-+
-+		if (lpt_alignment != 0) {
-+			compressed_surf_address_low_part =
-+				((compressed_surf_address_low_part
-+					+ (lpt_alignment - 1)) / lpt_alignment)
-+					* lpt_alignment;
-+		}
-+	}
-+
-+	/* Write address, HIGH has to be first. */
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		compressor->compr_surface_address.addr.high_part);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
-+		compressed_surf_address_low_part);
-+
-+	fbc_pitch = align_to_chunks_number_per_line(
-+		cp80,
-+		params->source_view_width);
-+
-+	if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
-+		fbc_pitch = fbc_pitch / 8;
-+	else
-+		dal_logger_write(
-+			compressor->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: Unexpected DCE8 compression ratio",
-+			__func__);
-+
-+	/* Clear content first. */
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+
-+	/* Write FBC Pitch. */
-+	set_reg_field_value(
-+		value,
-+		fbc_pitch,
-+		GRPH_COMPRESS_PITCH,
-+		GRPH_COMPRESS_PITCH);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+
-+}
-+
-+void dce80_compressor_disable_lpt(struct compressor *compressor)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t inx;
-+
-+	/* Disable all pipes LPT Stutter */
-+	for (inx = 0; inx < 3; inx++) {
-+		value =
-+			dm_read_reg(
-+				compressor->ctx,
-+				DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+			STUTTER_ENABLE_NONLPTCH);
-+		dm_write_reg(
-+			compressor->ctx,
-+			DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
-+			value);
-+	}
-+
-+	/* Disable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Clear selection of Channel(s) containing Compressed Surface */
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0xFFFFFFFF,
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
-+}
-+
-+void dce80_compressor_enable_lpt(struct compressor *compressor)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t value_control;
-+	uint32_t channels;
-+
-+	/* Enable LPT Stutter from Display pipe */
-+	value = dm_read_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
-+
-+	/* Selection of Channel(s) containing Compressed Surface: 0xfffffff
-+	 * will disable LPT.
-+	 * STCTRL_LPT_TARGETn corresponds to channel n. */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value_control = dm_read_reg(compressor->ctx, addr);
-+	channels = get_reg_field_value(value_control,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		channels + 1, /* not mentioned in programming guide,
-+				but follow DCE8.1 */
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Enable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce80_compressor_program_lpt_control(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t rows_per_channel;
-+	uint32_t lpt_alignment;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+	uint32_t lpt_control = 0;
-+
-+	if (!compressor->options.bits.LPT_SUPPORT)
-+		return;
-+
-+	lpt_control = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	/* POSSIBLE VALUES for Low Power Tiling Mode:
-+	 * 00 - Use channel 0
-+	 * 01 - Use Channel 0 and 1
-+	 * 02 - Use Channel 0,1,2,3
-+	 * 03 - reserved */
-+	switch (compressor->lpt_channels_num) {
-+	/* case 2:
-+	 * Use Channel 0 & 1 / Not used for DCE 11 */
-+	case 1:
-+		/*Use Channel 0 for LPT for DCE 11 */
-+		set_reg_field_value(
-+			lpt_control,
-+			0,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+		break;
-+	default:
-+		dal_logger_write(
-+			compressor->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: Invalid selected DRAM channels for LPT!!!",
-+			__func__);
-+		break;
-+	}
-+
-+	lpt_control = lpt_memory_control_config(cp80, lpt_control);
-+
-+	/* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
-+	 * FBC compressed surface pitch.
-+	 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
-+	 * Surface Pitch) / (Row Size * Number of Channels *
-+	 * Number of Banks)). */
-+	rows_per_channel = 0;
-+	lpt_alignment = lpt_size_alignment(cp80);
-+	source_view_width =
-+		align_to_chunks_number_per_line(
-+			cp80,
-+			params->source_view_width);
-+	source_view_height = (params->source_view_height + 1) & (~0x1);
-+
-+	if (lpt_alignment != 0) {
-+		rows_per_channel = source_view_width * source_view_height * 4;
-+		rows_per_channel =
-+			(rows_per_channel % lpt_alignment) ?
-+				(rows_per_channel / lpt_alignment + 1) :
-+				rows_per_channel / lpt_alignment;
-+	}
-+
-+	set_reg_field_value(
-+		lpt_control,
-+		rows_per_channel,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ROWS_PER_CHAN);
-+
-+	dm_write_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL, lpt_control);
-+}
-+
-+/*
-+ * DCE 11 Frame Buffer Compression Implementation
-+ */
-+
-+
-+void dce80_compressor_set_fbc_invalidation_triggers(
-+	struct compressor *compressor,
-+	uint32_t fbc_trigger)
-+{
-+	/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
-+	 * for DCE 11 regions cannot be used - does not work with S/G
-+	 */
-+	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
-+	uint32_t value = dm_read_reg(compressor->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		FBC_CLIENT_REGION_MASK,
-+		FBC_MEMORY_REGION_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Setup events when to clear all CSM entries (effectively marking
-+	 * current compressed data invalid)
-+	 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
-+	 * Used as the initial value of the metadata sent to the compressor
-+	 * after invalidation, to indicate that the compressor should attempt
-+	 * to compress all chunks on the current pass.  Also used when the chunk
-+	 * is not successfully written to memory.
-+	 * When this CSM value is detected, FBC reads from the uncompressed
-+	 * buffer. Set events according to passed in value, these events are
-+	 * valid for DCE8:
-+	 *     - bit  0 - display register updated
-+	 *     - bit 28 - memory write from any client except from MCIF
-+	 *     - bit 29 - CG static screen signal is inactive
-+	 * In addition, DCE8.1 also needs to set new DCE8.1 specific events
-+	 * that are used to trigger invalidation on certain register changes,
-+	 * for example enabling of Alpha Compression may trigger invalidation of
-+	 * FBC once bit is set. These events are as follows:
-+	 *      - Bit 2 - FBC_GRPH_COMP_EN register updated
-+	 *      - Bit 3 - FBC_SRC_SEL register updated
-+	 *      - Bit 4 - FBC_MIN_COMPRESSION register updated
-+	 *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
-+	 *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
-+	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
-+	 */
-+	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		fbc_trigger |
-+		FBC_IDLE_FORCE_GRPH_COMP_EN |
-+		FBC_IDLE_FORCE_SRC_SEL_CHANGE |
-+		FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
-+		FBC_IDLE_FORCE_ALPHA_COMP_EN |
-+		FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
-+		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
-+		FBC_IDLE_FORCE_CLEAR_MASK,
-+		FBC_IDLE_FORCE_CLEAR_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+bool dce80_compressor_construct(struct dce80_compressor *compressor,
-+	struct dc_context *ctx, struct adapter_service *as)
-+{
-+	struct embedded_panel_info panel_info;
-+
-+	compressor->base.options.bits.FBC_SUPPORT = true;
-+	if (!(dal_adapter_service_is_feature_supported(
-+		FEATURE_DISABLE_LPT_SUPPORT)))
-+		compressor->base.options.bits.LPT_SUPPORT = true;
-+	 /* For DCE 11 always use one DRAM channel for LPT */
-+	compressor->base.lpt_channels_num = 1;
-+
-+	if (dal_adapter_service_is_feature_supported(FEATURE_DUMMY_FBC_BACKEND))
-+		compressor->base.options.bits.DUMMY_BACKEND = true;
-+
-+	/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
-+	 * should not be supported */
-+	if (compressor->base.memory_bus_width == 64)
-+		compressor->base.options.bits.LPT_SUPPORT = false;
-+
-+	if (dal_adapter_service_is_feature_supported(
-+		FEATURE_DISABLE_FBC_COMP_CLK_GATE))
-+		compressor->base.options.bits.CLK_GATING_DISABLED = true;
-+
-+	compressor->base.ctx = ctx;
-+	compressor->base.embedded_panel_h_size = 0;
-+	compressor->base.embedded_panel_v_size = 0;
-+	compressor->base.memory_bus_width =
-+		dal_adapter_service_get_asic_vram_bit_width(as);
-+	compressor->base.allocated_size = 0;
-+	compressor->base.preferred_requested_size = 0;
-+	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-+	compressor->base.options.raw = 0;
-+	compressor->base.banks_num = 0;
-+	compressor->base.raw_size = 0;
-+	compressor->base.channel_interleave_size = 0;
-+	compressor->base.dram_channels_num = 0;
-+	compressor->base.lpt_channels_num = 0;
-+	compressor->base.attached_inst = 0;
-+	compressor->base.is_enabled = false;
-+
-+	if (dal_adapter_service_get_embedded_panel_info(as,
-+		&panel_info)) {
-+		compressor->base.embedded_panel_h_size =
-+			panel_info.lcd_timing.horizontal_addressable;
-+		compressor->base.embedded_panel_v_size =
-+			panel_info.lcd_timing.vertical_addressable;
-+	}
-+	return true;
-+}
-+
-+struct compressor *dce80_compressor_create(struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct dce80_compressor *cp80 =
-+		dm_alloc(ctx, sizeof(struct dce80_compressor));
-+
-+	if (!cp80)
-+		return NULL;
-+
-+	if (dce80_compressor_construct(cp80, ctx, as))
-+		return &cp80->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, cp80);
-+	return NULL;
-+}
-+
-+void dce80_compressor_destroy(struct compressor **compressor)
-+{
-+	dm_free((*compressor)->ctx, TO_DCE80_COMPRESSOR(*compressor));
-+	*compressor = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
-new file mode 100644
-index 0000000..8254118
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
-@@ -0,0 +1,84 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMPRESSOR_DCE80_H__
-+#define __DC_COMPRESSOR_DCE80_H__
-+
-+#include "../inc/compressor.h"
-+
-+#define TO_DCE80_COMPRESSOR(compressor)\
-+	container_of(compressor, struct dce80_compressor, base)
-+
-+struct dce80_compressor_reg_offsets {
-+	uint32_t dcp_offset;
-+	uint32_t dmif_offset;
-+};
-+
-+struct dce80_compressor {
-+	struct compressor base;
-+	struct dce80_compressor_reg_offsets offsets;
-+};
-+
-+struct compressor *dce80_compressor_create(struct dc_context *ctx,
-+	struct adapter_service *as);
-+
-+bool dce80_compressor_construct(struct dce80_compressor *cp80,
-+	struct dc_context *ctx, struct adapter_service *as);
-+
-+void dce80_compressor_destroy(struct compressor **cp);
-+
-+/* FBC RELATED */
-+void dce80_compressor_power_up_fbc(struct compressor *cp);
-+
-+void dce80_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params);
-+
-+void dce80_compressor_disable_fbc(struct compressor *cp);
-+
-+void dce80_compressor_set_fbc_invalidation_triggers(struct compressor *cp,
-+	uint32_t fbc_trigger);
-+
-+void dce80_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce80_compressor_get_required_compressed_surface_size(
-+	struct compressor *cp,
-+	struct fbc_input_info *input_info,
-+	struct fbc_requested_compressed_size *size);
-+
-+bool dce80_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
-+	uint32_t *fbc_mapped_crtc_id);
-+
-+/* LPT RELATED */
-+void dce80_compressor_enable_lpt(struct compressor *cp);
-+
-+void dce80_compressor_disable_lpt(struct compressor *cp);
-+
-+void dce80_compressor_program_lpt_control(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce80_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-new file mode 100644
-index 0000000..9f3201f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -0,0 +1,308 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_dc.h"
-+#include "core_types.h"
-+#include "dce80_hw_sequencer.h"
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+
-+#include "gpu/dce80/dc_clock_gating_dce80.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+struct dce80_hw_seq_reg_offsets {
-+	uint32_t blnd;
-+	uint32_t crtc;
-+};
-+
-+enum pipe_lock_control {
-+	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
-+	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
-+	PIPE_LOCK_CONTROL_SCL = 1 << 2,
-+	PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
-+	PIPE_LOCK_CONTROL_MODE = 1 << 4
-+};
-+
-+enum blender_mode {
-+	BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
-+	BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
-+	BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
-+	BLENDER_MODE_STEREO
-+};
-+
-+static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_BLND(reg, id)\
-+	(reg + reg_offsets[id].blnd)
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+
-+/***************************PIPE_CONTROL***********************************/
-+static void dce80_enable_fe_clock(
-+	struct dc_context *ctx, uint8_t controller_id, bool enable)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	addr = HW_REG_CRTC(mmCRTC_DCFE_CLOCK_CONTROL, controller_id);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		enable,
-+		CRTC_DCFE_CLOCK_CONTROL,
-+		CRTC_DCFE_CLOCK_ENABLE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static bool dce80_pipe_control_lock(
-+	struct dc_context *ctx,
-+	uint8_t controller_idx,
-+	uint32_t control_mask,
-+	bool lock)
-+{
-+	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+	bool need_to_wait = false;
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SCL)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_SCL_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	if (!lock && need_to_wait) {
-+		uint8_t counter = 0;
-+		const uint8_t counter_limit = 100;
-+		const uint16_t delay_us = 1000;
-+
-+		uint8_t pipe_pending;
-+
-+		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
-+				controller_idx);
-+
-+		while (counter < counter_limit) {
-+			value = dm_read_reg(ctx, addr);
-+
-+			pipe_pending = 0;
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDc_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDo_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDc_GRPH_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDo_GRPH_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDc_GRPH_SURF_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDo_GRPH_SURF_UPDATE_PENDING);
-+			}
-+
-+			if (pipe_pending == 0)
-+				break;
-+
-+			counter++;
-+			dm_delay_in_microseconds(ctx, delay_us);
-+		}
-+
-+		if (counter == counter_limit) {
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: wait for update exceeded (wait %d us)\n",
-+				__func__,
-+				counter * delay_us);
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: control %d, remain value %x\n",
-+				__func__,
-+				control_mask,
-+				value);
-+		} else {
-+			/* OK. */
-+		}
-+	}
-+
-+	return true;
-+}
-+
-+static void dce80_set_blender_mode(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	uint32_t mode)
-+{
-+	uint32_t value;
-+	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-+	uint32_t blnd_mode;
-+	uint32_t feedthrough = 0;
-+
-+	switch (mode) {
-+	case BLENDER_MODE_OTHER_PIPE:
-+		feedthrough = 0;
-+		blnd_mode = 1;
-+		break;
-+	case BLENDER_MODE_BLENDING:
-+		feedthrough = 0;
-+		blnd_mode = 2;
-+		break;
-+	case BLENDER_MODE_CURRENT_PIPE:
-+	default:
-+		feedthrough = 1;
-+		blnd_mode = 0;
-+		break;
-+	}
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		blnd_mode,
-+		BLND_CONTROL,
-+		BLND_MODE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static bool dce80_enable_display_power_gating(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0))
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+bool dce80_hw_sequencer_construct(struct dc *dc)
-+{
-+	dce110_hw_sequencer_construct(dc);
-+
-+	dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce80_power_up;
-+	dc->hwss.enable_fe_clock = dce80_enable_fe_clock;
-+	dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
-+	dc->hwss.pipe_control_lock = dce80_pipe_control_lock;
-+	dc->hwss.set_blender_mode = dce80_set_blender_mode;
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h
-new file mode 100644
-index 0000000..9d6dd05
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE80_H__
-+#define __DC_HWSS_DCE80_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+bool dce80_hw_sequencer_construct(struct dc *dc);
-+
-+#endif /* __DC_HWSS_DCE80_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c
-new file mode 100644
-index 0000000..6dde1eb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_ipp.h"
-+
-+#include "dce110/dce110_ipp.h"
-+
-+static struct ipp_funcs funcs = {
-+		.ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes,
-+		.ipp_cursor_set_position = dce110_ipp_cursor_set_position,
-+		.ipp_program_prescale = dce110_ipp_program_prescale,
-+		.ipp_set_degamma = dce110_ipp_set_degamma,
-+};
-+
-+bool dce80_ipp_construct(
-+	struct dce110_ipp *ipp,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offset)
-+{
-+	ipp->base.ctx = ctx;
-+
-+	ipp->base.inst = inst;
-+
-+	ipp->offsets = *offset;
-+
-+	ipp->base.funcs = &funcs;
-+
-+	return true;
-+}
-+
-+void dce80_ipp_destroy(struct input_pixel_processor **ipp)
-+{
-+	dm_free((*ipp)->ctx, TO_DCE80_IPP(*ipp));
-+	*ipp = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-new file mode 100644
-index 0000000..bd81693
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_IPP_DCE80_H__
-+#define __DC_IPP_DCE80_H__
-+
-+#include "inc/ipp.h"
-+
-+#define TO_DCE80_IPP(input_pixel_processor)\
-+		container_of(input_pixel_processor, struct dce110_ipp, base)
-+
-+struct dce110_ipp;
-+struct dce110_ipp_reg_offsets;
-+struct gamma_parameters;
-+struct dev_c_lut;
-+
-+
-+bool dce80_ipp_construct(
-+	struct dce110_ipp *ipp,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offset);
-+
-+void dce80_ipp_destroy(struct input_pixel_processor **ipp);
-+
-+
-+#endif /*__DC_IPP_DCE80_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c
-new file mode 100644
-index 0000000..fdffb8c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/fixed31_32.h"
-+#include "basics/conversion.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_ipp.h"
-+#include "dce110/dce110_ipp.h"
-+#include "gamma_types.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + ipp80->offsets.dcp_offset)
-+
-+enum {
-+	MAX_INPUT_LUT_ENTRY = 256
-+};
-+
-+
-+/*PROTOTYPE DECLARATIONS*/
-+
-+
-+static void set_legacy_input_gamma_mode(
-+	struct dce110_ipp *ipp80,
-+	bool is_legacy);
-+
-+
-+
-+void dce80_ipp_set_legacy_input_gamma_mode(
-+		struct input_pixel_processor *ipp,
-+		bool is_legacy)
-+{
-+	struct dce110_ipp *ipp80 = TO_DCE80_IPP(ipp);
-+
-+	set_legacy_input_gamma_mode(ipp80, is_legacy);
-+}
-+
-+
-+static void set_legacy_input_gamma_mode(
-+	struct dce110_ipp *ipp80,
-+	bool is_legacy)
-+{
-+	const uint32_t addr = DCP_REG(mmINPUT_GAMMA_CONTROL);
-+	uint32_t value = dm_read_reg(ipp80->base.ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		!is_legacy,
-+		INPUT_GAMMA_CONTROL,
-+		GRPH_INPUT_GAMMA_MODE);
-+
-+	dm_write_reg(ipp80->base.ctx, addr, value);
-+}
-+
-+
-+
-+
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-new file mode 100644
-index 0000000..5288436
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-@@ -0,0 +1,329 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "core_types.h"
-+#include "dce80_link_encoder.h"
-+#include "stream_encoder.h"
-+#include "../dce110/dce110_link_encoder.h"
-+#include "i2caux_interface.h"
-+
-+/* TODO: change to dce80 header file */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+#define LINK_REG(reg)\
-+	(enc110->link_regs->reg)
-+
-+#define DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 297000
-+
-+#define DEFAULT_AUX_MAX_DATA_SIZE 16
-+#define AUX_MAX_DEFER_WRITE_RETRY 20
-+/*
-+ * @brief
-+ * Trigger Source Select
-+ * ASIC-dependent, actual values for register programming
-+ */
-+#define DCE80_DIG_FE_SOURCE_SELECT_INVALID 0x0
-+#define DCE80_DIG_FE_SOURCE_SELECT_DIGA 0x01
-+#define DCE80_DIG_FE_SOURCE_SELECT_DIGB 0x02
-+#define DCE80_DIG_FE_SOURCE_SELECT_DIGC 0x04
-+#define DCE80_DIG_FE_SOURCE_SELECT_DIGD 0x08
-+#define DCE80_DIG_FE_SOURCE_SELECT_DIGE 0x10
-+#define DCE80_DIG_FE_SOURCE_SELECT_DIGF 0x20
-+
-+/* all values are in milliseconds */
-+/* For eDP, after power-up/power/down,
-+ * 300/500 msec max. delay from LCDVCC to black video generation */
-+#define PANEL_POWER_UP_TIMEOUT 300
-+#define PANEL_POWER_DOWN_TIMEOUT 500
-+#define HPD_CHECK_INTERVAL 10
-+
-+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-+#define TMDS_MIN_PIXEL_CLOCK 25000
-+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-+#define TMDS_MAX_PIXEL_CLOCK 165000
-+
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
-+static enum bp_result link_transmitter_control(
-+	struct dce110_link_encoder *enc110,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result;
-+	struct dc_bios *bp = dal_adapter_service_get_bios_parser(
-+					enc110->base.adapter_service);
-+
-+	result = bp->funcs->transmitter_control(bp, cntl);
-+
-+	return result;
-+}
-+
-+static void dce80_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
-+	uint32_t pixel_clock)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	/* Enable the PHY */
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = enc->preferred_engine;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	if (hdmi) {
-+		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+		cntl.lanes_number = 4;
-+	} else if (dual_link) {
-+		cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		cntl.lanes_number = 8;
-+	} else {
-+		cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		cntl.lanes_number = 4;
-+	}
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+
-+	cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+static void configure_encoder(
-+	struct dce110_link_encoder *enc110,
-+	const struct dc_link_settings *link_settings)
-+{
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	/* set number of lanes */
-+	addr = LINK_REG(DP_CONFIG);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
-+			DP_CONFIG, DP_UDI_LANES);
-+	dm_write_reg(ctx, addr, value);
-+
-+}
-+
-+/* enables DP PHY output */
-+static void dce80_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually.
-+	 */
-+	configure_encoder(enc110, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = enc->preferred_engine;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	/* TODO: check if undefined works */
-+	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dal_logger_write(ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+static struct link_encoder_funcs dce80_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		dce110_link_encoder_validate_output_with_stream,
-+	.hw_init = dce110_link_encoder_hw_init,
-+	.setup = dce110_link_encoder_setup,
-+	.enable_tmds_output = dce80_link_encoder_enable_tmds_output,
-+	.enable_dp_output = dce80_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
-+	.disable_output = dce110_link_encoder_disable_output,
-+	.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		dce110_link_encoder_update_mst_stream_allocation_table,
-+	.set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
-+	.backlight_control = dce110_link_encoder_edp_backlight_control,
-+	.power_control = dce110_link_encoder_edp_power_control,
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe
-+};
-+
-+
-+bool dce80_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs)
-+{
-+	struct graphics_object_encoder_cap_info enc_cap_info = {0};
-+
-+	enc110->base.funcs = &dce80_lnk_enc_funcs;
-+	enc110->base.ctx = init_data->ctx;
-+	enc110->base.id = init_data->encoder;
-+
-+	enc110->base.hpd_source = init_data->hpd_source;
-+	enc110->base.connector = init_data->connector;
-+	enc110->base.input_signals = SIGNAL_TYPE_ALL;
-+
-+	enc110->base.adapter_service = init_data->adapter_service;
-+
-+	enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-+
-+	enc110->base.features.flags.raw = 0;
-+
-+	enc110->base.transmitter = init_data->transmitter;
-+
-+	enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
-+
-+	enc110->base.features.max_pixel_clock = DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+
-+	/* set the flag to indicate whether driver poll the I2C data pin
-+	 * while doing the DP sink detect
-+	 */
-+
-+	if (dal_adapter_service_is_feature_supported(
-+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
-+		enc110->base.features.flags.bits.
-+			DP_SINK_DETECT_POLL_DATA_PIN = true;
-+
-+	enc110->base.output_signals =
-+		SIGNAL_TYPE_DVI_SINGLE_LINK |
-+		SIGNAL_TYPE_DVI_DUAL_LINK |
-+		SIGNAL_TYPE_LVDS |
-+		SIGNAL_TYPE_DISPLAY_PORT |
-+		SIGNAL_TYPE_DISPLAY_PORT_MST |
-+		SIGNAL_TYPE_EDP |
-+		SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
-+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
-+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
-+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
-+	 * Prefer DIG assignment is decided by board design.
-+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
-+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
-+	 * By this, adding DIGG should not hurt DCE 8.0.
-+	 * This will let DCE 8.1 share DCE 8.0 as much as possible
-+	 */
-+
-+	enc110->link_regs = link_regs;
-+	enc110->aux_regs = aux_regs;
-+	enc110->bl_regs = bl_regs;
-+
-+	switch (enc110->base.transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGA;
-+	break;
-+	case TRANSMITTER_UNIPHY_B:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGB;
-+
-+	break;
-+	case TRANSMITTER_UNIPHY_C:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGC;
-+	break;
-+	case TRANSMITTER_UNIPHY_D:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGD;
-+	break;
-+	case TRANSMITTER_UNIPHY_E:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGE;
-+	break;
-+	case TRANSMITTER_UNIPHY_F:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGF;
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	dal_logger_write(init_data->ctx->logger,
-+			LOG_MAJOR_I2C_AUX,
-+			LOG_MINOR_I2C_AUX_CFG,
-+			"Using channel: %s [%d]\n",
-+			DECODE_CHANNEL_ID(init_data->channel),
-+			init_data->channel);
-+
-+	/* Override features with DCE-specific values */
-+	if (dal_adapter_service_get_encoder_cap_info(
-+			enc110->base.adapter_service,
-+			enc110->base.id, &enc_cap_info))
-+		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
-+				enc_cap_info.dp_hbr2_cap;
-+
-+	/* test pattern 3 support */
-+	enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
-+	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-+
-+	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_SUPPORT_DP_Y_ONLY);
-+
-+	enc110->base.features.flags.bits.IS_YCBCR_CAPABLE =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_SUPPORT_DP_YUV);
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
-new file mode 100644
-index 0000000..b894643
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_ENCODER__DCE80_H__
-+#define __DC_LINK_ENCODER__DCE80_H__
-+
-+#include "inc/link_encoder.h"
-+#include "../dce110/dce110_link_encoder.h"
-+
-+bool dce80_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs);
-+
-+#endif /* __DC_LINK_ENCODER__DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-new file mode 100644
-index 0000000..a8e9961
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-@@ -0,0 +1,217 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DC_MEM_INPUT_DCE80_H__
-+
-+#define __DC_MEM_INPUT_DCE80_H__
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+/* TODO: this needs to be looked at, used by Stella's workaround*/
-+#include "gmc/gmc_7_1_d.h"
-+#include "gmc/gmc_7_1_sh_mask.h"
-+
-+#include "include/logger_interface.h"
-+#include "adapter_service_interface.h"
-+#include "inc/bandwidth_calcs.h"
-+
-+#include "../dce110/dce110_mem_input.h"
-+#include "dce80_mem_input.h"
-+
-+
-+#define MAX_WATERMARK 0xFFFF
-+#define SAFE_NBP_MARK 0x7FFF
-+
-+#define DCP_REG(reg) (reg + mem_input80->offsets.dcp)
-+#define DMIF_REG(reg) (reg + mem_input80->offsets.dmif)
-+#define PIPE_REG(reg) (reg + mem_input80->offsets.pipe)
-+
-+static uint32_t get_dmif_switch_time_us(
-+		uint32_t h_total,
-+		uint32_t v_total,
-+		uint32_t pix_clk_khz)
-+{
-+	uint32_t frame_time;
-+	uint32_t pixels_per_second;
-+	uint32_t pixels_per_frame;
-+	uint32_t refresh_rate;
-+	const uint32_t us_in_sec = 1000000;
-+	const uint32_t min_single_frame_time_us = 30000;
-+	/*return double of frame time*/
-+	const uint32_t single_frame_time_multiplier = 2;
-+
-+	if (!h_total || v_total || !pix_clk_khz)
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+
-+	/*TODO: should we use pixel format normalized pixel clock here?*/
-+	pixels_per_second = pix_clk_khz * 1000;
-+	pixels_per_frame = h_total * v_total;
-+
-+	if (!pixels_per_second || !pixels_per_frame) {
-+		/* avoid division by zero */
-+		ASSERT(pixels_per_frame);
-+		ASSERT(pixels_per_second);
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+	}
-+
-+	refresh_rate = pixels_per_second / pixels_per_frame;
-+
-+	if (!refresh_rate) {
-+		/* avoid division by zero*/
-+		ASSERT(refresh_rate);
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+	}
-+
-+	frame_time = us_in_sec / refresh_rate;
-+
-+	if (frame_time < min_single_frame_time_us)
-+		frame_time = min_single_frame_time_us;
-+
-+	frame_time *= single_frame_time_multiplier;
-+
-+	return frame_time;
-+}
-+
-+static void allocate_mem_input(
-+		struct mem_input *mi,
-+		uint32_t h_total,
-+		uint32_t v_total,
-+		uint32_t pix_clk_khz,
-+		uint32_t total_targets_num)
-+{
-+	const uint32_t retry_delay = 10;
-+	uint32_t retry_count = get_dmif_switch_time_us(
-+			h_total,
-+			v_total,
-+			pix_clk_khz) / retry_delay;
-+
-+	struct dce110_mem_input *bm80 = TO_DCE110_MEM_INPUT(mi);
-+	uint32_t addr = bm80->offsets.pipe + mmPIPE0_DMIF_BUFFER_CONTROL;
-+	uint32_t value;
-+	uint32_t field;
-+
-+	if (bm80->supported_stutter_mode
-+			& STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)
-+		goto register_underflow_int;
-+
-+	/*Allocate DMIF buffer*/
-+	value = dm_read_reg(mi->ctx, addr);
-+	field = get_reg_field_value(
-+		value, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED);
-+	if (field == 2)
-+		goto register_underflow_int;
-+
-+	set_reg_field_value(
-+			value,
-+			2,
-+			PIPE0_DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATED);
-+
-+	dm_write_reg(mi->ctx, addr, value);
-+
-+	do {
-+		value = dm_read_reg(mi->ctx, addr);
-+		field = get_reg_field_value(
-+			value,
-+			PIPE0_DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATION_COMPLETED);
-+
-+		if (field)
-+			break;
-+
-+		dm_delay_in_microseconds(mi->ctx, retry_delay);
-+		retry_count--;
-+
-+	} while (retry_count > 0);
-+
-+	if (field == 0)
-+		dal_logger_write(mi->ctx->logger,
-+				LOG_MAJOR_ERROR,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: DMIF allocation failed",
-+				__func__);
-+
-+	/*
-+	 * Stella Wong proposed the following change
-+	 *
-+	 * Value of mcHubRdReqDmifLimit.ENABLE:
-+	 * 00 - disable DMIF rdreq limit
-+	 * 01 - enable DMIF rdreq limit, disabled by DMIF stall = 1 || urg != 0
-+	 * 02 - enable DMIF rdreq limit, disable by DMIF stall = 1
-+	 * 03 - force enable DMIF rdreq limit, ignore DMIF stall / urgent
-+	 */
-+	addr = mmMC_HUB_RDREQ_DMIF_LIMIT;
-+	value = dm_read_reg(mi->ctx, addr);
-+	if (total_targets_num > 1)
-+		set_reg_field_value(value, 0, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+	else
-+		set_reg_field_value(value, 3, MC_HUB_RDREQ_DMIF_LIMIT, ENABLE);
-+	dm_write_reg(mi->ctx, addr, value);
-+
-+register_underflow_int:
-+	/*todo*/;
-+	/*register_interrupt(bm80, irq_source, ctrl_id);*/
-+}
-+
-+static struct mem_input_funcs dce80_mem_input_funcs = {
-+	.mem_input_program_display_marks =
-+			dce110_mem_input_program_display_marks,
-+	.allocate_mem_input = allocate_mem_input,
-+	.free_mem_input =
-+			dce110_free_mem_input,
-+	.mem_input_program_surface_flip_and_addr =
-+			dce110_mem_input_program_surface_flip_and_addr,
-+	.mem_input_program_surface_config =
-+			dce110_mem_input_program_surface_config,
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce80_mem_input_construct(
-+	struct dce110_mem_input *mem_input80,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets)
-+{
-+
-+	mem_input80->base.funcs = &dce80_mem_input_funcs;
-+	mem_input80->base.ctx = ctx;
-+
-+	mem_input80->base.inst = inst;
-+
-+	mem_input80->offsets = *offsets;
-+
-+	mem_input80->supported_stutter_mode = 0;
-+	dal_adapter_service_get_feature_value(FEATURE_STUTTER_MODE,
-+			&(mem_input80->supported_stutter_mode),
-+			sizeof(mem_input80->supported_stutter_mode));
-+
-+	return true;
-+}
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-new file mode 100644
-index 0000000..1d299da
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-@@ -0,0 +1,41 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MEM_INPUT_DCE80_H__
-+#define __DC_MEM_INPUT_DCE80_H__
-+
-+#include "inc/mem_input.h"
-+
-+bool dce80_mem_input_construct(
-+	struct dce110_mem_input *mem_input80,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets);
-+
-+
-+enum dc_status dce_base_validate_mapped_resource(
-+		const struct dc *dc,
-+		struct validate_context *context);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c
-new file mode 100644
-index 0000000..82c98a1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c
-@@ -0,0 +1,141 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_opp.h"
-+
-+#define FROM_OPP(opp)\
-+	container_of(opp, struct dce80_opp, base)
-+
-+enum {
-+	MAX_LUT_ENTRY = 256,
-+	MAX_NUMBER_OF_ENTRIES = 256
-+};
-+
-+static const struct dce80_opp_reg_offsets reg_offsets[] = {
-+{
-+	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.crtc_offset = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.crtc_offset = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.crtc_offset = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.crtc_offset = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.crtc_offset = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.crtc_offset = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+
-+
-+static struct opp_funcs funcs = {
-+		.opp_power_on_regamma_lut = dce80_opp_power_on_regamma_lut,
-+		.opp_program_bit_depth_reduction =
-+				dce80_opp_program_bit_depth_reduction,
-+		.opp_program_clamping_and_pixel_encoding =
-+				dce80_opp_program_clamping_and_pixel_encoding,
-+		.opp_set_csc_adjustment = dce80_opp_set_csc_adjustment,
-+		.opp_set_csc_default = dce80_opp_set_csc_default,
-+		.opp_set_dyn_expansion = dce80_opp_set_dyn_expansion,
-+		.opp_program_regamma_pwl = dce80_opp_program_regamma_pwl,
-+		.opp_set_regamma_mode = dce80_opp_set_regamma_mode,
-+		.opp_destroy = dce80_opp_destroy,
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce80_opp_construct(struct dce80_opp *opp80,
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	if (inst >= ARRAY_SIZE(reg_offsets))
-+		return false;
-+
-+	opp80->base.funcs = &funcs;
-+
-+	opp80->base.ctx = ctx;
-+
-+	opp80->base.inst = inst;
-+
-+	opp80->offsets = reg_offsets[inst];
-+
-+	return true;
-+}
-+
-+void dce80_opp_destroy(struct output_pixel_processor **opp)
-+{
-+	dm_free((*opp)->ctx, FROM_OPP(*opp));
-+	*opp = NULL;
-+}
-+
-+struct output_pixel_processor *dce80_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce80_opp *opp =
-+		dm_alloc(ctx, sizeof(struct dce80_opp));
-+
-+	if (!opp)
-+		return NULL;
-+
-+	if (dce80_opp_construct(opp,
-+			ctx, inst))
-+		return &opp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, opp);
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-new file mode 100644
-index 0000000..d414f50
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-@@ -0,0 +1,130 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_OPP_DCE80_H__
-+#define __DC_OPP_DCE80_H__
-+
-+#include "dc_types.h"
-+#include "inc/opp.h"
-+#include "gamma_types.h"
-+
-+struct gamma_parameters;
-+
-+struct dce80_regamma {
-+	struct gamma_curve arr_curve_points[16];
-+	struct curve_points arr_points[3];
-+	uint32_t hw_points_num;
-+	struct hw_x_point *coordinates_x;
-+	struct pwl_result_data *rgb_resulted;
-+
-+	/* re-gamma curve */
-+	struct pwl_float_data_ex *rgb_regamma;
-+	/* coeff used to map user evenly distributed points
-+	 * to our hardware points (predefined) for gamma 256 */
-+	struct pixel_gamma_point *coeff128;
-+	struct pixel_gamma_point *coeff128_oem;
-+	/* coeff used to map user evenly distributed points
-+	 * to our hardware points (predefined) for gamma 1025 */
-+	struct pixel_gamma_point *coeff128_dx;
-+	/* evenly distributed points, gamma 256 software points 0-255 */
-+	struct gamma_pixel *axis_x_256;
-+	/* evenly distributed points, gamma 1025 software points 0-1025 */
-+	struct gamma_pixel *axis_x_1025;
-+	/* OEM supplied gamma for regamma LUT */
-+	struct pwl_float_data *rgb_oem;
-+	/* user supplied gamma */
-+	struct pwl_float_data *rgb_user;
-+	uint32_t extra_points;
-+	bool use_half_points;
-+	struct fixed31_32 x_max1;
-+	struct fixed31_32 x_max2;
-+	struct fixed31_32 x_min;
-+	struct fixed31_32 divider1;
-+	struct fixed31_32 divider2;
-+	struct fixed31_32 divider3;
-+};
-+
-+/* OPP RELATED */
-+#define TO_DCE80_OPP(opp)\
-+	container_of(opp, struct dce80_opp, base)
-+
-+struct dce80_opp_reg_offsets {
-+	uint32_t fmt_offset;
-+	uint32_t dcp_offset;
-+	uint32_t crtc_offset;
-+};
-+
-+struct dce80_opp {
-+	struct output_pixel_processor base;
-+	struct dce80_opp_reg_offsets offsets;
-+	struct dce80_regamma regamma;
-+};
-+
-+bool dce80_opp_construct(struct dce80_opp *opp80,
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+void dce80_opp_destroy(struct output_pixel_processor **opp);
-+
-+struct output_pixel_processor *dce80_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst);
-+
-+/* REGAMMA RELATED */
-+void dce80_opp_power_on_regamma_lut(
-+	struct output_pixel_processor *opp,
-+	bool power_on);
-+
-+bool dce80_opp_program_regamma_pwl(
-+	struct output_pixel_processor *opp,
-+	const struct regamma_params *pamras);
-+
-+void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp,
-+		enum opp_regamma mode);
-+
-+void dce80_opp_set_csc_adjustment(
-+	struct output_pixel_processor *opp,
-+	const struct grph_csc_adjustment *adjust);
-+
-+void dce80_opp_set_csc_default(
-+	struct output_pixel_processor *opp,
-+	const struct default_adjustment *default_adjust);
-+
-+/* FORMATTER RELATED */
-+void dce80_opp_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params);
-+
-+void dce80_opp_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params);
-+
-+
-+void dce80_opp_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-new file mode 100644
-index 0000000..90662ae
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-@@ -0,0 +1,905 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce80_opp.h"
-+#include "basics/conversion.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + opp80->offsets.dcp_offset)
-+
-+enum {
-+	OUTPUT_CSC_MATRIX_SIZE = 12
-+};
-+
-+struct out_csc_color_matrix {
-+	enum color_space color_space;
-+	uint16_t regval[OUTPUT_CSC_MATRIX_SIZE];
-+};
-+
-+static const struct out_csc_color_matrix global_color_matrix[] = {
-+{ COLOR_SPACE_SRGB_FULL_RANGE,
-+	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+{ COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
-+{ COLOR_SPACE_YCBCR601,
-+	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
-+		0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-+	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-+/*  YOnly same as YCbCr709 but Y in Full range -To do. */
-+{ COLOR_SPACE_YCBCR601_YONLY, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709_YONLY, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
-+};
-+
-+enum csc_color_mode {
-+	/* 00 - BITS2:0 Bypass */
-+	CSC_COLOR_MODE_GRAPHICS_BYPASS,
-+	/* 01 - hard coded coefficient TV RGB */
-+	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
-+	/* 04 - programmable OUTPUT CSC coefficient */
-+	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
-+};
-+
-+static void program_color_matrix(
-+	struct dce80_opp *opp80,
-+	const struct out_csc_color_matrix *tbl_entry,
-+	enum grph_color_adjust_option options)
-+{
-+	struct dc_context *ctx = opp80->base.ctx;
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C11_C12);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[0],
-+			OUTPUT_CSC_C11_C12,
-+			OUTPUT_CSC_C11);
-+
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[1],
-+			OUTPUT_CSC_C11_C12,
-+			OUTPUT_CSC_C12);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C13_C14);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[2],
-+			OUTPUT_CSC_C13_C14,
-+			OUTPUT_CSC_C13);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[3],
-+			OUTPUT_CSC_C13_C14,
-+			OUTPUT_CSC_C14);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C21_C22);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[4],
-+			OUTPUT_CSC_C21_C22,
-+			OUTPUT_CSC_C21);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[5],
-+			OUTPUT_CSC_C21_C22,
-+			OUTPUT_CSC_C22);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C23_C24);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[6],
-+			OUTPUT_CSC_C23_C24,
-+			OUTPUT_CSC_C23);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[7],
-+			OUTPUT_CSC_C23_C24,
-+			OUTPUT_CSC_C24);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C31_C32);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[8],
-+			OUTPUT_CSC_C31_C32,
-+			OUTPUT_CSC_C31);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[9],
-+			OUTPUT_CSC_C31_C32,
-+			OUTPUT_CSC_C32);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		uint32_t value = 0;
-+		uint32_t addr = DCP_REG(mmOUTPUT_CSC_C33_C34);
-+		/* fixed S2.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[10],
-+			OUTPUT_CSC_C33_C34,
-+			OUTPUT_CSC_C33);
-+		/* fixed S0.13 format */
-+		set_reg_field_value(
-+			value,
-+			tbl_entry->regval[11],
-+			OUTPUT_CSC_C33_C34,
-+			OUTPUT_CSC_C34);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+/*
-+ * initialize_color_float_adj_reference_values
-+ * This initialize display color adjust input from API to HW range for later
-+ * calculation use. This is shared by all the display color adjustment.
-+ * @param :
-+ * @return None
-+ */
-+static void initialize_color_float_adj_reference_values(
-+	const struct grph_csc_adjustment *adjust,
-+	struct fixed31_32 *grph_cont,
-+	struct fixed31_32 *grph_sat,
-+	struct fixed31_32 *grph_bright,
-+	struct fixed31_32 *sin_grph_hue,
-+	struct fixed31_32 *cos_grph_hue)
-+{
-+	/* Hue adjustment could be negative. -45 ~ +45 */
-+	struct fixed31_32 hue =
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_from_fraction(adjust->grph_hue, 180),
-+			dal_fixed31_32_pi);
-+
-+	*sin_grph_hue = dal_fixed31_32_sin(hue);
-+	*cos_grph_hue = dal_fixed31_32_cos(hue);
-+
-+	if (adjust->adjust_divider) {
-+		*grph_cont =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_cont,
-+				adjust->adjust_divider);
-+		*grph_sat =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_sat,
-+				adjust->adjust_divider);
-+		*grph_bright =
-+			dal_fixed31_32_from_fraction(
-+				adjust->grph_bright,
-+				adjust->adjust_divider);
-+	} else {
-+		*grph_cont = dal_fixed31_32_from_int(adjust->grph_cont);
-+		*grph_sat = dal_fixed31_32_from_int(adjust->grph_sat);
-+		*grph_bright = dal_fixed31_32_from_int(adjust->grph_bright);
-+	}
-+}
-+
-+static inline struct fixed31_32 fixed31_32_clamp(
-+	struct fixed31_32 value,
-+	int32_t min_numerator,
-+	int32_t max_numerator,
-+	int32_t denominator)
-+{
-+	return dal_fixed31_32_clamp(
-+		value,
-+		dal_fixed31_32_from_fraction(
-+			min_numerator,
-+			denominator),
-+		dal_fixed31_32_from_fraction(
-+			max_numerator,
-+			denominator));
-+}
-+
-+static void setup_reg_format(
-+	struct fixed31_32 *coefficients,
-+	uint16_t *reg_values)
-+{
-+	enum {
-+		LENGTH = 12,
-+		DENOMINATOR = 10000
-+	};
-+
-+	static const int32_t min_numerator[] = {
-+		-3 * DENOMINATOR,
-+		-DENOMINATOR
-+	};
-+
-+	static const int32_t max_numerator[] = {
-+		DENOMINATOR,
-+		DENOMINATOR
-+	};
-+
-+	static const uint8_t integer_bits[] = { 2, 0 };
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		const uint32_t index = (i % 4) == 3;
-+
-+		reg_values[i] = fixed_point_to_int_frac(
-+			fixed31_32_clamp(coefficients[(i + 8) % LENGTH],
-+				min_numerator[index],
-+				max_numerator[index],
-+				DENOMINATOR),
-+			integer_bits[index], 13);
-+
-+		++i;
-+	} while (i != LENGTH);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: setup_adjustments
-+ *  @note prepare to setup the values
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-+	struct dc_csc_adjustments *adjustments)
-+{
-+	if (adjust->adjust_divider != 0) {
-+		adjustments->brightness =
-+			dal_fixed31_32_from_fraction(adjust->grph_bright,
-+			adjust->adjust_divider);
-+		adjustments->contrast =
-+			dal_fixed31_32_from_fraction(adjust->grph_cont,
-+			adjust->adjust_divider);
-+		adjustments->saturation =
-+			dal_fixed31_32_from_fraction(adjust->grph_sat,
-+			adjust->adjust_divider);
-+	} else {
-+		adjustments->brightness =
-+			dal_fixed31_32_from_fraction(adjust->grph_bright, 1);
-+		adjustments->contrast =
-+			dal_fixed31_32_from_fraction(adjust->grph_cont, 1);
-+		adjustments->saturation =
-+			dal_fixed31_32_from_fraction(adjust->grph_sat, 1);
-+	}
-+
-+	/* convert degrees into radians */
-+	adjustments->hue =
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_from_fraction(adjust->grph_hue, 180),
-+			dal_fixed31_32_pi);
-+}
-+
-+static void prepare_tv_rgb_ideal(
-+	struct fixed31_32 *matrix)
-+{
-+	static const int32_t matrix_[] = {
-+		85546875, 0, 0, 6250000,
-+		0, 85546875, 0, 6250000,
-+		0, 0, 85546875, 6250000
-+	};
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		matrix[i] = dal_fixed31_32_from_fraction(
-+			matrix_[i],
-+			100000000);
-+		++i;
-+	} while (i != ARRAY_SIZE(matrix_));
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_rgb_adjustment_legacy
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for sRGB color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_rgb_adjustment_legacy(
-+	struct dce80_opp *opp80,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	const struct fixed31_32 k1 =
-+		dal_fixed31_32_from_fraction(701000, 1000000);
-+	const struct fixed31_32 k2 =
-+		dal_fixed31_32_from_fraction(236568, 1000000);
-+	const struct fixed31_32 k3 =
-+		dal_fixed31_32_from_fraction(-587000, 1000000);
-+	const struct fixed31_32 k4 =
-+		dal_fixed31_32_from_fraction(464432, 1000000);
-+	const struct fixed31_32 k5 =
-+		dal_fixed31_32_from_fraction(-114000, 1000000);
-+	const struct fixed31_32 k6 =
-+		dal_fixed31_32_from_fraction(-701000, 1000000);
-+	const struct fixed31_32 k7 =
-+		dal_fixed31_32_from_fraction(-299000, 1000000);
-+	const struct fixed31_32 k8 =
-+		dal_fixed31_32_from_fraction(-292569, 1000000);
-+	const struct fixed31_32 k9 =
-+		dal_fixed31_32_from_fraction(413000, 1000000);
-+	const struct fixed31_32 k10 =
-+		dal_fixed31_32_from_fraction(-92482, 1000000);
-+	const struct fixed31_32 k11 =
-+		dal_fixed31_32_from_fraction(-114000, 1000000);
-+	const struct fixed31_32 k12 =
-+		dal_fixed31_32_from_fraction(385051, 1000000);
-+	const struct fixed31_32 k13 =
-+		dal_fixed31_32_from_fraction(-299000, 1000000);
-+	const struct fixed31_32 k14 =
-+		dal_fixed31_32_from_fraction(886000, 1000000);
-+	const struct fixed31_32 k15 =
-+		dal_fixed31_32_from_fraction(-587000, 1000000);
-+	const struct fixed31_32 k16 =
-+		dal_fixed31_32_from_fraction(-741914, 1000000);
-+	const struct fixed31_32 k17 =
-+		dal_fixed31_32_from_fraction(886000, 1000000);
-+	const struct fixed31_32 k18 =
-+		dal_fixed31_32_from_fraction(-144086, 1000000);
-+
-+	const struct fixed31_32 luma_r =
-+		dal_fixed31_32_from_fraction(299, 1000);
-+	const struct fixed31_32 luma_g =
-+		dal_fixed31_32_from_fraction(587, 1000);
-+	const struct fixed31_32 luma_b =
-+		dal_fixed31_32_from_fraction(114, 1000);
-+
-+	struct out_csc_color_matrix tbl_entry;
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	struct fixed31_32 grph_cont;
-+	struct fixed31_32 grph_sat;
-+	struct fixed31_32 grph_bright;
-+	struct fixed31_32 sin_grph_hue;
-+	struct fixed31_32 cos_grph_hue;
-+
-+	initialize_color_float_adj_reference_values(
-+		adjust, &grph_cont, &grph_sat,
-+		&grph_bright, &sin_grph_hue, &cos_grph_hue);
-+
-+	/* COEF_1_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 +
-+	 * Sin(GrphHue) * K2)) */
-+	/* (Cos(GrphHue) * K1 + Sin(GrphHue) * K2) */
-+	matrix[0] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k1),
-+			dal_fixed31_32_mul(sin_grph_hue, k2));
-+	/* GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2 */
-+	matrix[0] = dal_fixed31_32_mul(grph_sat, matrix[0]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)) */
-+	matrix[0] = dal_fixed31_32_add(luma_r, matrix[0]);
-+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) *
-+	 * K2)) */
-+	matrix[0] = dal_fixed31_32_mul(grph_cont, matrix[0]);
-+
-+	/* COEF_1_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 +
-+	 * Sin(GrphHue) * K4)) */
-+	/* (Cos(GrphHue) * K3 + Sin(GrphHue) * K4) */
-+	matrix[1] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k3),
-+			dal_fixed31_32_mul(sin_grph_hue, k4));
-+	/* GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4) */
-+	matrix[1] = dal_fixed31_32_mul(grph_sat, matrix[1]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)) */
-+	matrix[1] = dal_fixed31_32_add(luma_g, matrix[1]);
-+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) *
-+	 * K4)) */
-+	matrix[1] = dal_fixed31_32_mul(grph_cont, matrix[1]);
-+
-+	/* COEF_1_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 +
-+	 * Sin(GrphHue) * K6)) */
-+	/* (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k5),
-+			dal_fixed31_32_mul(sin_grph_hue, k6));
-+	/* GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] = dal_fixed31_32_mul(grph_sat, matrix[2]);
-+	/* LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6) */
-+	matrix[2] = dal_fixed31_32_add(luma_b, matrix[2]);
-+	/* GrphCont  * (LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) *
-+	 * K6)) */
-+	matrix[2] = dal_fixed31_32_mul(grph_cont, matrix[2]);
-+
-+	/* COEF_1_4 = GrphBright */
-+	matrix[3] = grph_bright;
-+
-+	/* COEF_2_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 +
-+	 * Sin(GrphHue) * K8)) */
-+	/* (Cos(GrphHue) * K7 + Sin(GrphHue) * K8) */
-+	matrix[4] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k7),
-+			dal_fixed31_32_mul(sin_grph_hue, k8));
-+	/* GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8) */
-+	matrix[4] = dal_fixed31_32_mul(grph_sat, matrix[4]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)) */
-+	matrix[4] = dal_fixed31_32_add(luma_r, matrix[4]);
-+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) *
-+	 * K8)) */
-+	matrix[4] = dal_fixed31_32_mul(grph_cont, matrix[4]);
-+
-+	/* COEF_2_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 +
-+	 * Sin(GrphHue) * K10)) */
-+	/* (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k9),
-+			dal_fixed31_32_mul(sin_grph_hue, k10));
-+	/* GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] = dal_fixed31_32_mul(grph_sat, matrix[5]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10)) */
-+	matrix[5] = dal_fixed31_32_add(luma_g, matrix[5]);
-+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) *
-+	 * K10)) */
-+	matrix[5] = dal_fixed31_32_mul(grph_cont, matrix[5]);
-+
-+	/*  COEF_2_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 +
-+	 * Sin(GrphHue) * K12)) */
-+	/* (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k11),
-+			dal_fixed31_32_mul(sin_grph_hue, k12));
-+	/* GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] = dal_fixed31_32_mul(grph_sat, matrix[6]);
-+	/*  (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12)) */
-+	matrix[6] = dal_fixed31_32_add(luma_b, matrix[6]);
-+	/* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) *
-+	 * K12)) */
-+	matrix[6] = dal_fixed31_32_mul(grph_cont, matrix[6]);
-+
-+	/* COEF_2_4 = GrphBright */
-+	matrix[7] = grph_bright;
-+
-+	/* COEF_3_1 = GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 +
-+	 * Sin(GrphHue) * K14)) */
-+	/* (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k13),
-+			dal_fixed31_32_mul(sin_grph_hue, k14));
-+	/* GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] = dal_fixed31_32_mul(grph_sat, matrix[8]);
-+	/* (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
-+	matrix[8] = dal_fixed31_32_add(luma_r, matrix[8]);
-+	/* GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) *
-+	 * K14)) */
-+	matrix[8] = dal_fixed31_32_mul(grph_cont, matrix[8]);
-+
-+	/* COEF_3_2    = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 +
-+	 * Sin(GrphHue) * K16)) */
-+	/* GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16) */
-+	matrix[9] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k15),
-+			dal_fixed31_32_mul(sin_grph_hue, k16));
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
-+	matrix[9] = dal_fixed31_32_mul(grph_sat, matrix[9]);
-+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
-+	matrix[9] = dal_fixed31_32_add(luma_g, matrix[9]);
-+	 /* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) *
-+	  * K16)) */
-+	matrix[9] = dal_fixed31_32_mul(grph_cont, matrix[9]);
-+
-+	/*  COEF_3_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 +
-+	 * Sin(GrphHue) * K18)) */
-+	/* (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] =
-+		dal_fixed31_32_add(
-+			dal_fixed31_32_mul(cos_grph_hue, k17),
-+			dal_fixed31_32_mul(sin_grph_hue, k18));
-+	/*  GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] = dal_fixed31_32_mul(grph_sat, matrix[10]);
-+	/* (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
-+	matrix[10] = dal_fixed31_32_add(luma_b, matrix[10]);
-+	 /* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) *
-+	  * K18)) */
-+	matrix[10] = dal_fixed31_32_mul(grph_cont, matrix[10]);
-+
-+	/*  COEF_3_4    = GrphBright */
-+	matrix[11] = grph_bright;
-+
-+	tbl_entry.color_space = adjust->c_space;
-+
-+	convert_float_matrix(tbl_entry.regval, matrix, OUTPUT_CSC_MATRIX_SIZE);
-+
-+	program_color_matrix(
-+		opp80, &tbl_entry, adjust->color_adjust_option);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_rgb_limited_range_adjustment
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for sRGB limited color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_rgb_limited_range_adjustment(
-+	struct dce80_opp *opp80,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct out_csc_color_matrix reg_matrix;
-+	struct fixed31_32 change_matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct dc_csc_adjustments adjustments;
-+	struct fixed31_32 ideals[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	prepare_tv_rgb_ideal(ideals);
-+
-+	setup_adjustments(adjust, &adjustments);
-+
-+	calculate_adjustments(ideals, &adjustments, matrix);
-+
-+	dm_memmove(change_matrix, matrix, sizeof(matrix));
-+
-+	/* from 1 -> 3 */
-+	matrix[8] = change_matrix[0];
-+	matrix[9] = change_matrix[1];
-+	matrix[10] = change_matrix[2];
-+	matrix[11] = change_matrix[3];
-+
-+	/* from 2 -> 1 */
-+	matrix[0] = change_matrix[4];
-+	matrix[1] = change_matrix[5];
-+	matrix[2] = change_matrix[6];
-+	matrix[3] = change_matrix[7];
-+
-+	/* from 3 -> 2 */
-+	matrix[4] = change_matrix[8];
-+	matrix[5] = change_matrix[9];
-+	matrix[6] = change_matrix[10];
-+	matrix[7] = change_matrix[11];
-+
-+	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+
-+	setup_reg_format(matrix, reg_matrix.regval);
-+
-+	program_color_matrix(opp80, &reg_matrix, GRPH_COLOR_MATRIX_SW);
-+}
-+
-+static void prepare_yuv_ideal(
-+	bool b601,
-+	struct fixed31_32 *matrix)
-+{
-+	static const int32_t matrix_1[] = {
-+		25578516, 50216016, 9752344, 6250000,
-+		-14764391, -28985609, 43750000, 50000000,
-+		43750000, -36635164, -7114836, 50000000
-+	};
-+
-+	static const int32_t matrix_2[] = {
-+		18187266, 61183125, 6176484, 6250000,
-+		-10025059, -33724941, 43750000, 50000000,
-+		43750000, -39738379, -4011621, 50000000
-+	};
-+
-+	const int32_t *matrix_x = b601 ? matrix_1 : matrix_2;
-+
-+	uint32_t i = 0;
-+
-+	do {
-+		matrix[i] = dal_fixed31_32_from_fraction(
-+			matrix_x[i],
-+			100000000);
-+		++i;
-+	} while (i != ARRAY_SIZE(matrix_1));
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_yuv_adjustment
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and program color adjustments for YUV  color spaces
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void set_yuv_adjustment(
-+	struct dce80_opp *opp80,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR601_YONLY);
-+	struct out_csc_color_matrix reg_matrix;
-+	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
-+	struct dc_csc_adjustments adjustments;
-+	struct fixed31_32 ideals[OUTPUT_CSC_MATRIX_SIZE];
-+
-+	prepare_yuv_ideal(b601, ideals);
-+
-+	setup_adjustments(adjust, &adjustments);
-+
-+	if ((adjust->c_space == COLOR_SPACE_YCBCR601_YONLY) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR709_YONLY))
-+		calculate_adjustments_y_only(
-+			ideals, &adjustments, matrix);
-+	else
-+		calculate_adjustments(
-+			ideals, &adjustments, matrix);
-+
-+	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+
-+	setup_reg_format(matrix, reg_matrix.regval);
-+
-+	program_color_matrix(opp80, &reg_matrix, GRPH_COLOR_MATRIX_SW);
-+}
-+
-+static bool configure_graphics_mode(
-+	struct dce80_opp *opp80,
-+	enum csc_color_mode config,
-+	enum graphics_csc_adjust_type csc_adjust_type,
-+	enum color_space color_space)
-+{
-+	struct dc_context *ctx = opp80->base.ctx;
-+	uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		OUTPUT_CSC_CONTROL,
-+		OUTPUT_CSC_GRPH_MODE);
-+
-+	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
-+		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
-+			set_reg_field_value(
-+				value,
-+				4,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+		} else {
-+
-+			switch (color_space) {
-+			case COLOR_SPACE_SRGB_FULL_RANGE:
-+				/* by pass */
-+				set_reg_field_value(
-+					value,
-+					0,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+				/* TV RGB */
-+				set_reg_field_value(
-+					value,
-+					1,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			case COLOR_SPACE_YCBCR601:
-+			case COLOR_SPACE_YPBPR601:
-+			case COLOR_SPACE_YCBCR601_YONLY:
-+				/* YCbCr601 */
-+				set_reg_field_value(
-+					value,
-+					2,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			case COLOR_SPACE_YCBCR709:
-+			case COLOR_SPACE_YPBPR709:
-+			case COLOR_SPACE_YCBCR709_YONLY:
-+				/* YCbCr709 */
-+				set_reg_field_value(
-+					value,
-+					3,
-+					OUTPUT_CSC_CONTROL,
-+					OUTPUT_CSC_GRPH_MODE);
-+				break;
-+			default:
-+				return false;
-+			}
-+		}
-+	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB_FULL_RANGE:
-+			/* by pass */
-+			set_reg_field_value(
-+				value,
-+				0,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+			/* TV RGB */
-+			set_reg_field_value(
-+				value,
-+				1,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YPBPR601:
-+		case COLOR_SPACE_YCBCR601_YONLY:
-+			/* YCbCr601 */
-+			set_reg_field_value(
-+				value,
-+				2,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YPBPR709:
-+		case COLOR_SPACE_YCBCR709_YONLY:
-+			 /* YCbCr709 */
-+			set_reg_field_value(
-+				value,
-+				3,
-+				OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_GRPH_MODE);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else
-+		/* by pass */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_GRPH_MODE);
-+
-+	addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	return true;
-+}
-+
-+void dce80_opp_set_csc_adjustment(
-+	struct output_pixel_processor *opp,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+
-+	/* Apply color adjustments: brightness, saturation, hue, contrast and
-+	 * CSC. No need for different color space routine, color space defines
-+	 * the ideal values only, but keep original design to allow quick switch
-+	 * to the old legacy routines */
-+	switch (adjust->c_space) {
-+	case COLOR_SPACE_SRGB_FULL_RANGE:
-+		set_rgb_adjustment_legacy(opp80, adjust);
-+		break;
-+	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		set_rgb_limited_range_adjustment(
-+			opp80, adjust);
-+		break;
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_YONLY:
-+	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YPBPR601:
-+	case COLOR_SPACE_YPBPR709:
-+		set_yuv_adjustment(opp80, adjust);
-+		break;
-+	default:
-+		set_rgb_adjustment_legacy(opp80, adjust);
-+		break;
-+	}
-+
-+	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-+	configure_graphics_mode(opp80, config, adjust->csc_adjust_type,
-+		adjust->c_space);
-+}
-+
-+void dce80_opp_set_csc_default(
-+	struct output_pixel_processor *opp,
-+	const struct default_adjustment *default_adjust)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
-+
-+	if (default_adjust->force_hw_default == false) {
-+		const struct out_csc_color_matrix *elm;
-+		/* currently parameter not in use */
-+		enum grph_color_adjust_option option =
-+			GRPH_COLOR_MATRIX_HW_DEFAULT;
-+		uint32_t i;
-+		/*
-+		 * HW default false we program locally defined matrix
-+		 * HW default true  we use predefined hw matrix and we
-+		 * do not need to program matrix
-+		 * OEM wants the HW default via runtime parameter.
-+		 */
-+		option = GRPH_COLOR_MATRIX_SW;
-+
-+		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
-+			elm = &global_color_matrix[i];
-+			if (elm->color_space != default_adjust->color_space)
-+				continue;
-+			/* program the matrix with default values from this
-+			 * file */
-+			program_color_matrix(opp80, elm, option);
-+			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+			break;
-+		}
-+	}
-+
-+	/* configure the what we programmed :
-+	 * 1. Default values from this file
-+	 * 2. Use hardware default from ROM_A and we do not need to program
-+	 * matrix */
-+
-+	configure_graphics_mode(opp80, config,
-+		default_adjust->csc_adjust_type,
-+		default_adjust->color_space);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c
-new file mode 100644
-index 0000000..9d0a214
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c
-@@ -0,0 +1,577 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_opp.h"
-+
-+#define FMT_REG(reg)\
-+	(reg + opp80->offsets.fmt_offset)
-+
-+/**
-+ *	set_truncation
-+ *	1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
-+ *	2) enable truncation
-+ *	3) HW remove 12bit FMT support for DCE8 power saving reason.
-+ */
-+static void set_truncation(
-+		struct dce80_opp *opp80,
-+		const struct bit_depth_reduction_params *params)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+
-+	/*Disable truncation*/
-+	value = dm_read_reg(opp80->base.ctx, addr);
-+	set_reg_field_value(value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN);
-+	set_reg_field_value(value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH);
-+	set_reg_field_value(value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE);
-+
-+	dm_write_reg(opp80->base.ctx, addr, value);
-+
-+	/* no 10bpc trunc on DCE8*/
-+	if (params->flags.TRUNCATE_ENABLED == 0 ||
-+		params->flags.TRUNCATE_DEPTH == 2)
-+		return;
-+
-+	/*Set truncation depth and Enable truncation*/
-+	set_reg_field_value(value, 1,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN);
-+	set_reg_field_value(value, params->flags.TRUNCATE_MODE,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE);
-+	set_reg_field_value(value, params->flags.TRUNCATE_DEPTH,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH);
-+
-+	dm_write_reg(opp80->base.ctx, addr, value);
-+
-+}
-+
-+/**
-+ *	set_spatial_dither
-+ *	1) set spatial dithering mode: pattern of seed
-+ *	2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
-+ *	3) set random seed
-+ *	4) set random mode
-+ *		lfsr is reset every frame or not reset
-+ *		RGB dithering method
-+ *		0: RGB data are all dithered with x^28+x^3+1
-+ *		1: R data is dithered with x^28+x^3+1
-+ *		G data is dithered with x^28+X^9+1
-+ *		B data is dithered with x^28+x^13+1
-+ *		enable high pass filter or not
-+ *	5) enable spatical dithering
-+ */
-+static void set_spatial_dither(
-+	struct dce80_opp *opp80,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	uint32_t depth_cntl_value = 0;
-+	uint32_t dither_r_value = 0;
-+	uint32_t dither_g_value = 0;
-+	uint32_t dither_b_value = 0;
-+
-+	/*Disable spatial (random) dithering*/
-+	depth_cntl_value = dm_read_reg(opp80->base.ctx, addr);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE);
-+	set_reg_field_value(depth_cntl_value, 0,
-+		FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE);
-+
-+	dm_write_reg(opp80->base.ctx, addr, depth_cntl_value);
-+
-+	/* no 10bpc on DCE8*/
-+	if (params->flags.SPATIAL_DITHER_ENABLED == 0 ||
-+		params->flags.SPATIAL_DITHER_DEPTH == 2)
-+		return;
-+
-+	/*Set seed for random values for
-+	 * spatial dithering for R,G,B channels*/
-+	addr = FMT_REG(mmFMT_DITHER_RAND_R_SEED);
-+	set_reg_field_value(dither_r_value, params->r_seed_value,
-+		FMT_DITHER_RAND_R_SEED,
-+		FMT_RAND_R_SEED);
-+	dm_write_reg(opp80->base.ctx, addr, dither_r_value);
-+
-+	addr = FMT_REG(mmFMT_DITHER_RAND_G_SEED);
-+	set_reg_field_value(dither_g_value,
-+		params->g_seed_value,
-+		FMT_DITHER_RAND_G_SEED,
-+		FMT_RAND_G_SEED);
-+	dm_write_reg(opp80->base.ctx, addr, dither_g_value);
-+
-+	addr = FMT_REG(mmFMT_DITHER_RAND_B_SEED);
-+	set_reg_field_value(dither_b_value, params->b_seed_value,
-+		FMT_DITHER_RAND_B_SEED,
-+		FMT_RAND_B_SEED);
-+	dm_write_reg(opp80->base.ctx, addr, dither_b_value);
-+
-+	/* FMT_OFFSET_R_Cr  31:16 0x0 Setting the zero
-+	 * offset for the R/Cr channel, lower 4LSB
-+	 * is forced to zeros. Typically set to 0
-+	 * RGB and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_G_Y   31:16 0x0 Setting the zero
-+	 * offset for the G/Y  channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB
-+	 * and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_B_Cb  31:16 0x0 Setting the zero
-+	 * offset for the B/Cb channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB and
-+	 * 0x80000 YCbCr.
-+	 */
-+
-+	/*Set spatial dithering bit depth*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.SPATIAL_DITHER_DEPTH,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_DEPTH);
-+
-+	/* Set spatial dithering mode
-+	 * (default is Seed patterrn AAAA...)
-+	 */
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.SPATIAL_DITHER_MODE,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_MODE);
-+
-+	/*Reset only at startup*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.FRAME_RANDOM,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_RGB_RANDOM_ENABLE);
-+
-+	/*Set RGB data dithered with x^28+x^3+1*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.RGB_RANDOM,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_RGB_RANDOM_ENABLE);
-+
-+	/*Disable High pass filter*/
-+	set_reg_field_value(depth_cntl_value,
-+		params->flags.HIGHPASS_RANDOM,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_HIGHPASS_RANDOM_ENABLE);
-+
-+	/*Enable spatial dithering*/
-+	set_reg_field_value(depth_cntl_value,
-+		1,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_EN);
-+
-+	addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	dm_write_reg(opp80->base.ctx, addr, depth_cntl_value);
-+
-+}
-+
-+/**
-+ *	SetTemporalDither (Frame Modulation)
-+ *	1) set temporal dither depth
-+ *	2) select pattern: from hard-coded pattern or programmable pattern
-+ *	3) select optimized strips for BGR or RGB LCD sub-pixel
-+ *	4) set s matrix
-+ *	5) set t matrix
-+ *	6) set grey level for 0.25, 0.5, 0.75
-+ *	7) enable temporal dithering
-+ */
-+static void set_temporal_dither(
-+	struct dce80_opp *opp80,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	uint32_t addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	uint32_t value;
-+
-+	/*Disable temporal (frame modulation) dithering first*/
-+	value = dm_read_reg(opp80->base.ctx, addr);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_RESET);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_OFFSET);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_DEPTH);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_LEVEL);
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_25FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_50FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_75FRC_SEL);
-+
-+	dm_write_reg(opp80->base.ctx, addr, value);
-+
-+	/* no 10bpc dither on DCE8*/
-+	if (params->flags.FRAME_MODULATION_ENABLED == 0 ||
-+		params->flags.FRAME_MODULATION_DEPTH == 2)
-+		return;
-+
-+	/* Set temporal dithering depth*/
-+	set_reg_field_value(value,
-+		params->flags.FRAME_MODULATION_DEPTH,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_DEPTH);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_RESET);
-+
-+	set_reg_field_value(value,
-+		0,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_OFFSET);
-+
-+	/*Select legacy pattern based on FRC and Temporal level*/
-+	addr = FMT_REG(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL);
-+	dm_write_reg(opp80->base.ctx, addr, 0);
-+	/*Set s matrix*/
-+	addr = FMT_REG(
-+		mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX);
-+	dm_write_reg(opp80->base.ctx, addr, 0);
-+	/*Set t matrix*/
-+	addr = FMT_REG(
-+		mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX);
-+	dm_write_reg(opp80->base.ctx, addr, 0);
-+
-+	/*Select patterns for 0.25, 0.5 and 0.75 grey level*/
-+	set_reg_field_value(value,
-+		params->flags.TEMPORAL_LEVEL,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_LEVEL);
-+
-+	set_reg_field_value(value,
-+		params->flags.FRC25,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_25FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		params->flags.FRC50,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_50FRC_SEL);
-+
-+	set_reg_field_value(value,
-+		params->flags.FRC75,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_75FRC_SEL);
-+
-+	/*Enable bit reduction by temporal (frame modulation) dithering*/
-+	set_reg_field_value(value,
-+		1,
-+		FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN);
-+
-+	addr = FMT_REG(mmFMT_BIT_DEPTH_CONTROL);
-+	dm_write_reg(opp80->base.ctx, addr, value);
-+
-+}
-+
-+/**
-+ *	Set Clamping
-+ *	1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
-+ *		1 for 8 bpc
-+ *		2 for 10 bpc
-+ *		3 for 12 bpc
-+ *		7 for programable
-+ *	2) Enable clamp if Limited range requested
-+ */
-+static void set_clamping(
-+	struct dce80_opp *opp80,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	uint32_t clamp_cntl_value = 0;
-+	uint32_t red_clamp_value = 0;
-+	uint32_t green_clamp_value = 0;
-+	uint32_t blue_clamp_value = 0;
-+	uint32_t addr = FMT_REG(mmFMT_CLAMP_CNTL);
-+
-+	clamp_cntl_value = dm_read_reg(opp80->base.ctx, addr);
-+
-+	set_reg_field_value(clamp_cntl_value,
-+		0,
-+		FMT_CLAMP_CNTL,
-+		FMT_CLAMP_DATA_EN);
-+
-+	set_reg_field_value(clamp_cntl_value,
-+		0,
-+		FMT_CLAMP_CNTL,
-+		FMT_CLAMP_COLOR_FORMAT);
-+
-+	switch (params->clamping_level) {
-+	case CLAMPING_FULL_RANGE:
-+		break;
-+
-+	case CLAMPING_LIMITED_RANGE_8BPC:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		break;
-+
-+	case CLAMPING_LIMITED_RANGE_10BPC:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			2,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		break;
-+	case CLAMPING_LIMITED_RANGE_12BPC:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			3,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		break;
-+	case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
-+		set_reg_field_value(clamp_cntl_value,
-+			1,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN);
-+
-+		set_reg_field_value(clamp_cntl_value,
-+			7,
-+			FMT_CLAMP_CNTL,
-+			FMT_CLAMP_COLOR_FORMAT);
-+
-+		/*set the defaults*/
-+		set_reg_field_value(red_clamp_value,
-+			0x10,
-+			FMT_CLAMP_COMPONENT_R,
-+			FMT_CLAMP_LOWER_R);
-+
-+		set_reg_field_value(red_clamp_value,
-+			0xFEF,
-+			FMT_CLAMP_COMPONENT_R,
-+			FMT_CLAMP_UPPER_R);
-+
-+		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_R);
-+		dm_write_reg(opp80->base.ctx, addr, red_clamp_value);
-+
-+		set_reg_field_value(green_clamp_value,
-+			0x10,
-+			FMT_CLAMP_COMPONENT_G,
-+			FMT_CLAMP_LOWER_G);
-+
-+		set_reg_field_value(green_clamp_value,
-+			0xFEF,
-+			FMT_CLAMP_COMPONENT_G,
-+			FMT_CLAMP_UPPER_G);
-+
-+		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_G);
-+		dm_write_reg(opp80->base.ctx, addr, green_clamp_value);
-+
-+		set_reg_field_value(blue_clamp_value,
-+			0x10,
-+			FMT_CLAMP_COMPONENT_B,
-+			FMT_CLAMP_LOWER_B);
-+
-+		set_reg_field_value(blue_clamp_value,
-+			0xFEF,
-+			FMT_CLAMP_COMPONENT_B,
-+			FMT_CLAMP_UPPER_B);
-+
-+		addr = FMT_REG(mmFMT_CLAMP_COMPONENT_B);
-+		dm_write_reg(opp80->base.ctx, addr, blue_clamp_value);
-+
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	addr = FMT_REG(mmFMT_CLAMP_CNTL);
-+	/*Set clamp control*/
-+	dm_write_reg(opp80->base.ctx, addr, clamp_cntl_value);
-+
-+}
-+
-+/**
-+ *	set_pixel_encoding
-+ *
-+ *	Set Pixel Encoding
-+ *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
-+ *		1: YCbCr 4:2:2
-+ */
-+static void set_pixel_encoding(
-+	struct dce80_opp *opp80,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	uint32_t fmt_cntl_value;
-+	uint32_t addr = FMT_REG(mmFMT_CONTROL);
-+
-+	/*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/
-+	fmt_cntl_value = dm_read_reg(opp80->base.ctx, addr);
-+
-+	set_reg_field_value(fmt_cntl_value,
-+		0,
-+		FMT_CONTROL,
-+		FMT_PIXEL_ENCODING);
-+
-+	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+		set_reg_field_value(fmt_cntl_value,
-+			1,
-+			FMT_CONTROL,
-+			FMT_PIXEL_ENCODING);
-+
-+		/*00 - Pixels drop mode ,01 - Pixels average mode*/
-+		set_reg_field_value(fmt_cntl_value,
-+			0,
-+			FMT_CONTROL,
-+			FMT_SUBSAMPLING_MODE);
-+
-+		/*00 - Cb before Cr ,01 - Cr before Cb*/
-+		set_reg_field_value(fmt_cntl_value,
-+			0,
-+			FMT_CONTROL,
-+			FMT_SUBSAMPLING_ORDER);
-+	}
-+	dm_write_reg(opp80->base.ctx, addr, fmt_cntl_value);
-+
-+}
-+
-+void dce80_opp_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+
-+	set_truncation(opp80, params);
-+	set_spatial_dither(opp80, params);
-+	set_temporal_dither(opp80, params);
-+}
-+
-+void dce80_opp_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+
-+	set_clamping(opp80, params);
-+	set_pixel_encoding(opp80, params);
-+}
-+
-+void dce80_opp_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+	uint32_t value;
-+	bool enable_dyn_exp = false;
-+	uint32_t addr = FMT_REG(mmFMT_DYNAMIC_EXP_CNTL);
-+
-+	value = dm_read_reg(opp->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-+	set_reg_field_value(value, 0,
-+		FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE);
-+
-+	/* From HW programming guide:
-+		FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output
-+		FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/
-+	if (color_sp == COLOR_SPACE_SRGB_FULL_RANGE)
-+		enable_dyn_exp = true;
-+
-+	/*00 - 10-bit -> 12-bit dynamic expansion*/
-+	/*01 - 8-bit  -> 12-bit dynamic expansion*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		switch (color_dpth) {
-+		case COLOR_DEPTH_888:
-+			set_reg_field_value(value, enable_dyn_exp ? 1:0,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-+			set_reg_field_value(value, 1,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE);
-+			break;
-+		case COLOR_DEPTH_101010:
-+			set_reg_field_value(value, enable_dyn_exp ? 1:0,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN);
-+			set_reg_field_value(value, 0,
-+				FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	dm_write_reg(opp->ctx, addr, value);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-new file mode 100644
-index 0000000..ef95e98
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-@@ -0,0 +1,546 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_opp.h"
-+#include "gamma_types.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + opp80->offsets.dcp_offset)
-+
-+#define DCFE_REG(reg)\
-+	(reg + opp80->offsets.crtc_offset)
-+
-+enum {
-+	MAX_PWL_ENTRY = 128,
-+	MAX_REGIONS_NUMBER = 16
-+
-+};
-+
-+struct curve_config {
-+	uint32_t offset;
-+	int8_t segments[MAX_REGIONS_NUMBER];
-+	int8_t begin;
-+};
-+
-+/*
-+ *****************************************************************************
-+ *  Function: regamma_config_regions_and_segments
-+ *
-+ *     build regamma curve by using predefined hw points
-+ *     uses interface parameters ,like EDID coeff.
-+ *
-+ * @param   : parameters   interface parameters
-+ *  @return void
-+ *
-+ *  @note
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void regamma_config_regions_and_segments(
-+	struct dce80_opp *opp80, const struct regamma_params *params)
-+{
-+	const struct gamma_curve *curve;
-+	uint32_t value = 0;
-+
-+	{
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[0].custom_float_x,
-+			REGAMMA_CNTLA_START_CNTL,
-+			REGAMMA_CNTLA_EXP_REGION_START);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			REGAMMA_CNTLA_START_CNTL,
-+			REGAMMA_CNTLA_EXP_REGION_START_SEGMENT);
-+
-+		dm_write_reg(opp80->base.ctx,
-+				DCP_REG(mmREGAMMA_CNTLA_START_CNTL),
-+				value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[0].custom_float_slope,
-+			REGAMMA_CNTLA_SLOPE_CNTL,
-+			REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_SLOPE_CNTL), value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_x,
-+			REGAMMA_CNTLA_END_CNTL1,
-+			REGAMMA_CNTLA_EXP_REGION_END);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_END_CNTL1), value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[2].custom_float_slope,
-+			REGAMMA_CNTLA_END_CNTL2,
-+			REGAMMA_CNTLA_EXP_REGION_END_BASE);
-+
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_y,
-+			REGAMMA_CNTLA_END_CNTL2,
-+			REGAMMA_CNTLA_EXP_REGION_END_SLOPE);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_END_CNTL2), value);
-+	}
-+
-+	curve = params->arr_curve_points;
-+
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_0_1,
-+			REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS);
-+
-+		dm_write_reg(
-+			opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_0_1),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_2_3,
-+			REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_2_3),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_4_5,
-+			REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_4_5),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_6_7,
-+			REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_6_7),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_8_9,
-+			REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_8_9),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_10_11,
-+			REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_10_11),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_12_13,
-+			REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_12_13),
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			REGAMMA_CNTLA_REGION_14_15,
-+			REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+			DCP_REG(mmREGAMMA_CNTLA_REGION_14_15),
-+			value);
-+	}
-+}
-+
-+static void program_pwl(
-+	struct dce80_opp *opp80,
-+	const struct regamma_params *params)
-+{
-+	uint32_t value;
-+
-+	{
-+		uint8_t max_tries = 10;
-+		uint8_t counter = 0;
-+
-+		/* Power on LUT memory */
-+		value = dm_read_reg(opp80->base.ctx,
-+				DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL));
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCFE_MEM_LIGHT_SLEEP_CNTL,
-+			REGAMMA_LUT_LIGHT_SLEEP_DIS);
-+
-+		dm_write_reg(opp80->base.ctx,
-+				DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL), value);
-+
-+		while (counter < max_tries) {
-+			value =
-+				dm_read_reg(
-+					opp80->base.ctx,
-+					DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL));
-+
-+			if (get_reg_field_value(
-+				value,
-+				DCFE_MEM_LIGHT_SLEEP_CNTL,
-+				REGAMMA_LUT_MEM_PWR_STATE) == 0)
-+				break;
-+
-+			++counter;
-+		}
-+
-+		if (counter == max_tries) {
-+			dal_logger_write(opp80->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: regamma lut was not powered on "
-+				"in a timely manner,"
-+				" programming still proceeds\n",
-+				__func__);
-+		}
-+	}
-+
-+	value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		7,
-+		REGAMMA_LUT_WRITE_EN_MASK,
-+		REGAMMA_LUT_WRITE_EN_MASK);
-+
-+	dm_write_reg(opp80->base.ctx,
-+		DCP_REG(mmREGAMMA_LUT_WRITE_EN_MASK), value);
-+	dm_write_reg(opp80->base.ctx,
-+		DCP_REG(mmREGAMMA_LUT_INDEX), 0);
-+
-+	/* Program REGAMMA_LUT_DATA */
-+	{
-+		const uint32_t addr = DCP_REG(mmREGAMMA_LUT_DATA);
-+
-+		uint32_t i = 0;
-+
-+		const struct pwl_result_data *rgb =
-+				params->rgb_resulted;
-+
-+		while (i != params->hw_points_num) {
-+			dm_write_reg(opp80->base.ctx, addr, rgb->red_reg);
-+			dm_write_reg(opp80->base.ctx, addr, rgb->green_reg);
-+			dm_write_reg(opp80->base.ctx, addr, rgb->blue_reg);
-+
-+			dm_write_reg(opp80->base.ctx, addr,
-+				rgb->delta_red_reg);
-+			dm_write_reg(opp80->base.ctx, addr,
-+				rgb->delta_green_reg);
-+			dm_write_reg(opp80->base.ctx, addr,
-+				rgb->delta_blue_reg);
-+
-+			++rgb;
-+			++i;
-+		}
-+	}
-+
-+	/*  we are done with DCP LUT memory; re-enable low power mode */
-+	value = dm_read_reg(opp80->base.ctx,
-+			DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL));
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFE_MEM_LIGHT_SLEEP_CNTL,
-+		REGAMMA_LUT_LIGHT_SLEEP_DIS);
-+
-+	dm_write_reg(opp80->base.ctx, DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+			value);
-+}
-+
-+
-+void dce80_opp_power_on_regamma_lut(
-+	struct output_pixel_processor *opp,
-+	bool power_on)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+
-+	uint32_t value =
-+		dm_read_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL));
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFE_MEM_LIGHT_SLEEP_CNTL,
-+		REGAMMA_LUT_LIGHT_SLEEP_DIS);
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFE_MEM_LIGHT_SLEEP_CNTL,
-+		DCP_LUT_LIGHT_SLEEP_DIS);
-+
-+	dm_write_reg(opp->ctx, DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL), value);
-+}
-+
-+bool dce80_opp_program_regamma_pwl(
-+	struct output_pixel_processor *opp,
-+	const struct regamma_params *params)
-+{
-+
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+
-+	regamma_config_regions_and_segments(opp80, params);
-+
-+	program_pwl(opp80, params);
-+
-+	return true;
-+}
-+
-+void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp,
-+		enum opp_regamma mode)
-+{
-+	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-+	uint32_t value = dm_read_reg(opp80->base.ctx,
-+				DCP_REG(mmREGAMMA_CONTROL));
-+
-+	set_reg_field_value(
-+		value,
-+		mode,
-+		REGAMMA_CONTROL,
-+		GRPH_REGAMMA_MODE);
-+
-+	dm_write_reg(opp80->base.ctx, DCP_REG(mmREGAMMA_CONTROL), value);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-new file mode 100644
-index 0000000..1eeb469
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -0,0 +1,1267 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "../virtual/virtual_stream_encoder.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "dce110/dce110_mem_input.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce80/dce80_timing_generator.h"
-+#include "dce80/dce80_link_encoder.h"
-+#include "dce110/dce110_link_encoder.h"
-+#include "dce80/dce80_mem_input.h"
-+#include "dce80/dce80_ipp.h"
-+#include "dce80/dce80_transform.h"
-+#include "dce110/dce110_stream_encoder.h"
-+#include "dce80/dce80_stream_encoder.h"
-+#include "dce80/dce80_opp.h"
-+#include "dce110/dce110_ipp.h"
-+#include "dce110/dce110_clock_source.h"
-+
-+#include "dce/dce_8_0_d.h"
-+
-+/* TODO remove this include */
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
-+#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
-+#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
-+#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
-+#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
-+#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
-+#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
-+#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
-+#endif
-+
-+enum dce80_clk_src_array_id {
-+	DCE80_CLK_SRC_PLL0 = 0,
-+	DCE80_CLK_SRC_PLL1,
-+	DCE80_CLK_SRC_PLL2,
-+	DCE80_CLK_SRC_EXT,
-+
-+	DCE80_CLK_SRC_TOTAL
-+};
-+
-+#define DCE11_DIG_FE_CNTL 0x4a00
-+#define DCE11_DIG_BE_CNTL 0x4a47
-+#define DCE11_DP_SEC 0x4ac3
-+
-+static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
-+		{
-+			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		}
-+};
-+
-+static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = {
-+	{
-+		.dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	}
-+};
-+
-+static const struct dce80_transform_reg_offsets dce80_xfm_offsets[] = {
-+{
-+	.scl_offset = (mmSCL_CONTROL - mmSCL_CONTROL),
-+	.crtc_offset = (mmDCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmGRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
-+	.crtc_offset = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
-+	.crtc_offset = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{
-+	.scl_offset = (mmSCL3_SCL_CONTROL - mmSCL_CONTROL),
-+	.crtc_offset = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB3_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{
-+	.scl_offset = (mmSCL4_SCL_CONTROL - mmSCL_CONTROL),
-+	.crtc_offset = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB4_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{
-+	.scl_offset = (mmSCL5_SCL_CONTROL - mmSCL_CONTROL),
-+	.crtc_offset = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL -
-+					mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB5_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+}
-+};
-+
-+static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-+}
-+};
-+
-+static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
-+		.BL_PWM_CNTL = mmBL_PWM_CNTL,
-+		.BL_PWM_GRP1_REG_LOCK = mmBL_PWM_GRP1_REG_LOCK,
-+		.BL_PWM_PERIOD_CNTL = mmBL_PWM_PERIOD_CNTL,
-+		.LVTMA_PWRSEQ_CNTL = mmLVTMA_PWRSEQ_CNTL,
-+		.LVTMA_PWRSEQ_STATE = mmLVTMA_PWRSEQ_STATE
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	.AUX_CONTROL = mmDP_AUX ## id ## _AUX_CONTROL,\
-+	.AUX_DPHY_RX_CONTROL0 = mmDP_AUX ## id ## _AUX_DPHY_RX_CONTROL0\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+	aux_regs(0),
-+	aux_regs(1),
-+	aux_regs(2),
-+	aux_regs(3),
-+	aux_regs(4),
-+	aux_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	.DIG_BE_CNTL = mmDIG ## id ## _DIG_BE_CNTL,\
-+	.DIG_BE_EN_CNTL = mmDIG ## id ## _DIG_BE_EN_CNTL,\
-+	.DP_CONFIG = mmDP ## id ## _DP_CONFIG,\
-+	.DP_DPHY_CNTL = mmDP ## id ## _DP_DPHY_CNTL,\
-+	.DP_DPHY_INTERNAL_CTRL = mmDP ## id ## _DP_DPHY_INTERNAL_CTRL,\
-+	.DP_DPHY_PRBS_CNTL = mmDP ## id ## _DP_DPHY_PRBS_CNTL,\
-+	.DP_DPHY_SYM0 = mmDP ## id ## _DP_DPHY_SYM0,\
-+	.DP_DPHY_SYM1 = mmDP ## id ## _DP_DPHY_SYM1,\
-+	.DP_DPHY_SYM2 = mmDP ## id ## _DP_DPHY_SYM2,\
-+	.DP_DPHY_TRAINING_PATTERN_SEL = mmDP ## id ## _DP_DPHY_TRAINING_PATTERN_SEL,\
-+	.DP_LINK_CNTL = mmDP ## id ## _DP_LINK_CNTL,\
-+	.DP_LINK_FRAMING_CNTL = mmDP ## id ## _DP_LINK_FRAMING_CNTL,\
-+	.DP_MSE_SAT0 = mmDP ## id ## _DP_MSE_SAT0,\
-+	.DP_MSE_SAT1 = mmDP ## id ## _DP_MSE_SAT1,\
-+	.DP_MSE_SAT2 = mmDP ## id ## _DP_MSE_SAT2,\
-+	.DP_MSE_SAT_UPDATE = mmDP ## id ## _DP_MSE_SAT_UPDATE,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5)
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	.AFMT_AVI_INFO0 = mmDIG ## id ## _AFMT_AVI_INFO0,\
-+	.AFMT_AVI_INFO1 = mmDIG ## id ## _AFMT_AVI_INFO1,\
-+	.AFMT_AVI_INFO2 = mmDIG ## id ## _AFMT_AVI_INFO2,\
-+	.AFMT_AVI_INFO3 = mmDIG ## id ## _AFMT_AVI_INFO3,\
-+	.AFMT_GENERIC_0 = mmDIG ## id ## _AFMT_GENERIC_0,\
-+	.AFMT_GENERIC_7 = mmDIG ## id ## _AFMT_GENERIC_7,\
-+	.AFMT_GENERIC_HDR = mmDIG ## id ## _AFMT_GENERIC_HDR,\
-+	.AFMT_INFOFRAME_CONTROL0 = mmDIG ## id ## _AFMT_INFOFRAME_CONTROL0,\
-+	.AFMT_VBI_PACKET_CONTROL = mmDIG ## id ## _AFMT_VBI_PACKET_CONTROL,\
-+	.DIG_FE_CNTL = mmDIG ## id ## _DIG_FE_CNTL,\
-+	.DP_MSE_RATE_CNTL = mmDP ## id ## _DP_MSE_RATE_CNTL,\
-+	.DP_MSE_RATE_UPDATE = mmDP ## id ## _DP_MSE_RATE_UPDATE,\
-+	.DP_PIXEL_FORMAT = mmDP ## id ## _DP_PIXEL_FORMAT,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_STEER_FIFO = mmDP ## id ## _DP_STEER_FIFO,\
-+	.DP_VID_M = mmDP ## id ## _DP_VID_M,\
-+	.DP_VID_N = mmDP ## id ## _DP_VID_N,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL,\
-+	.DP_VID_TIMING = mmDP ## id ## _DP_VID_TIMING,\
-+	.HDMI_CONTROL = mmDIG ## id ## _HDMI_CONTROL,\
-+	.HDMI_GC = mmDIG ## id ## _HDMI_GC,\
-+	.HDMI_GENERIC_PACKET_CONTROL0 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL0,\
-+	.HDMI_GENERIC_PACKET_CONTROL1 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL1,\
-+	.HDMI_INFOFRAME_CONTROL0 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL0,\
-+	.HDMI_INFOFRAME_CONTROL1 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL1,\
-+	.HDMI_VBI_PACKET_CONTROL = mmDIG ## id ## _HDMI_VBI_PACKET_CONTROL,\
-+	.TMDS_CNTL = mmDIG ## id ## _TMDS_CNTL\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5)
-+};
-+
-+static const struct dce110_clk_src_reg_offsets dce80_clk_src_reg_offsets[] = {
-+	{
-+		.pll_cntl = mmDCCG_PLL0_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK0_RESYNC_CNTL
-+	},
-+	{
-+		.pll_cntl = mmDCCG_PLL1_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK1_RESYNC_CNTL
-+	},
-+	{
-+		.pll_cntl = mmDCCG_PLL2_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK2_RESYNC_CNTL
-+	}
-+};
-+
-+static struct timing_generator *dce80_timing_generator_create(
-+		struct adapter_service *as,
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		dm_alloc(ctx, sizeof(struct dce110_timing_generator));
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	if (dce80_timing_generator_construct(tg110, as, ctx, instance, offsets))
-+		return &tg110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, tg110);
-+	return NULL;
-+}
-+
-+static struct stream_encoder *dce80_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx,
-+	struct dc_bios *dcb,
-+	const struct dce110_stream_enc_registers *regs)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		dm_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce80_stream_encoder_construct(enc110, ctx, dcb, eng_id, regs))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, enc110);
-+	return NULL;
-+}
-+
-+
-+static struct mem_input *dce80_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets)
-+{
-+	struct dce110_mem_input *mem_input80 =
-+		dm_alloc(ctx, sizeof(struct dce110_mem_input));
-+
-+	if (!mem_input80)
-+		return NULL;
-+
-+	if (dce80_mem_input_construct(mem_input80,
-+			ctx, inst, offsets))
-+		return &mem_input80->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, mem_input80);
-+	return NULL;
-+}
-+
-+static void dce80_transform_destroy(struct transform **xfm)
-+{
-+	dm_free((*xfm)->ctx, TO_DCE80_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce80_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce80_transform_reg_offsets *offsets)
-+{
-+	struct dce80_transform *transform =
-+		dm_alloc(ctx, sizeof(struct dce80_transform));
-+
-+	if (!transform)
-+		return NULL;
-+
-+	if (dce80_transform_construct(transform, ctx, inst, offsets))
-+		return &transform->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, transform);
-+	return NULL;
-+}
-+
-+static struct input_pixel_processor *dce80_ipp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offset)
-+{
-+	struct dce110_ipp *ipp =
-+		dm_alloc(ctx, sizeof(struct dce110_ipp));
-+
-+	if (!ipp)
-+		return NULL;
-+
-+	if (dce80_ipp_construct(ipp, ctx, inst, offset))
-+		return &ipp->base;
-+
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ctx, ipp);
-+	return NULL;
-+}
-+
-+struct link_encoder *dce80_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		dm_alloc(
-+		enc_init_data->ctx,
-+		sizeof(struct dce110_link_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce80_link_encoder_construct(
-+			enc110,
-+			enc_init_data,
-+			&link_enc_regs[enc_init_data->transmitter],
-+			&link_enc_aux_regs[enc_init_data->channel - 1],
-+			&link_enc_bl_regs))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(enc_init_data->ctx, enc110);
-+	return NULL;
-+}
-+
-+struct clock_source *dce80_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_reg_offsets *offsets)
-+{
-+	struct dce110_clk_src *clk_src =
-+		dm_alloc(ctx, sizeof(struct dce110_clk_src));
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id, offsets))
-+		return &clk_src->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce80_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	dm_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+void dce80_destruct_resource_pool(struct resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce80_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce80_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce80_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dm_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL)	{
-+			dm_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dm_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL) {
-+			dce80_clock_source_destroy(&pool->clock_sources[i]);
-+		}
-+	}
-+
-+	for (i = 0; i < pool->audio_count; i++)	{
-+		if (pool->audios[i] != NULL) {
-+			dal_audio_destroy(&pool->audios[i]);
-+		}
-+	}
-+
-+	if (pool->display_clock != NULL) {
-+		dal_display_clock_destroy(&pool->display_clock);
-+	}
-+
-+	if (pool->scaler_filter != NULL) {
-+		dal_scaler_filter_destroy(&pool->scaler_filter);
-+	}
-+	if (pool->irqs != NULL) {
-+		dal_irq_service_destroy(&pool->irqs);
-+	}
-+
-+	if (pool->adapter_srv != NULL) {
-+		dal_adapter_service_destroy(&pool->adapter_srv);
-+	}
-+}
-+
-+static struct clock_source *find_first_free_pll(
-+		struct resource_context *res_ctx)
-+{
-+	if (res_ctx->clock_source_ref_count[DCE80_CLK_SRC_PLL0] == 0) {
-+		return res_ctx->pool.clock_sources[DCE80_CLK_SRC_PLL0];
-+	}
-+	if (res_ctx->clock_source_ref_count[DCE80_CLK_SRC_PLL1] == 0) {
-+		return res_ctx->pool.clock_sources[DCE80_CLK_SRC_PLL1];
-+	}
-+	if (res_ctx->clock_source_ref_count[DCE80_CLK_SRC_PLL2] == 0) {
-+		return res_ctx->pool.clock_sources[DCE80_CLK_SRC_PLL2];
-+	}
-+
-+	return 0;
-+}
-+
-+static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-+{
-+	switch (crtc_id) {
-+	case CONTROLLER_ID_D0:
-+		return DTO_SOURCE_ID0;
-+	case CONTROLLER_ID_D1:
-+		return DTO_SOURCE_ID1;
-+	case CONTROLLER_ID_D2:
-+		return DTO_SOURCE_ID2;
-+	case CONTROLLER_ID_D3:
-+		return DTO_SOURCE_ID3;
-+	case CONTROLLER_ID_D4:
-+		return DTO_SOURCE_ID4;
-+	case CONTROLLER_ID_D5:
-+		return DTO_SOURCE_ID5;
-+	default:
-+		return DTO_SOURCE_UNKNOWN;
-+	}
-+}
-+
-+static void build_audio_output(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct audio_output *audio_output)
-+{
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	audio_output->engine_id = pipe_ctx->stream_enc->id;
-+
-+	audio_output->signal = pipe_ctx->signal;
-+
-+	/* audio_crtc_info  */
-+
-+	audio_output->crtc_info.h_total =
-+		stream->public.timing.h_total;
-+
-+	/* Audio packets are sent during actual CRTC blank physical signal, we
-+	 * need to specify actual active signal portion */
-+	audio_output->crtc_info.h_active =
-+			stream->public.timing.h_addressable
-+			+ stream->public.timing.h_border_left
-+			+ stream->public.timing.h_border_right;
-+
-+	audio_output->crtc_info.v_active =
-+			stream->public.timing.v_addressable
-+			+ stream->public.timing.v_border_top
-+			+ stream->public.timing.v_border_bottom;
-+
-+	audio_output->crtc_info.pixel_repetition = 1;
-+
-+	audio_output->crtc_info.interlaced =
-+			stream->public.timing.flags.INTERLACE;
-+
-+	audio_output->crtc_info.refresh_rate =
-+		(stream->public.timing.pix_clk_khz*1000)/
-+		(stream->public.timing.h_total*stream->public.timing.v_total);
-+
-+	audio_output->crtc_info.color_depth =
-+		stream->public.timing.display_color_depth;
-+
-+	audio_output->crtc_info.requested_pixel_clock =
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
-+
-+	/* TODO - Investigate why calculated pixel clk has to be
-+	 * requested pixel clk */
-+	audio_output->crtc_info.calculated_pixel_clock =
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
-+
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		audio_output->pll_info.dp_dto_source_clock_in_khz =
-+			dal_display_clock_get_dp_ref_clk_frequency(
-+				pipe_ctx->dis_clk);
-+	}
-+
-+	audio_output->pll_info.feed_back_divider =
-+			pipe_ctx->pll_settings.feedback_divider;
-+
-+	audio_output->pll_info.dto_source =
-+		translate_to_dto_source(
-+			pipe_ctx->pipe_idx + 1);
-+
-+	/* TODO hard code to enable for now. Need get from stream */
-+	audio_output->pll_info.ss_enabled = true;
-+
-+	audio_output->pll_info.ss_percentage =
-+			pipe_ctx->pll_settings.ss_percentage;
-+}
-+
-+static void get_pixel_clock_parameters(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct pixel_clk_params *pixel_clk_params)
-+{
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
-+	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
-+	pixel_clk_params->signal_type = stream->sink->public.sink_signal;
-+	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
-+	/* TODO: un-hardcode*/
-+	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+	pixel_clk_params->flags.ENABLE_SS = 0;
-+	pixel_clk_params->color_depth =
-+		stream->public.timing.display_color_depth;
-+	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-+}
-+
-+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
-+{
-+	/*TODO: unhardcode*/
-+	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
-+	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	pipe_ctx->max_hdmi_pixel_clock = 600000;
-+
-+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
-+	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-+		pipe_ctx->clock_source,
-+		&pipe_ctx->pix_clk_params,
-+		&pipe_ctx->pll_settings);
-+
-+	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
-+
-+	return DC_OK;
-+}
-+
-+static enum dc_status validate_mapped_resource(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	enum dc_status status = DC_OK;
-+	uint8_t i, j, k;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct core_link *link = stream->sink->link;
-+
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (!pipe_ctx->tg->funcs->validate_timing(
-+						pipe_ctx->tg, &stream->public.timing))
-+					return DC_FAIL_CONTROLLER_VALIDATE;
-+
-+				status = build_pipe_hw_param(pipe_ctx);
-+
-+				if (status != DC_OK)
-+					return status;
-+
-+				if (!link->link_enc->funcs->validate_output_with_stream(
-+						link->link_enc,
-+						pipe_ctx))
-+					return DC_FAIL_ENC_VALIDATE;
-+
-+				/* TODO: validate audio ASIC caps, encoder */
-+
-+				status = dc_link_validate_mode_timing(stream->sink,
-+						link,
-+						&stream->public.timing);
-+
-+				if (status != DC_OK)
-+					return status;
-+
-+				build_info_frame(pipe_ctx);
-+
-+				/* do not need to validate non root pipes */
-+				break;
-+			}
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce80_validate_bandwidth(
-+	const struct dc *dc,
-+	struct validate_context *context)
-+{
-+	uint8_t i;
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t number_of_displays = 0;
-+	uint8_t max_htaps = 1;
-+	uint8_t max_vtaps = 1;
-+	bool all_displays_in_sync = true;
-+	struct dc_crtc_timing prev_timing;
-+
-+	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct bw_calcs_input_single_display *disp = &context->
-+			bw_mode_data.displays_data[number_of_displays];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->ratios.vert.value == 0) {
-+			disp->graphics_scale_ratio = bw_int_to_fixed(1);
-+			disp->graphics_h_taps = 2;
-+			disp->graphics_v_taps = 2;
-+
-+			/* TODO: remove when bw formula accepts taps per
-+			 * display
-+			 */
-+			if (max_vtaps < 2)
-+				max_vtaps = 2;
-+			if (max_htaps < 2)
-+				max_htaps = 2;
-+
-+		} else {
-+			disp->graphics_scale_ratio =
-+				fixed31_32_to_bw_fixed(
-+					pipe_ctx->ratios.vert.value);
-+			disp->graphics_h_taps = pipe_ctx->taps.h_taps;
-+			disp->graphics_v_taps = pipe_ctx->taps.v_taps;
-+
-+			/* TODO: remove when bw formula accepts taps per
-+			 * display
-+			 */
-+			if (max_vtaps < pipe_ctx->taps.v_taps)
-+				max_vtaps = pipe_ctx->taps.v_taps;
-+			if (max_htaps < pipe_ctx->taps.h_taps)
-+				max_htaps = pipe_ctx->taps.h_taps;
-+		}
-+
-+		disp->graphics_src_width =
-+			pipe_ctx->stream->public.timing.h_addressable;
-+		disp->graphics_src_height =
-+			pipe_ctx->stream->public.timing.v_addressable;
-+		disp->h_total = pipe_ctx->stream->public.timing.h_total;
-+		disp->pixel_rate = bw_frc_to_fixed(
-+			pipe_ctx->stream->public.timing.pix_clk_khz, 1000);
-+
-+		/*TODO: get from surface*/
-+		disp->graphics_bytes_per_pixel = 4;
-+		disp->graphics_tiling_mode = bw_def_tiled;
-+
-+		/* DCE11 defaults*/
-+		disp->graphics_lb_bpc = 10;
-+		disp->graphics_interlace_mode = false;
-+		disp->fbc_enable = false;
-+		disp->lpt_enable = false;
-+		disp->graphics_stereo_mode = bw_def_mono;
-+		disp->underlay_mode = bw_def_none;
-+
-+		/*All displays will be synchronized if timings are all
-+		 * the same
-+		 */
-+		if (number_of_displays != 0 && all_displays_in_sync)
-+			if (dm_memcmp(&prev_timing,
-+				&pipe_ctx->stream->public.timing,
-+				sizeof(struct dc_crtc_timing)) != 0)
-+				all_displays_in_sync = false;
-+		if (number_of_displays == 0)
-+			prev_timing = pipe_ctx->stream->public.timing;
-+
-+		number_of_displays++;
-+	}
-+
-+	/* TODO: remove when bw formula accepts taps per
-+	 * display
-+	 */
-+	context->bw_mode_data.displays_data[0].graphics_v_taps = max_vtaps;
-+	context->bw_mode_data.displays_data[0].graphics_h_taps = max_htaps;
-+
-+	context->bw_mode_data.number_of_displays = number_of_displays;
-+	context->bw_mode_data.display_synchronization_enabled =
-+							all_displays_in_sync;
-+
-+	dal_logger_write(
-+		dc->ctx->logger,
-+		LOG_MAJOR_BWM,
-+		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-+		"%s: start",
-+		__func__);
-+
-+	if (!bw_calcs(
-+			dc->ctx,
-+			&dc->bw_dceip,
-+			&dc->bw_vbios,
-+			&context->bw_mode_data,
-+			&context->bw_results))
-+		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-+	else
-+		result =  DC_OK;
-+
-+	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
-+		dal_logger_write(dc->ctx->logger,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_MODE_VALIDATION,
-+			"%s: Bandwidth validation failed!",
-+			__func__);
-+
-+	if (dm_memcmp(&dc->current_context.bw_results,
-+			&context->bw_results, sizeof(context->bw_results))) {
-+		struct log_entry log_entry;
-+		dal_logger_open(
-+			dc->ctx->logger,
-+			&log_entry,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
-+		dal_logger_append(&log_entry, "%s: finish, numDisplays: %d\n"
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			__func__, number_of_displays,
-+			context->bw_results.nbp_state_change_wm_ns[0].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[0].a_mark,
-+			context->bw_results.urgent_wm_ns[0].b_mark,
-+			context->bw_results.urgent_wm_ns[0].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[1].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[1].a_mark,
-+			context->bw_results.urgent_wm_ns[1].b_mark,
-+			context->bw_results.urgent_wm_ns[1].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[2].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[2].a_mark,
-+			context->bw_results.urgent_wm_ns[2].b_mark,
-+			context->bw_results.urgent_wm_ns[2].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].a_mark,
-+			context->bw_results.stutter_mode_enable);
-+		dal_logger_append(&log_entry,
-+			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
-+			"sclk: %d sclk_sleep: %d yclk: %d blackout_duration: %d\n",
-+			context->bw_results.cpuc_state_change_enable,
-+			context->bw_results.cpup_state_change_enable,
-+			context->bw_results.nbp_state_change_enable,
-+			context->bw_results.all_displays_in_sync,
-+			context->bw_results.dispclk_khz,
-+			context->bw_results.required_sclk,
-+			context->bw_results.required_sclk_deep_sleep,
-+			context->bw_results.required_yclk,
-+			context->bw_results.required_blackout_duration_us);
-+		dal_logger_close(&log_entry);
-+	}
-+	return result;
-+}
-+
-+static void set_target_unchanged(
-+		struct validate_context *context,
-+		uint8_t target_idx)
-+{
-+	uint8_t i, j;
-+	struct core_target *target = context->targets[target_idx];
-+	context->target_flags[target_idx].unchanged = true;
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		struct core_stream *stream =
-+			DC_STREAM_TO_CORE(target->public.streams[i]);
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (context->res_ctx.pipe_ctx[j].stream == stream)
-+				context->res_ctx.pipe_ctx[j].flags.unchanged =
-+									true;
-+		}
-+	}
-+}
-+
-+static enum dc_status map_clock_resources(
-+		const struct dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j, k;
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (dc_is_dp_signal(pipe_ctx->signal)
-+					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
-+					pipe_ctx->clock_source = context->res_ctx.
-+							pool.clock_sources[DCE80_CLK_SRC_EXT];
-+				else
-+					pipe_ctx->clock_source =
-+						find_used_clk_src_for_sharing(
-+							&context->res_ctx, pipe_ctx);
-+				if (pipe_ctx->clock_source == NULL)
-+					pipe_ctx->clock_source =
-+							find_first_free_pll(&context->res_ctx);
-+
-+				if (pipe_ctx->clock_source == NULL)
-+					return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+				reference_clock_source(
-+						&context->res_ctx,
-+						pipe_ctx->clock_source);
-+
-+				/* only one cs per stream regardless of mpo */
-+				break;
-+			}
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce80_validate_with_context(
-+		const struct dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count,
-+		struct validate_context *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t i, j;
-+	struct dc_context *dc_ctx = dc->ctx;
-+
-+	for (i = 0; i < set_count; i++) {
-+		bool unchanged = false;
-+
-+		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		context->target_count++;
-+
-+		for (j = 0; j < dc->current_context.target_count; j++)
-+			if (dc->current_context.targets[j]
-+						== context->targets[i]) {
-+				unchanged = true;
-+				set_target_unchanged(context, i);
-+				context->target_status[i] =
-+					dc->current_context.target_status[j];
-+			}
-+		if (!unchanged)
-+			if (!attach_surfaces_to_context(
-+					(struct dc_surface **)set[i].surfaces,
-+					set[i].surface_count,
-+					&context->targets[i]->public,
-+					context)) {
-+				DC_ERROR("Failed to attach surface to target!\n");
-+				return DC_FAIL_ATTACH_SURFACES;
-+			}
-+	}
-+
-+	context->res_ctx.pool = dc->res_pool;
-+
-+	result = map_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = map_clock_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = validate_mapped_resource(dc, context);
-+
-+	if (result == DC_OK)
-+		build_scaling_params_for_context(dc, context);
-+
-+	if (result == DC_OK)
-+		result = dce80_validate_bandwidth(dc, context);
-+
-+	return result;
-+}
-+
-+static struct resource_funcs dce80_res_pool_funcs = {
-+	.destruct = dce80_destruct_resource_pool,
-+	.link_enc_create = dce80_link_encoder_create,
-+	.link_enc_destroy = dce110_link_encoder_destroy,
-+	.validate_with_context = dce80_validate_with_context,
-+	.validate_bandwidth = dce80_validate_bandwidth
-+};
-+
-+bool dce80_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct audio_init_data audio_init_data = { 0 };
-+	struct dc_context *ctx = dc->ctx;
-+	pool->adapter_srv = adapter_serv;
-+	pool->funcs = &dce80_res_pool_funcs;
-+
-+	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
-+
-+	pool->clock_sources[DCE80_CLK_SRC_PLL0] = dce80_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL0, &dce80_clk_src_reg_offsets[0]);
-+	pool->clock_sources[DCE80_CLK_SRC_PLL1] = dce80_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL1, &dce80_clk_src_reg_offsets[1]);
-+	pool->clock_sources[DCE80_CLK_SRC_PLL2] = dce80_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_PLL2, &dce80_clk_src_reg_offsets[2]);
-+	pool->clock_sources[DCE80_CLK_SRC_EXT] =  dce80_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_EXTERNAL, &dce80_clk_src_reg_offsets[0]);
-+	pool->clk_src_count = DCE80_CLK_SRC_TOTAL;
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->display_clock = dal_display_clock_dce80_create(ctx, adapter_serv);
-+	if (pool->display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->irqs = dal_irq_service_create(
-+				dal_adapter_service_get_dce_version(
-+					dc->res_pool.adapter_srv),
-+				&init_data);
-+		if (!pool->irqs)
-+			goto irqs_create_fail;
-+
-+	}
-+
-+	pool->pipe_count =
-+		dal_adapter_service_get_func_controllers_num(adapter_serv);
-+	pool->stream_enc_count =
-+					dal_adapter_service_get_stream_engines_num(adapter_serv);
-+	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+	if (pool->scaler_filter == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dm_error("DC: failed to create filter!\n");
-+		goto filter_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		pool->timing_generators[i] = dce80_timing_generator_create(
-+				adapter_serv, ctx, i, &dce80_tg_offsets[i]);
-+		if (pool->timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->mis[i] = dce80_mem_input_create(ctx, i,
-+				&dce80_mi_reg_offsets[i]);
-+		if (pool->mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->ipps[i] = dce80_ipp_create(ctx, i, &ipp_reg_offsets[i]);
-+		if (pool->ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->transforms[i] = dce80_transform_create(
-+						ctx, i, &dce80_xfm_offsets[i]);
-+		if (pool->transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create transform!\n");
-+			goto controller_create_fail;
-+		}
-+		pool->transforms[i]->funcs->transform_set_scaler_filter(
-+				pool->transforms[i],
-+				pool->scaler_filter);
-+
-+		pool->opps[i] = dce80_opp_create(ctx, i);
-+		if (pool->opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create output pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+	}
-+
-+	audio_init_data.as = adapter_serv;
-+	audio_init_data.ctx = ctx;
-+	pool->audio_count = 0;
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		struct graphics_object_id obj_id;
-+
-+		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		if (false == dal_graphics_object_id_is_valid(obj_id)) {
-+			/* no more valid audio objects */
-+			break;
-+		}
-+
-+		audio_init_data.audio_stream_id = obj_id;
-+		pool->audios[i] = dal_audio_create(&audio_init_data);
-+		if (pool->audios[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create DPPs!\n");
-+			goto audio_create_fail;
-+		}
-+		pool->audio_count++;
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_engines.u_all & 1 << i) {
-+			pool->stream_enc[i] = dce80_stream_encoder_create(
-+					i, dc->ctx,
-+					dal_adapter_service_get_bios_parser(
-+						adapter_serv),
-+					&stream_enc_regs[i]);
-+
-+			if (pool->stream_enc[i] == NULL) {
-+				BREAK_TO_DEBUGGER();
-+				dm_error("DC: failed to create stream_encoder!\n");
-+				goto stream_enc_create_fail;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < num_virtual_links; i++) {
-+		pool->stream_enc[pool->stream_enc_count] =
-+			virtual_stream_encoder_create(
-+				dc->ctx, dal_adapter_service_get_bios_parser(
-+								adapter_serv));
-+		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create stream_encoder!\n");
-+			goto stream_enc_create_fail;
-+		}
-+		pool->stream_enc_count++;
-+	}
-+
-+	return true;
-+
-+stream_enc_create_fail:
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dm_free(pool->stream_enc[i]->ctx,
-+				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+audio_create_fail:
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+
-+controller_create_fail:
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce80_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce80_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce80_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dm_free(pool->mis[i]->ctx,
-+					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+		if (pool->timing_generators[i] != NULL)	{
-+			dm_free(pool->timing_generators[i]->ctx,
-+				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+filter_create_fail:
-+	dal_irq_service_destroy(&pool->irqs);
-+
-+irqs_create_fail:
-+	dal_display_clock_destroy(&pool->display_clock);
-+
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dce80_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+
-+	return false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
-new file mode 100644
-index 0000000..3d0f8fe
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
-@@ -0,0 +1,42 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE80_H__
-+#define __DC_RESOURCE_DCE80_H__
-+
-+#include "core_types.h"
-+
-+struct adapter_service;
-+struct dc;
-+struct resource_pool;
-+
-+bool dce80_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct resource_pool *pool);
-+
-+#endif /* __DC_RESOURCE_DCE80_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-new file mode 100644
-index 0000000..d45a1e4
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-@@ -0,0 +1,1104 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "bios_parser_types.h"
-+#include "dc_bios_types.h"
-+#include "../dce110/dce110_stream_encoder.h"
-+#include "dce80_stream_encoder.h"
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#define LINK_REG(reg)\
-+	(enc110->regs->reg)
-+
-+#define VBI_LINE_0 0
-+#define DP_BLANK_MAX_RETRY 20
-+
-+enum dp_pixel_encoding {
-+	DP_PIXEL_ENCODING_RGB444 = 0,
-+	DP_PIXEL_ENCODING_YCBCR422,
-+	DP_PIXEL_ENCODING_YCBCR444,
-+	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT,
-+	DP_PIXEL_ENCODING_Y_ONLY
-+};
-+
-+enum dp_component_depth {
-+	DP_COMPONENT_DEPTH_6BPC = 0,
-+	DP_COMPONENT_DEPTH_8BPC,
-+	DP_COMPONENT_DEPTH_10BPC,
-+	DP_COMPONENT_DEPTH_12BPC
-+};
-+
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
-+static struct stream_encoder_funcs dce80_str_enc_funcs = {
-+	.dp_set_stream_attribute =
-+		dce80_stream_encoder_dp_set_stream_attribute,
-+	.hdmi_set_stream_attribute =
-+		dce80_stream_encoder_hdmi_set_stream_attribute,
-+	.dvi_set_stream_attribute =
-+		dce80_stream_encoder_dvi_set_stream_attribute,
-+	.set_mst_bandwidth =
-+		dce80_stream_encoder_set_mst_bandwidth,
-+	.update_hdmi_info_packets =
-+		dce80_stream_encoder_update_hdmi_info_packets,
-+	.stop_hdmi_info_packets =
-+		dce80_stream_encoder_stop_hdmi_info_packets,
-+	.update_dp_info_packets =
-+		dce80_stream_encoder_update_dp_info_packets,
-+	.stop_dp_info_packets =
-+		dce80_stream_encoder_stop_dp_info_packets,
-+	.dp_blank =
-+		dce80_stream_encoder_dp_blank,
-+	.dp_unblank =
-+		dce80_stream_encoder_dp_unblank,
-+};
-+
-+static void dce80_update_generic_info_packet(
-+	struct dce110_stream_encoder *enc110,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t regval;
-+	/* choose which generic packet to use */
-+	{
-+		addr = LINK_REG(AFMT_VBI_PACKET_CONTROL);
-+
-+		regval = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			packet_index,
-+			AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC_INDEX);
-+
-+		dm_write_reg(ctx, addr, regval);
-+	}
-+
-+	/* write generic packet header
-+	* (4th byte is for GENERIC0 only)
-+	*/
-+	{
-+		addr = LINK_REG(AFMT_GENERIC_HDR);
-+
-+		regval = 0;
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb0,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB0);
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb1,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB1);
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb2,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB2);
-+
-+		set_reg_field_value(
-+			regval,
-+			info_packet->hb3,
-+			AFMT_GENERIC_HDR,
-+			AFMT_GENERIC_HB3);
-+
-+		dm_write_reg(ctx, addr, regval);
-+	}
-+
-+	/* write generic packet contents
-+	* (we never use last 4 bytes)
-+	* there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
-+	*/
-+	{
-+		const uint32_t *content =
-+			(const uint32_t *) &info_packet->sb[0];
-+
-+		uint32_t counter = 0;
-+
-+		addr = LINK_REG(AFMT_GENERIC_0);
-+
-+		do {
-+			dm_write_reg(ctx, addr++, *content++);
-+
-+			++counter;
-+		} while (counter < 7);
-+	}
-+
-+	addr = LINK_REG(AFMT_GENERIC_7);
-+
-+	dm_write_reg(
-+		ctx,
-+		addr,
-+		0);
-+
-+	/* force double-buffered packet update */
-+	{
-+		addr = LINK_REG(AFMT_VBI_PACKET_CONTROL);
-+
-+		regval = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			(packet_index == 0),
-+			AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC0_UPDATE);
-+
-+		set_reg_field_value(
-+			regval,
-+			(packet_index == 2),
-+			AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC2_UPDATE);
-+
-+		dm_write_reg(ctx, addr, regval);
-+	}
-+}
-+
-+static void dce80_update_hdmi_info_packet(
-+	struct dce110_stream_encoder *enc110,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t cont, send, line;
-+	uint32_t addr = 0;
-+	uint32_t regval;
-+
-+	if (info_packet->valid) {
-+		dce80_update_generic_info_packet(
-+			enc110,
-+			packet_index,
-+			info_packet);
-+
-+		/* enable transmission of packet(s) -
-+		* packet transmission begins on the next frame
-+		*/
-+		cont = 1;
-+		/* send packet(s) every frame */
-+		send = 1;
-+		/* select line number to send packets on */
-+		line = 2;
-+	} else {
-+		cont = 0;
-+		send = 0;
-+		line = 0;
-+	}
-+
-+	/* choose which generic packet control to use */
-+
-+	switch (packet_index) {
-+	case 0:
-+	case 1:
-+		addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL0);
-+		break;
-+	case 2:
-+	case 3:
-+		addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL1);
-+		break;
-+	default:
-+		/* invalid HW packet index */
-+		dal_logger_write(
-+			ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"Invalid HW packet index: %s()\n",
-+			__func__);
-+		break;
-+	}
-+
-+	regval = dm_read_reg(ctx, addr);
-+
-+	switch (packet_index) {
-+	case 0:
-+	case 2:
-+		set_reg_field_value(
-+			regval,
-+			cont,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC0_CONT);
-+		set_reg_field_value(
-+			regval,
-+			send,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC0_SEND);
-+		set_reg_field_value(
-+			regval,
-+			line,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC0_LINE);
-+		break;
-+	case 1:
-+	case 3:
-+		set_reg_field_value(
-+			regval,
-+			cont,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC1_CONT);
-+		set_reg_field_value(
-+			regval,
-+			send,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC1_SEND);
-+		set_reg_field_value(
-+			regval,
-+			line,
-+			HDMI_GENERIC_PACKET_CONTROL0,
-+			HDMI_GENERIC1_LINE);
-+		break;
-+	default:
-+		/* invalid HW packet index */
-+		dal_logger_write(
-+			ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_ENCODER,
-+			"Invalid HW packet index: %s()\n",
-+			__func__);
-+		break;
-+	}
-+
-+	dm_write_reg(ctx, addr, regval);
-+}
-+
-+bool dce80_stream_encoder_construct(
-+	struct dce110_stream_encoder *enc110,
-+	struct dc_context *ctx,
-+	struct dc_bios *dcb,
-+	enum engine_id eng_id,
-+	const struct dce110_stream_enc_registers *regs)
-+{
-+	if (!enc110)
-+		return false;
-+	if (!dcb)
-+		return false;
-+
-+	enc110->base.funcs = &dce80_str_enc_funcs;
-+	enc110->base.ctx = ctx;
-+	enc110->base.id = eng_id;
-+	enc110->base.bp = dcb;
-+	enc110->regs = regs;
-+
-+	return true;
-+}
-+
-+/* setup stream encoder in dp mode */
-+void dce80_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = LINK_REG(DP_PIXEL_FORMAT);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	/* set pixel encoding */
-+	switch (crtc_timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(
-+			value,
-+			DP_PIXEL_ENCODING_YCBCR422,
-+			DP_PIXEL_FORMAT,
-+			DP_PIXEL_ENCODING);
-+		break;
-+	case PIXEL_ENCODING_YCBCR444:
-+		set_reg_field_value(
-+			value,
-+			DP_PIXEL_ENCODING_YCBCR444,
-+			DP_PIXEL_FORMAT,
-+			DP_PIXEL_ENCODING);
-+
-+		if (crtc_timing->flags.Y_ONLY)
-+			if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
-+				/* HW testing only, no use case yet.
-+				* Color depth of Y-only could be
-+				* 8, 10, 12, 16 bits
-+				*/
-+				set_reg_field_value(
-+					value,
-+					DP_PIXEL_ENCODING_Y_ONLY,
-+					DP_PIXEL_FORMAT,
-+					DP_PIXEL_ENCODING);
-+		/* Note: DP_MSA_MISC1 bit 7 is the indicator
-+		* of Y-only mode.
-+		* This bit is set in HW if register
-+		* DP_PIXEL_ENCODING is programmed to 0x4
-+		*/
-+		break;
-+	default:
-+		set_reg_field_value(
-+			value,
-+			DP_PIXEL_ENCODING_RGB444,
-+			DP_PIXEL_FORMAT,
-+			DP_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	/* set color depth */
-+
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_8BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_10BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_12BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	default:
-+		set_reg_field_value(
-+			value,
-+			DP_COMPONENT_DEPTH_6BPC,
-+			DP_PIXEL_FORMAT,
-+			DP_COMPONENT_DEPTH);
-+		break;
-+	}
-+
-+	/* set dynamic range and YCbCr range */
-+	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_DYN_RANGE);
-+	set_reg_field_value(value, 0, DP_PIXEL_FORMAT, DP_YCBCR_RANGE);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+}
-+
-+/* setup stream encoder in hdmi mode */
-+void dce80_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool enable_audio)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = LINK_REG(TMDS_CNTL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+	uint32_t output_pixel_clock = crtc_timing->pix_clk_khz;
-+	struct bp_encoder_control cntl = {0};
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc110->base.id;
-+	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+	cntl.enable_dp_audio = enable_audio;
-+	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.color_depth = crtc_timing->display_color_depth;
-+
-+	if (enc110->base.bp->funcs->encoder_control(
-+			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+		return;
-+
-+	switch (crtc_timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(value, 1, TMDS_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, TMDS_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	set_reg_field_value(value, 0, TMDS_CNTL, TMDS_COLOR_FORMAT);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* setup HDMI engine */
-+	addr = LINK_REG(HDMI_CONTROL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_PACKET_GEN_VERSION);
-+	set_reg_field_value(value, 1, HDMI_CONTROL, HDMI_KEEPOUT_MODE);
-+	set_reg_field_value(value, 0, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE);
-+
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			0,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_ENABLE);
-+		output_pixel_clock = (crtc_timing->pix_clk_khz * 30) / 24;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			2,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_ENABLE);
-+		output_pixel_clock = (crtc_timing->pix_clk_khz * 36) / 24;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		set_reg_field_value(
-+			value,
-+			3,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_DEPTH);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			HDMI_CONTROL,
-+			HDMI_DEEP_COLOR_ENABLE);
-+		output_pixel_clock = (crtc_timing->pix_clk_khz * 48) / 24;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = LINK_REG(HDMI_VBI_PACKET_CONTROL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT);
-+	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND);
-+	set_reg_field_value(value, 1, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* following belongs to audio */
-+	addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AUDIO_INFO_SEND);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = LINK_REG(AFMT_INFOFRAME_CONTROL0);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		AFMT_INFOFRAME_CONTROL0,
-+		AFMT_AUDIO_INFO_UPDATE);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = LINK_REG(HDMI_INFOFRAME_CONTROL1);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		VBI_LINE_0 + 2,
-+		HDMI_INFOFRAME_CONTROL1,
-+		HDMI_AUDIO_INFO_LINE);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = LINK_REG(HDMI_GC);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, 0, HDMI_GC, HDMI_GC_AVMUTE);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+/* setup stream encoder in dvi mode */
-+void dce80_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = LINK_REG(TMDS_CNTL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+	struct bp_encoder_control cntl = {0};
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc110->base.id;
-+	cntl.signal = is_dual_link ?
-+		SIGNAL_TYPE_DVI_DUAL_LINK :
-+		SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	cntl.enable_dp_audio = false;
-+	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+	cntl.lanes_number = (is_dual_link) ?
-+				LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+	cntl.color_depth = crtc_timing->display_color_depth;
-+
-+	if (enc110->base.bp->funcs->encoder_control(
-+			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+		return;
-+
-+	switch (crtc_timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		set_reg_field_value(value, 1, TMDS_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, TMDS_CNTL, TMDS_PIXEL_ENCODING);
-+		break;
-+	}
-+
-+	switch (crtc_timing->pixel_encoding) {
-+	case COLOR_DEPTH_101010:
-+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
-+			set_reg_field_value(
-+				value,
-+				2,
-+				TMDS_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				TMDS_CNTL,
-+				TMDS_COLOR_FORMAT);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0, TMDS_CNTL, TMDS_COLOR_FORMAT);
-+		break;
-+	}
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+void dce80_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	struct fixed31_32 avg_time_slots_per_mtp)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t field;
-+	uint32_t value;
-+	uint32_t retries = 0;
-+	uint32_t x = dal_fixed31_32_floor(
-+		avg_time_slots_per_mtp);
-+	uint32_t y = dal_fixed31_32_ceil(
-+		dal_fixed31_32_shl(
-+			dal_fixed31_32_sub_int(
-+				avg_time_slots_per_mtp,
-+				x),
-+			26));
-+
-+	{
-+		addr = LINK_REG(DP_MSE_RATE_CNTL);
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			x,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_X);
-+
-+		set_reg_field_value(
-+			value,
-+			y,
-+			DP_MSE_RATE_CNTL,
-+			DP_MSE_RATE_Y);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* wait for update to be completed on the link */
-+	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
-+	/* is reset to 0 (not pending) */
-+	{
-+		addr = LINK_REG(DP_MSE_RATE_UPDATE);
-+
-+		do {
-+			value = dm_read_reg(ctx, addr);
-+
-+			field = get_reg_field_value(
-+					value,
-+					DP_MSE_RATE_UPDATE,
-+					DP_MSE_RATE_UPDATE_PENDING);
-+
-+			if (!(field &
-+			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
-+				break;
-+
-+			dm_delay_in_microseconds(ctx, 10);
-+
-+			++retries;
-+		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+	}
-+}
-+
-+void dce80_stream_encoder_update_hdmi_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t regval;
-+	uint32_t control0val;
-+	uint32_t control1val;
-+
-+	if (info_frame->avi.valid) {
-+		const uint32_t *content =
-+			(const uint32_t *) &info_frame->avi.sb[0];
-+
-+		addr = LINK_REG(AFMT_AVI_INFO0);
-+		regval = content[0];
-+
-+		dm_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+
-+		addr = LINK_REG(AFMT_AVI_INFO1);
-+		regval = content[1];
-+
-+		dm_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+
-+		addr = LINK_REG(AFMT_AVI_INFO2);
-+		regval = content[2];
-+
-+		dm_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+
-+		addr = LINK_REG(AFMT_AVI_INFO3);
-+		regval = content[3];
-+
-+		/* move version to AVI_INFO3 */
-+		set_reg_field_value(
-+			regval,
-+			info_frame->avi.hb1,
-+			AFMT_AVI_INFO3,
-+			AFMT_AVI_INFO_VERSION);
-+
-+		dm_write_reg(
-+			ctx,
-+			addr,
-+			regval);
-+
-+			addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
-+			control0val = dm_read_reg(ctx, addr);
-+			set_reg_field_value(
-+				control0val,
-+				1,
-+				HDMI_INFOFRAME_CONTROL0,
-+				HDMI_AVI_INFO_SEND);
-+
-+			set_reg_field_value(
-+				control0val,
-+				1,
-+				HDMI_INFOFRAME_CONTROL0,
-+				HDMI_AVI_INFO_CONT);
-+
-+			dm_write_reg(ctx, addr, control0val);
-+
-+			addr = LINK_REG(HDMI_INFOFRAME_CONTROL1);
-+
-+			control1val = dm_read_reg(ctx, addr);
-+
-+			set_reg_field_value(
-+				control1val,
-+				VBI_LINE_0 + 2,
-+				HDMI_INFOFRAME_CONTROL1,
-+				HDMI_AVI_INFO_LINE);
-+
-+			dm_write_reg(ctx, addr, control1val);
-+	} else {
-+		addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
-+
-+		regval = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			regval,
-+			0,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_SEND);
-+
-+		set_reg_field_value(
-+			regval,
-+			0,
-+			HDMI_INFOFRAME_CONTROL0,
-+			HDMI_AVI_INFO_CONT);
-+
-+		dm_write_reg(ctx, addr, regval);
-+	}
-+
-+	dce80_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
-+	dce80_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
-+	dce80_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
-+}
-+
-+void dce80_stream_encoder_stop_hdmi_info_packets(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* stop generic packets 0 & 1 on HDMI */
-+	addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL0);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC1_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL0,
-+		HDMI_GENERIC0_SEND);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* stop generic packets 2 & 3 on HDMI */
-+	addr = LINK_REG(HDMI_GENERIC_PACKET_CONTROL1);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC2_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_CONT);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_LINE);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_GENERIC_PACKET_CONTROL1,
-+		HDMI_GENERIC3_SEND);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* stop AVI packet on HDMI */
-+	addr = LINK_REG(HDMI_INFOFRAME_CONTROL0);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AVI_INFO_SEND);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		HDMI_INFOFRAME_CONTROL0,
-+		HDMI_AVI_INFO_CONT);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+void dce80_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = LINK_REG(DP_SEC_CNTL);
-+	uint32_t value;
-+
-+	if (info_frame->vsc.valid)
-+		dce80_update_generic_info_packet(
-+			enc110,
-+			0,
-+			&info_frame->vsc);
-+
-+	/* enable/disable transmission of packet(s).
-+	* If enabled, packet transmission begins on the next frame
-+	*/
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		info_frame->vsc.valid,
-+		DP_SEC_CNTL,
-+		DP_SEC_GSP0_ENABLE);
-+
-+	/* This bit is the master enable bit.
-+	* When enabling secondary stream engine,
-+	* this master bit must also be set.
-+	* This register shared with audio info frame.
-+	* Therefore we need to enable master bit
-+	* if at least on of the fields is not 0
-+	*/
-+	if (value)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+void dce80_stream_encoder_stop_dp_info_packets(
-+	struct stream_encoder *enc)
-+{
-+	/* stop generic packets on DP */
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = LINK_REG(DP_SEC_CNTL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP0_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP1_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP2_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_GSP3_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_AVI_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_MPG_ENABLE);
-+	set_reg_field_value(value, 0, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE);
-+
-+	/* this register shared with audio info frame.
-+	* therefore we need to keep master enabled
-+	* if at least one of the fields is not 0
-+	*/
-+
-+	if (value)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+void dce80_stream_encoder_dp_blank(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = LINK_REG(DP_VID_STREAM_CNTL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+	uint32_t retries = 0;
-+	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
-+
-+	/* Note: For CZ, we are changing driver default to disable
-+	* stream deferred to next VBLANK. If results are positive, we
-+	* will make the same change to all DCE versions. There are a
-+	* handful of panels that cannot handle disable stream at
-+	* HBLANK and will result in a white line flash across the
-+	* screen on stream disable.
-+	*/
-+
-+	/* Specify the video stream disable point
-+	* (2 = start of the next vertical blank)
-+	*/
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DP_VID_STREAM_CNTL,
-+		DP_VID_STREAM_DIS_DEFER);
-+	/* Larger delay to wait until VBLANK - use max retry of
-+	* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
-+	* a little more because we may not trust delay accuracy.
-+	*/
-+	max_retries = DP_BLANK_MAX_RETRY * 150;
-+
-+	/* disable DP stream */
-+	set_reg_field_value(value, 0, DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* the encoder stops sending the video stream
-+	* at the start of the vertical blanking.
-+	* Poll for DP_VID_STREAM_STATUS == 0
-+	*/
-+
-+	do {
-+		value = dm_read_reg(ctx, addr);
-+
-+		if (!get_reg_field_value(
-+			value,
-+			DP_VID_STREAM_CNTL,
-+			DP_VID_STREAM_STATUS))
-+			break;
-+
-+		dm_delay_in_microseconds(ctx, 10);
-+
-+		++retries;
-+	} while (retries < max_retries);
-+
-+	ASSERT(retries <= max_retries);
-+
-+	/* Tell the DP encoder to ignore timing from CRTC, must be done after
-+	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
-+	* complete, stream status will be stuck in video stream enabled state,
-+	* i.e. DP_VID_STREAM_STATUS stuck at 1.
-+	*/
-+	addr = LINK_REG(DP_STEER_FIFO);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, true, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+/* output video stream to link encoder */
-+void dce80_stream_encoder_dp_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
-+		uint32_t n_vid = 0x8000;
-+		uint32_t m_vid;
-+
-+		/* M / N = Fstream / Flink
-+		* m_vid / n_vid = pixel rate / link rate
-+		*/
-+
-+		uint64_t m_vid_l = n_vid;
-+
-+		m_vid_l *= param->crtc_timing.pixel_clock;
-+		m_vid_l = div_u64(m_vid_l,
-+			param->link_settings.link_rate
-+				* LINK_RATE_REF_FREQ_IN_KHZ);
-+
-+		m_vid = (uint32_t) m_vid_l;
-+
-+		/* enable auto measurement */
-+		addr = LINK_REG(DP_VID_TIMING);
-+		value = dm_read_reg(ctx, addr);
-+		set_reg_field_value(value, 0, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
-+		dm_write_reg(ctx, addr, value);
-+
-+		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
-+		* therefore program initial value for Mvid and Nvid
-+		*/
-+		addr = LINK_REG(DP_VID_N);
-+		value = dm_read_reg(ctx, addr);
-+		set_reg_field_value(value, n_vid, DP_VID_N, DP_VID_N);
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = LINK_REG(DP_VID_M);
-+		value = dm_read_reg(ctx, addr);
-+		set_reg_field_value(value, m_vid, DP_VID_M, DP_VID_M);
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = LINK_REG(DP_VID_TIMING);
-+		value = dm_read_reg(ctx, addr);
-+		set_reg_field_value(value, 1, DP_VID_TIMING, DP_VID_M_N_GEN_EN);
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* set DIG_START to 0x1 to resync FIFO */
-+	addr = LINK_REG(DIG_FE_CNTL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, 1, DIG_FE_CNTL, DIG_START);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* switch DP encoder to CRTC data */
-+	addr = LINK_REG(DP_STEER_FIFO);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, false, DP_STEER_FIFO, DP_STEER_FIFO_RESET);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* wait 100us for DIG/DP logic to prime
-+	* (i.e. a few video lines)
-+	*/
-+	dm_delay_in_microseconds(ctx, 100);
-+
-+	/* the hardware would start sending video at the start of the next DP
-+	* frame (i.e. rising edge of the vblank).
-+	* NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
-+	* register has no effect on enable transition! HW always guarantees
-+	* VID_STREAM enable at start of next frame, and this is not
-+	* programmable
-+	*/
-+	addr = LINK_REG(DP_VID_STREAM_CNTL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		true,
-+		DP_VID_STREAM_CNTL,
-+		DP_VID_STREAM_ENABLE);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-new file mode 100644
-index 0000000..f4645a8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "inc/stream_encoder.h"
-+
-+#ifndef __DC_STREAM_ENCODER_DCE80_H__
-+#define __DC_STREAM_ENCODER_DCE80_H__
-+
-+bool dce80_stream_encoder_construct(
-+	struct dce110_stream_encoder *enc110,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp,
-+	enum engine_id eng_id,
-+	const struct dce110_stream_enc_registers *regs);
-+
-+/***** HW programming ***********/
-+/* setup stream encoder in dp mode */
-+void dce80_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing);
-+
-+/* setup stream encoder in hdmi mode */
-+void dce80_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool enable_audio);
-+
-+/* setup stream encoder in dvi mode */
-+void dce80_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link);
-+
-+/* set throttling for DP MST */
-+void dce80_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	struct fixed31_32 avg_time_slots_per_mtp);
-+
-+void dce80_stream_encoder_update_hdmi_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame);
-+
-+void dce80_stream_encoder_stop_hdmi_info_packets(
-+	struct stream_encoder *enc);
-+
-+void dce80_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame);
-+
-+void dce80_stream_encoder_stop_dp_info_packets(
-+	struct stream_encoder *enc);
-+
-+/* output blank/idle stream to link encoder */
-+void dce80_stream_encoder_dp_blank(
-+	struct stream_encoder *enc);
-+
-+/* output video stream to link encoder */
-+void dce80_stream_encoder_dp_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param);
-+
-+
-+#endif /* __DC_STREAM_ENCODER_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-new file mode 100644
-index 0000000..80391c2
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-@@ -0,0 +1,241 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/adapter_service_interface.h"
-+#include "include/logger_interface.h"
-+#include "../dce110/dce110_timing_generator.h"
-+#include "dce80_timing_generator.h"
-+
-+#include "../inc/timing_generator.h"
-+
-+enum black_color_format {
-+	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
-+	BLACK_COLOR_FORMAT_RGB_LIMITED,
-+	BLACK_COLOR_FORMAT_YUV_TV,
-+	BLACK_COLOR_FORMAT_YUV_CV,
-+	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
-+
-+	BLACK_COLOR_FORMAT_COUNT
-+};
-+
-+static const struct dce110_timing_generator_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
-+
-+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
-+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
-+
-+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
-+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
-+#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
-+
-+void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
-+{
-+	uint64_t pix_dur;
-+	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
-+					+ DCE110TG_FROM_TG(tg)->offsets.dmif;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (pix_clk_khz == 0)
-+		return;
-+
-+	pix_dur = 1000000000 / pix_clk_khz;
-+
-+	set_reg_field_value(
-+		value,
-+		pix_dur,
-+		DPG_PIPE_ARBITRATION_CONTROL1,
-+		PIXEL_DURATION);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (!use_vbios)
-+		program_pix_dur(tg, timing->pix_clk_khz);
-+
-+	dce110_tg_program_timing(tg, timing, use_vbios);
-+}
-+
-+static struct timing_generator_funcs dce80_tg_funcs = {
-+		.validate_timing = dce110_tg_validate_timing,
-+		.program_timing = program_timing,
-+		.enable_crtc = dce110_timing_generator_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_disable_crtc,
-+		.is_counter_moving = dce110_timing_generator_is_counter_moving,
-+		.get_position = dce110_timing_generator_get_crtc_positions,
-+		.get_frame_count = dce110_timing_generator_get_vblank_counter,
-+		.set_early_control = dce110_timing_generator_set_early_control,
-+		.wait_for_state = dce110_tg_wait_for_state,
-+		.set_blank = dce110_tg_set_blank,
-+		.set_colors = dce110_tg_set_colors,
-+		.set_overscan_blank_color =
-+				dce110_timing_generator_set_overscan_color_black,
-+		.set_blank_color = dce110_timing_generator_program_blank_color,
-+		.disable_vga = dce110_timing_generator_disable_vga,
-+		.did_triggered_reset_occur =
-+				dce110_timing_generator_did_triggered_reset_occur,
-+		.setup_global_swap_lock =
-+				dce110_timing_generator_setup_global_swap_lock,
-+		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
-+		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
-+		.tear_down_global_swap_lock =
-+				dce110_timing_generator_tear_down_global_swap_lock,
-+
-+		/* DCE8.0 overrides */
-+		.enable_advanced_request =
-+				dce80_timing_generator_enable_advanced_request
-+};
-+
-+bool dce80_timing_generator_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct adapter_service *as,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets)
-+{
-+	if (!tg110)
-+		return false;
-+
-+	if (!as)
-+		return false;
-+
-+	tg110->controller_id = CONTROLLER_ID_D0 + instance;
-+	tg110->offsets = *offsets;
-+	tg110->derived_offsets = reg_offsets[instance];
-+
-+	tg110->base.funcs = &dce80_tg_funcs;
-+
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = dal_adapter_service_get_bios_parser(as);
-+
-+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	tg110->min_h_blank = 56;
-+	tg110->min_h_front_porch = 4;
-+	tg110->min_h_back_porch = 4;
-+
-+	return true;
-+}
-+
-+void dce80_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (enable && !DCE110TG_FROM_TG(tg)->disable_advanced_request) {
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	}
-+
-+	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
-+		set_reg_field_value(
-+			value,
-+			3,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			4,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_PROGRESSIVE_START_LINE_EARLY);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_INTERLACE_START_LINE_EARLY);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-new file mode 100644
-index 0000000..0b88686
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_DCE80_H__
-+#define __DC_TIMING_GENERATOR_DCE80_H__
-+
-+
-+#include "../inc/timing_generator.h"
-+#include "../include/grph_object_id.h"
-+
-+/* DCE8.0 implementation inherits from DCE11.0 */
-+bool dce80_timing_generator_construct(
-+	struct dce110_timing_generator *tg,
-+	struct adapter_service *as,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets);
-+
-+/******** HW programming ************/
-+void dce80_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing);
-+
-+
-+
-+#endif /* __DC_TIMING_GENERATOR_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
-new file mode 100644
-index 0000000..5654738
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
-@@ -0,0 +1,91 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "core_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/fixed31_32.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce80_transform.h"
-+
-+#include "dce80_transform_bit_depth.h"
-+
-+static struct transform_funcs dce80_transform_funcs = {
-+	.transform_power_up =
-+		dce80_transform_power_up,
-+	.transform_set_scaler =
-+		dce80_transform_set_scaler,
-+	.transform_set_scaler_bypass =
-+		dce80_transform_set_scaler_bypass,
-+	.transform_update_viewport =
-+		dce80_transform_update_viewport,
-+	.transform_set_scaler_filter =
-+		dce80_transform_set_scaler_filter,
-+	.transform_set_gamut_remap =
-+		dce80_transform_set_gamut_remap,
-+	.transform_set_pixel_storage_depth =
-+		dce80_transform_set_pixel_storage_depth,
-+	.transform_get_current_pixel_storage_depth =
-+		dce80_transform_get_current_pixel_storage_depth
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce80_transform_construct(
-+	struct dce80_transform *xfm80,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce80_transform_reg_offsets *reg_offsets)
-+{
-+	xfm80->base.ctx = ctx;
-+
-+	xfm80->base.inst = inst;
-+	xfm80->base.funcs = &dce80_transform_funcs;
-+
-+	xfm80->offsets = *reg_offsets;
-+
-+	xfm80->lb_pixel_depth_supported =
-+			LB_PIXEL_DEPTH_18BPP |
-+			LB_PIXEL_DEPTH_24BPP |
-+			LB_PIXEL_DEPTH_30BPP;
-+
-+	return true;
-+}
-+
-+bool dce80_transform_power_up(struct transform *xfm)
-+{
-+	return dce80_transform_power_up_line_buffer(xfm);
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-new file mode 100644
-index 0000000..adcc54b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -0,0 +1,87 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_DCE80_H__
-+#define __DAL_TRANSFORM_DCE80_H__
-+
-+#include "inc/transform.h"
-+#include "include/grph_csc_types.h"
-+
-+#define TO_DCE80_TRANSFORM(transform)\
-+	container_of(transform, struct dce80_transform, base)
-+
-+struct dce80_transform_reg_offsets {
-+	uint32_t scl_offset;
-+	uint32_t crtc_offset;
-+	uint32_t dcp_offset;
-+	uint32_t lb_offset;
-+};
-+
-+struct dce80_transform {
-+	struct transform base;
-+	struct dce80_transform_reg_offsets offsets;
-+
-+	uint32_t lb_pixel_depth_supported;
-+};
-+
-+bool dce80_transform_construct(struct dce80_transform *xfm80,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce80_transform_reg_offsets *offsets);
-+
-+bool dce80_transform_power_up(struct transform *xfm);
-+
-+/* SCALER RELATED */
-+bool dce80_transform_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data);
-+
-+void dce80_transform_set_scaler_bypass(struct transform *xfm);
-+
-+bool dce80_transform_update_viewport(
-+	struct transform *xfm,
-+	const struct rect *view_port,
-+	bool is_fbc_attached);
-+
-+void dce80_transform_set_scaler_filter(
-+	struct transform *xfm,
-+	struct scaler_filter *filter);
-+
-+/* GAMUT RELATED */
-+void dce80_transform_set_gamut_remap(
-+	struct transform *xfm,
-+	const struct grph_csc_adjustment *adjust);
-+
-+/* BIT DEPTH RELATED */
-+bool dce80_transform_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params);
-+
-+bool dce80_transform_get_current_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth *depth);
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
-new file mode 100644
-index 0000000..1dc0dbc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
-@@ -0,0 +1,841 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_transform.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/fixed32_32.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + xfm80->offsets.dcp_offset)
-+
-+#define LB_REG(reg)\
-+	(reg + xfm80->offsets.lb_offset)
-+
-+#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-+#define LB_BITS_PER_ENTRY 144
-+
-+enum dcp_out_trunc_round_mode {
-+	DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+	DCP_OUT_TRUNC_ROUND_MODE_ROUND
-+};
-+
-+enum dcp_out_trunc_round_depth {
-+	DCP_OUT_TRUNC_ROUND_DEPTH_14BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_13BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_12BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_11BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_10BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_9BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_8BIT
-+};
-+
-+/*  defines the various methods of bit reduction available for use */
-+enum dcp_bit_depth_reduction_mode {
-+	DCP_BIT_DEPTH_REDUCTION_MODE_DITHER,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_ROUND,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_INVALID
-+};
-+
-+enum dcp_spatial_dither_mode {
-+	DCP_SPATIAL_DITHER_MODE_AAAA,
-+	DCP_SPATIAL_DITHER_MODE_A_AA_A,
-+	DCP_SPATIAL_DITHER_MODE_AABBAABB,
-+	DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC,
-+	DCP_SPATIAL_DITHER_MODE_INVALID
-+};
-+
-+enum dcp_spatial_dither_depth {
-+	DCP_SPATIAL_DITHER_DEPTH_30BPP,
-+	DCP_SPATIAL_DITHER_DEPTH_24BPP
-+};
-+
-+static bool set_clamp(
-+	struct dce80_transform *xfm80,
-+	enum dc_color_depth depth);
-+
-+static bool set_round(
-+	struct dce80_transform *xfm80,
-+	enum dcp_out_trunc_round_mode mode,
-+	enum dcp_out_trunc_round_depth depth);
-+
-+static bool set_dither(
-+	struct dce80_transform *xfm80,
-+	bool dither_enable,
-+	enum dcp_spatial_dither_mode dither_mode,
-+	enum dcp_spatial_dither_depth dither_depth,
-+	bool frame_random_enable,
-+	bool rgb_random_enable,
-+	bool highpass_random_enable);
-+
-+/**
-+ *******************************************************************************
-+ * dce80_transform_bit_depth_reduction_program
-+ *
-+ * @brief
-+ *     Programs the DCP bit depth reduction registers (Clamp, Round/Truncate,
-+ *      Dither) for dce80
-+ *
-+ * @param depth : bit depth to set the clamp to (should match denorm)
-+ *
-+ * @return
-+ *     true if succeeds.
-+ *******************************************************************************
-+ */
-+static bool program_bit_depth_reduction(
-+	struct dce80_transform *xfm80,
-+	enum dc_color_depth depth)
-+{
-+	enum dcp_bit_depth_reduction_mode depth_reduction_mode;
-+	enum dcp_spatial_dither_mode spatial_dither_mode;
-+	bool frame_random_enable;
-+	bool rgb_random_enable;
-+	bool highpass_random_enable;
-+
-+	if (depth > COLOR_DEPTH_121212) {
-+		ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
-+		return false;
-+	}
-+
-+	depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
-+
-+	spatial_dither_mode = DCP_SPATIAL_DITHER_MODE_A_AA_A;
-+
-+	frame_random_enable = true;
-+	rgb_random_enable = true;
-+	highpass_random_enable = true;
-+
-+	if (!set_clamp(xfm80, depth)) {
-+		/* Failure in set_clamp() */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+	switch (depth_reduction_mode) {
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_DITHER:
-+		/*  Spatial Dither: Set round/truncate to bypass (12bit),
-+		 *  enable Dither (30bpp) */
-+		set_round(xfm80,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-+
-+		set_dither(xfm80, true, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_ROUND:
-+		/*  Round: Enable round (10bit), disable Dither */
-+		set_round(xfm80,
-+			DCP_OUT_TRUNC_ROUND_MODE_ROUND,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-+
-+		set_dither(xfm80, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE: /*  Truncate */
-+		/*  Truncate: Enable truncate (10bit), disable Dither */
-+		set_round(xfm80,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-+
-+		set_dither(xfm80, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED: /*  Disabled */
-+		/*  Truncate: Set round/truncate to bypass (12bit),
-+		 * disable Dither */
-+		set_round(xfm80,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-+
-+		set_dither(xfm80, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	default:
-+		/* Invalid DCP Depth reduction mode */
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ *******************************************************************************
-+ * set_clamp
-+ *
-+ * @param depth : bit depth to set the clamp to (should match denorm)
-+ *
-+ * @brief
-+ *     Programs clamp according to panel bit depth.
-+ *
-+ * @return
-+ *     true if succeeds
-+ *
-+ *******************************************************************************
-+ */
-+static bool set_clamp(
-+	struct dce80_transform *xfm80,
-+	enum dc_color_depth depth)
-+{
-+	uint32_t clamp_max = 0;
-+
-+	/* At the clamp block the data will be MSB aligned, so we set the max
-+	 * clamp accordingly.
-+	 * For example, the max value for 6 bits MSB aligned (14 bit bus) would
-+	 * be "11 1111 0000 0000" in binary, so 0x3F00.
-+	 */
-+	switch (depth) {
-+	case COLOR_DEPTH_666:
-+		/* 6bit MSB aligned on 14 bit bus '11 1111 0000 0000' */
-+		clamp_max = 0x3F00;
-+		break;
-+	case COLOR_DEPTH_888:
-+		/* 8bit MSB aligned on 14 bit bus '11 1111 800 0000' */
-+		clamp_max = 0x3FC0;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 10bit MSB aligned on 14 bit bus '11 1111 1111 800' */
-+		clamp_max = 0x3FFC;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 12bit MSB aligned on 14 bit bus '11 1111 1111 1111' */
-+		clamp_max = 0x3FFF;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Invalid clamp bit depth */
-+		return false;
-+	}
-+
-+	{
-+		uint32_t value = 0;
-+		/*  always set min to 0 */
-+			set_reg_field_value(
-+			value,
-+			0,
-+			OUT_CLAMP_CONTROL_B_CB,
-+			OUT_CLAMP_MIN_B_CB);
-+
-+		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_B_CB,
-+			OUT_CLAMP_MAX_B_CB);
-+
-+		dm_write_reg(xfm80->base.ctx,
-+			DCP_REG(mmOUT_CLAMP_CONTROL_B_CB),
-+			value);
-+	}
-+
-+	{
-+		uint32_t value = 0;
-+		/*  always set min to 0 */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			OUT_CLAMP_CONTROL_G_Y,
-+			OUT_CLAMP_MIN_G_Y);
-+
-+		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_G_Y,
-+			OUT_CLAMP_MAX_G_Y);
-+
-+		dm_write_reg(xfm80->base.ctx,
-+			DCP_REG(mmOUT_CLAMP_CONTROL_G_Y),
-+			value);
-+	}
-+
-+	{
-+		uint32_t value = 0;
-+		/*  always set min to 0 */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MIN_R_CR);
-+
-+		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MAX_R_CR);
-+
-+		dm_write_reg(xfm80->base.ctx,
-+			DCP_REG(mmOUT_CLAMP_CONTROL_R_CR),
-+			value);
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+ *******************************************************************************
-+ * set_round
-+ *
-+ * @brief
-+ *     Programs Round/Truncate
-+ *
-+ * @param [in] mode  :round or truncate
-+ * @param [in] depth :bit depth to round/truncate to
-+ OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode
-+ POSSIBLE VALUES:
-+      00 - truncate to u0.12
-+      01 - truncate to u0.11
-+      02 - truncate to u0.10
-+      03 - truncate to u0.9
-+      04 - truncate to u0.8
-+      05 - reserved
-+      06 - truncate to u0.14
-+      07 - truncate to u0.13		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MAX_R_CR);
-+      08 - round to u0.12
-+      09 - round to u0.11
-+      10 - round to u0.10
-+      11 - round to u0.9
-+      12 - round to u0.8
-+      13 - reserved
-+      14 - round to u0.14
-+      15 - round to u0.13
-+
-+ * @return
-+ *     true if succeeds.
-+ *******************************************************************************
-+ */
-+static bool set_round(
-+	struct dce80_transform *xfm80,
-+	enum dcp_out_trunc_round_mode mode,
-+	enum dcp_out_trunc_round_depth depth)
-+{
-+	uint32_t depth_bits = 0;
-+	uint32_t mode_bit = 0;
-+	/*  zero out all bits */
-+	uint32_t value = 0;
-+
-+	/*  set up bit depth */
-+	switch (depth) {
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT:
-+		depth_bits = 6;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT:
-+		depth_bits = 7;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT:
-+		depth_bits = 0;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT:
-+		depth_bits = 1;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT:
-+		depth_bits = 2;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT:
-+		depth_bits = 3;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT:
-+		depth_bits = 4;
-+		break;
-+	default:
-+		/* Invalid dcp_out_trunc_round_depth */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		depth_bits,
-+		OUT_ROUND_CONTROL,
-+		OUT_ROUND_TRUNC_MODE);
-+
-+	/*  set up round or truncate */
-+	switch (mode) {
-+	case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
-+		mode_bit = 0;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_MODE_ROUND:
-+		mode_bit = 1;
-+		break;
-+	default:
-+		/* Invalid dcp_out_trunc_round_mode */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	depth_bits |= mode_bit << 3;
-+
-+	set_reg_field_value(
-+		value,
-+		depth_bits,
-+		OUT_ROUND_CONTROL,
-+		OUT_ROUND_TRUNC_MODE);
-+
-+	/*  write the register */
-+	dm_write_reg(xfm80->base.ctx,
-+				DCP_REG(mmOUT_ROUND_CONTROL),
-+				value);
-+
-+	return true;
-+}
-+
-+/**
-+ *******************************************************************************
-+ * set_dither
-+ *
-+ * @brief
-+ *     Programs Dither
-+ *
-+ * @param [in] dither_enable        : enable dither
-+ * @param [in] dither_mode           : dither mode to set
-+ * @param [in] dither_depth          : bit depth to dither to
-+ * @param [in] frame_random_enable    : enable frame random
-+ * @param [in] rgb_random_enable      : enable rgb random
-+ * @param [in] highpass_random_enable : enable highpass random
-+ *
-+ * @return
-+ *     true if succeeds.
-+ *******************************************************************************
-+ */
-+
-+static bool set_dither(
-+	struct dce80_transform *xfm80,
-+	bool dither_enable,
-+	enum dcp_spatial_dither_mode dither_mode,
-+	enum dcp_spatial_dither_depth dither_depth,
-+	bool frame_random_enable,
-+	bool rgb_random_enable,
-+	bool highpass_random_enable)
-+{
-+	uint32_t dither_depth_bits = 0;
-+	uint32_t dither_mode_bits = 0;
-+	/*  zero out all bits */
-+	uint32_t value = 0;
-+
-+	/* set up the fields */
-+	if (dither_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_SPATIAL_DITHER_EN);
-+
-+	switch (dither_mode) {
-+	case DCP_SPATIAL_DITHER_MODE_AAAA:
-+		dither_mode_bits = 0;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_A_AA_A:
-+		dither_mode_bits = 1;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_AABBAABB:
-+		dither_mode_bits = 2;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC:
-+		dither_mode_bits = 3;
-+		break;
-+	default:
-+		/* Invalid dcp_spatial_dither_mode */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+
-+	}
-+	set_reg_field_value(
-+		value,
-+		dither_mode_bits,
-+		DCP_SPATIAL_DITHER_CNTL,
-+		DCP_SPATIAL_DITHER_MODE);
-+
-+	switch (dither_depth) {
-+	case DCP_SPATIAL_DITHER_DEPTH_30BPP:
-+		dither_depth_bits = 0;
-+		break;
-+	case DCP_SPATIAL_DITHER_DEPTH_24BPP:
-+		dither_depth_bits = 1;
-+		break;
-+	default:
-+		/* Invalid dcp_spatial_dither_depth */
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		dither_depth_bits,
-+		DCP_SPATIAL_DITHER_CNTL,
-+		DCP_SPATIAL_DITHER_DEPTH);
-+
-+	if (frame_random_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_FRAME_RANDOM_ENABLE);
-+
-+	if (rgb_random_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_RGB_RANDOM_ENABLE);
-+
-+	if (highpass_random_enable)
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DCP_SPATIAL_DITHER_CNTL,
-+			DCP_HIGHPASS_RANDOM_ENABLE);
-+
-+	/*  write the register */
-+	dm_write_reg(xfm80->base.ctx,
-+				DCP_REG(mmDCP_SPATIAL_DITHER_CNTL),
-+				value);
-+
-+	return true;
-+}
-+
-+bool dce80_transform_get_max_num_of_supported_lines(
-+	struct dce80_transform *xfm80,
-+	enum lb_pixel_depth depth,
-+	uint32_t pixel_width,
-+	uint32_t *lines)
-+{
-+	uint32_t pixels_per_entries = 0;
-+	uint32_t max_pixels_supports = 0;
-+
-+	if (pixel_width == 0)
-+		return false;
-+
-+	/* Find number of pixels that can fit into a single LB entry and
-+	 * take floor of the value since we cannot store a single pixel
-+	 * across multiple entries. */
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 18;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_24BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 24;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_30BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 30;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_36BPP:
-+		pixels_per_entries = LB_BITS_PER_ENTRY / 36;
-+		break;
-+
-+	default:
-+		dal_logger_write(xfm80->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid LB pixel depth",
-+			__func__);
-+		break;
-+	}
-+
-+	if (pixels_per_entries == 0)
-+		return false;
-+
-+	max_pixels_supports = pixels_per_entries * LB_TOTAL_NUMBER_OF_ENTRIES;
-+
-+	*lines = max_pixels_supports / pixel_width;
-+	return true;
-+}
-+
-+void dce80_transform_enable_alpha(
-+	struct dce80_transform *xfm80,
-+	bool enable)
-+{
-+	struct dc_context *ctx = xfm80->base.ctx;
-+	uint32_t value;
-+	uint32_t addr = LB_REG(mmLB_DATA_FORMAT);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	if (enable == 1)
-+		set_reg_field_value(
-+				value,
-+				1,
-+				LB_DATA_FORMAT,
-+				ALPHA_EN);
-+	else
-+		set_reg_field_value(
-+				value,
-+				0,
-+				LB_DATA_FORMAT,
-+				ALPHA_EN);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static enum lb_pixel_depth translate_display_bpp_to_lb_depth(
-+	uint32_t display_bpp)
-+{
-+	switch (display_bpp) {
-+	case 18:
-+		return LB_PIXEL_DEPTH_18BPP;
-+	case 24:
-+		return LB_PIXEL_DEPTH_24BPP;
-+	case 36:
-+	case 42:
-+	case 48:
-+		return LB_PIXEL_DEPTH_36BPP;
-+	case 30:
-+	default:
-+		return LB_PIXEL_DEPTH_30BPP;
-+	}
-+}
-+
-+bool dce80_transform_get_next_lower_pixel_storage_depth(
-+	struct dce80_transform *xfm80,
-+	uint32_t display_bpp,
-+	enum lb_pixel_depth depth,
-+	enum lb_pixel_depth *lower_depth)
-+{
-+	enum lb_pixel_depth depth_req_by_display =
-+		translate_display_bpp_to_lb_depth(display_bpp);
-+	uint32_t current_required_depth = depth_req_by_display;
-+	uint32_t current_depth = depth;
-+
-+	/* if required display depth < current we could go down, for example
-+	 * from LB_PIXEL_DEPTH_30BPP to LB_PIXEL_DEPTH_24BPP
-+	 */
-+	if (current_required_depth < current_depth) {
-+		current_depth = current_depth >> 1;
-+		if (xfm80->lb_pixel_depth_supported & current_depth) {
-+			*lower_depth = current_depth;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+bool dce80_transform_is_prefetch_enabled(
-+	struct dce80_transform *xfm80)
-+{
-+	uint32_t value = dm_read_reg(
-+			xfm80->base.ctx, LB_REG(mmLB_DATA_FORMAT));
-+
-+	if (get_reg_field_value(value, LB_DATA_FORMAT, PREFETCH) == 1)
-+		return true;
-+
-+	return false;
-+}
-+
-+bool dce80_transform_get_current_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth *depth)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+	uint32_t value = 0;
-+
-+	if (depth == NULL)
-+		return false;
-+
-+	value = dm_read_reg(
-+			xfm->ctx,
-+			LB_REG(mmLB_DATA_FORMAT));
-+
-+	switch (get_reg_field_value(value, LB_DATA_FORMAT, PIXEL_DEPTH)) {
-+	case 0:
-+		*depth = LB_PIXEL_DEPTH_30BPP;
-+		break;
-+	case 1:
-+		*depth = LB_PIXEL_DEPTH_24BPP;
-+		break;
-+	case 2:
-+		*depth = LB_PIXEL_DEPTH_18BPP;
-+		break;
-+	case 3:
-+		*depth = LB_PIXEL_DEPTH_36BPP;
-+		break;
-+	default:
-+		dal_logger_write(xfm->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid LB pixel depth",
-+			__func__);
-+		*depth = LB_PIXEL_DEPTH_30BPP;
-+		break;
-+	}
-+	return true;
-+
-+}
-+
-+static void set_denormalization(
-+	struct dce80_transform *xfm80,
-+	enum dc_color_depth depth)
-+{
-+	uint32_t value = dm_read_reg(xfm80->base.ctx,
-+			DCP_REG(mmDENORM_CONTROL));
-+
-+	switch (depth) {
-+	case COLOR_DEPTH_666:
-+		/* 63/64 for 6 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_888:
-+		/* Unity for 8 bit output color depth
-+		 * because prescale is disabled by default */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 1023/1024 for 10 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 4095/4096 for 12 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			5,
-+			DENORM_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_141414:
-+	case COLOR_DEPTH_161616:
-+	default:
-+		/* not valid used case! */
-+		break;
-+	}
-+
-+	dm_write_reg(xfm80->base.ctx,
-+			DCP_REG(mmDENORM_CONTROL),
-+			value);
-+
-+}
-+
-+bool dce80_transform_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+	bool ret = true;
-+	uint32_t value;
-+	enum dc_color_depth color_depth;
-+
-+	value = dm_read_reg(
-+			xfm->ctx,
-+			LB_REG(mmLB_DATA_FORMAT));
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		color_depth = COLOR_DEPTH_666;
-+		set_reg_field_value(value, 2, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	case LB_PIXEL_DEPTH_24BPP:
-+		color_depth = COLOR_DEPTH_888;
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	case LB_PIXEL_DEPTH_30BPP:
-+		color_depth = COLOR_DEPTH_101010;
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		color_depth = COLOR_DEPTH_121212;
-+		set_reg_field_value(value, 3, LB_DATA_FORMAT, PIXEL_DEPTH);
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
-+		break;
-+	default:
-+		ret = false;
-+		break;
-+	}
-+
-+	if (ret == true) {
-+		set_denormalization(xfm80, color_depth);
-+		ret = program_bit_depth_reduction(xfm80, color_depth);
-+
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
-+		dm_write_reg(
-+				xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
-+		if (!(xfm80->lb_pixel_depth_supported & depth)) {
-+			/*we should use unsupported capabilities
-+			 *  unless it is required by w/a*/
-+			dal_logger_write(xfm->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: Capability not supported",
-+				__func__);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+/* LB_MEMORY_CONFIG
-+ *  00 - Use all three pieces of memory
-+ *  01 - Use only one piece of memory of total 720x144 bits
-+ *  10 - Use two pieces of memory of total 960x144 bits
-+ *  11 - reserved
-+ *
-+ * LB_MEMORY_SIZE
-+ *  Total entries of LB memory.
-+ *  This number should be larger than 960. The default value is 1712(0x6B0) */
-+bool dce80_transform_power_up_line_buffer(struct transform *xfm)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+	uint32_t value;
-+
-+	value = dm_read_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL));
-+
-+	/*Use all three pieces of memory always*/
-+	set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
-+	/*hard coded number DCE8 1712(0x6B0) Partitions: 720/960/1712*/
-+	set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LB_MEMORY_CTRL,
-+			LB_MEMORY_SIZE);
-+
-+	dm_write_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
-new file mode 100644
-index 0000000..af831f8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.h
-@@ -0,0 +1,51 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TRANSFORM_BIT_DEPTH_DCE80_H__
-+#define __DC_TRANSFORM_BIT_DEPTH_DCE80_H__
-+
-+#include "dce80_transform.h"
-+
-+bool dce80_transform_power_up_line_buffer(struct transform *xfm);
-+
-+bool dce80_transform_get_max_num_of_supported_lines(
-+	struct dce80_transform *xfm80,
-+	enum lb_pixel_depth depth,
-+	uint32_t pixel_width,
-+	uint32_t *lines);
-+
-+void dce80_transform_enable_alpha(
-+	struct dce80_transform *xfm80,
-+	bool enable);
-+
-+bool dce80_transform_get_next_lower_pixel_storage_depth(
-+	struct dce80_transform *xfm80,
-+	uint32_t display_bpp,
-+	enum lb_pixel_depth depth,
-+	enum lb_pixel_depth *lower_depth);
-+
-+bool dce80_transform_is_prefetch_enabled(
-+	struct dce80_transform *xfm80);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
-new file mode 100644
-index 0000000..df5db67
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
-@@ -0,0 +1,297 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce80_transform.h"
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+#include "include/fixed31_32.h"
-+#include "basics/conversion.h"
-+#include "include/grph_object_id.h"
-+
-+enum {
-+	GAMUT_MATRIX_SIZE = 12
-+};
-+
-+#define DCP_REG(reg)\
-+	(reg + xfm80->offsets.dcp_offset)
-+
-+#define DISP_BRIGHTNESS_DEFAULT_HW 0
-+#define DISP_BRIGHTNESS_MIN_HW -25
-+#define DISP_BRIGHTNESS_MAX_HW 25
-+#define DISP_BRIGHTNESS_STEP_HW 1
-+#define DISP_BRIGHTNESS_HW_DIVIDER 100
-+
-+#define DISP_HUE_DEFAULT_HW 0
-+#define DISP_HUE_MIN_HW -30
-+#define DISP_HUE_MAX_HW 30
-+#define DISP_HUE_STEP_HW 1
-+#define DISP_HUE_HW_DIVIDER 1
-+
-+#define DISP_CONTRAST_DEFAULT_HW 100
-+#define DISP_CONTRAST_MIN_HW 50
-+#define DISP_CONTRAST_MAX_HW 150
-+#define DISP_CONTRAST_STEP_HW 1
-+#define DISP_CONTRAST_HW_DIVIDER 100
-+
-+#define DISP_SATURATION_DEFAULT_HW 100
-+#define DISP_SATURATION_MIN_HW 0
-+#define DISP_SATURATION_MAX_HW 200
-+#define DISP_SATURATION_STEP_HW 1
-+#define DISP_SATURATION_HW_DIVIDER 100
-+
-+#define DISP_KELVIN_DEGRES_DEFAULT 6500
-+#define DISP_KELVIN_DEGRES_MIN 4000
-+#define DISP_KELVIN_DEGRES_MAX 10000
-+#define DISP_KELVIN_DEGRES_STEP 100
-+#define DISP_KELVIN_HW_DIVIDER 10000
-+
-+static void program_gamut_remap(
-+	struct dce80_transform *xfm80,
-+	const uint16_t *reg_val)
-+{
-+	struct dc_context *ctx = xfm80->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-+
-+	/* the register controls ovl also */
-+	value = dm_read_reg(ctx, addr);
-+
-+	if (reg_val) {
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C11_C12);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[0],
-+				GAMUT_REMAP_C11_C12,
-+				GAMUT_REMAP_C11);
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[1],
-+				GAMUT_REMAP_C11_C12,
-+				GAMUT_REMAP_C12);
-+
-+			dm_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C13_C14);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[2],
-+				GAMUT_REMAP_C13_C14,
-+				GAMUT_REMAP_C13);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[3],
-+				GAMUT_REMAP_C13_C14,
-+				GAMUT_REMAP_C14);
-+
-+			dm_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C21_C22);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[4],
-+				GAMUT_REMAP_C21_C22,
-+				GAMUT_REMAP_C21);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[5],
-+				GAMUT_REMAP_C21_C22,
-+				GAMUT_REMAP_C22);
-+
-+			dm_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C23_C24);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[6],
-+				GAMUT_REMAP_C23_C24,
-+				GAMUT_REMAP_C23);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[7],
-+				GAMUT_REMAP_C23_C24,
-+				GAMUT_REMAP_C24);
-+
-+			dm_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C31_C32);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[8],
-+				GAMUT_REMAP_C31_C32,
-+				GAMUT_REMAP_C31);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[9],
-+				GAMUT_REMAP_C31_C32,
-+				GAMUT_REMAP_C32);
-+
-+			dm_write_reg(ctx, addr, reg_data);
-+		}
-+		{
-+			uint32_t reg_data = 0;
-+			uint32_t addr = DCP_REG(mmGAMUT_REMAP_C33_C34);
-+
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[10],
-+				GAMUT_REMAP_C33_C34,
-+				GAMUT_REMAP_C33);
-+
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				reg_data,
-+				reg_val[11],
-+				GAMUT_REMAP_C33_C34,
-+				GAMUT_REMAP_C34);
-+
-+			dm_write_reg(ctx, addr, reg_data);
-+		}
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			GAMUT_REMAP_CONTROL,
-+			GRPH_GAMUT_REMAP_MODE);
-+
-+	} else
-+		set_reg_field_value(
-+			value,
-+			0,
-+			GAMUT_REMAP_CONTROL,
-+			GRPH_GAMUT_REMAP_MODE);
-+
-+	addr = DCP_REG(mmGAMUT_REMAP_CONTROL);
-+	dm_write_reg(ctx, addr, value);
-+
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_gamut_remap
-+ *
-+ *  @param [in] const struct grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and apply color temperature adjustment to in Rgb color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+void dce80_transform_set_gamut_remap(
-+	struct transform *xfm,
-+	const struct grph_csc_adjustment *adjust)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+
-+	if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW ||
-+		adjust->temperature_divider == 0)
-+		program_gamut_remap(xfm80, NULL);
-+	else {
-+		struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE];
-+		uint16_t arr_reg_val[GAMUT_MATRIX_SIZE];
-+
-+		arr_matrix[0] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[0],
-+				adjust->temperature_divider);
-+		arr_matrix[1] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[1],
-+				adjust->temperature_divider);
-+		arr_matrix[2] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[2],
-+				adjust->temperature_divider);
-+		arr_matrix[3] = dal_fixed31_32_zero;
-+
-+		arr_matrix[4] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[3],
-+				adjust->temperature_divider);
-+		arr_matrix[5] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[4],
-+				adjust->temperature_divider);
-+		arr_matrix[6] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[5],
-+				adjust->temperature_divider);
-+		arr_matrix[7] = dal_fixed31_32_zero;
-+
-+		arr_matrix[8] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[6],
-+				adjust->temperature_divider);
-+		arr_matrix[9] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[7],
-+				adjust->temperature_divider);
-+		arr_matrix[10] =
-+			dal_fixed31_32_from_fraction(
-+				adjust->temperature_matrix[8],
-+				adjust->temperature_divider);
-+		arr_matrix[11] = dal_fixed31_32_zero;
-+
-+		convert_float_matrix(
-+			arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
-+
-+		program_gamut_remap(xfm80, arr_reg_val);
-+	}
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-new file mode 100644
-index 0000000..62a3a04
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-@@ -0,0 +1,814 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dce80_transform.h"
-+
-+#define UP_SCALER_RATIO_MAX 16000
-+#define DOWN_SCALER_RATIO_MAX 250
-+#define SCALER_RATIO_DIVIDER 1000
-+
-+#define SCL_REG(reg)\
-+	(reg + xfm80->offsets.scl_offset)
-+
-+#define DCFE_REG(reg)\
-+	(reg + xfm80->offsets.crtc_offset)
-+
-+static void disable_enhanced_sharpness(struct dce80_transform *xfm80)
-+{
-+	uint32_t  value;
-+
-+	value = dm_read_reg(xfm80->base.ctx,
-+			SCL_REG(mmSCL_F_SHARP_CONTROL));
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_HF_SHARP_EN);
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_VF_SHARP_EN);
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_HF_SHARP_SCALE_FACTOR);
-+
-+	set_reg_field_value(value, 0,
-+			SCL_F_SHARP_CONTROL, SCL_VF_SHARP_SCALE_FACTOR);
-+
-+	dm_write_reg(xfm80->base.ctx,
-+			SCL_REG(mmSCL_F_SHARP_CONTROL), value);
-+}
-+
-+/**
-+* Function:
-+* void setup_scaling_configuration
-+*
-+* Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
-+* Input:   data
-+*
-+* Output:
-+   void
-+*/
-+static bool setup_scaling_configuration(
-+	struct dce80_transform *xfm80,
-+	const struct scaler_data *data)
-+{
-+	struct dc_context *ctx = xfm80->base.ctx;
-+	uint32_t addr;
-+	uint32_t value;
-+
-+	if (data->taps.h_taps + data->taps.v_taps <= 2) {
-+		dce80_transform_set_scaler_bypass(&xfm80->base);
-+		return false;
-+	}
-+
-+	{
-+		addr = SCL_REG(mmSCL_MODE);
-+		value = dm_read_reg(ctx, addr);
-+
-+		if (data->dal_pixel_format <= PIXEL_FORMAT_GRPH_END)
-+			set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
-+		else
-+			set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		addr = SCL_REG(mmSCL_TAP_CONTROL);
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(value, data->taps.h_taps - 1,
-+				SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+
-+		set_reg_field_value(value, data->taps.v_taps - 1,
-+				SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	{
-+		addr = SCL_REG(mmSCL_CONTROL);
-+		value = dm_read_reg(ctx, addr);
-+		 /* 1 - Replaced out of bound pixels with edge */
-+		set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
-+
-+		/* 1 - Replaced out of bound pixels with the edge pixel. */
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	return true;
-+}
-+
-+/**
-+* Function:
-+* void program_overscan
-+*
-+* Purpose: Programs overscan border
-+* Input:   overscan
-+*
-+* Output:
-+   void
-+*/
-+static void program_overscan(
-+		struct dce80_transform *xfm80,
-+		const struct overscan_info *overscan)
-+{
-+	uint32_t overscan_left_right = 0;
-+	uint32_t overscan_top_bottom = 0;
-+
-+	set_reg_field_value(overscan_left_right, overscan->left,
-+			EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-+
-+	set_reg_field_value(overscan_left_right, overscan->right,
-+			EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->top,
-+			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan->bottom,
-+			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-+
-+	dm_write_reg(xfm80->base.ctx,
-+			SCL_REG(mmEXT_OVERSCAN_LEFT_RIGHT),
-+			overscan_left_right);
-+
-+	dm_write_reg(xfm80->base.ctx,
-+			SCL_REG(mmEXT_OVERSCAN_TOP_BOTTOM),
-+			overscan_top_bottom);
-+}
-+
-+static void program_two_taps_filter(
-+	struct dce80_transform *xfm80,
-+	bool enable,
-+	bool vertical)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+	/* 1: Hard coded 2 tap filter
-+	 * 0: Programmable 2 tap filter from coefficient RAM
-+	 */
-+	if (vertical) {
-+		addr = SCL_REG(mmSCL_VERT_FILTER_CONTROL);
-+		value = dm_read_reg(xfm80->base.ctx, addr);
-+		set_reg_field_value(
-+			value,
-+			enable ? 1 : 0,
-+				SCL_VERT_FILTER_CONTROL,
-+				SCL_V_2TAP_HARDCODE_COEF_EN);
-+
-+	} else {
-+		addr = SCL_REG(mmSCL_HORZ_FILTER_CONTROL);
-+		value = dm_read_reg(xfm80->base.ctx, addr);
-+		set_reg_field_value(
-+			value,
-+			enable ? 1 : 0,
-+			SCL_HORZ_FILTER_CONTROL,
-+			SCL_H_2TAP_HARDCODE_COEF_EN);
-+	}
-+
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+}
-+
-+static void set_coeff_update_complete(struct dce80_transform *xfm80)
-+{
-+	uint32_t value;
-+	uint32_t addr = SCL_REG(mmSCL_UPDATE);
-+
-+	value = dm_read_reg(xfm80->base.ctx, addr);
-+	set_reg_field_value(value, 1,
-+			SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE);
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+}
-+
-+static void program_filter(
-+	struct dce80_transform *xfm80,
-+	enum ram_filter_type filter_type,
-+	struct scaler_filter_params *scl_filter_params,
-+	uint32_t *coeffs,
-+	uint32_t coeffs_num)
-+{
-+	uint32_t phase = 0;
-+	uint32_t array_idx = 0;
-+	uint32_t pair = 0;
-+
-+	uint32_t taps_pairs = (scl_filter_params->taps + 1) / 2;
-+	uint32_t phases_to_program = scl_filter_params->phases / 2 + 1;
-+
-+	uint32_t i;
-+	uint32_t addr;
-+	uint32_t select_addr;
-+	uint32_t select;
-+	uint32_t data;
-+	/* We need to disable power gating on coeff memory to do programming */
-+
-+	uint32_t pwr_ctrl_orig;
-+	uint32_t pwr_ctrl_off;
-+
-+	addr = DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL);
-+	pwr_ctrl_orig = dm_read_reg(xfm80->base.ctx, addr);
-+	pwr_ctrl_off = pwr_ctrl_orig;
-+	set_reg_field_value(
-+		pwr_ctrl_off,
-+		1,
-+		DCFE_MEM_LIGHT_SLEEP_CNTL,
-+		SCL_LIGHT_SLEEP_DIS);
-+	dm_write_reg(xfm80->base.ctx, addr, pwr_ctrl_off);
-+
-+	/* Wait to disable gating: */
-+	for (i = 0;
-+		i < 10 &&
-+		get_reg_field_value(
-+			dm_read_reg(xfm80->base.ctx, addr),
-+			DCFE_MEM_LIGHT_SLEEP_CNTL,
-+			SCL_MEM_PWR_STATE);
-+		i++)
-+		dm_delay_in_microseconds(xfm80->base.ctx, 1);
-+
-+	ASSERT(i < 10);
-+
-+	select_addr = SCL_REG(mmSCL_COEF_RAM_SELECT);
-+	select = dm_read_reg(xfm80->base.ctx, select_addr);
-+
-+	set_reg_field_value(
-+		select,
-+		filter_type,
-+		SCL_COEF_RAM_SELECT,
-+		SCL_C_RAM_FILTER_TYPE);
-+	set_reg_field_value(
-+		select,
-+		0,
-+		SCL_COEF_RAM_SELECT,
-+		SCL_C_RAM_TAP_PAIR_IDX);
-+	set_reg_field_value(
-+		select,
-+		0,
-+		SCL_COEF_RAM_SELECT,
-+		SCL_C_RAM_PHASE);
-+
-+	data = 0;
-+
-+	for (phase = 0; phase < phases_to_program; phase++) {
-+		/* we always program N/2 + 1 phases, total phases N, but N/2-1
-+		 * are just mirror phase 0 is unique and phase N/2 is unique
-+		 * if N is even
-+		 */
-+
-+		set_reg_field_value(
-+			select,
-+			phase,
-+			SCL_COEF_RAM_SELECT,
-+			SCL_C_RAM_PHASE);
-+
-+		for (pair = 0; pair < taps_pairs; pair++) {
-+			set_reg_field_value(
-+				select,
-+				pair,
-+				SCL_COEF_RAM_SELECT,
-+				SCL_C_RAM_TAP_PAIR_IDX);
-+			dm_write_reg(xfm80->base.ctx, select_addr, select);
-+
-+			/* even tap write enable */
-+			set_reg_field_value(
-+				data,
-+				1,
-+				SCL_COEF_RAM_TAP_DATA,
-+				SCL_C_RAM_EVEN_TAP_COEF_EN);
-+			/* even tap data */
-+			set_reg_field_value(
-+				data,
-+				coeffs[array_idx],
-+				SCL_COEF_RAM_TAP_DATA,
-+				SCL_C_RAM_EVEN_TAP_COEF);
-+
-+			/* if we have odd number of taps and the last pair is
-+			 * here then we do not need to program
-+			 */
-+			if (scl_filter_params->taps % 2 &&
-+				pair == taps_pairs - 1) {
-+				/* odd tap write disable */
-+				set_reg_field_value(
-+					data,
-+					0,
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF_EN);
-+				set_reg_field_value(
-+					data,
-+					0,
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF);
-+				array_idx += 1;
-+			} else {
-+				/* odd tap write enable */
-+				set_reg_field_value(
-+					data,
-+					1,
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF_EN);
-+				/* dbg_val: 0x1000 / sclFilterParams->taps; */
-+				set_reg_field_value(
-+					data,
-+					coeffs[array_idx + 1],
-+					SCL_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_ODD_TAP_COEF);
-+
-+				array_idx += 2;
-+			}
-+
-+			dm_write_reg(
-+				xfm80->base.ctx,
-+				SCL_REG(mmSCL_COEF_RAM_TAP_DATA),
-+				data);
-+		}
-+	}
-+
-+	ASSERT(coeffs_num == array_idx);
-+
-+	/* reset the power gating register */
-+	dm_write_reg(
-+		xfm80->base.ctx,
-+		DCFE_REG(mmDCFE_MEM_LIGHT_SLEEP_CNTL),
-+		pwr_ctrl_orig);
-+
-+	set_coeff_update_complete(xfm80);
-+}
-+
-+/*
-+ *
-+ * Populates an array with filter coefficients in 1.1.12 fixed point form
-+*/
-+static bool get_filter_coefficients(
-+	struct dce80_transform *xfm80,
-+	uint32_t taps,
-+	uint32_t **data_tab,
-+	uint32_t *data_size)
-+{
-+	uint32_t num = 0;
-+	uint32_t i;
-+	const struct fixed31_32 *filter =
-+		dal_scaler_filter_get(
-+			xfm80->base.filter,
-+			data_tab,
-+			&num);
-+	uint32_t *data_row;
-+
-+	if (!filter) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+	data_row = *data_tab;
-+
-+	for (i = 0; i < num; ++i) {
-+		/* req. format sign fixed 1.1.12, the values are always between
-+		 * [-1; 1]
-+		 *
-+		 * Each phase is mirrored as follows :
-+		 * 0 : Phase 0
-+		 * 1 : Phase 1 or Phase 64 - 1 / 128 - 1
-+		 * N : Phase N or Phase 64 - N / 128 - N
-+		 *
-+		 * Convert from Fixed31_32 to 1.1.12 by using floor on value
-+		 * shifted by number of required fractional bits(12)
-+		 */
-+		struct fixed31_32 value = filter[i];
-+
-+		data_row[i] =
-+			dal_fixed31_32_floor(dal_fixed31_32_shl(value, 12)) &
-+			0x3FFC;
-+	}
-+	*data_size = num;
-+
-+	return true;
-+}
-+
-+static bool program_multi_taps_filter(
-+	struct dce80_transform *xfm80,
-+	const struct scaler_data *data,
-+	bool horizontal)
-+{
-+	struct scaler_filter_params filter_params;
-+	enum ram_filter_type filter_type;
-+	uint32_t src_size;
-+	uint32_t dst_size;
-+
-+	uint32_t *filter_data = NULL;
-+	uint32_t filter_data_size = 0;
-+
-+	/* 16 phases total for DCE8 */
-+	filter_params.phases = 16;
-+
-+	if (horizontal) {
-+		filter_params.taps = data->taps.h_taps;
-+		filter_params.sharpness = data->h_sharpness;
-+		filter_params.flags.bits.HORIZONTAL = 1;
-+
-+		src_size = data->viewport.width;
-+		dst_size =
-+			dal_fixed31_32_floor(
-+				dal_fixed31_32_div(
-+					dal_fixed31_32_from_int(
-+						data->viewport.width),
-+					data->ratios->horz));
-+
-+		filter_type = FILTER_TYPE_RGB_Y_HORIZONTAL;
-+	} else {
-+		filter_params.taps = data->taps.v_taps;
-+		filter_params.sharpness = data->v_sharpness;
-+		filter_params.flags.bits.HORIZONTAL = 0;
-+
-+		src_size = data->viewport.height;
-+		dst_size =
-+			dal_fixed31_32_floor(
-+				dal_fixed31_32_div(
-+					dal_fixed31_32_from_int(
-+						data->viewport.height),
-+					data->ratios->vert));
-+
-+		filter_type = FILTER_TYPE_RGB_Y_VERTICAL;
-+	}
-+
-+	/* 1. Generate the coefficients */
-+	if (!dal_scaler_filter_generate(
-+		xfm80->base.filter,
-+		&filter_params,
-+		src_size,
-+		dst_size))
-+		return false;
-+
-+	/* 2. Convert coefficients to fixed point format 1.12 (note coeff.
-+	 * could be negative(!) and  range is [ from -1 to 1 ]) */
-+	if (!get_filter_coefficients(
-+		xfm80,
-+		filter_params.taps,
-+		&filter_data,
-+		&filter_data_size))
-+		return false;
-+
-+	/* 3. Program the filter */
-+	program_filter(
-+		xfm80,
-+		filter_type,
-+		&filter_params,
-+		filter_data,
-+		filter_data_size);
-+
-+	/* 4. Program the alpha if necessary */
-+	if (data->flags.bits.SHOULD_PROGRAM_ALPHA) {
-+		if (horizontal)
-+			filter_type = FILTER_TYPE_ALPHA_HORIZONTAL;
-+		else
-+			filter_type = FILTER_TYPE_ALPHA_VERTICAL;
-+
-+		program_filter(
-+			xfm80,
-+			filter_type,
-+			&filter_params,
-+			filter_data,
-+			filter_data_size);
-+	}
-+
-+	return true;
-+}
-+
-+static void program_viewport(
-+	struct dce80_transform *xfm80,
-+	const struct rect *view_port)
-+{
-+	struct dc_context *ctx = xfm80->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+
-+	addr = SCL_REG(mmVIEWPORT_START);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		view_port->x,
-+		VIEWPORT_START,
-+		VIEWPORT_X_START);
-+	set_reg_field_value(
-+		value,
-+		view_port->y,
-+		VIEWPORT_START,
-+		VIEWPORT_Y_START);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = SCL_REG(mmVIEWPORT_SIZE);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		view_port->height,
-+		VIEWPORT_SIZE,
-+		VIEWPORT_HEIGHT);
-+	set_reg_field_value(
-+		value,
-+		view_port->width,
-+		VIEWPORT_SIZE,
-+		VIEWPORT_WIDTH);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* TODO: add stereo support */
-+}
-+
-+static void calculate_inits(
-+	struct dce80_transform *xfm80,
-+	const struct scaler_data *data,
-+	struct scl_ratios_inits *inits)
-+{
-+	struct fixed31_32 h_init;
-+	struct fixed31_32 v_init;
-+	struct fixed31_32 v_init_bot;
-+
-+	inits->bottom_enable = 0;
-+	inits->h_int_scale_ratio =
-+		dal_fixed31_32_u2d19(data->ratios->horz) << 5;
-+	inits->v_int_scale_ratio =
-+		dal_fixed31_32_u2d19(data->ratios->vert) << 5;
-+
-+	h_init =
-+		dal_fixed31_32_div_int(
-+			dal_fixed31_32_add(
-+				data->ratios->horz,
-+				dal_fixed31_32_from_int(data->taps.h_taps + 1)),
-+				2);
-+	inits->h_init.integer = dal_fixed31_32_floor(h_init);
-+	inits->h_init.fraction = dal_fixed31_32_u0d19(h_init) << 5;
-+
-+	v_init =
-+		dal_fixed31_32_div_int(
-+			dal_fixed31_32_add(
-+				data->ratios->vert,
-+				dal_fixed31_32_from_int(data->taps.v_taps + 1)),
-+				2);
-+	inits->v_init.integer = dal_fixed31_32_floor(v_init);
-+	inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
-+
-+	if (data->flags.bits.INTERLACED) {
-+		v_init_bot =
-+			dal_fixed31_32_add(
-+				dal_fixed31_32_div_int(
-+					dal_fixed31_32_add(
-+						data->ratios->vert,
-+						dal_fixed31_32_from_int(
-+							data->taps.v_taps + 1)),
-+					2),
-+				data->ratios->vert);
-+		inits->v_init_bottom.integer = dal_fixed31_32_floor(v_init_bot);
-+		inits->v_init_bottom.fraction =
-+			dal_fixed31_32_u0d19(v_init_bot) << 5;
-+
-+		inits->bottom_enable = 1;
-+	}
-+}
-+
-+static void program_scl_ratios_inits(
-+	struct dce80_transform *xfm80,
-+	struct scl_ratios_inits *inits)
-+{
-+	uint32_t addr = SCL_REG(mmSCL_HORZ_FILTER_SCALE_RATIO);
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio,
-+		SCL_HORZ_FILTER_SCALE_RATIO,
-+		SCL_H_SCALE_RATIO);
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+
-+	addr = SCL_REG(mmSCL_VERT_FILTER_SCALE_RATIO);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio,
-+		SCL_VERT_FILTER_SCALE_RATIO,
-+		SCL_V_SCALE_RATIO);
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+
-+	addr = SCL_REG(mmSCL_HORZ_FILTER_INIT);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_init.integer,
-+		SCL_HORZ_FILTER_INIT,
-+		SCL_H_INIT_INT);
-+	set_reg_field_value(
-+		value,
-+		inits->h_init.fraction,
-+		SCL_HORZ_FILTER_INIT,
-+		SCL_H_INIT_FRAC);
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+
-+	addr = SCL_REG(mmSCL_VERT_FILTER_INIT);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_init.integer,
-+		SCL_VERT_FILTER_INIT,
-+		SCL_V_INIT_INT);
-+	set_reg_field_value(
-+		value,
-+		inits->v_init.fraction,
-+		SCL_VERT_FILTER_INIT,
-+		SCL_V_INIT_FRAC);
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+
-+	if (inits->bottom_enable) {
-+		addr = SCL_REG(mmSCL_VERT_FILTER_INIT_BOT);
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			inits->v_init_bottom.integer,
-+			SCL_VERT_FILTER_INIT_BOT,
-+			SCL_V_INIT_INT_BOT);
-+		set_reg_field_value(
-+			value,
-+			inits->v_init_bottom.fraction,
-+			SCL_VERT_FILTER_INIT_BOT,
-+			SCL_V_INIT_FRAC_BOT);
-+		dm_write_reg(xfm80->base.ctx, addr, value);
-+	}
-+
-+	addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		0,
-+		SCL_AUTOMATIC_MODE_CONTROL,
-+		SCL_V_CALC_AUTO_RATIO_EN);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		SCL_AUTOMATIC_MODE_CONTROL,
-+		SCL_H_CALC_AUTO_RATIO_EN);
-+	dm_write_reg(xfm80->base.ctx, addr, value);
-+}
-+
-+static void get_viewport(
-+		struct dce80_transform *xfm80,
-+		struct rect *current_view_port)
-+{
-+	uint32_t value_start;
-+	uint32_t value_size;
-+
-+	if (current_view_port == NULL)
-+		return;
-+
-+	value_start = dm_read_reg(xfm80->base.ctx, SCL_REG(mmVIEWPORT_START));
-+	value_size = dm_read_reg(xfm80->base.ctx, SCL_REG(mmVIEWPORT_SIZE));
-+
-+	current_view_port->x = get_reg_field_value(
-+			value_start,
-+			VIEWPORT_START,
-+			VIEWPORT_X_START);
-+	current_view_port->y = get_reg_field_value(
-+			value_start,
-+			VIEWPORT_START,
-+			VIEWPORT_Y_START);
-+	current_view_port->height = get_reg_field_value(
-+			value_size,
-+			VIEWPORT_SIZE,
-+			VIEWPORT_HEIGHT);
-+	current_view_port->width = get_reg_field_value(
-+			value_size,
-+			VIEWPORT_SIZE,
-+			VIEWPORT_WIDTH);
-+}
-+
-+
-+bool dce80_transform_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+	bool is_scaling_required;
-+	struct dc_context *ctx = xfm->ctx;
-+
-+	{
-+		uint32_t addr = SCL_REG(mmSCL_BYPASS_CONTROL);
-+		uint32_t value = dm_read_reg(xfm->ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			SCL_BYPASS_CONTROL,
-+			SCL_BYPASS_MODE);
-+		dm_write_reg(xfm->ctx, addr, value);
-+	}
-+
-+	disable_enhanced_sharpness(xfm80);
-+
-+	/* 3. Program overscan */
-+	program_overscan(xfm80, &data->overscan);
-+
-+	/* 4. Program taps and configuration */
-+	is_scaling_required = setup_scaling_configuration(xfm80, data);
-+	if (is_scaling_required) {
-+		/* 5. Calculate and program ratio, filter initialization */
-+		struct scl_ratios_inits inits = { 0 };
-+
-+		calculate_inits(xfm80, data, &inits);
-+
-+		program_scl_ratios_inits(xfm80, &inits);
-+
-+		/* 6. Program vertical filters */
-+		if (data->taps.v_taps > 2) {
-+			program_two_taps_filter(xfm80, false, true);
-+
-+			if (!program_multi_taps_filter(xfm80, data, false)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed vertical taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter(xfm80, true, true);
-+
-+		/* 7. Program horizontal filters */
-+		if (data->taps.h_taps > 2) {
-+			program_two_taps_filter(xfm80, false, false);
-+
-+			if (!program_multi_taps_filter(xfm80, data, true)) {
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_DCP,
-+					LOG_MINOR_DCP_SCALER,
-+					"Failed horizontal taps programming\n");
-+				return false;
-+			}
-+		} else
-+			program_two_taps_filter(xfm80, true, false);
-+	}
-+
-+	return true;
-+}
-+
-+void dce80_transform_set_scaler_bypass(struct transform *xfm)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+	uint32_t sclv_mode;
-+
-+	disable_enhanced_sharpness(xfm80);
-+
-+	sclv_mode = dm_read_reg(xfm->ctx, SCL_REG(mmSCL_MODE));
-+	set_reg_field_value(sclv_mode, 0, SCL_MODE, SCL_MODE);
-+	dm_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
-+}
-+
-+bool dce80_transform_update_viewport(
-+	struct transform *xfm,
-+	const struct rect *view_port,
-+	bool is_fbc_attached)
-+{
-+	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
-+	bool program_req = false;
-+	struct rect current_view_port;
-+
-+	if (view_port == NULL)
-+		return program_req;
-+
-+	get_viewport(xfm80, &current_view_port);
-+
-+	if (current_view_port.x != view_port->x ||
-+			current_view_port.y != view_port->y ||
-+			current_view_port.height != view_port->height ||
-+			current_view_port.width != view_port->width)
-+		program_req = true;
-+
-+	if (program_req) {
-+		/*underlay viewport is programmed with scaler
-+		 *program_viewport function pointer is not exposed*/
-+		program_viewport(xfm80, view_port);
-+	}
-+
-+	return program_req;
-+}
-+
-+void dce80_transform_set_scaler_filter(
-+	struct transform *xfm,
-+	struct scaler_filter *filter)
-+{
-+	xfm->filter = filter;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-index 2507bb5..a0d165c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/Makefile
-@@ -9,6 +9,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
- 
- AMD_DAL_FILES += $(AMD_DAL_GPIO)
- 
-+###############################################################################
-+# DCE 8x
-+###############################################################################
-+# all DCE8.x are derived from DCE8.0
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+GPIO_DCE80 = hw_translate_dce80.o hw_factory_dce80.o \
-+	hw_ddc_dce80.o hw_hpd_dce80.o
-+
-+AMD_DAL_GPIO_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpio/dce80/,$(GPIO_DCE80))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPIO_DCE80)
-+endif
- 
- ###############################################################################
- # DCE 11x
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-new file mode 100644
-index 0000000..850caeb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-@@ -0,0 +1,893 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/gpio_types.h"
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_ddc_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_HW_DDC(ptr) \
-+	container_of((ptr), struct hw_ddc_dce80, base)
-+
-+#define FROM_HW_GPIO(ptr) \
-+	FROM_HW_DDC(container_of((ptr), struct hw_ddc, base))
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	FROM_HW_GPIO(container_of((ptr), struct hw_gpio, base))
-+
-+static void destruct(
-+	struct hw_ddc_dce80 *pin)
-+{
-+	dal_hw_ddc_destruct(&pin->base);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_ddc_dce80 *pin = FROM_HW_GPIO_PIN(*ptr);
-+
-+	destruct(pin);
-+
-+	dm_free((*ptr)->ctx, pin);
-+
-+	*ptr = NULL;
-+}
-+
-+static void setup_i2c_polling(
-+	struct dc_context *ctx,
-+	const uint32_t addr,
-+	bool enable_detect,
-+	bool detect_mode)
-+{
-+	uint32_t value;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		enable_detect,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_ENABLE);
-+
-+	set_reg_field_value(
-+		value,
-+		enable_detect,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_EDID_DETECT_ENABLE);
-+
-+	if (enable_detect)
-+		set_reg_field_value(
-+			value,
-+			detect_mode,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_EDID_DETECT_MODE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static enum gpio_result set_config(
-+	struct hw_gpio_pin *ptr,
-+	const struct gpio_config_data *config_data)
-+{
-+	struct hw_ddc_dce80 *pin = FROM_HW_GPIO_PIN(ptr);
-+	struct hw_gpio *hw_gpio = NULL;
-+	uint32_t addr;
-+	uint32_t regval;
-+	uint32_t ddc_data_pd_en = 0;
-+	uint32_t ddc_clk_pd_en = 0;
-+	uint32_t aux_pad_mode = 0;
-+
-+	hw_gpio = &pin->base.base;
-+
-+	if (hw_gpio == NULL) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	/* switch dual mode GPIO to I2C/AUX mode */
-+
-+	addr = hw_gpio->pin_reg.DC_GPIO_DATA_MASK.addr;
-+
-+	regval = dm_read_reg(ptr->ctx, addr);
-+
-+	ddc_data_pd_en = get_reg_field_value(
-+			regval,
-+			DC_GPIO_DDC1_MASK,
-+			DC_GPIO_DDC1DATA_PD_EN);
-+
-+	ddc_clk_pd_en = get_reg_field_value(
-+			regval,
-+			DC_GPIO_DDC1_MASK,
-+			DC_GPIO_DDC1CLK_PD_EN);
-+
-+	aux_pad_mode = get_reg_field_value(
-+			regval,
-+			DC_GPIO_DDC1_MASK,
-+			AUX_PAD1_MODE);
-+
-+	switch (config_data->config.ddc.type) {
-+	case GPIO_DDC_CONFIG_TYPE_MODE_I2C:
-+		/* On plug-in, there is a transient level on the pad
-+		 * which must be discharged through the internal pull-down.
-+		 * Enable internal pull-down, 2.5msec discharge time
-+		 * is required for detection of AUX mode */
-+		if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
-+			if (!ddc_data_pd_en || !ddc_clk_pd_en) {
-+				set_reg_field_value(
-+					regval,
-+					1,
-+					DC_GPIO_DDC1_MASK,
-+					DC_GPIO_DDC1DATA_PD_EN);
-+
-+				set_reg_field_value(
-+					regval,
-+					1,
-+					DC_GPIO_DDC1_MASK,
-+					DC_GPIO_DDC1CLK_PD_EN);
-+
-+				dm_write_reg(ptr->ctx, addr, regval);
-+
-+				if (config_data->type ==
-+					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					/* should not affect normal I2C R/W */
-+					/* [anaumov] in DAL2, there was
-+					 * dc_service_delay_in_microseconds(2500); */
-+					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+			}
-+		} else {
-+			uint32_t reg2 = regval;
-+			uint32_t sda_pd_dis = 0;
-+			uint32_t scl_pd_dis = 0;
-+
-+			sda_pd_dis = get_reg_field_value(
-+					reg2,
-+					DC_GPIO_I2CPAD_MASK,
-+					DC_GPIO_SDA_PD_DIS);
-+
-+			scl_pd_dis = get_reg_field_value(
-+					reg2,
-+					DC_GPIO_I2CPAD_MASK,
-+					DC_GPIO_SCL_PD_DIS);
-+
-+			if (sda_pd_dis) {
-+				sda_pd_dis = 0;
-+
-+				dm_write_reg(ptr->ctx, addr, reg2);
-+
-+				if (config_data->type ==
-+					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					/* should not affect normal I2C R/W */
-+					/* [anaumov] in DAL2, there was
-+					 * dc_service_delay_in_microseconds(2500); */
-+					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+			}
-+
-+			if (!scl_pd_dis) {
-+				scl_pd_dis = 1;
-+
-+				dm_write_reg(ptr->ctx, addr, reg2);
-+
-+				if (config_data->type ==
-+					GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					/* should not affect normal I2C R/W */
-+					/* [anaumov] in DAL2, there was
-+					 * dc_service_delay_in_microseconds(2500); */
-+					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+			}
-+		}
-+
-+		if (aux_pad_mode) {
-+			/* let pins to get de-asserted
-+			 * before setting pad to I2C mode */
-+			if (config_data->config.ddc.data_en_bit_present ||
-+				config_data->config.ddc.clock_en_bit_present)
-+				/* [anaumov] in DAL2, there was
-+				 * dc_service_delay_in_microseconds(2000); */
-+				dm_sleep_in_milliseconds(ptr->ctx, 2);
-+
-+			/* set the I2C pad mode */
-+			/* read the register again,
-+			 * some bits may have been changed */
-+			regval = dm_read_reg(ptr->ctx, addr);
-+
-+			set_reg_field_value(
-+				regval,
-+				0,
-+				DC_GPIO_DDC1_MASK,
-+				AUX_PAD1_MODE);
-+
-+			dm_write_reg(ptr->ctx, addr, regval);
-+		}
-+
-+		return GPIO_RESULT_OK;
-+	case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
-+		/* set the AUX pad mode */
-+		if (!aux_pad_mode) {
-+			set_reg_field_value(
-+				regval,
-+				1,
-+				DC_GPIO_DDC1_MASK,
-+				AUX_PAD1_MODE);
-+
-+			dm_write_reg(ptr->ctx, addr, regval);
-+		}
-+
-+		return GPIO_RESULT_OK;
-+	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			setup_i2c_polling(
-+				ptr->ctx, pin->addr.dc_i2c_ddc_setup, 1, 0);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			setup_i2c_polling(
-+				ptr->ctx, pin->addr.dc_i2c_ddc_setup, 1, 1);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			setup_i2c_polling(
-+				ptr->ctx, pin->addr.dc_i2c_ddc_setup, 0, 0);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+}
-+
-+struct hw_ddc_dce80_init {
-+	struct hw_gpio_pin_reg hw_gpio_data_reg;
-+	struct hw_ddc_mask hw_ddc_mask;
-+	struct hw_ddc_dce80_addr hw_ddc_dce80_addr;
-+};
-+
-+static const struct hw_ddc_dce80_init
-+	hw_ddc_dce80_init_data[GPIO_DDC_LINE_COUNT] = {
-+	/* GPIO_DDC_LINE_DDC1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC1_MASK,
-+				DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_A,
-+				DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_EN,
-+				DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_Y,
-+				DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK,
-+			DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK,
-+			DC_GPIO_DDC1_MASK__AUX1_POL_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC1_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC2 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC2_MASK,
-+				DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_A,
-+				DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_EN,
-+				DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_Y,
-+				DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK,
-+			DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK,
-+			DC_GPIO_DDC2_MASK__AUX2_POL_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC2_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC3 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC3_MASK,
-+				DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_A,
-+				DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_EN,
-+				DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_Y,
-+				DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK,
-+			DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK,
-+			DC_GPIO_DDC3_MASK__AUX3_POL_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC3_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC4 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC4_MASK,
-+				DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_A,
-+				DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_EN,
-+				DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_Y,
-+				DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK,
-+			DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK,
-+			DC_GPIO_DDC4_MASK__AUX4_POL_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC4_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC5 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC5_MASK,
-+				DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_A,
-+				DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_EN,
-+				DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_Y,
-+				DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK,
-+			DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK,
-+			DC_GPIO_DDC5_MASK__AUX5_POL_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC5_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC6 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC6_MASK,
-+				DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_A,
-+				DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_EN,
-+				DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_Y,
-+				DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK,
-+			DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK,
-+			DC_GPIO_DDC6_MASK__AUX6_POL_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC6_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC_VGA */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDCVGA_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_A,
-+				DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_EN,
-+				DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_Y,
-+				DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDCVGA_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_I2CPAD */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_I2CPAD_MASK,
-+				DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_A,
-+				DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_EN,
-+				DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_Y,
-+				DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK,
-+			0,
-+			0,
-+			0
-+		},
-+		{
-+			0
-+		}
-+	}
-+};
-+
-+static const struct hw_ddc_dce80_init
-+	hw_ddc_dce80_init_clock[GPIO_DDC_LINE_COUNT] = {
-+	/* GPIO_DDC_LINE_DDC1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC1_MASK,
-+				DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_A,
-+				DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_EN,
-+				DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC1_Y,
-+				DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK,
-+			DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK,
-+			DC_GPIO_DDC1_MASK__AUX1_POL_MASK,
-+			DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC1_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC2 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC2_MASK,
-+				DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_A,
-+				DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_EN,
-+				DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC2_Y,
-+				DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK,
-+			DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK,
-+			DC_GPIO_DDC2_MASK__AUX2_POL_MASK,
-+			DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC2_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC3 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC3_MASK,
-+				DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_A,
-+				DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_EN,
-+				DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC3_Y,
-+				DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK,
-+			DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK,
-+			DC_GPIO_DDC3_MASK__AUX3_POL_MASK,
-+			DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC3_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC4 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC4_MASK,
-+				DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_A,
-+				DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_EN,
-+				DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC4_Y,
-+				DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK,
-+			DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK,
-+			DC_GPIO_DDC4_MASK__AUX4_POL_MASK,
-+			DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC4_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC5 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC5_MASK,
-+				DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_A,
-+				DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_EN,
-+				DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC5_Y,
-+				DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK,
-+			DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK,
-+			DC_GPIO_DDC5_MASK__AUX5_POL_MASK,
-+			DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC5_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC6 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDC6_MASK,
-+				DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_A,
-+				DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_EN,
-+				DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDC6_Y,
-+				DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK,
-+			DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK,
-+			DC_GPIO_DDC6_MASK__AUX6_POL_MASK,
-+			DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDC6_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_DDC_VGA */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_DDCVGA_MASK,
-+				DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_A,
-+				DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_EN,
-+				DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_DDCVGA_Y,
-+				DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK,
-+			DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK,
-+			DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK
-+		},
-+		{
-+			mmDC_I2C_DDCVGA_SETUP
-+		}
-+	},
-+	/* GPIO_DDC_LINE_I2CPAD */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_I2CPAD_MASK,
-+				DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_A,
-+				DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_EN,
-+				DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_I2CPAD_Y,
-+				DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK
-+			}
-+		},
-+		{
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK,
-+			DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK,
-+			0,
-+			0,
-+			0
-+		},
-+		{
-+			0
-+		}
-+	}
-+};
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = dal_hw_ddc_open,
-+	.get_value = dal_hw_gpio_get_value,
-+	.set_value = dal_hw_gpio_set_value,
-+	.set_config = set_config,
-+	.change_mode = dal_hw_gpio_change_mode,
-+	.close = dal_hw_gpio_close,
-+};
-+
-+static bool construct(
-+	struct hw_ddc_dce80 *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	const struct hw_ddc_dce80_init *init;
-+
-+	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!dal_hw_ddc_construct(&pin->base, id, en, ctx)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	pin->base.base.base.funcs = &funcs;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		init = hw_ddc_dce80_init_data + en;
-+
-+		pin->base.base.pin_reg = init->hw_gpio_data_reg;
-+		pin->base.mask = init->hw_ddc_mask;
-+		pin->addr = init->hw_ddc_dce80_addr;
-+
-+		return true;
-+	case GPIO_ID_DDC_CLOCK:
-+		init = hw_ddc_dce80_init_clock + en;
-+
-+		pin->base.base.pin_reg = init->hw_gpio_data_reg;
-+		pin->base.mask = init->hw_ddc_mask;
-+		pin->addr = init->hw_ddc_dce80_addr;
-+
-+		return true;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+	}
-+
-+	dal_hw_ddc_destruct(&pin->base);
-+
-+	return false;
-+}
-+
-+struct hw_gpio_pin *dal_hw_ddc_dce80_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_ddc_dce80 *pin = dm_alloc(ctx, sizeof(struct hw_ddc_dce80));
-+
-+	if (!pin) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(pin, id, en, ctx))
-+		return &pin->base.base.base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(ctx, pin);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.h
-new file mode 100644
-index 0000000..f5bbb83
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.h
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_DDC_DCE80_H__
-+#define __DAL_HW_DDC_DCE80_H__
-+
-+struct hw_ddc_dce80_addr {
-+	uint32_t dc_i2c_ddc_setup;
-+};
-+
-+struct hw_ddc_dce80 {
-+	struct hw_ddc base;
-+	struct hw_ddc_dce80_addr addr;
-+};
-+
-+struct hw_gpio_pin *dal_hw_ddc_dce80_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#define DDC_DCE80_FROM_BASE(ddc_base) \
-+	container_of(HW_DDC_FROM_BASE(ddc_base), struct hw_ddc_dce80, base)
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c
-new file mode 100644
-index 0000000..d1ea56d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c
-@@ -0,0 +1,78 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_factory_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_gpio_pad.h"
-+#include "../hw_ddc.h"
-+#include "hw_ddc_dce80.h"
-+#include "../hw_hpd.h"
-+#include "hw_hpd_dce80.h"
-+
-+/*
-+ * This unit
-+ */
-+static const struct hw_factory_funcs funcs = {
-+	.create_ddc_data = dal_hw_ddc_dce80_create,
-+	.create_ddc_clock = dal_hw_ddc_dce80_create,
-+	.create_generic = NULL,
-+	.create_hpd = dal_hw_hpd_dce80_create,
-+	.create_gpio_pad = NULL,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+};
-+
-+void dal_hw_factory_dce80_init(
-+	struct hw_factory *factory)
-+{
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.h
-new file mode 100644
-index 0000000..e78a8b3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DCE80_H__
-+#define __DAL_HW_FACTORY_DCE80_H__
-+
-+void dal_hw_factory_dce80_init(
-+	struct hw_factory *factory);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c
-new file mode 100644
-index 0000000..67b249b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c
-@@ -0,0 +1,378 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/gpio_types.h"
-+#include "../hw_gpio_pin.h"
-+#include "../hw_gpio.h"
-+#include "../hw_hpd.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_hpd_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_HW_HPD(ptr) \
-+	container_of((ptr), struct hw_hpd_dce80, base)
-+
-+#define FROM_HW_GPIO(ptr) \
-+	FROM_HW_HPD(container_of((ptr), struct hw_hpd, base))
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	FROM_HW_GPIO(container_of((ptr), struct hw_gpio, base))
-+
-+static void destruct(
-+	struct hw_hpd_dce80 *pin)
-+{
-+	dal_hw_hpd_destruct(&pin->base);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_hpd_dce80 *pin = FROM_HW_GPIO_PIN(*ptr);
-+
-+	destruct(pin);
-+
-+	dm_free((*ptr)->ctx, pin);
-+
-+	*ptr = NULL;
-+}
-+
-+static enum gpio_result get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	struct hw_hpd_dce80 *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	/* in Interrupt mode we ask for SENSE bit */
-+
-+	if (ptr->mode == GPIO_MODE_INTERRUPT) {
-+		uint32_t regval;
-+		uint32_t hpd_delayed = 0;
-+		uint32_t hpd_sense = 0;
-+
-+		regval = dm_read_reg(
-+				ptr->ctx,
-+				pin->addr.DC_HPD_INT_STATUS);
-+
-+		hpd_delayed = get_reg_field_value(
-+				regval,
-+				DC_HPD1_INT_STATUS,
-+				DC_HPD1_SENSE_DELAYED);
-+
-+		hpd_sense = get_reg_field_value(
-+				regval,
-+				DC_HPD1_INT_STATUS,
-+				DC_HPD1_SENSE);
-+
-+		*value = hpd_delayed;
-+		return GPIO_RESULT_OK;
-+	}
-+
-+	/* in any other modes, operate as normal GPIO */
-+
-+	return dal_hw_gpio_get_value(ptr, value);
-+}
-+
-+static enum gpio_result set_config(
-+	struct hw_gpio_pin *ptr,
-+	const struct gpio_config_data *config_data)
-+{
-+	struct hw_hpd_dce80 *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	if (!config_data)
-+		return GPIO_RESULT_INVALID_DATA;
-+
-+	{
-+		uint32_t value;
-+
-+		value = dm_read_reg(
-+			ptr->ctx,
-+			pin->addr.DC_HPD_TOGGLE_FILT_CNTL);
-+
-+		set_reg_field_value(
-+			value,
-+			config_data->config.hpd.delay_on_connect / 10,
-+			DC_HPD1_TOGGLE_FILT_CNTL,
-+			DC_HPD1_CONNECT_INT_DELAY);
-+
-+		set_reg_field_value(
-+			value,
-+			config_data->config.hpd.delay_on_disconnect / 10,
-+			DC_HPD1_TOGGLE_FILT_CNTL,
-+			DC_HPD1_DISCONNECT_INT_DELAY);
-+
-+		dm_write_reg(
-+			ptr->ctx,
-+			pin->addr.DC_HPD_TOGGLE_FILT_CNTL,
-+			value);
-+
-+	}
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+struct hw_gpio_generic_dce80_init {
-+	struct hw_gpio_pin_reg hw_gpio_data_reg;
-+	struct hw_hpd_dce80_addr addr;
-+};
-+
-+static const struct hw_gpio_generic_dce80_init
-+	hw_gpio_generic_dce80_init[GPIO_HPD_COUNT] = {
-+	/* GPIO_HPD_1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK
-+			}
-+		},
-+		{
-+			mmDC_HPD1_INT_STATUS,
-+			mmDC_HPD1_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_2 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK
-+			}
-+		},
-+		{
-+			mmDC_HPD2_INT_STATUS,
-+			mmDC_HPD2_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_3 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK
-+			}
-+		},
-+		{
-+			mmDC_HPD3_INT_STATUS,
-+			mmDC_HPD3_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_4 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK
-+			}
-+		},
-+		{
-+			mmDC_HPD4_INT_STATUS,
-+			mmDC_HPD4_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_5 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK
-+			}
-+		},
-+		{
-+			mmDC_HPD5_INT_STATUS,
-+			mmDC_HPD5_TOGGLE_FILT_CNTL
-+		}
-+	},
-+	/* GPIO_HPD_1 */
-+	{
-+		{
-+			{
-+				mmDC_GPIO_HPD_MASK,
-+				DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_A,
-+				DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_EN,
-+				DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK
-+			},
-+			{
-+				mmDC_GPIO_HPD_Y,
-+				DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK
-+			}
-+		},
-+		{
-+			mmDC_HPD6_INT_STATUS,
-+			mmDC_HPD6_TOGGLE_FILT_CNTL
-+		}
-+	}
-+};
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = dal_hw_gpio_open,
-+	.get_value = get_value,
-+	.set_value = dal_hw_gpio_set_value,
-+	.set_config = set_config,
-+	.change_mode = dal_hw_gpio_change_mode,
-+	.close = dal_hw_gpio_close,
-+};
-+
-+static bool construct(
-+	struct hw_hpd_dce80 *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	const struct hw_gpio_generic_dce80_init *init;
-+
-+	if (id != GPIO_ID_HPD) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!dal_hw_hpd_construct(&pin->base, id, en, ctx)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	pin->base.base.base.funcs = &funcs;
-+
-+	init = hw_gpio_generic_dce80_init + en;
-+
-+	pin->base.base.pin_reg = init->hw_gpio_data_reg;
-+
-+	pin->addr = init->addr;
-+
-+	return true;
-+}
-+
-+struct hw_gpio_pin *dal_hw_hpd_dce80_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_hpd_dce80 *pin = dm_alloc(ctx, sizeof(struct hw_hpd_dce80));
-+
-+	if (!pin) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(pin, id, en, ctx))
-+		return &pin->base.base.base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(ctx, pin);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.h
-new file mode 100644
-index 0000000..d74dbec
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.h
-@@ -0,0 +1,44 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_HPD_DCE80_H__
-+#define __DAL_HW_HPD_DCE80_H__
-+
-+struct hw_hpd_dce80_addr {
-+	uint32_t DC_HPD_INT_STATUS;
-+	uint32_t DC_HPD_TOGGLE_FILT_CNTL;
-+};
-+
-+struct hw_hpd_dce80 {
-+	struct hw_hpd base;
-+	struct hw_hpd_dce80_addr addr;
-+};
-+
-+struct hw_gpio_pin *dal_hw_hpd_dce80_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.c
-new file mode 100644
-index 0000000..9788106
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.c
-@@ -0,0 +1,424 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/gpio_types.h"
-+#include "../hw_translate.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_translate_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#include "../hw_gpio_pin.h"
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+#include "smu/smu_7_0_1_d.h"
-+
-+/*
-+ * @brief
-+ * Returns index of first bit (starting with LSB) which is set
-+ */
-+static uint32_t index_from_vector(
-+	uint32_t vector)
-+{
-+	uint32_t result = 0;
-+	uint32_t mask = 1;
-+
-+	do {
-+		if (vector == mask)
-+			return result;
-+
-+		++result;
-+		mask <<= 1;
-+	} while (mask);
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	return GPIO_ENUM_UNKNOWN;
-+}
-+
-+static bool offset_to_id(
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_id *id,
-+	uint32_t *en)
-+{
-+	switch (offset) {
-+	/* GENERIC */
-+	case mmDC_GPIO_GENERIC_A:
-+		*id = GPIO_ID_GENERIC;
-+		switch (mask) {
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
-+			*en = GPIO_GENERIC_A;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
-+			*en = GPIO_GENERIC_B;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
-+			*en = GPIO_GENERIC_C;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
-+			*en = GPIO_GENERIC_D;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
-+			*en = GPIO_GENERIC_E;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
-+			*en = GPIO_GENERIC_F;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
-+			*en = GPIO_GENERIC_G;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* HPD */
-+	case mmDC_GPIO_HPD_A:
-+		*id = GPIO_ID_HPD;
-+		switch (mask) {
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
-+			*en = GPIO_HPD_1;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
-+			*en = GPIO_HPD_2;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
-+			*en = GPIO_HPD_3;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
-+			*en = GPIO_HPD_4;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
-+			*en = GPIO_HPD_5;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
-+			*en = GPIO_HPD_6;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* SYNCA */
-+	case mmDC_GPIO_SYNCA_A:
-+		*id = GPIO_ID_SYNC;
-+		switch (mask) {
-+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
-+			*en = GPIO_SYNC_HSYNC_A;
-+			return true;
-+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
-+			*en = GPIO_SYNC_VSYNC_A;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* mmDC_GPIO_GENLK_MASK */
-+	case mmDC_GPIO_GENLK_A:
-+		*id = GPIO_ID_GSL;
-+		switch (mask) {
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_CLOCK;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_VSYNC;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_A;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_B;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* GPIOPAD */
-+	case mmGPIOPAD_A:
-+		*id = GPIO_ID_GPIO_PAD;
-+		*en = index_from_vector(mask);
-+		return (*en <= GPIO_GPIO_PAD_MAX);
-+	/* DDC */
-+	/* we don't care about the GPIO_ID for DDC
-+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-+	 * directly in the create method */
-+	case mmDC_GPIO_DDC1_A:
-+		*en = GPIO_DDC_LINE_DDC1;
-+		return true;
-+	case mmDC_GPIO_DDC2_A:
-+		*en = GPIO_DDC_LINE_DDC2;
-+		return true;
-+	case mmDC_GPIO_DDC3_A:
-+		*en = GPIO_DDC_LINE_DDC3;
-+		return true;
-+	case mmDC_GPIO_DDC4_A:
-+		*en = GPIO_DDC_LINE_DDC4;
-+		return true;
-+	case mmDC_GPIO_DDC5_A:
-+		*en = GPIO_DDC_LINE_DDC5;
-+		return true;
-+	case mmDC_GPIO_DDC6_A:
-+		*en = GPIO_DDC_LINE_DDC6;
-+		return true;
-+	case mmDC_GPIO_DDCVGA_A:
-+		*en = GPIO_DDC_LINE_DDC_VGA;
-+		return true;
-+	/* GPIO_I2CPAD */
-+	case mmDC_GPIO_I2CPAD_A:
-+		*en = GPIO_DDC_LINE_I2C_PAD;
-+		return true;
-+	/* Not implemented */
-+	case mmDC_GPIO_PWRSEQ_A:
-+	case mmDC_GPIO_PAD_STRENGTH_1:
-+	case mmDC_GPIO_PAD_STRENGTH_2:
-+	case mmDC_GPIO_DEBUG:
-+		return false;
-+	/* UNEXPECTED */
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+static bool id_to_offset(
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct gpio_pin_info *info)
-+{
-+	bool result = true;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GENERIC:
-+		info->offset = mmDC_GPIO_GENERIC_A;
-+		switch (en) {
-+		case GPIO_GENERIC_A:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
-+		break;
-+		case GPIO_GENERIC_B:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
-+		break;
-+		case GPIO_GENERIC_C:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
-+		break;
-+		case GPIO_GENERIC_D:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
-+		break;
-+		case GPIO_GENERIC_E:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
-+		break;
-+		case GPIO_GENERIC_F:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
-+		break;
-+		case GPIO_GENERIC_G:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		info->offset = mmDC_GPIO_HPD_A;
-+		switch (en) {
-+		case GPIO_HPD_1:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
-+		break;
-+		case GPIO_HPD_2:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
-+		break;
-+		case GPIO_HPD_3:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
-+		break;
-+		case GPIO_HPD_4:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
-+		break;
-+		case GPIO_HPD_5:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
-+		break;
-+		case GPIO_HPD_6:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_VSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_HSYNC_B:
-+		case GPIO_SYNC_VSYNC_B:
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
-+		break;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask =
-+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GPIO_PAD:
-+		info->offset = mmGPIOPAD_A;
-+		info->mask = (1 << en);
-+		result = (info->mask <= GPIO_GPIO_PAD_MAX);
-+	break;
-+	case GPIO_ID_VIP_PAD:
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		result = false;
-+	}
-+
-+	if (result) {
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask_y = info->mask;
-+		info->mask_en = info->mask;
-+		info->mask_mask = info->mask;
-+	}
-+
-+	return result;
-+}
-+
-+static const struct hw_translate_funcs funcs = {
-+		.offset_to_id = offset_to_id,
-+		.id_to_offset = id_to_offset,
-+};
-+
-+void dal_hw_translate_dce80_init(
-+	struct hw_translate *translate)
-+{
-+	translate->funcs = &funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.h
-new file mode 100644
-index 0000000..374f2f3
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_translate_dce80.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DCE80_H__
-+#define __DAL_HW_TRANSLATE_DCE80_H__
-+
-+void dal_hw_translate_dce80_init(
-+	struct hw_translate *tr);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index e0f6ecf..9c8ff54 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -40,6 +40,10 @@
-  * Post-requisites: headers required by this unit
-  */
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/hw_factory_dce80.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/hw_factory_dce110.h"
- #endif
-@@ -61,6 +65,11 @@ bool dal_hw_factory_init(
- 	}
- 
- 	switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		dal_hw_factory_dce80_init(factory);
-+		return true;
-+#endif
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index 215322e..d3c6bc8 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -40,6 +40,10 @@
-  * Post-requisites: headers required by this unit
-  */
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/hw_translate_dce80.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/hw_translate_dce110.h"
- #endif
-@@ -61,7 +65,11 @@ bool dal_hw_translate_init(
- 	}
- 
- 	switch (dce_version) {
--
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		dal_hw_translate_dce80_init(translate);
-+		return true;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-index b481a6d..cb23508 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-@@ -9,6 +9,18 @@ AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
- 
- AMD_DAL_FILES += $(AMD_DAL_GPU)
- 
-+###############################################################################
-+# DCE 80 family
-+###############################################################################
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+GPU_DCE80 = display_clock_dce80.o dc_clock_gating_dce80.o
-+
-+AMD_DAL_GPU_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpu/dce80/,$(GPU_DCE80))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPU_DCE80)
-+endif
-+
- 
- ###############################################################################
- # DCE 110 family
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
-new file mode 100644
-index 0000000..5f57577
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
-@@ -0,0 +1,52 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc_clock_gating_dce80.h"
-+
-+static void enable_hw_base_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+static void disable_sw_manual_control_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+static void enable_sw_manual_control_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+void dal_dc_clock_gating_dce80_power_up(struct dc_context *ctx, bool enable)
-+{
-+	if (enable) {
-+		enable_hw_base_light_sleep();
-+		disable_sw_manual_control_light_sleep();
-+	} else {
-+		enable_sw_manual_control_light_sleep();
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
-new file mode 100644
-index 0000000..f4111c5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
-@@ -0,0 +1,31 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DC_CLOCK_GATING_DCE80_H__
-+#define __DAL_DC_CLOCK_GATING_DCE80_H__
-+
-+void dal_dc_clock_gating_dce80_power_up(struct dc_context *ctx, bool enable);
-+
-+#endif /* __DAL_DC_CLOCK_GATING_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-new file mode 100644
-index 0000000..760705f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-@@ -0,0 +1,925 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/fixed32_32.h"
-+#include "include/logger_interface.h"
-+
-+#include "../divider_range.h"
-+#include "display_clock_dce80.h"
-+
-+#define DCE80_DFS_BYPASS_THRESHOLD_KHZ 100000
-+
-+/* Max clock values for each state indexed by "enum clocks_state": */
-+static struct state_dependent_clocks max_clks_by_state[] = {
-+/* ClocksStateInvalid - should not be used */
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/* ClocksStateLow */
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-+/* ClocksStateNominal */
-+{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-+/* ClocksStatePerformance */
-+{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-+
-+
-+/* Starting point for each divider range.*/
-+enum divider_range_start {
-+	DIVIDER_RANGE_01_START = 200, /* 2.00*/
-+	DIVIDER_RANGE_02_START = 1600, /* 16.00*/
-+	DIVIDER_RANGE_03_START = 3200, /* 32.00*/
-+	DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
-+};
-+
-+/* Ranges for divider identifiers (Divider ID or DID)
-+ mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
-+enum divider_id_register_setting {
-+	DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
-+	DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
-+	DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
-+	DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
-+};
-+
-+/* Step size between each divider within a range.
-+ Incrementing the DENTIST_DISPCLK_WDIVIDER by one
-+ will increment the divider by this much.*/
-+enum divider_range_step_size {
-+	DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
-+	DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
-+	DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
-+};
-+
-+/* Array identifiers and count for the divider ranges.*/
-+enum divider_range_count {
-+	DIVIDER_RANGE_01 = 0,
-+	DIVIDER_RANGE_02,
-+	DIVIDER_RANGE_03,
-+	DIVIDER_RANGE_MAX /* == 3*/
-+};
-+
-+static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
-+
-+#define FROM_DISPLAY_CLOCK(base) \
-+	container_of(base, struct display_clock_dce80, disp_clk)
-+
-+static struct fixed32_32 get_deep_color_factor(struct min_clock_params *params)
-+{
-+	/* DeepColorFactor = IF (HDMI = True, bpp / 24, 1)*/
-+	struct fixed32_32 deep_color_factor = dal_fixed32_32_from_int(1);
-+
-+	if (params->signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return deep_color_factor;
-+
-+	switch (params->deep_color_depth) {
-+	case COLOR_DEPTH_101010:
-+		/*deep color ratio for 30bpp is 30/24 = 1.25*/
-+		deep_color_factor = dal_fixed32_32_from_fraction(30, 24);
-+		break;
-+
-+	case COLOR_DEPTH_121212:
-+		/* deep color ratio for 36bpp is 36/24 = 1.5*/
-+		deep_color_factor = dal_fixed32_32_from_fraction(36, 24);
-+		break;
-+
-+	case COLOR_DEPTH_161616:
-+		/* deep color ratio for 48bpp is 48/24 = 2.0 */
-+		deep_color_factor = dal_fixed32_32_from_fraction(48, 24);
-+		break;
-+	default:
-+		break;
-+	}
-+	return deep_color_factor;
-+}
-+
-+static uint32_t get_scaler_efficiency(struct min_clock_params *params)
-+{
-+	uint32_t scaler_efficiency = 3;
-+
-+	switch (params->scaler_efficiency) {
-+	case V_SCALER_EFFICIENCY_LB18BPP:
-+	case V_SCALER_EFFICIENCY_LB24BPP:
-+		scaler_efficiency = 4;
-+		break;
-+
-+	case V_SCALER_EFFICIENCY_LB30BPP:
-+	case V_SCALER_EFFICIENCY_LB36BPP:
-+		scaler_efficiency = 3;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return scaler_efficiency;
-+}
-+
-+static uint32_t get_actual_required_display_clk(
-+	struct display_clock_dce80 *disp_clk,
-+	uint32_t  target_clk_khz)
-+{
-+	uint32_t disp_clk_khz = target_clk_khz;
-+	uint32_t div = INVALID_DIVIDER;
-+	uint32_t did = INVALID_DID;
-+	uint32_t scaled_vco =
-+		disp_clk->dentist_vco_freq_khz * DIVIDER_RANGE_SCALE_FACTOR;
-+
-+	ASSERT(disp_clk_khz);
-+
-+	if (disp_clk_khz)
-+		div = scaled_vco / disp_clk_khz;
-+
-+	did = dal_divider_range_get_did(divider_ranges, DIVIDER_RANGE_MAX, div);
-+
-+	if (did != INVALID_DID) {
-+		div = dal_divider_range_get_divider(
-+			divider_ranges, DIVIDER_RANGE_MAX, did);
-+
-+		if ((div != INVALID_DIVIDER) &&
-+			(did > DIVIDER_RANGE_01_BASE_DIVIDER_ID))
-+			if (disp_clk_khz > (scaled_vco / div))
-+				div = dal_divider_range_get_divider(
-+					divider_ranges, DIVIDER_RANGE_MAX,
-+					did - 1);
-+
-+		if (div != INVALID_DIVIDER)
-+			disp_clk_khz = scaled_vco / div;
-+
-+	}
-+	/* We need to add 10KHz to this value because the accuracy in VBIOS is
-+	 in 10KHz units. So we need to always round the last digit up in order
-+	 to reach the next div level.*/
-+	return disp_clk_khz + 10;
-+}
-+
-+static uint32_t get_validation_clock(struct display_clock *dc)
-+{
-+	uint32_t clk = 0;
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	switch (disp_clk->max_clks_state) {
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		/*Currently not supported, it has 0 in table entry*/
-+	case CLOCKS_STATE_LOW:
-+		clk = max_clks_by_state[CLOCKS_STATE_LOW].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_NOMINAL:
-+		clk = max_clks_by_state[CLOCKS_STATE_NOMINAL].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_PERFORMANCE:
-+		clk = max_clks_by_state[CLOCKS_STATE_PERFORMANCE].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_INVALID:
-+	default:
-+		/*Invalid Clocks State*/
-+		BREAK_TO_DEBUGGER();
-+		/* just return the display engine clock for
-+		 * lowest supported state*/
-+		clk = max_clks_by_state[CLOCKS_STATE_LOW].
-+						display_clk_khz;
-+		break;
-+	}
-+	return clk;
-+}
-+
-+static uint32_t calc_single_display_min_clks(
-+	struct display_clock *base,
-+	struct min_clock_params *params,
-+	bool set_clk)
-+{
-+	struct fixed32_32 h_scale = dal_fixed32_32_from_int(1);
-+	struct fixed32_32 v_scale = dal_fixed32_32_from_int(1);
-+	uint32_t pix_clk_khz = params->requested_pixel_clock;
-+	uint32_t line_total = params->timing_info.h_total;
-+	uint32_t max_clk_khz = get_validation_clock(base);
-+	struct fixed32_32 deep_color_factor = get_deep_color_factor(params);
-+	uint32_t scaler_efficiency = get_scaler_efficiency(params);
-+	struct fixed32_32 v_filter_init;
-+	uint32_t v_filter_init_trunc;
-+	struct fixed32_32 v_filter_init_ceil;
-+	struct fixed32_32 src_lines_per_dst_line;
-+	uint32_t src_wdth_rnd_to_chunks;
-+	struct fixed32_32 scaling_coeff;
-+	struct fixed32_32 fx_disp_clk_khz;
-+	struct fixed32_32 fx_alt_disp_clk_khz;
-+	uint32_t disp_clk_khz;
-+	uint32_t alt_disp_clk_khz;
-+	struct display_clock_dce80 *dc = FROM_DISPLAY_CLOCK(base);
-+
-+
-+	if (0 != params->dest_view.height && 0 != params->dest_view.width) {
-+
-+		h_scale = dal_fixed32_32_from_fraction(
-+			params->source_view.width,
-+			params->dest_view.width);
-+		v_scale = dal_fixed32_32_from_fraction(
-+			params->source_view.height,
-+			params->dest_view.height);
-+	}
-+
-+	v_filter_init = dal_fixed32_32_from_fraction(
-+		params->scaling_info.v_taps, 2u);
-+	v_filter_init = dal_fixed32_32_add(v_filter_init,
-+		dal_fixed32_32_div_int(v_scale, 2));
-+	v_filter_init = dal_fixed32_32_add(v_filter_init,
-+		dal_fixed32_32_from_fraction(15, 10));
-+
-+
-+	v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
-+
-+	v_filter_init_ceil = dal_fixed32_32_from_fraction(
-+						v_filter_init_trunc, 2);
-+	v_filter_init_ceil = dal_fixed32_32_from_int(
-+		dal_fixed32_32_ceil(v_filter_init_ceil));
-+	v_filter_init_ceil = dal_fixed32_32_mul_int(v_filter_init_ceil, 2);
-+	v_filter_init_ceil = dal_fixed32_32_div_int(v_filter_init_ceil, 3);
-+	v_filter_init_ceil = dal_fixed32_32_from_int(
-+		dal_fixed32_32_ceil(v_filter_init_ceil));
-+
-+	src_lines_per_dst_line = dal_fixed32_32_max(
-+		dal_fixed32_32_from_int(dal_fixed32_32_ceil(v_scale)),
-+		v_filter_init_ceil);
-+
-+	src_wdth_rnd_to_chunks =
-+		((params->source_view.width - 1) / 128) * 128 + 256;
-+
-+	scaling_coeff = dal_fixed32_32_max(
-+		dal_fixed32_32_from_fraction(params->scaling_info.h_taps, 4),
-+		dal_fixed32_32_mul(
-+			dal_fixed32_32_from_fraction(
-+				params->scaling_info.v_taps,
-+				scaler_efficiency),
-+					h_scale));
-+
-+	scaling_coeff = dal_fixed32_32_max(scaling_coeff, h_scale);
-+
-+	fx_disp_clk_khz = dal_fixed32_32_mul(
-+		scaling_coeff, dal_fixed32_32_from_fraction(11, 10));
-+	if (0 != line_total) {
-+		struct fixed32_32 d_clk = dal_fixed32_32_mul_int(
-+			src_lines_per_dst_line, src_wdth_rnd_to_chunks);
-+		d_clk = dal_fixed32_32_div_int(d_clk, line_total);
-+		d_clk = dal_fixed32_32_mul(d_clk,
-+				dal_fixed32_32_from_fraction(11, 10));
-+		fx_disp_clk_khz = dal_fixed32_32_max(fx_disp_clk_khz, d_clk);
-+	}
-+
-+	fx_disp_clk_khz = dal_fixed32_32_max(fx_disp_clk_khz,
-+		dal_fixed32_32_mul(deep_color_factor,
-+		dal_fixed32_32_from_fraction(11, 10)));
-+
-+	fx_disp_clk_khz = dal_fixed32_32_mul_int(fx_disp_clk_khz, pix_clk_khz);
-+	fx_disp_clk_khz = dal_fixed32_32_mul(fx_disp_clk_khz,
-+		dal_fixed32_32_from_fraction(1005, 1000));
-+
-+	fx_alt_disp_clk_khz = scaling_coeff;
-+
-+	if (0 != line_total) {
-+		struct fixed32_32 d_clk = dal_fixed32_32_mul_int(
-+			src_lines_per_dst_line, src_wdth_rnd_to_chunks);
-+		d_clk = dal_fixed32_32_div_int(d_clk, line_total);
-+		d_clk = dal_fixed32_32_mul(d_clk,
-+			dal_fixed32_32_from_fraction(105, 100));
-+		fx_alt_disp_clk_khz = dal_fixed32_32_max(
-+			fx_alt_disp_clk_khz, d_clk);
-+	}
-+	fx_alt_disp_clk_khz = dal_fixed32_32_max(
-+		fx_alt_disp_clk_khz, fx_alt_disp_clk_khz);
-+
-+	fx_alt_disp_clk_khz = dal_fixed32_32_mul_int(
-+		fx_alt_disp_clk_khz, pix_clk_khz);
-+
-+	/* convert to integer*/
-+	disp_clk_khz = dal_fixed32_32_floor(fx_disp_clk_khz);
-+	alt_disp_clk_khz = dal_fixed32_32_floor(fx_alt_disp_clk_khz);
-+
-+	if (set_clk) { /* only compensate clock if we are going to set it.*/
-+		disp_clk_khz = get_actual_required_display_clk(
-+			dc, disp_clk_khz);
-+		alt_disp_clk_khz = get_actual_required_display_clk(
-+			dc, alt_disp_clk_khz);
-+	}
-+
-+	if ((disp_clk_khz > max_clk_khz) && (alt_disp_clk_khz <= max_clk_khz))
-+		disp_clk_khz = alt_disp_clk_khz;
-+
-+	return disp_clk_khz;
-+
-+}
-+
-+static uint32_t calc_cursor_bw_for_min_clks(struct min_clock_params *params)
-+{
-+
-+	struct fixed32_32 v_scale = dal_fixed32_32_from_int(1);
-+	struct fixed32_32 v_filter_ceiling;
-+	struct fixed32_32 src_lines_per_dst_line;
-+	struct fixed32_32 cursor_bw;
-+
-+
-+	/*  DCE8 Mode Support and Mode Set Architecture Specification Rev 1.3
-+	 6.3.3	Cursor data Throughput requirement on DISPCLK
-+	 The MCIF to DCP cursor data return throughput is one pixel per DISPCLK
-+	  shared among the display heads.
-+	 If (Total Cursor Bandwidth in pixels for All heads> DISPCLK)
-+	 The mode is not supported
-+	 Cursor Bandwidth in Pixels = Cursor Width *
-+	 (SourceLinesPerDestinationLine / Line Time)
-+	 Assuming that Cursor Width = 128
-+	 */
-+	/*In the hardware doc they mention an Interlace Factor
-+	  It is not used here because we have already used it when
-+	  calculating destination view*/
-+	if (0 != params->dest_view.height)
-+		v_scale = dal_fixed32_32_from_fraction(
-+			params->source_view.height,
-+			params->dest_view.height);
-+
-+	{
-+	/*Do: Vertical Filter Init = 0.5 + VTAPS/2 + VSR/2 * Interlace Factor*/
-+	/*Interlace Factor is included in verticalScaleRatio*/
-+	struct fixed32_32 v_filter = dal_fixed32_32_add(
-+		dal_fixed32_32_from_fraction(params->scaling_info.v_taps, 2),
-+		dal_fixed32_32_div_int(v_scale, 2));
-+	/*Do : Ceiling (Vertical Filter Init, 2)/3 )*/
-+	v_filter_ceiling = dal_fixed32_32_div_int(v_filter, 2);
-+	v_filter_ceiling = dal_fixed32_32_mul_int(
-+		dal_fixed32_32_from_int(dal_fixed32_32_ceil(v_filter_ceiling)),
-+							2);
-+	v_filter_ceiling = dal_fixed32_32_div_int(v_filter_ceiling, 3);
-+	}
-+	/*Do : MAX( CeilCeiling (VSR), Ceiling (Vertical Filter Init, 2)/3 )*/
-+	/*Do : SourceLinesPerDestinationLine =
-+	 * MAX( Ceiling (VSR), Ceiling (Vertical Filter Init, 2)/3 )*/
-+	src_lines_per_dst_line = dal_fixed32_32_max(v_scale, v_filter_ceiling);
-+
-+	if ((params->requested_pixel_clock != 0) &&
-+		(params->timing_info.h_total != 0)) {
-+		/* pixelClock is in units of KHz.  Calc lineTime in us*/
-+		struct fixed32_32 inv_line_time = dal_fixed32_32_from_fraction(
-+			params->requested_pixel_clock,
-+			params->timing_info.h_total);
-+		cursor_bw = dal_fixed32_32_mul(
-+			dal_fixed32_32_mul_int(inv_line_time, 128),
-+						src_lines_per_dst_line);
-+	}
-+
-+	/* convert to integer*/
-+	return dal_fixed32_32_floor(cursor_bw);
-+}
-+
-+static bool validate(
-+	struct display_clock *dc,
-+	struct min_clock_params *params)
-+{
-+	uint32_t max_clk_khz = get_validation_clock(dc);
-+	uint32_t req_clk_khz;
-+
-+	if (params == NULL)
-+		return false;
-+
-+	req_clk_khz = calc_single_display_min_clks(dc, params, false);
-+
-+	return (req_clk_khz <= max_clk_khz);
-+}
-+
-+static uint32_t calculate_min_clock(
-+	struct display_clock *dc,
-+	uint32_t path_num,
-+	struct min_clock_params *params)
-+{
-+	uint32_t i;
-+	uint32_t validation_clk_khz = get_validation_clock(dc);
-+	uint32_t min_clk_khz = validation_clk_khz;
-+	uint32_t max_clk_khz = 0;
-+	uint32_t total_cursor_bw = 0;
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+
-+	if (disp_clk->use_max_disp_clk)
-+		return min_clk_khz;
-+
-+	if (params != NULL) {
-+		uint32_t disp_clk_khz = 0;
-+
-+		for (i = 0; i < path_num; ++i) {
-+			disp_clk_khz = calc_single_display_min_clks(
-+				dc, params, true);
-+
-+			/* update the max required clock found*/
-+			if (disp_clk_khz > max_clk_khz)
-+				max_clk_khz = disp_clk_khz;
-+
-+			disp_clk_khz = calc_cursor_bw_for_min_clks(params);
-+
-+			total_cursor_bw += disp_clk_khz;
-+
-+			params++;
-+
-+		}
-+	}
-+
-+	max_clk_khz = (total_cursor_bw > max_clk_khz) ? total_cursor_bw :
-+								max_clk_khz;
-+
-+	min_clk_khz = max_clk_khz;
-+
-+	/*"Cursor data Throughput requirement on DISPCLK is now a factor,
-+	 *  need to change the code */
-+	ASSERT(total_cursor_bw < validation_clk_khz);
-+
-+	if (min_clk_khz > validation_clk_khz)
-+		min_clk_khz = validation_clk_khz;
-+	else if (min_clk_khz < dc->min_display_clk_threshold_khz)
-+		min_clk_khz = dc->min_display_clk_threshold_khz;
-+
-+	return min_clk_khz;
-+}
-+
-+static void set_clock(
-+	struct display_clock *dc,
-+	uint32_t requested_clk_khz)
-+{
-+	struct bp_pixel_clock_parameters pxl_clk_params;
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+	struct dc_bios *bp = dal_adapter_service_get_bios_parser(dc->as);
-+
-+	/* Prepare to program display clock*/
-+	dm_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-+
-+	pxl_clk_params.target_pixel_clock = requested_clk_khz;
-+	pxl_clk_params.pll_id = dc->id;
-+
-+	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-+
-+	if (disp_clk->dfs_bypass_enabled) {
-+
-+		/* Cache the fixed display clock*/
-+		disp_clk->dfs_bypass_disp_clk =
-+			pxl_clk_params.dfs_bypass_display_clock;
-+	}
-+
-+	/* from power down, we need mark the clock state as ClocksStateNominal
-+	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-+	if (requested_clk_khz == 0)
-+		disp_clk->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
-+}
-+
-+static uint32_t get_clock(struct display_clock *dc)
-+{
-+	uint32_t disp_clock = get_validation_clock(dc);
-+	uint32_t target_div = INVALID_DIVIDER;
-+	uint32_t addr = mmDENTIST_DISPCLK_CNTL;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	if (disp_clk->dfs_bypass_enabled && disp_clk->dfs_bypass_disp_clk)
-+		return disp_clk->dfs_bypass_disp_clk;
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
-+	 DID DENTIST_DISPCLK_WDIVIDER.*/
-+	value = dm_read_reg(dc->ctx, addr);
-+	field = get_reg_field_value(
-+			value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
-+
-+	/* Convert DENTIST_DISPCLK_WDIVIDER to actual divider*/
-+	target_div = dal_divider_range_get_divider(
-+		divider_ranges,
-+		DIVIDER_RANGE_MAX,
-+		field);
-+
-+	if (target_div != INVALID_DIVIDER)
-+		/* Calculate the current DFS clock in KHz.
-+		 Should be okay up to 42.9 THz before overflowing.*/
-+		disp_clock = (DIVIDER_RANGE_SCALE_FACTOR
-+			* disp_clk->dentist_vco_freq_khz) / target_div;
-+	return disp_clock;
-+}
-+
-+static void set_clock_state(
-+	struct display_clock *dc,
-+	struct display_clock_state clk_state)
-+{
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	disp_clk->clock_state = clk_state;
-+}
-+static struct display_clock_state get_clock_state(
-+	struct display_clock *dc)
-+{
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	return disp_clk->clock_state;
-+}
-+
-+static enum clocks_state get_min_clocks_state(struct display_clock *dc)
-+{
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	return disp_clk->cur_min_clks_state;
-+}
-+
-+static enum clocks_state get_required_clocks_state
-+	(struct display_clock *dc,
-+	struct state_dependent_clocks *req_clocks)
-+{
-+	int32_t i;
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+	enum clocks_state low_req_clk = disp_clk->max_clks_state;
-+
-+	if (!req_clocks) {
-+		/* NULL pointer*/
-+		BREAK_TO_DEBUGGER();
-+		return CLOCKS_STATE_INVALID;
-+	}
-+
-+	/* Iterate from highest supported to lowest valid state, and update
-+	 * lowest RequiredState with the lowest state that satisfies
-+	 * all required clocks
-+	 */
-+	for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
-+		if ((req_clocks->display_clk_khz <=
-+			max_clks_by_state[i].display_clk_khz) &&
-+			(req_clocks->pixel_clk_khz <=
-+				max_clks_by_state[i].pixel_clk_khz))
-+			low_req_clk = i;
-+	}
-+	return low_req_clk;
-+}
-+
-+static bool set_min_clocks_state(
-+	struct display_clock *dc,
-+	enum clocks_state clocks_state)
-+{
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	if (clocks_state > disp_clk->max_clks_state) {
-+		/*Requested state exceeds max supported state.*/
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	} else if (clocks_state == disp_clk->cur_min_clks_state) {
-+		/*if we're trying to set the same state, we can just return
-+		 * since nothing needs to be done*/
-+		return true;
-+	}
-+
-+	disp_clk->cur_min_clks_state = clocks_state;
-+
-+	return true;
-+}
-+
-+static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
-+{
-+	uint32_t dispclk_cntl_value;
-+	uint32_t dp_ref_clk_cntl_value;
-+	uint32_t dp_ref_clk_cntl_src_sel_value;
-+	uint32_t dp_ref_clk_khz = 600000;
-+	uint32_t target_div = INVALID_DIVIDER;
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	/* ASSERT DP Reference Clock source is from DFS*/
-+	dp_ref_clk_cntl_value = dm_read_reg(dc->ctx,
-+			mmDPREFCLK_CNTL);
-+
-+	dp_ref_clk_cntl_src_sel_value =
-+			get_reg_field_value(
-+				dp_ref_clk_cntl_value,
-+				DPREFCLK_CNTL, DPREFCLK_SRC_SEL);
-+
-+	ASSERT(dp_ref_clk_cntl_src_sel_value == 0);
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
-+	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
-+	dispclk_cntl_value = dm_read_reg(dc->ctx,
-+			mmDENTIST_DISPCLK_CNTL);
-+
-+	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
-+	target_div = dal_divider_range_get_divider(
-+		divider_ranges,
-+		DIVIDER_RANGE_MAX,
-+		get_reg_field_value(dispclk_cntl_value,
-+			DENTIST_DISPCLK_CNTL,
-+			DENTIST_DPREFCLK_WDIVIDER));
-+
-+
-+	if (target_div != INVALID_DIVIDER) {
-+		/* Calculate the current DFS clock, in kHz.*/
-+		dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
-+			* disp_clk->dentist_vco_freq_khz) / target_div;
-+	}
-+
-+	/* SW will adjust DP REF Clock average value for all purposes
-+	 * (DP DTO / DP Audio DTO and DP GTC)
-+	 if clock is spread for all cases:
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
-+	 calculations for DS_INCR/DS_MODULO (this is planned to be default case)
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
-+	 calculations (not planned to be used, but average clock should still
-+	 be valid)
-+	 -if SS enabled on DP Ref clock and HW de-spreading disabled
-+	 (should not be case with CIK) then SW should program all rates
-+	 generated according to average value (case as with previous ASICs)
-+	  */
-+	if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) {
-+		struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+					disp_clk->gpu_pll_ss_percentage,
-+					disp_clk->gpu_pll_ss_divider), 200);
-+		struct fixed32_32 adj_dp_ref_clk_khz;
-+
-+		ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
-+								ss_percentage);
-+		adj_dp_ref_clk_khz =
-+			dal_fixed32_32_mul_int(
-+				ss_percentage,
-+				dp_ref_clk_khz);
-+		dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
-+	}
-+
-+	return dp_ref_clk_khz;
-+}
-+
-+static void store_max_clocks_state(
-+	struct display_clock *dc,
-+	enum clocks_state max_clocks_state)
-+{
-+	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	switch (max_clocks_state) {
-+	case CLOCKS_STATE_LOW:
-+	case CLOCKS_STATE_NOMINAL:
-+	case CLOCKS_STATE_PERFORMANCE:
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		disp_clk->max_clks_state = max_clocks_state;
-+		break;
-+
-+	case CLOCKS_STATE_INVALID:
-+	default:
-+		/*Invalid Clocks State!*/
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+}
-+
-+static void display_clock_ss_construct(
-+	struct display_clock_dce80 *disp_clk,
-+	struct adapter_service *as)
-+{
-+	uint32_t ss_entry_num = dal_adapter_service_get_ss_info_num(as,
-+		AS_SIGNAL_TYPE_GPU_PLL);
-+
-+	/*Read SS Info from VBIOS SS Info table for DP Reference Clock spread.*/
-+	if (ss_entry_num > 0) {/* Should be only one entry */
-+		struct spread_spectrum_info ss_info;
-+		bool res;
-+
-+		dm_memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+		res = dal_adapter_service_get_ss_info(as,
-+			AS_SIGNAL_TYPE_GPU_PLL, 0, &ss_info);
-+
-+		/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS even if
-+		 * SS not enabled and in that case
-+		 * SSInfo.spreadSpectrumPercentage !=0 would be
-+		 * sign that SS is enabled*/
-+		if (res && ss_info.spread_spectrum_percentage != 0) {
-+			disp_clk->ss_on_gpu_pll = true;
-+			disp_clk->gpu_pll_ss_divider =
-+				ss_info.spread_percentage_divider;
-+			if (ss_info.type.CENTER_MODE == 0)
-+				/* Currently we need only SS
-+				 * percentage for down-spread*/
-+				disp_clk->gpu_pll_ss_percentage =
-+					ss_info.spread_spectrum_percentage;
-+		}
-+	}
-+}
-+
-+static bool display_clock_integrated_info_construct(
-+	struct display_clock_dce80 *disp_clk,
-+	struct adapter_service *as)
-+{
-+	struct integrated_info info;
-+	struct firmware_info fw_info;
-+	bool res;
-+	uint32_t i;
-+
-+	res = dal_adapter_service_get_integrated_info(as, &info);
-+
-+	disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
-+	if (disp_clk->dentist_vco_freq_khz == 0) {
-+		dal_adapter_service_get_firmware_info(as, &fw_info);
-+		disp_clk->dentist_vco_freq_khz =
-+			fw_info.smu_gpu_pll_output_freq;
-+		if (disp_clk->dentist_vco_freq_khz == 0)
-+			disp_clk->dentist_vco_freq_khz = 3600000;
-+		}
-+	disp_clk->disp_clk.min_display_clk_threshold_khz =
-+		disp_clk->dentist_vco_freq_khz / 64;
-+
-+	if (!res)
-+		return false;
-+
-+	/* TODO: initialise disp_clk->dfs_bypass_disp_clk */
-+
-+	/*update the maximum display clock for each power state*/
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
-+
-+		switch (i) {
-+		case 0:
-+			clk_state = CLOCKS_STATE_ULTRA_LOW;
-+			break;
-+
-+		case 1:
-+			clk_state = CLOCKS_STATE_LOW;
-+			break;
-+
-+		case 2:
-+			clk_state = CLOCKS_STATE_NOMINAL;
-+			break;
-+
-+		case 3:
-+			clk_state = CLOCKS_STATE_PERFORMANCE;
-+			break;
-+
-+		default:
-+			clk_state = CLOCKS_STATE_INVALID;
-+			break;
-+		}
-+
-+		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
-+		 * check for > 100MHz*/
-+		if (info.disp_clk_voltage[i].max_supported_clk >= 100000) {
-+			max_clks_by_state[clk_state].display_clk_khz =
-+				info.disp_clk_voltage[i].max_supported_clk;
-+		}
-+		/*invalid input from bios*/
-+		ASSERT(info.disp_clk_voltage[i].max_supported_clk >= 100000);
-+	}
-+	disp_clk->dfs_bypass_enabled =
-+		dal_adapter_service_is_dfs_bypass_enabled(as) &&
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_ENABLE_DFS_BYPASS);
-+
-+	disp_clk->use_max_disp_clk =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_USE_MAX_DISPLAY_CLK);
-+	return true;
-+}
-+
-+static uint32_t get_dfs_bypass_threshold(struct display_clock *dc)
-+{
-+	return DCE80_DFS_BYPASS_THRESHOLD_KHZ;
-+}
-+
-+static void destroy(struct display_clock **dc)
-+{
-+	struct display_clock_dce80 *disp_clk;
-+
-+	disp_clk = FROM_DISPLAY_CLOCK(*dc);
-+	dm_free((*dc)->ctx, disp_clk);
-+	*dc = NULL;
-+}
-+
-+static const struct display_clock_funcs funcs = {
-+	.calculate_min_clock = calculate_min_clock,
-+	.destroy = destroy,
-+	.get_clock = get_clock,
-+	.get_clock_state = get_clock_state,
-+	.get_dfs_bypass_threshold = get_dfs_bypass_threshold,
-+	.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
-+	.get_min_clocks_state = get_min_clocks_state,
-+	.get_required_clocks_state = get_required_clocks_state,
-+	.get_validation_clock = get_validation_clock,
-+	.set_clock = set_clock,
-+	.set_clock_state = set_clock_state,
-+	.set_dp_ref_clock_source =
-+		dal_display_clock_base_set_dp_ref_clock_source,
-+	.set_min_clocks_state = set_min_clocks_state,
-+	.store_max_clocks_state = store_max_clocks_state,
-+	.validate = validate,
-+};
-+
-+static bool display_clock_construct(
-+	struct dc_context *ctx,
-+	struct display_clock_dce80 *disp_clk,
-+	struct adapter_service *as)
-+{
-+	struct display_clock *dc_base = &disp_clk->disp_clk;
-+
-+	if (NULL == as)
-+		return false;
-+
-+	if (!dal_display_clock_construct_base(dc_base, ctx, as))
-+		return false;
-+
-+	dc_base->funcs = &funcs;
-+	/*
-+	 * set_dp_ref_clock_source
-+	 * set_clock_state
-+	 * get_clock_state
-+	 * get_dfs_bypass_threshold
-+	 */
-+
-+	disp_clk->gpu_pll_ss_percentage = 0;
-+	disp_clk->gpu_pll_ss_divider = 1000;
-+	disp_clk->ss_on_gpu_pll = false;
-+	disp_clk->dfs_bypass_enabled = false;
-+	disp_clk->dfs_bypass_disp_clk = 0;
-+	disp_clk->use_max_disp_clk = true;/* false will hang the system! */
-+
-+	disp_clk->disp_clk.id = CLOCK_SOURCE_ID_DFS;
-+/* Initially set max clocks state to nominal.  This should be updated by
-+ * via a pplib call to DAL IRI eventually calling a
-+ * DisplayEngineClock_Dce50::StoreMaxClocksState().  This call will come in
-+ * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-+	disp_clk->max_clks_state = CLOCKS_STATE_NOMINAL;
-+/* Initially set current min clocks state to invalid since we
-+ * cannot make any assumption about PPLIB's initial state. This will be updated
-+ * by HWSS via SetMinClocksState() on first mode set prior to programming
-+ * state dependent clocks.*/
-+	disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
-+
-+	display_clock_ss_construct(disp_clk, as);
-+
-+	if (!display_clock_integrated_info_construct(disp_clk, as)) {
-+		dal_logger_write(dc_base->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Cannot obtain VBIOS integrated info");
-+	}
-+
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_01],
-+		DIVIDER_RANGE_01_START,
-+		DIVIDER_RANGE_01_STEP_SIZE,
-+		DIVIDER_RANGE_01_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID);
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_02],
-+		DIVIDER_RANGE_02_START,
-+		DIVIDER_RANGE_02_STEP_SIZE,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID);
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_03],
-+		DIVIDER_RANGE_03_START,
-+		DIVIDER_RANGE_03_STEP_SIZE,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_MAX_DIVIDER_ID);
-+	return true;
-+}
-+
-+struct display_clock *dal_display_clock_dce80_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct display_clock_dce80 *disp_clk;
-+
-+	disp_clk = dm_alloc(ctx, sizeof(struct display_clock_dce80));
-+
-+	if (disp_clk == NULL)
-+		return NULL;
-+
-+	if (display_clock_construct(ctx, disp_clk, as))
-+		return &disp_clk->disp_clk;
-+
-+	dm_free(ctx, disp_clk);
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h
-new file mode 100644
-index 0000000..2d68704
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h
-@@ -0,0 +1,58 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DISPLAY_CLOCK_DCE80_H__
-+#define __DAL_DISPLAY_CLOCK_DCE80_H__
-+
-+#include "gpu/display_clock.h"
-+
-+struct display_clock_dce80 {
-+	struct display_clock disp_clk;
-+	/* DFS input - GPUPLL VCO frequency - from VBIOS Firmware info. */
-+	uint32_t dentist_vco_freq_khz;
-+	/* GPU PLL SS percentage (if down-spread enabled)*/
-+	uint32_t gpu_pll_ss_percentage;
-+	/* GPU PLL SS percentage Divider (100 or 1000)*/
-+	uint32_t gpu_pll_ss_divider;
-+	/* Flag for Enabled SS on GPU PLL*/
-+	bool ss_on_gpu_pll;
-+	/* Max display block clocks state*/
-+	enum clocks_state max_clks_state;
-+	/* Current minimum display block clocks state*/
-+	enum clocks_state cur_min_clks_state;
-+	/* DFS-bypass feature variable
-+	 Cache the status of DFS-bypass feature*/
-+	bool dfs_bypass_enabled;
-+	/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
-+	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
-+	uint32_t dfs_bypass_disp_clk;
-+	bool use_max_disp_clk;
-+	struct display_clock_state clock_state;
-+};
-+
-+struct display_clock *dal_display_clock_dce80_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as);
-+
-+#endif /* __DAL_DISPLAY_CLOCK_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-index 390d83d..fc76821 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile
-@@ -9,6 +9,17 @@ AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
- 
- AMD_DAL_FILES += $(AMD_DAL_I2CAUX)
- 
-+###############################################################################
-+# DCE 8x family
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DAL_DCE8_0
-+I2CAUX_DCE80 = i2caux_dce80.o i2c_hw_engine_dce80.o \
-+	i2c_sw_engine_dce80.o aux_engine_dce80.o
-+
-+AMD_DAL_I2CAUX_DCE80 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce80/,$(I2CAUX_DCE80))
-+
-+AMD_DAL_FILES += $(AMD_DAL_I2CAUX_DCE80)
-+endif
- 
- ###############################################################################
- # DCE 11x family
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-new file mode 100644
-index 0000000..a4fc2cd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-@@ -0,0 +1,740 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../aux_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "aux_engine_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct aux_engine *'
-+ * to 'struct aux_engine_dce80 *'
-+ */
-+#define FROM_AUX_ENGINE(ptr) \
-+	container_of((ptr), struct aux_engine_dce80, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct aux_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct aux_engine_dce80 *aux_engine = FROM_ENGINE(engine);
-+
-+	const uint32_t addr = aux_engine->addr.AUX_ARB_CONTROL;
-+
-+	uint32_t value = dm_read_reg(engine->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		AUX_ARB_CONTROL,
-+		AUX_SW_DONE_USING_AUX_REG);
-+
-+	dm_write_reg(engine->ctx, addr, value);
-+}
-+
-+static void destruct(
-+	struct aux_engine_dce80 *engine);
-+
-+static void destroy(
-+	struct aux_engine **aux_engine)
-+{
-+	struct aux_engine_dce80 *engine = FROM_AUX_ENGINE(*aux_engine);
-+
-+	destruct(engine);
-+
-+	dm_free((*aux_engine)->base.ctx, engine);
-+
-+	*aux_engine = NULL;
-+}
-+
-+#define SW_CAN_ACCESS_AUX 1
-+
-+static bool acquire_engine(
-+	struct aux_engine *engine)
-+{
-+	struct aux_engine_dce80 *aux_engine = FROM_AUX_ENGINE(engine);
-+	uint32_t value;
-+	uint32_t field;
-+
-+	/* enable AUX before request SW to access AUX */
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_CONTROL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		field = get_reg_field_value(
-+				value,
-+				AUX_CONTROL,
-+				AUX_EN);
-+
-+		if (field == 0) {
-+			set_reg_field_value(
-+				value,
-+				1,
-+				AUX_CONTROL,
-+				AUX_EN);
-+
-+			dm_write_reg(engine->base.ctx, addr, value);
-+		}
-+	}
-+
-+	/* request SW to access AUX */
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_ARB_CONTROL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_ARB_CONTROL,
-+			AUX_SW_USE_AUX_REG_REQ);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		field = get_reg_field_value(
-+				value,
-+				AUX_ARB_CONTROL,
-+				AUX_REG_RW_CNTL_STATUS);
-+
-+		return field == SW_CAN_ACCESS_AUX;
-+	}
-+}
-+
-+static void configure(
-+	struct aux_engine *engine,
-+	union aux_config cfg)
-+{
-+	struct aux_engine_dce80 *aux_engine = FROM_AUX_ENGINE(engine);
-+
-+	const uint32_t addr = aux_engine->addr.AUX_CONTROL;
-+
-+	uint32_t value = dm_read_reg(engine->base.ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		(0 != cfg.bits.ALLOW_AUX_WHEN_HPD_LOW),
-+		AUX_CONTROL,
-+		AUX_IGNORE_HPD_DISCON);
-+
-+	dm_write_reg(engine->base.ctx, addr, value);
-+}
-+
-+static bool start_gtc_sync(
-+	struct aux_engine *engine)
-+{
-+	/* TODO */
-+	return false;
-+}
-+
-+static void stop_gtc_sync(
-+	struct aux_engine *engine)
-+{
-+	/* TODO */
-+}
-+
-+#define COMPOSE_AUX_SW_DATA_16_20(command, address) \
-+	((command) | ((0xF0000 & (address)) >> 16))
-+
-+#define COMPOSE_AUX_SW_DATA_8_15(address) \
-+	((0xFF00 & (address)) >> 8)
-+
-+#define COMPOSE_AUX_SW_DATA_0_7(address) \
-+	(0xFF & (address))
-+
-+static void submit_channel_request(
-+	struct aux_engine *engine,
-+	struct aux_request_transaction_data *request)
-+{
-+	struct aux_engine_dce80 *aux_engine = FROM_AUX_ENGINE(engine);
-+	uint32_t value;
-+	uint32_t length;
-+
-+	bool is_write =
-+		((request->type == AUX_TRANSACTION_TYPE_DP) &&
-+		 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
-+		((request->type == AUX_TRANSACTION_TYPE_I2C) &&
-+		((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
-+
-+	/* clear_aux_error */
-+	{
-+		const uint32_t addr = mmAUXN_IMPCAL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXN_IMPCAL,
-+			AUXN_CALOUT_ERROR_AK);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXN_IMPCAL,
-+			AUXN_CALOUT_ERROR_AK);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+	{
-+		const uint32_t addr = mmAUXP_IMPCAL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXP_IMPCAL,
-+			AUXP_CALOUT_ERROR_AK);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXP_IMPCAL,
-+			AUXP_CALOUT_ERROR_AK);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	/* force_default_calibrate */
-+	{
-+		const uint32_t addr = mmAUXN_IMPCAL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXN_IMPCAL,
-+			AUXN_IMPCAL_ENABLE);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXN_IMPCAL,
-+			AUXN_IMPCAL_OVERRIDE_ENABLE);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+	{
-+		const uint32_t addr = mmAUXP_IMPCAL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUXP_IMPCAL,
-+			AUXP_IMPCAL_OVERRIDE_ENABLE);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUXP_IMPCAL,
-+			AUXP_IMPCAL_OVERRIDE_ENABLE);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	/* set the delay and the number of bytes to write */
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_SW_CONTROL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			request->delay,
-+			AUX_SW_CONTROL,
-+			AUX_SW_START_DELAY);
-+
-+		/* The length include
-+		 * the 4 bit header and the 20 bit address
-+		 * (that is 3 byte).
-+		 * If the requested length is non zero this means
-+		 * an addition byte specifying the length is required. */
-+
-+		length = request->length ? 4 : 3;
-+		if (is_write)
-+			length += request->length;
-+
-+		set_reg_field_value(
-+			value,
-+			length,
-+			AUX_SW_CONTROL,
-+			AUX_SW_WR_BYTES);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	/* program action and address and payload data (if 'is_write') */
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_SW_DATA;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_INDEX);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_DATA_RW);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_DATA,
-+			AUX_SW_AUTOINCREMENT_DISABLE);
-+
-+		set_reg_field_value(
-+			value,
-+			COMPOSE_AUX_SW_DATA_16_20(
-+				request->action, request->address),
-+			AUX_SW_DATA,
-+			AUX_SW_DATA);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_AUTOINCREMENT_DISABLE);
-+
-+		set_reg_field_value(
-+			value,
-+			COMPOSE_AUX_SW_DATA_8_15(request->address),
-+			AUX_SW_DATA,
-+			AUX_SW_DATA);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			COMPOSE_AUX_SW_DATA_0_7(request->address),
-+			AUX_SW_DATA,
-+			AUX_SW_DATA);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		if (request->length) {
-+			set_reg_field_value(
-+				value,
-+				request->length - 1,
-+				AUX_SW_DATA,
-+				AUX_SW_DATA);
-+
-+			dm_write_reg(engine->base.ctx, addr, value);
-+		}
-+
-+		if (is_write) {
-+			/* Load the HW buffer with the Data to be sent.
-+			 * This is relevant for write operation.
-+			 * For read, the data recived data will be
-+			 * processed in process_channel_reply(). */
-+			uint32_t i = 0;
-+
-+			while (i < request->length) {
-+
-+				set_reg_field_value(
-+					value,
-+					request->data[i],
-+					AUX_SW_DATA,
-+					AUX_SW_DATA);
-+
-+				dm_write_reg(
-+					engine->base.ctx, addr, value);
-+
-+				++i;
-+			}
-+		}
-+	}
-+
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_INTERRUPT_CONTROL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_INTERRUPT_CONTROL,
-+			AUX_SW_DONE_ACK);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_SW_CONTROL;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_CONTROL,
-+			AUX_SW_GO);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+	}
-+}
-+
-+static void process_channel_reply(
-+	struct aux_engine *engine,
-+	struct aux_reply_transaction_data *reply)
-+{
-+	struct aux_engine_dce80 *aux_engine = FROM_AUX_ENGINE(engine);
-+
-+	/* Need to do a read to get the number of bytes to process
-+	 * Alternatively, this information can be passed -
-+	 * but that causes coupling which isn't good either. */
-+
-+	uint32_t bytes_replied;
-+	uint32_t value;
-+
-+	{
-+		const uint32_t addr = aux_engine->addr.AUX_SW_STATUS;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		bytes_replied = get_reg_field_value(
-+				value,
-+				AUX_SW_STATUS,
-+				AUX_SW_REPLY_BYTE_COUNT);
-+	}
-+
-+	if (bytes_replied) {
-+		uint32_t reply_result;
-+
-+		const uint32_t addr = aux_engine->addr.AUX_SW_DATA;
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			AUX_SW_DATA,
-+			AUX_SW_INDEX);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_DATA,
-+			AUX_SW_AUTOINCREMENT_DISABLE);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AUX_SW_DATA,
-+			AUX_SW_DATA_RW);
-+
-+		dm_write_reg(engine->base.ctx, addr, value);
-+
-+		value = dm_read_reg(engine->base.ctx, addr);
-+
-+		reply_result = get_reg_field_value(
-+				value,
-+				AUX_SW_DATA,
-+				AUX_SW_DATA);
-+
-+		reply_result = reply_result >> 4;
-+
-+		switch (reply_result) {
-+		case 0: /* ACK */ {
-+			uint32_t i = 0;
-+
-+			/* first byte was already used
-+			 * to get the command status */
-+			--bytes_replied;
-+
-+			while (i < bytes_replied) {
-+				value = dm_read_reg(
-+					engine->base.ctx, addr);
-+
-+				reply->data[i] = get_reg_field_value(
-+						value,
-+						AUX_SW_DATA,
-+						AUX_SW_DATA);
-+
-+				++i;
-+			}
-+
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
-+		}
-+		break;
-+		case 1: /* NACK */
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
-+		break;
-+		case 2: /* DEFER */
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
-+		break;
-+		case 4: /* AUX ACK / I2C NACK */
-+			reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
-+		break;
-+		case 8: /* AUX ACK / I2C DEFER */
-+			reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
-+		break;
-+		default:
-+			reply->status = AUX_TRANSACTION_REPLY_INVALID;
-+		}
-+	} else {
-+		/* Need to handle an error case...
-+		 * hopefully, upper layer function won't call this function
-+		 * if the number of bytes in the reply was 0
-+		 * because there was surely an error that was asserted
-+		 * that should have been handled
-+		 * for hot plug case, this could happens*/
-+		if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-+			ASSERT_CRITICAL(false);
-+	}
-+}
-+
-+static enum aux_channel_operation_result get_channel_status(
-+	struct aux_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	struct aux_engine_dce80 *aux_engine = FROM_AUX_ENGINE(engine);
-+
-+	const uint32_t addr = aux_engine->addr.AUX_SW_STATUS;
-+
-+	uint32_t value;
-+	uint32_t aux_sw_done;
-+
-+	if (returned_bytes == NULL) {
-+		/*caller pass NULL pointer*/
-+		ASSERT_CRITICAL(false);
-+		return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN;
-+	}
-+	*returned_bytes = 0;
-+
-+	/* poll to make sure that SW_DONE is asserted */
-+	{
-+		uint32_t time_elapsed = 0;
-+
-+		do {
-+			value = dm_read_reg(engine->base.ctx, addr);
-+
-+			aux_sw_done = get_reg_field_value(
-+					value,
-+					AUX_SW_STATUS,
-+					AUX_SW_DONE);
-+
-+			if (aux_sw_done)
-+				break;
-+
-+			dm_delay_in_microseconds(engine->base.ctx, 10);
-+
-+			time_elapsed += 10;
-+		} while (time_elapsed < aux_engine->timeout_period);
-+
-+
-+	}
-+
-+	/* Note that the following bits are set in 'status.bits'
-+	 * during CTS 4.2.1.2:
-+	 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
-+	 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
-+	 *
-+	 * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
-+	 * HW debugging bit and should be ignored. */
-+	if (aux_sw_done) {
-+		if (get_reg_field_value(
-+			value,
-+			AUX_SW_STATUS,
-+			AUX_SW_RX_TIMEOUT_STATE) ||
-+			get_reg_field_value(
-+				value,
-+				AUX_SW_STATUS,
-+				AUX_SW_RX_TIMEOUT))
-+			return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-+		else if (get_reg_field_value(
-+			value,
-+			AUX_SW_STATUS,
-+			AUX_SW_RX_INVALID_STOP))
-+			return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-+
-+		*returned_bytes = get_reg_field_value(
-+				value,
-+				AUX_SW_STATUS,
-+				AUX_SW_REPLY_BYTE_COUNT);
-+		if (*returned_bytes == 0)
-+			return
-+			AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-+		else {
-+			*returned_bytes -= 1;
-+			return AUX_CHANNEL_OPERATION_SUCCEEDED;
-+		}
-+	} else {
-+		/*time_elapsed >= aux_engine->timeout_period */
-+		if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-+			ASSERT_CRITICAL(false);
-+		return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-+	}
-+}
-+
-+static const int32_t aux_channel_offset[] = {
-+	mmDP_AUX0_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX1_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX2_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX3_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX4_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL,
-+	mmDP_AUX5_AUX_CONTROL - mmDP_AUX0_AUX_CONTROL
-+};
-+
-+static const struct aux_engine_funcs aux_engine_funcs = {
-+	.destroy = destroy,
-+	.acquire_engine = acquire_engine,
-+	.configure = configure,
-+	.start_gtc_sync = start_gtc_sync,
-+	.stop_gtc_sync = stop_gtc_sync,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.submit_request = dal_aux_engine_submit_request,
-+	.keep_power_up_count = dal_i2caux_keep_power_up_count,
-+	.get_engine_type = dal_aux_engine_get_engine_type,
-+	.acquire = dal_aux_engine_acquire,
-+};
-+
-+static bool construct(
-+	struct aux_engine_dce80 *engine,
-+	const struct aux_engine_dce80_create_arg *arg)
-+{
-+	int32_t offset;
-+
-+	if (arg->engine_id >= sizeof(aux_channel_offset) / sizeof(int32_t)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!dal_aux_engine_construct(&engine->base, arg->ctx)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+	engine->base.base.funcs = &engine_funcs;
-+	engine->base.funcs = &aux_engine_funcs;
-+	offset = aux_channel_offset[arg->engine_id];
-+	engine->addr.AUX_CONTROL = mmAUX_CONTROL + offset;
-+	engine->addr.AUX_ARB_CONTROL = mmAUX_ARB_CONTROL + offset;
-+	engine->addr.AUX_SW_DATA = mmAUX_SW_DATA + offset;
-+	engine->addr.AUX_SW_CONTROL = mmAUX_SW_CONTROL + offset;
-+	engine->addr.AUX_INTERRUPT_CONTROL = mmAUX_INTERRUPT_CONTROL + offset;
-+	engine->addr.AUX_SW_STATUS = mmAUX_SW_STATUS + offset;
-+	engine->addr.AUX_GTC_SYNC_CONTROL = mmAUX_GTC_SYNC_CONTROL + offset;
-+	engine->addr.AUX_GTC_SYNC_STATUS = mmAUX_GTC_SYNC_STATUS + offset;
-+	engine->addr.AUX_GTC_SYNC_CONTROLLER_STATUS =
-+		mmAUX_GTC_SYNC_CONTROLLER_STATUS + offset;
-+
-+	engine->timeout_period = arg->timeout_period;
-+
-+	return true;
-+}
-+
-+static void destruct(
-+	struct aux_engine_dce80 *engine)
-+{
-+	dal_aux_engine_destruct(&engine->base);
-+}
-+
-+struct aux_engine *dal_aux_engine_dce80_create(
-+	const struct aux_engine_dce80_create_arg *arg)
-+{
-+	struct aux_engine_dce80 *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = dm_alloc(arg->ctx, sizeof(struct aux_engine_dce80));
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(engine, arg))
-+		return &engine->base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(arg->ctx, engine);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.h
-new file mode 100644
-index 0000000..8523c45
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.h
-@@ -0,0 +1,54 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUX_ENGINE_DCE80_H__
-+#define __DAL_AUX_ENGINE_DCE80_H__
-+
-+struct aux_engine_dce80 {
-+	struct aux_engine base;
-+	struct {
-+		uint32_t AUX_CONTROL;
-+		uint32_t AUX_ARB_CONTROL;
-+		uint32_t AUX_SW_DATA;
-+		uint32_t AUX_SW_CONTROL;
-+		uint32_t AUX_INTERRUPT_CONTROL;
-+		uint32_t AUX_SW_STATUS;
-+		uint32_t AUX_GTC_SYNC_CONTROL;
-+		uint32_t AUX_GTC_SYNC_STATUS;
-+		uint32_t AUX_GTC_SYNC_CONTROLLER_STATUS;
-+	} addr;
-+	uint32_t timeout_period;
-+};
-+
-+struct aux_engine_dce80_create_arg {
-+	uint32_t engine_id;
-+	uint32_t timeout_period;
-+	struct dc_context *ctx;
-+};
-+
-+struct aux_engine *dal_aux_engine_dce80_create(
-+	const struct aux_engine_dce80_create_arg *arg);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-new file mode 100644
-index 0000000..3d61963
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-@@ -0,0 +1,901 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_hw_engine.h"
-+#include "../i2c_generic_hw_engine.h"
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_hw_engine_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+/*
-+ * This unit
-+ */
-+
-+enum dc_i2c_status {
-+	DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-+};
-+
-+enum dc_i2c_arbitration {
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-+};
-+
-+enum {
-+	/* No timeout in HW
-+	 * (timeout implemented in SW by querying status) */
-+	I2C_SETUP_TIME_LIMIT = 255,
-+	I2C_HW_BUFFER_SIZE = 144
-+};
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_hw_engine *'
-+ * to 'struct i2c_hw_engine_dce80 *'
-+ */
-+#define FROM_I2C_HW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_hw_engine_dce80, base)
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct i2c_engine *'
-+ * to pointer to 'struct i2c_hw_engine_dce80 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct engine *'
-+ * to 'pointer to struct i2c_hw_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+static void disable_i2c_hw_engine(
-+	struct i2c_hw_engine_dce80 *engine)
-+{
-+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+	uint32_t value = 0;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_ENABLE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_engine *base = NULL;
-+	bool safe_to_reset;
-+	uint32_t value = 0;
-+
-+	base = &hw_engine->base.base;
-+
-+	/* Restore original HW engine speed */
-+
-+	base->funcs->set_speed(base, hw_engine->base.original_speed);
-+
-+	/* Release I2C */
-+	{
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
-+
-+		set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_ARBITRATION,
-+				DC_I2C_SW_DONE_USING_I2C_REG);
-+
-+		dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
-+	}
-+
-+	/* Reset HW engine */
-+	{
-+		uint32_t i2c_sw_status = 0;
-+
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+		i2c_sw_status = get_reg_field_value(
-+				value,
-+				DC_I2C_SW_STATUS,
-+				DC_I2C_SW_STATUS);
-+		/* if used by SW, safe to reset */
-+		safe_to_reset = (i2c_sw_status == 1);
-+	}
-+	{
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+
-+		if (safe_to_reset)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_CONTROL,
-+				DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+	}
-+
-+	/* HW I2c engine - clock gating feature */
-+	if (!hw_engine->engine_keep_power_up_count)
-+		disable_i2c_hw_engine(hw_engine);
-+}
-+
-+static void keep_power_up_count(
-+	struct engine *engine,
-+	bool keep_power_up)
-+{
-+	struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
-+
-+	if (keep_power_up)
-+		++hw_engine->engine_keep_power_up_count;
-+	else {
-+		--hw_engine->engine_keep_power_up_count;
-+
-+		if (!hw_engine->engine_keep_power_up_count)
-+			disable_i2c_hw_engine(hw_engine);
-+	}
-+}
-+
-+static void destruct(
-+	struct i2c_hw_engine_dce80 *engine)
-+{
-+	dal_i2c_hw_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **i2c_engine)
-+{
-+	struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(*i2c_engine);
-+
-+	destruct(engine);
-+
-+	dm_free((*i2c_engine)->base.ctx, engine);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static bool setup_engine(
-+	struct i2c_engine *i2c_engine)
-+{
-+	uint32_t value = 0;
-+	struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	/* Program pin select */
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SEND_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_TRANSACTION_COUNT);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->engine_id,
-+			DC_I2C_CONTROL,
-+			DC_I2C_DDC_SELECT);
-+
-+
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+
-+	/* Program time limit */
-+	{
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+
-+		value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			I2C_SETUP_TIME_LIMIT,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_TIME_LIMIT);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_ENABLE);
-+
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+
-+	/* Program HW priority
-+	 * set to High - interrupt software I2C at any time
-+	 * Enable restart of SW I2C that was interrupted by HW
-+	 * disable queuing of software while I2C is in use by HW */
-+	{
-+		value = dm_read_reg(i2c_engine->base.ctx,
-+				mmDC_I2C_ARBITRATION);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_NO_QUEUED_SW_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_SW_PRIORITY);
-+
-+		dm_write_reg(i2c_engine->base.ctx,
-+				mmDC_I2C_ARBITRATION, value);
-+	}
-+
-+	return true;
-+}
-+
-+static uint32_t get_speed(
-+	const struct i2c_engine *i2c_engine)
-+{
-+	const struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-+
-+	uint32_t pre_scale = 0;
-+
-+	uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+	pre_scale = get_reg_field_value(
-+			value,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_PRESCALE);
-+
-+	/* [anaumov] it seems following is unnecessary */
-+	/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-+
-+	return pre_scale ?
-+		engine->reference_frequency / pre_scale :
-+		engine->base.default_speed;
-+}
-+
-+static void set_speed(
-+	struct i2c_engine *i2c_engine,
-+	uint32_t speed)
-+{
-+	struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	if (speed) {
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-+
-+		uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->reference_frequency / speed,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_PRESCALE);
-+
-+		set_reg_field_value(
-+			value,
-+			2,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_THRESHOLD);
-+
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+}
-+
-+static inline void reset_hw_engine(struct engine *engine)
-+{
-+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_CONTROL,
-+		DC_I2C_SOFT_RESET);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_CONTROL,
-+		DC_I2C_SW_STATUS_RESET);
-+
-+	dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+}
-+
-+static bool is_hw_busy(struct engine *engine)
-+{
-+	uint32_t i2c_sw_status = 0;
-+
-+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-+		return false;
-+
-+	reset_hw_engine(engine);
-+
-+	value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-+}
-+
-+/*
-+ * @brief
-+ * DC_GPIO_DDC MM register offsets
-+ */
-+static const uint32_t transaction_addr[] = {
-+	mmDC_I2C_TRANSACTION0,
-+	mmDC_I2C_TRANSACTION1,
-+	mmDC_I2C_TRANSACTION2,
-+	mmDC_I2C_TRANSACTION3
-+};
-+
-+static bool process_transaction(
-+	struct i2c_hw_engine_dce80 *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	uint8_t length = request->length;
-+	uint8_t *buffer = request->data;
-+
-+	bool last_transaction = false;
-+	uint32_t value = 0;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	{
-+		const uint32_t addr =
-+			transaction_addr[engine->transaction_count];
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_STOP_ON_NACK0);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_START0);
-+
-+
-+		if ((engine->transaction_count == 3) ||
-+		(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_TRANSACTION0,
-+				DC_I2C_STOP0);
-+
-+			last_transaction = true;
-+		} else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_TRANSACTION0,
-+				DC_I2C_STOP0);
-+
-+		set_reg_field_value(
-+			value,
-+			(0 != (request->action &
-+					I2CAUX_TRANSACTION_ACTION_I2C_READ)),
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_RW0);
-+
-+		set_reg_field_value(
-+			value,
-+			length,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_COUNT0);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* Write the I2C address and I2C data
-+	 * into the hardware circular buffer, one byte per entry.
-+	 * As an example, the 7-bit I2C slave address for CRT monitor
-+	 * for reading DDC/EDID information is 0b1010001.
-+	 * For an I2C send operation, the LSB must be programmed to 0;
-+	 * for I2C receive operation, the LSB must be programmed to 1. */
-+
-+	{
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			false,
-+			DC_I2C_DATA,
-+			DC_I2C_DATA_RW);
-+
-+		set_reg_field_value(
-+			value,
-+			request->address,
-+			DC_I2C_DATA,
-+			DC_I2C_DATA);
-+
-+		if (engine->transaction_count == 0) {
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX);
-+
-+			/*enable index write*/
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX_WRITE);
-+		}
-+
-+		dm_write_reg(ctx, mmDC_I2C_DATA, value);
-+
-+		if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX_WRITE);
-+
-+			while (length) {
-+
-+				set_reg_field_value(
-+					value,
-+					*buffer++,
-+					DC_I2C_DATA,
-+					DC_I2C_DATA);
-+
-+				dm_write_reg(ctx, mmDC_I2C_DATA, value);
-+				--length;
-+			}
-+		}
-+	}
-+
-+	++engine->transaction_count;
-+	engine->buffer_used_bytes += length + 1;
-+
-+	return last_transaction;
-+}
-+
-+static void execute_transaction(
-+	struct i2c_hw_engine_dce80 *engine)
-+{
-+	uint32_t value = 0;
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	{
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_DATA_DRIVE_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_CLK_DRIVE_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_DATA_DRIVE_SEL);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_INTRA_BYTE_DELAY);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SEND_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->transaction_count - 1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_TRANSACTION_COUNT);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* start I2C transfer */
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value	= dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* all transactions were executed and HW buffer became empty
-+	 * (even though it actually happens when status becomes DONE) */
-+	engine->transaction_count = 0;
-+	engine->buffer_used_bytes = 0;
-+}
-+
-+static void submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	if (!process_transaction(FROM_I2C_ENGINE(engine), request))
-+		return;
-+
-+	if (is_hw_busy(&engine->base)) {
-+		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+		return;
-+	}
-+
-+	execute_transaction(FROM_I2C_ENGINE(engine));
-+}
-+
-+static void process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply)
-+{
-+	uint8_t length = reply->length;
-+	uint8_t *buffer = reply->data;
-+
-+	uint32_t value = 0;
-+
-+	/*set index*/
-+	set_reg_field_value(
-+		value,
-+		length - 1,
-+		DC_I2C_DATA,
-+		DC_I2C_INDEX);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_DATA,
-+		DC_I2C_DATA_RW);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_DATA,
-+		DC_I2C_INDEX_WRITE);
-+
-+	dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
-+
-+	while (length) {
-+		/* after reading the status,
-+		 * if the I2C operation executed successfully
-+		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
-+		 * should read data bytes from I2C circular data buffer */
-+
-+		value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
-+
-+		*buffer++ = get_reg_field_value(
-+				value,
-+				DC_I2C_DATA,
-+				DC_I2C_DATA);
-+
-+		--length;
-+	}
-+}
-+
-+static enum i2c_channel_operation_result get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	uint32_t i2c_sw_status = 0;
-+	uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
-+		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
-+		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
-+		return I2C_CHANNEL_OPERATION_TIMEOUT;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
-+		return I2C_CHANNEL_OPERATION_FAILED;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
-+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	/* in DAL2, I2C_RESULT_OK was returned */
-+	return I2C_CHANNEL_OPERATION_NOT_STARTED;
-+}
-+
-+static uint8_t get_hw_buffer_available_size(
-+	const struct i2c_hw_engine *engine)
-+{
-+	return I2C_HW_BUFFER_SIZE -
-+		FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-+}
-+
-+static uint32_t get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length)
-+{
-+	uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-+
-+	uint32_t period_timeout;
-+	uint32_t num_of_clock_stretches;
-+
-+	if (!speed)
-+		return 0;
-+
-+	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-+
-+	num_of_clock_stretches = 1 + (length << 3) + 1;
-+	num_of_clock_stretches +=
-+		(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
-+		(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-+
-+	return period_timeout * num_of_clock_stretches;
-+}
-+
-+/*
-+ * @brief
-+ * DC_I2C_DDC1_SETUP MM register offsets
-+ *
-+ * @note
-+ * The indices of this offset array are DDC engine IDs
-+ */
-+static const int32_t ddc_setup_offset[] = {
-+
-+	mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
-+	mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
-+	mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
-+	mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
-+	mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
-+	mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
-+	mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
-+};
-+
-+/*
-+ * @brief
-+ * DC_I2C_DDC1_SPEED MM register offsets
-+ *
-+ * @note
-+ * The indices of this offset array are DDC engine IDs
-+ */
-+static const int32_t ddc_speed_offset[] = {
-+	mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
-+	mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
-+	mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
-+	mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
-+	mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
-+	mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
-+	mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
-+};
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.destroy = destroy,
-+	.get_speed = get_speed,
-+	.set_speed = set_speed,
-+	.setup_engine = setup_engine,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+	.acquire_engine = dal_i2c_hw_engine_acquire_engine,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.keep_power_up_count = keep_power_up_count,
-+	.get_engine_type = dal_i2c_hw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_hw_engine_submit_request,
-+};
-+
-+static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
-+	.get_hw_buffer_available_size =
-+		get_hw_buffer_available_size,
-+	.get_transaction_timeout =
-+		get_transaction_timeout,
-+	.wait_on_operation_result =
-+		dal_i2c_hw_engine_wait_on_operation_result,
-+};
-+
-+static bool construct(
-+	struct i2c_hw_engine_dce80 *engine,
-+	const struct i2c_hw_engine_dce80_create_arg *arg)
-+{
-+	if (arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t))
-+		return false;
-+	if (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t))
-+		return false;
-+
-+	if (!arg->reference_frequency)
-+		return false;
-+
-+	if (!dal_i2c_hw_engine_construct(&engine->base, arg->ctx))
-+		return false;
-+
-+	engine->base.base.base.funcs = &engine_funcs;
-+	engine->base.base.funcs = &i2c_engine_funcs;
-+	engine->base.funcs = &i2c_hw_engine_funcs;
-+	engine->base.default_speed = arg->default_speed;
-+	engine->addr.DC_I2C_DDCX_SETUP =
-+		mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
-+	engine->addr.DC_I2C_DDCX_SPEED =
-+		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
-+
-+	engine->engine_id = arg->engine_id;
-+	engine->reference_frequency = arg->reference_frequency;
-+	engine->buffer_used_bytes = 0;
-+	engine->transaction_count = 0;
-+	engine->engine_keep_power_up_count = 1;
-+
-+	return true;
-+}
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce80_create(
-+	const struct i2c_hw_engine_dce80_create_arg *arg)
-+{
-+	struct i2c_hw_engine_dce80 *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = dm_alloc(arg->ctx, sizeof(struct i2c_hw_engine_dce80));
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(engine, arg))
-+		return &engine->base.base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(arg->ctx, engine);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.h
-new file mode 100644
-index 0000000..5c6116f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.h
-@@ -0,0 +1,54 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_HW_ENGINE_DCE80_H__
-+#define __DAL_I2C_HW_ENGINE_DCE80_H__
-+
-+struct i2c_hw_engine_dce80 {
-+	struct i2c_hw_engine base;
-+	struct {
-+		uint32_t DC_I2C_DDCX_SETUP;
-+		uint32_t DC_I2C_DDCX_SPEED;
-+	} addr;
-+	uint32_t engine_id;
-+	/* expressed in kilohertz */
-+	uint32_t reference_frequency;
-+	/* number of bytes currently used in HW buffer */
-+	uint32_t buffer_used_bytes;
-+	/* number of pending transactions (before GO) */
-+	uint32_t transaction_count;
-+	uint32_t engine_keep_power_up_count;
-+};
-+
-+struct i2c_hw_engine_dce80_create_arg {
-+	uint32_t engine_id;
-+	uint32_t reference_frequency;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce80_create(
-+	const struct i2c_hw_engine_dce80_create_arg *arg);
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c
-new file mode 100644
-index 0000000..e5135c5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c
-@@ -0,0 +1,187 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_sw_engine_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+static const uint32_t ddc_hw_status_addr[] = {
-+	mmDC_I2C_DDC1_HW_STATUS,
-+	mmDC_I2C_DDC2_HW_STATUS,
-+	mmDC_I2C_DDC3_HW_STATUS,
-+	mmDC_I2C_DDC4_HW_STATUS,
-+	mmDC_I2C_DDC5_HW_STATUS,
-+	mmDC_I2C_DDC6_HW_STATUS,
-+	mmDC_I2C_DDCVGA_HW_STATUS
-+};
-+
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_sw_engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_I2C_SW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_sw_engine_dce80, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+
-+}
-+
-+static void destruct(
-+	struct i2c_sw_engine_dce80 *engine)
-+{
-+	dal_i2c_sw_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **engine)
-+{
-+	struct i2c_sw_engine_dce80 *sw_engine = FROM_I2C_ENGINE(*engine);
-+
-+	destruct(sw_engine);
-+
-+	dm_free((*engine)->base.ctx, sw_engine);
-+
-+	*engine = NULL;
-+}
-+
-+
-+static bool acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc_handle)
-+{
-+	return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.acquire_engine = acquire_engine,
-+	.destroy = destroy,
-+	.get_speed = dal_i2c_sw_engine_get_speed,
-+	.set_speed = dal_i2c_sw_engine_set_speed,
-+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
-+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
-+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_sw_engine_submit_request,
-+	.keep_power_up_count = dal_i2caux_keep_power_up_count,
-+};
-+
-+static bool construct(
-+	struct i2c_sw_engine_dce80 *engine,
-+	const struct i2c_sw_engine_dce80_create_arg *arg)
-+{
-+	struct i2c_sw_engine_create_arg arg_base;
-+
-+	arg_base.ctx = arg->ctx;
-+	arg_base.default_speed = arg->default_speed;
-+
-+	if (!dal_i2c_sw_engine_construct(&engine->base, &arg_base)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	engine->base.base.base.funcs = &engine_funcs;
-+	engine->base.base.funcs = &i2c_engine_funcs;
-+	engine->base.default_speed = arg->default_speed;
-+	engine->engine_id = arg->engine_id;
-+
-+	return true;
-+}
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce80_create(
-+	const struct i2c_sw_engine_dce80_create_arg *arg)
-+{
-+	struct i2c_sw_engine_dce80 *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = dm_alloc(arg->ctx, sizeof(struct i2c_sw_engine_dce80));
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(engine, arg))
-+		return &engine->base.base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(arg->ctx, engine);
-+
-+	return NULL;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.h
-new file mode 100644
-index 0000000..26355c0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.h
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_SW_ENGINE_DCE80_H__
-+#define __DAL_I2C_SW_ENGINE_DCE80_H__
-+
-+struct i2c_sw_engine_dce80 {
-+	struct i2c_sw_engine base;
-+	uint32_t engine_id;
-+};
-+
-+struct i2c_sw_engine_dce80_create_arg {
-+	uint32_t engine_id;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce80_create(
-+	const struct i2c_sw_engine_dce80_create_arg *arg);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-new file mode 100644
-index 0000000..4abf488
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-@@ -0,0 +1,264 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2caux_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "i2c_sw_engine_dce80.h"
-+#include "../i2c_hw_engine.h"
-+#include "i2c_hw_engine_dce80.h"
-+#include "../i2c_generic_hw_engine.h"
-+#include "../aux_engine.h"
-+#include "aux_engine_dce80.h"
-+
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_I2C_AUX(ptr) \
-+	container_of((ptr), struct i2caux_dce80, base)
-+
-+static void destruct(
-+	struct i2caux_dce80 *i2caux_dce80)
-+{
-+	dal_i2caux_destruct(&i2caux_dce80->base);
-+}
-+
-+static void destroy(
-+	struct i2caux **i2c_engine)
-+{
-+	struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(*i2c_engine);
-+
-+	destruct(i2caux_dce80);
-+
-+	dm_free((*i2c_engine)->ctx, i2caux_dce80);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static struct i2c_engine *acquire_i2c_hw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(i2caux);
-+
-+	struct i2c_engine *engine = NULL;
-+	bool non_generic;
-+
-+	if (!ddc)
-+		return NULL;
-+
-+	if (dal_ddc_is_hw_supported(ddc)) {
-+		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-+
-+		if (line < GPIO_DDC_LINE_COUNT) {
-+			non_generic = true;
-+			engine = i2caux->i2c_hw_engines[line];
-+		}
-+	}
-+
-+	if (!engine) {
-+		non_generic = false;
-+		engine = i2caux->i2c_generic_hw_engine;
-+	}
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (non_generic) {
-+		if (!i2caux_dce80->i2c_hw_buffer_in_use &&
-+			engine->base.funcs->acquire(&engine->base, ddc)) {
-+			i2caux_dce80->i2c_hw_buffer_in_use = true;
-+			return engine;
-+		}
-+	} else {
-+		if (engine->base.funcs->acquire(&engine->base, ddc))
-+			return engine;
-+	}
-+
-+	return NULL;
-+}
-+
-+static void release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine)
-+{
-+	if (engine->funcs->get_engine_type(engine) ==
-+		I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
-+		FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
-+
-+	dal_i2caux_release_engine(i2caux, engine);
-+}
-+
-+static const enum gpio_ddc_line hw_ddc_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
-+	GPIO_DDC_LINE_DDC_VGA
-+};
-+
-+static const enum gpio_ddc_line hw_aux_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6
-+};
-+
-+static const struct i2caux_funcs i2caux_funcs = {
-+	.destroy = destroy,
-+	.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
-+	.release_engine = release_engine,
-+	.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
-+	.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-+};
-+
-+static bool construct(
-+	struct i2caux_dce80 *i2caux_dce80,
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	/* Entire family have I2C engine reference clock frequency
-+	 * changed from XTALIN (27) to XTALIN/2 (13.5) */
-+
-+	struct i2caux *base = &i2caux_dce80->base;
-+
-+	uint32_t reference_frequency =
-+		dal_i2caux_get_reference_clock(as) >> 1;
-+
-+	bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(
-+		FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);
-+
-+	uint32_t i;
-+
-+	if (!dal_i2caux_construct(base, as, ctx)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	i2caux_dce80->base.funcs = &i2caux_funcs;
-+	i2caux_dce80->i2c_hw_buffer_in_use = false;
-+
-+	/* Create I2C HW engines (HW + SW pairs)
-+	 * for all lines which has assisted HW DDC
-+	 * 'i' (loop counter) used as DDC/AUX engine_id */
-+
-+	i = 0;
-+
-+	do {
-+		enum gpio_ddc_line line_id = hw_ddc_lines[i];
-+
-+		struct i2c_hw_engine_dce80_create_arg hw_arg;
-+
-+		if (use_i2c_sw_engine) {
-+			struct i2c_sw_engine_dce80_create_arg sw_arg;
-+
-+			sw_arg.engine_id = i;
-+			sw_arg.default_speed = base->default_i2c_sw_speed;
-+			sw_arg.ctx = ctx;
-+			base->i2c_sw_engines[line_id] =
-+				dal_i2c_sw_engine_dce80_create(&sw_arg);
-+		}
-+
-+		hw_arg.engine_id = i;
-+		hw_arg.reference_frequency = reference_frequency;
-+		hw_arg.default_speed = base->default_i2c_hw_speed;
-+		hw_arg.ctx = ctx;
-+
-+		base->i2c_hw_engines[line_id] =
-+			dal_i2c_hw_engine_dce80_create(&hw_arg);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_ddc_lines));
-+
-+	/* Create AUX engines for all lines which has assisted HW AUX
-+	 * 'i' (loop counter) used as DDC/AUX engine_id */
-+
-+	i = 0;
-+
-+	do {
-+		enum gpio_ddc_line line_id = hw_aux_lines[i];
-+
-+		struct aux_engine_dce80_create_arg arg;
-+
-+		arg.engine_id = i;
-+		arg.timeout_period = base->aux_timeout_period;
-+		arg.ctx = ctx;
-+
-+		base->aux_engines[line_id] =
-+			dal_aux_engine_dce80_create(&arg);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_aux_lines));
-+
-+	/* TODO Generic I2C SW and HW */
-+
-+	return true;
-+}
-+
-+struct i2caux *dal_i2caux_dce80_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce80 *i2caux_dce80 =
-+		dm_alloc(ctx, sizeof(struct i2caux_dce80));
-+
-+	if (!i2caux_dce80) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (construct(i2caux_dce80, as, ctx))
-+		return &i2caux_dce80->base;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dm_free(ctx, i2caux_dce80);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h
-new file mode 100644
-index 0000000..85417a8
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE80_H__
-+#define __DAL_I2C_AUX_DCE80_H__
-+
-+struct i2caux_dce80 {
-+	struct i2caux base;
-+	/* indicate the I2C HW circular buffer is in use */
-+	bool i2c_hw_buffer_in_use;
-+};
-+
-+struct i2caux *dal_i2caux_dce80_create(
-+	struct adapter_service *as,
-+	struct dc_context *ctx);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 4c2f2cb..47e7922 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -48,6 +48,10 @@
-  * This unit
-  */
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+#include "dce80/i2caux_dce80.h"
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/i2caux_dce110.h"
- #endif
-@@ -79,6 +83,10 @@ struct i2caux *dal_i2caux_create(
- 	}
- 
- 	switch (dce_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		return dal_i2caux_dce80_create(as, ctx);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-index 1372331..3e2f232 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -32,6 +32,13 @@
- #include "dce110/irq_service_dce110.h"
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	/*
-+	 * TODO: implement DCE8.x IRQ service
-+	 */
-+#include "dce110/irq_service_dce110.h"
-+#endif
-+
- #include "irq_service.h"
- 
- bool dal_irq_service_construct(
-@@ -50,6 +57,10 @@ struct irq_service *dal_irq_service_create(
- 	struct irq_service_init_data *init_data)
- {
- 	switch (version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		return dal_irq_service_dce110_create(init_data);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		return dal_irq_service_dce110_create(init_data);
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 3739776..8fdde70 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -34,6 +34,9 @@ struct dc_bios;
- 
- enum dce_version {
- 	DCE_VERSION_UNKNOWN = (-1),
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	DCE_VERSION_8_0,
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	DCE_VERSION_10_0,
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index 009b583..a621930 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -143,6 +143,12 @@ struct display_clock *dal_display_clock_dce80_create(
- 	struct adapter_service *as);
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+struct display_clock *dal_display_clock_dce80_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as);
-+#endif
-+
- void dal_display_clock_destroy(struct display_clock **to_destroy);
- bool dal_display_clock_validate(
- 	struct display_clock *disp_clk,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0804-drm-amd-amdgpu-Enabling-DAL-for-Bonaire-ASICs.patch b/common/recipes-kernel/linux/files/0804-drm-amd-amdgpu-Enabling-DAL-for-Bonaire-ASICs.patch
deleted file mode 100644
index 2c962afc..00000000
--- a/common/recipes-kernel/linux/files/0804-drm-amd-amdgpu-Enabling-DAL-for-Bonaire-ASICs.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 083fb4b9ef2c0a7eb7bad1bfc3d022bae9f99d7a Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 17 Feb 2016 11:46:16 -0500
-Subject: [PATCH 0804/1110] drm/amd/amdgpu: Enabling DAL for Bonaire ASICs
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 4b1d404..83d02c6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1389,6 +1389,11 @@ static int amdgpu_resume(struct amdgpu_device *adev)
- bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- {
- 	switch(adev->asic_type) {
-+#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
-+		return amdgpu_dal != 0;
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case CHIP_CARRIZO:
- 		return amdgpu_dal != 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0805-drm-amd-dal-Change-DEMODE-bit-in-blank-screen-settin.patch b/common/recipes-kernel/linux/files/0805-drm-amd-dal-Change-DEMODE-bit-in-blank-screen-settin.patch
deleted file mode 100644
index f5b42f5e..00000000
--- a/common/recipes-kernel/linux/files/0805-drm-amd-dal-Change-DEMODE-bit-in-blank-screen-settin.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 46c59437051b15599d634fa20dd872ac5a7a4e07 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 12 Feb 2016 11:41:51 -0500
-Subject: [PATCH 0805/1110] drm/amd/dal: Change DEMODE bit in blank screen
- setting.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c   | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 8fb90c0..ea5b064 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -347,7 +347,7 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- 
- 	set_reg_field_value(
- 		value,
--		1,
-+		0,
- 		CRTC_BLANK_CONTROL,
- 		CRTC_BLANK_DE_MODE);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index 08588f7..51d77da 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -88,7 +88,7 @@ static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
- 
- 	set_reg_field_value(
- 		value,
--		1,
-+		0,
- 		CRTCV_BLANK_CONTROL,
- 		CRTC_BLANK_DE_MODE);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0806-drm-amd-dal-Reset-unreference-clock-when-switching-s.patch b/common/recipes-kernel/linux/files/0806-drm-amd-dal-Reset-unreference-clock-when-switching-s.patch
deleted file mode 100644
index 1dcf9861..00000000
--- a/common/recipes-kernel/linux/files/0806-drm-amd-dal-Reset-unreference-clock-when-switching-s.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 946650b1bc9918336e22eb81f7994fd4742ed1f1 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 12 Feb 2016 11:42:41 -0500
-Subject: [PATCH 0806/1110] drm/amd/dal: Reset unreference clock when switching
- streams.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 810f6d5..4e73ad1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -776,9 +776,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		/*
- 		 * only disable stream in case it was ever enabled
- 		 */
--		if (old_pipe_ctx->stream)
-+		if (old_pipe_ctx->stream) {
- 			core_link_disable_stream(old_pipe_ctx);
- 
-+			ASSERT(old_pipe_ctx->clock_source);
-+			unreference_clock_source(&dc->current_context.res_ctx, old_pipe_ctx->clock_source);
-+		}
-+
- 		/*TODO: AUTO check if timing changed*/
- 		if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
- 				pipe_ctx->clock_source,
-@@ -1499,6 +1503,8 @@ static void reset_single_pipe_hw_ctx(
- 	dc->hwss.enable_display_power_gating(
- 		pipe_ctx->stream->ctx, pipe_ctx->pipe_idx, dcb,
- 			PIPE_GATING_CONTROL_ENABLE);
-+
-+	pipe_ctx->stream = NULL;
- }
- 
- static void reset_hw_ctx(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0807-drm-amd-dal-Use-verified-link-caps-to-cal-bw.patch b/common/recipes-kernel/linux/files/0807-drm-amd-dal-Use-verified-link-caps-to-cal-bw.patch
deleted file mode 100644
index 5b68f835..00000000
--- a/common/recipes-kernel/linux/files/0807-drm-amd-dal-Use-verified-link-caps-to-cal-bw.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From f9a73740f017113057cc544b5a4229c07b5ca598 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 17 Feb 2016 11:10:12 -0500
-Subject: [PATCH 0807/1110] drm/amd/dal: Use verified link caps to cal bw.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 2a5fee6..b8f7423 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1263,10 +1263,8 @@ bool dp_validate_mode_timing(
- 		timing->v_addressable == (uint32_t)480)
- 		return true;
- 
--	/* For static validation we always use reported
--	 * link settings for other cases, when no modelist
--	 * changed we can use verified link setting*/
--	link_setting = &link->public.reported_link_cap;
-+	/* We always use verified link settings */
-+	link_setting = &link->public.verified_link_cap;
- 
- 	/* TODO: DYNAMIC_VALIDATION needs to be implemented */
- 	/*if (flags.DYNAMIC_VALIDATION == 1 &&
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0808-drm-amd-dal-Only-run-detection-on-shortpulse-when-de.patch b/common/recipes-kernel/linux/files/0808-drm-amd-dal-Only-run-detection-on-shortpulse-when-de.patch
deleted file mode 100644
index 9e87e5f8..00000000
--- a/common/recipes-kernel/linux/files/0808-drm-amd-dal-Only-run-detection-on-shortpulse-when-de.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 6deef291de42d06bd405bac162ea85342251c970 Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Thu, 21 Jan 2016 14:08:25 -0500
-Subject: [PATCH 0808/1110] drm/amd/dal: Only run detection on shortpulse when
- dealing with active dongle
-
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index b8f7423..ed2add8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1527,8 +1527,9 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 		status = false;
- 	}
- 
--	if (hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
--				!= link->dpcd_sink_count)
-+	if (link->public.type == dc_connection_active_dongle &&
-+		hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
-+			!= link->dpcd_sink_count)
- 		status = true;
- 
- 	/* reasons for HPD RX:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0809-drm-amd-dal-fix-EXT-clock-source-creation.patch b/common/recipes-kernel/linux/files/0809-drm-amd-dal-fix-EXT-clock-source-creation.patch
deleted file mode 100644
index 46a68b92..00000000
--- a/common/recipes-kernel/linux/files/0809-drm-amd-dal-fix-EXT-clock-source-creation.patch
+++ /dev/null
@@ -1,525 +0,0 @@
-From 6c0ee5f2fca373ee5ad945064973ded3780db54b Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 18 Feb 2016 05:43:37 -0500
-Subject: [PATCH 0809/1110] drm/amd/dal: fix EXT clock source creation
-
-External clock source should only be created based
-on firmware info provided by bios
-
-Fix for dce10 to create pll2
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 95 +++++++++++++++-------
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    |  3 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 66 +++++++++------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 73 +++++++++++------
- 4 files changed, 157 insertions(+), 80 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index dcf44d4..f241318 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -61,6 +61,7 @@
- enum dce100_clk_src_array_id {
- 	DCE100_CLK_SRC_PLL0 = 0,
- 	DCE100_CLK_SRC_PLL1,
-+	DCE100_CLK_SRC_PLL2,
- 	DCE100_CLK_SRC_EXT,
- 
- 	DCE100_CLK_SRC_TOTAL
-@@ -147,6 +148,10 @@ static const struct dce110_clk_src_reg_offsets dce100_clk_src_reg_offsets[] = {
- 	{
- 		.pll_cntl = mmBPHYC_PLL1_PLL_CNTL,
- 		.pixclk_resync_cntl  = mmPIXCLK1_RESYNC_CNTL
-+	},
-+	{
-+		.pll_cntl = mmBPHYC_PLL2_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK2_RESYNC_CNTL
- 	}
- };
- 
-@@ -586,13 +591,14 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- static struct clock_source *find_first_free_pll(
- 		struct resource_context *res_ctx)
- {
--	if (res_ctx->clock_source_ref_count[DCE100_CLK_SRC_PLL0] == 0)
--		return res_ctx->pool.clock_sources[DCE100_CLK_SRC_PLL0];
-+	int i;
- 
--	if (res_ctx->clock_source_ref_count[DCE100_CLK_SRC_PLL1] == 0)
--		return res_ctx->pool.clock_sources[DCE100_CLK_SRC_PLL1];
-+	for (i = 0; i < DCE100_CLK_SRC_EXT; ++i) {
-+		if (res_ctx->clock_source_ref_count[i] == 0)
-+			return res_ctx->pool.clock_sources[i];
-+	}
- 
--	return 0;
-+	return NULL;
- }
- 
- static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-@@ -843,6 +849,7 @@ static enum dc_status map_clock_resources(
- 					pipe_ctx->clock_source =
- 						find_used_clk_src_for_sharing(
- 							&context->res_ctx, pipe_ctx);
-+
- 				if (pipe_ctx->clock_source == NULL)
- 					pipe_ctx->clock_source =
- 						find_first_free_pll(&context->res_ctx);
-@@ -926,7 +933,7 @@ static struct resource_funcs dce100_res_pool_funcs = {
- };
- 
- bool dce100_construct_resource_pool(
--	struct adapter_service *adapter_serv,
-+	struct adapter_service *as,
- 	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool)
-@@ -934,8 +941,10 @@ bool dce100_construct_resource_pool(
- 	unsigned int i;
- 	struct audio_init_data audio_init_data = { 0 };
- 	struct dc_context *ctx = dc->ctx;
-+	struct firmware_info info;
-+	struct dc_bios *bp;
- 
--	pool->adapter_srv = adapter_serv;
-+	pool->adapter_srv = as;
- 	pool->funcs = &dce100_res_pool_funcs;
- 
- 	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-@@ -945,16 +954,40 @@ bool dce100_construct_resource_pool(
- 	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
- 
--	pool->clock_sources[DCE100_CLK_SRC_PLL0] = dce100_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]);
--	pool->clock_sources[DCE100_CLK_SRC_PLL1] = dce100_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]);
--	pool->clock_sources[DCE100_CLK_SRC_EXT] =  dce100_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_EXTERNAL, &dce100_clk_src_reg_offsets[0]);
--	pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
-+	bp = dal_adapter_service_get_bios_parser(as);
-+
-+	pool->clock_sources[DCE100_CLK_SRC_PLL0] =
-+		dce100_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL0,
-+			&dce100_clk_src_reg_offsets[0]);
-+
-+	pool->clock_sources[DCE100_CLK_SRC_PLL1] =
-+		dce100_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL1,
-+			&dce100_clk_src_reg_offsets[1]);
-+
-+	pool->clock_sources[DCE100_CLK_SRC_PLL2] =
-+		dce100_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL2,
-+			&dce100_clk_src_reg_offsets[2]);
-+
-+	if (dal_adapter_service_get_firmware_info(as, &info) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->clock_sources[DCE100_CLK_SRC_EXT] =
-+			dce100_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_EXTERNAL,
-+				NULL);
-+		pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
-+	} else
-+		pool->clk_src_count = DCE100_CLK_SRC_TOTAL - 1;
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
-@@ -964,7 +997,7 @@ bool dce100_construct_resource_pool(
- 		}
- 	}
- 
--	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
-+	pool->display_clock = dal_display_clock_dce110_create(ctx, as);
- 	if (pool->display_clock == NULL) {
- 		dm_error("DC: failed to create display clock!\n");
- 		BREAK_TO_DEBUGGER();
-@@ -984,11 +1017,10 @@ bool dce100_construct_resource_pool(
- 
- 	}
- 
--	pool->pipe_count =
--		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
--			adapter_serv);
-+	pool->pipe_count = dal_adapter_service_get_func_controllers_num(as);
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(as);
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
- 		dm_error("DC: failed to create filter!\n");
-@@ -996,8 +1028,12 @@ bool dce100_construct_resource_pool(
- 	}
- 
- 	for (i = 0; i < pool->pipe_count; i++) {
--		pool->timing_generators[i] = dce100_timing_generator_create(
--				adapter_serv, ctx, i, &dce100_tg_offsets[i]);
-+		pool->timing_generators[i] =
-+			dce100_timing_generator_create(
-+				as,
-+				ctx,
-+				i,
-+				&dce100_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dm_error("DC: failed to create tg!\n");
-@@ -1043,13 +1079,13 @@ bool dce100_construct_resource_pool(
- 		}
- 	}
- 
--	audio_init_data.as = adapter_serv;
-+	audio_init_data.as = as;
- 	audio_init_data.ctx = ctx;
- 	pool->audio_count = 0;
- 	for (i = 0; i < pool->pipe_count; i++) {
- 		struct graphics_object_id obj_id;
- 
--		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		obj_id = dal_adapter_service_enum_audio_object(as, i);
- 		if (false == dal_graphics_object_id_is_valid(obj_id)) {
- 			/* no more valid audio objects */
- 			break;
-@@ -1070,8 +1106,7 @@ bool dce100_construct_resource_pool(
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce100_stream_encoder_create(
- 				i, dc->ctx,
--				dal_adapter_service_get_bios_parser(
--					adapter_serv),
-+				dal_adapter_service_get_bios_parser(as),
- 				&stream_enc_regs[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
-@@ -1084,8 +1119,8 @@ bool dce100_construct_resource_pool(
- 	for (i = 0; i < num_virtual_links; i++) {
- 		pool->stream_enc[pool->stream_enc_count] =
- 			virtual_stream_encoder_create(
--				dc->ctx, dal_adapter_service_get_bios_parser(
--								adapter_serv));
-+				dc->ctx,
-+				dal_adapter_service_get_bios_parser(as));
- 		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dm_error("DC: failed to create stream_encoder!\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index e1bac1f..ba2929b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -1110,7 +1110,6 @@ bool dce110_clk_src_construct(
- 	clk_src->bios = bios;
- 	clk_src->base.id = id;
- 	clk_src->base.funcs = &dce110_clk_src_funcs;
--	clk_src->offsets = *reg_offsets;
- 
- 	if (clk_src->bios->funcs->get_firmware_info(
- 			clk_src->bios, &fw_info) != BP_RESULT_OK) {
-@@ -1125,6 +1124,8 @@ bool dce110_clk_src_construct(
- 	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
- 		return true;
- 
-+	clk_src->offsets = *reg_offsets;
-+
- 	/* PLL only from here on */
- 	ss_info_from_atombios_create(clk_src);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index c65f401..26fc104 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1046,7 +1046,7 @@ static struct resource_funcs dce110_res_pool_funcs = {
- };
- 
- bool dce110_construct_resource_pool(
--	struct adapter_service *adapter_serv,
-+	struct adapter_service *as,
- 	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool)
-@@ -1054,7 +1054,10 @@ bool dce110_construct_resource_pool(
- 	unsigned int i;
- 	struct audio_init_data audio_init_data = { 0 };
- 	struct dc_context *ctx = dc->ctx;
--	pool->adapter_srv = adapter_serv;
-+	struct firmware_info info;
-+	struct dc_bios *bp;
-+
-+	pool->adapter_srv = as;
- 	pool->funcs = &dce110_res_pool_funcs;
- 
- 	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-@@ -1064,16 +1067,33 @@ bool dce110_construct_resource_pool(
- 	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
- 
--	pool->clock_sources[DCE110_CLK_SRC_PLL0] = dce110_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL0, &dce110_clk_src_reg_offsets[0]);
--	pool->clock_sources[DCE110_CLK_SRC_PLL1] = dce110_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL1, &dce110_clk_src_reg_offsets[1]);
--	pool->clock_sources[DCE110_CLK_SRC_EXT] =  dce110_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_EXTERNAL, &dce110_clk_src_reg_offsets[0]);
--	pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
-+	bp = dal_adapter_service_get_bios_parser(as);
-+
-+	pool->clock_sources[DCE110_CLK_SRC_PLL0] =
-+		dce110_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL0,
-+			&dce110_clk_src_reg_offsets[0]);
-+
-+	pool->clock_sources[DCE110_CLK_SRC_PLL1] =
-+		dce110_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL1,
-+			&dce110_clk_src_reg_offsets[1]);
-+
-+	if (dal_adapter_service_get_firmware_info(as, &info) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->clock_sources[DCE110_CLK_SRC_EXT] =
-+			dce110_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_EXTERNAL,
-+				NULL);
-+		pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
-+	} else
-+		pool->clk_src_count = DCE110_CLK_SRC_TOTAL - 1;
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
-@@ -1083,7 +1103,7 @@ bool dce110_construct_resource_pool(
- 		}
- 	}
- 
--	pool->display_clock = dal_display_clock_dce110_create(ctx, adapter_serv);
-+	pool->display_clock = dal_display_clock_dce110_create(ctx, as);
- 	if (pool->display_clock == NULL) {
- 		dm_error("DC: failed to create display clock!\n");
- 		BREAK_TO_DEBUGGER();
-@@ -1102,10 +1122,8 @@ bool dce110_construct_resource_pool(
- 
- 	}
- 
--	pool->pipe_count =
--		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(
--			adapter_serv);
-+	pool->pipe_count = dal_adapter_service_get_func_controllers_num(as);
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(as);
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
-@@ -1115,7 +1133,7 @@ bool dce110_construct_resource_pool(
- 
- 	for (i = 0; i < pool->pipe_count; i++) {
- 		pool->timing_generators[i] = dce110_timing_generator_create(
--				adapter_serv, ctx, i, &dce110_tg_offsets[i]);
-+				as, ctx, i, &dce110_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dm_error("DC: failed to create tg!\n");
-@@ -1160,13 +1178,13 @@ bool dce110_construct_resource_pool(
- 		}
- 	}
- 
--	audio_init_data.as = adapter_serv;
-+	audio_init_data.as = as;
- 	audio_init_data.ctx = ctx;
- 	pool->audio_count = 0;
- 	for (i = 0; i < pool->pipe_count; i++) {
- 		struct graphics_object_id obj_id;
- 
--		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		obj_id = dal_adapter_service_enum_audio_object(as, i);
- 		if (false == dal_graphics_object_id_is_valid(obj_id)) {
- 			/* no more valid audio objects */
- 			break;
-@@ -1187,8 +1205,7 @@ bool dce110_construct_resource_pool(
- 		if (pool->stream_engines.u_all & 1 << i) {
- 			pool->stream_enc[i] = dce110_stream_encoder_create(
- 				i, dc->ctx,
--				dal_adapter_service_get_bios_parser(
--					adapter_serv),
-+				dal_adapter_service_get_bios_parser(as),
- 				&stream_enc_regs[i]);
- 			if (pool->stream_enc[i] == NULL) {
- 				BREAK_TO_DEBUGGER();
-@@ -1201,8 +1218,9 @@ bool dce110_construct_resource_pool(
- 	for (i = 0; i < num_virtual_links; i++) {
- 		pool->stream_enc[pool->stream_enc_count] =
- 			virtual_stream_encoder_create(
--				dc->ctx, dal_adapter_service_get_bios_parser(
--								adapter_serv));
-+				dc->ctx,
-+				dal_adapter_service_get_bios_parser(as));
-+
- 		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dm_error("DC: failed to create stream_encoder!\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 1eeb469..c7bfa28 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -1048,7 +1048,7 @@ static struct resource_funcs dce80_res_pool_funcs = {
- };
- 
- bool dce80_construct_resource_pool(
--	struct adapter_service *adapter_serv,
-+	struct adapter_service *as,
- 	uint8_t num_virtual_links,
- 	struct dc *dc,
- 	struct resource_pool *pool)
-@@ -1056,7 +1056,10 @@ bool dce80_construct_resource_pool(
- 	unsigned int i;
- 	struct audio_init_data audio_init_data = { 0 };
- 	struct dc_context *ctx = dc->ctx;
--	pool->adapter_srv = adapter_serv;
-+	struct firmware_info info;
-+	struct dc_bios *bp;
-+
-+	pool->adapter_srv = as;
- 	pool->funcs = &dce80_res_pool_funcs;
- 
- 	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-@@ -1066,19 +1069,41 @@ bool dce80_construct_resource_pool(
- 	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
- 	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
- 
--	pool->clock_sources[DCE80_CLK_SRC_PLL0] = dce80_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL0, &dce80_clk_src_reg_offsets[0]);
--	pool->clock_sources[DCE80_CLK_SRC_PLL1] = dce80_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL1, &dce80_clk_src_reg_offsets[1]);
--	pool->clock_sources[DCE80_CLK_SRC_PLL2] = dce80_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_PLL2, &dce80_clk_src_reg_offsets[2]);
--	pool->clock_sources[DCE80_CLK_SRC_EXT] =  dce80_clock_source_create(
--		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
--		CLOCK_SOURCE_ID_EXTERNAL, &dce80_clk_src_reg_offsets[0]);
--	pool->clk_src_count = DCE80_CLK_SRC_TOTAL;
-+	bp = dal_adapter_service_get_bios_parser(as);
-+
-+	pool->clock_sources[DCE80_CLK_SRC_PLL0] =
-+		dce80_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL0,
-+			&dce80_clk_src_reg_offsets[0]);
-+
-+	pool->clock_sources[DCE80_CLK_SRC_PLL1] =
-+		dce80_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL1,
-+			&dce80_clk_src_reg_offsets[1]);
-+
-+	pool->clock_sources[DCE80_CLK_SRC_PLL2] =
-+		dce80_clock_source_create(
-+			ctx,
-+			bp,
-+			CLOCK_SOURCE_ID_PLL2,
-+			&dce80_clk_src_reg_offsets[2]);
-+
-+	if (dal_adapter_service_get_firmware_info(as, &info) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->clock_sources[DCE80_CLK_SRC_EXT] =
-+			dce80_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_EXTERNAL,
-+				NULL);
-+
-+		pool->clk_src_count = DCE80_CLK_SRC_TOTAL;
-+	} else
-+		pool->clk_src_count = DCE80_CLK_SRC_TOTAL - 1;
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
-@@ -1088,7 +1113,7 @@ bool dce80_construct_resource_pool(
- 		}
- 	}
- 
--	pool->display_clock = dal_display_clock_dce80_create(ctx, adapter_serv);
-+	pool->display_clock = dal_display_clock_dce80_create(ctx, as);
- 	if (pool->display_clock == NULL) {
- 		dm_error("DC: failed to create display clock!\n");
- 		BREAK_TO_DEBUGGER();
-@@ -1107,10 +1132,8 @@ bool dce80_construct_resource_pool(
- 
- 	}
- 
--	pool->pipe_count =
--		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count =
--					dal_adapter_service_get_stream_engines_num(adapter_serv);
-+	pool->pipe_count = dal_adapter_service_get_func_controllers_num(as);
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(as);
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
-@@ -1120,7 +1143,7 @@ bool dce80_construct_resource_pool(
- 
- 	for (i = 0; i < pool->pipe_count; i++) {
- 		pool->timing_generators[i] = dce80_timing_generator_create(
--				adapter_serv, ctx, i, &dce80_tg_offsets[i]);
-+				as, ctx, i, &dce80_tg_offsets[i]);
- 		if (pool->timing_generators[i] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dm_error("DC: failed to create tg!\n");
-@@ -1161,13 +1184,13 @@ bool dce80_construct_resource_pool(
- 		}
- 	}
- 
--	audio_init_data.as = adapter_serv;
-+	audio_init_data.as = as;
- 	audio_init_data.ctx = ctx;
- 	pool->audio_count = 0;
- 	for (i = 0; i < pool->pipe_count; i++) {
- 		struct graphics_object_id obj_id;
- 
--		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		obj_id = dal_adapter_service_enum_audio_object(as, i);
- 		if (false == dal_graphics_object_id_is_valid(obj_id)) {
- 			/* no more valid audio objects */
- 			break;
-@@ -1188,7 +1211,7 @@ bool dce80_construct_resource_pool(
- 			pool->stream_enc[i] = dce80_stream_encoder_create(
- 					i, dc->ctx,
- 					dal_adapter_service_get_bios_parser(
--						adapter_serv),
-+						as),
- 					&stream_enc_regs[i]);
- 
- 			if (pool->stream_enc[i] == NULL) {
-@@ -1203,7 +1226,7 @@ bool dce80_construct_resource_pool(
- 		pool->stream_enc[pool->stream_enc_count] =
- 			virtual_stream_encoder_create(
- 				dc->ctx, dal_adapter_service_get_bios_parser(
--								adapter_serv));
-+								as));
- 		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			dm_error("DC: failed to create stream_encoder!\n");
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0810-drm-amd-dal-allow-non-audio-DP-HDMI-light-up.patch b/common/recipes-kernel/linux/files/0810-drm-amd-dal-allow-non-audio-DP-HDMI-light-up.patch
deleted file mode 100644
index 39555ccf..00000000
--- a/common/recipes-kernel/linux/files/0810-drm-amd-dal-allow-non-audio-DP-HDMI-light-up.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 274b66f7447b467234f35ee71045ed38d4b58858 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 18 Feb 2016 06:05:09 -0500
-Subject: [PATCH 0810/1110] drm/amd/dal: allow non-audio DP/HDMI light-up
-
-In case asic has less audio endpoints available
-then pipes, display still should be available to
-light-up
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 12 ++++++++----
- drivers/gpu/drm/amd/dal/dc/inc/core_status.h  |  1 -
- 2 files changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 80fb823..5d9095e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -838,10 +838,14 @@ enum dc_status map_resources(
- 				pipe_ctx->audio = find_first_free_audio(
- 						&context->res_ctx);
- 
--				if (!pipe_ctx->audio)
--					return DC_NO_STREAM_AUDIO_RESOURCE;
--
--				set_audio_in_use(&context->res_ctx,
-+				/*
-+				 * Audio assigned in order first come first get.
-+				 * There are asics which has number of audio
-+				 * resources less then number of pipes
-+				 */
-+				if (pipe_ctx->audio)
-+					set_audio_in_use(
-+						&context->res_ctx,
- 						pipe_ctx->audio);
- 			}
- 		}
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_status.h b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-index 9682cf8..b395ae5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-@@ -31,7 +31,6 @@ enum dc_status {
- 
- 	DC_NO_CONTROLLER_RESOURCE,
- 	DC_NO_STREAM_ENG_RESOURCE,
--	DC_NO_STREAM_AUDIO_RESOURCE,
- 	DC_NO_CLOCK_SOURCE_RESOURCE,
- 	DC_FAIL_CONTROLLER_VALIDATE,
- 	DC_FAIL_ENC_VALIDATE,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0811-drm-amd-dal-refactor-ipp-header-for-HW-pseudo-code.patch b/common/recipes-kernel/linux/files/0811-drm-amd-dal-refactor-ipp-header-for-HW-pseudo-code.patch
deleted file mode 100644
index 6c24383d..00000000
--- a/common/recipes-kernel/linux/files/0811-drm-amd-dal-refactor-ipp-header-for-HW-pseudo-code.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From 0fbec3793881bf34bebbb67ab2f71bbaaa630b92 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 18 Feb 2016 12:37:30 -0500
-Subject: [PATCH 0811/1110] drm/amd/dal: refactor ipp header for HW pseudo code
-
-Make sure all types used in ipp.h are either in the file
-itself or in dc_hw_types.h so that they are visible for
-HW diag team when then write their pseudo code
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h          | 87 +++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc_types.h             | 71 ------------------
- drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h      |  5 --
- drivers/gpu/drm/amd/dal/include/video_csc_types.h |  7 --
- 4 files changed, 87 insertions(+), 83 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index 71d6301..2a9ec19 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -278,5 +278,92 @@ struct dc_cursor_position {
- 	bool hot_spot_enable;
- };
- 
-+/* IPP related types */
-+
-+/* Used by both ipp amd opp functions*/
-+/* TODO: to be consolidated with enum color_space */
-+enum ovl_color_space {
-+	OVL_COLOR_SPACE_UNKNOWN = 0,
-+	OVL_COLOR_SPACE_RGB,
-+	OVL_COLOR_SPACE_YUV601,
-+	OVL_COLOR_SPACE_YUV709
-+};
-+
-+/*
-+ * This enum is for programming CURSOR_MODE register field. What this register
-+ * should be programmed to depends on OS requested cursor shape flags and what
-+ * we stored in the cursor surface.
-+ */
-+enum dc_cursor_color_format {
-+	CURSOR_MODE_MONO,
-+	CURSOR_MODE_COLOR_1BIT_AND,
-+	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
-+	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
-+};
-+
-+/*
-+ * This is all the parameters required by DAL in order to update the cursor
-+ * attributes, including the new cursor image surface address, size, hotspot
-+ * location, color format, etc.
-+ */
-+
-+union dc_cursor_attribute_flags {
-+	struct {
-+		uint32_t ENABLE_MAGNIFICATION:1;
-+		uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
-+		uint32_t HORIZONTAL_MIRROR:1;
-+		uint32_t VERTICAL_MIRROR:1;
-+		uint32_t RESERVED:28;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct dc_cursor_attributes {
-+	PHYSICAL_ADDRESS_LOC address;
-+
-+	/* Width and height should correspond to cursor surface width x heigh */
-+	uint32_t width;
-+	uint32_t height;
-+	uint32_t x_hot;
-+	uint32_t y_hot;
-+
-+	enum dc_cursor_color_format color_format;
-+
-+	/* In case we support HW Cursor rotation in the future */
-+	enum dc_rotation_angle rotation_angle;
-+
-+	union dc_cursor_attribute_flags attribute_flags;
-+};
-+
-+/* Pixel format */
-+enum pixel_format {
-+	/*graph*/
-+	PIXEL_FORMAT_UNINITIALIZED,
-+	PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_RGB565,
-+	PIXEL_FORMAT_ARGB8888,
-+	PIXEL_FORMAT_ARGB2101010,
-+	PIXEL_FORMAT_ARGB2101010_XRBIAS,
-+	PIXEL_FORMAT_FP16,
-+	/*video*/
-+	PIXEL_FORMAT_420BPP12,
-+	PIXEL_FORMAT_422BPP16,
-+	PIXEL_FORMAT_444BPP16,
-+	PIXEL_FORMAT_444BPP32,
-+	/*end of pixel format definition*/
-+	PIXEL_FORMAT_INVALID,
-+
-+	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
-+	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
-+	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_444BPP32,
-+	PIXEL_FORMAT_UNKNOWN
-+};
-+
-+struct dev_c_lut {
-+	uint8_t red;
-+	uint8_t green;
-+	uint8_t blue;
-+};
- #endif /* DC_HW_TYPES_H */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 863443b..4e36b85 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -80,33 +80,6 @@ enum color_space {
- 	COLOR_SPACE_N_MVPU_SUPER_AA,
- };
- 
--
--
--/* Pixel format */
--enum pixel_format {
--	/*graph*/
--	PIXEL_FORMAT_UNINITIALIZED,
--	PIXEL_FORMAT_INDEX8,
--	PIXEL_FORMAT_RGB565,
--	PIXEL_FORMAT_ARGB8888,
--	PIXEL_FORMAT_ARGB2101010,
--	PIXEL_FORMAT_ARGB2101010_XRBIAS,
--	PIXEL_FORMAT_FP16,
--	/*video*/
--	PIXEL_FORMAT_420BPP12,
--	PIXEL_FORMAT_422BPP16,
--	PIXEL_FORMAT_444BPP16,
--	PIXEL_FORMAT_444BPP32,
--	/*end of pixel format definition*/
--	PIXEL_FORMAT_INVALID,
--
--	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
--	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
--	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
--	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_444BPP32,
--	PIXEL_FORMAT_UNKNOWN
--};
--
- enum tiling_mode {
- 	TILING_MODE_INVALID,
- 	TILING_MODE_LINEAR,
-@@ -472,50 +445,6 @@ struct dc_mode_timing {
- 	struct dc_crtc_timing crtc_timing;
- };
- 
--/* This enum is for programming CURSOR_MODE register field. */
--/* What this register should be programmed to depends on */
--/* OS requested cursor shape flags */
--/* and what we stored in the cursor surface. */
--enum dc_cursor_color_format {
--	CURSOR_MODE_MONO,
--	CURSOR_MODE_COLOR_1BIT_AND,
--	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
--	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
--};
--
--union dc_cursor_attribute_flags {
--	struct {
--		uint32_t ENABLE_MAGNIFICATION:1;
--		uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
--		uint32_t HORIZONTAL_MIRROR:1;
--		uint32_t VERTICAL_MIRROR:1;
--		uint32_t RESERVED:28;
--	} bits;
--	uint32_t value;
--};
--
--/* This is all the parameters required by DAL in order to */
--/* update the cursor attributes, */
--/* including the new cursor image surface address, size, */
--/* hotspot location, color format, etc. */
--struct dc_cursor_attributes {
--	PHYSICAL_ADDRESS_LOC address;
--
--	/* Width and height should correspond to cursor surface width x heigh */
--	uint32_t width;
--	uint32_t height;
--	uint32_t x_hot;
--	uint32_t y_hot;
--
--	enum dc_cursor_color_format color_format;
--
--	/* In case we support HW Cursor rotation in the future */
--	enum dc_rotation_angle rotation_angle;
--
--	union dc_cursor_attribute_flags attribute_flags;
--
--};
--
- enum dc_power_state {
- 	DC_POWER_STATE_ON = 1,
- 	DC_POWER_STATE_STANDBY,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-index ca23e1b..f1cdce8 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h
-@@ -29,11 +29,6 @@
- #include "dc_types.h"
- 
- /* TODO: Used in IPP and OPP */
--struct dev_c_lut {
--	uint8_t red;
--	uint8_t green;
--	uint8_t blue;
--};
- 
- struct dev_c_lut16 {
- 	uint16_t red;
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index e2a9343..354a01b 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -33,13 +33,6 @@ enum ovl_alpha_blending_mode {
- 	OVL_ALPHA_PER_PIXEL_OVL_ALPHA_MODE
- };
- 
--enum ovl_color_space {
--	OVL_COLOR_SPACE_UNKNOWN = 0,
--	OVL_COLOR_SPACE_RGB,
--	OVL_COLOR_SPACE_YUV601,
--	OVL_COLOR_SPACE_YUV709
--};
--
- enum ovl_surface_format {
- 	OVL_SURFACE_FORMAT_UNKNOWN = 0,
- 	OVL_SURFACE_FORMAT_YUY2,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0812-drm-amd-dal-Fixed-HDMI-DVI-dongle-not-light-up-issue.patch b/common/recipes-kernel/linux/files/0812-drm-amd-dal-Fixed-HDMI-DVI-dongle-not-light-up-issue.patch
deleted file mode 100644
index 4fa645a5..00000000
--- a/common/recipes-kernel/linux/files/0812-drm-amd-dal-Fixed-HDMI-DVI-dongle-not-light-up-issue.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 8e75667d141c823d595bc3e4a0a47f285676a1a1 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Thu, 18 Feb 2016 13:42:55 -0500
-Subject: [PATCH 0812/1110] drm/amd/dal: Fixed HDMI-DVI dongle not light up
- issue.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 5d9095e..18cddfd 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -747,6 +747,17 @@ static void set_stream_signal(struct pipe_ctx *pipe_ctx)
- 	}
- 
- 	pipe_ctx->signal = dc_sink->sink_signal;
-+
-+	/* Down-grade pipe_ctx signal instead of sink singal from HDMI to DVI
-+	 * here based on audio info in stream. This allows DC to handle stream
-+	 * with or without audio on a HDMI connector.
-+	 *
-+	 * On a HDMI to DVI passive dongle, audio info is not available from the
-+	 * EDID and the signal is down-graded in pipe ctx.
-+	 */
-+	if (pipe_ctx->signal == SIGNAL_TYPE_HDMI_TYPE_A &&
-+			pipe_ctx->stream->public.audio_info.mode_count == 0)
-+		pipe_ctx->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- }
- 
- enum dc_status map_resources(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0813-drm-amd-dal-Implement-power-control-of-COL_MAN-Gamma.patch b/common/recipes-kernel/linux/files/0813-drm-amd-dal-Implement-power-control-of-COL_MAN-Gamma.patch
deleted file mode 100644
index c403dd01..00000000
--- a/common/recipes-kernel/linux/files/0813-drm-amd-dal-Implement-power-control-of-COL_MAN-Gamma.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From c0a545146b53d2ccaff1e0b1ab064a0f79c1450d Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 18 Feb 2016 13:50:38 -0500
-Subject: [PATCH 0813/1110] drm/amd/dal: Implement power control of COL_MAN
- Gamma correction.
-
-This is a part of MPO bringup.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c   | 31 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c   |  6 +++++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |  3 +++
- 5 files changed, 42 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-index 404b2bf..170c273 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
-@@ -10,7 +10,7 @@ dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
- dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
- dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o \
- dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \
--dce110_mem_input_v.o
-+dce110_mem_input_v.o dce110_opp_v.o
- 
- AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index c06cf38..ab937d5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -42,7 +42,7 @@ enum {
- /* Constructor, Destructor               */
- /*****************************************/
- 
--struct opp_funcs funcs = {
-+static struct opp_funcs funcs = {
- 		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
- 		.opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction,
- 		.opp_program_clamping_and_pixel_encoding = dce110_opp_program_clamping_and_pixel_encoding,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-index b9d7eda..8f4cb96 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-@@ -517,4 +517,35 @@ bool dce110_opp_program_regamma_pwl_v(
- 	return true;
- }
- 
-+void dce110_opp_power_on_regamma_lut_v(
-+	struct output_pixel_processor *opp,
-+	bool power_on)
-+{
-+	uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_GAMMA_CORR_MEM_PWR_FORCE);
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
- 
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE);
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
-+
-+	dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-index 367325f..4b9042f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-@@ -39,6 +39,8 @@
- /*****************************************/
- 
- struct opp_funcs funcs = {
-+		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
-+
- 		.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
- 
- 		.opp_set_csc_default = dce110_opp_v_set_csc_default,
-@@ -47,10 +49,14 @@ struct opp_funcs funcs = {
- 
- 		.opp_program_bit_depth_reduction =
- 				dce110_opp_program_bit_depth_reduction,
-+
- 		.opp_program_clamping_and_pixel_encoding =
- 				dce110_opp_program_clamping_and_pixel_encoding,
- 
- 		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-+
-+		.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
-+
- 		.opp_destroy = dce110_opp_destroy,
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-index 3f2ed4a..9543a70 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -51,5 +51,8 @@ bool dce110_opp_program_regamma_pwl_v(
- 	struct output_pixel_processor *opp,
- 	const struct regamma_params *params);
- 
-+void dce110_opp_power_on_regamma_lut_v(
-+	struct output_pixel_processor *opp,
-+	bool power_on);
- 
- #endif /* __DC_OPP_DCE110_V_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0814-drm-amd-dal-hack-in-CZ-mpo-start-support.patch b/common/recipes-kernel/linux/files/0814-drm-amd-dal-hack-in-CZ-mpo-start-support.patch
deleted file mode 100644
index 2ef5df83..00000000
--- a/common/recipes-kernel/linux/files/0814-drm-amd-dal-hack-in-CZ-mpo-start-support.patch
+++ /dev/null
@@ -1,2506 +0,0 @@
-From 0c751063ee32626b7bc5f3b7ab45914cb046dacc Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Wed, 10 Feb 2016 17:03:10 -0500
-Subject: [PATCH 0814/1110] drm/amd/dal: hack in CZ mpo start support
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  21 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 142 ++++-----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 128 +++++----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 156 +++++-----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c   |  10 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |   4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  88 ++++--
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   |   2 -
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c   | 230 ++++-----------
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 316 ++++++++-------------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  16 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c |   2 -
- .../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c | 132 +--------
- drivers/gpu/drm/amd/dal/dc/inc/core_status.h       |   1 +
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   8 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   9 +-
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |   3 +
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |   5 -
- drivers/gpu/drm/amd/dal/include/scaler_types.h     | 149 +---------
- 19 files changed, 521 insertions(+), 901 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index bcc6f68..1d1cd89 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -175,13 +175,14 @@ static void init_hw(struct dc *dc)
- 	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		xfm = dc->res_pool.transforms[i];
- 
--		dc->hwss.enable_display_power_gating(
--				dc->ctx, i, bp,
--				PIPE_GATING_CONTROL_INIT);
--		dc->hwss.enable_display_power_gating(
--				dc->ctx, i, bp,
--				PIPE_GATING_CONTROL_DISABLE);
--
-+		if (i != DCE110_UNDERLAY_IDX) {
-+			dc->hwss.enable_display_power_gating(
-+					dc->ctx, i, bp,
-+					PIPE_GATING_CONTROL_INIT);
-+			dc->hwss.enable_display_power_gating(
-+					dc->ctx, i, bp,
-+					PIPE_GATING_CONTROL_DISABLE);
-+		}
- 		xfm->funcs->transform_power_up(xfm);
- 		dc->hwss.enable_display_pipe_clock_gating(
- 			dc->ctx,
-@@ -392,6 +393,7 @@ ctx_fail:
- 
- static void destruct(struct dc *dc)
- {
-+	destruct_val_ctx(&dc->current_context);
- 	destroy_links(dc);
- 	dc->res_pool.funcs->destruct(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
-@@ -452,6 +454,7 @@ bool dc_validate_resources(
- 	result = dc->res_pool.funcs->validate_with_context(
- 						dc, set, set_count, context);
- 
-+	destruct_val_ctx(context);
- 	dm_free(dc->ctx, context);
- context_alloc_fail:
- 
-@@ -678,10 +681,8 @@ void dc_flip_surface_addrs(
- 		 */
- 		surface->public.address = flip_addrs[i].address;
- 		surface->public.flip_immediate = flip_addrs[i].flip_immediate;
--
--		dc->hwss.update_plane_addrs(
--				dc, &dc->current_context.res_ctx, surface);
- 	}
-+	dc->hwss.update_plane_addrs(dc, &dc->current_context.res_ctx);
- }
- 
- enum dc_irq_source dc_interrupt_to_irq_source(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 18cddfd..e7a4b3e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -243,17 +243,17 @@ static void calculate_viewport(
- 	/* offset = src.ofs + (clip.ofs - dst.ofs) * scl_ratio
- 	 * num_pixels = clip.num_pix * scl_ratio
- 	 */
--	pipe_ctx->viewport.x = src.x + (clip.x - dst.x) * src.width / dst.width;
--	pipe_ctx->viewport.width = clip.width * src.width / dst.width;
-+	pipe_ctx->scl_data.viewport.x = src.x + (clip.x - dst.x) * src.width / dst.width;
-+	pipe_ctx->scl_data.viewport.width = clip.width * src.width / dst.width;
- 
--	pipe_ctx->viewport.y = src.y + (clip.y - dst.y) * src.height / dst.height;
--	pipe_ctx->viewport.height = clip.height * src.height / dst.height;
-+	pipe_ctx->scl_data.viewport.y = src.y + (clip.y - dst.y) * src.height / dst.height;
-+	pipe_ctx->scl_data.viewport.height = clip.height * src.height / dst.height;
- 
- 	/* Minimum viewport such that 420/422 chroma vp is non 0 */
--	if (pipe_ctx->viewport.width < 2)
--		pipe_ctx->viewport.width = 2;
--	if (pipe_ctx->viewport.height < 2)
--		pipe_ctx->viewport.height = 2;
-+	if (pipe_ctx->scl_data.viewport.width < 2)
-+		pipe_ctx->scl_data.viewport.width = 2;
-+	if (pipe_ctx->scl_data.viewport.height < 2)
-+		pipe_ctx->scl_data.viewport.height = 2;
- }
- 
- static void calculate_overscan(
-@@ -262,40 +262,40 @@ static void calculate_overscan(
- {
- 	struct core_stream *stream = pipe_ctx->stream;
- 
--	pipe_ctx->overscan.left = stream->public.dst.x;
-+	pipe_ctx->scl_data.overscan.left = stream->public.dst.x;
- 	if (stream->public.src.x < surface->clip_rect.x)
--		pipe_ctx->overscan.left += (surface->clip_rect.x
-+		pipe_ctx->scl_data.overscan.left += (surface->clip_rect.x
- 			- stream->public.src.x) * stream->public.dst.width
- 			/ stream->public.src.width;
- 
--	pipe_ctx->overscan.right = stream->public.timing.h_addressable
-+	pipe_ctx->scl_data.overscan.right = stream->public.timing.h_addressable
- 		- stream->public.dst.x - stream->public.dst.width;
- 	if (stream->public.src.x + stream->public.src.width
- 		> surface->clip_rect.x + surface->clip_rect.width)
--		pipe_ctx->overscan.right = stream->public.timing.h_addressable -
-+		pipe_ctx->scl_data.overscan.right = stream->public.timing.h_addressable -
- 			dal_fixed31_32_floor(dal_fixed31_32_div(
- 				dal_fixed31_32_from_int(
--						pipe_ctx->viewport.width),
--						pipe_ctx->ratios.horz)) -
--						pipe_ctx->overscan.left;
-+						pipe_ctx->scl_data.viewport.width),
-+						pipe_ctx->scl_data.ratios.horz)) -
-+						pipe_ctx->scl_data.overscan.left;
- 
- 
--	pipe_ctx->overscan.top = stream->public.dst.y;
-+	pipe_ctx->scl_data.overscan.top = stream->public.dst.y;
- 	if (stream->public.src.y < surface->clip_rect.y)
--		pipe_ctx->overscan.top += (surface->clip_rect.y
-+		pipe_ctx->scl_data.overscan.top += (surface->clip_rect.y
- 			- stream->public.src.y) * stream->public.dst.height
- 			/ stream->public.src.height;
- 
--	pipe_ctx->overscan.bottom = stream->public.timing.v_addressable
-+	pipe_ctx->scl_data.overscan.bottom = stream->public.timing.v_addressable
- 		- stream->public.dst.y - stream->public.dst.height;
- 	if (stream->public.src.y + stream->public.src.height
- 		> surface->clip_rect.y + surface->clip_rect.height)
--		pipe_ctx->overscan.bottom = stream->public.timing.v_addressable -
-+		pipe_ctx->scl_data.overscan.bottom = stream->public.timing.v_addressable -
- 			dal_fixed31_32_floor(dal_fixed31_32_div(
- 				dal_fixed31_32_from_int(
--						pipe_ctx->viewport.height),
--						pipe_ctx->ratios.vert)) -
--						pipe_ctx->overscan.top;
-+						pipe_ctx->scl_data.viewport.height),
-+						pipe_ctx->scl_data.ratios.vert)) -
-+						pipe_ctx->scl_data.overscan.top;
- 
- 
- 	/* TODO: Add timing overscan to finalize overscan calculation*/
-@@ -311,32 +311,32 @@ static void calculate_scaling_ratios(
- 	const uint32_t out_w = stream->public.dst.width;
- 	const uint32_t out_h = stream->public.dst.height;
- 
--	pipe_ctx->ratios.horz = dal_fixed31_32_from_fraction(
-+	pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
- 					surface->src_rect.width,
- 					surface->dst_rect.width);
--	pipe_ctx->ratios.vert = dal_fixed31_32_from_fraction(
-+	pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction(
- 					surface->src_rect.height,
- 					surface->dst_rect.height);
- 
- 	if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
--		pipe_ctx->ratios.horz.value *= 2;
-+		pipe_ctx->scl_data.ratios.horz.value *= 2;
- 	else if (surface->stereo_format
- 					== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
--		pipe_ctx->ratios.vert.value *= 2;
-+		pipe_ctx->scl_data.ratios.vert.value *= 2;
- 
--	pipe_ctx->ratios.vert.value = div64_s64(pipe_ctx->ratios.vert.value * in_h,
-+	pipe_ctx->scl_data.ratios.vert.value = div64_s64(pipe_ctx->scl_data.ratios.vert.value * in_h,
- 			out_h);
--	pipe_ctx->ratios.horz.value = div64_s64(pipe_ctx->ratios.horz.value * in_w,
-+	pipe_ctx->scl_data.ratios.horz.value = div64_s64(pipe_ctx->scl_data.ratios.horz.value * in_w,
- 			out_w);
- 
--	pipe_ctx->ratios.horz_c = pipe_ctx->ratios.horz;
--	pipe_ctx->ratios.vert_c = pipe_ctx->ratios.vert;
-+	pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
-+	pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
- 
--	if (pipe_ctx->format == PIXEL_FORMAT_420BPP12) {
--		pipe_ctx->ratios.horz_c.value /= 2;
--		pipe_ctx->ratios.vert_c.value /= 2;
--	} else if (pipe_ctx->format == PIXEL_FORMAT_422BPP16) {
--		pipe_ctx->ratios.horz_c.value /= 2;
-+	if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12) {
-+		pipe_ctx->scl_data.ratios.horz_c.value /= 2;
-+		pipe_ctx->scl_data.ratios.vert_c.value /= 2;
-+	} else if (pipe_ctx->scl_data.format == PIXEL_FORMAT_422BPP16) {
-+		pipe_ctx->scl_data.ratios.horz_c.value /= 2;
- 	}
- }
- 
-@@ -348,7 +348,7 @@ void build_scaling_params(
- 	 * overscan calculation requires scaling ratios and viewport
- 	 * and lb depth/taps calculation requires overscan. Call sequence
- 	 * is therefore important */
--	pipe_ctx->format = convert_pixel_format_to_dalsurface(surface->format);
-+	pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(surface->format);
- 
- 	calculate_viewport(surface, pipe_ctx);
- 
-@@ -357,25 +357,25 @@ void build_scaling_params(
- 	calculate_overscan(surface, pipe_ctx);
- 
- 	/* Check if scaling is required update taps if not */
--	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.horz) == 1 << 19)
--		pipe_ctx->taps.h_taps = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->scl_data.ratios.horz) == 1 << 19)
-+		pipe_ctx->scl_data.taps.h_taps = 1;
- 	else
--		pipe_ctx->taps.h_taps = surface->scaling_quality.h_taps;
-+		pipe_ctx->scl_data.taps.h_taps = surface->scaling_quality.h_taps;
- 
--	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.horz_c) == 1 << 19)
--		pipe_ctx->taps.h_taps_c = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->scl_data.ratios.horz_c) == 1 << 19)
-+		pipe_ctx->scl_data.taps.h_taps_c = 1;
- 	else
--		pipe_ctx->taps.h_taps_c = surface->scaling_quality.h_taps_c;
-+		pipe_ctx->scl_data.taps.h_taps_c = surface->scaling_quality.h_taps_c;
- 
--	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.vert) == 1 << 19)
--		pipe_ctx->taps.v_taps = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->scl_data.ratios.vert) == 1 << 19)
-+		pipe_ctx->scl_data.taps.v_taps = 1;
- 	else
--		pipe_ctx->taps.v_taps = surface->scaling_quality.v_taps;
-+		pipe_ctx->scl_data.taps.v_taps = surface->scaling_quality.v_taps;
- 
--	if (dal_fixed31_32_u2d19(pipe_ctx->ratios.vert_c) == 1 << 19)
--		pipe_ctx->taps.v_taps_c = 1;
-+	if (dal_fixed31_32_u2d19(pipe_ctx->scl_data.ratios.vert_c) == 1 << 19)
-+		pipe_ctx->scl_data.taps.v_taps_c = 1;
- 	else
--		pipe_ctx->taps.v_taps_c = surface->scaling_quality.v_taps_c;
-+		pipe_ctx->scl_data.taps.v_taps_c = surface->scaling_quality.v_taps_c;
- 
- 	dal_logger_write(pipe_ctx->stream->ctx->logger,
- 				LOG_MAJOR_DCP,
-@@ -385,14 +385,14 @@ void build_scaling_params(
- 				"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
- 				"y:%d\n",
- 				__func__,
--				pipe_ctx->overscan.bottom,
--				pipe_ctx->overscan.left,
--				pipe_ctx->overscan.right,
--				pipe_ctx->overscan.top,
--				pipe_ctx->viewport.height,
--				pipe_ctx->viewport.width,
--				pipe_ctx->viewport.x,
--				pipe_ctx->viewport.y,
-+				pipe_ctx->scl_data.overscan.bottom,
-+				pipe_ctx->scl_data.overscan.left,
-+				pipe_ctx->scl_data.overscan.right,
-+				pipe_ctx->scl_data.overscan.top,
-+				pipe_ctx->scl_data.viewport.height,
-+				pipe_ctx->scl_data.viewport.width,
-+				pipe_ctx->scl_data.viewport.x,
-+				pipe_ctx->scl_data.viewport.y,
- 				surface->dst_rect.height,
- 				surface->dst_rect.width,
- 				surface->dst_rect.x,
-@@ -439,13 +439,15 @@ bool attach_surfaces_to_context(
- 		return false;
- 	}
- 
-+
-+	for (i = 0; i < surface_count; i++)
-+		dc_surface_retain(surfaces[i]);
-+	/* Release after retain to account for surfaces remaining the same */
- 	for (i = 0; i < target_status->surface_count; i++)
- 		dc_surface_release(target_status->surfaces[i]);
--
--	for (i = 0; i < surface_count; i++) {
-+	for (i = 0; i < surface_count; i++)
- 		target_status->surfaces[i] = surfaces[i];
--		dc_surface_retain(target_status->surfaces[i]);
--	}
-+
- 	target_status->surface_count = surface_count;
- 
- 	for (i = 0; i < dc_target->stream_count; i++) {
-@@ -503,7 +505,7 @@ static void fill_display_configs(
- 	const struct validate_context *context,
- 	struct dc_pp_display_configuration *pp_display_cfg)
- {
--	uint8_t i, j;
-+	uint8_t i, j, k;
- 	uint8_t num_cfgs = 0;
- 
- 	for (i = 0; i < context->target_count; i++) {
-@@ -516,10 +518,10 @@ static void fill_display_configs(
- 					&pp_display_cfg->disp_configs[num_cfgs];
- 			const struct pipe_ctx *pipe_ctx = NULL;
- 
--			for (j = 0; j < MAX_PIPES; j++)
-+			for (k = 0; k < MAX_PIPES; k++)
- 				if (stream ==
--					context->res_ctx.pipe_ctx[j].stream) {
--					pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+					context->res_ctx.pipe_ctx[k].stream) {
-+					pipe_ctx = &context->res_ctx.pipe_ctx[k];
- 					break;
- 				}
- 
-@@ -1272,6 +1274,18 @@ static void set_vendor_info_packet(struct core_stream *stream,
- 	info_packet->valid = true;
- }
- 
-+void destruct_val_ctx(struct validate_context *context)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		for (j = 0; j < context->target_status[i].surface_count; j++)
-+			dc_surface_release(
-+				context->target_status[i].surfaces[j]);
-+		context->target_status[i].surface_count = 0;
-+	}
-+}
-+
- void build_info_frame(struct pipe_ctx *pipe_ctx)
- {
- 	enum signal_type signal = SIGNAL_TYPE_NONE;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 6b778d8..dc9f157 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -65,19 +65,7 @@ static void construct(
- 
- static void destruct(struct core_target *core_target)
- {
--	int i, j;
--	struct validate_context *context =
--				&core_target->ctx->dc->current_context;
--
--	for (i = 0; i < context->target_count; i++) {
--		if (context->targets[i] != core_target)
--			continue;
--		for (j = 0; j < context->target_status[i].surface_count; j++)
--			dc_surface_release(
--				context->target_status[i].surfaces[j]);
--		context->target_status[i].surface_count = 0;
--		break;
--	}
-+	int i;
- 
- 	for (i = 0; i < core_target->public.stream_count; i++) {
- 		dc_stream_release(
-@@ -148,30 +136,45 @@ target_alloc_fail:
- 	return NULL;
- }
- 
--static bool validate_surface_address(
--		struct dc_plane_address address)
-+static int8_t acquire_first_free_underlay(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
- {
--	bool is_valid_address = false;
--
--	switch (address.type) {
--	case PLN_ADDR_TYPE_GRAPHICS:
--		if (address.grph.addr.quad_part != 0)
--			is_valid_address = true;
--		break;
--	case PLN_ADDR_TYPE_GRPH_STEREO:
--		if ((address.grph_stereo.left_addr.quad_part != 0) &&
--			(address.grph_stereo.right_addr.quad_part != 0)) {
--			is_valid_address = true;
-+	BREAK_TO_DEBUGGER();
-+	if (!res_ctx->pipe_ctx[3].stream) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX];
-+
-+		pipe_ctx->tg = res_ctx->pool.timing_generators[DCE110_UNDERLAY_IDX];
-+		pipe_ctx->mi = res_ctx->pool.mis[DCE110_UNDERLAY_IDX];
-+		/*pipe_ctx->ipp = res_ctx->pool.ipps[DCE110_UNDERLAY_IDX];*/
-+		pipe_ctx->xfm = res_ctx->pool.transforms[DCE110_UNDERLAY_IDX];
-+		pipe_ctx->opp = res_ctx->pool.opps[DCE110_UNDERLAY_IDX];
-+		pipe_ctx->dis_clk = res_ctx->pool.display_clock;
-+		pipe_ctx->pipe_idx = DCE110_UNDERLAY_IDX;
-+
-+		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
-+			dm_error("DC: failed to blank crtc!\n");
-+			BREAK_TO_DEBUGGER();
-+		} else
-+			pipe_ctx->flags.blanked = true;
-+
-+		pipe_ctx->tg->funcs->program_timing(
-+				pipe_ctx->tg,
-+				&stream->public.timing,
-+				true);
-+
-+		if (!pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
-+			BREAK_TO_DEBUGGER();
- 		}
--		break;
--	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
--	default:
--		/* not supported */
--		BREAK_TO_DEBUGGER();
--		break;
--	}
- 
--	return is_valid_address;
-+		pipe_ctx->tg->funcs->set_blank_color(
-+				pipe_ctx->tg,
-+				COLOR_SPACE_SRGB_FULL_RANGE);/* TODO unhardcode*/
-+
-+		pipe_ctx->stream = stream;
-+		return DCE110_UNDERLAY_IDX;
-+	}
-+	return -1;
- }
- 
- bool dc_commit_surfaces_to_target(
-@@ -184,7 +187,7 @@ bool dc_commit_surfaces_to_target(
- 	int i, j;
- 	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	struct dc_target_status *status = NULL;
-+	struct dc_target_status *target_status = NULL;
- 	struct validate_context *context;
- 	int current_enabled_surface_count = 0;
- 	int new_enabled_surface_count = 0;
-@@ -196,7 +199,7 @@ bool dc_commit_surfaces_to_target(
- 	for (i = 0; i < context->target_count; i++)
- 		if (target == context->targets[i])
- 			break;
--	status = &context->target_status[i];
-+	target_status = &context->target_status[i];
- 	if (!dal_adapter_service_is_in_accelerated_mode(
- 						dc->res_pool.adapter_srv)
- 		|| i == context->target_count) {
-@@ -204,14 +207,23 @@ bool dc_commit_surfaces_to_target(
- 		goto unexpected_fail;
- 	}
- 
--	for (i = 0; i < status->surface_count; i++)
--		if (status->surfaces[i]->visible)
-+	for (i = 0; i < target_status->surface_count; i++)
-+		if (target_status->surfaces[i]->visible)
- 			current_enabled_surface_count++;
- 
- 	for (i = 0; i < new_surface_count; i++)
- 		if (new_surfaces[i]->visible)
- 			new_enabled_surface_count++;
- 
-+	/* TODO unhack mpo */
-+	if (new_surface_count == 2 && target_status->surface_count < 2)
-+		acquire_first_free_underlay(&context->res_ctx,
-+				DC_STREAM_TO_CORE(dc_target->streams[0]));
-+	else if (new_surface_count < 2 && target_status->surface_count == 2) {
-+		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].stream = NULL;
-+		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].surface = NULL;
-+	}
-+
- 	dal_logger_write(dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC,
-@@ -280,24 +292,20 @@ bool dc_commit_surfaces_to_target(
- 						dc_surface->dst_rect.width,
- 						dc_surface->dst_rect.height);
- 
--		if (surface->public.gamma_correction)
--			gamma = DC_GAMMA_TO_CORE(
-+			if (surface->public.gamma_correction)
-+				gamma = DC_GAMMA_TO_CORE(
- 					surface->public.gamma_correction);
- 
--		dc->hwss.set_gamma_correction(
--				pipe_ctx->ipp,
--				pipe_ctx->opp,
--			gamma, surface);
--
--			dc->hwss.set_plane_config(dc, surface, pipe_ctx);
-+			dc->hwss.set_gamma_correction(
-+					pipe_ctx->ipp,
-+					pipe_ctx->opp,
-+					gamma, surface);
- 
--			if (validate_surface_address(dc_surface->address))
--				dc->hwss.update_plane_addrs(
--					dc, &context->res_ctx, surface);
-+			dc->hwss.set_plane_config(
-+				dc, pipe_ctx, &context->res_ctx);
- 		}
- 
--	if (current_enabled_surface_count == 0 && new_enabled_surface_count > 0)
--		dc_target_enable_memory_requests(dc_target);
-+	dc->hwss.update_plane_addrs(dc, &context->res_ctx);
- 
- 	/* Lower display clock if necessary */
- 	if (prev_disp_clk > context->bw_results.dispclk_khz) {
-@@ -311,11 +319,9 @@ bool dc_commit_surfaces_to_target(
- 	return true;
- 
- unexpected_fail:
--	for (i = 0; i < new_surface_count; i++) {
--		status->surfaces[i] = NULL;
--	}
--	status->surface_count = 0;
- 
-+	destruct_val_ctx(context);
-+	dm_free(dc->ctx, context);
- 	return false;
- }
- 
-@@ -350,7 +356,8 @@ void dc_target_enable_memory_requests(struct dc_target *dc_target)
- 			if (!tg->funcs->set_blank(tg, false)) {
- 				dm_error("DC: failed to unblank crtc!\n");
- 				BREAK_TO_DEBUGGER();
--			}
-+			} else
-+				res_ctx->pipe_ctx[j].flags.blanked = false;
- 		}
- 	}
- }
-@@ -373,7 +380,8 @@ void dc_target_disable_memory_requests(struct dc_target *dc_target)
- 			if (!tg->funcs->set_blank(tg, true)) {
- 				dm_error("DC: failed to blank crtc!\n");
- 				BREAK_TO_DEBUGGER();
--			}
-+			} else
-+				res_ctx->pipe_ctx[j].flags.blanked = true;
- 		}
- 	}
- }
-@@ -408,6 +416,9 @@ bool dc_target_set_cursor_attributes(
- 			struct input_pixel_processor *ipp =
- 						res_ctx->pipe_ctx[j].ipp;
- 
-+			if (j == DCE110_UNDERLAY_IDX)
-+				continue;
-+
- 			if (res_ctx->pipe_ctx[j].stream !=
- 				DC_STREAM_TO_CORE(target->public.streams[i]))
- 				continue;
-@@ -451,6 +462,9 @@ bool dc_target_set_cursor_position(
- 			struct input_pixel_processor *ipp =
- 						res_ctx->pipe_ctx[j].ipp;
- 
-+			if (j == DCE110_UNDERLAY_IDX)
-+				continue;
-+
- 			if (res_ctx->pipe_ctx[j].stream !=
- 				DC_STREAM_TO_CORE(target->public.streams[i]))
- 				continue;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 4e73ad1..d01a116 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -86,7 +86,7 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- },
- {
--	.dcfe = (mmDCFEV_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcfe = (mmDCFEV_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
- 	.blnd = (mmBLNDV_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- }
-@@ -375,7 +375,10 @@ static void dce110_set_blender_mode(
- 		break;
- 	case BLENDER_MODE_CURRENT_PIPE:
- 	default:
--		feedthrough = 1;
-+		if (controller_id == DCE110_UNDERLAY_IDX)
-+			feedthrough = 0;
-+		else
-+			feedthrough = 1;
- 		blnd_mode = 0;
- 		break;
- 	}
-@@ -453,7 +456,7 @@ static bool dce110_enable_display_power_gating(
- 	else
- 		cntl = ASIC_PIPE_DISABLE;
- 
--	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0))
-+	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0)
- 		bp_result = dcb->funcs->enable_disp_power_gating(
- 						dcb, controller_id + 1, cntl);
- 
-@@ -523,16 +526,19 @@ static bool set_gamma_ramp(
- 
- 	build_prescale_params(prescale_params, surface);
- 
--	ipp->funcs->ipp_program_prescale(ipp, prescale_params);
-+	if (ipp)
-+		ipp->funcs->ipp_program_prescale(ipp, prescale_params);
- 
- 	if (ramp) {
- 		calculate_regamma_params(regamma_params,
- 				temp_params, ramp, surface);
- 		opp->funcs->opp_program_regamma_pwl(opp, regamma_params);
--		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_sRGB);
-+		if (ipp)
-+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_sRGB);
- 		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
- 	} else {
--		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
-+		if (ipp)
-+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
- 		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
- 	}
- 
-@@ -772,6 +778,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
- 		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
-+		pipe_ctx->flags.blanked = true;
-+
- 
- 		/*
- 		 * only disable stream in case it was ever enabled
-@@ -949,6 +957,8 @@ static void disable_vga_and_power_gate_all_controllers(
- 		 * powergating. */
- 		enable_display_pipe_clock_gating(ctx,
- 				true);
-+		if (i == DCE110_UNDERLAY_IDX)
-+			continue;
- 		dc->hwss.enable_display_power_gating(ctx, i, dcb,
- 				PIPE_GATING_CONTROL_ENABLE);
- 	}
-@@ -1138,7 +1148,8 @@ static void set_displaymarks(
- 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- 		uint32_t total_dest_line_time_ns;
- 
--		if (pipe_ctx->stream == NULL)
-+		if (pipe_ctx->stream == NULL
-+			|| pipe_ctx->pipe_idx == DCE110_UNDERLAY_IDX)
- 			continue;
- 
- 		total_dest_line_time_ns = compute_pstate_blackout_duration(
-@@ -1304,38 +1315,6 @@ static bool setup_line_buffer_pixel_depth(
- 	return false;
- }
- 
--static void hw_sequencer_build_scaler_parameter_plane(
--		const struct pipe_ctx *pipe_ctx,
--		struct scaler_data *scaler_data)
--{
--	/*TODO: per pipe not per stream*/
--	/*TODO: get from feature from adapterservice*/
--	scaler_data->flags.bits.SHOW_COLOURED_BORDER = false;
--
--	scaler_data->flags.bits.SHOULD_PROGRAM_ALPHA = 1;
--
--	scaler_data->flags.bits.SHOULD_PROGRAM_VIEWPORT = 0;
--
--	scaler_data->flags.bits.SHOULD_UNLOCK = 0;
--
--	scaler_data->flags.bits.INTERLACED = 0;
--
--	scaler_data->dal_pixel_format = pipe_ctx->format;
--
--	scaler_data->taps = pipe_ctx->taps;
--
--	scaler_data->viewport = pipe_ctx->viewport;
--
--	scaler_data->overscan = pipe_ctx->overscan;
--
--	scaler_data->ratios = &pipe_ctx->ratios;
--
--	/*TODO rotation and adjustment */
--	scaler_data->h_sharpness = 0;
--	scaler_data->v_sharpness = 0;
--
--}
--
- static void set_default_colors(struct pipe_ctx *pipe_ctx)
- {
- 	struct default_adjustment default_adjust = { 0 };
-@@ -1344,7 +1323,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
- 	default_adjust.color_space = get_output_color_space(
- 					&pipe_ctx->stream->public.timing);
- 	default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
--	default_adjust.surface_pixel_format = pipe_ctx->format;
-+	default_adjust.surface_pixel_format = pipe_ctx->scl_data.format;
- 
- 	/* display color depth */
- 	default_adjust.color_depth =
-@@ -1360,28 +1339,17 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
- 					pipe_ctx->opp, &default_adjust);
- }
- 
--static void program_scaler(
--	const struct core_surface *surface,
--	const struct pipe_ctx *pipe_ctx)
-+static void program_scaler(const struct pipe_ctx *pipe_ctx)
- {
--	struct scaler_data scaler_data = { { 0 } };
--
--	hw_sequencer_build_scaler_parameter_plane(
--		pipe_ctx,
--		&scaler_data);
--
- 	setup_line_buffer_pixel_depth(
- 		pipe_ctx,
- 		LB_PIXEL_DEPTH_24BPP,
- 		false);
- 
- 	pipe_ctx->tg->funcs->set_overscan_blank_color(
--		pipe_ctx->tg, surface->public.color_space);
--
--	pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, &scaler_data);
-+		pipe_ctx->tg, pipe_ctx->surface->public.color_space);
- 
--	pipe_ctx->xfm->funcs->transform_update_viewport(
--			pipe_ctx->xfm, &scaler_data.viewport, false);
-+	pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, &pipe_ctx->scl_data);
- }
- 
- /**
-@@ -1390,14 +1358,17 @@ static void program_scaler(
-  */
- static void set_plane_config(
- 	const struct dc *dc,
--	struct core_surface *surface,
--	struct pipe_ctx *pipe_ctx)
-+	struct pipe_ctx *pipe_ctx,
-+	struct resource_context *res_ctx)
- {
-+	int i;
- 	const struct dc_crtc_timing *crtc_timing =
- 				&pipe_ctx->stream->public.timing;
- 	struct mem_input *mi = pipe_ctx->mi;
- 	struct timing_generator *tg = pipe_ctx->tg;
- 	struct dc_context *ctx = pipe_ctx->stream->ctx;
-+	struct core_surface *surface = pipe_ctx->surface;
-+	enum blender_mode blender_mode = BLENDER_MODE_CURRENT_PIPE;
- 
- 	dc->hwss.pipe_control_lock(
- 		ctx, pipe_ctx->pipe_idx, PIPE_LOCK_CONTROL_MODE, false);
-@@ -1419,11 +1390,19 @@ static void set_plane_config(
- 
- 	set_default_colors(pipe_ctx);
- 
--	/* program Scaler */
--	program_scaler(surface, pipe_ctx);
-+	program_scaler(pipe_ctx);
-+
-+	for (i = pipe_ctx->pipe_idx + 1; i < MAX_PIPES; i++)
-+		if (res_ctx->pipe_ctx[i].stream == pipe_ctx->stream) {
-+			if (surface->public.visible)
-+				blender_mode = BLENDER_MODE_BLENDING;
-+			else
-+				blender_mode = BLENDER_MODE_OTHER_PIPE;
-+			break;
-+		}
- 
- 	dc->hwss.set_blender_mode(
--		ctx, pipe_ctx->pipe_idx, BLENDER_MODE_CURRENT_PIPE);
-+		ctx, pipe_ctx->pipe_idx, blender_mode);
- 
- 	mi->funcs->mem_input_program_surface_config(
- 			mi,
-@@ -1431,28 +1410,20 @@ static void set_plane_config(
- 			&surface->public.tiling_info,
- 			&surface->public.plane_size,
- 			surface->public.rotation);
--
--	dc->hwss.pipe_control_lock(
--			ctx,
--			pipe_ctx->pipe_idx,
--			PIPE_LOCK_CONTROL_GRAPHICS |
--			PIPE_LOCK_CONTROL_SCL |
--			PIPE_LOCK_CONTROL_BLENDER |
--			PIPE_LOCK_CONTROL_SURFACE,
--			false);
- }
- 
--static void update_plane_addrs(
--	struct dc *dc,
--	struct resource_context *res_ctx,
--	const struct core_surface *surface)
-+static void update_plane_addrs(struct dc *dc, struct resource_context *res_ctx)
- {
--	uint8_t j;
-+	int j;
- 
--	for (j = 0; j < MAX_PIPES; j++) {
-+	/* Go through pipes in reverse order to avoid underflow on unlock */
-+	for (j = MAX_PIPES - 1; j >= 0; j--) {
- 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j];
-+		struct core_surface *surface = pipe_ctx->surface;
- 
--		if (pipe_ctx->surface != surface)
-+		if (surface == NULL ||
-+			surface->status.requested_address.grph.addr.quad_part
-+			== surface->public.address.grph.addr.quad_part)
- 			continue;
- 
- 		dc->hwss.pipe_control_lock(
-@@ -1466,13 +1437,24 @@ static void update_plane_addrs(
- 			&surface->public.address,
- 			surface->public.flip_immediate);
- 
--		dc->hwss.pipe_control_lock(
--			dc->ctx,
--			j,
--			PIPE_LOCK_CONTROL_SURFACE,
--			false);
-+		surface->status.requested_address = surface->public.address;
- 
--		break;
-+		dc->hwss.pipe_control_lock(
-+					dc->ctx,
-+					pipe_ctx->pipe_idx,
-+					PIPE_LOCK_CONTROL_GRAPHICS |
-+					PIPE_LOCK_CONTROL_SCL |
-+					PIPE_LOCK_CONTROL_BLENDER |
-+					PIPE_LOCK_CONTROL_SURFACE,
-+					false);
-+
-+		if (pipe_ctx->flags.blanked) {
-+			if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false)) {
-+				dm_error("DC: failed to unblank crtc!\n");
-+				BREAK_TO_DEBUGGER();
-+			} else
-+				pipe_ctx->flags.blanked = false;
-+		}
- 	}
- }
- 
-@@ -1483,6 +1465,9 @@ static void reset_single_pipe_hw_ctx(
- {
- 	struct dc_bios *dcb;
- 
-+	if (pipe_ctx->pipe_idx == DCE110_UNDERLAY_IDX)
-+		return;
-+
- 	dcb = dal_adapter_service_get_bios_parser(
- 			context->res_ctx.pool.adapter_srv);
- 	if (pipe_ctx->audio) {
-@@ -1493,8 +1478,13 @@ static void reset_single_pipe_hw_ctx(
- 	}
- 
- 	core_link_disable_stream(pipe_ctx);
--
--	pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
-+	if (!pipe_ctx->flags.blanked) {
-+		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
-+			dm_error("DC: failed to blank crtc!\n");
-+			BREAK_TO_DEBUGGER();
-+		} else
-+			pipe_ctx->flags.blanked = true;
-+	}
- 	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
- 	pipe_ctx->mi->funcs->free_mem_input(
- 				pipe_ctx->mi, context->target_count);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-index 4b9042f..8babd01 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-@@ -57,22 +57,16 @@ struct opp_funcs funcs = {
- 
- 		.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
- 
--		.opp_destroy = dce110_opp_destroy,
-+		.opp_destroy = dce110_opp_destroy
- };
- 
- bool dce110_opp_v_construct(struct dce110_opp *opp110,
--	struct dc_context *ctx,
--	uint32_t inst,
--	const struct dce110_opp_reg_offsets *offsets)
-+	struct dc_context *ctx)
- {
- 	opp110->base.funcs = &funcs;
- 
- 	opp110->base.ctx = ctx;
- 
--	opp110->base.inst = inst;
--
--	opp110->offsets = *offsets;
--
- 	return true;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-index 9543a70..1936ba4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -34,9 +34,7 @@
- struct gamma_parameters;
- 
- bool dce110_opp_v_construct(struct dce110_opp *opp110,
--	struct dc_context *ctx,
--	uint32_t inst,
--	const struct dce110_opp_reg_offsets *offsets);
-+	struct dc_context *ctx);
- 
- /* underlay callbacks */
- void dce110_opp_v_set_csc_default(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 26fc104..26e9df5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -35,11 +35,13 @@
- #include "dce110/dce110_timing_generator_v.h"
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_mem_input.h"
-+#include "dce110/dce110_mem_input_v.h"
- #include "dce110/dce110_ipp.h"
- #include "dce110/dce110_transform.h"
- #include "dce110/dce110_transform_v.h"
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
-+#include "dce110/dce110_opp_v.h"
- #include "dce110/dce110_clock_source.h"
- 
- #include "dce/dce_11_0_d.h"
-@@ -307,14 +309,8 @@ static struct timing_generator *dce110_timing_generator_create(
- 	if (!tg110)
- 		return NULL;
- 
--	if (instance == 3) {
--		/* This is the Underlay instance. */
--		if (dce110_timing_generator_v_construct(tg110, as, ctx))
--			return &tg110->base;
--	} else {
--		if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
--			return &tg110->base;
--	}
-+	if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
-+		return &tg110->base;
- 
- 	BREAK_TO_DEBUGGER();
- 	dm_free(ctx, tg110);
-@@ -378,14 +374,8 @@ static struct transform *dce110_transform_create(
- 	if (!transform)
- 		return NULL;
- 
--	if (inst == 3) {
--		/* Underlay */
--		if (dce110_transform_v_construct(transform, ctx))
--			return &transform->base;
--	} else {
--		if (dce110_transform_construct(transform, ctx, inst, offsets))
--			return &transform->base;
--	}
-+	if (dce110_transform_construct(transform, ctx, inst, offsets))
-+		return &transform->base;
- 
- 	BREAK_TO_DEBUGGER();
- 	dm_free(ctx, transform);
-@@ -683,6 +673,18 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- 	return DC_OK;
- }
- 
-+static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx)
-+{
-+	if (pipe_ctx->pipe_idx != DCE110_UNDERLAY_IDX)
-+		return true;
-+	if (pipe_ctx->surface && pipe_ctx->surface->public.format <
-+					SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+		return false;
-+	if (!pipe_ctx->surface)
-+		return false;
-+	return true;
-+}
-+
- static enum dc_status validate_mapped_resource(
- 		const struct dc *dc,
- 		struct validate_context *context)
-@@ -706,8 +708,11 @@ static enum dc_status validate_mapped_resource(
- 				if (context->res_ctx.pipe_ctx[k].stream != stream)
- 					continue;
- 
-+				if (!is_surface_pixel_format_supported(pipe_ctx))
-+					return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
-+
- 				if (!pipe_ctx->tg->funcs->validate_timing(
--						pipe_ctx->tg, &stream->public.timing))
-+					pipe_ctx->tg, &stream->public.timing))
- 					return DC_FAIL_CONTROLLER_VALIDATE;
- 
- 				status = build_pipe_hw_param(pipe_ctx);
-@@ -762,7 +767,7 @@ enum dc_status dce110_validate_bandwidth(
- 		if (pipe_ctx->stream == NULL)
- 			continue;
- 
--		if (pipe_ctx->ratios.vert.value == 0) {
-+		if (pipe_ctx->scl_data.ratios.vert.value == 0) {
- 			disp->graphics_scale_ratio = bw_int_to_fixed(1);
- 			disp->graphics_h_taps = 2;
- 			disp->graphics_v_taps = 2;
-@@ -778,17 +783,17 @@ enum dc_status dce110_validate_bandwidth(
- 		} else {
- 			disp->graphics_scale_ratio =
- 				fixed31_32_to_bw_fixed(
--					pipe_ctx->ratios.vert.value);
--			disp->graphics_h_taps = pipe_ctx->taps.h_taps;
--			disp->graphics_v_taps = pipe_ctx->taps.v_taps;
-+					pipe_ctx->scl_data.ratios.vert.value);
-+			disp->graphics_h_taps = pipe_ctx->scl_data.taps.h_taps;
-+			disp->graphics_v_taps = pipe_ctx->scl_data.taps.v_taps;
- 
- 			/* TODO: remove when bw formula accepts taps per
- 			 * display
- 			 */
--			if (max_vtaps < pipe_ctx->taps.v_taps)
--				max_vtaps = pipe_ctx->taps.v_taps;
--			if (max_htaps < pipe_ctx->taps.h_taps)
--				max_htaps = pipe_ctx->taps.h_taps;
-+			if (max_vtaps < pipe_ctx->scl_data.taps.v_taps)
-+				max_vtaps = pipe_ctx->scl_data.taps.v_taps;
-+			if (max_htaps < pipe_ctx->scl_data.taps.h_taps)
-+				max_htaps = pipe_ctx->scl_data.taps.h_taps;
- 		}
- 
- 		disp->graphics_src_width =
-@@ -1004,10 +1009,16 @@ enum dc_status dce110_validate_with_context(
- 						== context->targets[i]) {
- 				unchanged = true;
- 				set_target_unchanged(context, i);
-+				attach_surfaces_to_context(
-+					(struct dc_surface **)dc->current_context.
-+						target_status[j].surfaces,
-+					dc->current_context.target_status[j].surface_count,
-+					&context->targets[i]->public,
-+					context);
- 				context->target_status[i] =
- 					dc->current_context.target_status[j];
- 			}
--		if (!unchanged)
-+		if (!unchanged || set[i].surface_count != 0)
- 			if (!attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
-@@ -1045,6 +1056,29 @@ static struct resource_funcs dce110_res_pool_funcs = {
- 	.validate_bandwidth = dce110_validate_bandwidth
- };
- 
-+static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
-+{
-+	struct dce110_timing_generator *dce110_tgv = dm_alloc(ctx, sizeof (*dce110_tgv));
-+	struct dce110_transform *dce110_xfmv = dm_alloc(ctx, sizeof (*dce110_xfmv));
-+	struct dce110_mem_input *dce110_miv = dm_alloc(ctx, sizeof (*dce110_miv));
-+	struct dce110_opp *dce110_oppv = dm_alloc(ctx, sizeof (*dce110_oppv));
-+
-+	dce110_opp_v_construct(dce110_oppv, ctx);
-+	dce110_timing_generator_v_construct(dce110_tgv, pool->adapter_srv, ctx);
-+	dce110_mem_input_v_construct(dce110_miv, ctx);
-+	dce110_transform_v_construct(dce110_xfmv, ctx);
-+
-+	pool->opps[pool->pipe_count] = &dce110_oppv->base;
-+	pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
-+	pool->mis[pool->pipe_count] = &dce110_miv->base;
-+	pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
-+
-+	pool->transforms[pool->pipe_count]->funcs->transform_set_scaler_filter(
-+			pool->transforms[pool->pipe_count],
-+			pool->scaler_filter);
-+	pool->pipe_count++;
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *as,
- 	uint8_t num_virtual_links,
-@@ -1177,6 +1211,8 @@ bool dce110_construct_resource_pool(
- 			goto controller_create_fail;
- 		}
- 	}
-+	/* TODO: failure? */
-+	underlay_create(ctx, pool);
- 
- 	audio_init_data.as = as;
- 	audio_init_data.ctx = ctx;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-index 2654a96..dba972f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -47,8 +47,6 @@ static struct transform_funcs dce110_transform_funcs = {
- 		dce110_transform_set_scaler,
- 	.transform_set_scaler_bypass =
- 		dce110_transform_set_scaler_bypass,
--	.transform_update_viewport =
--		dce110_transform_update_viewport,
- 	.transform_set_scaler_filter =
- 		dce110_transform_set_scaler_filter,
- 	.transform_set_gamut_remap =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index 7c15a13..4a5d54c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -64,16 +64,14 @@ static void disable_enhanced_sharpness(struct dce110_transform *xfm110)
- 			SCL_REG(mmSCL_F_SHARP_CONTROL), value);
- }
- 
--/**
--* Function:
--* void setup_scaling_configuration
--*
--* Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
--* Input:   data
--*
--* Output:
--   void
--*/
-+/*
-+ *	@Function:
-+ *		void setup_scaling_configuration
-+ *	@Purpose: setup scaling mode : bypass, RGb, YCbCr and number of taps
-+ *	@Input:   data
-+ *
-+ *	@Output: void
-+ */
- static bool setup_scaling_configuration(
- 	struct dce110_transform *xfm110,
- 	const struct scaler_data *data)
-@@ -82,45 +80,44 @@ static bool setup_scaling_configuration(
- 	uint32_t addr;
- 	uint32_t value;
- 
-+	addr = SCL_REG(mmSCL_BYPASS_CONTROL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		SCL_BYPASS_CONTROL,
-+		SCL_BYPASS_MODE);
-+	dm_write_reg(ctx, addr, value);
-+
- 	if (data->taps.h_taps + data->taps.v_taps <= 2) {
- 		dce110_transform_set_scaler_bypass(&xfm110->base);
- 		return false;
- 	}
- 
--	{
--		addr = SCL_REG(mmSCL_MODE);
--		value = dm_read_reg(ctx, addr);
--
--		if (data->dal_pixel_format <= PIXEL_FORMAT_GRPH_END)
--			set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
--		else
--			set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
--
--		set_reg_field_value(value, 1, SCL_MODE, SCL_PSCL_EN);
-+	addr = SCL_REG(mmSCL_MODE);
-+	value = dm_read_reg(ctx, addr);
-+	if (data->format <= PIXEL_FORMAT_GRPH_END)
-+		set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
-+	else
-+		set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
-+	set_reg_field_value(value, 1, SCL_MODE, SCL_PSCL_EN);
-+	dm_write_reg(ctx, addr, value);
- 
--		dm_write_reg(ctx, addr, value);
--	}
--	{
--		addr = SCL_REG(mmSCL_TAP_CONTROL);
--		value = dm_read_reg(ctx, addr);
- 
--		set_reg_field_value(value, data->taps.h_taps - 1,
--				SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+	addr = SCL_REG(mmSCL_TAP_CONTROL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(value, data->taps.h_taps - 1,
-+			SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+	set_reg_field_value(value, data->taps.v_taps - 1,
-+			SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+	dm_write_reg(ctx, addr, value);
- 
--		set_reg_field_value(value, data->taps.v_taps - 1,
--				SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
- 
--		dm_write_reg(ctx, addr, value);
--	}
--	{
--		addr = SCL_REG(mmSCL_CONTROL);
--		value = dm_read_reg(ctx, addr);
--		 /* 1 - Replaced out of bound pixels with edge */
--		set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
--
--		/* 1 - Replaced out of bound pixels with the edge pixel. */
--		dm_write_reg(ctx, addr, value);
--	}
-+	addr = SCL_REG(mmSCL_CONTROL);
-+	value = dm_read_reg(ctx, addr);
-+	 /* 1 - Replaced out of bound pixels with edge */
-+	set_reg_field_value(value, 1, SCL_CONTROL, SCL_BOUNDARY_MODE);
-+	dm_write_reg(ctx, addr, value);
- 
- 	return true;
- }
-@@ -425,7 +422,7 @@ static bool program_multi_taps_filter(
- 
- 	if (horizontal) {
- 		filter_params.taps = data->taps.h_taps;
--		filter_params.sharpness = data->h_sharpness;
-+		filter_params.sharpness = 0; /* TODO */
- 		filter_params.flags.bits.HORIZONTAL = 1;
- 
- 		src_size = data->viewport.width;
-@@ -434,12 +431,12 @@ static bool program_multi_taps_filter(
- 				dal_fixed31_32_div(
- 					dal_fixed31_32_from_int(
- 						data->viewport.width),
--					data->ratios->horz));
-+					data->ratios.horz));
- 
- 		filter_type = FILTER_TYPE_RGB_Y_HORIZONTAL;
- 	} else {
- 		filter_params.taps = data->taps.v_taps;
--		filter_params.sharpness = data->v_sharpness;
-+		filter_params.sharpness = 0; /* TODO */
- 		filter_params.flags.bits.HORIZONTAL = 0;
- 
- 		src_size = data->viewport.height;
-@@ -448,7 +445,7 @@ static bool program_multi_taps_filter(
- 				dal_fixed31_32_div(
- 					dal_fixed31_32_from_int(
- 						data->viewport.height),
--					data->ratios->vert));
-+					data->ratios.vert));
- 
- 		filter_type = FILTER_TYPE_RGB_Y_VERTICAL;
- 	}
-@@ -478,20 +475,18 @@ static bool program_multi_taps_filter(
- 		filter_data,
- 		filter_data_size);
- 
--	/* 4. Program the alpha if necessary */
--	if (data->flags.bits.SHOULD_PROGRAM_ALPHA) {
--		if (horizontal)
--			filter_type = FILTER_TYPE_ALPHA_HORIZONTAL;
--		else
--			filter_type = FILTER_TYPE_ALPHA_VERTICAL;
--
--		program_filter(
--			xfm110,
--			filter_type,
--			&filter_params,
--			filter_data,
--			filter_data_size);
--	}
-+	/* 4. Program the alpha*/
-+	if (horizontal)
-+		filter_type = FILTER_TYPE_ALPHA_HORIZONTAL;
-+	else
-+		filter_type = FILTER_TYPE_ALPHA_VERTICAL;
-+
-+	program_filter(
-+		xfm110,
-+		filter_type,
-+		&filter_params,
-+		filter_data,
-+		filter_data_size);
- 
- 	return true;
- }
-@@ -542,18 +537,16 @@ static void calculate_inits(
- {
- 	struct fixed31_32 h_init;
- 	struct fixed31_32 v_init;
--	struct fixed31_32 v_init_bot;
- 
--	inits->bottom_enable = 0;
- 	inits->h_int_scale_ratio =
--		dal_fixed31_32_u2d19(data->ratios->horz) << 5;
-+		dal_fixed31_32_u2d19(data->ratios.horz) << 5;
- 	inits->v_int_scale_ratio =
--		dal_fixed31_32_u2d19(data->ratios->vert) << 5;
-+		dal_fixed31_32_u2d19(data->ratios.vert) << 5;
- 
- 	h_init =
- 		dal_fixed31_32_div_int(
- 			dal_fixed31_32_add(
--				data->ratios->horz,
-+				data->ratios.horz,
- 				dal_fixed31_32_from_int(data->taps.h_taps + 1)),
- 				2);
- 	inits->h_init.integer = dal_fixed31_32_floor(h_init);
-@@ -562,28 +555,11 @@ static void calculate_inits(
- 	v_init =
- 		dal_fixed31_32_div_int(
- 			dal_fixed31_32_add(
--				data->ratios->vert,
-+				data->ratios.vert,
- 				dal_fixed31_32_from_int(data->taps.v_taps + 1)),
- 				2);
- 	inits->v_init.integer = dal_fixed31_32_floor(v_init);
- 	inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
--
--	if (data->flags.bits.INTERLACED) {
--		v_init_bot =
--			dal_fixed31_32_add(
--				dal_fixed31_32_div_int(
--					dal_fixed31_32_add(
--						data->ratios->vert,
--						dal_fixed31_32_from_int(
--							data->taps.v_taps + 1)),
--					2),
--				data->ratios->vert);
--		inits->v_init_bottom.integer = dal_fixed31_32_floor(v_init_bot);
--		inits->v_init_bottom.fraction =
--			dal_fixed31_32_u0d19(v_init_bot) << 5;
--
--		inits->bottom_enable = 1;
--	}
- }
- 
- static void program_scl_ratios_inits(
-@@ -637,22 +613,6 @@ static void program_scl_ratios_inits(
- 		SCL_V_INIT_FRAC);
- 	dm_write_reg(xfm110->base.ctx, addr, value);
- 
--	if (inits->bottom_enable) {
--		addr = SCL_REG(mmSCL_VERT_FILTER_INIT_BOT);
--		value = 0;
--		set_reg_field_value(
--			value,
--			inits->v_init_bottom.integer,
--			SCL_VERT_FILTER_INIT_BOT,
--			SCL_V_INIT_INT_BOT);
--		set_reg_field_value(
--			value,
--			inits->v_init_bottom.fraction,
--			SCL_VERT_FILTER_INIT_BOT,
--			SCL_V_INIT_FRAC_BOT);
--		dm_write_reg(xfm110->base.ctx, addr, value);
--	}
--
- 	addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
- 	value = 0;
- 	set_reg_field_value(
-@@ -668,38 +628,6 @@ static void program_scl_ratios_inits(
- 	dm_write_reg(xfm110->base.ctx, addr, value);
- }
- 
--static void get_viewport(
--		struct dce110_transform *xfm110,
--		struct rect *current_view_port)
--{
--	uint32_t value_start;
--	uint32_t value_size;
--
--	if (current_view_port == NULL)
--		return;
--
--	value_start = dm_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_START));
--	value_size = dm_read_reg(xfm110->base.ctx, SCL_REG(mmVIEWPORT_SIZE));
--
--	current_view_port->x = get_reg_field_value(
--			value_start,
--			VIEWPORT_START,
--			VIEWPORT_X_START);
--	current_view_port->y = get_reg_field_value(
--			value_start,
--			VIEWPORT_START,
--			VIEWPORT_Y_START);
--	current_view_port->height = get_reg_field_value(
--			value_size,
--			VIEWPORT_SIZE,
--			VIEWPORT_HEIGHT);
--	current_view_port->width = get_reg_field_value(
--			value_size,
--			VIEWPORT_SIZE,
--			VIEWPORT_WIDTH);
--}
--
--
- bool dce110_transform_set_scaler(
- 	struct transform *xfm,
- 	const struct scaler_data *data)
-@@ -708,18 +636,6 @@ bool dce110_transform_set_scaler(
- 	bool is_scaling_required;
- 	struct dc_context *ctx = xfm->ctx;
- 
--	{
--		uint32_t addr = SCL_REG(mmSCL_BYPASS_CONTROL);
--		uint32_t value = dm_read_reg(xfm->ctx, addr);
--
--		set_reg_field_value(
--			value,
--			0,
--			SCL_BYPASS_CONTROL,
--			SCL_BYPASS_MODE);
--		dm_write_reg(xfm->ctx, addr, value);
--	}
--
- 	disable_enhanced_sharpness(xfm110);
- 
- 	/* 3. Program overscan */
-@@ -764,6 +680,9 @@ bool dce110_transform_set_scaler(
- 			program_two_taps_filter(xfm110, true, false);
- 	}
- 
-+	/* 7. Program the viewport */
-+	program_viewport(xfm110, &data->viewport);
-+
- 	return true;
- }
- 
-@@ -780,35 +699,6 @@ void dce110_transform_set_scaler_bypass(struct transform *xfm)
- 	dm_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
- }
- 
--bool dce110_transform_update_viewport(
--	struct transform *xfm,
--	const struct rect *view_port,
--	bool is_fbc_attached)
--{
--	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
--	bool program_req = false;
--	struct rect current_view_port;
--
--	if (view_port == NULL)
--		return program_req;
--
--	get_viewport(xfm110, &current_view_port);
--
--	if (current_view_port.x != view_port->x ||
--			current_view_port.y != view_port->y ||
--			current_view_port.height != view_port->height ||
--			current_view_port.width != view_port->width)
--		program_req = true;
--
--	if (program_req) {
--		/*underlay viewport is programmed with scaler
--		 *program_viewport function pointer is not exposed*/
--		program_viewport(xfm110, view_port);
--	}
--
--	return program_req;
--}
--
- void dce110_transform_set_scaler_filter(
- 	struct transform *xfm,
- 	struct scaler_filter *filter)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index 6491435..aef17b3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -39,7 +39,6 @@
- 
- 
- struct sclv_ratios_inits {
--	uint32_t chroma_enable;
- 	uint32_t h_int_scale_ratio_luma;
- 	uint32_t h_int_scale_ratio_chroma;
- 	uint32_t v_int_scale_ratio_luma;
-@@ -48,10 +47,6 @@ struct sclv_ratios_inits {
- 	struct init_int_and_frac h_init_chroma;
- 	struct init_int_and_frac v_init_luma;
- 	struct init_int_and_frac v_init_chroma;
--	struct init_int_and_frac h_init_lumabottom;
--	struct init_int_and_frac h_init_chromabottom;
--	struct init_int_and_frac v_init_lumabottom;
--	struct init_int_and_frac v_init_chromabottom;
- };
- 
- /*
-@@ -80,14 +75,13 @@ static void calculate_viewport(
- 		scl_data->viewport.width - scl_data->viewport.width % 2;
- 	luma_viewport->height =
- 		scl_data->viewport.height - scl_data->viewport.height % 2;
-+	chroma_viewport->x = luma_viewport->x;
-+	chroma_viewport->y = luma_viewport->y;
-+	chroma_viewport->height = luma_viewport->height;
-+	chroma_viewport->width = luma_viewport->width;
- 
- 
--	if (scl_data->dal_pixel_format == PIXEL_FORMAT_422BPP16) {
--		luma_viewport->width += luma_viewport->width % 2;
--
--		chroma_viewport->x = luma_viewport->x / 2;
--		chroma_viewport->width = luma_viewport->width / 2;
--	} else if (scl_data->dal_pixel_format == PIXEL_FORMAT_420BPP12) {
-+	if (scl_data->format == PIXEL_FORMAT_420BPP12) {
- 		luma_viewport->height += luma_viewport->height % 2;
- 		luma_viewport->width += luma_viewport->width % 2;
- 		/*for 420 video chroma is 1/4 the area of luma, scaled
-@@ -169,24 +163,8 @@ static void program_viewport(
- 			VIEWPORT_WIDTH_C);
- 		dm_write_reg(ctx, addr, value);
- 	}
--	/* TODO: add stereo support */
- }
- 
--
--/*
-- * Until and For MPO video play story, to reduce time for implementation,
-- * below limits are applied for now: 2_TAPS only
-- * Use auto-calculated filter values
-- * Following routines will be empty for now:
-- *
-- * programSclRatiosInits -- calcualate scaler ratio manually
-- * calculateInits --- calcualate scaler ratio manually
-- * programFilter -- multi-taps
-- * GetOptimalNumberOfTaps -- will hard coded to 2 TAPS
-- * GetNextLowerNumberOfTaps -- will hard coded to 2TAPS
-- * validateRequestedScaleRatio - used by GetOptimalNumberOfTaps internally
-- */
--
- /*
-  * Function:
-  * void setup_scaling_configuration
-@@ -218,8 +196,8 @@ static bool setup_scaling_configuration(
- 		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C);
- 		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C);
- 		is_scaling_needed = true;
--	} else if (data->dal_pixel_format != PIXEL_FORMAT_420BPP12 &&
--		data->dal_pixel_format != PIXEL_FORMAT_422BPP16) {
-+	} else if (data->format != PIXEL_FORMAT_420BPP12 &&
-+		data->format != PIXEL_FORMAT_422BPP16) {
- 		set_reg_field_value(
- 			value,
- 			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
-@@ -236,39 +214,25 @@ static bool setup_scaling_configuration(
- 	}
- 	dm_write_reg(ctx, mmSCLV_MODE, value);
- 
--	{
--		value = dm_read_reg(ctx, mmSCLV_TAP_CONTROL);
--
--		set_reg_field_value(value, data->taps.h_taps - 1,
--				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
--
--		set_reg_field_value(value, data->taps.v_taps - 1,
--				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
--
--		set_reg_field_value(value, data->taps.h_taps_c - 1,
--				SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C);
--
--		set_reg_field_value(value, data->taps.v_taps_c - 1,
--				SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
--
--		dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
--	}
--
--	{
--		/*
--		 * we can ignore this register because we are ok with hw
--		 * default 0 -- change to 1 according to dal2 code
--		 */
--		value = dm_read_reg(ctx, mmSCLV_CONTROL);
--		 /*
--		  * 0 - Replaced out of bound pixels with black pixel
--		  * (or any other required color)
--		  */
--		set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
--
--		/* 1 - Replaced out of bound pixels with the edge pixel. */
--		dm_write_reg(ctx, mmSCLV_CONTROL, value);
--	}
-+	value = 0;
-+	set_reg_field_value(value, data->taps.h_taps - 1,
-+			SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+	set_reg_field_value(value, data->taps.v_taps - 1,
-+			SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+	set_reg_field_value(value, data->taps.h_taps_c - 1,
-+			SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C);
-+	set_reg_field_value(value, data->taps.v_taps_c - 1,
-+			SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
-+	dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
-+
-+	value = 0;
-+	/*
-+	 * 0 - Replaced out of bound pixels with black pixel
-+	 * (or any other required color)
-+	 * 1 - Replaced out of bound pixels with the edge pixel
-+	 */
-+	set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
-+	dm_write_reg(ctx, mmSCLV_CONTROL, value);
- 
- 	return is_scaling_needed;
- }
-@@ -379,17 +343,20 @@ static void calculate_inits(
- 	struct rect *luma_viewport,
- 	struct rect *chroma_viewport)
- {
--	if (data->dal_pixel_format == PIXEL_FORMAT_420BPP12 ||
--		data->dal_pixel_format == PIXEL_FORMAT_422BPP16)
--		inits->chroma_enable = true;
--
--	/* TODO: implement rest of this function properly */
--	if (inits->chroma_enable) {
--		inits->h_int_scale_ratio_luma = 0x1000000;
--		inits->v_int_scale_ratio_luma = 0x1000000;
--		inits->h_int_scale_ratio_chroma = 0x800000;
--		inits->v_int_scale_ratio_chroma = 0x800000;
--	}
-+	inits->h_int_scale_ratio_luma =
-+		dal_fixed31_32_u2d19(data->ratios.horz) << 5;
-+	inits->v_int_scale_ratio_luma =
-+		dal_fixed31_32_u2d19(data->ratios.vert) << 5;
-+	inits->h_int_scale_ratio_chroma =
-+		dal_fixed31_32_u2d19(data->ratios.horz_c) << 5;
-+	inits->v_int_scale_ratio_chroma =
-+		dal_fixed31_32_u2d19(data->ratios.vert_c) << 5;
-+
-+	inits->h_init_luma.integer = 1;
-+	inits->v_init_luma.integer = 1;
-+	inits->h_init_chroma.integer = 1;
-+	inits->v_init_chroma.integer = 1;
-+
- }
- 
- static void program_scl_ratios_inits(
-@@ -398,7 +365,7 @@ static void program_scl_ratios_inits(
- {
- 	struct dc_context *ctx = xfm110->base.ctx;
- 	uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;
--	uint32_t value = dm_read_reg(ctx, addr);
-+	uint32_t value = 0;
- 
- 	set_reg_field_value(
- 		value,
-@@ -408,7 +375,7 @@ static void program_scl_ratios_inits(
- 	dm_write_reg(ctx, addr, value);
- 
- 	addr = mmSCLV_VERT_FILTER_SCALE_RATIO;
--	value = dm_read_reg(ctx, addr);
-+	value = 0;
- 	set_reg_field_value(
- 		value,
- 		inits->v_int_scale_ratio_luma,
-@@ -416,8 +383,9 @@ static void program_scl_ratios_inits(
- 		SCL_V_SCALE_RATIO);
- 	dm_write_reg(ctx, addr, value);
- 
-+
- 	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
--	value = dm_read_reg(ctx, addr);
-+	value = 0;
- 	set_reg_field_value(
- 		value,
- 		inits->h_int_scale_ratio_chroma,
-@@ -426,13 +394,71 @@ static void program_scl_ratios_inits(
- 	dm_write_reg(ctx, addr, value);
- 
- 	addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C;
--	value = dm_read_reg(ctx, addr);
-+	value = 0;
- 	set_reg_field_value(
- 		value,
- 		inits->v_int_scale_ratio_chroma,
- 		SCLV_VERT_FILTER_SCALE_RATIO_C,
- 		SCL_V_SCALE_RATIO_C);
- 	dm_write_reg(ctx, addr, value);
-+
-+
-+	addr = mmSCLV_HORZ_FILTER_INIT;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_luma.fraction,
-+		SCLV_HORZ_FILTER_INIT,
-+		SCL_H_INIT_FRAC);
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_luma.integer,
-+		SCLV_HORZ_FILTER_INIT,
-+		SCL_H_INIT_INT);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_INIT;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_luma.fraction,
-+		SCLV_VERT_FILTER_INIT,
-+		SCL_V_INIT_FRAC);
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_luma.integer,
-+		SCLV_VERT_FILTER_INIT,
-+		SCL_V_INIT_INT);
-+	dm_write_reg(ctx, addr, value);
-+
-+
-+	addr = mmSCLV_HORZ_FILTER_INIT_C;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_chroma.fraction,
-+		SCLV_HORZ_FILTER_INIT_C,
-+		SCL_H_INIT_FRAC_C);
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_chroma.integer,
-+		SCLV_HORZ_FILTER_INIT_C,
-+		SCL_H_INIT_INT_C);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_INIT_C;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_chroma.fraction,
-+		SCLV_VERT_FILTER_INIT_C,
-+		SCL_V_INIT_FRAC_C);
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_chroma.integer,
-+		SCLV_VERT_FILTER_INIT_C,
-+		SCL_V_INIT_INT_C);
-+	dm_write_reg(ctx, addr, value);
- }
- 
- static void dce110_transform_v_set_scalerv_bypass(struct transform *xfm)
-@@ -447,34 +473,32 @@ static void dce110_transform_v_set_scalerv_bypass(struct transform *xfm)
- 	dm_write_reg(xfm->ctx, addr, value);
- }
- 
--/* TODO: sync this one with DAL2 */
- static bool dce110_transform_v_set_scaler(
- 	struct transform *xfm,
- 	const struct scaler_data *data)
- {
- 	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
--	bool is_scaling_required;
-+	bool is_scaling_required = false;
-+	bool filter_updated = false;
- 	struct rect luma_viewport = {0};
- 	struct rect chroma_viewport = {0};
- 	struct dc_context *ctx = xfm->ctx;
- 
--	/* 1. Lock Scaler TODO: enable?*/
--	/*set_scaler_update_lock(xfm, true);*/
- 
--	/* 2. Calculate viewport, viewport programming should happen after init
-+	/* 1. Calculate viewport, viewport programming should happen after init
- 	 * calculations as they may require an adjustment in the viewport.
- 	 */
- 
- 	calculate_viewport(data, &luma_viewport, &chroma_viewport);
- 
--	/* 3. Program overscan */
-+	/* 2. Program overscan */
- 	program_overscan(xfm110, &data->overscan);
- 
--	/* 4. Program taps and configuration */
-+	/* 3. Program taps and configuration */
- 	is_scaling_required = setup_scaling_configuration(xfm110, data);
- 
- 	if (is_scaling_required) {
--		/* 5. Calculate and program ratio, filter initialization */
-+		/* 4. Calculate and program ratio, filter initialization */
- 
- 		struct sclv_ratios_inits inits = { 0 };
- 
-@@ -489,7 +513,7 @@ static bool dce110_transform_v_set_scaler(
- 
- 		/*scaler coeff of 2-TAPS use hardware auto calculated value*/
- 
--		/* 6. Program vertical filters */
-+		/* 5. Program vertical filters */
- 		if (data->taps.v_taps > 2) {
- 			program_two_taps_filter_vert(xfm110, false);
- 
-@@ -500,10 +524,11 @@ static bool dce110_transform_v_set_scaler(
- 					"Failed vertical taps programming\n");
- 				return false;
- 			}
-+			filter_updated = true;
- 		} else
- 			program_two_taps_filter_vert(xfm110, true);
- 
--		/* 7. Program horizontal filters */
-+		/* 6. Program horizontal filters */
- 		if (data->taps.h_taps > 2) {
- 			program_two_taps_filter_horz(xfm110, false);
- 
-@@ -514,23 +539,16 @@ static bool dce110_transform_v_set_scaler(
- 					"Failed horizontal taps programming\n");
- 				return false;
- 			}
-+			filter_updated = true;
- 		} else
- 			program_two_taps_filter_horz(xfm110, true);
- 	}
- 
--	/* 8. Program the viewport */
--	if (data->flags.bits.SHOULD_PROGRAM_VIEWPORT)
--		program_viewport(xfm110, &luma_viewport, &chroma_viewport);
--
--	/* 9. Unlock the Scaler TODO: enable?
--	 * Every call to "set_scaler_update_lock(xfm, TRUE)"
--	 * must have a corresponding call to
--	 * "set_scaler_update_lock(xfm, FALSE)" */
--
--	/*set_scaler_update_lock(xfm, false);*/
-+	/* 7. Program the viewport */
-+	program_viewport(xfm110, &luma_viewport, &chroma_viewport);
- 
--	/* TODO: investigate purpose/need of SHOULD_UNLOCK */
--	if (data->flags.bits.SHOULD_UNLOCK == false)
-+	/* 8. Set bit to flip to new coefficient memory */
-+	if (filter_updated)
- 		set_coeff_update_complete(xfm110);
- 
- 	return true;
-@@ -554,104 +572,6 @@ static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
- 	return true;
- }
- 
--static void get_viewport(
--		struct dce110_transform *xfm110,
--		struct rect *current_view_port)
--{
--	uint32_t value_start;
--	uint32_t value_size;
--
--	if (current_view_port == NULL)
--		return;
--
--	value_start = dm_read_reg(xfm110->base.ctx, mmSCLV_VIEWPORT_START);
--	value_size = dm_read_reg(xfm110->base.ctx, mmSCLV_VIEWPORT_SIZE);
--
--	current_view_port->x = get_reg_field_value(
--			value_start,
--			SCLV_VIEWPORT_START,
--			VIEWPORT_X_START);
--	current_view_port->y = get_reg_field_value(
--			value_start,
--			SCLV_VIEWPORT_START,
--			VIEWPORT_Y_START);
--	current_view_port->height = get_reg_field_value(
--			value_size,
--			SCLV_VIEWPORT_SIZE,
--			VIEWPORT_HEIGHT);
--	current_view_port->width = get_reg_field_value(
--			value_size,
--			SCLV_VIEWPORT_SIZE,
--			VIEWPORT_WIDTH);
--}
--
--static void program_luma_viewport(
--	struct dce110_transform *xfm110,
--	const struct rect *view_port)
--{
--	struct dc_context *ctx = xfm110->base.ctx;
--	uint32_t value = 0;
--	uint32_t addr = 0;
--
--	addr = mmSCLV_VIEWPORT_START;
--	value = dm_read_reg(ctx, addr);
--	set_reg_field_value(
--		value,
--		view_port->x,
--		SCLV_VIEWPORT_START,
--		VIEWPORT_X_START);
--	set_reg_field_value(
--		value,
--		view_port->y,
--		SCLV_VIEWPORT_START,
--		VIEWPORT_Y_START);
--	dm_write_reg(ctx, addr, value);
--
--	addr = mmSCLV_VIEWPORT_SIZE;
--	value = dm_read_reg(ctx, addr);
--	set_reg_field_value(
--		value,
--		view_port->height,
--		SCLV_VIEWPORT_SIZE,
--		VIEWPORT_HEIGHT);
--	set_reg_field_value(
--		value,
--		view_port->width,
--		SCLV_VIEWPORT_SIZE,
--		VIEWPORT_WIDTH);
--	dm_write_reg(ctx, addr, value);
--
--	/* TODO: add stereo support */
--}
--
--static bool dce110_transform_v_update_viewport(
--	struct transform *xfm,
--	const struct rect *view_port,
--	bool is_fbc_attached)
--{
--	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
--	bool program_req = false;
--	struct rect current_view_port;
--
--	if (view_port == NULL)
--		return program_req;
--
--	get_viewport(xfm110, &current_view_port);
--
--	if (current_view_port.x != view_port->x ||
--			current_view_port.y != view_port->y ||
--			current_view_port.height != view_port->height ||
--			current_view_port.width != view_port->width)
--		program_req = true;
--
--	if (program_req) {
--		/*underlay viewport is programmed with scaler
--		 *program_viewport function pointer is not exposed*/
--		program_luma_viewport(xfm110, view_port);
--	}
--
--	return program_req;
--}
- 
- static struct transform_funcs dce110_transform_v_funcs = {
- 	.transform_power_up =
-@@ -660,8 +580,6 @@ static struct transform_funcs dce110_transform_v_funcs = {
- 		dce110_transform_v_set_scaler,
- 	.transform_set_scaler_bypass =
- 		dce110_transform_v_set_scalerv_bypass,
--	.transform_update_viewport =
--		dce110_transform_v_update_viewport,
- 	.transform_set_scaler_filter =
- 		dce110_transform_set_scaler_filter,
- 	.transform_set_gamut_remap =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index c7bfa28..ed143f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -764,7 +764,7 @@ enum dc_status dce80_validate_bandwidth(
- 		if (pipe_ctx->stream == NULL)
- 			continue;
- 
--		if (pipe_ctx->ratios.vert.value == 0) {
-+		if (pipe_ctx->scl_data.ratios.vert.value == 0) {
- 			disp->graphics_scale_ratio = bw_int_to_fixed(1);
- 			disp->graphics_h_taps = 2;
- 			disp->graphics_v_taps = 2;
-@@ -780,17 +780,17 @@ enum dc_status dce80_validate_bandwidth(
- 		} else {
- 			disp->graphics_scale_ratio =
- 				fixed31_32_to_bw_fixed(
--					pipe_ctx->ratios.vert.value);
--			disp->graphics_h_taps = pipe_ctx->taps.h_taps;
--			disp->graphics_v_taps = pipe_ctx->taps.v_taps;
-+					pipe_ctx->scl_data.ratios.vert.value);
-+			disp->graphics_h_taps = pipe_ctx->scl_data.taps.h_taps;
-+			disp->graphics_v_taps = pipe_ctx->scl_data.taps.v_taps;
- 
- 			/* TODO: remove when bw formula accepts taps per
- 			 * display
- 			 */
--			if (max_vtaps < pipe_ctx->taps.v_taps)
--				max_vtaps = pipe_ctx->taps.v_taps;
--			if (max_htaps < pipe_ctx->taps.h_taps)
--				max_htaps = pipe_ctx->taps.h_taps;
-+			if (max_vtaps < pipe_ctx->scl_data.taps.v_taps)
-+				max_vtaps = pipe_ctx->scl_data.taps.v_taps;
-+			if (max_htaps < pipe_ctx->scl_data.taps.h_taps)
-+				max_htaps = pipe_ctx->scl_data.taps.h_taps;
- 		}
- 
- 		disp->graphics_src_width =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
-index 5654738..204893e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
-@@ -47,8 +47,6 @@ static struct transform_funcs dce80_transform_funcs = {
- 		dce80_transform_set_scaler,
- 	.transform_set_scaler_bypass =
- 		dce80_transform_set_scaler_bypass,
--	.transform_update_viewport =
--		dce80_transform_update_viewport,
- 	.transform_set_scaler_filter =
- 		dce80_transform_set_scaler_filter,
- 	.transform_set_gamut_remap =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-index 62a3a04..c9b3af5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-@@ -91,7 +91,7 @@ static bool setup_scaling_configuration(
- 		addr = SCL_REG(mmSCL_MODE);
- 		value = dm_read_reg(ctx, addr);
- 
--		if (data->dal_pixel_format <= PIXEL_FORMAT_GRPH_END)
-+		if (data->format <= PIXEL_FORMAT_GRPH_END)
- 			set_reg_field_value(value, 1, SCL_MODE, SCL_MODE);
- 		else
- 			set_reg_field_value(value, 2, SCL_MODE, SCL_MODE);
-@@ -422,7 +422,7 @@ static bool program_multi_taps_filter(
- 
- 	if (horizontal) {
- 		filter_params.taps = data->taps.h_taps;
--		filter_params.sharpness = data->h_sharpness;
-+		filter_params.sharpness = 0; /* TODO */
- 		filter_params.flags.bits.HORIZONTAL = 1;
- 
- 		src_size = data->viewport.width;
-@@ -431,12 +431,12 @@ static bool program_multi_taps_filter(
- 				dal_fixed31_32_div(
- 					dal_fixed31_32_from_int(
- 						data->viewport.width),
--					data->ratios->horz));
-+					data->ratios.horz));
- 
- 		filter_type = FILTER_TYPE_RGB_Y_HORIZONTAL;
- 	} else {
- 		filter_params.taps = data->taps.v_taps;
--		filter_params.sharpness = data->v_sharpness;
-+		filter_params.sharpness = 0; /* TODO */
- 		filter_params.flags.bits.HORIZONTAL = 0;
- 
- 		src_size = data->viewport.height;
-@@ -445,7 +445,7 @@ static bool program_multi_taps_filter(
- 				dal_fixed31_32_div(
- 					dal_fixed31_32_from_int(
- 						data->viewport.height),
--					data->ratios->vert));
-+					data->ratios.vert));
- 
- 		filter_type = FILTER_TYPE_RGB_Y_VERTICAL;
- 	}
-@@ -475,21 +475,6 @@ static bool program_multi_taps_filter(
- 		filter_data,
- 		filter_data_size);
- 
--	/* 4. Program the alpha if necessary */
--	if (data->flags.bits.SHOULD_PROGRAM_ALPHA) {
--		if (horizontal)
--			filter_type = FILTER_TYPE_ALPHA_HORIZONTAL;
--		else
--			filter_type = FILTER_TYPE_ALPHA_VERTICAL;
--
--		program_filter(
--			xfm80,
--			filter_type,
--			&filter_params,
--			filter_data,
--			filter_data_size);
--	}
--
- 	return true;
- }
- 
-@@ -539,18 +524,16 @@ static void calculate_inits(
- {
- 	struct fixed31_32 h_init;
- 	struct fixed31_32 v_init;
--	struct fixed31_32 v_init_bot;
- 
--	inits->bottom_enable = 0;
- 	inits->h_int_scale_ratio =
--		dal_fixed31_32_u2d19(data->ratios->horz) << 5;
-+		dal_fixed31_32_u2d19(data->ratios.horz) << 5;
- 	inits->v_int_scale_ratio =
--		dal_fixed31_32_u2d19(data->ratios->vert) << 5;
-+		dal_fixed31_32_u2d19(data->ratios.vert) << 5;
- 
- 	h_init =
- 		dal_fixed31_32_div_int(
- 			dal_fixed31_32_add(
--				data->ratios->horz,
-+				data->ratios.horz,
- 				dal_fixed31_32_from_int(data->taps.h_taps + 1)),
- 				2);
- 	inits->h_init.integer = dal_fixed31_32_floor(h_init);
-@@ -559,28 +542,11 @@ static void calculate_inits(
- 	v_init =
- 		dal_fixed31_32_div_int(
- 			dal_fixed31_32_add(
--				data->ratios->vert,
-+				data->ratios.vert,
- 				dal_fixed31_32_from_int(data->taps.v_taps + 1)),
- 				2);
- 	inits->v_init.integer = dal_fixed31_32_floor(v_init);
- 	inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
--
--	if (data->flags.bits.INTERLACED) {
--		v_init_bot =
--			dal_fixed31_32_add(
--				dal_fixed31_32_div_int(
--					dal_fixed31_32_add(
--						data->ratios->vert,
--						dal_fixed31_32_from_int(
--							data->taps.v_taps + 1)),
--					2),
--				data->ratios->vert);
--		inits->v_init_bottom.integer = dal_fixed31_32_floor(v_init_bot);
--		inits->v_init_bottom.fraction =
--			dal_fixed31_32_u0d19(v_init_bot) << 5;
--
--		inits->bottom_enable = 1;
--	}
- }
- 
- static void program_scl_ratios_inits(
-@@ -634,22 +600,6 @@ static void program_scl_ratios_inits(
- 		SCL_V_INIT_FRAC);
- 	dm_write_reg(xfm80->base.ctx, addr, value);
- 
--	if (inits->bottom_enable) {
--		addr = SCL_REG(mmSCL_VERT_FILTER_INIT_BOT);
--		value = 0;
--		set_reg_field_value(
--			value,
--			inits->v_init_bottom.integer,
--			SCL_VERT_FILTER_INIT_BOT,
--			SCL_V_INIT_INT_BOT);
--		set_reg_field_value(
--			value,
--			inits->v_init_bottom.fraction,
--			SCL_VERT_FILTER_INIT_BOT,
--			SCL_V_INIT_FRAC_BOT);
--		dm_write_reg(xfm80->base.ctx, addr, value);
--	}
--
- 	addr = SCL_REG(mmSCL_AUTOMATIC_MODE_CONTROL);
- 	value = 0;
- 	set_reg_field_value(
-@@ -665,38 +615,6 @@ static void program_scl_ratios_inits(
- 	dm_write_reg(xfm80->base.ctx, addr, value);
- }
- 
--static void get_viewport(
--		struct dce80_transform *xfm80,
--		struct rect *current_view_port)
--{
--	uint32_t value_start;
--	uint32_t value_size;
--
--	if (current_view_port == NULL)
--		return;
--
--	value_start = dm_read_reg(xfm80->base.ctx, SCL_REG(mmVIEWPORT_START));
--	value_size = dm_read_reg(xfm80->base.ctx, SCL_REG(mmVIEWPORT_SIZE));
--
--	current_view_port->x = get_reg_field_value(
--			value_start,
--			VIEWPORT_START,
--			VIEWPORT_X_START);
--	current_view_port->y = get_reg_field_value(
--			value_start,
--			VIEWPORT_START,
--			VIEWPORT_Y_START);
--	current_view_port->height = get_reg_field_value(
--			value_size,
--			VIEWPORT_SIZE,
--			VIEWPORT_HEIGHT);
--	current_view_port->width = get_reg_field_value(
--			value_size,
--			VIEWPORT_SIZE,
--			VIEWPORT_WIDTH);
--}
--
--
- bool dce80_transform_set_scaler(
- 	struct transform *xfm,
- 	const struct scaler_data *data)
-@@ -761,6 +679,9 @@ bool dce80_transform_set_scaler(
- 			program_two_taps_filter(xfm80, true, false);
- 	}
- 
-+	/* 7. Program the viewport */
-+	program_viewport(xfm80, &data->viewport);
-+
- 	return true;
- }
- 
-@@ -776,35 +697,6 @@ void dce80_transform_set_scaler_bypass(struct transform *xfm)
- 	dm_write_reg(xfm->ctx, SCL_REG(mmSCL_MODE), sclv_mode);
- }
- 
--bool dce80_transform_update_viewport(
--	struct transform *xfm,
--	const struct rect *view_port,
--	bool is_fbc_attached)
--{
--	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
--	bool program_req = false;
--	struct rect current_view_port;
--
--	if (view_port == NULL)
--		return program_req;
--
--	get_viewport(xfm80, &current_view_port);
--
--	if (current_view_port.x != view_port->x ||
--			current_view_port.y != view_port->y ||
--			current_view_port.height != view_port->height ||
--			current_view_port.width != view_port->width)
--		program_req = true;
--
--	if (program_req) {
--		/*underlay viewport is programmed with scaler
--		 *program_viewport function pointer is not exposed*/
--		program_viewport(xfm80, view_port);
--	}
--
--	return program_req;
--}
--
- void dce80_transform_set_scaler_filter(
- 	struct transform *xfm,
- 	struct scaler_filter *filter)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_status.h b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-index b395ae5..f6621f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h
-@@ -37,6 +37,7 @@ enum dc_status {
- 	DC_FAIL_ATTACH_SURFACES,
- 	DC_NO_DP_LINK_BANDWIDTH,
- 	DC_EXCEED_DONGLE_MAX_CLK,
-+	DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED,
- 	DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */
- 
- 	DC_ERROR_UNEXPECTED = -1
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 18bd2da..d638054 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -29,6 +29,7 @@
- #include "dc.h"
- #include "bandwidth_calcs.h"
- #include "ddc_service_types.h"
-+#include "scaler_types.h"
- 
- struct core_stream;
- /********* core_target *************/
-@@ -288,11 +289,7 @@ struct pipe_ctx {
- 	struct output_pixel_processor *opp;
- 	struct timing_generator *tg;
- 
--	struct overscan_info overscan;
--	struct scaling_ratios ratios;
--	struct rect viewport;
--	struct scaling_taps taps;
--	enum pixel_format format;
-+	struct scaler_data scl_data;
- 
- 	struct stream_encoder *stream_enc;
- 	struct display_clock *dis_clk;
-@@ -319,6 +316,7 @@ struct pipe_ctx {
- 	uint8_t pipe_idx;
- 
- 	struct flags {
-+		bool blanked;
- 		bool unchanged;
- 		bool timing_changed;
- 	} flags;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 8b0afe1..014e83f 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -44,14 +44,13 @@ struct hw_sequencer_funcs {
- 	void (*reset_hw_ctx)(struct dc *dc, struct validate_context *context);
- 
- 	void (*set_plane_config)(
--				const struct dc *dc,
--				struct core_surface *surface,
--				struct pipe_ctx *pipe_ctx);
-+			const struct dc *dc,
-+			struct pipe_ctx *pipe_ctx,
-+			struct resource_context *res_ctx);
- 
- 	void (*update_plane_addrs)(
- 		struct dc *dc,
--		struct resource_context *res_ctx,
--		const struct core_surface *surface);
-+		struct resource_context *res_ctx);
- 
- 	bool (*set_gamma_correction)(
- 				struct input_pixel_processor *ipp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index a7b0032..c2d6011 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -31,6 +31,7 @@
- 
- /* TODO unhardcode, 4 for CZ*/
- #define MEMORY_TYPE_MULTIPLIER 4
-+#define DCE110_UNDERLAY_IDX 3
- 
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 				struct dc *dc,
-@@ -79,4 +80,6 @@ enum dc_status map_resources(
- 	const struct dc *dc,
- 	struct validate_context *context);
- 
-+void destruct_val_ctx(struct validate_context *context);
-+
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 1e5467c..efefedb 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -133,11 +133,6 @@ struct transform_funcs {
- 	void (*transform_set_scaler_bypass)(
- 		struct transform *xfm);
- 
--	bool (*transform_update_viewport)(
--		struct transform *xfm,
--		const struct rect *view_port,
--		bool is_fbc_attached);
--
- 	void (*transform_set_scaler_filter)(
- 		struct transform *xfm,
- 		struct scaler_filter *filter);
-diff --git a/drivers/gpu/drm/amd/dal/include/scaler_types.h b/drivers/gpu/drm/amd/dal/include/scaler_types.h
-index db52dbc..3947776 100644
---- a/drivers/gpu/drm/amd/dal/include/scaler_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/scaler_types.h
-@@ -26,15 +26,8 @@
- #ifndef __DAL_SCALER_TYPES_H__
- #define __DAL_SCALER_TYPES_H__
- 
--#include "signal_types.h"
--#include "fixed31_32.h"
- #include "dc_types.h"
- 
--enum pixel_type {
--	PIXEL_TYPE_30BPP = 1,
--	PIXEL_TYPE_20BPP
--};
--
- /*overscan or window*/
- struct overscan_info {
- 	uint32_t left;
-@@ -43,154 +36,42 @@ struct overscan_info {
- 	uint32_t bottom;
- };
- 
--struct mp_scaling_data {
--	struct rect viewport;
--	struct view dst_res;
-+struct scaler_data {
- 	struct overscan_info overscan;
- 	struct scaling_taps taps;
-+	struct rect viewport;
- 	struct scaling_ratios ratios;
--};
- 
--struct scaler_validation_params {
--	uint32_t INTERLACED:1;
--	uint32_t CHROMA_SUB_SAMPLING:1;
--
--	uint32_t line_buffer_size;
--	uint32_t display_clock; /* in KHz */
--	uint32_t actual_pixel_clock; /* in KHz */
--	struct view source_view;
--	struct view dest_view;
--	enum signal_type signal_type;
--
--	struct scaling_taps taps_requested;
--	enum pixel_format pixel_format;
--	enum dc_rotation_angle rotation;
-+	enum pixel_format format;
- };
- 
--struct adjustment_factor {
--	int32_t adjust;	 /* Actual adjustment value * lDivider */
--	uint32_t divider;
--};
--
--struct sharpness_adjustment {
--	int32_t sharpness;
--	bool enable_sharpening;
--};
--
--enum scaling_options {
--	SCALING_BYPASS = 0,
--	SCALING_ENABLE
--};
--
--/* same as Hw register */
--enum filter_type {
--	FILTER_TYPE_V_LOW_PASS = 0x0,
--	FILTER_TYPE_V_HIGH_PASS = 0x1,
--	FILTER_TYPE_H_LUMA = 0x2,
--	FILTER_TYPE_H_CHROMA = 0x3
--};
--
--/* Validation Result enumeration */
--enum scaler_validation_code {
--	SCALER_VALIDATION_OK = 0,
--	SCALER_VALIDATION_INVALID_INPUT_PARAMETERS,
--	SCALER_VALIDATION_SCALING_RATIO_NOT_SUPPORTED,
--	SCALER_VALIDATION_SOURCE_VIEW_WIDTH_EXCEEDING_LIMIT,
--	SCALER_VALIDATION_DISPLAY_CLOCK_BELOW_PIXEL_CLOCK,
--	SCALER_VALIDATION_FAILURE_PREDEFINED_TAPS_NUMBER
--};
--
--
--#define FILTER_TYPE_MASK 0x0000000FL
--#define TWO_TAPS 2
--
- struct init_int_and_frac {
- 	uint32_t integer;
- 	uint32_t fraction;
- };
- 
- struct scl_ratios_inits {
--	uint32_t bottom_enable;
- 	uint32_t h_int_scale_ratio;
- 	uint32_t v_int_scale_ratio;
- 	struct init_int_and_frac h_init;
- 	struct init_int_and_frac v_init;
--	struct init_int_and_frac v_init_bottom;
--};
--
--union scaler_flags {
--	uint32_t raw;
--	struct {
--		uint32_t INTERLACED:1;
--		uint32_t DOUBLE_SCAN_MODE:1;
--		/* this one is legacy flag only used in DCE80 */
--		uint32_t RGB_COLOR_SPACE:1;
--		uint32_t PIPE_LOCK_REQ:1;
--		/* 4 */
--		uint32_t WIDE_DISPLAY:1;
--		uint32_t OTHER_PIPE:1;
--		uint32_t SHOULD_PROGRAM_VIEWPORT:1;
--		uint32_t SHOULD_UNLOCK:1;
--		/* 8 */
--		uint32_t SHOULD_PROGRAM_ALPHA:1;
--		uint32_t SHOW_COLOURED_BORDER:1;
--
--		uint32_t  RESERVED:22;
--	} bits;
--};
--
--struct scaler_data {
--	struct view src_res;
--	struct view dst_res;
--	struct overscan_info overscan;
--	struct scaling_taps taps;
--	struct adjustment_factor scale_ratio_hp_factor;
--	struct adjustment_factor scale_ratio_lp_factor;
--	enum pixel_type pixel_type; /*legacy*/
--	struct sharpness_adjustment sharp_gain;
--
--	union scaler_flags flags;
--	int32_t h_sharpness;
--	int32_t v_sharpness;
--
--	struct view src_res_wide_display;
--	struct view dst_res_wide_display;
--
--	/* it is here because of the HW bug in NI (UBTS #269539)
--	causes glitches in this VBI signal. It shouldn't change after
--	initialization, kind of a const */
--	const struct hw_crtc_timing *hw_crtc_timing;
--
--	struct rect viewport;
--
--	enum pixel_format dal_pixel_format;/*plane concept*/
--	/*stereoformat TODO*/
--	/*hwtotation TODO*/
--
--	const struct scaling_ratios *ratios;
--};
--
--enum bypass_type {
--	/* 00 - 00 - Manual Centering, Manual Replication */
--	BYPASS_TYPE_MANUAL = 0,
--	/* 01 - 01 - Auto-Centering, No Replication */
--	BYPASS_TYPE_AUTO_CENTER = 1,
--	/* 02 - 10 - Auto-Centering, Auto-Replication */
--	BYPASS_TYPE_AUTO_REPLICATION = 3
- };
- 
--struct replication_factor {
--	uint32_t h_manual;
--	uint32_t v_manual;
-+/* same as Hw register */
-+enum filter_type {
-+	FILTER_TYPE_V_LOW_PASS	= 0x0,
-+	FILTER_TYPE_V_HIGH_PASS	= 0x1,
-+	FILTER_TYPE_H_LUMA	= 0x2,
-+	FILTER_TYPE_H_CHROMA	= 0x3
- };
- 
- enum ram_filter_type {
--	FILTER_TYPE_RGB_Y_VERTICAL = 0,	/* 0 - RGB/Y Vertical filter */
--	FILTER_TYPE_CBCR_VERTICAL = 1,	/* 1 - CbCr  Vertical filter */
--	FILTER_TYPE_RGB_Y_HORIZONTAL   = 2, /* 1 - RGB/Y Horizontal filter */
--	FILTER_TYPE_CBCR_HORIZONTAL   = 3, /* 3 - CbCr  Horizontal filter */
--	FILTER_TYPE_ALPHA_VERTICAL    = 4, /* 4 - Alpha Vertical filter. */
--	FILTER_TYPE_ALPHA_HORIZONTAL  = 5, /* 5 - Alpha Horizontal filter. */
-+	FILTER_TYPE_RGB_Y_VERTICAL	= 0, /* 0 - RGB/Y Vertical filter */
-+	FILTER_TYPE_CBCR_VERTICAL	= 1, /* 1 - CbCr  Vertical filter */
-+	FILTER_TYPE_RGB_Y_HORIZONTAL	= 2, /* 1 - RGB/Y Horizontal filter */
-+	FILTER_TYPE_CBCR_HORIZONTAL	= 3, /* 3 - CbCr  Horizontal filter */
-+	FILTER_TYPE_ALPHA_VERTICAL	= 4, /* 4 - Alpha Vertical filter. */
-+	FILTER_TYPE_ALPHA_HORIZONTAL	= 5, /* 5 - Alpha Horizontal filter. */
- };
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0815-drm-amd-dal-Ungate-Underlay-pipe-clock.patch b/common/recipes-kernel/linux/files/0815-drm-amd-dal-Ungate-Underlay-pipe-clock.patch
deleted file mode 100644
index e5b77433..00000000
--- a/common/recipes-kernel/linux/files/0815-drm-amd-dal-Ungate-Underlay-pipe-clock.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 738f0b087301175de753eb1a10825b50c191749a Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Thu, 18 Feb 2016 17:03:07 -0500
-Subject: [PATCH 0815/1110] drm/amd/dal: Ungate Underlay pipe clock.
-
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c   | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-index 4c307f6..a54cc25 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-@@ -62,6 +62,21 @@ static void force_hw_base_light_sleep(struct dc_context *ctx)
- 
- }
- 
-+static void underlay_clock_enable(struct dc_context *ctx)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(ctx, mmDCFEV_CLOCK_CONTROL);
-+
-+	set_reg_field_value(
-+			value,
-+			1,
-+			DCFEV_CLOCK_CONTROL,
-+			DCFEV_CLOCK_ENABLE);
-+
-+	dm_write_reg(ctx, mmDCFEV_CLOCK_CONTROL, value);
-+}
-+
- static void enable_hw_base_light_sleep(struct dc_context *ctx)
- {
- 	NOT_IMPLEMENTED();
-@@ -86,5 +101,6 @@ void dal_dc_clock_gating_dce110_power_up(
- 		disable_sw_manual_control_light_sleep(ctx);
- 	} else {
- 		force_hw_base_light_sleep(ctx);
-+		underlay_clock_enable(ctx);
- 	}
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0816-drm-amd-dal-Refactor-opp-xfm-ipp-headers-incremental.patch b/common/recipes-kernel/linux/files/0816-drm-amd-dal-Refactor-opp-xfm-ipp-headers-incremental.patch
deleted file mode 100644
index 8cd821f0..00000000
--- a/common/recipes-kernel/linux/files/0816-drm-amd-dal-Refactor-opp-xfm-ipp-headers-incremental.patch
+++ /dev/null
@@ -1,793 +0,0 @@
-From 5dfa96c7b0d63e7d154224fa86e5f43b2bab0e65 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 18 Feb 2016 15:40:51 -0500
-Subject: [PATCH 0816/1110] drm/amd/dal: Refactor opp xfm ipp headers
- incremental
-
-Incremental commit, this one mainly deal with opp. There is one
-change in ipp to move ovl_color_space out of dc_hw_types And
-minor change in transform to untangle dependencies between
-transform and opp.
-
-Goal of this changeis to make opp header files self-contained.
-i.e. all types used in opp.h, are either in the header itself or
-in dc_hw_types.h. This is to allow the header files to be shared
-with HW team to write pseudo code
-
-2 structures that are still not contained are signal_type and
-fix_point fixed31_32
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           | 41 +++++++++--
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 33 ---------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c | 18 ++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c   | 14 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |  2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |  3 +-
- .../drm/amd/dal/dc/dce110/dce110_transform_gamut.c |  4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h |  1 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h       |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c   | 18 ++---
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h |  3 +-
- .../drm/amd/dal/dc/dce80/dce80_transform_gamut.c   |  4 +-
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |  9 ++-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               | 39 ++++++++--
- drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h  |  2 -
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         | 17 ++++-
- drivers/gpu/drm/amd/dal/include/grph_csc_types.h   | 85 ----------------------
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  |  1 -
- 19 files changed, 125 insertions(+), 173 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index 2a9ec19..61939f7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -282,12 +282,6 @@ struct dc_cursor_position {
- 
- /* Used by both ipp amd opp functions*/
- /* TODO: to be consolidated with enum color_space */
--enum ovl_color_space {
--	OVL_COLOR_SPACE_UNKNOWN = 0,
--	OVL_COLOR_SPACE_RGB,
--	OVL_COLOR_SPACE_YUV601,
--	OVL_COLOR_SPACE_YUV709
--};
- 
- /*
-  * This enum is for programming CURSOR_MODE register field. What this register
-@@ -365,5 +359,40 @@ struct dev_c_lut {
- 	uint8_t green;
- 	uint8_t blue;
- };
-+
-+/* OPP */
-+enum dc_pixel_encoding {
-+	PIXEL_ENCODING_UNDEFINED,
-+	PIXEL_ENCODING_RGB,
-+	PIXEL_ENCODING_YCBCR422,
-+	PIXEL_ENCODING_YCBCR444,
-+	PIXEL_ENCODING_YCBCR420,
-+	PIXEL_ENCODING_COUNT
-+};
-+
-+enum color_space {
-+	COLOR_SPACE_UNKNOWN,
-+	COLOR_SPACE_SRGB_FULL_RANGE,
-+	COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	COLOR_SPACE_YPBPR601,
-+	COLOR_SPACE_YPBPR709,
-+	COLOR_SPACE_YCBCR601,
-+	COLOR_SPACE_YCBCR709,
-+	COLOR_SPACE_YCBCR601_YONLY,
-+	COLOR_SPACE_YCBCR709_YONLY,
-+	COLOR_SPACE_N_MVPU_SUPER_AA,
-+};
-+
-+enum dc_color_depth {
-+	COLOR_DEPTH_UNDEFINED,
-+	COLOR_DEPTH_666,
-+	COLOR_DEPTH_888,
-+	COLOR_DEPTH_101010,
-+	COLOR_DEPTH_121212,
-+	COLOR_DEPTH_141414,
-+	COLOR_DEPTH_161616,
-+	COLOR_DEPTH_COUNT
-+};
-+
- #endif /* DC_HW_TYPES_H */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 4e36b85..bcbb911 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -67,19 +67,6 @@ enum dce_environment {
- #define MAX_SURFACE_NUM 2
- #define NUM_PIXEL_FORMATS 10
- 
--enum color_space {
--	COLOR_SPACE_UNKNOWN,
--	COLOR_SPACE_SRGB_FULL_RANGE,
--	COLOR_SPACE_SRGB_LIMITED_RANGE,
--	COLOR_SPACE_YPBPR601,
--	COLOR_SPACE_YPBPR709,
--	COLOR_SPACE_YCBCR601,
--	COLOR_SPACE_YCBCR709,
--	COLOR_SPACE_YCBCR601_YONLY,
--	COLOR_SPACE_YCBCR709_YONLY,
--	COLOR_SPACE_N_MVPU_SUPER_AA,
--};
--
- enum tiling_mode {
- 	TILING_MODE_INVALID,
- 	TILING_MODE_LINEAR,
-@@ -115,15 +102,6 @@ enum plane_stereo_format {
- 	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
- };
- 
--enum dc_pixel_encoding {
--	PIXEL_ENCODING_UNDEFINED,
--	PIXEL_ENCODING_RGB,
--	PIXEL_ENCODING_YCBCR422,
--	PIXEL_ENCODING_YCBCR444,
--	PIXEL_ENCODING_YCBCR420,
--	PIXEL_ENCODING_COUNT
--};
--
- /* TODO: Find way to calculate number of bits
-  *  Please increase if pixel_format enum increases
-  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-@@ -307,17 +285,6 @@ enum dc_aspect_ratio {
- 	ASPECT_RATIO_FUTURE
- };
- 
--enum dc_color_depth {
--	COLOR_DEPTH_UNDEFINED,
--	COLOR_DEPTH_666,
--	COLOR_DEPTH_888,
--	COLOR_DEPTH_101010,
--	COLOR_DEPTH_121212,
--	COLOR_DEPTH_141414,
--	COLOR_DEPTH_161616,
--	COLOR_DEPTH_COUNT
--};
--
- enum dc_timing_3d_format {
- 	TIMING_3D_FORMAT_NONE,
- 	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index a19e744..e6dcaf8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -116,7 +116,7 @@ void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
- 
- void dce110_opp_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
--	const struct grph_csc_adjustment *adjust);
-+	const struct opp_grph_csc_adjustment *adjust);
- 
- void dce110_opp_set_csc_default(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-index 8f651e9..b1db0cc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -193,7 +193,7 @@ static void program_color_matrix(
-  * @return None
-  */
- static void initialize_color_float_adj_reference_values(
--	const struct grph_csc_adjustment *adjust,
-+	const struct opp_grph_csc_adjustment *adjust,
- 	struct fixed31_32 *grph_cont,
- 	struct fixed31_32 *grph_sat,
- 	struct fixed31_32 *grph_bright,
-@@ -291,7 +291,7 @@ static void setup_reg_format(
-  *
-  *****************************************************************************
-  */
--static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-+static void setup_adjustments(const struct opp_grph_csc_adjustment *adjust,
- 	struct dc_csc_adjustments *adjustments)
- {
- 	if (adjust->adjust_divider != 0) {
-@@ -343,7 +343,7 @@ static void prepare_tv_rgb_ideal(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_rgb_adjustment_legacy
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -356,7 +356,7 @@ static void prepare_tv_rgb_ideal(
-  */
- static void set_rgb_adjustment_legacy(
- 	struct dce110_opp *opp110,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	const struct fixed31_32 k1 =
- 		dal_fixed31_32_from_fraction(701000, 1000000);
-@@ -571,7 +571,7 @@ static void set_rgb_adjustment_legacy(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_rgb_limited_range_adjustment
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -584,7 +584,7 @@ static void set_rgb_adjustment_legacy(
-  */
- static void set_rgb_limited_range_adjustment(
- 	struct dce110_opp *opp110,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	struct out_csc_color_matrix reg_matrix;
- 	struct fixed31_32 change_matrix[OUTPUT_CSC_MATRIX_SIZE];
-@@ -657,7 +657,7 @@ static void prepare_yuv_ideal(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_yuv_adjustment
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -670,7 +670,7 @@ static void prepare_yuv_ideal(
-  */
- static void set_yuv_adjustment(
- 	struct dce110_opp *opp110,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
- 		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
-@@ -823,7 +823,7 @@ static bool configure_graphics_mode(
- 
- void dce110_opp_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
- 	enum csc_color_mode config =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-index 6ca749e..a786b98 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-@@ -364,7 +364,7 @@ static void program_color_matrix_v(
-  * @return None
-  */
- static void initialize_color_float_adj_reference_values(
--	const struct grph_csc_adjustment *adjust,
-+	const struct opp_grph_csc_adjustment *adjust,
- 	struct fixed31_32 *grph_cont,
- 	struct fixed31_32 *grph_sat,
- 	struct fixed31_32 *grph_bright,
-@@ -462,7 +462,7 @@ static void setup_reg_format(
-  *
-  *****************************************************************************
-  */
--static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-+static void setup_adjustments(const struct opp_grph_csc_adjustment *adjust,
- 	struct dc_csc_adjustments *adjustments)
- {
- 	if (adjust->adjust_divider != 0) {
-@@ -495,7 +495,7 @@ static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_rgb_adjustment_legacy
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -508,7 +508,7 @@ static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-  */
- static void set_rgb_adjustment_legacy(
- 	struct dce110_opp *opp110,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	const struct fixed31_32 k1 =
- 		dal_fixed31_32_from_fraction(701000, 1000000);
-@@ -769,7 +769,7 @@ static void prepare_yuv_ideal(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_yuv_adjustment
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -782,7 +782,7 @@ static void prepare_yuv_ideal(
-  */
- static void set_yuv_adjustment(
- 	struct dce110_opp *opp110,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
- 		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
-@@ -1014,7 +1014,7 @@ void dce110_opp_v_set_csc_default(
- 
- void dce110_opp_v_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
- 	enum csc_color_mode config =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-index 1936ba4..d78395a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -43,7 +43,7 @@ void dce110_opp_v_set_csc_default(
- 
- void dce110_opp_v_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
--	const struct grph_csc_adjustment *adjust);
-+	const struct opp_grph_csc_adjustment *adjust);
- 
- bool dce110_opp_program_regamma_pwl_v(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index 117aca3..f7c5565 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -26,7 +26,6 @@
- #define __DAL_TRANSFORM_DCE110_H__
- 
- #include "inc/transform.h"
--#include "include/grph_csc_types.h"
- 
- #define TO_DCE110_TRANSFORM(transform)\
- 	container_of(transform, struct dce110_transform, base)
-@@ -71,7 +70,7 @@ void dce110_transform_set_scaler_filter(
- /* GAMUT RELATED */
- void dce110_transform_set_gamut_remap(
- 	struct transform *xfm,
--	const struct grph_csc_adjustment *adjust);
-+	const struct xfm_grph_csc_adjustment *adjust);
- 
- /* BIT DEPTH RELATED */
- bool dce110_transform_set_pixel_storage_depth(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-index 05309c9..fe5be62 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
-@@ -221,7 +221,7 @@ static void program_gamut_remap(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_gamut_remap
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct xfm_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -234,7 +234,7 @@ static void program_gamut_remap(
-  */
- void dce110_transform_set_gamut_remap(
- 	struct transform *xfm,
--	const struct grph_csc_adjustment *adjust)
-+	const struct xfm_grph_csc_adjustment *adjust)
- {
- 	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-index b51bd78..eec3872 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-@@ -26,7 +26,6 @@
- #define __DAL_TRANSFORM_V_DCE110_H__
- 
- #include "inc/transform.h"
--#include "include/grph_csc_types.h"
- 
- bool dce110_transform_v_construct(
- 	struct dce110_transform *xfm110,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-index d414f50..db5e0eb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-@@ -105,7 +105,7 @@ void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp,
- 
- void dce80_opp_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
--	const struct grph_csc_adjustment *adjust);
-+	const struct opp_grph_csc_adjustment *adjust);
- 
- void dce80_opp_set_csc_default(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-index 90662ae..2ea6628 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-@@ -194,7 +194,7 @@ static void program_color_matrix(
-  * @return None
-  */
- static void initialize_color_float_adj_reference_values(
--	const struct grph_csc_adjustment *adjust,
-+	const struct opp_grph_csc_adjustment *adjust,
- 	struct fixed31_32 *grph_cont,
- 	struct fixed31_32 *grph_sat,
- 	struct fixed31_32 *grph_bright,
-@@ -292,7 +292,7 @@ static void setup_reg_format(
-  *
-  *****************************************************************************
-  */
--static void setup_adjustments(const struct grph_csc_adjustment *adjust,
-+static void setup_adjustments(const struct opp_grph_csc_adjustment *adjust,
- 	struct dc_csc_adjustments *adjustments)
- {
- 	if (adjust->adjust_divider != 0) {
-@@ -344,7 +344,7 @@ static void prepare_tv_rgb_ideal(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_rgb_adjustment_legacy
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -357,7 +357,7 @@ static void prepare_tv_rgb_ideal(
-  */
- static void set_rgb_adjustment_legacy(
- 	struct dce80_opp *opp80,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	const struct fixed31_32 k1 =
- 		dal_fixed31_32_from_fraction(701000, 1000000);
-@@ -572,7 +572,7 @@ static void set_rgb_adjustment_legacy(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_rgb_limited_range_adjustment
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -585,7 +585,7 @@ static void set_rgb_adjustment_legacy(
-  */
- static void set_rgb_limited_range_adjustment(
- 	struct dce80_opp *opp80,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	struct out_csc_color_matrix reg_matrix;
- 	struct fixed31_32 change_matrix[OUTPUT_CSC_MATRIX_SIZE];
-@@ -658,7 +658,7 @@ static void prepare_yuv_ideal(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_yuv_adjustment
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct opp_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -671,7 +671,7 @@ static void prepare_yuv_ideal(
-  */
- static void set_yuv_adjustment(
- 	struct dce80_opp *opp80,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
- 		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
-@@ -824,7 +824,7 @@ static bool configure_graphics_mode(
- 
- void dce80_opp_set_csc_adjustment(
- 	struct output_pixel_processor *opp,
--	const struct grph_csc_adjustment *adjust)
-+	const struct opp_grph_csc_adjustment *adjust)
- {
- 	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
- 	enum csc_color_mode config =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-index adcc54b..ac8e5c9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -26,7 +26,6 @@
- #define __DAL_TRANSFORM_DCE80_H__
- 
- #include "inc/transform.h"
--#include "include/grph_csc_types.h"
- 
- #define TO_DCE80_TRANSFORM(transform)\
- 	container_of(transform, struct dce80_transform, base)
-@@ -71,7 +70,7 @@ void dce80_transform_set_scaler_filter(
- /* GAMUT RELATED */
- void dce80_transform_set_gamut_remap(
- 	struct transform *xfm,
--	const struct grph_csc_adjustment *adjust);
-+	const struct xfm_grph_csc_adjustment *adjust);
- 
- /* BIT DEPTH RELATED */
- bool dce80_transform_set_pixel_storage_depth(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
-index df5db67..4c54f3d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_gamut.c
-@@ -222,7 +222,7 @@ static void program_gamut_remap(
-  *****************************************************************************
-  *  Function: dal_transform_wide_gamut_set_gamut_remap
-  *
-- *  @param [in] const struct grph_csc_adjustment *adjust
-+ *  @param [in] const struct xfm_grph_csc_adjustment *adjust
-  *
-  *  @return
-  *     void
-@@ -235,7 +235,7 @@ static void program_gamut_remap(
-  */
- void dce80_transform_set_gamut_remap(
- 	struct transform *xfm,
--	const struct grph_csc_adjustment *adjust)
-+	const struct xfm_grph_csc_adjustment *adjust)
- {
- 	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index c98102f..e231ce1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -28,7 +28,6 @@
- #define __DAL_IPP_H__
- 
- #include "include/grph_object_id.h"
--#include "include/grph_csc_types.h"
- #include "include/video_csc_types.h"
- #include "include/hw_sequencer_types.h"
- 
-@@ -79,6 +78,14 @@ enum wide_gamut_degamma_mode {
- 	WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_B,
- };
- 
-+
-+enum ovl_color_space {
-+	OVL_COLOR_SPACE_UNKNOWN = 0,
-+	OVL_COLOR_SPACE_RGB,
-+	OVL_COLOR_SPACE_YUV601,
-+	OVL_COLOR_SPACE_YUV709
-+};
-+
- struct dcp_video_matrix {
- 	enum ovl_color_space color_space;
- 	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 4924874..3d8fe0d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -28,7 +28,6 @@
- 
- #include "dc_types.h"
- #include "grph_object_id.h"
--#include "grph_csc_types.h"
- #include "video_csc_types.h"
- #include "hw_sequencer_types.h"
- 
-@@ -269,6 +268,38 @@ struct regamma_params {
- 	uint32_t hw_points_num;
- };
- 
-+enum graphics_csc_adjust_type {
-+	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
-+};
-+
-+struct default_adjustment {
-+	uint32_t lb_color_depth;
-+	enum color_space color_space;
-+	enum dc_color_depth color_depth;
-+	enum pixel_format surface_pixel_format;
-+	enum graphics_csc_adjust_type csc_adjust_type;
-+	bool force_hw_default;
-+};
-+
-+enum grph_color_adjust_option {
-+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
-+	GRPH_COLOR_MATRIX_SW
-+};
-+
-+struct opp_grph_csc_adjustment {
-+	enum grph_color_adjust_option color_adjust_option;
-+	enum color_space c_space;
-+	enum dc_color_depth color_depth; /* clean up to uint32_t */
-+	enum graphics_csc_adjust_type   csc_adjust_type;
-+	int32_t adjust_divider;
-+	int32_t grph_cont;
-+	int32_t grph_sat;
-+	int32_t grph_bright;
-+	int32_t grph_hue;
-+};
-+
- struct opp_funcs {
- 	void (*opp_power_on_regamma_lut)(
- 		struct output_pixel_processor *opp,
-@@ -283,7 +314,7 @@ struct opp_funcs {
- 
- 	void (*opp_set_csc_adjustment)(
- 		struct output_pixel_processor *opp,
--		const struct grph_csc_adjustment *adjust);
-+		const struct opp_grph_csc_adjustment *adjust);
- 
- 	void (*opp_set_csc_default)(
- 		struct output_pixel_processor *opp,
-@@ -310,10 +341,6 @@ struct opp_funcs {
- 			enum ovl_csc_adjust_item overlay_adjust_item,
- 			struct hw_adjustment_range *range);
- 
--	void (*opp_set_ovl_csc_adjustment)(
--			struct output_pixel_processor *opp,
--			const struct ovl_csc_adjustment *adjust,
--			enum color_space c_space);
- 
- 	void (*opp_destroy)(struct output_pixel_processor **opp);
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-index e9ca169..7ef22ad 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-@@ -26,8 +26,6 @@
- #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
- #define __DAL_TIMING_GENERATOR_TYPES_H__
- 
--#include "include/grph_csc_types.h"
--
- struct dc_bios;
- 
- /**
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index efefedb..47adc1d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -27,7 +27,6 @@
- #define __DAL_TRANSFORM_H__
- 
- #include "include/scaler_types.h"
--#include "include/grph_csc_types.h"
- #include "calcs/scaler_filter.h"
- #include "grph_object_id.h"
- 
-@@ -122,6 +121,20 @@ enum yyc_quantization_range {
-        YYC_QUANTIZATION_RESERVED3 = 3
- };
- 
-+enum graphics_gamut_adjust_type {
-+	GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_GAMUT_ADJUST_TYPE_SW  /* use adjustments */
-+};
-+
-+#define CSC_TEMPERATURE_MATRIX_SIZE 9
-+
-+struct xfm_grph_csc_adjustment {
-+	int32_t temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
-+	int32_t temperature_divider;
-+	enum graphics_gamut_adjust_type gamut_adjust_type;
-+};
-+
- struct transform_funcs {
- 	bool (*transform_power_up)(
- 		struct transform *xfm);
-@@ -139,7 +152,7 @@ struct transform_funcs {
- 
- 	void (*transform_set_gamut_remap)(
- 		struct transform *xfm,
--		const struct grph_csc_adjustment *adjust);
-+		const struct xfm_grph_csc_adjustment *adjust);
- 
- 	bool (*transform_set_pixel_storage_depth)(
- 		struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_csc_types.h b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-deleted file mode 100644
-index 5927dd0..0000000
---- a/drivers/gpu/drm/amd/dal/include/grph_csc_types.h
-+++ /dev/null
-@@ -1,85 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_GRPH_CSC_TYPES_H__
--#define __DAL_GRPH_CSC_TYPES_H__
--
--#include "set_mode_types.h"
--
--enum grph_color_adjust_option {
--	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
--	GRPH_COLOR_MATRIX_SW
--};
--
--enum grph_csc_adjust_item {
--	GRPH_ADJUSTMENT_CONTRAST = 1,
--	GRPH_ADJUSTMENT_SATURATION,
--	GRPH_ADJUSTMENT_BRIGHTNESS,
--	GRPH_ADJUSTMENT_HUE,
--	GRPH_ADJUSTMENT_COLOR_TEMPERATURE
--};
--
--#define CSC_TEMPERATURE_MATRIX_SIZE 9
--
--enum graphics_csc_adjust_type {
--	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
--	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
--	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
--};
--
--enum graphics_gamut_adjust_type {
--	GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
--	GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
--	GRAPHICS_GAMUT_ADJUST_TYPE_SW  /* use adjustments */
--};
--
--struct grph_csc_adjustment {
--	enum grph_color_adjust_option color_adjust_option;
--	enum color_space c_space;
--	int32_t grph_cont;
--	int32_t grph_sat;
--	int32_t grph_bright;
--	int32_t grph_hue;
--	int32_t adjust_divider;
--	int32_t temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
--	int32_t temperature_divider;
--	uint32_t lb_color_depth;
--	uint8_t gamma; /* gamma from Edid */
--	enum dc_color_depth color_depth; /* clean up to uint32_t */
--	enum pixel_format surface_pixel_format;
--	enum graphics_csc_adjust_type   csc_adjust_type;
--	enum graphics_gamut_adjust_type gamut_adjust_type;
--};
--
--struct default_adjustment {
--	uint32_t lb_color_depth;
--	enum color_space color_space;
--	enum dc_color_depth color_depth;
--	enum pixel_format surface_pixel_format;
--	enum graphics_csc_adjust_type csc_adjust_type;
--	bool force_hw_default;
--};
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index 354a01b..515f75b 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -82,7 +82,6 @@ union ovl_csc_flag {
- };
- 
- struct ovl_csc_adjustment {
--	enum ovl_color_space ovl_cs;
- 	struct ovl_color_adjust_option ovl_option;
- 	enum dc_color_depth display_color_depth;
- 	uint32_t lb_color_depth;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0817-drm-amd-dal-blanking-fix.patch b/common/recipes-kernel/linux/files/0817-drm-amd-dal-blanking-fix.patch
deleted file mode 100644
index 0f84b665..00000000
--- a/common/recipes-kernel/linux/files/0817-drm-amd-dal-blanking-fix.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From ac0c42a42f2444f764a60b11a69ceffca975f94f Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 18 Feb 2016 18:56:19 -0500
-Subject: [PATCH 0817/1110] drm/amd/dal: blanking fix
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 12 +++++-------
- 1 file changed, 5 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index d01a116..a642de4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1448,13 +1448,11 @@ static void update_plane_addrs(struct dc *dc, struct resource_context *res_ctx)
- 					PIPE_LOCK_CONTROL_SURFACE,
- 					false);
- 
--		if (pipe_ctx->flags.blanked) {
--			if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false)) {
--				dm_error("DC: failed to unblank crtc!\n");
--				BREAK_TO_DEBUGGER();
--			} else
--				pipe_ctx->flags.blanked = false;
--		}
-+		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false)) {
-+			dm_error("DC: failed to unblank crtc!\n");
-+			BREAK_TO_DEBUGGER();
-+		} else
-+			pipe_ctx->flags.blanked = false;
- 	}
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0818-drm-amd-dal-delete-dead-code.patch b/common/recipes-kernel/linux/files/0818-drm-amd-dal-delete-dead-code.patch
deleted file mode 100644
index fc0b7342..00000000
--- a/common/recipes-kernel/linux/files/0818-drm-amd-dal-delete-dead-code.patch
+++ /dev/null
@@ -1,226 +0,0 @@
-From c562cd14e7c34b0367e9749a007106020819ea07 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 18 Feb 2016 12:37:30 -0500
-Subject: [PATCH 0818/1110] drm/amd/dal: delete dead code
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 36 +---------------------
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           | 27 ++--------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 22 +++----------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |  1 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c |  4 +--
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |  6 ----
- 6 files changed, 10 insertions(+), 86 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index e7a4b3e..107636a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -192,39 +192,7 @@ static enum pixel_format convert_pixel_format_to_dalsurface(
- 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
- 		dal_pixel_format = PIXEL_FORMAT_420BPP12;
- 		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_422_YCb:
--		dal_pixel_format = PIXEL_FORMAT_422BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_422_YCr:
--		dal_pixel_format = PIXEL_FORMAT_422BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_422_CbY:
--		dal_pixel_format = PIXEL_FORMAT_422BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_422_CrY:
--		dal_pixel_format = PIXEL_FORMAT_422BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555:
--		dal_pixel_format = PIXEL_FORMAT_444BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565:
--		dal_pixel_format = PIXEL_FORMAT_444BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444:
--		dal_pixel_format = PIXEL_FORMAT_444BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551:
--		dal_pixel_format = PIXEL_FORMAT_444BPP16;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888:
--		dal_pixel_format = PIXEL_FORMAT_444BPP32;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010:
--		dal_pixel_format = PIXEL_FORMAT_444BPP32;
--		break;
--	case SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102:
--		dal_pixel_format = PIXEL_FORMAT_444BPP32;
--		break;
-+
- 	default:
- 		dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
- 		break;
-@@ -335,8 +303,6 @@ static void calculate_scaling_ratios(
- 	if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12) {
- 		pipe_ctx->scl_data.ratios.horz_c.value /= 2;
- 		pipe_ctx->scl_data.ratios.vert_c.value /= 2;
--	} else if (pipe_ctx->scl_data.format == PIXEL_FORMAT_422BPP16) {
--		pipe_ctx->scl_data.ratios.horz_c.value /= 2;
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index 61939f7..f11a78d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -153,20 +153,8 @@ enum surface_pixel_format {
- 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
- 		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
- 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_YCb,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_YCr,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_CbY,
--	SURFACE_PIXEL_FORMAT_VIDEO_422_CrY,
--	/*grow 422/420 video here if necessary */
--	SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 =
--		SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010,
--	SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102
-+	SURFACE_PIXEL_FORMAT_INVALID
-+
- 	/*grow 444 video here if necessary */
- };
- 
-@@ -341,25 +329,16 @@ enum pixel_format {
- 	PIXEL_FORMAT_FP16,
- 	/*video*/
- 	PIXEL_FORMAT_420BPP12,
--	PIXEL_FORMAT_422BPP16,
--	PIXEL_FORMAT_444BPP16,
--	PIXEL_FORMAT_444BPP32,
- 	/*end of pixel format definition*/
- 	PIXEL_FORMAT_INVALID,
- 
- 	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
- 	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
- 	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
--	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_444BPP32,
-+	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP12,
- 	PIXEL_FORMAT_UNKNOWN
- };
- 
--struct dev_c_lut {
--	uint8_t red;
--	uint8_t green;
--	uint8_t blue;
--};
--
- /* OPP */
- enum dc_pixel_encoding {
- 	PIXEL_ENCODING_UNDEFINED,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-index 8a211d8..042bd3a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-@@ -371,8 +371,7 @@ static void program_pixel_format(
- 	struct dce110_mem_input *mem_input110,
- 	enum surface_pixel_format format)
- {
--	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN ||
--			format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
- 		uint32_t value;
- 		uint8_t grph_depth;
- 		uint8_t grph_format;
-@@ -459,19 +458,8 @@ static void program_pixel_format(
- 		case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
- 			video_format = 3;
- 			break;
--		case SURFACE_PIXEL_FORMAT_VIDEO_422_YCb:
--			video_format = 4;
--			break;
--		case SURFACE_PIXEL_FORMAT_VIDEO_422_YCr:
--			video_format = 5;
--			break;
--		case SURFACE_PIXEL_FORMAT_VIDEO_422_CbY:
--			video_format = 6;
--			break;
--		case SURFACE_PIXEL_FORMAT_VIDEO_422_CrY:
--			video_format = 7;
--			break;
- 		default:
-+			video_format = 0;
- 			break;
- 		}
- 
-@@ -482,9 +470,9 @@ static void program_pixel_format(
- 			VIDEO_FORMAT);
- 
- 		dm_write_reg(
--				mem_input110->base.ctx,
--				DCP_REG(mmUNP_GRPH_CONTROL_EXP),
--				value);
-+			mem_input110->base.ctx,
-+			DCP_REG(mmUNP_GRPH_CONTROL_EXP),
-+			value);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index e6dcaf8..fada94d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -68,7 +68,6 @@ struct dce110_regamma {
- 	struct pwl_float_data *rgb_oem;
- 	/* user supplied gamma */
- 	struct pwl_float_data *rgb_user;
--	struct dev_c_lut saved_palette[RGB_256X3X16];
- 	uint32_t extra_points;
- 	bool use_half_points;
- 	struct fixed31_32 x_max1;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index aef17b3..47ab396 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -196,8 +196,7 @@ static bool setup_scaling_configuration(
- 		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C);
- 		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C);
- 		is_scaling_needed = true;
--	} else if (data->format != PIXEL_FORMAT_420BPP12 &&
--		data->format != PIXEL_FORMAT_422BPP16) {
-+	} else if (data->format != PIXEL_FORMAT_420BPP12) {
- 		set_reg_field_value(
- 			value,
- 			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
-@@ -356,7 +355,6 @@ static void calculate_inits(
- 	inits->v_init_luma.integer = 1;
- 	inits->h_init_chroma.integer = 1;
- 	inits->v_init_chroma.integer = 1;
--
- }
- 
- static void program_scl_ratios_inits(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index e231ce1..bffeef5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -111,12 +111,6 @@ struct ipp_funcs {
- 		struct input_pixel_processor *ipp,
- 		struct ipp_prescale_params *params);
- 
--	bool (*ipp_set_palette)(
--		struct input_pixel_processor *ipp,
--		const struct dev_c_lut *palette,
--		uint32_t start,
--		uint32_t length,
--		enum pixel_format surface_pixel_format);
- };
- 
- #endif /* __DAL_IPP_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0819-drm-amd-dal-refactor-ipp_degamma_mode-for-HW-diag.patch b/common/recipes-kernel/linux/files/0819-drm-amd-dal-refactor-ipp_degamma_mode-for-HW-diag.patch
deleted file mode 100644
index 40367932..00000000
--- a/common/recipes-kernel/linux/files/0819-drm-amd-dal-refactor-ipp_degamma_mode-for-HW-diag.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From a05c4f6285cc84af65e60769d5f9a13cbf5351ba Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 18 Feb 2016 14:56:52 -0500
-Subject: [PATCH 0819/1110] drm/amd/dal: refactor ipp_degamma_mode for HW diag
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c  |  5 ++++-
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h                  | 19 +++----------------
- 3 files changed, 8 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index a642de4..79ab334 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -534,7 +534,7 @@ static bool set_gamma_ramp(
- 				temp_params, ramp, surface);
- 		opp->funcs->opp_program_regamma_pwl(opp, regamma_params);
- 		if (ipp)
--			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_sRGB);
-+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
- 		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
- 	} else {
- 		if (ipp)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index dc0ccbb..fb90a6a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -64,7 +64,10 @@ bool dce110_ipp_set_degamma(
- 
- 	uint32_t value = 0;
- 
--	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_sRGB) ? 1 : 0;
-+	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
-+
-+	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||
-+			mode == IPP_DEGAMMA_MODE_USER_PWL);
- 
- 	set_reg_field_value(
- 		value,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index bffeef5..4599d68 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -60,22 +60,9 @@ struct ipp_prescale_params {
- 
- enum ipp_degamma_mode {
- 	IPP_DEGAMMA_MODE_BYPASS,
--	IPP_DEGAMMA_MODE_sRGB
--};
--
--enum wide_gamut_degamma_mode {
--	/*  00  - BITS1:0 Bypass */
--	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_BYPASS,
--	/*  0x1 - PWL gamma ROM A */
--	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_PWL_ROM_A,
--	/*  0x2 - PWL gamma ROM B */
--	WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_PWL_ROM_B,
--	/*  00  - BITS5:4 Bypass */
--	WIDE_GAMUT_DEGAMMA_MODE_OVL_BYPASS,
--	/*  0x1 - PWL gamma ROM A */
--	WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_A,
--	/*  0x2 - PWL gamma ROM B */
--	WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_B,
-+	IPP_DEGAMMA_MODE_HW_sRGB,
-+	IPP_DEGAMMA_MODE_HW_xvYCC,
-+	IPP_DEGAMMA_MODE_USER_PWL
- };
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0820-drm-amd-dal-Define-new-ipp-functions-for-diags.patch b/common/recipes-kernel/linux/files/0820-drm-amd-dal-Define-new-ipp-functions-for-diags.patch
deleted file mode 100644
index 543dc7bc..00000000
--- a/common/recipes-kernel/linux/files/0820-drm-amd-dal-Define-new-ipp-functions-for-diags.patch
+++ /dev/null
@@ -1,517 +0,0 @@
-From 0db01598b1e4618521164542693767fdf92e4260 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 19 Feb 2016 14:50:16 -0500
-Subject: [PATCH 0820/1110] drm/amd/dal: Define new ipp functions for diags
-
-Define new ipp functions for diags, created new file
-hw_shared.h for types shared between different
-virtual HW blocks. Minor clean up.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c     |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  4 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |  2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c |  6 +-
- .../drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c   |  6 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h       |  2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c   |  6 +-
- drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h       |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h         | 74 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               | 41 +++++++++---
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               | 68 +++++++-------------
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |  8 ---
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  | 11 ----
- 14 files changed, 146 insertions(+), 88 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-index e3a41b3..2fc1809 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-@@ -1287,7 +1287,7 @@ static bool convert_to_custom_float(
- 	return true;
- }
- 
--void calculate_regamma_params(struct regamma_params *params,
-+void calculate_regamma_params(struct pwl_params *params,
- 		struct temp_params *temp_params,
- 		const struct core_gamma *ramp,
- 		const struct core_surface *surface)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 79ab334..76c2cad 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -500,7 +500,7 @@ static bool set_gamma_ramp(
- 	const struct core_surface *surface)
- {
- 	struct ipp_prescale_params *prescale_params;
--	struct regamma_params *regamma_params;
-+	struct pwl_params *regamma_params;
- 	struct temp_params *temp_params;
- 	bool result = false;
- 
-@@ -511,7 +511,7 @@ static bool set_gamma_ramp(
- 		goto prescale_alloc_fail;
- 
- 	regamma_params = dm_alloc(opp->ctx,
--			sizeof(struct regamma_params));
-+			sizeof(struct pwl_params));
- 	if (regamma_params == NULL)
- 		goto regamma_alloc_fail;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index fada94d..cad4efa 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -108,7 +108,7 @@ void dce110_opp_power_on_regamma_lut(
- 
- bool dce110_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
--	const struct regamma_params *params);
-+	const struct pwl_params *params);
- 
- void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
- 		enum opp_regamma mode);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index 88803eb..e4f4fe0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -62,7 +62,7 @@ enum {
-  */
- static void regamma_config_regions_and_segments(
- 	struct dce110_opp *opp110,
--	const struct regamma_params *params)
-+	const struct pwl_params *params)
- {
- 	const struct gamma_curve *curve;
- 	uint32_t value = 0;
-@@ -385,7 +385,7 @@ static void regamma_config_regions_and_segments(
- 
- static void program_pwl(
- 	struct dce110_opp *opp110,
--	const struct regamma_params *params)
-+	const struct pwl_params *params)
- {
- 	uint32_t value;
- 
-@@ -485,7 +485,7 @@ static void program_pwl(
- 
- bool dce110_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
--	const struct regamma_params *params)
-+	const struct pwl_params *params)
- {
- 	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-index 8f4cb96..0004c9e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-@@ -129,7 +129,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
-  *****************************************************************************
-  */
- static void regamma_config_regions_and_segments(
--	struct dce110_opp *opp110, const struct regamma_params *params)
-+	struct dce110_opp *opp110, const struct pwl_params *params)
- {
- 	const struct gamma_curve *curve;
- 	uint32_t value = 0;
-@@ -450,7 +450,7 @@ static void regamma_config_regions_and_segments(
- }
- 
- static void program_pwl(struct dce110_opp *opp110,
--		const struct regamma_params *params)
-+		const struct pwl_params *params)
- {
- 	uint32_t value = 0;
- 
-@@ -493,7 +493,7 @@ static void program_pwl(struct dce110_opp *opp110,
- 
- bool dce110_opp_program_regamma_pwl_v(
- 	struct output_pixel_processor *opp,
--	const struct regamma_params *params)
-+	const struct pwl_params *params)
- {
- 	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-index d78395a..cb257fb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -47,7 +47,7 @@ void dce110_opp_v_set_csc_adjustment(
- 
- bool dce110_opp_program_regamma_pwl_v(
- 	struct output_pixel_processor *opp,
--	const struct regamma_params *params);
-+	const struct pwl_params *params);
- 
- void dce110_opp_power_on_regamma_lut_v(
- 	struct output_pixel_processor *opp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-index db5e0eb..725f18c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-@@ -98,7 +98,7 @@ void dce80_opp_power_on_regamma_lut(
- 
- bool dce80_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
--	const struct regamma_params *pamras);
-+	const struct pwl_params *pamras);
- 
- void dce80_opp_set_regamma_mode(struct output_pixel_processor *opp,
- 		enum opp_regamma mode);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-index ef95e98..5b9663c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-@@ -67,7 +67,7 @@ struct curve_config {
-  *****************************************************************************
-  */
- static void regamma_config_regions_and_segments(
--	struct dce80_opp *opp80, const struct regamma_params *params)
-+	struct dce80_opp *opp80, const struct pwl_params *params)
- {
- 	const struct gamma_curve *curve;
- 	uint32_t value = 0;
-@@ -390,7 +390,7 @@ static void regamma_config_regions_and_segments(
- 
- static void program_pwl(
- 	struct dce80_opp *opp80,
--	const struct regamma_params *params)
-+	const struct pwl_params *params)
- {
- 	uint32_t value;
- 
-@@ -517,7 +517,7 @@ void dce80_opp_power_on_regamma_lut(
- 
- bool dce80_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
--	const struct regamma_params *params)
-+	const struct pwl_params *params)
- {
- 
- 	struct dce80_opp *opp80 = TO_DCE80_OPP(opp);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-index 4e35960..baab77a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-@@ -23,7 +23,7 @@ struct temp_params {
- 
- };
- 
--void calculate_regamma_params(struct regamma_params *params,
-+void calculate_regamma_params(struct pwl_params *params,
- 		struct temp_params *temp_params,
- 		const struct core_gamma *ramp,
- 		const struct core_surface *surface);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h
-new file mode 100644
-index 0000000..3b0e616
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_SHARED_H__
-+#define __DAL_HW_SHARED_H__
-+
-+/******************************************************************************
-+ * Data types shared between different Virtual HW blocks
-+ ******************************************************************************/
-+struct gamma_curve {
-+	uint32_t offset;
-+	uint32_t segments_num;
-+};
-+
-+struct curve_points {
-+	struct fixed31_32 x;
-+	struct fixed31_32 y;
-+	struct fixed31_32 offset;
-+	struct fixed31_32 slope;
-+
-+	uint32_t custom_float_x;
-+	uint32_t custom_float_y;
-+	uint32_t custom_float_offset;
-+	uint32_t custom_float_slope;
-+};
-+
-+struct pwl_result_data {
-+	struct fixed31_32 red;
-+	struct fixed31_32 green;
-+	struct fixed31_32 blue;
-+
-+	struct fixed31_32 delta_red;
-+	struct fixed31_32 delta_green;
-+	struct fixed31_32 delta_blue;
-+
-+	uint32_t red_reg;
-+	uint32_t green_reg;
-+	uint32_t blue_reg;
-+
-+	uint32_t delta_red_reg;
-+	uint32_t delta_green_reg;
-+	uint32_t delta_blue_reg;
-+};
-+
-+struct pwl_params {
-+	uint32_t *data;
-+	struct gamma_curve arr_curve_points[16];
-+	struct curve_points arr_points[3];
-+	struct pwl_result_data rgb_resulted[256 + 3];
-+	uint32_t hw_points_num;
-+};
-+#endif /* __DAL_HW_SHARED_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index 4599d68..9081820 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -27,11 +27,7 @@
- #ifndef __DAL_IPP_H__
- #define __DAL_IPP_H__
- 
--#include "include/grph_object_id.h"
--#include "include/video_csc_types.h"
--#include "include/hw_sequencer_types.h"
--
--struct dev_c_lut;
-+#include "hw_shared.h"
- 
- #define MAXTRIX_COEFFICIENTS_NUMBER 12
- #define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
-@@ -78,9 +74,20 @@ struct dcp_video_matrix {
- 	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
- };
- 
-+enum expansion_mode {
-+	EXPANSION_MODE_ZERO,
-+	EXPANSION_MODE_DYNAMIC
-+};
-+
-+enum ipp_output_format {
-+	IPP_OUTPUT_FORMAT_12_BIT_FIX,
-+	IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
-+	IPP_OUTPUT_FORMAT_FLOAT
-+};
-+
- struct ipp_funcs {
- 
--	/* CURSOR RELATED */
-+	/*** cursor ***/
- 	bool (*ipp_cursor_set_position)(
- 		struct input_pixel_processor *ipp,
- 		const struct dc_cursor_position *position);
-@@ -89,14 +96,30 @@ struct ipp_funcs {
- 		struct input_pixel_processor *ipp,
- 		const struct dc_cursor_attributes *attributes);
- 
--	/* DEGAMMA RELATED */
-+	/*** setup input pixel processing ***/
-+
-+	/* put the entire pixel processor to bypass */
-+	void (*ipp_full_bypass)(struct input_pixel_processor *ipp);
-+
-+	/* setup ipp to expand/convert input to pixel processor internal format */
-+	void (*ipp_setup)(
-+		enum surface_pixel_format input_format,
-+		enum expansion_mode mode,
-+		enum ipp_output_format output_format);
-+
-+	/* DCE function to setup IPP.  TODO: see if we can consolidate to setup */
-+	void (*ipp_program_prescale)(
-+			struct input_pixel_processor *ipp,
-+			struct ipp_prescale_params *params);
-+
-+	/*** DEGAMMA RELATED ***/
- 	bool (*ipp_set_degamma)(
- 		struct input_pixel_processor *ipp,
- 		enum ipp_degamma_mode mode);
- 
--	void (*ipp_program_prescale)(
-+	bool (*ipp_program_degamma_pwl)(
- 		struct input_pixel_processor *ipp,
--		struct ipp_prescale_params *params);
-+		const struct pwl_params *params);
- 
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 3d8fe0d..5335b0e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -30,6 +30,7 @@
- #include "grph_object_id.h"
- #include "video_csc_types.h"
- #include "hw_sequencer_types.h"
-+#include "hw_shared.h"
- 
- struct fixed31_32;
- struct gamma_parameters;
-@@ -116,47 +117,12 @@ enum wide_gamut_regamma_mode {
- 	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
- };
- 
--struct pwl_result_data {
--	struct fixed31_32 red;
--	struct fixed31_32 green;
--	struct fixed31_32 blue;
--
--	struct fixed31_32 delta_red;
--	struct fixed31_32 delta_green;
--	struct fixed31_32 delta_blue;
--
--	uint32_t red_reg;
--	uint32_t green_reg;
--	uint32_t blue_reg;
--
--	uint32_t delta_red_reg;
--	uint32_t delta_green_reg;
--	uint32_t delta_blue_reg;
--};
--
- struct gamma_pixel {
- 	struct fixed31_32 r;
- 	struct fixed31_32 g;
- 	struct fixed31_32 b;
- };
- 
--struct gamma_curve {
--	uint32_t offset;
--	uint32_t segments_num;
--};
--
--struct curve_points {
--	struct fixed31_32 x;
--	struct fixed31_32 y;
--	struct fixed31_32 offset;
--	struct fixed31_32 slope;
--
--	uint32_t custom_float_x;
--	uint32_t custom_float_y;
--	uint32_t custom_float_offset;
--	uint32_t custom_float_slope;
--};
--
- enum channel_name {
- 	CHANNEL_NAME_RED,
- 	CHANNEL_NAME_GREEN,
-@@ -260,14 +226,6 @@ enum fmt_stereo_action {
- 	FMT_STEREO_ACTION_UPDATE_POLARITY
- };
- 
--struct regamma_params {
--	uint32_t *data;
--	struct gamma_curve arr_curve_points[16];
--	struct curve_points arr_points[3];
--	struct pwl_result_data rgb_resulted[256 + 3];
--	uint32_t hw_points_num;
--};
--
- enum graphics_csc_adjust_type {
- 	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
- 	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
-@@ -300,6 +258,28 @@ struct opp_grph_csc_adjustment {
- 	int32_t grph_hue;
- };
- 
-+
-+/* Underlay related types */
-+
-+struct hw_adjustment_range {
-+	int32_t hw_default;
-+	int32_t min;
-+	int32_t max;
-+	int32_t step;
-+	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
-+};
-+
-+enum ovl_csc_adjust_item {
-+	OVERLAY_BRIGHTNESS = 0,
-+	OVERLAY_GAMMA,
-+	OVERLAY_CONTRAST,
-+	OVERLAY_SATURATION,
-+	OVERLAY_HUE,
-+	OVERLAY_ALPHA,
-+	OVERLAY_ALPHA_PER_PIX,
-+	OVERLAY_COLOR_TEMPERATURE
-+};
-+
- struct opp_funcs {
- 	void (*opp_power_on_regamma_lut)(
- 		struct output_pixel_processor *opp,
-@@ -307,7 +287,7 @@ struct opp_funcs {
- 
- 	bool (*opp_program_regamma_pwl)(
- 		struct output_pixel_processor *opp,
--		const struct regamma_params *params);
-+		const struct pwl_params *params);
- 
- 	void (*opp_set_regamma_mode)(struct output_pixel_processor *opp,
- 			enum opp_regamma mode);
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index ad7b906..9e32674 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -293,12 +293,4 @@ enum channel_command_type {
- #define	TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
- #define	NATIVE_HDMI_MAX_PIXEL_CLOCK_IN_KHZ 297000
- 
--struct hw_adjustment_range {
--	int32_t hw_default;
--	int32_t min;
--	int32_t max;
--	int32_t step;
--	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
--};
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index 515f75b..d8526d3 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -107,17 +107,6 @@ struct ovl_csc_adjustment {
- 
- };
- 
--enum ovl_csc_adjust_item {
--	OVERLAY_BRIGHTNESS = 0,
--	OVERLAY_GAMMA,
--	OVERLAY_CONTRAST,
--	OVERLAY_SATURATION,
--	OVERLAY_HUE,
--	OVERLAY_ALPHA,
--	OVERLAY_ALPHA_PER_PIX,
--	OVERLAY_COLOR_TEMPERATURE
--};
--
- struct input_csc_matrix {
- 	enum color_space color_space;
- 	uint16_t regval[12];
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0821-drm-amd-dal-simplify-OPP-header-include-dependency.patch b/common/recipes-kernel/linux/files/0821-drm-amd-dal-simplify-OPP-header-include-dependency.patch
deleted file mode 100644
index aeb61226..00000000
--- a/common/recipes-kernel/linux/files/0821-drm-amd-dal-simplify-OPP-header-include-dependency.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From b1ad4ec8f523a55248341f96888b97b691dc3702 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 19 Feb 2016 14:59:43 -0500
-Subject: [PATCH 0821/1110] drm/amd/dal: simplify OPP header include dependency
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 1 +
- drivers/gpu/drm/amd/dal/dc/inc/opp.h          | 4 ----
- 2 files changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 107636a..03a3161 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -30,6 +30,7 @@
- #include "stream_encoder.h"
- #include "opp.h"
- #include "transform.h"
-+#include "video_csc_types.h"
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
- #include "dce80/dce80_resource.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index 5335b0e..f0c852a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -26,10 +26,6 @@
- #ifndef __DAL_OPP_H__
- #define __DAL_OPP_H__
- 
--#include "dc_types.h"
--#include "grph_object_id.h"
--#include "video_csc_types.h"
--#include "hw_sequencer_types.h"
- #include "hw_shared.h"
- 
- struct fixed31_32;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0822-drm-amd-dal-refactor-transform-header-for-HW-pseudoc.patch b/common/recipes-kernel/linux/files/0822-drm-amd-dal-refactor-transform-header-for-HW-pseudoc.patch
deleted file mode 100644
index 225230c8..00000000
--- a/common/recipes-kernel/linux/files/0822-drm-amd-dal-refactor-transform-header-for-HW-pseudoc.patch
+++ /dev/null
@@ -1,178 +0,0 @@
-From e36522a24e9c8e8bb6e9505b9993077560636804 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 19 Feb 2016 15:55:51 -0500
-Subject: [PATCH 0822/1110] drm/amd/dal: refactor transform header for HW
- pseudocode
-
-Make transform.h self contained, meaning all types used in this
-file are defined in the file itself or in dc_hw_types.h, this
-way HW team can see everything they need from the HW headers
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c   |  1 -
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h |  2 --
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h         | 10 ++++++++++
- drivers/gpu/drm/amd/dal/dc/dc_types.h            | 14 -------------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h      |  1 +
- drivers/gpu/drm/amd/dal/dc/inc/transform.h       | 25 +++++++++++++++++++++++-
- drivers/gpu/drm/amd/dal/include/scaler_types.h   | 17 ----------------
- 7 files changed, 35 insertions(+), 35 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-index 2fc1809..6f0f64a 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-@@ -25,7 +25,6 @@
- 
- #include "dm_services.h"
- #include "gamma_calcs.h"
--#include "core_types.h"
- 
- struct curve_config {
- 	uint32_t offset;
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
-index 668691d..220b736 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
-@@ -38,8 +38,6 @@ struct scaler_filter_params {
- 	} flags;
- };
- 
--struct q31_32;
--
- struct scaler_filter {
- 	struct scaler_filter_params params;
- 	uint32_t src_size;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index f11a78d..d1d2f57 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -373,5 +373,15 @@ enum dc_color_depth {
- 	COLOR_DEPTH_COUNT
- };
- 
-+/* XFM */
-+
-+/* used in  struct dc_surface */
-+struct scaling_taps {
-+	uint32_t v_taps;
-+	uint32_t h_taps;
-+	uint32_t v_taps_c;
-+	uint32_t h_taps_c;
-+};
-+
- #endif /* DC_HW_TYPES_H */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index bcbb911..219fe77 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -172,20 +172,6 @@ struct dc_edid_caps {
- 	uint8_t lte_340mcsc_scramble;
- };
- 
--struct scaling_taps {
--	uint32_t v_taps;
--	uint32_t h_taps;
--	uint32_t v_taps_c;
--	uint32_t h_taps_c;
--};
--
--struct scaling_ratios {
--	struct fixed31_32 horz;
--	struct fixed31_32 vert;
--	struct fixed31_32 horz_c;
--	struct fixed31_32 vert_c;
--};
--
- struct view {
- 	uint32_t width;
- 	uint32_t height;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index d638054..ff34292 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -231,6 +231,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
- 
- /********** DAL Core*********************/
- #include "display_clock_interface.h"
-+#include "transform.h"
- 
- struct resource_pool;
- struct validate_context;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 47adc1d..87dbff3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -28,7 +28,6 @@
- 
- #include "include/scaler_types.h"
- #include "calcs/scaler_filter.h"
--#include "grph_object_id.h"
- 
- struct bit_depth_reduction_params;
- 
-@@ -135,6 +134,30 @@ struct xfm_grph_csc_adjustment {
- 	enum graphics_gamut_adjust_type gamut_adjust_type;
- };
- 
-+/*overscan or window*/
-+struct overscan_info {
-+	uint32_t left;
-+	uint32_t right;
-+	uint32_t top;
-+	uint32_t bottom;
-+};
-+
-+struct scaling_ratios {
-+	struct fixed31_32 horz;
-+	struct fixed31_32 vert;
-+	struct fixed31_32 horz_c;
-+	struct fixed31_32 vert_c;
-+};
-+
-+struct scaler_data {
-+	struct overscan_info overscan;
-+	struct scaling_taps taps;
-+	struct rect viewport;
-+	struct scaling_ratios ratios;
-+
-+	enum pixel_format format;
-+};
-+
- struct transform_funcs {
- 	bool (*transform_power_up)(
- 		struct transform *xfm);
-diff --git a/drivers/gpu/drm/amd/dal/include/scaler_types.h b/drivers/gpu/drm/amd/dal/include/scaler_types.h
-index 3947776..0a31277 100644
---- a/drivers/gpu/drm/amd/dal/include/scaler_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/scaler_types.h
-@@ -28,23 +28,6 @@
- 
- #include "dc_types.h"
- 
--/*overscan or window*/
--struct overscan_info {
--	uint32_t left;
--	uint32_t right;
--	uint32_t top;
--	uint32_t bottom;
--};
--
--struct scaler_data {
--	struct overscan_info overscan;
--	struct scaling_taps taps;
--	struct rect viewport;
--	struct scaling_ratios ratios;
--
--	enum pixel_format format;
--};
--
- struct init_int_and_frac {
- 	uint32_t integer;
- 	uint32_t fraction;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0823-drm-amd-dal-Correctly-attach-surfaces-to-context-at-.patch b/common/recipes-kernel/linux/files/0823-drm-amd-dal-Correctly-attach-surfaces-to-context-at-.patch
deleted file mode 100644
index c597c447..00000000
--- a/common/recipes-kernel/linux/files/0823-drm-amd-dal-Correctly-attach-surfaces-to-context-at-.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 13d8cf5d9a728218d5e96222eb87c1498f4039af Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Fri, 19 Feb 2016 17:13:14 -0500
-Subject: [PATCH 0823/1110] drm/amd/dal: Correctly attach surfaces to context
- at validate
-
-DCE8, and 10 were missed previously.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 8 +++++++-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c   | 8 +++++++-
- 2 files changed, 14 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index f241318..d2ea0a0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -891,10 +891,16 @@ enum dc_status dce100_validate_with_context(
- 						== context->targets[i]) {
- 				unchanged = true;
- 				set_target_unchanged(context, i);
-+				attach_surfaces_to_context(
-+					(struct dc_surface **)dc->current_context.
-+						target_status[j].surfaces,
-+					dc->current_context.target_status[j].surface_count,
-+					&context->targets[i]->public,
-+					context);
- 				context->target_status[i] =
- 					dc->current_context.target_status[j];
- 			}
--		if (!unchanged)
-+		if (!unchanged || set[i].surface_count != 0)
- 			if (!attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index ed143f4..c645d25 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -1006,10 +1006,16 @@ enum dc_status dce80_validate_with_context(
- 						== context->targets[i]) {
- 				unchanged = true;
- 				set_target_unchanged(context, i);
-+				attach_surfaces_to_context(
-+					(struct dc_surface **)dc->current_context.
-+						target_status[j].surfaces,
-+					dc->current_context.target_status[j].surface_count,
-+					&context->targets[i]->public,
-+					context);
- 				context->target_status[i] =
- 					dc->current_context.target_status[j];
- 			}
--		if (!unchanged)
-+		if (!unchanged || set[i].surface_count != 0)
- 			if (!attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch b/common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch
deleted file mode 100644
index 9298275b..00000000
--- a/common/recipes-kernel/linux/files/0824-drm-amd-dal-fix-stack-corruption-during-timing-sync.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From e16926637ab52359896219cab89e4a4bd78c8e87 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 19 Feb 2016 05:45:19 -0500
-Subject: [PATCH 0824/1110] drm/amd/dal: fix stack corruption during timing
- sync
-
-Issue happens when more than 3 displays enabled. During
-fbdev initialization one surface allocated with smallest
-size selected among available displays. This is why same
-timing set on all displays and decided to enable timing sync.
-
-Array on stack was for 3 elements only. Now it is allocated
-in heap with size relevant to number of targets
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 1d1cd89..666e248 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -470,7 +470,7 @@ static void program_timing_sync(
- 	uint8_t j;
- 	uint8_t group_size = 0;
- 	uint8_t tg_count = ctx->res_ctx.pool.pipe_count;
--	struct timing_generator *tg_set[3];
-+	struct timing_generator *tg_set[MAX_PIPES];
- 
- 	for (i = 0; i < tg_count; i++) {
- 		if (!ctx->res_ctx.pipe_ctx[i].stream)
-@@ -487,8 +487,7 @@ static void program_timing_sync(
- 				continue;
- 
- 			if (is_same_timing(
--				&ctx->res_ctx.pipe_ctx[j].stream->public
--								.timing,
-+				&ctx->res_ctx.pipe_ctx[j].stream->public.timing,
- 				&ctx->res_ctx.pipe_ctx[i].stream->public
- 								.timing)) {
- 				tg_set[group_size] =
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0825-drm-amd-amdgpu-Route-dal-i2c-through-drm-s-i2cadapte.patch b/common/recipes-kernel/linux/files/0825-drm-amd-amdgpu-Route-dal-i2c-through-drm-s-i2cadapte.patch
deleted file mode 100644
index 90552fca..00000000
--- a/common/recipes-kernel/linux/files/0825-drm-amd-amdgpu-Route-dal-i2c-through-drm-s-i2cadapte.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 3273b17218edaeb42526187dd77fe0f87992e063 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 18 Feb 2016 15:46:44 -0500
-Subject: [PATCH 0825/1110] drm/amd/amdgpu: Route dal i2c through drm's
- i2cadapter
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 61c2345..076d2c0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -521,6 +521,12 @@ struct amdgpu_dm_dp_aux {
- 	uint32_t link_index;
- };
- 
-+struct amdgpu_i2c_adapter {
-+	struct i2c_adapter base;
-+	struct amdgpu_display_manager *dm;
-+	uint32_t link_index;
-+};
-+
- #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
- 
- struct amdgpu_connector {
-@@ -559,6 +565,9 @@ struct amdgpu_connector {
- 	bool is_mst_connector;
- 	struct amdgpu_encoder *mst_encoder;
- 	struct semaphore mst_sem;
-+
-+	/* TODO see if we can merge with ddc_bus or make a dm_connector */
-+	struct amdgpu_i2c_adapter *i2c;
- };
- 
- /* TODO: start to use this struct and remove same field from base one */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0826-drm-amd-dal-address-missed-change-from-ipp-refactor.patch b/common/recipes-kernel/linux/files/0826-drm-amd-dal-address-missed-change-from-ipp-refactor.patch
deleted file mode 100644
index 71eb42be..00000000
--- a/common/recipes-kernel/linux/files/0826-drm-amd-dal-address-missed-change-from-ipp-refactor.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 364ebd75c2247359f7c48320dfbfbc85a284a725 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 22 Feb 2016 13:36:26 -0500
-Subject: [PATCH 0826/1110] drm/amd/dal: address missed change from ipp
- refactor
-
-The degamma mode enum was refactored, the usage wasn't
-change accordingly, causing asserts
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-index fb90a6a..5d0fc59 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
-@@ -67,7 +67,7 @@ bool dce110_ipp_set_degamma(
- 	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
- 
- 	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||
--			mode == IPP_DEGAMMA_MODE_USER_PWL);
-+			mode == IPP_DEGAMMA_MODE_HW_sRGB);
- 
- 	set_reg_field_value(
- 		value,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0827-drm-amd-dal-Route-i2c-through-drm-s-i2cadapter.patch b/common/recipes-kernel/linux/files/0827-drm-amd-dal-Route-i2c-through-drm-s-i2cadapter.patch
deleted file mode 100644
index 16e2c74c..00000000
--- a/common/recipes-kernel/linux/files/0827-drm-amd-dal-Route-i2c-through-drm-s-i2cadapter.patch
+++ /dev/null
@@ -1,682 +0,0 @@
-From c0da0066c05d0e388a3e6a632ae61fab62f46ff5 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Thu, 18 Feb 2016 15:45:33 -0500
-Subject: [PATCH 0827/1110] drm/amd/dal: Route i2c through drm's i2cadapter
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  |  31 +++++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  74 +++++++++++-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      |   1 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  15 +++
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |   1 +
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      |  72 ++++--------
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   4 +
- drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h          | 129 +++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   3 +
- drivers/gpu/drm/amd/dal/dc/dm_helpers.h            |   5 +
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.h              |   7 --
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h       |   1 +
- .../gpu/drm/amd/dal/include/ddc_service_types.h    |  30 -----
- drivers/gpu/drm/amd/dal/include/gpio_types.h       |   4 -
- drivers/gpu/drm/amd/dal/include/i2caux_interface.h |  23 ----
- 15 files changed, 282 insertions(+), 118 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index bbc60a6..97a3206 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -26,6 +26,7 @@
- #include <linux/string.h>
- #include <linux/acpi.h>
- #include <linux/version.h>
-+#include <linux/i2c.h>
- 
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
-@@ -498,3 +499,33 @@ bool dm_helper_dp_write_dpcd(
- 	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
- 			address, (uint8_t *)data, size) > 0;
- }
-+
-+bool dm_helpers_submit_i2c(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		struct i2c_command *cmd)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+	struct i2c_msg *msgs;
-+	int i = 0;
-+	int num = cmd->number_of_payloads;
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	msgs = kzalloc(num * sizeof(struct i2c_msg), GFP_KERNEL);
-+
-+	for (i = 0; i < num; i++) {
-+		msgs[i].flags = cmd->payloads[i].write ? I2C_M_RD : 0;
-+		msgs[i].addr = cmd->payloads[i].address;
-+		msgs[i].len = cmd->payloads[i].length;
-+		msgs[i].buf = cmd->payloads[i].data;
-+	}
-+
-+	return i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index df7afc9..84ce0bb 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1808,6 +1808,58 @@ void amdgpu_dm_connector_init_helper(
- 				0);
- }
- 
-+int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
-+		      struct i2c_msg *msgs, int num)
-+{
-+	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
-+	struct i2c_command cmd;
-+	int i;
-+
-+	cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
-+	cmd.number_of_payloads = num;
-+	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
-+	cmd.speed = 100;
-+
-+	for (i = 0; i < num; i++) {
-+		cmd.payloads[i].write = (msgs[i].flags & I2C_M_RD);
-+		cmd.payloads[i].address = msgs[i].addr;
-+		cmd.payloads[i].length = msgs[i].len;
-+		cmd.payloads[i].data = msgs[i].buf;
-+	}
-+
-+	if (dc_submit_i2c(i2c->dm->dc, i2c->link_index, &cmd))
-+		return num;
-+	else
-+		return -EIO;
-+}
-+
-+u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
-+{
-+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
-+	.master_xfer = amdgpu_dm_i2c_xfer,
-+	.functionality = amdgpu_dm_i2c_func,
-+};
-+
-+struct amdgpu_i2c_adapter *create_i2c(unsigned int link_index, struct amdgpu_display_manager *dm, int *res)
-+{
-+	struct amdgpu_i2c_adapter *i2c;
-+
-+	i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL);
-+	i2c->dm = dm;
-+	i2c->base.owner = THIS_MODULE;
-+	i2c->base.class = I2C_CLASS_DDC;
-+	i2c->base.dev.parent = &dm->adev->pdev->dev;
-+	i2c->base.algo = &amdgpu_dm_i2c_algo;
-+	snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
-+	i2c->link_index = link_index;
-+	i2c_set_adapdata(&i2c->base, i2c);
-+
-+	return i2c;
-+}
-+
- /* Note: this function assumes that dc_link_detect() was called for the
-  * dc_link which will be represented by this aconnector. */
- int amdgpu_dm_connector_init(
-@@ -1816,12 +1868,23 @@ int amdgpu_dm_connector_init(
- 	uint32_t link_index,
- 	struct amdgpu_encoder *aencoder)
- {
--	int res, connector_type;
-+	int res = 0;
-+	int connector_type;
- 	struct dc *dc = dm->dc;
- 	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
-+	struct amdgpu_i2c_adapter *i2c;
- 
- 	DRM_DEBUG_KMS("%s()\n", __func__);
- 
-+	i2c = create_i2c(link->link_index, dm, &res);
-+	aconnector->i2c = i2c;
-+	res = i2c_add_adapter(&i2c->base);
-+
-+	if (res) {
-+		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
-+		goto out_free;
-+	}
-+
- 	connector_type = to_drm_connector_type(link->connector_signal);
- 
- 	res = drm_connector_init(
-@@ -1833,7 +1896,7 @@ int amdgpu_dm_connector_init(
- 	if (res) {
- 		DRM_ERROR("connector_init failed\n");
- 		aconnector->connector_id = -1;
--		return res;
-+		goto out_free;
- 	}
- 
- 	drm_connector_helper_add(
-@@ -1877,7 +1940,12 @@ int amdgpu_dm_connector_init(
- 	}
- #endif
- 
--	return 0;
-+out_free:
-+	if (res) {
-+		kfree(i2c);
-+		aconnector->i2c = NULL;
-+	}
-+	return res;
- }
- 
- int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 4ce5f9f..586a5ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -3432,6 +3432,7 @@ static bool i2c_read(
- 		cmd.payloads = payloads;
- 		cmd.number_of_payloads = ARRAY_SIZE(payloads);
- 
-+		/* TODO route this through drm i2c_adapter */
- 		result = dal_i2caux_submit_i2c_command(
- 				dal_adapter_service_get_i2caux(bp->as),
- 				ddc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 666e248..8ca8121 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -817,6 +817,21 @@ bool dc_write_dpcd(
- 	return r == DDC_RESULT_SUCESSFULL;
- }
- 
-+bool dc_submit_i2c(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		struct i2c_command *cmd)
-+{
-+	struct core_link *link =
-+			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
-+	struct ddc_service *ddc = link->ddc;
-+
-+	return dal_i2caux_submit_i2c_command(
-+		dal_adapter_service_get_i2caux(ddc->as),
-+		ddc->ddc_pin,
-+		cmd);
-+}
-+
- bool dc_link_add_remote_sink(const struct dc_link *link, struct dc_sink *sink)
- {
- 	struct core_link *core_link = DC_LINK_TO_LINK(link);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 8203432..054216c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -971,6 +971,7 @@ static bool construct(
- 	ddc_service_init_data.as = as;
- 	ddc_service_init_data.ctx = link->ctx;
- 	ddc_service_init_data.id = link->link_id;
-+	ddc_service_init_data.link = link;
- 	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
- 
- 	link->public.ddc_hw_inst =
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index 62b8c26..f725da7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -24,14 +24,14 @@
-  */
- 
- #include "dm_services.h"
--
-+#include "dm_helpers.h"
- #include "include/adapter_service_interface.h"
- #include "include/ddc_service_types.h"
- #include "include/grph_object_id.h"
- #include "include/dpcd_defs.h"
- #include "include/logger_interface.h"
- #include "include/vector.h"
--
-+#include "core_types.h"
- #include "dc_link_ddc.h"
- 
- #define AUX_POWER_UP_WA_DELAY 500
-@@ -145,37 +145,6 @@ union hdmi_scdc_test_config_Data {
- 
- 
- 
--union ddc_wa {
--	struct {
--		uint32_t DP_SKIP_POWER_OFF:1;
--		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
--	} bits;
--	uint32_t raw;
--};
--
--struct ddc_flags {
--	uint8_t EDID_QUERY_DONE_ONCE:1;
--	uint8_t IS_INTERNAL_DISPLAY:1;
--	uint8_t FORCE_READ_REPEATED_START:1;
--	uint8_t EDID_STRESS_READ:1;
--
--};
--
--struct ddc_service {
--	struct ddc *ddc_pin;
--	struct ddc_flags flags;
--	union ddc_wa wa;
--	enum ddc_transaction_type transaction_type;
--	enum display_dongle_type dongle_type;
--	struct dp_receiver_id_info dp_receiver_id_info;
--	struct adapter_service *as;
--	struct dc_context *ctx;
--
--	uint32_t address;
--	uint32_t edid_buf_len;
--	uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
--};
--
- struct i2c_payloads {
- 	struct vector payloads;
- };
-@@ -312,6 +281,7 @@ static bool construct(
- 	enum connector_id connector_id =
- 		dal_graphics_object_id_get_connector_id(init_data->id);
- 
-+	ddc_service->link = init_data->link;
- 	ddc_service->ctx = init_data->ctx;
- 	ddc_service->as = init_data->as;
- 	ddc_service->ddc_pin = dal_adapter_service_obtain_ddc(
-@@ -474,10 +444,10 @@ static bool i2c_read(
- 		.engine = DDC_I2C_COMMAND_ENGINE,
- 		.speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
- 
--	return dal_i2caux_submit_i2c_command(
--		dal_adapter_service_get_i2caux(ddc->as),
--		ddc->ddc_pin,
--		&command);
-+	return dm_helpers_submit_i2c(
-+			ddc->ctx,
-+			&ddc->link->public,
-+			&command);
- }
- 
- static uint8_t aux_read_edid_block(
-@@ -614,18 +584,18 @@ static uint8_t i2c_read_edid_block(
- 		cmd.payloads = &payloads[1];
- 		cmd.number_of_payloads = 1;
- 
--		if (dal_i2caux_submit_i2c_command(
--			dal_adapter_service_get_i2caux(ddc->as),
--			ddc->ddc_pin,
-+		if (dm_helpers_submit_i2c(
-+			ddc->ctx,
-+			&ddc->link->public,
- 			&cmd)) {
- 
- 			cmd.payloads = &payloads[2];
- 			cmd.number_of_payloads = 1;
- 
--			ret = dal_i2caux_submit_i2c_command(
--				dal_adapter_service_get_i2caux(ddc->as),
--				ddc->ddc_pin,
--				&cmd);
-+			ret = dm_helpers_submit_i2c(
-+					ddc->ctx,
-+					&ddc->link->public,
-+					&cmd);
- 		}
- 
- 	} else {
-@@ -644,10 +614,10 @@ static uint8_t i2c_read_edid_block(
- 			cmd.number_of_payloads = 2;
- 		}
- 
--		ret = dal_i2caux_submit_i2c_command(
--			dal_adapter_service_get_i2caux(ddc->as),
--			ddc->ddc_pin,
--			&cmd);
-+		ret = dm_helpers_submit_i2c(
-+				ddc->ctx,
-+				&ddc->link->public,
-+				&cmd);
- 	}
- 
- 	return ret ? DDC_EDID_BLOCK_SIZE : 0;
-@@ -982,9 +952,9 @@ bool dal_ddc_service_query_ddc_data(
- 		command.number_of_payloads =
- 			dal_ddc_i2c_payloads_get_count(payloads);
- 
--		ret = dal_i2caux_submit_i2c_command(
--				dal_adapter_service_get_i2caux(ddc->as),
--				ddc->ddc_pin,
-+		ret = dm_helpers_submit_i2c(
-+				ddc->ctx,
-+				&ddc->link->public,
- 				&command);
- 
- 		dal_ddc_i2c_payloads_destroy(&payloads);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 9cd239c..40e5883 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -511,5 +511,9 @@ bool dc_write_dpcd(
- 		const uint8_t *data,
- 	uint32_t size);
- 
-+bool dc_submit_i2c(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		struct i2c_command *cmd);
- 
- #endif /* DC_INTERFACE_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
-new file mode 100644
-index 0000000..c74d99c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
-@@ -0,0 +1,129 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef DC_DDC_TYPES_H_
-+#define DC_DDC_TYPES_H_
-+
-+struct i2c_payload {
-+	bool write;
-+	uint8_t address;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+enum i2c_command_engine {
-+	I2C_COMMAND_ENGINE_DEFAULT,
-+	I2C_COMMAND_ENGINE_SW,
-+	I2C_COMMAND_ENGINE_HW
-+};
-+
-+struct i2c_command {
-+	struct i2c_payload *payloads;
-+	uint8_t number_of_payloads;
-+
-+	enum i2c_command_engine engine;
-+
-+	/* expressed in KHz
-+	 * zero means "use default value" */
-+	uint32_t speed;
-+};
-+
-+struct gpio_ddc_hw_info {
-+	bool hw_supported;
-+	uint32_t ddc_channel;
-+};
-+
-+struct ddc {
-+	struct gpio *pin_data;
-+	struct gpio *pin_clock;
-+	struct gpio_ddc_hw_info hw_info;
-+	struct dc_context *ctx;
-+};
-+
-+
-+union ddc_wa {
-+	struct {
-+		uint32_t DP_SKIP_POWER_OFF:1;
-+		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct ddc_flags {
-+	uint8_t EDID_QUERY_DONE_ONCE:1;
-+	uint8_t IS_INTERNAL_DISPLAY:1;
-+	uint8_t FORCE_READ_REPEATED_START:1;
-+	uint8_t EDID_STRESS_READ:1;
-+
-+};
-+
-+enum ddc_transaction_type {
-+	DDC_TRANSACTION_TYPE_NONE = 0,
-+	DDC_TRANSACTION_TYPE_I2C,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
-+};
-+
-+enum display_dongle_type {
-+	DISPLAY_DONGLE_NONE = 0,
-+	/* Active converter types*/
-+	DISPLAY_DONGLE_DP_VGA_CONVERTER,
-+	DISPLAY_DONGLE_DP_DVI_CONVERTER,
-+	DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
-+	DISPLAY_DONGLE_DP_DVI_DONGLE,
-+	DISPLAY_DONGLE_DP_HDMI_DONGLE,
-+	/* Other types of dongle*/
-+	DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
-+};
-+
-+struct dp_receiver_id_info {
-+	uint32_t dpcd_rev;
-+	uint32_t sink_id;
-+	int8_t sink_id_str[6];
-+	int8_t sink_hw_revision;
-+	int8_t sink_fw_revision[2];
-+	uint32_t branch_id;
-+	int8_t branch_name[6];
-+	enum display_dongle_type dongle_type;
-+};
-+
-+struct ddc_service {
-+	struct ddc *ddc_pin;
-+	struct ddc_flags flags;
-+	union ddc_wa wa;
-+	enum ddc_transaction_type transaction_type;
-+	enum display_dongle_type dongle_type;
-+	struct dp_receiver_id_info dp_receiver_id_info;
-+	struct adapter_service *as;
-+	struct dc_context *ctx;
-+	struct core_link *link;
-+
-+	uint32_t address;
-+	uint32_t edid_buf_len;
-+	uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
-+};
-+
-+#endif /* DC_DDC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 219fe77..8d81d08 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -67,6 +67,8 @@ enum dce_environment {
- #define MAX_SURFACE_NUM 2
- #define NUM_PIXEL_FORMATS 10
- 
-+#include "dc_ddc_types.h"
-+
- enum tiling_mode {
- 	TILING_MODE_INVALID,
- 	TILING_MODE_LINEAR,
-@@ -102,6 +104,7 @@ enum plane_stereo_format {
- 	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
- };
- 
-+
- /* TODO: Find way to calculate number of bits
-  *  Please increase if pixel_format enum increases
-  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-index b6ce510..faffc16 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-@@ -95,4 +95,9 @@ bool dm_helper_dp_write_dpcd(
- 		const uint8_t *data,
- 		uint32_t size);
- 
-+bool dm_helpers_submit_i2c(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		struct i2c_command *cmd);
-+
- #endif /* __DM_HELPERS__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
-index 2631571..500c3cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.h
-@@ -26,13 +26,6 @@
- #ifndef __DAL_DDC_H__
- #define __DAL_DDC_H__
- 
--struct ddc {
--	struct gpio *pin_data;
--	struct gpio *pin_clock;
--	struct gpio_ddc_hw_info hw_info;
--	struct dc_context *ctx;
--};
--
- struct ddc *dal_gpio_create_ddc(
- 	struct gpio_service *service,
- 	uint32_t offset,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
-index 18104d6..088afce 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
-@@ -69,6 +69,7 @@ struct ddc_service_init_data {
- 	struct adapter_service *as;
- 	struct graphics_object_id id;
- 	struct dc_context *ctx;
-+	struct core_link *link;
- };
- 
- struct ddc_service *dal_ddc_service_create(
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-index cbdb6df..63dbbc5 100644
---- a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-@@ -52,26 +52,6 @@ enum ddc_service_type {
- 	DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
- };
- 
--enum ddc_transaction_type {
--	DDC_TRANSACTION_TYPE_NONE = 0,
--	DDC_TRANSACTION_TYPE_I2C,
--	DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
--	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
--	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
--};
--
--enum display_dongle_type {
--	DISPLAY_DONGLE_NONE = 0,
--	/* Active converter types*/
--	DISPLAY_DONGLE_DP_VGA_CONVERTER,
--	DISPLAY_DONGLE_DP_DVI_CONVERTER,
--	DISPLAY_DONGLE_DP_HDMI_CONVERTER,
--	/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
--	DISPLAY_DONGLE_DP_DVI_DONGLE,
--	DISPLAY_DONGLE_DP_HDMI_DONGLE,
--	/* Other types of dongle*/
--	DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
--};
- 
- enum dcs_dpcd_revision {
- 	DCS_DPCD_REV_10 = 0x10,
-@@ -130,16 +110,6 @@ struct display_sink_capability {
- 	enum signal_type signal;
- };
- 
--struct dp_receiver_id_info {
--	uint32_t dpcd_rev;
--	uint32_t sink_id;
--	int8_t sink_id_str[6];
--	int8_t sink_hw_revision;
--	int8_t sink_fw_revision[2];
--	uint32_t branch_id;
--	int8_t branch_name[6];
--	enum display_dongle_type dongle_type;
--};
- 
- struct av_sync_data {
- 	uint8_t av_granularity;/* DPCD 00023h */
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_types.h b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-index 6d3214b..62548d6 100644
---- a/drivers/gpu/drm/amd/dal/include/gpio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-@@ -329,10 +329,6 @@ struct gpio_config_data {
- 	} config;
- };
- 
--struct gpio_ddc_hw_info {
--	bool hw_supported;
--	uint32_t ddc_channel;
--};
- 
- struct gpio_ddc_open_options {
- 	bool en_bit_present;
-diff --git a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-index b961d24..ac16fa0 100644
---- a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-@@ -29,29 +29,6 @@
- #include "ddc_interface.h"
- #include "adapter_service_interface.h"
- 
--struct i2c_payload {
--	bool write;
--	uint8_t address;
--	uint8_t length;
--	uint8_t *data;
--};
--
--enum i2c_command_engine {
--	I2C_COMMAND_ENGINE_DEFAULT,
--	I2C_COMMAND_ENGINE_SW,
--	I2C_COMMAND_ENGINE_HW
--};
--
--struct i2c_command {
--	struct i2c_payload *payloads;
--	uint8_t number_of_payloads;
--
--	enum i2c_command_engine engine;
--
--	/* expressed in KHz
--	 * zero means "use default value" */
--	uint32_t speed;
--};
- 
- #define DEFAULT_AUX_MAX_DATA_SIZE 16
- #define AUX_MAX_DEFER_WRITE_RETRY 20
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0828-drm-amd-dal-Remove-wait_for_vblanks-call-on-atomic_c.patch b/common/recipes-kernel/linux/files/0828-drm-amd-dal-Remove-wait_for_vblanks-call-on-atomic_c.patch
deleted file mode 100644
index 3d3971c9..00000000
--- a/common/recipes-kernel/linux/files/0828-drm-amd-dal-Remove-wait_for_vblanks-call-on-atomic_c.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 221c063620a95be63d4e14c2933b1f81999d7452 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 23 Feb 2016 12:14:16 -0500
-Subject: [PATCH 0828/1110] drm/amd/dal: Remove wait_for_vblanks call on
- atomic_commit
-
-It appears to be superfluous, and having the call was causing a performance regression
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Reviewed-by: Tony Cheng <tony.cheng@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 84ce0bb..f469017 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2391,8 +2391,6 @@ int amdgpu_dm_atomic_commit(
- 				0);
- 	}
- 
--	drm_atomic_helper_wait_for_vblanks(dev, state);
--
- 	/* In this state all old framebuffers would be unpinned */
- 
- 	drm_atomic_helper_cleanup_planes(dev, state);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0829-drm-amd-dal-Minor-dm_helper-type-and-include-fixup.patch b/common/recipes-kernel/linux/files/0829-drm-amd-dal-Minor-dm_helper-type-and-include-fixup.patch
deleted file mode 100644
index afc5adb5..00000000
--- a/common/recipes-kernel/linux/files/0829-drm-amd-dal-Minor-dm_helper-type-and-include-fixup.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 88cb1446f04690d894772bf7a8797086e7fc3435 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 17 Feb 2016 15:44:41 -0500
-Subject: [PATCH 0829/1110] drm/amd/dal: Minor dm_helper type and include fixup
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 12 ++++++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c        |  4 ++--
- drivers/gpu/drm/amd/dal/dc/dm_helpers.h               |  4 ++--
- 3 files changed, 12 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index 97a3206..e414861 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -40,6 +40,8 @@
- #include "amdgpu_dm_irq.h"
- #include "amdgpu_dm_types.h"
- 
-+#include "dm_helpers.h"
-+
- /* dm_helpers_parse_edid_caps
-  *
-  * Parse edid caps
-@@ -459,12 +461,13 @@ void dm_helpers_dp_mst_stop_top_mgr(
- #endif
- }
- 
--bool dm_helper_dp_read_dpcd(
-+bool dm_helpers_dp_read_dpcd(
- 		struct dc_context *ctx,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		uint8_t *data,
--		uint32_t size) {
-+		uint32_t size)
-+{
- 
- 
- 	struct amdgpu_device *adev = ctx->driver_context;
-@@ -480,12 +483,13 @@ bool dm_helper_dp_read_dpcd(
- 			data, size) > 0;
- }
- 
--bool dm_helper_dp_write_dpcd(
-+bool dm_helpers_dp_write_dpcd(
- 		struct dc_context *ctx,
- 		const struct dc_link *link,
- 		uint32_t address,
- 		const uint8_t *data,
--		uint32_t size) {
-+		uint32_t size)
-+{
- 
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 04a0c17..f332185 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -19,7 +19,7 @@ enum dc_status core_link_read_dpcd(
- 	uint8_t *data,
- 	uint32_t size)
- {
--	if (!dm_helper_dp_read_dpcd(link->ctx,
-+	if (!dm_helpers_dp_read_dpcd(link->ctx,
- 			&link->public,
- 			address, data, size))
- 			return DC_ERROR_UNEXPECTED;
-@@ -33,7 +33,7 @@ enum dc_status core_link_write_dpcd(
- 	const uint8_t *data,
- 	uint32_t size)
- {
--	if (!dm_helper_dp_write_dpcd(link->ctx,
-+	if (!dm_helpers_dp_write_dpcd(link->ctx,
- 			&link->public,
- 			address, data, size))
- 				return DC_ERROR_UNEXPECTED;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-index faffc16..350dd11 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-@@ -78,7 +78,7 @@ void dm_helpers_dp_mst_stop_top_mgr(
- /**
-  * OS specific aux read callback.
-  */
--bool dm_helper_dp_read_dpcd(
-+bool dm_helpers_dp_read_dpcd(
- 		struct dc_context *ctx,
- 		const struct dc_link *link,
- 		uint32_t address,
-@@ -88,7 +88,7 @@ bool dm_helper_dp_read_dpcd(
- /**
-  * OS specific aux write callback.
-  */
--bool dm_helper_dp_write_dpcd(
-+bool dm_helpers_dp_write_dpcd(
- 		struct dc_context *ctx,
- 		const struct dc_link *link,
- 		uint32_t address,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0830-drm-amd-dal-destruct-validation-context-on-change.patch b/common/recipes-kernel/linux/files/0830-drm-amd-dal-destruct-validation-context-on-change.patch
deleted file mode 100644
index aa6f1216..00000000
--- a/common/recipes-kernel/linux/files/0830-drm-amd-dal-destruct-validation-context-on-change.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From c34a956b526380c7005087299be36e46cc6a57a8 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 22 Feb 2016 05:52:50 -0500
-Subject: [PATCH 0830/1110] drm/amd/dal: destruct validation context on change
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 8ca8121..1d25a39 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -605,6 +605,8 @@ bool dc_commit_targets(
- 		dc_target_retain(&context->targets[i]->public);
- 	}
- 
-+	destruct_val_ctx(&dc->current_context);
-+
- 	dc->current_context = *context;
- 
- 	program_timing_sync(dc->ctx, context);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0831-drm-amdgpu-add-stoney-to-dal-check.patch b/common/recipes-kernel/linux/files/0831-drm-amdgpu-add-stoney-to-dal-check.patch
deleted file mode 100644
index 3851e215..00000000
--- a/common/recipes-kernel/linux/files/0831-drm-amdgpu-add-stoney-to-dal-check.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From d3c290222b8242098807084acf480845c8c2e8d1 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 23 Feb 2016 18:05:41 -0500
-Subject: [PATCH 0831/1110] drm/amdgpu: add stoney to dal check
-
-This seems to have gotten lost at some point.
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 83d02c6..8965358 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1396,6 +1396,7 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- #endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
- 		return amdgpu_dal != 0;
- #endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE10_0)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0832-drm-amd-dal-fix-some-missing-stoney-cases-in-dm.patch b/common/recipes-kernel/linux/files/0832-drm-amd-dal-fix-some-missing-stoney-cases-in-dm.patch
deleted file mode 100644
index 83437516..00000000
--- a/common/recipes-kernel/linux/files/0832-drm-amd-dal-fix-some-missing-stoney-cases-in-dm.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 4c14218c5342df1574ee8403b1f31373331e672a Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 23 Feb 2016 18:08:30 -0500
-Subject: [PATCH 0832/1110] drm/amd/dal: fix some missing stoney cases in dm
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index aa78d6c..67dd7b9 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -286,7 +286,8 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
- 		adev->mode_info.atom_context->bios;
- 	init_data.asic_id.runtime_flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME = 1;
- 
--	if (adev->asic_type == CHIP_CARRIZO)
-+	if ((adev->asic_type == CHIP_CARRIZO) ||
-+	    (adev->asic_type == CHIP_STONEY))
- 		init_data.asic_id.runtime_flags.flags.bits.GNB_WAKEUP_SUPPORTED = 1;
- 
- 	init_data.driver = adev;
-@@ -1003,6 +1004,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
- 	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
- 		if (dce110_register_irq_handlers(dm->adev)) {
- 			DRM_ERROR("DM: Failed to initialize IRQ\n");
- 			return -1;
-@@ -1246,6 +1248,7 @@ static int dm_early_init(void *handle)
- 			adev->mode_info.funcs = &dm_dce_v10_0_display_funcs;
- 		break;
- 	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
- 		adev->mode_info.num_crtc = 3;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 9;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0833-drm-amdgpu-dal-dm-fix-compilation-when-CIK-support-i.patch b/common/recipes-kernel/linux/files/0833-drm-amdgpu-dal-dm-fix-compilation-when-CIK-support-i.patch
deleted file mode 100644
index 244977a4..00000000
--- a/common/recipes-kernel/linux/files/0833-drm-amdgpu-dal-dm-fix-compilation-when-CIK-support-i.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 5a9b8f9b9274bfda316cdca31306dc5a27a5215d Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 25 Feb 2016 16:24:46 -0500
-Subject: [PATCH 0833/1110] drm/amdgpu/dal/dm: fix compilation when CIK support
- is disabled
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Protect the dce8 stuff shared with non-DAL with the CIK config
-flag.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 67dd7b9..7f6325c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -36,7 +36,9 @@
- #include "amdgpu_dm_irq.h"
- #include "dm_helpers.h"
- 
-+#ifdef CONFIG_DRM_AMDGPU_CIK
- #include "dce_v8_0.h"
-+#endif
- #include "dce_v10_0.h"
- #include "dce_v11_0.h"
- 
-@@ -1158,6 +1160,7 @@ static void dm_page_flip(struct amdgpu_device *adev,
- 			&addr, 1);
- }
- 
-+#ifdef CONFIG_DRM_AMDGPU_CIK
- static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = {
- 	.set_vga_render_state = dce_v8_0_set_vga_render_state,
- 	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-@@ -1179,6 +1182,7 @@ static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = {
- 	.stop_mc_access = dce_v8_0_stop_mc_access, /* called unconditionally */
- 	.resume_mc_access = dce_v8_0_resume_mc_access, /* called unconditionally */
- };
-+#endif
- 
- static const struct amdgpu_display_funcs dm_dce_v10_0_display_funcs = {
- 	.set_vga_render_state = dce_v10_0_set_vga_render_state,
-@@ -1236,8 +1240,10 @@ static int dm_early_init(void *handle)
- 		adev->mode_info.num_crtc = 6;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 6;
-+#ifdef CONFIG_DRM_AMDGPU_CIK
- 		if (adev->mode_info.funcs == NULL)
- 			adev->mode_info.funcs = &dm_dce_v8_0_display_funcs;
-+#endif
- 		break;
- 	case CHIP_FIJI:
- 	case CHIP_TONGA:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0834-drm-amd-amdgpu-resume-displays-after-cursor-pin.patch b/common/recipes-kernel/linux/files/0834-drm-amd-amdgpu-resume-displays-after-cursor-pin.patch
deleted file mode 100644
index 36a6514c..00000000
--- a/common/recipes-kernel/linux/files/0834-drm-amd-amdgpu-resume-displays-after-cursor-pin.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From ab819a7405fb30117339ce7245050bb3b3a935f3 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 26 Feb 2016 11:27:34 -0500
-Subject: [PATCH 0834/1110] drm/amd/amdgpu: resume displays after cursor pin
-
-This will prevent cursor corruption on resume from
-S3 by turning on displays after cursor buffer pin.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  6 ++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  8 ++++++++
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++----
- 3 files changed, 26 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index d34b64e..1b22de0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2433,5 +2433,11 @@ struct amdgpu_bo_va_mapping *
- amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
- 		       uint64_t addr, struct amdgpu_bo **bo);
- 
-+#if defined(CONFIG_DRM_AMD_DAL)
-+int amdgpu_dm_display_resume(struct amdgpu_device *adev );
-+#else
-+static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
-+#endif
-+
- #include "amdgpu_object.h"
- #endif
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 8965358..356e2ea 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1860,6 +1860,14 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
- 				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
- 			}
- 			drm_modeset_unlock_all(dev);
-+		} else {
-+			/*
-+			 * There is no equivalent atomic helper to turn on
-+			 * display, so we defined our own function for this,
-+			 * once suspend resume is supported by the atomic
-+			 * framework this will be reworked
-+			 */
-+			amdgpu_dm_display_resume(adev);
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 7f6325c..7c3a683 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -575,11 +575,7 @@ err:
- static int dm_resume(void *handle)
- {
- 	struct amdgpu_device *adev = handle;
--	struct drm_device *ddev = adev->ddev;
- 	struct amdgpu_display_manager *dm = &adev->dm;
--	struct amdgpu_connector *aconnector;
--	struct drm_connector *connector;
--	int ret = 0;
- 
- 	/* power on hardware */
- 	dc_set_power_state(
-@@ -587,6 +583,17 @@ static int dm_resume(void *handle)
- 		DC_ACPI_CM_POWER_STATE_D0,
- 		DC_VIDEO_POWER_ON);
- 
-+	return 0;
-+}
-+
-+int amdgpu_dm_display_resume(struct amdgpu_device *adev )
-+{
-+	struct drm_device *ddev = adev->ddev;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector *connector;
-+	int ret = 0;
-+
- 	/* Do detection*/
- 	list_for_each_entry(connector,
- 			&ddev->mode_config.connector_list, head) {
-@@ -610,6 +617,7 @@ static int dm_resume(void *handle)
- 
- 	return ret;
- }
-+
- const struct amd_ip_funcs amdgpu_dm_funcs = {
- 	.early_init = dm_early_init,
- 	.late_init = NULL,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch b/common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch
deleted file mode 100644
index 18c20545..00000000
--- a/common/recipes-kernel/linux/files/0835-drm-amd-dal-allow-DP-non-external-clock-source-shari.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-From 46a67a9539b62458ba7c124a7e2efc3fe2ad271a Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 19 Feb 2016 06:05:08 -0500
-Subject: [PATCH 0835/1110] drm/amd/dal: allow DP non-external clock source
- sharing
-
-In case external clock source is not available DP connections
-could use one PLL
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c           |  3 ++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c        |  1 +
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c      |  5 +++--
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c       | 12 ++++++------
- drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 14 ++++++++++----
- drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h          |  1 +
- 6 files changed, 23 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 054216c..88a4eb9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1151,8 +1151,9 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
- 	/* get link settings for video mode timing */
- 	decide_link_settings(stream, &link_settings);
- 	dp_enable_link_phy(
--		stream->sink->link,
-+		link,
- 		pipe_ctx->signal,
-+		pipe_ctx->clock_source->id,
- 		&link_settings);
- 
- 	panel_mode = dp_get_panel_mode(link);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index ed2add8..e5a63f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1137,6 +1137,7 @@ bool dp_hbr_verify_link_cap(
- 		dp_enable_link_phy(
- 				link,
- 				link->public.connector_signal,
-+				CLOCK_SOURCE_ID_UNDEFINED,
- 				cur);
- 
- 		if (skip_link_training)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index f332185..3f05723 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -54,6 +54,7 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
- void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
-+	enum clock_source_id clock_source,
- 	const struct dc_link_settings *link_settings)
- {
- 	struct link_encoder *link_enc = link->link_enc;
-@@ -67,12 +68,12 @@ void dp_enable_link_phy(
- 		link_enc->funcs->enable_dp_output(
- 						link_enc,
- 						link_settings,
--						CLOCK_SOURCE_ID_EXTERNAL);
-+						clock_source);
- 	} else {
- 		link_enc->funcs->enable_dp_mst_output(
- 						link_enc,
- 						link_settings,
--						CLOCK_SOURCE_ID_EXTERNAL);
-+						clock_source);
- 	}
- 
- 	dp_receiver_power_ctrl(link, true);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 03a3161..42c456a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -106,7 +106,6 @@ static bool is_sharable_clk_src(
- 	const struct pipe_ctx *pipe_with_clk_src,
- 	const struct pipe_ctx *pipe)
- {
--	enum clock_source_id id = pipe_with_clk_src->clock_source->id;
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	enum dce_version dce_ver = dal_adapter_service_get_dce_version(
- 		pipe->stream->sink->link->adapter_srv);
-@@ -114,14 +113,18 @@ static bool is_sharable_clk_src(
- 	/* Currently no clocks are shared for DCE 10 until VBIOS behaviour
- 	 * is verified for this use case
- 	 */
--	if (dce_ver == DCE_VERSION_10_0)
-+	if (dce_ver == DCE_VERSION_10_0 && !dc_is_dp_signal(pipe->signal))
- 		return false;
- #endif
- 
- 	if (pipe_with_clk_src->clock_source == NULL)
- 		return false;
- 
--	if (id == CLOCK_SOURCE_ID_EXTERNAL)
-+	if (dc_is_dp_signal(pipe->signal) &&
-+		dc_is_dp_signal(pipe_with_clk_src->signal))
-+		return true;
-+
-+	if (pipe->signal != pipe_with_clk_src->signal)
- 		return false;
- 
- 	if(!is_same_timing(
-@@ -139,9 +142,6 @@ struct clock_source *find_used_clk_src_for_sharing(
- 	uint8_t i;
- 
- 	for (i = 0; i < MAX_PIPES; i++) {
--		if (res_ctx->pipe_ctx[i].clock_source == NULL)
--			continue;
--
- 		if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
- 			return res_ctx->pipe_ctx[i].clock_source;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index d2ea0a0..c7145c5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -841,14 +841,20 @@ static enum dc_status map_clock_resources(
- 				if (context->res_ctx.pipe_ctx[k].stream != stream)
- 					continue;
- 
-+				/*
-+				 * in this case if external clock source is not
-+				 * available for DP, it will pick-up first
-+				 * available pll from find_first_free_pll
-+				 */
- 				if (dc_is_dp_signal(pipe_ctx->signal)
- 					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source = context->res_ctx.
--						pool.clock_sources[DCE100_CLK_SRC_EXT];
--				else
-+					pipe_ctx->clock_source = context->res_ctx.pool.clock_sources[DCE100_CLK_SRC_EXT];
-+
-+				if (pipe_ctx->clock_source == NULL)
- 					pipe_ctx->clock_source =
- 						find_used_clk_src_for_sharing(
--							&context->res_ctx, pipe_ctx);
-+							&context->res_ctx,
-+							pipe_ctx);
- 
- 				if (pipe_ctx->clock_source == NULL)
- 					pipe_ctx->clock_source =
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-index d56b5d1..d4d9084 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
-@@ -43,6 +43,7 @@ enum dc_status core_link_write_dpcd(
- void dp_enable_link_phy(
- 	struct core_link *link,
- 	enum signal_type signal,
-+	enum clock_source_id clock_source,
- 	const struct dc_link_settings *link_settings);
- 
- void dp_receiver_power_ctrl(struct core_link *link, bool on);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0836-drm-amd-dal-Interface-change-to-commit-multiple-surf.patch b/common/recipes-kernel/linux/files/0836-drm-amd-dal-Interface-change-to-commit-multiple-surf.patch
deleted file mode 100644
index 2719c131..00000000
--- a/common/recipes-kernel/linux/files/0836-drm-amd-dal-Interface-change-to-commit-multiple-surf.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 4abac0d4510dc6600c45bf41b69711e27b5ec94d Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 24 Feb 2016 13:17:45 -0500
-Subject: [PATCH 0836/1110] drm/amd/dal: Interface change to commit multiple
- surfaces.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index dc9f157..42c794a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -140,7 +140,6 @@ static int8_t acquire_first_free_underlay(
- 		struct resource_context *res_ctx,
- 		struct core_stream *stream)
- {
--	BREAK_TO_DEBUGGER();
- 	if (!res_ctx->pipe_ctx[3].stream) {
- 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX];
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0837-drm-amd-dal-fix-4k-DP-displays-link-training.patch b/common/recipes-kernel/linux/files/0837-drm-amd-dal-fix-4k-DP-displays-link-training.patch
deleted file mode 100644
index 80fc21e4..00000000
--- a/common/recipes-kernel/linux/files/0837-drm-amd-dal-fix-4k-DP-displays-link-training.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 6c49ea3b9c564f30cad204670eb3938877785ed7 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 24 Feb 2016 05:51:14 -0500
-Subject: [PATCH 0837/1110] drm/amd/dal: fix 4k DP displays link training
-
-During initial link training of DP SST display
-acquire path for it, to get clock source id
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 61 +++++++++++++++++++++++++++-
- 1 file changed, 60 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index e5a63f4..92d44aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -10,6 +10,8 @@
- #include "core_status.h"
- #include "dpcd_defs.h"
- 
-+#include "core_dc.h"
-+
- /* maximum pre emphasis level allowed for each voltage swing level*/
- static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
- 		PRE_EMPHASIS_LEVEL3,
-@@ -1091,6 +1093,63 @@ static enum dc_link_rate get_max_link_rate(struct core_link *link)
- 	return max_link_rate;
- }
- 
-+static enum clock_source_id get_clock_source_id_for_link_training(
-+	struct core_link *link)
-+{
-+	bool result;
-+	struct dc_sink_init_data init_params = {0};
-+	struct dc_sink *sink;
-+	struct dc_stream *stream;
-+	struct dc_target *target;
-+	struct validate_context *context;
-+	struct dc_validation_set set;
-+	enum clock_source_id id = CLOCK_SOURCE_ID_UNDEFINED;
-+
-+	init_params.link = &link->public;
-+	init_params.sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
-+	sink = dc_sink_create(&init_params);
-+
-+	if (!sink)
-+		goto fail_sink;
-+
-+	stream = dc_create_stream_for_sink(sink);
-+
-+	if (!stream)
-+		goto fail_stream;
-+
-+	target = dc_create_target_for_streams(&stream, 1);
-+
-+	if (!target)
-+		goto fail_target;
-+
-+	set.surface_count = 0;
-+	set.target = target;
-+
-+	context = dm_alloc(link->ctx, sizeof(struct validate_context));
-+
-+	if (!context)
-+		goto fail_context;
-+
-+	result = link->dc->res_pool.funcs->validate_with_context(
-+		link->dc,
-+		&set,
-+		1,
-+		context);
-+
-+	if (result)
-+		id = context->res_ctx.pipe_ctx[0].clock_source->id;
-+
-+	dm_free(link->ctx, context);
-+fail_context:
-+	dc_target_release(target);
-+fail_target:
-+	dc_stream_release(stream);
-+fail_stream:
-+	dc_sink_release(sink);
-+fail_sink:
-+	return id;
-+}
-+
- bool dp_hbr_verify_link_cap(
- 	struct core_link *link,
- 	struct dc_link_settings *known_limit_link_setting)
-@@ -1137,7 +1196,7 @@ bool dp_hbr_verify_link_cap(
- 		dp_enable_link_phy(
- 				link,
- 				link->public.connector_signal,
--				CLOCK_SOURCE_ID_UNDEFINED,
-+				get_clock_source_id_for_link_training(link),
- 				cur);
- 
- 		if (skip_link_training)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0838-drm-amd-dal-minor-mpo-fixes.patch b/common/recipes-kernel/linux/files/0838-drm-amd-dal-minor-mpo-fixes.patch
deleted file mode 100644
index 557e5f99..00000000
--- a/common/recipes-kernel/linux/files/0838-drm-amd-dal-minor-mpo-fixes.patch
+++ /dev/null
@@ -1,498 +0,0 @@
-From beae654b9cd427c3daaacdb4dbbe4b89446428b2 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 18 Feb 2016 17:14:31 -0500
-Subject: [PATCH 0838/1110] drm/amd/dal: minor mpo fixes
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 14 +++--
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 58 +++++++++++++++------
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           |  5 ++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 60 +++++++++++++---------
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 28 ++++++++--
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |  6 ++-
- .../amd/dal/dc/dce110/dce110_timing_generator_v.c  | 18 ++++---
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  1 -
- 8 files changed, 127 insertions(+), 63 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 1d25a39..9ecd60c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -175,14 +175,12 @@ static void init_hw(struct dc *dc)
- 	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		xfm = dc->res_pool.transforms[i];
- 
--		if (i != DCE110_UNDERLAY_IDX) {
--			dc->hwss.enable_display_power_gating(
--					dc->ctx, i, bp,
--					PIPE_GATING_CONTROL_INIT);
--			dc->hwss.enable_display_power_gating(
--					dc->ctx, i, bp,
--					PIPE_GATING_CONTROL_DISABLE);
--		}
-+		dc->hwss.enable_display_power_gating(
-+				dc->ctx, i, bp,
-+				PIPE_GATING_CONTROL_INIT);
-+		dc->hwss.enable_display_power_gating(
-+				dc->ctx, i, bp,
-+				PIPE_GATING_CONTROL_DISABLE);
- 		xfm->funcs->transform_power_up(xfm);
- 		dc->hwss.enable_display_pipe_clock_gating(
- 			dc->ctx,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 42c794a..ac917e5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -136,11 +136,35 @@ target_alloc_fail:
- 	return NULL;
- }
- 
-+/*
-+void ProgramPixelDurationV(unsigned int pixelClockInKHz )
-+{
-+	fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
-+	unsigned int pixDurationInPico = round(pixel_duration);
-+
-+	DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
-+
-+	arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
-+	arb_control.bits.PIXEL_DURATION = pixDurationInPico;
-+	WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
-+
-+	arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
-+	arb_control.bits.PIXEL_DURATION = pixDurationInPico;
-+	WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
-+
-+	WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
-+	WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
-+
-+	WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
-+	WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
-+}
-+*/
- static int8_t acquire_first_free_underlay(
- 		struct resource_context *res_ctx,
- 		struct core_stream *stream)
- {
--	if (!res_ctx->pipe_ctx[3].stream) {
-+	if (!res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX].stream) {
-+		struct dc_bios *dcb;
- 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX];
- 
- 		pipe_ctx->tg = res_ctx->pool.timing_generators[DCE110_UNDERLAY_IDX];
-@@ -151,16 +175,18 @@ static int8_t acquire_first_free_underlay(
- 		pipe_ctx->dis_clk = res_ctx->pool.display_clock;
- 		pipe_ctx->pipe_idx = DCE110_UNDERLAY_IDX;
- 
-+		dcb = dal_adapter_service_get_bios_parser(
-+						res_ctx->pool.adapter_srv);
-+
-+		stream->ctx->dc->hwss.enable_display_power_gating(
-+			stream->ctx->dc->ctx,
-+			DCE110_UNDERLAY_IDX,
-+			dcb, PIPE_GATING_CONTROL_DISABLE);
-+
- 		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
- 			dm_error("DC: failed to blank crtc!\n");
- 			BREAK_TO_DEBUGGER();
--		} else
--			pipe_ctx->flags.blanked = true;
--
--		pipe_ctx->tg->funcs->program_timing(
--				pipe_ctx->tg,
--				&stream->public.timing,
--				true);
-+		}
- 
- 		if (!pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
- 			BREAK_TO_DEBUGGER();
-@@ -190,6 +216,7 @@ bool dc_commit_surfaces_to_target(
- 	struct validate_context *context;
- 	int current_enabled_surface_count = 0;
- 	int new_enabled_surface_count = 0;
-+	bool is_mpo_turning_on = false;
- 
- 	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
- 	*context = dc->current_context;
-@@ -215,10 +242,11 @@ bool dc_commit_surfaces_to_target(
- 			new_enabled_surface_count++;
- 
- 	/* TODO unhack mpo */
--	if (new_surface_count == 2 && target_status->surface_count < 2)
-+	if (new_surface_count == 2 && target_status->surface_count < 2) {
- 		acquire_first_free_underlay(&context->res_ctx,
- 				DC_STREAM_TO_CORE(dc_target->streams[0]));
--	else if (new_surface_count < 2 && target_status->surface_count == 2) {
-+		is_mpo_turning_on = true;
-+	} else if (new_surface_count < 2 && target_status->surface_count == 2) {
- 		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].stream = NULL;
- 		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].surface = NULL;
- 	}
-@@ -253,7 +281,9 @@ bool dc_commit_surfaces_to_target(
- 		goto unexpected_fail;
- 	}
- 
--	if (prev_disp_clk < context->bw_results.dispclk_khz) {
-+	if (prev_disp_clk < context->bw_results.dispclk_khz ||
-+		(is_mpo_turning_on &&
-+			prev_disp_clk == context->bw_results.dispclk_khz)) {
- 		dc->hwss.program_bw(dc, context);
- 		pplib_apply_display_requirements(dc, context,
- 						&context->pp_display_cfg);
-@@ -355,8 +385,7 @@ void dc_target_enable_memory_requests(struct dc_target *dc_target)
- 			if (!tg->funcs->set_blank(tg, false)) {
- 				dm_error("DC: failed to unblank crtc!\n");
- 				BREAK_TO_DEBUGGER();
--			} else
--				res_ctx->pipe_ctx[j].flags.blanked = false;
-+			}
- 		}
- 	}
- }
-@@ -379,8 +408,7 @@ void dc_target_disable_memory_requests(struct dc_target *dc_target)
- 			if (!tg->funcs->set_blank(tg, true)) {
- 				dm_error("DC: failed to blank crtc!\n");
- 				BREAK_TO_DEBUGGER();
--			} else
--				res_ctx->pipe_ctx[j].flags.blanked = true;
-+			}
- 		}
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index d1d2f57..ea8028c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -193,16 +193,19 @@ struct dc_tiling_info {
- 	 *	POSSIBLE VALUES: 1,2,4,8
- 	 */
- 	unsigned int bank_width;
-+	unsigned int bank_width_c;
- 	/* Specifies the number of tiles in the y direction to
- 	 *	be incorporated into the same bank.
- 	 * Only applies to 2D and 3D tiling modes.
- 	 *	POSSIBLE VALUES: 1,2,4,8
- 	 */
- 	unsigned int bank_height;
-+	unsigned int bank_height_c;
- 	/* Specifies the macro tile aspect ratio. Only applies
- 	 * to 2D and 3D tiling modes.
- 	 */
- 	unsigned int tile_aspect;
-+	unsigned int tile_aspect_c;
- 	/* Specifies the number of bytes that will be stored
- 	 *	contiguously for each tile.
- 	 * If the tile data requires more storage than this
-@@ -213,6 +216,7 @@ struct dc_tiling_info {
- 	 * For color render targets, TILE_SPLIT >= 256B.
- 	 */
- 	enum tile_split_values tile_split;
-+	enum tile_split_values tile_split_c;
- 	/* Specifies the addressing within a tile.
- 	 *	0x0 - DISPLAY_MICRO_TILING
- 	 *	0x1 - THIN_MICRO_TILING
-@@ -220,6 +224,7 @@ struct dc_tiling_info {
- 	 *	0x3 - ROTATED_MICRO_TILING
- 	 */
- 	enum tile_mode_values tile_mode;
-+	enum tile_mode_values tile_mode_c;
- 	/* Specifies the number of pipes and how they are
- 	 *	interleaved in the surface.
- 	 * Refer to memory addressing document for complete
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 76c2cad..1e22e59 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -71,17 +71,17 @@ enum blender_mode {
- 
- static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- {
--	.dcfe = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcfe = (mmDCFE0_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
- 	.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- },
- {
--	.dcfe = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcfe = (mmDCFE1_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
- 	.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- },
- {
--	.dcfe = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcfe = (mmDCFE2_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
- 	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- },
-@@ -115,7 +115,6 @@ static void dce110_enable_fe_clock(
- 	uint32_t value = 0;
- 	uint32_t addr;
- 
--	/*TODO: proper offset*/
- 	addr = HW_REG_DCFE(mmDCFE_CLOCK_CONTROL, controller_id);
- 
- 	value = dm_read_reg(ctx, addr);
-@@ -258,6 +257,7 @@ static bool dce110_pipe_control_lock(
- 
- 	dm_write_reg(ctx, addr, value);
- 
-+	need_to_wait = false;/*todo: mpo optimization remove*/
- 	if (!lock && need_to_wait) {
- 		uint8_t counter = 0;
- 		const uint8_t counter_limit = 100;
-@@ -361,25 +361,27 @@ static void dce110_set_blender_mode(
- {
- 	uint32_t value;
- 	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
--	uint32_t blnd_mode;
--	uint32_t feedthrough = 0;
-+	uint32_t alpha_mode = 2;
-+	uint32_t blnd_mode = 0;
-+	uint32_t feedthrough = 1;
-+	uint32_t multiplied_mode = 0;
- 
- 	switch (mode) {
- 	case BLENDER_MODE_OTHER_PIPE:
- 		feedthrough = 0;
-+		alpha_mode = 0;
- 		blnd_mode = 1;
- 		break;
- 	case BLENDER_MODE_BLENDING:
- 		feedthrough = 0;
-+		alpha_mode = 0;
- 		blnd_mode = 2;
-+		multiplied_mode = 1;
- 		break;
- 	case BLENDER_MODE_CURRENT_PIPE:
- 	default:
- 		if (controller_id == DCE110_UNDERLAY_IDX)
- 			feedthrough = 0;
--		else
--			feedthrough = 1;
--		blnd_mode = 0;
- 		break;
- 	}
- 
-@@ -390,12 +392,21 @@ static void dce110_set_blender_mode(
- 		feedthrough,
- 		BLND_CONTROL,
- 		BLND_FEEDTHROUGH_EN);
--
-+	set_reg_field_value(
-+		value,
-+		alpha_mode,
-+		BLND_CONTROL,
-+		BLND_ALPHA_MODE);
- 	set_reg_field_value(
- 		value,
- 		blnd_mode,
- 		BLND_CONTROL,
- 		BLND_MODE);
-+	set_reg_field_value(
-+		value,
-+		multiplied_mode,
-+		BLND_CONTROL,
-+		BLND_MULTIPLIED_MODE);
- 
- 
- 	dm_write_reg(ctx, addr, value);
-@@ -456,6 +467,9 @@ static bool dce110_enable_display_power_gating(
- 	else
- 		cntl = ASIC_PIPE_DISABLE;
- 
-+	if (controller_id == DCE110_UNDERLAY_IDX)
-+		controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
-+
- 	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0)
- 		bp_result = dcb->funcs->enable_disp_power_gating(
- 						dcb, controller_id + 1, cntl);
-@@ -524,10 +538,10 @@ static bool set_gamma_ramp(
- 
- 	opp->funcs->opp_power_on_regamma_lut(opp, true);
- 
--	build_prescale_params(prescale_params, surface);
--
--	if (ipp)
-+	if (ipp) {
-+		build_prescale_params(prescale_params, surface);
- 		ipp->funcs->ipp_program_prescale(ipp, prescale_params);
-+	}
- 
- 	if (ramp) {
- 		calculate_regamma_params(regamma_params,
-@@ -778,8 +792,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
- 		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
--		pipe_ctx->flags.blanked = true;
--
- 
- 		/*
- 		 * only disable stream in case it was ever enabled
-@@ -957,8 +969,6 @@ static void disable_vga_and_power_gate_all_controllers(
- 		 * powergating. */
- 		enable_display_pipe_clock_gating(ctx,
- 				true);
--		if (i == DCE110_UNDERLAY_IDX)
--			continue;
- 		dc->hwss.enable_display_power_gating(ctx, i, dcb,
- 				PIPE_GATING_CONTROL_ENABLE);
- 	}
-@@ -1385,6 +1395,10 @@ static void set_plane_config(
- 			true);
- 
- 	tg->funcs->program_timing(tg, crtc_timing, false);
-+	tg->funcs->enable_advanced_request(
-+			tg,
-+			true,
-+			&pipe_ctx->stream->public.timing);
- 
- 	dc->hwss.enable_fe_clock(ctx, pipe_ctx->pipe_idx, true);
- 
-@@ -1451,8 +1465,7 @@ static void update_plane_addrs(struct dc *dc, struct resource_context *res_ctx)
- 		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false)) {
- 			dm_error("DC: failed to unblank crtc!\n");
- 			BREAK_TO_DEBUGGER();
--		} else
--			pipe_ctx->flags.blanked = false;
-+		}
- 	}
- }
- 
-@@ -1476,12 +1489,9 @@ static void reset_single_pipe_hw_ctx(
- 	}
- 
- 	core_link_disable_stream(pipe_ctx);
--	if (!pipe_ctx->flags.blanked) {
--		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
--			dm_error("DC: failed to blank crtc!\n");
--			BREAK_TO_DEBUGGER();
--		} else
--			pipe_ctx->flags.blanked = true;
-+	if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
-+		dm_error("DC: failed to blank crtc!\n");
-+		BREAK_TO_DEBUGGER();
- 	}
- 	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
- 	pipe_ctx->mi->funcs->free_mem_input(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-index 042bd3a..08620e6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-@@ -183,10 +183,6 @@ static void program_tiling(
- {
- 	uint32_t value = 0;
- 
--	value = dm_read_reg(
--			mem_input110->base.ctx,
--			DCP_REG(mmUNP_GRPH_CONTROL));
--
- 	set_reg_field_value(value, info->num_banks,
- 		UNP_GRPH_CONTROL, GRPH_NUM_BANKS);
- 
-@@ -219,7 +215,29 @@ static void program_tiling(
- 
- 	dm_write_reg(
- 		mem_input110->base.ctx,
--		DCP_REG(mmUNP_GRPH_CONTROL),
-+		mmUNP_GRPH_CONTROL,
-+		value);
-+
-+	value = 0;
-+
-+	set_reg_field_value(value, info->bank_width_c,
-+		UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C);
-+
-+	set_reg_field_value(value, info->bank_height_c,
-+		UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C);
-+
-+	set_reg_field_value(value, info->tile_aspect_c,
-+		UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C);
-+
-+	set_reg_field_value(value, info->tile_split_c,
-+		UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C);
-+
-+	set_reg_field_value(value, info->tile_mode_c,
-+		UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_CONTROL_C,
- 		value);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index ea5b064..4e3276b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -285,11 +285,15 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 
- 	value = dm_read_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
--	set_reg_field_value(value, 3,
-+	set_reg_field_value(value, 0,
- 			CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
- 	dm_write_reg(tg->ctx,
- 			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
-+	/* TODO: may want this on for looking for underflow */
-+	value = 0;
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
-+
- 	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
- 
- 	return result == BP_RESULT_OK;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index 51d77da..99e8809 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -30,22 +30,24 @@
- 
- static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
- {
--    /*
--     * Set MASTER_UPDATE_MODE to 0
--     * This is needed for DRR, and also suggested to be default value by Syed.
--     */
-+/*
-+* Set MASTER_UPDATE_MODE to 0
-+* This is needed for DRR, and also suggested to be default value by Syed.
-+*/
- 
- 	uint32_t value;
- 
--	value = dm_read_reg(tg->ctx,
--			mmCRTCV_MASTER_UPDATE_MODE);
-+	value = 0;
- 	set_reg_field_value(value, 0,
- 			CRTCV_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
- 	dm_write_reg(tg->ctx,
- 			mmCRTCV_MASTER_UPDATE_MODE, value);
- 
--	value = dm_read_reg(tg->ctx,
--			mmCRTCV_MASTER_EN);
-+	/* TODO: may want this on for looking for underflow */
-+	value = 0;
-+	dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value);
-+
-+	value = 0;
- 	set_reg_field_value(value, 1,
- 			CRTCV_MASTER_EN, CRTC_MASTER_EN);
- 	dm_write_reg(tg->ctx,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index ff34292..70b4a85 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -317,7 +317,6 @@ struct pipe_ctx {
- 	uint8_t pipe_idx;
- 
- 	struct flags {
--		bool blanked;
- 		bool unchanged;
- 		bool timing_changed;
- 	} flags;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0839-drm-amd-dal-Address-HW-team-feedback-on-ipp.patch b/common/recipes-kernel/linux/files/0839-drm-amd-dal-Address-HW-team-feedback-on-ipp.patch
deleted file mode 100644
index a08205aa..00000000
--- a/common/recipes-kernel/linux/files/0839-drm-amd-dal-Address-HW-team-feedback-on-ipp.patch
+++ /dev/null
@@ -1,182 +0,0 @@
-From d2ffd84492fe27eb17aa683a57296d7d804bbe64 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 22 Feb 2016 12:18:24 -0500
-Subject: [PATCH 0839/1110] drm/amd/dal: Address HW team feedback on ipp
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  4 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  4 ++--
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           |  4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     |  2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c  |  8 +++-----
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   | 23 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         | 18 -----------------
- 8 files changed, 34 insertions(+), 31 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index f469017..ec02029 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -304,8 +304,8 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc,
- 	position.y = y;
- 
- 	position.hot_spot_enable = true;
--	position.x_origin = xorigin;
--	position.y_origin = yorigin;
-+	position.x_hotspot = xorigin;
-+	position.y_hotspot = yorigin;
- 
- 	if (!dc_target_set_cursor_position(
- 				amdgpu_crtc->target,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index ac917e5..87275b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -500,8 +500,8 @@ bool dc_target_set_cursor_position(
- 			 * plane so we only need to set it on first pipe we
- 			 * find. May need to make this code dce specific later.
- 			 */
--			if (ipp->funcs->ipp_cursor_set_position(ipp, position))
--				return true;
-+			ipp->funcs->ipp_cursor_set_position(ipp, position);
-+			return true;
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index ea8028c..273c544 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -256,8 +256,8 @@ struct dc_cursor_position {
- 	uint32_t x;
- 	uint32_t y;
- 
--	uint32_t x_origin;
--	uint32_t y_origin;
-+	uint32_t x_hotspot;
-+	uint32_t y_hotspot;
- 
- 	/*
- 	 * This parameter indicates whether HW cursor should be enabled
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index dde138c..13b9100 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -53,7 +53,7 @@ bool dce110_ipp_construct(
- void dce110_ipp_destroy(struct input_pixel_processor **ipp);
- 
- /* CURSOR RELATED */
--bool dce110_ipp_cursor_set_position(
-+void dce110_ipp_cursor_set_position(
- 	struct input_pixel_processor *ipp,
- 	const struct dc_cursor_position *position);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-index ef91f2d..eaa1f05 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-@@ -71,7 +71,7 @@ static void program_address(
- 	PHYSICAL_ADDRESS_LOC address);
- 
- 
--bool dce110_ipp_cursor_set_position(
-+void dce110_ipp_cursor_set_position(
- 	struct input_pixel_processor *ipp,
- 	const struct dc_cursor_position *position)
- {
-@@ -89,13 +89,11 @@ bool dce110_ipp_cursor_set_position(
- 	if (position->hot_spot_enable)
- 		program_hotspot(
- 				ipp110,
--				position->x_origin,
--				position->y_origin);
-+				position->x_hotspot,
-+				position->y_hotspot);
- 
- 	/* unlock cursor registers */
- 	lock(ipp110, false);
--
--	return true;
- }
- 
- bool dce110_ipp_cursor_set_attributes(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index a0db7aa..81b78fd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -36,6 +36,29 @@ struct dce110_mem_input_reg_offsets {
- 	uint32_t pipe;
- };
- 
-+
-+enum stutter_mode_type {
-+/*	TODO: Clean up these enums, right now only one is being used
-+ *	STUTTER_MODE_LEGACY = 0X00000001,
-+ *	STUTTER_MODE_ENHANCED = 0X00000002,
-+ *	STUTTER_MODE_FID_NBP_STATE = 0X00000004,
-+ *	STUTTER_MODE_WATERMARK_NBP_STATE = 0X00000008,
-+ *	STUTTER_MODE_SINGLE_DISPLAY_MODEL = 0X00000010,
-+ *	STUTTER_MODE_MIXED_DISPLAY_MODEL = 0X00000020,
-+ *	STUTTER_MODE_DUAL_DMIF_BUFFER = 0X00000040,
-+ */
-+	STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION = 0X00000080,
-+/*
-+ *	STUTTER_MODE_NO_ADVANCED_REQUEST = 0X00000100,
-+ *	STUTTER_MODE_NO_LB_RESET = 0X00000200,
-+ *	STUTTER_MODE_DISABLED = 0X00000400,
-+ *	STUTTER_MODE_AGGRESSIVE_MARKS = 0X00000800,
-+ *	STUTTER_MODE_URGENCY = 0X00001000,
-+ *	STUTTER_MODE_QUAD_DMIF_BUFFER = 0X00002000,
-+ *	STUTTER_MODE_NOT_USED = 0X00008000
-+ */
-+};
-+
- struct dce110_mem_input {
- 	struct mem_input base;
- 	struct dce110_mem_input_reg_offsets offsets;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-index 9081820..505bf72 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-@@ -88,7 +88,7 @@ enum ipp_output_format {
- struct ipp_funcs {
- 
- 	/*** cursor ***/
--	bool (*ipp_cursor_set_position)(
-+	void (*ipp_cursor_set_position)(
- 		struct input_pixel_processor *ipp,
- 		const struct dc_cursor_position *position);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-index 9cd9905..8339d61 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-@@ -66,22 +66,4 @@ struct mem_input_funcs {
- 		enum dc_rotation_angle rotation);
- };
- 
--enum stutter_mode_type {
--	STUTTER_MODE_LEGACY = 0X00000001,
--	STUTTER_MODE_ENHANCED = 0X00000002,
--	STUTTER_MODE_FID_NBP_STATE = 0X00000004,
--	STUTTER_MODE_WATERMARK_NBP_STATE = 0X00000008,
--	STUTTER_MODE_SINGLE_DISPLAY_MODEL = 0X00000010,
--	STUTTER_MODE_MIXED_DISPLAY_MODEL = 0X00000020,
--	STUTTER_MODE_DUAL_DMIF_BUFFER = 0X00000040,
--	STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION = 0X00000080,
--	STUTTER_MODE_NO_ADVANCED_REQUEST = 0X00000100,
--	STUTTER_MODE_NO_LB_RESET = 0X00000200,
--	STUTTER_MODE_DISABLED = 0X00000400,
--	STUTTER_MODE_AGGRESSIVE_MARKS = 0X00000800,
--	STUTTER_MODE_URGENCY = 0X00001000,
--	STUTTER_MODE_QUAD_DMIF_BUFFER = 0X00002000,
--	STUTTER_MODE_NOT_USED = 0X00008000
--};
--
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0840-drm-amd-dal-fix-ref-count-issue-on-validate-failure.patch b/common/recipes-kernel/linux/files/0840-drm-amd-dal-fix-ref-count-issue-on-validate-failure.patch
deleted file mode 100644
index ec3daa3f..00000000
--- a/common/recipes-kernel/linux/files/0840-drm-amd-dal-fix-ref-count-issue-on-validate-failure.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From 28a91920b2f50c7858c12601e3aff36886b34415 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 23 Feb 2016 14:27:59 -0500
-Subject: [PATCH 0840/1110] drm/amd/dal: fix ref count issue on validate
- failure
-
-When copying context, retain surfaces and targets and
-release when context is freed. This fixes crash on
-underscan test on CZ, which was caused by dangling pointer
-in the bandwidth validation failure code path.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 24 +++++----------
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 34 ++++++++++++++++++++--
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  9 ++++--
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  1 +
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  1 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  1 +
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  6 +++-
- 7 files changed, 53 insertions(+), 23 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 9ecd60c..7eaf7ef 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -391,7 +391,7 @@ ctx_fail:
- 
- static void destruct(struct dc *dc)
- {
--	destruct_val_ctx(&dc->current_context);
-+	val_ctx_destruct(&dc->current_context);
- 	destroy_links(dc);
- 	dc->res_pool.funcs->destruct(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
-@@ -452,7 +452,7 @@ bool dc_validate_resources(
- 	result = dc->res_pool.funcs->validate_with_context(
- 						dc, set, set_count, context);
- 
--	destruct_val_ctx(context);
-+	val_ctx_destruct(context);
- 	dm_free(dc->ctx, context);
- context_alloc_fail:
- 
-@@ -563,6 +563,7 @@ bool dc_commit_targets(
- 	result = dc->res_pool.funcs->validate_with_context(dc, set, target_count, context);
- 	if (result != DC_OK){
- 		BREAK_TO_DEBUGGER();
-+		val_ctx_destruct(context);
- 		goto fail;
- 	}
- 
-@@ -592,25 +593,14 @@ bool dc_commit_targets(
- 			dc_target_enable_memory_requests(dc_target);
- 	}
- 
--	/* Release old targets */
--	for (i = 0; i < dc->current_context.target_count; i++) {
--		dc_target_release(
--				&dc->current_context.targets[i]->public);
--		dc->current_context.targets[i] = NULL;
--	}
--	/* Retain new targets*/
--	for (i = 0; i < context->target_count; i++) {
--		dc_target_retain(&context->targets[i]->public);
--	}
--
--	destruct_val_ctx(&dc->current_context);
--
--	dc->current_context = *context;
--
- 	program_timing_sync(dc->ctx, context);
- 
- 	pplib_apply_display_requirements(dc, context, &context->pp_display_cfg);
- 
-+	val_ctx_destruct(&dc->current_context);
-+
-+	dc->current_context = *context;
-+
- fail:
- 	dm_free(dc->ctx, context);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 42c456a..1bb4adb 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -407,11 +407,17 @@ bool attach_surfaces_to_context(
- 	}
- 
- 
-+	/* retain new surfaces */
- 	for (i = 0; i < surface_count; i++)
- 		dc_surface_retain(surfaces[i]);
--	/* Release after retain to account for surfaces remaining the same */
--	for (i = 0; i < target_status->surface_count; i++)
-+
-+	/* release existing surfaces*/
-+	for (i = 0; i < target_status->surface_count; i++) {
- 		dc_surface_release(target_status->surfaces[i]);
-+		target_status->surfaces[i] = NULL;
-+	}
-+
-+	/* assign new surfaces*/
- 	for (i = 0; i < surface_count; i++)
- 		target_status->surfaces[i] = surfaces[i];
- 
-@@ -1241,7 +1247,7 @@ static void set_vendor_info_packet(struct core_stream *stream,
- 	info_packet->valid = true;
- }
- 
--void destruct_val_ctx(struct validate_context *context)
-+void val_ctx_destruct(struct validate_context *context)
- {
- 	int i, j;
- 
-@@ -1249,7 +1255,29 @@ void destruct_val_ctx(struct validate_context *context)
- 		for (j = 0; j < context->target_status[i].surface_count; j++)
- 			dc_surface_release(
- 				context->target_status[i].surfaces[j]);
-+
- 		context->target_status[i].surface_count = 0;
-+		dc_target_release(&context->targets[i]->public);
-+	}
-+}
-+
-+/*
-+ * Copy src_ctx into dst_ctx and retain all surfaces and targets referenced
-+ * by the src_ctx
-+ */
-+void val_ctx_copy_construct(
-+		const struct validate_context *src_ctx,
-+		struct validate_context *dst_ctx)
-+{
-+	int i, j;
-+
-+	*dst_ctx = *src_ctx;
-+
-+	for (i = 0; i < dst_ctx->target_count; i++) {
-+		dc_target_retain(&dst_ctx->targets[i]->public);
-+		for (j = 0; j < dst_ctx->target_status[i].surface_count; j++)
-+			dc_surface_retain(
-+				dst_ctx->target_status[i].surfaces[j]);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 87275b8..6a66ae9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -219,13 +219,16 @@ bool dc_commit_surfaces_to_target(
- 	bool is_mpo_turning_on = false;
- 
- 	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
--	*context = dc->current_context;
-+
-+	val_ctx_copy_construct(&dc->current_context, context);
- 
- 	/* Cannot commit surface to a target that is not commited */
- 	for (i = 0; i < context->target_count; i++)
- 		if (target == context->targets[i])
- 			break;
-+
- 	target_status = &context->target_status[i];
-+
- 	if (!dal_adapter_service_is_in_accelerated_mode(
- 						dc->res_pool.adapter_srv)
- 		|| i == context->target_count) {
-@@ -343,13 +346,15 @@ bool dc_commit_surfaces_to_target(
- 						&context->pp_display_cfg);
- 	}
- 
-+	val_ctx_destruct(&dc->current_context);
- 	dc->current_context = *context;
- 	dm_free(dc->ctx, context);
- 	return true;
- 
- unexpected_fail:
- 
--	destruct_val_ctx(context);
-+	val_ctx_destruct(context);
-+
- 	dm_free(dc->ctx, context);
- 	return false;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index c7145c5..a8c8f99 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -890,6 +890,7 @@ enum dc_status dce100_validate_with_context(
- 		bool unchanged = false;
- 
- 		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		dc_target_retain(&context->targets[i]->public);
- 		context->target_count++;
- 
- 		for (j = 0; j < dc->current_context.target_count; j++)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 26e9df5..c079bb7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1002,6 +1002,7 @@ enum dc_status dce110_validate_with_context(
- 		bool unchanged = false;
- 
- 		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		dc_target_retain(&context->targets[i]->public);
- 		context->target_count++;
- 
- 		for (j = 0; j < dc->current_context.target_count; j++)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index c645d25..cf51a44 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -999,6 +999,7 @@ enum dc_status dce80_validate_with_context(
- 		bool unchanged = false;
- 
- 		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		dc_target_retain(&context->targets[i]->public);
- 		context->target_count++;
- 
- 		for (j = 0; j < dc->current_context.target_count; j++)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index c2d6011..983d484 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -80,6 +80,10 @@ enum dc_status map_resources(
- 	const struct dc *dc,
- 	struct validate_context *context);
- 
--void destruct_val_ctx(struct validate_context *context);
-+void val_ctx_destruct(struct validate_context *context);
-+
-+void val_ctx_copy_construct(
-+	const struct validate_context *src_ctx,
-+	struct validate_context *dst_ctx);
- 
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0841-drm-amd-dal-fix-lb-alpha-programming.patch b/common/recipes-kernel/linux/files/0841-drm-amd-dal-fix-lb-alpha-programming.patch
deleted file mode 100644
index 3c97033c..00000000
--- a/common/recipes-kernel/linux/files/0841-drm-amd-dal-fix-lb-alpha-programming.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 9b9b78e7a2229cf1d2ec1773e757230afa2c202d Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 25 Feb 2016 14:07:49 -0500
-Subject: [PATCH 0841/1110] drm/amd/dal: fix lb alpha programming
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c | 18 ++++++------------
- 1 file changed, 6 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index 70dedbc..1fe8b1b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -772,9 +772,7 @@ bool dce110_transform_set_pixel_storage_depth(
- 	uint32_t value;
- 	enum dc_color_depth color_depth;
- 
--	value = dm_read_reg(
--			xfm->ctx,
--			LB_REG(mmLB_DATA_FORMAT));
-+	value = dm_read_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT));
- 	switch (depth) {
- 	case LB_PIXEL_DEPTH_18BPP:
- 		color_depth = COLOR_DEPTH_666;
-@@ -806,9 +804,8 @@ bool dce110_transform_set_pixel_storage_depth(
- 		ret = program_bit_depth_reduction(xfm110, color_depth,
- 				bit_depth_params);
- 
--		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
--		dm_write_reg(
--				xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
-+		set_reg_field_value(value, 1, LB_DATA_FORMAT, ALPHA_EN);
-+		dm_write_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
- 		if (!(xfm110->lb_pixel_depth_supported & depth)) {
- 			/*we should use unsupported capabilities
- 			 *  unless it is required by w/a*/
-@@ -901,9 +898,7 @@ bool dce110_transform_v_set_pixel_storage_depth(
- 	uint32_t value;
- 	enum dc_color_depth color_depth;
- 
--	value = dm_read_reg(
--			xfm->ctx,
--			LB_REG(mmLBV_DATA_FORMAT));
-+	value = dm_read_reg(xfm->ctx, mmLBV_DATA_FORMAT);
- 	switch (depth) {
- 	case LB_PIXEL_DEPTH_18BPP:
- 		color_depth = COLOR_DEPTH_666;
-@@ -947,9 +942,8 @@ bool dce110_transform_v_set_pixel_storage_depth(
- 		ret = program_bit_depth_reduction(xfm110, color_depth,
- 				bit_depth_params);
- 
--		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
--		dm_write_reg(
--				xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
-+		set_reg_field_value(value, 0, LBV_DATA_FORMAT, ALPHA_EN);
-+		dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, value);
- 		if (!(xfm110->lb_pixel_depth_supported & depth)) {
- 			/*we should use unsupported capabilities
- 			 *  unless it is required by w/a*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0842-drm-amd-dal-fix-memory-leaks-in-I2C-code.patch b/common/recipes-kernel/linux/files/0842-drm-amd-dal-fix-memory-leaks-in-I2C-code.patch
deleted file mode 100644
index bd3a533e..00000000
--- a/common/recipes-kernel/linux/files/0842-drm-amd-dal-fix-memory-leaks-in-I2C-code.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From eed795bce45f220f363abebbf87fac8a52877e16 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 26 Feb 2016 04:04:07 -0500
-Subject: [PATCH 0842/1110] drm/amd/dal: fix memory leaks in I2C code
-
-Two memory leaks were fixed
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 10 +++++++++-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c   | 13 ++++++++++---
- 2 files changed, 19 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index e414861..17240e0 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -515,6 +515,7 @@ bool dm_helpers_submit_i2c(
- 	struct i2c_msg *msgs;
- 	int i = 0;
- 	int num = cmd->number_of_payloads;
-+	bool result;
- 
- 	if (!aconnector) {
- 		DRM_ERROR("Failed to found connector for link!");
-@@ -523,6 +524,9 @@ bool dm_helpers_submit_i2c(
- 
- 	msgs = kzalloc(num * sizeof(struct i2c_msg), GFP_KERNEL);
- 
-+	if (!msgs)
-+		return false;
-+
- 	for (i = 0; i < num; i++) {
- 		msgs[i].flags = cmd->payloads[i].write ? I2C_M_RD : 0;
- 		msgs[i].addr = cmd->payloads[i].address;
-@@ -530,6 +534,10 @@ bool dm_helpers_submit_i2c(
- 		msgs[i].buf = cmd->payloads[i].data;
- 	}
- 
--	return i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
-+	result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
-+
-+	kfree(msgs);
-+
-+	return result;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index ec02029..f0eaafd 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1814,8 +1814,13 @@ int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
- 	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
- 	struct i2c_command cmd;
- 	int i;
-+	int result = -EIO;
- 
- 	cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL);
-+
-+	if (!cmd.payloads)
-+		return result;
-+
- 	cmd.number_of_payloads = num;
- 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
- 	cmd.speed = 100;
-@@ -1828,9 +1833,11 @@ int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
- 	}
- 
- 	if (dc_submit_i2c(i2c->dm->dc, i2c->link_index, &cmd))
--		return num;
--	else
--		return -EIO;
-+		result = num;
-+
-+	kfree(cmd.payloads);
-+
-+	return result;
- }
- 
- u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0843-drm-amd-dal-temporary-fix-for-black-screen-on-tonga.patch b/common/recipes-kernel/linux/files/0843-drm-amd-dal-temporary-fix-for-black-screen-on-tonga.patch
deleted file mode 100644
index 422a4d06..00000000
--- a/common/recipes-kernel/linux/files/0843-drm-amd-dal-temporary-fix-for-black-screen-on-tonga.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 1a45e01e0e97adba1946408d2290d2ed813b37bf Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 25 Feb 2016 19:07:37 -0500
-Subject: [PATCH 0843/1110] drm/amd/dal: temporary fix for black screen on
- tonga
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index 1fe8b1b..470453f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -804,7 +804,7 @@ bool dce110_transform_set_pixel_storage_depth(
- 		ret = program_bit_depth_reduction(xfm110, color_depth,
- 				bit_depth_params);
- 
--		set_reg_field_value(value, 1, LB_DATA_FORMAT, ALPHA_EN);
-+		set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
- 		dm_write_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
- 		if (!(xfm110->lb_pixel_depth_supported & depth)) {
- 			/*we should use unsupported capabilities
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0844-drm-amd-dal-add-input-csc-for-underlay.patch b/common/recipes-kernel/linux/files/0844-drm-amd-dal-add-input-csc-for-underlay.patch
deleted file mode 100644
index e52cac38..00000000
--- a/common/recipes-kernel/linux/files/0844-drm-amd-dal-add-input-csc-for-underlay.patch
+++ /dev/null
@@ -1,1309 +0,0 @@
-From 7faf187d881d9a761182cfb04ab4c8aba84b1bf7 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 25 Feb 2016 16:09:50 -0500
-Subject: [PATCH 0844/1110] drm/amd/dal: add input csc for underlay
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           |  11 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  56 ++----
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |   5 +
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c |  48 ++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c   | 212 ++++++++++++++++++---
- .../drm/amd/dal/dc/dce110/dce110_opp_formatter.c   |   4 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |  48 +----
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   6 +-
- .../amd/dal/dc/dce110/dce110_timing_generator_v.c  |  34 +---
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.c   |   3 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |   1 +
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.c |   7 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h       |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c   |  48 ++---
- .../gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c |   4 +-
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               |   7 +-
- drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h  |   4 +-
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         |   2 +
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  |   5 -
- 23 files changed, 302 insertions(+), 213 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index f0eaafd..9fb4e51 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -484,7 +484,7 @@ static void fill_plane_attributes_from_fb(
- 	surface->scaling_quality.v_taps_c = 2;
- 
- 	/* TODO: unhardcode */
--	surface->color_space = COLOR_SPACE_SRGB_FULL_RANGE;
-+	surface->color_space = COLOR_SPACE_SRGB;
- 	surface->scaling_quality.h_taps = 2;
- 	surface->scaling_quality.v_taps = 2;
- 	surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 6a66ae9..e892a2f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -194,7 +194,7 @@ static int8_t acquire_first_free_underlay(
- 
- 		pipe_ctx->tg->funcs->set_blank_color(
- 				pipe_ctx->tg,
--				COLOR_SPACE_SRGB_FULL_RANGE);/* TODO unhardcode*/
-+				COLOR_SPACE_YCBCR601);/* TODO unhardcode*/
- 
- 		pipe_ctx->stream = stream;
- 		return DCE110_UNDERLAY_IDX;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 40e5883..fb0b9f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -108,7 +108,7 @@ struct dc_surface {
- 
- 	union plane_size plane_size;
- 	struct dc_tiling_info tiling_info;
--	enum color_space color_space;
-+	enum dc_color_space color_space;
- 
- 	enum surface_pixel_format format;
- 	enum dc_rotation_angle rotation;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index 273c544..82e3afb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -354,17 +354,16 @@ enum dc_pixel_encoding {
- 	PIXEL_ENCODING_COUNT
- };
- 
--enum color_space {
-+enum dc_color_space {
- 	COLOR_SPACE_UNKNOWN,
--	COLOR_SPACE_SRGB_FULL_RANGE,
--	COLOR_SPACE_SRGB_LIMITED_RANGE,
-+	COLOR_SPACE_SRGB,
-+	COLOR_SPACE_SRGB_LIMITED,
- 	COLOR_SPACE_YPBPR601,
- 	COLOR_SPACE_YPBPR709,
- 	COLOR_SPACE_YCBCR601,
- 	COLOR_SPACE_YCBCR709,
--	COLOR_SPACE_YCBCR601_YONLY,
--	COLOR_SPACE_YCBCR709_YONLY,
--	COLOR_SPACE_N_MVPU_SUPER_AA,
-+	COLOR_SPACE_YCBCR601_LIMITED,
-+	COLOR_SPACE_YCBCR709_LIMITED
- };
- 
- enum dc_color_depth {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 1e22e59..a93cdbb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -737,10 +737,10 @@ static void unblank_stream(struct pipe_ctx *pipe_ctx,
- 	pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, &params);
- }
- 
--static enum color_space get_output_color_space(
-+static enum dc_color_space get_output_color_space(
- 				const struct dc_crtc_timing *dc_crtc_timing)
- {
--	enum color_space color_space = COLOR_SPACE_SRGB_FULL_RANGE;
-+	enum dc_color_space color_space = COLOR_SPACE_SRGB;
- 
- 	switch (dc_crtc_timing->pixel_encoding)	{
- 	case PIXEL_ENCODING_YCBCR422:
-@@ -754,13 +754,13 @@ static enum color_space get_output_color_space(
- 			if (dc_crtc_timing->pix_clk_khz > 27030) {
- 				if (dc_crtc_timing->flags.Y_ONLY)
- 					color_space =
--						COLOR_SPACE_YCBCR709_YONLY;
-+						COLOR_SPACE_YCBCR709_LIMITED;
- 				else
- 					color_space = COLOR_SPACE_YCBCR709;
- 			} else {
- 				if (dc_crtc_timing->flags.Y_ONLY)
- 					color_space =
--						COLOR_SPACE_YCBCR601_YONLY;
-+						COLOR_SPACE_YCBCR601_LIMITED;
- 				else
- 					color_space = COLOR_SPACE_YCBCR601;
- 			}
-@@ -785,7 +785,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		&dc->current_context.res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
- 	bool timing_changed = context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]
- 							.flags.timing_changed;
--	enum color_space color_space;
-+	enum dc_color_space color_space;
- 
- 	if (timing_changed) {
- 		/* Must blank CRTC after disabling power gating and before any
-@@ -1298,39 +1298,13 @@ static enum dc_status apply_ctx_to_hw(
- /*******************************************************************************
-  * Front End programming
-  ******************************************************************************/
--
--static bool setup_line_buffer_pixel_depth(
--	const struct pipe_ctx *pipe_ctx,
--	enum lb_pixel_depth depth,
--	bool blank)
--{
--	enum lb_pixel_depth current_depth;
--
--	struct timing_generator *tg = pipe_ctx->tg;
--	struct transform *xfm = pipe_ctx->xfm;
--
--	if (!xfm->funcs->transform_get_current_pixel_storage_depth(
--		xfm,
--		&current_depth))
--		return false;
--
--	if (current_depth != depth) {
--		if (blank)
--			tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
--
--		return xfm->funcs->transform_set_pixel_storage_depth(xfm, depth,
--				&pipe_ctx->stream->bit_depth_params);
--	}
--
--	return false;
--}
--
- static void set_default_colors(struct pipe_ctx *pipe_ctx)
- {
- 	struct default_adjustment default_adjust = { 0 };
- 
- 	default_adjust.force_hw_default = false;
--	default_adjust.color_space = get_output_color_space(
-+	default_adjust.in_color_space = pipe_ctx->surface->public.color_space;
-+	default_adjust.out_color_space = get_output_color_space(
- 					&pipe_ctx->stream->public.timing);
- 	default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
- 	default_adjust.surface_pixel_format = pipe_ctx->scl_data.format;
-@@ -1340,7 +1314,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
- 		pipe_ctx->stream->public.timing.display_color_depth;
- 
- 	/* Lb color depth */
--	default_adjust.lb_color_depth = LB_PIXEL_DEPTH_24BPP;
-+	default_adjust.lb_color_depth = LB_PIXEL_DEPTH_30BPP;
- 	/*dal_hw_sequencer_translate_to_lb_color_depth(
- 			build_params->
- 			line_buffer_params[path_id][plane_id].depth);*/
-@@ -1351,13 +1325,14 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
- 
- static void program_scaler(const struct pipe_ctx *pipe_ctx)
- {
--	setup_line_buffer_pixel_depth(
--		pipe_ctx,
--		LB_PIXEL_DEPTH_24BPP,
--		false);
-+	pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth(
-+		pipe_ctx->xfm,
-+		LB_PIXEL_DEPTH_30BPP,
-+		&pipe_ctx->stream->bit_depth_params);
- 
- 	pipe_ctx->tg->funcs->set_overscan_blank_color(
--		pipe_ctx->tg, pipe_ctx->surface->public.color_space);
-+		pipe_ctx->tg,
-+		get_output_color_space(&pipe_ctx->stream->public.timing));
- 
- 	pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm, &pipe_ctx->scl_data);
- }
-@@ -1418,6 +1393,9 @@ static void set_plane_config(
- 	dc->hwss.set_blender_mode(
- 		ctx, pipe_ctx->pipe_idx, blender_mode);
- 
-+	if (blender_mode != BLENDER_MODE_CURRENT_PIPE)
-+		pipe_ctx->xfm->funcs->transform_set_alpha(pipe_ctx->xfm, true);
-+
- 	mi->funcs->mem_input_program_surface_config(
- 			mi,
- 			surface->public.format,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index f640552..d9dab36 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -142,11 +142,16 @@ static void program_addr(
- {
- 	switch (addr->type) {
- 	case PLN_ADDR_TYPE_GRAPHICS:
-+		if (addr->grph.addr.quad_part == 0)
-+			break;
- 		program_pri_addr(
- 			mem_input110,
- 			addr->grph.addr);
- 		break;
- 	case PLN_ADDR_TYPE_GRPH_STEREO:
-+		if (addr->grph_stereo.left_addr.quad_part == 0
-+			|| addr->grph_stereo.right_addr.quad_part == 0)
-+			break;
- 		program_pri_addr(
- 			mem_input110,
- 			addr->grph_stereo.left_addr);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index cad4efa..45778e6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -133,7 +133,7 @@ void dce110_opp_program_clamping_and_pixel_encoding(
- 
- void dce110_opp_set_dyn_expansion(
- 	struct output_pixel_processor *opp,
--	enum color_space color_sp,
-+	enum dc_color_space color_sp,
- 	enum dc_color_depth color_dpth,
- 	enum signal_type signal);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-index b1db0cc..08df2ba 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -39,24 +39,24 @@ enum {
- };
- 
- struct out_csc_color_matrix {
--	enum color_space color_space;
-+	enum dc_color_space color_space;
- 	uint16_t regval[OUTPUT_CSC_MATRIX_SIZE];
- };
- 
- static const struct out_csc_color_matrix global_color_matrix[] = {
--{ COLOR_SPACE_SRGB_FULL_RANGE,
-+{ COLOR_SPACE_SRGB,
- 	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
--{ COLOR_SPACE_SRGB_LIMITED_RANGE,
-+{ COLOR_SPACE_SRGB_LIMITED,
- 	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
- { COLOR_SPACE_YCBCR601,
- 	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
- 		0xF6B9, 0xE00, 0x1000} },
- { COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
- 	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
--/*  YOnly same as YCbCr709 but Y in Full range -To do. */
--{ COLOR_SPACE_YCBCR601_YONLY, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+/* TODO: correct values below */
-+{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
- 	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
--{ COLOR_SPACE_YCBCR709_YONLY, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
- 	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
- };
- 
-@@ -674,7 +674,7 @@ static void set_yuv_adjustment(
- {
- 	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
- 		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
--		(adjust->c_space == COLOR_SPACE_YCBCR601_YONLY);
-+		(adjust->c_space == COLOR_SPACE_YCBCR601_LIMITED);
- 	struct out_csc_color_matrix reg_matrix;
- 	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
- 	struct dc_csc_adjustments adjustments;
-@@ -684,8 +684,8 @@ static void set_yuv_adjustment(
- 
- 	setup_adjustments(adjust, &adjustments);
- 
--	if ((adjust->c_space == COLOR_SPACE_YCBCR601_YONLY) ||
--		(adjust->c_space == COLOR_SPACE_YCBCR709_YONLY))
-+	if ((adjust->c_space == COLOR_SPACE_YCBCR601_LIMITED) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR709_LIMITED))
- 		calculate_adjustments_y_only(
- 			ideals, &adjustments, matrix);
- 	else
-@@ -703,7 +703,7 @@ static bool configure_graphics_mode(
- 	struct dce110_opp *opp110,
- 	enum csc_color_mode config,
- 	enum graphics_csc_adjust_type csc_adjust_type,
--	enum color_space color_space)
-+	enum dc_color_space color_space)
- {
- 	struct dc_context *ctx = opp110->base.ctx;
- 	uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
-@@ -725,7 +725,7 @@ static bool configure_graphics_mode(
- 		} else {
- 
- 			switch (color_space) {
--			case COLOR_SPACE_SRGB_FULL_RANGE:
-+			case COLOR_SPACE_SRGB:
- 				/* by pass */
- 				set_reg_field_value(
- 					value,
-@@ -733,7 +733,7 @@ static bool configure_graphics_mode(
- 					OUTPUT_CSC_CONTROL,
- 					OUTPUT_CSC_GRPH_MODE);
- 				break;
--			case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+			case COLOR_SPACE_SRGB_LIMITED:
- 				/* TV RGB */
- 				set_reg_field_value(
- 					value,
-@@ -743,7 +743,7 @@ static bool configure_graphics_mode(
- 				break;
- 			case COLOR_SPACE_YCBCR601:
- 			case COLOR_SPACE_YPBPR601:
--			case COLOR_SPACE_YCBCR601_YONLY:
-+			case COLOR_SPACE_YCBCR601_LIMITED:
- 				/* YCbCr601 */
- 				set_reg_field_value(
- 					value,
-@@ -753,7 +753,7 @@ static bool configure_graphics_mode(
- 				break;
- 			case COLOR_SPACE_YCBCR709:
- 			case COLOR_SPACE_YPBPR709:
--			case COLOR_SPACE_YCBCR709_YONLY:
-+			case COLOR_SPACE_YCBCR709_LIMITED:
- 				/* YCbCr709 */
- 				set_reg_field_value(
- 					value,
-@@ -767,7 +767,7 @@ static bool configure_graphics_mode(
- 		}
- 	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
- 		switch (color_space) {
--		case COLOR_SPACE_SRGB_FULL_RANGE:
-+		case COLOR_SPACE_SRGB:
- 			/* by pass */
- 			set_reg_field_value(
- 				value,
-@@ -775,7 +775,7 @@ static bool configure_graphics_mode(
- 				OUTPUT_CSC_CONTROL,
- 				OUTPUT_CSC_GRPH_MODE);
- 			break;
--		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		case COLOR_SPACE_SRGB_LIMITED:
- 			/* TV RGB */
- 			set_reg_field_value(
- 				value,
-@@ -785,7 +785,7 @@ static bool configure_graphics_mode(
- 			break;
- 		case COLOR_SPACE_YCBCR601:
- 		case COLOR_SPACE_YPBPR601:
--		case COLOR_SPACE_YCBCR601_YONLY:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
- 			/* YCbCr601 */
- 			set_reg_field_value(
- 				value,
-@@ -795,7 +795,7 @@ static bool configure_graphics_mode(
- 			break;
- 		case COLOR_SPACE_YCBCR709:
- 		case COLOR_SPACE_YPBPR709:
--		case COLOR_SPACE_YCBCR709_YONLY:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
- 			 /* YCbCr709 */
- 			set_reg_field_value(
- 				value,
-@@ -834,17 +834,17 @@ void dce110_opp_set_csc_adjustment(
- 	 * the ideal values only, but keep original design to allow quick switch
- 	 * to the old legacy routines */
- 	switch (adjust->c_space) {
--	case COLOR_SPACE_SRGB_FULL_RANGE:
-+	case COLOR_SPACE_SRGB:
- 		set_rgb_adjustment_legacy(opp110, adjust);
- 		break;
--	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+	case COLOR_SPACE_SRGB_LIMITED:
- 		set_rgb_limited_range_adjustment(
- 			opp110, adjust);
- 		break;
- 	case COLOR_SPACE_YCBCR601:
- 	case COLOR_SPACE_YCBCR709:
--	case COLOR_SPACE_YCBCR601_YONLY:
--	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
- 	case COLOR_SPACE_YPBPR601:
- 	case COLOR_SPACE_YPBPR709:
- 		set_yuv_adjustment(opp110, adjust);
-@@ -883,7 +883,7 @@ void dce110_opp_set_csc_default(
- 
- 		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
- 			elm = &global_color_matrix[i];
--			if (elm->color_space != default_adjust->color_space)
-+			if (elm->color_space != default_adjust->out_color_space)
- 				continue;
- 			/* program the matrix with default values from this
- 			 * file */
-@@ -900,5 +900,5 @@ void dce110_opp_set_csc_default(
- 
- 	configure_graphics_mode(opp110, config,
- 		default_adjust->csc_adjust_type,
--		default_adjust->color_space);
-+		default_adjust->out_color_space);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-index a786b98..2e50e5a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-@@ -76,24 +76,24 @@ enum {
- #define  UNDERLAY_BRIGHTNESS_DIVIDER  100
- 
- struct out_csc_color_matrix {
--	enum color_space color_space;
-+	enum dc_color_space color_space;
- 	uint16_t regval[OUTPUT_CSC_MATRIX_SIZE];
- };
- 
- static const struct out_csc_color_matrix global_color_matrix[] = {
--{ COLOR_SPACE_SRGB_FULL_RANGE,
-+{ COLOR_SPACE_SRGB,
- 	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
--{ COLOR_SPACE_SRGB_LIMITED_RANGE,
-+{ COLOR_SPACE_SRGB_LIMITED,
- 	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
- { COLOR_SPACE_YCBCR601,
- 	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
- 		0xF6B9, 0xE00, 0x1000} },
- { COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
- 	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
--/*  YOnly same as YCbCr709 but Y in Full range -To do. */
--{ COLOR_SPACE_YCBCR601_YONLY, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+/* TODO: correct values below */
-+{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
- 	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
--{ COLOR_SPACE_YCBCR709_YONLY, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
- 	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
- };
- 
-@@ -786,7 +786,7 @@ static void set_yuv_adjustment(
- {
- 	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
- 		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
--		(adjust->c_space == COLOR_SPACE_YCBCR601_YONLY);
-+		(adjust->c_space == COLOR_SPACE_YCBCR601_LIMITED);
- 	struct out_csc_color_matrix reg_matrix;
- 	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
- 	struct dc_csc_adjustments adjustments;
-@@ -796,8 +796,8 @@ static void set_yuv_adjustment(
- 
- 	setup_adjustments(adjust, &adjustments);
- 
--	if ((adjust->c_space == COLOR_SPACE_YCBCR601_YONLY) ||
--		(adjust->c_space == COLOR_SPACE_YCBCR709_YONLY))
-+	if ((adjust->c_space == COLOR_SPACE_YCBCR601_LIMITED) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR709_LIMITED))
- 		calculate_adjustments_y_only(
- 			ideals, &adjustments, matrix);
- 	else
-@@ -815,7 +815,7 @@ static bool configure_graphics_mode_v(
- 	struct dce110_opp *opp110,
- 	enum csc_color_mode config,
- 	enum graphics_csc_adjust_type csc_adjust_type,
--	enum color_space color_space)
-+	enum dc_color_space color_space)
- {
- 	struct dc_context *ctx = opp110->base.ctx;
- 	uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
-@@ -832,7 +832,7 @@ static bool configure_graphics_mode_v(
- 			return true;
- 
- 		switch (color_space) {
--		case COLOR_SPACE_SRGB_FULL_RANGE:
-+		case COLOR_SPACE_SRGB:
- 			/* by pass */
- 			set_reg_field_value(
- 				value,
-@@ -840,13 +840,13 @@ static bool configure_graphics_mode_v(
- 				COL_MAN_OUTPUT_CSC_CONTROL,
- 				OUTPUT_CSC_MODE);
- 			break;
--		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		case COLOR_SPACE_SRGB_LIMITED:
- 			/* not supported for underlay on CZ */
- 			return false;
- 
- 		case COLOR_SPACE_YCBCR601:
- 		case COLOR_SPACE_YPBPR601:
--		case COLOR_SPACE_YCBCR601_YONLY:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
- 			/* YCbCr601 */
- 			set_reg_field_value(
- 				value,
-@@ -856,7 +856,7 @@ static bool configure_graphics_mode_v(
- 			break;
- 		case COLOR_SPACE_YCBCR709:
- 		case COLOR_SPACE_YPBPR709:
--		case COLOR_SPACE_YCBCR709_YONLY:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
- 			/* YCbCr709 */
- 			set_reg_field_value(
- 				value,
-@@ -870,7 +870,7 @@ static bool configure_graphics_mode_v(
- 
- 	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
- 		switch (color_space) {
--		case COLOR_SPACE_SRGB_FULL_RANGE:
-+		case COLOR_SPACE_SRGB:
- 			/* by pass */
- 			set_reg_field_value(
- 				value,
-@@ -878,12 +878,12 @@ static bool configure_graphics_mode_v(
- 				COL_MAN_OUTPUT_CSC_CONTROL,
- 				OUTPUT_CSC_MODE);
- 			break;
--		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		case COLOR_SPACE_SRGB_LIMITED:
- 			/* not supported for underlay on CZ */
- 			return false;
- 		case COLOR_SPACE_YCBCR601:
- 		case COLOR_SPACE_YPBPR601:
--		case COLOR_SPACE_YCBCR601_YONLY:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
- 			/* YCbCr601 */
- 			set_reg_field_value(
- 				value,
-@@ -893,7 +893,7 @@ static bool configure_graphics_mode_v(
- 			break;
- 		case COLOR_SPACE_YCBCR709:
- 		case COLOR_SPACE_YPBPR709:
--		case COLOR_SPACE_YCBCR709_YONLY:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
- 			 /* YCbCr709 */
- 			set_reg_field_value(
- 				value,
-@@ -963,6 +963,170 @@ static void set_Denormalization(struct output_pixel_processor *opp,
- 	dm_write_reg(opp->ctx, mmDENORM_CLAMP_CONTROL, value);
- }
- 
-+struct input_csc_matrix {
-+	enum dc_color_space color_space;
-+	uint32_t regval[12];
-+};
-+
-+static const struct input_csc_matrix input_csc_matrix[] = {
-+	{COLOR_SPACE_SRGB,
-+/*1_1   1_2   1_3   1_4   2_1   2_2   2_3   2_4   3_1   3_2   3_3   3_4 */
-+		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+	{COLOR_SPACE_SRGB_LIMITED,
-+		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+	{COLOR_SPACE_YCBCR601,
-+		{0x2cdd, 0x2000, 0x0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
-+						0x0, 0x2000, 0x38b4, 0xe3a6} },
-+	{COLOR_SPACE_YCBCR601_LIMITED,
-+		{0x3353, 0x2568, 0x0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
-+						0x0, 0x2568, 0x40de, 0xdd3a} },
-+	{COLOR_SPACE_YCBCR709,
-+		{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
-+						0x2000, 0x3b61, 0xe24f} },
-+	{COLOR_SPACE_YCBCR709_LIMITED,
-+		{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
-+						0x2568, 0x43ee, 0xdbb2} }
-+};
-+
-+static void program_input_csc(
-+	struct output_pixel_processor *opp, enum dc_color_space color_space)
-+{
-+	int arr_size = sizeof(input_csc_matrix)/sizeof(struct input_csc_matrix);
-+	struct dc_context *ctx = opp->ctx;
-+	const uint32_t *regval = NULL;
-+	bool use_set_a;
-+	uint32_t value;
-+	int i;
-+
-+	for (i = 0; i < arr_size; i++)
-+		if (input_csc_matrix[i].color_space == color_space) {
-+			regval = input_csc_matrix[i].regval;
-+			break;
-+		}
-+	if (regval == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/*
-+	 * 1 == set A, the logic is 'if currently we're not using set A,
-+	 * then use set A, otherwise use set B'
-+	 */
-+	value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL);
-+	use_set_a = get_reg_field_value(
-+		value, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_MODE) != 1;
-+
-+	if (use_set_a) {
-+		/* fixed S2.13 format */
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[0], INPUT_CSC_C11_C12_A, INPUT_CSC_C11_A);
-+		set_reg_field_value(
-+			value, regval[1], INPUT_CSC_C11_C12_A, INPUT_CSC_C12_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C11_C12_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[2], INPUT_CSC_C13_C14_A, INPUT_CSC_C13_A);
-+		set_reg_field_value(
-+			value, regval[3], INPUT_CSC_C13_C14_A, INPUT_CSC_C14_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C13_C14_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[4], INPUT_CSC_C21_C22_A, INPUT_CSC_C21_A);
-+		set_reg_field_value(
-+			value, regval[5], INPUT_CSC_C21_C22_A, INPUT_CSC_C22_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C21_C22_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[6], INPUT_CSC_C23_C24_A, INPUT_CSC_C23_A);
-+		set_reg_field_value(
-+			value, regval[7], INPUT_CSC_C23_C24_A, INPUT_CSC_C24_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C23_C24_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[8], INPUT_CSC_C31_C32_A, INPUT_CSC_C31_A);
-+		set_reg_field_value(
-+			value, regval[9], INPUT_CSC_C31_C32_A, INPUT_CSC_C32_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C31_C32_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[10], INPUT_CSC_C33_C34_A, INPUT_CSC_C33_A);
-+		set_reg_field_value(
-+			value, regval[11], INPUT_CSC_C33_C34_A, INPUT_CSC_C34_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C33_C34_A, value);
-+	} else {
-+		/* fixed S2.13 format */
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[0], INPUT_CSC_C11_C12_B, INPUT_CSC_C11_B);
-+		set_reg_field_value(
-+			value, regval[1], INPUT_CSC_C11_C12_B, INPUT_CSC_C12_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C11_C12_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[2], INPUT_CSC_C13_C14_B, INPUT_CSC_C13_B);
-+		set_reg_field_value(
-+			value, regval[3], INPUT_CSC_C13_C14_B, INPUT_CSC_C14_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C13_C14_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[4], INPUT_CSC_C21_C22_B, INPUT_CSC_C21_B);
-+		set_reg_field_value(
-+			value, regval[5], INPUT_CSC_C21_C22_B, INPUT_CSC_C22_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C21_C22_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[6], INPUT_CSC_C23_C24_B, INPUT_CSC_C23_B);
-+		set_reg_field_value(
-+			value, regval[7], INPUT_CSC_C23_C24_B, INPUT_CSC_C24_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C23_C24_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[8], INPUT_CSC_C31_C32_B, INPUT_CSC_C31_B);
-+		set_reg_field_value(
-+			value, regval[9], INPUT_CSC_C31_C32_B, INPUT_CSC_C32_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C31_C32_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[10], INPUT_CSC_C33_C34_B, INPUT_CSC_C33_B);
-+		set_reg_field_value(
-+			value, regval[11], INPUT_CSC_C33_C34_B, INPUT_CSC_C34_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C33_C34_B, value);
-+	}
-+
-+	/* KK: leave INPUT_CSC_CONVERSION_MODE at default */
-+	value = 0;
-+	/*
-+	 * select 8.4 input type instead of default 12.0. From the discussion
-+	 * with HW team, this format depends on the UNP surface format, so for
-+	 * 8-bit we should select 8.4 (4 bits truncated). For 10 it should be
-+	 * 10.2. For Carrizo we only support 8-bit surfaces on underlay pipe
-+	 * so we can always keep this at 8.4 (input_type=2). If the later asics
-+	 * start supporting 10+ bits, we will have a problem: surface
-+	 * programming including UNP_GRPH* is being done in DalISR after this,
-+	 * so either we pass surface format to here, or move this logic to ISR
-+	 */
-+
-+	set_reg_field_value(
-+		value, 2, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_INPUT_TYPE);
-+	set_reg_field_value(
-+		value,
-+		use_set_a ? 1 : 2,
-+		COL_MAN_INPUT_CSC_CONTROL,
-+		INPUT_CSC_MODE);
-+
-+	dm_write_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL, value);
-+}
- 
- void dce110_opp_v_set_csc_default(
- 	struct output_pixel_processor *opp,
-@@ -988,7 +1152,7 @@ void dce110_opp_v_set_csc_default(
- 
- 		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
- 			elm = &global_color_matrix[i];
--			if (elm->color_space != default_adjust->color_space)
-+			if (elm->color_space != default_adjust->out_color_space)
- 				continue;
- 			/* program the matrix with default values from this
- 			 * file
-@@ -999,6 +1163,8 @@ void dce110_opp_v_set_csc_default(
- 		}
- 	}
- 
-+	program_input_csc(opp, default_adjust->in_color_space);
-+
- 	/* configure the what we programmed :
- 	 * 1. Default values from this file
- 	 * 2. Use hardware default from ROM_A and we do not need to program
-@@ -1007,7 +1173,7 @@ void dce110_opp_v_set_csc_default(
- 
- 	configure_graphics_mode_v(opp110, config,
- 		default_adjust->csc_adjust_type,
--		default_adjust->color_space);
-+		default_adjust->out_color_space);
- 
- 	set_Denormalization(opp, default_adjust->color_depth);
- }
-@@ -1026,13 +1192,13 @@ void dce110_opp_v_set_csc_adjustment(
- 	 * to the old legacy routines
- 	 */
- 	switch (adjust->c_space) {
--	case COLOR_SPACE_SRGB_FULL_RANGE:
-+	case COLOR_SPACE_SRGB:
- 		set_rgb_adjustment_legacy(opp110, adjust);
- 		break;
- 	case COLOR_SPACE_YCBCR601:
- 	case COLOR_SPACE_YCBCR709:
--	case COLOR_SPACE_YCBCR601_YONLY:
--	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
- 	case COLOR_SPACE_YPBPR601:
- 	case COLOR_SPACE_YPBPR709:
- 		set_yuv_adjustment(opp110, adjust);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-index 235b92e..2abc01c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
-@@ -561,7 +561,7 @@ void dce110_opp_program_clamping_and_pixel_encoding(
- 
- void dce110_opp_set_dyn_expansion(
- 	struct output_pixel_processor *opp,
--	enum color_space color_sp,
-+	enum dc_color_space color_sp,
- 	enum dc_color_depth color_dpth,
- 	enum signal_type signal)
- {
-@@ -580,7 +580,7 @@ void dce110_opp_set_dyn_expansion(
- 	/* From HW programming guide:
- 		FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output
- 		FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/
--	if (color_sp == COLOR_SPACE_SRGB_FULL_RANGE)
-+	if (color_sp == COLOR_SPACE_SRGB)
- 		enable_dyn_exp = true;
- 
- 	/*00 - 10-bit -> 12-bit dynamic expansion*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 4e3276b..d4c5944 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -191,7 +191,7 @@ static void dce110_timing_generator_apply_front_porch_workaround(
- }
- 
- void dce110_timing_generator_color_space_to_black_color(
--		enum color_space colorspace,
-+		enum dc_color_space colorspace,
- 	struct crtc_black_color *black_color)
- {
- 	switch (colorspace) {
-@@ -205,17 +205,7 @@ void dce110_timing_generator_color_space_to_black_color(
- 		*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
- 		break;
- 
--	case COLOR_SPACE_N_MVPU_SUPER_AA:
--		/* In crossfire SuperAA mode, the slave overscan data is forced
--		 * to 0 in the pixel mixer on the master.  As a result, we need
--		 * to adjust the blank color so that after blending the
--		 * master+slave, it will appear black
--		 */
--		*black_color =
--			black_color_format[BLACK_COLOR_FORMAT_YUV_SUPER_AA];
--		break;
--
--	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+	case COLOR_SPACE_SRGB_LIMITED:
- 		*black_color =
- 			black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
- 		break;
-@@ -301,7 +291,7 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 
- void dce110_timing_generator_program_blank_color(
- 		struct timing_generator *tg,
--		enum color_space color_space)
-+		enum dc_color_space color_space)
- {
- 	struct crtc_black_color black_color;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-@@ -1625,7 +1615,7 @@ void dce110_timing_generator_disable_vga(
- 
- void dce110_timing_generator_set_overscan_color_black(
- 	struct timing_generator *tg,
--	enum color_space black_color)
-+	enum dc_color_space black_color)
- {
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
-@@ -1659,8 +1649,8 @@ void dce110_timing_generator_set_overscan_color_black(
- 	case COLOR_SPACE_YPBPR709:
- 	case COLOR_SPACE_YCBCR601:
- 	case COLOR_SPACE_YCBCR709:
--	case COLOR_SPACE_YCBCR601_YONLY:
--	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
- 		set_reg_field_value(
- 			value,
- 			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV,
-@@ -1680,31 +1670,7 @@ void dce110_timing_generator_set_overscan_color_black(
- 			CRTC_OVERSCAN_COLOR_RED);
- 		break;
- 
--	case COLOR_SPACE_N_MVPU_SUPER_AA:
--		/* In crossfire SuperAA mode, the slave overscan data is forced
--		 * to 0 in the pixel mixer on the master.  As a result, we need
--		 * to adjust the blank color so that after blending the
--		 * master+slave, it will appear black */
--		set_reg_field_value(
--			value,
--			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4SUPERAA,
--			CRTC_OVERSCAN_COLOR,
--			CRTC_OVERSCAN_COLOR_BLUE);
--
--		set_reg_field_value(
--			value,
--			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4SUPERAA,
--			CRTC_OVERSCAN_COLOR,
--			CRTC_OVERSCAN_COLOR_GREEN);
--
--		set_reg_field_value(
--			value,
--			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA,
--			CRTC_OVERSCAN_COLOR,
--			CRTC_OVERSCAN_COLOR_RED);
--		break;
--
--	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+	case COLOR_SPACE_SRGB_LIMITED:
- 		set_reg_field_value(
- 			value,
- 			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_RGB_LIMITED_RANGE,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 3579736..9c5e390 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -170,13 +170,13 @@ void dce110_timing_generator_program_blanking(
- /* Combine with below and move YUV/RGB color conversion to SW layer */
- void dce110_timing_generator_program_blank_color(
- 	struct timing_generator *tg,
--	enum color_space color_space);
-+	enum dc_color_space color_space);
- /* Combine with above and move YUV/RGB color conversion to SW layer */
- void dce110_timing_generator_set_overscan_color_black(
- 	struct timing_generator *tg,
--	enum color_space black_color);
-+	enum dc_color_space black_color);
- void dce110_timing_generator_color_space_to_black_color(
--		enum color_space colorspace,
-+		enum dc_color_space colorspace,
- 	struct crtc_black_color *black_color);
- /*************** End-of-move ********************/
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index 99e8809..caf6631 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -393,7 +393,7 @@ static void dce110_timing_generator_v_program_timing(struct timing_generator *tg
- 
- static void dce110_timing_generator_v_program_blank_color(
- 		struct timing_generator *tg,
--		enum color_space color_space)
-+		enum dc_color_space color_space)
- {
- 	struct crtc_black_color black_color;
- 	uint32_t addr = mmCRTCV_BLACK_COLOR;
-@@ -424,7 +424,7 @@ static void dce110_timing_generator_v_program_blank_color(
- 
- static void dce110_timing_generator_v_set_overscan_color_black(
- 	struct timing_generator *tg,
--	enum color_space black_color)
-+	enum dc_color_space black_color)
- {
- 	struct dc_context *ctx = tg->ctx;
- 	uint32_t value = 0;
-@@ -458,8 +458,8 @@ static void dce110_timing_generator_v_set_overscan_color_black(
- 	case COLOR_SPACE_YPBPR709:
- 	case COLOR_SPACE_YCBCR601:
- 	case COLOR_SPACE_YCBCR709:
--	case COLOR_SPACE_YCBCR601_YONLY:
--	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
- 		set_reg_field_value(
- 			value,
- 			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4CV,
-@@ -479,31 +479,7 @@ static void dce110_timing_generator_v_set_overscan_color_black(
- 			CRTC_OVERSCAN_COLOR_RED);
- 		break;
- 
--	case COLOR_SPACE_N_MVPU_SUPER_AA:
--		/* In crossfire SuperAA mode, the slave overscan data is forced
--		 * to 0 in the pixel mixer on the master.  As a result, we need
--		 * to adjust the blank color so that after blending the
--		 * master+slave, it will appear black */
--		set_reg_field_value(
--			value,
--			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_CB_YUV_4SUPERAA,
--			CRTCV_OVERSCAN_COLOR,
--			CRTC_OVERSCAN_COLOR_BLUE);
--
--		set_reg_field_value(
--			value,
--			CRTC_OVERSCAN_COLOR_BLACK_COLOR_G_Y_YUV_4SUPERAA,
--			CRTCV_OVERSCAN_COLOR,
--			CRTC_OVERSCAN_COLOR_GREEN);
--
--		set_reg_field_value(
--			value,
--			CRTC_OVERSCAN_COLOR_BLACK_COLOR_R_CR_YUV_4SUPERAA,
--			CRTCV_OVERSCAN_COLOR,
--			CRTC_OVERSCAN_COLOR_RED);
--		break;
--
--	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+	case COLOR_SPACE_SRGB_LIMITED:
- 		set_reg_field_value(
- 			value,
- 			CRTC_OVERSCAN_COLOR_BLACK_COLOR_B_RGB_LIMITED_RANGE,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-index dba972f..032752c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
-@@ -54,7 +54,8 @@ static struct transform_funcs dce110_transform_funcs = {
- 	.transform_set_pixel_storage_depth =
- 		dce110_transform_set_pixel_storage_depth,
- 	.transform_get_current_pixel_storage_depth =
--		dce110_transform_get_current_pixel_storage_depth
-+		dce110_transform_get_current_pixel_storage_depth,
-+	.transform_set_alpha = dce110_transform_set_alpha
- };
- 
- /*****************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index f7c5565..7acbabc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -82,5 +82,6 @@ bool dce110_transform_get_current_pixel_storage_depth(
- 	struct transform *xfm,
- 	enum lb_pixel_depth *depth);
- 
-+void dce110_transform_set_alpha(struct transform *xfm, bool enable);
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-index 470453f..07f7d12 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
-@@ -588,11 +588,10 @@ bool dce110_transform_get_max_num_of_supported_lines(
- 	return true;
- }
- 
--void dce110_transform_enable_alpha(
--	struct dce110_transform *xfm110,
--	bool enable)
-+void dce110_transform_set_alpha(struct transform *xfm, bool enable)
- {
--	struct dc_context *ctx = xfm110->base.ctx;
-+	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
-+	struct dc_context *ctx = xfm->ctx;
- 	uint32_t value;
- 	uint32_t addr = LB_REG(mmLB_DATA_FORMAT);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-index 725f18c..e152306 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-@@ -123,7 +123,7 @@ void dce80_opp_program_clamping_and_pixel_encoding(
- 
- void dce80_opp_set_dyn_expansion(
- 	struct output_pixel_processor *opp,
--	enum color_space color_sp,
-+	enum dc_color_space color_sp,
- 	enum dc_color_depth color_dpth,
- 	enum signal_type signal);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-index 2ea6628..a8ad163 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-@@ -40,24 +40,24 @@ enum {
- };
- 
- struct out_csc_color_matrix {
--	enum color_space color_space;
-+	enum dc_color_space color_space;
- 	uint16_t regval[OUTPUT_CSC_MATRIX_SIZE];
- };
- 
- static const struct out_csc_color_matrix global_color_matrix[] = {
--{ COLOR_SPACE_SRGB_FULL_RANGE,
-+{ COLOR_SPACE_SRGB,
- 	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
--{ COLOR_SPACE_SRGB_LIMITED_RANGE,
-+{ COLOR_SPACE_SRGB_LIMITED,
- 	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
- { COLOR_SPACE_YCBCR601,
- 	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
- 		0xF6B9, 0xE00, 0x1000} },
- { COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
- 	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
--/*  YOnly same as YCbCr709 but Y in Full range -To do. */
--{ COLOR_SPACE_YCBCR601_YONLY, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+/* TODO: correct values below */
-+{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
- 	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
--{ COLOR_SPACE_YCBCR709_YONLY, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
- 	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
- };
- 
-@@ -675,7 +675,7 @@ static void set_yuv_adjustment(
- {
- 	bool b601 = (adjust->c_space == COLOR_SPACE_YPBPR601) ||
- 		(adjust->c_space == COLOR_SPACE_YCBCR601) ||
--		(adjust->c_space == COLOR_SPACE_YCBCR601_YONLY);
-+		(adjust->c_space == COLOR_SPACE_YCBCR601_LIMITED);
- 	struct out_csc_color_matrix reg_matrix;
- 	struct fixed31_32 matrix[OUTPUT_CSC_MATRIX_SIZE];
- 	struct dc_csc_adjustments adjustments;
-@@ -685,8 +685,8 @@ static void set_yuv_adjustment(
- 
- 	setup_adjustments(adjust, &adjustments);
- 
--	if ((adjust->c_space == COLOR_SPACE_YCBCR601_YONLY) ||
--		(adjust->c_space == COLOR_SPACE_YCBCR709_YONLY))
-+	if ((adjust->c_space == COLOR_SPACE_YCBCR601_LIMITED) ||
-+		(adjust->c_space == COLOR_SPACE_YCBCR709_LIMITED))
- 		calculate_adjustments_y_only(
- 			ideals, &adjustments, matrix);
- 	else
-@@ -704,7 +704,7 @@ static bool configure_graphics_mode(
- 	struct dce80_opp *opp80,
- 	enum csc_color_mode config,
- 	enum graphics_csc_adjust_type csc_adjust_type,
--	enum color_space color_space)
-+	enum dc_color_space color_space)
- {
- 	struct dc_context *ctx = opp80->base.ctx;
- 	uint32_t addr = DCP_REG(mmOUTPUT_CSC_CONTROL);
-@@ -726,7 +726,7 @@ static bool configure_graphics_mode(
- 		} else {
- 
- 			switch (color_space) {
--			case COLOR_SPACE_SRGB_FULL_RANGE:
-+			case COLOR_SPACE_SRGB:
- 				/* by pass */
- 				set_reg_field_value(
- 					value,
-@@ -734,7 +734,7 @@ static bool configure_graphics_mode(
- 					OUTPUT_CSC_CONTROL,
- 					OUTPUT_CSC_GRPH_MODE);
- 				break;
--			case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+			case COLOR_SPACE_SRGB_LIMITED:
- 				/* TV RGB */
- 				set_reg_field_value(
- 					value,
-@@ -744,7 +744,7 @@ static bool configure_graphics_mode(
- 				break;
- 			case COLOR_SPACE_YCBCR601:
- 			case COLOR_SPACE_YPBPR601:
--			case COLOR_SPACE_YCBCR601_YONLY:
-+			case COLOR_SPACE_YCBCR601_LIMITED:
- 				/* YCbCr601 */
- 				set_reg_field_value(
- 					value,
-@@ -754,7 +754,7 @@ static bool configure_graphics_mode(
- 				break;
- 			case COLOR_SPACE_YCBCR709:
- 			case COLOR_SPACE_YPBPR709:
--			case COLOR_SPACE_YCBCR709_YONLY:
-+			case COLOR_SPACE_YCBCR709_LIMITED:
- 				/* YCbCr709 */
- 				set_reg_field_value(
- 					value,
-@@ -768,7 +768,7 @@ static bool configure_graphics_mode(
- 		}
- 	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
- 		switch (color_space) {
--		case COLOR_SPACE_SRGB_FULL_RANGE:
-+		case COLOR_SPACE_SRGB:
- 			/* by pass */
- 			set_reg_field_value(
- 				value,
-@@ -776,7 +776,7 @@ static bool configure_graphics_mode(
- 				OUTPUT_CSC_CONTROL,
- 				OUTPUT_CSC_GRPH_MODE);
- 			break;
--		case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+		case COLOR_SPACE_SRGB_LIMITED:
- 			/* TV RGB */
- 			set_reg_field_value(
- 				value,
-@@ -786,7 +786,7 @@ static bool configure_graphics_mode(
- 			break;
- 		case COLOR_SPACE_YCBCR601:
- 		case COLOR_SPACE_YPBPR601:
--		case COLOR_SPACE_YCBCR601_YONLY:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
- 			/* YCbCr601 */
- 			set_reg_field_value(
- 				value,
-@@ -796,7 +796,7 @@ static bool configure_graphics_mode(
- 			break;
- 		case COLOR_SPACE_YCBCR709:
- 		case COLOR_SPACE_YPBPR709:
--		case COLOR_SPACE_YCBCR709_YONLY:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
- 			 /* YCbCr709 */
- 			set_reg_field_value(
- 				value,
-@@ -835,17 +835,17 @@ void dce80_opp_set_csc_adjustment(
- 	 * the ideal values only, but keep original design to allow quick switch
- 	 * to the old legacy routines */
- 	switch (adjust->c_space) {
--	case COLOR_SPACE_SRGB_FULL_RANGE:
-+	case COLOR_SPACE_SRGB:
- 		set_rgb_adjustment_legacy(opp80, adjust);
- 		break;
--	case COLOR_SPACE_SRGB_LIMITED_RANGE:
-+	case COLOR_SPACE_SRGB_LIMITED:
- 		set_rgb_limited_range_adjustment(
- 			opp80, adjust);
- 		break;
- 	case COLOR_SPACE_YCBCR601:
- 	case COLOR_SPACE_YCBCR709:
--	case COLOR_SPACE_YCBCR601_YONLY:
--	case COLOR_SPACE_YCBCR709_YONLY:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
- 	case COLOR_SPACE_YPBPR601:
- 	case COLOR_SPACE_YPBPR709:
- 		set_yuv_adjustment(opp80, adjust);
-@@ -884,7 +884,7 @@ void dce80_opp_set_csc_default(
- 
- 		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
- 			elm = &global_color_matrix[i];
--			if (elm->color_space != default_adjust->color_space)
-+			if (elm->color_space != default_adjust->out_color_space)
- 				continue;
- 			/* program the matrix with default values from this
- 			 * file */
-@@ -901,5 +901,5 @@ void dce80_opp_set_csc_default(
- 
- 	configure_graphics_mode(opp80, config,
- 		default_adjust->csc_adjust_type,
--		default_adjust->color_space);
-+		default_adjust->out_color_space);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c
-index 9d0a214..5df1749 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_formatter.c
-@@ -528,7 +528,7 @@ void dce80_opp_program_clamping_and_pixel_encoding(
- 
- void dce80_opp_set_dyn_expansion(
- 	struct output_pixel_processor *opp,
--	enum color_space color_sp,
-+	enum dc_color_space color_sp,
- 	enum dc_color_depth color_dpth,
- 	enum signal_type signal)
- {
-@@ -547,7 +547,7 @@ void dce80_opp_set_dyn_expansion(
- 	/* From HW programming guide:
- 		FMT_DYNAMIC_EXP_EN = 0 for limited RGB or YCbCr output
- 		FMT_DYNAMIC_EXP_EN = 1 for RGB full range only*/
--	if (color_sp == COLOR_SPACE_SRGB_FULL_RANGE)
-+	if (color_sp == COLOR_SPACE_SRGB)
- 		enable_dyn_exp = true;
- 
- 	/*00 - 10-bit -> 12-bit dynamic expansion*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-index f0c852a..1c9b732 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-@@ -230,7 +230,8 @@ enum graphics_csc_adjust_type {
- 
- struct default_adjustment {
- 	uint32_t lb_color_depth;
--	enum color_space color_space;
-+	enum dc_color_space out_color_space;
-+	enum dc_color_space in_color_space;
- 	enum dc_color_depth color_depth;
- 	enum pixel_format surface_pixel_format;
- 	enum graphics_csc_adjust_type csc_adjust_type;
-@@ -244,7 +245,7 @@ enum grph_color_adjust_option {
- 
- struct opp_grph_csc_adjustment {
- 	enum grph_color_adjust_option color_adjust_option;
--	enum color_space c_space;
-+	enum dc_color_space c_space;
- 	enum dc_color_depth color_depth; /* clean up to uint32_t */
- 	enum graphics_csc_adjust_type   csc_adjust_type;
- 	int32_t adjust_divider;
-@@ -307,7 +308,7 @@ struct opp_funcs {
- 
- 	void (*opp_set_dyn_expansion)(
- 		struct output_pixel_processor *opp,
--		enum color_space color_sp,
-+		enum dc_color_space color_sp,
- 		enum dc_color_depth color_dpth,
- 		enum signal_type signal);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-index 7ef22ad..374e222 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-@@ -132,8 +132,8 @@ struct timing_generator_funcs {
- 							enum crtc_state state);
- 	bool (*set_blank)(struct timing_generator *tg,
- 					   bool enable_blanking);
--	void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color);
--	void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color);
-+	void (*set_overscan_blank_color) (struct timing_generator *tg, enum dc_color_space black_color);
-+	void (*set_blank_color)(struct timing_generator *tg, enum dc_color_space black_color);
- 	void (*set_colors)(struct timing_generator *tg,
- 						const struct crtc_black_color *blank_color,
- 						const struct crtc_black_color *overscan_color);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-index 87dbff3..bf84f96 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-@@ -185,6 +185,8 @@ struct transform_funcs {
- 	bool (*transform_get_current_pixel_storage_depth)(
- 		struct transform *xfm,
- 		enum lb_pixel_depth *depth);
-+
-+	void (*transform_set_alpha)(struct transform *xfm, bool enable);
- };
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index d8526d3..58dcc04 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -107,9 +107,4 @@ struct ovl_csc_adjustment {
- 
- };
- 
--struct input_csc_matrix {
--	enum color_space color_space;
--	uint16_t regval[12];
--};
--
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0845-drm-amd-dal-fix-4th-display-cursor.patch b/common/recipes-kernel/linux/files/0845-drm-amd-dal-fix-4th-display-cursor.patch
deleted file mode 100644
index 70dfde13..00000000
--- a/common/recipes-kernel/linux/files/0845-drm-amd-dal-fix-4th-display-cursor.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 2eceb22c365683c61e6f407c26d44d433c5f0eeb Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Fri, 26 Feb 2016 14:06:45 -0500
-Subject: [PATCH 0845/1110] drm/amd/dal: fix 4th display cursor
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 6 ------
- 1 file changed, 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index e892a2f..66aae5f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -448,9 +448,6 @@ bool dc_target_set_cursor_attributes(
- 			struct input_pixel_processor *ipp =
- 						res_ctx->pipe_ctx[j].ipp;
- 
--			if (j == DCE110_UNDERLAY_IDX)
--				continue;
--
- 			if (res_ctx->pipe_ctx[j].stream !=
- 				DC_STREAM_TO_CORE(target->public.streams[i]))
- 				continue;
-@@ -494,9 +491,6 @@ bool dc_target_set_cursor_position(
- 			struct input_pixel_processor *ipp =
- 						res_ctx->pipe_ctx[j].ipp;
- 
--			if (j == DCE110_UNDERLAY_IDX)
--				continue;
--
- 			if (res_ctx->pipe_ctx[j].stream !=
- 				DC_STREAM_TO_CORE(target->public.streams[i]))
- 				continue;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0846-drm-amd-dal-Prevent-underflow-lock.patch b/common/recipes-kernel/linux/files/0846-drm-amd-dal-Prevent-underflow-lock.patch
deleted file mode 100644
index 0b09b454..00000000
--- a/common/recipes-kernel/linux/files/0846-drm-amd-dal-Prevent-underflow-lock.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 514f76d9dcfd503d00c0905303a4fb580f566dd9 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Fri, 26 Feb 2016 15:42:45 -0500
-Subject: [PATCH 0846/1110] drm/amd/dal: Prevent underflow lock
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c | 12 ++++--------
- 1 file changed, 4 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index d4c5944..d554332 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -273,17 +273,13 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	uint32_t value;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	value = dm_read_reg(tg->ctx,
--			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
--	set_reg_field_value(value, 0,
--			CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
--	dm_write_reg(tg->ctx,
--			CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
--
--	/* TODO: may want this on for looking for underflow */
- 	value = 0;
- 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
-+	/* TODO: may want this on to catch underflow */
-+	value = 0;
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value);
-+
- 	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
- 
- 	return result == BP_RESULT_OK;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch b/common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch
deleted file mode 100644
index f5648011..00000000
--- a/common/recipes-kernel/linux/files/0847-drm-amd-dal-Refactor-PPLib-interfaces.patch
+++ /dev/null
@@ -1,626 +0,0 @@
-From 4f8dfe4d331cfa5ecb96693591fc21a871bd341b Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Wed, 17 Feb 2016 16:28:47 -0500
-Subject: [PATCH 0847/1110] drm/amd/dal: Refactor PPLib interfaces
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c |  66 +++++-----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   8 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  11 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   1 +
- drivers/gpu/drm/amd/dal/dc/dm_services.h           | 146 +--------------------
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h     | 102 ++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |   2 +-
- 8 files changed, 155 insertions(+), 183 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index b155270..116d34d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -75,7 +75,7 @@ int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
- 	return memcmp(p1, p2, count);
- }
- 
--int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count)
-+int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count)
- {
- 	return strncmp(p1, p2, count);
- }
-@@ -150,8 +150,8 @@ bool dm_get_platform_info(struct dc_context *ctx,
- 
- bool dm_pp_pre_dce_clock_change(
- 		struct dc_context *ctx,
--		struct dal_to_power_info *input,
--		struct power_to_dal_info *output)
-+		struct dm_pp_gpu_clock_range *requested_state,
-+		struct dm_pp_gpu_clock_range *actual_state)
- {
- 	/*TODO*/
- 	return false;
-@@ -175,7 +175,7 @@ bool dm_pp_apply_safe_state(
- 
- bool dm_pp_apply_display_requirements(
- 		const struct dc_context *ctx,
--		const struct dc_pp_display_configuration *pp_display_cfg)
-+		const struct dm_pp_display_configuration *pp_display_cfg)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	struct amdgpu_device *adev = ctx->driver_context;
-@@ -248,26 +248,26 @@ bool dm_pp_apply_display_requirements(
- 
- bool dc_service_get_system_clocks_range(
- 		const struct dc_context *ctx,
--		struct dal_system_clock_range *sys_clks)
-+		struct dm_pp_gpu_clock_range *sys_clks)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	struct amdgpu_device *adev = ctx->driver_context;
- #endif
- 
- 	/* Default values, in case PPLib is not compiled-in. */
--	sys_clks->max_mclk = 80000;
--	sys_clks->min_mclk = 80000;
-+	sys_clks->mclk.max_khz = 800000;
-+	sys_clks->mclk.min_khz = 800000;
- 
--	sys_clks->max_sclk = 60000;
--	sys_clks->min_sclk = 30000;
-+	sys_clks->sclk.max_khz = 600000;
-+	sys_clks->sclk.min_khz = 300000;
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	if (adev->pm.dpm_enabled) {
--		sys_clks->max_mclk = amdgpu_dpm_get_mclk(adev, false);
--		sys_clks->min_mclk = amdgpu_dpm_get_mclk(adev, true);
-+		sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false);
-+		sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true);
- 
--		sys_clks->max_sclk = amdgpu_dpm_get_sclk(adev, false);
--		sys_clks->min_sclk = amdgpu_dpm_get_sclk(adev, true);
-+		sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false);
-+		sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true);
- 	}
- #endif
- 
-@@ -275,8 +275,8 @@ bool dc_service_get_system_clocks_range(
- }
- 
- static void get_default_clock_levels(
--		enum dc_pp_clock_type clk_type,
--		struct dc_pp_clock_levels *clks)
-+		enum dm_pp_clock_type clk_type,
-+		struct dm_pp_clock_levels *clks)
- {
- 	uint32_t disp_clks_in_khz[6] = {
- 			300000, 400000, 496560, 626090, 685720, 757900 };
-@@ -285,17 +285,17 @@ static void get_default_clock_levels(
- 	uint32_t mclks_in_khz[2] = { 333000, 800000 };
- 
- 	switch (clk_type) {
--	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
- 		clks->num_levels = 6;
- 		dm_memmove(clks->clocks_in_khz, disp_clks_in_khz,
- 				sizeof(disp_clks_in_khz));
- 		break;
--	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
- 		clks->num_levels = 6;
- 		dm_memmove(clks->clocks_in_khz, sclks_in_khz,
- 				sizeof(sclks_in_khz));
- 		break;
--	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
- 		clks->num_levels = 2;
- 		dm_memmove(clks->clocks_in_khz, mclks_in_khz,
- 				sizeof(mclks_in_khz));
-@@ -308,23 +308,23 @@ static void get_default_clock_levels(
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- static enum amd_pp_clock_type dc_to_pp_clock_type(
--		enum dc_pp_clock_type dc_pp_clk_type)
-+		enum dm_pp_clock_type dm_pp_clk_type)
- {
- 	enum amd_pp_clock_type amd_pp_clk_type = 0;
- 
--	switch (dc_pp_clk_type) {
--	case DC_PP_CLOCK_TYPE_DISPLAY_CLK:
-+	switch (dm_pp_clk_type) {
-+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
- 		amd_pp_clk_type = amd_pp_disp_clock;
- 		break;
--	case DC_PP_CLOCK_TYPE_ENGINE_CLK:
-+	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
- 		amd_pp_clk_type = amd_pp_sys_clock;
- 		break;
--	case DC_PP_CLOCK_TYPE_MEMORY_CLK:
-+	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
- 		amd_pp_clk_type = amd_pp_mem_clock;
- 		break;
- 	default:
- 		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
--				dc_pp_clk_type);
-+				dm_pp_clk_type);
- 		break;
- 	}
- 
-@@ -333,18 +333,18 @@ static enum amd_pp_clock_type dc_to_pp_clock_type(
- 
- static void pp_to_dc_clock_levels(
- 		const struct amd_pp_clocks *pp_clks,
--		struct dc_pp_clock_levels *dc_clks,
--		enum dc_pp_clock_type dc_clk_type)
-+		struct dm_pp_clock_levels *dc_clks,
-+		enum dm_pp_clock_type dc_clk_type)
- {
- 	uint32_t i;
- 
--	if (pp_clks->count > DC_PP_MAX_CLOCK_LEVELS) {
-+	if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
- 		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
- 				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
- 				pp_clks->count,
--				DC_PP_MAX_CLOCK_LEVELS);
-+				DM_PP_MAX_CLOCK_LEVELS);
- 
--		dc_clks->num_levels = DC_PP_MAX_CLOCK_LEVELS;
-+		dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
- 	} else
- 		dc_clks->num_levels = pp_clks->count;
- 
-@@ -361,8 +361,8 @@ static void pp_to_dc_clock_levels(
- 
- bool dm_pp_get_clock_levels_by_type(
- 		const struct dc_context *ctx,
--		enum dc_pp_clock_type clk_type,
--		struct dc_pp_clock_levels *dc_clks)
-+		enum dm_pp_clock_type clk_type,
-+		struct dm_pp_clock_levels *dc_clks)
- {
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	struct amdgpu_device *adev = ctx->driver_context;
-@@ -402,7 +402,7 @@ bool dm_pp_get_clock_levels_by_type(
- 	validation_clks.memory_max_clock *= 10;
- 
- 	/* Determine the highest non-boosted level from the Validation Clocks */
--	if (clk_type == DC_PP_CLOCK_TYPE_ENGINE_CLK) {
-+	if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
- 		for (i = 0; i < dc_clks->num_levels; i++) {
- 			if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
- 				/* This clock is higher the validation clock.
-@@ -414,7 +414,7 @@ bool dm_pp_get_clock_levels_by_type(
- 				break;
- 			}
- 		}
--	} else if (clk_type == DC_PP_CLOCK_TYPE_MEMORY_CLK) {
-+	} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
- 		for (i = 0; i < dc_clks->num_levels; i++) {
- 			if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
- 				DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 7eaf7ef..d02f3c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -259,12 +259,12 @@ static struct adapter_service *create_as(
- 
- static void bw_calcs_data_update_from_pplib(struct dc *dc)
- {
--	struct dc_pp_clock_levels clks = {0};
-+	struct dm_pp_clock_levels clks = {0};
- 
- 	/*do system clock*/
- 	dm_pp_get_clock_levels_by_type(
- 			dc->ctx,
--			DC_PP_CLOCK_TYPE_ENGINE_CLK,
-+			DM_PP_CLOCK_TYPE_ENGINE_CLK,
- 			&clks);
- 	/* convert all the clock fro kHz to fix point mHz */
- 	dc->bw_vbios.high_sclk = bw_frc_to_fixed(
-@@ -277,7 +277,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 	/*do display clock*/
- 	dm_pp_get_clock_levels_by_type(
- 			dc->ctx,
--			DC_PP_CLOCK_TYPE_DISPLAY_CLK,
-+			DM_PP_CLOCK_TYPE_DISPLAY_CLK,
- 			&clks);
- 
- 	dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
-@@ -290,7 +290,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 	/*do memory clock*/
- 	dm_pp_get_clock_levels_by_type(
- 			dc->ctx,
--			DC_PP_CLOCK_TYPE_MEMORY_CLK,
-+			DM_PP_CLOCK_TYPE_MEMORY_CLK,
- 			&clks);
- 
- 	dc->bw_vbios.low_yclk = bw_frc_to_fixed(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 1bb4adb..5e32289 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -476,7 +476,7 @@ static uint32_t get_min_vblank_time_us(const struct validate_context *context)
- 
- static void fill_display_configs(
- 	const struct validate_context *context,
--	struct dc_pp_display_configuration *pp_display_cfg)
-+	struct dm_pp_display_configuration *pp_display_cfg)
- {
- 	uint8_t i, j, k;
- 	uint8_t num_cfgs = 0;
-@@ -487,7 +487,7 @@ static void fill_display_configs(
- 		for (j = 0; j < target->public.stream_count; j++) {
- 			const struct core_stream *stream =
- 				DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct dc_pp_single_disp_config *cfg =
-+			struct dm_pp_single_disp_config *cfg =
- 					&pp_display_cfg->disp_configs[num_cfgs];
- 			const struct pipe_ctx *pipe_ctx = NULL;
- 
-@@ -507,8 +507,9 @@ static void fill_display_configs(
- 				stream->sink->link->ddi_channel_mapping.raw;
- 			cfg->transmitter =
- 				stream->sink->link->link_enc->transmitter;
--			cfg->link_settings =
--				stream->sink->link->public.cur_link_settings;
-+			cfg->link_settings.lane_count = stream->sink->link->public.cur_link_settings.lane_count;
-+			cfg->link_settings.link_rate = stream->sink->link->public.cur_link_settings.link_rate;
-+			cfg->link_settings.link_spread = stream->sink->link->public.cur_link_settings.link_spread;
- 			cfg->sym_clock = stream->public.timing.pix_clk_khz;
- 			switch (stream->public.timing.display_color_depth) {
- 			case COLOR_DEPTH_101010:
-@@ -539,7 +540,7 @@ void pplib_apply_safe_state(
- void pplib_apply_display_requirements(
- 	const struct dc *dc,
- 	const struct validate_context *context,
--	struct dc_pp_display_configuration *pp_display_cfg)
-+	struct dm_pp_display_configuration *pp_display_cfg)
- {
- 
- 	pp_display_cfg->all_displays_in_sync =
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 8d81d08..6b87b1d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -30,6 +30,7 @@
- #include "irq_types.h"
- #include "dc_dp_types.h"
- #include "dc_hw_types.h"
-+#include "signal_types.h"
- 
- /* forward declarations */
- struct dc;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 604aa43..5ba8be8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -54,7 +54,7 @@ void dm_memmove(void *dst, const void *src, uint32_t size);
- 
- int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
- 
--int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
-+int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count);
- 
- irq_handler_idx dm_register_interrupt(
- 	struct dc_context *ctx,
-@@ -205,53 +205,6 @@ uint32_t dm_bios_cmd_table_para_revision(
-  * Power Play (PP) interfaces
-  **************************************/
- 
--enum dal_to_power_clocks_state {
--	PP_CLOCKS_STATE_INVALID,
--	PP_CLOCKS_STATE_ULTRA_LOW,
--	PP_CLOCKS_STATE_LOW,
--	PP_CLOCKS_STATE_NOMINAL,
--	PP_CLOCKS_STATE_PERFORMANCE
--};
--
--/* clocks in khz */
--struct dal_to_power_info {
--	enum dal_to_power_clocks_state required_clock;
--	uint32_t min_sclk;
--	uint32_t min_mclk;
--	uint32_t min_deep_sleep_sclk;
--};
--
--/* clocks in khz */
--struct power_to_dal_info {
--	uint32_t min_sclk;
--	uint32_t max_sclk;
--	uint32_t min_mclk;
--	uint32_t max_mclk;
--};
--
--/* clocks in khz */
--struct dal_system_clock_range {
--	uint32_t min_sclk;
--	uint32_t max_sclk;
--
--	uint32_t min_mclk;
--	uint32_t max_mclk;
--
--	uint32_t min_dclk;
--	uint32_t max_dclk;
--
--	/* Wireless Display */
--	uint32_t min_eclk;
--	uint32_t max_eclk;
--};
--
--/* clocks in khz */
--struct dal_to_power_dclk {
--	uint32_t optimal; /* input: best optimizes for stutter efficiency */
--	uint32_t minimal; /* input: the lowest clk that DAL can support */
--	uint32_t established; /* output: the actually set one */
--};
--
- /* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-  * This is done *before* it changes DCE clock.
-  *
-@@ -270,75 +223,8 @@ struct dal_to_power_dclk {
-  */
- bool dm_pp_pre_dce_clock_change(
- 	struct dc_context *ctx,
--	struct dal_to_power_info *input,
--	struct power_to_dal_info *output);
--
--struct dc_pp_single_disp_config {
--	enum signal_type signal;
--	uint8_t transmitter;
--	uint8_t ddi_channel_mapping;
--	uint8_t pipe_idx;
--	uint32_t src_height;
--	uint32_t src_width;
--	uint32_t v_refresh;
--	uint32_t sym_clock; /* HDMI only */
--	struct dc_link_settings link_settings; /* DP only */
--};
--
--struct dc_pp_display_configuration {
--	bool nb_pstate_switch_disable;/* controls NB PState switch */
--	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
--	bool cpu_pstate_disable;
--	uint32_t cpu_pstate_separation_time;
--
--	uint32_t min_memory_clock_khz;
--	uint32_t min_engine_clock_khz;
--	uint32_t min_engine_clock_deep_sleep_khz;
--
--	uint32_t avail_mclk_switch_time_us;
--	uint32_t avail_mclk_switch_time_in_disp_active_us;
--
--	uint32_t disp_clk_khz;
--
--	bool all_displays_in_sync;
--
--	uint8_t display_count;
--	struct dc_pp_single_disp_config disp_configs[MAX_COFUNC_PATH];
--
--	/*Controller Index of primary display - used in MCLK SMC switching hang
--	 * SW Workaround*/
--	uint8_t crtc_index;
--	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
--	uint32_t line_time_in_us;
--};
--
--enum dc_pp_clocks_state {
--	DC_PP_CLOCKS_STATE_INVALID = 0,
--	DC_PP_CLOCKS_STATE_ULTRA_LOW,
--	DC_PP_CLOCKS_STATE_LOW,
--	DC_PP_CLOCKS_STATE_NOMINAL,
--	DC_PP_CLOCKS_STATE_PERFORMANCE,
--
--	/* Starting from DCE11, Max 8 levels of DPM state supported. */
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DC_PP_CLOCKS_STATE_INVALID,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_0 = DC_PP_CLOCKS_STATE_ULTRA_LOW,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_1 = DC_PP_CLOCKS_STATE_LOW,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_2 = DC_PP_CLOCKS_STATE_NOMINAL,
--	/* to be backward compatible */
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_3 = DC_PP_CLOCKS_STATE_PERFORMANCE,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_4 = DC_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_5 = DC_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_6 = DC_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
--	DC_PP_CLOCKS_DPM_STATE_LEVEL_7 = DC_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
--};
--
--struct dc_pp_static_clock_info {
--	uint32_t max_sclk_khz;
--	uint32_t max_mclk_khz;
--
--	 /* max possible display block clocks state */
--	enum dc_pp_clocks_state max_clocks_state;
--};
-+	struct dm_pp_gpu_clock_range *requested_state,
-+	struct dm_pp_gpu_clock_range *actual_state);
- 
- /* The returned clocks range are 'static' system clocks which will be used for
-  * mode validation purposes.
-@@ -348,25 +234,7 @@ struct dc_pp_static_clock_info {
-  */
- bool dc_service_get_system_clocks_range(
- 	const struct dc_context *ctx,
--	struct dal_system_clock_range *sys_clks);
--
--enum dc_pp_clock_type {
--	DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
--	DC_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
--	DC_PP_CLOCK_TYPE_MEMORY_CLK
--};
--
--#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
--	(clk_type) == DC_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
--	(clk_type) == DC_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
--	(clk_type) == DC_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
--
--#define DC_PP_MAX_CLOCK_LEVELS 8
--
--struct dc_pp_clock_levels {
--	uint32_t num_levels;
--	uint32_t clocks_in_khz[DC_PP_MAX_CLOCK_LEVELS];
--};
-+	struct dm_pp_gpu_clock_range *sys_clks);
- 
- /* Gets valid clocks levels from pplib
-  *
-@@ -378,8 +246,8 @@ struct dc_pp_clock_levels {
-  */
- bool dm_pp_get_clock_levels_by_type(
- 	const struct dc_context *ctx,
--	enum dc_pp_clock_type clk_type,
--	struct dc_pp_clock_levels *clk_level_info);
-+	enum dm_pp_clock_type clk_type,
-+	struct dm_pp_clock_levels *clk_level_info);
- 
- 
- bool dm_pp_apply_safe_state(
-@@ -398,7 +266,7 @@ bool dm_pp_apply_safe_state(
-  */
- bool dm_pp_apply_display_requirements(
- 	const struct dc_context *ctx,
--	const struct dc_pp_display_configuration *pp_display_cfg);
-+	const struct dm_pp_display_configuration *pp_display_cfg);
- 
- 
- /****** end of PP interfaces ******/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index 7c8b31f..a74fb85 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -162,4 +162,106 @@ static inline uint64_t div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem)
- 
- #endif
- 
-+#include "dc_types.h"
-+
-+struct dm_pp_clock_range {
-+	int min_khz;
-+	int max_khz;
-+};
-+
-+enum dm_pp_clocks_state {
-+	DM_PP_CLOCKS_STATE_INVALID,
-+	DM_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DM_PP_CLOCKS_STATE_LOW,
-+	DM_PP_CLOCKS_STATE_NOMINAL,
-+	DM_PP_CLOCKS_STATE_PERFORMANCE,
-+
-+	/* Starting from DCE11, Max 8 levels of DPM state supported. */
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_0 = DM_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_1 = DM_PP_CLOCKS_STATE_LOW,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_2 = DM_PP_CLOCKS_STATE_NOMINAL,
-+	/* to be backward compatible */
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_3 = DM_PP_CLOCKS_STATE_PERFORMANCE,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
-+};
-+
-+struct dm_pp_gpu_clock_range {
-+	enum dm_pp_clocks_state clock_state;
-+	struct dm_pp_clock_range sclk;
-+	struct dm_pp_clock_range mclk;
-+	struct dm_pp_clock_range eclk;
-+	struct dm_pp_clock_range dclk;
-+};
-+
-+enum dm_pp_clock_type {
-+	DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-+	DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
-+	DM_PP_CLOCK_TYPE_MEMORY_CLK
-+};
-+
-+#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
-+	(clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
-+	(clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-+	(clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
-+
-+#define DM_PP_MAX_CLOCK_LEVELS 8
-+
-+struct dm_pp_clock_levels {
-+	uint32_t num_levels;
-+	uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+struct dm_pp_single_disp_config {
-+	enum signal_type signal;
-+	uint8_t transmitter;
-+	uint8_t ddi_channel_mapping;
-+	uint8_t pipe_idx;
-+	uint32_t src_height;
-+	uint32_t src_width;
-+	uint32_t v_refresh;
-+	uint32_t sym_clock; /* HDMI only */
-+	struct dc_link_settings link_settings; /* DP only */
-+};
-+
-+#define MAX_DISPLAY_CONFIGS 6
-+
-+struct dm_pp_display_configuration {
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+
-+	uint32_t min_memory_clock_khz;
-+	uint32_t min_engine_clock_khz;
-+	uint32_t min_engine_clock_deep_sleep_khz;
-+
-+	uint32_t avail_mclk_switch_time_us;
-+	uint32_t avail_mclk_switch_time_in_disp_active_us;
-+
-+	uint32_t disp_clk_khz;
-+
-+	bool all_displays_in_sync;
-+
-+	uint8_t display_count;
-+	struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS];
-+
-+	/*Controller Index of primary display - used in MCLK SMC switching hang
-+	 * SW Workaround*/
-+	uint8_t crtc_index;
-+	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+	uint32_t line_time_in_us;
-+};
-+
-+struct dm_pp_static_clock_info {
-+	uint32_t max_sclk_khz;
-+	uint32_t max_mclk_khz;
-+
-+	 /* max possible display block clocks state */
-+	enum dm_pp_clocks_state max_clocks_state;
-+};
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 70b4a85..a5444cb 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -346,7 +346,7 @@ struct validate_context {
- 	/* The output from BW and WM calculations. */
- 	struct bw_calcs_output bw_results;
- 	/* Note: this is a big structure, do *not* put on stack! */
--	struct dc_pp_display_configuration pp_display_cfg;
-+	struct dm_pp_display_configuration pp_display_cfg;
- };
- 
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 983d484..717bf13 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -72,7 +72,7 @@ void pplib_apply_safe_state(const struct dc *dc);
- void pplib_apply_display_requirements(
- 	const struct dc *dc,
- 	const struct validate_context *context,
--	struct dc_pp_display_configuration *pp_display_cfg);
-+	struct dm_pp_display_configuration *pp_display_cfg);
- 
- void build_info_frame(struct pipe_ctx *pipe_ctx);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0848-drm-amd-dal-Remove-public-interfaces-for-target_memo.patch b/common/recipes-kernel/linux/files/0848-drm-amd-dal-Remove-public-interfaces-for-target_memo.patch
deleted file mode 100644
index 304eb661..00000000
--- a/common/recipes-kernel/linux/files/0848-drm-amd-dal-Remove-public-interfaces-for-target_memo.patch
+++ /dev/null
@@ -1,646 +0,0 @@
-From a9c0d2a29f4e8fca9ce1ddf46dd34eb8ae646680 Mon Sep 17 00:00:00 2001
-From: Aric Cyr <aric.cyr@amd.com>
-Date: Sat, 27 Feb 2016 10:00:34 -0500
-Subject: [PATCH 0848/1110] drm/amd/dal: Remove public interfaces for
- target_memory_request
-
-Rename dc_target_*_memory_request() and make it static in dc.
-
-Signed-off-by: Aric Cyr <aric.cyr@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c        | 273 ++++++++++++++++++++++++++-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 276 ----------------------------
- drivers/gpu/drm/amd/dal/dc/dc.h             |   3 -
- 3 files changed, 271 insertions(+), 281 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index d02f3c0..4ce2af2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -398,6 +398,72 @@ static void destruct(struct dc *dc)
- 	dm_free(dc->ctx, dc->ctx);
- }
- 
-+/*
-+void ProgramPixelDurationV(unsigned int pixelClockInKHz )
-+{
-+	fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
-+	unsigned int pixDurationInPico = round(pixel_duration);
-+
-+	DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
-+
-+	arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
-+	arb_control.bits.PIXEL_DURATION = pixDurationInPico;
-+	WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
-+
-+	arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
-+	arb_control.bits.PIXEL_DURATION = pixDurationInPico;
-+	WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
-+
-+	WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
-+	WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
-+
-+	WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
-+	WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
-+}
-+*/
-+static int8_t acquire_first_free_underlay(
-+		struct resource_context *res_ctx,
-+		struct core_stream *stream)
-+{
-+	if (!res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX].stream) {
-+		struct dc_bios *dcb;
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX];
-+
-+		pipe_ctx->tg = res_ctx->pool.timing_generators[DCE110_UNDERLAY_IDX];
-+		pipe_ctx->mi = res_ctx->pool.mis[DCE110_UNDERLAY_IDX];
-+		/*pipe_ctx->ipp = res_ctx->pool.ipps[DCE110_UNDERLAY_IDX];*/
-+		pipe_ctx->xfm = res_ctx->pool.transforms[DCE110_UNDERLAY_IDX];
-+		pipe_ctx->opp = res_ctx->pool.opps[DCE110_UNDERLAY_IDX];
-+		pipe_ctx->dis_clk = res_ctx->pool.display_clock;
-+		pipe_ctx->pipe_idx = DCE110_UNDERLAY_IDX;
-+
-+		dcb = dal_adapter_service_get_bios_parser(
-+						res_ctx->pool.adapter_srv);
-+
-+		stream->ctx->dc->hwss.enable_display_power_gating(
-+			stream->ctx->dc->ctx,
-+			DCE110_UNDERLAY_IDX,
-+			dcb, PIPE_GATING_CONTROL_DISABLE);
-+
-+		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
-+			dm_error("DC: failed to blank crtc!\n");
-+			BREAK_TO_DEBUGGER();
-+		}
-+
-+		if (!pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
-+			BREAK_TO_DEBUGGER();
-+		}
-+
-+		pipe_ctx->tg->funcs->set_blank_color(
-+				pipe_ctx->tg,
-+				COLOR_SPACE_YCBCR601);/* TODO unhardcode*/
-+
-+		pipe_ctx->stream = stream;
-+		return DCE110_UNDERLAY_IDX;
-+	}
-+	return -1;
-+}
-+
- /*******************************************************************************
-  * Public functions
-  ******************************************************************************/
-@@ -523,6 +589,52 @@ static bool targets_changed(
- 	return false;
- }
- 
-+static void target_enable_memory_requests(struct dc_target *dc_target)
-+{
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct resource_context *res_ctx =
-+		&target->ctx->dc->current_context.res_ctx;
-+
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
-+
-+			if (!tg->funcs->set_blank(tg, false)) {
-+				dm_error("DC: failed to unblank crtc!\n");
-+				BREAK_TO_DEBUGGER();
-+			}
-+		}
-+	}
-+}
-+
-+static void target_disable_memory_requests(struct dc_target *dc_target)
-+{
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct resource_context *res_ctx =
-+		&target->ctx->dc->current_context.res_ctx;
-+
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
-+
-+			if (!tg->funcs->set_blank(tg, true)) {
-+				dm_error("DC: failed to blank crtc!\n");
-+				BREAK_TO_DEBUGGER();
-+			}
-+		}
-+	}
-+}
-+
- bool dc_commit_targets(
- 	struct dc *dc,
- 	struct dc_target *targets[],
-@@ -576,7 +688,7 @@ bool dc_commit_targets(
- 
- 	for (i = 0; i < dc->current_context.target_count; i++) {
- 		/*TODO: optimize this to happen only when necessary*/
--		dc_target_disable_memory_requests(
-+		target_disable_memory_requests(
- 				&dc->current_context.targets[i]->public);
- 	}
- 
-@@ -590,7 +702,7 @@ bool dc_commit_targets(
- 	for (i = 0; i < context->target_count; i++) {
- 		struct dc_target *dc_target = &context->targets[i]->public;
- 		if (context->target_status[i].surface_count > 0)
--			dc_target_enable_memory_requests(dc_target);
-+			target_enable_memory_requests(dc_target);
- 	}
- 
- 	program_timing_sync(dc->ctx, context);
-@@ -608,6 +720,163 @@ context_alloc_fail:
- 	return (result == DC_OK);
- }
- 
-+bool dc_commit_surfaces_to_target(
-+		struct dc *dc,
-+		struct dc_surface *new_surfaces[],
-+		uint8_t new_surface_count,
-+		struct dc_target *dc_target)
-+
-+{
-+	int i, j;
-+	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct dc_target_status *target_status = NULL;
-+	struct validate_context *context;
-+	int current_enabled_surface_count = 0;
-+	int new_enabled_surface_count = 0;
-+	bool is_mpo_turning_on = false;
-+
-+	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
-+
-+	val_ctx_copy_construct(&dc->current_context, context);
-+
-+	/* Cannot commit surface to a target that is not commited */
-+	for (i = 0; i < context->target_count; i++)
-+		if (target == context->targets[i])
-+			break;
-+
-+	target_status = &context->target_status[i];
-+
-+	if (!dal_adapter_service_is_in_accelerated_mode(
-+						dc->res_pool.adapter_srv)
-+		|| i == context->target_count) {
-+		BREAK_TO_DEBUGGER();
-+		goto unexpected_fail;
-+	}
-+
-+	for (i = 0; i < target_status->surface_count; i++)
-+		if (target_status->surfaces[i]->visible)
-+			current_enabled_surface_count++;
-+
-+	for (i = 0; i < new_surface_count; i++)
-+		if (new_surfaces[i]->visible)
-+			new_enabled_surface_count++;
-+
-+	/* TODO unhack mpo */
-+	if (new_surface_count == 2 && target_status->surface_count < 2) {
-+		acquire_first_free_underlay(&context->res_ctx,
-+				DC_STREAM_TO_CORE(dc_target->streams[0]));
-+		is_mpo_turning_on = true;
-+	} else if (new_surface_count < 2 && target_status->surface_count == 2) {
-+		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].stream = NULL;
-+		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].surface = NULL;
-+	}
-+
-+	dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_INTERFACE_TRACE,
-+				LOG_MINOR_COMPONENT_DC,
-+				"%s: commit %d surfaces to target 0x%x\n",
-+				__func__,
-+				new_surface_count,
-+				dc_target);
-+
-+
-+	if (!attach_surfaces_to_context(
-+			new_surfaces, new_surface_count, dc_target, context)) {
-+		BREAK_TO_DEBUGGER();
-+		goto unexpected_fail;
-+	}
-+
-+	for (i = 0; i < new_surface_count; i++)
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (context->res_ctx.pipe_ctx[j].surface !=
-+					DC_SURFACE_TO_CORE(new_surfaces[i]))
-+				continue;
-+
-+			build_scaling_params(
-+				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
-+		}
-+
-+	if (dc->res_pool.funcs->validate_bandwidth(dc, context) != DC_OK) {
-+		BREAK_TO_DEBUGGER();
-+		goto unexpected_fail;
-+	}
-+
-+	if (prev_disp_clk < context->bw_results.dispclk_khz ||
-+		(is_mpo_turning_on &&
-+			prev_disp_clk == context->bw_results.dispclk_khz)) {
-+		dc->hwss.program_bw(dc, context);
-+		pplib_apply_display_requirements(dc, context,
-+						&context->pp_display_cfg);
-+	}
-+
-+	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
-+		target_disable_memory_requests(dc_target);
-+
-+	for (i = 0; i < new_surface_count; i++)
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct dc_surface *dc_surface = new_surfaces[i];
-+			struct core_surface *surface =
-+						DC_SURFACE_TO_CORE(dc_surface);
-+			struct pipe_ctx *pipe_ctx =
-+						&context->res_ctx.pipe_ctx[j];
-+			struct core_gamma *gamma = NULL;
-+
-+			if (pipe_ctx->surface !=
-+					DC_SURFACE_TO_CORE(new_surfaces[i]))
-+				continue;
-+
-+			dal_logger_write(dc->ctx->logger,
-+						LOG_MAJOR_INTERFACE_TRACE,
-+						LOG_MINOR_COMPONENT_DC,
-+						"Pipe:%d 0x%x: src: %d, %d, %d,"
-+						" %d; dst: %d, %d, %d, %d;\n",
-+						pipe_ctx->pipe_idx,
-+						dc_surface,
-+						dc_surface->src_rect.x,
-+						dc_surface->src_rect.y,
-+						dc_surface->src_rect.width,
-+						dc_surface->src_rect.height,
-+						dc_surface->dst_rect.x,
-+						dc_surface->dst_rect.y,
-+						dc_surface->dst_rect.width,
-+						dc_surface->dst_rect.height);
-+
-+			if (surface->public.gamma_correction)
-+				gamma = DC_GAMMA_TO_CORE(
-+					surface->public.gamma_correction);
-+
-+			dc->hwss.set_gamma_correction(
-+					pipe_ctx->ipp,
-+					pipe_ctx->opp,
-+					gamma, surface);
-+
-+			dc->hwss.set_plane_config(
-+				dc, pipe_ctx, &context->res_ctx);
-+		}
-+
-+	dc->hwss.update_plane_addrs(dc, &context->res_ctx);
-+
-+	/* Lower display clock if necessary */
-+	if (prev_disp_clk > context->bw_results.dispclk_khz) {
-+		dc->hwss.program_bw(dc, context);
-+		pplib_apply_display_requirements(dc, context,
-+						&context->pp_display_cfg);
-+	}
-+
-+	val_ctx_destruct(&dc->current_context);
-+	dc->current_context = *context;
-+	dm_free(dc->ctx, context);
-+	return true;
-+
-+unexpected_fail:
-+
-+	val_ctx_destruct(context);
-+
-+	dm_free(dc->ctx, context);
-+	return false;
-+}
-+
- uint8_t dc_get_current_target_count(const struct dc *dc)
- {
- 	return dc->current_context.target_count;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 66aae5f..bbcfbf5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -30,13 +30,6 @@
- #include "ipp.h"
- #include "timing_generator.h"
- 
--#define COEFF_RANGE	3
--#define REGAMMA_COEFF_A0	31308
--#define REGAMMA_COEFF_A1	12920
--#define REGAMMA_COEFF_A2	55
--#define REGAMMA_COEFF_A3	55
--#define REGAMMA_COEFF_GAMMA	2400
--
- struct target {
- 	struct core_target protected;
- 	int ref_count;
-@@ -136,229 +129,6 @@ target_alloc_fail:
- 	return NULL;
- }
- 
--/*
--void ProgramPixelDurationV(unsigned int pixelClockInKHz )
--{
--	fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
--	unsigned int pixDurationInPico = round(pixel_duration);
--
--	DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
--
--	arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
--	arb_control.bits.PIXEL_DURATION = pixDurationInPico;
--	WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
--
--	arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
--	arb_control.bits.PIXEL_DURATION = pixDurationInPico;
--	WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
--
--	WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
--	WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
--
--	WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
--	WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
--}
--*/
--static int8_t acquire_first_free_underlay(
--		struct resource_context *res_ctx,
--		struct core_stream *stream)
--{
--	if (!res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX].stream) {
--		struct dc_bios *dcb;
--		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX];
--
--		pipe_ctx->tg = res_ctx->pool.timing_generators[DCE110_UNDERLAY_IDX];
--		pipe_ctx->mi = res_ctx->pool.mis[DCE110_UNDERLAY_IDX];
--		/*pipe_ctx->ipp = res_ctx->pool.ipps[DCE110_UNDERLAY_IDX];*/
--		pipe_ctx->xfm = res_ctx->pool.transforms[DCE110_UNDERLAY_IDX];
--		pipe_ctx->opp = res_ctx->pool.opps[DCE110_UNDERLAY_IDX];
--		pipe_ctx->dis_clk = res_ctx->pool.display_clock;
--		pipe_ctx->pipe_idx = DCE110_UNDERLAY_IDX;
--
--		dcb = dal_adapter_service_get_bios_parser(
--						res_ctx->pool.adapter_srv);
--
--		stream->ctx->dc->hwss.enable_display_power_gating(
--			stream->ctx->dc->ctx,
--			DCE110_UNDERLAY_IDX,
--			dcb, PIPE_GATING_CONTROL_DISABLE);
--
--		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
--			dm_error("DC: failed to blank crtc!\n");
--			BREAK_TO_DEBUGGER();
--		}
--
--		if (!pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
--			BREAK_TO_DEBUGGER();
--		}
--
--		pipe_ctx->tg->funcs->set_blank_color(
--				pipe_ctx->tg,
--				COLOR_SPACE_YCBCR601);/* TODO unhardcode*/
--
--		pipe_ctx->stream = stream;
--		return DCE110_UNDERLAY_IDX;
--	}
--	return -1;
--}
--
--bool dc_commit_surfaces_to_target(
--		struct dc *dc,
--		struct dc_surface *new_surfaces[],
--		uint8_t new_surface_count,
--		struct dc_target *dc_target)
--
--{
--	int i, j;
--	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
--	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	struct dc_target_status *target_status = NULL;
--	struct validate_context *context;
--	int current_enabled_surface_count = 0;
--	int new_enabled_surface_count = 0;
--	bool is_mpo_turning_on = false;
--
--	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
--
--	val_ctx_copy_construct(&dc->current_context, context);
--
--	/* Cannot commit surface to a target that is not commited */
--	for (i = 0; i < context->target_count; i++)
--		if (target == context->targets[i])
--			break;
--
--	target_status = &context->target_status[i];
--
--	if (!dal_adapter_service_is_in_accelerated_mode(
--						dc->res_pool.adapter_srv)
--		|| i == context->target_count) {
--		BREAK_TO_DEBUGGER();
--		goto unexpected_fail;
--	}
--
--	for (i = 0; i < target_status->surface_count; i++)
--		if (target_status->surfaces[i]->visible)
--			current_enabled_surface_count++;
--
--	for (i = 0; i < new_surface_count; i++)
--		if (new_surfaces[i]->visible)
--			new_enabled_surface_count++;
--
--	/* TODO unhack mpo */
--	if (new_surface_count == 2 && target_status->surface_count < 2) {
--		acquire_first_free_underlay(&context->res_ctx,
--				DC_STREAM_TO_CORE(dc_target->streams[0]));
--		is_mpo_turning_on = true;
--	} else if (new_surface_count < 2 && target_status->surface_count == 2) {
--		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].stream = NULL;
--		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].surface = NULL;
--	}
--
--	dal_logger_write(dc->ctx->logger,
--				LOG_MAJOR_INTERFACE_TRACE,
--				LOG_MINOR_COMPONENT_DC,
--				"%s: commit %d surfaces to target 0x%x\n",
--				__func__,
--				new_surface_count,
--				dc_target);
--
--
--	if (!attach_surfaces_to_context(
--			new_surfaces, new_surface_count, dc_target, context)) {
--		BREAK_TO_DEBUGGER();
--		goto unexpected_fail;
--	}
--
--	for (i = 0; i < new_surface_count; i++)
--		for (j = 0; j < MAX_PIPES; j++) {
--			if (context->res_ctx.pipe_ctx[j].surface !=
--					DC_SURFACE_TO_CORE(new_surfaces[i]))
--				continue;
--
--			build_scaling_params(
--				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
--		}
--
--	if (dc->res_pool.funcs->validate_bandwidth(dc, context) != DC_OK) {
--		BREAK_TO_DEBUGGER();
--		goto unexpected_fail;
--	}
--
--	if (prev_disp_clk < context->bw_results.dispclk_khz ||
--		(is_mpo_turning_on &&
--			prev_disp_clk == context->bw_results.dispclk_khz)) {
--		dc->hwss.program_bw(dc, context);
--		pplib_apply_display_requirements(dc, context,
--						&context->pp_display_cfg);
--	}
--
--	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
--		dc_target_disable_memory_requests(dc_target);
--
--	for (i = 0; i < new_surface_count; i++)
--		for (j = 0; j < MAX_PIPES; j++) {
--			struct dc_surface *dc_surface = new_surfaces[i];
--			struct core_surface *surface =
--						DC_SURFACE_TO_CORE(dc_surface);
--			struct pipe_ctx *pipe_ctx =
--						&context->res_ctx.pipe_ctx[j];
--			struct core_gamma *gamma = NULL;
--
--			if (pipe_ctx->surface !=
--					DC_SURFACE_TO_CORE(new_surfaces[i]))
--				continue;
--
--			dal_logger_write(dc->ctx->logger,
--						LOG_MAJOR_INTERFACE_TRACE,
--						LOG_MINOR_COMPONENT_DC,
--						"Pipe:%d 0x%x: src: %d, %d, %d,"
--						" %d; dst: %d, %d, %d, %d;\n",
--						pipe_ctx->pipe_idx,
--						dc_surface,
--						dc_surface->src_rect.x,
--						dc_surface->src_rect.y,
--						dc_surface->src_rect.width,
--						dc_surface->src_rect.height,
--						dc_surface->dst_rect.x,
--						dc_surface->dst_rect.y,
--						dc_surface->dst_rect.width,
--						dc_surface->dst_rect.height);
--
--			if (surface->public.gamma_correction)
--				gamma = DC_GAMMA_TO_CORE(
--					surface->public.gamma_correction);
--
--			dc->hwss.set_gamma_correction(
--					pipe_ctx->ipp,
--					pipe_ctx->opp,
--					gamma, surface);
--
--			dc->hwss.set_plane_config(
--				dc, pipe_ctx, &context->res_ctx);
--		}
--
--	dc->hwss.update_plane_addrs(dc, &context->res_ctx);
--
--	/* Lower display clock if necessary */
--	if (prev_disp_clk > context->bw_results.dispclk_khz) {
--		dc->hwss.program_bw(dc, context);
--		pplib_apply_display_requirements(dc, context,
--						&context->pp_display_cfg);
--	}
--
--	val_ctx_destruct(&dc->current_context);
--	dc->current_context = *context;
--	dm_free(dc->ctx, context);
--	return true;
--
--unexpected_fail:
--
--	val_ctx_destruct(context);
--
--	dm_free(dc->ctx, context);
--	return false;
--}
--
- bool dc_target_is_connected_to_sink(
- 		const struct dc_target * dc_target,
- 		const struct dc_sink *dc_sink)
-@@ -372,52 +142,6 @@ bool dc_target_is_connected_to_sink(
- 	return false;
- }
- 
--void dc_target_enable_memory_requests(struct dc_target *dc_target)
--{
--	uint8_t i, j;
--	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	struct resource_context *res_ctx =
--		&target->ctx->dc->current_context.res_ctx;
--
--	for (i = 0; i < target->public.stream_count; i++) {
--		for (j = 0; j < MAX_PIPES; j++) {
--			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
--
--			if (res_ctx->pipe_ctx[j].stream !=
--				DC_STREAM_TO_CORE(target->public.streams[i]))
--				continue;
--
--			if (!tg->funcs->set_blank(tg, false)) {
--				dm_error("DC: failed to unblank crtc!\n");
--				BREAK_TO_DEBUGGER();
--			}
--		}
--	}
--}
--
--void dc_target_disable_memory_requests(struct dc_target *dc_target)
--{
--	uint8_t i, j;
--	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	struct resource_context *res_ctx =
--		&target->ctx->dc->current_context.res_ctx;
--
--	for (i = 0; i < target->public.stream_count; i++) {
--		for (j = 0; j < MAX_PIPES; j++) {
--			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
--
--			if (res_ctx->pipe_ctx[j].stream !=
--				DC_STREAM_TO_CORE(target->public.streams[i]))
--				continue;
--
--			if (!tg->funcs->set_blank(tg, true)) {
--				dm_error("DC: failed to blank crtc!\n");
--				BREAK_TO_DEBUGGER();
--			}
--		}
--	}
--}
--
- /**
-  * Update the cursor attributes and set cursor surface address
-  */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index fb0b9f6..1290f3f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -235,9 +235,6 @@ enum dc_irq_source dc_target_get_irq_src(
- 	const struct dc_target *dc_target,
- 	const enum irq_type irq_type);
- 
--void dc_target_enable_memory_requests(struct dc_target *target);
--void dc_target_disable_memory_requests(struct dc_target *target);
--
- /*
-  * Structure to store surface/target associations for validation
-  */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0849-drm-amd-dal-Get-rid-of-dal_types.h-in-dc.h.patch b/common/recipes-kernel/linux/files/0849-drm-amd-dal-Get-rid-of-dal_types.h-in-dc.h.patch
deleted file mode 100644
index 59e34bed..00000000
--- a/common/recipes-kernel/linux/files/0849-drm-amd-dal-Get-rid-of-dal_types.h-in-dc.h.patch
+++ /dev/null
@@ -1,358 +0,0 @@
-From 76bcf8ca5e27b996271b0ae5778ed6c1f60405e8 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Sat, 27 Feb 2016 11:05:55 -0500
-Subject: [PATCH 0849/1110] drm/amd/dal: Get rid of dal_types.h in dc.h
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   2 -
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  13 --
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  16 +++
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 107 +++++++++++++++++
- drivers/gpu/drm/amd/dal/include/dal_types.h        | 133 ---------------------
- 5 files changed, 123 insertions(+), 148 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 7c3a683..4bf4c5d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -58,8 +58,6 @@
- struct dal_override_parameters display_param = {
- 	.bool_param_enable_mask = 0,
- 	.bool_param_values = 0,
--	.int_param_values[DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS] = DAL_PARAM_INVALID_INT,
--	.int_param_values[DAL_PARAM_DRR_SUPPORT] = DAL_PARAM_INVALID_INT,
- };
- 
- /* Debug facilities */
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index f914a8c..0fd1050 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -396,17 +396,6 @@ case FEATURE_ ## feature: \
- 	} \
- 	break
- 
--#define check_int_feature(feature) \
--case FEATURE_ ## feature: \
--	if (param->int_param_values[DAL_PARAM_ ## feature] != \
--		DAL_PARAM_INVALID_INT) { \
--		*data = param->int_param_values[DAL_PARAM_ ## feature];\
--		ret = true;\
--		bool_feature = false;\
--		feature_name = "FEATURE_" #feature;\
--	} \
--	break
--
- /*
-  * override_default_parameters
-  *
-@@ -429,8 +418,6 @@ static bool override_default_parameters(
- 	}
- 
- 	switch (feature_entry_table[idx].feature_id) {
--	check_int_feature(MAX_COFUNC_NON_DP_DISPLAYS);
--	check_int_feature(DRR_SUPPORT);
- 	check_bool_feature(LIGHT_SLEEP);
- 	check_bool_feature(MAXIMIZE_STUTTER_MARKS);
- 	check_bool_feature(MAXIMIZE_URGENCY_WATERMARKS);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 1290f3f..ee5e8e7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -52,6 +52,22 @@ struct dc_caps {
- 
- void dc_get_caps(const struct dc *dc, struct dc_caps *caps);
- 
-+struct dal_init_data {
-+	struct hw_asic_id asic_id;
-+	struct view_port_alignment vp_alignment;
-+	struct bdf_info bdf_info;
-+	struct dal_override_parameters display_param;
-+	void *driver; /* ctx */
-+	void *cgs_device;
-+	uint8_t num_virtual_links;
-+	/*
-+	 * If 'vbios_override' not NULL, it will be called instead
-+	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
-+	 */
-+	struct dc_bios *vbios_override;
-+	enum dce_environment dce_environment;
-+};
-+
- struct dc *dc_create(const struct dal_init_data *init_params);
- void dc_destroy(struct dc **dc);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 6b87b1d..ac0f40d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -41,6 +41,10 @@ struct dc_link;
- struct dc_sink;
- struct dal;
- 
-+#if defined(BUILD_DAL_TEST)
-+struct test_driver_context;
-+#endif /* BUILD_DAL_TEST */
-+
- /********************************
-  * Environment definitions
-  ********************************/
-@@ -64,6 +68,109 @@ enum dce_environment {
- 
- /********************************/
- 
-+struct dc_context {
-+	struct dc *dc;
-+
-+#if defined(BUILD_DAL_TEST)
-+	struct test_driver_context *driver_context;
-+#else
-+	void *driver_context; /* e.g. amdgpu_device */
-+#endif
-+
-+	struct dal_logger *logger;
-+	void *cgs_device;
-+
-+	enum dce_environment dce_environment;
-+};
-+
-+/*
-+ * ASIC Runtime Flags
-+ */
-+struct dal_asic_runtime_flags {
-+	union {
-+		uint32_t raw;
-+		struct {
-+			uint32_t EMULATE_REPLUG_ON_CAP_CHANGE:1;
-+			uint32_t SUPPORT_XRBIAS:1;
-+			uint32_t SKIP_POWER_DOWN_ON_RESUME:1;
-+			uint32_t FULL_DETECT_ON_RESUME:1;
-+			uint32_t GSL_FRAMELOCK:1;
-+			uint32_t NO_LOW_BPP_MODES:1;
-+			uint32_t BLOCK_ON_INITIAL_DETECTION:1;
-+			uint32_t OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT:1;
-+			uint32_t DRIVER_CONTROLLED_BRIGHTNESS:1;
-+			uint32_t MODIFIABLE_FRAME_DURATION:1;
-+			uint32_t MIRACAST_SUPPORTED:1;
-+			uint32_t CONNECTED_STANDBY_SUPPORTED:1;
-+			uint32_t GNB_WAKEUP_SUPPORTED:1;
-+		} bits;
-+	} flags;
-+};
-+
-+struct hw_asic_id {
-+	uint32_t chip_id;
-+	uint32_t chip_family;
-+	uint32_t pci_revision_id;
-+	uint32_t hw_internal_rev;
-+	uint32_t vram_type;
-+	uint32_t vram_width;
-+	uint32_t feature_flags;
-+	struct dal_asic_runtime_flags runtime_flags;
-+	uint32_t fake_paths_num;
-+	void *atombios_base_address;
-+};
-+
-+/* this is pci information. BDF stands for BUS,DEVICE,FUNCTION*/
-+
-+struct bdf_info {
-+	uint16_t BUS_NUMBER:8;
-+	uint16_t DEVICE_NUMBER:5;
-+	uint16_t FUNCTION_NUMBER:3;
-+};
-+
-+/* array index for integer override parameters*/
-+enum int_param_array_index {
-+	DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0,
-+	DAL_PARAM_DRR_SUPPORT,
-+	DAL_INT_PARAM_MAX
-+};
-+
-+struct dal_override_parameters {
-+	uint32_t bool_param_enable_mask;
-+	uint32_t bool_param_values;
-+};
-+
-+/*
-+ * shift values for bool override parameter mask
-+ * bmask is for this struct,if we touch this feature
-+ * bval indicates every bit fields for this struct too,1 is enable this feature
-+ * amdgpu.disp_bval=1594, amdgpu.disp_bmask=1594 ,
-+ * finally will show log like this:
-+ * Overridden FEATURE_LIGHT_SLEEP is enabled now
-+ * Overridden FEATURE_USE_MAX_DISPLAY_CLK is enabled now
-+ * Overridden FEATURE_ENABLE_DFS_BYPASS is enabled now
-+ * Overridden FEATURE_POWER_GATING_PIPE_IN_TILE is enabled now
-+ * Overridden FEATURE_USE_PPLIB is enabled now
-+ * Overridden FEATURE_DISABLE_LPT_SUPPORT is enabled now
-+ * Overridden FEATURE_DUMMY_FBC_BACKEND is enabled now
-+ * */
-+enum bool_param_shift {
-+	DAL_PARAM_MAXIMIZE_STUTTER_MARKS = 0,
-+	DAL_PARAM_LIGHT_SLEEP,
-+	DAL_PARAM_MAXIMIZE_URGENCY_WATERMARKS,
-+	DAL_PARAM_USE_MAX_DISPLAY_CLK,
-+	DAL_PARAM_ENABLE_DFS_BYPASS,
-+	DAL_PARAM_POWER_GATING_PIPE_IN_TILE,
-+	DAL_PARAM_POWER_GATING_LB_PORTION,
-+	DAL_PARAM_PSR_ENABLE,
-+	DAL_PARAM_VARI_BRIGHT_ENABLE,
-+	DAL_PARAM_USE_PPLIB,
-+	DAL_PARAM_DISABLE_LPT_SUPPORT,
-+	DAL_PARAM_DUMMY_FBC_BACKEND,
-+	DAL_PARAM_ENABLE_GPU_SCALING,
-+	DAL_BOOL_PARAM_MAX
-+};
-+
- #define MAX_EDID_BUFFER_SIZE 512
- #define MAX_SURFACE_NUM 2
- #define NUM_PIXEL_FORMATS 10
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 8fdde70..eea3306 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -46,139 +46,6 @@ enum dce_version {
- 	DCE_VERSION_MAX
- };
- 
--/*
-- * ASIC Runtime Flags
-- */
--struct dal_asic_runtime_flags {
--	union {
--		uint32_t raw;
--		struct {
--			uint32_t EMULATE_REPLUG_ON_CAP_CHANGE:1;
--			uint32_t SUPPORT_XRBIAS:1;
--			uint32_t SKIP_POWER_DOWN_ON_RESUME:1;
--			uint32_t FULL_DETECT_ON_RESUME:1;
--			uint32_t GSL_FRAMELOCK:1;
--			uint32_t NO_LOW_BPP_MODES:1;
--			uint32_t BLOCK_ON_INITIAL_DETECTION:1;
--			uint32_t OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT:1;
--			uint32_t DRIVER_CONTROLLED_BRIGHTNESS:1;
--			uint32_t MODIFIABLE_FRAME_DURATION:1;
--			uint32_t MIRACAST_SUPPORTED:1;
--			uint32_t CONNECTED_STANDBY_SUPPORTED:1;
--			uint32_t GNB_WAKEUP_SUPPORTED:1;
--		} bits;
--	} flags;
--};
--
--struct hw_asic_id {
--	uint32_t chip_id;
--	uint32_t chip_family;
--	uint32_t pci_revision_id;
--	uint32_t hw_internal_rev;
--	uint32_t vram_type;
--	uint32_t vram_width;
--	uint32_t feature_flags;
--	struct dal_asic_runtime_flags runtime_flags;
--	uint32_t fake_paths_num;
--	void *atombios_base_address;
--};
--
--/* this is pci information. BDF stands for BUS,DEVICE,FUNCTION*/
--
--struct bdf_info {
--	uint16_t BUS_NUMBER:8;
--	uint16_t DEVICE_NUMBER:5;
--	uint16_t FUNCTION_NUMBER:3;
--};
--
--#define DAL_PARAM_INVALID_INT 0x80000000
--
--/* shift values for bool override parameter mask
-- * bmask is for this struct,if we touch this feature
-- * bval indicates every bit fields for this struct too,1 is enable this feature
-- * amdgpu.disp_bval=1594, amdgpu.disp_bmask=1594 ,
-- * finally will show log like this:
-- * Overridden FEATURE_LIGHT_SLEEP is enabled now
-- * Overridden FEATURE_USE_MAX_DISPLAY_CLK is enabled now
-- * Overridden FEATURE_ENABLE_DFS_BYPASS is enabled now
-- * Overridden FEATURE_POWER_GATING_PIPE_IN_TILE is enabled now
-- * Overridden FEATURE_USE_PPLIB is enabled now
-- * Overridden FEATURE_DISABLE_LPT_SUPPORT is enabled now
-- * Overridden FEATURE_DUMMY_FBC_BACKEND is enabled now */
--enum bool_param_shift {
--	DAL_PARAM_MAXIMIZE_STUTTER_MARKS = 0,
--	DAL_PARAM_LIGHT_SLEEP,
--	DAL_PARAM_MAXIMIZE_URGENCY_WATERMARKS,
--	DAL_PARAM_USE_MAX_DISPLAY_CLK,
--	DAL_PARAM_ENABLE_DFS_BYPASS,
--	DAL_PARAM_POWER_GATING_PIPE_IN_TILE,
--	DAL_PARAM_POWER_GATING_LB_PORTION,
--	DAL_PARAM_PSR_ENABLE,
--	DAL_PARAM_VARI_BRIGHT_ENABLE,
--	DAL_PARAM_USE_PPLIB,
--	DAL_PARAM_DISABLE_LPT_SUPPORT,
--	DAL_PARAM_DUMMY_FBC_BACKEND,
--	DAL_PARAM_ENABLE_GPU_SCALING,
--	DAL_BOOL_PARAM_MAX
--};
--
--/* array index for integer override parameters*/
--enum int_param_array_index {
--	DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0,
--	DAL_PARAM_DRR_SUPPORT,
--	DAL_INT_PARAM_MAX
--};
--
--struct dal_override_parameters {
--	uint32_t bool_param_enable_mask;
--	uint32_t bool_param_values;
--	uint32_t int_param_values[DAL_INT_PARAM_MAX];
--};
--
--
--struct dal_init_data {
--	struct hw_asic_id asic_id;
--	struct view_port_alignment vp_alignment;
--	struct bdf_info bdf_info;
--	struct dal_override_parameters display_param;
--	void *driver; /* ctx */
--	void *cgs_device;
--	uint8_t num_virtual_links;
--	/* If 'vbios_override' not NULL, it will be called instead
--	 * of the real VBIOS. Intended use is Diagnostics on FPGA. */
--	struct dc_bios *vbios_override;
--	enum dce_environment dce_environment;
--};
--
--struct dal_dc_init_data {
--	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
--	struct adapter_service *adapter_srv;
--};
--
--struct dal_dev_c_lut {
--	uint8_t red;
--	uint8_t green;
--	uint8_t blue;
--	uint8_t reserved;
--};
--
--struct dal_dev_gamma_lut {
--	uint16_t red;
--	uint16_t green;
--	uint16_t blue;
--};
--
--struct dc_context {
--	struct dc *dc;
--
--	void *driver_context; /* e.g. amdgpu_device */
--
--	struct dal_logger *logger;
--	void *cgs_device;
--
--	enum dce_environment dce_environment;
--};
--
- /* Wireless display structs */
- 
- union dal_remote_display_cea_mode_bitmap {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0850-drm-amd-dal-rename-struct-dc-to-struct-core_dc.patch b/common/recipes-kernel/linux/files/0850-drm-amd-dal-rename-struct-dc-to-struct-core_dc.patch
deleted file mode 100644
index cb37fab0..00000000
--- a/common/recipes-kernel/linux/files/0850-drm-amd-dal-rename-struct-dc-to-struct-core_dc.patch
+++ /dev/null
@@ -1,1379 +0,0 @@
-From 8bae2ee0014032f7ae99e70b0030f4e251a41d16 Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Sat, 27 Feb 2016 12:22:54 -0500
-Subject: [PATCH 0850/1110] drm/amd/dal: rename struct dc to struct core_dc
-
-Part 1 of 3 changes to refactor struct_dc, and dc_context
-
-1.) rename struct dc to struct core_dc <- This change
-2.) remove dc_context from core_dc, instead add driver_context
-3.) create struct dc which is returned by dc_create which contains dc_caps and links, refactor DM
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |  4 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h      |  2 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  2 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  6 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 73 +++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  4 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 10 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |  4 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  4 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    | 58 ++++++++---------
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  4 +-
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |  4 +-
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.h    |  4 +-
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 10 +--
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.h    |  4 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 34 +++++-----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h    |  4 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 10 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.h    |  4 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |  2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h  |  4 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 10 +--
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h  |  4 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |  2 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  8 +--
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      | 18 +++---
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          | 10 +--
- 28 files changed, 151 insertions(+), 154 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 4bf4c5d..6902861 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -162,7 +162,7 @@ static void dm_pflip_high_irq(void *interrupt_params)
- 	struct common_irq_params *irq_params = interrupt_params;
- 	struct amdgpu_device *adev = irq_params->adev;
- 	unsigned long flags;
--	const struct dc *dc = irq_params->adev->dm.dc;
-+	const struct core_dc *dc = irq_params->adev->dm.dc;
- 	const struct dc_target *dc_target =
- 			dc_get_target_on_irq_source(dc, irq_params->irq_src);
- 
-@@ -774,7 +774,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev)
- /* Register IRQ sources and initialize IRQ callbacks */
- static int dce110_register_irq_handlers(struct amdgpu_device *adev)
- {
--	struct dc *dc = adev->dm.dc;
-+	struct core_dc *dc = adev->dm.dc;
- 	struct common_irq_params *c_irq_params;
- 	struct dc_interrupt_params int_params = {0};
- 	int r;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 4a9b1c3..0da8530 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -74,7 +74,7 @@ struct irq_list_head {
- 
- struct amdgpu_display_manager {
- 	struct dal *dal;
--	struct dc *dc;
-+	struct core_dc *dc;
- 	void *cgs_device;
- 	/* lock to be used when DAL is called from SYNC IRQ context */
- 	spinlock_t dal_lock;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 2362003..a8b489f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -81,7 +81,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 	struct pci_dev *pdev = to_pci_dev(aux->dev);
- 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
- 	struct amdgpu_device *adev = drm_dev->dev_private;
--	struct dc *dc = adev->dm.dc;
-+	struct core_dc *dc = adev->dm.dc;
- 	bool res;
- 
- 	switch (msg->request) {
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 9fb4e51..f8c423a 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -624,7 +624,7 @@ static void calculate_stream_scaling_settings(
- }
- 
- static void dm_dc_surface_commit(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct drm_crtc *crtc,
- 		struct dm_connector_state *dm_state)
- {
-@@ -1877,7 +1877,7 @@ int amdgpu_dm_connector_init(
- {
- 	int res = 0;
- 	int connector_type;
--	struct dc *dc = dm->dc;
-+	struct core_dc *dc = dm->dc;
- 	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
- 	struct amdgpu_i2c_adapter *i2c;
- 
-@@ -2492,7 +2492,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 	struct dc_validation_set set[MAX_TARGET_NUM] = {{ 0 }};
- 	struct dc_target *new_targets[MAX_TARGET_NUM] = { 0 };
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct dc *dc = adev->dm.dc;
-+	struct core_dc *dc = adev->dm.dc;
- 	bool need_to_validate = false;
- 
- 	ret = drm_atomic_helper_check(dev, state);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 4ce2af2..69489f7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -59,7 +59,7 @@ struct dc_target_sync_report {
- /*******************************************************************************
-  * Private functions
-  ******************************************************************************/
--static void destroy_links(struct dc *dc)
-+static void destroy_links(struct core_dc *dc)
- {
- 	uint32_t i;
- 
-@@ -69,7 +69,7 @@ static void destroy_links(struct dc *dc)
- 	}
- }
- 
--static bool create_links(struct dc *dc, const struct dc_init_data *init_params)
-+static bool create_links(struct core_dc *dc, const struct dc_init_data *init_params)
- {
- 	int i;
- 	int connectors_num;
-@@ -165,7 +165,7 @@ failed_alloc:
- }
- 
- 
--static void init_hw(struct dc *dc)
-+static void init_hw(struct core_dc *dc)
- {
- 	int i;
- 	struct dc_bios *bp;
-@@ -257,7 +257,7 @@ static struct adapter_service *create_as(
- 	return as;
- }
- 
--static void bw_calcs_data_update_from_pplib(struct dc *dc)
-+static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
- {
- 	struct dm_pp_clock_levels clks = {0};
- 
-@@ -303,7 +303,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
- 		1000);
- }
- 
--static bool construct(struct dc *dc, const struct dal_init_data *init_params)
-+static bool construct(struct core_dc *dc, const struct dal_init_data *init_params)
- {
- 	struct dal_logger *logger;
- 	/* Tempory code
-@@ -389,7 +389,7 @@ ctx_fail:
- 	return false;
- }
- 
--static void destruct(struct dc *dc)
-+static void destruct(struct core_dc *dc)
- {
- 	val_ctx_destruct(&dc->current_context);
- 	destroy_links(dc);
-@@ -468,13 +468,13 @@ static int8_t acquire_first_free_underlay(
-  * Public functions
-  ******************************************************************************/
- 
--struct dc *dc_create(const struct dal_init_data *init_params)
-+struct core_dc *dc_create(const struct dal_init_data *init_params)
-  {
- 	struct dc_context ctx = {
- 		.driver_context = init_params->driver,
- 		.cgs_device = init_params->cgs_device
- 	};
--	struct dc *dc = dm_alloc(&ctx, sizeof(*dc));
-+	struct core_dc *dc = dm_alloc(&ctx, sizeof(*dc));
- 
- 	if (NULL == dc)
- 		goto alloc_fail;
-@@ -495,16 +495,16 @@ alloc_fail:
- 	return NULL;
- }
- 
--void dc_destroy(struct dc **dc)
-+void dc_destroy(struct core_dc **dc)
- {
--	struct dc_context ctx = *(*dc)->ctx;
-+	struct dc_context ctx = *((*dc)->ctx);
- 	destruct(*dc);
- 	dm_free(&ctx, *dc);
- 	*dc = NULL;
- }
- 
- bool dc_validate_resources(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count)
- {
-@@ -572,7 +572,7 @@ static void program_timing_sync(
- }
- 
- static bool targets_changed(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct dc_target *targets[],
- 		uint8_t target_count)
- {
-@@ -636,7 +636,7 @@ static void target_disable_memory_requests(struct dc_target *dc_target)
- }
- 
- bool dc_commit_targets(
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct dc_target *targets[],
- 	uint8_t target_count)
- {
-@@ -721,7 +721,7 @@ context_alloc_fail:
- }
- 
- bool dc_commit_surfaces_to_target(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct dc_surface *new_surfaces[],
- 		uint8_t new_surface_count,
- 		struct dc_target *dc_target)
-@@ -877,47 +877,47 @@ unexpected_fail:
- 	return false;
- }
- 
--uint8_t dc_get_current_target_count(const struct dc *dc)
-+uint8_t dc_get_current_target_count(const struct core_dc *dc)
- {
- 	return dc->current_context.target_count;
- }
- 
--struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i)
-+struct dc_target *dc_get_target_at_index(const struct core_dc *dc, uint8_t i)
- {
- 	if (i < dc->current_context.target_count)
- 		return &dc->current_context.targets[i]->public;
- 	return NULL;
- }
- 
--const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
-+const struct dc_link *dc_get_link_at_index(struct core_dc *dc, uint32_t link_index)
- {
- 	return &dc->links[link_index]->public;
- }
- 
- const struct graphics_object_id dc_get_link_id_at_index(
--	struct dc *dc, uint32_t link_index)
-+	struct core_dc *dc, uint32_t link_index)
- {
- 	return dc->links[link_index]->link_id;
- }
- 
- const struct ddc_service *dc_get_ddc_at_index(
--	struct dc *dc, uint32_t link_index)
-+	struct core_dc *dc, uint32_t link_index)
- {
- 	return dc->links[link_index]->ddc;
- }
- 
- const enum dc_irq_source dc_get_hpd_irq_source_at_index(
--	struct dc *dc, uint32_t link_index)
-+	struct core_dc *dc, uint32_t link_index)
- {
- 	return dc->links[link_index]->public.irq_source_hpd;
- }
- 
--const struct audio **dc_get_audios(struct dc *dc)
-+const struct audio **dc_get_audios(struct core_dc *dc)
- {
- 	return (const struct audio **)dc->res_pool.audios;
- }
- 
--void dc_get_caps(const struct dc *dc, struct dc_caps *caps)
-+void dc_get_caps(const struct core_dc *dc, struct dc_caps *caps)
- {
- 	caps->max_targets = dc->res_pool.pipe_count;
- 	caps->max_links = dc->link_count;
-@@ -925,7 +925,7 @@ void dc_get_caps(const struct dc *dc, struct dc_caps *caps)
- }
- 
- void dc_flip_surface_addrs(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		const struct dc_surface *const surfaces[],
- 		struct dc_flip_addrs flip_addrs[],
- 		uint32_t count)
-@@ -944,7 +944,7 @@ void dc_flip_surface_addrs(
- }
- 
- enum dc_irq_source dc_interrupt_to_irq_source(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t src_id,
- 		uint32_t ext_id)
- {
-@@ -952,18 +952,18 @@ enum dc_irq_source dc_interrupt_to_irq_source(
- }
- 
- 
--void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
-+void dc_interrupt_set(const struct core_dc *dc, enum dc_irq_source src, bool enable)
- {
- 	dal_irq_service_set(dc->res_pool.irqs, src, enable);
- }
- 
--void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
-+void dc_interrupt_ack(struct core_dc *dc, enum dc_irq_source src)
- {
- 	dal_irq_service_ack(dc->res_pool.irqs, src);
- }
- 
- const struct dc_target *dc_get_target_on_irq_source(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		enum dc_irq_source src)
- {
- 	uint8_t i, j;
-@@ -1011,7 +1011,7 @@ const struct dc_target *dc_get_target_on_irq_source(
- }
- 
- void dc_set_power_state(
--	struct dc *dc,
-+	struct core_dc *dc,
- 	enum dc_acpi_cm_power_state power_state,
- 	enum dc_video_power_state video_power_state)
- {
-@@ -1032,7 +1032,7 @@ void dc_set_power_state(
- 
- }
- 
--void dc_resume(const struct dc *dc)
-+void dc_resume(const struct core_dc *dc)
- {
- 	uint32_t i;
- 
-@@ -1041,14 +1041,13 @@ void dc_resume(const struct dc *dc)
- }
- 
- bool dc_read_dpcd(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		uint8_t *data,
- 		uint32_t size)
- {
--	struct core_link *link =
--			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
-+	struct core_link *link = dc->links[link_index];
- 
- 	enum ddc_result r = dal_ddc_service_read_dpcd_data(
- 			link->ddc,
-@@ -1059,14 +1058,13 @@ bool dc_read_dpcd(
- }
- 
- bool dc_write_dpcd(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		const uint8_t *data,
- 		uint32_t size)
- {
--	struct core_link *link =
--			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
-+	struct core_link *link = dc->links[link_index];
- 
- 	enum ddc_result r = dal_ddc_service_write_dpcd_data(
- 			link->ddc,
-@@ -1077,12 +1075,11 @@ bool dc_write_dpcd(
- }
- 
- bool dc_submit_i2c(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t link_index,
- 		struct i2c_command *cmd)
- {
--	struct core_link *link =
--			DC_LINK_TO_LINK(dc_get_link_at_index(dc, link_index));
-+	struct core_link *link = dc->links[link_index];
- 	struct ddc_service *ddc = link->ddc;
- 
- 	return dal_i2caux_submit_i2c_command(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-index 133b174..61bb67a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -37,7 +37,7 @@
- 
- bool dc_construct_hw_sequencer(
- 				struct adapter_service *adapter_serv,
--				struct dc *dc)
-+				struct core_dc *dc)
- {
- 	enum dce_version dce_ver = dal_adapter_service_get_dce_version(adapter_serv);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 88a4eb9..36b1661 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1617,7 +1617,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
- 
- void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- {
--	struct dc *dc = pipe_ctx->stream->ctx->dc;
-+    struct core_dc *dc = pipe_ctx->stream->ctx->dc;
- 
- 	if (DC_OK != enable_link(pipe_ctx)) {
- 			BREAK_TO_DEBUGGER();
-@@ -1634,7 +1634,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- 
- void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
- {
--	struct dc *dc = pipe_ctx->stream->ctx->dc;
-+	struct core_dc *dc = pipe_ctx->stream->ctx->dc;
- 
- 	pipe_ctx->stream->status.link = NULL;
- 	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 5e32289..013612a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -43,7 +43,7 @@
- #endif
- 
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
--				struct dc *dc,
-+				struct core_dc *dc,
- 				uint8_t num_virtual_links)
- {
- 	enum dce_version dce_ver = dal_adapter_service_get_dce_version(adapter_serv);
-@@ -367,7 +367,7 @@ void build_scaling_params(
- }
- 
- void build_scaling_params_for_context(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context)
- {
- 	uint8_t i;
-@@ -532,13 +532,13 @@ static void fill_display_configs(
- }
- 
- void pplib_apply_safe_state(
--	const struct dc *dc)
-+	const struct core_dc *dc)
- {
- 	dm_pp_apply_safe_state(dc->ctx);
- }
- 
- void pplib_apply_display_requirements(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	const struct validate_context *context,
- 	struct dm_pp_display_configuration *pp_display_cfg)
- {
-@@ -737,7 +737,7 @@ static void set_stream_signal(struct pipe_ctx *pipe_ctx)
- }
- 
- enum dc_status map_resources(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	uint8_t i, j, k;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 3878a61..7f6f1c3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -80,7 +80,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 	/*register_flip_interrupt(surface);*/
- }
- 
--struct dc_surface *dc_create_surface(const struct dc *dc)
-+struct dc_surface *dc_create_surface(const struct core_dc *dc)
- {
- 	struct surface *surface = dm_alloc(dc->ctx, sizeof(*surface));
- 
-@@ -148,7 +148,7 @@ void dc_gamma_release(const struct dc_gamma *dc_gamma)
- }
- 
- 
--struct dc_gamma *dc_create_gamma(const struct dc *dc)
-+struct dc_gamma *dc_create_gamma(const struct core_dc *dc)
- {
- 	struct gamma *gamma = dm_alloc(dc->ctx, sizeof(*gamma));
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index bbcfbf5..e1fce1c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -92,7 +92,7 @@ const struct dc_target_status *dc_target_get_status(
- {
- 	uint8_t i;
- 	struct core_target* target = DC_TARGET_TO_CORE(dc_target);
--	struct dc *dc = target->ctx->dc;
-+    struct core_dc *dc = target->ctx->dc;
- 
- 	for (i = 0; i < dc->current_context.target_count; i++)
- 		if (target == dc->current_context.targets[i])
-@@ -254,7 +254,7 @@ uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- }
- 
- enum dc_irq_source dc_target_get_irq_src(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	const struct dc_target *dc_target,
- 	const enum irq_type irq_type)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index ee5e8e7..68a63cf 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -50,7 +50,7 @@ struct dc_caps {
-     uint32_t max_audios;
- };
- 
--void dc_get_caps(const struct dc *dc, struct dc_caps *caps);
-+void dc_get_caps(const struct core_dc *dc, struct dc_caps *caps);
- 
- struct dal_init_data {
- 	struct hw_asic_id asic_id;
-@@ -68,8 +68,8 @@ struct dal_init_data {
- 	enum dce_environment dce_environment;
- };
- 
--struct dc *dc_create(const struct dal_init_data *init_params);
--void dc_destroy(struct dc **dc);
-+struct core_dc *dc_create(const struct dal_init_data *init_params);
-+void dc_destroy(struct core_dc **dc);
- 
- /*******************************************************************************
-  * Surface Interfaces
-@@ -146,7 +146,7 @@ struct dc_surface_status {
- /*
-  * Create a new surface with default parameters;
-  */
--struct dc_surface *dc_create_surface(const struct dc *dc);
-+struct dc_surface *dc_create_surface(const struct core_dc *dc);
- const struct dc_surface_status* dc_surface_get_status(
- 						struct dc_surface *dc_surface);
- 
-@@ -154,7 +154,7 @@ void dc_surface_retain(const struct dc_surface *dc_surface);
- void dc_surface_release(const struct dc_surface *dc_surface);
- 
- void dc_gamma_release(const struct dc_gamma *dc_gamma);
--struct dc_gamma *dc_create_gamma(const struct dc *dc);
-+struct dc_gamma *dc_create_gamma(const struct core_dc *dc);
- 
- /*
-  * This structure holds a surface address.  There could be multiple addresses
-@@ -175,7 +175,7 @@ struct dc_flip_addrs {
-  *   Surface addresses and flip attributes are programmed.
-  *   Surface flip occur at next configured time (h_sync or v_sync flip)
-  */
--void dc_flip_surface_addrs(struct dc* dc,
-+void dc_flip_surface_addrs(struct core_dc *dc,
- 		const struct dc_surface *const surfaces[],
- 		struct dc_flip_addrs flip_addrs[],
- 		uint32_t count);
-@@ -191,7 +191,7 @@ void dc_flip_surface_addrs(struct dc* dc,
-  *   This does not trigger a flip.  No surface address is programmed.
-  */
- bool dc_commit_surfaces_to_target(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct dc_surface *dc_surfaces[],
- 		uint8_t surface_count,
- 		struct dc_target *dc_target);
-@@ -236,8 +236,8 @@ void dc_target_log(
- 	enum log_major log_major,
- 	enum log_minor log_minor);
- 
--uint8_t dc_get_current_target_count(const struct dc *dc);
--struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i);
-+uint8_t dc_get_current_target_count(const struct core_dc *dc);
-+struct dc_target *dc_get_target_at_index(const struct core_dc *dc, uint8_t i);
- 
- bool dc_target_is_connected_to_sink(
- 		const struct dc_target *dc_target,
-@@ -247,7 +247,7 @@ uint8_t dc_target_get_controller_id(const struct dc_target *dc_target);
- 
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
- enum dc_irq_source dc_target_get_irq_src(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	const struct dc_target *dc_target,
- 	const enum irq_type irq_type);
- 
-@@ -267,7 +267,7 @@ struct dc_validation_set {
-  *   No hardware is programmed for call.  Only validation is done.
-  */
- bool dc_validate_resources(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count);
- 
-@@ -280,7 +280,7 @@ bool dc_validate_resources(
-  *   New targets are enabled with blank stream; no memory read.
-  */
- bool dc_commit_targets(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct dc_target *targets[],
- 		uint8_t target_count);
- 
-@@ -361,11 +361,11 @@ struct dc_link {
-  * boot time.  They cannot be created or destroyed.
-  * Use dc_get_caps() to get number of links.
-  */
--const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
-+const struct dc_link *dc_get_link_at_index(struct core_dc *dc, uint32_t link_index);
- 
- /* Return id of physical connector represented by a dc_link at link_index.*/
- const struct graphics_object_id dc_get_link_id_at_index(
--		struct dc *dc, uint32_t link_index);
-+		struct core_dc *dc, uint32_t link_index);
- 
- /* Set backlight level of an embedded panel (eDP, LVDS). */
- bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level);
-@@ -411,7 +411,7 @@ struct dc_sink {
- void dc_sink_retain(const struct dc_sink *sink);
- void dc_sink_release(const struct dc_sink *sink);
- 
--const struct audio **dc_get_audios(struct dc *dc);
-+const struct audio **dc_get_audios(struct core_dc *dc);
- 
- struct dc_sink_init_data {
- 	enum signal_type sink_signal;
-@@ -445,7 +445,7 @@ struct dc_cursor {
-  * Create a new cursor with default values for a given target.
-  */
- struct dc_cursor *dc_create_cursor_for_target(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct dc_target *dc_target);
- 
- /**
-@@ -457,7 +457,7 @@ struct dc_cursor *dc_create_cursor_for_target(
-  *   Cursor position is unmodified.
-  */
- bool dc_commit_cursor(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct dc_cursor *cursor);
- 
- /*
-@@ -467,7 +467,7 @@ bool dc_commit_cursor(
-  *   Cursor position will be programmed as well as enable/disable bit.
-  */
- bool dc_set_cursor_position(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct dc_cursor *cursor,
- 		struct dc_cursor_position *pos);
- 
-@@ -477,15 +477,15 @@ bool dc_set_cursor_position(
-  * Interrupt interfaces
-  ******************************************************************************/
- enum dc_irq_source dc_interrupt_to_irq_source(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t src_id,
- 		uint32_t ext_id);
--void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
--void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
-+void dc_interrupt_set(const struct core_dc *dc, enum dc_irq_source src, bool enable);
-+void dc_interrupt_ack(struct core_dc *dc, enum dc_irq_source src);
- const enum dc_irq_source dc_get_hpd_irq_source_at_index(
--		struct dc *dc, uint32_t link_index);
-+		struct core_dc *dc, uint32_t link_index);
- const struct dc_target *dc_get_target_on_irq_source(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		enum dc_irq_source src);
- 
- 
-@@ -494,38 +494,38 @@ const struct dc_target *dc_get_target_on_irq_source(
-  ******************************************************************************/
- 
- void dc_set_power_state(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		enum dc_acpi_cm_power_state power_state,
- 		enum dc_video_power_state video_power_state);
--void dc_resume(const struct dc *dc);
-+void dc_resume(const struct core_dc *dc);
- 
- /*******************************************************************************
-  * DDC Interfaces
-  ******************************************************************************/
- 
- const struct ddc_service *dc_get_ddc_at_index(
--		struct dc *dc, uint32_t link_index);
-+		struct core_dc *dc, uint32_t link_index);
- 
- /*
-  * DPCD access interfaces
-  */
- 
- bool dc_read_dpcd(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		uint8_t *data,
- 		uint32_t size);
- 
- bool dc_write_dpcd(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		const uint8_t *data,
- 	uint32_t size);
- 
- bool dc_submit_i2c(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		uint32_t link_index,
- 		struct i2c_command *cmd);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index ac0f40d..f764d37 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -33,7 +33,7 @@
- #include "signal_types.h"
- 
- /* forward declarations */
--struct dc;
-+struct core_dc;
- struct dc_surface;
- struct dc_target;
- struct dc_stream;
-@@ -69,7 +69,7 @@ enum dce_environment {
- /********************************/
- 
- struct dc_context {
--	struct dc *dc;
-+	struct core_dc *dc;
- 
- #if defined(BUILD_DAL_TEST)
- 	struct test_driver_context *driver_context;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index a1dbac4..a1c1d1c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -336,14 +336,14 @@ static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool ena
- }
- 
- static void set_displaymarks(
--		const struct dc *dc, struct validate_context *context)
-+		const struct core_dc *dc, struct validate_context *context)
- {
- 	/* Do nothing until we have proper bandwitdth calcs */
- }
- 
- /**************************************************************************/
- 
--bool dce100_hw_sequencer_construct(struct dc *dc)
-+bool dce100_hw_sequencer_construct(struct core_dc *dc)
- {
- 	dce110_hw_sequencer_construct(dc);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-index 0ce637e..cf497ea 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
-@@ -28,9 +28,9 @@
- 
- #include "core_types.h"
- 
--struct dc;
-+struct core_dc;
- 
--bool dce100_hw_sequencer_construct(struct dc *dc);
-+bool dce100_hw_sequencer_construct(struct core_dc *dc);
- 
- #endif /* __DC_HWSS_DCE100_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index a8c8f99..bc9fd02 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -729,7 +729,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- }
- 
- static enum dc_status validate_mapped_resource(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	enum dc_status status = DC_OK;
-@@ -790,7 +790,7 @@ static enum dc_status validate_mapped_resource(
- }
- 
- enum dc_status dce100_validate_bandwidth(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context)
- {
- 	/* TODO implement when needed but for now hardcode max value*/
-@@ -818,7 +818,7 @@ static void set_target_unchanged(
- }
- 
- static enum dc_status map_clock_resources(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	uint8_t i, j, k;
-@@ -877,7 +877,7 @@ static enum dc_status map_clock_resources(
- }
- 
- enum dc_status dce100_validate_with_context(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count,
- 		struct validate_context *context)
-@@ -948,7 +948,7 @@ static struct resource_funcs dce100_res_pool_funcs = {
- bool dce100_construct_resource_pool(
- 	struct adapter_service *as,
- 	uint8_t num_virtual_links,
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct resource_pool *pool)
- {
- 	unsigned int i;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-index a70bfee..65cd170 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-@@ -9,7 +9,7 @@
- #define DCE100_RESOURCE_H_
- 
- struct adapter_service;
--struct dc;
-+struct core_dc;
- struct resource_pool;
- struct dc_validation_set;
- 
-@@ -17,7 +17,7 @@ struct dc_validation_set;
- bool dce100_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct resource_pool *pool);
- 
- void dce100_destruct_resource_pool(struct resource_pool *pool);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index a93cdbb..68dc378 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -778,7 +778,7 @@ static enum dc_color_space get_output_color_space(
- static enum dc_status apply_single_controller_ctx_to_hw(
- 		struct pipe_ctx *pipe_ctx,
- 		struct validate_context *context,
--		struct dc *dc)
-+		struct core_dc *dc)
- {
- 	struct core_stream *stream = pipe_ctx->stream;
- 	struct pipe_ctx *old_pipe_ctx =
-@@ -908,7 +908,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 
- /******************************************************************************/
- 
--static void power_down_encoders(struct dc *dc)
-+static void power_down_encoders(struct core_dc *dc)
- {
- 	int i;
- 
-@@ -918,7 +918,7 @@ static void power_down_encoders(struct dc *dc)
- 	}
- }
- 
--static void power_down_controllers(struct dc *dc)
-+static void power_down_controllers(struct core_dc *dc)
- {
- 	int i;
- 
-@@ -928,7 +928,7 @@ static void power_down_controllers(struct dc *dc)
- 	}
- }
- 
--static void power_down_clock_sources(struct dc *dc)
-+static void power_down_clock_sources(struct core_dc *dc)
- {
- 	int i;
- 
-@@ -939,7 +939,7 @@ static void power_down_clock_sources(struct dc *dc)
- 	}
- }
- 
--static void power_down_all_hw_blocks(struct dc *dc)
-+static void power_down_all_hw_blocks(struct core_dc *dc)
- {
- 	power_down_encoders(dc);
- 
-@@ -949,7 +949,7 @@ static void power_down_all_hw_blocks(struct dc *dc)
- }
- 
- static void disable_vga_and_power_gate_all_controllers(
--		struct dc *dc)
-+		struct core_dc *dc)
- {
- 	int i;
- 	struct timing_generator *tg;
-@@ -981,7 +981,7 @@ static void disable_vga_and_power_gate_all_controllers(
-  *  3. Enable power gating for controller
-  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
-  */
--static void enable_accelerated_mode(struct dc *dc)
-+static void enable_accelerated_mode(struct core_dc *dc)
- {
- 	struct dc_bios *dcb;
- 
-@@ -1149,7 +1149,7 @@ static uint32_t compute_pstate_blackout_duration(
- }
- 
- static void set_displaymarks(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context)
- {
- 	uint8_t i, num_pipes;
-@@ -1194,7 +1194,7 @@ static void set_safe_displaymarks(struct resource_context *res_ctx)
- 	}
- }
- 
--static void program_bw(struct dc *dc, struct validate_context *context)
-+static void program_bw(struct core_dc *dc, struct validate_context *context)
- {
- 	set_safe_displaymarks(&context->res_ctx);
- 	/*TODO: when pplib works*/
-@@ -1205,7 +1205,7 @@ static void program_bw(struct dc *dc, struct validate_context *context)
- }
- 
- static void switch_dp_clock_sources(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct resource_context *res_ctx)
- {
- 	uint8_t i;
-@@ -1238,7 +1238,7 @@ static void switch_dp_clock_sources(
- 
- /*TODO: const validate_context*/
- static enum dc_status apply_ctx_to_hw(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	enum dc_status status;
-@@ -1342,7 +1342,7 @@ static void program_scaler(const struct pipe_ctx *pipe_ctx)
-  * The Back End was already programmed by Set Mode.
-  */
- static void set_plane_config(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct pipe_ctx *pipe_ctx,
- 	struct resource_context *res_ctx)
- {
-@@ -1404,7 +1404,7 @@ static void set_plane_config(
- 			surface->public.rotation);
- }
- 
--static void update_plane_addrs(struct dc *dc, struct resource_context *res_ctx)
-+static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_ctx)
- {
- 	int j;
- 
-@@ -1448,7 +1448,7 @@ static void update_plane_addrs(struct dc *dc, struct resource_context *res_ctx)
- }
- 
- static void reset_single_pipe_hw_ctx(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct pipe_ctx *pipe_ctx,
- 		struct validate_context *context)
- {
-@@ -1484,7 +1484,7 @@ static void reset_single_pipe_hw_ctx(
- }
- 
- static void reset_hw_ctx(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct validate_context *new_context)
- {
- 	uint8_t i;
-@@ -1501,7 +1501,7 @@ static void reset_hw_ctx(
- 	}
- }
- 
--static void power_down(struct dc *dc)
-+static void power_down(struct core_dc *dc)
- {
- 	power_down_all_hw_blocks(dc);
- 	disable_vga_and_power_gate_all_controllers(dc);
-@@ -1619,7 +1619,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.set_displaymarks = set_displaymarks,
- };
- 
--bool dce110_hw_sequencer_construct(struct dc *dc)
-+bool dce110_hw_sequencer_construct(struct core_dc *dc)
- {
- 	dc->hwss = dce110_funcs;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-index eafa345..ba4b81b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
-@@ -29,9 +29,9 @@
- #include "core_types.h"
- 
- #define GAMMA_HW_POINTS_NUM 256
--struct dc;
-+struct core_dc;
- 
--bool dce110_hw_sequencer_construct(struct dc *dc);
-+bool dce110_hw_sequencer_construct(struct core_dc *dc);
- 
- #endif /* __DC_HWSS_DCE110_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index c079bb7..cdd1f94 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -686,7 +686,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx)
- }
- 
- static enum dc_status validate_mapped_resource(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	enum dc_status status = DC_OK;
-@@ -746,7 +746,7 @@ static enum dc_status validate_mapped_resource(
- }
- 
- enum dc_status dce110_validate_bandwidth(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context)
- {
- 	uint8_t i;
-@@ -937,7 +937,7 @@ static void set_target_unchanged(
- }
- 
- static enum dc_status map_clock_resources(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	uint8_t i, j, k;
-@@ -989,7 +989,7 @@ static enum dc_status map_clock_resources(
- }
- 
- enum dc_status dce110_validate_with_context(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count,
- 		struct validate_context *context)
-@@ -1083,7 +1083,7 @@ static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
- bool dce110_construct_resource_pool(
- 	struct adapter_service *as,
- 	uint8_t num_virtual_links,
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct resource_pool *pool)
- {
- 	unsigned int i;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-index 5d60df2..3aeb1e5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-@@ -29,13 +29,13 @@
- #include "core_types.h"
- 
- struct adapter_service;
--struct dc;
-+struct core_dc;
- struct resource_pool;
- 
- bool dce110_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct resource_pool *pool);
- 
- void dce110_destruct_resource_pool(struct resource_pool *pool);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-index 9f3201f..1502829 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -293,7 +293,7 @@ static bool dce80_enable_display_power_gating(
- 		return false;
- }
- 
--bool dce80_hw_sequencer_construct(struct dc *dc)
-+bool dce80_hw_sequencer_construct(struct core_dc *dc)
- {
- 	dce110_hw_sequencer_construct(dc);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h
-index 9d6dd05..7cc203f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.h
-@@ -28,9 +28,9 @@
- 
- #include "core_types.h"
- 
--struct dc;
-+struct core_dc;
- 
--bool dce80_hw_sequencer_construct(struct dc *dc);
-+bool dce80_hw_sequencer_construct(struct core_dc *dc);
- 
- #endif /* __DC_HWSS_DCE80_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index cf51a44..be8bba1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -686,7 +686,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- }
- 
- static enum dc_status validate_mapped_resource(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	enum dc_status status = DC_OK;
-@@ -743,7 +743,7 @@ static enum dc_status validate_mapped_resource(
- }
- 
- enum dc_status dce80_validate_bandwidth(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context)
- {
- 	uint8_t i;
-@@ -934,7 +934,7 @@ static void set_target_unchanged(
- }
- 
- static enum dc_status map_clock_resources(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		struct validate_context *context)
- {
- 	uint8_t i, j, k;
-@@ -986,7 +986,7 @@ static enum dc_status map_clock_resources(
- }
- 
- enum dc_status dce80_validate_with_context(
--		const struct dc *dc,
-+		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count,
- 		struct validate_context *context)
-@@ -1057,7 +1057,7 @@ static struct resource_funcs dce80_res_pool_funcs = {
- bool dce80_construct_resource_pool(
- 	struct adapter_service *as,
- 	uint8_t num_virtual_links,
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct resource_pool *pool)
- {
- 	unsigned int i;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
-index 3d0f8fe..ef3c819 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
-@@ -29,13 +29,13 @@
- #include "core_types.h"
- 
- struct adapter_service;
--struct dc;
-+struct core_dc;
- struct resource_pool;
- 
- bool dce80_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
--	struct dc *dc,
-+	struct core_dc *dc,
- 	struct resource_pool *pool);
- 
- #endif /* __DC_RESOURCE_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index 4d4fd0c..6d20575 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -11,7 +11,7 @@
- #include "core_types.h"
- #include "hw_sequencer.h"
- 
--struct dc {
-+struct core_dc {
- 	struct dc_context *ctx;
- 
- 	uint8_t link_count;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index a5444cb..4b9ce6a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -122,7 +122,7 @@ struct core_sink {
- #define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public)
- 
- struct link_init_data {
--	const struct dc *dc;
-+	const struct core_dc *dc;
- 	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
- 	uint32_t connector_index; /* this will be mapped to the HPD pins */
- 	uint32_t link_index; /* this is mapped to DAL display_index
-@@ -191,7 +191,7 @@ struct link_mst_stream_allocation_table {
- 
- struct core_link {
- 	struct dc_link public;
--	const struct dc *dc;
-+	const struct core_dc *dc;
- 
- 	struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/
- 
-@@ -242,13 +242,13 @@ struct resource_funcs {
- 			const struct encoder_init_data *init);
- 	void (*link_enc_destroy)(struct link_encoder **enc);
- 	enum dc_status (*validate_with_context)(
--					const struct dc *dc,
-+					const struct core_dc *dc,
- 					const struct dc_validation_set set[],
- 					uint8_t set_count,
- 					struct validate_context *context);
- 
- 	enum dc_status (*validate_bandwidth)(
--					const struct dc *dc,
-+					const struct core_dc *dc,
- 					struct validate_context *context);
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 014e83f..2571691 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -39,17 +39,17 @@ enum pipe_gating_control {
- struct hw_sequencer_funcs {
- 
- 	enum dc_status (*apply_ctx_to_hw)(
--			struct dc *dc, struct validate_context *context);
-+			struct core_dc *dc, struct validate_context *context);
- 
--	void (*reset_hw_ctx)(struct dc *dc, struct validate_context *context);
-+	void (*reset_hw_ctx)(struct core_dc *dc, struct validate_context *context);
- 
- 	void (*set_plane_config)(
--			const struct dc *dc,
-+			const struct core_dc *dc,
- 			struct pipe_ctx *pipe_ctx,
- 			struct resource_context *res_ctx);
- 
- 	void (*update_plane_addrs)(
--		struct dc *dc,
-+		struct core_dc *dc,
- 		struct resource_context *res_ctx);
- 
- 	bool (*set_gamma_correction)(
-@@ -58,9 +58,9 @@ struct hw_sequencer_funcs {
- 				const struct core_gamma *ramp,
- 				const struct core_surface *surface);
- 
--	void (*power_down)(struct dc *dc);
-+	void (*power_down)(struct core_dc *dc);
- 
--	void (*enable_accelerated_mode)(struct dc *dc);
-+	void (*enable_accelerated_mode)(struct core_dc *dc);
- 
- 	void (*enable_timing_synchronization)(
- 					struct dc_context *dc_ctx,
-@@ -87,7 +87,7 @@ struct hw_sequencer_funcs {
- 					struct dc_bios *dcb,
- 					enum pipe_gating_control power_gating);
- 
--	void (*program_bw)(struct dc *dc, struct validate_context *context);
-+	void (*program_bw)(struct core_dc *dc, struct validate_context *context);
- 
- 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
- 
-@@ -108,7 +108,7 @@ struct hw_sequencer_funcs {
- 				uint32_t mode);
- 
- 	void (*set_displaymarks)(
--				const struct dc *dc,
-+				const struct core_dc *dc,
- 				struct validate_context *context);
- 
- 	void (*set_display_clock)(struct validate_context *context);
-@@ -116,7 +116,7 @@ struct hw_sequencer_funcs {
- 
- bool dc_construct_hw_sequencer(
- 				struct adapter_service *adapter_serv,
--				struct dc *dc);
-+				struct core_dc *dc);
- 
- 
- #endif /* __DC_HW_SEQUENCER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 717bf13..e6a386c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -34,7 +34,7 @@
- #define DCE110_UNDERLAY_IDX 3
- 
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
--				struct dc *dc,
-+				struct core_dc *dc,
- 				uint8_t num_virtual_links);
- 
- void build_scaling_params(
-@@ -42,7 +42,7 @@ void build_scaling_params(
- 	struct pipe_ctx *pipe_ctx);
- 
- void build_scaling_params_for_context(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context);
- 
- void unreference_clock_source(
-@@ -67,17 +67,17 @@ bool attach_surfaces_to_context(
- 		struct dc_target *dc_target,
- 		struct validate_context *context);
- 
--void pplib_apply_safe_state(const struct dc *dc);
-+void pplib_apply_safe_state(const struct core_dc *dc);
- 
- void pplib_apply_display_requirements(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	const struct validate_context *context,
- 	struct dm_pp_display_configuration *pp_display_cfg);
- 
- void build_info_frame(struct pipe_ctx *pipe_ctx);
- 
- enum dc_status map_resources(
--	const struct dc *dc,
-+	const struct core_dc *dc,
- 	struct validate_context *context);
- 
- void val_ctx_destruct(struct validate_context *context);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0851-drm-amd-dal-move-virtual-hardware-header-files-to-in.patch b/common/recipes-kernel/linux/files/0851-drm-amd-dal-move-virtual-hardware-header-files-to-in.patch
deleted file mode 100644
index b76743e6..00000000
--- a/common/recipes-kernel/linux/files/0851-drm-amd-dal-move-virtual-hardware-header-files-to-in.patch
+++ /dev/null
@@ -1,2777 +0,0 @@
-From a95e1ffaafa9040ac1d5f9187073f2b816b5b2a7 Mon Sep 17 00:00:00 2001
-From: Tony Cheng <Tony.Cheng@amd.com>
-Date: Sat, 27 Feb 2016 11:43:43 -0500
-Subject: [PATCH 0851/1110] drm/amd/dal: move virtual hardware header files to
- inc/hw
-
-Signed-off-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/Makefile                   |   1 +
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h   |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h  |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator_v.c  |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |   2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h       |   2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h  |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h       |   2 +-
- .../drm/amd/dal/dc/dce80/dce80_stream_encoder.h    |   2 +-
- .../drm/amd/dal/dc/dce80/dce80_timing_generator.c  |   2 +-
- .../drm/amd/dal/dc/dce80/dce80_timing_generator.h  |   2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h |   2 +-
- drivers/gpu/drm/amd/dal/dc/inc/hw/hw_shared.h      |  74 +++++
- drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h            | 126 ++++++++
- drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h   | 123 ++++++++
- drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h      |  69 +++++
- drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h            | 325 +++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h |  88 ++++++
- .../gpu/drm/amd/dal/dc/inc/hw/timing_generator.h   | 153 ++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h      | 192 ++++++++++++
- drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h         |  74 -----
- drivers/gpu/drm/amd/dal/dc/inc/ipp.h               | 126 --------
- drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h      | 123 --------
- drivers/gpu/drm/amd/dal/dc/inc/mem_input.h         |  69 -----
- drivers/gpu/drm/amd/dal/dc/inc/opp.h               | 325 ---------------------
- drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h    |  88 ------
- drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h  | 153 ----------
- drivers/gpu/drm/amd/dal/dc/inc/transform.h         | 192 ------------
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.h  |   2 +-
- .../amd/dal/dc/virtual/virtual_stream_encoder.h    |   2 +-
- 40 files changed, 1174 insertions(+), 1173 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/hw_shared.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/ipp.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/opp.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/inc/transform.h
-
-diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile
-index 25ae464..a140e0b 100644
---- a/drivers/gpu/drm/amd/dal/Makefile
-+++ b/drivers/gpu/drm/amd/dal/Makefile
-@@ -10,6 +10,7 @@ subdir-ccflags-y += -Werror
- subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include
- 
- subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/
-+subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/hw
- 
- #TODO: remove when Timing Sync feature is complete
- subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 7f6f1c3..967b106 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -29,7 +29,7 @@
- 
- /* DC core (private) */
- #include "core_dc.h"
--#include "inc/transform.h"
-+#include "transform.h"
- 
- /*******************************************************************************
-  * Private structures
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index 13b9100..0004d7a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_IPP_DCE110_H__
- #define __DC_IPP_DCE110_H__
- 
--#include "inc/ipp.h"
-+#include "ipp.h"
- 
- 
- struct gamma_parameters;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index bbddd0b..d1fa4a7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_LINK_ENCODER__DCE110_H__
- #define __DC_LINK_ENCODER__DCE110_H__
- 
--#include "inc/link_encoder.h"
-+#include "link_encoder.h"
- 
- #define TO_DCE110_LINK_ENC(link_encoder)\
- 	container_of(link_encoder, struct dce110_link_encoder, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 81b78fd..0383178 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -25,7 +25,7 @@
- #ifndef __DC_MEM_INPUT_DCE110_H__
- #define __DC_MEM_INPUT_DCE110_H__
- 
--#include "inc/mem_input.h"
-+#include "mem_input.h"
- 
- #define TO_DCE110_MEM_INPUT(mi)\
- 	container_of(mi, struct dce110_mem_input, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-index 529aace..24b4211 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-@@ -25,7 +25,7 @@
- #ifndef __DC_MEM_INPUT_V_DCE110_H__
- #define __DC_MEM_INPUT_V_DCE110_H__
- 
--#include "inc/mem_input.h"
-+#include "mem_input.h"
- #include "dce110_mem_input.h"
- 
- bool dce110_mem_input_v_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index 45778e6..abb5a5d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -26,7 +26,7 @@
- #define __DC_OPP_DCE110_H__
- 
- #include "dc_types.h"
--#include "inc/opp.h"
-+#include "opp.h"
- #include "core_types.h"
- 
- #include "gamma_types.h" /* decprecated */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-index cb257fb..d8d6910 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.h
-@@ -26,7 +26,7 @@
- #define __DC_OPP_DCE110_V_H__
- 
- #include "dc_types.h"
--#include "inc/opp.h"
-+#include "opp.h"
- #include "core_types.h"
- 
- #include "gamma_types.h" /* decprecated */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-index 5753a1b..f187ad3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_STREAM_ENCODER_DCE110_H__
- #define __DC_STREAM_ENCODER_DCE110_H__
- 
--#include "inc/stream_encoder.h"
-+#include "stream_encoder.h"
- 
- #define DCE110STRENC_FROM_STRENC(stream_encoder)\
- 	container_of(stream_encoder, struct dce110_stream_encoder, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index d554332..59ec7f4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -37,7 +37,7 @@
- #include "include/logger_interface.h"
- #include "dce110_timing_generator.h"
- 
--#include "../inc/timing_generator.h"
-+#include "timing_generator.h"
- 
- enum black_color_format {
- 	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 9c5e390..d09af97 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -27,7 +27,7 @@
- #define __DC_TIMING_GENERATOR_DCE110_H__
- 
- 
--#include "../inc/timing_generator.h"
-+#include "timing_generator.h"
- #include "../include/grph_object_id.h"
- #include "../include/hw_sequencer_types.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index caf6631..a7ea52e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -15,7 +15,7 @@
- #include "dce110_timing_generator.h"
- #include "dce110_timing_generator_v.h"
- 
--#include "../inc/timing_generator.h"
-+#include "timing_generator.h"
- 
- 
- /** ********************************************************************************
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index 7acbabc..e906fbf 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -25,7 +25,7 @@
- #ifndef __DAL_TRANSFORM_DCE110_H__
- #define __DAL_TRANSFORM_DCE110_H__
- 
--#include "inc/transform.h"
-+#include "transform.h"
- 
- #define TO_DCE110_TRANSFORM(transform)\
- 	container_of(transform, struct dce110_transform, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-index eec3872..1fdffac 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.h
-@@ -25,7 +25,7 @@
- #ifndef __DAL_TRANSFORM_V_DCE110_H__
- #define __DAL_TRANSFORM_V_DCE110_H__
- 
--#include "inc/transform.h"
-+#include "transform.h"
- 
- bool dce110_transform_v_construct(
- 	struct dce110_transform *xfm110,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-index bd81693..adf33cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_IPP_DCE80_H__
- #define __DC_IPP_DCE80_H__
- 
--#include "inc/ipp.h"
-+#include "ipp.h"
- 
- #define TO_DCE80_IPP(input_pixel_processor)\
- 		container_of(input_pixel_processor, struct dce110_ipp, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
-index b894643..06e2c37 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_LINK_ENCODER__DCE80_H__
- #define __DC_LINK_ENCODER__DCE80_H__
- 
--#include "inc/link_encoder.h"
-+#include "link_encoder.h"
- #include "../dce110/dce110_link_encoder.h"
- 
- bool dce80_link_encoder_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-index 1d299da..f07e94a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-@@ -25,7 +25,7 @@
- #ifndef __DC_MEM_INPUT_DCE80_H__
- #define __DC_MEM_INPUT_DCE80_H__
- 
--#include "inc/mem_input.h"
-+#include "mem_input.h"
- 
- bool dce80_mem_input_construct(
- 	struct dce110_mem_input *mem_input80,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-index e152306..a3b1c08 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-@@ -26,7 +26,7 @@
- #define __DC_OPP_DCE80_H__
- 
- #include "dc_types.h"
--#include "inc/opp.h"
-+#include "opp.h"
- #include "gamma_types.h"
- 
- struct gamma_parameters;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-index f4645a8..8b7edb9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-@@ -23,7 +23,7 @@
-  *
-  */
- 
--#include "inc/stream_encoder.h"
-+#include "stream_encoder.h"
- 
- #ifndef __DC_STREAM_ENCODER_DCE80_H__
- #define __DC_STREAM_ENCODER_DCE80_H__
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-index 80391c2..24c1832 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-@@ -37,7 +37,7 @@
- #include "../dce110/dce110_timing_generator.h"
- #include "dce80_timing_generator.h"
- 
--#include "../inc/timing_generator.h"
-+#include "timing_generator.h"
- 
- enum black_color_format {
- 	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-index 0b88686..06339ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-@@ -27,7 +27,7 @@
- #define __DC_TIMING_GENERATOR_DCE80_H__
- 
- 
--#include "../inc/timing_generator.h"
-+#include "timing_generator.h"
- #include "../include/grph_object_id.h"
- 
- /* DCE8.0 implementation inherits from DCE11.0 */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-index ac8e5c9..a0fb2d2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -25,7 +25,7 @@
- #ifndef __DAL_TRANSFORM_DCE80_H__
- #define __DAL_TRANSFORM_DCE80_H__
- 
--#include "inc/transform.h"
-+#include "transform.h"
- 
- #define TO_DCE80_TRANSFORM(transform)\
- 	container_of(transform, struct dce80_transform, base)
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/hw_shared.h
-new file mode 100644
-index 0000000..3b0e616
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/hw_shared.h
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_SHARED_H__
-+#define __DAL_HW_SHARED_H__
-+
-+/******************************************************************************
-+ * Data types shared between different Virtual HW blocks
-+ ******************************************************************************/
-+struct gamma_curve {
-+	uint32_t offset;
-+	uint32_t segments_num;
-+};
-+
-+struct curve_points {
-+	struct fixed31_32 x;
-+	struct fixed31_32 y;
-+	struct fixed31_32 offset;
-+	struct fixed31_32 slope;
-+
-+	uint32_t custom_float_x;
-+	uint32_t custom_float_y;
-+	uint32_t custom_float_offset;
-+	uint32_t custom_float_slope;
-+};
-+
-+struct pwl_result_data {
-+	struct fixed31_32 red;
-+	struct fixed31_32 green;
-+	struct fixed31_32 blue;
-+
-+	struct fixed31_32 delta_red;
-+	struct fixed31_32 delta_green;
-+	struct fixed31_32 delta_blue;
-+
-+	uint32_t red_reg;
-+	uint32_t green_reg;
-+	uint32_t blue_reg;
-+
-+	uint32_t delta_red_reg;
-+	uint32_t delta_green_reg;
-+	uint32_t delta_blue_reg;
-+};
-+
-+struct pwl_params {
-+	uint32_t *data;
-+	struct gamma_curve arr_curve_points[16];
-+	struct curve_points arr_points[3];
-+	struct pwl_result_data rgb_resulted[256 + 3];
-+	uint32_t hw_points_num;
-+};
-+#endif /* __DAL_HW_SHARED_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-new file mode 100644
-index 0000000..505bf72
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-@@ -0,0 +1,126 @@
-+
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IPP_H__
-+#define __DAL_IPP_H__
-+
-+#include "hw_shared.h"
-+
-+#define MAXTRIX_COEFFICIENTS_NUMBER 12
-+#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
-+#define MAX_OVL_MATRIX_COUNT 12
-+
-+/* IPP RELATED */
-+struct input_pixel_processor {
-+	struct  dc_context *ctx;
-+	uint32_t inst;
-+	struct ipp_funcs *funcs;
-+};
-+
-+enum ipp_prescale_mode {
-+	IPP_PRESCALE_MODE_BYPASS,
-+	IPP_PRESCALE_MODE_FIXED_SIGNED,
-+	IPP_PRESCALE_MODE_FLOAT_SIGNED,
-+	IPP_PRESCALE_MODE_FIXED_UNSIGNED,
-+	IPP_PRESCALE_MODE_FLOAT_UNSIGNED
-+};
-+
-+struct ipp_prescale_params {
-+	enum ipp_prescale_mode mode;
-+	uint16_t bias;
-+	uint16_t scale;
-+};
-+
-+enum ipp_degamma_mode {
-+	IPP_DEGAMMA_MODE_BYPASS,
-+	IPP_DEGAMMA_MODE_HW_sRGB,
-+	IPP_DEGAMMA_MODE_HW_xvYCC,
-+	IPP_DEGAMMA_MODE_USER_PWL
-+};
-+
-+
-+enum ovl_color_space {
-+	OVL_COLOR_SPACE_UNKNOWN = 0,
-+	OVL_COLOR_SPACE_RGB,
-+	OVL_COLOR_SPACE_YUV601,
-+	OVL_COLOR_SPACE_YUV709
-+};
-+
-+struct dcp_video_matrix {
-+	enum ovl_color_space color_space;
-+	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
-+};
-+
-+enum expansion_mode {
-+	EXPANSION_MODE_ZERO,
-+	EXPANSION_MODE_DYNAMIC
-+};
-+
-+enum ipp_output_format {
-+	IPP_OUTPUT_FORMAT_12_BIT_FIX,
-+	IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
-+	IPP_OUTPUT_FORMAT_FLOAT
-+};
-+
-+struct ipp_funcs {
-+
-+	/*** cursor ***/
-+	void (*ipp_cursor_set_position)(
-+		struct input_pixel_processor *ipp,
-+		const struct dc_cursor_position *position);
-+
-+	bool (*ipp_cursor_set_attributes)(
-+		struct input_pixel_processor *ipp,
-+		const struct dc_cursor_attributes *attributes);
-+
-+	/*** setup input pixel processing ***/
-+
-+	/* put the entire pixel processor to bypass */
-+	void (*ipp_full_bypass)(struct input_pixel_processor *ipp);
-+
-+	/* setup ipp to expand/convert input to pixel processor internal format */
-+	void (*ipp_setup)(
-+		enum surface_pixel_format input_format,
-+		enum expansion_mode mode,
-+		enum ipp_output_format output_format);
-+
-+	/* DCE function to setup IPP.  TODO: see if we can consolidate to setup */
-+	void (*ipp_program_prescale)(
-+			struct input_pixel_processor *ipp,
-+			struct ipp_prescale_params *params);
-+
-+	/*** DEGAMMA RELATED ***/
-+	bool (*ipp_set_degamma)(
-+		struct input_pixel_processor *ipp,
-+		enum ipp_degamma_mode mode);
-+
-+	bool (*ipp_program_degamma_pwl)(
-+		struct input_pixel_processor *ipp,
-+		const struct pwl_params *params);
-+
-+};
-+
-+#endif /* __DAL_IPP_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-new file mode 100644
-index 0000000..d11ef05
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-@@ -0,0 +1,123 @@
-+/*
-+ * link_encoder.h
-+ *
-+ *  Created on: Oct 6, 2015
-+ *      Author: yonsun
-+ */
-+
-+#ifndef LINK_ENCODER_H_
-+#define LINK_ENCODER_H_
-+
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+#include "dc_types.h"
-+
-+struct dc_context;
-+struct adapter_service;
-+struct encoder_set_dp_phy_pattern_param;
-+struct link_mst_stream_allocation_table;
-+struct dc_link_settings;
-+struct link_training_settings;
-+struct core_stream;
-+struct pipe_ctx;
-+
-+struct encoder_init_data {
-+	struct adapter_service *adapter_service;
-+	enum channel_id channel;
-+	struct graphics_object_id connector;
-+	enum hpd_source_id hpd_source;
-+	/* TODO: in DAL2, here was pointer to EventManagerInterface */
-+	struct graphics_object_id encoder;
-+	struct dc_context *ctx;
-+	enum transmitter transmitter;
-+};
-+
-+struct encoder_feature_support {
-+	union {
-+		struct {
-+			/* 1 - external encoder; 0 - internal encoder */
-+			uint32_t EXTERNAL_ENCODER:1;
-+			uint32_t ANALOG_ENCODER:1;
-+			uint32_t STEREO_SYNC:1;
-+			/* check the DDC data pin
-+			 * when performing DP Sink detection */
-+			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
-+			/* CPLIB authentication
-+			 * for external DP chip supported */
-+			uint32_t CPLIB_DP_AUTHENTICATION:1;
-+			uint32_t IS_HBR2_CAPABLE:1;
-+			uint32_t IS_HBR3_CAPABLE:1;
-+			uint32_t IS_HBR2_VALIDATED:1;
-+			uint32_t IS_TPS3_CAPABLE:1;
-+			uint32_t IS_TPS4_CAPABLE:1;
-+			uint32_t IS_AUDIO_CAPABLE:1;
-+			uint32_t IS_VCE_SUPPORTED:1;
-+			uint32_t IS_CONVERTER:1;
-+			uint32_t IS_Y_ONLY_CAPABLE:1;
-+			uint32_t IS_YCBCR_CAPABLE:1;
-+		} bits;
-+		uint32_t raw;
-+	} flags;
-+	/* maximum supported deep color depth */
-+	enum dc_color_depth max_deep_color;
-+	/* maximum supported clock */
-+	uint32_t max_pixel_clock;
-+};
-+
-+struct link_enc_status {
-+	int dummy; /*TODO*/
-+};
-+struct link_encoder {
-+	struct link_encoder_funcs *funcs;
-+	struct adapter_service *adapter_service;
-+	int32_t aux_channel_offset;
-+	struct dc_context *ctx;
-+	struct graphics_object_id id;
-+	struct graphics_object_id connector;
-+	uint32_t input_signals;
-+	uint32_t output_signals;
-+	enum engine_id preferred_engine;
-+	struct encoder_feature_support features;
-+	enum transmitter transmitter;
-+	enum hpd_source_id hpd_source;
-+};
-+
-+struct link_encoder_funcs {
-+	bool (*validate_output_with_stream)(
-+		struct link_encoder *enc, struct pipe_ctx *pipe_ctx);
-+	void (*hw_init)(struct link_encoder *enc);
-+	void (*setup)(struct link_encoder *enc,
-+		enum signal_type signal);
-+	void (*enable_tmds_output)(struct link_encoder *enc,
-+		enum clock_source_id clock_source,
-+		enum dc_color_depth color_depth,
-+		bool hdmi,
-+		bool dual_link,
-+		uint32_t pixel_clock);
-+	void (*enable_dp_output)(struct link_encoder *enc,
-+		const struct dc_link_settings *link_settings,
-+		enum clock_source_id clock_source);
-+	void (*enable_dp_mst_output)(struct link_encoder *enc,
-+		const struct dc_link_settings *link_settings,
-+		enum clock_source_id clock_source);
-+	void (*disable_output)(struct link_encoder *link_enc,
-+		enum signal_type signal);
-+	void (*dp_set_lane_settings)(struct link_encoder *enc,
-+		const struct link_training_settings *link_settings);
-+	void (*dp_set_phy_pattern)(struct link_encoder *enc,
-+		const struct encoder_set_dp_phy_pattern_param *para);
-+	void (*update_mst_stream_allocation_table)(
-+		struct link_encoder *enc,
-+		const struct link_mst_stream_allocation_table *table);
-+	void (*set_lcd_backlight_level) (struct link_encoder *enc,
-+		uint32_t level);
-+	void (*backlight_control) (struct link_encoder *enc,
-+		bool enable);
-+	void (*power_control) (struct link_encoder *enc,
-+		bool power_up);
-+	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
-+		enum engine_id engine,
-+		bool connect);
-+};
-+
-+#endif /* LINK_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-new file mode 100644
-index 0000000..8339d61
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-@@ -0,0 +1,69 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_MEM_INPUT_H__
-+#define __DAL_MEM_INPUT_H__
-+
-+#include "include/grph_object_id.h"
-+#include "dc.h"
-+
-+struct mem_input {
-+	struct mem_input_funcs *funcs;
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+};
-+
-+struct mem_input_funcs {
-+	void (*mem_input_program_display_marks)(
-+		struct mem_input *mem_input,
-+		struct bw_watermarks nbp,
-+		struct bw_watermarks stutter,
-+		struct bw_watermarks urgent,
-+		uint32_t total_dest_line_time_ns);
-+
-+	void (*allocate_mem_input)(
-+		struct mem_input *mem_input,
-+		uint32_t h_total,/* for current target */
-+		uint32_t v_total,/* for current target */
-+		uint32_t pix_clk_khz,/* for current target */
-+		uint32_t total_streams_num);
-+
-+	void (*free_mem_input)(
-+		struct mem_input *mem_input,
-+		uint32_t paths_num);
-+
-+	bool (*mem_input_program_surface_flip_and_addr)(
-+		struct mem_input *mem_input,
-+		const struct dc_plane_address *address,
-+		bool flip_immediate);
-+
-+	bool (*mem_input_program_surface_config)(
-+		struct mem_input *mem_input,
-+		enum surface_pixel_format format,
-+		struct dc_tiling_info *tiling_info,
-+		union plane_size *plane_size,
-+		enum dc_rotation_angle rotation);
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-new file mode 100644
-index 0000000..1c9b732
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-@@ -0,0 +1,325 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_OPP_H__
-+#define __DAL_OPP_H__
-+
-+#include "hw_shared.h"
-+
-+struct fixed31_32;
-+struct gamma_parameters;
-+
-+/* TODO: Need cleanup */
-+enum clamping_range {
-+	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
-+	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
-+	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
-+	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
-+	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
-+	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
-+};
-+
-+struct clamping_and_pixel_encoding_params {
-+	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
-+	enum clamping_range clamping_level; /* Clamping identifier */
-+	enum dc_color_depth c_depth; /* Deep color use. */
-+};
-+
-+struct bit_depth_reduction_params {
-+	struct {
-+		/* truncate/round */
-+		/* trunc/round enabled*/
-+		uint32_t TRUNCATE_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
-+		uint32_t TRUNCATE_DEPTH:2;
-+		/* truncate or round*/
-+		uint32_t TRUNCATE_MODE:1;
-+
-+		/* spatial dither */
-+		/* Spatial Bit Depth Reduction enabled*/
-+		uint32_t SPATIAL_DITHER_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
-+		uint32_t SPATIAL_DITHER_DEPTH:2;
-+		/* 0-3 to select patterns*/
-+		uint32_t SPATIAL_DITHER_MODE:2;
-+		/* Enable RGB random dithering*/
-+		uint32_t RGB_RANDOM:1;
-+		/* Enable Frame random dithering*/
-+		uint32_t FRAME_RANDOM:1;
-+		/* Enable HighPass random dithering*/
-+		uint32_t HIGHPASS_RANDOM:1;
-+
-+		/* temporal dither*/
-+		 /* frame modulation enabled*/
-+		uint32_t FRAME_MODULATION_ENABLED:1;
-+		/* same as for trunc/spatial*/
-+		uint32_t FRAME_MODULATION_DEPTH:2;
-+		/* 2/4 gray levels*/
-+		uint32_t TEMPORAL_LEVEL:1;
-+		uint32_t FRC25:2;
-+		uint32_t FRC50:2;
-+		uint32_t FRC75:2;
-+	} flags;
-+
-+	uint32_t r_seed_value;
-+	uint32_t b_seed_value;
-+	uint32_t g_seed_value;
-+};
-+
-+
-+
-+enum wide_gamut_regamma_mode {
-+	/*  0x0  - BITS2:0 Bypass */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
-+	/*  0x1  - Fixed curve sRGB 2.4 */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24,
-+	/*  0x2  - Fixed curve xvYCC 2.22 */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22,
-+	/*  0x3  - Programmable control A */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A,
-+	/*  0x4  - Programmable control B */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B,
-+	/*  0x0  - BITS6:4 Bypass */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS,
-+	/*  0x1  - Fixed curve sRGB 2.4 */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24,
-+	/*  0x2  - Fixed curve xvYCC 2.22 */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22,
-+	/*  0x3  - Programmable control A */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A,
-+	/*  0x4  - Programmable control B */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
-+};
-+
-+struct gamma_pixel {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+};
-+
-+enum channel_name {
-+	CHANNEL_NAME_RED,
-+	CHANNEL_NAME_GREEN,
-+	CHANNEL_NAME_BLUE
-+};
-+
-+struct custom_float_format {
-+	uint32_t mantissa_bits;
-+	uint32_t exponenta_bits;
-+	bool sign;
-+};
-+
-+struct custom_float_value {
-+	uint32_t mantissa;
-+	uint32_t exponenta;
-+	uint32_t value;
-+	bool negative;
-+};
-+
-+struct hw_x_point {
-+	uint32_t custom_float_x;
-+	uint32_t custom_float_x_adjusted;
-+	struct fixed31_32 x;
-+	struct fixed31_32 adjusted_x;
-+	struct fixed31_32 regamma_y_red;
-+	struct fixed31_32 regamma_y_green;
-+	struct fixed31_32 regamma_y_blue;
-+
-+};
-+
-+struct pwl_float_data_ex {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+	struct fixed31_32 delta_r;
-+	struct fixed31_32 delta_g;
-+	struct fixed31_32 delta_b;
-+};
-+
-+enum hw_point_position {
-+	/* hw point sits between left and right sw points */
-+	HW_POINT_POSITION_MIDDLE,
-+	/* hw point lays left from left (smaller) sw point */
-+	HW_POINT_POSITION_LEFT,
-+	/* hw point lays stays from right (bigger) sw point */
-+	HW_POINT_POSITION_RIGHT
-+};
-+
-+struct gamma_point {
-+	int32_t left_index;
-+	int32_t right_index;
-+	enum hw_point_position pos;
-+	struct fixed31_32 coeff;
-+};
-+
-+struct pixel_gamma_point {
-+	struct gamma_point r;
-+	struct gamma_point g;
-+	struct gamma_point b;
-+};
-+
-+struct gamma_coefficients {
-+	struct fixed31_32 a0[3];
-+	struct fixed31_32 a1[3];
-+	struct fixed31_32 a2[3];
-+	struct fixed31_32 a3[3];
-+	struct fixed31_32 user_gamma[3];
-+	struct fixed31_32 user_contrast;
-+	struct fixed31_32 user_brightness;
-+};
-+
-+struct csc_adjustments {
-+	struct fixed31_32 contrast;
-+	struct fixed31_32 saturation;
-+	struct fixed31_32 brightness;
-+	struct fixed31_32 hue;
-+};
-+
-+struct pwl_float_data {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+};
-+
-+enum opp_regamma {
-+	OPP_REGAMMA_BYPASS = 0,
-+	OPP_REGAMMA_SRGB,
-+	OPP_REGAMMA_3_6,
-+	OPP_REGAMMA_USER,
-+};
-+
-+struct output_pixel_processor {
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+	struct opp_funcs *funcs;
-+};
-+
-+enum fmt_stereo_action {
-+	FMT_STEREO_ACTION_ENABLE = 0,
-+	FMT_STEREO_ACTION_DISABLE,
-+	FMT_STEREO_ACTION_UPDATE_POLARITY
-+};
-+
-+enum graphics_csc_adjust_type {
-+	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
-+};
-+
-+struct default_adjustment {
-+	uint32_t lb_color_depth;
-+	enum dc_color_space out_color_space;
-+	enum dc_color_space in_color_space;
-+	enum dc_color_depth color_depth;
-+	enum pixel_format surface_pixel_format;
-+	enum graphics_csc_adjust_type csc_adjust_type;
-+	bool force_hw_default;
-+};
-+
-+enum grph_color_adjust_option {
-+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
-+	GRPH_COLOR_MATRIX_SW
-+};
-+
-+struct opp_grph_csc_adjustment {
-+	enum grph_color_adjust_option color_adjust_option;
-+	enum dc_color_space c_space;
-+	enum dc_color_depth color_depth; /* clean up to uint32_t */
-+	enum graphics_csc_adjust_type   csc_adjust_type;
-+	int32_t adjust_divider;
-+	int32_t grph_cont;
-+	int32_t grph_sat;
-+	int32_t grph_bright;
-+	int32_t grph_hue;
-+};
-+
-+
-+/* Underlay related types */
-+
-+struct hw_adjustment_range {
-+	int32_t hw_default;
-+	int32_t min;
-+	int32_t max;
-+	int32_t step;
-+	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
-+};
-+
-+enum ovl_csc_adjust_item {
-+	OVERLAY_BRIGHTNESS = 0,
-+	OVERLAY_GAMMA,
-+	OVERLAY_CONTRAST,
-+	OVERLAY_SATURATION,
-+	OVERLAY_HUE,
-+	OVERLAY_ALPHA,
-+	OVERLAY_ALPHA_PER_PIX,
-+	OVERLAY_COLOR_TEMPERATURE
-+};
-+
-+struct opp_funcs {
-+	void (*opp_power_on_regamma_lut)(
-+		struct output_pixel_processor *opp,
-+		bool power_on);
-+
-+	bool (*opp_program_regamma_pwl)(
-+		struct output_pixel_processor *opp,
-+		const struct pwl_params *params);
-+
-+	void (*opp_set_regamma_mode)(struct output_pixel_processor *opp,
-+			enum opp_regamma mode);
-+
-+	void (*opp_set_csc_adjustment)(
-+		struct output_pixel_processor *opp,
-+		const struct opp_grph_csc_adjustment *adjust);
-+
-+	void (*opp_set_csc_default)(
-+		struct output_pixel_processor *opp,
-+		const struct default_adjustment *default_adjust);
-+
-+	/* FORMATTER RELATED */
-+	void (*opp_program_bit_depth_reduction)(
-+		struct output_pixel_processor *opp,
-+		const struct bit_depth_reduction_params *params);
-+
-+	void (*opp_program_clamping_and_pixel_encoding)(
-+		struct output_pixel_processor *opp,
-+		const struct clamping_and_pixel_encoding_params *params);
-+
-+	void (*opp_set_dyn_expansion)(
-+		struct output_pixel_processor *opp,
-+		enum dc_color_space color_sp,
-+		enum dc_color_depth color_dpth,
-+		enum signal_type signal);
-+
-+	/* underlay related */
-+	void (*opp_get_underlay_adjustment_range)(
-+			struct output_pixel_processor *opp,
-+			enum ovl_csc_adjust_item overlay_adjust_item,
-+			struct hw_adjustment_range *range);
-+
-+
-+	void (*opp_destroy)(struct output_pixel_processor **opp);
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
-new file mode 100644
-index 0000000..47cf6de
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
-@@ -0,0 +1,88 @@
-+/*
-+ * stream_encoder.h
-+ *
-+ */
-+
-+#ifndef STREAM_ENCODER_H_
-+#define STREAM_ENCODER_H_
-+
-+#include "include/hw_sequencer_types.h"
-+
-+struct dc_bios;
-+struct dc_context;
-+struct dc_crtc_timing;
-+
-+
-+struct encoder_info_packet {
-+	bool valid;
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t hb3;
-+	uint8_t sb[28];
-+};
-+
-+struct encoder_info_frame {
-+	/* auxiliary video information */
-+	struct encoder_info_packet avi;
-+	struct encoder_info_packet gamut;
-+	struct encoder_info_packet vendor;
-+	/* source product description */
-+	struct encoder_info_packet spd;
-+	/* video stream configuration */
-+	struct encoder_info_packet vsc;
-+};
-+
-+struct encoder_unblank_param {
-+	struct hw_crtc_timing crtc_timing;
-+	struct dc_link_settings link_settings;
-+};
-+
-+struct encoder_set_dp_phy_pattern_param {
-+	enum dp_test_pattern dp_phy_pattern;
-+	const uint8_t *custom_pattern;
-+	uint32_t custom_pattern_size;
-+	enum dp_panel_mode dp_panel_mode;
-+};
-+
-+
-+struct stream_encoder {
-+	struct stream_encoder_funcs *funcs;
-+	struct dc_context *ctx;
-+	struct dc_bios *bp;
-+	enum engine_id id;
-+};
-+
-+struct stream_encoder_funcs {
-+	void (*dp_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing);
-+	void (*hdmi_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		bool enable_audio);
-+	void (*dvi_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		bool is_dual_link);
-+	void (*set_mst_bandwidth)(
-+		struct stream_encoder *enc,
-+		struct fixed31_32 avg_time_slots_per_mtp);
-+	void (*update_hdmi_info_packets)(
-+		struct stream_encoder *enc,
-+		const struct encoder_info_frame *info_frame);
-+	void (*stop_hdmi_info_packets)(
-+		struct stream_encoder *enc);
-+	void (*update_dp_info_packets)(
-+		struct stream_encoder *enc,
-+		const struct encoder_info_frame *info_frame);
-+	void (*stop_dp_info_packets)(
-+		struct stream_encoder *enc);
-+	void (*dp_blank)(
-+		struct stream_encoder *enc);
-+	void (*dp_unblank)(
-+		struct stream_encoder *enc,
-+		const struct encoder_unblank_param *param);
-+};
-+
-+#endif /* STREAM_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-new file mode 100644
-index 0000000..374e222
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-@@ -0,0 +1,153 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
-+#define __DAL_TIMING_GENERATOR_TYPES_H__
-+
-+struct dc_bios;
-+
-+/**
-+ *  These parameters are required as input when doing blanking/Unblanking
-+*/
-+struct crtc_black_color {
-+	uint32_t black_color_r_cr;
-+	uint32_t black_color_g_y;
-+	uint32_t black_color_b_cb;
-+};
-+
-+/* Contains CRTC vertical/horizontal pixel counters */
-+struct crtc_position {
-+	uint32_t vertical_count;
-+	uint32_t horizontal_count;
-+	uint32_t nominal_vcount;
-+};
-+
-+
-+enum dcp_gsl_purpose {
-+	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
-+	DCP_GSL_PURPOSE_STEREO3D_PHASE,
-+	DCP_GSL_PURPOSE_UNDEFINED
-+};
-+
-+struct dcp_gsl_params {
-+	enum sync_source gsl_group;
-+	enum dcp_gsl_purpose gsl_purpose;
-+	bool timing_server;
-+	bool overlay_present;
-+	bool gsl_paused;
-+};
-+
-+#define LEFT_EYE_3D_PRIMARY_SURFACE 1
-+#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
-+
-+enum test_pattern_dyn_range {
-+	TEST_PATTERN_DYN_RANGE_VESA = 0,
-+	TEST_PATTERN_DYN_RANGE_CEA
-+};
-+
-+enum test_pattern_mode {
-+	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
-+	TEST_PATTERN_MODE_VERTICALBARS,
-+	TEST_PATTERN_MODE_HORIZONTALBARS,
-+	TEST_PATTERN_MODE_SINGLERAMP_RGB,
-+	TEST_PATTERN_MODE_DUALRAMP_RGB
-+};
-+
-+enum test_pattern_color_format {
-+	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_8,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_10,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_12
-+};
-+
-+enum controller_dp_test_pattern {
-+	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
-+	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
-+	CONTROLLER_DP_TEST_PATTERN_PRBS7,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
-+	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
-+	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-+};
-+
-+enum crtc_state {
-+	CRTC_STATE_VBLANK = 0,
-+	CRTC_STATE_VACTIVE
-+};
-+
-+struct timing_generator {
-+	struct timing_generator_funcs *funcs;
-+	struct dc_bios *bp;
-+	struct dc_context *ctx;
-+};
-+
-+
-+struct dc_crtc_timing;
-+
-+struct timing_generator_funcs {
-+	bool (*validate_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing);
-+	void (*program_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing,
-+							bool use_vbios);
-+	bool (*enable_crtc)(struct timing_generator *tg);
-+	bool (*disable_crtc)(struct timing_generator *tg);
-+	bool (*is_counter_moving)(struct timing_generator *tg);
-+	void (*get_position)(struct timing_generator *tg,
-+								int32_t *h_position,
-+								int32_t *v_position);
-+	uint32_t (*get_frame_count)(struct timing_generator *tg);
-+	void (*set_early_control)(struct timing_generator *tg,
-+							   uint32_t early_cntl);
-+	void (*wait_for_state)(struct timing_generator *tg,
-+							enum crtc_state state);
-+	bool (*set_blank)(struct timing_generator *tg,
-+					   bool enable_blanking);
-+	void (*set_overscan_blank_color) (struct timing_generator *tg, enum dc_color_space black_color);
-+	void (*set_blank_color)(struct timing_generator *tg, enum dc_color_space black_color);
-+	void (*set_colors)(struct timing_generator *tg,
-+						const struct crtc_black_color *blank_color,
-+						const struct crtc_black_color *overscan_color);
-+
-+	void (*disable_vga)(struct timing_generator *tg);
-+	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
-+	void (*setup_global_swap_lock)(struct timing_generator *tg,
-+							const struct dcp_gsl_params *gsl_params);
-+	void (*enable_reset_trigger)(struct timing_generator *tg,
-+						const struct trigger_params *trigger_params);
-+	void (*disable_reset_trigger)(struct timing_generator *tg);
-+	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
-+	void (*enable_advanced_request)(struct timing_generator *tg,
-+					bool enable, const struct dc_crtc_timing *timing);
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-new file mode 100644
-index 0000000..bf84f96
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-@@ -0,0 +1,192 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_H__
-+#define __DAL_TRANSFORM_H__
-+
-+#include "include/scaler_types.h"
-+#include "calcs/scaler_filter.h"
-+
-+struct bit_depth_reduction_params;
-+
-+struct transform {
-+	struct transform_funcs *funcs;
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+	struct scaler_filter *filter;
-+};
-+
-+enum lb_pixel_depth {
-+	/* do not change the values because it is used as bit vector */
-+	LB_PIXEL_DEPTH_18BPP = 1,
-+	LB_PIXEL_DEPTH_24BPP = 2,
-+	LB_PIXEL_DEPTH_30BPP = 4,
-+	LB_PIXEL_DEPTH_36BPP = 8
-+};
-+
-+
-+enum raw_gamma_ramp_type {
-+       GAMMA_RAMP_TYPE_UNINITIALIZED,
-+       GAMMA_RAMP_TYPE_DEFAULT,
-+       GAMMA_RAMP_TYPE_RGB256,
-+       GAMMA_RAMP_TYPE_FIXED_POINT
-+};
-+
-+#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
-+
-+/* Colorimetry */
-+enum colorimetry {
-+       COLORIMETRY_NO_DATA = 0,
-+       COLORIMETRY_ITU601 = 1,
-+       COLORIMETRY_ITU709 = 2,
-+       COLORIMETRY_EXTENDED = 3
-+};
-+
-+enum ds_color_space {
-+       DS_COLOR_SPACE_UNKNOWN = 0,
-+       DS_COLOR_SPACE_SRGB_FULLRANGE = 1,
-+       DS_COLOR_SPACE_SRGB_LIMITEDRANGE,
-+       DS_COLOR_SPACE_YPBPR601,
-+       DS_COLOR_SPACE_YPBPR709,
-+       DS_COLOR_SPACE_YCBCR601,
-+       DS_COLOR_SPACE_YCBCR709,
-+       DS_COLOR_SPACE_NMVPU_SUPERAA,
-+       DS_COLOR_SPACE_YCBCR601_YONLY,
-+       DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/
-+};
-+
-+enum active_format_info {
-+       ACTIVE_FORMAT_NO_DATA = 0,
-+       ACTIVE_FORMAT_VALID = 1
-+};
-+
-+/* Active format aspect ratio */
-+enum active_format_aspect_ratio {
-+       ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
-+       ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
-+       ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
-+       ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
-+};
-+
-+enum bar_info {
-+       BAR_INFO_NOT_VALID = 0,
-+       BAR_INFO_VERTICAL_VALID = 1,
-+       BAR_INFO_HORIZONTAL_VALID = 2,
-+       BAR_INFO_BOTH_VALID = 3
-+};
-+
-+enum picture_scaling {
-+       PICTURE_SCALING_UNIFORM = 0,
-+       PICTURE_SCALING_HORIZONTAL = 1,
-+       PICTURE_SCALING_VERTICAL = 2,
-+       PICTURE_SCALING_BOTH = 3
-+};
-+
-+/* RGB quantization range */
-+enum rgb_quantization_range {
-+       RGB_QUANTIZATION_DEFAULT_RANGE = 0,
-+       RGB_QUANTIZATION_LIMITED_RANGE = 1,
-+       RGB_QUANTIZATION_FULL_RANGE = 2,
-+       RGB_QUANTIZATION_RESERVED = 3
-+};
-+
-+/* YYC quantization range */
-+enum yyc_quantization_range {
-+       YYC_QUANTIZATION_LIMITED_RANGE = 0,
-+       YYC_QUANTIZATION_FULL_RANGE = 1,
-+       YYC_QUANTIZATION_RESERVED2 = 2,
-+       YYC_QUANTIZATION_RESERVED3 = 3
-+};
-+
-+enum graphics_gamut_adjust_type {
-+	GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_GAMUT_ADJUST_TYPE_SW  /* use adjustments */
-+};
-+
-+#define CSC_TEMPERATURE_MATRIX_SIZE 9
-+
-+struct xfm_grph_csc_adjustment {
-+	int32_t temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
-+	int32_t temperature_divider;
-+	enum graphics_gamut_adjust_type gamut_adjust_type;
-+};
-+
-+/*overscan or window*/
-+struct overscan_info {
-+	uint32_t left;
-+	uint32_t right;
-+	uint32_t top;
-+	uint32_t bottom;
-+};
-+
-+struct scaling_ratios {
-+	struct fixed31_32 horz;
-+	struct fixed31_32 vert;
-+	struct fixed31_32 horz_c;
-+	struct fixed31_32 vert_c;
-+};
-+
-+struct scaler_data {
-+	struct overscan_info overscan;
-+	struct scaling_taps taps;
-+	struct rect viewport;
-+	struct scaling_ratios ratios;
-+
-+	enum pixel_format format;
-+};
-+
-+struct transform_funcs {
-+	bool (*transform_power_up)(
-+		struct transform *xfm);
-+
-+	bool (*transform_set_scaler)(
-+		struct transform *xfm,
-+		const struct scaler_data *data);
-+
-+	void (*transform_set_scaler_bypass)(
-+		struct transform *xfm);
-+
-+	void (*transform_set_scaler_filter)(
-+		struct transform *xfm,
-+		struct scaler_filter *filter);
-+
-+	void (*transform_set_gamut_remap)(
-+		struct transform *xfm,
-+		const struct xfm_grph_csc_adjustment *adjust);
-+
-+	bool (*transform_set_pixel_storage_depth)(
-+		struct transform *xfm,
-+		enum lb_pixel_depth depth,
-+		const struct bit_depth_reduction_params *bit_depth_params);
-+
-+	bool (*transform_get_current_pixel_storage_depth)(
-+		struct transform *xfm,
-+		enum lb_pixel_depth *depth);
-+
-+	void (*transform_set_alpha)(struct transform *xfm, bool enable);
-+};
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h
-deleted file mode 100644
-index 3b0e616..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_shared.h
-+++ /dev/null
-@@ -1,74 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_HW_SHARED_H__
--#define __DAL_HW_SHARED_H__
--
--/******************************************************************************
-- * Data types shared between different Virtual HW blocks
-- ******************************************************************************/
--struct gamma_curve {
--	uint32_t offset;
--	uint32_t segments_num;
--};
--
--struct curve_points {
--	struct fixed31_32 x;
--	struct fixed31_32 y;
--	struct fixed31_32 offset;
--	struct fixed31_32 slope;
--
--	uint32_t custom_float_x;
--	uint32_t custom_float_y;
--	uint32_t custom_float_offset;
--	uint32_t custom_float_slope;
--};
--
--struct pwl_result_data {
--	struct fixed31_32 red;
--	struct fixed31_32 green;
--	struct fixed31_32 blue;
--
--	struct fixed31_32 delta_red;
--	struct fixed31_32 delta_green;
--	struct fixed31_32 delta_blue;
--
--	uint32_t red_reg;
--	uint32_t green_reg;
--	uint32_t blue_reg;
--
--	uint32_t delta_red_reg;
--	uint32_t delta_green_reg;
--	uint32_t delta_blue_reg;
--};
--
--struct pwl_params {
--	uint32_t *data;
--	struct gamma_curve arr_curve_points[16];
--	struct curve_points arr_points[3];
--	struct pwl_result_data rgb_resulted[256 + 3];
--	uint32_t hw_points_num;
--};
--#endif /* __DAL_HW_SHARED_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-deleted file mode 100644
-index 505bf72..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
-+++ /dev/null
-@@ -1,126 +0,0 @@
--
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_IPP_H__
--#define __DAL_IPP_H__
--
--#include "hw_shared.h"
--
--#define MAXTRIX_COEFFICIENTS_NUMBER 12
--#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
--#define MAX_OVL_MATRIX_COUNT 12
--
--/* IPP RELATED */
--struct input_pixel_processor {
--	struct  dc_context *ctx;
--	uint32_t inst;
--	struct ipp_funcs *funcs;
--};
--
--enum ipp_prescale_mode {
--	IPP_PRESCALE_MODE_BYPASS,
--	IPP_PRESCALE_MODE_FIXED_SIGNED,
--	IPP_PRESCALE_MODE_FLOAT_SIGNED,
--	IPP_PRESCALE_MODE_FIXED_UNSIGNED,
--	IPP_PRESCALE_MODE_FLOAT_UNSIGNED
--};
--
--struct ipp_prescale_params {
--	enum ipp_prescale_mode mode;
--	uint16_t bias;
--	uint16_t scale;
--};
--
--enum ipp_degamma_mode {
--	IPP_DEGAMMA_MODE_BYPASS,
--	IPP_DEGAMMA_MODE_HW_sRGB,
--	IPP_DEGAMMA_MODE_HW_xvYCC,
--	IPP_DEGAMMA_MODE_USER_PWL
--};
--
--
--enum ovl_color_space {
--	OVL_COLOR_SPACE_UNKNOWN = 0,
--	OVL_COLOR_SPACE_RGB,
--	OVL_COLOR_SPACE_YUV601,
--	OVL_COLOR_SPACE_YUV709
--};
--
--struct dcp_video_matrix {
--	enum ovl_color_space color_space;
--	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
--};
--
--enum expansion_mode {
--	EXPANSION_MODE_ZERO,
--	EXPANSION_MODE_DYNAMIC
--};
--
--enum ipp_output_format {
--	IPP_OUTPUT_FORMAT_12_BIT_FIX,
--	IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
--	IPP_OUTPUT_FORMAT_FLOAT
--};
--
--struct ipp_funcs {
--
--	/*** cursor ***/
--	void (*ipp_cursor_set_position)(
--		struct input_pixel_processor *ipp,
--		const struct dc_cursor_position *position);
--
--	bool (*ipp_cursor_set_attributes)(
--		struct input_pixel_processor *ipp,
--		const struct dc_cursor_attributes *attributes);
--
--	/*** setup input pixel processing ***/
--
--	/* put the entire pixel processor to bypass */
--	void (*ipp_full_bypass)(struct input_pixel_processor *ipp);
--
--	/* setup ipp to expand/convert input to pixel processor internal format */
--	void (*ipp_setup)(
--		enum surface_pixel_format input_format,
--		enum expansion_mode mode,
--		enum ipp_output_format output_format);
--
--	/* DCE function to setup IPP.  TODO: see if we can consolidate to setup */
--	void (*ipp_program_prescale)(
--			struct input_pixel_processor *ipp,
--			struct ipp_prescale_params *params);
--
--	/*** DEGAMMA RELATED ***/
--	bool (*ipp_set_degamma)(
--		struct input_pixel_processor *ipp,
--		enum ipp_degamma_mode mode);
--
--	bool (*ipp_program_degamma_pwl)(
--		struct input_pixel_processor *ipp,
--		const struct pwl_params *params);
--
--};
--
--#endif /* __DAL_IPP_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-deleted file mode 100644
-index d11ef05..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h
-+++ /dev/null
-@@ -1,123 +0,0 @@
--/*
-- * link_encoder.h
-- *
-- *  Created on: Oct 6, 2015
-- *      Author: yonsun
-- */
--
--#ifndef LINK_ENCODER_H_
--#define LINK_ENCODER_H_
--
--#include "grph_object_defs.h"
--#include "signal_types.h"
--#include "dc_types.h"
--
--struct dc_context;
--struct adapter_service;
--struct encoder_set_dp_phy_pattern_param;
--struct link_mst_stream_allocation_table;
--struct dc_link_settings;
--struct link_training_settings;
--struct core_stream;
--struct pipe_ctx;
--
--struct encoder_init_data {
--	struct adapter_service *adapter_service;
--	enum channel_id channel;
--	struct graphics_object_id connector;
--	enum hpd_source_id hpd_source;
--	/* TODO: in DAL2, here was pointer to EventManagerInterface */
--	struct graphics_object_id encoder;
--	struct dc_context *ctx;
--	enum transmitter transmitter;
--};
--
--struct encoder_feature_support {
--	union {
--		struct {
--			/* 1 - external encoder; 0 - internal encoder */
--			uint32_t EXTERNAL_ENCODER:1;
--			uint32_t ANALOG_ENCODER:1;
--			uint32_t STEREO_SYNC:1;
--			/* check the DDC data pin
--			 * when performing DP Sink detection */
--			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
--			/* CPLIB authentication
--			 * for external DP chip supported */
--			uint32_t CPLIB_DP_AUTHENTICATION:1;
--			uint32_t IS_HBR2_CAPABLE:1;
--			uint32_t IS_HBR3_CAPABLE:1;
--			uint32_t IS_HBR2_VALIDATED:1;
--			uint32_t IS_TPS3_CAPABLE:1;
--			uint32_t IS_TPS4_CAPABLE:1;
--			uint32_t IS_AUDIO_CAPABLE:1;
--			uint32_t IS_VCE_SUPPORTED:1;
--			uint32_t IS_CONVERTER:1;
--			uint32_t IS_Y_ONLY_CAPABLE:1;
--			uint32_t IS_YCBCR_CAPABLE:1;
--		} bits;
--		uint32_t raw;
--	} flags;
--	/* maximum supported deep color depth */
--	enum dc_color_depth max_deep_color;
--	/* maximum supported clock */
--	uint32_t max_pixel_clock;
--};
--
--struct link_enc_status {
--	int dummy; /*TODO*/
--};
--struct link_encoder {
--	struct link_encoder_funcs *funcs;
--	struct adapter_service *adapter_service;
--	int32_t aux_channel_offset;
--	struct dc_context *ctx;
--	struct graphics_object_id id;
--	struct graphics_object_id connector;
--	uint32_t input_signals;
--	uint32_t output_signals;
--	enum engine_id preferred_engine;
--	struct encoder_feature_support features;
--	enum transmitter transmitter;
--	enum hpd_source_id hpd_source;
--};
--
--struct link_encoder_funcs {
--	bool (*validate_output_with_stream)(
--		struct link_encoder *enc, struct pipe_ctx *pipe_ctx);
--	void (*hw_init)(struct link_encoder *enc);
--	void (*setup)(struct link_encoder *enc,
--		enum signal_type signal);
--	void (*enable_tmds_output)(struct link_encoder *enc,
--		enum clock_source_id clock_source,
--		enum dc_color_depth color_depth,
--		bool hdmi,
--		bool dual_link,
--		uint32_t pixel_clock);
--	void (*enable_dp_output)(struct link_encoder *enc,
--		const struct dc_link_settings *link_settings,
--		enum clock_source_id clock_source);
--	void (*enable_dp_mst_output)(struct link_encoder *enc,
--		const struct dc_link_settings *link_settings,
--		enum clock_source_id clock_source);
--	void (*disable_output)(struct link_encoder *link_enc,
--		enum signal_type signal);
--	void (*dp_set_lane_settings)(struct link_encoder *enc,
--		const struct link_training_settings *link_settings);
--	void (*dp_set_phy_pattern)(struct link_encoder *enc,
--		const struct encoder_set_dp_phy_pattern_param *para);
--	void (*update_mst_stream_allocation_table)(
--		struct link_encoder *enc,
--		const struct link_mst_stream_allocation_table *table);
--	void (*set_lcd_backlight_level) (struct link_encoder *enc,
--		uint32_t level);
--	void (*backlight_control) (struct link_encoder *enc,
--		bool enable);
--	void (*power_control) (struct link_encoder *enc,
--		bool power_up);
--	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
--		enum engine_id engine,
--		bool connect);
--};
--
--#endif /* LINK_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-deleted file mode 100644
-index 8339d61..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h
-+++ /dev/null
-@@ -1,69 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_MEM_INPUT_H__
--#define __DAL_MEM_INPUT_H__
--
--#include "include/grph_object_id.h"
--#include "dc.h"
--
--struct mem_input {
--	struct mem_input_funcs *funcs;
--	struct dc_context *ctx;
--	uint32_t inst;
--};
--
--struct mem_input_funcs {
--	void (*mem_input_program_display_marks)(
--		struct mem_input *mem_input,
--		struct bw_watermarks nbp,
--		struct bw_watermarks stutter,
--		struct bw_watermarks urgent,
--		uint32_t total_dest_line_time_ns);
--
--	void (*allocate_mem_input)(
--		struct mem_input *mem_input,
--		uint32_t h_total,/* for current target */
--		uint32_t v_total,/* for current target */
--		uint32_t pix_clk_khz,/* for current target */
--		uint32_t total_streams_num);
--
--	void (*free_mem_input)(
--		struct mem_input *mem_input,
--		uint32_t paths_num);
--
--	bool (*mem_input_program_surface_flip_and_addr)(
--		struct mem_input *mem_input,
--		const struct dc_plane_address *address,
--		bool flip_immediate);
--
--	bool (*mem_input_program_surface_config)(
--		struct mem_input *mem_input,
--		enum surface_pixel_format format,
--		struct dc_tiling_info *tiling_info,
--		union plane_size *plane_size,
--		enum dc_rotation_angle rotation);
--};
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-deleted file mode 100644
-index 1c9b732..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h
-+++ /dev/null
-@@ -1,325 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_OPP_H__
--#define __DAL_OPP_H__
--
--#include "hw_shared.h"
--
--struct fixed31_32;
--struct gamma_parameters;
--
--/* TODO: Need cleanup */
--enum clamping_range {
--	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
--	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
--	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
--	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
--	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
--	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
--};
--
--struct clamping_and_pixel_encoding_params {
--	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
--	enum clamping_range clamping_level; /* Clamping identifier */
--	enum dc_color_depth c_depth; /* Deep color use. */
--};
--
--struct bit_depth_reduction_params {
--	struct {
--		/* truncate/round */
--		/* trunc/round enabled*/
--		uint32_t TRUNCATE_ENABLED:1;
--		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
--		uint32_t TRUNCATE_DEPTH:2;
--		/* truncate or round*/
--		uint32_t TRUNCATE_MODE:1;
--
--		/* spatial dither */
--		/* Spatial Bit Depth Reduction enabled*/
--		uint32_t SPATIAL_DITHER_ENABLED:1;
--		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
--		uint32_t SPATIAL_DITHER_DEPTH:2;
--		/* 0-3 to select patterns*/
--		uint32_t SPATIAL_DITHER_MODE:2;
--		/* Enable RGB random dithering*/
--		uint32_t RGB_RANDOM:1;
--		/* Enable Frame random dithering*/
--		uint32_t FRAME_RANDOM:1;
--		/* Enable HighPass random dithering*/
--		uint32_t HIGHPASS_RANDOM:1;
--
--		/* temporal dither*/
--		 /* frame modulation enabled*/
--		uint32_t FRAME_MODULATION_ENABLED:1;
--		/* same as for trunc/spatial*/
--		uint32_t FRAME_MODULATION_DEPTH:2;
--		/* 2/4 gray levels*/
--		uint32_t TEMPORAL_LEVEL:1;
--		uint32_t FRC25:2;
--		uint32_t FRC50:2;
--		uint32_t FRC75:2;
--	} flags;
--
--	uint32_t r_seed_value;
--	uint32_t b_seed_value;
--	uint32_t g_seed_value;
--};
--
--
--
--enum wide_gamut_regamma_mode {
--	/*  0x0  - BITS2:0 Bypass */
--	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
--	/*  0x1  - Fixed curve sRGB 2.4 */
--	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24,
--	/*  0x2  - Fixed curve xvYCC 2.22 */
--	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22,
--	/*  0x3  - Programmable control A */
--	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A,
--	/*  0x4  - Programmable control B */
--	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B,
--	/*  0x0  - BITS6:4 Bypass */
--	WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS,
--	/*  0x1  - Fixed curve sRGB 2.4 */
--	WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24,
--	/*  0x2  - Fixed curve xvYCC 2.22 */
--	WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22,
--	/*  0x3  - Programmable control A */
--	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A,
--	/*  0x4  - Programmable control B */
--	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
--};
--
--struct gamma_pixel {
--	struct fixed31_32 r;
--	struct fixed31_32 g;
--	struct fixed31_32 b;
--};
--
--enum channel_name {
--	CHANNEL_NAME_RED,
--	CHANNEL_NAME_GREEN,
--	CHANNEL_NAME_BLUE
--};
--
--struct custom_float_format {
--	uint32_t mantissa_bits;
--	uint32_t exponenta_bits;
--	bool sign;
--};
--
--struct custom_float_value {
--	uint32_t mantissa;
--	uint32_t exponenta;
--	uint32_t value;
--	bool negative;
--};
--
--struct hw_x_point {
--	uint32_t custom_float_x;
--	uint32_t custom_float_x_adjusted;
--	struct fixed31_32 x;
--	struct fixed31_32 adjusted_x;
--	struct fixed31_32 regamma_y_red;
--	struct fixed31_32 regamma_y_green;
--	struct fixed31_32 regamma_y_blue;
--
--};
--
--struct pwl_float_data_ex {
--	struct fixed31_32 r;
--	struct fixed31_32 g;
--	struct fixed31_32 b;
--	struct fixed31_32 delta_r;
--	struct fixed31_32 delta_g;
--	struct fixed31_32 delta_b;
--};
--
--enum hw_point_position {
--	/* hw point sits between left and right sw points */
--	HW_POINT_POSITION_MIDDLE,
--	/* hw point lays left from left (smaller) sw point */
--	HW_POINT_POSITION_LEFT,
--	/* hw point lays stays from right (bigger) sw point */
--	HW_POINT_POSITION_RIGHT
--};
--
--struct gamma_point {
--	int32_t left_index;
--	int32_t right_index;
--	enum hw_point_position pos;
--	struct fixed31_32 coeff;
--};
--
--struct pixel_gamma_point {
--	struct gamma_point r;
--	struct gamma_point g;
--	struct gamma_point b;
--};
--
--struct gamma_coefficients {
--	struct fixed31_32 a0[3];
--	struct fixed31_32 a1[3];
--	struct fixed31_32 a2[3];
--	struct fixed31_32 a3[3];
--	struct fixed31_32 user_gamma[3];
--	struct fixed31_32 user_contrast;
--	struct fixed31_32 user_brightness;
--};
--
--struct csc_adjustments {
--	struct fixed31_32 contrast;
--	struct fixed31_32 saturation;
--	struct fixed31_32 brightness;
--	struct fixed31_32 hue;
--};
--
--struct pwl_float_data {
--	struct fixed31_32 r;
--	struct fixed31_32 g;
--	struct fixed31_32 b;
--};
--
--enum opp_regamma {
--	OPP_REGAMMA_BYPASS = 0,
--	OPP_REGAMMA_SRGB,
--	OPP_REGAMMA_3_6,
--	OPP_REGAMMA_USER,
--};
--
--struct output_pixel_processor {
--	struct dc_context *ctx;
--	uint32_t inst;
--	struct opp_funcs *funcs;
--};
--
--enum fmt_stereo_action {
--	FMT_STEREO_ACTION_ENABLE = 0,
--	FMT_STEREO_ACTION_DISABLE,
--	FMT_STEREO_ACTION_UPDATE_POLARITY
--};
--
--enum graphics_csc_adjust_type {
--	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
--	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
--	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
--};
--
--struct default_adjustment {
--	uint32_t lb_color_depth;
--	enum dc_color_space out_color_space;
--	enum dc_color_space in_color_space;
--	enum dc_color_depth color_depth;
--	enum pixel_format surface_pixel_format;
--	enum graphics_csc_adjust_type csc_adjust_type;
--	bool force_hw_default;
--};
--
--enum grph_color_adjust_option {
--	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
--	GRPH_COLOR_MATRIX_SW
--};
--
--struct opp_grph_csc_adjustment {
--	enum grph_color_adjust_option color_adjust_option;
--	enum dc_color_space c_space;
--	enum dc_color_depth color_depth; /* clean up to uint32_t */
--	enum graphics_csc_adjust_type   csc_adjust_type;
--	int32_t adjust_divider;
--	int32_t grph_cont;
--	int32_t grph_sat;
--	int32_t grph_bright;
--	int32_t grph_hue;
--};
--
--
--/* Underlay related types */
--
--struct hw_adjustment_range {
--	int32_t hw_default;
--	int32_t min;
--	int32_t max;
--	int32_t step;
--	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
--};
--
--enum ovl_csc_adjust_item {
--	OVERLAY_BRIGHTNESS = 0,
--	OVERLAY_GAMMA,
--	OVERLAY_CONTRAST,
--	OVERLAY_SATURATION,
--	OVERLAY_HUE,
--	OVERLAY_ALPHA,
--	OVERLAY_ALPHA_PER_PIX,
--	OVERLAY_COLOR_TEMPERATURE
--};
--
--struct opp_funcs {
--	void (*opp_power_on_regamma_lut)(
--		struct output_pixel_processor *opp,
--		bool power_on);
--
--	bool (*opp_program_regamma_pwl)(
--		struct output_pixel_processor *opp,
--		const struct pwl_params *params);
--
--	void (*opp_set_regamma_mode)(struct output_pixel_processor *opp,
--			enum opp_regamma mode);
--
--	void (*opp_set_csc_adjustment)(
--		struct output_pixel_processor *opp,
--		const struct opp_grph_csc_adjustment *adjust);
--
--	void (*opp_set_csc_default)(
--		struct output_pixel_processor *opp,
--		const struct default_adjustment *default_adjust);
--
--	/* FORMATTER RELATED */
--	void (*opp_program_bit_depth_reduction)(
--		struct output_pixel_processor *opp,
--		const struct bit_depth_reduction_params *params);
--
--	void (*opp_program_clamping_and_pixel_encoding)(
--		struct output_pixel_processor *opp,
--		const struct clamping_and_pixel_encoding_params *params);
--
--	void (*opp_set_dyn_expansion)(
--		struct output_pixel_processor *opp,
--		enum dc_color_space color_sp,
--		enum dc_color_depth color_dpth,
--		enum signal_type signal);
--
--	/* underlay related */
--	void (*opp_get_underlay_adjustment_range)(
--			struct output_pixel_processor *opp,
--			enum ovl_csc_adjust_item overlay_adjust_item,
--			struct hw_adjustment_range *range);
--
--
--	void (*opp_destroy)(struct output_pixel_processor **opp);
--};
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-deleted file mode 100644
-index 47cf6de..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h
-+++ /dev/null
-@@ -1,88 +0,0 @@
--/*
-- * stream_encoder.h
-- *
-- */
--
--#ifndef STREAM_ENCODER_H_
--#define STREAM_ENCODER_H_
--
--#include "include/hw_sequencer_types.h"
--
--struct dc_bios;
--struct dc_context;
--struct dc_crtc_timing;
--
--
--struct encoder_info_packet {
--	bool valid;
--	uint8_t hb0;
--	uint8_t hb1;
--	uint8_t hb2;
--	uint8_t hb3;
--	uint8_t sb[28];
--};
--
--struct encoder_info_frame {
--	/* auxiliary video information */
--	struct encoder_info_packet avi;
--	struct encoder_info_packet gamut;
--	struct encoder_info_packet vendor;
--	/* source product description */
--	struct encoder_info_packet spd;
--	/* video stream configuration */
--	struct encoder_info_packet vsc;
--};
--
--struct encoder_unblank_param {
--	struct hw_crtc_timing crtc_timing;
--	struct dc_link_settings link_settings;
--};
--
--struct encoder_set_dp_phy_pattern_param {
--	enum dp_test_pattern dp_phy_pattern;
--	const uint8_t *custom_pattern;
--	uint32_t custom_pattern_size;
--	enum dp_panel_mode dp_panel_mode;
--};
--
--
--struct stream_encoder {
--	struct stream_encoder_funcs *funcs;
--	struct dc_context *ctx;
--	struct dc_bios *bp;
--	enum engine_id id;
--};
--
--struct stream_encoder_funcs {
--	void (*dp_set_stream_attribute)(
--		struct stream_encoder *enc,
--		struct dc_crtc_timing *crtc_timing);
--	void (*hdmi_set_stream_attribute)(
--		struct stream_encoder *enc,
--		struct dc_crtc_timing *crtc_timing,
--		bool enable_audio);
--	void (*dvi_set_stream_attribute)(
--		struct stream_encoder *enc,
--		struct dc_crtc_timing *crtc_timing,
--		bool is_dual_link);
--	void (*set_mst_bandwidth)(
--		struct stream_encoder *enc,
--		struct fixed31_32 avg_time_slots_per_mtp);
--	void (*update_hdmi_info_packets)(
--		struct stream_encoder *enc,
--		const struct encoder_info_frame *info_frame);
--	void (*stop_hdmi_info_packets)(
--		struct stream_encoder *enc);
--	void (*update_dp_info_packets)(
--		struct stream_encoder *enc,
--		const struct encoder_info_frame *info_frame);
--	void (*stop_dp_info_packets)(
--		struct stream_encoder *enc);
--	void (*dp_blank)(
--		struct stream_encoder *enc);
--	void (*dp_unblank)(
--		struct stream_encoder *enc,
--		const struct encoder_unblank_param *param);
--};
--
--#endif /* STREAM_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-deleted file mode 100644
-index 374e222..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h
-+++ /dev/null
-@@ -1,153 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
--#define __DAL_TIMING_GENERATOR_TYPES_H__
--
--struct dc_bios;
--
--/**
-- *  These parameters are required as input when doing blanking/Unblanking
--*/
--struct crtc_black_color {
--	uint32_t black_color_r_cr;
--	uint32_t black_color_g_y;
--	uint32_t black_color_b_cb;
--};
--
--/* Contains CRTC vertical/horizontal pixel counters */
--struct crtc_position {
--	uint32_t vertical_count;
--	uint32_t horizontal_count;
--	uint32_t nominal_vcount;
--};
--
--
--enum dcp_gsl_purpose {
--	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
--	DCP_GSL_PURPOSE_STEREO3D_PHASE,
--	DCP_GSL_PURPOSE_UNDEFINED
--};
--
--struct dcp_gsl_params {
--	enum sync_source gsl_group;
--	enum dcp_gsl_purpose gsl_purpose;
--	bool timing_server;
--	bool overlay_present;
--	bool gsl_paused;
--};
--
--#define LEFT_EYE_3D_PRIMARY_SURFACE 1
--#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
--
--enum test_pattern_dyn_range {
--	TEST_PATTERN_DYN_RANGE_VESA = 0,
--	TEST_PATTERN_DYN_RANGE_CEA
--};
--
--enum test_pattern_mode {
--	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
--	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
--	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
--	TEST_PATTERN_MODE_VERTICALBARS,
--	TEST_PATTERN_MODE_HORIZONTALBARS,
--	TEST_PATTERN_MODE_SINGLERAMP_RGB,
--	TEST_PATTERN_MODE_DUALRAMP_RGB
--};
--
--enum test_pattern_color_format {
--	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
--	TEST_PATTERN_COLOR_FORMAT_BPC_8,
--	TEST_PATTERN_COLOR_FORMAT_BPC_10,
--	TEST_PATTERN_COLOR_FORMAT_BPC_12
--};
--
--enum controller_dp_test_pattern {
--	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
--	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
--	CONTROLLER_DP_TEST_PATTERN_PRBS7,
--	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
--	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
--	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
--	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
--	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
--	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
--	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
--};
--
--enum crtc_state {
--	CRTC_STATE_VBLANK = 0,
--	CRTC_STATE_VACTIVE
--};
--
--struct timing_generator {
--	struct timing_generator_funcs *funcs;
--	struct dc_bios *bp;
--	struct dc_context *ctx;
--};
--
--
--struct dc_crtc_timing;
--
--struct timing_generator_funcs {
--	bool (*validate_timing)(struct timing_generator *tg,
--							const struct dc_crtc_timing *timing);
--	void (*program_timing)(struct timing_generator *tg,
--							const struct dc_crtc_timing *timing,
--							bool use_vbios);
--	bool (*enable_crtc)(struct timing_generator *tg);
--	bool (*disable_crtc)(struct timing_generator *tg);
--	bool (*is_counter_moving)(struct timing_generator *tg);
--	void (*get_position)(struct timing_generator *tg,
--								int32_t *h_position,
--								int32_t *v_position);
--	uint32_t (*get_frame_count)(struct timing_generator *tg);
--	void (*set_early_control)(struct timing_generator *tg,
--							   uint32_t early_cntl);
--	void (*wait_for_state)(struct timing_generator *tg,
--							enum crtc_state state);
--	bool (*set_blank)(struct timing_generator *tg,
--					   bool enable_blanking);
--	void (*set_overscan_blank_color) (struct timing_generator *tg, enum dc_color_space black_color);
--	void (*set_blank_color)(struct timing_generator *tg, enum dc_color_space black_color);
--	void (*set_colors)(struct timing_generator *tg,
--						const struct crtc_black_color *blank_color,
--						const struct crtc_black_color *overscan_color);
--
--	void (*disable_vga)(struct timing_generator *tg);
--	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
--	void (*setup_global_swap_lock)(struct timing_generator *tg,
--							const struct dcp_gsl_params *gsl_params);
--	void (*enable_reset_trigger)(struct timing_generator *tg,
--						const struct trigger_params *trigger_params);
--	void (*disable_reset_trigger)(struct timing_generator *tg);
--	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
--	void (*enable_advanced_request)(struct timing_generator *tg,
--					bool enable, const struct dc_crtc_timing *timing);
--};
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-deleted file mode 100644
-index bf84f96..0000000
---- a/drivers/gpu/drm/amd/dal/dc/inc/transform.h
-+++ /dev/null
-@@ -1,192 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_TRANSFORM_H__
--#define __DAL_TRANSFORM_H__
--
--#include "include/scaler_types.h"
--#include "calcs/scaler_filter.h"
--
--struct bit_depth_reduction_params;
--
--struct transform {
--	struct transform_funcs *funcs;
--	struct dc_context *ctx;
--	uint32_t inst;
--	struct scaler_filter *filter;
--};
--
--enum lb_pixel_depth {
--	/* do not change the values because it is used as bit vector */
--	LB_PIXEL_DEPTH_18BPP = 1,
--	LB_PIXEL_DEPTH_24BPP = 2,
--	LB_PIXEL_DEPTH_30BPP = 4,
--	LB_PIXEL_DEPTH_36BPP = 8
--};
--
--
--enum raw_gamma_ramp_type {
--       GAMMA_RAMP_TYPE_UNINITIALIZED,
--       GAMMA_RAMP_TYPE_DEFAULT,
--       GAMMA_RAMP_TYPE_RGB256,
--       GAMMA_RAMP_TYPE_FIXED_POINT
--};
--
--#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
--
--/* Colorimetry */
--enum colorimetry {
--       COLORIMETRY_NO_DATA = 0,
--       COLORIMETRY_ITU601 = 1,
--       COLORIMETRY_ITU709 = 2,
--       COLORIMETRY_EXTENDED = 3
--};
--
--enum ds_color_space {
--       DS_COLOR_SPACE_UNKNOWN = 0,
--       DS_COLOR_SPACE_SRGB_FULLRANGE = 1,
--       DS_COLOR_SPACE_SRGB_LIMITEDRANGE,
--       DS_COLOR_SPACE_YPBPR601,
--       DS_COLOR_SPACE_YPBPR709,
--       DS_COLOR_SPACE_YCBCR601,
--       DS_COLOR_SPACE_YCBCR709,
--       DS_COLOR_SPACE_NMVPU_SUPERAA,
--       DS_COLOR_SPACE_YCBCR601_YONLY,
--       DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/
--};
--
--enum active_format_info {
--       ACTIVE_FORMAT_NO_DATA = 0,
--       ACTIVE_FORMAT_VALID = 1
--};
--
--/* Active format aspect ratio */
--enum active_format_aspect_ratio {
--       ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
--       ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
--       ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
--       ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
--};
--
--enum bar_info {
--       BAR_INFO_NOT_VALID = 0,
--       BAR_INFO_VERTICAL_VALID = 1,
--       BAR_INFO_HORIZONTAL_VALID = 2,
--       BAR_INFO_BOTH_VALID = 3
--};
--
--enum picture_scaling {
--       PICTURE_SCALING_UNIFORM = 0,
--       PICTURE_SCALING_HORIZONTAL = 1,
--       PICTURE_SCALING_VERTICAL = 2,
--       PICTURE_SCALING_BOTH = 3
--};
--
--/* RGB quantization range */
--enum rgb_quantization_range {
--       RGB_QUANTIZATION_DEFAULT_RANGE = 0,
--       RGB_QUANTIZATION_LIMITED_RANGE = 1,
--       RGB_QUANTIZATION_FULL_RANGE = 2,
--       RGB_QUANTIZATION_RESERVED = 3
--};
--
--/* YYC quantization range */
--enum yyc_quantization_range {
--       YYC_QUANTIZATION_LIMITED_RANGE = 0,
--       YYC_QUANTIZATION_FULL_RANGE = 1,
--       YYC_QUANTIZATION_RESERVED2 = 2,
--       YYC_QUANTIZATION_RESERVED3 = 3
--};
--
--enum graphics_gamut_adjust_type {
--	GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
--	GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
--	GRAPHICS_GAMUT_ADJUST_TYPE_SW  /* use adjustments */
--};
--
--#define CSC_TEMPERATURE_MATRIX_SIZE 9
--
--struct xfm_grph_csc_adjustment {
--	int32_t temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
--	int32_t temperature_divider;
--	enum graphics_gamut_adjust_type gamut_adjust_type;
--};
--
--/*overscan or window*/
--struct overscan_info {
--	uint32_t left;
--	uint32_t right;
--	uint32_t top;
--	uint32_t bottom;
--};
--
--struct scaling_ratios {
--	struct fixed31_32 horz;
--	struct fixed31_32 vert;
--	struct fixed31_32 horz_c;
--	struct fixed31_32 vert_c;
--};
--
--struct scaler_data {
--	struct overscan_info overscan;
--	struct scaling_taps taps;
--	struct rect viewport;
--	struct scaling_ratios ratios;
--
--	enum pixel_format format;
--};
--
--struct transform_funcs {
--	bool (*transform_power_up)(
--		struct transform *xfm);
--
--	bool (*transform_set_scaler)(
--		struct transform *xfm,
--		const struct scaler_data *data);
--
--	void (*transform_set_scaler_bypass)(
--		struct transform *xfm);
--
--	void (*transform_set_scaler_filter)(
--		struct transform *xfm,
--		struct scaler_filter *filter);
--
--	void (*transform_set_gamut_remap)(
--		struct transform *xfm,
--		const struct xfm_grph_csc_adjustment *adjust);
--
--	bool (*transform_set_pixel_storage_depth)(
--		struct transform *xfm,
--		enum lb_pixel_depth depth,
--		const struct bit_depth_reduction_params *bit_depth_params);
--
--	bool (*transform_get_current_pixel_storage_depth)(
--		struct transform *xfm,
--		enum lb_pixel_depth *depth);
--
--	void (*transform_set_alpha)(struct transform *xfm, bool enable);
--};
--
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-index c34bd04..e44713f 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_VIRTUAL_LINK_ENCODER_H__
- #define __DC_VIRTUAL_LINK_ENCODER_H__
- 
--#include "inc/link_encoder.h"
-+#include "link_encoder.h"
- 
- bool virtual_link_encoder_construct(
- 	struct link_encoder *enc, const struct encoder_init_data *init_data);
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
-index dce8425..bf3422c 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
-@@ -26,7 +26,7 @@
- #ifndef __DC_VIRTUAL_STREAM_ENCODER_H__
- #define __DC_VIRTUAL_STREAM_ENCODER_H__
- 
--#include "inc/stream_encoder.h"
-+#include "stream_encoder.h"
- 
- struct stream_encoder *virtual_stream_encoder_create(
- 	struct dc_context *ctx, struct dc_bios *bp);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0852-drm-amd-dal-Fix-mem-input-build-error.patch b/common/recipes-kernel/linux/files/0852-drm-amd-dal-Fix-mem-input-build-error.patch
deleted file mode 100644
index e772596f..00000000
--- a/common/recipes-kernel/linux/files/0852-drm-amd-dal-Fix-mem-input-build-error.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 66981b673861e1800492d2f2e985793310cbc54b Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 14:17:09 -0500
-Subject: [PATCH 0852/1110] drm/amd/dal: Fix mem input build error
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 5 -----
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h | 5 -----
- 2 files changed, 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-index a8e9961..86a79b2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-@@ -22,10 +22,6 @@
-  * Authors: AMD
-  *
-  */
--#ifndef __DC_MEM_INPUT_DCE80_H__
--
--#define __DC_MEM_INPUT_DCE80_H__
--
- #include "dm_services.h"
- 
- #include "dce/dce_8_0_d.h"
-@@ -214,4 +210,3 @@ bool dce80_mem_input_construct(
- 	return true;
- }
- 
--#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-index f07e94a..357b9e2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
-@@ -33,9 +33,4 @@ bool dce80_mem_input_construct(
- 	uint32_t inst,
- 	const struct dce110_mem_input_reg_offsets *offsets);
- 
--
--enum dc_status dce_base_validate_mapped_resource(
--		const struct dc *dc,
--		struct validate_context *context);
--
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0853-drm-amd-dal-Fix-amdgpu-build-error.patch b/common/recipes-kernel/linux/files/0853-drm-amd-dal-Fix-amdgpu-build-error.patch
deleted file mode 100644
index 6ac479de..00000000
--- a/common/recipes-kernel/linux/files/0853-drm-amd-dal-Fix-amdgpu-build-error.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From cff034e456966c1fa24c767781feeff6ae5e1bb2 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 14:18:30 -0500
-Subject: [PATCH 0853/1110] drm/amd/dal: Fix amdgpu build error
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 6902861..0f60db4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -204,7 +204,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
- {
- 	struct common_irq_params *irq_params = interrupt_params;
- 	struct amdgpu_device *adev = irq_params->adev;
--	const struct dc *dc = irq_params->adev->dm.dc;
-+	const struct core_dc *dc = irq_params->adev->dm.dc;
- 	const struct dc_target *dc_target =
- 			dc_get_target_on_irq_source(dc, irq_params->irq_src);
- 	uint8_t crtc_index = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0854-drm-amd-dal-Remove-ctx-from-dm_alloc-free.patch b/common/recipes-kernel/linux/files/0854-drm-amd-dal-Remove-ctx-from-dm_alloc-free.patch
deleted file mode 100644
index 8f9cd058..00000000
--- a/common/recipes-kernel/linux/files/0854-drm-amd-dal-Remove-ctx-from-dm_alloc-free.patch
+++ /dev/null
@@ -1,6190 +0,0 @@
-From 8820504bbbbfd950f080208b481806ff2275e082 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Mon, 22 Feb 2016 14:10:19 -0500
-Subject: [PATCH 0854/1110] drm/amd/dal: Remove ctx from dm_alloc/free
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |  9 ---
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h      |  1 -
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  |  2 -
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c  |  3 -
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  3 -
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 27 +-------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  5 --
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |  1 -
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   | 15 +---
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h   |  1 -
- .../adapter/dce110/hw_ctx_adapter_service_dce110.c |  8 +--
- .../adapter/dce110/hw_ctx_adapter_service_dce110.h |  1 -
- .../adapter/dce80/hw_ctx_adapter_service_dce80.c   |  6 +-
- .../adapter/dce80/hw_ctx_adapter_service_dce80.h   |  1 -
- .../diagnostics/hw_ctx_adapter_service_diag.c      |  5 +-
- .../diagnostics/hw_ctx_adapter_service_diag.h      |  1 -
- .../drm/amd/dal/dc/adapter/wireless_data_source.h  |  1 -
- .../amd/dal/dc/asic_capability/asic_capability.c   |  6 +-
- .../dc/asic_capability/carrizo_asic_capability.c   |  1 -
- .../dc/asic_capability/hawaii_asic_capability.c    |  2 -
- .../dal/dc/asic_capability/tonga_asic_capability.c |  2 -
- drivers/gpu/drm/amd/dal/dc/audio/audio.h           |  2 -
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c |  8 +--
- .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h |  2 -
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c  | 15 +---
- .../gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c   |  8 +--
- .../gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h   |  1 -
- .../amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c    | 40 +----------
- .../amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h    |  3 -
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c    | 11 ---
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h    |  7 --
- drivers/gpu/drm/amd/dal/dc/basics/conversion.c     |  1 -
- drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c     |  2 -
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         | 39 +++--------
- drivers/gpu/drm/amd/dal/dc/basics/logger.h         |  1 -
- drivers/gpu/drm/amd/dal/dc/basics/vector.c         | 20 +++---
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 24 +++----
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    |  5 --
- .../dc/bios/dce110/command_table_helper_dce110.c   |  1 -
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   |  1 -
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 10 ++-
- drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c        |  2 -
- drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c     |  3 -
- drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c   | 63 +++++++----------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 37 ++++------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          | 15 +---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      | 25 +++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 13 +---
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  2 -
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  7 --
- drivers/gpu/drm/amd/dal/dc/core/dc_sink.c          |  9 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |  7 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       | 14 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  4 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  4 --
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |  1 -
- drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h          |  1 -
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h           |  1 -
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  3 -
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |  1 -
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 81 +++++++++-------------
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.h    |  1 -
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    | 19 ++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c  |  9 +--
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 23 ++----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     |  1 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c  |  1 -
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.h    |  1 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  7 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h   |  2 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c |  7 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h |  1 -
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c     |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h     |  1 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c |  1 -
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c   |  3 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 66 ++++++++----------
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |  4 --
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |  4 --
- .../amd/dal/dc/dce110/dce110_timing_generator_v.c  |  4 --
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c   |  2 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c |  8 ---
- .../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c    |  9 +--
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |  2 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c       |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h       |  2 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c |  9 ---
- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c  |  1 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c |  1 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c       |  8 +--
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h       |  1 -
- .../gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c   |  1 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 51 ++++++--------
- .../drm/amd/dal/dc/dce80/dce80_stream_encoder.h    |  1 -
- .../drm/amd/dal/dc/dce80/dce80_timing_generator.h  |  3 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h |  1 -
- drivers/gpu/drm/amd/dal/dc/dm_services.h           | 12 +---
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h     |  1 -
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c |  7 +-
- .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c |  6 +-
- .../gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c   |  6 +-
- .../gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c   |  7 +-
- drivers/gpu/drm/amd/dal/dc/gpio/ddc.c              |  6 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c  |  6 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c  |  7 +-
- .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h  |  1 -
- .../dal/dc/gpio/diagnostics/hw_translate_diag.c    |  1 -
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c        |  4 +-
- drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c     | 14 ++--
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |  2 +-
- drivers/gpu/drm/amd/dal/dc/gpio/irq.c              |  6 +-
- .../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c |  1 -
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |  9 +--
- .../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 12 +---
- drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h     |  1 -
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c   |  7 +-
- .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c    | 11 +--
- .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c    |  6 +-
- .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c   |  6 +-
- .../drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c |  8 +--
- .../amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c  |  8 +--
- .../amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c  |  8 +--
- .../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c |  7 +-
- .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c    |  8 +--
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c  |  8 +--
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  3 -
- drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h          |  1 -
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  3 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h            |  2 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h            |  4 --
- drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h |  2 -
- .../gpu/drm/amd/dal/dc/inc/hw/timing_generator.h   |  2 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h      |  1 -
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  3 -
- .../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c |  4 +-
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |  2 +-
- drivers/gpu/drm/amd/dal/dc/irq_types.h             |  1 -
- .../drm/amd/dal/dc/virtual/virtual_link_encoder.h  |  1 -
- .../amd/dal/dc/virtual/virtual_stream_encoder.c    |  4 +-
- .../amd/dal/include/adapter_service_interface.h    |  3 -
- .../amd/dal/include/asic_capability_interface.h    |  2 -
- .../drm/amd/dal/include/asic_capability_types.h    |  4 --
- drivers/gpu/drm/amd/dal/include/audio_interface.h  |  2 -
- drivers/gpu/drm/amd/dal/include/audio_types.h      |  2 -
- drivers/gpu/drm/amd/dal/include/dal_asic_id.h      |  1 -
- .../gpu/drm/amd/dal/include/dal_register_logger.h  |  1 -
- .../gpu/drm/amd/dal/include/ddc_service_types.h    |  2 -
- .../drm/amd/dal/include/display_clock_interface.h  |  1 -
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h        |  1 -
- drivers/gpu/drm/amd/dal/include/fixed31_32.h       |  1 -
- drivers/gpu/drm/amd/dal/include/gpio_types.h       |  1 -
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    |  2 -
- drivers/gpu/drm/amd/dal/include/grph_object_defs.h |  1 -
- drivers/gpu/drm/amd/dal/include/grph_object_id.h   |  3 -
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |  4 --
- drivers/gpu/drm/amd/dal/include/i2caux_interface.h |  1 -
- drivers/gpu/drm/amd/dal/include/logger_interface.h |  1 -
- drivers/gpu/drm/amd/dal/include/logger_types.h     |  3 -
- drivers/gpu/drm/amd/dal/include/set_mode_types.h   |  3 -
- 160 files changed, 311 insertions(+), 803 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 0f60db4..257969f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -382,7 +382,6 @@ static int dm_sw_fini(void *handle)
- 	return 0;
- }
- 
--
- static void detect_link_for_all_connectors(struct drm_device *dev)
- {
- 	struct amdgpu_connector *aconnector;
-@@ -406,7 +405,6 @@ static void detect_link_for_all_connectors(struct drm_device *dev)
- 	drm_modeset_unlock(&dev->mode_config.connection_mutex);
- }
- 
--
- static int dm_hw_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -417,8 +415,6 @@ static int dm_hw_init(void *handle)
- 
- 	detect_link_for_all_connectors(adev->ddev);
- 
--
--
- 	return 0;
- }
- 
-@@ -601,7 +597,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 		amdgpu_dm_update_connector_after_detect(aconnector);
- 	}
- 
--
- 	drm_modeset_lock_all(ddev);
- 	ret = dm_display_resume(ddev);
- 	drm_modeset_unlock_all(ddev);
-@@ -639,7 +634,6 @@ static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
- 	.atomic_commit = amdgpu_dm_atomic_commit
- };
- 
--
- void amdgpu_dm_update_connector_after_detect(
- 	struct amdgpu_connector *aconnector)
- {
-@@ -1276,12 +1270,9 @@ static int dm_early_init(void *handle)
- 	 * adev->audio_endpt_wreg because they are initialised in
- 	 * amdgpu_device_init() */
- 
--
--
- 	return 0;
- }
- 
--
- bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm)
- {
- 	/* TODO */
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 0da8530..4f3bf97 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -128,7 +128,6 @@ struct amdgpu_display_manager {
- 	struct work_struct mst_hotplug_work;
- };
- 
--
- /* basic init/fini API */
- int amdgpu_dm_init(struct amdgpu_device *adev);
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index 17240e0..e442318 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -164,7 +164,6 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
--
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static void get_payload_table(
- 		struct amdgpu_connector *aconnector,
-@@ -469,7 +468,6 @@ bool dm_helpers_dp_read_dpcd(
- 		uint32_t size)
- {
- 
--
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index d04ed18..2757c5c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -32,7 +32,6 @@
- #include "amdgpu_dm.h"
- #include "amdgpu_dm_irq.h"
- 
--
- /******************************************************************************
-  * Private declarations.
-  *****************************************************************************/
-@@ -57,7 +56,6 @@ struct amdgpu_dm_timer_handler_data {
- 	struct delayed_work d_work;
- };
- 
--
- #define DM_IRQ_TABLE_LOCK(adev, flags) \
- 	spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
- 
-@@ -548,7 +546,6 @@ int amdgpu_dm_irq_resume(
- 	return 0;
- }
- 
--
- /**
-  * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
-  * "irq_source".
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index a8b489f..6876643 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -33,7 +33,6 @@
- #include "dc.h"
- #include "dm_helpers.h"
- 
--
- /* #define TRACE_DPCD */
- 
- #ifdef TRACE_DPCD
-@@ -342,7 +341,6 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_
- 	}
- 	drm_modeset_unlock(&dev->mode_config.connection_mutex);
- 
--
- 	aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
- 	if (!aconnector)
- 		return NULL;
-@@ -459,7 +457,6 @@ struct drm_dp_mst_topology_cbs dm_mst_cbs = {
- };
- #endif
- 
--
- void amdgpu_dm_initialize_mst_connector(
- 	struct amdgpu_display_manager *dm,
- 	struct amdgpu_connector *aconnector)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index 116d34d..26208eb 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -36,35 +36,15 @@
- #include "amdgpu_dm_types.h"
- #include "amdgpu_pm.h"
- 
--/*
--#include "logger_interface.h"
--#include "acpimethod_atif.h"
--#include "amdgpu_powerplay.h"
--#include "amdgpu_notifications.h"
--*/
--
--/* if the pointer is not NULL, the allocated memory is zeroed */
--void *dm_alloc(struct dc_context *ctx, uint32_t size)
--{
--	return kzalloc(size, GFP_KERNEL);
--}
--
--/* Reallocate memory. The contents will remain unchanged.*/
--void *dm_realloc(struct dc_context *ctx, const void *ptr, uint32_t size)
--{
--	return krealloc(ptr, size, GFP_KERNEL);
--}
-+#define dm_alloc(size) kzalloc(size, GFP_KERNEL)
-+#define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
-+#define dm_free(ptr) kfree(ptr)
- 
- void dm_memmove(void *dst, const void *src, uint32_t size)
- {
- 	memmove(dst, src, size);
- }
- 
--void dm_free(struct dc_context *ctx, void *p)
--{
--	kfree(p);
--}
--
- void dm_memset(void *p, int32_t c, uint32_t count)
- {
- 	memset(p, c, count);
-@@ -432,7 +412,6 @@ bool dm_pp_get_clock_levels_by_type(
- 
- /**** end of power component interfaces ****/
- 
--
- /* Calls to notification */
- 
- void dal_notify_setmode_complete(struct dc_context *ctx,
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index f8c423a..1c767f3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -397,7 +397,6 @@ static bool get_fb_info(
- 		return false;
- 	}
- 
--
- 	if (fb_location)
- 		*fb_location = amdgpu_bo_gpu_offset(rbo);
- 
-@@ -453,7 +452,6 @@ static void fill_plane_attributes_from_fb(
- 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
- 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
- 
--
- 		/* XXX fix me for VI */
- 		surface->tiling_info.num_banks = num_banks;
- 		surface->tiling_info.array_mode =
-@@ -848,7 +846,6 @@ static void decide_crtc_timing_for_drm_display_mode(
- 	}
- }
- 
--
- static struct dc_target *create_target_for_sink(
- 		const struct amdgpu_connector *aconnector,
- 		struct drm_display_mode *drm_mode)
-@@ -1282,7 +1279,6 @@ stream_create_fail:
- 	return result;
- }
- 
--
- static const struct drm_connector_helper_funcs
- amdgpu_dm_connector_helper_funcs = {
- 	/*
-@@ -2598,7 +2594,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 		}
- 	}
- 
--
- 	for (i = 0; i < set_count; i++) {
- 		for_each_plane_in_state(state, plane, plane_state, j) {
- 			struct drm_plane_state *old_plane_state = plane->state;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 0481075..2cf7cd2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -23,7 +23,6 @@
-  *
-  */
- 
--
- #ifndef __AMDGPU_DM_TYPES_H__
- #define __AMDGPU_DM_TYPES_H__
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 0fd1050..99ba0c7 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -179,7 +179,6 @@ static struct feature_source_entry feature_entry_table[] = {
- 	{FEATURE_8BPP_SUPPORTED, false, true}
- };
- 
--
- /* Stores entire ASIC features by sets */
- uint32_t adapter_feature_set[FEATURE_MAXIMUM/32];
- 
-@@ -210,7 +209,6 @@ static void get_platform_info_methods(
- 	if (dm_get_platform_info(as->ctx, &params))
- 		as->platform_methods_mask = mask;
- 
--
- }
- 
- static void initialize_backlight_caps(
-@@ -602,7 +600,6 @@ static bool generate_feature_set(
- 	dm_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
- 	entry_num = get_feature_entries_num();
- 
--
- 	while (i != entry_num) {
- 		entry = &feature_entry_table[i];
- 
-@@ -641,7 +638,6 @@ static bool generate_feature_set(
- 	return true;
- }
- 
--
- /*
-  * create_hw_ctx
-  *
-@@ -845,7 +841,7 @@ struct adapter_service *dal_adapter_service_create(
- {
- 	struct adapter_service *as;
- 
--	as = dm_alloc(init_data->ctx, sizeof(struct adapter_service));
-+	as = dm_alloc(sizeof(struct adapter_service));
- 
- 	if (!as) {
- 		ASSERT_CRITICAL(false);
-@@ -857,7 +853,7 @@ struct adapter_service *dal_adapter_service_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(init_data->ctx, as);
-+	dm_free(as);
- 
- 	return NULL;
- }
-@@ -882,7 +878,7 @@ void dal_adapter_service_destroy(
- 
- 	adapter_service_destruct(*as);
- 
--	dm_free((*as)->ctx, *as);
-+	dm_free(*as);
- 
- 	*as = NULL;
- }
-@@ -923,7 +919,6 @@ enum dce_environment dal_adapter_service_get_dce_environment(
- 	return as->dce_environment;
- }
- 
--
- /*
-  * dal_adapter_service_get_controllers_num
-  *
-@@ -1257,7 +1252,6 @@ struct ddc *dal_adapter_service_obtain_ddc(
- 	struct graphics_object_i2c_info i2c_info;
- 	struct gpio_ddc_hw_info hw_info;
- 
--
- 	if (!dal_adapter_service_get_i2c_info(as, id, &i2c_info))
- 		return NULL;
- 
-@@ -1451,7 +1445,6 @@ struct asic_bugs dal_adapter_service_get_asic_bugs(
- 	return as->asic_cap->bugs;
- }
- 
--
- struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
- 		struct adapter_service *as)
- {
-@@ -1754,7 +1747,6 @@ struct graphics_object_id dal_adapter_service_enum_audio_object(
- 	return as->hw_ctx->funcs->enum_audio_object(as->hw_ctx, index);
- }
- 
--
- void dal_adapter_service_update_audio_connectivity(
- 	struct adapter_service *as,
- 	uint32_t number_of_audio_capable_display_path)
-@@ -2015,7 +2007,6 @@ bool dal_adapter_service_get_panel_backlight_boundaries(
- 	return false;
- }
- 
--
- uint32_t dal_adapter_service_get_view_port_pixel_granularity(
- 	struct adapter_service *as)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-index 60464e8..7cc8991 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -37,7 +37,6 @@
- struct gpio_service;
- struct asic_cap;
- 
--
- /* Adapter service */
- struct adapter_service {
- 	struct dc_context *ctx;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-index f10bee6..73eb816 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c
-@@ -87,7 +87,7 @@ static void destroy(
- 
- 	destruct(hw_ctx);
- 
--	dm_free(ptr->ctx, hw_ctx);
-+	dm_free(hw_ctx);
- }
- 
- /*
-@@ -191,7 +191,6 @@ static uint32_t get_number_of_connected_audio_endpoints(
- 	return field;
- }
- 
--
- /*
-  * power_up
-  *
-@@ -212,7 +211,6 @@ static bool power_up(
- 	/* Allow DP audio all the time
- 	 * without additional pinstrap check on Fusion */
- 
--
- 	{
- 		uint32_t value = 0;
- 		uint32_t field = 0;
-@@ -286,7 +284,7 @@ struct hw_ctx_adapter_service *
- 			struct dc_context *ctx)
- {
- 	struct hw_ctx_adapter_service_dce110 *hw_ctx =
--			dm_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce110));
-+			dm_alloc(sizeof(struct hw_ctx_adapter_service_dce110));
- 
- 	if (!hw_ctx) {
- 		ASSERT_CRITICAL(false);
-@@ -298,7 +296,7 @@ struct hw_ctx_adapter_service *
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, hw_ctx);
-+	dm_free(hw_ctx);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-index 092b671..72b2103 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h
-@@ -37,4 +37,3 @@ struct hw_ctx_adapter_service *
- 
- #endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DCE110_H__ */
- 
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c
-index 9d6505c..95d0d00 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.c
-@@ -89,7 +89,7 @@ static void destroy(
- 
- 	destruct(hw_ctx);
- 
--	dm_free(ptr->ctx, hw_ctx);
-+	dm_free(hw_ctx);
- }
- 
- static uint32_t get_number_of_connected_audio_endpoints_multistream(
-@@ -304,7 +304,7 @@ struct hw_ctx_adapter_service *
- 	dal_adapter_service_create_hw_ctx_dce80(struct dc_context *ctx)
- {
- 	struct hw_ctx_adapter_service_dce80 *hw_ctx =
--			dm_alloc(ctx, sizeof(struct hw_ctx_adapter_service_dce80));
-+			dm_alloc(sizeof(struct hw_ctx_adapter_service_dce80));
- 
- 	if (!hw_ctx) {
- 		BREAK_TO_DEBUGGER();
-@@ -316,7 +316,7 @@ struct hw_ctx_adapter_service *
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, hw_ctx);
-+	dm_free(hw_ctx);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h
-index a735eaf..9fddbe0 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce80/hw_ctx_adapter_service_dce80.h
-@@ -37,4 +37,3 @@ struct hw_ctx_adapter_service *
- 
- #endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DCE80_H__ */
- 
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-index 4f5f040..363564f 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c
-@@ -112,8 +112,7 @@ static bool construct(
- struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
- 	struct dc_context *ctx)
- {
--	struct hw_ctx_adapter_service *hw_ctx = dm_alloc(ctx,
--			sizeof(*hw_ctx));
-+	struct hw_ctx_adapter_service *hw_ctx = dm_alloc(sizeof(*hw_ctx));
- 
- 	if (!hw_ctx) {
- 		ASSERT_CRITICAL(false);
-@@ -125,7 +124,7 @@ struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, hw_ctx);
-+	dm_free(hw_ctx);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h
-index 39ae752..d939bef 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h
-@@ -26,7 +26,6 @@
- #ifndef __DAL_HW_CTX_ADAPTER_SERVICE_DIAG_H__
- #define __DAL_HW_CTX_ADAPTER_SERVICE_DIAG_H__
- 
--
- struct hw_ctx_adapter_service *dal_adapter_service_create_hw_ctx_diag(
- 		struct dc_context *ctx);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-index b64089e..972ada8 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
-@@ -51,7 +51,6 @@ struct wireless_data {
- 	bool miracast_connector_enable;
- };
- 
--
- /*construct wireless data*/
- bool wireless_data_init(
- 	struct wireless_data *data,
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index 69909dd..f7fa96c 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -155,7 +155,7 @@ struct asic_capability *dal_asic_capability_create(
- 		return NULL;
- 	}
- 
--	cap = dm_alloc(ctx, sizeof(struct asic_capability));
-+	cap = dm_alloc(sizeof(struct asic_capability));
- 
- 	if (!cap) {
- 		BREAK_TO_DEBUGGER();
-@@ -167,7 +167,7 @@ struct asic_capability *dal_asic_capability_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, cap);
-+	dm_free(cap);
- 
- 	return NULL;
- }
-@@ -192,7 +192,7 @@ void dal_asic_capability_destroy(
- 
- 	destruct(*cap);
- 
--	dm_free((*cap)->ctx, *cap);
-+	dm_free(*cap);
- 
- 	*cap = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-index 4aa8c30..4f2e6b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
-@@ -143,5 +143,4 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
- 
- 	}
- 
--
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
-index 2745ac1..2913e57 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
-@@ -41,7 +41,6 @@
- #include "dce/dce_8_0_d.h"
- #include "gmc/gmc_7_1_d.h"
- 
--
- /*
-  * Sea Islands (CI) ASIC capability.
-  *
-@@ -124,7 +123,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
- 	/* Report headless if no OPM attached (with MXM connectors present). */
- 	cap->caps.HEADLESS_NO_OPM_SUPPORTED = true;
- 
--
- 	cap->caps.HPD_CHECK_FOR_EDID = true;
- 	cap->caps.NO_VCC_OFF_HPD_POLLING = true;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-index af669c8..880820c 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
-@@ -70,7 +70,6 @@ void tonga_asic_capability_create(struct asic_capability *cap,
- 	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
- 	cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
- 
--
- 	/* ASIC basic capability */
- 	cap->caps.IS_FUSION = true;
- 	cap->caps.DP_MST_SUPPORTED = true;
-@@ -142,5 +141,4 @@ void tonga_asic_capability_create(struct asic_capability *cap,
- 		break;
- 	}
- 
--
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio.h b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-index ad2dc18..7ca71eb 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-@@ -191,5 +191,3 @@ void dal_audio_release_hw_base(
- 
- #endif  /* __DAL_AUDIO__ */
- 
--
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-index 1aa0c1e..9f311b2 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
-@@ -53,11 +53,10 @@ static void destroy(struct audio **ptr)
- 	destruct(audio);
- 
- 	/* release memory allocated for audio_dce110*/
--	dm_free((*ptr)->ctx, audio);
-+	dm_free(audio);
- 	*ptr = NULL;
- }
- 
--
- /* The inital call of hook function comes from audio object level.
-  *The passing object handle "struct audio *audio" point to base object
-  *already.There is not need to get base object from audio_dce110.
-@@ -419,14 +418,13 @@ static bool construct(
- 	return true;
- }
- 
--
- /* --- audio scope functions  --- */
- 
- struct audio *dal_audio_create_dce110(
- 	const struct audio_init_data *init_data)
- {
- 	/*allocate memory for audio_dce110 */
--	struct audio_dce110 *audio = dm_alloc(init_data->ctx, sizeof(*audio));
-+	struct audio_dce110 *audio = dm_alloc(sizeof(*audio));
- 
- 	if (audio == NULL) {
- 		ASSERT_CRITICAL(audio);
-@@ -443,7 +441,7 @@ struct audio *dal_audio_create_dce110(
- 		"Failed to create audio object for DCE11\n");
- 
- 	 /*release memory allocated if fail */
--	dm_free(init_data->ctx, audio);
-+	dm_free(audio);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-index e5ff823..efd441e 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
-@@ -29,8 +29,6 @@
- #include "audio/hw_ctx_audio.h"
- #include "audio/dce110/hw_ctx_audio_dce110.h"
- 
--
--
- struct audio_dce110 {
- 	struct audio base;
- 	/* dce-specific members are following */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-index 50f2e66..64d3dbf 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -73,7 +73,7 @@ static void destroy(
- 
- 	destruct(hw_ctx_dce110);
- 	/* release memory allocated for struct hw_ctx_audio_dce110 */
--	dm_free((*ptr)->ctx, hw_ctx_dce110);
-+	dm_free(hw_ctx_dce110);
- 
- 	*ptr = NULL;
- }
-@@ -128,7 +128,6 @@ static uint32_t read_indirect_azalia_reg(
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 
--
- 	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
- 	{
- 		addr =
-@@ -238,7 +237,6 @@ static void set_video_latency(
- 	if ((latency_in_ms < 0) || (latency_in_ms > 255))
- 		return;
- 
--
- 	value = read_indirect_azalia_reg(
- 		hw_ctx,
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-@@ -775,7 +773,6 @@ static void setup_dp_audio(
- 	/* --- The following are the registers
- 	 *  copied from the SetupHDMI --- */
- 
--
- 	/* AFMT_AUDIO_PACKET_CONTROL */
- 	{
- 		addr = mmAFMT_AUDIO_PACKET_CONTROL +
-@@ -1269,7 +1266,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
- 		value);
- 
--
- 	value = 0;
- 
- 	/*get display name string length */
-@@ -1287,7 +1283,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
- 		value);
- 
--
- 	/*
- 	*write the port ID:
- 	*PORT_ID0 = display index
-@@ -1340,7 +1335,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
- 		value);
- 
--
- 	value = 0;
- 	set_reg_field_value(value, audio_info->display_name[4],
- 		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-@@ -1407,7 +1401,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
- 		value);
- 
--
- 	value = 0;
- 	set_reg_field_value(value, audio_info->display_name[16],
- 		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-@@ -1526,7 +1519,6 @@ static void setup_channel_splitting_mapping(
- 	if ((audio_mapping == NULL || audio_mapping->u32all == 0) && enable)
- 		return;
- 
--
- 	value = audio_mapping->u32all;
- 
- 	if (enable == false)
-@@ -1907,7 +1899,7 @@ struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
- {
- 	/* allocate memory for struc hw_ctx_audio_dce110 */
- 	struct hw_ctx_audio_dce110 *hw_ctx_dce110 =
--			dm_alloc(ctx, sizeof(struct hw_ctx_audio_dce110));
-+			dm_alloc(sizeof(struct hw_ctx_audio_dce110));
- 
- 	if (!hw_ctx_dce110) {
- 		ASSERT_CRITICAL(hw_ctx_dce110);
-@@ -1925,8 +1917,7 @@ struct hw_ctx_audio *dal_hw_ctx_audio_dce110_create(
- 		LOG_MINOR_COMPONENT_AUDIO,
- 		"Failed to create hw_ctx_audio for DCE11\n");
- 
--
--	dm_free(ctx, hw_ctx_dce110);
-+	dm_free(hw_ctx_dce110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c
-index d6f437c..8b9ad02 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.c
-@@ -53,11 +53,10 @@ static void destroy(struct audio **ptr)
- 	destruct(audio);
- 
- 	/* release memory allocated for audio_dce80*/
--	dm_free(audio->base.ctx, audio);
-+	dm_free(audio);
- 	*ptr = NULL;
- }
- 
--
- /* The inital call of hook function comes from audio object level.
-  *The passing object handle "struct audio *audio" point to base object
-  *already.There is not need to get base object from audio_dce80.
-@@ -407,14 +406,13 @@ static bool construct(
- 	return true;
- }
- 
--
- /* --- audio scope functions  --- */
- 
- struct audio *dal_audio_create_dce80(
- 	const struct audio_init_data *init_data)
- {
- 	/*allocate memory for audio_dce80 */
--	struct audio_dce80 *audio = dm_alloc(init_data->ctx, sizeof(struct audio_dce80));
-+	struct audio_dce80 *audio = dm_alloc(sizeof(struct audio_dce80));
- 
- 	if (audio == NULL)
- 		return NULL;
-@@ -424,7 +422,7 @@ struct audio *dal_audio_create_dce80(
- 		return &audio->base;
- 
- 	 /*release memory allocated if fail */
--	dm_free(init_data->ctx, audio);
-+	dm_free(audio);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h
-index 4fef455..4779fac 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/audio_dce80.h
-@@ -29,7 +29,6 @@
- #include "audio/hw_ctx_audio.h"
- #include "audio/dce80/hw_ctx_audio_dce80.h"
- 
--
- struct audio_dce80 {
- 	struct audio base;
- 	/* dce-specific members are following */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-index 521ad07..5f6a433 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-@@ -58,7 +58,6 @@ static const uint32_t engine_offset[] = {
- /* static void dal_audio_destruct_hw_ctx_audio_dce80(
- 	struct hw_ctx_audio_dce80 *ctx);*/
- 
--
- static void destroy(
- 	struct hw_ctx_audio **ptr)
- {
-@@ -69,13 +68,11 @@ static void destroy(
- 
- 	dal_audio_destruct_hw_ctx_audio_dce80(hw_ctx_dce80);
- 	/* release memory allocated for struct hw_ctx_audio_dce80 */
--	dm_free((*ptr)->ctx, hw_ctx_dce80);
-+	dm_free(hw_ctx_dce80);
- 
- 	*ptr = NULL;
- }
- 
--
--
- /* ---  helpers --- */
- 
- static void write_indirect_azalia_reg(
-@@ -127,7 +124,6 @@ static uint32_t read_indirect_azalia_reg(
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 
--
- 	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
- 	{
- 		addr =
-@@ -183,8 +179,6 @@ static void set_high_bit_rate_capable(
- 		value);
- }
- 
--
--
- /* set HBR channnel count */
- /*static void set_hbr_channel_count(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -235,7 +229,6 @@ static void set_video_latency(
- 	if ((latency_in_ms < 0) || (latency_in_ms > 255))
- 		return;
- 
--
- 	value = read_indirect_azalia_reg(
- 		hw_ctx,
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-@@ -250,9 +243,6 @@ static void set_video_latency(
- 		value);
- }
- 
--
--
--
- /* set audio latency in in ms/2+1 */
- static void set_audio_latency(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -280,8 +270,6 @@ static void set_audio_latency(
- 		value);
- }
- 
--
--
- /* enable HW/SW Sync */
- /*static void enable_hw_sw_sync(
- 	const struct hw_ctx_audio *hw_ctx)
-@@ -293,8 +281,6 @@ static void set_audio_latency(
- 	dal_write_reg(mmAZALIA_CYCLIC_BUFFER_SYNC, value.u32All);
- }*/
- 
--
--
- /* disable HW/SW Sync */
- /*static void disable_hw_sw_sync(
- 	const struct hw_ctx_audio *hw_ctx)
-@@ -308,7 +294,6 @@ static void set_audio_latency(
- 		mmAZALIA_CYCLIC_BUFFER_SYNC, value.u32All);
- }*/
- 
--
- /* update hardware with software's current position in cyclic buffer */
- /*static void update_sw_write_ptr(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -324,7 +309,6 @@ static void set_audio_latency(
- 		value.u32All);
- }*/
- 
--
- /* update Audio/Video association */
- /*static void update_av_association(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -335,10 +319,6 @@ static void set_audio_latency(
- 
- }*/
- 
--
--
--
--
- /* ---  hook functions --- */
- 
- static bool get_azalia_clock_info_hdmi(
-@@ -353,8 +333,6 @@ static bool get_azalia_clock_info_dp(
- 	const struct audio_pll_info *pll_info,
- 	struct azalia_clock_info *azalia_clock_info);
- 
--
--
- static void setup_audio_wall_dto(
- 	const struct hw_ctx_audio *hw_ctx,
- 	enum signal_type signal,
-@@ -785,7 +763,6 @@ static void setup_dp_audio(
- 	/* --- The following are the registers
- 	 *  copied from the SetupHDMI --- */
- 
--
- 	/* AFMT_AUDIO_PACKET_CONTROL */
- 	{
- 		addr = mmAFMT_AUDIO_PACKET_CONTROL +
-@@ -900,7 +877,6 @@ static void enable_azalia_audio(
- 		value);
- }
- 
--
- /* disable Azalia audio */
- static void disable_azalia_audio(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -1218,7 +1194,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
- 		value);
- 
--
- 	value = 0;
- 
- 	/*get display name string length */
-@@ -1236,7 +1211,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
- 		value);
- 
--
- 	/*
- 	*write the port ID:
- 	*PORT_ID0 = display index
-@@ -1289,7 +1263,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
- 		value);
- 
--
- 	value = 0;
- 	set_reg_field_value(value, audio_info->display_name[4],
- 		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-@@ -1356,7 +1329,6 @@ static void configure_azalia(
- 		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
- 		value);
- 
--
- 	value = 0;
- 	set_reg_field_value(value, audio_info->display_name[16],
- 		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-@@ -1475,7 +1447,6 @@ static void setup_channel_splitting_mapping(
- 	if ((audio_mapping == NULL || audio_mapping->u32all == 0) && enable)
- 		return;
- 
--
- 	value = audio_mapping->u32all;
- 
- 	if (enable == false)
-@@ -1726,8 +1697,6 @@ static bool get_azalia_clock_info_hdmi(
- 	return true;
- }
- 
--
--
- /* search pixel clock value for Azalia DP Audio */
- static bool get_azalia_clock_info_dp(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -1888,7 +1857,6 @@ bool dal_audio_construct_hw_ctx_audio_dce80(
- 	return true;
- }
- 
--
- /* audio_dce80 is derived from audio directly, not via dce80  */
- 
- void dal_audio_destruct_hw_ctx_audio_dce80(
-@@ -1903,7 +1871,7 @@ struct hw_ctx_audio *dal_audio_create_hw_ctx_audio_dce80(
- {
- 	/* allocate memory for struc hw_ctx_audio_dce80 */
- 	struct hw_ctx_audio_dce80 *hw_ctx_dce80 =
--			dm_alloc(ctx, sizeof(struct hw_ctx_audio_dce80));
-+			dm_alloc(sizeof(struct hw_ctx_audio_dce80));
- 
- 	if (!hw_ctx_dce80) {
- 		BREAK_TO_DEBUGGER();
-@@ -1917,10 +1885,8 @@ struct hw_ctx_audio *dal_audio_create_hw_ctx_audio_dce80(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, hw_ctx_dce80);
-+	dm_free(hw_ctx_dce80);
- 
- 	return NULL;
- }
- 
--
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h
-index 1d0e00d..51b467b 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.h
-@@ -40,7 +40,6 @@ struct hw_ctx_audio_dce80 {
- 	/* audio encoder block MM register offset -- associate with DIG FRONT */
- };
- 
--
- /* ---  helpers ---  all static functions*/
- /*set_high_bit_rate_capable
- set_hbr_channel_count
-@@ -71,5 +70,3 @@ struct hw_ctx_audio *dal_audio_create_hw_ctx_audio_dce80(
- 
- #endif  /* __DAL_HW_CTX_AUDIO_DCE80_H__ */
- 
--
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-index 58207f5..6d88771 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-@@ -85,7 +85,6 @@ static const struct audio_clock_info audio_clock_info_table_48bpc[12] = {
- 	{14850, 4096, 297000, 6272, 330000, 6144, 297000}
- };
- 
--
- /***** static function *****/
- 
- /*
-@@ -298,17 +297,8 @@ static bool get_azalia_clock_info_dp(
- 	return false;
- }
- 
--
--
--
--
--
--
--
--
- /*****SCOPE : within audio hw context dal-audio-hw-ctx *****/
- 
--
- /* check whether specified sample rates can fit into a given timing */
- void dal_hw_ctx_audio_check_audio_bandwidth(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -691,7 +681,6 @@ bool dal_audio_hw_ctx_get_audio_clock_info(
- 		}
- 	}
- 
--
- 	/* not found */
- 	if (actual_pixel_clock_in_khz == 0)
- 		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-index 8ab2e58..52865c8 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-@@ -31,7 +31,6 @@
- 
- struct hw_ctx_audio;
- 
--
- struct azalia_reg_offsets {
- 	uint32_t azf0endpointx_azalia_f0_codec_endpoint_index;
- 	uint32_t azf0endpointx_azalia_f0_codec_endpoint_data;
-@@ -184,7 +183,6 @@ struct hw_ctx_audio_funcs {
- 
- };
- 
--
- struct hw_ctx_audio {
- 	const struct hw_ctx_audio_funcs *funcs;
- 	struct dc_context *ctx;
-@@ -199,8 +197,6 @@ struct hw_ctx_audio {
- 	 */
- };
- 
--
--
- /* --- object construct, destruct --- */
- 
- /*
-@@ -218,14 +214,12 @@ void dal_audio_destruct_hw_ctx_audio(
-  *Top base or interface object does not have implementation of creator.
-  */
- 
--
- /* --- functions called by audio hw context itself --- */
- 
- /* MM register access */
- /*read_register  - dal_read_reg */
- /*write_register - dal_write_reg*/
- 
--
- /*check whether specified sample rates can fit into a given timing */
- void dal_hw_ctx_audio_check_audio_bandwidth(
- 	const struct hw_ctx_audio *hw_ctx,
-@@ -280,6 +274,5 @@ bool dal_audio_hw_ctx_get_audio_clock_info(
- 	uint32_t actual_pixel_clock_in_khz,
- 	struct audio_clock_info *audio_clock_info);
- 
--
- #endif  /* __DAL_HW_CTX_AUDIO_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-index 2f1f3d4..ebe14e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/conversion.c
-@@ -23,7 +23,6 @@
-  *
-  */
- 
--
- #include "dm_services.h"
- 
- #define DIVIDER 10000
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-index 74e6d75..911e90b 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
-@@ -137,8 +137,6 @@ struct fixed32_32 dal_fixed32_32_mul_int(struct fixed32_32 lhs, uint32_t rhs)
- 	return fx;
- }
- 
--
--
- struct fixed32_32 dal_fixed32_32_div(
- 	struct fixed32_32 lhs,
- 	struct fixed32_32 rhs)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index e7938ec..60c13fc 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -116,7 +116,6 @@ static const struct log_minor_info info_packet_minor_info_tbl[] = {
- 	{LOG_MINOR_INFO_PACKETS_HDMI, "Hdmi"},
- };
- 
--
- static const struct log_minor_info dsat_minor_info_tbl[] = {
- 	{LOG_MINOR_DSAT_LOGGER, "Logger"},
- 	{LOG_MINOR_DSAT_EDID_OVERRIDE, "EDID_Override"},
-@@ -180,7 +179,6 @@ static const struct log_minor_info backlight_minor_info_tbl[] = {
- 	{LOG_MINOR_BACKLIGHT_LID, "Lid Status"}
- };
- 
--
- static const struct log_minor_info override_feature_minor_info_tbl[] = {
- 	{LOG_MINOR_FEATURE_OVERRIDE, "overriden feature"},
- };
-@@ -209,7 +207,6 @@ static const struct log_minor_info ds_minor_info_tbl[] = {
- 	{LOG_MINOR_DS_MODE_SETTING, "Mode_Setting"},
- };
- 
--
- struct log_major_mask_info {
- 	struct log_major_info major_info;
- 	uint32_t default_mask;
-@@ -231,7 +228,6 @@ struct log_major_mask_info {
- /* IFT - InterFaceTrace */
- #define LG_IFT_MSK (1 << LOG_MINOR_COMPONENT_DC)
- 
--
- #define LG_HW_TR_AUD_MSK (1 << LOG_MINOR_HW_TRACE_AUDIO)
- #define LG_HW_TR_INTERRUPT_MSK (1 << LOG_MINOR_HW_TRACE_INTERRUPT) | \
- 		(1 << LOG_MINOR_HW_TRACE_HPD_IRQ)
-@@ -283,8 +279,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
- 	/* malloc buffer and init offsets */
- 
- 	logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
--	logger->log_buffer = (char *)dm_alloc(ctx,
--		logger->log_buffer_size *
-+	logger->log_buffer = (char *)dm_alloc(logger->log_buffer_size *
- 		sizeof(char));
- 
- 	if (!logger->log_buffer)
-@@ -307,14 +302,11 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
- 
- 	/* malloc and init minor mask array */
- 	logger->log_enable_mask_minors =
--			(uint32_t *)dm_alloc(
--				ctx,
--				NUM_ELEMENTS(log_major_mask_info_tbl)
-+			(uint32_t *)dm_alloc(NUM_ELEMENTS(log_major_mask_info_tbl)
- 				* sizeof(uint32_t));
- 	if (!logger->log_enable_mask_minors)
- 		return false;
- 
--
- 	/* Set default values for mask */
- 	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
- 
-@@ -329,12 +321,12 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
- static void destruct(struct dal_logger *logger)
- {
- 	if (logger->log_buffer) {
--		dm_free(logger->ctx, logger->log_buffer);
-+		dm_free(logger->log_buffer);
- 		logger->log_buffer = NULL;
- 	}
- 
- 	if (logger->log_enable_mask_minors) {
--		dm_free(logger->ctx, logger->log_enable_mask_minors);
-+		dm_free(logger->log_enable_mask_minors);
- 		logger->log_enable_mask_minors = NULL;
- 	}
- }
-@@ -342,12 +334,12 @@ static void destruct(struct dal_logger *logger)
- struct dal_logger *dal_logger_create(struct dc_context *ctx)
- {
- 	/* malloc struct */
--	struct dal_logger *logger = dm_alloc(ctx, sizeof(struct dal_logger));
-+	struct dal_logger *logger = dm_alloc(sizeof(struct dal_logger));
- 
- 	if (!logger)
- 		return NULL;
- 	if (!construct(ctx, logger)) {
--		dm_free(ctx, logger);
-+		dm_free(logger);
- 		return NULL;
- 	}
- 
-@@ -359,7 +351,7 @@ uint32_t dal_logger_destroy(struct dal_logger **logger)
- 	if (logger == NULL || *logger == NULL)
- 		return 1;
- 	destruct(*logger);
--	dm_free((*logger)->ctx, *logger);
-+	dm_free(*logger);
- 	*logger = NULL;
- 
- 	return 0;
-@@ -474,9 +466,6 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			logger->buffer_read_offset = 0;
- 		}
- 
--
--
--
- 		if (space_before_wrap > size) {
- 			/* No wrap around, copy 'size' bytes
- 			 * from 'entry->buf' to 'log_buffer'
-@@ -520,7 +509,6 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 	unlock(logger);
- }
- 
--
- static void log_timestamp(struct log_entry *entry)
- {
- 	dal_logger_append(entry, "00:00:00 ");
-@@ -567,7 +555,6 @@ static void log_heading(struct log_entry *entry,
- 	log_major_minor(entry);
- }
- 
--
- static void append_entry(
- 		struct log_entry *entry,
- 		char *buffer,
-@@ -608,7 +595,6 @@ void dal_logger_write(
- 		va_start(args, msg);
- 		dal_logger_open(logger, &entry, major, minor);
- 
--
- 		size = dm_log_to_buffer(
- 			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
- 
-@@ -631,7 +617,6 @@ void dal_logger_write(
- 	}
- }
- 
--
- /* Same as dal_logger_write, except without open() and close(), which must
-  * be done separately.
-  */
-@@ -671,7 +656,6 @@ void dal_logger_append(
- 	}
- }
- 
--
- uint32_t dal_logger_read(
- 	struct dal_logger *logger, /* <[in] */
- 	uint32_t output_buffer_size, /* <[in] */
-@@ -763,9 +747,7 @@ void dal_logger_open(
- 	entry->minor = 0;
- 	entry->logger = logger;
- 
--	entry->buf = dm_alloc(
--		logger->ctx,
--		DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char));
-+	entry->buf = dm_alloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char));
- 
- 	entry->buf_offset = 0;
- 	entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
-@@ -781,7 +763,6 @@ void dal_logger_close(struct log_entry *entry)
- {
- 	struct dal_logger *logger = entry->logger;
- 
--
- 	if (logger && logger->open_count > 0) {
- 		logger->open_count--;
- 	} else {
-@@ -799,7 +780,7 @@ void dal_logger_close(struct log_entry *entry)
- 
- cleanup:
- 	if (entry->buf) {
--		dm_free(entry->logger->ctx, entry->buf);
-+		dm_free(entry->buf);
- 		entry->buf = NULL;
- 		entry->buf_offset = 0;
- 		entry->max_buf_bytes = 0;
-@@ -888,7 +869,6 @@ void dal_logger_set_flags(
- 	logger->flags = flags;
- }
- 
--
- uint32_t dal_logger_get_buffer_size(struct dal_logger *logger)
- {
- 	return DAL_LOGGER_BUFFER_MAX_SIZE;
-@@ -904,7 +884,6 @@ uint32_t dal_logger_set_buffer_size(
- 	return DAL_LOGGER_BUFFER_MAX_SIZE;
- }
- 
--
- const struct log_major_info *dal_logger_enum_log_major_info(
- 		struct dal_logger *logger,
- 		unsigned int enum_index)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.h b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-index fba5ec3..c2aea53 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-@@ -31,7 +31,6 @@
- #define DAL_LOGGER_BUFFER_MAX_SIZE 2048
- #define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 256
- 
--
- #include "include/logger_types.h"
- 
- struct dal_logger {
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/vector.c b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-index 32ca6b1..7ad7fef 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-@@ -40,7 +40,7 @@ bool dal_vector_construct(
- 		return false;
- 	}
- 
--	vector->container = dm_alloc(ctx, struct_size * capacity);
-+	vector->container = dm_alloc(struct_size * capacity);
- 	if (vector->container == NULL)
- 		return false;
- 	vector->capacity = capacity;
-@@ -67,7 +67,7 @@ bool dal_vector_presized_costruct(
- 		return false;
- 	}
- 
--	vector->container = dm_alloc(ctx, struct_size * count);
-+	vector->container = dm_alloc(struct_size * count);
- 
- 	if (vector->container == NULL)
- 		return false;
-@@ -95,7 +95,7 @@ struct vector *dal_vector_presized_create(
- 	void *initial_value,
- 	uint32_t struct_size)
- {
--	struct vector *vector = dm_alloc(ctx, sizeof(struct vector));
-+	struct vector *vector = dm_alloc(sizeof(struct vector));
- 
- 	if (vector == NULL)
- 		return NULL;
-@@ -105,7 +105,7 @@ struct vector *dal_vector_presized_create(
- 		return vector;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, vector);
-+	dm_free(vector);
- 	return NULL;
- }
- 
-@@ -114,7 +114,7 @@ struct vector *dal_vector_create(
- 	uint32_t capacity,
- 	uint32_t struct_size)
- {
--	struct vector *vector = dm_alloc(ctx, sizeof(struct vector));
-+	struct vector *vector = dm_alloc(sizeof(struct vector));
- 
- 	if (vector == NULL)
- 		return NULL;
-@@ -122,9 +122,8 @@ struct vector *dal_vector_create(
- 	if (dal_vector_construct(vector, ctx, capacity, struct_size))
- 		return vector;
- 
--
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, vector);
-+	dm_free(vector);
- 	return NULL;
- }
- 
-@@ -132,7 +131,7 @@ void dal_vector_destruct(
- 	struct vector *vector)
- {
- 	if (vector->container != NULL)
--		dm_free(vector->ctx, vector->container);
-+		dm_free(vector->container);
- 	vector->count = 0;
- 	vector->capacity = 0;
- }
-@@ -143,7 +142,7 @@ void dal_vector_destroy(
- 	if (vector == NULL || *vector == NULL)
- 		return;
- 	dal_vector_destruct(*vector);
--	dm_free((*vector)->ctx, *vector);
-+	dm_free(*vector);
- 	*vector = NULL;
- }
- 
-@@ -291,8 +290,7 @@ bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
- 	if (capacity <= vector->capacity)
- 		return true;
- 
--	new_container = dm_realloc(vector->ctx, vector->container,
--		capacity * vector->struct_size);
-+	new_container = dm_realloc(vector->container, capacity * vector->struct_size);
- 
- 	if (new_container) {
- 		vector->container = new_container;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 586a5ee..f433f8e 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -96,7 +96,6 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- 	ATOM_OBJECT *object);
- static void process_ext_display_connection_info(struct bios_parser *bp);
- 
--
- #define BIOS_IMAGE_SIZE_OFFSET 2
- #define BIOS_IMAGE_SIZE_UNIT 512
- 
-@@ -120,14 +119,14 @@ struct dc_bios *dal_bios_parser_create(
- {
- 	struct bios_parser *bp = NULL;
- 
--	bp = dm_alloc(init->ctx, sizeof(struct bios_parser));
-+	bp = dm_alloc(sizeof(struct bios_parser));
- 	if (!bp)
- 		return NULL;
- 
- 	if (bios_parser_construct(bp, init, as))
- 		return &bp->base;
- 
--	dm_free(init->ctx, bp);
-+	dm_free(bp);
- 	BREAK_TO_DEBUGGER();
- 	return NULL;
- }
-@@ -135,7 +134,7 @@ struct dc_bios *dal_bios_parser_create(
- static void destruct(struct bios_parser *bp)
- {
- 	if (bp->bios_local_image)
--		dm_free(bp->ctx, bp->bios_local_image);
-+		dm_free(bp->bios_local_image);
- }
- 
- void dal_bios_parser_destroy(struct dc_bios **dcb)
-@@ -149,7 +148,7 @@ void dal_bios_parser_destroy(struct dc_bios **dcb)
- 
- 	destruct(bp);
- 
--	dm_free((bp)->ctx, bp);
-+	dm_free(bp);
- 	*dcb = NULL;
- }
- 
-@@ -563,7 +562,6 @@ static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
- 		result = bios_parser_get_thermal_ddc_info(dcb,
- 			i2c_line, info);
- 
--
- 	return result;
- }
- 
-@@ -1528,7 +1526,6 @@ static ATOM_I2C_RECORD *get_i2c_record(
- 	return NULL;
- }
- 
--
- static enum bp_result get_ss_info_from_ss_info_table(
- 	struct bios_parser *bp,
- 	uint32_t id,
-@@ -2312,7 +2309,6 @@ static uint32_t bios_parser_get_ss_entry_number(
- 	return 0;
- }
- 
--
- /**
-  * get_ss_entry_number_from_ss_info_tbl
-  * Get Number of spread spectrum entry from the SS_Info table from the VBIOS.
-@@ -2381,7 +2377,6 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
- 	return number;
- }
- 
--
- /**
-  * get_ss_entry_number
-  * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-@@ -4089,7 +4084,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 		uint8_t *original_bios;
- 		/* Step 1: Replace bios image with the new copy which will be
- 		 * patched */
--		bp->bios_local_image = dm_alloc(bp->ctx, bp->bios_size);
-+		bp->bios_local_image = dm_alloc(bp->bios_size);
- 		if (bp->bios_local_image == NULL) {
- 			BREAK_TO_DEBUGGER();
- 			/* Failed to alloc bp->bios_local_image */
-@@ -4667,14 +4662,13 @@ static enum bp_result construct_integrated_info(
- 	return result;
- }
- 
--
- static struct integrated_info *bios_parser_create_integrated_info(
- 	struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct integrated_info *info = NULL;
- 
--	info = dm_alloc(bp->ctx, sizeof(struct integrated_info));
-+	info = dm_alloc(sizeof(struct integrated_info));
- 
- 	if (info == NULL) {
- 		ASSERT_CRITICAL(0);
-@@ -4684,7 +4678,7 @@ static struct integrated_info *bios_parser_create_integrated_info(
- 	if (construct_integrated_info(bp, info) == BP_RESULT_OK)
- 		return info;
- 
--	dm_free(bp->ctx, info);
-+	dm_free(info);
- 
- 	return NULL;
- }
-@@ -4693,15 +4687,13 @@ static void bios_parser_destroy_integrated_info(
- 	struct dc_bios *dcb,
- 	struct integrated_info **info)
- {
--	struct bios_parser *bp = BP_FROM_DCB(dcb);
--
- 	if (info == NULL) {
- 		ASSERT_CRITICAL(0);
- 		return;
- 	}
- 
- 	if (*info != NULL) {
--		dm_free(bp->ctx, *info);
-+		dm_free(*info);
- 		*info = NULL;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index 3bc52f5..2ea0576 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -47,7 +47,6 @@
- 	dm_bios_cmd_table_para_revision(bp->ctx, \
- 		GetIndexIntoMasterTable(COMMAND, command))
- 
--
- static void init_dig_encoder_control(struct bios_parser *bp);
- static void init_transmitter_control(struct bios_parser *bp);
- static void init_set_pixel_clock(struct bios_parser *bp);
-@@ -268,7 +267,6 @@ static enum bp_result encoder_control_digx_v4(
- 	else
- 		params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
- 
--
- 	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
- 
- 	/* We need to convert from KHz units into 10KHz units */
-@@ -1907,7 +1905,6 @@ static enum bp_result set_crtc_timing_v1(
- 	params.usV_SyncWidth =
- 			cpu_to_le16((uint16_t)(bp_params->v_sync_width));
- 
--
- 	/* VBIOS does not expect any value except zero into this call, for
- 	 * underscan use another entry ProgramOverscan call but when mode
- 	 * 1776x1000 with the overscan 72x44 .e.i. 1920x1080 @30 DAL2 is ok,
-@@ -2006,7 +2003,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
- 		params.susModeMiscInfo.usAccess =
- 				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
- 
--
- 	if (bp_params->flags.INTERLACE)	{
- 		params.susModeMiscInfo.usAccess =
- 				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-@@ -2652,7 +2648,6 @@ static enum bp_result enable_disp_power_gating_v2_1(
- 	return result;
- }
- 
--
- /*******************************************************************************
-  ********************************************************************************
-  **
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-index 614ba94..092c0f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c
-@@ -65,7 +65,6 @@ static uint8_t phy_id_to_atom(enum transmitter t)
- 	return atom_phy_id;
- }
- 
--
- static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
- {
- 	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index 541a8c4..b6ee5bf 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -38,7 +38,6 @@
- 
- #include "../bios_parser_helper.h"
- 
--
- static const uint8_t bios_scratch0_dacb_shift = 8;
- 
- /**
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 2b69536..ca17b25 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3601,7 +3601,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
- 	vbios.blackout_duration = bw_int_to_fixed(18); /* us */
- 	vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
- 
--
- 	dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
- 	dceip.de_tiling_buffer = bw_int_to_fixed(0);
- 	dceip.dcfclk_request_generation = 0;
-@@ -3703,10 +3702,9 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 	const struct bw_calcs_mode_data *mode_data,
- 	struct bw_calcs_output *calcs_output)
- {
--	struct bw_calcs_results *bw_results_internal = dm_alloc(
--				ctx, sizeof(struct bw_calcs_results));
-+	struct bw_calcs_results *bw_results_internal = dm_alloc(sizeof(struct bw_calcs_results));
- 	struct bw_calcs_mode_data_internal *bw_data_internal =
--		dm_alloc(ctx, sizeof(struct bw_calcs_mode_data_internal));
-+		dm_alloc(sizeof(struct bw_calcs_mode_data_internal));
- 
- 	switch (mode_data->number_of_displays) {
- 	case (6):
-@@ -3941,8 +3939,8 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->required_sclk = 0;
- 	}
- 
--	dm_free(ctx, bw_data_internal);
--	dm_free(ctx, bw_results_internal);
-+	dm_free(bw_data_internal);
-+	dm_free(bw_results_internal);
- 
- 	return is_display_configuration_supported(vbios, calcs_output);
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-index 8a7a4c9..edb109e 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
-@@ -25,7 +25,6 @@
- #include "dm_services.h"
- #include "bw_fixed.h"
- 
--
- #define BITS_PER_FRACTIONAL_PART 24
- 
- #define MIN_I32 \
-@@ -40,7 +39,6 @@
- #define MAX_I64 \
- 	(int64_t)((1ULL << 63) - 1)
- 
--
- #define FRACTIONAL_PART_MASK \
- 	((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-index 6f0f64a..9c18bda 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-@@ -185,7 +185,6 @@ static bool setup_custom_float(
- 	return true;
- }
- 
--
- static bool convert_to_custom_float_format_ex(
- 	struct fixed31_32 value,
- 	const struct custom_float_format *format,
-@@ -432,7 +431,6 @@ struct dividers {
- 	struct fixed31_32 divider3;
- };
- 
--
- static void build_regamma_coefficients(struct gamma_coefficients *coefficients)
- {
- 	/* sRGB should apply 2.4 */
-@@ -1338,4 +1336,3 @@ void calculate_regamma_params(struct pwl_params *params,
- 			params->hw_points_num);
- }
- 
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-index 64ca203..706bf0a 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
-@@ -1099,9 +1099,7 @@ static bool allocate_3d_storage(
- 	int32_t indexof_table = 0;
- 	int32_t indexof_row = 0;
- 
--	struct fixed31_32 ***tables = dm_alloc(
--		ctx,
--		numberof_tables * sizeof(struct fixed31_32 **));
-+	struct fixed31_32 ***tables = dm_alloc(numberof_tables * sizeof(struct fixed31_32 **));
- 
- 	if (!tables) {
- 		BREAK_TO_DEBUGGER();
-@@ -1109,9 +1107,7 @@ static bool allocate_3d_storage(
- 	}
- 
- 	while (indexof_table != numberof_tables) {
--		struct fixed31_32 **rows = dm_alloc(
--			ctx,
--			numberof_rows * sizeof(struct fixed31_32 *));
-+		struct fixed31_32 **rows = dm_alloc(numberof_rows * sizeof(struct fixed31_32 *));
- 
- 		if (!rows) {
- 			BREAK_TO_DEBUGGER();
-@@ -1122,9 +1118,7 @@ static bool allocate_3d_storage(
- 		tables[indexof_table] = rows;
- 
- 		while (indexof_row != numberof_rows) {
--			struct fixed31_32 *columns = dm_alloc(
--				ctx,
--				numberof_columns * sizeof(struct fixed31_32));
-+			struct fixed31_32 *columns = dm_alloc(numberof_columns * sizeof(struct fixed31_32));
- 
- 			if (!columns) {
- 				BREAK_TO_DEBUGGER();
-@@ -1150,19 +1144,19 @@ failure:
- 
- 	while (indexof_table >= 0) {
- 		while (indexof_row >= 0) {
--			dm_free(ctx, tables[indexof_table][indexof_row]);
-+			dm_free(tables[indexof_table][indexof_row]);
- 
- 			--indexof_row;
- 		}
- 
- 		indexof_row = numberof_rows - 1;
- 
--		dm_free(ctx, tables[indexof_table]);
-+		dm_free(tables[indexof_table]);
- 
- 		--indexof_table;
- 	}
- 
--	dm_free(ctx, tables);
-+	dm_free(tables);
- 
- 	return false;
- }
-@@ -1184,18 +1178,17 @@ static void destroy_3d_storage(
- 		uint32_t indexof_row = 0;
- 
- 		while (indexof_row != numberof_rows) {
--			dm_free(
--				ctx, tables[indexof_table][indexof_row]);
-+			dm_free(tables[indexof_table][indexof_row]);
- 
- 			++indexof_row;
- 		};
- 
--		dm_free(ctx, tables[indexof_table]);
-+		dm_free(tables[indexof_table]);
- 
- 		++indexof_table;
- 	};
- 
--	dm_free(ctx, tables);
-+	dm_free(tables);
- 
- 	*ptr = NULL;
- }
-@@ -1627,15 +1620,13 @@ static bool generate_filter(
- 
- 	if (filter->coefficients_quantity < coefficients_quantity) {
- 		if (filter->coefficients) {
--			dm_free(filter->ctx, filter->coefficients);
-+			dm_free(filter->coefficients);
- 
- 			filter->coefficients = NULL;
- 			filter->coefficients_quantity = 0;
- 		}
- 
--		filter->coefficients = dm_alloc(
--			filter->ctx,
--			coefficients_quantity * sizeof(struct fixed31_32));
-+		filter->coefficients = dm_alloc(coefficients_quantity * sizeof(struct fixed31_32));
- 
- 		if (!filter->coefficients) {
- 			BREAK_TO_DEBUGGER();
-@@ -1655,15 +1646,13 @@ static bool generate_filter(
- 
- 	if (filter->coefficients_sum_quantity < coefficients_sum_quantity) {
- 		if (filter->coefficients_sum) {
--			dm_free(filter->ctx, filter->coefficients_sum);
-+			dm_free(filter->coefficients_sum);
- 
- 			filter->coefficients_sum = NULL;
- 			filter->coefficients_sum_quantity = 0;
- 		}
- 
--		filter->coefficients_sum = dm_alloc(
--			filter->ctx,
--			coefficients_sum_quantity * sizeof(struct fixed31_32));
-+		filter->coefficients_sum = dm_alloc(coefficients_sum_quantity * sizeof(struct fixed31_32));
- 
- 		if (!filter->coefficients_sum) {
- 			BREAK_TO_DEBUGGER();
-@@ -1831,16 +1820,16 @@ static void destruct_scaler_filter(
- 	struct scaler_filter *filter)
- {
- 	if (filter->coefficients_sum)
--		dm_free(filter->ctx, filter->coefficients_sum);
-+		dm_free(filter->coefficients_sum);
- 
- 	if (filter->coefficients)
--		dm_free(filter->ctx, filter->coefficients);
-+		dm_free(filter->coefficients);
- 
- 	if (filter->integer_filter)
--		dm_free(filter->ctx, filter->integer_filter);
-+		dm_free(filter->integer_filter);
- 
- 	if (filter->filter)
--		dm_free(filter->ctx, filter->filter);
-+		dm_free(filter->filter);
- 
- 	destroy_upscaling_table(filter);
- 
-@@ -1850,7 +1839,7 @@ static void destruct_scaler_filter(
- struct scaler_filter *dal_scaler_filter_create(struct dc_context *ctx)
- {
- 	struct scaler_filter *filter =
--		dm_alloc(ctx, sizeof(struct scaler_filter));
-+		dm_alloc(sizeof(struct scaler_filter));
- 
- 	if (!filter) {
- 		BREAK_TO_DEBUGGER();
-@@ -1862,7 +1851,7 @@ struct scaler_filter *dal_scaler_filter_create(struct dc_context *ctx)
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, filter);
-+	dm_free(filter);
- 
- 	return NULL;
- }
-@@ -1902,15 +1891,13 @@ bool dal_scaler_filter_generate(
- 
- 	if (filter_size_required > filter->filter_size_allocated) {
- 		if (filter->filter) {
--			dm_free(filter->ctx, filter->filter);
-+			dm_free(filter->filter);
- 
- 			filter->filter = 0;
- 			filter->filter_size_allocated = 0;
- 		}
- 
--		filter->filter = dm_alloc(
--			filter->ctx,
--			filter_size_required * sizeof(struct fixed31_32));
-+		filter->filter = dm_alloc(filter_size_required * sizeof(struct fixed31_32));
- 
- 		if (!filter->filter) {
- 			BREAK_TO_DEBUGGER();
-@@ -1918,14 +1905,12 @@ bool dal_scaler_filter_generate(
- 		}
- 
- 		if (filter->integer_filter) {
--			dm_free(filter->ctx, filter->integer_filter);
-+			dm_free(filter->integer_filter);
- 
- 			filter->integer_filter = 0;
- 		}
- 
--		filter->integer_filter = dm_alloc(
--			filter->ctx,
--			filter_size_required * sizeof(uint32_t));
-+		filter->integer_filter = dm_alloc(filter_size_required * sizeof(uint32_t));
- 
- 		if (!filter->integer_filter) {
- 			BREAK_TO_DEBUGGER();
-@@ -1986,7 +1971,7 @@ void dal_scaler_filter_destroy(
- 
- 	destruct_scaler_filter(*filter);
- 
--	dm_free((*filter)->ctx, *filter);
-+	dm_free(*filter);
- 
- 	*filter = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 69489f7..44f43ea 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -121,9 +121,7 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 	}
- 
- 	for (i = 0; i < init_params->num_virtual_links; i++) {
--		struct core_link *link = dm_alloc(
--			dc->ctx,
--			sizeof(*link));
-+		struct core_link *link = dm_alloc(sizeof(*link));
- 		struct encoder_init_data enc_init = {0};
- 
- 		if (link == NULL) {
-@@ -138,9 +136,7 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 		link->link_id.type = OBJECT_TYPE_CONNECTOR;
- 		link->link_id.id = CONNECTOR_ID_VIRTUAL;
- 		link->link_id.enum_id = ENUM_ID_1;
--		link->link_enc = dm_alloc(
--			dc->ctx,
--			sizeof(*link->link_enc));
-+		link->link_enc = dm_alloc(sizeof(*link->link_enc));
- 
- 		enc_init.adapter_service = init_params->adapter_srv;
- 		enc_init.ctx = init_params->ctx;
-@@ -164,7 +160,6 @@ failed_alloc:
- 	return false;
- }
- 
--
- static void init_hw(struct core_dc *dc)
- {
- 	int i;
-@@ -318,7 +313,7 @@ static bool construct(struct core_dc *dc, const struct dal_init_data *init_param
- 	ctx.cgs_device = init_params->cgs_device;
- 	ctx.dc = dc;
- 
--	dc_init_data.ctx = dm_alloc(&ctx, sizeof(*dc_init_data.ctx));
-+	dc_init_data.ctx = dm_alloc(sizeof(*dc_init_data.ctx));
- 	if (!dc_init_data.ctx) {
- 		dm_error("%s: failed to create ctx\n", __func__);
- 		goto ctx_fail;
-@@ -384,7 +379,7 @@ as_fail:
- 	dal_logger_destroy(&dc_init_data.ctx->logger);
- logger_fail:
- hwss_fail:
--	dm_free(&ctx, dc_init_data.ctx);
-+	dm_free(dc_init_data.ctx);
- ctx_fail:
- 	return false;
- }
-@@ -395,7 +390,7 @@ static void destruct(struct core_dc *dc)
- 	destroy_links(dc);
- 	dc->res_pool.funcs->destruct(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
--	dm_free(dc->ctx, dc->ctx);
-+	dm_free(dc->ctx);
- }
- 
- /*
-@@ -474,7 +469,7 @@ struct core_dc *dc_create(const struct dal_init_data *init_params)
- 		.driver_context = init_params->driver,
- 		.cgs_device = init_params->cgs_device
- 	};
--	struct core_dc *dc = dm_alloc(&ctx, sizeof(*dc));
-+	struct core_dc *dc = dm_alloc(sizeof(*dc));
- 
- 	if (NULL == dc)
- 		goto alloc_fail;
-@@ -489,7 +484,7 @@ struct core_dc *dc_create(const struct dal_init_data *init_params)
- 	return dc;
- 
- construct_fail:
--	dm_free(&ctx, dc);
-+	dm_free(dc);
- 
- alloc_fail:
- 	return NULL;
-@@ -497,9 +492,8 @@ alloc_fail:
- 
- void dc_destroy(struct core_dc **dc)
- {
--	struct dc_context ctx = *((*dc)->ctx);
- 	destruct(*dc);
--	dm_free(&ctx, *dc);
-+	dm_free(*dc);
- 	*dc = NULL;
- }
- 
-@@ -511,7 +505,7 @@ bool dc_validate_resources(
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	struct validate_context *context;
- 
--	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
-+	context = dm_alloc(sizeof(struct validate_context));
- 	if(context == NULL)
- 		goto context_alloc_fail;
- 
-@@ -519,7 +513,7 @@ bool dc_validate_resources(
- 						dc, set, set_count, context);
- 
- 	val_ctx_destruct(context);
--	dm_free(dc->ctx, context);
-+	dm_free(context);
- context_alloc_fail:
- 
- 	return (result == DC_OK);
-@@ -668,7 +662,7 @@ bool dc_commit_targets(
- 
- 	}
- 
--	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
-+	context = dm_alloc(sizeof(struct validate_context));
- 	if (context == NULL)
- 		goto context_alloc_fail;
- 
-@@ -714,7 +708,7 @@ bool dc_commit_targets(
- 	dc->current_context = *context;
- 
- fail:
--	dm_free(dc->ctx, context);
-+	dm_free(context);
- 
- context_alloc_fail:
- 	return (result == DC_OK);
-@@ -736,7 +730,7 @@ bool dc_commit_surfaces_to_target(
- 	int new_enabled_surface_count = 0;
- 	bool is_mpo_turning_on = false;
- 
--	context = dm_alloc(dc->ctx, sizeof(struct validate_context));
-+	context = dm_alloc(sizeof(struct validate_context));
- 
- 	val_ctx_copy_construct(&dc->current_context, context);
- 
-@@ -866,14 +860,14 @@ bool dc_commit_surfaces_to_target(
- 
- 	val_ctx_destruct(&dc->current_context);
- 	dc->current_context = *context;
--	dm_free(dc->ctx, context);
-+	dm_free(context);
- 	return true;
- 
- unexpected_fail:
- 
- 	val_ctx_destruct(context);
- 
--	dm_free(dc->ctx, context);
-+	dm_free(context);
- 	return false;
- }
- 
-@@ -951,7 +945,6 @@ enum dc_irq_source dc_interrupt_to_irq_source(
- 	return dal_irq_service_to_irq_source(dc->res_pool.irqs, src_id, ext_id);
- }
- 
--
- void dc_interrupt_set(const struct core_dc *dc, enum dc_irq_source src, bool enable)
- {
- 	dal_irq_service_set(dc->res_pool.irqs, src, enable);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 36b1661..e259509 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -39,13 +39,11 @@
- #include "hw_sequencer.h"
- #include "fixed31_32.h"
- 
--
- #define LINK_INFO(...) \
- 	dal_logger_write(dc_ctx->logger, \
- 		LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_HOTPLUG, \
- 		__VA_ARGS__)
- 
--
- /*******************************************************************************
-  * Private structures
-  ******************************************************************************/
-@@ -172,13 +170,11 @@ hpd_gpio_failure:
- 	return false;
- }
- 
--
- enum ddc_transaction_type get_ddc_transaction_type(
- 		enum signal_type sink_signal)
- {
- 	enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
- 
--
- 	switch (sink_signal) {
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
-@@ -204,7 +200,6 @@ enum ddc_transaction_type get_ddc_transaction_type(
- 		break;
- 	}
- 
--
- 	return transaction_type;
- }
- 
-@@ -636,7 +631,6 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 			else
- 				link->dpcd_sink_count = 1;
- 
--
- 		dal_ddc_service_set_transaction_type(
- 						link->ddc,
- 						sink_caps.transaction_type);
-@@ -1063,7 +1057,7 @@ create_fail:
- struct core_link *link_create(const struct link_init_data *init_params)
- {
- 	struct core_link *link =
--			dm_alloc(init_params->ctx, sizeof(*link));
-+			dm_alloc(sizeof(*link));
- 
- 	if (NULL == link)
- 		goto alloc_fail;
-@@ -1074,7 +1068,7 @@ struct core_link *link_create(const struct link_init_data *init_params)
- 	return link;
- 
- construct_fail:
--	dm_free(init_params->ctx, link);
-+	dm_free(link);
- 
- alloc_fail:
- 	return NULL;
-@@ -1083,7 +1077,7 @@ alloc_fail:
- void link_destroy(struct core_link **link)
- {
- 	destruct(*link);
--	dm_free((*link)->ctx, *link);
-+	dm_free(*link);
- 	*link = NULL;
- }
- 
-@@ -1530,8 +1524,6 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
- 	pbn = get_pbn_from_timing(pipe_ctx);
- 	avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
- 
--
--
- 	stream_encoder->funcs->set_mst_bandwidth(
- 		stream_encoder,
- 		avg_time_slots_per_mtp);
-@@ -1647,4 +1639,3 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
- 	disable_link(pipe_ctx->stream->sink->link, pipe_ctx->signal);
- }
- 
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index f725da7..f211408 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -95,7 +95,6 @@ enum edid_read_result {
- #define HDMI_SCDC_ERR_DETECT 0x50
- #define HDMI_SCDC_TEST_CONFIG 0xC0
- 
--
- union hdmi_scdc_update_read_data {
- 	uint8_t byte[2];
- 	struct {
-@@ -143,8 +142,6 @@ union hdmi_scdc_test_config_Data {
- 	} fields;
- };
- 
--
--
- struct i2c_payloads {
- 	struct vector payloads;
- };
-@@ -157,7 +154,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_
- {
- 	struct i2c_payloads *payloads;
- 
--	payloads = dm_alloc(ctx, sizeof(struct i2c_payloads));
-+	payloads = dm_alloc(sizeof(struct i2c_payloads));
- 
- 	if (!payloads)
- 		return NULL;
-@@ -166,7 +163,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_
- 		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
- 		return payloads;
- 
--	dm_free(ctx, payloads);
-+	dm_free(payloads);
- 	return NULL;
- 
- }
-@@ -186,7 +183,7 @@ void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
- 	if (!p || !*p)
- 		return;
- 	dal_vector_destruct(&(*p)->payloads);
--	dm_free((*p)->payloads.ctx, *p);
-+	dm_free(*p);
- 	*p = NULL;
- 
- }
-@@ -195,7 +192,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_
- {
- 	struct aux_payloads *payloads;
- 
--	payloads = dm_alloc(ctx, sizeof(struct aux_payloads));
-+	payloads = dm_alloc(sizeof(struct aux_payloads));
- 
- 	if (!payloads)
- 		return NULL;
-@@ -204,7 +201,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_
- 		&payloads->payloads, ctx, count, sizeof(struct aux_payloads)))
- 		return payloads;
- 
--	dm_free(ctx, payloads);
-+	dm_free(payloads);
- 	return NULL;
- }
- 
-@@ -218,14 +215,13 @@ uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
- 	return p->payloads.count;
- }
- 
--
- void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
- {
- 	if (!p || !*p)
- 		return;
- 
- 	dal_vector_destruct(&(*p)->payloads);
--	dm_free((*p)->payloads.ctx, *p);
-+	dm_free(*p);
- 	*p = NULL;
- }
- 
-@@ -273,7 +269,6 @@ void dal_ddc_aux_payloads_add(
- 	}
- }
- 
--
- static bool construct(
- 	struct ddc_service *ddc_service,
- 	struct ddc_service_init_data *init_data)
-@@ -297,7 +292,6 @@ static bool construct(
- 			dal_adapter_service_is_feature_supported(
- 				FEATURE_EDID_STRESS_READ);
- 
--
- 	ddc_service->flags.IS_INTERNAL_DISPLAY =
- 		connector_id == CONNECTOR_ID_EDP ||
- 		connector_id == CONNECTOR_ID_LVDS;
-@@ -311,7 +305,7 @@ struct ddc_service *dal_ddc_service_create(
- {
- 	struct ddc_service *ddc_service;
- 
--	ddc_service = dm_alloc(init_data->ctx, sizeof(struct ddc_service));
-+	ddc_service = dm_alloc(sizeof(struct ddc_service));
- 
- 	if (!ddc_service)
- 		return NULL;
-@@ -319,7 +313,7 @@ struct ddc_service *dal_ddc_service_create(
- 	if (construct(ddc_service, init_data))
- 		return ddc_service;
- 
--	dm_free(init_data->ctx, ddc_service);
-+	dm_free(ddc_service);
- 	return NULL;
- }
- 
-@@ -336,7 +330,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc)
- 		return;
- 	}
- 	destruct(*ddc);
--	dm_free((*ddc)->ctx, *ddc);
-+	dm_free(*ddc);
- 	*ddc = NULL;
- }
- 
-@@ -1055,7 +1049,6 @@ struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
- 	return ddc_service->ddc_pin;
- }
- 
--
- void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
- {
- 	dm_memset(&ddc_service->dp_receiver_id_info,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 92d44aa..31f8ce3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -119,7 +119,6 @@ static void dpcd_set_link_settings(
- 	union lane_count_set lane_count_set = {{0}};
- 	uint8_t link_set_buffer[2];
- 
--
- 	downspread.raw = (uint8_t)
- 	(lt_settings->link_settings.link_spread);
- 
-@@ -219,7 +218,6 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 		DPCD_ADDRESS_TRAINING_PATTERN_SET,
- 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
- 
--
- 	/*****************************************************************
- 	* DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
- 	*****************************************************************/
-@@ -261,7 +259,6 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 		dpcd_lane[0].bits.MAX_SWING_REACHED,
- 		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
- 
--
- 	if (edp_workaround) {
- 		/* for eDP write in 2 parts because the 5-byte burst is
- 		* causing issues on some eDP panels (EPR#366724)
-@@ -390,7 +387,6 @@ static void find_max_drive_settings(
- 			link_training_setting->
- 			lane_settings[lane].VOLTAGE_SWING;
- 
--
- 		if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
- 				max_requested.PRE_EMPHASIS)
- 			max_requested.PRE_EMPHASIS =
-@@ -479,7 +475,6 @@ static void get_lane_status_and_drive_settings(
- 		(uint8_t *)(dpcd_buf),
- 		sizeof(dpcd_buf));
- 
--
- 	for (lane = 0; lane <
- 		(uint32_t)(link_training_setting->link_settings.lane_count);
- 		lane++) {
-@@ -875,7 +870,6 @@ static bool perform_clock_recovery_sequence(
- 					link,
- 					lt_settings);
- 
--
- 		/* 3. wait receiver to lock-on*/
- 		wait_for_training_aux_rd_interval(
- 				link,
-@@ -891,7 +885,6 @@ static bool perform_clock_recovery_sequence(
- 				&dpcd_lane_status_updated,
- 				&req_settings);
- 
--
- 		/* 5. check CR done*/
- 		if (is_cr_done(lane_count, dpcd_lane_status))
- 			return true;
-@@ -909,7 +902,6 @@ static bool perform_clock_recovery_sequence(
- 		else
- 			retries_cr = 0;
- 
--
- 			/* 8. update VS/PE/PC2 in lt_settings*/
- 			update_drive_settings(lt_settings, req_settings);
- 
-@@ -1125,7 +1117,7 @@ static enum clock_source_id get_clock_source_id_for_link_training(
- 	set.surface_count = 0;
- 	set.target = target;
- 
--	context = dm_alloc(link->ctx, sizeof(struct validate_context));
-+	context = dm_alloc(sizeof(struct validate_context));
- 
- 	if (!context)
- 		goto fail_context;
-@@ -1139,7 +1131,7 @@ static enum clock_source_id get_clock_source_id_for_link_training(
- 	if (result)
- 		id = context->res_ctx.pipe_ctx[0].clock_source->id;
- 
--	dm_free(link->ctx, context);
-+	dm_free(context);
- fail_context:
- 	dc_target_release(target);
- fail_target:
-@@ -1575,7 +1567,6 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 		hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
- 		return false;
- 
--
- 	/* For now we only handle 'Downstream port status' case. */
- 	/* If we got sink count changed it means Downstream port status changed,
- 	 * then DM should call DC to do the detection. */
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 3f05723..63ff4b0 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -12,7 +12,6 @@
- #include "dce110/dce110_link_encoder.h"
- #include "dce110/dce110_stream_encoder.h"
- 
--
- enum dc_status core_link_read_dpcd(
- 	struct core_link* link,
- 	uint32_t address,
-@@ -131,7 +130,6 @@ bool dp_set_hw_training_pattern(
- 	return true;
- }
- 
--
- void dp_set_hw_lane_settings(
- 	struct core_link *link,
- 	const struct link_training_settings *link_settings)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 013612a..e397751 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -80,7 +80,6 @@ void unreference_clock_source(
- 		}
- 	}
- 
--
- }
- 
- void reference_clock_source(
-@@ -186,7 +185,6 @@ static enum pixel_format convert_pixel_format_to_dalsurface(
- 		dal_pixel_format = PIXEL_FORMAT_FP16;
- 		break;
- 
--
- 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
- 		dal_pixel_format = PIXEL_FORMAT_420BPP12;
- 		break;
-@@ -248,7 +246,6 @@ static void calculate_overscan(
- 						pipe_ctx->scl_data.ratios.horz)) -
- 						pipe_ctx->scl_data.overscan.left;
- 
--
- 	pipe_ctx->scl_data.overscan.top = stream->public.dst.y;
- 	if (stream->public.src.y < surface->clip_rect.y)
- 		pipe_ctx->scl_data.overscan.top += (surface->clip_rect.y
-@@ -266,7 +263,6 @@ static void calculate_overscan(
- 						pipe_ctx->scl_data.ratios.vert)) -
- 						pipe_ctx->scl_data.overscan.top;
- 
--
- 	/* TODO: Add timing overscan to finalize overscan calculation*/
- }
- 
-@@ -406,7 +402,6 @@ bool attach_surfaces_to_context(
- 		return false;
- 	}
- 
--
- 	/* retain new surfaces */
- 	for (i = 0; i < surface_count; i++)
- 		dc_surface_retain(surfaces[i]);
-@@ -1011,7 +1006,6 @@ static void set_avi_info_frame(
- 	info_frame.avi_info_packet.info_packet_hdmi.bits.Y0_Y1_Y2 =
- 		pixel_encoding;
- 
--
- 	/* A0 = 1 Active Format Information valid */
- 	info_frame.avi_info_packet.info_packet_hdmi.bits.A0 =
- 		ACTIVE_FORMAT_VALID;
-@@ -1039,7 +1033,6 @@ static void set_avi_info_frame(
- 		info_frame.avi_info_packet.info_packet_hdmi.bits.C0_C1 =
- 				COLORIMETRY_NO_DATA;
- 
--
- 	/* TODO: un-hardcode aspect ratio */
- 	aspect = stream->public.timing.aspect_ratio;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-index c5a770e..67ae799 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_sink.c
-@@ -76,22 +76,19 @@ void dc_sink_retain(const struct dc_sink *dc_sink)
- 
- void dc_sink_release(const struct dc_sink *dc_sink)
- {
--	struct core_sink *core_sink = DC_SINK_TO_CORE(dc_sink);
- 	struct sink *sink = DC_SINK_TO_SINK(dc_sink);
- 
- 	--sink->ref_count;
- 
- 	if (sink->ref_count == 0) {
- 		destruct(sink);
--		dm_free(core_sink->ctx, sink);
-+		dm_free(sink);
- 	}
- }
- 
- struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
- {
--	struct core_link *core_link = DC_LINK_TO_LINK(init_params->link);
--
--	struct sink *sink = dm_alloc(core_link->ctx, sizeof(*sink));
-+	struct sink *sink = dm_alloc(sizeof(*sink));
- 
- 	if (NULL == sink)
- 		goto alloc_fail;
-@@ -105,7 +102,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
- 	return &sink->protected.public;
- 
- construct_fail:
--	dm_free(core_link->ctx, sink);
-+	dm_free(sink);
- 
- alloc_fail:
- 	return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index d7012bc..4ceee56 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -140,12 +140,11 @@ void dc_stream_release(struct dc_stream *public)
- {
- 	struct stream *stream = DC_STREAM_TO_STREAM(public);
- 	struct core_stream *protected = DC_STREAM_TO_CORE(public);
--	struct dc_context *ctx = protected->ctx;
- 	stream->ref_count--;
- 
- 	if (stream->ref_count == 0) {
- 		destruct(protected);
--		dm_free(ctx, stream);
-+		dm_free(stream);
- 	}
- }
- 
-@@ -157,7 +156,7 @@ struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink)
- 	if (sink == NULL)
- 		goto alloc_fail;
- 
--	stream = dm_alloc(sink->ctx, sizeof(struct stream));
-+	stream = dm_alloc(sizeof(struct stream));
- 
- 	if (NULL == stream)
- 		goto alloc_fail;
-@@ -170,7 +169,7 @@ struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink)
- 	return &stream->protected.public;
- 
- construct_fail:
--	dm_free(sink->ctx, stream);
-+	dm_free(stream);
- 
- alloc_fail:
- 	return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 967b106..4a3d18d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -53,7 +53,6 @@ struct gamma {
- #define CORE_GAMMA_TO_GAMMA(core_gamma) \
- 	container_of(core_gamma, struct gamma, protected)
- 
--
- /*******************************************************************************
-  * Private functions
-  ******************************************************************************/
-@@ -82,7 +81,7 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 
- struct dc_surface *dc_create_surface(const struct core_dc *dc)
- {
--	struct surface *surface = dm_alloc(dc->ctx, sizeof(*surface));
-+	struct surface *surface = dm_alloc(sizeof(*surface));
- 
- 	if (NULL == surface)
- 		goto alloc_fail;
-@@ -95,7 +94,7 @@ struct dc_surface *dc_create_surface(const struct core_dc *dc)
- 	return &surface->protected.public;
- 
- construct_fail:
--	dm_free(dc->ctx, surface);
-+	dm_free(surface);
- 
- alloc_fail:
- 	return NULL;
-@@ -115,7 +114,7 @@ void dc_surface_release(const struct dc_surface *dc_surface)
- 
- 	if (surface->ref_count == 0) {
- 		destruct(surface);
--		dm_free(surface->protected.ctx, surface);
-+		dm_free(surface);
- 	}
- }
- 
-@@ -143,14 +142,13 @@ void dc_gamma_release(const struct dc_gamma *dc_gamma)
- 
- 	if (gamma->ref_count == 0) {
- 		destruct_gamma(gamma);
--		dm_free(gamma->protected.ctx, gamma);
-+		dm_free(gamma);
- 	}
- }
- 
--
- struct dc_gamma *dc_create_gamma(const struct core_dc *dc)
- {
--	struct gamma *gamma = dm_alloc(dc->ctx, sizeof(*gamma));
-+	struct gamma *gamma = dm_alloc(sizeof(*gamma));
- 
- 	if (gamma == NULL)
- 		goto alloc_fail;
-@@ -163,7 +161,7 @@ struct dc_gamma *dc_create_gamma(const struct core_dc *dc)
- 	return &gamma->protected.public;
- 
- construct_fail:
--	dm_free(dc->ctx, gamma);
-+	dm_free(gamma);
- 
- alloc_fail:
- 	return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index e1fce1c..c697a5e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -83,7 +83,7 @@ void dc_target_release(struct dc_target *dc_target)
- 	target->ref_count--;
- 	if (target->ref_count == 0) {
- 		destruct(protected);
--		dm_free(protected->ctx, target);
-+		dm_free(target);
- 	}
- }
- 
-@@ -113,7 +113,7 @@ struct dc_target *dc_create_target_for_streams(
- 
- 	stream = DC_STREAM_TO_CORE(dc_streams[0]);
- 
--	target = dm_alloc(stream->ctx, sizeof(struct target));
-+	target = dm_alloc(sizeof(struct target));
- 
- 	if (NULL == target)
- 		goto target_alloc_fail;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 68a63cf..aacdefe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -422,7 +422,6 @@ struct dc_sink_init_data {
- 
- struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
- 
--
- /*******************************************************************************
-  * Cursor interfaces - To manages the cursor within a target
-  ******************************************************************************/
-@@ -471,8 +470,6 @@ bool dc_set_cursor_position(
- 		struct dc_cursor *cursor,
- 		struct dc_cursor_position *pos);
- 
--
--
- /*******************************************************************************
-  * Interrupt interfaces
-  ******************************************************************************/
-@@ -488,7 +485,6 @@ const struct dc_target *dc_get_target_on_irq_source(
- 		const struct core_dc *dc,
- 		enum dc_irq_source src);
- 
--
- /*******************************************************************************
-  * Power Interfaces
-  ******************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index 53f0477..7def8dd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -38,7 +38,6 @@
- 
- #include "include/bios_parser_types.h"
- 
--
- struct dc_vbios_funcs {
- 	uint8_t (*get_connectors_number)(struct dc_bios *bios);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
-index c74d99c..5f2107f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
-@@ -61,7 +61,6 @@ struct ddc {
- 	struct dc_context *ctx;
- };
- 
--
- union ddc_wa {
- 	struct {
- 		uint32_t DP_SKIP_POWER_OFF:1;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index 82e3afb..03b95e9 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -251,7 +251,6 @@ enum dc_rotation_angle {
- 	ROTATION_ANGLE_COUNT
- };
- 
--
- struct dc_cursor_position {
- 	uint32_t x;
- 	uint32_t y;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index f764d37..b737206 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -212,13 +212,11 @@ enum plane_stereo_format {
- 	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
- };
- 
--
- /* TODO: Find way to calculate number of bits
-  *  Please increase if pixel_format enum increases
-  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-  */
- 
--
- enum dc_edid_connector_type {
- 	EDID_CONNECTOR_UNKNOWN = 0,
- 	EDID_CONNECTOR_ANALOG = 1,
-@@ -293,7 +291,6 @@ struct dc_resolution {
- 	uint32_t height;
- };
- 
--
- struct dc_mode_flags {
- 	/* note: part of refresh rate flag*/
- 	uint32_t INTERLACE :1;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index a1c1d1c..c759081 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -75,7 +75,6 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
- #define HW_REG_CRTC(reg, id)\
- 	(reg + reg_offsets[id].crtc)
- 
--
- /*******************************************************************************
-  * Private definitions
-  ******************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index bc9fd02..6260751 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -139,7 +139,6 @@ static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
- 	}
- };
- 
--
- static const struct dce110_clk_src_reg_offsets dce100_clk_src_reg_offsets[] = {
- 	{
- 		.pll_cntl = mmBPHYC_PLL0_PLL_CNTL,
-@@ -211,7 +210,6 @@ static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
- }
- };
- 
--
- static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
- 		.BL_PWM_CNTL = mmBL_PWM_CNTL,
- 		.BL_PWM_GRP1_REG_LOCK = mmBL_PWM_GRP1_REG_LOCK,
-@@ -339,7 +337,6 @@ static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
- }
- };
- 
--
- static struct timing_generator *dce100_timing_generator_create(
- 		struct adapter_service *as,
- 		struct dc_context *ctx,
-@@ -347,7 +344,7 @@ static struct timing_generator *dce100_timing_generator_create(
- 		const struct dce110_timing_generator_offsets *offsets)
- {
- 	struct dce110_timing_generator *tg110 =
--		dm_alloc(ctx, sizeof(struct dce110_timing_generator));
-+		dm_alloc(sizeof(struct dce110_timing_generator));
- 
- 	if (!tg110)
- 		return NULL;
-@@ -357,7 +354,7 @@ static struct timing_generator *dce100_timing_generator_create(
- 		return &tg110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, tg110);
-+	dm_free(tg110);
- 	return NULL;
- }
- 
-@@ -368,7 +365,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
- 	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
--		dm_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+		dm_alloc(sizeof(struct dce110_stream_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -377,7 +374,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, enc110);
-+	dm_free(enc110);
- 	return NULL;
- }
- 
-@@ -387,7 +384,7 @@ static struct mem_input *dce100_mem_input_create(
- 	const struct dce110_mem_input_reg_offsets *offset)
- {
- 	struct dce110_mem_input *mem_input110 =
--		dm_alloc(ctx, sizeof(struct dce110_mem_input));
-+		dm_alloc(sizeof(struct dce110_mem_input));
- 
- 	if (!mem_input110)
- 		return NULL;
-@@ -397,13 +394,13 @@ static struct mem_input *dce100_mem_input_create(
- 		return &mem_input110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, mem_input110);
-+	dm_free(mem_input110);
- 	return NULL;
- }
- 
- static void dce100_transform_destroy(struct transform **xfm)
- {
--	dm_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	dm_free(TO_DCE110_TRANSFORM(*xfm));
- 	*xfm = NULL;
- }
- 
-@@ -413,7 +410,7 @@ static struct transform *dce100_transform_create(
- 	const struct dce110_transform_reg_offsets *offsets)
- {
- 	struct dce110_transform *transform =
--		dm_alloc(ctx, sizeof(struct dce110_transform));
-+		dm_alloc(sizeof(struct dce110_transform));
- 
- 	if (!transform)
- 		return NULL;
-@@ -422,7 +419,7 @@ static struct transform *dce100_transform_create(
- 		return &transform->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, transform);
-+	dm_free(transform);
- 	return NULL;
- }
- 
-@@ -432,7 +429,7 @@ static struct input_pixel_processor *dce100_ipp_create(
- 	const struct dce110_ipp_reg_offsets *offsets)
- {
- 	struct dce110_ipp *ipp =
--		dm_alloc(ctx, sizeof(struct dce110_ipp));
-+		dm_alloc(sizeof(struct dce110_ipp));
- 
- 	if (!ipp)
- 		return NULL;
-@@ -441,7 +438,7 @@ static struct input_pixel_processor *dce100_ipp_create(
- 		return &ipp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, ipp);
-+	dm_free(ipp);
- 	return NULL;
- }
- 
-@@ -449,9 +446,7 @@ struct link_encoder *dce100_link_encoder_create(
- 	const struct encoder_init_data *enc_init_data)
- {
- 	struct dce110_link_encoder *enc110 =
--		dm_alloc(
--			enc_init_data->ctx,
--			sizeof(struct dce110_link_encoder));
-+		dm_alloc(sizeof(struct dce110_link_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -465,18 +460,17 @@ struct link_encoder *dce100_link_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(enc_init_data->ctx, enc110);
-+	dm_free(enc110);
- 	return NULL;
- }
- 
--
- struct output_pixel_processor *dce100_opp_create(
- 	struct dc_context *ctx,
- 	uint32_t inst,
- 	const struct dce110_opp_reg_offsets *offset)
- {
- 	struct dce110_opp *opp =
--		dm_alloc(ctx, sizeof(struct dce110_opp));
-+		dm_alloc(sizeof(struct dce110_opp));
- 
- 	if (!opp)
- 		return NULL;
-@@ -486,24 +480,23 @@ struct output_pixel_processor *dce100_opp_create(
- 		return &opp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, opp);
-+	dm_free(opp);
- 	return NULL;
- }
- 
--
- void dce100_opp_destroy(struct output_pixel_processor **opp)
- {
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user);
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coeff128);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_user);
-+	dm_free(FROM_DCE11_OPP(*opp));
- 	*opp = NULL;
- }
- 
-@@ -514,7 +507,7 @@ struct clock_source *dce100_clock_source_create(
- 	const struct dce110_clk_src_reg_offsets *offsets)
- {
- 	struct dce110_clk_src *clk_src =
--		dm_alloc(ctx, sizeof(struct dce110_clk_src));
-+		dm_alloc(sizeof(struct dce110_clk_src));
- 
- 	if (!clk_src)
- 		return NULL;
-@@ -528,7 +521,7 @@ struct clock_source *dce100_clock_source_create(
- 
- void dce100_clock_source_destroy(struct clock_source **clk_src)
- {
--	dm_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	dm_free(TO_DCE110_CLK_SRC(*clk_src));
- 	*clk_src = NULL;
- }
- 
-@@ -547,22 +540,19 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dm_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dm_free(pool->timing_generators[i]->ctx,
--					DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dm_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
-@@ -1147,8 +1137,7 @@ bool dce100_construct_resource_pool(
- stream_enc_create_fail:
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dm_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- audio_create_fail:
-@@ -1169,14 +1158,12 @@ controller_create_fail:
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dm_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dm_free(pool->timing_generators[i]->ctx,
--				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-index 65cd170..c332869 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
-@@ -13,7 +13,6 @@ struct core_dc;
- struct resource_pool;
- struct dc_validation_set;
- 
--
- bool dce100_construct_resource_pool(
- 	struct adapter_service *adapter_serv,
- 	uint8_t num_virtual_links,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index ba2929b..033afe8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -225,7 +225,6 @@ static bool calc_fb_divider_checking_tolerance(
- 	return false;
- }
- 
--
- static bool calc_pll_dividers_in_range(
- 		struct calc_pll_clock_source *calc_pll_cs,
- 		struct pll_settings *pll_settings,
-@@ -582,11 +581,8 @@ static bool calculate_ss(
- 	if (pll_settings == NULL)
- 		return false;
- 
--
- 	dm_memset(ds_data, 0, sizeof(struct delta_sigma_data));
- 
--
--
- 	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
- 	/* 6 decimal point support in fractional feedback divider */
- 	fb_div  = dal_fixed32_32_from_fraction(
-@@ -616,7 +612,6 @@ static bool calculate_ss(
- 		pll_settings->reference_freq * 1000,
- 		pll_settings->reference_divider * ss_data->modulation_freq_hz);
- 
--
- 	if (ss_data->flags.CENTER_SPREAD)
- 		modulation_time = dal_fixed32_32_div_int(modulation_time, 4);
- 	else
-@@ -829,7 +824,6 @@ static struct clock_source_funcs dce110_clk_src_funcs = {
- 	.get_pix_clk_dividers = dce110_get_pix_clk_dividers
- };
- 
--
- static void get_ss_info_from_atombios(
- 		struct dce110_clk_src *clk_src,
- 		enum as_signal_type as_signal,
-@@ -868,14 +862,12 @@ static void get_ss_info_from_atombios(
- 	if (*ss_entries_num == 0)
- 		return;
- 
--	ss_info = dm_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_info)
--				* (*ss_entries_num));
-+	ss_info = dm_alloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num));
- 	ss_info_cur = ss_info;
- 	if (ss_info == NULL)
- 		return;
- 
--	ss_data = dm_alloc(clk_src->base.ctx, sizeof(struct spread_spectrum_data) *
--							(*ss_entries_num));
-+	ss_data = dm_alloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num));
- 	if (ss_data == NULL)
- 		goto out_free_info;
- 
-@@ -949,14 +941,14 @@ static void get_ss_info_from_atombios(
- 	}
- 
- 	*spread_spectrum_data = ss_data;
--	dm_free(clk_src->base.ctx, ss_info);
-+	dm_free(ss_info);
- 	return;
- 
- out_free_data:
--	dm_free(clk_src->base.ctx, ss_data);
-+	dm_free(ss_data);
- 	*ss_entries_num = 0;
- out_free_info:
--	dm_free(clk_src->base.ctx, ss_info);
-+	dm_free(ss_info);
- }
- 
- static void ss_info_from_atombios_create(
-@@ -1160,4 +1152,3 @@ unexpected_failure:
- 	return false;
- }
- 
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-index 285d544..5b55ce8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-@@ -280,8 +280,6 @@ static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
- 	return lpt_control;
- }
- 
--
--
- static bool is_source_bigger_than_epanel_size(
- 	struct dce110_compressor *cp110,
- 	uint32_t source_view_width,
-@@ -753,7 +751,6 @@ void dce110_compressor_program_lpt_control(
-  * DCE 11 Frame Buffer Compression Implementation
-  */
- 
--
- void dce110_compressor_set_fbc_invalidation_triggers(
- 	struct compressor *compressor,
- 	uint32_t fbc_trigger)
-@@ -866,7 +863,7 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx,
- 	struct adapter_service *as)
- {
- 	struct dce110_compressor *cp110 =
--		dm_alloc(ctx, sizeof(struct dce110_compressor));
-+		dm_alloc(sizeof(struct dce110_compressor));
- 
- 	if (!cp110)
- 		return NULL;
-@@ -875,12 +872,12 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx,
- 		return &cp110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, cp110);
-+	dm_free(cp110);
- 	return NULL;
- }
- 
- void dce110_compressor_destroy(struct compressor **compressor)
- {
--	dm_free((*compressor)->ctx, TO_DCE110_COMPRESSOR(*compressor));
-+	dm_free(TO_DCE110_COMPRESSOR(*compressor));
- 	*compressor = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 68dc378..716a762 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -101,7 +101,6 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
- #define HW_REG_CRTC(reg, id)\
- 	(reg + reg_offsets[id].crtc)
- 
--
- #define MAX_WATERMARK 0xFFFF
- #define SAFE_NBP_MARK 0x7FFF
- 
-@@ -408,7 +407,6 @@ static void dce110_set_blender_mode(
- 		BLND_CONTROL,
- 		BLND_MULTIPLIED_MODE);
- 
--
- 	dm_write_reg(ctx, addr, value);
- }
- 
-@@ -506,7 +504,6 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
- 	}
- }
- 
--
- static bool set_gamma_ramp(
- 	struct input_pixel_processor *ipp,
- 	struct output_pixel_processor *opp,
-@@ -518,18 +515,16 @@ static bool set_gamma_ramp(
- 	struct temp_params *temp_params;
- 	bool result = false;
- 
--	prescale_params = dm_alloc(opp->ctx,
--			sizeof(struct ipp_prescale_params));
-+	prescale_params = dm_alloc(sizeof(struct ipp_prescale_params));
- 
- 	if (prescale_params == NULL)
- 		goto prescale_alloc_fail;
- 
--	regamma_params = dm_alloc(opp->ctx,
--			sizeof(struct pwl_params));
-+	regamma_params = dm_alloc(sizeof(struct pwl_params));
- 	if (regamma_params == NULL)
- 		goto regamma_alloc_fail;
- 
--	temp_params = dm_alloc(opp->ctx, sizeof(struct temp_params));
-+	temp_params = dm_alloc(sizeof(struct temp_params));
- 
- 	if (temp_params == NULL)
- 		goto temp_alloc_fail;
-@@ -558,14 +553,14 @@ static bool set_gamma_ramp(
- 
- 	opp->funcs->opp_power_on_regamma_lut(opp, false);
- 
--	dm_free(opp->ctx, temp_params);
-+	dm_free(temp_params);
- 
- 	result = true;
- 
- temp_alloc_fail:
--	dm_free(opp->ctx, regamma_params);
-+	dm_free(regamma_params);
- regamma_alloc_fail:
--	dm_free(opp->ctx, prescale_params);
-+	dm_free(prescale_params);
- prescale_alloc_fail:
- 	return result;
- }
-@@ -641,7 +636,6 @@ static void update_info_frame(struct pipe_ctx *pipe_ctx)
- 			&pipe_ctx->encoder_info_frame);
- }
- 
--
- static void enable_stream(struct pipe_ctx *pipe_ctx)
- {
- 	enum dc_lane_count lane_count =
-@@ -905,7 +899,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 	return DC_OK;
- }
- 
--
- /******************************************************************************/
- 
- static void power_down_encoders(struct core_dc *dc)
-@@ -1064,7 +1057,6 @@ static bool dc_set_clocks_and_clock_state (
- 	struct display_clock *disp_clk = context->res_ctx.pool.display_clock;
- 	struct dc_context *ctx = context->targets[0]->ctx;
- 
--
- 	if (!dc_pre_clock_change(
- 			ctx,
- 			&context->res_ctx.min_clocks,
-@@ -1092,7 +1084,6 @@ static bool dc_set_clocks_and_clock_state (
- 		dm_error("DC: failed to set minimum clock state!\n");
- 	}
- 
--
- 	/*bm_clk_info.max_mclk_khz = output.max_mclk;
- 	bm_clk_info.min_mclk_khz = output.min_mclk;
- 	bm_clk_info.max_sclk_khz = output.max_sclk;
-@@ -1174,7 +1165,6 @@ static void set_displaymarks(
- 	}
- }
- 
--
- static void set_safe_displaymarks(struct resource_context *res_ctx)
- {
- 	uint8_t i;
-@@ -1294,7 +1284,6 @@ static enum dc_status apply_ctx_to_hw(
- 	return DC_OK;
- }
- 
--
- /*******************************************************************************
-  * Front End programming
-  ******************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-index e67b7e6..3a9756d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
-@@ -57,6 +57,6 @@ bool dce110_ipp_construct(
- 
- void dce110_ipp_destroy(struct input_pixel_processor **ipp)
- {
--	dm_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
-+	dm_free(TO_DCE110_IPP(*ipp));
- 	*ipp = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-index 0004d7a..b20a8e7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
-@@ -28,7 +28,6 @@
- 
- #include "ipp.h"
- 
--
- struct gamma_parameters;
- struct dev_c_lut;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-index eaa1f05..2dabaed 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-@@ -70,7 +70,6 @@ static void program_address(
- 	struct dce110_ipp *ipp110,
- 	PHYSICAL_ADDRESS_LOC address);
- 
--
- void dce110_ipp_cursor_set_position(
- 	struct input_pixel_processor *ipp,
- 	const struct dc_cursor_position *position)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index d1fa4a7..e412804 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -156,5 +156,4 @@ void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
- 	struct link_encoder *enc,
- 	uint32_t index);
- 
--
- #endif /* __DC_LINK_ENCODER__DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index d9dab36..b1f1135 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -36,7 +36,6 @@
- 
- #include "dce110_mem_input.h"
- 
--
- #define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
- #define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
- #define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
-@@ -287,7 +286,6 @@ static void program_size_and_rotation(
- 		DCP_REG(mmGRPH_PITCH),
- 		value);
- 
--
- 	value = 0;
- 	switch (rotation) {
- 	case ROTATION_ANGLE_90:
-@@ -338,7 +336,6 @@ static void program_pixel_format(
- 			DCP_REG(mmGRPH_SWAP_CNTL),
- 			value);
- 
--
- 		value =	dm_read_reg(
- 				mem_input110->base.ctx,
- 				DCP_REG(mmGRPH_CONTROL));
-@@ -508,7 +505,6 @@ static void program_urgency_watermark(
- 		URGENCY_HIGH_WATERMARK);
- 	dm_write_reg(ctx, urgency_addr, urgency_cntl);
- 
--
- 	/*Write mask to enable reading/writing of watermark set B*/
- 	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- 	set_reg_field_value(wm_mask_cntl,
-@@ -812,7 +808,6 @@ void dce110_allocate_mem_input(
- 				"%s: DMIF allocation failed",
- 				__func__);
- 
--
- 	if (pix_clk_khz != 0) {
- 		addr = mmDPG_PIPE_ARBITRATION_CONTROL1 + bm110->offsets.dmif;
- 		value = dm_read_reg(mi->ctx, addr);
-@@ -955,6 +950,6 @@ bool dce110_mem_input_construct(
- 
- void dce110_mem_input_destroy(struct mem_input **mem_input)
- {
--	dm_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
-+	dm_free(TO_DCE110_MEM_INPUT(*mem_input));
- 	*mem_input = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 0383178..32ee571 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -36,7 +36,6 @@ struct dce110_mem_input_reg_offsets {
- 	uint32_t pipe;
- };
- 
--
- enum stutter_mode_type {
- /*	TODO: Clean up these enums, right now only one is being used
-  *	STUTTER_MODE_LEGACY = 0X00000001,
-@@ -129,5 +128,4 @@ bool  dce110_mem_input_program_surface_config(
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation);
- 
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-index 08620e6..acfbd08 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-@@ -36,12 +36,10 @@
- 
- #include "dce110_mem_input.h"
- 
--
- #define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
- /*#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)*/
- /*#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)*/
- 
--
- static const struct dce110_mem_input_reg_offsets dce110_mi_v_reg_offsets[] = {
- 	{
- 		.dcp = 0,
-@@ -575,7 +573,6 @@ static void program_urgency_watermark(
- 		URGENCY_HIGH_WATERMARK);
- 	dm_write_reg(ctx, urgency_addr, urgency_cntl);
- 
--
- 	/*Write mask to enable reading/writing of watermark set B*/
- 	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
- 	set_reg_field_value(wm_mask_cntl,
-@@ -727,7 +724,6 @@ static void program_nbp_watermark(
- 		NB_PSTATE_CHANGE_WATERMARK_MASK);
- 	dm_write_reg(ctx, wm_mask_ctrl_addr, value);
- 
--
- 	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
- 
- 	set_reg_field_value(
-@@ -847,7 +843,6 @@ void dce110_mem_input_v_program_display_marks(
- 		stutter);
- }
- 
--
- void dce110_allocate_mem_input_v(
- 	struct mem_input *mi,
- 	uint32_t h_total,/* for current stream */
-@@ -899,7 +894,7 @@ bool dce110_mem_input_v_construct(
- #if 0
- void dce110_mem_input_v_destroy(struct mem_input **mem_input)
- {
--	dm_free((*mem_input)->ctx, TO_DCE110_MEM_INPUT(*mem_input));
-+	dm_free(TO_DCE110_MEM_INPUT(*mem_input));
- 	*mem_input = NULL;
- }
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-index 24b4211..3df346b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
-@@ -80,5 +80,4 @@ bool  dce110_mem_input_v_program_surface_config(
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation);
- 
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-index ab937d5..d3da726 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
-@@ -72,7 +72,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
- 
- void dce110_opp_destroy(struct output_pixel_processor **opp)
- {
--	dm_free((*opp)->ctx, FROM_DCE11_OPP(*opp));
-+	dm_free(FROM_DCE11_OPP(*opp));
- 	*opp = NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-index abb5a5d..a0b6d8e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
-@@ -130,7 +130,6 @@ void dce110_opp_program_clamping_and_pixel_encoding(
- 	struct output_pixel_processor *opp,
- 	const struct clamping_and_pixel_encoding_params *params);
- 
--
- void dce110_opp_set_dyn_expansion(
- 	struct output_pixel_processor *opp,
- 	enum dc_color_space color_sp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-index e4f4fe0..8b9725c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
-@@ -482,7 +482,6 @@ static void program_pwl(
- 	dm_write_reg(opp110->base.ctx, DCFE_REG(mmDCFE_MEM_PWR_CTRL), value);
- }
- 
--
- bool dce110_opp_program_regamma_pwl(
- 	struct output_pixel_processor *opp,
- 	const struct pwl_params *params)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-index 8babd01..7413db4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_v.c
-@@ -70,6 +70,3 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110,
- 	return true;
- }
- 
--
--
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index cdd1f94..99484f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -254,7 +254,6 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
- 		stream_enc_regs(6)
- };
- 
--
- /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
- static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = {
- {
-@@ -285,7 +284,6 @@ static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = {
- }
- };
- 
--
- static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = {
- 	{
- 		.pll_cntl = mmBPHYC_PLL0_PLL_CNTL,
-@@ -304,7 +302,7 @@ static struct timing_generator *dce110_timing_generator_create(
- 		const struct dce110_timing_generator_offsets *offsets)
- {
- 	struct dce110_timing_generator *tg110 =
--		dm_alloc(ctx, sizeof(struct dce110_timing_generator));
-+		dm_alloc(sizeof(struct dce110_timing_generator));
- 
- 	if (!tg110)
- 		return NULL;
-@@ -313,7 +311,7 @@ static struct timing_generator *dce110_timing_generator_create(
- 		return &tg110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, tg110);
-+	dm_free(tg110);
- 	return NULL;
- }
- 
-@@ -324,7 +322,7 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
--		dm_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+		dm_alloc(sizeof(struct dce110_stream_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -333,7 +331,7 @@ static struct stream_encoder *dce110_stream_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, enc110);
-+	dm_free(enc110);
- 	return NULL;
- }
- 
-@@ -343,7 +341,7 @@ static struct mem_input *dce110_mem_input_create(
- 	const struct dce110_mem_input_reg_offsets *offset)
- {
- 	struct dce110_mem_input *mem_input110 =
--		dm_alloc(ctx, sizeof(struct dce110_mem_input));
-+		dm_alloc(sizeof(struct dce110_mem_input));
- 
- 	if (!mem_input110)
- 		return NULL;
-@@ -353,13 +351,13 @@ static struct mem_input *dce110_mem_input_create(
- 		return &mem_input110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, mem_input110);
-+	dm_free(mem_input110);
- 	return NULL;
- }
- 
- static void dce110_transform_destroy(struct transform **xfm)
- {
--	dm_free((*xfm)->ctx, TO_DCE110_TRANSFORM(*xfm));
-+	dm_free(TO_DCE110_TRANSFORM(*xfm));
- 	*xfm = NULL;
- }
- 
-@@ -369,7 +367,7 @@ static struct transform *dce110_transform_create(
- 	const struct dce110_transform_reg_offsets *offsets)
- {
- 	struct dce110_transform *transform =
--		dm_alloc(ctx, sizeof(struct dce110_transform));
-+		dm_alloc(sizeof(struct dce110_transform));
- 
- 	if (!transform)
- 		return NULL;
-@@ -378,7 +376,7 @@ static struct transform *dce110_transform_create(
- 		return &transform->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, transform);
-+	dm_free(transform);
- 	return NULL;
- }
- 
-@@ -388,7 +386,7 @@ static struct input_pixel_processor *dce110_ipp_create(
- 	const struct dce110_ipp_reg_offsets *offsets)
- {
- 	struct dce110_ipp *ipp =
--		dm_alloc(ctx, sizeof(struct dce110_ipp));
-+		dm_alloc(sizeof(struct dce110_ipp));
- 
- 	if (!ipp)
- 		return NULL;
-@@ -397,7 +395,7 @@ static struct input_pixel_processor *dce110_ipp_create(
- 		return &ipp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, ipp);
-+	dm_free(ipp);
- 	return NULL;
- }
- 
-@@ -405,9 +403,7 @@ struct link_encoder *dce110_link_encoder_create(
- 	const struct encoder_init_data *enc_init_data)
- {
- 	struct dce110_link_encoder *enc110 =
--		dm_alloc(
--			enc_init_data->ctx,
--			sizeof(struct dce110_link_encoder));
-+		dm_alloc(sizeof(struct dce110_link_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -421,24 +417,23 @@ struct link_encoder *dce110_link_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(enc_init_data->ctx, enc110);
-+	dm_free(enc110);
- 	return NULL;
- }
- 
- void dce110_link_encoder_destroy(struct link_encoder **enc)
- {
--	dm_free((*enc)->ctx, TO_DCE110_LINK_ENC(*enc));
-+	dm_free(TO_DCE110_LINK_ENC(*enc));
- 	*enc = NULL;
- }
- 
--
- static struct output_pixel_processor *dce110_opp_create(
- 	struct dc_context *ctx,
- 	uint32_t inst,
- 	const struct dce110_opp_reg_offsets *offsets)
- {
- 	struct dce110_opp *opp =
--		dm_alloc(ctx, sizeof(struct dce110_opp));
-+		dm_alloc(sizeof(struct dce110_opp));
- 
- 	if (!opp)
- 		return NULL;
-@@ -448,7 +443,7 @@ static struct output_pixel_processor *dce110_opp_create(
- 		return &opp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, opp);
-+	dm_free(opp);
- 	return NULL;
- }
- 
-@@ -459,7 +454,7 @@ struct clock_source *dce110_clock_source_create(
- 	const struct dce110_clk_src_reg_offsets *offsets)
- {
- 	struct dce110_clk_src *clk_src =
--		dm_alloc(ctx, sizeof(struct dce110_clk_src));
-+		dm_alloc(sizeof(struct dce110_clk_src));
- 
- 	if (!clk_src)
- 		return NULL;
-@@ -473,7 +468,7 @@ struct clock_source *dce110_clock_source_create(
- 
- void dce110_clock_source_destroy(struct clock_source **clk_src)
- {
--	dm_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	dm_free(TO_DCE110_CLK_SRC(*clk_src));
- 	*clk_src = NULL;
- }
- 
-@@ -492,21 +487,19 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dm_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dm_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dm_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
-@@ -1059,10 +1052,10 @@ static struct resource_funcs dce110_res_pool_funcs = {
- 
- static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
- {
--	struct dce110_timing_generator *dce110_tgv = dm_alloc(ctx, sizeof (*dce110_tgv));
--	struct dce110_transform *dce110_xfmv = dm_alloc(ctx, sizeof (*dce110_xfmv));
--	struct dce110_mem_input *dce110_miv = dm_alloc(ctx, sizeof (*dce110_miv));
--	struct dce110_opp *dce110_oppv = dm_alloc(ctx, sizeof (*dce110_oppv));
-+	struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv));
-+	struct dce110_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv));
-+	struct dce110_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv));
-+	struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv));
- 
- 	dce110_opp_v_construct(dce110_oppv, ctx);
- 	dce110_timing_generator_v_construct(dce110_tgv, pool->adapter_srv, ctx);
-@@ -1271,8 +1264,7 @@ bool dce110_construct_resource_pool(
- stream_enc_create_fail:
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dm_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- audio_create_fail:
-@@ -1293,14 +1285,12 @@ controller_create_fail:
- 			dce110_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dm_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dm_free(pool->timing_generators[i]->ctx,
--				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 59ec7f4..ceb91fc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -444,7 +444,6 @@ static void disable_stereo(struct timing_generator *tg)
- 	value = 0;
- 	dm_write_reg(tg->ctx, addr, value);
- 
--
- 	addr = tg->regs[IDX_CRTC_STEREO_CONTROL];
- 	dm_write_reg(tg->ctx, addr, value);
- }
-@@ -1196,7 +1195,6 @@ void dce110_timing_generator_setup_global_swap_lock(
- 	dm_write_reg(tg->ctx, address, value);
- }
- 
--
- void dce110_timing_generator_tear_down_global_swap_lock(
- 	struct timing_generator *tg)
- {
-@@ -1227,7 +1225,6 @@ void dce110_timing_generator_tear_down_global_swap_lock(
- 			DCP_GSL_CONTROL,
- 			DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
- 
--
- 	set_reg_field_value(value,
- 			0x6,
- 			DCP_GSL_CONTROL,
-@@ -1807,7 +1804,6 @@ bool dce110_tg_validate_timing(struct timing_generator *tg,
- 	return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
- }
- 
--
- void dce110_tg_wait_for_state(struct timing_generator *tg,
- 	enum crtc_state state)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index d09af97..005f22b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -26,7 +26,6 @@
- #ifndef __DC_TIMING_GENERATOR_DCE110_H__
- #define __DC_TIMING_GENERATOR_DCE110_H__
- 
--
- #include "timing_generator.h"
- #include "../include/grph_object_id.h"
- #include "../include/hw_sequencer_types.h"
-@@ -129,7 +128,6 @@ void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg);
- /* wait until TG is in beginning of active region */
- void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg);
- 
--
- /*********** Timing Generator Synchronization routines ****/
- 
- /* Setups Global Swap Lock group, TimingServer or TimingClient*/
-@@ -180,7 +178,6 @@ void dce110_timing_generator_color_space_to_black_color(
- 	struct crtc_black_color *black_color);
- /*************** End-of-move ********************/
- 
--
- /* Not called yet */
- void dce110_timing_generator_set_test_pattern(
- 	struct timing_generator *tg,
-@@ -226,7 +223,6 @@ bool dce110_tg_set_blank(struct timing_generator *tg,
- bool dce110_tg_validate_timing(struct timing_generator *tg,
- 	const struct dc_crtc_timing *timing);
- 
--
- void dce110_tg_wait_for_state(struct timing_generator *tg,
- 	enum crtc_state state);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index a7ea52e..10fc041 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -1,5 +1,3 @@
--
--
- #include "dm_services.h"
- 
- /* include DCE11 register header files */
-@@ -17,7 +15,6 @@
- 
- #include "timing_generator.h"
- 
--
- /** ********************************************************************************
-  *
-  * DCE11 Timing Generator Implementation
-@@ -591,7 +588,6 @@ static void dce110_timing_generator_v_set_colors(struct timing_generator *tg,
- 		dce110_timing_generator_v_set_overscan_color(tg, overscan_color);
- }
- 
--
- static void dce110_timing_generator_v_set_early_control(
- 		struct timing_generator *tg,
- 		uint32_t early_cntl)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index 4a5d54c..f8376f8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -103,7 +103,6 @@ static bool setup_scaling_configuration(
- 	set_reg_field_value(value, 1, SCL_MODE, SCL_PSCL_EN);
- 	dm_write_reg(ctx, addr, value);
- 
--
- 	addr = SCL_REG(mmSCL_TAP_CONTROL);
- 	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(value, data->taps.h_taps - 1,
-@@ -112,7 +111,6 @@ static bool setup_scaling_configuration(
- 			SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
- 	dm_write_reg(ctx, addr, value);
- 
--
- 	addr = SCL_REG(mmSCL_CONTROL);
- 	value = dm_read_reg(ctx, addr);
- 	 /* 1 - Replaced out of bound pixels with edge */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index 47ab396..17b72e7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -37,7 +37,6 @@
- 			"TRANSFORM SCALER:%s()\n", __func__)
- #define LB_TOTAL_NUMBER_OF_ENTRIES 1712
- 
--
- struct sclv_ratios_inits {
- 	uint32_t h_int_scale_ratio_luma;
- 	uint32_t h_int_scale_ratio_chroma;
-@@ -80,7 +79,6 @@ static void calculate_viewport(
- 	chroma_viewport->height = luma_viewport->height;
- 	chroma_viewport->width = luma_viewport->width;
- 
--
- 	if (scl_data->format == PIXEL_FORMAT_420BPP12) {
- 		luma_viewport->height += luma_viewport->height % 2;
- 		luma_viewport->width += luma_viewport->width % 2;
-@@ -94,7 +92,6 @@ static void calculate_viewport(
- 	}
- }
- 
--
- static void program_viewport(
- 	struct dce110_transform *xfm110,
- 	struct rect *luma_view_port,
-@@ -381,7 +378,6 @@ static void program_scl_ratios_inits(
- 		SCL_V_SCALE_RATIO);
- 	dm_write_reg(ctx, addr, value);
- 
--
- 	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
- 	value = 0;
- 	set_reg_field_value(
-@@ -400,7 +396,6 @@ static void program_scl_ratios_inits(
- 		SCL_V_SCALE_RATIO_C);
- 	dm_write_reg(ctx, addr, value);
- 
--
- 	addr = mmSCLV_HORZ_FILTER_INIT;
- 	value = 0;
- 	set_reg_field_value(
-@@ -429,7 +424,6 @@ static void program_scl_ratios_inits(
- 		SCL_V_INIT_INT);
- 	dm_write_reg(ctx, addr, value);
- 
--
- 	addr = mmSCLV_HORZ_FILTER_INIT_C;
- 	value = 0;
- 	set_reg_field_value(
-@@ -482,7 +476,6 @@ static bool dce110_transform_v_set_scaler(
- 	struct rect chroma_viewport = {0};
- 	struct dc_context *ctx = xfm->ctx;
- 
--
- 	/* 1. Calculate viewport, viewport programming should happen after init
- 	 * calculations as they may require an adjustment in the viewport.
- 	 */
-@@ -570,7 +563,6 @@ static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
- 	return true;
- }
- 
--
- static struct transform_funcs dce110_transform_v_funcs = {
- 	.transform_power_up =
- 		dce110_transform_v_power_up_line_buffer,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-index a3b767e..d7d0088 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-@@ -292,8 +292,6 @@ static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
- 	return lpt_control;
- }
- 
--
--
- static bool is_source_bigger_than_epanel_size(
- 	struct dce80_compressor *cp80,
- 	uint32_t source_view_width,
-@@ -734,7 +732,6 @@ void dce80_compressor_program_lpt_control(
-  * DCE 11 Frame Buffer Compression Implementation
-  */
- 
--
- void dce80_compressor_set_fbc_invalidation_triggers(
- 	struct compressor *compressor,
- 	uint32_t fbc_trigger)
-@@ -847,7 +844,7 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx,
- 	struct adapter_service *as)
- {
- 	struct dce80_compressor *cp80 =
--		dm_alloc(ctx, sizeof(struct dce80_compressor));
-+		dm_alloc(sizeof(struct dce80_compressor));
- 
- 	if (!cp80)
- 		return NULL;
-@@ -856,12 +853,12 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx,
- 		return &cp80->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, cp80);
-+	dm_free(cp80);
- 	return NULL;
- }
- 
- void dce80_compressor_destroy(struct compressor **compressor)
- {
--	dm_free((*compressor)->ctx, TO_DCE80_COMPRESSOR(*compressor));
-+	dm_free(TO_DCE80_COMPRESSOR(*compressor));
- 	*compressor = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-index 1502829..ef55de3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -90,8 +90,6 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
- #define HW_REG_CRTC(reg, id)\
- 	(reg + reg_offsets[id].crtc)
- 
--
--
- /*******************************************************************************
-  * Private definitions
-  ******************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c
-index 6dde1eb..2ddcffd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.c
-@@ -59,6 +59,6 @@ bool dce80_ipp_construct(
- 
- void dce80_ipp_destroy(struct input_pixel_processor **ipp)
- {
--	dm_free((*ipp)->ctx, TO_DCE80_IPP(*ipp));
-+	dm_free(TO_DCE80_IPP(*ipp));
- 	*ipp = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-index adf33cd..d350138 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp.h
-@@ -36,7 +36,6 @@ struct dce110_ipp_reg_offsets;
- struct gamma_parameters;
- struct dev_c_lut;
- 
--
- bool dce80_ipp_construct(
- 	struct dce110_ipp *ipp,
- 	struct dc_context *ctx,
-@@ -45,5 +44,4 @@ bool dce80_ipp_construct(
- 
- void dce80_ipp_destroy(struct input_pixel_processor **ipp);
- 
--
- #endif /*__DC_IPP_DCE80_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c
-index fdffb8c..eacb14e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_ipp_gamma.c
-@@ -43,16 +43,12 @@ enum {
- 	MAX_INPUT_LUT_ENTRY = 256
- };
- 
--
- /*PROTOTYPE DECLARATIONS*/
- 
--
- static void set_legacy_input_gamma_mode(
- 	struct dce110_ipp *ipp80,
- 	bool is_legacy);
- 
--
--
- void dce80_ipp_set_legacy_input_gamma_mode(
- 		struct input_pixel_processor *ipp,
- 		bool is_legacy)
-@@ -62,7 +58,6 @@ void dce80_ipp_set_legacy_input_gamma_mode(
- 	set_legacy_input_gamma_mode(ipp80, is_legacy);
- }
- 
--
- static void set_legacy_input_gamma_mode(
- 	struct dce110_ipp *ipp80,
- 	bool is_legacy)
-@@ -79,7 +74,3 @@ static void set_legacy_input_gamma_mode(
- 	dm_write_reg(ipp80->base.ctx, addr, value);
- }
- 
--
--
--
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-index 5288436..e8c9e86 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-@@ -209,7 +209,6 @@ static struct link_encoder_funcs dce80_lnk_enc_funcs = {
- 	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe
- };
- 
--
- bool dce80_link_encoder_construct(
- 	struct dce110_link_encoder *enc110,
- 	const struct encoder_init_data *init_data,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-index 86a79b2..27533bb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-@@ -37,7 +37,6 @@
- #include "../dce110/dce110_mem_input.h"
- #include "dce80_mem_input.h"
- 
--
- #define MAX_WATERMARK 0xFFFF
- #define SAFE_NBP_MARK 0x7FFF
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c
-index 82c98a1..9a3f674 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.c
-@@ -76,8 +76,6 @@ static const struct dce80_opp_reg_offsets reg_offsets[] = {
- }
- };
- 
--
--
- static struct opp_funcs funcs = {
- 		.opp_power_on_regamma_lut = dce80_opp_power_on_regamma_lut,
- 		.opp_program_bit_depth_reduction =
-@@ -116,7 +114,7 @@ bool dce80_opp_construct(struct dce80_opp *opp80,
- 
- void dce80_opp_destroy(struct output_pixel_processor **opp)
- {
--	dm_free((*opp)->ctx, FROM_OPP(*opp));
-+	dm_free(FROM_OPP(*opp));
- 	*opp = NULL;
- }
- 
-@@ -125,7 +123,7 @@ struct output_pixel_processor *dce80_opp_create(
- 	uint32_t inst)
- {
- 	struct dce80_opp *opp =
--		dm_alloc(ctx, sizeof(struct dce80_opp));
-+		dm_alloc(sizeof(struct dce80_opp));
- 
- 	if (!opp)
- 		return NULL;
-@@ -135,7 +133,7 @@ struct output_pixel_processor *dce80_opp_create(
- 		return &opp->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, opp);
-+	dm_free(opp);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-index a3b1c08..a8a8813 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp.h
-@@ -120,7 +120,6 @@ void dce80_opp_program_clamping_and_pixel_encoding(
- 	struct output_pixel_processor *opp,
- 	const struct clamping_and_pixel_encoding_params *params);
- 
--
- void dce80_opp_set_dyn_expansion(
- 	struct output_pixel_processor *opp,
- 	enum dc_color_space color_sp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-index 5b9663c..14362b4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
-@@ -490,7 +490,6 @@ static void program_pwl(
- 			value);
- }
- 
--
- void dce80_opp_power_on_regamma_lut(
- 	struct output_pixel_processor *opp,
- 	bool power_on)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index be8bba1..ae85fec 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -338,7 +338,7 @@ static struct timing_generator *dce80_timing_generator_create(
- 		const struct dce110_timing_generator_offsets *offsets)
- {
- 	struct dce110_timing_generator *tg110 =
--		dm_alloc(ctx, sizeof(struct dce110_timing_generator));
-+		dm_alloc(sizeof(struct dce110_timing_generator));
- 
- 	if (!tg110)
- 		return NULL;
-@@ -347,7 +347,7 @@ static struct timing_generator *dce80_timing_generator_create(
- 		return &tg110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, tg110);
-+	dm_free(tg110);
- 	return NULL;
- }
- 
-@@ -358,7 +358,7 @@ static struct stream_encoder *dce80_stream_encoder_create(
- 	const struct dce110_stream_enc_registers *regs)
- {
- 	struct dce110_stream_encoder *enc110 =
--		dm_alloc(ctx, sizeof(struct dce110_stream_encoder));
-+		dm_alloc(sizeof(struct dce110_stream_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -367,18 +367,17 @@ static struct stream_encoder *dce80_stream_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, enc110);
-+	dm_free(enc110);
- 	return NULL;
- }
- 
--
- static struct mem_input *dce80_mem_input_create(
- 	struct dc_context *ctx,
- 	uint32_t inst,
- 	const struct dce110_mem_input_reg_offsets *offsets)
- {
- 	struct dce110_mem_input *mem_input80 =
--		dm_alloc(ctx, sizeof(struct dce110_mem_input));
-+		dm_alloc(sizeof(struct dce110_mem_input));
- 
- 	if (!mem_input80)
- 		return NULL;
-@@ -388,13 +387,13 @@ static struct mem_input *dce80_mem_input_create(
- 		return &mem_input80->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, mem_input80);
-+	dm_free(mem_input80);
- 	return NULL;
- }
- 
- static void dce80_transform_destroy(struct transform **xfm)
- {
--	dm_free((*xfm)->ctx, TO_DCE80_TRANSFORM(*xfm));
-+	dm_free(TO_DCE80_TRANSFORM(*xfm));
- 	*xfm = NULL;
- }
- 
-@@ -404,7 +403,7 @@ static struct transform *dce80_transform_create(
- 	const struct dce80_transform_reg_offsets *offsets)
- {
- 	struct dce80_transform *transform =
--		dm_alloc(ctx, sizeof(struct dce80_transform));
-+		dm_alloc(sizeof(struct dce80_transform));
- 
- 	if (!transform)
- 		return NULL;
-@@ -413,7 +412,7 @@ static struct transform *dce80_transform_create(
- 		return &transform->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, transform);
-+	dm_free(transform);
- 	return NULL;
- }
- 
-@@ -423,7 +422,7 @@ static struct input_pixel_processor *dce80_ipp_create(
- 	const struct dce110_ipp_reg_offsets *offset)
- {
- 	struct dce110_ipp *ipp =
--		dm_alloc(ctx, sizeof(struct dce110_ipp));
-+		dm_alloc(sizeof(struct dce110_ipp));
- 
- 	if (!ipp)
- 		return NULL;
-@@ -431,9 +430,8 @@ static struct input_pixel_processor *dce80_ipp_create(
- 	if (dce80_ipp_construct(ipp, ctx, inst, offset))
- 		return &ipp->base;
- 
--
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, ipp);
-+	dm_free(ipp);
- 	return NULL;
- }
- 
-@@ -441,9 +439,7 @@ struct link_encoder *dce80_link_encoder_create(
- 	const struct encoder_init_data *enc_init_data)
- {
- 	struct dce110_link_encoder *enc110 =
--		dm_alloc(
--		enc_init_data->ctx,
--		sizeof(struct dce110_link_encoder));
-+		dm_alloc(sizeof(struct dce110_link_encoder));
- 
- 	if (!enc110)
- 		return NULL;
-@@ -457,7 +453,7 @@ struct link_encoder *dce80_link_encoder_create(
- 		return &enc110->base;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(enc_init_data->ctx, enc110);
-+	dm_free(enc110);
- 	return NULL;
- }
- 
-@@ -468,7 +464,7 @@ struct clock_source *dce80_clock_source_create(
- 	const struct dce110_clk_src_reg_offsets *offsets)
- {
- 	struct dce110_clk_src *clk_src =
--		dm_alloc(ctx, sizeof(struct dce110_clk_src));
-+		dm_alloc(sizeof(struct dce110_clk_src));
- 
- 	if (!clk_src)
- 		return NULL;
-@@ -482,7 +478,7 @@ struct clock_source *dce80_clock_source_create(
- 
- void dce80_clock_source_destroy(struct clock_source **clk_src)
- {
--	dm_free((*clk_src)->ctx, TO_DCE110_CLK_SRC(*clk_src));
-+	dm_free(TO_DCE110_CLK_SRC(*clk_src));
- 	*clk_src = NULL;
- }
- 
-@@ -501,21 +497,19 @@ void dce80_destruct_resource_pool(struct resource_pool *pool)
- 			dce80_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dm_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 
- 		if (pool->timing_generators[i] != NULL)	{
--			dm_free(pool->timing_generators[i]->ctx, DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
- 
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dm_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
-@@ -1247,8 +1241,7 @@ bool dce80_construct_resource_pool(
- stream_enc_create_fail:
- 	for (i = 0; i < pool->stream_enc_count; i++) {
- 		if (pool->stream_enc[i] != NULL)
--			dm_free(pool->stream_enc[i]->ctx,
--				DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
- 	}
- 
- audio_create_fail:
-@@ -1269,13 +1262,11 @@ controller_create_fail:
- 			dce80_ipp_destroy(&pool->ipps[i]);
- 
- 		if (pool->mis[i] != NULL) {
--			dm_free(pool->mis[i]->ctx,
--					TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
- 			pool->mis[i] = NULL;
- 		}
- 		if (pool->timing_generators[i] != NULL)	{
--			dm_free(pool->timing_generators[i]->ctx,
--				DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
- 			pool->timing_generators[i] = NULL;
- 		}
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-index 8b7edb9..158522d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.h
-@@ -81,5 +81,4 @@ void dce80_stream_encoder_dp_unblank(
- 	struct stream_encoder *enc,
- 	const struct encoder_unblank_param *param);
- 
--
- #endif /* __DC_STREAM_ENCODER_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-index 06339ed..86de41a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
-@@ -26,7 +26,6 @@
- #ifndef __DC_TIMING_GENERATOR_DCE80_H__
- #define __DC_TIMING_GENERATOR_DCE80_H__
- 
--
- #include "timing_generator.h"
- #include "../include/grph_object_id.h"
- 
-@@ -44,6 +43,4 @@ void dce80_timing_generator_enable_advanced_request(
- 	bool enable,
- 	const struct dc_crtc_timing *timing);
- 
--
--
- #endif /* __DC_TIMING_GENERATOR_DCE80_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-index a0fb2d2..b719546 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -82,5 +82,4 @@ bool dce80_transform_get_current_pixel_storage_depth(
- 	struct transform *xfm,
- 	enum lb_pixel_depth *depth);
- 
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 5ba8be8..d3820f8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -40,13 +40,9 @@
- 
- #undef DEPRECATED
- 
--/* if the pointer is not NULL, the allocated memory is zeroed */
--void *dm_alloc(struct dc_context *ctx, uint32_t size);
--
--/* reallocate memory. The contents will remain unchanged.*/
--void *dm_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
--
--void dm_free(struct dc_context *ctx, void *p);
-+#define dm_alloc(size) kzalloc(size, GFP_KERNEL)
-+#define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
-+#define dm_free(ptr) kfree(ptr)
- 
- void dm_memset(void *p, int32_t c, uint32_t count);
- 
-@@ -249,7 +245,6 @@ bool dm_pp_get_clock_levels_by_type(
- 	enum dm_pp_clock_type clk_type,
- 	struct dm_pp_clock_levels *clk_level_info);
- 
--
- bool dm_pp_apply_safe_state(
- 		const struct dc_context *ctx);
- 
-@@ -268,7 +263,6 @@ bool dm_pp_apply_display_requirements(
- 	const struct dc_context *ctx,
- 	const struct dm_pp_display_configuration *pp_display_cfg);
- 
--
- /****** end of PP interfaces ******/
- 
- void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index a74fb85..1e87624 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -102,7 +102,6 @@ enum { false, true };
- 			printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \
- 				while (false)
- 
--
- #define dm_debug(fmt, ...) printf("[DAL_DBG]" fmt, ##__VA_ARGS__)
- 
- #define dm_vlog(fmt, args) vprintf(fmt, args)
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-index 8ff899c..3e7d42e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-@@ -62,7 +62,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dm_free((*ptr)->ctx, pin);
-+	dm_free(pin);
- 
- 	*ptr = NULL;
- }
-@@ -814,7 +814,6 @@ static const struct hw_gpio_pin_funcs funcs = {
- 	.close = dal_hw_gpio_close,
- };
- 
--
- static bool construct(
- 	struct hw_ddc_dce110 *pin,
- 	enum gpio_id id,
-@@ -864,7 +863,7 @@ struct hw_gpio_pin *dal_hw_ddc_dce110_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_ddc_dce110 *pin = dm_alloc(ctx, sizeof(struct hw_ddc_dce110));
-+	struct hw_ddc_dce110 *pin = dm_alloc(sizeof(struct hw_ddc_dce110));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -876,7 +875,7 @@ struct hw_gpio_pin *dal_hw_ddc_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, pin);
-+	dm_free(pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-index a90115c..f385394 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c
-@@ -61,7 +61,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dm_free((*ptr)->ctx, pin);
-+	dm_free(pin);
- 
- 	*ptr = NULL;
- }
-@@ -348,7 +348,7 @@ struct hw_gpio_pin *dal_hw_hpd_dce110_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_hpd_dce110 *pin = dm_alloc(ctx, sizeof(struct hw_hpd_dce110));
-+	struct hw_hpd_dce110 *pin = dm_alloc(sizeof(struct hw_hpd_dce110));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -360,7 +360,7 @@ struct hw_gpio_pin *dal_hw_hpd_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, pin);
-+	dm_free(pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-index 850caeb..5776751 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-@@ -72,7 +72,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dm_free((*ptr)->ctx, pin);
-+	dm_free(pin);
- 
- 	*ptr = NULL;
- }
-@@ -875,7 +875,7 @@ struct hw_gpio_pin *dal_hw_ddc_dce80_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_ddc_dce80 *pin = dm_alloc(ctx, sizeof(struct hw_ddc_dce80));
-+	struct hw_ddc_dce80 *pin = dm_alloc(sizeof(struct hw_ddc_dce80));
- 
- 	if (!pin) {
- 		BREAK_TO_DEBUGGER();
-@@ -887,7 +887,7 @@ struct hw_gpio_pin *dal_hw_ddc_dce80_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, pin);
-+	dm_free(pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c
-index 67b249b..342b3aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_hpd_dce80.c
-@@ -46,7 +46,6 @@
- #include "dce/dce_8_0_d.h"
- #include "dce/dce_8_0_sh_mask.h"
- 
--
- /*
-  * This unit
-  */
-@@ -73,7 +72,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dm_free((*ptr)->ctx, pin);
-+	dm_free(pin);
- 
- 	*ptr = NULL;
- }
-@@ -360,7 +359,7 @@ struct hw_gpio_pin *dal_hw_hpd_dce80_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_hpd_dce80 *pin = dm_alloc(ctx, sizeof(struct hw_hpd_dce80));
-+	struct hw_hpd_dce80 *pin = dm_alloc(sizeof(struct hw_hpd_dce80));
- 
- 	if (!pin) {
- 		BREAK_TO_DEBUGGER();
-@@ -372,7 +371,7 @@ struct hw_gpio_pin *dal_hw_hpd_dce80_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, pin);
-+	dm_free(pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-index c3d8cdb..6eedef6 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc.c
-@@ -229,7 +229,7 @@ struct ddc *dal_gpio_create_ddc(
- 	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en))
- 		return NULL;
- 
--	ddc = dm_alloc(service->ctx, sizeof(struct ddc));
-+	ddc = dm_alloc(sizeof(struct ddc));
- 
- 	if (!ddc) {
- 		BREAK_TO_DEBUGGER();
-@@ -262,7 +262,7 @@ failure_2:
- 	dal_gpio_service_destroy_gpio(&ddc->pin_data);
- 
- failure_1:
--	dm_free(service->ctx, ddc);
-+	dm_free(ddc);
- 
- 	return NULL;
- }
-@@ -284,7 +284,7 @@ void dal_gpio_destroy_ddc(
- 	}
- 
- 	destruct(*ddc);
--	dm_free((*ddc)->ctx, *ddc);
-+	dm_free(*ddc);
- 
- 	*ddc = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-index 1dd31d8..6e4bfd2 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c
-@@ -49,7 +49,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dm_free((*ptr)->ctx, pin);
-+	dm_free(pin);
- 
- 	*ptr = NULL;
- }
-@@ -79,7 +79,7 @@ struct hw_gpio_pin *dal_hw_ddc_diag_fpga_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_ddc *pin = dm_alloc(ctx, sizeof(struct hw_ddc));
-+	struct hw_ddc *pin = dm_alloc(sizeof(struct hw_ddc));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -91,7 +91,7 @@ struct hw_gpio_pin *dal_hw_ddc_diag_fpga_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, pin);
-+	dm_free(pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-index 019e810..c193f0e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c
-@@ -33,7 +33,6 @@
- #include "../hw_gpio.h"
- #include "../hw_hpd.h"
- 
--
- static void destruct(
- 	struct hw_hpd *pin)
- {
-@@ -47,7 +46,7 @@ static void destroy(
- 
- 	destruct(pin);
- 
--	dm_free((*ptr)->ctx, pin);
-+	dm_free(pin);
- 
- 	*ptr = NULL;
- }
-@@ -83,7 +82,7 @@ struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
- 	enum gpio_id id,
- 	uint32_t en)
- {
--	struct hw_hpd *pin = dm_alloc(ctx, sizeof(struct hw_hpd));
-+	struct hw_hpd *pin = dm_alloc(sizeof(struct hw_hpd));
- 
- 	if (!pin) {
- 		ASSERT_CRITICAL(false);
-@@ -95,7 +94,7 @@ struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, pin);
-+	dm_free(pin);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h
-index bfa2c24..aa9cd54 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h
-@@ -26,7 +26,6 @@
- #ifndef __DAL_HW_HPD_DIAG_FPGA_H__
- #define __DAL_HW_HPD_DIAG_FPGA_H__
- 
--
- struct hw_gpio_pin *dal_hw_hpd_diag_fpga_create(
- 	struct dc_context *ctx,
- 	enum gpio_id id,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-index 177330a..bf90688 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c
-@@ -28,7 +28,6 @@
- 
- #include "../hw_translate.h"
- 
--
- /* function table */
- static const struct hw_translate_funcs funcs = {
- 	.offset_to_id = NULL,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-index 7e16d63..eeefaa2 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c
-@@ -246,7 +246,7 @@ struct gpio *dal_gpio_create(
- 	uint32_t en,
- 	enum gpio_pin_output_state output_state)
- {
--	struct gpio *gpio = dm_alloc(service->ctx, sizeof(struct gpio));
-+	struct gpio *gpio = dm_alloc(sizeof(struct gpio));
- 
- 	if (!gpio) {
- 		ASSERT_CRITICAL(false);
-@@ -273,7 +273,7 @@ void dal_gpio_destroy(
- 
- 	dal_gpio_close(*gpio);
- 
--	dm_free((*gpio)->service->ctx, *gpio);
-+	dm_free(*gpio);
- 
- 	*gpio = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-index 6837898..8b4eba9 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c
-@@ -68,7 +68,7 @@ struct gpio_service *dal_gpio_service_create(
- 
- 	uint32_t index_of_id;
- 
--	service = dm_alloc(ctx, sizeof(struct gpio_service));
-+	service = dm_alloc(sizeof(struct gpio_service));
- 
- 	if (!service) {
- 		BREAK_TO_DEBUGGER();
-@@ -107,9 +107,7 @@ struct gpio_service *dal_gpio_service_create(
- 			if (number_of_bits) {
- 				uint32_t index_of_uint = 0;
- 
--				slot = dm_alloc(
--					ctx,
--					number_of_uints * sizeof(uint32_t));
-+				slot = dm_alloc(number_of_uints * sizeof(uint32_t));
- 
- 				if (!slot) {
- 					BREAK_TO_DEBUGGER();
-@@ -141,11 +139,11 @@ failure_2:
- 		slot = service->busyness[index_of_id];
- 
- 		if (slot)
--			dm_free(ctx, slot);
-+			dm_free(slot);
- 	};
- 
- failure_1:
--	dm_free(ctx, service);
-+	dm_free(service);
- 
- 	return NULL;
- }
-@@ -243,13 +241,13 @@ void dal_gpio_service_destroy(
- 			uint32_t *slot = (*ptr)->busyness[index_of_id];
- 
- 			if (slot)
--				dm_free((*ptr)->ctx, slot);
-+				dm_free(slot);
- 
- 			++index_of_id;
- 		} while (index_of_id < GPIO_ID_COUNT);
- 	}
- 
--	dm_free((*ptr)->ctx, *ptr);
-+	dm_free(*ptr);
- 
- 	*ptr = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index 9c8ff54..63d6b54 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -96,7 +96,7 @@ void dal_hw_factory_destroy(
- 		return;
- 	}
- 
--	dm_free(ctx, *factory);
-+	dm_free(*factory);
- 
- 	*factory = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-index debc2ea..bf577f5 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/irq.c
-@@ -137,7 +137,7 @@ struct irq *dal_gpio_create_irq(
- 		return NULL;
- 	}
- 
--	irq = dm_alloc(service->ctx, sizeof(struct irq));
-+	irq = dm_alloc(sizeof(struct irq));
- 
- 	if (!irq) {
- 		ASSERT_CRITICAL(false);
-@@ -153,7 +153,7 @@ struct irq *dal_gpio_create_irq(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(service->ctx, irq);
-+	dm_free(irq);
- 
- 	return NULL;
- }
-@@ -174,7 +174,7 @@ void dal_gpio_destroy_irq(
- 	}
- 
- 	destruct(*irq);
--	dm_free((*irq)->ctx, *irq);
-+	dm_free(*irq);
- 
- 	*irq = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-index a54cc25..36a08a5 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
-@@ -46,7 +46,6 @@ static void force_hw_base_light_sleep(struct dc_context *ctx)
- 	uint32_t addr = 0;
- 	uint32_t value = 0;
- 
--
- 	addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
- 	/* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
- 	 * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 15243de..2ee5773 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -52,7 +52,6 @@ static struct state_dependent_clocks max_clks_by_state[] = {
- /*ClocksStatePerformance*/
- { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
- 
--
- /* Starting point for each divider range.*/
- enum divider_range_start {
- 	DIVIDER_RANGE_01_START = 200, /* 2.00*/
-@@ -188,7 +187,6 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
- 			DENTIST_DISPCLK_CNTL,
- 			DENTIST_DPREFCLK_WDIVIDER));
- 
--
- 	if (target_div != INVALID_DIVIDER) {
- 		/* Calculate the current DFS clock, in kHz.*/
- 		dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
-@@ -226,14 +224,13 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
- 	return dp_ref_clk_khz;
- }
- 
--
- static void destroy(struct display_clock **base)
- {
- 	struct display_clock_dce110 *dc110;
- 
- 	dc110 = DCLCK110_FROM_BASE(*base);
- 
--	dm_free((*base)->ctx, dc110);
-+	dm_free(dc110);
- 
- 	*base = NULL;
- }
-@@ -954,7 +951,7 @@ struct display_clock *dal_display_clock_dce110_create(
- {
- 	struct display_clock_dce110 *dc110;
- 
--	dc110 = dm_alloc(ctx, sizeof(struct display_clock_dce110));
-+	dc110 = dm_alloc(sizeof(struct display_clock_dce110));
- 
- 	if (dc110 == NULL)
- 		return NULL;
-@@ -962,7 +959,7 @@ struct display_clock *dal_display_clock_dce110_create(
- 	if (dal_display_clock_dce110_construct(dc110, ctx, as))
- 		return &dc110->disp_clk_base;
- 
--	dm_free(ctx, dc110);
-+	dm_free(dc110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-index 760705f..5346ded 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-@@ -51,7 +51,6 @@ static struct state_dependent_clocks max_clks_by_state[] = {
- /* ClocksStatePerformance */
- { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
- 
--
- /* Starting point for each divider range.*/
- enum divider_range_start {
- 	DIVIDER_RANGE_01_START = 200, /* 2.00*/
-@@ -240,7 +239,6 @@ static uint32_t calc_single_display_min_clks(
- 	uint32_t alt_disp_clk_khz;
- 	struct display_clock_dce80 *dc = FROM_DISPLAY_CLOCK(base);
- 
--
- 	if (0 != params->dest_view.height && 0 != params->dest_view.width) {
- 
- 		h_scale = dal_fixed32_32_from_fraction(
-@@ -258,7 +256,6 @@ static uint32_t calc_single_display_min_clks(
- 	v_filter_init = dal_fixed32_32_add(v_filter_init,
- 		dal_fixed32_32_from_fraction(15, 10));
- 
--
- 	v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
- 
- 	v_filter_init_ceil = dal_fixed32_32_from_fraction(
-@@ -349,7 +346,6 @@ static uint32_t calc_cursor_bw_for_min_clks(struct min_clock_params *params)
- 	struct fixed32_32 src_lines_per_dst_line;
- 	struct fixed32_32 cursor_bw;
- 
--
- 	/*  DCE8 Mode Support and Mode Set Architecture Specification Rev 1.3
- 	 6.3.3	Cursor data Throughput requirement on DISPCLK
- 	 The MCIF to DCP cursor data return throughput is one pixel per DISPCLK
-@@ -428,7 +424,6 @@ static uint32_t calculate_min_clock(
- 	uint32_t total_cursor_bw = 0;
- 	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
- 
--
- 	if (disp_clk->use_max_disp_clk)
- 		return min_clk_khz;
- 
-@@ -635,7 +630,6 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
- 			DENTIST_DISPCLK_CNTL,
- 			DENTIST_DPREFCLK_WDIVIDER));
- 
--
- 	if (target_div != INVALID_DIVIDER) {
- 		/* Calculate the current DFS clock, in kHz.*/
- 		dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
-@@ -812,7 +806,7 @@ static void destroy(struct display_clock **dc)
- 	struct display_clock_dce80 *disp_clk;
- 
- 	disp_clk = FROM_DISPLAY_CLOCK(*dc);
--	dm_free((*dc)->ctx, disp_clk);
-+	dm_free(disp_clk);
- 	*dc = NULL;
- }
- 
-@@ -911,7 +905,7 @@ struct display_clock *dal_display_clock_dce80_create(
- {
- 	struct display_clock_dce80 *disp_clk;
- 
--	disp_clk = dm_alloc(ctx, sizeof(struct display_clock_dce80));
-+	disp_clk = dm_alloc(sizeof(struct display_clock_dce80));
- 
- 	if (disp_clk == NULL)
- 		return NULL;
-@@ -919,7 +913,7 @@ struct display_clock *dal_display_clock_dce80_create(
- 	if (display_clock_construct(ctx, disp_clk, as))
- 		return &disp_clk->disp_clk;
- 
--	dm_free(ctx, disp_clk);
-+	dm_free(disp_clk);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
-index 2ec1034..e53522f 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
-@@ -59,5 +59,4 @@ uint32_t dal_divider_range_get_did(
- 	uint32_t ranges_num,
- 	uint32_t divider);
- 
--
- #endif /* __DAL_DIVIDER_RANGE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-index f9c5543..d2f49b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-@@ -92,7 +92,7 @@ static void destroy(
- 
- 	destruct(engine);
- 
--	dm_free((*aux_engine)->base.ctx, engine);
-+	dm_free(engine);
- 
- 	*aux_engine = NULL;
- }
-@@ -645,7 +645,6 @@ static enum aux_channel_operation_result get_channel_status(
- 			time_elapsed += 10;
- 		} while (time_elapsed < aux_engine->timeout_period);
- 
--
- 	}
- 
- 	/* Note that the following bits are set in 'status.bits'
-@@ -770,7 +769,7 @@ struct aux_engine *dal_aux_engine_dce110_create(
- 		return NULL;
- 	}
- 
--	engine = dm_alloc(aux_init_data->ctx, sizeof(*engine));
-+	engine = dm_alloc(sizeof(*engine));
- 
- 	if (!engine) {
- 		ASSERT_CRITICAL(false);
-@@ -782,7 +781,7 @@ struct aux_engine *dal_aux_engine_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(aux_init_data->ctx, engine);
-+	dm_free(engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-index 2517f44..b43a431 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-@@ -91,7 +91,6 @@ enum {
- #define FROM_ENGINE(ptr) \
- 	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
- 
--
- static void disable_i2c_hw_engine(
- 	struct i2c_hw_engine_dce110 *engine)
- {
-@@ -242,7 +241,6 @@ static bool setup_engine(
- 			DC_I2C_CONTROL,
- 			DC_I2C_DDC_SELECT);
- 
--
- 		dm_write_reg(i2c_engine->base.ctx, addr, value);
- 	}
- 
-@@ -448,7 +446,6 @@ static bool process_transaction(
- 			DC_I2C_TRANSACTION0,
- 			DC_I2C_START0);
- 
--
- 		if ((engine->transaction_count == 3) ||
- 		(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
- 		(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-@@ -792,7 +789,7 @@ static void destroy(
- 
- 	dal_i2c_hw_engine_destruct(&engine_dce110->base);
- 
--	dm_free((*i2c_engine)->base.ctx, engine_dce110);
-+	dm_free(engine_dce110);
- 
- 	*i2c_engine = NULL;
- }
-@@ -892,7 +889,6 @@ static bool construct(
- 	engine_dce110->addr.DC_I2C_DDCX_SPEED =
- 		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
- 
--
- 	value = dm_read_reg(
- 		engine_dce110->base.base.base.ctx,
- 		mmMICROSECOND_TIME_BASE_DIV);
-@@ -922,7 +918,6 @@ static bool construct(
- 	engine_dce110->reference_frequency =
- 		(arg->reference_frequency * 2) / xtal_ref_div;
- 
--
- 	return true;
- }
- 
-@@ -936,7 +931,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create(
- 		return NULL;
- 	}
- 
--	engine_dce10 = dm_alloc(arg->ctx, sizeof(struct i2c_hw_engine_dce110));
-+	engine_dce10 = dm_alloc(sizeof(struct i2c_hw_engine_dce110));
- 
- 	if (!engine_dce10) {
- 		ASSERT_CRITICAL(false);
-@@ -948,7 +943,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(arg->ctx, engine_dce10);
-+	dm_free(engine_dce10);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-index f060b25..0a339b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c
-@@ -88,7 +88,7 @@ static void destroy(
- 
- 	destruct(sw_engine);
- 
--	dm_free((*engine)->base.ctx, sw_engine);
-+	dm_free(sw_engine);
- 
- 	*engine = NULL;
- }
-@@ -154,7 +154,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create(
- 		return NULL;
- 	}
- 
--	engine_dce110 = dm_alloc(arg->ctx, sizeof(struct i2c_sw_engine_dce110));
-+	engine_dce110 = dm_alloc(sizeof(struct i2c_sw_engine_dce110));
- 
- 	if (!engine_dce110) {
- 		ASSERT_CRITICAL(false);
-@@ -166,7 +166,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(arg->ctx, engine_dce110);
-+	dm_free(engine_dce110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-index 9c88762..2470c77 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
-@@ -68,7 +68,7 @@ static void destroy(
- 
- 	destruct(i2caux_dce110);
- 
--	dm_free((*i2c_engine)->ctx, i2caux_dce110);
-+	dm_free(i2caux_dce110);
- 
- 	*i2c_engine = NULL;
- }
-@@ -248,7 +248,7 @@ struct i2caux *dal_i2caux_dce110_create(
- 	struct dc_context *ctx)
- {
- 	struct i2caux_dce110 *i2caux_dce110 =
--		dm_alloc(ctx, sizeof(struct i2caux_dce110));
-+		dm_alloc(sizeof(struct i2caux_dce110));
- 
- 	if (!i2caux_dce110) {
- 		ASSERT_CRITICAL(false);
-@@ -260,7 +260,7 @@ struct i2caux *dal_i2caux_dce110_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, i2caux_dce110);
-+	dm_free(i2caux_dce110);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-index a4fc2cd..b732860 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-@@ -45,7 +45,6 @@
- #include "dce/dce_8_0_d.h"
- #include "dce/dce_8_0_sh_mask.h"
- 
--
- /*
-  * This unit
-  */
-@@ -94,7 +93,7 @@ static void destroy(
- 
- 	destruct(engine);
- 
--	dm_free((*aux_engine)->base.ctx, engine);
-+	dm_free(engine);
- 
- 	*aux_engine = NULL;
- }
-@@ -599,7 +598,6 @@ static enum aux_channel_operation_result get_channel_status(
- 			time_elapsed += 10;
- 		} while (time_elapsed < aux_engine->timeout_period);
- 
--
- 	}
- 
- 	/* Note that the following bits are set in 'status.bits'
-@@ -722,7 +720,7 @@ struct aux_engine *dal_aux_engine_dce80_create(
- 		return NULL;
- 	}
- 
--	engine = dm_alloc(arg->ctx, sizeof(struct aux_engine_dce80));
-+	engine = dm_alloc(sizeof(struct aux_engine_dce80));
- 
- 	if (!engine) {
- 		BREAK_TO_DEBUGGER();
-@@ -734,7 +732,7 @@ struct aux_engine *dal_aux_engine_dce80_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(arg->ctx, engine);
-+	dm_free(engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-index 3d61963..bce2b94 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-@@ -206,7 +206,7 @@ static void destroy(
- 
- 	destruct(engine);
- 
--	dm_free((*i2c_engine)->base.ctx, engine);
-+	dm_free(engine);
- 
- 	*i2c_engine = NULL;
- }
-@@ -259,7 +259,6 @@ static bool setup_engine(
- 			DC_I2C_CONTROL,
- 			DC_I2C_DDC_SELECT);
- 
--
- 		dm_write_reg(i2c_engine->base.ctx, addr, value);
- 	}
- 
-@@ -450,7 +449,6 @@ static bool process_transaction(
- 			DC_I2C_TRANSACTION0,
- 			DC_I2C_START0);
- 
--
- 		if ((engine->transaction_count == 3) ||
- 		(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
- 		(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-@@ -883,7 +881,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create(
- 		return NULL;
- 	}
- 
--	engine = dm_alloc(arg->ctx, sizeof(struct i2c_hw_engine_dce80));
-+	engine = dm_alloc(sizeof(struct i2c_hw_engine_dce80));
- 
- 	if (!engine) {
- 		BREAK_TO_DEBUGGER();
-@@ -895,7 +893,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(arg->ctx, engine);
-+	dm_free(engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c
-index e5135c5..5f2f298 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_sw_engine_dce80.c
-@@ -60,7 +60,6 @@ static const uint32_t ddc_hw_status_addr[] = {
- 	mmDC_I2C_DDCVGA_HW_STATUS
- };
- 
--
- /*
-  * @brief
-  * Cast 'struct i2c_sw_engine *'
-@@ -104,12 +103,11 @@ static void destroy(
- 
- 	destruct(sw_engine);
- 
--	dm_free((*engine)->base.ctx, sw_engine);
-+	dm_free(sw_engine);
- 
- 	*engine = NULL;
- }
- 
--
- static bool acquire_engine(
- 	struct i2c_engine *engine,
- 	struct ddc *ddc_handle)
-@@ -168,7 +166,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create(
- 		return NULL;
- 	}
- 
--	engine = dm_alloc(arg->ctx, sizeof(struct i2c_sw_engine_dce80));
-+	engine = dm_alloc(sizeof(struct i2c_sw_engine_dce80));
- 
- 	if (!engine) {
- 		BREAK_TO_DEBUGGER();
-@@ -180,7 +178,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(arg->ctx, engine);
-+	dm_free(engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-index 4abf488..1ed6196 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-@@ -51,7 +51,6 @@
- #include "../aux_engine.h"
- #include "aux_engine_dce80.h"
- 
--
- /*
-  * This unit
-  */
-@@ -72,7 +71,7 @@ static void destroy(
- 
- 	destruct(i2caux_dce80);
- 
--	dm_free((*i2c_engine)->ctx, i2caux_dce80);
-+	dm_free(i2caux_dce80);
- 
- 	*i2c_engine = NULL;
- }
-@@ -246,7 +245,7 @@ struct i2caux *dal_i2caux_dce80_create(
- 	struct dc_context *ctx)
- {
- 	struct i2caux_dce80 *i2caux_dce80 =
--		dm_alloc(ctx, sizeof(struct i2caux_dce80));
-+		dm_alloc(sizeof(struct i2caux_dce80));
- 
- 	if (!i2caux_dce80) {
- 		BREAK_TO_DEBUGGER();
-@@ -258,7 +257,7 @@ struct i2caux *dal_i2caux_dce80_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(ctx, i2caux_dce80);
-+	dm_free(i2caux_dce80);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-index f4bc39d..027b207 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
-@@ -59,13 +59,11 @@ static void destroy(
- {
- 	destruct(*i2c_engine);
- 
--	dm_free((*i2c_engine)->ctx, *i2c_engine);
-+	dm_free(*i2c_engine);
- 
- 	*i2c_engine = NULL;
- }
- 
--
--
- /* function table */
- static const struct i2caux_funcs i2caux_funcs = {
- 	.destroy = destroy,
-@@ -94,7 +92,7 @@ struct i2caux *dal_i2caux_diag_fpga_create(
- 	struct adapter_service *as,
- 	struct dc_context *ctx)
- {
--	struct i2caux *i2caux =	dm_alloc(ctx, sizeof(struct i2caux));
-+	struct i2caux *i2caux =	dm_alloc(sizeof(struct i2caux));
- 
- 	if (!i2caux) {
- 		ASSERT_CRITICAL(false);
-@@ -106,7 +104,7 @@ struct i2caux *dal_i2caux_diag_fpga_create(
- 
- 	ASSERT_CRITICAL(false);
- 
--	dm_free(ctx, i2caux);
-+	dm_free(i2caux);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-index 21e8fa2..2ee5118 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-@@ -542,7 +542,7 @@ static void destroy(
- {
- 	dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
- 
--	dm_free((*ptr)->base.ctx, *ptr);
-+	dm_free(*ptr);
- 	*ptr = NULL;
- }
- 
-@@ -584,8 +584,6 @@ bool dal_i2c_sw_engine_construct(
- 	return true;
- }
- 
--
--
- struct i2c_engine *dal_i2c_sw_engine_create(
- 	const struct i2c_sw_engine_create_arg *arg)
- {
-@@ -596,7 +594,7 @@ struct i2c_engine *dal_i2c_sw_engine_create(
- 		return NULL;
- 	}
- 
--	engine = dm_alloc(arg->ctx, sizeof(struct i2c_sw_engine));
-+	engine = dm_alloc(sizeof(struct i2c_sw_engine));
- 
- 	if (!engine) {
- 		BREAK_TO_DEBUGGER();
-@@ -608,7 +606,7 @@ struct i2c_engine *dal_i2c_sw_engine_create(
- 
- 	BREAK_TO_DEBUGGER();
- 
--	dm_free(arg->ctx, engine);
-+	dm_free(engine);
- 
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index 0d228ed..2adad08 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -230,7 +230,6 @@ struct bw_calcs_mode_data_internal {
- 	enum bw_defines d2_graphics_stereo_mode;
- };
- 
--
- struct bw_calcs_input_single_display {
- 	uint32_t graphics_rotation_angle;
- 	uint32_t underlay_rotation_angle;
-@@ -484,7 +483,6 @@ struct bw_calcs_output {
- 	int32_t required_blackout_duration_us;
- };
- 
--
- /**
-  * Initialize structures with data which will NOT change at runtime.
-  */
-@@ -505,6 +503,5 @@ bool bw_calcs(
- 	const struct bw_calcs_mode_data *mode_data,
- 	struct bw_calcs_output *calcs_output);
- 
--
- #endif /* __BANDWIDTH_CALCS_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-index ff271cc..b31d07a 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h
-@@ -60,5 +60,4 @@ bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2);
- bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2);
- bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2);
- 
--
- #endif //BW_FIXED_H_
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 4b9ce6a..be3a693 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -55,7 +55,6 @@ struct core_target {
- #define DC_GAMMA_TO_CORE(dc_gamma) \
- 	container_of(dc_gamma, struct core_gamma, public)
- 
--
- struct core_surface {
- 	struct dc_surface public;
- 	struct dc_surface_status status;
-@@ -99,7 +98,6 @@ struct core_stream {
- 	struct dc_stream_status status;
- };
- 
--
- /************ core_sink *****************/
- 
- #define DC_SINK_TO_CORE(dc_sink) \
-@@ -349,5 +347,4 @@ struct validate_context {
- 	struct dm_pp_display_configuration pp_display_cfg;
- };
- 
--
- #endif /* _CORE_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-index 505bf72..f419331 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-@@ -1,4 +1,3 @@
--
- /*
-  * Copyright 2015 Advanced Micro Devices, Inc.
-  *
-@@ -61,7 +60,6 @@ enum ipp_degamma_mode {
- 	IPP_DEGAMMA_MODE_USER_PWL
- };
- 
--
- enum ovl_color_space {
- 	OVL_COLOR_SPACE_UNKNOWN = 0,
- 	OVL_COLOR_SPACE_RGB,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-index 1c9b732..1c6bab3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-@@ -88,8 +88,6 @@ struct bit_depth_reduction_params {
- 	uint32_t g_seed_value;
- };
- 
--
--
- enum wide_gamut_regamma_mode {
- 	/*  0x0  - BITS2:0 Bypass */
- 	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
-@@ -255,7 +253,6 @@ struct opp_grph_csc_adjustment {
- 	int32_t grph_hue;
- };
- 
--
- /* Underlay related types */
- 
- struct hw_adjustment_range {
-@@ -318,7 +315,6 @@ struct opp_funcs {
- 			enum ovl_csc_adjust_item overlay_adjust_item,
- 			struct hw_adjustment_range *range);
- 
--
- 	void (*opp_destroy)(struct output_pixel_processor **opp);
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
-index 47cf6de..87a1343 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
-@@ -12,7 +12,6 @@ struct dc_bios;
- struct dc_context;
- struct dc_crtc_timing;
- 
--
- struct encoder_info_packet {
- 	bool valid;
- 	uint8_t hb0;
-@@ -45,7 +44,6 @@ struct encoder_set_dp_phy_pattern_param {
- 	enum dp_panel_mode dp_panel_mode;
- };
- 
--
- struct stream_encoder {
- 	struct stream_encoder_funcs *funcs;
- 	struct dc_context *ctx;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-index 374e222..25f2417 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-@@ -44,7 +44,6 @@ struct crtc_position {
- 	uint32_t nominal_vcount;
- };
- 
--
- enum dcp_gsl_purpose {
- 	DCP_GSL_PURPOSE_SURFACE_FLIP = 0,
- 	DCP_GSL_PURPOSE_STEREO3D_PHASE,
-@@ -110,7 +109,6 @@ struct timing_generator {
- 	struct dc_context *ctx;
- };
- 
--
- struct dc_crtc_timing;
- 
- struct timing_generator_funcs {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-index bf84f96..c0fd26b 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-@@ -46,7 +46,6 @@ enum lb_pixel_depth {
- 	LB_PIXEL_DEPTH_36BPP = 8
- };
- 
--
- enum raw_gamma_ramp_type {
-        GAMMA_RAMP_TYPE_UNINITIALIZED,
-        GAMMA_RAMP_TYPE_DEFAULT,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 2571691..490ee10 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -35,7 +35,6 @@ enum pipe_gating_control {
- 	PIPE_GATING_CONTROL_INIT
- };
- 
--
- struct hw_sequencer_funcs {
- 
- 	enum dc_status (*apply_ctx_to_hw)(
-@@ -71,7 +70,6 @@ struct hw_sequencer_funcs {
- 	void (*encoder_set_lcd_backlight_level)(
- 		struct link_encoder *enc, uint32_t level);
- 
--
- 	void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t);
- 
- 	/* power management */
-@@ -118,5 +116,4 @@ bool dc_construct_hw_sequencer(
- 				struct adapter_service *adapter_serv,
- 				struct core_dc *dc);
- 
--
- #endif /* __DC_HW_SEQUENCER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-index 4085b6f..ff40f5c 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
-@@ -376,7 +376,7 @@ bool construct(
- struct irq_service *dal_irq_service_dce110_create(
- 	struct irq_service_init_data *init_data)
- {
--	struct irq_service *irq_service = dm_alloc(init_data->ctx, sizeof(*irq_service));
-+	struct irq_service *irq_service = dm_alloc(sizeof(*irq_service));
- 
- 	if (!irq_service)
- 		return NULL;
-@@ -384,6 +384,6 @@ struct irq_service *dal_irq_service_dce110_create(
- 	if (construct(irq_service, init_data))
- 		return irq_service;
- 
--	dm_free(init_data->ctx, irq_service);
-+	dm_free(irq_service);
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-index 3e2f232..cde34ce 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -81,7 +81,7 @@ void dal_irq_service_destroy(struct irq_service **irq_service)
- 		return;
- 	}
- 
--	dm_free((*irq_service)->ctx, *irq_service);
-+	dm_free(*irq_service);
- 
- 	*irq_service = NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq_types.h b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-index 35a0991..1f62e52 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/irq_types.h
-@@ -33,7 +33,6 @@ typedef void (*interrupt_handler)(void *);
- typedef void *irq_handler_idx;
- #define DAL_INVALID_IRQ_HANDLER_IDX NULL
- 
--
- /* The order of the IRQ sources is important and MUST match the one's
- of base driver */
- enum dc_irq_source {
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-index e44713f..eb1a94f 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
-@@ -31,5 +31,4 @@
- bool virtual_link_encoder_construct(
- 	struct link_encoder *enc, const struct encoder_init_data *init_data);
- 
--
- #endif /* __DC_VIRTUAL_LINK_ENCODER_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-index 4f5271b..33f4ef9 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
-@@ -109,7 +109,7 @@ bool virtual_stream_encoder_construct(
- struct stream_encoder *virtual_stream_encoder_create(
- 	struct dc_context *ctx, struct dc_bios *bp)
- {
--	struct stream_encoder *enc = dm_alloc(ctx, sizeof(*enc));
-+	struct stream_encoder *enc = dm_alloc(sizeof(*enc));
- 
- 	if (!enc)
- 		return NULL;
-@@ -118,7 +118,7 @@ struct stream_encoder *virtual_stream_encoder_create(
- 		return enc;
- 
- 	BREAK_TO_DEBUGGER();
--	dm_free(ctx, enc);
-+	dm_free(enc);
- 	return NULL;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-index 8ebbe65..a4b37ff 100644
---- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-@@ -39,7 +39,6 @@
- struct i2caux;
- struct adapter_service;
- 
--
- /*
-  * enum adapter_feature_id
-  *
-@@ -345,7 +344,6 @@ bool dal_adapter_service_get_firmware_info(
- 	struct adapter_service *as,
- 	struct firmware_info *info);
- 
--
- /* functions to get a total number of objects of specific type */
- uint8_t dal_adapter_service_get_connectors_num(
- 	struct adapter_service *as);
-@@ -585,7 +583,6 @@ struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
- struct bdf_info dal_adapter_service_get_adapter_info(
- 	struct adapter_service *as);
- 
--
- /* Determine if this ASIC needs to wait on PLL lock bit */
- bool dal_adapter_service_should_psr_skip_wait_for_pll_lock(
- 	struct adapter_service *as);
-diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
-index bdeaaf9..b5335d1 100644
---- a/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
-@@ -32,7 +32,6 @@
- /* Forward declaration */
- struct hw_asic_id;
- 
--
- /* ASIC capability */
- struct asic_capability {
- 	struct dc_context *ctx;
-@@ -43,7 +42,6 @@ struct asic_capability {
- 	uint32_t data[ASIC_DATA_MAX_NUMBER];
- };
- 
--
- /**
-  * Interfaces
-  */
-diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
-index 1cb9776..56fdcd8 100644
---- a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
-@@ -55,7 +55,6 @@ struct asic_caps {
- 	bool SUPPORT_8BPP:1;
- };
- 
--
- /*
-  * ASIC Stereo 3D Caps
-  */
-@@ -69,7 +68,6 @@ struct asic_stereo_3d_caps {
- 	bool INTERLEAVE:1;
- };
- 
--
- /*
-  * ASIC Bugs
-  */
-@@ -81,7 +79,6 @@ struct asic_bugs {
- 	bool PSR_WA_OVERSCAN_CRC_ERROR:1;
- };
- 
--
- /*
-  * ASIC Data
-  */
-@@ -115,7 +112,6 @@ enum asic_data {
- 	ASIC_DATA_MAX_NUMBER /* end of enum */
- };
- 
--
- /*
-  * ASIC Feature Flags
-  */
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_interface.h b/drivers/gpu/drm/amd/dal/include/audio_interface.h
-index bf21762..ef740a2 100644
---- a/drivers/gpu/drm/amd/dal/include/audio_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/audio_interface.h
-@@ -80,7 +80,6 @@ bool dal_audio_is_output_signal_supported(
- 	struct audio *audio,
- 	enum signal_type signal);
- 
--
- /***** programming interface *****/
- 
- /* perform power up sequence (boot up, resume, recovery) */
-@@ -131,7 +130,6 @@ enum audio_result dal_audio_mute(
- 	enum engine_id engine_id,
- 	enum signal_type signal);
- 
--
- /***** information interface *****/
- 
- struct audio_feature_support dal_audio_get_supported_features(
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h
-index 54f5546..8f1eda1 100644
---- a/drivers/gpu/drm/amd/dal/include/audio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/audio_types.h
-@@ -33,7 +33,6 @@
- #define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18
- #define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF
- 
--
- struct audio_pll_hw_settings {
- 	uint32_t feed_back_divider;
- 	uint32_t step_size_integer;
-@@ -154,7 +153,6 @@ struct audio_info_flags {
- 	};
- };
- 
--
- /*struct audio_info_flags {
- 	struct audio_speaker_flags {
- 		uint32_t FL_FR:1;
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-index 78f88b1..d8c4cd1 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-@@ -105,7 +105,6 @@
- #define DEVICE_ID_TEMASH_9839 0x9839
- #define DEVICE_ID_TEMASH_983D 0x983D
- 
--
- /* Asic Family IDs for different asic family. */
- #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
- #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_register_logger.h b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
-index 176d811..00dfcd7 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
-@@ -35,7 +35,6 @@ void dal_reg_logger_push(const char *caller_func);
- /* dal_reg_logger_pop - stop Register Logging */
- void dal_reg_logger_pop(void);
- 
--
- /* for internal use of the Logger only */
- void dal_reg_logger_rw_count_increment(void);
- bool dal_reg_logger_should_dump_register(void);
-diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-index 63dbbc5..0a6ba91 100644
---- a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h
-@@ -52,7 +52,6 @@ enum ddc_service_type {
- 	DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
- };
- 
--
- enum dcs_dpcd_revision {
- 	DCS_DPCD_REV_10 = 0x10,
- 	DCS_DPCD_REV_11 = 0x11,
-@@ -110,7 +109,6 @@ struct display_sink_capability {
- 	enum signal_type signal;
- };
- 
--
- struct av_sync_data {
- 	uint8_t av_granularity;/* DPCD 00023h */
- 	uint8_t aud_dec_lat1;/* DPCD 00024h */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index a621930..a625e24 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -194,5 +194,4 @@ uint32_t dal_display_clock_get_dfs_bypass_threshold(
- void dal_display_clock_invalid_clock_state(
- 	struct display_clock *disp_clk);
- 
--
- #endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index 2e9672b..59677ed 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -747,7 +747,6 @@ union dp_downstream_port_present {
- 	} fields;
- };
- 
--
- union dwnstream_port_caps_byte3_dvi {
- 	struct {
- 		uint8_t RESERVED1:1;
-diff --git a/drivers/gpu/drm/amd/dal/include/fixed31_32.h b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-index 507f9f6..05f04a6 100644
---- a/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-+++ b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
-@@ -385,5 +385,4 @@ uint32_t dal_fixed31_32_u2d19(
- uint32_t dal_fixed31_32_u0d19(
- 	struct fixed31_32 arg);
- 
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/gpio_types.h b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-index 62548d6..8b2db41 100644
---- a/drivers/gpu/drm/amd/dal/include/gpio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/gpio_types.h
-@@ -329,7 +329,6 @@ struct gpio_config_data {
- 	} config;
- };
- 
--
- struct gpio_ddc_open_options {
- 	bool en_bit_present;
- };
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index fe65b18..7df01ff 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -151,7 +151,6 @@ struct graphics_object_i2c_info {
- 	uint32_t i2c_slave_address;
- };
- 
--
- struct graphics_object_hpd_info {
- 	uint8_t hpd_int_gpio_uid;
- 	uint8_t hpd_active;
-@@ -335,7 +334,6 @@ struct transmitter_configuration {
- 	struct transmitter_configuration_info secondary_transmitter_config;
- };
- 
--
- /* These size should be sufficient to store info coming from BIOS */
- #define NUMBER_OF_UCHAR_FOR_GUID 16
- #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-index a1e468f..a7c42f0 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-@@ -215,7 +215,6 @@ struct static_screen_events {
- 	};
- };
- 
--
- /*
-  * ***************************************************************
-  * ********************* Register programming sequences ********
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-index 4c8079c..64b113b 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
-@@ -111,7 +111,6 @@ enum clock_source_id {
- 	CLOCK_SOURCE_COMBO_DISPLAY_PLL0
- };
- 
--
- /* Encoder object ids */
- enum encoder_id {
- 	ENCODER_ID_UNKNOWN = 0,
-@@ -146,7 +145,6 @@ enum encoder_id {
- 	ENCODER_ID_INTERNAL_VIRTUAL,
- };
- 
--
- /* Connector object ids */
- enum connector_id {
- 	CONNECTOR_ID_UNKNOWN = 0,
-@@ -261,7 +259,6 @@ bool dal_graphics_object_id_is_equal(
- uint32_t dal_graphics_object_id_to_uint(
- 	struct graphics_object_id id);
- 
--
- enum controller_id dal_graphics_object_id_get_controller_id(
- 	struct graphics_object_id id);
- enum clock_source_id dal_graphics_object_id_get_clock_source_id(
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index 9e32674..76c551c 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -232,8 +232,6 @@ struct hw_stereo_mixer_params {
- 	bool single_pipe;
- };
- 
--
--
- struct hw_action_flags {
- 	uint32_t RESYNC_PATH:1;
- 	uint32_t TIMING_CHANGED:1;
-@@ -281,14 +279,12 @@ struct hw_info_frame {
- 	struct hw_info_packet vsc_packet;
- };
- 
--
- enum channel_command_type {
- 	CHANNEL_COMMAND_I2C,
- 	CHANNEL_COMMAND_I2C_OVER_AUX,
- 	CHANNEL_COMMAND_AUX
- };
- 
--
- /* maximum TMDS transmitter pixel clock is 165 MHz. So it is KHz */
- #define	TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
- #define	NATIVE_HDMI_MAX_PIXEL_CLOCK_IN_KHZ 297000
-diff --git a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-index ac16fa0..17c7768 100644
---- a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
-@@ -29,7 +29,6 @@
- #include "ddc_interface.h"
- #include "adapter_service_interface.h"
- 
--
- #define DEFAULT_AUX_MAX_DATA_SIZE 16
- #define AUX_MAX_DEFER_WRITE_RETRY 20
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h
-index 4d945ea..e4e6b3a 100644
---- a/drivers/gpu/drm/amd/dal/include/logger_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h
-@@ -36,7 +36,6 @@ union logger_flags;
-  * TODO: This logger functionality needs to be implemented and reworked.
-  */
- 
--
- /*
-  *
-  * DAL logger functionality
-diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
-index 6147999..759542a 100644
---- a/drivers/gpu/drm/amd/dal/include/logger_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
-@@ -26,12 +26,10 @@
- #ifndef __DAL_LOGGER_TYPES_H__
- #define __DAL_LOGGER_TYPES_H__
- 
--
- /*
-  * TODO: This logger functionality needs to be implemented and reworked.
-  */
- 
--
- struct dal_logger;
- 
- enum log_major {
-@@ -75,7 +73,6 @@ enum log_major {
- *        of log message per LogMajor
- */
- 
--
- enum log_minor {
- 
- 	/* Special case for 'all' checkbox */
-diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_types.h b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-index 97160fe..93aa534 100644
---- a/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/set_mode_types.h
-@@ -28,7 +28,6 @@
- 
- #include "dc_types.h"
- 
--
- /* GTC group number */
- enum gtc_group {
- 	GTC_GROUP_DISABLED,
-@@ -135,8 +134,6 @@ struct info_frame {
- 	struct info_packet spd_info_packet;
- };
- 
--
--
- #pragma pack(pop)
- 
- #endif /* __DAL_SET_MODE_TYPES_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0855-drm-amd-dal-fix-memory-during-fail-link-creation.patch b/common/recipes-kernel/linux/files/0855-drm-amd-dal-fix-memory-during-fail-link-creation.patch
deleted file mode 100644
index 8e75566a..00000000
--- a/common/recipes-kernel/linux/files/0855-drm-amd-dal-fix-memory-during-fail-link-creation.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From cfb494199e72b18539e80a266470b40110221eb4 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Fri, 26 Feb 2016 04:06:56 -0500
-Subject: [PATCH 0855/1110] drm/amd/dal: fix memory during fail link creation
-
-In case device tag is incorrect, already allocated
-resources should be cleaned-up
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 28 ++++++++++++++++++++--------
- 1 file changed, 20 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index e259509..9bfa35b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -954,6 +954,8 @@ static bool construct(
- 	if (hpd_gpio != NULL) {
- 		dal_adapter_service_release_irq(
- 			as, hpd_gpio);
-+
-+		hpd_gpio = NULL;
- 	}
- 
- 	/* TODO: #DAL3 Implement id to str function.*/
-@@ -968,15 +970,15 @@ static bool construct(
- 	ddc_service_init_data.link = link;
- 	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
- 
--	link->public.ddc_hw_inst =
--		dal_ddc_get_line(
--			dal_ddc_service_get_ddc_pin(link->ddc));
--
- 	if (NULL == link->ddc) {
- 		DC_ERROR("Failed to create ddc_service!\n");
--		goto create_fail;
-+		goto ddc_create_fail;
- 	}
- 
-+	link->public.ddc_hw_inst =
-+		dal_ddc_get_line(
-+			dal_ddc_service_get_ddc_pin(link->ddc));
-+
- 	enc_init_data.adapter_service = as;
- 	enc_init_data.ctx = dc_ctx;
- 	enc_init_data.encoder = dal_adapter_service_get_src_obj(
-@@ -991,7 +993,7 @@ static bool construct(
- 
- 	if( link->link_enc == NULL) {
- 		DC_ERROR("Failed to create link encoder!\n");
--		goto create_fail;
-+		goto link_enc_create_fail;
- 	}
- 
- 	link->public.link_enc_hw_inst = link->link_enc->transmitter;
-@@ -1002,7 +1004,7 @@ static bool construct(
- 		if (!dal_adapter_service_get_device_tag(
- 				as, link->link_id, i, &link->device_tag)) {
- 			DC_ERROR("Failed to find device tag!\n");
--			goto create_fail;
-+			goto device_tag_fail;
- 		}
- 
- 		/* Look for device tag that matches connector signal,
-@@ -1046,8 +1048,18 @@ static bool construct(
- 	program_hpd_filter(link);
- 
- 	return true;
--
-+device_tag_fail:
-+	link->ctx->dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
-+link_enc_create_fail:
-+	dal_ddc_service_destroy(&link->ddc);
-+ddc_create_fail:
- create_fail:
-+
-+	if (hpd_gpio != NULL) {
-+		dal_adapter_service_release_irq(
-+			as, hpd_gpio);
-+	}
-+
- 	return false;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0856-drm-amd-dal-Refactor-DC-creation-merge-dc-and-dal-in.patch b/common/recipes-kernel/linux/files/0856-drm-amd-dal-Refactor-DC-creation-merge-dc-and-dal-in.patch
deleted file mode 100644
index 5ad0f63c..00000000
--- a/common/recipes-kernel/linux/files/0856-drm-amd-dal-Refactor-DC-creation-merge-dc-and-dal-in.patch
+++ /dev/null
@@ -1,406 +0,0 @@
-From 735bfe630c7dbbd8387dbeba3e353b5898d7c8be Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Sat, 27 Feb 2016 14:22:46 -0500
-Subject: [PATCH 0856/1110] drm/amd/dal: Refactor DC creation merge dc and dal
- init_data
-
-Also deletes unused members in the two init data structures
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 11 +--
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  5 --
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.h   |  1 -
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 89 ++++++++++------------
- drivers/gpu/drm/amd/dal/dc/dc.h                    | 12 +--
- drivers/gpu/drm/amd/dal/dc/dc_types.h              | 15 ----
- .../amd/dal/include/adapter_service_interface.h    |  4 -
- 7 files changed, 44 insertions(+), 93 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 257969f..ed2cdc5 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -246,8 +246,7 @@ static void hotplug_notify_work_func(struct work_struct *work)
-  */
- int amdgpu_dm_init(struct amdgpu_device *adev)
- {
--	struct dal_init_data init_data;
--	struct drm_device *ddev = adev->ddev;
-+	struct dc_init_data init_data;
- 	adev->dm.ddev = adev->ddev;
- 	adev->dm.adev = adev;
- 
-@@ -265,14 +264,6 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
- 		goto error;
- 	}
- 
--	if (ddev->pdev) {
--		init_data.bdf_info.DEVICE_NUMBER = PCI_SLOT(ddev->pdev->devfn);
--		init_data.bdf_info.FUNCTION_NUMBER =
--			PCI_FUNC(ddev->pdev->devfn);
--		if (ddev->pdev->bus)
--			init_data.bdf_info.BUS_NUMBER = ddev->pdev->bus->number;
--	}
--
- 	init_data.display_param = display_param;
- 
- 	init_data.asic_id.chip_family = adev->family;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 99ba0c7..339f046 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -1938,11 +1938,6 @@ struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
- 		(1 << info->gpio_info.clk_a_shift), &hw_info);
- }
- 
--struct bdf_info dal_adapter_service_get_adapter_info(struct adapter_service *as)
--{
--	return as->bdf_info;
--}
--
- /*
-  * dal_adapter_service_should_psr_skip_wait_for_pll_lock
-  *
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-index 7cc8991..57f9a87 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
-@@ -49,7 +49,6 @@ struct adapter_service {
- 	struct wireless_data wireless_data;
- 	struct hw_ctx_adapter_service *hw_ctx;
- 	struct integrated_info *integrated_info;
--	struct bdf_info bdf_info;
- 	uint32_t platform_methods_mask;
- 	uint32_t ac_level_percentage;
- 	uint32_t dc_level_percentage;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 44f43ea..ef238a0 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -69,7 +69,10 @@ static void destroy_links(struct core_dc *dc)
- 	}
- }
- 
--static bool create_links(struct core_dc *dc, const struct dc_init_data *init_params)
-+static bool create_links(
-+		struct core_dc *dc,
-+		struct adapter_service *as,
-+		uint32_t num_virtual_links)
- {
- 	int i;
- 	int connectors_num;
-@@ -77,7 +80,7 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 
- 	dc->link_count = 0;
- 
--	dcb = dal_adapter_service_get_bios_parser(init_params->adapter_srv);
-+	dcb = dal_adapter_service_get_bios_parser(as);
- 
- 	connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
-@@ -89,7 +92,7 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 		return false;
- 	}
- 
--	if (connectors_num == 0 && init_params->num_virtual_links == 0) {
-+	if (connectors_num == 0 && num_virtual_links == 0) {
- 		dm_error("DC: Number of connectors can not be zero!\n");
- 		return false;
- 	}
-@@ -98,14 +101,14 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 		"DC: %s: connectors_num: physical:%d, virtual:%d\n",
- 		__func__,
- 		connectors_num,
--		init_params->num_virtual_links);
-+		num_virtual_links);
- 
- 	for (i = 0; i < connectors_num; i++) {
- 		struct link_init_data link_init_params = {0};
- 		struct core_link *link;
- 
--		link_init_params.ctx = init_params->ctx;
--		link_init_params.adapter_srv = init_params->adapter_srv;
-+		link_init_params.ctx = dc->ctx;
-+		link_init_params.adapter_srv = as;
- 		link_init_params.connector_index = i;
- 		link_init_params.link_index = dc->link_count;
- 		link_init_params.dc = dc;
-@@ -120,7 +123,7 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 		}
- 	}
- 
--	for (i = 0; i < init_params->num_virtual_links; i++) {
-+	for (i = 0; i < num_virtual_links; i++) {
- 		struct core_link *link = dm_alloc(sizeof(*link));
- 		struct encoder_init_data enc_init = {0};
- 
-@@ -129,8 +132,8 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 			goto failed_alloc;
- 		}
- 
--		link->adapter_srv = init_params->adapter_srv;
--		link->ctx = init_params->ctx;
-+		link->adapter_srv = as;
-+		link->ctx = dc->ctx;
- 		link->dc = dc;
- 		link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
- 		link->link_id.type = OBJECT_TYPE_CONNECTOR;
-@@ -138,8 +141,8 @@ static bool create_links(struct core_dc *dc, const struct dc_init_data *init_par
- 		link->link_id.enum_id = ENUM_ID_1;
- 		link->link_enc = dm_alloc(sizeof(*link->link_enc));
- 
--		enc_init.adapter_service = init_params->adapter_srv;
--		enc_init.ctx = init_params->ctx;
-+		enc_init.adapter_service = as;
-+		enc_init.ctx = dc->ctx;
- 		enc_init.channel = CHANNEL_ID_UNKNOWN;
- 		enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
- 		enc_init.transmitter = TRANSMITTER_UNKNOWN;
-@@ -215,18 +218,18 @@ static void init_hw(struct core_dc *dc)
- }
- 
- static struct adapter_service *create_as(
--		struct dc_init_data *dc_init_data,
--		const struct dal_init_data *init)
-+		const struct dc_init_data *init,
-+		struct dc_context *dc_ctx)
- {
- 	struct adapter_service *as = NULL;
- 	struct as_init_data init_data;
- 
- 	dm_memset(&init_data, 0, sizeof(init_data));
- 
--	init_data.ctx = dc_init_data->ctx;
-+	init_data.ctx = dc_ctx;
- 
- 	/* BIOS parser init data */
--	init_data.bp_init_data.ctx = dc_init_data->ctx;
-+	init_data.bp_init_data.ctx = dc_ctx;
- 	init_data.bp_init_data.bios = init->asic_id.atombios_base_address;
- 
- 	/* HW init data */
-@@ -240,9 +243,6 @@ static struct adapter_service *create_as(
- 	init_data.hw_init_data.vram_width = init->asic_id.vram_width;
- 	init_data.hw_init_data.vram_type = init->asic_id.vram_type;
- 
--	/* bdf is BUS,DEVICE,FUNCTION*/
--	init_data.bdf_info = init->bdf_info;
--
- 	init_data.display_param = &init->display_param;
- 	init_data.vbios_override = init->vbios_override;
- 	init_data.dce_environment = init->dce_environment;
-@@ -298,72 +298,63 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
- 		1000);
- }
- 
--static bool construct(struct core_dc *dc, const struct dal_init_data *init_params)
-+static bool construct(struct core_dc *dc, const struct dc_init_data *init_params)
- {
- 	struct dal_logger *logger;
--	/* Tempory code
--	 * TODO: replace dal_init_data with dc_init_data when dal is removed
--	 */
--	struct dc_init_data dc_init_data = {0};
--
--	/* Create dc context */
--	/* A temp dc context is used only to allocate the memory for actual
--	 * dc context */
--	struct dc_context ctx = {0};
--	ctx.cgs_device = init_params->cgs_device;
--	ctx.dc = dc;
-+	struct adapter_service *as;
-+	struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
- 
--	dc_init_data.ctx = dm_alloc(sizeof(*dc_init_data.ctx));
--	if (!dc_init_data.ctx) {
-+
-+	if (!dc_ctx) {
- 		dm_error("%s: failed to create ctx\n", __func__);
- 		goto ctx_fail;
- 	}
--	dc_init_data.ctx->driver_context = init_params->driver;
--	dc_init_data.ctx->cgs_device = init_params->cgs_device;
--	dc_init_data.num_virtual_links = init_params->num_virtual_links;
--	dc_init_data.ctx->dc = dc;
-+
-+	dc_ctx->cgs_device = init_params->cgs_device;
-+	dc_ctx->driver_context = init_params->driver;
-+	dc_ctx->dc = dc;
- 
- 	/* Create logger */
--	logger = dal_logger_create(dc_init_data.ctx);
-+	logger = dal_logger_create(dc_ctx);
- 
- 	if (!logger) {
- 		/* can *not* call logger. call base driver 'print error' */
- 		dm_error("%s: failed to create Logger!\n", __func__);
- 		goto logger_fail;
- 	}
--	dc_init_data.ctx->logger = logger;
-+	dc_ctx->logger = logger;
- 
- 	/* Create adapter service */
--	dc_init_data.adapter_srv = create_as(&dc_init_data, init_params);
-+	as = create_as(init_params, dc_ctx);
- 
--	if (!dc_init_data.adapter_srv) {
-+	if (!as) {
- 		dm_error("%s: create_as() failed!\n", __func__);
- 		goto as_fail;
- 	}
- 
- 	/* Initialize HW controlled by Adapter Service */
- 	if (false == dal_adapter_service_initialize_hw_data(
--			dc_init_data.adapter_srv)) {
-+			as)) {
- 		dm_error("%s: dal_adapter_service_initialize_hw_data()"\
- 				"  failed!\n", __func__);
- 		/* Note that AS exist, so have to destroy it.*/
- 		goto as_fail;
- 	}
- 
--	dc->ctx = dc_init_data.ctx;
-+	dc->ctx = dc_ctx;
- 
- 	dc->ctx->dce_environment = dal_adapter_service_get_dce_environment(
--			dc_init_data.adapter_srv);
-+			as);
- 
- 	/* Create hardware sequencer */
--	if (!dc_construct_hw_sequencer(dc_init_data.adapter_srv, dc))
-+	if (!dc_construct_hw_sequencer(as, dc))
- 		goto hwss_fail;
- 
- 	if (!dc_construct_resource_pool(
--		dc_init_data.adapter_srv, dc, dc_init_data.num_virtual_links))
-+		as, dc, init_params->num_virtual_links))
- 		goto construct_resource_fail;
- 
--	if (!create_links(dc, &dc_init_data))
-+	if (!create_links(dc, as, init_params->num_virtual_links))
- 		goto create_links_fail;
- 
- 	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
-@@ -376,10 +367,10 @@ static bool construct(struct core_dc *dc, const struct dal_init_data *init_param
- construct_resource_fail:
- create_links_fail:
- as_fail:
--	dal_logger_destroy(&dc_init_data.ctx->logger);
-+	dal_logger_destroy(&dc_ctx->logger);
- logger_fail:
- hwss_fail:
--	dm_free(dc_init_data.ctx);
-+	dm_free(dc_ctx);
- ctx_fail:
- 	return false;
- }
-@@ -463,7 +454,7 @@ static int8_t acquire_first_free_underlay(
-  * Public functions
-  ******************************************************************************/
- 
--struct core_dc *dc_create(const struct dal_init_data *init_params)
-+struct core_dc *dc_create(const struct dc_init_data *init_params)
-  {
- 	struct dc_context ctx = {
- 		.driver_context = init_params->driver,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index aacdefe..41010f7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -38,11 +38,6 @@
- /*******************************************************************************
-  * Display Core Interfaces
-  ******************************************************************************/
--struct dc_init_data {
--	struct dc_context *ctx;
--	struct adapter_service *adapter_srv;
--	uint8_t num_virtual_links;
--};
- 
- struct dc_caps {
-     uint32_t max_targets;
-@@ -52,13 +47,12 @@ struct dc_caps {
- 
- void dc_get_caps(const struct core_dc *dc, struct dc_caps *caps);
- 
--struct dal_init_data {
-+struct dc_init_data {
- 	struct hw_asic_id asic_id;
--	struct view_port_alignment vp_alignment;
--	struct bdf_info bdf_info;
- 	struct dal_override_parameters display_param;
- 	void *driver; /* ctx */
- 	void *cgs_device;
-+
- 	uint8_t num_virtual_links;
- 	/*
- 	 * If 'vbios_override' not NULL, it will be called instead
-@@ -68,7 +62,7 @@ struct dal_init_data {
- 	enum dce_environment dce_environment;
- };
- 
--struct core_dc *dc_create(const struct dal_init_data *init_params);
-+struct core_dc *dc_create(const struct dc_init_data *init_params);
- void dc_destroy(struct core_dc **dc);
- 
- /*******************************************************************************
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index b737206..0fb4822 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -120,14 +120,6 @@ struct hw_asic_id {
- 	void *atombios_base_address;
- };
- 
--/* this is pci information. BDF stands for BUS,DEVICE,FUNCTION*/
--
--struct bdf_info {
--	uint16_t BUS_NUMBER:8;
--	uint16_t DEVICE_NUMBER:5;
--	uint16_t FUNCTION_NUMBER:3;
--};
--
- /* array index for integer override parameters*/
- enum int_param_array_index {
- 	DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0,
-@@ -534,13 +526,6 @@ enum dc_acpi_cm_power_state {
- 	DC_ACPI_CM_POWER_STATE_D3 = 8
- };
- 
--struct view_port_alignment {
--	uint8_t x_width_size_alignment;
--	uint8_t y_height_size_alignment;
--	uint8_t x_start_alignment;
--	uint8_t y_start_alignment;
--};
--
- enum dc_connection_type {
- 	dc_connection_none,
- 	dc_connection_single,
-diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-index a4b37ff..cc093b1 100644
---- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
-@@ -318,7 +318,6 @@ struct as_init_data {
- 	struct hw_asic_id hw_init_data;
- 	struct bp_init_data bp_init_data;
- 	struct dc_context *ctx;
--	struct bdf_info bdf_info;
- 	const struct dal_override_parameters *display_param;
- 	struct dc_bios *vbios_override;
- 	enum dce_environment dce_environment;
-@@ -580,9 +579,6 @@ struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
- 	struct adapter_service *as,
- 	struct graphics_object_i2c_info *info);
- 
--struct bdf_info dal_adapter_service_get_adapter_info(
--	struct adapter_service *as);
--
- /* Determine if this ASIC needs to wait on PLL lock bit */
- bool dal_adapter_service_should_psr_skip_wait_for_pll_lock(
- 	struct adapter_service *as);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0857-drm-amd-dal-Use-native-memset-directly.patch b/common/recipes-kernel/linux/files/0857-drm-amd-dal-Use-native-memset-directly.patch
deleted file mode 100644
index 6dcb3518..00000000
--- a/common/recipes-kernel/linux/files/0857-drm-amd-dal-Use-native-memset-directly.patch
+++ /dev/null
@@ -1,735 +0,0 @@
-From 2242a5491fe574b3bf90f4ad6d0e1c7e2b4b908e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 14:39:32 -0500
-Subject: [PATCH 0857/1110] drm/amd/dal: Use native memset directly
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c |  5 ---
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  2 +-
- .../amd/dal/dc/asic_capability/asic_capability.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |  2 +-
- .../gpu/drm/amd/dal/dc/basics/register_logger.c    |  4 +--
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 20 +++++------
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    | 42 +++++++++++-----------
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  4 +--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 14 ++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    |  4 +--
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c |  4 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c   |  2 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c   |  4 +--
- drivers/gpu/drm/amd/dal/dc/dm_services.h           |  2 --
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |  8 ++---
- .../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c |  4 +--
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c     |  2 +-
- 25 files changed, 67 insertions(+), 74 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index 26208eb..5823789 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -45,11 +45,6 @@ void dm_memmove(void *dst, const void *src, uint32_t size)
- 	memmove(dst, src, size);
- }
- 
--void dm_memset(void *p, int32_t c, uint32_t count)
--{
--	memset(p, c, count);
--}
--
- int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
- {
- 	return memcmp(p1, p2, count);
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 339f046..9a68ed9 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -597,7 +597,7 @@ static bool generate_feature_set(
- 	uint32_t entry_num = 0;
- 	const struct feature_source_entry *entry = NULL;
- 
--	dm_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
-+	memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
- 	entry_num = get_feature_entries_num();
- 
- 	while (i != entry_num) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index f7fa96c..75e0e27 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -55,7 +55,7 @@ static bool construct(
- 	bool asic_supported = false;
- 
- 	cap->ctx = ctx;
--	dm_memset(cap->data, 0, sizeof(cap->data));
-+	memset(cap->data, 0, sizeof(cap->data));
- 
- 	/* ASIC data */
- 	cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index 269c75d..c297d95 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -157,7 +157,7 @@ static struct audio_feature_support get_supported_features(struct audio *audio)
- 	/*DCE specific, must be implemented in derived*/
- 	struct audio_feature_support features;
- 
--	dm_memset(&features, 0, sizeof(features));
-+	memset(&features, 0, sizeof(features));
- 
- 	features.ENGINE_DIGA = 1;
- 	features.ENGINE_DIGB = 1;
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-index 6d32b1b..b8d57d9 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
-@@ -137,7 +137,7 @@ void dal_reg_logger_push(const char *caller_func)
- 	if (NULL == free_stack_location)
- 		return;
- 
--	dm_memset(free_stack_location, 0, sizeof(*free_stack_location));
-+	memset(free_stack_location, 0, sizeof(*free_stack_location));
- 
- 	free_stack_location->current_caller_func = caller_func;
- 	free_stack_location->current_pid = dm_get_pid();
-@@ -170,7 +170,7 @@ void dal_reg_logger_pop(void)
- 			dm_get_pid(),
- 			dm_get_tgid());
- 
--	dm_memset(top_stack_location, 0, sizeof(*top_stack_location));
-+	memset(top_stack_location, 0, sizeof(*top_stack_location));
- }
- 
- void dal_reg_logger_rw_count_increment(void)
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index f433f8e..0fe8afc 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -377,7 +377,7 @@ static enum bp_result bios_parser_get_oem_ddc_info(struct dc_bios *dcb,
- 			ATOM_I2C_RECORD record;
- 			ATOM_I2C_ID_CONFIG_ACCESS *config;
- 
--			dm_memset(&record, 0, sizeof(record));
-+			memset(&record, 0, sizeof(record));
- 
- 			config = &tbl->sucI2cId + index - 1;
- 
-@@ -873,7 +873,7 @@ static enum bp_result get_firmware_info_v1_4(
- 	if (!firmware_info)
- 		return BP_RESULT_BADBIOSTABLE;
- 
--	dm_memset(info, 0, sizeof(*info));
-+	memset(info, 0, sizeof(*info));
- 
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
-@@ -924,7 +924,7 @@ static enum bp_result get_firmware_info_v2_1(
- 	if (!firmwareInfo)
- 		return BP_RESULT_BADBIOSTABLE;
- 
--	dm_memset(info, 0, sizeof(*info));
-+	memset(info, 0, sizeof(*info));
- 
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
-@@ -1010,7 +1010,7 @@ static enum bp_result get_firmware_info_v2_2(
- 	if (!firmware_info)
- 		return BP_RESULT_BADBIOSTABLE;
- 
--	dm_memset(info, 0, sizeof(*info));
-+	memset(info, 0, sizeof(*info));
- 
- 	/* Pixel clock pll information. We need to convert from 10KHz units into
- 	 * KHz units */
-@@ -1115,7 +1115,7 @@ static enum bp_result get_ss_info_v3_1(
- 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
- 				&ss_table_header_include->asSpreadSpectrum[0];
- 
--	dm_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+	memset(ss_info, 0, sizeof(struct spread_spectrum_info));
- 
- 	for (i = 0; i < table_size; i++) {
- 		if (tbl[i].ucClockIndication != (uint8_t) id)
-@@ -1661,7 +1661,7 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
- 	header = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
- 		DATA_TABLES(ASIC_InternalSS_Info));
- 
--	dm_memset(info, 0, sizeof(struct spread_spectrum_info));
-+	memset(info, 0, sizeof(struct spread_spectrum_info));
- 
- 	tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
- 			- sizeof(ATOM_COMMON_TABLE_HEADER))
-@@ -1765,7 +1765,7 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 		if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
- 			continue;
- 
--		dm_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+		memset(ss_info, 0, sizeof(struct spread_spectrum_info));
- 
- 		if (ATOM_EXTERNAL_SS_MASK &
- 				tbl->asSS_Info[i].ucSpreadSpectrumType)
-@@ -1857,7 +1857,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
- 		|| 2 > lvds->sHeader.ucTableContentRevision)
- 		return BP_RESULT_UNSUPPORTED;
- 
--	dm_memset(info, 0, sizeof(struct embedded_panel_info));
-+	memset(info, 0, sizeof(struct embedded_panel_info));
- 
- 	/* We need to convert from 10KHz units into KHz units*/
- 	info->lcd_timing.pixel_clk =
-@@ -1975,7 +1975,7 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 			&& (3 <= lvds->sHeader.ucTableContentRevision)))
- 		return BP_RESULT_UNSUPPORTED;
- 
--	dm_memset(info, 0, sizeof(struct embedded_panel_info));
-+	memset(info, 0, sizeof(struct embedded_panel_info));
- 
- 	/* We need to convert from 10KHz units into KHz units */
- 	info->lcd_timing.pixel_clk =
-@@ -3826,7 +3826,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 	if (!opm_object)
- 		return BP_RESULT_UNSUPPORTED;
- 
--	dm_memset(&ext_display_connection_info_tbl, 0,
-+	memset(&ext_display_connection_info_tbl, 0,
- 			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
- 
- 	connector_tbl_offset = bp->object_info_tbl_offset
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index 2ea0576..ccd1c7e 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -365,7 +365,7 @@ static enum bp_result transmitter_control_v2(
- 	enum connector_id connector_id =
- 		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	switch (cntl->transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -489,7 +489,7 @@ static enum bp_result transmitter_control_v3(
- 	bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
- 					|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	switch (cntl->transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -638,7 +638,7 @@ static enum bp_result transmitter_control_v4(
- 			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	switch (cntl->transmitter) {
- 	case TRANSMITTER_UNIPHY_A:
-@@ -776,7 +776,7 @@ static enum bp_result transmitter_control_v1_5(
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 params;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
- 	params.ucAction = (uint8_t)cntl->action;
- 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-@@ -842,7 +842,7 @@ static enum bp_result transmitter_control_v1_6(
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 params;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
- 	params.ucAction = (uint8_t)cntl->action;
- 
-@@ -946,7 +946,7 @@ static enum bp_result set_pixel_clock_v3(
- 	PIXEL_CLOCK_PARAMETERS_V3 *params;
- 	SET_PIXEL_CLOCK_PS_ALLOCATION allocation;
- 
--	dm_memset(&allocation, 0, sizeof(allocation));
-+	memset(&allocation, 0, sizeof(allocation));
- 
- 	if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
- 		allocation.sPCLKInput.ucPpll = ATOM_PPLL1;
-@@ -1019,7 +1019,7 @@ static enum bp_result set_pixel_clock_v5(
- 	uint8_t controller_id;
- 	uint32_t pll_id;
- 
--	dm_memset(&clk, 0, sizeof(clk));
-+	memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
- 			&& bp->cmd_helper->controller_id_to_atom(
-@@ -1076,7 +1076,7 @@ static enum bp_result set_pixel_clock_v6(
- 	uint8_t controller_id;
- 	uint32_t pll_id;
- 
--	dm_memset(&clk, 0, sizeof(clk));
-+	memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
- 			&& bp->cmd_helper->controller_id_to_atom(
-@@ -1155,7 +1155,7 @@ static enum bp_result set_pixel_clock_v7(
- 	uint8_t controller_id;
- 	uint32_t pll_id;
- 
--	dm_memset(&clk, 0, sizeof(clk));
-+	memset(&clk, 0, sizeof(clk));
- 
- 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
- 			&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
-@@ -1265,7 +1265,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v1(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	ENABLE_SPREAD_SPECTRUM_ON_PPLL params;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	if ((enable == true) && (bp_params->percentage > 0))
- 		params.ucEnable = ATOM_ENABLE;
-@@ -1309,7 +1309,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v2(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 params;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
- 		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P1PLL;
-@@ -1361,7 +1361,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v3(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 params;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	switch (bp_params->pll_id) {
- 	case CLOCK_SOURCE_ID_PLL0:
-@@ -1482,7 +1482,7 @@ static enum bp_result adjust_display_pll_v3(
- 	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 params;
- 	uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	/* We need to convert from KHz units into 10KHz units and then convert
- 	 * output pixel clock back 10KHz-->KHz */
-@@ -1729,7 +1729,7 @@ static enum signal_type dac_load_detection_v3(
- 	DAC_LOAD_DETECTION_PS_ALLOCATION params;
- 	enum signal_type signal = SIGNAL_TYPE_NONE;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	/* load detection is cupported for CRT, TV and CV */
- 	switch (display_signal) {
-@@ -2131,7 +2131,7 @@ static enum bp_result select_crtc_source_v2(
- 	uint32_t atom_engine_id;
- 	enum signal_type s = bp_params->signal;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	/* set controller id */
- 	if (bp->cmd_helper->controller_id_to_atom(
-@@ -2172,7 +2172,7 @@ static enum bp_result select_crtc_source_v3(
- 	uint32_t atom_engine_id;
- 	enum signal_type s = bp_params->signal;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
- 			&atom_controller_id))
-@@ -2343,7 +2343,7 @@ static enum bp_result program_clock_v5(
- 	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 params;
- 	uint32_t atom_pll_id;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 	if (!bp->cmd_helper->clock_source_id_to_atom(
- 			bp_params->pll_id, &atom_pll_id)) {
- 		BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
-@@ -2374,7 +2374,7 @@ static enum bp_result program_clock_v6(
- 	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 params;
- 	uint32_t atom_pll_id;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	if (!bp->cmd_helper->clock_source_id_to_atom(
- 			bp_params->pll_id, &atom_pll_id)) {
-@@ -2433,7 +2433,7 @@ static enum bp_result compute_memore_engine_pll_v4(
- 	enum bp_result result = BP_RESULT_FAILURE;
- 	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
- 
-@@ -2489,7 +2489,7 @@ static enum bp_result external_encoder_control_v3(
- 	struct graphics_object_id encoder;
- 	bool is_input_signal_dp = false;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	cntl_params = &params.sExtEncoder;
- 
-@@ -2687,7 +2687,7 @@ static enum bp_result set_dce_clock_v2_1(
- 	uint32_t atom_clock_type;
- 	const struct command_table_helper *cmd = bp->cmd_helper;
- 
--	dm_memset(&params, 0, sizeof(params));
-+	memset(&params, 0, sizeof(params));
- 
- 	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
- 			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index b6ee5bf..4973132 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -580,7 +580,7 @@ static void get_bios_event_info(
- 	uint32_t s2, s6;
- 	uint32_t clear_mask;
- 
--	dm_memset(info, 0, sizeof(struct bios_event_info));
-+	memset(info, 0, sizeof(struct bios_event_info));
- 
- 	/* Handle backlight event ONLY. PPLib still handling other events */
- 	s6 = dm_read_reg(ctx, mmBIOS_SCRATCH_6);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index ef238a0..9ae1bc7 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -224,7 +224,7 @@ static struct adapter_service *create_as(
- 	struct adapter_service *as = NULL;
- 	struct as_init_data init_data;
- 
--	dm_memset(&init_data, 0, sizeof(init_data));
-+	memset(&init_data, 0, sizeof(init_data));
- 
- 	init_data.ctx = dc_ctx;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 9bfa35b..58c7d43 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1100,7 +1100,7 @@ static void dpcd_configure_panel_mode(
- 	union dpcd_edp_config edp_config_set;
- 	bool panel_mode_edp = false;
- 
--	dm_memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
-+	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
- 
- 	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
- 
-@@ -1226,7 +1226,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
- 			normalized_pix_clk,
- 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
- 
--	dm_memset(&stream->sink->link->public.cur_link_settings, 0,
-+	memset(&stream->sink->link->public.cur_link_settings, 0,
- 			sizeof(struct dc_link_settings));
- 
- 	link->link_enc->funcs->enable_tmds_output(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index f211408..f7a14a2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -1051,7 +1051,7 @@ struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
- 
- void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
- {
--	dm_memset(&ddc_service->dp_receiver_id_info,
-+	memset(&ddc_service->dp_receiver_id_info,
- 		0, sizeof(struct dp_receiver_id_info));
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 31f8ce3..ca7aa20 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -467,7 +467,7 @@ static void get_lane_status_and_drive_settings(
- 	struct link_training_settings request_settings = {{0}};
- 	uint32_t lane;
- 
--	dm_memset(req_settings, '\0', sizeof(struct link_training_settings));
-+	memset(req_settings, '\0', sizeof(struct link_training_settings));
- 
- 	core_link_read_dpcd(
- 		link,
-@@ -848,8 +848,8 @@ static bool perform_clock_recovery_sequence(
- 	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
- 	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
- 
--		dm_memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
--		dm_memset(&dpcd_lane_status_updated, '\0',
-+		memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
-+		memset(&dpcd_lane_status_updated, '\0',
- 		sizeof(dpcd_lane_status_updated));
- 
- 		/* 1. call HWSS to set lane settings*/
-@@ -975,7 +975,7 @@ bool perform_link_training(
- 	struct link_training_settings lt_settings;
- 
- 	status = false;
--	dm_memset(&lt_settings, '\0', sizeof(lt_settings));
-+	memset(&lt_settings, '\0', sizeof(lt_settings));
- 
- 	lt_settings.link_settings.link_rate = link_setting->link_rate;
- 	lt_settings.link_settings.lane_count = link_setting->lane_count;
-@@ -1751,10 +1751,10 @@ static void retrieve_link_cap(struct core_link *link)
- 	union edp_configuration_cap edp_config_cap;
- 	union dp_downstream_port_present ds_port = { 0 };
- 
--	dm_memset(dpcd_data, '\0', sizeof(dpcd_data));
--	dm_memset(&down_strm_port_count,
-+	memset(dpcd_data, '\0', sizeof(dpcd_data));
-+	memset(&down_strm_port_count,
- 		'\0', sizeof(union down_stream_port_count));
--	dm_memset(&edp_config_cap, '\0',
-+	memset(&edp_config_cap, '\0',
- 		sizeof(union edp_configuration_cap));
- 
- 	core_link_read_dpcd(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-index 63ff4b0..98ff372 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
-@@ -89,7 +89,7 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
- 	link->link_enc->funcs->disable_output(link->link_enc, signal);
- 
- 	/* Clear current link setting.*/
--	dm_memset(&link->public.cur_link_settings, 0,
-+	memset(&link->public.cur_link_settings, 0,
- 			sizeof(link->public.cur_link_settings));
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index e397751..c214870 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -900,7 +900,7 @@ static enum ds_color_space build_default_color_space(
- static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 	struct encoder_info_frame *encoder_info_frame)
- {
--	dm_memset(
-+	memset(
- 		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
- 
- 	/* For gamut we recalc checksum */
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index 4ceee56..c78366a 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -46,7 +46,7 @@ static void build_bit_depth_reduction_params(
- 		const struct core_stream *stream,
- 		struct bit_depth_reduction_params *fmt_bit_depth)
- {
--	dm_memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
-+	memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
- 
- 	/*TODO: Need to un-hardcode, refer to function with same name
- 	 * in dal2 hw_sequencer*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index 033afe8..d9c1d86 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -475,7 +475,7 @@ static uint32_t dce110_get_pix_clk_dividers(
- 		return pll_calc_error;
- 	}
- 
--	dm_memset(pll_settings, 0, sizeof(*pll_settings));
-+	memset(pll_settings, 0, sizeof(*pll_settings));
- 
- 	if (cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
- 		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-@@ -581,7 +581,7 @@ static bool calculate_ss(
- 	if (pll_settings == NULL)
- 		return false;
- 
--	dm_memset(ds_data, 0, sizeof(struct delta_sigma_data));
-+	memset(ds_data, 0, sizeof(struct delta_sigma_data));
- 
- 	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
- 	/* 6 decimal point support in fractional feedback divider */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 716a762..de727fb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1559,7 +1559,7 @@ static void enable_timing_synchronization(
- 
- 	/* Reset slave controllers on master VSync */
- 	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
--	dm_memset(&trigger_params, 0, sizeof(trigger_params));
-+	memset(&trigger_params, 0, sizeof(trigger_params));
- 
- 	trigger_params.edge = TRIGGER_EDGE_DEFAULT;
- 	trigger_params.source = SYNC_SOURCE_GSL_GROUP0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-index 08df2ba..5fb827a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -618,7 +618,7 @@ static void set_rgb_limited_range_adjustment(
- 	matrix[6] = change_matrix[10];
- 	matrix[7] = change_matrix[11];
- 
--	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-@@ -692,7 +692,7 @@ static void set_yuv_adjustment(
- 		calculate_adjustments(
- 			ideals, &adjustments, matrix);
- 
--	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-index 2e50e5a..216e275 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
-@@ -804,7 +804,7 @@ static void set_yuv_adjustment(
- 		calculate_adjustments(
- 			ideals, &adjustments, matrix);
- 
--	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index ceb91fc..70b82f1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -518,7 +518,7 @@ bool dce110_timing_generator_program_timing_generator(
- 			dc_crtc_timing->h_front_porch;
- 	uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;
- 
--	dm_memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
-+	memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
- 
- 	/* Due to an asic bug we need to apply the Front Porch workaround prior
- 	 * to programming the timing.
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-index a8ad163..464f0ad 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-@@ -619,7 +619,7 @@ static void set_rgb_limited_range_adjustment(
- 	matrix[6] = change_matrix[10];
- 	matrix[7] = change_matrix[11];
- 
--	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-@@ -693,7 +693,7 @@ static void set_yuv_adjustment(
- 		calculate_adjustments(
- 			ideals, &adjustments, matrix);
- 
--	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
-+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
- 
- 	setup_reg_format(matrix, reg_matrix.regval);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index d3820f8..2d33187 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -44,8 +44,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--void dm_memset(void *p, int32_t c, uint32_t count);
--
- void dm_memmove(void *dst, const void *src, uint32_t size);
- 
- int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 2ee5773..ba9a1fa 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -649,8 +649,8 @@ static bool display_clock_integrated_info_construct(
- 	struct display_clock *base = &disp_clk->disp_clk_base;
- 	bool res;
- 
--	dm_memset(&info, 0, sizeof(struct integrated_info));
--	dm_memset(&fw_info, 0, sizeof(struct firmware_info));
-+	memset(&info, 0, sizeof(struct integrated_info));
-+	memset(&fw_info, 0, sizeof(struct firmware_info));
- 
- 	res = dal_adapter_service_get_integrated_info(as, &info);
- 
-@@ -784,7 +784,7 @@ static void set_clock(
- 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(base->as);
- 
- 	/* Prepare to program display clock*/
--	dm_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-+	memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
- 
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = base->id;
-@@ -907,7 +907,7 @@ static bool dal_display_clock_dce110_construct(
- 			struct spread_spectrum_info info;
- 			bool result;
- 
--			dm_memset(&info, 0, sizeof(info));
-+			memset(&info, 0, sizeof(info));
- 
- 			result =
- 				dal_adapter_service_get_ss_info(
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-index 5346ded..74d5b2e 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-@@ -473,7 +473,7 @@ static void set_clock(
- 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(dc->as);
- 
- 	/* Prepare to program display clock*/
--	dm_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-+	memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
- 
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = dc->id;
-@@ -701,7 +701,7 @@ static void display_clock_ss_construct(
- 		struct spread_spectrum_info ss_info;
- 		bool res;
- 
--		dm_memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
-+		memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
- 
- 		res = dal_adapter_service_get_ss_info(as,
- 			AS_SIGNAL_TYPE_GPU_PLL, 0, &ss_info);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-index 7042d10..725e183 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-@@ -264,7 +264,7 @@ static bool read_command(
- 	ctx.request.delay = 0;
- 
- 	do {
--		dm_memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-+		memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
- 
- 		ctx.request.data = ctx.buffer + ctx.offset;
- 		ctx.request.length = ctx.current_read_length;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0858-drm-amd-dal-Use-native-memmove-directly.patch b/common/recipes-kernel/linux/files/0858-drm-amd-dal-Use-native-memmove-directly.patch
deleted file mode 100644
index ad9805c1..00000000
--- a/common/recipes-kernel/linux/files/0858-drm-amd-dal-Use-native-memmove-directly.patch
+++ /dev/null
@@ -1,352 +0,0 @@
-From 0d7d11832f4cd3c2ac31a0b3197e16242860b9e6 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 14:41:11 -0500
-Subject: [PATCH 0858/1110] drm/amd/dal: Use native memmove directly
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c |  2 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c  | 11 +++--------
- drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c    |  2 +-
- drivers/gpu/drm/amd/dal/dc/basics/logger.c              | 10 +++++-----
- drivers/gpu/drm/amd/dal/dc/basics/vector.c              | 12 ++++++------
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c           |  8 ++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c           |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c            |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c           | 10 +++++-----
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c             |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c      |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c        |  2 +-
- drivers/gpu/drm/amd/dal/dc/dm_services.h                |  2 --
- 13 files changed, 30 insertions(+), 37 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 6876643..ed0b9d7 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -198,7 +198,7 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 	if (!dc_sink)
- 		return NULL;
- 
--	dm_memmove(dc_sink->dc_edid.raw_edid, edid, len);
-+	memmove(dc_sink->dc_edid.raw_edid, edid, len);
- 	dc_sink->dc_edid.length = len;
- 
- 	if (!dc_link_add_remote_sink(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index 5823789..f587bc3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -40,11 +40,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--void dm_memmove(void *dst, const void *src, uint32_t size)
--{
--	memmove(dst, src, size);
--}
--
- int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
- {
- 	return memcmp(p1, p2, count);
-@@ -262,17 +257,17 @@ static void get_default_clock_levels(
- 	switch (clk_type) {
- 	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
- 		clks->num_levels = 6;
--		dm_memmove(clks->clocks_in_khz, disp_clks_in_khz,
-+		memmove(clks->clocks_in_khz, disp_clks_in_khz,
- 				sizeof(disp_clks_in_khz));
- 		break;
- 	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
- 		clks->num_levels = 6;
--		dm_memmove(clks->clocks_in_khz, sclks_in_khz,
-+		memmove(clks->clocks_in_khz, sclks_in_khz,
- 				sizeof(sclks_in_khz));
- 		break;
- 	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
- 		clks->num_levels = 2;
--		dm_memmove(clks->clocks_in_khz, mclks_in_khz,
-+		memmove(clks->clocks_in_khz, mclks_in_khz,
- 				sizeof(mclks_in_khz));
- 		break;
- 	default:
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 9a68ed9..f7aea01 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -1365,7 +1365,7 @@ bool dal_adapter_service_get_integrated_info(
- 	if (info == NULL || as->integrated_info == NULL)
- 		return false;
- 
--	dm_memmove(info, as->integrated_info, sizeof(struct integrated_info));
-+	memmove(info, as->integrated_info, sizeof(struct integrated_info));
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index 60c13fc..f637c3f 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -470,7 +470,7 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			/* No wrap around, copy 'size' bytes
- 			 * from 'entry->buf' to 'log_buffer'
- 			 */
--			dm_memmove(logger->log_buffer +
-+			memmove(logger->log_buffer +
- 					logger->buffer_write_offset,
- 					entry->buf, size);
- 			logger->buffer_write_offset += size;
-@@ -482,10 +482,10 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			int space_after_wrap = total_free_space -
- 					space_before_wrap;
- 
--			dm_memmove(logger->log_buffer +
-+			memmove(logger->log_buffer +
- 					logger->buffer_write_offset,
- 					entry->buf, space_before_wrap);
--			dm_memmove(logger->log_buffer, entry->buf +
-+			memmove(logger->log_buffer, entry->buf +
- 					space_before_wrap, space_after_wrap);
- 
- 			logger->buffer_write_offset = space_after_wrap;
-@@ -499,7 +499,7 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 			flush_to_debug_console(logger);
- 
- 			/* Start writing to beginning of buffer */
--			dm_memmove(logger->log_buffer, entry->buf, size);
-+			memmove(logger->log_buffer, entry->buf, size);
- 			logger->buffer_write_offset = size;
- 			logger->buffer_read_offset = 0;
- 		}
-@@ -568,7 +568,7 @@ static void append_entry(
- 	}
- 
- 	/* Todo: check if off by 1 byte due to \0 anywhere */
--	dm_memmove(entry->buf + entry->buf_offset, buffer, buf_size);
-+	memmove(entry->buf + entry->buf_offset, buffer, buf_size);
- 	entry->buf_offset += buf_size;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/vector.c b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-index 7ad7fef..bb72a18 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/vector.c
-@@ -77,7 +77,7 @@ bool dal_vector_presized_costruct(
- 	 * initialises the memory to. */
- 	if (NULL != initial_value) {
- 		for (i = 0; i < count; ++i)
--			dm_memmove(
-+			memmove(
- 				vector->container + i * struct_size,
- 				initial_value,
- 				struct_size);
-@@ -169,7 +169,7 @@ bool dal_vector_remove_at_index(
- 		return false;
- 
- 	if (index != vector->count - 1)
--		dm_memmove(
-+		memmove(
- 			vector->container + (index * vector->struct_size),
- 			vector->container + ((index + 1) * vector->struct_size),
- 			(vector->count - index - 1) * vector->struct_size);
-@@ -189,7 +189,7 @@ void dal_vector_set_at_index(
- 		BREAK_TO_DEBUGGER();
- 		return;
- 	}
--	dm_memmove(
-+	memmove(
- 		where,
- 		what,
- 		vector->struct_size);
-@@ -218,12 +218,12 @@ bool dal_vector_insert_at(
- 	insert_address = vector->container + (vector->struct_size * position);
- 
- 	if (vector->count && position < vector->count)
--		dm_memmove(
-+		memmove(
- 			insert_address + vector->struct_size,
- 			insert_address,
- 			vector->struct_size * (vector->count - position));
- 
--	dm_memmove(
-+	memmove(
- 		insert_address,
- 		what,
- 		vector->struct_size);
-@@ -272,7 +272,7 @@ struct vector *dal_vector_clone(
- 	}
- 
- 	/* copy vector's data */
--	dm_memmove(vec_cloned->container, vector->container,
-+	memmove(vec_cloned->container, vector->container,
- 			vec_cloned->struct_size * vec_cloned->capacity);
- 
- 	return vec_cloned;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 0fe8afc..a43da0c 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -2546,7 +2546,7 @@ static enum bp_result bios_parser_get_faked_edid_buf(
- 	if (len < edid_size)
- 		return BP_RESULT_BADINPUT; /* buffer not big enough to fill */
- 
--	dm_memmove(buff, &edid_record->ucFakeEDIDString, edid_size);
-+	memmove(buff, &edid_record->ucFakeEDIDString, edid_size);
- 
- 	return BP_RESULT_OK;
- }
-@@ -4091,7 +4091,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 			return;
- 		}
- 
--		dm_memmove(bp->bios_local_image, bp->bios, bp->bios_size);
-+		memmove(bp->bios_local_image, bp->bios, bp->bios_size);
- 		original_bios = bp->bios;
- 		bp->bios = bp->bios_local_image;
- 		connector_tbl =
-@@ -4105,7 +4105,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 			/* Patching the bios image has failed. We will copy
- 			 * again original image provided and afterwards
- 			 * only remove null entries */
--			dm_memmove(
-+			memmove(
- 					bp->bios_local_image,
- 					original_bios,
- 					bp->bios_size);
-@@ -4122,7 +4122,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 				continue;
- 
- 			if (i != connectors_num) {
--				dm_memmove(
-+				memmove(
- 						&connector_tbl->
- 						asObjects[connectors_num],
- 						object,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index f7a14a2..22017ff 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -745,7 +745,7 @@ uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc)
- 
- void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf)
- {
--	dm_memmove(edid_buf,
-+	memmove(edid_buf,
- 			ddc->edid_buf, ddc->edid_buf_len);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index ca7aa20..e4ea886 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -242,7 +242,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
- 	size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
- 
- 	 // 0x00103 - 0x00102
--	dm_memmove(
-+	memmove(
- 		&dpcd_lt_buffer[DPCD_ADDRESS_LANE0_SET - dpcd_base_lt_offset],
- 		dpcd_lane,
- 		size_in_bytes);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index c214870..519329b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -909,7 +909,7 @@ static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 		uint8_t *ptr;
- 		uint8_t i;
- 
--		dm_memmove(
-+		memmove(
- 						&encoder_info_frame->gamut,
- 						&hw_info_frame->gamut_packet,
- 						sizeof(struct hw_info_packet));
-@@ -924,28 +924,28 @@ static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
- 	}
- 
- 	if (hw_info_frame->avi_info_packet.valid) {
--		dm_memmove(
-+		memmove(
- 						&encoder_info_frame->avi,
- 						&hw_info_frame->avi_info_packet,
- 						sizeof(struct hw_info_packet));
- 	}
- 
- 	if (hw_info_frame->vendor_info_packet.valid) {
--		dm_memmove(
-+		memmove(
- 						&encoder_info_frame->vendor,
- 						&hw_info_frame->vendor_info_packet,
- 						sizeof(struct hw_info_packet));
- 	}
- 
- 	if (hw_info_frame->spd_packet.valid) {
--		dm_memmove(
-+		memmove(
- 						&encoder_info_frame->spd,
- 						&hw_info_frame->spd_packet,
- 						sizeof(struct hw_info_packet));
- 	}
- 
- 	if (hw_info_frame->vsc_packet.valid) {
--		dm_memmove(
-+		memmove(
- 						&encoder_info_frame->vsc,
- 						&hw_info_frame->vsc_packet,
- 						sizeof(struct hw_info_packet));
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index c78366a..b696401 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -108,7 +108,7 @@ static bool construct(struct core_stream *stream,
- 	stream->public.audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
- 	stream->public.audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
- 	stream->public.audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
--	dm_memmove(
-+	memmove(
- 		stream->public.audio_info.display_name,
- 		dc_sink_data->edid_caps.display_name,
- 		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-index 5fb827a..b16d9b0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
-@@ -598,7 +598,7 @@ static void set_rgb_limited_range_adjustment(
- 
- 	calculate_adjustments(ideals, &adjustments, matrix);
- 
--	dm_memmove(change_matrix, matrix, sizeof(matrix));
-+	memmove(change_matrix, matrix, sizeof(matrix));
- 
- 	/* from 1 -> 3 */
- 	matrix[8] = change_matrix[0];
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-index 464f0ad..b39930e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
-@@ -599,7 +599,7 @@ static void set_rgb_limited_range_adjustment(
- 
- 	calculate_adjustments(ideals, &adjustments, matrix);
- 
--	dm_memmove(change_matrix, matrix, sizeof(matrix));
-+	memmove(change_matrix, matrix, sizeof(matrix));
- 
- 	/* from 1 -> 3 */
- 	matrix[8] = change_matrix[0];
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 2d33187..8f1bb5c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -44,8 +44,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--void dm_memmove(void *dst, const void *src, uint32_t size);
--
- int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
- 
- int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0859-drm-amd-dal-Use-native-memcmp-directly.patch b/common/recipes-kernel/linux/files/0859-drm-amd-dal-Use-native-memcmp-directly.patch
deleted file mode 100644
index 3be30733..00000000
--- a/common/recipes-kernel/linux/files/0859-drm-amd-dal-Use-native-memcmp-directly.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 584476ee37b5d38e15b654d5cb75a0b6e3faa6a0 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 14:42:36 -0500
-Subject: [PATCH 0859/1110] drm/amd/dal: Use native memcmp directly
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 5 -----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c          | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c      | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dm_services.h               | 2 --
- 5 files changed, 5 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index f587bc3..7bab44a 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -40,11 +40,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
--{
--	return memcmp(p1, p2, count);
--}
--
- int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count)
- {
- 	return strncmp(p1, p2, count);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 519329b..fcb9a0f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -98,7 +98,7 @@ bool is_same_timing(
- 	const struct dc_crtc_timing *timing1,
- 	const struct dc_crtc_timing *timing2)
- {
--	return dm_memcmp(timing1, timing2, sizeof(struct dc_crtc_timing)) == 0;
-+	return memcmp(timing1, timing2, sizeof(struct dc_crtc_timing)) == 0;
- }
- 
- static bool is_sharable_clk_src(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 99484f6..2ebd398 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -813,7 +813,7 @@ enum dc_status dce110_validate_bandwidth(
- 		 * the same
- 		 */
- 		if (number_of_displays != 0 && all_displays_in_sync)
--			if (dm_memcmp(&prev_timing,
-+			if (memcmp(&prev_timing,
- 				&pipe_ctx->stream->public.timing,
- 				sizeof(struct dc_crtc_timing)) != 0)
- 				all_displays_in_sync = false;
-@@ -857,7 +857,7 @@ enum dc_status dce110_validate_bandwidth(
- 			"%s: Bandwidth validation failed!",
- 			__func__);
- 
--	if (dm_memcmp(&dc->current_context.bw_results,
-+	if (memcmp(&dc->current_context.bw_results,
- 			&context->bw_results, sizeof(context->bw_results))) {
- 		struct log_entry log_entry;
- 		dal_logger_open(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index ae85fec..04f235a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -811,7 +811,7 @@ enum dc_status dce80_validate_bandwidth(
- 		 * the same
- 		 */
- 		if (number_of_displays != 0 && all_displays_in_sync)
--			if (dm_memcmp(&prev_timing,
-+			if (memcmp(&prev_timing,
- 				&pipe_ctx->stream->public.timing,
- 				sizeof(struct dc_crtc_timing)) != 0)
- 				all_displays_in_sync = false;
-@@ -855,7 +855,7 @@ enum dc_status dce80_validate_bandwidth(
- 			"%s: Bandwidth validation failed!",
- 			__func__);
- 
--	if (dm_memcmp(&dc->current_context.bw_results,
-+	if (memcmp(&dc->current_context.bw_results,
- 			&context->bw_results, sizeof(context->bw_results))) {
- 		struct log_entry log_entry;
- 		dal_logger_open(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 8f1bb5c..3862682 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -44,8 +44,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
--
- int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count);
- 
- irq_handler_idx dm_register_interrupt(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0860-drm-amd-dal-Use-native-strncmp-directly.patch b/common/recipes-kernel/linux/files/0860-drm-amd-dal-Use-native-strncmp-directly.patch
deleted file mode 100644
index b7948830..00000000
--- a/common/recipes-kernel/linux/files/0860-drm-amd-dal-Use-native-strncmp-directly.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From a942385866ff99840e17365d22e2f84b7f650e2e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 14:43:22 -0500
-Subject: [PATCH 0860/1110] drm/amd/dal: Use native strncmp directly
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 5 -----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c          | 2 +-
- drivers/gpu/drm/amd/dal/dc/dm_services.h               | 2 --
- 3 files changed, 1 insertion(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index 7bab44a..30fc871 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -40,11 +40,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count)
--{
--	return strncmp(p1, p2, count);
--}
--
- void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
- {
- 	if (milliseconds >= 20)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index 22017ff..2922453 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -373,7 +373,7 @@ static uint32_t defer_delay_converter_wa(
- 
- 	if (dal_ddc_service_get_dp_receiver_id_info(ddc, &dp_rec_info) &&
- 		(dp_rec_info.branch_id == DP_BRANCH_DEVICE_ID_4) &&
--		!dm_strncmp(dp_rec_info.branch_name,
-+		!strncmp(dp_rec_info.branch_name,
- 			DP_DVI_CONVERTER_ID_4,
- 			sizeof(dp_rec_info.branch_name)))
- 		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 3862682..2d44e92 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -44,8 +44,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--int32_t dm_strncmp(const char *p1, const char *p2, uint32_t count);
--
- irq_handler_idx dm_register_interrupt(
- 	struct dc_context *ctx,
- 	struct dc_interrupt_params *int_params,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0861-drm-amd-dal-simplify-clock-sources-allocation.patch b/common/recipes-kernel/linux/files/0861-drm-amd-dal-simplify-clock-sources-allocation.patch
deleted file mode 100644
index 009490b3..00000000
--- a/common/recipes-kernel/linux/files/0861-drm-amd-dal-simplify-clock-sources-allocation.patch
+++ /dev/null
@@ -1,704 +0,0 @@
-From 115c06efef095c72ba9fa30ebde9ab9418b59b8a Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 25 Feb 2016 06:25:10 -0500
-Subject: [PATCH 0861/1110] drm/amd/dal: simplify clock sources allocation
-
-Separate DP clock source from regular clock sources
-and so simplify DP clock source access
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 74 ++++--------------
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 49 ++++++++----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 82 ++++++++------------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  5 ++
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 68 ++++++++--------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 90 +++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  6 ++
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  3 +
- 8 files changed, 174 insertions(+), 203 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index e4ea886..619e910 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1085,63 +1085,6 @@ static enum dc_link_rate get_max_link_rate(struct core_link *link)
- 	return max_link_rate;
- }
- 
--static enum clock_source_id get_clock_source_id_for_link_training(
--	struct core_link *link)
--{
--	bool result;
--	struct dc_sink_init_data init_params = {0};
--	struct dc_sink *sink;
--	struct dc_stream *stream;
--	struct dc_target *target;
--	struct validate_context *context;
--	struct dc_validation_set set;
--	enum clock_source_id id = CLOCK_SOURCE_ID_UNDEFINED;
--
--	init_params.link = &link->public;
--	init_params.sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
--	sink = dc_sink_create(&init_params);
--
--	if (!sink)
--		goto fail_sink;
--
--	stream = dc_create_stream_for_sink(sink);
--
--	if (!stream)
--		goto fail_stream;
--
--	target = dc_create_target_for_streams(&stream, 1);
--
--	if (!target)
--		goto fail_target;
--
--	set.surface_count = 0;
--	set.target = target;
--
--	context = dm_alloc(sizeof(struct validate_context));
--
--	if (!context)
--		goto fail_context;
--
--	result = link->dc->res_pool.funcs->validate_with_context(
--		link->dc,
--		&set,
--		1,
--		context);
--
--	if (result)
--		id = context->res_ctx.pipe_ctx[0].clock_source->id;
--
--	dm_free(context);
--fail_context:
--	dc_target_release(target);
--fail_target:
--	dc_stream_release(stream);
--fail_stream:
--	dc_sink_release(sink);
--fail_sink:
--	return id;
--}
--
- bool dp_hbr_verify_link_cap(
- 	struct core_link *link,
- 	struct dc_link_settings *known_limit_link_setting)
-@@ -1152,11 +1095,12 @@ bool dp_hbr_verify_link_cap(
- 	const struct dc_link_settings *cur;
- 	bool skip_video_pattern;
- 	uint32_t i;
-+	struct clock_source *dp_cs;
-+	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
- 
- 	success = false;
- 	skip_link_training = false;
- 
--	/* TODO confirm this is correct for cz */
- 	max_link_cap.lane_count = LANE_COUNT_FOUR;
- 	max_link_cap.link_rate = get_max_link_rate(link);
- 	max_link_cap.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
-@@ -1169,6 +1113,18 @@ bool dp_hbr_verify_link_cap(
- 	/* disable PHY done possible by BIOS, will be done by driver itself */
- 	dp_disable_link_phy(link, link->public.connector_signal);
- 
-+	dp_cs = link->dc->res_pool.dp_clock_source;
-+
-+	if (dp_cs)
-+		dp_cs_id = dp_cs->id;
-+	else {
-+		/*
-+		 * dp clock source is not initialized for some reason.
-+		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
-+		 */
-+		ASSERT(dp_cs);
-+	}
-+
- 	for (i = 0; i < get_link_training_fallback_table_len(link) &&
- 		!success; i++) {
- 		cur = get_link_training_fallback_table(link, i);
-@@ -1188,7 +1144,7 @@ bool dp_hbr_verify_link_cap(
- 		dp_enable_link_phy(
- 				link,
- 				link->public.connector_signal,
--				get_clock_source_id_for_link_training(link),
-+				dp_cs_id,
- 				cur);
- 
- 		if (skip_link_training)
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index fcb9a0f..f5bfaf3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -72,14 +72,23 @@ void unreference_clock_source(
- {
- 	int i;
- 	for (i = 0; i < res_ctx->pool.clk_src_count; i++) {
--		if (res_ctx->pool.clock_sources[i] == clock_source) {
--			res_ctx->clock_source_ref_count[i]--;
-+		if (res_ctx->pool.clock_sources[i] != clock_source)
-+			continue;
-+
-+		res_ctx->clock_source_ref_count[i]--;
- 
- 		if (res_ctx->clock_source_ref_count[i] == 0)
- 			clock_source->funcs->cs_power_down(clock_source);
--		}
-+
-+		break;
- 	}
- 
-+	if (res_ctx->pool.dp_clock_source == clock_source) {
-+		res_ctx->dp_clock_source_ref_count--;
-+
-+		if (res_ctx->dp_clock_source_ref_count == 0)
-+			clock_source->funcs->cs_power_down(clock_source);
-+	}
- }
- 
- void reference_clock_source(
-@@ -88,10 +97,15 @@ void reference_clock_source(
- {
- 	int i;
- 	for (i = 0; i < res_ctx->pool.clk_src_count; i++) {
--		if (res_ctx->pool.clock_sources[i] == clock_source) {
--			res_ctx->clock_source_ref_count[i]++;
--		}
-+		if (res_ctx->pool.clock_sources[i] != clock_source)
-+			continue;
-+
-+		res_ctx->clock_source_ref_count[i]++;
-+		break;
- 	}
-+
-+	if (res_ctx->pool.dp_clock_source == clock_source)
-+		res_ctx->dp_clock_source_ref_count++;
- }
- 
- bool is_same_timing(
-@@ -109,21 +123,17 @@ static bool is_sharable_clk_src(
- 	enum dce_version dce_ver = dal_adapter_service_get_dce_version(
- 		pipe->stream->sink->link->adapter_srv);
- 
--	/* Currently no clocks are shared for DCE 10 until VBIOS behaviour
-+	/* Currently no clocks are shared for DCE 10 until VBIOS behavior
- 	 * is verified for this use case
- 	 */
--	if (dce_ver == DCE_VERSION_10_0 && !dc_is_dp_signal(pipe->signal))
-+	if (dce_ver == DCE_VERSION_10_0)
- 		return false;
- #endif
- 
- 	if (pipe_with_clk_src->clock_source == NULL)
- 		return false;
- 
--	if (dc_is_dp_signal(pipe->signal) &&
--		dc_is_dp_signal(pipe_with_clk_src->signal))
--		return true;
--
--	if (pipe->signal != pipe_with_clk_src->signal)
-+	if (dc_is_dp_signal(pipe_with_clk_src->signal))
- 		return false;
- 
- 	if(!is_same_timing(
-@@ -1275,6 +1285,19 @@ void val_ctx_copy_construct(
- 	}
- }
- 
-+struct clock_source *dc_resource_find_first_free_pll(
-+		struct resource_context *res_ctx)
-+{
-+	int i;
-+
-+	for (i = 0; i < res_ctx->pool.clk_src_count; ++i) {
-+		if (res_ctx->clock_source_ref_count[i] == 0)
-+			return res_ctx->pool.clock_sources[i];
-+	}
-+
-+	return NULL;
-+}
-+
- void build_info_frame(struct pipe_ctx *pipe_ctx)
- {
- 	enum signal_type signal = SIGNAL_TYPE_NONE;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 6260751..642c82a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -59,10 +59,9 @@
- #endif
- 
- enum dce100_clk_src_array_id {
--	DCE100_CLK_SRC_PLL0 = 0,
--	DCE100_CLK_SRC_PLL1,
--	DCE100_CLK_SRC_PLL2,
--	DCE100_CLK_SRC_EXT,
-+	DCE100_CLK_SRC0 = 0,
-+	DCE100_CLK_SRC1,
-+	DCE100_CLK_SRC2,
- 
- 	DCE100_CLK_SRC_TOTAL
- };
-@@ -560,6 +559,9 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 			dce100_clock_source_destroy(&pool->clock_sources[i]);
- 	}
- 
-+	if (pool->dp_clock_source != NULL)
-+		dce100_clock_source_destroy(&pool->dp_clock_source);
-+
- 	for (i = 0; i < pool->audio_count; i++)	{
- 		if (pool->audios[i] != NULL)
- 			dal_audio_destroy(&pool->audios[i]);
-@@ -578,19 +580,6 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 		dal_adapter_service_destroy(&pool->adapter_srv);
- }
- 
--static struct clock_source *find_first_free_pll(
--		struct resource_context *res_ctx)
--{
--	int i;
--
--	for (i = 0; i < DCE100_CLK_SRC_EXT; ++i) {
--		if (res_ctx->clock_source_ref_count[i] == 0)
--			return res_ctx->pool.clock_sources[i];
--	}
--
--	return NULL;
--}
--
- static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
- {
- 	switch (crtc_id) {
-@@ -838,17 +827,18 @@ static enum dc_status map_clock_resources(
- 				 */
- 				if (dc_is_dp_signal(pipe_ctx->signal)
- 					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source = context->res_ctx.pool.clock_sources[DCE100_CLK_SRC_EXT];
--
--				if (pipe_ctx->clock_source == NULL)
-+					pipe_ctx->clock_source =
-+						context->res_ctx.pool.dp_clock_source;
-+				else {
- 					pipe_ctx->clock_source =
- 						find_used_clk_src_for_sharing(
- 							&context->res_ctx,
- 							pipe_ctx);
- 
--				if (pipe_ctx->clock_source == NULL)
--					pipe_ctx->clock_source =
--						find_first_free_pll(&context->res_ctx);
-+					if (pipe_ctx->clock_source == NULL)
-+						pipe_ctx->clock_source =
-+							dc_resource_find_first_free_pll(&context->res_ctx);
-+				}
- 
- 				if (pipe_ctx->clock_source == NULL)
- 					return DC_NO_CLOCK_SOURCE_RESOURCE;
-@@ -946,6 +936,7 @@ bool dce100_construct_resource_pool(
- 	struct dc_context *ctx = dc->ctx;
- 	struct firmware_info info;
- 	struct dc_bios *bp;
-+	int regular_pll_offset = 0;
- 
- 	pool->adapter_srv = as;
- 	pool->funcs = &dce100_res_pool_funcs;
-@@ -959,38 +950,33 @@ bool dce100_construct_resource_pool(
- 
- 	bp = dal_adapter_service_get_bios_parser(as);
- 
--	pool->clock_sources[DCE100_CLK_SRC_PLL0] =
--		dce100_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL0,
--			&dce100_clk_src_reg_offsets[0]);
--
--	pool->clock_sources[DCE100_CLK_SRC_PLL1] =
--		dce100_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL1,
--			&dce100_clk_src_reg_offsets[1]);
--
--	pool->clock_sources[DCE100_CLK_SRC_PLL2] =
--		dce100_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL2,
--			&dce100_clk_src_reg_offsets[2]);
--
- 	if (dal_adapter_service_get_firmware_info(as, &info) &&
- 		info.external_clock_source_frequency_for_dp != 0) {
--		pool->clock_sources[DCE100_CLK_SRC_EXT] =
-+		pool->dp_clock_source =
- 			dce100_clock_source_create(
- 				ctx,
- 				bp,
- 				CLOCK_SOURCE_ID_EXTERNAL,
- 				NULL);
--		pool->clk_src_count = DCE100_CLK_SRC_TOTAL;
--	} else
--		pool->clk_src_count = DCE100_CLK_SRC_TOTAL - 1;
-+	} else {
-+		pool->dp_clock_source =
-+			dce100_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_PLL0,
-+				&dce100_clk_src_reg_offsets[0]);
-+		regular_pll_offset = 1;
-+	}
-+
-+	pool->clk_src_count = DCE100_CLK_SRC_TOTAL - regular_pll_offset;
-+
-+	for (i = 0; i < pool->clk_src_count; ++i, ++regular_pll_offset)
-+		pool->clock_sources[i] =
-+			dce100_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_PLL0 + regular_pll_offset,
-+				&dce100_clk_src_reg_offsets[regular_pll_offset]);
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index de727fb..4e4ada8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -925,6 +925,10 @@ static void power_down_clock_sources(struct core_dc *dc)
- {
- 	int i;
- 
-+	if (dc->res_pool.dp_clock_source->funcs->cs_power_down(
-+		dc->res_pool.dp_clock_source) == false)
-+		dm_error("Failed to power down pll! (dp clk src)\n");
-+
- 	for (i = 0; i < dc->res_pool.clk_src_count; i++) {
- 		if (dc->res_pool.clock_sources[i]->funcs->cs_power_down(
- 				dc->res_pool.clock_sources[i]) == false)
-@@ -1429,6 +1433,7 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_
- 					PIPE_LOCK_CONTROL_SURFACE,
- 					false);
- 
-+
- 		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false)) {
- 			dm_error("DC: failed to unblank crtc!\n");
- 			BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 2ebd398..1a315c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -60,9 +60,8 @@
- #endif
- 
- enum dce110_clk_src_array_id {
--	DCE110_CLK_SRC_PLL0 = 0,
--	DCE110_CLK_SRC_PLL1,
--	DCE110_CLK_SRC_EXT,
-+	DCE110_CLK_SRC0 = 0,
-+	DCE110_CLK_SRC1,
- 
- 	DCE110_CLK_SRC_TOTAL
- };
-@@ -508,6 +507,9 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 		}
- 	}
- 
-+	if (pool->dp_clock_source != NULL)
-+		dce110_clock_source_destroy(&pool->dp_clock_source);
-+
- 	for (i = 0; i < pool->audio_count; i++)	{
- 		if (pool->audios[i] != NULL) {
- 			dal_audio_destroy(&pool->audios[i]);
-@@ -530,19 +532,6 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 	}
- }
- 
--static struct clock_source *find_first_free_pll(
--		struct resource_context *res_ctx)
--{
--	if (res_ctx->clock_source_ref_count[DCE110_CLK_SRC_PLL0] == 0) {
--		return res_ctx->pool.clock_sources[DCE110_CLK_SRC_PLL0];
--	}
--	if (res_ctx->clock_source_ref_count[DCE110_CLK_SRC_PLL1] == 0) {
--		return res_ctx->pool.clock_sources[DCE110_CLK_SRC_PLL1];
--	}
--
--	return 0;
--}
--
- static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
- {
- 	switch (crtc_id) {
-@@ -955,15 +944,17 @@ static enum dc_status map_clock_resources(
- 
- 				if (dc_is_dp_signal(pipe_ctx->signal)
- 					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source = context->res_ctx.
--						pool.clock_sources[DCE110_CLK_SRC_EXT];
--				else
-+					pipe_ctx->clock_source =
-+						context->res_ctx.pool.dp_clock_source;
-+				else {
- 					pipe_ctx->clock_source =
- 						find_used_clk_src_for_sharing(
- 							&context->res_ctx, pipe_ctx);
--				if (pipe_ctx->clock_source == NULL)
--					pipe_ctx->clock_source =
--						find_first_free_pll(&context->res_ctx);
-+
-+					if (pipe_ctx->clock_source == NULL)
-+						pipe_ctx->clock_source =
-+							dc_resource_find_first_free_pll(&context->res_ctx);
-+				}
- 
- 				if (pipe_ctx->clock_source == NULL)
- 					return DC_NO_CLOCK_SOURCE_RESOURCE;
-@@ -1097,32 +1088,37 @@ bool dce110_construct_resource_pool(
- 
- 	bp = dal_adapter_service_get_bios_parser(as);
- 
--	pool->clock_sources[DCE110_CLK_SRC_PLL0] =
-+	if (dal_adapter_service_get_firmware_info(as, &info) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->dp_clock_source =
-+			dce110_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_EXTERNAL,
-+				NULL);
-+	} else {
-+		pool->dp_clock_source =
-+			dce110_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_PLL0,
-+				&dce110_clk_src_reg_offsets[0]);
-+	}
-+
-+	pool->clock_sources[DCE110_CLK_SRC0] =
- 		dce110_clock_source_create(
- 			ctx,
- 			bp,
- 			CLOCK_SOURCE_ID_PLL0,
- 			&dce110_clk_src_reg_offsets[0]);
- 
--	pool->clock_sources[DCE110_CLK_SRC_PLL1] =
-+	pool->clock_sources[DCE110_CLK_SRC1] =
- 		dce110_clock_source_create(
- 			ctx,
- 			bp,
- 			CLOCK_SOURCE_ID_PLL1,
- 			&dce110_clk_src_reg_offsets[1]);
- 
--	if (dal_adapter_service_get_firmware_info(as, &info) &&
--		info.external_clock_source_frequency_for_dp != 0) {
--		pool->clock_sources[DCE110_CLK_SRC_EXT] =
--			dce110_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_EXTERNAL,
--				NULL);
--		pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
--	} else
--		pool->clk_src_count = DCE110_CLK_SRC_TOTAL - 1;
--
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
- 			dm_error("DC: failed to create clock sources!\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 04f235a..e4f2bef 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -62,10 +62,9 @@
- #endif
- 
- enum dce80_clk_src_array_id {
--	DCE80_CLK_SRC_PLL0 = 0,
--	DCE80_CLK_SRC_PLL1,
--	DCE80_CLK_SRC_PLL2,
--	DCE80_CLK_SRC_EXT,
-+	DCE80_CLK_SRC0 = 0,
-+	DCE80_CLK_SRC1,
-+	DCE80_CLK_SRC2,
- 
- 	DCE80_CLK_SRC_TOTAL
- };
-@@ -518,6 +517,9 @@ void dce80_destruct_resource_pool(struct resource_pool *pool)
- 		}
- 	}
- 
-+	if (pool->dp_clock_source != NULL)
-+		dce80_clock_source_destroy(&pool->dp_clock_source);
-+
- 	for (i = 0; i < pool->audio_count; i++)	{
- 		if (pool->audios[i] != NULL) {
- 			dal_audio_destroy(&pool->audios[i]);
-@@ -540,22 +542,6 @@ void dce80_destruct_resource_pool(struct resource_pool *pool)
- 	}
- }
- 
--static struct clock_source *find_first_free_pll(
--		struct resource_context *res_ctx)
--{
--	if (res_ctx->clock_source_ref_count[DCE80_CLK_SRC_PLL0] == 0) {
--		return res_ctx->pool.clock_sources[DCE80_CLK_SRC_PLL0];
--	}
--	if (res_ctx->clock_source_ref_count[DCE80_CLK_SRC_PLL1] == 0) {
--		return res_ctx->pool.clock_sources[DCE80_CLK_SRC_PLL1];
--	}
--	if (res_ctx->clock_source_ref_count[DCE80_CLK_SRC_PLL2] == 0) {
--		return res_ctx->pool.clock_sources[DCE80_CLK_SRC_PLL2];
--	}
--
--	return 0;
--}
--
- static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
- {
- 	switch (crtc_id) {
-@@ -953,15 +939,16 @@ static enum dc_status map_clock_resources(
- 
- 				if (dc_is_dp_signal(pipe_ctx->signal)
- 					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source = context->res_ctx.
--							pool.clock_sources[DCE80_CLK_SRC_EXT];
--				else
-+					pipe_ctx->clock_source = context->res_ctx.pool.dp_clock_source;
-+				else {
- 					pipe_ctx->clock_source =
- 						find_used_clk_src_for_sharing(
- 							&context->res_ctx, pipe_ctx);
--				if (pipe_ctx->clock_source == NULL)
--					pipe_ctx->clock_source =
--							find_first_free_pll(&context->res_ctx);
-+
-+					if (pipe_ctx->clock_source == NULL)
-+						pipe_ctx->clock_source =
-+							dc_resource_find_first_free_pll(&context->res_ctx);
-+				}
- 
- 				if (pipe_ctx->clock_source == NULL)
- 					return DC_NO_CLOCK_SOURCE_RESOURCE;
-@@ -1059,6 +1046,7 @@ bool dce80_construct_resource_pool(
- 	struct dc_context *ctx = dc->ctx;
- 	struct firmware_info info;
- 	struct dc_bios *bp;
-+	int regular_pll_offset = 0;
- 
- 	pool->adapter_srv = as;
- 	pool->funcs = &dce80_res_pool_funcs;
-@@ -1072,40 +1060,48 @@ bool dce80_construct_resource_pool(
- 
- 	bp = dal_adapter_service_get_bios_parser(as);
- 
--	pool->clock_sources[DCE80_CLK_SRC_PLL0] =
--		dce80_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL0,
--			&dce80_clk_src_reg_offsets[0]);
-+	if (dal_adapter_service_get_firmware_info(as, &info) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->dp_clock_source =
-+			dce80_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_EXTERNAL,
-+				NULL);
-+	} else {
-+		pool->dp_clock_source =
-+			dce80_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_PLL0,
-+				&dce80_clk_src_reg_offsets[0]);
-+		regular_pll_offset = 1;
-+	}
-+
-+	pool->clk_src_count = DCE80_CLK_SRC_TOTAL - regular_pll_offset;
-+
-+	for (i = 0; i < DCE80_CLK_SRC_TOTAL; ++i, ++regular_pll_offset)
-+		pool->clock_sources[DCE80_CLK_SRC0 + i] =
-+			dce80_clock_source_create(
-+				ctx,
-+				bp,
-+				CLOCK_SOURCE_ID_PLL0 + regular_pll_offset,
-+				&dce80_clk_src_reg_offsets[regular_pll_offset]);
- 
--	pool->clock_sources[DCE80_CLK_SRC_PLL1] =
-+	pool->clock_sources[DCE80_CLK_SRC1] =
- 		dce80_clock_source_create(
- 			ctx,
- 			bp,
- 			CLOCK_SOURCE_ID_PLL1,
- 			&dce80_clk_src_reg_offsets[1]);
- 
--	pool->clock_sources[DCE80_CLK_SRC_PLL2] =
-+	pool->clock_sources[DCE80_CLK_SRC2] =
- 		dce80_clock_source_create(
- 			ctx,
- 			bp,
- 			CLOCK_SOURCE_ID_PLL2,
- 			&dce80_clk_src_reg_offsets[2]);
- 
--	if (dal_adapter_service_get_firmware_info(as, &info) &&
--		info.external_clock_source_frequency_for_dp != 0) {
--		pool->clock_sources[DCE80_CLK_SRC_EXT] =
--			dce80_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_EXTERNAL,
--				NULL);
--
--		pool->clk_src_count = DCE80_CLK_SRC_TOTAL;
--	} else
--		pool->clk_src_count = DCE80_CLK_SRC_TOTAL - 1;
--
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
- 			dm_error("DC: failed to create clock sources!\n");
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index be3a693..02dddc4 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -265,6 +265,11 @@ struct resource_pool {
- 
- 	union supported_stream_engines stream_engines;
- 
-+	/*
-+	 * reserved clock source for DP
-+	 */
-+	struct clock_source *dp_clock_source;
-+
- 	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
- 	uint8_t clk_src_count;
- 
-@@ -327,6 +332,7 @@ struct resource_context {
- 	bool is_stream_enc_acquired[MAX_PIPES * 2];
- 	bool is_audio_acquired[MAX_PIPES];
- 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
-+	uint8_t dp_clock_source_ref_count;
-  };
- 
- struct target_flags {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index e6a386c..6991c3e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -61,6 +61,9 @@ struct clock_source *find_used_clk_src_for_sharing(
- 	struct resource_context *res_ctx,
- 	struct pipe_ctx *pipe_ctx);
- 
-+struct clock_source *dc_resource_find_first_free_pll(
-+		struct resource_context *res_ctx);
-+
- bool attach_surfaces_to_context(
- 		struct dc_surface *surfaces[],
- 		uint8_t surface_count,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0862-drm-amd-dal-fix-HW-I2C-channel-status.patch b/common/recipes-kernel/linux/files/0862-drm-amd-dal-fix-HW-I2C-channel-status.patch
deleted file mode 100644
index 9e04042d..00000000
--- a/common/recipes-kernel/linux/files/0862-drm-amd-dal-fix-HW-I2C-channel-status.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From d2e4c6dfe706e0608cc6fedbd312fe5120bf8986 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 25 Feb 2016 06:01:25 -0500
-Subject: [PATCH 0862/1110] drm/amd/dal: fix HW I2C channel status
-
-Original code was incorrectly ported from DAL2
-Zero I2C status value does not mean an error
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 7 +++++--
- drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c   | 7 +++++--
- 2 files changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-index b43a431..a27dbe7 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
-@@ -748,8 +748,11 @@ static enum i2c_channel_operation_result get_channel_status(
- 	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
- 		return I2C_CHANNEL_OPERATION_SUCCEEDED;
- 
--	/* in DAL2, I2C_RESULT_OK was returned */
--	return I2C_CHANNEL_OPERATION_NOT_STARTED;
-+	/*
-+	 * this is the case when HW used for communication, I2C_SW_STATUS
-+	 * could be zero
-+	 */
-+	return I2C_CHANNEL_OPERATION_SUCCEEDED;
- }
- 
- static uint8_t get_hw_buffer_available_size(
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-index bce2b94..bc94433 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2c_hw_engine_dce80.c
-@@ -742,8 +742,11 @@ static enum i2c_channel_operation_result get_channel_status(
- 	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
- 		return I2C_CHANNEL_OPERATION_SUCCEEDED;
- 
--	/* in DAL2, I2C_RESULT_OK was returned */
--	return I2C_CHANNEL_OPERATION_NOT_STARTED;
-+	/*
-+	 * this is the case when HW used for communication, I2C_SW_STATUS
-+	 * could be zero
-+	 */
-+	return I2C_CHANNEL_OPERATION_SUCCEEDED;
- }
- 
- static uint8_t get_hw_buffer_available_size(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0863-drm-amd-dal-Remove-delay_in_nanoseconds.patch b/common/recipes-kernel/linux/files/0863-drm-amd-dal-Remove-delay_in_nanoseconds.patch
deleted file mode 100644
index 4d6d2a56..00000000
--- a/common/recipes-kernel/linux/files/0863-drm-amd-dal-Remove-delay_in_nanoseconds.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 3122449db2eb102df4205dd0ec3d052eb23f2d31 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 15:43:04 -0500
-Subject: [PATCH 0863/1110] drm/amd/dal: Remove delay_in_nanoseconds
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index 30fc871..d0a17af 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -48,11 +48,6 @@ void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
- 		usleep_range(milliseconds*1000, milliseconds*1000+1);
- }
- 
--void dal_delay_in_nanoseconds(uint32_t nanoseconds)
--{
--	ndelay(nanoseconds);
--}
--
- void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds)
- {
- 	udelay(microseconds);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0864-drm-amd-dal-Create-struct-dc-as-public-version-of-dc.patch b/common/recipes-kernel/linux/files/0864-drm-amd-dal-Create-struct-dc-as-public-version-of-dc.patch
deleted file mode 100644
index 7b95d2c3..00000000
--- a/common/recipes-kernel/linux/files/0864-drm-amd-dal-Create-struct-dc-as-public-version-of-dc.patch
+++ /dev/null
@@ -1,1212 +0,0 @@
-From 43f8163624df6de327571c0d5cd6a4cbd517058c Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Sat, 27 Feb 2016 16:31:53 -0500
-Subject: [PATCH 0864/1110] drm/amd/dal: Create struct dc as public version of
- dc handle rather than forward declare pointer to struct core_dc
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |  17 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h      |   2 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |   2 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |   6 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 235 +++++++++++----------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  16 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c       |  11 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  19 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  60 +++---
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |   3 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_dc.h           |   4 +
- 11 files changed, 205 insertions(+), 170 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index ed2cdc5..2f2077e1 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -162,7 +162,7 @@ static void dm_pflip_high_irq(void *interrupt_params)
- 	struct common_irq_params *irq_params = interrupt_params;
- 	struct amdgpu_device *adev = irq_params->adev;
- 	unsigned long flags;
--	const struct core_dc *dc = irq_params->adev->dm.dc;
-+	const struct dc *dc = irq_params->adev->dm.dc;
- 	const struct dc_target *dc_target =
- 			dc_get_target_on_irq_source(dc, irq_params->irq_src);
- 
-@@ -204,7 +204,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
- {
- 	struct common_irq_params *irq_params = interrupt_params;
- 	struct amdgpu_device *adev = irq_params->adev;
--	const struct core_dc *dc = irq_params->adev->dm.dc;
-+	const struct dc *dc = irq_params->adev->dm.dc;
- 	const struct dc_target *dc_target =
- 			dc_get_target_on_irq_source(dc, irq_params->irq_src);
- 	uint8_t crtc_index = 0;
-@@ -759,14 +759,11 @@ static void register_hpd_handlers(struct amdgpu_device *adev)
- /* Register IRQ sources and initialize IRQ callbacks */
- static int dce110_register_irq_handlers(struct amdgpu_device *adev)
- {
--	struct core_dc *dc = adev->dm.dc;
-+	struct dc *dc = adev->dm.dc;
- 	struct common_irq_params *c_irq_params;
- 	struct dc_interrupt_params int_params = {0};
- 	int r;
- 	int i;
--	struct dc_caps caps = { 0 };
--
--	dc_get_caps(dc, &caps);
- 
- 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
- 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-@@ -928,18 +925,16 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 	struct amdgpu_connector *aconnector;
- 	struct amdgpu_encoder *aencoder;
- 	struct amdgpu_crtc *acrtc;
--	struct dc_caps caps = { 0 };
- 	uint32_t link_cnt;
- 
--	dc_get_caps(dm->dc, &caps);
--	link_cnt = caps.max_links;
-+	link_cnt = dm->dc->caps.max_links;
- 
- 	if (amdgpu_dm_mode_config_init(dm->adev)) {
- 		DRM_ERROR("DM: Failed to initialize mode config\n");
- 		return -1;
- 	}
- 
--	for (i = 0; i < caps.max_targets; i++) {
-+	for (i = 0; i < dm->dc->caps.max_targets; i++) {
- 		acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
- 		if (!acrtc)
- 			goto fail;
-@@ -954,7 +949,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 		}
- 	}
- 
--	dm->display_indexes_num = caps.max_targets;
-+	dm->display_indexes_num = dm->dc->caps.max_targets;
- 
- 	/* loops over all connectors on the board */
- 	for (i = 0; i < link_cnt; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 4f3bf97..94c20d5 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -74,7 +74,7 @@ struct irq_list_head {
- 
- struct amdgpu_display_manager {
- 	struct dal *dal;
--	struct core_dc *dc;
-+	struct dc *dc;
- 	void *cgs_device;
- 	/* lock to be used when DAL is called from SYNC IRQ context */
- 	spinlock_t dal_lock;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index ed0b9d7..2ab2703 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -80,7 +80,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 	struct pci_dev *pdev = to_pci_dev(aux->dev);
- 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
- 	struct amdgpu_device *adev = drm_dev->dev_private;
--	struct core_dc *dc = adev->dm.dc;
-+	struct dc *dc = adev->dm.dc;
- 	bool res;
- 
- 	switch (msg->request) {
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 1c767f3..a8a2e10 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -622,7 +622,7 @@ static void calculate_stream_scaling_settings(
- }
- 
- static void dm_dc_surface_commit(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		struct drm_crtc *crtc,
- 		struct dm_connector_state *dm_state)
- {
-@@ -1873,7 +1873,7 @@ int amdgpu_dm_connector_init(
- {
- 	int res = 0;
- 	int connector_type;
--	struct core_dc *dc = dm->dc;
-+	struct dc *dc = dm->dc;
- 	const struct dc_link *link = dc_get_link_at_index(dc, link_index);
- 	struct amdgpu_i2c_adapter *i2c;
- 
-@@ -2488,7 +2488,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 	struct dc_validation_set set[MAX_TARGET_NUM] = {{ 0 }};
- 	struct dc_target *new_targets[MAX_TARGET_NUM] = { 0 };
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct core_dc *dc = adev->dm.dc;
-+	struct dc *dc = adev->dm.dc;
- 	bool need_to_validate = false;
- 
- 	ret = drm_atomic_helper_check(dev, state);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 9ae1bc7..339c82f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -304,7 +304,6 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 	struct adapter_service *as;
- 	struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
- 
--
- 	if (!dc_ctx) {
- 		dm_error("%s: failed to create ctx\n", __func__);
- 		goto ctx_fail;
-@@ -312,7 +311,7 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 
- 	dc_ctx->cgs_device = init_params->cgs_device;
- 	dc_ctx->driver_context = init_params->driver;
--	dc_ctx->dc = dc;
-+	dc_ctx->dc = &dc->public;
- 
- 	/* Create logger */
- 	logger = dal_logger_create(dc_ctx);
-@@ -409,7 +408,8 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz )
- */
- static int8_t acquire_first_free_underlay(
- 		struct resource_context *res_ctx,
--		struct core_stream *stream)
-+		struct core_stream *stream,
-+		struct core_dc* core_dc)
- {
- 	if (!res_ctx->pipe_ctx[DCE110_UNDERLAY_IDX].stream) {
- 		struct dc_bios *dcb;
-@@ -426,8 +426,8 @@ static int8_t acquire_first_free_underlay(
- 		dcb = dal_adapter_service_get_bios_parser(
- 						res_ctx->pool.adapter_srv);
- 
--		stream->ctx->dc->hwss.enable_display_power_gating(
--			stream->ctx->dc->ctx,
-+		core_dc->hwss.enable_display_power_gating(
-+			core_dc->ctx,
- 			DCE110_UNDERLAY_IDX,
- 			dcb, PIPE_GATING_CONTROL_DISABLE);
- 
-@@ -454,7 +454,7 @@ static int8_t acquire_first_free_underlay(
-  * Public functions
-  ******************************************************************************/
- 
--struct core_dc *dc_create(const struct dc_init_data *init_params)
-+struct dc *dc_create(const struct dc_init_data *init_params)
-  {
- 	struct dc_context ctx = {
- 		.driver_context = init_params->driver,
-@@ -465,14 +465,18 @@ struct core_dc *dc_create(const struct dc_init_data *init_params)
- 	if (NULL == dc)
- 		goto alloc_fail;
- 
--	ctx.dc = dc;
-+	ctx.dc = &dc->public;
- 	if (false == construct(dc, init_params))
- 		goto construct_fail;
- 
- 	/*TODO: separate HW and SW initialization*/
- 	init_hw(dc);
- 
--	return dc;
-+	dc->public.caps.max_targets = dc->res_pool.pipe_count;
-+	dc->public.caps.max_links = dc->link_count;
-+	dc->public.caps.max_audios = dc->res_pool.audio_count;
-+
-+	return &dc->public;
- 
- construct_fail:
- 	dm_free(dc);
-@@ -481,18 +485,20 @@ alloc_fail:
- 	return NULL;
- }
- 
--void dc_destroy(struct core_dc **dc)
-+void dc_destroy(struct dc **dc)
- {
--	destruct(*dc);
--	dm_free(*dc);
-+	struct core_dc *core_dc = DC_TO_CORE(*dc);
-+	destruct(core_dc);
-+	dm_free(core_dc);
- 	*dc = NULL;
- }
- 
- bool dc_validate_resources(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	struct validate_context *context;
- 
-@@ -500,8 +506,8 @@ bool dc_validate_resources(
- 	if(context == NULL)
- 		goto context_alloc_fail;
- 
--	result = dc->res_pool.funcs->validate_with_context(
--						dc, set, set_count, context);
-+	result = core_dc->res_pool.funcs->validate_with_context(
-+						core_dc, set, set_count, context);
- 
- 	val_ctx_destruct(context);
- 	dm_free(context);
-@@ -512,7 +518,7 @@ context_alloc_fail:
- }
- 
- static void program_timing_sync(
--		struct dc_context *dc_ctx,
-+		struct core_dc *core_dc,
- 		struct validate_context *ctx)
- {
- 	uint8_t i;
-@@ -552,7 +558,7 @@ static void program_timing_sync(
- 	}
- 
- 	if(group_size > 1) {
--		dc_ctx->dc->hwss.enable_timing_synchronization(dc_ctx, group_size, tg_set);
-+		core_dc->hwss.enable_timing_synchronization(core_dc->ctx, group_size, tg_set);
- 	}
- }
- 
-@@ -574,12 +580,11 @@ static bool targets_changed(
- 	return false;
- }
- 
--static void target_enable_memory_requests(struct dc_target *dc_target)
-+static void target_enable_memory_requests(struct dc_target *dc_target,
-+		struct resource_context *res_ctx)
- {
- 	uint8_t i, j;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	struct resource_context *res_ctx =
--		&target->ctx->dc->current_context.res_ctx;
- 
- 	for (i = 0; i < target->public.stream_count; i++) {
- 		for (j = 0; j < MAX_PIPES; j++) {
-@@ -597,12 +602,11 @@ static void target_enable_memory_requests(struct dc_target *dc_target)
- 	}
- }
- 
--static void target_disable_memory_requests(struct dc_target *dc_target)
-+static void target_disable_memory_requests(struct dc_target *dc_target,
-+		struct resource_context *res_ctx)
- {
- 	uint8_t i, j;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
--	struct resource_context *res_ctx =
--		&target->ctx->dc->current_context.res_ctx;
- 
- 	for (i = 0; i < target->public.stream_count; i++) {
- 		for (j = 0; j < MAX_PIPES; j++) {
-@@ -621,19 +625,20 @@ static void target_disable_memory_requests(struct dc_target *dc_target)
- }
- 
- bool dc_commit_targets(
--	struct core_dc *dc,
-+	struct dc *dc,
- 	struct dc_target *targets[],
- 	uint8_t target_count)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	struct validate_context *context;
- 	struct dc_validation_set set[4];
- 	uint8_t i;
- 
--	if (false == targets_changed(dc, targets, target_count))
-+	if (false == targets_changed(core_dc, targets, target_count))
- 		return DC_OK;
- 
--	dal_logger_write(dc->ctx->logger,
-+	dal_logger_write(core_dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC,
- 				"%s: %d targets\n",
-@@ -644,7 +649,7 @@ bool dc_commit_targets(
- 		struct dc_target *target = targets[i];
- 
- 		dc_target_log(target,
--				dc->ctx->logger,
-+				core_dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC);
- 
-@@ -657,46 +662,46 @@ bool dc_commit_targets(
- 	if (context == NULL)
- 		goto context_alloc_fail;
- 
--	result = dc->res_pool.funcs->validate_with_context(dc, set, target_count, context);
-+	result = core_dc->res_pool.funcs->validate_with_context(core_dc, set, target_count, context);
- 	if (result != DC_OK){
- 		BREAK_TO_DEBUGGER();
- 		val_ctx_destruct(context);
- 		goto fail;
- 	}
- 
--	pplib_apply_safe_state(dc);
-+	pplib_apply_safe_state(core_dc);
- 
- 	if (!dal_adapter_service_is_in_accelerated_mode(
--						dc->res_pool.adapter_srv)) {
--		dc->hwss.enable_accelerated_mode(dc);
-+						core_dc->res_pool.adapter_srv)) {
-+		core_dc->hwss.enable_accelerated_mode(core_dc);
- 	}
- 
--	for (i = 0; i < dc->current_context.target_count; i++) {
-+	for (i = 0; i < core_dc->current_context.target_count; i++) {
- 		/*TODO: optimize this to happen only when necessary*/
- 		target_disable_memory_requests(
--				&dc->current_context.targets[i]->public);
-+				&core_dc->current_context.targets[i]->public, &core_dc->current_context.res_ctx);
- 	}
- 
- 	if (result == DC_OK) {
--		dc->hwss.reset_hw_ctx(dc, context);
-+		core_dc->hwss.reset_hw_ctx(core_dc, context);
- 
- 		if (context->target_count > 0)
--			result = dc->hwss.apply_ctx_to_hw(dc, context);
-+			result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
- 	}
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		struct dc_target *dc_target = &context->targets[i]->public;
- 		if (context->target_status[i].surface_count > 0)
--			target_enable_memory_requests(dc_target);
-+			target_enable_memory_requests(dc_target, &core_dc->current_context.res_ctx);
- 	}
- 
--	program_timing_sync(dc->ctx, context);
-+	program_timing_sync(core_dc, context);
- 
--	pplib_apply_display_requirements(dc, context, &context->pp_display_cfg);
-+	pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg);
- 
--	val_ctx_destruct(&dc->current_context);
-+	val_ctx_destruct(&core_dc->current_context);
- 
--	dc->current_context = *context;
-+	core_dc->current_context = *context;
- 
- fail:
- 	dm_free(context);
-@@ -706,14 +711,16 @@ context_alloc_fail:
- }
- 
- bool dc_commit_surfaces_to_target(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		struct dc_surface *new_surfaces[],
- 		uint8_t new_surface_count,
- 		struct dc_target *dc_target)
- 
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
- 	int i, j;
--	uint32_t prev_disp_clk = dc->current_context.bw_results.dispclk_khz;
-+	uint32_t prev_disp_clk = core_dc->current_context.bw_results.dispclk_khz;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
- 	struct dc_target_status *target_status = NULL;
- 	struct validate_context *context;
-@@ -723,7 +730,7 @@ bool dc_commit_surfaces_to_target(
- 
- 	context = dm_alloc(sizeof(struct validate_context));
- 
--	val_ctx_copy_construct(&dc->current_context, context);
-+	val_ctx_copy_construct(&core_dc->current_context, context);
- 
- 	/* Cannot commit surface to a target that is not commited */
- 	for (i = 0; i < context->target_count; i++)
-@@ -733,7 +740,7 @@ bool dc_commit_surfaces_to_target(
- 	target_status = &context->target_status[i];
- 
- 	if (!dal_adapter_service_is_in_accelerated_mode(
--						dc->res_pool.adapter_srv)
-+						core_dc->res_pool.adapter_srv)
- 		|| i == context->target_count) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
-@@ -750,14 +757,14 @@ bool dc_commit_surfaces_to_target(
- 	/* TODO unhack mpo */
- 	if (new_surface_count == 2 && target_status->surface_count < 2) {
- 		acquire_first_free_underlay(&context->res_ctx,
--				DC_STREAM_TO_CORE(dc_target->streams[0]));
-+				DC_STREAM_TO_CORE(dc_target->streams[0]), core_dc);
- 		is_mpo_turning_on = true;
- 	} else if (new_surface_count < 2 && target_status->surface_count == 2) {
- 		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].stream = NULL;
- 		context->res_ctx.pipe_ctx[DCE110_UNDERLAY_IDX].surface = NULL;
- 	}
- 
--	dal_logger_write(dc->ctx->logger,
-+	dal_logger_write(core_dc->ctx->logger,
- 				LOG_MAJOR_INTERFACE_TRACE,
- 				LOG_MINOR_COMPONENT_DC,
- 				"%s: commit %d surfaces to target 0x%x\n",
-@@ -782,7 +789,7 @@ bool dc_commit_surfaces_to_target(
- 				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
- 		}
- 
--	if (dc->res_pool.funcs->validate_bandwidth(dc, context) != DC_OK) {
-+	if (core_dc->res_pool.funcs->validate_bandwidth(core_dc, context) != DC_OK) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
- 	}
-@@ -790,13 +797,13 @@ bool dc_commit_surfaces_to_target(
- 	if (prev_disp_clk < context->bw_results.dispclk_khz ||
- 		(is_mpo_turning_on &&
- 			prev_disp_clk == context->bw_results.dispclk_khz)) {
--		dc->hwss.program_bw(dc, context);
--		pplib_apply_display_requirements(dc, context,
-+		core_dc->hwss.program_bw(core_dc, context);
-+		pplib_apply_display_requirements(core_dc, context,
- 						&context->pp_display_cfg);
- 	}
- 
- 	if (current_enabled_surface_count > 0 && new_enabled_surface_count == 0)
--		target_disable_memory_requests(dc_target);
-+		target_disable_memory_requests(dc_target, &core_dc->current_context.res_ctx);
- 
- 	for (i = 0; i < new_surface_count; i++)
- 		for (j = 0; j < MAX_PIPES; j++) {
-@@ -811,7 +818,7 @@ bool dc_commit_surfaces_to_target(
- 					DC_SURFACE_TO_CORE(new_surfaces[i]))
- 				continue;
- 
--			dal_logger_write(dc->ctx->logger,
-+			dal_logger_write(core_dc->ctx->logger,
- 						LOG_MAJOR_INTERFACE_TRACE,
- 						LOG_MINOR_COMPONENT_DC,
- 						"Pipe:%d 0x%x: src: %d, %d, %d,"
-@@ -831,26 +838,26 @@ bool dc_commit_surfaces_to_target(
- 				gamma = DC_GAMMA_TO_CORE(
- 					surface->public.gamma_correction);
- 
--			dc->hwss.set_gamma_correction(
-+			core_dc->hwss.set_gamma_correction(
- 					pipe_ctx->ipp,
- 					pipe_ctx->opp,
- 					gamma, surface);
- 
--			dc->hwss.set_plane_config(
--				dc, pipe_ctx, &context->res_ctx);
-+			core_dc->hwss.set_plane_config(
-+				core_dc, pipe_ctx, &context->res_ctx);
- 		}
- 
--	dc->hwss.update_plane_addrs(dc, &context->res_ctx);
-+	core_dc->hwss.update_plane_addrs(core_dc, &context->res_ctx);
- 
- 	/* Lower display clock if necessary */
- 	if (prev_disp_clk > context->bw_results.dispclk_khz) {
--		dc->hwss.program_bw(dc, context);
--		pplib_apply_display_requirements(dc, context,
-+		core_dc->hwss.program_bw(core_dc, context);
-+		pplib_apply_display_requirements(core_dc, context,
- 						&context->pp_display_cfg);
- 	}
- 
--	val_ctx_destruct(&dc->current_context);
--	dc->current_context = *context;
-+	val_ctx_destruct(&(core_dc->current_context));
-+	core_dc->current_context = *context;
- 	dm_free(context);
- 	return true;
- 
-@@ -862,59 +869,61 @@ unexpected_fail:
- 	return false;
- }
- 
--uint8_t dc_get_current_target_count(const struct core_dc *dc)
-+uint8_t dc_get_current_target_count(const struct dc *dc)
- {
--	return dc->current_context.target_count;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return core_dc->current_context.target_count;
- }
- 
--struct dc_target *dc_get_target_at_index(const struct core_dc *dc, uint8_t i)
-+struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i)
- {
--	if (i < dc->current_context.target_count)
--		return &dc->current_context.targets[i]->public;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	if (i < core_dc->current_context.target_count)
-+		return &(core_dc->current_context.targets[i]->public);
- 	return NULL;
- }
- 
--const struct dc_link *dc_get_link_at_index(struct core_dc *dc, uint32_t link_index)
-+const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
- {
--	return &dc->links[link_index]->public;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return &core_dc->links[link_index]->public;
- }
- 
- const struct graphics_object_id dc_get_link_id_at_index(
--	struct core_dc *dc, uint32_t link_index)
-+	struct dc *dc, uint32_t link_index)
- {
--	return dc->links[link_index]->link_id;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return core_dc->links[link_index]->link_id;
- }
- 
- const struct ddc_service *dc_get_ddc_at_index(
--	struct core_dc *dc, uint32_t link_index)
-+	struct dc *dc, uint32_t link_index)
- {
--	return dc->links[link_index]->ddc;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return core_dc->links[link_index]->ddc;
- }
- 
- const enum dc_irq_source dc_get_hpd_irq_source_at_index(
--	struct core_dc *dc, uint32_t link_index)
-+	struct dc *dc, uint32_t link_index)
- {
--	return dc->links[link_index]->public.irq_source_hpd;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return core_dc->links[link_index]->public.irq_source_hpd;
- }
- 
--const struct audio **dc_get_audios(struct core_dc *dc)
-+const struct audio **dc_get_audios(struct dc *dc)
- {
--	return (const struct audio **)dc->res_pool.audios;
--}
--
--void dc_get_caps(const struct core_dc *dc, struct dc_caps *caps)
--{
--	caps->max_targets = dc->res_pool.pipe_count;
--	caps->max_links = dc->link_count;
--	caps->max_audios = dc->res_pool.audio_count;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return (const struct audio **)core_dc->res_pool.audios;
- }
- 
- void dc_flip_surface_addrs(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		const struct dc_surface *const surfaces[],
- 		struct dc_flip_addrs flip_addrs[],
- 		uint32_t count)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
- 	uint8_t i;
- 	for (i = 0; i < count; i++) {
- 		struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
-@@ -925,31 +934,36 @@ void dc_flip_surface_addrs(
- 		surface->public.address = flip_addrs[i].address;
- 		surface->public.flip_immediate = flip_addrs[i].flip_immediate;
- 	}
--	dc->hwss.update_plane_addrs(dc, &dc->current_context.res_ctx);
-+	core_dc->hwss.update_plane_addrs(core_dc, &core_dc->current_context.res_ctx);
- }
- 
- enum dc_irq_source dc_interrupt_to_irq_source(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t src_id,
- 		uint32_t ext_id)
- {
--	return dal_irq_service_to_irq_source(dc->res_pool.irqs, src_id, ext_id);
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	return dal_irq_service_to_irq_source(core_dc->res_pool.irqs, src_id, ext_id);
- }
- 
--void dc_interrupt_set(const struct core_dc *dc, enum dc_irq_source src, bool enable)
-+void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
- {
--	dal_irq_service_set(dc->res_pool.irqs, src, enable);
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	dal_irq_service_set(core_dc->res_pool.irqs, src, enable);
- }
- 
--void dc_interrupt_ack(struct core_dc *dc, enum dc_irq_source src)
-+void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
- {
--	dal_irq_service_ack(dc->res_pool.irqs, src);
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	dal_irq_service_ack(core_dc->res_pool.irqs, src);
- }
- 
- const struct dc_target *dc_get_target_on_irq_source(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		enum dc_irq_source src)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
- 	uint8_t i, j;
- 	uint8_t crtc_idx;
- 
-@@ -976,15 +990,15 @@ const struct dc_target *dc_get_target_on_irq_source(
- 		return NULL;
- 	}
- 
--	for (i = 0; i < dc->current_context.target_count; i++) {
--		struct core_target *target = dc->current_context.targets[i];
-+	for (i = 0; i < core_dc->current_context.target_count; i++) {
-+		struct core_target *target = core_dc->current_context.targets[i];
- 		struct dc_target *dc_target = &target->public;
- 
- 		for (j = 0; j < target->public.stream_count; j++) {
- 			const struct core_stream *stream =
- 				DC_STREAM_TO_CORE(dc_target->streams[j]);
- 
--			if (dc->current_context.res_ctx.
-+			if (core_dc->current_context.res_ctx.
- 					pipe_ctx[crtc_idx].stream == stream)
- 				return dc_target;
- 		}
-@@ -995,44 +1009,49 @@ const struct dc_target *dc_get_target_on_irq_source(
- }
- 
- void dc_set_power_state(
--	struct core_dc *dc,
-+	struct dc *dc,
- 	enum dc_acpi_cm_power_state power_state,
- 	enum dc_video_power_state video_power_state)
- {
--	dc->previous_power_state = dc->current_power_state;
--	dc->current_power_state = video_power_state;
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
-+	core_dc->previous_power_state = core_dc->current_power_state;
-+	core_dc->current_power_state = video_power_state;
- 
- 	switch (power_state) {
- 	case DC_ACPI_CM_POWER_STATE_D0:
--		init_hw(dc);
-+		init_hw(core_dc);
- 		break;
- 	default:
- 		/* NULL means "reset/release all DC targets" */
- 		dc_commit_targets(dc, NULL, 0);
- 
--		dc->hwss.power_down(dc);
-+		core_dc->hwss.power_down(core_dc);
- 		break;
- 	}
- 
- }
- 
--void dc_resume(const struct core_dc *dc)
-+void dc_resume(const struct dc *dc)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
- 	uint32_t i;
- 
--	for (i = 0; i < dc->link_count; i++)
--		core_link_resume(dc->links[i]);
-+	for (i = 0; i < core_dc->link_count; i++)
-+		core_link_resume(core_dc->links[i]);
- }
- 
- bool dc_read_dpcd(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		uint8_t *data,
- 		uint32_t size)
- {
--	struct core_link *link = dc->links[link_index];
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
- 
-+	struct core_link *link = core_dc->links[link_index];
- 	enum ddc_result r = dal_ddc_service_read_dpcd_data(
- 			link->ddc,
- 			address,
-@@ -1042,13 +1061,15 @@ bool dc_read_dpcd(
- }
- 
- bool dc_write_dpcd(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		const uint8_t *data,
- 		uint32_t size)
- {
--	struct core_link *link = dc->links[link_index];
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
-+	struct core_link *link = core_dc->links[link_index];
- 
- 	enum ddc_result r = dal_ddc_service_write_dpcd_data(
- 			link->ddc,
-@@ -1059,11 +1080,13 @@ bool dc_write_dpcd(
- }
- 
- bool dc_submit_i2c(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t link_index,
- 		struct i2c_command *cmd)
- {
--	struct core_link *link = dc->links[link_index];
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
-+	struct core_link *link = core_dc->links[link_index];
- 	struct ddc_service *ddc = link->ddc;
- 
- 	return dal_i2caux_submit_i2c_command(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 58c7d43..01c28f2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -58,11 +58,13 @@ enum {
-  ******************************************************************************/
- static void destruct(struct core_link *link)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
-+
- 	if (link->ddc)
- 		dal_ddc_service_destroy(&link->ddc);
- 
- 	if(link->link_enc)
--		link->ctx->dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
-+		core_dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
- }
- 
- /*
-@@ -988,7 +990,7 @@ static bool construct(
- 	enc_init_data.hpd_source = get_hpd_line(link, as);
- 	enc_init_data.transmitter =
- 			translate_encoder_to_transmitter(enc_init_data.encoder);
--	link->link_enc = dc_ctx->dc->res_pool.funcs->link_enc_create(
-+	link->link_enc = link->dc->res_pool.funcs->link_enc_create(
- 								&enc_init_data);
- 
- 	if( link->link_enc == NULL) {
-@@ -1049,7 +1051,7 @@ static bool construct(
- 
- 	return true;
- device_tag_fail:
--	link->ctx->dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
-+	link->dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
- link_enc_create_fail:
- 	dal_ddc_service_destroy(&link->ddc);
- ddc_create_fail:
-@@ -1621,14 +1623,14 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
- 
- void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- {
--    struct core_dc *dc = pipe_ctx->stream->ctx->dc;
-+	struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
- 
- 	if (DC_OK != enable_link(pipe_ctx)) {
- 			BREAK_TO_DEBUGGER();
- 			return;
- 	}
- 
--	dc->hwss.enable_stream(pipe_ctx);
-+	core_dc->hwss.enable_stream(pipe_ctx);
- 
- 	pipe_ctx->stream->status.link = &pipe_ctx->stream->sink->link->public;
- 
-@@ -1638,13 +1640,13 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- 
- void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
- {
--	struct core_dc *dc = pipe_ctx->stream->ctx->dc;
-+	struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
- 
- 	pipe_ctx->stream->status.link = NULL;
- 	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- 		deallocate_mst_payload(pipe_ctx);
- 
--	dc->hwss.disable_stream(pipe_ctx);
-+	core_dc->hwss.disable_stream(pipe_ctx);
- 
- 	pipe_ctx->stream->status.link = NULL;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 4a3d18d..5c586ba 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -79,14 +79,16 @@ void enable_surface_flip_reporting(struct dc_surface *dc_surface,
- 	/*register_flip_interrupt(surface);*/
- }
- 
--struct dc_surface *dc_create_surface(const struct core_dc *dc)
-+struct dc_surface *dc_create_surface(const struct dc *dc)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
- 	struct surface *surface = dm_alloc(sizeof(*surface));
- 
- 	if (NULL == surface)
- 		goto alloc_fail;
- 
--	if (false == construct(dc->ctx, surface))
-+	if (false == construct(core_dc->ctx, surface))
- 		goto construct_fail;
- 
- 	dc_surface_retain(&surface->protected.public);
-@@ -146,14 +148,15 @@ void dc_gamma_release(const struct dc_gamma *dc_gamma)
- 	}
- }
- 
--struct dc_gamma *dc_create_gamma(const struct core_dc *dc)
-+struct dc_gamma *dc_create_gamma(const struct dc *dc)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
- 	struct gamma *gamma = dm_alloc(sizeof(*gamma));
- 
- 	if (gamma == NULL)
- 		goto alloc_fail;
- 
--	if (false == construct_gamma(dc->ctx, gamma))
-+	if (false == construct_gamma(core_dc->ctx, gamma))
- 		goto construct_fail;
- 
- 	dc_gamma_retain(&gamma->protected.public);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index c697a5e..44fe442 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -92,7 +92,7 @@ const struct dc_target_status *dc_target_get_status(
- {
- 	uint8_t i;
- 	struct core_target* target = DC_TARGET_TO_CORE(dc_target);
--    struct core_dc *dc = target->ctx->dc;
-+    struct core_dc *dc = DC_TO_CORE(target->ctx->dc);
- 
- 	for (i = 0; i < dc->current_context.target_count; i++)
- 		if (target == dc->current_context.targets[i])
-@@ -151,6 +151,7 @@ bool dc_target_set_cursor_attributes(
- {
- 	uint8_t i, j;
- 	struct core_target *target;
-+	struct core_dc *core_dc;
- 	struct resource_context *res_ctx;
- 
- 	if (NULL == dc_target) {
-@@ -165,7 +166,8 @@ bool dc_target_set_cursor_attributes(
- 	}
- 
- 	target = DC_TARGET_TO_CORE(dc_target);
--	res_ctx = &target->ctx->dc->current_context.res_ctx;
-+	core_dc = DC_TO_CORE(target->ctx->dc);
-+	res_ctx = &core_dc->current_context.res_ctx;
- 
- 	for (i = 0; i < target->public.stream_count; i++) {
- 		for (j = 0; j < MAX_PIPES; j++) {
-@@ -195,6 +197,7 @@ bool dc_target_set_cursor_position(
- {
- 	uint8_t i, j;
- 	struct core_target *target;
-+	struct core_dc *core_dc;
- 	struct resource_context *res_ctx;
- 
- 	if (NULL == dc_target) {
-@@ -208,7 +211,8 @@ bool dc_target_set_cursor_position(
- 	}
- 
- 	target = DC_TARGET_TO_CORE(dc_target);
--	res_ctx = &target->ctx->dc->current_context.res_ctx;
-+	core_dc = DC_TO_CORE(target->ctx->dc);
-+	res_ctx = &core_dc->current_context.res_ctx;
- 
- 	for (i = 0; i < target->public.stream_count; i++) {
- 		for (j = 0; j < MAX_PIPES; j++) {
-@@ -235,8 +239,9 @@ uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- {
- 	uint8_t i, j;
- 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc);
- 	struct resource_context *res_ctx =
--		&target->ctx->dc->current_context.res_ctx;
-+		&core_dc->current_context.res_ctx;
- 
- 	for (i = 0; i < target->public.stream_count; i++) {
- 		for (j = 0; j < MAX_PIPES; j++) {
-@@ -254,17 +259,19 @@ uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- }
- 
- enum dc_irq_source dc_target_get_irq_src(
--	const struct core_dc *dc,
-+	const struct dc *dc,
- 	const struct dc_target *dc_target,
- 	const enum irq_type irq_type)
- {
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+
- 	uint8_t i;
- 	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
- 	struct core_stream *stream =
- 			DC_STREAM_TO_CORE(core_target->public.streams[0]);
- 
- 	for (i = 0; i < MAX_PIPES; i++)
--		if (dc->current_context.res_ctx.pipe_ctx[i].stream == stream)
-+		if (core_dc->current_context.res_ctx.pipe_ctx[i].stream == stream)
- 			return irq_type + i;
- 
- 	return irq_type;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 41010f7..5660790 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -45,7 +45,9 @@ struct dc_caps {
-     uint32_t max_audios;
- };
- 
--void dc_get_caps(const struct core_dc *dc, struct dc_caps *caps);
-+struct dc {
-+	struct dc_caps caps;
-+};
- 
- struct dc_init_data {
- 	struct hw_asic_id asic_id;
-@@ -62,8 +64,8 @@ struct dc_init_data {
- 	enum dce_environment dce_environment;
- };
- 
--struct core_dc *dc_create(const struct dc_init_data *init_params);
--void dc_destroy(struct core_dc **dc);
-+struct dc *dc_create(const struct dc_init_data *init_params);
-+void dc_destroy(struct dc **dc);
- 
- /*******************************************************************************
-  * Surface Interfaces
-@@ -140,7 +142,7 @@ struct dc_surface_status {
- /*
-  * Create a new surface with default parameters;
-  */
--struct dc_surface *dc_create_surface(const struct core_dc *dc);
-+struct dc_surface *dc_create_surface(const struct dc *dc);
- const struct dc_surface_status* dc_surface_get_status(
- 						struct dc_surface *dc_surface);
- 
-@@ -148,7 +150,7 @@ void dc_surface_retain(const struct dc_surface *dc_surface);
- void dc_surface_release(const struct dc_surface *dc_surface);
- 
- void dc_gamma_release(const struct dc_gamma *dc_gamma);
--struct dc_gamma *dc_create_gamma(const struct core_dc *dc);
-+struct dc_gamma *dc_create_gamma(const struct dc *dc);
- 
- /*
-  * This structure holds a surface address.  There could be multiple addresses
-@@ -169,7 +171,7 @@ struct dc_flip_addrs {
-  *   Surface addresses and flip attributes are programmed.
-  *   Surface flip occur at next configured time (h_sync or v_sync flip)
-  */
--void dc_flip_surface_addrs(struct core_dc *dc,
-+void dc_flip_surface_addrs(struct dc *dc,
- 		const struct dc_surface *const surfaces[],
- 		struct dc_flip_addrs flip_addrs[],
- 		uint32_t count);
-@@ -185,7 +187,7 @@ void dc_flip_surface_addrs(struct core_dc *dc,
-  *   This does not trigger a flip.  No surface address is programmed.
-  */
- bool dc_commit_surfaces_to_target(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		struct dc_surface *dc_surfaces[],
- 		uint8_t surface_count,
- 		struct dc_target *dc_target);
-@@ -230,8 +232,8 @@ void dc_target_log(
- 	enum log_major log_major,
- 	enum log_minor log_minor);
- 
--uint8_t dc_get_current_target_count(const struct core_dc *dc);
--struct dc_target *dc_get_target_at_index(const struct core_dc *dc, uint8_t i);
-+uint8_t dc_get_current_target_count(const struct dc *dc);
-+struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i);
- 
- bool dc_target_is_connected_to_sink(
- 		const struct dc_target *dc_target,
-@@ -241,7 +243,7 @@ uint8_t dc_target_get_controller_id(const struct dc_target *dc_target);
- 
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
- enum dc_irq_source dc_target_get_irq_src(
--	const struct core_dc *dc,
-+	const struct dc *dc,
- 	const struct dc_target *dc_target,
- 	const enum irq_type irq_type);
- 
-@@ -261,7 +263,7 @@ struct dc_validation_set {
-  *   No hardware is programmed for call.  Only validation is done.
-  */
- bool dc_validate_resources(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		const struct dc_validation_set set[],
- 		uint8_t set_count);
- 
-@@ -274,7 +276,7 @@ bool dc_validate_resources(
-  *   New targets are enabled with blank stream; no memory read.
-  */
- bool dc_commit_targets(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		struct dc_target *targets[],
- 		uint8_t target_count);
- 
-@@ -355,11 +357,11 @@ struct dc_link {
-  * boot time.  They cannot be created or destroyed.
-  * Use dc_get_caps() to get number of links.
-  */
--const struct dc_link *dc_get_link_at_index(struct core_dc *dc, uint32_t link_index);
-+const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
- 
- /* Return id of physical connector represented by a dc_link at link_index.*/
- const struct graphics_object_id dc_get_link_id_at_index(
--		struct core_dc *dc, uint32_t link_index);
-+		struct dc *dc, uint32_t link_index);
- 
- /* Set backlight level of an embedded panel (eDP, LVDS). */
- bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level);
-@@ -405,7 +407,7 @@ struct dc_sink {
- void dc_sink_retain(const struct dc_sink *sink);
- void dc_sink_release(const struct dc_sink *sink);
- 
--const struct audio **dc_get_audios(struct core_dc *dc);
-+const struct audio **dc_get_audios(struct dc *dc);
- 
- struct dc_sink_init_data {
- 	enum signal_type sink_signal;
-@@ -438,7 +440,7 @@ struct dc_cursor {
-  * Create a new cursor with default values for a given target.
-  */
- struct dc_cursor *dc_create_cursor_for_target(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		struct dc_target *dc_target);
- 
- /**
-@@ -450,7 +452,7 @@ struct dc_cursor *dc_create_cursor_for_target(
-  *   Cursor position is unmodified.
-  */
- bool dc_commit_cursor(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		struct dc_cursor *cursor);
- 
- /*
-@@ -460,7 +462,7 @@ bool dc_commit_cursor(
-  *   Cursor position will be programmed as well as enable/disable bit.
-  */
- bool dc_set_cursor_position(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		struct dc_cursor *cursor,
- 		struct dc_cursor_position *pos);
- 
-@@ -468,15 +470,15 @@ bool dc_set_cursor_position(
-  * Interrupt interfaces
-  ******************************************************************************/
- enum dc_irq_source dc_interrupt_to_irq_source(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t src_id,
- 		uint32_t ext_id);
--void dc_interrupt_set(const struct core_dc *dc, enum dc_irq_source src, bool enable);
--void dc_interrupt_ack(struct core_dc *dc, enum dc_irq_source src);
-+void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
-+void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
- const enum dc_irq_source dc_get_hpd_irq_source_at_index(
--		struct core_dc *dc, uint32_t link_index);
-+		struct dc *dc, uint32_t link_index);
- const struct dc_target *dc_get_target_on_irq_source(
--		const struct core_dc *dc,
-+		const struct dc *dc,
- 		enum dc_irq_source src);
- 
- /*******************************************************************************
-@@ -484,38 +486,38 @@ const struct dc_target *dc_get_target_on_irq_source(
-  ******************************************************************************/
- 
- void dc_set_power_state(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		enum dc_acpi_cm_power_state power_state,
- 		enum dc_video_power_state video_power_state);
--void dc_resume(const struct core_dc *dc);
-+void dc_resume(const struct dc *dc);
- 
- /*******************************************************************************
-  * DDC Interfaces
-  ******************************************************************************/
- 
- const struct ddc_service *dc_get_ddc_at_index(
--		struct core_dc *dc, uint32_t link_index);
-+		struct dc *dc, uint32_t link_index);
- 
- /*
-  * DPCD access interfaces
-  */
- 
- bool dc_read_dpcd(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		uint8_t *data,
- 		uint32_t size);
- 
- bool dc_write_dpcd(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t link_index,
- 		uint32_t address,
- 		const uint8_t *data,
- 	uint32_t size);
- 
- bool dc_submit_i2c(
--		struct core_dc *dc,
-+		struct dc *dc,
- 		uint32_t link_index,
- 		struct i2c_command *cmd);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 0fb4822..e849972 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -33,7 +33,6 @@
- #include "signal_types.h"
- 
- /* forward declarations */
--struct core_dc;
- struct dc_surface;
- struct dc_target;
- struct dc_stream;
-@@ -69,7 +68,7 @@ enum dce_environment {
- /********************************/
- 
- struct dc_context {
--	struct core_dc *dc;
-+	struct dc *dc;
- 
- #if defined(BUILD_DAL_TEST)
- 	struct test_driver_context *driver_context;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-index 6d20575..21860e4 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
-@@ -11,7 +11,11 @@
- #include "core_types.h"
- #include "hw_sequencer.h"
- 
-+#define DC_TO_CORE(dc)\
-+	container_of(dc, struct core_dc, public)
-+
- struct core_dc {
-+	struct dc public;
- 	struct dc_context *ctx;
- 
- 	uint8_t link_count;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0865-drm-amd-dal-Fix-DCE110-not-initializing-number-of-cl.patch b/common/recipes-kernel/linux/files/0865-drm-amd-dal-Fix-DCE110-not-initializing-number-of-cl.patch
deleted file mode 100644
index cbb58e64..00000000
--- a/common/recipes-kernel/linux/files/0865-drm-amd-dal-Fix-DCE110-not-initializing-number-of-cl.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 9b7f7483ee369cfed1d98952ecf8cc3408a683b6 Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Sat, 27 Feb 2016 17:48:33 -0500
-Subject: [PATCH 0865/1110] drm/amd/dal: Fix DCE110 not initializing number of
- clock sources.
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 1a315c0..557c2fe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1096,6 +1096,7 @@ bool dce110_construct_resource_pool(
- 				bp,
- 				CLOCK_SOURCE_ID_EXTERNAL,
- 				NULL);
-+		pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
- 	} else {
- 		pool->dp_clock_source =
- 			dce110_clock_source_create(
-@@ -1103,6 +1104,7 @@ bool dce110_construct_resource_pool(
- 				bp,
- 				CLOCK_SOURCE_ID_PLL0,
- 				&dce110_clk_src_reg_offsets[0]);
-+		pool->clk_src_count = DCE110_CLK_SRC_TOTAL - 1;
- 	}
- 
- 	pool->clock_sources[DCE110_CLK_SRC0] =
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0866-drm-amd-dal-Don-t-include-audio-type-in-dc.h.patch b/common/recipes-kernel/linux/files/0866-drm-amd-dal-Don-t-include-audio-type-in-dc.h.patch
deleted file mode 100644
index 3c2ef09d..00000000
--- a/common/recipes-kernel/linux/files/0866-drm-amd-dal-Don-t-include-audio-type-in-dc.h.patch
+++ /dev/null
@@ -1,307 +0,0 @@
-From 4be119ad847e317ad53d1162155b63dccd2ec607 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Sat, 27 Feb 2016 17:04:24 -0500
-Subject: [PATCH 0866/1110] drm/amd/dal: Don't include audio type in dc.h
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc.h               |   2 +-
- drivers/gpu/drm/amd/dal/dc/dc_types.h         | 101 ++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dm_services.h      |   2 -
- drivers/gpu/drm/amd/dal/include/audio_types.h | 129 --------------------------
- 4 files changed, 102 insertions(+), 132 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 5660790..348bb0d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -28,7 +28,7 @@
- 
- #include "dc_types.h"
- #include "dal_types.h"
--#include "audio_types.h"
-+#include "grph_object_defs.h"
- #include "logger_types.h"
- #include "gpio_types.h"
- #include "link_service_types.h"
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index e849972..a0a8542 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -571,4 +571,105 @@ struct render_mode {
- 	enum pixel_format pixel_format;
- };
- 
-+/* audio*/
-+
-+union audio_sample_rates {
-+	struct sample_rates {
-+		uint8_t RATE_32:1;
-+		uint8_t RATE_44_1:1;
-+		uint8_t RATE_48:1;
-+		uint8_t RATE_88_2:1;
-+		uint8_t RATE_96:1;
-+		uint8_t RATE_176_4:1;
-+		uint8_t RATE_192:1;
-+	} rate;
-+
-+	uint8_t all;
-+};
-+
-+struct audio_speaker_flags {
-+    uint32_t FL_FR:1;
-+    uint32_t LFE:1;
-+    uint32_t FC:1;
-+    uint32_t RL_RR:1;
-+    uint32_t RC:1;
-+    uint32_t FLC_FRC:1;
-+    uint32_t RLC_RRC:1;
-+    uint32_t SUPPORT_AI:1;
-+};
-+
-+struct audio_speaker_info {
-+	uint32_t ALLSPEAKERS:7;
-+	uint32_t SUPPORT_AI:1;
-+};
-+
-+
-+struct audio_info_flags {
-+
-+	union {
-+
-+		struct audio_speaker_flags speaker_flags;
-+		struct audio_speaker_info   info;
-+
-+		uint8_t all;
-+	};
-+};
-+
-+enum audio_format_code {
-+	AUDIO_FORMAT_CODE_FIRST = 1,
-+	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
-+
-+	AUDIO_FORMAT_CODE_AC3,
-+	/*Layers 1 & 2 */
-+	AUDIO_FORMAT_CODE_MPEG1,
-+	/*MPEG1 Layer 3 */
-+	AUDIO_FORMAT_CODE_MP3,
-+	/*multichannel */
-+	AUDIO_FORMAT_CODE_MPEG2,
-+	AUDIO_FORMAT_CODE_AAC,
-+	AUDIO_FORMAT_CODE_DTS,
-+	AUDIO_FORMAT_CODE_ATRAC,
-+	AUDIO_FORMAT_CODE_1BITAUDIO,
-+	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
-+	AUDIO_FORMAT_CODE_DTS_HD,
-+	AUDIO_FORMAT_CODE_MAT_MLP,
-+	AUDIO_FORMAT_CODE_DST,
-+	AUDIO_FORMAT_CODE_WMAPRO,
-+	AUDIO_FORMAT_CODE_LAST,
-+	AUDIO_FORMAT_CODE_COUNT =
-+		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
-+};
-+
-+struct audio_mode {
-+	 /* ucData[0] [6:3] */
-+	enum audio_format_code format_code;
-+	/* ucData[0] [2:0] */
-+	uint8_t channel_count;
-+	/* ucData[1] */
-+	union audio_sample_rates sample_rates;
-+	union {
-+		/* for LPCM */
-+		uint8_t sample_size;
-+		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
-+		uint8_t max_bit_rate;
-+		/* for Audio Formats 9-15 */
-+		uint8_t vendor_specific;
-+	};
-+};
-+
-+struct audio_info {
-+	struct audio_info_flags flags;
-+	uint32_t video_latency;
-+	uint32_t audio_latency;
-+	uint32_t display_index;
-+	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
-+	uint32_t manufacture_id;
-+	uint32_t product_id;
-+	/* PortID used for ContainerID when defined */
-+	uint32_t port_id[2];
-+	uint32_t mode_count;
-+	/* this field must be last in this struct */
-+	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
-+};
-+
- #endif /* DC_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 2d44e92..8acdcd4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -34,8 +34,6 @@
- /* TODO: remove when DC is complete. */
- #include "dm_services_types.h"
- #include "logger_interface.h"
--#include "include/dal_types.h"
--#include "irq_types.h"
- #include "link_service_types.h"
- 
- #undef DEPRECATED
-diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h
-index 8f1eda1..f08b609 100644
---- a/drivers/gpu/drm/amd/dal/include/audio_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/audio_types.h
-@@ -33,13 +33,6 @@
- #define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18
- #define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF
- 
--struct audio_pll_hw_settings {
--	uint32_t feed_back_divider;
--	uint32_t step_size_integer;
--	uint32_t step_size_fraction;
--	uint32_t step_range;
--};
--
- struct audio_clock_info {
- 	/* pixel clock frequency*/
- 	uint32_t pixel_clock_in_10khz;
-@@ -70,113 +63,6 @@ enum audio_dto_source {
- 	DTO_SOURCE_ID5
- };
- 
--union audio_sample_rates {
--	struct sample_rates {
--		uint8_t RATE_32:1;
--		uint8_t RATE_44_1:1;
--		uint8_t RATE_48:1;
--		uint8_t RATE_88_2:1;
--		uint8_t RATE_96:1;
--		uint8_t RATE_176_4:1;
--		uint8_t RATE_192:1;
--	} rate;
--
--	uint8_t all;
--};
--
--enum audio_format_code {
--	AUDIO_FORMAT_CODE_FIRST = 1,
--	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
--
--	AUDIO_FORMAT_CODE_AC3,
--	/*Layers 1 & 2 */
--	AUDIO_FORMAT_CODE_MPEG1,
--	/*MPEG1 Layer 3 */
--	AUDIO_FORMAT_CODE_MP3,
--	/*multichannel */
--	AUDIO_FORMAT_CODE_MPEG2,
--	AUDIO_FORMAT_CODE_AAC,
--	AUDIO_FORMAT_CODE_DTS,
--	AUDIO_FORMAT_CODE_ATRAC,
--	AUDIO_FORMAT_CODE_1BITAUDIO,
--	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
--	AUDIO_FORMAT_CODE_DTS_HD,
--	AUDIO_FORMAT_CODE_MAT_MLP,
--	AUDIO_FORMAT_CODE_DST,
--	AUDIO_FORMAT_CODE_WMAPRO,
--	AUDIO_FORMAT_CODE_LAST,
--	AUDIO_FORMAT_CODE_COUNT =
--		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
--};
--
--struct audio_mode {
--	 /* ucData[0] [6:3] */
--	enum audio_format_code format_code;
--	/* ucData[0] [2:0] */
--	uint8_t channel_count;
--	/* ucData[1] */
--	union audio_sample_rates sample_rates;
--	union {
--		/* for LPCM */
--		uint8_t sample_size;
--		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
--		uint8_t max_bit_rate;
--		/* for Audio Formats 9-15 */
--		uint8_t vendor_specific;
--	};
--};
--
--struct audio_speaker_flags {
--    uint32_t FL_FR:1;
--    uint32_t LFE:1;
--    uint32_t FC:1;
--    uint32_t RL_RR:1;
--    uint32_t RC:1;
--    uint32_t FLC_FRC:1;
--    uint32_t RLC_RRC:1;
--    uint32_t SUPPORT_AI:1;
--};
--
--struct audio_speaker_info {
--    uint32_t ALLSPEAKERS:7;
--    uint32_t SUPPORT_AI:1;
--};
--
--struct audio_info_flags {
--
--	union {
--
--		struct audio_speaker_flags speaker_flags;
--		struct audio_speaker_info   info;
--
--		uint8_t all;
--	};
--};
--
--/*struct audio_info_flags {
--	struct audio_speaker_flags {
--		uint32_t FL_FR:1;
--		uint32_t LFE:1;
--		uint32_t FC:1;
--		uint32_t RL_RR:1;
--		uint32_t RC:1;
--		uint32_t FLC_FRC:1;
--		uint32_t RLC_RRC:1;
--		uint32_t SUPPORT_AI:1;
--	};
--
--	struct audio_speaker_info {
--		uint32_t ALLSPEAKERS:7;
--		uint32_t SUPPORT_AI:1;
--	};
--
--	union {
--		struct audio_speaker_flags speaker_flags;
--		struct audio_speaker_info info;
--	};
--};
--*/
--
- union audio_cea_channels {
- 	uint8_t all;
- 	struct audio_cea_channels_bits {
-@@ -191,21 +77,6 @@ union audio_cea_channels {
- 	} channels;
- };
- 
--struct audio_info {
--	struct audio_info_flags flags;
--	uint32_t video_latency;
--	uint32_t audio_latency;
--	uint32_t display_index;
--	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
--	uint32_t manufacture_id;
--	uint32_t product_id;
--	/* PortID used for ContainerID when defined */
--	uint32_t port_id[2];
--	uint32_t mode_count;
--	/* this field must be last in this struct */
--	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
--};
--
- struct audio_crtc_info {
- 	uint32_t h_total;
- 	uint32_t h_active;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0867-drm-amd-dal-Fix-surface-flip-pending-polling.patch b/common/recipes-kernel/linux/files/0867-drm-amd-dal-Fix-surface-flip-pending-polling.patch
deleted file mode 100644
index 593e66e4..00000000
--- a/common/recipes-kernel/linux/files/0867-drm-amd-dal-Fix-surface-flip-pending-polling.patch
+++ /dev/null
@@ -1,206 +0,0 @@
-From 4c480f494dfd11d9a8677eaa5f05b2f214ae1571 Mon Sep 17 00:00:00 2001
-From: Aric Cyr <aric.cyr@amd.com>
-Date: Sat, 27 Feb 2016 18:22:23 -0500
-Subject: [PATCH 0867/1110] drm/amd/dal: Fix surface flip pending polling
-
-Surface flips were waiting for surface pending bit to be cleared
-while the pipe was locked resulting in an infinite loop.
-
-Signed-off-by: Aric Cyr <aric.cyr@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c                  | 19 +++++++++++--------
- .../gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c   |  3 +++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c  | 16 ++++++----------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h  | 10 ++++++++++
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c    | 17 +++++++----------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c    |  2 ++
- drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h         |  2 ++
- 7 files changed, 41 insertions(+), 28 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 339c82f..0ccf1d1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -923,17 +923,20 @@ void dc_flip_surface_addrs(
- 		uint32_t count)
- {
- 	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	int i, j;
- 
--	uint8_t i;
- 	for (i = 0; i < count; i++) {
--		struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
--		/*
--		 * TODO figure out a good way to keep track of address. Until
--		 * then we'll have to awkwardly bypass the "const" surface.
--		 */
--		surface->public.address = flip_addrs[i].address;
--		surface->public.flip_immediate = flip_addrs[i].flip_immediate;
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct core_surface *ctx_surface =
-+				core_dc->current_context.res_ctx.pipe_ctx[j].surface;
-+			if (DC_SURFACE_TO_CORE(surfaces[i]) == ctx_surface) {
-+				ctx_surface->public.address = flip_addrs[i].address;
-+				ctx_surface->public.flip_immediate = flip_addrs[i].flip_immediate;
-+				break;
-+			}
-+		}
- 	}
-+
- 	core_dc->hwss.update_plane_addrs(core_dc, &core_dc->current_context.res_ctx);
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 4e4ada8..0513731 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1434,6 +1434,9 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_
- 					false);
- 
- 
-+		if (surface->public.flip_immediate)
-+			pipe_ctx->mi->funcs->wait_for_no_surface_update_pending(pipe_ctx->mi);
-+
- 		if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false)) {
- 			dm_error("DC: failed to unblank crtc!\n");
- 			BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index b1f1135..30c6048 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -422,17 +422,14 @@ static void program_pixel_format(
- 	}
- }
- 
--static void wait_for_no_surface_update_pending(
--				struct dce110_mem_input *mem_input110)
-+void dce110_mem_input_wait_for_no_surface_update_pending(struct mem_input *mem_input)
- {
-+	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- 	uint32_t value;
- 
- 	do  {
--		value = dm_read_reg(mem_input110->base.ctx,
--				DCP_REG(mmGRPH_UPDATE));
--
--	} while (get_reg_field_value(value, GRPH_UPDATE,
--			GRPH_SURFACE_UPDATE_PENDING));
-+		value = dm_read_reg(mem_input110->base.ctx,	DCP_REG(mmGRPH_UPDATE));
-+	} while (get_reg_field_value(value, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING));
- }
- 
- bool dce110_mem_input_program_surface_flip_and_addr(
-@@ -446,9 +443,6 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- 	program_addr(mem_input110,
- 		address);
- 
--	if (flip_immediate)
--		wait_for_no_surface_update_pending(mem_input110);
--
- 	return true;
- }
- 
-@@ -922,6 +916,8 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
- 			dce110_mem_input_program_surface_flip_and_addr,
- 	.mem_input_program_surface_config =
- 			dce110_mem_input_program_surface_config,
-+	.wait_for_no_surface_update_pending =
-+			dce110_mem_input_wait_for_no_surface_update_pending
- };
- /*****************************************/
- /* Constructor, Destructor               */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-index 32ee571..a42e06a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
-@@ -128,4 +128,14 @@ bool  dce110_mem_input_program_surface_config(
- 	union plane_size *plane_size,
- 	enum dc_rotation_angle rotation);
- 
-+/*
-+ * dce110_mem_input_wait_for_no_surface_update_pending
-+ *
-+ * This function will wait until the surface update-pending bit is cleared.
-+ * This is necessary when a flip immediate call is requested as we shouldn't
-+ * return until the flip has actually occurred.
-+ */
-+void dce110_mem_input_wait_for_no_surface_update_pending(
-+	struct mem_input *mem_input);
-+
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-index acfbd08..5f819de 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
-@@ -492,17 +492,15 @@ static void program_pixel_format(
- 	}
- }
- 
--static void wait_for_no_surface_update_pending(
--				struct dce110_mem_input *mem_input110)
-+void dce110_mem_input_v_wait_for_no_surface_update_pending(
-+				struct mem_input *mem_input)
- {
-+	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- 	uint32_t value;
- 
- 	do  {
--		value = dm_read_reg(mem_input110->base.ctx,
--				DCP_REG(mmUNP_GRPH_UPDATE));
--
--	} while (get_reg_field_value(value, UNP_GRPH_UPDATE,
--			GRPH_SURFACE_UPDATE_PENDING));
-+		value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmUNP_GRPH_UPDATE));
-+	} while (get_reg_field_value(value, UNP_GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING));
- }
- 
- bool dce110_mem_input_v_program_surface_flip_and_addr(
-@@ -516,9 +514,6 @@ bool dce110_mem_input_v_program_surface_flip_and_addr(
- 	program_addr(mem_input110,
- 		address);
- 
--	if (flip_immediate)
--		wait_for_no_surface_update_pending(mem_input110);
--
- 	return true;
- }
- 
-@@ -867,6 +862,8 @@ static struct mem_input_funcs dce110_mem_input_v_funcs = {
- 			dce110_mem_input_v_program_surface_flip_and_addr,
- 	.mem_input_program_surface_config =
- 			dce110_mem_input_v_program_surface_config,
-+	.wait_for_no_surface_update_pending =
-+			dce110_mem_input_v_wait_for_no_surface_update_pending
- };
- /*****************************************/
- /* Constructor, Destructor               */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-index 27533bb..d9bc223 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-@@ -181,6 +181,8 @@ static struct mem_input_funcs dce80_mem_input_funcs = {
- 			dce110_mem_input_program_surface_flip_and_addr,
- 	.mem_input_program_surface_config =
- 			dce110_mem_input_program_surface_config,
-+	.wait_for_no_surface_update_pending =
-+			dce110_mem_input_wait_for_no_surface_update_pending
- };
- 
- /*****************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-index 8339d61..3829694 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-@@ -64,6 +64,8 @@ struct mem_input_funcs {
- 		struct dc_tiling_info *tiling_info,
- 		union plane_size *plane_size,
- 		enum dc_rotation_angle rotation);
-+
-+	void (*wait_for_no_surface_update_pending)(struct mem_input *mem_input);
- };
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch b/common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch
deleted file mode 100644
index a961978b..00000000
--- a/common/recipes-kernel/linux/files/0868-drm-amd-dal-simplify-clock-source-creation-by-unroll.patch
+++ /dev/null
@@ -1,271 +0,0 @@
-From ac4532f549eb83f60bc38503b3dc63960e2b453b Mon Sep 17 00:00:00 2001
-From: Tony Cheng <Tony.Cheng@amd.com>
-Date: Sat, 27 Feb 2016 17:09:52 -0500
-Subject: [PATCH 0868/1110] drm/amd/dal: simplify clock source creation by
- unrolling loop
-
-- also fix bug where we don't handle dp clk create failure
-
-Signed-off-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 50 +++++++----------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 53 +++++++-----------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 64 +++++++---------------
- 3 files changed, 61 insertions(+), 106 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 642c82a..03a5ab0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -58,14 +58,6 @@
- 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
- #endif
- 
--enum dce100_clk_src_array_id {
--	DCE100_CLK_SRC0 = 0,
--	DCE100_CLK_SRC1,
--	DCE100_CLK_SRC2,
--
--	DCE100_CLK_SRC_TOTAL
--};
--
- static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
- 	{
- 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-@@ -936,7 +928,6 @@ bool dce100_construct_resource_pool(
- 	struct dc_context *ctx = dc->ctx;
- 	struct firmware_info info;
- 	struct dc_bios *bp;
--	int regular_pll_offset = 0;
- 
- 	pool->adapter_srv = as;
- 	pool->funcs = &dce100_res_pool_funcs;
-@@ -953,30 +944,31 @@ bool dce100_construct_resource_pool(
- 	if (dal_adapter_service_get_firmware_info(as, &info) &&
- 		info.external_clock_source_frequency_for_dp != 0) {
- 		pool->dp_clock_source =
--			dce100_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_EXTERNAL,
--				NULL);
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL);
-+
-+		pool->clock_sources[0] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]);
-+		pool->clock_sources[1] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]);
-+		pool->clock_sources[2] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce100_clk_src_reg_offsets[2]);
-+		pool->clk_src_count = 3;
-+
- 	} else {
- 		pool->dp_clock_source =
--			dce100_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_PLL0,
--				&dce100_clk_src_reg_offsets[0]);
--		regular_pll_offset = 1;
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce100_clk_src_reg_offsets[0]);
-+		pool->clock_sources[0] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce100_clk_src_reg_offsets[1]);
-+		pool->clock_sources[1] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce100_clk_src_reg_offsets[2]);
-+		pool->clk_src_count = 2;
- 	}
- 
--	pool->clk_src_count = DCE100_CLK_SRC_TOTAL - regular_pll_offset;
--
--	for (i = 0; i < pool->clk_src_count; ++i, ++regular_pll_offset)
--		pool->clock_sources[i] =
--			dce100_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_PLL0 + regular_pll_offset,
--				&dce100_clk_src_reg_offsets[regular_pll_offset]);
-+	if (pool->dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto clk_src_create_fail;
-+	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 557c2fe..cde8d64 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -59,13 +59,6 @@
- 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
- #endif
- 
--enum dce110_clk_src_array_id {
--	DCE110_CLK_SRC0 = 0,
--	DCE110_CLK_SRC1,
--
--	DCE110_CLK_SRC_TOTAL
--};
--
- static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
- 	{
- 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-@@ -291,6 +284,10 @@ static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = {
- 	{
- 		.pll_cntl = mmBPHYC_PLL1_PLL_CNTL,
- 		.pixclk_resync_cntl  = mmPIXCLK1_RESYNC_CNTL
-+	},
-+	{
-+		.pll_cntl = mmBPHYC_PLL2_PLL_CNTL,
-+		.pixclk_resync_cntl  = mmPIXCLK2_RESYNC_CNTL
- 	}
- };
- 
-@@ -1091,35 +1088,23 @@ bool dce110_construct_resource_pool(
- 	if (dal_adapter_service_get_firmware_info(as, &info) &&
- 		info.external_clock_source_frequency_for_dp != 0) {
- 		pool->dp_clock_source =
--			dce110_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_EXTERNAL,
--				NULL);
--		pool->clk_src_count = DCE110_CLK_SRC_TOTAL;
--	} else {
--		pool->dp_clock_source =
--			dce110_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_PLL0,
--				&dce110_clk_src_reg_offsets[0]);
--		pool->clk_src_count = DCE110_CLK_SRC_TOTAL - 1;
-+				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL);
-+
-+		pool->clock_sources[0] =
-+				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce110_clk_src_reg_offsets[0]);
-+		pool->clock_sources[1] =
-+				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce110_clk_src_reg_offsets[1]);
-+
-+		pool->clk_src_count = 2;
-+
-+		/* TODO: find out if CZ support 3 PLLs */
- 	}
- 
--	pool->clock_sources[DCE110_CLK_SRC0] =
--		dce110_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL0,
--			&dce110_clk_src_reg_offsets[0]);
--
--	pool->clock_sources[DCE110_CLK_SRC1] =
--		dce110_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL1,
--			&dce110_clk_src_reg_offsets[1]);
-+	if (pool->dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto clk_src_create_fail;
-+	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index e4f2bef..fd97afe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -61,14 +61,6 @@
- #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
- #endif
- 
--enum dce80_clk_src_array_id {
--	DCE80_CLK_SRC0 = 0,
--	DCE80_CLK_SRC1,
--	DCE80_CLK_SRC2,
--
--	DCE80_CLK_SRC_TOTAL
--};
--
- #define DCE11_DIG_FE_CNTL 0x4a00
- #define DCE11_DIG_BE_CNTL 0x4a47
- #define DCE11_DP_SEC 0x4ac3
-@@ -1046,7 +1038,6 @@ bool dce80_construct_resource_pool(
- 	struct dc_context *ctx = dc->ctx;
- 	struct firmware_info info;
- 	struct dc_bios *bp;
--	int regular_pll_offset = 0;
- 
- 	pool->adapter_srv = as;
- 	pool->funcs = &dce80_res_pool_funcs;
-@@ -1063,44 +1054,31 @@ bool dce80_construct_resource_pool(
- 	if (dal_adapter_service_get_firmware_info(as, &info) &&
- 		info.external_clock_source_frequency_for_dp != 0) {
- 		pool->dp_clock_source =
--			dce80_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_EXTERNAL,
--				NULL);
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL);
-+
-+		pool->clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce80_clk_src_reg_offsets[0]);
-+		pool->clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce80_clk_src_reg_offsets[1]);
-+		pool->clock_sources[2] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce80_clk_src_reg_offsets[2]);
-+		pool->clk_src_count = 3;
-+
- 	} else {
- 		pool->dp_clock_source =
--			dce80_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_PLL0,
--				&dce80_clk_src_reg_offsets[0]);
--		regular_pll_offset = 1;
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &dce80_clk_src_reg_offsets[0]);
-+		pool->clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &dce80_clk_src_reg_offsets[1]);
-+		pool->clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &dce80_clk_src_reg_offsets[2]);
-+		pool->clk_src_count = 2;
- 	}
- 
--	pool->clk_src_count = DCE80_CLK_SRC_TOTAL - regular_pll_offset;
--
--	for (i = 0; i < DCE80_CLK_SRC_TOTAL; ++i, ++regular_pll_offset)
--		pool->clock_sources[DCE80_CLK_SRC0 + i] =
--			dce80_clock_source_create(
--				ctx,
--				bp,
--				CLOCK_SOURCE_ID_PLL0 + regular_pll_offset,
--				&dce80_clk_src_reg_offsets[regular_pll_offset]);
--
--	pool->clock_sources[DCE80_CLK_SRC1] =
--		dce80_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL1,
--			&dce80_clk_src_reg_offsets[1]);
--
--	pool->clock_sources[DCE80_CLK_SRC2] =
--		dce80_clock_source_create(
--			ctx,
--			bp,
--			CLOCK_SOURCE_ID_PLL2,
--			&dce80_clk_src_reg_offsets[2]);
-+	if (pool->dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto clk_src_create_fail;
-+	}
- 
- 	for (i = 0; i < pool->clk_src_count; i++) {
- 		if (pool->clock_sources[i] == NULL) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0869-drm-amd-dal-clean-up-resource.h-with-proper-prefix.patch b/common/recipes-kernel/linux/files/0869-drm-amd-dal-clean-up-resource.h-with-proper-prefix.patch
deleted file mode 100644
index 3145c475..00000000
--- a/common/recipes-kernel/linux/files/0869-drm-amd-dal-clean-up-resource.h-with-proper-prefix.patch
+++ /dev/null
@@ -1,858 +0,0 @@
-From e2357a4df01c1a0ada555e0202597069e22a4cce Mon Sep 17 00:00:00 2001
-From: Tony Cheng <Tony.Cheng@amd.com>
-Date: Sat, 27 Feb 2016 14:07:48 -0500
-Subject: [PATCH 0869/1110] drm/amd/dal: clean up resource.h with proper prefix
-
-- prefix public function with resource_*
-- move pplib related logic to dc.c
-
-Signed-off-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 155 +++++++++++++++++--
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 165 ++-------------------
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  14 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  10 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  14 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  14 +-
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  40 +++--
- 7 files changed, 204 insertions(+), 208 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 0ccf1d1..d547fb9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -376,7 +376,7 @@ ctx_fail:
- 
- static void destruct(struct core_dc *dc)
- {
--	val_ctx_destruct(&dc->current_context);
-+	resource_validate_ctx_destruct(&dc->current_context);
- 	destroy_links(dc);
- 	dc->res_pool.funcs->destruct(&dc->res_pool);
- 	dal_logger_destroy(&dc->ctx->logger);
-@@ -509,8 +509,9 @@ bool dc_validate_resources(
- 	result = core_dc->res_pool.funcs->validate_with_context(
- 						core_dc, set, set_count, context);
- 
--	val_ctx_destruct(context);
-+	resource_validate_ctx_destruct(context);
- 	dm_free(context);
-+
- context_alloc_fail:
- 
- 	return (result == DC_OK);
-@@ -541,7 +542,7 @@ static void program_timing_sync(
- 			if (!ctx->res_ctx.pipe_ctx[j].stream)
- 				continue;
- 
--			if (is_same_timing(
-+			if (resource_is_same_timing(
- 				&ctx->res_ctx.pipe_ctx[j].stream->public.timing,
- 				&ctx->res_ctx.pipe_ctx[i].stream->public
- 								.timing)) {
-@@ -624,6 +625,140 @@ static void target_disable_memory_requests(struct dc_target *dc_target,
- 	}
- }
- 
-+void pplib_apply_safe_state(
-+	const struct core_dc *dc)
-+{
-+	dm_pp_apply_safe_state(dc->ctx);
-+}
-+
-+static void fill_display_configs(
-+	const struct validate_context *context,
-+	struct dm_pp_display_configuration *pp_display_cfg)
-+{
-+	uint8_t i, j, k;
-+	uint8_t num_cfgs = 0;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		const struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct dm_pp_single_disp_config *cfg =
-+					&pp_display_cfg->disp_configs[num_cfgs];
-+			const struct pipe_ctx *pipe_ctx = NULL;
-+
-+			for (k = 0; k < MAX_PIPES; k++)
-+				if (stream ==
-+					context->res_ctx.pipe_ctx[k].stream) {
-+					pipe_ctx = &context->res_ctx.pipe_ctx[k];
-+					break;
-+				}
-+
-+			num_cfgs++;
-+			cfg->signal = pipe_ctx->signal;
-+			cfg->pipe_idx = pipe_ctx->pipe_idx;
-+			cfg->src_height = stream->public.src.height;
-+			cfg->src_width = stream->public.src.width;
-+			cfg->ddi_channel_mapping =
-+				stream->sink->link->ddi_channel_mapping.raw;
-+			cfg->transmitter =
-+				stream->sink->link->link_enc->transmitter;
-+			cfg->link_settings.lane_count = stream->sink->link->public.cur_link_settings.lane_count;
-+			cfg->link_settings.link_rate = stream->sink->link->public.cur_link_settings.link_rate;
-+			cfg->link_settings.link_spread = stream->sink->link->public.cur_link_settings.link_spread;
-+			cfg->sym_clock = stream->public.timing.pix_clk_khz;
-+			switch (stream->public.timing.display_color_depth) {
-+			case COLOR_DEPTH_101010:
-+				cfg->sym_clock = (cfg->sym_clock * 30) / 24;
-+				break;
-+			case COLOR_DEPTH_121212:
-+				cfg->sym_clock = (cfg->sym_clock * 36) / 24;
-+				break;
-+			case COLOR_DEPTH_161616:
-+				cfg->sym_clock = (cfg->sym_clock * 48) / 24;
-+				break;
-+			default:
-+				break;
-+			}
-+			/* TODO: unhardcode*/
-+			cfg->v_refresh = 60;
-+		}
-+	}
-+	pp_display_cfg->display_count = num_cfgs;
-+}
-+
-+static uint32_t get_min_vblank_time_us(const struct validate_context *context)
-+{
-+	uint8_t i, j;
-+	uint32_t min_vertical_blank_time = -1;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		const struct core_target *target = context->targets[i];
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			const struct dc_stream *stream =
-+						target->public.streams[j];
-+			uint32_t vertical_blank_in_pixels = 0;
-+			uint32_t vertical_blank_time = 0;
-+
-+			vertical_blank_in_pixels = stream->timing.h_total *
-+				(stream->timing.v_total
-+					- stream->timing.v_addressable);
-+			vertical_blank_time = vertical_blank_in_pixels
-+				* 1000 / stream->timing.pix_clk_khz;
-+			if (min_vertical_blank_time > vertical_blank_time)
-+				min_vertical_blank_time = vertical_blank_time;
-+		}
-+	}
-+	return min_vertical_blank_time;
-+}
-+
-+void pplib_apply_display_requirements(
-+	const struct core_dc *dc,
-+	const struct validate_context *context,
-+	struct dm_pp_display_configuration *pp_display_cfg)
-+{
-+	pp_display_cfg->all_displays_in_sync =
-+		context->bw_results.all_displays_in_sync;
-+	pp_display_cfg->nb_pstate_switch_disable =
-+			context->bw_results.nbp_state_change_enable == false;
-+	pp_display_cfg->cpu_cc6_disable =
-+			context->bw_results.cpuc_state_change_enable == false;
-+	pp_display_cfg->cpu_pstate_disable =
-+			context->bw_results.cpup_state_change_enable == false;
-+	pp_display_cfg->cpu_pstate_separation_time =
-+			context->bw_results.required_blackout_duration_us;
-+
-+	pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
-+		/ MEMORY_TYPE_MULTIPLIER;
-+	pp_display_cfg->min_engine_clock_khz = context->bw_results.required_sclk;
-+	pp_display_cfg->min_engine_clock_deep_sleep_khz
-+			= context->bw_results.required_sclk_deep_sleep;
-+
-+	pp_display_cfg->avail_mclk_switch_time_us =
-+						get_min_vblank_time_us(context);
-+	/* TODO: dce11.2*/
-+	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
-+
-+	pp_display_cfg->disp_clk_khz = context->bw_results.dispclk_khz;
-+
-+	fill_display_configs(context, pp_display_cfg);
-+
-+	/* TODO: is this still applicable?*/
-+	if (pp_display_cfg->display_count == 1) {
-+		const struct dc_crtc_timing *timing =
-+			&context->targets[0]->public.streams[0]->timing;
-+
-+		pp_display_cfg->crtc_index =
-+			pp_display_cfg->disp_configs[0].pipe_idx;
-+		pp_display_cfg->line_time_in_us = timing->h_total * 1000
-+							/ timing->pix_clk_khz;
-+	}
-+
-+	dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-+}
-+
- bool dc_commit_targets(
- 	struct dc *dc,
- 	struct dc_target *targets[],
-@@ -665,7 +800,7 @@ bool dc_commit_targets(
- 	result = core_dc->res_pool.funcs->validate_with_context(core_dc, set, target_count, context);
- 	if (result != DC_OK){
- 		BREAK_TO_DEBUGGER();
--		val_ctx_destruct(context);
-+		resource_validate_ctx_destruct(context);
- 		goto fail;
- 	}
- 
-@@ -699,7 +834,7 @@ bool dc_commit_targets(
- 
- 	pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg);
- 
--	val_ctx_destruct(&core_dc->current_context);
-+	resource_validate_ctx_destruct(&core_dc->current_context);
- 
- 	core_dc->current_context = *context;
- 
-@@ -730,7 +865,7 @@ bool dc_commit_surfaces_to_target(
- 
- 	context = dm_alloc(sizeof(struct validate_context));
- 
--	val_ctx_copy_construct(&core_dc->current_context, context);
-+	resource_validate_ctx_copy_construct(&core_dc->current_context, context);
- 
- 	/* Cannot commit surface to a target that is not commited */
- 	for (i = 0; i < context->target_count; i++)
-@@ -773,7 +908,7 @@ bool dc_commit_surfaces_to_target(
- 				dc_target);
- 
- 
--	if (!attach_surfaces_to_context(
-+	if (!resource_attach_surfaces_to_context(
- 			new_surfaces, new_surface_count, dc_target, context)) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
-@@ -785,7 +920,7 @@ bool dc_commit_surfaces_to_target(
- 					DC_SURFACE_TO_CORE(new_surfaces[i]))
- 				continue;
- 
--			build_scaling_params(
-+			resource_build_scaling_params(
- 				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
- 		}
- 
-@@ -856,14 +991,14 @@ bool dc_commit_surfaces_to_target(
- 						&context->pp_display_cfg);
- 	}
- 
--	val_ctx_destruct(&(core_dc->current_context));
-+	resource_validate_ctx_destruct(&(core_dc->current_context));
- 	core_dc->current_context = *context;
- 	dm_free(context);
- 	return true;
- 
- unexpected_fail:
- 
--	val_ctx_destruct(context);
-+	resource_validate_ctx_destruct(context);
- 
- 	dm_free(context);
- 	return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index f5bfaf3..0414f3e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -66,7 +66,7 @@ bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 	return false;
- }
- 
--void unreference_clock_source(
-+void resource_unreference_clock_source(
- 		struct resource_context *res_ctx,
- 		struct clock_source *clock_source)
- {
-@@ -91,7 +91,7 @@ void unreference_clock_source(
- 	}
- }
- 
--void reference_clock_source(
-+void resource_reference_clock_source(
- 		struct resource_context *res_ctx,
- 		struct clock_source *clock_source)
- {
-@@ -108,7 +108,7 @@ void reference_clock_source(
- 		res_ctx->dp_clock_source_ref_count++;
- }
- 
--bool is_same_timing(
-+bool resource_is_same_timing(
- 	const struct dc_crtc_timing *timing1,
- 	const struct dc_crtc_timing *timing2)
- {
-@@ -136,7 +136,7 @@ static bool is_sharable_clk_src(
- 	if (dc_is_dp_signal(pipe_with_clk_src->signal))
- 		return false;
- 
--	if(!is_same_timing(
-+	if (!resource_is_same_timing(
- 		&pipe_with_clk_src->stream->public.timing,
- 		&pipe->stream->public.timing))
- 		return false;
-@@ -144,7 +144,7 @@ static bool is_sharable_clk_src(
- 	return true;
- }
- 
--struct clock_source *find_used_clk_src_for_sharing(
-+struct clock_source *resource_find_used_clk_src_for_sharing(
- 					struct resource_context *res_ctx,
- 					struct pipe_ctx *pipe_ctx)
- {
-@@ -313,7 +313,7 @@ static void calculate_scaling_ratios(
- 	}
- }
- 
--void build_scaling_params(
-+void resource_build_scaling_params(
- 	const struct dc_surface *surface,
- 	struct pipe_ctx *pipe_ctx)
- {
-@@ -372,7 +372,8 @@ void build_scaling_params(
- 				surface->dst_rect.y);
- }
- 
--void build_scaling_params_for_context(
-+
-+void resource_build_scaling_params_for_context(
- 	const struct core_dc *dc,
- 	struct validate_context *context)
- {
-@@ -381,13 +382,13 @@ void build_scaling_params_for_context(
- 	for (i = 0; i < MAX_PIPES; i++) {
- 		if (context->res_ctx.pipe_ctx[i].surface != NULL &&
- 				context->res_ctx.pipe_ctx[i].stream != NULL)
--			build_scaling_params(
-+			resource_build_scaling_params(
- 				&context->res_ctx.pipe_ctx[i].surface->public,
- 				&context->res_ctx.pipe_ctx[i]);
- 	}
- }
- 
--bool attach_surfaces_to_context(
-+bool resource_attach_surfaces_to_context(
- 		struct dc_surface *surfaces[],
- 		uint8_t surface_count,
- 		struct dc_target *dc_target,
-@@ -453,140 +454,6 @@ bool attach_surfaces_to_context(
- 	return true;
- }
- 
--static uint32_t get_min_vblank_time_us(const struct validate_context *context)
--{
--	uint8_t i, j;
--	uint32_t min_vertical_blank_time = -1;
--
--	for (i = 0; i < context->target_count; i++) {
--		const struct core_target *target = context->targets[i];
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			const struct dc_stream *stream =
--						target->public.streams[j];
--			uint32_t vertical_blank_in_pixels = 0;
--			uint32_t vertical_blank_time = 0;
--
--			vertical_blank_in_pixels = stream->timing.h_total *
--				(stream->timing.v_total
--					- stream->timing.v_addressable);
--			vertical_blank_time = vertical_blank_in_pixels
--				* 1000 / stream->timing.pix_clk_khz;
--			if (min_vertical_blank_time > vertical_blank_time)
--				min_vertical_blank_time = vertical_blank_time;
--		}
--	}
--	return min_vertical_blank_time;
--}
--
--static void fill_display_configs(
--	const struct validate_context *context,
--	struct dm_pp_display_configuration *pp_display_cfg)
--{
--	uint8_t i, j, k;
--	uint8_t num_cfgs = 0;
--
--	for (i = 0; i < context->target_count; i++) {
--		const struct core_target *target = context->targets[i];
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			const struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--			struct dm_pp_single_disp_config *cfg =
--					&pp_display_cfg->disp_configs[num_cfgs];
--			const struct pipe_ctx *pipe_ctx = NULL;
--
--			for (k = 0; k < MAX_PIPES; k++)
--				if (stream ==
--					context->res_ctx.pipe_ctx[k].stream) {
--					pipe_ctx = &context->res_ctx.pipe_ctx[k];
--					break;
--				}
--
--			num_cfgs++;
--			cfg->signal = pipe_ctx->signal;
--			cfg->pipe_idx = pipe_ctx->pipe_idx;
--			cfg->src_height = stream->public.src.height;
--			cfg->src_width = stream->public.src.width;
--			cfg->ddi_channel_mapping =
--				stream->sink->link->ddi_channel_mapping.raw;
--			cfg->transmitter =
--				stream->sink->link->link_enc->transmitter;
--			cfg->link_settings.lane_count = stream->sink->link->public.cur_link_settings.lane_count;
--			cfg->link_settings.link_rate = stream->sink->link->public.cur_link_settings.link_rate;
--			cfg->link_settings.link_spread = stream->sink->link->public.cur_link_settings.link_spread;
--			cfg->sym_clock = stream->public.timing.pix_clk_khz;
--			switch (stream->public.timing.display_color_depth) {
--			case COLOR_DEPTH_101010:
--				cfg->sym_clock = (cfg->sym_clock * 30) / 24;
--				break;
--			case COLOR_DEPTH_121212:
--				cfg->sym_clock = (cfg->sym_clock * 36) / 24;
--				break;
--			case COLOR_DEPTH_161616:
--				cfg->sym_clock = (cfg->sym_clock * 48) / 24;
--				break;
--			default:
--				break;
--			}
--			/* TODO: unhardcode*/
--			cfg->v_refresh = 60;
--		}
--	}
--	pp_display_cfg->display_count = num_cfgs;
--}
--
--void pplib_apply_safe_state(
--	const struct core_dc *dc)
--{
--	dm_pp_apply_safe_state(dc->ctx);
--}
--
--void pplib_apply_display_requirements(
--	const struct core_dc *dc,
--	const struct validate_context *context,
--	struct dm_pp_display_configuration *pp_display_cfg)
--{
--
--	pp_display_cfg->all_displays_in_sync =
--		context->bw_results.all_displays_in_sync;
--	pp_display_cfg->nb_pstate_switch_disable =
--			context->bw_results.nbp_state_change_enable == false;
--	pp_display_cfg->cpu_cc6_disable =
--			context->bw_results.cpuc_state_change_enable == false;
--	pp_display_cfg->cpu_pstate_disable =
--			context->bw_results.cpup_state_change_enable == false;
--	pp_display_cfg->cpu_pstate_separation_time =
--			context->bw_results.required_blackout_duration_us;
--
--	pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
--		/ MEMORY_TYPE_MULTIPLIER;
--	pp_display_cfg->min_engine_clock_khz = context->bw_results.required_sclk;
--	pp_display_cfg->min_engine_clock_deep_sleep_khz
--			= context->bw_results.required_sclk_deep_sleep;
--
--	pp_display_cfg->avail_mclk_switch_time_us =
--						get_min_vblank_time_us(context);
--	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
--
--	pp_display_cfg->disp_clk_khz = context->bw_results.dispclk_khz;
--
--	fill_display_configs(context, pp_display_cfg);
--
--	/* TODO: is this still applicable?*/
--	if (pp_display_cfg->display_count == 1) {
--		const struct dc_crtc_timing *timing =
--			&context->targets[0]->public.streams[0]->timing;
--
--		pp_display_cfg->crtc_index =
--			pp_display_cfg->disp_configs[0].pipe_idx;
--		pp_display_cfg->line_time_in_us = timing->h_total * 1000
--							/ timing->pix_clk_khz;
--	}
--
--	dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
--}
--
- /* Maximum TMDS single link pixel clock 165MHz */
- #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
- 
-@@ -704,7 +571,7 @@ static bool check_timing_change(struct core_stream *cur_stream,
- 	if (cur_stream->sink != new_stream->sink)
- 		return true;
- 
--	return !is_same_timing(
-+	return !resource_is_same_timing(
- 					&cur_stream->public.timing,
- 					&new_stream->public.timing);
- }
-@@ -741,7 +608,7 @@ static void set_stream_signal(struct pipe_ctx *pipe_ctx)
- 		pipe_ctx->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- }
- 
--enum dc_status map_resources(
-+enum dc_status resource_map_pool_resources(
- 		const struct core_dc *dc,
- 		struct validate_context *context)
- {
-@@ -775,7 +642,7 @@ enum dc_status map_resources(
- 					&context->res_ctx,
- 					pipe_ctx->stream_enc);
- 
--				reference_clock_source(
-+				resource_reference_clock_source(
- 					&context->res_ctx,
- 					pipe_ctx->clock_source);
- 
-@@ -1251,7 +1118,7 @@ static void set_vendor_info_packet(struct core_stream *stream,
- 	info_packet->valid = true;
- }
- 
--void val_ctx_destruct(struct validate_context *context)
-+void resource_validate_ctx_destruct(struct validate_context *context)
- {
- 	int i, j;
- 
-@@ -1269,7 +1136,7 @@ void val_ctx_destruct(struct validate_context *context)
-  * Copy src_ctx into dst_ctx and retain all surfaces and targets referenced
-  * by the src_ctx
-  */
--void val_ctx_copy_construct(
-+void resource_validate_ctx_copy_construct(
- 		const struct validate_context *src_ctx,
- 		struct validate_context *dst_ctx)
- {
-@@ -1298,7 +1165,7 @@ struct clock_source *dc_resource_find_first_free_pll(
- 	return NULL;
- }
- 
--void build_info_frame(struct pipe_ctx *pipe_ctx)
-+void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
- {
- 	enum signal_type signal = SIGNAL_TYPE_NONE;
- 	struct hw_info_frame info_frame = { { 0 } };
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 03a5ab0..f6b9cb8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -749,7 +749,7 @@ static enum dc_status validate_mapped_resource(
- 				if (status != DC_OK)
- 					return status;
- 
--				build_info_frame(pipe_ctx);
-+				resource_build_info_frame(pipe_ctx);
- 
- 				/* do not need to validate non root pipes */
- 				break;
-@@ -823,7 +823,7 @@ static enum dc_status map_clock_resources(
- 						context->res_ctx.pool.dp_clock_source;
- 				else {
- 					pipe_ctx->clock_source =
--						find_used_clk_src_for_sharing(
-+						resource_find_used_clk_src_for_sharing(
- 							&context->res_ctx,
- 							pipe_ctx);
- 
-@@ -835,7 +835,7 @@ static enum dc_status map_clock_resources(
- 				if (pipe_ctx->clock_source == NULL)
- 					return DC_NO_CLOCK_SOURCE_RESOURCE;
- 
--				reference_clock_source(
-+				resource_reference_clock_source(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
-@@ -870,7 +870,7 @@ enum dc_status dce100_validate_with_context(
- 						== context->targets[i]) {
- 				unchanged = true;
- 				set_target_unchanged(context, i);
--				attach_surfaces_to_context(
-+				resource_attach_surfaces_to_context(
- 					(struct dc_surface **)dc->current_context.
- 						target_status[j].surfaces,
- 					dc->current_context.target_status[j].surface_count,
-@@ -880,7 +880,7 @@ enum dc_status dce100_validate_with_context(
- 					dc->current_context.target_status[j];
- 			}
- 		if (!unchanged || set[i].surface_count != 0)
--			if (!attach_surfaces_to_context(
-+			if (!resource_attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
- 					&context->targets[i]->public,
-@@ -892,7 +892,7 @@ enum dc_status dce100_validate_with_context(
- 
- 	context->res_ctx.pool = dc->res_pool;
- 
--	result = map_resources(dc, context);
-+	result = resource_map_pool_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = map_clock_resources(dc, context);
-@@ -901,7 +901,7 @@ enum dc_status dce100_validate_with_context(
- 		result = validate_mapped_resource(dc, context);
- 
- 	if (result == DC_OK)
--		build_scaling_params_for_context(dc, context);
-+		resource_build_scaling_params_for_context(dc, context);
- 
- 	if (result == DC_OK)
- 		result = dce100_validate_bandwidth(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 0513731..1b49201 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -794,7 +794,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 			core_link_disable_stream(old_pipe_ctx);
- 
- 			ASSERT(old_pipe_ctx->clock_source);
--			unreference_clock_source(&dc->current_context.res_ctx, old_pipe_ctx->clock_source);
-+			resource_unreference_clock_source(&dc->current_context.res_ctx, old_pipe_ctx->clock_source);
- 		}
- 
- 		/*TODO: AUTO check if timing changed*/
-@@ -1211,15 +1211,15 @@ static void switch_dp_clock_sources(
- 
- 		if (dc_is_dp_signal(pipe_ctx->signal)) {
- 			struct clock_source *clk_src =
--				find_used_clk_src_for_sharing(
-+				resource_find_used_clk_src_for_sharing(
- 						res_ctx, pipe_ctx);
- 
- 			if (clk_src &&
- 				clk_src != pipe_ctx->clock_source) {
--				unreference_clock_source(
-+				resource_unreference_clock_source(
- 					res_ctx, pipe_ctx->clock_source);
- 				pipe_ctx->clock_source = clk_src;
--				reference_clock_source(res_ctx, clk_src);
-+				resource_reference_clock_source(res_ctx, clk_src);
- 				dc->hwss.crtc_switch_to_clk_src(clk_src, i);
- 			}
- 		}
-@@ -1472,7 +1472,7 @@ static void reset_single_pipe_hw_ctx(
- 	pipe_ctx->mi->funcs->free_mem_input(
- 				pipe_ctx->mi, context->target_count);
- 	pipe_ctx->xfm->funcs->transform_set_scaler_bypass(pipe_ctx->xfm);
--	unreference_clock_source(&context->res_ctx, pipe_ctx->clock_source);
-+	resource_unreference_clock_source(&context->res_ctx, pipe_ctx->clock_source);
- 	dc->hwss.enable_display_power_gating(
- 		pipe_ctx->stream->ctx, pipe_ctx->pipe_idx, dcb,
- 			PIPE_GATING_CONTROL_ENABLE);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index cde8d64..66b7014 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -713,7 +713,7 @@ static enum dc_status validate_mapped_resource(
- 				if (status != DC_OK)
- 					return status;
- 
--				build_info_frame(pipe_ctx);
-+				resource_build_info_frame(pipe_ctx);
- 
- 				/* do not need to validate non root pipes */
- 				break;
-@@ -945,7 +945,7 @@ static enum dc_status map_clock_resources(
- 						context->res_ctx.pool.dp_clock_source;
- 				else {
- 					pipe_ctx->clock_source =
--						find_used_clk_src_for_sharing(
-+						resource_find_used_clk_src_for_sharing(
- 							&context->res_ctx, pipe_ctx);
- 
- 					if (pipe_ctx->clock_source == NULL)
-@@ -956,7 +956,7 @@ static enum dc_status map_clock_resources(
- 				if (pipe_ctx->clock_source == NULL)
- 					return DC_NO_CLOCK_SOURCE_RESOURCE;
- 
--				reference_clock_source(
-+				resource_reference_clock_source(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
-@@ -991,7 +991,7 @@ enum dc_status dce110_validate_with_context(
- 						== context->targets[i]) {
- 				unchanged = true;
- 				set_target_unchanged(context, i);
--				attach_surfaces_to_context(
-+				resource_attach_surfaces_to_context(
- 					(struct dc_surface **)dc->current_context.
- 						target_status[j].surfaces,
- 					dc->current_context.target_status[j].surface_count,
-@@ -1001,7 +1001,7 @@ enum dc_status dce110_validate_with_context(
- 					dc->current_context.target_status[j];
- 			}
- 		if (!unchanged || set[i].surface_count != 0)
--			if (!attach_surfaces_to_context(
-+			if (!resource_attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
- 					&context->targets[i]->public,
-@@ -1013,7 +1013,7 @@ enum dc_status dce110_validate_with_context(
- 
- 	context->res_ctx.pool = dc->res_pool;
- 
--	result = map_resources(dc, context);
-+	result = resource_map_pool_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = map_clock_resources(dc, context);
-@@ -1022,7 +1022,7 @@ enum dc_status dce110_validate_with_context(
- 		result = validate_mapped_resource(dc, context);
- 
- 	if (result == DC_OK)
--		build_scaling_params_for_context(dc, context);
-+		resource_build_scaling_params_for_context(dc, context);
- 
- 	if (result == DC_OK)
- 		result = dce110_validate_bandwidth(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index fd97afe..864f32a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -703,7 +703,7 @@ static enum dc_status validate_mapped_resource(
- 				if (status != DC_OK)
- 					return status;
- 
--				build_info_frame(pipe_ctx);
-+				resource_build_info_frame(pipe_ctx);
- 
- 				/* do not need to validate non root pipes */
- 				break;
-@@ -934,7 +934,7 @@ static enum dc_status map_clock_resources(
- 					pipe_ctx->clock_source = context->res_ctx.pool.dp_clock_source;
- 				else {
- 					pipe_ctx->clock_source =
--						find_used_clk_src_for_sharing(
-+						resource_find_used_clk_src_for_sharing(
- 							&context->res_ctx, pipe_ctx);
- 
- 					if (pipe_ctx->clock_source == NULL)
-@@ -945,7 +945,7 @@ static enum dc_status map_clock_resources(
- 				if (pipe_ctx->clock_source == NULL)
- 					return DC_NO_CLOCK_SOURCE_RESOURCE;
- 
--				reference_clock_source(
-+				resource_reference_clock_source(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
-@@ -980,7 +980,7 @@ enum dc_status dce80_validate_with_context(
- 						== context->targets[i]) {
- 				unchanged = true;
- 				set_target_unchanged(context, i);
--				attach_surfaces_to_context(
-+				resource_attach_surfaces_to_context(
- 					(struct dc_surface **)dc->current_context.
- 						target_status[j].surfaces,
- 					dc->current_context.target_status[j].surface_count,
-@@ -990,7 +990,7 @@ enum dc_status dce80_validate_with_context(
- 					dc->current_context.target_status[j];
- 			}
- 		if (!unchanged || set[i].surface_count != 0)
--			if (!attach_surfaces_to_context(
-+			if (!resource_attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
- 					&context->targets[i]->public,
-@@ -1002,7 +1002,7 @@ enum dc_status dce80_validate_with_context(
- 
- 	context->res_ctx.pool = dc->res_pool;
- 
--	result = map_resources(dc, context);
-+	result = resource_map_pool_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = map_clock_resources(dc, context);
-@@ -1011,7 +1011,7 @@ enum dc_status dce80_validate_with_context(
- 		result = validate_mapped_resource(dc, context);
- 
- 	if (result == DC_OK)
--		build_scaling_params_for_context(dc, context);
-+		resource_build_scaling_params_for_context(dc, context);
- 
- 	if (result == DC_OK)
- 		result = dce80_validate_bandwidth(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 6991c3e..0836e41 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -37,56 +37,50 @@ bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 				struct core_dc *dc,
- 				uint8_t num_virtual_links);
- 
--void build_scaling_params(
-+enum dc_status resource_map_pool_resources(
-+	const struct core_dc *dc,
-+	struct validate_context *context);
-+
-+void resource_build_scaling_params(
- 	const struct dc_surface *surface,
- 	struct pipe_ctx *pipe_ctx);
- 
--void build_scaling_params_for_context(
-+void resource_build_scaling_params_for_context(
- 	const struct core_dc *dc,
- 	struct validate_context *context);
- 
--void unreference_clock_source(
-+void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
-+
-+void resource_unreference_clock_source(
- 		struct resource_context *res_ctx,
- 		struct clock_source *clock_source);
- 
--void reference_clock_source(
-+void resource_reference_clock_source(
- 		struct resource_context *res_ctx,
- 		struct clock_source *clock_source);
- 
--bool is_same_timing(
-+bool resource_is_same_timing(
- 	const struct dc_crtc_timing *timing1,
- 	const struct dc_crtc_timing *timing2);
- 
--struct clock_source *find_used_clk_src_for_sharing(
-+struct clock_source *resource_find_used_clk_src_for_sharing(
- 	struct resource_context *res_ctx,
- 	struct pipe_ctx *pipe_ctx);
- 
- struct clock_source *dc_resource_find_first_free_pll(
- 		struct resource_context *res_ctx);
- 
--bool attach_surfaces_to_context(
-+bool resource_attach_surfaces_to_context(
- 		struct dc_surface *surfaces[],
- 		uint8_t surface_count,
- 		struct dc_target *dc_target,
- 		struct validate_context *context);
- 
--void pplib_apply_safe_state(const struct core_dc *dc);
--
--void pplib_apply_display_requirements(
--	const struct core_dc *dc,
--	const struct validate_context *context,
--	struct dm_pp_display_configuration *pp_display_cfg);
--
--void build_info_frame(struct pipe_ctx *pipe_ctx);
--
--enum dc_status map_resources(
--	const struct core_dc *dc,
--	struct validate_context *context);
--
--void val_ctx_destruct(struct validate_context *context);
--
--void val_ctx_copy_construct(
-+void resource_validate_ctx_copy_construct(
- 	const struct validate_context *src_ctx,
- 	struct validate_context *dst_ctx);
- 
-+void resource_validate_ctx_destruct(struct validate_context *context);
-+
-+
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0870-drm-amd-dal-remove-unused-type-ovl_csc_adjustment.patch b/common/recipes-kernel/linux/files/0870-drm-amd-dal-remove-unused-type-ovl_csc_adjustment.patch
deleted file mode 100644
index 7b81514a..00000000
--- a/common/recipes-kernel/linux/files/0870-drm-amd-dal-remove-unused-type-ovl_csc_adjustment.patch
+++ /dev/null
@@ -1,112 +0,0 @@
-From 8a33d2b27da7b9e6081ac603fe8e2d7770344a06 Mon Sep 17 00:00:00 2001
-From: Tony Cheng <Tony.Cheng@amd.com>
-Date: Sat, 27 Feb 2016 17:33:12 -0500
-Subject: [PATCH 0870/1110] drm/amd/dal: remove unused type ovl_csc_adjustment
-
-Signed-off-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h          | 44 +++++++++++------------
- drivers/gpu/drm/amd/dal/include/video_csc_types.h | 25 -------------
- 2 files changed, 22 insertions(+), 47 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index 03b95e9..bfe9955 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -158,6 +158,28 @@ enum surface_pixel_format {
- 	/*grow 444 video here if necessary */
- };
- 
-+/* Pixel format */
-+enum pixel_format {
-+	/*graph*/
-+	PIXEL_FORMAT_UNINITIALIZED,
-+	PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_RGB565,
-+	PIXEL_FORMAT_ARGB8888,
-+	PIXEL_FORMAT_ARGB2101010,
-+	PIXEL_FORMAT_ARGB2101010_XRBIAS,
-+	PIXEL_FORMAT_FP16,
-+	/*video*/
-+	PIXEL_FORMAT_420BPP12,
-+	/*end of pixel format definition*/
-+	PIXEL_FORMAT_INVALID,
-+
-+	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
-+	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
-+	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP12,
-+	PIXEL_FORMAT_UNKNOWN
-+};
-+
- enum tile_split_values {
- 	DC_DISPLAY_MICRO_TILING = 0x0,
- 	DC_THIN_MICRO_TILING = 0x1,
-@@ -321,28 +343,6 @@ struct dc_cursor_attributes {
- 	union dc_cursor_attribute_flags attribute_flags;
- };
- 
--/* Pixel format */
--enum pixel_format {
--	/*graph*/
--	PIXEL_FORMAT_UNINITIALIZED,
--	PIXEL_FORMAT_INDEX8,
--	PIXEL_FORMAT_RGB565,
--	PIXEL_FORMAT_ARGB8888,
--	PIXEL_FORMAT_ARGB2101010,
--	PIXEL_FORMAT_ARGB2101010_XRBIAS,
--	PIXEL_FORMAT_FP16,
--	/*video*/
--	PIXEL_FORMAT_420BPP12,
--	/*end of pixel format definition*/
--	PIXEL_FORMAT_INVALID,
--
--	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
--	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
--	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
--	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP12,
--	PIXEL_FORMAT_UNKNOWN
--};
--
- /* OPP */
- enum dc_pixel_encoding {
- 	PIXEL_ENCODING_UNDEFINED,
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index 58dcc04..85619fc 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -81,30 +81,5 @@ union ovl_csc_flag {
- 	} bits;
- };
- 
--struct ovl_csc_adjustment {
--	struct ovl_color_adjust_option ovl_option;
--	enum dc_color_depth display_color_depth;
--	uint32_t lb_color_depth;
--	enum pixel_format desktop_surface_pixel_format;
--	enum ovl_surface_format ovl_sf;
--	/* API adjustment */
--	struct overlay_adjust_item overlay_brightness;
--	struct overlay_adjust_item overlay_gamma;
--	struct overlay_adjust_item overlay_contrast;
--	struct overlay_adjust_item overlay_saturation;
--	struct overlay_adjust_item overlay_hue; /* unit in degree from API. */
--	int32_t f_temperature[TEMPERATURE_MATRIX_SIZE];
--	uint32_t temperature_divider;
--	/* OEM/Application matrix related. */
--	int32_t matrix[MAXTRIX_SIZE_WITH_OFFSET];
--	uint32_t matrix_divider;
--
--	/* DCE50 parameters */
--	enum overlay_gamma_adjust adjust_gamma_type;
--	enum overlay_csc_adjust_type adjust_csc_type;
--	enum overlay_gamut_adjust_type adjust_gamut_type;
--	union ovl_csc_flag flag;
--
--};
- 
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0871-drm-amd-dal-Remove-unnecessary-SIGTRAP.patch b/common/recipes-kernel/linux/files/0871-drm-amd-dal-Remove-unnecessary-SIGTRAP.patch
deleted file mode 100644
index 86d84104..00000000
--- a/common/recipes-kernel/linux/files/0871-drm-amd-dal-Remove-unnecessary-SIGTRAP.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From ec9c37970569976638e1ac882230a26366b09849 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 26 Feb 2016 17:30:32 -0500
-Subject: [PATCH 0871/1110] drm/amd/dal: Remove unnecessary SIGTRAP
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 7 -------
- 1 file changed, 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 0414f3e..917e6a5 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -438,13 +438,6 @@ bool resource_attach_surfaces_to_context(
- 			if (context->res_ctx.pipe_ctx[j].stream !=
- 				DC_STREAM_TO_CORE(dc_target->streams[i]))
- 				continue;
--			if (k == surface_count) {
--				/* this means there are more pipes per stream
--				 * than there are planes and makes no sense
--				 */
--				BREAK_TO_DEBUGGER();
--				continue;
--			}
- 
- 			context->res_ctx.pipe_ctx[j].surface = surface;
- 			k++;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0872-drm-amd-dal-Fix-HSYNC-flip-for-DCE8-10.patch b/common/recipes-kernel/linux/files/0872-drm-amd-dal-Fix-HSYNC-flip-for-DCE8-10.patch
deleted file mode 100644
index 24f46f14..00000000
--- a/common/recipes-kernel/linux/files/0872-drm-amd-dal-Fix-HSYNC-flip-for-DCE8-10.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From d46934473c1409a1734828cc2d398e3970602831 Mon Sep 17 00:00:00 2001
-From: Aric Cyr <aric.cyr@amd.com>
-Date: Mon, 29 Feb 2016 12:05:52 -0500
-Subject: [PATCH 0872/1110] drm/amd/dal: Fix HSYNC flip for DCE8/10
-
-DCE8/DCE10 does not support immediate flip so must also program HSYNC
-flip bit.  Immediate flip takes precedence on DCE11+ so enabling it will
-not affect those ASICs.
-
-Signed-off-by: Aric Cyr <aric.cyr@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 136 +++++++--------------
- 1 file changed, 45 insertions(+), 91 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 30c6048..077278d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -40,64 +40,30 @@
- #define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
- #define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
- 
--static void set_flip_control(
--	struct dce110_mem_input *mem_input110,
--	bool immediate)
--{
--	uint32_t value = 0;
--
--	value = dm_read_reg(
--			mem_input110->base.ctx,
--			DCP_REG(mmGRPH_FLIP_CONTROL));
--	set_reg_field_value(value, 0,
--				GRPH_FLIP_CONTROL,
--				GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
--	set_reg_field_value(value, 0,
--				GRPH_FLIP_CONTROL,
--				GRPH_SURFACE_UPDATE_H_RETRACE_EN);
--	if (immediate == true)
--		set_reg_field_value(value, 1,
--			GRPH_FLIP_CONTROL,
--			GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
--
--	dm_write_reg(
--		mem_input110->base.ctx,
--		DCP_REG(mmGRPH_FLIP_CONTROL),
--		value);
--}
--
- static void program_sec_addr(
- 	struct dce110_mem_input *mem_input110,
- 	PHYSICAL_ADDRESS_LOC address)
- {
- 	uint32_t value = 0;
--	uint32_t temp = 0;
-+	uint32_t temp;
-+
- 	/*high register MUST be programmed first*/
- 	temp = address.high_part &
--GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
--
-+		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
- 	set_reg_field_value(value, temp,
- 		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
- 		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
-+	dm_write_reg(mem_input110->base.ctx,
-+				 DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH), value);
- 
--	dm_write_reg(
--			mem_input110->base.ctx,
--			DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH),
--			value);
--
--	temp = 0;
- 	value = 0;
- 	temp = address.low_part >>
--	GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
--
-+		GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
- 	set_reg_field_value(value, temp,
- 		GRPH_SECONDARY_SURFACE_ADDRESS,
- 		GRPH_SECONDARY_SURFACE_ADDRESS);
--
--	dm_write_reg(
--			mem_input110->base.ctx,
--			DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS),
--			value);
-+	dm_write_reg(mem_input110->base.ctx,
-+				 DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS), value);
- }
- 
- static void program_pri_addr(
-@@ -105,64 +71,25 @@ static void program_pri_addr(
- 	PHYSICAL_ADDRESS_LOC address)
- {
- 	uint32_t value = 0;
--	uint32_t temp = 0;
-+	uint32_t temp;
- 
- 	/*high register MUST be programmed first*/
- 	temp = address.high_part &
--GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
--
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
- 	set_reg_field_value(value, temp,
- 		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
- 		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH);
-+	dm_write_reg(mem_input110->base.ctx,
-+				 DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH), value);
- 
--	dm_write_reg(
--		mem_input110->base.ctx,
--		DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH),
--		value);
--
--	temp = 0;
- 	value = 0;
- 	temp = address.low_part >>
--	GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT;
--
-+		GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT;
- 	set_reg_field_value(value, temp,
- 		GRPH_PRIMARY_SURFACE_ADDRESS,
- 		GRPH_PRIMARY_SURFACE_ADDRESS);
--
--	dm_write_reg(
--		mem_input110->base.ctx,
--		DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS),
--		value);
--}
--
--static void program_addr(
--	struct dce110_mem_input *mem_input110,
--	const struct dc_plane_address *addr)
--{
--	switch (addr->type) {
--	case PLN_ADDR_TYPE_GRAPHICS:
--		if (addr->grph.addr.quad_part == 0)
--			break;
--		program_pri_addr(
--			mem_input110,
--			addr->grph.addr);
--		break;
--	case PLN_ADDR_TYPE_GRPH_STEREO:
--		if (addr->grph_stereo.left_addr.quad_part == 0
--			|| addr->grph_stereo.right_addr.quad_part == 0)
--			break;
--		program_pri_addr(
--			mem_input110,
--			addr->grph_stereo.left_addr);
--		program_sec_addr(
--			mem_input110,
--			addr->grph_stereo.right_addr);
--		break;
--	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
--	default:
--		/* not supported */
--		BREAK_TO_DEBUGGER();
--	}
-+	dm_write_reg(mem_input110->base.ctx,
-+				 DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS), value);
- }
- 
- static void enable(struct dce110_mem_input *mem_input110)
-@@ -439,9 +366,36 @@ bool dce110_mem_input_program_surface_flip_and_addr(
- {
- 	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- 
--	set_flip_control(mem_input110, flip_immediate);
--	program_addr(mem_input110,
--		address);
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL));
-+	if (flip_immediate) {
-+		set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
-+		set_reg_field_value(value, 1, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN);
-+	} else {
-+		set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
-+		set_reg_field_value(value, 0, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN);
-+	}
-+	dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_FLIP_CONTROL), value);
-+
-+	switch (address->type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		if (address->grph.addr.quad_part == 0)
-+			break;
-+		program_pri_addr(mem_input110, address->grph.addr);
-+		break;
-+	case PLN_ADDR_TYPE_GRPH_STEREO:
-+		if (address->grph_stereo.left_addr.quad_part == 0
-+			|| address->grph_stereo.right_addr.quad_part == 0)
-+			break;
-+		program_pri_addr(mem_input110, address->grph_stereo.left_addr);
-+		program_sec_addr(mem_input110, address->grph_stereo.right_addr);
-+		break;
-+	default:
-+		/* not supported */
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
- 
- 	return true;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch b/common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch
deleted file mode 100644
index 35dabb79..00000000
--- a/common/recipes-kernel/linux/files/0873-drm-amd-dal-Use-usleep-for-microsecond-sleep.patch
+++ /dev/null
@@ -1,600 +0,0 @@
-From 62a3999b85f0102a285a341b6121b3063079920f Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sat, 27 Feb 2016 16:04:29 -0500
-Subject: [PATCH 0873/1110] drm/amd/dal: Use usleep for microsecond sleep
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c |  5 ---
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c  |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  1 -
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  1 -
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |  2 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c  |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |  4 +--
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   |  4 +--
- .../drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c   |  2 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  |  6 ++--
- .../drm/amd/dal/dc/dce110/dce110_transform_scl.c   |  2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c    |  2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c |  2 +-
- .../drm/amd/dal/dc/dce80/dce80_stream_encoder.c    |  6 ++--
- .../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c |  2 +-
- drivers/gpu/drm/amd/dal/dc/dm_services.h           |  2 --
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c     |  6 ++--
- .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c   |  6 ++--
- .../drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c |  2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c     |  2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c  |  2 +-
- drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c  | 40 +++++++++++-----------
- 25 files changed, 50 insertions(+), 59 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index d0a17af..d89f9c4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -48,11 +48,6 @@ void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
- 		usleep_range(milliseconds*1000, milliseconds*1000+1);
- }
- 
--void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds)
--{
--	udelay(microseconds);
--}
--
- /******************************************************************************
-  * IRQ Interfaces.
-  *****************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-index 64d3dbf..d8a674d 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -891,7 +891,7 @@ static void enable_afmt_clock(
- 	 */
- 	do {
- 		/* Wait for 1us between subsequent register reads.*/
--		dm_delay_in_microseconds(hw_ctx->ctx, 1);
-+		udelay(1);
- 		value = dm_read_reg(hw_ctx->ctx,
- 				mmAFMT_CNTL + engine_offs);
- 	} while (get_reg_field_value(value,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index d547fb9..4a52d43 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -907,7 +907,6 @@ bool dc_commit_surfaces_to_target(
- 				new_surface_count,
- 				dc_target);
- 
--
- 	if (!resource_attach_surfaces_to_context(
- 			new_surfaces, new_surface_count, dc_target, context)) {
- 		BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 619e910..48e3e4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -79,7 +79,7 @@ static void wait_for_training_aux_rd_interval(
- 				training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
- 	}
- 
--	dm_delay_in_microseconds(link->ctx, default_wait_in_micro_secs);
-+	udelay(default_wait_in_micro_secs);
- 
- 	dal_logger_write(link->ctx->logger,
- 		LOG_MAJOR_HW_TRACE,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 44fe442..53bb64b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -124,7 +124,6 @@ struct dc_target *dc_create_target_for_streams(
- 
- 	return &target->protected.public;
- 
--
- target_alloc_fail:
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index c759081..0c17aa1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -213,7 +213,7 @@ static bool dce100_pipe_control_lock(
- 				break;
- 
- 			counter++;
--			dm_delay_in_microseconds(ctx, delay_us);
-+			udelay(delay_us);
- 		}
- 
- 		if (counter == counter_limit) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-index 5b55ce8..7a647cd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
-@@ -317,7 +317,7 @@ static void wait_for_fbc_state_changed(
- 			FBC_STATUS,
- 			FBC_ENABLE_STATUS) == enabled)
- 			break;
--		dm_delay_in_microseconds(cp110->base.ctx, 10);
-+		udelay(10);
- 		counter++;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 1b49201..e6d1c3a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -323,7 +323,7 @@ static bool dce110_pipe_control_lock(
- 				break;
- 
- 			counter++;
--			dm_delay_in_microseconds(ctx, delay_us);
-+			udelay(delay_us);
- 		}
- 
- 		if (counter == counter_limit) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 9efed4f..71ef1de 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -1738,7 +1738,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
- 	 * after this bit is cleared */
- 
- 	do {
--		dm_delay_in_microseconds(ctx, 10);
-+		udelay(10);
- 
- 		value0 = dm_read_reg(ctx,
- 				LINK_REG(DP_MSE_SAT_UPDATE));
-@@ -1889,7 +1889,7 @@ void dce110_link_encoder_set_lcd_backlight_level(
- 			BL_PWM_GRP1_REG_UPDATE_PENDING))
- 			break;
- 
--		dm_delay_in_microseconds(ctx, 10);
-+		udelay(10);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 077278d..e7fc5bd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -744,7 +744,7 @@ void dce110_allocate_mem_input(
- 		if (field)
- 			break;
- 
--		dm_delay_in_microseconds(mi->ctx, retry_delay);
-+		udelay(retry_delay);
- 		retry_count--;
- 
- 	} while (retry_count > 0);
-@@ -815,7 +815,7 @@ static void deallocate_dmif_buffer_helper(
- 
- 	do {
- 		value = dm_read_reg(ctx, mmPIPE0_DMIF_BUFFER_CONTROL + offset);
--		dm_delay_in_microseconds(ctx, 10);
-+		udelay(10);
- 		count--;
- 	} while (count > 0 &&
- 		!get_reg_field_value(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-index 0004c9e..3b3a917 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma_v.c
-@@ -78,7 +78,7 @@ static void power_on_lut(struct output_pixel_processor *opp,
- 					COL_MAN_GAMMA_CORR_MEM_PWR_DIS))
- 			break;
- 
--		dm_delay_in_microseconds(opp->ctx, 2);
-+		udelay(2);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index 2107309..dcca860 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -682,7 +682,7 @@ void dce110_stream_encoder_set_mst_bandwidth(
- 			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
- 				break;
- 
--			dm_delay_in_microseconds(ctx, 10);
-+			udelay(10);
- 
- 			++retries;
- 		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-@@ -1017,7 +1017,7 @@ void dce110_stream_encoder_dp_blank(
- 			DP_VID_STREAM_STATUS))
- 			break;
- 
--		dm_delay_in_microseconds(ctx, 10);
-+		udelay(10);
- 
- 		++retries;
- 	} while (retries < max_retries);
-@@ -1102,7 +1102,7 @@ void dce110_stream_encoder_dp_unblank(
- 	/* wait 100us for DIG/DP logic to prime
- 	* (i.e. a few video lines)
- 	*/
--	dm_delay_in_microseconds(ctx, 100);
-+	udelay(100);
- 
- 	/* the hardware would start sending video at the start of the next DP
- 	* frame (i.e. rising edge of the vblank).
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index f8376f8..65f9e01 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -244,7 +244,7 @@ static void program_filter(
- 			DCFE_MEM_PWR_STATUS,
- 			SCL_COEFF_MEM_PWR_STATE);
- 		i++)
--		dm_delay_in_microseconds(xfm110->base.ctx, 1);
-+		udelay(1);
- 
- 	ASSERT(i < 10);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-index d7d0088..dc008e7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
-@@ -329,7 +329,7 @@ static void wait_for_fbc_state_changed(
- 			FBC_STATUS,
- 			FBC_ENABLE_STATUS) == enabled)
- 			break;
--		dm_delay_in_microseconds(cp80->base.ctx, 10);
-+		udelay(10);
- 		counter++;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-index ef55de3..caec585 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -201,7 +201,7 @@ static bool dce80_pipe_control_lock(
- 				break;
- 
- 			counter++;
--			dm_delay_in_microseconds(ctx, delay_us);
-+			udelay(delay_us);
- 		}
- 
- 		if (counter == counter_limit) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-index d9bc223..c73c118 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
-@@ -137,7 +137,7 @@ static void allocate_mem_input(
- 		if (field)
- 			break;
- 
--		dm_delay_in_microseconds(mi->ctx, retry_delay);
-+		udelay(retry_delay);
- 		retry_count--;
- 
- 	} while (retry_count > 0);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-index d45a1e4..f0a7ee1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-@@ -658,7 +658,7 @@ void dce80_stream_encoder_set_mst_bandwidth(
- 			DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
- 				break;
- 
--			dm_delay_in_microseconds(ctx, 10);
-+			udelay(10);
- 
- 			++retries;
- 		} while (retries < DP_MST_UPDATE_MAX_RETRY);
-@@ -998,7 +998,7 @@ void dce80_stream_encoder_dp_blank(
- 			DP_VID_STREAM_STATUS))
- 			break;
- 
--		dm_delay_in_microseconds(ctx, 10);
-+		udelay(10);
- 
- 		++retries;
- 	} while (retries < max_retries);
-@@ -1083,7 +1083,7 @@ void dce80_stream_encoder_dp_unblank(
- 	/* wait 100us for DIG/DP logic to prime
- 	* (i.e. a few video lines)
- 	*/
--	dm_delay_in_microseconds(ctx, 100);
-+	udelay(100);
- 
- 	/* the hardware would start sending video at the start of the next DP
- 	* frame (i.e. rising edge of the vblank).
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-index c9b3af5..0025e05 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-@@ -246,7 +246,7 @@ static void program_filter(
- 			DCFE_MEM_LIGHT_SLEEP_CNTL,
- 			SCL_MEM_PWR_STATE);
- 		i++)
--		dm_delay_in_microseconds(xfm80->base.ctx, 1);
-+		udelay(1);
- 
- 	ASSERT(i < 10);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 8acdcd4..bf315ac 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -257,8 +257,6 @@ bool dm_pp_apply_display_requirements(
- 
- void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
- 
--void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds);
--
- enum platform_method {
- 	PM_GET_AVAILABLE_METHODS = 1 << 0,
- 	PM_GET_LID_STATE = 1 << 1,
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-index 725e183..a281dc0 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-@@ -203,7 +203,7 @@ static void process_read_request(
- 				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- 			ctx->operation_succeeded = false;
- 		} else
--			dm_delay_in_microseconds(engine->base.ctx, 400);
-+			udelay(400);
- 	break;
- 	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
- 		++ctx->timed_out_retry_aux;
-@@ -330,7 +330,7 @@ static void process_write_reply(
- 				I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- 				ctx->operation_succeeded = false;
- 			} else
--				dm_delay_in_microseconds(engine->base.ctx, 300);
-+				udelay(300);
- 		} else {
- 			ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- 			ctx->defer_retry_aux = 0;
-@@ -401,7 +401,7 @@ static void process_write_request(
- 				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- 			ctx->operation_succeeded = false;
- 		} else
--			dm_delay_in_microseconds(engine->base.ctx, 400);
-+			udelay(400);
- 	break;
- 	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
- 		++ctx->timed_out_retry_aux;
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-index d2f49b8..8a23528 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
-@@ -137,7 +137,7 @@ static bool acquire_engine(
- 
- 			/*poll HW to make sure reset it done*/
- 			do {
--				dm_delay_in_microseconds(engine->base.ctx, 1);
-+				udelay(1);
- 
- 				value = dm_read_reg(engine->base.ctx, addr);
- 
-@@ -161,7 +161,7 @@ static bool acquire_engine(
- 			counter = 0;
- 
- 			do {
--				dm_delay_in_microseconds(engine->base.ctx, 1);
-+				udelay(1);
- 
- 				value = dm_read_reg(engine->base.ctx, addr);
- 
-@@ -640,7 +640,7 @@ static enum aux_channel_operation_result get_channel_status(
- 			if (aux_sw_done)
- 				break;
- 
--			dm_delay_in_microseconds(engine->base.ctx, 10);
-+			udelay(10);
- 
- 			time_elapsed += 10;
- 		} while (time_elapsed < aux_engine->timeout_period);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-index b732860..4b81f67 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/aux_engine_dce80.c
-@@ -593,7 +593,7 @@ static enum aux_channel_operation_result get_channel_status(
- 			if (aux_sw_done)
- 				break;
- 
--			dm_delay_in_microseconds(engine->base.ctx, 10);
-+			udelay(10);
- 
- 			time_elapsed += 10;
- 		} while (time_elapsed < aux_engine->timeout_period);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-index dccb1c5..144f51d 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c
-@@ -66,7 +66,7 @@ bool dal_i2c_engine_acquire(
- 
- 		/* i2c_engine is busy by VBios, lets wait and retry */
- 
--		dm_delay_in_microseconds(engine->ctx, 10);
-+		udelay(10);
- 
- 		++counter;
- 	} while (counter < 2);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-index b02ba79..00a8f07 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c
-@@ -220,7 +220,7 @@ enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
- 		if (result != expected_result)
- 			break;
- 
--		dm_delay_in_microseconds(engine->base.base.ctx, 1);
-+		udelay(1);
- 
- 		++i;
- 	} while (i < timeout);
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-index 2ee5118..ee85f7e 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c
-@@ -84,7 +84,7 @@ static bool wait_for_scl_high(
- 	uint32_t scl_retry = 0;
- 	uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	/* 3 milliseconds delay
- 	 * to wake up some displays from "low power" state.
-@@ -94,7 +94,7 @@ static bool wait_for_scl_high(
- 		if (read_bit_from_ddc(ddc, SCL))
- 			return true;
- 
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		++scl_retry;
- 	} while (scl_retry <= scl_retry_max);
-@@ -114,7 +114,7 @@ static bool start_sync(
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	do {
- 		write_bit_to_ddc(ddc_handle, SDA, true);
-@@ -124,7 +124,7 @@ static bool start_sync(
- 			continue;
- 		}
- 
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -133,11 +133,11 @@ static bool start_sync(
- 
- 		write_bit_to_ddc(ddc_handle, SDA, false);
- 
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SCL, false);
- 
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		return true;
- 	} while (retry <= I2C_SW_RETRIES);
-@@ -157,11 +157,11 @@ static bool stop_sync(
- 
- 	write_bit_to_ddc(ddc_handle, SCL, false);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SDA, false);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -171,7 +171,7 @@ static bool stop_sync(
- 	write_bit_to_ddc(ddc_handle, SDA, true);
- 
- 	do {
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		if (read_bit_from_ddc(ddc_handle, SDA))
- 			return true;
-@@ -194,11 +194,11 @@ static bool write_byte(
- 	/* bits are transmitted serially, starting from MSB */
- 
- 	do {
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
- 
--		dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+		udelay(clock_delay_div_4);
- 
- 		write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -214,11 +214,11 @@ static bool write_byte(
- 	 * after the SCL pulse we use to send our last data bit.
- 	 * If the SDA goes high after that bit, it's a NACK */
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SDA, true);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -229,11 +229,11 @@ static bool write_byte(
- 
- 	ack = !read_bit_from_ddc(ddc_handle, SDA);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+	udelay(clock_delay_div_4 << 1);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, false);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+	udelay(clock_delay_div_4 << 1);
- 
- 	return ack;
- }
-@@ -263,7 +263,7 @@ static bool read_byte(
- 
- 		write_bit_to_ddc(ddc_handle, SCL, false);
- 
--		dm_delay_in_microseconds(ctx, clock_delay_div_4 << 1);
-+		udelay(clock_delay_div_4 << 1);
- 
- 		--shift;
- 	} while (shift >= 0);
-@@ -272,14 +272,14 @@ static bool read_byte(
- 
- 	*byte = data;
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	/* send the acknowledge bit:
- 	 * SDA low means ACK, SDA high means NACK */
- 
- 	write_bit_to_ddc(ddc_handle, SDA, !more);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SCL, true);
- 
-@@ -288,11 +288,11 @@ static bool read_byte(
- 
- 	write_bit_to_ddc(ddc_handle, SCL, false);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	write_bit_to_ddc(ddc_handle, SDA, true);
- 
--	dm_delay_in_microseconds(ctx, clock_delay_div_4);
-+	udelay(clock_delay_div_4);
- 
- 	return true;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0874-drm-amd-dal-Temporarily-disable-HW-i2c-on-DCE80.patch b/common/recipes-kernel/linux/files/0874-drm-amd-dal-Temporarily-disable-HW-i2c-on-DCE80.patch
deleted file mode 100644
index a407c24d..00000000
--- a/common/recipes-kernel/linux/files/0874-drm-amd-dal-Temporarily-disable-HW-i2c-on-DCE80.patch
+++ /dev/null
@@ -1,256 +0,0 @@
-From ad908df5b5037252c7d619acb23b5a6d04049641 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 25 Feb 2016 17:27:53 -0500
-Subject: [PATCH 0874/1110] drm/amd/dal: Temporarily disable HW i2c on DCE80
-
-HWi2c has a bug where we aren't able to read edid. Temporarily force SW
-i2c on DCE8 until we can fix the issue
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Reviewed-by: Eagle Yeh <Eagle.Yeh@amd.com>
-Acked-by: Harry Wentland<harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c        | 8 --------
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c                     | 2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c                  | 6 ++----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c       | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c   | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c | 2 +-
- drivers/gpu/drm/amd/dal/dc/dm_services.h                      | 2 --
- drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c        | 8 ++++----
- drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c          | 8 ++++----
- drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c                | 4 ++--
- drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c        | 7 +++++--
- 11 files changed, 21 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-index d89f9c4..03337f3 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
-@@ -40,14 +40,6 @@
- #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
- #define dm_free(ptr) kfree(ptr)
- 
--void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds)
--{
--	if (milliseconds >= 20)
--		msleep(milliseconds);
--	else
--		usleep_range(milliseconds*1000, milliseconds*1000+1);
--}
--
- /******************************************************************************
-  * IRQ Interfaces.
-  *****************************************************************************/
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 01c28f2..0903b0e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1254,7 +1254,7 @@ static enum dc_status enable_link(struct pipe_ctx *pipe_ctx)
- 		break;
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 		status = enable_link_dp_mst(pipe_ctx);
--		dm_sleep_in_milliseconds(pipe_ctx->stream->ctx, 200);
-+		msleep(200);
- 		break;
- 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
- 	case SIGNAL_TYPE_DVI_DUAL_LINK:
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 48e3e4d..aab73ff 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -702,7 +702,7 @@ static bool perform_post_lt_adj_req_sequence(
- 				break;
- 			}
- 
--			dm_sleep_in_milliseconds(link->ctx, 1);
-+			msleep(1);
- 		}
- 
- 		if (!req_drv_setting_changed) {
-@@ -1163,9 +1163,7 @@ bool dp_hbr_verify_link_cap(
- 				if (success)
- 					break;
- 
--				dm_sleep_in_milliseconds(
--					link->ctx,
--					delay_between_retries);
-+				msleep(delay_between_retries);
- 
- 				delay_between_retries += 10;
- 			}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 71ef1de..525a923 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -649,7 +649,7 @@ static void link_encoder_edp_wait_for_hpd_ready(
- 			break;
- 		}
- 
--		dm_sleep_in_milliseconds(ctx, HPD_CHECK_INTERVAL);
-+		msleep(HPD_CHECK_INTERVAL);
- 
- 		time_elapsed += HPD_CHECK_INTERVAL;
- 	} while (time_elapsed < timeout);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 70b82f1..61dc9c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -356,7 +356,7 @@ bool dce110_timing_generator_blank_crtc(struct timing_generator *tg)
- 			CRTC_CURRENT_BLANK_STATE) == 1)
- 			break;
- 
--		dm_sleep_in_milliseconds(tg->ctx, 1);
-+		msleep(1);
- 		counter--;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-index 10fc041..fcd2b58 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
-@@ -106,7 +106,7 @@ static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
- 			CRTC_CURRENT_BLANK_STATE) == 1)
- 			break;
- 
--		dm_sleep_in_milliseconds(tg->ctx, 1);
-+		msleep(1);
- 		counter--;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index bf315ac..4c45a66 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -255,8 +255,6 @@ bool dm_pp_apply_display_requirements(
- 
- /****** end of PP interfaces ******/
- 
--void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds);
--
- enum platform_method {
- 	PM_GET_AVAILABLE_METHODS = 1 << 0,
- 	PM_GET_LID_STATE = 1 << 1,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-index 3e7d42e..7cbdc35 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c
-@@ -692,7 +692,7 @@ static enum gpio_result set_config(
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+					msleep(3);
- 			}
- 		} else {
- 			uint32_t reg2 = regval;
-@@ -719,7 +719,7 @@ static enum gpio_result set_config(
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+					msleep(3);
- 			}
- 
- 			if (!scl_pd_dis) {
-@@ -732,7 +732,7 @@ static enum gpio_result set_config(
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+					msleep(3);
- 			}
- 		}
- 
-@@ -743,7 +743,7 @@ static enum gpio_result set_config(
- 				config_data->config.ddc.clock_en_bit_present)
- 				/* [anaumov] in DAL2, there was
- 				 * dc_service_delay_in_microseconds(2000); */
--				dm_sleep_in_milliseconds(ptr->ctx, 2);
-+				msleep(2);
- 
- 			/* set the I2C pad mode */
- 			/* read the register again,
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-index 5776751..74b980d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_ddc_dce80.c
-@@ -176,7 +176,7 @@ static enum gpio_result set_config(
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+					msleep(3);
- 			}
- 		} else {
- 			uint32_t reg2 = regval;
-@@ -203,7 +203,7 @@ static enum gpio_result set_config(
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+					msleep(3);
- 			}
- 
- 			if (!scl_pd_dis) {
-@@ -216,7 +216,7 @@ static enum gpio_result set_config(
- 					/* should not affect normal I2C R/W */
- 					/* [anaumov] in DAL2, there was
- 					 * dc_service_delay_in_microseconds(2500); */
--					dm_sleep_in_milliseconds(ptr->ctx, 3);
-+					msleep(3);
- 			}
- 		}
- 
-@@ -227,7 +227,7 @@ static enum gpio_result set_config(
- 				config_data->config.ddc.clock_en_bit_present)
- 				/* [anaumov] in DAL2, there was
- 				 * dc_service_delay_in_microseconds(2000); */
--				dm_sleep_in_milliseconds(ptr->ctx, 2);
-+				msleep(2);
- 
- 			/* set the I2C pad mode */
- 			/* read the register again,
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-index a281dc0..c0715d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
-@@ -275,7 +275,7 @@ static bool read_command(
- 
- 		if (ctx.operation_succeeded && !ctx.transaction_complete)
- 			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
--				dm_sleep_in_milliseconds(engine->base.ctx, engine->delay);
-+				msleep(engine->delay);
- 	} while (ctx.operation_succeeded && !ctx.transaction_complete);
- 
- 	return ctx.operation_succeeded;
-@@ -475,7 +475,7 @@ static bool write_command(
- 
- 		if (ctx.operation_succeeded && !ctx.transaction_complete)
- 			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
--				dm_sleep_in_milliseconds(engine->base.ctx, engine->delay);
-+				msleep(engine->delay);
- 	} while (ctx.operation_succeeded && !ctx.transaction_complete);
- 
- 	return ctx.operation_succeeded;
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-index 1ed6196..1e5c2ad 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
-@@ -170,8 +170,11 @@ static bool construct(
- 	uint32_t reference_frequency =
- 		dal_i2caux_get_reference_clock(as) >> 1;
- 
--	bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(
--		FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);
-+	/*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(
-+		FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
-+
-+	/* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
-+	bool use_i2c_sw_engine = true;
- 
- 	uint32_t i;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0875-drm-amd-dal-Parse-asic-ID-in-dc-rather-than-AS.patch b/common/recipes-kernel/linux/files/0875-drm-amd-dal-Parse-asic-ID-in-dc-rather-than-AS.patch
deleted file mode 100644
index 62384d0b..00000000
--- a/common/recipes-kernel/linux/files/0875-drm-amd-dal-Parse-asic-ID-in-dc-rather-than-AS.patch
+++ /dev/null
@@ -1,174 +0,0 @@
-From 5a01917f514b22162da1246cc2de13369f82ca83 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Wed, 2 Mar 2016 13:44:23 -0500
-Subject: [PATCH 0875/1110] drm/amd/dal: Parse asic ID in dc rather than AS
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c          | 25 +++++++++++++----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 40 +++++++++++++++++++++++++--
- drivers/gpu/drm/amd/dal/dc/inc/resource.h     |  8 +++++-
- drivers/gpu/drm/amd/dal/include/dal_types.h   |  2 +-
- 4 files changed, 64 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 4a52d43..80339f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -303,6 +303,7 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 	struct dal_logger *logger;
- 	struct adapter_service *as;
- 	struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
-+	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
- 
- 	if (!dc_ctx) {
- 		dm_error("%s: failed to create ctx\n", __func__);
-@@ -322,7 +323,15 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 		goto logger_fail;
- 	}
- 	dc_ctx->logger = logger;
-+	dc->ctx = dc_ctx;
-+	dc->ctx->dce_environment = init_params->dce_environment;
-+
-+
-+	resource_parse_asic_id(dc, init_params->asic_id, &dc_version);
- 
-+
-+/* TODO: Refactor DCE code to remove AS and asic caps */
-+if (dc_version < DCE_VERSION_MAX) {
- 	/* Create adapter service */
- 	as = create_as(init_params, dc_ctx);
- 
-@@ -340,17 +349,12 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 		goto as_fail;
- 	}
- 
--	dc->ctx = dc_ctx;
--
--	dc->ctx->dce_environment = dal_adapter_service_get_dce_environment(
--			as);
--
- 	/* Create hardware sequencer */
- 	if (!dc_construct_hw_sequencer(as, dc))
- 		goto hwss_fail;
- 
- 	if (!dc_construct_resource_pool(
--		as, dc, init_params->num_virtual_links))
-+		as, dc, init_params->num_virtual_links, dc_version))
- 		goto construct_resource_fail;
- 
- 	if (!create_links(dc, as, init_params->num_virtual_links))
-@@ -359,6 +363,15 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
- 
- 	bw_calcs_data_update_from_pplib(dc);
-+} else {
-+
-+	/* Resource should construct all asic specific resources.
-+	 * This should be the only place where we need to parse the asic id
-+	 */
-+	if (!dc_construct_resource_pool(
-+		NULL, dc, init_params->num_virtual_links, dc_version))
-+		goto construct_resource_fail;
-+}
- 
- 	return true;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 917e6a5..2229699 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -42,13 +42,47 @@
- #include "dce110/dce110_resource.h"
- #endif
- 
-+bool resource_parse_asic_id(struct core_dc *dc,
-+		struct hw_asic_id asic_id,
-+		enum dce_version *dc_version)
-+{
-+	switch (asic_id.chip_family) {
-+
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case FAMILY_CI:
-+	case FAMILY_KV:
-+		*dc_version = DCE_VERSION_8_0;
-+		break;
-+#endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case FAMILY_CZ:
-+		*dc_version = DCE_VERSION_11_0;
-+		break;
-+#endif
-+
-+	case FAMILY_VI:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-+		if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
-+				ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
-+			*dc_version = DCE_VERSION_10_0;
-+			break;
-+		}
-+#endif
-+		break;
-+	default:
-+		*dc_version = DCE_VERSION_UNKNOWN;
-+		return false;
-+	}
-+	return true;
-+}
-+
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 				struct core_dc *dc,
--				uint8_t num_virtual_links)
-+				uint8_t num_virtual_links,
-+				enum dce_version dc_version)
- {
--	enum dce_version dce_ver = dal_adapter_service_get_dce_version(adapter_serv);
- 
--	switch (dce_ver) {
-+	switch (dc_version) {
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		return dce100_construct_resource_pool(
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 0836e41..9aefe9e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -28,14 +28,20 @@
- #include "core_types.h"
- #include "core_status.h"
- #include "core_dc.h"
-+#include "dal_asic_id.h"
- 
- /* TODO unhardcode, 4 for CZ*/
- #define MEMORY_TYPE_MULTIPLIER 4
- #define DCE110_UNDERLAY_IDX 3
- 
-+bool resource_parse_asic_id(struct core_dc *dc,
-+				struct hw_asic_id asic_id,
-+				enum dce_version *dc_version);
-+
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 				struct core_dc *dc,
--				uint8_t num_virtual_links);
-+				uint8_t num_virtual_links,
-+				enum dce_version dc_version);
- 
- enum dc_status resource_map_pool_resources(
- 	const struct core_dc *dc,
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index eea3306..bcf83e9 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -43,7 +43,7 @@ enum dce_version {
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	DCE_VERSION_11_0,
- #endif
--	DCE_VERSION_MAX
-+	DCE_VERSION_MAX,
- };
- 
- /* Wireless display structs */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0876-drm-amd-dal-Add-print-to-indicate-DC-creation.patch b/common/recipes-kernel/linux/files/0876-drm-amd-dal-Add-print-to-indicate-DC-creation.patch
deleted file mode 100644
index 1c6f736a..00000000
--- a/common/recipes-kernel/linux/files/0876-drm-amd-dal-Add-print-to-indicate-DC-creation.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 6cd9b175ad4042f07b185763c2043da96720603e Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 2 Mar 2016 14:21:43 -0500
-Subject: [PATCH 0876/1110] drm/amd/dal: Add print to indicate DC creation
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 4 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc.c          | 5 +++++
- 2 files changed, 9 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 2f2077e1..b089124 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -250,6 +250,7 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
- 	adev->dm.ddev = adev->ddev;
- 	adev->dm.adev = adev;
- 
-+	DRM_INFO("DAL is enabled\n");
- 	/* Zero all the fields */
- 	memset(&init_data, 0, sizeof(init_data));
- 
-@@ -305,6 +306,9 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
- 	/* Display Core create. */
- 	adev->dm.dc = dc_create(&init_data);
- 
-+	if (!adev->dm.dc)
-+		DRM_INFO("Display Core failed to initialize!\n");
-+
- 	INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
- 
- 	if (amdgpu_dm_initialize_drm_device(adev)) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 80339f6..b533b59 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -489,6 +489,11 @@ struct dc *dc_create(const struct dc_init_data *init_params)
- 	dc->public.caps.max_links = dc->link_count;
- 	dc->public.caps.max_audios = dc->res_pool.audio_count;
- 
-+	dal_logger_write(dc->ctx->logger,
-+			LOG_MAJOR_INTERFACE_TRACE,
-+			LOG_MINOR_COMPONENT_DC,
-+			"Display Core initialized\n");
-+
- 	return &dc->public;
- 
- construct_fail:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0877-drm-amd-dal-Return-dc_version-directly-from-parse_as.patch b/common/recipes-kernel/linux/files/0877-drm-amd-dal-Return-dc_version-directly-from-parse_as.patch
deleted file mode 100644
index 1f28c0ac..00000000
--- a/common/recipes-kernel/linux/files/0877-drm-amd-dal-Return-dc_version-directly-from-parse_as.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 2eb80bad732ca2e939df6e0699859016d059b8ab Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Wed, 2 Mar 2016 15:14:18 -0500
-Subject: [PATCH 0877/1110] drm/amd/dal: Return dc_version directly from
- parse_asic_id
-
-No need to pass the output as a parameter.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c          |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 20 +++++++-------
- drivers/gpu/drm/amd/dal/dc/inc/resource.h     | 38 +++++++++++++--------------
- 3 files changed, 30 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index b533b59..a25741d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -327,7 +327,7 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 	dc->ctx->dce_environment = init_params->dce_environment;
- 
- 
--	resource_parse_asic_id(dc, init_params->asic_id, &dc_version);
-+	dc_version = resource_parse_asic_id(init_params->asic_id);
- 
- 
- /* TODO: Refactor DCE code to remove AS and asic caps */
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 2229699..ba163c3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -42,21 +42,21 @@
- #include "dce110/dce110_resource.h"
- #endif
- 
--bool resource_parse_asic_id(struct core_dc *dc,
--		struct hw_asic_id asic_id,
--		enum dce_version *dc_version)
--{
-+enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
-+ {
-+	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
-+
- 	switch (asic_id.chip_family) {
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
- 	case FAMILY_CI:
- 	case FAMILY_KV:
--		*dc_version = DCE_VERSION_8_0;
-+		dc_version = DCE_VERSION_8_0;
- 		break;
- #endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case FAMILY_CZ:
--		*dc_version = DCE_VERSION_11_0;
-+		dc_version = DCE_VERSION_11_0;
- 		break;
- #endif
- 
-@@ -64,16 +64,16 @@ bool resource_parse_asic_id(struct core_dc *dc,
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 		if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
- 				ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
--			*dc_version = DCE_VERSION_10_0;
-+			dc_version = DCE_VERSION_10_0;
- 			break;
- 		}
- #endif
- 		break;
- 	default:
--		*dc_version = DCE_VERSION_UNKNOWN;
--		return false;
-+		dc_version = DCE_VERSION_UNKNOWN;
-+		break;
- 	}
--	return true;
-+	return dc_version;
- }
- 
- bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 9aefe9e..45ee324 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -34,26 +34,26 @@
- #define MEMORY_TYPE_MULTIPLIER 4
- #define DCE110_UNDERLAY_IDX 3
- 
--bool resource_parse_asic_id(struct core_dc *dc,
--				struct hw_asic_id asic_id,
--				enum dce_version *dc_version);
-+enum dce_version resource_parse_asic_id(
-+		struct hw_asic_id asic_id);
- 
--bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
--				struct core_dc *dc,
--				uint8_t num_virtual_links,
--				enum dce_version dc_version);
-+bool dc_construct_resource_pool(
-+		struct adapter_service *adapter_serv,
-+		struct core_dc *dc,
-+		uint8_t num_virtual_links,
-+		enum dce_version dc_version);
- 
- enum dc_status resource_map_pool_resources(
--	const struct core_dc *dc,
--	struct validate_context *context);
-+		const struct core_dc *dc,
-+		struct validate_context *context);
- 
- void resource_build_scaling_params(
--	const struct dc_surface *surface,
--	struct pipe_ctx *pipe_ctx);
-+		const struct dc_surface *surface,
-+		struct pipe_ctx *pipe_ctx);
- 
- void resource_build_scaling_params_for_context(
--	const struct core_dc *dc,
--	struct validate_context *context);
-+		const struct core_dc *dc,
-+		struct validate_context *context);
- 
- void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
- 
-@@ -66,12 +66,12 @@ void resource_reference_clock_source(
- 		struct clock_source *clock_source);
- 
- bool resource_is_same_timing(
--	const struct dc_crtc_timing *timing1,
--	const struct dc_crtc_timing *timing2);
-+		const struct dc_crtc_timing *timing1,
-+		const struct dc_crtc_timing *timing2);
- 
- struct clock_source *resource_find_used_clk_src_for_sharing(
--	struct resource_context *res_ctx,
--	struct pipe_ctx *pipe_ctx);
-+		struct resource_context *res_ctx,
-+		struct pipe_ctx *pipe_ctx);
- 
- struct clock_source *dc_resource_find_first_free_pll(
- 		struct resource_context *res_ctx);
-@@ -83,8 +83,8 @@ bool resource_attach_surfaces_to_context(
- 		struct validate_context *context);
- 
- void resource_validate_ctx_copy_construct(
--	const struct validate_context *src_ctx,
--	struct validate_context *dst_ctx);
-+		const struct validate_context *src_ctx,
-+		struct validate_context *dst_ctx);
- 
- void resource_validate_ctx_destruct(struct validate_context *context);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0878-drm-amd-dal-Start-calling-create_links-for-diag.patch b/common/recipes-kernel/linux/files/0878-drm-amd-dal-Start-calling-create_links-for-diag.patch
deleted file mode 100644
index f01c488b..00000000
--- a/common/recipes-kernel/linux/files/0878-drm-amd-dal-Start-calling-create_links-for-diag.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From ec6ea01b7ddafd72ebf915d74446cfdd30fdf850 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Thu, 3 Mar 2016 17:25:56 -0500
-Subject: [PATCH 0878/1110] drm/amd/dal: Start calling create_links for diag
-
-Also store bios pointer inside dc_context rather than in AS
-as a step of removing adapter service
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c  | 79 +++++++++++++++++++----------------
- drivers/gpu/drm/amd/dal/dc/dc_types.h |  2 +
- 2 files changed, 45 insertions(+), 36 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index a25741d..3a6d0c1 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -80,7 +80,7 @@ static bool create_links(
- 
- 	dc->link_count = 0;
- 
--	dcb = dal_adapter_service_get_bios_parser(as);
-+	dcb = dc->ctx->dc_bios;
- 
- 	connectors_num = dcb->funcs->get_connectors_number(dcb);
- 
-@@ -169,7 +169,7 @@ static void init_hw(struct core_dc *dc)
- 	struct dc_bios *bp;
- 	struct transform *xfm;
- 
--	bp = dal_adapter_service_get_bios_parser(dc->res_pool.adapter_srv);
-+	bp = dc->ctx->dc_bios;
- 	for (i = 0; i < dc->res_pool.pipe_count; i++) {
- 		xfm = dc->res_pool.transforms[i];
- 
-@@ -330,48 +330,55 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 	dc_version = resource_parse_asic_id(init_params->asic_id);
- 
- 
--/* TODO: Refactor DCE code to remove AS and asic caps */
--if (dc_version < DCE_VERSION_MAX) {
--	/* Create adapter service */
--	as = create_as(init_params, dc_ctx);
-+	/* TODO: Refactor DCE code to remove AS and asic caps */
-+	if (dc_version < DCE_VERSION_MAX) {
-+		/* Create adapter service */
-+		as = create_as(init_params, dc_ctx);
- 
--	if (!as) {
--		dm_error("%s: create_as() failed!\n", __func__);
--		goto as_fail;
--	}
-+		if (!as) {
-+			dm_error("%s: create_as() failed!\n", __func__);
-+			goto as_fail;
-+		}
- 
--	/* Initialize HW controlled by Adapter Service */
--	if (false == dal_adapter_service_initialize_hw_data(
--			as)) {
--		dm_error("%s: dal_adapter_service_initialize_hw_data()"\
--				"  failed!\n", __func__);
--		/* Note that AS exist, so have to destroy it.*/
--		goto as_fail;
--	}
-+		/* Initialize HW controlled by Adapter Service */
-+		if (false == dal_adapter_service_initialize_hw_data(
-+				as)) {
-+			dm_error("%s: dal_adapter_service_initialize_hw_data()"\
-+					"  failed!\n", __func__);
-+			/* Note that AS exist, so have to destroy it.*/
-+			goto as_fail;
-+		}
- 
--	/* Create hardware sequencer */
--	if (!dc_construct_hw_sequencer(as, dc))
--		goto hwss_fail;
-+		dc_ctx->dc_bios = dal_adapter_service_get_bios_parser(as);
- 
--	if (!dc_construct_resource_pool(
--		as, dc, init_params->num_virtual_links, dc_version))
--		goto construct_resource_fail;
-+		/* Create hardware sequencer */
-+		if (!dc_construct_hw_sequencer(as, dc))
-+			goto hwss_fail;
- 
--	if (!create_links(dc, as, init_params->num_virtual_links))
--		goto create_links_fail;
-+		if (!dc_construct_resource_pool(
-+			as, dc, init_params->num_virtual_links, dc_version))
-+			goto construct_resource_fail;
- 
--	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
-+		if (!create_links(dc, as, init_params->num_virtual_links))
-+			goto create_links_fail;
- 
--	bw_calcs_data_update_from_pplib(dc);
--} else {
-+		bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
- 
--	/* Resource should construct all asic specific resources.
--	 * This should be the only place where we need to parse the asic id
--	 */
--	if (!dc_construct_resource_pool(
--		NULL, dc, init_params->num_virtual_links, dc_version))
--		goto construct_resource_fail;
--}
-+		bw_calcs_data_update_from_pplib(dc);
-+	} else {
-+
-+		/* Resource should construct all asic specific resources.
-+		 * This should be the only place where we need to parse the asic id
-+		 */
-+
-+		dc_ctx->dc_bios = init_params->vbios_override;
-+		if (!dc_construct_resource_pool(
-+			NULL, dc, init_params->num_virtual_links, dc_version))
-+			goto construct_resource_fail;
-+
-+		if (!create_links(dc, NULL, init_params->num_virtual_links))
-+			goto create_links_fail;
-+	}
- 
- 	return true;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index a0a8542..d3d105e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -80,6 +80,8 @@ struct dc_context {
- 	void *cgs_device;
- 
- 	enum dce_environment dce_environment;
-+
-+	struct dc_bios *dc_bios;
- };
- 
- /*
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0879-drm-amd-dal-dm-fix-crtc-count-for-STONEY.patch b/common/recipes-kernel/linux/files/0879-drm-amd-dal-dm-fix-crtc-count-for-STONEY.patch
deleted file mode 100644
index 9c94e3a3..00000000
--- a/common/recipes-kernel/linux/files/0879-drm-amd-dal-dm-fix-crtc-count-for-STONEY.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From edd619acefeaa7a95c52ec9b5b01b97558c62531 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 4 Mar 2016 18:02:39 -0500
-Subject: [PATCH 0879/1110] drm/amd/dal/dm: fix crtc count for STONEY
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Stoney has 2 rather then 3.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index b089124..c12ef99 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1244,13 +1244,19 @@ static int dm_early_init(void *handle)
- 			adev->mode_info.funcs = &dm_dce_v10_0_display_funcs;
- 		break;
- 	case CHIP_CARRIZO:
--	case CHIP_STONEY:
- 		adev->mode_info.num_crtc = 3;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 9;
- 		if (adev->mode_info.funcs == NULL)
- 			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
- 		break;
-+	case CHIP_STONEY:
-+		adev->mode_info.num_crtc = 2;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 9;
-+		if (adev->mode_info.funcs == NULL)
-+			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
-+		break;
- 	default:
- 		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
- 		return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0880-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-checks.patch b/common/recipes-kernel/linux/files/0880-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-checks.patch
deleted file mode 100644
index b92ca818..00000000
--- a/common/recipes-kernel/linux/files/0880-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-checks.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From feacff771ed584224d437d1ec7dcf0549ccbfaf5 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 18 Mar 2016 14:36:37 -0400
-Subject: [PATCH 0880/1110] drm/amd/dal/dm: remove LINUX_VERSION_CODE checks
-
-No longer needed upstream.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  | 26 ----------------------
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  4 ----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  3 ---
- 3 files changed, 33 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index e442318..8688ca2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -130,7 +130,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
- 	return result;
- }
- 
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static struct amdgpu_connector *get_connector_for_sink(
- 	struct drm_device *dev,
- 	const struct dc_sink *sink)
-@@ -146,7 +145,6 @@ static struct amdgpu_connector *get_connector_for_sink(
- 
- 	return aconnector;
- }
--#endif
- 
- static struct amdgpu_connector *get_connector_for_link(
- 	struct drm_device *dev,
-@@ -164,7 +162,6 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static void get_payload_table(
- 		struct amdgpu_connector *aconnector,
- 		struct dp_mst_stream_allocation_table *proposed_table)
-@@ -201,7 +198,6 @@ static void get_payload_table(
- 
- 	mutex_unlock(&mst_mgr->payload_lock);
- }
--#endif
- 
- /*
-  * Writes payload allocation table in immediate downstream device.
-@@ -212,7 +208,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
- 		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable)
- {
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -292,9 +287,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
- 		return false;
- 
- 	return true;
--#else
--	return false;
--#endif
- }
- 
- /*
-@@ -305,7 +297,6 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream)
- {
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -328,9 +319,6 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		return false;
- 
- 	return true;
--#else
--	return false;
--#endif
- }
- 
- bool dm_helpers_dp_mst_send_payload_allocation(
-@@ -338,7 +326,6 @@ bool dm_helpers_dp_mst_send_payload_allocation(
- 		const struct dc_stream *stream,
- 		bool enable)
- {
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -367,14 +354,10 @@ bool dm_helpers_dp_mst_send_payload_allocation(
- 		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
- 
- 	return true;
--#else
--	return false;
--#endif
- }
- 
- void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- {
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	uint8_t esi[8] = { 0 };
- 	uint8_t dret;
- 	bool new_irq_handled = true;
-@@ -413,9 +396,6 @@ void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- 				DP_SINK_COUNT_ESI, esi, 8);
- 		}
- 	}
--#else
--	return false;
--#endif
- }
- 
- bool dm_helpers_dp_mst_start_top_mgr(
-@@ -423,7 +403,6 @@ bool dm_helpers_dp_mst_start_top_mgr(
- 		const struct dc_link *link,
- 		bool boot)
- {
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-@@ -438,16 +417,12 @@ bool dm_helpers_dp_mst_start_top_mgr(
- 			aconnector, aconnector->base.base.id);
- 
- 	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
--#else
--	return false;
--#endif
- }
- 
- void dm_helpers_dp_mst_stop_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link)
- {
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-@@ -457,7 +432,6 @@ void dm_helpers_dp_mst_stop_top_mgr(
- 
- 	if (aconnector->mst_mgr.mst_state == true)
- 		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
--#endif
- }
- 
- bool dm_helpers_dp_read_dpcd(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 2ab2703..b0a82a2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -115,7 +115,6 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 	return msg->size;
- }
- 
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static enum drm_connector_status
- dm_dp_mst_detect(struct drm_connector *connector, bool force)
- {
-@@ -455,7 +454,6 @@ struct drm_dp_mst_topology_cbs dm_mst_cbs = {
- 	.hotplug = dm_dp_mst_hotplug,
- 	.register_connector = dm_dp_mst_register_connector
- };
--#endif
- 
- void amdgpu_dm_initialize_mst_connector(
- 	struct amdgpu_display_manager *dm,
-@@ -467,7 +465,6 @@ void amdgpu_dm_initialize_mst_connector(
- 	aconnector->dm_dp_aux.link_index = aconnector->connector_id;
- 
- 	drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	aconnector->mst_mgr.cbs = &dm_mst_cbs;
- 	drm_dp_mst_topology_mgr_init(
- 		&aconnector->mst_mgr,
-@@ -476,6 +473,5 @@ void amdgpu_dm_initialize_mst_connector(
- 		16,
- 		4,
- 		aconnector->connector_id);
--#endif
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a8a2e10..ca553ce 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1539,10 +1539,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 	if (!primary_plane)
- 		goto fail_plane;
- 
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
--	/* this flag doesn't exist in older kernels */
- 	primary_plane->format_default = true;
--#endif
- 
- 	res = drm_universal_plane_init(
- 		dm->adev->ddev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0881-drm-amd-dal-merge-same-map_clock_resources.patch b/common/recipes-kernel/linux/files/0881-drm-amd-dal-merge-same-map_clock_resources.patch
deleted file mode 100644
index f1c4e6a9..00000000
--- a/common/recipes-kernel/linux/files/0881-drm-amd-dal-merge-same-map_clock_resources.patch
+++ /dev/null
@@ -1,325 +0,0 @@
-From 7d7df856a24ba94a4fb4b6c83dd410ac0f671f2d Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Mon, 7 Mar 2016 00:18:44 -0500
-Subject: [PATCH 0881/1110] drm/amd/dal: merge same map_clock_resources
-
-This is the follow-up change for clock sources clean-up
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 55 +++++++++++++++++++
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 62 +---------------------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 56 +------------------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 55 +------------------
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  4 ++
- 5 files changed, 62 insertions(+), 170 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index ba163c3..5f3b702 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -1217,3 +1217,58 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
- 	translate_info_frame(&info_frame,
- 			&pipe_ctx->encoder_info_frame);
- }
-+
-+enum dc_status resource_map_clock_resources(
-+		const struct core_dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j, k;
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (dc_is_dp_signal(pipe_ctx->signal)
-+					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
-+					pipe_ctx->clock_source =
-+						context->res_ctx.pool.dp_clock_source;
-+				else {
-+					pipe_ctx->clock_source =
-+						resource_find_used_clk_src_for_sharing(
-+							&context->res_ctx,
-+							pipe_ctx);
-+
-+					if (pipe_ctx->clock_source == NULL)
-+						pipe_ctx->clock_source =
-+							dc_resource_find_first_free_pll(&context->res_ctx);
-+				}
-+
-+				if (pipe_ctx->clock_source == NULL)
-+					return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+				resource_reference_clock_source(
-+						&context->res_ctx,
-+						pipe_ctx->clock_source);
-+
-+				/* only one cs per stream regardless of mpo */
-+				break;
-+			}
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index f6b9cb8..6b8ae77 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -788,66 +788,6 @@ static void set_target_unchanged(
- 	}
- }
- 
--static enum dc_status map_clock_resources(
--		const struct core_dc *dc,
--		struct validate_context *context)
--{
--	uint8_t i, j, k;
--
--	/* acquire new resources */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			for (k = 0; k < MAX_PIPES; k++) {
--				struct pipe_ctx *pipe_ctx =
--					&context->res_ctx.pipe_ctx[k];
--
--				if (context->res_ctx.pipe_ctx[k].stream != stream)
--					continue;
--
--				/*
--				 * in this case if external clock source is not
--				 * available for DP, it will pick-up first
--				 * available pll from find_first_free_pll
--				 */
--				if (dc_is_dp_signal(pipe_ctx->signal)
--					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source =
--						context->res_ctx.pool.dp_clock_source;
--				else {
--					pipe_ctx->clock_source =
--						resource_find_used_clk_src_for_sharing(
--							&context->res_ctx,
--							pipe_ctx);
--
--					if (pipe_ctx->clock_source == NULL)
--						pipe_ctx->clock_source =
--							dc_resource_find_first_free_pll(&context->res_ctx);
--				}
--
--				if (pipe_ctx->clock_source == NULL)
--					return DC_NO_CLOCK_SOURCE_RESOURCE;
--
--				resource_reference_clock_source(
--						&context->res_ctx,
--						pipe_ctx->clock_source);
--
--				/* only one cs per stream regardless of mpo */
--				break;
--			}
--		}
--	}
--
--	return DC_OK;
--}
--
- enum dc_status dce100_validate_with_context(
- 		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
-@@ -895,7 +835,7 @@ enum dc_status dce100_validate_with_context(
- 	result = resource_map_pool_resources(dc, context);
- 
- 	if (result == DC_OK)
--		result = map_clock_resources(dc, context);
-+		result = resource_map_clock_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = validate_mapped_resource(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index 66b7014..b39e2af 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -915,60 +915,6 @@ static void set_target_unchanged(
- 	}
- }
- 
--static enum dc_status map_clock_resources(
--		const struct core_dc *dc,
--		struct validate_context *context)
--{
--	uint8_t i, j, k;
--
--	/* acquire new resources */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			for (k = 0; k < MAX_PIPES; k++) {
--				struct pipe_ctx *pipe_ctx =
--					&context->res_ctx.pipe_ctx[k];
--
--				if (context->res_ctx.pipe_ctx[k].stream != stream)
--					continue;
--
--				if (dc_is_dp_signal(pipe_ctx->signal)
--					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source =
--						context->res_ctx.pool.dp_clock_source;
--				else {
--					pipe_ctx->clock_source =
--						resource_find_used_clk_src_for_sharing(
--							&context->res_ctx, pipe_ctx);
--
--					if (pipe_ctx->clock_source == NULL)
--						pipe_ctx->clock_source =
--							dc_resource_find_first_free_pll(&context->res_ctx);
--				}
--
--				if (pipe_ctx->clock_source == NULL)
--					return DC_NO_CLOCK_SOURCE_RESOURCE;
--
--				resource_reference_clock_source(
--						&context->res_ctx,
--						pipe_ctx->clock_source);
--
--				/* only one cs per stream regardless of mpo */
--				break;
--			}
--		}
--	}
--
--	return DC_OK;
--}
--
- enum dc_status dce110_validate_with_context(
- 		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
-@@ -1016,7 +962,7 @@ enum dc_status dce110_validate_with_context(
- 	result = resource_map_pool_resources(dc, context);
- 
- 	if (result == DC_OK)
--		result = map_clock_resources(dc, context);
-+		result = resource_map_clock_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = validate_mapped_resource(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 864f32a..3b70643 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -905,59 +905,6 @@ static void set_target_unchanged(
- 	}
- }
- 
--static enum dc_status map_clock_resources(
--		const struct core_dc *dc,
--		struct validate_context *context)
--{
--	uint8_t i, j, k;
--
--	/* acquire new resources */
--	for (i = 0; i < context->target_count; i++) {
--		struct core_target *target = context->targets[i];
--
--		if (context->target_flags[i].unchanged)
--			continue;
--
--		for (j = 0; j < target->public.stream_count; j++) {
--			struct core_stream *stream =
--				DC_STREAM_TO_CORE(target->public.streams[j]);
--
--			for (k = 0; k < MAX_PIPES; k++) {
--				struct pipe_ctx *pipe_ctx =
--					&context->res_ctx.pipe_ctx[k];
--
--				if (context->res_ctx.pipe_ctx[k].stream != stream)
--					continue;
--
--				if (dc_is_dp_signal(pipe_ctx->signal)
--					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					pipe_ctx->clock_source = context->res_ctx.pool.dp_clock_source;
--				else {
--					pipe_ctx->clock_source =
--						resource_find_used_clk_src_for_sharing(
--							&context->res_ctx, pipe_ctx);
--
--					if (pipe_ctx->clock_source == NULL)
--						pipe_ctx->clock_source =
--							dc_resource_find_first_free_pll(&context->res_ctx);
--				}
--
--				if (pipe_ctx->clock_source == NULL)
--					return DC_NO_CLOCK_SOURCE_RESOURCE;
--
--				resource_reference_clock_source(
--						&context->res_ctx,
--						pipe_ctx->clock_source);
--
--				/* only one cs per stream regardless of mpo */
--				break;
--			}
--		}
--	}
--
--	return DC_OK;
--}
--
- enum dc_status dce80_validate_with_context(
- 		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
-@@ -1005,7 +952,7 @@ enum dc_status dce80_validate_with_context(
- 	result = resource_map_pool_resources(dc, context);
- 
- 	if (result == DC_OK)
--		result = map_clock_resources(dc, context);
-+		result = resource_map_clock_resources(dc, context);
- 
- 	if (result == DC_OK)
- 		result = validate_mapped_resource(dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 45ee324..00843a4 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -88,5 +88,9 @@ void resource_validate_ctx_copy_construct(
- 
- void resource_validate_ctx_destruct(struct validate_context *context);
- 
-+enum dc_status resource_map_clock_resources(
-+		const struct core_dc *dc,
-+		struct validate_context *context);
-+
- 
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0882-drm-amd-dal-Move-hw_init-into-hwss.patch b/common/recipes-kernel/linux/files/0882-drm-amd-dal-Move-hw_init-into-hwss.patch
deleted file mode 100644
index 13174eb2..00000000
--- a/common/recipes-kernel/linux/files/0882-drm-amd-dal-Move-hw_init-into-hwss.patch
+++ /dev/null
@@ -1,291 +0,0 @@
-From 8bea7ee56f14f0cfcc25373b35cc5907a1f03f79 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 7 Mar 2016 13:53:12 -0500
-Subject: [PATCH 0882/1110] drm/amd/dal: Move hw_init into hwss
-
-Also move hwss creation to the bottom of dc_resource
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 81 ++++------------------
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  4 ++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 57 ++++++++++++++-
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  4 ++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  4 ++
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  2 +
- 6 files changed, 82 insertions(+), 70 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 3a6d0c1..f6eccbd 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -163,59 +163,7 @@ failed_alloc:
- 	return false;
- }
- 
--static void init_hw(struct core_dc *dc)
--{
--	int i;
--	struct dc_bios *bp;
--	struct transform *xfm;
--
--	bp = dc->ctx->dc_bios;
--	for (i = 0; i < dc->res_pool.pipe_count; i++) {
--		xfm = dc->res_pool.transforms[i];
--
--		dc->hwss.enable_display_power_gating(
--				dc->ctx, i, bp,
--				PIPE_GATING_CONTROL_INIT);
--		dc->hwss.enable_display_power_gating(
--				dc->ctx, i, bp,
--				PIPE_GATING_CONTROL_DISABLE);
--		xfm->funcs->transform_power_up(xfm);
--		dc->hwss.enable_display_pipe_clock_gating(
--			dc->ctx,
--			true);
--	}
--
--	dc->hwss.clock_gating_power_up(dc->ctx, false);
--	bp->funcs->power_up(bp);
--	/***************************************/
- 
--	for (i = 0; i < dc->link_count; i++) {
--		/****************************************/
--		/* Power up AND update implementation according to the
--		 * required signal (which may be different from the
--		 * default signal on connector). */
--		struct core_link *link = dc->links[i];
--		link->link_enc->funcs->hw_init(link->link_enc);
--	}
--
--	for (i = 0; i < dc->res_pool.pipe_count; i++) {
--		struct timing_generator *tg = dc->res_pool.timing_generators[i];
--
--		tg->funcs->disable_vga(tg);
--
--		/* Blank controller using driver code instead of
--		 * command table. */
--		tg->funcs->set_blank(tg, true);
--	}
--
--	for(i = 0; i < dc->res_pool.audio_count; i++) {
--		struct audio *audio = dc->res_pool.audios[i];
--
--		if (dal_audio_power_up(audio) != AUDIO_RESULT_OK)
--			dm_error("Failed audio power up!\n");
--	}
--
--}
- 
- static struct adapter_service *create_as(
- 		const struct dc_init_data *init,
-@@ -351,10 +299,6 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 
- 		dc_ctx->dc_bios = dal_adapter_service_get_bios_parser(as);
- 
--		/* Create hardware sequencer */
--		if (!dc_construct_hw_sequencer(as, dc))
--			goto hwss_fail;
--
- 		if (!dc_construct_resource_pool(
- 			as, dc, init_params->num_virtual_links, dc_version))
- 			goto construct_resource_fail;
-@@ -388,7 +332,6 @@ create_links_fail:
- as_fail:
- 	dal_logger_destroy(&dc_ctx->logger);
- logger_fail:
--hwss_fail:
- 	dm_free(dc_ctx);
- ctx_fail:
- 	return false;
-@@ -480,31 +423,31 @@ struct dc *dc_create(const struct dc_init_data *init_params)
- 		.driver_context = init_params->driver,
- 		.cgs_device = init_params->cgs_device
- 	};
--	struct core_dc *dc = dm_alloc(sizeof(*dc));
-+	struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
- 
--	if (NULL == dc)
-+	if (NULL == core_dc)
- 		goto alloc_fail;
- 
--	ctx.dc = &dc->public;
--	if (false == construct(dc, init_params))
-+	ctx.dc = &core_dc->public;
-+	if (false == construct(core_dc, init_params))
- 		goto construct_fail;
- 
- 	/*TODO: separate HW and SW initialization*/
--	init_hw(dc);
-+	core_dc->hwss.init_hw(core_dc);
- 
--	dc->public.caps.max_targets = dc->res_pool.pipe_count;
--	dc->public.caps.max_links = dc->link_count;
--	dc->public.caps.max_audios = dc->res_pool.audio_count;
-+	core_dc->public.caps.max_targets = core_dc->res_pool.pipe_count;
-+	core_dc->public.caps.max_links = core_dc->link_count;
-+	core_dc->public.caps.max_audios = core_dc->res_pool.audio_count;
- 
--	dal_logger_write(dc->ctx->logger,
-+	dal_logger_write(core_dc->ctx->logger,
- 			LOG_MAJOR_INTERFACE_TRACE,
- 			LOG_MINOR_COMPONENT_DC,
- 			"Display Core initialized\n");
- 
--	return &dc->public;
-+	return &core_dc->public;
- 
- construct_fail:
--	dm_free(dc);
-+	dm_free(core_dc);
- 
- alloc_fail:
- 	return NULL;
-@@ -1182,7 +1125,7 @@ void dc_set_power_state(
- 
- 	switch (power_state) {
- 	case DC_ACPI_CM_POWER_STATE_D0:
--		init_hw(core_dc);
-+		core_dc->hwss.init_hw(core_dc);
- 		break;
- 	default:
- 		/* NULL means "reset/release all DC targets" */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 6b8ae77..1911bbb 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -1050,6 +1050,10 @@ bool dce100_construct_resource_pool(
- 		pool->stream_enc_count++;
- 	}
- 
-+	/* Create hardware sequencer */
-+	if (!dc_construct_hw_sequencer(as, dc))
-+		goto stream_enc_create_fail;
-+
- 	return true;
- 
- stream_enc_create_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index e6d1c3a..defaac4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1593,7 +1593,62 @@ static void enable_timing_synchronization(
- 	DC_SYNC_INFO("GSL: Set-up complete.\n");
- }
- 
-+static void init_hw(struct core_dc *dc)
-+{
-+	int i;
-+	struct dc_bios *bp;
-+	struct transform *xfm;
-+
-+	bp = dc->ctx->dc_bios;
-+	for (i = 0; i < dc->res_pool.pipe_count; i++) {
-+		xfm = dc->res_pool.transforms[i];
-+
-+		dc->hwss.enable_display_power_gating(
-+				dc->ctx, i, bp,
-+				PIPE_GATING_CONTROL_INIT);
-+		dc->hwss.enable_display_power_gating(
-+				dc->ctx, i, bp,
-+				PIPE_GATING_CONTROL_DISABLE);
-+		xfm->funcs->transform_power_up(xfm);
-+		dc->hwss.enable_display_pipe_clock_gating(
-+			dc->ctx,
-+			true);
-+	}
-+
-+	dc->hwss.clock_gating_power_up(dc->ctx, false);
-+	bp->funcs->power_up(bp);
-+	/***************************************/
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		/****************************************/
-+		/* Power up AND update implementation according to the
-+		 * required signal (which may be different from the
-+		 * default signal on connector). */
-+		struct core_link *link = dc->links[i];
-+		link->link_enc->funcs->hw_init(link->link_enc);
-+	}
-+
-+	for (i = 0; i < dc->res_pool.pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool.timing_generators[i];
-+
-+		tg->funcs->disable_vga(tg);
-+
-+		/* Blank controller using driver code instead of
-+		 * command table. */
-+		tg->funcs->set_blank(tg, true);
-+	}
-+
-+	for (i = 0; i < dc->res_pool.audio_count; i++) {
-+		struct audio *audio = dc->res_pool.audios[i];
-+
-+		if (dal_audio_power_up(audio) != AUDIO_RESULT_OK)
-+			dm_error("Failed audio power up!\n");
-+	}
-+
-+}
-+
- static const struct hw_sequencer_funcs dce110_funcs = {
-+	.init_hw = init_hw,
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
- 	.reset_hw_ctx = reset_hw_ctx,
- 	.set_plane_config = set_plane_config,
-@@ -1613,7 +1668,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.set_blender_mode = dce110_set_blender_mode,
- 	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,/*todo*/
- 	.set_display_clock = set_display_clock,
--	.set_displaymarks = set_displaymarks,
-+	.set_displaymarks = set_displaymarks
- };
- 
- bool dce110_hw_sequencer_construct(struct core_dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index b39e2af..ef3f502 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1188,6 +1188,10 @@ bool dce110_construct_resource_pool(
- 		pool->stream_enc_count++;
- 	}
- 
-+	/* Create hardware sequencer */
-+	if (!dc_construct_hw_sequencer(as, dc))
-+		goto stream_enc_create_fail;
-+
- 	return true;
- 
- stream_enc_create_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 3b70643..078183b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -1157,6 +1157,10 @@ bool dce80_construct_resource_pool(
- 		pool->stream_enc_count++;
- 	}
- 
-+	/* Create hardware sequencer */
-+	if (!dc_construct_hw_sequencer(as, dc))
-+		goto stream_enc_create_fail;
-+
- 	return true;
- 
- stream_enc_create_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index 490ee10..d801a60 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -37,6 +37,8 @@ enum pipe_gating_control {
- 
- struct hw_sequencer_funcs {
- 
-+	void (*init_hw)(struct core_dc *dc);
-+
- 	enum dc_status (*apply_ctx_to_hw)(
- 			struct core_dc *dc, struct validate_context *context);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0883-drm-amd-dal-add-logic-to-handle-hw-and-sw-state-inco.patch b/common/recipes-kernel/linux/files/0883-drm-amd-dal-add-logic-to-handle-hw-and-sw-state-inco.patch
deleted file mode 100644
index 98146592..00000000
--- a/common/recipes-kernel/linux/files/0883-drm-amd-dal-add-logic-to-handle-hw-and-sw-state-inco.patch
+++ /dev/null
@@ -1,279 +0,0 @@
-From 5a1c2aeefdef4941aedb5f719f159d6b16fb8b49 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 4 Mar 2016 14:34:46 -0500
-Subject: [PATCH 0883/1110] drm/amd/dal: add logic to handle hw and sw state
- inconsitency
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      |   6 +
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 162 ++++++++++++---------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |   2 +
- 3 files changed, 103 insertions(+), 67 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index c12ef99..a9973ed 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -697,8 +697,14 @@ static void handle_hpd_irq(void *param)
- 	 */
- 	if (dc_link_detect(aconnector->dc_link, false)) {
- 		amdgpu_dm_update_connector_after_detect(aconnector);
-+
-+		drm_modeset_lock_all(dev);
-+		dm_restore_drm_connector_state(dev, connector);
-+		drm_modeset_unlock_all(dev);
-+
- 		drm_kms_helper_hotplug_event(dev);
- 	}
-+
- }
- 
- static void handle_hpd_rx_irq(void *param)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index ca553ce..dcffffe 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -884,15 +884,20 @@ static struct dc_target *create_target_for_sink(
- 				&aconnector->base.modes,
- 				struct drm_display_mode,
- 				head);
-+
- 	if (NULL == preferred_mode) {
--		DRM_ERROR("No preferred mode found\n");
--		goto stream_create_fail;
-+		/* This may not be an error, the use case is when we we have no
-+		 * usermode calls to reset and set mode upon hotplug. In this
-+		 * case, we call set mode ourselves to restore the previous mode
-+		 * and the modelist may not be filled in in time.
-+		 */
-+		DRM_INFO("No preferred mode found\n");
-+	} else {
-+		decide_crtc_timing_for_drm_display_mode(
-+				&mode, preferred_mode,
-+				dm_state->scaling != RMX_OFF);
- 	}
- 
--	decide_crtc_timing_for_drm_display_mode(
--			&mode, preferred_mode,
--			dm_state->scaling != RMX_OFF);
--
- 	dc_timing_from_drm_display_mode(&stream->timing,
- 			&mode, &aconnector->base);
- 
-@@ -2004,6 +2009,15 @@ static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
- {
- 	/* mode changed means either actually mode changed or enabled changed */
- 	/* active changed means dpms changed */
-+
-+	DRM_DEBUG_KMS("crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
-+			state->enable,
-+			state->active,
-+			state->planes_changed,
-+			state->mode_changed,
-+			state->active_changed,
-+			state->connectors_changed);
-+
- 	if (state->mode_changed) {
- 		/* if it is got disabled - call reset mode */
- 		if (!state->enable)
-@@ -2020,6 +2034,9 @@ static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
- 		if (!state->enable)
- 			return DM_COMMIT_ACTION_NOTHING;
- 
-+		if (state->active && state->connectors_changed)
-+			return DM_COMMIT_ACTION_SET;
-+
- 		if (state->active_changed) {
- 			if (state->active) {
- 				return DM_COMMIT_ACTION_DPMS_ON;
-@@ -2089,64 +2106,6 @@ static void manage_dm_interrupts(
- 	}
- }
- 
--/*
-- * Handle headless hotplug workaround
-- *
-- * In case of headless hotplug, if plugging the same monitor to the same
-- * DDI, DRM consider it as mode unchanged. We should check whether the
-- * sink pointer changed, and set mode_changed properly to
-- * make sure commit is doing everything.
-- */
--static void handle_headless_hotplug(
--		const struct amdgpu_crtc *acrtc,
--		struct drm_crtc_state *state,
--		struct amdgpu_connector **aconnector)
--{
--	struct amdgpu_connector *old_connector =
--			aconnector_from_drm_crtc_id(&acrtc->base);
--
--	/*
--	 * TODO Revisit this. This code is kinda hacky and might break things.
--	 */
--
--	if (!old_connector)
--		return;
--
--	if (!*aconnector)
--		*aconnector = old_connector;
--
--	if (acrtc->target && (*aconnector)->dc_sink) {
--		if ((*aconnector)->dc_sink !=
--				acrtc->target->streams[0]->sink) {
--			state->mode_changed = true;
--		}
--	}
--
--	if (!acrtc->target) {
--		/* In case of headless with DPMS on, when system waked up,
--		 * if no monitor connected, target is null and will not create
--		 * new target, on that condition, we should check
--		 * if any connector is connected, if connected,
--		 * it means a hot plug happened after wake up,
--		 * mode_changed should be set to true to make sure
--		 * commit targets will do everything.
--		 */
--		state->mode_changed =
--			(*aconnector)->base.status ==
--					connector_status_connected;
--	} else {
--		/* In case of headless hotplug, if plug same monitor to same
--		 * DDI, DRM consider it as mode unchanged, we should check
--		 * sink pointer changed, and set mode changed properly to
--		 * make sure commit doing everything.
--		 */
--		/* check if sink has changed from last commit */
--		if ((*aconnector)->dc_sink && (*aconnector)->dc_sink !=
--					acrtc->target->streams[0]->sink)
--			state->mode_changed = true;
--	}
--}
--
- int amdgpu_dm_atomic_commit(
- 	struct drm_device *dev,
- 	struct drm_atomic_state *state,
-@@ -2217,7 +2176,6 @@ int amdgpu_dm_atomic_commit(
- 		/* handles headless hotplug case, updating new_state and
- 		 * aconnector as needed
- 		 */
--		handle_headless_hotplug(acrtc, new_state, &aconnector);
- 
- 		action = get_dm_commit_action(new_state);
- 
-@@ -2229,7 +2187,7 @@ int amdgpu_dm_atomic_commit(
- 					aconnector,
- 					&crtc->state->mode);
- 
--			DRM_DEBUG_KMS("Atomic commit: SET.\n");
-+			DRM_INFO("Atomic commit: SET.\n");
- 
- 			if (!new_target) {
- 				/*
-@@ -2275,11 +2233,12 @@ int amdgpu_dm_atomic_commit(
- 		}
- 
- 		case DM_COMMIT_ACTION_NOTHING:
-+			DRM_DEBUG_KMS("Atomic commit: Nothing.\n");
- 			break;
- 
- 		case DM_COMMIT_ACTION_DPMS_OFF:
- 		case DM_COMMIT_ACTION_RESET:
--			DRM_DEBUG_KMS("Atomic commit: RESET.\n");
-+			DRM_INFO("Atomic commit: RESET.\n");
- 			/* i.e. reset mode */
- 			if (acrtc->target) {
- 				manage_dm_interrupts(adev, acrtc, false);
-@@ -2399,6 +2358,75 @@ int amdgpu_dm_atomic_commit(
- 
- 	return 0;
- }
-+/*
-+ * This functions handle all cases when set mode does not come upon hotplug.
-+ * This include when the same display is unplugged then plugged back into the
-+ * same port and when we are running without usermode desktop manager supprot
-+ */
-+void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
-+{
-+	struct drm_crtc *crtc;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct dc *dc = adev->dm.dc;
-+	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
-+	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->state->crtc);
-+	const struct dc_sink *sink;
-+	struct dc_target *commit_targets[6];
-+	uint32_t commit_targets_count = 0;
-+
-+	if (!aconnector->dc_sink || !connector->state || !connector->state->crtc)
-+		return;
-+
-+	if (!disconnected_acrtc->target)
-+		return;
-+
-+	sink = disconnected_acrtc->target->streams[0]->sink;
-+
-+	/*
-+	 * If the previous sink is not released and different from the current,
-+	 * we deduce we are in a state where we can not rely on usermode call
-+	 * to turn on the display, so we do it here
-+	 */
-+	if (sink != aconnector->dc_sink) {
-+		struct dc_target *new_target =
-+			create_target_for_sink(
-+				aconnector,
-+				&disconnected_acrtc->base.state->mode);
-+		/*
-+		 * we evade vblanks and pflips on crtc that
-+		 * should be changed
-+		 */
-+		manage_dm_interrupts(adev, disconnected_acrtc, false);
-+		/* this is the update mode case */
-+		dc_target_release(disconnected_acrtc->target);
-+
-+		disconnected_acrtc->target = new_target;
-+		disconnected_acrtc->enabled = true;
-+		disconnected_acrtc->hw_mode = disconnected_acrtc->base.state->mode;
-+
-+		commit_targets_count = 0;
-+
-+		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+			struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+
-+			if (acrtc->target) {
-+				commit_targets[commit_targets_count] = acrtc->target;
-+				++commit_targets_count;
-+			}
-+		}
-+
-+		/* DC is optimized not to do anything if 'targets' didn't change. */
-+		dc_commit_targets(dc, commit_targets, commit_targets_count);
-+
-+		dm_dc_surface_commit(dc, &disconnected_acrtc->base,
-+				to_dm_connector_state(
-+				connector->state));
-+
-+		manage_dm_interrupts(adev, disconnected_acrtc, true);
-+		dm_crtc_cursor_reset(&disconnected_acrtc->base);
-+
-+	}
-+}
- 
- static uint32_t add_val_sets_surface(
- 	struct dc_validation_set *val_sets,
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 2cf7cd2..8f65194 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -94,6 +94,8 @@ int amdgpu_dm_connector_mode_valid(
- 	struct drm_connector *connector,
- 	struct drm_display_mode *mode);
- 
-+void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector);
-+
- extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
- 
- #endif		/* __AMDGPU_DM_TYPES_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0884-drm-amd-dal-Move-link-encoder-destroy-from-resource-.patch b/common/recipes-kernel/linux/files/0884-drm-amd-dal-Move-link-encoder-destroy-from-resource-.patch
deleted file mode 100644
index 042d0170..00000000
--- a/common/recipes-kernel/linux/files/0884-drm-amd-dal-Move-link-encoder-destroy-from-resource-.patch
+++ /dev/null
@@ -1,242 +0,0 @@
-From e3e7fa9e289b35926faa082a1b2a8d60c429f545 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 7 Mar 2016 17:24:41 -0500
-Subject: [PATCH 0884/1110] drm/amd/dal: Move link encoder destroy from
- resource to link_encoder
-
-We should be treating link_encoder_destroy as a function pointer within
-link_encoder on a per-link-encoder basis, and not relying on resource to
-clean it up properly
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c                 |  6 ++----
- drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c       |  1 -
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c   | 10 +++++++++-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h   |  2 ++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c       |  7 -------
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h       |  2 --
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c     |  3 ++-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c         |  1 -
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h               |  1 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h          |  1 +
- drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c | 13 ++++++++++++-
- 11 files changed, 28 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 0903b0e..68a167b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -58,13 +58,11 @@ enum {
-  ******************************************************************************/
- static void destruct(struct core_link *link)
- {
--	struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
--
- 	if (link->ddc)
- 		dal_ddc_service_destroy(&link->ddc);
- 
- 	if(link->link_enc)
--		core_dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
-+		link->link_enc->funcs->destroy(&link->link_enc);
- }
- 
- /*
-@@ -1051,7 +1049,7 @@ static bool construct(
- 
- 	return true;
- device_tag_fail:
--	link->dc->res_pool.funcs->link_enc_destroy(&link->link_enc);
-+	link->link_enc->funcs->destroy(&link->link_enc);
- link_enc_create_fail:
- 	dal_ddc_service_destroy(&link->ddc);
- ddc_create_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 1911bbb..a4dba58 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -852,7 +852,6 @@ enum dc_status dce100_validate_with_context(
- static struct resource_funcs dce100_res_pool_funcs = {
- 	.destruct = dce100_destruct_resource_pool,
- 	.link_enc_create = dce100_link_encoder_create,
--	.link_enc_destroy = dce110_link_encoder_destroy,
- 	.validate_with_context = dce100_validate_with_context,
- 	.validate_bandwidth = dce100_validate_bandwidth
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 525a923..0e5588a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -105,9 +105,11 @@ static struct link_encoder_funcs dce110_lnk_enc_funcs = {
- 	.set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- 	.backlight_control = dce110_link_encoder_edp_backlight_control,
- 	.power_control = dce110_link_encoder_edp_power_control,
--	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
-+	.destroy = dce110_link_encoder_destroy
- };
- 
-+
- static enum bp_result link_transmitter_control(
- 	struct dce110_link_encoder *enc110,
- 	struct bp_transmitter_control *cntl)
-@@ -1261,6 +1263,12 @@ void dce110_link_encoder_hw_init(
- 	hpd_initialize(enc110);
- }
- 
-+void dce110_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	dm_free(TO_DCE110_LINK_ENC(*enc));
-+	*enc = NULL;
-+}
-+
- void dce110_link_encoder_setup(
- 	struct link_encoder *enc,
- 	enum signal_type signal)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-index e412804..45dfc60 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
-@@ -88,6 +88,8 @@ bool dce110_link_encoder_validate_output_with_stream(
- /* initialize HW */  /* why do we initialze aux in here? */
- void dce110_link_encoder_hw_init(struct link_encoder *enc);
- 
-+void dce110_link_encoder_destroy(struct link_encoder **enc);
-+
- /* program DIG_MODE in DIG_BE */
- /* TODO can this be combined with enable_output? */
- void dce110_link_encoder_setup(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index ef3f502..f02335e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -417,12 +417,6 @@ struct link_encoder *dce110_link_encoder_create(
- 	return NULL;
- }
- 
--void dce110_link_encoder_destroy(struct link_encoder **enc)
--{
--	dm_free(TO_DCE110_LINK_ENC(*enc));
--	*enc = NULL;
--}
--
- static struct output_pixel_processor *dce110_opp_create(
- 	struct dc_context *ctx,
- 	uint32_t inst,
-@@ -979,7 +973,6 @@ enum dc_status dce110_validate_with_context(
- static struct resource_funcs dce110_res_pool_funcs = {
- 	.destruct = dce110_destruct_resource_pool,
- 	.link_enc_create = dce110_link_encoder_create,
--	.link_enc_destroy = dce110_link_encoder_destroy,
- 	.validate_with_context = dce110_validate_with_context,
- 	.validate_bandwidth = dce110_validate_bandwidth
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-index 3aeb1e5..cf79abe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
-@@ -40,7 +40,5 @@ bool dce110_construct_resource_pool(
- 
- void dce110_destruct_resource_pool(struct resource_pool *pool);
- 
--void dce110_link_encoder_destroy(struct link_encoder **enc);
--
- #endif /* __DC_RESOURCE_DCE110_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-index e8c9e86..e25fca2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-@@ -206,7 +206,8 @@ static struct link_encoder_funcs dce80_lnk_enc_funcs = {
- 	.set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- 	.backlight_control = dce110_link_encoder_edp_backlight_control,
- 	.power_control = dce110_link_encoder_edp_power_control,
--	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
-+	.destroy = dce110_link_encoder_destroy
- };
- 
- bool dce80_link_encoder_construct(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 078183b..594f9ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -969,7 +969,6 @@ enum dc_status dce80_validate_with_context(
- static struct resource_funcs dce80_res_pool_funcs = {
- 	.destruct = dce80_destruct_resource_pool,
- 	.link_enc_create = dce80_link_encoder_create,
--	.link_enc_destroy = dce110_link_encoder_destroy,
- 	.validate_with_context = dce80_validate_with_context,
- 	.validate_bandwidth = dce80_validate_bandwidth
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 02dddc4..4ec6192 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -238,7 +238,6 @@ struct resource_funcs {
- 	void (*destruct)(struct resource_pool *pool);
- 	struct link_encoder *(*link_enc_create)(
- 			const struct encoder_init_data *init);
--	void (*link_enc_destroy)(struct link_encoder **enc);
- 	enum dc_status (*validate_with_context)(
- 					const struct core_dc *dc,
- 					const struct dc_validation_set set[],
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-index d11ef05..24d318d 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-@@ -118,6 +118,7 @@ struct link_encoder_funcs {
- 	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
- 		enum engine_id engine,
- 		bool connect);
-+	void (*destroy)(struct link_encoder **enc);
- };
- 
- #endif /* LINK_ENCODER_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-index 0b3b1b8..66e1fcf 100644
---- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
-@@ -23,6 +23,7 @@
-  *
-  */
- 
-+#include "dm_services.h"
- #include "dm_services_types.h"
- 
- #include "virtual_link_encoder.h"
-@@ -90,6 +91,13 @@ static void virtual_link_encoder_connect_dig_be_to_fe(
- 	enum engine_id engine,
- 	bool connect) {}
- 
-+static void virtual_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	dm_free(*enc);
-+	*enc = NULL;
-+}
-+
-+
- static struct link_encoder_funcs virtual_lnk_enc_funcs = {
- 	.validate_output_with_stream =
- 		virtual_link_encoder_validate_output_with_stream,
-@@ -106,7 +114,8 @@ static struct link_encoder_funcs virtual_lnk_enc_funcs = {
- 	.set_lcd_backlight_level = virtual_link_encoder_set_lcd_backlight_level,
- 	.backlight_control = virtual_link_encoder_edp_backlight_control,
- 	.power_control = virtual_link_encoder_edp_power_control,
--	.connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe
-+	.connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe,
-+	.destroy = virtual_link_encoder_destroy
- };
- 
- bool virtual_link_encoder_construct(
-@@ -131,3 +140,5 @@ bool virtual_link_encoder_construct(
- 
- 	return true;
- }
-+
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0885-drm-amd-dal-Call-BP-directly-to-check-for-accelerate.patch b/common/recipes-kernel/linux/files/0885-drm-amd-dal-Call-BP-directly-to-check-for-accelerate.patch
deleted file mode 100644
index 16248090..00000000
--- a/common/recipes-kernel/linux/files/0885-drm-amd-dal-Call-BP-directly-to-check-for-accelerate.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From a6705cc313235cca40c4379d9ac7f56ced7c540f Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Mon, 7 Mar 2016 15:54:26 -0500
-Subject: [PATCH 0885/1110] drm/amd/dal: Call BP directly to check for
- accelerated mode
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index f6eccbd..4c775f6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -733,6 +733,7 @@ bool dc_commit_targets(
- 	uint8_t target_count)
- {
- 	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	struct dc_bios *dcb = core_dc->ctx->dc_bios;
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	struct validate_context *context;
- 	struct dc_validation_set set[4];
-@@ -774,8 +775,7 @@ bool dc_commit_targets(
- 
- 	pplib_apply_safe_state(core_dc);
- 
--	if (!dal_adapter_service_is_in_accelerated_mode(
--						core_dc->res_pool.adapter_srv)) {
-+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
- 		core_dc->hwss.enable_accelerated_mode(core_dc);
- 	}
- 
-@@ -821,6 +821,7 @@ bool dc_commit_surfaces_to_target(
- 
- {
- 	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	struct dc_bios *dcb = core_dc->ctx->dc_bios;
- 
- 	int i, j;
- 	uint32_t prev_disp_clk = core_dc->current_context.bw_results.dispclk_khz;
-@@ -842,9 +843,8 @@ bool dc_commit_surfaces_to_target(
- 
- 	target_status = &context->target_status[i];
- 
--	if (!dal_adapter_service_is_in_accelerated_mode(
--						core_dc->res_pool.adapter_srv)
--		|| i == context->target_count) {
-+	if (!dcb->funcs->is_accelerated_mode(dcb)
-+			|| i == context->target_count) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0886-drm-amd-dal-Fixed-active-dongle-not-light-up-issue.patch b/common/recipes-kernel/linux/files/0886-drm-amd-dal-Fixed-active-dongle-not-light-up-issue.patch
deleted file mode 100644
index 46ba84f5..00000000
--- a/common/recipes-kernel/linux/files/0886-drm-amd-dal-Fixed-active-dongle-not-light-up-issue.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From d9a3ca6816f486312fee0a7639a1334b64463dd9 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Tue, 8 Mar 2016 15:18:18 -0500
-Subject: [PATCH 0886/1110] drm/amd/dal: Fixed active dongle not light up
- issue.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 68a167b..0232956 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -480,8 +480,8 @@ static void detect_dp(
- 
- 		/* DP active dongles */
- 		if (is_dp_active_dongle(link)) {
-+			link->public.type = dc_connection_active_dongle;
- 			if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
--				link->public.type = dc_connection_none;
- 				/*
- 				 * active dongle unplug processing for short irq
- 				 */
-@@ -607,7 +607,9 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 				&audio_support, boot);
- 
- 			/* Active dongle downstream unplug */
--			if (link->public.type == dc_connection_none)
-+			if (link->public.type == dc_connection_active_dongle
-+					&& link->dpcd_caps.sink_count.
-+					bits.SINK_COUNT == 0)
- 				return true;
- 
- 			if (link->public.type == dc_connection_mst_branch) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0887-drm-amd-dal-Move-crtc-timing-definitions-to-dc_hw_ty.patch b/common/recipes-kernel/linux/files/0887-drm-amd-dal-Move-crtc-timing-definitions-to-dc_hw_ty.patch
deleted file mode 100644
index 1f554d83..00000000
--- a/common/recipes-kernel/linux/files/0887-drm-amd-dal-Move-crtc-timing-definitions-to-dc_hw_ty.patch
+++ /dev/null
@@ -1,341 +0,0 @@
-From 9e513990a2e53959b0df3febe5d334ad357bec25 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 8 Mar 2016 17:37:39 -0500
-Subject: [PATCH 0887/1110] drm/amd/dal: Move crtc timing definitions to
- dc_hw_types header
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 157 ++++++++++++++++++++++++++++---
- drivers/gpu/drm/amd/dal/dc/dc_types.h    | 123 ------------------------
- 2 files changed, 142 insertions(+), 138 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-index bfe9955..9a92dd7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
-@@ -344,14 +344,7 @@ struct dc_cursor_attributes {
- };
- 
- /* OPP */
--enum dc_pixel_encoding {
--	PIXEL_ENCODING_UNDEFINED,
--	PIXEL_ENCODING_RGB,
--	PIXEL_ENCODING_YCBCR422,
--	PIXEL_ENCODING_YCBCR444,
--	PIXEL_ENCODING_YCBCR420,
--	PIXEL_ENCODING_COUNT
--};
-+
- 
- enum dc_color_space {
- 	COLOR_SPACE_UNKNOWN,
-@@ -365,6 +358,63 @@ enum dc_color_space {
- 	COLOR_SPACE_YCBCR709_LIMITED
- };
- 
-+
-+
-+/* XFM */
-+
-+/* used in  struct dc_surface */
-+struct scaling_taps {
-+	uint32_t v_taps;
-+	uint32_t h_taps;
-+	uint32_t v_taps_c;
-+	uint32_t h_taps_c;
-+};
-+
-+
-+enum dc_timing_standard {
-+	TIMING_STANDARD_UNDEFINED,
-+	TIMING_STANDARD_DMT,
-+	TIMING_STANDARD_GTF,
-+	TIMING_STANDARD_CVT,
-+	TIMING_STANDARD_CVT_RB,
-+	TIMING_STANDARD_CEA770,
-+	TIMING_STANDARD_CEA861,
-+	TIMING_STANDARD_HDMI,
-+	TIMING_STANDARD_TV_NTSC,
-+	TIMING_STANDARD_TV_NTSC_J,
-+	TIMING_STANDARD_TV_PAL,
-+	TIMING_STANDARD_TV_PAL_M,
-+	TIMING_STANDARD_TV_PAL_CN,
-+	TIMING_STANDARD_TV_SECAM,
-+	TIMING_STANDARD_EXPLICIT,
-+	/*!< For explicit timings from EDID, VBIOS, etc.*/
-+	TIMING_STANDARD_USER_OVERRIDE,
-+	/*!< For mode timing override by user*/
-+	TIMING_STANDARD_MAX
-+};
-+
-+enum dc_timing_3d_format {
-+	TIMING_3D_FORMAT_NONE,
-+	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
-+	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
-+	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
-+	/* for active DP-HDMI dongle*/
-+	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
-+	TIMING_3D_FORMAT_HW_FRAME_PACKING,
-+	TIMING_3D_FORMAT_SW_FRAME_PACKING,
-+	TIMING_3D_FORMAT_ROW_INTERLEAVE,
-+	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
-+	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
-+	TIMING_3D_FORMAT_SIDE_BY_SIDE,
-+	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
-+	TIMING_3D_FORMAT_SBS_SW_PACKED,
-+	/* Side-by-side, packed by application/driver into 2D frame*/
-+	TIMING_3D_FORMAT_TB_SW_PACKED,
-+	/* Top-and-bottom, packed by application/driver into 2D frame*/
-+
-+	TIMING_3D_FORMAT_MAX,
-+};
-+
- enum dc_color_depth {
- 	COLOR_DEPTH_UNDEFINED,
- 	COLOR_DEPTH_666,
-@@ -376,14 +426,91 @@ enum dc_color_depth {
- 	COLOR_DEPTH_COUNT
- };
- 
--/* XFM */
-+enum dc_pixel_encoding {
-+	PIXEL_ENCODING_UNDEFINED,
-+	PIXEL_ENCODING_RGB,
-+	PIXEL_ENCODING_YCBCR422,
-+	PIXEL_ENCODING_YCBCR444,
-+	PIXEL_ENCODING_YCBCR420,
-+	PIXEL_ENCODING_COUNT
-+};
- 
--/* used in  struct dc_surface */
--struct scaling_taps {
--	uint32_t v_taps;
--	uint32_t h_taps;
--	uint32_t v_taps_c;
--	uint32_t h_taps_c;
-+enum dc_aspect_ratio {
-+	ASPECT_RATIO_NO_DATA,
-+	ASPECT_RATIO_4_3,
-+	ASPECT_RATIO_16_9,
-+	ASPECT_RATIO_64_27,
-+	ASPECT_RATIO_256_135,
-+	ASPECT_RATIO_FUTURE
-+};
-+
-+enum scanning_type {
-+	SCANNING_TYPE_NODATA = 0,
-+	SCANNING_TYPE_OVERSCAN,
-+	SCANNING_TYPE_UNDERSCAN,
-+	SCANNING_TYPE_FUTURE,
-+	SCANNING_TYPE_UNDEFINED
-+};
-+
-+struct dc_crtc_timing_flags {
-+	uint32_t INTERLACE :1;
-+	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-+	 it is positive polarity --reversed with dal1 or video bios define*/
-+	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-+	 it is positive polarity --reversed with dal1 or video bios define*/
-+
-+	uint32_t HORZ_COUNT_BY_TWO:1;
-+
-+	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
-+	 timing can be driven in 3D format only
-+	 and there is no corresponding 2D timing*/
-+	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
-+	 (right eye = '1', left eye = '0') */
-+	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
-+	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
-+	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
-+	 because corresponding 2D timing also present in the list*/
-+	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
-+	 and we want to match priority of corresponding 3D timing*/
-+	uint32_t Y_ONLY :1;
-+
-+	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
-+	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
-+
-+	/* HDMI 2.0 - Support scrambling for TMDS character
-+	 * rates less than or equal to 340Mcsc */
-+	uint32_t LTE_340MCSC_SCRAMBLE:1;
-+
-+};
-+
-+struct dc_crtc_timing {
-+
-+	uint32_t h_total;
-+	uint32_t h_border_left;
-+	uint32_t h_addressable;
-+	uint32_t h_border_right;
-+	uint32_t h_front_porch;
-+	uint32_t h_sync_width;
-+
-+	uint32_t v_total;
-+	uint32_t v_border_top;
-+	uint32_t v_addressable;
-+	uint32_t v_border_bottom;
-+	uint32_t v_front_porch;
-+	uint32_t v_sync_width;
-+
-+	uint32_t pix_clk_khz;
-+
-+	uint32_t vic;
-+	uint32_t hdmi_vic;
-+	enum dc_timing_standard timing_standard;
-+	enum dc_timing_3d_format timing_3d_format;
-+	enum dc_color_depth display_color_depth;
-+	enum dc_pixel_encoding pixel_encoding;
-+	enum dc_aspect_ratio aspect_ratio;
-+	enum scanning_type scan_type;
-+
-+	struct dc_crtc_timing_flags flags;
- };
- 
- #endif /* DC_HW_TYPES_H */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index d3d105e..99da485 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -310,89 +310,6 @@ struct dc_mode_flags {
- 	uint32_t MIRACAST_REFRESH_DIVIDER;
- };
- 
--struct dc_crtc_timing_flags {
--	uint32_t INTERLACE :1;
--	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
--	 it is positive polarity --reversed with dal1 or video bios define*/
--	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
--	 it is positive polarity --reversed with dal1 or video bios define*/
--
--	uint32_t HORZ_COUNT_BY_TWO:1;
--
--	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
--	 timing can be driven in 3D format only
--	 and there is no corresponding 2D timing*/
--	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
--	 (right eye = '1', left eye = '0') */
--	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
--	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
--	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
--	 because corresponding 2D timing also present in the list*/
--	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
--	 and we want to match priority of corresponding 3D timing*/
--	uint32_t Y_ONLY :1;
--
--	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
--	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
--
--	/* HDMI 2.0 - Support scrambling for TMDS character
--	 * rates less than or equal to 340Mcsc */
--	uint32_t LTE_340MCSC_SCRAMBLE:1;
--
--};
--
--enum dc_timing_standard {
--	TIMING_STANDARD_UNDEFINED,
--	TIMING_STANDARD_DMT,
--	TIMING_STANDARD_GTF,
--	TIMING_STANDARD_CVT,
--	TIMING_STANDARD_CVT_RB,
--	TIMING_STANDARD_CEA770,
--	TIMING_STANDARD_CEA861,
--	TIMING_STANDARD_HDMI,
--	TIMING_STANDARD_TV_NTSC,
--	TIMING_STANDARD_TV_NTSC_J,
--	TIMING_STANDARD_TV_PAL,
--	TIMING_STANDARD_TV_PAL_M,
--	TIMING_STANDARD_TV_PAL_CN,
--	TIMING_STANDARD_TV_SECAM,
--	TIMING_STANDARD_EXPLICIT,
--	/*!< For explicit timings from EDID, VBIOS, etc.*/
--	TIMING_STANDARD_USER_OVERRIDE,
--	/*!< For mode timing override by user*/
--	TIMING_STANDARD_MAX
--};
--
--enum dc_aspect_ratio {
--	ASPECT_RATIO_NO_DATA,
--	ASPECT_RATIO_4_3,
--	ASPECT_RATIO_16_9,
--	ASPECT_RATIO_64_27,
--	ASPECT_RATIO_256_135,
--	ASPECT_RATIO_FUTURE
--};
--
--enum dc_timing_3d_format {
--	TIMING_3D_FORMAT_NONE,
--	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
--	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
--	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
--	/* for active DP-HDMI dongle*/
--	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
--	TIMING_3D_FORMAT_HW_FRAME_PACKING,
--	TIMING_3D_FORMAT_SW_FRAME_PACKING,
--	TIMING_3D_FORMAT_ROW_INTERLEAVE,
--	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
--	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
--	TIMING_3D_FORMAT_SIDE_BY_SIDE,
--	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
--	TIMING_3D_FORMAT_SBS_SW_PACKED,
--	/* Side-by-side, packed by application/driver into 2D frame*/
--	TIMING_3D_FORMAT_TB_SW_PACKED,
--	/* Top-and-bottom, packed by application/driver into 2D frame*/
--
--	TIMING_3D_FORMAT_MAX,
--};
- 
- enum dc_timing_source {
- 	TIMING_SOURCE_UNDEFINED,
-@@ -454,46 +371,6 @@ struct dc_mode_info {
- 	struct dc_mode_flags flags;
- };
- 
--/* TODO: assess necessity*/
--/*scanning type*/
--enum scanning_type {
--	SCANNING_TYPE_NODATA = 0,
--	SCANNING_TYPE_OVERSCAN,
--	SCANNING_TYPE_UNDERSCAN,
--	SCANNING_TYPE_FUTURE,
--	SCANNING_TYPE_UNDEFINED
--};
--
--struct dc_crtc_timing {
--
--	uint32_t h_total;
--	uint32_t h_border_left;
--	uint32_t h_addressable;
--	uint32_t h_border_right;
--	uint32_t h_front_porch;
--	uint32_t h_sync_width;
--
--	uint32_t v_total;
--	uint32_t v_border_top;
--	uint32_t v_addressable;
--	uint32_t v_border_bottom;
--	uint32_t v_front_porch;
--	uint32_t v_sync_width;
--
--	uint32_t pix_clk_khz;
--
--	uint32_t vic;
--	uint32_t hdmi_vic;
--	enum dc_timing_standard timing_standard;
--	enum dc_timing_3d_format timing_3d_format;
--	enum dc_color_depth display_color_depth;
--	enum dc_pixel_encoding pixel_encoding;
--	enum dc_aspect_ratio aspect_ratio;
--	enum scanning_type scan_type;
--
--	struct dc_crtc_timing_flags flags;
--};
--
- struct dc_mode_timing {
- 	struct dc_mode_info mode_info;
- 	struct dc_crtc_timing crtc_timing;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0888-drm-amd-dal-skip-MST-fake-connectors-on-resume.patch b/common/recipes-kernel/linux/files/0888-drm-amd-dal-skip-MST-fake-connectors-on-resume.patch
deleted file mode 100644
index 5cd092b4..00000000
--- a/common/recipes-kernel/linux/files/0888-drm-amd-dal-skip-MST-fake-connectors-on-resume.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 09ed2790db75c799a013646a1c74a4675157bf71 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 8 Mar 2016 05:17:06 -0500
-Subject: [PATCH 0888/1110] drm/amd/dal: skip MST fake connectors on resume
-
-This change is needed in order to avoid multiple dc_link_detect
-calls on one DP link.
-
-Also it disables removal of sink from connector hence allow
-to restore mode on resume.
-
-However this is only partial fix. Additional change will be
-provided in order to fix topology change
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index a9973ed..5bef63c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -587,6 +587,14 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	list_for_each_entry(connector,
- 			&ddev->mode_config.connector_list, head) {
- 		aconnector = to_amdgpu_connector(connector);
-+
-+		/*
-+		 * this is the case when traversing through already created
-+		 * MST connectors, should be skipped
-+		 */
-+		if (aconnector->mst_port)
-+			continue;
-+
- 		dc_link_detect(aconnector->dc_link, false);
- 		aconnector->dc_sink = NULL;
- 		amdgpu_dm_update_connector_after_detect(aconnector);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0889-drm-amd-dal-Allow-for-ASIC-specific-bw_calcs.patch b/common/recipes-kernel/linux/files/0889-drm-amd-dal-Allow-for-ASIC-specific-bw_calcs.patch
deleted file mode 100644
index ee50a086..00000000
--- a/common/recipes-kernel/linux/files/0889-drm-amd-dal-Allow-for-ASIC-specific-bw_calcs.patch
+++ /dev/null
@@ -1,399 +0,0 @@
-From 07981bae0a25f2a3dfbc171245b5dd6a8903cb61 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 7 Mar 2016 11:08:23 -0500
-Subject: [PATCH 0889/1110] drm/amd/dal: Allow for ASIC specific bw_calcs
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 199 ++++++++++++---------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  50 ------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  51 ++++++
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |   8 +-
- 4 files changed, 168 insertions(+), 140 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index ca17b25..52557db 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3568,101 +3568,122 @@ static void calculate_bandwidth(
- /*******************************************************************************
-  * Public functions
-  ******************************************************************************/
--
- void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
--	struct bw_calcs_vbios *bw_vbios)
-+	struct bw_calcs_vbios *bw_vbios,
-+	enum bw_calcs_version version)
- {
- 	struct bw_calcs_dceip dceip = {{ 0 }};
- 	struct bw_calcs_vbios vbios = { 0 };
- 
--	vbios.number_of_dram_channels = 2;
--	vbios.dram_channel_width_in_bits = 64;
--	vbios.number_of_dram_banks = 8;
--	vbios.high_yclk = bw_int_to_fixed(1600);
--	vbios.mid_yclk = bw_int_to_fixed(1600);
--	vbios.low_yclk = bw_frc_to_fixed(66666, 100);
--	vbios.low_sclk = bw_int_to_fixed(200);
--	vbios.mid_sclk = bw_int_to_fixed(300);
--	vbios.high_sclk = bw_frc_to_fixed(62609, 100);
--	vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
--	vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
--	vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
--	vbios.data_return_bus_width = bw_int_to_fixed(32);
--	vbios.trc = bw_int_to_fixed(50);
--	vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
--	vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 10);
--	vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
--	vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
--	vbios.scatter_gather_enable = true;
--	vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
--	vbios.cursor_width = 32;
--	vbios.average_compression_rate = 4;
--	vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
--	vbios.blackout_duration = bw_int_to_fixed(18); /* us */
--	vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
--
--	dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
--	dceip.de_tiling_buffer = bw_int_to_fixed(0);
--	dceip.dcfclk_request_generation = 0;
--	dceip.lines_interleaved_into_lb = 2;
--	dceip.chunk_width = 256;
--	dceip.number_of_graphics_pipes = 3;
--	dceip.number_of_underlay_pipes = 1;
--	dceip.display_write_back_supported = false;
--	dceip.argb_compression_support = false;
--	dceip.underlay_vscaler_efficiency6_bit_per_component = bw_frc_to_fixed(
--		35556, 10000);
--	dceip.underlay_vscaler_efficiency8_bit_per_component = bw_frc_to_fixed(
--		34286, 10000);
--	dceip.underlay_vscaler_efficiency10_bit_per_component = bw_frc_to_fixed(32,
--		10);
--	dceip.underlay_vscaler_efficiency12_bit_per_component = bw_int_to_fixed(3);
--	dceip.graphics_vscaler_efficiency6_bit_per_component = bw_frc_to_fixed(35,
--		10);
--	dceip.graphics_vscaler_efficiency8_bit_per_component = bw_frc_to_fixed(
--		34286, 10000);
--	dceip.graphics_vscaler_efficiency10_bit_per_component = bw_frc_to_fixed(32,
--		10);
--	dceip.graphics_vscaler_efficiency12_bit_per_component = bw_int_to_fixed(3);
--	dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
--	dceip.max_dmif_buffer_allocated = 2;
--	dceip.graphics_dmif_size = 12288;
--	dceip.underlay_luma_dmif_size = 19456;
--	dceip.underlay_chroma_dmif_size = 23552;
--	dceip.pre_downscaler_enabled = true;
--	dceip.underlay_downscale_prefetch_enabled = true;
--	dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
--	dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
--	dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
--	dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
--		bw_int_to_fixed(0);
--	dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(82176);
--	dceip.underlay420_chroma_lb_size_per_component = bw_int_to_fixed(164352);
--	dceip.underlay422_lb_size_per_component = bw_int_to_fixed(82176);
--	dceip.cursor_chunk_width = bw_int_to_fixed(64);
--	dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
--	dceip.cursor_memory_interface_buffer_pixels = bw_int_to_fixed(64);
--	dceip.underlay_maximum_width_efficient_for_tiling = bw_int_to_fixed(1920);
--	dceip.underlay_maximum_height_efficient_for_tiling = bw_int_to_fixed(1080);
--	dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
--		bw_frc_to_fixed(3, 10);
--	dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
--		bw_int_to_fixed(25);
--	dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(2);
--	dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
--		bw_int_to_fixed(128);
--	dceip.limit_excessive_outstanding_dmif_requests = true;
--	dceip.linear_mode_line_request_alternation_slice = bw_int_to_fixed(64);
--	dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode = 32;
--	dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
--	dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
--	dceip.request_efficiency = bw_frc_to_fixed(8, 10);
--	dceip.dispclk_per_request = bw_int_to_fixed(2);
--	dceip.dispclk_ramping_factor = bw_frc_to_fixed(11, 10);
--	dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
--	dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
--	dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
-+	switch (version) {
-+	case BW_CALCS_VERSION_CARRIZO:
-+		vbios.number_of_dram_channels = 2;
-+		vbios.dram_channel_width_in_bits = 64;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(1600);
-+		vbios.mid_yclk = bw_int_to_fixed(1600);
-+		vbios.low_yclk = bw_frc_to_fixed(66666, 100);
-+		vbios.low_sclk = bw_int_to_fixed(200);
-+		vbios.mid_sclk = bw_int_to_fixed(300);
-+		vbios.high_sclk = bw_frc_to_fixed(62609, 100);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(50);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-+		vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(
-+			153,
-+			10);
-+		vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel =
-+			256;
-+		vbios.blackout_duration = bw_int_to_fixed(18); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
- 
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.de_tiling_buffer = bw_int_to_fixed(0);
-+		dceip.dcfclk_request_generation = 0;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 3;
-+		dceip.number_of_underlay_pipes = 1;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = false;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 2;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(0);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.cursor_memory_interface_buffer_pixels = bw_int_to_fixed(
-+			64);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(11, 10);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(
-+			105,
-+			100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
-+		break;
-+	default:
-+		break;
-+	}
- 	*bw_dceip = dceip;
- 	*bw_vbios = vbios;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 4c775f6..f8459a3 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -200,52 +200,6 @@ static struct adapter_service *create_as(
- 	return as;
- }
- 
--static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
--{
--	struct dm_pp_clock_levels clks = {0};
--
--	/*do system clock*/
--	dm_pp_get_clock_levels_by_type(
--			dc->ctx,
--			DM_PP_CLOCK_TYPE_ENGINE_CLK,
--			&clks);
--	/* convert all the clock fro kHz to fix point mHz */
--	dc->bw_vbios.high_sclk = bw_frc_to_fixed(
--			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	dc->bw_vbios.mid_sclk  = bw_frc_to_fixed(
--			clks.clocks_in_khz[clks.num_levels>>1], 1000);
--	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
--			clks.clocks_in_khz[0], 1000);
--
--	/*do display clock*/
--	dm_pp_get_clock_levels_by_type(
--			dc->ctx,
--			DM_PP_CLOCK_TYPE_DISPLAY_CLK,
--			&clks);
--
--	dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
--			clks.clocks_in_khz[clks.num_levels-1], 1000);
--	dc->bw_vbios.mid_voltage_max_dispclk  = bw_frc_to_fixed(
--			clks.clocks_in_khz[clks.num_levels>>1], 1000);
--	dc->bw_vbios.low_voltage_max_dispclk  = bw_frc_to_fixed(
--			clks.clocks_in_khz[0], 1000);
--
--	/*do memory clock*/
--	dm_pp_get_clock_levels_by_type(
--			dc->ctx,
--			DM_PP_CLOCK_TYPE_MEMORY_CLK,
--			&clks);
--
--	dc->bw_vbios.low_yclk = bw_frc_to_fixed(
--		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
--	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
--		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
--		1000);
--	dc->bw_vbios.high_yclk = bw_frc_to_fixed(
--		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
--		1000);
--}
--
- static bool construct(struct core_dc *dc, const struct dc_init_data *init_params)
- {
- 	struct dal_logger *logger;
-@@ -305,10 +259,6 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 
- 		if (!create_links(dc, as, init_params->num_virtual_links))
- 			goto create_links_fail;
--
--		bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios);
--
--		bw_calcs_data_update_from_pplib(dc);
- 	} else {
- 
- 		/* Resource should construct all asic specific resources.
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index f02335e..b8fc445 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -1000,6 +1000,52 @@ static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
- 	pool->pipe_count++;
- }
- 
-+static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
-+{
-+	struct dm_pp_clock_levels clks = {0};
-+
-+	/*do system clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_ENGINE_CLK,
-+			&clks);
-+	/* convert all the clock fro kHz to fix point mHz */
-+	dc->bw_vbios.high_sclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.mid_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do display clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_DISPLAY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.mid_voltage_max_dispclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios.low_voltage_max_dispclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do memory clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios.low_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
-+	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+	dc->bw_vbios.high_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+}
-+
- bool dce110_construct_resource_pool(
- 	struct adapter_service *as,
- 	uint8_t num_virtual_links,
-@@ -1181,10 +1227,15 @@ bool dce110_construct_resource_pool(
- 		pool->stream_enc_count++;
- 	}
- 
-+
- 	/* Create hardware sequencer */
- 	if (!dc_construct_hw_sequencer(as, dc))
- 		goto stream_enc_create_fail;
- 
-+	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO);
-+
-+	bw_calcs_data_update_from_pplib(dc);
-+
- 	return true;
- 
- stream_enc_create_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index 2adad08..ff1ea09 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -483,12 +483,18 @@ struct bw_calcs_output {
- 	int32_t required_blackout_duration_us;
- };
- 
-+enum bw_calcs_version {
-+	BW_CALCS_VERSION_INVALID,
-+	BW_CALCS_VERSION_CARRIZO
-+};
-+
- /**
-  * Initialize structures with data which will NOT change at runtime.
-  */
- void bw_calcs_init(
- 	struct bw_calcs_dceip *bw_dceip,
--	struct bw_calcs_vbios *bw_vbios);
-+	struct bw_calcs_vbios *bw_vbios,
-+	enum bw_calcs_version version);
- 
- /**
-  * Return:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0890-drm-amd-dal-initial-framework-for-s3-debugging.patch b/common/recipes-kernel/linux/files/0890-drm-amd-dal-initial-framework-for-s3-debugging.patch
deleted file mode 100644
index 9b43e81f..00000000
--- a/common/recipes-kernel/linux/files/0890-drm-amd-dal-initial-framework-for-s3-debugging.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From d9d03b7b657d80cf163e650f8c6afc60d114e6f7 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Mar 2016 05:45:11 -0500
-Subject: [PATCH 0890/1110] drm/amd/dal: initial framework for s3 debugging
-
-Adds sysfs driver property to trigger suspend/resume
-sequences, thus allow to debug through them w/o actual
-s3.
-
-E.g.
-
-will trigger suspend sequence and
-
-will trigger resume sequence.
-
-Currently it only supports DAL s3 sequences, but could be
-expanded to support whole driver sequence.
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 37 +++++++++++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 5bef63c..bf4ad69 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1232,6 +1232,38 @@ static const struct amdgpu_display_funcs dm_dce_v11_0_display_funcs = {
- 	.resume_mc_access = dce_v11_0_resume_mc_access, /* called unconditionally */
- };
- 
-+#if defined(CONFIG_DEBUG_KERNEL_DAL)
-+
-+static ssize_t s3_debug_store(
-+	struct device *device,
-+	struct device_attribute *attr,
-+	const char *buf,
-+	size_t count)
-+{
-+	int ret;
-+	int s3_state;
-+	struct pci_dev *pdev = to_pci_dev(device);
-+	struct drm_device *drm_dev = pci_get_drvdata(pdev);
-+	struct amdgpu_device *adev = drm_dev->dev_private;
-+
-+	ret = kstrtoint(buf, 0, &s3_state);
-+
-+	if (ret == 0) {
-+		if (s3_state) {
-+			dm_resume(adev);
-+			amdgpu_dm_display_resume(adev);
-+			drm_kms_helper_hotplug_event(adev->ddev);
-+		} else
-+			dm_suspend(adev);
-+	}
-+
-+	return ret == 0 ? count : 0;
-+}
-+
-+DEVICE_ATTR_WO(s3_debug);
-+
-+#endif
-+
- static int dm_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -1279,6 +1311,11 @@ static int dm_early_init(void *handle)
- 	/* Note: Do NOT change adev->audio_endpt_rreg and
- 	 * adev->audio_endpt_wreg because they are initialised in
- 	 * amdgpu_device_init() */
-+#if defined(CONFIG_DEBUG_KERNEL_DAL)
-+	device_create_file(
-+		adev->ddev->dev,
-+		&dev_attr_s3_debug);
-+#endif
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0891-drm-amd-dal-Use-fine-grained-watermarks-for-support-.patch b/common/recipes-kernel/linux/files/0891-drm-amd-dal-Use-fine-grained-watermarks-for-support-.patch
deleted file mode 100644
index bf7269c0..00000000
--- a/common/recipes-kernel/linux/files/0891-drm-amd-dal-Use-fine-grained-watermarks-for-support-.patch
+++ /dev/null
@@ -1,263 +0,0 @@
-From 7821e089e8f8d7ec06df41a2e4ca7453f0c1af79 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 8 Mar 2016 17:35:27 -0500
-Subject: [PATCH 0891/1110] drm/amd/dal: Use fine-grained watermarks for
- support new ASICs
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 89 +++++++++++++++++++---
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  6 +-
- .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 13 ++--
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  2 +
- drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h      |  3 +-
- 5 files changed, 94 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index 52557db..c64efe6 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3879,6 +3879,41 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 				bw_mul(high_yclk, bw_int_to_fixed(1000)));
- 
- 		/* units: nanosecond, 16bit storage. */
-+		calcs_output->nbp_state_change_wm_ns[0].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[1].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[2].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+
-+		calcs_output->stutter_exit_wm_ns[0].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[1].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[2].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+
-+		calcs_output->urgent_wm_ns[0].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[1].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[2].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[6], bw_int_to_fixed(1000)));
-+
-+		/*TODO check correctness*/
-+		((struct bw_calcs_vbios *)vbios)->low_sclk = mid_sclk;
-+		calculate_bandwidth(dceip, vbios, bw_data_internal,
-+							bw_results_internal);
-+
- 		calcs_output->nbp_state_change_wm_ns[0].b_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[4],bw_int_to_fixed(1000)));
-@@ -3909,6 +3944,42 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[6], bw_int_to_fixed(1000)));
- 
-+		/*TODO check correctness*/
-+		((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
-+		((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
-+		calculate_bandwidth(dceip, vbios, bw_data_internal,
-+							bw_results_internal);
-+
-+		calcs_output->nbp_state_change_wm_ns[0].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[1].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[2].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+
-+		calcs_output->stutter_exit_wm_ns[0].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[1].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[2].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+
-+		calcs_output->urgent_wm_ns[0].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[1].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[2].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[6], bw_int_to_fixed(1000)));
-+
- 		((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
- 		((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
- 		((struct bw_calcs_vbios *)vbios)->low_sclk = high_sclk;
-@@ -3917,33 +3988,33 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calculate_bandwidth(dceip, vbios, bw_data_internal,
- 							bw_results_internal);
- 
--		calcs_output->nbp_state_change_wm_ns[0].a_mark =
-+		calcs_output->nbp_state_change_wm_ns[0].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
--		calcs_output->nbp_state_change_wm_ns[1].a_mark =
-+		calcs_output->nbp_state_change_wm_ns[1].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
--		calcs_output->nbp_state_change_wm_ns[2].a_mark =
-+		calcs_output->nbp_state_change_wm_ns[2].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
- 
--		calcs_output->stutter_exit_wm_ns[0].a_mark =
-+		calcs_output->stutter_exit_wm_ns[0].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
--		calcs_output->stutter_exit_wm_ns[1].a_mark =
-+		calcs_output->stutter_exit_wm_ns[1].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
--		calcs_output->stutter_exit_wm_ns[2].a_mark =
-+		calcs_output->stutter_exit_wm_ns[2].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
- 
--		calcs_output->urgent_wm_ns[0].a_mark =
-+		calcs_output->urgent_wm_ns[0].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[4], bw_int_to_fixed(1000)));
--		calcs_output->urgent_wm_ns[1].a_mark =
-+		calcs_output->urgent_wm_ns[1].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[5], bw_int_to_fixed(1000)));
--		calcs_output->urgent_wm_ns[2].a_mark =
-+		calcs_output->urgent_wm_ns[2].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[6], bw_int_to_fixed(1000)));
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index defaac4..80faa98 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1172,8 +1172,10 @@ static void set_displaymarks(
- static void set_safe_displaymarks(struct resource_context *res_ctx)
- {
- 	uint8_t i;
--	struct bw_watermarks max_marks = { MAX_WATERMARK, MAX_WATERMARK };
--	struct bw_watermarks nbp_marks = { SAFE_NBP_MARK, SAFE_NBP_MARK };
-+	struct bw_watermarks max_marks = {
-+		MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
-+	struct bw_watermarks nbp_marks = {
-+		SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
- 
- 	for (i = 0; i < MAX_PIPES; i++) {
- 		if (res_ctx->pipe_ctx[i].stream == NULL)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index e7fc5bd..6f3ca2d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -32,7 +32,6 @@
- 
- #include "include/logger_interface.h"
- #include "adapter_service_interface.h"
--#include "inc/bandwidth_calcs.h"
- 
- #include "dce110_mem_input.h"
- 
-@@ -442,7 +441,7 @@ static void program_urgency_watermark(
- 
- 	set_reg_field_value(
- 		urgency_cntl,
--		marks_low.a_mark,
-+		marks_low.d_mark,
- 		DPG_PIPE_URGENCY_CONTROL,
- 		URGENCY_LOW_WATERMARK);
- 
-@@ -464,7 +463,7 @@ static void program_urgency_watermark(
- 	urgency_cntl = dm_read_reg(ctx, urgency_addr);
- 
- 	set_reg_field_value(urgency_cntl,
--		marks_low.b_mark,
-+		marks_low.a_mark,
- 		DPG_PIPE_URGENCY_CONTROL,
- 		URGENCY_LOW_WATERMARK);
- 
-@@ -509,7 +508,7 @@ static void program_stutter_watermark(
- 
- 	/*Write watermark set A*/
- 	set_reg_field_value(stutter_cntl,
--		marks.a_mark,
-+		marks.d_mark,
- 		DPG_PIPE_STUTTER_CONTROL,
- 		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
- 	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-@@ -534,7 +533,7 @@ static void program_stutter_watermark(
- 
- 	/*Write watermark set B*/
- 	set_reg_field_value(stutter_cntl,
--		marks.b_mark,
-+		marks.a_mark,
- 		DPG_PIPE_STUTTER_CONTROL,
- 		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
- 	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-@@ -580,7 +579,7 @@ static void program_nbp_watermark(
- 	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
--		marks.a_mark,
-+		marks.d_mark,
- 		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- 		NB_PSTATE_CHANGE_WATERMARK);
- 	dm_write_reg(ctx, addr, value);
-@@ -618,7 +617,7 @@ static void program_nbp_watermark(
- 	value = dm_read_reg(ctx, addr);
- 	set_reg_field_value(
- 		value,
--		marks.b_mark,
-+		marks.a_mark,
- 		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
- 		NB_PSTATE_CHANGE_WATERMARK);
- 	dm_write_reg(ctx, addr, value);
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index ff1ea09..023efd3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -465,6 +465,8 @@ struct bw_calcs_results {
- struct bw_watermarks {
- 	uint32_t a_mark;
- 	uint32_t b_mark;
-+	uint32_t c_mark;
-+	uint32_t d_mark;
- };
- 
- struct bw_calcs_output {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-index 3829694..6d7412c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
-@@ -25,8 +25,9 @@
- #ifndef __DAL_MEM_INPUT_H__
- #define __DAL_MEM_INPUT_H__
- 
--#include "include/grph_object_id.h"
- #include "dc.h"
-+#include "include/grph_object_id.h"
-+#include "inc/bandwidth_calcs.h"
- 
- struct mem_input {
- 	struct mem_input_funcs *funcs;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0892-drm-amd-dal-enable-hpd-rx-irqs-earlier-on-resume.patch b/common/recipes-kernel/linux/files/0892-drm-amd-dal-enable-hpd-rx-irqs-earlier-on-resume.patch
deleted file mode 100644
index aaf9e23b..00000000
--- a/common/recipes-kernel/linux/files/0892-drm-amd-dal-enable-hpd-rx-irqs-earlier-on-resume.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-From 692020a27565d2c20016de433e81108e48bbdd20 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 9 Mar 2016 01:15:00 -0500
-Subject: [PATCH 0892/1110] drm/amd/dal: enable hpd rx irqs earlier on resume
-
-This is needed to correctly process MST mode set
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c     | 12 ++++++++---
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 26 +++++++++++++++++++++--
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h |  8 +++----
- 3 files changed, 37 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index bf4ad69..c06f126 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -583,6 +583,15 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	struct drm_connector *connector;
- 	int ret = 0;
- 
-+	/* program HPD filter */
-+	dc_resume(dm->dc);
-+
-+	/*
-+	 * early enable HPD Rx IRQ, should be done before set mode as short
-+	 * pulse interrupts are used for MST
-+	 */
-+	amdgpu_dm_irq_resume_early(adev);
-+
- 	/* Do detection*/
- 	list_for_each_entry(connector,
- 			&ddev->mode_config.connector_list, head) {
-@@ -606,9 +615,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 
- 	drm_kms_helper_hotplug_event(ddev);
- 
--	/* program HPD filter*/
--	dc_resume(dm->dc);
--	/* resume IRQ */
- 	amdgpu_dm_irq_resume(adev);
- 
- 	return ret;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index 2757c5c..f6d7920 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -522,8 +522,30 @@ int amdgpu_dm_irq_suspend(
- 	return 0;
- }
- 
--int amdgpu_dm_irq_resume(
--	struct amdgpu_device *adev)
-+int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct list_head *hnd_list_h, *hnd_list_l;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: early resume\n");
-+
-+	/* re-enable short pulse interrupts HW interrupt */
-+	for (src = DC_IRQ_SOURCE_HPD1RX; src < DC_IRQ_SOURCE_HPD6RX + 1; src++) {
-+		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
-+		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
-+		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
-+			dc_interrupt_set(adev->dm.dc, src, true);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	return 0;
-+}
-+
-+int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
- {
- 	int src;
- 	struct list_head *hnd_list_h, *hnd_list_l;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-index afedb50..9339861 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-@@ -109,14 +109,14 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
-  * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
-  *
-  */
--int amdgpu_dm_irq_suspend(
--	struct amdgpu_device *adev);
-+int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
- 
- /**
-+ * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
-  * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
-  *
-  */
--int amdgpu_dm_irq_resume(
--	struct amdgpu_device *adev);
-+int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
-+int amdgpu_dm_irq_resume(struct amdgpu_device *adev);
- 
- #endif /* __AMDGPU_DM_IRQ_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0893-drm-amd-dal-Fixed-DP-passive-dongle-not-light-up-iss.patch b/common/recipes-kernel/linux/files/0893-drm-amd-dal-Fixed-DP-passive-dongle-not-light-up-iss.patch
deleted file mode 100644
index 79ad2581..00000000
--- a/common/recipes-kernel/linux/files/0893-drm-amd-dal-Fixed-DP-passive-dongle-not-light-up-iss.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From f9c3ad9cf9ffb05ce4f2b0ea5f58f81415594c57 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 9 Mar 2016 14:56:16 -0500
-Subject: [PATCH 0893/1110] drm/amd/dal: Fixed DP passive dongle not light up
- issue
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 0232956..fd406f9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -99,7 +99,13 @@ static bool program_hpd_filter(
- 	case SIGNAL_TYPE_DISPLAY_PORT:
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 		/* Program hpd filter to allow DP signal to settle */
--		delay_on_connect_in_ms = 20;
-+		/* 500:	not able to detect MST <-> SST switch as HPD is low for
-+		 * 	only 100ms on DELL U2413
-+		 * 0:	some passive dongle still show aux mode instead of i2c
-+		 * 20-50:not enough to hide bouncing HPD with passive dongle.
-+		 * 	also see intermittent i2c read issues.
-+		 */
-+		delay_on_connect_in_ms = 80;
- 		delay_on_disconnect_in_ms = 0;
- 		break;
- 	case SIGNAL_TYPE_LVDS:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0894-drm-amd-dal-allocate-structures-in-temp_params-separ.patch b/common/recipes-kernel/linux/files/0894-drm-amd-dal-allocate-structures-in-temp_params-separ.patch
deleted file mode 100644
index 0ceb1fee..00000000
--- a/common/recipes-kernel/linux/files/0894-drm-amd-dal-allocate-structures-in-temp_params-separ.patch
+++ /dev/null
@@ -1,183 +0,0 @@
-From 79ec3f43623e99119beb903e1e4214744dc25f6d Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 9 Mar 2016 17:09:53 -0500
-Subject: [PATCH 0894/1110] drm/amd/dal: allocate structures in temp_params
- separately
-
-The temp_params structure was very big (117648 bytes) and fails
-to allocate on some systems in suspend/resume. This causes gamma
-to not be programmed and color corruption seen on resume.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c     | 62 ++++++++++++++++++----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 15 ++----
- drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h       | 14 +----
- 3 files changed, 57 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-index 9c18bda..0ddd961 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/gamma_calcs.c
-@@ -1284,22 +1284,47 @@ static bool convert_to_custom_float(
- 	return true;
- }
- 
--void calculate_regamma_params(struct pwl_params *params,
--		struct temp_params *temp_params,
-+bool calculate_regamma_params(struct pwl_params *params,
- 		const struct core_gamma *ramp,
- 		const struct core_surface *surface)
- {
- 	struct gamma_curve *arr_curve_points = params->arr_curve_points;
- 	struct curve_points *arr_points = params->arr_points;
--	struct hw_x_point *coordinates_x = temp_params->coordinates_x;
--	struct pwl_float_data *rgb_user = temp_params->rgb_user;
--	struct pwl_float_data_ex *rgb_regamma = temp_params->rgb_regamma;
--	struct pwl_float_data *rgb_oem = temp_params->rgb_oem;
- 	struct pwl_result_data *rgb_resulted = params->rgb_resulted;
- 	struct dividers dividers;
--	struct gamma_pixel *axix_x_256 = temp_params->axix_x_256;
--	struct pixel_gamma_point *coeff128_oem = temp_params->coeff128_oem;
--	struct pixel_gamma_point *coeff128 = temp_params->coeff128;
-+
-+	struct hw_x_point *coordinates_x = NULL;
-+	struct pwl_float_data *rgb_user = NULL ;
-+	struct pwl_float_data_ex *rgb_regamma = NULL;
-+	struct pwl_float_data *rgb_oem = NULL;
-+	struct gamma_pixel *axix_x_256 = NULL;
-+	struct pixel_gamma_point *coeff128_oem = NULL;
-+	struct pixel_gamma_point *coeff128 = NULL;
-+
-+
-+	bool ret = false;
-+
-+	coordinates_x = dm_alloc(sizeof(*coordinates_x)*(256 + 3));
-+	if (!coordinates_x)
-+		goto coordinates_x_alloc_fail;
-+	rgb_user = dm_alloc(sizeof(*rgb_user) * (FLOAT_GAMMA_RAMP_MAX + 3));
-+	if (!rgb_user)
-+		goto rgb_user_alloc_fail;
-+	rgb_regamma = dm_alloc(sizeof(*rgb_regamma) * (256 + 3));
-+	if (!rgb_regamma)
-+		goto rgb_regamma_alloc_fail;
-+	rgb_oem = dm_alloc(sizeof(*rgb_oem) * (FLOAT_GAMMA_RAMP_MAX + 3));
-+	if (!rgb_oem)
-+		goto rgb_oem_alloc_fail;
-+	axix_x_256 = dm_alloc(sizeof(*axix_x_256) * 256);
-+	if (!axix_x_256)
-+		goto axix_x_256_alloc_fail;
-+	coeff128_oem = dm_alloc(sizeof(*coeff128_oem) * (256 + 3));
-+	if (!coeff128_oem)
-+		goto coeff128_oem_alloc_fail;
-+	coeff128 = dm_alloc(sizeof(*coeff128) * (256 + 3));
-+	if (!coeff128)
-+		goto coeff128_alloc_fail;
- 
- 	dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
- 	dividers.divider2 = dal_fixed31_32_from_int(2);
-@@ -1334,5 +1359,24 @@ void calculate_regamma_params(struct pwl_params *params,
- 
- 	convert_to_custom_float(rgb_resulted, arr_points,
- 			params->hw_points_num);
-+
-+	ret = true;
-+
-+	dm_free(coeff128);
-+coeff128_alloc_fail:
-+	dm_free(coeff128_oem);
-+coeff128_oem_alloc_fail:
-+	dm_free(axix_x_256);
-+axix_x_256_alloc_fail:
-+	dm_free(rgb_oem);
-+rgb_oem_alloc_fail:
-+	dm_free(rgb_regamma);
-+rgb_regamma_alloc_fail:
-+	dm_free(rgb_user);
-+rgb_user_alloc_fail:
-+	dm_free(coordinates_x);
-+coordinates_x_alloc_fail:
-+	return ret;
-+
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 80faa98..fae2f8a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -512,7 +512,6 @@ static bool set_gamma_ramp(
- {
- 	struct ipp_prescale_params *prescale_params;
- 	struct pwl_params *regamma_params;
--	struct temp_params *temp_params;
- 	bool result = false;
- 
- 	prescale_params = dm_alloc(sizeof(struct ipp_prescale_params));
-@@ -524,11 +523,6 @@ static bool set_gamma_ramp(
- 	if (regamma_params == NULL)
- 		goto regamma_alloc_fail;
- 
--	temp_params = dm_alloc(sizeof(struct temp_params));
--
--	if (temp_params == NULL)
--		goto temp_alloc_fail;
--
- 	regamma_params->hw_points_num = GAMMA_HW_POINTS_NUM;
- 
- 	opp->funcs->opp_power_on_regamma_lut(opp, true);
-@@ -538,9 +532,8 @@ static bool set_gamma_ramp(
- 		ipp->funcs->ipp_program_prescale(ipp, prescale_params);
- 	}
- 
--	if (ramp) {
--		calculate_regamma_params(regamma_params,
--				temp_params, ramp, surface);
-+	if (ramp && calculate_regamma_params(regamma_params, ramp, surface)) {
-+
- 		opp->funcs->opp_program_regamma_pwl(opp, regamma_params);
- 		if (ipp)
- 			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
-@@ -553,12 +546,10 @@ static bool set_gamma_ramp(
- 
- 	opp->funcs->opp_power_on_regamma_lut(opp, false);
- 
--	dm_free(temp_params);
--
- 	result = true;
- 
--temp_alloc_fail:
- 	dm_free(regamma_params);
-+
- regamma_alloc_fail:
- 	dm_free(prescale_params);
- prescale_alloc_fail:
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-index baab77a..2064f28 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_calcs.h
-@@ -12,19 +12,7 @@
- #include "core_types.h"
- #include "dc.h"
- 
--struct temp_params {
--	struct hw_x_point coordinates_x[256 + 3];
--	struct pwl_float_data rgb_user[FLOAT_GAMMA_RAMP_MAX + 3];
--	struct pwl_float_data_ex rgb_regamma[256 + 3];
--	struct pwl_float_data rgb_oem[FLOAT_GAMMA_RAMP_MAX + 3];
--	struct gamma_pixel axix_x_256[256];
--	struct pixel_gamma_point coeff128_oem[256 + 3];
--	struct pixel_gamma_point coeff128[256 + 3];
--
--};
--
--void calculate_regamma_params(struct pwl_params *params,
--		struct temp_params *temp_params,
-+bool calculate_regamma_params(struct pwl_params *params,
- 		const struct core_gamma *ramp,
- 		const struct core_surface *surface);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0895-drm-amd-dal-simplify-suspend-resume-sequence.patch b/common/recipes-kernel/linux/files/0895-drm-amd-dal-simplify-suspend-resume-sequence.patch
deleted file mode 100644
index 14c8256d..00000000
--- a/common/recipes-kernel/linux/files/0895-drm-amd-dal-simplify-suspend-resume-sequence.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 417422b7f5a2f0e37d178939a809f9dfc0ade509 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 8 Mar 2016 05:11:36 -0500
-Subject: [PATCH 0895/1110] drm/amd/dal: simplify suspend/resume sequence
-
-Code that changes state to reset modes on suspend is removed
-as reset mode already called from dc_set_power_state
-
-Removed userspace notification from DM code, as one already
-done in the end of base driver resume sequence
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 71 +--------------------------
- 1 file changed, 1 insertion(+), 70 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index c06f126..20654b9 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -424,86 +424,19 @@ static int dm_hw_fini(void *handle)
- 	return 0;
- }
- 
--static int dm_display_suspend(struct drm_device *ddev)
--{
--	struct drm_mode_config *config = &ddev->mode_config;
--	struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
--	struct drm_atomic_state *state;
--	struct drm_crtc *crtc;
--	unsigned crtc_mask = 0;
--	int ret = 0;
--
--	if (WARN_ON(!ctx))
--		return 0;
--
--	lockdep_assert_held(&ctx->ww_ctx);
--
--	state = drm_atomic_state_alloc(ddev);
--	if (WARN_ON(!state))
--		return -ENOMEM;
--
--	state->acquire_ctx = ctx;
--	state->allow_modeset = true;
--
--	/* Set all active crtcs to inactive, to turn off displays*/
--	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
--		struct drm_crtc_state *crtc_state =
--			drm_atomic_get_crtc_state(state, crtc);
--
--		ret = PTR_ERR_OR_ZERO(crtc_state);
--		if (ret)
--			goto free;
--
--		if (!crtc_state->active)
--			continue;
--
--		crtc_state->active = false;
--		crtc_mask |= (1 << drm_crtc_index(crtc));
--	}
--
--	if (crtc_mask) {
--		ret = drm_atomic_commit(state);
--
--		/* In case of failure, revert everything we did*/
--		if (!ret) {
--			list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head)
--				if (crtc_mask & (1 << drm_crtc_index(crtc)))
--					crtc->state->active = true;
--
--			return ret;
--		}
--	}
--
--free:
--	if (ret) {
--		DRM_ERROR("Suspending crtc's failed with %i\n", ret);
--		drm_atomic_state_free(state);
--		return ret;
--	}
--
--	return 0;
--}
- static int dm_suspend(void *handle)
- {
- 	struct amdgpu_device *adev = handle;
- 	struct amdgpu_display_manager *dm = &adev->dm;
--	struct drm_device *ddev = adev->ddev;
- 	int ret = 0;
- 
--	drm_modeset_lock_all(ddev);
--	ret = dm_display_suspend(ddev);
--	drm_modeset_unlock_all(ddev);
--
--	if (ret)
--		goto fail;
--
- 	dc_set_power_state(
- 		dm->dc,
- 		DC_ACPI_CM_POWER_STATE_D3,
- 		DC_VIDEO_POWER_SUSPEND);
- 
- 	amdgpu_dm_irq_suspend(adev);
--fail:
-+
- 	return ret;
- }
- 
-@@ -613,8 +546,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	ret = dm_display_resume(ddev);
- 	drm_modeset_unlock_all(ddev);
- 
--	drm_kms_helper_hotplug_event(ddev);
--
- 	amdgpu_dm_irq_resume(adev);
- 
- 	return ret;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0896-drm-amd-dal-zero-out-current-context-on-suspend.patch b/common/recipes-kernel/linux/files/0896-drm-amd-dal-zero-out-current-context-on-suspend.patch
deleted file mode 100644
index de625ffe..00000000
--- a/common/recipes-kernel/linux/files/0896-drm-amd-dal-zero-out-current-context-on-suspend.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From eb60252c7886935b2fc170fbdbb1ac9c9e1916fd Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 14 Mar 2016 16:46:31 -0400
-Subject: [PATCH 0896/1110] drm/amd/dal: zero out current context on suspend
-
-Since everything shuts down on S3, the states stored in current
-context are no longer valid and should be zeroed to make sure
-they don't confuse DC level optimization into incorrectly skipping
-hw programming. For the S3 issue on Tonga, the display clock was
-always hard coded, therefore not changing on resuming, so ended
-up not being programmed due to optimization. This change fixes
-S3 resume on Tonga.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c                    | 7 +++++++
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 1 -
- 2 files changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index f8459a3..5d87597 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -1081,6 +1081,13 @@ void dc_set_power_state(
- 		/* NULL means "reset/release all DC targets" */
- 		dc_commit_targets(dc, NULL, 0);
- 
-+		/* Zero out the current context so that on resume we start with
-+		 * clean state, and dc hw programming optimizations will not
-+		 * cause any trouble.
-+		 */
-+		memset(&core_dc->current_context, 0,
-+				sizeof(core_dc->current_context));
-+
- 		core_dc->hwss.power_down(core_dc);
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index fae2f8a..3d4f8b7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1637,7 +1637,6 @@ static void init_hw(struct core_dc *dc)
- 		if (dal_audio_power_up(audio) != AUDIO_RESULT_OK)
- 			dm_error("Failed audio power up!\n");
- 	}
--
- }
- 
- static const struct hw_sequencer_funcs dce110_funcs = {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0897-drm-amd-dal-zero-current-context-after-powerdown.patch b/common/recipes-kernel/linux/files/0897-drm-amd-dal-zero-current-context-after-powerdown.patch
deleted file mode 100644
index 1301a327..00000000
--- a/common/recipes-kernel/linux/files/0897-drm-amd-dal-zero-current-context-after-powerdown.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 0fd8c895534ba20c89899148583b11bb60d7c0df Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 15 Mar 2016 11:00:26 -0400
-Subject: [PATCH 0897/1110] drm/amd/dal: zero current context after powerdown
-
-Just in case we ever decide to use current_context in
-powerdown.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 5d87597..3f28446 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -1081,14 +1081,14 @@ void dc_set_power_state(
- 		/* NULL means "reset/release all DC targets" */
- 		dc_commit_targets(dc, NULL, 0);
- 
-+		core_dc->hwss.power_down(core_dc);
-+
- 		/* Zero out the current context so that on resume we start with
- 		 * clean state, and dc hw programming optimizations will not
- 		 * cause any trouble.
- 		 */
- 		memset(&core_dc->current_context, 0,
- 				sizeof(core_dc->current_context));
--
--		core_dc->hwss.power_down(core_dc);
- 		break;
- 	}
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0898-drm-amd-dal-dm-update-hw_mode-in-amdgpu_dm_atomic_co.patch b/common/recipes-kernel/linux/files/0898-drm-amd-dal-dm-update-hw_mode-in-amdgpu_dm_atomic_co.patch
deleted file mode 100644
index 08cd26a4..00000000
--- a/common/recipes-kernel/linux/files/0898-drm-amd-dal-dm-update-hw_mode-in-amdgpu_dm_atomic_co.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 89c337fb639e46df87aa337f9f87bb506b8c0fc5 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 15 Mar 2016 13:47:31 -0400
-Subject: [PATCH 0898/1110] drm/amd/dal/dm: update hw_mode in
- amdgpu_dm_atomic_commit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Needed for vblank handling.
-
-Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index dcffffe..572c5bd 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2228,6 +2228,7 @@ int amdgpu_dm_atomic_commit(
- 
- 			acrtc->target = new_target;
- 			acrtc->enabled = true;
-+			acrtc->hw_mode = crtc->state->mode;
- 
- 			break;
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0899-drm-amdgpu-Remove-is_mst_connector-flag-from-amdgpu_.patch b/common/recipes-kernel/linux/files/0899-drm-amdgpu-Remove-is_mst_connector-flag-from-amdgpu_.patch
deleted file mode 100644
index 38a8eb16..00000000
--- a/common/recipes-kernel/linux/files/0899-drm-amdgpu-Remove-is_mst_connector-flag-from-amdgpu_.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From ff59726c523947b07b8a90dc47707a8c23ac579a Mon Sep 17 00:00:00 2001
-From: David Rokhvarg <David.Rokhvarg@amd.com>
-Date: Tue, 29 Dec 2015 14:56:04 -0500
-Subject: [PATCH 0899/1110] drm/amdgpu: Remove 'is_mst_connector' flag from
- 'amdgpu_connector'.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The flag is not used.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
-Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 076d2c0..3d8c7c5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -562,7 +562,6 @@ struct amdgpu_connector {
- 	struct amdgpu_dm_dp_aux dm_dp_aux;
- 	struct drm_dp_mst_port *port;
- 	struct amdgpu_connector *mst_port;
--	bool is_mst_connector;
- 	struct amdgpu_encoder *mst_encoder;
- 	struct semaphore mst_sem;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0900-drm-amdgpu-move-all-Kconfig-options-to-amdgpu-Kconfi.patch b/common/recipes-kernel/linux/files/0900-drm-amdgpu-move-all-Kconfig-options-to-amdgpu-Kconfi.patch
deleted file mode 100644
index 3567242a..00000000
--- a/common/recipes-kernel/linux/files/0900-drm-amdgpu-move-all-Kconfig-options-to-amdgpu-Kconfi.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 88fc773d619b323d5860a8e6f4e9dce65423201b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 31 Mar 2016 18:18:28 -0400
-Subject: [PATCH 0900/1110] drm/amdgpu: move all Kconfig options to
- amdgpu/Kconfig
-
-For consistency.
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Kconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig
-index 6b9dac8..3e29c86 100644
---- a/drivers/gpu/drm/amd/amdgpu/Kconfig
-+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
-@@ -25,4 +25,6 @@ config DRM_AMDGPU_GART_DEBUGFS
- 	  Selecting this option creates a debugfs file to inspect the mapped
- 	  pages. Uses more memory for housekeeping, enable only for debugging.
- 
-+source "drivers/gpu/drm/amd/powerplay/Kconfig"
-+source "drivers/gpu/drm/amd/acp/Kconfig"
- source "drivers/gpu/drm/amd/dal/Kconfig"
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0901-drm-amd-dal-on-resume-do-not-set-mode-on-disconnecte.patch b/common/recipes-kernel/linux/files/0901-drm-amd-dal-on-resume-do-not-set-mode-on-disconnecte.patch
deleted file mode 100644
index 68796fc3..00000000
--- a/common/recipes-kernel/linux/files/0901-drm-amd-dal-on-resume-do-not-set-mode-on-disconnecte.patch
+++ /dev/null
@@ -1,194 +0,0 @@
-From 2708dd4f43bf9542e55188db188403ef1d71e1a2 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 10 Mar 2016 05:22:27 -0500
-Subject: [PATCH 0901/1110] drm/amd/dal: on resume do not set mode on
- disconnected sink
-
-In case display got disconnected during sleep (s3), it should not
-be restored during resume, as for DP it will try to link train
-which will fail and generate backtrace with warning
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 77 +++++++++++++++++++---
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h      |  5 ++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 19 ++----
- 3 files changed, 79 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 20654b9..6cea7e2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -440,6 +440,33 @@ static int dm_suspend(void *handle)
- 	return ret;
- }
- 
-+struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
-+	struct drm_atomic_state *state,
-+	struct drm_crtc *crtc,
-+	bool from_state_var)
-+{
-+	uint32_t i;
-+	struct drm_connector_state *conn_state;
-+	struct drm_connector *connector;
-+	struct drm_crtc *crtc_from_state;
-+
-+	for_each_connector_in_state(
-+		state,
-+		connector,
-+		conn_state,
-+		i) {
-+		crtc_from_state =
-+			from_state_var ?
-+				conn_state->crtc :
-+				connector->state->crtc;
-+
-+		if (crtc_from_state == crtc)
-+			return to_amdgpu_connector(connector);
-+	}
-+
-+	return NULL;
-+}
-+
- static int dm_display_resume(struct drm_device *ddev)
- {
- 	int ret = 0;
-@@ -448,13 +475,38 @@ static int dm_display_resume(struct drm_device *ddev)
- 	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
- 	struct drm_plane *plane;
- 	struct drm_crtc *crtc;
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector_state *conn_state;
- 
- 	if (!state)
- 		return ENOMEM;
- 
- 	state->acquire_ctx = ddev->mode_config.acquire_ctx;
- 
--	/* Construct an atomic state to restore previous display setting*/
-+	/* Construct an atomic state to restore previous display setting */
-+
-+	/*
-+	 * Attach connectors to drm_atomic_state
-+	 * Should be done in the first place in order to make connectors
-+	 * available in state during crtc state processing. It is used for
-+	 * making decision if crtc should be disabled in case sink got
-+	 * disconnected.
-+	 *
-+	 * Connectors state crtc with NULL dc_sink should be cleared, because it
-+	 * will fail validation during commit
-+	 */
-+	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		conn_state = drm_atomic_get_connector_state(state, connector);
-+
-+		ret = PTR_ERR_OR_ZERO(conn_state);
-+		if (ret)
-+			goto err;
-+
-+		if (!aconnector->dc_sink)
-+			conn_state->crtc = NULL;
-+	}
-+
- 	/* Attach crtcs to drm_atomic_state*/
- 	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
- 		struct drm_crtc_state *crtc_state =
-@@ -464,24 +516,31 @@ static int dm_display_resume(struct drm_device *ddev)
- 		if (ret)
- 			goto err;
- 
-+		aconnector =
-+			amdgpu_dm_find_first_crct_matching_connector(
-+				state,
-+				crtc,
-+				true);
-+
-+		/*
-+		 * this is the case when display disappear during sleep
-+		 */
-+		if (!aconnector) {
-+			crtc_state->active = false;
-+			crtc_state->enable = false;
-+		}
-+
- 		/* force a restore */
- 		crtc_state->mode_changed = true;
- 	}
- 
--	/* Attach planes to drm_atomic_state*/
-+	/* Attach planes to drm_atomic_state */
- 	list_for_each_entry(plane, &ddev->mode_config.plane_list, head) {
- 		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, plane));
- 		if (ret)
- 			goto err;
- 	}
- 
--	/* Attach connectors to drm_atomic_state*/
--	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
--		ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, connector));
--		if (ret)
--			goto err;
--	}
--
- 	/* Call commit internally with the state we just constructed */
- 	ret = drm_atomic_commit(state);
- 	if (!ret)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 94c20d5..5674a82 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -165,4 +165,9 @@ extern const struct amd_ip_funcs amdgpu_dm_funcs;
- void amdgpu_dm_update_connector_after_detect(
- 	struct amdgpu_connector *aconnector);
- 
-+struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
-+	struct drm_atomic_state *state,
-+	struct drm_crtc *crtc,
-+	bool from_state_var);
-+
- #endif /* __AMDGPU_DM_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 572c5bd..474439f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2115,7 +2115,7 @@ int amdgpu_dm_atomic_commit(
- 	struct amdgpu_display_manager *dm = &adev->dm;
- 	struct drm_plane *plane;
- 	struct drm_plane_state *old_plane_state;
--	uint32_t i, j;
-+	uint32_t i;
- 	int32_t ret;
- 	uint32_t commit_targets_count = 0;
- 	uint32_t new_crtcs_count = 0;
-@@ -2157,21 +2157,14 @@ int amdgpu_dm_atomic_commit(
- 		struct amdgpu_connector *aconnector = NULL;
- 		enum dm_commit_action action;
- 		struct drm_crtc_state *new_state = crtc->state;
--		struct drm_connector *connector;
--		struct drm_connector_state *old_con_state;
- 
- 		acrtc = to_amdgpu_crtc(crtc);
- 
--		for_each_connector_in_state(
--			state,
--			connector,
--			old_con_state,
--			j) {
--			if (connector->state->crtc == crtc) {
--				aconnector = to_amdgpu_connector(connector);
--				break;
--			}
--		}
-+		aconnector =
-+			amdgpu_dm_find_first_crct_matching_connector(
-+				state,
-+				crtc,
-+				false);
- 
- 		/* handles headless hotplug case, updating new_state and
- 		 * aconnector as needed
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0902-drm-amd-dal-Avoid-mutex-aquire-while-holding-spinloc.patch b/common/recipes-kernel/linux/files/0902-drm-amd-dal-Avoid-mutex-aquire-while-holding-spinloc.patch
deleted file mode 100644
index 1e86e463..00000000
--- a/common/recipes-kernel/linux/files/0902-drm-amd-dal-Avoid-mutex-aquire-while-holding-spinloc.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From b4ff2947a681ac22f0686a45d697f8e0c28eb5ff Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 11 Mar 2016 22:47:54 -0500
-Subject: [PATCH 0902/1110] drm/amd/dal: Avoid mutex aquire while holding
- spinlock.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 43 +++++++++++++---------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 16 +++-----
- 2 files changed, 32 insertions(+), 27 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 6cea7e2..1564485 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1073,31 +1073,40 @@ void amdgpu_dm_flip_cleanup(
- 	struct amdgpu_crtc *acrtc)
- {
- 	int r;
--	struct amdgpu_flip_work *works = acrtc->pflip_works;
-+	unsigned long flags;
-+	struct amdgpu_flip_work *works = NULL;
- 
--	acrtc->pflip_works = NULL;
--	acrtc->pflip_status = AMDGPU_FLIP_NONE;
-+	spin_lock_irqsave(&adev->ddev->event_lock, flags);
-+	if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
-+		works = acrtc->pflip_works;
-+		acrtc->pflip_works = NULL;
-+		acrtc->pflip_status = AMDGPU_FLIP_NONE;
- 
--	if (works) {
--		if(works->event)
-+		if (works && works->event) {
- 			drm_send_vblank_event(
- 				adev->ddev,
- 				acrtc->crtc_id,
- 				works->event);
-+		}
-+		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 
--		r = amdgpu_bo_reserve(works->old_rbo, false);
--		if (likely(r == 0)) {
--			r = amdgpu_bo_unpin(works->old_rbo);
--			if (unlikely(r != 0)) {
--				DRM_ERROR("failed to unpin buffer after flip\n");
--			}
--			amdgpu_bo_unreserve(works->old_rbo);
--		} else
--			DRM_ERROR("failed to reserve buffer after flip\n");
-+		if (works) {
-+			r = amdgpu_bo_reserve(works->old_rbo, false);
-+			if (likely(r == 0)) {
-+				r = amdgpu_bo_unpin(works->old_rbo);
-+				if (unlikely(r != 0)) {
-+					DRM_ERROR("failed to unpin buffer after flip\n");
-+				}
-+				amdgpu_bo_unreserve(works->old_rbo);
-+			} else
-+				DRM_ERROR("failed to reserve buffer after flip\n");
- 
--		amdgpu_bo_unref(&works->old_rbo);
--		kfree(works->shared);
--		kfree(works);
-+			amdgpu_bo_unref(&works->old_rbo);
-+			kfree(works->shared);
-+			kfree(works);
-+		}
-+	} else {
-+		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 	}
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 474439f..a085559 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2071,7 +2071,6 @@ static void manage_dm_interrupts(
- 			&adev->pageflip_irq,
- 			irq_type);
- 	} else {
--		unsigned long flags;
- 		amdgpu_irq_put(
- 			adev,
- 			&adev->pageflip_irq,
-@@ -2094,15 +2093,12 @@ static void manage_dm_interrupts(
- 		 * lock and check to amdgpu_dm_flip_cleanup function
- 		 */
- 
--		spin_lock_irqsave(&adev->ddev->event_lock, flags);
--		if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
--			/*
--			 * this is the case when on reset, last pending pflip
--			 * interrupt did not not occur. Clean-up
--			 */
--			amdgpu_dm_flip_cleanup(adev, acrtc);
--		}
--		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+
-+		/*
-+		 * this is the case when on reset, last pending pflip
-+		 * interrupt did not not occur. Clean-up
-+		 */
-+		amdgpu_dm_flip_cleanup(adev, acrtc);
- 	}
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0903-drm-amd-dal-Avoid-mutex-aquire-while-holding-spinloc.patch b/common/recipes-kernel/linux/files/0903-drm-amd-dal-Avoid-mutex-aquire-while-holding-spinloc.patch
deleted file mode 100644
index afe252ed..00000000
--- a/common/recipes-kernel/linux/files/0903-drm-amd-dal-Avoid-mutex-aquire-while-holding-spinloc.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 6eab78e6d2f918719c4269f52ee2713a53191f9b Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Mon, 14 Mar 2016 14:14:53 -0400
-Subject: [PATCH 0903/1110] drm/amd/dal: Avoid mutex aquire while holding
- spinlock 2.
-
-Just clean an obsolete comment.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 7 -------
- 1 file changed, 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a085559..6eaf54d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2088,13 +2088,6 @@ static void manage_dm_interrupts(
- 		}
- 
- 		/*
--		 * TODO: once Vitaly's change to adjust locking in
--		 * page_flip_work_func is submitted to base driver move
--		 * lock and check to amdgpu_dm_flip_cleanup function
--		 */
--
--
--		/*
- 		 * this is the case when on reset, last pending pflip
- 		 * interrupt did not not occur. Clean-up
- 		 */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0904-drm-amd-dal-bw-calculations-fixed-for-displays-4-6.patch b/common/recipes-kernel/linux/files/0904-drm-amd-dal-bw-calculations-fixed-for-displays-4-6.patch
deleted file mode 100644
index 00c36adf..00000000
--- a/common/recipes-kernel/linux/files/0904-drm-amd-dal-bw-calculations-fixed-for-displays-4-6.patch
+++ /dev/null
@@ -1,362 +0,0 @@
-From 4611e5b60b8b8beab49a192ea35d2a813088df34 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 14 Mar 2016 15:20:31 -0400
-Subject: [PATCH 0904/1110] drm/amd/dal: bw calculations fixed for displays 4-6
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 191 ++++++++++++++++++++-
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |  24 ++-
- 2 files changed, 211 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index c64efe6..f39499a 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -357,7 +357,7 @@ static void calculate_bandwidth(
- 			results->scale_ratio[i] =
- 				mode_data->d1_graphics_scale_ratio;
- 			stereo_mode[i] = mode_data->d1_graphics_stereo_mode;
--		} else {
-+		} else if (i == 6) {
- 			results->compression_rate[i] = bw_int_to_fixed(1);
- 			results->access_one_channel_only[i] = 0;
- 			results->h_total[i] = bw_int_to_fixed(
-@@ -372,6 +372,51 @@ static void calculate_bandwidth(
- 			results->scale_ratio[i] =
- 				mode_data->d2_graphics_scale_ratio;
- 			stereo_mode[i] = mode_data->d2_graphics_stereo_mode;
-+		} else if (i == 7) {
-+			results->compression_rate[i] = bw_int_to_fixed(1);
-+			results->access_one_channel_only[i] = 0;
-+			results->h_total[i] = bw_int_to_fixed(
-+				mode_data->d3_htotal);
-+			results->pixel_rate[i] = mode_data->d3_pixel_rate;
-+			results->src_width[i] = bw_int_to_fixed(
-+				mode_data->d3_graphics_src_width);
-+			results->src_height[i] = bw_int_to_fixed(
-+				mode_data->d3_graphics_src_height);
-+			results->pitch_in_pixels[i] = bw_int_to_fixed(
-+				mode_data->d3_graphics_src_width);
-+			results->scale_ratio[i] =
-+				mode_data->d3_graphics_scale_ratio;
-+			stereo_mode[i] = mode_data->d3_graphics_stereo_mode;
-+		} else if (i == 8) {
-+			results->compression_rate[i] = bw_int_to_fixed(1);
-+			results->access_one_channel_only[i] = 0;
-+			results->h_total[i] = bw_int_to_fixed(
-+				mode_data->d4_htotal);
-+			results->pixel_rate[i] = mode_data->d4_pixel_rate;
-+			results->src_width[i] = bw_int_to_fixed(
-+				mode_data->d4_graphics_src_width);
-+			results->src_height[i] = bw_int_to_fixed(
-+				mode_data->d4_graphics_src_height);
-+			results->pitch_in_pixels[i] = bw_int_to_fixed(
-+				mode_data->d4_graphics_src_width);
-+			results->scale_ratio[i] =
-+				mode_data->d4_graphics_scale_ratio;
-+			stereo_mode[i] = mode_data->d4_graphics_stereo_mode;
-+		} else {
-+			results->compression_rate[i] = bw_int_to_fixed(1);
-+			results->access_one_channel_only[i] = 0;
-+			results->h_total[i] = bw_int_to_fixed(
-+				mode_data->d5_htotal);
-+			results->pixel_rate[i] = mode_data->d5_pixel_rate;
-+			results->src_width[i] = bw_int_to_fixed(
-+				mode_data->d5_graphics_src_width);
-+			results->src_height[i] = bw_int_to_fixed(
-+				mode_data->d5_graphics_src_height);
-+			results->pitch_in_pixels[i] = bw_int_to_fixed(
-+				mode_data->d5_graphics_src_width);
-+			results->scale_ratio[i] =
-+				mode_data->d5_graphics_scale_ratio;
-+			stereo_mode[i] = mode_data->d5_graphics_stereo_mode;
- 		}
- 		results->cursor_width_pixels[i] = bw_int_to_fixed(
- 			vbios->cursor_width);
-@@ -3729,10 +3774,46 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 
- 	switch (mode_data->number_of_displays) {
- 	case (6):
-+		bw_data_internal->d5_htotal =
-+			mode_data->displays_data[5].h_total;
-+		bw_data_internal->d5_pixel_rate =
-+			mode_data->displays_data[5].pixel_rate;
-+		bw_data_internal->d5_graphics_src_width =
-+			mode_data->displays_data[5].graphics_src_width;
-+		bw_data_internal->d5_graphics_src_height =
-+			mode_data->displays_data[5].graphics_src_height;
-+		bw_data_internal->d5_graphics_scale_ratio =
-+			mode_data->displays_data[5].graphics_scale_ratio;
-+		bw_data_internal->d5_graphics_stereo_mode =
-+			mode_data->displays_data[5].graphics_stereo_mode;
- 		/* fall through */
- 	case (5):
-+		bw_data_internal->d4_htotal =
-+			mode_data->displays_data[4].h_total;
-+		bw_data_internal->d4_pixel_rate =
-+			mode_data->displays_data[4].pixel_rate;
-+		bw_data_internal->d4_graphics_src_width =
-+			mode_data->displays_data[4].graphics_src_width;
-+		bw_data_internal->d4_graphics_src_height =
-+			mode_data->displays_data[4].graphics_src_height;
-+		bw_data_internal->d4_graphics_scale_ratio =
-+			mode_data->displays_data[4].graphics_scale_ratio;
-+		bw_data_internal->d4_graphics_stereo_mode =
-+			mode_data->displays_data[4].graphics_stereo_mode;
- 		/* fall through */
- 	case (4):
-+		bw_data_internal->d3_htotal =
-+			mode_data->displays_data[3].h_total;
-+		bw_data_internal->d3_pixel_rate =
-+			mode_data->displays_data[3].pixel_rate;
-+		bw_data_internal->d3_graphics_src_width =
-+			mode_data->displays_data[3].graphics_src_width;
-+		bw_data_internal->d3_graphics_src_height =
-+			mode_data->displays_data[3].graphics_src_height;
-+		bw_data_internal->d3_graphics_scale_ratio =
-+			mode_data->displays_data[3].graphics_scale_ratio;
-+		bw_data_internal->d3_graphics_stereo_mode =
-+			mode_data->displays_data[3].graphics_stereo_mode;
- 		/* fall through */
- 	case (3):
- 		bw_data_internal->d2_htotal =
-@@ -3888,6 +3969,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->nbp_state_change_wm_ns[2].a_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[3].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[4].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[5].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->stutter_exit_wm_ns[0].a_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -3898,6 +3988,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->stutter_exit_wm_ns[2].a_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[3].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[4].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[5].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->urgent_wm_ns[0].a_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -3908,6 +4007,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->urgent_wm_ns[2].a_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[3].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[4].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[5].a_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[9], bw_int_to_fixed(1000)));
- 
- 		/*TODO check correctness*/
- 		((struct bw_calcs_vbios *)vbios)->low_sclk = mid_sclk;
-@@ -3923,6 +4031,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->nbp_state_change_wm_ns[2].b_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[3].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[4].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[5].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->stutter_exit_wm_ns[0].b_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -3933,6 +4050,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->stutter_exit_wm_ns[2].b_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[3].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[4].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[5].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->urgent_wm_ns[0].b_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -3943,6 +4069,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->urgent_wm_ns[2].b_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[3].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[4].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[5].b_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[9], bw_int_to_fixed(1000)));
- 
- 		/*TODO check correctness*/
- 		((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
-@@ -3959,6 +4094,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->nbp_state_change_wm_ns[2].c_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[3].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[4].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[5].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->stutter_exit_wm_ns[0].c_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -3969,6 +4113,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->stutter_exit_wm_ns[2].c_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[3].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[4].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[5].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->urgent_wm_ns[0].c_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -3979,6 +4132,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->urgent_wm_ns[2].c_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[3].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[4].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[5].c_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[9], bw_int_to_fixed(1000)));
- 
- 		((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
- 		((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
-@@ -3997,6 +4159,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->nbp_state_change_wm_ns[2].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[3].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[4].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[5].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->stutter_exit_wm_ns[0].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -4007,6 +4178,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->stutter_exit_wm_ns[2].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[3].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[4].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[5].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				stutter_exit_watermark[9], bw_int_to_fixed(1000)));
- 
- 		calcs_output->urgent_wm_ns[0].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
-@@ -4017,6 +4197,15 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_dceip *dceip,
- 		calcs_output->urgent_wm_ns[2].d_mark =
- 			bw_fixed_to_int(bw_mul(bw_results_internal->
- 				urgent_watermark[6], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[3].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[7], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[4].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[8], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[5].d_mark =
-+			bw_fixed_to_int(bw_mul(bw_results_internal->
-+				urgent_watermark[9], bw_int_to_fixed(1000)));
- 
- 		((struct bw_calcs_vbios *)vbios)->low_yclk = low_yclk;
- 		((struct bw_calcs_vbios *)vbios)->mid_yclk = mid_yclk;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index 023efd3..d6a599c 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -228,6 +228,24 @@ struct bw_calcs_mode_data_internal {
- 	uint32_t d2_graphics_src_height;
- 	struct bw_fixed d2_graphics_scale_ratio;
- 	enum bw_defines d2_graphics_stereo_mode;
-+	uint32_t d3_htotal;
-+	struct bw_fixed d3_pixel_rate;
-+	uint32_t d3_graphics_src_width;
-+	uint32_t d3_graphics_src_height;
-+	struct bw_fixed d3_graphics_scale_ratio;
-+	enum bw_defines d3_graphics_stereo_mode;
-+	uint32_t d4_htotal;
-+	struct bw_fixed d4_pixel_rate;
-+	uint32_t d4_graphics_src_width;
-+	uint32_t d4_graphics_src_height;
-+	struct bw_fixed d4_graphics_scale_ratio;
-+	enum bw_defines d4_graphics_stereo_mode;
-+	uint32_t d5_htotal;
-+	struct bw_fixed d5_pixel_rate;
-+	uint32_t d5_graphics_src_width;
-+	uint32_t d5_graphics_src_height;
-+	struct bw_fixed d5_graphics_scale_ratio;
-+	enum bw_defines d5_graphics_stereo_mode;
- };
- 
- struct bw_calcs_input_single_display {
-@@ -475,9 +493,9 @@ struct bw_calcs_output {
- 	bool stutter_mode_enable;
- 	bool nbp_state_change_enable;
- 	bool all_displays_in_sync;
--	struct bw_watermarks urgent_wm_ns[4];
--	struct bw_watermarks stutter_exit_wm_ns[4];
--	struct bw_watermarks nbp_state_change_wm_ns[4];
-+	struct bw_watermarks urgent_wm_ns[6];
-+	struct bw_watermarks stutter_exit_wm_ns[6];
-+	struct bw_watermarks nbp_state_change_wm_ns[6];
- 	uint32_t required_sclk;
- 	uint32_t required_sclk_deep_sleep;
- 	uint32_t required_yclk;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0905-drm-amd-dal-fix-warnings-with-msc-in-Xorg.patch b/common/recipes-kernel/linux/files/0905-drm-amd-dal-fix-warnings-with-msc-in-Xorg.patch
deleted file mode 100644
index 26892338..00000000
--- a/common/recipes-kernel/linux/files/0905-drm-amd-dal-fix-warnings-with-msc-in-Xorg.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 5f602a6381c0a03a4f57cb9cfa3282cf163433e1 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 15 Mar 2016 05:52:55 -0400
-Subject: [PATCH 0905/1110] drm/amd/dal: fix warnings with msc in Xorg
-
-Mode 3 should be used in MASTER_UPDATE_MODE in
-order to make V_UPDATE occur at the beginning of
-the first line of vertical front porch. And so
-flips are syncronized specific way required by
-userspace
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c   | 15 +++++++++++----
- 1 file changed, 11 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index 61dc9c0..de370ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -268,12 +268,19 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- {
- 	enum bp_result result;
- 
--	/* 0 value is needed by DRR and is also suggested default value for CZ
--	 */
--	uint32_t value;
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = 0;
-+
-+	/*
-+	 * 3 is used to make sure V_UPDATE occurs at the beginning of the first
-+	 * line of vertical front porch
-+	 */
-+	set_reg_field_value(
-+		value,
-+		3,
-+		CRTC_MASTER_UPDATE_MODE,
-+		MASTER_UPDATE_MODE);
- 
--	value = 0;
- 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
- 
- 	/* TODO: may want this on to catch underflow */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0906-drm-amd-dal-micro-refactoring-in-DM-and-DC.patch b/common/recipes-kernel/linux/files/0906-drm-amd-dal-micro-refactoring-in-DM-and-DC.patch
deleted file mode 100644
index 5c915cd0..00000000
--- a/common/recipes-kernel/linux/files/0906-drm-amd-dal-micro-refactoring-in-DM-and-DC.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 94dacf0885af116dc218c22d21408a210045dd50 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Thu, 10 Mar 2016 05:38:28 -0500
-Subject: [PATCH 0906/1110] drm/amd/dal: micro refactoring in DM and DC
-
-Removed warning generated for edids with more than 1 extension,
-e.g. for tiled display case.
-
-Fixed few identation issues.
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c  | 4 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c        | 2 --
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c         | 6 +++---
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 4 ++--
- 4 files changed, 7 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 6eaf54d..8e7c491 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2634,8 +2634,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 
- 	}
- 
--	if (need_to_validate == false || set_count == 0
--				|| dc_validate_resources(dc, set, set_count))
-+	if (need_to_validate == false || set_count == 0 ||
-+		dc_validate_resources(dc, set, set_count))
- 		ret = 0;
- 
- connector_not_found:
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index 2922453..698a34e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -630,8 +630,6 @@ static uint32_t query_edid_block(
- 		return 0;
- 
- 	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
--
--		ASSERT(index < 2);
- 		size_retrieved =
- 			aux_read_edid_block(ddc, address, index, buf);
- 	} else {
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index aab73ff..282a56b 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -902,10 +902,10 @@ static bool perform_clock_recovery_sequence(
- 		else
- 			retries_cr = 0;
- 
--			/* 8. update VS/PE/PC2 in lt_settings*/
--			update_drive_settings(lt_settings, req_settings);
-+		/* 8. update VS/PE/PC2 in lt_settings*/
-+		update_drive_settings(lt_settings, req_settings);
- 
--			retry_count++;
-+		retry_count++;
- 	}
- 
- 	if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-index 6f3ca2d..6629f2f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
-@@ -353,8 +353,8 @@ void dce110_mem_input_wait_for_no_surface_update_pending(struct mem_input *mem_i
- 	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
- 	uint32_t value;
- 
--	do  {
--		value = dm_read_reg(mem_input110->base.ctx,	DCP_REG(mmGRPH_UPDATE));
-+	do {
-+		value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_UPDATE));
- 	} while (get_reg_field_value(value, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING));
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0907-drm-amd-dal-fix-division-by-0-on-boot-for-dce80.patch b/common/recipes-kernel/linux/files/0907-drm-amd-dal-fix-division-by-0-on-boot-for-dce80.patch
deleted file mode 100644
index f7292f1b..00000000
--- a/common/recipes-kernel/linux/files/0907-drm-amd-dal-fix-division-by-0-on-boot-for-dce80.patch
+++ /dev/null
@@ -1,228 +0,0 @@
-From d2f023c883e3a8b999ee9b4b43ee784152159e5c Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 16 Mar 2016 16:38:28 -0400
-Subject: [PATCH 0907/1110] drm/amd/dal: fix division by 0 on boot for dce80
-
-DCE80 used to have bandwidth parameters initialized with the dce110
-numbers. This was taken out a while ago, leaving the parameters to
-be uninitialized. This causes division by 0 on boot. This change
-resolves this by skipping bandwidth calculation and displaymark
-programming. For now, we will have dce80 always running safemark
-
-Reviewed-by: Eagle Yeh <eagle.yeh@amd.com>
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |   7 +
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 169 +--------------------
- 2 files changed, 10 insertions(+), 166 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-index caec585..02d7508 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -291,6 +291,12 @@ static bool dce80_enable_display_power_gating(
- 		return false;
- }
- 
-+static void set_displaymarks(
-+		const struct core_dc *dc, struct validate_context *context)
-+{
-+	/* Do nothing until we have proper bandwitdth calcs */
-+}
-+
- bool dce80_hw_sequencer_construct(struct core_dc *dc)
- {
- 	dce110_hw_sequencer_construct(dc);
-@@ -300,6 +306,7 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
- 	dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
- 	dc->hwss.pipe_control_lock = dce80_pipe_control_lock;
- 	dc->hwss.set_blender_mode = dce80_set_blender_mode;
-+	dc->hwss.set_displaymarks = set_displaymarks;
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 594f9ab..311f5fa 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -718,173 +718,10 @@ enum dc_status dce80_validate_bandwidth(
- 	const struct core_dc *dc,
- 	struct validate_context *context)
- {
--	uint8_t i;
--	enum dc_status result = DC_ERROR_UNEXPECTED;
--	uint8_t number_of_displays = 0;
--	uint8_t max_htaps = 1;
--	uint8_t max_vtaps = 1;
--	bool all_displays_in_sync = true;
--	struct dc_crtc_timing prev_timing;
--
--	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
--
--	for (i = 0; i < MAX_PIPES; i++) {
--		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
--		struct bw_calcs_input_single_display *disp = &context->
--			bw_mode_data.displays_data[number_of_displays];
--
--		if (pipe_ctx->stream == NULL)
--			continue;
--
--		if (pipe_ctx->scl_data.ratios.vert.value == 0) {
--			disp->graphics_scale_ratio = bw_int_to_fixed(1);
--			disp->graphics_h_taps = 2;
--			disp->graphics_v_taps = 2;
--
--			/* TODO: remove when bw formula accepts taps per
--			 * display
--			 */
--			if (max_vtaps < 2)
--				max_vtaps = 2;
--			if (max_htaps < 2)
--				max_htaps = 2;
--
--		} else {
--			disp->graphics_scale_ratio =
--				fixed31_32_to_bw_fixed(
--					pipe_ctx->scl_data.ratios.vert.value);
--			disp->graphics_h_taps = pipe_ctx->scl_data.taps.h_taps;
--			disp->graphics_v_taps = pipe_ctx->scl_data.taps.v_taps;
--
--			/* TODO: remove when bw formula accepts taps per
--			 * display
--			 */
--			if (max_vtaps < pipe_ctx->scl_data.taps.v_taps)
--				max_vtaps = pipe_ctx->scl_data.taps.v_taps;
--			if (max_htaps < pipe_ctx->scl_data.taps.h_taps)
--				max_htaps = pipe_ctx->scl_data.taps.h_taps;
--		}
--
--		disp->graphics_src_width =
--			pipe_ctx->stream->public.timing.h_addressable;
--		disp->graphics_src_height =
--			pipe_ctx->stream->public.timing.v_addressable;
--		disp->h_total = pipe_ctx->stream->public.timing.h_total;
--		disp->pixel_rate = bw_frc_to_fixed(
--			pipe_ctx->stream->public.timing.pix_clk_khz, 1000);
--
--		/*TODO: get from surface*/
--		disp->graphics_bytes_per_pixel = 4;
--		disp->graphics_tiling_mode = bw_def_tiled;
--
--		/* DCE11 defaults*/
--		disp->graphics_lb_bpc = 10;
--		disp->graphics_interlace_mode = false;
--		disp->fbc_enable = false;
--		disp->lpt_enable = false;
--		disp->graphics_stereo_mode = bw_def_mono;
--		disp->underlay_mode = bw_def_none;
--
--		/*All displays will be synchronized if timings are all
--		 * the same
--		 */
--		if (number_of_displays != 0 && all_displays_in_sync)
--			if (memcmp(&prev_timing,
--				&pipe_ctx->stream->public.timing,
--				sizeof(struct dc_crtc_timing)) != 0)
--				all_displays_in_sync = false;
--		if (number_of_displays == 0)
--			prev_timing = pipe_ctx->stream->public.timing;
--
--		number_of_displays++;
--	}
-+	/* TODO implement when needed but for now hardcode max value*/
-+	context->bw_results.dispclk_khz = 681000;
- 
--	/* TODO: remove when bw formula accepts taps per
--	 * display
--	 */
--	context->bw_mode_data.displays_data[0].graphics_v_taps = max_vtaps;
--	context->bw_mode_data.displays_data[0].graphics_h_taps = max_htaps;
--
--	context->bw_mode_data.number_of_displays = number_of_displays;
--	context->bw_mode_data.display_synchronization_enabled =
--							all_displays_in_sync;
--
--	dal_logger_write(
--		dc->ctx->logger,
--		LOG_MAJOR_BWM,
--		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
--		"%s: start",
--		__func__);
--
--	if (!bw_calcs(
--			dc->ctx,
--			&dc->bw_dceip,
--			&dc->bw_vbios,
--			&context->bw_mode_data,
--			&context->bw_results))
--		result =  DC_FAIL_BANDWIDTH_VALIDATE;
--	else
--		result =  DC_OK;
--
--	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
--		dal_logger_write(dc->ctx->logger,
--			LOG_MAJOR_BWM,
--			LOG_MINOR_BWM_MODE_VALIDATION,
--			"%s: Bandwidth validation failed!",
--			__func__);
--
--	if (memcmp(&dc->current_context.bw_results,
--			&context->bw_results, sizeof(context->bw_results))) {
--		struct log_entry log_entry;
--		dal_logger_open(
--			dc->ctx->logger,
--			&log_entry,
--			LOG_MAJOR_BWM,
--			LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
--		dal_logger_append(&log_entry, "%s: finish, numDisplays: %d\n"
--			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
--			"stutMark_b: %d stutMark_a: %d\n",
--			__func__, number_of_displays,
--			context->bw_results.nbp_state_change_wm_ns[0].b_mark,
--			context->bw_results.nbp_state_change_wm_ns[0].a_mark,
--			context->bw_results.urgent_wm_ns[0].b_mark,
--			context->bw_results.urgent_wm_ns[0].a_mark,
--			context->bw_results.stutter_exit_wm_ns[0].b_mark,
--			context->bw_results.stutter_exit_wm_ns[0].a_mark);
--		dal_logger_append(&log_entry,
--			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
--			"stutMark_b: %d stutMark_a: %d\n",
--			context->bw_results.nbp_state_change_wm_ns[1].b_mark,
--			context->bw_results.nbp_state_change_wm_ns[1].a_mark,
--			context->bw_results.urgent_wm_ns[1].b_mark,
--			context->bw_results.urgent_wm_ns[1].a_mark,
--			context->bw_results.stutter_exit_wm_ns[1].b_mark,
--			context->bw_results.stutter_exit_wm_ns[1].a_mark);
--		dal_logger_append(&log_entry,
--			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
--			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
--			context->bw_results.nbp_state_change_wm_ns[2].b_mark,
--			context->bw_results.nbp_state_change_wm_ns[2].a_mark,
--			context->bw_results.urgent_wm_ns[2].b_mark,
--			context->bw_results.urgent_wm_ns[2].a_mark,
--			context->bw_results.stutter_exit_wm_ns[2].b_mark,
--			context->bw_results.stutter_exit_wm_ns[2].a_mark,
--			context->bw_results.stutter_mode_enable);
--		dal_logger_append(&log_entry,
--			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
--			"sclk: %d sclk_sleep: %d yclk: %d blackout_duration: %d\n",
--			context->bw_results.cpuc_state_change_enable,
--			context->bw_results.cpup_state_change_enable,
--			context->bw_results.nbp_state_change_enable,
--			context->bw_results.all_displays_in_sync,
--			context->bw_results.dispclk_khz,
--			context->bw_results.required_sclk,
--			context->bw_results.required_sclk_deep_sleep,
--			context->bw_results.required_yclk,
--			context->bw_results.required_blackout_duration_us);
--		dal_logger_close(&log_entry);
--	}
--	return result;
-+	return DC_OK;
- }
- 
- static void set_target_unchanged(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0908-drm-amd-add-DCE-11.2-register-headers.patch b/common/recipes-kernel/linux/files/0908-drm-amd-add-DCE-11.2-register-headers.patch
deleted file mode 100644
index 881e1396..00000000
--- a/common/recipes-kernel/linux/files/0908-drm-amd-add-DCE-11.2-register-headers.patch
+++ /dev/null
@@ -1,35619 +0,0 @@
-From 7d8dca4f2ce1ecfa3c83945c5a9c8667e50cd888 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 11 Mar 2016 14:46:46 -0500
-Subject: [PATCH 0908/1110] drm/amd: add DCE 11.2 register headers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add register headers for DCE (Display and Composition Engine)
-11.2.
-
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h  | 10075 ++++++++++
- .../drm/amd/include/asic_reg/dce/dce_11_2_enum.h   |  6813 +++++++
- .../amd/include/asic_reg/dce/dce_11_2_sh_mask.h    | 18687 +++++++++++++++++++
- 3 files changed, 35575 insertions(+)
- create mode 100755 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h
- create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
- create mode 100755 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h
-new file mode 100755
-index 0000000..09a7df1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h
-@@ -0,0 +1,10075 @@
-+/*
-+ * DCE_11_2 Register documentation
-+ *
-+ * Copyright (C) 2016  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef DCE_11_2_D_H
-+#define DCE_11_2_D_H
-+
-+#define mmPIPE0_PG_CONFIG                                                       0x2c0
-+#define mmPIPE0_PG_ENABLE                                                       0x2c1
-+#define mmPIPE0_PG_STATUS                                                       0x2c2
-+#define mmPIPE1_PG_CONFIG                                                       0x2c3
-+#define mmPIPE1_PG_ENABLE                                                       0x2c4
-+#define mmPIPE1_PG_STATUS                                                       0x2c5
-+#define mmPIPE2_PG_CONFIG                                                       0x2c6
-+#define mmPIPE2_PG_ENABLE                                                       0x2c7
-+#define mmPIPE2_PG_STATUS                                                       0x2c8
-+#define mmPIPE3_PG_CONFIG                                                       0x2c9
-+#define mmPIPE3_PG_ENABLE                                                       0x2ca
-+#define mmPIPE3_PG_STATUS                                                       0x2cb
-+#define mmPIPE4_PG_CONFIG                                                       0x2cc
-+#define mmPIPE4_PG_ENABLE                                                       0x2cd
-+#define mmPIPE4_PG_STATUS                                                       0x2ce
-+#define mmPIPE5_PG_CONFIG                                                       0x2cf
-+#define mmPIPE5_PG_ENABLE                                                       0x2d0
-+#define mmPIPE5_PG_STATUS                                                       0x2d1
-+#define mmDCPG_INTERRUPT_STATUS                                                 0x2de
-+#define mmDCPG_INTERRUPT_CONTROL                                                0x2df
-+#define mmDCPG_INTERRUPT_CONTROL2                                               0x2e0
-+#define mmDC_IP_REQUEST_CNTL                                                    0x2d2
-+#define mmDC_PGFSM_CONFIG_REG                                                   0x2d3
-+#define mmDC_PGFSM_WRITE_REG                                                    0x2d4
-+#define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
-+#define mmDCPG_TEST_DEBUG_INDEX                                                 0x2d6
-+#define mmDCPG_TEST_DEBUG_DATA                                                  0x2d7
-+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                           0x1628
-+#define mmBL1_PWM_USER_LEVEL                                                    0x1629
-+#define mmBL1_PWM_TARGET_ABM_LEVEL                                              0x162a
-+#define mmBL1_PWM_CURRENT_ABM_LEVEL                                             0x162b
-+#define mmBL1_PWM_FINAL_DUTY_CYCLE                                              0x162c
-+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                            0x162d
-+#define mmBL1_PWM_ABM_CNTL                                                      0x162e
-+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
-+#define mmBL1_PWM_GRP2_REG_LOCK                                                 0x1630
-+#define mmDC_ABM1_CNTL                                                          0x1638
-+#define mmDC_ABM1_IPCSC_COEFF_SEL                                               0x1639
-+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                            0x163a
-+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                            0x163b
-+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                            0x163c
-+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                            0x163d
-+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                            0x163e
-+#define mmDC_ABM1_ACE_THRES_12                                                  0x163f
-+#define mmDC_ABM1_ACE_THRES_34                                                  0x1640
-+#define mmDC_ABM1_ACE_CNTL_MISC                                                 0x1641
-+#define mmDC_ABM1_DEBUG_MISC                                                    0x1649
-+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                        0x164a
-+#define mmDC_ABM1_HG_MISC_CTRL                                                  0x164b
-+#define mmDC_ABM1_LS_SUM_OF_LUMA                                                0x164c
-+#define mmDC_ABM1_LS_MIN_MAX_LUMA                                               0x164d
-+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                      0x164e
-+#define mmDC_ABM1_LS_PIXEL_COUNT                                                0x164f
-+#define mmDC_ABM1_LS_OVR_SCAN_BIN                                               0x1650
-+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                  0x1651
-+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                      0x1652
-+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                      0x1653
-+#define mmDC_ABM1_HG_SAMPLE_RATE                                                0x1654
-+#define mmDC_ABM1_LS_SAMPLE_RATE                                                0x1655
-+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                        0x1656
-+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                        0x1657
-+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                       0x1658
-+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                      0x1659
-+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                      0x165a
-+#define mmDC_ABM1_HG_RESULT_1                                                   0x165b
-+#define mmDC_ABM1_HG_RESULT_2                                                   0x165c
-+#define mmDC_ABM1_HG_RESULT_3                                                   0x165d
-+#define mmDC_ABM1_HG_RESULT_4                                                   0x165e
-+#define mmDC_ABM1_HG_RESULT_5                                                   0x165f
-+#define mmDC_ABM1_HG_RESULT_6                                                   0x1660
-+#define mmDC_ABM1_HG_RESULT_7                                                   0x1661
-+#define mmDC_ABM1_HG_RESULT_8                                                   0x1662
-+#define mmDC_ABM1_HG_RESULT_9                                                   0x1663
-+#define mmDC_ABM1_HG_RESULT_10                                                  0x1664
-+#define mmDC_ABM1_HG_RESULT_11                                                  0x1665
-+#define mmDC_ABM1_HG_RESULT_12                                                  0x1666
-+#define mmDC_ABM1_HG_RESULT_13                                                  0x1667
-+#define mmDC_ABM1_HG_RESULT_14                                                  0x1668
-+#define mmDC_ABM1_HG_RESULT_15                                                  0x1669
-+#define mmDC_ABM1_HG_RESULT_16                                                  0x166a
-+#define mmDC_ABM1_HG_RESULT_17                                                  0x166b
-+#define mmDC_ABM1_HG_RESULT_18                                                  0x166c
-+#define mmDC_ABM1_HG_RESULT_19                                                  0x166d
-+#define mmDC_ABM1_HG_RESULT_20                                                  0x166e
-+#define mmDC_ABM1_HG_RESULT_21                                                  0x166f
-+#define mmDC_ABM1_HG_RESULT_22                                                  0x1670
-+#define mmDC_ABM1_HG_RESULT_23                                                  0x1671
-+#define mmDC_ABM1_HG_RESULT_24                                                  0x1672
-+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                          0x169b
-+#define mmDC_ABM1_BL_MASTER_LOCK                                                0x169c
-+#define mmABM_TEST_DEBUG_INDEX                                                  0x169e
-+#define mmABM_TEST_DEBUG_DATA                                                   0x169f
-+#define mmCRTC_H_BLANK_EARLY_NUM                                                0x1b7d
-+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                          0x1b7d
-+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                          0x1d7d
-+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                          0x1f7d
-+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                          0x417d
-+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                          0x437d
-+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                          0x457d
-+#define mmCRTC_H_TOTAL                                                          0x1b80
-+#define mmCRTC0_CRTC_H_TOTAL                                                    0x1b80
-+#define mmCRTC1_CRTC_H_TOTAL                                                    0x1d80
-+#define mmCRTC2_CRTC_H_TOTAL                                                    0x1f80
-+#define mmCRTC3_CRTC_H_TOTAL                                                    0x4180
-+#define mmCRTC4_CRTC_H_TOTAL                                                    0x4380
-+#define mmCRTC5_CRTC_H_TOTAL                                                    0x4580
-+#define mmCRTC_H_BLANK_START_END                                                0x1b81
-+#define mmCRTC0_CRTC_H_BLANK_START_END                                          0x1b81
-+#define mmCRTC1_CRTC_H_BLANK_START_END                                          0x1d81
-+#define mmCRTC2_CRTC_H_BLANK_START_END                                          0x1f81
-+#define mmCRTC3_CRTC_H_BLANK_START_END                                          0x4181
-+#define mmCRTC4_CRTC_H_BLANK_START_END                                          0x4381
-+#define mmCRTC5_CRTC_H_BLANK_START_END                                          0x4581
-+#define mmCRTC_H_SYNC_A                                                         0x1b82
-+#define mmCRTC0_CRTC_H_SYNC_A                                                   0x1b82
-+#define mmCRTC1_CRTC_H_SYNC_A                                                   0x1d82
-+#define mmCRTC2_CRTC_H_SYNC_A                                                   0x1f82
-+#define mmCRTC3_CRTC_H_SYNC_A                                                   0x4182
-+#define mmCRTC4_CRTC_H_SYNC_A                                                   0x4382
-+#define mmCRTC5_CRTC_H_SYNC_A                                                   0x4582
-+#define mmCRTC_H_SYNC_A_CNTL                                                    0x1b83
-+#define mmCRTC0_CRTC_H_SYNC_A_CNTL                                              0x1b83
-+#define mmCRTC1_CRTC_H_SYNC_A_CNTL                                              0x1d83
-+#define mmCRTC2_CRTC_H_SYNC_A_CNTL                                              0x1f83
-+#define mmCRTC3_CRTC_H_SYNC_A_CNTL                                              0x4183
-+#define mmCRTC4_CRTC_H_SYNC_A_CNTL                                              0x4383
-+#define mmCRTC5_CRTC_H_SYNC_A_CNTL                                              0x4583
-+#define mmCRTC_H_SYNC_B                                                         0x1b84
-+#define mmCRTC0_CRTC_H_SYNC_B                                                   0x1b84
-+#define mmCRTC1_CRTC_H_SYNC_B                                                   0x1d84
-+#define mmCRTC2_CRTC_H_SYNC_B                                                   0x1f84
-+#define mmCRTC3_CRTC_H_SYNC_B                                                   0x4184
-+#define mmCRTC4_CRTC_H_SYNC_B                                                   0x4384
-+#define mmCRTC5_CRTC_H_SYNC_B                                                   0x4584
-+#define mmCRTC_H_SYNC_B_CNTL                                                    0x1b85
-+#define mmCRTC0_CRTC_H_SYNC_B_CNTL                                              0x1b85
-+#define mmCRTC1_CRTC_H_SYNC_B_CNTL                                              0x1d85
-+#define mmCRTC2_CRTC_H_SYNC_B_CNTL                                              0x1f85
-+#define mmCRTC3_CRTC_H_SYNC_B_CNTL                                              0x4185
-+#define mmCRTC4_CRTC_H_SYNC_B_CNTL                                              0x4385
-+#define mmCRTC5_CRTC_H_SYNC_B_CNTL                                              0x4585
-+#define mmCRTC_VBI_END                                                          0x1b86
-+#define mmCRTC0_CRTC_VBI_END                                                    0x1b86
-+#define mmCRTC1_CRTC_VBI_END                                                    0x1d86
-+#define mmCRTC2_CRTC_VBI_END                                                    0x1f86
-+#define mmCRTC3_CRTC_VBI_END                                                    0x4186
-+#define mmCRTC4_CRTC_VBI_END                                                    0x4386
-+#define mmCRTC5_CRTC_VBI_END                                                    0x4586
-+#define mmCRTC_V_TOTAL                                                          0x1b87
-+#define mmCRTC0_CRTC_V_TOTAL                                                    0x1b87
-+#define mmCRTC1_CRTC_V_TOTAL                                                    0x1d87
-+#define mmCRTC2_CRTC_V_TOTAL                                                    0x1f87
-+#define mmCRTC3_CRTC_V_TOTAL                                                    0x4187
-+#define mmCRTC4_CRTC_V_TOTAL                                                    0x4387
-+#define mmCRTC5_CRTC_V_TOTAL                                                    0x4587
-+#define mmCRTC_V_TOTAL_MIN                                                      0x1b88
-+#define mmCRTC0_CRTC_V_TOTAL_MIN                                                0x1b88
-+#define mmCRTC1_CRTC_V_TOTAL_MIN                                                0x1d88
-+#define mmCRTC2_CRTC_V_TOTAL_MIN                                                0x1f88
-+#define mmCRTC3_CRTC_V_TOTAL_MIN                                                0x4188
-+#define mmCRTC4_CRTC_V_TOTAL_MIN                                                0x4388
-+#define mmCRTC5_CRTC_V_TOTAL_MIN                                                0x4588
-+#define mmCRTC_V_TOTAL_MAX                                                      0x1b89
-+#define mmCRTC0_CRTC_V_TOTAL_MAX                                                0x1b89
-+#define mmCRTC1_CRTC_V_TOTAL_MAX                                                0x1d89
-+#define mmCRTC2_CRTC_V_TOTAL_MAX                                                0x1f89
-+#define mmCRTC3_CRTC_V_TOTAL_MAX                                                0x4189
-+#define mmCRTC4_CRTC_V_TOTAL_MAX                                                0x4389
-+#define mmCRTC5_CRTC_V_TOTAL_MAX                                                0x4589
-+#define mmCRTC_V_TOTAL_CONTROL                                                  0x1b8a
-+#define mmCRTC0_CRTC_V_TOTAL_CONTROL                                            0x1b8a
-+#define mmCRTC1_CRTC_V_TOTAL_CONTROL                                            0x1d8a
-+#define mmCRTC2_CRTC_V_TOTAL_CONTROL                                            0x1f8a
-+#define mmCRTC3_CRTC_V_TOTAL_CONTROL                                            0x418a
-+#define mmCRTC4_CRTC_V_TOTAL_CONTROL                                            0x438a
-+#define mmCRTC5_CRTC_V_TOTAL_CONTROL                                            0x458a
-+#define mmCRTC_V_TOTAL_INT_STATUS                                               0x1b8b
-+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                         0x1b8b
-+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                         0x1d8b
-+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                         0x1f8b
-+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                         0x418b
-+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                         0x438b
-+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                         0x458b
-+#define mmCRTC_VSYNC_NOM_INT_STATUS                                             0x1b8c
-+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                       0x1b8c
-+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                       0x1d8c
-+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                       0x1f8c
-+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                       0x418c
-+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                       0x438c
-+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                       0x458c
-+#define mmCRTC_V_BLANK_START_END                                                0x1b8d
-+#define mmCRTC0_CRTC_V_BLANK_START_END                                          0x1b8d
-+#define mmCRTC1_CRTC_V_BLANK_START_END                                          0x1d8d
-+#define mmCRTC2_CRTC_V_BLANK_START_END                                          0x1f8d
-+#define mmCRTC3_CRTC_V_BLANK_START_END                                          0x418d
-+#define mmCRTC4_CRTC_V_BLANK_START_END                                          0x438d
-+#define mmCRTC5_CRTC_V_BLANK_START_END                                          0x458d
-+#define mmCRTC_V_SYNC_A                                                         0x1b8e
-+#define mmCRTC0_CRTC_V_SYNC_A                                                   0x1b8e
-+#define mmCRTC1_CRTC_V_SYNC_A                                                   0x1d8e
-+#define mmCRTC2_CRTC_V_SYNC_A                                                   0x1f8e
-+#define mmCRTC3_CRTC_V_SYNC_A                                                   0x418e
-+#define mmCRTC4_CRTC_V_SYNC_A                                                   0x438e
-+#define mmCRTC5_CRTC_V_SYNC_A                                                   0x458e
-+#define mmCRTC_V_SYNC_A_CNTL                                                    0x1b8f
-+#define mmCRTC0_CRTC_V_SYNC_A_CNTL                                              0x1b8f
-+#define mmCRTC1_CRTC_V_SYNC_A_CNTL                                              0x1d8f
-+#define mmCRTC2_CRTC_V_SYNC_A_CNTL                                              0x1f8f
-+#define mmCRTC3_CRTC_V_SYNC_A_CNTL                                              0x418f
-+#define mmCRTC4_CRTC_V_SYNC_A_CNTL                                              0x438f
-+#define mmCRTC5_CRTC_V_SYNC_A_CNTL                                              0x458f
-+#define mmCRTC_V_SYNC_B                                                         0x1b90
-+#define mmCRTC0_CRTC_V_SYNC_B                                                   0x1b90
-+#define mmCRTC1_CRTC_V_SYNC_B                                                   0x1d90
-+#define mmCRTC2_CRTC_V_SYNC_B                                                   0x1f90
-+#define mmCRTC3_CRTC_V_SYNC_B                                                   0x4190
-+#define mmCRTC4_CRTC_V_SYNC_B                                                   0x4390
-+#define mmCRTC5_CRTC_V_SYNC_B                                                   0x4590
-+#define mmCRTC_V_SYNC_B_CNTL                                                    0x1b91
-+#define mmCRTC0_CRTC_V_SYNC_B_CNTL                                              0x1b91
-+#define mmCRTC1_CRTC_V_SYNC_B_CNTL                                              0x1d91
-+#define mmCRTC2_CRTC_V_SYNC_B_CNTL                                              0x1f91
-+#define mmCRTC3_CRTC_V_SYNC_B_CNTL                                              0x4191
-+#define mmCRTC4_CRTC_V_SYNC_B_CNTL                                              0x4391
-+#define mmCRTC5_CRTC_V_SYNC_B_CNTL                                              0x4591
-+#define mmCRTC_DTMTEST_CNTL                                                     0x1b92
-+#define mmCRTC0_CRTC_DTMTEST_CNTL                                               0x1b92
-+#define mmCRTC1_CRTC_DTMTEST_CNTL                                               0x1d92
-+#define mmCRTC2_CRTC_DTMTEST_CNTL                                               0x1f92
-+#define mmCRTC3_CRTC_DTMTEST_CNTL                                               0x4192
-+#define mmCRTC4_CRTC_DTMTEST_CNTL                                               0x4392
-+#define mmCRTC5_CRTC_DTMTEST_CNTL                                               0x4592
-+#define mmCRTC_DTMTEST_STATUS_POSITION                                          0x1b93
-+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                    0x1b93
-+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                    0x1d93
-+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                    0x1f93
-+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                    0x4193
-+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                    0x4393
-+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                    0x4593
-+#define mmCRTC_TRIGA_CNTL                                                       0x1b94
-+#define mmCRTC0_CRTC_TRIGA_CNTL                                                 0x1b94
-+#define mmCRTC1_CRTC_TRIGA_CNTL                                                 0x1d94
-+#define mmCRTC2_CRTC_TRIGA_CNTL                                                 0x1f94
-+#define mmCRTC3_CRTC_TRIGA_CNTL                                                 0x4194
-+#define mmCRTC4_CRTC_TRIGA_CNTL                                                 0x4394
-+#define mmCRTC5_CRTC_TRIGA_CNTL                                                 0x4594
-+#define mmCRTC_TRIGA_MANUAL_TRIG                                                0x1b95
-+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                          0x1b95
-+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                          0x1d95
-+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                          0x1f95
-+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                          0x4195
-+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                          0x4395
-+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                          0x4595
-+#define mmCRTC_TRIGB_CNTL                                                       0x1b96
-+#define mmCRTC0_CRTC_TRIGB_CNTL                                                 0x1b96
-+#define mmCRTC1_CRTC_TRIGB_CNTL                                                 0x1d96
-+#define mmCRTC2_CRTC_TRIGB_CNTL                                                 0x1f96
-+#define mmCRTC3_CRTC_TRIGB_CNTL                                                 0x4196
-+#define mmCRTC4_CRTC_TRIGB_CNTL                                                 0x4396
-+#define mmCRTC5_CRTC_TRIGB_CNTL                                                 0x4596
-+#define mmCRTC_TRIGB_MANUAL_TRIG                                                0x1b97
-+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                          0x1b97
-+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                          0x1d97
-+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                          0x1f97
-+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                          0x4197
-+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                          0x4397
-+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                          0x4597
-+#define mmCRTC_FORCE_COUNT_NOW_CNTL                                             0x1b98
-+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1b98
-+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1d98
-+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1f98
-+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4198
-+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4398
-+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4598
-+#define mmCRTC_FLOW_CONTROL                                                     0x1b99
-+#define mmCRTC0_CRTC_FLOW_CONTROL                                               0x1b99
-+#define mmCRTC1_CRTC_FLOW_CONTROL                                               0x1d99
-+#define mmCRTC2_CRTC_FLOW_CONTROL                                               0x1f99
-+#define mmCRTC3_CRTC_FLOW_CONTROL                                               0x4199
-+#define mmCRTC4_CRTC_FLOW_CONTROL                                               0x4399
-+#define mmCRTC5_CRTC_FLOW_CONTROL                                               0x4599
-+#define mmCRTC_STEREO_FORCE_NEXT_EYE                                            0x1b9a
-+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1b9a
-+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1d9a
-+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1f9a
-+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                      0x419a
-+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                      0x439a
-+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                      0x459a
-+#define mmCRTC_AVSYNC_COUNTER                                                   0x1b9b
-+#define mmCRTC0_CRTC_AVSYNC_COUNTER                                             0x1b9b
-+#define mmCRTC1_CRTC_AVSYNC_COUNTER                                             0x1d9b
-+#define mmCRTC2_CRTC_AVSYNC_COUNTER                                             0x1f9b
-+#define mmCRTC3_CRTC_AVSYNC_COUNTER                                             0x419b
-+#define mmCRTC4_CRTC_AVSYNC_COUNTER                                             0x439b
-+#define mmCRTC5_CRTC_AVSYNC_COUNTER                                             0x459b
-+#define mmCRTC_CONTROL                                                          0x1b9c
-+#define mmCRTC0_CRTC_CONTROL                                                    0x1b9c
-+#define mmCRTC1_CRTC_CONTROL                                                    0x1d9c
-+#define mmCRTC2_CRTC_CONTROL                                                    0x1f9c
-+#define mmCRTC3_CRTC_CONTROL                                                    0x419c
-+#define mmCRTC4_CRTC_CONTROL                                                    0x439c
-+#define mmCRTC5_CRTC_CONTROL                                                    0x459c
-+#define mmCRTC_BLANK_CONTROL                                                    0x1b9d
-+#define mmCRTC0_CRTC_BLANK_CONTROL                                              0x1b9d
-+#define mmCRTC1_CRTC_BLANK_CONTROL                                              0x1d9d
-+#define mmCRTC2_CRTC_BLANK_CONTROL                                              0x1f9d
-+#define mmCRTC3_CRTC_BLANK_CONTROL                                              0x419d
-+#define mmCRTC4_CRTC_BLANK_CONTROL                                              0x439d
-+#define mmCRTC5_CRTC_BLANK_CONTROL                                              0x459d
-+#define mmCRTC_INTERLACE_CONTROL                                                0x1b9e
-+#define mmCRTC0_CRTC_INTERLACE_CONTROL                                          0x1b9e
-+#define mmCRTC1_CRTC_INTERLACE_CONTROL                                          0x1d9e
-+#define mmCRTC2_CRTC_INTERLACE_CONTROL                                          0x1f9e
-+#define mmCRTC3_CRTC_INTERLACE_CONTROL                                          0x419e
-+#define mmCRTC4_CRTC_INTERLACE_CONTROL                                          0x439e
-+#define mmCRTC5_CRTC_INTERLACE_CONTROL                                          0x459e
-+#define mmCRTC_INTERLACE_STATUS                                                 0x1b9f
-+#define mmCRTC0_CRTC_INTERLACE_STATUS                                           0x1b9f
-+#define mmCRTC1_CRTC_INTERLACE_STATUS                                           0x1d9f
-+#define mmCRTC2_CRTC_INTERLACE_STATUS                                           0x1f9f
-+#define mmCRTC3_CRTC_INTERLACE_STATUS                                           0x419f
-+#define mmCRTC4_CRTC_INTERLACE_STATUS                                           0x439f
-+#define mmCRTC5_CRTC_INTERLACE_STATUS                                           0x459f
-+#define mmCRTC_FIELD_INDICATION_CONTROL                                         0x1ba0
-+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                   0x1ba0
-+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                   0x1da0
-+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                   0x1fa0
-+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                   0x41a0
-+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                   0x43a0
-+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                   0x45a0
-+#define mmCRTC_PIXEL_DATA_READBACK0                                             0x1ba1
-+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                       0x1ba1
-+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                       0x1da1
-+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                       0x1fa1
-+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                       0x41a1
-+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                       0x43a1
-+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                       0x45a1
-+#define mmCRTC_PIXEL_DATA_READBACK1                                             0x1ba2
-+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                       0x1ba2
-+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                       0x1da2
-+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                       0x1fa2
-+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                       0x41a2
-+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                       0x43a2
-+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                       0x45a2
-+#define mmCRTC_STATUS                                                           0x1ba3
-+#define mmCRTC0_CRTC_STATUS                                                     0x1ba3
-+#define mmCRTC1_CRTC_STATUS                                                     0x1da3
-+#define mmCRTC2_CRTC_STATUS                                                     0x1fa3
-+#define mmCRTC3_CRTC_STATUS                                                     0x41a3
-+#define mmCRTC4_CRTC_STATUS                                                     0x43a3
-+#define mmCRTC5_CRTC_STATUS                                                     0x45a3
-+#define mmCRTC_STATUS_POSITION                                                  0x1ba4
-+#define mmCRTC0_CRTC_STATUS_POSITION                                            0x1ba4
-+#define mmCRTC1_CRTC_STATUS_POSITION                                            0x1da4
-+#define mmCRTC2_CRTC_STATUS_POSITION                                            0x1fa4
-+#define mmCRTC3_CRTC_STATUS_POSITION                                            0x41a4
-+#define mmCRTC4_CRTC_STATUS_POSITION                                            0x43a4
-+#define mmCRTC5_CRTC_STATUS_POSITION                                            0x45a4
-+#define mmCRTC_NOM_VERT_POSITION                                                0x1ba5
-+#define mmCRTC0_CRTC_NOM_VERT_POSITION                                          0x1ba5
-+#define mmCRTC1_CRTC_NOM_VERT_POSITION                                          0x1da5
-+#define mmCRTC2_CRTC_NOM_VERT_POSITION                                          0x1fa5
-+#define mmCRTC3_CRTC_NOM_VERT_POSITION                                          0x41a5
-+#define mmCRTC4_CRTC_NOM_VERT_POSITION                                          0x43a5
-+#define mmCRTC5_CRTC_NOM_VERT_POSITION                                          0x45a5
-+#define mmCRTC_STATUS_FRAME_COUNT                                               0x1ba6
-+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT                                         0x1ba6
-+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT                                         0x1da6
-+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT                                         0x1fa6
-+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT                                         0x41a6
-+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT                                         0x43a6
-+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT                                         0x45a6
-+#define mmCRTC_STATUS_VF_COUNT                                                  0x1ba7
-+#define mmCRTC0_CRTC_STATUS_VF_COUNT                                            0x1ba7
-+#define mmCRTC1_CRTC_STATUS_VF_COUNT                                            0x1da7
-+#define mmCRTC2_CRTC_STATUS_VF_COUNT                                            0x1fa7
-+#define mmCRTC3_CRTC_STATUS_VF_COUNT                                            0x41a7
-+#define mmCRTC4_CRTC_STATUS_VF_COUNT                                            0x43a7
-+#define mmCRTC5_CRTC_STATUS_VF_COUNT                                            0x45a7
-+#define mmCRTC_STATUS_HV_COUNT                                                  0x1ba8
-+#define mmCRTC0_CRTC_STATUS_HV_COUNT                                            0x1ba8
-+#define mmCRTC1_CRTC_STATUS_HV_COUNT                                            0x1da8
-+#define mmCRTC2_CRTC_STATUS_HV_COUNT                                            0x1fa8
-+#define mmCRTC3_CRTC_STATUS_HV_COUNT                                            0x41a8
-+#define mmCRTC4_CRTC_STATUS_HV_COUNT                                            0x43a8
-+#define mmCRTC5_CRTC_STATUS_HV_COUNT                                            0x45a8
-+#define mmCRTC_COUNT_CONTROL                                                    0x1ba9
-+#define mmCRTC0_CRTC_COUNT_CONTROL                                              0x1ba9
-+#define mmCRTC1_CRTC_COUNT_CONTROL                                              0x1da9
-+#define mmCRTC2_CRTC_COUNT_CONTROL                                              0x1fa9
-+#define mmCRTC3_CRTC_COUNT_CONTROL                                              0x41a9
-+#define mmCRTC4_CRTC_COUNT_CONTROL                                              0x43a9
-+#define mmCRTC5_CRTC_COUNT_CONTROL                                              0x45a9
-+#define mmCRTC_COUNT_RESET                                                      0x1baa
-+#define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
-+#define mmCRTC1_CRTC_COUNT_RESET                                                0x1daa
-+#define mmCRTC2_CRTC_COUNT_RESET                                                0x1faa
-+#define mmCRTC3_CRTC_COUNT_RESET                                                0x41aa
-+#define mmCRTC4_CRTC_COUNT_RESET                                                0x43aa
-+#define mmCRTC5_CRTC_COUNT_RESET                                                0x45aa
-+#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                     0x1bab
-+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1bab
-+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1dab
-+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1fab
-+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x41ab
-+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x43ab
-+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x45ab
-+#define mmCRTC_VERT_SYNC_CONTROL                                                0x1bac
-+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL                                          0x1bac
-+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL                                          0x1dac
-+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL                                          0x1fac
-+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL                                          0x41ac
-+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL                                          0x43ac
-+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL                                          0x45ac
-+#define mmCRTC_STEREO_STATUS                                                    0x1bad
-+#define mmCRTC0_CRTC_STEREO_STATUS                                              0x1bad
-+#define mmCRTC1_CRTC_STEREO_STATUS                                              0x1dad
-+#define mmCRTC2_CRTC_STEREO_STATUS                                              0x1fad
-+#define mmCRTC3_CRTC_STEREO_STATUS                                              0x41ad
-+#define mmCRTC4_CRTC_STEREO_STATUS                                              0x43ad
-+#define mmCRTC5_CRTC_STEREO_STATUS                                              0x45ad
-+#define mmCRTC_STEREO_CONTROL                                                   0x1bae
-+#define mmCRTC0_CRTC_STEREO_CONTROL                                             0x1bae
-+#define mmCRTC1_CRTC_STEREO_CONTROL                                             0x1dae
-+#define mmCRTC2_CRTC_STEREO_CONTROL                                             0x1fae
-+#define mmCRTC3_CRTC_STEREO_CONTROL                                             0x41ae
-+#define mmCRTC4_CRTC_STEREO_CONTROL                                             0x43ae
-+#define mmCRTC5_CRTC_STEREO_CONTROL                                             0x45ae
-+#define mmCRTC_SNAPSHOT_STATUS                                                  0x1baf
-+#define mmCRTC0_CRTC_SNAPSHOT_STATUS                                            0x1baf
-+#define mmCRTC1_CRTC_SNAPSHOT_STATUS                                            0x1daf
-+#define mmCRTC2_CRTC_SNAPSHOT_STATUS                                            0x1faf
-+#define mmCRTC3_CRTC_SNAPSHOT_STATUS                                            0x41af
-+#define mmCRTC4_CRTC_SNAPSHOT_STATUS                                            0x43af
-+#define mmCRTC5_CRTC_SNAPSHOT_STATUS                                            0x45af
-+#define mmCRTC_SNAPSHOT_CONTROL                                                 0x1bb0
-+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL                                           0x1bb0
-+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL                                           0x1db0
-+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL                                           0x1fb0
-+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL                                           0x41b0
-+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL                                           0x43b0
-+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL                                           0x45b0
-+#define mmCRTC_SNAPSHOT_POSITION                                                0x1bb1
-+#define mmCRTC0_CRTC_SNAPSHOT_POSITION                                          0x1bb1
-+#define mmCRTC1_CRTC_SNAPSHOT_POSITION                                          0x1db1
-+#define mmCRTC2_CRTC_SNAPSHOT_POSITION                                          0x1fb1
-+#define mmCRTC3_CRTC_SNAPSHOT_POSITION                                          0x41b1
-+#define mmCRTC4_CRTC_SNAPSHOT_POSITION                                          0x43b1
-+#define mmCRTC5_CRTC_SNAPSHOT_POSITION                                          0x45b1
-+#define mmCRTC_SNAPSHOT_FRAME                                                   0x1bb2
-+#define mmCRTC0_CRTC_SNAPSHOT_FRAME                                             0x1bb2
-+#define mmCRTC1_CRTC_SNAPSHOT_FRAME                                             0x1db2
-+#define mmCRTC2_CRTC_SNAPSHOT_FRAME                                             0x1fb2
-+#define mmCRTC3_CRTC_SNAPSHOT_FRAME                                             0x41b2
-+#define mmCRTC4_CRTC_SNAPSHOT_FRAME                                             0x43b2
-+#define mmCRTC5_CRTC_SNAPSHOT_FRAME                                             0x45b2
-+#define mmCRTC_START_LINE_CONTROL                                               0x1bb3
-+#define mmCRTC0_CRTC_START_LINE_CONTROL                                         0x1bb3
-+#define mmCRTC1_CRTC_START_LINE_CONTROL                                         0x1db3
-+#define mmCRTC2_CRTC_START_LINE_CONTROL                                         0x1fb3
-+#define mmCRTC3_CRTC_START_LINE_CONTROL                                         0x41b3
-+#define mmCRTC4_CRTC_START_LINE_CONTROL                                         0x43b3
-+#define mmCRTC5_CRTC_START_LINE_CONTROL                                         0x45b3
-+#define mmCRTC_INTERRUPT_CONTROL                                                0x1bb4
-+#define mmCRTC0_CRTC_INTERRUPT_CONTROL                                          0x1bb4
-+#define mmCRTC1_CRTC_INTERRUPT_CONTROL                                          0x1db4
-+#define mmCRTC2_CRTC_INTERRUPT_CONTROL                                          0x1fb4
-+#define mmCRTC3_CRTC_INTERRUPT_CONTROL                                          0x41b4
-+#define mmCRTC4_CRTC_INTERRUPT_CONTROL                                          0x43b4
-+#define mmCRTC5_CRTC_INTERRUPT_CONTROL                                          0x45b4
-+#define mmCRTC_UPDATE_LOCK                                                      0x1bb5
-+#define mmCRTC0_CRTC_UPDATE_LOCK                                                0x1bb5
-+#define mmCRTC1_CRTC_UPDATE_LOCK                                                0x1db5
-+#define mmCRTC2_CRTC_UPDATE_LOCK                                                0x1fb5
-+#define mmCRTC3_CRTC_UPDATE_LOCK                                                0x41b5
-+#define mmCRTC4_CRTC_UPDATE_LOCK                                                0x43b5
-+#define mmCRTC5_CRTC_UPDATE_LOCK                                                0x45b5
-+#define mmCRTC_DOUBLE_BUFFER_CONTROL                                            0x1bb6
-+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1bb6
-+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1db6
-+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1fb6
-+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                      0x41b6
-+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                      0x43b6
-+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                      0x45b6
-+#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE                                       0x1bb7
-+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1bb7
-+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1db7
-+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1fb7
-+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x41b7
-+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x43b7
-+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x45b7
-+#define mmCRTC_TEST_PATTERN_CONTROL                                             0x1bba
-+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                       0x1bba
-+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                       0x1dba
-+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                       0x1fba
-+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                       0x41ba
-+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                       0x43ba
-+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                       0x45ba
-+#define mmCRTC_TEST_PATTERN_PARAMETERS                                          0x1bbb
-+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                    0x1bbb
-+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                    0x1dbb
-+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                    0x1fbb
-+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                    0x41bb
-+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                    0x43bb
-+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                    0x45bb
-+#define mmCRTC_TEST_PATTERN_COLOR                                               0x1bbc
-+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR                                         0x1bbc
-+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR                                         0x1dbc
-+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR                                         0x1fbc
-+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR                                         0x41bc
-+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR                                         0x43bc
-+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR                                         0x45bc
-+#define mmCRTC_MASTER_UPDATE_LOCK                                               0x1bbd
-+#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK                                         0x1bbd
-+#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK                                         0x1dbd
-+#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK                                         0x1fbd
-+#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK                                         0x41bd
-+#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK                                         0x43bd
-+#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK                                         0x45bd
-+#define mmCRTC_MASTER_UPDATE_MODE                                               0x1bbe
-+#define mmCRTC0_CRTC_MASTER_UPDATE_MODE                                         0x1bbe
-+#define mmCRTC1_CRTC_MASTER_UPDATE_MODE                                         0x1dbe
-+#define mmCRTC2_CRTC_MASTER_UPDATE_MODE                                         0x1fbe
-+#define mmCRTC3_CRTC_MASTER_UPDATE_MODE                                         0x41be
-+#define mmCRTC4_CRTC_MASTER_UPDATE_MODE                                         0x43be
-+#define mmCRTC5_CRTC_MASTER_UPDATE_MODE                                         0x45be
-+#define mmCRTC_MVP_INBAND_CNTL_INSERT                                           0x1bbf
-+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1bbf
-+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1dbf
-+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1fbf
-+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                     0x41bf
-+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                     0x43bf
-+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                     0x45bf
-+#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER                                     0x1bc0
-+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1bc0
-+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1dc0
-+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1fc0
-+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x41c0
-+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x43c0
-+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x45c0
-+#define mmCRTC_MVP_STATUS                                                       0x1bc1
-+#define mmCRTC0_CRTC_MVP_STATUS                                                 0x1bc1
-+#define mmCRTC1_CRTC_MVP_STATUS                                                 0x1dc1
-+#define mmCRTC2_CRTC_MVP_STATUS                                                 0x1fc1
-+#define mmCRTC3_CRTC_MVP_STATUS                                                 0x41c1
-+#define mmCRTC4_CRTC_MVP_STATUS                                                 0x43c1
-+#define mmCRTC5_CRTC_MVP_STATUS                                                 0x45c1
-+#define mmCRTC_MASTER_EN                                                        0x1bc2
-+#define mmCRTC0_CRTC_MASTER_EN                                                  0x1bc2
-+#define mmCRTC1_CRTC_MASTER_EN                                                  0x1dc2
-+#define mmCRTC2_CRTC_MASTER_EN                                                  0x1fc2
-+#define mmCRTC3_CRTC_MASTER_EN                                                  0x41c2
-+#define mmCRTC4_CRTC_MASTER_EN                                                  0x43c2
-+#define mmCRTC5_CRTC_MASTER_EN                                                  0x45c2
-+#define mmCRTC_ALLOW_STOP_OFF_V_CNT                                             0x1bc3
-+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1bc3
-+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1dc3
-+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1fc3
-+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x41c3
-+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x43c3
-+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x45c3
-+#define mmCRTC_V_UPDATE_INT_STATUS                                              0x1bc4
-+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                        0x1bc4
-+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                        0x1dc4
-+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                        0x1fc4
-+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                        0x41c4
-+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                        0x43c4
-+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                        0x45c4
-+#define mmCRTC_OVERSCAN_COLOR                                                   0x1bc8
-+#define mmCRTC0_CRTC_OVERSCAN_COLOR                                             0x1bc8
-+#define mmCRTC1_CRTC_OVERSCAN_COLOR                                             0x1dc8
-+#define mmCRTC2_CRTC_OVERSCAN_COLOR                                             0x1fc8
-+#define mmCRTC3_CRTC_OVERSCAN_COLOR                                             0x41c8
-+#define mmCRTC4_CRTC_OVERSCAN_COLOR                                             0x43c8
-+#define mmCRTC5_CRTC_OVERSCAN_COLOR                                             0x45c8
-+#define mmCRTC_OVERSCAN_COLOR_EXT                                               0x1bc9
-+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                         0x1bc9
-+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                         0x1dc9
-+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                         0x1fc9
-+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                         0x41c9
-+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                         0x43c9
-+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                         0x45c9
-+#define mmCRTC_BLANK_DATA_COLOR                                                 0x1bca
-+#define mmCRTC0_CRTC_BLANK_DATA_COLOR                                           0x1bca
-+#define mmCRTC1_CRTC_BLANK_DATA_COLOR                                           0x1dca
-+#define mmCRTC2_CRTC_BLANK_DATA_COLOR                                           0x1fca
-+#define mmCRTC3_CRTC_BLANK_DATA_COLOR                                           0x41ca
-+#define mmCRTC4_CRTC_BLANK_DATA_COLOR                                           0x43ca
-+#define mmCRTC5_CRTC_BLANK_DATA_COLOR                                           0x45ca
-+#define mmCRTC_BLANK_DATA_COLOR_EXT                                             0x1bcb
-+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                       0x1bcb
-+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                       0x1dcb
-+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                       0x1fcb
-+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                       0x41cb
-+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                       0x43cb
-+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                       0x45cb
-+#define mmCRTC_BLACK_COLOR                                                      0x1bcc
-+#define mmCRTC0_CRTC_BLACK_COLOR                                                0x1bcc
-+#define mmCRTC1_CRTC_BLACK_COLOR                                                0x1dcc
-+#define mmCRTC2_CRTC_BLACK_COLOR                                                0x1fcc
-+#define mmCRTC3_CRTC_BLACK_COLOR                                                0x41cc
-+#define mmCRTC4_CRTC_BLACK_COLOR                                                0x43cc
-+#define mmCRTC5_CRTC_BLACK_COLOR                                                0x45cc
-+#define mmCRTC_BLACK_COLOR_EXT                                                  0x1bcd
-+#define mmCRTC0_CRTC_BLACK_COLOR_EXT                                            0x1bcd
-+#define mmCRTC1_CRTC_BLACK_COLOR_EXT                                            0x1dcd
-+#define mmCRTC2_CRTC_BLACK_COLOR_EXT                                            0x1fcd
-+#define mmCRTC3_CRTC_BLACK_COLOR_EXT                                            0x41cd
-+#define mmCRTC4_CRTC_BLACK_COLOR_EXT                                            0x43cd
-+#define mmCRTC5_CRTC_BLACK_COLOR_EXT                                            0x45cd
-+#define mmCRTC_VERTICAL_INTERRUPT0_POSITION                                     0x1bce
-+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1bce
-+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1dce
-+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1fce
-+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x41ce
-+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x43ce
-+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x45ce
-+#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL                                      0x1bcf
-+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1bcf
-+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1dcf
-+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1fcf
-+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x41cf
-+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x43cf
-+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x45cf
-+#define mmCRTC_VERTICAL_INTERRUPT1_POSITION                                     0x1bd0
-+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1bd0
-+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1dd0
-+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1fd0
-+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x41d0
-+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x43d0
-+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x45d0
-+#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL                                      0x1bd1
-+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1bd1
-+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1dd1
-+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1fd1
-+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x41d1
-+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x43d1
-+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x45d1
-+#define mmCRTC_VERTICAL_INTERRUPT2_POSITION                                     0x1bd2
-+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1bd2
-+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1dd2
-+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1fd2
-+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x41d2
-+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x43d2
-+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x45d2
-+#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL                                      0x1bd3
-+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1bd3
-+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1dd3
-+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1fd3
-+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x41d3
-+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x43d3
-+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x45d3
-+#define mmCRTC_CRC_CNTL                                                         0x1bd4
-+#define mmCRTC0_CRTC_CRC_CNTL                                                   0x1bd4
-+#define mmCRTC1_CRTC_CRC_CNTL                                                   0x1dd4
-+#define mmCRTC2_CRTC_CRC_CNTL                                                   0x1fd4
-+#define mmCRTC3_CRTC_CRC_CNTL                                                   0x41d4
-+#define mmCRTC4_CRTC_CRC_CNTL                                                   0x43d4
-+#define mmCRTC5_CRTC_CRC_CNTL                                                   0x45d4
-+#define mmCRTC_CRC0_WINDOWA_X_CONTROL                                           0x1bd5
-+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1bd5
-+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1dd5
-+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1fd5
-+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x41d5
-+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x43d5
-+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x45d5
-+#define mmCRTC_CRC0_WINDOWA_Y_CONTROL                                           0x1bd6
-+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1bd6
-+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1dd6
-+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1fd6
-+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x41d6
-+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x43d6
-+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x45d6
-+#define mmCRTC_CRC0_WINDOWB_X_CONTROL                                           0x1bd7
-+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1bd7
-+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1dd7
-+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1fd7
-+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x41d7
-+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x43d7
-+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x45d7
-+#define mmCRTC_CRC0_WINDOWB_Y_CONTROL                                           0x1bd8
-+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1bd8
-+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1dd8
-+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1fd8
-+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x41d8
-+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x43d8
-+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x45d8
-+#define mmCRTC_CRC0_DATA_RG                                                     0x1bd9
-+#define mmCRTC0_CRTC_CRC0_DATA_RG                                               0x1bd9
-+#define mmCRTC1_CRTC_CRC0_DATA_RG                                               0x1dd9
-+#define mmCRTC2_CRTC_CRC0_DATA_RG                                               0x1fd9
-+#define mmCRTC3_CRTC_CRC0_DATA_RG                                               0x41d9
-+#define mmCRTC4_CRTC_CRC0_DATA_RG                                               0x43d9
-+#define mmCRTC5_CRTC_CRC0_DATA_RG                                               0x45d9
-+#define mmCRTC_CRC0_DATA_B                                                      0x1bda
-+#define mmCRTC0_CRTC_CRC0_DATA_B                                                0x1bda
-+#define mmCRTC1_CRTC_CRC0_DATA_B                                                0x1dda
-+#define mmCRTC2_CRTC_CRC0_DATA_B                                                0x1fda
-+#define mmCRTC3_CRTC_CRC0_DATA_B                                                0x41da
-+#define mmCRTC4_CRTC_CRC0_DATA_B                                                0x43da
-+#define mmCRTC5_CRTC_CRC0_DATA_B                                                0x45da
-+#define mmCRTC_CRC1_WINDOWA_X_CONTROL                                           0x1bdb
-+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1bdb
-+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1ddb
-+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1fdb
-+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x41db
-+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x43db
-+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x45db
-+#define mmCRTC_CRC1_WINDOWA_Y_CONTROL                                           0x1bdc
-+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1bdc
-+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1ddc
-+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1fdc
-+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x41dc
-+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x43dc
-+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x45dc
-+#define mmCRTC_CRC1_WINDOWB_X_CONTROL                                           0x1bdd
-+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1bdd
-+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1ddd
-+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1fdd
-+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x41dd
-+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x43dd
-+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x45dd
-+#define mmCRTC_CRC1_WINDOWB_Y_CONTROL                                           0x1bde
-+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1bde
-+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1dde
-+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1fde
-+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x41de
-+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x43de
-+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x45de
-+#define mmCRTC_CRC1_DATA_RG                                                     0x1bdf
-+#define mmCRTC0_CRTC_CRC1_DATA_RG                                               0x1bdf
-+#define mmCRTC1_CRTC_CRC1_DATA_RG                                               0x1ddf
-+#define mmCRTC2_CRTC_CRC1_DATA_RG                                               0x1fdf
-+#define mmCRTC3_CRTC_CRC1_DATA_RG                                               0x41df
-+#define mmCRTC4_CRTC_CRC1_DATA_RG                                               0x43df
-+#define mmCRTC5_CRTC_CRC1_DATA_RG                                               0x45df
-+#define mmCRTC_CRC1_DATA_B                                                      0x1be0
-+#define mmCRTC0_CRTC_CRC1_DATA_B                                                0x1be0
-+#define mmCRTC1_CRTC_CRC1_DATA_B                                                0x1de0
-+#define mmCRTC2_CRTC_CRC1_DATA_B                                                0x1fe0
-+#define mmCRTC3_CRTC_CRC1_DATA_B                                                0x41e0
-+#define mmCRTC4_CRTC_CRC1_DATA_B                                                0x43e0
-+#define mmCRTC5_CRTC_CRC1_DATA_B                                                0x45e0
-+#define mmCRTC_EXT_TIMING_SYNC_CONTROL                                          0x1be1
-+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1be1
-+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1de1
-+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1fe1
-+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x41e1
-+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x43e1
-+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x45e1
-+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START                                     0x1be2
-+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1be2
-+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1de2
-+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1fe2
-+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x41e2
-+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x43e2
-+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x45e2
-+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END                                       0x1be3
-+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1be3
-+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1de3
-+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1fe3
-+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x41e3
-+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x43e3
-+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x45e3
-+#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                           0x1be4
-+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1be4
-+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1de4
-+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1fe4
-+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x41e4
-+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x43e4
-+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x45e4
-+#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                0x1be5
-+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1be5
-+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1de5
-+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1fe5
-+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x41e5
-+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x43e5
-+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x45e5
-+#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                         0x1be6
-+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1be6
-+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1de6
-+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1fe6
-+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x41e6
-+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x43e6
-+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x45e6
-+#define mmCRTC_STATIC_SCREEN_CONTROL                                            0x1be7
-+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                      0x1be7
-+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                      0x1de7
-+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                      0x1fe7
-+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                      0x41e7
-+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                      0x43e7
-+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                      0x45e7
-+#define mmCRTC_3D_STRUCTURE_CONTROL                                             0x1b78
-+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                       0x1b78
-+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                       0x1d78
-+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                       0x1f78
-+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                       0x4178
-+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                       0x4378
-+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                       0x4578
-+#define mmCRTC_GSL_VSYNC_GAP                                                    0x1b79
-+#define mmCRTC0_CRTC_GSL_VSYNC_GAP                                              0x1b79
-+#define mmCRTC1_CRTC_GSL_VSYNC_GAP                                              0x1d79
-+#define mmCRTC2_CRTC_GSL_VSYNC_GAP                                              0x1f79
-+#define mmCRTC3_CRTC_GSL_VSYNC_GAP                                              0x4179
-+#define mmCRTC4_CRTC_GSL_VSYNC_GAP                                              0x4379
-+#define mmCRTC5_CRTC_GSL_VSYNC_GAP                                              0x4579
-+#define mmCRTC_GSL_WINDOW                                                       0x1b7a
-+#define mmCRTC0_CRTC_GSL_WINDOW                                                 0x1b7a
-+#define mmCRTC1_CRTC_GSL_WINDOW                                                 0x1d7a
-+#define mmCRTC2_CRTC_GSL_WINDOW                                                 0x1f7a
-+#define mmCRTC3_CRTC_GSL_WINDOW                                                 0x417a
-+#define mmCRTC4_CRTC_GSL_WINDOW                                                 0x437a
-+#define mmCRTC5_CRTC_GSL_WINDOW                                                 0x457a
-+#define mmCRTC_GSL_CONTROL                                                      0x1b7b
-+#define mmCRTC0_CRTC_GSL_CONTROL                                                0x1b7b
-+#define mmCRTC1_CRTC_GSL_CONTROL                                                0x1d7b
-+#define mmCRTC2_CRTC_GSL_CONTROL                                                0x1f7b
-+#define mmCRTC3_CRTC_GSL_CONTROL                                                0x417b
-+#define mmCRTC4_CRTC_GSL_CONTROL                                                0x437b
-+#define mmCRTC5_CRTC_GSL_CONTROL                                                0x457b
-+#define mmCRTC_TEST_DEBUG_INDEX                                                 0x1bc6
-+#define mmCRTC0_CRTC_TEST_DEBUG_INDEX                                           0x1bc6
-+#define mmCRTC1_CRTC_TEST_DEBUG_INDEX                                           0x1dc6
-+#define mmCRTC2_CRTC_TEST_DEBUG_INDEX                                           0x1fc6
-+#define mmCRTC3_CRTC_TEST_DEBUG_INDEX                                           0x41c6
-+#define mmCRTC4_CRTC_TEST_DEBUG_INDEX                                           0x43c6
-+#define mmCRTC5_CRTC_TEST_DEBUG_INDEX                                           0x45c6
-+#define mmCRTC_TEST_DEBUG_DATA                                                  0x1bc7
-+#define mmCRTC0_CRTC_TEST_DEBUG_DATA                                            0x1bc7
-+#define mmCRTC1_CRTC_TEST_DEBUG_DATA                                            0x1dc7
-+#define mmCRTC2_CRTC_TEST_DEBUG_DATA                                            0x1fc7
-+#define mmCRTC3_CRTC_TEST_DEBUG_DATA                                            0x41c7
-+#define mmCRTC4_CRTC_TEST_DEBUG_DATA                                            0x43c7
-+#define mmCRTC5_CRTC_TEST_DEBUG_DATA                                            0x45c7
-+#define mmDAC_ENABLE                                                            0x16aa
-+#define mmDAC_SOURCE_SELECT                                                     0x16ab
-+#define mmDAC_CRC_EN                                                            0x16ac
-+#define mmDAC_CRC_CONTROL                                                       0x16ad
-+#define mmDAC_CRC_SIG_RGB_MASK                                                  0x16ae
-+#define mmDAC_CRC_SIG_CONTROL_MASK                                              0x16af
-+#define mmDAC_CRC_SIG_RGB                                                       0x16b0
-+#define mmDAC_CRC_SIG_CONTROL                                                   0x16b1
-+#define mmDAC_SYNC_TRISTATE_CONTROL                                             0x16b2
-+#define mmDAC_STEREOSYNC_SELECT                                                 0x16b3
-+#define mmDAC_AUTODETECT_CONTROL                                                0x16b4
-+#define mmDAC_AUTODETECT_CONTROL2                                               0x16b5
-+#define mmDAC_AUTODETECT_CONTROL3                                               0x16b6
-+#define mmDAC_AUTODETECT_STATUS                                                 0x16b7
-+#define mmDAC_AUTODETECT_INT_CONTROL                                            0x16b8
-+#define mmDAC_FORCE_OUTPUT_CNTL                                                 0x16b9
-+#define mmDAC_FORCE_DATA                                                        0x16ba
-+#define mmDAC_POWERDOWN                                                         0x16bb
-+#define mmDAC_CONTROL                                                           0x16bc
-+#define mmDAC_COMPARATOR_ENABLE                                                 0x16bd
-+#define mmDAC_COMPARATOR_OUTPUT                                                 0x16be
-+#define mmDAC_PWR_CNTL                                                          0x16bf
-+#define mmDAC_DFT_CONFIG                                                        0x16c0
-+#define mmDAC_FIFO_STATUS                                                       0x16c1
-+#define mmDAC_TEST_DEBUG_INDEX                                                  0x16c2
-+#define mmDAC_TEST_DEBUG_DATA                                                   0x16c3
-+#define mmPERFCOUNTER_CNTL                                                      0x170
-+#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                          0x170
-+#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                          0x358
-+#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                          0x364
-+#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                          0x18c8
-+#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                          0x1b24
-+#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                          0x1d24
-+#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                          0x1f24
-+#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                          0x4124
-+#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                          0x4324
-+#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                          0x4524
-+#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                         0x4724
-+#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                         0x59a0
-+#define mmDC_PERFMON12_PERFCOUNTER_CNTL                                         0x5f68
-+#define mmDC_PERFMON13_PERFCOUNTER_CNTL                                         0x9924
-+#define mmPERFCOUNTER_STATE                                                     0x171
-+#define mmDC_PERFMON0_PERFCOUNTER_STATE                                         0x171
-+#define mmDC_PERFMON1_PERFCOUNTER_STATE                                         0x359
-+#define mmDC_PERFMON2_PERFCOUNTER_STATE                                         0x365
-+#define mmDC_PERFMON3_PERFCOUNTER_STATE                                         0x18c9
-+#define mmDC_PERFMON4_PERFCOUNTER_STATE                                         0x1b25
-+#define mmDC_PERFMON5_PERFCOUNTER_STATE                                         0x1d25
-+#define mmDC_PERFMON6_PERFCOUNTER_STATE                                         0x1f25
-+#define mmDC_PERFMON7_PERFCOUNTER_STATE                                         0x4125
-+#define mmDC_PERFMON8_PERFCOUNTER_STATE                                         0x4325
-+#define mmDC_PERFMON9_PERFCOUNTER_STATE                                         0x4525
-+#define mmDC_PERFMON10_PERFCOUNTER_STATE                                        0x4725
-+#define mmDC_PERFMON11_PERFCOUNTER_STATE                                        0x59a1
-+#define mmDC_PERFMON12_PERFCOUNTER_STATE                                        0x5f69
-+#define mmDC_PERFMON13_PERFCOUNTER_STATE                                        0x9925
-+#define mmPERFMON_CNTL                                                          0x173
-+#define mmDC_PERFMON0_PERFMON_CNTL                                              0x173
-+#define mmDC_PERFMON1_PERFMON_CNTL                                              0x35b
-+#define mmDC_PERFMON2_PERFMON_CNTL                                              0x367
-+#define mmDC_PERFMON3_PERFMON_CNTL                                              0x18cb
-+#define mmDC_PERFMON4_PERFMON_CNTL                                              0x1b27
-+#define mmDC_PERFMON5_PERFMON_CNTL                                              0x1d27
-+#define mmDC_PERFMON6_PERFMON_CNTL                                              0x1f27
-+#define mmDC_PERFMON7_PERFMON_CNTL                                              0x4127
-+#define mmDC_PERFMON8_PERFMON_CNTL                                              0x4327
-+#define mmDC_PERFMON9_PERFMON_CNTL                                              0x4527
-+#define mmDC_PERFMON10_PERFMON_CNTL                                             0x4727
-+#define mmDC_PERFMON11_PERFMON_CNTL                                             0x59a3
-+#define mmDC_PERFMON12_PERFMON_CNTL                                             0x5f6b
-+#define mmDC_PERFMON13_PERFMON_CNTL                                             0x9927
-+#define mmPERFMON_CNTL2                                                         0x17a
-+#define mmDC_PERFMON0_PERFMON_CNTL2                                             0x17a
-+#define mmDC_PERFMON1_PERFMON_CNTL2                                             0x362
-+#define mmDC_PERFMON2_PERFMON_CNTL2                                             0x36e
-+#define mmDC_PERFMON3_PERFMON_CNTL2                                             0x18d2
-+#define mmDC_PERFMON4_PERFMON_CNTL2                                             0x1b2e
-+#define mmDC_PERFMON5_PERFMON_CNTL2                                             0x1d2e
-+#define mmDC_PERFMON6_PERFMON_CNTL2                                             0x1f2e
-+#define mmDC_PERFMON7_PERFMON_CNTL2                                             0x412e
-+#define mmDC_PERFMON8_PERFMON_CNTL2                                             0x432e
-+#define mmDC_PERFMON9_PERFMON_CNTL2                                             0x452e
-+#define mmDC_PERFMON10_PERFMON_CNTL2                                            0x472e
-+#define mmDC_PERFMON11_PERFMON_CNTL2                                            0x59aa
-+#define mmDC_PERFMON12_PERFMON_CNTL2                                            0x5f72
-+#define mmDC_PERFMON13_PERFMON_CNTL2                                            0x992e
-+#define mmPERFMON_CVALUE_INT_MISC                                               0x172
-+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                   0x172
-+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                   0x35a
-+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                   0x366
-+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                   0x18ca
-+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                   0x1b26
-+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                   0x1d26
-+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                   0x1f26
-+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                   0x4126
-+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                   0x4326
-+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                   0x4526
-+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                  0x4726
-+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                  0x59a2
-+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                  0x5f6a
-+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                  0x9926
-+#define mmPERFMON_CVALUE_LOW                                                    0x174
-+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                        0x174
-+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                        0x35c
-+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                        0x368
-+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                        0x18cc
-+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                        0x1b28
-+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                        0x1d28
-+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                        0x1f28
-+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                        0x4128
-+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                        0x4328
-+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                        0x4528
-+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                       0x4728
-+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                       0x59a4
-+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                       0x5f6c
-+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                       0x9928
-+#define mmPERFMON_HI                                                            0x175
-+#define mmDC_PERFMON0_PERFMON_HI                                                0x175
-+#define mmDC_PERFMON1_PERFMON_HI                                                0x35d
-+#define mmDC_PERFMON2_PERFMON_HI                                                0x369
-+#define mmDC_PERFMON3_PERFMON_HI                                                0x18cd
-+#define mmDC_PERFMON4_PERFMON_HI                                                0x1b29
-+#define mmDC_PERFMON5_PERFMON_HI                                                0x1d29
-+#define mmDC_PERFMON6_PERFMON_HI                                                0x1f29
-+#define mmDC_PERFMON7_PERFMON_HI                                                0x4129
-+#define mmDC_PERFMON8_PERFMON_HI                                                0x4329
-+#define mmDC_PERFMON9_PERFMON_HI                                                0x4529
-+#define mmDC_PERFMON10_PERFMON_HI                                               0x4729
-+#define mmDC_PERFMON11_PERFMON_HI                                               0x59a5
-+#define mmDC_PERFMON12_PERFMON_HI                                               0x5f6d
-+#define mmDC_PERFMON13_PERFMON_HI                                               0x9929
-+#define mmPERFMON_LOW                                                           0x176
-+#define mmDC_PERFMON0_PERFMON_LOW                                               0x176
-+#define mmDC_PERFMON1_PERFMON_LOW                                               0x35e
-+#define mmDC_PERFMON2_PERFMON_LOW                                               0x36a
-+#define mmDC_PERFMON3_PERFMON_LOW                                               0x18ce
-+#define mmDC_PERFMON4_PERFMON_LOW                                               0x1b2a
-+#define mmDC_PERFMON5_PERFMON_LOW                                               0x1d2a
-+#define mmDC_PERFMON6_PERFMON_LOW                                               0x1f2a
-+#define mmDC_PERFMON7_PERFMON_LOW                                               0x412a
-+#define mmDC_PERFMON8_PERFMON_LOW                                               0x432a
-+#define mmDC_PERFMON9_PERFMON_LOW                                               0x452a
-+#define mmDC_PERFMON10_PERFMON_LOW                                              0x472a
-+#define mmDC_PERFMON11_PERFMON_LOW                                              0x59a6
-+#define mmDC_PERFMON12_PERFMON_LOW                                              0x5f6e
-+#define mmDC_PERFMON13_PERFMON_LOW                                              0x992a
-+#define mmPERFMON_TEST_DEBUG_INDEX                                              0x177
-+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX                                  0x177
-+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX                                  0x35f
-+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX                                  0x36b
-+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX                                  0x18cf
-+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX                                  0x1b2b
-+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX                                  0x1d2b
-+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                                  0x1f2b
-+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                                  0x412b
-+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                                  0x432b
-+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                                  0x452b
-+#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                                 0x472b
-+#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                                 0x59a7
-+#define mmDC_PERFMON12_PERFMON_TEST_DEBUG_INDEX                                 0x5f6f
-+#define mmDC_PERFMON13_PERFMON_TEST_DEBUG_INDEX                                 0x992b
-+#define mmPERFMON_TEST_DEBUG_DATA                                               0x178
-+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA                                   0x178
-+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA                                   0x360
-+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA                                   0x36c
-+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA                                   0x18d0
-+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA                                   0x1b2c
-+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA                                   0x1d2c
-+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                                   0x1f2c
-+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                                   0x412c
-+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                                   0x432c
-+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                                   0x452c
-+#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA                                  0x472c
-+#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA                                  0x59a8
-+#define mmDC_PERFMON12_PERFMON_TEST_DEBUG_DATA                                  0x5f70
-+#define mmDC_PERFMON13_PERFMON_TEST_DEBUG_DATA                                  0x992c
-+#define mmREFCLK_CNTL                                                           0x109
-+#define mmDCCG_CBUS_ANTIGLITCH_RESETB                                           0x15c
-+#define mmDCCG_CBUS_SPARE                                                       0x15d
-+#define mmDCCG_CBUS_WRCMD_DELAY                                                 0x110
-+#define mmDPREFCLK_CNTL                                                         0x118
-+#define mmDCE_VERSION                                                           0x11e
-+#define mmAVSYNC_COUNTER_WRITE                                                  0x12a
-+#define mmAVSYNC_COUNTER_CONTROL                                                0x12b
-+#define mmAVSYNC_COUNTER_READ                                                   0x12f
-+#define mmDCCG_GTC_CNTL                                                         0x120
-+#define mmDCCG_GTC_DTO_INCR                                                     0x121
-+#define mmDCCG_GTC_DTO_MODULO                                                   0x122
-+#define mmDCCG_GTC_CURRENT                                                      0x123
-+#define mmDCCG_DS_DTO_INCR                                                      0x113
-+#define mmDCCG_DS_DTO_MODULO                                                    0x114
-+#define mmDCCG_DS_CNTL                                                          0x115
-+#define mmDCCG_DS_HW_CAL_INTERVAL                                               0x116
-+#define mmDCCG_DS_DEBUG_CNTL                                                    0x112
-+#define mmDMCU_SMU_INTERRUPT_CNTL                                               0x12c
-+#define mmSMU_CONTROL                                                           0x12d
-+#define mmSMU_INTERRUPT_CONTROL                                                 0x12e
-+#define mmDAC_CLK_ENABLE                                                        0x128
-+#define mmDVO_CLK_ENABLE                                                        0x129
-+#define mmDCCG_GATE_DISABLE_CNTL                                                0x134
-+#define mmDCCG_GATE_DISABLE_CNTL2                                               0x13c
-+#define mmDISPCLK_CGTT_BLK_CTRL_REG                                             0x135
-+#define mmSCLK_CGTT_BLK_CTRL_REG                                                0x136
-+#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                            0x108
-+#define mmREFCLK_CGTT_BLK_CTRL_REG                                              0x10b
-+#define mmSYMCLK_CGTT_BLK_CTRL_REG                                              0x13d
-+#define mmDCCG_CAC_STATUS                                                       0x137
-+#define mmPIXCLK0_RESYNC_CNTL                                                   0x13a
-+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                            0x100
-+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                            0x101
-+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                            0x102
-+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                            0x103
-+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                            0x10c
-+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL                                            0x13e
-+#define mmMICROSECOND_TIME_BASE_DIV                                             0x13b
-+#define mmDCCG_DISP_CNTL_REG                                                    0x13f
-+#define mmMILLISECOND_TIME_BASE_DIV                                             0x130
-+#define mmDISPCLK_FREQ_CHANGE_CNTL                                              0x131
-+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                            0x132
-+#define mmDCCG_PERFMON_CNTL                                                     0x133
-+#define mmDCCG_PERFMON_CNTL2                                                    0x10e
-+#define mmCRTC0_PIXEL_RATE_CNTL                                                 0x140
-+#define mmDP_DTO0_PHASE                                                         0x141
-+#define mmDP_DTO0_MODULO                                                        0x142
-+#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL                                          0x143
-+#define mmCRTC1_PIXEL_RATE_CNTL                                                 0x144
-+#define mmDP_DTO1_PHASE                                                         0x145
-+#define mmDP_DTO1_MODULO                                                        0x146
-+#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL                                          0x147
-+#define mmCRTC2_PIXEL_RATE_CNTL                                                 0x148
-+#define mmDP_DTO2_PHASE                                                         0x149
-+#define mmDP_DTO2_MODULO                                                        0x14a
-+#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL                                          0x14b
-+#define mmCRTC3_PIXEL_RATE_CNTL                                                 0x14c
-+#define mmDP_DTO3_PHASE                                                         0x14d
-+#define mmDP_DTO3_MODULO                                                        0x14e
-+#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL                                          0x14f
-+#define mmCRTC4_PIXEL_RATE_CNTL                                                 0x150
-+#define mmDP_DTO4_PHASE                                                         0x151
-+#define mmDP_DTO4_MODULO                                                        0x152
-+#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL                                          0x153
-+#define mmCRTC5_PIXEL_RATE_CNTL                                                 0x154
-+#define mmDP_DTO5_PHASE                                                         0x155
-+#define mmDP_DTO5_MODULO                                                        0x156
-+#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL                                          0x157
-+#define mmDCCG_SOFT_RESET                                                       0x15f
-+#define mmSYMCLKA_CLOCK_ENABLE                                                  0x160
-+#define mmSYMCLKB_CLOCK_ENABLE                                                  0x161
-+#define mmSYMCLKC_CLOCK_ENABLE                                                  0x162
-+#define mmSYMCLKD_CLOCK_ENABLE                                                  0x163
-+#define mmSYMCLKE_CLOCK_ENABLE                                                  0x164
-+#define mmSYMCLKF_CLOCK_ENABLE                                                  0x165
-+#define mmDPDBG_CLK_FORCE_CONTROL                                               0x10d
-+#define mmDCCG_AUDIO_DTO_SOURCE                                                 0x16b
-+#define mmDCCG_AUDIO_DTO0_PHASE                                                 0x16c
-+#define mmDCCG_AUDIO_DTO0_MODULE                                                0x16d
-+#define mmDCCG_AUDIO_DTO1_PHASE                                                 0x16e
-+#define mmDCCG_AUDIO_DTO1_MODULE                                                0x16f
-+#define mmDCCG_TEST_DEBUG_INDEX                                                 0x17c
-+#define mmDCCG_TEST_DEBUG_DATA                                                  0x17d
-+#define mmDCCG_TEST_CLK_SEL                                                     0x17e
-+#define mmCPLL_MACRO_CNTL_RESERVED0                                             0x5fd0
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0                                  0x5fd0
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                                  0x5fdc
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                                  0x5fe8
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                                  0x5ff4
-+#define mmCPLL_MACRO_CNTL_RESERVED1                                             0x5fd1
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1                                  0x5fd1
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                                  0x5fdd
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                                  0x5fe9
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                                  0x5ff5
-+#define mmCPLL_MACRO_CNTL_RESERVED2                                             0x5fd2
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2                                  0x5fd2
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                                  0x5fde
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                                  0x5fea
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                                  0x5ff6
-+#define mmCPLL_MACRO_CNTL_RESERVED3                                             0x5fd3
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3                                  0x5fd3
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                                  0x5fdf
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                                  0x5feb
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                                  0x5ff7
-+#define mmCPLL_MACRO_CNTL_RESERVED4                                             0x5fd4
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4                                  0x5fd4
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                                  0x5fe0
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                                  0x5fec
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                                  0x5ff8
-+#define mmCPLL_MACRO_CNTL_RESERVED5                                             0x5fd5
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5                                  0x5fd5
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                                  0x5fe1
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                                  0x5fed
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                                  0x5ff9
-+#define mmCPLL_MACRO_CNTL_RESERVED6                                             0x5fd6
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6                                  0x5fd6
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                                  0x5fe2
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                                  0x5fee
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                                  0x5ffa
-+#define mmCPLL_MACRO_CNTL_RESERVED7                                             0x5fd7
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7                                  0x5fd7
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                                  0x5fe3
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                                  0x5fef
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                                  0x5ffb
-+#define mmCPLL_MACRO_CNTL_RESERVED8                                             0x5fd8
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8                                  0x5fd8
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                                  0x5fe4
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                                  0x5ff0
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                                  0x5ffc
-+#define mmCPLL_MACRO_CNTL_RESERVED9                                             0x5fd9
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9                                  0x5fd9
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                                  0x5fe5
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                                  0x5ff1
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                                  0x5ffd
-+#define mmCPLL_MACRO_CNTL_RESERVED10                                            0x5fda
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10                                 0x5fda
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                                 0x5fe6
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                                 0x5ff2
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                                 0x5ffe
-+#define mmCPLL_MACRO_CNTL_RESERVED11                                            0x5fdb
-+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11                                 0x5fdb
-+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                                 0x5fe7
-+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                                 0x5ff3
-+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                                 0x5fff
-+#define mmPLL_MACRO_CNTL_RESERVED0                                              0x1700
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0                                    0x1700
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0                                    0x172a
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0                                    0x1754
-+#define mmPLL_MACRO_CNTL_RESERVED1                                              0x1701
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1                                    0x1701
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1                                    0x172b
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1                                    0x1755
-+#define mmPLL_MACRO_CNTL_RESERVED2                                              0x1702
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2                                    0x1702
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2                                    0x172c
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2                                    0x1756
-+#define mmPLL_MACRO_CNTL_RESERVED3                                              0x1703
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3                                    0x1703
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3                                    0x172d
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3                                    0x1757
-+#define mmPLL_MACRO_CNTL_RESERVED4                                              0x1704
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4                                    0x1704
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4                                    0x172e
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4                                    0x1758
-+#define mmPLL_MACRO_CNTL_RESERVED5                                              0x1705
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5                                    0x1705
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5                                    0x172f
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5                                    0x1759
-+#define mmPLL_MACRO_CNTL_RESERVED6                                              0x1706
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6                                    0x1706
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6                                    0x1730
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6                                    0x175a
-+#define mmPLL_MACRO_CNTL_RESERVED7                                              0x1707
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7                                    0x1707
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7                                    0x1731
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7                                    0x175b
-+#define mmPLL_MACRO_CNTL_RESERVED8                                              0x1708
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8                                    0x1708
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8                                    0x1732
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8                                    0x175c
-+#define mmPLL_MACRO_CNTL_RESERVED9                                              0x1709
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9                                    0x1709
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9                                    0x1733
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9                                    0x175d
-+#define mmPLL_MACRO_CNTL_RESERVED10                                             0x170a
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10                                   0x170a
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10                                   0x1734
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10                                   0x175e
-+#define mmPLL_MACRO_CNTL_RESERVED11                                             0x170b
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11                                   0x170b
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11                                   0x1735
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11                                   0x175f
-+#define mmPLL_MACRO_CNTL_RESERVED12                                             0x170c
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12                                   0x170c
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12                                   0x1736
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12                                   0x1760
-+#define mmPLL_MACRO_CNTL_RESERVED13                                             0x170d
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13                                   0x170d
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13                                   0x1737
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13                                   0x1761
-+#define mmPLL_MACRO_CNTL_RESERVED14                                             0x170e
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14                                   0x170e
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14                                   0x1738
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14                                   0x1762
-+#define mmPLL_MACRO_CNTL_RESERVED15                                             0x170f
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15                                   0x170f
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15                                   0x1739
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15                                   0x1763
-+#define mmPLL_MACRO_CNTL_RESERVED16                                             0x1710
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16                                   0x1710
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16                                   0x173a
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16                                   0x1764
-+#define mmPLL_MACRO_CNTL_RESERVED17                                             0x1711
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17                                   0x1711
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17                                   0x173b
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17                                   0x1765
-+#define mmPLL_MACRO_CNTL_RESERVED18                                             0x1712
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18                                   0x1712
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18                                   0x173c
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18                                   0x1766
-+#define mmPLL_MACRO_CNTL_RESERVED19                                             0x1713
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19                                   0x1713
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19                                   0x173d
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19                                   0x1767
-+#define mmPLL_MACRO_CNTL_RESERVED20                                             0x1714
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20                                   0x1714
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20                                   0x173e
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20                                   0x1768
-+#define mmPLL_MACRO_CNTL_RESERVED21                                             0x1715
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21                                   0x1715
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21                                   0x173f
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21                                   0x1769
-+#define mmPLL_MACRO_CNTL_RESERVED22                                             0x1716
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22                                   0x1716
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22                                   0x1740
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22                                   0x176a
-+#define mmPLL_MACRO_CNTL_RESERVED23                                             0x1717
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23                                   0x1717
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23                                   0x1741
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23                                   0x176b
-+#define mmPLL_MACRO_CNTL_RESERVED24                                             0x1718
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24                                   0x1718
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24                                   0x1742
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24                                   0x176c
-+#define mmPLL_MACRO_CNTL_RESERVED25                                             0x1719
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25                                   0x1719
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25                                   0x1743
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25                                   0x176d
-+#define mmPLL_MACRO_CNTL_RESERVED26                                             0x171a
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26                                   0x171a
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26                                   0x1744
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26                                   0x176e
-+#define mmPLL_MACRO_CNTL_RESERVED27                                             0x171b
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27                                   0x171b
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27                                   0x1745
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27                                   0x176f
-+#define mmPLL_MACRO_CNTL_RESERVED28                                             0x171c
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28                                   0x171c
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28                                   0x1746
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28                                   0x1770
-+#define mmPLL_MACRO_CNTL_RESERVED29                                             0x171d
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29                                   0x171d
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29                                   0x1747
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29                                   0x1771
-+#define mmPLL_MACRO_CNTL_RESERVED30                                             0x171e
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30                                   0x171e
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30                                   0x1748
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30                                   0x1772
-+#define mmPLL_MACRO_CNTL_RESERVED31                                             0x171f
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31                                   0x171f
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31                                   0x1749
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31                                   0x1773
-+#define mmPLL_MACRO_CNTL_RESERVED32                                             0x1720
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32                                   0x1720
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32                                   0x174a
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32                                   0x1774
-+#define mmPLL_MACRO_CNTL_RESERVED33                                             0x1721
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33                                   0x1721
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33                                   0x174b
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33                                   0x1775
-+#define mmPLL_MACRO_CNTL_RESERVED34                                             0x1722
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34                                   0x1722
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34                                   0x174c
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34                                   0x1776
-+#define mmPLL_MACRO_CNTL_RESERVED35                                             0x1723
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35                                   0x1723
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35                                   0x174d
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35                                   0x1777
-+#define mmPLL_MACRO_CNTL_RESERVED36                                             0x1724
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36                                   0x1724
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36                                   0x174e
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36                                   0x1778
-+#define mmPLL_MACRO_CNTL_RESERVED37                                             0x1725
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37                                   0x1725
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37                                   0x174f
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37                                   0x1779
-+#define mmPLL_MACRO_CNTL_RESERVED38                                             0x1726
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38                                   0x1726
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38                                   0x1750
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38                                   0x177a
-+#define mmPLL_MACRO_CNTL_RESERVED39                                             0x1727
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39                                   0x1727
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39                                   0x1751
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39                                   0x177b
-+#define mmPLL_MACRO_CNTL_RESERVED40                                             0x1728
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40                                   0x1728
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40                                   0x1752
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40                                   0x177c
-+#define mmPLL_MACRO_CNTL_RESERVED41                                             0x1729
-+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41                                   0x1729
-+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41                                   0x1753
-+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41                                   0x177d
-+#define mmDENTIST_DISPCLK_CNTL                                                  0x124
-+#define mmDCDEBUG_BUS_CLK1_SEL                                                  0x16c4
-+#define mmDCDEBUG_BUS_CLK2_SEL                                                  0x16c5
-+#define mmDCDEBUG_BUS_CLK3_SEL                                                  0x16c6
-+#define mmDCDEBUG_BUS_CLK4_SEL                                                  0x16c7
-+#define mmDCDEBUG_BUS_CLK5_SEL                                                  0x16c8
-+#define mmDCDEBUG_OUT_PIN_OVERRIDE                                              0x16c9
-+#define mmDCDEBUG_OUT_CNTL                                                      0x16ca
-+#define mmDCDEBUG_OUT_DATA                                                      0x16cb
-+#define mmDMIF_CONTROL                                                          0x2f6
-+#define mmDMIF_STATUS                                                           0x2f7
-+#define mmDMIFV_STATUS                                                          0x2f5
-+#define mmDMIF_HW_DEBUG                                                         0x2f8
-+#define mmDMIF_ARBITRATION_CONTROL                                              0x2f9
-+#define mmPIPE0_ARBITRATION_CONTROL3                                            0x2fa
-+#define mmPIPE1_ARBITRATION_CONTROL3                                            0x2fb
-+#define mmPIPE2_ARBITRATION_CONTROL3                                            0x2fc
-+#define mmPIPE3_ARBITRATION_CONTROL3                                            0x2fd
-+#define mmPIPE4_ARBITRATION_CONTROL3                                            0x2fe
-+#define mmPIPE5_ARBITRATION_CONTROL3                                            0x2ff
-+#define mmPIPE6_ARBITRATION_CONTROL3                                            0x32a
-+#define mmPIPE7_ARBITRATION_CONTROL3                                            0x32b
-+#define mmDMIF_P_VMID                                                           0x300
-+#define mmDMIF_URG_OVERRIDE                                                     0x329
-+#define mmDMIF_TEST_DEBUG_INDEX                                                 0x301
-+#define mmDMIF_TEST_DEBUG_DATA                                                  0x302
-+#define ixDMIF_DEBUG02_CORE0                                                    0x2
-+#define ixDMIF_DEBUG02_CORE1                                                    0xa
-+#define mmDMIF_ADDR_CALC                                                        0x303
-+#define mmDMIF_STATUS2                                                          0x304
-+#define mmPIPE0_MAX_REQUESTS                                                    0x305
-+#define mmPIPE1_MAX_REQUESTS                                                    0x306
-+#define mmPIPE2_MAX_REQUESTS                                                    0x307
-+#define mmPIPE3_MAX_REQUESTS                                                    0x308
-+#define mmPIPE4_MAX_REQUESTS                                                    0x309
-+#define mmPIPE5_MAX_REQUESTS                                                    0x30a
-+#define mmPIPE6_MAX_REQUESTS                                                    0x32c
-+#define mmPIPE7_MAX_REQUESTS                                                    0x32d
-+#define mmDVMM_REG_RD_STATUS                                                    0x32e
-+#define mmDVMM_REG_RD_DATA                                                      0x32f
-+#define mmDVMM_PTE_REQ                                                          0x330
-+#define mmDVMM_CNTL                                                             0x331
-+#define mmDVMM_FAULT_STATUS                                                     0x332
-+#define mmDVMM_FAULT_ADDR                                                       0x333
-+#define mmLOW_POWER_TILING_CONTROL                                              0x30b
-+#define mmMCIF_CONTROL                                                          0x30c
-+#define mmMCIF_WRITE_COMBINE_CONTROL                                            0x30d
-+#define mmMCIF_TEST_DEBUG_INDEX                                                 0x30e
-+#define mmMCIF_TEST_DEBUG_DATA                                                  0x30f
-+#define ixIDDCCIF02_DBG_DCCIF_C                                                 0x9
-+#define ixIDDCCIF04_DBG_DCCIF_E                                                 0xb
-+#define ixIDDCCIF05_DBG_DCCIF_F                                                 0xc
-+#define mmMCIF_VMID                                                             0x310
-+#define mmMCIF_MEM_CONTROL                                                      0x311
-+#define mmCC_DC_PIPE_DIS                                                        0x312
-+#define mmMC_DC_INTERFACE_NACK_STATUS                                           0x313
-+#define mmRBBMIF_TIMEOUT                                                        0x314
-+#define mmRBBMIF_STATUS                                                         0x315
-+#define mmRBBMIF_TIMEOUT_DIS                                                    0x316
-+#define mmRBBMIF_STATUS_FLAG                                                    0x327
-+#define mmDCI_MEM_PWR_STATUS                                                    0x317
-+#define mmDCI_MEM_PWR_STATUS2                                                   0x318
-+#define mmDCI_MEM_PWR_STATUS3                                                   0x33d
-+#define mmDCI_CLK_CNTL                                                          0x319
-+#define mmDCI_CLK_RAMP_CNTL                                                     0x31a
-+#define mmDCI_MEM_PWR_CNTL                                                      0x31b
-+#define mmDCI_MEM_PWR_CNTL2                                                     0x31c
-+#define mmDCI_MEM_PWR_CNTL3                                                     0x31d
-+#define mmDCI_MEM_PWR_CNTL4                                                     0x33b
-+#define mmDVMM_PTE_PGMEM_CONTROL                                                0x335
-+#define mmDVMM_PTE_PGMEM_STATE                                                  0x336
-+#define mmDCI_SOFT_RESET                                                        0x328
-+#define mmDCI_MISC                                                              0x33c
-+#define mmDCI_TEST_DEBUG_INDEX                                                  0x31e
-+#define mmDCI_TEST_DEBUG_DATA                                                   0x31f
-+#define mmDCI_DEBUG_CONFIG                                                      0x320
-+#define mmPIPE0_DMIF_BUFFER_CONTROL                                             0x321
-+#define mmPIPE1_DMIF_BUFFER_CONTROL                                             0x322
-+#define mmPIPE2_DMIF_BUFFER_CONTROL                                             0x323
-+#define mmPIPE3_DMIF_BUFFER_CONTROL                                             0x324
-+#define mmPIPE4_DMIF_BUFFER_CONTROL                                             0x325
-+#define mmPIPE5_DMIF_BUFFER_CONTROL                                             0x326
-+#define mmDC_GENERICA                                                           0x4800
-+#define mmDC_GENERICB                                                           0x4801
-+#define mmDC_PAD_EXTERN_SIG                                                     0x4802
-+#define mmDC_REF_CLK_CNTL                                                       0x4803
-+#define mmDC_GPIO_DEBUG                                                         0x4804
-+#define mmUNIPHYA_LINK_CNTL                                                     0x4805
-+#define mmUNIPHYB_LINK_CNTL                                                     0x4807
-+#define mmUNIPHYC_LINK_CNTL                                                     0x4809
-+#define mmUNIPHYD_LINK_CNTL                                                     0x480b
-+#define mmUNIPHYE_LINK_CNTL                                                     0x480d
-+#define mmUNIPHYF_LINK_CNTL                                                     0x480f
-+#define mmUNIPHYG_LINK_CNTL                                                     0x4811
-+#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                             0x4806
-+#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                             0x4808
-+#define mmUNIPHYC_CHANNEL_XBAR_CNTL                                             0x480a
-+#define mmUNIPHYD_CHANNEL_XBAR_CNTL                                             0x480c
-+#define mmUNIPHYE_CHANNEL_XBAR_CNTL                                             0x480e
-+#define mmUNIPHYF_CHANNEL_XBAR_CNTL                                             0x4810
-+#define mmUNIPHYG_CHANNEL_XBAR_CNTL                                             0x4812
-+#define mmUNIPHYLPA_LINK_CNTL                                                   0x4847
-+#define mmUNIPHYLPB_LINK_CNTL                                                   0x4848
-+#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL                                           0x4849
-+#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL                                           0x484a
-+#define mmUNIPHY_IMPCAL_LINKA                                                   0x4838
-+#define mmUNIPHY_IMPCAL_LINKB                                                   0x4839
-+#define mmUNIPHY_IMPCAL_LINKC                                                   0x483f
-+#define mmUNIPHY_IMPCAL_LINKD                                                   0x4840
-+#define mmUNIPHY_IMPCAL_LINKE                                                   0x4843
-+#define mmUNIPHY_IMPCAL_LINKF                                                   0x4844
-+#define mmUNIPHY_IMPCAL_PERIOD                                                  0x483a
-+#define mmAUXP_IMPCAL                                                           0x483b
-+#define mmAUXN_IMPCAL                                                           0x483c
-+#define mmDCIO_IMPCAL_CNTL                                                      0x483d
-+#define mmUNIPHY_IMPCAL_PSW_AB                                                  0x483e
-+#define mmDCIO_IMPCAL_CNTL_CD                                                   0x4841
-+#define mmUNIPHY_IMPCAL_PSW_CD                                                  0x4842
-+#define mmDCIO_IMPCAL_CNTL_EF                                                   0x4845
-+#define mmUNIPHY_IMPCAL_PSW_EF                                                  0x4846
-+#define mmDCIO_WRCMD_DELAY                                                      0x4816
-+#define mmDC_PINSTRAPS                                                          0x4818
-+#define mmDC_DVODATA_CONFIG                                                     0x481a
-+#define mmLVTMA_PWRSEQ_CNTL                                                     0x481b
-+#define mmLVTMA_PWRSEQ_STATE                                                    0x481c
-+#define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
-+#define mmLVTMA_PWRSEQ_DELAY1                                                   0x481e
-+#define mmLVTMA_PWRSEQ_DELAY2                                                   0x481f
-+#define mmBL_PWM_CNTL                                                           0x4820
-+#define mmBL_PWM_CNTL2                                                          0x4821
-+#define mmBL_PWM_PERIOD_CNTL                                                    0x4822
-+#define mmBL_PWM_GRP1_REG_LOCK                                                  0x4823
-+#define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
-+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                            0x4825
-+#define mmDCIO_GSL0_CNTL                                                        0x4826
-+#define mmDCIO_GSL1_CNTL                                                        0x4827
-+#define mmDCIO_GSL2_CNTL                                                        0x4828
-+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                  0x4829
-+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP                                    0x482a
-+#define mmDC_GPU_TIMER_READ                                                     0x482b
-+#define mmDC_GPU_TIMER_READ_CNTL                                                0x482c
-+#define mmDCIO_CLOCK_CNTL                                                       0x482d
-+#define mmDCIO_DEBUG                                                            0x482f
-+#define mmDCO_DCFE_EXT_VSYNC_CNTL                                               0x4830
-+#define mmDBG_OUT_CNTL                                                          0x4834
-+#define mmDCIO_DEBUG_CONFIG                                                     0x4835
-+#define mmDCIO_SOFT_RESET                                                       0x4836
-+#define mmDCIO_DPHY_SEL                                                         0x4837
-+#define mmDCIO_DPCS_TX_INTERRUPT                                                0x484b
-+#define mmDCIO_DPCS_RX_INTERRUPT                                                0x484c
-+#define mmDCIO_SEMAPHORE0                                                       0x484d
-+#define mmDCIO_SEMAPHORE1                                                       0x484e
-+#define mmDCIO_SEMAPHORE2                                                       0x484f
-+#define mmDCIO_SEMAPHORE3                                                       0x4850
-+#define mmDCIO_SEMAPHORE4                                                       0x4851
-+#define mmDCIO_SEMAPHORE5                                                       0x4852
-+#define mmDCIO_SEMAPHORE6                                                       0x4853
-+#define mmDCIO_SEMAPHORE7                                                       0x4854
-+#define mmDCIO_TEST_DEBUG_INDEX                                                 0x4831
-+#define mmDCIO_TEST_DEBUG_DATA                                                  0x4832
-+#define ixDCIO_DEBUG1                                                           0x1
-+#define ixDCIO_DEBUG2                                                           0x2
-+#define ixDCIO_DEBUG3                                                           0x3
-+#define ixDCIO_DEBUG4                                                           0x4
-+#define ixDCIO_DEBUG5                                                           0x5
-+#define ixDCIO_DEBUG6                                                           0x6
-+#define ixDCIO_DEBUG7                                                           0x7
-+#define ixDCIO_DEBUG8                                                           0x8
-+#define ixDCIO_DEBUG9                                                           0x9
-+#define ixDCIO_DEBUGA                                                           0xa
-+#define ixDCIO_DEBUGB                                                           0xb
-+#define ixDCIO_DEBUGC                                                           0xc
-+#define ixDCIO_DEBUGD                                                           0xd
-+#define ixDCIO_DEBUGE                                                           0xe
-+#define ixDCIO_DEBUGF                                                           0xf
-+#define ixDCIO_DEBUG10                                                          0x10
-+#define ixDCIO_DEBUG11                                                          0x11
-+#define ixDCIO_DEBUG12                                                          0x12
-+#define ixDCIO_DEBUG13                                                          0x13
-+#define ixDCIO_DEBUG14                                                          0x14
-+#define ixDCIO_DEBUG15                                                          0x15
-+#define ixDCIO_DEBUG16                                                          0x16
-+#define ixDCIO_DEBUG17                                                          0x17
-+#define ixDCIO_DEBUG18                                                          0x18
-+#define ixDCIO_DEBUG19                                                          0x19
-+#define ixDCIO_DEBUG1A                                                          0x1a
-+#define ixDCIO_DEBUG1B                                                          0x1b
-+#define ixDCIO_DEBUG1C                                                          0x1c
-+#define ixDCIO_DEBUG1D                                                          0x1d
-+#define ixDCIO_DEBUG1E                                                          0x1e
-+#define ixDCIO_DEBUG1F                                                          0x1f
-+#define ixDCIO_DEBUG20                                                          0x20
-+#define ixDCIO_DEBUG21                                                          0x21
-+#define ixDCIO_DEBUG22                                                          0x22
-+#define ixDCIO_DEBUG23                                                          0x23
-+#define ixDCIO_DEBUG24                                                          0x24
-+#define ixDCIO_DEBUG25                                                          0x25
-+#define ixDCIO_DEBUG26                                                          0x26
-+#define ixDCIO_DEBUG27                                                          0x27
-+#define ixDCIO_DEBUG28                                                          0x28
-+#define ixDCIO_DEBUG_ID                                                         0x0
-+#define mmDC_GPIO_GENERIC_MASK                                                  0x4860
-+#define mmDC_GPIO_GENERIC_A                                                     0x4861
-+#define mmDC_GPIO_GENERIC_EN                                                    0x4862
-+#define mmDC_GPIO_GENERIC_Y                                                     0x4863
-+#define mmDC_GPIO_DDC1_MASK                                                     0x4868
-+#define mmDC_GPIO_DDC1_A                                                        0x4869
-+#define mmDC_GPIO_DDC1_EN                                                       0x486a
-+#define mmDC_GPIO_DDC1_Y                                                        0x486b
-+#define mmDC_GPIO_DDC2_MASK                                                     0x486c
-+#define mmDC_GPIO_DDC2_A                                                        0x486d
-+#define mmDC_GPIO_DDC2_EN                                                       0x486e
-+#define mmDC_GPIO_DDC2_Y                                                        0x486f
-+#define mmDC_GPIO_DDC3_MASK                                                     0x4870
-+#define mmDC_GPIO_DDC3_A                                                        0x4871
-+#define mmDC_GPIO_DDC3_EN                                                       0x4872
-+#define mmDC_GPIO_DDC3_Y                                                        0x4873
-+#define mmDC_GPIO_DDC4_MASK                                                     0x4874
-+#define mmDC_GPIO_DDC4_A                                                        0x4875
-+#define mmDC_GPIO_DDC4_EN                                                       0x4876
-+#define mmDC_GPIO_DDC4_Y                                                        0x4877
-+#define mmDC_GPIO_DDC5_MASK                                                     0x4878
-+#define mmDC_GPIO_DDC5_A                                                        0x4879
-+#define mmDC_GPIO_DDC5_EN                                                       0x487a
-+#define mmDC_GPIO_DDC5_Y                                                        0x487b
-+#define mmDC_GPIO_DDC6_MASK                                                     0x487c
-+#define mmDC_GPIO_DDC6_A                                                        0x487d
-+#define mmDC_GPIO_DDC6_EN                                                       0x487e
-+#define mmDC_GPIO_DDC6_Y                                                        0x487f
-+#define mmDC_GPIO_DDCVGA_MASK                                                   0x4880
-+#define mmDC_GPIO_DDCVGA_A                                                      0x4881
-+#define mmDC_GPIO_DDCVGA_EN                                                     0x4882
-+#define mmDC_GPIO_DDCVGA_Y                                                      0x4883
-+#define mmDC_GPIO_SYNCA_MASK                                                    0x4884
-+#define mmDC_GPIO_SYNCA_A                                                       0x4885
-+#define mmDC_GPIO_SYNCA_EN                                                      0x4886
-+#define mmDC_GPIO_SYNCA_Y                                                       0x4887
-+#define mmDC_GPIO_GENLK_MASK                                                    0x4888
-+#define mmDC_GPIO_GENLK_A                                                       0x4889
-+#define mmDC_GPIO_GENLK_EN                                                      0x488a
-+#define mmDC_GPIO_GENLK_Y                                                       0x488b
-+#define mmDC_GPIO_HPD_MASK                                                      0x488c
-+#define mmDC_GPIO_HPD_A                                                         0x488d
-+#define mmDC_GPIO_HPD_EN                                                        0x488e
-+#define mmDC_GPIO_HPD_Y                                                         0x488f
-+#define mmDC_GPIO_PWRSEQ_MASK                                                   0x4890
-+#define mmDC_GPIO_PWRSEQ_A                                                      0x4891
-+#define mmDC_GPIO_PWRSEQ_EN                                                     0x4892
-+#define mmDC_GPIO_PWRSEQ_Y                                                      0x4893
-+#define mmDC_GPIO_PAD_STRENGTH_1                                                0x4894
-+#define mmDC_GPIO_PAD_STRENGTH_2                                                0x4895
-+#define mmPHY_AUX_CNTL                                                          0x4897
-+#define mmDC_GPIO_I2CPAD_A                                                      0x4899
-+#define mmDC_GPIO_I2CPAD_EN                                                     0x489a
-+#define mmDC_GPIO_I2CPAD_Y                                                      0x489b
-+#define mmDC_GPIO_I2CPAD_STRENGTH                                               0x489c
-+#define mmDVO_VREF_CONTROL                                                      0x489e
-+#define mmDVO_SKEW_ADJUST                                                       0x489f
-+#define mmDC_GPIO_RECEIVER_EN0                                                  0x48a0
-+#define mmDC_GPIO_RECEIVER_EN1                                                  0x48a1
-+#define mmDC_GPIO_I2S_SPDIF_MASK                                                0x48a8
-+#define mmDC_GPIO_I2S_SPDIF_A                                                   0x48a9
-+#define mmDC_GPIO_I2S_SPDIF_EN                                                  0x48aa
-+#define mmDC_GPIO_I2S_SPDIF_Y                                                   0x48ab
-+#define mmDC_GPIO_I2S_SPDIF_STRENGTH                                            0x48ac
-+#define mmDC_GPIO_TX12_EN                                                       0x48ad
-+#define mmDC_GPIO_AUX_CTRL_0                                                    0x48ae
-+#define mmDC_GPIO_AUX_CTRL_1                                                    0x48af
-+#define mmDC_GPIO_AUX_CTRL_2                                                    0x48b0
-+#define mmDC_GPIO_HPD_CTRL_0                                                    0x48b1
-+#define mmDC_GPIO_HPD_CTRL_1                                                    0x48b2
-+#define mmDAC_MACRO_CNTL_RESERVED0                                              0x48b8
-+#define mmDAC_MACRO_CNTL_RESERVED1                                              0x48b9
-+#define mmDAC_MACRO_CNTL_RESERVED2                                              0x48ba
-+#define mmDAC_MACRO_CNTL_RESERVED3                                              0x48bb
-+#define mmUNIPHY_MACRO_CNTL_RESERVED0                                           0x48c0
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                              0x48c0
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                              0x4960
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                              0x9a00
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                              0x9aa0
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                              0x9b40
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0                              0x9be0
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0                              0x9c80
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0                              0x9d20
-+#define mmUNIPHY_MACRO_CNTL_RESERVED1                                           0x48c1
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                              0x48c1
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                              0x4961
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                              0x9a01
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                              0x9aa1
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                              0x9b41
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1                              0x9be1
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1                              0x9c81
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1                              0x9d21
-+#define mmUNIPHY_MACRO_CNTL_RESERVED2                                           0x48c2
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                              0x48c2
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                              0x4962
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                              0x9a02
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                              0x9aa2
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                              0x9b42
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2                              0x9be2
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2                              0x9c82
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2                              0x9d22
-+#define mmUNIPHY_MACRO_CNTL_RESERVED3                                           0x48c3
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                              0x48c3
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                              0x4963
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                              0x9a03
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                              0x9aa3
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                              0x9b43
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3                              0x9be3
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3                              0x9c83
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3                              0x9d23
-+#define mmUNIPHY_MACRO_CNTL_RESERVED4                                           0x48c4
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                              0x48c4
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                              0x4964
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                              0x9a04
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                              0x9aa4
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                              0x9b44
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4                              0x9be4
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4                              0x9c84
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4                              0x9d24
-+#define mmUNIPHY_MACRO_CNTL_RESERVED5                                           0x48c5
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                              0x48c5
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                              0x4965
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                              0x9a05
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                              0x9aa5
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                              0x9b45
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5                              0x9be5
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5                              0x9c85
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5                              0x9d25
-+#define mmUNIPHY_MACRO_CNTL_RESERVED6                                           0x48c6
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                              0x48c6
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                              0x4966
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                              0x9a06
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                              0x9aa6
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                              0x9b46
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6                              0x9be6
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6                              0x9c86
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6                              0x9d26
-+#define mmUNIPHY_MACRO_CNTL_RESERVED7                                           0x48c7
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                              0x48c7
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                              0x4967
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                              0x9a07
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                              0x9aa7
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                              0x9b47
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7                              0x9be7
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7                              0x9c87
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7                              0x9d27
-+#define mmUNIPHY_MACRO_CNTL_RESERVED8                                           0x48c8
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                              0x48c8
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                              0x4968
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                              0x9a08
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                              0x9aa8
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                              0x9b48
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8                              0x9be8
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8                              0x9c88
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8                              0x9d28
-+#define mmUNIPHY_MACRO_CNTL_RESERVED9                                           0x48c9
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                              0x48c9
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                              0x4969
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                              0x9a09
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                              0x9aa9
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                              0x9b49
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9                              0x9be9
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9                              0x9c89
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9                              0x9d29
-+#define mmUNIPHY_MACRO_CNTL_RESERVED10                                          0x48ca
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                             0x48ca
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                             0x496a
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                             0x9a0a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                             0x9aaa
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                             0x9b4a
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10                             0x9bea
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10                             0x9c8a
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10                             0x9d2a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED11                                          0x48cb
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                             0x48cb
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                             0x496b
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                             0x9a0b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                             0x9aab
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                             0x9b4b
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11                             0x9beb
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11                             0x9c8b
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11                             0x9d2b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED12                                          0x48cc
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                             0x48cc
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                             0x496c
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                             0x9a0c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                             0x9aac
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                             0x9b4c
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12                             0x9bec
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12                             0x9c8c
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12                             0x9d2c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED13                                          0x48cd
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                             0x48cd
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                             0x496d
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                             0x9a0d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                             0x9aad
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                             0x9b4d
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13                             0x9bed
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13                             0x9c8d
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13                             0x9d2d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED14                                          0x48ce
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                             0x48ce
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                             0x496e
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                             0x9a0e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                             0x9aae
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                             0x9b4e
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14                             0x9bee
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14                             0x9c8e
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14                             0x9d2e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED15                                          0x48cf
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                             0x48cf
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                             0x496f
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                             0x9a0f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                             0x9aaf
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                             0x9b4f
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15                             0x9bef
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15                             0x9c8f
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15                             0x9d2f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED16                                          0x48d0
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                             0x48d0
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                             0x4970
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                             0x9a10
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                             0x9ab0
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                             0x9b50
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16                             0x9bf0
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16                             0x9c90
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16                             0x9d30
-+#define mmUNIPHY_MACRO_CNTL_RESERVED17                                          0x48d1
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                             0x48d1
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                             0x4971
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                             0x9a11
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                             0x9ab1
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                             0x9b51
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17                             0x9bf1
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17                             0x9c91
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17                             0x9d31
-+#define mmUNIPHY_MACRO_CNTL_RESERVED18                                          0x48d2
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                             0x48d2
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                             0x4972
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                             0x9a12
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                             0x9ab2
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                             0x9b52
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18                             0x9bf2
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18                             0x9c92
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18                             0x9d32
-+#define mmUNIPHY_MACRO_CNTL_RESERVED19                                          0x48d3
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                             0x48d3
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                             0x4973
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                             0x9a13
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                             0x9ab3
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                             0x9b53
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19                             0x9bf3
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19                             0x9c93
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19                             0x9d33
-+#define mmUNIPHY_MACRO_CNTL_RESERVED20                                          0x48d4
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                             0x48d4
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                             0x4974
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                             0x9a14
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                             0x9ab4
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                             0x9b54
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20                             0x9bf4
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20                             0x9c94
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20                             0x9d34
-+#define mmUNIPHY_MACRO_CNTL_RESERVED21                                          0x48d5
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                             0x48d5
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                             0x4975
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                             0x9a15
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                             0x9ab5
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                             0x9b55
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21                             0x9bf5
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21                             0x9c95
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21                             0x9d35
-+#define mmUNIPHY_MACRO_CNTL_RESERVED22                                          0x48d6
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                             0x48d6
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                             0x4976
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                             0x9a16
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                             0x9ab6
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                             0x9b56
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22                             0x9bf6
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22                             0x9c96
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22                             0x9d36
-+#define mmUNIPHY_MACRO_CNTL_RESERVED23                                          0x48d7
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                             0x48d7
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                             0x4977
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                             0x9a17
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                             0x9ab7
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                             0x9b57
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23                             0x9bf7
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23                             0x9c97
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23                             0x9d37
-+#define mmUNIPHY_MACRO_CNTL_RESERVED24                                          0x48d8
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                             0x48d8
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                             0x4978
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                             0x9a18
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                             0x9ab8
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                             0x9b58
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24                             0x9bf8
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24                             0x9c98
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24                             0x9d38
-+#define mmUNIPHY_MACRO_CNTL_RESERVED25                                          0x48d9
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                             0x48d9
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                             0x4979
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                             0x9a19
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                             0x9ab9
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                             0x9b59
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25                             0x9bf9
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25                             0x9c99
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25                             0x9d39
-+#define mmUNIPHY_MACRO_CNTL_RESERVED26                                          0x48da
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                             0x48da
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                             0x497a
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                             0x9a1a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                             0x9aba
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                             0x9b5a
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26                             0x9bfa
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26                             0x9c9a
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26                             0x9d3a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED27                                          0x48db
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                             0x48db
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                             0x497b
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                             0x9a1b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                             0x9abb
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                             0x9b5b
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27                             0x9bfb
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27                             0x9c9b
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27                             0x9d3b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED28                                          0x48dc
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                             0x48dc
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                             0x497c
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                             0x9a1c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                             0x9abc
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                             0x9b5c
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28                             0x9bfc
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28                             0x9c9c
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28                             0x9d3c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED29                                          0x48dd
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                             0x48dd
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                             0x497d
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                             0x9a1d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                             0x9abd
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                             0x9b5d
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29                             0x9bfd
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29                             0x9c9d
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29                             0x9d3d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED30                                          0x48de
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                             0x48de
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                             0x497e
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                             0x9a1e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                             0x9abe
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                             0x9b5e
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30                             0x9bfe
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30                             0x9c9e
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30                             0x9d3e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED31                                          0x48df
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                             0x48df
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                             0x497f
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                             0x9a1f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                             0x9abf
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                             0x9b5f
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31                             0x9bff
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31                             0x9c9f
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31                             0x9d3f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED32                                          0x48e0
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                             0x48e0
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                             0x4980
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                             0x9a20
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                             0x9ac0
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                             0x9b60
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32                             0x9c00
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32                             0x9ca0
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED32                             0x9d40
-+#define mmUNIPHY_MACRO_CNTL_RESERVED33                                          0x48e1
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                             0x48e1
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                             0x4981
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                             0x9a21
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                             0x9ac1
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                             0x9b61
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33                             0x9c01
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33                             0x9ca1
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED33                             0x9d41
-+#define mmUNIPHY_MACRO_CNTL_RESERVED34                                          0x48e2
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                             0x48e2
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                             0x4982
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                             0x9a22
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                             0x9ac2
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                             0x9b62
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34                             0x9c02
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34                             0x9ca2
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED34                             0x9d42
-+#define mmUNIPHY_MACRO_CNTL_RESERVED35                                          0x48e3
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                             0x48e3
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                             0x4983
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                             0x9a23
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                             0x9ac3
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                             0x9b63
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35                             0x9c03
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35                             0x9ca3
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED35                             0x9d43
-+#define mmUNIPHY_MACRO_CNTL_RESERVED36                                          0x48e4
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                             0x48e4
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                             0x4984
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                             0x9a24
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                             0x9ac4
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                             0x9b64
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36                             0x9c04
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36                             0x9ca4
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED36                             0x9d44
-+#define mmUNIPHY_MACRO_CNTL_RESERVED37                                          0x48e5
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                             0x48e5
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                             0x4985
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                             0x9a25
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                             0x9ac5
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                             0x9b65
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37                             0x9c05
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37                             0x9ca5
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED37                             0x9d45
-+#define mmUNIPHY_MACRO_CNTL_RESERVED38                                          0x48e6
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                             0x48e6
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                             0x4986
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                             0x9a26
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                             0x9ac6
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                             0x9b66
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38                             0x9c06
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38                             0x9ca6
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED38                             0x9d46
-+#define mmUNIPHY_MACRO_CNTL_RESERVED39                                          0x48e7
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                             0x48e7
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                             0x4987
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                             0x9a27
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                             0x9ac7
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                             0x9b67
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39                             0x9c07
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39                             0x9ca7
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED39                             0x9d47
-+#define mmUNIPHY_MACRO_CNTL_RESERVED40                                          0x48e8
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                             0x48e8
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                             0x4988
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                             0x9a28
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                             0x9ac8
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                             0x9b68
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40                             0x9c08
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40                             0x9ca8
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED40                             0x9d48
-+#define mmUNIPHY_MACRO_CNTL_RESERVED41                                          0x48e9
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                             0x48e9
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                             0x4989
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                             0x9a29
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                             0x9ac9
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                             0x9b69
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41                             0x9c09
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41                             0x9ca9
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED41                             0x9d49
-+#define mmUNIPHY_MACRO_CNTL_RESERVED42                                          0x48ea
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                             0x48ea
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                             0x498a
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                             0x9a2a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                             0x9aca
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                             0x9b6a
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42                             0x9c0a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42                             0x9caa
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED42                             0x9d4a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED43                                          0x48eb
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                             0x48eb
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                             0x498b
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                             0x9a2b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                             0x9acb
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                             0x9b6b
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43                             0x9c0b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43                             0x9cab
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED43                             0x9d4b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED44                                          0x48ec
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                             0x48ec
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                             0x498c
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                             0x9a2c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                             0x9acc
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                             0x9b6c
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44                             0x9c0c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44                             0x9cac
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED44                             0x9d4c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED45                                          0x48ed
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                             0x48ed
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                             0x498d
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                             0x9a2d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                             0x9acd
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                             0x9b6d
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45                             0x9c0d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45                             0x9cad
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED45                             0x9d4d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED46                                          0x48ee
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                             0x48ee
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                             0x498e
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                             0x9a2e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                             0x9ace
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                             0x9b6e
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46                             0x9c0e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46                             0x9cae
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED46                             0x9d4e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED47                                          0x48ef
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                             0x48ef
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                             0x498f
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                             0x9a2f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                             0x9acf
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                             0x9b6f
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47                             0x9c0f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47                             0x9caf
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED47                             0x9d4f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED48                                          0x48f0
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                             0x48f0
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                             0x4990
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                             0x9a30
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                             0x9ad0
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                             0x9b70
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48                             0x9c10
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48                             0x9cb0
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED48                             0x9d50
-+#define mmUNIPHY_MACRO_CNTL_RESERVED49                                          0x48f1
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                             0x48f1
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                             0x4991
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                             0x9a31
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                             0x9ad1
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                             0x9b71
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49                             0x9c11
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49                             0x9cb1
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED49                             0x9d51
-+#define mmUNIPHY_MACRO_CNTL_RESERVED50                                          0x48f2
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                             0x48f2
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                             0x4992
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                             0x9a32
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                             0x9ad2
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                             0x9b72
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50                             0x9c12
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50                             0x9cb2
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED50                             0x9d52
-+#define mmUNIPHY_MACRO_CNTL_RESERVED51                                          0x48f3
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                             0x48f3
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                             0x4993
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                             0x9a33
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                             0x9ad3
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                             0x9b73
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51                             0x9c13
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51                             0x9cb3
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED51                             0x9d53
-+#define mmUNIPHY_MACRO_CNTL_RESERVED52                                          0x48f4
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                             0x48f4
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                             0x4994
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                             0x9a34
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                             0x9ad4
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                             0x9b74
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52                             0x9c14
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52                             0x9cb4
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED52                             0x9d54
-+#define mmUNIPHY_MACRO_CNTL_RESERVED53                                          0x48f5
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                             0x48f5
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                             0x4995
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                             0x9a35
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                             0x9ad5
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                             0x9b75
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53                             0x9c15
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53                             0x9cb5
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED53                             0x9d55
-+#define mmUNIPHY_MACRO_CNTL_RESERVED54                                          0x48f6
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                             0x48f6
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                             0x4996
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                             0x9a36
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                             0x9ad6
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                             0x9b76
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54                             0x9c16
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54                             0x9cb6
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED54                             0x9d56
-+#define mmUNIPHY_MACRO_CNTL_RESERVED55                                          0x48f7
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                             0x48f7
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                             0x4997
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                             0x9a37
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                             0x9ad7
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                             0x9b77
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55                             0x9c17
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55                             0x9cb7
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED55                             0x9d57
-+#define mmUNIPHY_MACRO_CNTL_RESERVED56                                          0x48f8
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                             0x48f8
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                             0x4998
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                             0x9a38
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                             0x9ad8
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                             0x9b78
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56                             0x9c18
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56                             0x9cb8
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED56                             0x9d58
-+#define mmUNIPHY_MACRO_CNTL_RESERVED57                                          0x48f9
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                             0x48f9
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                             0x4999
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                             0x9a39
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                             0x9ad9
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                             0x9b79
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57                             0x9c19
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57                             0x9cb9
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED57                             0x9d59
-+#define mmUNIPHY_MACRO_CNTL_RESERVED58                                          0x48fa
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58                             0x48fa
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58                             0x499a
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58                             0x9a3a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58                             0x9ada
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58                             0x9b7a
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58                             0x9c1a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58                             0x9cba
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED58                             0x9d5a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED59                                          0x48fb
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59                             0x48fb
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59                             0x499b
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59                             0x9a3b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59                             0x9adb
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59                             0x9b7b
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59                             0x9c1b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59                             0x9cbb
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED59                             0x9d5b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED60                                          0x48fc
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60                             0x48fc
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60                             0x499c
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60                             0x9a3c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60                             0x9adc
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60                             0x9b7c
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60                             0x9c1c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60                             0x9cbc
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED60                             0x9d5c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED61                                          0x48fd
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61                             0x48fd
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61                             0x499d
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61                             0x9a3d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61                             0x9add
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61                             0x9b7d
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61                             0x9c1d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61                             0x9cbd
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED61                             0x9d5d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED62                                          0x48fe
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62                             0x48fe
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62                             0x499e
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62                             0x9a3e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62                             0x9ade
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62                             0x9b7e
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62                             0x9c1e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62                             0x9cbe
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED62                             0x9d5e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED63                                          0x48ff
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63                             0x48ff
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63                             0x499f
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63                             0x9a3f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63                             0x9adf
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63                             0x9b7f
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63                             0x9c1f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63                             0x9cbf
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED63                             0x9d5f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED64                                          0x4900
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64                             0x4900
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64                             0x49a0
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64                             0x9a40
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64                             0x9ae0
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64                             0x9b80
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64                             0x9c20
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64                             0x9cc0
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED64                             0x9d60
-+#define mmUNIPHY_MACRO_CNTL_RESERVED65                                          0x4901
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65                             0x4901
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65                             0x49a1
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65                             0x9a41
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65                             0x9ae1
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65                             0x9b81
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65                             0x9c21
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65                             0x9cc1
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED65                             0x9d61
-+#define mmUNIPHY_MACRO_CNTL_RESERVED66                                          0x4902
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66                             0x4902
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66                             0x49a2
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66                             0x9a42
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66                             0x9ae2
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66                             0x9b82
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66                             0x9c22
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66                             0x9cc2
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED66                             0x9d62
-+#define mmUNIPHY_MACRO_CNTL_RESERVED67                                          0x4903
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67                             0x4903
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67                             0x49a3
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67                             0x9a43
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67                             0x9ae3
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67                             0x9b83
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67                             0x9c23
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67                             0x9cc3
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED67                             0x9d63
-+#define mmUNIPHY_MACRO_CNTL_RESERVED68                                          0x4904
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68                             0x4904
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68                             0x49a4
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68                             0x9a44
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68                             0x9ae4
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68                             0x9b84
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68                             0x9c24
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68                             0x9cc4
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED68                             0x9d64
-+#define mmUNIPHY_MACRO_CNTL_RESERVED69                                          0x4905
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69                             0x4905
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69                             0x49a5
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69                             0x9a45
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69                             0x9ae5
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69                             0x9b85
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69                             0x9c25
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69                             0x9cc5
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED69                             0x9d65
-+#define mmUNIPHY_MACRO_CNTL_RESERVED70                                          0x4906
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70                             0x4906
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70                             0x49a6
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70                             0x9a46
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70                             0x9ae6
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70                             0x9b86
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70                             0x9c26
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70                             0x9cc6
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED70                             0x9d66
-+#define mmUNIPHY_MACRO_CNTL_RESERVED71                                          0x4907
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71                             0x4907
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71                             0x49a7
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71                             0x9a47
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71                             0x9ae7
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71                             0x9b87
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71                             0x9c27
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71                             0x9cc7
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED71                             0x9d67
-+#define mmUNIPHY_MACRO_CNTL_RESERVED72                                          0x4908
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72                             0x4908
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72                             0x49a8
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72                             0x9a48
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72                             0x9ae8
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72                             0x9b88
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72                             0x9c28
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72                             0x9cc8
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED72                             0x9d68
-+#define mmUNIPHY_MACRO_CNTL_RESERVED73                                          0x4909
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73                             0x4909
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73                             0x49a9
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73                             0x9a49
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73                             0x9ae9
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73                             0x9b89
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73                             0x9c29
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73                             0x9cc9
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED73                             0x9d69
-+#define mmUNIPHY_MACRO_CNTL_RESERVED74                                          0x490a
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74                             0x490a
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74                             0x49aa
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74                             0x9a4a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74                             0x9aea
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74                             0x9b8a
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74                             0x9c2a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74                             0x9cca
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED74                             0x9d6a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED75                                          0x490b
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75                             0x490b
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75                             0x49ab
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75                             0x9a4b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75                             0x9aeb
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75                             0x9b8b
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75                             0x9c2b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75                             0x9ccb
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED75                             0x9d6b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED76                                          0x490c
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76                             0x490c
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76                             0x49ac
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76                             0x9a4c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76                             0x9aec
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76                             0x9b8c
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76                             0x9c2c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76                             0x9ccc
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED76                             0x9d6c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED77                                          0x490d
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77                             0x490d
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77                             0x49ad
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77                             0x9a4d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77                             0x9aed
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77                             0x9b8d
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77                             0x9c2d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77                             0x9ccd
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED77                             0x9d6d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED78                                          0x490e
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78                             0x490e
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78                             0x49ae
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78                             0x9a4e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78                             0x9aee
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78                             0x9b8e
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78                             0x9c2e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78                             0x9cce
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED78                             0x9d6e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED79                                          0x490f
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79                             0x490f
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79                             0x49af
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79                             0x9a4f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79                             0x9aef
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79                             0x9b8f
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79                             0x9c2f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79                             0x9ccf
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED79                             0x9d6f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED80                                          0x4910
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80                             0x4910
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80                             0x49b0
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80                             0x9a50
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80                             0x9af0
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80                             0x9b90
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80                             0x9c30
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80                             0x9cd0
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED80                             0x9d70
-+#define mmUNIPHY_MACRO_CNTL_RESERVED81                                          0x4911
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81                             0x4911
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81                             0x49b1
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81                             0x9a51
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81                             0x9af1
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81                             0x9b91
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81                             0x9c31
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81                             0x9cd1
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED81                             0x9d71
-+#define mmUNIPHY_MACRO_CNTL_RESERVED82                                          0x4912
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82                             0x4912
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82                             0x49b2
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82                             0x9a52
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82                             0x9af2
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82                             0x9b92
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82                             0x9c32
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82                             0x9cd2
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED82                             0x9d72
-+#define mmUNIPHY_MACRO_CNTL_RESERVED83                                          0x4913
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83                             0x4913
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83                             0x49b3
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83                             0x9a53
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83                             0x9af3
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83                             0x9b93
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83                             0x9c33
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83                             0x9cd3
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED83                             0x9d73
-+#define mmUNIPHY_MACRO_CNTL_RESERVED84                                          0x4914
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84                             0x4914
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84                             0x49b4
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84                             0x9a54
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84                             0x9af4
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84                             0x9b94
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84                             0x9c34
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84                             0x9cd4
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED84                             0x9d74
-+#define mmUNIPHY_MACRO_CNTL_RESERVED85                                          0x4915
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85                             0x4915
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85                             0x49b5
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85                             0x9a55
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85                             0x9af5
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85                             0x9b95
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85                             0x9c35
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85                             0x9cd5
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED85                             0x9d75
-+#define mmUNIPHY_MACRO_CNTL_RESERVED86                                          0x4916
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86                             0x4916
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86                             0x49b6
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86                             0x9a56
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86                             0x9af6
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86                             0x9b96
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86                             0x9c36
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86                             0x9cd6
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED86                             0x9d76
-+#define mmUNIPHY_MACRO_CNTL_RESERVED87                                          0x4917
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87                             0x4917
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87                             0x49b7
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87                             0x9a57
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87                             0x9af7
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87                             0x9b97
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87                             0x9c37
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87                             0x9cd7
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED87                             0x9d77
-+#define mmUNIPHY_MACRO_CNTL_RESERVED88                                          0x4918
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88                             0x4918
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88                             0x49b8
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88                             0x9a58
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88                             0x9af8
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88                             0x9b98
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88                             0x9c38
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88                             0x9cd8
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED88                             0x9d78
-+#define mmUNIPHY_MACRO_CNTL_RESERVED89                                          0x4919
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89                             0x4919
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89                             0x49b9
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89                             0x9a59
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89                             0x9af9
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89                             0x9b99
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89                             0x9c39
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89                             0x9cd9
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED89                             0x9d79
-+#define mmUNIPHY_MACRO_CNTL_RESERVED90                                          0x491a
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90                             0x491a
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90                             0x49ba
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90                             0x9a5a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90                             0x9afa
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90                             0x9b9a
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90                             0x9c3a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90                             0x9cda
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED90                             0x9d7a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED91                                          0x491b
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91                             0x491b
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91                             0x49bb
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91                             0x9a5b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91                             0x9afb
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91                             0x9b9b
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91                             0x9c3b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91                             0x9cdb
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED91                             0x9d7b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED92                                          0x491c
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92                             0x491c
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92                             0x49bc
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92                             0x9a5c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92                             0x9afc
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92                             0x9b9c
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92                             0x9c3c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92                             0x9cdc
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED92                             0x9d7c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED93                                          0x491d
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93                             0x491d
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93                             0x49bd
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93                             0x9a5d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93                             0x9afd
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93                             0x9b9d
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93                             0x9c3d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93                             0x9cdd
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED93                             0x9d7d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED94                                          0x491e
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94                             0x491e
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94                             0x49be
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94                             0x9a5e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94                             0x9afe
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94                             0x9b9e
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94                             0x9c3e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94                             0x9cde
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED94                             0x9d7e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED95                                          0x491f
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95                             0x491f
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95                             0x49bf
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95                             0x9a5f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95                             0x9aff
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95                             0x9b9f
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95                             0x9c3f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95                             0x9cdf
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED95                             0x9d7f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED96                                          0x4920
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96                             0x4920
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96                             0x49c0
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96                             0x9a60
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96                             0x9b00
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96                             0x9ba0
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96                             0x9c40
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96                             0x9ce0
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED96                             0x9d80
-+#define mmUNIPHY_MACRO_CNTL_RESERVED97                                          0x4921
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97                             0x4921
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97                             0x49c1
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97                             0x9a61
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97                             0x9b01
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97                             0x9ba1
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97                             0x9c41
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97                             0x9ce1
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED97                             0x9d81
-+#define mmUNIPHY_MACRO_CNTL_RESERVED98                                          0x4922
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98                             0x4922
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98                             0x49c2
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98                             0x9a62
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98                             0x9b02
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98                             0x9ba2
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98                             0x9c42
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98                             0x9ce2
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED98                             0x9d82
-+#define mmUNIPHY_MACRO_CNTL_RESERVED99                                          0x4923
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99                             0x4923
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99                             0x49c3
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99                             0x9a63
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99                             0x9b03
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99                             0x9ba3
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99                             0x9c43
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99                             0x9ce3
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED99                             0x9d83
-+#define mmUNIPHY_MACRO_CNTL_RESERVED100                                         0x4924
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100                            0x4924
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100                            0x49c4
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100                            0x9a64
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100                            0x9b04
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100                            0x9ba4
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100                            0x9c44
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100                            0x9ce4
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED100                            0x9d84
-+#define mmUNIPHY_MACRO_CNTL_RESERVED101                                         0x4925
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101                            0x4925
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101                            0x49c5
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101                            0x9a65
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101                            0x9b05
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101                            0x9ba5
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101                            0x9c45
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101                            0x9ce5
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED101                            0x9d85
-+#define mmUNIPHY_MACRO_CNTL_RESERVED102                                         0x4926
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102                            0x4926
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102                            0x49c6
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102                            0x9a66
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102                            0x9b06
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102                            0x9ba6
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102                            0x9c46
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102                            0x9ce6
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED102                            0x9d86
-+#define mmUNIPHY_MACRO_CNTL_RESERVED103                                         0x4927
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103                            0x4927
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103                            0x49c7
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103                            0x9a67
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103                            0x9b07
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103                            0x9ba7
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103                            0x9c47
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103                            0x9ce7
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED103                            0x9d87
-+#define mmUNIPHY_MACRO_CNTL_RESERVED104                                         0x4928
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104                            0x4928
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104                            0x49c8
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104                            0x9a68
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104                            0x9b08
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104                            0x9ba8
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104                            0x9c48
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104                            0x9ce8
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED104                            0x9d88
-+#define mmUNIPHY_MACRO_CNTL_RESERVED105                                         0x4929
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105                            0x4929
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105                            0x49c9
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105                            0x9a69
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105                            0x9b09
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105                            0x9ba9
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105                            0x9c49
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105                            0x9ce9
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED105                            0x9d89
-+#define mmUNIPHY_MACRO_CNTL_RESERVED106                                         0x492a
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106                            0x492a
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106                            0x49ca
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106                            0x9a6a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106                            0x9b0a
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106                            0x9baa
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106                            0x9c4a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106                            0x9cea
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED106                            0x9d8a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED107                                         0x492b
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107                            0x492b
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107                            0x49cb
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107                            0x9a6b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107                            0x9b0b
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107                            0x9bab
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107                            0x9c4b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107                            0x9ceb
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED107                            0x9d8b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED108                                         0x492c
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108                            0x492c
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108                            0x49cc
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108                            0x9a6c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108                            0x9b0c
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108                            0x9bac
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108                            0x9c4c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108                            0x9cec
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED108                            0x9d8c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED109                                         0x492d
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109                            0x492d
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109                            0x49cd
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109                            0x9a6d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109                            0x9b0d
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109                            0x9bad
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109                            0x9c4d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109                            0x9ced
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED109                            0x9d8d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED110                                         0x492e
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110                            0x492e
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110                            0x49ce
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110                            0x9a6e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110                            0x9b0e
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110                            0x9bae
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110                            0x9c4e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110                            0x9cee
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED110                            0x9d8e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED111                                         0x492f
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111                            0x492f
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111                            0x49cf
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111                            0x9a6f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111                            0x9b0f
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111                            0x9baf
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111                            0x9c4f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111                            0x9cef
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED111                            0x9d8f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED112                                         0x4930
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112                            0x4930
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112                            0x49d0
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112                            0x9a70
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112                            0x9b10
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112                            0x9bb0
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112                            0x9c50
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112                            0x9cf0
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED112                            0x9d90
-+#define mmUNIPHY_MACRO_CNTL_RESERVED113                                         0x4931
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113                            0x4931
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113                            0x49d1
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113                            0x9a71
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113                            0x9b11
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113                            0x9bb1
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113                            0x9c51
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113                            0x9cf1
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED113                            0x9d91
-+#define mmUNIPHY_MACRO_CNTL_RESERVED114                                         0x4932
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114                            0x4932
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114                            0x49d2
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114                            0x9a72
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114                            0x9b12
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114                            0x9bb2
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114                            0x9c52
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114                            0x9cf2
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED114                            0x9d92
-+#define mmUNIPHY_MACRO_CNTL_RESERVED115                                         0x4933
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115                            0x4933
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115                            0x49d3
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115                            0x9a73
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115                            0x9b13
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115                            0x9bb3
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115                            0x9c53
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115                            0x9cf3
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED115                            0x9d93
-+#define mmUNIPHY_MACRO_CNTL_RESERVED116                                         0x4934
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116                            0x4934
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116                            0x49d4
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116                            0x9a74
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116                            0x9b14
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116                            0x9bb4
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116                            0x9c54
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116                            0x9cf4
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED116                            0x9d94
-+#define mmUNIPHY_MACRO_CNTL_RESERVED117                                         0x4935
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117                            0x4935
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117                            0x49d5
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117                            0x9a75
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117                            0x9b15
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117                            0x9bb5
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117                            0x9c55
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117                            0x9cf5
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED117                            0x9d95
-+#define mmUNIPHY_MACRO_CNTL_RESERVED118                                         0x4936
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118                            0x4936
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118                            0x49d6
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118                            0x9a76
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118                            0x9b16
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118                            0x9bb6
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118                            0x9c56
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118                            0x9cf6
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED118                            0x9d96
-+#define mmUNIPHY_MACRO_CNTL_RESERVED119                                         0x4937
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119                            0x4937
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119                            0x49d7
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119                            0x9a77
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119                            0x9b17
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119                            0x9bb7
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119                            0x9c57
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119                            0x9cf7
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED119                            0x9d97
-+#define mmUNIPHY_MACRO_CNTL_RESERVED120                                         0x4938
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120                            0x4938
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120                            0x49d8
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120                            0x9a78
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120                            0x9b18
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120                            0x9bb8
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120                            0x9c58
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120                            0x9cf8
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED120                            0x9d98
-+#define mmUNIPHY_MACRO_CNTL_RESERVED121                                         0x4939
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121                            0x4939
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121                            0x49d9
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121                            0x9a79
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121                            0x9b19
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121                            0x9bb9
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121                            0x9c59
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121                            0x9cf9
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED121                            0x9d99
-+#define mmUNIPHY_MACRO_CNTL_RESERVED122                                         0x493a
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122                            0x493a
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122                            0x49da
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122                            0x9a7a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122                            0x9b1a
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122                            0x9bba
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122                            0x9c5a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122                            0x9cfa
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED122                            0x9d9a
-+#define mmUNIPHY_MACRO_CNTL_RESERVED123                                         0x493b
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123                            0x493b
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123                            0x49db
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123                            0x9a7b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123                            0x9b1b
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123                            0x9bbb
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123                            0x9c5b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123                            0x9cfb
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED123                            0x9d9b
-+#define mmUNIPHY_MACRO_CNTL_RESERVED124                                         0x493c
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124                            0x493c
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124                            0x49dc
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124                            0x9a7c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124                            0x9b1c
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124                            0x9bbc
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124                            0x9c5c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124                            0x9cfc
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED124                            0x9d9c
-+#define mmUNIPHY_MACRO_CNTL_RESERVED125                                         0x493d
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125                            0x493d
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125                            0x49dd
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125                            0x9a7d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125                            0x9b1d
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125                            0x9bbd
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125                            0x9c5d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125                            0x9cfd
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED125                            0x9d9d
-+#define mmUNIPHY_MACRO_CNTL_RESERVED126                                         0x493e
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126                            0x493e
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126                            0x49de
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126                            0x9a7e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126                            0x9b1e
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126                            0x9bbe
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126                            0x9c5e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126                            0x9cfe
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED126                            0x9d9e
-+#define mmUNIPHY_MACRO_CNTL_RESERVED127                                         0x493f
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127                            0x493f
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127                            0x49df
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127                            0x9a7f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127                            0x9b1f
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127                            0x9bbf
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127                            0x9c5f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127                            0x9cff
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED127                            0x9d9f
-+#define mmUNIPHY_MACRO_CNTL_RESERVED128                                         0x4940
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128                            0x4940
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128                            0x49e0
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128                            0x9a80
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128                            0x9b20
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128                            0x9bc0
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128                            0x9c60
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128                            0x9d00
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED128                            0x9da0
-+#define mmUNIPHY_MACRO_CNTL_RESERVED129                                         0x4941
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129                            0x4941
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129                            0x49e1
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129                            0x9a81
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129                            0x9b21
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129                            0x9bc1
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129                            0x9c61
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129                            0x9d01
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED129                            0x9da1
-+#define mmUNIPHY_MACRO_CNTL_RESERVED130                                         0x4942
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130                            0x4942
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130                            0x49e2
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130                            0x9a82
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130                            0x9b22
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130                            0x9bc2
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130                            0x9c62
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130                            0x9d02
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED130                            0x9da2
-+#define mmUNIPHY_MACRO_CNTL_RESERVED131                                         0x4943
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131                            0x4943
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131                            0x49e3
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131                            0x9a83
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131                            0x9b23
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131                            0x9bc3
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131                            0x9c63
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131                            0x9d03
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED131                            0x9da3
-+#define mmUNIPHY_MACRO_CNTL_RESERVED132                                         0x4944
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132                            0x4944
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132                            0x49e4
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132                            0x9a84
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132                            0x9b24
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132                            0x9bc4
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132                            0x9c64
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132                            0x9d04
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED132                            0x9da4
-+#define mmUNIPHY_MACRO_CNTL_RESERVED133                                         0x4945
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133                            0x4945
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133                            0x49e5
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133                            0x9a85
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133                            0x9b25
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133                            0x9bc5
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133                            0x9c65
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133                            0x9d05
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED133                            0x9da5
-+#define mmUNIPHY_MACRO_CNTL_RESERVED134                                         0x4946
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134                            0x4946
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134                            0x49e6
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134                            0x9a86
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134                            0x9b26
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134                            0x9bc6
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134                            0x9c66
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134                            0x9d06
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED134                            0x9da6
-+#define mmUNIPHY_MACRO_CNTL_RESERVED135                                         0x4947
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135                            0x4947
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135                            0x49e7
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135                            0x9a87
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135                            0x9b27
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135                            0x9bc7
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135                            0x9c67
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135                            0x9d07
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED135                            0x9da7
-+#define mmUNIPHY_MACRO_CNTL_RESERVED136                                         0x4948
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136                            0x4948
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136                            0x49e8
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136                            0x9a88
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136                            0x9b28
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136                            0x9bc8
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136                            0x9c68
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136                            0x9d08
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED136                            0x9da8
-+#define mmUNIPHY_MACRO_CNTL_RESERVED137                                         0x4949
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137                            0x4949
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137                            0x49e9
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137                            0x9a89
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137                            0x9b29
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137                            0x9bc9
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137                            0x9c69
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137                            0x9d09
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED137                            0x9da9
-+#define mmUNIPHY_MACRO_CNTL_RESERVED138                                         0x494a
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138                            0x494a
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138                            0x49ea
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138                            0x9a8a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138                            0x9b2a
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138                            0x9bca
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138                            0x9c6a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138                            0x9d0a
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED138                            0x9daa
-+#define mmUNIPHY_MACRO_CNTL_RESERVED139                                         0x494b
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139                            0x494b
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139                            0x49eb
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139                            0x9a8b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139                            0x9b2b
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139                            0x9bcb
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139                            0x9c6b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139                            0x9d0b
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED139                            0x9dab
-+#define mmUNIPHY_MACRO_CNTL_RESERVED140                                         0x494c
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140                            0x494c
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140                            0x49ec
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140                            0x9a8c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140                            0x9b2c
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140                            0x9bcc
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140                            0x9c6c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140                            0x9d0c
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED140                            0x9dac
-+#define mmUNIPHY_MACRO_CNTL_RESERVED141                                         0x494d
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141                            0x494d
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141                            0x49ed
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141                            0x9a8d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141                            0x9b2d
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141                            0x9bcd
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141                            0x9c6d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141                            0x9d0d
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED141                            0x9dad
-+#define mmUNIPHY_MACRO_CNTL_RESERVED142                                         0x494e
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142                            0x494e
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142                            0x49ee
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142                            0x9a8e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142                            0x9b2e
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142                            0x9bce
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142                            0x9c6e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142                            0x9d0e
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED142                            0x9dae
-+#define mmUNIPHY_MACRO_CNTL_RESERVED143                                         0x494f
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143                            0x494f
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143                            0x49ef
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143                            0x9a8f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143                            0x9b2f
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143                            0x9bcf
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143                            0x9c6f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143                            0x9d0f
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED143                            0x9daf
-+#define mmUNIPHY_MACRO_CNTL_RESERVED144                                         0x4950
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144                            0x4950
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144                            0x49f0
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144                            0x9a90
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144                            0x9b30
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144                            0x9bd0
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144                            0x9c70
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144                            0x9d10
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED144                            0x9db0
-+#define mmUNIPHY_MACRO_CNTL_RESERVED145                                         0x4951
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145                            0x4951
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145                            0x49f1
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145                            0x9a91
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145                            0x9b31
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145                            0x9bd1
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145                            0x9c71
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145                            0x9d11
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED145                            0x9db1
-+#define mmUNIPHY_MACRO_CNTL_RESERVED146                                         0x4952
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146                            0x4952
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146                            0x49f2
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146                            0x9a92
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146                            0x9b32
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146                            0x9bd2
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146                            0x9c72
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146                            0x9d12
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED146                            0x9db2
-+#define mmUNIPHY_MACRO_CNTL_RESERVED147                                         0x4953
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147                            0x4953
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147                            0x49f3
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147                            0x9a93
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147                            0x9b33
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147                            0x9bd3
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147                            0x9c73
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147                            0x9d13
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED147                            0x9db3
-+#define mmUNIPHY_MACRO_CNTL_RESERVED148                                         0x4954
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148                            0x4954
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148                            0x49f4
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148                            0x9a94
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148                            0x9b34
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148                            0x9bd4
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148                            0x9c74
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148                            0x9d14
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED148                            0x9db4
-+#define mmUNIPHY_MACRO_CNTL_RESERVED149                                         0x4955
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149                            0x4955
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149                            0x49f5
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149                            0x9a95
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149                            0x9b35
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149                            0x9bd5
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149                            0x9c75
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149                            0x9d15
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED149                            0x9db5
-+#define mmUNIPHY_MACRO_CNTL_RESERVED150                                         0x4956
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150                            0x4956
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150                            0x49f6
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150                            0x9a96
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150                            0x9b36
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150                            0x9bd6
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150                            0x9c76
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150                            0x9d16
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED150                            0x9db6
-+#define mmUNIPHY_MACRO_CNTL_RESERVED151                                         0x4957
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151                            0x4957
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151                            0x49f7
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151                            0x9a97
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151                            0x9b37
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151                            0x9bd7
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151                            0x9c77
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151                            0x9d17
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED151                            0x9db7
-+#define mmUNIPHY_MACRO_CNTL_RESERVED152                                         0x4958
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152                            0x4958
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152                            0x49f8
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152                            0x9a98
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152                            0x9b38
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152                            0x9bd8
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152                            0x9c78
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152                            0x9d18
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED152                            0x9db8
-+#define mmUNIPHY_MACRO_CNTL_RESERVED153                                         0x4959
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153                            0x4959
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153                            0x49f9
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153                            0x9a99
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153                            0x9b39
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153                            0x9bd9
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153                            0x9c79
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153                            0x9d19
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED153                            0x9db9
-+#define mmUNIPHY_MACRO_CNTL_RESERVED154                                         0x495a
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154                            0x495a
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154                            0x49fa
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154                            0x9a9a
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154                            0x9b3a
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154                            0x9bda
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154                            0x9c7a
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154                            0x9d1a
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED154                            0x9dba
-+#define mmUNIPHY_MACRO_CNTL_RESERVED155                                         0x495b
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155                            0x495b
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155                            0x49fb
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155                            0x9a9b
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155                            0x9b3b
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155                            0x9bdb
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155                            0x9c7b
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155                            0x9d1b
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED155                            0x9dbb
-+#define mmUNIPHY_MACRO_CNTL_RESERVED156                                         0x495c
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156                            0x495c
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156                            0x49fc
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156                            0x9a9c
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156                            0x9b3c
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156                            0x9bdc
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156                            0x9c7c
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156                            0x9d1c
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED156                            0x9dbc
-+#define mmUNIPHY_MACRO_CNTL_RESERVED157                                         0x495d
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157                            0x495d
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157                            0x49fd
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157                            0x9a9d
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157                            0x9b3d
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157                            0x9bdd
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157                            0x9c7d
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157                            0x9d1d
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED157                            0x9dbd
-+#define mmUNIPHY_MACRO_CNTL_RESERVED158                                         0x495e
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158                            0x495e
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158                            0x49fe
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158                            0x9a9e
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158                            0x9b3e
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158                            0x9bde
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158                            0x9c7e
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158                            0x9d1e
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED158                            0x9dbe
-+#define mmUNIPHY_MACRO_CNTL_RESERVED159                                         0x495f
-+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159                            0x495f
-+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159                            0x49ff
-+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159                            0x9a9f
-+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159                            0x9b3f
-+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159                            0x9bdf
-+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159                            0x9c7f
-+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159                            0x9d1f
-+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED159                            0x9dbf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED0                                         0x5a84
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED1                                         0x5a85
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED2                                         0x5a86
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED3                                         0x5a87
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED4                                         0x5a88
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED5                                         0x5a89
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED6                                         0x5a8a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED7                                         0x5a8b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED8                                         0x5a8c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED9                                         0x5a8d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED10                                        0x5a8e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED11                                        0x5a8f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED12                                        0x5a90
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED13                                        0x5a91
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED14                                        0x5a92
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED15                                        0x5a93
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED16                                        0x5a94
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED17                                        0x5a95
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED18                                        0x5a96
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED19                                        0x5a97
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED20                                        0x5a98
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED21                                        0x5a99
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED22                                        0x5a9a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED23                                        0x5a9b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED24                                        0x5a9c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED25                                        0x5a9d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED26                                        0x5a9e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED27                                        0x5a9f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED28                                        0x5aa0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED29                                        0x5aa1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED30                                        0x5aa2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED31                                        0x5aa3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED32                                        0x5aa4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED33                                        0x5aa5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED34                                        0x5aa6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED35                                        0x5aa7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED36                                        0x5aa8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED37                                        0x5aa9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED38                                        0x5aaa
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED39                                        0x5aab
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED40                                        0x5aac
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED41                                        0x5aad
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED42                                        0x5aae
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED43                                        0x5aaf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED44                                        0x5ab0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED45                                        0x5ab1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED46                                        0x5ab2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED47                                        0x5ab3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED48                                        0x5ab4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED49                                        0x5ab5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED50                                        0x5ab6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED51                                        0x5ab7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED52                                        0x5ab8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED53                                        0x5ab9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED54                                        0x5aba
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED55                                        0x5abb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED56                                        0x5abc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED57                                        0x5abd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED58                                        0x5abe
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED59                                        0x5abf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED60                                        0x5ac0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED61                                        0x5ac1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED62                                        0x5ac2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED63                                        0x5ac3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED64                                        0x5ac4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED65                                        0x5ac5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED66                                        0x5ac6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED67                                        0x5ac7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED68                                        0x5ac8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED69                                        0x5ac9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED70                                        0x5aca
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED71                                        0x5acb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED72                                        0x5acc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED73                                        0x5acd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED74                                        0x5ace
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED75                                        0x5acf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED76                                        0x5ad0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED77                                        0x5ad1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED78                                        0x5ad2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED79                                        0x5ad3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED80                                        0x5ad4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED81                                        0x5ad5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED82                                        0x5ad6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED83                                        0x5ad7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED84                                        0x5ad8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED85                                        0x5ad9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED86                                        0x5ada
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED87                                        0x5adb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED88                                        0x5adc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED89                                        0x5add
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED90                                        0x5ade
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED91                                        0x5adf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED92                                        0x5ae0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED93                                        0x5ae1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED94                                        0x5ae2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED95                                        0x5ae3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED96                                        0x5ae4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED97                                        0x5ae5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED98                                        0x5ae6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED99                                        0x5ae7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED100                                       0x5ae8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED101                                       0x5ae9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED102                                       0x5aea
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED103                                       0x5aeb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED104                                       0x5aec
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED105                                       0x5aed
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED106                                       0x5aee
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED107                                       0x5aef
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED108                                       0x5af0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED109                                       0x5af1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED110                                       0x5af2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED111                                       0x5af3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED112                                       0x5af4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED113                                       0x5af5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED114                                       0x5af6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED115                                       0x5af7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED116                                       0x5af8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED117                                       0x5af9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED118                                       0x5afa
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED119                                       0x5afb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED120                                       0x5afc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED121                                       0x5afd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED122                                       0x5afe
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED123                                       0x5aff
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED124                                       0x5b00
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED125                                       0x5b01
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED126                                       0x5b02
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED127                                       0x5b03
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED128                                       0x5b04
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED129                                       0x5b05
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED130                                       0x5b06
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED131                                       0x5b07
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED132                                       0x5b08
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED133                                       0x5b09
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED134                                       0x5b0a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED135                                       0x5b0b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED136                                       0x5b0c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED137                                       0x5b0d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED138                                       0x5b0e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED139                                       0x5b0f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED140                                       0x5b10
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED141                                       0x5b11
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED142                                       0x5b12
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED143                                       0x5b13
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED144                                       0x5b14
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED145                                       0x5b15
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED146                                       0x5b16
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED147                                       0x5b17
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED148                                       0x5b18
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED149                                       0x5b19
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED150                                       0x5b1a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED151                                       0x5b1b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED152                                       0x5b1c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED153                                       0x5b1d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED154                                       0x5b1e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED155                                       0x5b1f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED156                                       0x5b20
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED157                                       0x5b21
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED158                                       0x5b22
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED159                                       0x5b23
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED160                                       0x5b24
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED161                                       0x5b25
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED162                                       0x5b26
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED163                                       0x5b27
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED164                                       0x5b28
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED165                                       0x5b29
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED166                                       0x5b2a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED167                                       0x5b2b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED168                                       0x5b2c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED169                                       0x5b2d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED170                                       0x5b2e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED171                                       0x5b2f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED172                                       0x5b30
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED173                                       0x5b31
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED174                                       0x5b32
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED175                                       0x5b33
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED176                                       0x5b34
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED177                                       0x5b35
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED178                                       0x5b36
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED179                                       0x5b37
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED180                                       0x5b38
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED181                                       0x5b39
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED182                                       0x5b3a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED183                                       0x5b3b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED184                                       0x5b3c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED185                                       0x5b3d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED186                                       0x5b3e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED187                                       0x5b3f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED188                                       0x5b40
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED189                                       0x5b41
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED190                                       0x5b42
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED191                                       0x5b43
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED192                                       0x5b44
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED193                                       0x5b45
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED194                                       0x5b46
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED195                                       0x5b47
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED196                                       0x5b48
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED197                                       0x5b49
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED198                                       0x5b4a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED199                                       0x5b4b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED200                                       0x5b4c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED201                                       0x5b4d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED202                                       0x5b4e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED203                                       0x5b4f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED204                                       0x5b50
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED205                                       0x5b51
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED206                                       0x5b52
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED207                                       0x5b53
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED208                                       0x5b54
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED209                                       0x5b55
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED210                                       0x5b56
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED211                                       0x5b57
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED212                                       0x5b58
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED213                                       0x5b59
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED214                                       0x5b5a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED215                                       0x5b5b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED216                                       0x5b5c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED217                                       0x5b5d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED218                                       0x5b5e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED219                                       0x5b5f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED220                                       0x5b60
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED221                                       0x5b61
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED222                                       0x5b62
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED223                                       0x5b63
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED224                                       0x5b64
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED225                                       0x5b65
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED226                                       0x5b66
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED227                                       0x5b67
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED228                                       0x5b68
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED229                                       0x5b69
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED230                                       0x5b6a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED231                                       0x5b6b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED232                                       0x5b6c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED233                                       0x5b6d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED234                                       0x5b6e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED235                                       0x5b6f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED236                                       0x5b70
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED237                                       0x5b71
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED238                                       0x5b72
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED239                                       0x5b73
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED240                                       0x5b74
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED241                                       0x5b75
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED242                                       0x5b76
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED243                                       0x5b77
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED244                                       0x5b78
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED245                                       0x5b79
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED246                                       0x5b7a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED247                                       0x5b7b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED248                                       0x5b7c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED249                                       0x5b7d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED250                                       0x5b7e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED251                                       0x5b7f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED252                                       0x5b80
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED253                                       0x5b81
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED254                                       0x5b82
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED255                                       0x5b83
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED256                                       0x5b84
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED257                                       0x5b85
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED258                                       0x5b86
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED259                                       0x5b87
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED260                                       0x5b88
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED261                                       0x5b89
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED262                                       0x5b8a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED263                                       0x5b8b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED264                                       0x5b8c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED265                                       0x5b8d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED266                                       0x5b8e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED267                                       0x5b8f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED268                                       0x5b90
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED269                                       0x5b91
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED270                                       0x5b92
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED271                                       0x5b93
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED272                                       0x5b94
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED273                                       0x5b95
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED274                                       0x5b96
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED275                                       0x5b97
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED276                                       0x5b98
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED277                                       0x5b99
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED278                                       0x5b9a
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED279                                       0x5b9b
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED280                                       0x5b9c
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED281                                       0x5b9d
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED282                                       0x5b9e
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED283                                       0x5b9f
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED284                                       0x5ba0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED285                                       0x5ba1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED286                                       0x5ba2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED287                                       0x5ba3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED288                                       0x5ba4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED289                                       0x5ba5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED290                                       0x5ba6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED291                                       0x5ba7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED292                                       0x5ba8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED293                                       0x5ba9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED294                                       0x5baa
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED295                                       0x5bab
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED296                                       0x5bac
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED297                                       0x5bad
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED298                                       0x5bae
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED299                                       0x5baf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED300                                       0x5bb0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED301                                       0x5bb1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED302                                       0x5bb2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED303                                       0x5bb3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED304                                       0x5bb4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED305                                       0x5bb5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED306                                       0x5bb6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED307                                       0x5bb7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED308                                       0x5bb8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED309                                       0x5bb9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED310                                       0x5bba
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED311                                       0x5bbb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED312                                       0x5bbc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED313                                       0x5bbd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED314                                       0x5bbe
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED315                                       0x5bbf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED316                                       0x5bc0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED317                                       0x5bc1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED318                                       0x5bc2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED319                                       0x5bc3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED320                                       0x5bc4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED321                                       0x5bc5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED322                                       0x5bc6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED323                                       0x5bc7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED324                                       0x5bc8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED325                                       0x5bc9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED326                                       0x5bca
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED327                                       0x5bcb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED328                                       0x5bcc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED329                                       0x5bcd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED330                                       0x5bce
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED331                                       0x5bcf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED332                                       0x5bd0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED333                                       0x5bd1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED334                                       0x5bd2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED335                                       0x5bd3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED336                                       0x5bd4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED337                                       0x5bd5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED338                                       0x5bd6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED339                                       0x5bd7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED340                                       0x5bd8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED341                                       0x5bd9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED342                                       0x5bda
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED343                                       0x5bdb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED344                                       0x5bdc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED345                                       0x5bdd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED346                                       0x5bde
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED347                                       0x5bdf
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED348                                       0x5be0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED349                                       0x5be1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED350                                       0x5be2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED351                                       0x5be3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED352                                       0x5be4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED353                                       0x5be5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED354                                       0x5be6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED355                                       0x5be7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED356                                       0x5be8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED357                                       0x5be9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED358                                       0x5bea
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED359                                       0x5beb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED360                                       0x5bec
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED361                                       0x5bed
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED362                                       0x5bee
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED363                                       0x5bef
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED364                                       0x5bf0
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED365                                       0x5bf1
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED366                                       0x5bf2
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED367                                       0x5bf3
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED368                                       0x5bf4
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED369                                       0x5bf5
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED370                                       0x5bf6
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED371                                       0x5bf7
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED372                                       0x5bf8
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED373                                       0x5bf9
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED374                                       0x5bfa
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED375                                       0x5bfb
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED376                                       0x5bfc
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED377                                       0x5bfd
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED378                                       0x5bfe
-+#define mmDCRX_PHY_MACRO_CNTL_RESERVED379                                       0x5bff
-+#define mmDPHY_MACRO_CNTL_RESERVED0                                             0x5d98
-+#define mmDPHY_MACRO_CNTL_RESERVED1                                             0x5d99
-+#define mmDPHY_MACRO_CNTL_RESERVED2                                             0x5d9a
-+#define mmDPHY_MACRO_CNTL_RESERVED3                                             0x5d9b
-+#define mmDPHY_MACRO_CNTL_RESERVED4                                             0x5d9c
-+#define mmDPHY_MACRO_CNTL_RESERVED5                                             0x5d9d
-+#define mmDPHY_MACRO_CNTL_RESERVED6                                             0x5d9e
-+#define mmDPHY_MACRO_CNTL_RESERVED7                                             0x5d9f
-+#define mmDPHY_MACRO_CNTL_RESERVED8                                             0x5da0
-+#define mmDPHY_MACRO_CNTL_RESERVED9                                             0x5da1
-+#define mmDPHY_MACRO_CNTL_RESERVED10                                            0x5da2
-+#define mmDPHY_MACRO_CNTL_RESERVED11                                            0x5da3
-+#define mmDPHY_MACRO_CNTL_RESERVED12                                            0x5da4
-+#define mmDPHY_MACRO_CNTL_RESERVED13                                            0x5da5
-+#define mmDPHY_MACRO_CNTL_RESERVED14                                            0x5da6
-+#define mmDPHY_MACRO_CNTL_RESERVED15                                            0x5da7
-+#define mmDPHY_MACRO_CNTL_RESERVED16                                            0x5da8
-+#define mmDPHY_MACRO_CNTL_RESERVED17                                            0x5da9
-+#define mmDPHY_MACRO_CNTL_RESERVED18                                            0x5daa
-+#define mmDPHY_MACRO_CNTL_RESERVED19                                            0x5dab
-+#define mmDPHY_MACRO_CNTL_RESERVED20                                            0x5dac
-+#define mmDPHY_MACRO_CNTL_RESERVED21                                            0x5dad
-+#define mmDPHY_MACRO_CNTL_RESERVED22                                            0x5dae
-+#define mmDPHY_MACRO_CNTL_RESERVED23                                            0x5daf
-+#define mmDPHY_MACRO_CNTL_RESERVED24                                            0x5db0
-+#define mmDPHY_MACRO_CNTL_RESERVED25                                            0x5db1
-+#define mmDPHY_MACRO_CNTL_RESERVED26                                            0x5db2
-+#define mmDPHY_MACRO_CNTL_RESERVED27                                            0x5db3
-+#define mmDPHY_MACRO_CNTL_RESERVED28                                            0x5db4
-+#define mmDPHY_MACRO_CNTL_RESERVED29                                            0x5db5
-+#define mmDPHY_MACRO_CNTL_RESERVED30                                            0x5db6
-+#define mmDPHY_MACRO_CNTL_RESERVED31                                            0x5db7
-+#define mmDPHY_MACRO_CNTL_RESERVED32                                            0x5db8
-+#define mmDPHY_MACRO_CNTL_RESERVED33                                            0x5db9
-+#define mmDPHY_MACRO_CNTL_RESERVED34                                            0x5dba
-+#define mmDPHY_MACRO_CNTL_RESERVED35                                            0x5dbb
-+#define mmDPHY_MACRO_CNTL_RESERVED36                                            0x5dbc
-+#define mmDPHY_MACRO_CNTL_RESERVED37                                            0x5dbd
-+#define mmDPHY_MACRO_CNTL_RESERVED38                                            0x5dbe
-+#define mmDPHY_MACRO_CNTL_RESERVED39                                            0x5dbf
-+#define mmDPHY_MACRO_CNTL_RESERVED40                                            0x5dc0
-+#define mmDPHY_MACRO_CNTL_RESERVED41                                            0x5dc1
-+#define mmDPHY_MACRO_CNTL_RESERVED42                                            0x5dc2
-+#define mmDPHY_MACRO_CNTL_RESERVED43                                            0x5dc3
-+#define mmDPHY_MACRO_CNTL_RESERVED44                                            0x5dc4
-+#define mmDPHY_MACRO_CNTL_RESERVED45                                            0x5dc5
-+#define mmDPHY_MACRO_CNTL_RESERVED46                                            0x5dc6
-+#define mmDPHY_MACRO_CNTL_RESERVED47                                            0x5dc7
-+#define mmDPHY_MACRO_CNTL_RESERVED48                                            0x5dc8
-+#define mmDPHY_MACRO_CNTL_RESERVED49                                            0x5dc9
-+#define mmDPHY_MACRO_CNTL_RESERVED50                                            0x5dca
-+#define mmDPHY_MACRO_CNTL_RESERVED51                                            0x5dcb
-+#define mmDPHY_MACRO_CNTL_RESERVED52                                            0x5dcc
-+#define mmDPHY_MACRO_CNTL_RESERVED53                                            0x5dcd
-+#define mmDPHY_MACRO_CNTL_RESERVED54                                            0x5dce
-+#define mmDPHY_MACRO_CNTL_RESERVED55                                            0x5dcf
-+#define mmDPHY_MACRO_CNTL_RESERVED56                                            0x5dd0
-+#define mmDPHY_MACRO_CNTL_RESERVED57                                            0x5dd1
-+#define mmDPHY_MACRO_CNTL_RESERVED58                                            0x5dd2
-+#define mmDPHY_MACRO_CNTL_RESERVED59                                            0x5dd3
-+#define mmDPHY_MACRO_CNTL_RESERVED60                                            0x5dd4
-+#define mmDPHY_MACRO_CNTL_RESERVED61                                            0x5dd5
-+#define mmDPHY_MACRO_CNTL_RESERVED62                                            0x5dd6
-+#define mmDPHY_MACRO_CNTL_RESERVED63                                            0x5dd7
-+#define mmGRPH_ENABLE                                                           0x1a00
-+#define mmDCP0_GRPH_ENABLE                                                      0x1a00
-+#define mmDCP1_GRPH_ENABLE                                                      0x1c00
-+#define mmDCP2_GRPH_ENABLE                                                      0x1e00
-+#define mmDCP3_GRPH_ENABLE                                                      0x4000
-+#define mmDCP4_GRPH_ENABLE                                                      0x4200
-+#define mmDCP5_GRPH_ENABLE                                                      0x4400
-+#define mmGRPH_CONTROL                                                          0x1a01
-+#define mmDCP0_GRPH_CONTROL                                                     0x1a01
-+#define mmDCP1_GRPH_CONTROL                                                     0x1c01
-+#define mmDCP2_GRPH_CONTROL                                                     0x1e01
-+#define mmDCP3_GRPH_CONTROL                                                     0x4001
-+#define mmDCP4_GRPH_CONTROL                                                     0x4201
-+#define mmDCP5_GRPH_CONTROL                                                     0x4401
-+#define mmGRPH_LUT_10BIT_BYPASS                                                 0x1a02
-+#define mmDCP0_GRPH_LUT_10BIT_BYPASS                                            0x1a02
-+#define mmDCP1_GRPH_LUT_10BIT_BYPASS                                            0x1c02
-+#define mmDCP2_GRPH_LUT_10BIT_BYPASS                                            0x1e02
-+#define mmDCP3_GRPH_LUT_10BIT_BYPASS                                            0x4002
-+#define mmDCP4_GRPH_LUT_10BIT_BYPASS                                            0x4202
-+#define mmDCP5_GRPH_LUT_10BIT_BYPASS                                            0x4402
-+#define mmGRPH_SWAP_CNTL                                                        0x1a03
-+#define mmDCP0_GRPH_SWAP_CNTL                                                   0x1a03
-+#define mmDCP1_GRPH_SWAP_CNTL                                                   0x1c03
-+#define mmDCP2_GRPH_SWAP_CNTL                                                   0x1e03
-+#define mmDCP3_GRPH_SWAP_CNTL                                                   0x4003
-+#define mmDCP4_GRPH_SWAP_CNTL                                                   0x4203
-+#define mmDCP5_GRPH_SWAP_CNTL                                                   0x4403
-+#define mmGRPH_PRIMARY_SURFACE_ADDRESS                                          0x1a04
-+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1a04
-+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1c04
-+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1e04
-+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4004
-+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4204
-+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4404
-+#define mmGRPH_SECONDARY_SURFACE_ADDRESS                                        0x1a05
-+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1a05
-+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1c05
-+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1e05
-+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4005
-+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4205
-+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4405
-+#define mmGRPH_PITCH                                                            0x1a06
-+#define mmDCP0_GRPH_PITCH                                                       0x1a06
-+#define mmDCP1_GRPH_PITCH                                                       0x1c06
-+#define mmDCP2_GRPH_PITCH                                                       0x1e06
-+#define mmDCP3_GRPH_PITCH                                                       0x4006
-+#define mmDCP4_GRPH_PITCH                                                       0x4206
-+#define mmDCP5_GRPH_PITCH                                                       0x4406
-+#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                     0x1a07
-+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1a07
-+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1c07
-+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1e07
-+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4007
-+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4207
-+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4407
-+#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                   0x1a08
-+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1a08
-+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1c08
-+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1e08
-+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4008
-+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4208
-+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4408
-+#define mmGRPH_SURFACE_OFFSET_X                                                 0x1a09
-+#define mmDCP0_GRPH_SURFACE_OFFSET_X                                            0x1a09
-+#define mmDCP1_GRPH_SURFACE_OFFSET_X                                            0x1c09
-+#define mmDCP2_GRPH_SURFACE_OFFSET_X                                            0x1e09
-+#define mmDCP3_GRPH_SURFACE_OFFSET_X                                            0x4009
-+#define mmDCP4_GRPH_SURFACE_OFFSET_X                                            0x4209
-+#define mmDCP5_GRPH_SURFACE_OFFSET_X                                            0x4409
-+#define mmGRPH_SURFACE_OFFSET_Y                                                 0x1a0a
-+#define mmDCP0_GRPH_SURFACE_OFFSET_Y                                            0x1a0a
-+#define mmDCP1_GRPH_SURFACE_OFFSET_Y                                            0x1c0a
-+#define mmDCP2_GRPH_SURFACE_OFFSET_Y                                            0x1e0a
-+#define mmDCP3_GRPH_SURFACE_OFFSET_Y                                            0x400a
-+#define mmDCP4_GRPH_SURFACE_OFFSET_Y                                            0x420a
-+#define mmDCP5_GRPH_SURFACE_OFFSET_Y                                            0x440a
-+#define mmGRPH_X_START                                                          0x1a0b
-+#define mmDCP0_GRPH_X_START                                                     0x1a0b
-+#define mmDCP1_GRPH_X_START                                                     0x1c0b
-+#define mmDCP2_GRPH_X_START                                                     0x1e0b
-+#define mmDCP3_GRPH_X_START                                                     0x400b
-+#define mmDCP4_GRPH_X_START                                                     0x420b
-+#define mmDCP5_GRPH_X_START                                                     0x440b
-+#define mmGRPH_Y_START                                                          0x1a0c
-+#define mmDCP0_GRPH_Y_START                                                     0x1a0c
-+#define mmDCP1_GRPH_Y_START                                                     0x1c0c
-+#define mmDCP2_GRPH_Y_START                                                     0x1e0c
-+#define mmDCP3_GRPH_Y_START                                                     0x400c
-+#define mmDCP4_GRPH_Y_START                                                     0x420c
-+#define mmDCP5_GRPH_Y_START                                                     0x440c
-+#define mmGRPH_X_END                                                            0x1a0d
-+#define mmDCP0_GRPH_X_END                                                       0x1a0d
-+#define mmDCP1_GRPH_X_END                                                       0x1c0d
-+#define mmDCP2_GRPH_X_END                                                       0x1e0d
-+#define mmDCP3_GRPH_X_END                                                       0x400d
-+#define mmDCP4_GRPH_X_END                                                       0x420d
-+#define mmDCP5_GRPH_X_END                                                       0x440d
-+#define mmGRPH_Y_END                                                            0x1a0e
-+#define mmDCP0_GRPH_Y_END                                                       0x1a0e
-+#define mmDCP1_GRPH_Y_END                                                       0x1c0e
-+#define mmDCP2_GRPH_Y_END                                                       0x1e0e
-+#define mmDCP3_GRPH_Y_END                                                       0x400e
-+#define mmDCP4_GRPH_Y_END                                                       0x420e
-+#define mmDCP5_GRPH_Y_END                                                       0x440e
-+#define mmINPUT_GAMMA_CONTROL                                                   0x1a10
-+#define mmDCP0_INPUT_GAMMA_CONTROL                                              0x1a10
-+#define mmDCP1_INPUT_GAMMA_CONTROL                                              0x1c10
-+#define mmDCP2_INPUT_GAMMA_CONTROL                                              0x1e10
-+#define mmDCP3_INPUT_GAMMA_CONTROL                                              0x4010
-+#define mmDCP4_INPUT_GAMMA_CONTROL                                              0x4210
-+#define mmDCP5_INPUT_GAMMA_CONTROL                                              0x4410
-+#define mmGRPH_UPDATE                                                           0x1a11
-+#define mmDCP0_GRPH_UPDATE                                                      0x1a11
-+#define mmDCP1_GRPH_UPDATE                                                      0x1c11
-+#define mmDCP2_GRPH_UPDATE                                                      0x1e11
-+#define mmDCP3_GRPH_UPDATE                                                      0x4011
-+#define mmDCP4_GRPH_UPDATE                                                      0x4211
-+#define mmDCP5_GRPH_UPDATE                                                      0x4411
-+#define mmGRPH_FLIP_CONTROL                                                     0x1a12
-+#define mmDCP0_GRPH_FLIP_CONTROL                                                0x1a12
-+#define mmDCP1_GRPH_FLIP_CONTROL                                                0x1c12
-+#define mmDCP2_GRPH_FLIP_CONTROL                                                0x1e12
-+#define mmDCP3_GRPH_FLIP_CONTROL                                                0x4012
-+#define mmDCP4_GRPH_FLIP_CONTROL                                                0x4212
-+#define mmDCP5_GRPH_FLIP_CONTROL                                                0x4412
-+#define mmGRPH_SURFACE_ADDRESS_INUSE                                            0x1a13
-+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                       0x1a13
-+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                       0x1c13
-+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                       0x1e13
-+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                       0x4013
-+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                       0x4213
-+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                       0x4413
-+#define mmGRPH_DFQ_CONTROL                                                      0x1a14
-+#define mmDCP0_GRPH_DFQ_CONTROL                                                 0x1a14
-+#define mmDCP1_GRPH_DFQ_CONTROL                                                 0x1c14
-+#define mmDCP2_GRPH_DFQ_CONTROL                                                 0x1e14
-+#define mmDCP3_GRPH_DFQ_CONTROL                                                 0x4014
-+#define mmDCP4_GRPH_DFQ_CONTROL                                                 0x4214
-+#define mmDCP5_GRPH_DFQ_CONTROL                                                 0x4414
-+#define mmGRPH_DFQ_STATUS                                                       0x1a15
-+#define mmDCP0_GRPH_DFQ_STATUS                                                  0x1a15
-+#define mmDCP1_GRPH_DFQ_STATUS                                                  0x1c15
-+#define mmDCP2_GRPH_DFQ_STATUS                                                  0x1e15
-+#define mmDCP3_GRPH_DFQ_STATUS                                                  0x4015
-+#define mmDCP4_GRPH_DFQ_STATUS                                                  0x4215
-+#define mmDCP5_GRPH_DFQ_STATUS                                                  0x4415
-+#define mmGRPH_INTERRUPT_STATUS                                                 0x1a16
-+#define mmDCP0_GRPH_INTERRUPT_STATUS                                            0x1a16
-+#define mmDCP1_GRPH_INTERRUPT_STATUS                                            0x1c16
-+#define mmDCP2_GRPH_INTERRUPT_STATUS                                            0x1e16
-+#define mmDCP3_GRPH_INTERRUPT_STATUS                                            0x4016
-+#define mmDCP4_GRPH_INTERRUPT_STATUS                                            0x4216
-+#define mmDCP5_GRPH_INTERRUPT_STATUS                                            0x4416
-+#define mmGRPH_INTERRUPT_CONTROL                                                0x1a17
-+#define mmDCP0_GRPH_INTERRUPT_CONTROL                                           0x1a17
-+#define mmDCP1_GRPH_INTERRUPT_CONTROL                                           0x1c17
-+#define mmDCP2_GRPH_INTERRUPT_CONTROL                                           0x1e17
-+#define mmDCP3_GRPH_INTERRUPT_CONTROL                                           0x4017
-+#define mmDCP4_GRPH_INTERRUPT_CONTROL                                           0x4217
-+#define mmDCP5_GRPH_INTERRUPT_CONTROL                                           0x4417
-+#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE                                       0x1a18
-+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1a18
-+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1c18
-+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1e18
-+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4018
-+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4218
-+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4418
-+#define mmGRPH_COMPRESS_SURFACE_ADDRESS                                         0x1a19
-+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1a19
-+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1c19
-+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1e19
-+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4019
-+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4219
-+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4419
-+#define mmGRPH_COMPRESS_PITCH                                                   0x1a1a
-+#define mmDCP0_GRPH_COMPRESS_PITCH                                              0x1a1a
-+#define mmDCP1_GRPH_COMPRESS_PITCH                                              0x1c1a
-+#define mmDCP2_GRPH_COMPRESS_PITCH                                              0x1e1a
-+#define mmDCP3_GRPH_COMPRESS_PITCH                                              0x401a
-+#define mmDCP4_GRPH_COMPRESS_PITCH                                              0x421a
-+#define mmDCP5_GRPH_COMPRESS_PITCH                                              0x441a
-+#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                    0x1a1b
-+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1a1b
-+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1c1b
-+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1e1b
-+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x401b
-+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x421b
-+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x441b
-+#define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                   0x1a1c
-+#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1a1c
-+#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1c1c
-+#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1e1c
-+#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x401c
-+#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x421c
-+#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x441c
-+#define mmPRESCALE_GRPH_CONTROL                                                 0x1a2d
-+#define mmDCP0_PRESCALE_GRPH_CONTROL                                            0x1a2d
-+#define mmDCP1_PRESCALE_GRPH_CONTROL                                            0x1c2d
-+#define mmDCP2_PRESCALE_GRPH_CONTROL                                            0x1e2d
-+#define mmDCP3_PRESCALE_GRPH_CONTROL                                            0x402d
-+#define mmDCP4_PRESCALE_GRPH_CONTROL                                            0x422d
-+#define mmDCP5_PRESCALE_GRPH_CONTROL                                            0x442d
-+#define mmPRESCALE_VALUES_GRPH_R                                                0x1a2e
-+#define mmDCP0_PRESCALE_VALUES_GRPH_R                                           0x1a2e
-+#define mmDCP1_PRESCALE_VALUES_GRPH_R                                           0x1c2e
-+#define mmDCP2_PRESCALE_VALUES_GRPH_R                                           0x1e2e
-+#define mmDCP3_PRESCALE_VALUES_GRPH_R                                           0x402e
-+#define mmDCP4_PRESCALE_VALUES_GRPH_R                                           0x422e
-+#define mmDCP5_PRESCALE_VALUES_GRPH_R                                           0x442e
-+#define mmPRESCALE_VALUES_GRPH_G                                                0x1a2f
-+#define mmDCP0_PRESCALE_VALUES_GRPH_G                                           0x1a2f
-+#define mmDCP1_PRESCALE_VALUES_GRPH_G                                           0x1c2f
-+#define mmDCP2_PRESCALE_VALUES_GRPH_G                                           0x1e2f
-+#define mmDCP3_PRESCALE_VALUES_GRPH_G                                           0x402f
-+#define mmDCP4_PRESCALE_VALUES_GRPH_G                                           0x422f
-+#define mmDCP5_PRESCALE_VALUES_GRPH_G                                           0x442f
-+#define mmPRESCALE_VALUES_GRPH_B                                                0x1a30
-+#define mmDCP0_PRESCALE_VALUES_GRPH_B                                           0x1a30
-+#define mmDCP1_PRESCALE_VALUES_GRPH_B                                           0x1c30
-+#define mmDCP2_PRESCALE_VALUES_GRPH_B                                           0x1e30
-+#define mmDCP3_PRESCALE_VALUES_GRPH_B                                           0x4030
-+#define mmDCP4_PRESCALE_VALUES_GRPH_B                                           0x4230
-+#define mmDCP5_PRESCALE_VALUES_GRPH_B                                           0x4430
-+#define mmINPUT_CSC_CONTROL                                                     0x1a35
-+#define mmDCP0_INPUT_CSC_CONTROL                                                0x1a35
-+#define mmDCP1_INPUT_CSC_CONTROL                                                0x1c35
-+#define mmDCP2_INPUT_CSC_CONTROL                                                0x1e35
-+#define mmDCP3_INPUT_CSC_CONTROL                                                0x4035
-+#define mmDCP4_INPUT_CSC_CONTROL                                                0x4235
-+#define mmDCP5_INPUT_CSC_CONTROL                                                0x4435
-+#define mmINPUT_CSC_C11_C12                                                     0x1a36
-+#define mmDCP0_INPUT_CSC_C11_C12                                                0x1a36
-+#define mmDCP1_INPUT_CSC_C11_C12                                                0x1c36
-+#define mmDCP2_INPUT_CSC_C11_C12                                                0x1e36
-+#define mmDCP3_INPUT_CSC_C11_C12                                                0x4036
-+#define mmDCP4_INPUT_CSC_C11_C12                                                0x4236
-+#define mmDCP5_INPUT_CSC_C11_C12                                                0x4436
-+#define mmINPUT_CSC_C13_C14                                                     0x1a37
-+#define mmDCP0_INPUT_CSC_C13_C14                                                0x1a37
-+#define mmDCP1_INPUT_CSC_C13_C14                                                0x1c37
-+#define mmDCP2_INPUT_CSC_C13_C14                                                0x1e37
-+#define mmDCP3_INPUT_CSC_C13_C14                                                0x4037
-+#define mmDCP4_INPUT_CSC_C13_C14                                                0x4237
-+#define mmDCP5_INPUT_CSC_C13_C14                                                0x4437
-+#define mmINPUT_CSC_C21_C22                                                     0x1a38
-+#define mmDCP0_INPUT_CSC_C21_C22                                                0x1a38
-+#define mmDCP1_INPUT_CSC_C21_C22                                                0x1c38
-+#define mmDCP2_INPUT_CSC_C21_C22                                                0x1e38
-+#define mmDCP3_INPUT_CSC_C21_C22                                                0x4038
-+#define mmDCP4_INPUT_CSC_C21_C22                                                0x4238
-+#define mmDCP5_INPUT_CSC_C21_C22                                                0x4438
-+#define mmINPUT_CSC_C23_C24                                                     0x1a39
-+#define mmDCP0_INPUT_CSC_C23_C24                                                0x1a39
-+#define mmDCP1_INPUT_CSC_C23_C24                                                0x1c39
-+#define mmDCP2_INPUT_CSC_C23_C24                                                0x1e39
-+#define mmDCP3_INPUT_CSC_C23_C24                                                0x4039
-+#define mmDCP4_INPUT_CSC_C23_C24                                                0x4239
-+#define mmDCP5_INPUT_CSC_C23_C24                                                0x4439
-+#define mmINPUT_CSC_C31_C32                                                     0x1a3a
-+#define mmDCP0_INPUT_CSC_C31_C32                                                0x1a3a
-+#define mmDCP1_INPUT_CSC_C31_C32                                                0x1c3a
-+#define mmDCP2_INPUT_CSC_C31_C32                                                0x1e3a
-+#define mmDCP3_INPUT_CSC_C31_C32                                                0x403a
-+#define mmDCP4_INPUT_CSC_C31_C32                                                0x423a
-+#define mmDCP5_INPUT_CSC_C31_C32                                                0x443a
-+#define mmINPUT_CSC_C33_C34                                                     0x1a3b
-+#define mmDCP0_INPUT_CSC_C33_C34                                                0x1a3b
-+#define mmDCP1_INPUT_CSC_C33_C34                                                0x1c3b
-+#define mmDCP2_INPUT_CSC_C33_C34                                                0x1e3b
-+#define mmDCP3_INPUT_CSC_C33_C34                                                0x403b
-+#define mmDCP4_INPUT_CSC_C33_C34                                                0x423b
-+#define mmDCP5_INPUT_CSC_C33_C34                                                0x443b
-+#define mmOUTPUT_CSC_CONTROL                                                    0x1a3c
-+#define mmDCP0_OUTPUT_CSC_CONTROL                                               0x1a3c
-+#define mmDCP1_OUTPUT_CSC_CONTROL                                               0x1c3c
-+#define mmDCP2_OUTPUT_CSC_CONTROL                                               0x1e3c
-+#define mmDCP3_OUTPUT_CSC_CONTROL                                               0x403c
-+#define mmDCP4_OUTPUT_CSC_CONTROL                                               0x423c
-+#define mmDCP5_OUTPUT_CSC_CONTROL                                               0x443c
-+#define mmOUTPUT_CSC_C11_C12                                                    0x1a3d
-+#define mmDCP0_OUTPUT_CSC_C11_C12                                               0x1a3d
-+#define mmDCP1_OUTPUT_CSC_C11_C12                                               0x1c3d
-+#define mmDCP2_OUTPUT_CSC_C11_C12                                               0x1e3d
-+#define mmDCP3_OUTPUT_CSC_C11_C12                                               0x403d
-+#define mmDCP4_OUTPUT_CSC_C11_C12                                               0x423d
-+#define mmDCP5_OUTPUT_CSC_C11_C12                                               0x443d
-+#define mmOUTPUT_CSC_C13_C14                                                    0x1a3e
-+#define mmDCP0_OUTPUT_CSC_C13_C14                                               0x1a3e
-+#define mmDCP1_OUTPUT_CSC_C13_C14                                               0x1c3e
-+#define mmDCP2_OUTPUT_CSC_C13_C14                                               0x1e3e
-+#define mmDCP3_OUTPUT_CSC_C13_C14                                               0x403e
-+#define mmDCP4_OUTPUT_CSC_C13_C14                                               0x423e
-+#define mmDCP5_OUTPUT_CSC_C13_C14                                               0x443e
-+#define mmOUTPUT_CSC_C21_C22                                                    0x1a3f
-+#define mmDCP0_OUTPUT_CSC_C21_C22                                               0x1a3f
-+#define mmDCP1_OUTPUT_CSC_C21_C22                                               0x1c3f
-+#define mmDCP2_OUTPUT_CSC_C21_C22                                               0x1e3f
-+#define mmDCP3_OUTPUT_CSC_C21_C22                                               0x403f
-+#define mmDCP4_OUTPUT_CSC_C21_C22                                               0x423f
-+#define mmDCP5_OUTPUT_CSC_C21_C22                                               0x443f
-+#define mmOUTPUT_CSC_C23_C24                                                    0x1a40
-+#define mmDCP0_OUTPUT_CSC_C23_C24                                               0x1a40
-+#define mmDCP1_OUTPUT_CSC_C23_C24                                               0x1c40
-+#define mmDCP2_OUTPUT_CSC_C23_C24                                               0x1e40
-+#define mmDCP3_OUTPUT_CSC_C23_C24                                               0x4040
-+#define mmDCP4_OUTPUT_CSC_C23_C24                                               0x4240
-+#define mmDCP5_OUTPUT_CSC_C23_C24                                               0x4440
-+#define mmOUTPUT_CSC_C31_C32                                                    0x1a41
-+#define mmDCP0_OUTPUT_CSC_C31_C32                                               0x1a41
-+#define mmDCP1_OUTPUT_CSC_C31_C32                                               0x1c41
-+#define mmDCP2_OUTPUT_CSC_C31_C32                                               0x1e41
-+#define mmDCP3_OUTPUT_CSC_C31_C32                                               0x4041
-+#define mmDCP4_OUTPUT_CSC_C31_C32                                               0x4241
-+#define mmDCP5_OUTPUT_CSC_C31_C32                                               0x4441
-+#define mmOUTPUT_CSC_C33_C34                                                    0x1a42
-+#define mmDCP0_OUTPUT_CSC_C33_C34                                               0x1a42
-+#define mmDCP1_OUTPUT_CSC_C33_C34                                               0x1c42
-+#define mmDCP2_OUTPUT_CSC_C33_C34                                               0x1e42
-+#define mmDCP3_OUTPUT_CSC_C33_C34                                               0x4042
-+#define mmDCP4_OUTPUT_CSC_C33_C34                                               0x4242
-+#define mmDCP5_OUTPUT_CSC_C33_C34                                               0x4442
-+#define mmCOMM_MATRIXA_TRANS_C11_C12                                            0x1a43
-+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                       0x1a43
-+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                       0x1c43
-+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                       0x1e43
-+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                       0x4043
-+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                       0x4243
-+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                       0x4443
-+#define mmCOMM_MATRIXA_TRANS_C13_C14                                            0x1a44
-+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                       0x1a44
-+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                       0x1c44
-+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                       0x1e44
-+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                       0x4044
-+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                       0x4244
-+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                       0x4444
-+#define mmCOMM_MATRIXA_TRANS_C21_C22                                            0x1a45
-+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                       0x1a45
-+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                       0x1c45
-+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                       0x1e45
-+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                       0x4045
-+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                       0x4245
-+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                       0x4445
-+#define mmCOMM_MATRIXA_TRANS_C23_C24                                            0x1a46
-+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                       0x1a46
-+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                       0x1c46
-+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                       0x1e46
-+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                       0x4046
-+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                       0x4246
-+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                       0x4446
-+#define mmCOMM_MATRIXA_TRANS_C31_C32                                            0x1a47
-+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                       0x1a47
-+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                       0x1c47
-+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                       0x1e47
-+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                       0x4047
-+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                       0x4247
-+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                       0x4447
-+#define mmCOMM_MATRIXA_TRANS_C33_C34                                            0x1a48
-+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                       0x1a48
-+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                       0x1c48
-+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                       0x1e48
-+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                       0x4048
-+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                       0x4248
-+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                       0x4448
-+#define mmCOMM_MATRIXB_TRANS_C11_C12                                            0x1a49
-+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                       0x1a49
-+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                       0x1c49
-+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                       0x1e49
-+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                       0x4049
-+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                       0x4249
-+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                       0x4449
-+#define mmCOMM_MATRIXB_TRANS_C13_C14                                            0x1a4a
-+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                       0x1a4a
-+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                       0x1c4a
-+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                       0x1e4a
-+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                       0x404a
-+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                       0x424a
-+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                       0x444a
-+#define mmCOMM_MATRIXB_TRANS_C21_C22                                            0x1a4b
-+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                       0x1a4b
-+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                       0x1c4b
-+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                       0x1e4b
-+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                       0x404b
-+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                       0x424b
-+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                       0x444b
-+#define mmCOMM_MATRIXB_TRANS_C23_C24                                            0x1a4c
-+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                       0x1a4c
-+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                       0x1c4c
-+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                       0x1e4c
-+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                       0x404c
-+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                       0x424c
-+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                       0x444c
-+#define mmCOMM_MATRIXB_TRANS_C31_C32                                            0x1a4d
-+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                       0x1a4d
-+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                       0x1c4d
-+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                       0x1e4d
-+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                       0x404d
-+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                       0x424d
-+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                       0x444d
-+#define mmCOMM_MATRIXB_TRANS_C33_C34                                            0x1a4e
-+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                       0x1a4e
-+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                       0x1c4e
-+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                       0x1e4e
-+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                       0x404e
-+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                       0x424e
-+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                       0x444e
-+#define mmDENORM_CONTROL                                                        0x1a50
-+#define mmDCP0_DENORM_CONTROL                                                   0x1a50
-+#define mmDCP1_DENORM_CONTROL                                                   0x1c50
-+#define mmDCP2_DENORM_CONTROL                                                   0x1e50
-+#define mmDCP3_DENORM_CONTROL                                                   0x4050
-+#define mmDCP4_DENORM_CONTROL                                                   0x4250
-+#define mmDCP5_DENORM_CONTROL                                                   0x4450
-+#define mmOUT_ROUND_CONTROL                                                     0x1a51
-+#define mmDCP0_OUT_ROUND_CONTROL                                                0x1a51
-+#define mmDCP1_OUT_ROUND_CONTROL                                                0x1c51
-+#define mmDCP2_OUT_ROUND_CONTROL                                                0x1e51
-+#define mmDCP3_OUT_ROUND_CONTROL                                                0x4051
-+#define mmDCP4_OUT_ROUND_CONTROL                                                0x4251
-+#define mmDCP5_OUT_ROUND_CONTROL                                                0x4451
-+#define mmOUT_CLAMP_CONTROL_R_CR                                                0x1a52
-+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR                                           0x1a52
-+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR                                           0x1c52
-+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR                                           0x1e52
-+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR                                           0x4052
-+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR                                           0x4252
-+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR                                           0x4452
-+#define mmOUT_CLAMP_CONTROL_G_Y                                                 0x1a9c
-+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y                                            0x1a9c
-+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y                                            0x1c9c
-+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y                                            0x1e9c
-+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y                                            0x409c
-+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y                                            0x429c
-+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y                                            0x449c
-+#define mmOUT_CLAMP_CONTROL_B_CB                                                0x1a9d
-+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB                                           0x1a9d
-+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB                                           0x1c9d
-+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB                                           0x1e9d
-+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB                                           0x409d
-+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB                                           0x429d
-+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB                                           0x449d
-+#define mmKEY_CONTROL                                                           0x1a53
-+#define mmDCP0_KEY_CONTROL                                                      0x1a53
-+#define mmDCP1_KEY_CONTROL                                                      0x1c53
-+#define mmDCP2_KEY_CONTROL                                                      0x1e53
-+#define mmDCP3_KEY_CONTROL                                                      0x4053
-+#define mmDCP4_KEY_CONTROL                                                      0x4253
-+#define mmDCP5_KEY_CONTROL                                                      0x4453
-+#define mmKEY_RANGE_ALPHA                                                       0x1a54
-+#define mmDCP0_KEY_RANGE_ALPHA                                                  0x1a54
-+#define mmDCP1_KEY_RANGE_ALPHA                                                  0x1c54
-+#define mmDCP2_KEY_RANGE_ALPHA                                                  0x1e54
-+#define mmDCP3_KEY_RANGE_ALPHA                                                  0x4054
-+#define mmDCP4_KEY_RANGE_ALPHA                                                  0x4254
-+#define mmDCP5_KEY_RANGE_ALPHA                                                  0x4454
-+#define mmKEY_RANGE_RED                                                         0x1a55
-+#define mmDCP0_KEY_RANGE_RED                                                    0x1a55
-+#define mmDCP1_KEY_RANGE_RED                                                    0x1c55
-+#define mmDCP2_KEY_RANGE_RED                                                    0x1e55
-+#define mmDCP3_KEY_RANGE_RED                                                    0x4055
-+#define mmDCP4_KEY_RANGE_RED                                                    0x4255
-+#define mmDCP5_KEY_RANGE_RED                                                    0x4455
-+#define mmKEY_RANGE_GREEN                                                       0x1a56
-+#define mmDCP0_KEY_RANGE_GREEN                                                  0x1a56
-+#define mmDCP1_KEY_RANGE_GREEN                                                  0x1c56
-+#define mmDCP2_KEY_RANGE_GREEN                                                  0x1e56
-+#define mmDCP3_KEY_RANGE_GREEN                                                  0x4056
-+#define mmDCP4_KEY_RANGE_GREEN                                                  0x4256
-+#define mmDCP5_KEY_RANGE_GREEN                                                  0x4456
-+#define mmKEY_RANGE_BLUE                                                        0x1a57
-+#define mmDCP0_KEY_RANGE_BLUE                                                   0x1a57
-+#define mmDCP1_KEY_RANGE_BLUE                                                   0x1c57
-+#define mmDCP2_KEY_RANGE_BLUE                                                   0x1e57
-+#define mmDCP3_KEY_RANGE_BLUE                                                   0x4057
-+#define mmDCP4_KEY_RANGE_BLUE                                                   0x4257
-+#define mmDCP5_KEY_RANGE_BLUE                                                   0x4457
-+#define mmDEGAMMA_CONTROL                                                       0x1a58
-+#define mmDCP0_DEGAMMA_CONTROL                                                  0x1a58
-+#define mmDCP1_DEGAMMA_CONTROL                                                  0x1c58
-+#define mmDCP2_DEGAMMA_CONTROL                                                  0x1e58
-+#define mmDCP3_DEGAMMA_CONTROL                                                  0x4058
-+#define mmDCP4_DEGAMMA_CONTROL                                                  0x4258
-+#define mmDCP5_DEGAMMA_CONTROL                                                  0x4458
-+#define mmGAMUT_REMAP_CONTROL                                                   0x1a59
-+#define mmDCP0_GAMUT_REMAP_CONTROL                                              0x1a59
-+#define mmDCP1_GAMUT_REMAP_CONTROL                                              0x1c59
-+#define mmDCP2_GAMUT_REMAP_CONTROL                                              0x1e59
-+#define mmDCP3_GAMUT_REMAP_CONTROL                                              0x4059
-+#define mmDCP4_GAMUT_REMAP_CONTROL                                              0x4259
-+#define mmDCP5_GAMUT_REMAP_CONTROL                                              0x4459
-+#define mmGAMUT_REMAP_C11_C12                                                   0x1a5a
-+#define mmDCP0_GAMUT_REMAP_C11_C12                                              0x1a5a
-+#define mmDCP1_GAMUT_REMAP_C11_C12                                              0x1c5a
-+#define mmDCP2_GAMUT_REMAP_C11_C12                                              0x1e5a
-+#define mmDCP3_GAMUT_REMAP_C11_C12                                              0x405a
-+#define mmDCP4_GAMUT_REMAP_C11_C12                                              0x425a
-+#define mmDCP5_GAMUT_REMAP_C11_C12                                              0x445a
-+#define mmGAMUT_REMAP_C13_C14                                                   0x1a5b
-+#define mmDCP0_GAMUT_REMAP_C13_C14                                              0x1a5b
-+#define mmDCP1_GAMUT_REMAP_C13_C14                                              0x1c5b
-+#define mmDCP2_GAMUT_REMAP_C13_C14                                              0x1e5b
-+#define mmDCP3_GAMUT_REMAP_C13_C14                                              0x405b
-+#define mmDCP4_GAMUT_REMAP_C13_C14                                              0x425b
-+#define mmDCP5_GAMUT_REMAP_C13_C14                                              0x445b
-+#define mmGAMUT_REMAP_C21_C22                                                   0x1a5c
-+#define mmDCP0_GAMUT_REMAP_C21_C22                                              0x1a5c
-+#define mmDCP1_GAMUT_REMAP_C21_C22                                              0x1c5c
-+#define mmDCP2_GAMUT_REMAP_C21_C22                                              0x1e5c
-+#define mmDCP3_GAMUT_REMAP_C21_C22                                              0x405c
-+#define mmDCP4_GAMUT_REMAP_C21_C22                                              0x425c
-+#define mmDCP5_GAMUT_REMAP_C21_C22                                              0x445c
-+#define mmGAMUT_REMAP_C23_C24                                                   0x1a5d
-+#define mmDCP0_GAMUT_REMAP_C23_C24                                              0x1a5d
-+#define mmDCP1_GAMUT_REMAP_C23_C24                                              0x1c5d
-+#define mmDCP2_GAMUT_REMAP_C23_C24                                              0x1e5d
-+#define mmDCP3_GAMUT_REMAP_C23_C24                                              0x405d
-+#define mmDCP4_GAMUT_REMAP_C23_C24                                              0x425d
-+#define mmDCP5_GAMUT_REMAP_C23_C24                                              0x445d
-+#define mmGAMUT_REMAP_C31_C32                                                   0x1a5e
-+#define mmDCP0_GAMUT_REMAP_C31_C32                                              0x1a5e
-+#define mmDCP1_GAMUT_REMAP_C31_C32                                              0x1c5e
-+#define mmDCP2_GAMUT_REMAP_C31_C32                                              0x1e5e
-+#define mmDCP3_GAMUT_REMAP_C31_C32                                              0x405e
-+#define mmDCP4_GAMUT_REMAP_C31_C32                                              0x425e
-+#define mmDCP5_GAMUT_REMAP_C31_C32                                              0x445e
-+#define mmGAMUT_REMAP_C33_C34                                                   0x1a5f
-+#define mmDCP0_GAMUT_REMAP_C33_C34                                              0x1a5f
-+#define mmDCP1_GAMUT_REMAP_C33_C34                                              0x1c5f
-+#define mmDCP2_GAMUT_REMAP_C33_C34                                              0x1e5f
-+#define mmDCP3_GAMUT_REMAP_C33_C34                                              0x405f
-+#define mmDCP4_GAMUT_REMAP_C33_C34                                              0x425f
-+#define mmDCP5_GAMUT_REMAP_C33_C34                                              0x445f
-+#define mmDCP_SPATIAL_DITHER_CNTL                                               0x1a60
-+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL                                          0x1a60
-+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL                                          0x1c60
-+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL                                          0x1e60
-+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL                                          0x4060
-+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL                                          0x4260
-+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL                                          0x4460
-+#define mmDCP_RANDOM_SEEDS                                                      0x1a61
-+#define mmDCP0_DCP_RANDOM_SEEDS                                                 0x1a61
-+#define mmDCP1_DCP_RANDOM_SEEDS                                                 0x1c61
-+#define mmDCP2_DCP_RANDOM_SEEDS                                                 0x1e61
-+#define mmDCP3_DCP_RANDOM_SEEDS                                                 0x4061
-+#define mmDCP4_DCP_RANDOM_SEEDS                                                 0x4261
-+#define mmDCP5_DCP_RANDOM_SEEDS                                                 0x4461
-+#define mmDCP_FP_CONVERTED_FIELD                                                0x1a65
-+#define mmDCP0_DCP_FP_CONVERTED_FIELD                                           0x1a65
-+#define mmDCP1_DCP_FP_CONVERTED_FIELD                                           0x1c65
-+#define mmDCP2_DCP_FP_CONVERTED_FIELD                                           0x1e65
-+#define mmDCP3_DCP_FP_CONVERTED_FIELD                                           0x4065
-+#define mmDCP4_DCP_FP_CONVERTED_FIELD                                           0x4265
-+#define mmDCP5_DCP_FP_CONVERTED_FIELD                                           0x4465
-+#define mmCUR_CONTROL                                                           0x1a66
-+#define mmDCP0_CUR_CONTROL                                                      0x1a66
-+#define mmDCP1_CUR_CONTROL                                                      0x1c66
-+#define mmDCP2_CUR_CONTROL                                                      0x1e66
-+#define mmDCP3_CUR_CONTROL                                                      0x4066
-+#define mmDCP4_CUR_CONTROL                                                      0x4266
-+#define mmDCP5_CUR_CONTROL                                                      0x4466
-+#define mmCUR_SURFACE_ADDRESS                                                   0x1a67
-+#define mmDCP0_CUR_SURFACE_ADDRESS                                              0x1a67
-+#define mmDCP1_CUR_SURFACE_ADDRESS                                              0x1c67
-+#define mmDCP2_CUR_SURFACE_ADDRESS                                              0x1e67
-+#define mmDCP3_CUR_SURFACE_ADDRESS                                              0x4067
-+#define mmDCP4_CUR_SURFACE_ADDRESS                                              0x4267
-+#define mmDCP5_CUR_SURFACE_ADDRESS                                              0x4467
-+#define mmCUR_SIZE                                                              0x1a68
-+#define mmDCP0_CUR_SIZE                                                         0x1a68
-+#define mmDCP1_CUR_SIZE                                                         0x1c68
-+#define mmDCP2_CUR_SIZE                                                         0x1e68
-+#define mmDCP3_CUR_SIZE                                                         0x4068
-+#define mmDCP4_CUR_SIZE                                                         0x4268
-+#define mmDCP5_CUR_SIZE                                                         0x4468
-+#define mmCUR_SURFACE_ADDRESS_HIGH                                              0x1a69
-+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                         0x1a69
-+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                         0x1c69
-+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                         0x1e69
-+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                         0x4069
-+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                         0x4269
-+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                         0x4469
-+#define mmCUR_POSITION                                                          0x1a6a
-+#define mmDCP0_CUR_POSITION                                                     0x1a6a
-+#define mmDCP1_CUR_POSITION                                                     0x1c6a
-+#define mmDCP2_CUR_POSITION                                                     0x1e6a
-+#define mmDCP3_CUR_POSITION                                                     0x406a
-+#define mmDCP4_CUR_POSITION                                                     0x426a
-+#define mmDCP5_CUR_POSITION                                                     0x446a
-+#define mmCUR_HOT_SPOT                                                          0x1a6b
-+#define mmDCP0_CUR_HOT_SPOT                                                     0x1a6b
-+#define mmDCP1_CUR_HOT_SPOT                                                     0x1c6b
-+#define mmDCP2_CUR_HOT_SPOT                                                     0x1e6b
-+#define mmDCP3_CUR_HOT_SPOT                                                     0x406b
-+#define mmDCP4_CUR_HOT_SPOT                                                     0x426b
-+#define mmDCP5_CUR_HOT_SPOT                                                     0x446b
-+#define mmCUR_COLOR1                                                            0x1a6c
-+#define mmDCP0_CUR_COLOR1                                                       0x1a6c
-+#define mmDCP1_CUR_COLOR1                                                       0x1c6c
-+#define mmDCP2_CUR_COLOR1                                                       0x1e6c
-+#define mmDCP3_CUR_COLOR1                                                       0x406c
-+#define mmDCP4_CUR_COLOR1                                                       0x426c
-+#define mmDCP5_CUR_COLOR1                                                       0x446c
-+#define mmCUR_COLOR2                                                            0x1a6d
-+#define mmDCP0_CUR_COLOR2                                                       0x1a6d
-+#define mmDCP1_CUR_COLOR2                                                       0x1c6d
-+#define mmDCP2_CUR_COLOR2                                                       0x1e6d
-+#define mmDCP3_CUR_COLOR2                                                       0x406d
-+#define mmDCP4_CUR_COLOR2                                                       0x426d
-+#define mmDCP5_CUR_COLOR2                                                       0x446d
-+#define mmCUR_UPDATE                                                            0x1a6e
-+#define mmDCP0_CUR_UPDATE                                                       0x1a6e
-+#define mmDCP1_CUR_UPDATE                                                       0x1c6e
-+#define mmDCP2_CUR_UPDATE                                                       0x1e6e
-+#define mmDCP3_CUR_UPDATE                                                       0x406e
-+#define mmDCP4_CUR_UPDATE                                                       0x426e
-+#define mmDCP5_CUR_UPDATE                                                       0x446e
-+#define mmCUR_REQUEST_FILTER_CNTL                                               0x1a99
-+#define mmDCP0_CUR_REQUEST_FILTER_CNTL                                          0x1a99
-+#define mmDCP1_CUR_REQUEST_FILTER_CNTL                                          0x1c99
-+#define mmDCP2_CUR_REQUEST_FILTER_CNTL                                          0x1e99
-+#define mmDCP3_CUR_REQUEST_FILTER_CNTL                                          0x4099
-+#define mmDCP4_CUR_REQUEST_FILTER_CNTL                                          0x4299
-+#define mmDCP5_CUR_REQUEST_FILTER_CNTL                                          0x4499
-+#define mmCUR_STEREO_CONTROL                                                    0x1a9a
-+#define mmDCP0_CUR_STEREO_CONTROL                                               0x1a9a
-+#define mmDCP1_CUR_STEREO_CONTROL                                               0x1c9a
-+#define mmDCP2_CUR_STEREO_CONTROL                                               0x1e9a
-+#define mmDCP3_CUR_STEREO_CONTROL                                               0x409a
-+#define mmDCP4_CUR_STEREO_CONTROL                                               0x429a
-+#define mmDCP5_CUR_STEREO_CONTROL                                               0x449a
-+#define mmDC_LUT_RW_MODE                                                        0x1a78
-+#define mmDCP0_DC_LUT_RW_MODE                                                   0x1a78
-+#define mmDCP1_DC_LUT_RW_MODE                                                   0x1c78
-+#define mmDCP2_DC_LUT_RW_MODE                                                   0x1e78
-+#define mmDCP3_DC_LUT_RW_MODE                                                   0x4078
-+#define mmDCP4_DC_LUT_RW_MODE                                                   0x4278
-+#define mmDCP5_DC_LUT_RW_MODE                                                   0x4478
-+#define mmDC_LUT_RW_INDEX                                                       0x1a79
-+#define mmDCP0_DC_LUT_RW_INDEX                                                  0x1a79
-+#define mmDCP1_DC_LUT_RW_INDEX                                                  0x1c79
-+#define mmDCP2_DC_LUT_RW_INDEX                                                  0x1e79
-+#define mmDCP3_DC_LUT_RW_INDEX                                                  0x4079
-+#define mmDCP4_DC_LUT_RW_INDEX                                                  0x4279
-+#define mmDCP5_DC_LUT_RW_INDEX                                                  0x4479
-+#define mmDC_LUT_SEQ_COLOR                                                      0x1a7a
-+#define mmDCP0_DC_LUT_SEQ_COLOR                                                 0x1a7a
-+#define mmDCP1_DC_LUT_SEQ_COLOR                                                 0x1c7a
-+#define mmDCP2_DC_LUT_SEQ_COLOR                                                 0x1e7a
-+#define mmDCP3_DC_LUT_SEQ_COLOR                                                 0x407a
-+#define mmDCP4_DC_LUT_SEQ_COLOR                                                 0x427a
-+#define mmDCP5_DC_LUT_SEQ_COLOR                                                 0x447a
-+#define mmDC_LUT_PWL_DATA                                                       0x1a7b
-+#define mmDCP0_DC_LUT_PWL_DATA                                                  0x1a7b
-+#define mmDCP1_DC_LUT_PWL_DATA                                                  0x1c7b
-+#define mmDCP2_DC_LUT_PWL_DATA                                                  0x1e7b
-+#define mmDCP3_DC_LUT_PWL_DATA                                                  0x407b
-+#define mmDCP4_DC_LUT_PWL_DATA                                                  0x427b
-+#define mmDCP5_DC_LUT_PWL_DATA                                                  0x447b
-+#define mmDC_LUT_30_COLOR                                                       0x1a7c
-+#define mmDCP0_DC_LUT_30_COLOR                                                  0x1a7c
-+#define mmDCP1_DC_LUT_30_COLOR                                                  0x1c7c
-+#define mmDCP2_DC_LUT_30_COLOR                                                  0x1e7c
-+#define mmDCP3_DC_LUT_30_COLOR                                                  0x407c
-+#define mmDCP4_DC_LUT_30_COLOR                                                  0x427c
-+#define mmDCP5_DC_LUT_30_COLOR                                                  0x447c
-+#define mmDC_LUT_VGA_ACCESS_ENABLE                                              0x1a7d
-+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                         0x1a7d
-+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                         0x1c7d
-+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                         0x1e7d
-+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                         0x407d
-+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                         0x427d
-+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                         0x447d
-+#define mmDC_LUT_WRITE_EN_MASK                                                  0x1a7e
-+#define mmDCP0_DC_LUT_WRITE_EN_MASK                                             0x1a7e
-+#define mmDCP1_DC_LUT_WRITE_EN_MASK                                             0x1c7e
-+#define mmDCP2_DC_LUT_WRITE_EN_MASK                                             0x1e7e
-+#define mmDCP3_DC_LUT_WRITE_EN_MASK                                             0x407e
-+#define mmDCP4_DC_LUT_WRITE_EN_MASK                                             0x427e
-+#define mmDCP5_DC_LUT_WRITE_EN_MASK                                             0x447e
-+#define mmDC_LUT_AUTOFILL                                                       0x1a7f
-+#define mmDCP0_DC_LUT_AUTOFILL                                                  0x1a7f
-+#define mmDCP1_DC_LUT_AUTOFILL                                                  0x1c7f
-+#define mmDCP2_DC_LUT_AUTOFILL                                                  0x1e7f
-+#define mmDCP3_DC_LUT_AUTOFILL                                                  0x407f
-+#define mmDCP4_DC_LUT_AUTOFILL                                                  0x427f
-+#define mmDCP5_DC_LUT_AUTOFILL                                                  0x447f
-+#define mmDC_LUT_CONTROL                                                        0x1a80
-+#define mmDCP0_DC_LUT_CONTROL                                                   0x1a80
-+#define mmDCP1_DC_LUT_CONTROL                                                   0x1c80
-+#define mmDCP2_DC_LUT_CONTROL                                                   0x1e80
-+#define mmDCP3_DC_LUT_CONTROL                                                   0x4080
-+#define mmDCP4_DC_LUT_CONTROL                                                   0x4280
-+#define mmDCP5_DC_LUT_CONTROL                                                   0x4480
-+#define mmDC_LUT_BLACK_OFFSET_BLUE                                              0x1a81
-+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                         0x1a81
-+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                         0x1c81
-+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                         0x1e81
-+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                         0x4081
-+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                         0x4281
-+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                         0x4481
-+#define mmDC_LUT_BLACK_OFFSET_GREEN                                             0x1a82
-+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                        0x1a82
-+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                        0x1c82
-+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                        0x1e82
-+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                        0x4082
-+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                        0x4282
-+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                        0x4482
-+#define mmDC_LUT_BLACK_OFFSET_RED                                               0x1a83
-+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED                                          0x1a83
-+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED                                          0x1c83
-+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED                                          0x1e83
-+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED                                          0x4083
-+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED                                          0x4283
-+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED                                          0x4483
-+#define mmDC_LUT_WHITE_OFFSET_BLUE                                              0x1a84
-+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                         0x1a84
-+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                         0x1c84
-+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                         0x1e84
-+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                         0x4084
-+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                         0x4284
-+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                         0x4484
-+#define mmDC_LUT_WHITE_OFFSET_GREEN                                             0x1a85
-+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                        0x1a85
-+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                        0x1c85
-+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                        0x1e85
-+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                        0x4085
-+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                        0x4285
-+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                        0x4485
-+#define mmDC_LUT_WHITE_OFFSET_RED                                               0x1a86
-+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED                                          0x1a86
-+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED                                          0x1c86
-+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED                                          0x1e86
-+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED                                          0x4086
-+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED                                          0x4286
-+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED                                          0x4486
-+#define mmDCP_CRC_CONTROL                                                       0x1a87
-+#define mmDCP0_DCP_CRC_CONTROL                                                  0x1a87
-+#define mmDCP1_DCP_CRC_CONTROL                                                  0x1c87
-+#define mmDCP2_DCP_CRC_CONTROL                                                  0x1e87
-+#define mmDCP3_DCP_CRC_CONTROL                                                  0x4087
-+#define mmDCP4_DCP_CRC_CONTROL                                                  0x4287
-+#define mmDCP5_DCP_CRC_CONTROL                                                  0x4487
-+#define mmDCP_CRC_MASK                                                          0x1a88
-+#define mmDCP0_DCP_CRC_MASK                                                     0x1a88
-+#define mmDCP1_DCP_CRC_MASK                                                     0x1c88
-+#define mmDCP2_DCP_CRC_MASK                                                     0x1e88
-+#define mmDCP3_DCP_CRC_MASK                                                     0x4088
-+#define mmDCP4_DCP_CRC_MASK                                                     0x4288
-+#define mmDCP5_DCP_CRC_MASK                                                     0x4488
-+#define mmDCP_CRC_CURRENT                                                       0x1a89
-+#define mmDCP0_DCP_CRC_CURRENT                                                  0x1a89
-+#define mmDCP1_DCP_CRC_CURRENT                                                  0x1c89
-+#define mmDCP2_DCP_CRC_CURRENT                                                  0x1e89
-+#define mmDCP3_DCP_CRC_CURRENT                                                  0x4089
-+#define mmDCP4_DCP_CRC_CURRENT                                                  0x4289
-+#define mmDCP5_DCP_CRC_CURRENT                                                  0x4489
-+#define mmDVMM_PTE_CONTROL                                                      0x1a8a
-+#define mmDCP0_DVMM_PTE_CONTROL                                                 0x1a8a
-+#define mmDCP1_DVMM_PTE_CONTROL                                                 0x1c8a
-+#define mmDCP2_DVMM_PTE_CONTROL                                                 0x1e8a
-+#define mmDCP3_DVMM_PTE_CONTROL                                                 0x408a
-+#define mmDCP4_DVMM_PTE_CONTROL                                                 0x428a
-+#define mmDCP5_DVMM_PTE_CONTROL                                                 0x448a
-+#define mmDCP_CRC_LAST                                                          0x1a8b
-+#define mmDCP0_DCP_CRC_LAST                                                     0x1a8b
-+#define mmDCP1_DCP_CRC_LAST                                                     0x1c8b
-+#define mmDCP2_DCP_CRC_LAST                                                     0x1e8b
-+#define mmDCP3_DCP_CRC_LAST                                                     0x408b
-+#define mmDCP4_DCP_CRC_LAST                                                     0x428b
-+#define mmDCP5_DCP_CRC_LAST                                                     0x448b
-+#define mmDCP_DEBUG                                                             0x1a8d
-+#define mmDCP0_DCP_DEBUG                                                        0x1a8d
-+#define mmDCP1_DCP_DEBUG                                                        0x1c8d
-+#define mmDCP2_DCP_DEBUG                                                        0x1e8d
-+#define mmDCP3_DCP_DEBUG                                                        0x408d
-+#define mmDCP4_DCP_DEBUG                                                        0x428d
-+#define mmDCP5_DCP_DEBUG                                                        0x448d
-+#define mmGRPH_FLIP_RATE_CNTL                                                   0x1a8e
-+#define mmDCP0_GRPH_FLIP_RATE_CNTL                                              0x1a8e
-+#define mmDCP1_GRPH_FLIP_RATE_CNTL                                              0x1c8e
-+#define mmDCP2_GRPH_FLIP_RATE_CNTL                                              0x1e8e
-+#define mmDCP3_GRPH_FLIP_RATE_CNTL                                              0x408e
-+#define mmDCP4_GRPH_FLIP_RATE_CNTL                                              0x428e
-+#define mmDCP5_GRPH_FLIP_RATE_CNTL                                              0x448e
-+#define mmDCP_GSL_CONTROL                                                       0x1a90
-+#define mmDCP0_DCP_GSL_CONTROL                                                  0x1a90
-+#define mmDCP1_DCP_GSL_CONTROL                                                  0x1c90
-+#define mmDCP2_DCP_GSL_CONTROL                                                  0x1e90
-+#define mmDCP3_DCP_GSL_CONTROL                                                  0x4090
-+#define mmDCP4_DCP_GSL_CONTROL                                                  0x4290
-+#define mmDCP5_DCP_GSL_CONTROL                                                  0x4490
-+#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x1a91
-+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1a91
-+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1c91
-+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1e91
-+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4091
-+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4291
-+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4491
-+#define mmDCP_DEBUG_SG                                                          0x1a92
-+#define mmDCP0_DCP_DEBUG_SG                                                     0x1a92
-+#define mmDCP1_DCP_DEBUG_SG                                                     0x1c92
-+#define mmDCP2_DCP_DEBUG_SG                                                     0x1e92
-+#define mmDCP3_DCP_DEBUG_SG                                                     0x4092
-+#define mmDCP4_DCP_DEBUG_SG                                                     0x4292
-+#define mmDCP5_DCP_DEBUG_SG                                                     0x4492
-+#define mmDCP_DEBUG_SG2                                                         0x1a94
-+#define mmDCP0_DCP_DEBUG_SG2                                                    0x1a94
-+#define mmDCP1_DCP_DEBUG_SG2                                                    0x1c94
-+#define mmDCP2_DCP_DEBUG_SG2                                                    0x1e94
-+#define mmDCP3_DCP_DEBUG_SG2                                                    0x4094
-+#define mmDCP4_DCP_DEBUG_SG2                                                    0x4294
-+#define mmDCP5_DCP_DEBUG_SG2                                                    0x4494
-+#define mmDCP_DVMM_DEBUG                                                        0x1a93
-+#define mmDCP0_DCP_DVMM_DEBUG                                                   0x1a93
-+#define mmDCP1_DCP_DVMM_DEBUG                                                   0x1c93
-+#define mmDCP2_DCP_DVMM_DEBUG                                                   0x1e93
-+#define mmDCP3_DCP_DVMM_DEBUG                                                   0x4093
-+#define mmDCP4_DCP_DVMM_DEBUG                                                   0x4293
-+#define mmDCP5_DCP_DVMM_DEBUG                                                   0x4493
-+#define mmDCP_TEST_DEBUG_INDEX                                                  0x1a95
-+#define mmDCP0_DCP_TEST_DEBUG_INDEX                                             0x1a95
-+#define mmDCP1_DCP_TEST_DEBUG_INDEX                                             0x1c95
-+#define mmDCP2_DCP_TEST_DEBUG_INDEX                                             0x1e95
-+#define mmDCP3_DCP_TEST_DEBUG_INDEX                                             0x4095
-+#define mmDCP4_DCP_TEST_DEBUG_INDEX                                             0x4295
-+#define mmDCP5_DCP_TEST_DEBUG_INDEX                                             0x4495
-+#define mmDCP_TEST_DEBUG_DATA                                                   0x1a96
-+#define mmDCP0_DCP_TEST_DEBUG_DATA                                              0x1a96
-+#define mmDCP1_DCP_TEST_DEBUG_DATA                                              0x1c96
-+#define mmDCP2_DCP_TEST_DEBUG_DATA                                              0x1e96
-+#define mmDCP3_DCP_TEST_DEBUG_DATA                                              0x4096
-+#define mmDCP4_DCP_TEST_DEBUG_DATA                                              0x4296
-+#define mmDCP5_DCP_TEST_DEBUG_DATA                                              0x4496
-+#define mmGRPH_STEREOSYNC_FLIP                                                  0x1a97
-+#define mmDCP0_GRPH_STEREOSYNC_FLIP                                             0x1a97
-+#define mmDCP1_GRPH_STEREOSYNC_FLIP                                             0x1c97
-+#define mmDCP2_GRPH_STEREOSYNC_FLIP                                             0x1e97
-+#define mmDCP3_GRPH_STEREOSYNC_FLIP                                             0x4097
-+#define mmDCP4_GRPH_STEREOSYNC_FLIP                                             0x4297
-+#define mmDCP5_GRPH_STEREOSYNC_FLIP                                             0x4497
-+#define mmDCP_DEBUG2                                                            0x1a98
-+#define mmDCP0_DCP_DEBUG2                                                       0x1a98
-+#define mmDCP1_DCP_DEBUG2                                                       0x1c98
-+#define mmDCP2_DCP_DEBUG2                                                       0x1e98
-+#define mmDCP3_DCP_DEBUG2                                                       0x4098
-+#define mmDCP4_DCP_DEBUG2                                                       0x4298
-+#define mmDCP5_DCP_DEBUG2                                                       0x4498
-+#define mmHW_ROTATION                                                           0x1a9e
-+#define mmDCP0_HW_ROTATION                                                      0x1a9e
-+#define mmDCP1_HW_ROTATION                                                      0x1c9e
-+#define mmDCP2_HW_ROTATION                                                      0x1e9e
-+#define mmDCP3_HW_ROTATION                                                      0x409e
-+#define mmDCP4_HW_ROTATION                                                      0x429e
-+#define mmDCP5_HW_ROTATION                                                      0x449e
-+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                    0x1a9f
-+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1a9f
-+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1c9f
-+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1e9f
-+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x409f
-+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x429f
-+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x449f
-+#define mmREGAMMA_CONTROL                                                       0x1aa0
-+#define mmDCP0_REGAMMA_CONTROL                                                  0x1aa0
-+#define mmDCP1_REGAMMA_CONTROL                                                  0x1ca0
-+#define mmDCP2_REGAMMA_CONTROL                                                  0x1ea0
-+#define mmDCP3_REGAMMA_CONTROL                                                  0x40a0
-+#define mmDCP4_REGAMMA_CONTROL                                                  0x42a0
-+#define mmDCP5_REGAMMA_CONTROL                                                  0x44a0
-+#define mmREGAMMA_LUT_INDEX                                                     0x1aa1
-+#define mmDCP0_REGAMMA_LUT_INDEX                                                0x1aa1
-+#define mmDCP1_REGAMMA_LUT_INDEX                                                0x1ca1
-+#define mmDCP2_REGAMMA_LUT_INDEX                                                0x1ea1
-+#define mmDCP3_REGAMMA_LUT_INDEX                                                0x40a1
-+#define mmDCP4_REGAMMA_LUT_INDEX                                                0x42a1
-+#define mmDCP5_REGAMMA_LUT_INDEX                                                0x44a1
-+#define mmREGAMMA_LUT_DATA                                                      0x1aa2
-+#define mmDCP0_REGAMMA_LUT_DATA                                                 0x1aa2
-+#define mmDCP1_REGAMMA_LUT_DATA                                                 0x1ca2
-+#define mmDCP2_REGAMMA_LUT_DATA                                                 0x1ea2
-+#define mmDCP3_REGAMMA_LUT_DATA                                                 0x40a2
-+#define mmDCP4_REGAMMA_LUT_DATA                                                 0x42a2
-+#define mmDCP5_REGAMMA_LUT_DATA                                                 0x44a2
-+#define mmREGAMMA_LUT_WRITE_EN_MASK                                             0x1aa3
-+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                        0x1aa3
-+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ca3
-+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ea3
-+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                        0x40a3
-+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                        0x42a3
-+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                        0x44a3
-+#define mmREGAMMA_CNTLA_START_CNTL                                              0x1aa4
-+#define mmDCP0_REGAMMA_CNTLA_START_CNTL                                         0x1aa4
-+#define mmDCP1_REGAMMA_CNTLA_START_CNTL                                         0x1ca4
-+#define mmDCP2_REGAMMA_CNTLA_START_CNTL                                         0x1ea4
-+#define mmDCP3_REGAMMA_CNTLA_START_CNTL                                         0x40a4
-+#define mmDCP4_REGAMMA_CNTLA_START_CNTL                                         0x42a4
-+#define mmDCP5_REGAMMA_CNTLA_START_CNTL                                         0x44a4
-+#define mmREGAMMA_CNTLA_SLOPE_CNTL                                              0x1aa5
-+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1aa5
-+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ca5
-+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ea5
-+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                         0x40a5
-+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                         0x42a5
-+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                         0x44a5
-+#define mmREGAMMA_CNTLA_END_CNTL1                                               0x1aa6
-+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1                                          0x1aa6
-+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1                                          0x1ca6
-+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1                                          0x1ea6
-+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1                                          0x40a6
-+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1                                          0x42a6
-+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1                                          0x44a6
-+#define mmREGAMMA_CNTLA_END_CNTL2                                               0x1aa7
-+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2                                          0x1aa7
-+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2                                          0x1ca7
-+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2                                          0x1ea7
-+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2                                          0x40a7
-+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2                                          0x42a7
-+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2                                          0x44a7
-+#define mmREGAMMA_CNTLA_REGION_0_1                                              0x1aa8
-+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1                                         0x1aa8
-+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1                                         0x1ca8
-+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1                                         0x1ea8
-+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1                                         0x40a8
-+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1                                         0x42a8
-+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1                                         0x44a8
-+#define mmREGAMMA_CNTLA_REGION_2_3                                              0x1aa9
-+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3                                         0x1aa9
-+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3                                         0x1ca9
-+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3                                         0x1ea9
-+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3                                         0x40a9
-+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3                                         0x42a9
-+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3                                         0x44a9
-+#define mmREGAMMA_CNTLA_REGION_4_5                                              0x1aaa
-+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5                                         0x1aaa
-+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5                                         0x1caa
-+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5                                         0x1eaa
-+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5                                         0x40aa
-+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5                                         0x42aa
-+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5                                         0x44aa
-+#define mmREGAMMA_CNTLA_REGION_6_7                                              0x1aab
-+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7                                         0x1aab
-+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7                                         0x1cab
-+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7                                         0x1eab
-+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7                                         0x40ab
-+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7                                         0x42ab
-+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7                                         0x44ab
-+#define mmREGAMMA_CNTLA_REGION_8_9                                              0x1aac
-+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9                                         0x1aac
-+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9                                         0x1cac
-+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9                                         0x1eac
-+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9                                         0x40ac
-+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9                                         0x42ac
-+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9                                         0x44ac
-+#define mmREGAMMA_CNTLA_REGION_10_11                                            0x1aad
-+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11                                       0x1aad
-+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11                                       0x1cad
-+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11                                       0x1ead
-+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11                                       0x40ad
-+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11                                       0x42ad
-+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11                                       0x44ad
-+#define mmREGAMMA_CNTLA_REGION_12_13                                            0x1aae
-+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13                                       0x1aae
-+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13                                       0x1cae
-+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13                                       0x1eae
-+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13                                       0x40ae
-+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13                                       0x42ae
-+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13                                       0x44ae
-+#define mmREGAMMA_CNTLA_REGION_14_15                                            0x1aaf
-+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15                                       0x1aaf
-+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15                                       0x1caf
-+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15                                       0x1eaf
-+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15                                       0x40af
-+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15                                       0x42af
-+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15                                       0x44af
-+#define mmREGAMMA_CNTLB_START_CNTL                                              0x1ab0
-+#define mmDCP0_REGAMMA_CNTLB_START_CNTL                                         0x1ab0
-+#define mmDCP1_REGAMMA_CNTLB_START_CNTL                                         0x1cb0
-+#define mmDCP2_REGAMMA_CNTLB_START_CNTL                                         0x1eb0
-+#define mmDCP3_REGAMMA_CNTLB_START_CNTL                                         0x40b0
-+#define mmDCP4_REGAMMA_CNTLB_START_CNTL                                         0x42b0
-+#define mmDCP5_REGAMMA_CNTLB_START_CNTL                                         0x44b0
-+#define mmREGAMMA_CNTLB_SLOPE_CNTL                                              0x1ab1
-+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1ab1
-+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1cb1
-+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1eb1
-+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                         0x40b1
-+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                         0x42b1
-+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                         0x44b1
-+#define mmREGAMMA_CNTLB_END_CNTL1                                               0x1ab2
-+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1                                          0x1ab2
-+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1                                          0x1cb2
-+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1                                          0x1eb2
-+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1                                          0x40b2
-+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1                                          0x42b2
-+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1                                          0x44b2
-+#define mmREGAMMA_CNTLB_END_CNTL2                                               0x1ab3
-+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2                                          0x1ab3
-+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2                                          0x1cb3
-+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2                                          0x1eb3
-+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2                                          0x40b3
-+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2                                          0x42b3
-+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2                                          0x44b3
-+#define mmREGAMMA_CNTLB_REGION_0_1                                              0x1ab4
-+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1                                         0x1ab4
-+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1                                         0x1cb4
-+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1                                         0x1eb4
-+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1                                         0x40b4
-+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1                                         0x42b4
-+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1                                         0x44b4
-+#define mmREGAMMA_CNTLB_REGION_2_3                                              0x1ab5
-+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3                                         0x1ab5
-+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3                                         0x1cb5
-+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3                                         0x1eb5
-+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3                                         0x40b5
-+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3                                         0x42b5
-+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3                                         0x44b5
-+#define mmREGAMMA_CNTLB_REGION_4_5                                              0x1ab6
-+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5                                         0x1ab6
-+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5                                         0x1cb6
-+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5                                         0x1eb6
-+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5                                         0x40b6
-+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5                                         0x42b6
-+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5                                         0x44b6
-+#define mmREGAMMA_CNTLB_REGION_6_7                                              0x1ab7
-+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7                                         0x1ab7
-+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7                                         0x1cb7
-+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7                                         0x1eb7
-+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7                                         0x40b7
-+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7                                         0x42b7
-+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7                                         0x44b7
-+#define mmREGAMMA_CNTLB_REGION_8_9                                              0x1ab8
-+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9                                         0x1ab8
-+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9                                         0x1cb8
-+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9                                         0x1eb8
-+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9                                         0x40b8
-+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9                                         0x42b8
-+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9                                         0x44b8
-+#define mmREGAMMA_CNTLB_REGION_10_11                                            0x1ab9
-+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11                                       0x1ab9
-+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11                                       0x1cb9
-+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11                                       0x1eb9
-+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11                                       0x40b9
-+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11                                       0x42b9
-+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11                                       0x44b9
-+#define mmREGAMMA_CNTLB_REGION_12_13                                            0x1aba
-+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13                                       0x1aba
-+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13                                       0x1cba
-+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13                                       0x1eba
-+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13                                       0x40ba
-+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13                                       0x42ba
-+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13                                       0x44ba
-+#define mmREGAMMA_CNTLB_REGION_14_15                                            0x1abb
-+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15                                       0x1abb
-+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15                                       0x1cbb
-+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15                                       0x1ebb
-+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15                                       0x40bb
-+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15                                       0x42bb
-+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15                                       0x44bb
-+#define mmALPHA_CONTROL                                                         0x1abc
-+#define mmDCP0_ALPHA_CONTROL                                                    0x1abc
-+#define mmDCP1_ALPHA_CONTROL                                                    0x1cbc
-+#define mmDCP2_ALPHA_CONTROL                                                    0x1ebc
-+#define mmDCP3_ALPHA_CONTROL                                                    0x40bc
-+#define mmDCP4_ALPHA_CONTROL                                                    0x42bc
-+#define mmDCP5_ALPHA_CONTROL                                                    0x44bc
-+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                    0x1abd
-+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1abd
-+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1cbd
-+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1ebd
-+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x40bd
-+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x42bd
-+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x44bd
-+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                               0x1abe
-+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1abe
-+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1cbe
-+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1ebe
-+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x40be
-+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x42be
-+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x44be
-+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                  0x1abf
-+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1abf
-+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1cbf
-+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1ebf
-+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x40bf
-+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x42bf
-+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x44bf
-+#define mmGRPH_SURFACE_COUNTER_CONTROL                                          0x1a0f
-+#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL                                     0x1a0f
-+#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL                                     0x1c0f
-+#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL                                     0x1e0f
-+#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL                                     0x400f
-+#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL                                     0x420f
-+#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL                                     0x440f
-+#define mmGRPH_SURFACE_COUNTER_OUTPUT                                           0x1a1d
-+#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1a1d
-+#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1c1d
-+#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1e1d
-+#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT                                      0x401d
-+#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT                                      0x421d
-+#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT                                      0x441d
-+#define mmDIG_FE_CNTL                                                           0x4a00
-+#define mmDIG0_DIG_FE_CNTL                                                      0x4a00
-+#define mmDIG1_DIG_FE_CNTL                                                      0x4b00
-+#define mmDIG2_DIG_FE_CNTL                                                      0x4c00
-+#define mmDIG3_DIG_FE_CNTL                                                      0x4d00
-+#define mmDIG4_DIG_FE_CNTL                                                      0x4e00
-+#define mmDIG5_DIG_FE_CNTL                                                      0x4f00
-+#define mmDIG6_DIG_FE_CNTL                                                      0x5400
-+#define mmDIG7_DIG_FE_CNTL                                                      0x5600
-+#define mmDIG8_DIG_FE_CNTL                                                      0x5700
-+#define mmDIG_OUTPUT_CRC_CNTL                                                   0x4a01
-+#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                              0x4a01
-+#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                              0x4b01
-+#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                              0x4c01
-+#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                              0x4d01
-+#define mmDIG4_DIG_OUTPUT_CRC_CNTL                                              0x4e01
-+#define mmDIG5_DIG_OUTPUT_CRC_CNTL                                              0x4f01
-+#define mmDIG6_DIG_OUTPUT_CRC_CNTL                                              0x5401
-+#define mmDIG7_DIG_OUTPUT_CRC_CNTL                                              0x5601
-+#define mmDIG8_DIG_OUTPUT_CRC_CNTL                                              0x5701
-+#define mmDIG_OUTPUT_CRC_RESULT                                                 0x4a02
-+#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                            0x4a02
-+#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                            0x4b02
-+#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                            0x4c02
-+#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                            0x4d02
-+#define mmDIG4_DIG_OUTPUT_CRC_RESULT                                            0x4e02
-+#define mmDIG5_DIG_OUTPUT_CRC_RESULT                                            0x4f02
-+#define mmDIG6_DIG_OUTPUT_CRC_RESULT                                            0x5402
-+#define mmDIG7_DIG_OUTPUT_CRC_RESULT                                            0x5602
-+#define mmDIG8_DIG_OUTPUT_CRC_RESULT                                            0x5702
-+#define mmDIG_CLOCK_PATTERN                                                     0x4a03
-+#define mmDIG0_DIG_CLOCK_PATTERN                                                0x4a03
-+#define mmDIG1_DIG_CLOCK_PATTERN                                                0x4b03
-+#define mmDIG2_DIG_CLOCK_PATTERN                                                0x4c03
-+#define mmDIG3_DIG_CLOCK_PATTERN                                                0x4d03
-+#define mmDIG4_DIG_CLOCK_PATTERN                                                0x4e03
-+#define mmDIG5_DIG_CLOCK_PATTERN                                                0x4f03
-+#define mmDIG6_DIG_CLOCK_PATTERN                                                0x5403
-+#define mmDIG7_DIG_CLOCK_PATTERN                                                0x5603
-+#define mmDIG8_DIG_CLOCK_PATTERN                                                0x5703
-+#define mmDIG_TEST_PATTERN                                                      0x4a04
-+#define mmDIG0_DIG_TEST_PATTERN                                                 0x4a04
-+#define mmDIG1_DIG_TEST_PATTERN                                                 0x4b04
-+#define mmDIG2_DIG_TEST_PATTERN                                                 0x4c04
-+#define mmDIG3_DIG_TEST_PATTERN                                                 0x4d04
-+#define mmDIG4_DIG_TEST_PATTERN                                                 0x4e04
-+#define mmDIG5_DIG_TEST_PATTERN                                                 0x4f04
-+#define mmDIG6_DIG_TEST_PATTERN                                                 0x5404
-+#define mmDIG7_DIG_TEST_PATTERN                                                 0x5604
-+#define mmDIG8_DIG_TEST_PATTERN                                                 0x5704
-+#define mmDIG_RANDOM_PATTERN_SEED                                               0x4a05
-+#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                          0x4a05
-+#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                          0x4b05
-+#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                          0x4c05
-+#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                          0x4d05
-+#define mmDIG4_DIG_RANDOM_PATTERN_SEED                                          0x4e05
-+#define mmDIG5_DIG_RANDOM_PATTERN_SEED                                          0x4f05
-+#define mmDIG6_DIG_RANDOM_PATTERN_SEED                                          0x5405
-+#define mmDIG7_DIG_RANDOM_PATTERN_SEED                                          0x5605
-+#define mmDIG8_DIG_RANDOM_PATTERN_SEED                                          0x5705
-+#define mmDIG_FIFO_STATUS                                                       0x4a06
-+#define mmDIG0_DIG_FIFO_STATUS                                                  0x4a06
-+#define mmDIG1_DIG_FIFO_STATUS                                                  0x4b06
-+#define mmDIG2_DIG_FIFO_STATUS                                                  0x4c06
-+#define mmDIG3_DIG_FIFO_STATUS                                                  0x4d06
-+#define mmDIG4_DIG_FIFO_STATUS                                                  0x4e06
-+#define mmDIG5_DIG_FIFO_STATUS                                                  0x4f06
-+#define mmDIG6_DIG_FIFO_STATUS                                                  0x5406
-+#define mmDIG7_DIG_FIFO_STATUS                                                  0x5606
-+#define mmDIG8_DIG_FIFO_STATUS                                                  0x5706
-+#define mmDIG_DISPCLK_SWITCH_CNTL                                               0x4a07
-+#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL                                          0x4a07
-+#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL                                          0x4b07
-+#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL                                          0x4c07
-+#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL                                          0x4d07
-+#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL                                          0x4e07
-+#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL                                          0x4f07
-+#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL                                          0x5407
-+#define mmDIG7_DIG_DISPCLK_SWITCH_CNTL                                          0x5607
-+#define mmDIG8_DIG_DISPCLK_SWITCH_CNTL                                          0x5707
-+#define mmDIG_DISPCLK_SWITCH_STATUS                                             0x4a08
-+#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS                                        0x4a08
-+#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS                                        0x4b08
-+#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS                                        0x4c08
-+#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS                                        0x4d08
-+#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS                                        0x4e08
-+#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS                                        0x4f08
-+#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS                                        0x5408
-+#define mmDIG7_DIG_DISPCLK_SWITCH_STATUS                                        0x5608
-+#define mmDIG8_DIG_DISPCLK_SWITCH_STATUS                                        0x5708
-+#define mmHDMI_CONTROL                                                          0x4a09
-+#define mmDIG0_HDMI_CONTROL                                                     0x4a09
-+#define mmDIG1_HDMI_CONTROL                                                     0x4b09
-+#define mmDIG2_HDMI_CONTROL                                                     0x4c09
-+#define mmDIG3_HDMI_CONTROL                                                     0x4d09
-+#define mmDIG4_HDMI_CONTROL                                                     0x4e09
-+#define mmDIG5_HDMI_CONTROL                                                     0x4f09
-+#define mmDIG6_HDMI_CONTROL                                                     0x5409
-+#define mmDIG7_HDMI_CONTROL                                                     0x5609
-+#define mmDIG8_HDMI_CONTROL                                                     0x5709
-+#define mmHDMI_STATUS                                                           0x4a0a
-+#define mmDIG0_HDMI_STATUS                                                      0x4a0a
-+#define mmDIG1_HDMI_STATUS                                                      0x4b0a
-+#define mmDIG2_HDMI_STATUS                                                      0x4c0a
-+#define mmDIG3_HDMI_STATUS                                                      0x4d0a
-+#define mmDIG4_HDMI_STATUS                                                      0x4e0a
-+#define mmDIG5_HDMI_STATUS                                                      0x4f0a
-+#define mmDIG6_HDMI_STATUS                                                      0x540a
-+#define mmDIG7_HDMI_STATUS                                                      0x560a
-+#define mmDIG8_HDMI_STATUS                                                      0x570a
-+#define mmHDMI_AUDIO_PACKET_CONTROL                                             0x4a0b
-+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                        0x4a0b
-+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                        0x4b0b
-+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                        0x4c0b
-+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                        0x4d0b
-+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                        0x4e0b
-+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                        0x4f0b
-+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                        0x540b
-+#define mmDIG7_HDMI_AUDIO_PACKET_CONTROL                                        0x560b
-+#define mmDIG8_HDMI_AUDIO_PACKET_CONTROL                                        0x570b
-+#define mmHDMI_ACR_PACKET_CONTROL                                               0x4a0c
-+#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                          0x4a0c
-+#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                          0x4b0c
-+#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                          0x4c0c
-+#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                          0x4d0c
-+#define mmDIG4_HDMI_ACR_PACKET_CONTROL                                          0x4e0c
-+#define mmDIG5_HDMI_ACR_PACKET_CONTROL                                          0x4f0c
-+#define mmDIG6_HDMI_ACR_PACKET_CONTROL                                          0x540c
-+#define mmDIG7_HDMI_ACR_PACKET_CONTROL                                          0x560c
-+#define mmDIG8_HDMI_ACR_PACKET_CONTROL                                          0x570c
-+#define mmHDMI_VBI_PACKET_CONTROL                                               0x4a0d
-+#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                          0x4a0d
-+#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                          0x4b0d
-+#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                          0x4c0d
-+#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                          0x4d0d
-+#define mmDIG4_HDMI_VBI_PACKET_CONTROL                                          0x4e0d
-+#define mmDIG5_HDMI_VBI_PACKET_CONTROL                                          0x4f0d
-+#define mmDIG6_HDMI_VBI_PACKET_CONTROL                                          0x540d
-+#define mmDIG7_HDMI_VBI_PACKET_CONTROL                                          0x560d
-+#define mmDIG8_HDMI_VBI_PACKET_CONTROL                                          0x570d
-+#define mmHDMI_INFOFRAME_CONTROL0                                               0x4a0e
-+#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                          0x4a0e
-+#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                          0x4b0e
-+#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                          0x4c0e
-+#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                          0x4d0e
-+#define mmDIG4_HDMI_INFOFRAME_CONTROL0                                          0x4e0e
-+#define mmDIG5_HDMI_INFOFRAME_CONTROL0                                          0x4f0e
-+#define mmDIG6_HDMI_INFOFRAME_CONTROL0                                          0x540e
-+#define mmDIG7_HDMI_INFOFRAME_CONTROL0                                          0x560e
-+#define mmDIG8_HDMI_INFOFRAME_CONTROL0                                          0x570e
-+#define mmHDMI_INFOFRAME_CONTROL1                                               0x4a0f
-+#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                          0x4a0f
-+#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                          0x4b0f
-+#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                          0x4c0f
-+#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                          0x4d0f
-+#define mmDIG4_HDMI_INFOFRAME_CONTROL1                                          0x4e0f
-+#define mmDIG5_HDMI_INFOFRAME_CONTROL1                                          0x4f0f
-+#define mmDIG6_HDMI_INFOFRAME_CONTROL1                                          0x540f
-+#define mmDIG7_HDMI_INFOFRAME_CONTROL1                                          0x560f
-+#define mmDIG8_HDMI_INFOFRAME_CONTROL1                                          0x570f
-+#define mmHDMI_GENERIC_PACKET_CONTROL0                                          0x4a10
-+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                     0x4a10
-+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                     0x4b10
-+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                     0x4c10
-+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                     0x4d10
-+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                     0x4e10
-+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                     0x4f10
-+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                     0x5410
-+#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0                                     0x5610
-+#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0                                     0x5710
-+#define mmAFMT_INTERRUPT_STATUS                                                 0x4a11
-+#define mmDIG0_AFMT_INTERRUPT_STATUS                                            0x4a11
-+#define mmDIG1_AFMT_INTERRUPT_STATUS                                            0x4b11
-+#define mmDIG2_AFMT_INTERRUPT_STATUS                                            0x4c11
-+#define mmDIG3_AFMT_INTERRUPT_STATUS                                            0x4d11
-+#define mmDIG4_AFMT_INTERRUPT_STATUS                                            0x4e11
-+#define mmDIG5_AFMT_INTERRUPT_STATUS                                            0x4f11
-+#define mmDIG6_AFMT_INTERRUPT_STATUS                                            0x5411
-+#define mmDIG7_AFMT_INTERRUPT_STATUS                                            0x5611
-+#define mmDIG8_AFMT_INTERRUPT_STATUS                                            0x5711
-+#define mmHDMI_GC                                                               0x4a13
-+#define mmDIG0_HDMI_GC                                                          0x4a13
-+#define mmDIG1_HDMI_GC                                                          0x4b13
-+#define mmDIG2_HDMI_GC                                                          0x4c13
-+#define mmDIG3_HDMI_GC                                                          0x4d13
-+#define mmDIG4_HDMI_GC                                                          0x4e13
-+#define mmDIG5_HDMI_GC                                                          0x4f13
-+#define mmDIG6_HDMI_GC                                                          0x5413
-+#define mmDIG7_HDMI_GC                                                          0x5613
-+#define mmDIG8_HDMI_GC                                                          0x5713
-+#define mmAFMT_AUDIO_PACKET_CONTROL2                                            0x4a14
-+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                       0x4a14
-+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                       0x4b14
-+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                       0x4c14
-+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                       0x4d14
-+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                       0x4e14
-+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                       0x4f14
-+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                       0x5414
-+#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2                                       0x5614
-+#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2                                       0x5714
-+#define mmAFMT_ISRC1_0                                                          0x4a15
-+#define mmDIG0_AFMT_ISRC1_0                                                     0x4a15
-+#define mmDIG1_AFMT_ISRC1_0                                                     0x4b15
-+#define mmDIG2_AFMT_ISRC1_0                                                     0x4c15
-+#define mmDIG3_AFMT_ISRC1_0                                                     0x4d15
-+#define mmDIG4_AFMT_ISRC1_0                                                     0x4e15
-+#define mmDIG5_AFMT_ISRC1_0                                                     0x4f15
-+#define mmDIG6_AFMT_ISRC1_0                                                     0x5415
-+#define mmDIG7_AFMT_ISRC1_0                                                     0x5615
-+#define mmDIG8_AFMT_ISRC1_0                                                     0x5715
-+#define mmAFMT_ISRC1_1                                                          0x4a16
-+#define mmDIG0_AFMT_ISRC1_1                                                     0x4a16
-+#define mmDIG1_AFMT_ISRC1_1                                                     0x4b16
-+#define mmDIG2_AFMT_ISRC1_1                                                     0x4c16
-+#define mmDIG3_AFMT_ISRC1_1                                                     0x4d16
-+#define mmDIG4_AFMT_ISRC1_1                                                     0x4e16
-+#define mmDIG5_AFMT_ISRC1_1                                                     0x4f16
-+#define mmDIG6_AFMT_ISRC1_1                                                     0x5416
-+#define mmDIG7_AFMT_ISRC1_1                                                     0x5616
-+#define mmDIG8_AFMT_ISRC1_1                                                     0x5716
-+#define mmAFMT_ISRC1_2                                                          0x4a17
-+#define mmDIG0_AFMT_ISRC1_2                                                     0x4a17
-+#define mmDIG1_AFMT_ISRC1_2                                                     0x4b17
-+#define mmDIG2_AFMT_ISRC1_2                                                     0x4c17
-+#define mmDIG3_AFMT_ISRC1_2                                                     0x4d17
-+#define mmDIG4_AFMT_ISRC1_2                                                     0x4e17
-+#define mmDIG5_AFMT_ISRC1_2                                                     0x4f17
-+#define mmDIG6_AFMT_ISRC1_2                                                     0x5417
-+#define mmDIG7_AFMT_ISRC1_2                                                     0x5617
-+#define mmDIG8_AFMT_ISRC1_2                                                     0x5717
-+#define mmAFMT_ISRC1_3                                                          0x4a18
-+#define mmDIG0_AFMT_ISRC1_3                                                     0x4a18
-+#define mmDIG1_AFMT_ISRC1_3                                                     0x4b18
-+#define mmDIG2_AFMT_ISRC1_3                                                     0x4c18
-+#define mmDIG3_AFMT_ISRC1_3                                                     0x4d18
-+#define mmDIG4_AFMT_ISRC1_3                                                     0x4e18
-+#define mmDIG5_AFMT_ISRC1_3                                                     0x4f18
-+#define mmDIG6_AFMT_ISRC1_3                                                     0x5418
-+#define mmDIG7_AFMT_ISRC1_3                                                     0x5618
-+#define mmDIG8_AFMT_ISRC1_3                                                     0x5718
-+#define mmAFMT_ISRC1_4                                                          0x4a19
-+#define mmDIG0_AFMT_ISRC1_4                                                     0x4a19
-+#define mmDIG1_AFMT_ISRC1_4                                                     0x4b19
-+#define mmDIG2_AFMT_ISRC1_4                                                     0x4c19
-+#define mmDIG3_AFMT_ISRC1_4                                                     0x4d19
-+#define mmDIG4_AFMT_ISRC1_4                                                     0x4e19
-+#define mmDIG5_AFMT_ISRC1_4                                                     0x4f19
-+#define mmDIG6_AFMT_ISRC1_4                                                     0x5419
-+#define mmDIG7_AFMT_ISRC1_4                                                     0x5619
-+#define mmDIG8_AFMT_ISRC1_4                                                     0x5719
-+#define mmAFMT_ISRC2_0                                                          0x4a1a
-+#define mmDIG0_AFMT_ISRC2_0                                                     0x4a1a
-+#define mmDIG1_AFMT_ISRC2_0                                                     0x4b1a
-+#define mmDIG2_AFMT_ISRC2_0                                                     0x4c1a
-+#define mmDIG3_AFMT_ISRC2_0                                                     0x4d1a
-+#define mmDIG4_AFMT_ISRC2_0                                                     0x4e1a
-+#define mmDIG5_AFMT_ISRC2_0                                                     0x4f1a
-+#define mmDIG6_AFMT_ISRC2_0                                                     0x541a
-+#define mmDIG7_AFMT_ISRC2_0                                                     0x561a
-+#define mmDIG8_AFMT_ISRC2_0                                                     0x571a
-+#define mmAFMT_ISRC2_1                                                          0x4a1b
-+#define mmDIG0_AFMT_ISRC2_1                                                     0x4a1b
-+#define mmDIG1_AFMT_ISRC2_1                                                     0x4b1b
-+#define mmDIG2_AFMT_ISRC2_1                                                     0x4c1b
-+#define mmDIG3_AFMT_ISRC2_1                                                     0x4d1b
-+#define mmDIG4_AFMT_ISRC2_1                                                     0x4e1b
-+#define mmDIG5_AFMT_ISRC2_1                                                     0x4f1b
-+#define mmDIG6_AFMT_ISRC2_1                                                     0x541b
-+#define mmDIG7_AFMT_ISRC2_1                                                     0x561b
-+#define mmDIG8_AFMT_ISRC2_1                                                     0x571b
-+#define mmAFMT_ISRC2_2                                                          0x4a1c
-+#define mmDIG0_AFMT_ISRC2_2                                                     0x4a1c
-+#define mmDIG1_AFMT_ISRC2_2                                                     0x4b1c
-+#define mmDIG2_AFMT_ISRC2_2                                                     0x4c1c
-+#define mmDIG3_AFMT_ISRC2_2                                                     0x4d1c
-+#define mmDIG4_AFMT_ISRC2_2                                                     0x4e1c
-+#define mmDIG5_AFMT_ISRC2_2                                                     0x4f1c
-+#define mmDIG6_AFMT_ISRC2_2                                                     0x541c
-+#define mmDIG7_AFMT_ISRC2_2                                                     0x561c
-+#define mmDIG8_AFMT_ISRC2_2                                                     0x571c
-+#define mmAFMT_ISRC2_3                                                          0x4a1d
-+#define mmDIG0_AFMT_ISRC2_3                                                     0x4a1d
-+#define mmDIG1_AFMT_ISRC2_3                                                     0x4b1d
-+#define mmDIG2_AFMT_ISRC2_3                                                     0x4c1d
-+#define mmDIG3_AFMT_ISRC2_3                                                     0x4d1d
-+#define mmDIG4_AFMT_ISRC2_3                                                     0x4e1d
-+#define mmDIG5_AFMT_ISRC2_3                                                     0x4f1d
-+#define mmDIG6_AFMT_ISRC2_3                                                     0x541d
-+#define mmDIG7_AFMT_ISRC2_3                                                     0x561d
-+#define mmDIG8_AFMT_ISRC2_3                                                     0x571d
-+#define mmAFMT_AVI_INFO0                                                        0x4a1e
-+#define mmDIG0_AFMT_AVI_INFO0                                                   0x4a1e
-+#define mmDIG1_AFMT_AVI_INFO0                                                   0x4b1e
-+#define mmDIG2_AFMT_AVI_INFO0                                                   0x4c1e
-+#define mmDIG3_AFMT_AVI_INFO0                                                   0x4d1e
-+#define mmDIG4_AFMT_AVI_INFO0                                                   0x4e1e
-+#define mmDIG5_AFMT_AVI_INFO0                                                   0x4f1e
-+#define mmDIG6_AFMT_AVI_INFO0                                                   0x541e
-+#define mmDIG7_AFMT_AVI_INFO0                                                   0x561e
-+#define mmDIG8_AFMT_AVI_INFO0                                                   0x571e
-+#define mmAFMT_AVI_INFO1                                                        0x4a1f
-+#define mmDIG0_AFMT_AVI_INFO1                                                   0x4a1f
-+#define mmDIG1_AFMT_AVI_INFO1                                                   0x4b1f
-+#define mmDIG2_AFMT_AVI_INFO1                                                   0x4c1f
-+#define mmDIG3_AFMT_AVI_INFO1                                                   0x4d1f
-+#define mmDIG4_AFMT_AVI_INFO1                                                   0x4e1f
-+#define mmDIG5_AFMT_AVI_INFO1                                                   0x4f1f
-+#define mmDIG6_AFMT_AVI_INFO1                                                   0x541f
-+#define mmDIG7_AFMT_AVI_INFO1                                                   0x561f
-+#define mmDIG8_AFMT_AVI_INFO1                                                   0x571f
-+#define mmAFMT_AVI_INFO2                                                        0x4a20
-+#define mmDIG0_AFMT_AVI_INFO2                                                   0x4a20
-+#define mmDIG1_AFMT_AVI_INFO2                                                   0x4b20
-+#define mmDIG2_AFMT_AVI_INFO2                                                   0x4c20
-+#define mmDIG3_AFMT_AVI_INFO2                                                   0x4d20
-+#define mmDIG4_AFMT_AVI_INFO2                                                   0x4e20
-+#define mmDIG5_AFMT_AVI_INFO2                                                   0x4f20
-+#define mmDIG6_AFMT_AVI_INFO2                                                   0x5420
-+#define mmDIG7_AFMT_AVI_INFO2                                                   0x5620
-+#define mmDIG8_AFMT_AVI_INFO2                                                   0x5720
-+#define mmAFMT_AVI_INFO3                                                        0x4a21
-+#define mmDIG0_AFMT_AVI_INFO3                                                   0x4a21
-+#define mmDIG1_AFMT_AVI_INFO3                                                   0x4b21
-+#define mmDIG2_AFMT_AVI_INFO3                                                   0x4c21
-+#define mmDIG3_AFMT_AVI_INFO3                                                   0x4d21
-+#define mmDIG4_AFMT_AVI_INFO3                                                   0x4e21
-+#define mmDIG5_AFMT_AVI_INFO3                                                   0x4f21
-+#define mmDIG6_AFMT_AVI_INFO3                                                   0x5421
-+#define mmDIG7_AFMT_AVI_INFO3                                                   0x5621
-+#define mmDIG8_AFMT_AVI_INFO3                                                   0x5721
-+#define mmAFMT_MPEG_INFO0                                                       0x4a22
-+#define mmDIG0_AFMT_MPEG_INFO0                                                  0x4a22
-+#define mmDIG1_AFMT_MPEG_INFO0                                                  0x4b22
-+#define mmDIG2_AFMT_MPEG_INFO0                                                  0x4c22
-+#define mmDIG3_AFMT_MPEG_INFO0                                                  0x4d22
-+#define mmDIG4_AFMT_MPEG_INFO0                                                  0x4e22
-+#define mmDIG5_AFMT_MPEG_INFO0                                                  0x4f22
-+#define mmDIG6_AFMT_MPEG_INFO0                                                  0x5422
-+#define mmDIG7_AFMT_MPEG_INFO0                                                  0x5622
-+#define mmDIG8_AFMT_MPEG_INFO0                                                  0x5722
-+#define mmAFMT_MPEG_INFO1                                                       0x4a23
-+#define mmDIG0_AFMT_MPEG_INFO1                                                  0x4a23
-+#define mmDIG1_AFMT_MPEG_INFO1                                                  0x4b23
-+#define mmDIG2_AFMT_MPEG_INFO1                                                  0x4c23
-+#define mmDIG3_AFMT_MPEG_INFO1                                                  0x4d23
-+#define mmDIG4_AFMT_MPEG_INFO1                                                  0x4e23
-+#define mmDIG5_AFMT_MPEG_INFO1                                                  0x4f23
-+#define mmDIG6_AFMT_MPEG_INFO1                                                  0x5423
-+#define mmDIG7_AFMT_MPEG_INFO1                                                  0x5623
-+#define mmDIG8_AFMT_MPEG_INFO1                                                  0x5723
-+#define mmAFMT_GENERIC_HDR                                                      0x4a24
-+#define mmDIG0_AFMT_GENERIC_HDR                                                 0x4a24
-+#define mmDIG1_AFMT_GENERIC_HDR                                                 0x4b24
-+#define mmDIG2_AFMT_GENERIC_HDR                                                 0x4c24
-+#define mmDIG3_AFMT_GENERIC_HDR                                                 0x4d24
-+#define mmDIG4_AFMT_GENERIC_HDR                                                 0x4e24
-+#define mmDIG5_AFMT_GENERIC_HDR                                                 0x4f24
-+#define mmDIG6_AFMT_GENERIC_HDR                                                 0x5424
-+#define mmDIG7_AFMT_GENERIC_HDR                                                 0x5624
-+#define mmDIG8_AFMT_GENERIC_HDR                                                 0x5724
-+#define mmAFMT_GENERIC_0                                                        0x4a25
-+#define mmDIG0_AFMT_GENERIC_0                                                   0x4a25
-+#define mmDIG1_AFMT_GENERIC_0                                                   0x4b25
-+#define mmDIG2_AFMT_GENERIC_0                                                   0x4c25
-+#define mmDIG3_AFMT_GENERIC_0                                                   0x4d25
-+#define mmDIG4_AFMT_GENERIC_0                                                   0x4e25
-+#define mmDIG5_AFMT_GENERIC_0                                                   0x4f25
-+#define mmDIG6_AFMT_GENERIC_0                                                   0x5425
-+#define mmDIG7_AFMT_GENERIC_0                                                   0x5625
-+#define mmDIG8_AFMT_GENERIC_0                                                   0x5725
-+#define mmAFMT_GENERIC_1                                                        0x4a26
-+#define mmDIG0_AFMT_GENERIC_1                                                   0x4a26
-+#define mmDIG1_AFMT_GENERIC_1                                                   0x4b26
-+#define mmDIG2_AFMT_GENERIC_1                                                   0x4c26
-+#define mmDIG3_AFMT_GENERIC_1                                                   0x4d26
-+#define mmDIG4_AFMT_GENERIC_1                                                   0x4e26
-+#define mmDIG5_AFMT_GENERIC_1                                                   0x4f26
-+#define mmDIG6_AFMT_GENERIC_1                                                   0x5426
-+#define mmDIG7_AFMT_GENERIC_1                                                   0x5626
-+#define mmDIG8_AFMT_GENERIC_1                                                   0x5726
-+#define mmAFMT_GENERIC_2                                                        0x4a27
-+#define mmDIG0_AFMT_GENERIC_2                                                   0x4a27
-+#define mmDIG1_AFMT_GENERIC_2                                                   0x4b27
-+#define mmDIG2_AFMT_GENERIC_2                                                   0x4c27
-+#define mmDIG3_AFMT_GENERIC_2                                                   0x4d27
-+#define mmDIG4_AFMT_GENERIC_2                                                   0x4e27
-+#define mmDIG5_AFMT_GENERIC_2                                                   0x4f27
-+#define mmDIG6_AFMT_GENERIC_2                                                   0x5427
-+#define mmDIG7_AFMT_GENERIC_2                                                   0x5627
-+#define mmDIG8_AFMT_GENERIC_2                                                   0x5727
-+#define mmAFMT_GENERIC_3                                                        0x4a28
-+#define mmDIG0_AFMT_GENERIC_3                                                   0x4a28
-+#define mmDIG1_AFMT_GENERIC_3                                                   0x4b28
-+#define mmDIG2_AFMT_GENERIC_3                                                   0x4c28
-+#define mmDIG3_AFMT_GENERIC_3                                                   0x4d28
-+#define mmDIG4_AFMT_GENERIC_3                                                   0x4e28
-+#define mmDIG5_AFMT_GENERIC_3                                                   0x4f28
-+#define mmDIG6_AFMT_GENERIC_3                                                   0x5428
-+#define mmDIG7_AFMT_GENERIC_3                                                   0x5628
-+#define mmDIG8_AFMT_GENERIC_3                                                   0x5728
-+#define mmAFMT_GENERIC_4                                                        0x4a29
-+#define mmDIG0_AFMT_GENERIC_4                                                   0x4a29
-+#define mmDIG1_AFMT_GENERIC_4                                                   0x4b29
-+#define mmDIG2_AFMT_GENERIC_4                                                   0x4c29
-+#define mmDIG3_AFMT_GENERIC_4                                                   0x4d29
-+#define mmDIG4_AFMT_GENERIC_4                                                   0x4e29
-+#define mmDIG5_AFMT_GENERIC_4                                                   0x4f29
-+#define mmDIG6_AFMT_GENERIC_4                                                   0x5429
-+#define mmDIG7_AFMT_GENERIC_4                                                   0x5629
-+#define mmDIG8_AFMT_GENERIC_4                                                   0x5729
-+#define mmAFMT_GENERIC_5                                                        0x4a2a
-+#define mmDIG0_AFMT_GENERIC_5                                                   0x4a2a
-+#define mmDIG1_AFMT_GENERIC_5                                                   0x4b2a
-+#define mmDIG2_AFMT_GENERIC_5                                                   0x4c2a
-+#define mmDIG3_AFMT_GENERIC_5                                                   0x4d2a
-+#define mmDIG4_AFMT_GENERIC_5                                                   0x4e2a
-+#define mmDIG5_AFMT_GENERIC_5                                                   0x4f2a
-+#define mmDIG6_AFMT_GENERIC_5                                                   0x542a
-+#define mmDIG7_AFMT_GENERIC_5                                                   0x562a
-+#define mmDIG8_AFMT_GENERIC_5                                                   0x572a
-+#define mmAFMT_GENERIC_6                                                        0x4a2b
-+#define mmDIG0_AFMT_GENERIC_6                                                   0x4a2b
-+#define mmDIG1_AFMT_GENERIC_6                                                   0x4b2b
-+#define mmDIG2_AFMT_GENERIC_6                                                   0x4c2b
-+#define mmDIG3_AFMT_GENERIC_6                                                   0x4d2b
-+#define mmDIG4_AFMT_GENERIC_6                                                   0x4e2b
-+#define mmDIG5_AFMT_GENERIC_6                                                   0x4f2b
-+#define mmDIG6_AFMT_GENERIC_6                                                   0x542b
-+#define mmDIG7_AFMT_GENERIC_6                                                   0x562b
-+#define mmDIG8_AFMT_GENERIC_6                                                   0x572b
-+#define mmAFMT_GENERIC_7                                                        0x4a2c
-+#define mmDIG0_AFMT_GENERIC_7                                                   0x4a2c
-+#define mmDIG1_AFMT_GENERIC_7                                                   0x4b2c
-+#define mmDIG2_AFMT_GENERIC_7                                                   0x4c2c
-+#define mmDIG3_AFMT_GENERIC_7                                                   0x4d2c
-+#define mmDIG4_AFMT_GENERIC_7                                                   0x4e2c
-+#define mmDIG5_AFMT_GENERIC_7                                                   0x4f2c
-+#define mmDIG6_AFMT_GENERIC_7                                                   0x542c
-+#define mmDIG7_AFMT_GENERIC_7                                                   0x562c
-+#define mmDIG8_AFMT_GENERIC_7                                                   0x572c
-+#define mmHDMI_GENERIC_PACKET_CONTROL1                                          0x4a2d
-+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                     0x4a2d
-+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                     0x4b2d
-+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                     0x4c2d
-+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                     0x4d2d
-+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                     0x4e2d
-+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                     0x4f2d
-+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                     0x542d
-+#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1                                     0x562d
-+#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1                                     0x572d
-+#define mmHDMI_ACR_32_0                                                         0x4a2e
-+#define mmDIG0_HDMI_ACR_32_0                                                    0x4a2e
-+#define mmDIG1_HDMI_ACR_32_0                                                    0x4b2e
-+#define mmDIG2_HDMI_ACR_32_0                                                    0x4c2e
-+#define mmDIG3_HDMI_ACR_32_0                                                    0x4d2e
-+#define mmDIG4_HDMI_ACR_32_0                                                    0x4e2e
-+#define mmDIG5_HDMI_ACR_32_0                                                    0x4f2e
-+#define mmDIG6_HDMI_ACR_32_0                                                    0x542e
-+#define mmDIG7_HDMI_ACR_32_0                                                    0x562e
-+#define mmDIG8_HDMI_ACR_32_0                                                    0x572e
-+#define mmHDMI_ACR_32_1                                                         0x4a2f
-+#define mmDIG0_HDMI_ACR_32_1                                                    0x4a2f
-+#define mmDIG1_HDMI_ACR_32_1                                                    0x4b2f
-+#define mmDIG2_HDMI_ACR_32_1                                                    0x4c2f
-+#define mmDIG3_HDMI_ACR_32_1                                                    0x4d2f
-+#define mmDIG4_HDMI_ACR_32_1                                                    0x4e2f
-+#define mmDIG5_HDMI_ACR_32_1                                                    0x4f2f
-+#define mmDIG6_HDMI_ACR_32_1                                                    0x542f
-+#define mmDIG7_HDMI_ACR_32_1                                                    0x562f
-+#define mmDIG8_HDMI_ACR_32_1                                                    0x572f
-+#define mmHDMI_ACR_44_0                                                         0x4a30
-+#define mmDIG0_HDMI_ACR_44_0                                                    0x4a30
-+#define mmDIG1_HDMI_ACR_44_0                                                    0x4b30
-+#define mmDIG2_HDMI_ACR_44_0                                                    0x4c30
-+#define mmDIG3_HDMI_ACR_44_0                                                    0x4d30
-+#define mmDIG4_HDMI_ACR_44_0                                                    0x4e30
-+#define mmDIG5_HDMI_ACR_44_0                                                    0x4f30
-+#define mmDIG6_HDMI_ACR_44_0                                                    0x5430
-+#define mmDIG7_HDMI_ACR_44_0                                                    0x5630
-+#define mmDIG8_HDMI_ACR_44_0                                                    0x5730
-+#define mmHDMI_ACR_44_1                                                         0x4a31
-+#define mmDIG0_HDMI_ACR_44_1                                                    0x4a31
-+#define mmDIG1_HDMI_ACR_44_1                                                    0x4b31
-+#define mmDIG2_HDMI_ACR_44_1                                                    0x4c31
-+#define mmDIG3_HDMI_ACR_44_1                                                    0x4d31
-+#define mmDIG4_HDMI_ACR_44_1                                                    0x4e31
-+#define mmDIG5_HDMI_ACR_44_1                                                    0x4f31
-+#define mmDIG6_HDMI_ACR_44_1                                                    0x5431
-+#define mmDIG7_HDMI_ACR_44_1                                                    0x5631
-+#define mmDIG8_HDMI_ACR_44_1                                                    0x5731
-+#define mmHDMI_ACR_48_0                                                         0x4a32
-+#define mmDIG0_HDMI_ACR_48_0                                                    0x4a32
-+#define mmDIG1_HDMI_ACR_48_0                                                    0x4b32
-+#define mmDIG2_HDMI_ACR_48_0                                                    0x4c32
-+#define mmDIG3_HDMI_ACR_48_0                                                    0x4d32
-+#define mmDIG4_HDMI_ACR_48_0                                                    0x4e32
-+#define mmDIG5_HDMI_ACR_48_0                                                    0x4f32
-+#define mmDIG6_HDMI_ACR_48_0                                                    0x5432
-+#define mmDIG7_HDMI_ACR_48_0                                                    0x5632
-+#define mmDIG8_HDMI_ACR_48_0                                                    0x5732
-+#define mmHDMI_ACR_48_1                                                         0x4a33
-+#define mmDIG0_HDMI_ACR_48_1                                                    0x4a33
-+#define mmDIG1_HDMI_ACR_48_1                                                    0x4b33
-+#define mmDIG2_HDMI_ACR_48_1                                                    0x4c33
-+#define mmDIG3_HDMI_ACR_48_1                                                    0x4d33
-+#define mmDIG4_HDMI_ACR_48_1                                                    0x4e33
-+#define mmDIG5_HDMI_ACR_48_1                                                    0x4f33
-+#define mmDIG6_HDMI_ACR_48_1                                                    0x5433
-+#define mmDIG7_HDMI_ACR_48_1                                                    0x5633
-+#define mmDIG8_HDMI_ACR_48_1                                                    0x5733
-+#define mmHDMI_ACR_STATUS_0                                                     0x4a34
-+#define mmDIG0_HDMI_ACR_STATUS_0                                                0x4a34
-+#define mmDIG1_HDMI_ACR_STATUS_0                                                0x4b34
-+#define mmDIG2_HDMI_ACR_STATUS_0                                                0x4c34
-+#define mmDIG3_HDMI_ACR_STATUS_0                                                0x4d34
-+#define mmDIG4_HDMI_ACR_STATUS_0                                                0x4e34
-+#define mmDIG5_HDMI_ACR_STATUS_0                                                0x4f34
-+#define mmDIG6_HDMI_ACR_STATUS_0                                                0x5434
-+#define mmDIG7_HDMI_ACR_STATUS_0                                                0x5634
-+#define mmDIG8_HDMI_ACR_STATUS_0                                                0x5734
-+#define mmHDMI_ACR_STATUS_1                                                     0x4a35
-+#define mmDIG0_HDMI_ACR_STATUS_1                                                0x4a35
-+#define mmDIG1_HDMI_ACR_STATUS_1                                                0x4b35
-+#define mmDIG2_HDMI_ACR_STATUS_1                                                0x4c35
-+#define mmDIG3_HDMI_ACR_STATUS_1                                                0x4d35
-+#define mmDIG4_HDMI_ACR_STATUS_1                                                0x4e35
-+#define mmDIG5_HDMI_ACR_STATUS_1                                                0x4f35
-+#define mmDIG6_HDMI_ACR_STATUS_1                                                0x5435
-+#define mmDIG7_HDMI_ACR_STATUS_1                                                0x5635
-+#define mmDIG8_HDMI_ACR_STATUS_1                                                0x5735
-+#define mmAFMT_AUDIO_INFO0                                                      0x4a36
-+#define mmDIG0_AFMT_AUDIO_INFO0                                                 0x4a36
-+#define mmDIG1_AFMT_AUDIO_INFO0                                                 0x4b36
-+#define mmDIG2_AFMT_AUDIO_INFO0                                                 0x4c36
-+#define mmDIG3_AFMT_AUDIO_INFO0                                                 0x4d36
-+#define mmDIG4_AFMT_AUDIO_INFO0                                                 0x4e36
-+#define mmDIG5_AFMT_AUDIO_INFO0                                                 0x4f36
-+#define mmDIG6_AFMT_AUDIO_INFO0                                                 0x5436
-+#define mmDIG7_AFMT_AUDIO_INFO0                                                 0x5636
-+#define mmDIG8_AFMT_AUDIO_INFO0                                                 0x5736
-+#define mmAFMT_AUDIO_INFO1                                                      0x4a37
-+#define mmDIG0_AFMT_AUDIO_INFO1                                                 0x4a37
-+#define mmDIG1_AFMT_AUDIO_INFO1                                                 0x4b37
-+#define mmDIG2_AFMT_AUDIO_INFO1                                                 0x4c37
-+#define mmDIG3_AFMT_AUDIO_INFO1                                                 0x4d37
-+#define mmDIG4_AFMT_AUDIO_INFO1                                                 0x4e37
-+#define mmDIG5_AFMT_AUDIO_INFO1                                                 0x4f37
-+#define mmDIG6_AFMT_AUDIO_INFO1                                                 0x5437
-+#define mmDIG7_AFMT_AUDIO_INFO1                                                 0x5637
-+#define mmDIG8_AFMT_AUDIO_INFO1                                                 0x5737
-+#define mmAFMT_60958_0                                                          0x4a38
-+#define mmDIG0_AFMT_60958_0                                                     0x4a38
-+#define mmDIG1_AFMT_60958_0                                                     0x4b38
-+#define mmDIG2_AFMT_60958_0                                                     0x4c38
-+#define mmDIG3_AFMT_60958_0                                                     0x4d38
-+#define mmDIG4_AFMT_60958_0                                                     0x4e38
-+#define mmDIG5_AFMT_60958_0                                                     0x4f38
-+#define mmDIG6_AFMT_60958_0                                                     0x5438
-+#define mmDIG7_AFMT_60958_0                                                     0x5638
-+#define mmDIG8_AFMT_60958_0                                                     0x5738
-+#define mmAFMT_60958_1                                                          0x4a39
-+#define mmDIG0_AFMT_60958_1                                                     0x4a39
-+#define mmDIG1_AFMT_60958_1                                                     0x4b39
-+#define mmDIG2_AFMT_60958_1                                                     0x4c39
-+#define mmDIG3_AFMT_60958_1                                                     0x4d39
-+#define mmDIG4_AFMT_60958_1                                                     0x4e39
-+#define mmDIG5_AFMT_60958_1                                                     0x4f39
-+#define mmDIG6_AFMT_60958_1                                                     0x5439
-+#define mmDIG7_AFMT_60958_1                                                     0x5639
-+#define mmDIG8_AFMT_60958_1                                                     0x5739
-+#define mmAFMT_AUDIO_CRC_CONTROL                                                0x4a3a
-+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                           0x4a3a
-+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                           0x4b3a
-+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                           0x4c3a
-+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                           0x4d3a
-+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                           0x4e3a
-+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL                                           0x4f3a
-+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL                                           0x543a
-+#define mmDIG7_AFMT_AUDIO_CRC_CONTROL                                           0x563a
-+#define mmDIG8_AFMT_AUDIO_CRC_CONTROL                                           0x573a
-+#define mmAFMT_RAMP_CONTROL0                                                    0x4a3b
-+#define mmDIG0_AFMT_RAMP_CONTROL0                                               0x4a3b
-+#define mmDIG1_AFMT_RAMP_CONTROL0                                               0x4b3b
-+#define mmDIG2_AFMT_RAMP_CONTROL0                                               0x4c3b
-+#define mmDIG3_AFMT_RAMP_CONTROL0                                               0x4d3b
-+#define mmDIG4_AFMT_RAMP_CONTROL0                                               0x4e3b
-+#define mmDIG5_AFMT_RAMP_CONTROL0                                               0x4f3b
-+#define mmDIG6_AFMT_RAMP_CONTROL0                                               0x543b
-+#define mmDIG7_AFMT_RAMP_CONTROL0                                               0x563b
-+#define mmDIG8_AFMT_RAMP_CONTROL0                                               0x573b
-+#define mmAFMT_RAMP_CONTROL1                                                    0x4a3c
-+#define mmDIG0_AFMT_RAMP_CONTROL1                                               0x4a3c
-+#define mmDIG1_AFMT_RAMP_CONTROL1                                               0x4b3c
-+#define mmDIG2_AFMT_RAMP_CONTROL1                                               0x4c3c
-+#define mmDIG3_AFMT_RAMP_CONTROL1                                               0x4d3c
-+#define mmDIG4_AFMT_RAMP_CONTROL1                                               0x4e3c
-+#define mmDIG5_AFMT_RAMP_CONTROL1                                               0x4f3c
-+#define mmDIG6_AFMT_RAMP_CONTROL1                                               0x543c
-+#define mmDIG7_AFMT_RAMP_CONTROL1                                               0x563c
-+#define mmDIG8_AFMT_RAMP_CONTROL1                                               0x573c
-+#define mmAFMT_RAMP_CONTROL2                                                    0x4a3d
-+#define mmDIG0_AFMT_RAMP_CONTROL2                                               0x4a3d
-+#define mmDIG1_AFMT_RAMP_CONTROL2                                               0x4b3d
-+#define mmDIG2_AFMT_RAMP_CONTROL2                                               0x4c3d
-+#define mmDIG3_AFMT_RAMP_CONTROL2                                               0x4d3d
-+#define mmDIG4_AFMT_RAMP_CONTROL2                                               0x4e3d
-+#define mmDIG5_AFMT_RAMP_CONTROL2                                               0x4f3d
-+#define mmDIG6_AFMT_RAMP_CONTROL2                                               0x543d
-+#define mmDIG7_AFMT_RAMP_CONTROL2                                               0x563d
-+#define mmDIG8_AFMT_RAMP_CONTROL2                                               0x573d
-+#define mmAFMT_RAMP_CONTROL3                                                    0x4a3e
-+#define mmDIG0_AFMT_RAMP_CONTROL3                                               0x4a3e
-+#define mmDIG1_AFMT_RAMP_CONTROL3                                               0x4b3e
-+#define mmDIG2_AFMT_RAMP_CONTROL3                                               0x4c3e
-+#define mmDIG3_AFMT_RAMP_CONTROL3                                               0x4d3e
-+#define mmDIG4_AFMT_RAMP_CONTROL3                                               0x4e3e
-+#define mmDIG5_AFMT_RAMP_CONTROL3                                               0x4f3e
-+#define mmDIG6_AFMT_RAMP_CONTROL3                                               0x543e
-+#define mmDIG7_AFMT_RAMP_CONTROL3                                               0x563e
-+#define mmDIG8_AFMT_RAMP_CONTROL3                                               0x573e
-+#define mmAFMT_60958_2                                                          0x4a3f
-+#define mmDIG0_AFMT_60958_2                                                     0x4a3f
-+#define mmDIG1_AFMT_60958_2                                                     0x4b3f
-+#define mmDIG2_AFMT_60958_2                                                     0x4c3f
-+#define mmDIG3_AFMT_60958_2                                                     0x4d3f
-+#define mmDIG4_AFMT_60958_2                                                     0x4e3f
-+#define mmDIG5_AFMT_60958_2                                                     0x4f3f
-+#define mmDIG6_AFMT_60958_2                                                     0x543f
-+#define mmDIG7_AFMT_60958_2                                                     0x563f
-+#define mmDIG8_AFMT_60958_2                                                     0x573f
-+#define mmAFMT_AUDIO_CRC_RESULT                                                 0x4a40
-+#define mmDIG0_AFMT_AUDIO_CRC_RESULT                                            0x4a40
-+#define mmDIG1_AFMT_AUDIO_CRC_RESULT                                            0x4b40
-+#define mmDIG2_AFMT_AUDIO_CRC_RESULT                                            0x4c40
-+#define mmDIG3_AFMT_AUDIO_CRC_RESULT                                            0x4d40
-+#define mmDIG4_AFMT_AUDIO_CRC_RESULT                                            0x4e40
-+#define mmDIG5_AFMT_AUDIO_CRC_RESULT                                            0x4f40
-+#define mmDIG6_AFMT_AUDIO_CRC_RESULT                                            0x5440
-+#define mmDIG7_AFMT_AUDIO_CRC_RESULT                                            0x5640
-+#define mmDIG8_AFMT_AUDIO_CRC_RESULT                                            0x5740
-+#define mmAFMT_STATUS                                                           0x4a41
-+#define mmDIG0_AFMT_STATUS                                                      0x4a41
-+#define mmDIG1_AFMT_STATUS                                                      0x4b41
-+#define mmDIG2_AFMT_STATUS                                                      0x4c41
-+#define mmDIG3_AFMT_STATUS                                                      0x4d41
-+#define mmDIG4_AFMT_STATUS                                                      0x4e41
-+#define mmDIG5_AFMT_STATUS                                                      0x4f41
-+#define mmDIG6_AFMT_STATUS                                                      0x5441
-+#define mmDIG7_AFMT_STATUS                                                      0x5641
-+#define mmDIG8_AFMT_STATUS                                                      0x5741
-+#define mmAFMT_AUDIO_PACKET_CONTROL                                             0x4a42
-+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                        0x4a42
-+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                        0x4b42
-+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                        0x4c42
-+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                        0x4d42
-+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                        0x4e42
-+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                        0x4f42
-+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                        0x5442
-+#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL                                        0x5642
-+#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL                                        0x5742
-+#define mmAFMT_VBI_PACKET_CONTROL                                               0x4a43
-+#define mmDIG0_AFMT_VBI_PACKET_CONTROL                                          0x4a43
-+#define mmDIG1_AFMT_VBI_PACKET_CONTROL                                          0x4b43
-+#define mmDIG2_AFMT_VBI_PACKET_CONTROL                                          0x4c43
-+#define mmDIG3_AFMT_VBI_PACKET_CONTROL                                          0x4d43
-+#define mmDIG4_AFMT_VBI_PACKET_CONTROL                                          0x4e43
-+#define mmDIG5_AFMT_VBI_PACKET_CONTROL                                          0x4f43
-+#define mmDIG6_AFMT_VBI_PACKET_CONTROL                                          0x5443
-+#define mmDIG7_AFMT_VBI_PACKET_CONTROL                                          0x5643
-+#define mmDIG8_AFMT_VBI_PACKET_CONTROL                                          0x5743
-+#define mmAFMT_INFOFRAME_CONTROL0                                               0x4a44
-+#define mmDIG0_AFMT_INFOFRAME_CONTROL0                                          0x4a44
-+#define mmDIG1_AFMT_INFOFRAME_CONTROL0                                          0x4b44
-+#define mmDIG2_AFMT_INFOFRAME_CONTROL0                                          0x4c44
-+#define mmDIG3_AFMT_INFOFRAME_CONTROL0                                          0x4d44
-+#define mmDIG4_AFMT_INFOFRAME_CONTROL0                                          0x4e44
-+#define mmDIG5_AFMT_INFOFRAME_CONTROL0                                          0x4f44
-+#define mmDIG6_AFMT_INFOFRAME_CONTROL0                                          0x5444
-+#define mmDIG7_AFMT_INFOFRAME_CONTROL0                                          0x5644
-+#define mmDIG8_AFMT_INFOFRAME_CONTROL0                                          0x5744
-+#define mmAFMT_AUDIO_SRC_CONTROL                                                0x4a45
-+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                           0x4a45
-+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                           0x4b45
-+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                           0x4c45
-+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                           0x4d45
-+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                           0x4e45
-+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL                                           0x4f45
-+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL                                           0x5445
-+#define mmDIG7_AFMT_AUDIO_SRC_CONTROL                                           0x5645
-+#define mmDIG8_AFMT_AUDIO_SRC_CONTROL                                           0x5745
-+#define mmAFMT_AUDIO_DBG_DTO_CNTL                                               0x4a46
-+#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4a46
-+#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4b46
-+#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4c46
-+#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4d46
-+#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4e46
-+#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4f46
-+#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5446
-+#define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5646
-+#define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5746
-+#define mmAFMT_CNTL                                                             0x4a7e
-+#define mmDIG0_AFMT_CNTL                                                        0x4a7e
-+#define mmDIG1_AFMT_CNTL                                                        0x4b7e
-+#define mmDIG2_AFMT_CNTL                                                        0x4c7e
-+#define mmDIG3_AFMT_CNTL                                                        0x4d7e
-+#define mmDIG4_AFMT_CNTL                                                        0x4e7e
-+#define mmDIG5_AFMT_CNTL                                                        0x4f7e
-+#define mmDIG6_AFMT_CNTL                                                        0x547e
-+#define mmDIG7_AFMT_CNTL                                                        0x567e
-+#define mmDIG8_AFMT_CNTL                                                        0x577e
-+#define mmDIG_BE_CNTL                                                           0x4a47
-+#define mmDIG0_DIG_BE_CNTL                                                      0x4a47
-+#define mmDIG1_DIG_BE_CNTL                                                      0x4b47
-+#define mmDIG2_DIG_BE_CNTL                                                      0x4c47
-+#define mmDIG3_DIG_BE_CNTL                                                      0x4d47
-+#define mmDIG4_DIG_BE_CNTL                                                      0x4e47
-+#define mmDIG5_DIG_BE_CNTL                                                      0x4f47
-+#define mmDIG6_DIG_BE_CNTL                                                      0x5447
-+#define mmDIG7_DIG_BE_CNTL                                                      0x5647
-+#define mmDIG8_DIG_BE_CNTL                                                      0x5747
-+#define mmDIG_BE_EN_CNTL                                                        0x4a48
-+#define mmDIG0_DIG_BE_EN_CNTL                                                   0x4a48
-+#define mmDIG1_DIG_BE_EN_CNTL                                                   0x4b48
-+#define mmDIG2_DIG_BE_EN_CNTL                                                   0x4c48
-+#define mmDIG3_DIG_BE_EN_CNTL                                                   0x4d48
-+#define mmDIG4_DIG_BE_EN_CNTL                                                   0x4e48
-+#define mmDIG5_DIG_BE_EN_CNTL                                                   0x4f48
-+#define mmDIG6_DIG_BE_EN_CNTL                                                   0x5448
-+#define mmDIG7_DIG_BE_EN_CNTL                                                   0x5648
-+#define mmDIG8_DIG_BE_EN_CNTL                                                   0x5748
-+#define mmTMDS_CNTL                                                             0x4a6b
-+#define mmDIG0_TMDS_CNTL                                                        0x4a6b
-+#define mmDIG1_TMDS_CNTL                                                        0x4b6b
-+#define mmDIG2_TMDS_CNTL                                                        0x4c6b
-+#define mmDIG3_TMDS_CNTL                                                        0x4d6b
-+#define mmDIG4_TMDS_CNTL                                                        0x4e6b
-+#define mmDIG5_TMDS_CNTL                                                        0x4f6b
-+#define mmDIG6_TMDS_CNTL                                                        0x546b
-+#define mmDIG7_TMDS_CNTL                                                        0x566b
-+#define mmDIG8_TMDS_CNTL                                                        0x576b
-+#define mmTMDS_CONTROL_CHAR                                                     0x4a6c
-+#define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
-+#define mmDIG1_TMDS_CONTROL_CHAR                                                0x4b6c
-+#define mmDIG2_TMDS_CONTROL_CHAR                                                0x4c6c
-+#define mmDIG3_TMDS_CONTROL_CHAR                                                0x4d6c
-+#define mmDIG4_TMDS_CONTROL_CHAR                                                0x4e6c
-+#define mmDIG5_TMDS_CONTROL_CHAR                                                0x4f6c
-+#define mmDIG6_TMDS_CONTROL_CHAR                                                0x546c
-+#define mmDIG7_TMDS_CONTROL_CHAR                                                0x566c
-+#define mmDIG8_TMDS_CONTROL_CHAR                                                0x576c
-+#define mmTMDS_CONTROL0_FEEDBACK                                                0x4a6d
-+#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                           0x4a6d
-+#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                           0x4b6d
-+#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                           0x4c6d
-+#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                           0x4d6d
-+#define mmDIG4_TMDS_CONTROL0_FEEDBACK                                           0x4e6d
-+#define mmDIG5_TMDS_CONTROL0_FEEDBACK                                           0x4f6d
-+#define mmDIG6_TMDS_CONTROL0_FEEDBACK                                           0x546d
-+#define mmDIG7_TMDS_CONTROL0_FEEDBACK                                           0x566d
-+#define mmDIG8_TMDS_CONTROL0_FEEDBACK                                           0x576d
-+#define mmTMDS_STEREOSYNC_CTL_SEL                                               0x4a6e
-+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                          0x4a6e
-+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                          0x4b6e
-+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                          0x4c6e
-+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                          0x4d6e
-+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                          0x4e6e
-+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                          0x4f6e
-+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                          0x546e
-+#define mmDIG7_TMDS_STEREOSYNC_CTL_SEL                                          0x566e
-+#define mmDIG8_TMDS_STEREOSYNC_CTL_SEL                                          0x576e
-+#define mmTMDS_SYNC_CHAR_PATTERN_0_1                                            0x4a6f
-+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4a6f
-+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4b6f
-+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4c6f
-+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4d6f
-+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4e6f
-+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4f6f
-+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x546f
-+#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x566f
-+#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x576f
-+#define mmTMDS_SYNC_CHAR_PATTERN_2_3                                            0x4a70
-+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4a70
-+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4b70
-+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4c70
-+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4d70
-+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4e70
-+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4f70
-+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5470
-+#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5670
-+#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5770
-+#define mmTMDS_DEBUG                                                            0x4a71
-+#define mmDIG0_TMDS_DEBUG                                                       0x4a71
-+#define mmDIG1_TMDS_DEBUG                                                       0x4b71
-+#define mmDIG2_TMDS_DEBUG                                                       0x4c71
-+#define mmDIG3_TMDS_DEBUG                                                       0x4d71
-+#define mmDIG4_TMDS_DEBUG                                                       0x4e71
-+#define mmDIG5_TMDS_DEBUG                                                       0x4f71
-+#define mmDIG6_TMDS_DEBUG                                                       0x5471
-+#define mmDIG7_TMDS_DEBUG                                                       0x5671
-+#define mmDIG8_TMDS_DEBUG                                                       0x5771
-+#define mmTMDS_CTL_BITS                                                         0x4a72
-+#define mmDIG0_TMDS_CTL_BITS                                                    0x4a72
-+#define mmDIG1_TMDS_CTL_BITS                                                    0x4b72
-+#define mmDIG2_TMDS_CTL_BITS                                                    0x4c72
-+#define mmDIG3_TMDS_CTL_BITS                                                    0x4d72
-+#define mmDIG4_TMDS_CTL_BITS                                                    0x4e72
-+#define mmDIG5_TMDS_CTL_BITS                                                    0x4f72
-+#define mmDIG6_TMDS_CTL_BITS                                                    0x5472
-+#define mmDIG7_TMDS_CTL_BITS                                                    0x5672
-+#define mmDIG8_TMDS_CTL_BITS                                                    0x5772
-+#define mmTMDS_DCBALANCER_CONTROL                                               0x4a73
-+#define mmDIG0_TMDS_DCBALANCER_CONTROL                                          0x4a73
-+#define mmDIG1_TMDS_DCBALANCER_CONTROL                                          0x4b73
-+#define mmDIG2_TMDS_DCBALANCER_CONTROL                                          0x4c73
-+#define mmDIG3_TMDS_DCBALANCER_CONTROL                                          0x4d73
-+#define mmDIG4_TMDS_DCBALANCER_CONTROL                                          0x4e73
-+#define mmDIG5_TMDS_DCBALANCER_CONTROL                                          0x4f73
-+#define mmDIG6_TMDS_DCBALANCER_CONTROL                                          0x5473
-+#define mmDIG7_TMDS_DCBALANCER_CONTROL                                          0x5673
-+#define mmDIG8_TMDS_DCBALANCER_CONTROL                                          0x5773
-+#define mmTMDS_CTL0_1_GEN_CNTL                                                  0x4a75
-+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                             0x4a75
-+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                             0x4b75
-+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                             0x4c75
-+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                             0x4d75
-+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                             0x4e75
-+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                             0x4f75
-+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL                                             0x5475
-+#define mmDIG7_TMDS_CTL0_1_GEN_CNTL                                             0x5675
-+#define mmDIG8_TMDS_CTL0_1_GEN_CNTL                                             0x5775
-+#define mmTMDS_CTL2_3_GEN_CNTL                                                  0x4a76
-+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                             0x4a76
-+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                             0x4b76
-+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                             0x4c76
-+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                             0x4d76
-+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                             0x4e76
-+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                             0x4f76
-+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL                                             0x5476
-+#define mmDIG7_TMDS_CTL2_3_GEN_CNTL                                             0x5676
-+#define mmDIG8_TMDS_CTL2_3_GEN_CNTL                                             0x5776
-+#define mmDIG_VERSION                                                           0x4a78
-+#define mmDIG0_DIG_VERSION                                                      0x4a78
-+#define mmDIG1_DIG_VERSION                                                      0x4b78
-+#define mmDIG2_DIG_VERSION                                                      0x4c78
-+#define mmDIG3_DIG_VERSION                                                      0x4d78
-+#define mmDIG4_DIG_VERSION                                                      0x4e78
-+#define mmDIG5_DIG_VERSION                                                      0x4f78
-+#define mmDIG6_DIG_VERSION                                                      0x5478
-+#define mmDIG7_DIG_VERSION                                                      0x5678
-+#define mmDIG8_DIG_VERSION                                                      0x5778
-+#define mmDIG_LANE_ENABLE                                                       0x4a79
-+#define mmDIG0_DIG_LANE_ENABLE                                                  0x4a79
-+#define mmDIG1_DIG_LANE_ENABLE                                                  0x4b79
-+#define mmDIG2_DIG_LANE_ENABLE                                                  0x4c79
-+#define mmDIG3_DIG_LANE_ENABLE                                                  0x4d79
-+#define mmDIG4_DIG_LANE_ENABLE                                                  0x4e79
-+#define mmDIG5_DIG_LANE_ENABLE                                                  0x4f79
-+#define mmDIG6_DIG_LANE_ENABLE                                                  0x5479
-+#define mmDIG7_DIG_LANE_ENABLE                                                  0x5679
-+#define mmDIG8_DIG_LANE_ENABLE                                                  0x5779
-+#define mmDIG_TEST_DEBUG_INDEX                                                  0x4a7a
-+#define mmDIG0_DIG_TEST_DEBUG_INDEX                                             0x4a7a
-+#define mmDIG1_DIG_TEST_DEBUG_INDEX                                             0x4b7a
-+#define mmDIG2_DIG_TEST_DEBUG_INDEX                                             0x4c7a
-+#define mmDIG3_DIG_TEST_DEBUG_INDEX                                             0x4d7a
-+#define mmDIG4_DIG_TEST_DEBUG_INDEX                                             0x4e7a
-+#define mmDIG5_DIG_TEST_DEBUG_INDEX                                             0x4f7a
-+#define mmDIG6_DIG_TEST_DEBUG_INDEX                                             0x547a
-+#define mmDIG7_DIG_TEST_DEBUG_INDEX                                             0x567a
-+#define mmDIG8_DIG_TEST_DEBUG_INDEX                                             0x577a
-+#define mmDIG_TEST_DEBUG_DATA                                                   0x4a7b
-+#define mmDIG0_DIG_TEST_DEBUG_DATA                                              0x4a7b
-+#define mmDIG1_DIG_TEST_DEBUG_DATA                                              0x4b7b
-+#define mmDIG2_DIG_TEST_DEBUG_DATA                                              0x4c7b
-+#define mmDIG3_DIG_TEST_DEBUG_DATA                                              0x4d7b
-+#define mmDIG4_DIG_TEST_DEBUG_DATA                                              0x4e7b
-+#define mmDIG5_DIG_TEST_DEBUG_DATA                                              0x4f7b
-+#define mmDIG6_DIG_TEST_DEBUG_DATA                                              0x547b
-+#define mmDIG7_DIG_TEST_DEBUG_DATA                                              0x567b
-+#define mmDIG8_DIG_TEST_DEBUG_DATA                                              0x577b
-+#define mmDIG_FE_TEST_DEBUG_INDEX                                               0x4a7c
-+#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX                                          0x4a7c
-+#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX                                          0x4b7c
-+#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX                                          0x4c7c
-+#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX                                          0x4d7c
-+#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX                                          0x4e7c
-+#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX                                          0x4f7c
-+#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX                                          0x547c
-+#define mmDIG7_DIG_FE_TEST_DEBUG_INDEX                                          0x567c
-+#define mmDIG8_DIG_FE_TEST_DEBUG_INDEX                                          0x577c
-+#define mmDIG_FE_TEST_DEBUG_DATA                                                0x4a7d
-+#define mmDIG0_DIG_FE_TEST_DEBUG_DATA                                           0x4a7d
-+#define mmDIG1_DIG_FE_TEST_DEBUG_DATA                                           0x4b7d
-+#define mmDIG2_DIG_FE_TEST_DEBUG_DATA                                           0x4c7d
-+#define mmDIG3_DIG_FE_TEST_DEBUG_DATA                                           0x4d7d
-+#define mmDIG4_DIG_FE_TEST_DEBUG_DATA                                           0x4e7d
-+#define mmDIG5_DIG_FE_TEST_DEBUG_DATA                                           0x4f7d
-+#define mmDIG6_DIG_FE_TEST_DEBUG_DATA                                           0x547d
-+#define mmDIG7_DIG_FE_TEST_DEBUG_DATA                                           0x567d
-+#define mmDIG8_DIG_FE_TEST_DEBUG_DATA                                           0x577d
-+#define mmDMCU_CTRL                                                             0x1600
-+#define mmDMCU_STATUS                                                           0x1601
-+#define mmDMCU_PC_START_ADDR                                                    0x1602
-+#define mmDMCU_FW_START_ADDR                                                    0x1603
-+#define mmDMCU_FW_END_ADDR                                                      0x1604
-+#define mmDMCU_FW_ISR_START_ADDR                                                0x1605
-+#define mmDMCU_FW_CS_HI                                                         0x1606
-+#define mmDMCU_FW_CS_LO                                                         0x1607
-+#define mmDMCU_RAM_ACCESS_CTRL                                                  0x1608
-+#define mmDMCU_ERAM_WR_CTRL                                                     0x1609
-+#define mmDMCU_ERAM_WR_DATA                                                     0x160a
-+#define mmDMCU_ERAM_RD_CTRL                                                     0x160b
-+#define mmDMCU_ERAM_RD_DATA                                                     0x160c
-+#define mmDMCU_IRAM_WR_CTRL                                                     0x160d
-+#define mmDMCU_IRAM_WR_DATA                                                     0x160e
-+#define mmDMCU_IRAM_RD_CTRL                                                     0x160f
-+#define mmDMCU_IRAM_RD_DATA                                                     0x1610
-+#define mmDMCU_EVENT_TRIGGER                                                    0x1611
-+#define mmDMCU_UC_INTERNAL_INT_STATUS                                           0x1612
-+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                         0x1613
-+#define mmDMCU_INTERRUPT_STATUS                                                 0x1614
-+#define mmDMCU_INTERRUPT_STATUS_1                                               0x1633
-+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                        0x1615
-+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                          0x1616
-+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                        0x1631
-+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                     0x1617
-+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                   0x1632
-+#define mmDC_DMCU_SCRATCH                                                       0x1618
-+#define mmDMCU_INT_CNT                                                          0x1619
-+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                        0x161a
-+#define mmDMCU_UC_CLK_GATING_CNTL                                               0x161b
-+#define mmMASTER_COMM_DATA_REG1                                                 0x161c
-+#define mmMASTER_COMM_DATA_REG2                                                 0x161d
-+#define mmMASTER_COMM_DATA_REG3                                                 0x161e
-+#define mmMASTER_COMM_CMD_REG                                                   0x161f
-+#define mmMASTER_COMM_CNTL_REG                                                  0x1620
-+#define mmSLAVE_COMM_DATA_REG1                                                  0x1621
-+#define mmSLAVE_COMM_DATA_REG2                                                  0x1622
-+#define mmSLAVE_COMM_DATA_REG3                                                  0x1623
-+#define mmSLAVE_COMM_CMD_REG                                                    0x1624
-+#define mmSLAVE_COMM_CNTL_REG                                                   0x1625
-+#define mmDMCU_TEST_DEBUG_INDEX                                                 0x1626
-+#define mmDMCU_TEST_DEBUG_DATA                                                  0x1627
-+#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                        0x1644
-+#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                        0x1645
-+#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                        0x1646
-+#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                        0x1647
-+#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                        0x1642
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                 0x1674
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                 0x1675
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                 0x1676
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                 0x1677
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                 0x1643
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                            0x1678
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                            0x1679
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                            0x167a
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                            0x167b
-+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                            0x1673
-+#define mmDMCU_DPRX_INTERRUPT_STATUS1                                           0x1634
-+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                    0x1635
-+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                               0x1636
-+#define mmDP_LINK_CNTL                                                          0x4aa0
-+#define mmDP0_DP_LINK_CNTL                                                      0x4aa0
-+#define mmDP1_DP_LINK_CNTL                                                      0x4ba0
-+#define mmDP2_DP_LINK_CNTL                                                      0x4ca0
-+#define mmDP3_DP_LINK_CNTL                                                      0x4da0
-+#define mmDP4_DP_LINK_CNTL                                                      0x4ea0
-+#define mmDP5_DP_LINK_CNTL                                                      0x4fa0
-+#define mmDP6_DP_LINK_CNTL                                                      0x54a0
-+#define mmDP7_DP_LINK_CNTL                                                      0x56a0
-+#define mmDP8_DP_LINK_CNTL                                                      0x57a0
-+#define mmDP_PIXEL_FORMAT                                                       0x4aa1
-+#define mmDP0_DP_PIXEL_FORMAT                                                   0x4aa1
-+#define mmDP1_DP_PIXEL_FORMAT                                                   0x4ba1
-+#define mmDP2_DP_PIXEL_FORMAT                                                   0x4ca1
-+#define mmDP3_DP_PIXEL_FORMAT                                                   0x4da1
-+#define mmDP4_DP_PIXEL_FORMAT                                                   0x4ea1
-+#define mmDP5_DP_PIXEL_FORMAT                                                   0x4fa1
-+#define mmDP6_DP_PIXEL_FORMAT                                                   0x54a1
-+#define mmDP7_DP_PIXEL_FORMAT                                                   0x56a1
-+#define mmDP8_DP_PIXEL_FORMAT                                                   0x57a1
-+#define mmDP_MSA_COLORIMETRY                                                    0x4aa2
-+#define mmDP0_DP_MSA_COLORIMETRY                                                0x4aa2
-+#define mmDP1_DP_MSA_COLORIMETRY                                                0x4ba2
-+#define mmDP2_DP_MSA_COLORIMETRY                                                0x4ca2
-+#define mmDP3_DP_MSA_COLORIMETRY                                                0x4da2
-+#define mmDP4_DP_MSA_COLORIMETRY                                                0x4ea2
-+#define mmDP5_DP_MSA_COLORIMETRY                                                0x4fa2
-+#define mmDP6_DP_MSA_COLORIMETRY                                                0x54a2
-+#define mmDP7_DP_MSA_COLORIMETRY                                                0x56a2
-+#define mmDP8_DP_MSA_COLORIMETRY                                                0x57a2
-+#define mmDP_CONFIG                                                             0x4aa3
-+#define mmDP0_DP_CONFIG                                                         0x4aa3
-+#define mmDP1_DP_CONFIG                                                         0x4ba3
-+#define mmDP2_DP_CONFIG                                                         0x4ca3
-+#define mmDP3_DP_CONFIG                                                         0x4da3
-+#define mmDP4_DP_CONFIG                                                         0x4ea3
-+#define mmDP5_DP_CONFIG                                                         0x4fa3
-+#define mmDP6_DP_CONFIG                                                         0x54a3
-+#define mmDP7_DP_CONFIG                                                         0x56a3
-+#define mmDP8_DP_CONFIG                                                         0x57a3
-+#define mmDP_VID_STREAM_CNTL                                                    0x4aa4
-+#define mmDP0_DP_VID_STREAM_CNTL                                                0x4aa4
-+#define mmDP1_DP_VID_STREAM_CNTL                                                0x4ba4
-+#define mmDP2_DP_VID_STREAM_CNTL                                                0x4ca4
-+#define mmDP3_DP_VID_STREAM_CNTL                                                0x4da4
-+#define mmDP4_DP_VID_STREAM_CNTL                                                0x4ea4
-+#define mmDP5_DP_VID_STREAM_CNTL                                                0x4fa4
-+#define mmDP6_DP_VID_STREAM_CNTL                                                0x54a4
-+#define mmDP7_DP_VID_STREAM_CNTL                                                0x56a4
-+#define mmDP8_DP_VID_STREAM_CNTL                                                0x57a4
-+#define mmDP_STEER_FIFO                                                         0x4aa5
-+#define mmDP0_DP_STEER_FIFO                                                     0x4aa5
-+#define mmDP1_DP_STEER_FIFO                                                     0x4ba5
-+#define mmDP2_DP_STEER_FIFO                                                     0x4ca5
-+#define mmDP3_DP_STEER_FIFO                                                     0x4da5
-+#define mmDP4_DP_STEER_FIFO                                                     0x4ea5
-+#define mmDP5_DP_STEER_FIFO                                                     0x4fa5
-+#define mmDP6_DP_STEER_FIFO                                                     0x54a5
-+#define mmDP7_DP_STEER_FIFO                                                     0x56a5
-+#define mmDP8_DP_STEER_FIFO                                                     0x57a5
-+#define mmDP_MSA_MISC                                                           0x4aa6
-+#define mmDP0_DP_MSA_MISC                                                       0x4aa6
-+#define mmDP1_DP_MSA_MISC                                                       0x4ba6
-+#define mmDP2_DP_MSA_MISC                                                       0x4ca6
-+#define mmDP3_DP_MSA_MISC                                                       0x4da6
-+#define mmDP4_DP_MSA_MISC                                                       0x4ea6
-+#define mmDP5_DP_MSA_MISC                                                       0x4fa6
-+#define mmDP6_DP_MSA_MISC                                                       0x54a6
-+#define mmDP7_DP_MSA_MISC                                                       0x56a6
-+#define mmDP8_DP_MSA_MISC                                                       0x57a6
-+#define mmDP_VID_TIMING                                                         0x4aa8
-+#define mmDP0_DP_VID_TIMING                                                     0x4aa8
-+#define mmDP1_DP_VID_TIMING                                                     0x4ba8
-+#define mmDP2_DP_VID_TIMING                                                     0x4ca8
-+#define mmDP3_DP_VID_TIMING                                                     0x4da8
-+#define mmDP4_DP_VID_TIMING                                                     0x4ea8
-+#define mmDP5_DP_VID_TIMING                                                     0x4fa8
-+#define mmDP6_DP_VID_TIMING                                                     0x54a8
-+#define mmDP7_DP_VID_TIMING                                                     0x56a8
-+#define mmDP8_DP_VID_TIMING                                                     0x57a8
-+#define mmDP_VID_N                                                              0x4aa9
-+#define mmDP0_DP_VID_N                                                          0x4aa9
-+#define mmDP1_DP_VID_N                                                          0x4ba9
-+#define mmDP2_DP_VID_N                                                          0x4ca9
-+#define mmDP3_DP_VID_N                                                          0x4da9
-+#define mmDP4_DP_VID_N                                                          0x4ea9
-+#define mmDP5_DP_VID_N                                                          0x4fa9
-+#define mmDP6_DP_VID_N                                                          0x54a9
-+#define mmDP7_DP_VID_N                                                          0x56a9
-+#define mmDP8_DP_VID_N                                                          0x57a9
-+#define mmDP_VID_M                                                              0x4aaa
-+#define mmDP0_DP_VID_M                                                          0x4aaa
-+#define mmDP1_DP_VID_M                                                          0x4baa
-+#define mmDP2_DP_VID_M                                                          0x4caa
-+#define mmDP3_DP_VID_M                                                          0x4daa
-+#define mmDP4_DP_VID_M                                                          0x4eaa
-+#define mmDP5_DP_VID_M                                                          0x4faa
-+#define mmDP6_DP_VID_M                                                          0x54aa
-+#define mmDP7_DP_VID_M                                                          0x56aa
-+#define mmDP8_DP_VID_M                                                          0x57aa
-+#define mmDP_LINK_FRAMING_CNTL                                                  0x4aab
-+#define mmDP0_DP_LINK_FRAMING_CNTL                                              0x4aab
-+#define mmDP1_DP_LINK_FRAMING_CNTL                                              0x4bab
-+#define mmDP2_DP_LINK_FRAMING_CNTL                                              0x4cab
-+#define mmDP3_DP_LINK_FRAMING_CNTL                                              0x4dab
-+#define mmDP4_DP_LINK_FRAMING_CNTL                                              0x4eab
-+#define mmDP5_DP_LINK_FRAMING_CNTL                                              0x4fab
-+#define mmDP6_DP_LINK_FRAMING_CNTL                                              0x54ab
-+#define mmDP7_DP_LINK_FRAMING_CNTL                                              0x56ab
-+#define mmDP8_DP_LINK_FRAMING_CNTL                                              0x57ab
-+#define mmDP_HBR2_EYE_PATTERN                                                   0x4aac
-+#define mmDP0_DP_HBR2_EYE_PATTERN                                               0x4aac
-+#define mmDP1_DP_HBR2_EYE_PATTERN                                               0x4bac
-+#define mmDP2_DP_HBR2_EYE_PATTERN                                               0x4cac
-+#define mmDP3_DP_HBR2_EYE_PATTERN                                               0x4dac
-+#define mmDP4_DP_HBR2_EYE_PATTERN                                               0x4eac
-+#define mmDP5_DP_HBR2_EYE_PATTERN                                               0x4fac
-+#define mmDP6_DP_HBR2_EYE_PATTERN                                               0x54ac
-+#define mmDP7_DP_HBR2_EYE_PATTERN                                               0x56ac
-+#define mmDP8_DP_HBR2_EYE_PATTERN                                               0x57ac
-+#define mmDP_VID_MSA_VBID                                                       0x4aad
-+#define mmDP0_DP_VID_MSA_VBID                                                   0x4aad
-+#define mmDP1_DP_VID_MSA_VBID                                                   0x4bad
-+#define mmDP2_DP_VID_MSA_VBID                                                   0x4cad
-+#define mmDP3_DP_VID_MSA_VBID                                                   0x4dad
-+#define mmDP4_DP_VID_MSA_VBID                                                   0x4ead
-+#define mmDP5_DP_VID_MSA_VBID                                                   0x4fad
-+#define mmDP6_DP_VID_MSA_VBID                                                   0x54ad
-+#define mmDP7_DP_VID_MSA_VBID                                                   0x56ad
-+#define mmDP8_DP_VID_MSA_VBID                                                   0x57ad
-+#define mmDP_VID_INTERRUPT_CNTL                                                 0x4aae
-+#define mmDP0_DP_VID_INTERRUPT_CNTL                                             0x4aae
-+#define mmDP1_DP_VID_INTERRUPT_CNTL                                             0x4bae
-+#define mmDP2_DP_VID_INTERRUPT_CNTL                                             0x4cae
-+#define mmDP3_DP_VID_INTERRUPT_CNTL                                             0x4dae
-+#define mmDP4_DP_VID_INTERRUPT_CNTL                                             0x4eae
-+#define mmDP5_DP_VID_INTERRUPT_CNTL                                             0x4fae
-+#define mmDP6_DP_VID_INTERRUPT_CNTL                                             0x54ae
-+#define mmDP7_DP_VID_INTERRUPT_CNTL                                             0x56ae
-+#define mmDP8_DP_VID_INTERRUPT_CNTL                                             0x57ae
-+#define mmDP_DPHY_CNTL                                                          0x4aaf
-+#define mmDP0_DP_DPHY_CNTL                                                      0x4aaf
-+#define mmDP1_DP_DPHY_CNTL                                                      0x4baf
-+#define mmDP2_DP_DPHY_CNTL                                                      0x4caf
-+#define mmDP3_DP_DPHY_CNTL                                                      0x4daf
-+#define mmDP4_DP_DPHY_CNTL                                                      0x4eaf
-+#define mmDP5_DP_DPHY_CNTL                                                      0x4faf
-+#define mmDP6_DP_DPHY_CNTL                                                      0x54af
-+#define mmDP7_DP_DPHY_CNTL                                                      0x56af
-+#define mmDP8_DP_DPHY_CNTL                                                      0x57af
-+#define mmDP_DPHY_TRAINING_PATTERN_SEL                                          0x4ab0
-+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4ab0
-+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4bb0
-+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4cb0
-+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4db0
-+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4eb0
-+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4fb0
-+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                      0x54b0
-+#define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL                                      0x56b0
-+#define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL                                      0x57b0
-+#define mmDP_DPHY_SYM0                                                          0x4ab1
-+#define mmDP0_DP_DPHY_SYM0                                                      0x4ab1
-+#define mmDP1_DP_DPHY_SYM0                                                      0x4bb1
-+#define mmDP2_DP_DPHY_SYM0                                                      0x4cb1
-+#define mmDP3_DP_DPHY_SYM0                                                      0x4db1
-+#define mmDP4_DP_DPHY_SYM0                                                      0x4eb1
-+#define mmDP5_DP_DPHY_SYM0                                                      0x4fb1
-+#define mmDP6_DP_DPHY_SYM0                                                      0x54b1
-+#define mmDP7_DP_DPHY_SYM0                                                      0x56b1
-+#define mmDP8_DP_DPHY_SYM0                                                      0x57b1
-+#define mmDP_DPHY_SYM1                                                          0x4ab2
-+#define mmDP0_DP_DPHY_SYM1                                                      0x4ab2
-+#define mmDP1_DP_DPHY_SYM1                                                      0x4bb2
-+#define mmDP2_DP_DPHY_SYM1                                                      0x4cb2
-+#define mmDP3_DP_DPHY_SYM1                                                      0x4db2
-+#define mmDP4_DP_DPHY_SYM1                                                      0x4eb2
-+#define mmDP5_DP_DPHY_SYM1                                                      0x4fb2
-+#define mmDP6_DP_DPHY_SYM1                                                      0x54b2
-+#define mmDP7_DP_DPHY_SYM1                                                      0x56b2
-+#define mmDP8_DP_DPHY_SYM1                                                      0x57b2
-+#define mmDP_DPHY_SYM2                                                          0x4ab3
-+#define mmDP0_DP_DPHY_SYM2                                                      0x4ab3
-+#define mmDP1_DP_DPHY_SYM2                                                      0x4bb3
-+#define mmDP2_DP_DPHY_SYM2                                                      0x4cb3
-+#define mmDP3_DP_DPHY_SYM2                                                      0x4db3
-+#define mmDP4_DP_DPHY_SYM2                                                      0x4eb3
-+#define mmDP5_DP_DPHY_SYM2                                                      0x4fb3
-+#define mmDP6_DP_DPHY_SYM2                                                      0x54b3
-+#define mmDP7_DP_DPHY_SYM2                                                      0x56b3
-+#define mmDP8_DP_DPHY_SYM2                                                      0x57b3
-+#define mmDP_DPHY_8B10B_CNTL                                                    0x4ab4
-+#define mmDP0_DP_DPHY_8B10B_CNTL                                                0x4ab4
-+#define mmDP1_DP_DPHY_8B10B_CNTL                                                0x4bb4
-+#define mmDP2_DP_DPHY_8B10B_CNTL                                                0x4cb4
-+#define mmDP3_DP_DPHY_8B10B_CNTL                                                0x4db4
-+#define mmDP4_DP_DPHY_8B10B_CNTL                                                0x4eb4
-+#define mmDP5_DP_DPHY_8B10B_CNTL                                                0x4fb4
-+#define mmDP6_DP_DPHY_8B10B_CNTL                                                0x54b4
-+#define mmDP7_DP_DPHY_8B10B_CNTL                                                0x56b4
-+#define mmDP8_DP_DPHY_8B10B_CNTL                                                0x57b4
-+#define mmDP_DPHY_PRBS_CNTL                                                     0x4ab5
-+#define mmDP0_DP_DPHY_PRBS_CNTL                                                 0x4ab5
-+#define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
-+#define mmDP2_DP_DPHY_PRBS_CNTL                                                 0x4cb5
-+#define mmDP3_DP_DPHY_PRBS_CNTL                                                 0x4db5
-+#define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
-+#define mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4fb5
-+#define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5
-+#define mmDP7_DP_DPHY_PRBS_CNTL                                                 0x56b5
-+#define mmDP8_DP_DPHY_PRBS_CNTL                                                 0x57b5
-+#define mmDP_DPHY_BS_SR_SWAP_CNTL                                               0x4adc
-+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4adc
-+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4bdc
-+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4cdc
-+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4ddc
-+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4edc
-+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4fdc
-+#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                                           0x54dc
-+#define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL                                           0x56dc
-+#define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL                                           0x57dc
-+#define mmDP_DPHY_CRC_EN                                                        0x4ab7
-+#define mmDP0_DP_DPHY_CRC_EN                                                    0x4ab7
-+#define mmDP1_DP_DPHY_CRC_EN                                                    0x4bb7
-+#define mmDP2_DP_DPHY_CRC_EN                                                    0x4cb7
-+#define mmDP3_DP_DPHY_CRC_EN                                                    0x4db7
-+#define mmDP4_DP_DPHY_CRC_EN                                                    0x4eb7
-+#define mmDP5_DP_DPHY_CRC_EN                                                    0x4fb7
-+#define mmDP6_DP_DPHY_CRC_EN                                                    0x54b7
-+#define mmDP7_DP_DPHY_CRC_EN                                                    0x56b7
-+#define mmDP8_DP_DPHY_CRC_EN                                                    0x57b7
-+#define mmDP_DPHY_CRC_CNTL                                                      0x4ab8
-+#define mmDP0_DP_DPHY_CRC_CNTL                                                  0x4ab8
-+#define mmDP1_DP_DPHY_CRC_CNTL                                                  0x4bb8
-+#define mmDP2_DP_DPHY_CRC_CNTL                                                  0x4cb8
-+#define mmDP3_DP_DPHY_CRC_CNTL                                                  0x4db8
-+#define mmDP4_DP_DPHY_CRC_CNTL                                                  0x4eb8
-+#define mmDP5_DP_DPHY_CRC_CNTL                                                  0x4fb8
-+#define mmDP6_DP_DPHY_CRC_CNTL                                                  0x54b8
-+#define mmDP7_DP_DPHY_CRC_CNTL                                                  0x56b8
-+#define mmDP8_DP_DPHY_CRC_CNTL                                                  0x57b8
-+#define mmDP_DPHY_CRC_RESULT                                                    0x4ab9
-+#define mmDP0_DP_DPHY_CRC_RESULT                                                0x4ab9
-+#define mmDP1_DP_DPHY_CRC_RESULT                                                0x4bb9
-+#define mmDP2_DP_DPHY_CRC_RESULT                                                0x4cb9
-+#define mmDP3_DP_DPHY_CRC_RESULT                                                0x4db9
-+#define mmDP4_DP_DPHY_CRC_RESULT                                                0x4eb9
-+#define mmDP5_DP_DPHY_CRC_RESULT                                                0x4fb9
-+#define mmDP6_DP_DPHY_CRC_RESULT                                                0x54b9
-+#define mmDP7_DP_DPHY_CRC_RESULT                                                0x56b9
-+#define mmDP8_DP_DPHY_CRC_RESULT                                                0x57b9
-+#define mmDP_DPHY_CRC_MST_CNTL                                                  0x4aba
-+#define mmDP0_DP_DPHY_CRC_MST_CNTL                                              0x4aba
-+#define mmDP1_DP_DPHY_CRC_MST_CNTL                                              0x4bba
-+#define mmDP2_DP_DPHY_CRC_MST_CNTL                                              0x4cba
-+#define mmDP3_DP_DPHY_CRC_MST_CNTL                                              0x4dba
-+#define mmDP4_DP_DPHY_CRC_MST_CNTL                                              0x4eba
-+#define mmDP5_DP_DPHY_CRC_MST_CNTL                                              0x4fba
-+#define mmDP6_DP_DPHY_CRC_MST_CNTL                                              0x54ba
-+#define mmDP7_DP_DPHY_CRC_MST_CNTL                                              0x56ba
-+#define mmDP8_DP_DPHY_CRC_MST_CNTL                                              0x57ba
-+#define mmDP_DPHY_CRC_MST_STATUS                                                0x4abb
-+#define mmDP0_DP_DPHY_CRC_MST_STATUS                                            0x4abb
-+#define mmDP1_DP_DPHY_CRC_MST_STATUS                                            0x4bbb
-+#define mmDP2_DP_DPHY_CRC_MST_STATUS                                            0x4cbb
-+#define mmDP3_DP_DPHY_CRC_MST_STATUS                                            0x4dbb
-+#define mmDP4_DP_DPHY_CRC_MST_STATUS                                            0x4ebb
-+#define mmDP5_DP_DPHY_CRC_MST_STATUS                                            0x4fbb
-+#define mmDP6_DP_DPHY_CRC_MST_STATUS                                            0x54bb
-+#define mmDP7_DP_DPHY_CRC_MST_STATUS                                            0x56bb
-+#define mmDP8_DP_DPHY_CRC_MST_STATUS                                            0x57bb
-+#define mmDP_DPHY_FAST_TRAINING                                                 0x4abc
-+#define mmDP0_DP_DPHY_FAST_TRAINING                                             0x4abc
-+#define mmDP1_DP_DPHY_FAST_TRAINING                                             0x4bbc
-+#define mmDP2_DP_DPHY_FAST_TRAINING                                             0x4cbc
-+#define mmDP3_DP_DPHY_FAST_TRAINING                                             0x4dbc
-+#define mmDP4_DP_DPHY_FAST_TRAINING                                             0x4ebc
-+#define mmDP5_DP_DPHY_FAST_TRAINING                                             0x4fbc
-+#define mmDP6_DP_DPHY_FAST_TRAINING                                             0x54bc
-+#define mmDP7_DP_DPHY_FAST_TRAINING                                             0x56bc
-+#define mmDP8_DP_DPHY_FAST_TRAINING                                             0x57bc
-+#define mmDP_DPHY_FAST_TRAINING_STATUS                                          0x4abd
-+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                      0x4abd
-+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                      0x4bbd
-+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                      0x4cbd
-+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                      0x4dbd
-+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                      0x4ebd
-+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                      0x4fbd
-+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                      0x54bd
-+#define mmDP7_DP_DPHY_FAST_TRAINING_STATUS                                      0x56bd
-+#define mmDP8_DP_DPHY_FAST_TRAINING_STATUS                                      0x57bd
-+#define mmDP_DPHY_HBR2_PATTERN_CONTROL                                          0x4add
-+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4add
-+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4bdd
-+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4cdd
-+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4ddd
-+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4edd
-+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4fdd
-+#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x54dd
-+#define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x56dd
-+#define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x57dd
-+#define mmDP_MSA_V_TIMING_OVERRIDE1                                             0x4abe
-+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                         0x4abe
-+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                         0x4bbe
-+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                         0x4cbe
-+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                         0x4dbe
-+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                         0x4ebe
-+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                         0x4fbe
-+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                         0x54be
-+#define mmDP7_DP_MSA_V_TIMING_OVERRIDE1                                         0x56be
-+#define mmDP8_DP_MSA_V_TIMING_OVERRIDE1                                         0x57be
-+#define mmDP_MSA_V_TIMING_OVERRIDE2                                             0x4abf
-+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                         0x4abf
-+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                         0x4bbf
-+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                         0x4cbf
-+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                         0x4dbf
-+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                         0x4ebf
-+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                         0x4fbf
-+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                         0x54bf
-+#define mmDP7_DP_MSA_V_TIMING_OVERRIDE2                                         0x56bf
-+#define mmDP8_DP_MSA_V_TIMING_OVERRIDE2                                         0x57bf
-+#define mmDP_SEC_CNTL                                                           0x4ac3
-+#define mmDP0_DP_SEC_CNTL                                                       0x4ac3
-+#define mmDP1_DP_SEC_CNTL                                                       0x4bc3
-+#define mmDP2_DP_SEC_CNTL                                                       0x4cc3
-+#define mmDP3_DP_SEC_CNTL                                                       0x4dc3
-+#define mmDP4_DP_SEC_CNTL                                                       0x4ec3
-+#define mmDP5_DP_SEC_CNTL                                                       0x4fc3
-+#define mmDP6_DP_SEC_CNTL                                                       0x54c3
-+#define mmDP7_DP_SEC_CNTL                                                       0x56c3
-+#define mmDP8_DP_SEC_CNTL                                                       0x57c3
-+#define mmDP_SEC_CNTL1                                                          0x4ac4
-+#define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
-+#define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
-+#define mmDP2_DP_SEC_CNTL1                                                      0x4cc4
-+#define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
-+#define mmDP4_DP_SEC_CNTL1                                                      0x4ec4
-+#define mmDP5_DP_SEC_CNTL1                                                      0x4fc4
-+#define mmDP6_DP_SEC_CNTL1                                                      0x54c4
-+#define mmDP7_DP_SEC_CNTL1                                                      0x56c4
-+#define mmDP8_DP_SEC_CNTL1                                                      0x57c4
-+#define mmDP_SEC_FRAMING1                                                       0x4ac5
-+#define mmDP0_DP_SEC_FRAMING1                                                   0x4ac5
-+#define mmDP1_DP_SEC_FRAMING1                                                   0x4bc5
-+#define mmDP2_DP_SEC_FRAMING1                                                   0x4cc5
-+#define mmDP3_DP_SEC_FRAMING1                                                   0x4dc5
-+#define mmDP4_DP_SEC_FRAMING1                                                   0x4ec5
-+#define mmDP5_DP_SEC_FRAMING1                                                   0x4fc5
-+#define mmDP6_DP_SEC_FRAMING1                                                   0x54c5
-+#define mmDP7_DP_SEC_FRAMING1                                                   0x56c5
-+#define mmDP8_DP_SEC_FRAMING1                                                   0x57c5
-+#define mmDP_SEC_FRAMING2                                                       0x4ac6
-+#define mmDP0_DP_SEC_FRAMING2                                                   0x4ac6
-+#define mmDP1_DP_SEC_FRAMING2                                                   0x4bc6
-+#define mmDP2_DP_SEC_FRAMING2                                                   0x4cc6
-+#define mmDP3_DP_SEC_FRAMING2                                                   0x4dc6
-+#define mmDP4_DP_SEC_FRAMING2                                                   0x4ec6
-+#define mmDP5_DP_SEC_FRAMING2                                                   0x4fc6
-+#define mmDP6_DP_SEC_FRAMING2                                                   0x54c6
-+#define mmDP7_DP_SEC_FRAMING2                                                   0x56c6
-+#define mmDP8_DP_SEC_FRAMING2                                                   0x57c6
-+#define mmDP_SEC_FRAMING3                                                       0x4ac7
-+#define mmDP0_DP_SEC_FRAMING3                                                   0x4ac7
-+#define mmDP1_DP_SEC_FRAMING3                                                   0x4bc7
-+#define mmDP2_DP_SEC_FRAMING3                                                   0x4cc7
-+#define mmDP3_DP_SEC_FRAMING3                                                   0x4dc7
-+#define mmDP4_DP_SEC_FRAMING3                                                   0x4ec7
-+#define mmDP5_DP_SEC_FRAMING3                                                   0x4fc7
-+#define mmDP6_DP_SEC_FRAMING3                                                   0x54c7
-+#define mmDP7_DP_SEC_FRAMING3                                                   0x56c7
-+#define mmDP8_DP_SEC_FRAMING3                                                   0x57c7
-+#define mmDP_SEC_FRAMING4                                                       0x4ac8
-+#define mmDP0_DP_SEC_FRAMING4                                                   0x4ac8
-+#define mmDP1_DP_SEC_FRAMING4                                                   0x4bc8
-+#define mmDP2_DP_SEC_FRAMING4                                                   0x4cc8
-+#define mmDP3_DP_SEC_FRAMING4                                                   0x4dc8
-+#define mmDP4_DP_SEC_FRAMING4                                                   0x4ec8
-+#define mmDP5_DP_SEC_FRAMING4                                                   0x4fc8
-+#define mmDP6_DP_SEC_FRAMING4                                                   0x54c8
-+#define mmDP7_DP_SEC_FRAMING4                                                   0x56c8
-+#define mmDP8_DP_SEC_FRAMING4                                                   0x57c8
-+#define mmDP_SEC_AUD_N                                                          0x4ac9
-+#define mmDP0_DP_SEC_AUD_N                                                      0x4ac9
-+#define mmDP1_DP_SEC_AUD_N                                                      0x4bc9
-+#define mmDP2_DP_SEC_AUD_N                                                      0x4cc9
-+#define mmDP3_DP_SEC_AUD_N                                                      0x4dc9
-+#define mmDP4_DP_SEC_AUD_N                                                      0x4ec9
-+#define mmDP5_DP_SEC_AUD_N                                                      0x4fc9
-+#define mmDP6_DP_SEC_AUD_N                                                      0x54c9
-+#define mmDP7_DP_SEC_AUD_N                                                      0x56c9
-+#define mmDP8_DP_SEC_AUD_N                                                      0x57c9
-+#define mmDP_SEC_AUD_N_READBACK                                                 0x4aca
-+#define mmDP0_DP_SEC_AUD_N_READBACK                                             0x4aca
-+#define mmDP1_DP_SEC_AUD_N_READBACK                                             0x4bca
-+#define mmDP2_DP_SEC_AUD_N_READBACK                                             0x4cca
-+#define mmDP3_DP_SEC_AUD_N_READBACK                                             0x4dca
-+#define mmDP4_DP_SEC_AUD_N_READBACK                                             0x4eca
-+#define mmDP5_DP_SEC_AUD_N_READBACK                                             0x4fca
-+#define mmDP6_DP_SEC_AUD_N_READBACK                                             0x54ca
-+#define mmDP7_DP_SEC_AUD_N_READBACK                                             0x56ca
-+#define mmDP8_DP_SEC_AUD_N_READBACK                                             0x57ca
-+#define mmDP_SEC_AUD_M                                                          0x4acb
-+#define mmDP0_DP_SEC_AUD_M                                                      0x4acb
-+#define mmDP1_DP_SEC_AUD_M                                                      0x4bcb
-+#define mmDP2_DP_SEC_AUD_M                                                      0x4ccb
-+#define mmDP3_DP_SEC_AUD_M                                                      0x4dcb
-+#define mmDP4_DP_SEC_AUD_M                                                      0x4ecb
-+#define mmDP5_DP_SEC_AUD_M                                                      0x4fcb
-+#define mmDP6_DP_SEC_AUD_M                                                      0x54cb
-+#define mmDP7_DP_SEC_AUD_M                                                      0x56cb
-+#define mmDP8_DP_SEC_AUD_M                                                      0x57cb
-+#define mmDP_SEC_AUD_M_READBACK                                                 0x4acc
-+#define mmDP0_DP_SEC_AUD_M_READBACK                                             0x4acc
-+#define mmDP1_DP_SEC_AUD_M_READBACK                                             0x4bcc
-+#define mmDP2_DP_SEC_AUD_M_READBACK                                             0x4ccc
-+#define mmDP3_DP_SEC_AUD_M_READBACK                                             0x4dcc
-+#define mmDP4_DP_SEC_AUD_M_READBACK                                             0x4ecc
-+#define mmDP5_DP_SEC_AUD_M_READBACK                                             0x4fcc
-+#define mmDP6_DP_SEC_AUD_M_READBACK                                             0x54cc
-+#define mmDP7_DP_SEC_AUD_M_READBACK                                             0x56cc
-+#define mmDP8_DP_SEC_AUD_M_READBACK                                             0x57cc
-+#define mmDP_SEC_TIMESTAMP                                                      0x4acd
-+#define mmDP0_DP_SEC_TIMESTAMP                                                  0x4acd
-+#define mmDP1_DP_SEC_TIMESTAMP                                                  0x4bcd
-+#define mmDP2_DP_SEC_TIMESTAMP                                                  0x4ccd
-+#define mmDP3_DP_SEC_TIMESTAMP                                                  0x4dcd
-+#define mmDP4_DP_SEC_TIMESTAMP                                                  0x4ecd
-+#define mmDP5_DP_SEC_TIMESTAMP                                                  0x4fcd
-+#define mmDP6_DP_SEC_TIMESTAMP                                                  0x54cd
-+#define mmDP7_DP_SEC_TIMESTAMP                                                  0x56cd
-+#define mmDP8_DP_SEC_TIMESTAMP                                                  0x57cd
-+#define mmDP_SEC_PACKET_CNTL                                                    0x4ace
-+#define mmDP0_DP_SEC_PACKET_CNTL                                                0x4ace
-+#define mmDP1_DP_SEC_PACKET_CNTL                                                0x4bce
-+#define mmDP2_DP_SEC_PACKET_CNTL                                                0x4cce
-+#define mmDP3_DP_SEC_PACKET_CNTL                                                0x4dce
-+#define mmDP4_DP_SEC_PACKET_CNTL                                                0x4ece
-+#define mmDP5_DP_SEC_PACKET_CNTL                                                0x4fce
-+#define mmDP6_DP_SEC_PACKET_CNTL                                                0x54ce
-+#define mmDP7_DP_SEC_PACKET_CNTL                                                0x56ce
-+#define mmDP8_DP_SEC_PACKET_CNTL                                                0x57ce
-+#define mmDP_MSE_RATE_CNTL                                                      0x4acf
-+#define mmDP0_DP_MSE_RATE_CNTL                                                  0x4acf
-+#define mmDP1_DP_MSE_RATE_CNTL                                                  0x4bcf
-+#define mmDP2_DP_MSE_RATE_CNTL                                                  0x4ccf
-+#define mmDP3_DP_MSE_RATE_CNTL                                                  0x4dcf
-+#define mmDP4_DP_MSE_RATE_CNTL                                                  0x4ecf
-+#define mmDP5_DP_MSE_RATE_CNTL                                                  0x4fcf
-+#define mmDP6_DP_MSE_RATE_CNTL                                                  0x54cf
-+#define mmDP7_DP_MSE_RATE_CNTL                                                  0x56cf
-+#define mmDP8_DP_MSE_RATE_CNTL                                                  0x57cf
-+#define mmDP_MSE_RATE_UPDATE                                                    0x4ad1
-+#define mmDP0_DP_MSE_RATE_UPDATE                                                0x4ad1
-+#define mmDP1_DP_MSE_RATE_UPDATE                                                0x4bd1
-+#define mmDP2_DP_MSE_RATE_UPDATE                                                0x4cd1
-+#define mmDP3_DP_MSE_RATE_UPDATE                                                0x4dd1
-+#define mmDP4_DP_MSE_RATE_UPDATE                                                0x4ed1
-+#define mmDP5_DP_MSE_RATE_UPDATE                                                0x4fd1
-+#define mmDP6_DP_MSE_RATE_UPDATE                                                0x54d1
-+#define mmDP7_DP_MSE_RATE_UPDATE                                                0x56d1
-+#define mmDP8_DP_MSE_RATE_UPDATE                                                0x57d1
-+#define mmDP_MSE_SAT0                                                           0x4ad2
-+#define mmDP0_DP_MSE_SAT0                                                       0x4ad2
-+#define mmDP1_DP_MSE_SAT0                                                       0x4bd2
-+#define mmDP2_DP_MSE_SAT0                                                       0x4cd2
-+#define mmDP3_DP_MSE_SAT0                                                       0x4dd2
-+#define mmDP4_DP_MSE_SAT0                                                       0x4ed2
-+#define mmDP5_DP_MSE_SAT0                                                       0x4fd2
-+#define mmDP6_DP_MSE_SAT0                                                       0x54d2
-+#define mmDP7_DP_MSE_SAT0                                                       0x56d2
-+#define mmDP8_DP_MSE_SAT0                                                       0x57d2
-+#define mmDP_MSE_SAT1                                                           0x4ad3
-+#define mmDP0_DP_MSE_SAT1                                                       0x4ad3
-+#define mmDP1_DP_MSE_SAT1                                                       0x4bd3
-+#define mmDP2_DP_MSE_SAT1                                                       0x4cd3
-+#define mmDP3_DP_MSE_SAT1                                                       0x4dd3
-+#define mmDP4_DP_MSE_SAT1                                                       0x4ed3
-+#define mmDP5_DP_MSE_SAT1                                                       0x4fd3
-+#define mmDP6_DP_MSE_SAT1                                                       0x54d3
-+#define mmDP7_DP_MSE_SAT1                                                       0x56d3
-+#define mmDP8_DP_MSE_SAT1                                                       0x57d3
-+#define mmDP_MSE_SAT2                                                           0x4ad4
-+#define mmDP0_DP_MSE_SAT2                                                       0x4ad4
-+#define mmDP1_DP_MSE_SAT2                                                       0x4bd4
-+#define mmDP2_DP_MSE_SAT2                                                       0x4cd4
-+#define mmDP3_DP_MSE_SAT2                                                       0x4dd4
-+#define mmDP4_DP_MSE_SAT2                                                       0x4ed4
-+#define mmDP5_DP_MSE_SAT2                                                       0x4fd4
-+#define mmDP6_DP_MSE_SAT2                                                       0x54d4
-+#define mmDP7_DP_MSE_SAT2                                                       0x56d4
-+#define mmDP8_DP_MSE_SAT2                                                       0x57d4
-+#define mmDP_MSE_SAT_UPDATE                                                     0x4ad5
-+#define mmDP0_DP_MSE_SAT_UPDATE                                                 0x4ad5
-+#define mmDP1_DP_MSE_SAT_UPDATE                                                 0x4bd5
-+#define mmDP2_DP_MSE_SAT_UPDATE                                                 0x4cd5
-+#define mmDP3_DP_MSE_SAT_UPDATE                                                 0x4dd5
-+#define mmDP4_DP_MSE_SAT_UPDATE                                                 0x4ed5
-+#define mmDP5_DP_MSE_SAT_UPDATE                                                 0x4fd5
-+#define mmDP6_DP_MSE_SAT_UPDATE                                                 0x54d5
-+#define mmDP7_DP_MSE_SAT_UPDATE                                                 0x56d5
-+#define mmDP8_DP_MSE_SAT_UPDATE                                                 0x57d5
-+#define mmDP_MSE_LINK_TIMING                                                    0x4ad6
-+#define mmDP0_DP_MSE_LINK_TIMING                                                0x4ad6
-+#define mmDP1_DP_MSE_LINK_TIMING                                                0x4bd6
-+#define mmDP2_DP_MSE_LINK_TIMING                                                0x4cd6
-+#define mmDP3_DP_MSE_LINK_TIMING                                                0x4dd6
-+#define mmDP4_DP_MSE_LINK_TIMING                                                0x4ed6
-+#define mmDP5_DP_MSE_LINK_TIMING                                                0x4fd6
-+#define mmDP6_DP_MSE_LINK_TIMING                                                0x54d6
-+#define mmDP7_DP_MSE_LINK_TIMING                                                0x56d6
-+#define mmDP8_DP_MSE_LINK_TIMING                                                0x57d6
-+#define mmDP_MSE_MISC_CNTL                                                      0x4ad7
-+#define mmDP0_DP_MSE_MISC_CNTL                                                  0x4ad7
-+#define mmDP1_DP_MSE_MISC_CNTL                                                  0x4bd7
-+#define mmDP2_DP_MSE_MISC_CNTL                                                  0x4cd7
-+#define mmDP3_DP_MSE_MISC_CNTL                                                  0x4dd7
-+#define mmDP4_DP_MSE_MISC_CNTL                                                  0x4ed7
-+#define mmDP5_DP_MSE_MISC_CNTL                                                  0x4fd7
-+#define mmDP6_DP_MSE_MISC_CNTL                                                  0x54d7
-+#define mmDP7_DP_MSE_MISC_CNTL                                                  0x56d7
-+#define mmDP8_DP_MSE_MISC_CNTL                                                  0x57d7
-+#define mmDP_MSE_SAT0_STATUS                                                    0x4adf
-+#define mmDP0_DP_MSE_SAT0_STATUS                                                0x4adf
-+#define mmDP1_DP_MSE_SAT0_STATUS                                                0x4bdf
-+#define mmDP2_DP_MSE_SAT0_STATUS                                                0x4cdf
-+#define mmDP3_DP_MSE_SAT0_STATUS                                                0x4ddf
-+#define mmDP4_DP_MSE_SAT0_STATUS                                                0x4edf
-+#define mmDP5_DP_MSE_SAT0_STATUS                                                0x4fdf
-+#define mmDP6_DP_MSE_SAT0_STATUS                                                0x54df
-+#define mmDP7_DP_MSE_SAT0_STATUS                                                0x56df
-+#define mmDP8_DP_MSE_SAT0_STATUS                                                0x57df
-+#define mmDP_MSE_SAT1_STATUS                                                    0x4ae0
-+#define mmDP0_DP_MSE_SAT1_STATUS                                                0x4ae0
-+#define mmDP1_DP_MSE_SAT1_STATUS                                                0x4be0
-+#define mmDP2_DP_MSE_SAT1_STATUS                                                0x4ce0
-+#define mmDP3_DP_MSE_SAT1_STATUS                                                0x4de0
-+#define mmDP4_DP_MSE_SAT1_STATUS                                                0x4ee0
-+#define mmDP5_DP_MSE_SAT1_STATUS                                                0x4fe0
-+#define mmDP6_DP_MSE_SAT1_STATUS                                                0x54e0
-+#define mmDP7_DP_MSE_SAT1_STATUS                                                0x56e0
-+#define mmDP8_DP_MSE_SAT1_STATUS                                                0x57e0
-+#define mmDP_MSE_SAT2_STATUS                                                    0x4ae1
-+#define mmDP0_DP_MSE_SAT2_STATUS                                                0x4ae1
-+#define mmDP1_DP_MSE_SAT2_STATUS                                                0x4be1
-+#define mmDP2_DP_MSE_SAT2_STATUS                                                0x4ce1
-+#define mmDP3_DP_MSE_SAT2_STATUS                                                0x4de1
-+#define mmDP4_DP_MSE_SAT2_STATUS                                                0x4ee1
-+#define mmDP5_DP_MSE_SAT2_STATUS                                                0x4fe1
-+#define mmDP6_DP_MSE_SAT2_STATUS                                                0x54e1
-+#define mmDP7_DP_MSE_SAT2_STATUS                                                0x56e1
-+#define mmDP8_DP_MSE_SAT2_STATUS                                                0x57e1
-+#define mmDP_TEST_DEBUG_INDEX                                                   0x4ad8
-+#define mmDP0_DP_TEST_DEBUG_INDEX                                               0x4ad8
-+#define mmDP1_DP_TEST_DEBUG_INDEX                                               0x4bd8
-+#define mmDP2_DP_TEST_DEBUG_INDEX                                               0x4cd8
-+#define mmDP3_DP_TEST_DEBUG_INDEX                                               0x4dd8
-+#define mmDP4_DP_TEST_DEBUG_INDEX                                               0x4ed8
-+#define mmDP5_DP_TEST_DEBUG_INDEX                                               0x4fd8
-+#define mmDP6_DP_TEST_DEBUG_INDEX                                               0x54d8
-+#define mmDP7_DP_TEST_DEBUG_INDEX                                               0x56d8
-+#define mmDP8_DP_TEST_DEBUG_INDEX                                               0x57d8
-+#define mmDP_TEST_DEBUG_DATA                                                    0x4ad9
-+#define mmDP0_DP_TEST_DEBUG_DATA                                                0x4ad9
-+#define mmDP1_DP_TEST_DEBUG_DATA                                                0x4bd9
-+#define mmDP2_DP_TEST_DEBUG_DATA                                                0x4cd9
-+#define mmDP3_DP_TEST_DEBUG_DATA                                                0x4dd9
-+#define mmDP4_DP_TEST_DEBUG_DATA                                                0x4ed9
-+#define mmDP5_DP_TEST_DEBUG_DATA                                                0x4fd9
-+#define mmDP6_DP_TEST_DEBUG_DATA                                                0x54d9
-+#define mmDP7_DP_TEST_DEBUG_DATA                                                0x56d9
-+#define mmDP8_DP_TEST_DEBUG_DATA                                                0x57d9
-+#define mmDP_FE_TEST_DEBUG_INDEX                                                0x4ada
-+#define mmDP0_DP_FE_TEST_DEBUG_INDEX                                            0x4ada
-+#define mmDP1_DP_FE_TEST_DEBUG_INDEX                                            0x4bda
-+#define mmDP2_DP_FE_TEST_DEBUG_INDEX                                            0x4cda
-+#define mmDP3_DP_FE_TEST_DEBUG_INDEX                                            0x4dda
-+#define mmDP4_DP_FE_TEST_DEBUG_INDEX                                            0x4eda
-+#define mmDP5_DP_FE_TEST_DEBUG_INDEX                                            0x4fda
-+#define mmDP6_DP_FE_TEST_DEBUG_INDEX                                            0x54da
-+#define mmDP7_DP_FE_TEST_DEBUG_INDEX                                            0x56da
-+#define mmDP8_DP_FE_TEST_DEBUG_INDEX                                            0x57da
-+#define mmDP_FE_TEST_DEBUG_DATA                                                 0x4adb
-+#define mmDP0_DP_FE_TEST_DEBUG_DATA                                             0x4adb
-+#define mmDP1_DP_FE_TEST_DEBUG_DATA                                             0x4bdb
-+#define mmDP2_DP_FE_TEST_DEBUG_DATA                                             0x4cdb
-+#define mmDP3_DP_FE_TEST_DEBUG_DATA                                             0x4ddb
-+#define mmDP4_DP_FE_TEST_DEBUG_DATA                                             0x4edb
-+#define mmDP5_DP_FE_TEST_DEBUG_DATA                                             0x4fdb
-+#define mmDP6_DP_FE_TEST_DEBUG_DATA                                             0x54db
-+#define mmDP7_DP_FE_TEST_DEBUG_DATA                                             0x56db
-+#define mmDP8_DP_FE_TEST_DEBUG_DATA                                             0x57db
-+#define mmAUX_CONTROL                                                           0x5c00
-+#define mmDP_AUX0_AUX_CONTROL                                                   0x5c00
-+#define mmDP_AUX1_AUX_CONTROL                                                   0x5c1c
-+#define mmDP_AUX2_AUX_CONTROL                                                   0x5c38
-+#define mmDP_AUX3_AUX_CONTROL                                                   0x5c54
-+#define mmDP_AUX4_AUX_CONTROL                                                   0x5c70
-+#define mmDP_AUX5_AUX_CONTROL                                                   0x5c8c
-+#define mmAUX_SW_CONTROL                                                        0x5c01
-+#define mmDP_AUX0_AUX_SW_CONTROL                                                0x5c01
-+#define mmDP_AUX1_AUX_SW_CONTROL                                                0x5c1d
-+#define mmDP_AUX2_AUX_SW_CONTROL                                                0x5c39
-+#define mmDP_AUX3_AUX_SW_CONTROL                                                0x5c55
-+#define mmDP_AUX4_AUX_SW_CONTROL                                                0x5c71
-+#define mmDP_AUX5_AUX_SW_CONTROL                                                0x5c8d
-+#define mmAUX_ARB_CONTROL                                                       0x5c02
-+#define mmDP_AUX0_AUX_ARB_CONTROL                                               0x5c02
-+#define mmDP_AUX1_AUX_ARB_CONTROL                                               0x5c1e
-+#define mmDP_AUX2_AUX_ARB_CONTROL                                               0x5c3a
-+#define mmDP_AUX3_AUX_ARB_CONTROL                                               0x5c56
-+#define mmDP_AUX4_AUX_ARB_CONTROL                                               0x5c72
-+#define mmDP_AUX5_AUX_ARB_CONTROL                                               0x5c8e
-+#define mmAUX_INTERRUPT_CONTROL                                                 0x5c03
-+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                         0x5c03
-+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                         0x5c1f
-+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                         0x5c3b
-+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                         0x5c57
-+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                         0x5c73
-+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL                                         0x5c8f
-+#define mmAUX_SW_STATUS                                                         0x5c04
-+#define mmDP_AUX0_AUX_SW_STATUS                                                 0x5c04
-+#define mmDP_AUX1_AUX_SW_STATUS                                                 0x5c20
-+#define mmDP_AUX2_AUX_SW_STATUS                                                 0x5c3c
-+#define mmDP_AUX3_AUX_SW_STATUS                                                 0x5c58
-+#define mmDP_AUX4_AUX_SW_STATUS                                                 0x5c74
-+#define mmDP_AUX5_AUX_SW_STATUS                                                 0x5c90
-+#define mmAUX_LS_STATUS                                                         0x5c05
-+#define mmDP_AUX0_AUX_LS_STATUS                                                 0x5c05
-+#define mmDP_AUX1_AUX_LS_STATUS                                                 0x5c21
-+#define mmDP_AUX2_AUX_LS_STATUS                                                 0x5c3d
-+#define mmDP_AUX3_AUX_LS_STATUS                                                 0x5c59
-+#define mmDP_AUX4_AUX_LS_STATUS                                                 0x5c75
-+#define mmDP_AUX5_AUX_LS_STATUS                                                 0x5c91
-+#define mmAUX_SW_DATA                                                           0x5c06
-+#define mmDP_AUX0_AUX_SW_DATA                                                   0x5c06
-+#define mmDP_AUX1_AUX_SW_DATA                                                   0x5c22
-+#define mmDP_AUX2_AUX_SW_DATA                                                   0x5c3e
-+#define mmDP_AUX3_AUX_SW_DATA                                                   0x5c5a
-+#define mmDP_AUX4_AUX_SW_DATA                                                   0x5c76
-+#define mmDP_AUX5_AUX_SW_DATA                                                   0x5c92
-+#define mmAUX_LS_DATA                                                           0x5c07
-+#define mmDP_AUX0_AUX_LS_DATA                                                   0x5c07
-+#define mmDP_AUX1_AUX_LS_DATA                                                   0x5c23
-+#define mmDP_AUX2_AUX_LS_DATA                                                   0x5c3f
-+#define mmDP_AUX3_AUX_LS_DATA                                                   0x5c5b
-+#define mmDP_AUX4_AUX_LS_DATA                                                   0x5c77
-+#define mmDP_AUX5_AUX_LS_DATA                                                   0x5c93
-+#define mmAUX_DPHY_TX_REF_CONTROL                                               0x5c08
-+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                       0x5c08
-+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                       0x5c24
-+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                       0x5c40
-+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                       0x5c5c
-+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                       0x5c78
-+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                       0x5c94
-+#define mmAUX_DPHY_TX_CONTROL                                                   0x5c09
-+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                           0x5c09
-+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                           0x5c25
-+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                           0x5c41
-+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                           0x5c5d
-+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                           0x5c79
-+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL                                           0x5c95
-+#define mmAUX_DPHY_RX_CONTROL0                                                  0x5c0a
-+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                          0x5c0a
-+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                          0x5c26
-+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                          0x5c42
-+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                          0x5c5e
-+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                          0x5c7a
-+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                          0x5c96
-+#define mmAUX_DPHY_RX_CONTROL1                                                  0x5c0b
-+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                          0x5c0b
-+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                          0x5c27
-+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                          0x5c43
-+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                          0x5c5f
-+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                          0x5c7b
-+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                          0x5c97
-+#define mmAUX_DPHY_TX_STATUS                                                    0x5c0c
-+#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                            0x5c0c
-+#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                            0x5c28
-+#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                            0x5c44
-+#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                            0x5c60
-+#define mmDP_AUX4_AUX_DPHY_TX_STATUS                                            0x5c7c
-+#define mmDP_AUX5_AUX_DPHY_TX_STATUS                                            0x5c98
-+#define mmAUX_DPHY_RX_STATUS                                                    0x5c0d
-+#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                            0x5c0d
-+#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                            0x5c29
-+#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                            0x5c45
-+#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                            0x5c61
-+#define mmDP_AUX4_AUX_DPHY_RX_STATUS                                            0x5c7d
-+#define mmDP_AUX5_AUX_DPHY_RX_STATUS                                            0x5c99
-+#define mmAUX_GTC_SYNC_ERROR_CONTROL                                            0x5c0f
-+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c0f
-+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c2b
-+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c47
-+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c63
-+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c7f
-+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c9b
-+#define mmAUX_GTC_SYNC_CONTROLLER_STATUS                                        0x5c10
-+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c10
-+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c2c
-+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c48
-+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c64
-+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c80
-+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c9c
-+#define mmAUX_GTC_SYNC_STATUS                                                   0x5c11
-+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                           0x5c11
-+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                           0x5c2d
-+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                           0x5c49
-+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                           0x5c65
-+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                           0x5c81
-+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS                                           0x5c9d
-+#define mmAUX_TEST_DEBUG_INDEX                                                  0x5c14
-+#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX                                          0x5c14
-+#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX                                          0x5c30
-+#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX                                          0x5c4c
-+#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX                                          0x5c68
-+#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX                                          0x5c84
-+#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX                                          0x5ca0
-+#define mmAUX_TEST_DEBUG_DATA                                                   0x5c15
-+#define mmDP_AUX0_AUX_TEST_DEBUG_DATA                                           0x5c15
-+#define mmDP_AUX1_AUX_TEST_DEBUG_DATA                                           0x5c31
-+#define mmDP_AUX2_AUX_TEST_DEBUG_DATA                                           0x5c4d
-+#define mmDP_AUX3_AUX_TEST_DEBUG_DATA                                           0x5c69
-+#define mmDP_AUX4_AUX_TEST_DEBUG_DATA                                           0x5c85
-+#define mmDP_AUX5_AUX_TEST_DEBUG_DATA                                           0x5ca1
-+#define ixDP_AUX_DEBUG_A                                                        0x10
-+#define ixDP_AUX_DEBUG_B                                                        0x11
-+#define ixDP_AUX_DEBUG_C                                                        0x12
-+#define ixDP_AUX_DEBUG_D                                                        0x13
-+#define ixDP_AUX_DEBUG_E                                                        0x14
-+#define ixDP_AUX_DEBUG_F                                                        0x15
-+#define ixDP_AUX_DEBUG_G                                                        0x16
-+#define ixDP_AUX_DEBUG_H                                                        0x17
-+#define ixDP_AUX_DEBUG_I                                                        0x18
-+#define ixDP_AUX_DEBUG_J                                                        0x19
-+#define ixDP_AUX_DEBUG_K                                                        0x1a
-+#define ixDP_AUX_DEBUG_L                                                        0x1b
-+#define ixDP_AUX_DEBUG_M                                                        0x1c
-+#define ixDP_AUX_DEBUG_N                                                        0x1d
-+#define ixDP_AUX_DEBUG_O                                                        0x1e
-+#define ixDP_AUX_DEBUG_P                                                        0x1f
-+#define ixDP_AUX_DEBUG_Q                                                        0x20
-+#define mmDVO_ENABLE                                                            0x16a0
-+#define mmDVO_SOURCE_SELECT                                                     0x16a1
-+#define mmDVO_OUTPUT                                                            0x16a2
-+#define mmDVO_CONTROL                                                           0x16a3
-+#define mmDVO_CRC_EN                                                            0x16a4
-+#define mmDVO_CRC2_SIG_MASK                                                     0x16a5
-+#define mmDVO_CRC2_SIG_RESULT                                                   0x16a6
-+#define mmDVO_FIFO_ERROR_STATUS                                                 0x16a7
-+#define mmDVO_TEST_DEBUG_INDEX                                                  0x16a8
-+#define mmDVO_TEST_DEBUG_DATA                                                   0x16a9
-+#define mmFBC_CNTL                                                              0x280
-+#define mmFBC_IDLE_FORCE_CLEAR_MASK                                             0x282
-+#define mmFBC_START_STOP_DELAY                                                  0x283
-+#define mmFBC_COMP_CNTL                                                         0x284
-+#define mmFBC_COMP_MODE                                                         0x285
-+#define mmFBC_DEBUG0                                                            0x286
-+#define mmFBC_DEBUG1                                                            0x287
-+#define mmFBC_DEBUG2                                                            0x288
-+#define mmFBC_IND_LUT0                                                          0x289
-+#define mmFBC_IND_LUT1                                                          0x28a
-+#define mmFBC_IND_LUT2                                                          0x28b
-+#define mmFBC_IND_LUT3                                                          0x28c
-+#define mmFBC_IND_LUT4                                                          0x28d
-+#define mmFBC_IND_LUT5                                                          0x28e
-+#define mmFBC_IND_LUT6                                                          0x28f
-+#define mmFBC_IND_LUT7                                                          0x290
-+#define mmFBC_IND_LUT8                                                          0x291
-+#define mmFBC_IND_LUT9                                                          0x292
-+#define mmFBC_IND_LUT10                                                         0x293
-+#define mmFBC_IND_LUT11                                                         0x294
-+#define mmFBC_IND_LUT12                                                         0x295
-+#define mmFBC_IND_LUT13                                                         0x296
-+#define mmFBC_IND_LUT14                                                         0x297
-+#define mmFBC_IND_LUT15                                                         0x298
-+#define mmFBC_CSM_REGION_OFFSET_01                                              0x299
-+#define mmFBC_CSM_REGION_OFFSET_23                                              0x29a
-+#define mmFBC_CLIENT_REGION_MASK                                                0x29b
-+#define mmFBC_DEBUG_COMP                                                        0x29c
-+#define mmFBC_DEBUG_CSR                                                         0x29d
-+#define mmFBC_DEBUG_CSR_RDATA                                                   0x29e
-+#define mmFBC_DEBUG_CSR_WDATA                                                   0x29f
-+#define mmFBC_DEBUG_CSR_RDATA_HI                                                0x2a0
-+#define mmFBC_DEBUG_CSR_WDATA_HI                                                0x2a1
-+#define mmFBC_MISC                                                              0x2a2
-+#define mmFBC_STATUS                                                            0x2a3
-+#define mmFBC_ALPHA_CNTL                                                        0x2a6
-+#define mmFBC_ALPHA_RGB_OVERRIDE                                                0x2a7
-+#define mmFBC_TEST_DEBUG_INDEX                                                  0x2a4
-+#define mmFBC_TEST_DEBUG_DATA                                                   0x2a5
-+#define mmFMT_CLAMP_COMPONENT_R                                                 0x1be8
-+#define mmFMT0_FMT_CLAMP_COMPONENT_R                                            0x1be8
-+#define mmFMT1_FMT_CLAMP_COMPONENT_R                                            0x1de8
-+#define mmFMT2_FMT_CLAMP_COMPONENT_R                                            0x1fe8
-+#define mmFMT3_FMT_CLAMP_COMPONENT_R                                            0x41e8
-+#define mmFMT4_FMT_CLAMP_COMPONENT_R                                            0x43e8
-+#define mmFMT5_FMT_CLAMP_COMPONENT_R                                            0x45e8
-+#define mmFMT_CLAMP_COMPONENT_G                                                 0x1be9
-+#define mmFMT0_FMT_CLAMP_COMPONENT_G                                            0x1be9
-+#define mmFMT1_FMT_CLAMP_COMPONENT_G                                            0x1de9
-+#define mmFMT2_FMT_CLAMP_COMPONENT_G                                            0x1fe9
-+#define mmFMT3_FMT_CLAMP_COMPONENT_G                                            0x41e9
-+#define mmFMT4_FMT_CLAMP_COMPONENT_G                                            0x43e9
-+#define mmFMT5_FMT_CLAMP_COMPONENT_G                                            0x45e9
-+#define mmFMT_CLAMP_COMPONENT_B                                                 0x1bea
-+#define mmFMT0_FMT_CLAMP_COMPONENT_B                                            0x1bea
-+#define mmFMT1_FMT_CLAMP_COMPONENT_B                                            0x1dea
-+#define mmFMT2_FMT_CLAMP_COMPONENT_B                                            0x1fea
-+#define mmFMT3_FMT_CLAMP_COMPONENT_B                                            0x41ea
-+#define mmFMT4_FMT_CLAMP_COMPONENT_B                                            0x43ea
-+#define mmFMT5_FMT_CLAMP_COMPONENT_B                                            0x45ea
-+#define mmFMT_DYNAMIC_EXP_CNTL                                                  0x1bed
-+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                             0x1bed
-+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                             0x1ded
-+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                             0x1fed
-+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                             0x41ed
-+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                             0x43ed
-+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                             0x45ed
-+#define mmFMT_CONTROL                                                           0x1bee
-+#define mmFMT0_FMT_CONTROL                                                      0x1bee
-+#define mmFMT1_FMT_CONTROL                                                      0x1dee
-+#define mmFMT2_FMT_CONTROL                                                      0x1fee
-+#define mmFMT3_FMT_CONTROL                                                      0x41ee
-+#define mmFMT4_FMT_CONTROL                                                      0x43ee
-+#define mmFMT5_FMT_CONTROL                                                      0x45ee
-+#define mmFMT_BIT_DEPTH_CONTROL                                                 0x1bf2
-+#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                            0x1bf2
-+#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                            0x1df2
-+#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                            0x1ff2
-+#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                            0x41f2
-+#define mmFMT4_FMT_BIT_DEPTH_CONTROL                                            0x43f2
-+#define mmFMT5_FMT_BIT_DEPTH_CONTROL                                            0x45f2
-+#define mmFMT_DITHER_RAND_R_SEED                                                0x1bf3
-+#define mmFMT0_FMT_DITHER_RAND_R_SEED                                           0x1bf3
-+#define mmFMT1_FMT_DITHER_RAND_R_SEED                                           0x1df3
-+#define mmFMT2_FMT_DITHER_RAND_R_SEED                                           0x1ff3
-+#define mmFMT3_FMT_DITHER_RAND_R_SEED                                           0x41f3
-+#define mmFMT4_FMT_DITHER_RAND_R_SEED                                           0x43f3
-+#define mmFMT5_FMT_DITHER_RAND_R_SEED                                           0x45f3
-+#define mmFMT_DITHER_RAND_G_SEED                                                0x1bf4
-+#define mmFMT0_FMT_DITHER_RAND_G_SEED                                           0x1bf4
-+#define mmFMT1_FMT_DITHER_RAND_G_SEED                                           0x1df4
-+#define mmFMT2_FMT_DITHER_RAND_G_SEED                                           0x1ff4
-+#define mmFMT3_FMT_DITHER_RAND_G_SEED                                           0x41f4
-+#define mmFMT4_FMT_DITHER_RAND_G_SEED                                           0x43f4
-+#define mmFMT5_FMT_DITHER_RAND_G_SEED                                           0x45f4
-+#define mmFMT_DITHER_RAND_B_SEED                                                0x1bf5
-+#define mmFMT0_FMT_DITHER_RAND_B_SEED                                           0x1bf5
-+#define mmFMT1_FMT_DITHER_RAND_B_SEED                                           0x1df5
-+#define mmFMT2_FMT_DITHER_RAND_B_SEED                                           0x1ff5
-+#define mmFMT3_FMT_DITHER_RAND_B_SEED                                           0x41f5
-+#define mmFMT4_FMT_DITHER_RAND_B_SEED                                           0x43f5
-+#define mmFMT5_FMT_DITHER_RAND_B_SEED                                           0x45f5
-+#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL                                   0x1bf6
-+#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1bf6
-+#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1df6
-+#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1ff6
-+#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x41f6
-+#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x43f6
-+#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x45f6
-+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                     0x1bf7
-+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1bf7
-+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1df7
-+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1ff7
-+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x41f7
-+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x43f7
-+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x45f7
-+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                     0x1bf8
-+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1bf8
-+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1df8
-+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1ff8
-+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x41f8
-+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x43f8
-+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x45f8
-+#define mmFMT_CLAMP_CNTL                                                        0x1bf9
-+#define mmFMT0_FMT_CLAMP_CNTL                                                   0x1bf9
-+#define mmFMT1_FMT_CLAMP_CNTL                                                   0x1df9
-+#define mmFMT2_FMT_CLAMP_CNTL                                                   0x1ff9
-+#define mmFMT3_FMT_CLAMP_CNTL                                                   0x41f9
-+#define mmFMT4_FMT_CLAMP_CNTL                                                   0x43f9
-+#define mmFMT5_FMT_CLAMP_CNTL                                                   0x45f9
-+#define mmFMT_CRC_CNTL                                                          0x1bfa
-+#define mmFMT0_FMT_CRC_CNTL                                                     0x1bfa
-+#define mmFMT1_FMT_CRC_CNTL                                                     0x1dfa
-+#define mmFMT2_FMT_CRC_CNTL                                                     0x1ffa
-+#define mmFMT3_FMT_CRC_CNTL                                                     0x41fa
-+#define mmFMT4_FMT_CRC_CNTL                                                     0x43fa
-+#define mmFMT5_FMT_CRC_CNTL                                                     0x45fa
-+#define mmFMT_CRC_SIG_RED_GREEN_MASK                                            0x1bfb
-+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1bfb
-+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1dfb
-+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1ffb
-+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                                       0x41fb
-+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                                       0x43fb
-+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                                       0x45fb
-+#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK                                         0x1bfc
-+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1bfc
-+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1dfc
-+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1ffc
-+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x41fc
-+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x43fc
-+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x45fc
-+#define mmFMT_CRC_SIG_RED_GREEN                                                 0x1bfd
-+#define mmFMT0_FMT_CRC_SIG_RED_GREEN                                            0x1bfd
-+#define mmFMT1_FMT_CRC_SIG_RED_GREEN                                            0x1dfd
-+#define mmFMT2_FMT_CRC_SIG_RED_GREEN                                            0x1ffd
-+#define mmFMT3_FMT_CRC_SIG_RED_GREEN                                            0x41fd
-+#define mmFMT4_FMT_CRC_SIG_RED_GREEN                                            0x43fd
-+#define mmFMT5_FMT_CRC_SIG_RED_GREEN                                            0x45fd
-+#define mmFMT_CRC_SIG_BLUE_CONTROL                                              0x1bfe
-+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL                                         0x1bfe
-+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL                                         0x1dfe
-+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL                                         0x1ffe
-+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                                         0x41fe
-+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL                                         0x43fe
-+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                                         0x45fe
-+#define mmFMT_DEBUG_CNTL                                                        0x1bff
-+#define mmFMT0_FMT_DEBUG_CNTL                                                   0x1bff
-+#define mmFMT1_FMT_DEBUG_CNTL                                                   0x1dff
-+#define mmFMT2_FMT_DEBUG_CNTL                                                   0x1fff
-+#define mmFMT3_FMT_DEBUG_CNTL                                                   0x41ff
-+#define mmFMT4_FMT_DEBUG_CNTL                                                   0x43ff
-+#define mmFMT5_FMT_DEBUG_CNTL                                                   0x45ff
-+#define mmFMT_SIDE_BY_SIDE_STEREO_CONTROL                                       0x1bf0
-+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x1bf0
-+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x1df0
-+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x1ff0
-+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x41f0
-+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x43f0
-+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x45f0
-+#define mmFMT_420_HBLANK_EARLY_START                                            0x1bf1
-+#define mmFMT0_FMT_420_HBLANK_EARLY_START                                       0x1bf1
-+#define mmFMT1_FMT_420_HBLANK_EARLY_START                                       0x1df1
-+#define mmFMT2_FMT_420_HBLANK_EARLY_START                                       0x1ff1
-+#define mmFMT3_FMT_420_HBLANK_EARLY_START                                       0x41f1
-+#define mmFMT4_FMT_420_HBLANK_EARLY_START                                       0x43f1
-+#define mmFMT5_FMT_420_HBLANK_EARLY_START                                       0x45f1
-+#define mmFMT_TEST_DEBUG_INDEX                                                  0x1beb
-+#define mmFMT0_FMT_TEST_DEBUG_INDEX                                             0x1beb
-+#define mmFMT1_FMT_TEST_DEBUG_INDEX                                             0x1deb
-+#define mmFMT2_FMT_TEST_DEBUG_INDEX                                             0x1feb
-+#define mmFMT3_FMT_TEST_DEBUG_INDEX                                             0x41eb
-+#define mmFMT4_FMT_TEST_DEBUG_INDEX                                             0x43eb
-+#define mmFMT5_FMT_TEST_DEBUG_INDEX                                             0x45eb
-+#define mmFMT_TEST_DEBUG_DATA                                                   0x1bec
-+#define mmFMT0_FMT_TEST_DEBUG_DATA                                              0x1bec
-+#define mmFMT1_FMT_TEST_DEBUG_DATA                                              0x1dec
-+#define mmFMT2_FMT_TEST_DEBUG_DATA                                              0x1fec
-+#define mmFMT3_FMT_TEST_DEBUG_DATA                                              0x41ec
-+#define mmFMT4_FMT_TEST_DEBUG_DATA                                              0x43ec
-+#define mmFMT5_FMT_TEST_DEBUG_DATA                                              0x45ec
-+#define ixFMT_DEBUG0                                                            0x1
-+#define ixFMT_DEBUG1                                                            0x2
-+#define ixFMT_DEBUG2                                                            0x3
-+#define ixFMT_DEBUG3                                                            0x4
-+#define ixFMT_DEBUG_ID                                                          0x0
-+#define mmLB_DATA_FORMAT                                                        0x1ac0
-+#define mmLB0_LB_DATA_FORMAT                                                    0x1ac0
-+#define mmLB1_LB_DATA_FORMAT                                                    0x1cc0
-+#define mmLB2_LB_DATA_FORMAT                                                    0x1ec0
-+#define mmLB3_LB_DATA_FORMAT                                                    0x40c0
-+#define mmLB4_LB_DATA_FORMAT                                                    0x42c0
-+#define mmLB5_LB_DATA_FORMAT                                                    0x44c0
-+#define mmLB_MEMORY_CTRL                                                        0x1ac1
-+#define mmLB0_LB_MEMORY_CTRL                                                    0x1ac1
-+#define mmLB1_LB_MEMORY_CTRL                                                    0x1cc1
-+#define mmLB2_LB_MEMORY_CTRL                                                    0x1ec1
-+#define mmLB3_LB_MEMORY_CTRL                                                    0x40c1
-+#define mmLB4_LB_MEMORY_CTRL                                                    0x42c1
-+#define mmLB5_LB_MEMORY_CTRL                                                    0x44c1
-+#define mmLB_MEMORY_SIZE_STATUS                                                 0x1ac2
-+#define mmLB0_LB_MEMORY_SIZE_STATUS                                             0x1ac2
-+#define mmLB1_LB_MEMORY_SIZE_STATUS                                             0x1cc2
-+#define mmLB2_LB_MEMORY_SIZE_STATUS                                             0x1ec2
-+#define mmLB3_LB_MEMORY_SIZE_STATUS                                             0x40c2
-+#define mmLB4_LB_MEMORY_SIZE_STATUS                                             0x42c2
-+#define mmLB5_LB_MEMORY_SIZE_STATUS                                             0x44c2
-+#define mmLB_DESKTOP_HEIGHT                                                     0x1ac3
-+#define mmLB0_LB_DESKTOP_HEIGHT                                                 0x1ac3
-+#define mmLB1_LB_DESKTOP_HEIGHT                                                 0x1cc3
-+#define mmLB2_LB_DESKTOP_HEIGHT                                                 0x1ec3
-+#define mmLB3_LB_DESKTOP_HEIGHT                                                 0x40c3
-+#define mmLB4_LB_DESKTOP_HEIGHT                                                 0x42c3
-+#define mmLB5_LB_DESKTOP_HEIGHT                                                 0x44c3
-+#define mmLB_VLINE_START_END                                                    0x1ac4
-+#define mmLB0_LB_VLINE_START_END                                                0x1ac4
-+#define mmLB1_LB_VLINE_START_END                                                0x1cc4
-+#define mmLB2_LB_VLINE_START_END                                                0x1ec4
-+#define mmLB3_LB_VLINE_START_END                                                0x40c4
-+#define mmLB4_LB_VLINE_START_END                                                0x42c4
-+#define mmLB5_LB_VLINE_START_END                                                0x44c4
-+#define mmLB_VLINE2_START_END                                                   0x1ac5
-+#define mmLB0_LB_VLINE2_START_END                                               0x1ac5
-+#define mmLB1_LB_VLINE2_START_END                                               0x1cc5
-+#define mmLB2_LB_VLINE2_START_END                                               0x1ec5
-+#define mmLB3_LB_VLINE2_START_END                                               0x40c5
-+#define mmLB4_LB_VLINE2_START_END                                               0x42c5
-+#define mmLB5_LB_VLINE2_START_END                                               0x44c5
-+#define mmLB_V_COUNTER                                                          0x1ac6
-+#define mmLB0_LB_V_COUNTER                                                      0x1ac6
-+#define mmLB1_LB_V_COUNTER                                                      0x1cc6
-+#define mmLB2_LB_V_COUNTER                                                      0x1ec6
-+#define mmLB3_LB_V_COUNTER                                                      0x40c6
-+#define mmLB4_LB_V_COUNTER                                                      0x42c6
-+#define mmLB5_LB_V_COUNTER                                                      0x44c6
-+#define mmLB_SNAPSHOT_V_COUNTER                                                 0x1ac7
-+#define mmLB0_LB_SNAPSHOT_V_COUNTER                                             0x1ac7
-+#define mmLB1_LB_SNAPSHOT_V_COUNTER                                             0x1cc7
-+#define mmLB2_LB_SNAPSHOT_V_COUNTER                                             0x1ec7
-+#define mmLB3_LB_SNAPSHOT_V_COUNTER                                             0x40c7
-+#define mmLB4_LB_SNAPSHOT_V_COUNTER                                             0x42c7
-+#define mmLB5_LB_SNAPSHOT_V_COUNTER                                             0x44c7
-+#define mmLB_INTERRUPT_MASK                                                     0x1ac8
-+#define mmLB0_LB_INTERRUPT_MASK                                                 0x1ac8
-+#define mmLB1_LB_INTERRUPT_MASK                                                 0x1cc8
-+#define mmLB2_LB_INTERRUPT_MASK                                                 0x1ec8
-+#define mmLB3_LB_INTERRUPT_MASK                                                 0x40c8
-+#define mmLB4_LB_INTERRUPT_MASK                                                 0x42c8
-+#define mmLB5_LB_INTERRUPT_MASK                                                 0x44c8
-+#define mmLB_VLINE_STATUS                                                       0x1ac9
-+#define mmLB0_LB_VLINE_STATUS                                                   0x1ac9
-+#define mmLB1_LB_VLINE_STATUS                                                   0x1cc9
-+#define mmLB2_LB_VLINE_STATUS                                                   0x1ec9
-+#define mmLB3_LB_VLINE_STATUS                                                   0x40c9
-+#define mmLB4_LB_VLINE_STATUS                                                   0x42c9
-+#define mmLB5_LB_VLINE_STATUS                                                   0x44c9
-+#define mmLB_VLINE2_STATUS                                                      0x1aca
-+#define mmLB0_LB_VLINE2_STATUS                                                  0x1aca
-+#define mmLB1_LB_VLINE2_STATUS                                                  0x1cca
-+#define mmLB2_LB_VLINE2_STATUS                                                  0x1eca
-+#define mmLB3_LB_VLINE2_STATUS                                                  0x40ca
-+#define mmLB4_LB_VLINE2_STATUS                                                  0x42ca
-+#define mmLB5_LB_VLINE2_STATUS                                                  0x44ca
-+#define mmLB_VBLANK_STATUS                                                      0x1acb
-+#define mmLB0_LB_VBLANK_STATUS                                                  0x1acb
-+#define mmLB1_LB_VBLANK_STATUS                                                  0x1ccb
-+#define mmLB2_LB_VBLANK_STATUS                                                  0x1ecb
-+#define mmLB3_LB_VBLANK_STATUS                                                  0x40cb
-+#define mmLB4_LB_VBLANK_STATUS                                                  0x42cb
-+#define mmLB5_LB_VBLANK_STATUS                                                  0x44cb
-+#define mmLB_SYNC_RESET_SEL                                                     0x1acc
-+#define mmLB0_LB_SYNC_RESET_SEL                                                 0x1acc
-+#define mmLB1_LB_SYNC_RESET_SEL                                                 0x1ccc
-+#define mmLB2_LB_SYNC_RESET_SEL                                                 0x1ecc
-+#define mmLB3_LB_SYNC_RESET_SEL                                                 0x40cc
-+#define mmLB4_LB_SYNC_RESET_SEL                                                 0x42cc
-+#define mmLB5_LB_SYNC_RESET_SEL                                                 0x44cc
-+#define mmLB_BLACK_KEYER_R_CR                                                   0x1acd
-+#define mmLB0_LB_BLACK_KEYER_R_CR                                               0x1acd
-+#define mmLB1_LB_BLACK_KEYER_R_CR                                               0x1ccd
-+#define mmLB2_LB_BLACK_KEYER_R_CR                                               0x1ecd
-+#define mmLB3_LB_BLACK_KEYER_R_CR                                               0x40cd
-+#define mmLB4_LB_BLACK_KEYER_R_CR                                               0x42cd
-+#define mmLB5_LB_BLACK_KEYER_R_CR                                               0x44cd
-+#define mmLB_BLACK_KEYER_G_Y                                                    0x1ace
-+#define mmLB0_LB_BLACK_KEYER_G_Y                                                0x1ace
-+#define mmLB1_LB_BLACK_KEYER_G_Y                                                0x1cce
-+#define mmLB2_LB_BLACK_KEYER_G_Y                                                0x1ece
-+#define mmLB3_LB_BLACK_KEYER_G_Y                                                0x40ce
-+#define mmLB4_LB_BLACK_KEYER_G_Y                                                0x42ce
-+#define mmLB5_LB_BLACK_KEYER_G_Y                                                0x44ce
-+#define mmLB_BLACK_KEYER_B_CB                                                   0x1acf
-+#define mmLB0_LB_BLACK_KEYER_B_CB                                               0x1acf
-+#define mmLB1_LB_BLACK_KEYER_B_CB                                               0x1ccf
-+#define mmLB2_LB_BLACK_KEYER_B_CB                                               0x1ecf
-+#define mmLB3_LB_BLACK_KEYER_B_CB                                               0x40cf
-+#define mmLB4_LB_BLACK_KEYER_B_CB                                               0x42cf
-+#define mmLB5_LB_BLACK_KEYER_B_CB                                               0x44cf
-+#define mmLB_KEYER_COLOR_CTRL                                                   0x1ad0
-+#define mmLB0_LB_KEYER_COLOR_CTRL                                               0x1ad0
-+#define mmLB1_LB_KEYER_COLOR_CTRL                                               0x1cd0
-+#define mmLB2_LB_KEYER_COLOR_CTRL                                               0x1ed0
-+#define mmLB3_LB_KEYER_COLOR_CTRL                                               0x40d0
-+#define mmLB4_LB_KEYER_COLOR_CTRL                                               0x42d0
-+#define mmLB5_LB_KEYER_COLOR_CTRL                                               0x44d0
-+#define mmLB_KEYER_COLOR_R_CR                                                   0x1ad1
-+#define mmLB0_LB_KEYER_COLOR_R_CR                                               0x1ad1
-+#define mmLB1_LB_KEYER_COLOR_R_CR                                               0x1cd1
-+#define mmLB2_LB_KEYER_COLOR_R_CR                                               0x1ed1
-+#define mmLB3_LB_KEYER_COLOR_R_CR                                               0x40d1
-+#define mmLB4_LB_KEYER_COLOR_R_CR                                               0x42d1
-+#define mmLB5_LB_KEYER_COLOR_R_CR                                               0x44d1
-+#define mmLB_KEYER_COLOR_G_Y                                                    0x1ad2
-+#define mmLB0_LB_KEYER_COLOR_G_Y                                                0x1ad2
-+#define mmLB1_LB_KEYER_COLOR_G_Y                                                0x1cd2
-+#define mmLB2_LB_KEYER_COLOR_G_Y                                                0x1ed2
-+#define mmLB3_LB_KEYER_COLOR_G_Y                                                0x40d2
-+#define mmLB4_LB_KEYER_COLOR_G_Y                                                0x42d2
-+#define mmLB5_LB_KEYER_COLOR_G_Y                                                0x44d2
-+#define mmLB_KEYER_COLOR_B_CB                                                   0x1ad3
-+#define mmLB0_LB_KEYER_COLOR_B_CB                                               0x1ad3
-+#define mmLB1_LB_KEYER_COLOR_B_CB                                               0x1cd3
-+#define mmLB2_LB_KEYER_COLOR_B_CB                                               0x1ed3
-+#define mmLB3_LB_KEYER_COLOR_B_CB                                               0x40d3
-+#define mmLB4_LB_KEYER_COLOR_B_CB                                               0x42d3
-+#define mmLB5_LB_KEYER_COLOR_B_CB                                               0x44d3
-+#define mmLB_KEYER_COLOR_REP_R_CR                                               0x1ad4
-+#define mmLB0_LB_KEYER_COLOR_REP_R_CR                                           0x1ad4
-+#define mmLB1_LB_KEYER_COLOR_REP_R_CR                                           0x1cd4
-+#define mmLB2_LB_KEYER_COLOR_REP_R_CR                                           0x1ed4
-+#define mmLB3_LB_KEYER_COLOR_REP_R_CR                                           0x40d4
-+#define mmLB4_LB_KEYER_COLOR_REP_R_CR                                           0x42d4
-+#define mmLB5_LB_KEYER_COLOR_REP_R_CR                                           0x44d4
-+#define mmLB_KEYER_COLOR_REP_G_Y                                                0x1ad5
-+#define mmLB0_LB_KEYER_COLOR_REP_G_Y                                            0x1ad5
-+#define mmLB1_LB_KEYER_COLOR_REP_G_Y                                            0x1cd5
-+#define mmLB2_LB_KEYER_COLOR_REP_G_Y                                            0x1ed5
-+#define mmLB3_LB_KEYER_COLOR_REP_G_Y                                            0x40d5
-+#define mmLB4_LB_KEYER_COLOR_REP_G_Y                                            0x42d5
-+#define mmLB5_LB_KEYER_COLOR_REP_G_Y                                            0x44d5
-+#define mmLB_KEYER_COLOR_REP_B_CB                                               0x1ad6
-+#define mmLB0_LB_KEYER_COLOR_REP_B_CB                                           0x1ad6
-+#define mmLB1_LB_KEYER_COLOR_REP_B_CB                                           0x1cd6
-+#define mmLB2_LB_KEYER_COLOR_REP_B_CB                                           0x1ed6
-+#define mmLB3_LB_KEYER_COLOR_REP_B_CB                                           0x40d6
-+#define mmLB4_LB_KEYER_COLOR_REP_B_CB                                           0x42d6
-+#define mmLB5_LB_KEYER_COLOR_REP_B_CB                                           0x44d6
-+#define mmLB_BUFFER_LEVEL_STATUS                                                0x1ad7
-+#define mmLB0_LB_BUFFER_LEVEL_STATUS                                            0x1ad7
-+#define mmLB1_LB_BUFFER_LEVEL_STATUS                                            0x1cd7
-+#define mmLB2_LB_BUFFER_LEVEL_STATUS                                            0x1ed7
-+#define mmLB3_LB_BUFFER_LEVEL_STATUS                                            0x40d7
-+#define mmLB4_LB_BUFFER_LEVEL_STATUS                                            0x42d7
-+#define mmLB5_LB_BUFFER_LEVEL_STATUS                                            0x44d7
-+#define mmLB_BUFFER_URGENCY_CTRL                                                0x1ad8
-+#define mmLB0_LB_BUFFER_URGENCY_CTRL                                            0x1ad8
-+#define mmLB1_LB_BUFFER_URGENCY_CTRL                                            0x1cd8
-+#define mmLB2_LB_BUFFER_URGENCY_CTRL                                            0x1ed8
-+#define mmLB3_LB_BUFFER_URGENCY_CTRL                                            0x40d8
-+#define mmLB4_LB_BUFFER_URGENCY_CTRL                                            0x42d8
-+#define mmLB5_LB_BUFFER_URGENCY_CTRL                                            0x44d8
-+#define mmLB_BUFFER_URGENCY_STATUS                                              0x1ad9
-+#define mmLB0_LB_BUFFER_URGENCY_STATUS                                          0x1ad9
-+#define mmLB1_LB_BUFFER_URGENCY_STATUS                                          0x1cd9
-+#define mmLB2_LB_BUFFER_URGENCY_STATUS                                          0x1ed9
-+#define mmLB3_LB_BUFFER_URGENCY_STATUS                                          0x40d9
-+#define mmLB4_LB_BUFFER_URGENCY_STATUS                                          0x42d9
-+#define mmLB5_LB_BUFFER_URGENCY_STATUS                                          0x44d9
-+#define mmLB_BUFFER_STATUS                                                      0x1ada
-+#define mmLB0_LB_BUFFER_STATUS                                                  0x1ada
-+#define mmLB1_LB_BUFFER_STATUS                                                  0x1cda
-+#define mmLB2_LB_BUFFER_STATUS                                                  0x1eda
-+#define mmLB3_LB_BUFFER_STATUS                                                  0x40da
-+#define mmLB4_LB_BUFFER_STATUS                                                  0x42da
-+#define mmLB5_LB_BUFFER_STATUS                                                  0x44da
-+#define mmLB_NO_OUTSTANDING_REQ_STATUS                                          0x1adc
-+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1adc
-+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1cdc
-+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1edc
-+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                                      0x40dc
-+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                                      0x42dc
-+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                                      0x44dc
-+#define mmMVP_AFR_FLIP_MODE                                                     0x1ae0
-+#define mmLB0_MVP_AFR_FLIP_MODE                                                 0x1ae0
-+#define mmLB1_MVP_AFR_FLIP_MODE                                                 0x1ce0
-+#define mmLB2_MVP_AFR_FLIP_MODE                                                 0x1ee0
-+#define mmLB3_MVP_AFR_FLIP_MODE                                                 0x40e0
-+#define mmLB4_MVP_AFR_FLIP_MODE                                                 0x42e0
-+#define mmLB5_MVP_AFR_FLIP_MODE                                                 0x44e0
-+#define mmMVP_AFR_FLIP_FIFO_CNTL                                                0x1ae1
-+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ae1
-+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ce1
-+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ee1
-+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL                                            0x40e1
-+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL                                            0x42e1
-+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL                                            0x44e1
-+#define mmMVP_FLIP_LINE_NUM_INSERT                                              0x1ae2
-+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT                                          0x1ae2
-+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT                                          0x1ce2
-+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT                                          0x1ee2
-+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT                                          0x40e2
-+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT                                          0x42e2
-+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT                                          0x44e2
-+#define mmDC_MVP_LB_CONTROL                                                     0x1ae3
-+#define mmLB0_DC_MVP_LB_CONTROL                                                 0x1ae3
-+#define mmLB1_DC_MVP_LB_CONTROL                                                 0x1ce3
-+#define mmLB2_DC_MVP_LB_CONTROL                                                 0x1ee3
-+#define mmLB3_DC_MVP_LB_CONTROL                                                 0x40e3
-+#define mmLB4_DC_MVP_LB_CONTROL                                                 0x42e3
-+#define mmLB5_DC_MVP_LB_CONTROL                                                 0x44e3
-+#define mmLB_DEBUG                                                              0x1ae4
-+#define mmLB0_LB_DEBUG                                                          0x1ae4
-+#define mmLB1_LB_DEBUG                                                          0x1ce4
-+#define mmLB2_LB_DEBUG                                                          0x1ee4
-+#define mmLB3_LB_DEBUG                                                          0x40e4
-+#define mmLB4_LB_DEBUG                                                          0x42e4
-+#define mmLB5_LB_DEBUG                                                          0x44e4
-+#define mmLB_DEBUG2                                                             0x1ae5
-+#define mmLB0_LB_DEBUG2                                                         0x1ae5
-+#define mmLB1_LB_DEBUG2                                                         0x1ce5
-+#define mmLB2_LB_DEBUG2                                                         0x1ee5
-+#define mmLB3_LB_DEBUG2                                                         0x40e5
-+#define mmLB4_LB_DEBUG2                                                         0x42e5
-+#define mmLB5_LB_DEBUG2                                                         0x44e5
-+#define mmLB_DEBUG3                                                             0x1ae6
-+#define mmLB0_LB_DEBUG3                                                         0x1ae6
-+#define mmLB1_LB_DEBUG3                                                         0x1ce6
-+#define mmLB2_LB_DEBUG3                                                         0x1ee6
-+#define mmLB3_LB_DEBUG3                                                         0x40e6
-+#define mmLB4_LB_DEBUG3                                                         0x42e6
-+#define mmLB5_LB_DEBUG3                                                         0x44e6
-+#define mmLB_TEST_DEBUG_INDEX                                                   0x1afe
-+#define mmLB0_LB_TEST_DEBUG_INDEX                                               0x1afe
-+#define mmLB1_LB_TEST_DEBUG_INDEX                                               0x1cfe
-+#define mmLB2_LB_TEST_DEBUG_INDEX                                               0x1efe
-+#define mmLB3_LB_TEST_DEBUG_INDEX                                               0x40fe
-+#define mmLB4_LB_TEST_DEBUG_INDEX                                               0x42fe
-+#define mmLB5_LB_TEST_DEBUG_INDEX                                               0x44fe
-+#define mmLB_TEST_DEBUG_DATA                                                    0x1aff
-+#define mmLB0_LB_TEST_DEBUG_DATA                                                0x1aff
-+#define mmLB1_LB_TEST_DEBUG_DATA                                                0x1cff
-+#define mmLB2_LB_TEST_DEBUG_DATA                                                0x1eff
-+#define mmLB3_LB_TEST_DEBUG_DATA                                                0x40ff
-+#define mmLB4_LB_TEST_DEBUG_DATA                                                0x42ff
-+#define mmLB5_LB_TEST_DEBUG_DATA                                                0x44ff
-+#define mmLBV_DATA_FORMAT                                                       0x463c
-+#define mmLBV0_LBV_DATA_FORMAT                                                  0x463c
-+#define mmLBV1_LBV_DATA_FORMAT                                                  0x983c
-+#define mmLBV_MEMORY_CTRL                                                       0x463d
-+#define mmLBV0_LBV_MEMORY_CTRL                                                  0x463d
-+#define mmLBV1_LBV_MEMORY_CTRL                                                  0x983d
-+#define mmLBV_MEMORY_SIZE_STATUS                                                0x463e
-+#define mmLBV0_LBV_MEMORY_SIZE_STATUS                                           0x463e
-+#define mmLBV1_LBV_MEMORY_SIZE_STATUS                                           0x983e
-+#define mmLBV_DESKTOP_HEIGHT                                                    0x463f
-+#define mmLBV0_LBV_DESKTOP_HEIGHT                                               0x463f
-+#define mmLBV1_LBV_DESKTOP_HEIGHT                                               0x983f
-+#define mmLBV_VLINE_START_END                                                   0x4640
-+#define mmLBV0_LBV_VLINE_START_END                                              0x4640
-+#define mmLBV1_LBV_VLINE_START_END                                              0x9840
-+#define mmLBV_VLINE2_START_END                                                  0x4641
-+#define mmLBV0_LBV_VLINE2_START_END                                             0x4641
-+#define mmLBV1_LBV_VLINE2_START_END                                             0x9841
-+#define mmLBV_V_COUNTER                                                         0x4642
-+#define mmLBV0_LBV_V_COUNTER                                                    0x4642
-+#define mmLBV1_LBV_V_COUNTER                                                    0x9842
-+#define mmLBV_SNAPSHOT_V_COUNTER                                                0x4643
-+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER                                           0x4643
-+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER                                           0x9843
-+#define mmLBV_V_COUNTER_CHROMA                                                  0x4644
-+#define mmLBV0_LBV_V_COUNTER_CHROMA                                             0x4644
-+#define mmLBV1_LBV_V_COUNTER_CHROMA                                             0x9844
-+#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA                                         0x4645
-+#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA                                    0x4645
-+#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA                                    0x9845
-+#define mmLBV_INTERRUPT_MASK                                                    0x4646
-+#define mmLBV0_LBV_INTERRUPT_MASK                                               0x4646
-+#define mmLBV1_LBV_INTERRUPT_MASK                                               0x9846
-+#define mmLBV_VLINE_STATUS                                                      0x4647
-+#define mmLBV0_LBV_VLINE_STATUS                                                 0x4647
-+#define mmLBV1_LBV_VLINE_STATUS                                                 0x9847
-+#define mmLBV_VLINE2_STATUS                                                     0x4648
-+#define mmLBV0_LBV_VLINE2_STATUS                                                0x4648
-+#define mmLBV1_LBV_VLINE2_STATUS                                                0x9848
-+#define mmLBV_VBLANK_STATUS                                                     0x4649
-+#define mmLBV0_LBV_VBLANK_STATUS                                                0x4649
-+#define mmLBV1_LBV_VBLANK_STATUS                                                0x9849
-+#define mmLBV_SYNC_RESET_SEL                                                    0x464a
-+#define mmLBV0_LBV_SYNC_RESET_SEL                                               0x464a
-+#define mmLBV1_LBV_SYNC_RESET_SEL                                               0x984a
-+#define mmLBV_BLACK_KEYER_R_CR                                                  0x464b
-+#define mmLBV0_LBV_BLACK_KEYER_R_CR                                             0x464b
-+#define mmLBV1_LBV_BLACK_KEYER_R_CR                                             0x984b
-+#define mmLBV_BLACK_KEYER_G_Y                                                   0x464c
-+#define mmLBV0_LBV_BLACK_KEYER_G_Y                                              0x464c
-+#define mmLBV1_LBV_BLACK_KEYER_G_Y                                              0x984c
-+#define mmLBV_BLACK_KEYER_B_CB                                                  0x464d
-+#define mmLBV0_LBV_BLACK_KEYER_B_CB                                             0x464d
-+#define mmLBV1_LBV_BLACK_KEYER_B_CB                                             0x984d
-+#define mmLBV_KEYER_COLOR_CTRL                                                  0x464e
-+#define mmLBV0_LBV_KEYER_COLOR_CTRL                                             0x464e
-+#define mmLBV1_LBV_KEYER_COLOR_CTRL                                             0x984e
-+#define mmLBV_KEYER_COLOR_R_CR                                                  0x464f
-+#define mmLBV0_LBV_KEYER_COLOR_R_CR                                             0x464f
-+#define mmLBV1_LBV_KEYER_COLOR_R_CR                                             0x984f
-+#define mmLBV_KEYER_COLOR_G_Y                                                   0x4650
-+#define mmLBV0_LBV_KEYER_COLOR_G_Y                                              0x4650
-+#define mmLBV1_LBV_KEYER_COLOR_G_Y                                              0x9850
-+#define mmLBV_KEYER_COLOR_B_CB                                                  0x4651
-+#define mmLBV0_LBV_KEYER_COLOR_B_CB                                             0x4651
-+#define mmLBV1_LBV_KEYER_COLOR_B_CB                                             0x9851
-+#define mmLBV_KEYER_COLOR_REP_R_CR                                              0x4652
-+#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR                                         0x4652
-+#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR                                         0x9852
-+#define mmLBV_KEYER_COLOR_REP_G_Y                                               0x4653
-+#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y                                          0x4653
-+#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y                                          0x9853
-+#define mmLBV_KEYER_COLOR_REP_B_CB                                              0x4654
-+#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB                                         0x4654
-+#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB                                         0x9854
-+#define mmLBV_BUFFER_LEVEL_STATUS                                               0x4655
-+#define mmLBV0_LBV_BUFFER_LEVEL_STATUS                                          0x4655
-+#define mmLBV1_LBV_BUFFER_LEVEL_STATUS                                          0x9855
-+#define mmLBV_BUFFER_URGENCY_CTRL                                               0x4656
-+#define mmLBV0_LBV_BUFFER_URGENCY_CTRL                                          0x4656
-+#define mmLBV1_LBV_BUFFER_URGENCY_CTRL                                          0x9856
-+#define mmLBV_BUFFER_URGENCY_STATUS                                             0x4657
-+#define mmLBV0_LBV_BUFFER_URGENCY_STATUS                                        0x4657
-+#define mmLBV1_LBV_BUFFER_URGENCY_STATUS                                        0x9857
-+#define mmLBV_BUFFER_STATUS                                                     0x4658
-+#define mmLBV0_LBV_BUFFER_STATUS                                                0x4658
-+#define mmLBV1_LBV_BUFFER_STATUS                                                0x9858
-+#define mmLBV_NO_OUTSTANDING_REQ_STATUS                                         0x4659
-+#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS                                    0x4659
-+#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS                                    0x9859
-+#define mmLBV_DEBUG                                                             0x465a
-+#define mmLBV0_LBV_DEBUG                                                        0x465a
-+#define mmLBV1_LBV_DEBUG                                                        0x985a
-+#define mmLBV_DEBUG2                                                            0x465b
-+#define mmLBV0_LBV_DEBUG2                                                       0x465b
-+#define mmLBV1_LBV_DEBUG2                                                       0x985b
-+#define mmLBV_DEBUG3                                                            0x465c
-+#define mmLBV0_LBV_DEBUG3                                                       0x465c
-+#define mmLBV1_LBV_DEBUG3                                                       0x985c
-+#define mmLBV_TEST_DEBUG_INDEX                                                  0x4666
-+#define mmLBV0_LBV_TEST_DEBUG_INDEX                                             0x4666
-+#define mmLBV1_LBV_TEST_DEBUG_INDEX                                             0x9866
-+#define mmLBV_TEST_DEBUG_DATA                                                   0x4667
-+#define mmLBV0_LBV_TEST_DEBUG_DATA                                              0x4667
-+#define mmLBV1_LBV_TEST_DEBUG_DATA                                              0x9867
-+#define mmMVP_CONTROL1                                                          0x2ac
-+#define mmMVP_CONTROL2                                                          0x2ad
-+#define mmMVP_FIFO_CONTROL                                                      0x2ae
-+#define mmMVP_FIFO_STATUS                                                       0x2af
-+#define mmMVP_SLAVE_STATUS                                                      0x2b0
-+#define mmMVP_INBAND_CNTL_CAP                                                   0x2b1
-+#define mmMVP_BLACK_KEYER                                                       0x2b2
-+#define mmMVP_CRC_CNTL                                                          0x2b3
-+#define mmMVP_CRC_RESULT_BLUE_GREEN                                             0x2b4
-+#define mmMVP_CRC_RESULT_RED                                                    0x2b5
-+#define mmMVP_CONTROL3                                                          0x2b6
-+#define mmMVP_RECEIVE_CNT_CNTL1                                                 0x2b7
-+#define mmMVP_RECEIVE_CNT_CNTL2                                                 0x2b8
-+#define mmMVP_DEBUG                                                             0x2bb
-+#define mmMVP_TEST_DEBUG_INDEX                                                  0x2b9
-+#define mmMVP_TEST_DEBUG_DATA                                                   0x2ba
-+#define ixMVP_DEBUG_12                                                          0xc
-+#define ixMVP_DEBUG_13                                                          0xd
-+#define ixMVP_DEBUG_14                                                          0xe
-+#define ixMVP_DEBUG_15                                                          0xf
-+#define ixMVP_DEBUG_16                                                          0x10
-+#define ixMVP_DEBUG_17                                                          0x11
-+#define mmSCL_COEF_RAM_SELECT                                                   0x1b40
-+#define mmSCL0_SCL_COEF_RAM_SELECT                                              0x1b40
-+#define mmSCL1_SCL_COEF_RAM_SELECT                                              0x1d40
-+#define mmSCL2_SCL_COEF_RAM_SELECT                                              0x1f40
-+#define mmSCL3_SCL_COEF_RAM_SELECT                                              0x4140
-+#define mmSCL4_SCL_COEF_RAM_SELECT                                              0x4340
-+#define mmSCL5_SCL_COEF_RAM_SELECT                                              0x4540
-+#define mmSCL_COEF_RAM_TAP_DATA                                                 0x1b41
-+#define mmSCL0_SCL_COEF_RAM_TAP_DATA                                            0x1b41
-+#define mmSCL1_SCL_COEF_RAM_TAP_DATA                                            0x1d41
-+#define mmSCL2_SCL_COEF_RAM_TAP_DATA                                            0x1f41
-+#define mmSCL3_SCL_COEF_RAM_TAP_DATA                                            0x4141
-+#define mmSCL4_SCL_COEF_RAM_TAP_DATA                                            0x4341
-+#define mmSCL5_SCL_COEF_RAM_TAP_DATA                                            0x4541
-+#define mmSCL_MODE                                                              0x1b42
-+#define mmSCL0_SCL_MODE                                                         0x1b42
-+#define mmSCL1_SCL_MODE                                                         0x1d42
-+#define mmSCL2_SCL_MODE                                                         0x1f42
-+#define mmSCL3_SCL_MODE                                                         0x4142
-+#define mmSCL4_SCL_MODE                                                         0x4342
-+#define mmSCL5_SCL_MODE                                                         0x4542
-+#define mmSCL_TAP_CONTROL                                                       0x1b43
-+#define mmSCL0_SCL_TAP_CONTROL                                                  0x1b43
-+#define mmSCL1_SCL_TAP_CONTROL                                                  0x1d43
-+#define mmSCL2_SCL_TAP_CONTROL                                                  0x1f43
-+#define mmSCL3_SCL_TAP_CONTROL                                                  0x4143
-+#define mmSCL4_SCL_TAP_CONTROL                                                  0x4343
-+#define mmSCL5_SCL_TAP_CONTROL                                                  0x4543
-+#define mmSCL_CONTROL                                                           0x1b44
-+#define mmSCL0_SCL_CONTROL                                                      0x1b44
-+#define mmSCL1_SCL_CONTROL                                                      0x1d44
-+#define mmSCL2_SCL_CONTROL                                                      0x1f44
-+#define mmSCL3_SCL_CONTROL                                                      0x4144
-+#define mmSCL4_SCL_CONTROL                                                      0x4344
-+#define mmSCL5_SCL_CONTROL                                                      0x4544
-+#define mmSCL_BYPASS_CONTROL                                                    0x1b45
-+#define mmSCL0_SCL_BYPASS_CONTROL                                               0x1b45
-+#define mmSCL1_SCL_BYPASS_CONTROL                                               0x1d45
-+#define mmSCL2_SCL_BYPASS_CONTROL                                               0x1f45
-+#define mmSCL3_SCL_BYPASS_CONTROL                                               0x4145
-+#define mmSCL4_SCL_BYPASS_CONTROL                                               0x4345
-+#define mmSCL5_SCL_BYPASS_CONTROL                                               0x4545
-+#define mmSCL_MANUAL_REPLICATE_CONTROL                                          0x1b46
-+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL                                     0x1b46
-+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL                                     0x1d46
-+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL                                     0x1f46
-+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                                     0x4146
-+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                                     0x4346
-+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                                     0x4546
-+#define mmSCL_AUTOMATIC_MODE_CONTROL                                            0x1b47
-+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL                                       0x1b47
-+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL                                       0x1d47
-+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL                                       0x1f47
-+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                                       0x4147
-+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                                       0x4347
-+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                                       0x4547
-+#define mmSCL_HORZ_FILTER_CONTROL                                               0x1b48
-+#define mmSCL0_SCL_HORZ_FILTER_CONTROL                                          0x1b48
-+#define mmSCL1_SCL_HORZ_FILTER_CONTROL                                          0x1d48
-+#define mmSCL2_SCL_HORZ_FILTER_CONTROL                                          0x1f48
-+#define mmSCL3_SCL_HORZ_FILTER_CONTROL                                          0x4148
-+#define mmSCL4_SCL_HORZ_FILTER_CONTROL                                          0x4348
-+#define mmSCL5_SCL_HORZ_FILTER_CONTROL                                          0x4548
-+#define mmSCL_HORZ_FILTER_SCALE_RATIO                                           0x1b49
-+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1b49
-+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1d49
-+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1f49
-+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4149
-+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4349
-+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4549
-+#define mmSCL_HORZ_FILTER_INIT                                                  0x1b4a
-+#define mmSCL0_SCL_HORZ_FILTER_INIT                                             0x1b4a
-+#define mmSCL1_SCL_HORZ_FILTER_INIT                                             0x1d4a
-+#define mmSCL2_SCL_HORZ_FILTER_INIT                                             0x1f4a
-+#define mmSCL3_SCL_HORZ_FILTER_INIT                                             0x414a
-+#define mmSCL4_SCL_HORZ_FILTER_INIT                                             0x434a
-+#define mmSCL5_SCL_HORZ_FILTER_INIT                                             0x454a
-+#define mmSCL_VERT_FILTER_CONTROL                                               0x1b4b
-+#define mmSCL0_SCL_VERT_FILTER_CONTROL                                          0x1b4b
-+#define mmSCL1_SCL_VERT_FILTER_CONTROL                                          0x1d4b
-+#define mmSCL2_SCL_VERT_FILTER_CONTROL                                          0x1f4b
-+#define mmSCL3_SCL_VERT_FILTER_CONTROL                                          0x414b
-+#define mmSCL4_SCL_VERT_FILTER_CONTROL                                          0x434b
-+#define mmSCL5_SCL_VERT_FILTER_CONTROL                                          0x454b
-+#define mmSCL_VERT_FILTER_SCALE_RATIO                                           0x1b4c
-+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO                                      0x1b4c
-+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO                                      0x1d4c
-+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO                                      0x1f4c
-+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                                      0x414c
-+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                                      0x434c
-+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                                      0x454c
-+#define mmSCL_VERT_FILTER_INIT                                                  0x1b4d
-+#define mmSCL0_SCL_VERT_FILTER_INIT                                             0x1b4d
-+#define mmSCL1_SCL_VERT_FILTER_INIT                                             0x1d4d
-+#define mmSCL2_SCL_VERT_FILTER_INIT                                             0x1f4d
-+#define mmSCL3_SCL_VERT_FILTER_INIT                                             0x414d
-+#define mmSCL4_SCL_VERT_FILTER_INIT                                             0x434d
-+#define mmSCL5_SCL_VERT_FILTER_INIT                                             0x454d
-+#define mmSCL_VERT_FILTER_INIT_BOT                                              0x1b4e
-+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT                                         0x1b4e
-+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT                                         0x1d4e
-+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT                                         0x1f4e
-+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT                                         0x414e
-+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT                                         0x434e
-+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT                                         0x454e
-+#define mmSCL_ROUND_OFFSET                                                      0x1b4f
-+#define mmSCL0_SCL_ROUND_OFFSET                                                 0x1b4f
-+#define mmSCL1_SCL_ROUND_OFFSET                                                 0x1d4f
-+#define mmSCL2_SCL_ROUND_OFFSET                                                 0x1f4f
-+#define mmSCL3_SCL_ROUND_OFFSET                                                 0x414f
-+#define mmSCL4_SCL_ROUND_OFFSET                                                 0x434f
-+#define mmSCL5_SCL_ROUND_OFFSET                                                 0x454f
-+#define mmSCL_UPDATE                                                            0x1b51
-+#define mmSCL0_SCL_UPDATE                                                       0x1b51
-+#define mmSCL1_SCL_UPDATE                                                       0x1d51
-+#define mmSCL2_SCL_UPDATE                                                       0x1f51
-+#define mmSCL3_SCL_UPDATE                                                       0x4151
-+#define mmSCL4_SCL_UPDATE                                                       0x4351
-+#define mmSCL5_SCL_UPDATE                                                       0x4551
-+#define mmSCL_F_SHARP_CONTROL                                                   0x1b53
-+#define mmSCL0_SCL_F_SHARP_CONTROL                                              0x1b53
-+#define mmSCL1_SCL_F_SHARP_CONTROL                                              0x1d53
-+#define mmSCL2_SCL_F_SHARP_CONTROL                                              0x1f53
-+#define mmSCL3_SCL_F_SHARP_CONTROL                                              0x4153
-+#define mmSCL4_SCL_F_SHARP_CONTROL                                              0x4353
-+#define mmSCL5_SCL_F_SHARP_CONTROL                                              0x4553
-+#define mmSCL_ALU_CONTROL                                                       0x1b54
-+#define mmSCL0_SCL_ALU_CONTROL                                                  0x1b54
-+#define mmSCL1_SCL_ALU_CONTROL                                                  0x1d54
-+#define mmSCL2_SCL_ALU_CONTROL                                                  0x1f54
-+#define mmSCL3_SCL_ALU_CONTROL                                                  0x4154
-+#define mmSCL4_SCL_ALU_CONTROL                                                  0x4354
-+#define mmSCL5_SCL_ALU_CONTROL                                                  0x4554
-+#define mmSCL_COEF_RAM_CONFLICT_STATUS                                          0x1b55
-+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1b55
-+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1d55
-+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1f55
-+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4155
-+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4355
-+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4555
-+#define mmVIEWPORT_START_SECONDARY                                              0x1b5b
-+#define mmSCL0_VIEWPORT_START_SECONDARY                                         0x1b5b
-+#define mmSCL1_VIEWPORT_START_SECONDARY                                         0x1d5b
-+#define mmSCL2_VIEWPORT_START_SECONDARY                                         0x1f5b
-+#define mmSCL3_VIEWPORT_START_SECONDARY                                         0x415b
-+#define mmSCL4_VIEWPORT_START_SECONDARY                                         0x435b
-+#define mmSCL5_VIEWPORT_START_SECONDARY                                         0x455b
-+#define mmVIEWPORT_START                                                        0x1b5c
-+#define mmSCL0_VIEWPORT_START                                                   0x1b5c
-+#define mmSCL1_VIEWPORT_START                                                   0x1d5c
-+#define mmSCL2_VIEWPORT_START                                                   0x1f5c
-+#define mmSCL3_VIEWPORT_START                                                   0x415c
-+#define mmSCL4_VIEWPORT_START                                                   0x435c
-+#define mmSCL5_VIEWPORT_START                                                   0x455c
-+#define mmVIEWPORT_SIZE                                                         0x1b5d
-+#define mmSCL0_VIEWPORT_SIZE                                                    0x1b5d
-+#define mmSCL1_VIEWPORT_SIZE                                                    0x1d5d
-+#define mmSCL2_VIEWPORT_SIZE                                                    0x1f5d
-+#define mmSCL3_VIEWPORT_SIZE                                                    0x415d
-+#define mmSCL4_VIEWPORT_SIZE                                                    0x435d
-+#define mmSCL5_VIEWPORT_SIZE                                                    0x455d
-+#define mmEXT_OVERSCAN_LEFT_RIGHT                                               0x1b5e
-+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT                                          0x1b5e
-+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT                                          0x1d5e
-+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT                                          0x1f5e
-+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                                          0x415e
-+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                                          0x435e
-+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                                          0x455e
-+#define mmEXT_OVERSCAN_TOP_BOTTOM                                               0x1b5f
-+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM                                          0x1b5f
-+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM                                          0x1d5f
-+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM                                          0x1f5f
-+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                                          0x415f
-+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                                          0x435f
-+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                                          0x455f
-+#define mmSCL_MODE_CHANGE_DET1                                                  0x1b60
-+#define mmSCL0_SCL_MODE_CHANGE_DET1                                             0x1b60
-+#define mmSCL1_SCL_MODE_CHANGE_DET1                                             0x1d60
-+#define mmSCL2_SCL_MODE_CHANGE_DET1                                             0x1f60
-+#define mmSCL3_SCL_MODE_CHANGE_DET1                                             0x4160
-+#define mmSCL4_SCL_MODE_CHANGE_DET1                                             0x4360
-+#define mmSCL5_SCL_MODE_CHANGE_DET1                                             0x4560
-+#define mmSCL_MODE_CHANGE_DET2                                                  0x1b61
-+#define mmSCL0_SCL_MODE_CHANGE_DET2                                             0x1b61
-+#define mmSCL1_SCL_MODE_CHANGE_DET2                                             0x1d61
-+#define mmSCL2_SCL_MODE_CHANGE_DET2                                             0x1f61
-+#define mmSCL3_SCL_MODE_CHANGE_DET2                                             0x4161
-+#define mmSCL4_SCL_MODE_CHANGE_DET2                                             0x4361
-+#define mmSCL5_SCL_MODE_CHANGE_DET2                                             0x4561
-+#define mmSCL_MODE_CHANGE_DET3                                                  0x1b62
-+#define mmSCL0_SCL_MODE_CHANGE_DET3                                             0x1b62
-+#define mmSCL1_SCL_MODE_CHANGE_DET3                                             0x1d62
-+#define mmSCL2_SCL_MODE_CHANGE_DET3                                             0x1f62
-+#define mmSCL3_SCL_MODE_CHANGE_DET3                                             0x4162
-+#define mmSCL4_SCL_MODE_CHANGE_DET3                                             0x4362
-+#define mmSCL5_SCL_MODE_CHANGE_DET3                                             0x4562
-+#define mmSCL_MODE_CHANGE_MASK                                                  0x1b63
-+#define mmSCL0_SCL_MODE_CHANGE_MASK                                             0x1b63
-+#define mmSCL1_SCL_MODE_CHANGE_MASK                                             0x1d63
-+#define mmSCL2_SCL_MODE_CHANGE_MASK                                             0x1f63
-+#define mmSCL3_SCL_MODE_CHANGE_MASK                                             0x4163
-+#define mmSCL4_SCL_MODE_CHANGE_MASK                                             0x4363
-+#define mmSCL5_SCL_MODE_CHANGE_MASK                                             0x4563
-+#define mmSCL_DEBUG2                                                            0x1b69
-+#define mmSCL0_SCL_DEBUG2                                                       0x1b69
-+#define mmSCL1_SCL_DEBUG2                                                       0x1d69
-+#define mmSCL2_SCL_DEBUG2                                                       0x1f69
-+#define mmSCL3_SCL_DEBUG2                                                       0x4169
-+#define mmSCL4_SCL_DEBUG2                                                       0x4369
-+#define mmSCL5_SCL_DEBUG2                                                       0x4569
-+#define mmSCL_DEBUG                                                             0x1b6a
-+#define mmSCL0_SCL_DEBUG                                                        0x1b6a
-+#define mmSCL1_SCL_DEBUG                                                        0x1d6a
-+#define mmSCL2_SCL_DEBUG                                                        0x1f6a
-+#define mmSCL3_SCL_DEBUG                                                        0x416a
-+#define mmSCL4_SCL_DEBUG                                                        0x436a
-+#define mmSCL5_SCL_DEBUG                                                        0x456a
-+#define mmSCL_TEST_DEBUG_INDEX                                                  0x1b6b
-+#define mmSCL0_SCL_TEST_DEBUG_INDEX                                             0x1b6b
-+#define mmSCL1_SCL_TEST_DEBUG_INDEX                                             0x1d6b
-+#define mmSCL2_SCL_TEST_DEBUG_INDEX                                             0x1f6b
-+#define mmSCL3_SCL_TEST_DEBUG_INDEX                                             0x416b
-+#define mmSCL4_SCL_TEST_DEBUG_INDEX                                             0x436b
-+#define mmSCL5_SCL_TEST_DEBUG_INDEX                                             0x456b
-+#define mmSCL_TEST_DEBUG_DATA                                                   0x1b6c
-+#define mmSCL0_SCL_TEST_DEBUG_DATA                                              0x1b6c
-+#define mmSCL1_SCL_TEST_DEBUG_DATA                                              0x1d6c
-+#define mmSCL2_SCL_TEST_DEBUG_DATA                                              0x1f6c
-+#define mmSCL3_SCL_TEST_DEBUG_DATA                                              0x416c
-+#define mmSCL4_SCL_TEST_DEBUG_DATA                                              0x436c
-+#define mmSCL5_SCL_TEST_DEBUG_DATA                                              0x456c
-+#define mmSCLV_COEF_RAM_SELECT                                                  0x4670
-+#define mmSCLV0_SCLV_COEF_RAM_SELECT                                            0x4670
-+#define mmSCLV1_SCLV_COEF_RAM_SELECT                                            0x9870
-+#define mmSCLV_COEF_RAM_TAP_DATA                                                0x4671
-+#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA                                          0x4671
-+#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA                                          0x9871
-+#define mmSCLV_MODE                                                             0x4672
-+#define mmSCLV0_SCLV_MODE                                                       0x4672
-+#define mmSCLV1_SCLV_MODE                                                       0x9872
-+#define mmSCLV_TAP_CONTROL                                                      0x4673
-+#define mmSCLV0_SCLV_TAP_CONTROL                                                0x4673
-+#define mmSCLV1_SCLV_TAP_CONTROL                                                0x9873
-+#define mmSCLV_CONTROL                                                          0x4674
-+#define mmSCLV0_SCLV_CONTROL                                                    0x4674
-+#define mmSCLV1_SCLV_CONTROL                                                    0x9874
-+#define mmSCLV_MANUAL_REPLICATE_CONTROL                                         0x4675
-+#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL                                   0x4675
-+#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL                                   0x9875
-+#define mmSCLV_AUTOMATIC_MODE_CONTROL                                           0x4676
-+#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL                                     0x4676
-+#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL                                     0x9876
-+#define mmSCLV_HORZ_FILTER_CONTROL                                              0x4677
-+#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL                                        0x4677
-+#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL                                        0x9877
-+#define mmSCLV_HORZ_FILTER_SCALE_RATIO                                          0x4678
-+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO                                    0x4678
-+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO                                    0x9878
-+#define mmSCLV_HORZ_FILTER_INIT                                                 0x4679
-+#define mmSCLV0_SCLV_HORZ_FILTER_INIT                                           0x4679
-+#define mmSCLV1_SCLV_HORZ_FILTER_INIT                                           0x9879
-+#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C                                        0x467a
-+#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C                                  0x467a
-+#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C                                  0x987a
-+#define mmSCLV_HORZ_FILTER_INIT_C                                               0x467b
-+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C                                         0x467b
-+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C                                         0x987b
-+#define mmSCLV_VERT_FILTER_CONTROL                                              0x467c
-+#define mmSCLV0_SCLV_VERT_FILTER_CONTROL                                        0x467c
-+#define mmSCLV1_SCLV_VERT_FILTER_CONTROL                                        0x987c
-+#define mmSCLV_VERT_FILTER_SCALE_RATIO                                          0x467d
-+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO                                    0x467d
-+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO                                    0x987d
-+#define mmSCLV_VERT_FILTER_INIT                                                 0x467e
-+#define mmSCLV0_SCLV_VERT_FILTER_INIT                                           0x467e
-+#define mmSCLV1_SCLV_VERT_FILTER_INIT                                           0x987e
-+#define mmSCLV_VERT_FILTER_INIT_BOT                                             0x467f
-+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT                                       0x467f
-+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT                                       0x987f
-+#define mmSCLV_VERT_FILTER_SCALE_RATIO_C                                        0x4680
-+#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C                                  0x4680
-+#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C                                  0x9880
-+#define mmSCLV_VERT_FILTER_INIT_C                                               0x4681
-+#define mmSCLV0_SCLV_VERT_FILTER_INIT_C                                         0x4681
-+#define mmSCLV1_SCLV_VERT_FILTER_INIT_C                                         0x9881
-+#define mmSCLV_VERT_FILTER_INIT_BOT_C                                           0x4682
-+#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C                                     0x4682
-+#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C                                     0x9882
-+#define mmSCLV_ROUND_OFFSET                                                     0x4683
-+#define mmSCLV0_SCLV_ROUND_OFFSET                                               0x4683
-+#define mmSCLV1_SCLV_ROUND_OFFSET                                               0x9883
-+#define mmSCLV_UPDATE                                                           0x4684
-+#define mmSCLV0_SCLV_UPDATE                                                     0x4684
-+#define mmSCLV1_SCLV_UPDATE                                                     0x9884
-+#define mmSCLV_ALU_CONTROL                                                      0x4685
-+#define mmSCLV0_SCLV_ALU_CONTROL                                                0x4685
-+#define mmSCLV1_SCLV_ALU_CONTROL                                                0x9885
-+#define mmSCLV_VIEWPORT_START                                                   0x4686
-+#define mmSCLV0_SCLV_VIEWPORT_START                                             0x4686
-+#define mmSCLV1_SCLV_VIEWPORT_START                                             0x9886
-+#define mmSCLV_VIEWPORT_START_SECONDARY                                         0x4687
-+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY                                   0x4687
-+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY                                   0x9887
-+#define mmSCLV_VIEWPORT_SIZE                                                    0x4688
-+#define mmSCLV0_SCLV_VIEWPORT_SIZE                                              0x4688
-+#define mmSCLV1_SCLV_VIEWPORT_SIZE                                              0x9888
-+#define mmSCLV_VIEWPORT_START_C                                                 0x4689
-+#define mmSCLV0_SCLV_VIEWPORT_START_C                                           0x4689
-+#define mmSCLV1_SCLV_VIEWPORT_START_C                                           0x9889
-+#define mmSCLV_VIEWPORT_START_SECONDARY_C                                       0x468a
-+#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C                                 0x468a
-+#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C                                 0x988a
-+#define mmSCLV_VIEWPORT_SIZE_C                                                  0x468b
-+#define mmSCLV0_SCLV_VIEWPORT_SIZE_C                                            0x468b
-+#define mmSCLV1_SCLV_VIEWPORT_SIZE_C                                            0x988b
-+#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT                                          0x468c
-+#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT                                    0x468c
-+#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT                                    0x988c
-+#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM                                          0x468d
-+#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM                                    0x468d
-+#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM                                    0x988d
-+#define mmSCLV_MODE_CHANGE_DET1                                                 0x468e
-+#define mmSCLV0_SCLV_MODE_CHANGE_DET1                                           0x468e
-+#define mmSCLV1_SCLV_MODE_CHANGE_DET1                                           0x988e
-+#define mmSCLV_MODE_CHANGE_DET2                                                 0x468f
-+#define mmSCLV0_SCLV_MODE_CHANGE_DET2                                           0x468f
-+#define mmSCLV1_SCLV_MODE_CHANGE_DET2                                           0x988f
-+#define mmSCLV_MODE_CHANGE_DET3                                                 0x4690
-+#define mmSCLV0_SCLV_MODE_CHANGE_DET3                                           0x4690
-+#define mmSCLV1_SCLV_MODE_CHANGE_DET3                                           0x9890
-+#define mmSCLV_MODE_CHANGE_MASK                                                 0x4691
-+#define mmSCLV0_SCLV_MODE_CHANGE_MASK                                           0x4691
-+#define mmSCLV1_SCLV_MODE_CHANGE_MASK                                           0x9891
-+#define mmSCLV_HORZ_FILTER_INIT_BOT                                             0x4692
-+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT                                       0x4692
-+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT                                       0x9892
-+#define mmSCLV_HORZ_FILTER_INIT_BOT_C                                           0x4693
-+#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C                                     0x4693
-+#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C                                     0x9893
-+#define mmSCLV_DEBUG2                                                           0x4694
-+#define mmSCLV0_SCLV_DEBUG2                                                     0x4694
-+#define mmSCLV1_SCLV_DEBUG2                                                     0x9894
-+#define mmSCLV_DEBUG                                                            0x4695
-+#define mmSCLV0_SCLV_DEBUG                                                      0x4695
-+#define mmSCLV1_SCLV_DEBUG                                                      0x9895
-+#define mmSCLV_TEST_DEBUG_INDEX                                                 0x4696
-+#define mmSCLV0_SCLV_TEST_DEBUG_INDEX                                           0x4696
-+#define mmSCLV1_SCLV_TEST_DEBUG_INDEX                                           0x9896
-+#define mmSCLV_TEST_DEBUG_DATA                                                  0x4697
-+#define mmSCLV0_SCLV_TEST_DEBUG_DATA                                            0x4697
-+#define mmSCLV1_SCLV_TEST_DEBUG_DATA                                            0x9897
-+#define mmCOL_MAN_UPDATE                                                        0x46a4
-+#define mmCOL_MAN0_COL_MAN_UPDATE                                               0x46a4
-+#define mmCOL_MAN1_COL_MAN_UPDATE                                               0x98a4
-+#define mmCOL_MAN_INPUT_CSC_CONTROL                                             0x46a5
-+#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL                                    0x46a5
-+#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL                                    0x98a5
-+#define mmINPUT_CSC_C11_C12_A                                                   0x46a6
-+#define mmCOL_MAN0_INPUT_CSC_C11_C12_A                                          0x46a6
-+#define mmCOL_MAN1_INPUT_CSC_C11_C12_A                                          0x98a6
-+#define mmINPUT_CSC_C13_C14_A                                                   0x46a7
-+#define mmCOL_MAN0_INPUT_CSC_C13_C14_A                                          0x46a7
-+#define mmCOL_MAN1_INPUT_CSC_C13_C14_A                                          0x98a7
-+#define mmINPUT_CSC_C21_C22_A                                                   0x46a8
-+#define mmCOL_MAN0_INPUT_CSC_C21_C22_A                                          0x46a8
-+#define mmCOL_MAN1_INPUT_CSC_C21_C22_A                                          0x98a8
-+#define mmINPUT_CSC_C23_C24_A                                                   0x46a9
-+#define mmCOL_MAN0_INPUT_CSC_C23_C24_A                                          0x46a9
-+#define mmCOL_MAN1_INPUT_CSC_C23_C24_A                                          0x98a9
-+#define mmINPUT_CSC_C31_C32_A                                                   0x46aa
-+#define mmCOL_MAN0_INPUT_CSC_C31_C32_A                                          0x46aa
-+#define mmCOL_MAN1_INPUT_CSC_C31_C32_A                                          0x98aa
-+#define mmINPUT_CSC_C33_C34_A                                                   0x46ab
-+#define mmCOL_MAN0_INPUT_CSC_C33_C34_A                                          0x46ab
-+#define mmCOL_MAN1_INPUT_CSC_C33_C34_A                                          0x98ab
-+#define mmINPUT_CSC_C11_C12_B                                                   0x46ac
-+#define mmCOL_MAN0_INPUT_CSC_C11_C12_B                                          0x46ac
-+#define mmCOL_MAN1_INPUT_CSC_C11_C12_B                                          0x98ac
-+#define mmINPUT_CSC_C13_C14_B                                                   0x46ad
-+#define mmCOL_MAN0_INPUT_CSC_C13_C14_B                                          0x46ad
-+#define mmCOL_MAN1_INPUT_CSC_C13_C14_B                                          0x98ad
-+#define mmINPUT_CSC_C21_C22_B                                                   0x46ae
-+#define mmCOL_MAN0_INPUT_CSC_C21_C22_B                                          0x46ae
-+#define mmCOL_MAN1_INPUT_CSC_C21_C22_B                                          0x98ae
-+#define mmINPUT_CSC_C23_C24_B                                                   0x46af
-+#define mmCOL_MAN0_INPUT_CSC_C23_C24_B                                          0x46af
-+#define mmCOL_MAN1_INPUT_CSC_C23_C24_B                                          0x98af
-+#define mmINPUT_CSC_C31_C32_B                                                   0x46b0
-+#define mmCOL_MAN0_INPUT_CSC_C31_C32_B                                          0x46b0
-+#define mmCOL_MAN1_INPUT_CSC_C31_C32_B                                          0x98b0
-+#define mmINPUT_CSC_C33_C34_B                                                   0x46b1
-+#define mmCOL_MAN0_INPUT_CSC_C33_C34_B                                          0x46b1
-+#define mmCOL_MAN1_INPUT_CSC_C33_C34_B                                          0x98b1
-+#define mmPRESCALE_CONTROL                                                      0x46b2
-+#define mmCOL_MAN0_PRESCALE_CONTROL                                             0x46b2
-+#define mmCOL_MAN1_PRESCALE_CONTROL                                             0x98b2
-+#define mmPRESCALE_VALUES_R                                                     0x46b3
-+#define mmCOL_MAN0_PRESCALE_VALUES_R                                            0x46b3
-+#define mmCOL_MAN1_PRESCALE_VALUES_R                                            0x98b3
-+#define mmPRESCALE_VALUES_G                                                     0x46b4
-+#define mmCOL_MAN0_PRESCALE_VALUES_G                                            0x46b4
-+#define mmCOL_MAN1_PRESCALE_VALUES_G                                            0x98b4
-+#define mmPRESCALE_VALUES_B                                                     0x46b5
-+#define mmCOL_MAN0_PRESCALE_VALUES_B                                            0x46b5
-+#define mmCOL_MAN1_PRESCALE_VALUES_B                                            0x98b5
-+#define mmCOL_MAN_OUTPUT_CSC_CONTROL                                            0x46b6
-+#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL                                   0x46b6
-+#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL                                   0x98b6
-+#define mmOUTPUT_CSC_C11_C12_A                                                  0x46b7
-+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A                                         0x46b7
-+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A                                         0x98b7
-+#define mmOUTPUT_CSC_C13_C14_A                                                  0x46b8
-+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A                                         0x46b8
-+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A                                         0x98b8
-+#define mmOUTPUT_CSC_C21_C22_A                                                  0x46b9
-+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A                                         0x46b9
-+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A                                         0x98b9
-+#define mmOUTPUT_CSC_C23_C24_A                                                  0x46ba
-+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A                                         0x46ba
-+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A                                         0x98ba
-+#define mmOUTPUT_CSC_C31_C32_A                                                  0x46bb
-+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A                                         0x46bb
-+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A                                         0x98bb
-+#define mmOUTPUT_CSC_C33_C34_A                                                  0x46bc
-+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A                                         0x46bc
-+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A                                         0x98bc
-+#define mmOUTPUT_CSC_C11_C12_B                                                  0x46bd
-+#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B                                         0x46bd
-+#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B                                         0x98bd
-+#define mmOUTPUT_CSC_C13_C14_B                                                  0x46be
-+#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B                                         0x46be
-+#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B                                         0x98be
-+#define mmOUTPUT_CSC_C21_C22_B                                                  0x46bf
-+#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B                                         0x46bf
-+#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B                                         0x98bf
-+#define mmOUTPUT_CSC_C23_C24_B                                                  0x46c0
-+#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B                                         0x46c0
-+#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B                                         0x98c0
-+#define mmOUTPUT_CSC_C31_C32_B                                                  0x46c1
-+#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B                                         0x46c1
-+#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B                                         0x98c1
-+#define mmOUTPUT_CSC_C33_C34_B                                                  0x46c2
-+#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B                                         0x46c2
-+#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B                                         0x98c2
-+#define mmDENORM_CLAMP_CONTROL                                                  0x46c3
-+#define mmCOL_MAN0_DENORM_CLAMP_CONTROL                                         0x46c3
-+#define mmCOL_MAN1_DENORM_CLAMP_CONTROL                                         0x98c3
-+#define mmDENORM_CLAMP_RANGE_R_CR                                               0x46c4
-+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR                                      0x46c4
-+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR                                      0x98c4
-+#define mmDENORM_CLAMP_RANGE_G_Y                                                0x46c5
-+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y                                       0x46c5
-+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y                                       0x98c5
-+#define mmDENORM_CLAMP_RANGE_B_CB                                               0x46c6
-+#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB                                      0x46c6
-+#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB                                      0x98c6
-+#define mmCOL_MAN_FP_CONVERTED_FIELD                                            0x46c7
-+#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD                                   0x46c7
-+#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD                                   0x98c7
-+#define mmGAMMA_CORR_CONTROL                                                    0x46c8
-+#define mmCOL_MAN0_GAMMA_CORR_CONTROL                                           0x46c8
-+#define mmCOL_MAN1_GAMMA_CORR_CONTROL                                           0x98c8
-+#define mmGAMMA_CORR_LUT_INDEX                                                  0x46c9
-+#define mmCOL_MAN0_GAMMA_CORR_LUT_INDEX                                         0x46c9
-+#define mmCOL_MAN1_GAMMA_CORR_LUT_INDEX                                         0x98c9
-+#define mmGAMMA_CORR_LUT_DATA                                                   0x46ca
-+#define mmCOL_MAN0_GAMMA_CORR_LUT_DATA                                          0x46ca
-+#define mmCOL_MAN1_GAMMA_CORR_LUT_DATA                                          0x98ca
-+#define mmGAMMA_CORR_LUT_WRITE_EN_MASK                                          0x46cb
-+#define mmCOL_MAN0_GAMMA_CORR_LUT_WRITE_EN_MASK                                 0x46cb
-+#define mmCOL_MAN1_GAMMA_CORR_LUT_WRITE_EN_MASK                                 0x98cb
-+#define mmGAMMA_CORR_CNTLA_START_CNTL                                           0x46cc
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_START_CNTL                                  0x46cc
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_START_CNTL                                  0x98cc
-+#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL                                           0x46cd
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_SLOPE_CNTL                                  0x46cd
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_SLOPE_CNTL                                  0x98cd
-+#define mmGAMMA_CORR_CNTLA_END_CNTL1                                            0x46ce
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL1                                   0x46ce
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL1                                   0x98ce
-+#define mmGAMMA_CORR_CNTLA_END_CNTL2                                            0x46cf
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL2                                   0x46cf
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL2                                   0x98cf
-+#define mmGAMMA_CORR_CNTLA_REGION_0_1                                           0x46d0
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_0_1                                  0x46d0
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_0_1                                  0x98d0
-+#define mmGAMMA_CORR_CNTLA_REGION_2_3                                           0x46d1
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_2_3                                  0x46d1
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_2_3                                  0x98d1
-+#define mmGAMMA_CORR_CNTLA_REGION_4_5                                           0x46d2
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_4_5                                  0x46d2
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_4_5                                  0x98d2
-+#define mmGAMMA_CORR_CNTLA_REGION_6_7                                           0x46d3
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_6_7                                  0x46d3
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_6_7                                  0x98d3
-+#define mmGAMMA_CORR_CNTLA_REGION_8_9                                           0x46d4
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_8_9                                  0x46d4
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_8_9                                  0x98d4
-+#define mmGAMMA_CORR_CNTLA_REGION_10_11                                         0x46d5
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_10_11                                0x46d5
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_10_11                                0x98d5
-+#define mmGAMMA_CORR_CNTLA_REGION_12_13                                         0x46d6
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_12_13                                0x46d6
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_12_13                                0x98d6
-+#define mmGAMMA_CORR_CNTLA_REGION_14_15                                         0x46d7
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_14_15                                0x46d7
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_14_15                                0x98d7
-+#define mmGAMMA_CORR_CNTLB_START_CNTL                                           0x46d8
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_START_CNTL                                  0x46d8
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_START_CNTL                                  0x98d8
-+#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL                                           0x46d9
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_SLOPE_CNTL                                  0x46d9
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_SLOPE_CNTL                                  0x98d9
-+#define mmGAMMA_CORR_CNTLB_END_CNTL1                                            0x46da
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL1                                   0x46da
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL1                                   0x98da
-+#define mmGAMMA_CORR_CNTLB_END_CNTL2                                            0x46db
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL2                                   0x46db
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL2                                   0x98db
-+#define mmGAMMA_CORR_CNTLB_REGION_0_1                                           0x46dc
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_0_1                                  0x46dc
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_0_1                                  0x98dc
-+#define mmGAMMA_CORR_CNTLB_REGION_2_3                                           0x46dd
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_2_3                                  0x46dd
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_2_3                                  0x98dd
-+#define mmGAMMA_CORR_CNTLB_REGION_4_5                                           0x46de
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_4_5                                  0x46de
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_4_5                                  0x98de
-+#define mmGAMMA_CORR_CNTLB_REGION_6_7                                           0x46df
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_6_7                                  0x46df
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_6_7                                  0x98df
-+#define mmGAMMA_CORR_CNTLB_REGION_8_9                                           0x46e0
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_8_9                                  0x46e0
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_8_9                                  0x98e0
-+#define mmGAMMA_CORR_CNTLB_REGION_10_11                                         0x46e1
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_10_11                                0x46e1
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_10_11                                0x98e1
-+#define mmGAMMA_CORR_CNTLB_REGION_12_13                                         0x46e2
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_12_13                                0x46e2
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_12_13                                0x98e2
-+#define mmGAMMA_CORR_CNTLB_REGION_14_15                                         0x46e3
-+#define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_14_15                                0x46e3
-+#define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_14_15                                0x98e3
-+#define mmPACK_FIFO_ERROR                                                       0x46e4
-+#define mmCOL_MAN0_PACK_FIFO_ERROR                                              0x46e4
-+#define mmCOL_MAN1_PACK_FIFO_ERROR                                              0x98e4
-+#define mmOUTPUT_FIFO_ERROR                                                     0x46e5
-+#define mmCOL_MAN0_OUTPUT_FIFO_ERROR                                            0x46e5
-+#define mmCOL_MAN1_OUTPUT_FIFO_ERROR                                            0x98e5
-+#define mmINPUT_GAMMA_LUT_AUTOFILL                                              0x46e6
-+#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL                                     0x46e6
-+#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL                                     0x98e6
-+#define mmINPUT_GAMMA_LUT_RW_INDEX                                              0x46e7
-+#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX                                     0x46e7
-+#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX                                     0x98e7
-+#define mmINPUT_GAMMA_LUT_SEQ_COLOR                                             0x46e8
-+#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR                                    0x46e8
-+#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR                                    0x98e8
-+#define mmINPUT_GAMMA_LUT_PWL_DATA                                              0x46e9
-+#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA                                     0x46e9
-+#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA                                     0x98e9
-+#define mmINPUT_GAMMA_LUT_30_COLOR                                              0x46ea
-+#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR                                     0x46ea
-+#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR                                     0x98ea
-+#define mmCOL_MAN_INPUT_GAMMA_CONTROL1                                          0x46eb
-+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1                                 0x46eb
-+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1                                 0x98eb
-+#define mmCOL_MAN_INPUT_GAMMA_CONTROL2                                          0x46ec
-+#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2                                 0x46ec
-+#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2                                 0x98ec
-+#define mmINPUT_GAMMA_BW_OFFSETS_B                                              0x46ed
-+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B                                     0x46ed
-+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B                                     0x98ed
-+#define mmINPUT_GAMMA_BW_OFFSETS_G                                              0x46ee
-+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G                                     0x46ee
-+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G                                     0x98ee
-+#define mmINPUT_GAMMA_BW_OFFSETS_R                                              0x46ef
-+#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R                                     0x46ef
-+#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R                                     0x98ef
-+#define mmCOL_MAN_DEBUG_CONTROL                                                 0x46f0
-+#define mmCOL_MAN0_COL_MAN_DEBUG_CONTROL                                        0x46f0
-+#define mmCOL_MAN1_COL_MAN_DEBUG_CONTROL                                        0x98f0
-+#define mmCOL_MAN_TEST_DEBUG_INDEX                                              0x46f1
-+#define mmCOL_MAN0_COL_MAN_TEST_DEBUG_INDEX                                     0x46f1
-+#define mmCOL_MAN1_COL_MAN_TEST_DEBUG_INDEX                                     0x98f1
-+#define mmCOL_MAN_TEST_DEBUG_DATA                                               0x46f3
-+#define mmCOL_MAN0_COL_MAN_TEST_DEBUG_DATA                                      0x46f3
-+#define mmCOL_MAN1_COL_MAN_TEST_DEBUG_DATA                                      0x98f3
-+#define mmUNP_GRPH_ENABLE                                                       0x4600
-+#define mmUNP0_UNP_GRPH_ENABLE                                                  0x4600
-+#define mmUNP1_UNP_GRPH_ENABLE                                                  0x9800
-+#define mmUNP_GRPH_CONTROL                                                      0x4601
-+#define mmUNP0_UNP_GRPH_CONTROL                                                 0x4601
-+#define mmUNP1_UNP_GRPH_CONTROL                                                 0x9801
-+#define mmUNP_GRPH_CONTROL_C                                                    0x4602
-+#define mmUNP0_UNP_GRPH_CONTROL_C                                               0x4602
-+#define mmUNP1_UNP_GRPH_CONTROL_C                                               0x9802
-+#define mmUNP_GRPH_CONTROL_EXP                                                  0x4603
-+#define mmUNP0_UNP_GRPH_CONTROL_EXP                                             0x4603
-+#define mmUNP1_UNP_GRPH_CONTROL_EXP                                             0x9803
-+#define mmUNP_GRPH_SWAP_CNTL                                                    0x4605
-+#define mmUNP0_UNP_GRPH_SWAP_CNTL                                               0x4605
-+#define mmUNP1_UNP_GRPH_SWAP_CNTL                                               0x9805
-+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                                    0x4606
-+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                               0x4606
-+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                               0x9806
-+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                                    0x4607
-+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                               0x4607
-+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                               0x9807
-+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                               0x4608
-+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                          0x4608
-+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                          0x9808
-+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                               0x4609
-+#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                          0x4609
-+#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                          0x9809
-+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                             0x460a
-+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                        0x460a
-+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                        0x980a
-+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                             0x460b
-+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                        0x460b
-+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                        0x980b
-+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                        0x460c
-+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                   0x460c
-+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                   0x980c
-+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                        0x460d
-+#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                   0x460d
-+#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                   0x980d
-+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                                  0x460e
-+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                             0x460e
-+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                             0x980e
-+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                                  0x460f
-+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                             0x460f
-+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                             0x980f
-+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                             0x4610
-+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                        0x4610
-+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                        0x9810
-+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                             0x4611
-+#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                        0x4611
-+#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                        0x9811
-+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                           0x4612
-+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                      0x4612
-+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                      0x9812
-+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                           0x4613
-+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                      0x4613
-+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                      0x9813
-+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                      0x4614
-+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                 0x4614
-+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                 0x9814
-+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                      0x4615
-+#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                 0x4615
-+#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                 0x9815
-+#define mmUNP_GRPH_PITCH_L                                                      0x4616
-+#define mmUNP0_UNP_GRPH_PITCH_L                                                 0x4616
-+#define mmUNP1_UNP_GRPH_PITCH_L                                                 0x9816
-+#define mmUNP_GRPH_PITCH_C                                                      0x4617
-+#define mmUNP0_UNP_GRPH_PITCH_C                                                 0x4617
-+#define mmUNP1_UNP_GRPH_PITCH_C                                                 0x9817
-+#define mmUNP_GRPH_SURFACE_OFFSET_X_L                                           0x4618
-+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L                                      0x4618
-+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L                                      0x9818
-+#define mmUNP_GRPH_SURFACE_OFFSET_X_C                                           0x4619
-+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C                                      0x4619
-+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C                                      0x9819
-+#define mmUNP_GRPH_SURFACE_OFFSET_Y_L                                           0x461a
-+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L                                      0x461a
-+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L                                      0x981a
-+#define mmUNP_GRPH_SURFACE_OFFSET_Y_C                                           0x461b
-+#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C                                      0x461b
-+#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C                                      0x981b
-+#define mmUNP_GRPH_X_START_L                                                    0x461c
-+#define mmUNP0_UNP_GRPH_X_START_L                                               0x461c
-+#define mmUNP1_UNP_GRPH_X_START_L                                               0x981c
-+#define mmUNP_GRPH_X_START_C                                                    0x461d
-+#define mmUNP0_UNP_GRPH_X_START_C                                               0x461d
-+#define mmUNP1_UNP_GRPH_X_START_C                                               0x981d
-+#define mmUNP_GRPH_Y_START_L                                                    0x461e
-+#define mmUNP0_UNP_GRPH_Y_START_L                                               0x461e
-+#define mmUNP1_UNP_GRPH_Y_START_L                                               0x981e
-+#define mmUNP_GRPH_Y_START_C                                                    0x461f
-+#define mmUNP0_UNP_GRPH_Y_START_C                                               0x461f
-+#define mmUNP1_UNP_GRPH_Y_START_C                                               0x981f
-+#define mmUNP_GRPH_X_END_L                                                      0x4620
-+#define mmUNP0_UNP_GRPH_X_END_L                                                 0x4620
-+#define mmUNP1_UNP_GRPH_X_END_L                                                 0x9820
-+#define mmUNP_GRPH_X_END_C                                                      0x4621
-+#define mmUNP0_UNP_GRPH_X_END_C                                                 0x4621
-+#define mmUNP1_UNP_GRPH_X_END_C                                                 0x9821
-+#define mmUNP_GRPH_Y_END_L                                                      0x4622
-+#define mmUNP0_UNP_GRPH_Y_END_L                                                 0x4622
-+#define mmUNP1_UNP_GRPH_Y_END_L                                                 0x9822
-+#define mmUNP_GRPH_Y_END_C                                                      0x4623
-+#define mmUNP0_UNP_GRPH_Y_END_C                                                 0x4623
-+#define mmUNP1_UNP_GRPH_Y_END_C                                                 0x9823
-+#define mmUNP_GRPH_UPDATE                                                       0x4624
-+#define mmUNP0_UNP_GRPH_UPDATE                                                  0x4624
-+#define mmUNP1_UNP_GRPH_UPDATE                                                  0x9824
-+#define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT                                    0x463a
-+#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT                               0x463a
-+#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT                               0x983a
-+#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L                                      0x4625
-+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L                                 0x4625
-+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L                                 0x9825
-+#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C                                      0x4626
-+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C                                 0x4626
-+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C                                 0x9826
-+#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                                 0x4627
-+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                            0x4627
-+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                            0x9827
-+#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                                 0x4628
-+#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                            0x4628
-+#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                            0x9828
-+#define mmUNP_DVMM_PTE_CONTROL                                                  0x4629
-+#define mmUNP_GRPH_INTERRUPT_STATUS                                             0x462b
-+#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS                                        0x462b
-+#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS                                        0x982b
-+#define mmUNP_GRPH_INTERRUPT_CONTROL                                            0x462c
-+#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL                                       0x462c
-+#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL                                       0x982c
-+#define mmUNP_GRPH_STEREOSYNC_FLIP                                              0x462e
-+#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP                                         0x462e
-+#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP                                         0x982e
-+#define mmUNP_FLIP_CONTROL                                                      0x462f
-+#define mmUNP0_UNP_FLIP_CONTROL                                                 0x462f
-+#define mmUNP1_UNP_FLIP_CONTROL                                                 0x982f
-+#define mmUNP_CRC_CONTROL                                                       0x4630
-+#define mmUNP0_UNP_CRC_CONTROL                                                  0x4630
-+#define mmUNP1_UNP_CRC_CONTROL                                                  0x9830
-+#define mmUNP_CRC_MASK                                                          0x4631
-+#define mmUNP0_UNP_CRC_MASK                                                     0x4631
-+#define mmUNP1_UNP_CRC_MASK                                                     0x9831
-+#define mmUNP_CRC_CURRENT                                                       0x4632
-+#define mmUNP0_UNP_CRC_CURRENT                                                  0x4632
-+#define mmUNP1_UNP_CRC_CURRENT                                                  0x9832
-+#define mmUNP_CRC_LAST                                                          0x4633
-+#define mmUNP0_UNP_CRC_LAST                                                     0x4633
-+#define mmUNP1_UNP_CRC_LAST                                                     0x9833
-+#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x4634
-+#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4634
-+#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x9834
-+#define mmUNP_HW_ROTATION                                                       0x4635
-+#define mmUNP0_UNP_HW_ROTATION                                                  0x4635
-+#define mmUNP1_UNP_HW_ROTATION                                                  0x9835
-+#define mmUNP_DEBUG                                                             0x4636
-+#define mmUNP0_UNP_DEBUG                                                        0x4636
-+#define mmUNP1_UNP_DEBUG                                                        0x9836
-+#define mmUNP_DEBUG2                                                            0x4637
-+#define mmUNP0_UNP_DEBUG2                                                       0x4637
-+#define mmUNP1_UNP_DEBUG2                                                       0x9837
-+#define mmUNP_DVMM_DEBUG                                                        0x463b
-+#define mmUNP0_UNP_DVMM_DEBUG                                                   0x463b
-+#define mmUNP1_UNP_DVMM_DEBUG                                                   0x983b
-+#define mmUNP_TEST_DEBUG_INDEX                                                  0x4638
-+#define mmUNP0_UNP_TEST_DEBUG_INDEX                                             0x4638
-+#define mmUNP1_UNP_TEST_DEBUG_INDEX                                             0x9838
-+#define mmUNP_TEST_DEBUG_DATA                                                   0x4639
-+#define mmUNP0_UNP_TEST_DEBUG_DATA                                              0x4639
-+#define mmUNP1_UNP_TEST_DEBUG_DATA                                              0x9839
-+#define mmGENMO_WT                                                              0xf0
-+#define mmGENMO_RD                                                              0xf3
-+#define mmGENENB                                                                0xf0
-+#define mmGENFC_WT                                                              0xee
-+#define mmVGA0_GENFC_WT                                                         0xee
-+#define mmVGA1_GENFC_WT                                                         0xf6
-+#define mmGENFC_RD                                                              0xf2
-+#define mmGENS0                                                                 0xf0
-+#define mmGENS1                                                                 0xee
-+#define mmVGA0_GENS1                                                            0xee
-+#define mmVGA1_GENS1                                                            0xf6
-+#define mmDAC_DATA                                                              0xf2
-+#define mmDAC_MASK                                                              0xf1
-+#define mmDAC_R_INDEX                                                           0xf1
-+#define mmDAC_W_INDEX                                                           0xf2
-+#define mmSEQ8_IDX                                                              0xf1
-+#define mmSEQ8_DATA                                                             0xf1
-+#define ixSEQ00                                                                 0x0
-+#define ixSEQ01                                                                 0x1
-+#define ixSEQ02                                                                 0x2
-+#define ixSEQ03                                                                 0x3
-+#define ixSEQ04                                                                 0x4
-+#define mmCRTC8_IDX                                                             0xed
-+#define mmVGA0_CRTC8_IDX                                                        0xed
-+#define mmVGA1_CRTC8_IDX                                                        0xf5
-+#define mmCRTC8_DATA                                                            0xed
-+#define mmVGA0_CRTC8_DATA                                                       0xed
-+#define mmVGA1_CRTC8_DATA                                                       0xf5
-+#define ixCRT00                                                                 0x0
-+#define ixCRT01                                                                 0x1
-+#define ixCRT02                                                                 0x2
-+#define ixCRT03                                                                 0x3
-+#define ixCRT04                                                                 0x4
-+#define ixCRT05                                                                 0x5
-+#define ixCRT06                                                                 0x6
-+#define ixCRT07                                                                 0x7
-+#define ixCRT08                                                                 0x8
-+#define ixCRT09                                                                 0x9
-+#define ixCRT0A                                                                 0xa
-+#define ixCRT0B                                                                 0xb
-+#define ixCRT0C                                                                 0xc
-+#define ixCRT0D                                                                 0xd
-+#define ixCRT0E                                                                 0xe
-+#define ixCRT0F                                                                 0xf
-+#define ixCRT10                                                                 0x10
-+#define ixCRT11                                                                 0x11
-+#define ixCRT12                                                                 0x12
-+#define ixCRT13                                                                 0x13
-+#define ixCRT14                                                                 0x14
-+#define ixCRT15                                                                 0x15
-+#define ixCRT16                                                                 0x16
-+#define ixCRT17                                                                 0x17
-+#define ixCRT18                                                                 0x18
-+#define ixCRT1E                                                                 0x1e
-+#define ixCRT1F                                                                 0x1f
-+#define ixCRT22                                                                 0x22
-+#define mmGRPH8_IDX                                                             0xf3
-+#define mmGRPH8_DATA                                                            0xf3
-+#define ixGRA00                                                                 0x0
-+#define ixGRA01                                                                 0x1
-+#define ixGRA02                                                                 0x2
-+#define ixGRA03                                                                 0x3
-+#define ixGRA04                                                                 0x4
-+#define ixGRA05                                                                 0x5
-+#define ixGRA06                                                                 0x6
-+#define ixGRA07                                                                 0x7
-+#define ixGRA08                                                                 0x8
-+#define mmATTRX                                                                 0xf0
-+#define mmATTRDW                                                                0xf0
-+#define mmATTRDR                                                                0xf0
-+#define ixATTR00                                                                0x0
-+#define ixATTR01                                                                0x1
-+#define ixATTR02                                                                0x2
-+#define ixATTR03                                                                0x3
-+#define ixATTR04                                                                0x4
-+#define ixATTR05                                                                0x5
-+#define ixATTR06                                                                0x6
-+#define ixATTR07                                                                0x7
-+#define ixATTR08                                                                0x8
-+#define ixATTR09                                                                0x9
-+#define ixATTR0A                                                                0xa
-+#define ixATTR0B                                                                0xb
-+#define ixATTR0C                                                                0xc
-+#define ixATTR0D                                                                0xd
-+#define ixATTR0E                                                                0xe
-+#define ixATTR0F                                                                0xf
-+#define ixATTR10                                                                0x10
-+#define ixATTR11                                                                0x11
-+#define ixATTR12                                                                0x12
-+#define ixATTR13                                                                0x13
-+#define ixATTR14                                                                0x14
-+#define mmVGA_RENDER_CONTROL                                                    0xc0
-+#define mmVGA_SOURCE_SELECT                                                     0xfc
-+#define mmVGA_SEQUENCER_RESET_CONTROL                                           0xc1
-+#define mmVGA_MODE_CONTROL                                                      0xc2
-+#define mmVGA_SURFACE_PITCH_SELECT                                              0xc3
-+#define mmVGA_MEMORY_BASE_ADDRESS                                               0xc4
-+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                          0xc9
-+#define mmVGA_DISPBUF1_SURFACE_ADDR                                             0xc6
-+#define mmVGA_DISPBUF2_SURFACE_ADDR                                             0xc8
-+#define mmVGA_HDP_CONTROL                                                       0xca
-+#define mmVGA_CACHE_CONTROL                                                     0xcb
-+#define mmD1VGA_CONTROL                                                         0xcc
-+#define mmD2VGA_CONTROL                                                         0xce
-+#define mmD3VGA_CONTROL                                                         0xf8
-+#define mmD4VGA_CONTROL                                                         0xf9
-+#define mmD5VGA_CONTROL                                                         0xfa
-+#define mmD6VGA_CONTROL                                                         0xfb
-+#define mmVGA_HW_DEBUG                                                          0xcf
-+#define mmVGA_STATUS                                                            0xd0
-+#define mmVGA_INTERRUPT_CONTROL                                                 0xd1
-+#define mmVGA_STATUS_CLEAR                                                      0xd2
-+#define mmVGA_INTERRUPT_STATUS                                                  0xd3
-+#define mmVGA_MAIN_CONTROL                                                      0xd4
-+#define mmVGA_TEST_CONTROL                                                      0xd5
-+#define mmVGA_DEBUG_READBACK_INDEX                                              0xd6
-+#define mmVGA_DEBUG_READBACK_DATA                                               0xd7
-+#define mmVGA_MEM_WRITE_PAGE_ADDR                                               0x12
-+#define mmVGA_MEM_READ_PAGE_ADDR                                                0x13
-+#define mmVGA_TEST_DEBUG_INDEX                                                  0xc5
-+#define mmVGA_TEST_DEBUG_DATA                                                   0xc7
-+#define ixVGADCC_DBG_DCCIF_C                                                    0x7e
-+#define mmBPHYC_DAC_MACRO_CNTL                                                  0x48b9
-+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL                                          0x48ba
-+#define mmDPG_PIPE_ARBITRATION_CONTROL1                                         0x1b30
-+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1                                0x1b30
-+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1                                0x1d30
-+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1                                0x1f30
-+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                                0x4130
-+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                                0x4330
-+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                                0x4530
-+#define mmDPG_PIPE_ARBITRATION_CONTROL2                                         0x1b31
-+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2                                0x1b31
-+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2                                0x1d31
-+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2                                0x1f31
-+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                                0x4131
-+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                                0x4331
-+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                                0x4531
-+#define mmDPG_WATERMARK_MASK_CONTROL                                            0x1b32
-+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL                                   0x1b32
-+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL                                   0x1d32
-+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL                                   0x1f32
-+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                                   0x4132
-+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                                   0x4332
-+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                                   0x4532
-+#define mmDPG_PIPE_URGENCY_CONTROL                                              0x1b33
-+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL                                     0x1b33
-+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL                                     0x1d33
-+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL                                     0x1f33
-+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                                     0x4133
-+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                                     0x4333
-+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                                     0x4533
-+#define mmDPG_PIPE_DPM_CONTROL                                                  0x1b34
-+#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL                                         0x1b34
-+#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL                                         0x1d34
-+#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL                                         0x1f34
-+#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                                         0x4134
-+#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                                         0x4334
-+#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                                         0x4534
-+#define mmDPG_PIPE_STUTTER_CONTROL                                              0x1b35
-+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL                                     0x1b35
-+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL                                     0x1d35
-+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL                                     0x1f35
-+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                                     0x4135
-+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                                     0x4335
-+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                                     0x4535
-+#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL                                     0x1b36
-+#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1b36
-+#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1d36
-+#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1f36
-+#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4136
-+#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4336
-+#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4536
-+#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH                                     0x1b37
-+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1b37
-+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1d37
-+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1f37
-+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4137
-+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4337
-+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4537
-+#define mmDPG_REPEATER_PROGRAM                                                  0x1b3a
-+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM                                         0x1b3a
-+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM                                         0x1d3a
-+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM                                         0x1f3a
-+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM                                         0x413a
-+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM                                         0x433a
-+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM                                         0x453a
-+#define mmDPG_HW_DEBUG_A                                                        0x1b3b
-+#define mmDMIF_PG0_DPG_HW_DEBUG_A                                               0x1b3b
-+#define mmDMIF_PG1_DPG_HW_DEBUG_A                                               0x1d3b
-+#define mmDMIF_PG2_DPG_HW_DEBUG_A                                               0x1f3b
-+#define mmDMIF_PG3_DPG_HW_DEBUG_A                                               0x413b
-+#define mmDMIF_PG4_DPG_HW_DEBUG_A                                               0x433b
-+#define mmDMIF_PG5_DPG_HW_DEBUG_A                                               0x453b
-+#define mmDPG_HW_DEBUG_B                                                        0x1b3c
-+#define mmDMIF_PG0_DPG_HW_DEBUG_B                                               0x1b3c
-+#define mmDMIF_PG1_DPG_HW_DEBUG_B                                               0x1d3c
-+#define mmDMIF_PG2_DPG_HW_DEBUG_B                                               0x1f3c
-+#define mmDMIF_PG3_DPG_HW_DEBUG_B                                               0x413c
-+#define mmDMIF_PG4_DPG_HW_DEBUG_B                                               0x433c
-+#define mmDMIF_PG5_DPG_HW_DEBUG_B                                               0x453c
-+#define mmDPG_HW_DEBUG_11                                                       0x1b3d
-+#define mmDMIF_PG0_DPG_HW_DEBUG_11                                              0x1b3d
-+#define mmDMIF_PG1_DPG_HW_DEBUG_11                                              0x1d3d
-+#define mmDMIF_PG2_DPG_HW_DEBUG_11                                              0x1f3d
-+#define mmDMIF_PG3_DPG_HW_DEBUG_11                                              0x413d
-+#define mmDMIF_PG4_DPG_HW_DEBUG_11                                              0x433d
-+#define mmDMIF_PG5_DPG_HW_DEBUG_11                                              0x453d
-+#define mmDPG_CHK_PRE_PROC_CNTL                                                 0x1b3e
-+#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL                                        0x1b3e
-+#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL                                        0x1d3e
-+#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL                                        0x1f3e
-+#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL                                        0x413e
-+#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL                                        0x433e
-+#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL                                        0x453e
-+#define mmDPG_DVMM_STATUS                                                       0x1b3f
-+#define mmDMIF_PG0_DPG_DVMM_STATUS                                              0x1b3f
-+#define mmDMIF_PG1_DPG_DVMM_STATUS                                              0x1d3f
-+#define mmDMIF_PG2_DPG_DVMM_STATUS                                              0x1f3f
-+#define mmDMIF_PG3_DPG_DVMM_STATUS                                              0x413f
-+#define mmDMIF_PG4_DPG_DVMM_STATUS                                              0x433f
-+#define mmDMIF_PG5_DPG_DVMM_STATUS                                              0x453f
-+#define mmDPG_TEST_DEBUG_INDEX                                                  0x1b38
-+#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX                                         0x1b38
-+#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX                                         0x1d38
-+#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX                                         0x1f38
-+#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                                         0x4138
-+#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                                         0x4338
-+#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                                         0x4538
-+#define mmDPG_TEST_DEBUG_DATA                                                   0x1b39
-+#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA                                          0x1b39
-+#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA                                          0x1d39
-+#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA                                          0x1f39
-+#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA                                          0x4139
-+#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA                                          0x4339
-+#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA                                          0x4539
-+#define mmDPGV0_PIPE_ARBITRATION_CONTROL1                                       0x4730
-+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1                             0x4730
-+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1                             0x9930
-+#define mmDPGV1_PIPE_ARBITRATION_CONTROL1                                       0x473d
-+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1                             0x473d
-+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1                             0x993d
-+#define mmDPGV0_PIPE_ARBITRATION_CONTROL2                                       0x4731
-+#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2                             0x4731
-+#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2                             0x9931
-+#define mmDPGV1_PIPE_ARBITRATION_CONTROL2                                       0x473e
-+#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2                             0x473e
-+#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2                             0x993e
-+#define mmDPGV0_WATERMARK_MASK_CONTROL                                          0x4732
-+#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL                                0x4732
-+#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL                                0x9932
-+#define mmDPGV1_WATERMARK_MASK_CONTROL                                          0x473f
-+#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL                                0x473f
-+#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL                                0x993f
-+#define mmDPGV0_PIPE_URGENCY_CONTROL                                            0x4733
-+#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL                                  0x4733
-+#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL                                  0x9933
-+#define mmDPGV1_PIPE_URGENCY_CONTROL                                            0x4740
-+#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL                                  0x4740
-+#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL                                  0x9940
-+#define mmDPGV0_PIPE_DPM_CONTROL                                                0x4734
-+#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL                                      0x4734
-+#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL                                      0x9934
-+#define mmDPGV1_PIPE_DPM_CONTROL                                                0x4741
-+#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL                                      0x4741
-+#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL                                      0x9941
-+#define mmDPGV0_PIPE_STUTTER_CONTROL                                            0x4735
-+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL                                  0x4735
-+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL                                  0x9935
-+#define mmDPGV1_PIPE_STUTTER_CONTROL                                            0x4742
-+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL                                  0x4742
-+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL                                  0x9942
-+#define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                                   0x4736
-+#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x4736
-+#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x9936
-+#define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                                   0x4743
-+#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x4743
-+#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x9943
-+#define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                                   0x4737
-+#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                         0x4737
-+#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                         0x9937
-+#define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                                   0x4744
-+#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                         0x4744
-+#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                         0x9944
-+#define mmDPGV0_REPEATER_PROGRAM                                                0x4738
-+#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM                                      0x4738
-+#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM                                      0x9938
-+#define mmDPGV1_REPEATER_PROGRAM                                                0x4745
-+#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM                                      0x4745
-+#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM                                      0x9945
-+#define mmDPGV0_HW_DEBUG_A                                                      0x4739
-+#define mmDMIFV_PG0_DPGV0_HW_DEBUG_A                                            0x4739
-+#define mmDMIFV_PG1_DPGV0_HW_DEBUG_A                                            0x9939
-+#define mmDPGV1_HW_DEBUG_A                                                      0x4746
-+#define mmDMIFV_PG0_DPGV1_HW_DEBUG_A                                            0x4746
-+#define mmDMIFV_PG1_DPGV1_HW_DEBUG_A                                            0x9946
-+#define mmDPGV0_HW_DEBUG_B                                                      0x473a
-+#define mmDMIFV_PG0_DPGV0_HW_DEBUG_B                                            0x473a
-+#define mmDMIFV_PG1_DPGV0_HW_DEBUG_B                                            0x993a
-+#define mmDPGV1_HW_DEBUG_B                                                      0x4747
-+#define mmDMIFV_PG0_DPGV1_HW_DEBUG_B                                            0x4747
-+#define mmDMIFV_PG1_DPGV1_HW_DEBUG_B                                            0x9947
-+#define mmDPGV0_HW_DEBUG_11                                                     0x473b
-+#define mmDMIFV_PG0_DPGV0_HW_DEBUG_11                                           0x473b
-+#define mmDMIFV_PG1_DPGV0_HW_DEBUG_11                                           0x993b
-+#define mmDPGV1_HW_DEBUG_11                                                     0x4748
-+#define mmDMIFV_PG0_DPGV1_HW_DEBUG_11                                           0x4748
-+#define mmDMIFV_PG1_DPGV1_HW_DEBUG_11                                           0x9948
-+#define mmDPGV0_CHK_PRE_PROC_CNTL                                               0x473c
-+#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL                                     0x473c
-+#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL                                     0x993c
-+#define mmDPGV1_CHK_PRE_PROC_CNTL                                               0x4749
-+#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL                                     0x4749
-+#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL                                     0x9949
-+#define mmDPGV_TEST_DEBUG_INDEX                                                 0x474e
-+#define mmDMIFV_PG0_DPGV_TEST_DEBUG_INDEX                                       0x474e
-+#define mmDMIFV_PG1_DPGV_TEST_DEBUG_INDEX                                       0x994e
-+#define mmDPGV_TEST_DEBUG_DATA                                                  0x474f
-+#define mmDMIFV_PG0_DPGV_TEST_DEBUG_DATA                                        0x474f
-+#define mmDMIFV_PG1_DPGV_TEST_DEBUG_DATA                                        0x994f
-+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                       0x18
-+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                        0x18
-+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0xf00
-+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                            0xf02
-+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                 0xf04
-+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT             0x1f04
-+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x1f05
-+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x1f0a
-+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x1f0b
-+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x1f0f
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1705
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                0x17ff
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1720
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2              0x1721
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3              0x1722
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4              0x1723
-+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1770
-+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0x1828
-+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                            0x1829
-+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
-+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                   0x182b
-+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x182c
-+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x182d
-+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x182e
-+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x182f
-+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1830
-+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                0x1831
-+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1832
-+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1833
-+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                     0x1834
-+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                               0x1835
-+#define mmAZALIA_F0_CODEC_DEBUG                                                 0x1836
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                           0x1837
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                           0x1838
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                           0x1839
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                           0x183a
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                           0x183b
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                           0x183c
-+#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                           0x183d
-+#define mmGLOBAL_CAPABILITIES                                                   0x0
-+#define mmMINOR_VERSION                                                         0x0
-+#define mmMAJOR_VERSION                                                         0x0
-+#define mmOUTPUT_PAYLOAD_CAPABILITY                                             0x1
-+#define mmINPUT_PAYLOAD_CAPABILITY                                              0x1
-+#define mmGLOBAL_CONTROL                                                        0x2
-+#define mmWAKE_ENABLE                                                           0x3
-+#define mmSTATE_CHANGE_STATUS                                                   0x3
-+#define mmGLOBAL_STATUS                                                         0x4
-+#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY                                      0x6
-+#define mmINPUT_STREAM_PAYLOAD_CAPABILITY                                       0x6
-+#define mmINTERRUPT_CONTROL                                                     0x8
-+#define mmINTERRUPT_STATUS                                                      0x9
-+#define mmWALL_CLOCK_COUNTER                                                    0xc
-+#define mmSTREAM_SYNCHRONIZATION                                                0xe
-+#define mmCORB_LOWER_BASE_ADDRESS                                               0x10
-+#define mmCORB_UPPER_BASE_ADDRESS                                               0x11
-+#define mmCORB_WRITE_POINTER                                                    0x12
-+#define mmCORB_READ_POINTER                                                     0x12
-+#define mmCORB_CONTROL                                                          0x13
-+#define mmCORB_STATUS                                                           0x13
-+#define mmCORB_SIZE                                                             0x13
-+#define mmRIRB_LOWER_BASE_ADDRESS                                               0x14
-+#define mmRIRB_UPPER_BASE_ADDRESS                                               0x15
-+#define mmRIRB_WRITE_POINTER                                                    0x16
-+#define mmRESPONSE_INTERRUPT_COUNT                                              0x16
-+#define mmRIRB_CONTROL                                                          0x17
-+#define mmRIRB_STATUS                                                           0x17
-+#define mmRIRB_SIZE                                                             0x17
-+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                    0x18
-+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x18
-+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x18
-+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                    0x19
-+#define mmIMMEDIATE_COMMAND_STATUS                                              0x1a
-+#define mmDMA_POSITION_LOWER_BASE_ADDRESS                                       0x1c
-+#define mmDMA_POSITION_UPPER_BASE_ADDRESS                                       0x1d
-+#define mmWALL_CLOCK_COUNTER_ALIAS                                              0x80c
-+#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                           0x20
-+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER              0x21
-+#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                         0x22
-+#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                             0x23
-+#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                    0x24
-+#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT                                       0x24
-+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS               0x26
-+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS               0x27
-+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS        0x821
-+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                   0x18
-+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                    0x18
-+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x2f09
-+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x2f0a
-+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x2f0b
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2200
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x2706
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x270d
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                 0x270e
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                 0x273e
-+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                              0x2724
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x2770
-+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x2771
-+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x3f09
-+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                            0x3f0c
-+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                  0x3f0e
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY            0x3702
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x3707
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x3708
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x3709
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x371c
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2          0x371d
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3          0x371e
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4          0x371f
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION               0x3770
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                        0x3771
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                             0x3772
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                          0x3776
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                     0x3776
-+#define ixAUDIO_DESCRIPTOR0                                                     0x1
-+#define ixAUDIO_DESCRIPTOR1                                                     0x2
-+#define ixAUDIO_DESCRIPTOR2                                                     0x3
-+#define ixAUDIO_DESCRIPTOR3                                                     0x4
-+#define ixAUDIO_DESCRIPTOR4                                                     0x5
-+#define ixAUDIO_DESCRIPTOR5                                                     0x6
-+#define ixAUDIO_DESCRIPTOR6                                                     0x7
-+#define ixAUDIO_DESCRIPTOR7                                                     0x8
-+#define ixAUDIO_DESCRIPTOR8                                                     0x9
-+#define ixAUDIO_DESCRIPTOR9                                                     0xa
-+#define ixAUDIO_DESCRIPTOR10                                                    0xb
-+#define ixAUDIO_DESCRIPTOR11                                                    0xc
-+#define ixAUDIO_DESCRIPTOR12                                                    0xd
-+#define ixAUDIO_DESCRIPTOR13                                                    0xe
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                     0x3777
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                     0x3778
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                     0x3779
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                     0x377a
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                   0x377b
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                     0x3780
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                      0x3781
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                           0x0
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                0x1
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                      0x2
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                   0x3
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                   0x4
-+#define ixSINK_DESCRIPTION0                                                     0x5
-+#define ixSINK_DESCRIPTION1                                                     0x6
-+#define ixSINK_DESCRIPTION2                                                     0x7
-+#define ixSINK_DESCRIPTION3                                                     0x8
-+#define ixSINK_DESCRIPTION4                                                     0x9
-+#define ixSINK_DESCRIPTION5                                                     0xa
-+#define ixSINK_DESCRIPTION6                                                     0xb
-+#define ixSINK_DESCRIPTION7                                                     0xc
-+#define ixSINK_DESCRIPTION8                                                     0xd
-+#define ixSINK_DESCRIPTION9                                                     0xe
-+#define ixSINK_DESCRIPTION10                                                    0xf
-+#define ixSINK_DESCRIPTION11                                                    0x10
-+#define ixSINK_DESCRIPTION12                                                    0x11
-+#define ixSINK_DESCRIPTION13                                                    0x12
-+#define ixSINK_DESCRIPTION14                                                    0x13
-+#define ixSINK_DESCRIPTION15                                                    0x14
-+#define ixSINK_DESCRIPTION16                                                    0x15
-+#define ixSINK_DESCRIPTION17                                                    0x16
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                      0x3785
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                      0x3786
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                      0x3787
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                      0x3788
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x3789
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x378a
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x378b
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x378c
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x378d
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x378e
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x378f
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x3790
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x3791
-+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x3792
-+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                  0x3793
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x3797
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x3798
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                      0x3799
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x379a
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                               0x379b
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x379c
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x379d
-+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x379e
-+#define mmAZALIA_CONTROLLER_CLOCK_GATING                                        0x17e4
-+#define mmAZALIA_AUDIO_DTO                                                      0x17e5
-+#define mmAZALIA_AUDIO_DTO_CONTROL                                              0x17e6
-+#define mmAZALIA_SCLK_CONTROL                                                   0x17e7
-+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                        0x17e8
-+#define mmAZALIA_DATA_DMA_CONTROL                                               0x17e9
-+#define mmAZALIA_BDL_DMA_CONTROL                                                0x17ea
-+#define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
-+#define mmAZALIA_CORB_DMA_CONTROL                                               0x17ec
-+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                          0x17f3
-+#define mmAZALIA_CYCLIC_BUFFER_SYNC                                             0x17f4
-+#define mmAZALIA_GLOBAL_CAPABILITIES                                            0x17f5
-+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                      0x17f6
-+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                  0x17f7
-+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                       0x17f8
-+#define mmAZALIA_CONTROLLER_DEBUG                                               0x17f9
-+#define mmAZALIA_MEM_PWR_CTRL                                                   0x1810
-+#define mmAZALIA_MEM_PWR_STATUS                                                 0x1811
-+#define mmDCI_PG_DEBUG_CONFIG                                                   0x1812
-+#define mmAZALIA_INPUT_CRC0_CONTROL0                                            0x17fb
-+#define mmAZALIA_INPUT_CRC0_CONTROL1                                            0x17fc
-+#define mmAZALIA_INPUT_CRC0_CONTROL2                                            0x17fd
-+#define mmAZALIA_INPUT_CRC0_CONTROL3                                            0x17fe
-+#define mmAZALIA_INPUT_CRC0_RESULT                                              0x17ff
-+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                            0x0
-+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                            0x1
-+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                            0x2
-+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                            0x3
-+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                            0x4
-+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                            0x5
-+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                            0x6
-+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                            0x7
-+#define mmAZALIA_INPUT_CRC1_CONTROL0                                            0x1800
-+#define mmAZALIA_INPUT_CRC1_CONTROL1                                            0x1801
-+#define mmAZALIA_INPUT_CRC1_CONTROL2                                            0x1802
-+#define mmAZALIA_INPUT_CRC1_CONTROL3                                            0x1803
-+#define mmAZALIA_INPUT_CRC1_RESULT                                              0x1804
-+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                            0x0
-+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                            0x1
-+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                            0x2
-+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                            0x3
-+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                            0x4
-+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                            0x5
-+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                            0x6
-+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                            0x7
-+#define mmAZALIA_CRC0_CONTROL0                                                  0x1805
-+#define mmAZALIA_CRC0_CONTROL1                                                  0x1806
-+#define mmAZALIA_CRC0_CONTROL2                                                  0x1807
-+#define mmAZALIA_CRC0_CONTROL3                                                  0x1808
-+#define mmAZALIA_CRC0_RESULT                                                    0x1809
-+#define ixAZALIA_CRC0_CHANNEL0                                                  0x0
-+#define ixAZALIA_CRC0_CHANNEL1                                                  0x1
-+#define ixAZALIA_CRC0_CHANNEL2                                                  0x2
-+#define ixAZALIA_CRC0_CHANNEL3                                                  0x3
-+#define ixAZALIA_CRC0_CHANNEL4                                                  0x4
-+#define ixAZALIA_CRC0_CHANNEL5                                                  0x5
-+#define ixAZALIA_CRC0_CHANNEL6                                                  0x6
-+#define ixAZALIA_CRC0_CHANNEL7                                                  0x7
-+#define mmAZALIA_CRC1_CONTROL0                                                  0x180a
-+#define mmAZALIA_CRC1_CONTROL1                                                  0x180b
-+#define mmAZALIA_CRC1_CONTROL2                                                  0x180c
-+#define mmAZALIA_CRC1_CONTROL3                                                  0x180d
-+#define mmAZALIA_CRC1_RESULT                                                    0x180e
-+#define ixAZALIA_CRC1_CHANNEL0                                                  0x0
-+#define ixAZALIA_CRC1_CHANNEL1                                                  0x1
-+#define ixAZALIA_CRC1_CHANNEL2                                                  0x2
-+#define ixAZALIA_CRC1_CHANNEL3                                                  0x3
-+#define ixAZALIA_CRC1_CHANNEL4                                                  0x4
-+#define ixAZALIA_CRC1_CHANNEL5                                                  0x5
-+#define ixAZALIA_CRC1_CHANNEL6                                                  0x6
-+#define ixAZALIA_CRC1_CHANNEL7                                                  0x7
-+#define mmAZ_TEST_DEBUG_INDEX                                                   0x181f
-+#define mmAZ_TEST_DEBUG_DATA                                                    0x1820
-+#define mmAZALIA_STREAM_INDEX                                                   0x1780
-+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                       0x1780
-+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                       0x1782
-+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                       0x1784
-+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                       0x1786
-+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                       0x1788
-+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                       0x178a
-+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                       0x178c
-+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                       0x178e
-+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                       0x59c0
-+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                       0x59c2
-+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                      0x59c4
-+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                      0x59c6
-+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                      0x59c8
-+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                      0x59ca
-+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                      0x59cc
-+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                      0x59ce
-+#define mmAZALIA_STREAM_DATA                                                    0x1781
-+#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                        0x1781
-+#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                        0x1783
-+#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                        0x1785
-+#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                        0x1787
-+#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                        0x1789
-+#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                        0x178b
-+#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                        0x178d
-+#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                        0x178f
-+#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                        0x59c1
-+#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                        0x59c3
-+#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                       0x59c5
-+#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                       0x59c7
-+#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                       0x59c9
-+#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                       0x59cb
-+#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                       0x59cd
-+#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                       0x59cf
-+#define ixAZALIA_FIFO_SIZE_CONTROL                                              0x0
-+#define ixAZALIA_LATENCY_COUNTER_CONTROL                                        0x1
-+#define ixAZALIA_WORSTCASE_LATENCY_COUNT                                        0x2
-+#define ixAZALIA_CUMULATIVE_LATENCY_COUNT                                       0x3
-+#define ixAZALIA_CUMULATIVE_REQUEST_COUNT                                       0x4
-+#define ixAZALIA_STREAM_DEBUG                                                   0x5
-+#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX                                        0x17a8
-+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17a8
-+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17ac
-+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b0
-+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b4
-+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b8
-+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17bc
-+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c0
-+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c4
-+#define mmAZALIA_F0_CODEC_ENDPOINT_DATA                                         0x17a9
-+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17a9
-+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17ad
-+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b1
-+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b5
-+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b9
-+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17bd
-+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c1
-+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c5
-+#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG                                   0x0
-+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x1
-+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2
-+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x3
-+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x4
-+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x5
-+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x6
-+#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                              0x7
-+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x8
-+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x9
-+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG                    0xa
-+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                           0xc
-+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                       0xd
-+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                       0xe
-+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x20
-+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                            0x21
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x22
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                         0x2b
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                         0x2c
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                         0x2d
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                         0x2e
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                         0x2f
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                         0x30
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                         0x31
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                        0x32
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                        0x33
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                        0x34
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                        0x35
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                       0x36
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                      0x57
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x58
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                          0x37
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                              0x38
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                0x3a
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                0x3b
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                0x3c
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                0x3d
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                0x3e
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                0x3f
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                0x40
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                0x41
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                0x42
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                          0x54
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                0x55
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x56
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x59
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x5a
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x5b
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x5c
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x5d
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x5e
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x5f
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x60
-+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x61
-+#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                  0x62
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x63
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x64
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB                                      0x65
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x66
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                               0x67
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x68
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x69
-+#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x6a
-+#define ixAZALIA_F0_AUDIO_ENABLE_STATUS                                         0x6b
-+#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS                                    0x6c
-+#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS                                   0x6d
-+#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                             0x6e
-+#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                  0x59d4
-+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d4
-+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d8
-+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59dc
-+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e0
-+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e4
-+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e8
-+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59ec
-+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59f0
-+#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                   0x59d5
-+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d5
-+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d9
-+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59dd
-+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e1
-+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e5
-+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e9
-+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59ed
-+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59f1
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG                             0x0
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x1
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x2
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x3
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x4
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x5
-+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x20
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x21
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x22
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE            0x23
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x24
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                 0x36
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                0x37
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                        0x38
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x53
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                    0x54
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE          0x55
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x56
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x67
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x68
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x64
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                0x65
-+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x66
-+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                    0x18
-+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                     0x18
-+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x6f09
-+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6f0a
-+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x6f0b
-+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x6200
-+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x6706
-+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x670d
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x7f09
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x7f0c
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x7707
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x7708
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                  0x7709
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x771c
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2    0x771d
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3    0x771e
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4    0x771f
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                0x7777
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                0x7785
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                0x7778
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                0x7786
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                 0x777c
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                0x7779
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                0x7787
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                0x777a
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                0x7788
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x7771
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x779b
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x779c
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                    0x779d
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                    0x779e
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x7798
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                0x7799
-+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x779a
-+#define mmBLND_CONTROL                                                          0x1b6d
-+#define mmBLND0_BLND_CONTROL                                                    0x1b6d
-+#define mmBLND1_BLND_CONTROL                                                    0x1d6d
-+#define mmBLND2_BLND_CONTROL                                                    0x1f6d
-+#define mmBLND3_BLND_CONTROL                                                    0x416d
-+#define mmBLND4_BLND_CONTROL                                                    0x436d
-+#define mmBLND5_BLND_CONTROL                                                    0x456d
-+#define mmBLND_SM_CONTROL2                                                      0x1b6e
-+#define mmBLND0_BLND_SM_CONTROL2                                                0x1b6e
-+#define mmBLND1_BLND_SM_CONTROL2                                                0x1d6e
-+#define mmBLND2_BLND_SM_CONTROL2                                                0x1f6e
-+#define mmBLND3_BLND_SM_CONTROL2                                                0x416e
-+#define mmBLND4_BLND_SM_CONTROL2                                                0x436e
-+#define mmBLND5_BLND_SM_CONTROL2                                                0x456e
-+#define mmBLND_CONTROL2                                                         0x1b6f
-+#define mmBLND0_BLND_CONTROL2                                                   0x1b6f
-+#define mmBLND1_BLND_CONTROL2                                                   0x1d6f
-+#define mmBLND2_BLND_CONTROL2                                                   0x1f6f
-+#define mmBLND3_BLND_CONTROL2                                                   0x416f
-+#define mmBLND4_BLND_CONTROL2                                                   0x436f
-+#define mmBLND5_BLND_CONTROL2                                                   0x456f
-+#define mmBLND_UPDATE                                                           0x1b70
-+#define mmBLND0_BLND_UPDATE                                                     0x1b70
-+#define mmBLND1_BLND_UPDATE                                                     0x1d70
-+#define mmBLND2_BLND_UPDATE                                                     0x1f70
-+#define mmBLND3_BLND_UPDATE                                                     0x4170
-+#define mmBLND4_BLND_UPDATE                                                     0x4370
-+#define mmBLND5_BLND_UPDATE                                                     0x4570
-+#define mmBLND_UNDERFLOW_INTERRUPT                                              0x1b71
-+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT                                        0x1b71
-+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT                                        0x1d71
-+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT                                        0x1f71
-+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT                                        0x4171
-+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT                                        0x4371
-+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT                                        0x4571
-+#define mmBLND_V_UPDATE_LOCK                                                    0x1b73
-+#define mmBLND0_BLND_V_UPDATE_LOCK                                              0x1b73
-+#define mmBLND1_BLND_V_UPDATE_LOCK                                              0x1d73
-+#define mmBLND2_BLND_V_UPDATE_LOCK                                              0x1f73
-+#define mmBLND3_BLND_V_UPDATE_LOCK                                              0x4173
-+#define mmBLND4_BLND_V_UPDATE_LOCK                                              0x4373
-+#define mmBLND5_BLND_V_UPDATE_LOCK                                              0x4573
-+#define mmBLND_REG_UPDATE_STATUS                                                0x1b77
-+#define mmBLND0_BLND_REG_UPDATE_STATUS                                          0x1b77
-+#define mmBLND1_BLND_REG_UPDATE_STATUS                                          0x1d77
-+#define mmBLND2_BLND_REG_UPDATE_STATUS                                          0x1f77
-+#define mmBLND3_BLND_REG_UPDATE_STATUS                                          0x4177
-+#define mmBLND4_BLND_REG_UPDATE_STATUS                                          0x4377
-+#define mmBLND5_BLND_REG_UPDATE_STATUS                                          0x4577
-+#define mmBLND_DEBUG                                                            0x1b74
-+#define mmBLND0_BLND_DEBUG                                                      0x1b74
-+#define mmBLND1_BLND_DEBUG                                                      0x1d74
-+#define mmBLND2_BLND_DEBUG                                                      0x1f74
-+#define mmBLND3_BLND_DEBUG                                                      0x4174
-+#define mmBLND4_BLND_DEBUG                                                      0x4374
-+#define mmBLND5_BLND_DEBUG                                                      0x4574
-+#define mmBLND_TEST_DEBUG_INDEX                                                 0x1b75
-+#define mmBLND0_BLND_TEST_DEBUG_INDEX                                           0x1b75
-+#define mmBLND1_BLND_TEST_DEBUG_INDEX                                           0x1d75
-+#define mmBLND2_BLND_TEST_DEBUG_INDEX                                           0x1f75
-+#define mmBLND3_BLND_TEST_DEBUG_INDEX                                           0x4175
-+#define mmBLND4_BLND_TEST_DEBUG_INDEX                                           0x4375
-+#define mmBLND5_BLND_TEST_DEBUG_INDEX                                           0x4575
-+#define mmBLND_TEST_DEBUG_DATA                                                  0x1b76
-+#define mmBLND0_BLND_TEST_DEBUG_DATA                                            0x1b76
-+#define mmBLND1_BLND_TEST_DEBUG_DATA                                            0x1d76
-+#define mmBLND2_BLND_TEST_DEBUG_DATA                                            0x1f76
-+#define mmBLND3_BLND_TEST_DEBUG_DATA                                            0x4176
-+#define mmBLND4_BLND_TEST_DEBUG_DATA                                            0x4376
-+#define mmBLND5_BLND_TEST_DEBUG_DATA                                            0x4576
-+#define mmWB_ENABLE                                                             0x5e18
-+#define mmWB_EC_CONFIG                                                          0x5e19
-+#define mmCNV_MODE                                                              0x5e1a
-+#define mmCNV_WINDOW_START                                                      0x5e1b
-+#define mmCNV_WINDOW_SIZE                                                       0x5e1c
-+#define mmCNV_UPDATE                                                            0x5e1d
-+#define mmCNV_SOURCE_SIZE                                                       0x5e1e
-+#define mmCNV_CSC_CONTROL                                                       0x5e1f
-+#define mmCNV_CSC_C11_C12                                                       0x5e20
-+#define mmCNV_CSC_C13_C14                                                       0x5e21
-+#define mmCNV_CSC_C21_C22                                                       0x5e22
-+#define mmCNV_CSC_C23_C24                                                       0x5e23
-+#define mmCNV_CSC_C31_C32                                                       0x5e24
-+#define mmCNV_CSC_C33_C34                                                       0x5e25
-+#define mmCNV_CSC_ROUND_OFFSET_R                                                0x5e26
-+#define mmCNV_CSC_ROUND_OFFSET_G                                                0x5e27
-+#define mmCNV_CSC_ROUND_OFFSET_B                                                0x5e28
-+#define mmCNV_CSC_CLAMP_R                                                       0x5e29
-+#define mmCNV_CSC_CLAMP_G                                                       0x5e2a
-+#define mmCNV_CSC_CLAMP_B                                                       0x5e2b
-+#define mmCNV_TEST_CNTL                                                         0x5e2c
-+#define mmCNV_TEST_CRC_RED                                                      0x5e2d
-+#define mmCNV_TEST_CRC_GREEN                                                    0x5e2e
-+#define mmCNV_TEST_CRC_BLUE                                                     0x5e2f
-+#define mmWB_DEBUG_CTRL                                                         0x5e30
-+#define mmWB_DBG_MODE                                                           0x5e31
-+#define mmWB_HW_DEBUG                                                           0x5e32
-+#define mmCNV_INPUT_SELECT                                                      0x5e33
-+#define mmWB_SOFT_RESET                                                         0x5e36
-+#define mmWB_WARM_UP_MODE_CTL1                                                  0x5e37
-+#define mmWB_WARM_UP_MODE_CTL2                                                  0x5e38
-+#define mmCNV_TEST_DEBUG_INDEX                                                  0x5e34
-+#define mmCNV_TEST_DEBUG_DATA                                                   0x5e35
-+#define mmDCFE_CLOCK_CONTROL                                                    0x1b00
-+#define mmDCFE0_DCFE_CLOCK_CONTROL                                              0x1b00
-+#define mmDCFE1_DCFE_CLOCK_CONTROL                                              0x1d00
-+#define mmDCFE2_DCFE_CLOCK_CONTROL                                              0x1f00
-+#define mmDCFE3_DCFE_CLOCK_CONTROL                                              0x4100
-+#define mmDCFE4_DCFE_CLOCK_CONTROL                                              0x4300
-+#define mmDCFE5_DCFE_CLOCK_CONTROL                                              0x4500
-+#define mmDCFE_SOFT_RESET                                                       0x1b01
-+#define mmDCFE0_DCFE_SOFT_RESET                                                 0x1b01
-+#define mmDCFE1_DCFE_SOFT_RESET                                                 0x1d01
-+#define mmDCFE2_DCFE_SOFT_RESET                                                 0x1f01
-+#define mmDCFE3_DCFE_SOFT_RESET                                                 0x4101
-+#define mmDCFE4_DCFE_SOFT_RESET                                                 0x4301
-+#define mmDCFE5_DCFE_SOFT_RESET                                                 0x4501
-+#define mmDCFE_DBG_CONFIG                                                       0x1b02
-+#define mmDCFE0_DCFE_DBG_CONFIG                                                 0x1b02
-+#define mmDCFE1_DCFE_DBG_CONFIG                                                 0x1d02
-+#define mmDCFE2_DCFE_DBG_CONFIG                                                 0x1f02
-+#define mmDCFE3_DCFE_DBG_CONFIG                                                 0x4102
-+#define mmDCFE4_DCFE_DBG_CONFIG                                                 0x4302
-+#define mmDCFE5_DCFE_DBG_CONFIG                                                 0x4502
-+#define mmDCFE_MEM_PWR_CTRL                                                     0x1b03
-+#define mmDCFE0_DCFE_MEM_PWR_CTRL                                               0x1b03
-+#define mmDCFE1_DCFE_MEM_PWR_CTRL                                               0x1d03
-+#define mmDCFE2_DCFE_MEM_PWR_CTRL                                               0x1f03
-+#define mmDCFE3_DCFE_MEM_PWR_CTRL                                               0x4103
-+#define mmDCFE4_DCFE_MEM_PWR_CTRL                                               0x4303
-+#define mmDCFE5_DCFE_MEM_PWR_CTRL                                               0x4503
-+#define mmDCFE_MEM_PWR_CTRL2                                                    0x1b04
-+#define mmDCFE0_DCFE_MEM_PWR_CTRL2                                              0x1b04
-+#define mmDCFE1_DCFE_MEM_PWR_CTRL2                                              0x1d04
-+#define mmDCFE2_DCFE_MEM_PWR_CTRL2                                              0x1f04
-+#define mmDCFE3_DCFE_MEM_PWR_CTRL2                                              0x4104
-+#define mmDCFE4_DCFE_MEM_PWR_CTRL2                                              0x4304
-+#define mmDCFE5_DCFE_MEM_PWR_CTRL2                                              0x4504
-+#define mmDCFE_MEM_PWR_STATUS                                                   0x1b05
-+#define mmDCFE0_DCFE_MEM_PWR_STATUS                                             0x1b05
-+#define mmDCFE1_DCFE_MEM_PWR_STATUS                                             0x1d05
-+#define mmDCFE2_DCFE_MEM_PWR_STATUS                                             0x1f05
-+#define mmDCFE3_DCFE_MEM_PWR_STATUS                                             0x4105
-+#define mmDCFE4_DCFE_MEM_PWR_STATUS                                             0x4305
-+#define mmDCFE5_DCFE_MEM_PWR_STATUS                                             0x4505
-+#define mmDCFE_MISC                                                             0x1b06
-+#define mmDCFE0_DCFE_MISC                                                       0x1b06
-+#define mmDCFE1_DCFE_MISC                                                       0x1d06
-+#define mmDCFE2_DCFE_MISC                                                       0x1f06
-+#define mmDCFE3_DCFE_MISC                                                       0x4106
-+#define mmDCFE4_DCFE_MISC                                                       0x4306
-+#define mmDCFE5_DCFE_MISC                                                       0x4506
-+#define mmDCFE_FLUSH                                                            0x1b07
-+#define mmDCFE0_DCFE_FLUSH                                                      0x1b07
-+#define mmDCFE1_DCFE_FLUSH                                                      0x1d07
-+#define mmDCFE2_DCFE_FLUSH                                                      0x1f07
-+#define mmDCFE3_DCFE_FLUSH                                                      0x4107
-+#define mmDCFE4_DCFE_FLUSH                                                      0x4307
-+#define mmDCFE5_DCFE_FLUSH                                                      0x4507
-+#define mmDCFEV_CLOCK_CONTROL                                                   0x46f4
-+#define mmDCFEV0_DCFEV_CLOCK_CONTROL                                            0x46f4
-+#define mmDCFEV1_DCFEV_CLOCK_CONTROL                                            0x98f4
-+#define mmDCFEV_SOFT_RESET                                                      0x46f5
-+#define mmDCFEV0_DCFEV_SOFT_RESET                                               0x46f5
-+#define mmDCFEV1_DCFEV_SOFT_RESET                                               0x98f5
-+#define mmDCFEV_DMIFV_CLOCK_CONTROL                                             0x46f6
-+#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL                                      0x46f6
-+#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL                                      0x98f6
-+#define mmDCFEV_DBG_CONFIG                                                      0x46f7
-+#define mmDCFEV0_DCFEV_DBG_CONFIG                                               0x46f7
-+#define mmDCFEV1_DCFEV_DBG_CONFIG                                               0x98f7
-+#define mmDCFEV_DMIFV_MEM_PWR_CTRL                                              0x46f8
-+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL                                       0x46f8
-+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL                                       0x98f8
-+#define mmDCFEV_DMIFV_MEM_PWR_STATUS                                            0x46f9
-+#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS                                     0x46f9
-+#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS                                     0x98f9
-+#define mmDCFEV_MEM_PWR_CTRL                                                    0x46fa
-+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL                                             0x46fa
-+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL                                             0x98fa
-+#define mmDCFEV_MEM_PWR_CTRL2                                                   0x46fb
-+#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2                                            0x46fb
-+#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2                                            0x98fb
-+#define mmDCFEV_MEM_PWR_STATUS                                                  0x46fc
-+#define mmDCFEV0_DCFEV_MEM_PWR_STATUS                                           0x46fc
-+#define mmDCFEV1_DCFEV_MEM_PWR_STATUS                                           0x98fc
-+#define mmDCFEV_L_FLUSH                                                         0x46ff
-+#define mmDCFEV0_DCFEV_L_FLUSH                                                  0x46ff
-+#define mmDCFEV1_DCFEV_L_FLUSH                                                  0x98ff
-+#define mmDCFEV_C_FLUSH                                                         0x4700
-+#define mmDCFEV0_DCFEV_C_FLUSH                                                  0x4700
-+#define mmDCFEV1_DCFEV_C_FLUSH                                                  0x9900
-+#define mmDCFEV_DMIFV_DEBUG                                                     0x46fd
-+#define mmDCFEV0_DCFEV_DMIFV_DEBUG                                              0x46fd
-+#define mmDCFEV1_DCFEV_DMIFV_DEBUG                                              0x98fd
-+#define mmDCFEV_MISC                                                            0x46fe
-+#define mmDCFEV0_DCFEV_MISC                                                     0x46fe
-+#define mmDCFEV1_DCFEV_MISC                                                     0x98fe
-+#define mmDC_HPD_INT_STATUS                                                     0x1898
-+#define mmHPD0_DC_HPD_INT_STATUS                                                0x1898
-+#define mmHPD1_DC_HPD_INT_STATUS                                                0x18a0
-+#define mmHPD2_DC_HPD_INT_STATUS                                                0x18a8
-+#define mmHPD3_DC_HPD_INT_STATUS                                                0x18b0
-+#define mmHPD4_DC_HPD_INT_STATUS                                                0x18b8
-+#define mmHPD5_DC_HPD_INT_STATUS                                                0x18c0
-+#define mmDC_HPD_INT_CONTROL                                                    0x1899
-+#define mmHPD0_DC_HPD_INT_CONTROL                                               0x1899
-+#define mmHPD1_DC_HPD_INT_CONTROL                                               0x18a1
-+#define mmHPD2_DC_HPD_INT_CONTROL                                               0x18a9
-+#define mmHPD3_DC_HPD_INT_CONTROL                                               0x18b1
-+#define mmHPD4_DC_HPD_INT_CONTROL                                               0x18b9
-+#define mmHPD5_DC_HPD_INT_CONTROL                                               0x18c1
-+#define mmDC_HPD_CONTROL                                                        0x189a
-+#define mmHPD0_DC_HPD_CONTROL                                                   0x189a
-+#define mmHPD1_DC_HPD_CONTROL                                                   0x18a2
-+#define mmHPD2_DC_HPD_CONTROL                                                   0x18aa
-+#define mmHPD3_DC_HPD_CONTROL                                                   0x18b2
-+#define mmHPD4_DC_HPD_CONTROL                                                   0x18ba
-+#define mmHPD5_DC_HPD_CONTROL                                                   0x18c2
-+#define mmDC_HPD_FAST_TRAIN_CNTL                                                0x189b
-+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                           0x189b
-+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                           0x18a3
-+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                           0x18ab
-+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                           0x18b3
-+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                           0x18bb
-+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL                                           0x18c3
-+#define mmDC_HPD_TOGGLE_FILT_CNTL                                               0x189c
-+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                          0x189c
-+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                          0x18a4
-+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                          0x18ac
-+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                          0x18b4
-+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                          0x18bc
-+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL                                          0x18c4
-+#define mmDCO_SCRATCH0                                                          0x184e
-+#define mmDCO_SCRATCH1                                                          0x184f
-+#define mmDCO_SCRATCH2                                                          0x1850
-+#define mmDCO_SCRATCH3                                                          0x1851
-+#define mmDCO_SCRATCH4                                                          0x1852
-+#define mmDCO_SCRATCH5                                                          0x1853
-+#define mmDCO_SCRATCH6                                                          0x1854
-+#define mmDCO_SCRATCH7                                                          0x1855
-+#define mmDCE_VCE_CONTROL                                                       0x1856
-+#define mmDISP_INTERRUPT_STATUS                                                 0x1857
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE                                        0x1858
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                       0x1859
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                       0x185a
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                       0x185b
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                       0x185c
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                       0x185d
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                       0x185e
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                       0x185f
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                       0x1860
-+#define mmDISP_INTERRUPT_STATUS_CONTINUE10                                      0x1875
-+#define mmDCO_MEM_PWR_STATUS                                                    0x1861
-+#define mmDCO_MEM_PWR_STATUS1                                                   0x1874
-+#define mmDCO_MEM_PWR_CTRL                                                      0x1862
-+#define mmDCO_MEM_PWR_CTRL2                                                     0x1863
-+#define mmFMT_MEMORY0_CONTROL                                                   0x1888
-+#define mmFMT_MEMORY1_CONTROL                                                   0x1889
-+#define mmFMT_MEMORY2_CONTROL                                                   0x188a
-+#define mmFMT_MEMORY3_CONTROL                                                   0x188b
-+#define mmFMT_MEMORY4_CONTROL                                                   0x188c
-+#define mmFMT_MEMORY5_CONTROL                                                   0x188d
-+#define mmDCO_CLK_CNTL                                                          0x1864
-+#define mmDCO_CLK_CNTL2                                                         0x1876
-+#define mmDCO_CLK_CNTL3                                                         0x1877
-+#define mmDPDBG_CNTL                                                            0x1866
-+#define mmDPDBG_INTERRUPT                                                       0x1867
-+#define mmDCO_POWER_MANAGEMENT_CNTL                                             0x1868
-+#define mmDCO_SOFT_RESET                                                        0x1871
-+#define mmDIG_SOFT_RESET                                                        0x1872
-+#define mmDIG_SOFT_RESET_2                                                      0x186a
-+#define mmDCO_STEREOSYNC_SEL                                                    0x186e
-+#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL                                       0x1883
-+#define mmDCO_PSP_INTERRUPT_STATUS                                              0x1884
-+#define mmDCO_PSP_INTERRUPT_CLEAR                                               0x1885
-+#define mmDCO_GENERIC_INTERRUPT_MESSAGE                                         0x1886
-+#define mmDCO_GENERIC_INTERRUPT_CLEAR                                           0x1887
-+#define mmDCO_TEST_DEBUG_INDEX                                                  0x186f
-+#define mmDCO_TEST_DEBUG_DATA                                                   0x1870
-+#define mmDC_I2C_CONTROL                                                        0x16d4
-+#define mmDC_I2C_ARBITRATION                                                    0x16d5
-+#define mmDC_I2C_INTERRUPT_CONTROL                                              0x16d6
-+#define mmDC_I2C_SW_STATUS                                                      0x16d7
-+#define mmDC_I2C_DDC1_HW_STATUS                                                 0x16d8
-+#define mmDC_I2C_DDC2_HW_STATUS                                                 0x16d9
-+#define mmDC_I2C_DDC3_HW_STATUS                                                 0x16da
-+#define mmDC_I2C_DDC4_HW_STATUS                                                 0x16db
-+#define mmDC_I2C_DDC5_HW_STATUS                                                 0x16dc
-+#define mmDC_I2C_DDC6_HW_STATUS                                                 0x16dd
-+#define mmDC_I2C_DDC1_SPEED                                                     0x16de
-+#define mmDC_I2C_DDC1_SETUP                                                     0x16df
-+#define mmDC_I2C_DDC2_SPEED                                                     0x16e0
-+#define mmDC_I2C_DDC2_SETUP                                                     0x16e1
-+#define mmDC_I2C_DDC3_SPEED                                                     0x16e2
-+#define mmDC_I2C_DDC3_SETUP                                                     0x16e3
-+#define mmDC_I2C_DDC4_SPEED                                                     0x16e4
-+#define mmDC_I2C_DDC4_SETUP                                                     0x16e5
-+#define mmDC_I2C_DDC5_SPEED                                                     0x16e6
-+#define mmDC_I2C_DDC5_SETUP                                                     0x16e7
-+#define mmDC_I2C_DDC6_SPEED                                                     0x16e8
-+#define mmDC_I2C_DDC6_SETUP                                                     0x16e9
-+#define mmDC_I2C_TRANSACTION0                                                   0x16ea
-+#define mmDC_I2C_TRANSACTION1                                                   0x16eb
-+#define mmDC_I2C_TRANSACTION2                                                   0x16ec
-+#define mmDC_I2C_TRANSACTION3                                                   0x16ed
-+#define mmDC_I2C_DATA                                                           0x16ee
-+#define mmDC_I2C_DDCVGA_HW_STATUS                                               0x16ef
-+#define mmDC_I2C_DDCVGA_SPEED                                                   0x16f0
-+#define mmDC_I2C_DDCVGA_SETUP                                                   0x16f1
-+#define mmDC_I2C_EDID_DETECT_CTRL                                               0x16f2
-+#define mmDC_I2C_READ_REQUEST_INTERRUPT                                         0x16f3
-+#define mmGENERIC_I2C_CONTROL                                                   0x16f4
-+#define mmGENERIC_I2C_INTERRUPT_CONTROL                                         0x16f5
-+#define mmGENERIC_I2C_STATUS                                                    0x16f6
-+#define mmGENERIC_I2C_SPEED                                                     0x16f7
-+#define mmGENERIC_I2C_SETUP                                                     0x16f8
-+#define mmGENERIC_I2C_TRANSACTION                                               0x16f9
-+#define mmGENERIC_I2C_DATA                                                      0x16fa
-+#define mmGENERIC_I2C_PIN_SELECTION                                             0x16fb
-+#define mmGENERIC_I2C_PIN_DEBUG                                                 0x16fc
-+#define mmBLNDV_CONTROL                                                         0x476d
-+#define mmBLNDV0_BLNDV_CONTROL                                                  0x476d
-+#define mmBLNDV1_BLNDV_CONTROL                                                  0x996d
-+#define mmBLNDV_SM_CONTROL2                                                     0x476e
-+#define mmBLNDV0_BLNDV_SM_CONTROL2                                              0x476e
-+#define mmBLNDV1_BLNDV_SM_CONTROL2                                              0x996e
-+#define mmBLNDV_CONTROL2                                                        0x476f
-+#define mmBLNDV0_BLNDV_CONTROL2                                                 0x476f
-+#define mmBLNDV1_BLNDV_CONTROL2                                                 0x996f
-+#define mmBLNDV_UPDATE                                                          0x4770
-+#define mmBLNDV0_BLNDV_UPDATE                                                   0x4770
-+#define mmBLNDV1_BLNDV_UPDATE                                                   0x9970
-+#define mmBLNDV_UNDERFLOW_INTERRUPT                                             0x4771
-+#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT                                      0x4771
-+#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT                                      0x9971
-+#define mmBLNDV_V_UPDATE_LOCK                                                   0x4773
-+#define mmBLNDV0_BLNDV_V_UPDATE_LOCK                                            0x4773
-+#define mmBLNDV1_BLNDV_V_UPDATE_LOCK                                            0x9973
-+#define mmBLNDV_REG_UPDATE_STATUS                                               0x4777
-+#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS                                        0x4777
-+#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS                                        0x9977
-+#define mmBLNDV_DEBUG                                                           0x4774
-+#define mmBLNDV0_BLNDV_DEBUG                                                    0x4774
-+#define mmBLNDV1_BLNDV_DEBUG                                                    0x9974
-+#define mmBLNDV_TEST_DEBUG_INDEX                                                0x4775
-+#define mmBLNDV0_BLNDV_TEST_DEBUG_INDEX                                         0x4775
-+#define mmBLNDV1_BLNDV_TEST_DEBUG_INDEX                                         0x9975
-+#define mmBLNDV_TEST_DEBUG_DATA                                                 0x4776
-+#define mmBLNDV0_BLNDV_TEST_DEBUG_DATA                                          0x4776
-+#define mmBLNDV1_BLNDV_TEST_DEBUG_DATA                                          0x9976
-+#define mmCRTCV_H_TOTAL                                                         0x4780
-+#define mmCRTCV0_CRTCV_H_TOTAL                                                  0x4780
-+#define mmCRTCV1_CRTCV_H_TOTAL                                                  0x9980
-+#define mmCRTCV_H_BLANK_START_END                                               0x4781
-+#define mmCRTCV0_CRTCV_H_BLANK_START_END                                        0x4781
-+#define mmCRTCV1_CRTCV_H_BLANK_START_END                                        0x9981
-+#define mmCRTCV_H_SYNC_A                                                        0x4782
-+#define mmCRTCV0_CRTCV_H_SYNC_A                                                 0x4782
-+#define mmCRTCV1_CRTCV_H_SYNC_A                                                 0x9982
-+#define mmCRTCV_V_TOTAL                                                         0x4787
-+#define mmCRTCV0_CRTCV_V_TOTAL                                                  0x4787
-+#define mmCRTCV1_CRTCV_V_TOTAL                                                  0x9987
-+#define mmCRTCV_V_BLANK_START_END                                               0x478d
-+#define mmCRTCV0_CRTCV_V_BLANK_START_END                                        0x478d
-+#define mmCRTCV1_CRTCV_V_BLANK_START_END                                        0x998d
-+#define mmCRTCV_V_SYNC_A                                                        0x478e
-+#define mmCRTCV0_CRTCV_V_SYNC_A                                                 0x478e
-+#define mmCRTCV1_CRTCV_V_SYNC_A                                                 0x998e
-+#define mmCRTCV_CONTROL                                                         0x479c
-+#define mmCRTCV0_CRTCV_CONTROL                                                  0x479c
-+#define mmCRTCV1_CRTCV_CONTROL                                                  0x999c
-+#define mmCRTCV_START_LINE_CONTROL                                              0x47b3
-+#define mmCRTCV0_CRTCV_START_LINE_CONTROL                                       0x47b3
-+#define mmCRTCV1_CRTCV_START_LINE_CONTROL                                       0x99b3
-+#define mmCRTCV_OVERSCAN_COLOR                                                  0x47c8
-+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR                                           0x47c8
-+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR                                           0x99c8
-+#define mmCRTCV_OVERSCAN_COLOR_EXT                                              0x47c9
-+#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT                                       0x47c9
-+#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT                                       0x99c9
-+#define mmCRTCV_BLACK_COLOR                                                     0x47cc
-+#define mmCRTCV0_CRTCV_BLACK_COLOR                                              0x47cc
-+#define mmCRTCV1_CRTCV_BLACK_COLOR                                              0x99cc
-+#define mmCRTCV_BLACK_COLOR_EXT                                                 0x47cd
-+#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT                                          0x47cd
-+#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT                                          0x99cd
-+#define mmCRTCV_CRC_CNTL                                                        0x47d4
-+#define mmCRTCV0_CRTCV_CRC_CNTL                                                 0x47d4
-+#define mmCRTCV1_CRTCV_CRC_CNTL                                                 0x99d4
-+#define mmCRTCV_CRC0_WINDOWA_X_CONTROL                                          0x47d5
-+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL                                   0x47d5
-+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL                                   0x99d5
-+#define mmCRTCV_CRC0_WINDOWA_Y_CONTROL                                          0x47d6
-+#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL                                   0x47d6
-+#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL                                   0x99d6
-+#define mmCRTCV_CRC0_WINDOWB_X_CONTROL                                          0x47d7
-+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL                                   0x47d7
-+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL                                   0x99d7
-+#define mmCRTCV_CRC0_WINDOWB_Y_CONTROL                                          0x47d8
-+#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL                                   0x47d8
-+#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL                                   0x99d8
-+#define mmCRTCV_CRC0_DATA_RG                                                    0x47d9
-+#define mmCRTCV0_CRTCV_CRC0_DATA_RG                                             0x47d9
-+#define mmCRTCV1_CRTCV_CRC0_DATA_RG                                             0x99d9
-+#define mmCRTCV_CRC0_DATA_B                                                     0x47da
-+#define mmCRTCV0_CRTCV_CRC0_DATA_B                                              0x47da
-+#define mmCRTCV1_CRTCV_CRC0_DATA_B                                              0x99da
-+#define mmCRTCV_CRC1_WINDOWA_X_CONTROL                                          0x47db
-+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL                                   0x47db
-+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL                                   0x99db
-+#define mmCRTCV_CRC1_WINDOWA_Y_CONTROL                                          0x47dc
-+#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL                                   0x47dc
-+#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL                                   0x99dc
-+#define mmCRTCV_CRC1_WINDOWB_X_CONTROL                                          0x47dd
-+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL                                   0x47dd
-+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL                                   0x99dd
-+#define mmCRTCV_CRC1_WINDOWB_Y_CONTROL                                          0x47de
-+#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL                                   0x47de
-+#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL                                   0x99de
-+#define mmCRTCV_CRC1_DATA_RG                                                    0x47df
-+#define mmCRTCV0_CRTCV_CRC1_DATA_RG                                             0x47df
-+#define mmCRTCV1_CRTCV_CRC1_DATA_RG                                             0x99df
-+#define mmCRTCV_CRC1_DATA_B                                                     0x47e0
-+#define mmCRTCV0_CRTCV_CRC1_DATA_B                                              0x47e0
-+#define mmCRTCV1_CRTCV_CRC1_DATA_B                                              0x99e0
-+#define mmCRTCV_TEST_DEBUG_INDEX                                                0x47c6
-+#define mmCRTCV0_CRTCV_TEST_DEBUG_INDEX                                         0x47c6
-+#define mmCRTCV1_CRTCV_TEST_DEBUG_INDEX                                         0x99c6
-+#define mmCRTCV_TEST_DEBUG_DATA                                                 0x47c7
-+#define mmCRTCV0_CRTCV_TEST_DEBUG_DATA                                          0x47c7
-+#define mmCRTCV1_CRTCV_TEST_DEBUG_DATA                                          0x99c7
-+#define mmXDMA_MC_PCIE_CLIENT_CONFIG                                            0x3e0
-+#define mmXDMA_LOCAL_SURFACE_TILING1                                            0x3e1
-+#define mmXDMA_LOCAL_SURFACE_TILING2                                            0x3e2
-+#define mmXDMA_INTERRUPT                                                        0x3e3
-+#define mmXDMA_CLOCK_GATING_CNTL                                                0x3e4
-+#define mmXDMA_MEM_POWER_CNTL                                                   0x3e6
-+#define mmXDMA_IF_BIF_STATUS                                                    0x3e7
-+#define mmXDMA_PERF_MEAS_STATUS                                                 0x3e8
-+#define mmXDMA_IF_STATUS                                                        0x3e9
-+#define mmXDMA_TEST_DEBUG_INDEX                                                 0x3ea
-+#define mmXDMA_TEST_DEBUG_DATA                                                  0x3eb
-+#define mmXDMA_RBBMIF_RDWR_CNTL                                                 0x3f8
-+#define mmXDMA_PG_CONTROL                                                       0x3f9
-+#define mmXDMA_PG_WDATA                                                         0x3fa
-+#define mmXDMA_PG_STATUS                                                        0x3fb
-+#define mmXDMA_AON_TEST_DEBUG_INDEX                                             0x3fc
-+#define mmXDMA_AON_TEST_DEBUG_DATA                                              0x3fd
-+#define mmXDMA_MSTR_CNTL                                                        0x3ec
-+#define mmXDMA_MSTR_STATUS                                                      0x3ed
-+#define mmXDMA_MSTR_MEM_CLIENT_CONFIG                                           0x3ee
-+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR                                     0x3ef
-+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH                                0x3f0
-+#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH                                         0x3f1
-+#define mmXDMA_MSTR_CMD_URGENT_CNTL                                             0x3f2
-+#define mmXDMA_MSTR_MEM_URGENT_CNTL                                             0x3f3
-+#define mmXDMA_MSTR_PCIE_NACK_STATUS                                            0x3f5
-+#define mmXDMA_MSTR_MEM_NACK_STATUS                                             0x3f6
-+#define mmXDMA_MSTR_VSYNC_GSL_CHECK                                             0x3f7
-+#define mmXDMA_MSTR_PIPE_CNTL                                                   0x400
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL                                   0x400
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL                                   0x410
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL                                   0x420
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL                                   0x430
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL                                   0x440
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL                                   0x450
-+#define mmXDMA_MSTR_READ_COMMAND                                                0x401
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND                                0x401
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND                                0x411
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND                                0x421
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND                                0x431
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND                                0x441
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND                                0x451
-+#define mmXDMA_MSTR_CHANNEL_DIM                                                 0x402
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM                                 0x402
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM                                 0x412
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM                                 0x422
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM                                 0x432
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM                                 0x442
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM                                 0x452
-+#define mmXDMA_MSTR_HEIGHT                                                      0x403
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT                                      0x403
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT                                      0x413
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT                                      0x423
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT                                      0x433
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT                                      0x443
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT                                      0x453
-+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE                                         0x404
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x404
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x414
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x424
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x434
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x444
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x454
-+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                                    0x405
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x405
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x415
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x425
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x435
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x445
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x455
-+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS                                          0x406
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x406
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x416
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x426
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x436
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x446
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x456
-+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                                     0x407
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x407
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x417
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x427
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x437
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x447
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x457
-+#define mmXDMA_MSTR_CACHE_BASE_ADDR                                             0x408
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR                             0x408
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR                             0x418
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR                             0x428
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR                             0x438
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR                             0x448
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR                             0x458
-+#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH                                        0x409
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x409
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x419
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x429
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x439
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x449
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x459
-+#define mmXDMA_MSTR_CACHE                                                       0x40a
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE                                       0x40a
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE                                       0x41a
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE                                       0x42a
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE                                       0x43a
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE                                       0x44a
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE                                       0x45a
-+#define mmXDMA_MSTR_CHANNEL_START                                               0x40b
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START                               0x40b
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START                               0x41b
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START                               0x42b
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START                               0x43b
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START                               0x44b
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START                               0x45b
-+#define mmXDMA_MSTR_PERFMEAS_STATUS                                             0x40e
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS                             0x40e
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS                             0x41e
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS                             0x42e
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS                             0x43e
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS                             0x44e
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS                             0x45e
-+#define mmXDMA_MSTR_PERFMEAS_CNTL                                               0x40f
-+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL                               0x40f
-+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL                               0x41f
-+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL                               0x42f
-+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL                               0x43f
-+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL                               0x44f
-+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL                               0x45f
-+#define mmXDMA_SLV_CNTL                                                         0x460
-+#define mmXDMA_SLV_MEM_CLIENT_CONFIG                                            0x461
-+#define mmXDMA_SLV_SLS_PITCH                                                    0x462
-+#define mmXDMA_SLV_READ_URGENT_CNTL                                             0x463
-+#define mmXDMA_SLV_WRITE_URGENT_CNTL                                            0x464
-+#define mmXDMA_SLV_WB_RATE_CNTL                                                 0x465
-+#define mmXDMA_SLV_READ_LATENCY_MINMAX                                          0x466
-+#define mmXDMA_SLV_READ_LATENCY_AVE                                             0x467
-+#define mmXDMA_SLV_PCIE_NACK_STATUS                                             0x468
-+#define mmXDMA_SLV_MEM_NACK_STATUS                                              0x469
-+#define mmXDMA_SLV_RDRET_BUF_STATUS                                             0x46a
-+#define mmXDMA_SLV_READ_LATENCY_TIMER                                           0x46b
-+#define mmXDMA_SLV_FLIP_PENDING                                                 0x46c
-+#define mmXDMA_SLV_CHANNEL_CNTL                                                 0x470
-+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL                               0x470
-+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL                               0x478
-+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL                               0x480
-+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL                               0x488
-+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL                               0x490
-+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL                               0x498
-+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS                                           0x471
-+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x471
-+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x479
-+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x481
-+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x489
-+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x491
-+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x499
-+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                                      0x472
-+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x472
-+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x47a
-+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x482
-+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x48a
-+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x492
-+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x49a
-+#define mmCMD_BUS_TX_CONTROL_LANE0                                              0x48e0
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0                           0x48e0
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0                           0x4980
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0                           0x9a20
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0                           0x9ac0
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0                           0x9b60
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0                           0x9c00
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0                           0x9ca0
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE0                           0x9d40
-+#define mmCMD_BUS_TX_CONTROL_LANE1                                              0x48f0
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1                           0x48f0
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1                           0x4990
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1                           0x9a30
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1                           0x9ad0
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1                           0x9b70
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1                           0x9c10
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1                           0x9cb0
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE1                           0x9d50
-+#define mmCMD_BUS_TX_CONTROL_LANE2                                              0x4900
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2                           0x4900
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2                           0x49a0
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2                           0x9a40
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2                           0x9ae0
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2                           0x9b80
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2                           0x9c20
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2                           0x9cc0
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE2                           0x9d60
-+#define mmCMD_BUS_TX_CONTROL_LANE3                                              0x4910
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3                           0x4910
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3                           0x49b0
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3                           0x9a50
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3                           0x9af0
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3                           0x9b90
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3                           0x9c30
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3                           0x9cd0
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE3                           0x9d70
-+#define mmMARGIN_DEEMPH_LANE0                                                   0x48e1
-+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0                                0x48e1
-+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0                                0x4981
-+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0                                0x9a21
-+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0                                0x9ac1
-+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0                                0x9b61
-+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0                                0x9c01
-+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0                                0x9ca1
-+#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE0                                0x9d41
-+#define mmMARGIN_DEEMPH_LANE1                                                   0x48f1
-+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1                                0x48f1
-+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1                                0x4991
-+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1                                0x9a31
-+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1                                0x9ad1
-+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1                                0x9b71
-+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1                                0x9c11
-+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1                                0x9cb1
-+#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE1                                0x9d51
-+#define mmMARGIN_DEEMPH_LANE2                                                   0x4901
-+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2                                0x4901
-+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2                                0x49a1
-+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2                                0x9a41
-+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2                                0x9ae1
-+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2                                0x9b81
-+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2                                0x9c21
-+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2                                0x9cc1
-+#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE2                                0x9d61
-+#define mmMARGIN_DEEMPH_LANE3                                                   0x4911
-+#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3                                0x4911
-+#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3                                0x49b1
-+#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3                                0x9a51
-+#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3                                0x9af1
-+#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3                                0x9b91
-+#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3                                0x9c31
-+#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3                                0x9cd1
-+#define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE3                                0x9d71
-+#define mmCMD_BUS_GLOBAL_FOR_TX_LANE0                                           0x48e2
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x48e2
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x4982
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9a22
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9ac2
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9b62
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9c02
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9ca2
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9d42
-+#define mmCMD_BUS_GLOBAL_FOR_TX_LANE1                                           0x48f2
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x48f2
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x4992
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9a32
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9ad2
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9b72
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9c12
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9cb2
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9d52
-+#define mmCMD_BUS_GLOBAL_FOR_TX_LANE2                                           0x4902
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x4902
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x49a2
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9a42
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9ae2
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9b82
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9c22
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9cc2
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9d62
-+#define mmCMD_BUS_GLOBAL_FOR_TX_LANE3                                           0x4912
-+#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x4912
-+#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x49b2
-+#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9a52
-+#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9af2
-+#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9b92
-+#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9c32
-+#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9cd2
-+#define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9d72
-+#define mmTX_DISP_RFU0_LANE0                                                    0x48e3
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0                                 0x48e3
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0                                 0x4983
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0                                 0x9a23
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0                                 0x9ac3
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0                                 0x9b63
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0                                 0x9c03
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0                                 0x9ca3
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE0                                 0x9d43
-+#define mmTX_DISP_RFU0_LANE1                                                    0x48f3
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1                                 0x48f3
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1                                 0x4993
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1                                 0x9a33
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1                                 0x9ad3
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1                                 0x9b73
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1                                 0x9c13
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1                                 0x9cb3
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE1                                 0x9d53
-+#define mmTX_DISP_RFU0_LANE2                                                    0x4903
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2                                 0x4903
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2                                 0x49a3
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2                                 0x9a43
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2                                 0x9ae3
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2                                 0x9b83
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2                                 0x9c23
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2                                 0x9cc3
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE2                                 0x9d63
-+#define mmTX_DISP_RFU0_LANE3                                                    0x4913
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3                                 0x4913
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3                                 0x49b3
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3                                 0x9a53
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3                                 0x9af3
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3                                 0x9b93
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3                                 0x9c33
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3                                 0x9cd3
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE3                                 0x9d73
-+#define mmTX_DISP_RFU1_LANE0                                                    0x48e4
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0                                 0x48e4
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0                                 0x4984
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0                                 0x9a24
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0                                 0x9ac4
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0                                 0x9b64
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0                                 0x9c04
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0                                 0x9ca4
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE0                                 0x9d44
-+#define mmTX_DISP_RFU1_LANE1                                                    0x48f4
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1                                 0x48f4
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1                                 0x4994
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1                                 0x9a34
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1                                 0x9ad4
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1                                 0x9b74
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1                                 0x9c14
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1                                 0x9cb4
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE1                                 0x9d54
-+#define mmTX_DISP_RFU1_LANE2                                                    0x4904
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2                                 0x4904
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2                                 0x49a4
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2                                 0x9a44
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2                                 0x9ae4
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2                                 0x9b84
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2                                 0x9c24
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2                                 0x9cc4
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE2                                 0x9d64
-+#define mmTX_DISP_RFU1_LANE3                                                    0x4914
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3                                 0x4914
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3                                 0x49b4
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3                                 0x9a54
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3                                 0x9af4
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3                                 0x9b94
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3                                 0x9c34
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3                                 0x9cd4
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE3                                 0x9d74
-+#define mmTX_DISP_RFU2_LANE0                                                    0x48e5
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0                                 0x48e5
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0                                 0x4985
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0                                 0x9a25
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0                                 0x9ac5
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0                                 0x9b65
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0                                 0x9c05
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0                                 0x9ca5
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE0                                 0x9d45
-+#define mmTX_DISP_RFU2_LANE1                                                    0x48f5
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1                                 0x48f5
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1                                 0x4995
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1                                 0x9a35
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1                                 0x9ad5
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1                                 0x9b75
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1                                 0x9c15
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1                                 0x9cb5
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE1                                 0x9d55
-+#define mmTX_DISP_RFU2_LANE2                                                    0x4905
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2                                 0x4905
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2                                 0x49a5
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2                                 0x9a45
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2                                 0x9ae5
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2                                 0x9b85
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2                                 0x9c25
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2                                 0x9cc5
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE2                                 0x9d65
-+#define mmTX_DISP_RFU2_LANE3                                                    0x4915
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3                                 0x4915
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3                                 0x49b5
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3                                 0x9a55
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3                                 0x9af5
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3                                 0x9b95
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3                                 0x9c35
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3                                 0x9cd5
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE3                                 0x9d75
-+#define mmTX_DISP_RFU3_LANE0                                                    0x48e6
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0                                 0x48e6
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0                                 0x4986
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0                                 0x9a26
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0                                 0x9ac6
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0                                 0x9b66
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0                                 0x9c06
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0                                 0x9ca6
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE0                                 0x9d46
-+#define mmTX_DISP_RFU3_LANE1                                                    0x48f6
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1                                 0x48f6
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1                                 0x4996
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1                                 0x9a36
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1                                 0x9ad6
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1                                 0x9b76
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1                                 0x9c16
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1                                 0x9cb6
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE1                                 0x9d56
-+#define mmTX_DISP_RFU3_LANE2                                                    0x4906
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2                                 0x4906
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2                                 0x49a6
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2                                 0x9a46
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2                                 0x9ae6
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2                                 0x9b86
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2                                 0x9c26
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2                                 0x9cc6
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE2                                 0x9d66
-+#define mmTX_DISP_RFU3_LANE3                                                    0x4916
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3                                 0x4916
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3                                 0x49b6
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3                                 0x9a56
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3                                 0x9af6
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3                                 0x9b96
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3                                 0x9c36
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3                                 0x9cd6
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE3                                 0x9d76
-+#define mmTX_DISP_RFU4_LANE0                                                    0x48e7
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0                                 0x48e7
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0                                 0x4987
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0                                 0x9a27
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0                                 0x9ac7
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0                                 0x9b67
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0                                 0x9c07
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0                                 0x9ca7
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE0                                 0x9d47
-+#define mmTX_DISP_RFU4_LANE1                                                    0x48f7
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1                                 0x48f7
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1                                 0x4997
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1                                 0x9a37
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1                                 0x9ad7
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1                                 0x9b77
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1                                 0x9c17
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1                                 0x9cb7
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE1                                 0x9d57
-+#define mmTX_DISP_RFU4_LANE2                                                    0x4907
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2                                 0x4907
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2                                 0x49a7
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2                                 0x9a47
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2                                 0x9ae7
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2                                 0x9b87
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2                                 0x9c27
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2                                 0x9cc7
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE2                                 0x9d67
-+#define mmTX_DISP_RFU4_LANE3                                                    0x4917
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3                                 0x4917
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3                                 0x49b7
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3                                 0x9a57
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3                                 0x9af7
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3                                 0x9b97
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3                                 0x9c37
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3                                 0x9cd7
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE3                                 0x9d77
-+#define mmTX_DISP_RFU5_LANE0                                                    0x48e8
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0                                 0x48e8
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0                                 0x4988
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0                                 0x9a28
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0                                 0x9ac8
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0                                 0x9b68
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0                                 0x9c08
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0                                 0x9ca8
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE0                                 0x9d48
-+#define mmTX_DISP_RFU5_LANE1                                                    0x48f8
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1                                 0x48f8
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1                                 0x4998
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1                                 0x9a38
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1                                 0x9ad8
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1                                 0x9b78
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1                                 0x9c18
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1                                 0x9cb8
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE1                                 0x9d58
-+#define mmTX_DISP_RFU5_LANE2                                                    0x4908
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2                                 0x4908
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2                                 0x49a8
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2                                 0x9a48
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2                                 0x9ae8
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2                                 0x9b88
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2                                 0x9c28
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2                                 0x9cc8
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE2                                 0x9d68
-+#define mmTX_DISP_RFU5_LANE3                                                    0x4918
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3                                 0x4918
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3                                 0x49b8
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3                                 0x9a58
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3                                 0x9af8
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3                                 0x9b98
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3                                 0x9c38
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3                                 0x9cd8
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE3                                 0x9d78
-+#define mmTX_DISP_RFU6_LANE0                                                    0x48e9
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0                                 0x48e9
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0                                 0x4989
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0                                 0x9a29
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0                                 0x9ac9
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0                                 0x9b69
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0                                 0x9c09
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0                                 0x9ca9
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE0                                 0x9d49
-+#define mmTX_DISP_RFU6_LANE1                                                    0x48f9
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1                                 0x48f9
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1                                 0x4999
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1                                 0x9a39
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1                                 0x9ad9
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1                                 0x9b79
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1                                 0x9c19
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1                                 0x9cb9
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE1                                 0x9d59
-+#define mmTX_DISP_RFU6_LANE2                                                    0x4909
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2                                 0x4909
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2                                 0x49a9
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2                                 0x9a49
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2                                 0x9ae9
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2                                 0x9b89
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2                                 0x9c29
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2                                 0x9cc9
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE2                                 0x9d69
-+#define mmTX_DISP_RFU6_LANE3                                                    0x4919
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3                                 0x4919
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3                                 0x49b9
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3                                 0x9a59
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3                                 0x9af9
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3                                 0x9b99
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3                                 0x9c39
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3                                 0x9cd9
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE3                                 0x9d79
-+#define mmTX_DISP_RFU7_LANE0                                                    0x48ea
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0                                 0x48ea
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0                                 0x498a
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0                                 0x9a2a
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0                                 0x9aca
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0                                 0x9b6a
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0                                 0x9c0a
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0                                 0x9caa
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE0                                 0x9d4a
-+#define mmTX_DISP_RFU7_LANE1                                                    0x48fa
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1                                 0x48fa
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1                                 0x499a
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1                                 0x9a3a
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1                                 0x9ada
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1                                 0x9b7a
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1                                 0x9c1a
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1                                 0x9cba
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE1                                 0x9d5a
-+#define mmTX_DISP_RFU7_LANE2                                                    0x490a
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2                                 0x490a
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2                                 0x49aa
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2                                 0x9a4a
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2                                 0x9aea
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2                                 0x9b8a
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2                                 0x9c2a
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2                                 0x9cca
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE2                                 0x9d6a
-+#define mmTX_DISP_RFU7_LANE3                                                    0x491a
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3                                 0x491a
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3                                 0x49ba
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3                                 0x9a5a
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3                                 0x9afa
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3                                 0x9b9a
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3                                 0x9c3a
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3                                 0x9cda
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE3                                 0x9d7a
-+#define mmTX_DISP_RFU8_LANE0                                                    0x48eb
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0                                 0x48eb
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0                                 0x498b
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0                                 0x9a2b
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0                                 0x9acb
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0                                 0x9b6b
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0                                 0x9c0b
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0                                 0x9cab
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE0                                 0x9d4b
-+#define mmTX_DISP_RFU8_LANE1                                                    0x48fb
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1                                 0x48fb
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1                                 0x499b
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1                                 0x9a3b
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1                                 0x9adb
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1                                 0x9b7b
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1                                 0x9c1b
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1                                 0x9cbb
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE1                                 0x9d5b
-+#define mmTX_DISP_RFU8_LANE2                                                    0x490b
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2                                 0x490b
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2                                 0x49ab
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2                                 0x9a4b
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2                                 0x9aeb
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2                                 0x9b8b
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2                                 0x9c2b
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2                                 0x9ccb
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE2                                 0x9d6b
-+#define mmTX_DISP_RFU8_LANE3                                                    0x491b
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3                                 0x491b
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3                                 0x49bb
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3                                 0x9a5b
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3                                 0x9afb
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3                                 0x9b9b
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3                                 0x9c3b
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3                                 0x9cdb
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE3                                 0x9d7b
-+#define mmTX_DISP_RFU9_LANE0                                                    0x48ec
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0                                 0x48ec
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0                                 0x498c
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0                                 0x9a2c
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0                                 0x9acc
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0                                 0x9b6c
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0                                 0x9c0c
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0                                 0x9cac
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE0                                 0x9d4c
-+#define mmTX_DISP_RFU9_LANE1                                                    0x48fc
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1                                 0x48fc
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1                                 0x499c
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1                                 0x9a3c
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1                                 0x9adc
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1                                 0x9b7c
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1                                 0x9c1c
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1                                 0x9cbc
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE1                                 0x9d5c
-+#define mmTX_DISP_RFU9_LANE2                                                    0x490c
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2                                 0x490c
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2                                 0x49ac
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2                                 0x9a4c
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2                                 0x9aec
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2                                 0x9b8c
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2                                 0x9c2c
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2                                 0x9ccc
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE2                                 0x9d6c
-+#define mmTX_DISP_RFU9_LANE3                                                    0x491c
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3                                 0x491c
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3                                 0x49bc
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3                                 0x9a5c
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3                                 0x9afc
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3                                 0x9b9c
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3                                 0x9c3c
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3                                 0x9cdc
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE3                                 0x9d7c
-+#define mmTX_DISP_RFU10_LANE0                                                   0x48ed
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0                                0x48ed
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0                                0x498d
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0                                0x9a2d
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0                                0x9acd
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0                                0x9b6d
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0                                0x9c0d
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0                                0x9cad
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE0                                0x9d4d
-+#define mmTX_DISP_RFU10_LANE1                                                   0x48fd
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1                                0x48fd
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1                                0x499d
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1                                0x9a3d
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1                                0x9add
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1                                0x9b7d
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1                                0x9c1d
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1                                0x9cbd
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE1                                0x9d5d
-+#define mmTX_DISP_RFU10_LANE2                                                   0x490d
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2                                0x490d
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2                                0x49ad
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2                                0x9a4d
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2                                0x9aed
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2                                0x9b8d
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2                                0x9c2d
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2                                0x9ccd
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE2                                0x9d6d
-+#define mmTX_DISP_RFU10_LANE3                                                   0x491d
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3                                0x491d
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3                                0x49bd
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3                                0x9a5d
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3                                0x9afd
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3                                0x9b9d
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3                                0x9c3d
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3                                0x9cdd
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE3                                0x9d7d
-+#define mmTX_DISP_RFU11_LANE0                                                   0x48ee
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0                                0x48ee
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0                                0x498e
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0                                0x9a2e
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0                                0x9ace
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0                                0x9b6e
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0                                0x9c0e
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0                                0x9cae
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE0                                0x9d4e
-+#define mmTX_DISP_RFU11_LANE1                                                   0x48fe
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1                                0x48fe
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1                                0x499e
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1                                0x9a3e
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1                                0x9ade
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1                                0x9b7e
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1                                0x9c1e
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1                                0x9cbe
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE1                                0x9d5e
-+#define mmTX_DISP_RFU11_LANE2                                                   0x490e
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2                                0x490e
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2                                0x49ae
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2                                0x9a4e
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2                                0x9aee
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2                                0x9b8e
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2                                0x9c2e
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2                                0x9cce
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE2                                0x9d6e
-+#define mmTX_DISP_RFU11_LANE3                                                   0x491e
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3                                0x491e
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3                                0x49be
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3                                0x9a5e
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3                                0x9afe
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3                                0x9b9e
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3                                0x9c3e
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3                                0x9cde
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE3                                0x9d7e
-+#define mmTX_DISP_RFU12_LANE0                                                   0x48ef
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0                                0x48ef
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0                                0x498f
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0                                0x9a2f
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0                                0x9acf
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0                                0x9b6f
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0                                0x9c0f
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0                                0x9caf
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE0                                0x9d4f
-+#define mmTX_DISP_RFU12_LANE1                                                   0x48ff
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1                                0x48ff
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1                                0x499f
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1                                0x9a3f
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1                                0x9adf
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1                                0x9b7f
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1                                0x9c1f
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1                                0x9cbf
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE1                                0x9d5f
-+#define mmTX_DISP_RFU12_LANE2                                                   0x490f
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2                                0x490f
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2                                0x49af
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2                                0x9a4f
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2                                0x9aef
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2                                0x9b8f
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2                                0x9c2f
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2                                0x9ccf
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE2                                0x9d6f
-+#define mmTX_DISP_RFU12_LANE3                                                   0x491f
-+#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3                                0x491f
-+#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3                                0x49bf
-+#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3                                0x9a5f
-+#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3                                0x9aff
-+#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3                                0x9b9f
-+#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3                                0x9c3f
-+#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3                                0x9cdf
-+#define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE3                                0x9d7f
-+#define mmCOMMON_MAR_DEEMPH_NOM                                                 0x48c3
-+#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM                              0x48c3
-+#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM                              0x4963
-+#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM                              0x9a03
-+#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM                              0x9aa3
-+#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM                              0x9b43
-+#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM                              0x9be3
-+#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM                              0x9c83
-+#define mmDC_COMBOPHYCMREGS7_COMMON_MAR_DEEMPH_NOM                              0x9d23
-+#define mmCOMMON_LANE_PWRMGMT                                                   0x48c4
-+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT                                0x48c4
-+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT                                0x4964
-+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT                                0x9a04
-+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT                                0x9aa4
-+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT                                0x9b44
-+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT                                0x9be4
-+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT                                0x9c84
-+#define mmDC_COMBOPHYCMREGS7_COMMON_LANE_PWRMGMT                                0x9d24
-+#define mmCOMMON_TXCNTRL                                                        0x48c5
-+#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL                                     0x48c5
-+#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL                                     0x4965
-+#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL                                     0x9a05
-+#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL                                     0x9aa5
-+#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL                                     0x9b45
-+#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL                                     0x9be5
-+#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL                                     0x9c85
-+#define mmDC_COMBOPHYCMREGS7_COMMON_TXCNTRL                                     0x9d25
-+#define mmCOMMON_TMDP                                                           0x48c6
-+#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP                                        0x48c6
-+#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP                                        0x4966
-+#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP                                        0x9a06
-+#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP                                        0x9aa6
-+#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP                                        0x9b46
-+#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP                                        0x9be6
-+#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP                                        0x9c86
-+#define mmDC_COMBOPHYCMREGS7_COMMON_TMDP                                        0x9d26
-+#define mmCOMMON_LANE_RESETS                                                    0x48c7
-+#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS                                 0x48c7
-+#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS                                 0x4967
-+#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS                                 0x9a07
-+#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS                                 0x9aa7
-+#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS                                 0x9b47
-+#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS                                 0x9be7
-+#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS                                 0x9c87
-+#define mmDC_COMBOPHYCMREGS7_COMMON_LANE_RESETS                                 0x9d27
-+#define mmCOMMON_ZCALCODE_CTRL                                                  0x48c8
-+#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL                               0x48c8
-+#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL                               0x4968
-+#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL                               0x9a08
-+#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL                               0x9aa8
-+#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL                               0x9b48
-+#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL                               0x9be8
-+#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL                               0x9c88
-+#define mmDC_COMBOPHYCMREGS7_COMMON_ZCALCODE_CTRL                               0x9d28
-+#define mmCOMMON_DISP_RFU1                                                      0x48c9
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1                                   0x48c9
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1                                   0x4969
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1                                   0x9a09
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1                                   0x9aa9
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1                                   0x9b49
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1                                   0x9be9
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1                                   0x9c89
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU1                                   0x9d29
-+#define mmCOMMON_DISP_RFU2                                                      0x48ca
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2                                   0x48ca
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2                                   0x496a
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2                                   0x9a0a
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2                                   0x9aaa
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2                                   0x9b4a
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2                                   0x9bea
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2                                   0x9c8a
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU2                                   0x9d2a
-+#define mmCOMMON_DISP_RFU3                                                      0x48cb
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3                                   0x48cb
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3                                   0x496b
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3                                   0x9a0b
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3                                   0x9aab
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3                                   0x9b4b
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3                                   0x9beb
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3                                   0x9c8b
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU3                                   0x9d2b
-+#define mmCOMMON_DISP_RFU4                                                      0x48cc
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4                                   0x48cc
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4                                   0x496c
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4                                   0x9a0c
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4                                   0x9aac
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4                                   0x9b4c
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4                                   0x9bec
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4                                   0x9c8c
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU4                                   0x9d2c
-+#define mmCOMMON_DISP_RFU5                                                      0x48cd
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5                                   0x48cd
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5                                   0x496d
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5                                   0x9a0d
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5                                   0x9aad
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5                                   0x9b4d
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5                                   0x9bed
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5                                   0x9c8d
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU5                                   0x9d2d
-+#define mmCOMMON_DISP_RFU6                                                      0x48ce
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6                                   0x48ce
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6                                   0x496e
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6                                   0x9a0e
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6                                   0x9aae
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6                                   0x9b4e
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6                                   0x9bee
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6                                   0x9c8e
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU6                                   0x9d2e
-+#define mmCOMMON_DISP_RFU7                                                      0x48cf
-+#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7                                   0x48cf
-+#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7                                   0x496f
-+#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7                                   0x9a0f
-+#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7                                   0x9aaf
-+#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7                                   0x9b4f
-+#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7                                   0x9bef
-+#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7                                   0x9c8f
-+#define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU7                                   0x9d2f
-+#define mmFREQ_CTRL0                                                            0x4920
-+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0                                        0x4920
-+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0                                        0x49c0
-+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0                                        0x9a60
-+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0                                        0x9b00
-+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0                                        0x9ba0
-+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0                                        0x9c40
-+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0                                        0x9ce0
-+#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL0                                        0x9d80
-+#define mmFREQ_CTRL1                                                            0x4921
-+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1                                        0x4921
-+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1                                        0x49c1
-+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1                                        0x9a61
-+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1                                        0x9b01
-+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1                                        0x9ba1
-+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1                                        0x9c41
-+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1                                        0x9ce1
-+#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL1                                        0x9d81
-+#define mmFREQ_CTRL2                                                            0x4922
-+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2                                        0x4922
-+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2                                        0x49c2
-+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2                                        0x9a62
-+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2                                        0x9b02
-+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2                                        0x9ba2
-+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2                                        0x9c42
-+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2                                        0x9ce2
-+#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL2                                        0x9d82
-+#define mmFREQ_CTRL3                                                            0x4923
-+#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3                                        0x4923
-+#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3                                        0x49c3
-+#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3                                        0x9a63
-+#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3                                        0x9b03
-+#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3                                        0x9ba3
-+#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3                                        0x9c43
-+#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3                                        0x9ce3
-+#define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL3                                        0x9d83
-+#define mmBW_CTRL_COARSE                                                        0x4924
-+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE                                    0x4924
-+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE                                    0x49c4
-+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE                                    0x9a64
-+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE                                    0x9b04
-+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE                                    0x9ba4
-+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE                                    0x9c44
-+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE                                    0x9ce4
-+#define mmDC_COMBOPHYPLLREGS7_BW_CTRL_COARSE                                    0x9d84
-+#define mmBW_CTRL_FINE                                                          0x4925
-+#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE                                      0x4925
-+#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE                                      0x49c5
-+#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE                                      0x9a65
-+#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE                                      0x9b05
-+#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE                                      0x9ba5
-+#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE                                      0x9c45
-+#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE                                      0x9ce5
-+#define mmDC_COMBOPHYPLLREGS7_BW_CTRL_FINE                                      0x9d85
-+#define mmCAL_CTRL                                                              0x4926
-+#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL                                          0x4926
-+#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL                                          0x49c6
-+#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL                                          0x9a66
-+#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL                                          0x9b06
-+#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL                                          0x9ba6
-+#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL                                          0x9c46
-+#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL                                          0x9ce6
-+#define mmDC_COMBOPHYPLLREGS7_CAL_CTRL                                          0x9d86
-+#define mmLOOP_CTRL                                                             0x4927
-+#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL                                         0x4927
-+#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL                                         0x49c7
-+#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL                                         0x9a67
-+#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL                                         0x9b07
-+#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL                                         0x9ba7
-+#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL                                         0x9c47
-+#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL                                         0x9ce7
-+#define mmDC_COMBOPHYPLLREGS7_LOOP_CTRL                                         0x9d87
-+#define mmDEBUG0                                                                0x4928
-+#define mmDC_COMBOPHYPLLREGS0_DEBUG0                                            0x4928
-+#define mmDC_COMBOPHYPLLREGS1_DEBUG0                                            0x49c8
-+#define mmDC_COMBOPHYPLLREGS2_DEBUG0                                            0x9a68
-+#define mmDC_COMBOPHYPLLREGS3_DEBUG0                                            0x9b08
-+#define mmDC_COMBOPHYPLLREGS4_DEBUG0                                            0x9ba8
-+#define mmDC_COMBOPHYPLLREGS5_DEBUG0                                            0x9c48
-+#define mmDC_COMBOPHYPLLREGS6_DEBUG0                                            0x9ce8
-+#define mmDC_COMBOPHYPLLREGS7_DEBUG0                                            0x9d88
-+#define mmVREG_CFG                                                              0x4929
-+#define mmDC_COMBOPHYPLLREGS0_VREG_CFG                                          0x4929
-+#define mmDC_COMBOPHYPLLREGS1_VREG_CFG                                          0x49c9
-+#define mmDC_COMBOPHYPLLREGS2_VREG_CFG                                          0x9a69
-+#define mmDC_COMBOPHYPLLREGS3_VREG_CFG                                          0x9b09
-+#define mmDC_COMBOPHYPLLREGS4_VREG_CFG                                          0x9ba9
-+#define mmDC_COMBOPHYPLLREGS5_VREG_CFG                                          0x9c49
-+#define mmDC_COMBOPHYPLLREGS6_VREG_CFG                                          0x9ce9
-+#define mmDC_COMBOPHYPLLREGS7_VREG_CFG                                          0x9d89
-+#define mmOBSERVE0                                                              0x492a
-+#define mmDC_COMBOPHYPLLREGS0_OBSERVE0                                          0x492a
-+#define mmDC_COMBOPHYPLLREGS1_OBSERVE0                                          0x49ca
-+#define mmDC_COMBOPHYPLLREGS2_OBSERVE0                                          0x9a6a
-+#define mmDC_COMBOPHYPLLREGS3_OBSERVE0                                          0x9b0a
-+#define mmDC_COMBOPHYPLLREGS4_OBSERVE0                                          0x9baa
-+#define mmDC_COMBOPHYPLLREGS5_OBSERVE0                                          0x9c4a
-+#define mmDC_COMBOPHYPLLREGS6_OBSERVE0                                          0x9cea
-+#define mmDC_COMBOPHYPLLREGS7_OBSERVE0                                          0x9d8a
-+#define mmOBSERVE1                                                              0x492b
-+#define mmDC_COMBOPHYPLLREGS0_OBSERVE1                                          0x492b
-+#define mmDC_COMBOPHYPLLREGS1_OBSERVE1                                          0x49cb
-+#define mmDC_COMBOPHYPLLREGS2_OBSERVE1                                          0x9a6b
-+#define mmDC_COMBOPHYPLLREGS3_OBSERVE1                                          0x9b0b
-+#define mmDC_COMBOPHYPLLREGS4_OBSERVE1                                          0x9bab
-+#define mmDC_COMBOPHYPLLREGS5_OBSERVE1                                          0x9c4b
-+#define mmDC_COMBOPHYPLLREGS6_OBSERVE1                                          0x9ceb
-+#define mmDC_COMBOPHYPLLREGS7_OBSERVE1                                          0x9d8b
-+#define mmDFT_OUT                                                               0x492c
-+#define mmDC_COMBOPHYPLLREGS0_DFT_OUT                                           0x492c
-+#define mmDC_COMBOPHYPLLREGS1_DFT_OUT                                           0x49cc
-+#define mmDC_COMBOPHYPLLREGS2_DFT_OUT                                           0x9a6c
-+#define mmDC_COMBOPHYPLLREGS3_DFT_OUT                                           0x9b0c
-+#define mmDC_COMBOPHYPLLREGS4_DFT_OUT                                           0x9bac
-+#define mmDC_COMBOPHYPLLREGS5_DFT_OUT                                           0x9c4c
-+#define mmDC_COMBOPHYPLLREGS6_DFT_OUT                                           0x9cec
-+#define mmDC_COMBOPHYPLLREGS7_DFT_OUT                                           0x9d8c
-+#define mmPLL_WRAP_CNTRL1                                                       0x495e
-+#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1                                   0x495e
-+#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1                                   0x49fe
-+#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1                                   0x9a9e
-+#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1                                   0x9b3e
-+#define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL1                                   0x9bde
-+#define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL1                                   0x9c7e
-+#define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL1                                   0x9d1e
-+#define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL1                                   0x9dbe
-+#define mmPLL_WRAP_CNTRL                                                        0x495f
-+#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL                                    0x495f
-+#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL                                    0x49ff
-+#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL                                    0x9a9f
-+#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL                                    0x9b3f
-+#define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL                                    0x9bdf
-+#define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL                                    0x9c7f
-+#define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL                                    0x9d1f
-+#define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL                                    0x9dbf
-+#define mmPPLL_VREG_CFG                                                         0x1700
-+#define mmDC_DISPLAYPLLREGS0_PPLL_VREG_CFG                                      0x1700
-+#define mmDC_DISPLAYPLLREGS1_PPLL_VREG_CFG                                      0x172a
-+#define mmDC_DISPLAYPLLREGS2_PPLL_VREG_CFG                                      0x1754
-+#define mmPPLL_MODE_CNTL                                                        0x1701
-+#define mmDC_DISPLAYPLLREGS0_PPLL_MODE_CNTL                                     0x1701
-+#define mmDC_DISPLAYPLLREGS1_PPLL_MODE_CNTL                                     0x172b
-+#define mmDC_DISPLAYPLLREGS2_PPLL_MODE_CNTL                                     0x1755
-+#define mmPPLL_FREQ_CTRL0                                                       0x1702
-+#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL0                                    0x1702
-+#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL0                                    0x172c
-+#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL0                                    0x1756
-+#define mmPPLL_FREQ_CTRL1                                                       0x1703
-+#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL1                                    0x1703
-+#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL1                                    0x172d
-+#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL1                                    0x1757
-+#define mmPPLL_FREQ_CTRL2                                                       0x1704
-+#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL2                                    0x1704
-+#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL2                                    0x172e
-+#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL2                                    0x1758
-+#define mmPPLL_FREQ_CTRL3                                                       0x1705
-+#define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL3                                    0x1705
-+#define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL3                                    0x172f
-+#define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL3                                    0x1759
-+#define mmPPLL_BW_CTRL_COARSE                                                   0x1706
-+#define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_COARSE                                0x1706
-+#define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_COARSE                                0x1730
-+#define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_COARSE                                0x175a
-+#define mmPPLL_BW_CTRL_FINE                                                     0x1708
-+#define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_FINE                                  0x1708
-+#define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_FINE                                  0x1732
-+#define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_FINE                                  0x175c
-+#define mmPPLL_CAL_CTRL                                                         0x1709
-+#define mmDC_DISPLAYPLLREGS0_PPLL_CAL_CTRL                                      0x1709
-+#define mmDC_DISPLAYPLLREGS1_PPLL_CAL_CTRL                                      0x1733
-+#define mmDC_DISPLAYPLLREGS2_PPLL_CAL_CTRL                                      0x175d
-+#define mmPPLL_LOOP_CTRL                                                        0x170a
-+#define mmDC_DISPLAYPLLREGS0_PPLL_LOOP_CTRL                                     0x170a
-+#define mmDC_DISPLAYPLLREGS1_PPLL_LOOP_CTRL                                     0x1734
-+#define mmDC_DISPLAYPLLREGS2_PPLL_LOOP_CTRL                                     0x175e
-+#define mmPPLL_REFCLK_CNTL                                                      0x1718
-+#define mmDC_DISPLAYPLLREGS0_PPLL_REFCLK_CNTL                                   0x1718
-+#define mmDC_DISPLAYPLLREGS1_PPLL_REFCLK_CNTL                                   0x1742
-+#define mmDC_DISPLAYPLLREGS2_PPLL_REFCLK_CNTL                                   0x176c
-+#define mmPPLL_CLKOUT_CNTL                                                      0x1719
-+#define mmDC_DISPLAYPLLREGS0_PPLL_CLKOUT_CNTL                                   0x1719
-+#define mmDC_DISPLAYPLLREGS1_PPLL_CLKOUT_CNTL                                   0x1743
-+#define mmDC_DISPLAYPLLREGS2_PPLL_CLKOUT_CNTL                                   0x176d
-+#define mmPPLL_DFT_CNTL                                                         0x171a
-+#define mmDC_DISPLAYPLLREGS0_PPLL_DFT_CNTL                                      0x171a
-+#define mmDC_DISPLAYPLLREGS1_PPLL_DFT_CNTL                                      0x1744
-+#define mmDC_DISPLAYPLLREGS2_PPLL_DFT_CNTL                                      0x176e
-+#define mmPPLL_ANALOG_CNTL                                                      0x171b
-+#define mmDC_DISPLAYPLLREGS0_PPLL_ANALOG_CNTL                                   0x171b
-+#define mmDC_DISPLAYPLLREGS1_PPLL_ANALOG_CNTL                                   0x1745
-+#define mmDC_DISPLAYPLLREGS2_PPLL_ANALOG_CNTL                                   0x176f
-+#define mmPPLL_POSTDIV                                                          0x171c
-+#define mmDC_DISPLAYPLLREGS0_PPLL_POSTDIV                                       0x171c
-+#define mmDC_DISPLAYPLLREGS1_PPLL_POSTDIV                                       0x1746
-+#define mmDC_DISPLAYPLLREGS2_PPLL_POSTDIV                                       0x1770
-+#define mmPPLL_DEBUG0                                                           0x1720
-+#define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG0                                        0x1720
-+#define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG0                                        0x174a
-+#define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG0                                        0x1774
-+#define mmPPLL_OBSERVE0                                                         0x1721
-+#define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0                                      0x1721
-+#define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0                                      0x174b
-+#define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0                                      0x1775
-+#define mmPPLL_OBSERVE1                                                         0x1722
-+#define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE1                                      0x1722
-+#define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE1                                      0x174c
-+#define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE1                                      0x1776
-+#define mmPPLL_UPDATE_CNTL                                                      0x1724
-+#define mmDC_DISPLAYPLLREGS0_PPLL_UPDATE_CNTL                                   0x1724
-+#define mmDC_DISPLAYPLLREGS1_PPLL_UPDATE_CNTL                                   0x174e
-+#define mmDC_DISPLAYPLLREGS2_PPLL_UPDATE_CNTL                                   0x1778
-+#define mmPPLL_OBSERVE0_OUT                                                     0x1725
-+#define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0_OUT                                  0x1725
-+#define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0_OUT                                  0x174f
-+#define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0_OUT                                  0x1779
-+#define mmPPLL_STATUS_DEBUG1                                                    0x1726
-+#define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG1                                 0x1726
-+#define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG1                                 0x1750
-+#define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG1                                 0x177a
-+#define mmPPLL_DEBUG_MUX_CNTL                                                   0x1727
-+#define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG_MUX_CNTL                                0x1727
-+#define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG_MUX_CNTL                                0x1751
-+#define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG_MUX_CNTL                                0x177b
-+#define mmPPLL_DIV_UPDATE_DEBUG                                                 0x1728
-+#define mmDC_DISPLAYPLLREGS0_PPLL_DIV_UPDATE_DEBUG                              0x1728
-+#define mmDC_DISPLAYPLLREGS1_PPLL_DIV_UPDATE_DEBUG                              0x1752
-+#define mmDC_DISPLAYPLLREGS2_PPLL_DIV_UPDATE_DEBUG                              0x177c
-+#define mmPPLL_STATUS_DEBUG0                                                    0x1729
-+#define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG0                                 0x1729
-+#define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG0                                 0x1753
-+#define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG0                                 0x177d
-+#define mmCOMP_EN_CTL                                                           0x9dc0
-+#define mmDPCSTX_PHY_CNTL                                                       0x48d0
-+#define mmDPCSTX0_DPCSTX_PHY_CNTL                                               0x48d0
-+#define mmDPCSTX1_DPCSTX_PHY_CNTL                                               0x4970
-+#define mmDPCSTX2_DPCSTX_PHY_CNTL                                               0x9a10
-+#define mmDPCSTX3_DPCSTX_PHY_CNTL                                               0x9ab0
-+#define mmDPCSTX4_DPCSTX_PHY_CNTL                                               0x9b50
-+#define mmDPCSTX5_DPCSTX_PHY_CNTL                                               0x9bf0
-+#define mmDPCSTX6_DPCSTX_PHY_CNTL                                               0x9c90
-+#define mmDPCSTX7_DPCSTX_PHY_CNTL                                               0x9d30
-+#define mmDPCSTX_TX_CLOCK_CNTL                                                  0x48d1
-+#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                          0x48d1
-+#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                          0x4971
-+#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                          0x9a11
-+#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                          0x9ab1
-+#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                          0x9b51
-+#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL                                          0x9bf1
-+#define mmDPCSTX6_DPCSTX_TX_CLOCK_CNTL                                          0x9c91
-+#define mmDPCSTX7_DPCSTX_TX_CLOCK_CNTL                                          0x9d31
-+#define mmDPCSTX_TX_CNTL                                                        0x48d3
-+#define mmDPCSTX0_DPCSTX_TX_CNTL                                                0x48d3
-+#define mmDPCSTX1_DPCSTX_TX_CNTL                                                0x4973
-+#define mmDPCSTX2_DPCSTX_TX_CNTL                                                0x9a13
-+#define mmDPCSTX3_DPCSTX_TX_CNTL                                                0x9ab3
-+#define mmDPCSTX4_DPCSTX_TX_CNTL                                                0x9b53
-+#define mmDPCSTX5_DPCSTX_TX_CNTL                                                0x9bf3
-+#define mmDPCSTX6_DPCSTX_TX_CNTL                                                0x9c93
-+#define mmDPCSTX7_DPCSTX_TX_CNTL                                                0x9d33
-+#define mmDPCSTX_CBUS_CNTL                                                      0x48d5
-+#define mmDPCSTX0_DPCSTX_CBUS_CNTL                                              0x48d5
-+#define mmDPCSTX1_DPCSTX_CBUS_CNTL                                              0x4975
-+#define mmDPCSTX2_DPCSTX_CBUS_CNTL                                              0x9a15
-+#define mmDPCSTX3_DPCSTX_CBUS_CNTL                                              0x9ab5
-+#define mmDPCSTX4_DPCSTX_CBUS_CNTL                                              0x9b55
-+#define mmDPCSTX5_DPCSTX_CBUS_CNTL                                              0x9bf5
-+#define mmDPCSTX6_DPCSTX_CBUS_CNTL                                              0x9c95
-+#define mmDPCSTX7_DPCSTX_CBUS_CNTL                                              0x9d35
-+#define mmDPCSTX_REG_ERROR_STATUS                                               0x48d6
-+#define mmDPCSTX0_DPCSTX_REG_ERROR_STATUS                                       0x48d6
-+#define mmDPCSTX1_DPCSTX_REG_ERROR_STATUS                                       0x4976
-+#define mmDPCSTX2_DPCSTX_REG_ERROR_STATUS                                       0x9a16
-+#define mmDPCSTX3_DPCSTX_REG_ERROR_STATUS                                       0x9ab6
-+#define mmDPCSTX4_DPCSTX_REG_ERROR_STATUS                                       0x9b56
-+#define mmDPCSTX5_DPCSTX_REG_ERROR_STATUS                                       0x9bf6
-+#define mmDPCSTX6_DPCSTX_REG_ERROR_STATUS                                       0x9c96
-+#define mmDPCSTX7_DPCSTX_REG_ERROR_STATUS                                       0x9d36
-+#define mmDPCSTX_TX_ERROR_STATUS                                                0x48d7
-+#define mmDPCSTX0_DPCSTX_TX_ERROR_STATUS                                        0x48d7
-+#define mmDPCSTX1_DPCSTX_TX_ERROR_STATUS                                        0x4977
-+#define mmDPCSTX2_DPCSTX_TX_ERROR_STATUS                                        0x9a17
-+#define mmDPCSTX3_DPCSTX_TX_ERROR_STATUS                                        0x9ab7
-+#define mmDPCSTX4_DPCSTX_TX_ERROR_STATUS                                        0x9b57
-+#define mmDPCSTX5_DPCSTX_TX_ERROR_STATUS                                        0x9bf7
-+#define mmDPCSTX6_DPCSTX_TX_ERROR_STATUS                                        0x9c97
-+#define mmDPCSTX7_DPCSTX_TX_ERROR_STATUS                                        0x9d37
-+#define mmDPCSTX_PLL_UPDATE_ADDR                                                0x48d8
-+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                        0x48d8
-+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                        0x4978
-+#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                        0x9a18
-+#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                        0x9ab8
-+#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                        0x9b58
-+#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR                                        0x9bf8
-+#define mmDPCSTX6_DPCSTX_PLL_UPDATE_ADDR                                        0x9c98
-+#define mmDPCSTX7_DPCSTX_PLL_UPDATE_ADDR                                        0x9d38
-+#define mmDPCSTX_PLL_UPDATE_DATA                                                0x48d9
-+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                        0x48d9
-+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                        0x4979
-+#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                        0x9a19
-+#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                        0x9ab9
-+#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                        0x9b59
-+#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA                                        0x9bf9
-+#define mmDPCSTX6_DPCSTX_PLL_UPDATE_DATA                                        0x9c99
-+#define mmDPCSTX7_DPCSTX_PLL_UPDATE_DATA                                        0x9d39
-+#define mmDPCSTX_INDEX_MODE_ADDR                                                0x48da
-+#define mmDPCSTX0_DPCSTX_INDEX_MODE_ADDR                                        0x48da
-+#define mmDPCSTX1_DPCSTX_INDEX_MODE_ADDR                                        0x497a
-+#define mmDPCSTX2_DPCSTX_INDEX_MODE_ADDR                                        0x9a1a
-+#define mmDPCSTX3_DPCSTX_INDEX_MODE_ADDR                                        0x9aba
-+#define mmDPCSTX4_DPCSTX_INDEX_MODE_ADDR                                        0x9b5a
-+#define mmDPCSTX5_DPCSTX_INDEX_MODE_ADDR                                        0x9bfa
-+#define mmDPCSTX6_DPCSTX_INDEX_MODE_ADDR                                        0x9c9a
-+#define mmDPCSTX7_DPCSTX_INDEX_MODE_ADDR                                        0x9d3a
-+#define mmDPCSTX_INDEX_MODE_DATA                                                0x48db
-+#define mmDPCSTX0_DPCSTX_INDEX_MODE_DATA                                        0x48db
-+#define mmDPCSTX1_DPCSTX_INDEX_MODE_DATA                                        0x497b
-+#define mmDPCSTX2_DPCSTX_INDEX_MODE_DATA                                        0x9a1b
-+#define mmDPCSTX3_DPCSTX_INDEX_MODE_DATA                                        0x9abb
-+#define mmDPCSTX4_DPCSTX_INDEX_MODE_DATA                                        0x9b5b
-+#define mmDPCSTX5_DPCSTX_INDEX_MODE_DATA                                        0x9bfb
-+#define mmDPCSTX6_DPCSTX_INDEX_MODE_DATA                                        0x9c9b
-+#define mmDPCSTX7_DPCSTX_INDEX_MODE_DATA                                        0x9d3b
-+#define mmDPCSTX_DEBUG_CONFIG                                                   0x48dc
-+#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                           0x48dc
-+#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                           0x497c
-+#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                           0x9a1c
-+#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                           0x9abc
-+#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                           0x9b5c
-+#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG                                           0x9bfc
-+#define mmDPCSTX6_DPCSTX_DEBUG_CONFIG                                           0x9c9c
-+#define mmDPCSTX7_DPCSTX_DEBUG_CONFIG                                           0x9d3c
-+#define mmDPCSTX_TEST_DEBUG_DATA                                                0x48dd
-+#define mmDPCSTX0_DPCSTX_TEST_DEBUG_DATA                                        0x48dd
-+#define mmDPCSTX1_DPCSTX_TEST_DEBUG_DATA                                        0x497d
-+#define mmDPCSTX2_DPCSTX_TEST_DEBUG_DATA                                        0x9a1d
-+#define mmDPCSTX3_DPCSTX_TEST_DEBUG_DATA                                        0x9abd
-+#define mmDPCSTX4_DPCSTX_TEST_DEBUG_DATA                                        0x9b5d
-+#define mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA                                        0x9bfd
-+#define mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA                                        0x9c9d
-+#define mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA                                        0x9d3d
-+
-+#endif /* DCE_11_2_D_H */
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
-new file mode 100644
-index 0000000..b2ea420
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
-@@ -0,0 +1,6813 @@
-+/*
-+ * DCE_11_2 Register documentation
-+ *
-+ * Copyright (C) 2016  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef DCE_11_2_ENUM_H
-+#define DCE_11_2_ENUM_H
-+
-+typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
-+	CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL        = 0x0,
-+	CRTC_CONTROL_CRTC_START_POINT_CNTL_DP            = 0x1,
-+} CRTC_CONTROL_CRTC_START_POINT_CNTL;
-+typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
-+	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL       = 0x0,
-+	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP           = 0x1,
-+} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
-+typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
-+	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE     = 0x0,
-+	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
-+	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED    = 0x2,
-+	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
-+} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
-+typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
-+	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE    = 0x0,
-+	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE     = 0x1,
-+} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
-+typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
-+	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
-+	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
-+} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
-+typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
-+	CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE              = 0x0,
-+	CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE               = 0x1,
-+} CRTC_CONTROL_CRTC_SOF_PULL_EN;
-+typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
-+	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE       = 0x0,
-+	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE        = 0x1,
-+} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
-+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
-+	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x0,
-+	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE   = 0x1,
-+} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
-+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
-+	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x0,
-+	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE   = 0x1,
-+} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
-+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
-+} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
-+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
-+	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
-+	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
-+} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
-+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
-+	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
-+	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
-+} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
-+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
-+	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
-+} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
-+typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
-+	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
-+	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
-+} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
-+typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
-+	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
-+	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
-+} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
-+typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
-+	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE       = 0x0,
-+	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE        = 0x1,
-+} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
-+typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
-+	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE     = 0x0,
-+	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE      = 0x1,
-+} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
-+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x7,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x8,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x9,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0xa,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1    = 0xb,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2    = 0xc,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0   = 0x10,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1   = 0x11,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2   = 0x12,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON   = 0x13,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
-+} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
-+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
-+} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
-+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
-+} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
-+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE           = 0x0,
-+	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE            = 0x1,
-+} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
-+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x7,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x8,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x9,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0xa,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1    = 0xb,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2    = 0xc,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0   = 0x10,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1   = 0x11,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2   = 0x12,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON   = 0x13,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
-+} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
-+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
-+} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
-+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
-+} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
-+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE           = 0x0,
-+	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE            = 0x1,
-+} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
-+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
-+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
-+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
-+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
-+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
-+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
-+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
-+	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
-+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
-+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
-+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
-+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
-+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
-+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
-+	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
-+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
-+typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
-+	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
-+	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
-+	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
-+	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
-+} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
-+typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
-+	CRTC_CONTROL_CRTC_MASTER_EN_FALSE                = 0x0,
-+	CRTC_CONTROL_CRTC_MASTER_EN_TRUE                 = 0x1,
-+} CRTC_CONTROL_CRTC_MASTER_EN;
-+typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
-+	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE      = 0x0,
-+	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE       = 0x1,
-+} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
-+typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
-+	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE      = 0x0,
-+	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE       = 0x1,
-+} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
-+typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
-+	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
-+	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
-+} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
-+typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
-+	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
-+	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
-+	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
-+	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
-+} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
-+typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
-+	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
-+	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
-+} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
-+typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
-+	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
-+	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
-+} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
-+typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
-+	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x0,
-+	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE   = 0x1,
-+} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
-+typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
-+	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
-+	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
-+} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
-+typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
-+	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
-+	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
-+} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
-+typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
-+	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
-+	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
-+	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
-+	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
-+} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
-+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
-+} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
-+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
-+} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
-+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
-+} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
-+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE         = 0x0,
-+	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE          = 0x1,
-+} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
-+typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
-+	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE   = 0x0,
-+	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE    = 0x1,
-+} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
-+typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
-+	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
-+	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
-+	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
-+	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
-+} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
-+typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
-+	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
-+	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
-+} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
-+typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
-+	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
-+	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
-+} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
-+typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
-+	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
-+	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
-+} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
-+typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
-+	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE   = 0x0,
-+	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE    = 0x1,
-+} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE   = 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE   = 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
-+	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
-+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
-+	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
-+	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
-+} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
-+typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
-+	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE          = 0x0,
-+	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE           = 0x1,
-+} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
-+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
-+	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
-+	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
-+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
-+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
-+	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
-+	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
-+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
-+typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
-+	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
-+	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
-+} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
-+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
-+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
-+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
-+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
-+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
-+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
-+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
-+	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
-+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
-+typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
-+	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE      = 0x0,
-+	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE       = 0x1,
-+} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
-+typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
-+	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
-+	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
-+} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
-+typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
-+	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE   = 0x0,
-+	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE    = 0x1,
-+} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
-+typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN    = 0x0,
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA     = 0x1,
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA     = 0x2,
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE     = 0x3,
-+} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
-+typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
-+	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
-+} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
-+typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
-+	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
-+	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
-+	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
-+} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
-+typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
-+	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE        = 0x0,
-+	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE         = 0x1,
-+} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
-+typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
-+	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
-+	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
-+} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
-+typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
-+	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
-+	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
-+} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
-+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
-+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
-+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
-+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
-+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
-+	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
-+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
-+	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
-+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
-+	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
-+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
-+	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
-+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
-+	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
-+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
-+	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
-+	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
-+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
-+	CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE                  = 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE                   = 0x1,
-+} CRTC_CRC_CNTL_CRTC_CRC_EN;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
-+	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE             = 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE              = 0x1,
-+} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
-+	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT          = 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT         = 0x1,
-+	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES     = 0x2,
-+	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS   = 0x3,
-+} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
-+	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP        = 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM     = 0x1,
-+	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
-+	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
-+} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
-+	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
-+} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB          = 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B         = 0x1,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB         = 0x2,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B        = 0x3,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB          = 0x4,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B         = 0x5,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB         = 0x6,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B        = 0x7,
-+} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
-+typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB          = 0x0,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B         = 0x1,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB         = 0x2,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B        = 0x3,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB          = 0x4,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B         = 0x5,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB         = 0x6,
-+	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B        = 0x7,
-+} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT= 0x1,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS= 0x2,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED= 0x3,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel= 0x1,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel= 0x2,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel= 0x3,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
-+typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
-+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
-+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
-+typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME= 0x0,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME= 0x1,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME= 0x2,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME= 0x3,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME= 0x4,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME= 0x5,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME= 0x6,
-+	CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME= 0x7,
-+} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
-+typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
-+	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
-+typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
-+	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
-+typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
-+	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
-+typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
-+	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
-+typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
-+	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE= 0x0,
-+	CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE= 0x1,
-+} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
-+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
-+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
-+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
-+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
-+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
-+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
-+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE= 0x0,
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE= 0x1,
-+} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
-+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF= 0x0,
-+	CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON= 0x1,
-+} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
-+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
-+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
-+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
-+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
-+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
-+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
-+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
-+	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
-+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
-+typedef enum CRTC_V_SYNC_A_POL {
-+	CRTC_V_SYNC_A_POL_HIGH                           = 0x0,
-+	CRTC_V_SYNC_A_POL_LOW                            = 0x1,
-+} CRTC_V_SYNC_A_POL;
-+typedef enum CRTC_H_SYNC_A_POL {
-+	CRTC_H_SYNC_A_POL_HIGH                           = 0x0,
-+	CRTC_H_SYNC_A_POL_LOW                            = 0x1,
-+} CRTC_H_SYNC_A_POL;
-+typedef enum CRTC_HORZ_REPETITION_COUNT {
-+	CRTC_HORZ_REPETITION_COUNT_0                     = 0x0,
-+	CRTC_HORZ_REPETITION_COUNT_1                     = 0x1,
-+	CRTC_HORZ_REPETITION_COUNT_2                     = 0x2,
-+	CRTC_HORZ_REPETITION_COUNT_3                     = 0x3,
-+	CRTC_HORZ_REPETITION_COUNT_4                     = 0x4,
-+	CRTC_HORZ_REPETITION_COUNT_5                     = 0x5,
-+	CRTC_HORZ_REPETITION_COUNT_6                     = 0x6,
-+	CRTC_HORZ_REPETITION_COUNT_7                     = 0x7,
-+	CRTC_HORZ_REPETITION_COUNT_8                     = 0x8,
-+	CRTC_HORZ_REPETITION_COUNT_9                     = 0x9,
-+	CRTC_HORZ_REPETITION_COUNT_10                    = 0xa,
-+	CRTC_HORZ_REPETITION_COUNT_11                    = 0xb,
-+	CRTC_HORZ_REPETITION_COUNT_12                    = 0xc,
-+	CRTC_HORZ_REPETITION_COUNT_13                    = 0xd,
-+	CRTC_HORZ_REPETITION_COUNT_14                    = 0xe,
-+	CRTC_HORZ_REPETITION_COUNT_15                    = 0xf,
-+} CRTC_HORZ_REPETITION_COUNT;
-+typedef enum PERFCOUNTER_CVALUE_SEL {
-+	PERFCOUNTER_CVALUE_SEL_47_0                      = 0x0,
-+	PERFCOUNTER_CVALUE_SEL_15_0                      = 0x1,
-+	PERFCOUNTER_CVALUE_SEL_31_16                     = 0x2,
-+	PERFCOUNTER_CVALUE_SEL_47_32                     = 0x3,
-+	PERFCOUNTER_CVALUE_SEL_11_0                      = 0x4,
-+	PERFCOUNTER_CVALUE_SEL_23_12                     = 0x5,
-+	PERFCOUNTER_CVALUE_SEL_35_24                     = 0x6,
-+	PERFCOUNTER_CVALUE_SEL_47_36                     = 0x7,
-+} PERFCOUNTER_CVALUE_SEL;
-+typedef enum PERFCOUNTER_INC_MODE {
-+	PERFCOUNTER_INC_MODE_MULTI_BIT                   = 0x0,
-+	PERFCOUNTER_INC_MODE_BOTH_EDGE                   = 0x1,
-+	PERFCOUNTER_INC_MODE_LSB                         = 0x2,
-+	PERFCOUNTER_INC_MODE_POS_EDGE                    = 0x3,
-+} PERFCOUNTER_INC_MODE;
-+typedef enum PERFCOUNTER_HW_CNTL_SEL {
-+	PERFCOUNTER_HW_CNTL_SEL_RUNEN                    = 0x0,
-+	PERFCOUNTER_HW_CNTL_SEL_CNTOFF                   = 0x1,
-+} PERFCOUNTER_HW_CNTL_SEL;
-+typedef enum PERFCOUNTER_RUNEN_MODE {
-+	PERFCOUNTER_RUNEN_MODE_LEVEL                     = 0x0,
-+	PERFCOUNTER_RUNEN_MODE_EDGE                      = 0x1,
-+} PERFCOUNTER_RUNEN_MODE;
-+typedef enum PERFCOUNTER_CNTOFF_START_DIS {
-+	PERFCOUNTER_CNTOFF_START_ENABLE                  = 0x0,
-+	PERFCOUNTER_CNTOFF_START_DISABLE                 = 0x1,
-+} PERFCOUNTER_CNTOFF_START_DIS;
-+typedef enum PERFCOUNTER_RESTART_EN {
-+	PERFCOUNTER_RESTART_DISABLE                      = 0x0,
-+	PERFCOUNTER_RESTART_ENABLE                       = 0x1,
-+} PERFCOUNTER_RESTART_EN;
-+typedef enum PERFCOUNTER_INT_EN {
-+	PERFCOUNTER_INT_DISABLE                          = 0x0,
-+	PERFCOUNTER_INT_ENABLE                           = 0x1,
-+} PERFCOUNTER_INT_EN;
-+typedef enum PERFCOUNTER_OFF_MASK {
-+	PERFCOUNTER_OFF_MASK_DISABLE                     = 0x0,
-+	PERFCOUNTER_OFF_MASK_ENABLE                      = 0x1,
-+} PERFCOUNTER_OFF_MASK;
-+typedef enum PERFCOUNTER_ACTIVE {
-+	PERFCOUNTER_IS_IDLE                              = 0x0,
-+	PERFCOUNTER_IS_ACTIVE                            = 0x1,
-+} PERFCOUNTER_ACTIVE;
-+typedef enum PERFCOUNTER_INT_TYPE {
-+	PERFCOUNTER_INT_TYPE_LEVEL                       = 0x0,
-+	PERFCOUNTER_INT_TYPE_PULSE                       = 0x1,
-+} PERFCOUNTER_INT_TYPE;
-+typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
-+	PERFCOUNTER_COUNTED_VALUE_TYPE_ACC               = 0x0,
-+	PERFCOUNTER_COUNTED_VALUE_TYPE_MAX               = 0x1,
-+} PERFCOUNTER_COUNTED_VALUE_TYPE;
-+typedef enum PERFCOUNTER_CNTL_SEL {
-+	PERFCOUNTER_CNTL_SEL_0                           = 0x0,
-+	PERFCOUNTER_CNTL_SEL_1                           = 0x1,
-+	PERFCOUNTER_CNTL_SEL_2                           = 0x2,
-+	PERFCOUNTER_CNTL_SEL_3                           = 0x3,
-+	PERFCOUNTER_CNTL_SEL_4                           = 0x4,
-+	PERFCOUNTER_CNTL_SEL_5                           = 0x5,
-+	PERFCOUNTER_CNTL_SEL_6                           = 0x6,
-+	PERFCOUNTER_CNTL_SEL_7                           = 0x7,
-+} PERFCOUNTER_CNTL_SEL;
-+typedef enum PERFCOUNTER_CNT0_STATE {
-+	PERFCOUNTER_CNT0_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT0_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT0_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT0_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT0_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL0 {
-+	PERFCOUNTER_STATE_SEL0_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL0_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL0;
-+typedef enum PERFCOUNTER_CNT1_STATE {
-+	PERFCOUNTER_CNT1_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT1_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT1_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT1_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT1_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL1 {
-+	PERFCOUNTER_STATE_SEL1_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL1_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL1;
-+typedef enum PERFCOUNTER_CNT2_STATE {
-+	PERFCOUNTER_CNT2_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT2_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT2_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT2_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT2_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL2 {
-+	PERFCOUNTER_STATE_SEL2_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL2_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL2;
-+typedef enum PERFCOUNTER_CNT3_STATE {
-+	PERFCOUNTER_CNT3_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT3_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT3_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT3_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT3_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL3 {
-+	PERFCOUNTER_STATE_SEL3_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL3_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL3;
-+typedef enum PERFCOUNTER_CNT4_STATE {
-+	PERFCOUNTER_CNT4_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT4_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT4_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT4_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT4_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL4 {
-+	PERFCOUNTER_STATE_SEL4_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL4_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL4;
-+typedef enum PERFCOUNTER_CNT5_STATE {
-+	PERFCOUNTER_CNT5_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT5_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT5_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT5_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT5_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL5 {
-+	PERFCOUNTER_STATE_SEL5_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL5_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL5;
-+typedef enum PERFCOUNTER_CNT6_STATE {
-+	PERFCOUNTER_CNT6_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT6_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT6_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT6_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT6_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL6 {
-+	PERFCOUNTER_STATE_SEL6_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL6_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL6;
-+typedef enum PERFCOUNTER_CNT7_STATE {
-+	PERFCOUNTER_CNT7_STATE_RESET                     = 0x0,
-+	PERFCOUNTER_CNT7_STATE_START                     = 0x1,
-+	PERFCOUNTER_CNT7_STATE_FREEZE                    = 0x2,
-+	PERFCOUNTER_CNT7_STATE_HW                        = 0x3,
-+} PERFCOUNTER_CNT7_STATE;
-+typedef enum PERFCOUNTER_STATE_SEL7 {
-+	PERFCOUNTER_STATE_SEL7_GLOBAL                    = 0x0,
-+	PERFCOUNTER_STATE_SEL7_LOCAL                     = 0x1,
-+} PERFCOUNTER_STATE_SEL7;
-+typedef enum PERFMON_STATE {
-+	PERFMON_STATE_RESET                              = 0x0,
-+	PERFMON_STATE_START                              = 0x1,
-+	PERFMON_STATE_FREEZE                             = 0x2,
-+	PERFMON_STATE_HW                                 = 0x3,
-+} PERFMON_STATE;
-+typedef enum PERFMON_CNTOFF_AND_OR {
-+	PERFMON_CNTOFF_OR                                = 0x0,
-+	PERFMON_CNTOFF_AND                               = 0x1,
-+} PERFMON_CNTOFF_AND_OR;
-+typedef enum PERFMON_CNTOFF_INT_EN {
-+	PERFMON_CNTOFF_INT_DISABLE                       = 0x0,
-+	PERFMON_CNTOFF_INT_ENABLE                        = 0x1,
-+} PERFMON_CNTOFF_INT_EN;
-+typedef enum PERFMON_CNTOFF_INT_TYPE {
-+	PERFMON_CNTOFF_INT_TYPE_LEVEL                    = 0x0,
-+	PERFMON_CNTOFF_INT_TYPE_PULSE                    = 0x1,
-+} PERFMON_CNTOFF_INT_TYPE;
-+typedef enum ENABLE {
-+	DISABLE_THE_FEATURE                              = 0x0,
-+	ENABLE_THE_FEATURE                               = 0x1,
-+} ENABLE;
-+typedef enum ENABLE_CLOCK {
-+	DISABLE_THE_CLOCK                                = 0x0,
-+	ENABLE_THE_CLOCK                                 = 0x1,
-+} ENABLE_CLOCK;
-+typedef enum FORCE_VBI {
-+	FORCE_VBI_LOW                                    = 0x0,
-+	FORCE_VBI_HIGH                                   = 0x1,
-+} FORCE_VBI;
-+typedef enum OVERRIDE_CGTT_SCLK {
-+	OVERRIDE_CGTT_SCLK_NOOP                          = 0x0,
-+	SET_OVERRIDE_CGTT_SCLK                           = 0x1,
-+} OVERRIDE_CGTT_SCLK;
-+typedef enum CLEAR_SMU_INTR {
-+	SMU_INTR_STATUS_NOOP                             = 0x0,
-+	SMU_INTR_STATUS_CLEAR                            = 0x1,
-+} CLEAR_SMU_INTR;
-+typedef enum STATIC_SCREEN_SMU_INTR {
-+	STATIC_SCREEN_SMU_INTR_NOOP                      = 0x0,
-+	SET_STATIC_SCREEN_SMU_INTR                       = 0x1,
-+} STATIC_SCREEN_SMU_INTR;
-+typedef enum JITTER_REMOVE_DISABLE {
-+	ENABLE_JITTER_REMOVAL                            = 0x0,
-+	DISABLE_JITTER_REMOVAL                           = 0x1,
-+} JITTER_REMOVE_DISABLE;
-+typedef enum DISABLE_CLOCK_GATING {
-+	CLOCK_GATING_ENABLED                             = 0x0,
-+	CLOCK_GATING_DISABLED                            = 0x1,
-+} DISABLE_CLOCK_GATING;
-+typedef enum DISABLE_CLOCK_GATING_IN_DCO {
-+	CLOCK_GATING_ENABLED_IN_DCO                      = 0x0,
-+	CLOCK_GATING_DISABLED_IN_DCO                     = 0x1,
-+} DISABLE_CLOCK_GATING_IN_DCO;
-+typedef enum DCCG_DEEP_COLOR_CNTL {
-+	DCCG_DEEP_COLOR_DTO_DISABLE                      = 0x0,
-+	DCCG_DEEP_COLOR_DTO_5_4_RATIO                    = 0x1,
-+	DCCG_DEEP_COLOR_DTO_3_2_RATIO                    = 0x2,
-+	DCCG_DEEP_COLOR_DTO_2_1_RATIO                    = 0x3,
-+} DCCG_DEEP_COLOR_CNTL;
-+typedef enum REFCLK_CLOCK_EN {
-+	REFCLK_CLOCK_EN_PCIE_REFCLK                      = 0x0,
-+	REFCLK_CLOCK_EN_ALLOW_SRC                        = 0x1,
-+} REFCLK_CLOCK_EN;
-+typedef enum REFCLK_SRC_SEL {
-+	REFCLK_SRC_SEL_XTALIN                            = 0x0,
-+	REFCLK_SRC_SEL_DISPPLL                           = 0x1,
-+} REFCLK_SRC_SEL;
-+typedef enum DPREFCLK_SRC_SEL {
-+	DPREFCLK_SRC_SEL_CK                              = 0x0,
-+	DPREFCLK_SRC_SEL_P0PLL                           = 0x1,
-+	DPREFCLK_SRC_SEL_P1PLL                           = 0x2,
-+	DPREFCLK_SRC_SEL_P2PLL                           = 0x3,
-+	DPREFCLK_SRC_SEL_P3PLL                           = 0x4,
-+} DPREFCLK_SRC_SEL;
-+typedef enum XTAL_REF_SEL {
-+	XTAL_REF_SEL_1X                                  = 0x0,
-+	XTAL_REF_SEL_2X                                  = 0x1,
-+} XTAL_REF_SEL;
-+typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
-+	XTAL_REF_CLOCK_SOURCE_SEL_XTALIN                 = 0x0,
-+	XTAL_REF_CLOCK_SOURCE_SEL_PPLL                   = 0x1,
-+} XTAL_REF_CLOCK_SOURCE_SEL;
-+typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
-+	MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN            = 0x0,
-+	MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK       = 0x1,
-+} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
-+typedef enum ALLOW_SR_ON_TRANS_REQ {
-+	ALLOW_SR_ON_TRANS_REQ_ENABLE                     = 0x0,
-+	ALLOW_SR_ON_TRANS_REQ_DISABLE                    = 0x1,
-+} ALLOW_SR_ON_TRANS_REQ;
-+typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
-+	MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN            = 0x0,
-+	MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK       = 0x1,
-+} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
-+typedef enum PIPE_PIXEL_RATE_SOURCE {
-+	PIPE_PIXEL_RATE_SOURCE_P0PLL                     = 0x0,
-+	PIPE_PIXEL_RATE_SOURCE_P1PLL                     = 0x1,
-+	PIPE_PIXEL_RATE_SOURCE_P2PLL                     = 0x2,
-+} PIPE_PIXEL_RATE_SOURCE;
-+typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA            = 0x0,
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB            = 0x1,
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC            = 0x2,
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD            = 0x3,
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE            = 0x4,
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF            = 0x5,
-+	PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG            = 0x6,
-+} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
-+typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
-+	PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL                = 0x0,
-+	PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL               = 0x1,
-+} PIPE_PIXEL_RATE_PLL_SOURCE;
-+typedef enum DP_DTO_DS_DISABLE {
-+	DP_DTO_DESPREAD_DISABLE                          = 0x0,
-+	DP_DTO_DESPREAD_ENABLE                           = 0x1,
-+} DP_DTO_DS_DISABLE;
-+typedef enum CRTC_ADD_PIXEL {
-+	CRTC_ADD_PIXEL_NOOP                              = 0x0,
-+	CRTC_ADD_PIXEL_FORCE                             = 0x1,
-+} CRTC_ADD_PIXEL;
-+typedef enum CRTC_DROP_PIXEL {
-+	CRTC_DROP_PIXEL_NOOP                             = 0x0,
-+	CRTC_DROP_PIXEL_FORCE                            = 0x1,
-+} CRTC_DROP_PIXEL;
-+typedef enum SYMCLK_FE_FORCE_EN {
-+	SYMCLK_FE_FORCE_EN_DISABLE                       = 0x0,
-+	SYMCLK_FE_FORCE_EN_ENABLE                        = 0x1,
-+} SYMCLK_FE_FORCE_EN;
-+typedef enum SYMCLK_FE_FORCE_SRC {
-+	SYMCLK_FE_FORCE_SRC_UNIPHYA                      = 0x0,
-+	SYMCLK_FE_FORCE_SRC_UNIPHYB                      = 0x1,
-+	SYMCLK_FE_FORCE_SRC_UNIPHYC                      = 0x2,
-+	SYMCLK_FE_FORCE_SRC_UNIPHYD                      = 0x3,
-+	SYMCLK_FE_FORCE_SRC_UNIPHYE                      = 0x4,
-+	SYMCLK_FE_FORCE_SRC_UNIPHYF                      = 0x5,
-+	SYMCLK_FE_FORCE_SRC_UNIPHYG                      = 0x6,
-+} SYMCLK_FE_FORCE_SRC;
-+typedef enum DPDBG_CLK_FORCE_EN {
-+	DPDBG_CLK_FORCE_EN_DISABLE                       = 0x0,
-+	DPDBG_CLK_FORCE_EN_ENABLE                        = 0x1,
-+} DPDBG_CLK_FORCE_EN;
-+typedef enum DVOACLK_COARSE_SKEW_CNTL {
-+	DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT           = 0x0,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP            = 0x1,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS           = 0x2,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS           = 0x3,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS           = 0x4,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS           = 0x5,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS           = 0x6,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS           = 0x7,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS           = 0x8,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS           = 0x9,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS          = 0xa,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS          = 0xb,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS          = 0xc,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS          = 0xd,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS          = 0xe,
-+	DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS          = 0xf,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP            = 0x10,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS           = 0x11,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS           = 0x12,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS           = 0x13,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS           = 0x14,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS           = 0x15,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS           = 0x16,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS           = 0x17,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS           = 0x18,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS          = 0x19,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS          = 0x1a,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS          = 0x1b,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS          = 0x1c,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS          = 0x1d,
-+	DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS          = 0x1e,
-+} DVOACLK_COARSE_SKEW_CNTL;
-+typedef enum DVOACLK_FINE_SKEW_CNTL {
-+	DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT             = 0x0,
-+	DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP              = 0x1,
-+	DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS             = 0x2,
-+	DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS             = 0x3,
-+	DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP              = 0x4,
-+	DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS             = 0x5,
-+	DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS             = 0x6,
-+	DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS             = 0x7,
-+} DVOACLK_FINE_SKEW_CNTL;
-+typedef enum DVOACLKD_IN_PHASE {
-+	DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO         = 0x0,
-+	DVOACLKD_IN_PHASE_WITH_PCLK_DVO                  = 0x1,
-+} DVOACLKD_IN_PHASE;
-+typedef enum DVOACLKC_IN_PHASE {
-+	DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO         = 0x0,
-+	DVOACLKC_IN_PHASE_WITH_PCLK_DVO                  = 0x1,
-+} DVOACLKC_IN_PHASE;
-+typedef enum DVOACLKC_MVP_IN_PHASE {
-+	DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO     = 0x0,
-+	DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO              = 0x1,
-+} DVOACLKC_MVP_IN_PHASE;
-+typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
-+	DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE         = 0x0,
-+	DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE          = 0x1,
-+} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
-+typedef enum MVP_CLK_SRC_SEL {
-+	MVP_CLK_SRC_SEL_RSRV                             = 0x0,
-+	MVP_CLK_SRC_SEL_IO_1                             = 0x1,
-+	MVP_CLK_SRC_SEL_IO_2                             = 0x2,
-+	MVP_CLK_SRC_SEL_REFCLK                           = 0x3,
-+} MVP_CLK_SRC_SEL;
-+typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0                 = 0x0,
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1                 = 0x1,
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2                 = 0x2,
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3                 = 0x3,
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4                 = 0x4,
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5                 = 0x5,
-+	DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED              = 0x6,
-+} DCCG_AUDIO_DTO0_SOURCE_SEL;
-+typedef enum DCCG_AUDIO_DTO_SEL {
-+	DCCG_AUDIO_DTO_SEL_AUDIO_DTO0                    = 0x0,
-+	DCCG_AUDIO_DTO_SEL_AUDIO_DTO1                    = 0x1,
-+	DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO                  = 0x2,
-+} DCCG_AUDIO_DTO_SEL;
-+typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
-+	DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0                = 0x0,
-+	DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1                = 0x1,
-+} DCCG_AUDIO_DTO2_SOURCE_SEL;
-+typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
-+	DCCG_AUDIO_DTO_USE_128FBR_FOR_DP                 = 0x0,
-+	DCCG_AUDIO_DTO_USE_512FBR_FOR_DP                 = 0x1,
-+} DCCG_AUDIO_DTO_USE_512FBR_DTO;
-+typedef enum DCCG_DBG_EN {
-+	DCCG_DBG_EN_DISABLE                              = 0x0,
-+	DCCG_DBG_EN_ENABLE                               = 0x1,
-+} DCCG_DBG_EN;
-+typedef enum DCCG_DBG_BLOCK_SEL {
-+	DCCG_DBG_BLOCK_SEL_DCCG                          = 0x0,
-+	DCCG_DBG_BLOCK_SEL_PMON                          = 0x1,
-+	DCCG_DBG_BLOCK_SEL_PMON2                         = 0x2,
-+} DCCG_DBG_BLOCK_SEL;
-+typedef enum DCCG_DBG_CLOCK_SEL {
-+	DCCG_DBG_CLOCK_SEL_DISPCLK                       = 0x0,
-+	DCCG_DBG_CLOCK_SEL_SCLK                          = 0x1,
-+	DCCG_DBG_CLOCK_SEL_MVPCLK                        = 0x2,
-+	DCCG_DBG_CLOCK_SEL_DVOCLK                        = 0x3,
-+	DCCG_DBG_CLOCK_SEL_DACCLK                        = 0x4,
-+	DCCG_DBG_CLOCK_SEL_REFCLK                        = 0x5,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKA                       = 0x6,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKB                       = 0x7,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKC                       = 0x8,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKD                       = 0x9,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKE                       = 0xa,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKG                       = 0xb,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKF                       = 0xc,
-+	DCCG_DBG_CLOCK_SEL_RSRV                          = 0xd,
-+	DCCG_DBG_CLOCK_SEL_AOMCLK0                       = 0xe,
-+	DCCG_DBG_CLOCK_SEL_AOMCLK1                       = 0xf,
-+	DCCG_DBG_CLOCK_SEL_AOMCLK2                       = 0x10,
-+	DCCG_DBG_CLOCK_SEL_DPREFCLK                      = 0x11,
-+	DCCG_DBG_CLOCK_SEL_UNB_DB_CLK                    = 0x12,
-+	DCCG_DBG_CLOCK_SEL_DSICLK                        = 0x13,
-+	DCCG_DBG_CLOCK_SEL_BYTECLK                       = 0x14,
-+	DCCG_DBG_CLOCK_SEL_ESCCLK                        = 0x15,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKLPA                     = 0x16,
-+	DCCG_DBG_CLOCK_SEL_SYMCLKLPB                     = 0x17,
-+} DCCG_DBG_CLOCK_SEL;
-+typedef enum DCCG_DBG_OUT_BLOCK_SEL {
-+	DCCG_DBG_OUT_BLOCK_SEL_DCCG                      = 0x0,
-+	DCCG_DBG_OUT_BLOCK_SEL_DCO                       = 0x1,
-+	DCCG_DBG_OUT_BLOCK_SEL_DCIO                      = 0x2,
-+	DCCG_DBG_OUT_BLOCK_SEL_DSI                       = 0x3,
-+} DCCG_DBG_OUT_BLOCK_SEL;
-+typedef enum DISPCLK_FREQ_RAMP_DONE {
-+	DISPCLK_FREQ_RAMP_IN_PROGRESS                    = 0x0,
-+	DISPCLK_FREQ_RAMP_COMPLETED                      = 0x1,
-+} DISPCLK_FREQ_RAMP_DONE;
-+typedef enum DCCG_FIFO_ERRDET_RESET {
-+	DCCG_FIFO_ERRDET_RESET_NOOP                      = 0x0,
-+	DCCG_FIFO_ERRDET_RESET_FORCE                     = 0x1,
-+} DCCG_FIFO_ERRDET_RESET;
-+typedef enum DCCG_FIFO_ERRDET_STATE {
-+	DCCG_FIFO_ERRDET_STATE_DETECTION                 = 0x0,
-+	DCCG_FIFO_ERRDET_STATE_CALIBRATION               = 0x1,
-+} DCCG_FIFO_ERRDET_STATE;
-+typedef enum DCCG_FIFO_ERRDET_OVR_EN {
-+	DCCG_FIFO_ERRDET_OVR_DISABLE                     = 0x0,
-+	DCCG_FIFO_ERRDET_OVR_ENABLE                      = 0x1,
-+} DCCG_FIFO_ERRDET_OVR_EN;
-+typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
-+	DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING         = 0x0,
-+	DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING        = 0x1,
-+} DISPCLK_CHG_FWD_CORR_DISABLE;
-+typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
-+	DC_MEM_GLOBAL_PWR_REQ_ENABLE                     = 0x0,
-+	DC_MEM_GLOBAL_PWR_REQ_DISABLE                    = 0x1,
-+} DC_MEM_GLOBAL_PWR_REQ_DIS;
-+typedef enum DCCG_PERF_RUN {
-+	DCCG_PERF_RUN_NOOP                               = 0x0,
-+	DCCG_PERF_RUN_START                              = 0x1,
-+} DCCG_PERF_RUN;
-+typedef enum DCCG_PERF_MODE_VSYNC {
-+	DCCG_PERF_MODE_VSYNC_NOOP                        = 0x0,
-+	DCCG_PERF_MODE_VSYNC_START                       = 0x1,
-+} DCCG_PERF_MODE_VSYNC;
-+typedef enum DCCG_PERF_MODE_HSYNC {
-+	DCCG_PERF_MODE_HSYNC_NOOP                        = 0x0,
-+	DCCG_PERF_MODE_HSYNC_START                       = 0x1,
-+} DCCG_PERF_MODE_HSYNC;
-+typedef enum DCCG_PERF_CRTC_SELECT {
-+	DCCG_PERF_SEL_CRTC0                              = 0x0,
-+	DCCG_PERF_SEL_CRTC1                              = 0x1,
-+	DCCG_PERF_SEL_CRTC2                              = 0x2,
-+	DCCG_PERF_SEL_CRTC3                              = 0x3,
-+	DCCG_PERF_SEL_CRTC4                              = 0x4,
-+	DCCG_PERF_SEL_CRTC5                              = 0x5,
-+} DCCG_PERF_CRTC_SELECT;
-+typedef enum CLOCK_BRANCH_SOFT_RESET {
-+	CLOCK_BRANCH_SOFT_RESET_NOOP                     = 0x0,
-+	CLOCK_BRANCH_SOFT_RESET_FORCE                    = 0x1,
-+} CLOCK_BRANCH_SOFT_RESET;
-+typedef enum PLL_CFG_IF_SOFT_RESET {
-+	PLL_CFG_IF_SOFT_RESET_NOOP                       = 0x0,
-+	PLL_CFG_IF_SOFT_RESET_FORCE                      = 0x1,
-+} PLL_CFG_IF_SOFT_RESET;
-+typedef enum DVO_ENABLE_RST {
-+	DVO_ENABLE_RST_DISABLE                           = 0x0,
-+	DVO_ENABLE_RST_ENABLE                            = 0x1,
-+} DVO_ENABLE_RST;
-+typedef enum LptNumBanks {
-+	LPT_NUM_BANKS_2BANK                              = 0x0,
-+	LPT_NUM_BANKS_4BANK                              = 0x1,
-+	LPT_NUM_BANKS_8BANK                              = 0x2,
-+	LPT_NUM_BANKS_16BANK                             = 0x3,
-+	LPT_NUM_BANKS_32BANK                             = 0x4,
-+} LptNumBanks;
-+typedef enum DCIO_DC_GENERICA_SEL {
-+	DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
-+	DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
-+	DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
-+	DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
-+	DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
-+	DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
-+	DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
-+	DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
-+	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
-+	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
-+	DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
-+	DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
-+	DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
-+	DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
-+	DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
-+	DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
-+	DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
-+	DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
-+} DCIO_DC_GENERICA_SEL;
-+typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
-+	DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
-+	DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
-+	DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
-+	DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
-+	DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
-+	DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
-+	DCIO_UNIPHYG_TEST_REFDIV_CLK                     = 0x6,
-+	DCIO_UNIPHYLPA_TEST_REFDIV_CLK                   = 0x7,
-+	DCIO_UNIPHYLPB_TEST_REFDIV_CLK                   = 0x8,
-+} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
-+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
-+	DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
-+	DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
-+	DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
-+	DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
-+	DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
-+	DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
-+	DCIO_UNIPHYG_FBDIV_CLK                           = 0x6,
-+	DCIO_UNIPHYLPA_FBDIV_CLK                         = 0x7,
-+	DCIO_UNIPHYLPB_FBDIV_CLK                         = 0x8,
-+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
-+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
-+	DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
-+	DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
-+	DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
-+	DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
-+	DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
-+	DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
-+	DCIO_UNIPHYG_FBDIV_SSC_CLK                       = 0x6,
-+	DCIO_UNIPHYLPA_FBDIV_SSC_CLK                     = 0x7,
-+	DCIO_UNIPHYLPB_FBDIV_SSC_CLK                     = 0x8,
-+} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
-+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
-+	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
-+	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
-+	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
-+	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
-+	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
-+	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
-+	DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2                 = 0x6,
-+	DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2               = 0x7,
-+	DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2               = 0x8,
-+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
-+typedef enum DCIO_DC_GENERICB_SEL {
-+	DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
-+	DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
-+	DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
-+	DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
-+	DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
-+	DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
-+	DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
-+	DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
-+	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
-+	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
-+	DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
-+	DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
-+	DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
-+	DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
-+	DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
-+	DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
-+} DCIO_DC_GENERICB_SEL;
-+typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
-+	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,
-+} DCIO_DC_PAD_EXTERN_SIG_SEL;
-+typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
-+	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA                 = 0x0,
-+	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE       = 0x1,
-+	DCIO_MVP_PIXEL_SRC_STATUS_CRTC                   = 0x2,
-+	DCIO_MVP_PIXEL_SRC_STATUS_LB                     = 0x3,
-+} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
-+typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
-+	DCIO_HSYNCA_OUTPUT_SEL_DISABLE                   = 0x0,
-+	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
-+	DCIO_HSYNCA_OUTPUT_SEL_PPLL2                     = 0x2,
-+	DCIO_HSYNCA_OUTPUT_SEL_RESERVED                  = 0x3,
-+} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
-+typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
-+	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE                = 0x0,
-+	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1                  = 0x1,
-+	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
-+	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3        = 0x3,
-+} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
-+typedef enum DCIO_DC_GPIO_VIP_DEBUG {
-+	DCIO_DC_GPIO_VIP_DEBUG_NORMAL                    = 0x0,
-+	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG                    = 0x1,
-+} DCIO_DC_GPIO_VIP_DEBUG;
-+typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
-+	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL                  = 0x0,
-+	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF                = 0x1,
-+	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2         = 0x2,
-+	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3         = 0x3,
-+} DCIO_DC_GPIO_MACRO_DEBUG;
-+typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
-+	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL       = 0x0,
-+	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP         = 0x1,
-+} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
-+typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
-+	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS            = 0x0,
-+	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE            = 0x1,
-+} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
-+typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
-+	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL                 = 0x0,
-+	DCIO_DPRX_LOOPBACK_ENABLE_LOOP                   = 0x1,
-+} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
-+typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
-+	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
-+} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
-+typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
-+	DCIO_UNIPHY_CHANNEL_NO_INVERSION                 = 0x0,
-+	DCIO_UNIPHY_CHANNEL_INVERTED                     = 0x1,
-+} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
-+typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
-+	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW        = 0x0,
-+	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW           = 0x1,
-+	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
-+	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
-+} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
-+typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
-+	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0              = 0x0,
-+	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1              = 0x1,
-+	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2              = 0x2,
-+	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3              = 0x3,
-+} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
-+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
-+	DCIO_VIP_MUX_EN_DVO                              = 0x0,
-+	DCIO_VIP_MUX_EN_VIP                              = 0x1,
-+} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
-+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
-+	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT                = 0x0,
-+	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
-+} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
-+typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
-+	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT                = 0x0,
-+	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
-+} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
-+	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
-+	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
-+	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF           = 0x0,
-+	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON            = 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
-+	DCIO_LVTMA_SYNCEN_POL_NON_INVERT                 = 0x0,
-+	DCIO_LVTMA_SYNCEN_POL_INVERT                     = 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
-+	DCIO_LVTMA_DIGON_OFF                             = 0x0,
-+	DCIO_LVTMA_DIGON_ON                              = 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
-+	DCIO_LVTMA_DIGON_POL_NON_INVERT                  = 0x0,
-+	DCIO_LVTMA_DIGON_POL_INVERT                      = 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
-+	DCIO_LVTMA_BLON_OFF                              = 0x0,
-+	DCIO_LVTMA_BLON_ON                               = 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
-+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
-+	DCIO_LVTMA_BLON_POL_NON_INVERT                   = 0x0,
-+	DCIO_LVTMA_BLON_POL_INVERT                       = 0x1,
-+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
-+typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
-+	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON              = 0x0,
-+	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE          = 0x1,
-+} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
-+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
-+	DCIO_BL_PWM_FRACTIONAL_DISABLE                   = 0x0,
-+	DCIO_BL_PWM_FRACTIONAL_ENABLE                    = 0x1,
-+} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
-+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
-+	DCIO_BL_PWM_DISABLE                              = 0x0,
-+	DCIO_BL_PWM_ENABLE                               = 0x1,
-+} DCIO_BL_PWM_CNTL_BL_PWM_EN;
-+typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
-+	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL       = 0x0,
-+	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1       = 0x1,
-+	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2       = 0x2,
-+	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3       = 0x3,
-+} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
-+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
-+	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE              = 0x0,
-+	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE               = 0x1,
-+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
-+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
-+	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL      = 0x0,
-+	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM         = 0x1,
-+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
-+typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
-+	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE                = 0x0,
-+	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE                 = 0x1,
-+} DCIO_BL_PWM_GRP1_REG_LOCK;
-+typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
-+	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE   = 0x0,
-+	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE    = 0x1,
-+} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
-+typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
-+	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
-+	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
-+	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
-+	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
-+	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
-+	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
-+} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
-+typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
-+	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
-+	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
-+} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
-+typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
-+	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE       = 0x0,
-+	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE      = 0x1,
-+} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
-+typedef enum DCIO_GSL_SEL {
-+	DCIO_GSL_SEL_GROUP_0                             = 0x0,
-+	DCIO_GSL_SEL_GROUP_1                             = 0x1,
-+	DCIO_GSL_SEL_GROUP_2                             = 0x2,
-+} DCIO_GSL_SEL;
-+typedef enum DCIO_GENLK_CLK_GSL_MASK {
-+	DCIO_GENLK_CLK_GSL_MASK_NO                       = 0x0,
-+	DCIO_GENLK_CLK_GSL_MASK_TIMING                   = 0x1,
-+	DCIO_GENLK_CLK_GSL_MASK_STEREO                   = 0x2,
-+} DCIO_GENLK_CLK_GSL_MASK;
-+typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
-+	DCIO_GENLK_VSYNC_GSL_MASK_NO                     = 0x0,
-+	DCIO_GENLK_VSYNC_GSL_MASK_TIMING                 = 0x1,
-+	DCIO_GENLK_VSYNC_GSL_MASK_STEREO                 = 0x2,
-+} DCIO_GENLK_VSYNC_GSL_MASK;
-+typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
-+	DCIO_SWAPLOCK_A_GSL_MASK_NO                      = 0x0,
-+	DCIO_SWAPLOCK_A_GSL_MASK_TIMING                  = 0x1,
-+	DCIO_SWAPLOCK_A_GSL_MASK_STEREO                  = 0x2,
-+} DCIO_SWAPLOCK_A_GSL_MASK;
-+typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
-+	DCIO_SWAPLOCK_B_GSL_MASK_NO                      = 0x0,
-+	DCIO_SWAPLOCK_B_GSL_MASK_TIMING                  = 0x1,
-+	DCIO_SWAPLOCK_B_GSL_MASK_STEREO                  = 0x2,
-+} DCIO_SWAPLOCK_B_GSL_MASK;
-+typedef enum DCIO_GSL_VSYNC_SEL {
-+	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
-+	DCIO_GSL_VSYNC_SEL_PIPE1                         = 0x1,
-+	DCIO_GSL_VSYNC_SEL_PIPE2                         = 0x2,
-+	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
-+	DCIO_GSL_VSYNC_SEL_PIPE4                         = 0x4,
-+	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
-+} DCIO_GSL_VSYNC_SEL;
-+typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
-+	DCIO_GSL0_TIMING_SYNC_SEL_PIPE                   = 0x0,
-+	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
-+	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
-+	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
-+	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
-+} DCIO_GSL0_TIMING_SYNC_SEL;
-+typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
-+	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
-+	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
-+	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
-+	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
-+	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
-+} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
-+typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
-+	DCIO_GSL1_TIMING_SYNC_SEL_PIPE                   = 0x0,
-+	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
-+	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
-+	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
-+	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
-+} DCIO_GSL1_TIMING_SYNC_SEL;
-+typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
-+	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
-+	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
-+	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
-+	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
-+	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
-+} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
-+typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
-+	DCIO_GSL2_TIMING_SYNC_SEL_PIPE                   = 0x0,
-+	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
-+	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
-+	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
-+	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
-+} DCIO_GSL2_TIMING_SYNC_SEL;
-+typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
-+	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
-+	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
-+	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
-+	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
-+	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
-+} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
-+typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
-+	DCIO_GPU_TIMER_START_0_END_27                    = 0x0,
-+	DCIO_GPU_TIMER_START_1_END_28                    = 0x1,
-+	DCIO_GPU_TIMER_START_2_END_29                    = 0x2,
-+	DCIO_GPU_TIMER_START_3_END_30                    = 0x3,
-+	DCIO_GPU_TIMER_START_4_END_31                    = 0x4,
-+	DCIO_GPU_TIMER_START_6_END_33                    = 0x5,
-+	DCIO_GPU_TIMER_START_8_END_35                    = 0x6,
-+	DCIO_GPU_TIMER_START_10_END_37                   = 0x7,
-+} DCIO_DC_GPU_TIMER_START_POSITION;
-+typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
-+	DCIO_TEST_CLK_SEL_DISPCLK                        = 0x0,
-+	DCIO_TEST_CLK_SEL_GATED_DISPCLK                  = 0x1,
-+	DCIO_TEST_CLK_SEL_SCLK                           = 0x2,
-+} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
-+typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
-+	DCIO_DISPCLK_R_DCIO_GATE_DISABLE                 = 0x0,
-+	DCIO_DISPCLK_R_DCIO_GATE_ENABLE                  = 0x1,
-+} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
-+typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
-+	DCIO_EXT_VSYNC_MUX_SWAPLOCKB                     = 0x0,
-+	DCIO_EXT_VSYNC_MUX_CRTC0                         = 0x1,
-+	DCIO_EXT_VSYNC_MUX_CRTC1                         = 0x2,
-+	DCIO_EXT_VSYNC_MUX_CRTC2                         = 0x3,
-+	DCIO_EXT_VSYNC_MUX_CRTC3                         = 0x4,
-+	DCIO_EXT_VSYNC_MUX_CRTC4                         = 0x5,
-+	DCIO_EXT_VSYNC_MUX_CRTC5                         = 0x6,
-+	DCIO_EXT_VSYNC_MUX_GENERICB                      = 0x7,
-+} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
-+typedef enum DCIO_DCO_EXT_VSYNC_MASK {
-+	DCIO_EXT_VSYNC_MASK_NONE                         = 0x0,
-+	DCIO_EXT_VSYNC_MASK_PIPE0                        = 0x1,
-+	DCIO_EXT_VSYNC_MASK_PIPE1                        = 0x2,
-+	DCIO_EXT_VSYNC_MASK_PIPE2                        = 0x3,
-+	DCIO_EXT_VSYNC_MASK_PIPE3                        = 0x4,
-+	DCIO_EXT_VSYNC_MASK_PIPE4                        = 0x5,
-+	DCIO_EXT_VSYNC_MASK_PIPE5                        = 0x6,
-+	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE               = 0x7,
-+} DCIO_DCO_EXT_VSYNC_MASK;
-+typedef enum DCIO_DBG_OUT_PIN_SEL {
-+	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT                   = 0x0,
-+	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT                  = 0x1,
-+} DCIO_DBG_OUT_PIN_SEL;
-+typedef enum DCIO_DBG_OUT_12BIT_SEL {
-+	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT                 = 0x0,
-+	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT                 = 0x1,
-+	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT                = 0x2,
-+	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE                  = 0x3,
-+} DCIO_DBG_OUT_12BIT_SEL;
-+typedef enum DCIO_DSYNC_SOFT_RESET {
-+	DCIO_DSYNC_SOFT_RESET_DEASSERT                   = 0x0,
-+	DCIO_DSYNC_SOFT_RESET_ASSERT                     = 0x1,
-+} DCIO_DSYNC_SOFT_RESET;
-+typedef enum DCIO_DACA_SOFT_RESET {
-+	DCIO_DACA_SOFT_RESET_DEASSERT                    = 0x0,
-+	DCIO_DACA_SOFT_RESET_ASSERT                      = 0x1,
-+} DCIO_DACA_SOFT_RESET;
-+typedef enum DCIO_DCRXPHY_SOFT_RESET {
-+	DCIO_DCRXPHY_SOFT_RESET_DEASSERT                 = 0x0,
-+	DCIO_DCRXPHY_SOFT_RESET_ASSERT                   = 0x1,
-+} DCIO_DCRXPHY_SOFT_RESET;
-+typedef enum DCIO_DPHY_LANE_SEL {
-+	DCIO_DPHY_LANE_SEL_LANE0                         = 0x0,
-+	DCIO_DPHY_LANE_SEL_LANE1                         = 0x1,
-+	DCIO_DPHY_LANE_SEL_LANE2                         = 0x2,
-+	DCIO_DPHY_LANE_SEL_LANE3                         = 0x3,
-+} DCIO_DPHY_LANE_SEL;
-+typedef enum DCIO_DPCS_INTERRUPT_TYPE {
-+	DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED             = 0x0,
-+	DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED             = 0x1,
-+} DCIO_DPCS_INTERRUPT_TYPE;
-+typedef enum DCIO_DPCS_INTERRUPT_MASK {
-+	DCIO_DPCS_INTERRUPT_DISABLE                      = 0x0,
-+	DCIO_DPCS_INTERRUPT_ENABLE                       = 0x1,
-+} DCIO_DPCS_INTERRUPT_MASK;
-+typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE     = 0x0,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE     = 0x1,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE     = 0x2,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE     = 0x3,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE     = 0x4,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE     = 0x5,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE     = 0x6,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE     = 0x7,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE     = 0x8,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE     = 0x9,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE     = 0xa,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE     = 0xb,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP       = 0xc,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP       = 0xd,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP       = 0xe,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP       = 0xf,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP       = 0x10,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP       = 0x11,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP       = 0x12,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP       = 0x13,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP       = 0x14,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP       = 0x15,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP       = 0x16,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP       = 0x17,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM    = 0x18,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM    = 0x19,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM    = 0x1a,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM    = 0x1b,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM    = 0x1c,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM    = 0x1d,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM    = 0x1e,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM    = 0x1f,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM    = 0x20,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM    = 0x21,
-+	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM    = 0x22,
-+	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM    = 0x23,
-+} DCIO_DC_GPU_TIMER_READ_SELECT;
-+typedef enum DCIO_IMPCAL_STEP_DELAY {
-+	DCIO_IMPCAL_STEP_DELAY_1us                       = 0x0,
-+	DCIO_IMPCAL_STEP_DELAY_2us                       = 0x1,
-+	DCIO_IMPCAL_STEP_DELAY_3us                       = 0x2,
-+	DCIO_IMPCAL_STEP_DELAY_4us                       = 0x3,
-+	DCIO_IMPCAL_STEP_DELAY_5us                       = 0x4,
-+	DCIO_IMPCAL_STEP_DELAY_6us                       = 0x5,
-+	DCIO_IMPCAL_STEP_DELAY_7us                       = 0x6,
-+	DCIO_IMPCAL_STEP_DELAY_8us                       = 0x7,
-+	DCIO_IMPCAL_STEP_DELAY_9us                       = 0x8,
-+	DCIO_IMPCAL_STEP_DELAY_10us                      = 0x9,
-+	DCIO_IMPCAL_STEP_DELAY_11us                      = 0xa,
-+	DCIO_IMPCAL_STEP_DELAY_12us                      = 0xb,
-+	DCIO_IMPCAL_STEP_DELAY_13us                      = 0xc,
-+	DCIO_IMPCAL_STEP_DELAY_14us                      = 0xd,
-+	DCIO_IMPCAL_STEP_DELAY_15us                      = 0xe,
-+	DCIO_IMPCAL_STEP_DELAY_16us                      = 0xf,
-+} DCIO_IMPCAL_STEP_DELAY;
-+typedef enum DCIO_UNIPHY_IMPCAL_SEL {
-+	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE               = 0x0,
-+	DCIO_UNIPHY_IMPCAL_SEL_BINARY                    = 0x1,
-+} DCIO_UNIPHY_IMPCAL_SEL;
-+typedef enum DCIO_DBG_CLOCK_SEL {
-+	DCIO_DBG_CLOCK_SEL_DISPCLK                       = 0x0,
-+	DCIO_DBG_CLOCK_SEL_SYMCLKA                       = 0x1,
-+	DCIO_DBG_CLOCK_SEL_SYMCLKB                       = 0x2,
-+	DCIO_DBG_CLOCK_SEL_SYMCLKC                       = 0x3,
-+	DCIO_DBG_CLOCK_SEL_SYMCLKD                       = 0x4,
-+	DCIO_DBG_CLOCK_SEL_SYMCLKE                       = 0x5,
-+	DCIO_DBG_CLOCK_SEL_SYMCLKF                       = 0x6,
-+	DCIO_DBG_CLOCK_SEL_REFCLK                        = 0xb,
-+} DCIO_DBG_CLOCK_SEL;
-+typedef enum DCIOCHIP_HPD_SEL {
-+	DCIOCHIP_HPD_SEL_ASYNC                           = 0x0,
-+	DCIOCHIP_HPD_SEL_CLOCKED                         = 0x1,
-+} DCIOCHIP_HPD_SEL;
-+typedef enum DCIOCHIP_PAD_MODE {
-+	DCIOCHIP_PAD_MODE_DDC                            = 0x0,
-+	DCIOCHIP_PAD_MODE_DP                             = 0x1,
-+} DCIOCHIP_PAD_MODE;
-+typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
-+	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C                   = 0x0,
-+	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX                   = 0x1,
-+} DCIOCHIP_AUXSLAVE_PAD_MODE;
-+typedef enum DCIOCHIP_INVERT {
-+	DCIOCHIP_POL_NON_INVERT                          = 0x0,
-+	DCIOCHIP_POL_INVERT                              = 0x1,
-+} DCIOCHIP_INVERT;
-+typedef enum DCIOCHIP_PD_EN {
-+	DCIOCHIP_PD_EN_NOTALLOW                          = 0x0,
-+	DCIOCHIP_PD_EN_ALLOW                             = 0x1,
-+} DCIOCHIP_PD_EN;
-+typedef enum DCIOCHIP_GPIO_MASK_EN {
-+	DCIOCHIP_GPIO_MASK_EN_HARDWARE                   = 0x0,
-+	DCIOCHIP_GPIO_MASK_EN_SOFTWARE                   = 0x1,
-+} DCIOCHIP_GPIO_MASK_EN;
-+typedef enum DCIOCHIP_MASK {
-+	DCIOCHIP_MASK_DISABLE                            = 0x0,
-+	DCIOCHIP_MASK_ENABLE                             = 0x1,
-+} DCIOCHIP_MASK;
-+typedef enum DCIOCHIP_GPIO_I2C_MASK {
-+	DCIOCHIP_GPIO_I2C_MASK_DISABLE                   = 0x0,
-+	DCIOCHIP_GPIO_I2C_MASK_ENABLE                    = 0x1,
-+} DCIOCHIP_GPIO_I2C_MASK;
-+typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
-+	DCIOCHIP_GPIO_I2C_DRIVE_LOW                      = 0x0,
-+	DCIOCHIP_GPIO_I2C_DRIVE_HIGH                     = 0x1,
-+} DCIOCHIP_GPIO_I2C_DRIVE;
-+typedef enum DCIOCHIP_GPIO_I2C_EN {
-+	DCIOCHIP_GPIO_I2C_DISABLE                        = 0x0,
-+	DCIOCHIP_GPIO_I2C_ENABLE                         = 0x1,
-+} DCIOCHIP_GPIO_I2C_EN;
-+typedef enum DCIOCHIP_MASK_4BIT {
-+	DCIOCHIP_MASK_4BIT_DISABLE                       = 0x0,
-+	DCIOCHIP_MASK_4BIT_ENABLE                        = 0xf,
-+} DCIOCHIP_MASK_4BIT;
-+typedef enum DCIOCHIP_ENABLE_4BIT {
-+	DCIOCHIP_4BIT_DISABLE                            = 0x0,
-+	DCIOCHIP_4BIT_ENABLE                             = 0xf,
-+} DCIOCHIP_ENABLE_4BIT;
-+typedef enum DCIOCHIP_MASK_5BIT {
-+	DCIOCHIP_MASIK_5BIT_DISABLE                      = 0x0,
-+	DCIOCHIP_MASIK_5BIT_ENABLE                       = 0x1f,
-+} DCIOCHIP_MASK_5BIT;
-+typedef enum DCIOCHIP_ENABLE_5BIT {
-+	DCIOCHIP_5BIT_DISABLE                            = 0x0,
-+	DCIOCHIP_5BIT_ENABLE                             = 0x1f,
-+} DCIOCHIP_ENABLE_5BIT;
-+typedef enum DCIOCHIP_MASK_2BIT {
-+	DCIOCHIP_MASK_2BIT_DISABLE                       = 0x0,
-+	DCIOCHIP_MASK_2BIT_ENABLE                        = 0x3,
-+} DCIOCHIP_MASK_2BIT;
-+typedef enum DCIOCHIP_ENABLE_2BIT {
-+	DCIOCHIP_2BIT_DISABLE                            = 0x0,
-+	DCIOCHIP_2BIT_ENABLE                             = 0x3,
-+} DCIOCHIP_ENABLE_2BIT;
-+typedef enum DCIOCHIP_REF_27_SRC_SEL {
-+	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER             = 0x0,
-+	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER      = 0x1,
-+	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS              = 0x2,
-+	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS       = 0x3,
-+} DCIOCHIP_REF_27_SRC_SEL;
-+typedef enum DCIOCHIP_DVO_VREFPON {
-+	DCIOCHIP_DVO_VREFPON_DISABLE                     = 0x0,
-+	DCIOCHIP_DVO_VREFPON_ENABLE                      = 0x1,
-+} DCIOCHIP_DVO_VREFPON;
-+typedef enum DCIOCHIP_DVO_VREFSEL {
-+	DCIOCHIP_DVO_VREFSEL_ONCHIP                      = 0x0,
-+	DCIOCHIP_DVO_VREFSEL_EXTERNAL                    = 0x1,
-+} DCIOCHIP_DVO_VREFSEL;
-+typedef enum DCIOCHIP_SPDIF1_IMODE {
-+	DCIOCHIP_SPDIF1_IMODE_OE_A                       = 0x0,
-+	DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO                  = 0x1,
-+} DCIOCHIP_SPDIF1_IMODE;
-+typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
-+	DCIOCHIP_AUX_FALLSLEWSEL_LOW                     = 0x0,
-+	DCIOCHIP_AUX_FALLSLEWSEL_HIGH0                   = 0x1,
-+	DCIOCHIP_AUX_FALLSLEWSEL_HIGH1                   = 0x2,
-+	DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH               = 0x3,
-+} DCIOCHIP_AUX_FALLSLEWSEL;
-+typedef enum DCIOCHIP_AUX_SPIKESEL {
-+	DCIOCHIP_AUX_SPIKESEL_50NS                       = 0x0,
-+	DCIOCHIP_AUX_SPIKESEL_10NS                       = 0x1,
-+} DCIOCHIP_AUX_SPIKESEL;
-+typedef enum DCIOCHIP_AUX_CSEL0P9 {
-+	DCIOCHIP_AUX_CSEL_DEC1P0                         = 0x0,
-+	DCIOCHIP_AUX_CSEL_DEC0P9                         = 0x1,
-+} DCIOCHIP_AUX_CSEL0P9;
-+typedef enum DCIOCHIP_AUX_CSEL1P1 {
-+	DCIOCHIP_AUX_CSEL_INC1P0                         = 0x0,
-+	DCIOCHIP_AUX_CSEL_INC1P1                         = 0x1,
-+} DCIOCHIP_AUX_CSEL1P1;
-+typedef enum DCIOCHIP_AUX_RSEL0P9 {
-+	DCIOCHIP_AUX_RSEL_DEC1P0                         = 0x0,
-+	DCIOCHIP_AUX_RSEL_DEC0P9                         = 0x1,
-+} DCIOCHIP_AUX_RSEL0P9;
-+typedef enum DCIOCHIP_AUX_RSEL1P1 {
-+	DCIOCHIP_AUX_RSEL_INC1P0                         = 0x0,
-+	DCIOCHIP_AUX_RSEL_INC1P1                         = 0x1,
-+} DCIOCHIP_AUX_RSEL1P1;
-+typedef enum DCP_GRPH_ENABLE {
-+	DCP_GRPH_ENABLE_FALSE                            = 0x0,
-+	DCP_GRPH_ENABLE_TRUE                             = 0x1,
-+} DCP_GRPH_ENABLE;
-+typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
-+	DCP_GRPH_KEYER_ALPHA_SEL_FALSE                   = 0x0,
-+	DCP_GRPH_KEYER_ALPHA_SEL_TRUE                    = 0x1,
-+} DCP_GRPH_KEYER_ALPHA_SEL;
-+typedef enum DCP_GRPH_DEPTH {
-+	DCP_GRPH_DEPTH_8BPP                              = 0x0,
-+	DCP_GRPH_DEPTH_16BPP                             = 0x1,
-+	DCP_GRPH_DEPTH_32BPP                             = 0x2,
-+	DCP_GRPH_DEPTH_64BPP                             = 0x3,
-+} DCP_GRPH_DEPTH;
-+typedef enum DCP_GRPH_NUM_BANKS {
-+	DCP_GRPH_NUM_BANKS_2BANK                         = 0x0,
-+	DCP_GRPH_NUM_BANKS_4BANK                         = 0x1,
-+	DCP_GRPH_NUM_BANKS_8BANK                         = 0x2,
-+	DCP_GRPH_NUM_BANKS_16BANK                        = 0x3,
-+} DCP_GRPH_NUM_BANKS;
-+typedef enum DCP_GRPH_BANK_WIDTH {
-+	DCP_GRPH_BANK_WIDTH_1                            = 0x0,
-+	DCP_GRPH_BANK_WIDTH_2                            = 0x1,
-+	DCP_GRPH_BANK_WIDTH_4                            = 0x2,
-+	DCP_GRPH_BANK_WIDTH_8                            = 0x3,
-+} DCP_GRPH_BANK_WIDTH;
-+typedef enum DCP_GRPH_FORMAT {
-+	DCP_GRPH_FORMAT_8BPP                             = 0x0,
-+	DCP_GRPH_FORMAT_16BPP                            = 0x1,
-+	DCP_GRPH_FORMAT_32BPP                            = 0x2,
-+	DCP_GRPH_FORMAT_64BPP                            = 0x3,
-+} DCP_GRPH_FORMAT;
-+typedef enum DCP_GRPH_BANK_HEIGHT {
-+	DCP_GRPH_BANK_HEIGHT_1                           = 0x0,
-+	DCP_GRPH_BANK_HEIGHT_2                           = 0x1,
-+	DCP_GRPH_BANK_HEIGHT_4                           = 0x2,
-+	DCP_GRPH_BANK_HEIGHT_8                           = 0x3,
-+} DCP_GRPH_BANK_HEIGHT;
-+typedef enum DCP_GRPH_TILE_SPLIT {
-+	DCP_GRPH_TILE_SPLIT_64B                          = 0x0,
-+	DCP_GRPH_TILE_SPLIT_128B                         = 0x1,
-+	DCP_GRPH_TILE_SPLIT_256B                         = 0x2,
-+	DCP_GRPH_TILE_SPLIT_512B                         = 0x3,
-+	DCP_GRPH_TILE_SPLIT_1B                           = 0x4,
-+	DCP_GRPH_TILE_SPLIT_2B                           = 0x5,
-+	DCP_GRPH_TILE_SPLIT_4B                           = 0x6,
-+} DCP_GRPH_TILE_SPLIT;
-+typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
-+	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE        = 0x0,
-+	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE         = 0x1,
-+} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
-+typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
-+	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE          = 0x0,
-+	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE           = 0x1,
-+} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
-+typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
-+	DCP_GRPH_MACRO_TILE_ASPECT_1                     = 0x0,
-+	DCP_GRPH_MACRO_TILE_ASPECT_2                     = 0x1,
-+	DCP_GRPH_MACRO_TILE_ASPECT_4                     = 0x2,
-+	DCP_GRPH_MACRO_TILE_ASPECT_8                     = 0x3,
-+} DCP_GRPH_MACRO_TILE_ASPECT;
-+typedef enum DCP_GRPH_ARRAY_MODE {
-+	DCP_GRPH_ARRAY_MODE_0                            = 0x0,
-+	DCP_GRPH_ARRAY_MODE_1                            = 0x1,
-+	DCP_GRPH_ARRAY_MODE_2                            = 0x2,
-+	DCP_GRPH_ARRAY_MODE_3                            = 0x3,
-+	DCP_GRPH_ARRAY_MODE_4                            = 0x4,
-+	DCP_GRPH_ARRAY_MODE_7                            = 0x7,
-+	DCP_GRPH_ARRAY_MODE_12                           = 0xc,
-+	DCP_GRPH_ARRAY_MODE_13                           = 0xd,
-+} DCP_GRPH_ARRAY_MODE;
-+typedef enum DCP_GRPH_MICRO_TILE_MODE {
-+	DCP_GRPH_MICRO_TILE_MODE_0                       = 0x0,
-+	DCP_GRPH_MICRO_TILE_MODE_1                       = 0x1,
-+	DCP_GRPH_MICRO_TILE_MODE_2                       = 0x2,
-+	DCP_GRPH_MICRO_TILE_MODE_3                       = 0x3,
-+} DCP_GRPH_MICRO_TILE_MODE;
-+typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
-+	DCP_GRPH_COLOR_EXPANSION_MODE_DEXP               = 0x0,
-+	DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP               = 0x1,
-+} DCP_GRPH_COLOR_EXPANSION_MODE;
-+typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
-+	DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE               = 0x0,
-+	DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE                = 0x1,
-+} DCP_GRPH_LUT_10BIT_BYPASS_EN;
-+typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
-+	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE       = 0x0,
-+	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE        = 0x1,
-+} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
-+typedef enum DCP_GRPH_ENDIAN_SWAP {
-+	DCP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
-+	DCP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
-+	DCP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
-+	DCP_GRPH_ENDIAN_SWAP_8IN64                       = 0x3,
-+} DCP_GRPH_ENDIAN_SWAP;
-+typedef enum DCP_GRPH_RED_CROSSBAR {
-+	DCP_GRPH_RED_CROSSBAR_FROM_R                     = 0x0,
-+	DCP_GRPH_RED_CROSSBAR_FROM_G                     = 0x1,
-+	DCP_GRPH_RED_CROSSBAR_FROM_B                     = 0x2,
-+	DCP_GRPH_RED_CROSSBAR_FROM_A                     = 0x3,
-+} DCP_GRPH_RED_CROSSBAR;
-+typedef enum DCP_GRPH_GREEN_CROSSBAR {
-+	DCP_GRPH_GREEN_CROSSBAR_FROM_G                   = 0x0,
-+	DCP_GRPH_GREEN_CROSSBAR_FROM_B                   = 0x1,
-+	DCP_GRPH_GREEN_CROSSBAR_FROM_A                   = 0x2,
-+	DCP_GRPH_GREEN_CROSSBAR_FROM_R                   = 0x3,
-+} DCP_GRPH_GREEN_CROSSBAR;
-+typedef enum DCP_GRPH_BLUE_CROSSBAR {
-+	DCP_GRPH_BLUE_CROSSBAR_FROM_B                    = 0x0,
-+	DCP_GRPH_BLUE_CROSSBAR_FROM_A                    = 0x1,
-+	DCP_GRPH_BLUE_CROSSBAR_FROM_R                    = 0x2,
-+	DCP_GRPH_BLUE_CROSSBAR_FROM_G                    = 0x3,
-+} DCP_GRPH_BLUE_CROSSBAR;
-+typedef enum DCP_GRPH_ALPHA_CROSSBAR {
-+	DCP_GRPH_ALPHA_CROSSBAR_FROM_A                   = 0x0,
-+	DCP_GRPH_ALPHA_CROSSBAR_FROM_R                   = 0x1,
-+	DCP_GRPH_ALPHA_CROSSBAR_FROM_G                   = 0x2,
-+	DCP_GRPH_ALPHA_CROSSBAR_FROM_B                   = 0x3,
-+} DCP_GRPH_ALPHA_CROSSBAR;
-+typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
-+	DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE                = 0x0,
-+	DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE                 = 0x1,
-+} DCP_GRPH_PRIMARY_DFQ_ENABLE;
-+typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
-+	DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE              = 0x0,
-+	DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE               = 0x1,
-+} DCP_GRPH_SECONDARY_DFQ_ENABLE;
-+typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
-+	DCP_GRPH_INPUT_GAMMA_MODE_LUT                    = 0x0,
-+	DCP_GRPH_INPUT_GAMMA_MODE_BYPASS                 = 0x1,
-+} DCP_GRPH_INPUT_GAMMA_MODE;
-+typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
-+	DCP_GRPH_MODE_UPDATE_PENDING_FALSE               = 0x0,
-+	DCP_GRPH_MODE_UPDATE_PENDING_TRUE                = 0x1,
-+} DCP_GRPH_MODE_UPDATE_PENDING;
-+typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
-+	DCP_GRPH_MODE_UPDATE_TAKEN_FALSE                 = 0x0,
-+	DCP_GRPH_MODE_UPDATE_TAKEN_TRUE                  = 0x1,
-+} DCP_GRPH_MODE_UPDATE_TAKEN;
-+typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
-+	DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE            = 0x0,
-+	DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE             = 0x1,
-+} DCP_GRPH_SURFACE_UPDATE_PENDING;
-+typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
-+	DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE              = 0x0,
-+	DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE               = 0x1,
-+} DCP_GRPH_SURFACE_UPDATE_TAKEN;
-+typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
-+	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE       = 0x0,
-+	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE        = 0x1,
-+} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
-+typedef enum DCP_GRPH_UPDATE_LOCK {
-+	DCP_GRPH_UPDATE_LOCK_FALSE                       = 0x0,
-+	DCP_GRPH_UPDATE_LOCK_TRUE                        = 0x1,
-+} DCP_GRPH_UPDATE_LOCK;
-+typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
-+	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE        = 0x0,
-+	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE         = 0x1,
-+} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
-+typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
-+	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE      = 0x0,
-+	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE       = 0x1,
-+} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
-+typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
-+	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE   = 0x0,
-+	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE    = 0x1,
-+} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
-+typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
-+	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE       = 0x0,
-+	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE        = 0x1,
-+} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
-+typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
-+	DCP_GRPH_XDMA_SUPER_AA_EN_FALSE                  = 0x0,
-+	DCP_GRPH_XDMA_SUPER_AA_EN_TRUE                   = 0x1,
-+} DCP_GRPH_XDMA_SUPER_AA_EN;
-+typedef enum DCP_GRPH_DFQ_RESET {
-+	DCP_GRPH_DFQ_RESET_FALSE                         = 0x0,
-+	DCP_GRPH_DFQ_RESET_TRUE                          = 0x1,
-+} DCP_GRPH_DFQ_RESET;
-+typedef enum DCP_GRPH_DFQ_SIZE {
-+	DCP_GRPH_DFQ_SIZE_DEEP1                          = 0x0,
-+	DCP_GRPH_DFQ_SIZE_DEEP2                          = 0x1,
-+	DCP_GRPH_DFQ_SIZE_DEEP3                          = 0x2,
-+	DCP_GRPH_DFQ_SIZE_DEEP4                          = 0x3,
-+	DCP_GRPH_DFQ_SIZE_DEEP5                          = 0x4,
-+	DCP_GRPH_DFQ_SIZE_DEEP6                          = 0x5,
-+	DCP_GRPH_DFQ_SIZE_DEEP7                          = 0x6,
-+	DCP_GRPH_DFQ_SIZE_DEEP8                          = 0x7,
-+} DCP_GRPH_DFQ_SIZE;
-+typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1                  = 0x0,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2                  = 0x1,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3                  = 0x2,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4                  = 0x3,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5                  = 0x4,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6                  = 0x5,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7                  = 0x6,
-+	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8                  = 0x7,
-+} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
-+typedef enum DCP_GRPH_DFQ_RESET_ACK {
-+	DCP_GRPH_DFQ_RESET_ACK_FALSE                     = 0x0,
-+	DCP_GRPH_DFQ_RESET_ACK_TRUE                      = 0x1,
-+} DCP_GRPH_DFQ_RESET_ACK;
-+typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
-+	DCP_GRPH_PFLIP_INT_CLEAR_FALSE                   = 0x0,
-+	DCP_GRPH_PFLIP_INT_CLEAR_TRUE                    = 0x1,
-+} DCP_GRPH_PFLIP_INT_CLEAR;
-+typedef enum DCP_GRPH_PFLIP_INT_MASK {
-+	DCP_GRPH_PFLIP_INT_MASK_FALSE                    = 0x0,
-+	DCP_GRPH_PFLIP_INT_MASK_TRUE                     = 0x1,
-+} DCP_GRPH_PFLIP_INT_MASK;
-+typedef enum DCP_GRPH_PFLIP_INT_TYPE {
-+	DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL             = 0x0,
-+	DCP_GRPH_PFLIP_INT_TYPE_PULSE                    = 0x1,
-+} DCP_GRPH_PFLIP_INT_TYPE;
-+typedef enum DCP_GRPH_PRESCALE_SELECT {
-+	DCP_GRPH_PRESCALE_SELECT_FIXED                   = 0x0,
-+	DCP_GRPH_PRESCALE_SELECT_FLOATING                = 0x1,
-+} DCP_GRPH_PRESCALE_SELECT;
-+typedef enum DCP_GRPH_PRESCALE_R_SIGN {
-+	DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED                = 0x0,
-+	DCP_GRPH_PRESCALE_R_SIGN_SIGNED                  = 0x1,
-+} DCP_GRPH_PRESCALE_R_SIGN;
-+typedef enum DCP_GRPH_PRESCALE_G_SIGN {
-+	DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED                = 0x0,
-+	DCP_GRPH_PRESCALE_G_SIGN_SIGNED                  = 0x1,
-+} DCP_GRPH_PRESCALE_G_SIGN;
-+typedef enum DCP_GRPH_PRESCALE_B_SIGN {
-+	DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED                = 0x0,
-+	DCP_GRPH_PRESCALE_B_SIGN_SIGNED                  = 0x1,
-+} DCP_GRPH_PRESCALE_B_SIGN;
-+typedef enum DCP_GRPH_PRESCALE_BYPASS {
-+	DCP_GRPH_PRESCALE_BYPASS_FALSE                   = 0x0,
-+	DCP_GRPH_PRESCALE_BYPASS_TRUE                    = 0x1,
-+} DCP_GRPH_PRESCALE_BYPASS;
-+typedef enum DCP_INPUT_CSC_GRPH_MODE {
-+	DCP_INPUT_CSC_GRPH_MODE_BYPASS                   = 0x0,
-+	DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF           = 0x1,
-+	DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF              = 0x2,
-+	DCP_INPUT_CSC_GRPH_MODE_RESERVED                 = 0x3,
-+} DCP_INPUT_CSC_GRPH_MODE;
-+typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
-+	DCP_OUTPUT_CSC_GRPH_MODE_BYPASS                  = 0x0,
-+	DCP_OUTPUT_CSC_GRPH_MODE_RGB                     = 0x1,
-+	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601                = 0x2,
-+	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709                = 0x3,
-+	DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF         = 0x4,
-+	DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF             = 0x5,
-+	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0               = 0x6,
-+	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1               = 0x7,
-+} DCP_OUTPUT_CSC_GRPH_MODE;
-+typedef enum DCP_DENORM_MODE {
-+	DCP_DENORM_MODE_UNITY                            = 0x0,
-+	DCP_DENORM_MODE_6BIT                             = 0x1,
-+	DCP_DENORM_MODE_8BIT                             = 0x2,
-+	DCP_DENORM_MODE_10BIT                            = 0x3,
-+	DCP_DENORM_MODE_11BIT                            = 0x4,
-+	DCP_DENORM_MODE_12BIT                            = 0x5,
-+	DCP_DENORM_MODE_RESERVED0                        = 0x6,
-+	DCP_DENORM_MODE_RESERVED1                        = 0x7,
-+} DCP_DENORM_MODE;
-+typedef enum DCP_DENORM_14BIT_OUT {
-+	DCP_DENORM_14BIT_OUT_FALSE                       = 0x0,
-+	DCP_DENORM_14BIT_OUT_TRUE                        = 0x1,
-+} DCP_DENORM_14BIT_OUT;
-+typedef enum DCP_OUT_ROUND_TRUNC_MODE {
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12             = 0x0,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11             = 0x1,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10             = 0x2,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9              = 0x3,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8              = 0x4,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED       = 0x5,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14             = 0x6,
-+	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13             = 0x7,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_12                = 0x8,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_11                = 0x9,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_10                = 0xa,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_9                 = 0xb,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_8                 = 0xc,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED          = 0xd,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_14                = 0xe,
-+	DCP_OUT_ROUND_TRUNC_MODE_ROUND_13                = 0xf,
-+} DCP_OUT_ROUND_TRUNC_MODE;
-+typedef enum DCP_KEY_MODE {
-+	DCP_KEY_MODE_ALPHA0                              = 0x0,
-+	DCP_KEY_MODE_ALPHA1                              = 0x1,
-+	DCP_KEY_MODE_IN_RANGE_ALPHA1                     = 0x2,
-+	DCP_KEY_MODE_IN_RANGE_ALPHA0                     = 0x3,
-+} DCP_KEY_MODE;
-+typedef enum DCP_GRPH_DEGAMMA_MODE {
-+	DCP_GRPH_DEGAMMA_MODE_BYPASS                     = 0x0,
-+	DCP_GRPH_DEGAMMA_MODE_ROMA                       = 0x1,
-+	DCP_GRPH_DEGAMMA_MODE_ROMB                       = 0x2,
-+	DCP_GRPH_DEGAMMA_MODE_RESERVED                   = 0x3,
-+} DCP_GRPH_DEGAMMA_MODE;
-+typedef enum DCP_CURSOR2_DEGAMMA_MODE {
-+	DCP_CURSOR2_DEGAMMA_MODE_BYPASS                  = 0x0,
-+	DCP_CURSOR2_DEGAMMA_MODE_ROMA                    = 0x1,
-+	DCP_CURSOR2_DEGAMMA_MODE_ROMB                    = 0x2,
-+	DCP_CURSOR2_DEGAMMA_MODE_RESERVED                = 0x3,
-+} DCP_CURSOR2_DEGAMMA_MODE;
-+typedef enum DCP_CURSOR_DEGAMMA_MODE {
-+	DCP_CURSOR_DEGAMMA_MODE_BYPASS                   = 0x0,
-+	DCP_CURSOR_DEGAMMA_MODE_ROMA                     = 0x1,
-+	DCP_CURSOR_DEGAMMA_MODE_ROMB                     = 0x2,
-+	DCP_CURSOR_DEGAMMA_MODE_RESERVED                 = 0x3,
-+} DCP_CURSOR_DEGAMMA_MODE;
-+typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
-+	DCP_GRPH_GAMUT_REMAP_MODE_BYPASS                 = 0x0,
-+	DCP_GRPH_GAMUT_REMAP_MODE_ROMA                   = 0x1,
-+	DCP_GRPH_GAMUT_REMAP_MODE_ROMB                   = 0x2,
-+	DCP_GRPH_GAMUT_REMAP_MODE_RESERVED               = 0x3,
-+} DCP_GRPH_GAMUT_REMAP_MODE;
-+typedef enum DCP_SPATIAL_DITHER_EN {
-+	DCP_SPATIAL_DITHER_EN_FALSE                      = 0x0,
-+	DCP_SPATIAL_DITHER_EN_TRUE                       = 0x1,
-+} DCP_SPATIAL_DITHER_EN;
-+typedef enum DCP_SPATIAL_DITHER_MODE {
-+	DCP_SPATIAL_DITHER_MODE_BYPASS                   = 0x0,
-+	DCP_SPATIAL_DITHER_MODE_ROMA                     = 0x1,
-+	DCP_SPATIAL_DITHER_MODE_ROMB                     = 0x2,
-+	DCP_SPATIAL_DITHER_MODE_RESERVED                 = 0x3,
-+} DCP_SPATIAL_DITHER_MODE;
-+typedef enum DCP_SPATIAL_DITHER_DEPTH {
-+	DCP_SPATIAL_DITHER_DEPTH_30BPP                   = 0x0,
-+	DCP_SPATIAL_DITHER_DEPTH_24BPP                   = 0x1,
-+	DCP_SPATIAL_DITHER_DEPTH_36BPP                   = 0x2,
-+	DCP_SPATIAL_DITHER_DEPTH_UNDEFINED               = 0x3,
-+} DCP_SPATIAL_DITHER_DEPTH;
-+typedef enum DCP_FRAME_RANDOM_ENABLE {
-+	DCP_FRAME_RANDOM_ENABLE_FALSE                    = 0x0,
-+	DCP_FRAME_RANDOM_ENABLE_TRUE                     = 0x1,
-+} DCP_FRAME_RANDOM_ENABLE;
-+typedef enum DCP_RGB_RANDOM_ENABLE {
-+	DCP_RGB_RANDOM_ENABLE_FALSE                      = 0x0,
-+	DCP_RGB_RANDOM_ENABLE_TRUE                       = 0x1,
-+} DCP_RGB_RANDOM_ENABLE;
-+typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
-+	DCP_HIGHPASS_RANDOM_ENABLE_FALSE                 = 0x0,
-+	DCP_HIGHPASS_RANDOM_ENABLE_TRUE                  = 0x1,
-+} DCP_HIGHPASS_RANDOM_ENABLE;
-+typedef enum DCP_CURSOR_EN {
-+	DCP_CURSOR_EN_FALSE                              = 0x0,
-+	DCP_CURSOR_EN_TRUE                               = 0x1,
-+} DCP_CURSOR_EN;
-+typedef enum DCP_CUR_INV_TRANS_CLAMP {
-+	DCP_CUR_INV_TRANS_CLAMP_FALSE                    = 0x0,
-+	DCP_CUR_INV_TRANS_CLAMP_TRUE                     = 0x1,
-+} DCP_CUR_INV_TRANS_CLAMP;
-+typedef enum DCP_CURSOR_MODE {
-+	DCP_CURSOR_MODE_MONO_2BPP                        = 0x0,
-+	DCP_CURSOR_MODE_24BPP_1BIT                       = 0x1,
-+	DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI              = 0x2,
-+	DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI            = 0x3,
-+} DCP_CURSOR_MODE;
-+typedef enum DCP_CURSOR_2X_MAGNIFY {
-+	DCP_CURSOR_2X_MAGNIFY_FALSE                      = 0x0,
-+	DCP_CURSOR_2X_MAGNIFY_TRUE                       = 0x1,
-+} DCP_CURSOR_2X_MAGNIFY;
-+typedef enum DCP_CURSOR_FORCE_MC_ON {
-+	DCP_CURSOR_FORCE_MC_ON_FALSE                     = 0x0,
-+	DCP_CURSOR_FORCE_MC_ON_TRUE                      = 0x1,
-+} DCP_CURSOR_FORCE_MC_ON;
-+typedef enum DCP_CURSOR_URGENT_CONTROL {
-+	DCP_CURSOR_URGENT_CONTROL_MODE_0                 = 0x0,
-+	DCP_CURSOR_URGENT_CONTROL_MODE_1                 = 0x1,
-+	DCP_CURSOR_URGENT_CONTROL_MODE_2                 = 0x2,
-+	DCP_CURSOR_URGENT_CONTROL_MODE_3                 = 0x3,
-+	DCP_CURSOR_URGENT_CONTROL_MODE_4                 = 0x4,
-+} DCP_CURSOR_URGENT_CONTROL;
-+typedef enum DCP_CURSOR_UPDATE_PENDING {
-+	DCP_CURSOR_UPDATE_PENDING_FALSE                  = 0x0,
-+	DCP_CURSOR_UPDATE_PENDING_TRUE                   = 0x1,
-+} DCP_CURSOR_UPDATE_PENDING;
-+typedef enum DCP_CURSOR_UPDATE_TAKEN {
-+	DCP_CURSOR_UPDATE_TAKEN_FALSE                    = 0x0,
-+	DCP_CURSOR_UPDATE_TAKEN_TRUE                     = 0x1,
-+} DCP_CURSOR_UPDATE_TAKEN;
-+typedef enum DCP_CURSOR_UPDATE_LOCK {
-+	DCP_CURSOR_UPDATE_LOCK_FALSE                     = 0x0,
-+	DCP_CURSOR_UPDATE_LOCK_TRUE                      = 0x1,
-+} DCP_CURSOR_UPDATE_LOCK;
-+typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
-+	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE         = 0x0,
-+	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE          = 0x1,
-+} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
-+typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
-+	DCP_CURSOR_UPDATE_STEREO_MODE_BOTH               = 0x0,
-+	DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY     = 0x1,
-+	DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED          = 0x2,
-+	DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY       = 0x3,
-+} DCP_CURSOR_UPDATE_STEREO_MODE;
-+typedef enum DCP_CURSOR2_EN {
-+	DCP_CURSOR2_EN_FALSE                             = 0x0,
-+	DCP_CURSOR2_EN_TRUE                              = 0x1,
-+} DCP_CURSOR2_EN;
-+typedef enum DCP_CUR2_INV_TRANS_CLAMP {
-+	DCP_CUR2_INV_TRANS_CLAMP_FALSE                   = 0x0,
-+	DCP_CUR2_INV_TRANS_CLAMP_TRUE                    = 0x1,
-+} DCP_CUR2_INV_TRANS_CLAMP;
-+typedef enum DCP_CURSOR2_MODE {
-+	DCP_CURSOR2_MODE_MONO_2BPP                       = 0x0,
-+	DCP_CURSOR2_MODE_24BPP_1BIT                      = 0x1,
-+	DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI             = 0x2,
-+	DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI           = 0x3,
-+} DCP_CURSOR2_MODE;
-+typedef enum DCP_CURSOR2_2X_MAGNIFY {
-+	DCP_CURSOR2_2X_MAGNIFY_FALSE                     = 0x0,
-+	DCP_CURSOR2_2X_MAGNIFY_TRUE                      = 0x1,
-+} DCP_CURSOR2_2X_MAGNIFY;
-+typedef enum DCP_CURSOR2_FORCE_MC_ON {
-+	DCP_CURSOR2_FORCE_MC_ON_FALSE                    = 0x0,
-+	DCP_CURSOR2_FORCE_MC_ON_TRUE                     = 0x1,
-+} DCP_CURSOR2_FORCE_MC_ON;
-+typedef enum DCP_CURSOR2_URGENT_CONTROL {
-+	DCP_CURSOR2_URGENT_CONTROL_MODE_0                = 0x0,
-+	DCP_CURSOR2_URGENT_CONTROL_MODE_1                = 0x1,
-+	DCP_CURSOR2_URGENT_CONTROL_MODE_2                = 0x2,
-+	DCP_CURSOR2_URGENT_CONTROL_MODE_3                = 0x3,
-+	DCP_CURSOR2_URGENT_CONTROL_MODE_4                = 0x4,
-+} DCP_CURSOR2_URGENT_CONTROL;
-+typedef enum DCP_CURSOR2_UPDATE_PENDING {
-+	DCP_CURSOR2_UPDATE_PENDING_FALSE                 = 0x0,
-+	DCP_CURSOR2_UPDATE_PENDING_TRUE                  = 0x1,
-+} DCP_CURSOR2_UPDATE_PENDING;
-+typedef enum DCP_CURSOR2_UPDATE_TAKEN {
-+	DCP_CURSOR2_UPDATE_TAKEN_FALSE                   = 0x0,
-+	DCP_CURSOR2_UPDATE_TAKEN_TRUE                    = 0x1,
-+} DCP_CURSOR2_UPDATE_TAKEN;
-+typedef enum DCP_CURSOR2_UPDATE_LOCK {
-+	DCP_CURSOR2_UPDATE_LOCK_FALSE                    = 0x0,
-+	DCP_CURSOR2_UPDATE_LOCK_TRUE                     = 0x1,
-+} DCP_CURSOR2_UPDATE_LOCK;
-+typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
-+	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE        = 0x0,
-+	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE         = 0x1,
-+} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
-+typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
-+	DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH              = 0x0,
-+	DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY    = 0x1,
-+	DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED         = 0x2,
-+	DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY      = 0x3,
-+} DCP_CURSOR2_UPDATE_STEREO_MODE;
-+typedef enum DCP_CUR_REQUEST_FILTER_DIS {
-+	DCP_CUR_REQUEST_FILTER_DIS_FALSE                 = 0x0,
-+	DCP_CUR_REQUEST_FILTER_DIS_TRUE                  = 0x1,
-+} DCP_CUR_REQUEST_FILTER_DIS;
-+typedef enum DCP_CURSOR_STEREO_EN {
-+	DCP_CURSOR_STEREO_EN_FALSE                       = 0x0,
-+	DCP_CURSOR_STEREO_EN_TRUE                        = 0x1,
-+} DCP_CURSOR_STEREO_EN;
-+typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
-+	DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION          = 0x0,
-+	DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION          = 0x1,
-+} DCP_CURSOR_STEREO_OFFSET_YNX;
-+typedef enum DCP_CURSOR2_STEREO_EN {
-+	DCP_CURSOR2_STEREO_EN_FALSE                      = 0x0,
-+	DCP_CURSOR2_STEREO_EN_TRUE                       = 0x1,
-+} DCP_CURSOR2_STEREO_EN;
-+typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
-+	DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION         = 0x0,
-+	DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION         = 0x1,
-+} DCP_CURSOR2_STEREO_OFFSET_YNX;
-+typedef enum DCP_DC_LUT_RW_MODE {
-+	DCP_DC_LUT_RW_MODE_256_ENTRY                     = 0x0,
-+	DCP_DC_LUT_RW_MODE_PWL                           = 0x1,
-+} DCP_DC_LUT_RW_MODE;
-+typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
-+	DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE               = 0x0,
-+	DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE                = 0x1,
-+} DCP_DC_LUT_VGA_ACCESS_ENABLE;
-+typedef enum DCP_DC_LUT_AUTOFILL {
-+	DCP_DC_LUT_AUTOFILL_FALSE                        = 0x0,
-+	DCP_DC_LUT_AUTOFILL_TRUE                         = 0x1,
-+} DCP_DC_LUT_AUTOFILL;
-+typedef enum DCP_DC_LUT_AUTOFILL_DONE {
-+	DCP_DC_LUT_AUTOFILL_DONE_FALSE                   = 0x0,
-+	DCP_DC_LUT_AUTOFILL_DONE_TRUE                    = 0x1,
-+} DCP_DC_LUT_AUTOFILL_DONE;
-+typedef enum DCP_DC_LUT_INC_B {
-+	DCP_DC_LUT_INC_B_NA                              = 0x0,
-+	DCP_DC_LUT_INC_B_2                               = 0x1,
-+	DCP_DC_LUT_INC_B_4                               = 0x2,
-+	DCP_DC_LUT_INC_B_8                               = 0x3,
-+	DCP_DC_LUT_INC_B_16                              = 0x4,
-+	DCP_DC_LUT_INC_B_32                              = 0x5,
-+	DCP_DC_LUT_INC_B_64                              = 0x6,
-+	DCP_DC_LUT_INC_B_128                             = 0x7,
-+	DCP_DC_LUT_INC_B_256                             = 0x8,
-+	DCP_DC_LUT_INC_B_512                             = 0x9,
-+} DCP_DC_LUT_INC_B;
-+typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
-+	DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE                = 0x0,
-+	DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE                 = 0x1,
-+} DCP_DC_LUT_DATA_B_SIGNED_EN;
-+typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
-+	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE           = 0x0,
-+	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE            = 0x1,
-+} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
-+typedef enum DCP_DC_LUT_DATA_B_FORMAT {
-+	DCP_DC_LUT_DATA_B_FORMAT_U0P10                   = 0x0,
-+	DCP_DC_LUT_DATA_B_FORMAT_S1P10                   = 0x1,
-+	DCP_DC_LUT_DATA_B_FORMAT_U1P11                   = 0x2,
-+	DCP_DC_LUT_DATA_B_FORMAT_U0P12                   = 0x3,
-+} DCP_DC_LUT_DATA_B_FORMAT;
-+typedef enum DCP_DC_LUT_INC_G {
-+	DCP_DC_LUT_INC_G_NA                              = 0x0,
-+	DCP_DC_LUT_INC_G_2                               = 0x1,
-+	DCP_DC_LUT_INC_G_4                               = 0x2,
-+	DCP_DC_LUT_INC_G_8                               = 0x3,
-+	DCP_DC_LUT_INC_G_16                              = 0x4,
-+	DCP_DC_LUT_INC_G_32                              = 0x5,
-+	DCP_DC_LUT_INC_G_64                              = 0x6,
-+	DCP_DC_LUT_INC_G_128                             = 0x7,
-+	DCP_DC_LUT_INC_G_256                             = 0x8,
-+	DCP_DC_LUT_INC_G_512                             = 0x9,
-+} DCP_DC_LUT_INC_G;
-+typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
-+	DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE                = 0x0,
-+	DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE                 = 0x1,
-+} DCP_DC_LUT_DATA_G_SIGNED_EN;
-+typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
-+	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE           = 0x0,
-+	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE            = 0x1,
-+} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
-+typedef enum DCP_DC_LUT_DATA_G_FORMAT {
-+	DCP_DC_LUT_DATA_G_FORMAT_U0P10                   = 0x0,
-+	DCP_DC_LUT_DATA_G_FORMAT_S1P10                   = 0x1,
-+	DCP_DC_LUT_DATA_G_FORMAT_U1P11                   = 0x2,
-+	DCP_DC_LUT_DATA_G_FORMAT_U0P12                   = 0x3,
-+} DCP_DC_LUT_DATA_G_FORMAT;
-+typedef enum DCP_DC_LUT_INC_R {
-+	DCP_DC_LUT_INC_R_NA                              = 0x0,
-+	DCP_DC_LUT_INC_R_2                               = 0x1,
-+	DCP_DC_LUT_INC_R_4                               = 0x2,
-+	DCP_DC_LUT_INC_R_8                               = 0x3,
-+	DCP_DC_LUT_INC_R_16                              = 0x4,
-+	DCP_DC_LUT_INC_R_32                              = 0x5,
-+	DCP_DC_LUT_INC_R_64                              = 0x6,
-+	DCP_DC_LUT_INC_R_128                             = 0x7,
-+	DCP_DC_LUT_INC_R_256                             = 0x8,
-+	DCP_DC_LUT_INC_R_512                             = 0x9,
-+} DCP_DC_LUT_INC_R;
-+typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
-+	DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE                = 0x0,
-+	DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE                 = 0x1,
-+} DCP_DC_LUT_DATA_R_SIGNED_EN;
-+typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
-+	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE           = 0x0,
-+	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE            = 0x1,
-+} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
-+typedef enum DCP_DC_LUT_DATA_R_FORMAT {
-+	DCP_DC_LUT_DATA_R_FORMAT_U0P10                   = 0x0,
-+	DCP_DC_LUT_DATA_R_FORMAT_S1P10                   = 0x1,
-+	DCP_DC_LUT_DATA_R_FORMAT_U1P11                   = 0x2,
-+	DCP_DC_LUT_DATA_R_FORMAT_U0P12                   = 0x3,
-+} DCP_DC_LUT_DATA_R_FORMAT;
-+typedef enum DCP_CRC_ENABLE {
-+	DCP_CRC_ENABLE_FALSE                             = 0x0,
-+	DCP_CRC_ENABLE_TRUE                              = 0x1,
-+} DCP_CRC_ENABLE;
-+typedef enum DCP_CRC_SOURCE_SEL {
-+	DCP_CRC_SOURCE_SEL_OUTPUT_PIX                    = 0x0,
-+	DCP_CRC_SOURCE_SEL_INPUT_L32                     = 0x1,
-+	DCP_CRC_SOURCE_SEL_INPUT_H32                     = 0x2,
-+	DCP_CRC_SOURCE_SEL_OUTPUT_CNTL                   = 0x4,
-+} DCP_CRC_SOURCE_SEL;
-+typedef enum DCP_CRC_LINE_SEL {
-+	DCP_CRC_LINE_SEL_RESERVED                        = 0x0,
-+	DCP_CRC_LINE_SEL_EVEN                            = 0x1,
-+	DCP_CRC_LINE_SEL_ODD                             = 0x2,
-+	DCP_CRC_LINE_SEL_BOTH                            = 0x3,
-+} DCP_CRC_LINE_SEL;
-+typedef enum DCP_GRPH_FLIP_RATE {
-+	DCP_GRPH_FLIP_RATE_1FRAME                        = 0x0,
-+	DCP_GRPH_FLIP_RATE_2FRAME                        = 0x1,
-+	DCP_GRPH_FLIP_RATE_3FRAME                        = 0x2,
-+	DCP_GRPH_FLIP_RATE_4FRAME                        = 0x3,
-+	DCP_GRPH_FLIP_RATE_5FRAME                        = 0x4,
-+	DCP_GRPH_FLIP_RATE_6FRAME                        = 0x5,
-+	DCP_GRPH_FLIP_RATE_7FRAME                        = 0x6,
-+	DCP_GRPH_FLIP_RATE_8FRAME                        = 0x7,
-+} DCP_GRPH_FLIP_RATE;
-+typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
-+	DCP_GRPH_FLIP_RATE_ENABLE_FALSE                  = 0x0,
-+	DCP_GRPH_FLIP_RATE_ENABLE_TRUE                   = 0x1,
-+} DCP_GRPH_FLIP_RATE_ENABLE;
-+typedef enum DCP_GSL0_EN {
-+	DCP_GSL0_EN_FALSE                                = 0x0,
-+	DCP_GSL0_EN_TRUE                                 = 0x1,
-+} DCP_GSL0_EN;
-+typedef enum DCP_GSL1_EN {
-+	DCP_GSL1_EN_FALSE                                = 0x0,
-+	DCP_GSL1_EN_TRUE                                 = 0x1,
-+} DCP_GSL1_EN;
-+typedef enum DCP_GSL2_EN {
-+	DCP_GSL2_EN_FALSE                                = 0x0,
-+	DCP_GSL2_EN_TRUE                                 = 0x1,
-+} DCP_GSL2_EN;
-+typedef enum DCP_GSL_MASTER_EN {
-+	DCP_GSL_MASTER_EN_FALSE                          = 0x0,
-+	DCP_GSL_MASTER_EN_TRUE                           = 0x1,
-+} DCP_GSL_MASTER_EN;
-+typedef enum DCP_GSL_XDMA_GROUP {
-+	DCP_GSL_XDMA_GROUP_VSYNC                         = 0x0,
-+	DCP_GSL_XDMA_GROUP_HSYNC0                        = 0x1,
-+	DCP_GSL_XDMA_GROUP_HSYNC1                        = 0x2,
-+	DCP_GSL_XDMA_GROUP_HSYNC2                        = 0x3,
-+} DCP_GSL_XDMA_GROUP;
-+typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
-+	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE            = 0x0,
-+	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE             = 0x1,
-+} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
-+typedef enum DCP_GSL_SYNC_SOURCE {
-+	DCP_GSL_SYNC_SOURCE_FLIP                         = 0x0,
-+	DCP_GSL_SYNC_SOURCE_PHASE0                       = 0x1,
-+	DCP_GSL_SYNC_SOURCE_RESET                        = 0x2,
-+	DCP_GSL_SYNC_SOURCE_PHASE1                       = 0x3,
-+} DCP_GSL_SYNC_SOURCE;
-+typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
-+	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE       = 0x0,
-+	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE        = 0x1,
-+} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
-+typedef enum DCP_TEST_DEBUG_WRITE_EN {
-+	DCP_TEST_DEBUG_WRITE_EN_FALSE                    = 0x0,
-+	DCP_TEST_DEBUG_WRITE_EN_TRUE                     = 0x1,
-+} DCP_TEST_DEBUG_WRITE_EN;
-+typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
-+	DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE                = 0x0,
-+	DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE                 = 0x1,
-+} DCP_GRPH_STEREOSYNC_FLIP_EN;
-+typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
-+	DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP               = 0x0,
-+	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0             = 0x1,
-+	DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET              = 0x2,
-+	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1             = 0x3,
-+} DCP_GRPH_STEREOSYNC_FLIP_MODE;
-+typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
-+	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE         = 0x0,
-+	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE          = 0x1,
-+} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
-+typedef enum DCP_GRPH_ROTATION_ANGLE {
-+	DCP_GRPH_ROTATION_ANGLE_0                        = 0x0,
-+	DCP_GRPH_ROTATION_ANGLE_90                       = 0x1,
-+	DCP_GRPH_ROTATION_ANGLE_180                      = 0x2,
-+	DCP_GRPH_ROTATION_ANGLE_270                      = 0x3,
-+} DCP_GRPH_ROTATION_ANGLE;
-+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE       = 0x0,
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE        = 0x1,
-+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
-+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x0,
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
-+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
-+typedef enum DCP_GRPH_REGAMMA_MODE {
-+	DCP_GRPH_REGAMMA_MODE_BYPASS                     = 0x0,
-+	DCP_GRPH_REGAMMA_MODE_SRGB                       = 0x1,
-+	DCP_GRPH_REGAMMA_MODE_XVYCC                      = 0x2,
-+	DCP_GRPH_REGAMMA_MODE_PROGA                      = 0x3,
-+	DCP_GRPH_REGAMMA_MODE_PROGB                      = 0x4,
-+} DCP_GRPH_REGAMMA_MODE;
-+typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
-+	DCP_ALPHA_ROUND_TRUNC_MODE_ROUND                 = 0x0,
-+	DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC                 = 0x1,
-+} DCP_ALPHA_ROUND_TRUNC_MODE;
-+typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
-+	DCP_CURSOR_ALPHA_BLND_ENA_FALSE                  = 0x0,
-+	DCP_CURSOR_ALPHA_BLND_ENA_TRUE                   = 0x1,
-+} DCP_CURSOR_ALPHA_BLND_ENA;
-+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE   = 0x0,
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE    = 0x1,
-+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
-+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE    = 0x0,
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE     = 0x1,
-+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
-+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE     = 0x0,
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE      = 0x1,
-+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
-+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE      = 0x0,
-+	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE       = 0x1,
-+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
-+typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
-+	DCP_GRPH_SURFACE_COUNTER_EN_DISABLE              = 0x0,
-+	DCP_GRPH_SURFACE_COUNTER_EN_ENABLE               = 0x1,
-+} DCP_GRPH_SURFACE_COUNTER_EN;
-+typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0          = 0x0,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1          = 0x1,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2          = 0x2,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3          = 0x3,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4          = 0x4,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5          = 0x5,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6          = 0x6,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7          = 0x7,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8          = 0x8,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9          = 0x9,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10         = 0xa,
-+	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11         = 0xb,
-+} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
-+typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
-+	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO     = 0x0,
-+	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES    = 0x1,
-+} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
-+typedef enum HDMI_KEEPOUT_MODE {
-+	HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC                = 0x0,
-+	HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC              = 0x1,
-+} HDMI_KEEPOUT_MODE;
-+typedef enum HDMI_CLOCK_CHANNEL_RATE {
-+	HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE       = 0x0,
-+	HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE     = 0x1,
-+} HDMI_CLOCK_CHANNEL_RATE;
-+typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
-+	HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE             = 0x0,
-+	HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE            = 0x1,
-+} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
-+typedef enum HDMI_PACKET_GEN_VERSION {
-+	HDMI_PACKET_GEN_VERSION_OLD                      = 0x0,
-+	HDMI_PACKET_GEN_VERSION_NEW                      = 0x1,
-+} HDMI_PACKET_GEN_VERSION;
-+typedef enum HDMI_ERROR_ACK {
-+	HDMI_ERROR_ACK_INT                               = 0x0,
-+	HDMI_ERROR_NOT_ACK                               = 0x1,
-+} HDMI_ERROR_ACK;
-+typedef enum HDMI_ERROR_MASK {
-+	HDMI_ERROR_MASK_INT                              = 0x0,
-+	HDMI_ERROR_NOT_MASK                              = 0x1,
-+} HDMI_ERROR_MASK;
-+typedef enum HDMI_DEEP_COLOR_DEPTH {
-+	HDMI_DEEP_COLOR_DEPTH_24BPP                      = 0x0,
-+	HDMI_DEEP_COLOR_DEPTH_30BPP                      = 0x1,
-+	HDMI_DEEP_COLOR_DEPTH_36BPP                      = 0x2,
-+	HDMI_DEEP_COLOR_DEPTH_RESERVED                   = 0x3,
-+} HDMI_DEEP_COLOR_DEPTH;
-+typedef enum HDMI_AUDIO_DELAY_EN {
-+	HDMI_AUDIO_DELAY_DISABLE                         = 0x0,
-+	HDMI_AUDIO_DELAY_58CLK                           = 0x1,
-+	HDMI_AUDIO_DELAY_56CLK                           = 0x2,
-+	HDMI_AUDIO_DELAY_RESERVED                        = 0x3,
-+} HDMI_AUDIO_DELAY_EN;
-+typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
-+	HDMI_NOT_SEND_MAX_AUDIO_PACKETS                  = 0x0,
-+	HDMI_SEND_MAX_AUDIO_PACKETS                      = 0x1,
-+} HDMI_AUDIO_SEND_MAX_PACKETS;
-+typedef enum HDMI_ACR_SEND {
-+	HDMI_ACR_NOT_SEND                                = 0x0,
-+	HDMI_ACR_PKT_SEND                                = 0x1,
-+} HDMI_ACR_SEND;
-+typedef enum HDMI_ACR_CONT {
-+	HDMI_ACR_CONT_DISABLE                            = 0x0,
-+	HDMI_ACR_CONT_ENABLE                             = 0x1,
-+} HDMI_ACR_CONT;
-+typedef enum HDMI_ACR_SELECT {
-+	HDMI_ACR_SELECT_HW                               = 0x0,
-+	HDMI_ACR_SELECT_32K                              = 0x1,
-+	HDMI_ACR_SELECT_44K                              = 0x2,
-+	HDMI_ACR_SELECT_48K                              = 0x3,
-+} HDMI_ACR_SELECT;
-+typedef enum HDMI_ACR_SOURCE {
-+	HDMI_ACR_SOURCE_HW                               = 0x0,
-+	HDMI_ACR_SOURCE_SW                               = 0x1,
-+} HDMI_ACR_SOURCE;
-+typedef enum HDMI_ACR_N_MULTIPLE {
-+	HDMI_ACR_0_MULTIPLE_RESERVED                     = 0x0,
-+	HDMI_ACR_1_MULTIPLE                              = 0x1,
-+	HDMI_ACR_2_MULTIPLE                              = 0x2,
-+	HDMI_ACR_3_MULTIPLE_RESERVED                     = 0x3,
-+	HDMI_ACR_4_MULTIPLE                              = 0x4,
-+	HDMI_ACR_5_MULTIPLE_RESERVED                     = 0x5,
-+	HDMI_ACR_6_MULTIPLE_RESERVED                     = 0x6,
-+	HDMI_ACR_7_MULTIPLE_RESERVED                     = 0x7,
-+} HDMI_ACR_N_MULTIPLE;
-+typedef enum HDMI_ACR_AUDIO_PRIORITY {
-+	HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE     = 0x0,
-+	HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT     = 0x1,
-+} HDMI_ACR_AUDIO_PRIORITY;
-+typedef enum HDMI_NULL_SEND {
-+	HDMI_NULL_NOT_SEND                               = 0x0,
-+	HDMI_NULL_PKT_SEND                               = 0x1,
-+} HDMI_NULL_SEND;
-+typedef enum HDMI_GC_SEND {
-+	HDMI_GC_NOT_SEND                                 = 0x0,
-+	HDMI_GC_PKT_SEND                                 = 0x1,
-+} HDMI_GC_SEND;
-+typedef enum HDMI_GC_CONT {
-+	HDMI_GC_CONT_DISABLE                             = 0x0,
-+	HDMI_GC_CONT_ENABLE                              = 0x1,
-+} HDMI_GC_CONT;
-+typedef enum HDMI_ISRC_SEND {
-+	HDMI_ISRC_NOT_SEND                               = 0x0,
-+	HDMI_ISRC_PKT_SEND                               = 0x1,
-+} HDMI_ISRC_SEND;
-+typedef enum HDMI_ISRC_CONT {
-+	HDMI_ISRC_CONT_DISABLE                           = 0x0,
-+	HDMI_ISRC_CONT_ENABLE                            = 0x1,
-+} HDMI_ISRC_CONT;
-+typedef enum HDMI_AVI_INFO_SEND {
-+	HDMI_AVI_INFO_NOT_SEND                           = 0x0,
-+	HDMI_AVI_INFO_PKT_SEND                           = 0x1,
-+} HDMI_AVI_INFO_SEND;
-+typedef enum HDMI_AVI_INFO_CONT {
-+	HDMI_AVI_INFO_CONT_DISABLE                       = 0x0,
-+	HDMI_AVI_INFO_CONT_ENABLE                        = 0x1,
-+} HDMI_AVI_INFO_CONT;
-+typedef enum HDMI_AUDIO_INFO_SEND {
-+	HDMI_AUDIO_INFO_NOT_SEND                         = 0x0,
-+	HDMI_AUDIO_INFO_PKT_SEND                         = 0x1,
-+} HDMI_AUDIO_INFO_SEND;
-+typedef enum HDMI_AUDIO_INFO_CONT {
-+	HDMI_AUDIO_INFO_CONT_DISABLE                     = 0x0,
-+	HDMI_AUDIO_INFO_CONT_ENABLE                      = 0x1,
-+} HDMI_AUDIO_INFO_CONT;
-+typedef enum HDMI_MPEG_INFO_SEND {
-+	HDMI_MPEG_INFO_NOT_SEND                          = 0x0,
-+	HDMI_MPEG_INFO_PKT_SEND                          = 0x1,
-+} HDMI_MPEG_INFO_SEND;
-+typedef enum HDMI_MPEG_INFO_CONT {
-+	HDMI_MPEG_INFO_CONT_DISABLE                      = 0x0,
-+	HDMI_MPEG_INFO_CONT_ENABLE                       = 0x1,
-+} HDMI_MPEG_INFO_CONT;
-+typedef enum HDMI_GENERIC0_SEND {
-+	HDMI_GENERIC0_NOT_SEND                           = 0x0,
-+	HDMI_GENERIC0_PKT_SEND                           = 0x1,
-+} HDMI_GENERIC0_SEND;
-+typedef enum HDMI_GENERIC0_CONT {
-+	HDMI_GENERIC0_CONT_DISABLE                       = 0x0,
-+	HDMI_GENERIC0_CONT_ENABLE                        = 0x1,
-+} HDMI_GENERIC0_CONT;
-+typedef enum HDMI_GENERIC1_SEND {
-+	HDMI_GENERIC1_NOT_SEND                           = 0x0,
-+	HDMI_GENERIC1_PKT_SEND                           = 0x1,
-+} HDMI_GENERIC1_SEND;
-+typedef enum HDMI_GENERIC1_CONT {
-+	HDMI_GENERIC1_CONT_DISABLE                       = 0x0,
-+	HDMI_GENERIC1_CONT_ENABLE                        = 0x1,
-+} HDMI_GENERIC1_CONT;
-+typedef enum HDMI_GC_AVMUTE_CONT {
-+	HDMI_GC_AVMUTE_CONT_DISABLE                      = 0x0,
-+	HDMI_GC_AVMUTE_CONT_ENABLE                       = 0x1,
-+} HDMI_GC_AVMUTE_CONT;
-+typedef enum HDMI_PACKING_PHASE_OVERRIDE {
-+	HDMI_PACKING_PHASE_SET_BY_HW                     = 0x0,
-+	HDMI_PACKING_PHASE_SET_BY_SW                     = 0x1,
-+} HDMI_PACKING_PHASE_OVERRIDE;
-+typedef enum HDMI_GENERIC2_SEND {
-+	HDMI_GENERIC2_NOT_SEND                           = 0x0,
-+	HDMI_GENERIC2_PKT_SEND                           = 0x1,
-+} HDMI_GENERIC2_SEND;
-+typedef enum HDMI_GENERIC2_CONT {
-+	HDMI_GENERIC2_CONT_DISABLE                       = 0x0,
-+	HDMI_GENERIC2_CONT_ENABLE                        = 0x1,
-+} HDMI_GENERIC2_CONT;
-+typedef enum HDMI_GENERIC3_SEND {
-+	HDMI_GENERIC3_NOT_SEND                           = 0x0,
-+	HDMI_GENERIC3_PKT_SEND                           = 0x1,
-+} HDMI_GENERIC3_SEND;
-+typedef enum HDMI_GENERIC3_CONT {
-+	HDMI_GENERIC3_CONT_DISABLE                       = 0x0,
-+	HDMI_GENERIC3_CONT_ENABLE                        = 0x1,
-+} HDMI_GENERIC3_CONT;
-+typedef enum TMDS_PIXEL_ENCODING {
-+	TMDS_PIXEL_ENCODING_444_OR_420                   = 0x0,
-+	TMDS_PIXEL_ENCODING_422                          = 0x1,
-+} TMDS_PIXEL_ENCODING;
-+typedef enum TMDS_COLOR_FORMAT {
-+	TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
-+	TMDS_COLOR_FORMAT_TWIN30BPP_LSB                  = 0x1,
-+	TMDS_COLOR_FORMAT_DUAL30BPP                      = 0x2,
-+	TMDS_COLOR_FORMAT_RESERVED                       = 0x3,
-+} TMDS_COLOR_FORMAT;
-+typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
-+	TMDS_STEREOSYNC_CTL0                             = 0x0,
-+	TMDS_STEREOSYNC_CTL1                             = 0x1,
-+	TMDS_STEREOSYNC_CTL2                             = 0x2,
-+	TMDS_STEREOSYNC_CTL3                             = 0x3,
-+} TMDS_STEREOSYNC_CTL_SEL_REG;
-+typedef enum TMDS_CTL0_DATA_SEL {
-+	TMDS_CTL0_DATA_SEL0_RESERVED                     = 0x0,
-+	TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
-+	TMDS_CTL0_DATA_SEL2_VSYNC                        = 0x2,
-+	TMDS_CTL0_DATA_SEL3_RESERVED                     = 0x3,
-+	TMDS_CTL0_DATA_SEL4_HSYNC                        = 0x4,
-+	TMDS_CTL0_DATA_SEL5_SEL7_RESERVED                = 0x5,
-+	TMDS_CTL0_DATA_SEL8_RANDOM_DATA                  = 0x6,
-+	TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA            = 0x7,
-+} TMDS_CTL0_DATA_SEL;
-+typedef enum TMDS_CTL0_DATA_INVERT {
-+	TMDS_CTL0_DATA_NORMAL                            = 0x0,
-+	TMDS_CTL0_DATA_INVERT_EN                         = 0x1,
-+} TMDS_CTL0_DATA_INVERT;
-+typedef enum TMDS_CTL0_DATA_MODULATION {
-+	TMDS_CTL0_DATA_MODULATION_DISABLE                = 0x0,
-+	TMDS_CTL0_DATA_MODULATION_BIT0                   = 0x1,
-+	TMDS_CTL0_DATA_MODULATION_BIT1                   = 0x2,
-+	TMDS_CTL0_DATA_MODULATION_BIT2                   = 0x3,
-+} TMDS_CTL0_DATA_MODULATION;
-+typedef enum TMDS_CTL0_PATTERN_OUT_EN {
-+	TMDS_CTL0_PATTERN_OUT_DISABLE                    = 0x0,
-+	TMDS_CTL0_PATTERN_OUT_ENABLE                     = 0x1,
-+} TMDS_CTL0_PATTERN_OUT_EN;
-+typedef enum TMDS_CTL1_DATA_SEL {
-+	TMDS_CTL1_DATA_SEL0_RESERVED                     = 0x0,
-+	TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
-+	TMDS_CTL1_DATA_SEL2_VSYNC                        = 0x2,
-+	TMDS_CTL1_DATA_SEL3_RESERVED                     = 0x3,
-+	TMDS_CTL1_DATA_SEL4_HSYNC                        = 0x4,
-+	TMDS_CTL1_DATA_SEL5_SEL7_RESERVED                = 0x5,
-+	TMDS_CTL1_DATA_SEL8_BLANK_TIME                   = 0x6,
-+	TMDS_CTL1_DATA_SEL9_SEL15_RESERVED               = 0x7,
-+} TMDS_CTL1_DATA_SEL;
-+typedef enum TMDS_CTL1_DATA_INVERT {
-+	TMDS_CTL1_DATA_NORMAL                            = 0x0,
-+	TMDS_CTL1_DATA_INVERT_EN                         = 0x1,
-+} TMDS_CTL1_DATA_INVERT;
-+typedef enum TMDS_CTL1_DATA_MODULATION {
-+	TMDS_CTL1_DATA_MODULATION_DISABLE                = 0x0,
-+	TMDS_CTL1_DATA_MODULATION_BIT0                   = 0x1,
-+	TMDS_CTL1_DATA_MODULATION_BIT1                   = 0x2,
-+	TMDS_CTL1_DATA_MODULATION_BIT2                   = 0x3,
-+} TMDS_CTL1_DATA_MODULATION;
-+typedef enum TMDS_CTL1_PATTERN_OUT_EN {
-+	TMDS_CTL1_PATTERN_OUT_DISABLE                    = 0x0,
-+	TMDS_CTL1_PATTERN_OUT_ENABLE                     = 0x1,
-+} TMDS_CTL1_PATTERN_OUT_EN;
-+typedef enum TMDS_CTL2_DATA_SEL {
-+	TMDS_CTL2_DATA_SEL0_RESERVED                     = 0x0,
-+	TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
-+	TMDS_CTL2_DATA_SEL2_VSYNC                        = 0x2,
-+	TMDS_CTL2_DATA_SEL3_RESERVED                     = 0x3,
-+	TMDS_CTL2_DATA_SEL4_HSYNC                        = 0x4,
-+	TMDS_CTL2_DATA_SEL5_SEL7_RESERVED                = 0x5,
-+	TMDS_CTL2_DATA_SEL8_BLANK_TIME                   = 0x6,
-+	TMDS_CTL2_DATA_SEL9_SEL15_RESERVED               = 0x7,
-+} TMDS_CTL2_DATA_SEL;
-+typedef enum TMDS_CTL2_DATA_INVERT {
-+	TMDS_CTL2_DATA_NORMAL                            = 0x0,
-+	TMDS_CTL2_DATA_INVERT_EN                         = 0x1,
-+} TMDS_CTL2_DATA_INVERT;
-+typedef enum TMDS_CTL2_DATA_MODULATION {
-+	TMDS_CTL2_DATA_MODULATION_DISABLE                = 0x0,
-+	TMDS_CTL2_DATA_MODULATION_BIT0                   = 0x1,
-+	TMDS_CTL2_DATA_MODULATION_BIT1                   = 0x2,
-+	TMDS_CTL2_DATA_MODULATION_BIT2                   = 0x3,
-+} TMDS_CTL2_DATA_MODULATION;
-+typedef enum TMDS_CTL2_PATTERN_OUT_EN {
-+	TMDS_CTL2_PATTERN_OUT_DISABLE                    = 0x0,
-+	TMDS_CTL2_PATTERN_OUT_ENABLE                     = 0x1,
-+} TMDS_CTL2_PATTERN_OUT_EN;
-+typedef enum TMDS_CTL3_DATA_INVERT {
-+	TMDS_CTL3_DATA_NORMAL                            = 0x0,
-+	TMDS_CTL3_DATA_INVERT_EN                         = 0x1,
-+} TMDS_CTL3_DATA_INVERT;
-+typedef enum TMDS_CTL3_DATA_MODULATION {
-+	TMDS_CTL3_DATA_MODULATION_DISABLE                = 0x0,
-+	TMDS_CTL3_DATA_MODULATION_BIT0                   = 0x1,
-+	TMDS_CTL3_DATA_MODULATION_BIT1                   = 0x2,
-+	TMDS_CTL3_DATA_MODULATION_BIT2                   = 0x3,
-+} TMDS_CTL3_DATA_MODULATION;
-+typedef enum TMDS_CTL3_PATTERN_OUT_EN {
-+	TMDS_CTL3_PATTERN_OUT_DISABLE                    = 0x0,
-+	TMDS_CTL3_PATTERN_OUT_ENABLE                     = 0x1,
-+} TMDS_CTL3_PATTERN_OUT_EN;
-+typedef enum TMDS_CTL3_DATA_SEL {
-+	TMDS_CTL3_DATA_SEL0_RESERVED                     = 0x0,
-+	TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
-+	TMDS_CTL3_DATA_SEL2_VSYNC                        = 0x2,
-+	TMDS_CTL3_DATA_SEL3_RESERVED                     = 0x3,
-+	TMDS_CTL3_DATA_SEL4_HSYNC                        = 0x4,
-+	TMDS_CTL3_DATA_SEL5_SEL7_RESERVED                = 0x5,
-+	TMDS_CTL3_DATA_SEL8_BLANK_TIME                   = 0x6,
-+	TMDS_CTL3_DATA_SEL9_SEL15_RESERVED               = 0x7,
-+} TMDS_CTL3_DATA_SEL;
-+typedef enum DIG_FE_CNTL_SOURCE_SELECT {
-+	DIG_FE_SOURCE_FROM_FMT0                          = 0x0,
-+	DIG_FE_SOURCE_FROM_FMT1                          = 0x1,
-+	DIG_FE_SOURCE_FROM_FMT2                          = 0x2,
-+	DIG_FE_SOURCE_FROM_FMT3                          = 0x3,
-+	DIG_FE_SOURCE_FROM_FMT4                          = 0x4,
-+	DIG_FE_SOURCE_FROM_FMT5                          = 0x5,
-+} DIG_FE_CNTL_SOURCE_SELECT;
-+typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
-+	DIG_FE_STEREOSYNC_FROM_FMT0                      = 0x0,
-+	DIG_FE_STEREOSYNC_FROM_FMT1                      = 0x1,
-+	DIG_FE_STEREOSYNC_FROM_FMT2                      = 0x2,
-+	DIG_FE_STEREOSYNC_FROM_FMT3                      = 0x3,
-+	DIG_FE_STEREOSYNC_FROM_FMT4                      = 0x4,
-+	DIG_FE_STEREOSYNC_FROM_FMT5                      = 0x5,
-+} DIG_FE_CNTL_STEREOSYNC_SELECT;
-+typedef enum DIG_FIFO_READ_CLOCK_SRC {
-+	DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG                = 0x0,
-+	DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE        = 0x1,
-+} DIG_FIFO_READ_CLOCK_SRC;
-+typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
-+	DIG_OUTPUT_CRC_ON_LINK0                          = 0x0,
-+	DIG_OUTPUT_CRC_ON_LINK1                          = 0x1,
-+} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
-+typedef enum DIG_OUTPUT_CRC_DATA_SEL {
-+	DIG_OUTPUT_CRC_FOR_FULLFRAME                     = 0x0,
-+	DIG_OUTPUT_CRC_FOR_ACTIVEONLY                    = 0x1,
-+	DIG_OUTPUT_CRC_FOR_VBI                           = 0x2,
-+	DIG_OUTPUT_CRC_FOR_AUDIO                         = 0x3,
-+} DIG_OUTPUT_CRC_DATA_SEL;
-+typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
-+	DIG_IN_NORMAL_OPERATION                          = 0x0,
-+	DIG_IN_DEBUG_MODE                                = 0x1,
-+} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
-+typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
-+	DIG_10BIT_TEST_PATTERN                           = 0x0,
-+	DIG_ALTERNATING_TEST_PATTERN                     = 0x1,
-+} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
-+typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
-+	DIG_TEST_PATTERN_NORMAL                          = 0x0,
-+	DIG_TEST_PATTERN_RANDOM                          = 0x1,
-+} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
-+typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
-+	DIG_RANDOM_PATTERN_ENABLED                       = 0x0,
-+	DIG_RANDOM_PATTERN_RESETED                       = 0x1,
-+} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
-+typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
-+	DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE           = 0x0,
-+	DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG       = 0x1,
-+} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
-+typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
-+	DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS       = 0x0,
-+	DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH          = 0x1,
-+} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
-+typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
-+	DIG_FIFO_USE_OVERWRITE_LEVEL                     = 0x0,
-+	DIG_FIFO_USE_CAL_AVERAGE_LEVEL                   = 0x1,
-+} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
-+typedef enum DIG_FIFO_ERROR_ACK {
-+	DIG_FIFO_ERROR_ACK_INT                           = 0x0,
-+	DIG_FIFO_ERROR_NOT_ACK                           = 0x1,
-+} DIG_FIFO_ERROR_ACK;
-+typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
-+	DIG_FIFO_NOT_FORCE_RECAL_AVERAGE                 = 0x0,
-+	DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL               = 0x1,
-+} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
-+typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
-+	DIG_FIFO_NOT_FORCE_RECOMP_MINMAX                 = 0x0,
-+	DIG_FIFO_FORCE_RECOMP_MINMAX                     = 0x1,
-+} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
-+typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
-+	DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK               = 0x0,
-+	DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC                = 0x1,
-+} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
-+typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
-+	DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT               = 0x0,
-+	DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK           = 0x1,
-+} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
-+typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
-+	DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT              = 0x0,
-+	DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK            = 0x1,
-+} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
-+typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
-+	AFMT_INTERRUPT_DISABLE                           = 0x0,
-+	AFMT_INTERRUPT_ENABLE                            = 0x1,
-+} AFMT_INTERRUPT_STATUS_CHG_MASK;
-+typedef enum HDMI_GC_AVMUTE {
-+	HDMI_GC_AVMUTE_SET                               = 0x0,
-+	HDMI_GC_AVMUTE_UNSET                             = 0x1,
-+} HDMI_GC_AVMUTE;
-+typedef enum HDMI_DEFAULT_PAHSE {
-+	HDMI_DEFAULT_PHASE_IS_0                          = 0x0,
-+	HDMI_DEFAULT_PHASE_IS_1                          = 0x1,
-+} HDMI_DEFAULT_PAHSE;
-+typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
-+	AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
-+	AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER               = 0x1,
-+} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
-+typedef enum AUDIO_LAYOUT_SELECT {
-+	AUDIO_LAYOUT_0                                   = 0x0,
-+	AUDIO_LAYOUT_1                                   = 0x1,
-+} AUDIO_LAYOUT_SELECT;
-+typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
-+	AFMT_AUDIO_CRC_ONESHOT                           = 0x0,
-+	AFMT_AUDIO_CRC_AUTO_RESTART                      = 0x1,
-+} AFMT_AUDIO_CRC_CONTROL_CONT;
-+typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
-+	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT            = 0x0,
-+	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT           = 0x1,
-+} AFMT_AUDIO_CRC_CONTROL_SOURCE;
-+typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
-+	AFMT_AUDIO_CRC_CH0_SIG                           = 0x0,
-+	AFMT_AUDIO_CRC_CH1_SIG                           = 0x1,
-+	AFMT_AUDIO_CRC_CH2_SIG                           = 0x2,
-+	AFMT_AUDIO_CRC_CH3_SIG                           = 0x3,
-+	AFMT_AUDIO_CRC_CH4_SIG                           = 0x4,
-+	AFMT_AUDIO_CRC_CH5_SIG                           = 0x5,
-+	AFMT_AUDIO_CRC_CH6_SIG                           = 0x6,
-+	AFMT_AUDIO_CRC_CH7_SIG                           = 0x7,
-+	AFMT_AUDIO_CRC_RESERVED                          = 0x8,
-+	AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT                = 0x9,
-+} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
-+typedef enum AFMT_RAMP_CONTROL0_SIGN {
-+	AFMT_RAMP_SIGNED                                 = 0x0,
-+	AFMT_RAMP_UNSIGNED                               = 0x1,
-+} AFMT_RAMP_CONTROL0_SIGN;
-+typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
-+	AFMT_AUDIO_PACKET_SENT_DISABLED                  = 0x0,
-+	AFMT_AUDIO_PACKET_SENT_ENABLED                   = 0x1,
-+} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
-+typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
-+	AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
-+	AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED        = 0x1,
-+} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
-+typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
-+	AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK          = 0x0,
-+	AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS        = 0x1,
-+} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
-+typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
-+	AFMT_AUDIO_SRC_FROM_AZ_STREAM0                   = 0x0,
-+	AFMT_AUDIO_SRC_FROM_AZ_STREAM1                   = 0x1,
-+	AFMT_AUDIO_SRC_FROM_AZ_STREAM2                   = 0x2,
-+	AFMT_AUDIO_SRC_FROM_AZ_STREAM3                   = 0x3,
-+	AFMT_AUDIO_SRC_FROM_AZ_STREAM4                   = 0x4,
-+	AFMT_AUDIO_SRC_FROM_AZ_STREAM5                   = 0x5,
-+	AFMT_AUDIO_SRC_RESERVED                          = 0x6,
-+} AFMT_AUDIO_SRC_CONTROL_SELECT;
-+typedef enum DIG_BE_CNTL_MODE {
-+	DIG_BE_DP_SST_MODE                               = 0x0,
-+	DIG_BE_RESERVED1                                 = 0x1,
-+	DIG_BE_TMDS_DVI_MODE                             = 0x2,
-+	DIG_BE_TMDS_HDMI_MODE                            = 0x3,
-+	DIG_BE_SDVO_RESERVED                             = 0x4,
-+	DIG_BE_DP_MST_MODE                               = 0x5,
-+	DIG_BE_RESERVED2                                 = 0x6,
-+	DIG_BE_RESERVED3                                 = 0x7,
-+} DIG_BE_CNTL_MODE;
-+typedef enum DIG_BE_CNTL_HPD_SELECT {
-+	DIG_BE_CNTL_HPD1                                 = 0x0,
-+	DIG_BE_CNTL_HPD2                                 = 0x1,
-+	DIG_BE_CNTL_HPD3                                 = 0x2,
-+	DIG_BE_CNTL_HPD4                                 = 0x3,
-+	DIG_BE_CNTL_HPD5                                 = 0x4,
-+	DIG_BE_CNTL_HPD6                                 = 0x5,
-+} DIG_BE_CNTL_HPD_SELECT;
-+typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
-+	LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS             = 0x0,
-+	LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH           = 0x1,
-+} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
-+typedef enum TMDS_SYNC_PHASE {
-+	TMDS_NOT_SYNC_PHASE_ON_FRAME_START               = 0x0,
-+	TMDS_SYNC_PHASE_ON_FRAME_START                   = 0x1,
-+} TMDS_SYNC_PHASE;
-+typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
-+	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS     = 0x0,
-+	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL      = 0x1,
-+} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
-+typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
-+	TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE           = 0x0,
-+	TMDS_TRANSMITTER_HPD_MASK_OVERRIDE               = 0x1,
-+} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
-+typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
-+	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
-+	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE        = 0x1,
-+} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
-+typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
-+	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
-+	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE        = 0x1,
-+} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
-+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
-+	TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE     = 0x0,
-+	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
-+	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x2,
-+	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE         = 0x3,
-+} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
-+typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
-+	TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK           = 0x0,
-+	TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK             = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
-+typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
-+	TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK           = 0x0,
-+	TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK             = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
-+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
-+	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE           = 0x0,
-+	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE            = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
-+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
-+	TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD              = 0x0,
-+	TMDS_TRANSMITTER_PLL_RST_ON_HPD                  = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
-+typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
-+	TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK           = 0x0,
-+	TMDS_TRANSMITTER_TMCLK_FROM_PADS                 = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
-+typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
-+	TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK           = 0x0,
-+	TMDS_TRANSMITTER_TDCLK_FROM_PADS                 = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
-+typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
-+	TMDS_TRANSMITTER_PLLSEL_BY_HW                    = 0x0,
-+	TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW          = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
-+typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
-+	TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT            = 0x0,
-+	TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT          = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
-+typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
-+	TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT            = 0x0,
-+	TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT          = 0x1,
-+} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
-+typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
-+	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0              = 0x0,
-+	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1              = 0x1,
-+	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2              = 0x2,
-+	TMDS_REG_TEST_OUTPUTA_CNTLA_NA                   = 0x3,
-+} TMDS_REG_TEST_OUTPUTA_CNTLA;
-+typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
-+	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0              = 0x0,
-+	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1              = 0x1,
-+	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2              = 0x2,
-+	TMDS_REG_TEST_OUTPUTB_CNTLB_NA                   = 0x3,
-+} TMDS_REG_TEST_OUTPUTB_CNTLB;
-+typedef enum DP_LINK_TRAINING_COMPLETE {
-+	DP_LINK_TRAINING_NOT_COMPLETE                    = 0x0,
-+	DP_LINK_TRAINING_ALREADY_COMPLETE                = 0x1,
-+} DP_LINK_TRAINING_COMPLETE;
-+typedef enum DP_EMBEDDED_PANEL_MODE {
-+	DP_EXTERNAL_PANEL                                = 0x0,
-+	DP_EMBEDDED_PANEL                                = 0x1,
-+} DP_EMBEDDED_PANEL_MODE;
-+typedef enum DP_PIXEL_ENCODING {
-+	DP_PIXEL_ENCODING_RGB444                         = 0x0,
-+	DP_PIXEL_ENCODING_YCBCR422                       = 0x1,
-+	DP_PIXEL_ENCODING_YCBCR444                       = 0x2,
-+	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT                 = 0x3,
-+	DP_PIXEL_ENCODING_Y_ONLY                         = 0x4,
-+	DP_PIXEL_ENCODING_YCBCR420                       = 0x5,
-+	DP_PIXEL_ENCODING_RESERVED                       = 0x6,
-+} DP_PIXEL_ENCODING;
-+typedef enum DP_DYN_RANGE {
-+	DP_DYN_VESA_RANGE                                = 0x0,
-+	DP_DYN_CEA_RANGE                                 = 0x1,
-+} DP_DYN_RANGE;
-+typedef enum DP_YCBCR_RANGE {
-+	DP_YCBCR_RANGE_BT601_5                           = 0x0,
-+	DP_YCBCR_RANGE_BT709_5                           = 0x1,
-+} DP_YCBCR_RANGE;
-+typedef enum DP_COMPONENT_DEPTH {
-+	DP_COMPONENT_DEPTH_6BPC                          = 0x0,
-+	DP_COMPONENT_DEPTH_8BPC                          = 0x1,
-+	DP_COMPONENT_DEPTH_10BPC                         = 0x2,
-+	DP_COMPONENT_DEPTH_12BPC                         = 0x3,
-+	DP_COMPONENT_DEPTH_16BPC                         = 0x4,
-+	DP_COMPONENT_DEPTH_RESERVED                      = 0x5,
-+} DP_COMPONENT_DEPTH;
-+typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
-+	MSA_MISC0_OVERRIDE_DISABLE                       = 0x0,
-+	MSA_MISC0_OVERRIDE_ENABLE                        = 0x1,
-+} DP_MSA_MISC0_OVERRIDE_ENABLE;
-+typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
-+	MSA_MISC1_BIT7_OVERRIDE_DISABLE                  = 0x0,
-+	MSA_MISC1_BIT7_OVERRIDE_ENABLE                   = 0x1,
-+} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
-+typedef enum DP_UDI_LANES {
-+	DP_UDI_1_LANE                                    = 0x0,
-+	DP_UDI_2_LANES                                   = 0x1,
-+	DP_UDI_LANES_RESERVED                            = 0x2,
-+	DP_UDI_4_LANES                                   = 0x3,
-+} DP_UDI_LANES;
-+typedef enum DP_VID_STREAM_DIS_DEFER {
-+	DP_VID_STREAM_DIS_NO_DEFER                       = 0x0,
-+	DP_VID_STREAM_DIS_DEFER_TO_HBLANK                = 0x1,
-+	DP_VID_STREAM_DIS_DEFER_TO_VBLANK                = 0x2,
-+} DP_VID_STREAM_DIS_DEFER;
-+typedef enum DP_STEER_OVERFLOW_ACK {
-+	DP_STEER_OVERFLOW_ACK_NO_EFFECT                  = 0x0,
-+	DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT              = 0x1,
-+} DP_STEER_OVERFLOW_ACK;
-+typedef enum DP_STEER_OVERFLOW_MASK {
-+	DP_STEER_OVERFLOW_MASKED                         = 0x0,
-+	DP_STEER_OVERFLOW_UNMASK                         = 0x1,
-+} DP_STEER_OVERFLOW_MASK;
-+typedef enum DP_TU_OVERFLOW_ACK {
-+	DP_TU_OVERFLOW_ACK_NO_EFFECT                     = 0x0,
-+	DP_TU_OVERFLOW_ACK_CLR_INTERRUPT                 = 0x1,
-+} DP_TU_OVERFLOW_ACK;
-+typedef enum DP_VID_TIMING_MODE {
-+	DP_VID_TIMING_MODE_ASYNC                         = 0x0,
-+	DP_VID_TIMING_MODE_SYNC                          = 0x1,
-+} DP_VID_TIMING_MODE;
-+typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
-+	DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE      = 0x0,
-+	DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START          = 0x1,
-+} DP_VID_M_N_DOUBLE_BUFFER_MODE;
-+typedef enum DP_VID_M_N_GEN_EN {
-+	DP_VID_M_N_PROGRAMMED_VIA_REG                    = 0x0,
-+	DP_VID_M_N_CALC_AUTO                             = 0x1,
-+} DP_VID_M_N_GEN_EN;
-+typedef enum DP_VID_M_DOUBLE_VALUE_EN {
-+	DP_VID_M_INPUT_PIXEL_RATE                        = 0x0,
-+	DP_VID_M_DOUBLE_INPUT_PIXEL_RATE                 = 0x1,
-+} DP_VID_M_DOUBLE_VALUE_EN;
-+typedef enum DP_VID_ENHANCED_FRAME_MODE {
-+	VID_NORMAL_FRAME_MODE                            = 0x0,
-+	VID_ENHANCED_MODE                                = 0x1,
-+} DP_VID_ENHANCED_FRAME_MODE;
-+typedef enum DP_VID_MSA_TOP_FIELD_MODE {
-+	DP_TOP_FIELD_ONLY                                = 0x0,
-+	DP_TOP_PLUS_BOTTOM_FIELD                         = 0x1,
-+} DP_VID_MSA_TOP_FIELD_MODE;
-+typedef enum DP_VID_VBID_FIELD_POL {
-+	DP_VID_VBID_FIELD_POL_NORMAL                     = 0x0,
-+	DP_VID_VBID_FIELD_POL_INV                        = 0x1,
-+} DP_VID_VBID_FIELD_POL;
-+typedef enum DP_VID_STREAM_DISABLE_ACK {
-+	ID_STREAM_DISABLE_NO_ACK                         = 0x0,
-+	ID_STREAM_DISABLE_ACKED                          = 0x1,
-+} DP_VID_STREAM_DISABLE_ACK;
-+typedef enum DP_VID_STREAM_DISABLE_MASK {
-+	VID_STREAM_DISABLE_MASKED                        = 0x0,
-+	VID_STREAM_DISABLE_UNMASK                        = 0x1,
-+} DP_VID_STREAM_DISABLE_MASK;
-+typedef enum DPHY_ATEST_SEL_LANE0 {
-+	DPHY_ATEST_LANE0_PRBS_PATTERN                    = 0x0,
-+	DPHY_ATEST_LANE0_REG_PATTERN                     = 0x1,
-+} DPHY_ATEST_SEL_LANE0;
-+typedef enum DPHY_ATEST_SEL_LANE1 {
-+	DPHY_ATEST_LANE1_PRBS_PATTERN                    = 0x0,
-+	DPHY_ATEST_LANE1_REG_PATTERN                     = 0x1,
-+} DPHY_ATEST_SEL_LANE1;
-+typedef enum DPHY_ATEST_SEL_LANE2 {
-+	DPHY_ATEST_LANE2_PRBS_PATTERN                    = 0x0,
-+	DPHY_ATEST_LANE2_REG_PATTERN                     = 0x1,
-+} DPHY_ATEST_SEL_LANE2;
-+typedef enum DPHY_ATEST_SEL_LANE3 {
-+	DPHY_ATEST_LANE3_PRBS_PATTERN                    = 0x0,
-+	DPHY_ATEST_LANE3_REG_PATTERN                     = 0x1,
-+} DPHY_ATEST_SEL_LANE3;
-+typedef enum DPHY_BYPASS {
-+	DPHY_8B10B_OUTPUT                                = 0x0,
-+	DPHY_DBG_OUTPUT                                  = 0x1,
-+} DPHY_BYPASS;
-+typedef enum DPHY_SKEW_BYPASS {
-+	DPHY_WITH_SKEW                                   = 0x0,
-+	DPHY_NO_SKEW                                     = 0x1,
-+} DPHY_SKEW_BYPASS;
-+typedef enum DPHY_TRAINING_PATTERN_SEL {
-+	DPHY_TRAINING_PATTERN_1                          = 0x0,
-+	DPHY_TRAINING_PATTERN_2                          = 0x1,
-+	DPHY_TRAINING_PATTERN_3                          = 0x2,
-+	DPHY_TRAINING_PATTERN_4                          = 0x3,
-+} DPHY_TRAINING_PATTERN_SEL;
-+typedef enum DPHY_8B10B_RESET {
-+	DPHY_8B10B_NOT_RESET                             = 0x0,
-+	DPHY_8B10B_RESETET                               = 0x1,
-+} DPHY_8B10B_RESET;
-+typedef enum DP_DPHY_8B10B_EXT_DISP {
-+	DP_DPHY_8B10B_EXT_DISP_ZERO                      = 0x0,
-+	DP_DPHY_8B10B_EXT_DISP_ONE                       = 0x1,
-+} DP_DPHY_8B10B_EXT_DISP;
-+typedef enum DPHY_8B10B_CUR_DISP {
-+	DPHY_8B10B_CUR_DISP_ZERO                         = 0x0,
-+	DPHY_8B10B_CUR_DISP_ONE                          = 0x1,
-+} DPHY_8B10B_CUR_DISP;
-+typedef enum DPHY_PRBS_EN {
-+	DPHY_PRBS_DISABLE                                = 0x0,
-+	DPHY_PRBS_ENABLE                                 = 0x1,
-+} DPHY_PRBS_EN;
-+typedef enum DPHY_PRBS_SEL {
-+	DPHY_PRBS7_SELECTED                              = 0x0,
-+	DPHY_PRBS23_SELECTED                             = 0x1,
-+	DPHY_PRBS11_SELECTED                             = 0x2,
-+} DPHY_PRBS_SEL;
-+typedef enum DPHY_LOAD_BS_COUNT_START {
-+	DPHY_LOAD_BS_COUNT_STARTED                       = 0x0,
-+	DPHY_LOAD_BS_COUNT_NOT_STARTED                   = 0x1,
-+} DPHY_LOAD_BS_COUNT_START;
-+typedef enum DPHY_CRC_EN {
-+	DPHY_CRC_DISABLED                                = 0x0,
-+	DPHY_CRC_ENABLED                                 = 0x1,
-+} DPHY_CRC_EN;
-+typedef enum DPHY_CRC_CONT_EN {
-+	DPHY_CRC_ONE_SHOT                                = 0x0,
-+	DPHY_CRC_CONTINUOUS                              = 0x1,
-+} DPHY_CRC_CONT_EN;
-+typedef enum DPHY_CRC_FIELD {
-+	DPHY_CRC_START_FROM_TOP_FIELD                    = 0x0,
-+	DPHY_CRC_START_FROM_BOTTOM_FIELD                 = 0x1,
-+} DPHY_CRC_FIELD;
-+typedef enum DPHY_CRC_SEL {
-+	DPHY_CRC_LANE0_SELECTED                          = 0x0,
-+	DPHY_CRC_LANE1_SELECTED                          = 0x1,
-+	DPHY_CRC_LANE2_SELECTED                          = 0x2,
-+	DPHY_CRC_LANE3_SELECTED                          = 0x3,
-+} DPHY_CRC_SEL;
-+typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
-+	DPHY_FAST_TRAINING_NOT_CAPABLE_0                 = 0x0,
-+	DPHY_FAST_TRAINING_CAPABLE                       = 0x1,
-+} DPHY_RX_FAST_TRAINING_CAPABLE;
-+typedef enum DP_SEC_COLLISION_ACK {
-+	DP_SEC_COLLISION_ACK_NO_EFFECT                   = 0x0,
-+	DP_SEC_COLLISION_ACK_CLR_FLAG                    = 0x1,
-+} DP_SEC_COLLISION_ACK;
-+typedef enum DP_SEC_AUDIO_MUTE {
-+	DP_SEC_AUDIO_MUTE_HW_CTRL                        = 0x0,
-+	DP_SEC_AUDIO_MUTE_SW_CTRL                        = 0x1,
-+} DP_SEC_AUDIO_MUTE;
-+typedef enum DP_SEC_TIMESTAMP_MODE {
-+	DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE               = 0x0,
-+	DP_SEC_TIMESTAMP_AUTO_CALC_MODE                  = 0x1,
-+} DP_SEC_TIMESTAMP_MODE;
-+typedef enum DP_SEC_ASP_PRIORITY {
-+	DP_SEC_ASP_LOW_PRIORITY                          = 0x0,
-+	DP_SEC_ASP_HIGH_PRIORITY                         = 0x1,
-+} DP_SEC_ASP_PRIORITY;
-+typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
-+	DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ                 = 0x0,
-+	DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED        = 0x1,
-+} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
-+typedef enum DP_MSE_SAT_UPDATE_ACT {
-+	DP_MSE_SAT_UPDATE_NO_ACTION                      = 0x0,
-+	DP_MSE_SAT_UPDATE_WITH_TRIGGER                   = 0x1,
-+	DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER                = 0x2,
-+} DP_MSE_SAT_UPDATE_ACT;
-+typedef enum DP_MSE_LINK_LINE {
-+	DP_MSE_LINK_LINE_32_MTP_LONG                     = 0x0,
-+	DP_MSE_LINK_LINE_64_MTP_LONG                     = 0x1,
-+	DP_MSE_LINK_LINE_128_MTP_LONG                    = 0x2,
-+	DP_MSE_LINK_LINE_256_MTP_LONG                    = 0x3,
-+} DP_MSE_LINK_LINE;
-+typedef enum DP_MSE_BLANK_CODE {
-+	DP_MSE_BLANK_CODE_SF_FILLED                      = 0x0,
-+	DP_MSE_BLANK_CODE_ZERO_FILLED                    = 0x1,
-+} DP_MSE_BLANK_CODE;
-+typedef enum DP_MSE_TIMESTAMP_MODE {
-+	DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE         = 0x0,
-+	DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE           = 0x1,
-+} DP_MSE_TIMESTAMP_MODE;
-+typedef enum DP_MSE_ZERO_ENCODER {
-+	DP_MSE_NOT_ZERO_FE_ENCODER                       = 0x0,
-+	DP_MSE_ZERO_FE_ENCODER                           = 0x1,
-+} DP_MSE_ZERO_ENCODER;
-+typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
-+	DP_MSE_OUTPUT_DPDBG_DATA_DIS                     = 0x0,
-+	DP_MSE_OUTPUT_DPDBG_DATA_EN                      = 0x1,
-+} DP_MSE_OUTPUT_DPDBG_DATA;
-+typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
-+	DP_DPHY_HBR2_PASS_THROUGH                        = 0x0,
-+	DP_DPHY_HBR2_PATTERN_1                           = 0x1,
-+	DP_DPHY_HBR2_PATTERN_2_NEG                       = 0x2,
-+	DP_DPHY_HBR2_PATTERN_3                           = 0x3,
-+	DP_DPHY_HBR2_PATTERN_2_POS                       = 0x6,
-+} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
-+typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
-+	DPHY_CRC_MST_PHASE_ERROR_NO_ACK                  = 0x0,
-+	DPHY_CRC_MST_PHASE_ERROR_ACKED                   = 0x1,
-+} DPHY_CRC_MST_PHASE_ERROR_ACK;
-+typedef enum DPHY_SW_FAST_TRAINING_START {
-+	DPHY_SW_FAST_TRAINING_NOT_STARTED                = 0x0,
-+	DPHY_SW_FAST_TRAINING_STARTED                    = 0x1,
-+} DPHY_SW_FAST_TRAINING_START;
-+typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
-+	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
-+	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
-+} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
-+typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
-+	DP_DPHY_FAST_TRAINING_COMPLETE_MASKED            = 0x0,
-+	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED        = 0x1,
-+} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
-+typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
-+	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED         = 0x0,
-+	DP_DPHY_FAST_TRAINING_COMPLETE_ACKED             = 0x1,
-+} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
-+typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
-+	MSA_V_TIMING_OVERRIDE_DISABLED                   = 0x0,
-+	MSA_V_TIMING_OVERRIDE_ENABLED                    = 0x1,
-+} DP_MSA_V_TIMING_OVERRIDE_EN;
-+typedef enum DP_SEC_GSP0_PRIORITY {
-+	SEC_GSP0_PRIORITY_LOW                            = 0x0,
-+	SEC_GSP0_PRIORITY_HIGH                           = 0x1,
-+} DP_SEC_GSP0_PRIORITY;
-+typedef enum DP_SEC_GSP0_SEND {
-+	NOT_SENT                                         = 0x0,
-+	FORCE_SENT                                       = 0x1,
-+} DP_SEC_GSP0_SEND;
-+typedef enum DP_AUX_CONTROL_HPD_SEL {
-+	DP_AUX_CONTROL_HPD1_SELECTED                     = 0x0,
-+	DP_AUX_CONTROL_HPD2_SELECTED                     = 0x1,
-+	DP_AUX_CONTROL_HPD3_SELECTED                     = 0x2,
-+	DP_AUX_CONTROL_HPD4_SELECTED                     = 0x3,
-+	DP_AUX_CONTROL_HPD5_SELECTED                     = 0x4,
-+	DP_AUX_CONTROL_HPD6_SELECTED                     = 0x5,
-+} DP_AUX_CONTROL_HPD_SEL;
-+typedef enum DP_AUX_CONTROL_TEST_MODE {
-+	DP_AUX_CONTROL_TEST_MODE_DISABLE                 = 0x0,
-+	DP_AUX_CONTROL_TEST_MODE_ENABLE                  = 0x1,
-+} DP_AUX_CONTROL_TEST_MODE;
-+typedef enum DP_AUX_SW_CONTROL_SW_GO {
-+	DP_AUX_SW_CONTROL_SW__NOT_GO                     = 0x0,
-+	DP_AUX_SW_CONTROL_SW__GO                         = 0x1,
-+} DP_AUX_SW_CONTROL_SW_GO;
-+typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
-+	DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG              = 0x0,
-+	DP_AUX_SW_CONTROL_LS_READ__TRIG                  = 0x1,
-+} DP_AUX_SW_CONTROL_LS_READ_TRIG;
-+typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
-+	DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW       = 0x0,
-+	DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW       = 0x1,
-+	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC       = 0x2,
-+	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS       = 0x3,
-+} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
-+typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
-+	DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ          = 0x0,
-+	DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ              = 0x1,
-+} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
-+typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
-+	DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG       = 0x0,
-+	DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG           = 0x1,
-+} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
-+typedef enum DP_AUX_INT_ACK {
-+	DP_AUX_INT__NOT_ACK                              = 0x0,
-+	DP_AUX_INT__ACK                                  = 0x1,
-+} DP_AUX_INT_ACK;
-+typedef enum DP_AUX_LS_UPDATE_ACK {
-+	DP_AUX_INT_LS_UPDATE_NOT_ACK                     = 0x0,
-+	DP_AUX_INT_LS_UPDATE_ACK                         = 0x1,
-+} DP_AUX_LS_UPDATE_ACK;
-+typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
-+	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
-+	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
-+} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
-+typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
-+	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ         = 0x0,
-+	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ         = 0x1,
-+	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ         = 0x2,
-+	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ         = 0x3,
-+} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
-+typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US        = 0x0,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US        = 0x1,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US       = 0x2,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US       = 0x3,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US       = 0x4,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US       = 0x5,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US       = 0x6,
-+	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US       = 0x7,
-+} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
-+typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
-+	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0   = 0x0,
-+	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
-+	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
-+	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
-+	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
-+	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
-+} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
-+	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
-+} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
-+	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
-+} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
-+	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
-+	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
-+	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
-+	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
-+} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
-+	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
-+	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
-+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
-+	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
-+	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
-+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
-+	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
-+	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
-+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
-+	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
-+	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
-+	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
-+	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
-+} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
-+typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US         = 0x0,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US         = 0x1,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US         = 0x2,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US         = 0x3,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US         = 0x4,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US         = 0x5,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US         = 0x6,
-+	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US         = 0x7,
-+} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
-+typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2         = 0x0,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4         = 0x1,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8         = 0x2,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16       = 0x3,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32       = 0x4,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64       = 0x5,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128     = 0x6,
-+	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256     = 0x7,
-+} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
-+typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
-+	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
-+	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
-+} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
-+typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
-+	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
-+	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
-+	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
-+	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
-+} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
-+typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
-+	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
-+	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
-+	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
-+	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
-+} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
-+typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
-+	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
-+	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
-+	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
-+	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
-+} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
-+typedef enum DP_AUX_ERR_OCCURRED_ACK {
-+	DP_AUX_ERR_OCCURRED__NOT_ACK                     = 0x0,
-+	DP_AUX_ERR_OCCURRED__ACK                         = 0x1,
-+} DP_AUX_ERR_OCCURRED_ACK;
-+typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
-+	DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK            = 0x0,
-+	DP_AUX_POTENTIAL_ERR_REACHED__ACK                = 0x1,
-+} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
-+typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
-+	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK        = 0x0,
-+	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK            = 0x1,
-+} DP_AUX_DEFINITE_ERR_REACHED_ACK;
-+typedef enum DP_AUX_RESET {
-+	DP_AUX_RESET_DEASSERTED                          = 0x0,
-+	DP_AUX_RESET_ASSERTED                            = 0x1,
-+} DP_AUX_RESET;
-+typedef enum DP_AUX_RESET_DONE {
-+	DP_AUX_RESET_SEQUENCE_NOT_DONE                   = 0x0,
-+	DP_AUX_RESET_SEQUENCE_DONE                       = 0x1,
-+} DP_AUX_RESET_DONE;
-+typedef enum FBC_IDLE_MASK_MASK_BITS {
-+	FBC_IDLE_MASK_DISP_REG_UPDATE                    = 0x0,
-+	FBC_IDLE_MASK_RESERVED1                          = 0x1,
-+	FBC_IDLE_MASK_FBC_GRPH_COMP_EN                   = 0x2,
-+	FBC_IDLE_MASK_FBC_MIN_COMPRESSION                = 0x3,
-+	FBC_IDLE_MASK_FBC_ALPHA_COMP_EN                  = 0x4,
-+	FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN       = 0x5,
-+	FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF         = 0x6,
-+	FBC_IDLE_MASK_RESERVED7                          = 0x7,
-+	FBC_IDLE_MASK_RESERVED8                          = 0x8,
-+	FBC_IDLE_MASK_RESERVED9                          = 0x9,
-+	FBC_IDLE_MASK_RESERVED10                         = 0xa,
-+	FBC_IDLE_MASK_RESERVED11                         = 0xb,
-+	FBC_IDLE_MASK_RESERVED12                         = 0xc,
-+	FBC_IDLE_MASK_RESERVED13                         = 0xd,
-+	FBC_IDLE_MASK_RESERVED14                         = 0xe,
-+	FBC_IDLE_MASK_RESERVED15                         = 0xf,
-+	FBC_IDLE_MASK_RESERVED16                         = 0x10,
-+	FBC_IDLE_MASK_RESERVED17                         = 0x11,
-+	FBC_IDLE_MASK_RESERVED18                         = 0x12,
-+	FBC_IDLE_MASK_RESERVED19                         = 0x13,
-+	FBC_IDLE_MASK_RESERVED20                         = 0x14,
-+	FBC_IDLE_MASK_RESERVED21                         = 0x15,
-+	FBC_IDLE_MASK_RESERVED22                         = 0x16,
-+	FBC_IDLE_MASK_RESERVED23                         = 0x17,
-+	FBC_IDLE_MASK_MC_HIT_REGION_0                    = 0x18,
-+	FBC_IDLE_MASK_MC_HIT_REGION_1                    = 0x19,
-+	FBC_IDLE_MASK_MC_HIT_REGION_2                    = 0x1a,
-+	FBC_IDLE_MASK_MC_HIT_REGION_3                    = 0x1b,
-+	FBC_IDLE_MASK_MC_WRITE                           = 0x1c,
-+	FBC_IDLE_MASK_CG_STATIC_SCREEN                   = 0x1d,
-+	FBC_IDLE_MASK_RESERVED30                         = 0x1e,
-+	FBC_IDLE_MASK_RESERVED31                         = 0x1f,
-+} FBC_IDLE_MASK_MASK_BITS;
-+typedef enum FMT_CONTROL_PIXEL_ENCODING {
-+	FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444    = 0x0,
-+	FMT_CONTROL_PIXEL_ENCODING_YCBCR422              = 0x1,
-+	FMT_CONTROL_PIXEL_ENCODING_YCBCR420              = 0x2,
-+	FMT_CONTROL_PIXEL_ENCODING_RESERVED              = 0x3,
-+} FMT_CONTROL_PIXEL_ENCODING;
-+typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
-+	FMT_CONTROL_SUBSAMPLING_MODE_DROP                = 0x0,
-+	FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE             = 0x1,
-+	FMT_CONTROL_SUBSAMPLING_MODE_3_TAP               = 0x2,
-+	FMT_CONTROL_SUBSAMPLING_MODE_RESERVED            = 0x3,
-+} FMT_CONTROL_SUBSAMPLING_MODE;
-+typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
-+	FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR       = 0x0,
-+	FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB       = 0x1,
-+} FMT_CONTROL_SUBSAMPLING_ORDER;
-+typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
-+	FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE    = 0x0,
-+	FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE     = 0x1,
-+} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
-+typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
-+	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION   = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING     = 0x1,
-+} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
-+typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
-+	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP       = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP       = 0x1,
-+	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP       = 0x2,
-+} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
-+typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
-+	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
-+	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
-+} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
-+typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
-+	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
-+	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
-+	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
-+} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
-+typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
-+	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
-+} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
-+typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
-+	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei               = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi               = 0x1,
-+	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi               = 0x2,
-+	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED         = 0x3,
-+} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
-+typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
-+	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A                = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B                = 0x1,
-+	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C                = 0x2,
-+	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D                = 0x3,
-+} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
-+typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
-+	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E                = 0x0,
-+	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F                = 0x1,
-+	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G                = 0x2,
-+	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED         = 0x3,
-+} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
-+typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
-+	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
-+	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
-+} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
-+typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
-+	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
-+	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
-+} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
-+typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC                 = 0x0,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC                 = 0x1,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC                = 0x2,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC                = 0x3,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1            = 0x4,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2            = 0x5,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3            = 0x6,
-+	FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE         = 0x7,
-+} FMT_CLAMP_CNTL_COLOR_FORMAT;
-+typedef enum FMT_CRC_CNTL_CONT_EN {
-+	FMT_CRC_CNTL_CONT_EN_ONE_SHOT                    = 0x0,
-+	FMT_CRC_CNTL_CONT_EN_CONT                        = 0x1,
-+} FMT_CRC_CNTL_CONT_EN;
-+typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
-+	FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE        = 0x0,
-+	FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE            = 0x1,
-+} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
-+typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
-+	FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD            = 0x0,
-+	FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK               = 0x1,
-+} FMT_CRC_CNTL_ONLY_BLANKB;
-+typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
-+	FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL              = 0x0,
-+	FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC         = 0x1,
-+} FMT_CRC_CNTL_PSR_MODE_ENABLE;
-+typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
-+	FMT_CRC_CNTL_INTERLACE_MODE_TOP                  = 0x0,
-+	FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM               = 0x1,
-+	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM          = 0x2,
-+	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH            = 0x3,
-+} FMT_CRC_CNTL_INTERLACE_MODE;
-+typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
-+	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL             = 0x0,
-+	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN        = 0x1,
-+} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
-+typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
-+	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN            = 0x0,
-+	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD             = 0x1,
-+} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
-+typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
-+	FMT_DEBUG_CNTL_COLOR_SELECT_BLUE                 = 0x0,
-+	FMT_DEBUG_CNTL_COLOR_SELECT_GREEN                = 0x1,
-+	FMT_DEBUG_CNTL_COLOR_SELECT_RED1                 = 0x2,
-+	FMT_DEBUG_CNTL_COLOR_SELECT_RED2                 = 0x3,
-+} FMT_DEBUG_CNTL_COLOR_SELECT;
-+typedef enum FMT_SPATIAL_DITHER_MODE {
-+	FMT_SPATIAL_DITHER_MODE_0                        = 0x0,
-+	FMT_SPATIAL_DITHER_MODE_1                        = 0x1,
-+	FMT_SPATIAL_DITHER_MODE_2                        = 0x2,
-+	FMT_SPATIAL_DITHER_MODE_3                        = 0x3,
-+} FMT_SPATIAL_DITHER_MODE;
-+typedef enum FMT_STEREOSYNC_OVR_POL {
-+	FMT_STEREOSYNC_OVR_POL_INVERTED                  = 0x0,
-+	FMT_STEREOSYNC_OVR_POL_NOT_INVERTED              = 0x1,
-+} FMT_STEREOSYNC_OVR_POL;
-+typedef enum FMT_DYNAMIC_EXP_MODE {
-+	FMT_DYNAMIC_EXP_MODE_10to12                      = 0x0,
-+	FMT_DYNAMIC_EXP_MODE_8to12                       = 0x1,
-+} FMT_DYNAMIC_EXP_MODE;
-+typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
-+	LB_DATA_FORMAT_PIXEL_DEPTH_30BPP                 = 0x0,
-+	LB_DATA_FORMAT_PIXEL_DEPTH_24BPP                 = 0x1,
-+	LB_DATA_FORMAT_PIXEL_DEPTH_18BPP                 = 0x2,
-+	LB_DATA_FORMAT_PIXEL_DEPTH_36BPP                 = 0x3,
-+} LB_DATA_FORMAT_PIXEL_DEPTH;
-+typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
-+	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
-+	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
-+} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
-+typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
-+	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION      = 0x0,
-+	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING        = 0x1,
-+} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
-+typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
-+	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP         = 0x0,
-+	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP         = 0x1,
-+} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
-+typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
-+	LB_DATA_FORMAT_INTERLEAVE_DISABLE                = 0x0,
-+	LB_DATA_FORMAT_INTERLEAVE_ENABLE                 = 0x1,
-+} LB_DATA_FORMAT_INTERLEAVE_EN;
-+typedef enum LB_DATA_FORMAT_PREFILL_EN {
-+	LB_DATA_FORMAT_PREFILL_DISABLE                   = 0x0,
-+	LB_DATA_FORMAT_PREFILL_ENABLE                    = 0x1,
-+} LB_DATA_FORMAT_PREFILL_EN;
-+typedef enum LB_DATA_FORMAT_REQUEST_MODE {
-+	LB_DATA_FORMAT_REQUEST_MODE_NORMAL               = 0x0,
-+	LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE        = 0x1,
-+} LB_DATA_FORMAT_REQUEST_MODE;
-+typedef enum LB_DATA_FORMAT_ALPHA_EN {
-+	LB_DATA_FORMAT_ALPHA_DISABLE                     = 0x0,
-+	LB_DATA_FORMAT_ALPHA_ENABLE                      = 0x1,
-+} LB_DATA_FORMAT_ALPHA_EN;
-+typedef enum LB_VLINE_START_END_VLINE_INV {
-+	LB_VLINE_START_END_VLINE_NORMAL                  = 0x0,
-+	LB_VLINE_START_END_VLINE_INVERSE                 = 0x1,
-+} LB_VLINE_START_END_VLINE_INV;
-+typedef enum LB_VLINE2_START_END_VLINE2_INV {
-+	LB_VLINE2_START_END_VLINE2_NORMAL                = 0x0,
-+	LB_VLINE2_START_END_VLINE2_INVERSE               = 0x1,
-+} LB_VLINE2_START_END_VLINE2_INV;
-+typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
-+	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE       = 0x0,
-+	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE        = 0x1,
-+} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
-+typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
-+	LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE        = 0x0,
-+	LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE         = 0x1,
-+} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
-+typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
-+	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE       = 0x0,
-+	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE        = 0x1,
-+} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
-+typedef enum LB_VLINE_STATUS_VLINE_ACK {
-+	LB_VLINE_STATUS_VLINE_NORMAL                     = 0x0,
-+	LB_VLINE_STATUS_VLINE_CLEAR                      = 0x1,
-+} LB_VLINE_STATUS_VLINE_ACK;
-+typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
-+	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
-+	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
-+} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
-+typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
-+	LB_VLINE2_STATUS_VLINE2_NORMAL                   = 0x0,
-+	LB_VLINE2_STATUS_VLINE2_CLEAR                    = 0x1,
-+} LB_VLINE2_STATUS_VLINE2_ACK;
-+typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
-+	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
-+	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
-+} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
-+typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
-+	LB_VBLANK_STATUS_VBLANK_NORMAL                   = 0x0,
-+	LB_VBLANK_STATUS_VBLANK_CLEAR                    = 0x1,
-+} LB_VBLANK_STATUS_VBLANK_ACK;
-+typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
-+	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
-+	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
-+} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
-+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
-+	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE      = 0x0,
-+	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
-+	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
-+	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
-+} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
-+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
-+	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x0,
-+	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC   = 0x1,
-+} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
-+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
-+	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS     = 0x0,
-+	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS     = 0x1,
-+	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS     = 0x2,
-+	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS    = 0x3,
-+} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
-+typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
-+	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE       = 0x0,
-+	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE        = 0x1,
-+} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
-+typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
-+	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
-+	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
-+} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
-+typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
-+	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL          = 0x0,
-+	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET           = 0x1,
-+} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
-+typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
-+	LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL           = 0x0,
-+	LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET            = 0x1,
-+} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
-+typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
-+	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
-+	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
-+} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
-+typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
-+	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
-+	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
-+} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
-+typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
-+	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
-+	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
-+} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
-+typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
-+	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
-+	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
-+	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
-+} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
-+typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
-+	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
-+	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN     = 0x1,
-+} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
-+typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
-+	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
-+	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
-+} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
-+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
-+	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
-+	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
-+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
-+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
-+	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
-+	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
-+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
-+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
-+	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
-+	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
-+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
-+typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
-+	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
-+	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
-+} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
-+typedef enum LBV_PIXEL_DEPTH {
-+	PIXEL_DEPTH_30BPP                                = 0x0,
-+	PIXEL_DEPTH_24BPP                                = 0x1,
-+	PIXEL_DEPTH_18BPP                                = 0x2,
-+	PIXEL_DEPTH_38BPP                                = 0x3,
-+} LBV_PIXEL_DEPTH;
-+typedef enum LBV_PIXEL_EXPAN_MODE {
-+	PIXEL_EXPAN_MODE_ZERO_EXP                        = 0x0,
-+	PIXEL_EXPAN_MODE_DYN_EXP                         = 0x1,
-+} LBV_PIXEL_EXPAN_MODE;
-+typedef enum LBV_INTERLEAVE_EN {
-+	INTERLEAVE_DIS                                   = 0x0,
-+	INTERLEAVE_EN                                    = 0x1,
-+} LBV_INTERLEAVE_EN;
-+typedef enum LBV_PIXEL_REDUCE_MODE {
-+	PIXEL_REDUCE_MODE_TRUNCATION                     = 0x0,
-+	PIXEL_REDUCE_MODE_ROUNDING                       = 0x1,
-+} LBV_PIXEL_REDUCE_MODE;
-+typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
-+	DYNAMIC_PIXEL_DEPTH_36BPP                        = 0x0,
-+	DYNAMIC_PIXEL_DEPTH_30BPP                        = 0x1,
-+} LBV_DYNAMIC_PIXEL_DEPTH;
-+typedef enum LBV_DITHER_EN {
-+	DITHER_DIS                                       = 0x0,
-+	DITHER_EN                                        = 0x1,
-+} LBV_DITHER_EN;
-+typedef enum LBV_DOWNSCALE_PREFETCH_EN {
-+	DOWNSCALE_PREFETCH_DIS                           = 0x0,
-+	DOWNSCALE_PREFETCH_EN                            = 0x1,
-+} LBV_DOWNSCALE_PREFETCH_EN;
-+typedef enum LBV_MEMORY_CONFIG {
-+	MEMORY_CONFIG_0                                  = 0x0,
-+	MEMORY_CONFIG_1                                  = 0x1,
-+	MEMORY_CONFIG_2                                  = 0x2,
-+	MEMORY_CONFIG_3                                  = 0x3,
-+} LBV_MEMORY_CONFIG;
-+typedef enum LBV_SYNC_RESET_SEL2 {
-+	SYNC_RESET_SEL2_VBLANK                           = 0x0,
-+	SYNC_RESET_SEL2_VSYNC                            = 0x1,
-+} LBV_SYNC_RESET_SEL2;
-+typedef enum LBV_SYNC_DURATION {
-+	SYNC_DURATION_16                                 = 0x0,
-+	SYNC_DURATION_32                                 = 0x1,
-+	SYNC_DURATION_64                                 = 0x2,
-+	SYNC_DURATION_128                                = 0x3,
-+} LBV_SYNC_DURATION;
-+typedef enum SCL_C_RAM_TAP_PAIR_IDX {
-+	SCL_C_RAM_TAP_PAIR_ID0                           = 0x0,
-+	SCL_C_RAM_TAP_PAIR_ID1                           = 0x1,
-+	SCL_C_RAM_TAP_PAIR_ID2                           = 0x2,
-+	SCL_C_RAM_TAP_PAIR_ID3                           = 0x3,
-+	SCL_C_RAM_TAP_PAIR_ID4                           = 0x4,
-+} SCL_C_RAM_TAP_PAIR_IDX;
-+typedef enum SCL_C_RAM_PHASE {
-+	SCL_C_RAM_PHASE_0                                = 0x0,
-+	SCL_C_RAM_PHASE_1                                = 0x1,
-+	SCL_C_RAM_PHASE_2                                = 0x2,
-+	SCL_C_RAM_PHASE_3                                = 0x3,
-+	SCL_C_RAM_PHASE_4                                = 0x4,
-+	SCL_C_RAM_PHASE_5                                = 0x5,
-+	SCL_C_RAM_PHASE_6                                = 0x6,
-+	SCL_C_RAM_PHASE_7                                = 0x7,
-+	SCL_C_RAM_PHASE_8                                = 0x8,
-+} SCL_C_RAM_PHASE;
-+typedef enum SCL_C_RAM_FILTER_TYPE {
-+	SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT          = 0x0,
-+	SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT            = 0x1,
-+	SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT          = 0x2,
-+	SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT            = 0x3,
-+} SCL_C_RAM_FILTER_TYPE;
-+typedef enum SCL_MODE_SEL {
-+	SCL_MODE_RGB_BYPASS                              = 0x0,
-+	SCL_MODE_RGB_SCALING                             = 0x1,
-+	SCL_MODE_YCBCR_SCALING                           = 0x2,
-+	SCL_MODE_YCBCR_BYPASS                            = 0x3,
-+} SCL_MODE_SEL;
-+typedef enum SCL_PSCL_EN {
-+	SCL_PSCL_DISABLE                                 = 0x0,
-+	SCL_PSCL_ENANBLE                                 = 0x1,
-+} SCL_PSCL_EN;
-+typedef enum SCL_V_NUM_OF_TAPS {
-+	SCL_V_NUM_OF_TAPS_1                              = 0x0,
-+	SCL_V_NUM_OF_TAPS_2                              = 0x1,
-+	SCL_V_NUM_OF_TAPS_3                              = 0x2,
-+	SCL_V_NUM_OF_TAPS_4                              = 0x3,
-+	SCL_V_NUM_OF_TAPS_5                              = 0x4,
-+	SCL_V_NUM_OF_TAPS_6                              = 0x5,
-+} SCL_V_NUM_OF_TAPS;
-+typedef enum SCL_H_NUM_OF_TAPS {
-+	SCL_H_NUM_OF_TAPS_1                              = 0x0,
-+	SCL_H_NUM_OF_TAPS_2                              = 0x1,
-+	SCL_H_NUM_OF_TAPS_4                              = 0x3,
-+	SCL_H_NUM_OF_TAPS_6                              = 0x5,
-+	SCL_H_NUM_OF_TAPS_8                              = 0x7,
-+	SCL_H_NUM_OF_TAPS_10                             = 0x9,
-+} SCL_H_NUM_OF_TAPS;
-+typedef enum SCL_BOUNDARY_MODE {
-+	SCL_BOUNDARY_MODE_BLACK                          = 0x0,
-+	SCL_BOUNDARY_MODE_EDGE                           = 0x1,
-+} SCL_BOUNDARY_MODE;
-+typedef enum SCL_EARLY_EOL_MOD {
-+	SCL_EARLY_EOL_MODE_CRTC                          = 0x0,
-+	SCL_EARLY_EOL_MODE_INTERNAL                      = 0x1,
-+} SCL_EARLY_EOL_MOD;
-+typedef enum SCL_BYPASS_MODE {
-+	SCL_BYPASS_MODE_MC_MR                            = 0x0,
-+	SCL_BYPASS_MODE_AC_NR                            = 0x1,
-+	SCL_BYPASS_MODE_AC_AR                            = 0x2,
-+	SCL_BYPASS_MODE_RESERVED                         = 0x3,
-+} SCL_BYPASS_MODE;
-+typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
-+	SCL_V_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
-+	SCL_V_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
-+} SCL_V_MANUAL_REPLICATE_FACTOR;
-+typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
-+	SCL_H_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
-+	SCL_H_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
-+} SCL_H_MANUAL_REPLICATE_FACTOR;
-+typedef enum SCL_V_CALC_AUTO_RATIO_EN {
-+	SCL_V_CALC_AUTO_RATIO_DISABLE                    = 0x0,
-+	SCL_V_CALC_AUTO_RATIO_ENABLE                     = 0x1,
-+} SCL_V_CALC_AUTO_RATIO_EN;
-+typedef enum SCL_H_CALC_AUTO_RATIO_EN {
-+	SCL_H_CALC_AUTO_RATIO_DISABLE                    = 0x0,
-+	SCL_H_CALC_AUTO_RATIO_ENABLE                     = 0x1,
-+} SCL_H_CALC_AUTO_RATIO_EN;
-+typedef enum SCL_H_FILTER_PICK_NEAREST {
-+	SCL_H_FILTER_PICK_NEAREST_DISABLE                = 0x0,
-+	SCL_H_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
-+} SCL_H_FILTER_PICK_NEAREST;
-+typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
-+	SCL_H_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
-+	SCL_H_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
-+} SCL_H_2TAP_HARDCODE_COEF_EN;
-+typedef enum SCL_V_FILTER_PICK_NEAREST {
-+	SCL_V_FILTER_PICK_NEAREST_DISABLE                = 0x0,
-+	SCL_V_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
-+} SCL_V_FILTER_PICK_NEAREST;
-+typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
-+	SCL_V_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
-+	SCL_V_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
-+} SCL_V_2TAP_HARDCODE_COEF_EN;
-+typedef enum SCL_UPDATE_TAKEN {
-+	SCL_UPDATE_TAKEN_NO                              = 0x0,
-+	SCL_UPDATE_TAKEN_YES                             = 0x1,
-+} SCL_UPDATE_TAKEN;
-+typedef enum SCL_UPDATE_LOCK {
-+	SCL_UPDATE_UNLOCKED                              = 0x0,
-+	SCL_UPDATE_LOCKED                                = 0x1,
-+} SCL_UPDATE_LOCK;
-+typedef enum SCL_COEF_UPDATE_COMPLETE {
-+	SCL_COEF_UPDATE_NOT_COMPLETED                    = 0x0,
-+	SCL_COEF_UPDATE_COMPLETED                        = 0x1,
-+} SCL_COEF_UPDATE_COMPLETE;
-+typedef enum SCL_HF_SHARP_SCALE_FACTOR {
-+	SCL_HF_SHARP_SCALE_FACTOR_0                      = 0x0,
-+	SCL_HF_SHARP_SCALE_FACTOR_1                      = 0x1,
-+	SCL_HF_SHARP_SCALE_FACTOR_2                      = 0x2,
-+	SCL_HF_SHARP_SCALE_FACTOR_3                      = 0x3,
-+	SCL_HF_SHARP_SCALE_FACTOR_4                      = 0x4,
-+	SCL_HF_SHARP_SCALE_FACTOR_5                      = 0x5,
-+	SCL_HF_SHARP_SCALE_FACTOR_6                      = 0x6,
-+	SCL_HF_SHARP_SCALE_FACTOR_7                      = 0x7,
-+} SCL_HF_SHARP_SCALE_FACTOR;
-+typedef enum SCL_HF_SHARP_EN {
-+	SCL_HF_SHARP_DISABLE                             = 0x0,
-+	SCL_HF_SHARP_ENABLE                              = 0x1,
-+} SCL_HF_SHARP_EN;
-+typedef enum SCL_VF_SHARP_SCALE_FACTOR {
-+	SCL_VF_SHARP_SCALE_FACTOR_0                      = 0x0,
-+	SCL_VF_SHARP_SCALE_FACTOR_1                      = 0x1,
-+	SCL_VF_SHARP_SCALE_FACTOR_2                      = 0x2,
-+	SCL_VF_SHARP_SCALE_FACTOR_3                      = 0x3,
-+	SCL_VF_SHARP_SCALE_FACTOR_4                      = 0x4,
-+	SCL_VF_SHARP_SCALE_FACTOR_5                      = 0x5,
-+	SCL_VF_SHARP_SCALE_FACTOR_6                      = 0x6,
-+	SCL_VF_SHARP_SCALE_FACTOR_7                      = 0x7,
-+} SCL_VF_SHARP_SCALE_FACTOR;
-+typedef enum SCL_VF_SHARP_EN {
-+	SCL_VF_SHARP_DISABLE                             = 0x0,
-+	SCL_VF_SHARP_ENABLE                              = 0x1,
-+} SCL_VF_SHARP_EN;
-+typedef enum SCL_ALU_DISABLE {
-+	SCL_ALU_ENABLED                                  = 0x0,
-+	SCL_ALU_DISABLED                                 = 0x1,
-+} SCL_ALU_DISABLE;
-+typedef enum SCL_HOST_CONFLICT_MASK {
-+	SCL_HOST_CONFLICT_DISABLE_INTERRUPT              = 0x0,
-+	SCL_HOST_CONFLICT_ENABLE_INTERRUPT               = 0x1,
-+} SCL_HOST_CONFLICT_MASK;
-+typedef enum SCL_SCL_MODE_CHANGE_MASK {
-+	SCL_MODE_CHANGE_DISABLE_INTERRUPT                = 0x0,
-+	SCL_MODE_CHANGE_ENABLE_INTERRUPT                 = 0x1,
-+} SCL_SCL_MODE_CHANGE_MASK;
-+typedef enum SCLV_MODE_SEL {
-+	SCLV_MODE_RGB_BYPASS                             = 0x0,
-+	SCLV_MODE_RGB_SCALING                            = 0x1,
-+	SCLV_MODE_YCBCR_SCALING                          = 0x2,
-+	SCLV_MODE_YCBCR_BYPASS                           = 0x3,
-+} SCLV_MODE_SEL;
-+typedef enum SCLV_INTERLACE_SOURCE {
-+	INTERLACE_SOURCE_PROGRESSIVE                     = 0x0,
-+	INTERLACE_SOURCE_INTERLEAVE                      = 0x1,
-+	INTERLACE_SOURCE_STACK                           = 0x2,
-+} SCLV_INTERLACE_SOURCE;
-+typedef enum SCLV_UPDATE_LOCK {
-+	UPDATE_UNLOCKED                                  = 0x0,
-+	UPDATE_LOCKED                                    = 0x1,
-+} SCLV_UPDATE_LOCK;
-+typedef enum SCLV_COEF_UPDATE_COMPLETE {
-+	COEF_UPDATE_NOT_COMPLETE                         = 0x0,
-+	COEF_UPDATE_COMPLETE                             = 0x1,
-+} SCLV_COEF_UPDATE_COMPLETE;
-+typedef enum COL_MAN_UPDATE_LOCK {
-+	COL_MAN_UPDATE_UNLOCKED                          = 0x0,
-+	COL_MAN_UPDATE_LOCKED                            = 0x1,
-+} COL_MAN_UPDATE_LOCK;
-+typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
-+	COL_MAN_MULTIPLE_UPDATE                          = 0x0,
-+	COL_MAN_MULTIPLE_UPDAT_EDISABLE                  = 0x1,
-+} COL_MAN_DISABLE_MULTIPLE_UPDATE;
-+typedef enum COL_MAN_INPUTCSC_MODE {
-+	INPUTCSC_MODE_BYPASS                             = 0x0,
-+	INPUTCSC_MODE_A                                  = 0x1,
-+	INPUTCSC_MODE_B                                  = 0x2,
-+	INPUTCSC_MODE_UNITY                              = 0x3,
-+} COL_MAN_INPUTCSC_MODE;
-+typedef enum COL_MAN_INPUTCSC_TYPE {
-+	INPUTCSC_TYPE_12_0                               = 0x0,
-+	INPUTCSC_TYPE_10_2                               = 0x1,
-+	INPUTCSC_TYPE_8_4                                = 0x2,
-+} COL_MAN_INPUTCSC_TYPE;
-+typedef enum COL_MAN_INPUTCSC_CONVERT {
-+	INPUTCSC_ROUND                                   = 0x0,
-+	INPUTCSC_TRUNCATE                                = 0x1,
-+} COL_MAN_INPUTCSC_CONVERT;
-+typedef enum COL_MAN_PRESCALE_MODE {
-+	PRESCALE_MODE_BYPASS                             = 0x0,
-+	PRESCALE_MODE_PROGRAM                            = 0x1,
-+	PRESCALE_MODE_UNITY                              = 0x2,
-+} COL_MAN_PRESCALE_MODE;
-+typedef enum COL_MAN_INPUT_GAMMA_MODE {
-+	INGAMMA_MODE_BYPASS                              = 0x0,
-+	INGAMMA_MODE_FIX                                 = 0x1,
-+	INGAMMA_MODE_FLOAT                               = 0x2,
-+} COL_MAN_INPUT_GAMMA_MODE;
-+typedef enum COL_MAN_OUTPUT_CSC_MODE {
-+	COL_MAN_OUTPUT_CSC_BYPASS                        = 0x0,
-+	COL_MAN_OUTPUT_CSC_RGB                           = 0x1,
-+	COL_MAN_OUTPUT_CSC_YCrCb601                      = 0x2,
-+	COL_MAN_OUTPUT_CSC_YCrCb709                      = 0x3,
-+	COL_MAN_OUTPUT_CSC_A                             = 0x4,
-+	COL_MAN_OUTPUT_CSC_B                             = 0x5,
-+	COL_MAN_OUTPUT_CSC_UNITY                         = 0x6,
-+} COL_MAN_OUTPUT_CSC_MODE;
-+typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
-+	DENORM_CLAMP_MODE_UNITY                          = 0x0,
-+	DENORM_CLAMP_MODE_8                              = 0x1,
-+	DENORM_CLAMP_MODE_10                             = 0x2,
-+	DENORM_CLAMP_MODE_12                             = 0x3,
-+} COL_MAN_DENORM_CLAMP_CONTROL;
-+typedef enum COL_MAN_GAMMA_CORR_CONTROL {
-+	GAMMA_CORR_MODE_BYPASS                           = 0x0,
-+	GAMMA_CORR_MODE_A                                = 0x1,
-+	GAMMA_CORR_MODE_B                                = 0x2,
-+} COL_MAN_GAMMA_CORR_CONTROL;
-+typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
-+	CM_GLOBAL_PASSTHROUGH_DISBALE                    = 0x0,
-+	CM_GLOBAL_PASSTHROUGH_ENABLE                     = 0x1,
-+} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
-+typedef enum UNP_GRPH_EN {
-+	UNP_GRPH_DISABLED                                = 0x0,
-+	UNP_GRPH_ENABLED                                 = 0x1,
-+} UNP_GRPH_EN;
-+typedef enum UNP_GRPH_DEPTH {
-+	UNP_GRPH_8BPP                                    = 0x0,
-+	UNP_GRPH_16BPP                                   = 0x1,
-+	UNP_GRPH_32BPP                                   = 0x2,
-+} UNP_GRPH_DEPTH;
-+typedef enum UNP_GRPH_NUM_BANKS {
-+	UNP_GRPH_ADDR_SURF_2_BANK                        = 0x0,
-+	UNP_GRPH_ADDR_SURF_4_BANK                        = 0x1,
-+	UNP_GRPH_ADDR_SURF_8_BANK                        = 0x2,
-+	UNP_GRPH_ADDR_SURF_16_BANK                       = 0x3,
-+} UNP_GRPH_NUM_BANKS;
-+typedef enum UNP_GRPH_BANK_WIDTH {
-+	UNP_GRPH_ADDR_SURF_BANK_WIDTH_1                  = 0x0,
-+	UNP_GRPH_ADDR_SURF_BANK_WIDTH_2                  = 0x1,
-+	UNP_GRPH_ADDR_SURF_BANK_WIDTH_4                  = 0x2,
-+	UNP_GRPH_ADDR_SURF_BANK_WIDTH_8                  = 0x3,
-+} UNP_GRPH_BANK_WIDTH;
-+typedef enum UNP_GRPH_BANK_HEIGHT {
-+	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1                 = 0x0,
-+	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2                 = 0x1,
-+	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4                 = 0x2,
-+	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8                 = 0x3,
-+} UNP_GRPH_BANK_HEIGHT;
-+typedef enum UNP_GRPH_TILE_SPLIT {
-+	UNP_ADDR_SURF_TILE_SPLIT_64B                     = 0x0,
-+	UNP_ADDR_SURF_TILE_SPLIT_128B                    = 0x1,
-+	UNP_ADDR_SURF_TILE_SPLIT_256B                    = 0x2,
-+	UNP_ADDR_SURF_TILE_SPLIT_512B                    = 0x3,
-+	UNP_ADDR_SURF_TILE_SPLIT_1KB                     = 0x4,
-+	UNP_ADDR_SURF_TILE_SPLIT_2KB                     = 0x5,
-+	UNP_ADDR_SURF_TILE_SPLIT_4KB                     = 0x6,
-+} UNP_GRPH_TILE_SPLIT;
-+typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
-+	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0             = 0x0,
-+	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1             = 0x1,
-+} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
-+typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
-+	UNP_GRPH_PRIVILEGED_ACCESS_DIS                   = 0x0,
-+	UNP_GRPH_PRIVILEGED_ACCESS_EN                    = 0x1,
-+} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
-+typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
-+	UNP_ADDR_SURF_MACRO_ASPECT_1                     = 0x0,
-+	UNP_ADDR_SURF_MACRO_ASPECT_2                     = 0x1,
-+	UNP_ADDR_SURF_MACRO_ASPECT_4                     = 0x2,
-+	UNP_ADDR_SURF_MACRO_ASPECT_8                     = 0x3,
-+} UNP_GRPH_MACRO_TILE_ASPECT;
-+typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
-+	UNP_GRPH_DYNAMIC_EXPANSION                       = 0x0,
-+	UNP_GRPH_ZERO_EXPANSION                          = 0x1,
-+} UNP_GRPH_COLOR_EXPANSION_MODE;
-+typedef enum UNP_VIDEO_FORMAT {
-+	UNP_VIDEO_FORMAT0                                = 0x0,
-+	UNP_VIDEO_FORMAT1                                = 0x1,
-+	UNP_VIDEO_FORMAT_YUV420_YCbCr                    = 0x2,
-+	UNP_VIDEO_FORMAT_YUV420_YCrCb                    = 0x3,
-+	UNP_VIDEO_FORMAT_YUV422_YCb                      = 0x4,
-+	UNP_VIDEO_FORMAT_YUV422_YCr                      = 0x5,
-+	UNP_VIDEO_FORMAT_YUV422_CbY                      = 0x6,
-+	UNP_VIDEO_FORMAT_YUV422_CrY                      = 0x7,
-+} UNP_VIDEO_FORMAT;
-+typedef enum UNP_GRPH_ENDIAN_SWAP {
-+	UNP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
-+	UNP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
-+	UNP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
-+	UNP_GRPH_ENDIAN_SWAP_8IN43                       = 0x3,
-+} UNP_GRPH_ENDIAN_SWAP;
-+typedef enum UNP_GRPH_RED_CROSSBAR {
-+	UNP_GRPH_RED_CROSSBAR_R_Cr                       = 0x0,
-+	UNP_GRPH_RED_CROSSBAR_G_Y                        = 0x1,
-+	UNP_GRPH_RED_CROSSBAR_B_Cb                       = 0x2,
-+	UNP_GRPH_RED_CROSSBAR_A                          = 0x3,
-+} UNP_GRPH_RED_CROSSBAR;
-+typedef enum UNP_GRPH_GREEN_CROSSBAR {
-+	UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y             = 0x0,
-+	UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C           = 0x1,
-+	UNP_UNP_GRPH_GREEN_CROSSBAR_A                    = 0x2,
-+	UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr                 = 0x3,
-+} UNP_GRPH_GREEN_CROSSBAR;
-+typedef enum UNP_GRPH_BLUE_CROSSBAR {
-+	UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C                = 0x0,
-+	UNP_GRPH_BLUE_CROSSBAR_A                         = 0x1,
-+	UNP_GRPH_BLUE_CROSSBAR_R_Cr                      = 0x2,
-+	UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y                  = 0x3,
-+} UNP_GRPH_BLUE_CROSSBAR;
-+typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
-+	UNP_GRPH_UPDATE_LOCK_0                           = 0x0,
-+	UNP_GRPH_UPDATE_LOCK_1                           = 0x1,
-+} UNP_GRPH_MODE_UPDATE_LOCKG;
-+typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
-+	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0            = 0x0,
-+	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1            = 0x1,
-+} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
-+typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
-+	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0          = 0x0,
-+	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1          = 0x1,
-+} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
-+typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
-+	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0       = 0x0,
-+	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1       = 0x1,
-+} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
-+typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
-+	UNP_GRPH_STEREOSYNC_FLIP_DISABLE                 = 0x0,
-+	UNP_GRPH_STEREOSYNC_FLIP_ENABLE                  = 0x1,
-+} UNP_GRPH_STEREOSYNC_FLIP_EN;
-+typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
-+	UNP_GRPH_STEREOSYNC_FLIP_MODE_0                  = 0x0,
-+	UNP_GRPH_STEREOSYNC_FLIP_MODE_1                  = 0x1,
-+	UNP_GRPH_STEREOSYNC_FLIP_MODE_2                  = 0x2,
-+	UNP_GRPH_STEREOSYNC_FLIP_MODE_3                  = 0x3,
-+} UNP_GRPH_STEREOSYNC_FLIP_MODE;
-+typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
-+	UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE            = 0x0,
-+	UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE             = 0x1,
-+} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
-+typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
-+	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0             = 0x0,
-+	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1             = 0x1,
-+	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2             = 0x2,
-+	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3             = 0x3,
-+} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
-+typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
-+	UNP_GRPH_STEREOSYNC_SELECT_EN                    = 0x0,
-+	UNP_GRPH_STEREOSYNC_SELECT_DIS                   = 0x1,
-+} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
-+typedef enum UNP_CRC_SOURCE_SEL {
-+	UNP_CRC_SOURCE_SEL_NP_TO_LBV                     = 0x0,
-+	UNP_CRC_SOURCE_SEL_LOWER32                       = 0x1,
-+	UNP_CRC_SOURCE_SEL_RESERVED                      = 0x2,
-+	UNP_CRC_SOURCE_SEL_LOWER16                       = 0x3,
-+	UNP_CRC_SOURCE_SEL_UNP_TO_LBV                    = 0x4,
-+} UNP_CRC_SOURCE_SEL;
-+typedef enum UNP_CRC_LINE_SEL {
-+	UNP_CRC_LINE_SEL_RESERVED                        = 0x0,
-+	UNP_CRC_LINE_SEL_EVEN_ONLY                       = 0x1,
-+	UNP_CRC_LINE_SEL_ODD_ONLY                        = 0x2,
-+	UNP_CRC_LINE_SEL_ODD_EVEN                        = 0x3,
-+} UNP_CRC_LINE_SEL;
-+typedef enum UNP_ROTATION_ANGLE {
-+	UNP_ROTATION_ANGLE_0                             = 0x0,
-+	UNP_ROTATION_ANGLE_90                            = 0x1,
-+	UNP_ROTATION_ANGLE_180                           = 0x2,
-+	UNP_ROTATION_ANGLE_270                           = 0x3,
-+	UNP_ROTATION_ANGLE_0m                            = 0x4,
-+	UNP_ROTATION_ANGLE_90m                           = 0x5,
-+	UNP_ROTATION_ANGLE_180m                          = 0x6,
-+	UNP_ROTATION_ANGLE_270m                          = 0x7,
-+} UNP_ROTATION_ANGLE;
-+typedef enum UNP_PIXEL_DROP {
-+	UNP_PIXEL_NO_DROP                                = 0x0,
-+	UNP_PIXEL_DROPPING                               = 0x1,
-+} UNP_PIXEL_DROP;
-+typedef enum UNP_BUFFER_MODE {
-+	UNP_BUFFER_MODE_LUMA                             = 0x0,
-+	UNP_BUFFER_MODE_LUMA_CHROMA                      = 0x1,
-+} UNP_BUFFER_MODE;
-+typedef enum WATERMARK_MASK_CONTROL {
-+	WM_MASK_CONTROL_SET_A                            = 0x0,
-+	WM_MASK_CONTROL_SET_B                            = 0x1,
-+	WM_MASK_CONTROL_SET_C                            = 0x2,
-+	WM_MASK_CONTROL_SET_D                            = 0x3,
-+	WM_MASK_CONTROL_RESERVED1                        = 0x4,
-+	WM_MASK_CONTROL_RESERVED2                        = 0x5,
-+	WM_MASK_CONTROL_RESERVED3                        = 0x6,
-+	WM_MASK_CONTROL_ACTIVE_SET                       = 0x7,
-+} WATERMARK_MASK_CONTROL;
-+typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
-+	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
-+	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
-+} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
-+typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
-+	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
-+} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
-+typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
-+	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
-+} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
-+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
-+	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE           = 0x0,
-+	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE            = 0x1,
-+} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
-+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
-+	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x0,
-+	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED   = 0x1,
-+} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
-+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
-+	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET    = 0x0,
-+	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET        = 0x1,
-+} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
-+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
-+	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
-+	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
-+} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
-+typedef enum AZ_GLOBAL_CAPABILITIES {
-+	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
-+	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
-+} AZ_GLOBAL_CAPABILITIES;
-+typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
-+	ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE           = 0x0,
-+	ACCEPT_UNSOLICITED_RESPONSE_ENABLE               = 0x1,
-+} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
-+typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
-+	FLUSH_CONTROL_FLUSH_NOT_STARTED                  = 0x0,
-+	FLUSH_CONTROL_FLUSH_STARTED                      = 0x1,
-+} GLOBAL_CONTROL_FLUSH_CONTROL;
-+typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
-+	CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET          = 0x0,
-+	CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET      = 0x1,
-+} GLOBAL_CONTROL_CONTROLLER_RESET;
-+typedef enum AZ_STATE_CHANGE_STATUS {
-+	AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT         = 0x0,
-+	AZ_STATE_CHANGE_STATUS_CODEC_PRESENT             = 0x1,
-+} AZ_STATE_CHANGE_STATUS;
-+typedef enum GLOBAL_STATUS_FLUSH_STATUS {
-+	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED       = 0x0,
-+	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED           = 0x1,
-+} GLOBAL_STATUS_FLUSH_STATUS;
-+typedef enum STREAM_0_SYNCHRONIZATION {
-+	STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
-+	STREAM_0_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
-+} STREAM_0_SYNCHRONIZATION;
-+typedef enum STREAM_1_SYNCHRONIZATION {
-+	STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
-+	STREAM_1_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
-+} STREAM_1_SYNCHRONIZATION;
-+typedef enum STREAM_2_SYNCHRONIZATION {
-+	STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
-+	STREAM_2_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
-+} STREAM_2_SYNCHRONIZATION;
-+typedef enum STREAM_3_SYNCHRONIZATION {
-+	STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
-+	STREAM_3_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
-+} STREAM_3_SYNCHRONIZATION;
-+typedef enum STREAM_4_SYNCHRONIZATION {
-+	STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
-+	STREAM_4_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
-+} STREAM_4_SYNCHRONIZATION;
-+typedef enum STREAM_5_SYNCHRONIZATION {
-+	STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
-+	STREAM_5_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
-+} STREAM_5_SYNCHRONIZATION;
-+typedef enum STREAM_6_SYNCHRONIZATION {
-+	STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
-+} STREAM_6_SYNCHRONIZATION;
-+typedef enum STREAM_7_SYNCHRONIZATION {
-+	STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
-+} STREAM_7_SYNCHRONIZATION;
-+typedef enum STREAM_8_SYNCHRONIZATION {
-+	STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
-+} STREAM_8_SYNCHRONIZATION;
-+typedef enum STREAM_9_SYNCHRONIZATION {
-+	STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
-+} STREAM_9_SYNCHRONIZATION;
-+typedef enum STREAM_10_SYNCHRONIZATION {
-+	STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-+} STREAM_10_SYNCHRONIZATION;
-+typedef enum STREAM_11_SYNCHRONIZATION {
-+	STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-+} STREAM_11_SYNCHRONIZATION;
-+typedef enum STREAM_12_SYNCHRONIZATION {
-+	STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-+} STREAM_12_SYNCHRONIZATION;
-+typedef enum STREAM_13_SYNCHRONIZATION {
-+	STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-+} STREAM_13_SYNCHRONIZATION;
-+typedef enum STREAM_14_SYNCHRONIZATION {
-+	STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-+} STREAM_14_SYNCHRONIZATION;
-+typedef enum STREAM_15_SYNCHRONIZATION {
-+	STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
-+	STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-+} STREAM_15_SYNCHRONIZATION;
-+typedef enum CORB_READ_POINTER_RESET {
-+	CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET    = 0x0,
-+	CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET        = 0x1,
-+} CORB_READ_POINTER_RESET;
-+typedef enum AZ_CORB_SIZE {
-+	AZ_CORB_SIZE_2ENTRIES_RESERVED                   = 0x0,
-+	AZ_CORB_SIZE_16ENTRIES_RESERVED                  = 0x1,
-+	AZ_CORB_SIZE_256ENTRIES                          = 0x2,
-+	AZ_CORB_SIZE_RESERVED                            = 0x3,
-+} AZ_CORB_SIZE;
-+typedef enum AZ_RIRB_WRITE_POINTER_RESET {
-+	AZ_RIRB_WRITE_POINTER_NOT_RESET                  = 0x0,
-+	AZ_RIRB_WRITE_POINTER_DO_RESET                   = 0x1,
-+} AZ_RIRB_WRITE_POINTER_RESET;
-+typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
-+	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
-+	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
-+} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
-+typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
-+	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
-+	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
-+} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
-+typedef enum AZ_RIRB_SIZE {
-+	AZ_RIRB_SIZE_2ENTRIES_RESERVED                   = 0x0,
-+	AZ_RIRB_SIZE_16ENTRIES_RESERVED                  = 0x1,
-+	AZ_RIRB_SIZE_256ENTRIES                          = 0x2,
-+	AZ_RIRB_SIZE_UNDEFINED                           = 0x3,
-+} AZ_RIRB_SIZE;
-+typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
-+	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
-+	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
-+} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
-+typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
-+	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
-+	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
-+} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
-+typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
-+	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
-+	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
-+} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
-+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
-+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
-+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
-+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
-+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
-+	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
-+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
-+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
-+	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
-+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
-+	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN   = 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
-+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
-+	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
-+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
-+typedef enum AZ_LATENCY_COUNTER_CONTROL {
-+	AZ_LATENCY_COUNTER_NO_RESET                      = 0x0,
-+	AZ_LATENCY_COUNTER_RESET_DONE                    = 0x1,
-+} AZ_LATENCY_COUNTER_CONTROL;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
-+	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
-+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
-+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
-+	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
-+	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
-+} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
-+typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
-+	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
-+	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
-+} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
-+	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
-+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
-+typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
-+	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
-+	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
-+} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
-+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
-+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
-+	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
-+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
-+typedef enum BLND_CONTROL_BLND_MODE {
-+	BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY         = 0x0,
-+	BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY           = 0x1,
-+	BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE       = 0x2,
-+	BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE         = 0x3,
-+} BLND_CONTROL_BLND_MODE;
-+typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
-+	BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
-+	BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
-+	BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
-+	BLND_CONTROL_BLND_STEREO_TYPE_UNUSED             = 0x3,
-+} BLND_CONTROL_BLND_STEREO_TYPE;
-+typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
-+	BLND_CONTROL_BLND_STEREO_POLARITY_LOW            = 0x0,
-+	BLND_CONTROL_BLND_STEREO_POLARITY_HIGH           = 0x1,
-+} BLND_CONTROL_BLND_STEREO_POLARITY;
-+typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
-+	BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE           = 0x0,
-+	BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE            = 0x1,
-+} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
-+typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
-+	BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
-+	BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
-+	BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY   = 0x2,
-+	BLND_CONTROL_BLND_ALPHA_MODE_UNUSED              = 0x3,
-+} BLND_CONTROL_BLND_ALPHA_MODE;
-+typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
-+	BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE      = 0x0,
-+	BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE       = 0x1,
-+} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
-+typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
-+	BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE          = 0x0,
-+	BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE           = 0x1,
-+} BLND_CONTROL_BLND_MULTIPLIED_MODE;
-+typedef enum BLND_SM_CONTROL2_SM_MODE {
-+	BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE            = 0x0,
-+	BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING         = 0x2,
-+	BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING      = 0x4,
-+	BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
-+} BLND_SM_CONTROL2_SM_MODE;
-+typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
-+	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE        = 0x0,
-+	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE         = 0x1,
-+} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
-+typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
-+	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE        = 0x0,
-+	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE         = 0x1,
-+} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
-+typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
-+} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
-+typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE  = 0x0,
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED  = 0x1,
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
-+	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
-+} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
-+typedef enum BLND_CONTROL2_PTI_ENABLE {
-+	BLND_CONTROL2_PTI_ENABLE_FALSE                   = 0x0,
-+	BLND_CONTROL2_PTI_ENABLE_TRUE                    = 0x1,
-+} BLND_CONTROL2_PTI_ENABLE;
-+typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
-+	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE      = 0x0,
-+	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE       = 0x1,
-+} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
-+typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
-+	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE      = 0x0,
-+	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE       = 0x1,
-+} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
-+typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
-+	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
-+	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
-+} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
-+typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
-+	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
-+	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
-+} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
-+	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
-+	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
-+	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
-+	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
-+	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE  = 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE   = 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
-+	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE  = 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
-+typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
-+	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
-+	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE  = 0x1,
-+} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
-+typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
-+	BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW               = 0x0,
-+	BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH              = 0x1,
-+} BLND_DEBUG_BLND_CNV_MUX_SELECT;
-+typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
-+	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
-+	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
-+} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
-+typedef enum SurfaceEndian {
-+	ENDIAN_NONE                                      = 0x0,
-+	ENDIAN_8IN16                                     = 0x1,
-+	ENDIAN_8IN32                                     = 0x2,
-+	ENDIAN_8IN64                                     = 0x3,
-+} SurfaceEndian;
-+typedef enum ArrayMode {
-+	ARRAY_LINEAR_GENERAL                             = 0x0,
-+	ARRAY_LINEAR_ALIGNED                             = 0x1,
-+	ARRAY_1D_TILED_THIN1                             = 0x2,
-+	ARRAY_1D_TILED_THICK                             = 0x3,
-+	ARRAY_2D_TILED_THIN1                             = 0x4,
-+	ARRAY_PRT_TILED_THIN1                            = 0x5,
-+	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
-+	ARRAY_2D_TILED_THICK                             = 0x7,
-+	ARRAY_2D_TILED_XTHICK                            = 0x8,
-+	ARRAY_PRT_TILED_THICK                            = 0x9,
-+	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
-+	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
-+	ARRAY_3D_TILED_THIN1                             = 0xc,
-+	ARRAY_3D_TILED_THICK                             = 0xd,
-+	ARRAY_3D_TILED_XTHICK                            = 0xe,
-+	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
-+} ArrayMode;
-+typedef enum PipeTiling {
-+	CONFIG_1_PIPE                                    = 0x0,
-+	CONFIG_2_PIPE                                    = 0x1,
-+	CONFIG_4_PIPE                                    = 0x2,
-+	CONFIG_8_PIPE                                    = 0x3,
-+} PipeTiling;
-+typedef enum BankTiling {
-+	CONFIG_4_BANK                                    = 0x0,
-+	CONFIG_8_BANK                                    = 0x1,
-+} BankTiling;
-+typedef enum GroupInterleave {
-+	CONFIG_256B_GROUP                                = 0x0,
-+	CONFIG_512B_GROUP                                = 0x1,
-+} GroupInterleave;
-+typedef enum RowTiling {
-+	CONFIG_1KB_ROW                                   = 0x0,
-+	CONFIG_2KB_ROW                                   = 0x1,
-+	CONFIG_4KB_ROW                                   = 0x2,
-+	CONFIG_8KB_ROW                                   = 0x3,
-+	CONFIG_1KB_ROW_OPT                               = 0x4,
-+	CONFIG_2KB_ROW_OPT                               = 0x5,
-+	CONFIG_4KB_ROW_OPT                               = 0x6,
-+	CONFIG_8KB_ROW_OPT                               = 0x7,
-+} RowTiling;
-+typedef enum BankSwapBytes {
-+	CONFIG_128B_SWAPS                                = 0x0,
-+	CONFIG_256B_SWAPS                                = 0x1,
-+	CONFIG_512B_SWAPS                                = 0x2,
-+	CONFIG_1KB_SWAPS                                 = 0x3,
-+} BankSwapBytes;
-+typedef enum SampleSplitBytes {
-+	CONFIG_1KB_SPLIT                                 = 0x0,
-+	CONFIG_2KB_SPLIT                                 = 0x1,
-+	CONFIG_4KB_SPLIT                                 = 0x2,
-+	CONFIG_8KB_SPLIT                                 = 0x3,
-+} SampleSplitBytes;
-+typedef enum NumPipes {
-+	ADDR_CONFIG_1_PIPE                               = 0x0,
-+	ADDR_CONFIG_2_PIPE                               = 0x1,
-+	ADDR_CONFIG_4_PIPE                               = 0x2,
-+	ADDR_CONFIG_8_PIPE                               = 0x3,
-+} NumPipes;
-+typedef enum PipeInterleaveSize {
-+	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
-+	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
-+} PipeInterleaveSize;
-+typedef enum BankInterleaveSize {
-+	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
-+	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
-+	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
-+	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
-+} BankInterleaveSize;
-+typedef enum NumShaderEngines {
-+	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
-+	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
-+} NumShaderEngines;
-+typedef enum ShaderEngineTileSize {
-+	ADDR_CONFIG_SE_TILE_16                           = 0x0,
-+	ADDR_CONFIG_SE_TILE_32                           = 0x1,
-+} ShaderEngineTileSize;
-+typedef enum NumGPUs {
-+	ADDR_CONFIG_1_GPU                                = 0x0,
-+	ADDR_CONFIG_2_GPU                                = 0x1,
-+	ADDR_CONFIG_4_GPU                                = 0x2,
-+} NumGPUs;
-+typedef enum MultiGPUTileSize {
-+	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
-+	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
-+	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
-+	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
-+} MultiGPUTileSize;
-+typedef enum RowSize {
-+	ADDR_CONFIG_1KB_ROW                              = 0x0,
-+	ADDR_CONFIG_2KB_ROW                              = 0x1,
-+	ADDR_CONFIG_4KB_ROW                              = 0x2,
-+} RowSize;
-+typedef enum NumLowerPipes {
-+	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
-+	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
-+} NumLowerPipes;
-+typedef enum DebugBlockId {
-+	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
-+	DBG_CLIENT_BLKID_dbg                             = 0x1,
-+	DBG_CLIENT_BLKID_scf2                            = 0x2,
-+	DBG_CLIENT_BLKID_mcd5                            = 0x3,
-+	DBG_CLIENT_BLKID_vmc                             = 0x4,
-+	DBG_CLIENT_BLKID_sx30                            = 0x5,
-+	DBG_CLIENT_BLKID_mcd2                            = 0x6,
-+	DBG_CLIENT_BLKID_bci1                            = 0x7,
-+	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
-+	DBG_CLIENT_BLKID_mcc0                            = 0x9,
-+	DBG_CLIENT_BLKID_uvdf_2                          = 0xa,
-+	DBG_CLIENT_BLKID_uvdf_3                          = 0xb,
-+	DBG_CLIENT_BLKID_uvdt_0                          = 0xc,
-+	DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
-+	DBG_CLIENT_BLKID_bci0                            = 0xe,
-+	DBG_CLIENT_BLKID_vceb0_1                         = 0xf,
-+	DBG_CLIENT_BLKID_cb100                           = 0x10,
-+	DBG_CLIENT_BLKID_cb001                           = 0x11,
-+	DBG_CLIENT_BLKID_mcd4                            = 0x12,
-+	DBG_CLIENT_BLKID_tmonw00                         = 0x13,
-+	DBG_CLIENT_BLKID_cb101                           = 0x14,
-+	DBG_CLIENT_BLKID_sx10                            = 0x15,
-+	DBG_CLIENT_BLKID_cb301                           = 0x16,
-+	DBG_CLIENT_BLKID_tmonw01                         = 0x17,
-+	DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
-+	DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
-+	DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
-+	DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
-+	DBG_CLIENT_BLKID_scf1                            = 0x1c,
-+	DBG_CLIENT_BLKID_sx20                            = 0x1d,
-+	DBG_CLIENT_BLKID_spim1                           = 0x1e,
-+	DBG_CLIENT_BLKID_pa10                            = 0x1f,
-+	DBG_CLIENT_BLKID_pa00                            = 0x20,
-+	DBG_CLIENT_BLKID_gmcon                           = 0x21,
-+	DBG_CLIENT_BLKID_mcb                             = 0x22,
-+	DBG_CLIENT_BLKID_vgt0                            = 0x23,
-+	DBG_CLIENT_BLKID_pc0                             = 0x24,
-+	DBG_CLIENT_BLKID_bci2                            = 0x25,
-+	DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
-+	DBG_CLIENT_BLKID_spim3                           = 0x27,
-+	DBG_CLIENT_BLKID_cpc_0                           = 0x28,
-+	DBG_CLIENT_BLKID_cpc_1                           = 0x29,
-+	DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
-+	DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
-+	DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
-+	DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
-+	DBG_CLIENT_BLKID_cb000                           = 0x2e,
-+	DBG_CLIENT_BLKID_spim0                           = 0x2f,
-+	DBG_CLIENT_BLKID_mcc2                            = 0x30,
-+	DBG_CLIENT_BLKID_ds0                             = 0x31,
-+	DBG_CLIENT_BLKID_srbm                            = 0x32,
-+	DBG_CLIENT_BLKID_ih                              = 0x33,
-+	DBG_CLIENT_BLKID_sem                             = 0x34,
-+	DBG_CLIENT_BLKID_sdma_0                          = 0x35,
-+	DBG_CLIENT_BLKID_sdma_1                          = 0x36,
-+	DBG_CLIENT_BLKID_hdp                             = 0x37,
-+	DBG_CLIENT_BLKID_cb200                           = 0x38,
-+	DBG_CLIENT_BLKID_scf3                            = 0x39,
-+	DBG_CLIENT_BLKID_vceb1_0                         = 0x3a,
-+	DBG_CLIENT_BLKID_vcea1_0                         = 0x3b,
-+	DBG_CLIENT_BLKID_vcea1_1                         = 0x3c,
-+	DBG_CLIENT_BLKID_vcea1_2                         = 0x3d,
-+	DBG_CLIENT_BLKID_vcea1_3                         = 0x3e,
-+	DBG_CLIENT_BLKID_bci3                            = 0x3f,
-+	DBG_CLIENT_BLKID_mcd0                            = 0x40,
-+	DBG_CLIENT_BLKID_pa11                            = 0x41,
-+	DBG_CLIENT_BLKID_pa01                            = 0x42,
-+	DBG_CLIENT_BLKID_cb201                           = 0x43,
-+	DBG_CLIENT_BLKID_spim2                           = 0x44,
-+	DBG_CLIENT_BLKID_vgt2                            = 0x45,
-+	DBG_CLIENT_BLKID_pc2                             = 0x46,
-+	DBG_CLIENT_BLKID_smu_0                           = 0x47,
-+	DBG_CLIENT_BLKID_smu_1                           = 0x48,
-+	DBG_CLIENT_BLKID_smu_2                           = 0x49,
-+	DBG_CLIENT_BLKID_cb1                             = 0x4a,
-+	DBG_CLIENT_BLKID_ia0                             = 0x4b,
-+	DBG_CLIENT_BLKID_wd                              = 0x4c,
-+	DBG_CLIENT_BLKID_ia1                             = 0x4d,
-+	DBG_CLIENT_BLKID_vcec1_0                         = 0x4e,
-+	DBG_CLIENT_BLKID_scf0                            = 0x4f,
-+	DBG_CLIENT_BLKID_vgt1                            = 0x50,
-+	DBG_CLIENT_BLKID_pc1                             = 0x51,
-+	DBG_CLIENT_BLKID_cb0                             = 0x52,
-+	DBG_CLIENT_BLKID_gdc_one_0                       = 0x53,
-+	DBG_CLIENT_BLKID_gdc_one_1                       = 0x54,
-+	DBG_CLIENT_BLKID_gdc_one_2                       = 0x55,
-+	DBG_CLIENT_BLKID_gdc_one_3                       = 0x56,
-+	DBG_CLIENT_BLKID_gdc_one_4                       = 0x57,
-+	DBG_CLIENT_BLKID_gdc_one_5                       = 0x58,
-+	DBG_CLIENT_BLKID_gdc_one_6                       = 0x59,
-+	DBG_CLIENT_BLKID_gdc_one_7                       = 0x5a,
-+	DBG_CLIENT_BLKID_gdc_one_8                       = 0x5b,
-+	DBG_CLIENT_BLKID_gdc_one_9                       = 0x5c,
-+	DBG_CLIENT_BLKID_gdc_one_10                      = 0x5d,
-+	DBG_CLIENT_BLKID_gdc_one_11                      = 0x5e,
-+	DBG_CLIENT_BLKID_gdc_one_12                      = 0x5f,
-+	DBG_CLIENT_BLKID_gdc_one_13                      = 0x60,
-+	DBG_CLIENT_BLKID_gdc_one_14                      = 0x61,
-+	DBG_CLIENT_BLKID_gdc_one_15                      = 0x62,
-+	DBG_CLIENT_BLKID_gdc_one_16                      = 0x63,
-+	DBG_CLIENT_BLKID_gdc_one_17                      = 0x64,
-+	DBG_CLIENT_BLKID_gdc_one_18                      = 0x65,
-+	DBG_CLIENT_BLKID_gdc_one_19                      = 0x66,
-+	DBG_CLIENT_BLKID_gdc_one_20                      = 0x67,
-+	DBG_CLIENT_BLKID_gdc_one_21                      = 0x68,
-+	DBG_CLIENT_BLKID_gdc_one_22                      = 0x69,
-+	DBG_CLIENT_BLKID_gdc_one_23                      = 0x6a,
-+	DBG_CLIENT_BLKID_gdc_one_24                      = 0x6b,
-+	DBG_CLIENT_BLKID_gdc_one_25                      = 0x6c,
-+	DBG_CLIENT_BLKID_gdc_one_26                      = 0x6d,
-+	DBG_CLIENT_BLKID_gdc_one_27                      = 0x6e,
-+	DBG_CLIENT_BLKID_gdc_one_28                      = 0x6f,
-+	DBG_CLIENT_BLKID_gdc_one_29                      = 0x70,
-+	DBG_CLIENT_BLKID_gdc_one_30                      = 0x71,
-+	DBG_CLIENT_BLKID_gdc_one_31                      = 0x72,
-+	DBG_CLIENT_BLKID_gdc_one_32                      = 0x73,
-+	DBG_CLIENT_BLKID_gdc_one_33                      = 0x74,
-+	DBG_CLIENT_BLKID_gdc_one_34                      = 0x75,
-+	DBG_CLIENT_BLKID_gdc_one_35                      = 0x76,
-+	DBG_CLIENT_BLKID_vceb0_0                         = 0x77,
-+	DBG_CLIENT_BLKID_vgt3                            = 0x78,
-+	DBG_CLIENT_BLKID_pc3                             = 0x79,
-+	DBG_CLIENT_BLKID_mcd3                            = 0x7a,
-+	DBG_CLIENT_BLKID_uvdu_0                          = 0x7b,
-+	DBG_CLIENT_BLKID_uvdu_1                          = 0x7c,
-+	DBG_CLIENT_BLKID_uvdu_2                          = 0x7d,
-+	DBG_CLIENT_BLKID_uvdu_3                          = 0x7e,
-+	DBG_CLIENT_BLKID_uvdu_4                          = 0x7f,
-+	DBG_CLIENT_BLKID_uvdu_5                          = 0x80,
-+	DBG_CLIENT_BLKID_uvdu_6                          = 0x81,
-+	DBG_CLIENT_BLKID_cb300                           = 0x82,
-+	DBG_CLIENT_BLKID_mcd1                            = 0x83,
-+	DBG_CLIENT_BLKID_sx00                            = 0x84,
-+	DBG_CLIENT_BLKID_uvdf_0                          = 0x85,
-+	DBG_CLIENT_BLKID_uvdf_1                          = 0x86,
-+	DBG_CLIENT_BLKID_mcc3                            = 0x87,
-+	DBG_CLIENT_BLKID_cpg_0                           = 0x88,
-+	DBG_CLIENT_BLKID_cpg_1                           = 0x89,
-+	DBG_CLIENT_BLKID_gck                             = 0x8a,
-+	DBG_CLIENT_BLKID_mcc1                            = 0x8b,
-+	DBG_CLIENT_BLKID_cpf_0                           = 0x8c,
-+	DBG_CLIENT_BLKID_cpf_1                           = 0x8d,
-+	DBG_CLIENT_BLKID_rlc                             = 0x8e,
-+	DBG_CLIENT_BLKID_grbm                            = 0x8f,
-+	DBG_CLIENT_BLKID_sammsp                          = 0x90,
-+	DBG_CLIENT_BLKID_dci_pg                          = 0x91,
-+	DBG_CLIENT_BLKID_dci_0                           = 0x92,
-+	DBG_CLIENT_BLKID_dccg0_0                         = 0x93,
-+	DBG_CLIENT_BLKID_dccg0_1                         = 0x94,
-+	DBG_CLIENT_BLKID_dccg0_2                         = 0x95,
-+	DBG_CLIENT_BLKID_dccg0_3                         = 0x96,
-+	DBG_CLIENT_BLKID_dccg0_4                         = 0x97,
-+	DBG_CLIENT_BLKID_dccg0_5                         = 0x98,
-+	DBG_CLIENT_BLKID_dccg0_6                         = 0x99,
-+	DBG_CLIENT_BLKID_dccg0_7                         = 0x9a,
-+	DBG_CLIENT_BLKID_dccg0_8                         = 0x9b,
-+	DBG_CLIENT_BLKID_dcfe01_0                        = 0x9c,
-+	DBG_CLIENT_BLKID_dcfe02_0                        = 0x9d,
-+	DBG_CLIENT_BLKID_dcfe03_0                        = 0x9e,
-+	DBG_CLIENT_BLKID_dcfe04_0                        = 0x9f,
-+	DBG_CLIENT_BLKID_dcfe05_0                        = 0xa0,
-+	DBG_CLIENT_BLKID_dcfe06_0                        = 0xa1,
-+	DBG_CLIENT_BLKID_uvde_0                          = 0xa2,
-+	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0xa3,
-+} DebugBlockId;
-+typedef enum DebugBlockId_OLD {
-+	DBG_BLOCK_ID_RESERVED                            = 0x0,
-+	DBG_BLOCK_ID_DBG                                 = 0x1,
-+	DBG_BLOCK_ID_VMC                                 = 0x2,
-+	DBG_BLOCK_ID_PDMA                                = 0x3,
-+	DBG_BLOCK_ID_CG                                  = 0x4,
-+	DBG_BLOCK_ID_SRBM                                = 0x5,
-+	DBG_BLOCK_ID_GRBM                                = 0x6,
-+	DBG_BLOCK_ID_RLC                                 = 0x7,
-+	DBG_BLOCK_ID_CSC                                 = 0x8,
-+	DBG_BLOCK_ID_SEM                                 = 0x9,
-+	DBG_BLOCK_ID_IH                                  = 0xa,
-+	DBG_BLOCK_ID_SC                                  = 0xb,
-+	DBG_BLOCK_ID_SQ                                  = 0xc,
-+	DBG_BLOCK_ID_AVP                                 = 0xd,
-+	DBG_BLOCK_ID_GMCON                               = 0xe,
-+	DBG_BLOCK_ID_SMU                                 = 0xf,
-+	DBG_BLOCK_ID_DMA0                                = 0x10,
-+	DBG_BLOCK_ID_DMA1                                = 0x11,
-+	DBG_BLOCK_ID_SPIM                                = 0x12,
-+	DBG_BLOCK_ID_GDS                                 = 0x13,
-+	DBG_BLOCK_ID_SPIS                                = 0x14,
-+	DBG_BLOCK_ID_UNUSED0                             = 0x15,
-+	DBG_BLOCK_ID_PA0                                 = 0x16,
-+	DBG_BLOCK_ID_PA1                                 = 0x17,
-+	DBG_BLOCK_ID_CP0                                 = 0x18,
-+	DBG_BLOCK_ID_CP1                                 = 0x19,
-+	DBG_BLOCK_ID_CP2                                 = 0x1a,
-+	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
-+	DBG_BLOCK_ID_UVDU                                = 0x1c,
-+	DBG_BLOCK_ID_UVDM                                = 0x1d,
-+	DBG_BLOCK_ID_VCE                                 = 0x1e,
-+	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
-+	DBG_BLOCK_ID_VGT0                                = 0x20,
-+	DBG_BLOCK_ID_VGT1                                = 0x21,
-+	DBG_BLOCK_ID_IA                                  = 0x22,
-+	DBG_BLOCK_ID_UNUSED3                             = 0x23,
-+	DBG_BLOCK_ID_SCT0                                = 0x24,
-+	DBG_BLOCK_ID_SCT1                                = 0x25,
-+	DBG_BLOCK_ID_SPM0                                = 0x26,
-+	DBG_BLOCK_ID_SPM1                                = 0x27,
-+	DBG_BLOCK_ID_TCAA                                = 0x28,
-+	DBG_BLOCK_ID_TCAB                                = 0x29,
-+	DBG_BLOCK_ID_TCCA                                = 0x2a,
-+	DBG_BLOCK_ID_TCCB                                = 0x2b,
-+	DBG_BLOCK_ID_MCC0                                = 0x2c,
-+	DBG_BLOCK_ID_MCC1                                = 0x2d,
-+	DBG_BLOCK_ID_MCC2                                = 0x2e,
-+	DBG_BLOCK_ID_MCC3                                = 0x2f,
-+	DBG_BLOCK_ID_SX0                                 = 0x30,
-+	DBG_BLOCK_ID_SX1                                 = 0x31,
-+	DBG_BLOCK_ID_SX2                                 = 0x32,
-+	DBG_BLOCK_ID_SX3                                 = 0x33,
-+	DBG_BLOCK_ID_UNUSED4                             = 0x34,
-+	DBG_BLOCK_ID_UNUSED5                             = 0x35,
-+	DBG_BLOCK_ID_UNUSED6                             = 0x36,
-+	DBG_BLOCK_ID_UNUSED7                             = 0x37,
-+	DBG_BLOCK_ID_PC0                                 = 0x38,
-+	DBG_BLOCK_ID_PC1                                 = 0x39,
-+	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
-+	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
-+	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
-+	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
-+	DBG_BLOCK_ID_MCB                                 = 0x3e,
-+	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
-+	DBG_BLOCK_ID_SCB0                                = 0x40,
-+	DBG_BLOCK_ID_SCB1                                = 0x41,
-+	DBG_BLOCK_ID_UNUSED13                            = 0x42,
-+	DBG_BLOCK_ID_UNUSED14                            = 0x43,
-+	DBG_BLOCK_ID_SCF0                                = 0x44,
-+	DBG_BLOCK_ID_SCF1                                = 0x45,
-+	DBG_BLOCK_ID_UNUSED15                            = 0x46,
-+	DBG_BLOCK_ID_UNUSED16                            = 0x47,
-+	DBG_BLOCK_ID_BCI0                                = 0x48,
-+	DBG_BLOCK_ID_BCI1                                = 0x49,
-+	DBG_BLOCK_ID_BCI2                                = 0x4a,
-+	DBG_BLOCK_ID_BCI3                                = 0x4b,
-+	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
-+	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
-+	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
-+	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
-+	DBG_BLOCK_ID_CB00                                = 0x50,
-+	DBG_BLOCK_ID_CB01                                = 0x51,
-+	DBG_BLOCK_ID_CB02                                = 0x52,
-+	DBG_BLOCK_ID_CB03                                = 0x53,
-+	DBG_BLOCK_ID_CB04                                = 0x54,
-+	DBG_BLOCK_ID_UNUSED21                            = 0x55,
-+	DBG_BLOCK_ID_UNUSED22                            = 0x56,
-+	DBG_BLOCK_ID_UNUSED23                            = 0x57,
-+	DBG_BLOCK_ID_CB10                                = 0x58,
-+	DBG_BLOCK_ID_CB11                                = 0x59,
-+	DBG_BLOCK_ID_CB12                                = 0x5a,
-+	DBG_BLOCK_ID_CB13                                = 0x5b,
-+	DBG_BLOCK_ID_CB14                                = 0x5c,
-+	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
-+	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
-+	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
-+	DBG_BLOCK_ID_TCP0                                = 0x60,
-+	DBG_BLOCK_ID_TCP1                                = 0x61,
-+	DBG_BLOCK_ID_TCP2                                = 0x62,
-+	DBG_BLOCK_ID_TCP3                                = 0x63,
-+	DBG_BLOCK_ID_TCP4                                = 0x64,
-+	DBG_BLOCK_ID_TCP5                                = 0x65,
-+	DBG_BLOCK_ID_TCP6                                = 0x66,
-+	DBG_BLOCK_ID_TCP7                                = 0x67,
-+	DBG_BLOCK_ID_TCP8                                = 0x68,
-+	DBG_BLOCK_ID_TCP9                                = 0x69,
-+	DBG_BLOCK_ID_TCP10                               = 0x6a,
-+	DBG_BLOCK_ID_TCP11                               = 0x6b,
-+	DBG_BLOCK_ID_TCP12                               = 0x6c,
-+	DBG_BLOCK_ID_TCP13                               = 0x6d,
-+	DBG_BLOCK_ID_TCP14                               = 0x6e,
-+	DBG_BLOCK_ID_TCP15                               = 0x6f,
-+	DBG_BLOCK_ID_TCP16                               = 0x70,
-+	DBG_BLOCK_ID_TCP17                               = 0x71,
-+	DBG_BLOCK_ID_TCP18                               = 0x72,
-+	DBG_BLOCK_ID_TCP19                               = 0x73,
-+	DBG_BLOCK_ID_TCP20                               = 0x74,
-+	DBG_BLOCK_ID_TCP21                               = 0x75,
-+	DBG_BLOCK_ID_TCP22                               = 0x76,
-+	DBG_BLOCK_ID_TCP23                               = 0x77,
-+	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
-+	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
-+	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
-+	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
-+	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
-+	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
-+	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
-+	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
-+	DBG_BLOCK_ID_DB00                                = 0x80,
-+	DBG_BLOCK_ID_DB01                                = 0x81,
-+	DBG_BLOCK_ID_DB02                                = 0x82,
-+	DBG_BLOCK_ID_DB03                                = 0x83,
-+	DBG_BLOCK_ID_DB04                                = 0x84,
-+	DBG_BLOCK_ID_UNUSED27                            = 0x85,
-+	DBG_BLOCK_ID_UNUSED28                            = 0x86,
-+	DBG_BLOCK_ID_UNUSED29                            = 0x87,
-+	DBG_BLOCK_ID_DB10                                = 0x88,
-+	DBG_BLOCK_ID_DB11                                = 0x89,
-+	DBG_BLOCK_ID_DB12                                = 0x8a,
-+	DBG_BLOCK_ID_DB13                                = 0x8b,
-+	DBG_BLOCK_ID_DB14                                = 0x8c,
-+	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
-+	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
-+	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
-+	DBG_BLOCK_ID_TCC0                                = 0x90,
-+	DBG_BLOCK_ID_TCC1                                = 0x91,
-+	DBG_BLOCK_ID_TCC2                                = 0x92,
-+	DBG_BLOCK_ID_TCC3                                = 0x93,
-+	DBG_BLOCK_ID_TCC4                                = 0x94,
-+	DBG_BLOCK_ID_TCC5                                = 0x95,
-+	DBG_BLOCK_ID_TCC6                                = 0x96,
-+	DBG_BLOCK_ID_TCC7                                = 0x97,
-+	DBG_BLOCK_ID_SPS00                               = 0x98,
-+	DBG_BLOCK_ID_SPS01                               = 0x99,
-+	DBG_BLOCK_ID_SPS02                               = 0x9a,
-+	DBG_BLOCK_ID_SPS10                               = 0x9b,
-+	DBG_BLOCK_ID_SPS11                               = 0x9c,
-+	DBG_BLOCK_ID_SPS12                               = 0x9d,
-+	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
-+	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
-+	DBG_BLOCK_ID_TA00                                = 0xa0,
-+	DBG_BLOCK_ID_TA01                                = 0xa1,
-+	DBG_BLOCK_ID_TA02                                = 0xa2,
-+	DBG_BLOCK_ID_TA03                                = 0xa3,
-+	DBG_BLOCK_ID_TA04                                = 0xa4,
-+	DBG_BLOCK_ID_TA05                                = 0xa5,
-+	DBG_BLOCK_ID_TA06                                = 0xa6,
-+	DBG_BLOCK_ID_TA07                                = 0xa7,
-+	DBG_BLOCK_ID_TA08                                = 0xa8,
-+	DBG_BLOCK_ID_TA09                                = 0xa9,
-+	DBG_BLOCK_ID_TA0A                                = 0xaa,
-+	DBG_BLOCK_ID_TA0B                                = 0xab,
-+	DBG_BLOCK_ID_UNUSED35                            = 0xac,
-+	DBG_BLOCK_ID_UNUSED36                            = 0xad,
-+	DBG_BLOCK_ID_UNUSED37                            = 0xae,
-+	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
-+	DBG_BLOCK_ID_TA10                                = 0xb0,
-+	DBG_BLOCK_ID_TA11                                = 0xb1,
-+	DBG_BLOCK_ID_TA12                                = 0xb2,
-+	DBG_BLOCK_ID_TA13                                = 0xb3,
-+	DBG_BLOCK_ID_TA14                                = 0xb4,
-+	DBG_BLOCK_ID_TA15                                = 0xb5,
-+	DBG_BLOCK_ID_TA16                                = 0xb6,
-+	DBG_BLOCK_ID_TA17                                = 0xb7,
-+	DBG_BLOCK_ID_TA18                                = 0xb8,
-+	DBG_BLOCK_ID_TA19                                = 0xb9,
-+	DBG_BLOCK_ID_TA1A                                = 0xba,
-+	DBG_BLOCK_ID_TA1B                                = 0xbb,
-+	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
-+	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
-+	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
-+	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
-+	DBG_BLOCK_ID_TD00                                = 0xc0,
-+	DBG_BLOCK_ID_TD01                                = 0xc1,
-+	DBG_BLOCK_ID_TD02                                = 0xc2,
-+	DBG_BLOCK_ID_TD03                                = 0xc3,
-+	DBG_BLOCK_ID_TD04                                = 0xc4,
-+	DBG_BLOCK_ID_TD05                                = 0xc5,
-+	DBG_BLOCK_ID_TD06                                = 0xc6,
-+	DBG_BLOCK_ID_TD07                                = 0xc7,
-+	DBG_BLOCK_ID_TD08                                = 0xc8,
-+	DBG_BLOCK_ID_TD09                                = 0xc9,
-+	DBG_BLOCK_ID_TD0A                                = 0xca,
-+	DBG_BLOCK_ID_TD0B                                = 0xcb,
-+	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
-+	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
-+	DBG_BLOCK_ID_UNUSED45                            = 0xce,
-+	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
-+	DBG_BLOCK_ID_TD10                                = 0xd0,
-+	DBG_BLOCK_ID_TD11                                = 0xd1,
-+	DBG_BLOCK_ID_TD12                                = 0xd2,
-+	DBG_BLOCK_ID_TD13                                = 0xd3,
-+	DBG_BLOCK_ID_TD14                                = 0xd4,
-+	DBG_BLOCK_ID_TD15                                = 0xd5,
-+	DBG_BLOCK_ID_TD16                                = 0xd6,
-+	DBG_BLOCK_ID_TD17                                = 0xd7,
-+	DBG_BLOCK_ID_TD18                                = 0xd8,
-+	DBG_BLOCK_ID_TD19                                = 0xd9,
-+	DBG_BLOCK_ID_TD1A                                = 0xda,
-+	DBG_BLOCK_ID_TD1B                                = 0xdb,
-+	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
-+	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
-+	DBG_BLOCK_ID_UNUSED49                            = 0xde,
-+	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
-+	DBG_BLOCK_ID_MCD0                                = 0xe0,
-+	DBG_BLOCK_ID_MCD1                                = 0xe1,
-+	DBG_BLOCK_ID_MCD2                                = 0xe2,
-+	DBG_BLOCK_ID_MCD3                                = 0xe3,
-+	DBG_BLOCK_ID_MCD4                                = 0xe4,
-+	DBG_BLOCK_ID_MCD5                                = 0xe5,
-+	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
-+	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
-+} DebugBlockId_OLD;
-+typedef enum DebugBlockId_BY2 {
-+	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
-+	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
-+	DBG_BLOCK_ID_CG_BY2                              = 0x2,
-+	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
-+	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
-+	DBG_BLOCK_ID_IH_BY2                              = 0x5,
-+	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
-+	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
-+	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
-+	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
-+	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
-+	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
-+	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
-+	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
-+	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
-+	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
-+	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
-+	DBG_BLOCK_ID_IA_BY2                              = 0x11,
-+	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
-+	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
-+	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
-+	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
-+	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
-+	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
-+	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
-+	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
-+	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
-+	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
-+	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
-+	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
-+	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
-+	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
-+	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
-+	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
-+	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
-+	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
-+	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
-+	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
-+	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
-+	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
-+	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
-+	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
-+	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
-+	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
-+	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
-+	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
-+	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
-+	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
-+	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
-+	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
-+	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
-+	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
-+	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
-+	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
-+	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
-+	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
-+	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
-+	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
-+	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
-+	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
-+	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
-+	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
-+	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
-+	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
-+	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
-+	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
-+	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
-+	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
-+	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
-+	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
-+	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
-+	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
-+	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
-+	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
-+	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
-+	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
-+	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
-+	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
-+	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
-+	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
-+	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
-+	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
-+	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
-+	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
-+	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
-+	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
-+	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
-+	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
-+	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
-+	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
-+	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
-+	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
-+	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
-+	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
-+	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
-+	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
-+	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
-+	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
-+	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
-+	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
-+	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
-+	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
-+	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
-+	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
-+	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
-+	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
-+	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
-+	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
-+	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
-+	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
-+	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
-+	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
-+	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
-+	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
-+	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
-+	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
-+} DebugBlockId_BY2;
-+typedef enum DebugBlockId_BY4 {
-+	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
-+	DBG_BLOCK_ID_CG_BY4                              = 0x1,
-+	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
-+	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
-+	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
-+	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
-+	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
-+	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
-+	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
-+	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
-+	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
-+	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
-+	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
-+	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
-+	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
-+	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
-+	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
-+	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
-+	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
-+	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
-+	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
-+	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
-+	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
-+	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
-+	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
-+	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
-+	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
-+	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
-+	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
-+	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
-+	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
-+	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
-+	DBG_BLOCK_ID_DB_BY4                              = 0x20,
-+	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
-+	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
-+	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
-+	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
-+	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
-+	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
-+	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
-+	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
-+	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
-+	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
-+	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
-+	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
-+	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
-+	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
-+	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
-+	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
-+	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
-+	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
-+	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
-+	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
-+	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
-+	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
-+	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
-+	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
-+	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
-+} DebugBlockId_BY4;
-+typedef enum DebugBlockId_BY8 {
-+	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
-+	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
-+	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
-+	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
-+	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
-+	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
-+	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
-+	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
-+	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
-+	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
-+	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
-+	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
-+	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
-+	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
-+	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
-+	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
-+	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
-+	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
-+	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
-+	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
-+	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
-+	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
-+	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
-+	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
-+	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
-+	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
-+	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
-+	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
-+	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
-+} DebugBlockId_BY8;
-+typedef enum DebugBlockId_BY16 {
-+	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
-+	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
-+	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
-+	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
-+	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
-+	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
-+	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
-+	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
-+	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
-+	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
-+	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
-+	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
-+	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
-+	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
-+	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
-+} DebugBlockId_BY16;
-+typedef enum ColorTransform {
-+	DCC_CT_AUTO                                      = 0x0,
-+	DCC_CT_NONE                                      = 0x1,
-+	ABGR_TO_A_BG_G_RB                                = 0x2,
-+	BGRA_TO_BG_G_RB_A                                = 0x3,
-+} ColorTransform;
-+typedef enum CompareRef {
-+	REF_NEVER                                        = 0x0,
-+	REF_LESS                                         = 0x1,
-+	REF_EQUAL                                        = 0x2,
-+	REF_LEQUAL                                       = 0x3,
-+	REF_GREATER                                      = 0x4,
-+	REF_NOTEQUAL                                     = 0x5,
-+	REF_GEQUAL                                       = 0x6,
-+	REF_ALWAYS                                       = 0x7,
-+} CompareRef;
-+typedef enum ReadSize {
-+	READ_256_BITS                                    = 0x0,
-+	READ_512_BITS                                    = 0x1,
-+} ReadSize;
-+typedef enum DepthFormat {
-+	DEPTH_INVALID                                    = 0x0,
-+	DEPTH_16                                         = 0x1,
-+	DEPTH_X8_24                                      = 0x2,
-+	DEPTH_8_24                                       = 0x3,
-+	DEPTH_X8_24_FLOAT                                = 0x4,
-+	DEPTH_8_24_FLOAT                                 = 0x5,
-+	DEPTH_32_FLOAT                                   = 0x6,
-+	DEPTH_X24_8_32_FLOAT                             = 0x7,
-+} DepthFormat;
-+typedef enum ZFormat {
-+	Z_INVALID                                        = 0x0,
-+	Z_16                                             = 0x1,
-+	Z_24                                             = 0x2,
-+	Z_32_FLOAT                                       = 0x3,
-+} ZFormat;
-+typedef enum StencilFormat {
-+	STENCIL_INVALID                                  = 0x0,
-+	STENCIL_8                                        = 0x1,
-+} StencilFormat;
-+typedef enum CmaskMode {
-+	CMASK_CLEAR_NONE                                 = 0x0,
-+	CMASK_CLEAR_ONE                                  = 0x1,
-+	CMASK_CLEAR_ALL                                  = 0x2,
-+	CMASK_ANY_EXPANDED                               = 0x3,
-+	CMASK_ALPHA0_FRAG1                               = 0x4,
-+	CMASK_ALPHA0_FRAG2                               = 0x5,
-+	CMASK_ALPHA0_FRAG4                               = 0x6,
-+	CMASK_ALPHA0_FRAGS                               = 0x7,
-+	CMASK_ALPHA1_FRAG1                               = 0x8,
-+	CMASK_ALPHA1_FRAG2                               = 0x9,
-+	CMASK_ALPHA1_FRAG4                               = 0xa,
-+	CMASK_ALPHA1_FRAGS                               = 0xb,
-+	CMASK_ALPHAX_FRAG1                               = 0xc,
-+	CMASK_ALPHAX_FRAG2                               = 0xd,
-+	CMASK_ALPHAX_FRAG4                               = 0xe,
-+	CMASK_ALPHAX_FRAGS                               = 0xf,
-+} CmaskMode;
-+typedef enum QuadExportFormat {
-+	EXPORT_UNUSED                                    = 0x0,
-+	EXPORT_32_R                                      = 0x1,
-+	EXPORT_32_GR                                     = 0x2,
-+	EXPORT_32_AR                                     = 0x3,
-+	EXPORT_FP16_ABGR                                 = 0x4,
-+	EXPORT_UNSIGNED16_ABGR                           = 0x5,
-+	EXPORT_SIGNED16_ABGR                             = 0x6,
-+	EXPORT_32_ABGR                                   = 0x7,
-+} QuadExportFormat;
-+typedef enum QuadExportFormatOld {
-+	EXPORT_4P_32BPC_ABGR                             = 0x0,
-+	EXPORT_4P_16BPC_ABGR                             = 0x1,
-+	EXPORT_4P_32BPC_GR                               = 0x2,
-+	EXPORT_4P_32BPC_AR                               = 0x3,
-+	EXPORT_2P_32BPC_ABGR                             = 0x4,
-+	EXPORT_8P_32BPC_R                                = 0x5,
-+} QuadExportFormatOld;
-+typedef enum ColorFormat {
-+	COLOR_INVALID                                    = 0x0,
-+	COLOR_8                                          = 0x1,
-+	COLOR_16                                         = 0x2,
-+	COLOR_8_8                                        = 0x3,
-+	COLOR_32                                         = 0x4,
-+	COLOR_16_16                                      = 0x5,
-+	COLOR_10_11_11                                   = 0x6,
-+	COLOR_11_11_10                                   = 0x7,
-+	COLOR_10_10_10_2                                 = 0x8,
-+	COLOR_2_10_10_10                                 = 0x9,
-+	COLOR_8_8_8_8                                    = 0xa,
-+	COLOR_32_32                                      = 0xb,
-+	COLOR_16_16_16_16                                = 0xc,
-+	COLOR_RESERVED_13                                = 0xd,
-+	COLOR_32_32_32_32                                = 0xe,
-+	COLOR_RESERVED_15                                = 0xf,
-+	COLOR_5_6_5                                      = 0x10,
-+	COLOR_1_5_5_5                                    = 0x11,
-+	COLOR_5_5_5_1                                    = 0x12,
-+	COLOR_4_4_4_4                                    = 0x13,
-+	COLOR_8_24                                       = 0x14,
-+	COLOR_24_8                                       = 0x15,
-+	COLOR_X24_8_32_FLOAT                             = 0x16,
-+	COLOR_RESERVED_23                                = 0x17,
-+} ColorFormat;
-+typedef enum SurfaceFormat {
-+	FMT_INVALID                                      = 0x0,
-+	FMT_8                                            = 0x1,
-+	FMT_16                                           = 0x2,
-+	FMT_8_8                                          = 0x3,
-+	FMT_32                                           = 0x4,
-+	FMT_16_16                                        = 0x5,
-+	FMT_10_11_11                                     = 0x6,
-+	FMT_11_11_10                                     = 0x7,
-+	FMT_10_10_10_2                                   = 0x8,
-+	FMT_2_10_10_10                                   = 0x9,
-+	FMT_8_8_8_8                                      = 0xa,
-+	FMT_32_32                                        = 0xb,
-+	FMT_16_16_16_16                                  = 0xc,
-+	FMT_32_32_32                                     = 0xd,
-+	FMT_32_32_32_32                                  = 0xe,
-+	FMT_RESERVED_4                                   = 0xf,
-+	FMT_5_6_5                                        = 0x10,
-+	FMT_1_5_5_5                                      = 0x11,
-+	FMT_5_5_5_1                                      = 0x12,
-+	FMT_4_4_4_4                                      = 0x13,
-+	FMT_8_24                                         = 0x14,
-+	FMT_24_8                                         = 0x15,
-+	FMT_X24_8_32_FLOAT                               = 0x16,
-+	FMT_RESERVED_33                                  = 0x17,
-+	FMT_11_11_10_FLOAT                               = 0x18,
-+	FMT_16_FLOAT                                     = 0x19,
-+	FMT_32_FLOAT                                     = 0x1a,
-+	FMT_16_16_FLOAT                                  = 0x1b,
-+	FMT_8_24_FLOAT                                   = 0x1c,
-+	FMT_24_8_FLOAT                                   = 0x1d,
-+	FMT_32_32_FLOAT                                  = 0x1e,
-+	FMT_10_11_11_FLOAT                               = 0x1f,
-+	FMT_16_16_16_16_FLOAT                            = 0x20,
-+	FMT_3_3_2                                        = 0x21,
-+	FMT_6_5_5                                        = 0x22,
-+	FMT_32_32_32_32_FLOAT                            = 0x23,
-+	FMT_RESERVED_36                                  = 0x24,
-+	FMT_1                                            = 0x25,
-+	FMT_1_REVERSED                                   = 0x26,
-+	FMT_GB_GR                                        = 0x27,
-+	FMT_BG_RG                                        = 0x28,
-+	FMT_32_AS_8                                      = 0x29,
-+	FMT_32_AS_8_8                                    = 0x2a,
-+	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
-+	FMT_8_8_8                                        = 0x2c,
-+	FMT_16_16_16                                     = 0x2d,
-+	FMT_16_16_16_FLOAT                               = 0x2e,
-+	FMT_4_4                                          = 0x2f,
-+	FMT_32_32_32_FLOAT                               = 0x30,
-+	FMT_BC1                                          = 0x31,
-+	FMT_BC2                                          = 0x32,
-+	FMT_BC3                                          = 0x33,
-+	FMT_BC4                                          = 0x34,
-+	FMT_BC5                                          = 0x35,
-+	FMT_BC6                                          = 0x36,
-+	FMT_BC7                                          = 0x37,
-+	FMT_32_AS_32_32_32_32                            = 0x38,
-+	FMT_APC3                                         = 0x39,
-+	FMT_APC4                                         = 0x3a,
-+	FMT_APC5                                         = 0x3b,
-+	FMT_APC6                                         = 0x3c,
-+	FMT_APC7                                         = 0x3d,
-+	FMT_CTX1                                         = 0x3e,
-+	FMT_RESERVED_63                                  = 0x3f,
-+} SurfaceFormat;
-+typedef enum BUF_DATA_FORMAT {
-+	BUF_DATA_FORMAT_INVALID                          = 0x0,
-+	BUF_DATA_FORMAT_8                                = 0x1,
-+	BUF_DATA_FORMAT_16                               = 0x2,
-+	BUF_DATA_FORMAT_8_8                              = 0x3,
-+	BUF_DATA_FORMAT_32                               = 0x4,
-+	BUF_DATA_FORMAT_16_16                            = 0x5,
-+	BUF_DATA_FORMAT_10_11_11                         = 0x6,
-+	BUF_DATA_FORMAT_11_11_10                         = 0x7,
-+	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
-+	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
-+	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
-+	BUF_DATA_FORMAT_32_32                            = 0xb,
-+	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
-+	BUF_DATA_FORMAT_32_32_32                         = 0xd,
-+	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
-+	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
-+} BUF_DATA_FORMAT;
-+typedef enum IMG_DATA_FORMAT {
-+	IMG_DATA_FORMAT_INVALID                          = 0x0,
-+	IMG_DATA_FORMAT_8                                = 0x1,
-+	IMG_DATA_FORMAT_16                               = 0x2,
-+	IMG_DATA_FORMAT_8_8                              = 0x3,
-+	IMG_DATA_FORMAT_32                               = 0x4,
-+	IMG_DATA_FORMAT_16_16                            = 0x5,
-+	IMG_DATA_FORMAT_10_11_11                         = 0x6,
-+	IMG_DATA_FORMAT_11_11_10                         = 0x7,
-+	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
-+	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
-+	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
-+	IMG_DATA_FORMAT_32_32                            = 0xb,
-+	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
-+	IMG_DATA_FORMAT_32_32_32                         = 0xd,
-+	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
-+	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
-+	IMG_DATA_FORMAT_5_6_5                            = 0x10,
-+	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
-+	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
-+	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
-+	IMG_DATA_FORMAT_8_24                             = 0x14,
-+	IMG_DATA_FORMAT_24_8                             = 0x15,
-+	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
-+	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
-+	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
-+	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
-+	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
-+	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
-+	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
-+	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
-+	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
-+	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
-+	IMG_DATA_FORMAT_GB_GR                            = 0x20,
-+	IMG_DATA_FORMAT_BG_RG                            = 0x21,
-+	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
-+	IMG_DATA_FORMAT_BC1                              = 0x23,
-+	IMG_DATA_FORMAT_BC2                              = 0x24,
-+	IMG_DATA_FORMAT_BC3                              = 0x25,
-+	IMG_DATA_FORMAT_BC4                              = 0x26,
-+	IMG_DATA_FORMAT_BC5                              = 0x27,
-+	IMG_DATA_FORMAT_BC6                              = 0x28,
-+	IMG_DATA_FORMAT_BC7                              = 0x29,
-+	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
-+	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
-+	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
-+	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
-+	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
-+	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
-+	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
-+	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
-+	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
-+	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
-+	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
-+	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
-+	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
-+	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
-+	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
-+	IMG_DATA_FORMAT_4_4                              = 0x39,
-+	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
-+	IMG_DATA_FORMAT_1                                = 0x3b,
-+	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
-+	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
-+	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
-+	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
-+} IMG_DATA_FORMAT;
-+typedef enum BUF_NUM_FORMAT {
-+	BUF_NUM_FORMAT_UNORM                             = 0x0,
-+	BUF_NUM_FORMAT_SNORM                             = 0x1,
-+	BUF_NUM_FORMAT_USCALED                           = 0x2,
-+	BUF_NUM_FORMAT_SSCALED                           = 0x3,
-+	BUF_NUM_FORMAT_UINT                              = 0x4,
-+	BUF_NUM_FORMAT_SINT                              = 0x5,
-+	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
-+	BUF_NUM_FORMAT_FLOAT                             = 0x7,
-+} BUF_NUM_FORMAT;
-+typedef enum IMG_NUM_FORMAT {
-+	IMG_NUM_FORMAT_UNORM                             = 0x0,
-+	IMG_NUM_FORMAT_SNORM                             = 0x1,
-+	IMG_NUM_FORMAT_USCALED                           = 0x2,
-+	IMG_NUM_FORMAT_SSCALED                           = 0x3,
-+	IMG_NUM_FORMAT_UINT                              = 0x4,
-+	IMG_NUM_FORMAT_SINT                              = 0x5,
-+	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
-+	IMG_NUM_FORMAT_FLOAT                             = 0x7,
-+	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
-+	IMG_NUM_FORMAT_SRGB                              = 0x9,
-+	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
-+	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
-+	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
-+	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
-+	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
-+	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
-+} IMG_NUM_FORMAT;
-+typedef enum TileType {
-+	ARRAY_COLOR_TILE                                 = 0x0,
-+	ARRAY_DEPTH_TILE                                 = 0x1,
-+} TileType;
-+typedef enum NonDispTilingOrder {
-+	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
-+	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
-+} NonDispTilingOrder;
-+typedef enum MicroTileMode {
-+	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
-+	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
-+	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
-+	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
-+	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
-+} MicroTileMode;
-+typedef enum TileSplit {
-+	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
-+	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
-+	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
-+	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
-+	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
-+	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
-+	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
-+} TileSplit;
-+typedef enum SampleSplit {
-+	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
-+	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
-+	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
-+	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
-+} SampleSplit;
-+typedef enum PipeConfig {
-+	ADDR_SURF_P2                                     = 0x0,
-+	ADDR_SURF_P2_RESERVED0                           = 0x1,
-+	ADDR_SURF_P2_RESERVED1                           = 0x2,
-+	ADDR_SURF_P2_RESERVED2                           = 0x3,
-+	ADDR_SURF_P4_8x16                                = 0x4,
-+	ADDR_SURF_P4_16x16                               = 0x5,
-+	ADDR_SURF_P4_16x32                               = 0x6,
-+	ADDR_SURF_P4_32x32                               = 0x7,
-+	ADDR_SURF_P8_16x16_8x16                          = 0x8,
-+	ADDR_SURF_P8_16x32_8x16                          = 0x9,
-+	ADDR_SURF_P8_32x32_8x16                          = 0xa,
-+	ADDR_SURF_P8_16x32_16x16                         = 0xb,
-+	ADDR_SURF_P8_32x32_16x16                         = 0xc,
-+	ADDR_SURF_P8_32x32_16x32                         = 0xd,
-+	ADDR_SURF_P8_32x64_32x32                         = 0xe,
-+	ADDR_SURF_P8_RESERVED0                           = 0xf,
-+	ADDR_SURF_P16_32x32_8x16                         = 0x10,
-+	ADDR_SURF_P16_32x32_16x16                        = 0x11,
-+} PipeConfig;
-+typedef enum NumBanks {
-+	ADDR_SURF_2_BANK                                 = 0x0,
-+	ADDR_SURF_4_BANK                                 = 0x1,
-+	ADDR_SURF_8_BANK                                 = 0x2,
-+	ADDR_SURF_16_BANK                                = 0x3,
-+} NumBanks;
-+typedef enum BankWidth {
-+	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
-+	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
-+	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
-+	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
-+} BankWidth;
-+typedef enum BankHeight {
-+	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
-+	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
-+	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
-+	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
-+} BankHeight;
-+typedef enum BankWidthHeight {
-+	ADDR_SURF_BANK_WH_1                              = 0x0,
-+	ADDR_SURF_BANK_WH_2                              = 0x1,
-+	ADDR_SURF_BANK_WH_4                              = 0x2,
-+	ADDR_SURF_BANK_WH_8                              = 0x3,
-+} BankWidthHeight;
-+typedef enum MacroTileAspect {
-+	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
-+	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
-+	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
-+	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
-+} MacroTileAspect;
-+typedef enum GATCL1RequestType {
-+	GATCL1_TYPE_NORMAL                               = 0x0,
-+	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
-+	GATCL1_TYPE_BYPASS                               = 0x2,
-+} GATCL1RequestType;
-+typedef enum TCC_CACHE_POLICIES {
-+	TCC_CACHE_POLICY_LRU                             = 0x0,
-+	TCC_CACHE_POLICY_STREAM                          = 0x1,
-+} TCC_CACHE_POLICIES;
-+typedef enum MTYPE {
-+	MTYPE_NC_NV                                      = 0x0,
-+	MTYPE_NC                                         = 0x1,
-+	MTYPE_CC                                         = 0x2,
-+	MTYPE_UC                                         = 0x3,
-+} MTYPE;
-+typedef enum PERFMON_COUNTER_MODE {
-+	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
-+	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
-+	PERFMON_COUNTER_MODE_MAX                         = 0x2,
-+	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
-+	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
-+	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
-+	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
-+	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
-+	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
-+	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
-+	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
-+} PERFMON_COUNTER_MODE;
-+typedef enum PERFMON_SPM_MODE {
-+	PERFMON_SPM_MODE_OFF                             = 0x0,
-+	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
-+	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
-+	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
-+	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
-+	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
-+	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
-+	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
-+	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
-+	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
-+	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
-+} PERFMON_SPM_MODE;
-+typedef enum SurfaceTiling {
-+	ARRAY_LINEAR                                     = 0x0,
-+	ARRAY_TILED                                      = 0x1,
-+} SurfaceTiling;
-+typedef enum SurfaceArray {
-+	ARRAY_1D                                         = 0x0,
-+	ARRAY_2D                                         = 0x1,
-+	ARRAY_3D                                         = 0x2,
-+	ARRAY_3D_SLICE                                   = 0x3,
-+} SurfaceArray;
-+typedef enum ColorArray {
-+	ARRAY_2D_ALT_COLOR                               = 0x0,
-+	ARRAY_2D_COLOR                                   = 0x1,
-+	ARRAY_3D_SLICE_COLOR                             = 0x3,
-+} ColorArray;
-+typedef enum DepthArray {
-+	ARRAY_2D_ALT_DEPTH                               = 0x0,
-+	ARRAY_2D_DEPTH                                   = 0x1,
-+} DepthArray;
-+typedef enum ENUM_NUM_SIMD_PER_CU {
-+	NUM_SIMD_PER_CU                                  = 0x4,
-+} ENUM_NUM_SIMD_PER_CU;
-+typedef enum MEM_PWR_FORCE_CTRL {
-+	NO_FORCE_REQUEST                                 = 0x0,
-+	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
-+	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
-+	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
-+} MEM_PWR_FORCE_CTRL;
-+typedef enum MEM_PWR_FORCE_CTRL2 {
-+	NO_FORCE_REQ                                     = 0x0,
-+	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
-+} MEM_PWR_FORCE_CTRL2;
-+typedef enum MEM_PWR_DIS_CTRL {
-+	ENABLE_MEM_PWR_CTRL                              = 0x0,
-+	DISABLE_MEM_PWR_CTRL                             = 0x1,
-+} MEM_PWR_DIS_CTRL;
-+typedef enum MEM_PWR_SEL_CTRL {
-+	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
-+	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
-+	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
-+} MEM_PWR_SEL_CTRL;
-+typedef enum MEM_PWR_SEL_CTRL2 {
-+	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
-+	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
-+} MEM_PWR_SEL_CTRL2;
-+typedef enum HPD_INT_CONTROL_ACK {
-+	HPD_INT_CONTROL_ACK_0                            = 0x0,
-+	HPD_INT_CONTROL_ACK_1                            = 0x1,
-+} HPD_INT_CONTROL_ACK;
-+typedef enum HPD_INT_CONTROL_POLARITY {
-+	HPD_INT_CONTROL_GEN_INT_ON_DISCON                = 0x0,
-+	HPD_INT_CONTROL_GEN_INT_ON_CON                   = 0x1,
-+} HPD_INT_CONTROL_POLARITY;
-+typedef enum HPD_INT_CONTROL_RX_INT_ACK {
-+	HPD_INT_CONTROL_RX_INT_ACK_0                     = 0x0,
-+	HPD_INT_CONTROL_RX_INT_ACK_1                     = 0x1,
-+} HPD_INT_CONTROL_RX_INT_ACK;
-+typedef enum DPDBG_EN {
-+	DPDBG_DISABLE                                    = 0x0,
-+	DPDBG_ENABLE                                     = 0x1,
-+} DPDBG_EN;
-+typedef enum DPDBG_INPUT_EN {
-+	DPDBG_INPUT_DISABLE                              = 0x0,
-+	DPDBG_INPUT_ENABLE                               = 0x1,
-+} DPDBG_INPUT_EN;
-+typedef enum DPDBG_ERROR_DETECTION_MODE {
-+	DPDBG_ERROR_DETECTION_MODE_CSC                   = 0x0,
-+	DPDBG_ERROR_DETECTION_MODE_RS_ENCODING           = 0x1,
-+} DPDBG_ERROR_DETECTION_MODE;
-+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
-+	DPDBG_FIFO_OVERFLOW_INT_DISABLE                  = 0x0,
-+	DPDBG_FIFO_OVERFLOW_INT_ENABLE                   = 0x1,
-+} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
-+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
-+	DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED              = 0x0,
-+	DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED              = 0x1,
-+} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
-+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
-+	DPDBG_FIFO_OVERFLOW_INT_NO_ACK                   = 0x0,
-+	DPDBG_FIFO_OVERFLOW_INT_CLEAR                    = 0x1,
-+} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
-+typedef enum PM_ASSERT_RESET {
-+	PM_ASSERT_RESET_0                                = 0x0,
-+	PM_ASSERT_RESET_1                                = 0x1,
-+} PM_ASSERT_RESET;
-+typedef enum DAC_MUX_SELECT {
-+	DAC_MUX_SELECT_DACA                              = 0x0,
-+	DAC_MUX_SELECT_DACB                              = 0x1,
-+} DAC_MUX_SELECT;
-+typedef enum TMDS_DVO_MUX_SELECT {
-+	TMDS_DVO_MUX_SELECT_B                            = 0x0,
-+	TMDS_DVO_MUX_SELECT_G                            = 0x1,
-+	TMDS_DVO_MUX_SELECT_R                            = 0x2,
-+	TMDS_DVO_MUX_SELECT_RESERVED                     = 0x3,
-+} TMDS_DVO_MUX_SELECT;
-+typedef enum DACA_SOFT_RESET {
-+	DACA_SOFT_RESET_0                                = 0x0,
-+	DACA_SOFT_RESET_1                                = 0x1,
-+} DACA_SOFT_RESET;
-+typedef enum I2S0_SPDIF0_SOFT_RESET {
-+	I2S0_SPDIF0_SOFT_RESET_0                         = 0x0,
-+	I2S0_SPDIF0_SOFT_RESET_1                         = 0x1,
-+} I2S0_SPDIF0_SOFT_RESET;
-+typedef enum I2S1_SOFT_RESET {
-+	I2S1_SOFT_RESET_0                                = 0x0,
-+	I2S1_SOFT_RESET_1                                = 0x1,
-+} I2S1_SOFT_RESET;
-+typedef enum SPDIF1_SOFT_RESET {
-+	SPDIF1_SOFT_RESET_0                              = 0x0,
-+	SPDIF1_SOFT_RESET_1                              = 0x1,
-+} SPDIF1_SOFT_RESET;
-+typedef enum DB_CLK_SOFT_RESET {
-+	DB_CLK_SOFT_RESET_0                              = 0x0,
-+	DB_CLK_SOFT_RESET_1                              = 0x1,
-+} DB_CLK_SOFT_RESET;
-+typedef enum FMT0_SOFT_RESET {
-+	FMT0_SOFT_RESET_0                                = 0x0,
-+	FMT0_SOFT_RESET_1                                = 0x1,
-+} FMT0_SOFT_RESET;
-+typedef enum FMT1_SOFT_RESET {
-+	FMT1_SOFT_RESET_0                                = 0x0,
-+	FMT1_SOFT_RESET_1                                = 0x1,
-+} FMT1_SOFT_RESET;
-+typedef enum FMT2_SOFT_RESET {
-+	FMT2_SOFT_RESET_0                                = 0x0,
-+	FMT2_SOFT_RESET_1                                = 0x1,
-+} FMT2_SOFT_RESET;
-+typedef enum FMT3_SOFT_RESET {
-+	FMT3_SOFT_RESET_0                                = 0x0,
-+	FMT3_SOFT_RESET_1                                = 0x1,
-+} FMT3_SOFT_RESET;
-+typedef enum FMT4_SOFT_RESET {
-+	FMT4_SOFT_RESET_0                                = 0x0,
-+	FMT4_SOFT_RESET_1                                = 0x1,
-+} FMT4_SOFT_RESET;
-+typedef enum FMT5_SOFT_RESET {
-+	FMT5_SOFT_RESET_0                                = 0x0,
-+	FMT5_SOFT_RESET_1                                = 0x1,
-+} FMT5_SOFT_RESET;
-+typedef enum MVP_SOFT_RESET {
-+	MVP_SOFT_RESET_0                                 = 0x0,
-+	MVP_SOFT_RESET_1                                 = 0x1,
-+} MVP_SOFT_RESET;
-+typedef enum ABM_SOFT_RESET {
-+	ABM_SOFT_RESET_0                                 = 0x0,
-+	ABM_SOFT_RESET_1                                 = 0x1,
-+} ABM_SOFT_RESET;
-+typedef enum DVO_SOFT_RESET {
-+	DVO_SOFT_RESET_0                                 = 0x0,
-+	DVO_SOFT_RESET_1                                 = 0x1,
-+} DVO_SOFT_RESET;
-+typedef enum DIGA_FE_SOFT_RESET {
-+	DIGA_FE_SOFT_RESET_0                             = 0x0,
-+	DIGA_FE_SOFT_RESET_1                             = 0x1,
-+} DIGA_FE_SOFT_RESET;
-+typedef enum DIGA_BE_SOFT_RESET {
-+	DIGA_BE_SOFT_RESET_0                             = 0x0,
-+	DIGA_BE_SOFT_RESET_1                             = 0x1,
-+} DIGA_BE_SOFT_RESET;
-+typedef enum DIGB_FE_SOFT_RESET {
-+	DIGB_FE_SOFT_RESET_0                             = 0x0,
-+	DIGB_FE_SOFT_RESET_1                             = 0x1,
-+} DIGB_FE_SOFT_RESET;
-+typedef enum DIGB_BE_SOFT_RESET {
-+	DIGB_BE_SOFT_RESET_0                             = 0x0,
-+	DIGB_BE_SOFT_RESET_1                             = 0x1,
-+} DIGB_BE_SOFT_RESET;
-+typedef enum DIGC_FE_SOFT_RESET {
-+	DIGC_FE_SOFT_RESET_0                             = 0x0,
-+	DIGC_FE_SOFT_RESET_1                             = 0x1,
-+} DIGC_FE_SOFT_RESET;
-+typedef enum DIGC_BE_SOFT_RESET {
-+	DIGC_BE_SOFT_RESET_0                             = 0x0,
-+	DIGC_BE_SOFT_RESET_1                             = 0x1,
-+} DIGC_BE_SOFT_RESET;
-+typedef enum DIGD_FE_SOFT_RESET {
-+	DIGD_FE_SOFT_RESET_0                             = 0x0,
-+	DIGD_FE_SOFT_RESET_1                             = 0x1,
-+} DIGD_FE_SOFT_RESET;
-+typedef enum DIGD_BE_SOFT_RESET {
-+	DIGD_BE_SOFT_RESET_0                             = 0x0,
-+	DIGD_BE_SOFT_RESET_1                             = 0x1,
-+} DIGD_BE_SOFT_RESET;
-+typedef enum DIGE_FE_SOFT_RESET {
-+	DIGE_FE_SOFT_RESET_0                             = 0x0,
-+	DIGE_FE_SOFT_RESET_1                             = 0x1,
-+} DIGE_FE_SOFT_RESET;
-+typedef enum DIGE_BE_SOFT_RESET {
-+	DIGE_BE_SOFT_RESET_0                             = 0x0,
-+	DIGE_BE_SOFT_RESET_1                             = 0x1,
-+} DIGE_BE_SOFT_RESET;
-+typedef enum DIGF_FE_SOFT_RESET {
-+	DIGF_FE_SOFT_RESET_0                             = 0x0,
-+	DIGF_FE_SOFT_RESET_1                             = 0x1,
-+} DIGF_FE_SOFT_RESET;
-+typedef enum DIGF_BE_SOFT_RESET {
-+	DIGF_BE_SOFT_RESET_0                             = 0x0,
-+	DIGF_BE_SOFT_RESET_1                             = 0x1,
-+} DIGF_BE_SOFT_RESET;
-+typedef enum DIGG_FE_SOFT_RESET {
-+	DIGG_FE_SOFT_RESET_0                             = 0x0,
-+	DIGG_FE_SOFT_RESET_1                             = 0x1,
-+} DIGG_FE_SOFT_RESET;
-+typedef enum DIGG_BE_SOFT_RESET {
-+	DIGG_BE_SOFT_RESET_0                             = 0x0,
-+	DIGG_BE_SOFT_RESET_1                             = 0x1,
-+} DIGG_BE_SOFT_RESET;
-+typedef enum DPDBG_SOFT_RESET {
-+	DPDBG_SOFT_RESET_0                               = 0x0,
-+	DPDBG_SOFT_RESET_1                               = 0x1,
-+} DPDBG_SOFT_RESET;
-+typedef enum DIGLPA_FE_SOFT_RESET {
-+	DIGLPA_FE_SOFT_RESET_0                           = 0x0,
-+	DIGLPA_FE_SOFT_RESET_1                           = 0x1,
-+} DIGLPA_FE_SOFT_RESET;
-+typedef enum DIGLPA_BE_SOFT_RESET {
-+	DIGLPA_BE_SOFT_RESET_0                           = 0x0,
-+	DIGLPA_BE_SOFT_RESET_1                           = 0x1,
-+} DIGLPA_BE_SOFT_RESET;
-+typedef enum DIGLPB_FE_SOFT_RESET {
-+	DIGLPB_FE_SOFT_RESET_0                           = 0x0,
-+	DIGLPB_FE_SOFT_RESET_1                           = 0x1,
-+} DIGLPB_FE_SOFT_RESET;
-+typedef enum DIGLPB_BE_SOFT_RESET {
-+	DIGLPB_BE_SOFT_RESET_0                           = 0x0,
-+	DIGLPB_BE_SOFT_RESET_1                           = 0x1,
-+} DIGLPB_BE_SOFT_RESET;
-+typedef enum GENERICA_STEREOSYNC_SEL {
-+	GENERICA_STEREOSYNC_SEL_D1                       = 0x0,
-+	GENERICA_STEREOSYNC_SEL_D2                       = 0x1,
-+	GENERICA_STEREOSYNC_SEL_D3                       = 0x2,
-+	GENERICA_STEREOSYNC_SEL_D4                       = 0x3,
-+	GENERICA_STEREOSYNC_SEL_D5                       = 0x4,
-+	GENERICA_STEREOSYNC_SEL_D6                       = 0x5,
-+	GENERICA_STEREOSYNC_SEL_RESERVED                 = 0x6,
-+} GENERICA_STEREOSYNC_SEL;
-+typedef enum GENERICB_STEREOSYNC_SEL {
-+	GENERICB_STEREOSYNC_SEL_D1                       = 0x0,
-+	GENERICB_STEREOSYNC_SEL_D2                       = 0x1,
-+	GENERICB_STEREOSYNC_SEL_D3                       = 0x2,
-+	GENERICB_STEREOSYNC_SEL_D4                       = 0x3,
-+	GENERICB_STEREOSYNC_SEL_D5                       = 0x4,
-+	GENERICB_STEREOSYNC_SEL_D6                       = 0x5,
-+	GENERICB_STEREOSYNC_SEL_RESERVED                 = 0x6,
-+} GENERICB_STEREOSYNC_SEL;
-+typedef enum DCO_DBG_BLOCK_SEL {
-+	DCO_DBG_BLOCK_SEL_DCO                            = 0x0,
-+	DCO_DBG_BLOCK_SEL_ABM                            = 0x1,
-+	DCO_DBG_BLOCK_SEL_DVO                            = 0x2,
-+	DCO_DBG_BLOCK_SEL_DAC                            = 0x3,
-+	DCO_DBG_BLOCK_SEL_MVP                            = 0x4,
-+	DCO_DBG_BLOCK_SEL_FMT0                           = 0x5,
-+	DCO_DBG_BLOCK_SEL_FMT1                           = 0x6,
-+	DCO_DBG_BLOCK_SEL_FMT2                           = 0x7,
-+	DCO_DBG_BLOCK_SEL_FMT3                           = 0x8,
-+	DCO_DBG_BLOCK_SEL_FMT4                           = 0x9,
-+	DCO_DBG_BLOCK_SEL_FMT5                           = 0xa,
-+	DCO_DBG_BLOCK_SEL_DIGFE_A                        = 0xb,
-+	DCO_DBG_BLOCK_SEL_DIGFE_B                        = 0xc,
-+	DCO_DBG_BLOCK_SEL_DIGFE_C                        = 0xd,
-+	DCO_DBG_BLOCK_SEL_DIGFE_D                        = 0xe,
-+	DCO_DBG_BLOCK_SEL_DIGFE_E                        = 0xf,
-+	DCO_DBG_BLOCK_SEL_DIGFE_F                        = 0x10,
-+	DCO_DBG_BLOCK_SEL_DIGFE_G                        = 0x11,
-+	DCO_DBG_BLOCK_SEL_DIGA                           = 0x12,
-+	DCO_DBG_BLOCK_SEL_DIGB                           = 0x13,
-+	DCO_DBG_BLOCK_SEL_DIGC                           = 0x14,
-+	DCO_DBG_BLOCK_SEL_DIGD                           = 0x15,
-+	DCO_DBG_BLOCK_SEL_DIGE                           = 0x16,
-+	DCO_DBG_BLOCK_SEL_DIGF                           = 0x17,
-+	DCO_DBG_BLOCK_SEL_DIGG                           = 0x18,
-+	DCO_DBG_BLOCK_SEL_DPFE_A                         = 0x19,
-+	DCO_DBG_BLOCK_SEL_DPFE_B                         = 0x1a,
-+	DCO_DBG_BLOCK_SEL_DPFE_C                         = 0x1b,
-+	DCO_DBG_BLOCK_SEL_DPFE_D                         = 0x1c,
-+	DCO_DBG_BLOCK_SEL_DPFE_E                         = 0x1d,
-+	DCO_DBG_BLOCK_SEL_DPFE_F                         = 0x1e,
-+	DCO_DBG_BLOCK_SEL_DPFE_G                         = 0x1f,
-+	DCO_DBG_BLOCK_SEL_DPA                            = 0x20,
-+	DCO_DBG_BLOCK_SEL_DPB                            = 0x21,
-+	DCO_DBG_BLOCK_SEL_DPC                            = 0x22,
-+	DCO_DBG_BLOCK_SEL_DPD                            = 0x23,
-+	DCO_DBG_BLOCK_SEL_DPE                            = 0x24,
-+	DCO_DBG_BLOCK_SEL_DPF                            = 0x25,
-+	DCO_DBG_BLOCK_SEL_DPG                            = 0x26,
-+	DCO_DBG_BLOCK_SEL_AUX0                           = 0x27,
-+	DCO_DBG_BLOCK_SEL_AUX1                           = 0x28,
-+	DCO_DBG_BLOCK_SEL_AUX2                           = 0x29,
-+	DCO_DBG_BLOCK_SEL_AUX3                           = 0x2a,
-+	DCO_DBG_BLOCK_SEL_AUX4                           = 0x2b,
-+	DCO_DBG_BLOCK_SEL_AUX5                           = 0x2c,
-+	DCO_DBG_BLOCK_SEL_PERFMON_DCO                    = 0x2d,
-+	DCO_DBG_BLOCK_SEL_AUDIO_OUT                      = 0x2e,
-+	DCO_DBG_BLOCK_SEL_DIGLPFEA                       = 0x2f,
-+	DCO_DBG_BLOCK_SEL_DIGLPFEB                       = 0x30,
-+	DCO_DBG_BLOCK_SEL_DIGLPA                         = 0x31,
-+	DCO_DBG_BLOCK_SEL_DIGLPB                         = 0x32,
-+	DCO_DBG_BLOCK_SEL_DPLPFEA                        = 0x33,
-+	DCO_DBG_BLOCK_SEL_DPLPFEB                        = 0x34,
-+	DCO_DBG_BLOCK_SEL_DPLPA                          = 0x35,
-+	DCO_DBG_BLOCK_SEL_DPLPB                          = 0x36,
-+} DCO_DBG_BLOCK_SEL;
-+typedef enum DCO_DBG_CLOCK_SEL {
-+	DCO_DBG_CLOCK_SEL_DISPCLK                        = 0x0,
-+	DCO_DBG_CLOCK_SEL_SCLK                           = 0x1,
-+	DCO_DBG_CLOCK_SEL_MVPCLK                         = 0x2,
-+	DCO_DBG_CLOCK_SEL_DVOCLK                         = 0x3,
-+	DCO_DBG_CLOCK_SEL_DACCLK                         = 0x4,
-+	DCO_DBG_CLOCK_SEL_REFCLK                         = 0x5,
-+	DCO_DBG_CLOCK_SEL_SYMCLKA                        = 0x6,
-+	DCO_DBG_CLOCK_SEL_SYMCLKB                        = 0x7,
-+	DCO_DBG_CLOCK_SEL_SYMCLKC                        = 0x8,
-+	DCO_DBG_CLOCK_SEL_SYMCLKD                        = 0x9,
-+	DCO_DBG_CLOCK_SEL_SYMCLKE                        = 0xa,
-+	DCO_DBG_CLOCK_SEL_SYMCLKF                        = 0xb,
-+	DCO_DBG_CLOCK_SEL_SYMCLKG                        = 0xc,
-+	DCO_DBG_CLOCK_SEL_RESERVED                       = 0xd,
-+	DCO_DBG_CLOCK_SEL_AM0CLK                         = 0xe,
-+	DCO_DBG_CLOCK_SEL_AM1CLK                         = 0xf,
-+	DCO_DBG_CLOCK_SEL_AM2CLK                         = 0x10,
-+	DCO_DBG_CLOCK_SEL_SYMCLKLPA                      = 0x11,
-+	DCO_DBG_CLOCK_SEL_SYMCLKLPB                      = 0x12,
-+} DCO_DBG_CLOCK_SEL;
-+typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
-+	DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL               = 0x0,
-+	DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE               = 0x1,
-+} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
-+typedef enum FMT420_MEMORY_SOURCE_SEL {
-+	FMT420_MEMORY_SOURCE_SEL_FMT0                    = 0x0,
-+	FMT420_MEMORY_SOURCE_SEL_FMT1                    = 0x1,
-+	FMT420_MEMORY_SOURCE_SEL_FMT2                    = 0x2,
-+	FMT420_MEMORY_SOURCE_SEL_FMT3                    = 0x3,
-+	FMT420_MEMORY_SOURCE_SEL_FMT4                    = 0x4,
-+	FMT420_MEMORY_SOURCE_SEL_FMT5                    = 0x5,
-+	FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED            = 0x6,
-+} FMT420_MEMORY_SOURCE_SEL;
-+typedef enum DOUT_I2C_CONTROL_GO {
-+	DOUT_I2C_CONTROL_STOP_TRANSFER                   = 0x0,
-+	DOUT_I2C_CONTROL_START_TRANSFER                  = 0x1,
-+} DOUT_I2C_CONTROL_GO;
-+typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
-+	DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER        = 0x0,
-+	DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER            = 0x1,
-+} DOUT_I2C_CONTROL_SOFT_RESET;
-+typedef enum DOUT_I2C_CONTROL_SEND_RESET {
-+	DOUT_I2C_CONTROL__NOT_SEND_RESET                 = 0x0,
-+	DOUT_I2C_CONTROL__SEND_RESET                     = 0x1,
-+} DOUT_I2C_CONTROL_SEND_RESET;
-+typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
-+	DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS             = 0x0,
-+	DOUT_I2C_CONTROL_RESET_SW_STATUS                 = 0x1,
-+} DOUT_I2C_CONTROL_SW_STATUS_RESET;
-+typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
-+	DOUT_I2C_CONTROL_SELECT_DDC1                     = 0x0,
-+	DOUT_I2C_CONTROL_SELECT_DDC2                     = 0x1,
-+	DOUT_I2C_CONTROL_SELECT_DDC3                     = 0x2,
-+	DOUT_I2C_CONTROL_SELECT_DDC4                     = 0x3,
-+	DOUT_I2C_CONTROL_SELECT_DDC5                     = 0x4,
-+	DOUT_I2C_CONTROL_SELECT_DDC6                     = 0x5,
-+	DOUT_I2C_CONTROL_SELECT_DDCVGA                   = 0x6,
-+} DOUT_I2C_CONTROL_DDC_SELECT;
-+typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
-+	DOUT_I2C_CONTROL_TRANS0                          = 0x0,
-+	DOUT_I2C_CONTROL_TRANS0_TRANS1                   = 0x1,
-+	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2            = 0x2,
-+	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3     = 0x3,
-+} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
-+typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
-+	DOUT_I2C_CONTROL_NORMAL_DEBUG                    = 0x0,
-+	DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG            = 0x1,
-+} DOUT_I2C_CONTROL_DBG_REF_SEL;
-+typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
-+	DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL          = 0x0,
-+	DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH            = 0x1,
-+	DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED      = 0x2,
-+	DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED      = 0x3,
-+} DOUT_I2C_ARBITRATION_SW_PRIORITY;
-+typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
-+	DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED            = 0x0,
-+	DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED           = 0x1,
-+} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
-+typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
-+	DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER  = 0x0,
-+	DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER      = 0x1,
-+} DOUT_I2C_ARBITRATION_ABORT_XFER;
-+typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
-+	DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ        = 0x0,
-+	DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ            = 0x1,
-+} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
-+typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
-+	DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG     = 0x0,
-+	DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG         = 0x1,
-+} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
-+typedef enum DOUT_I2C_ACK {
-+	DOUT_I2C_NO_ACK                                  = 0x0,
-+	DOUT_I2C_ACK_TO_CLEAN                            = 0x1,
-+} DOUT_I2C_ACK;
-+typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
-+	DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO       = 0x0,
-+	DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
-+	DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
-+	DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
-+} DOUT_I2C_DDC_SPEED_THRESHOLD;
-+typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
-+	DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
-+	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA             = 0x1,
-+} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
-+typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
-+	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS        = 0x0,
-+	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS        = 0x1,
-+} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
-+typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
-+	DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT           = 0x0,
-+	DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT        = 0x1,
-+} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
-+typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
-+	DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
-+	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL             = 0x1,
-+} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
-+typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
-+	DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS          = 0x0,
-+	DOUT_I2C_TRANSACTION_STOP_ALL_TRANS              = 0x1,
-+} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
-+typedef enum DOUT_I2C_DATA_INDEX_WRITE {
-+	DOUT_I2C_DATA__NOT_INDEX_WRITE                   = 0x0,
-+	DOUT_I2C_DATA__INDEX_WRITE                       = 0x1,
-+} DOUT_I2C_DATA_INDEX_WRITE;
-+typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
-+	DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
-+	DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
-+} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
-+typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
-+	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL      = 0x0,
-+	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE      = 0x1,
-+} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
-+typedef enum BLNDV_CONTROL_BLND_MODE {
-+	BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY        = 0x0,
-+	BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY          = 0x1,
-+	BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE      = 0x2,
-+	BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE        = 0x3,
-+} BLNDV_CONTROL_BLND_MODE;
-+typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
-+	BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
-+	BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
-+	BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
-+	BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED            = 0x3,
-+} BLNDV_CONTROL_BLND_STEREO_TYPE;
-+typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
-+	BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW           = 0x0,
-+	BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH          = 0x1,
-+} BLNDV_CONTROL_BLND_STEREO_POLARITY;
-+typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
-+	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE          = 0x0,
-+	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE           = 0x1,
-+} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
-+typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
-+	BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
-+	BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
-+	BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY  = 0x2,
-+	BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED             = 0x3,
-+} BLNDV_CONTROL_BLND_ALPHA_MODE;
-+typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
-+	BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE     = 0x0,
-+	BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE      = 0x1,
-+} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
-+typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
-+	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE         = 0x0,
-+	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE          = 0x1,
-+} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
-+typedef enum BLNDV_SM_CONTROL2_SM_MODE {
-+	BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE           = 0x0,
-+	BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING        = 0x2,
-+	BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING     = 0x4,
-+	BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
-+} BLNDV_SM_CONTROL2_SM_MODE;
-+typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
-+	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE       = 0x0,
-+	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE        = 0x1,
-+} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
-+typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
-+	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE       = 0x0,
-+	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE        = 0x1,
-+} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
-+typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
-+} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
-+typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
-+	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
-+} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
-+typedef enum BLNDV_CONTROL2_PTI_ENABLE {
-+	BLNDV_CONTROL2_PTI_ENABLE_FALSE                  = 0x0,
-+	BLNDV_CONTROL2_PTI_ENABLE_TRUE                   = 0x1,
-+} BLNDV_CONTROL2_PTI_ENABLE;
-+typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
-+	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE     = 0x0,
-+	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE      = 0x1,
-+} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
-+typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
-+	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE     = 0x0,
-+	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE      = 0x1,
-+} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
-+typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
-+	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
-+	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
-+} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
-+typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
-+	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
-+	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
-+} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
-+	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE  = 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
-+	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
-+typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
-+	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
-+	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
-+} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
-+typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
-+	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW              = 0x0,
-+	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH             = 0x1,
-+} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
-+typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
-+	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
-+	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
-+} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
-+typedef enum DPCSTX_DBG_CFGCLK_SEL {
-+	DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF                = 0x0,
-+	DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF              = 0x1,
-+	DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE                 = 0x2,
-+	DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER                = 0x3,
-+} DPCSTX_DBG_CFGCLK_SEL;
-+typedef enum DPCSTX_TX_SYMCLK_SEL {
-+	DPCSTX_DBG_TX_SYMCLK_SEL_IN0                     = 0x0,
-+	DPCSTX_DBG_TX_SYMCLK_SEL_IN1                     = 0x1,
-+	DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR                 = 0x2,
-+} DPCSTX_TX_SYMCLK_SEL;
-+typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
-+	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0               = 0x0,
-+	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1               = 0x1,
-+	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2               = 0x2,
-+	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3               = 0x3,
-+	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD            = 0x4,
-+	DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT                = 0x5,
-+} DPCSTX_TX_SYMCLK_DIV2_SEL;
-+typedef enum DPCSTX_DBG_CLOCK_SEL {
-+	DPCSTX_DBG_CLOCK_SEL_DC_CFGCLK                   = 0x0,
-+	DPCSTX_DBG_CLOCK_SEL_PHY_CFGCLK                  = 0x1,
-+	DPCSTX_DBG_CLOCK_SEL_TXSYMCLK                    = 0x2,
-+} DPCSTX_DBG_CLOCK_SEL;
-+typedef enum DPCSTX_DVI_LINK_MODE {
-+	DPCSTX_DVI_LINK_MODE_NORMAL                      = 0x0,
-+	DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER            = 0x1,
-+	DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER            = 0x2,
-+} DPCSTX_DVI_LINK_MODE;
-+
-+#endif /* DCE_11_2_ENUM_H */
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
-new file mode 100755
-index 0000000..1ddc418
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h
-@@ -0,0 +1,18687 @@
-+/*
-+ * DCE_11_2 Register documentation
-+ *
-+ * Copyright (C) 2016  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef DCE_11_2_SH_MASK_H
-+#define DCE_11_2_SH_MASK_H
-+
-+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
-+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
-+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
-+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
-+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
-+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
-+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
-+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
-+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
-+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
-+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
-+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
-+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
-+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
-+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
-+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
-+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
-+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
-+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
-+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
-+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
-+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
-+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
-+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
-+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
-+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
-+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
-+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
-+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
-+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
-+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
-+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
-+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
-+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
-+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
-+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
-+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
-+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
-+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
-+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
-+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
-+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
-+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
-+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
-+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
-+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
-+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff
-+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0
-+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000
-+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18
-+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000
-+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
-+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000
-+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d
-+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000
-+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
-+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
-+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
-+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
-+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
-+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff
-+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0
-+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000
-+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18
-+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000
-+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
-+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000
-+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d
-+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000
-+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
-+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1
-+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
-+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1
-+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
-+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff
-+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0
-+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000
-+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18
-+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000
-+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
-+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
-+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d
-+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000
-+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
-+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1
-+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0
-+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x2
-+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
-+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x4
-+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2
-+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8
-+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
-+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10
-+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4
-+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x20
-+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
-+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x40
-+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6
-+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x80
-+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
-+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100
-+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
-+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200
-+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
-+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x400
-+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa
-+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800
-+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
-+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1000
-+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc
-+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x2000
-+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
-+#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x4000
-+#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe
-+#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x8000
-+#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
-+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x10000
-+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x10
-+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x20000
-+#define DCPG_INTERRUPT_STATUS__DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x11
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x1
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x2
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x4
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8
-+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x20
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x40
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80
-+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x400
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800
-+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x1000
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x2000
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x4000
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x8000
-+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x10000
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x20000
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x40000
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x80000
-+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x100000
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x200000
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x400000
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
-+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x1000000
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x2000000
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x4000000
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x8000000
-+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000
-+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK_MASK 0x1000000
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_MASK__SHIFT 0x18
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR_MASK 0x2000000
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x19
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK_MASK 0x4000000
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_MASK__SHIFT 0x1a
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x8000000
-+#define DCPG_INTERRUPT_CONTROL2__DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
-+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
-+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
-+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
-+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
-+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
-+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
-+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
-+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
-+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
-+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
-+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
-+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
-+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
-+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
-+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
-+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
-+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
-+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
-+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
-+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
-+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
-+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
-+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
-+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
-+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
-+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
-+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
-+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
-+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
-+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
-+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
-+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
-+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
-+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
-+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
-+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
-+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
-+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
-+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
-+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
-+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
-+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
-+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
-+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
-+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
-+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
-+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
-+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
-+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
-+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
-+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
-+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
-+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
-+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
-+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
-+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
-+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
-+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
-+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
-+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
-+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
-+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
-+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
-+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
-+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
-+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
-+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
-+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
-+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
-+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
-+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
-+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
-+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
-+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
-+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
-+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
-+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
-+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
-+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
-+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
-+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
-+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
-+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
-+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
-+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
-+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
-+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
-+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
-+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
-+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
-+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
-+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
-+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
-+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
-+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
-+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
-+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
-+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
-+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
-+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
-+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
-+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
-+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
-+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
-+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
-+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
-+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
-+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
-+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
-+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
-+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
-+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
-+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
-+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
-+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
-+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
-+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
-+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
-+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
-+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
-+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
-+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
-+#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
-+#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
-+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
-+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
-+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
-+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
-+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
-+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
-+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
-+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
-+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
-+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
-+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
-+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
-+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
-+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
-+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
-+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
-+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
-+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
-+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
-+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
-+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
-+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
-+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
-+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
-+#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
-+#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
-+#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
-+#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
-+#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
-+#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
-+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
-+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
-+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
-+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
-+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
-+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
-+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
-+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
-+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
-+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
-+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
-+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
-+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
-+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
-+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
-+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
-+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
-+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
-+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
-+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
-+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
-+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
-+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
-+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
-+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
-+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
-+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
-+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
-+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
-+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
-+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
-+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
-+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
-+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
-+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
-+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
-+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
-+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
-+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
-+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
-+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
-+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
-+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
-+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
-+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
-+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
-+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
-+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
-+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
-+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
-+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
-+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
-+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
-+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
-+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
-+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
-+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
-+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
-+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
-+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
-+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
-+#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
-+#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
-+#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
-+#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
-+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
-+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
-+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
-+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
-+#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
-+#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
-+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
-+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
-+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
-+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
-+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
-+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
-+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
-+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
-+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
-+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
-+#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
-+#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
-+#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
-+#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
-+#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
-+#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
-+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
-+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
-+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
-+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
-+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
-+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
-+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
-+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
-+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
-+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
-+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
-+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
-+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
-+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
-+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
-+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
-+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
-+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
-+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
-+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
-+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
-+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
-+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
-+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
-+#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
-+#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
-+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
-+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
-+#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
-+#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
-+#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
-+#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
-+#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
-+#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
-+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
-+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
-+#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
-+#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
-+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
-+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
-+#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
-+#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
-+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
-+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
-+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
-+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
-+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
-+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
-+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
-+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
-+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
-+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
-+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
-+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
-+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
-+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
-+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
-+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
-+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
-+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
-+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
-+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
-+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
-+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
-+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
-+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
-+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
-+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
-+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
-+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
-+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
-+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
-+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
-+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
-+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
-+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
-+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
-+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
-+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
-+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
-+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
-+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
-+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
-+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
-+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
-+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
-+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
-+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
-+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
-+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
-+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
-+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
-+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2
-+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
-+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4
-+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
-+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100
-+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
-+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
-+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
-+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
-+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
-+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
-+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
-+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
-+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
-+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
-+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
-+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
-+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
-+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
-+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
-+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
-+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
-+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
-+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
-+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
-+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
-+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
-+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
-+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
-+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
-+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
-+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
-+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
-+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
-+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
-+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
-+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
-+#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
-+#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
-+#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
-+#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
-+#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000
-+#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
-+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
-+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
-+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
-+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
-+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
-+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
-+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
-+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
-+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
-+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
-+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
-+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
-+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
-+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
-+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
-+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
-+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
-+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
-+#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
-+#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
-+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
-+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
-+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
-+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
-+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
-+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
-+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
-+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
-+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
-+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
-+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
-+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
-+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
-+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
-+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
-+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
-+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
-+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
-+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
-+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
-+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
-+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
-+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
-+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
-+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
-+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
-+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
-+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
-+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
-+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
-+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
-+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
-+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
-+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
-+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
-+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
-+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
-+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
-+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
-+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
-+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
-+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
-+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
-+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
-+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
-+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
-+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
-+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
-+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
-+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
-+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
-+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
-+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
-+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
-+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
-+#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
-+#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
-+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
-+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
-+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
-+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
-+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
-+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
-+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
-+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
-+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
-+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
-+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
-+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
-+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
-+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
-+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
-+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
-+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
-+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
-+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
-+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
-+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
-+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
-+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
-+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
-+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
-+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
-+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
-+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
-+#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
-+#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
-+#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
-+#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
-+#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
-+#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
-+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
-+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
-+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
-+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
-+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
-+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
-+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
-+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
-+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
-+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
-+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
-+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
-+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
-+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
-+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
-+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
-+#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
-+#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
-+#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
-+#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
-+#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
-+#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000
-+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000
-+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000
-+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000
-+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000
-+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_MASK 0x40000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000
-+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
-+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
-+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
-+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
-+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
-+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
-+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
-+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
-+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
-+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
-+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
-+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
-+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
-+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
-+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
-+#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
-+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
-+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
-+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
-+#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
-+#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
-+#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
-+#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
-+#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
-+#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
-+#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
-+#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
-+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100
-+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
-+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
-+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
-+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
-+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
-+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
-+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
-+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
-+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
-+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
-+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
-+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
-+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
-+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
-+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
-+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
-+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
-+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
-+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
-+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
-+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
-+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
-+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
-+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
-+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
-+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
-+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
-+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
-+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
-+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
-+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
-+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
-+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
-+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
-+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
-+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
-+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
-+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
-+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
-+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
-+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
-+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
-+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
-+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
-+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
-+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
-+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
-+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
-+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000
-+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
-+#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
-+#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
-+#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
-+#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
-+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
-+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
-+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
-+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
-+#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
-+#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
-+#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
-+#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
-+#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
-+#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
-+#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
-+#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
-+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
-+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
-+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
-+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
-+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
-+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
-+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
-+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
-+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
-+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
-+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
-+#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
-+#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
-+#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
-+#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
-+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
-+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
-+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
-+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
-+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
-+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
-+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
-+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
-+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
-+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
-+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
-+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
-+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
-+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
-+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
-+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
-+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
-+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
-+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff
-+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
-+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
-+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
-+#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
-+#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc
-+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2
-+#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
-+#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
-+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
-+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
-+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
-+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
-+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
-+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
-+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
-+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
-+#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1
-+#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
-+#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x2
-+#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
-+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
-+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
-+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
-+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
-+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
-+#define PERFMON_HI__PERFMON_HI_MASK 0xffff
-+#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
-+#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
-+#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
-+#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
-+#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
-+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
-+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
-+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1
-+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
-+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2
-+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P0PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x1
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P0PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x0
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P1PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x2
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P1PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x1
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P2PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x4
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P2PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x2
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P3PLL_CBUS_ANTIGLITCH_RESETB_MASK 0x8
-+#define DCCG_CBUS_ANTIGLITCH_RESETB__P3PLL_CBUS_ANTIGLITCH_RESETB__SHIFT 0x3
-+#define DCCG_CBUS_SPARE__P0PLL_CBUS_SPARE_MASK 0xff
-+#define DCCG_CBUS_SPARE__P0PLL_CBUS_SPARE__SHIFT 0x0
-+#define DCCG_CBUS_SPARE__P1PLL_CBUS_SPARE_MASK 0xff00
-+#define DCCG_CBUS_SPARE__P1PLL_CBUS_SPARE__SHIFT 0x8
-+#define DCCG_CBUS_SPARE__P2PLL_CBUS_SPARE_MASK 0xff0000
-+#define DCCG_CBUS_SPARE__P2PLL_CBUS_SPARE__SHIFT 0x10
-+#define DCCG_CBUS_SPARE__P3PLL_CBUS_SPARE_MASK 0xff000000
-+#define DCCG_CBUS_SPARE__P3PLL_CBUS_SPARE__SHIFT 0x18
-+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf
-+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
-+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
-+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
-+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100
-+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
-+#define DCE_VERSION__MAJOR_VERSION_MASK 0xff
-+#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
-+#define DCE_VERSION__MINOR_VERSION_MASK 0xff00
-+#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
-+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff
-+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
-+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1
-+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
-+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff
-+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
-+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
-+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
-+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
-+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
-+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
-+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
-+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
-+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
-+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
-+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
-+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
-+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
-+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
-+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
-+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x30
-+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4
-+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
-+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
-+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
-+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
-+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
-+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
-+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
-+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
-+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
-+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
-+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
-+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
-+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
-+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
-+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
-+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
-+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
-+#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
-+#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
-+#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
-+#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
-+#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
-+#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
-+#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
-+#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
-+#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
-+#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
-+#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
-+#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
-+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40
-+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
-+#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI_MASK 0x80
-+#define SMU_CONTROL__DISPLAY_V1_FORCE_VBI__SHIFT 0x7
-+#define SMU_CONTROL__MCIF_WB_FORCE_VBI_MASK 0x100
-+#define SMU_CONTROL__MCIF_WB_FORCE_VBI__SHIFT 0x8
-+#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
-+#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
-+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
-+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
-+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
-+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
-+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
-+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
-+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
-+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
-+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
-+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
-+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
-+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
-+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
-+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
-+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
-+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
-+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
-+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
-+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
-+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
-+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
-+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
-+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
-+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
-+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
-+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
-+#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80
-+#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7
-+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100
-+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
-+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
-+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
-+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
-+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
-+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
-+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
-+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
-+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
-+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
-+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
-+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000
-+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
-+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000
-+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
-+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000
-+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
-+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000
-+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
-+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000
-+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
-+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000
-+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x1
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x2
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x4
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x8
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x10
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x20
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x40
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x100
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x10000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x20000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x40000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x80000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x100000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x200000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x400000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x1000000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x2000000
-+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19
-+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
-+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
-+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
-+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
-+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
-+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
-+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
-+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
-+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
-+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
-+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf
-+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
-+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0
-+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
-+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf
-+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
-+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0
-+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
-+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0xf
-+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
-+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0xff0
-+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
-+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
-+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
-+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
-+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
-+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
-+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x1
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x30
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x100
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200
-+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x1
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x30
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x100
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200
-+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x1
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x30
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x100
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200
-+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x1
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x30
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x100
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200
-+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x1
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x30
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x100
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200
-+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x1
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x30
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x100
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x200
-+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
-+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
-+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
-+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
-+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
-+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
-+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
-+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
-+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
-+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
-+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
-+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
-+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
-+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
-+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
-+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
-+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
-+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
-+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
-+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
-+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
-+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1
-+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x4
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x8
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
-+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x10
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x20
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x40
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x80
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x100
-+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
-+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
-+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
-+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN_MASK 0x800
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_HALF_RATE_EN__SHIFT 0xb
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
-+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
-+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
-+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
-+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
-+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
-+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7
-+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE_MASK 0x10
-+#define CRTC0_PHYPLL_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
-+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
-+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
-+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN_MASK 0x800
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_HALF_RATE_EN__SHIFT 0xb
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
-+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
-+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
-+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
-+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
-+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
-+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7
-+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE_MASK 0x10
-+#define CRTC1_PHYPLL_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
-+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
-+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
-+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN_MASK 0x800
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_HALF_RATE_EN__SHIFT 0xb
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
-+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
-+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
-+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
-+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
-+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
-+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7
-+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE_MASK 0x10
-+#define CRTC2_PHYPLL_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
-+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
-+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
-+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN_MASK 0x800
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_HALF_RATE_EN__SHIFT 0xb
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
-+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
-+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
-+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
-+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
-+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
-+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7
-+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE_MASK 0x10
-+#define CRTC3_PHYPLL_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
-+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
-+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
-+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN_MASK 0x800
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_HALF_RATE_EN__SHIFT 0xb
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
-+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
-+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
-+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
-+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
-+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
-+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7
-+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE_MASK 0x10
-+#define CRTC4_PHYPLL_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
-+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
-+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
-+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN_MASK 0x800
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_HALF_RATE_EN__SHIFT 0xb
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
-+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
-+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
-+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
-+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
-+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
-+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x7
-+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
-+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE_MASK 0x10
-+#define CRTC5_PHYPLL_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
-+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
-+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
-+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2
-+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
-+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
-+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
-+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
-+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
-+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
-+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
-+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
-+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
-+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
-+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
-+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
-+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
-+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000
-+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
-+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000
-+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
-+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000
-+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
-+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000
-+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
-+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000
-+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
-+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000
-+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
-+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000
-+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
-+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000
-+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
-+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
-+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
-+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
-+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
-+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
-+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
-+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
-+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
-+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
-+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
-+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
-+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
-+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
-+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
-+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
-+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
-+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
-+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
-+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
-+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
-+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
-+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
-+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
-+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
-+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
-+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
-+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
-+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
-+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
-+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
-+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
-+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
-+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
-+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
-+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
-+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
-+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10
-+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4
-+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700
-+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
-+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
-+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
-+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
-+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
-+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
-+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
-+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
-+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
-+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
-+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
-+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
-+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
-+#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
-+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
-+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
-+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
-+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
-+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
-+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
-+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
-+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
-+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
-+#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff
-+#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
-+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
-+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
-+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
-+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000
-+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17
-+#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000
-+#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18
-+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
-+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
-+#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
-+#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
-+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
-+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
-+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
-+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
-+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
-+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
-+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
-+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
-+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x1f000
-+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
-+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x7e0000
-+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x11
-+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
-+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
-+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
-+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
-+#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE_MASK 0x80000000
-+#define DMIF_CONTROL__DMIF_PSTATE_URGENT_DISABLE__SHIFT 0x1f
-+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f
-+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
-+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00
-+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
-+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
-+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
-+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
-+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
-+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0xf00000
-+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
-+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0xf000000
-+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
-+#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
-+#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
-+#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000
-+#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d
-+#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000
-+#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f
-+#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE_MASK 0xf
-+#define DMIFV_STATUS__DMIFV_MC_SEND_ON_IDLE__SHIFT 0x0
-+#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE_MASK 0xf00
-+#define DMIFV_STATUS__DMIFV_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
-+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
-+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
-+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
-+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
-+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
-+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
-+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
-+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
-+#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf
-+#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
-+#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0
-+#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
-+#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00
-+#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
-+#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000
-+#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
-+#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000
-+#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
-+#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000
-+#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
-+#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000
-+#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
-+#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000
-+#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
-+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1
-+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
-+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0
-+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
-+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
-+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
-+#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
-+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
-+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
-+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
-+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
-+#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
-+#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
-+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
-+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
-+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
-+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
-+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
-+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
-+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
-+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
-+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
-+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
-+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
-+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
-+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
-+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
-+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
-+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
-+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
-+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
-+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
-+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
-+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
-+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
-+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
-+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
-+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
-+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
-+#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x1
-+#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0
-+#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xffffffff
-+#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0
-+#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0xff
-+#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0
-+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0xff00
-+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8
-+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x3f0000
-+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10
-+#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x3
-+#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0
-+#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK 0x30
-+#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT 0x4
-+#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x80
-+#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7
-+#define DVMM_CNTL__DBG_DCE_VMID_MASK 0xf00
-+#define DVMM_CNTL__DBG_DCE_VMID__SHIFT 0x8
-+#define DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK 0x8000
-+#define DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT 0xf
-+#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x20000
-+#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11
-+#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x40000
-+#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12
-+#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xffffffff
-+#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0
-+#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xffffffff
-+#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
-+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
-+#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
-+#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
-+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
-+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
-+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
-+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
-+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
-+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
-+#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
-+#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
-+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
-+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
-+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
-+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
-+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
-+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
-+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
-+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
-+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
-+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
-+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
-+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
-+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
-+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
-+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
-+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
-+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
-+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
-+#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
-+#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
-+#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
-+#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
-+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
-+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
-+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
-+#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x3f0000
-+#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10
-+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
-+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
-+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
-+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
-+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
-+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
-+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
-+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
-+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
-+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff
-+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
-+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xfff00000
-+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xffff
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000
-+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
-+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1
-+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
-+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2
-+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
-+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4
-+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
-+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8
-+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
-+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10
-+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
-+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20
-+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
-+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40
-+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
-+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80
-+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
-+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100
-+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
-+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200
-+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
-+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400
-+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
-+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
-+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
-+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000
-+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
-+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000
-+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
-+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000
-+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
-+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x8000
-+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf
-+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x3
-+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
-+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10
-+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
-+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20
-+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
-+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40
-+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
-+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3
-+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
-+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc
-+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2
-+#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10
-+#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4
-+#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40
-+#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6
-+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100
-+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
-+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600
-+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
-+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
-+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
-+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000
-+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
-+#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000
-+#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe
-+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000
-+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
-+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000
-+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
-+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000
-+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
-+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000
-+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
-+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM3_PWR_STATE_MASK 0xc0000000
-+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM3_PWR_STATE__SHIFT 0x1e
-+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3
-+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
-+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc
-+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
-+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10
-+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
-+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60
-+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
-+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180
-+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
-+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200
-+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
-+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00
-+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
-+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000
-+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
-+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000
-+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
-+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000
-+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
-+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
-+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
-+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000
-+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
-+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000
-+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
-+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000
-+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
-+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000
-+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE_MASK 0x3
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM0_PWR_STATE__SHIFT 0x0
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE_MASK 0xc
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_LUMA_MEM1_PWR_STATE__SHIFT 0x2
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE_MASK 0x30
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM0_PWR_STATE__SHIFT 0x4
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE_MASK 0xc0
-+#define DCI_MEM_PWR_STATUS3__MCIF_DWB_CHROMA_MEM1_PWR_STATE__SHIFT 0x6
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE_MASK 0x300
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x8
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE_MASK 0xc00
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_LUMA_MEM1_PWR_STATE__SHIFT 0xa
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE_MASK 0x3000
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0xc
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE_MASK 0xc000
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0xe
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE_MASK 0x30000
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x10
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE_MASK 0xc0000
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_LUMA_MEM1_PWR_STATE__SHIFT 0x12
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE_MASK 0x300000
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0x14
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE_MASK 0xc00000
-+#define DCI_MEM_PWR_STATUS3__MCIF_CWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0x16
-+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
-+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
-+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
-+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
-+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
-+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
-+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
-+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
-+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
-+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
-+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
-+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS_MASK 0x400
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_L_GATE_DIS__SHIFT 0xa
-+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
-+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS_MASK 0x1000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV1_C_GATE_DIS__SHIFT 0xc
-+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
-+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
-+#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000
-+#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
-+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
-+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
-+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
-+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
-+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
-+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
-+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS_MASK 0x2000000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_L_GATE_DIS__SHIFT 0x19
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS_MASK 0x4000000
-+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV0_C_GATE_DIS__SHIFT 0x1a
-+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
-+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
-+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x1
-+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0
-+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x2
-+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1
-+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x4
-+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2
-+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x8
-+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3
-+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x10
-+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4
-+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000
-+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f
-+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3
-+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
-+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4
-+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
-+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8
-+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3
-+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10
-+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4
-+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20
-+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5
-+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40
-+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6
-+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80
-+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
-+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100
-+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
-+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600
-+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
-+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
-+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
-+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000
-+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
-+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000
-+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
-+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000
-+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
-+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000
-+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
-+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000
-+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11
-+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000
-+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13
-+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000
-+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
-+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000
-+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000
-+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
-+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000
-+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
-+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000
-+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
-+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3
-+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
-+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4
-+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
-+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18
-+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
-+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20
-+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
-+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40
-+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
-+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80
-+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
-+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300
-+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
-+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400
-+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
-+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800
-+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
-+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000
-+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
-+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000
-+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
-+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000
-+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
-+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000
-+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
-+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000
-+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
-+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000
-+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
-+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000
-+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
-+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000
-+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
-+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000
-+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
-+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000
-+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
-+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000
-+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
-+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000
-+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
-+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000
-+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
-+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000
-+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
-+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000
-+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
-+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3
-+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
-+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4
-+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
-+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18
-+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
-+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20
-+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
-+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40
-+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
-+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80
-+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
-+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300
-+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
-+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400
-+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
-+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800
-+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
-+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000
-+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
-+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000
-+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
-+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000
-+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
-+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000
-+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
-+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000
-+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
-+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000
-+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
-+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000
-+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
-+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000
-+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
-+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000
-+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
-+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000
-+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
-+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000
-+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
-+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM_MASK 0x1
-+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_LUMA_MEM_EN_NUM__SHIFT 0x0
-+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM_MASK 0x2
-+#define DCI_MEM_PWR_CNTL4__MCIF_DWB_CHROMA_MEM_EN_NUM__SHIFT 0x1
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM_MASK 0x4
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_LUMA_MEM_EN_NUM__SHIFT 0x2
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM_MASK 0x8
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB0_CHROMA_MEM_EN_NUM__SHIFT 0x3
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM_MASK 0x10
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_LUMA_MEM_EN_NUM__SHIFT 0x4
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM_MASK 0x20
-+#define DCI_MEM_PWR_CNTL4__MCIF_CWB1_CHROMA_MEM_EN_NUM__SHIFT 0x5
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x3
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x4
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x18
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x20
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0xc0
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x100
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x600
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x800
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x3000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x4000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x18000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x20000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0xc0000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x100000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x600000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x800000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x3000000
-+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x3
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0xc
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x30
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0xc0
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x300
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0xc00
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x3000
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0xc000
-+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe
-+#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
-+#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
-+#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
-+#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
-+#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
-+#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
-+#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
-+#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
-+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
-+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
-+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
-+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
-+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
-+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
-+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
-+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
-+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
-+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
-+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
-+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
-+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400
-+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
-+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800
-+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
-+#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET_MASK 0x1000
-+#define DCI_SOFT_RESET__DCFEV1_L_SOFT_RESET__SHIFT 0xc
-+#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET_MASK 0x2000
-+#define DCI_SOFT_RESET__DCFEV1_C_SOFT_RESET__SHIFT 0xd
-+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x4000
-+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xe
-+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000
-+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
-+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000
-+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
-+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000
-+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
-+#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET_MASK 0x80000
-+#define DCI_SOFT_RESET__MCIF_WB_SOFT_RESET__SHIFT 0x13
-+#define DCI_MISC__MCIF_WB_URG_OVRD_MASK 0x1
-+#define DCI_MISC__MCIF_WB_URG_OVRD__SHIFT 0x0
-+#define DCI_MISC__MCIF_WB_URG_LVL_MASK 0x1e
-+#define DCI_MISC__MCIF_WB_URG_LVL__SHIFT 0x1
-+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
-+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1
-+#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0
-+#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0
-+#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4
-+#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00
-+#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8
-+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
-+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
-+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
-+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
-+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
-+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
-+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
-+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
-+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
-+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
-+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
-+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
-+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
-+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
-+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
-+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
-+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
-+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
-+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
-+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
-+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
-+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
-+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
-+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
-+#define DC_GENERICA__GENERICA_EN_MASK 0x1
-+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
-+#define DC_GENERICA__GENERICA_SEL_MASK 0xf80
-+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
-+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000
-+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
-+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000
-+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
-+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000
-+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
-+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000
-+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
-+#define DC_GENERICB__GENERICB_EN_MASK 0x1
-+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
-+#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
-+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
-+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000
-+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
-+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000
-+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
-+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000
-+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
-+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000
-+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
-+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
-+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
-+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
-+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
-+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
-+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
-+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
-+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
-+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
-+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
-+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
-+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
-+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
-+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
-+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
-+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
-+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000
-+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
-+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
-+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
-+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000
-+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000
-+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
-+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
-+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
-+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
-+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
-+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
-+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
-+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
-+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
-+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
-+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
-+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
-+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
-+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
-+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
-+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
-+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
-+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
-+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
-+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
-+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
-+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
-+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
-+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
-+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
-+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
-+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
-+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
-+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
-+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
-+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
-+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
-+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
-+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
-+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
-+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
-+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
-+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
-+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
-+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
-+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
-+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf
-+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
-+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20
-+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
-+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300
-+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
-+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000
-+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_BIASENTST_MASK 0x380000
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_BIASENTST__SHIFT 0x13
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_RESBIASEN_MASK 0x400000
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_RESBIASEN__SHIFT 0x16
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_SPARE_CONTROL_MASK 0x1800000
-+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_SPARE_CONTROL__SHIFT 0x17
-+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
-+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
-+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
-+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
-+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
-+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
-+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
-+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
-+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
-+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
-+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
-+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
-+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
-+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
-+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
-+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
-+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
-+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
-+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
-+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
-+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
-+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
-+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
-+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
-+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
-+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
-+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
-+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
-+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf
-+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
-+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0
-+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
-+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00
-+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
-+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000
-+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
-+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0xf0000
-+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10
-+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
-+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
-+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
-+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
-+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
-+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
-+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
-+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
-+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000
-+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11
-+#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
-+#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
-+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
-+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
-+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
-+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
-+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
-+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
-+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
-+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
-+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
-+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
-+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
-+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
-+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
-+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
-+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
-+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
-+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
-+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
-+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
-+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
-+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
-+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
-+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
-+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
-+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
-+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
-+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
-+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
-+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
-+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
-+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
-+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
-+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
-+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
-+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
-+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
-+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
-+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
-+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
-+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
-+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
-+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
-+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
-+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
-+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
-+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
-+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
-+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
-+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
-+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
-+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
-+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP_MASK 0x3800000
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP__SHIFT 0x17
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP_MASK 0x1c000000
-+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP__SHIFT 0x1a
-+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
-+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
-+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
-+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f
-+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
-+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20
-+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
-+#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
-+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
-+#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1
-+#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0
-+#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10
-+#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4
-+#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300
-+#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8
-+#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000
-+#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc
-+#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1
-+#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
-+#define DCIO_DEBUG_CONFIG__DCIO_DBG_SEL_MASK 0xf00
-+#define DCIO_DEBUG_CONFIG__DCIO_DBG_SEL__SHIFT 0x8
-+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1
-+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
-+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2
-+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
-+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4
-+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
-+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8
-+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
-+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10
-+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
-+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20
-+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
-+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40
-+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
-+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80
-+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
-+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100
-+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
-+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200
-+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
-+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400
-+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
-+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800
-+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
-+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000
-+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
-+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000
-+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
-+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000
-+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
-+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000
-+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
-+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000
-+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
-+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x4000000
-+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a
-+#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000
-+#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c
-+#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000
-+#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d
-+#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000
-+#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e
-+#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000
-+#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f
-+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3
-+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
-+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc
-+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
-+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30
-+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
-+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0
-+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x1
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x2
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x4
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x8
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x10
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x20
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x40
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x80
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x100
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x200
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x400
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x800
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x1000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x2000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x4000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x8000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x10000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x20000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x40000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x80000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x100000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE_MASK 0x1000000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_TYPE__SHIFT 0x18
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK_MASK 0x2000000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_MASK__SHIFT 0x19
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR_MASK 0x4000000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPA_INT_OCCUR__SHIFT 0x1a
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE_MASK 0x8000000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_TYPE__SHIFT 0x1b
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK_MASK 0x10000000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_MASK__SHIFT 0x1c
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR_MASK 0x20000000
-+#define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXLPB_INT_OCCUR__SHIFT 0x1d
-+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x1
-+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0
-+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x2
-+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1
-+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x4
-+#define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2
-+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10
-+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0xffff
-+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0
-+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xffff0000
-+#define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10
-+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
-+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000
-+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000
-+#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
-+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
-+#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
-+#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
-+#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
-+#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
-+#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
-+#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
-+#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
-+#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
-+#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
-+#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
-+#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
-+#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
-+#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
-+#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
-+#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
-+#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
-+#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
-+#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
-+#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
-+#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
-+#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
-+#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
-+#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
-+#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
-+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
-+#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
-+#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff
-+#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0
-+#define DCIO_DEBUG17__DCIO_DEBUG17_MASK 0xffffffff
-+#define DCIO_DEBUG17__DCIO_DEBUG17__SHIFT 0x0
-+#define DCIO_DEBUG18__DCIO_DEBUG18_MASK 0xffffffff
-+#define DCIO_DEBUG18__DCIO_DEBUG18__SHIFT 0x0
-+#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK 0xffffffff
-+#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT 0x0
-+#define DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK 0xffffffff
-+#define DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT 0x0
-+#define DCIO_DEBUG1C__DCIO_DEBUG_UNIPHYA_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG1C__DCIO_DEBUG_UNIPHYA_CFG__SHIFT 0x0
-+#define DCIO_DEBUG1D__DCIO_DEBUG_UNIPHYB_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG1D__DCIO_DEBUG_UNIPHYB_CFG__SHIFT 0x0
-+#define DCIO_DEBUG1E__DCIO_DEBUG_UNIPHYC_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG1E__DCIO_DEBUG_UNIPHYC_CFG__SHIFT 0x0
-+#define DCIO_DEBUG1F__DCIO_DEBUG_UNIPHYD_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG1F__DCIO_DEBUG_UNIPHYD_CFG__SHIFT 0x0
-+#define DCIO_DEBUG20__DCIO_DEBUG_UNIPHYE_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG20__DCIO_DEBUG_UNIPHYE_CFG__SHIFT 0x0
-+#define DCIO_DEBUG21__DCIO_DEBUG_UNIPHYF_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG21__DCIO_DEBUG_UNIPHYF_CFG__SHIFT 0x0
-+#define DCIO_DEBUG22__DCIO_DEBUG_UNIPHYG_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG22__DCIO_DEBUG_UNIPHYG_CFG__SHIFT 0x0
-+#define DCIO_DEBUG23__DCIO_DEBUG_UNIPHYLPA_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG23__DCIO_DEBUG_UNIPHYLPA_CFG__SHIFT 0x0
-+#define DCIO_DEBUG24__DCIO_DEBUG_UNIPHYLPB_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG24__DCIO_DEBUG_UNIPHYLPB_CFG__SHIFT 0x0
-+#define DCIO_DEBUG25__DCIO_DEBUG_DCRXPHY_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG25__DCIO_DEBUG_DCRXPHY_CFG__SHIFT 0x0
-+#define DCIO_DEBUG26__DCIO_DEBUG_DPHY_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG26__DCIO_DEBUG_DPHY_CFG__SHIFT 0x0
-+#define DCIO_DEBUG27__DCIO_DEBUG_DACA_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG27__DCIO_DEBUG_DACA_CFG__SHIFT 0x0
-+#define DCIO_DEBUG28__DCIO_DEBUG_ZCAL_CFG_MASK 0xffffffff
-+#define DCIO_DEBUG28__DCIO_DEBUG_ZCAL_CFG__SHIFT 0x0
-+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
-+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV1_MASK 0x8
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV1__SHIFT 0x3
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV1_MASK 0x80
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV1__SHIFT 0x7
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV1_MASK 0x800
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV1__SHIFT 0xb
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV1_MASK 0x8000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV1__SHIFT 0xf
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV1_MASK 0x80000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV1__SHIFT 0x13
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV1_MASK 0x800000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV1__SHIFT 0x17
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV1_MASK 0x8000000
-+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV1__SHIFT 0x1b
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
-+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
-+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
-+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
-+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
-+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
-+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
-+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
-+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
-+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
-+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
-+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
-+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
-+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
-+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
-+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
-+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
-+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
-+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
-+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
-+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
-+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
-+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
-+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
-+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
-+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
-+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
-+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
-+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
-+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
-+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
-+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
-+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
-+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
-+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
-+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
-+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
-+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
-+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
-+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
-+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
-+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
-+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
-+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
-+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
-+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
-+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
-+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
-+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
-+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
-+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
-+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
-+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
-+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
-+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
-+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
-+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
-+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
-+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
-+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
-+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
-+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
-+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
-+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
-+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
-+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
-+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
-+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
-+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
-+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
-+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
-+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
-+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
-+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
-+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
-+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV1_MASK 0x80
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV1__SHIFT 0x7
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV1_MASK 0x8000
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV1__SHIFT 0xf
-+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
-+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
-+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
-+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
-+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
-+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
-+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
-+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
-+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
-+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
-+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RXSEL_MASK 0x30000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RXSEL__SHIFT 0x10
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPARE_MASK 0xc0000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPARE__SHIFT 0x12
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_BIASCRTEN_MASK 0x100000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_BIASCRTEN__SHIFT 0x14
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL0P9_MASK 0x200000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL0P9__SHIFT 0x15
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL1P1_MASK 0x400000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_CSEL1P1__SHIFT 0x16
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_COMPSEL_MASK 0x800000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_COMPSEL__SHIFT 0x17
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL0P9_MASK 0x1000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL0P9__SHIFT 0x18
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL1P1_MASK 0x2000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RSEL1P1__SHIFT 0x19
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCEN_MASK 0x4000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCEN__SHIFT 0x1a
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL_MASK 0x8000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL__SHIFT 0x1b
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL_MASK 0x30000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL__SHIFT 0x1c
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RESBIASEN_MASK 0x40000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_RESBIASEN__SHIFT 0x1e
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SLEWN_MASK 0x80000000
-+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_PAD_SLEWN__SHIFT 0x1f
-+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
-+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
-+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
-+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV1_MASK 0x80
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV1__SHIFT 0x7
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV1_MASK 0x8000
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV1__SHIFT 0xf
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
-+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
-+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
-+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
-+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
-+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
-+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
-+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
-+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
-+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
-+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
-+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
-+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
-+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV1_MASK 0x10
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV1__SHIFT 0x4
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV1_MASK 0x20
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV1__SHIFT 0x5
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV1_MASK 0x100000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV1__SHIFT 0x14
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV1_MASK 0x800000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV1__SHIFT 0x17
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
-+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
-+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
-+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
-+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
-+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
-+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
-+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
-+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
-+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
-+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
-+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
-+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
-+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
-+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
-+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
-+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
-+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
-+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
-+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
-+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
-+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
-+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
-+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
-+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
-+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV_MASK 0x8
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV__SHIFT 0x3
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV1_MASK 0x20
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV1__SHIFT 0x5
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV1_MASK 0x80
-+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RECV1__SHIFT 0x7
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV1_MASK 0x800
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV1__SHIFT 0xb
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV1_MASK 0x80000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV1__SHIFT 0x13
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV1_MASK 0x800000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV1__SHIFT 0x17
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV1_MASK 0x8000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV1__SHIFT 0x1b
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV1_MASK 0x80000000
-+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV1__SHIFT 0x1f
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
-+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
-+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2
-+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
-+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4
-+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
-+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8
-+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
-+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10
-+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
-+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x20
-+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
-+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40
-+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
-+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80
-+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
-+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x200
-+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
-+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x400
-+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
-+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x20000
-+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
-+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x40000
-+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x100000
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
-+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x200000
-+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
-+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x400000
-+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x1000000
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
-+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x2000000
-+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
-+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x4000000
-+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
-+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
-+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000
-+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
-+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000
-+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
-+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV1_MASK 0x80
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV1__SHIFT 0x7
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV1_MASK 0x8000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV1__SHIFT 0xf
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV1_MASK 0x800000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV1__SHIFT 0x17
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV1_MASK 0x8000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV1__SHIFT 0x1b
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV1_MASK 0x80000000
-+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV1__SHIFT 0x1f
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
-+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
-+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
-+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
-+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
-+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
-+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
-+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
-+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00
-+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
-+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000
-+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
-+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0xf0000
-+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
-+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0xf00000
-+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
-+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
-+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
-+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
-+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
-+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
-+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
-+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
-+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
-+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
-+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
-+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
-+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
-+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
-+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
-+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
-+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
-+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
-+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8
-+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
-+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10
-+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
-+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20
-+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
-+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40
-+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
-+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80
-+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
-+#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
-+#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
-+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000
-+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
-+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
-+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
-+#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x30000
-+#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
-+#define PHY_AUX_CNTL__AUX_PAD_RESBIASEN_MASK 0x40000
-+#define PHY_AUX_CNTL__AUX_PAD_RESBIASEN__SHIFT 0x12
-+#define PHY_AUX_CNTL__AUX_PAD_COMPSEL_MASK 0x80000
-+#define PHY_AUX_CNTL__AUX_PAD_COMPSEL__SHIFT 0x13
-+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
-+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
-+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
-+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_DATA_PD_EN_MASK 0x4
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_DATA_PD_EN__SHIFT 0x2
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RXSEL_MASK 0x30000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RXSEL__SHIFT 0x10
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPARE_MASK 0xc0000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPARE__SHIFT 0x12
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_BIASCRTEN_MASK 0x100000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_BIASCRTEN__SHIFT 0x14
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL0P9_MASK 0x200000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL0P9__SHIFT 0x15
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL1P1_MASK 0x400000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_CSEL1P1__SHIFT 0x16
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_COMPSEL_MASK 0x800000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_COMPSEL__SHIFT 0x17
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL0P9_MASK 0x1000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL0P9__SHIFT 0x18
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL1P1_MASK 0x2000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RSEL1P1__SHIFT 0x19
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCEN_MASK 0x4000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCEN__SHIFT 0x1a
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCSEL_MASK 0x8000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SPIKERCSEL__SHIFT 0x1b
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_FALLSLEWSEL_MASK 0x30000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_FALLSLEWSEL__SHIFT 0x1c
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RESBIASEN_MASK 0x40000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_RESBIASEN__SHIFT 0x1e
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SLEWN_MASK 0x80000000
-+#define DC_GPIO_I2CPAD_EN__DC_GPIO_I2C_PAD_SLEWN__SHIFT 0x1f
-+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
-+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
-+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
-+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
-+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
-+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
-+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
-+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
-+#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
-+#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
-+#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
-+#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
-+#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
-+#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
-+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
-+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
-+#define DC_GPIO_RECEIVER_EN0__VIPPAD_SCL_RECEN_MASK 0x1
-+#define DC_GPIO_RECEIVER_EN0__VIPPAD_SCL_RECEN__SHIFT 0x0
-+#define DC_GPIO_RECEIVER_EN0__VIPPAD_SDA_RECEN_MASK 0x2
-+#define DC_GPIO_RECEIVER_EN0__VIPPAD_SDA_RECEN__SHIFT 0x1
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_RX_HPD_RECEN_MASK 0x10000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_RX_HPD_RECEN__SHIFT 0x10
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HPD1_RECEN_MASK 0x20000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HPD1_RECEN__SHIFT 0x11
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_VSYNC_RECEN_MASK 0x40000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_VSYNC_RECEN__SHIFT 0x12
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_CLK_RECEN_MASK 0x80000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENLK_CLK_RECEN__SHIFT 0x13
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_VSYNCA_RECEN_MASK 0x100000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_VSYNCA_RECEN__SHIFT 0x14
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HSYNCA_RECEN_MASK 0x200000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_HSYNCA_RECEN__SHIFT 0x15
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICG_RECEN_MASK 0x400000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICG_RECEN__SHIFT 0x16
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICF_RECEN_MASK 0x800000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICF_RECEN__SHIFT 0x17
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICE_RECEN_MASK 0x1000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICE_RECEN__SHIFT 0x18
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICD_RECEN_MASK 0x2000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICD_RECEN__SHIFT 0x19
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICC_RECEN_MASK 0x4000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICC_RECEN__SHIFT 0x1a
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICB_RECEN_MASK 0x8000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICB_RECEN__SHIFT 0x1b
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICA_RECEN_MASK 0x10000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_GENERICA_RECEN__SHIFT 0x1c
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_BLON_RECEN_MASK 0x20000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_BLON_RECEN__SHIFT 0x1d
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DIGON_RECEN_MASK 0x40000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DIGON_RECEN__SHIFT 0x1e
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DDC2DATA_RECEN_MASK 0x80000000
-+#define DC_GPIO_RECEIVER_EN0__DC_GPIO_DDC2DATA_RECEN__SHIFT 0x1f
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC2CLK_RECEN_MASK 0x1
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC2CLK_RECEN__SHIFT 0x0
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1DATA_RECEN_MASK 0x2
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1DATA_RECEN__SHIFT 0x1
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1CLK_RECEN_MASK 0x4
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC1CLK_RECEN__SHIFT 0x2
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3DATA_RECEN_MASK 0x8
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3DATA_RECEN__SHIFT 0x3
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3CLK_RECEN_MASK 0x10
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC3CLK_RECEN__SHIFT 0x4
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4DATA_RECEN_MASK 0x20
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4DATA_RECEN__SHIFT 0x5
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4CLK_RECEN_MASK 0x40
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC4CLK_RECEN__SHIFT 0x6
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5DATA_RECEN_MASK 0x80
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5DATA_RECEN__SHIFT 0x7
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5CLK_RECEN_MASK 0x100
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC5CLK_RECEN__SHIFT 0x8
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6DATA_RECEN_MASK 0x200
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6DATA_RECEN__SHIFT 0x9
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6CLK_RECEN_MASK 0x400
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_DDC6CLK_RECEN__SHIFT 0xa
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD2_RECEN_MASK 0x800
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD2_RECEN__SHIFT 0xb
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD3_RECEN_MASK 0x1000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD3_RECEN__SHIFT 0xc
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD4_RECEN_MASK 0x2000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD4_RECEN__SHIFT 0xd
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD5_RECEN_MASK 0x4000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD5_RECEN__SHIFT 0xe
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD6_RECEN_MASK 0x8000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_HPD6_RECEN__SHIFT 0xf
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_ENA_BL_RECEN_MASK 0x10000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_ENA_BL_RECEN__SHIFT 0x10
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_A_RECEN_MASK 0x20000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_A_RECEN__SHIFT 0x11
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_B_RECEN_MASK 0x40000
-+#define DC_GPIO_RECEIVER_EN1__DC_GPIO_SWAPLOCK_B_RECEN__SHIFT 0x12
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000
-+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000
-+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000
-+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x2000
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x4000
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x8000
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x10000
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x20000
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x40000
-+#define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000
-+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x700
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x3800
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x7000000
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000
-+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b
-+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x1
-+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0
-+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x2
-+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1
-+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x4
-+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x8
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x10
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x20
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x40
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x80
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x100
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x200
-+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x3
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0xc
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x30
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0xc0
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x300
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0xc00
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x10000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x20000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x40000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x80000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x100000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x200000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x1000000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x2000000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x4000000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x8000000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000
-+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_0P9_MASK 0x1
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_0P9__SHIFT 0x0
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_0P9_MASK 0x2
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_0P9__SHIFT 0x1
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_0P9_MASK 0x4
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_0P9__SHIFT 0x2
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_0P9_MASK 0x8
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_0P9__SHIFT 0x3
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_0P9_MASK 0x10
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_0P9__SHIFT 0x4
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_0P9_MASK 0x20
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_0P9__SHIFT 0x5
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_1P1_MASK 0x100
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_CSEL_1P1__SHIFT 0x8
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_1P1_MASK 0x200
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_CSEL_1P1__SHIFT 0x9
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_1P1_MASK 0x400
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_CSEL_1P1__SHIFT 0xa
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_1P1_MASK 0x800
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_CSEL_1P1__SHIFT 0xb
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_1P1_MASK 0x1000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_CSEL_1P1__SHIFT 0xc
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_1P1_MASK 0x2000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_CSEL_1P1__SHIFT 0xd
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_0P9_MASK 0x10000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_0P9__SHIFT 0x10
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_0P9_MASK 0x20000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_0P9__SHIFT 0x11
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_0P9_MASK 0x40000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_0P9__SHIFT 0x12
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_0P9_MASK 0x80000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_0P9__SHIFT 0x13
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_0P9_MASK 0x100000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_0P9__SHIFT 0x14
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_0P9_MASK 0x200000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_0P9__SHIFT 0x15
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_1P1_MASK 0x1000000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_RSEL_1P1__SHIFT 0x18
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_1P1_MASK 0x2000000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_RSEL_1P1__SHIFT 0x19
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_1P1_MASK 0x4000000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_RSEL_1P1__SHIFT 0x1a
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_1P1_MASK 0x8000000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_RSEL_1P1__SHIFT 0x1b
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_1P1_MASK 0x10000000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_RSEL_1P1__SHIFT 0x1c
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_1P1_MASK 0x20000000
-+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_RSEL_1P1__SHIFT 0x1d
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX1_BIASCRTEN_MASK 0x1
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX1_BIASCRTEN__SHIFT 0x0
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX2_BIASCRTEN_MASK 0x2
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX2_BIASCRTEN__SHIFT 0x1
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX3_BIASCRTEN_MASK 0x4
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX3_BIASCRTEN__SHIFT 0x2
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX4_BIASCRTEN_MASK 0x8
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX4_BIASCRTEN__SHIFT 0x3
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX5_BIASCRTEN_MASK 0x10
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX5_BIASCRTEN__SHIFT 0x4
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX6_BIASCRTEN_MASK 0x20
-+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_AUX6_BIASCRTEN__SHIFT 0x5
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX1_SPARE_MASK 0xc0
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX1_SPARE__SHIFT 0x6
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX2_SPARE_MASK 0x300
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX2_SPARE__SHIFT 0x8
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX3_SPARE_MASK 0xc00
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX3_SPARE__SHIFT 0xa
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX4_SPARE_MASK 0x3000
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX4_SPARE__SHIFT 0xc
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX5_SPARE_MASK 0xc000
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX5_SPARE__SHIFT 0xe
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX6_SPARE_MASK 0x30000
-+#define DC_GPIO_AUX_CTRL_2__DC_IO_AUX6_SPARE__SHIFT 0x10
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x3
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0xc
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x30
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCEN_MASK 0x100
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCEN_MASK 0x200
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCEN_MASK 0x400
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x1000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x2000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x4000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_0P9_MASK 0x10000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_0P9__SHIFT 0x10
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_0P9_MASK 0x20000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_0P9__SHIFT 0x11
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_0P9_MASK 0x40000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_0P9__SHIFT 0x12
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_1P1_MASK 0x100000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_CSEL_1P1__SHIFT 0x14
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_1P1_MASK 0x200000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_CSEL_1P1__SHIFT 0x15
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_1P1_MASK 0x400000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_CSEL_1P1__SHIFT 0x16
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_0P9_MASK 0x1000000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_0P9__SHIFT 0x18
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_0P9_MASK 0x2000000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_0P9__SHIFT 0x19
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_0P9_MASK 0x4000000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_0P9__SHIFT 0x1a
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_1P1_MASK 0x10000000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD12_RSEL_1P1__SHIFT 0x1c
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_1P1_MASK 0x20000000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD34_RSEL_1P1__SHIFT 0x1d
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_1P1_MASK 0x40000000
-+#define DC_GPIO_HPD_CTRL_0__DC_GPIO_HPD56_RSEL_1P1__SHIFT 0x1e
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_BIASCRTEN_MASK 0x1
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_BIASCRTEN__SHIFT 0x0
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_BIASCRTEN_MASK 0x2
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_BIASCRTEN__SHIFT 0x1
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_BIASCRTEN_MASK 0x4
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_BIASCRTEN__SHIFT 0x2
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_SLEWN_MASK 0x10
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD12_SLEWN__SHIFT 0x4
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_SLEWN_MASK 0x20
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD34_SLEWN__SHIFT 0x5
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_SLEWN_MASK 0x40
-+#define DC_GPIO_HPD_CTRL_1__DC_GPIO_HPD56_SLEWN__SHIFT 0x6
-+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
-+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
-+#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
-+#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
-+#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x2
-+#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
-+#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
-+#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
-+#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
-+#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
-+#define GRPH_CONTROL__GRPH_Z_MASK 0x30
-+#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
-+#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
-+#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
-+#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
-+#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
-+#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
-+#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
-+#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
-+#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
-+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
-+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
-+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
-+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
-+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
-+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
-+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
-+#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
-+#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
-+#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
-+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
-+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
-+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
-+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
-+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
-+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
-+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
-+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
-+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
-+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
-+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
-+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
-+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
-+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
-+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
-+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
-+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
-+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
-+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
-+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
-+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
-+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
-+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
-+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
-+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
-+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
-+#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
-+#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
-+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
-+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
-+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
-+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
-+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
-+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
-+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
-+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
-+#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
-+#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
-+#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
-+#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
-+#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
-+#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
-+#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
-+#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
-+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x1
-+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
-+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
-+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
-+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
-+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
-+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
-+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
-+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
-+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
-+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
-+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
-+#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
-+#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
-+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
-+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
-+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
-+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
-+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
-+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
-+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
-+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
-+#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2
-+#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
-+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x10
-+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
-+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x20
-+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
-+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
-+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
-+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
-+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
-+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
-+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
-+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
-+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
-+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
-+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
-+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
-+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
-+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
-+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
-+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
-+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
-+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
-+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
-+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
-+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
-+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
-+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
-+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
-+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
-+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
-+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
-+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
-+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
-+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
-+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
-+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
-+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
-+#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0xff
-+#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
-+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
-+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
-+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
-+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
-+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
-+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
-+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
-+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
-+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
-+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
-+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
-+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
-+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
-+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
-+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
-+#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
-+#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
-+#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
-+#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
-+#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
-+#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
-+#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
-+#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
-+#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
-+#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
-+#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
-+#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
-+#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
-+#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
-+#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
-+#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
-+#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
-+#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
-+#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
-+#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
-+#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
-+#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
-+#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
-+#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
-+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
-+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
-+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
-+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
-+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
-+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
-+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
-+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
-+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
-+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
-+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
-+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
-+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
-+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
-+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
-+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
-+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
-+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
-+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
-+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
-+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
-+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
-+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
-+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
-+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
-+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
-+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
-+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
-+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
-+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
-+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
-+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
-+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
-+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
-+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
-+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
-+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
-+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
-+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
-+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
-+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
-+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
-+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
-+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
-+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
-+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
-+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
-+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
-+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
-+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
-+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
-+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
-+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
-+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
-+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
-+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
-+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
-+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
-+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
-+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
-+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
-+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
-+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
-+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
-+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
-+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
-+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
-+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
-+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
-+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
-+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
-+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
-+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
-+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
-+#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
-+#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
-+#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
-+#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
-+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
-+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
-+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
-+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
-+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
-+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
-+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
-+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
-+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
-+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
-+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
-+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
-+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
-+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
-+#define KEY_CONTROL__KEY_MODE_MASK 0x6
-+#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
-+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
-+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
-+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
-+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
-+#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
-+#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
-+#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
-+#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
-+#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
-+#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
-+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
-+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
-+#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
-+#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
-+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
-+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
-+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
-+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
-+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
-+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
-+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
-+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
-+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
-+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
-+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
-+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
-+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
-+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
-+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
-+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
-+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
-+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
-+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
-+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
-+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
-+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
-+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
-+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
-+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
-+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
-+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
-+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
-+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
-+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
-+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
-+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
-+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
-+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
-+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
-+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff
-+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
-+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00
-+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
-+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000
-+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
-+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
-+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
-+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
-+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
-+#define CUR_CONTROL__CURSOR_EN_MASK 0x1
-+#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
-+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
-+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
-+#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
-+#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
-+#define CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION_MASK 0xf000
-+#define CUR_CONTROL__CURSOR_BUSY_START_LINE_POSITION__SHIFT 0xc
-+#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
-+#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
-+#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
-+#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
-+#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
-+#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
-+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
-+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
-+#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
-+#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
-+#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
-+#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
-+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
-+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
-+#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
-+#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
-+#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
-+#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
-+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
-+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
-+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
-+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
-+#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
-+#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
-+#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
-+#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
-+#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
-+#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
-+#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
-+#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
-+#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
-+#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
-+#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
-+#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
-+#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
-+#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
-+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
-+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
-+#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
-+#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
-+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
-+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
-+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
-+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
-+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
-+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
-+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
-+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
-+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
-+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
-+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
-+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
-+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
-+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
-+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
-+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
-+#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000
-+#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
-+#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000
-+#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
-+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
-+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
-+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
-+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
-+#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
-+#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
-+#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
-+#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
-+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
-+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
-+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
-+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
-+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
-+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
-+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
-+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
-+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
-+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
-+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
-+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
-+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
-+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
-+#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
-+#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
-+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
-+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
-+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
-+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
-+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
-+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
-+#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
-+#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
-+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
-+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
-+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
-+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
-+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
-+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
-+#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
-+#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
-+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
-+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
-+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
-+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
-+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
-+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
-+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
-+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
-+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
-+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
-+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
-+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
-+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
-+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
-+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
-+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
-+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
-+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
-+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
-+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
-+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
-+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
-+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
-+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
-+#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
-+#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
-+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
-+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
-+#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1
-+#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
-+#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e
-+#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
-+#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0
-+#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
-+#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00
-+#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
-+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000
-+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
-+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000
-+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
-+#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
-+#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
-+#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
-+#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
-+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
-+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
-+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
-+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
-+#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
-+#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
-+#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
-+#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
-+#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
-+#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
-+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
-+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
-+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
-+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
-+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000
-+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11
-+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000
-+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13
-+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
-+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
-+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
-+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
-+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
-+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
-+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
-+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
-+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0
-+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
-+#define DCP_DEBUG_SG__DCP_DEBUG_SG_MASK 0xffffffff
-+#define DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT 0x0
-+#define DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK 0xffffffff
-+#define DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT 0x0
-+#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK 0xffffffff
-+#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT 0x0
-+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
-+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
-+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
-+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
-+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
-+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
-+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
-+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
-+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
-+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
-+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
-+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
-+#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
-+#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
-+#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
-+#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
-+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
-+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
-+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
-+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
-+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
-+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
-+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
-+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
-+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
-+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
-+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
-+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
-+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
-+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
-+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
-+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
-+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
-+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
-+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
-+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
-+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
-+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
-+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
-+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
-+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
-+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
-+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
-+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
-+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
-+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
-+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
-+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
-+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
-+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
-+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
-+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
-+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
-+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
-+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
-+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
-+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
-+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x1
-+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
-+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x1e
-+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
-+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x200
-+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
-+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0xffff
-+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
-+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xffff0000
-+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
-+#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
-+#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
-+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
-+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
-+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
-+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
-+#define DIG_FE_CNTL__DIG_START_MASK 0x400
-+#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
-+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
-+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
-+#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000
-+#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
-+#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000
-+#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
-+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
-+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
-+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
-+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
-+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
-+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
-+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
-+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
-+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
-+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
-+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
-+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
-+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
-+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
-+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
-+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
-+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
-+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
-+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
-+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
-+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
-+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
-+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
-+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
-+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
-+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
-+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
-+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
-+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
-+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
-+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
-+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
-+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
-+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
-+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
-+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
-+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
-+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
-+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
-+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
-+#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x4000000
-+#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
-+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
-+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
-+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
-+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
-+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
-+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
-+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
-+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
-+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
-+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
-+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
-+#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
-+#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
-+#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8
-+#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
-+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
-+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
-+#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
-+#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
-+#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
-+#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
-+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
-+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
-+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
-+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
-+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
-+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
-+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
-+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
-+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
-+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
-+#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
-+#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
-+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
-+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
-+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
-+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
-+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
-+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
-+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
-+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
-+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
-+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
-+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
-+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
-+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
-+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
-+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
-+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
-+#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
-+#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
-+#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
-+#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
-+#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
-+#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
-+#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
-+#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
-+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
-+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
-+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
-+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
-+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
-+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
-+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
-+#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
-+#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
-+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
-+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
-+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
-+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
-+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
-+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
-+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
-+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0xe000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
-+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0xff
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
-+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
-+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
-+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
-+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
-+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
-+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
-+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
-+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
-+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
-+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
-+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
-+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
-+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
-+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
-+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
-+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
-+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
-+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
-+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
-+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
-+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
-+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
-+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
-+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
-+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
-+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
-+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
-+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
-+#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
-+#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
-+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
-+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
-+#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
-+#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
-+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
-+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
-+#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
-+#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
-+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
-+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
-+#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
-+#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
-+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
-+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
-+#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
-+#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
-+#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
-+#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
-+#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
-+#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
-+#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
-+#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
-+#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
-+#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
-+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
-+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
-+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
-+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
-+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
-+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
-+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
-+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
-+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
-+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
-+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
-+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
-+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
-+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
-+#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
-+#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
-+#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
-+#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
-+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
-+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
-+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
-+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
-+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
-+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
-+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
-+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
-+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
-+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
-+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
-+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
-+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
-+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
-+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
-+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
-+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
-+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
-+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
-+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
-+#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
-+#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
-+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
-+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
-+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
-+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
-+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
-+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
-+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
-+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
-+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
-+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
-+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
-+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
-+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
-+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
-+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
-+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
-+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
-+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
-+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
-+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
-+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
-+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
-+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x1
-+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
-+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x100
-+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
-+#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1
-+#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
-+#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2
-+#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
-+#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4
-+#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
-+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
-+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
-+#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
-+#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
-+#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
-+#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
-+#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
-+#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
-+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
-+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
-+#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
-+#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
-+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
-+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
-+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
-+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
-+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
-+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
-+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
-+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
-+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
-+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
-+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
-+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
-+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
-+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
-+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
-+#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
-+#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
-+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
-+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
-+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
-+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
-+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
-+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
-+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
-+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
-+#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
-+#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
-+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
-+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
-+#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
-+#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
-+#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
-+#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
-+#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
-+#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
-+#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
-+#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
-+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
-+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
-+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
-+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
-+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
-+#define DIG_VERSION__DIG_TYPE_MASK 0x1
-+#define DIG_VERSION__DIG_TYPE__SHIFT 0x0
-+#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
-+#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
-+#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
-+#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
-+#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
-+#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
-+#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
-+#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
-+#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
-+#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
-+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff
-+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff
-+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DMCU_CTRL__RESET_UC_MASK 0x1
-+#define DMCU_CTRL__RESET_UC__SHIFT 0x0
-+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
-+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
-+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
-+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
-+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
-+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
-+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
-+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
-+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x100
-+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
-+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000
-+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
-+#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
-+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
-+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
-+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
-+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
-+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
-+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
-+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
-+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
-+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
-+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
-+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
-+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
-+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
-+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
-+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
-+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
-+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
-+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
-+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
-+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
-+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
-+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
-+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
-+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
-+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
-+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
-+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
-+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
-+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
-+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
-+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
-+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
-+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
-+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
-+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
-+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
-+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
-+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
-+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
-+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
-+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
-+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
-+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
-+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
-+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
-+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
-+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
-+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
-+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
-+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
-+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
-+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
-+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
-+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
-+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
-+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
-+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
-+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
-+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
-+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
-+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
-+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
-+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
-+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
-+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
-+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
-+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
-+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
-+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
-+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
-+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
-+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
-+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
-+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
-+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
-+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
-+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
-+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
-+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
-+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
-+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
-+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
-+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
-+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
-+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
-+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
-+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
-+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
-+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
-+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
-+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
-+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
-+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
-+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
-+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
-+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
-+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
-+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
-+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
-+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
-+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
-+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
-+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
-+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x1
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x0
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED_MASK 0x2
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR_MASK 0x2
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR__SHIFT 0x1
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x4
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x4
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x2
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED_MASK 0x8
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR_MASK 0x8
-+#define DMCU_INTERRUPT_STATUS_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR__SHIFT 0x3
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x10
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR_MASK 0x10
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x4
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED_MASK 0x20
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR_MASK 0x20
-+#define DMCU_INTERRUPT_STATUS_1__DCFEV1_VBLANK_INT_CLEAR__SHIFT 0x5
-+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x2000
-+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd
-+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x2000
-+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
-+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCFEV1_VBLANK_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
-+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
-+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
-+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
-+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
-+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
-+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
-+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
-+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
-+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
-+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
-+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
-+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
-+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
-+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
-+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
-+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
-+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
-+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
-+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
-+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
-+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
-+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
-+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
-+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
-+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
-+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
-+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
-+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
-+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
-+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
-+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
-+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
-+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER0_INT_CLEAR__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER1_INT_CLEAR__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER2_INT_CLEAR__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_OCCURRED__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER3_INT_CLEAR__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER4_INT_CLEAR__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_OCCURRED__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER5_INT_CLEAR__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER6_INT_CLEAR__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_OCCURRED__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER7_INT_CLEAR__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000
-+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000
-+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
-+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
-+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
-+#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
-+#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
-+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
-+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
-+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
-+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
-+#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
-+#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
-+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
-+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
-+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
-+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_MASK 0x200
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE__SHIFT 0x9
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE_MASK 0x20000
-+#define DP_MSA_COLORIMETRY__DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__SHIFT 0x11
-+#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
-+#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
-+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
-+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
-+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
-+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
-+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
-+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
-+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
-+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
-+#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
-+#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
-+#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
-+#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
-+#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
-+#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
-+#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
-+#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
-+#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
-+#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
-+#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x10
-+#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
-+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
-+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
-+#define DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN_MASK 0x200
-+#define DP_VID_TIMING__DP_VID_M_DOUBLE_VALUE_EN__SHIFT 0x9
-+#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
-+#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
-+#define DP_VID_N__DP_VID_N_MASK 0xffffff
-+#define DP_VID_N__DP_VID_N__SHIFT 0x0
-+#define DP_VID_M__DP_VID_M_MASK 0xffffff
-+#define DP_VID_M__DP_VID_M__SHIFT 0x0
-+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
-+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
-+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
-+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
-+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
-+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
-+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
-+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
-+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
-+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
-+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
-+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
-+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
-+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
-+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
-+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
-+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
-+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
-+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
-+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
-+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
-+#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
-+#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
-+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
-+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
-+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
-+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
-+#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
-+#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
-+#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
-+#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
-+#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
-+#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
-+#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
-+#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
-+#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
-+#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
-+#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
-+#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
-+#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
-+#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
-+#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
-+#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
-+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
-+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
-+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
-+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
-+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
-+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
-+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
-+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
-+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
-+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
-+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
-+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
-+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff
-+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
-+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000
-+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
-+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x10000
-+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
-+#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
-+#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
-+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
-+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
-+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
-+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
-+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
-+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
-+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
-+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
-+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
-+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
-+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
-+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
-+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
-+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
-+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
-+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
-+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
-+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
-+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
-+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
-+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
-+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
-+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
-+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
-+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
-+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
-+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
-+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
-+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
-+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
-+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
-+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
-+#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x7
-+#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
-+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
-+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
-+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0
-+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
-+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff
-+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
-+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000
-+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
-+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
-+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
-+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
-+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
-+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
-+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
-+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
-+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
-+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
-+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
-+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
-+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
-+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
-+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
-+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
-+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
-+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
-+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
-+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
-+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
-+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
-+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
-+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
-+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x10
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x20
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x40
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x80
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xffff0000
-+#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
-+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
-+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
-+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
-+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
-+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
-+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
-+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
-+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
-+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
-+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
-+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
-+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
-+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
-+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
-+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
-+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
-+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
-+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
-+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
-+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
-+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
-+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
-+#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
-+#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
-+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
-+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
-+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
-+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
-+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
-+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
-+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
-+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
-+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
-+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
-+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
-+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
-+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
-+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
-+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
-+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
-+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
-+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
-+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
-+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
-+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
-+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
-+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
-+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
-+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
-+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
-+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
-+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
-+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
-+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
-+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
-+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
-+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
-+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
-+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
-+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
-+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
-+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
-+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
-+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
-+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
-+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
-+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
-+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
-+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
-+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
-+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
-+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
-+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
-+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
-+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
-+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
-+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
-+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
-+#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000
-+#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x7
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x3f00
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x70000
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3f000000
-+#define DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x7
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x3f00
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x70000
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3f000000
-+#define DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x7
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x3f00
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x70000
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3f000000
-+#define DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
-+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
-+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff
-+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0
-+#define AUX_CONTROL__AUX_EN_MASK 0x1
-+#define AUX_CONTROL__AUX_EN__SHIFT 0x0
-+#define AUX_CONTROL__AUX_RESET_MASK 0x10
-+#define AUX_CONTROL__AUX_RESET__SHIFT 0x4
-+#define AUX_CONTROL__AUX_RESET_DONE_MASK 0x20
-+#define AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
-+#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
-+#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
-+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
-+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
-+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
-+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
-+#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
-+#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
-+#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
-+#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
-+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
-+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
-+#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
-+#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
-+#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
-+#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
-+#define AUX_CONTROL__SPARE_0_MASK 0x40000000
-+#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
-+#define AUX_CONTROL__SPARE_1_MASK 0x80000000
-+#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
-+#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
-+#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
-+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
-+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
-+#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
-+#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
-+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
-+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
-+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
-+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
-+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
-+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
-+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
-+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
-+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
-+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
-+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
-+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
-+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
-+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
-+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
-+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
-+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
-+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
-+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
-+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
-+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
-+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
-+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
-+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
-+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
-+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
-+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
-+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
-+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
-+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
-+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
-+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
-+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
-+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
-+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
-+#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
-+#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
-+#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
-+#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
-+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
-+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
-+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
-+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
-+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
-+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
-+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
-+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
-+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
-+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
-+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
-+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
-+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
-+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
-+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
-+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
-+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
-+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
-+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
-+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
-+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
-+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
-+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
-+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
-+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
-+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
-+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
-+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
-+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
-+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
-+#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
-+#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
-+#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
-+#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
-+#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
-+#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
-+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
-+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
-+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
-+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
-+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
-+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
-+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
-+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
-+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
-+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
-+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
-+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
-+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
-+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
-+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
-+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
-+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
-+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
-+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
-+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
-+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
-+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
-+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
-+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
-+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
-+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
-+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
-+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
-+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
-+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
-+#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
-+#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
-+#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
-+#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
-+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
-+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
-+#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
-+#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
-+#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
-+#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
-+#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
-+#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
-+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
-+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
-+#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
-+#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
-+#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
-+#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
-+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
-+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
-+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
-+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
-+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
-+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
-+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
-+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
-+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
-+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
-+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
-+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
-+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
-+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
-+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
-+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
-+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
-+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
-+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
-+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
-+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
-+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
-+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
-+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
-+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
-+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
-+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
-+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
-+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
-+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
-+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
-+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
-+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff
-+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff
-+#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0
-+#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff
-+#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0
-+#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff
-+#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0
-+#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff
-+#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0
-+#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff
-+#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0
-+#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff
-+#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0
-+#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff
-+#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0
-+#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff
-+#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0
-+#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff
-+#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0
-+#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff
-+#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0
-+#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff
-+#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0
-+#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff
-+#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0
-+#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff
-+#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0
-+#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff
-+#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0
-+#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff
-+#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0
-+#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff
-+#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0
-+#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff
-+#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0
-+#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
-+#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
-+#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
-+#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
-+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
-+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
-+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
-+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
-+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
-+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
-+#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
-+#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
-+#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
-+#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
-+#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
-+#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
-+#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
-+#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
-+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
-+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
-+#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
-+#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
-+#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
-+#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
-+#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
-+#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
-+#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
-+#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
-+#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
-+#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
-+#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
-+#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
-+#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
-+#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
-+#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
-+#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
-+#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
-+#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
-+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
-+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
-+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
-+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
-+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
-+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff
-+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0
-+#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
-+#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
-+#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
-+#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
-+#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x100
-+#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8
-+#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN_MASK 0x400
-+#define FBC_CNTL__FBC_DECOMP_CLK_GATE_EN__SHIFT 0xa
-+#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
-+#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
-+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
-+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
-+#define FBC_CNTL__FBC_EN_MASK 0x80000000
-+#define FBC_CNTL__FBC_EN__SHIFT 0x1f
-+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
-+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
-+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
-+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
-+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
-+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
-+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
-+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
-+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
-+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
-+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
-+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
-+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
-+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
-+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
-+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
-+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
-+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
-+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
-+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
-+#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
-+#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
-+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
-+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
-+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
-+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
-+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
-+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
-+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
-+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
-+#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
-+#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
-+#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
-+#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
-+#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
-+#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
-+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
-+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
-+#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
-+#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
-+#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
-+#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
-+#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
-+#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
-+#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
-+#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
-+#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffffff
-+#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
-+#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffffff
-+#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
-+#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffffff
-+#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
-+#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffffff
-+#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
-+#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffffff
-+#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
-+#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffffff
-+#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
-+#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffffff
-+#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
-+#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffffff
-+#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
-+#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffffff
-+#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
-+#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffffff
-+#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
-+#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffffff
-+#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
-+#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffffff
-+#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
-+#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffffff
-+#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
-+#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffffff
-+#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
-+#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffffff
-+#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
-+#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffffff
-+#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
-+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0xfff
-+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
-+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0xfff0000
-+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
-+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0xfff
-+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
-+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0xfff0000
-+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
-+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
-+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
-+#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
-+#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
-+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
-+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
-+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
-+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
-+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
-+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
-+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
-+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
-+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
-+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0xfff
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
-+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
-+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
-+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
-+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
-+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
-+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
-+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
-+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
-+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
-+#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
-+#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
-+#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
-+#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
-+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
-+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
-+#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
-+#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
-+#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
-+#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
-+#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
-+#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
-+#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
-+#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
-+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
-+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
-+#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x2000
-+#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd
-+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
-+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
-+#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
-+#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
-+#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
-+#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
-+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000
-+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
-+#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000
-+#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f
-+#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
-+#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
-+#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN_MASK 0x1
-+#define FBC_ALPHA_CNTL__FBC_ALPHA_COMP_EN__SHIFT 0x0
-+#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF_MASK 0x10
-+#define FBC_ALPHA_CNTL__FBC_FORCE_COPY_TO_COMP_BUF__SHIFT 0x4
-+#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN_MASK 0x100
-+#define FBC_ALPHA_CNTL__FBC_ZERO_ALPHA_CHUNK_SKIP_EN__SHIFT 0x8
-+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL_MASK 0xff
-+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_R_VAL__SHIFT 0x0
-+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL_MASK 0xff000
-+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_G_VAL__SHIFT 0xc
-+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL_MASK 0xff000000
-+#define FBC_ALPHA_RGB_OVERRIDE__FBC_ZERO_ALPHA_B_VAL__SHIFT 0x18
-+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
-+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
-+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
-+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
-+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
-+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
-+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
-+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
-+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
-+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
-+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
-+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
-+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
-+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
-+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
-+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
-+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
-+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
-+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
-+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
-+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
-+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
-+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00
-+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
-+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000
-+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
-+#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x30000
-+#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
-+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0xc0000
-+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
-+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x100000
-+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
-+#define FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x200000
-+#define FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
-+#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
-+#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
-+#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_MASK 0x40000000
-+#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED__SHIFT 0x1e
-+#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR_MASK 0x80000000
-+#define FMT_CONTROL__FMT_420_PIXEL_PHASE_LOCKED_CLEAR__SHIFT 0x1f
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
-+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
-+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
-+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
-+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
-+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
-+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
-+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
-+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
-+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
-+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
-+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
-+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
-+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
-+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
-+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
-+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
-+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
-+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
-+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
-+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
-+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
-+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
-+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
-+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
-+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
-+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
-+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
-+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
-+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
-+#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
-+#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
-+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
-+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
-+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
-+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
-+#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x20
-+#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
-+#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x40
-+#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
-+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100
-+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
-+#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x200
-+#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
-+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
-+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
-+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
-+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
-+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
-+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
-+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
-+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
-+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
-+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
-+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
-+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
-+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
-+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
-+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
-+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
-+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
-+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
-+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
-+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
-+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
-+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
-+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
-+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
-+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
-+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
-+#define FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x1fff
-+#define FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
-+#define FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START_MASK 0xfff
-+#define FMT_420_HBLANK_EARLY_START__FMT_420_HBLANK_EARLY_START__SHIFT 0x0
-+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
-+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
-+#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
-+#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
-+#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
-+#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
-+#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
-+#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
-+#define FMT_DEBUG3__FMT_DEBUG3_MASK 0xffffffff
-+#define FMT_DEBUG3__FMT_DEBUG3__SHIFT 0x0
-+#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
-+#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
-+#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
-+#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
-+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
-+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
-+#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
-+#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
-+#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
-+#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
-+#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
-+#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
-+#define LB_DATA_FORMAT__PREFILL_EN_MASK 0x100
-+#define LB_DATA_FORMAT__PREFILL_EN__SHIFT 0x8
-+#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
-+#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
-+#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
-+#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
-+#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
-+#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
-+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0x1fff
-+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
-+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
-+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
-+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
-+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
-+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0x1fff
-+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
-+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
-+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
-+#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
-+#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
-+#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
-+#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
-+#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
-+#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
-+#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
-+#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
-+#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
-+#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
-+#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
-+#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
-+#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
-+#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
-+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
-+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
-+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
-+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
-+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
-+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
-+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
-+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
-+#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
-+#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
-+#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
-+#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
-+#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
-+#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
-+#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
-+#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
-+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
-+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
-+#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
-+#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
-+#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
-+#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
-+#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
-+#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
-+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
-+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
-+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
-+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
-+#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
-+#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
-+#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
-+#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
-+#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
-+#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
-+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
-+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
-+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
-+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
-+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
-+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
-+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
-+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
-+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
-+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
-+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
-+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
-+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
-+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
-+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
-+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
-+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
-+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
-+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
-+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
-+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
-+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
-+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
-+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
-+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
-+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
-+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
-+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
-+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
-+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
-+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
-+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
-+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
-+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
-+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
-+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
-+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
-+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
-+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
-+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
-+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
-+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
-+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
-+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
-+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
-+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
-+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
-+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
-+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
-+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
-+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
-+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
-+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
-+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
-+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
-+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
-+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
-+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
-+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
-+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
-+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
-+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
-+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
-+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
-+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
-+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
-+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
-+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
-+#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
-+#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
-+#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
-+#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
-+#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
-+#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
-+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
-+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
-+#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
-+#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
-+#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
-+#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
-+#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
-+#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
-+#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
-+#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
-+#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
-+#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
-+#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40
-+#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
-+#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80
-+#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
-+#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000
-+#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
-+#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
-+#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
-+#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
-+#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
-+#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
-+#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
-+#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
-+#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
-+#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
-+#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
-+#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
-+#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
-+#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
-+#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
-+#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff
-+#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
-+#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000
-+#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
-+#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000
-+#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
-+#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff
-+#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
-+#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
-+#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
-+#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
-+#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
-+#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff
-+#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
-+#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
-+#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
-+#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff
-+#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
-+#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff
-+#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
-+#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
-+#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
-+#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
-+#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
-+#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
-+#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
-+#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
-+#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
-+#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10
-+#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
-+#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000
-+#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
-+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
-+#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
-+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
-+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
-+#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
-+#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
-+#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
-+#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
-+#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
-+#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
-+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
-+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
-+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
-+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
-+#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
-+#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
-+#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
-+#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
-+#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
-+#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
-+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
-+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
-+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
-+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
-+#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
-+#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
-+#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
-+#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
-+#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
-+#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
-+#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
-+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
-+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
-+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
-+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
-+#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
-+#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
-+#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
-+#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
-+#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
-+#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
-+#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
-+#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
-+#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
-+#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
-+#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
-+#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
-+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
-+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
-+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
-+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
-+#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
-+#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
-+#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
-+#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
-+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
-+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
-+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
-+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
-+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
-+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
-+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
-+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
-+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
-+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
-+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
-+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
-+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
-+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
-+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
-+#define LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT_MASK 0x2000000
-+#define LBV_BUFFER_STATUS__LB_ENABLE_HIGH_THROUGHPUT__SHIFT 0x19
-+#define LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL_MASK 0x1c000000
-+#define LBV_BUFFER_STATUS__LB_HIGH_THROUGHPUT_CNTL__SHIFT 0x1a
-+#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
-+#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
-+#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff
-+#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0
-+#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff
-+#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0
-+#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff
-+#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0
-+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
-+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
-+#define MVP_CONTROL1__MVP_EN_MASK 0x1
-+#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
-+#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
-+#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
-+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
-+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
-+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
-+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
-+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
-+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
-+#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
-+#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
-+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
-+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
-+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
-+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
-+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
-+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
-+#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
-+#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
-+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
-+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
-+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
-+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
-+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
-+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
-+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
-+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
-+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
-+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
-+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
-+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
-+#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
-+#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
-+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
-+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
-+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
-+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
-+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
-+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
-+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
-+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
-+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
-+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
-+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
-+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
-+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
-+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
-+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
-+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
-+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
-+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
-+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
-+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
-+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
-+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
-+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
-+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
-+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
-+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
-+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
-+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
-+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
-+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
-+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
-+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
-+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
-+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
-+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
-+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
-+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
-+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
-+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
-+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
-+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
-+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
-+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
-+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
-+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
-+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
-+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
-+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
-+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
-+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
-+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
-+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
-+#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
-+#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
-+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
-+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
-+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
-+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
-+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
-+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
-+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
-+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
-+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
-+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
-+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
-+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
-+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
-+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
-+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
-+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
-+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
-+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
-+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
-+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
-+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
-+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
-+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
-+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
-+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
-+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
-+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
-+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
-+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
-+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
-+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
-+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
-+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
-+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
-+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
-+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
-+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
-+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
-+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
-+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
-+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
-+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
-+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
-+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
-+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
-+#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
-+#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
-+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
-+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
-+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
-+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
-+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
-+#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
-+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
-+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
-+#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
-+#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
-+#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
-+#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
-+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
-+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
-+#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
-+#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
-+#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
-+#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
-+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
-+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
-+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
-+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
-+#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
-+#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
-+#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
-+#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
-+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
-+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
-+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
-+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
-+#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
-+#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
-+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
-+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
-+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
-+#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
-+#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
-+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
-+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
-+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
-+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
-+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
-+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
-+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
-+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
-+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
-+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
-+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
-+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
-+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
-+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
-+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
-+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
-+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
-+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
-+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
-+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
-+#define SCL_MODE__SCL_MODE_MASK 0x3
-+#define SCL_MODE__SCL_MODE__SHIFT 0x0
-+#define SCL_MODE__SCL_PSCL_EN_MASK 0x10
-+#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
-+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
-+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
-+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
-+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
-+#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
-+#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
-+#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
-+#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
-+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
-+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
-+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
-+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
-+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
-+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
-+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
-+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
-+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
-+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
-+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
-+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
-+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
-+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
-+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
-+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
-+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
-+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
-+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
-+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
-+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
-+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
-+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
-+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
-+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
-+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
-+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
-+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
-+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
-+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
-+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
-+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
-+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
-+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
-+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
-+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
-+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
-+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
-+#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
-+#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
-+#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
-+#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
-+#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
-+#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
-+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
-+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
-+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
-+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
-+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
-+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
-+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
-+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
-+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
-+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
-+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
-+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
-+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
-+#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
-+#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
-+#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
-+#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
-+#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
-+#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
-+#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
-+#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
-+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
-+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
-+#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
-+#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
-+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
-+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
-+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
-+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
-+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
-+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
-+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
-+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
-+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
-+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
-+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
-+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
-+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
-+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
-+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
-+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
-+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
-+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
-+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
-+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
-+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
-+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
-+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
-+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
-+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
-+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
-+#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
-+#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
-+#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
-+#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
-+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
-+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
-+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3
-+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
-+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00
-+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
-+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000
-+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
-+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
-+#define SCLV_MODE__SCL_MODE_MASK 0x3
-+#define SCLV_MODE__SCL_MODE__SHIFT 0x0
-+#define SCLV_MODE__SCL_MODE_C_MASK 0xc
-+#define SCLV_MODE__SCL_MODE_C__SHIFT 0x2
-+#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10
-+#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
-+#define SCLV_MODE__SCL_PSCL_EN_C_MASK 0x20
-+#define SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
-+#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300
-+#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
-+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
-+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
-+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70
-+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
-+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700
-+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
-+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000
-+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
-+#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
-+#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
-+#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
-+#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
-+#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100
-+#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
-+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
-+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
-+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
-+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
-+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
-+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
-+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
-+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
-+#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
-+#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
-+#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
-+#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
-+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
-+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
-+#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff
-+#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff
-+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000
-+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
-+#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
-+#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
-+#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
-+#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
-+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
-+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
-+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
-+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
-+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
-+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
-+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
-+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
-+#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff
-+#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
-+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff
-+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
-+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000
-+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
-+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff
-+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
-+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000
-+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
-+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
-+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
-+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
-+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
-+#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
-+#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
-+#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
-+#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
-+#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
-+#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
-+#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
-+#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
-+#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
-+#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
-+#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
-+#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
-+#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
-+#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
-+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
-+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
-+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
-+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
-+#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff
-+#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
-+#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000
-+#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
-+#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff
-+#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
-+#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000
-+#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
-+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff
-+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
-+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000
-+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
-+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff
-+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
-+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000
-+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
-+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
-+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
-+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
-+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
-+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
-+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
-+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
-+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
-+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
-+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
-+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
-+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
-+#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
-+#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
-+#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
-+#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
-+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
-+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
-+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
-+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
-+#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
-+#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0xffffff
-+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0xf000000
-+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
-+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0xffffff
-+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
-+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0xf000000
-+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
-+#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
-+#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
-+#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
-+#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
-+#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
-+#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3
-+#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff
-+#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0
-+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
-+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
-+#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1
-+#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
-+#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2
-+#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
-+#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000
-+#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
-+#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
-+#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
-+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3
-+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
-+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x300
-+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
-+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10000
-+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
-+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff
-+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
-+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000
-+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
-+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff
-+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
-+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000
-+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
-+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff
-+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
-+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000
-+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
-+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff
-+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
-+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000
-+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
-+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff
-+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
-+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000
-+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
-+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff
-+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
-+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000
-+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
-+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff
-+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
-+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000
-+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
-+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff
-+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
-+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000
-+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
-+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff
-+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
-+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000
-+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
-+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff
-+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
-+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000
-+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
-+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff
-+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
-+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000
-+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
-+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff
-+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
-+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000
-+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
-+#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3
-+#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
-+#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff
-+#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
-+#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000
-+#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
-+#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff
-+#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
-+#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000
-+#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
-+#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff
-+#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
-+#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000
-+#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
-+#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7
-+#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
-+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff
-+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
-+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000
-+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
-+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff
-+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
-+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000
-+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
-+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff
-+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
-+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000
-+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
-+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff
-+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
-+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000
-+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
-+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff
-+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
-+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000
-+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
-+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff
-+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
-+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000
-+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
-+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff
-+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
-+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000
-+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
-+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff
-+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
-+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000
-+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
-+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff
-+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
-+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000
-+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
-+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff
-+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
-+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000
-+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
-+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff
-+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
-+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000
-+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
-+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff
-+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
-+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000
-+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
-+#define DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x3
-+#define DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
-+#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x100
-+#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
-+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff
-+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
-+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000
-+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
-+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff
-+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
-+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000
-+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
-+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff
-+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
-+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000
-+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
-+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
-+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
-+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000
-+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
-+#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3
-+#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0
-+#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0xff
-+#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0
-+#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff
-+#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0
-+#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7
-+#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff
-+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
-+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
-+#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
-+#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff
-+#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
-+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
-+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff
-+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
-+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
-+#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
-+#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff
-+#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
-+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
-+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
-+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x1
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x2
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x100
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x200
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x10000
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x20000
-+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x1000000
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x2000000
-+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x1
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x2
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x100
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x200
-+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
-+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x1
-+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
-+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x2
-+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
-+#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0xff
-+#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
-+#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0xffff
-+#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
-+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0xffff
-+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
-+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xffff0000
-+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
-+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x3ff
-+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
-+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0xffc00
-+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
-+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3ff00000
-+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
-+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x3
-+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
-+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x4000000
-+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x1e
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x20
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0xc0
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0xf00
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x1000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x6000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x78000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x80000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x300000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x400000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x3800000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x4000000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x8000000
-+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
-+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0xffff
-+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
-+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xffff0000
-+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
-+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0xffff
-+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
-+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xffff0000
-+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
-+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0xffff
-+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
-+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xffff0000
-+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
-+#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1
-+#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0
-+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff
-+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0
-+#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
-+#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
-+#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
-+#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
-+#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
-+#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
-+#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30
-+#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
-+#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0xc0
-+#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
-+#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
-+#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
-+#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x1800
-+#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
-+#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0xe000
-+#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
-+#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
-+#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
-+#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
-+#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
-+#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0xc0000
-+#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
-+#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
-+#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
-+#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
-+#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
-+#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000
-+#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
-+#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
-+#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
-+#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0xc0
-+#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
-+#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x1800
-+#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
-+#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0xe000
-+#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
-+#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0xc0000
-+#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
-+#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000
-+#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
-+#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7
-+#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
-+#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
-+#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
-+#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
-+#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
-+#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
-+#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
-+#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
-+#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
-+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
-+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
-+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
-+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
-+#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff
-+#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
-+#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff
-+#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
-+#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff
-+#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
-+#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff
-+#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
-+#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff
-+#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
-+#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff
-+#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
-+#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff
-+#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
-+#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff
-+#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
-+#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff
-+#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
-+#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff
-+#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
-+#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff
-+#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
-+#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff
-+#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
-+#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff
-+#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
-+#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff
-+#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
-+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
-+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
-+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
-+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
-+#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
-+#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
-+#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
-+#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
-+#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
-+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0xff
-+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
-+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0xff00
-+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
-+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00
-+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
-+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00
-+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
-+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff
-+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
-+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff
-+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
-+#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1
-+#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
-+#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00
-+#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000
-+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
-+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
-+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
-+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
-+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
-+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
-+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
-+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
-+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
-+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
-+#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x1
-+#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
-+#define UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK 0xfffffffc
-+#define UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT 0x2
-+#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1
-+#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
-+#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c
-+#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
-+#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300
-+#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
-+#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff
-+#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
-+#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff
-+#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
-+#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff
-+#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
-+#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0
-+#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
-+#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7
-+#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
-+#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10
-+#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
-+#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100
-+#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
-+#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff
-+#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0
-+#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff
-+#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0
-+#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK 0xffff
-+#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT 0x0
-+#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK 0xffff0000
-+#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT 0x10
-+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff
-+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0
-+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
-+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
-+#define GENMO_WT__VGA_RAM_EN_MASK 0x2
-+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
-+#define GENMO_WT__VGA_CKSEL_MASK 0xc
-+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
-+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
-+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
-+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
-+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
-+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
-+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
-+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
-+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
-+#define GENMO_RD__VGA_RAM_EN_MASK 0x2
-+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
-+#define GENMO_RD__VGA_CKSEL_MASK 0xc
-+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
-+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
-+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
-+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
-+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
-+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
-+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
-+#define GENENB__BLK_IO_BASE_MASK 0xff
-+#define GENENB__BLK_IO_BASE__SHIFT 0x0
-+#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
-+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
-+#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
-+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
-+#define GENS0__SENSE_SWITCH_MASK 0x10
-+#define GENS0__SENSE_SWITCH__SHIFT 0x4
-+#define GENS0__CRT_INTR_MASK 0x80
-+#define GENS0__CRT_INTR__SHIFT 0x7
-+#define GENS1__NO_DISPLAY_MASK 0x1
-+#define GENS1__NO_DISPLAY__SHIFT 0x0
-+#define GENS1__VGA_VSTATUS_MASK 0x8
-+#define GENS1__VGA_VSTATUS__SHIFT 0x3
-+#define GENS1__PIXEL_READ_BACK_MASK 0x30
-+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
-+#define DAC_DATA__DAC_DATA_MASK 0x3f
-+#define DAC_DATA__DAC_DATA__SHIFT 0x0
-+#define DAC_MASK__DAC_MASK_MASK 0xff
-+#define DAC_MASK__DAC_MASK__SHIFT 0x0
-+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
-+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
-+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
-+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
-+#define SEQ8_IDX__SEQ_IDX_MASK 0x7
-+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
-+#define SEQ8_DATA__SEQ_DATA_MASK 0xff
-+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
-+#define SEQ00__SEQ_RST0B_MASK 0x1
-+#define SEQ00__SEQ_RST0B__SHIFT 0x0
-+#define SEQ00__SEQ_RST1B_MASK 0x2
-+#define SEQ00__SEQ_RST1B__SHIFT 0x1
-+#define SEQ01__SEQ_DOT8_MASK 0x1
-+#define SEQ01__SEQ_DOT8__SHIFT 0x0
-+#define SEQ01__SEQ_SHIFT2_MASK 0x4
-+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
-+#define SEQ01__SEQ_PCLKBY2_MASK 0x8
-+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
-+#define SEQ01__SEQ_SHIFT4_MASK 0x10
-+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
-+#define SEQ01__SEQ_MAXBW_MASK 0x20
-+#define SEQ01__SEQ_MAXBW__SHIFT 0x5
-+#define SEQ02__SEQ_MAP0_EN_MASK 0x1
-+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
-+#define SEQ02__SEQ_MAP1_EN_MASK 0x2
-+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
-+#define SEQ02__SEQ_MAP2_EN_MASK 0x4
-+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
-+#define SEQ02__SEQ_MAP3_EN_MASK 0x8
-+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
-+#define SEQ03__SEQ_FONT_B1_MASK 0x1
-+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
-+#define SEQ03__SEQ_FONT_B2_MASK 0x2
-+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
-+#define SEQ03__SEQ_FONT_A1_MASK 0x4
-+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
-+#define SEQ03__SEQ_FONT_A2_MASK 0x8
-+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
-+#define SEQ03__SEQ_FONT_B0_MASK 0x10
-+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
-+#define SEQ03__SEQ_FONT_A0_MASK 0x20
-+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
-+#define SEQ04__SEQ_256K_MASK 0x2
-+#define SEQ04__SEQ_256K__SHIFT 0x1
-+#define SEQ04__SEQ_ODDEVEN_MASK 0x4
-+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
-+#define SEQ04__SEQ_CHAIN_MASK 0x8
-+#define SEQ04__SEQ_CHAIN__SHIFT 0x3
-+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
-+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
-+#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
-+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
-+#define CRT00__H_TOTAL_MASK 0xff
-+#define CRT00__H_TOTAL__SHIFT 0x0
-+#define CRT01__H_DISP_END_MASK 0xff
-+#define CRT01__H_DISP_END__SHIFT 0x0
-+#define CRT02__H_BLANK_START_MASK 0xff
-+#define CRT02__H_BLANK_START__SHIFT 0x0
-+#define CRT03__H_BLANK_END_MASK 0x1f
-+#define CRT03__H_BLANK_END__SHIFT 0x0
-+#define CRT03__H_DE_SKEW_MASK 0x60
-+#define CRT03__H_DE_SKEW__SHIFT 0x5
-+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
-+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
-+#define CRT04__H_SYNC_START_MASK 0xff
-+#define CRT04__H_SYNC_START__SHIFT 0x0
-+#define CRT05__H_SYNC_END_MASK 0x1f
-+#define CRT05__H_SYNC_END__SHIFT 0x0
-+#define CRT05__H_SYNC_SKEW_MASK 0x60
-+#define CRT05__H_SYNC_SKEW__SHIFT 0x5
-+#define CRT05__H_BLANK_END_B5_MASK 0x80
-+#define CRT05__H_BLANK_END_B5__SHIFT 0x7
-+#define CRT06__V_TOTAL_MASK 0xff
-+#define CRT06__V_TOTAL__SHIFT 0x0
-+#define CRT07__V_TOTAL_B8_MASK 0x1
-+#define CRT07__V_TOTAL_B8__SHIFT 0x0
-+#define CRT07__V_DISP_END_B8_MASK 0x2
-+#define CRT07__V_DISP_END_B8__SHIFT 0x1
-+#define CRT07__V_SYNC_START_B8_MASK 0x4
-+#define CRT07__V_SYNC_START_B8__SHIFT 0x2
-+#define CRT07__V_BLANK_START_B8_MASK 0x8
-+#define CRT07__V_BLANK_START_B8__SHIFT 0x3
-+#define CRT07__LINE_CMP_B8_MASK 0x10
-+#define CRT07__LINE_CMP_B8__SHIFT 0x4
-+#define CRT07__V_TOTAL_B9_MASK 0x20
-+#define CRT07__V_TOTAL_B9__SHIFT 0x5
-+#define CRT07__V_DISP_END_B9_MASK 0x40
-+#define CRT07__V_DISP_END_B9__SHIFT 0x6
-+#define CRT07__V_SYNC_START_B9_MASK 0x80
-+#define CRT07__V_SYNC_START_B9__SHIFT 0x7
-+#define CRT08__ROW_SCAN_START_MASK 0x1f
-+#define CRT08__ROW_SCAN_START__SHIFT 0x0
-+#define CRT08__BYTE_PAN_MASK 0x60
-+#define CRT08__BYTE_PAN__SHIFT 0x5
-+#define CRT09__MAX_ROW_SCAN_MASK 0x1f
-+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
-+#define CRT09__V_BLANK_START_B9_MASK 0x20
-+#define CRT09__V_BLANK_START_B9__SHIFT 0x5
-+#define CRT09__LINE_CMP_B9_MASK 0x40
-+#define CRT09__LINE_CMP_B9__SHIFT 0x6
-+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
-+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
-+#define CRT0A__CURSOR_START_MASK 0x1f
-+#define CRT0A__CURSOR_START__SHIFT 0x0
-+#define CRT0A__CURSOR_DISABLE_MASK 0x20
-+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
-+#define CRT0B__CURSOR_END_MASK 0x1f
-+#define CRT0B__CURSOR_END__SHIFT 0x0
-+#define CRT0B__CURSOR_SKEW_MASK 0x60
-+#define CRT0B__CURSOR_SKEW__SHIFT 0x5
-+#define CRT0C__DISP_START_MASK 0xff
-+#define CRT0C__DISP_START__SHIFT 0x0
-+#define CRT0D__DISP_START_MASK 0xff
-+#define CRT0D__DISP_START__SHIFT 0x0
-+#define CRT0E__CURSOR_LOC_HI_MASK 0xff
-+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
-+#define CRT0F__CURSOR_LOC_LO_MASK 0xff
-+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
-+#define CRT10__V_SYNC_START_MASK 0xff
-+#define CRT10__V_SYNC_START__SHIFT 0x0
-+#define CRT11__V_SYNC_END_MASK 0xf
-+#define CRT11__V_SYNC_END__SHIFT 0x0
-+#define CRT11__V_INTR_CLR_MASK 0x10
-+#define CRT11__V_INTR_CLR__SHIFT 0x4
-+#define CRT11__V_INTR_EN_MASK 0x20
-+#define CRT11__V_INTR_EN__SHIFT 0x5
-+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
-+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
-+#define CRT11__C0T7_WR_ONLY_MASK 0x80
-+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
-+#define CRT12__V_DISP_END_MASK 0xff
-+#define CRT12__V_DISP_END__SHIFT 0x0
-+#define CRT13__DISP_PITCH_MASK 0xff
-+#define CRT13__DISP_PITCH__SHIFT 0x0
-+#define CRT14__UNDRLN_LOC_MASK 0x1f
-+#define CRT14__UNDRLN_LOC__SHIFT 0x0
-+#define CRT14__ADDR_CNT_BY4_MASK 0x20
-+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
-+#define CRT14__DOUBLE_WORD_MASK 0x40
-+#define CRT14__DOUBLE_WORD__SHIFT 0x6
-+#define CRT15__V_BLANK_START_MASK 0xff
-+#define CRT15__V_BLANK_START__SHIFT 0x0
-+#define CRT16__V_BLANK_END_MASK 0xff
-+#define CRT16__V_BLANK_END__SHIFT 0x0
-+#define CRT17__RA0_AS_A13B_MASK 0x1
-+#define CRT17__RA0_AS_A13B__SHIFT 0x0
-+#define CRT17__RA1_AS_A14B_MASK 0x2
-+#define CRT17__RA1_AS_A14B__SHIFT 0x1
-+#define CRT17__VCOUNT_BY2_MASK 0x4
-+#define CRT17__VCOUNT_BY2__SHIFT 0x2
-+#define CRT17__ADDR_CNT_BY2_MASK 0x8
-+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
-+#define CRT17__WRAP_A15TOA0_MASK 0x20
-+#define CRT17__WRAP_A15TOA0__SHIFT 0x5
-+#define CRT17__BYTE_MODE_MASK 0x40
-+#define CRT17__BYTE_MODE__SHIFT 0x6
-+#define CRT17__CRTC_SYNC_EN_MASK 0x80
-+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
-+#define CRT18__LINE_CMP_MASK 0xff
-+#define CRT18__LINE_CMP__SHIFT 0x0
-+#define CRT1E__GRPH_DEC_RD1_MASK 0x2
-+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
-+#define CRT1F__GRPH_DEC_RD0_MASK 0xff
-+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
-+#define CRT22__GRPH_LATCH_DATA_MASK 0xff
-+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
-+#define GRPH8_IDX__GRPH_IDX_MASK 0xf
-+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
-+#define GRPH8_DATA__GRPH_DATA_MASK 0xff
-+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
-+#define GRA00__GRPH_SET_RESET0_MASK 0x1
-+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
-+#define GRA00__GRPH_SET_RESET1_MASK 0x2
-+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
-+#define GRA00__GRPH_SET_RESET2_MASK 0x4
-+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
-+#define GRA00__GRPH_SET_RESET3_MASK 0x8
-+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
-+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
-+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
-+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
-+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
-+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
-+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
-+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
-+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
-+#define GRA02__GRPH_CCOMP_MASK 0xf
-+#define GRA02__GRPH_CCOMP__SHIFT 0x0
-+#define GRA03__GRPH_ROTATE_MASK 0x7
-+#define GRA03__GRPH_ROTATE__SHIFT 0x0
-+#define GRA03__GRPH_FN_SEL_MASK 0x18
-+#define GRA03__GRPH_FN_SEL__SHIFT 0x3
-+#define GRA04__GRPH_RMAP_MASK 0x3
-+#define GRA04__GRPH_RMAP__SHIFT 0x0
-+#define GRA05__GRPH_WRITE_MODE_MASK 0x3
-+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
-+#define GRA05__GRPH_READ1_MASK 0x8
-+#define GRA05__GRPH_READ1__SHIFT 0x3
-+#define GRA05__CGA_ODDEVEN_MASK 0x10
-+#define GRA05__CGA_ODDEVEN__SHIFT 0x4
-+#define GRA05__GRPH_OES_MASK 0x20
-+#define GRA05__GRPH_OES__SHIFT 0x5
-+#define GRA05__GRPH_PACK_MASK 0x40
-+#define GRA05__GRPH_PACK__SHIFT 0x6
-+#define GRA06__GRPH_GRAPHICS_MASK 0x1
-+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
-+#define GRA06__GRPH_ODDEVEN_MASK 0x2
-+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
-+#define GRA06__GRPH_ADRSEL_MASK 0xc
-+#define GRA06__GRPH_ADRSEL__SHIFT 0x2
-+#define GRA07__GRPH_XCARE0_MASK 0x1
-+#define GRA07__GRPH_XCARE0__SHIFT 0x0
-+#define GRA07__GRPH_XCARE1_MASK 0x2
-+#define GRA07__GRPH_XCARE1__SHIFT 0x1
-+#define GRA07__GRPH_XCARE2_MASK 0x4
-+#define GRA07__GRPH_XCARE2__SHIFT 0x2
-+#define GRA07__GRPH_XCARE3_MASK 0x8
-+#define GRA07__GRPH_XCARE3__SHIFT 0x3
-+#define GRA08__GRPH_BMSK_MASK 0xff
-+#define GRA08__GRPH_BMSK__SHIFT 0x0
-+#define ATTRX__ATTR_IDX_MASK 0x1f
-+#define ATTRX__ATTR_IDX__SHIFT 0x0
-+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
-+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
-+#define ATTRDW__ATTR_DATA_MASK 0xff
-+#define ATTRDW__ATTR_DATA__SHIFT 0x0
-+#define ATTRDR__ATTR_DATA_MASK 0xff
-+#define ATTRDR__ATTR_DATA__SHIFT 0x0
-+#define ATTR00__ATTR_PAL_MASK 0x3f
-+#define ATTR00__ATTR_PAL__SHIFT 0x0
-+#define ATTR01__ATTR_PAL_MASK 0x3f
-+#define ATTR01__ATTR_PAL__SHIFT 0x0
-+#define ATTR02__ATTR_PAL_MASK 0x3f
-+#define ATTR02__ATTR_PAL__SHIFT 0x0
-+#define ATTR03__ATTR_PAL_MASK 0x3f
-+#define ATTR03__ATTR_PAL__SHIFT 0x0
-+#define ATTR04__ATTR_PAL_MASK 0x3f
-+#define ATTR04__ATTR_PAL__SHIFT 0x0
-+#define ATTR05__ATTR_PAL_MASK 0x3f
-+#define ATTR05__ATTR_PAL__SHIFT 0x0
-+#define ATTR06__ATTR_PAL_MASK 0x3f
-+#define ATTR06__ATTR_PAL__SHIFT 0x0
-+#define ATTR07__ATTR_PAL_MASK 0x3f
-+#define ATTR07__ATTR_PAL__SHIFT 0x0
-+#define ATTR08__ATTR_PAL_MASK 0x3f
-+#define ATTR08__ATTR_PAL__SHIFT 0x0
-+#define ATTR09__ATTR_PAL_MASK 0x3f
-+#define ATTR09__ATTR_PAL__SHIFT 0x0
-+#define ATTR0A__ATTR_PAL_MASK 0x3f
-+#define ATTR0A__ATTR_PAL__SHIFT 0x0
-+#define ATTR0B__ATTR_PAL_MASK 0x3f
-+#define ATTR0B__ATTR_PAL__SHIFT 0x0
-+#define ATTR0C__ATTR_PAL_MASK 0x3f
-+#define ATTR0C__ATTR_PAL__SHIFT 0x0
-+#define ATTR0D__ATTR_PAL_MASK 0x3f
-+#define ATTR0D__ATTR_PAL__SHIFT 0x0
-+#define ATTR0E__ATTR_PAL_MASK 0x3f
-+#define ATTR0E__ATTR_PAL__SHIFT 0x0
-+#define ATTR0F__ATTR_PAL_MASK 0x3f
-+#define ATTR0F__ATTR_PAL__SHIFT 0x0
-+#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
-+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
-+#define ATTR10__ATTR_MONO_EN_MASK 0x2
-+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
-+#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
-+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
-+#define ATTR10__ATTR_BLINK_EN_MASK 0x8
-+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
-+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
-+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
-+#define ATTR10__ATTR_PCLKBY2_MASK 0x40
-+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
-+#define ATTR10__ATTR_CSEL_EN_MASK 0x80
-+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
-+#define ATTR11__ATTR_OVSC_MASK 0xff
-+#define ATTR11__ATTR_OVSC__SHIFT 0x0
-+#define ATTR12__ATTR_MAP_EN_MASK 0xf
-+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
-+#define ATTR12__ATTR_VSMUX_MASK 0x30
-+#define ATTR12__ATTR_VSMUX__SHIFT 0x4
-+#define ATTR13__ATTR_PPAN_MASK 0xf
-+#define ATTR13__ATTR_PPAN__SHIFT 0x0
-+#define ATTR14__ATTR_CSEL1_MASK 0x3
-+#define ATTR14__ATTR_CSEL1__SHIFT 0x0
-+#define ATTR14__ATTR_CSEL2_MASK 0xc
-+#define ATTR14__ATTR_CSEL2__SHIFT 0x2
-+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
-+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
-+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
-+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
-+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
-+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
-+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
-+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
-+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
-+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
-+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
-+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
-+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
-+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
-+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
-+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
-+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
-+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
-+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
-+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
-+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
-+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
-+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
-+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
-+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
-+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
-+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
-+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
-+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
-+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
-+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
-+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
-+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
-+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
-+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
-+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
-+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
-+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
-+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
-+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
-+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
-+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
-+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
-+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
-+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
-+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
-+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
-+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
-+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
-+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
-+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
-+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
-+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
-+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
-+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
-+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
-+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
-+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
-+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
-+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
-+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
-+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
-+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
-+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
-+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
-+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
-+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
-+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
-+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
-+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
-+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
-+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
-+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
-+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
-+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
-+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
-+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
-+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
-+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
-+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
-+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
-+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
-+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
-+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
-+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
-+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
-+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
-+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
-+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
-+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
-+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
-+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
-+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
-+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
-+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
-+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
-+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
-+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
-+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
-+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
-+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
-+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
-+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
-+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
-+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
-+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
-+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
-+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
-+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
-+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
-+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
-+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
-+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
-+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
-+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
-+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
-+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
-+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
-+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
-+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
-+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
-+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
-+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
-+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
-+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
-+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
-+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
-+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
-+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
-+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
-+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
-+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
-+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
-+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
-+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
-+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
-+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
-+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
-+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
-+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
-+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
-+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
-+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
-+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
-+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
-+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
-+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
-+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
-+#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
-+#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
-+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
-+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
-+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
-+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
-+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
-+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
-+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
-+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
-+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
-+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
-+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
-+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
-+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
-+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
-+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
-+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
-+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
-+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
-+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
-+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
-+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
-+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
-+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
-+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
-+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
-+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
-+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
-+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
-+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
-+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
-+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
-+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
-+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
-+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
-+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
-+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
-+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
-+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
-+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
-+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
-+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000
-+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
-+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
-+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
-+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
-+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
-+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
-+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
-+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
-+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
-+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
-+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
-+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
-+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
-+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
-+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
-+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
-+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
-+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
-+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
-+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
-+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
-+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
-+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
-+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
-+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
-+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
-+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
-+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
-+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
-+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
-+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
-+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
-+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
-+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
-+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
-+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
-+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
-+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
-+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
-+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
-+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
-+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
-+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
-+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
-+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
-+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
-+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
-+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
-+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
-+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x7
-+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
-+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x700
-+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
-+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x70000
-+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
-+#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
-+#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
-+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
-+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
-+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
-+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
-+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
-+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
-+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
-+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff8000
-+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0xf
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
-+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
-+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
-+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
-+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
-+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
-+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
-+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
-+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
-+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
-+#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
-+#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
-+#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
-+#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_MASK 0x1
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED__SHIFT 0x0
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_MASK 0x2
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED__SHIFT 0x1
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR_MASK 0x10
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR__SHIFT 0x4
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR_MASK 0x20
-+#define DPG_DVMM_STATUS__DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR__SHIFT 0x5
-+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
-+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
-+#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
-+#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
-+#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
-+#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
-+#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
-+#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
-+#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
-+#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
-+#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
-+#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
-+#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
-+#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
-+#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
-+#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
-+#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
-+#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
-+#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
-+#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
-+#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
-+#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
-+#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
-+#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
-+#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
-+#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
-+#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
-+#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
-+#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
-+#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
-+#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
-+#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
-+#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
-+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
-+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
-+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
-+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
-+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
-+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
-+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
-+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
-+#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
-+#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
-+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
-+#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
-+#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
-+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
-+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
-+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
-+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
-+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
-+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
-+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
-+#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
-+#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
-+#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
-+#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
-+#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
-+#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
-+#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
-+#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
-+#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
-+#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
-+#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
-+#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
-+#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
-+#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
-+#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
-+#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
-+#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
-+#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
-+#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
-+#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
-+#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
-+#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
-+#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
-+#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
-+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
-+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
-+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
-+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
-+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
-+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
-+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
-+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
-+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
-+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
-+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
-+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
-+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
-+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
-+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
-+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
-+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
-+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
-+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
-+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7
-+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
-+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
-+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f
-+#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0
-+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0
-+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6
-+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
-+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
-+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
-+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
-+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
-+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
-+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
-+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
-+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
-+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
-+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
-+#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
-+#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
-+#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
-+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
-+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
-+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
-+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
-+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
-+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
-+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
-+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
-+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
-+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
-+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
-+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
-+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
-+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
-+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
-+#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
-+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
-+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
-+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
-+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff
-+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0
-+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1
-+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
-+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2
-+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
-+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4
-+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
-+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8
-+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
-+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10
-+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
-+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20
-+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
-+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40
-+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6
-+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80
-+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7
-+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100
-+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8
-+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200
-+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9
-+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400
-+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
-+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800
-+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb
-+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000
-+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc
-+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000
-+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd
-+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000
-+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe
-+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000
-+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf
-+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
-+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
-+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
-+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
-+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1
-+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
-+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2
-+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
-+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4
-+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
-+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8
-+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
-+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10
-+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
-+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20
-+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
-+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40
-+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6
-+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80
-+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7
-+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100
-+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8
-+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200
-+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9
-+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400
-+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
-+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800
-+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb
-+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000
-+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc
-+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000
-+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd
-+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000
-+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe
-+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000
-+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf
-+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
-+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
-+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
-+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
-+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
-+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
-+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
-+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
-+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
-+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
-+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
-+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
-+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
-+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
-+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
-+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
-+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
-+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
-+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40
-+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6
-+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80
-+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7
-+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100
-+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8
-+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200
-+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9
-+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400
-+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
-+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800
-+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb
-+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000
-+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc
-+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000
-+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd
-+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000
-+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe
-+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000
-+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf
-+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
-+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
-+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
-+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
-+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
-+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
-+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
-+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
-+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
-+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
-+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
-+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
-+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
-+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
-+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
-+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
-+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
-+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
-+#define CORB_SIZE__CORB_SIZE_MASK 0x3
-+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
-+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
-+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
-+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
-+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
-+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
-+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
-+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
-+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
-+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
-+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
-+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
-+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
-+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
-+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
-+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
-+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
-+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
-+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
-+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
-+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
-+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
-+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
-+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
-+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
-+#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
-+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
-+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
-+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
-+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
-+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
-+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
-+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
-+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
-+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
-+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
-+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
-+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
-+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
-+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
-+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
-+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
-+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
-+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
-+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
-+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
-+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
-+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
-+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
-+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
-+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
-+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
-+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
-+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
-+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
-+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
-+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
-+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
-+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
-+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
-+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
-+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
-+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
-+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
-+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
-+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
-+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
-+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
-+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
-+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
-+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
-+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
-+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
-+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
-+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
-+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
-+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
-+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
-+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
-+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
-+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
-+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
-+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
-+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
-+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
-+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
-+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
-+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
-+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
-+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
-+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
-+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
-+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
-+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
-+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
-+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
-+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
-+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
-+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
-+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
-+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
-+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc
-+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
-+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
-+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
-+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0
-+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
-+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
-+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
-+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
-+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
-+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
-+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
-+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc
-+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
-+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
-+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
-+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0
-+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
-+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
-+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
-+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
-+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
-+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0
-+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
-+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
-+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
-+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
-+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
-+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
-+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
-+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
-+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
-+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
-+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
-+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
-+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
-+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
-+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
-+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
-+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
-+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
-+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
-+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000
-+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
-+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
-+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
-+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000
-+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
-+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
-+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
-+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3
-+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
-+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4
-+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000
-+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
-+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000
-+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
-+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3
-+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000
-+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
-+#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1
-+#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1
-+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
-+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
-+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
-+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
-+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
-+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
-+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
-+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
-+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
-+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
-+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
-+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1
-+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
-+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
-+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
-+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
-+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
-+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
-+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
-+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
-+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
-+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
-+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
-+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
-+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
-+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
-+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
-+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
-+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
-+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
-+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
-+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
-+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
-+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
-+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
-+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
-+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
-+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
-+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
-+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
-+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
-+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
-+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
-+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
-+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
-+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
-+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
-+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
-+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
-+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
-+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
-+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
-+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
-+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
-+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
-+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
-+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
-+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
-+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
-+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
-+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
-+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
-+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
-+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
-+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
-+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
-+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
-+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
-+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
-+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
-+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
-+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
-+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
-+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
-+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
-+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
-+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
-+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
-+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
-+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
-+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
-+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
-+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
-+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
-+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
-+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
-+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
-+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
-+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
-+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
-+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
-+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
-+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
-+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
-+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
-+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
-+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
-+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
-+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
-+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
-+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
-+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
-+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
-+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
-+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
-+#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
-+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
-+#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
-+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
-+#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1
-+#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
-+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1
-+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
-+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10
-+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
-+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100
-+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
-+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1
-+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
-+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10
-+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
-+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100
-+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
-+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1
-+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
-+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10
-+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
-+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100
-+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff
-+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
-+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
-+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
-+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
-+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
-+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
-+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
-+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
-+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
-+#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
-+#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
-+#define BLND_CONTROL__BLND_MODE_MASK 0x300
-+#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
-+#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
-+#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
-+#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
-+#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
-+#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
-+#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
-+#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
-+#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
-+#define BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x40000
-+#define BLND_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
-+#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
-+#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
-+#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
-+#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
-+#define BLND_SM_CONTROL2__SM_MODE_MASK 0x7
-+#define BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
-+#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
-+#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
-+#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
-+#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
-+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
-+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
-+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
-+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
-+#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
-+#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
-+#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1
-+#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
-+#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
-+#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
-+#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
-+#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
-+#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
-+#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
-+#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
-+#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
-+#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
-+#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
-+#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
-+#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
-+#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
-+#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
-+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
-+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
-+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
-+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
-+#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
-+#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
-+#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
-+#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
-+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
-+#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
-+#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
-+#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
-+#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
-+#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
-+#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
-+#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
-+#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
-+#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
-+#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
-+#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
-+#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
-+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
-+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
-+#define WB_ENABLE__WB_ENABLE_MASK 0x1
-+#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
-+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1
-+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
-+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2
-+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
-+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4
-+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
-+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x78
-+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3
-+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x80
-+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7
-+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x100
-+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8
-+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x200
-+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x3000
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x4000
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x18000
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x60000
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x180000
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x600000
-+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15
-+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000
-+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
-+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x3000000
-+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18
-+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0xc000000
-+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a
-+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
-+#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
-+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
-+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
-+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300
-+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
-+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000
-+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
-+#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000
-+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
-+#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000
-+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
-+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
-+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
-+#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000
-+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
-+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000
-+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
-+#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000
-+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
-+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
-+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
-+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000
-+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
-+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
-+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
-+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
-+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
-+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
-+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
-+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
-+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
-+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
-+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
-+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
-+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
-+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
-+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
-+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
-+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
-+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
-+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
-+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1
-+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
-+#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
-+#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
-+#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
-+#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
-+#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
-+#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
-+#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
-+#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
-+#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
-+#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
-+#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
-+#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
-+#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
-+#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
-+#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
-+#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
-+#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
-+#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
-+#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
-+#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
-+#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
-+#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
-+#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
-+#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
-+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
-+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
-+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
-+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
-+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
-+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
-+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
-+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
-+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
-+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
-+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
-+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
-+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
-+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
-+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
-+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
-+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
-+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
-+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
-+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
-+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
-+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
-+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
-+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
-+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0
-+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
-+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
-+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
-+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0
-+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
-+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
-+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
-+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0
-+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
-+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
-+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
-+#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1
-+#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0
-+#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0
-+#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
-+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1
-+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
-+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2
-+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
-+#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4
-+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
-+#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8
-+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
-+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100
-+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
-+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000
-+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
-+#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff
-+#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
-+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3
-+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
-+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c
-+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
-+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1
-+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
-+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x7fff
-+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0
-+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7fff0000
-+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10
-+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000
-+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f
-+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0xff
-+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0
-+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x100
-+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8
-+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
-+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
-+#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x8000
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE_MASK 0x20000
-+#define DCFE_CLOCK_CONTROL__DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE__SHIFT 0x11
-+#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000
-+#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
-+#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000
-+#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
-+#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1
-+#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
-+#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2
-+#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
-+#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4
-+#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
-+#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8
-+#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
-+#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
-+#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
-+#define DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x20
-+#define DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
-+#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1
-+#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0
-+#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0
-+#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4
-+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3
-+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
-+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4
-+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
-+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18
-+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
-+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20
-+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
-+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0
-+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
-+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100
-+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
-+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600
-+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
-+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
-+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
-+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000
-+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
-+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000
-+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
-+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000
-+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
-+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
-+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
-+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000
-+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
-+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000
-+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
-+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000
-+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
-+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000
-+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
-+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000
-+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
-+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000
-+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
-+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000
-+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
-+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000
-+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
-+#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3
-+#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
-+#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc
-+#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
-+#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
-+#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
-+#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300
-+#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
-+#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00
-+#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
-+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000
-+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
-+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000
-+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
-+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000
-+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000
-+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
-+#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
-+#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
-+#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc
-+#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
-+#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30
-+#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
-+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0
-+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
-+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300
-+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
-+#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00
-+#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
-+#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000
-+#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
-+#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000
-+#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
-+#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000
-+#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
-+#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
-+#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
-+#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000
-+#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
-+#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000
-+#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
-+#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x1
-+#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
-+#define DCFE_FLUSH__FLUSH_OCCURED_MASK 0x1
-+#define DCFE_FLUSH__FLUSH_OCCURED__SHIFT 0x0
-+#define DCFE_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x2
-+#define DCFE_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
-+#define DCFE_FLUSH__FLUSH_DEEP_MASK 0x4
-+#define DCFE_FLUSH__FLUSH_DEEP__SHIFT 0x2
-+#define DCFE_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x8
-+#define DCFE_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
-+#define DCFE_FLUSH__ALL_MC_REQ_RET_MASK 0x10
-+#define DCFE_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000
-+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
-+#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000
-+#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
-+#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000
-+#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
-+#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1
-+#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
-+#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2
-+#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
-+#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4
-+#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
-+#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8
-+#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
-+#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
-+#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
-+#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20
-+#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
-+#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40
-+#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000
-+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
-+#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1
-+#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0
-+#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0
-+#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800
-+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000
-+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK 0x3
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT 0x0
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK 0x4
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT 0x2
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x18
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x20
-+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
-+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0xc0
-+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
-+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x100
-+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
-+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x600
-+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
-+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x800
-+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
-+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x3000
-+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
-+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x4000
-+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
-+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x18000
-+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
-+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x20000
-+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
-+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK 0x3
-+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT 0x0
-+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0xc
-+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
-+#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
-+#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
-+#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0xc0
-+#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
-+#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK 0x3
-+#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT 0x0
-+#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0xc
-+#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
-+#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x30
-+#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
-+#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0xc0
-+#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
-+#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x300
-+#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
-+#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0xc00
-+#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
-+#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x3000
-+#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
-+#define DCFEV_L_FLUSH__FLUSH_OCCURED_MASK 0x1
-+#define DCFEV_L_FLUSH__FLUSH_OCCURED__SHIFT 0x0
-+#define DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x2
-+#define DCFEV_L_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
-+#define DCFEV_L_FLUSH__FLUSH_DEEP_MASK 0x4
-+#define DCFEV_L_FLUSH__FLUSH_DEEP__SHIFT 0x2
-+#define DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x8
-+#define DCFEV_L_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
-+#define DCFEV_L_FLUSH__ALL_MC_REQ_RET_MASK 0x10
-+#define DCFEV_L_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
-+#define DCFEV_C_FLUSH__FLUSH_OCCURED_MASK 0x1
-+#define DCFEV_C_FLUSH__FLUSH_OCCURED__SHIFT 0x0
-+#define DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED_MASK 0x2
-+#define DCFEV_C_FLUSH__CLEAR_FLUSH_OCCURED__SHIFT 0x1
-+#define DCFEV_C_FLUSH__FLUSH_DEEP_MASK 0x4
-+#define DCFEV_C_FLUSH__FLUSH_DEEP__SHIFT 0x2
-+#define DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP_MASK 0x8
-+#define DCFEV_C_FLUSH__CLEAR_FLUSH_DEEP__SHIFT 0x3
-+#define DCFEV_C_FLUSH__ALL_MC_REQ_RET_MASK 0x10
-+#define DCFEV_C_FLUSH__ALL_MC_REQ_RET__SHIFT 0x4
-+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK 0xf
-+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT 0x0
-+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK 0x10
-+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT 0x4
-+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK 0x20
-+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT 0x5
-+#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x1
-+#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
-+#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1
-+#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
-+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2
-+#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
-+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10
-+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
-+#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100
-+#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
-+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
-+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
-+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
-+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
-+#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1
-+#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
-+#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100
-+#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
-+#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000
-+#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
-+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000
-+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
-+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000
-+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
-+#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff
-+#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
-+#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000
-+#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
-+#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000
-+#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
-+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
-+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff
-+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
-+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000
-+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
-+#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff
-+#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
-+#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff
-+#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
-+#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff
-+#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
-+#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff
-+#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
-+#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff
-+#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
-+#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff
-+#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
-+#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff
-+#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
-+#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff
-+#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
-+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
-+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
-+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
-+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000
-+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x400
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x800
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x1000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x2000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT_MASK 0x4000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER2_INTERRUPT__SHIFT 0xe
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT_MASK 0x8000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER3_INTERRUPT__SHIFT 0xf
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT_MASK 0x10000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER4_INTERRUPT__SHIFT 0x10
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT_MASK 0x20000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER5_INTERRUPT__SHIFT 0x11
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT_MASK 0x40000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER6_INTERRUPT__SHIFT 0x12
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT_MASK 0x80000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER7_INTERRUPT__SHIFT 0x13
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT_MASK 0x100000
-+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER_OFF_INTERRUPT__SHIFT 0x14
-+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1
-+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
-+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4
-+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
-+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8
-+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
-+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10
-+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
-+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20
-+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
-+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40
-+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
-+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80
-+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
-+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100
-+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
-+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200
-+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
-+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00
-+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
-+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000
-+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
-+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000
-+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
-+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000
-+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
-+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000
-+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
-+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000
-+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
-+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000
-+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
-+#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x1
-+#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0
-+#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x2
-+#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1
-+#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0xc00
-+#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa
-+#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x3000
-+#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
-+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1
-+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
-+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2
-+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
-+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8
-+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
-+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10
-+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
-+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20
-+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
-+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40
-+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
-+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80
-+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
-+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100
-+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
-+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200
-+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
-+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400
-+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
-+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800
-+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
-+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000
-+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
-+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000
-+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
-+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000
-+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
-+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000
-+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
-+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000
-+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
-+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000
-+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
-+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000
-+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
-+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000
-+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
-+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000
-+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
-+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000
-+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
-+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000
-+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
-+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000
-+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
-+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000
-+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
-+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3
-+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
-+#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x4
-+#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2
-+#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x8
-+#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3
-+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x30000
-+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10
-+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x40000
-+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12
-+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x180000
-+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13
-+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x200000
-+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL_MASK 0x7
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_SOURCE_SEL__SHIFT 0x0
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE_MASK 0x30
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_FORCE__SHIFT 0x4
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS_MASK 0x100
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_DIS__SHIFT 0x8
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE_MASK 0x3000
-+#define FMT_MEMORY0_CONTROL__FMT420_MEM0_PWR_STATE__SHIFT 0xc
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL_MASK 0x7
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_SOURCE_SEL__SHIFT 0x0
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE_MASK 0x30
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_FORCE__SHIFT 0x4
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS_MASK 0x100
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_DIS__SHIFT 0x8
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE_MASK 0x3000
-+#define FMT_MEMORY1_CONTROL__FMT420_MEM1_PWR_STATE__SHIFT 0xc
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL_MASK 0x7
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_SOURCE_SEL__SHIFT 0x0
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE_MASK 0x30
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_FORCE__SHIFT 0x4
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS_MASK 0x100
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_DIS__SHIFT 0x8
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE_MASK 0x3000
-+#define FMT_MEMORY2_CONTROL__FMT420_MEM2_PWR_STATE__SHIFT 0xc
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL_MASK 0x7
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_SOURCE_SEL__SHIFT 0x0
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE_MASK 0x30
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_FORCE__SHIFT 0x4
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS_MASK 0x100
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_DIS__SHIFT 0x8
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE_MASK 0x3000
-+#define FMT_MEMORY3_CONTROL__FMT420_MEM3_PWR_STATE__SHIFT 0xc
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL_MASK 0x7
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_SOURCE_SEL__SHIFT 0x0
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE_MASK 0x30
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_FORCE__SHIFT 0x4
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS_MASK 0x100
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_DIS__SHIFT 0x8
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE_MASK 0x3000
-+#define FMT_MEMORY4_CONTROL__FMT420_MEM4_PWR_STATE__SHIFT 0xc
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL_MASK 0x7
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_SOURCE_SEL__SHIFT 0x0
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE_MASK 0x30
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_FORCE__SHIFT 0x4
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS_MASK 0x100
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_DIS__SHIFT 0x8
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE_MASK 0x3000
-+#define FMT_MEMORY5_CONTROL__FMT420_MEM5_PWR_STATE__SHIFT 0xc
-+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
-+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
-+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
-+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
-+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
-+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
-+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
-+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
-+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
-+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
-+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400
-+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
-+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x400000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x800000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
-+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
-+#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x7f
-+#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x80
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x100
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x200
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x400
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x800
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x1000
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x2000
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x8000
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x10000
-+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10
-+#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x20000
-+#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
-+#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x40000
-+#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
-+#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x80000
-+#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
-+#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x100000
-+#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
-+#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x200000
-+#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
-+#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x400000
-+#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
-+#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x800000
-+#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
-+#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x2000000
-+#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19
-+#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x4000000
-+#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a
-+#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x1
-+#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
-+#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x2
-+#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
-+#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x4
-+#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
-+#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x8
-+#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
-+#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x10
-+#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
-+#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x20
-+#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
-+#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x40
-+#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
-+#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x100
-+#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8
-+#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x200
-+#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9
-+#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x400
-+#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
-+#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x800
-+#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
-+#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x1000
-+#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
-+#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x2000
-+#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
-+#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x4000
-+#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
-+#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x8000
-+#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
-+#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x10000
-+#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
-+#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x40000
-+#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12
-+#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x80000
-+#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13
-+#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1
-+#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0
-+#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2
-+#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1
-+#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10
-+#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4
-+#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100
-+#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8
-+#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000
-+#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000
-+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18
-+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
-+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
-+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
-+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
-+#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
-+#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
-+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
-+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
-+#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
-+#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
-+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
-+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
-+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000
-+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
-+#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
-+#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
-+#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
-+#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
-+#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
-+#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
-+#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
-+#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
-+#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
-+#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
-+#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
-+#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
-+#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
-+#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
-+#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
-+#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
-+#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
-+#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
-+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
-+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
-+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
-+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
-+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
-+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
-+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
-+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
-+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
-+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
-+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
-+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
-+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
-+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
-+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
-+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
-+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
-+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
-+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
-+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
-+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
-+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
-+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
-+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
-+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
-+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
-+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
-+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
-+#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000
-+#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f
-+#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x1
-+#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0
-+#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x2
-+#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1
-+#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x10
-+#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4
-+#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x20
-+#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5
-+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
-+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
-+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
-+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x1
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x10
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x100
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x1000
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0xfff0000
-+#define DCO_HDMI_RXSTATUS_TIMER_CONTROL__DCO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10
-+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS_MASK 0x1
-+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_STATUS__SHIFT 0x0
-+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE_MASK 0xfffffffe
-+#define DCO_PSP_INTERRUPT_STATUS__DCO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1
-+#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR_MASK 0x1
-+#define DCO_PSP_INTERRUPT_CLEAR__DCO_PSP_INTERRUPT_CLEAR__SHIFT 0x0
-+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS_MASK 0x1
-+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0
-+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE_MASK 0xfffffffe
-+#define DCO_GENERIC_INTERRUPT_MESSAGE__DCO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1
-+#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR_MASK 0x1
-+#define DCO_GENERIC_INTERRUPT_CLEAR__DCO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0
-+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff
-+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0
-+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
-+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
-+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
-+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
-+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
-+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
-+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
-+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
-+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
-+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
-+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
-+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
-+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
-+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
-+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
-+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
-+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
-+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
-+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
-+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
-+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
-+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
-+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
-+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
-+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
-+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
-+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
-+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
-+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
-+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
-+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
-+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
-+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
-+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
-+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
-+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
-+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
-+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
-+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
-+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
-+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
-+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x3ff0000
-+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
-+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
-+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
-+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
-+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
-+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
-+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
-+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
-+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
-+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x3ff0000
-+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
-+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
-+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
-+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
-+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
-+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
-+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
-+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
-+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
-+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x3ff0000
-+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
-+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
-+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
-+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
-+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
-+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
-+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
-+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
-+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
-+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x3ff0000
-+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
-+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
-+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
-+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
-+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
-+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x3ff0000
-+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
-+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
-+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
-+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
-+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
-+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
-+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
-+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
-+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
-+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
-+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
-+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000
-+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
-+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000
-+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
-+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
-+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
-+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
-+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
-+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
-+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
-+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
-+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
-+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
-+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
-+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
-+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
-+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
-+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
-+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
-+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
-+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
-+#define BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
-+#define BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
-+#define BLNDV_CONTROL__BLND_MODE_MASK 0x300
-+#define BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
-+#define BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
-+#define BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
-+#define BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
-+#define BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
-+#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
-+#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
-+#define BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
-+#define BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
-+#define BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY_MASK 0x40000
-+#define BLNDV_CONTROL__BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x12
-+#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
-+#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
-+#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
-+#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
-+#define BLNDV_SM_CONTROL2__SM_MODE_MASK 0x7
-+#define BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
-+#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
-+#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
-+#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
-+#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
-+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
-+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
-+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
-+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
-+#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
-+#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
-+#define BLNDV_CONTROL2__PTI_ENABLE_MASK 0x1
-+#define BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
-+#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
-+#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
-+#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
-+#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
-+#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
-+#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
-+#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
-+#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
-+#define BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
-+#define BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
-+#define BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
-+#define BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
-+#define BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
-+#define BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
-+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
-+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
-+#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
-+#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
-+#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
-+#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
-+#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
-+#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
-+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
-+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
-+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
-+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
-+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
-+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
-+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
-+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
-+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
-+#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
-+#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
-+#define BLNDV_DEBUG__BLND_DEBUG_MASK 0xfffffffe
-+#define BLNDV_DEBUG__BLND_DEBUG__SHIFT 0x1
-+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
-+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
-+#define CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
-+#define CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
-+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
-+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
-+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
-+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
-+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
-+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
-+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
-+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
-+#define CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
-+#define CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
-+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
-+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
-+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
-+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
-+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
-+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
-+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
-+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
-+#define CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x1
-+#define CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
-+#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
-+#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
-+#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
-+#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
-+#define CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
-+#define CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
-+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
-+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
-+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
-+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
-+#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
-+#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
-+#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
-+#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
-+#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
-+#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
-+#define CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
-+#define CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
-+#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
-+#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
-+#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
-+#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
-+#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
-+#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
-+#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2
-+#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
-+#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4
-+#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
-+#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100
-+#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
-+#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
-+#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
-+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
-+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
-+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
-+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
-+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
-+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
-+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
-+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
-+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
-+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
-+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
-+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
-+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
-+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
-+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
-+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
-+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
-+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
-+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
-+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
-+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
-+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
-+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
-+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
-+#define CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
-+#define CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
-+#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
-+#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
-+#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
-+#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
-+#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
-+#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
-+#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
-+#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
-+#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
-+#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
-+#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
-+#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
-+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
-+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
-+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
-+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
-+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
-+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
-+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
-+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
-+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
-+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
-+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
-+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
-+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
-+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
-+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
-+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
-+#define CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
-+#define CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
-+#define CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
-+#define CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
-+#define CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
-+#define CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
-+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
-+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
-+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
-+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
-+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
-+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
-+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
-+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
-+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
-+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
-+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
-+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
-+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
-+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
-+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
-+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
-+#define CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
-+#define CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
-+#define CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
-+#define CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
-+#define CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
-+#define CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
-+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
-+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
-+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
-+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
-+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
-+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
-+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
-+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
-+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
-+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
-+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
-+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
-+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
-+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
-+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
-+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
-+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
-+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
-+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
-+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
-+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
-+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
-+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
-+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
-+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
-+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
-+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
-+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
-+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
-+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
-+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
-+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
-+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
-+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000
-+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f
-+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
-+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
-+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
-+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
-+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
-+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
-+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
-+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
-+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
-+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
-+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
-+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
-+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
-+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
-+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
-+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
-+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
-+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
-+#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
-+#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
-+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
-+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
-+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
-+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
-+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
-+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
-+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
-+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400
-+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa
-+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
-+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
-+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
-+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
-+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
-+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
-+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
-+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
-+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
-+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
-+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
-+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
-+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
-+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
-+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
-+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
-+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
-+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
-+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
-+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
-+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
-+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
-+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
-+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
-+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
-+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
-+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
-+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
-+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
-+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
-+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
-+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
-+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
-+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
-+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
-+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
-+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
-+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
-+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
-+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
-+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
-+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
-+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000
-+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f
-+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
-+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
-+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
-+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
-+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
-+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
-+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
-+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
-+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
-+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
-+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
-+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
-+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
-+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
-+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
-+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
-+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
-+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
-+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
-+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
-+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
-+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
-+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
-+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
-+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
-+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
-+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000
-+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d
-+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000
-+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f
-+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
-+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
-+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
-+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
-+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
-+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
-+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
-+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
-+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
-+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
-+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
-+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
-+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
-+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
-+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
-+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
-+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
-+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
-+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
-+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
-+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
-+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
-+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
-+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
-+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
-+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
-+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
-+#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000
-+#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19
-+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
-+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
-+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
-+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
-+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
-+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
-+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
-+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
-+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
-+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
-+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
-+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
-+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
-+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
-+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
-+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
-+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
-+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
-+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
-+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
-+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
-+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
-+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
-+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
-+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
-+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
-+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
-+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
-+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
-+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
-+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
-+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
-+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
-+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
-+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
-+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
-+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
-+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
-+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
-+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
-+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000
-+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18
-+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
-+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
-+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
-+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
-+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
-+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
-+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
-+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
-+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
-+#define CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
-+#define CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
-+#define CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
-+#define CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
-+#define CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x100
-+#define CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8
-+#define CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
-+#define CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
-+#define CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
-+#define CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
-+#define CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x100
-+#define CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8
-+#define CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
-+#define CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
-+#define CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
-+#define CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
-+#define CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x100
-+#define CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8
-+#define CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
-+#define CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
-+#define CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
-+#define CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
-+#define CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x100
-+#define CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8
-+#define MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x7
-+#define MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0
-+#define MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x18
-+#define MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3
-+#define MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x20
-+#define MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5
-+#define MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x7
-+#define MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0
-+#define MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x18
-+#define MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3
-+#define MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x20
-+#define MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5
-+#define MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x7
-+#define MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0
-+#define MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x18
-+#define MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3
-+#define MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x20
-+#define MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5
-+#define MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x7
-+#define MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0
-+#define MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x18
-+#define MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3
-+#define MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x20
-+#define MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x6
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x18
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x300
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0xc00
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x1000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x2000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x4000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x8000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0xf0000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x100000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0xc00000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x6
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x18
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x300
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0xc00
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x1000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x2000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x4000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x8000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0xf0000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x100000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0xc00000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x6
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x18
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x300
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0xc00
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x1000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x2000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x4000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x8000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0xf0000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x100000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0xc00000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x6
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x18
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x300
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0xc00
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x1000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x2000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x4000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x8000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0xf0000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x100000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0xc00000
-+#define CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16
-+#define TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xffffffff
-+#define TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0
-+#define TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xffffffff
-+#define TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0
-+#define TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xffffffff
-+#define TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0
-+#define TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xffffffff
-+#define TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0
-+#define TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xffffffff
-+#define TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0
-+#define TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xffffffff
-+#define TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0
-+#define TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xffffffff
-+#define TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0
-+#define TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xffffffff
-+#define TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0
-+#define TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xffffffff
-+#define TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0
-+#define TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xffffffff
-+#define TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0
-+#define TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xffffffff
-+#define TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0
-+#define TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xffffffff
-+#define TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0
-+#define TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xffffffff
-+#define TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0
-+#define TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xffffffff
-+#define TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0
-+#define TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xffffffff
-+#define TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0
-+#define TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xffffffff
-+#define TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0
-+#define TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xffffffff
-+#define TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0
-+#define TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xffffffff
-+#define TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0
-+#define TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xffffffff
-+#define TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0
-+#define TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xffffffff
-+#define TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0
-+#define TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xffffffff
-+#define TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0
-+#define TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xffffffff
-+#define TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0
-+#define TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xffffffff
-+#define TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0
-+#define TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xffffffff
-+#define TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0
-+#define TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xffffffff
-+#define TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0
-+#define TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xffffffff
-+#define TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0
-+#define TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xffffffff
-+#define TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0
-+#define TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xffffffff
-+#define TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0
-+#define TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xffffffff
-+#define TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0
-+#define TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xffffffff
-+#define TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0
-+#define TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xffffffff
-+#define TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0
-+#define TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xffffffff
-+#define TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0
-+#define TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xffffffff
-+#define TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0
-+#define TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xffffffff
-+#define TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0
-+#define TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xffffffff
-+#define TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0
-+#define TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xffffffff
-+#define TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0
-+#define TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xffffffff
-+#define TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0
-+#define TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xffffffff
-+#define TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0
-+#define TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xffffffff
-+#define TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0
-+#define TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xffffffff
-+#define TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0
-+#define TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xffffffff
-+#define TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0
-+#define TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xffffffff
-+#define TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0
-+#define TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xffffffff
-+#define TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0
-+#define TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xffffffff
-+#define TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0
-+#define TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xffffffff
-+#define TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0
-+#define TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xffffffff
-+#define TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0
-+#define TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xffffffff
-+#define TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0
-+#define TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xffffffff
-+#define TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0
-+#define TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xffffffff
-+#define TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0
-+#define TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xffffffff
-+#define TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0
-+#define TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xffffffff
-+#define TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0
-+#define TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xffffffff
-+#define TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0
-+#define COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
-+#define COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
-+#define COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
-+#define COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
-+#define COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
-+#define COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
-+#define COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
-+#define COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
-+#define COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
-+#define COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
-+#define COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
-+#define COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
-+#define COMMON_LANE_PWRMGMT__vprot_en_MASK 0x800
-+#define COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb
-+#define COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x1f
-+#define COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0
-+#define COMMON_TXCNTRL__clkgate_dis_MASK 0x20
-+#define COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5
-+#define COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x1c0
-+#define COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6
-+#define COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0xe00
-+#define COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9
-+#define COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x7000
-+#define COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc
-+#define COMMON_TXCNTRL__dual_dvi_mstr_en_MASK 0x8000
-+#define COMMON_TXCNTRL__dual_dvi_mstr_en__SHIFT 0xf
-+#define COMMON_TXCNTRL__dual_dvi_en_MASK 0x10000
-+#define COMMON_TXCNTRL__dual_dvi_en__SHIFT 0x10
-+#define COMMON_TMDP__tmdp_spare_MASK 0xffffffff
-+#define COMMON_TMDP__tmdp_spare__SHIFT 0x0
-+#define COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x1
-+#define COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0
-+#define COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x2
-+#define COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1
-+#define COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x4
-+#define COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2
-+#define COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x8
-+#define COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3
-+#define COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x10
-+#define COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4
-+#define COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x20
-+#define COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5
-+#define COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x40
-+#define COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6
-+#define COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x80
-+#define COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7
-+#define COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x1
-+#define COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0
-+#define COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x3e
-+#define COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1
-+#define COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x200000
-+#define COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15
-+#define COMMON_DISP_RFU1__rfu_value1_MASK 0xffffffff
-+#define COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0
-+#define COMMON_DISP_RFU2__rfu_value2_MASK 0xffffffff
-+#define COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0
-+#define COMMON_DISP_RFU3__rfu_value3_MASK 0xffffffff
-+#define COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0
-+#define COMMON_DISP_RFU4__rfu_value4_MASK 0xffffffff
-+#define COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0
-+#define COMMON_DISP_RFU5__rfu_value5_MASK 0xffffffff
-+#define COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0
-+#define COMMON_DISP_RFU6__rfu_value6_MASK 0xffffffff
-+#define COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0
-+#define COMMON_DISP_RFU7__rfu_value7_MASK 0xffffffff
-+#define COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0
-+#define FREQ_CTRL0__fcw0_frac_MASK 0xffff
-+#define FREQ_CTRL0__fcw0_frac__SHIFT 0x0
-+#define FREQ_CTRL0__fcw0_int_MASK 0x1ff0000
-+#define FREQ_CTRL0__fcw0_int__SHIFT 0x10
-+#define FREQ_CTRL1__fcw1_frac_MASK 0xffff
-+#define FREQ_CTRL1__fcw1_frac__SHIFT 0x0
-+#define FREQ_CTRL1__fcw1_int_MASK 0x1ff0000
-+#define FREQ_CTRL1__fcw1_int__SHIFT 0x10
-+#define FREQ_CTRL2__fcw_denom_MASK 0xffff
-+#define FREQ_CTRL2__fcw_denom__SHIFT 0x0
-+#define FREQ_CTRL2__fcw_slew_frac_MASK 0xffff0000
-+#define FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10
-+#define FREQ_CTRL3__refclk_div_MASK 0x3
-+#define FREQ_CTRL3__refclk_div__SHIFT 0x0
-+#define FREQ_CTRL3__vco_pre_div_MASK 0x18
-+#define FREQ_CTRL3__vco_pre_div__SHIFT 0x3
-+#define FREQ_CTRL3__fracn_en_MASK 0x40
-+#define FREQ_CTRL3__fracn_en__SHIFT 0x6
-+#define FREQ_CTRL3__ssc_en_MASK 0x100
-+#define FREQ_CTRL3__ssc_en__SHIFT 0x8
-+#define FREQ_CTRL3__fcw_sel_MASK 0x400
-+#define FREQ_CTRL3__fcw_sel__SHIFT 0xa
-+#define FREQ_CTRL3__freq_jump_en_MASK 0x1000
-+#define FREQ_CTRL3__freq_jump_en__SHIFT 0xc
-+#define FREQ_CTRL3__tdc_resolution_MASK 0xff0000
-+#define FREQ_CTRL3__tdc_resolution__SHIFT 0x10
-+#define FREQ_CTRL3__dpll_cfg_1_MASK 0xff000000
-+#define FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18
-+#define BW_CTRL_COARSE__gi_coarse_mant_MASK 0x3
-+#define BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0
-+#define BW_CTRL_COARSE__gi_coarse_exp_MASK 0x3c
-+#define BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2
-+#define BW_CTRL_COARSE__gp_coarse_mant_MASK 0x780
-+#define BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7
-+#define BW_CTRL_COARSE__gp_coarse_exp_MASK 0xf000
-+#define BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc
-+#define BW_CTRL_COARSE__nctl_coarse_res_MASK 0x7e0000
-+#define BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11
-+#define BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x3000000
-+#define BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18
-+#define BW_CTRL_FINE__dpll_cfg_3_MASK 0x3ff
-+#define BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0
-+#define CAL_CTRL__bypass_freq_lock_MASK 0x1
-+#define CAL_CTRL__bypass_freq_lock__SHIFT 0x0
-+#define CAL_CTRL__tdc_cal_en_MASK 0x2
-+#define CAL_CTRL__tdc_cal_en__SHIFT 0x1
-+#define CAL_CTRL__tdc_cal_ctrl_MASK 0x1f8
-+#define CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3
-+#define CAL_CTRL__meas_win_sel_MASK 0x600
-+#define CAL_CTRL__meas_win_sel__SHIFT 0x9
-+#define CAL_CTRL__kdco_cal_dis_MASK 0x800
-+#define CAL_CTRL__kdco_cal_dis__SHIFT 0xb
-+#define CAL_CTRL__kdco_ratio_MASK 0x1fe000
-+#define CAL_CTRL__kdco_ratio__SHIFT 0xd
-+#define CAL_CTRL__kdco_incr_cal_dis_MASK 0x400000
-+#define CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16
-+#define CAL_CTRL__nctl_adj_dis_MASK 0x800000
-+#define CAL_CTRL__nctl_adj_dis__SHIFT 0x17
-+#define CAL_CTRL__refclk_rate_MASK 0xff000000
-+#define CAL_CTRL__refclk_rate__SHIFT 0x18
-+#define LOOP_CTRL__fbdiv_mask_en_MASK 0x1
-+#define LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0
-+#define LOOP_CTRL__fb_slip_dis_MASK 0x4
-+#define LOOP_CTRL__fb_slip_dis__SHIFT 0x2
-+#define LOOP_CTRL__clk_tdc_sel_MASK 0x30
-+#define LOOP_CTRL__clk_tdc_sel__SHIFT 0x4
-+#define LOOP_CTRL__clk_nctl_sel_MASK 0x180
-+#define LOOP_CTRL__clk_nctl_sel__SHIFT 0x7
-+#define LOOP_CTRL__sig_del_patt_sel_MASK 0x400
-+#define LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa
-+#define LOOP_CTRL__nctl_sig_del_dis_MASK 0x1000
-+#define LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc
-+#define LOOP_CTRL__fbclk_track_refclk_MASK 0x4000
-+#define LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe
-+#define LOOP_CTRL__prbs_en_MASK 0x10000
-+#define LOOP_CTRL__prbs_en__SHIFT 0x10
-+#define LOOP_CTRL__tdc_clk_gate_en_MASK 0x40000
-+#define LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12
-+#define LOOP_CTRL__phase_offset_MASK 0x7f00000
-+#define LOOP_CTRL__phase_offset__SHIFT 0x14
-+#define VREG_CFG__bleeder_ac_MASK 0x1
-+#define VREG_CFG__bleeder_ac__SHIFT 0x0
-+#define VREG_CFG__bleeder_en_MASK 0x2
-+#define VREG_CFG__bleeder_en__SHIFT 0x1
-+#define VREG_CFG__is_1p2_MASK 0x4
-+#define VREG_CFG__is_1p2__SHIFT 0x2
-+#define VREG_CFG__reg_obs_sel_MASK 0x18
-+#define VREG_CFG__reg_obs_sel__SHIFT 0x3
-+#define VREG_CFG__reg_on_mode_MASK 0x60
-+#define VREG_CFG__reg_on_mode__SHIFT 0x5
-+#define VREG_CFG__rlad_tap_sel_MASK 0x780
-+#define VREG_CFG__rlad_tap_sel__SHIFT 0x7
-+#define VREG_CFG__reg_off_hi_MASK 0x800
-+#define VREG_CFG__reg_off_hi__SHIFT 0xb
-+#define VREG_CFG__reg_off_lo_MASK 0x1000
-+#define VREG_CFG__reg_off_lo__SHIFT 0xc
-+#define VREG_CFG__scale_driver_MASK 0x6000
-+#define VREG_CFG__scale_driver__SHIFT 0xd
-+#define VREG_CFG__sel_bump_MASK 0x8000
-+#define VREG_CFG__sel_bump__SHIFT 0xf
-+#define VREG_CFG__sel_rladder_x_MASK 0x10000
-+#define VREG_CFG__sel_rladder_x__SHIFT 0x10
-+#define VREG_CFG__short_rc_filt_x_MASK 0x20000
-+#define VREG_CFG__short_rc_filt_x__SHIFT 0x11
-+#define VREG_CFG__vref_pwr_on_MASK 0x40000
-+#define VREG_CFG__vref_pwr_on__SHIFT 0x12
-+#define VREG_CFG__dpll_cfg_2_MASK 0xff00000
-+#define VREG_CFG__dpll_cfg_2__SHIFT 0x14
-+#define OBSERVE0__lock_det_tdc_steps_MASK 0x1f
-+#define OBSERVE0__lock_det_tdc_steps__SHIFT 0x0
-+#define OBSERVE0__clear_sticky_lock_MASK 0x40
-+#define OBSERVE0__clear_sticky_lock__SHIFT 0x6
-+#define OBSERVE0__lock_det_dis_MASK 0x100
-+#define OBSERVE0__lock_det_dis__SHIFT 0x8
-+#define OBSERVE0__dco_cfg_MASK 0x3fc00
-+#define OBSERVE0__dco_cfg__SHIFT 0xa
-+#define OBSERVE0__anaobs_sel_MASK 0xe00000
-+#define OBSERVE0__anaobs_sel__SHIFT 0x15
-+#define OBSERVE1__digobs_sel_MASK 0xf
-+#define OBSERVE1__digobs_sel__SHIFT 0x0
-+#define OBSERVE1__digobs_trig_sel_MASK 0x1e0
-+#define OBSERVE1__digobs_trig_sel__SHIFT 0x5
-+#define OBSERVE1__digobs_div_MASK 0xc00
-+#define OBSERVE1__digobs_div__SHIFT 0xa
-+#define OBSERVE1__digobs_trig_div_MASK 0x6000
-+#define OBSERVE1__digobs_trig_div__SHIFT 0xd
-+#define OBSERVE1__lock_timer_MASK 0x3fff0000
-+#define OBSERVE1__lock_timer__SHIFT 0x10
-+#define DFT_OUT__dft_data_MASK 0xffffffff
-+#define DFT_OUT__dft_data__SHIFT 0x0
-+#define PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x3
-+#define PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x1
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x2
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0xc
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2
-+#define PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0xe0
-+#define PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5
-+#define PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x100
-+#define PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8
-+#define PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x400
-+#define PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x2000
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x4000
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe
-+#define PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x8000
-+#define PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf
-+#define PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x10000
-+#define PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0xe0000
-+#define PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11
-+#define PPLL_VREG_CFG__pw_pc_bleeder_ac_MASK 0x1
-+#define PPLL_VREG_CFG__pw_pc_bleeder_ac__SHIFT 0x0
-+#define PPLL_VREG_CFG__pw_pc_bleeder_en_MASK 0x2
-+#define PPLL_VREG_CFG__pw_pc_bleeder_en__SHIFT 0x1
-+#define PPLL_VREG_CFG__pw_pc_is_1p2_MASK 0x4
-+#define PPLL_VREG_CFG__pw_pc_is_1p2__SHIFT 0x2
-+#define PPLL_VREG_CFG__pw_pc_reg_obs_sel_MASK 0x18
-+#define PPLL_VREG_CFG__pw_pc_reg_obs_sel__SHIFT 0x3
-+#define PPLL_VREG_CFG__pw_pc_reg_on_mode_MASK 0x60
-+#define PPLL_VREG_CFG__pw_pc_reg_on_mode__SHIFT 0x5
-+#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel_MASK 0x780
-+#define PPLL_VREG_CFG__pw_pc_rlad_tap_sel__SHIFT 0x7
-+#define PPLL_VREG_CFG__pw_pc_reg_off_hi_MASK 0x800
-+#define PPLL_VREG_CFG__pw_pc_reg_off_hi__SHIFT 0xb
-+#define PPLL_VREG_CFG__pw_pc_reg_off_lo_MASK 0x1000
-+#define PPLL_VREG_CFG__pw_pc_reg_off_lo__SHIFT 0xc
-+#define PPLL_VREG_CFG__pw_pc_scale_driver_MASK 0x6000
-+#define PPLL_VREG_CFG__pw_pc_scale_driver__SHIFT 0xd
-+#define PPLL_VREG_CFG__pw_pc_sel_bump_MASK 0x8000
-+#define PPLL_VREG_CFG__pw_pc_sel_bump__SHIFT 0xf
-+#define PPLL_VREG_CFG__pw_pc_sel_rladder_x_MASK 0x10000
-+#define PPLL_VREG_CFG__pw_pc_sel_rladder_x__SHIFT 0x10
-+#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x_MASK 0x20000
-+#define PPLL_VREG_CFG__pw_pc_short_rc_filt_x__SHIFT 0x11
-+#define PPLL_VREG_CFG__pw_pc_vref_pwr_on_MASK 0x40000
-+#define PPLL_VREG_CFG__pw_pc_vref_pwr_on__SHIFT 0x12
-+#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2_MASK 0xff00000
-+#define PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT 0x14
-+#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis_MASK 0x1
-+#define PPLL_MODE_CNTL__pw_pc_refclk_gate_dis__SHIFT 0x0
-+#define PPLL_MODE_CNTL__pw_pc_multi_phase_en_MASK 0xf00
-+#define PPLL_MODE_CNTL__pw_pc_multi_phase_en__SHIFT 0x8
-+#define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 0x30000
-+#define PPLL_MODE_CNTL__reg_tmg_pwr_state__SHIFT 0x10
-+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK 0xffff
-+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac__SHIFT 0x0
-+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int_MASK 0x1ff0000
-+#define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT 0x10
-+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 0xffff
-+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac__SHIFT 0x0
-+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int_MASK 0x1ff0000
-+#define PPLL_FREQ_CTRL1__reg_tmg_fcw1_int__SHIFT 0x10
-+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom_MASK 0xffff
-+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_denom__SHIFT 0x0
-+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac_MASK 0xffff0000
-+#define PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac__SHIFT 0x10
-+#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div_MASK 0x3
-+#define PPLL_FREQ_CTRL3__reg_tmg_refclk_div__SHIFT 0x0
-+#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div_MASK 0x18
-+#define PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div__SHIFT 0x3
-+#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en_MASK 0x40
-+#define PPLL_FREQ_CTRL3__reg_tmg_fracn_en__SHIFT 0x6
-+#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en_MASK 0x100
-+#define PPLL_FREQ_CTRL3__reg_tmg_ssc_en__SHIFT 0x8
-+#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 0x400
-+#define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel__SHIFT 0xa
-+#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en_MASK 0x1000
-+#define PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en__SHIFT 0xc
-+#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol_MASK 0xff0000
-+#define PPLL_FREQ_CTRL3__reg_tmg_tdc_resol__SHIFT 0x10
-+#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1_MASK 0xff000000
-+#define PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1__SHIFT 0x18
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant_MASK 0x3
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant__SHIFT 0x0
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp_MASK 0x3c
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp__SHIFT 0x2
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant_MASK 0x780
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant__SHIFT 0x7
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp_MASK 0xf000
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp__SHIFT 0xc
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res_MASK 0x7e0000
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res__SHIFT 0x11
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res_MASK 0x3000000
-+#define PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res__SHIFT 0x18
-+#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3_MASK 0x3ff
-+#define PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3__SHIFT 0x0
-+#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock_MASK 0x1
-+#define PPLL_CAL_CTRL__pw_pc_bypass_freq_lock__SHIFT 0x0
-+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en_MASK 0x2
-+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_en__SHIFT 0x1
-+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl_MASK 0x1f8
-+#define PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl__SHIFT 0x3
-+#define PPLL_CAL_CTRL__pw_pc_meas_win_sel_MASK 0x600
-+#define PPLL_CAL_CTRL__pw_pc_meas_win_sel__SHIFT 0x9
-+#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis_MASK 0x800
-+#define PPLL_CAL_CTRL__pw_pc_kdco_cal_dis__SHIFT 0xb
-+#define PPLL_CAL_CTRL__pw_pc_kdco_ratio_MASK 0x1fe000
-+#define PPLL_CAL_CTRL__pw_pc_kdco_ratio__SHIFT 0xd
-+#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis_MASK 0x400000
-+#define PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis__SHIFT 0x16
-+#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis_MASK 0x800000
-+#define PPLL_CAL_CTRL__pw_pc_nctl_adj_dis__SHIFT 0x17
-+#define PPLL_CAL_CTRL__pw_pc_refclk_rate_MASK 0xff000000
-+#define PPLL_CAL_CTRL__pw_pc_refclk_rate__SHIFT 0x18
-+#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en_MASK 0x1
-+#define PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en__SHIFT 0x0
-+#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis_MASK 0x4
-+#define PPLL_LOOP_CTRL__pw_pc_fb_slip_dis__SHIFT 0x2
-+#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel_MASK 0x30
-+#define PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel__SHIFT 0x4
-+#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel_MASK 0x180
-+#define PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel__SHIFT 0x7
-+#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel_MASK 0x400
-+#define PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel__SHIFT 0xa
-+#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis_MASK 0x1000
-+#define PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis__SHIFT 0xc
-+#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk_MASK 0x4000
-+#define PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk__SHIFT 0xe
-+#define PPLL_LOOP_CTRL__pw_pc_prbs_en_MASK 0x10000
-+#define PPLL_LOOP_CTRL__pw_pc_prbs_en__SHIFT 0x10
-+#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en_MASK 0x40000
-+#define PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en__SHIFT 0x12
-+#define PPLL_LOOP_CTRL__pw_pc_phase_offset_MASK 0x7f00000
-+#define PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT 0x14
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en_MASK 0x1
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en__SHIFT 0x0
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en_MASK 0x2
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en__SHIFT 0x1
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en_MASK 0x4
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en__SHIFT 0x2
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en_MASK 0x8
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en__SHIFT 0x3
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel_MASK 0x100
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel__SHIFT 0x8
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel_MASK 0x200
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel__SHIFT 0x9
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel_MASK 0x400
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel__SHIFT 0xa
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel_MASK 0x800
-+#define PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel__SHIFT 0xb
-+#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc_MASK 0xc000
-+#define PPLL_REFCLK_CNTL__regs_pw_refdivsrc__SHIFT 0xe
-+#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel_MASK 0x10000
-+#define PPLL_REFCLK_CNTL__regs_pw_ref2core_sel__SHIFT 0x10
-+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel_MASK 0x100
-+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel__SHIFT 0x8
-+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel_MASK 0x200
-+#define PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel__SHIFT 0x9
-+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel_MASK 0x400
-+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel__SHIFT 0xa
-+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel_MASK 0x800
-+#define PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel__SHIFT 0xb
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en_MASK 0x1000
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_en__SHIFT 0xc
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel_MASK 0x2000
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel__SHIFT 0xd
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel_MASK 0x4000
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel__SHIFT 0xe
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel_MASK 0x8000
-+#define PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel__SHIFT 0xf
-+#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel_MASK 0x30000
-+#define PPLL_CLKOUT_CNTL__regs_pw_refclk_sel__SHIFT 0x10
-+#define PPLL_CLKOUT_CNTL__regs_cc_resetb_MASK 0x100000
-+#define PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT 0x14
-+#define PPLL_DFT_CNTL__regs_pw_obs_en_MASK 0x1
-+#define PPLL_DFT_CNTL__regs_pw_obs_en__SHIFT 0x0
-+#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1_MASK 0x6
-+#define PPLL_DFT_CNTL__regs_pw_obs_div_sel_1__SHIFT 0x1
-+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 0xf0
-+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1__SHIFT 0x4
-+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2_MASK 0xf00
-+#define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2__SHIFT 0x8
-+#define PPLL_DFT_CNTL__regs_pw_obs_sel_MASK 0x3000
-+#define PPLL_DFT_CNTL__regs_pw_obs_sel__SHIFT 0xc
-+#define PPLL_ANALOG_CNTL__regs_pw_spare_MASK 0xff
-+#define PPLL_ANALOG_CNTL__regs_pw_spare__SHIFT 0x0
-+#define PPLL_POSTDIV__reg_tmg_postdiv_MASK 0xf00
-+#define PPLL_POSTDIV__reg_tmg_postdiv__SHIFT 0x8
-+#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2_MASK 0x1000
-+#define PPLL_POSTDIV__reg_tmg_pixclk_pdiv2__SHIFT 0xc
-+#define PPLL_DEBUG0__pw_pc_phase_jump_trig_MASK 0x2
-+#define PPLL_DEBUG0__pw_pc_phase_jump_trig__SHIFT 0x1
-+#define PPLL_DEBUG0__pw_pc_fine_tdc_dis_MASK 0x4
-+#define PPLL_DEBUG0__pw_pc_fine_tdc_dis__SHIFT 0x2
-+#define PPLL_DEBUG0__pw_pc_coarse_tdc_dis_MASK 0x8
-+#define PPLL_DEBUG0__pw_pc_coarse_tdc_dis__SHIFT 0x3
-+#define PPLL_DEBUG0__pw_pc_alt_nctl_en_MASK 0x10
-+#define PPLL_DEBUG0__pw_pc_alt_nctl_en__SHIFT 0x4
-+#define PPLL_DEBUG0__pw_pc_alt_nctl_MASK 0x1ffffe0
-+#define PPLL_DEBUG0__pw_pc_alt_nctl__SHIFT 0x5
-+#define PPLL_DEBUG0__pw_pc_nctl_coarse_step_dis_MASK 0x2000000
-+#define PPLL_DEBUG0__pw_pc_nctl_coarse_step_dis__SHIFT 0x19
-+#define PPLL_DEBUG0__pw_pc_trig_coarse_step_MASK 0x4000000
-+#define PPLL_DEBUG0__pw_pc_trig_coarse_step__SHIFT 0x1a
-+#define PPLL_DEBUG0__pw_pc_dft_sel_MASK 0x38000000
-+#define PPLL_DEBUG0__pw_pc_dft_sel__SHIFT 0x1b
-+#define PPLL_DEBUG0__pw_pc_dft_capture_MASK 0x40000000
-+#define PPLL_DEBUG0__pw_pc_dft_capture__SHIFT 0x1e
-+#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps_MASK 0x1f
-+#define PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps__SHIFT 0x0
-+#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock_MASK 0x40
-+#define PPLL_OBSERVE0__pw_pc_clear_sticky_lock__SHIFT 0x6
-+#define PPLL_OBSERVE0__pw_pc_lock_det_dis_MASK 0x100
-+#define PPLL_OBSERVE0__pw_pc_lock_det_dis__SHIFT 0x8
-+#define PPLL_OBSERVE0__pw_pc_dco_cfg_MASK 0x3fc00
-+#define PPLL_OBSERVE0__pw_pc_dco_cfg__SHIFT 0xa
-+#define PPLL_OBSERVE0__pw_pc_anaobs_sel_MASK 0xe00000
-+#define PPLL_OBSERVE0__pw_pc_anaobs_sel__SHIFT 0x15
-+#define PPLL_OBSERVE1__pw_pc_digobs_sel_MASK 0xf
-+#define PPLL_OBSERVE1__pw_pc_digobs_sel__SHIFT 0x0
-+#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel_MASK 0x1e0
-+#define PPLL_OBSERVE1__pw_pc_digobs_trig_sel__SHIFT 0x5
-+#define PPLL_OBSERVE1__pw_pc_digobs_div_MASK 0xc00
-+#define PPLL_OBSERVE1__pw_pc_digobs_div__SHIFT 0xa
-+#define PPLL_OBSERVE1__pw_pc_digobs_trig_div_MASK 0x3000
-+#define PPLL_OBSERVE1__pw_pc_digobs_trig_div__SHIFT 0xc
-+#define PPLL_OBSERVE1__reg_tmg_lock_timer_MASK 0x3fff0000
-+#define PPLL_OBSERVE1__reg_tmg_lock_timer__SHIFT 0x10
-+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK_MASK 0x4
-+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK__SHIFT 0x2
-+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT_MASK 0x8
-+#define PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT__SHIFT 0x3
-+#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING_MASK 0x100
-+#define PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING__SHIFT 0x8
-+#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy_MASK 0x200
-+#define PPLL_UPDATE_CNTL__pc_pw_pll_rdy__SHIFT 0x9
-+#define PPLL_UPDATE_CNTL__TieLow1_MASK 0x10000
-+#define PPLL_UPDATE_CNTL__TieLow1__SHIFT 0x10
-+#define PPLL_OBSERVE0_OUT__disppll_core_obsout_MASK 0xffffffff
-+#define PPLL_OBSERVE0_OUT__disppll_core_obsout__SHIFT 0x0
-+#define PPLL_STATUS_DEBUG1__dbg_pll_rdy_MASK 0x1
-+#define PPLL_STATUS_DEBUG1__dbg_pll_rdy__SHIFT 0x0
-+#define PPLL_STATUS_DEBUG1__core_disppll_pwr_ok_vddp_MASK 0x2
-+#define PPLL_STATUS_DEBUG1__core_disppll_pwr_ok_vddp__SHIFT 0x1
-+#define PPLL_STATUS_DEBUG1__core_disppll_rcu_dc_resetb_vddp_MASK 0x4
-+#define PPLL_STATUS_DEBUG1__core_disppll_rcu_dc_resetb_vddp__SHIFT 0x2
-+#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f
-+#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0
-+#define PPLL_DIV_UPDATE_DEBUG__TieLow2_MASK 0x1
-+#define PPLL_DIV_UPDATE_DEBUG__TieLow2__SHIFT 0x0
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_FB_DIV_CHANGED_MASK 0x2
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_FB_DIV_CHANGED__SHIFT 0x1
-+#define PPLL_DIV_UPDATE_DEBUG__dbg_UPDATE_PENDING_MASK 0x4
-+#define PPLL_DIV_UPDATE_DEBUG__dbg_UPDATE_PENDING__SHIFT 0x2
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_CURRENT_STATE_MASK 0x18
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_CURRENT_STATE__SHIFT 0x3
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ENABLE_MASK 0x20
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ENABLE__SHIFT 0x5
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_REQ_MASK 0x40
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_REQ__SHIFT 0x6
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ACK_MASK 0x80
-+#define PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ACK__SHIFT 0x7
-+#define PPLL_STATUS_DEBUG0__obsout_MASK 0xffffffff
-+#define PPLL_STATUS_DEBUG0__obsout__SHIFT 0x0
-+#define COMP_EN_CTL__comp_en_MASK 0x1
-+#define COMP_EN_CTL__comp_en__SHIFT 0x0
-+#define COMP_EN_CTL__comp_en_override_MASK 0x4
-+#define COMP_EN_CTL__comp_en_override__SHIFT 0x2
-+#define COMP_EN_CTL__comp_done_MASK 0x10
-+#define COMP_EN_CTL__comp_done__SHIFT 0x4
-+#define COMP_EN_CTL__zcal_code_override_MASK 0x40
-+#define COMP_EN_CTL__zcal_code_override__SHIFT 0x6
-+#define COMP_EN_CTL__zcal_cal_rtt_MASK 0x80
-+#define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7
-+#define COMP_EN_CTL__zcal_base_en_MASK 0x100
-+#define COMP_EN_CTL__zcal_base_en__SHIFT 0x8
-+#define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x200
-+#define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9
-+#define COMP_EN_CTL__zcal_code_MASK 0x7c00
-+#define COMP_EN_CTL__zcal_code__SHIFT 0xa
-+#define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x10000
-+#define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10
-+#define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x60000
-+#define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11
-+#define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x80000
-+#define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13
-+#define COMP_EN_CTL__dsm_sel_MASK 0xf00000
-+#define COMP_EN_CTL__dsm_sel__SHIFT 0x14
-+#define DPCSTX_PHY_CNTL__DPCS_PHY_RESET_MASK 0x1
-+#define DPCSTX_PHY_CNTL__DPCS_PHY_RESET__SHIFT 0x0
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x1
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x2
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x4
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x8
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX0_EN_MASK 0x10
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX1_EN_MASK 0x20
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX2_EN_MASK 0x40
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX3_EN_MASK 0x80
-+#define DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7
-+#define DPCSTX_TX_CNTL__DPCS_TX_RESYNC_MASK 0x1
-+#define DPCSTX_TX_CNTL__DPCS_TX_RESYNC__SHIFT 0x0
-+#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_EN_MASK 0x2
-+#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_EN__SHIFT 0x1
-+#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN_MASK 0x4
-+#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN__SHIFT 0x2
-+#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE_MASK 0xf0
-+#define DPCSTX_TX_CNTL__DPCS_TX_HIGH_IMP_IDLE__SHIFT 0x4
-+#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_DELAY_MASK 0x700
-+#define DPCSTX_TX_CNTL__DPCS_TX_STAGGERING_DELAY__SHIFT 0x8
-+#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x1000
-+#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
-+#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x2000
-+#define DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
-+#define DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x4000
-+#define DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe
-+#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x10000
-+#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10
-+#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x20000
-+#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11
-+#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_WR_START_DELAY_MASK 0xf00000
-+#define DPCSTX_TX_CNTL__DPCS_TX_FIFO_WR_START_DELAY__SHIFT 0x14
-+#define DPCSTX_TX_CNTL__DPCS_TX_DVI_LINK_MODE_MASK 0x3000000
-+#define DPCSTX_TX_CNTL__DPCS_TX_DVI_LINK_MODE__SHIFT 0x18
-+#define DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000
-+#define DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f
-+#define DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0xf
-+#define DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0
-+#define DPCSTX_CBUS_CNTL__DPCS_PHY_MASTER_REQ_DELAY_MASK 0xff00
-+#define DPCSTX_CBUS_CNTL__DPCS_PHY_MASTER_REQ_DELAY__SHIFT 0x8
-+#define DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000
-+#define DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f
-+#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_OVERFLOW_MASK 0x1
-+#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0
-+#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_ERROR_CLR_MASK 0x2
-+#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_ERROR_CLR__SHIFT 0x1
-+#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_ERROR_MASK_MASK 0x10
-+#define DPCSTX_REG_ERROR_STATUS__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX0_FIFO_ERROR_MASK 0x1
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX0_FIFO_ERROR__SHIFT 0x0
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX1_FIFO_ERROR_MASK 0x2
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX1_FIFO_ERROR__SHIFT 0x1
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX2_FIFO_ERROR_MASK 0x4
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX2_FIFO_ERROR__SHIFT 0x2
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX3_FIFO_ERROR_MASK 0x8
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX3_FIFO_ERROR__SHIFT 0x3
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_ERROR_CLR_MASK 0x100
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_ERROR_CLR__SHIFT 0x8
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_FIFO_ERROR_MASK_MASK 0x1000
-+#define DPCSTX_TX_ERROR_STATUS__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0xc
-+#define DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x3ffff
-+#define DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0
-+#define DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xffffffff
-+#define DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0
-+#define DPCSTX_INDEX_MODE_ADDR__DPCS_INDEX_MODE_ADDR_MASK 0x3ffff
-+#define DPCSTX_INDEX_MODE_ADDR__DPCS_INDEX_MODE_ADDR__SHIFT 0x0
-+#define DPCSTX_INDEX_MODE_DATA__DPCS_INDEX_MODE_DATA_MASK 0xffffffff
-+#define DPCSTX_INDEX_MODE_DATA__DPCS_INDEX_MODE_DATA__SHIFT 0x0
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x1
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x6
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x38
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x3
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CLOCK_SEL_MASK 0x700
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CLOCK_SEL__SHIFT 0x8
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_BLOCK_SEL_MASK 0x3800
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_BLOCK_SEL__SHIFT 0xb
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x4000
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe
-+#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x10000
-+#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0xe0000
-+#define DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x11
-+#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xff000000
-+#define DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18
-+#define DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA_MASK 0xffffffff
-+#define DPCSTX_TEST_DEBUG_DATA__DPCS_TEST_DEBUG_DATA__SHIFT 0x0
-+
-+#endif /* DCE_11_2_SH_MASK_H */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0909-drm-amdgpu-add-ELM-BAF-asic-types.patch b/common/recipes-kernel/linux/files/0909-drm-amdgpu-add-ELM-BAF-asic-types.patch
deleted file mode 100644
index 69460cb7..00000000
--- a/common/recipes-kernel/linux/files/0909-drm-amdgpu-add-ELM-BAF-asic-types.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From dd7591b2861a5af28f14c1d99b9fb7288bcb8e07 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 14 Oct 2015 17:14:16 -0400
-Subject: [PATCH 0909/1110] drm/amdgpu: add ELM/BAF asic types
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-New asic types for ellesmere and baffin.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
- drivers/gpu/drm/amd/include/amd_shared.h   | 2 ++
- 2 files changed, 4 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 356e2ea..42d0efd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -61,6 +61,8 @@ static const char *amdgpu_asic_name[] = {
- 	"FIJI",
- 	"CARRIZO",
- 	"STONEY",
-+	"ELLESMERE",
-+	"BAFFIN",
- 	"LAST",
- };
- 
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index f8afe53..72858a0 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -48,6 +48,8 @@ enum amd_asic_type {
- 	CHIP_FIJI,
- 	CHIP_CARRIZO,
- 	CHIP_STONEY,
-+	CHIP_ELLESMERE,
-+	CHIP_BAFFIN,
- 	CHIP_LAST,
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0910-drm-amdgpu-add-ELM-BAF-DCE11-configs.patch b/common/recipes-kernel/linux/files/0910-drm-amdgpu-add-ELM-BAF-DCE11-configs.patch
deleted file mode 100644
index 28ab318e..00000000
--- a/common/recipes-kernel/linux/files/0910-drm-amdgpu-add-ELM-BAF-DCE11-configs.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 458533fc638acd865b3d3f7d17e0ce234c98a64b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 14 Oct 2015 17:17:15 -0400
-Subject: [PATCH 0910/1110] drm/amdgpu: add ELM/BAF DCE11 configs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add support for the display configuration on elm/baf.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 24 +++++++++++++++++++++++-
- 1 file changed, 23 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 8a616a7..53e338b 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -1580,7 +1580,19 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
- 
- 	adev->mode_info.audio.enabled = true;
- 
--	adev->mode_info.audio.num_pins = 7;
-+	switch (adev->asic_type) {
-+	case CHIP_CARRIZO:
-+		adev->mode_info.audio.num_pins = 7;
-+		break;
-+	case CHIP_ELLESMERE:
-+		adev->mode_info.audio.num_pins = 8;
-+		break;
-+	case CHIP_BAFFIN:
-+		adev->mode_info.audio.num_pins = 6;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
- 
- 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
- 		adev->mode_info.audio.pin[i].channels = -1;
-@@ -2900,6 +2912,16 @@ static int dce_v11_0_early_init(void *handle)
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 9;
- 		break;
-+	case CHIP_ELLESMERE:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		break;
-+	case CHIP_BAFFIN:
-+		adev->mode_info.num_crtc = 5;
-+		adev->mode_info.num_hpd = 5;
-+		adev->mode_info.num_dig = 5;
-+		break;
- 	default:
- 		/* FIXME: not supported yet */
- 		return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0911-drm-amdgpu-update-atombios.h-v2.patch b/common/recipes-kernel/linux/files/0911-drm-amdgpu-update-atombios.h-v2.patch
deleted file mode 100644
index 9bb44c24..00000000
--- a/common/recipes-kernel/linux/files/0911-drm-amdgpu-update-atombios.h-v2.patch
+++ /dev/null
@@ -1,1003 +0,0 @@
-From 402d9982c9f447baa8381a2ce318f6db71d8e9ee Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 00:43:41 -0400
-Subject: [PATCH 0911/1110] drm/amdgpu: update atombios.h (v2)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-update to internal version 893
-
-v2: Pull in gfx_info changes from 898
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/include/atombios.h | 663 ++++++++++++++++++++++++++++++---
- 1 file changed, 619 insertions(+), 44 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
-index eaf451e..296def3 100644
---- a/drivers/gpu/drm/amd/include/atombios.h
-+++ b/drivers/gpu/drm/amd/include/atombios.h
-@@ -79,9 +79,23 @@
- #define ATOM_PPLL0            2
- #define ATOM_PPLL3            3
- 
-+#define ATOM_PHY_PLL0         4
-+#define ATOM_PHY_PLL1         5
-+
- #define ATOM_EXT_PLL1         8
-+#define ATOM_GCK_DFS          8
- #define ATOM_EXT_PLL2         9
-+#define ATOM_FCH_CLK          9
- #define ATOM_EXT_CLOCK        10
-+#define ATOM_DP_DTO           11
-+
-+#define ATOM_COMBOPHY_PLL0    20
-+#define ATOM_COMBOPHY_PLL1    21
-+#define ATOM_COMBOPHY_PLL2    22
-+#define ATOM_COMBOPHY_PLL3    23
-+#define ATOM_COMBOPHY_PLL4    24
-+#define ATOM_COMBOPHY_PLL5    25
-+
- #define ATOM_PPLL_INVALID     0xFF
- 
- #define ENCODER_REFCLK_SRC_P1PLL       0
-@@ -224,6 +238,31 @@ typedef struct _ATOM_ROM_HEADER
-   UCHAR  ucReserved;
- }ATOM_ROM_HEADER;
- 
-+
-+typedef struct _ATOM_ROM_HEADER_V2_1
-+{
-+  ATOM_COMMON_TABLE_HEADER      sHeader;
-+  UCHAR  uaFirmWareSignature[4];    //Signature to distinguish between Atombios and non-atombios,
-+                                    //atombios should init it as "ATOM", don't change the position
-+  USHORT usBiosRuntimeSegmentAddress;
-+  USHORT usProtectedModeInfoOffset;
-+  USHORT usConfigFilenameOffset;
-+  USHORT usCRC_BlockOffset;
-+  USHORT usBIOS_BootupMessageOffset;
-+  USHORT usInt10Offset;
-+  USHORT usPciBusDevInitCode;
-+  USHORT usIoBaseAddress;
-+  USHORT usSubsystemVendorID;
-+  USHORT usSubsystemID;
-+  USHORT usPCI_InfoOffset;
-+  USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
-+  USHORT usMasterDataTableOffset;   //Offest for SW to get all data table offsets, Don't change the position
-+  UCHAR  ucExtendedFunctionCode;
-+  UCHAR  ucReserved;
-+  ULONG  ulPSPDirTableOffset;
-+}ATOM_ROM_HEADER_V2_1;
-+
-+
- //==============================Command Table Portion====================================
- 
- 
-@@ -272,12 +311,12 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
-   USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
-   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
-   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
--  USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
-+  USHORT GetSMUClockInfo;                         //Atomic Table,  used only by Bios
-   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
-   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
-   USHORT UpdateCRTC_DoubleBufferRegisters;       //Atomic Table,  used only by Bios
-   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
--  USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
-+  USHORT SetDCEClock;                            //Atomic Table,  start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK
-   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
-   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
-   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
-@@ -292,7 +331,7 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
-   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
-   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
--  USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
-+  USHORT Gfx_Init;                               //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
-   USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
-   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
-   USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
-@@ -333,6 +372,10 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
- #define LCD1OutputControl                        HW_Misc_Operation
- #define TV1OutputControl                         Gfx_Harvesting
- #define TVEncoderControl                         SMC_Init
-+#define EnableHW_IconCursor                      SetDCEClock
-+#define SetCRTC_Replication                      GetSMUClockInfo
-+
-+#define MemoryRefreshConversion                  Gfx_Init
- 
- typedef struct _ATOM_MASTER_COMMAND_TABLE
- {
-@@ -425,6 +468,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
- #define b3FIRST_TIME_CHANGE_CLOCK                 0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
- #define b3SKIP_SW_PROGRAM_PLL                     0x10       //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
- #define b3DRAM_SELF_REFRESH_EXIT                  0x20       //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path
-+#define b3SRIOV_INIT_BOOT                         0x40       //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
-+#define b3SRIOV_LOAD_UCODE                        0x40       //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
-+#define b3SRIOV_SKIP_ASIC_INIT                    0x02       //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only
- 
- typedef struct _ATOM_COMPUTE_CLOCK_FREQ
- {
-@@ -518,6 +564,33 @@ typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
- //ucPllCntlFlag
- #define SPLL_CNTL_FLAG_VCO_MODE_MASK            0x03
- 
-+typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7
-+{
-+  ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
-+  ULONG   ulReserved[5];
-+}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7;
-+
-+//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
-+#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK            0x0f
-+#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK           0x00
-+#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK                     0x01
-+
-+typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7
-+{
-+  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4  ulClock;         //Output Parameter: ucPostDiv=DFS divider
-+  USHORT  usSclk_fcw_frac;                  //fractional divider of fcw = usSclk_fcw_frac/65536
-+  USHORT  usSclk_fcw_int;                   //integer divider of fcwc
-+  UCHAR   ucSclkPostDiv;                    //PLL post divider = 2^ucSclkPostDiv
-+  UCHAR   ucSclkVcoMode;                    //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
-+  UCHAR   ucSclkPllRange;                   //GreenTable SCLK PLL range entry index ( 0~7 )
-+  UCHAR   ucSscEnable;
-+  USHORT  usSsc_fcw1_frac;                  //fcw1_frac when SSC enable
-+  USHORT  usSsc_fcw1_int;                   //fcw1_int when SSC enable
-+  USHORT  usReserved;
-+  USHORT  usPcc_fcw_int;
-+  USHORT  usSsc_fcw_slew_frac;              //fcw_slew_frac when SSC enable
-+  USHORT  usPcc_fcw_slew_frac;
-+}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7;
- 
- // ucInputFlag
- #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
-@@ -557,12 +630,16 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2
-   ULONG ulReserved;
- }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
- 
-+//Input parameter of DynamicMemorySettingsTable
-+//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM
- typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
- {
-   ATOM_COMPUTE_CLOCK_FREQ ulClock;
-   ULONG ulReserved[2];
- }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
- 
-+//Input parameter of DynamicMemorySettingsTable
-+//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM
- typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
- {
-   ATOM_COMPUTE_CLOCK_FREQ ulClock;
-@@ -570,6 +647,29 @@ typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
-   ULONG ulReserved;
- }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
- 
-+//Input parameter of DynamicMemorySettingsTable ver2.1 and above
-+//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM
-+typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER
-+{
-+  ATOM_COMPUTE_CLOCK_FREQ ulClock;
-+  UCHAR ucMclkDPMState;
-+  UCHAR ucReserved[3];
-+  ULONG ulReserved;
-+}DYNAMICE_MC_DPM_SETTINGS_PARAMETER;
-+
-+//ucMclkDPMState
-+#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE       0
-+#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE    1
-+#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE      2
-+
-+typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1
-+{
-+  DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg;
-+  DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg;
-+  DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg;
-+}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1;
-+
-+
- /****************************************************************************/
- // Structures used by SetEngineClockTable
- /****************************************************************************/
-@@ -584,6 +684,13 @@ typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
-   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
- }SET_ENGINE_CLOCK_PS_ALLOCATION;
- 
-+typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2
-+{
-+  ULONG ulTargetEngineClock;          //In 10Khz unit
-+  COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved;
-+}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2;
-+
-+
- /****************************************************************************/
- // Structures used by SetMemoryClockTable
- /****************************************************************************/
-@@ -827,6 +934,12 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
- #define ATOM_ENCODER_CMD_SETUP                        0x0f
- #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE            0x10
- 
-+// New Command for DIGxEncoderControlTable v1.5
-+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4    0x14
-+#define ATOM_ENCODER_CMD_STREAM_SETUP                 0x0F      //change name ATOM_ENCODER_CMD_SETUP
-+#define ATOM_ENCODER_CMD_LINK_SETUP                   0x11      //internal use, called by other Command Table
-+#define ATOM_ENCODER_CMD_ENCODER_BLANK                0x12      //internal use, called by other Command Table
-+
- // ucStatus
- #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
- #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
-@@ -955,6 +1068,69 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
- #define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
- #define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
- 
-+
-+typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5
-+{
-+  UCHAR ucDigId;           // 0~6 map to DIG0~DIG6
-+  UCHAR ucAction;          // =  ATOM_ENOCODER_CMD_STREAM_SETUP
-+  UCHAR ucDigMode;         // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
-+  UCHAR ucLaneNum;         // Lane number
-+  ULONG ulPixelClock;      // Pixel Clock in 10Khz
-+  UCHAR ucBitPerColor;
-+  UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G  = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
-+  UCHAR ucReserved[2];
-+}ENCODER_STREAM_SETUP_PARAMETERS_V5;
-+
-+typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5
-+{
-+  UCHAR ucDigId;           // 0~6 map to DIG0~DIG6
-+  UCHAR ucAction;          // =  ATOM_ENOCODER_CMD_LINK_SETUP
-+  UCHAR ucDigMode;         // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
-+  UCHAR ucLaneNum;         // Lane number
-+  ULONG ulSymClock;        // Symbol Clock in 10Khz
-+  UCHAR ucHPDSel;
-+  UCHAR ucDigEncoderSel;   // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
-+  UCHAR ucReserved[2];
-+}ENCODER_LINK_SETUP_PARAMETERS_V5;
-+
-+typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5
-+{
-+  UCHAR ucDigId;           // 0~6 map to DIG0~DIG6
-+  UCHAR ucAction;          // = ATOM_ENCODER_CMD_DPLINK_SETUP
-+  UCHAR ucPanelMode;       // =0:     external DP
-+                           // =0x1:   internal DP2
-+                           // =0x11:  internal DP1 NutMeg/Travis DP Translator
-+  UCHAR ucReserved;
-+  ULONG ulReserved[2];
-+}DP_PANEL_MODE_SETUP_PARAMETERS_V5;
-+
-+typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5
-+{
-+  UCHAR ucDigId;           // 0~6 map to DIG0~DIG6
-+  UCHAR ucAction;          // = rest of generic encoder command which does not carry any parameters
-+  UCHAR ucReserved[2];
-+  ULONG ulReserved[2];
-+}ENCODER_GENERIC_CMD_PARAMETERS_V5;
-+
-+//ucDigId
-+#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER                 0x00
-+#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER                 0x01
-+#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER                 0x02
-+#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER                 0x03
-+#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER                 0x04
-+#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER                 0x05
-+#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER                 0x06
-+
-+
-+typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5
-+{
-+  ENCODER_GENERIC_CMD_PARAMETERS_V5  asCmdParam;
-+  ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam;
-+  ENCODER_LINK_SETUP_PARAMETERS_V5  asLinkParam;
-+  DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam;
-+}DIG_ENCODER_CONTROL_PARAMETERS_V5;
-+
-+
- /****************************************************************************/
- // Structures used by UNIPHYTransmitterControlTable
- //                    LVTMATransmitterControlTable
-@@ -1371,6 +1547,49 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
- 
- #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5            DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
- 
-+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6
-+{
-+  UCHAR ucPhyId;           // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
-+  UCHAR ucAction;          // define as ATOM_TRANSMITER_ACTION_xxx
-+  union
-+  {
-+    UCHAR ucDigMode;       // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
-+    UCHAR ucDPLaneSet;     // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
-+  };
-+  UCHAR ucLaneNum;         // Lane number
-+  ULONG ulSymClock;        // Symbol Clock in 10Khz
-+  UCHAR ucHPDSel;          // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
-+  UCHAR ucDigEncoderSel;   // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
-+  UCHAR ucConnObjId;       // Connector Object Id defined in ObjectId.h
-+  UCHAR ucReserved;
-+  ULONG ulReserved;
-+}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6;
-+
-+
-+// ucDigEncoderSel
-+#define ATOM_TRANMSITTER_V6__DIGA_SEL                       0x01
-+#define ATOM_TRANMSITTER_V6__DIGB_SEL                       0x02
-+#define ATOM_TRANMSITTER_V6__DIGC_SEL                       0x04
-+#define ATOM_TRANMSITTER_V6__DIGD_SEL                       0x08
-+#define ATOM_TRANMSITTER_V6__DIGE_SEL                       0x10
-+#define ATOM_TRANMSITTER_V6__DIGF_SEL                       0x20
-+#define ATOM_TRANMSITTER_V6__DIGG_SEL                       0x40
-+
-+// ucDigMode
-+#define ATOM_TRANSMITTER_DIGMODE_V6_DP                      0
-+#define ATOM_TRANSMITTER_DIGMODE_V6_DVI                     2
-+#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI                    3
-+#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST                  5
-+
-+//ucHPDSel
-+#define ATOM_TRANSMITTER_V6_NO_HPD_SEL                      0x00
-+#define ATOM_TRANSMITTER_V6_HPD1_SEL                        0x01
-+#define ATOM_TRANSMITTER_V6_HPD2_SEL                        0x02
-+#define ATOM_TRANSMITTER_V6_HPD3_SEL                        0x03
-+#define ATOM_TRANSMITTER_V6_HPD4_SEL                        0x04
-+#define ATOM_TRANSMITTER_V6_HPD5_SEL                        0x05
-+#define ATOM_TRANSMITTER_V6_HPD6_SEL                        0x06
-+
- 
- /****************************************************************************/
- // Structures used by ExternalEncoderControlTable V1.3
-@@ -1784,6 +2003,101 @@ typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
-   PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
- }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
- 
-+typedef struct _PIXEL_CLOCK_PARAMETERS_V7
-+{
-+    ULONG  ulPixelClock;               // target the pixel clock to drive the CRTC timing in unit of 100Hz.
-+
-+    UCHAR  ucPpll;                     // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
-+    UCHAR  ucTransmitterID;            // ASIC encoder id defined in objectId.h,
-+                                       // indicate which graphic encoder will be used.
-+    UCHAR  ucEncoderMode;              // Encoder mode:
-+    UCHAR  ucMiscInfo;                 // bit[0]= Force program PLL for pixclk
-+                                       // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk )
-+                                       // bit[5:4]= RefClock source for PPLL.
-+                                       //          =0: XTLAIN( default mode )
-+                                       //          =1: pcie
-+                                       //          =2: GENLK
-+    UCHAR  ucCRTC;                     // ATOM_CRTC1~6, indicate the CRTC controller to
-+    UCHAR  ucDeepColorRatio;           // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
-+    UCHAR  ucReserved[2];
-+    ULONG  ulReserved;
-+}PIXEL_CLOCK_PARAMETERS_V7;
-+
-+//ucMiscInfo
-+#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL         0x01
-+#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL             0x02
-+#define PIXEL_CLOCK_V7_MISC_YUV420_MODE             0x04
-+#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN         0x08
-+#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC             0x30
-+#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN      0x00
-+#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE        0x10
-+#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK       0x20
-+
-+//ucDeepColorRatio
-+#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS          0x00      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
-+#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4          0x01      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
-+#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2          0x02      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
-+#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1          0x03      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
-+
-+// SetDCEClockTable input parameter for DCE11.1
-+typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1
-+{
-+  ULONG  ulDISPClkFreq;       // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
-+  UCHAR  ucFlag;              // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
-+  UCHAR  ucCrtc;              // use when enable DCCG pixel clock ucFlag[1]=1
-+  UCHAR  ucPpllId;            // use when enable DCCG pixel clock ucFlag[1]=1
-+  UCHAR  ucDeepColorRatio;    // use when enable DCCG pixel clock ucFlag[1]=1
-+}SET_DCE_CLOCK_PARAMETERS_V1_1;
-+
-+
-+typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1
-+{
-+  SET_DCE_CLOCK_PARAMETERS_V1_1 asParam;
-+  ULONG ulReserved[2];
-+}SET_DCE_CLOCK_PS_ALLOCATION_V1_1;
-+
-+//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag
-+#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK            0x01
-+#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS         0x01
-+#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK           0x02
-+
-+// SetDCEClockTable input parameter for DCE11.2( ELM and BF ) and above
-+typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1
-+{
-+  ULONG  ulDCEClkFreq;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
-+  UCHAR  ucDCEClkType;                               // =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK
-+  UCHAR  ucDCEClkSrc;                                // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
-+  UCHAR  ucDCEClkFlag;                               // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
-+  UCHAR  ucCRTC;                                     // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
-+}SET_DCE_CLOCK_PARAMETERS_V2_1;
-+
-+//ucDCEClkType
-+#define DCE_CLOCK_TYPE_DISPCLK                        0
-+#define DCE_CLOCK_TYPE_DPREFCLK                       1
-+#define DCE_CLOCK_TYPE_PIXELCLK                       2        // used by VBIOS internally, called by SetPixelClockTable
-+
-+//ucDCEClkFlag when ucDCEClkType == DPREFCLK
-+#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK            0x03
-+#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA        0x00
-+#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK           0x01
-+#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE            0x02
-+#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN          0x03
-+
-+//ucDCEClkFlag when ucDCEClkType == PIXCLK
-+#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK      0x03
-+#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS       0x00      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
-+#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4       0x01      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
-+#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2       0x02      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
-+#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1       0x03      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
-+#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE             0x04
-+
-+typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1
-+{
-+  SET_DCE_CLOCK_PARAMETERS_V2_1 asParam;
-+  ULONG ulReserved[2];
-+}SET_DCE_CLOCK_PS_ALLOCATION_V2_1;
-+
-+
- 
- /****************************************************************************/
- // Structures used by AdjustDisplayPllTable
-@@ -2300,6 +2614,11 @@ typedef struct   _SET_VOLTAGE_PARAMETERS_V1_3
- #define VOLTAGE_TYPE_VDDCI                   4
- #define VOLTAGE_TYPE_VDDGFX                  5
- #define VOLTAGE_TYPE_PCC                     6
-+#define VOLTAGE_TYPE_MVPP                    7
-+#define VOLTAGE_TYPE_LEDDPM                  8
-+#define VOLTAGE_TYPE_PCC_MVDD                9
-+#define VOLTAGE_TYPE_PCIE_VDDC               10
-+#define VOLTAGE_TYPE_PCIE_VDDR               11
- 
- #define VOLTAGE_TYPE_GENERIC_I2C_1           0x11
- #define VOLTAGE_TYPE_GENERIC_I2C_2           0x12
-@@ -2396,6 +2715,39 @@ typedef struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
-   USHORT   usTDP_Power;                                  // TDP_Current in unit  of 0.1W
- }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
- 
-+
-+// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
-+typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
-+{
-+  UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
-+  UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
-+  USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
-+  ULONG    ulSCLKFreq;                  // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
-+  ULONG    ulReserved[3];
-+}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3;
-+
-+// New Added from CI Hawaii for EVV feature
-+typedef struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3
-+{
-+  ULONG    ulVoltageLevel;                               // real voltage level in unit of 0.01mv
-+  ULONG    ulReserved[4];
-+}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3;
-+
-+
-+/****************************************************************************/
-+// Structures used by GetSMUClockInfo
-+/****************************************************************************/
-+typedef struct  _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1
-+{
-+  ULONG ulDfsPllOutputFreq:24;
-+  ULONG ucDfsDivider:8;
-+}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1;
-+
-+typedef struct  _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1
-+{
-+  ULONG ulDfsOutputFreq;
-+}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1;
-+
- /****************************************************************************/
- // Structures used by TVEncoderControlTable
- /****************************************************************************/
-@@ -2429,13 +2781,13 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
-   USHORT        PaletteData;              // Only used by BIOS
-   USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info
-   USHORT        DIGTransmitterInfo;       // Internal used by VBIOS only version 3.1
--  USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
-+  USHORT        SMU_Info;                 // Shared by various SW components,latest version 1.1
-   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
-   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600
-   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
-   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
-   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
--  USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
-+  USHORT        GFX_Info;                 // Shared by various SW components,latest version 2.1 will be used from R600
-   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
-   USHORT        GPUVirtualizationInfo;    // Will be obsolete from R600
-   USHORT        SaveRestoreInfo;          // Only used by Bios
-@@ -2455,7 +2807,7 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
-   USHORT        ASIC_ProfilingInfo;       // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
-   USHORT        VoltageObjectInfo;        // Shared by various SW components, latest version 1.1
-   USHORT        PowerSourceInfo;          // Shared by various SW components, latest versoin 1.1
--  USHORT	      ServiceInfo;
-+  USHORT        ServiceInfo;
- }ATOM_MASTER_LIST_OF_DATA_TABLES;
- 
- typedef struct _ATOM_MASTER_DATA_TABLE
-@@ -2469,6 +2821,8 @@ typedef struct _ATOM_MASTER_DATA_TABLE
- #define DAC_Info                 PaletteData
- #define TMDS_Info                DIGTransmitterInfo
- #define CompassionateData        GPUVirtualizationInfo
-+#define AnalogTV_Info            SMU_Info
-+#define ComponentVideoInfo       GFX_Info
- 
- /****************************************************************************/
- // Structure used in MultimediaCapabilityInfoTable
-@@ -4278,10 +4632,15 @@ typedef struct _EXT_DISPLAY_PATH
- #define MAX_NUMBER_OF_EXT_DISPLAY_PATH    7
- 
- //usCaps
--#define  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE               0x01
--#define  EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN             0x02
--#define  EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204          0x04
--#define  EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT     0x08
-+#define  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE               0x0001
-+#define  EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN             0x0002
-+#define  EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK              0x007C
-+#define  EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204          (0x01 << 2 )     //PI redriver chip
-+#define  EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT     (0x02 << 2 )     //TI retimer chip
-+#define  EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175        (0x03 << 2 )     //Parade DP->HDMI recoverter chip
-+
-+
-+
- 
- typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
- {
-@@ -4325,10 +4684,10 @@ typedef struct _ATOM_COMMON_RECORD_HEADER
- #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE          19
- #define ATOM_ENCODER_CAP_RECORD_TYPE                   20
- #define ATOM_BRACKET_LAYOUT_RECORD_TYPE                21
--
-+#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE     22
- 
- //Must be updated when new record type is added,equal to that record definition!
--#define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_ENCODER_CAP_RECORD_TYPE
-+#define ATOM_MAX_OBJECT_RECORD_NUMBER                  ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE
- 
- typedef struct  _ATOM_I2C_RECORD
- {
-@@ -4458,10 +4817,12 @@ typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
-   UCHAR                       ucPadding[2];
- }ATOM_ENCODER_DVO_CF_RECORD;
- 
--// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
--#define ATOM_ENCODER_CAP_RECORD_HBR2                  0x01         // DP1.2 HBR2 is supported by HW encoder
-+// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
-+#define ATOM_ENCODER_CAP_RECORD_HBR2                  0x01         // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
-+#define ATOM_ENCODER_CAP_RECORD_MST_EN                0x01         // from SI, this bit means DP MST is enable or not.
- #define ATOM_ENCODER_CAP_RECORD_HBR2_EN               0x02         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
- #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          0x04         // HDMI2.0 6Gbps enable or not.
-+#define ATOM_ENCODER_CAP_RECORD_HBR3_EN               0x08         // DP1.3 HBR3 is supported by board.
- 
- typedef struct  _ATOM_ENCODER_CAP_RECORD
- {
-@@ -4482,6 +4843,31 @@ typedef struct  _ATOM_ENCODER_CAP_RECORD
-   };
- }ATOM_ENCODER_CAP_RECORD;
- 
-+// Used after SI
-+typedef struct  _ATOM_ENCODER_CAP_RECORD_V2
-+{
-+  ATOM_COMMON_RECORD_HEADER   sheader;
-+  union {
-+    USHORT                    usEncoderCap;
-+    struct {
-+#if ATOM_BIG_ENDIAN
-+      USHORT                  usReserved:12;        // Bit4-15 may be defined for other capability in future
-+      USHORT                  usHBR3En:1;           // bit3 is for DP1.3 HBR3 enable
-+      USHORT                  usHDMI6GEn:1;         // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
-+      USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
-+      USHORT                  usMSTEn:1;            // Bit0 is for DP1.2 MST enable
-+#else
-+      USHORT                  usMSTEn:1;            // Bit0 is for DP1.2 MST enable
-+      USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
-+      USHORT                  usHDMI6GEn:1;         // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
-+      USHORT                  usHBR3En:1;           // bit3 is for DP1.3 HBR3 enable
-+      USHORT                  usReserved:12;        // Bit4-15 may be defined for other capability in future
-+#endif
-+    };
-+  };
-+}ATOM_ENCODER_CAP_RECORD_V2;
-+
-+
- // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
- #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
- #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
-@@ -4554,6 +4940,16 @@ typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
-   USHORT                      usReserved;
- }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
- 
-+
-+typedef struct  _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD
-+{
-+  ATOM_COMMON_RECORD_HEADER   sheader;
-+  // override TMDS capability on this connector when it operate in TMDS mode.  usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
-+  UCHAR                       ucMaxTmdsClkRateIn2_5Mhz;
-+  UCHAR                       ucReserved;
-+} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD;
-+
-+
- typedef struct  _ATOM_CONNECTOR_LAYOUT_INFO
- {
-    USHORT usConnectorObjectId;
-@@ -4657,12 +5053,12 @@ typedef struct _ATOM_VOLTAGE_CONTROL
- #define VOLTAGE_CONTROL_ID_UP1801             0x0C
- #define VOLTAGE_CONTROL_ID_ST6788A            0x0D
- #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2      0x0E
--#define VOLTAGE_CONTROL_ID_AD527x      	      0x0F
--#define VOLTAGE_CONTROL_ID_NCP81022    	      0x10
--#define VOLTAGE_CONTROL_ID_LTC2635			  0x11
--#define VOLTAGE_CONTROL_ID_NCP4208	          0x12
-+#define VOLTAGE_CONTROL_ID_AD527x             0x0F
-+#define VOLTAGE_CONTROL_ID_NCP81022           0x10
-+#define VOLTAGE_CONTROL_ID_LTC2635            0x11
-+#define VOLTAGE_CONTROL_ID_NCP4208            0x12
- #define VOLTAGE_CONTROL_ID_IR35xx             0x13
--#define VOLTAGE_CONTROL_ID_RT9403	          0x14
-+#define VOLTAGE_CONTROL_ID_RT9403             0x14
- 
- #define VOLTAGE_CONTROL_ID_GENERIC_I2C        0x40
- 
-@@ -4784,11 +5180,38 @@ typedef struct  _ATOM_SVID2_VOLTAGE_OBJECT_V3
-    ULONG    ulReserved;
- }ATOM_SVID2_VOLTAGE_OBJECT_V3;
- 
-+
-+
-+typedef struct  _ATOM_MERGED_VOLTAGE_OBJECT_V3
-+{
-+   ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_MERGED_POWER
-+   UCHAR    ucMergedVType;                   // VDDC/VDCCI/....
-+   UCHAR    ucReserved[3];
-+}ATOM_MERGED_VOLTAGE_OBJECT_V3;
-+
-+
-+typedef struct _ATOM_EVV_DPM_INFO
-+{
-+  ULONG ulDPMSclk;            // DPM state SCLK
-+  USHORT usVAdjOffset;        // Adjust Voltage offset in unit of mv
-+  UCHAR ucDPMTblVIndex;       // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable
-+  UCHAR ucDPMState;           // DPMState0~7
-+} ATOM_EVV_DPM_INFO;
-+
-+// ucVoltageMode = VOLTAGE_OBJ_EVV
-+typedef struct  _ATOM_EVV_VOLTAGE_OBJECT_V3
-+{
-+  ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_SVID2
-+  ATOM_EVV_DPM_INFO asEvvDpmList[8];
-+}ATOM_EVV_VOLTAGE_OBJECT_V3;
-+
-+
- typedef union _ATOM_VOLTAGE_OBJECT_V3{
-   ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
-   ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
-   ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
-   ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
-+  ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj;
- }ATOM_VOLTAGE_OBJECT_V3;
- 
- typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V3_1
-@@ -4963,7 +5386,11 @@ typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_3
-   ULONG  ulLkgEncodeMax;
-   ULONG  ulLkgEncodeMin;
-   ULONG  ulEfuseLogisticAlpha;
-+
-+  union{
-   USHORT usPowerDpm0;
-+  USHORT usParamNegFlag;          //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m  max is postive
-+  };
-   USHORT usPowerDpm1;
-   USHORT usPowerDpm2;
-   USHORT usPowerDpm3;
-@@ -5067,6 +5494,86 @@ typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_4
-   ULONG ulReserved[8];            // Reserved for future ASIC
- }ATOM_ASIC_PROFILING_INFO_V3_4;
- 
-+// for Ellemser/Baffin speed EVV algorithm
-+typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_5
-+{
-+  ATOM_COMMON_TABLE_HEADER         asHeader;
-+  ULONG  ulMaxVddc;               //Maximum voltage for all parts, in unit of 0.01mv
-+  ULONG  ulMinVddc;               //Minimum voltage for all parts, in unit of 0.01mv
-+  USHORT usLkgEuseIndex;          //Efuse Lkg_FT address ( BYTE address )
-+  UCHAR  ucLkgEfuseBitLSB;        //Efuse Lkg_FT bit shift in 32bit DWORD
-+  UCHAR  ucLkgEfuseLength;        //Efuse Lkg_FT length
-+  ULONG  ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )
-+  ULONG  ulLkgEncodeMax;          //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
-+  ULONG  ulLkgEncodeMin;          //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
-+  EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1.
-+  ULONG  ulEvvDefaultVddc;        //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>
-+  ULONG  ulEvvNoCalcVddc;         //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>
-+  ULONG  ulSpeed_Model;           //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>
-+  ULONG  ulSM_A0;                 //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>
-+  ULONG  ulSM_A1;                 //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>
-+  ULONG  ulSM_A2;                 //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>
-+  ULONG  ulSM_A3;                 //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>
-+  ULONG  ulSM_A4;                 //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>
-+  ULONG  ulSM_A5;                 //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>
-+  ULONG  ulSM_A6;                 //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>
-+  ULONG  ulSM_A7;                 //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>
-+  UCHAR  ucSM_A0_sign;            //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
-+  UCHAR  ucSM_A1_sign;            //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
-+  UCHAR  ucSM_A2_sign;            //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
-+  UCHAR  ucSM_A3_sign;            //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
-+  UCHAR  ucSM_A4_sign;            //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
-+  UCHAR  ucSM_A5_sign;            //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
-+  UCHAR  ucSM_A6_sign;            //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>
-+  UCHAR  ucSM_A7_sign;            //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>
-+  ULONG  ulMargin_RO_a;           //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
-+  ULONG  ulMargin_RO_b;           //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
-+  ULONG  ulMargin_RO_c;           //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"
-+  ULONG  ulMargin_fixed;          //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
-+  ULONG  ulMargin_Fmax_mean;      //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/>
-+  ULONG  ulMargin_plat_mean;      //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>
-+  ULONG  ulMargin_Fmax_sigma;     //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>
-+  ULONG  ulMargin_plat_sigma;     //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>
-+  ULONG  ulMargin_DC_sigma;       //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>
-+  ULONG  ulReserved[12];
-+}ATOM_ASIC_PROFILING_INFO_V3_5;
-+
-+
-+typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
-+  ULONG  ulMaxSclkFreq;
-+  UCHAR  ucVco_setting;      // 1: 3-6GHz, 3: 2-4GHz
-+  UCHAR  ucPostdiv;          // divide by 2^n
-+  USHORT ucFcw_pcc;
-+  USHORT ucFcw_trans_upper;
-+  USHORT ucRcw_trans_lower;
-+}ATOM_SCLK_FCW_RANGE_ENTRY_V1;
-+
-+
-+// SMU_InfoTable for Ellesmere/Baffin
-+typedef struct  _ATOM_SMU_INFO_V2_1
-+{
-+  ATOM_COMMON_TABLE_HEADER         asHeader;
-+  UCHAR ucSclkEntryNum;            // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
-+  UCHAR ucReserved[3];
-+  ATOM_SCLK_FCW_RANGE_ENTRY_V1     asSclkFcwRangeEntry[8];
-+}ATOM_SMU_INFO_V2_1;
-+
-+
-+// GFX_InfoTable for Polaris10/Polaris11
-+typedef struct  _ATOM_GFX_INFO_V2_1
-+{
-+  ATOM_COMMON_TABLE_HEADER asHeader;
-+  UCHAR GfxIpMinVer;
-+  UCHAR GfxIpMajVer;
-+  UCHAR max_shader_engines;
-+  UCHAR max_tile_pipes;
-+  UCHAR max_cu_per_sh;
-+  UCHAR max_sh_per_se;
-+  UCHAR max_backends_per_se;
-+  UCHAR max_texture_channel_caches;
-+}ATOM_GFX_INFO_V2_1;
-+
-+
- typedef struct _ATOM_POWER_SOURCE_OBJECT
- {
-    UCHAR  ucPwrSrcId;                                   // Power source
-@@ -5765,14 +6272,6 @@ sExtDispConnInfo:                 Display connector information table provided t
- 
- **********************************************************************************************************************/
- 
--// this Table is used for Kaveri/Kabini APU
--typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
--{
--  ATOM_INTEGRATED_SYSTEM_INFO_V1_8    sIntegratedSysInfo;       // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
--  ULONG                               ulPowerplayTable[128];    // Update comments here to link new powerplay table definition structure
--}ATOM_FUSION_SYSTEM_INFO_V2;
--
--
- typedef struct _ATOM_I2C_REG_INFO
- {
-   UCHAR ucI2cRegIndex;
-@@ -5859,7 +6358,50 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
- #define EDP_VS_VARIABLE_PREM_MODE           5
- 
- 
--// this IntegrateSystemInfoTable is used for Carrizo
-+// ulGPUCapInfo
-+#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT                         0x08
-+#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS                               0x10
-+//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
-+#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE                         0x00010000
-+//ulGPUCapInfo[18]=1 indicate the IOMMU is not available
-+#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE                                    0x00040000
-+//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened.
-+#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE                             0x00080000
-+
-+
-+typedef struct _DPHY_TIMING_PARA
-+{
-+    UCHAR  ucProfileID;       // SENSOR_PROFILES
-+    ULONG  ucPara;
-+} DPHY_TIMING_PARA;
-+
-+typedef struct _DPHY_ELEC_PARA
-+{
-+    USHORT  usPara[3];
-+} DPHY_ELEC_PARA;
-+
-+typedef struct _CAMERA_MODULE_INFO
-+{
-+    UCHAR    ucID;                    // 0: Rear, 1: Front right of user, 2: Front left of user
-+    UCHAR    strModuleName[8];
-+    DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor
-+} CAMERA_MODULE_INFO;
-+
-+typedef struct _FLASHLIGHT_INFO
-+{
-+    UCHAR    ucID;         // 0: Rear, 1: Front
-+    UCHAR    strName[8];
-+} FLASHLIGHT_INFO;
-+
-+typedef struct _CAMERA_DATA
-+{
-+    ULONG                   ulVersionCode;
-+    CAMERA_MODULE_INFO      asCameraInfo[3];     // Assuming 3 camera sensors max
-+    FLASHLIGHT_INFO         asFlashInfo;      // Assuming 1 flashlight max
-+    DPHY_ELEC_PARA          asDphyElecPara;
-+    ULONG                   ulCrcVal;         // CRC
-+}CAMERA_DATA;
-+
- typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
- {
-   ATOM_COMMON_TABLE_HEADER   sHeader;
-@@ -5883,7 +6425,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
-   USHORT usPanelRefreshRateRange;
-   UCHAR  ucMemoryType;
-   UCHAR  ucUMAChannelNumber;
--  UCHAR  strVBIOSMsg[40];
-+  ULONG  ulMsgReserved[10];
-   ATOM_TDP_CONFIG  asTdpConfig;
-   ULONG  ulReserved[7];
-   ATOM_CLK_VOLT_CAPABILITY_V2   sDispClkVoltageMapping[8];
-@@ -5925,8 +6467,27 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
-   UCHAR  ucEDPv1_4VSMode;
-   UCHAR  ucReserved2;
-   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
-+  CAMERA_DATA asCameraInfo;
-+  ULONG  ulReserved8[29];
- }ATOM_INTEGRATED_SYSTEM_INFO_V1_10;
- 
-+
-+// this Table is used for Kaveri/Kabini APU
-+typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
-+{
-+  ATOM_INTEGRATED_SYSTEM_INFO_V1_8    sIntegratedSysInfo;       // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
-+  ULONG                               ulPowerplayTable[128];    // Update comments here to link new powerplay table definition structure
-+}ATOM_FUSION_SYSTEM_INFO_V2;
-+
-+
-+typedef struct _ATOM_FUSION_SYSTEM_INFO_V3
-+{
-+  ATOM_INTEGRATED_SYSTEM_INFO_V1_10   sIntegratedSysInfo;           // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
-+  ULONG                               ulPowerplayTable[192];        // Reserve 768 bytes space for PowerPlayInfoTable
-+}ATOM_FUSION_SYSTEM_INFO_V3;
-+
-+#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800
-+
- /**************************************************************************/
- // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
- //Memory SS Info Table
-@@ -6193,12 +6754,12 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
- #define ATOM_S3_DFP1_ACTIVE             0x00000008L
- #define ATOM_S3_CRT2_ACTIVE             0x00000010L
- #define ATOM_S3_LCD2_ACTIVE             0x00000020L
--#define ATOM_S3_DFP6_ACTIVE                     0x00000040L
-+#define ATOM_S3_DFP6_ACTIVE             0x00000040L
- #define ATOM_S3_DFP2_ACTIVE             0x00000080L
- #define ATOM_S3_CV_ACTIVE               0x00000100L
--#define ATOM_S3_DFP3_ACTIVE                     0x00000200L
--#define ATOM_S3_DFP4_ACTIVE                     0x00000400L
--#define ATOM_S3_DFP5_ACTIVE                     0x00000800L
-+#define ATOM_S3_DFP3_ACTIVE             0x00000200L
-+#define ATOM_S3_DFP4_ACTIVE             0x00000400L
-+#define ATOM_S3_DFP5_ACTIVE             0x00000800L
- 
- 
- #define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
-@@ -6215,9 +6776,9 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
- #define ATOM_S3_DFP6_CRTC_ACTIVE        0x00400000L
- #define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
- #define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
--#define ATOM_S3_DFP3_CRTC_ACTIVE            0x02000000L
--#define ATOM_S3_DFP4_CRTC_ACTIVE            0x04000000L
--#define ATOM_S3_DFP5_CRTC_ACTIVE            0x08000000L
-+#define ATOM_S3_DFP3_CRTC_ACTIVE        0x02000000L
-+#define ATOM_S3_DFP4_CRTC_ACTIVE        0x04000000L
-+#define ATOM_S3_DFP5_CRTC_ACTIVE        0x08000000L
- 
- 
- #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
-@@ -6238,9 +6799,9 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
- #define ATOM_S3_DFP6_ACTIVEb0           0x40
- #define ATOM_S3_DFP2_ACTIVEb0           0x80
- #define ATOM_S3_CV_ACTIVEb1             0x01
--#define ATOM_S3_DFP3_ACTIVEb1                  0x02
--#define ATOM_S3_DFP4_ACTIVEb1                  0x04
--#define ATOM_S3_DFP5_ACTIVEb1                  0x08
-+#define ATOM_S3_DFP3_ACTIVEb1           0x02
-+#define ATOM_S3_DFP4_ACTIVEb1           0x04
-+#define ATOM_S3_DFP5_ACTIVEb1           0x08
- 
- 
- #define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
-@@ -6254,9 +6815,9 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
- #define ATOM_S3_DFP6_CRTC_ACTIVEb2      0x40
- #define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
- #define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
--#define ATOM_S3_DFP3_CRTC_ACTIVEb3         0x02
--#define ATOM_S3_DFP4_CRTC_ACTIVEb3         0x04
--#define ATOM_S3_DFP5_CRTC_ACTIVEb3         0x08
-+#define ATOM_S3_DFP3_CRTC_ACTIVEb3      0x02
-+#define ATOM_S3_DFP4_CRTC_ACTIVEb3      0x04
-+#define ATOM_S3_DFP5_CRTC_ACTIVEb3      0x08
- 
- 
- #define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
-@@ -6878,15 +7439,18 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1
- #define _32Mx16             0x32
- #define _32Mx32             0x33
- #define _32Mx128            0x35
--#define _64Mx32             0x43
- #define _64Mx8              0x41
- #define _64Mx16             0x42
-+#define _64Mx32             0x43
-+#define _64Mx128            0x45
- #define _128Mx8             0x51
- #define _128Mx16            0x52
- #define _128Mx32            0x53
- #define _256Mx8             0x61
- #define _256Mx16            0x62
-+#define _256Mx32            0x63
- #define _512Mx8             0x71
-+#define _512Mx16            0x72
- 
- 
- #define SAMSUNG             0x1
-@@ -7407,6 +7971,17 @@ typedef struct _ATOM_MEMORY_TRAINING_INFO
- }ATOM_MEMORY_TRAINING_INFO;
- 
- 
-+typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1
-+{
-+   ATOM_COMMON_TABLE_HEADER   sHeader;
-+   ULONG                      ulMCUcodeVersion;
-+   USHORT                     usMCIOInitLen;         //len of ATOM_REG_INIT_SETTING array
-+   USHORT                     usMCUcodeLen;          //len of ATOM_MC_UCODE_DATA array
-+   USHORT                     usMCIORegInitOffset;   //point of offset of ATOM_REG_INIT_SETTING array
-+   USHORT                     usMCUcodeOffset;       //point of offset of MC uCode ULONG array.
-+}ATOM_MEMORY_TRAINING_INFO_V3_1;
-+
-+
- typedef struct SW_I2C_CNTL_DATA_PARAMETERS
- {
-   UCHAR    ucControl;
-@@ -7623,7 +8198,7 @@ typedef struct _ASIC_TRANSMITTER_INFO
- {
-    USHORT usTransmitterObjId;
-    USHORT usSupportDevice;
--  UCHAR  ucTransmitterCmdTblId;
-+   UCHAR  ucTransmitterCmdTblId;
-    UCHAR  ucConfig;
-    UCHAR  ucEncoderID;                //available 1st encoder ( default )
-    UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0912-drm-amdgpu-atom-add-SetDCEClock-helper.patch b/common/recipes-kernel/linux/files/0912-drm-amdgpu-atom-add-SetDCEClock-helper.patch
deleted file mode 100644
index 563da0f6..00000000
--- a/common/recipes-kernel/linux/files/0912-drm-amdgpu-atom-add-SetDCEClock-helper.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 54371792a70486399433d75c04cf30613f656898 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 01:24:49 -0400
-Subject: [PATCH 0912/1110] drm/amdgpu/atom: add SetDCEClock helper
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-New cmd table for ELM/BAF for setting the dispclock or
-dprefclock.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 45 +++++++++++++++++++++++++++++-
- drivers/gpu/drm/amd/amdgpu/atombios_crtc.h |  2 ++
- 2 files changed, 46 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
-index 49aa350..bd6c530 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
-@@ -467,7 +467,7 @@ union set_pixel_clock {
-  * required disp clk.
-  */
- void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
--				    u32 dispclk)
-+					   u32 dispclk)
- {
- 	u8 frev, crev;
- 	int index;
-@@ -510,6 +510,49 @@ void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
- 	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
- }
- 
-+union set_dce_clock {
-+	SET_DCE_CLOCK_PS_ALLOCATION_V1_1 v1_1;
-+	SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1;
-+};
-+
-+u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,
-+				       u32 freq, u8 clk_type, u8 clk_src)
-+{
-+	u8 frev, crev;
-+	int index;
-+	union set_dce_clock args;
-+	u32 ret_freq = 0;
-+
-+	memset(&args, 0, sizeof(args));
-+
-+	index = GetIndexIntoMasterTable(COMMAND, SetDCEClock);
-+	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
-+				   &crev))
-+		return 0;
-+
-+	switch (frev) {
-+	case 2:
-+		switch (crev) {
-+		case 1:
-+			args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */
-+			args.v2_1.asParam.ucDCEClkType = clk_type;
-+			args.v2_1.asParam.ucDCEClkSrc = clk_src;
-+			amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
-+			ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10;
-+			break;
-+		default:
-+			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
-+			return 0;
-+		}
-+		break;
-+	default:
-+		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
-+		return 0;
-+	}
-+
-+	return ret_freq;
-+}
-+
- static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
- {
- 	if (ENCODER_MODE_IS_DP(encoder_mode)) {
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h
-index c670833..0eeda8e 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h
-@@ -37,6 +37,8 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
- 				  struct drm_display_mode *mode);
- void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
- 				    u32 dispclk);
-+u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,
-+				       u32 freq, u8 clk_type, u8 clk_src);
- void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
- 			       u32 crtc_id,
- 			       int pll_id,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch b/common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch
deleted file mode 100644
index 4adfb3b3..00000000
--- a/common/recipes-kernel/linux/files/0913-drm-amdgpu-atom-add-support-for-new-SetPixelClock-ta.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 29c91eca599b8d27ff614a0d8979b3a1bf6abd65 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 02:05:31 -0400
-Subject: [PATCH 0913/1110] drm/amdgpu/atom: add support for new SetPixelClock
- table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-New version of the SetPixelClock table for elm/baf.  The
-new table calculates the pll dividers and handles spread
-spectrum calculations and setup.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 53 +++++++++++++++++++++++-------
- 1 file changed, 41 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
-index bd6c530..49a39b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
-@@ -461,6 +461,7 @@ union set_pixel_clock {
- 	PIXEL_CLOCK_PARAMETERS_V3 v3;
- 	PIXEL_CLOCK_PARAMETERS_V5 v5;
- 	PIXEL_CLOCK_PARAMETERS_V6 v6;
-+	PIXEL_CLOCK_PARAMETERS_V7 v7;
- };
- 
- /* on DCE5, make sure the voltage is high enough to support the
-@@ -566,18 +567,18 @@ static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
- }
- 
- void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
--			       u32 crtc_id,
--			       int pll_id,
--			       u32 encoder_mode,
--			       u32 encoder_id,
--			       u32 clock,
--			       u32 ref_div,
--			       u32 fb_div,
--			       u32 frac_fb_div,
--			       u32 post_div,
--			       int bpc,
--			       bool ss_enabled,
--			       struct amdgpu_atom_ss *ss)
-+				      u32 crtc_id,
-+				      int pll_id,
-+				      u32 encoder_mode,
-+				      u32 encoder_id,
-+				      u32 clock,
-+				      u32 ref_div,
-+				      u32 fb_div,
-+				      u32 frac_fb_div,
-+				      u32 post_div,
-+				      int bpc,
-+				      bool ss_enabled,
-+				      struct amdgpu_atom_ss *ss)
- {
- 	struct drm_device *dev = crtc->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
-@@ -695,6 +696,34 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
- 			args.v6.ucEncoderMode = encoder_mode;
- 			args.v6.ucPpll = pll_id;
- 			break;
-+		case 7:
-+			args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */
-+			args.v7.ucMiscInfo = 0;
-+			if ((encoder_mode == ATOM_ENCODER_MODE_DVI) &&
-+			    (clock > 165000))
-+				args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
-+			args.v7.ucCRTC = crtc_id;
-+			if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
-+				switch (bpc) {
-+				case 8:
-+				default:
-+					args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
-+					break;
-+				case 10:
-+					args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
-+					break;
-+				case 12:
-+					args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
-+					break;
-+				case 16:
-+					args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
-+					break;
-+				}
-+			}
-+			args.v7.ucTransmitterID = encoder_id;
-+			args.v7.ucEncoderMode = encoder_mode;
-+			args.v7.ucPpll = pll_id;
-+			break;
- 		default:
- 			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
- 			return;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0914-drm-amdgpu-atom-add-support-for-new-DIGxEncoderContr.patch b/common/recipes-kernel/linux/files/0914-drm-amdgpu-atom-add-support-for-new-DIGxEncoderContr.patch
deleted file mode 100644
index d30858cb..00000000
--- a/common/recipes-kernel/linux/files/0914-drm-amdgpu-atom-add-support-for-new-DIGxEncoderContr.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 626eec7371d0431e3f446ed843e4b63b2779040d Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 14:49:53 -0400
-Subject: [PATCH 0914/1110] drm/amdgpu/atom: add support for new
- DIGxEncoderControl cmd table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-New digital encoder setup table for elm/baf.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 42 ++++++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
-index 1cd6de5..3481962 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
-@@ -567,6 +567,7 @@ union dig_encoder_control {
- 	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
- 	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
- 	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V5 v5;
- };
- 
- void
-@@ -694,6 +695,47 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
- 			else
- 				args.v4.ucHPD_ID = hpd_id + 1;
- 			break;
-+		case 5:
-+			switch (action) {
-+			case ATOM_ENCODER_CMD_SETUP_PANEL_MODE:
-+				args.v5.asDPPanelModeParam.ucAction = action;
-+				args.v5.asDPPanelModeParam.ucPanelMode = panel_mode;
-+				args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder;
-+				break;
-+			case ATOM_ENCODER_CMD_STREAM_SETUP:
-+				args.v5.asStreamParam.ucAction = action;
-+				args.v5.asStreamParam.ucDigId = dig->dig_encoder;
-+				args.v5.asStreamParam.ucDigMode =
-+					amdgpu_atombios_encoder_get_encoder_mode(encoder);
-+				if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode))
-+					args.v5.asStreamParam.ucLaneNum = dp_lane_count;
-+				else if (amdgpu_dig_monitor_is_duallink(encoder,
-+									amdgpu_encoder->pixel_clock))
-+					args.v5.asStreamParam.ucLaneNum = 8;
-+				else
-+					args.v5.asStreamParam.ucLaneNum = 4;
-+				args.v5.asStreamParam.ulPixelClock =
-+					cpu_to_le32(amdgpu_encoder->pixel_clock / 10);
-+				args.v5.asStreamParam.ucBitPerColor =
-+					amdgpu_atombios_encoder_get_bpc(encoder);
-+				args.v5.asStreamParam.ucLinkRateIn270Mhz = dp_clock / 27000;
-+				break;
-+			case ATOM_ENCODER_CMD_DP_LINK_TRAINING_START:
-+			case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1:
-+			case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2:
-+			case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3:
-+			case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4:
-+			case ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE:
-+			case ATOM_ENCODER_CMD_DP_VIDEO_OFF:
-+			case ATOM_ENCODER_CMD_DP_VIDEO_ON:
-+				args.v5.asCmdParam.ucAction = action;
-+				args.v5.asCmdParam.ucDigId = dig->dig_encoder;
-+				break;
-+			default:
-+				DRM_ERROR("Unsupported action 0x%x\n", action);
-+				break;
-+			}
-+			break;
- 		default:
- 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
- 			break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch b/common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch
deleted file mode 100644
index dc2fde6e..00000000
--- a/common/recipes-kernel/linux/files/0915-drm-amdgpu-atom-add-support-for-new-UNIPHYTransmitte.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 615383736e7c94eeaa266c7aeeabef70f48411ed Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 15:08:30 -0400
-Subject: [PATCH 0915/1110] drm/amdgpu/atom: add support for new
- UNIPHYTransmitterContol cmd table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-New uniphy transmitter setup table for elm/baf.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 51 +++++++++++++++++++++++++-
- 1 file changed, 50 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
-index 3481962..48b6bd6 100644
---- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
-+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
-@@ -756,11 +756,12 @@ union dig_transmitter_control {
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
- 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 v6;
- };
- 
- void
- amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action,
--				       uint8_t lane_num, uint8_t lane_set)
-+					      uint8_t lane_num, uint8_t lane_set)
- {
- 	struct drm_device *dev = encoder->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
-@@ -1112,6 +1113,54 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
- 			args.v5.ucDigEncoderSel = 1 << dig_encoder;
- 			args.v5.ucDPLaneSet = lane_set;
- 			break;
-+		case 6:
-+			args.v6.ucAction = action;
-+			if (is_dp)
-+				args.v6.ulSymClock = cpu_to_le32(dp_clock / 10);
-+			else
-+				args.v6.ulSymClock = cpu_to_le32(amdgpu_encoder->pixel_clock / 10);
-+
-+			switch (amdgpu_encoder->encoder_id) {
-+			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-+				if (dig->linkb)
-+					args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYB;
-+				else
-+					args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYA;
-+				break;
-+			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-+				if (dig->linkb)
-+					args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYD;
-+				else
-+					args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYC;
-+				break;
-+			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-+				if (dig->linkb)
-+					args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYF;
-+				else
-+					args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYE;
-+				break;
-+			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
-+				args.v6.ucPhyId = ATOM_PHY_ID_UNIPHYG;
-+				break;
-+			}
-+			if (is_dp)
-+				args.v6.ucLaneNum = dp_lane_count;
-+			else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))
-+				args.v6.ucLaneNum = 8;
-+			else
-+				args.v6.ucLaneNum = 4;
-+			args.v6.ucConnObjId = connector_object_id;
-+			if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH)
-+				args.v6.ucDPLaneSet = lane_set;
-+			else
-+				args.v6.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
-+
-+			if (hpd_id == AMDGPU_HPD_NONE)
-+				args.v6.ucHPDSel = 0;
-+			else
-+				args.v6.ucHPDSel = hpd_id + 1;
-+			args.v6.ucDigEncoderSel = 1 << dig_encoder;
-+			break;
- 		default:
- 			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
- 			break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0916-drm-amdgpu-add-ELM-BAF-support-to-dce_v11_0_pick_pll.patch b/common/recipes-kernel/linux/files/0916-drm-amdgpu-add-ELM-BAF-support-to-dce_v11_0_pick_pll.patch
deleted file mode 100644
index cff9b6c2..00000000
--- a/common/recipes-kernel/linux/files/0916-drm-amdgpu-add-ELM-BAF-support-to-dce_v11_0_pick_pll.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 9355b7d47bafc14da1944d323db96cb5b32af968 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 15:21:09 -0400
-Subject: [PATCH 0916/1110] drm/amdgpu: add ELM/BAF support to
- dce_v11_0_pick_pll
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-New PLL scheme on ELM/BAF.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 53e338b..92a242a 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2384,6 +2384,18 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
- 	u32 pll_in_use;
- 	int pll;
- 
-+	if ((adev->asic_type == CHIP_ELLESMERE) ||
-+	    (adev->asic_type == CHIP_BAFFIN)) {
-+		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
-+			return ATOM_DP_DTO;
-+		/* use the same PPLL for all monitors with the same clock */
-+		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
-+		if (pll != ATOM_PPLL_INVALID)
-+			return pll;
-+
-+		return ATOM_COMBOPHY_PLL0 + amdgpu_crtc->crtc_id;
-+	}
-+
- 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
- 		if (adev->clock.dp_extclk)
- 			/* skip PPLL programming if using ext clock */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch
deleted file mode 100644
index a1d1b7a2..00000000
--- a/common/recipes-kernel/linux/files/0917-drm-amdgpu-dce11-update-pll-programming-for-ELM-BAF.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 7671e6b69ffaffe933791336c4924f9a55b8a9de Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 16:35:33 -0400
-Subject: [PATCH 0917/1110] drm/amdgpu/dce11: update pll programming for
- ELM/BAF
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-SetPixelClock table handles pll divider calculation and
-spread spectrum setup, so no need to use calculate the
-dividers and call the ss enable cmd table.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 31 +++++++++++++++++++++++++++++--
- 1 file changed, 29 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 92a242a..d068de8 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2751,7 +2751,17 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
- 	case ATOM_PPLL2:
- 		/* disable the ppll */
- 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
--					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
-+						 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
-+		break;
-+	case ATOM_COMBOPHY_PLL0:
-+	case ATOM_COMBOPHY_PLL1:
-+	case ATOM_COMBOPHY_PLL2:
-+	case ATOM_COMBOPHY_PLL3:
-+	case ATOM_COMBOPHY_PLL4:
-+	case ATOM_COMBOPHY_PLL5:
-+		/* disable the ppll */
-+		amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
-+						 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
- 		break;
- 	default:
- 		break;
-@@ -2769,11 +2779,28 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
- 				  int x, int y, struct drm_framebuffer *old_fb)
- {
- 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-+	struct drm_device *dev = crtc->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
- 
- 	if (!amdgpu_crtc->adjusted_clock)
- 		return -EINVAL;
- 
--	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
-+	if ((adev->asic_type == CHIP_ELLESMERE) ||
-+	    (adev->asic_type == CHIP_BAFFIN)) {
-+		struct amdgpu_encoder *amdgpu_encoder =
-+			to_amdgpu_encoder(amdgpu_crtc->encoder);
-+		int encoder_mode =
-+			amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
-+
-+		/* SetPixelClock calculates the plls and ss values now */
-+		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
-+						 amdgpu_crtc->pll_id,
-+						 encoder_mode, amdgpu_encoder->encoder_id,
-+						 adjusted_mode->clock, 0, 0, 0, 0,
-+						 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
-+	} else {
-+		amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
-+	}
- 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
- 	dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
- 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0918-drm-amdgpu-dce11-add-dce-clock-setting-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0918-drm-amdgpu-dce11-add-dce-clock-setting-for-ELM-BAF.patch
deleted file mode 100644
index 4792c76f..00000000
--- a/common/recipes-kernel/linux/files/0918-drm-amdgpu-dce11-add-dce-clock-setting-for-ELM-BAF.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 9e99a7c6708cf90b76fc13766fba4cfc3d665379 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 15 Oct 2015 17:14:31 -0400
-Subject: [PATCH 0918/1110] drm/amdgpu/dce11: add dce clock setting for ELM/BAF
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Setup the disp clock and dp reference clock.  This is
-now a separate command table on elm/baf compared to
-older asics.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index d068de8..78cd659 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -3063,7 +3063,15 @@ static int dce_v11_0_hw_init(void *handle)
- 	/* init dig PHYs, disp eng pll */
- 	amdgpu_atombios_crtc_powergate_init(adev);
- 	amdgpu_atombios_encoder_init_dig(adev);
--	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
-+	if ((adev->asic_type == CHIP_ELLESMERE) ||
-+	    (adev->asic_type == CHIP_BAFFIN)) {
-+		amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
-+						   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
-+		amdgpu_atombios_crtc_set_dce_clock(adev, 0,
-+						   DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
-+	} else {
-+		amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
-+	}
- 
- 	/* initialize hpd */
- 	dce_v11_0_hpd_init(adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0919-drm-amdgpu-add-GMC-support-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0919-drm-amdgpu-add-GMC-support-for-ELM-BAF.patch
deleted file mode 100644
index aa7483d2..00000000
--- a/common/recipes-kernel/linux/files/0919-drm-amdgpu-add-GMC-support-for-ELM-BAF.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From c356af68cfa472cab33fc689644c61328590e091 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Fri, 11 Mar 2016 14:28:53 -0500
-Subject: [PATCH 0919/1110] drm/amdgpu: add GMC support for ELM/BAF
-
-V2: add golden_settings_baffin_a11 instead of reuse golden_settings_fiji_a10
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 35 +++++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 9fbce45..27956dd 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -43,6 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
- static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
- 
- MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_mc.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin");
- 
- static const u32 golden_settings_tonga_a11[] =
- {
-@@ -73,6 +75,23 @@ static const u32 fiji_mgcg_cgcg_init[] =
- 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
- };
- 
-+static const u32 golden_settings_baffin_a11[] =
-+{
-+	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-+	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-+	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-+	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
-+};
-+
-+static const u32 golden_settings_ellesmere_a11[] =
-+{
-+	mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
-+	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-+	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-+	mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-+	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
-+};
-+
- static const u32 cz_mgcg_cgcg_init[] =
- {
- 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
-@@ -103,6 +122,16 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
- 						 golden_settings_tonga_a11,
- 						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
-+	case CHIP_BAFFIN:
-+		amdgpu_program_register_sequence(adev,
-+						 golden_settings_baffin_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
-+		break;
-+	case CHIP_ELLESMERE:
-+		amdgpu_program_register_sequence(adev,
-+						 golden_settings_ellesmere_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
-+		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
-@@ -209,6 +238,12 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
- 	case CHIP_TONGA:
- 		chip_name = "tonga";
- 		break;
-+	case CHIP_BAFFIN:
-+		chip_name = "baffin";
-+		break;
-+	case CHIP_ELLESMERE:
-+		chip_name = "ellesmere";
-+		break;
- 	case CHIP_FIJI:
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0920-drm-amdgpu-add-DCE-golden-setting-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0920-drm-amdgpu-add-DCE-golden-setting-for-ELM-BAF.patch
deleted file mode 100644
index dca2381d..00000000
--- a/common/recipes-kernel/linux/files/0920-drm-amdgpu-add-DCE-golden-setting-for-ELM-BAF.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 0ad46c7ea886c937db154f76c1ab3a5d1f3668a5 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Thu, 29 Oct 2015 17:25:48 +0800
-Subject: [PATCH 0920/1110] drm/amdgpu: add DCE golden setting for ELM/BAF
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 78cd659..bcb8626 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -132,6 +132,22 @@ static const u32 stoney_golden_settings_a11[] =
- 	mmFBC_MISC, 0x1f311fff, 0x14302000,
- };
- 
-+static const u32 baffin_golden_settings_a11[] =
-+{
-+	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
-+	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
-+	mmFBC_DEBUG1, 0xffffffff, 0x00000008,
-+	mmFBC_MISC, 0x9f313fff, 0x14300008,
-+	mmHDMI_CONTROL, 0x313f031f, 0x00000011,
-+};
-+
-+static const u32 ellesmere_golden_settings_a11[] =
-+{
-+	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
-+	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
-+	mmFBC_MISC, 0x9f313fff, 0x14300008,
-+	mmHDMI_CONTROL, 0x313f031f, 0x00000011,
-+};
- 
- static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
- {
-@@ -149,6 +165,16 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
- 						 stoney_golden_settings_a11,
- 						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
- 		break;
-+	case CHIP_BAFFIN:
-+		amdgpu_program_register_sequence(adev,
-+						 baffin_golden_settings_a11,
-+						 (const u32)ARRAY_SIZE(baffin_golden_settings_a11));
-+		break;
-+	case CHIP_ELLESMERE:
-+		amdgpu_program_register_sequence(adev,
-+						 ellesmere_golden_settings_a11,
-+						 (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11));
-+		break;
- 	default:
- 		break;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0921-drm-amdgpu-add-SDMA-support-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0921-drm-amdgpu-add-SDMA-support-for-ELM-BAF.patch
deleted file mode 100644
index 86744607..00000000
--- a/common/recipes-kernel/linux/files/0921-drm-amdgpu-add-SDMA-support-for-ELM-BAF.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From 77a082f6a3c7bd4ace7422434094979f5639ad03 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Thu, 29 Oct 2015 17:26:22 +0800
-Subject: [PATCH 0921/1110] drm/amdgpu: add SDMA support for ELM/BAF
-
-V2: seperate baffin & ellesmere settings instead of using fiji ones.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 47 ++++++++++++++++++++++++++++++++++
- 1 file changed, 47 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 368a46b..6b24a9c 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -56,6 +56,11 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
- MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
- MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
- MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_sdma.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin");
-+
- 
- static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
- {
-@@ -101,6 +106,32 @@ static const u32 fiji_mgcg_cgcg_init[] =
- 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
- };
- 
-+static const u32 golden_settings_baffin_a11[] =
-+{
-+	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
-+	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
-+	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
-+};
-+
-+static const u32 golden_settings_ellesmere_a11[] =
-+{
-+	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
-+	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
-+	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
-+	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
-+	mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
-+	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
-+};
-+
- static const u32 cz_golden_settings_a11[] =
- {
- 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
-@@ -172,6 +203,16 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
- 						 golden_settings_tonga_a11,
- 						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
-+	case CHIP_BAFFIN:
-+		amdgpu_program_register_sequence(adev,
-+						 golden_settings_baffin_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
-+		break;
-+	case CHIP_ELLESMERE:
-+		amdgpu_program_register_sequence(adev,
-+						 golden_settings_ellesmere_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
-+		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
-@@ -220,6 +261,12 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
- 	case CHIP_FIJI:
- 		chip_name = "fiji";
- 		break;
-+	case CHIP_BAFFIN:
-+		chip_name = "baffin";
-+		break;
-+	case CHIP_ELLESMERE:
-+		chip_name = "ellesmere";
-+		break;
- 	case CHIP_CARRIZO:
- 		chip_name = "carrizo";
- 		break;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0922-drm-amdgpu-add-an-interface-to-get-gfx-constants-fro.patch b/common/recipes-kernel/linux/files/0922-drm-amdgpu-add-an-interface-to-get-gfx-constants-fro.patch
deleted file mode 100644
index bcbd53b6..00000000
--- a/common/recipes-kernel/linux/files/0922-drm-amdgpu-add-an-interface-to-get-gfx-constants-fro.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 8df2f9c9f5621578e6313694eafa79453af0ca85 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 14 Mar 2016 16:51:24 -0400
-Subject: [PATCH 0922/1110] drm/amdgpu: add an interface to get gfx constants
- from atombios
-
-Fetch the values from atom rather than hardcoding them in the
-driver.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 30 ++++++++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |  2 ++
- 2 files changed, 32 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
-index 84b0ce3..6830ed4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
-@@ -699,6 +699,36 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
- 	return ret;
- }
- 
-+union gfx_info {
-+	ATOM_GFX_INFO_V2_1 info;
-+};
-+
-+int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
-+{
-+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
-+	int index = GetIndexIntoMasterTable(DATA, GFX_Info);
-+	uint8_t frev, crev;
-+	uint16_t data_offset;
-+	int ret = -EINVAL;
-+
-+	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
-+				   &frev, &crev, &data_offset)) {
-+		union gfx_info *gfx_info = (union gfx_info *)
-+			(mode_info->atom_context->bios + data_offset);
-+
-+		adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
-+		adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
-+		adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
-+		adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
-+		adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
-+		adev->gfx.config.max_texture_channel_caches =
-+			gfx_info->info.max_texture_channel_caches;
-+
-+		ret = 0;
-+	}
-+	return ret;
-+}
-+
- union igp_info {
- 	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
- 	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
-index 9e14420..8c2e696 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
-@@ -144,6 +144,8 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
- 
- int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev);
- 
-+int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev);
-+
- bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
- 				      struct amdgpu_atom_ss *ss,
- 				      int id, u32 clock);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0923-drm-amdgpu-add-mmRLC_CGCG_CGLS_CTRL_3D-mmRLC_CGCG_RA.patch b/common/recipes-kernel/linux/files/0923-drm-amdgpu-add-mmRLC_CGCG_CGLS_CTRL_3D-mmRLC_CGCG_RA.patch
deleted file mode 100644
index 1d546304..00000000
--- a/common/recipes-kernel/linux/files/0923-drm-amdgpu-add-mmRLC_CGCG_CGLS_CTRL_3D-mmRLC_CGCG_RA.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 582a592186e798d3808625bf71a90940379f0b98 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Thu, 5 Nov 2015 12:42:59 +0800
-Subject: [PATCH 0923/1110] drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D &
- mmRLC_CGCG_RAMP_CTRL_3D
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-index a9b6923..ebaf67b 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-@@ -1391,6 +1391,8 @@
- #define mmRLC_CGTT_MGCG_OVERRIDE                                                0xec48
- #define mmRLC_CGCG_CGLS_CTRL                                                    0xec49
- #define mmRLC_CGCG_RAMP_CTRL                                                    0xec4a
-+#define mmRLC_CGCG_CGLS_CTRL_3D                                                 0xec9d
-+#define mmRLC_CGCG_RAMP_CTRL_3D                                                 0xec9e
- #define mmRLC_DYN_PG_STATUS                                                     0xec4b
- #define mmRLC_DYN_PG_REQUEST                                                    0xec4c
- #define mmRLC_PG_DELAY                                                          0xec4d
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0924-drm-amdgpu-add-GFX-support-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0924-drm-amdgpu-add-GFX-support-for-ELM-BAF.patch
deleted file mode 100644
index 4227af6c..00000000
--- a/common/recipes-kernel/linux/files/0924-drm-amdgpu-add-GFX-support-for-ELM-BAF.patch
+++ /dev/null
@@ -1,697 +0,0 @@
-From 7d04db9ac06939c022aa1de067fbdbdf5a5b730d Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Thu, 29 Oct 2015 17:26:56 +0800
-Subject: [PATCH 0924/1110] drm/amdgpu: add GFX support for ELM/BAF
-
-V2: use gfx_8_0_*.h instead of gfx_8_1_*.h
-v3: agd: integrate support for gfx info table
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 555 +++++++++++++++++++++++++++++++++-
- 1 file changed, 551 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 83ceafa..75a76f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -27,6 +27,7 @@
- #include "vi.h"
- #include "vid.h"
- #include "amdgpu_ucode.h"
-+#include "amdgpu_atombios.h"
- #include "clearstate_vi.h"
- 
- #include "gmc/gmc_8_2_d.h"
-@@ -51,6 +52,7 @@
- 
- #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
- #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
-+#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002
- #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
- 
- #define ARRAY_MODE(x)					((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
-@@ -117,6 +119,20 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
- MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
- MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
- 
-+MODULE_FIRMWARE("amdgpu/baffin_ce.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_me.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_mec.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/baffin_rlc.bin");
-+
-+MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_me.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin");
-+
- static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
- {
- 	{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
-@@ -247,6 +263,64 @@ static const u32 tonga_mgcg_cgcg_init[] =
- 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
- };
- 
-+static const u32 golden_settings_baffin_a11[] =
-+{
-+	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
-+	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
-+	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
-+	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
-+	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
-+	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
-+	mmSQ_CONFIG, 0x07f80000, 0x07180000,
-+	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
-+	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
-+	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
-+	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
-+	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
-+};
-+
-+static const u32 baffin_golden_common_all[] =
-+{
-+	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
-+	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
-+	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
-+	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
-+	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
-+	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
-+	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
-+	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
-+};
-+
-+static const u32 golden_settings_ellesmere_a11[] =
-+{
-+	mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
-+	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
-+	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
-+	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
-+	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
-+	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
-+	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
-+	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
-+	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
-+	mmSQ_CONFIG, 0x07f80000, 0x07180000,
-+	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
-+	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
-+	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
-+	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
-+};
-+
-+static const u32 ellesmere_golden_common_all[] =
-+{
-+	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
-+	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
-+	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
-+	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
-+	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
-+	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
-+	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
-+	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
-+};
-+
- static const u32 fiji_golden_common_all[] =
- {
- 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
-@@ -597,6 +671,22 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
- 						 tonga_golden_common_all,
- 						 (const u32)ARRAY_SIZE(tonga_golden_common_all));
- 		break;
-+	case CHIP_BAFFIN:
-+		amdgpu_program_register_sequence(adev,
-+						 golden_settings_baffin_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
-+		amdgpu_program_register_sequence(adev,
-+						 baffin_golden_common_all,
-+						 (const u32)ARRAY_SIZE(baffin_golden_common_all));
-+		break;
-+	case CHIP_ELLESMERE:
-+		amdgpu_program_register_sequence(adev,
-+						 golden_settings_ellesmere_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
-+		amdgpu_program_register_sequence(adev,
-+						 ellesmere_golden_common_all,
-+						 (const u32)ARRAY_SIZE(ellesmere_golden_common_all));
-+		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
-@@ -764,6 +854,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
- 	case CHIP_FIJI:
- 		chip_name = "fiji";
- 		break;
-+	case CHIP_BAFFIN:
-+		chip_name = "baffin";
-+		break;
-+	case CHIP_ELLESMERE:
-+		chip_name = "ellesmere";
-+		break;
- 	case CHIP_STONEY:
- 		chip_name = "stoney";
- 		break;
-@@ -1297,12 +1393,13 @@ fail:
- 	return r;
- }
- 
--static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
-+static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- {
- 	u32 gb_addr_config;
- 	u32 mc_shared_chmap, mc_arb_ramcfg;
- 	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
- 	u32 tmp;
-+	int ret;
- 
- 	switch (adev->asic_type) {
- 	case CHIP_TOPAZ:
-@@ -1339,6 +1436,34 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
- 		gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
- 		break;
-+	case CHIP_BAFFIN:
-+		ret = amdgpu_atombios_get_gfx_info(adev);
-+		if (ret)
-+			return ret;
-+		adev->gfx.config.max_gprs = 256;
-+		adev->gfx.config.max_gs_threads = 32;
-+		adev->gfx.config.max_hw_contexts = 8;
-+
-+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+		gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN;
-+		break;
-+	case CHIP_ELLESMERE:
-+		ret = amdgpu_atombios_get_gfx_info(adev);
-+		if (ret)
-+			return ret;
-+		adev->gfx.config.max_gprs = 256;
-+		adev->gfx.config.max_gs_threads = 32;
-+		adev->gfx.config.max_hw_contexts = 8;
-+
-+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-+		gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-+		break;
- 	case CHIP_TONGA:
- 		adev->gfx.config.max_shader_engines = 4;
- 		adev->gfx.config.max_tile_pipes = 8;
-@@ -1521,6 +1646,8 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- 		break;
- 	}
- 	adev->gfx.config.gb_addr_config = gb_addr_config;
-+
-+	return 0;
- }
- 
- static int gfx_v8_0_sw_init(void *handle)
-@@ -1630,7 +1757,9 @@ static int gfx_v8_0_sw_init(void *handle)
- 
- 	adev->gfx.ce_ram_size = 0x8000;
- 
--	gfx_v8_0_gpu_early_init(adev);
-+	r = gfx_v8_0_gpu_early_init(adev);
-+	if (r)
-+		return r;
- 
- 	return 0;
- }
-@@ -2220,6 +2349,410 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
- 
- 		break;
-+	case CHIP_BAFFIN:
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
-+		break;
-+	case CHIP_ELLESMERE:
-+		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+		modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
-+		modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+		modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+		modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+		modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+				MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+				SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+				NUM_BANKS(ADDR_SURF_16_BANK));
-+
-+		mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+		mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+				NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+			WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+			if (reg_offset != 7)
-+				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
-+		break;
- 	case CHIP_STONEY:
- 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- 				PIPE_CONFIG(ADDR_SURF_P2) |
-@@ -2859,6 +3392,9 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
- 
- 	/* disable CG */
- 	WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
-+	if (adev->asic_type == CHIP_BAFFIN ||
-+		adev->asic_type == CHIP_ELLESMERE)
-+		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
- 
- 	/* disable PG */
- 	WREG32(mmRLC_PG_CNTL, 0);
-@@ -3036,9 +3572,14 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
- 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
- 	switch (adev->asic_type) {
- 	case CHIP_TONGA:
-+	case CHIP_ELLESMERE:
- 		amdgpu_ring_write(ring, 0x16000012);
- 		amdgpu_ring_write(ring, 0x0000002A);
- 		break;
-+	case CHIP_BAFFIN:
-+		amdgpu_ring_write(ring, 0x16000012);
-+		amdgpu_ring_write(ring, 0x00000000);
-+		break;
- 	case CHIP_FIJI:
- 		amdgpu_ring_write(ring, 0x3a00161a);
- 		amdgpu_ring_write(ring, 0x0000002e);
-@@ -3123,6 +3664,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
- 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
- 					    DOORBELL_OFFSET, ring->doorbell_index);
- 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-+					    DOORBELL_HIT, 0);
-+			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
- 					    DOORBELL_EN, 1);
- 		} else {
- 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
-@@ -3680,7 +4223,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- 		if (use_doorbell) {
- 			if ((adev->asic_type == CHIP_CARRIZO) ||
- 			    (adev->asic_type == CHIP_FIJI) ||
--			    (adev->asic_type == CHIP_STONEY)) {
-+			    (adev->asic_type == CHIP_STONEY) ||
-+			    (adev->asic_type == CHIP_BAFFIN) ||
-+			    (adev->asic_type == CHIP_ELLESMERE)) {
- 				WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
- 				       AMDGPU_DOORBELL_KIQ << 2);
- 				WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-@@ -3714,7 +4259,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- 		tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
- 		WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
- 		mqd->cp_hqd_persistent_state = tmp;
--		if (adev->asic_type == CHIP_STONEY) {
-+		if (adev->asic_type == CHIP_STONEY ||
-+			adev->asic_type == CHIP_BAFFIN ||
-+			adev->asic_type == CHIP_ELLESMERE) {
- 			tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
- 			tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
- 			WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0925-drm-amdgpu-add-UVD-support-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0925-drm-amdgpu-add-UVD-support-for-ELM-BAF.patch
deleted file mode 100644
index 8cc97acd..00000000
--- a/common/recipes-kernel/linux/files/0925-drm-amdgpu-add-UVD-support-for-ELM-BAF.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From cb235a2c0eb86d9965241aa187b78285cc6290e2 Mon Sep 17 00:00:00 2001
-From: Sonny Jiang <sonny.jiang@amd.com>
-Date: Thu, 5 Nov 2015 15:17:18 -0500
-Subject: [PATCH 0925/1110] drm/amdgpu: add UVD support for ELM/BAF
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Ellesmere and Baffin are UVD 6.3
-
-Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index cb6990a..239b764 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -54,6 +54,8 @@
- #define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"
- #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
- #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
-+#define FIRMWARE_ELLESMERE	"amdgpu/ellesmere_uvd.bin"
-+#define FIRMWARE_BAFFIN         "amdgpu/baffin_uvd.bin"
- 
- /**
-  * amdgpu_uvd_cs_ctx - Command submission parser context
-@@ -85,6 +87,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA);
- MODULE_FIRMWARE(FIRMWARE_CARRIZO);
- MODULE_FIRMWARE(FIRMWARE_FIJI);
- MODULE_FIRMWARE(FIRMWARE_STONEY);
-+MODULE_FIRMWARE(FIRMWARE_ELLESMERE);
-+MODULE_FIRMWARE(FIRMWARE_BAFFIN);
- 
- static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
- static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
-@@ -131,6 +135,12 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- 	case CHIP_STONEY:
- 		fw_name = FIRMWARE_STONEY;
- 		break;
-+	case CHIP_ELLESMERE:
-+		fw_name = FIRMWARE_ELLESMERE;
-+		break;
-+	case CHIP_BAFFIN:
-+		fw_name = FIRMWARE_BAFFIN;
-+		break;
- 	default:
- 		return -EINVAL;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0926-drm-amdgpu-add-VCE-support-to-ELM-BAF.patch b/common/recipes-kernel/linux/files/0926-drm-amdgpu-add-VCE-support-to-ELM-BAF.patch
deleted file mode 100644
index 8734b97d..00000000
--- a/common/recipes-kernel/linux/files/0926-drm-amdgpu-add-VCE-support-to-ELM-BAF.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From f0a4448a8d4bd1ce2931b6949b9a4156f3fbf1a8 Mon Sep 17 00:00:00 2001
-From: Sonny Jiang <sonny.jiang@amd.com>
-Date: Fri, 11 Mar 2016 14:33:40 -0500
-Subject: [PATCH 0926/1110] drm/amdgpu: add VCE support to ELM/BAF
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Ellesmere and Baffin are VCE 3.4
-
-Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 10 ++++++++++
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c   |  6 ++++--
- 2 files changed, 14 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 923ee5a..2904842 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -50,6 +50,8 @@
- #define FIRMWARE_CARRIZO	"amdgpu/carrizo_vce.bin"
- #define FIRMWARE_FIJI		"amdgpu/fiji_vce.bin"
- #define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"
-+#define FIRMWARE_ELLESMERE	"amdgpu/ellesmere_vce.bin"
-+#define FIRMWARE_BAFFIN         "amdgpu/baffin_vce.bin"
- 
- #ifdef CONFIG_DRM_AMDGPU_CIK
- MODULE_FIRMWARE(FIRMWARE_BONAIRE);
-@@ -62,6 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA);
- MODULE_FIRMWARE(FIRMWARE_CARRIZO);
- MODULE_FIRMWARE(FIRMWARE_FIJI);
- MODULE_FIRMWARE(FIRMWARE_STONEY);
-+MODULE_FIRMWARE(FIRMWARE_ELLESMERE);
-+MODULE_FIRMWARE(FIRMWARE_BAFFIN);
- 
- static void amdgpu_vce_idle_work_handler(struct work_struct *work);
- 
-@@ -113,6 +117,12 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
- 	case CHIP_STONEY:
- 		fw_name = FIRMWARE_STONEY;
- 		break;
-+	case CHIP_ELLESMERE:
-+		fw_name = FIRMWARE_ELLESMERE;
-+		break;
-+	case CHIP_BAFFIN:
-+		fw_name = FIRMWARE_BAFFIN;
-+		break;
- 
- 	default:
- 		return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index bf7bc84..c12fd83 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -315,9 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
- {
- 	u32 tmp;
- 
--	/* Fiji, Stoney are single pipe */
-+	/* Fiji, Stoney, Ellesmere, Baffin are single pipe */
- 	if ((adev->asic_type == CHIP_FIJI) ||
--	    (adev->asic_type == CHIP_STONEY))
-+	    (adev->asic_type == CHIP_STONEY) ||
-+	    (adev->asic_type == CHIP_ELLESMERE) ||
-+	    (adev->asic_type == CHIP_BAFFIN))
- 		return AMDGPU_VCE_HARVEST_VCE1;
- 
- 	/* Tonga and CZ are dual or single pipe */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0927-drm-amd-powerplay-add-header-files-for-ellesmere-smu.patch b/common/recipes-kernel/linux/files/0927-drm-amd-powerplay-add-header-files-for-ellesmere-smu.patch
deleted file mode 100644
index dd88bc73..00000000
--- a/common/recipes-kernel/linux/files/0927-drm-amd-powerplay-add-header-files-for-ellesmere-smu.patch
+++ /dev/null
@@ -1,12088 +0,0 @@
-From 56a59d5189fbbddb96bf573a7d6c4678f2429d71 Mon Sep 17 00:00:00 2001
-From: rezhu <Rex.Zhu@amd.com>
-Date: Mon, 16 Nov 2015 10:33:31 +0800
-Subject: [PATCH 0927/1110] drm/amd/powerplay: add header files for ellesmere
- smu manager.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- .../gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h    |   401 +
- .../gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h | 10088 +++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/smu74.h          |   774 ++
- drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h |   780 ++
- 4 files changed, 12043 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu74.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
-new file mode 100644
-index 0000000..18fe230
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
-@@ -0,0 +1,401 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef ELLESMERE_PP_SMC_H
-+#define ELLESMERE_PP_SMC_H
-+
-+
-+#pragma pack(push, 1)
-+
-+
-+#define PPSMC_SWSTATE_FLAG_DC                           0x01
-+#define PPSMC_SWSTATE_FLAG_UVD                          0x02
-+#define PPSMC_SWSTATE_FLAG_VCE                          0x04
-+
-+#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
-+#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
-+#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
-+
-+#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
-+#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
-+#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
-+
-+#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
-+
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
-+#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
-+
-+
-+#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
-+#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
-+#define PPSMC_DPM2FLAGS_OCP                             0x04
-+
-+
-+#define PPSMC_DISPLAY_WATERMARK_LOW                     0
-+#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
-+
-+
-+#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
-+#define PPSMC_STATEFLAG_POWERBOOST         0x02
-+#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
-+#define PPSMC_STATEFLAG_POWERSHIFT         0x08
-+#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
-+#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
-+#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
-+
-+
-+#define FDO_MODE_HARDWARE 0
-+#define FDO_MODE_PIECE_WISE_LINEAR 1
-+
-+enum FAN_CONTROL {
-+	FAN_CONTROL_FUZZY,
-+	FAN_CONTROL_TABLE
-+};
-+
-+
-+#define PPSMC_Result_OK             ((uint16_t)0x01)
-+#define PPSMC_Result_NoMore         ((uint16_t)0x02)
-+
-+#define PPSMC_Result_NotNow         ((uint16_t)0x03)
-+#define PPSMC_Result_Failed         ((uint16_t)0xFF)
-+#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
-+#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
-+
-+typedef uint16_t PPSMC_Result;
-+
-+#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
-+
-+
-+#define PPSMC_MSG_Halt                      ((uint16_t)0x10)
-+#define PPSMC_MSG_Resume                    ((uint16_t)0x11)
-+#define PPSMC_MSG_EnableDPMLevel            ((uint16_t)0x12)
-+#define PPSMC_MSG_ZeroLevelsDisabled        ((uint16_t)0x13)
-+#define PPSMC_MSG_OneLevelsDisabled         ((uint16_t)0x14)
-+#define PPSMC_MSG_TwoLevelsDisabled         ((uint16_t)0x15)
-+#define PPSMC_MSG_EnableThermalInterrupt    ((uint16_t)0x16)
-+#define PPSMC_MSG_RunningOnAC               ((uint16_t)0x17)
-+#define PPSMC_MSG_LevelUp                   ((uint16_t)0x18)
-+#define PPSMC_MSG_LevelDown                 ((uint16_t)0x19)
-+#define PPSMC_MSG_ResetDPMCounters          ((uint16_t)0x1a)
-+#define PPSMC_MSG_SwitchToSwState           ((uint16_t)0x20)
-+#define PPSMC_MSG_SwitchToSwStateLast       ((uint16_t)0x3f)
-+#define PPSMC_MSG_SwitchToInitialState      ((uint16_t)0x40)
-+#define PPSMC_MSG_NoForcedLevel             ((uint16_t)0x41)
-+#define PPSMC_MSG_ForceHigh                 ((uint16_t)0x42)
-+#define PPSMC_MSG_ForceMediumOrHigh         ((uint16_t)0x43)
-+#define PPSMC_MSG_SwitchToMinimumPower      ((uint16_t)0x51)
-+#define PPSMC_MSG_ResumeFromMinimumPower    ((uint16_t)0x52)
-+#define PPSMC_MSG_EnableCac                 ((uint16_t)0x53)
-+#define PPSMC_MSG_DisableCac                ((uint16_t)0x54)
-+#define PPSMC_DPMStateHistoryStart          ((uint16_t)0x55)
-+#define PPSMC_DPMStateHistoryStop           ((uint16_t)0x56)
-+#define PPSMC_CACHistoryStart               ((uint16_t)0x57)
-+#define PPSMC_CACHistoryStop                ((uint16_t)0x58)
-+#define PPSMC_TDPClampingActive             ((uint16_t)0x59)
-+#define PPSMC_TDPClampingInactive           ((uint16_t)0x5A)
-+#define PPSMC_StartFanControl               ((uint16_t)0x5B)
-+#define PPSMC_StopFanControl                ((uint16_t)0x5C)
-+#define PPSMC_NoDisplay                     ((uint16_t)0x5D)
-+#define PPSMC_HasDisplay                    ((uint16_t)0x5E)
-+#define PPSMC_MSG_UVDPowerOFF               ((uint16_t)0x60)
-+#define PPSMC_MSG_UVDPowerON                ((uint16_t)0x61)
-+#define PPSMC_MSG_EnableULV                 ((uint16_t)0x62)
-+#define PPSMC_MSG_DisableULV                ((uint16_t)0x63)
-+#define PPSMC_MSG_EnterULV                  ((uint16_t)0x64)
-+#define PPSMC_MSG_ExitULV                   ((uint16_t)0x65)
-+#define PPSMC_PowerShiftActive              ((uint16_t)0x6A)
-+#define PPSMC_PowerShiftInactive            ((uint16_t)0x6B)
-+#define PPSMC_OCPActive                     ((uint16_t)0x6C)
-+#define PPSMC_OCPInactive                   ((uint16_t)0x6D)
-+#define PPSMC_CACLongTermAvgEnable          ((uint16_t)0x6E)
-+#define PPSMC_CACLongTermAvgDisable         ((uint16_t)0x6F)
-+#define PPSMC_MSG_InferredStateSweep_Start  ((uint16_t)0x70)
-+#define PPSMC_MSG_InferredStateSweep_Stop   ((uint16_t)0x71)
-+#define PPSMC_MSG_SwitchToLowestInfState    ((uint16_t)0x72)
-+#define PPSMC_MSG_SwitchToNonInfState       ((uint16_t)0x73)
-+#define PPSMC_MSG_AllStateSweep_Start       ((uint16_t)0x74)
-+#define PPSMC_MSG_AllStateSweep_Stop        ((uint16_t)0x75)
-+#define PPSMC_MSG_SwitchNextLowerInfState   ((uint16_t)0x76)
-+#define PPSMC_MSG_SwitchNextHigherInfState  ((uint16_t)0x77)
-+#define PPSMC_MSG_MclkRetrainingTest        ((uint16_t)0x78)
-+#define PPSMC_MSG_ForceTDPClamping          ((uint16_t)0x79)
-+#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint16_t)0x7A)
-+#define PPSMC_MSG_CollectCAC_WeightCalib    ((uint16_t)0x7B)
-+#define PPSMC_MSG_CollectCAC_SQonly         ((uint16_t)0x7C)
-+#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
-+
-+#define PPSMC_MSG_ExtremitiesTest_Start     ((uint16_t)0x7E)
-+#define PPSMC_MSG_ExtremitiesTest_Stop      ((uint16_t)0x7F)
-+#define PPSMC_FlushDataCache                ((uint16_t)0x80)
-+#define PPSMC_FlushInstrCache               ((uint16_t)0x81)
-+
-+#define PPSMC_MSG_SetEnabledLevels          ((uint16_t)0x82)
-+#define PPSMC_MSG_SetForcedLevels           ((uint16_t)0x83)
-+
-+#define PPSMC_MSG_ResetToDefaults           ((uint16_t)0x84)
-+
-+#define PPSMC_MSG_SetForcedLevelsAndJump      ((uint16_t)0x85)
-+#define PPSMC_MSG_SetCACHistoryMode           ((uint16_t)0x86)
-+#define PPSMC_MSG_EnableDTE                   ((uint16_t)0x87)
-+#define PPSMC_MSG_DisableDTE                  ((uint16_t)0x88)
-+
-+#define PPSMC_MSG_SmcSpaceSetAddress          ((uint16_t)0x89)
-+#define PPSM_MSG_SmcSpaceWriteDWordInc        ((uint16_t)0x8A)
-+#define PPSM_MSG_SmcSpaceWriteWordInc         ((uint16_t)0x8B)
-+#define PPSM_MSG_SmcSpaceWriteByteInc         ((uint16_t)0x8C)
-+
-+#define PPSMC_MSG_BREAK                       ((uint16_t)0xF8)
-+
-+#define PPSMC_MSG_Test                        ((uint16_t) 0x100)
-+#define PPSMC_MSG_DPM_Voltage_Pwrmgt          ((uint16_t) 0x101)
-+#define PPSMC_MSG_DPM_Config                  ((uint16_t) 0x102)
-+#define PPSMC_MSG_PM_Controller_Start         ((uint16_t) 0x103)
-+#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
-+#define PPSMC_MSG_PG_PowerDownSIMD            ((uint16_t) 0x105)
-+#define PPSMC_MSG_PG_PowerUpSIMD              ((uint16_t) 0x106)
-+#define PPSMC_MSG_PM_Controller_Stop          ((uint16_t) 0x107)
-+#define PPSMC_MSG_PG_SIMD_Config              ((uint16_t) 0x108)
-+#define PPSMC_MSG_Voltage_Cntl_Enable         ((uint16_t) 0x109)
-+#define PPSMC_MSG_Thermal_Cntl_Enable         ((uint16_t) 0x10a)
-+#define PPSMC_MSG_Reset_Service               ((uint16_t) 0x10b)
-+#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x10e)
-+#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0x10f)
-+#define PPSMC_MSG_DPM_Disable_VCE_HS          ((uint16_t) 0x110)
-+#define PPSMC_MSG_DPM_Enable_VCE_HS           ((uint16_t) 0x111)
-+#define PPSMC_MSG_DPM_N_LevelsDisabled        ((uint16_t) 0x112)
-+#define PPSMC_MSG_DCEPowerOFF                 ((uint16_t) 0x113)
-+#define PPSMC_MSG_DCEPowerON                  ((uint16_t) 0x114)
-+#define PPSMC_MSG_PCIE_DDIPowerDown           ((uint16_t) 0x117)
-+#define PPSMC_MSG_PCIE_DDIPowerUp             ((uint16_t) 0x118)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerDown    ((uint16_t) 0x119)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerUp      ((uint16_t) 0x11a)
-+#define PPSMC_MSG_SYSPLLPowerOff              ((uint16_t) 0x11b)
-+#define PPSMC_MSG_SYSPLLPowerOn               ((uint16_t) 0x11c)
-+#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
-+#define PPSMC_MSG_DCE_AllowVoltageAdjustment  ((uint16_t) 0x11e)
-+#define PPSMC_MSG_DISPLAYPHYStatusNotify      ((uint16_t) 0x11f)
-+#define PPSMC_MSG_EnableBAPM                  ((uint16_t) 0x120)
-+#define PPSMC_MSG_DisableBAPM                 ((uint16_t) 0x121)
-+#define PPSMC_MSG_Spmi_Enable                 ((uint16_t) 0x122)
-+#define PPSMC_MSG_Spmi_Timer                  ((uint16_t) 0x123)
-+#define PPSMC_MSG_LCLK_DPM_Config             ((uint16_t) 0x124)
-+#define PPSMC_MSG_VddNB_Request               ((uint16_t) 0x125)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerDown        ((uint32_t) 0x126)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerUp          ((uint32_t) 0x127)
-+#define PPSMC_MSG_MCLKDPM_Config              ((uint16_t) 0x128)
-+
-+#define PPSMC_MSG_UVDDPM_Config               ((uint16_t) 0x129)
-+#define PPSMC_MSG_VCEDPM_Config               ((uint16_t) 0x12A)
-+#define PPSMC_MSG_ACPDPM_Config               ((uint16_t) 0x12B)
-+#define PPSMC_MSG_SAMUDPM_Config              ((uint16_t) 0x12C)
-+#define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
-+#define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
-+#define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
-+#define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
-+#define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
-+#define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
-+#define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
-+#define PPSMC_MSG_SetTDPLimit                 ((uint16_t) 0x134)
-+#define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
-+#define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
-+#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
-+#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
-+#define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
-+#define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
-+#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0x13b)
-+#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0x13c)
-+#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
-+#define PPSMC_MSG_IOMMUPowerOFF               ((uint16_t) 0x13e)
-+#define PPSMC_MSG_IOMMUPowerON                ((uint16_t) 0x13f)
-+#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
-+#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
-+#define PPSMC_MSG_NBDPM_ForceNominal          ((uint16_t) 0x142)
-+#define PPSMC_MSG_NBDPM_ForcePerformance      ((uint16_t) 0x143)
-+#define PPSMC_MSG_NBDPM_UnForce               ((uint16_t) 0x144)
-+#define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
-+#define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
-+#define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
-+#define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
-+#define PPSMC_MSG_EnableACDCGPIOInterrupt     ((uint16_t) 0x149)
-+#define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
-+#define PPSMC_MSG_SwitchToAC                  ((uint16_t) 0x14b)
-+#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0x14c)
-+#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x14d)
-+
-+#define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
-+#define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
-+#define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
-+#define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
-+#define PPSMC_MSG_LCLKDPM_Enable              ((uint16_t) 0x152)
-+#define PPSMC_MSG_LCLKDPM_Disable             ((uint16_t) 0x153)
-+#define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
-+#define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
-+#define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
-+#define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
-+#define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
-+#define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
-+#define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
-+#define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
-+#define PPSMC_MSG_LCLKDPM_SetEnabledMask      ((uint16_t) 0x15c)
-+#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
-+#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
-+#define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
-+#define PPSMC_MSG_MCLKDPM_GetEnabledMask      ((uint16_t) 0x160)
-+#define PPSMC_MSG_LCLKDPM_GetEnabledMask      ((uint16_t) 0x161)
-+#define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
-+#define PPSMC_MSG_UVDDPM_GetEnabledMask       ((uint16_t) 0x163)
-+#define PPSMC_MSG_SAMUDPM_GetEnabledMask      ((uint16_t) 0x164)
-+#define PPSMC_MSG_ACPDPM_GetEnabledMask       ((uint16_t) 0x165)
-+#define PPSMC_MSG_VCEDPM_GetEnabledMask       ((uint16_t) 0x166)
-+#define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
-+#define PPSMC_MSG_PCIeDPM_GetEnabledMask      ((uint16_t) 0x168)
-+#define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
-+#define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
-+#define PPSMC_MSG_DPM_AutoRotate_Mode         ((uint16_t) 0x16b)
-+#define PPSMC_MSG_DISPCLK_FROM_FCH            ((uint16_t) 0x16c)
-+#define PPSMC_MSG_DISPCLK_FROM_DFS            ((uint16_t) 0x16d)
-+#define PPSMC_MSG_DPREFCLK_FROM_FCH           ((uint16_t) 0x16e)
-+#define PPSMC_MSG_DPREFCLK_FROM_DFS           ((uint16_t) 0x16f)
-+#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
-+#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
-+#define PPSMC_MSG_SCLK_AutoDPM_ON             ((uint16_t) 0x172)
-+#define PPSMC_MSG_MCLK_AutoDPM_ON             ((uint16_t) 0x173)
-+#define PPSMC_MSG_LCLK_AutoDPM_ON             ((uint16_t) 0x174)
-+#define PPSMC_MSG_UVD_AutoDPM_ON              ((uint16_t) 0x175)
-+#define PPSMC_MSG_SAMU_AutoDPM_ON             ((uint16_t) 0x176)
-+#define PPSMC_MSG_ACP_AutoDPM_ON              ((uint16_t) 0x177)
-+#define PPSMC_MSG_VCE_AutoDPM_ON              ((uint16_t) 0x178)
-+#define PPSMC_MSG_PCIe_AutoDPM_ON             ((uint16_t) 0x179)
-+#define PPSMC_MSG_MASTER_AutoDPM_ON           ((uint16_t) 0x17a)
-+#define PPSMC_MSG_MASTER_AutoDPM_OFF          ((uint16_t) 0x17b)
-+#define PPSMC_MSG_DYNAMICDISPPHYPOWER         ((uint16_t) 0x17c)
-+#define PPSMC_MSG_CAC_COLLECTION_ON           ((uint16_t) 0x17d)
-+#define PPSMC_MSG_CAC_COLLECTION_OFF          ((uint16_t) 0x17e)
-+#define PPSMC_MSG_CAC_CORRELATION_ON          ((uint16_t) 0x17f)
-+#define PPSMC_MSG_CAC_CORRELATION_OFF         ((uint16_t) 0x180)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON        ((uint16_t) 0x181)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF       ((uint16_t) 0x182)
-+#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT     ((uint16_t) 0x184)
-+#define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
-+#define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
-+#define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
-+#define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
-+#define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
-+#define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
-+#define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
-+#define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
-+#define PPSMC_MSG_START_DRAM_LOGGING          ((uint16_t) 0x18D)
-+#define PPSMC_MSG_STOP_DRAM_LOGGING           ((uint16_t) 0x18E)
-+#define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
-+#define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
-+#define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
-+#define PPSMC_MSG_DisableACDCGPIOInterrupt    ((uint16_t) 0x192)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddc       ((uint16_t) 0x193)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddci      ((uint16_t) 0x194)
-+#define PPSMC_MSG_SetVidOffset_1              ((uint16_t) 0x195)
-+#define PPSMC_MSG_SetVidOffset_2              ((uint16_t) 0x207)
-+#define PPSMC_MSG_GetVidOffset_1              ((uint16_t) 0x196)
-+#define PPSMC_MSG_GetVidOffset_2              ((uint16_t) 0x208)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable    ((uint16_t) 0x197)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable   ((uint16_t) 0x198)
-+#define PPSMC_MSG_SetTjMax                    ((uint16_t) 0x199)
-+#define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
-+#define PPSMC_MSG_WaitForMclkSwitchFinish     ((uint16_t) 0x19B)
-+#define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
-+#define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
-+
-+#define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
-+#define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
-+#define PPSMC_MSG_API_GetSclkBusy             ((uint16_t) 0x202)
-+#define PPSMC_MSG_API_GetMclkBusy             ((uint16_t) 0x203)
-+#define PPSMC_MSG_API_GetAsicPower            ((uint16_t) 0x204)
-+#define PPSMC_MSG_SetFanRpmMax                ((uint16_t) 0x205)
-+#define PPSMC_MSG_SetFanSclkTarget            ((uint16_t) 0x206)
-+#define PPSMC_MSG_SetFanMinPwm                ((uint16_t) 0x209)
-+#define PPSMC_MSG_SetFanTemperatureTarget     ((uint16_t) 0x20A)
-+
-+#define PPSMC_MSG_BACO_StartMonitor           ((uint16_t) 0x240)
-+#define PPSMC_MSG_BACO_Cancel                 ((uint16_t) 0x241)
-+#define PPSMC_MSG_EnableVddGfx                ((uint16_t) 0x242)
-+#define PPSMC_MSG_DisableVddGfx               ((uint16_t) 0x243)
-+#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x244)
-+#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x245)
-+#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x246)
-+
-+#define PPSMC_MSG_DRV_DRAM_ADDR_HI            ((uint16_t) 0x250)
-+#define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
-+#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
-+#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x255)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI      ((uint16_t) 0x256)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO      ((uint16_t) 0x257)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI          ((uint16_t) 0x258)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO          ((uint16_t) 0x259)
-+#define PPSMC_MSG_LoadVBios                   ((uint16_t) 0x25A)
-+#define PPSMC_MSG_GetUcodeVersion             ((uint16_t) 0x25B)
-+#define DMCUSMC_MSG_PSREntry                  ((uint16_t) 0x25C)
-+#define DMCUSMC_MSG_PSRExit                   ((uint16_t) 0x25D)
-+#define PPSMC_MSG_EnableClockGatingFeature    ((uint16_t) 0x260)
-+#define PPSMC_MSG_DisableClockGatingFeature   ((uint16_t) 0x261)
-+#define PPSMC_MSG_IsDeviceRunning             ((uint16_t) 0x262)
-+#define PPSMC_MSG_LoadMetaData                ((uint16_t) 0x263)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Enable  ((uint16_t) 0x264)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
-+#define PPSMC_MSG_GetTelemetry1Slope          ((uint16_t) 0x266)
-+#define PPSMC_MSG_GetTelemetry1Offset         ((uint16_t) 0x267)
-+#define PPSMC_MSG_GetTelemetry2Slope          ((uint16_t) 0x268)
-+#define PPSMC_MSG_GetTelemetry2Offset         ((uint16_t) 0x269)
-+#define PPSMC_MSG_EnableAvfs                  ((uint16_t) 0x26A)
-+#define PPSMC_MSG_DisableAvfs                 ((uint16_t) 0x26B)
-+
-+#define PPSMC_MSG_PerformBtc                  ((uint16_t) 0x26C)
-+#define PPSMC_MSG_VftTableIsValid             ((uint16_t) 0x275)
-+#define PPSMC_MSG_UseNewGPIOScheme            ((uint16_t) 0x277)
-+#define PPSMC_MSG_GetEnabledPsm               ((uint16_t) 0x400)
-+#define PPSMC_MSG_AgmStartPsm                 ((uint16_t) 0x401)
-+#define PPSMC_MSG_AgmReadPsm                  ((uint16_t) 0x402)
-+#define PPSMC_MSG_AgmResetPsm                 ((uint16_t) 0x403)
-+#define PPSMC_MSG_ReadVftCell                 ((uint16_t) 0x404)
-+
-+#define PPSMC_MSG_GFX_CU_PG_ENABLE            ((uint16_t) 0x280)
-+#define PPSMC_MSG_GFX_CU_PG_DISABLE           ((uint16_t) 0x281)
-+
-+#define PPSMC_MSG_SetGpuPllDfsForSclk         ((uint16_t) 0x300)
-+
-+typedef uint16_t PPSMC_Msg;
-+
-+#define PPSMC_EVENT_STATUS_THERMAL          0x00000001
-+#define PPSMC_EVENT_STATUS_REGULATORHOT     0x00000002
-+#define PPSMC_EVENT_STATUS_DC               0x00000004
-+
-+#pragma pack(pop)
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
-new file mode 100644
-index 0000000..997811c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
-@@ -0,0 +1,10088 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _ELLESMERE_PWRVIRUS_H
-+#define _ELLESMERE_PWRVIRUS_H
-+
-+#define mmSMC_IND_INDEX_11                              0x01AC
-+#define mmSMC_IND_DATA_11                               0x01AD
-+#define mmCP_HYP_MEC1_UCODE_ADDR	0xf81a
-+#define mmCP_HYP_MEC1_UCODE_DATA	0xf81b
-+#define mmCP_HYP_MEC2_UCODE_ADDR	0xf81c
-+#define mmCP_HYP_MEC2_UCODE_DATA	0xf81d
-+
-+enum PWR_Command {
-+	PwrCmdNull = 0,
-+	PwrCmdWrite,
-+	PwrCmdEnd,
-+	PwrCmdMax
-+};
-+
-+typedef enum PWR_Command PWR_Command;
-+
-+struct PWR_Command_Table {
-+	PWR_Command        command;
-+	uint32_t              data;
-+	uint32_t reg;
-+};
-+
-+typedef struct PWR_Command_Table PWR_Command_Table;
-+
-+
-+#define PWR_VIRUS_TABLE_SIZE  10031
-+
-+static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
-+	{ PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+	{ PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
-+	{ PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
-+	{ PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL                              },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL                              },
-+	{ PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL                                 },
-+	{ PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE                          },
-+	{ PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG                          },
-+	{ PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
-+	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR                   },
-+	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1                    },
-+	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+	{ PwrCmdEnd,   0x00000000, 0x00000000                                 },
-+};
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74.h b/drivers/gpu/drm/amd/powerplay/inc/smu74.h
-new file mode 100644
-index 0000000..1a12d85
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74.h
-@@ -0,0 +1,774 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+
-+#ifndef SMU74_H
-+#define SMU74_H
-+
-+#pragma pack(push, 1)
-+
-+#define SMU__DGPU_ONLY
-+
-+#define SMU__NUM_SCLK_DPM_STATE  8
-+#define SMU__NUM_MCLK_DPM_LEVELS 4
-+#define SMU__NUM_LCLK_DPM_LEVELS 8
-+#define SMU__NUM_PCIE_DPM_LEVELS 8
-+
-+enum SID_OPTION {
-+	SID_OPTION_HI,
-+	SID_OPTION_LO,
-+	SID_OPTION_COUNT
-+};
-+
-+enum Poly3rdOrderCoeff {
-+	LEAKAGE_TEMPERATURE_SCALAR,
-+	LEAKAGE_VOLTAGE_SCALAR,
-+	DYNAMIC_VOLTAGE_SCALAR,
-+	POLY_3RD_ORDER_COUNT
-+};
-+
-+struct SMU7_Poly3rdOrder_Data {
-+	int32_t a;
-+	int32_t b;
-+	int32_t c;
-+	int32_t d;
-+	uint8_t a_shift;
-+	uint8_t b_shift;
-+	uint8_t c_shift;
-+	uint8_t x_shift;
-+};
-+
-+typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
-+
-+struct Power_Calculator_Data {
-+	uint16_t NoLoadVoltage;
-+	uint16_t LoadVoltage;
-+	uint16_t Resistance;
-+	uint16_t Temperature;
-+	uint16_t BaseLeakage;
-+	uint16_t LkgTempScalar;
-+	uint16_t LkgVoltScalar;
-+	uint16_t LkgAreaScalar;
-+	uint16_t LkgPower;
-+	uint16_t DynVoltScalar;
-+	uint32_t Cac;
-+	uint32_t DynPower;
-+	uint32_t TotalCurrent;
-+	uint32_t TotalPower;
-+};
-+
-+typedef struct Power_Calculator_Data PowerCalculatorData_t;
-+
-+struct Gc_Cac_Weight_Data {
-+	uint8_t index;
-+	uint32_t value;
-+};
-+
-+typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
-+
-+
-+typedef struct {
-+	uint32_t high;
-+	uint32_t low;
-+} data_64_t;
-+
-+typedef struct {
-+	data_64_t high;
-+	data_64_t low;
-+} data_128_t;
-+
-+#define SMU7_CONTEXT_ID_SMC        1
-+#define SMU7_CONTEXT_ID_VBIOS      2
-+
-+#define SMU74_MAX_LEVELS_VDDC            16
-+#define SMU74_MAX_LEVELS_VDDGFX          16
-+#define SMU74_MAX_LEVELS_VDDCI           8
-+#define SMU74_MAX_LEVELS_MVDD            4
-+
-+#define SMU_MAX_SMIO_LEVELS              4
-+
-+#define SMU74_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   /* SCLK + SQ DPM + ULV */
-+#define SMU74_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
-+#define SMU74_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  /* LCLK Levels */
-+#define SMU74_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  /* PCIe speed and number of lanes */
-+#define SMU74_MAX_LEVELS_UVD             8   /* VCLK/DCLK levels for UVD */
-+#define SMU74_MAX_LEVELS_VCE             8   /* ECLK levels for VCE */
-+#define SMU74_MAX_LEVELS_ACP             8   /* ACLK levels for ACP */
-+#define SMU74_MAX_LEVELS_SAMU            8   /* SAMCLK levels for SAMU */
-+#define SMU74_MAX_ENTRIES_SMIO           32  /* Number of entries in SMIO table */
-+
-+#define DPM_NO_LIMIT 0
-+#define DPM_NO_UP 1
-+#define DPM_GO_DOWN 2
-+#define DPM_GO_UP 3
-+
-+#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
-+#define SMU7_FIRST_DPM_MEMORY_LEVEL      0
-+
-+#define GPIO_CLAMP_MODE_VRHOT      1
-+#define GPIO_CLAMP_MODE_THERM      2
-+#define GPIO_CLAMP_MODE_DC         4
-+
-+#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
-+#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
-+#define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
-+#define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
-+#define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
-+#define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
-+#define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
-+#define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
-+#define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
-+#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
-+#define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
-+#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
-+#define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
-+
-+/* Virtualization Defines */
-+#define CG_XDMA_MASK  0x1
-+#define CG_XDMA_SHIFT 0
-+#define CG_UVD_MASK   0x2
-+#define CG_UVD_SHIFT  1
-+#define CG_VCE_MASK   0x4
-+#define CG_VCE_SHIFT  2
-+#define CG_SAMU_MASK  0x8
-+#define CG_SAMU_SHIFT 3
-+#define CG_GFX_MASK   0x10
-+#define CG_GFX_SHIFT  4
-+#define CG_SDMA_MASK  0x20
-+#define CG_SDMA_SHIFT 5
-+#define CG_HDP_MASK   0x40
-+#define CG_HDP_SHIFT  6
-+#define CG_MC_MASK    0x80
-+#define CG_MC_SHIFT   7
-+#define CG_DRM_MASK   0x100
-+#define CG_DRM_SHIFT  8
-+#define CG_ROM_MASK   0x200
-+#define CG_ROM_SHIFT  9
-+#define CG_BIF_MASK   0x400
-+#define CG_BIF_SHIFT  10
-+
-+
-+#define SMU74_DTE_ITERATIONS 5
-+#define SMU74_DTE_SOURCES 3
-+#define SMU74_DTE_SINKS 1
-+#define SMU74_NUM_CPU_TES 0
-+#define SMU74_NUM_GPU_TES 1
-+#define SMU74_NUM_NON_TES 2
-+#define SMU74_DTE_FAN_SCALAR_MIN 0x100
-+#define SMU74_DTE_FAN_SCALAR_MAX 0x166
-+#define SMU74_DTE_FAN_TEMP_MAX 93
-+#define SMU74_DTE_FAN_TEMP_MIN 83
-+
-+
-+#if defined SMU__FUSION_ONLY
-+#define SMU7_DTE_ITERATIONS 5
-+#define SMU7_DTE_SOURCES 5
-+#define SMU7_DTE_SINKS 3
-+#define SMU7_NUM_CPU_TES 2
-+#define SMU7_NUM_GPU_TES 1
-+#define SMU7_NUM_NON_TES 2
-+#endif
-+
-+struct SMU7_HystController_Data {
-+	uint8_t waterfall_up;
-+	uint8_t waterfall_down;
-+	uint8_t waterfall_limit;
-+	uint8_t spare;
-+	uint16_t release_cnt;
-+	uint16_t release_limit;
-+};
-+
-+typedef struct SMU7_HystController_Data SMU7_HystController_Data;
-+
-+struct SMU74_PIDController {
-+	uint32_t Ki;
-+	int32_t LFWindupUpperLim;
-+	int32_t LFWindupLowerLim;
-+	uint32_t StatePrecision;
-+	uint32_t LfPrecision;
-+	uint32_t LfOffset;
-+	uint32_t MaxState;
-+	uint32_t MaxLfFraction;
-+	uint32_t StateShift;
-+};
-+
-+typedef struct SMU74_PIDController SMU74_PIDController;
-+
-+struct SMU7_LocalDpmScoreboard {
-+	uint32_t PercentageBusy;
-+
-+	int32_t  PIDError;
-+	int32_t  PIDIntegral;
-+	int32_t  PIDOutput;
-+
-+	uint32_t SigmaDeltaAccum;
-+	uint32_t SigmaDeltaOutput;
-+	uint32_t SigmaDeltaLevel;
-+
-+	uint32_t UtilizationSetpoint;
-+
-+	uint8_t  TdpClampMode;
-+	uint8_t  TdcClampMode;
-+	uint8_t  ThermClampMode;
-+	uint8_t  VoltageBusy;
-+
-+	int8_t   CurrLevel;
-+	int8_t   TargLevel;
-+	uint8_t  LevelChangeInProgress;
-+	uint8_t  UpHyst;
-+
-+	uint8_t  DownHyst;
-+	uint8_t  VoltageDownHyst;
-+	uint8_t  DpmEnable;
-+	uint8_t  DpmRunning;
-+
-+	uint8_t  DpmForce;
-+	uint8_t  DpmForceLevel;
-+	uint8_t  DisplayWatermark;
-+	uint8_t  McArbIndex;
-+
-+	uint32_t MinimumPerfSclk;
-+
-+	uint8_t  AcpiReq;
-+	uint8_t  AcpiAck;
-+	uint8_t  GfxClkSlow;
-+	uint8_t  GpioClampMode;
-+
-+	uint8_t  spare2;
-+	uint8_t  EnabledLevelsChange;
-+	uint8_t  DteClampMode;
-+	uint8_t  FpsClampMode;
-+
-+	uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_GRAPHICS];
-+	uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_GRAPHICS];
-+
-+	void     (*TargetStateCalculator)(uint8_t);
-+	void     (*SavedTargetStateCalculator)(uint8_t);
-+
-+	uint16_t AutoDpmInterval;
-+	uint16_t AutoDpmRange;
-+
-+	uint8_t  FpsEnabled;
-+	uint8_t  MaxPerfLevel;
-+	uint8_t  AllowLowClkInterruptToHost;
-+	uint8_t  FpsRunning;
-+
-+	uint32_t MaxAllowedFrequency;
-+
-+	uint32_t FilteredSclkFrequency;
-+	uint32_t LastSclkFrequency;
-+	uint32_t FilteredSclkFrequencyCnt;
-+
-+	uint8_t MinPerfLevel;
-+	uint8_t padding[3];
-+
-+	uint16_t FpsAlpha;
-+	uint16_t DeltaTime;
-+	uint32_t CurrentFps;
-+	uint32_t FilteredFps;
-+	uint32_t FrameCount;
-+	uint32_t FrameCountLast;
-+	uint16_t FpsTargetScalar;
-+	uint16_t FpsWaterfallLimitScalar;
-+	uint16_t FpsAlphaScalar;
-+	uint16_t spare8;
-+	SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
-+
-+#define SMU7_MAX_VOLTAGE_CLIENTS 12
-+
-+typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
-+
-+#define VDDC_MASK    0x00007FFF
-+#define VDDC_SHIFT   0
-+#define VDDCI_MASK   0x3FFF8000
-+#define VDDCI_SHIFT  15
-+#define PHASES_MASK  0xC0000000
-+#define PHASES_SHIFT 30
-+
-+typedef uint32_t SMU_VoltageLevel;
-+
-+struct SMU7_VoltageScoreboard {
-+
-+	SMU_VoltageLevel TargetVoltage;
-+	uint16_t MaxVid;
-+	uint8_t  HighestVidOffset;
-+	uint8_t  CurrentVidOffset;
-+
-+	uint16_t CurrentVddc;
-+	uint16_t CurrentVddci;
-+
-+
-+	uint8_t  ControllerBusy;
-+	uint8_t  CurrentVid;
-+	uint8_t  CurrentVddciVid;
-+	uint8_t  padding;
-+
-+	SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
-+	SMU_VoltageLevel TargetVoltageState;
-+	uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
-+
-+	uint8_t  padding2;
-+	uint8_t  padding3;
-+	uint8_t  ControllerEnable;
-+	uint8_t  ControllerRunning;
-+	uint16_t CurrentStdVoltageHiSidd;
-+	uint16_t CurrentStdVoltageLoSidd;
-+	uint8_t  OverrideVoltage;
-+	uint8_t  padding4;
-+	uint8_t  padding5;
-+	uint8_t  CurrentPhases;
-+
-+	VoltageChangeHandler_t ChangeVddc;
-+
-+	VoltageChangeHandler_t ChangeVddci;
-+	VoltageChangeHandler_t ChangePhase;
-+	VoltageChangeHandler_t ChangeMvdd;
-+
-+	VoltageChangeHandler_t functionLinks[6];
-+
-+	uint16_t *VddcFollower1;
-+
-+	int16_t  Driver_OD_RequestedVidOffset1;
-+	int16_t  Driver_OD_RequestedVidOffset2;
-+};
-+
-+typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
-+
-+#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
-+
-+struct SMU7_PCIeLinkSpeedScoreboard {
-+	uint8_t     DpmEnable;
-+	uint8_t     DpmRunning;
-+	uint8_t     DpmForce;
-+	uint8_t     DpmForceLevel;
-+
-+	uint8_t     CurrentLinkSpeed;
-+	uint8_t     EnabledLevelsChange;
-+	uint16_t    AutoDpmInterval;
-+
-+	uint16_t    AutoDpmRange;
-+	uint16_t    AutoDpmCount;
-+
-+	uint8_t     DpmMode;
-+	uint8_t     AcpiReq;
-+	uint8_t     AcpiAck;
-+	uint8_t     CurrentLinkLevel;
-+
-+};
-+
-+typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
-+
-+#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
-+#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
-+
-+#define SMU7_SCALE_I  7
-+#define SMU7_SCALE_R 12
-+
-+struct SMU7_PowerScoreboard {
-+	PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
-+
-+	uint32_t TotalGpuPower;
-+	uint32_t TdcCurrent;
-+
-+	uint16_t   VddciTotalPower;
-+	uint16_t   sparesasfsdfd;
-+	uint16_t   Vddr1Power;
-+	uint16_t   RocPower;
-+
-+	uint16_t   CalcMeasPowerBlend;
-+	uint8_t    SidOptionPower;
-+	uint8_t    SidOptionCurrent;
-+
-+	uint32_t   WinTime;
-+
-+	uint16_t Telemetry_1_slope;
-+	uint16_t Telemetry_2_slope;
-+	int32_t Telemetry_1_offset;
-+	int32_t Telemetry_2_offset;
-+
-+	uint32_t VddcCurrentTelemetry;
-+	uint32_t VddGfxCurrentTelemetry;
-+	uint32_t VddcPowerTelemetry;
-+	uint32_t VddGfxPowerTelemetry;
-+	uint32_t VddciPowerTelemetry;
-+
-+	uint32_t VddcPower;
-+	uint32_t VddGfxPower;
-+	uint32_t VddciPower;
-+
-+	uint32_t TelemetryCurrent[2];
-+	uint32_t TelemetryVoltage[2];
-+	uint32_t TelemetryPower[2];
-+};
-+
-+typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
-+
-+struct SMU7_ThermalScoreboard {
-+	int16_t  GpuLimit;
-+	int16_t  GpuHyst;
-+	uint16_t CurrGnbTemp;
-+	uint16_t FilteredGnbTemp;
-+
-+	uint8_t  ControllerEnable;
-+	uint8_t  ControllerRunning;
-+	uint8_t  AutoTmonCalInterval;
-+	uint8_t  AutoTmonCalEnable;
-+
-+	uint8_t  ThermalDpmEnabled;
-+	uint8_t  SclkEnabledMask;
-+	uint8_t  spare[2];
-+	int32_t  temperature_gradient;
-+
-+	SMU7_HystController_Data HystControllerData;
-+	int32_t  WeightedSensorTemperature;
-+	uint16_t TemperatureLimit[SMU74_MAX_LEVELS_GRAPHICS];
-+	uint32_t Alpha;
-+};
-+
-+typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
-+
-+#define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
-+#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
-+#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
-+#define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
-+#define SMU7_UVD_DPM_CONFIG_MASK                         0x10
-+#define SMU7_VCE_DPM_CONFIG_MASK                         0x20
-+#define SMU7_ACP_DPM_CONFIG_MASK                         0x40
-+#define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
-+#define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
-+
-+#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
-+#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
-+#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
-+#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
-+#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
-+#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
-+
-+/* All 'soft registers' should be uint32_t. */
-+struct SMU74_SoftRegisters {
-+	uint32_t        RefClockFrequency;
-+	uint32_t        PmTimerPeriod;
-+	uint32_t        FeatureEnables;
-+
-+	uint32_t        PreVBlankGap;
-+	uint32_t        VBlankTimeout;
-+	uint32_t        TrainTimeGap;
-+
-+	uint32_t        MvddSwitchTime;
-+	uint32_t        LongestAcpiTrainTime;
-+	uint32_t        AcpiDelay;
-+	uint32_t        G5TrainTime;
-+	uint32_t        DelayMpllPwron;
-+	uint32_t        VoltageChangeTimeout;
-+
-+	uint32_t        HandshakeDisables;
-+
-+	uint8_t         DisplayPhy1Config;
-+	uint8_t         DisplayPhy2Config;
-+	uint8_t         DisplayPhy3Config;
-+	uint8_t         DisplayPhy4Config;
-+
-+	uint8_t         DisplayPhy5Config;
-+	uint8_t         DisplayPhy6Config;
-+	uint8_t         DisplayPhy7Config;
-+	uint8_t         DisplayPhy8Config;
-+
-+	uint32_t        AverageGraphicsActivity;
-+	uint32_t        AverageMemoryActivity;
-+	uint32_t        AverageGioActivity;
-+
-+	uint8_t         SClkDpmEnabledLevels;
-+	uint8_t         MClkDpmEnabledLevels;
-+	uint8_t         LClkDpmEnabledLevels;
-+	uint8_t         PCIeDpmEnabledLevels;
-+
-+	uint8_t         UVDDpmEnabledLevels;
-+	uint8_t         SAMUDpmEnabledLevels;
-+	uint8_t         ACPDpmEnabledLevels;
-+	uint8_t         VCEDpmEnabledLevels;
-+
-+	uint32_t        DRAM_LOG_ADDR_H;
-+	uint32_t        DRAM_LOG_ADDR_L;
-+	uint32_t        DRAM_LOG_PHY_ADDR_H;
-+	uint32_t        DRAM_LOG_PHY_ADDR_L;
-+	uint32_t        DRAM_LOG_BUFF_SIZE;
-+	uint32_t        UlvEnterCount;
-+	uint32_t        UlvTime;
-+	uint32_t        UcodeLoadStatus;
-+	uint32_t        AllowMvddSwitch;
-+	uint8_t         Activity_Weight;
-+	uint8_t         Reserved8[3];
-+};
-+
-+typedef struct SMU74_SoftRegisters SMU74_SoftRegisters;
-+
-+struct SMU74_Firmware_Header {
-+	uint32_t Digest[5];
-+	uint32_t Version;
-+	uint32_t HeaderSize;
-+	uint32_t Flags;
-+	uint32_t EntryPoint;
-+	uint32_t CodeSize;
-+	uint32_t ImageSize;
-+
-+	uint32_t Rtos;
-+	uint32_t SoftRegisters;
-+	uint32_t DpmTable;
-+	uint32_t FanTable;
-+	uint32_t CacConfigTable;
-+	uint32_t CacStatusTable;
-+
-+
-+	uint32_t mcRegisterTable;
-+
-+
-+	uint32_t mcArbDramTimingTable;
-+
-+
-+
-+
-+	uint32_t PmFuseTable;
-+	uint32_t Globals;
-+	uint32_t ClockStretcherTable;
-+	uint32_t VftTable;
-+	uint32_t Reserved[21];
-+	uint32_t Signature;
-+};
-+
-+typedef struct SMU74_Firmware_Header SMU74_Firmware_Header;
-+
-+#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
-+
-+enum  DisplayConfig {
-+	PowerDown = 1,
-+	DP54x4,
-+	DP54x2,
-+	DP54x1,
-+	DP27x4,
-+	DP27x2,
-+	DP27x1,
-+	HDMI297,
-+	HDMI162,
-+	LVDS,
-+	DP324x4,
-+	DP324x2,
-+	DP324x1
-+};
-+
-+
-+#define MC_BLOCK_COUNT 1
-+#define CPL_BLOCK_COUNT 5
-+#define SE_BLOCK_COUNT 15
-+#define GC_BLOCK_COUNT 24
-+
-+struct SMU7_Local_Cac {
-+	uint8_t BlockId;
-+	uint8_t SignalId;
-+	uint8_t Threshold;
-+	uint8_t Padding;
-+};
-+
-+typedef struct SMU7_Local_Cac SMU7_Local_Cac;
-+
-+struct SMU7_Local_Cac_Table {
-+
-+	SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
-+	SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
-+	SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
-+	SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
-+};
-+
-+typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
-+
-+#pragma pack(pop)
-+
-+/* Description of Clock Gating bitmask for Tonga:
-+ * System Clock Gating
-+ */
-+#define CG_SYS_BITMASK_FIRST_BIT      0  /* First bit of Sys CG bitmask */
-+#define CG_SYS_BITMASK_LAST_BIT       9  /* Last bit of Sys CG bitmask */
-+#define CG_SYS_BIF_MGLS_SHIFT         0
-+#define CG_SYS_ROM_SHIFT              1
-+#define CG_SYS_MC_MGCG_SHIFT          2
-+#define CG_SYS_MC_MGLS_SHIFT          3
-+#define CG_SYS_SDMA_MGCG_SHIFT        4
-+#define CG_SYS_SDMA_MGLS_SHIFT        5
-+#define CG_SYS_DRM_MGCG_SHIFT         6
-+#define CG_SYS_HDP_MGCG_SHIFT         7
-+#define CG_SYS_HDP_MGLS_SHIFT         8
-+#define CG_SYS_DRM_MGLS_SHIFT         9
-+#define CG_SYS_BIF_MGCG_SHIFT         10
-+
-+#define CG_SYS_BIF_MGLS_MASK          0x1
-+#define CG_SYS_ROM_MASK               0x2
-+#define CG_SYS_MC_MGCG_MASK           0x4
-+#define CG_SYS_MC_MGLS_MASK           0x8
-+#define CG_SYS_SDMA_MGCG_MASK         0x10
-+#define CG_SYS_SDMA_MGLS_MASK         0x20
-+#define CG_SYS_DRM_MGCG_MASK          0x40
-+#define CG_SYS_HDP_MGCG_MASK          0x80
-+#define CG_SYS_HDP_MGLS_MASK          0x100
-+#define CG_SYS_DRM_MGLS_MASK          0x200
-+#define CG_SYS_BIF_MGCG_MASK          0x400
-+
-+/* Graphics Clock Gating */
-+#define CG_GFX_BITMASK_FIRST_BIT      16 /* First bit of Gfx CG bitmask */
-+#define CG_GFX_BITMASK_LAST_BIT       24 /* Last bit of Gfx CG bitmask */
-+
-+#define CG_GFX_CGCG_SHIFT             16
-+#define CG_GFX_CGLS_SHIFT             17
-+#define CG_CPF_MGCG_SHIFT             18
-+#define CG_RLC_MGCG_SHIFT             19
-+#define CG_GFX_OTHERS_MGCG_SHIFT      20
-+#define CG_GFX_3DCG_SHIFT             21
-+#define CG_GFX_3DLS_SHIFT             22
-+#define CG_GFX_RLC_LS_SHIFT           23
-+#define CG_GFX_CP_LS_SHIFT            24
-+
-+#define CG_GFX_CGCG_MASK              0x00010000
-+#define CG_GFX_CGLS_MASK              0x00020000
-+#define CG_CPF_MGCG_MASK              0x00040000
-+#define CG_RLC_MGCG_MASK              0x00080000
-+#define CG_GFX_OTHERS_MGCG_MASK       0x00100000
-+#define CG_GFX_3DCG_MASK              0x00200000
-+#define CG_GFX_3DLS_MASK              0x00400000
-+#define CG_GFX_RLC_LS_MASK            0x00800000
-+#define CG_GFX_CP_LS_MASK             0x01000000
-+
-+
-+/* Voltage Regulator Configuration
-+VR Config info is contained in dpmTable.VRConfig */
-+
-+#define VRCONF_VDDC_MASK         0x000000FF
-+#define VRCONF_VDDC_SHIFT        0
-+#define VRCONF_VDDGFX_MASK       0x0000FF00
-+#define VRCONF_VDDGFX_SHIFT      8
-+#define VRCONF_VDDCI_MASK        0x00FF0000
-+#define VRCONF_VDDCI_SHIFT       16
-+#define VRCONF_MVDD_MASK         0xFF000000
-+#define VRCONF_MVDD_SHIFT        24
-+
-+#define VR_MERGED_WITH_VDDC      0
-+#define VR_SVI2_PLANE_1          1
-+#define VR_SVI2_PLANE_2          2
-+#define VR_SMIO_PATTERN_1        3
-+#define VR_SMIO_PATTERN_2        4
-+#define VR_STATIC_VOLTAGE        5
-+
-+/* Clock Stretcher Configuration */
-+
-+#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
-+#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
-+
-+/* The 'settings' field is subdivided in the following way: */
-+#define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
-+#define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
-+#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
-+#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
-+#define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
-+#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
-+
-+struct SMU_ClockStretcherDataTableEntry {
-+	uint8_t minVID;
-+	uint8_t maxVID;
-+
-+
-+	uint16_t setting;
-+};
-+typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
-+
-+struct SMU_ClockStretcherDataTable {
-+	SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
-+};
-+typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
-+
-+struct SMU_CKS_LOOKUPTableEntry {
-+	uint16_t minFreq;
-+	uint16_t maxFreq;
-+
-+	uint8_t setting;
-+	uint8_t padding[3];
-+};
-+typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
-+
-+struct SMU_CKS_LOOKUPTable {
-+	SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
-+};
-+typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
-+
-+struct AgmAvfsData_t {
-+	uint16_t avgPsmCount[28];
-+	uint16_t minPsmCount[28];
-+};
-+
-+typedef struct AgmAvfsData_t AgmAvfsData_t;
-+
-+enum VFT_COLUMNS {
-+	SCLK0,
-+	SCLK1,
-+	SCLK2,
-+	SCLK3,
-+	SCLK4,
-+	SCLK5,
-+	SCLK6,
-+	SCLK7,
-+
-+	NUM_VFT_COLUMNS
-+};
-+
-+#define VFT_TABLE_DEFINED
-+
-+#define TEMP_RANGE_MAXSTEPS 12
-+
-+struct VFT_CELL_t {
-+	uint16_t Voltage;
-+};
-+
-+typedef struct VFT_CELL_t VFT_CELL_t;
-+
-+struct VFT_TABLE_t {
-+	VFT_CELL_t    Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
-+	uint16_t      AvfsGbv[NUM_VFT_COLUMNS];
-+	uint16_t      BtcGbv[NUM_VFT_COLUMNS];
-+	uint16_t      Temperature[TEMP_RANGE_MAXSTEPS];
-+
-+	uint8_t       NumTemperatureSteps;
-+	uint8_t       padding[3];
-+};
-+
-+typedef struct VFT_TABLE_t VFT_TABLE_t;
-+
-+
-+#endif
-+
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-new file mode 100644
-index 0000000..733fa37
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-@@ -0,0 +1,780 @@
-+/*
-+ * Copyright 2014 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef SMU74_DISCRETE_H
-+#define SMU74_DISCRETE_H
-+
-+#include "smu74.h"
-+
-+#pragma pack(push, 1)
-+
-+
-+#define NUM_SCLK_RANGE 8
-+
-+#define VCO_3_6 1
-+#define VCO_2_4 3
-+
-+#define POSTDIV_DIV_BY_1  0
-+#define POSTDIV_DIV_BY_2  1
-+#define POSTDIV_DIV_BY_4  2
-+#define POSTDIV_DIV_BY_8  3
-+#define POSTDIV_DIV_BY_16 4
-+
-+struct sclkFcwRange_t {
-+	uint8_t  vco_setting;
-+	uint8_t  postdiv;
-+	uint16_t fcw_pcc;
-+
-+	uint16_t fcw_trans_upper;
-+	uint16_t fcw_trans_lower;
-+};
-+typedef struct sclkFcwRange_t sclkFcwRange_t;
-+
-+struct SMIO_Pattern {
-+	uint16_t Voltage;
-+	uint8_t  Smio;
-+	uint8_t  padding;
-+};
-+
-+typedef struct SMIO_Pattern SMIO_Pattern;
-+
-+struct SMIO_Table {
-+	SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
-+};
-+
-+typedef struct SMIO_Table SMIO_Table;
-+
-+struct SMU_SclkSetting {
-+	uint32_t    SclkFrequency;
-+	uint16_t    Fcw_int;
-+	uint16_t    Fcw_frac;
-+	uint16_t    Pcc_fcw_int;
-+	uint8_t     PllRange;
-+	uint8_t     SSc_En;
-+	uint16_t    Fcw1_int;
-+	uint16_t    Fcw1_frac;
-+};
-+typedef struct SMU_SclkSetting SMU_SclkSetting;
-+
-+struct SMU74_Discrete_GraphicsLevel {
-+	SMU_VoltageLevel MinVoltage;
-+	uint8_t     pcieDpmLevel;
-+	uint8_t     DeepSleepDivId;
-+	uint16_t    ActivityLevel;
-+	uint32_t    CgSpllFuncCntl3;
-+	uint32_t    CgSpllFuncCntl4;
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+	uint8_t     SclkDid;
-+	uint8_t     padding;
-+	uint8_t     EnabledForActivity;
-+	uint8_t     EnabledForThrottle;
-+	uint8_t     UpHyst;
-+	uint8_t     DownHyst;
-+	uint8_t     VoltageDownHyst;
-+	uint8_t     PowerThrottle;
-+	SMU_SclkSetting SclkSetting;
-+};
-+
-+typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
-+
-+struct SMU74_Discrete_ACPILevel {
-+	uint32_t    Flags;
-+	SMU_VoltageLevel MinVoltage;
-+	uint32_t    SclkFrequency;
-+	uint8_t     SclkDid;
-+	uint8_t     DisplayWatermark;
-+	uint8_t     DeepSleepDivId;
-+	uint8_t     padding;
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+
-+	SMU_SclkSetting SclkSetting;
-+};
-+
-+typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
-+
-+struct SMU74_Discrete_Ulv {
-+	uint32_t    CcPwrDynRm;
-+	uint32_t    CcPwrDynRm1;
-+	uint16_t    VddcOffset;
-+	uint8_t     VddcOffsetVid;
-+	uint8_t     VddcPhase;
-+	uint32_t    Reserved;
-+};
-+
-+typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
-+
-+struct SMU74_Discrete_MemoryLevel {
-+	SMU_VoltageLevel MinVoltage;
-+	uint32_t    MinMvdd;
-+
-+	uint32_t    MclkFrequency;
-+
-+	uint8_t     StutterEnable;
-+	uint8_t     EnabledForThrottle;
-+	uint8_t     EnabledForActivity;
-+	uint8_t     padding_0;
-+
-+	uint8_t     UpHyst;
-+	uint8_t     DownHyst;
-+	uint8_t     VoltageDownHyst;
-+	uint8_t     padding_1;
-+
-+	uint16_t    ActivityLevel;
-+	uint8_t     DisplayWatermark;
-+	uint8_t     Reserved;
-+};
-+
-+typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
-+
-+struct SMU74_Discrete_LinkLevel {
-+	uint8_t     PcieGenSpeed;
-+	uint8_t     PcieLaneCount;
-+	uint8_t     EnabledForActivity;
-+	uint8_t     SPC;
-+	uint32_t    DownThreshold;
-+	uint32_t    UpThreshold;
-+	uint32_t    Reserved;
-+};
-+
-+typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
-+
-+struct SMU74_Discrete_MCArbDramTimingTableEntry {
-+	uint32_t McArbDramTiming;
-+	uint32_t McArbDramTiming2;
-+	uint8_t  McArbBurstTime;
-+	uint8_t  padding[3];
-+};
-+
-+typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
-+
-+struct SMU74_Discrete_MCArbDramTimingTable {
-+	SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
-+};
-+
-+typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
-+
-+struct SMU74_Discrete_UvdLevel {
-+	uint32_t VclkFrequency;
-+	uint32_t DclkFrequency;
-+	SMU_VoltageLevel MinVoltage;
-+	uint8_t  VclkDivider;
-+	uint8_t  DclkDivider;
-+	uint8_t  padding[2];
-+};
-+
-+typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
-+
-+struct SMU74_Discrete_ExtClkLevel {
-+	uint32_t Frequency;
-+	SMU_VoltageLevel MinVoltage;
-+	uint8_t  Divider;
-+	uint8_t  padding[3];
-+};
-+
-+typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
-+
-+struct SMU74_Discrete_StateInfo {
-+	uint32_t SclkFrequency;
-+	uint32_t MclkFrequency;
-+	uint32_t VclkFrequency;
-+	uint32_t DclkFrequency;
-+	uint32_t SamclkFrequency;
-+	uint32_t AclkFrequency;
-+	uint32_t EclkFrequency;
-+	uint16_t MvddVoltage;
-+	uint16_t padding16;
-+	uint8_t  DisplayWatermark;
-+	uint8_t  McArbIndex;
-+	uint8_t  McRegIndex;
-+	uint8_t  SeqIndex;
-+	uint8_t  SclkDid;
-+	int8_t   SclkIndex;
-+	int8_t   MclkIndex;
-+	uint8_t  PCIeGen;
-+};
-+
-+typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
-+
-+struct SMU74_Discrete_DpmTable {
-+
-+	SMU74_PIDController                  GraphicsPIDController;
-+	SMU74_PIDController                  MemoryPIDController;
-+	SMU74_PIDController                  LinkPIDController;
-+
-+	uint32_t                            SystemFlags;
-+
-+	uint32_t                            VRConfig;
-+	uint32_t                            SmioMask1;
-+	uint32_t                            SmioMask2;
-+	SMIO_Table                          SmioTable1;
-+	SMIO_Table                          SmioTable2;
-+
-+	uint32_t                            MvddLevelCount;
-+
-+
-+	uint8_t                             BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
-+	uint8_t                             BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
-+	uint8_t                             BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
-+
-+	uint8_t                             GraphicsDpmLevelCount;
-+	uint8_t                             MemoryDpmLevelCount;
-+	uint8_t                             LinkLevelCount;
-+	uint8_t                             MasterDeepSleepControl;
-+
-+	uint8_t                             UvdLevelCount;
-+	uint8_t                             VceLevelCount;
-+	uint8_t                             AcpLevelCount;
-+	uint8_t                             SamuLevelCount;
-+
-+	uint8_t                             ThermOutGpio;
-+	uint8_t                             ThermOutPolarity;
-+	uint8_t                             ThermOutMode;
-+	uint8_t                             BootPhases;
-+	uint32_t                            Reserved[4];
-+
-+	SMU74_Discrete_GraphicsLevel        GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
-+	SMU74_Discrete_MemoryLevel          MemoryACPILevel;
-+	SMU74_Discrete_MemoryLevel          MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
-+	SMU74_Discrete_LinkLevel            LinkLevel[SMU74_MAX_LEVELS_LINK];
-+	SMU74_Discrete_ACPILevel            ACPILevel;
-+	SMU74_Discrete_UvdLevel             UvdLevel[SMU74_MAX_LEVELS_UVD];
-+	SMU74_Discrete_ExtClkLevel          VceLevel[SMU74_MAX_LEVELS_VCE];
-+	SMU74_Discrete_ExtClkLevel          AcpLevel[SMU74_MAX_LEVELS_ACP];
-+	SMU74_Discrete_ExtClkLevel          SamuLevel[SMU74_MAX_LEVELS_SAMU];
-+	SMU74_Discrete_Ulv                  Ulv;
-+
-+	uint8_t                             DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
-+
-+	uint32_t                            SclkStepSize;
-+	uint32_t                            Smio[SMU74_MAX_ENTRIES_SMIO];
-+
-+	uint8_t                             UvdBootLevel;
-+	uint8_t                             VceBootLevel;
-+	uint8_t                             AcpBootLevel;
-+	uint8_t                             SamuBootLevel;
-+
-+	uint8_t                             GraphicsBootLevel;
-+	uint8_t                             GraphicsVoltageChangeEnable;
-+	uint8_t                             GraphicsThermThrottleEnable;
-+	uint8_t                             GraphicsInterval;
-+
-+	uint8_t                             VoltageInterval;
-+	uint8_t                             ThermalInterval;
-+	uint16_t                            TemperatureLimitHigh;
-+
-+	uint16_t                            TemperatureLimitLow;
-+	uint8_t                             MemoryBootLevel;
-+	uint8_t                             MemoryVoltageChangeEnable;
-+
-+	uint16_t                            BootMVdd;
-+	uint8_t                             MemoryInterval;
-+	uint8_t                             MemoryThermThrottleEnable;
-+
-+	uint16_t                            VoltageResponseTime;
-+	uint16_t                            PhaseResponseTime;
-+
-+	uint8_t                             PCIeBootLinkLevel;
-+	uint8_t                             PCIeGenInterval;
-+	uint8_t                             DTEInterval;
-+	uint8_t                             DTEMode;
-+
-+	uint8_t                             SVI2Enable;
-+	uint8_t                             VRHotGpio;
-+	uint8_t                             AcDcGpio;
-+	uint8_t                             ThermGpio;
-+
-+	uint16_t                            PPM_PkgPwrLimit;
-+	uint16_t                            PPM_TemperatureLimit;
-+
-+	uint16_t                            DefaultTdp;
-+	uint16_t                            TargetTdp;
-+
-+	uint16_t                            FpsHighThreshold;
-+	uint16_t                            FpsLowThreshold;
-+
-+	uint16_t                            BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
-+	uint16_t                            BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
-+
-+	uint8_t                             DTEAmbientTempBase;
-+	uint8_t                             DTETjOffset;
-+	uint8_t                             GpuTjMax;
-+	uint8_t                             GpuTjHyst;
-+	uint16_t                            BootVddc;
-+	uint16_t                            BootVddci;
-+
-+	uint32_t                            BAPM_TEMP_GRADIENT;
-+
-+	uint32_t                            LowSclkInterruptThreshold;
-+	uint32_t                            VddGfxReChkWait;
-+
-+	uint8_t                             ClockStretcherAmount;
-+	uint8_t                             Sclk_CKS_masterEn0_7;
-+	uint8_t                             Sclk_CKS_masterEn8_15;
-+	uint8_t                             DPMFreezeAndForced;
-+
-+	uint8_t                             Sclk_voltageOffset[8];
-+
-+	SMU_ClockStretcherDataTable         ClockStretcherDataTable;
-+	SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
-+
-+	uint32_t                            CurrSclkPllRange;
-+	sclkFcwRange_t                      SclkFcwRangeTable[NUM_SCLK_RANGE];
-+};
-+
-+typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
-+
-+
-+struct SMU74_Discrete_FanTable {
-+	uint16_t FdoMode;
-+	int16_t  TempMin;
-+	int16_t  TempMed;
-+	int16_t  TempMax;
-+	int16_t  Slope1;
-+	int16_t  Slope2;
-+	int16_t  FdoMin;
-+	int16_t  HystUp;
-+	int16_t  HystDown;
-+	int16_t  HystSlope;
-+	int16_t  TempRespLim;
-+	int16_t  TempCurr;
-+	int16_t  SlopeCurr;
-+	int16_t  PwmCurr;
-+	uint32_t RefreshPeriod;
-+	int16_t  FdoMax;
-+	uint8_t  TempSrc;
-+	int8_t   Padding;
-+};
-+
-+typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
-+
-+#define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
-+#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
-+
-+
-+struct SMU7_MclkDpmScoreboard {
-+	uint32_t PercentageBusy;
-+
-+	int32_t  PIDError;
-+	int32_t  PIDIntegral;
-+	int32_t  PIDOutput;
-+
-+	uint32_t SigmaDeltaAccum;
-+	uint32_t SigmaDeltaOutput;
-+	uint32_t SigmaDeltaLevel;
-+
-+	uint32_t UtilizationSetpoint;
-+
-+	uint8_t  TdpClampMode;
-+	uint8_t  TdcClampMode;
-+	uint8_t  ThermClampMode;
-+	uint8_t  VoltageBusy;
-+
-+	int8_t   CurrLevel;
-+	int8_t   TargLevel;
-+	uint8_t  LevelChangeInProgress;
-+	uint8_t  UpHyst;
-+
-+	uint8_t  DownHyst;
-+	uint8_t  VoltageDownHyst;
-+	uint8_t  DpmEnable;
-+	uint8_t  DpmRunning;
-+
-+	uint8_t  DpmForce;
-+	uint8_t  DpmForceLevel;
-+	uint8_t  padding2;
-+	uint8_t  McArbIndex;
-+
-+	uint32_t MinimumPerfMclk;
-+
-+	uint8_t  AcpiReq;
-+	uint8_t  AcpiAck;
-+	uint8_t  MclkSwitchInProgress;
-+	uint8_t  MclkSwitchCritical;
-+
-+	uint8_t  IgnoreVBlank;
-+	uint8_t  TargetMclkIndex;
-+	uint16_t VbiFailureCount;
-+	uint8_t  VbiWaitCounter;
-+	uint8_t  EnabledLevelsChange;
-+
-+	uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
-+	uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
-+
-+	void     (*TargetStateCalculator)(uint8_t);
-+	void     (*SavedTargetStateCalculator)(uint8_t);
-+
-+	uint16_t AutoDpmInterval;
-+	uint16_t AutoDpmRange;
-+
-+	uint16_t VbiTimeoutCount;
-+	uint16_t MclkSwitchingTime;
-+
-+	uint8_t  fastSwitch;
-+	uint8_t  Save_PIC_VDDGFX_EXIT;
-+	uint8_t  Save_PIC_VDDGFX_ENTER;
-+	uint8_t  padding;
-+};
-+
-+typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
-+
-+struct SMU7_UlvScoreboard {
-+	uint8_t     EnterUlv;
-+	uint8_t     ExitUlv;
-+	uint8_t     UlvActive;
-+	uint8_t     WaitingForUlv;
-+	uint8_t     UlvEnable;
-+	uint8_t     UlvRunning;
-+	uint8_t     UlvMasterEnable;
-+	uint8_t     padding;
-+	uint32_t    UlvAbortedCount;
-+	uint32_t    UlvTimeStamp;
-+};
-+
-+typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
-+
-+struct VddgfxSavedRegisters {
-+	uint32_t GPU_DBG[3];
-+	uint32_t MEC_BaseAddress_Hi;
-+	uint32_t MEC_BaseAddress_Lo;
-+	uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
-+	uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
-+	uint32_t CP_INT_CNTL;
-+};
-+
-+typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
-+
-+struct SMU7_VddGfxScoreboard {
-+	uint8_t     VddGfxEnable;
-+	uint8_t     VddGfxActive;
-+	uint8_t     VPUResetOccured;
-+	uint8_t     padding;
-+
-+	uint32_t    VddGfxEnteredCount;
-+	uint32_t    VddGfxAbortedCount;
-+
-+	uint32_t    VddGfxVid;
-+
-+	VddgfxSavedRegisters SavedRegisters;
-+};
-+
-+typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
-+
-+struct SMU7_TdcLimitScoreboard {
-+	uint8_t  Enable;
-+	uint8_t  Running;
-+	uint16_t Alpha;
-+	uint32_t FilteredIddc;
-+	uint32_t IddcLimit;
-+	uint32_t IddcHyst;
-+	SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
-+
-+struct SMU7_PkgPwrLimitScoreboard {
-+	uint8_t  Enable;
-+	uint8_t  Running;
-+	uint16_t Alpha;
-+	uint32_t FilteredPkgPwr;
-+	uint32_t Limit;
-+	uint32_t Hyst;
-+	uint32_t LimitFromDriver;
-+	SMU7_HystController_Data HystControllerData;
-+};
-+
-+typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
-+
-+struct SMU7_BapmScoreboard {
-+	uint32_t source_powers[SMU74_DTE_SOURCES];
-+	uint32_t source_powers_last[SMU74_DTE_SOURCES];
-+	int32_t entity_temperatures[SMU74_NUM_GPU_TES];
-+	int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
-+	int32_t Limit;
-+	int32_t Hyst;
-+	int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
-+	int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
-+	uint16_t ConfigTDPPowerScalar;
-+	uint16_t FanSpeedPowerScalar;
-+	uint16_t OverDrivePowerScalar;
-+	uint16_t OverDriveLimitScalar;
-+	uint16_t FinalPowerScalar;
-+	uint8_t VariantID;
-+	uint8_t spare997;
-+
-+	SMU7_HystController_Data HystControllerData;
-+
-+	int32_t temperature_gradient_slope;
-+	int32_t temperature_gradient;
-+	uint32_t measured_temperature;
-+};
-+
-+
-+typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
-+
-+struct SMU7_AcpiScoreboard {
-+	uint32_t SavedInterruptMask[2];
-+	uint8_t LastACPIRequest;
-+	uint8_t CgBifResp;
-+	uint8_t RequestType;
-+	uint8_t Padding;
-+	SMU74_Discrete_ACPILevel D0Level;
-+};
-+
-+typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
-+
-+struct SMU_QuadraticCoeffs {
-+	int32_t m1;
-+	uint32_t b;
-+
-+	int16_t m2;
-+	uint8_t m1_shift;
-+	uint8_t m2_shift;
-+};
-+typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
-+
-+struct SMU74_Discrete_PmFuses {
-+	uint8_t BapmVddCVidHiSidd[8];
-+	uint8_t BapmVddCVidLoSidd[8];
-+	uint8_t VddCVid[8];
-+	uint8_t SviLoadLineEn;
-+	uint8_t SviLoadLineVddC;
-+	uint8_t SviLoadLineTrimVddC;
-+	uint8_t SviLoadLineOffsetVddC;
-+	uint16_t TDC_VDDC_PkgLimit;
-+	uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
-+	uint8_t TDC_MAWt;
-+	uint8_t TdcWaterfallCtl;
-+	uint8_t LPMLTemperatureMin;
-+	uint8_t LPMLTemperatureMax;
-+	uint8_t Reserved;
-+
-+	uint8_t LPMLTemperatureScaler[16];
-+
-+	int16_t FuzzyFan_ErrorSetDelta;
-+	int16_t FuzzyFan_ErrorRateSetDelta;
-+	int16_t FuzzyFan_PwmSetDelta;
-+	uint16_t Reserved6;
-+
-+	uint8_t GnbLPML[16];
-+
-+	uint8_t GnbLPMLMaxVid;
-+	uint8_t GnbLPMLMinVid;
-+	uint8_t Reserved1[2];
-+
-+	uint16_t BapmVddCBaseLeakageHiSidd;
-+	uint16_t BapmVddCBaseLeakageLoSidd;
-+
-+	uint16_t  VFT_Temp[3];
-+	uint16_t  padding;
-+
-+	SMU_QuadraticCoeffs VFT_ATE[3];
-+
-+	SMU_QuadraticCoeffs AVFS_GB;
-+	SMU_QuadraticCoeffs ATE_ACBTC_GB;
-+
-+	SMU_QuadraticCoeffs P2V;
-+
-+	uint32_t PsmCharzFreq;
-+
-+	uint16_t InversionVoltage;
-+	uint16_t PsmCharzTemp;
-+
-+	uint32_t EnabledAvfsModules;
-+};
-+
-+typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
-+
-+struct SMU7_Discrete_Log_Header_Table {
-+	uint32_t    version;
-+	uint32_t    asic_id;
-+	uint16_t    flags;
-+	uint16_t    entry_size;
-+	uint32_t    total_size;
-+	uint32_t    num_of_entries;
-+	uint8_t     type;
-+	uint8_t     mode;
-+	uint8_t     filler_0[2];
-+	uint32_t    filler_1[2];
-+};
-+
-+typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
-+
-+struct SMU7_Discrete_Log_Cntl {
-+	uint8_t             Enabled;
-+	uint8_t             Type;
-+	uint8_t             padding[2];
-+	uint32_t            BufferSize;
-+	uint32_t            SamplesLogged;
-+	uint32_t            SampleSize;
-+	uint32_t            AddrL;
-+	uint32_t            AddrH;
-+};
-+
-+typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
-+
-+#if defined SMU__DGPU_ONLY
-+#define CAC_ACC_NW_NUM_OF_SIGNALS 87
-+#endif
-+
-+
-+struct SMU7_Discrete_Cac_Collection_Table {
-+	uint32_t temperature;
-+	uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
-+};
-+
-+typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
-+
-+struct SMU7_Discrete_Cac_Verification_Table {
-+	uint32_t VddcTotalPower;
-+	uint32_t VddcLeakagePower;
-+	uint32_t VddcConstantPower;
-+	uint32_t VddcGfxDynamicPower;
-+	uint32_t VddcUvdDynamicPower;
-+	uint32_t VddcVceDynamicPower;
-+	uint32_t VddcAcpDynamicPower;
-+	uint32_t VddcPcieDynamicPower;
-+	uint32_t VddcDceDynamicPower;
-+	uint32_t VddcCurrent;
-+	uint32_t VddcVoltage;
-+	uint32_t VddciTotalPower;
-+	uint32_t VddciLeakagePower;
-+	uint32_t VddciConstantPower;
-+	uint32_t VddciDynamicPower;
-+	uint32_t Vddr1TotalPower;
-+	uint32_t Vddr1LeakagePower;
-+	uint32_t Vddr1ConstantPower;
-+	uint32_t Vddr1DynamicPower;
-+	uint32_t spare[4];
-+	uint32_t temperature;
-+};
-+
-+typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
-+
-+struct SMU7_Discrete_Pm_Status_Table {
-+	int32_t T_meas_max;
-+	int32_t T_meas_acc;
-+	int32_t T_calc_max;
-+	int32_t T_calc_acc;
-+	uint32_t P_scalar_acc;
-+	uint32_t P_calc_max;
-+	uint32_t P_calc_acc;
-+
-+	uint32_t I_calc_max;
-+	uint32_t I_calc_acc;
-+	uint32_t I_calc_acc_vddci;
-+	uint32_t V_calc_noload_acc;
-+	uint32_t V_calc_load_acc;
-+	uint32_t V_calc_noload_acc_vddci;
-+	uint32_t P_meas_acc;
-+	uint32_t V_meas_noload_acc;
-+	uint32_t V_meas_load_acc;
-+	uint32_t I_meas_acc;
-+	uint32_t P_meas_acc_vddci;
-+	uint32_t V_meas_noload_acc_vddci;
-+	uint32_t V_meas_load_acc_vddci;
-+	uint32_t I_meas_acc_vddci;
-+
-+	uint16_t Sclk_dpm_residency[8];
-+	uint16_t Uvd_dpm_residency[8];
-+	uint16_t Vce_dpm_residency[8];
-+
-+	uint32_t P_vddci_acc;
-+	uint32_t P_vddr1_acc;
-+	uint32_t P_nte1_acc;
-+	uint32_t PkgPwr_max;
-+	uint32_t PkgPwr_acc;
-+	uint32_t MclkSwitchingTime_max;
-+	uint32_t MclkSwitchingTime_acc;
-+	uint32_t FanPwm_acc;
-+	uint32_t FanRpm_acc;
-+
-+	uint32_t AccCnt;
-+};
-+
-+typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
-+
-+#define SMU7_MAX_GFX_CU_COUNT 16
-+
-+struct SMU7_GfxCuPgScoreboard {
-+	uint8_t Enabled;
-+	uint8_t WaterfallUp;
-+	uint8_t WaterfallDown;
-+	uint8_t WaterfallLimit;
-+	uint8_t CurrMaxCu;
-+	uint8_t TargMaxCu;
-+	uint8_t ClampMode;
-+	uint8_t Active;
-+	uint8_t MaxSupportedCu;
-+	uint8_t MinSupportedCu;
-+	uint8_t PendingGfxCuHostInterrupt;
-+	uint8_t LastFilteredMaxCuInteger;
-+	uint16_t FilteredMaxCu;
-+	uint16_t FilteredMaxCuAlpha;
-+	uint16_t FilterResetCount;
-+	uint16_t FilterResetCountLimit;
-+	uint8_t ForceCu;
-+	uint8_t ForceCuCount;
-+	uint8_t spare[2];
-+};
-+
-+typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
-+
-+#define SMU7_SCLK_CAC 0x561
-+#define SMU7_MCLK_CAC 0xF9
-+#define SMU7_VCLK_CAC 0x2DE
-+#define SMU7_DCLK_CAC 0x2DE
-+#define SMU7_ECLK_CAC 0x25E
-+#define SMU7_ACLK_CAC 0x25E
-+#define SMU7_SAMCLK_CAC 0x25E
-+#define SMU7_DISPCLK_CAC 0x100
-+#define SMU7_CAC_CONSTANT 0x2EE3430
-+#define SMU7_CAC_CONSTANT_SHIFT 18
-+
-+#define SMU7_VDDCI_MCLK_CONST        1765
-+#define SMU7_VDDCI_MCLK_CONST_SHIFT  16
-+#define SMU7_VDDCI_VDDCI_CONST       50958
-+#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
-+#define SMU7_VDDCI_CONST             11781
-+#define SMU7_VDDCI_STROBE_PWR        1331
-+
-+#define SMU7_VDDR1_CONST            693
-+#define SMU7_VDDR1_CAC_WEIGHT       20
-+#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
-+#define SMU7_VDDR1_STROBE_PWR       512
-+
-+#define SMU7_AREA_COEFF_UVD 0xA78
-+#define SMU7_AREA_COEFF_VCE 0x190A
-+#define SMU7_AREA_COEFF_ACP 0x22D1
-+#define SMU7_AREA_COEFF_SAMU 0x534
-+
-+#define SMU7_THERM_OUT_MODE_DISABLE       0x0
-+#define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
-+#define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
-+
-+#pragma pack(pop)
-+
-+
-+#endif
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0928-drm-amd-powerplay-add-smu-support-for-ellesmere-baff.patch b/common/recipes-kernel/linux/files/0928-drm-amd-powerplay-add-smu-support-for-ellesmere-baff.patch
deleted file mode 100644
index b9f9fb6b..00000000
--- a/common/recipes-kernel/linux/files/0928-drm-amd-powerplay-add-smu-support-for-ellesmere-baff.patch
+++ /dev/null
@@ -1,1134 +0,0 @@
-From 8dbf648aa23c5f7c18bf336a475ac603abad58b2 Mon Sep 17 00:00:00 2001
-From: rezhu <Rex.Zhu@amd.com>
-Date: Tue, 10 Nov 2015 10:26:39 +0800
-Subject: [PATCH 0928/1110] drm/amd/powerplay: add smu support for
- ellesmere/baffin
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c            |  11 +-
- drivers/gpu/drm/amd/powerplay/smumgr/Makefile      |   2 +-
- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c    | 969 +++++++++++++++++++++
- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.h    |  66 ++
- drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |   5 +
- 5 files changed, 1050 insertions(+), 3 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 8b653f2..8bc4040 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -681,9 +681,10 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
- 		result = AMDGPU_UCODE_ID_CP_MEC1;
- 		break;
- 	case CGS_UCODE_ID_CP_MEC_JT2:
--		if (adev->asic_type == CHIP_TONGA)
-+		if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_BAFFIN
-+		  || adev->asic_type == CHIP_ELLESMERE)
- 			result = AMDGPU_UCODE_ID_CP_MEC2;
--		else if (adev->asic_type == CHIP_CARRIZO)
-+		else
- 			result = AMDGPU_UCODE_ID_CP_MEC1;
- 		break;
- 	case CGS_UCODE_ID_RLC_G:
-@@ -741,6 +742,12 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
- 		case CHIP_FIJI:
- 			strcpy(fw_name, "amdgpu/fiji_smc.bin");
- 			break;
-+		case CHIP_BAFFIN:
-+			strcpy(fw_name, "amdgpu/baffin_smc.bin");
-+			break;
-+		case CHIP_ELLESMERE:
-+			strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
-+			break;
- 		default:
- 			DRM_ERROR("SMC firmware not supported\n");
- 			return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-index 6c4ef13..4f751e5 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'smu manager' sub-component of powerplay.
- # It provides the smu management services for the driver.
- 
--SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o
-+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o
- 
- AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-new file mode 100644
-index 0000000..f57ba12
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-@@ -0,0 +1,969 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "smumgr.h"
-+#include "smu74.h"
-+#include "smu_ucode_xfer_vi.h"
-+#include "ellesmere_smumgr.h"
-+#include "smu74_discrete.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "oss/oss_3_0_d.h"
-+#include "gca/gfx_8_0_d.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "ellesmere_pwrvirus.h"
-+#include "ppatomctrl.h"
-+#include "pp_debug.h"
-+#include "cgs_common.h"
-+
-+#define ELLESMERE_SMC_SIZE 0x20000
-+#define VOLTAGE_SCALE 4
-+
-+/* Microcode file is stored in this buffer */
-+#define BUFFER_SIZE                 80000
-+#define MAX_STRING_SIZE             15
-+#define BUFFER_SIZETWO              131072  /* 128 *1024 */
-+
-+#define SMC_RAM_END 0x40000
-+
-+SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = {
-+	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
-+	/* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
-+	{ 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
-+};
-+
-+SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
-+							0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
-+
-+/**
-+* Set the address for reading/writing the SMC SRAM space.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smcAddress the address in the SMC RAM to access.
-+*/
-+static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
-+{
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
-+
-+	return 0;
-+}
-+
-+/**
-+* Copy bytes from SMC RAM space into driver memory.
-+*
-+* @param    smumgr  the address of the powerplay SMU manager.
-+* @param    smc_start_address the start address in the SMC RAM to copy bytes from
-+* @param    src the byte array to copy the bytes to.
-+* @param    byte_count the number of bytes to copy.
-+*/
-+int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
-+{
-+	uint32_t data;
-+	uint32_t addr;
-+	uint8_t *dest_byte;
-+	uint8_t i, data_byte[4] = {0};
-+	uint32_t *pdata = (uint32_t *)&data_byte;
-+
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;);
-+	PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
-+
-+	addr = smc_start_address;
-+
-+	while (byte_count >= 4) {
-+		ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
-+
-+		*dest = PP_SMC_TO_HOST_UL(data);
-+
-+		dest += 1;
-+		byte_count -= 4;
-+		addr += 4;
-+	}
-+
-+	if (byte_count) {
-+		ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
-+		*pdata = PP_SMC_TO_HOST_UL(data);
-+	/* Cast dest into byte type in dest_byte.  This way, we don't overflow if the allocated memory is not 4-byte aligned. */
-+		dest_byte = (uint8_t *)dest;
-+		for (i = 0; i < byte_count; i++)
-+			dest_byte[i] = data_byte[i];
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Copy bytes from an array into the SMC RAM space.
-+*
-+* @param    pSmuMgr  the address of the powerplay SMU manager.
-+* @param    smc_start_address the start address in the SMC RAM to copy bytes to.
-+* @param    src the byte array to copy the bytes from.
-+* @param    byte_count the number of bytes to copy.
-+*/
-+int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+				const uint8_t *src, uint32_t byte_count, uint32_t limit)
-+{
-+	int result;
-+	uint32_t data = 0;
-+	uint32_t original_data;
-+	uint32_t addr = 0;
-+	uint32_t extra_shift;
-+
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1);
-+	PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
-+
-+	addr = smc_start_address;
-+
-+	while (byte_count >= 4) {
-+	/* Bytes are written into the SMC addres space with the MSB first. */
-+		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
-+
-+		result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
-+
-+		src += 4;
-+		byte_count -= 4;
-+		addr += 4;
-+	}
-+
-+	if (0 != byte_count) {
-+
-+		data = 0;
-+
-+		result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+
-+		original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
-+
-+		extra_shift = 8 * (4 - byte_count);
-+
-+		while (byte_count > 0) {
-+			/* Bytes are written into the SMC addres space with the MSB first. */
-+			data = (0x100 * data) + *src++;
-+			byte_count--;
-+		}
-+
-+		data <<= extra_shift;
-+
-+		data |= (original_data & ~((~0UL) << extra_shift));
-+
-+		result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr)
-+{
-+	static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
-+
-+	ellesmere_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Return if the SMC is currently running.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+*/
-+bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr)
-+{
-+	return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-+	&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
-+}
-+
-+/**
-+* Send a message to the SMC, and wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	if (!ellesmere_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+		printk("Failed to send Previous Message.\n");
-+
-+
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+		printk("Failed to send Message.\n");
-+
-+	return 0;
-+}
-+
-+
-+/**
-+* Send a message to the SMC, and do not wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   Always return 0.
-+*/
-+int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	return 0;
-+}
-+
-+/**
-+* Send a message to the SMC with parameter
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+{
-+	if (!ellesmere_is_smc_ram_running(smumgr)) {
-+		return -1;
-+	}
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+
-+	return ellesmere_send_msg_to_smc(smumgr, msg);
-+}
-+
-+
-+/**
-+* Send a message to the SMC with parameter, do not wait for response
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+int ellesmere_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+{
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+
-+	return ellesmere_send_msg_to_smc_without_waiting(smumgr, msg);
-+}
-+
-+int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
-+{
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+		printk("Failed to send Message.\n");
-+
-+	return 0;
-+}
-+
-+/**
-+* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr)
-+{
-+	/* If the SMC is not even on it qualifies as inactive. */
-+	if (!ellesmere_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
-+	return 0;
-+}
-+
-+
-+/**
-+* Upload the SMC firmware to the SMC microcontroller.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    pFirmware the data structure containing the various sections of the firmware.
-+*/
-+static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
-+{
-+	uint32_t byte_count = length;
-+
-+	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1);
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
-+
-+
-+	for (; byte_count >= 4; byte_count -= 4)
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
-+
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
-+
-+	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1);
-+
-+	return 0;
-+}
-+
-+static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
-+{
-+	enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SMU:
-+		result = CGS_UCODE_ID_SMU;
-+		break;
-+	case UCODE_ID_SDMA0:
-+		result = CGS_UCODE_ID_SDMA0;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = CGS_UCODE_ID_SDMA1;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = CGS_UCODE_ID_CP_CE;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = CGS_UCODE_ID_CP_PFP;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = CGS_UCODE_ID_CP_ME;
-+		break;
-+	case UCODE_ID_CP_MEC:
-+		result = CGS_UCODE_ID_CP_MEC;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+		result = CGS_UCODE_ID_CP_MEC_JT1;
-+		break;
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = CGS_UCODE_ID_CP_MEC_JT2;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = CGS_UCODE_ID_RLC_G;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	struct cgs_firmware_info info = {0};
-+
-+	cgs_get_firmware_info(smumgr->device,
-+			ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
-+
-+	/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
-+
-+	result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE);
-+
-+	return result;
-+}
-+
-+/**
-+* Read a 32bit value from the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smcAddress the address in the SMC RAM to access.
-+* @param    value and output parameter for the data read from the SMC SRAM.
-+*/
-+int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
-+{
-+	int result;
-+
-+	result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
-+	return 0;
-+}
-+
-+/**
-+* Write a 32bit value to the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smc_addr the address in the SMC RAM to access.
-+* @param    value to write to the SMC SRAM.
-+*/
-+int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
-+{
-+	int result;
-+
-+	result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
-+
-+	return 0;
-+}
-+
-+
-+int ellesmere_smu_fini(struct pp_smumgr *smumgr)
-+{
-+	if (smumgr->backend) {
-+		kfree(smumgr->backend);
-+		smumgr->backend = NULL;
-+	}
-+	return 0;
-+}
-+
-+/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
-+static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type)
-+{
-+	uint32_t result = 0;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SDMA0:
-+		result = UCODE_ID_SDMA0_MASK;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = UCODE_ID_SDMA1_MASK;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = UCODE_ID_CP_CE_MASK;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = UCODE_ID_CP_PFP_MASK;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = UCODE_ID_CP_ME_MASK;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = UCODE_ID_CP_MEC_MASK;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = UCODE_ID_RLC_G_MASK;
-+		break;
-+	default:
-+		printk("UCode type is out of range! \n");
-+		result = 0;
-+	}
-+
-+	return result;
-+}
-+
-+/* Populate one firmware image to the data structure */
-+
-+static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr,
-+						uint32_t fw_type,
-+						struct SMU_Entry *entry)
-+{
-+	int result = 0;
-+	struct cgs_firmware_info info = {0};
-+
-+	result = cgs_get_firmware_info(smumgr->device,
-+				ellesmere_convert_fw_type_to_cgs(fw_type),
-+				&info);
-+
-+	if (!result) {
-+		entry->version = info.version;
-+		entry->id = (uint16_t)fw_type;
-+		entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
-+		entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
-+		entry->meta_data_addr_high = 0;
-+		entry->meta_data_addr_low = 0;
-+		entry->data_size_byte = info.image_size;
-+		entry->num_register_entries = 0;
-+	}
-+
-+	if (fw_type == UCODE_ID_RLC_G)
-+		entry->flags = 1;
-+	else
-+		entry->flags = 0;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr)
-+{
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+	uint32_t fw_to_load;
-+
-+	int result = 0;
-+	struct SMU_DRAMData_TOC *toc;
-+
-+	if (!smumgr->reload_fw) {
-+		printk(KERN_INFO "[ powerplay ] skip reloading...\n");
-+		return 0;
-+	}
-+
-+	if (smu_data->soft_regs_start)
-+		cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+					smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
-+					0x0);
-+
-+	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
-+	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
-+
-+	toc = (struct SMU_DRAMData_TOC *)smu_data->header;
-+	toc->num_entries = 0;
-+	toc->structure_version = 1;
-+
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+
-+	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
-+	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
-+
-+	fw_to_load = UCODE_ID_RLC_G_MASK
-+		   + UCODE_ID_SDMA0_MASK
-+		   + UCODE_ID_SDMA1_MASK
-+		   + UCODE_ID_CP_CE_MASK
-+		   + UCODE_ID_CP_ME_MASK
-+		   + UCODE_ID_CP_PFP_MASK
-+		   + UCODE_ID_CP_MEC_MASK;
-+
-+	if (ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
-+		printk(KERN_ERR "Fail to Request SMU Load uCode");
-+
-+	return result;
-+}
-+
-+/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
-+static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
-+{
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+	uint32_t fw_mask = ellesmere_get_mask_for_firmware_type(fw_type);
-+	uint32_t ret;
-+	/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
-+	ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
-+					smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
-+					fw_mask, fw_mask);
-+
-+	return ret;
-+}
-+
-+static int ellesmere_reload_firmware(struct pp_smumgr *smumgr)
-+{
-+	return smumgr->smumgr_funcs->start_smu(smumgr);
-+}
-+
-+static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr)
-+{
-+	int i;
-+	int result = -1;
-+	uint32_t reg, data;
-+
-+	PWR_Command_Table *pvirus = pwr_virus_table;
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+
-+
-+	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
-+		switch (pvirus->command) {
-+		case PwrCmdWrite:
-+			reg  = pvirus->reg;
-+			data = pvirus->data;
-+			cgs_write_register(smumgr->device, reg, data);
-+			break;
-+
-+		case PwrCmdEnd:
-+			result = 0;
-+			break;
-+
-+		default:
-+			printk("Table Exit with Invalid Command!");
-+			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
-+			result = -1;
-+			break;
-+		}
-+		pvirus++;
-+	}
-+
-+	return result;
-+}
-+
-+static int ellesmere_perform_btc(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+
-+	if (0 != smu_data->avfs.avfs_btc_param) {
-+		if (0 != ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
-+			printk("[AVFS][SmuEllesmere_PerformBtc] PerformBTC SMU msg failed");
-+			result = -1;
-+		}
-+	}
-+	if (smu_data->avfs.avfs_btc_param > 1) {
-+		/* Soft-Reset to reset the engine before loading uCode */
-+		/* halt */
-+		cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
-+		/* reset everything */
-+		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
-+		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
-+	}
-+	return result;
-+}
-+
-+
-+int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr)
-+{
-+	uint32_t vr_config;
-+	uint32_t dpm_table_start;
-+
-+	uint16_t u16_boot_mvdd;
-+	uint32_t graphics_level_address, vr_config_address, graphics_level_size;
-+
-+	graphics_level_size = sizeof(avfs_graphics_level_ellesmere);
-+	u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
-+
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_read_smc_sram_dword(smumgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
-+				&dpm_table_start, 0x40000),
-+			"[AVFS][Ellesmere_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
-+			return -1);
-+
-+	/*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
-+	vr_config = 0x01000500; /* Real value:0x50001 */
-+
-+	vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
-+
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, vr_config_address,
-+				(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
-+			"[AVFS][Ellesmere_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
-+			return -1);
-+
-+	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
-+
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
-+				(uint8_t *)(&avfs_graphics_level_ellesmere),
-+				graphics_level_size, 0x40000),
-+			"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
-+			return -1);
-+
-+	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
-+
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
-+				(uint8_t *)(&avfs_memory_level_ellesmere), sizeof(avfs_memory_level_ellesmere), 0x40000),
-+				"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
-+			return -1);
-+
-+	/* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
-+
-+	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
-+
-+	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
-+			(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
-+			"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of DPM table failed!",
-+			return -1);
-+
-+	return 0;
-+}
-+
-+int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
-+{
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+
-+	switch (smu_data->avfs.avfs_btc_status) {
-+	case AVFS_BTC_COMPLETED_PREVIOUSLY:
-+		break;
-+
-+	case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
-+
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == ellesmere_setup_graphics_level_structure(smumgr),
-+		"[AVFS][Ellesmere_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
-+		return -1);
-+
-+		if (smu_data->avfs.avfs_btc_param > 1) {
-+			printk("[AVFS][Ellesmere_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
-+			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
-+			PP_ASSERT_WITH_CODE(-1 == ellesmere_setup_pwr_virus(smumgr),
-+			"[AVFS][Ellesmere_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
-+			return -1);
-+		}
-+
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == ellesmere_perform_btc(smumgr),
-+					"[AVFS][Ellesmere_AVFSEventMgr] Failure at SmuEllesmere_PerformBTC. AVFS Disabled",
-+				 return -1);
-+
-+		break;
-+
-+	case AVFS_BTC_DISABLED:
-+	case AVFS_BTC_NOTSUPPORTED:
-+		break;
-+
-+	default:
-+		printk("[AVFS] Something is broken. See log!");
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* Wait for smc boot up */
-+	/* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
-+
-+	/* Assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	result = ellesmere_upload_smu_firmware_image(smumgr);
-+	if (result != 0)
-+		return result;
-+
-+	/* Clear status */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	/* De-assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
-+
-+
-+	/* Call Test SMU message with 0x20000 offset to trigger SMU start */
-+	ellesmere_send_msg_to_smc_offset(smumgr);
-+
-+	/* Wait done bit to be set */
-+	/* Check pass/failed indicator */
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
-+
-+	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+						SMU_STATUS, SMU_PASS))
-+		PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
-+
-+
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for firmware to initialize */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* wait for smc boot up */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
-+
-+	/* Clear firmware interrupt enable flag */
-+	/* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+				ixFIRMWARE_FLAGS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL,
-+					rst_reg, 1);
-+
-+	result = ellesmere_upload_smu_firmware_image(smumgr);
-+	if (result != 0)
-+		return result;
-+
-+	/* Set smc instruct start point at 0x0 */
-+	ellesmere_program_jump_on_start(smumgr);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for firmware to initialize */
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+					FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+static int ellesmere_start_smu(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+	bool SMU_VFT_INTACT;
-+
-+	/* Only start SMC if SMC RAM is not running */
-+	if (!ellesmere_is_smc_ram_running(smumgr)) {
-+		SMU_VFT_INTACT = false;
-+		/* Check if SMU is running in protected mode */
-+		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE))
-+			result = ellesmere_start_smu_in_non_protection_mode(smumgr);
-+		else
-+			result = ellesmere_start_smu_in_protection_mode(smumgr);
-+
-+		if (result != 0)
-+			PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
-+
-+		ellesmere_avfs_event_mgr(smumgr, true);
-+	} else
-+		SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
-+
-+	smu_data->post_initial_boot = true;
-+	ellesmere_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
-+	/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
-+	ellesmere_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
-+					&(smu_data->soft_regs_start), 0x40000);
-+
-+	result = ellesmere_request_smu_load_fw(smumgr);
-+
-+	return result;
-+}
-+
-+static int ellesmere_smu_init(struct pp_smumgr *smumgr)
-+{
-+	struct ellesmere_smumgr *smu_data;
-+	uint8_t *internal_buf;
-+	uint64_t mc_addr = 0;
-+	/* Allocate memory for backend private data */
-+	smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+	smu_data->header_buffer.data_size =
-+		((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
-+	smu_data->smu_buffer.data_size = 200*4096;
-+	smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
-+/* Allocate FW image data structure and header buffer and
-+ * send the header buffer address to SMU */
-+	smu_allocate_memory(smumgr->device,
-+		smu_data->header_buffer.data_size,
-+		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+		PAGE_SIZE,
-+		&mc_addr,
-+		&smu_data->header_buffer.kaddr,
-+		&smu_data->header_buffer.handle);
-+
-+	smu_data->header = smu_data->header_buffer.kaddr;
-+	smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != smu_data->header),
-+		"Out of memory.",
-+		kfree(smumgr->backend);
-+		cgs_free_gpu_mem(smumgr->device,
-+		(cgs_handle_t)smu_data->header_buffer.handle);
-+		return -1);
-+
-+/* Allocate buffer for SMU internal buffer and send the address to SMU.
-+ * Iceland SMU does not need internal buffer.*/
-+	smu_allocate_memory(smumgr->device,
-+		smu_data->smu_buffer.data_size,
-+		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+		PAGE_SIZE,
-+		&mc_addr,
-+		&smu_data->smu_buffer.kaddr,
-+		&smu_data->smu_buffer.handle);
-+
-+	internal_buf = smu_data->smu_buffer.kaddr;
-+	smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != internal_buf),
-+		"Out of memory.",
-+		kfree(smumgr->backend);
-+		cgs_free_gpu_mem(smumgr->device,
-+		(cgs_handle_t)smu_data->smu_buffer.handle);
-+		return -1;);
-+
-+	return 0;
-+}
-+
-+static const struct pp_smumgr_func ellsemere_smu_funcs = {
-+	.smu_init = ellesmere_smu_init,
-+	.smu_fini = ellesmere_smu_fini,
-+	.start_smu = ellesmere_start_smu,
-+	.check_fw_load_finish = ellesmere_check_fw_load_finish,
-+	.request_smu_load_fw = ellesmere_reload_firmware,
-+	.request_smu_load_specific_fw = NULL,
-+	.send_msg_to_smc = ellesmere_send_msg_to_smc,
-+	.send_msg_to_smc_with_parameter = ellesmere_send_msg_to_smc_with_parameter,
-+	.download_pptable_settings = NULL,
-+	.upload_pptable_settings = NULL,
-+};
-+
-+int ellesmere_smum_init(struct pp_smumgr *smumgr)
-+{
-+	struct ellesmere_smumgr *ellesmere_smu = NULL;
-+
-+	ellesmere_smu = kzalloc(sizeof(struct ellesmere_smumgr), GFP_KERNEL);
-+
-+	if (ellesmere_smu == NULL)
-+		return -1;
-+
-+	smumgr->backend = ellesmere_smu;
-+	smumgr->smumgr_funcs = &ellsemere_smu_funcs;
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-new file mode 100644
-index 0000000..3712b32
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-@@ -0,0 +1,66 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _ELLESMERE_SMUMANAGER_H
-+#define _ELLESMERE_SMUMANAGER_H
-+
-+#include <ellesmere_ppsmc.h>
-+#include <pp_endian.h>
-+
-+struct ellesmere_avfs {
-+	enum AVFS_BTC_STATUS avfs_btc_status;
-+	uint32_t           avfs_btc_param;
-+};
-+
-+struct ellesmere_buffer_entry {
-+	uint32_t data_size;
-+	uint32_t mc_addr_low;
-+	uint32_t mc_addr_high;
-+	void *kaddr;
-+	unsigned long  handle;
-+};
-+
-+struct ellesmere_smumgr {
-+	uint8_t *header;
-+	uint8_t *mec_image;
-+	struct ellesmere_buffer_entry smu_buffer;
-+	struct ellesmere_buffer_entry header_buffer;
-+	uint32_t soft_regs_start;
-+	uint8_t *read_rrm_straps;
-+	uint32_t read_drm_straps_mc_address_high;
-+	uint32_t read_drm_straps_mc_address_low;
-+	uint32_t acpi_optimization;
-+	bool post_initial_boot;
-+	struct ellesmere_avfs  avfs;
-+};
-+
-+
-+int ellesmere_smum_init(struct pp_smumgr *smumgr);
-+
-+int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
-+int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
-+int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+				const uint8_t *src, uint32_t byte_count, uint32_t limit);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-index 063ae71..06bbe90 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-@@ -30,6 +30,7 @@
- #include "cz_smumgr.h"
- #include "tonga_smumgr.h"
- #include "fiji_smumgr.h"
-+#include "ellesmere_smumgr.h"
- 
- int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -62,6 +63,10 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		case CHIP_FIJI:
- 			fiji_smum_init(smumgr);
- 			break;
-+		case CHIP_BAFFIN:
-+		case CHIP_ELLESMERE:
-+			ellesmere_smum_init(smumgr);
-+			break;
- 		default:
- 			return -EINVAL;
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0929-drm-amd-powerplay-enable-dpm-for-baffin.patch b/common/recipes-kernel/linux/files/0929-drm-amd-powerplay-enable-dpm-for-baffin.patch
deleted file mode 100644
index 236541f5..00000000
--- a/common/recipes-kernel/linux/files/0929-drm-amd-powerplay-enable-dpm-for-baffin.patch
+++ /dev/null
@@ -1,5733 +0,0 @@
-From acaf5a8b6c9ea0867a927241977be58e9b88368f Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Thu, 19 Nov 2015 18:23:32 +0800
-Subject: [PATCH 0929/1110] drm/amd/powerplay: enable dpm for baffin.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |    3 +-
- .../amd/powerplay/hwmgr/ellesmere_dyn_defaults.h   |   62 +
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  | 4560 ++++++++++++++++++++
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |  349 ++
- .../drm/amd/powerplay/hwmgr/ellesmere_powertune.c  |  396 ++
- .../drm/amd/powerplay/hwmgr/ellesmere_powertune.h  |   70 +
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c   |  111 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h   |   40 +-
- 8 files changed, 5581 insertions(+), 10 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index b664e34..2982d5c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -8,7 +8,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
- 	       tonga_processpptables.o ppatomctrl.o \
-                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
-                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
--               fiji_clockpowergating.o fiji_thermal.o
-+               fiji_clockpowergating.o fiji_thermal.o \
-+	       ellesmere_hwmgr.o ellesmere_powertune.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
-new file mode 100644
-index 0000000..ba1187c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef ELLESMERE_DYN_DEFAULTS_H
-+#define ELLESMERE_DYN_DEFAULTS_H
-+
-+
-+enum Ellesmeredpm_TrendDetection {
-+	EllesmereAdpm_TrendDetection_AUTO,
-+	EllesmereAdpm_TrendDetection_UP,
-+	EllesmereAdpm_TrendDetection_DOWN
-+};
-+typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection;
-+
-+/*  We need to fill in the default values */
-+
-+
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1              0x000400
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033
-+#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000
-+
-+
-+#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT            0x200
-+#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT        0
-+#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT            0x00C8
-+#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200
-+#define PPELLESMERE_REFERENCEDIVIDER_DFLT                  4
-+
-+#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT             1687
-+
-+#define PPELLESMERE_CGULVPARAMETER_DFLT                    0x00040035
-+#define PPELLESMERE_CGULVCONTROL_DFLT                      0x00007450
-+#define PPELLESMERE_TARGETACTIVITY_DFLT                     50
-+#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT                10
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-new file mode 100644
-index 0000000..10e8e87
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-@@ -0,0 +1,4560 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+#include "linux/delay.h"
-+#include "pp_acpi.h"
-+#include "hwmgr.h"
-+#include "ellesmere_hwmgr.h"
-+#include "ellesmere_powertune.h"
-+#include "ellesmere_dyn_defaults.h"
-+#include "ellesmere_smumgr.h"
-+#include "pp_debug.h"
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "tonga_pptable.h"
-+#include "pppcielanes.h"
-+#include "amd_pcie_helpers.h"
-+#include "hardwaremanager.h"
-+#include "tonga_processpptables.h"
-+#include "cgs_common.h"
-+#include "smu74.h"
-+#include "smu_ucode_xfer_vi.h"
-+#include "smu74_discrete.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "oss/oss_3_0_d.h"
-+#include "gca/gfx_8_0_d.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+#define MC_CG_ARB_FREQ_F0           0x0a
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define MC_CG_ARB_FREQ_F2           0x0c
-+#define MC_CG_ARB_FREQ_F3           0x0d
-+
-+#define MC_CG_SEQ_DRAMCONF_S0       0x05
-+#define MC_CG_SEQ_DRAMCONF_S1       0x06
-+#define MC_CG_SEQ_YCLK_SUSPEND      0x04
-+#define MC_CG_SEQ_YCLK_RESUME       0x0a
-+
-+
-+#define SMC_RAM_END 0x40000
-+
-+#define SMC_CG_IND_START            0xc0030000
-+#define SMC_CG_IND_END              0xc0040000
-+
-+#define VOLTAGE_SCALE               4
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+
-+#define VDDC_VDDCI_DELTA            200
-+
-+#define MEM_FREQ_LOW_LATENCY        25000
-+#define MEM_FREQ_HIGH_LATENCY       80000
-+
-+#define MEM_LATENCY_HIGH            45
-+#define MEM_LATENCY_LOW             35
-+#define MEM_LATENCY_ERR             0xFFFF
-+
-+#define MC_SEQ_MISC0_GDDR5_SHIFT 28
-+#define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
-+#define MC_SEQ_MISC0_GDDR5_VALUE 5
-+
-+
-+#define PCIE_BUS_CLK                10000
-+#define TCLK                        (PCIE_BUS_CLK / 10)
-+
-+
-+uint16_t ellesmere_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
-+							  {600, 1050, 6, 1} };
-+
-+/*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
-+uint32_t ellesmere_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+							{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-+
-+/*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
-+uint8_t ellesmere_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
-+							    {0, 2, 4, 5, 6, 5} };
-+
-+/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
-+enum DPM_EVENT_SRC {
-+	DPM_EVENT_SRC_ANALOG = 0,
-+	DPM_EVENT_SRC_EXTERNAL = 1,
-+	DPM_EVENT_SRC_DIGITAL = 2,
-+	DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
-+	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
-+};
-+
-+const unsigned long PhwEllesmere_Magic = (unsigned long)(PHM_VIslands_Magic);
-+
-+struct ellesmere_power_state *cast_phw_ellesmere_power_state(
-+				  struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL);
-+
-+	return (struct ellesmere_power_state *)hw_ps;
-+}
-+
-+const struct ellesmere_power_state *cast_const_phw_ellesmere_power_state(
-+				 const struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL);
-+
-+	return (const struct ellesmere_power_state *)hw_ps;
-+}
-+
-+static bool ellesmere_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
-+/**
-+ * Find the MC microcode version and store it in the HwMgr struct
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
-+{
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
-+
-+	hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
-+
-+	return 0;
-+}
-+
-+uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t speedCntl = 0;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
-+			ixPCIE_LC_SPEED_CNTL);
-+	return((uint16_t)PHM_GET_FIELD(speedCntl,
-+			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
-+}
-+
-+int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t link_width;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
-+			PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
-+
-+	PP_ASSERT_WITH_CODE((7 >= link_width),
-+			"Invalid PCIe lane width!", return 0);
-+
-+	return decode_pcie_lane_width(link_width);
-+}
-+
-+void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_clock_voltage_dependency_table *table =
-+				table_info->vddc_dep_on_dal_pwrl;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-+	enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-+	uint32_t req_vddc = 0, req_volt, i;
-+
-+	if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
-+			dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
-+		return;
-+
-+	for (i = 0; i < table->count; i++) {
-+		if (dal_power_level == table->entries[i].clk) {
-+			req_vddc = table->entries[i].v;
-+			break;
-+		}
-+	}
-+
-+	vddc_table = table_info->vdd_dep_on_sclk;
-+	for (i = 0; i < vddc_table->count; i++) {
-+		if (req_vddc <= vddc_table->entries[i].vddc) {
-+			req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-+					<< VDDC_SHIFT;
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VddC_Request, req_volt);
-+			return;
-+		}
-+	}
-+	printk(KERN_ERR "DAL requested level can not"
-+			" found a available voltage in VDDC DPM Table \n");
-+}
-+
-+
-+/**
-+* Checks if we want to support voltage control
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*/
-+static bool ellesmere_voltage_control(const struct pp_hwmgr *hwmgr)
-+{
-+	const struct ellesmere_hwmgr *data =
-+			(const struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	return (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control);
-+}
-+
-+/**
-+* Enable voltage control
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int ellesmere_enable_voltage_control(struct pp_hwmgr *hwmgr)
-+{
-+	/* enable voltage control */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Create Voltage Tables.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	int result;
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
-+				&(data->mvdd_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve MVDD table.",
-+				return result);
-+	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
-+				table_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 MVDD table from dependancy table.",
-+				return result;);
-+	}
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
-+				&(data->vddci_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve VDDCI table.",
-+				return result);
-+	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
-+				table_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 VDDCI table from dependancy table.",
-+				return result);
-+	}
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
-+				table_info->vddc_lookup_table);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 VDDC table from lookup table.",
-+				return result);
-+	}
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
-+			"Too many voltage values for VDDC. Trimming to fit state table.",
-+			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
-+								&(data->vddc_voltage_table)));
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
-+			"Too many voltage values for VDDCI. Trimming to fit state table.",
-+			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
-+					&(data->vddci_voltage_table)));
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
-+			"Too many voltage values for MVDD. Trimming to fit state table.",
-+			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
-+							   &(data->mvdd_voltage_table)));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs static screed detection parameters
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int ellesmere_program_static_screen_threshold_parameters(
-+							struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	/* Set static screen threshold unit */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
-+			data->static_screen_threshold_unit);
-+	/* Set static screen threshold */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
-+			data->static_screen_threshold);
-+
-+	return 0;
-+}
-+
-+/**
-+* Setup display gap for glitch free memory clock switching.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int ellesmere_enable_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t display_gap =
-+			cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixCG_DISPLAY_GAP_CNTL);
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP, DISPLAY_GAP_IGNORE);
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs activity state transition voting clients
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int ellesmere_program_voting_clients(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	/* Clear reset for voting clients before enabling DPM */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
-+
-+	return 0;
-+}
-+
-+/**
-+* Get the location of various tables inside the FW image.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(hwmgr->smumgr->backend);
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, DpmTable),
-+			&tmp, data->sram_end);
-+
-+	if (0 == result)
-+		data->dpm_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, SoftRegisters),
-+			&tmp, data->sram_end);
-+
-+	if (!result) {
-+		data->soft_regs_start = tmp;
-+		smu_data->soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, mcRegisterTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->mc_reg_table_start = tmp;
-+
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, FanTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->fan_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->arb_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, Version),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (0 != result);
-+
-+	return error ? -1 : 0;
-+}
-+
-+/* Copy one arb setting to another and then switch the active set.
-+ * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
-+ */
-+static int ellesmere_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
-+		uint32_t arb_src, uint32_t arb_dest)
-+{
-+	uint32_t mc_arb_dram_timing;
-+	uint32_t mc_arb_dram_timing2;
-+	uint32_t burst_time;
-+	uint32_t mc_cg_config;
-+
-+	switch (arb_src) {
-+	case MC_CG_ARB_FREQ_F0:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+		break;
-+	case MC_CG_ARB_FREQ_F1:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (arb_dest) {
-+	case MC_CG_ARB_FREQ_F0:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
-+		break;
-+	case MC_CG_ARB_FREQ_F1:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
-+	mc_cg_config |= 0x0000000F;
-+	cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
-+	PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
-+
-+	return 0;
-+}
-+
-+/**
-+* Initial switch from ARB F0->F1
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+* This function is to be called from the SetPowerState table.
-+*/
-+static int ellesmere_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
-+{
-+	return ellesmere_copy_and_switch_arb_sets(hwmgr,
-+			MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
-+}
-+
-+static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint32_t i, max_entry;
-+
-+	PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
-+			data->use_pcie_power_saving_levels), "No pcie performance levels!",
-+			return -EINVAL);
-+
-+	if (data->use_pcie_performance_levels &&
-+			!data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_power_saving = data->pcie_gen_performance;
-+		data->pcie_lane_power_saving = data->pcie_lane_performance;
-+	} else if (!data->use_pcie_performance_levels &&
-+			data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_performance = data->pcie_gen_power_saving;
-+		data->pcie_lane_performance = data->pcie_lane_power_saving;
-+	}
-+
-+	phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
-+					SMU74_MAX_LEVELS_LINK,
-+					MAX_REGULAR_DPM_NUMBER);
-+
-+	if (pcie_table != NULL) {
-+		/* max_entry is used to make sure we reserve one PCIE level
-+		 * for boot level (fix for A+A PSPP issue).
-+		 * If PCIE table from PPTable have ULV entry + 8 entries,
-+		 * then ignore the last entry.*/
-+		max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
-+				SMU74_MAX_LEVELS_LINK : pcie_table->count;
-+		for (i = 1; i < max_entry; i++) {
-+			phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
-+					get_pcie_gen_support(data->pcie_gen_cap,
-+							pcie_table->entries[i].gen_speed),
-+					get_pcie_lane_support(data->pcie_lane_cap,
-+							pcie_table->entries[i].lane_width));
-+		}
-+		data->dpm_table.pcie_speed_table.count = max_entry - 1;
-+	} else {
-+		/* Hardcode Pcie Table */
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Min_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Min_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+
-+		data->dpm_table.pcie_speed_table.count = 6;
-+	}
-+	/* Populate last level for boot PCIE level, but do not increment count. */
-+	phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
-+			data->dpm_table.pcie_speed_table.count,
-+			get_pcie_gen_support(data->pcie_gen_cap,
-+					PP_Min_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap,
-+					PP_Max_PCIELane));
-+
-+	return 0;
-+}
-+
-+/*
-+ * This function is to initalize all DPM state tables
-+ * for SMU7 based on the dependency table.
-+ * Dynamic state patching function will then trim these
-+ * state tables to the allowed range based
-+ * on the power policy or external client requests,
-+ * such as UVD request, etc.
-+ */
-+int ellesmere_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i;
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
-+			"SCLK dependency table is missing. This table is mandatory",
-+			return -EINVAL);
-+	PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
-+			"SCLK dependency table has to have is missing."
-+			"This table is mandatory",
-+			return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
-+			"MCLK dependency table is missing. This table is mandatory",
-+			return -EINVAL);
-+	PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
-+			"MCLK dependency table has to have is missing."
-+			"This table is mandatory",
-+			return -EINVAL);
-+
-+	/* clear the state table to reset everything to default */
-+	phm_reset_single_dpm_table(
-+			&data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
-+	phm_reset_single_dpm_table(
-+			&data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
-+
-+
-+	/* Initialize Sclk DPM table based on allow Sclk values */
-+	data->dpm_table.sclk_table.count = 0;
-+	for (i = 0; i < dep_sclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
-+						dep_sclk_table->entries[i].clk) {
-+
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
-+					dep_sclk_table->entries[i].clk;
-+
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
-+					(i == 0) ? true : false;
-+			data->dpm_table.sclk_table.count++;
-+		}
-+	}
-+
-+	/* Initialize Mclk DPM table based on allow Mclk values */
-+	data->dpm_table.mclk_table.count = 0;
-+	for (i = 0; i < dep_mclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.mclk_table.dpm_levels
-+				[data->dpm_table.mclk_table.count - 1].value !=
-+						dep_mclk_table->entries[i].clk) {
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
-+							dep_mclk_table->entries[i].clk;
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
-+							(i == 0) ? true : false;
-+			data->dpm_table.mclk_table.count++;
-+		}
-+	}
-+
-+	/* setup PCIE gen speed levels */
-+	ellesmere_setup_default_pcie_table(hwmgr);
-+
-+	/* save a copy of the default DPM table */
-+	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
-+			sizeof(struct ellesmere_dpm_table));
-+
-+	return 0;
-+}
-+
-+uint8_t convert_to_vid(uint16_t vddc)
-+{
-+	return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-+}
-+
-+/**
-+ * Mvdd table preparation for SMC.
-+ *
-+ * @param    *hwmgr The address of the hardware manager.
-+ * @param    *table The SMC DPM table structure to be populated.
-+ * @return   0
-+ */
-+static int ellesmere_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU74_Discrete_DpmTable *table)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t count, level;
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		count = data->mvdd_voltage_table.count;
-+		if (count > SMU_MAX_SMIO_LEVELS)
-+			count = SMU_MAX_SMIO_LEVELS;
-+		for (level = 0; level < count; level++) {
-+			table->SmioTable2.Pattern[level].Voltage =
-+				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
-+			table->SmioTable2.Pattern[level].Smio =
-+				(uint8_t) level;
-+			table->Smio[level] |=
-+				data->mvdd_voltage_table.entries[level].smio_low;
-+		}
-+		table->SmioMask2 = data->vddci_voltage_table.mask_low;
-+
-+		table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
-+					struct SMU74_Discrete_DpmTable *table)
-+{
-+	uint32_t count, level;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	count = data->vddci_voltage_table.count;
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		if (count > SMU_MAX_SMIO_LEVELS)
-+			count = SMU_MAX_SMIO_LEVELS;
-+		for (level = 0; level < count; ++level) {
-+			table->SmioTable1.Pattern[level].Voltage =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
-+			table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
-+
-+			table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
-+		}
-+	}
-+
-+	table->SmioMask1 = data->vddci_voltage_table.mask_low;
-+
-+	return 0;
-+}
-+
-+/**
-+* Preparation of vddc and vddgfx CAC tables for SMC.
-+*
-+* @param    hwmgr  the address of the hardware manager
-+* @param    table  the SMC DPM table structure to be populated
-+* @return   always 0
-+*/
-+static int ellesmere_populate_cac_table(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
-+			table_info->vddc_lookup_table;
-+	/* tables is already swapped, so in order to use the value from it,
-+	 * we need to swap it back.
-+	 * We are populating vddc CAC data to BapmVddc table
-+	 * in split and merged mode
-+	 */
-+	for (count = 0; count < lookup_table->count; count++) {
-+		index = phm_get_voltage_index(lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
-+		table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
-+		table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Preparation of voltage tables for SMC.
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    table   the SMC DPM table structure to be populated
-+* @return   always  0
-+*/
-+
-+int ellesmere_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	ellesmere_populate_smc_vddci_table(hwmgr, table);
-+	ellesmere_populate_smc_mvdd_table(hwmgr, table);
-+	ellesmere_populate_cac_table(hwmgr, table);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_Ulv *state)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
-+	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
-+			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-+
-+	state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	return ellesmere_populate_ulv_level(hwmgr, &table->Ulv);
-+}
-+
-+static int ellesmere_populate_smc_link_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
-+	int i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count)
-+	 * is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
-+				dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity = 1;
-+		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	data->smc_state_table.LinkLevelCount =
-+			(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static uint32_t ellesemere_get_xclk(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t reference_clock, tmp;
-+	struct cgs_display_info info = {0};
-+	struct cgs_mode_info mode_info;
-+
-+	info.mode_info = &mode_info;
-+
-+	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
-+
-+	if (tmp)
-+		return TCLK;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	reference_clock = mode_info.ref_clock;
-+
-+	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
-+
-+	if (0 != tmp)
-+		return reference_clock / 4;
-+
-+	return reference_clock;
-+}
-+
-+/**
-+* Calculates the SCLK dividers using the provided engine clock
-+*
-+* @param    hwmgr  the address of the hardware manager
-+* @param    clock  the engine clock to use to populate the structure
-+* @param    sclk   the SMC SCLK structure to be populated
-+*/
-+static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, SMU_SclkSetting *sclk_setting)
-+{
-+	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
-+	struct pp_atomctrl_clock_dividers_ai dividers;
-+
-+	uint32_t ref_clock;
-+	uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
-+	uint8_t i;
-+	int result;
-+	uint64_t temp;
-+
-+	sclk_setting->SclkFrequency = clock;
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
-+	if (result == 0) {
-+		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
-+		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
-+		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
-+		sclk_setting->PllRange = dividers.ucSclkPllRange;
-+		sclk_setting->SSc_En = dividers.ucSscEnable;
-+		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
-+		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
-+		return result;
-+	}
-+
-+	ref_clock = ellesemere_get_xclk(hwmgr);
-+
-+	for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+		if (clock > data->range_table[i].trans_lower_frequency
-+		&& clock <= data->range_table[i].trans_upper_frequency) {
-+			sclk_setting->PllRange = i;
-+			break;
-+		}
-+	}
-+
-+	sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
-+	temp <<= 0x10;
-+	sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
-+
-+	pcc_target_percent = 10; /*  Hardcode 10% for now. */
-+	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
-+	sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+
-+	ss_target_percent = 2; /*  Hardcode 2% for now. */
-+	sclk_setting->SSc_En = 0;
-+	if (ss_target_percent) {
-+		sclk_setting->SSc_En = 1;
-+		ss_target_freq = clock - (clock * ss_target_percent / 100);
-+		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
-+		temp <<= 0x10;
-+		sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
-+		uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i;
-+	uint16_t vddci;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	*voltage = *mvdd = 0;
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (dep_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (dep_table->entries[i].clk >= clock) {
-+			*voltage |= (dep_table->entries[i].vddc *
-+					VOLTAGE_SCALE) << VDDC_SHIFT;
-+			if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else if (dep_table->entries[i].vddci)
-+				*voltage |= (dep_table->entries[i].vddci *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else {
-+				vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						(dep_table->entries[i].vddc -
-+								(uint16_t)data->vddc_vddci_delta));
-+				*voltage |= (vddci * VOLTAGE_SCALE) <<	VDDCI_SHIFT;
-+			}
-+
-+			if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
-+					VOLTAGE_SCALE;
-+			else if (dep_table->entries[i].mvdd)
-+				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
-+					VOLTAGE_SCALE;
-+
-+			*voltage |= 1 << PHASES_SHIFT;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+				VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	else if (dep_table->entries[i-1].vddci) {
-+		vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+				(dep_table->entries[i].vddc -
-+						(uint16_t)data->vddc_vddci_delta));
-+		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	}
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
-+	else if (dep_table->entries[i].mvdd)
-+		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-+
-+	return 0;
-+}
-+
-+sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
-+						{VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
-+						{VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
-+						{VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
-+						{VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
-+						{VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
-+						{VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
-+						{VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
-+
-+static void ellesmere_get_sclk_range_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t i, ref_clk;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
-+	struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
-+
-+	ref_clk = ellesemere_get_xclk(hwmgr);
-+
-+	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
-+		for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+			table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
-+			table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
-+			table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
-+
-+			table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
-+			table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
-+
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
-+		}
-+		return;
-+	}
-+
-+	for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+
-+		data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
-+		data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
-+
-+		table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
-+		table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
-+		table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
-+
-+		table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
-+		table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
-+
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
-+	}
-+}
-+
-+/**
-+* Populates single SMC SCLK structure using the provided engine clock
-+*
-+* @param    hwmgr      the address of the hardware manager
-+* @param    clock the engine clock to use to populate the structure
-+* @param    sclk        the SMC SCLK structure to be populated
-+*/
-+
-+static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, uint16_t sclk_al_threshold,
-+		struct SMU74_Discrete_GraphicsLevel *level)
-+{
-+	int result, i, temp;
-+	/* PP_Clocks minClocks; */
-+	uint32_t mvdd;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMU_SclkSetting curr_sclk_setting = { 0 };
-+
-+	result = ellesmere_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
-+
-+	/* populate graphics levels */
-+	result = ellesmere_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_sclk, clock,
-+			&level->MinVoltage, &mvdd);
-+
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find VDDC voltage value for "
-+			"VDDC engine clock dependency table",
-+			return result);
-+	level->ActivityLevel = sclk_al_threshold;
-+
-+	level->CcPwrDynRm = 0;
-+	level->CcPwrDynRm1 = 0;
-+	level->EnabledForActivity = 0;
-+	level->EnabledForThrottle = 1;
-+	level->UpHyst = 10;
-+	level->DownHyst = 0;
-+	level->VoltageDownHyst = 0;
-+	level->PowerThrottle = 0;
-+
-+	/*
-+	* TODO: get minimum clocks from dal configaration
-+	* PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
-+	*/
-+	/* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
-+
-+	/* get level->DeepSleepDivId
-+	if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+		level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
-+	*/
-+	PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
-+	for (i = ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
-+		temp = clock / (1UL << i);
-+
-+		if (temp >= 2500 || i == 0)
-+			break;
-+	}
-+
-+	level->DeepSleepDivId = i;
-+
-+	/* Default to slow, highest DPM level will be
-+	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-+	 */
-+	if (data->update_up_hyst)
-+		level->UpHyst = (uint8_t)data->up_hyst;
-+	if (data->update_down_hyst)
-+		level->DownHyst = (uint8_t)data->down_hyst;
-+
-+	level->SclkSetting = curr_sclk_setting;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
-+	return 0;
-+}
-+
-+/**
-+* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
-+*
-+* @param    hwmgr      the address of the hardware manager
-+*/
-+static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
-+	int result = 0;
-+	uint32_t array = data->dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
-+			SMU74_MAX_LEVELS_GRAPHICS;
-+	struct SMU74_Discrete_GraphicsLevel *levels =
-+			data->smc_state_table.GraphicsLevel;
-+	uint32_t i, max_entry;
-+	uint8_t hightest_pcie_level_enabled = 0,
-+		lowest_pcie_level_enabled = 0,
-+		mid_pcie_level_enabled = 0,
-+		count = 0;
-+
-+	ellesmere_get_sclk_range_table(hwmgr);
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+
-+		result = ellesmere_populate_single_graphic_level(hwmgr,
-+				dpm_table->sclk_table.dpm_levels[i].value,
-+				(uint16_t)data->activity_target[i],
-+				&(data->smc_state_table.GraphicsLevel[i]));
-+		if (result)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			levels[i].DeepSleepDivId = 0;
-+	}
-+
-+	data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+	data->smc_state_table.GraphicsDpmLevelCount =
-+			(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
-+				"There must be 1 or more PCIE levels defined in PPTable.",
-+				return -EINVAL);
-+		max_entry = pcie_entry_cnt - 1;
-+		for (i = 0; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel =
-+					(uint8_t) ((i < max_entry) ? i : max_entry);
-+	} else {
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-+			hightest_pcie_level_enabled++;
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << lowest_pcie_level_enabled)) == 0))
-+			lowest_pcie_level_enabled++;
-+
-+		while ((count < hightest_pcie_level_enabled) &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
-+			count++;
-+
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-+				hightest_pcie_level_enabled ?
-+						(lowest_pcie_level_enabled + 1 + count) :
-+						hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to hightest_pcie_level_enabled */
-+		for (i = 2; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled */
-+		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled */
-+		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change */
-+	result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, data->sram_end);
-+
-+	return result;
-+}
-+
-+static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+	struct cgs_display_info info = {0, 0, NULL};
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (table_info->vdd_dep_on_mclk) {
-+		result = ellesmere_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk, clock,
-+				&mem_level->MinVoltage, &mem_level->MinMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find MinVddc voltage value from memory "
-+				"VDDC voltage dependency table", return result);
-+	}
-+
-+	mem_level->MclkFrequency = clock;
-+	mem_level->StutterEnable = 0;
-+	mem_level->EnabledForThrottle = 1;
-+	mem_level->EnabledForActivity = 0;
-+	mem_level->UpHyst = 0;
-+	mem_level->DownHyst = 100;
-+	mem_level->VoltageDownHyst = 0;
-+	mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	mem_level->StutterEnable = false;
-+
-+	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	if ((data->mclk_stutter_mode_threshold) &&
-+		(clock <= data->mclk_stutter_mode_threshold) &&
-+		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
-+				STUTTER_ENABLE) & 0x1))
-+		mem_level->StutterEnable = true;
-+
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
-+	}
-+	return result;
-+}
-+
-+/**
-+* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
-+*
-+* @param    hwmgr      the address of the hardware manager
-+*/
-+static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t array = data->dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
-+	uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
-+			SMU74_MAX_LEVELS_MEMORY;
-+	struct SMU74_Discrete_MemoryLevel *levels =
-+			data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+				"can not populate memory level as memory clock is zero",
-+				return -EINVAL);
-+		result = ellesmere_populate_single_memory_level(hwmgr,
-+				dpm_table->mclk_table.dpm_levels[i].value,
-+				&levels[i]);
-+		if (result)
-+			return result;
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	levels[0].EnabledForActivity = 1;
-+
-+	/* in order to prevent MC activity from stutter mode to push DPM up.
-+	 * the UVD change complements this by putting the MCLK in
-+	 * a higher state by default such that we are not effected by
-+	 * up threshold or and MCLK DPM latency.
-+	 */
-+	levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
-+	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-+
-+	data->smc_state_table.MemoryDpmLevelCount =
-+			(uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high */
-+	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change */
-+	result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, data->sram_end);
-+
-+	return result;
-+}
-+
-+/**
-+* Populates the SMC MVDD structure using the provided memory clock.
-+*
-+* @param    hwmgr      the address of the hardware manager
-+* @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
-+* @param    voltage     the SMC VOLTAGE structure to be populated
-+*/
-+int ellesmere_populate_mvdd_value(struct pp_hwmgr *hwmgr,
-+		uint32_t mclk, SMIO_Pattern *smio_pat)
-+{
-+	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
-+				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
-+				"MVDD Voltage is outside the supported range.",
-+				return -EINVAL);
-+	} else
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint32_t sclk_frequency;
-+	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMIO_Pattern vol_level;
-+	uint32_t mvdd;
-+	uint16_t us_mvdd;
-+
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0,
-+		 * already converted to SMC_UL */
-+		sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
-+		result = ellesmere_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_sclk,
-+				table->ACPILevel.SclkFrequency,
-+				&table->ACPILevel.MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDC voltage value "
-+				"in Clock Dependency Table", );
-+	} else {
-+		sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
-+		table->ACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	result = ellesmere_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
-+	PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	table->ACPILevel.DeepSleepDivId = 0;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->dpm_table.mclk_table.dpm_levels[0].value;
-+		result = ellesmere_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk,
-+				table->MemoryACPILevel.MclkFrequency,
-+				&table->MemoryACPILevel.MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDCI voltage value "
-+				"in Clock Dependency Table",
-+				);
-+	} else {
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->vbios_boot_state.mclk_bootup_value;
-+		table->MemoryACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	us_mvdd = 0;
-+	if ((ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
-+			(data->mclk_dpm_key_disabled))
-+		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	else {
-+		if (!ellesmere_populate_mvdd_value(hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[0].value,
-+				&vol_level))
-+			us_mvdd = vol_level.Voltage;
-+	}
-+
-+	if (0 == ellesmere_populate_mvdd_value(hwmgr, 0, &vol_level))
-+		table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	table->MemoryACPILevel.StutterEnable = false;
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	table->MemoryACPILevel.ActivityLevel =
-+			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-+
-+	return result;
-+}
-+
-+static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	table->VceLevelCount = (uint8_t)(mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage |=
-+				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->VceLevel[count].MinVoltage |=
-+				((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/*retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t)(mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int ellesmere_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
-+		int32_t eng_clock, int32_t mem_clock,
-+		SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
-+{
-+	uint32_t dram_timing;
-+	uint32_t dram_timing2;
-+	uint32_t burst_time;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+			eng_clock, mem_clock);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
-+	arb_regs->McArbBurstTime   = (uint8_t)burst_time;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
-+	uint32_t i, j;
-+	int result = 0;
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = ellesmere_populate_memory_timing_parameters(hwmgr,
-+					data->dpm_table.sclk_table.dpm_levels[i].value,
-+					data->dpm_table.mclk_table.dpm_levels[j].value,
-+					&arb_regs.entries[i][j]);
-+			if (result == 0)
-+				result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
-+			if (result != 0)
-+				return result;
-+		}
-+	}
-+
-+	result = ellesmere_copy_bytes_to_smc(
-+			hwmgr->smumgr,
-+			data->arb_table_start,
-+			(uint8_t *)&arb_regs,
-+			sizeof(SMU74_Discrete_MCArbDramTimingTable),
-+			data->sram_end);
-+	return result;
-+}
-+
-+static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	table->UvdLevelCount = (uint8_t)(mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
-+
-+	}
-+	return result;
-+}
-+
-+static int ellesmere_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table */
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(table->GraphicsBootLevel));
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+			data->vbios_boot_state.mclk_bootup_value,
-+			(uint32_t *)&(table->MemoryBootLevel));
-+
-+	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
-+			VOLTAGE_SCALE;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return 0;
-+}
-+
-+
-+static int ellesmere_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_sclk->entries[level].clk >=
-+				data->vbios_boot_state.sclk_bootup_value) {
-+			data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
-+				data->vbios_boot_state.mclk_bootup_value) {
-+			data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-+			volt_with_cks, value;
-+	uint16_t clock_freq_u16;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-+			volt_offset = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+
-+	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-+
-+	/* Read SMU_Eefuse to read and calculate RO and determine
-+	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
-+	 */
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (146 * 4));
-+	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (148 * 4));
-+	efuse &= 0xFF000000;
-+	efuse = efuse >> 24;
-+	efuse2 &= 0xF;
-+
-+	if (efuse2 == 1)
-+		ro = (2300 - 1350) * efuse / 255 + 1350;
-+	else
-+		ro = (2500 - 1000) * efuse / 255 + 1000;
-+
-+	if (ro >= 1660)
-+		type = 0;
-+	else
-+		type = 1;
-+
-+	/* Populate Stretch amount */
-+	data->smc_state_table.ClockStretcherAmount = stretch_amount;
-+
-+	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
-+	for (i = 0; i < sclk_table->count; i++) {
-+		data->smc_state_table.Sclk_CKS_masterEn0_7 |=
-+				sclk_table->entries[i].cks_enable << i;
-+		volt_without_cks = (uint32_t)((14041 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-+			(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-+		volt_with_cks = (uint32_t)((13946 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-+			(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
-+		if (volt_without_cks >= volt_with_cks)
-+			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
-+					sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
-+		data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
-+	}
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			STRETCH_ENABLE, 0x0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x1);
-+	/* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x0);
-+
-+	/* Populate CKS Lookup Table */
-+	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
-+		stretch_amount2 = 0;
-+	else if (stretch_amount == 3 || stretch_amount == 4)
-+		stretch_amount2 = 1;
-+	else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+		PP_ASSERT_WITH_CODE(false,
-+				"Stretch Amount in PPTable not supported\n",
-+				return -EINVAL);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL);
-+	value &= 0xFFC2FF87;
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-+			ellesmere_clock_stretcher_lookup_table[stretch_amount2][0];
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-+			ellesmere_clock_stretcher_lookup_table[stretch_amount2][1];
-+	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
-+			GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
-+	if (ellesmere_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
-+	&& ellesmere_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
-+		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-+		value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-+		/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-+		value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-+		/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-+		value |= (ellesmere_clock_stretch_amount_conversion
-+				[ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]]
-+				 [stretch_amount]) << 3;
-+	}
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-+			ellesmere_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-+			(ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL, value);
-+
-+	/* Populate DDT Lookup Table */
-+	for (i = 0; i < 4; i++) {
-+		/* Assign the minimum and maximum VID stored
-+		 * in the last row of Clock Stretcher Voltage Table.
-+		 */
-+		data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
-+				(uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][2];
-+		data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
-+				(uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][3];
-+		/* Loop through each SCLK and check the frequency
-+		 * to see if it lies within the frequency for clock stretcher.
-+		 */
-+		for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
-+			cks_setting = 0;
-+			clock_freq = PP_SMC_TO_HOST_UL(
-+					data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
-+			/* Check the allowed frequency against the sclk level[j].
-+			 *  Sclk's endianness has already been converted,
-+			 *  and it's in 10Khz unit,
-+			 *  as opposed to Data table, which is in Mhz unit.
-+			 */
-+			if (clock_freq >= (ellesmere_clock_stretcher_ddt_table[type][i][0]) * 100) {
-+				cks_setting |= 0x2;
-+				if (clock_freq < (ellesmere_clock_stretcher_ddt_table[type][i][1]) * 100)
-+					cks_setting |= 0x1;
-+			}
-+			data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
-+							|= cks_setting << (j * 2);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_US(
-+			data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
-+	value &= 0xFFFFFFFE;
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-+
-+	return 0;
-+}
-+
-+/**
-+* Populates the SMC VRConfig field in DPM table.
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    table   the SMC DPM table structure to be populated
-+* @return   always 0
-+*/
-+static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint16_t config;
-+
-+	config = VR_MERGED_WITH_VDDC;
-+	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-+
-+	/* Set Vddc Voltage Controller */
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= config;
-+	} else {
-+		PP_ASSERT_WITH_CODE(false,
-+				"VDDC should be on SVI2 control in merged mode!",
-+				);
-+	}
-+	/* Set Vddci Voltage Controller */
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	}
-+	/* Set Mvdd Voltage Controller */
-+	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		config = VR_SVI2_PLANE_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		config = VR_SMIO_PATTERN_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Initializes the SMC table and uploads it
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
-+	const struct ellesmere_ulv_parm *ulv = &(data->ulv);
-+	uint8_t i;
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+
-+	result = ellesmere_setup_default_dpm_tables(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to setup default DPM tables!", return result);
-+
-+	if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control)
-+		ellesmere_populate_smc_voltage_tables(hwmgr, table);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
-+		result = ellesmere_populate_ulv_state(hwmgr, table);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to initialize ULV state!", return result);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_ULV_PARAMETER, PPELLESMERE_CGULVPARAMETER_DFLT);
-+	}
-+
-+	result = ellesmere_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Link Level!", return result);
-+
-+	result = ellesmere_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Graphics Level!", return result);
-+
-+	result = ellesmere_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Memory Level!", return result);
-+
-+	result = ellesmere_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACPI Level!", return result);
-+
-+	result = ellesmere_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize VCE Level!", return result);
-+
-+	result = ellesmere_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize SAMU Level!", return result);
-+
-+	/* Since only the initial state is completely set up at this point
-+	 * (the other states are just copies of the boot state) we only
-+	 * need to populate the  ARB settings for the initial state.
-+	 */
-+	result = ellesmere_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to Write ARB settings for the initial state.", return result);
-+
-+	result = ellesmere_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize UVD Level!", return result);
-+
-+	result = ellesmere_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot Level!", return result);
-+
-+	result = ellesmere_populate_smc_initailial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot State!", return result);
-+
-+	result = ellesmere_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate BAPM Parameters!", return result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = ellesmere_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to populate Clock Stretcher Data Table!",
-+				return result);
-+	}
-+
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+			table_info->cac_dtp_table->usTargetOperatingTemp *
-+			ELLESMERE_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow  =
-+			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+			ELLESMERE_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable = 1;
-+	table->MemoryInterval = 1;
-+	table->VoltageResponseTime = 0;
-+	table->PhaseResponseTime = 0;
-+	table->MemoryThermThrottleEnable = 1;
-+	table->PCIeBootLinkLevel = 0;
-+	table->PCIeGenInterval = 1;
-+
-+	result = ellesmere_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate VRConfig setting!", return result);
-+
-+	table->ThermGpio = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
-+		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+	} else {
-+		table->VRHotGpio = ELLESMERE_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
-+			&gpio_pin)) {
-+		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = ELLESMERE_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	/* Thermal Output GPIO */
-+	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
-+			&gpio_pin)) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+
-+		/* For porlarity read GPIOPAD_A with assigned Gpio pin
-+		 * since VBIOS will program this register to set 'inactive state',
-+		 * driver can then determine 'active state' from this and
-+		 * program SMU with correct polarity
-+		 */
-+		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
-+					& (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
-+		&& phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+	} else {
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr,
-+			data->dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, SystemFlags),
-+			(uint8_t *)&(table->SystemFlags),
-+			sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
-+			data->sram_end);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload dpm data to SMC memory!", return result);
-+
-+	return 0;
-+}
-+
-+/**
-+* Initialize the ARB DRAM timing table's index field.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/* This is a read-modify-write on the first byte of the ARB table.
-+	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
-+	 * is the field 'current'.
-+	 * This solution is ugly, but we never write the whole table only
-+	 * individual fields in it.
-+	 * In reality this field should not be in that structure
-+	 * but in a soft register.
-+	 */
-+	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start, &tmp, data->sram_end);
-+
-+	if (result)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return ellesmere_write_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start, tmp, data->sram_end);
-+}
-+
-+static int ellesmere_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_EnableVRHotGPIOInterrupt);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_enable_sclk_control(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-+			SCLK_PWRMGT_OFF, 0);
-+	return 0;
-+}
-+
-+static int ellesmere_enable_ulv(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_ulv_parm *ulv = &(data->ulv);
-+
-+	if (ulv->ulv_supported)
-+		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep)) {
-+		if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to enable Master Deep Sleep switch failed!",
-+					return -1);
-+	} else {
-+		if (smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to disable Master Deep Sleep switch failed!",
-+					return -1);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	/* enable SCLK dpm */
-+	if (!data->sclk_dpm_key_disabled)
-+		PP_ASSERT_WITH_CODE(
-+		(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
-+		"Failed to enable SCLK DPM during DPM Start Function!",
-+		return -1);
-+
-+	/* enable MCLK dpm */
-+	if (0 == data->mclk_dpm_key_disabled) {
-+
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_MCLKDPM_Enable)),
-+				"Failed to enable MCLK DPM during DPM Start Function!",
-+				return -1);
-+
-+
-+		PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
-+		udelay(10);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	/*enable general power management */
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+			GLOBAL_PWRMGT_EN, 1);
-+
-+	/* enable sclk deep sleep */
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-+			DYNAMIC_PM_EN, 1);
-+
-+	/* prepare for PCIE DPM */
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			data->soft_regs_start + offsetof(SMU74_SoftRegisters,
-+					VoltageChangeTimeout), 0x1000);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
-+			SWRST_COMMAND_1, RESETLC, 0x0);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_Voltage_Cntl_Enable)),
-+			"Failed to enable voltage DPM during DPM Start Function!",
-+			return -1);
-+
-+	if (ellesmere_enable_sclk_mclk_dpm(hwmgr)) {
-+		printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
-+		return -1;
-+	}
-+
-+	/* enable PCIE dpm */
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_Enable)),
-+				"Failed to enable pcie DPM during DPM Start Function!",
-+				return -1);
-+	}
-+
-+	PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_EnableACDCGPIOInterrupt)),
-+					"Failed to enable AC DC GPIO Interrupt!",
-+			);
-+
-+	return 0;
-+}
-+
-+static void ellesmere_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
-+{
-+	bool protection;
-+	enum DPM_EVENT_SRC src;
-+
-+	switch (sources) {
-+	default:
-+		printk(KERN_ERR "Unknown throttling event sources.");
-+		/* fall through */
-+	case 0:
-+		protection = false;
-+		/* src is unused */
-+		break;
-+	case (1 << PHM_AutoThrottleSource_Thermal):
-+		protection = true;
-+		src = DPM_EVENT_SRC_DIGITAL;
-+		break;
-+	case (1 << PHM_AutoThrottleSource_External):
-+		protection = true;
-+		src = DPM_EVENT_SRC_EXTERNAL;
-+		break;
-+	case (1 << PHM_AutoThrottleSource_External) |
-+			(1 << PHM_AutoThrottleSource_Thermal):
-+		protection = true;
-+		src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
-+		break;
-+	}
-+	/* Order matters - don't enable thermal protection for the wrong source. */
-+	if (protection) {
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
-+				DPM_EVENT_SRC, src);
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+				THERMAL_PROTECTION_DIS,
-+				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_ThermalController));
-+	} else
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+				THERMAL_PROTECTION_DIS, 1);
-+}
-+
-+static int ellesmere_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
-+		PHM_AutoThrottleSource source)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (!(data->active_auto_throttle_sources & (1 << source))) {
-+		data->active_auto_throttle_sources |= 1 << source;
-+		ellesmere_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
-+	}
-+	return 0;
-+}
-+
-+static int ellesmere_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
-+{
-+	return ellesmere_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
-+}
-+
-+int ellesmere_pcie_performance_request(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	data->pcie_performance_request = true;
-+
-+	return 0;
-+}
-+
-+int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+	tmp_result = (!ellesmere_is_dpm_running(hwmgr)) ? 0 : -1;
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"DPM is already running right now, no need to enable DPM!",
-+			return 0);
-+
-+	if (ellesmere_voltage_control(hwmgr)) {
-+		tmp_result = ellesmere_enable_voltage_control(hwmgr);
-+		PP_ASSERT_WITH_CODE(tmp_result == 0,
-+				"Failed to enable voltage control!",
-+				result = tmp_result);
-+
-+		tmp_result = ellesmere_construct_voltage_tables(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to contruct voltage tables!",
-+				result = tmp_result);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport))
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalController))
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
-+
-+	tmp_result = ellesmere_program_static_screen_threshold_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program static screen threshold parameters!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_display_gap(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable display gap!", result = tmp_result);
-+
-+	tmp_result = ellesmere_program_voting_clients(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program voting clients!", result = tmp_result);
-+
-+	tmp_result = ellesmere_process_firmware_header(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to process firmware header!", result = tmp_result);
-+
-+	tmp_result = ellesmere_initial_switch_from_arbf0_to_f1(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize switch from ArbF0 to F1!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_init_smc_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize SMC table!", result = tmp_result);
-+
-+	tmp_result = ellesmere_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize ARB table index!", result = tmp_result);
-+
-+	tmp_result = ellesmere_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to populate PM fuses!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_vrhot_gpio_interrupt(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_sclk_control(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable SCLK control!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_ulv(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable ULV!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_deep_sleep_master_switch(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable deep sleep master switch!", result = tmp_result);
-+
-+	tmp_result = ellesmere_start_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to start DPM!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_smc_cac(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable SMC CAC!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_power_containment(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable power containment!", result = tmp_result);
-+
-+	tmp_result = ellesmere_power_control_set_level(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to power control set level!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_thermal_auto_throttle(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable thermal auto throttle!", result = tmp_result);
-+
-+	tmp_result = ellesmere_pcie_performance_request(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable thermal auto throttle!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+int ellesmere_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+
-+	return 0;
-+}
-+
-+int ellesmere_reset_asic_tasks(struct pp_hwmgr *hwmgr)
-+{
-+
-+	return 0;
-+}
-+
-+int ellesmere_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
-+{
-+	return phm_hwmgr_backend_fini(hwmgr);
-+}
-+
-+int ellesmere_set_features_platform_caps(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep);
-+
-+	if (data->mvdd_control == ELLESMERE_VOLTAGE_CONTROL_NONE)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EnableMVDDControl);
-+
-+	if (data->vddci_control == ELLESMERE_VOLTAGE_CONTROL_NONE)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ControlVDDCI);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			 PHM_PlatformCaps_TablelessHardwareInterface);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableSMU7ThermalManagement);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DynamicPowerManagement);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TablelessHardwareInterface);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_SMC);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_NonABMSupportInPPLib);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_DynamicUVDState);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_SclkThrottleLowNotification);
-+
-+	/* power tune caps Assume disabled */
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_PowerContainment);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+							PHM_PlatformCaps_CAC);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_SQRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_DBRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_TDRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_TCPRamping);
-+
-+	return 0;
-+}
-+
-+static void ellesmere_init_dpm_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	ellesmere_initialize_power_tune_defaults(hwmgr);
-+
-+	data->pcie_gen_performance.max = PP_PCIEGen1;
-+	data->pcie_gen_performance.min = PP_PCIEGen3;
-+	data->pcie_gen_power_saving.max = PP_PCIEGen1;
-+	data->pcie_gen_power_saving.min = PP_PCIEGen3;
-+	data->pcie_lane_performance.max = 0;
-+	data->pcie_lane_performance.min = 16;
-+	data->pcie_lane_power_saving.max = 0;
-+	data->pcie_lane_power_saving.min = 16;
-+}
-+
-+/**
-+* Get Leakage VDDC based on leakage ID.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint16_t vv_id;
-+	uint16_t vddc = 0;
-+	uint16_t i, j;
-+	uint32_t sclk = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	int result;
-+
-+	for (i = 0; i < ELLESMERE_MAX_LEAKAGE_COUNT; i++) {
-+		vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-+		if (!phm_get_sclk_for_voltage_evv(hwmgr,
-+				table_info->vddc_lookup_table, vv_id, &sclk)) {
-+			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_ClockStretcher)) {
-+				for (j = 1; j < sclk_table->count; j++) {
-+					if (sclk_table->entries[j].clk == sclk &&
-+							sclk_table->entries[j].cks_enable == 0) {
-+						sclk += 5000;
-+						break;
-+					}
-+				}
-+			}
-+
-+
-+			PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
-+							VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
-+						"Error retrieving EVV voltage value!",
-+						continue);
-+
-+
-+			/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
-+			PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
-+					"Invalid VDDC value", result = -EINVAL;);
-+
-+			/* the voltage should not be zero nor equal to leakage ID */
-+			if (vddc != 0 && vddc != vv_id) {
-+				data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
-+				data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
-+				data->vddc_leakage.count++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Change virtual leakage voltage to actual value.
-+ *
-+ * @param     hwmgr  the address of the powerplay hardware manager.
-+ * @param     pointer to changing voltage
-+ * @param     pointer to leakage table
-+ */
-+static void ellesmere_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
-+		uint16_t *voltage, struct ellesmere_leakage_voltage *leakage_table)
-+{
-+	uint32_t index;
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 */
-+	for (index = 0; index < leakage_table->count; index++) {
-+		/* if this voltage matches a leakage voltage ID */
-+		/* patch with actual leakage voltage */
-+		if (leakage_table->leakage_id[index] == *voltage) {
-+			*voltage = leakage_table->actual_voltage[index];
-+			break;
-+		}
-+	}
-+
-+	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
-+		printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
-+}
-+
-+/**
-+* Patch voltage lookup table by EVV leakages.
-+*
-+* @param     hwmgr  the address of the powerplay hardware manager.
-+* @param     pointer to voltage lookup table
-+* @param     pointer to leakage table
-+* @return     always 0
-+*/
-+static int ellesmere_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table,
-+		struct ellesmere_leakage_voltage *leakage_table)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < lookup_table->count; i++)
-+		ellesmere_patch_with_vdd_leakage(hwmgr,
-+				&lookup_table->entries[i].us_vdd, leakage_table);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_patch_clock_voltage_limits_with_vddc_leakage(
-+		struct pp_hwmgr *hwmgr, struct ellesmere_leakage_voltage *leakage_table,
-+		uint16_t *vddc)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	ellesmere_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
-+			table_info->max_clock_voltage_on_dc.vddc;
-+	return 0;
-+}
-+
-+static int ellesmere_patch_voltage_dependency_tables_with_lookup_table(
-+		struct pp_hwmgr *hwmgr)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	for (entryId = 0; entryId < sclk_table->count; ++entryId) {
-+		voltageId = sclk_table->entries[entryId].vddInd;
-+		sclk_table->entries[entryId].vddc =
-+				table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mclk_table->count; ++entryId) {
-+		voltageId = mclk_table->entries[entryId].vddInd;
-+		mclk_table->entries[entryId].vddc =
-+			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mm_table->count; ++entryId) {
-+		voltageId = mm_table->entries[entryId].vddcInd;
-+		mm_table->entries[entryId].vddc =
-+			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	return 0;
-+
-+}
-+
-+static int ellesmere_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	/* Need to determine if we need calculated voltage. */
-+	return 0;
-+}
-+
-+static int ellesmere_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
-+{
-+	/* Need to determine if we need calculated voltage from mm table. */
-+	return 0;
-+}
-+
-+static int ellesmere_sort_lookup_table(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
-+{
-+	uint32_t table_size, i, j;
-+	struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
-+	table_size = lookup_table->count;
-+
-+	PP_ASSERT_WITH_CODE(0 != lookup_table->count,
-+		"Lookup table is empty", return -EINVAL);
-+
-+	/* Sorting voltages */
-+	for (i = 0; i < table_size - 1; i++) {
-+		for (j = i + 1; j > 0; j--) {
-+			if (lookup_table->entries[j].us_vdd <
-+					lookup_table->entries[j - 1].us_vdd) {
-+				tmp_voltage_lookup_record = lookup_table->entries[j - 1];
-+				lookup_table->entries[j - 1] = lookup_table->entries[j];
-+				lookup_table->entries[j] = tmp_voltage_lookup_record;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_complete_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	int tmp_result;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	tmp_result = ellesmere_patch_lookup_table_with_leakage(hwmgr,
-+			table_info->vddc_lookup_table, &(data->vddc_leakage));
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = ellesmere_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
-+			&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = ellesmere_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = ellesmere_calc_voltage_dependency_tables(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = ellesmere_calc_mm_voltage_dependency_table(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = ellesmere_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	return result;
-+}
-+
-+static int ellesmere_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
-+						table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
-+						table_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-+		"VDD dependency on SCLK table is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-+		"VDD dependency on SCLK table has to have is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-+		"VDD dependency on MCLK table is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
-+		"VDD dependency on MCLK table has to have is missing.	 \
-+		This table is mandatory", return -EINVAL);
-+
-+	table_info->max_clock_voltage_on_ac.sclk =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
-+	table_info->max_clock_voltage_on_ac.mclk =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
-+	table_info->max_clock_voltage_on_ac.vddc =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
-+	table_info->max_clock_voltage_on_ac.vddci =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
-+
-+	return 0;
-+}
-+
-+int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
-+	uint32_t temp_reg;
-+	int result;
-+
-+	data->dll_default_on = false;
-+	data->sram_end = SMC_RAM_END;
-+
-+	data->disable_dpm_mask = 0xFF;
-+	data->static_screen_threshold = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT;
-+	data->static_screen_threshold_unit = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT;
-+	data->activity_target[0] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[1] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[2] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[3] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[4] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[5] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[6] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+	data->activity_target[7] = PPELLESMERE_TARGETACTIVITY_DFLT;
-+
-+	data->voting_rights_clients0 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0;
-+	data->voting_rights_clients1 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1;
-+	data->voting_rights_clients2 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2;
-+	data->voting_rights_clients3 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3;
-+	data->voting_rights_clients4 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4;
-+	data->voting_rights_clients5 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5;
-+	data->voting_rights_clients6 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6;
-+	data->voting_rights_clients7 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7;
-+
-+	data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
-+
-+	data->mclk_activity_target = PPELLESMERE_MCLK_TARGETACTIVITY_DFLT;
-+
-+	/* need to set voltage control types before EVV patching */
-+	data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
-+	data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
-+	data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
-+
-+	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
-+		data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_DynamicPatchPowerState);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableMVDDControl)) {
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
-+			data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO;
-+		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
-+			data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ControlVDDCI)) {
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
-+			data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO;
-+		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
-+			data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	ellesmere_set_features_platform_caps(hwmgr);
-+
-+	ellesmere_init_dpm_defaults(hwmgr);
-+
-+	/* Get leakage voltage based on leakage ID. */
-+	result = ellesmere_get_evv_voltages(hwmgr);
-+
-+	if (result) {
-+		printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
-+		return -1;
-+	}
-+
-+	ellesmere_complete_dependency_tables(hwmgr);
-+	ellesmere_set_private_data_based_on_pptable(hwmgr);
-+
-+	/* Initalize Dynamic State Adjustment Rule Settings */
-+	result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
-+
-+	if (0 == result) {
-+		struct cgs_system_info sys_info = {0};
-+
-+		data->is_tlu_enabled = 0;
-+
-+		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
-+							ELLESMERE_MAX_HARDWARE_POWERLEVELS;
-+		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
-+		hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
-+		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
-+/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
-+		hwmgr->platform_descriptor.clockStep.engineClock = 500;
-+		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
-+
-+		if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
-+			temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
-+			switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
-+			case 0:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
-+				break;
-+			case 1:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
-+				break;
-+			case 2:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
-+				break;
-+			case 3:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
-+				break;
-+			case 4:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
-+				break;
-+			default:
-+				PP_ASSERT_WITH_CODE(0,
-+				"Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
-+				);
-+				break;
-+			}
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
-+		}
-+
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_gen_cap = 0x30007;
-+		else
-+			data->pcie_gen_cap = (uint32_t)sys_info.value;
-+		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-+			data->pcie_spc_cap = 20;
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_lane_cap = 0x2f0000;
-+		else
-+			data->pcie_lane_cap = (uint32_t)sys_info.value;
-+	} else {
-+		/* Ignore return value in here, we are cleaning up a mess. */
-+		ellesmere_hwmgr_backend_fini(hwmgr);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_force_dpm_highest(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t level, tmp;
-+
-+	if (!data->pcie_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_ForceLevel, level);
-+		}
-+	}
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+						(1 << level));
-+		}
-+	}
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+						(1 << level));
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	phm_apply_dal_min_voltage_request(hwmgr);
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+	}
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (!ellesmere_is_dpm_running(hwmgr))
-+		return -EINVAL;
-+
-+	if (!data->pcie_dpm_key_disabled) {
-+		smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_PCIeDPM_UnForceLevel);
-+	}
-+
-+	return ellesmere_upload_dpm_level_enable_mask(hwmgr);
-+}
-+
-+static int ellesmere_force_dpm_lowest(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data =
-+			(struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t level;
-+
-+	if (!data->sclk_dpm_key_disabled)
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = phm_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+							    (1 << level));
-+
-+	}
-+/* uvd is enabled, can't set mclk low right now
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			level = phm_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+							    (1 << level));
-+		}
-+	}
-+*/
-+	if (!data->pcie_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-+			level = phm_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.pcie_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_PCIeDPM_ForceLevel,
-+							    (level));
-+		}
-+	}
-+
-+	return 0;
-+
-+}
-+static int ellesmere_force_dpm_level(struct pp_hwmgr *hwmgr,
-+				enum amd_dpm_forced_level level)
-+{
-+	int ret = 0;
-+
-+	switch (level) {
-+	case AMD_DPM_FORCED_LEVEL_HIGH:
-+		ret = ellesmere_force_dpm_highest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_LOW:
-+		ret = ellesmere_force_dpm_lowest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_AUTO:
-+		ret = ellesmere_unforce_dpm_levels(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	hwmgr->dpm_level = level;
-+
-+	return ret;
-+}
-+
-+static int ellesmere_get_power_state_size(struct pp_hwmgr *hwmgr)
-+{
-+	return sizeof(struct ellesmere_power_state);
-+}
-+
-+
-+static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				struct pp_power_state *request_ps,
-+			const struct pp_power_state *current_ps)
-+{
-+
-+	struct ellesmere_power_state *ellesmere_ps =
-+				cast_phw_ellesmere_power_state(&request_ps->hardware);
-+	uint32_t sclk;
-+	uint32_t mclk;
-+	struct PP_Clocks minimum_clocks = {0};
-+	bool disable_mclk_switching;
-+	bool disable_mclk_switching_for_frame_lock;
-+	struct cgs_display_info info = {0};
-+	const struct phm_clock_and_voltage_limits *max_limits;
-+	uint32_t i;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int32_t count;
-+	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
-+
-+	data->battery_state = (PP_StateUILabel_Battery ==
-+			request_ps->classification.ui_label);
-+
-+	PP_ASSERT_WITH_CODE(ellesmere_ps->performance_level_count == 2,
-+				 "VI should always have 2 performance levels",
-+				);
-+
-+	max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
-+			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
-+			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
-+
-+	/* Cap clock DPM tables at DC MAX if it is in DC. */
-+	if (PP_PowerSource_DC == hwmgr->power_source) {
-+		for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
-+			if (ellesmere_ps->performance_levels[i].memory_clock > max_limits->mclk)
-+				ellesmere_ps->performance_levels[i].memory_clock = max_limits->mclk;
-+			if (ellesmere_ps->performance_levels[i].engine_clock > max_limits->sclk)
-+				ellesmere_ps->performance_levels[i].engine_clock = max_limits->sclk;
-+		}
-+	}
-+
-+	ellesmere_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
-+	ellesmere_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-+
-+	/* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState)) {
-+		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
-+		stable_pstate_sclk = (max_limits->sclk * 75) / 100;
-+
-+		for (count = table_info->vdd_dep_on_sclk->count - 1;
-+				count >= 0; count--) {
-+			if (stable_pstate_sclk >=
-+					table_info->vdd_dep_on_sclk->entries[count].clk) {
-+				stable_pstate_sclk =
-+						table_info->vdd_dep_on_sclk->entries[count].clk;
-+				break;
-+			}
-+		}
-+
-+		if (count < 0)
-+			stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
-+
-+		stable_pstate_mclk = max_limits->mclk;
-+
-+		minimum_clocks.engineClock = stable_pstate_sclk;
-+		minimum_clocks.memoryClock = stable_pstate_mclk;
-+	}
-+
-+	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
-+		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
-+
-+	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
-+		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-+
-+	ellesmere_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-+
-+	if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
-+				hwmgr->platform_descriptor.overdriveLimit.engineClock),
-+				"Overdrive sclk exceeds limit",
-+				hwmgr->gfx_arbiter.sclk_over_drive =
-+						hwmgr->platform_descriptor.overdriveLimit.engineClock);
-+
-+		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
-+			ellesmere_ps->performance_levels[1].engine_clock =
-+					hwmgr->gfx_arbiter.sclk_over_drive;
-+	}
-+
-+	if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
-+				hwmgr->platform_descriptor.overdriveLimit.memoryClock),
-+				"Overdrive mclk exceeds limit",
-+				hwmgr->gfx_arbiter.mclk_over_drive =
-+						hwmgr->platform_descriptor.overdriveLimit.memoryClock);
-+
-+		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
-+			ellesmere_ps->performance_levels[1].memory_clock =
-+					hwmgr->gfx_arbiter.mclk_over_drive;
-+	}
-+
-+	disable_mclk_switching_for_frame_lock = phm_cap_enabled(
-+				    hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
-+
-+	disable_mclk_switching = (1 < info.display_count) ||
-+				    disable_mclk_switching_for_frame_lock;
-+
-+	sclk = ellesmere_ps->performance_levels[0].engine_clock;
-+	mclk = ellesmere_ps->performance_levels[0].memory_clock;
-+
-+	if (disable_mclk_switching)
-+		mclk = ellesmere_ps->performance_levels
-+		[ellesmere_ps->performance_level_count - 1].memory_clock;
-+
-+	if (sclk < minimum_clocks.engineClock)
-+		sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
-+				max_limits->sclk : minimum_clocks.engineClock;
-+
-+	if (mclk < minimum_clocks.memoryClock)
-+		mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
-+				max_limits->mclk : minimum_clocks.memoryClock;
-+
-+	ellesmere_ps->performance_levels[0].engine_clock = sclk;
-+	ellesmere_ps->performance_levels[0].memory_clock = mclk;
-+
-+	ellesmere_ps->performance_levels[1].engine_clock =
-+		(ellesmere_ps->performance_levels[1].engine_clock >=
-+				ellesmere_ps->performance_levels[0].engine_clock) ?
-+						ellesmere_ps->performance_levels[1].engine_clock :
-+						ellesmere_ps->performance_levels[0].engine_clock;
-+
-+	if (disable_mclk_switching) {
-+		if (mclk < ellesmere_ps->performance_levels[1].memory_clock)
-+			mclk = ellesmere_ps->performance_levels[1].memory_clock;
-+
-+		ellesmere_ps->performance_levels[0].memory_clock = mclk;
-+		ellesmere_ps->performance_levels[1].memory_clock = mclk;
-+	} else {
-+		if (ellesmere_ps->performance_levels[1].memory_clock <
-+				ellesmere_ps->performance_levels[0].memory_clock)
-+			ellesmere_ps->performance_levels[1].memory_clock =
-+					ellesmere_ps->performance_levels[0].memory_clock;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState)) {
-+		for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
-+			ellesmere_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
-+			ellesmere_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
-+			ellesmere_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
-+			ellesmere_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
-+		}
-+	}
-+	return 0;
-+}
-+
-+
-+static int ellesmere_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct ellesmere_power_state  *ellesmere_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware);
-+
-+	if (low)
-+		return ellesmere_ps->performance_levels[0].memory_clock;
-+	else
-+		return ellesmere_ps->performance_levels
-+				[ellesmere_ps->performance_level_count-1].memory_clock;
-+}
-+
-+static int ellesmere_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct ellesmere_power_state  *ellesmere_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware);
-+
-+	if (low)
-+		return ellesmere_ps->performance_levels[0].engine_clock;
-+	else
-+		return ellesmere_ps->performance_levels
-+				[ellesmere_ps->performance_level_count-1].engine_clock;
-+}
-+
-+static int ellesmere_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
-+					struct pp_hw_power_state *hw_ps)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_power_state *ps = (struct ellesmere_power_state *)hw_ps;
-+	ATOM_FIRMWARE_INFO_V2_2 *fw_info;
-+	uint16_t size;
-+	uint8_t frev, crev;
-+	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-+
-+	/* First retrieve the Boot clocks and VDDC from the firmware info table.
-+	 * We assume here that fw_info is unchanged if this call fails.
-+	 */
-+	fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
-+			hwmgr->device, index,
-+			&size, &frev, &crev);
-+	if (!fw_info)
-+		/* During a test, there is no firmware info table. */
-+		return 0;
-+
-+	/* Patch the state. */
-+	data->vbios_boot_state.sclk_bootup_value =
-+			le32_to_cpu(fw_info->ulDefaultEngineClock);
-+	data->vbios_boot_state.mclk_bootup_value =
-+			le32_to_cpu(fw_info->ulDefaultMemoryClock);
-+	data->vbios_boot_state.mvdd_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
-+	data->vbios_boot_state.vddc_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpVDDCVoltage);
-+	data->vbios_boot_state.vddci_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
-+	data->vbios_boot_state.pcie_gen_bootup_value =
-+			phm_get_current_pcie_speed(hwmgr);
-+
-+	data->vbios_boot_state.pcie_lane_bootup_value =
-+			(uint16_t)phm_get_current_pcie_lane_number(hwmgr);
-+
-+	/* set boot power state */
-+	ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
-+	ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
-+	ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
-+	ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
-+		void *state, struct pp_power_state *power_state,
-+		void *pp_table, uint32_t classification_flag)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_power_state  *ellesmere_power_state =
-+			(struct ellesmere_power_state *)(&(power_state->hardware));
-+	struct ellesmere_performance_level *performance_level;
-+	ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
-+	ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
-+			(ATOM_Tonga_POWERPLAYTABLE *)pp_table;
-+	ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-+			(ATOM_Tonga_SCLK_Dependency_Table *)
-+			(((unsigned long)powerplay_table) +
-+				le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
-+	ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
-+			(ATOM_Tonga_MCLK_Dependency_Table *)
-+			(((unsigned long)powerplay_table) +
-+				le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
-+
-+	/* The following fields are not initialized here: id orderedList allStatesList */
-+	power_state->classification.ui_label =
-+			(le16_to_cpu(state_entry->usClassification) &
-+			ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
-+			ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
-+	power_state->classification.flags = classification_flag;
-+	/* NOTE: There is a classification2 flag in BIOS that is not being used right now */
-+
-+	power_state->classification.temporary_state = false;
-+	power_state->classification.to_be_deleted = false;
-+
-+	power_state->validation.disallowOnDC =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
-+					ATOM_Tonga_DISALLOW_ON_DC));
-+
-+	power_state->pcie.lanes = 0;
-+
-+	power_state->display.disableFrameModulation = false;
-+	power_state->display.limitRefreshrate = false;
-+	power_state->display.enableVariBright =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
-+					ATOM_Tonga_ENABLE_VARIBRIGHT));
-+
-+	power_state->validation.supportedPowerLevels = 0;
-+	power_state->uvd_clocks.VCLK = 0;
-+	power_state->uvd_clocks.DCLK = 0;
-+	power_state->temperatures.min = 0;
-+	power_state->temperatures.max = 0;
-+
-+	performance_level = &(ellesmere_power_state->performance_levels
-+			[ellesmere_power_state->performance_level_count++]);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(ellesmere_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
-+			"Performance levels exceeds SMC limit!",
-+			return -1);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(ellesmere_power_state->performance_level_count <=
-+					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
-+			"Performance levels exceeds Driver limit!",
-+			return -1);
-+
-+	/* Performance levels are arranged from low to high. */
-+	performance_level->memory_clock = mclk_dep_table->entries
-+			[state_entry->ucMemoryClockIndexLow].ulMclk;
-+	performance_level->engine_clock = sclk_dep_table->entries
-+			[state_entry->ucEngineClockIndexLow].ulSclk;
-+	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
-+			state_entry->ucPCIEGenLow);
-+	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-+			state_entry->ucPCIELaneHigh);
-+
-+	performance_level = &(ellesmere_power_state->performance_levels
-+			[ellesmere_power_state->performance_level_count++]);
-+	performance_level->memory_clock = mclk_dep_table->entries
-+			[state_entry->ucMemoryClockIndexHigh].ulMclk;
-+	performance_level->engine_clock = sclk_dep_table->entries
-+			[state_entry->ucEngineClockIndexHigh].ulSclk;
-+	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
-+			state_entry->ucPCIEGenHigh);
-+	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-+			state_entry->ucPCIELaneHigh);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr,
-+		unsigned long entry_index, struct pp_power_state *state)
-+{
-+	int result;
-+	struct ellesmere_power_state *ps;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	state->hardware.magic = PHM_VIslands_Magic;
-+
-+	ps = (struct ellesmere_power_state *)(&state->hardware);
-+
-+	result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
-+			ellesmere_get_pp_table_entry_callback_func);
-+
-+	/* This is the earliest time we have all the dependency table and the VBIOS boot state
-+	 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
-+	 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
-+	 */
-+	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
-+		if (dep_mclk_table->entries[0].clk !=
-+				data->vbios_boot_state.mclk_bootup_value)
-+			printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot MCLK level");
-+		if (dep_mclk_table->entries[0].vddci !=
-+				data->vbios_boot_state.vddci_bootup_value)
-+			printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot VDDCI level");
-+	}
-+
-+	/* set DC compatible flag if this state supports DC */
-+	if (!state->validation.disallowOnDC)
-+		ps->dc_compatible = true;
-+
-+	if (state->classification.flags & PP_StateClassificationFlag_ACPI)
-+		data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
-+
-+	ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
-+	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
-+
-+	if (!result) {
-+		uint32_t i;
-+
-+		switch (state->classification.ui_label) {
-+		case PP_StateUILabel_Performance:
-+			data->use_pcie_performance_levels = true;
-+
-+			for (i = 0; i < ps->performance_level_count; i++) {
-+				if (data->pcie_gen_performance.max <
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.max =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_performance.min >
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.min =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_performance.max <
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.max =
-+							ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_performance.min >
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.min =
-+							ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		case PP_StateUILabel_Battery:
-+			data->use_pcie_power_saving_levels = true;
-+
-+			for (i = 0; i < ps->performance_level_count; i++) {
-+				if (data->pcie_gen_power_saving.max <
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.max =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_power_saving.min >
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.min =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_power_saving.max <
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.max =
-+							ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_power_saving.min >
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.min =
-+							ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static void
-+ellesmere_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
-+{
-+	uint32_t sclk, mclk;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+
-+	sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+
-+	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
-+			mclk / 100, sclk / 100);
-+}
-+
-+static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	const struct ellesmere_power_state *ellesmere_ps =
-+			cast_const_phw_ellesmere_power_state(states->pnew_state);
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
-+	uint32_t sclk = ellesmere_ps->performance_levels
-+			[ellesmere_ps->performance_level_count - 1].engine_clock;
-+	struct ellesmere_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
-+	uint32_t mclk = ellesmere_ps->performance_levels
-+			[ellesmere_ps->performance_level_count - 1].memory_clock;
-+	struct PP_Clocks min_clocks = {0};
-+	uint32_t i;
-+	struct cgs_display_info info = {0};
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	for (i = 0; i < sclk_table->count; i++) {
-+		if (sclk == sclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= sclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-+	else {
-+	/* TODO: Check SCLK in DAL's minimum clocks
-+	 * in case DeepSleep divider update is required.
-+	 */
-+		if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
-+			data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
-+	}
-+
-+	for (i = 0; i < mclk_table->count; i++) {
-+		if (mclk == mclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= mclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
-+
-+	return 0;
-+}
-+
-+static uint16_t ellesmere_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
-+		const struct ellesmere_power_state *ellesmere_ps)
-+{
-+	uint32_t i;
-+	uint32_t sclk, max_sclk = 0;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
-+
-+	for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
-+		sclk = ellesmere_ps->performance_levels[i].engine_clock;
-+		if (max_sclk < sclk)
-+			max_sclk = sclk;
-+	}
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
-+			return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
-+					dpm_table->pcie_speed_table.dpm_levels
-+					[dpm_table->pcie_speed_table.count - 1].value :
-+					dpm_table->pcie_speed_table.dpm_levels[i].value);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_request_link_speed_change_before_state_change(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	const struct ellesmere_power_state *ellesmere_nps =
-+			cast_const_phw_ellesmere_power_state(states->pnew_state);
-+	const struct ellesmere_power_state *ellesmere_cps =
-+			cast_const_phw_ellesmere_power_state(states->pcurrent_state);
-+
-+	uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_nps);
-+	uint16_t current_link_speed;
-+
-+	if (data->force_pcie_gen == PP_PCIEGenInvalid)
-+		current_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_cps);
-+	else
-+		current_link_speed = data->force_pcie_gen;
-+
-+	data->force_pcie_gen = PP_PCIEGenInvalid;
-+	data->pspp_notify_required = false;
-+
-+	if (target_link_speed > current_link_speed) {
-+		switch (target_link_speed) {
-+		case PP_PCIEGen3:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
-+				break;
-+			data->force_pcie_gen = PP_PCIEGen2;
-+			if (current_link_speed == PP_PCIEGen2)
-+				break;
-+		case PP_PCIEGen2:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
-+				break;
-+		default:
-+			data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
-+			break;
-+		}
-+	} else {
-+		if (target_link_speed < current_link_speed)
-+			data->pspp_notify_required = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
-+				"Trying to freeze SCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_FreezeLevel),
-+				"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
-+				return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		 DPMTABLE_OD_UPDATE_MCLK)) {
-+		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
-+				"Trying to freeze MCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_MCLKDPM_FreezeLevel),
-+				"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
-+				return -1);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result = 0;
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	const struct ellesmere_power_state *ellesmere_ps =
-+			cast_const_phw_ellesmere_power_state(states->pnew_state);
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t sclk = ellesmere_ps->performance_levels
-+			[ellesmere_ps->performance_level_count - 1].engine_clock;
-+	uint32_t mclk = ellesmere_ps->performance_levels
-+			[ellesmere_ps->performance_level_count - 1].memory_clock;
-+	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
-+
-+	struct ellesmere_dpm_table *golden_dpm_table = &data->golden_dpm_table;
-+	uint32_t dpm_count, clock_percent;
-+	uint32_t i;
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
-+		dpm_table->sclk_table.dpm_levels
-+		[dpm_table->sclk_table.count - 1].value = sclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-+		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+		/* Need to do calculation based on the golden DPM table
-+		 * as the Heatmap GPU Clock axis is also based on the default values
-+		 */
-+			PP_ASSERT_WITH_CODE(
-+				(golden_dpm_table->sclk_table.dpm_levels
-+						[golden_dpm_table->sclk_table.count - 1].value != 0),
-+				"Divide by 0!",
-+				return -1);
-+			dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
-+
-+			for (i = dpm_count; i > 1; i--) {
-+				if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
-+					clock_percent =
-+					      ((sclk
-+						- golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
-+						) * 100)
-+						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-+
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value +
-+							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-+								clock_percent)/100;
-+
-+				} else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
-+					clock_percent =
-+						((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
-+						- sclk) * 100)
-+						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-+
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value -
-+							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+				} else
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
-+		dpm_table->mclk_table.dpm_levels
-+			[dpm_table->mclk_table.count - 1].value = mclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-+		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+
-+			PP_ASSERT_WITH_CODE(
-+					(golden_dpm_table->mclk_table.dpm_levels
-+						[golden_dpm_table->mclk_table.count-1].value != 0),
-+					"Divide by 0!",
-+					return -1);
-+			dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
-+			for (i = dpm_count; i > 1; i--) {
-+				if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
-+					clock_percent = ((mclk -
-+					golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
-+					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-+
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value +
-+							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-+							clock_percent) / 100;
-+
-+				} else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
-+					clock_percent = (
-+					 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
-+					* 100)
-+					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-+
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value -
-+							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+				} else
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
-+		result = ellesmere_populate_all_graphic_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
-+		/*populate MCLK dpm table to SMU7 */
-+		result = ellesmere_populate_all_memory_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	return result;
-+}
-+
-+static int ellesmere_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
-+			  struct ellesmere_single_dpm_table *dpm_table,
-+			uint32_t low_limit, uint32_t high_limit)
-+{
-+	uint32_t i;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	for (i = 0; i < dpm_table->count; i++) {
-+		if ((dpm_table->dpm_levels[i].value < low_limit)
-+		|| (dpm_table->dpm_levels[i].value > high_limit))
-+			dpm_table->dpm_levels[i].enabled = false;
-+		else if (((1 << i) & data->disable_dpm_mask) == 0)
-+			dpm_table->dpm_levels[i].enabled = false;
-+		else
-+			dpm_table->dpm_levels[i].enabled = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_trim_dpm_states(struct pp_hwmgr *hwmgr,
-+		const struct ellesmere_power_state *ellesmere_ps)
-+{
-+	int result = 0;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t high_limit_count;
-+
-+	PP_ASSERT_WITH_CODE((ellesmere_ps->performance_level_count >= 1),
-+			"power state did not have any performance level",
-+			return -1);
-+
-+	high_limit_count = (1 == ellesmere_ps->performance_level_count) ? 0 : 1;
-+
-+	ellesmere_trim_single_dpm_states(hwmgr,
-+			&(data->dpm_table.sclk_table),
-+			ellesmere_ps->performance_levels[0].engine_clock,
-+			ellesmere_ps->performance_levels[high_limit_count].engine_clock);
-+
-+	ellesmere_trim_single_dpm_states(hwmgr,
-+			&(data->dpm_table.mclk_table),
-+			ellesmere_ps->performance_levels[0].memory_clock,
-+			ellesmere_ps->performance_levels[high_limit_count].memory_clock);
-+
-+	return result;
-+}
-+
-+static int ellesmere_generate_dpm_level_enable_mask(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result;
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	const struct ellesmere_power_state *ellesmere_ps =
-+			cast_const_phw_ellesmere_power_state(states->pnew_state);
-+
-+	result = ellesmere_trim_dpm_states(hwmgr, ellesmere_ps);
-+	if (result)
-+		return result;
-+
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+			PPSMC_MSG_VCEDPM_Enable :
-+			PPSMC_MSG_VCEDPM_Disable);
-+}
-+
-+static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	const struct ellesmere_power_state *ellesmere_nps =
-+			cast_const_phw_ellesmere_power_state(states->pnew_state);
-+	const struct ellesmere_power_state *ellesmere_cps =
-+			cast_const_phw_ellesmere_power_state(states->pcurrent_state);
-+
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (ellesmere_nps->vce_clks.evclk > 0 &&
-+	(ellesmere_cps == NULL || ellesmere_cps->vce_clks.evclk == 0)) {
-+
-+		data->smc_state_table.VceBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFF00FFFF;
-+		mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VCEDPM_SetEnabledMask,
-+					(uint32_t)1 << data->smc_state_table.VceBootLevel);
-+
-+			ellesmere_enable_disable_vce_dpm(hwmgr, true);
-+		} else if (ellesmere_nps->vce_clks.evclk == 0 &&
-+				ellesmere_cps != NULL &&
-+				ellesmere_cps->vce_clks.evclk > 0)
-+			ellesmere_enable_disable_vce_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = ellesmere_copy_bytes_to_smc(
-+				hwmgr->smumgr,
-+				data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				data->sram_end);
-+	}
-+
-+	return result;
-+}
-+
-+static int ellesmere_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return ellesmere_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+
-+		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze SCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+			"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
-+			return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
-+
-+		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze MCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+		    "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
-+		    return -1);
-+	}
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_notify_link_speed_change_after_state_change(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	const struct ellesmere_power_state *ellesmere_ps =
-+			cast_const_phw_ellesmere_power_state(states->pnew_state);
-+	uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_ps);
-+	uint8_t  request;
-+
-+	if (data->pspp_notify_required) {
-+		if (target_link_speed == PP_PCIEGen3)
-+			request = PCIE_PERF_REQ_GEN3;
-+		else if (target_link_speed == PP_PCIEGen2)
-+			request = PCIE_PERF_REQ_GEN2;
-+		else
-+			request = PCIE_PERF_REQ_GEN1;
-+
-+		if (request == PCIE_PERF_REQ_GEN1 &&
-+				phm_get_current_pcie_speed(hwmgr) > 0)
-+			return 0;
-+
-+		if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
-+			if (PP_PCIEGen2 == target_link_speed)
-+				printk("PSPP request to switch to Gen2 from Gen3 Failed!");
-+			else
-+				printk("PSPP request to switch to Gen1 from Gen2 Failed!");
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int tmp_result, result = 0;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	tmp_result = ellesmere_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to find DPM states clocks in DPM table!",
-+			result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result =
-+			ellesmere_request_link_speed_change_before_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to request link speed change before state change!",
-+				result = tmp_result);
-+	}
-+
-+	tmp_result = ellesmere_freeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to freeze SCLK MCLK DPM!", result = tmp_result);
-+
-+	tmp_result = ellesmere_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to populate and upload SCLK MCLK DPM levels!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_generate_dpm_level_enable_mask(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to generate DPM level enabled mask!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_update_vce_dpm(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to update VCE DPM!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_update_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to update SCLK threshold!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program memory timing parameters!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_unfreeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to unfreeze SCLK MCLK DPM!",
-+			result = tmp_result);
-+
-+	tmp_result = ellesmere_upload_dpm_level_enable_mask(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to upload DPM level enabled mask!",
-+			result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result =
-+			ellesmere_notify_link_speed_change_after_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to notify link speed change after state change!",
-+				result = tmp_result);
-+	}
-+	data->apply_optimized_settings = false;
-+	return result;
-+}
-+
-+static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
-+{
-+
-+		return 0;
-+}
-+
-+int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
-+{
-+	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
-+
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
-+}
-+
-+int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t num_active_displays = 0;
-+	struct cgs_display_info info = {0};
-+	info.mode_info = NULL;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	num_active_displays = info.display_count;
-+
-+	if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
-+		ellesmere_notify_smc_display_change(hwmgr, false);
-+	else
-+		ellesmere_notify_smc_display_change(hwmgr, true);
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs the display gap
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always OK
-+*/
-+int ellesmere_program_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t num_active_displays = 0;
-+	uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
-+	uint32_t display_gap2;
-+	uint32_t pre_vbi_time_in_us;
-+	uint32_t frame_time_in_us;
-+	uint32_t ref_clock;
-+	uint32_t refresh_rate = 0;
-+	struct cgs_display_info info = {0};
-+	struct cgs_mode_info mode_info;
-+
-+	info.mode_info = &mode_info;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	num_active_displays = info.display_count;
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	ref_clock = mode_info.ref_clock;
-+	refresh_rate = mode_info.refresh_rate;
-+
-+	if (0 == refresh_rate)
-+		refresh_rate = 60;
-+
-+	frame_time_in_us = 1000000 / refresh_rate;
-+
-+	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
-+	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
-+
-+	if (num_active_displays == 1)
-+		ellesmere_notify_smc_display_change(hwmgr, true);
-+
-+	return 0;
-+}
-+
-+
-+int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
-+{
-+	return ellesmere_program_display_gap(hwmgr);
-+}
-+
-+/**
-+*  Set maximum target operating fan output RPM
-+*
-+* @param    hwmgr:  the address of the powerplay hardware manager.
-+* @param    usMaxFanRpm:  max operating fan RPM value.
-+* @return   The response that came from the SMC.
-+*/
-+static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
-+{
-+	return 0;
-+}
-+
-+int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
-+					const void *thermal_interrupt_info)
-+{
-+	return 0;
-+}
-+
-+bool ellesmere_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	bool is_update_required = false;
-+	struct cgs_display_info info = {0, 0, NULL};
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		is_update_required = true;
-+/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
-+	if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+		cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
-+		if (min_clocks.engineClockInSR != data->display_timing.minClockInSR)
-+			is_update_required = true;
-+*/
-+	return is_update_required;
-+}
-+
-+static inline bool ellesmere_are_power_levels_equal(const struct ellesmere_performance_level *pl1,
-+							   const struct ellesmere_performance_level *pl2)
-+{
-+	return ((pl1->memory_clock == pl2->memory_clock) &&
-+		  (pl1->engine_clock == pl2->engine_clock) &&
-+		  (pl1->pcie_gen == pl2->pcie_gen) &&
-+		  (pl1->pcie_lane == pl2->pcie_lane));
-+}
-+
-+int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
-+{
-+	const struct ellesmere_power_state *psa = cast_const_phw_ellesmere_power_state(pstate1);
-+	const struct ellesmere_power_state *psb = cast_const_phw_ellesmere_power_state(pstate2);
-+	int i;
-+
-+	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
-+		return -EINVAL;
-+
-+	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
-+	if (psa->performance_level_count != psb->performance_level_count) {
-+		*equal = false;
-+		return 0;
-+	}
-+
-+	for (i = 0; i < psa->performance_level_count; i++) {
-+		if (!ellesmere_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
-+			/* If we have found even one performance level pair that is different the states are different. */
-+			*equal = false;
-+			return 0;
-+		}
-+	}
-+
-+	/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
-+	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
-+	*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
-+	*equal &= (psa->sclk_threshold == psb->sclk_threshold);
-+
-+	return 0;
-+}
-+
-+int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t vbios_version;
-+
-+	/*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
-+
-+	phm_get_mc_microcode_version(hwmgr);
-+	vbios_version = hwmgr->microcode_version_info.MC & 0xf;
-+	/*  Full version of MC ucode has already been loaded. */
-+	if (vbios_version == 0) {
-+		data->need_long_memory_training = false;
-+		return 0;
-+	}
-+
-+	data->need_long_memory_training = true;
-+
-+/*
-+ * 	PPMCME_FirmwareDescriptorEntry *pfd = NULL;
-+	pfd = &tonga_mcmeFirmware;
-+	if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
-+		ellesmere_load_mc_microcode(hwmgr, pfd->dpmThreshold,
-+					pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
-+					pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
-+*/
-+	return 0;
-+}
-+
-+/**
-+ * Read clock related registers.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int ellesmere_read_clock_registers(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
-+						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
-+						& CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
-+						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
-+						& CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
-+						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
-+						& CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Find out if memory is GDDR5.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int ellesmere_get_memory_type(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t temp;
-+
-+	temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
-+
-+	data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
-+			((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
-+			 MC_SEQ_MISC0_GDDR5_SHIFT));
-+
-+	return 0;
-+}
-+
-+/**
-+ * Enables Dynamic Power Management by SMC
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int ellesmere_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			GENERAL_PWRMGT, STATIC_PM_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initialize PowerGating States for different engines
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int ellesmere_init_power_gate_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+	data->samu_power_gated = false;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_init_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	data->low_sclk_interrupt_threshold = 0;
-+
-+	return 0;
-+}
-+
-+int ellesmere_setup_asic_task(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	ellesmere_upload_mc_firmware(hwmgr);
-+
-+	tmp_result = ellesmere_read_clock_registers(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to read clock registers!", result = tmp_result);
-+
-+	tmp_result = ellesmere_get_memory_type(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to get memory type!", result = tmp_result);
-+
-+	tmp_result = ellesmere_enable_acpi_power_management(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable ACPI power management!", result = tmp_result);
-+
-+	tmp_result = ellesmere_init_power_gate_state(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to init power gate state!", result = tmp_result);
-+
-+	tmp_result = phm_get_mc_microcode_version(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to get MC microcode version!", result = tmp_result);
-+
-+	tmp_result = ellesmere_init_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to init sclk threshold!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
-+	.backend_init = &ellesmere_hwmgr_backend_init,
-+	.backend_fini = &ellesmere_hwmgr_backend_fini,
-+	.asic_setup = &ellesmere_setup_asic_task,
-+	.dynamic_state_management_enable = &ellesmere_enable_dpm_tasks,
-+	.apply_state_adjust_rules = ellesmere_apply_state_adjust_rules,
-+	.force_dpm_level = &ellesmere_force_dpm_level,
-+	.power_state_set = ellesmere_set_power_state_tasks,
-+	.get_power_state_size = ellesmere_get_power_state_size,
-+	.get_mclk = ellesmere_dpm_get_mclk,
-+	.get_sclk = ellesmere_dpm_get_sclk,
-+	.patch_boot_state = ellesmere_dpm_patch_boot_state,
-+	.get_pp_table_entry = ellesmere_get_pp_table_entry,
-+	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
-+	.print_current_perforce_level = ellesmere_print_current_perforce_level,
-+	.powerdown_uvd = NULL,
-+	.powergate_uvd = NULL,
-+	.powergate_vce = NULL,
-+	.disable_clock_power_gating = NULL,
-+	.notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment,
-+	.display_config_changed = ellesmere_display_configuration_changed_task,
-+	.set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
-+	.set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output,
-+	.get_temperature = NULL,
-+	.stop_thermal_controller = NULL,
-+	.get_fan_speed_info = NULL,
-+	.get_fan_speed_percent = NULL,
-+	.set_fan_speed_percent = NULL,
-+	.reset_fan_speed_to_default = NULL,
-+	.get_fan_speed_rpm = NULL,
-+	.set_fan_speed_rpm = NULL,
-+	.uninitialize_thermal_controller = NULL,
-+	.register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt,
-+	.check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration,
-+	.check_states_equal = ellesmere_check_states_equal,
-+};
-+
-+int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr  *data;
-+
-+	data = kzalloc (sizeof(struct ellesmere_hwmgr), GFP_KERNEL);
-+	if (data == NULL)
-+		return -ENOMEM;
-+
-+	hwmgr->backend = data;
-+	hwmgr->hwmgr_func = &ellesmere_hwmgr_funcs;
-+	hwmgr->pptable_func = &tonga_pptable_funcs;
-+
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-new file mode 100644
-index 0000000..4d57698
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-@@ -0,0 +1,349 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef ELLESMERE_HWMGR_H
-+#define ELLESMERE_HWMGR_H
-+
-+#include "hwmgr.h"
-+#include "smu74.h"
-+#include "smu74_discrete.h"
-+#include "ppatomctrl.h"
-+#include "ellesmere_ppsmc.h"
-+#include "ellesmere_powertune.h"
-+
-+#define ELLESMERE_MAX_HARDWARE_POWERLEVELS	2
-+
-+#define ELLESMERE_VOLTAGE_CONTROL_NONE                   0x0
-+#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO                0x1
-+#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2               0x2
-+#define ELLESMERE_VOLTAGE_CONTROL_MERGED                 0x3
-+
-+#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-+#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
-+#define DPMTABLE_UPDATE_SCLK        0x00000004
-+#define DPMTABLE_UPDATE_MCLK        0x00000008
-+
-+struct ellesmere_performance_level {
-+	uint32_t  memory_clock;
-+	uint32_t  engine_clock;
-+	uint16_t  pcie_gen;
-+	uint16_t  pcie_lane;
-+};
-+
-+struct ellesmere_uvd_clocks {
-+	uint32_t  vclk;
-+	uint32_t  dclk;
-+};
-+
-+struct ellesmere_vce_clocks {
-+	uint32_t  evclk;
-+	uint32_t  ecclk;
-+};
-+
-+struct ellesmere_power_state {
-+	uint32_t                  magic;
-+	struct ellesmere_uvd_clocks    uvd_clks;
-+	struct ellesmere_vce_clocks    vce_clks;
-+	uint32_t                  sam_clk;
-+	uint16_t                  performance_level_count;
-+	bool                      dc_compatible;
-+	uint32_t                  sclk_threshold;
-+	struct ellesmere_performance_level  performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS];
-+};
-+
-+struct ellesmere_dpm_level {
-+	bool	enabled;
-+	uint32_t	value;
-+	uint32_t	param1;
-+};
-+
-+#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5
-+#define MAX_REGULAR_DPM_NUMBER 8
-+#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500
-+
-+struct ellesmere_single_dpm_table {
-+	uint32_t		count;
-+	struct ellesmere_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
-+};
-+
-+struct ellesmere_dpm_table {
-+	struct ellesmere_single_dpm_table  sclk_table;
-+	struct ellesmere_single_dpm_table  mclk_table;
-+	struct ellesmere_single_dpm_table  pcie_speed_table;
-+	struct ellesmere_single_dpm_table  vddc_table;
-+	struct ellesmere_single_dpm_table  vddci_table;
-+	struct ellesmere_single_dpm_table  mvdd_table;
-+};
-+
-+struct ellesmere_clock_registers {
-+	uint32_t  vCG_SPLL_FUNC_CNTL;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t  vDLL_CNTL;
-+	uint32_t  vMCLK_PWRMGT_CNTL;
-+	uint32_t  vMPLL_AD_FUNC_CNTL;
-+	uint32_t  vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL_1;
-+	uint32_t  vMPLL_FUNC_CNTL_2;
-+	uint32_t  vMPLL_SS1;
-+	uint32_t  vMPLL_SS2;
-+};
-+
-+#define DISABLE_MC_LOADMICROCODE   1
-+#define DISABLE_MC_CFGPROGRAMMING  2
-+
-+struct ellesmere_voltage_smio_registers {
-+	uint32_t vS0_VID_LOWER_SMIO_CNTL;
-+};
-+
-+#define ELLESMERE_MAX_LEAKAGE_COUNT  8
-+
-+struct ellesmere_leakage_voltage {
-+	uint16_t  count;
-+	uint16_t  leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT];
-+	uint16_t  actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT];
-+};
-+
-+struct ellesmere_vbios_boot_state {
-+	uint16_t    mvdd_bootup_value;
-+	uint16_t    vddc_bootup_value;
-+	uint16_t    vddci_bootup_value;
-+	uint32_t    sclk_bootup_value;
-+	uint32_t    mclk_bootup_value;
-+	uint16_t    pcie_gen_bootup_value;
-+	uint16_t    pcie_lane_bootup_value;
-+};
-+
-+/* Ultra Low Voltage parameter structure */
-+struct ellesmere_ulv_parm {
-+	bool                           ulv_supported;
-+	uint32_t                       cg_ulv_parameter;
-+	uint32_t                       ulv_volt_change_delay;
-+	struct ellesmere_performance_level  ulv_power_level;
-+};
-+
-+struct ellesmere_display_timing {
-+	uint32_t  min_clock_in_sr;
-+	uint32_t  num_existing_displays;
-+};
-+
-+struct ellesmere_dpmlevel_enable_mask {
-+	uint32_t  uvd_dpm_enable_mask;
-+	uint32_t  vce_dpm_enable_mask;
-+	uint32_t  acp_dpm_enable_mask;
-+	uint32_t  samu_dpm_enable_mask;
-+	uint32_t  sclk_dpm_enable_mask;
-+	uint32_t  mclk_dpm_enable_mask;
-+	uint32_t  pcie_dpm_enable_mask;
-+};
-+
-+struct ellesmere_pcie_perf_range {
-+	uint16_t  max;
-+	uint16_t  min;
-+};
-+struct ellesmere_range_table {
-+	uint32_t trans_lower_frequency; /* in 10khz */
-+	uint32_t trans_upper_frequency;
-+};
-+
-+struct ellesmere_hwmgr {
-+	struct ellesmere_dpm_table			dpm_table;
-+	struct ellesmere_dpm_table			golden_dpm_table;
-+	SMU74_Discrete_DpmTable				smc_state_table;
-+	struct SMU74_Discrete_Ulv            ulv_setting;
-+
-+	struct ellesmere_range_table                range_table[NUM_SCLK_RANGE];
-+	uint32_t						voting_rights_clients0;
-+	uint32_t						voting_rights_clients1;
-+	uint32_t						voting_rights_clients2;
-+	uint32_t						voting_rights_clients3;
-+	uint32_t						voting_rights_clients4;
-+	uint32_t						voting_rights_clients5;
-+	uint32_t						voting_rights_clients6;
-+	uint32_t						voting_rights_clients7;
-+	uint32_t						static_screen_threshold_unit;
-+	uint32_t						static_screen_threshold;
-+	uint32_t						voltage_control;
-+	uint32_t						vddc_vddci_delta;
-+
-+	uint32_t						active_auto_throttle_sources;
-+
-+	struct ellesmere_clock_registers            clock_registers;
-+	struct ellesmere_voltage_smio_registers      voltage_smio_registers;
-+
-+	bool                           is_memory_gddr5;
-+	uint16_t                       acpi_vddc;
-+	bool                           pspp_notify_required;
-+	uint16_t                       force_pcie_gen;
-+	uint16_t                       acpi_pcie_gen;
-+	uint32_t                       pcie_gen_cap;
-+	uint32_t                       pcie_lane_cap;
-+	uint32_t                       pcie_spc_cap;
-+	struct ellesmere_leakage_voltage          vddc_leakage;
-+	struct ellesmere_leakage_voltage          Vddci_leakage;
-+
-+	uint32_t                             mvdd_control;
-+	uint32_t                             vddc_mask_low;
-+	uint32_t                             mvdd_mask_low;
-+	uint16_t                            max_vddc_in_pptable;
-+	uint16_t                            min_vddc_in_pptable;
-+	uint16_t                            max_vddci_in_pptable;
-+	uint16_t                            min_vddci_in_pptable;
-+	uint32_t                             mclk_strobe_mode_threshold;
-+	uint32_t                             mclk_stutter_mode_threshold;
-+	uint32_t                             mclk_edc_enable_threshold;
-+	uint32_t                             mclk_edcwr_enable_threshold;
-+	bool                                is_uvd_enabled;
-+	struct ellesmere_vbios_boot_state        vbios_boot_state;
-+
-+	bool                           pcie_performance_request;
-+	bool                           battery_state;
-+	bool                           is_tlu_enabled;
-+
-+	/* ---- SMC SRAM Address of firmware header tables ---- */
-+	uint32_t                             sram_end;
-+	uint32_t                             dpm_table_start;
-+	uint32_t                             soft_regs_start;
-+	uint32_t                             mc_reg_table_start;
-+	uint32_t                             fan_table_start;
-+	uint32_t                             arb_table_start;
-+
-+	/* ---- Stuff originally coming from Evergreen ---- */
-+	uint32_t                             vddci_control;
-+	struct pp_atomctrl_voltage_table     vddc_voltage_table;
-+	struct pp_atomctrl_voltage_table     vddci_voltage_table;
-+	struct pp_atomctrl_voltage_table     mvdd_voltage_table;
-+
-+	uint32_t                             mgcg_cgtt_local2;
-+	uint32_t                             mgcg_cgtt_local3;
-+	uint32_t                             gpio_debug;
-+	uint32_t                             mc_micro_code_feature;
-+	uint32_t                             highest_mclk;
-+	uint16_t                             acpi_vddci;
-+	uint8_t                              mvdd_high_index;
-+	uint8_t                              mvdd_low_index;
-+	bool                                 dll_default_on;
-+	bool                                 performance_request_registered;
-+
-+	/* ---- Low Power Features ---- */
-+	struct ellesmere_ulv_parm                 ulv;
-+
-+	/* ---- CAC Stuff ---- */
-+	uint32_t                       cac_table_start;
-+	bool                           cac_configuration_required;
-+	bool                           driver_calculate_cac_leakage;
-+	bool                           cac_enabled;
-+
-+	/* ---- DPM2 Parameters ---- */
-+	uint32_t                       power_containment_features;
-+	bool                           enable_dte_feature;
-+	bool                           enable_tdc_limit_feature;
-+	bool                           enable_pkg_pwr_tracking_feature;
-+	bool                           disable_uvd_power_tune_feature;
-+	struct ellesmere_pt_defaults       *power_tune_defaults;
-+	struct SMU74_Discrete_PmFuses  power_tune_table;
-+	uint32_t                       dte_tj_offset;
-+	uint32_t                       fast_watermark_threshold;
-+
-+	/* ---- Phase Shedding ---- */
-+	bool                           vddc_phase_shed_control;
-+
-+	/* ---- DI/DT ---- */
-+	struct ellesmere_display_timing        display_timing;
-+
-+	/* ---- Thermal Temperature Setting ---- */
-+	struct ellesmere_dpmlevel_enable_mask     dpm_level_enable_mask;
-+	uint32_t                                  need_update_smu7_dpm_table;
-+	uint32_t                                  sclk_dpm_key_disabled;
-+	uint32_t                                  mclk_dpm_key_disabled;
-+	uint32_t                                  pcie_dpm_key_disabled;
-+	uint32_t                                  min_engine_clocks;
-+	struct ellesmere_pcie_perf_range          pcie_gen_performance;
-+	struct ellesmere_pcie_perf_range          pcie_lane_performance;
-+	struct ellesmere_pcie_perf_range          pcie_gen_power_saving;
-+	struct ellesmere_pcie_perf_range          pcie_lane_power_saving;
-+	bool                                      use_pcie_performance_levels;
-+	bool                                      use_pcie_power_saving_levels;
-+	uint32_t                                  activity_target[SMU74_MAX_LEVELS_GRAPHICS];
-+	uint32_t                                  mclk_activity_target;
-+	uint32_t                                  mclk_dpm0_activity_target;
-+	uint32_t                                  low_sclk_interrupt_threshold;
-+	uint32_t                                  last_mclk_dpm_enable_mask;
-+	bool                                      uvd_enabled;
-+
-+	/* ---- Power Gating States ---- */
-+	bool                           uvd_power_gated;
-+	bool                           vce_power_gated;
-+	bool                           samu_power_gated;
-+	bool                           need_long_memory_training;
-+
-+	/* Application power optimization parameters */
-+	bool                               update_up_hyst;
-+	bool                               update_down_hyst;
-+	uint32_t                           down_hyst;
-+	uint32_t                           up_hyst;
-+	uint32_t disable_dpm_mask;
-+	bool apply_optimized_settings;
-+};
-+
-+/* To convert to Q8.8 format for firmware */
-+#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT             256
-+
-+enum Ellesmere_I2CLineID {
-+	Ellesmere_I2CLineID_DDC1 = 0x90,
-+	Ellesmere_I2CLineID_DDC2 = 0x91,
-+	Ellesmere_I2CLineID_DDC3 = 0x92,
-+	Ellesmere_I2CLineID_DDC4 = 0x93,
-+	Ellesmere_I2CLineID_DDC5 = 0x94,
-+	Ellesmere_I2CLineID_DDC6 = 0x95,
-+	Ellesmere_I2CLineID_SCLSDA = 0x96,
-+	Ellesmere_I2CLineID_DDCVGA = 0x97
-+};
-+
-+#define ELLESMERE_I2C_DDC1DATA          0
-+#define ELLESMERE_I2C_DDC1CLK           1
-+#define ELLESMERE_I2C_DDC2DATA          2
-+#define ELLESMERE_I2C_DDC2CLK           3
-+#define ELLESMERE_I2C_DDC3DATA          4
-+#define ELLESMERE_I2C_DDC3CLK           5
-+#define ELLESMERE_I2C_SDA               40
-+#define ELLESMERE_I2C_SCL               41
-+#define ELLESMERE_I2C_DDC4DATA          65
-+#define ELLESMERE_I2C_DDC4CLK           66
-+#define ELLESMERE_I2C_DDC5DATA          0x48
-+#define ELLESMERE_I2C_DDC5CLK           0x49
-+#define ELLESMERE_I2C_DDC6DATA          0x4a
-+#define ELLESMERE_I2C_DDC6CLK           0x4b
-+#define ELLESMERE_I2C_DDCVGADATA        0x4c
-+#define ELLESMERE_I2C_DDCVGACLK         0x4d
-+
-+#define ELLESMERE_UNUSED_GPIO_PIN       0x7F
-+
-+int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
-new file mode 100644
-index 0000000..ff41c41
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
-@@ -0,0 +1,396 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "hwmgr.h"
-+#include "smumgr.h"
-+#include "ellesmere_hwmgr.h"
-+#include "ellesmere_powertune.h"
-+#include "ellesmere_smumgr.h"
-+#include "smu74_discrete.h"
-+#include "pp_debug.h"
-+
-+#define VOLTAGE_SCALE  4
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+
-+struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
-+	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
-+	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-+	{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
-+	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
-+};
-+
-+void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *ellesmere_hwmgr = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct  phm_ppt_v1_information *table_info =
-+			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (table_info &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID)
-+		ellesmere_hwmgr->power_tune_defaults =
-+				&ellesmere_power_tune_data_set_array
-+				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
-+	else
-+		ellesmere_hwmgr->power_tune_defaults = &ellesmere_power_tune_data_set_array[0];
-+
-+}
-+
-+int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
-+	SMU74_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	int i, j, k;
-+	uint16_t *pdef1;
-+	uint16_t *pdef2;
-+
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-+	dpm_table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-+
-+	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
-+				"Target Operating Temp is out of Range!",
-+				);
-+/*  This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */
-+	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
-+
-+/*  HW request to hard code this value to 8 which is 0.5C */
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
-+	dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset);
-+	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT);
-+	pdef1 = defaults->BAPMTI_R;
-+	pdef2 = defaults->BAPMTI_RC;
-+
-+	for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
-+		for (j = 0; j < SMU74_DTE_SOURCES; j++) {
-+			for (k = 0; k < SMU74_DTE_SINKS; k++) {
-+				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
-+				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
-+				pdef1++;
-+				pdef2++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
-+
-+	data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
-+	data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-+	data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct  ellesmere_pt_defaults *defaults = data->power_tune_defaults;
-+
-+	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
-+	data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
-+	data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+			fuse_table_offset +
-+			offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, data->sram_end))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else {
-+		data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
-+		data->power_tune_table.LPMLTemperatureMin =
-+				(uint8_t)((temp >> 16) & 0xff);
-+		data->power_tune_table.LPMLTemperatureMax =
-+				(uint8_t)((temp >> 8) & 0xff);
-+		data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
-+	}
-+	return 0;
-+}
-+
-+static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
-+		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
-+			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
-+				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
-+	return 0;
-+}
-+
-+static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-+{
-+	return 0;
-+}
-+
-+static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+
-+	hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
-+	data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
-+
-+	return 0;
-+}
-+
-+int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t pm_fuse_table_offset;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU74_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, data->sram_end))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to get pm_fuse_table_offset Failed!",
-+					return -EINVAL);
-+
-+		if (ellesmere_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate SviLoadLine Failed!",
-+					return -EINVAL);
-+
-+		if (ellesmere_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed!", return -EINVAL);
-+
-+		if (ellesmere_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TdcWaterfallCtl, "
-+					"LPMLTemperature Min and Max Failed!",
-+					return -EINVAL);
-+
-+		if (0 != ellesmere_populate_temperature_scaler(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate LPMLTemperatureScaler Failed!",
-+					return -EINVAL);
-+
-+		if (ellesmere_populate_fuzzy_fan(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate Fuzzy Fan Control parameters Failed!",
-+					return -EINVAL);
-+
-+		if (ellesmere_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Failed!",
-+					return -EINVAL);
-+
-+		if (ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Min and Max Vid Failed!",
-+					return -EINVAL);
-+
-+		if (ellesmere_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
-+					"Sidd Failed!", return -EINVAL);
-+
-+		if (ellesmere_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
-+				(uint8_t *)&data->power_tune_table,
-+				sizeof(struct SMU74_Discrete_PmFuses), data->sram_end))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed!",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	int result = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_CAC)) {
-+		int smc_result;
-+		smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+				(uint16_t)(PPSMC_MSG_EnableCac));
-+		PP_ASSERT_WITH_CODE((0 == smc_result),
-+				"Failed to enable CAC in SMC.", result = -1);
-+
-+		data->cac_enabled = (0 == smc_result) ? true : false;
-+	}
-+	return result;
-+}
-+
-+int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (data->power_containment_features &
-+			POWERCONTAINMENT_FEATURE_PkgPwrLimit)
-+		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_PkgPwrSetLimit, n);
-+	return 0;
-+}
-+
-+static int ellesmere_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
-+{
-+	return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
-+			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
-+}
-+
-+int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int smc_result;
-+	int result = 0;
-+
-+	data->power_containment_features = 0;
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (data->enable_dte_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_EnableDTE));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable DTE in SMC.", result = -1;);
-+			if (0 == smc_result)
-+				data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
-+		}
-+
-+		if (data->enable_tdc_limit_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_TDCLimitEnable));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable TDCLimit in SMC.", result = -1;);
-+			if (0 == smc_result)
-+				data->power_containment_features |=
-+						POWERCONTAINMENT_FEATURE_TDCLimit;
-+		}
-+
-+		if (data->enable_pkg_pwr_tracking_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable PkgPwrTracking in SMC.", result = -1;);
-+			if (0 == smc_result) {
-+				struct phm_cac_tdp_table *cac_table =
-+						table_info->cac_dtp_table;
-+				uint32_t default_limit =
-+					(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
-+
-+				data->power_containment_features |=
-+						POWERCONTAINMENT_FEATURE_PkgPwrLimit;
-+
-+				if (ellesmere_set_power_limit(hwmgr, default_limit))
-+					printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
-+			}
-+		}
-+	}
-+	return result;
-+}
-+
-+int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+	int adjust_percent, target_tdp;
-+	int result = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		/* adjustment percentage has already been validated */
-+		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
-+				hwmgr->platform_descriptor.TDPAdjustment :
-+				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
-+		/* SMC requested that target_tdp to be 7 bit fraction in DPM table
-+		 * but message to be 8 bit fraction for messages
-+		 */
-+		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
-+		result = ellesmere_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
-+	}
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h
-new file mode 100644
-index 0000000..5772bf9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h
-@@ -0,0 +1,70 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef ELLESMERE_POWERTUNE_H
-+#define ELLESMERE_POWERTUNE_H
-+
-+enum ellesmere_pt_config_reg_type {
-+	ELLESMERE_CONFIGREG_MMR = 0,
-+	ELLESMERE_CONFIGREG_SMC_IND,
-+	ELLESMERE_CONFIGREG_DIDT_IND,
-+	ELLESMERE_CONFIGREG_CACHE,
-+	ELLESMERE_CONFIGREG_MAX
-+};
-+
-+/* PowerContainment Features */
-+#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
-+#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
-+#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
-+
-+struct ellesmere_pt_config_reg {
-+	uint32_t                           offset;
-+	uint32_t                           mask;
-+	uint32_t                           shift;
-+	uint32_t                           value;
-+	enum ellesmere_pt_config_reg_type       type;
-+};
-+
-+struct ellesmere_pt_defaults {
-+	uint8_t   SviLoadLineEn;
-+	uint8_t   SviLoadLineVddC;
-+	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
-+	uint8_t   TDC_MAWt;
-+	uint8_t   TdcWaterfallCtl;
-+	uint8_t   DTEAmbientTempBase;
-+
-+	uint32_t  DisplayCac;
-+	uint32_t  BAPM_TEMP_GRADIENT;
-+	uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
-+	uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
-+};
-+
-+void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
-+int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
-+int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr);
-+int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr);
-+int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr);
-+int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
-+int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr);
-+
-+#endif  /* ELLESMERE_POWERTUNE_H */
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-index 2a83a4a..8ba3ad5 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-@@ -373,6 +373,37 @@ int atomctrl_get_engine_pll_dividers_vi(
- 	return result;
- }
- 
-+int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr,
-+		uint32_t clock_value,
-+		pp_atomctrl_clock_dividers_ai *dividers)
-+{
-+	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
-+	int result;
-+
-+	pll_patameters.ulClock.ulClock = clock_value;
-+	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
-+
-+	result = cgs_atom_exec_cmd_table
-+		(hwmgr->device,
-+		 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
-+		 &pll_patameters);
-+
-+	if (0 == result) {
-+		dividers->usSclk_fcw_frac     = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
-+		dividers->usSclk_fcw_int      = le16_to_cpu(pll_patameters.usSclk_fcw_int);
-+		dividers->ucSclkPostDiv       = pll_patameters.ucSclkPostDiv;
-+		dividers->ucSclkVcoMode       = pll_patameters.ucSclkVcoMode;
-+		dividers->ucSclkPllRange      = pll_patameters.ucSclkPllRange;
-+		dividers->ucSscEnable         = pll_patameters.ucSscEnable;
-+		dividers->usSsc_fcw1_frac     = le16_to_cpu(pll_patameters.usSsc_fcw1_frac);
-+		dividers->usSsc_fcw1_int      = le16_to_cpu(pll_patameters.usSsc_fcw1_int);
-+		dividers->usPcc_fcw_int       = le16_to_cpu(pll_patameters.usPcc_fcw_int);
-+		dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac);
-+		dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac);
-+	}
-+	return result;
-+}
-+
- int atomctrl_get_dfs_pll_dividers_vi(
- 		struct pp_hwmgr *hwmgr,
- 		uint32_t clock_value,
-@@ -618,7 +649,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
- 	if (!getASICProfilingInfo)
- 		return -1;
- 
--	if(getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 ||
-+	if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 ||
- 			(getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 &&
- 			getASICProfilingInfo->asHeader.ucTableContentRevision < 4))
- 		return -1;
-@@ -891,18 +922,18 @@ int atomctrl_calculate_voltage_evv_on_sclk(
- 	 *-----------------------
- 	 */
- 
--	fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4,fSclk), fSM_A5));
-+	fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5));
- 	fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b);
- 	fC_Term = fAdd(fMargin_RO_c,
- 			fAdd(fMultiply(fSM_A0,fLkg_FT),
--			fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT,fSclk)),
-+			fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)),
- 			fAdd(fMultiply(fSM_A3, fSclk),
--			fSubtract(fSM_A7,fRO_fused)))));
-+			fSubtract(fSM_A7, fRO_fused)))));
- 
- 	fVDDC_base = fSubtract(fRO_fused,
- 			fSubtract(fMargin_RO_c,
- 					fSubtract(fSM_A3, fMultiply(fSM_A1, fSclk))));
--	fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0,fSclk), fSM_A2));
-+	fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0, fSclk), fSM_A2));
- 
- 	repeat = fSubtract(fVDDC_base,
- 			fDivide(fMargin_DC_sigma, ConvertToFraction(1000)));
-@@ -916,7 +947,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
- 			fSubtract(fRO_DC_margin,
- 			fSubtract(fSM_A3,
- 			fMultiply(fSM_A2, repeat))));
--	fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0,repeat), fSM_A1));
-+	fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0, repeat), fSM_A1));
- 
- 	fSigma_DC = fSubtract(fSclk, fDC_SCLK);
- 
-@@ -996,7 +1027,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
- 		fV_NL = fRoundUpByStepSize(fV_NL, fStepSize, 0);
- 
- 		if (GreaterThan(fV_max, fV_NL) &&
--			(GreaterThan(fV_NL,fEVV_V) ||
-+			(GreaterThan(fV_NL, fEVV_V) ||
- 			Equal(fV_NL, fEVV_V))) {
- 			fV_NL = fMultiply(fV_NL, ConvertToFraction(1000));
- 
-@@ -1205,3 +1236,69 @@ int atomctrl_read_efuse(void *device, uint16_t start_index,
- 
- 	return result;
- }
-+
-+int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
-+								uint8_t level)
-+{
-+	DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
-+	int result;
-+
-+	memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq = memory_clock & SET_CLOCK_FREQ_MASK;
-+	memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag = ADJUST_MC_SETTING_PARAM;
-+	memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
-+
-+	result = cgs_atom_exec_cmd_table
-+		(hwmgr->device,
-+		 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
-+		 &memory_clock_parameters);
-+
-+	return result;
-+}
-+
-+int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
-+				uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage)
-+{
-+
-+	int result;
-+	GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;
-+
-+	get_voltage_info_param_space.ucVoltageType = voltage_type;
-+	get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
-+	get_voltage_info_param_space.usVoltageLevel = virtual_voltage_Id;
-+	get_voltage_info_param_space.ulSCLKFreq = sclk;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
-+			&get_voltage_info_param_space);
-+
-+	if (0 != result)
-+		return result;
-+
-+	*voltage = get_voltage_info_param_space.usVoltageLevel;
-+
-+	return result;
-+}
-+
-+int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table)
-+{
-+
-+	int i;
-+	u8 frev, crev;
-+	u16 size;
-+
-+	ATOM_SMU_INFO_V2_1 *psmu_info =
-+		(ATOM_SMU_INFO_V2_1 *)cgs_atom_get_data_table(hwmgr->device,
-+			GetIndexIntoMasterTable(DATA, SMU_Info),
-+			&size, &frev, &crev);
-+
-+
-+	for (i = 0; i < psmu_info->ucSclkEntryNum; i++) {
-+		table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting;
-+		table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv;
-+		table->entry[i].usFcw_pcc = psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc;
-+		table->entry[i].usFcw_trans_upper = psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper;
-+		table->entry[i].usRcw_trans_lower = psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower;
-+	}
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-index 627420b..d24ebb5 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
-@@ -101,6 +101,23 @@ struct pp_atomctrl_clock_dividers_vi {
- };
- typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
- 
-+struct pp_atomctrl_clock_dividers_ai {
-+	u16 usSclk_fcw_frac;
-+	u16  usSclk_fcw_int;
-+	u8   ucSclkPostDiv;
-+	u8   ucSclkVcoMode;
-+	u8   ucSclkPllRange;
-+	u8   ucSscEnable;
-+	u16  usSsc_fcw1_frac;
-+	u16  usSsc_fcw1_int;
-+	u16  usReserved;
-+	u16  usPcc_fcw_int;
-+	u16  usSsc_fcw_slew_frac;
-+	u16  usPcc_fcw_slew_frac;
-+};
-+typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;
-+
-+
- union pp_atomctrl_s_mpll_fb_divider {
- 	struct {
- 		uint32_t cl_kf : 12;
-@@ -204,6 +221,21 @@ struct pp_atomctrl_mc_register_address {
- 
- typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
- 
-+#define MAX_SCLK_RANGE 8
-+
-+struct pp_atom_ctrl_sclk_range_table_entry{
-+	uint8_t  ucVco_setting;
-+	uint8_t  ucPostdiv;
-+	uint16_t usFcw_pcc;
-+	uint16_t usFcw_trans_upper;
-+	uint16_t usRcw_trans_lower;
-+};
-+
-+
-+struct pp_atom_ctrl_sclk_range_table{
-+	struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
-+};
-+
- struct pp_atomctrl_mc_reg_table {
- 	uint8_t                         last;                    /* number of registers */
- 	uint8_t                         num_entries;             /* number of AC timing entries */
-@@ -240,7 +272,11 @@ extern int atomctrl_read_efuse(void *device, uint16_t start_index,
- 		uint16_t end_index, uint32_t mask, uint32_t *efuse);
- extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
- 		uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
--
--
-+extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
-+extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
-+								uint8_t level);
-+extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
-+				uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
-+extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
- #endif
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0930-drm-amd-powerplay-init-hwmgr-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0930-drm-amd-powerplay-init-hwmgr-for-ELM-BAF.patch
deleted file mode 100644
index b7ce46d8..00000000
--- a/common/recipes-kernel/linux/files/0930-drm-amd-powerplay-init-hwmgr-for-ELM-BAF.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 4fdaf2e5ff667d7b6f1ef2c3911bfe1bcf9e3a16 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 11 Mar 2016 14:39:31 -0500
-Subject: [PATCH 0930/1110] drm/amd/powerplay: init hwmgr for ELM/BAF
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index 5fb98aa..2c68199 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -34,6 +34,7 @@
- extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
- extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
- extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
-+extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
- 
- int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -67,6 +68,10 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		case CHIP_FIJI:
- 			fiji_hwmgr_init(hwmgr);
- 			break;
-+		case CHIP_BAFFIN:
-+		case CHIP_ELLESMERE:
-+			ellesemere_hwmgr_init(hwmgr);
-+			break;
- 		default:
- 			return -EINVAL;
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0931-drm-amd-powerplay-enable-powerplay-for-baffin.patch b/common/recipes-kernel/linux/files/0931-drm-amd-powerplay-enable-powerplay-for-baffin.patch
deleted file mode 100644
index 0254cb9a..00000000
--- a/common/recipes-kernel/linux/files/0931-drm-amd-powerplay-enable-powerplay-for-baffin.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From cd3797ad2438a5aea8edacd8f097c7547c0e21eb Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 11 Mar 2016 14:43:13 -0500
-Subject: [PATCH 0931/1110] drm/amd/powerplay: enable powerplay for baffin.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index e9c6ae6..ea2006a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -101,6 +101,8 @@ static int amdgpu_pp_early_init(void *handle)
- 	switch (adev->asic_type) {
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
-+	case CHIP_BAFFIN:
-+	case CHIP_ELLESMERE:
- 		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
- 		break;
- 	case CHIP_CARRIZO:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0932-drm-amd-powerplay-add-thermal-control-for-elm-baf.patch b/common/recipes-kernel/linux/files/0932-drm-amd-powerplay-add-thermal-control-for-elm-baf.patch
deleted file mode 100644
index f4b7d274..00000000
--- a/common/recipes-kernel/linux/files/0932-drm-amd-powerplay-add-thermal-control-for-elm-baf.patch
+++ /dev/null
@@ -1,898 +0,0 @@
-From ebb94bea73212b28b3bea0edf614b3cd21d60f27 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 2 Feb 2016 16:09:24 -0500
-Subject: [PATCH 0932/1110] drm/amd/powerplay: add thermal control for elm/baf
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   2 +-
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  39 +-
- .../drm/amd/powerplay/hwmgr/ellesmere_thermal.c    | 711 +++++++++++++++++++++
- .../drm/amd/powerplay/hwmgr/ellesmere_thermal.h    |  62 ++
- 4 files changed, 801 insertions(+), 13 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index 2982d5c..f13327d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -9,7 +9,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
-                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
-                fiji_clockpowergating.o fiji_thermal.o \
--	       ellesmere_hwmgr.o ellesmere_powertune.o
-+	       ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-index 10e8e87..3ef8d3c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-@@ -57,6 +57,8 @@
- #include "dce/dce_10_0_d.h"
- #include "dce/dce_10_0_sh_mask.h"
- 
-+#include "ellesmere_thermal.h"
-+
- #define MC_CG_ARB_FREQ_F0           0x0a
- #define MC_CG_ARB_FREQ_F1           0x0b
- #define MC_CG_ARB_FREQ_F2           0x0c
-@@ -4198,8 +4200,14 @@ static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i
- 
- static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
- {
-+	hwmgr->thermal_controller.
-+	advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
- 
-+	if (phm_is_hw_access_blocked(hwmgr))
- 		return 0;
-+
-+	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
- }
- 
- int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
-@@ -4290,9 +4298,16 @@ int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
- * @param    usMaxFanRpm:  max operating fan RPM value.
- * @return   The response that came from the SMC.
- */
--static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
-+static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
- {
--	return 0;
-+	hwmgr->thermal_controller.
-+	advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
- }
- 
- int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
-@@ -4529,15 +4544,15 @@ static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
- 	.display_config_changed = ellesmere_display_configuration_changed_task,
- 	.set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
- 	.set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output,
--	.get_temperature = NULL,
--	.stop_thermal_controller = NULL,
--	.get_fan_speed_info = NULL,
--	.get_fan_speed_percent = NULL,
--	.set_fan_speed_percent = NULL,
--	.reset_fan_speed_to_default = NULL,
--	.get_fan_speed_rpm = NULL,
--	.set_fan_speed_rpm = NULL,
--	.uninitialize_thermal_controller = NULL,
-+	.get_temperature = ellesmere_thermal_get_temperature,
-+	.stop_thermal_controller = ellesmere_thermal_stop_thermal_controller,
-+	.get_fan_speed_info = ellesmere_fan_ctrl_get_fan_speed_info,
-+	.get_fan_speed_percent = ellesmere_fan_ctrl_get_fan_speed_percent,
-+	.set_fan_speed_percent = ellesmere_fan_ctrl_set_fan_speed_percent,
-+	.reset_fan_speed_to_default = ellesmere_fan_ctrl_reset_fan_speed_to_default,
-+	.get_fan_speed_rpm = ellesmere_fan_ctrl_get_fan_speed_rpm,
-+	.set_fan_speed_rpm = ellesmere_fan_ctrl_set_fan_speed_rpm,
-+	.uninitialize_thermal_controller = ellesmere_thermal_ctrl_uninitialize_thermal_controller,
- 	.register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt,
- 	.check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration,
- 	.check_states_equal = ellesmere_check_states_equal,
-@@ -4554,7 +4569,7 @@ int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
- 	hwmgr->backend = data;
- 	hwmgr->hwmgr_func = &ellesmere_hwmgr_funcs;
- 	hwmgr->pptable_func = &tonga_pptable_funcs;
--
-+	pp_ellesmere_thermal_initialize(hwmgr);
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
-new file mode 100644
-index 0000000..08be400
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
-@@ -0,0 +1,711 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "ellesmere_thermal.h"
-+#include "ellesmere_hwmgr.h"
-+#include "ellesmere_smumgr.h"
-+#include "ellesmere_ppsmc.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+
-+int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
-+		struct phm_fan_speed_info *fan_speed_info)
-+{
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	fan_speed_info->supports_percent_read = true;
-+	fan_speed_info->supports_percent_write = true;
-+	fan_speed_info->min_percent = 0;
-+	fan_speed_info->max_percent = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
-+		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
-+		fan_speed_info->supports_rpm_read = true;
-+		fan_speed_info->supports_rpm_write = true;
-+		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
-+		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
-+	} else {
-+		fan_speed_info->min_rpm = 0;
-+		fan_speed_info->max_rpm = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
-+		uint32_t *speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_STATUS, FDO_PWM_DUTY);
-+
-+	if (duty100 == 0)
-+		return -EINVAL;
-+
-+
-+	tmp64 = (uint64_t)duty * 100;
-+	do_div(tmp64, duty100);
-+	*speed = (uint32_t)tmp64;
-+
-+	if (*speed > 100)
-+		*speed = 100;
-+
-+	return 0;
-+}
-+
-+int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
-+{
-+	uint32_t tach_period;
-+	uint32_t crystal_clock_freq;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
-+			(hwmgr->thermal_controller.fanInfo.
-+				ucTachometerPulsesPerRevolution == 0))
-+		return 0;
-+
-+	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_TACH_STATUS, TACH_PERIOD);
-+
-+	if (tach_period == 0)
-+		return -EINVAL;
-+
-+	crystal_clock_freq = tonga_get_xclk(hwmgr);
-+
-+	*speed = 60 * crystal_clock_freq * 10000 / tach_period;
-+
-+	return 0;
-+}
-+
-+/**
-+* Set Fan Speed Control to static mode, so that the user can decide what speed to use.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*           mode    the fan control mode, 0 default, 1 by percent, 5, by RPM
-+* @exception Should always succeed.
-+*/
-+int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+
-+	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+		hwmgr->fan_ctrl_default_mode =
-+				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,	CGS_IND_REG__SMC,
-+						CG_FDO_CTRL2, FDO_PWM_MODE);
-+		hwmgr->tmin =
-+				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+						CG_FDO_CTRL2, TMIN);
-+		hwmgr->fan_ctrl_is_in_default_mode = false;
-+	}
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, TMIN, 0);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, FDO_PWM_MODE, mode);
-+
-+	return 0;
-+}
-+
-+/**
-+* Reset Fan Speed Control to default mode.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Should always succeed.
-+*/
-+int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (!hwmgr->fan_ctrl_is_in_default_mode) {
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, TMIN, hwmgr->tmin);
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	}
-+
-+	return 0;
-+}
-+
-+int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
-+		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_FanSpeedInTableIsRPM))
-+			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
-+					hwmgr->thermal_controller.
-+					advanceFanControlParameters.usMaxFanRPM);
-+		else
-+			hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
-+					hwmgr->thermal_controller.
-+					advanceFanControlParameters.usMaxFanPWM);
-+
-+	} else {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
-+		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+	}
-+
-+	if (!result && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucTargetTemperature)
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanTemperatureTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucTargetTemperature);
-+
-+	return result;
-+}
-+
-+
-+int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
-+}
-+
-+/**
-+* Set Fan Speed in percent.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (0% - 100%) to be set.
-+* @exception Fails is the 100% setting appears to be 0.
-+*/
-+int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
-+		uint32_t speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (speed > 100)
-+		speed = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl))
-+		ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr);
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0)
-+		return -EINVAL;
-+
-+	tmp64 = (uint64_t)speed * 100;
-+	do_div(tmp64, duty100);
-+	duty = (uint32_t)tmp64;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
-+
-+	return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reset Fan Speed to default.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Always succeeds.
-+*/
-+int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl)) {
-+		result = ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+		if (!result)
-+			result = ellesmere_fan_ctrl_start_smc_fan_control(hwmgr);
-+	} else
-+		result = ellesmere_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set Fan Speed in RPM.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (min - max) to be set.
-+* @exception Fails is the speed not lie between min and max.
-+*/
-+int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
-+{
-+	uint32_t tach_period;
-+	uint32_t crystal_clock_freq;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
-+			(hwmgr->thermal_controller.fanInfo.
-+			ucTachometerPulsesPerRevolution == 0) ||
-+			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
-+			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
-+		return 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl))
-+		ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr);
-+
-+	crystal_clock_freq = tonga_get_xclk(hwmgr);
-+
-+	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_TACH_STATUS, TACH_PERIOD, tach_period);
-+
-+	return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reads the remote temperature from the SIslands thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr)
-+{
-+	int temp;
-+
-+	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_STATUS, CTF_TEMP);
-+
-+	/* Bit 9 means the reading is lower than the lowest usable value. */
-+	if (temp & 0x200)
-+		temp = ELLESMERE_THERMAL_MAXIMUM_TEMP_READING;
-+	else
-+		temp = temp & 0x1ff;
-+
-+	temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	return temp;
-+}
-+
-+/**
-+* Set the requested temperature range for high and low alert signals
-+*
-+* @param    hwmgr The address of the hardware manager.
-+* @param    range Temperature range to be programmed for high and low alert signals
-+* @exception PP_Result_BadInput if the input data is not valid.
-+*/
-+static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-+		uint32_t low_temp, uint32_t high_temp)
-+{
-+	uint32_t low = ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP *
-+			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+	uint32_t high = ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP *
-+			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	if (low < low_temp)
-+		low = low_temp;
-+	if (high > high_temp)
-+		high = high_temp;
-+
-+	if (low > high)
-+		return -EINVAL;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, DIG_THERM_INTH,
-+			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, DIG_THERM_INTL,
-+			(low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_CTRL, DIG_THERM_DPM,
-+			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs thermal controller one-time setting registers
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_TACH_CTRL, EDGE_PER_REV,
-+				hwmgr->thermal_controller.fanInfo.
-+				ucTachometerPulsesPerRevolution - 1);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
-+
-+	return 0;
-+}
-+
-+/**
-+* Enable thermal alerts on the RV770 thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK);
-+	alert &= ~(ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to enable internal thermal interrupts */
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
-+}
-+
-+/**
-+* Disable thermal alerts on the RV770 thermal controller.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK);
-+	alert |= (ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to disable internal thermal interrupts */
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
-+}
-+
-+/**
-+* Uninitialize the thermal controller.
-+* Currently just disables alerts.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	int result = ellesmere_thermal_disable_alert(hwmgr);
-+
-+	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
-+		ellesmere_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set up the fan table to control the fan using the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (data->fan_table_start == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
-+			usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->
-+			thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = tonga_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
-+			thermal_controller.advanceFanControlParameters.ulCycleDelay *
-+			reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
-+			hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	res = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start,
-+			(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
-+			data->sram_end);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucMinimumPWMLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanMinPwm,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucMinimumPWMLimit);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanSclkTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-+
-+	if (res)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+
-+	return 0;
-+}
-+
-+/**
-+* Start the fan control on the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+/* If the fantable setup has failed we could have disabled
-+ * PHM_PlatformCaps_MicrocodeFanControl even after
-+ * this function was included in the table.
-+ * Make sure that we still think controlling the fan is OK.
-+*/
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl)) {
-+		ellesmere_fan_ctrl_start_smc_fan_control(hwmgr);
-+		ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Set temperature range for high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
-+
-+	if (range == NULL)
-+		return -EINVAL;
-+
-+	return ellesmere_thermal_set_temperature_range(hwmgr, range->min, range->max);
-+}
-+
-+/**
-+* Programs one-time setting registers
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from initialize thermal controller routine
-+*/
-+int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+    return ellesmere_thermal_initialize(hwmgr);
-+}
-+
-+/**
-+* Enable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from enable alert routine
-+*/
-+int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	return ellesmere_thermal_enable_alert(hwmgr);
-+}
-+
-+/**
-+* Disable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from disable alert routine
-+*/
-+static int tf_ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	return ellesmere_thermal_disable_alert(hwmgr);
-+}
-+
-+static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	int ret;
-+	struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
-+
-+	if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
-+		return 0;
-+
-+	ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
-+			0 : -1;
-+
-+	if (!ret)
-+		/* If this param is not changed, this function could fire unnecessarily */
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
-+
-+	return ret;
-+}
-+
-+static struct phm_master_table_item
-+ellesmere_thermal_start_thermal_controller_master_list[] = {
-+	{NULL, tf_ellesmere_thermal_initialize},
-+	{NULL, tf_ellesmere_thermal_set_temperature_range},
-+	{NULL, tf_ellesmere_thermal_enable_alert},
-+	{NULL, tf_ellesmere_thermal_avfs_enable},
-+/* We should restrict performance levels to low before we halt the SMC.
-+ * On the other hand we are still in boot state when we do this
-+ * so it would be pointless.
-+ * If this assumption changes we have to revisit this table.
-+ */
-+	{NULL, tf_ellesmere_thermal_setup_fan_table},
-+	{NULL, tf_ellesmere_thermal_start_smc_fan_control},
-+	{NULL, NULL}
-+};
-+
-+static struct phm_master_table_header
-+ellesmere_thermal_start_thermal_controller_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	ellesmere_thermal_start_thermal_controller_master_list
-+};
-+
-+static struct phm_master_table_item
-+ellesmere_thermal_set_temperature_range_master_list[] = {
-+	{NULL, tf_ellesmere_thermal_disable_alert},
-+	{NULL, tf_ellesmere_thermal_set_temperature_range},
-+	{NULL, tf_ellesmere_thermal_enable_alert},
-+	{NULL, NULL}
-+};
-+
-+struct phm_master_table_header
-+ellesmere_thermal_set_temperature_range_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	ellesmere_thermal_set_temperature_range_master_list
-+};
-+
-+int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
-+		ellesmere_fan_ctrl_set_default_mode(hwmgr);
-+	return 0;
-+}
-+
-+/**
-+* Initializes the thermal controller related functions in the Hardware Manager structure.
-+* @param    hwmgr The address of the hardware manager.
-+* @exception Any error code from the low-level communication.
-+*/
-+int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	result = phm_construct_table(hwmgr,
-+			&ellesmere_thermal_set_temperature_range_master,
-+			&(hwmgr->set_temperature_range));
-+
-+	if (!result) {
-+		result = phm_construct_table(hwmgr,
-+				&ellesmere_thermal_start_thermal_controller_master,
-+				&(hwmgr->start_thermal_controller));
-+		if (result)
-+			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
-+	}
-+
-+	if (!result)
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	return result;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h
-new file mode 100644
-index 0000000..4263e9b
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _ELLESMERE_THERMAL_H_
-+#define _ELLESMERE_THERMAL_H_
-+
-+#include "hwmgr.h"
-+
-+#define ELLESMERE_THERMAL_HIGH_ALERT_MASK         0x1
-+#define ELLESMERE_THERMAL_LOW_ALERT_MASK          0x2
-+
-+#define ELLESMERE_THERMAL_MINIMUM_TEMP_READING    -256
-+#define ELLESMERE_THERMAL_MAXIMUM_TEMP_READING    255
-+
-+#define ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP      0
-+#define ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP      255
-+
-+#define FDO_PWM_MODE_STATIC  1
-+#define FDO_PWM_MODE_STATIC_RPM 5
-+
-+
-+extern int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+
-+extern int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr);
-+extern int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
-+extern int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
-+extern int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
-+extern int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-+extern int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr);
-+extern int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
-+extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
-+
-+#endif
-+
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0933-drm-amd-powerplay-add-UVD-VCE-DPM-and-powergating-su.patch b/common/recipes-kernel/linux/files/0933-drm-amd-powerplay-add-UVD-VCE-DPM-and-powergating-su.patch
deleted file mode 100644
index e2bfea45..00000000
--- a/common/recipes-kernel/linux/files/0933-drm-amd-powerplay-add-UVD-VCE-DPM-and-powergating-su.patch
+++ /dev/null
@@ -1,380 +0,0 @@
-From d926bf6939e84d8837b80d0883d1711817a9081c Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 5 Feb 2016 14:47:06 -0500
-Subject: [PATCH 0933/1110] drm/amd/powerplay: add UVD&VCE DPM and powergating
- support for elm/baf
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |   3 +-
- .../powerplay/hwmgr/ellesmere_clockpowergating.c   | 153 +++++++++++++++++++++
- .../powerplay/hwmgr/ellesmere_clockpowergating.h   |  37 +++++
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  91 +++++++++++-
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |   4 +
- 5 files changed, 282 insertions(+), 6 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index f13327d..5437ec0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -9,7 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
-                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
-                fiji_clockpowergating.o fiji_thermal.o \
--	       ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o
-+	       ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \
-+	       ellesmere_clockpowergating.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-new file mode 100644
-index 0000000..0dee0df
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-@@ -0,0 +1,153 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "ellesmere_clockpowergating.h"
-+
-+int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_uvd_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_UVDPowerOFF);
-+	return 0;
-+}
-+
-+int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_uvd_power_gating(hwmgr)) {
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDPowerON, 1);
-+		} else {
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDPowerON, 0);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_vce_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_VCEPowerOFF);
-+	return 0;
-+}
-+
-+int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_vce_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_VCEPowerON);
-+	return 0;
-+}
-+
-+int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SamuPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SAMPowerOFF);
-+	return 0;
-+}
-+
-+int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SamuPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SAMPowerON);
-+	return 0;
-+}
-+
-+int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+	data->samu_power_gated = false;
-+
-+	ellesmere_phm_powerup_uvd(hwmgr);
-+	ellesmere_phm_powerup_vce(hwmgr);
-+	ellesmere_phm_powerup_samu(hwmgr);
-+
-+	return 0;
-+}
-+
-+int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (data->uvd_power_gated == bgate)
-+		return 0;
-+
-+	data->uvd_power_gated = bgate;
-+
-+	if (bgate) {
-+		ellesmere_update_uvd_dpm(hwmgr, true);
-+		ellesmere_phm_powerdown_uvd(hwmgr);
-+	} else {
-+		ellesmere_phm_powerup_uvd(hwmgr);
-+		ellesmere_update_uvd_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (data->vce_power_gated == bgate)
-+		return 0;
-+
-+	if (bgate)
-+		ellesmere_phm_powerdown_vce(hwmgr);
-+	else
-+		ellesmere_phm_powerup_vce(hwmgr);
-+
-+	return 0;
-+}
-+
-+int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+
-+	if (data->samu_power_gated == bgate)
-+		return 0;
-+
-+	data->samu_power_gated = bgate;
-+
-+	if (bgate) {
-+		ellesmere_update_samu_dpm(hwmgr, true);
-+		ellesmere_phm_powerdown_samu(hwmgr);
-+	} else {
-+		ellesmere_phm_powerup_samu(hwmgr);
-+		ellesmere_update_samu_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-new file mode 100644
-index 0000000..56a950e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _ELLESMERE_CLOCK_POWER_GATING_H_
-+#define _ELLESMERE_CLOCK_POWER_GATING_H_
-+
-+#include "ellesmere_hwmgr.h"
-+#include "pp_asicblocks.h"
-+
-+int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
-+int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
-+int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
-+int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
-+
-+#endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-index 3ef8d3c..62f0f36 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-@@ -58,6 +58,7 @@
- #include "dce/dce_10_0_sh_mask.h"
- 
- #include "ellesmere_thermal.h"
-+#include "ellesmere_clockpowergating.h"
- 
- #define MC_CG_ARB_FREQ_F0           0x0a
- #define MC_CG_ARB_FREQ_F1           0x0b
-@@ -3962,13 +3963,62 @@ static int ellesmere_generate_dpm_level_enable_mask(
- 	return 0;
- }
- 
--static int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+int ellesmere_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
- 	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+			PPSMC_MSG_UVDDPM_Enable :
-+			PPSMC_MSG_UVDDPM_Disable);
-+}
-+
-+int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
- 			PPSMC_MSG_VCEDPM_Enable :
- 			PPSMC_MSG_VCEDPM_Disable);
- }
- 
-+int ellesmere_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+			PPSMC_MSG_SAMUDPM_Enable :
-+			PPSMC_MSG_SAMUDPM_Disable);
-+}
-+
-+int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.UvdBootLevel = 0;
-+		if (table_info->mm_dep_table->count > 0)
-+			data->smc_state_table.UvdBootLevel =
-+					(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0x00FFFFFF;
-+		mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_UVDDPM) ||
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDDPM_SetEnabledMask,
-+					(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
-+	}
-+
-+	return ellesmere_enable_disable_uvd_dpm(hwmgr, !bgate);
-+}
-+
- static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- {
- 	const struct phm_set_power_state_input *states =
-@@ -4015,6 +4065,37 @@ static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
- 	return 0;
- }
- 
-+int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.SamuBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFFFFFF00;
-+		mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SAMUDPM_SetEnabledMask,
-+					(uint32_t)(1 << data->smc_state_table.SamuBootLevel));
-+	}
-+
-+	return ellesmere_enable_disable_samu_dpm(hwmgr, !bgate);
-+}
-+
- static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr)
- {
- 	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-@@ -4536,10 +4617,10 @@ static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
- 	.get_pp_table_entry = ellesmere_get_pp_table_entry,
- 	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
- 	.print_current_perforce_level = ellesmere_print_current_perforce_level,
--	.powerdown_uvd = NULL,
--	.powergate_uvd = NULL,
--	.powergate_vce = NULL,
--	.disable_clock_power_gating = NULL,
-+	.powerdown_uvd = ellesmere_phm_powerdown_uvd,
-+	.powergate_uvd = ellesmere_phm_powergate_uvd,
-+	.powergate_vce = ellesmere_phm_powergate_vce,
-+	.disable_clock_power_gating = ellesmere_phm_disable_clock_power_gating,
- 	.notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment,
- 	.display_config_changed = ellesmere_display_configuration_changed_task,
- 	.set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-index 4d57698..7f90252 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-@@ -345,5 +345,9 @@ enum Ellesmere_I2CLineID {
- 
- int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
- 
-+int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
-+
- #endif
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0934-drm-amd-amdgpu-Add-smc_sk-firmware-in-baffin-ellesme.patch b/common/recipes-kernel/linux/files/0934-drm-amd-amdgpu-Add-smc_sk-firmware-in-baffin-ellesme.patch
deleted file mode 100644
index f9782b6c..00000000
--- a/common/recipes-kernel/linux/files/0934-drm-amd-amdgpu-Add-smc_sk-firmware-in-baffin-ellesme.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 34b371ae9b63f4c0ee28fcef5636c3a5f60bb2d6 Mon Sep 17 00:00:00 2001
-From: yanyang1 <Young.Yang@amd.com>
-Date: Fri, 5 Feb 2016 17:39:37 +0800
-Subject: [PATCH 0934/1110] drm/amd/amdgpu: Add smc_sk firmware in baffin &
- ellesmere.
-
-add CGS_UCODE_ID_SMU_SK.
-
-Signed-off-by: yanyang1 <Young.Yang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 12 +++++++++---
- drivers/gpu/drm/amd/include/cgs_common.h |  1 +
- 2 files changed, 10 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 8bc4040..594159c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -702,7 +702,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
- {
- 	CGS_FUNC_ADEV;
- 
--	if (CGS_UCODE_ID_SMU != type) {
-+	if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
- 		uint64_t gpu_addr;
- 		uint32_t data_size;
- 		const struct gfx_firmware_header_v1_0 *header;
-@@ -743,10 +743,16 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
- 			strcpy(fw_name, "amdgpu/fiji_smc.bin");
- 			break;
- 		case CHIP_BAFFIN:
--			strcpy(fw_name, "amdgpu/baffin_smc.bin");
-+			if (type == CGS_UCODE_ID_SMU)
-+				strcpy(fw_name, "amdgpu/baffin_smc.bin");
-+			else if (type == CGS_UCODE_ID_SMU_SK)
-+				strcpy(fw_name, "amdgpu/baffin_smc_sk.bin");
- 			break;
- 		case CHIP_ELLESMERE:
--			strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
-+			if (type == CGS_UCODE_ID_SMU)
-+				strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
-+			else if (type == CGS_UCODE_ID_SMU_SK)
-+				strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin");
- 			break;
- 		default:
- 			DRM_ERROR("SMC firmware not supported\n");
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index ca1e229..7a3714b 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -94,6 +94,7 @@ enum cgs_voltage_planes {
-  */
- enum cgs_ucode_id {
- 	CGS_UCODE_ID_SMU = 0,
-+	CGS_UCODE_ID_SMU_SK,
- 	CGS_UCODE_ID_SDMA0,
- 	CGS_UCODE_ID_SDMA1,
- 	CGS_UCODE_ID_CP_CE,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0935-drm-amd-powerplay-Add-smc_sk-firmware-to-baffin-elle.patch b/common/recipes-kernel/linux/files/0935-drm-amd-powerplay-Add-smc_sk-firmware-to-baffin-elle.patch
deleted file mode 100644
index 4c25fe37..00000000
--- a/common/recipes-kernel/linux/files/0935-drm-amd-powerplay-Add-smc_sk-firmware-to-baffin-elle.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 1467339fa32c56dcb71c93326748646b9553ef62 Mon Sep 17 00:00:00 2001
-From: yanyang1 <Young.Yang@amd.com>
-Date: Fri, 5 Feb 2016 17:43:17 +0800
-Subject: [PATCH 0935/1110] drm/amd/powerplay: Add smc_sk firmware to baffin &
- ellesmere.
-
-update relational h files.
-
-Signed-off-by: yanyang1 <Young.Yang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h        |  1 +
- drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h    | 10 ++++++++--
- drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h |  1 +
- 3 files changed, 10 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
-index c24a81e..880152c 100644
---- a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
-+++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h
-@@ -44,6 +44,7 @@
- #define UCODE_ID_IH_REG_RESTORE   11
- #define UCODE_ID_VBIOS            12
- #define UCODE_ID_MISC_METADATA    13
-+#define UCODE_ID_SMU_SK		      14
- #define UCODE_ID_RLC_SCRATCH      32
- #define UCODE_ID_RLC_SRM_ARAM     33
- #define UCODE_ID_RLC_SRM_DRAM     34
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-index 733fa37..f816262 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-@@ -71,8 +71,12 @@ struct SMU_SclkSetting {
- 	uint16_t    Pcc_fcw_int;
- 	uint8_t     PllRange;
- 	uint8_t     SSc_En;
-+	uint16_t    Sclk_slew_rate;
-+	uint16_t    Pcc_up_slew_rate;
-+	uint16_t    Pcc_down_slew_rate;
- 	uint16_t    Fcw1_int;
- 	uint16_t    Fcw1_frac;
-+	uint16_t    Sclk_ss_slew_rate;
- };
- typedef struct SMU_SclkSetting SMU_SclkSetting;
- 
-@@ -120,7 +124,8 @@ struct SMU74_Discrete_Ulv {
- 	uint16_t    VddcOffset;
- 	uint8_t     VddcOffsetVid;
- 	uint8_t     VddcPhase;
--	uint32_t    Reserved;
-+	uint16_t    BifSclkDfs;
-+	uint16_t    Reserved;
- };
- 
- typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
-@@ -155,7 +160,8 @@ struct SMU74_Discrete_LinkLevel {
- 	uint8_t     SPC;
- 	uint32_t    DownThreshold;
- 	uint32_t    UpThreshold;
--	uint32_t    Reserved;
-+	uint16_t    BifSclkDfs;
-+	uint16_t    Reserved;
- };
- 
- typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
-index c24a81e..880152c 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h
-@@ -44,6 +44,7 @@
- #define UCODE_ID_IH_REG_RESTORE   11
- #define UCODE_ID_VBIOS            12
- #define UCODE_ID_MISC_METADATA    13
-+#define UCODE_ID_SMU_SK		      14
- #define UCODE_ID_RLC_SCRATCH      32
- #define UCODE_ID_RLC_SRM_ARAM     33
- #define UCODE_ID_RLC_SRM_DRAM     34
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0936-drm-amd-powerplay-update-baffin-ellesmere-smc_sk-fir.patch b/common/recipes-kernel/linux/files/0936-drm-amd-powerplay-update-baffin-ellesmere-smc_sk-fir.patch
deleted file mode 100644
index 52b2bc51..00000000
--- a/common/recipes-kernel/linux/files/0936-drm-amd-powerplay-update-baffin-ellesmere-smc_sk-fir.patch
+++ /dev/null
@@ -1,431 +0,0 @@
-From 684b54e089cf5a830d0c9c99abb8c7a990e384fe Mon Sep 17 00:00:00 2001
-From: yanyang1 <Young.Yang@amd.com>
-Date: Sat, 6 Feb 2016 13:28:47 +0800
-Subject: [PATCH 0936/1110] drm/amd/powerplay: update baffin & ellesmere smc_sk
- firmware.
-
-sync the code form catalyst CL:#1230866.
-
-Signed-off-by: yanyang1 <Young.Yang@amd.com>
-Rviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  51 ++++++++++-
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |   1 +
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h    |   2 +
- .../gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h    |  14 +++
- .../amd/powerplay/hwmgr/tonga_processpptables.c    | 101 +++++++++++++++------
- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c    |  28 ++++--
- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.h    |   2 +
- 7 files changed, 162 insertions(+), 37 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-index 62f0f36..043aefa 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-@@ -222,6 +222,22 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
- 			" found a available voltage in VDDC DPM Table \n");
- }
- 
-+/**
-+* Enable voltage control
-+*
-+* @param    pHwMgr  the address of the powerplay hardware manager.
-+* @return   always PP_Result_OK
-+*/
-+int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
-+{
-+	PP_ASSERT_WITH_CODE(
-+		(hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
-+		"Failed to enable voltage DPM during DPM Start Function!",
-+		return 1;
-+	);
-+
-+	return 0;
-+}
- 
- /**
- * Checks if we want to support voltage control
-@@ -586,6 +602,10 @@ static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
- 							pcie_table->entries[i].lane_width));
- 		}
- 		data->dpm_table.pcie_speed_table.count = max_entry - 1;
-+
-+		/* Setup BIF_SCLK levels */
-+		for (i = 0; i < max_entry; i++)
-+			data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
- 	} else {
- 		/* Hardcode Pcie Table */
- 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
-@@ -938,9 +958,13 @@ static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- 		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
- 		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
- 		sclk_setting->PllRange = dividers.ucSclkPllRange;
-+		sclk_setting->Sclk_slew_rate = 0x400;
-+		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
-+		sclk_setting->Pcc_down_slew_rate = 0xffff;
- 		sclk_setting->SSc_En = dividers.ucSscEnable;
- 		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
- 		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
-+		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
- 		return result;
- 	}
- 
-@@ -1174,8 +1198,12 @@ static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
- 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
- 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
- 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
- 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
- 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
- 	return 0;
- }
- 
-@@ -1458,8 +1486,12 @@ static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
- 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
- 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
- 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
- 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
- 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
- 
- 	if (!data->mclk_dpm_key_disabled) {
- 		/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
-@@ -1966,6 +1998,7 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr)
- 	const struct ellesmere_ulv_parm *ulv = &(data->ulv);
- 	uint8_t i;
- 	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+	pp_atomctrl_clock_dividers_vi dividers;
- 
- 	result = ellesmere_setup_default_dpm_tables(hwmgr);
- 	PP_ASSERT_WITH_CODE(0 == result,
-@@ -2121,6 +2154,17 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr)
- 		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
- 	}
- 
-+	/* Populate BIF_SCLK levels into SMC DPM table */
-+	for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
-+		PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
-+
-+		if (i == 0)
-+			table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
-+		else
-+			table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
-+	}
-+
- 	for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
- 		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
- 
-@@ -2284,12 +2328,13 @@ static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr)
- 					VoltageChangeTimeout), 0x1000);
- 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
- 			SWRST_COMMAND_1, RESETLC, 0x0);
--
-+/*
- 	PP_ASSERT_WITH_CODE(
- 			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
- 					PPSMC_MSG_Voltage_Cntl_Enable)),
- 			"Failed to enable voltage DPM during DPM Start Function!",
- 			return -1);
-+*/
- 
- 	if (ellesmere_enable_sclk_mclk_dpm(hwmgr)) {
- 		printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
-@@ -2450,6 +2495,10 @@ int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
- 			"Failed to enable SCLK control!", result = tmp_result);
- 
-+	tmp_result = ellesmere_enable_smc_voltage_controller(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable voltage control!", result = tmp_result);
-+
- 	tmp_result = ellesmere_enable_ulv(hwmgr);
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
- 			"Failed to enable ULV!", result = tmp_result);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-index 7f90252..dd6c60b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-@@ -274,6 +274,7 @@ struct ellesmere_hwmgr {
- 
- 	/* ---- DI/DT ---- */
- 	struct ellesmere_display_timing        display_timing;
-+	uint32_t                      bif_sclk_table[SMU74_MAX_LEVELS_LINK];
- 
- 	/* ---- Thermal Temperature Setting ---- */
- 	struct ellesmere_dpmlevel_enable_mask     dpm_level_enable_mask;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
-index c9e6c2d..347fef1 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
-@@ -92,6 +92,8 @@ typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table;
- struct phm_ppt_v1_pcie_record {
- 	uint8_t gen_speed;
- 	uint8_t lane_width;
-+	uint16_t usreserved;
-+	uint32_t pcie_sclk;
- };
- typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-index 9a4456e..a2c87ae 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-@@ -209,6 +209,20 @@ typedef struct _ATOM_Tonga_PCIE_Table {
- 	ATOM_Tonga_PCIE_Record entries[1];							/* Dynamically allocate entries. */
- } ATOM_Tonga_PCIE_Table;
- 
-+typedef struct _ATOM_Ellesmere_PCIE_Record {
-+	UCHAR ucPCIEGenSpeed;
-+	UCHAR usPCIELaneWidth;
-+	UCHAR ucReserved[2];
-+	ULONG ulPCIE_Sclk;
-+} ATOM_Ellesmere_PCIE_Record;
-+
-+typedef struct _ATOM_Ellesmere_PCIE_Table {
-+	UCHAR ucRevId;
-+	UCHAR ucNumEntries;                                         /* Number of entries. */
-+	ATOM_Ellesmere_PCIE_Record entries[1];                      /* Dynamically allocate entries. */
-+} ATOM_Ellesmere_PCIE_Table;
-+
-+
- typedef struct _ATOM_Tonga_MM_Dependency_Record {
- 	UCHAR   ucVddcInd;											 /* VDDC voltage */
- 	USHORT  usVddgfxOffset;									  /* Offset relative to VDDC voltage */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index b156481..ecbc43f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -448,47 +448,90 @@ static int get_sclk_voltage_dependency_table(
- static int get_pcie_table(
- 		struct pp_hwmgr *hwmgr,
- 		phm_ppt_v1_pcie_table **pp_tonga_pcie_table,
--		const ATOM_Tonga_PCIE_Table * atom_pcie_table
-+		const PPTable_Generic_SubTable_Header * pTable
- 		)
- {
- 	uint32_t table_size, i, pcie_count;
- 	phm_ppt_v1_pcie_table *pcie_table;
- 	struct phm_ppt_v1_information *pp_table_information =
- 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	PP_ASSERT_WITH_CODE((0 != atom_pcie_table->ucNumEntries),
--		"Invalid PowerPlay Table!", return -1);
- 
--	table_size = sizeof(uint32_t) +
--		sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
-+	if (pTable->ucRevId < 1) {
-+		const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)pTable;
-+		PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
-+			"Invalid PowerPlay Table!", return -1);
- 
--	pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
-+		table_size = sizeof(uint32_t) +
-+			sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
- 
--	if (NULL == pcie_table)
--		return -ENOMEM;
-+		pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
- 
--	memset(pcie_table, 0x00, table_size);
-+		if (pcie_table == NULL)
-+			return -ENOMEM;
- 
--	/*
--	* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
--	* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
--	*/
--	pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
--	if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
--		pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
--	else
--		printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
--		Disregarding the excess entries... \n");
-+		memset(pcie_table, 0x00, table_size);
- 
--	pcie_table->count = pcie_count;
-+		/*
-+		* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
-+		* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
-+		*/
-+		pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
-+		if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
-+			pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
-+		else
-+			printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
-+			Disregarding the excess entries... \n");
- 
--	for (i = 0; i < pcie_count; i++) {
--		pcie_table->entries[i].gen_speed =
--			atom_pcie_table->entries[i].ucPCIEGenSpeed;
--		pcie_table->entries[i].lane_width =
--			atom_pcie_table->entries[i].usPCIELaneWidth;
--	}
-+		pcie_table->count = pcie_count;
-+
-+		for (i = 0; i < pcie_count; i++) {
-+			pcie_table->entries[i].gen_speed =
-+				atom_pcie_table->entries[i].ucPCIEGenSpeed;
-+			pcie_table->entries[i].lane_width =
-+				atom_pcie_table->entries[i].usPCIELaneWidth;
-+		}
-+
-+		*pp_tonga_pcie_table = pcie_table;
-+	} else {
-+		/* Ellesmere/Baffin and newer. */
-+		const ATOM_Ellesmere_PCIE_Table *atom_pcie_table = (ATOM_Ellesmere_PCIE_Table *)pTable;
-+		PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
-+			"Invalid PowerPlay Table!", return -1);
-+
-+		table_size = sizeof(uint32_t) +
-+			sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
-+
-+		pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
-+
-+		if (pcie_table == NULL)
-+			return -ENOMEM;
-+
-+		memset(pcie_table, 0x00, table_size);
-+
-+		/*
-+		* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
-+		* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
-+		*/
-+		pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
-+		if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
-+			pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
-+		else
-+			printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
-+			Disregarding the excess entries... \n");
-+
-+		pcie_table->count = pcie_count;
-+
-+		for (i = 0; i < pcie_count; i++) {
-+			pcie_table->entries[i].gen_speed =
-+				atom_pcie_table->entries[i].ucPCIEGenSpeed;
-+			pcie_table->entries[i].lane_width =
-+				atom_pcie_table->entries[i].usPCIELaneWidth;
-+			pcie_table->entries[i].pcie_sclk =
-+				atom_pcie_table->entries[i].ulPCIE_Sclk;
-+		}
- 
--	*pp_tonga_pcie_table = pcie_table;
-+		*pp_tonga_pcie_table = pcie_table;
-+	}
- 
- 	return 0;
- }
-@@ -668,8 +711,8 @@ static int init_clock_voltage_dependency(
- 	const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
- 		(const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
- 		le16_to_cpu(powerplay_table->usHardLimitTableOffset));
--	const ATOM_Tonga_PCIE_Table *pcie_table =
--		(const ATOM_Tonga_PCIE_Table *)(((unsigned long) powerplay_table) +
-+	const PPTable_Generic_SubTable_Header *pcie_table =
-+		(const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
- 		le16_to_cpu(powerplay_table->usPCIETableOffset));
- 
- 	pp_table_information->vdd_dep_on_sclk = NULL;
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-index f57ba12..6395065 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-@@ -345,7 +345,6 @@ static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t
- 	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
- 	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
- 
--
- 	for (; byte_count >= 4; byte_count -= 4)
- 		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
- 
-@@ -364,6 +363,9 @@ static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
- 	case UCODE_ID_SMU:
- 		result = CGS_UCODE_ID_SMU;
- 		break;
-+	case UCODE_ID_SMU_SK:
-+		result = CGS_UCODE_ID_SMU_SK;
-+		break;
- 	case UCODE_ID_SDMA0:
- 		result = CGS_UCODE_ID_SDMA0;
- 		break;
-@@ -401,14 +403,18 @@ static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
- static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr)
- {
- 	int result = 0;
-+	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
- 
- 	struct cgs_firmware_info info = {0};
- 
--	cgs_get_firmware_info(smumgr->device,
-+	if (smu_data->security_hard_key == 1)
-+		cgs_get_firmware_info(smumgr->device,
- 			ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
-+	else
-+		cgs_get_firmware_info(smumgr->device,
-+			ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
- 
- 	/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
--
- 	result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE);
- 
- 	return result;
-@@ -798,13 +804,11 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
- 						SMU_STATUS, SMU_PASS))
- 		PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
- 
--
- 	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
- 
- 	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--
- 	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
-@@ -860,12 +864,22 @@ static int ellesmere_start_smu(struct pp_smumgr *smumgr)
- 	/* Only start SMC if SMC RAM is not running */
- 	if (!ellesmere_is_smc_ram_running(smumgr)) {
- 		SMU_VFT_INTACT = false;
-+		smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
-+		smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
-+
- 		/* Check if SMU is running in protected mode */
--		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE))
-+		if (smu_data->protected_mode == 0) {
- 			result = ellesmere_start_smu_in_non_protection_mode(smumgr);
--		else
-+		} else {
- 			result = ellesmere_start_smu_in_protection_mode(smumgr);
- 
-+			/* If failed, try with different security Key. */
-+			if (result != 0) {
-+				smu_data->security_hard_key ^= 1;
-+				result = ellesmere_start_smu_in_protection_mode(smumgr);
-+			}
-+		}
-+
- 		if (result != 0)
- 			PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-index 3712b32..05d636a 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-@@ -51,6 +51,8 @@ struct ellesmere_smumgr {
- 	uint32_t read_drm_straps_mc_address_low;
- 	uint32_t acpi_optimization;
- 	bool post_initial_boot;
-+	uint8_t protected_mode;
-+	uint8_t security_hard_key;
- 	struct ellesmere_avfs  avfs;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0937-drm-amd-powerplay-add-all-blocks-clockgating-support.patch b/common/recipes-kernel/linux/files/0937-drm-amd-powerplay-add-all-blocks-clockgating-support.patch
deleted file mode 100644
index 77396154..00000000
--- a/common/recipes-kernel/linux/files/0937-drm-amd-powerplay-add-all-blocks-clockgating-support.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From a3e67c37baba1d9fb9fa3fa3a72fd9dbe9eab346 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 9 Feb 2016 16:26:00 -0500
-Subject: [PATCH 0937/1110] drm/amd/powerplay: add all blocks clockgating
- support through SMU/powerplay
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 81 +++++++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  3 +
- 2 files changed, 84 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 9d22900..9c742e0 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -180,6 +180,87 @@ static void pp_print_status(void *handle)
- static int pp_set_clockgating_state(void *handle,
- 				    enum amd_clockgating_state state)
- {
-+	struct pp_hwmgr  *hwmgr;
-+	uint32_t msg_id, pp_state;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+			hwmgr->hwmgr_func->update_clock_gatings == NULL)
-+			return -EINVAL;
-+
-+	if (state == AMD_CG_STATE_UNGATE)
-+		pp_state = 0;
-+	else
-+		pp_state = PP_STATE_CG | PP_STATE_LS;
-+
-+	/* Enable/disable GFX blocks clock gating through SMU */
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-+			PP_BLOCK_GFX_CG,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-+			PP_BLOCK_GFX_3D,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-+			PP_BLOCK_GFX_RLC,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-+			PP_BLOCK_GFX_CP,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
-+			PP_BLOCK_GFX_MG,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+
-+	/* Enable/disable System blocks clock gating through SMU */
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_BIF,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_BIF,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_MC,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_ROM,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_DRM,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_HDP,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-+			PP_BLOCK_SYS_SDMA,
-+			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-+			pp_state);
-+	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index bbe02ec..e5356cf 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -288,6 +288,9 @@ struct pp_states_info {
- 
- #define PP_BLOCK_GFX_CG         0x01
- #define PP_BLOCK_GFX_MG         0x02
-+#define PP_BLOCK_GFX_3D         0x04
-+#define PP_BLOCK_GFX_RLC        0x08
-+#define PP_BLOCK_GFX_CP         0x10
- #define PP_BLOCK_SYS_BIF        0x01
- #define PP_BLOCK_SYS_MC         0x02
- #define PP_BLOCK_SYS_ROM        0x04
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0938-drm-amd-powerplay-add-GFX-SYS-clockgating-support-fo.patch b/common/recipes-kernel/linux/files/0938-drm-amd-powerplay-add-GFX-SYS-clockgating-support-fo.patch
deleted file mode 100644
index 9b5d14a5..00000000
--- a/common/recipes-kernel/linux/files/0938-drm-amd-powerplay-add-GFX-SYS-clockgating-support-fo.patch
+++ /dev/null
@@ -1,300 +0,0 @@
-From 1385ca339527a381716524984d21e6fe6c9cf280 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 11 Feb 2016 11:09:09 -0500
-Subject: [PATCH 0938/1110] drm/amd/powerplay: add GFX/SYS clockgating support
- for ELM/BAF
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- .../powerplay/hwmgr/ellesmere_clockpowergating.c   | 247 +++++++++++++++++++++
- .../powerplay/hwmgr/ellesmere_clockpowergating.h   |   2 +
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |   1 +
- 3 files changed, 250 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-index 0dee0df..a94f6a8 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-@@ -151,3 +151,250 @@ int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
- 	return 0;
- }
- 
-+int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
-+					const uint32_t *msg_id)
-+{
-+	PPSMC_Msg msg;
-+	uint32_t value;
-+
-+	switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
-+	case PP_GROUP_GFX:
-+		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
-+		case PP_BLOCK_GFX_CG:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+					? PPSMC_MSG_EnableClockGatingFeature
-+					: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_3D:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_3DCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if  (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_3DLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_RLC:
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_RLC_LS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_CP:
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CP_LS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_MG:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK |
-+						CG_GFX_OTHERS_MGCG_MASK);
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		default:
-+			return -1;
-+		}
-+		break;
-+
-+	case PP_GROUP_SYS:
-+		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
-+		case PP_BLOCK_SYS_BIF:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_BIF_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if  (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_BIF_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_MC:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_MC_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_MC_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_DRM:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_DRM_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_DRM_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_HDP:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_HDP_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_HDP_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_SDMA:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_SDMA_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_SDMA_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_ROM:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_ROM_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		default:
-+			return -1;
-+
-+		}
-+		break;
-+
-+	default:
-+		return -1;
-+
-+	}
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-index 56a950e..a90577e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-@@ -33,5 +33,7 @@ int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
- int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
- int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
- int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
-+int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
-+					const uint32_t *msg_id);
- 
- #endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-index 043aefa..c87d5ef 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-@@ -4670,6 +4670,7 @@ static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
- 	.powergate_uvd = ellesmere_phm_powergate_uvd,
- 	.powergate_vce = ellesmere_phm_powergate_vce,
- 	.disable_clock_power_gating = ellesmere_phm_disable_clock_power_gating,
-+	.update_clock_gatings = ellesmere_phm_update_clock_gatings,
- 	.notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment,
- 	.display_config_changed = ellesmere_display_configuration_changed_task,
- 	.set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0939-drm-amd-amdgpu-add-query-GFX-cu-info-in-CGS-query-sy.patch b/common/recipes-kernel/linux/files/0939-drm-amd-amdgpu-add-query-GFX-cu-info-in-CGS-query-sy.patch
deleted file mode 100644
index 860d9f3b..00000000
--- a/common/recipes-kernel/linux/files/0939-drm-amd-amdgpu-add-query-GFX-cu-info-in-CGS-query-sy.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From e38eccb590e15c25d2601c335dde4fc2bbfb93da Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 17 Mar 2016 18:29:08 -0400
-Subject: [PATCH 0939/1110] drm/amd/amdgpu: add query GFX cu info in CGS query
- system info
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Needed for per CU powergating.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 5 +++++
- drivers/gpu/drm/amd/include/cgs_common.h | 1 +
- 2 files changed, 6 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 594159c..e066817 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -791,6 +791,7 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
- 				struct cgs_system_info *sys_info)
- {
- 	CGS_FUNC_ADEV;
-+	struct amdgpu_cu_info cu_info;
- 
- 	if (NULL == sys_info)
- 		return -ENODEV;
-@@ -814,6 +815,10 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
- 	case CGS_SYSTEM_INFO_PG_FLAGS:
- 		sys_info->value = adev->pg_flags;
- 		break;
-+	case CGS_SYSTEM_INFO_GFX_CU_INFO:
-+		amdgpu_asic_get_cu_info(adev, &cu_info);
-+		sys_info->value = cu_info.number;
-+		break;
- 	default:
- 		return -ENODEV;
- 	}
-diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
-index 7a3714b..a461e15 100644
---- a/drivers/gpu/drm/amd/include/cgs_common.h
-+++ b/drivers/gpu/drm/amd/include/cgs_common.h
-@@ -114,6 +114,7 @@ enum cgs_system_info_id {
- 	CGS_SYSTEM_INFO_PCIE_MLW,
- 	CGS_SYSTEM_INFO_CG_FLAGS,
- 	CGS_SYSTEM_INFO_PG_FLAGS,
-+	CGS_SYSTEM_INFO_GFX_CU_INFO,
- 	CGS_SYSTEM_INFO_ID_MAXIMUM,
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0940-drm-amd-powerplay-add-GFX-per-cu-powergating-support.patch b/common/recipes-kernel/linux/files/0940-drm-amd-powerplay-add-GFX-per-cu-powergating-support.patch
deleted file mode 100644
index b441bb5f..00000000
--- a/common/recipes-kernel/linux/files/0940-drm-amd-powerplay-add-GFX-per-cu-powergating-support.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 9a2ebfbb6e70cd50f79b9841a8dc048a34ea6a85 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 11 Feb 2016 15:54:45 -0500
-Subject: [PATCH 0940/1110] drm/amd/powerplay: add GFX per cu powergating
- support through SMU/powerplay
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 ++++++++++++++-
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     |  1 +
- 2 files changed, 15 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 9c742e0..94b7809 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -267,7 +267,20 @@ static int pp_set_clockgating_state(void *handle,
- static int pp_set_powergating_state(void *handle,
- 				    enum amd_powergating_state state)
- {
--	return 0;
-+	struct pp_hwmgr  *hwmgr;
-+
-+	if (handle == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = ((struct pp_instance *)handle)->hwmgr;
-+
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
-+			hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL)
-+				return -EINVAL;
-+
-+	/* Enable/disable GFX per cu powergating through SMU */
-+	return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
-+			state == AMD_PG_STATE_GATE ? true : false);
- }
- 
- static int pp_suspend(void *handle)
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index e1ca36c..12285a9 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -337,6 +337,7 @@ struct pp_hwmgr_func {
- 	int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
- 	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level);
- 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
-+	int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
- };
- 
- struct pp_table_func {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0941-drm-amd-powerplay-add-GFX-per-cu-powergating-for-Baf.patch b/common/recipes-kernel/linux/files/0941-drm-amd-powerplay-add-GFX-per-cu-powergating-for-Baf.patch
deleted file mode 100644
index d16fed0e..00000000
--- a/common/recipes-kernel/linux/files/0941-drm-amd-powerplay-add-GFX-per-cu-powergating-for-Baf.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From c948005590136584455dd5cad2bfc727eff606f4 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 11 Mar 2016 14:53:39 -0500
-Subject: [PATCH 0941/1110] drm/amd/powerplay: add GFX per cu powergating for
- Baffin
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- .../powerplay/hwmgr/ellesmere_clockpowergating.c   | 28 ++++++++++++++++++++++
- .../powerplay/hwmgr/ellesmere_clockpowergating.h   |  1 +
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  5 ++++
- 3 files changed, 34 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-index a94f6a8..93db824 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-@@ -398,3 +398,31 @@ int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
- 
- 	return 0;
- }
-+
-+/* This function is for Baffin only for now,
-+ * Powerplay will only control the static per CU Power Gating.
-+ * Dynamic per CU Power Gating will be done in gfx.
-+ */
-+int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	struct cgs_system_info sys_info = {0};
-+	uint32_t active_cus;
-+	int result;
-+
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
-+
-+	result = cgs_query_system_info(hwmgr->device, &sys_info);
-+
-+	if (result)
-+		return -EINVAL;
-+	else
-+		active_cus = sys_info.value;
-+
-+	if (enable)
-+		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
-+	else
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_GFX_CU_PG_DISABLE);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-index a90577e..b403e11 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-@@ -35,5 +35,6 @@ int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
- int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
- int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
- 					const uint32_t *msg_id);
-+int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
- 
- #endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-index c87d5ef..152d77d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-@@ -4687,6 +4687,11 @@ static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
- 	.register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt,
- 	.check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration,
- 	.check_states_equal = ellesmere_check_states_equal,
-+	.get_pp_table = ellesmere_get_pp_table,
-+	.set_pp_table = ellesmere_set_pp_table,
-+	.force_clock_level = ellesmere_force_clock_level,
-+	.print_clock_levels = ellesmere_print_clock_levels,
-+	.enable_per_cu_power_gating = ellesmere_phm_enable_per_cu_power_gating,
- };
- 
- int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0942-drm-amd-amdgpu-add-medium-grain-powergating-support-.patch b/common/recipes-kernel/linux/files/0942-drm-amd-amdgpu-add-medium-grain-powergating-support-.patch
deleted file mode 100644
index 7e5bc234..00000000
--- a/common/recipes-kernel/linux/files/0942-drm-amd-amdgpu-add-medium-grain-powergating-support-.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 6a27d706098d2889ce342448617cdcf01bbfd8b6 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 12 Feb 2016 10:58:51 -0500
-Subject: [PATCH 0942/1110] drm/amd/amdgpu: add medium grain powergating
- support for Baffin
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 95 +++++++++++++++++++++++++++++++++++
- 1 file changed, 95 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 75a76f4..17391b8 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4393,6 +4393,9 @@ static int gfx_v8_0_hw_fini(void *handle)
- 	gfx_v8_0_rlc_stop(adev);
- 	gfx_v8_0_cp_compute_fini(adev);
- 
-+	amdgpu_set_powergating_state(adev,
-+			AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
-+
- 	return 0;
- }
- 
-@@ -4821,12 +4824,104 @@ static int gfx_v8_0_late_init(void *handle)
- 	if (r)
- 		return r;
- 
-+	amdgpu_set_powergating_state(adev,
-+			AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
-+
- 	return 0;
- }
- 
-+static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t data, temp;
-+
-+	/* Send msg to SMU via Powerplay */
-+	amdgpu_set_powergating_state(adev,
-+			AMD_IP_BLOCK_TYPE_SMC,
-+			enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
-+
-+	if (enable) {
-+		/* Enable static MGPG */
-+		temp = data = RREG32(mmRLC_PG_CNTL);
-+		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmRLC_PG_CNTL, data);
-+	} else {
-+		temp = data = RREG32(mmRLC_PG_CNTL);
-+		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmRLC_PG_CNTL, data);
-+	}
-+}
-+
-+static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t data, temp;
-+
-+	if (enable) {
-+		/* Enable dynamic MGPG */
-+		temp = data = RREG32(mmRLC_PG_CNTL);
-+		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmRLC_PG_CNTL, data);
-+	} else {
-+		temp = data = RREG32(mmRLC_PG_CNTL);
-+		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+
-+		if (temp != data)
-+			WREG32(mmRLC_PG_CNTL, data);
-+	}
-+}
-+
-+static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
-+		bool enable)
-+{
-+	uint32_t data, temp;
-+
-+	if (enable) {
-+		/* Enable quick PG */
-+		temp = data = RREG32(mmRLC_PG_CNTL);
-+		data |= 0x100000;
-+
-+		if (temp != data)
-+			WREG32(mmRLC_PG_CNTL, data);
-+	} else {
-+		temp = data = RREG32(mmRLC_PG_CNTL);
-+		data &= ~0x100000;
-+
-+		if (temp != data)
-+			WREG32(mmRLC_PG_CNTL, data);
-+	}
-+}
-+
- static int gfx_v8_0_set_powergating_state(void *handle,
- 					  enum amd_powergating_state state)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
-+		return 0;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_BAFFIN:
-+		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)
-+			baffin_enable_gfx_static_mg_power_gating(adev,
-+					state == AMD_PG_STATE_GATE ? true : false);
-+		else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)
-+			baffin_enable_gfx_dynamic_mg_power_gating(adev,
-+					state == AMD_PG_STATE_GATE ? true : false);
-+		else
-+			baffin_enable_gfx_quick_mg_power_gating(adev,
-+					state == AMD_PG_STATE_GATE ? true : false);
-+		break;
-+	default:
-+		break;
-+	}
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0943-drm-amd-powerplay-add-default-clockgating-handling.patch b/common/recipes-kernel/linux/files/0943-drm-amd-powerplay-add-default-clockgating-handling.patch
deleted file mode 100644
index 3b224197..00000000
--- a/common/recipes-kernel/linux/files/0943-drm-amd-powerplay-add-default-clockgating-handling.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 9ccec0e41eb87aa3e2711993518da784d395099c Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Mon, 15 Feb 2016 15:45:59 +0800
-Subject: [PATCH 0943/1110] drm/amd/powerplay: add default clockgating handling
-
-This is to workaround regression introduced in
-46c34bcb6a15dd85329a39a5e72c62108626acdc. It should be reverted with a
-final fix.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 94b7809..32a6a6f 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -188,10 +188,12 @@ static int pp_set_clockgating_state(void *handle,
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--			hwmgr->hwmgr_func->update_clock_gatings == NULL)
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
- 			return -EINVAL;
- 
-+	if (hwmgr->hwmgr_func->update_clock_gatings == NULL)
-+		return 0;
-+
- 	if (state == AMD_CG_STATE_UNGATE)
- 		pp_state = 0;
- 	else
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0944-drm-amd-amdgpu-add-power-gating-initialization-suppo.patch b/common/recipes-kernel/linux/files/0944-drm-amd-amdgpu-add-power-gating-initialization-suppo.patch
deleted file mode 100644
index af31e77a..00000000
--- a/common/recipes-kernel/linux/files/0944-drm-amd-amdgpu-add-power-gating-initialization-suppo.patch
+++ /dev/null
@@ -1,461 +0,0 @@
-From 6530781feecc3ea8bdb603b0978abaabea82cb4a Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 14 Apr 2016 17:26:07 -0400
-Subject: [PATCH 0944/1110] drm/amd/amdgpu: add power gating initialization
- support for GFX8.0
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  14 ++
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 353 +++++++++++++++++++++++++++++++++-
- 2 files changed, 364 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1b22de0..a8c59be 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1082,6 +1082,20 @@ struct amdgpu_rlc {
- 	/* safe mode for updating CG/PG state */
- 	bool in_safe_mode;
- 	const struct amdgpu_rlc_funcs *funcs;
-+
-+	/* for firmware data */
-+	u32 save_and_restore_offset;
-+	u32 clear_state_descriptor_offset;
-+	u32 avail_scratch_ram_locations;
-+	u32 reg_restore_list_size;
-+	u32 reg_list_format_start;
-+	u32 reg_list_format_separate_start;
-+	u32 starting_offsets_start;
-+	u32 reg_list_format_size_bytes;
-+	u32 reg_list_size_bytes;
-+
-+	u32 *register_list_format;
-+	u32 *register_restore;
- };
- 
- struct amdgpu_mec {
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 17391b8..3fdce2d 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -86,6 +86,8 @@ enum {
- 	BPM_REG_FGCG_MAX
- };
- 
-+#define RLC_FormatDirectRegListLength        14
-+
- MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
- MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
- MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
-@@ -633,6 +635,7 @@ static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
- static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
- static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
- static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
-+static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
- 
- static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
- {
-@@ -838,6 +841,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
- 	struct amdgpu_firmware_info *info = NULL;
- 	const struct common_firmware_header *header = NULL;
- 	const struct gfx_firmware_header_v1_0 *cp_hdr;
-+	const struct rlc_firmware_header_v2_0 *rlc_hdr;
-+	unsigned int *tmp = NULL, i;
- 
- 	DRM_DEBUG("\n");
- 
-@@ -905,9 +910,49 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
- 	if (err)
- 		goto out;
- 	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
--	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
--	adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
--	adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
-+	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
-+	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
-+	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
-+
-+	adev->gfx.rlc.save_and_restore_offset =
-+			le32_to_cpu(rlc_hdr->save_and_restore_offset);
-+	adev->gfx.rlc.clear_state_descriptor_offset =
-+			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
-+	adev->gfx.rlc.avail_scratch_ram_locations =
-+			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
-+	adev->gfx.rlc.reg_restore_list_size =
-+			le32_to_cpu(rlc_hdr->reg_restore_list_size);
-+	adev->gfx.rlc.reg_list_format_start =
-+			le32_to_cpu(rlc_hdr->reg_list_format_start);
-+	adev->gfx.rlc.reg_list_format_separate_start =
-+			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
-+	adev->gfx.rlc.starting_offsets_start =
-+			le32_to_cpu(rlc_hdr->starting_offsets_start);
-+	adev->gfx.rlc.reg_list_format_size_bytes =
-+			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
-+	adev->gfx.rlc.reg_list_size_bytes =
-+			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
-+
-+	adev->gfx.rlc.register_list_format =
-+			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
-+					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
-+
-+	if (!adev->gfx.rlc.register_list_format) {
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
-+	tmp = (unsigned int *)((uint64_t)rlc_hdr +
-+			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
-+	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
-+		adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
-+
-+	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
-+
-+	tmp = (unsigned int *)((uint64_t)rlc_hdr +
-+			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
-+	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
-+		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
- 
- 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
- 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
-@@ -1008,6 +1053,148 @@ out:
- 	return err;
- }
- 
-+static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
-+				    volatile u32 *buffer)
-+{
-+	u32 count = 0, i;
-+	const struct cs_section_def *sect = NULL;
-+	const struct cs_extent_def *ext = NULL;
-+
-+	if (adev->gfx.rlc.cs_data == NULL)
-+		return;
-+	if (buffer == NULL)
-+		return;
-+
-+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
-+	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
-+
-+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
-+	buffer[count++] = cpu_to_le32(0x80000000);
-+	buffer[count++] = cpu_to_le32(0x80000000);
-+
-+	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
-+		for (ext = sect->section; ext->extent != NULL; ++ext) {
-+			if (sect->id == SECT_CONTEXT) {
-+				buffer[count++] =
-+					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
-+				buffer[count++] = cpu_to_le32(ext->reg_index -
-+						PACKET3_SET_CONTEXT_REG_START);
-+				for (i = 0; i < ext->reg_count; i++)
-+					buffer[count++] = cpu_to_le32(ext->extent[i]);
-+			} else {
-+				return;
-+			}
-+		}
-+	}
-+
-+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-+	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
-+			PACKET3_SET_CONTEXT_REG_START);
-+	switch (adev->asic_type) {
-+	case CHIP_TONGA:
-+		buffer[count++] = cpu_to_le32(0x16000012);
-+		buffer[count++] = cpu_to_le32(0x0000002A);
-+		break;
-+	case CHIP_FIJI:
-+		buffer[count++] = cpu_to_le32(0x3a00161a);
-+		buffer[count++] = cpu_to_le32(0x0000002e);
-+		break;
-+	case CHIP_TOPAZ:
-+	case CHIP_CARRIZO:
-+		buffer[count++] = cpu_to_le32(0x00000002);
-+		buffer[count++] = cpu_to_le32(0x00000000);
-+		break;
-+	case CHIP_STONEY:
-+		buffer[count++] = cpu_to_le32(0x00000000);
-+		buffer[count++] = cpu_to_le32(0x00000000);
-+		break;
-+	default:
-+		buffer[count++] = cpu_to_le32(0x00000000);
-+		buffer[count++] = cpu_to_le32(0x00000000);
-+		break;
-+	}
-+
-+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
-+	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
-+
-+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
-+	buffer[count++] = cpu_to_le32(0);
-+}
-+
-+static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
-+{
-+	int r;
-+
-+	/* clear state block */
-+	if (adev->gfx.rlc.clear_state_obj) {
-+		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
-+		if (unlikely(r != 0))
-+			dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
-+		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
-+		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
-+
-+		amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
-+		adev->gfx.rlc.clear_state_obj = NULL;
-+	}
-+}
-+
-+static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
-+{
-+	volatile u32 *dst_ptr;
-+	u32 dws;
-+	const struct cs_section_def *cs_data;
-+	int r;
-+
-+	adev->gfx.rlc.cs_data = vi_cs_data;
-+
-+	cs_data = adev->gfx.rlc.cs_data;
-+
-+	if (cs_data) {
-+		/* clear state block */
-+		adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
-+
-+		if (adev->gfx.rlc.clear_state_obj == NULL) {
-+			r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
-+					     AMDGPU_GEM_DOMAIN_VRAM,
-+					     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
-+					     NULL, NULL,
-+					     &adev->gfx.rlc.clear_state_obj);
-+			if (r) {
-+				dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
-+				gfx_v8_0_rlc_fini(adev);
-+				return r;
-+			}
-+		}
-+		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
-+		if (unlikely(r != 0)) {
-+			gfx_v8_0_rlc_fini(adev);
-+			return r;
-+		}
-+		r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
-+				  &adev->gfx.rlc.clear_state_gpu_addr);
-+		if (r) {
-+			amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
-+			dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
-+			gfx_v8_0_rlc_fini(adev);
-+			return r;
-+		}
-+
-+		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
-+		if (r) {
-+			dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
-+			gfx_v8_0_rlc_fini(adev);
-+			return r;
-+		}
-+		/* set up the cs buffer */
-+		dst_ptr = adev->gfx.rlc.cs_ptr;
-+		gfx_v8_0_get_csb_buffer(adev, dst_ptr);
-+		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
-+		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
-+	}
-+
-+	return 0;
-+}
-+
- static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
- {
- 	int r;
-@@ -1681,6 +1868,12 @@ static int gfx_v8_0_sw_init(void *handle)
- 		return r;
- 	}
- 
-+	r = gfx_v8_0_rlc_init(adev);
-+	if (r) {
-+		DRM_ERROR("Failed to init rlc BOs!\n");
-+		return r;
-+	}
-+
- 	r = gfx_v8_0_mec_init(adev);
- 	if (r) {
- 		DRM_ERROR("Failed to init MEC BOs!\n");
-@@ -1780,6 +1973,10 @@ static int gfx_v8_0_sw_fini(void *handle)
- 
- 	gfx_v8_0_mec_fini(adev);
- 
-+	gfx_v8_0_rlc_fini(adev);
-+
-+	kfree(adev->gfx.rlc.register_list_format);
-+
- 	return 0;
- }
- 
-@@ -3322,6 +3519,154 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
- 	WREG32(mmCP_INT_CNTL_RING0, tmp);
- }
- 
-+static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
-+{
-+	/* csib */
-+	WREG32(mmRLC_CSIB_ADDR_HI,
-+			adev->gfx.rlc.clear_state_gpu_addr >> 32);
-+	WREG32(mmRLC_CSIB_ADDR_LO,
-+			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
-+	WREG32(mmRLC_CSIB_LENGTH,
-+			adev->gfx.rlc.clear_state_size);
-+}
-+
-+static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
-+				int ind_offset,
-+				int list_size,
-+				int *unique_indices,
-+				int *indices_count,
-+				int max_indices,
-+				int *ind_start_offsets,
-+				int *offset_count,
-+				int max_offset)
-+{
-+	int indices;
-+	bool new_entry = true;
-+
-+	for (; ind_offset < list_size; ind_offset++) {
-+
-+		if (new_entry) {
-+			new_entry = false;
-+			ind_start_offsets[*offset_count] = ind_offset;
-+			*offset_count = *offset_count + 1;
-+			BUG_ON(*offset_count >= max_offset);
-+		}
-+
-+		if (register_list_format[ind_offset] == 0xFFFFFFFF) {
-+			new_entry = true;
-+			continue;
-+		}
-+
-+		ind_offset += 2;
-+
-+		/* look for the matching indice */
-+		for (indices = 0;
-+			indices < *indices_count;
-+			indices++) {
-+			if (unique_indices[indices] ==
-+				register_list_format[ind_offset])
-+				break;
-+		}
-+
-+		if (indices >= *indices_count) {
-+			unique_indices[*indices_count] =
-+				register_list_format[ind_offset];
-+			indices = *indices_count;
-+			*indices_count = *indices_count + 1;
-+			BUG_ON(*indices_count >= max_indices);
-+		}
-+
-+		register_list_format[ind_offset] = indices;
-+	}
-+}
-+
-+static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
-+{
-+	int i, temp, data;
-+	int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
-+	int indices_count = 0;
-+	int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-+	int offset_count = 0;
-+
-+	int list_size;
-+	unsigned int *register_list_format =
-+		kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
-+	if (register_list_format == NULL)
-+		return -ENOMEM;
-+	memcpy(register_list_format, adev->gfx.rlc.register_list_format,
-+			adev->gfx.rlc.reg_list_format_size_bytes);
-+
-+	gfx_v8_0_parse_ind_reg_list(register_list_format,
-+				RLC_FormatDirectRegListLength,
-+				adev->gfx.rlc.reg_list_format_size_bytes >> 2,
-+				unique_indices,
-+				&indices_count,
-+				sizeof(unique_indices) / sizeof(int),
-+				indirect_start_offsets,
-+				&offset_count,
-+				sizeof(indirect_start_offsets)/sizeof(int));
-+
-+	/* save and restore list */
-+	temp = RREG32(mmRLC_SRM_CNTL);
-+	temp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
-+	WREG32(mmRLC_SRM_CNTL, temp);
-+
-+	WREG32(mmRLC_SRM_ARAM_ADDR, 0);
-+	for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
-+		WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
-+
-+	/* indirect list */
-+	WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
-+	for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
-+		WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
-+
-+	list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
-+	list_size = list_size >> 1;
-+	WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
-+	WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
-+
-+	/* starting offsets starts */
-+	WREG32(mmRLC_GPM_SCRATCH_ADDR,
-+		adev->gfx.rlc.starting_offsets_start);
-+	for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
-+		WREG32(mmRLC_GPM_SCRATCH_DATA,
-+				indirect_start_offsets[i]);
-+
-+	/* unique indices */
-+	temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
-+	data = mmRLC_SRM_INDEX_CNTL_DATA_0;
-+	for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-+		amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
-+		amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
-+	}
-+	kfree(register_list_format);
-+
-+	return 0;
-+}
-+
-+static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
-+{
-+	uint32_t data;
-+
-+	data = RREG32(mmRLC_SRM_CNTL);
-+	data |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
-+	WREG32(mmRLC_SRM_CNTL, data);
-+}
-+
-+static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
-+{
-+	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-+			      AMD_PG_SUPPORT_GFX_SMG |
-+			      AMD_PG_SUPPORT_GFX_DMG |
-+			      AMD_PG_SUPPORT_CP |
-+			      AMD_PG_SUPPORT_GDS |
-+			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
-+		gfx_v8_0_init_csb(adev);
-+		gfx_v8_0_init_save_restore_list(adev);
-+		gfx_v8_0_enable_save_restore_machine(adev);
-+	}
-+}
-+
- void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
- {
- 	u32 tmp = RREG32(mmRLC_CNTL);
-@@ -3401,6 +3746,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
- 
- 	gfx_v8_0_rlc_reset(adev);
- 
-+	gfx_v8_0_init_pg(adev);
-+
- 	if (!adev->pp_enabled) {
- 		if (!adev->firmware.smu_load) {
- 			/* legacy rlc firmware loading */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0945-drm-amd-amdgpu-add-power-gating-init-for-Baffin.patch b/common/recipes-kernel/linux/files/0945-drm-amd-amdgpu-add-power-gating-init-for-Baffin.patch
deleted file mode 100644
index 92939e18..00000000
--- a/common/recipes-kernel/linux/files/0945-drm-amd-amdgpu-add-power-gating-init-for-Baffin.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 3ea4bbeab61e874a7c1577f0528c23dc1c33bd6b Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 16 Feb 2016 17:33:14 -0500
-Subject: [PATCH 0945/1110] drm/amd/amdgpu: add power gating init for Baffin
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 39 +++++++++++++++++++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 3fdce2d..4cd0d19 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1092,9 +1092,14 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
- 			PACKET3_SET_CONTEXT_REG_START);
- 	switch (adev->asic_type) {
- 	case CHIP_TONGA:
-+	case CHIP_ELLESMERE:
- 		buffer[count++] = cpu_to_le32(0x16000012);
- 		buffer[count++] = cpu_to_le32(0x0000002A);
- 		break;
-+	case CHIP_BAFFIN:
-+		buffer[count++] = cpu_to_le32(0x16000012);
-+		buffer[count++] = cpu_to_le32(0x00000000);
-+		break;
- 	case CHIP_FIJI:
- 		buffer[count++] = cpu_to_le32(0x3a00161a);
- 		buffer[count++] = cpu_to_le32(0x0000002e);
-@@ -3653,6 +3658,37 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
- 	WREG32(mmRLC_SRM_CNTL, data);
- }
- 
-+static void baffin_init_power_gating(struct amdgpu_device *adev)
-+{
-+	uint32_t data;
-+
-+	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-+			AMD_PG_SUPPORT_GFX_SMG |
-+			AMD_PG_SUPPORT_GFX_DMG)) {
-+		data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
-+		data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
-+		data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
-+		WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
-+
-+		data = 0;
-+		data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
-+		data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
-+		data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
-+		data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
-+		WREG32(mmRLC_PG_DELAY, data);
-+
-+		data = RREG32(mmRLC_PG_DELAY_2);
-+		data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
-+		data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
-+		WREG32(mmRLC_PG_DELAY_2, data);
-+
-+		data = RREG32(mmRLC_AUTO_PG_CTRL);
-+		data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
-+		data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
-+		WREG32(mmRLC_AUTO_PG_CTRL, data);
-+	}
-+}
-+
- static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
- {
- 	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-@@ -3664,6 +3700,9 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
- 		gfx_v8_0_init_csb(adev);
- 		gfx_v8_0_init_save_restore_list(adev);
- 		gfx_v8_0_enable_save_restore_machine(adev);
-+
-+		if (adev->asic_type == CHIP_BAFFIN)
-+			baffin_init_power_gating(adev);
- 	}
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0946-drm-amdgpu-ungate-SMC-clockgating-first-before-suspe.patch b/common/recipes-kernel/linux/files/0946-drm-amdgpu-ungate-SMC-clockgating-first-before-suspe.patch
deleted file mode 100644
index f68fb12e..00000000
--- a/common/recipes-kernel/linux/files/0946-drm-amdgpu-ungate-SMC-clockgating-first-before-suspe.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 92c26f2d88d2eb5330b6ff3d478f30e2fe539c5a Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Fri, 26 Feb 2016 10:45:25 +0800
-Subject: [PATCH 0946/1110] drm/amdgpu: ungate SMC clockgating first before
- suspend
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-46c34bcb6a15dd85329a39a5e72c62108626acdc put all block’s clockgating
-support in SMC. The sequence in suspend routine should be adjusted
-accordingly, otherwise it causes asic hang.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 42d0efd..7d91a69 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1343,14 +1343,23 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
- {
- 	int i, r;
- 
-+	/* ungate SMC block first */
-+	r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
-+					 AMD_CG_STATE_UNGATE);
-+	if (r) {
-+		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
-+	}
-+
- 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
- 		if (!adev->ip_block_status[i].valid)
- 			continue;
- 		/* ungate blocks so that suspend can properly shut them down */
--		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
--								    AMD_CG_STATE_UNGATE);
--		if (r) {
--			DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
-+		if (i != AMD_IP_BLOCK_TYPE_SMC) {
-+			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
-+									    AMD_CG_STATE_UNGATE);
-+			if (r) {
-+				DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
-+			}
- 		}
- 		/* XXX handle errors */
- 		r = adev->ip_blocks[i].funcs->suspend(adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0947-drm-amdgpu-update-the-core-VI-support-for-ELM-BAF.patch b/common/recipes-kernel/linux/files/0947-drm-amdgpu-update-the-core-VI-support-for-ELM-BAF.patch
deleted file mode 100644
index 9d9abb1a..00000000
--- a/common/recipes-kernel/linux/files/0947-drm-amdgpu-update-the-core-VI-support-for-ELM-BAF.patch
+++ /dev/null
@@ -1,154 +0,0 @@
-From be926a35cfaa56629e4d6ef58966eab59c38c97c Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Mon, 7 Dec 2015 18:33:10 +0800
-Subject: [PATCH 0947/1110] drm/amdgpu: update the core VI support for ELM/BAF
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +
- drivers/gpu/drm/amd/amdgpu/vi.c            | 87 ++++++++++++++++++++++++++++++
- 2 files changed, 89 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 7d91a69..51703e7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1153,6 +1153,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
- 	case CHIP_TOPAZ:
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
-+	case CHIP_BAFFIN:
-+	case CHIP_ELLESMERE:
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
- 		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index fc02cad..8e0e014 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -277,6 +277,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
- 						 stoney_mgcg_cgcg_init,
- 						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
- 		break;
-+	case CHIP_BAFFIN:
-+	case CHIP_ELLESMERE:
- 	default:
- 		break;
- 	}
-@@ -538,6 +540,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
- 		break;
- 	case CHIP_FIJI:
- 	case CHIP_TONGA:
-+	case CHIP_BAFFIN:
-+	case CHIP_ELLESMERE:
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
- 		asic_register_table = cz_allowed_read_registers;
-@@ -908,6 +912,74 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
- 	},
- };
- 
-+static const struct amdgpu_ip_block_version baffin_ip_blocks[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vi_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 8,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &gmc_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 3,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &tonga_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 7,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 11,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &dce_v11_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gfx_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 3,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &sdma_v3_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 6,
-+		.minor = 3,
-+		.rev = 0,
-+		.funcs = &uvd_v6_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 3,
-+		.minor = 4,
-+		.rev = 0,
-+		.funcs = &vce_v3_0_ip_funcs,
-+	},
-+};
-+
- static const struct amdgpu_ip_block_version cz_ip_blocks[] =
- {
- 	/* ORDER MATTERS! */
-@@ -1239,6 +1311,11 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
- #endif
- 		break;
-+	case CHIP_BAFFIN:
-+	case CHIP_ELLESMERE:
-+		adev->ip_blocks = baffin_ip_blocks;
-+		adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks);
-+		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
- #if defined(CONFIG_DRM_AMD_DAL)
-@@ -1350,6 +1427,16 @@ static int vi_common_early_init(void *handle)
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
-+	case CHIP_BAFFIN:
-+		adev->cg_flags = 0;
-+		adev->pg_flags = 0;
-+		adev->external_rev_id = adev->rev_id + 0x5A;
-+		break;
-+	case CHIP_ELLESMERE:
-+		adev->cg_flags = 0;
-+		adev->pg_flags = 0;
-+		adev->external_rev_id = adev->rev_id + 0x50;
-+		break;
- 	case CHIP_CARRIZO:
- 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
- 			AMD_CG_SUPPORT_GFX_MGLS |
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0948-drm-amdgpu-add-ELM-BAF-pci-ids.patch b/common/recipes-kernel/linux/files/0948-drm-amdgpu-add-ELM-BAF-pci-ids.patch
deleted file mode 100644
index 8a6ffc7b..00000000
--- a/common/recipes-kernel/linux/files/0948-drm-amdgpu-add-ELM-BAF-pci-ids.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 73ec2bca3fea76a6ce06b8a29a0bfced99f45ce1 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Thu, 29 Oct 2015 17:32:11 +0800
-Subject: [PATCH 0948/1110] drm/amdgpu: add ELM/BAF pci ids
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 3dc354b..7cb8118 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -281,6 +281,16 @@ static const struct pci_device_id pciidlist[] = {
- 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
- 	/* stoney */
- 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
-+	/* Baffin */
-+	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-+	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-+	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-+	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-+	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-+	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-+	/* Ellesmere */
-+	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
-+	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
- 
- 	{0, 0, 0}
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0949-drm-amdgpu-change-ELM-BAF-to-Polaris10-Polaris11.patch b/common/recipes-kernel/linux/files/0949-drm-amdgpu-change-ELM-BAF-to-Polaris10-Polaris11.patch
deleted file mode 100644
index 1b45531a..00000000
--- a/common/recipes-kernel/linux/files/0949-drm-amdgpu-change-ELM-BAF-to-Polaris10-Polaris11.patch
+++ /dev/null
@@ -1,38194 +0,0 @@
-From 4f67f6f7f0a5a267d342bdf8ce7146a6ca04e0ac Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Mon, 14 Mar 2016 18:33:29 -0400
-Subject: [PATCH 0949/1110] drm/amdgpu: change ELM/BAF to Polaris10/Polaris11
-
-Adjust to preferred code names.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c            |    16 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c         |     8 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            |    20 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c      |     6 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c            |    16 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c            |    16 +-
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c             |    36 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              |   116 +-
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c              |    28 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c             |    32 +-
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c              |     6 +-
- drivers/gpu/drm/amd/amdgpu/vi.c                    |    22 +-
- drivers/gpu/drm/amd/include/amd_shared.h           |     4 +-
- drivers/gpu/drm/amd/include/atombios.h             |     6 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile       |     4 +-
- .../powerplay/hwmgr/ellesmere_clockpowergating.c   |   428 -
- .../powerplay/hwmgr/ellesmere_clockpowergating.h   |    40 -
- .../amd/powerplay/hwmgr/ellesmere_dyn_defaults.h   |    62 -
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c  |  4711 ---------
- .../gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h  |   354 -
- .../drm/amd/powerplay/hwmgr/ellesmere_powertune.c  |   396 -
- .../drm/amd/powerplay/hwmgr/ellesmere_powertune.h  |    70 -
- .../drm/amd/powerplay/hwmgr/ellesmere_thermal.c    |   711 --
- .../drm/amd/powerplay/hwmgr/ellesmere_thermal.h    |    62 -
- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |     8 +-
- .../powerplay/hwmgr/polaris10_clockpowergating.c   |   428 +
- .../powerplay/hwmgr/polaris10_clockpowergating.h   |    40 +
- .../amd/powerplay/hwmgr/polaris10_dyn_defaults.h   |    62 +
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  4844 +++++++++
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h  |   354 +
- .../drm/amd/powerplay/hwmgr/polaris10_powertune.c  |   396 +
- .../drm/amd/powerplay/hwmgr/polaris10_powertune.h  |    70 +
- .../drm/amd/powerplay/hwmgr/polaris10_thermal.c    |   711 ++
- .../drm/amd/powerplay/hwmgr/polaris10_thermal.h    |    62 +
- .../gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h    |    10 +-
- .../amd/powerplay/hwmgr/tonga_processpptables.c    |     4 +-
- .../gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h    |   401 -
- .../gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h | 10088 -------------------
- .../gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h    |   409 +
- .../gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h | 10088 +++++++++++++++++++
- drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h |    42 +
- drivers/gpu/drm/amd/powerplay/smumgr/Makefile      |     2 +-
- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.c    |   983 --
- .../drm/amd/powerplay/smumgr/ellesmere_smumgr.h    |    68 -
- .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |   983 ++
- .../drm/amd/powerplay/smumgr/polaris10_smumgr.h    |    68 +
- drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |     8 +-
- 47 files changed, 18742 insertions(+), 18557 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
- delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
- delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
- delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
- create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index e066817..837cdd2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -681,8 +681,8 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
- 		result = AMDGPU_UCODE_ID_CP_MEC1;
- 		break;
- 	case CGS_UCODE_ID_CP_MEC_JT2:
--		if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_BAFFIN
--		  || adev->asic_type == CHIP_ELLESMERE)
-+		if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11
-+		  || adev->asic_type == CHIP_POLARIS10)
- 			result = AMDGPU_UCODE_ID_CP_MEC2;
- 		else
- 			result = AMDGPU_UCODE_ID_CP_MEC1;
-@@ -742,17 +742,17 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
- 		case CHIP_FIJI:
- 			strcpy(fw_name, "amdgpu/fiji_smc.bin");
- 			break;
--		case CHIP_BAFFIN:
-+		case CHIP_POLARIS11:
- 			if (type == CGS_UCODE_ID_SMU)
--				strcpy(fw_name, "amdgpu/baffin_smc.bin");
-+				strcpy(fw_name, "amdgpu/polaris11_smc.bin");
- 			else if (type == CGS_UCODE_ID_SMU_SK)
--				strcpy(fw_name, "amdgpu/baffin_smc_sk.bin");
-+				strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
- 			break;
--		case CHIP_ELLESMERE:
-+		case CHIP_POLARIS10:
- 			if (type == CGS_UCODE_ID_SMU)
--				strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
-+				strcpy(fw_name, "amdgpu/polaris10_smc.bin");
- 			else if (type == CGS_UCODE_ID_SMU_SK)
--				strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin");
-+				strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
- 			break;
- 		default:
- 			DRM_ERROR("SMC firmware not supported\n");
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 51703e7..b73533d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -61,8 +61,8 @@ static const char *amdgpu_asic_name[] = {
- 	"FIJI",
- 	"CARRIZO",
- 	"STONEY",
--	"ELLESMERE",
--	"BAFFIN",
-+	"POLARIS10",
-+	"POLARIS11",
- 	"LAST",
- };
- 
-@@ -1153,8 +1153,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
- 	case CHIP_TOPAZ:
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
--	case CHIP_BAFFIN:
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
- 		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 7cb8118..30e8c46 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -281,16 +281,16 @@ static const struct pci_device_id pciidlist[] = {
- 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
- 	/* stoney */
- 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
--	/* Baffin */
--	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
--	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
--	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
--	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
--	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
--	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
--	/* Ellesmere */
--	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
--	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
-+	/* Polaris11 */
-+	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-+	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-+	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-+	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-+	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-+	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-+	/* Polaris10 */
-+	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
-+	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
- 
- 	{0, 0, 0}
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index ea2006a..f315995 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -99,10 +99,12 @@ static int amdgpu_pp_early_init(void *handle)
- 
- #ifdef CONFIG_DRM_AMD_POWERPLAY
- 	switch (adev->asic_type) {
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
-+		adev->pp_enabled = true;
-+		break;
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
--	case CHIP_BAFFIN:
--	case CHIP_ELLESMERE:
- 		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
- 		break;
- 	case CHIP_CARRIZO:
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 239b764..b5b5ff3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -54,8 +54,8 @@
- #define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"
- #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
- #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
--#define FIRMWARE_ELLESMERE	"amdgpu/ellesmere_uvd.bin"
--#define FIRMWARE_BAFFIN         "amdgpu/baffin_uvd.bin"
-+#define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
-+#define FIRMWARE_POLARIS11         "amdgpu/polaris11_uvd.bin"
- 
- /**
-  * amdgpu_uvd_cs_ctx - Command submission parser context
-@@ -87,8 +87,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA);
- MODULE_FIRMWARE(FIRMWARE_CARRIZO);
- MODULE_FIRMWARE(FIRMWARE_FIJI);
- MODULE_FIRMWARE(FIRMWARE_STONEY);
--MODULE_FIRMWARE(FIRMWARE_ELLESMERE);
--MODULE_FIRMWARE(FIRMWARE_BAFFIN);
-+MODULE_FIRMWARE(FIRMWARE_POLARIS10);
-+MODULE_FIRMWARE(FIRMWARE_POLARIS11);
- 
- static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
- static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
-@@ -135,11 +135,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- 	case CHIP_STONEY:
- 		fw_name = FIRMWARE_STONEY;
- 		break;
--	case CHIP_ELLESMERE:
--		fw_name = FIRMWARE_ELLESMERE;
-+	case CHIP_POLARIS10:
-+		fw_name = FIRMWARE_POLARIS10;
- 		break;
--	case CHIP_BAFFIN:
--		fw_name = FIRMWARE_BAFFIN;
-+	case CHIP_POLARIS11:
-+		fw_name = FIRMWARE_POLARIS11;
- 		break;
- 	default:
- 		return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 2904842..199f5cb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -50,8 +50,8 @@
- #define FIRMWARE_CARRIZO	"amdgpu/carrizo_vce.bin"
- #define FIRMWARE_FIJI		"amdgpu/fiji_vce.bin"
- #define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"
--#define FIRMWARE_ELLESMERE	"amdgpu/ellesmere_vce.bin"
--#define FIRMWARE_BAFFIN         "amdgpu/baffin_vce.bin"
-+#define FIRMWARE_POLARIS10	"amdgpu/polaris10_vce.bin"
-+#define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
- 
- #ifdef CONFIG_DRM_AMDGPU_CIK
- MODULE_FIRMWARE(FIRMWARE_BONAIRE);
-@@ -64,8 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA);
- MODULE_FIRMWARE(FIRMWARE_CARRIZO);
- MODULE_FIRMWARE(FIRMWARE_FIJI);
- MODULE_FIRMWARE(FIRMWARE_STONEY);
--MODULE_FIRMWARE(FIRMWARE_ELLESMERE);
--MODULE_FIRMWARE(FIRMWARE_BAFFIN);
-+MODULE_FIRMWARE(FIRMWARE_POLARIS10);
-+MODULE_FIRMWARE(FIRMWARE_POLARIS11);
- 
- static void amdgpu_vce_idle_work_handler(struct work_struct *work);
- 
-@@ -117,11 +117,11 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
- 	case CHIP_STONEY:
- 		fw_name = FIRMWARE_STONEY;
- 		break;
--	case CHIP_ELLESMERE:
--		fw_name = FIRMWARE_ELLESMERE;
-+	case CHIP_POLARIS10:
-+		fw_name = FIRMWARE_POLARIS10;
- 		break;
--	case CHIP_BAFFIN:
--		fw_name = FIRMWARE_BAFFIN;
-+	case CHIP_POLARIS11:
-+		fw_name = FIRMWARE_POLARIS11;
- 		break;
- 
- 	default:
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index bcb8626..e47b252 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -132,7 +132,7 @@ static const u32 stoney_golden_settings_a11[] =
- 	mmFBC_MISC, 0x1f311fff, 0x14302000,
- };
- 
--static const u32 baffin_golden_settings_a11[] =
-+static const u32 polaris11_golden_settings_a11[] =
- {
- 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
- 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
-@@ -141,7 +141,7 @@ static const u32 baffin_golden_settings_a11[] =
- 	mmHDMI_CONTROL, 0x313f031f, 0x00000011,
- };
- 
--static const u32 ellesmere_golden_settings_a11[] =
-+static const u32 polaris10_golden_settings_a11[] =
- {
- 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
- 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
-@@ -165,15 +165,15 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
- 						 stoney_golden_settings_a11,
- 						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		amdgpu_program_register_sequence(adev,
--						 baffin_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(baffin_golden_settings_a11));
-+						 polaris11_golden_settings_a11,
-+						 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
--						 ellesmere_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11));
-+						 polaris10_golden_settings_a11,
-+						 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
- 		break;
- 	default:
- 		break;
-@@ -1610,10 +1610,10 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
- 	case CHIP_CARRIZO:
- 		adev->mode_info.audio.num_pins = 7;
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		adev->mode_info.audio.num_pins = 8;
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		adev->mode_info.audio.num_pins = 6;
- 		break;
- 	default:
-@@ -2410,8 +2410,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
- 	u32 pll_in_use;
- 	int pll;
- 
--	if ((adev->asic_type == CHIP_ELLESMERE) ||
--	    (adev->asic_type == CHIP_BAFFIN)) {
-+	if ((adev->asic_type == CHIP_POLARIS10) ||
-+	    (adev->asic_type == CHIP_POLARIS11)) {
- 		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
- 			return ATOM_DP_DTO;
- 		/* use the same PPLL for all monitors with the same clock */
-@@ -2811,8 +2811,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
- 	if (!amdgpu_crtc->adjusted_clock)
- 		return -EINVAL;
- 
--	if ((adev->asic_type == CHIP_ELLESMERE) ||
--	    (adev->asic_type == CHIP_BAFFIN)) {
-+	if ((adev->asic_type == CHIP_POLARIS10) ||
-+	    (adev->asic_type == CHIP_POLARIS11)) {
- 		struct amdgpu_encoder *amdgpu_encoder =
- 			to_amdgpu_encoder(amdgpu_crtc->encoder);
- 		int encoder_mode =
-@@ -2977,12 +2977,12 @@ static int dce_v11_0_early_init(void *handle)
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 9;
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		adev->mode_info.num_crtc = 6;
- 		adev->mode_info.num_hpd = 6;
- 		adev->mode_info.num_dig = 6;
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		adev->mode_info.num_crtc = 5;
- 		adev->mode_info.num_hpd = 5;
- 		adev->mode_info.num_dig = 5;
-@@ -3089,8 +3089,8 @@ static int dce_v11_0_hw_init(void *handle)
- 	/* init dig PHYs, disp eng pll */
- 	amdgpu_atombios_crtc_powergate_init(adev);
- 	amdgpu_atombios_encoder_init_dig(adev);
--	if ((adev->asic_type == CHIP_ELLESMERE) ||
--	    (adev->asic_type == CHIP_BAFFIN)) {
-+	if ((adev->asic_type == CHIP_POLARIS10) ||
-+	    (adev->asic_type == CHIP_POLARIS11)) {
- 		amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
- 						   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
- 		amdgpu_atombios_crtc_set_dce_clock(adev, 0,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 4cd0d19..b043dd6 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -52,7 +52,7 @@
- 
- #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
- #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
--#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002
-+#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
- #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
- 
- #define ARRAY_MODE(x)					((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
-@@ -121,19 +121,19 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
- MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
- MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
- 
--MODULE_FIRMWARE("amdgpu/baffin_ce.bin");
--MODULE_FIRMWARE("amdgpu/baffin_pfp.bin");
--MODULE_FIRMWARE("amdgpu/baffin_me.bin");
--MODULE_FIRMWARE("amdgpu/baffin_mec.bin");
--MODULE_FIRMWARE("amdgpu/baffin_mec2.bin");
--MODULE_FIRMWARE("amdgpu/baffin_rlc.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
- 
--MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_me.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
- 
- static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
- {
-@@ -265,7 +265,7 @@ static const u32 tonga_mgcg_cgcg_init[] =
- 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
- };
- 
--static const u32 golden_settings_baffin_a11[] =
-+static const u32 golden_settings_polaris11_a11[] =
- {
- 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
- 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
-@@ -281,7 +281,7 @@ static const u32 golden_settings_baffin_a11[] =
- 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
- };
- 
--static const u32 baffin_golden_common_all[] =
-+static const u32 polaris11_golden_common_all[] =
- {
- 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
- 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
-@@ -293,7 +293,7 @@ static const u32 baffin_golden_common_all[] =
- 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
- };
- 
--static const u32 golden_settings_ellesmere_a11[] =
-+static const u32 golden_settings_polaris10_a11[] =
- {
- 	mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
- 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
-@@ -311,7 +311,7 @@ static const u32 golden_settings_ellesmere_a11[] =
- 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
- };
- 
--static const u32 ellesmere_golden_common_all[] =
-+static const u32 polaris10_golden_common_all[] =
- {
- 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
- 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
-@@ -674,21 +674,21 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
- 						 tonga_golden_common_all,
- 						 (const u32)ARRAY_SIZE(tonga_golden_common_all));
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		amdgpu_program_register_sequence(adev,
--						 golden_settings_baffin_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
-+						 golden_settings_polaris11_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
- 		amdgpu_program_register_sequence(adev,
--						 baffin_golden_common_all,
--						 (const u32)ARRAY_SIZE(baffin_golden_common_all));
-+						 polaris11_golden_common_all,
-+						 (const u32)ARRAY_SIZE(polaris11_golden_common_all));
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
--						 golden_settings_ellesmere_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
-+						 golden_settings_polaris10_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
- 		amdgpu_program_register_sequence(adev,
--						 ellesmere_golden_common_all,
--						 (const u32)ARRAY_SIZE(ellesmere_golden_common_all));
-+						 polaris10_golden_common_all,
-+						 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
- 		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
-@@ -859,11 +859,11 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
- 	case CHIP_FIJI:
- 		chip_name = "fiji";
- 		break;
--	case CHIP_BAFFIN:
--		chip_name = "baffin";
-+	case CHIP_POLARIS11:
-+		chip_name = "polaris11";
- 		break;
--	case CHIP_ELLESMERE:
--		chip_name = "ellesmere";
-+	case CHIP_POLARIS10:
-+		chip_name = "polaris10";
- 		break;
- 	case CHIP_STONEY:
- 		chip_name = "stoney";
-@@ -1092,11 +1092,11 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
- 			PACKET3_SET_CONTEXT_REG_START);
- 	switch (adev->asic_type) {
- 	case CHIP_TONGA:
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		buffer[count++] = cpu_to_le32(0x16000012);
- 		buffer[count++] = cpu_to_le32(0x0000002A);
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		buffer[count++] = cpu_to_le32(0x16000012);
- 		buffer[count++] = cpu_to_le32(0x00000000);
- 		break;
-@@ -1628,7 +1628,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
- 		gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		ret = amdgpu_atombios_get_gfx_info(adev);
- 		if (ret)
- 			return ret;
-@@ -1640,9 +1640,9 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
- 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
- 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
--		gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN;
-+		gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		ret = amdgpu_atombios_get_gfx_info(adev);
- 		if (ret)
- 			return ret;
-@@ -2551,7 +2551,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
- 
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- 				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- 				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-@@ -2753,7 +2753,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
- 
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- 				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- 				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-@@ -3658,7 +3658,7 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
- 	WREG32(mmRLC_SRM_CNTL, data);
- }
- 
--static void baffin_init_power_gating(struct amdgpu_device *adev)
-+static void polaris11_init_power_gating(struct amdgpu_device *adev)
- {
- 	uint32_t data;
- 
-@@ -3701,8 +3701,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
- 		gfx_v8_0_init_save_restore_list(adev);
- 		gfx_v8_0_enable_save_restore_machine(adev);
- 
--		if (adev->asic_type == CHIP_BAFFIN)
--			baffin_init_power_gating(adev);
-+		if (adev->asic_type == CHIP_POLARIS11)
-+			polaris11_init_power_gating(adev);
- 	}
- }
- 
-@@ -3776,8 +3776,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
- 
- 	/* disable CG */
- 	WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
--	if (adev->asic_type == CHIP_BAFFIN ||
--		adev->asic_type == CHIP_ELLESMERE)
-+	if (adev->asic_type == CHIP_POLARIS11 ||
-+		adev->asic_type == CHIP_POLARIS10)
- 		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
- 
- 	/* disable PG */
-@@ -3958,11 +3958,11 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
- 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
- 	switch (adev->asic_type) {
- 	case CHIP_TONGA:
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		amdgpu_ring_write(ring, 0x16000012);
- 		amdgpu_ring_write(ring, 0x0000002A);
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		amdgpu_ring_write(ring, 0x16000012);
- 		amdgpu_ring_write(ring, 0x00000000);
- 		break;
-@@ -4610,8 +4610,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- 			if ((adev->asic_type == CHIP_CARRIZO) ||
- 			    (adev->asic_type == CHIP_FIJI) ||
- 			    (adev->asic_type == CHIP_STONEY) ||
--			    (adev->asic_type == CHIP_BAFFIN) ||
--			    (adev->asic_type == CHIP_ELLESMERE)) {
-+			    (adev->asic_type == CHIP_POLARIS11) ||
-+			    (adev->asic_type == CHIP_POLARIS10)) {
- 				WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
- 				       AMDGPU_DOORBELL_KIQ << 2);
- 				WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-@@ -4646,8 +4646,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- 		WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
- 		mqd->cp_hqd_persistent_state = tmp;
- 		if (adev->asic_type == CHIP_STONEY ||
--			adev->asic_type == CHIP_BAFFIN ||
--			adev->asic_type == CHIP_ELLESMERE) {
-+			adev->asic_type == CHIP_POLARIS11 ||
-+			adev->asic_type == CHIP_POLARIS10) {
- 			tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
- 			tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
- 			WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
-@@ -5216,7 +5216,7 @@ static int gfx_v8_0_late_init(void *handle)
- 	return 0;
- }
- 
--static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
-+static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
- 		bool enable)
- {
- 	uint32_t data, temp;
-@@ -5242,7 +5242,7 @@ static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
- 	}
- }
- 
--static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
-+static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
- 		bool enable)
- {
- 	uint32_t data, temp;
-@@ -5263,7 +5263,7 @@ static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev
- 	}
- }
- 
--static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
-+static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
- 		bool enable)
- {
- 	uint32_t data, temp;
-@@ -5293,15 +5293,15 @@ static int gfx_v8_0_set_powergating_state(void *handle,
- 		return 0;
- 
- 	switch (adev->asic_type) {
--	case CHIP_BAFFIN:
--		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)
--			baffin_enable_gfx_static_mg_power_gating(adev,
-+	case CHIP_POLARIS11:
-+		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)
-+			polaris11_enable_gfx_static_mg_power_gating(adev,
- 					state == AMD_PG_STATE_GATE ? true : false);
--		else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)
--			baffin_enable_gfx_dynamic_mg_power_gating(adev,
-+		else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)
-+			polaris11_enable_gfx_dynamic_mg_power_gating(adev,
- 					state == AMD_PG_STATE_GATE ? true : false);
- 		else
--			baffin_enable_gfx_quick_mg_power_gating(adev,
-+			polaris11_enable_gfx_quick_mg_power_gating(adev,
- 					state == AMD_PG_STATE_GATE ? true : false);
- 		break;
- 	default:
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 27956dd..f5efc67 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -43,8 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
- static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
- 
- MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
--MODULE_FIRMWARE("amdgpu/baffin_mc.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
- 
- static const u32 golden_settings_tonga_a11[] =
- {
-@@ -75,7 +75,7 @@ static const u32 fiji_mgcg_cgcg_init[] =
- 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
- };
- 
--static const u32 golden_settings_baffin_a11[] =
-+static const u32 golden_settings_polaris11_a11[] =
- {
- 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
- 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-@@ -83,7 +83,7 @@ static const u32 golden_settings_baffin_a11[] =
- 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
- };
- 
--static const u32 golden_settings_ellesmere_a11[] =
-+static const u32 golden_settings_polaris10_a11[] =
- {
- 	mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
- 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
-@@ -122,15 +122,15 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
- 						 golden_settings_tonga_a11,
- 						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		amdgpu_program_register_sequence(adev,
--						 golden_settings_baffin_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
-+						 golden_settings_polaris11_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
--						 golden_settings_ellesmere_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
-+						 golden_settings_polaris10_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
- 		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
-@@ -238,11 +238,11 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
- 	case CHIP_TONGA:
- 		chip_name = "tonga";
- 		break;
--	case CHIP_BAFFIN:
--		chip_name = "baffin";
-+	case CHIP_POLARIS11:
-+		chip_name = "polaris11";
- 		break;
--	case CHIP_ELLESMERE:
--		chip_name = "ellesmere";
-+	case CHIP_POLARIS10:
-+		chip_name = "polaris10";
- 		break;
- 	case CHIP_FIJI:
- 	case CHIP_CARRIZO:
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 6b24a9c..72cae36 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -56,10 +56,10 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
- MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
- MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
- MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin");
--MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin");
--MODULE_FIRMWARE("amdgpu/baffin_sdma.bin");
--MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
- 
- 
- static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
-@@ -106,7 +106,7 @@ static const u32 fiji_mgcg_cgcg_init[] =
- 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
- };
- 
--static const u32 golden_settings_baffin_a11[] =
-+static const u32 golden_settings_polaris11_a11[] =
- {
- 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
- 	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
-@@ -118,7 +118,7 @@ static const u32 golden_settings_baffin_a11[] =
- 	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
- };
- 
--static const u32 golden_settings_ellesmere_a11[] =
-+static const u32 golden_settings_polaris10_a11[] =
- {
- 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
- 	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
-@@ -203,15 +203,15 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
- 						 golden_settings_tonga_a11,
- 						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		amdgpu_program_register_sequence(adev,
--						 golden_settings_baffin_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
-+						 golden_settings_polaris11_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
--						 golden_settings_ellesmere_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
-+						 golden_settings_polaris10_a11,
-+						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
- 		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
-@@ -261,11 +261,11 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
- 	case CHIP_FIJI:
- 		chip_name = "fiji";
- 		break;
--	case CHIP_BAFFIN:
--		chip_name = "baffin";
-+	case CHIP_POLARIS11:
-+		chip_name = "polaris11";
- 		break;
--	case CHIP_ELLESMERE:
--		chip_name = "ellesmere";
-+	case CHIP_POLARIS10:
-+		chip_name = "polaris10";
- 		break;
- 	case CHIP_CARRIZO:
- 		chip_name = "carrizo";
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index c12fd83..5834285 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -315,11 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
- {
- 	u32 tmp;
- 
--	/* Fiji, Stoney, Ellesmere, Baffin are single pipe */
-+	/* Fiji, Stoney, Polaris10, Polaris11 are single pipe */
- 	if ((adev->asic_type == CHIP_FIJI) ||
- 	    (adev->asic_type == CHIP_STONEY) ||
--	    (adev->asic_type == CHIP_ELLESMERE) ||
--	    (adev->asic_type == CHIP_BAFFIN))
-+	    (adev->asic_type == CHIP_POLARIS10) ||
-+	    (adev->asic_type == CHIP_POLARIS11))
- 		return AMDGPU_VCE_HARVEST_VCE1;
- 
- 	/* Tonga and CZ are dual or single pipe */
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 8e0e014..0d61d5b 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -277,8 +277,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
- 						 stoney_mgcg_cgcg_init,
- 						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
- 		break;
--	case CHIP_BAFFIN:
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
- 	default:
- 		break;
- 	}
-@@ -540,8 +540,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
- 		break;
- 	case CHIP_FIJI:
- 	case CHIP_TONGA:
--	case CHIP_BAFFIN:
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
- 		asic_register_table = cz_allowed_read_registers;
-@@ -912,7 +912,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
- 	},
- };
- 
--static const struct amdgpu_ip_block_version baffin_ip_blocks[] =
-+static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
- {
- 	/* ORDER MATTERS! */
- 	{
-@@ -1311,10 +1311,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
- #endif
- 		break;
--	case CHIP_BAFFIN:
--	case CHIP_ELLESMERE:
--		adev->ip_blocks = baffin_ip_blocks;
--		adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks);
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
-+		adev->ip_blocks = polaris11_ip_blocks;
-+		adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
- 		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
-@@ -1427,12 +1427,12 @@ static int vi_common_early_init(void *handle)
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x14;
- 		break;
--	case CHIP_BAFFIN:
-+	case CHIP_POLARIS11:
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x5A;
- 		break;
--	case CHIP_ELLESMERE:
-+	case CHIP_POLARIS10:
- 		adev->cg_flags = 0;
- 		adev->pg_flags = 0;
- 		adev->external_rev_id = adev->rev_id + 0x50;
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index 72858a0..e56d8a3 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -48,8 +48,8 @@ enum amd_asic_type {
- 	CHIP_FIJI,
- 	CHIP_CARRIZO,
- 	CHIP_STONEY,
--	CHIP_ELLESMERE,
--	CHIP_BAFFIN,
-+	CHIP_POLARIS10,
-+	CHIP_POLARIS11,
- 	CHIP_LAST,
- };
- 
-diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
-index 296def3..32f3e34 100644
---- a/drivers/gpu/drm/amd/include/atombios.h
-+++ b/drivers/gpu/drm/amd/include/atombios.h
-@@ -2061,7 +2061,7 @@ typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1
- #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS         0x01
- #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK           0x02
- 
--// SetDCEClockTable input parameter for DCE11.2( ELM and BF ) and above
-+// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above
- typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1
- {
-   ULONG  ulDCEClkFreq;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
-@@ -5494,7 +5494,7 @@ typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_4
-   ULONG ulReserved[8];            // Reserved for future ASIC
- }ATOM_ASIC_PROFILING_INFO_V3_4;
- 
--// for Ellemser/Baffin speed EVV algorithm
-+// for  Polaris10/Polaris11 speed EVV algorithm
- typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_5
- {
-   ATOM_COMMON_TABLE_HEADER         asHeader;
-@@ -5549,7 +5549,7 @@ typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
- }ATOM_SCLK_FCW_RANGE_ENTRY_V1;
- 
- 
--// SMU_InfoTable for Ellesmere/Baffin
-+// SMU_InfoTable for  Polaris10/Polaris11
- typedef struct  _ATOM_SMU_INFO_V2_1
- {
-   ATOM_COMMON_TABLE_HEADER         asHeader;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-index 5437ec0..f7ce4cb 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
-@@ -9,8 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
-                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
-                fiji_clockpowergating.o fiji_thermal.o \
--	       ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \
--	       ellesmere_clockpowergating.o
-+	       polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \
-+	       polaris10_clockpowergating.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-deleted file mode 100644
-index 93db824..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c
-+++ /dev/null
-@@ -1,428 +0,0 @@
--/*
-- * Copyright 2016 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#include "ellesmere_clockpowergating.h"
--
--int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cf_want_uvd_power_gating(hwmgr))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_UVDPowerOFF);
--	return 0;
--}
--
--int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cf_want_uvd_power_gating(hwmgr)) {
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
--			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_UVDPowerON, 1);
--		} else {
--			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_UVDPowerON, 0);
--		}
--	}
--
--	return 0;
--}
--
--int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cf_want_vce_power_gating(hwmgr))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_VCEPowerOFF);
--	return 0;
--}
--
--int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cf_want_vce_power_gating(hwmgr))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_VCEPowerON);
--	return 0;
--}
--
--int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SamuPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_SAMPowerOFF);
--	return 0;
--}
--
--int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SamuPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_SAMPowerON);
--	return 0;
--}
--
--int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	data->uvd_power_gated = false;
--	data->vce_power_gated = false;
--	data->samu_power_gated = false;
--
--	ellesmere_phm_powerup_uvd(hwmgr);
--	ellesmere_phm_powerup_vce(hwmgr);
--	ellesmere_phm_powerup_samu(hwmgr);
--
--	return 0;
--}
--
--int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (data->uvd_power_gated == bgate)
--		return 0;
--
--	data->uvd_power_gated = bgate;
--
--	if (bgate) {
--		ellesmere_update_uvd_dpm(hwmgr, true);
--		ellesmere_phm_powerdown_uvd(hwmgr);
--	} else {
--		ellesmere_phm_powerup_uvd(hwmgr);
--		ellesmere_update_uvd_dpm(hwmgr, false);
--	}
--
--	return 0;
--}
--
--int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (data->vce_power_gated == bgate)
--		return 0;
--
--	if (bgate)
--		ellesmere_phm_powerdown_vce(hwmgr);
--	else
--		ellesmere_phm_powerup_vce(hwmgr);
--
--	return 0;
--}
--
--int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (data->samu_power_gated == bgate)
--		return 0;
--
--	data->samu_power_gated = bgate;
--
--	if (bgate) {
--		ellesmere_update_samu_dpm(hwmgr, true);
--		ellesmere_phm_powerdown_samu(hwmgr);
--	} else {
--		ellesmere_phm_powerup_samu(hwmgr);
--		ellesmere_update_samu_dpm(hwmgr, false);
--	}
--
--	return 0;
--}
--
--int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
--					const uint32_t *msg_id)
--{
--	PPSMC_Msg msg;
--	uint32_t value;
--
--	switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
--	case PP_GROUP_GFX:
--		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
--		case PP_BLOCK_GFX_CG:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_GFX_CGCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
--					? PPSMC_MSG_EnableClockGatingFeature
--					: PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_GFX_CGLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_GFX_3D:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_GFX_3DCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--
--			if  (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_GFX_3DLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_GFX_RLC:
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_GFX_RLC_LS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_GFX_CP:
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_GFX_CP_LS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_GFX_MG:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK |
--						CG_GFX_OTHERS_MGCG_MASK);
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		default:
--			return -1;
--		}
--		break;
--
--	case PP_GROUP_SYS:
--		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
--		case PP_BLOCK_SYS_BIF:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_BIF_MGCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			if  (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_BIF_MGLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_SYS_MC:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_MC_MGCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_MC_MGLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_SYS_DRM:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_DRM_MGCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_DRM_MGLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_SYS_HDP:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_HDP_MGCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_HDP_MGLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_SYS_SDMA:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_SDMA_MGCG_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--
--			if (PP_STATE_SUPPORT_LS & *msg_id) {
--				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_SDMA_MGLS_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		case PP_BLOCK_SYS_ROM:
--			if (PP_STATE_SUPPORT_CG & *msg_id) {
--				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
--						PPSMC_MSG_EnableClockGatingFeature :
--						PPSMC_MSG_DisableClockGatingFeature;
--				value = CG_SYS_ROM_MASK;
--
--				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
--					return -1;
--			}
--			break;
--
--		default:
--			return -1;
--
--		}
--		break;
--
--	default:
--		return -1;
--
--	}
--
--	return 0;
--}
--
--/* This function is for Baffin only for now,
-- * Powerplay will only control the static per CU Power Gating.
-- * Dynamic per CU Power Gating will be done in gfx.
-- */
--int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
--{
--	struct cgs_system_info sys_info = {0};
--	uint32_t active_cus;
--	int result;
--
--	sys_info.size = sizeof(struct cgs_system_info);
--	sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
--
--	result = cgs_query_system_info(hwmgr->device, &sys_info);
--
--	if (result)
--		return -EINVAL;
--	else
--		active_cus = sys_info.value;
--
--	if (enable)
--		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
--	else
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_GFX_CU_PG_DISABLE);
--}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-deleted file mode 100644
-index b403e11..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h
-+++ /dev/null
-@@ -1,40 +0,0 @@
--/*
-- * Copyright 2016 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef _ELLESMERE_CLOCK_POWER_GATING_H_
--#define _ELLESMERE_CLOCK_POWER_GATING_H_
--
--#include "ellesmere_hwmgr.h"
--#include "pp_asicblocks.h"
--
--int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
--int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
--int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
--int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
--int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
--int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
--int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
--					const uint32_t *msg_id);
--int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
--
--#endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
-deleted file mode 100644
-index ba1187c..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
-+++ /dev/null
-@@ -1,62 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef ELLESMERE_DYN_DEFAULTS_H
--#define ELLESMERE_DYN_DEFAULTS_H
--
--
--enum Ellesmeredpm_TrendDetection {
--	EllesmereAdpm_TrendDetection_AUTO,
--	EllesmereAdpm_TrendDetection_UP,
--	EllesmereAdpm_TrendDetection_DOWN
--};
--typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection;
--
--/*  We need to fill in the default values */
--
--
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1              0x000400
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033
--#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000
--
--
--#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT            0x200
--#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT        0
--#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT            0x00C8
--#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200
--#define PPELLESMERE_REFERENCEDIVIDER_DFLT                  4
--
--#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT             1687
--
--#define PPELLESMERE_CGULVPARAMETER_DFLT                    0x00040035
--#define PPELLESMERE_CGULVCONTROL_DFLT                      0x00007450
--#define PPELLESMERE_TARGETACTIVITY_DFLT                     50
--#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT                10
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-deleted file mode 100644
-index 152d77d..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c
-+++ /dev/null
-@@ -1,4711 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--#include <linux/module.h>
--#include <linux/slab.h>
--#include <linux/fb.h>
--#include "linux/delay.h"
--#include "pp_acpi.h"
--#include "hwmgr.h"
--#include "ellesmere_hwmgr.h"
--#include "ellesmere_powertune.h"
--#include "ellesmere_dyn_defaults.h"
--#include "ellesmere_smumgr.h"
--#include "pp_debug.h"
--#include "ppatomctrl.h"
--#include "atombios.h"
--#include "tonga_pptable.h"
--#include "pppcielanes.h"
--#include "amd_pcie_helpers.h"
--#include "hardwaremanager.h"
--#include "tonga_processpptables.h"
--#include "cgs_common.h"
--#include "smu74.h"
--#include "smu_ucode_xfer_vi.h"
--#include "smu74_discrete.h"
--#include "smu/smu_7_1_3_d.h"
--#include "smu/smu_7_1_3_sh_mask.h"
--#include "gmc/gmc_8_1_d.h"
--#include "gmc/gmc_8_1_sh_mask.h"
--#include "oss/oss_3_0_d.h"
--#include "gca/gfx_8_0_d.h"
--#include "bif/bif_5_0_d.h"
--#include "bif/bif_5_0_sh_mask.h"
--#include "gmc/gmc_8_1_d.h"
--#include "gmc/gmc_8_1_sh_mask.h"
--#include "bif/bif_5_0_d.h"
--#include "bif/bif_5_0_sh_mask.h"
--#include "dce/dce_10_0_d.h"
--#include "dce/dce_10_0_sh_mask.h"
--
--#include "ellesmere_thermal.h"
--#include "ellesmere_clockpowergating.h"
--
--#define MC_CG_ARB_FREQ_F0           0x0a
--#define MC_CG_ARB_FREQ_F1           0x0b
--#define MC_CG_ARB_FREQ_F2           0x0c
--#define MC_CG_ARB_FREQ_F3           0x0d
--
--#define MC_CG_SEQ_DRAMCONF_S0       0x05
--#define MC_CG_SEQ_DRAMCONF_S1       0x06
--#define MC_CG_SEQ_YCLK_SUSPEND      0x04
--#define MC_CG_SEQ_YCLK_RESUME       0x0a
--
--
--#define SMC_RAM_END 0x40000
--
--#define SMC_CG_IND_START            0xc0030000
--#define SMC_CG_IND_END              0xc0040000
--
--#define VOLTAGE_SCALE               4
--#define VOLTAGE_VID_OFFSET_SCALE1   625
--#define VOLTAGE_VID_OFFSET_SCALE2   100
--
--#define VDDC_VDDCI_DELTA            200
--
--#define MEM_FREQ_LOW_LATENCY        25000
--#define MEM_FREQ_HIGH_LATENCY       80000
--
--#define MEM_LATENCY_HIGH            45
--#define MEM_LATENCY_LOW             35
--#define MEM_LATENCY_ERR             0xFFFF
--
--#define MC_SEQ_MISC0_GDDR5_SHIFT 28
--#define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
--#define MC_SEQ_MISC0_GDDR5_VALUE 5
--
--
--#define PCIE_BUS_CLK                10000
--#define TCLK                        (PCIE_BUS_CLK / 10)
--
--
--uint16_t ellesmere_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
--							  {600, 1050, 6, 1} };
--
--/*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
--uint32_t ellesmere_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
--							{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
--
--/*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
--uint8_t ellesmere_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
--							    {0, 2, 4, 5, 6, 5} };
--
--/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
--enum DPM_EVENT_SRC {
--	DPM_EVENT_SRC_ANALOG = 0,
--	DPM_EVENT_SRC_EXTERNAL = 1,
--	DPM_EVENT_SRC_DIGITAL = 2,
--	DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
--	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
--};
--
--const unsigned long PhwEllesmere_Magic = (unsigned long)(PHM_VIslands_Magic);
--
--struct ellesmere_power_state *cast_phw_ellesmere_power_state(
--				  struct pp_hw_power_state *hw_ps)
--{
--	PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic),
--				"Invalid Powerstate Type!",
--				 return NULL);
--
--	return (struct ellesmere_power_state *)hw_ps;
--}
--
--const struct ellesmere_power_state *cast_const_phw_ellesmere_power_state(
--				 const struct pp_hw_power_state *hw_ps)
--{
--	PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic),
--				"Invalid Powerstate Type!",
--				 return NULL);
--
--	return (const struct ellesmere_power_state *)hw_ps;
--}
--
--static bool ellesmere_is_dpm_running(struct pp_hwmgr *hwmgr)
--{
--	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
--			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
--			? true : false;
--}
--
--/**
-- * Find the MC microcode version and store it in the HwMgr struct
-- *
-- * @param    hwmgr  the address of the powerplay hardware manager.
-- * @return   always 0
-- */
--int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
--{
--	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
--
--	hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
--
--	return 0;
--}
--
--uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
--{
--	uint32_t speedCntl = 0;
--
--	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
--	speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
--			ixPCIE_LC_SPEED_CNTL);
--	return((uint16_t)PHM_GET_FIELD(speedCntl,
--			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
--}
--
--int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
--{
--	uint32_t link_width;
--
--	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
--	link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
--			PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
--
--	PP_ASSERT_WITH_CODE((7 >= link_width),
--			"Invalid PCIe lane width!", return 0);
--
--	return decode_pcie_lane_width(link_width);
--}
--
--void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
--{
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)hwmgr->pptable;
--	struct phm_clock_voltage_dependency_table *table =
--				table_info->vddc_dep_on_dal_pwrl;
--	struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
--	enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
--	uint32_t req_vddc = 0, req_volt, i;
--
--	if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
--			dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
--		return;
--
--	for (i = 0; i < table->count; i++) {
--		if (dal_power_level == table->entries[i].clk) {
--			req_vddc = table->entries[i].v;
--			break;
--		}
--	}
--
--	vddc_table = table_info->vdd_dep_on_sclk;
--	for (i = 0; i < vddc_table->count; i++) {
--		if (req_vddc <= vddc_table->entries[i].vddc) {
--			req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
--					<< VDDC_SHIFT;
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_VddC_Request, req_volt);
--			return;
--		}
--	}
--	printk(KERN_ERR "DAL requested level can not"
--			" found a available voltage in VDDC DPM Table \n");
--}
--
--/**
--* Enable voltage control
--*
--* @param    pHwMgr  the address of the powerplay hardware manager.
--* @return   always PP_Result_OK
--*/
--int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
--{
--	PP_ASSERT_WITH_CODE(
--		(hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
--		"Failed to enable voltage DPM during DPM Start Function!",
--		return 1;
--	);
--
--	return 0;
--}
--
--/**
--* Checks if we want to support voltage control
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--*/
--static bool ellesmere_voltage_control(const struct pp_hwmgr *hwmgr)
--{
--	const struct ellesmere_hwmgr *data =
--			(const struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	return (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control);
--}
--
--/**
--* Enable voltage control
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--*/
--static int ellesmere_enable_voltage_control(struct pp_hwmgr *hwmgr)
--{
--	/* enable voltage control */
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
--
--	return 0;
--}
--
--/**
--* Create Voltage Tables.
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--*/
--static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)hwmgr->pptable;
--	int result;
--
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
--		result = atomctrl_get_voltage_table_v3(hwmgr,
--				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
--				&(data->mvdd_voltage_table));
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to retrieve MVDD table.",
--				return result);
--	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
--		result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
--				table_info->vdd_dep_on_mclk);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to retrieve SVI2 MVDD table from dependancy table.",
--				return result;);
--	}
--
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
--		result = atomctrl_get_voltage_table_v3(hwmgr,
--				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
--				&(data->vddci_voltage_table));
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to retrieve VDDCI table.",
--				return result);
--	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
--		result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
--				table_info->vdd_dep_on_mclk);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to retrieve SVI2 VDDCI table from dependancy table.",
--				return result);
--	}
--
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
--		result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
--				table_info->vddc_lookup_table);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to retrieve SVI2 VDDC table from lookup table.",
--				return result);
--	}
--
--	PP_ASSERT_WITH_CODE(
--			(data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
--			"Too many voltage values for VDDC. Trimming to fit state table.",
--			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
--								&(data->vddc_voltage_table)));
--
--	PP_ASSERT_WITH_CODE(
--			(data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
--			"Too many voltage values for VDDCI. Trimming to fit state table.",
--			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
--					&(data->vddci_voltage_table)));
--
--	PP_ASSERT_WITH_CODE(
--			(data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
--			"Too many voltage values for MVDD. Trimming to fit state table.",
--			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
--							   &(data->mvdd_voltage_table)));
--
--	return 0;
--}
--
--/**
--* Programs static screed detection parameters
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--*/
--static int ellesmere_program_static_screen_threshold_parameters(
--							struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	/* Set static screen threshold unit */
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
--			data->static_screen_threshold_unit);
--	/* Set static screen threshold */
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
--			data->static_screen_threshold);
--
--	return 0;
--}
--
--/**
--* Setup display gap for glitch free memory clock switching.
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always  0
--*/
--static int ellesmere_enable_display_gap(struct pp_hwmgr *hwmgr)
--{
--	uint32_t display_gap =
--			cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--					ixCG_DISPLAY_GAP_CNTL);
--
--	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
--			DISP_GAP, DISPLAY_GAP_IGNORE);
--
--	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
--			DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_DISPLAY_GAP_CNTL, display_gap);
--
--	return 0;
--}
--
--/**
--* Programs activity state transition voting clients
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always  0
--*/
--static int ellesmere_program_voting_clients(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	/* Clear reset for voting clients before enabling DPM */
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
--
--	return 0;
--}
--
--/**
--* Get the location of various tables inside the FW image.
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always  0
--*/
--static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(hwmgr->smumgr->backend);
--	uint32_t tmp;
--	int result;
--	bool error = false;
--
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			SMU7_FIRMWARE_HEADER_LOCATION +
--			offsetof(SMU74_Firmware_Header, DpmTable),
--			&tmp, data->sram_end);
--
--	if (0 == result)
--		data->dpm_table_start = tmp;
--
--	error |= (0 != result);
--
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			SMU7_FIRMWARE_HEADER_LOCATION +
--			offsetof(SMU74_Firmware_Header, SoftRegisters),
--			&tmp, data->sram_end);
--
--	if (!result) {
--		data->soft_regs_start = tmp;
--		smu_data->soft_regs_start = tmp;
--	}
--
--	error |= (0 != result);
--
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			SMU7_FIRMWARE_HEADER_LOCATION +
--			offsetof(SMU74_Firmware_Header, mcRegisterTable),
--			&tmp, data->sram_end);
--
--	if (!result)
--		data->mc_reg_table_start = tmp;
--
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			SMU7_FIRMWARE_HEADER_LOCATION +
--			offsetof(SMU74_Firmware_Header, FanTable),
--			&tmp, data->sram_end);
--
--	if (!result)
--		data->fan_table_start = tmp;
--
--	error |= (0 != result);
--
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			SMU7_FIRMWARE_HEADER_LOCATION +
--			offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
--			&tmp, data->sram_end);
--
--	if (!result)
--		data->arb_table_start = tmp;
--
--	error |= (0 != result);
--
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			SMU7_FIRMWARE_HEADER_LOCATION +
--			offsetof(SMU74_Firmware_Header, Version),
--			&tmp, data->sram_end);
--
--	if (!result)
--		hwmgr->microcode_version_info.SMC = tmp;
--
--	error |= (0 != result);
--
--	return error ? -1 : 0;
--}
--
--/* Copy one arb setting to another and then switch the active set.
-- * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
-- */
--static int ellesmere_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
--		uint32_t arb_src, uint32_t arb_dest)
--{
--	uint32_t mc_arb_dram_timing;
--	uint32_t mc_arb_dram_timing2;
--	uint32_t burst_time;
--	uint32_t mc_cg_config;
--
--	switch (arb_src) {
--	case MC_CG_ARB_FREQ_F0:
--		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
--		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
--		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
--		break;
--	case MC_CG_ARB_FREQ_F1:
--		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
--		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
--		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
--		break;
--	default:
--		return -EINVAL;
--	}
--
--	switch (arb_dest) {
--	case MC_CG_ARB_FREQ_F0:
--		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
--		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
--		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
--		break;
--	case MC_CG_ARB_FREQ_F1:
--		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
--		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
--		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
--		break;
--	default:
--		return -EINVAL;
--	}
--
--	mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
--	mc_cg_config |= 0x0000000F;
--	cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
--	PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
--
--	return 0;
--}
--
--/**
--* Initial switch from ARB F0->F1
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--* This function is to be called from the SetPowerState table.
--*/
--static int ellesmere_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
--{
--	return ellesmere_copy_and_switch_arb_sets(hwmgr,
--			MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
--}
--
--static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
--	uint32_t i, max_entry;
--
--	PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
--			data->use_pcie_power_saving_levels), "No pcie performance levels!",
--			return -EINVAL);
--
--	if (data->use_pcie_performance_levels &&
--			!data->use_pcie_power_saving_levels) {
--		data->pcie_gen_power_saving = data->pcie_gen_performance;
--		data->pcie_lane_power_saving = data->pcie_lane_performance;
--	} else if (!data->use_pcie_performance_levels &&
--			data->use_pcie_power_saving_levels) {
--		data->pcie_gen_performance = data->pcie_gen_power_saving;
--		data->pcie_lane_performance = data->pcie_lane_power_saving;
--	}
--
--	phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
--					SMU74_MAX_LEVELS_LINK,
--					MAX_REGULAR_DPM_NUMBER);
--
--	if (pcie_table != NULL) {
--		/* max_entry is used to make sure we reserve one PCIE level
--		 * for boot level (fix for A+A PSPP issue).
--		 * If PCIE table from PPTable have ULV entry + 8 entries,
--		 * then ignore the last entry.*/
--		max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
--				SMU74_MAX_LEVELS_LINK : pcie_table->count;
--		for (i = 1; i < max_entry; i++) {
--			phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
--					get_pcie_gen_support(data->pcie_gen_cap,
--							pcie_table->entries[i].gen_speed),
--					get_pcie_lane_support(data->pcie_lane_cap,
--							pcie_table->entries[i].lane_width));
--		}
--		data->dpm_table.pcie_speed_table.count = max_entry - 1;
--
--		/* Setup BIF_SCLK levels */
--		for (i = 0; i < max_entry; i++)
--			data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
--	} else {
--		/* Hardcode Pcie Table */
--		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
--				get_pcie_gen_support(data->pcie_gen_cap,
--						PP_Min_PCIEGen),
--				get_pcie_lane_support(data->pcie_lane_cap,
--						PP_Max_PCIELane));
--		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
--				get_pcie_gen_support(data->pcie_gen_cap,
--						PP_Min_PCIEGen),
--				get_pcie_lane_support(data->pcie_lane_cap,
--						PP_Max_PCIELane));
--		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
--				get_pcie_gen_support(data->pcie_gen_cap,
--						PP_Max_PCIEGen),
--				get_pcie_lane_support(data->pcie_lane_cap,
--						PP_Max_PCIELane));
--		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
--				get_pcie_gen_support(data->pcie_gen_cap,
--						PP_Max_PCIEGen),
--				get_pcie_lane_support(data->pcie_lane_cap,
--						PP_Max_PCIELane));
--		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
--				get_pcie_gen_support(data->pcie_gen_cap,
--						PP_Max_PCIEGen),
--				get_pcie_lane_support(data->pcie_lane_cap,
--						PP_Max_PCIELane));
--		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
--				get_pcie_gen_support(data->pcie_gen_cap,
--						PP_Max_PCIEGen),
--				get_pcie_lane_support(data->pcie_lane_cap,
--						PP_Max_PCIELane));
--
--		data->dpm_table.pcie_speed_table.count = 6;
--	}
--	/* Populate last level for boot PCIE level, but do not increment count. */
--	phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
--			data->dpm_table.pcie_speed_table.count,
--			get_pcie_gen_support(data->pcie_gen_cap,
--					PP_Min_PCIEGen),
--			get_pcie_lane_support(data->pcie_lane_cap,
--					PP_Max_PCIELane));
--
--	return 0;
--}
--
--/*
-- * This function is to initalize all DPM state tables
-- * for SMU7 based on the dependency table.
-- * Dynamic state patching function will then trim these
-- * state tables to the allowed range based
-- * on the power policy or external client requests,
-- * such as UVD request, etc.
-- */
--int ellesmere_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	uint32_t i;
--
--	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
--			table_info->vdd_dep_on_sclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
--			table_info->vdd_dep_on_mclk;
--
--	PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
--			"SCLK dependency table is missing. This table is mandatory",
--			return -EINVAL);
--	PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
--			"SCLK dependency table has to have is missing."
--			"This table is mandatory",
--			return -EINVAL);
--
--	PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
--			"MCLK dependency table is missing. This table is mandatory",
--			return -EINVAL);
--	PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
--			"MCLK dependency table has to have is missing."
--			"This table is mandatory",
--			return -EINVAL);
--
--	/* clear the state table to reset everything to default */
--	phm_reset_single_dpm_table(
--			&data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
--	phm_reset_single_dpm_table(
--			&data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
--
--
--	/* Initialize Sclk DPM table based on allow Sclk values */
--	data->dpm_table.sclk_table.count = 0;
--	for (i = 0; i < dep_sclk_table->count; i++) {
--		if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
--						dep_sclk_table->entries[i].clk) {
--
--			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
--					dep_sclk_table->entries[i].clk;
--
--			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
--					(i == 0) ? true : false;
--			data->dpm_table.sclk_table.count++;
--		}
--	}
--
--	/* Initialize Mclk DPM table based on allow Mclk values */
--	data->dpm_table.mclk_table.count = 0;
--	for (i = 0; i < dep_mclk_table->count; i++) {
--		if (i == 0 || data->dpm_table.mclk_table.dpm_levels
--				[data->dpm_table.mclk_table.count - 1].value !=
--						dep_mclk_table->entries[i].clk) {
--			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
--							dep_mclk_table->entries[i].clk;
--			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
--							(i == 0) ? true : false;
--			data->dpm_table.mclk_table.count++;
--		}
--	}
--
--	/* setup PCIE gen speed levels */
--	ellesmere_setup_default_pcie_table(hwmgr);
--
--	/* save a copy of the default DPM table */
--	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
--			sizeof(struct ellesmere_dpm_table));
--
--	return 0;
--}
--
--uint8_t convert_to_vid(uint16_t vddc)
--{
--	return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
--}
--
--/**
-- * Mvdd table preparation for SMC.
-- *
-- * @param    *hwmgr The address of the hardware manager.
-- * @param    *table The SMC DPM table structure to be populated.
-- * @return   0
-- */
--static int ellesmere_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
--			SMU74_Discrete_DpmTable *table)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t count, level;
--
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
--		count = data->mvdd_voltage_table.count;
--		if (count > SMU_MAX_SMIO_LEVELS)
--			count = SMU_MAX_SMIO_LEVELS;
--		for (level = 0; level < count; level++) {
--			table->SmioTable2.Pattern[level].Voltage =
--				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
--			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
--			table->SmioTable2.Pattern[level].Smio =
--				(uint8_t) level;
--			table->Smio[level] |=
--				data->mvdd_voltage_table.entries[level].smio_low;
--		}
--		table->SmioMask2 = data->vddci_voltage_table.mask_low;
--
--		table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
--	}
--
--	return 0;
--}
--
--static int ellesmere_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
--					struct SMU74_Discrete_DpmTable *table)
--{
--	uint32_t count, level;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	count = data->vddci_voltage_table.count;
--
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
--		if (count > SMU_MAX_SMIO_LEVELS)
--			count = SMU_MAX_SMIO_LEVELS;
--		for (level = 0; level < count; ++level) {
--			table->SmioTable1.Pattern[level].Voltage =
--				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
--			table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
--
--			table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
--		}
--	}
--
--	table->SmioMask1 = data->vddci_voltage_table.mask_low;
--
--	return 0;
--}
--
--/**
--* Preparation of vddc and vddgfx CAC tables for SMC.
--*
--* @param    hwmgr  the address of the hardware manager
--* @param    table  the SMC DPM table structure to be populated
--* @return   always 0
--*/
--static int ellesmere_populate_cac_table(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	uint32_t count;
--	uint8_t index;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
--			table_info->vddc_lookup_table;
--	/* tables is already swapped, so in order to use the value from it,
--	 * we need to swap it back.
--	 * We are populating vddc CAC data to BapmVddc table
--	 * in split and merged mode
--	 */
--	for (count = 0; count < lookup_table->count; count++) {
--		index = phm_get_voltage_index(lookup_table,
--				data->vddc_voltage_table.entries[count].value);
--		table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
--		table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
--		table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
--	}
--
--	return 0;
--}
--
--/**
--* Preparation of voltage tables for SMC.
--*
--* @param    hwmgr   the address of the hardware manager
--* @param    table   the SMC DPM table structure to be populated
--* @return   always  0
--*/
--
--int ellesmere_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	ellesmere_populate_smc_vddci_table(hwmgr, table);
--	ellesmere_populate_smc_mvdd_table(hwmgr, table);
--	ellesmere_populate_cac_table(hwmgr, table);
--
--	return 0;
--}
--
--static int ellesmere_populate_ulv_level(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_Ulv *state)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	state->CcPwrDynRm = 0;
--	state->CcPwrDynRm1 = 0;
--
--	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
--	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
--			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
--
--	state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
--
--	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
--	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
--	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
--
--	return 0;
--}
--
--static int ellesmere_populate_ulv_state(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	return ellesmere_populate_ulv_level(hwmgr, &table->Ulv);
--}
--
--static int ellesmere_populate_smc_link_level(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
--	int i;
--
--	/* Index (dpm_table->pcie_speed_table.count)
--	 * is reserved for PCIE boot level. */
--	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
--		table->LinkLevel[i].PcieGenSpeed  =
--				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
--		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
--				dpm_table->pcie_speed_table.dpm_levels[i].param1);
--		table->LinkLevel[i].EnabledForActivity = 1;
--		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
--		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
--		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
--	}
--
--	data->smc_state_table.LinkLevelCount =
--			(uint8_t)dpm_table->pcie_speed_table.count;
--	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
--			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
--
--	return 0;
--}
--
--static uint32_t ellesemere_get_xclk(struct pp_hwmgr *hwmgr)
--{
--	uint32_t reference_clock, tmp;
--	struct cgs_display_info info = {0};
--	struct cgs_mode_info mode_info;
--
--	info.mode_info = &mode_info;
--
--	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
--
--	if (tmp)
--		return TCLK;
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--	reference_clock = mode_info.ref_clock;
--
--	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
--
--	if (0 != tmp)
--		return reference_clock / 4;
--
--	return reference_clock;
--}
--
--/**
--* Calculates the SCLK dividers using the provided engine clock
--*
--* @param    hwmgr  the address of the hardware manager
--* @param    clock  the engine clock to use to populate the structure
--* @param    sclk   the SMC SCLK structure to be populated
--*/
--static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr,
--		uint32_t clock, SMU_SclkSetting *sclk_setting)
--{
--	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
--	struct pp_atomctrl_clock_dividers_ai dividers;
--
--	uint32_t ref_clock;
--	uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
--	uint8_t i;
--	int result;
--	uint64_t temp;
--
--	sclk_setting->SclkFrequency = clock;
--	/* get the engine clock dividers for this clock value */
--	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
--	if (result == 0) {
--		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
--		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
--		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
--		sclk_setting->PllRange = dividers.ucSclkPllRange;
--		sclk_setting->Sclk_slew_rate = 0x400;
--		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
--		sclk_setting->Pcc_down_slew_rate = 0xffff;
--		sclk_setting->SSc_En = dividers.ucSscEnable;
--		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
--		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
--		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
--		return result;
--	}
--
--	ref_clock = ellesemere_get_xclk(hwmgr);
--
--	for (i = 0; i < NUM_SCLK_RANGE; i++) {
--		if (clock > data->range_table[i].trans_lower_frequency
--		&& clock <= data->range_table[i].trans_upper_frequency) {
--			sclk_setting->PllRange = i;
--			break;
--		}
--	}
--
--	sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
--	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
--	temp <<= 0x10;
--	sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
--
--	pcc_target_percent = 10; /*  Hardcode 10% for now. */
--	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
--	sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
--
--	ss_target_percent = 2; /*  Hardcode 2% for now. */
--	sclk_setting->SSc_En = 0;
--	if (ss_target_percent) {
--		sclk_setting->SSc_En = 1;
--		ss_target_freq = clock - (clock * ss_target_percent / 100);
--		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
--		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
--		temp <<= 0x10;
--		sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
--	}
--
--	return 0;
--}
--
--static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
--		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
--		uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
--{
--	uint32_t i;
--	uint16_t vddci;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	*voltage = *mvdd = 0;
--
--	/* clock - voltage dependency table is empty table */
--	if (dep_table->count == 0)
--		return -EINVAL;
--
--	for (i = 0; i < dep_table->count; i++) {
--		/* find first sclk bigger than request */
--		if (dep_table->entries[i].clk >= clock) {
--			*voltage |= (dep_table->entries[i].vddc *
--					VOLTAGE_SCALE) << VDDC_SHIFT;
--			if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control)
--				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
--						VOLTAGE_SCALE) << VDDCI_SHIFT;
--			else if (dep_table->entries[i].vddci)
--				*voltage |= (dep_table->entries[i].vddci *
--						VOLTAGE_SCALE) << VDDCI_SHIFT;
--			else {
--				vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
--						(dep_table->entries[i].vddc -
--								(uint16_t)data->vddc_vddci_delta));
--				*voltage |= (vddci * VOLTAGE_SCALE) <<	VDDCI_SHIFT;
--			}
--
--			if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control)
--				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
--					VOLTAGE_SCALE;
--			else if (dep_table->entries[i].mvdd)
--				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
--					VOLTAGE_SCALE;
--
--			*voltage |= 1 << PHASES_SHIFT;
--			return 0;
--		}
--	}
--
--	/* sclk is bigger than max sclk in the dependence table */
--	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
--
--	if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control)
--		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
--				VOLTAGE_SCALE) << VDDCI_SHIFT;
--	else if (dep_table->entries[i-1].vddci) {
--		vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
--				(dep_table->entries[i].vddc -
--						(uint16_t)data->vddc_vddci_delta));
--		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
--	}
--
--	if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control)
--		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
--	else if (dep_table->entries[i].mvdd)
--		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
--
--	return 0;
--}
--
--sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
--						{VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
--						{VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
--						{VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
--						{VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
--						{VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
--						{VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
--						{VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
--
--static void ellesmere_get_sclk_range_table(struct pp_hwmgr *hwmgr)
--{
--	uint32_t i, ref_clk;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
--	struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
--
--	ref_clk = ellesemere_get_xclk(hwmgr);
--
--	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
--		for (i = 0; i < NUM_SCLK_RANGE; i++) {
--			table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
--			table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
--			table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
--
--			table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
--			table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
--
--			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
--			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
--			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
--		}
--		return;
--	}
--
--	for (i = 0; i < NUM_SCLK_RANGE; i++) {
--
--		data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
--		data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
--
--		table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
--		table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
--		table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
--
--		table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
--		table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
--
--		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
--		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
--		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
--	}
--}
--
--/**
--* Populates single SMC SCLK structure using the provided engine clock
--*
--* @param    hwmgr      the address of the hardware manager
--* @param    clock the engine clock to use to populate the structure
--* @param    sclk        the SMC SCLK structure to be populated
--*/
--
--static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
--		uint32_t clock, uint16_t sclk_al_threshold,
--		struct SMU74_Discrete_GraphicsLevel *level)
--{
--	int result, i, temp;
--	/* PP_Clocks minClocks; */
--	uint32_t mvdd;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	SMU_SclkSetting curr_sclk_setting = { 0 };
--
--	result = ellesmere_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
--
--	/* populate graphics levels */
--	result = ellesmere_get_dependency_volt_by_clk(hwmgr,
--			table_info->vdd_dep_on_sclk, clock,
--			&level->MinVoltage, &mvdd);
--
--	PP_ASSERT_WITH_CODE((0 == result),
--			"can not find VDDC voltage value for "
--			"VDDC engine clock dependency table",
--			return result);
--	level->ActivityLevel = sclk_al_threshold;
--
--	level->CcPwrDynRm = 0;
--	level->CcPwrDynRm1 = 0;
--	level->EnabledForActivity = 0;
--	level->EnabledForThrottle = 1;
--	level->UpHyst = 10;
--	level->DownHyst = 0;
--	level->VoltageDownHyst = 0;
--	level->PowerThrottle = 0;
--
--	/*
--	* TODO: get minimum clocks from dal configaration
--	* PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
--	*/
--	/* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
--
--	/* get level->DeepSleepDivId
--	if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
--		level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
--	*/
--	PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
--	for (i = ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
--		temp = clock / (1UL << i);
--
--		if (temp >= 2500 || i == 0)
--			break;
--	}
--
--	level->DeepSleepDivId = i;
--
--	/* Default to slow, highest DPM level will be
--	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
--	 */
--	if (data->update_up_hyst)
--		level->UpHyst = (uint8_t)data->up_hyst;
--	if (data->update_down_hyst)
--		level->DownHyst = (uint8_t)data->down_hyst;
--
--	level->SclkSetting = curr_sclk_setting;
--
--	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
--	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
--	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
--	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
--	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
--	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
--	return 0;
--}
--
--/**
--* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
--*
--* @param    hwmgr      the address of the hardware manager
--*/
--static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
--	uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
--	int result = 0;
--	uint32_t array = data->dpm_table_start +
--			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
--	uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
--			SMU74_MAX_LEVELS_GRAPHICS;
--	struct SMU74_Discrete_GraphicsLevel *levels =
--			data->smc_state_table.GraphicsLevel;
--	uint32_t i, max_entry;
--	uint8_t hightest_pcie_level_enabled = 0,
--		lowest_pcie_level_enabled = 0,
--		mid_pcie_level_enabled = 0,
--		count = 0;
--
--	ellesmere_get_sclk_range_table(hwmgr);
--
--	for (i = 0; i < dpm_table->sclk_table.count; i++) {
--
--		result = ellesmere_populate_single_graphic_level(hwmgr,
--				dpm_table->sclk_table.dpm_levels[i].value,
--				(uint16_t)data->activity_target[i],
--				&(data->smc_state_table.GraphicsLevel[i]));
--		if (result)
--			return result;
--
--		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
--		if (i > 1)
--			levels[i].DeepSleepDivId = 0;
--	}
--
--	data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
--	data->smc_state_table.GraphicsDpmLevelCount =
--			(uint8_t)dpm_table->sclk_table.count;
--	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
--			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
--
--
--	if (pcie_table != NULL) {
--		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
--				"There must be 1 or more PCIE levels defined in PPTable.",
--				return -EINVAL);
--		max_entry = pcie_entry_cnt - 1;
--		for (i = 0; i < dpm_table->sclk_table.count; i++)
--			levels[i].pcieDpmLevel =
--					(uint8_t) ((i < max_entry) ? i : max_entry);
--	} else {
--		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
--				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
--						(1 << (hightest_pcie_level_enabled + 1))) != 0))
--			hightest_pcie_level_enabled++;
--
--		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
--				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
--						(1 << lowest_pcie_level_enabled)) == 0))
--			lowest_pcie_level_enabled++;
--
--		while ((count < hightest_pcie_level_enabled) &&
--				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
--						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
--			count++;
--
--		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
--				hightest_pcie_level_enabled ?
--						(lowest_pcie_level_enabled + 1 + count) :
--						hightest_pcie_level_enabled;
--
--		/* set pcieDpmLevel to hightest_pcie_level_enabled */
--		for (i = 2; i < dpm_table->sclk_table.count; i++)
--			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
--
--		/* set pcieDpmLevel to lowest_pcie_level_enabled */
--		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
--
--		/* set pcieDpmLevel to mid_pcie_level_enabled */
--		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
--	}
--	/* level count will send to smc once at init smc table and never change */
--	result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
--			(uint32_t)array_size, data->sram_end);
--
--	return result;
--}
--
--static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr,
--		uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	int result = 0;
--	struct cgs_display_info info = {0, 0, NULL};
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--
--	if (table_info->vdd_dep_on_mclk) {
--		result = ellesmere_get_dependency_volt_by_clk(hwmgr,
--				table_info->vdd_dep_on_mclk, clock,
--				&mem_level->MinVoltage, &mem_level->MinMvdd);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"can not find MinVddc voltage value from memory "
--				"VDDC voltage dependency table", return result);
--	}
--
--	mem_level->MclkFrequency = clock;
--	mem_level->StutterEnable = 0;
--	mem_level->EnabledForThrottle = 1;
--	mem_level->EnabledForActivity = 0;
--	mem_level->UpHyst = 0;
--	mem_level->DownHyst = 100;
--	mem_level->VoltageDownHyst = 0;
--	mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
--	mem_level->StutterEnable = false;
--
--	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
--
--	data->display_timing.num_existing_displays = info.display_count;
--
--	if ((data->mclk_stutter_mode_threshold) &&
--		(clock <= data->mclk_stutter_mode_threshold) &&
--		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
--				STUTTER_ENABLE) & 0x1))
--		mem_level->StutterEnable = true;
--
--	if (!result) {
--		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
--		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
--		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
--		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
--	}
--	return result;
--}
--
--/**
--* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
--*
--* @param    hwmgr      the address of the hardware manager
--*/
--static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
--	int result;
--	/* populate MCLK dpm table to SMU7 */
--	uint32_t array = data->dpm_table_start +
--			offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
--	uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
--			SMU74_MAX_LEVELS_MEMORY;
--	struct SMU74_Discrete_MemoryLevel *levels =
--			data->smc_state_table.MemoryLevel;
--	uint32_t i;
--
--	for (i = 0; i < dpm_table->mclk_table.count; i++) {
--		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
--				"can not populate memory level as memory clock is zero",
--				return -EINVAL);
--		result = ellesmere_populate_single_memory_level(hwmgr,
--				dpm_table->mclk_table.dpm_levels[i].value,
--				&levels[i]);
--		if (result)
--			return result;
--	}
--
--	/* Only enable level 0 for now. */
--	levels[0].EnabledForActivity = 1;
--
--	/* in order to prevent MC activity from stutter mode to push DPM up.
--	 * the UVD change complements this by putting the MCLK in
--	 * a higher state by default such that we are not effected by
--	 * up threshold or and MCLK DPM latency.
--	 */
--	levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
--	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
--
--	data->smc_state_table.MemoryDpmLevelCount =
--			(uint8_t)dpm_table->mclk_table.count;
--	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
--			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
--	/* set highest level watermark to high */
--	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
--			PPSMC_DISPLAY_WATERMARK_HIGH;
--
--	/* level count will send to smc once at init smc table and never change */
--	result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
--			(uint32_t)array_size, data->sram_end);
--
--	return result;
--}
--
--/**
--* Populates the SMC MVDD structure using the provided memory clock.
--*
--* @param    hwmgr      the address of the hardware manager
--* @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
--* @param    voltage     the SMC VOLTAGE structure to be populated
--*/
--int ellesmere_populate_mvdd_value(struct pp_hwmgr *hwmgr,
--		uint32_t mclk, SMIO_Pattern *smio_pat)
--{
--	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	uint32_t i = 0;
--
--	if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
--		/* find mvdd value which clock is more than request */
--		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
--			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
--				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
--				break;
--			}
--		}
--		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
--				"MVDD Voltage is outside the supported range.",
--				return -EINVAL);
--	} else
--		return -EINVAL;
--
--	return 0;
--}
--
--static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
--		SMU74_Discrete_DpmTable *table)
--{
--	int result = 0;
--	uint32_t sclk_frequency;
--	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	SMIO_Pattern vol_level;
--	uint32_t mvdd;
--	uint16_t us_mvdd;
--
--	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
--
--	if (!data->sclk_dpm_key_disabled) {
--		/* Get MinVoltage and Frequency from DPM0,
--		 * already converted to SMC_UL */
--		sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
--		result = ellesmere_get_dependency_volt_by_clk(hwmgr,
--				table_info->vdd_dep_on_sclk,
--				table->ACPILevel.SclkFrequency,
--				&table->ACPILevel.MinVoltage, &mvdd);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Cannot find ACPI VDDC voltage value "
--				"in Clock Dependency Table", );
--	} else {
--		sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
--		table->ACPILevel.MinVoltage =
--				data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
--	}
--
--	result = ellesmere_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
--	PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
--
--	table->ACPILevel.DeepSleepDivId = 0;
--	table->ACPILevel.CcPwrDynRm = 0;
--	table->ACPILevel.CcPwrDynRm1 = 0;
--
--	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
--
--	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
--	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
--
--	if (!data->mclk_dpm_key_disabled) {
--		/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
--		table->MemoryACPILevel.MclkFrequency =
--				data->dpm_table.mclk_table.dpm_levels[0].value;
--		result = ellesmere_get_dependency_volt_by_clk(hwmgr,
--				table_info->vdd_dep_on_mclk,
--				table->MemoryACPILevel.MclkFrequency,
--				&table->MemoryACPILevel.MinVoltage, &mvdd);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Cannot find ACPI VDDCI voltage value "
--				"in Clock Dependency Table",
--				);
--	} else {
--		table->MemoryACPILevel.MclkFrequency =
--				data->vbios_boot_state.mclk_bootup_value;
--		table->MemoryACPILevel.MinVoltage =
--				data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
--	}
--
--	us_mvdd = 0;
--	if ((ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
--			(data->mclk_dpm_key_disabled))
--		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
--	else {
--		if (!ellesmere_populate_mvdd_value(hwmgr,
--				data->dpm_table.mclk_table.dpm_levels[0].value,
--				&vol_level))
--			us_mvdd = vol_level.Voltage;
--	}
--
--	if (0 == ellesmere_populate_mvdd_value(hwmgr, 0, &vol_level))
--		table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
--	else
--		table->MemoryACPILevel.MinMvdd = 0;
--
--	table->MemoryACPILevel.StutterEnable = false;
--
--	table->MemoryACPILevel.EnabledForThrottle = 0;
--	table->MemoryACPILevel.EnabledForActivity = 0;
--	table->MemoryACPILevel.UpHyst = 0;
--	table->MemoryACPILevel.DownHyst = 100;
--	table->MemoryACPILevel.VoltageDownHyst = 0;
--	table->MemoryACPILevel.ActivityLevel =
--			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
--
--	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
--
--	return result;
--}
--
--static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
--		SMU74_Discrete_DpmTable *table)
--{
--	int result = -EINVAL;
--	uint8_t count;
--	struct pp_atomctrl_clock_dividers_vi dividers;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
--			table_info->mm_dep_table;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	table->VceLevelCount = (uint8_t)(mm_table->count);
--	table->VceBootLevel = 0;
--
--	for (count = 0; count < table->VceLevelCount; count++) {
--		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
--		table->VceLevel[count].MinVoltage |=
--				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
--		table->VceLevel[count].MinVoltage |=
--				((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
--						VOLTAGE_SCALE) << VDDCI_SHIFT;
--		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
--
--		/*retrieve divider value for VBIOS */
--		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
--				table->VceLevel[count].Frequency, &dividers);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"can not find divide id for VCE engine clock",
--				return result);
--
--		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
--
--		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
--		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
--	}
--	return result;
--}
--
--static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
--		SMU74_Discrete_DpmTable *table)
--{
--	int result = -EINVAL;
--	uint8_t count;
--	struct pp_atomctrl_clock_dividers_vi dividers;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
--			table_info->mm_dep_table;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	table->SamuBootLevel = 0;
--	table->SamuLevelCount = (uint8_t)(mm_table->count);
--
--	for (count = 0; count < table->SamuLevelCount; count++) {
--		/* not sure whether we need evclk or not */
--		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
--		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
--				VOLTAGE_SCALE) << VDDC_SHIFT;
--		table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
--				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
--		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
--
--		/* retrieve divider value for VBIOS */
--		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
--				table->SamuLevel[count].Frequency, &dividers);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"can not find divide id for samu clock", return result);
--
--		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
--
--		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
--		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
--	}
--	return result;
--}
--
--static int ellesmere_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
--		int32_t eng_clock, int32_t mem_clock,
--		SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
--{
--	uint32_t dram_timing;
--	uint32_t dram_timing2;
--	uint32_t burst_time;
--	int result;
--
--	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
--			eng_clock, mem_clock);
--	PP_ASSERT_WITH_CODE(result == 0,
--			"Error calling VBIOS to set DRAM_TIMING.", return result);
--
--	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
--	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
--	burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
--
--
--	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
--	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
--	arb_regs->McArbBurstTime   = (uint8_t)burst_time;
--
--	return 0;
--}
--
--static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
--	uint32_t i, j;
--	int result = 0;
--
--	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
--		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
--			result = ellesmere_populate_memory_timing_parameters(hwmgr,
--					data->dpm_table.sclk_table.dpm_levels[i].value,
--					data->dpm_table.mclk_table.dpm_levels[j].value,
--					&arb_regs.entries[i][j]);
--			if (result == 0)
--				result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
--			if (result != 0)
--				return result;
--		}
--	}
--
--	result = ellesmere_copy_bytes_to_smc(
--			hwmgr->smumgr,
--			data->arb_table_start,
--			(uint8_t *)&arb_regs,
--			sizeof(SMU74_Discrete_MCArbDramTimingTable),
--			data->sram_end);
--	return result;
--}
--
--static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	int result = -EINVAL;
--	uint8_t count;
--	struct pp_atomctrl_clock_dividers_vi dividers;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
--			table_info->mm_dep_table;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	table->UvdLevelCount = (uint8_t)(mm_table->count);
--	table->UvdBootLevel = 0;
--
--	for (count = 0; count < table->UvdLevelCount; count++) {
--		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
--		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
--		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
--				VOLTAGE_SCALE) << VDDC_SHIFT;
--		table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
--				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
--		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
--
--		/* retrieve divider value for VBIOS */
--		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
--				table->UvdLevel[count].VclkFrequency, &dividers);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"can not find divide id for Vclk clock", return result);
--
--		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
--
--		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
--				table->UvdLevel[count].DclkFrequency, &dividers);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"can not find divide id for Dclk clock", return result);
--
--		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
--
--		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
--		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
--		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
--
--	}
--	return result;
--}
--
--static int ellesmere_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	int result = 0;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	table->GraphicsBootLevel = 0;
--	table->MemoryBootLevel = 0;
--
--	/* find boot level from dpm table */
--	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
--			data->vbios_boot_state.sclk_bootup_value,
--			(uint32_t *)&(table->GraphicsBootLevel));
--
--	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
--			data->vbios_boot_state.mclk_bootup_value,
--			(uint32_t *)&(table->MemoryBootLevel));
--
--	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
--			VOLTAGE_SCALE;
--	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
--			VOLTAGE_SCALE;
--	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
--			VOLTAGE_SCALE;
--
--	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
--	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
--	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
--
--	return 0;
--}
--
--
--static int ellesmere_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	uint8_t count, level;
--
--	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
--
--	for (level = 0; level < count; level++) {
--		if (table_info->vdd_dep_on_sclk->entries[level].clk >=
--				data->vbios_boot_state.sclk_bootup_value) {
--			data->smc_state_table.GraphicsBootLevel = level;
--			break;
--		}
--	}
--
--	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
--	for (level = 0; level < count; level++) {
--		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
--				data->vbios_boot_state.mclk_bootup_value) {
--			data->smc_state_table.MemoryBootLevel = level;
--			break;
--		}
--	}
--
--	return 0;
--}
--
--static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
--{
--	uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
--			volt_with_cks, value;
--	uint16_t clock_freq_u16;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
--			volt_offset = 0;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
--			table_info->vdd_dep_on_sclk;
--
--	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
--
--	/* Read SMU_Eefuse to read and calculate RO and determine
--	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
--	 */
--	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixSMU_EFUSE_0 + (146 * 4));
--	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixSMU_EFUSE_0 + (148 * 4));
--	efuse &= 0xFF000000;
--	efuse = efuse >> 24;
--	efuse2 &= 0xF;
--
--	if (efuse2 == 1)
--		ro = (2300 - 1350) * efuse / 255 + 1350;
--	else
--		ro = (2500 - 1000) * efuse / 255 + 1000;
--
--	if (ro >= 1660)
--		type = 0;
--	else
--		type = 1;
--
--	/* Populate Stretch amount */
--	data->smc_state_table.ClockStretcherAmount = stretch_amount;
--
--	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
--	for (i = 0; i < sclk_table->count; i++) {
--		data->smc_state_table.Sclk_CKS_masterEn0_7 |=
--				sclk_table->entries[i].cks_enable << i;
--		volt_without_cks = (uint32_t)((14041 *
--			(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
--			(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
--		volt_with_cks = (uint32_t)((13946 *
--			(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
--			(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
--		if (volt_without_cks >= volt_with_cks)
--			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
--					sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
--		data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
--	}
--
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
--			STRETCH_ENABLE, 0x0);
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
--			masterReset, 0x1);
--	/* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
--			masterReset, 0x0);
--
--	/* Populate CKS Lookup Table */
--	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
--		stretch_amount2 = 0;
--	else if (stretch_amount == 3 || stretch_amount == 4)
--		stretch_amount2 = 1;
--	else {
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_ClockStretcher);
--		PP_ASSERT_WITH_CODE(false,
--				"Stretch Amount in PPTable not supported\n",
--				return -EINVAL);
--	}
--
--	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixPWR_CKS_CNTL);
--	value &= 0xFFC2FF87;
--	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
--			ellesmere_clock_stretcher_lookup_table[stretch_amount2][0];
--	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
--			ellesmere_clock_stretcher_lookup_table[stretch_amount2][1];
--	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
--			GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
--	if (ellesmere_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
--	&& ellesmere_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
--		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
--		value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
--		/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
--		value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
--		/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
--		value |= (ellesmere_clock_stretch_amount_conversion
--				[ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]]
--				 [stretch_amount]) << 3;
--	}
--	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
--	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
--	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
--			ellesmere_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
--	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
--			(ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixPWR_CKS_CNTL, value);
--
--	/* Populate DDT Lookup Table */
--	for (i = 0; i < 4; i++) {
--		/* Assign the minimum and maximum VID stored
--		 * in the last row of Clock Stretcher Voltage Table.
--		 */
--		data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
--				(uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][2];
--		data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
--				(uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][3];
--		/* Loop through each SCLK and check the frequency
--		 * to see if it lies within the frequency for clock stretcher.
--		 */
--		for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
--			cks_setting = 0;
--			clock_freq = PP_SMC_TO_HOST_UL(
--					data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
--			/* Check the allowed frequency against the sclk level[j].
--			 *  Sclk's endianness has already been converted,
--			 *  and it's in 10Khz unit,
--			 *  as opposed to Data table, which is in Mhz unit.
--			 */
--			if (clock_freq >= (ellesmere_clock_stretcher_ddt_table[type][i][0]) * 100) {
--				cks_setting |= 0x2;
--				if (clock_freq < (ellesmere_clock_stretcher_ddt_table[type][i][1]) * 100)
--					cks_setting |= 0x1;
--			}
--			data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
--							|= cks_setting << (j * 2);
--		}
--		CONVERT_FROM_HOST_TO_SMC_US(
--			data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
--	}
--
--	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
--	value &= 0xFFFFFFFE;
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
--
--	return 0;
--}
--
--/**
--* Populates the SMC VRConfig field in DPM table.
--*
--* @param    hwmgr   the address of the hardware manager
--* @param    table   the SMC DPM table structure to be populated
--* @return   always 0
--*/
--static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr,
--		struct SMU74_Discrete_DpmTable *table)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint16_t config;
--
--	config = VR_MERGED_WITH_VDDC;
--	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
--
--	/* Set Vddc Voltage Controller */
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
--		config = VR_SVI2_PLANE_1;
--		table->VRConfig |= config;
--	} else {
--		PP_ASSERT_WITH_CODE(false,
--				"VDDC should be on SVI2 control in merged mode!",
--				);
--	}
--	/* Set Vddci Voltage Controller */
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
--		config = VR_SVI2_PLANE_2;  /* only in merged mode */
--		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
--	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
--		config = VR_SMIO_PATTERN_1;
--		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
--	} else {
--		config = VR_STATIC_VOLTAGE;
--		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
--	}
--	/* Set Mvdd Voltage Controller */
--	if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
--		config = VR_SVI2_PLANE_2;
--		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
--	} else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
--		config = VR_SMIO_PATTERN_2;
--		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
--	} else {
--		config = VR_STATIC_VOLTAGE;
--		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
--	}
--
--	return 0;
--}
--
--/**
--* Initializes the SMC table and uploads it
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--*/
--static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr)
--{
--	int result;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
--	const struct ellesmere_ulv_parm *ulv = &(data->ulv);
--	uint8_t i;
--	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
--	pp_atomctrl_clock_dividers_vi dividers;
--
--	result = ellesmere_setup_default_dpm_tables(hwmgr);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to setup default DPM tables!", return result);
--
--	if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control)
--		ellesmere_populate_smc_voltage_tables(hwmgr, table);
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_AutomaticDCTransition))
--		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_StepVddc))
--		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
--
--	if (data->is_memory_gddr5)
--		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
--
--	if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
--		result = ellesmere_populate_ulv_state(hwmgr, table);
--		PP_ASSERT_WITH_CODE(0 == result,
--				"Failed to initialize ULV state!", return result);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--				ixCG_ULV_PARAMETER, PPELLESMERE_CGULVPARAMETER_DFLT);
--	}
--
--	result = ellesmere_populate_smc_link_level(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize Link Level!", return result);
--
--	result = ellesmere_populate_all_graphic_levels(hwmgr);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize Graphics Level!", return result);
--
--	result = ellesmere_populate_all_memory_levels(hwmgr);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize Memory Level!", return result);
--
--	result = ellesmere_populate_smc_acpi_level(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize ACPI Level!", return result);
--
--	result = ellesmere_populate_smc_vce_level(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize VCE Level!", return result);
--
--	result = ellesmere_populate_smc_samu_level(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize SAMU Level!", return result);
--
--	/* Since only the initial state is completely set up at this point
--	 * (the other states are just copies of the boot state) we only
--	 * need to populate the  ARB settings for the initial state.
--	 */
--	result = ellesmere_program_memory_timing_parameters(hwmgr);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to Write ARB settings for the initial state.", return result);
--
--	result = ellesmere_populate_smc_uvd_level(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize UVD Level!", return result);
--
--	result = ellesmere_populate_smc_boot_level(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize Boot Level!", return result);
--
--	result = ellesmere_populate_smc_initailial_state(hwmgr);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to initialize Boot State!", return result);
--
--	result = ellesmere_populate_bapm_parameters_in_dpm_table(hwmgr);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to populate BAPM Parameters!", return result);
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ClockStretcher)) {
--		result = ellesmere_populate_clock_stretcher_data_table(hwmgr);
--		PP_ASSERT_WITH_CODE(0 == result,
--				"Failed to populate Clock Stretcher Data Table!",
--				return result);
--	}
--
--	table->GraphicsVoltageChangeEnable  = 1;
--	table->GraphicsThermThrottleEnable  = 1;
--	table->GraphicsInterval = 1;
--	table->VoltageInterval  = 1;
--	table->ThermalInterval  = 1;
--	table->TemperatureLimitHigh =
--			table_info->cac_dtp_table->usTargetOperatingTemp *
--			ELLESMERE_Q88_FORMAT_CONVERSION_UNIT;
--	table->TemperatureLimitLow  =
--			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
--			ELLESMERE_Q88_FORMAT_CONVERSION_UNIT;
--	table->MemoryVoltageChangeEnable = 1;
--	table->MemoryInterval = 1;
--	table->VoltageResponseTime = 0;
--	table->PhaseResponseTime = 0;
--	table->MemoryThermThrottleEnable = 1;
--	table->PCIeBootLinkLevel = 0;
--	table->PCIeGenInterval = 1;
--
--	result = ellesmere_populate_vr_config(hwmgr, table);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to populate VRConfig setting!", return result);
--
--	table->ThermGpio = 17;
--	table->SclkStepSize = 0x4000;
--
--	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
--		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
--	} else {
--		table->VRHotGpio = ELLESMERE_UNUSED_GPIO_PIN;
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_RegulatorHot);
--	}
--
--	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
--			&gpio_pin)) {
--		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
--		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_AutomaticDCTransition);
--	} else {
--		table->AcDcGpio = ELLESMERE_UNUSED_GPIO_PIN;
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_AutomaticDCTransition);
--	}
--
--	/* Thermal Output GPIO */
--	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
--			&gpio_pin)) {
--		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_ThermalOutGPIO);
--
--		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
--
--		/* For porlarity read GPIOPAD_A with assigned Gpio pin
--		 * since VBIOS will program this register to set 'inactive state',
--		 * driver can then determine 'active state' from this and
--		 * program SMU with correct polarity
--		 */
--		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
--					& (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
--		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
--
--		/* if required, combine VRHot/PCC with thermal out GPIO */
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
--		&& phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
--			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
--	} else {
--		table->ThermOutGpio = 17;
--		table->ThermOutPolarity = 1;
--		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
--	}
--
--	/* Populate BIF_SCLK levels into SMC DPM table */
--	for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
--		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
--		PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
--
--		if (i == 0)
--			table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
--		else
--			table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
--	}
--
--	for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
--		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
--
--	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
--	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
--	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
--	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
--	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
--	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
--
--	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
--	result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr,
--			data->dpm_table_start +
--			offsetof(SMU74_Discrete_DpmTable, SystemFlags),
--			(uint8_t *)&(table->SystemFlags),
--			sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
--			data->sram_end);
--	PP_ASSERT_WITH_CODE(0 == result,
--			"Failed to upload dpm data to SMC memory!", return result);
--
--	return 0;
--}
--
--/**
--* Initialize the ARB DRAM timing table's index field.
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--*/
--static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr)
--{
--	const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t tmp;
--	int result;
--
--	/* This is a read-modify-write on the first byte of the ARB table.
--	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
--	 * is the field 'current'.
--	 * This solution is ugly, but we never write the whole table only
--	 * individual fields in it.
--	 * In reality this field should not be in that structure
--	 * but in a soft register.
--	 */
--	result = ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			data->arb_table_start, &tmp, data->sram_end);
--
--	if (result)
--		return result;
--
--	tmp &= 0x00FFFFFF;
--	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
--
--	return ellesmere_write_smc_sram_dword(hwmgr->smumgr,
--			data->arb_table_start, tmp, data->sram_end);
--}
--
--static int ellesmere_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_RegulatorHot))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_EnableVRHotGPIOInterrupt);
--
--	return 0;
--}
--
--static int ellesmere_enable_sclk_control(struct pp_hwmgr *hwmgr)
--{
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
--			SCLK_PWRMGT_OFF, 0);
--	return 0;
--}
--
--static int ellesmere_enable_ulv(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_ulv_parm *ulv = &(data->ulv);
--
--	if (ulv->ulv_supported)
--		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
--
--	return 0;
--}
--
--static int ellesmere_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
--{
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SclkDeepSleep)) {
--		if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to enable Master Deep Sleep switch failed!",
--					return -1);
--	} else {
--		if (smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to disable Master Deep Sleep switch failed!",
--					return -1);
--		}
--	}
--
--	return 0;
--}
--
--static int ellesmere_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	/* enable SCLK dpm */
--	if (!data->sclk_dpm_key_disabled)
--		PP_ASSERT_WITH_CODE(
--		(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
--		"Failed to enable SCLK DPM during DPM Start Function!",
--		return -1);
--
--	/* enable MCLK dpm */
--	if (0 == data->mclk_dpm_key_disabled) {
--
--		PP_ASSERT_WITH_CODE(
--				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--						PPSMC_MSG_MCLKDPM_Enable)),
--				"Failed to enable MCLK DPM during DPM Start Function!",
--				return -1);
--
--
--		PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
--
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
--		udelay(10);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
--	}
--
--	return 0;
--}
--
--static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	/*enable general power management */
--
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
--			GLOBAL_PWRMGT_EN, 1);
--
--	/* enable sclk deep sleep */
--
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
--			DYNAMIC_PM_EN, 1);
--
--	/* prepare for PCIE DPM */
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			data->soft_regs_start + offsetof(SMU74_SoftRegisters,
--					VoltageChangeTimeout), 0x1000);
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
--			SWRST_COMMAND_1, RESETLC, 0x0);
--/*
--	PP_ASSERT_WITH_CODE(
--			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--					PPSMC_MSG_Voltage_Cntl_Enable)),
--			"Failed to enable voltage DPM during DPM Start Function!",
--			return -1);
--*/
--
--	if (ellesmere_enable_sclk_mclk_dpm(hwmgr)) {
--		printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
--		return -1;
--	}
--
--	/* enable PCIE dpm */
--	if (0 == data->pcie_dpm_key_disabled) {
--		PP_ASSERT_WITH_CODE(
--				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--						PPSMC_MSG_PCIeDPM_Enable)),
--				"Failed to enable pcie DPM during DPM Start Function!",
--				return -1);
--	}
--
--	PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
--					PPSMC_MSG_EnableACDCGPIOInterrupt)),
--					"Failed to enable AC DC GPIO Interrupt!",
--			);
--
--	return 0;
--}
--
--static void ellesmere_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
--{
--	bool protection;
--	enum DPM_EVENT_SRC src;
--
--	switch (sources) {
--	default:
--		printk(KERN_ERR "Unknown throttling event sources.");
--		/* fall through */
--	case 0:
--		protection = false;
--		/* src is unused */
--		break;
--	case (1 << PHM_AutoThrottleSource_Thermal):
--		protection = true;
--		src = DPM_EVENT_SRC_DIGITAL;
--		break;
--	case (1 << PHM_AutoThrottleSource_External):
--		protection = true;
--		src = DPM_EVENT_SRC_EXTERNAL;
--		break;
--	case (1 << PHM_AutoThrottleSource_External) |
--			(1 << PHM_AutoThrottleSource_Thermal):
--		protection = true;
--		src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
--		break;
--	}
--	/* Order matters - don't enable thermal protection for the wrong source. */
--	if (protection) {
--		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
--				DPM_EVENT_SRC, src);
--		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
--				THERMAL_PROTECTION_DIS,
--				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_ThermalController));
--	} else
--		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
--				THERMAL_PROTECTION_DIS, 1);
--}
--
--static int ellesmere_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
--		PHM_AutoThrottleSource source)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (!(data->active_auto_throttle_sources & (1 << source))) {
--		data->active_auto_throttle_sources |= 1 << source;
--		ellesmere_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
--	}
--	return 0;
--}
--
--static int ellesmere_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
--{
--	return ellesmere_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
--}
--
--int ellesmere_pcie_performance_request(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	data->pcie_performance_request = true;
--
--	return 0;
--}
--
--int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
--{
--	int tmp_result, result = 0;
--	tmp_result = (!ellesmere_is_dpm_running(hwmgr)) ? 0 : -1;
--	PP_ASSERT_WITH_CODE(result == 0,
--			"DPM is already running right now, no need to enable DPM!",
--			return 0);
--
--	if (ellesmere_voltage_control(hwmgr)) {
--		tmp_result = ellesmere_enable_voltage_control(hwmgr);
--		PP_ASSERT_WITH_CODE(tmp_result == 0,
--				"Failed to enable voltage control!",
--				result = tmp_result);
--
--		tmp_result = ellesmere_construct_voltage_tables(hwmgr);
--		PP_ASSERT_WITH_CODE((0 == tmp_result),
--				"Failed to contruct voltage tables!",
--				result = tmp_result);
--	}
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_EngineSpreadSpectrumSupport))
--		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--				GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ThermalController))
--		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--				GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
--
--	tmp_result = ellesmere_program_static_screen_threshold_parameters(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to program static screen threshold parameters!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_enable_display_gap(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable display gap!", result = tmp_result);
--
--	tmp_result = ellesmere_program_voting_clients(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to program voting clients!", result = tmp_result);
--
--	tmp_result = ellesmere_process_firmware_header(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to process firmware header!", result = tmp_result);
--
--	tmp_result = ellesmere_initial_switch_from_arbf0_to_f1(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to initialize switch from ArbF0 to F1!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_init_smc_table(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to initialize SMC table!", result = tmp_result);
--
--	tmp_result = ellesmere_init_arb_table_index(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to initialize ARB table index!", result = tmp_result);
--
--	tmp_result = ellesmere_populate_pm_fuses(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to populate PM fuses!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_vrhot_gpio_interrupt(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_sclk_control(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable SCLK control!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_smc_voltage_controller(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable voltage control!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_ulv(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable ULV!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_deep_sleep_master_switch(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable deep sleep master switch!", result = tmp_result);
--
--	tmp_result = ellesmere_start_dpm(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to start DPM!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_smc_cac(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable SMC CAC!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_power_containment(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable power containment!", result = tmp_result);
--
--	tmp_result = ellesmere_power_control_set_level(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to power control set level!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_thermal_auto_throttle(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable thermal auto throttle!", result = tmp_result);
--
--	tmp_result = ellesmere_pcie_performance_request(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable thermal auto throttle!", result = tmp_result);
--
--	return result;
--}
--
--int ellesmere_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
--{
--
--	return 0;
--}
--
--int ellesmere_reset_asic_tasks(struct pp_hwmgr *hwmgr)
--{
--
--	return 0;
--}
--
--int ellesmere_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
--{
--	return phm_hwmgr_backend_fini(hwmgr);
--}
--
--int ellesmere_set_features_platform_caps(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SclkDeepSleep);
--
--	if (data->mvdd_control == ELLESMERE_VOLTAGE_CONTROL_NONE)
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_EnableMVDDControl);
--
--	if (data->vddci_control == ELLESMERE_VOLTAGE_CONTROL_NONE)
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_ControlVDDCI);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			 PHM_PlatformCaps_TablelessHardwareInterface);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_EnableSMU7ThermalManagement);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_DynamicPowerManagement);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_TablelessHardwareInterface);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_SMC);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_NonABMSupportInPPLib);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_DynamicUVDState);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_SclkThrottleLowNotification);
--
--	/* power tune caps Assume disabled */
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_PowerContainment);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--							PHM_PlatformCaps_CAC);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_SQRamping);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_DBRamping);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_TDRamping);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_TCPRamping);
--
--	return 0;
--}
--
--static void ellesmere_init_dpm_defaults(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	ellesmere_initialize_power_tune_defaults(hwmgr);
--
--	data->pcie_gen_performance.max = PP_PCIEGen1;
--	data->pcie_gen_performance.min = PP_PCIEGen3;
--	data->pcie_gen_power_saving.max = PP_PCIEGen1;
--	data->pcie_gen_power_saving.min = PP_PCIEGen3;
--	data->pcie_lane_performance.max = 0;
--	data->pcie_lane_performance.min = 16;
--	data->pcie_lane_power_saving.max = 0;
--	data->pcie_lane_power_saving.min = 16;
--}
--
--/**
--* Get Leakage VDDC based on leakage ID.
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always 0
--*/
--static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint16_t vv_id;
--	uint16_t vddc = 0;
--	uint16_t i, j;
--	uint32_t sclk = 0;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)hwmgr->pptable;
--	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
--			table_info->vdd_dep_on_sclk;
--	int result;
--
--	for (i = 0; i < ELLESMERE_MAX_LEAKAGE_COUNT; i++) {
--		vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
--		if (!phm_get_sclk_for_voltage_evv(hwmgr,
--				table_info->vddc_lookup_table, vv_id, &sclk)) {
--			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_ClockStretcher)) {
--				for (j = 1; j < sclk_table->count; j++) {
--					if (sclk_table->entries[j].clk == sclk &&
--							sclk_table->entries[j].cks_enable == 0) {
--						sclk += 5000;
--						break;
--					}
--				}
--			}
--
--
--			PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
--							VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
--						"Error retrieving EVV voltage value!",
--						continue);
--
--
--			/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
--			PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
--					"Invalid VDDC value", result = -EINVAL;);
--
--			/* the voltage should not be zero nor equal to leakage ID */
--			if (vddc != 0 && vddc != vv_id) {
--				data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
--				data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
--				data->vddc_leakage.count++;
--			}
--		}
--	}
--
--	return 0;
--}
--
--/**
-- * Change virtual leakage voltage to actual value.
-- *
-- * @param     hwmgr  the address of the powerplay hardware manager.
-- * @param     pointer to changing voltage
-- * @param     pointer to leakage table
-- */
--static void ellesmere_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
--		uint16_t *voltage, struct ellesmere_leakage_voltage *leakage_table)
--{
--	uint32_t index;
--
--	/* search for leakage voltage ID 0xff01 ~ 0xff08 */
--	for (index = 0; index < leakage_table->count; index++) {
--		/* if this voltage matches a leakage voltage ID */
--		/* patch with actual leakage voltage */
--		if (leakage_table->leakage_id[index] == *voltage) {
--			*voltage = leakage_table->actual_voltage[index];
--			break;
--		}
--	}
--
--	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
--		printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
--}
--
--/**
--* Patch voltage lookup table by EVV leakages.
--*
--* @param     hwmgr  the address of the powerplay hardware manager.
--* @param     pointer to voltage lookup table
--* @param     pointer to leakage table
--* @return     always 0
--*/
--static int ellesmere_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
--		phm_ppt_v1_voltage_lookup_table *lookup_table,
--		struct ellesmere_leakage_voltage *leakage_table)
--{
--	uint32_t i;
--
--	for (i = 0; i < lookup_table->count; i++)
--		ellesmere_patch_with_vdd_leakage(hwmgr,
--				&lookup_table->entries[i].us_vdd, leakage_table);
--
--	return 0;
--}
--
--static int ellesmere_patch_clock_voltage_limits_with_vddc_leakage(
--		struct pp_hwmgr *hwmgr, struct ellesmere_leakage_voltage *leakage_table,
--		uint16_t *vddc)
--{
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	ellesmere_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
--	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
--			table_info->max_clock_voltage_on_dc.vddc;
--	return 0;
--}
--
--static int ellesmere_patch_voltage_dependency_tables_with_lookup_table(
--		struct pp_hwmgr *hwmgr)
--{
--	uint8_t entryId;
--	uint8_t voltageId;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
--			table_info->vdd_dep_on_sclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
--			table_info->vdd_dep_on_mclk;
--	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
--			table_info->mm_dep_table;
--
--	for (entryId = 0; entryId < sclk_table->count; ++entryId) {
--		voltageId = sclk_table->entries[entryId].vddInd;
--		sclk_table->entries[entryId].vddc =
--				table_info->vddc_lookup_table->entries[voltageId].us_vdd;
--	}
--
--	for (entryId = 0; entryId < mclk_table->count; ++entryId) {
--		voltageId = mclk_table->entries[entryId].vddInd;
--		mclk_table->entries[entryId].vddc =
--			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
--	}
--
--	for (entryId = 0; entryId < mm_table->count; ++entryId) {
--		voltageId = mm_table->entries[entryId].vddcInd;
--		mm_table->entries[entryId].vddc =
--			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
--	}
--
--	return 0;
--
--}
--
--static int ellesmere_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
--{
--	/* Need to determine if we need calculated voltage. */
--	return 0;
--}
--
--static int ellesmere_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
--{
--	/* Need to determine if we need calculated voltage from mm table. */
--	return 0;
--}
--
--static int ellesmere_sort_lookup_table(struct pp_hwmgr *hwmgr,
--		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
--{
--	uint32_t table_size, i, j;
--	struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
--	table_size = lookup_table->count;
--
--	PP_ASSERT_WITH_CODE(0 != lookup_table->count,
--		"Lookup table is empty", return -EINVAL);
--
--	/* Sorting voltages */
--	for (i = 0; i < table_size - 1; i++) {
--		for (j = i + 1; j > 0; j--) {
--			if (lookup_table->entries[j].us_vdd <
--					lookup_table->entries[j - 1].us_vdd) {
--				tmp_voltage_lookup_record = lookup_table->entries[j - 1];
--				lookup_table->entries[j - 1] = lookup_table->entries[j];
--				lookup_table->entries[j] = tmp_voltage_lookup_record;
--			}
--		}
--	}
--
--	return 0;
--}
--
--static int ellesmere_complete_dependency_tables(struct pp_hwmgr *hwmgr)
--{
--	int result = 0;
--	int tmp_result;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	tmp_result = ellesmere_patch_lookup_table_with_leakage(hwmgr,
--			table_info->vddc_lookup_table, &(data->vddc_leakage));
--	if (tmp_result)
--		result = tmp_result;
--
--	tmp_result = ellesmere_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
--			&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
--	if (tmp_result)
--		result = tmp_result;
--
--	tmp_result = ellesmere_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
--	if (tmp_result)
--		result = tmp_result;
--
--	tmp_result = ellesmere_calc_voltage_dependency_tables(hwmgr);
--	if (tmp_result)
--		result = tmp_result;
--
--	tmp_result = ellesmere_calc_mm_voltage_dependency_table(hwmgr);
--	if (tmp_result)
--		result = tmp_result;
--
--	tmp_result = ellesmere_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
--	if (tmp_result)
--		result = tmp_result;
--
--	return result;
--}
--
--static int ellesmere_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
--{
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
--						table_info->vdd_dep_on_sclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
--						table_info->vdd_dep_on_mclk;
--
--	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
--		"VDD dependency on SCLK table is missing. 	\
--		This table is mandatory", return -EINVAL);
--	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
--		"VDD dependency on SCLK table has to have is missing. 	\
--		This table is mandatory", return -EINVAL);
--
--	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
--		"VDD dependency on MCLK table is missing. 	\
--		This table is mandatory", return -EINVAL);
--	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
--		"VDD dependency on MCLK table has to have is missing.	 \
--		This table is mandatory", return -EINVAL);
--
--	table_info->max_clock_voltage_on_ac.sclk =
--		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
--	table_info->max_clock_voltage_on_ac.mclk =
--		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
--	table_info->max_clock_voltage_on_ac.vddc =
--		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
--	table_info->max_clock_voltage_on_ac.vddci =
--		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
--
--	return 0;
--}
--
--int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
--	uint32_t temp_reg;
--	int result;
--
--	data->dll_default_on = false;
--	data->sram_end = SMC_RAM_END;
--
--	data->disable_dpm_mask = 0xFF;
--	data->static_screen_threshold = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT;
--	data->static_screen_threshold_unit = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT;
--	data->activity_target[0] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[1] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[2] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[3] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[4] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[5] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[6] = PPELLESMERE_TARGETACTIVITY_DFLT;
--	data->activity_target[7] = PPELLESMERE_TARGETACTIVITY_DFLT;
--
--	data->voting_rights_clients0 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0;
--	data->voting_rights_clients1 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1;
--	data->voting_rights_clients2 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2;
--	data->voting_rights_clients3 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3;
--	data->voting_rights_clients4 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4;
--	data->voting_rights_clients5 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5;
--	data->voting_rights_clients6 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6;
--	data->voting_rights_clients7 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7;
--
--	data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
--
--	data->mclk_activity_target = PPELLESMERE_MCLK_TARGETACTIVITY_DFLT;
--
--	/* need to set voltage control types before EVV patching */
--	data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
--	data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
--	data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_NONE;
--
--	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
--			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
--		data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_DynamicPatchPowerState);
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_EnableMVDDControl)) {
--		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
--				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
--			data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO;
--		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
--				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
--			data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
--	}
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ControlVDDCI)) {
--		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
--				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
--			data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO;
--		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
--				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
--			data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2;
--	}
--
--	ellesmere_set_features_platform_caps(hwmgr);
--
--	ellesmere_init_dpm_defaults(hwmgr);
--
--	/* Get leakage voltage based on leakage ID. */
--	result = ellesmere_get_evv_voltages(hwmgr);
--
--	if (result) {
--		printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
--		return -1;
--	}
--
--	ellesmere_complete_dependency_tables(hwmgr);
--	ellesmere_set_private_data_based_on_pptable(hwmgr);
--
--	/* Initalize Dynamic State Adjustment Rule Settings */
--	result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
--
--	if (0 == result) {
--		struct cgs_system_info sys_info = {0};
--
--		data->is_tlu_enabled = 0;
--
--		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
--							ELLESMERE_MAX_HARDWARE_POWERLEVELS;
--		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
--		hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
--		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
--/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
--		hwmgr->platform_descriptor.clockStep.engineClock = 500;
--		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
--
--		if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
--			temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
--			switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
--			case 0:
--				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
--				break;
--			case 1:
--				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
--				break;
--			case 2:
--				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
--				break;
--			case 3:
--				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
--				break;
--			case 4:
--				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
--				break;
--			default:
--				PP_ASSERT_WITH_CODE(0,
--				"Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
--				);
--				break;
--			}
--			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
--		}
--
--		sys_info.size = sizeof(struct cgs_system_info);
--		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
--		result = cgs_query_system_info(hwmgr->device, &sys_info);
--		if (result)
--			data->pcie_gen_cap = 0x30007;
--		else
--			data->pcie_gen_cap = (uint32_t)sys_info.value;
--		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
--			data->pcie_spc_cap = 20;
--		sys_info.size = sizeof(struct cgs_system_info);
--		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
--		result = cgs_query_system_info(hwmgr->device, &sys_info);
--		if (result)
--			data->pcie_lane_cap = 0x2f0000;
--		else
--			data->pcie_lane_cap = (uint32_t)sys_info.value;
--	} else {
--		/* Ignore return value in here, we are cleaning up a mess. */
--		ellesmere_hwmgr_backend_fini(hwmgr);
--	}
--
--	return 0;
--}
--
--static int ellesmere_force_dpm_highest(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t level, tmp;
--
--	if (!data->pcie_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
--			level = 0;
--			tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
--			while (tmp >>= 1)
--				level++;
--
--			if (level)
--				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						PPSMC_MSG_PCIeDPM_ForceLevel, level);
--		}
--	}
--
--	if (!data->sclk_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
--			level = 0;
--			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
--			while (tmp >>= 1)
--				level++;
--
--			if (level)
--				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						PPSMC_MSG_SCLKDPM_SetEnabledMask,
--						(1 << level));
--		}
--	}
--
--	if (!data->mclk_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
--			level = 0;
--			tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
--			while (tmp >>= 1)
--				level++;
--
--			if (level)
--				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						PPSMC_MSG_MCLKDPM_SetEnabledMask,
--						(1 << level));
--		}
--	}
--
--	return 0;
--}
--
--static int ellesmere_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	phm_apply_dal_min_voltage_request(hwmgr);
--
--	if (!data->sclk_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
--	}
--
--	if (!data->mclk_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					data->dpm_level_enable_mask.mclk_dpm_enable_mask);
--	}
--
--	return 0;
--}
--
--static int ellesmere_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (!ellesmere_is_dpm_running(hwmgr))
--		return -EINVAL;
--
--	if (!data->pcie_dpm_key_disabled) {
--		smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_PCIeDPM_UnForceLevel);
--	}
--
--	return ellesmere_upload_dpm_level_enable_mask(hwmgr);
--}
--
--static int ellesmere_force_dpm_lowest(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data =
--			(struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t level;
--
--	if (!data->sclk_dpm_key_disabled)
--		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
--			level = phm_get_lowest_enabled_level(hwmgr,
--							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--							    PPSMC_MSG_SCLKDPM_SetEnabledMask,
--							    (1 << level));
--
--	}
--/* uvd is enabled, can't set mclk low right now
--	if (!data->mclk_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
--			level = phm_get_lowest_enabled_level(hwmgr,
--							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--							    PPSMC_MSG_MCLKDPM_SetEnabledMask,
--							    (1 << level));
--		}
--	}
--*/
--	if (!data->pcie_dpm_key_disabled) {
--		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
--			level = phm_get_lowest_enabled_level(hwmgr,
--							      data->dpm_level_enable_mask.pcie_dpm_enable_mask);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--							    PPSMC_MSG_PCIeDPM_ForceLevel,
--							    (level));
--		}
--	}
--
--	return 0;
--
--}
--static int ellesmere_force_dpm_level(struct pp_hwmgr *hwmgr,
--				enum amd_dpm_forced_level level)
--{
--	int ret = 0;
--
--	switch (level) {
--	case AMD_DPM_FORCED_LEVEL_HIGH:
--		ret = ellesmere_force_dpm_highest(hwmgr);
--		if (ret)
--			return ret;
--		break;
--	case AMD_DPM_FORCED_LEVEL_LOW:
--		ret = ellesmere_force_dpm_lowest(hwmgr);
--		if (ret)
--			return ret;
--		break;
--	case AMD_DPM_FORCED_LEVEL_AUTO:
--		ret = ellesmere_unforce_dpm_levels(hwmgr);
--		if (ret)
--			return ret;
--		break;
--	default:
--		break;
--	}
--
--	hwmgr->dpm_level = level;
--
--	return ret;
--}
--
--static int ellesmere_get_power_state_size(struct pp_hwmgr *hwmgr)
--{
--	return sizeof(struct ellesmere_power_state);
--}
--
--
--static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
--				struct pp_power_state *request_ps,
--			const struct pp_power_state *current_ps)
--{
--
--	struct ellesmere_power_state *ellesmere_ps =
--				cast_phw_ellesmere_power_state(&request_ps->hardware);
--	uint32_t sclk;
--	uint32_t mclk;
--	struct PP_Clocks minimum_clocks = {0};
--	bool disable_mclk_switching;
--	bool disable_mclk_switching_for_frame_lock;
--	struct cgs_display_info info = {0};
--	const struct phm_clock_and_voltage_limits *max_limits;
--	uint32_t i;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	int32_t count;
--	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
--
--	data->battery_state = (PP_StateUILabel_Battery ==
--			request_ps->classification.ui_label);
--
--	PP_ASSERT_WITH_CODE(ellesmere_ps->performance_level_count == 2,
--				 "VI should always have 2 performance levels",
--				);
--
--	max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
--			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
--			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
--
--	/* Cap clock DPM tables at DC MAX if it is in DC. */
--	if (PP_PowerSource_DC == hwmgr->power_source) {
--		for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
--			if (ellesmere_ps->performance_levels[i].memory_clock > max_limits->mclk)
--				ellesmere_ps->performance_levels[i].memory_clock = max_limits->mclk;
--			if (ellesmere_ps->performance_levels[i].engine_clock > max_limits->sclk)
--				ellesmere_ps->performance_levels[i].engine_clock = max_limits->sclk;
--		}
--	}
--
--	ellesmere_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
--	ellesmere_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--
--	/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
--
--	/* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_StablePState)) {
--		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
--		stable_pstate_sclk = (max_limits->sclk * 75) / 100;
--
--		for (count = table_info->vdd_dep_on_sclk->count - 1;
--				count >= 0; count--) {
--			if (stable_pstate_sclk >=
--					table_info->vdd_dep_on_sclk->entries[count].clk) {
--				stable_pstate_sclk =
--						table_info->vdd_dep_on_sclk->entries[count].clk;
--				break;
--			}
--		}
--
--		if (count < 0)
--			stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
--
--		stable_pstate_mclk = max_limits->mclk;
--
--		minimum_clocks.engineClock = stable_pstate_sclk;
--		minimum_clocks.memoryClock = stable_pstate_mclk;
--	}
--
--	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
--		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
--
--	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
--		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
--
--	ellesmere_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
--
--	if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
--		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
--				hwmgr->platform_descriptor.overdriveLimit.engineClock),
--				"Overdrive sclk exceeds limit",
--				hwmgr->gfx_arbiter.sclk_over_drive =
--						hwmgr->platform_descriptor.overdriveLimit.engineClock);
--
--		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
--			ellesmere_ps->performance_levels[1].engine_clock =
--					hwmgr->gfx_arbiter.sclk_over_drive;
--	}
--
--	if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
--		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
--				hwmgr->platform_descriptor.overdriveLimit.memoryClock),
--				"Overdrive mclk exceeds limit",
--				hwmgr->gfx_arbiter.mclk_over_drive =
--						hwmgr->platform_descriptor.overdriveLimit.memoryClock);
--
--		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
--			ellesmere_ps->performance_levels[1].memory_clock =
--					hwmgr->gfx_arbiter.mclk_over_drive;
--	}
--
--	disable_mclk_switching_for_frame_lock = phm_cap_enabled(
--				    hwmgr->platform_descriptor.platformCaps,
--				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
--
--	disable_mclk_switching = (1 < info.display_count) ||
--				    disable_mclk_switching_for_frame_lock;
--
--	sclk = ellesmere_ps->performance_levels[0].engine_clock;
--	mclk = ellesmere_ps->performance_levels[0].memory_clock;
--
--	if (disable_mclk_switching)
--		mclk = ellesmere_ps->performance_levels
--		[ellesmere_ps->performance_level_count - 1].memory_clock;
--
--	if (sclk < minimum_clocks.engineClock)
--		sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
--				max_limits->sclk : minimum_clocks.engineClock;
--
--	if (mclk < minimum_clocks.memoryClock)
--		mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
--				max_limits->mclk : minimum_clocks.memoryClock;
--
--	ellesmere_ps->performance_levels[0].engine_clock = sclk;
--	ellesmere_ps->performance_levels[0].memory_clock = mclk;
--
--	ellesmere_ps->performance_levels[1].engine_clock =
--		(ellesmere_ps->performance_levels[1].engine_clock >=
--				ellesmere_ps->performance_levels[0].engine_clock) ?
--						ellesmere_ps->performance_levels[1].engine_clock :
--						ellesmere_ps->performance_levels[0].engine_clock;
--
--	if (disable_mclk_switching) {
--		if (mclk < ellesmere_ps->performance_levels[1].memory_clock)
--			mclk = ellesmere_ps->performance_levels[1].memory_clock;
--
--		ellesmere_ps->performance_levels[0].memory_clock = mclk;
--		ellesmere_ps->performance_levels[1].memory_clock = mclk;
--	} else {
--		if (ellesmere_ps->performance_levels[1].memory_clock <
--				ellesmere_ps->performance_levels[0].memory_clock)
--			ellesmere_ps->performance_levels[1].memory_clock =
--					ellesmere_ps->performance_levels[0].memory_clock;
--	}
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_StablePState)) {
--		for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
--			ellesmere_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
--			ellesmere_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
--			ellesmere_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
--			ellesmere_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
--		}
--	}
--	return 0;
--}
--
--
--static int ellesmere_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
--{
--	struct pp_power_state  *ps;
--	struct ellesmere_power_state  *ellesmere_ps;
--
--	if (hwmgr == NULL)
--		return -EINVAL;
--
--	ps = hwmgr->request_ps;
--
--	if (ps == NULL)
--		return -EINVAL;
--
--	ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware);
--
--	if (low)
--		return ellesmere_ps->performance_levels[0].memory_clock;
--	else
--		return ellesmere_ps->performance_levels
--				[ellesmere_ps->performance_level_count-1].memory_clock;
--}
--
--static int ellesmere_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
--{
--	struct pp_power_state  *ps;
--	struct ellesmere_power_state  *ellesmere_ps;
--
--	if (hwmgr == NULL)
--		return -EINVAL;
--
--	ps = hwmgr->request_ps;
--
--	if (ps == NULL)
--		return -EINVAL;
--
--	ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware);
--
--	if (low)
--		return ellesmere_ps->performance_levels[0].engine_clock;
--	else
--		return ellesmere_ps->performance_levels
--				[ellesmere_ps->performance_level_count-1].engine_clock;
--}
--
--static int ellesmere_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
--					struct pp_hw_power_state *hw_ps)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_power_state *ps = (struct ellesmere_power_state *)hw_ps;
--	ATOM_FIRMWARE_INFO_V2_2 *fw_info;
--	uint16_t size;
--	uint8_t frev, crev;
--	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
--
--	/* First retrieve the Boot clocks and VDDC from the firmware info table.
--	 * We assume here that fw_info is unchanged if this call fails.
--	 */
--	fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
--			hwmgr->device, index,
--			&size, &frev, &crev);
--	if (!fw_info)
--		/* During a test, there is no firmware info table. */
--		return 0;
--
--	/* Patch the state. */
--	data->vbios_boot_state.sclk_bootup_value =
--			le32_to_cpu(fw_info->ulDefaultEngineClock);
--	data->vbios_boot_state.mclk_bootup_value =
--			le32_to_cpu(fw_info->ulDefaultMemoryClock);
--	data->vbios_boot_state.mvdd_bootup_value =
--			le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
--	data->vbios_boot_state.vddc_bootup_value =
--			le16_to_cpu(fw_info->usBootUpVDDCVoltage);
--	data->vbios_boot_state.vddci_bootup_value =
--			le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
--	data->vbios_boot_state.pcie_gen_bootup_value =
--			phm_get_current_pcie_speed(hwmgr);
--
--	data->vbios_boot_state.pcie_lane_bootup_value =
--			(uint16_t)phm_get_current_pcie_lane_number(hwmgr);
--
--	/* set boot power state */
--	ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
--	ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
--	ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
--	ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
--
--	return 0;
--}
--
--static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
--		void *state, struct pp_power_state *power_state,
--		void *pp_table, uint32_t classification_flag)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_power_state  *ellesmere_power_state =
--			(struct ellesmere_power_state *)(&(power_state->hardware));
--	struct ellesmere_performance_level *performance_level;
--	ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
--	ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
--			(ATOM_Tonga_POWERPLAYTABLE *)pp_table;
--	ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
--			(ATOM_Tonga_SCLK_Dependency_Table *)
--			(((unsigned long)powerplay_table) +
--				le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
--	ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
--			(ATOM_Tonga_MCLK_Dependency_Table *)
--			(((unsigned long)powerplay_table) +
--				le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
--
--	/* The following fields are not initialized here: id orderedList allStatesList */
--	power_state->classification.ui_label =
--			(le16_to_cpu(state_entry->usClassification) &
--			ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
--			ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
--	power_state->classification.flags = classification_flag;
--	/* NOTE: There is a classification2 flag in BIOS that is not being used right now */
--
--	power_state->classification.temporary_state = false;
--	power_state->classification.to_be_deleted = false;
--
--	power_state->validation.disallowOnDC =
--			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
--					ATOM_Tonga_DISALLOW_ON_DC));
--
--	power_state->pcie.lanes = 0;
--
--	power_state->display.disableFrameModulation = false;
--	power_state->display.limitRefreshrate = false;
--	power_state->display.enableVariBright =
--			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
--					ATOM_Tonga_ENABLE_VARIBRIGHT));
--
--	power_state->validation.supportedPowerLevels = 0;
--	power_state->uvd_clocks.VCLK = 0;
--	power_state->uvd_clocks.DCLK = 0;
--	power_state->temperatures.min = 0;
--	power_state->temperatures.max = 0;
--
--	performance_level = &(ellesmere_power_state->performance_levels
--			[ellesmere_power_state->performance_level_count++]);
--
--	PP_ASSERT_WITH_CODE(
--			(ellesmere_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
--			"Performance levels exceeds SMC limit!",
--			return -1);
--
--	PP_ASSERT_WITH_CODE(
--			(ellesmere_power_state->performance_level_count <=
--					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
--			"Performance levels exceeds Driver limit!",
--			return -1);
--
--	/* Performance levels are arranged from low to high. */
--	performance_level->memory_clock = mclk_dep_table->entries
--			[state_entry->ucMemoryClockIndexLow].ulMclk;
--	performance_level->engine_clock = sclk_dep_table->entries
--			[state_entry->ucEngineClockIndexLow].ulSclk;
--	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
--			state_entry->ucPCIEGenLow);
--	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
--			state_entry->ucPCIELaneHigh);
--
--	performance_level = &(ellesmere_power_state->performance_levels
--			[ellesmere_power_state->performance_level_count++]);
--	performance_level->memory_clock = mclk_dep_table->entries
--			[state_entry->ucMemoryClockIndexHigh].ulMclk;
--	performance_level->engine_clock = sclk_dep_table->entries
--			[state_entry->ucEngineClockIndexHigh].ulSclk;
--	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
--			state_entry->ucPCIEGenHigh);
--	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
--			state_entry->ucPCIELaneHigh);
--
--	return 0;
--}
--
--static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr,
--		unsigned long entry_index, struct pp_power_state *state)
--{
--	int result;
--	struct ellesmere_power_state *ps;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
--			table_info->vdd_dep_on_mclk;
--
--	state->hardware.magic = PHM_VIslands_Magic;
--
--	ps = (struct ellesmere_power_state *)(&state->hardware);
--
--	result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
--			ellesmere_get_pp_table_entry_callback_func);
--
--	/* This is the earliest time we have all the dependency table and the VBIOS boot state
--	 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
--	 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
--	 */
--	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
--		if (dep_mclk_table->entries[0].clk !=
--				data->vbios_boot_state.mclk_bootup_value)
--			printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
--					"does not match VBIOS boot MCLK level");
--		if (dep_mclk_table->entries[0].vddci !=
--				data->vbios_boot_state.vddci_bootup_value)
--			printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
--					"does not match VBIOS boot VDDCI level");
--	}
--
--	/* set DC compatible flag if this state supports DC */
--	if (!state->validation.disallowOnDC)
--		ps->dc_compatible = true;
--
--	if (state->classification.flags & PP_StateClassificationFlag_ACPI)
--		data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
--
--	ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
--	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
--
--	if (!result) {
--		uint32_t i;
--
--		switch (state->classification.ui_label) {
--		case PP_StateUILabel_Performance:
--			data->use_pcie_performance_levels = true;
--
--			for (i = 0; i < ps->performance_level_count; i++) {
--				if (data->pcie_gen_performance.max <
--						ps->performance_levels[i].pcie_gen)
--					data->pcie_gen_performance.max =
--							ps->performance_levels[i].pcie_gen;
--
--				if (data->pcie_gen_performance.min >
--						ps->performance_levels[i].pcie_gen)
--					data->pcie_gen_performance.min =
--							ps->performance_levels[i].pcie_gen;
--
--				if (data->pcie_lane_performance.max <
--						ps->performance_levels[i].pcie_lane)
--					data->pcie_lane_performance.max =
--							ps->performance_levels[i].pcie_lane;
--
--				if (data->pcie_lane_performance.min >
--						ps->performance_levels[i].pcie_lane)
--					data->pcie_lane_performance.min =
--							ps->performance_levels[i].pcie_lane;
--			}
--			break;
--		case PP_StateUILabel_Battery:
--			data->use_pcie_power_saving_levels = true;
--
--			for (i = 0; i < ps->performance_level_count; i++) {
--				if (data->pcie_gen_power_saving.max <
--						ps->performance_levels[i].pcie_gen)
--					data->pcie_gen_power_saving.max =
--							ps->performance_levels[i].pcie_gen;
--
--				if (data->pcie_gen_power_saving.min >
--						ps->performance_levels[i].pcie_gen)
--					data->pcie_gen_power_saving.min =
--							ps->performance_levels[i].pcie_gen;
--
--				if (data->pcie_lane_power_saving.max <
--						ps->performance_levels[i].pcie_lane)
--					data->pcie_lane_power_saving.max =
--							ps->performance_levels[i].pcie_lane;
--
--				if (data->pcie_lane_power_saving.min >
--						ps->performance_levels[i].pcie_lane)
--					data->pcie_lane_power_saving.min =
--							ps->performance_levels[i].pcie_lane;
--			}
--			break;
--		default:
--			break;
--		}
--	}
--	return 0;
--}
--
--static void
--ellesmere_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
--{
--	uint32_t sclk, mclk;
--
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
--
--	sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
--
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
--
--	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
--	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
--			mclk / 100, sclk / 100);
--}
--
--static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
--{
--	const struct phm_set_power_state_input *states =
--			(const struct phm_set_power_state_input *)input;
--	const struct ellesmere_power_state *ellesmere_ps =
--			cast_const_phw_ellesmere_power_state(states->pnew_state);
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
--	uint32_t sclk = ellesmere_ps->performance_levels
--			[ellesmere_ps->performance_level_count - 1].engine_clock;
--	struct ellesmere_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
--	uint32_t mclk = ellesmere_ps->performance_levels
--			[ellesmere_ps->performance_level_count - 1].memory_clock;
--	struct PP_Clocks min_clocks = {0};
--	uint32_t i;
--	struct cgs_display_info info = {0};
--
--	data->need_update_smu7_dpm_table = 0;
--
--	for (i = 0; i < sclk_table->count; i++) {
--		if (sclk == sclk_table->dpm_levels[i].value)
--			break;
--	}
--
--	if (i >= sclk_table->count)
--		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
--	else {
--	/* TODO: Check SCLK in DAL's minimum clocks
--	 * in case DeepSleep divider update is required.
--	 */
--		if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
--			data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
--	}
--
--	for (i = 0; i < mclk_table->count; i++) {
--		if (mclk == mclk_table->dpm_levels[i].value)
--			break;
--	}
--
--	if (i >= mclk_table->count)
--		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--
--	if (data->display_timing.num_existing_displays != info.display_count)
--		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
--
--	return 0;
--}
--
--static uint16_t ellesmere_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
--		const struct ellesmere_power_state *ellesmere_ps)
--{
--	uint32_t i;
--	uint32_t sclk, max_sclk = 0;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
--
--	for (i = 0; i < ellesmere_ps->performance_level_count; i++) {
--		sclk = ellesmere_ps->performance_levels[i].engine_clock;
--		if (max_sclk < sclk)
--			max_sclk = sclk;
--	}
--
--	for (i = 0; i < dpm_table->sclk_table.count; i++) {
--		if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
--			return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
--					dpm_table->pcie_speed_table.dpm_levels
--					[dpm_table->pcie_speed_table.count - 1].value :
--					dpm_table->pcie_speed_table.dpm_levels[i].value);
--	}
--
--	return 0;
--}
--
--static int ellesmere_request_link_speed_change_before_state_change(
--		struct pp_hwmgr *hwmgr, const void *input)
--{
--	const struct phm_set_power_state_input *states =
--			(const struct phm_set_power_state_input *)input;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	const struct ellesmere_power_state *ellesmere_nps =
--			cast_const_phw_ellesmere_power_state(states->pnew_state);
--	const struct ellesmere_power_state *ellesmere_cps =
--			cast_const_phw_ellesmere_power_state(states->pcurrent_state);
--
--	uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_nps);
--	uint16_t current_link_speed;
--
--	if (data->force_pcie_gen == PP_PCIEGenInvalid)
--		current_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_cps);
--	else
--		current_link_speed = data->force_pcie_gen;
--
--	data->force_pcie_gen = PP_PCIEGenInvalid;
--	data->pspp_notify_required = false;
--
--	if (target_link_speed > current_link_speed) {
--		switch (target_link_speed) {
--		case PP_PCIEGen3:
--			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
--				break;
--			data->force_pcie_gen = PP_PCIEGen2;
--			if (current_link_speed == PP_PCIEGen2)
--				break;
--		case PP_PCIEGen2:
--			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
--				break;
--		default:
--			data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
--			break;
--		}
--	} else {
--		if (target_link_speed < current_link_speed)
--			data->pspp_notify_required = true;
--	}
--
--	return 0;
--}
--
--static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (0 == data->need_update_smu7_dpm_table)
--		return 0;
--
--	if ((0 == data->sclk_dpm_key_disabled) &&
--		(data->need_update_smu7_dpm_table &
--			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
--		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
--				"Trying to freeze SCLK DPM when DPM is disabled",
--				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_SCLKDPM_FreezeLevel),
--				"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
--				return -1);
--	}
--
--	if ((0 == data->mclk_dpm_key_disabled) &&
--		(data->need_update_smu7_dpm_table &
--		 DPMTABLE_OD_UPDATE_MCLK)) {
--		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
--				"Trying to freeze MCLK DPM when DPM is disabled",
--				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_MCLKDPM_FreezeLevel),
--				"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
--				return -1);
--	}
--
--	return 0;
--}
--
--static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels(
--		struct pp_hwmgr *hwmgr, const void *input)
--{
--	int result = 0;
--	const struct phm_set_power_state_input *states =
--			(const struct phm_set_power_state_input *)input;
--	const struct ellesmere_power_state *ellesmere_ps =
--			cast_const_phw_ellesmere_power_state(states->pnew_state);
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t sclk = ellesmere_ps->performance_levels
--			[ellesmere_ps->performance_level_count - 1].engine_clock;
--	uint32_t mclk = ellesmere_ps->performance_levels
--			[ellesmere_ps->performance_level_count - 1].memory_clock;
--	struct ellesmere_dpm_table *dpm_table = &data->dpm_table;
--
--	struct ellesmere_dpm_table *golden_dpm_table = &data->golden_dpm_table;
--	uint32_t dpm_count, clock_percent;
--	uint32_t i;
--
--	if (0 == data->need_update_smu7_dpm_table)
--		return 0;
--
--	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
--		dpm_table->sclk_table.dpm_levels
--		[dpm_table->sclk_table.count - 1].value = sclk;
--
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
--		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
--		/* Need to do calculation based on the golden DPM table
--		 * as the Heatmap GPU Clock axis is also based on the default values
--		 */
--			PP_ASSERT_WITH_CODE(
--				(golden_dpm_table->sclk_table.dpm_levels
--						[golden_dpm_table->sclk_table.count - 1].value != 0),
--				"Divide by 0!",
--				return -1);
--			dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
--
--			for (i = dpm_count; i > 1; i--) {
--				if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
--					clock_percent =
--					      ((sclk
--						- golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
--						) * 100)
--						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
--
--					dpm_table->sclk_table.dpm_levels[i].value =
--							golden_dpm_table->sclk_table.dpm_levels[i].value +
--							(golden_dpm_table->sclk_table.dpm_levels[i].value *
--								clock_percent)/100;
--
--				} else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
--					clock_percent =
--						((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
--						- sclk) * 100)
--						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
--
--					dpm_table->sclk_table.dpm_levels[i].value =
--							golden_dpm_table->sclk_table.dpm_levels[i].value -
--							(golden_dpm_table->sclk_table.dpm_levels[i].value *
--									clock_percent) / 100;
--				} else
--					dpm_table->sclk_table.dpm_levels[i].value =
--							golden_dpm_table->sclk_table.dpm_levels[i].value;
--			}
--		}
--	}
--
--	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
--		dpm_table->mclk_table.dpm_levels
--			[dpm_table->mclk_table.count - 1].value = mclk;
--
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
--		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
--
--			PP_ASSERT_WITH_CODE(
--					(golden_dpm_table->mclk_table.dpm_levels
--						[golden_dpm_table->mclk_table.count-1].value != 0),
--					"Divide by 0!",
--					return -1);
--			dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
--			for (i = dpm_count; i > 1; i--) {
--				if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
--					clock_percent = ((mclk -
--					golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
--					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
--
--					dpm_table->mclk_table.dpm_levels[i].value =
--							golden_dpm_table->mclk_table.dpm_levels[i].value +
--							(golden_dpm_table->mclk_table.dpm_levels[i].value *
--							clock_percent) / 100;
--
--				} else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
--					clock_percent = (
--					 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
--					* 100)
--					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
--
--					dpm_table->mclk_table.dpm_levels[i].value =
--							golden_dpm_table->mclk_table.dpm_levels[i].value -
--							(golden_dpm_table->mclk_table.dpm_levels[i].value *
--									clock_percent) / 100;
--				} else
--					dpm_table->mclk_table.dpm_levels[i].value =
--							golden_dpm_table->mclk_table.dpm_levels[i].value;
--			}
--		}
--	}
--
--	if (data->need_update_smu7_dpm_table &
--			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
--		result = ellesmere_populate_all_graphic_levels(hwmgr);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
--				return result);
--	}
--
--	if (data->need_update_smu7_dpm_table &
--			(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
--		/*populate MCLK dpm table to SMU7 */
--		result = ellesmere_populate_all_memory_levels(hwmgr);
--		PP_ASSERT_WITH_CODE((0 == result),
--				"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
--				return result);
--	}
--
--	return result;
--}
--
--static int ellesmere_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
--			  struct ellesmere_single_dpm_table *dpm_table,
--			uint32_t low_limit, uint32_t high_limit)
--{
--	uint32_t i;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	for (i = 0; i < dpm_table->count; i++) {
--		if ((dpm_table->dpm_levels[i].value < low_limit)
--		|| (dpm_table->dpm_levels[i].value > high_limit))
--			dpm_table->dpm_levels[i].enabled = false;
--		else if (((1 << i) & data->disable_dpm_mask) == 0)
--			dpm_table->dpm_levels[i].enabled = false;
--		else
--			dpm_table->dpm_levels[i].enabled = true;
--	}
--
--	return 0;
--}
--
--static int ellesmere_trim_dpm_states(struct pp_hwmgr *hwmgr,
--		const struct ellesmere_power_state *ellesmere_ps)
--{
--	int result = 0;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t high_limit_count;
--
--	PP_ASSERT_WITH_CODE((ellesmere_ps->performance_level_count >= 1),
--			"power state did not have any performance level",
--			return -1);
--
--	high_limit_count = (1 == ellesmere_ps->performance_level_count) ? 0 : 1;
--
--	ellesmere_trim_single_dpm_states(hwmgr,
--			&(data->dpm_table.sclk_table),
--			ellesmere_ps->performance_levels[0].engine_clock,
--			ellesmere_ps->performance_levels[high_limit_count].engine_clock);
--
--	ellesmere_trim_single_dpm_states(hwmgr,
--			&(data->dpm_table.mclk_table),
--			ellesmere_ps->performance_levels[0].memory_clock,
--			ellesmere_ps->performance_levels[high_limit_count].memory_clock);
--
--	return result;
--}
--
--static int ellesmere_generate_dpm_level_enable_mask(
--		struct pp_hwmgr *hwmgr, const void *input)
--{
--	int result;
--	const struct phm_set_power_state_input *states =
--			(const struct phm_set_power_state_input *)input;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	const struct ellesmere_power_state *ellesmere_ps =
--			cast_const_phw_ellesmere_power_state(states->pnew_state);
--
--	result = ellesmere_trim_dpm_states(hwmgr, ellesmere_ps);
--	if (result)
--		return result;
--
--	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
--			phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
--	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
--			phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
--	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
--			phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
--
--	return 0;
--}
--
--int ellesmere_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
--{
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
--			PPSMC_MSG_UVDDPM_Enable :
--			PPSMC_MSG_UVDDPM_Disable);
--}
--
--int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
--{
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
--			PPSMC_MSG_VCEDPM_Enable :
--			PPSMC_MSG_VCEDPM_Disable);
--}
--
--int ellesmere_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
--{
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
--			PPSMC_MSG_SAMUDPM_Enable :
--			PPSMC_MSG_SAMUDPM_Disable);
--}
--
--int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t mm_boot_level_offset, mm_boot_level_value;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	if (!bgate) {
--		data->smc_state_table.UvdBootLevel = 0;
--		if (table_info->mm_dep_table->count > 0)
--			data->smc_state_table.UvdBootLevel =
--					(uint8_t) (table_info->mm_dep_table->count - 1);
--		mm_boot_level_offset = data->dpm_table_start +
--				offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
--		mm_boot_level_offset /= 4;
--		mm_boot_level_offset *= 4;
--		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
--				CGS_IND_REG__SMC, mm_boot_level_offset);
--		mm_boot_level_value &= 0x00FFFFFF;
--		mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
--		cgs_write_ind_register(hwmgr->device,
--				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
--
--		if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_UVDDPM) ||
--			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_StablePState))
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_UVDDPM_SetEnabledMask,
--					(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
--	}
--
--	return ellesmere_enable_disable_uvd_dpm(hwmgr, !bgate);
--}
--
--static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
--{
--	const struct phm_set_power_state_input *states =
--			(const struct phm_set_power_state_input *)input;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	const struct ellesmere_power_state *ellesmere_nps =
--			cast_const_phw_ellesmere_power_state(states->pnew_state);
--	const struct ellesmere_power_state *ellesmere_cps =
--			cast_const_phw_ellesmere_power_state(states->pcurrent_state);
--
--	uint32_t mm_boot_level_offset, mm_boot_level_value;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	if (ellesmere_nps->vce_clks.evclk > 0 &&
--	(ellesmere_cps == NULL || ellesmere_cps->vce_clks.evclk == 0)) {
--
--		data->smc_state_table.VceBootLevel =
--				(uint8_t) (table_info->mm_dep_table->count - 1);
--
--		mm_boot_level_offset = data->dpm_table_start +
--				offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
--		mm_boot_level_offset /= 4;
--		mm_boot_level_offset *= 4;
--		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
--				CGS_IND_REG__SMC, mm_boot_level_offset);
--		mm_boot_level_value &= 0xFF00FFFF;
--		mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
--		cgs_write_ind_register(hwmgr->device,
--				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
--
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_VCEDPM_SetEnabledMask,
--					(uint32_t)1 << data->smc_state_table.VceBootLevel);
--
--			ellesmere_enable_disable_vce_dpm(hwmgr, true);
--		} else if (ellesmere_nps->vce_clks.evclk == 0 &&
--				ellesmere_cps != NULL &&
--				ellesmere_cps->vce_clks.evclk > 0)
--			ellesmere_enable_disable_vce_dpm(hwmgr, false);
--	}
--
--	return 0;
--}
--
--int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t mm_boot_level_offset, mm_boot_level_value;
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--
--	if (!bgate) {
--		data->smc_state_table.SamuBootLevel =
--				(uint8_t) (table_info->mm_dep_table->count - 1);
--		mm_boot_level_offset = data->dpm_table_start +
--				offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
--		mm_boot_level_offset /= 4;
--		mm_boot_level_offset *= 4;
--		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
--				CGS_IND_REG__SMC, mm_boot_level_offset);
--		mm_boot_level_value &= 0xFFFFFF00;
--		mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
--		cgs_write_ind_register(hwmgr->device,
--				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
--
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_StablePState))
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_SAMUDPM_SetEnabledMask,
--					(uint32_t)(1 << data->smc_state_table.SamuBootLevel));
--	}
--
--	return ellesmere_enable_disable_samu_dpm(hwmgr, !bgate);
--}
--
--static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	int result = 0;
--	uint32_t low_sclk_interrupt_threshold = 0;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SclkThrottleLowNotification)
--		&& (hwmgr->gfx_arbiter.sclk_threshold !=
--				data->low_sclk_interrupt_threshold)) {
--		data->low_sclk_interrupt_threshold =
--				hwmgr->gfx_arbiter.sclk_threshold;
--		low_sclk_interrupt_threshold =
--				data->low_sclk_interrupt_threshold;
--
--		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
--
--		result = ellesmere_copy_bytes_to_smc(
--				hwmgr->smumgr,
--				data->dpm_table_start +
--				offsetof(SMU74_Discrete_DpmTable,
--					LowSclkInterruptThreshold),
--				(uint8_t *)&low_sclk_interrupt_threshold,
--				sizeof(uint32_t),
--				data->sram_end);
--	}
--
--	return result;
--}
--
--static int ellesmere_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (data->need_update_smu7_dpm_table &
--		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
--		return ellesmere_program_memory_timing_parameters(hwmgr);
--
--	return 0;
--}
--
--static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (0 == data->need_update_smu7_dpm_table)
--		return 0;
--
--	if ((0 == data->sclk_dpm_key_disabled) &&
--		(data->need_update_smu7_dpm_table &
--		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
--
--		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
--				"Trying to Unfreeze SCLK DPM when DPM is disabled",
--				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
--			"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
--			return -1);
--	}
--
--	if ((0 == data->mclk_dpm_key_disabled) &&
--		(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
--
--		PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr),
--				"Trying to Unfreeze MCLK DPM when DPM is disabled",
--				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
--		    "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
--		    return -1);
--	}
--
--	data->need_update_smu7_dpm_table = 0;
--
--	return 0;
--}
--
--static int ellesmere_notify_link_speed_change_after_state_change(
--		struct pp_hwmgr *hwmgr, const void *input)
--{
--	const struct phm_set_power_state_input *states =
--			(const struct phm_set_power_state_input *)input;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	const struct ellesmere_power_state *ellesmere_ps =
--			cast_const_phw_ellesmere_power_state(states->pnew_state);
--	uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_ps);
--	uint8_t  request;
--
--	if (data->pspp_notify_required) {
--		if (target_link_speed == PP_PCIEGen3)
--			request = PCIE_PERF_REQ_GEN3;
--		else if (target_link_speed == PP_PCIEGen2)
--			request = PCIE_PERF_REQ_GEN2;
--		else
--			request = PCIE_PERF_REQ_GEN1;
--
--		if (request == PCIE_PERF_REQ_GEN1 &&
--				phm_get_current_pcie_speed(hwmgr) > 0)
--			return 0;
--
--		if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
--			if (PP_PCIEGen2 == target_link_speed)
--				printk("PSPP request to switch to Gen2 from Gen3 Failed!");
--			else
--				printk("PSPP request to switch to Gen1 from Gen2 Failed!");
--		}
--	}
--
--	return 0;
--}
--
--static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
--{
--	int tmp_result, result = 0;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	tmp_result = ellesmere_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to find DPM states clocks in DPM table!",
--			result = tmp_result);
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PCIEPerformanceRequest)) {
--		tmp_result =
--			ellesmere_request_link_speed_change_before_state_change(hwmgr, input);
--		PP_ASSERT_WITH_CODE((0 == tmp_result),
--				"Failed to request link speed change before state change!",
--				result = tmp_result);
--	}
--
--	tmp_result = ellesmere_freeze_sclk_mclk_dpm(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to freeze SCLK MCLK DPM!", result = tmp_result);
--
--	tmp_result = ellesmere_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to populate and upload SCLK MCLK DPM levels!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_generate_dpm_level_enable_mask(hwmgr, input);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to generate DPM level enabled mask!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_update_vce_dpm(hwmgr, input);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to update VCE DPM!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_update_sclk_threshold(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to update SCLK threshold!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_program_mem_timing_parameters(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to program memory timing parameters!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_unfreeze_sclk_mclk_dpm(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to unfreeze SCLK MCLK DPM!",
--			result = tmp_result);
--
--	tmp_result = ellesmere_upload_dpm_level_enable_mask(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to upload DPM level enabled mask!",
--			result = tmp_result);
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PCIEPerformanceRequest)) {
--		tmp_result =
--			ellesmere_notify_link_speed_change_after_state_change(hwmgr, input);
--		PP_ASSERT_WITH_CODE((0 == tmp_result),
--				"Failed to notify link speed change after state change!",
--				result = tmp_result);
--	}
--	data->apply_optimized_settings = false;
--	return result;
--}
--
--static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
--{
--	hwmgr->thermal_controller.
--	advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
--
--	if (phm_is_hw_access_blocked(hwmgr))
--		return 0;
--
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
--}
--
--int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
--{
--	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
--
--	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
--}
--
--int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
--{
--	uint32_t num_active_displays = 0;
--	struct cgs_display_info info = {0};
--	info.mode_info = NULL;
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--
--	num_active_displays = info.display_count;
--
--	if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
--		ellesmere_notify_smc_display_change(hwmgr, false);
--	else
--		ellesmere_notify_smc_display_change(hwmgr, true);
--
--	return 0;
--}
--
--/**
--* Programs the display gap
--*
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @return   always OK
--*/
--int ellesmere_program_display_gap(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t num_active_displays = 0;
--	uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
--	uint32_t display_gap2;
--	uint32_t pre_vbi_time_in_us;
--	uint32_t frame_time_in_us;
--	uint32_t ref_clock;
--	uint32_t refresh_rate = 0;
--	struct cgs_display_info info = {0};
--	struct cgs_mode_info mode_info;
--
--	info.mode_info = &mode_info;
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--	num_active_displays = info.display_count;
--
--	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
--
--	ref_clock = mode_info.ref_clock;
--	refresh_rate = mode_info.refresh_rate;
--
--	if (0 == refresh_rate)
--		refresh_rate = 60;
--
--	frame_time_in_us = 1000000 / refresh_rate;
--
--	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
--	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
--
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
--
--	if (num_active_displays == 1)
--		ellesmere_notify_smc_display_change(hwmgr, true);
--
--	return 0;
--}
--
--
--int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
--{
--	return ellesmere_program_display_gap(hwmgr);
--}
--
--/**
--*  Set maximum target operating fan output RPM
--*
--* @param    hwmgr:  the address of the powerplay hardware manager.
--* @param    usMaxFanRpm:  max operating fan RPM value.
--* @return   The response that came from the SMC.
--*/
--static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
--{
--	hwmgr->thermal_controller.
--	advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
--
--	if (phm_is_hw_access_blocked(hwmgr))
--		return 0;
--
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
--}
--
--int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
--					const void *thermal_interrupt_info)
--{
--	return 0;
--}
--
--bool ellesmere_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	bool is_update_required = false;
--	struct cgs_display_info info = {0, 0, NULL};
--
--	cgs_get_active_displays_info(hwmgr->device, &info);
--
--	if (data->display_timing.num_existing_displays != info.display_count)
--		is_update_required = true;
--/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
--	if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
--		cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
--		if (min_clocks.engineClockInSR != data->display_timing.minClockInSR)
--			is_update_required = true;
--*/
--	return is_update_required;
--}
--
--static inline bool ellesmere_are_power_levels_equal(const struct ellesmere_performance_level *pl1,
--							   const struct ellesmere_performance_level *pl2)
--{
--	return ((pl1->memory_clock == pl2->memory_clock) &&
--		  (pl1->engine_clock == pl2->engine_clock) &&
--		  (pl1->pcie_gen == pl2->pcie_gen) &&
--		  (pl1->pcie_lane == pl2->pcie_lane));
--}
--
--int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
--{
--	const struct ellesmere_power_state *psa = cast_const_phw_ellesmere_power_state(pstate1);
--	const struct ellesmere_power_state *psb = cast_const_phw_ellesmere_power_state(pstate2);
--	int i;
--
--	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
--		return -EINVAL;
--
--	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
--	if (psa->performance_level_count != psb->performance_level_count) {
--		*equal = false;
--		return 0;
--	}
--
--	for (i = 0; i < psa->performance_level_count; i++) {
--		if (!ellesmere_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
--			/* If we have found even one performance level pair that is different the states are different. */
--			*equal = false;
--			return 0;
--		}
--	}
--
--	/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
--	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
--	*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
--	*equal &= (psa->sclk_threshold == psb->sclk_threshold);
--
--	return 0;
--}
--
--int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	uint32_t vbios_version;
--
--	/*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
--
--	phm_get_mc_microcode_version(hwmgr);
--	vbios_version = hwmgr->microcode_version_info.MC & 0xf;
--	/*  Full version of MC ucode has already been loaded. */
--	if (vbios_version == 0) {
--		data->need_long_memory_training = false;
--		return 0;
--	}
--
--	data->need_long_memory_training = true;
--
--/*
-- * 	PPMCME_FirmwareDescriptorEntry *pfd = NULL;
--	pfd = &tonga_mcmeFirmware;
--	if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
--		ellesmere_load_mc_microcode(hwmgr, pfd->dpmThreshold,
--					pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
--					pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
--*/
--	return 0;
--}
--
--/**
-- * Read clock related registers.
-- *
-- * @param    hwmgr  the address of the powerplay hardware manager.
-- * @return   always 0
-- */
--static int ellesmere_read_clock_registers(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
--						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
--						& CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
--
--	data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
--						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
--						& CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
--
--	data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
--						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
--						& CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
--
--	return 0;
--}
--
--/**
-- * Find out if memory is GDDR5.
-- *
-- * @param    hwmgr  the address of the powerplay hardware manager.
-- * @return   always 0
-- */
--static int ellesmere_get_memory_type(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t temp;
--
--	temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
--
--	data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
--			((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
--			 MC_SEQ_MISC0_GDDR5_SHIFT));
--
--	return 0;
--}
--
--/**
-- * Enables Dynamic Power Management by SMC
-- *
-- * @param    hwmgr  the address of the powerplay hardware manager.
-- * @return   always 0
-- */
--static int ellesmere_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
--{
--	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			GENERAL_PWRMGT, STATIC_PM_EN, 1);
--
--	return 0;
--}
--
--/**
-- * Initialize PowerGating States for different engines
-- *
-- * @param    hwmgr  the address of the powerplay hardware manager.
-- * @return   always 0
-- */
--static int ellesmere_init_power_gate_state(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	data->uvd_power_gated = false;
--	data->vce_power_gated = false;
--	data->samu_power_gated = false;
--
--	return 0;
--}
--
--static int ellesmere_init_sclk_threshold(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	data->low_sclk_interrupt_threshold = 0;
--
--	return 0;
--}
--
--int ellesmere_setup_asic_task(struct pp_hwmgr *hwmgr)
--{
--	int tmp_result, result = 0;
--
--	ellesmere_upload_mc_firmware(hwmgr);
--
--	tmp_result = ellesmere_read_clock_registers(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to read clock registers!", result = tmp_result);
--
--	tmp_result = ellesmere_get_memory_type(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to get memory type!", result = tmp_result);
--
--	tmp_result = ellesmere_enable_acpi_power_management(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable ACPI power management!", result = tmp_result);
--
--	tmp_result = ellesmere_init_power_gate_state(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to init power gate state!", result = tmp_result);
--
--	tmp_result = phm_get_mc_microcode_version(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to get MC microcode version!", result = tmp_result);
--
--	tmp_result = ellesmere_init_sclk_threshold(hwmgr);
--	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to init sclk threshold!", result = tmp_result);
--
--	return result;
--}
--
--static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = {
--	.backend_init = &ellesmere_hwmgr_backend_init,
--	.backend_fini = &ellesmere_hwmgr_backend_fini,
--	.asic_setup = &ellesmere_setup_asic_task,
--	.dynamic_state_management_enable = &ellesmere_enable_dpm_tasks,
--	.apply_state_adjust_rules = ellesmere_apply_state_adjust_rules,
--	.force_dpm_level = &ellesmere_force_dpm_level,
--	.power_state_set = ellesmere_set_power_state_tasks,
--	.get_power_state_size = ellesmere_get_power_state_size,
--	.get_mclk = ellesmere_dpm_get_mclk,
--	.get_sclk = ellesmere_dpm_get_sclk,
--	.patch_boot_state = ellesmere_dpm_patch_boot_state,
--	.get_pp_table_entry = ellesmere_get_pp_table_entry,
--	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
--	.print_current_perforce_level = ellesmere_print_current_perforce_level,
--	.powerdown_uvd = ellesmere_phm_powerdown_uvd,
--	.powergate_uvd = ellesmere_phm_powergate_uvd,
--	.powergate_vce = ellesmere_phm_powergate_vce,
--	.disable_clock_power_gating = ellesmere_phm_disable_clock_power_gating,
--	.update_clock_gatings = ellesmere_phm_update_clock_gatings,
--	.notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment,
--	.display_config_changed = ellesmere_display_configuration_changed_task,
--	.set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output,
--	.set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output,
--	.get_temperature = ellesmere_thermal_get_temperature,
--	.stop_thermal_controller = ellesmere_thermal_stop_thermal_controller,
--	.get_fan_speed_info = ellesmere_fan_ctrl_get_fan_speed_info,
--	.get_fan_speed_percent = ellesmere_fan_ctrl_get_fan_speed_percent,
--	.set_fan_speed_percent = ellesmere_fan_ctrl_set_fan_speed_percent,
--	.reset_fan_speed_to_default = ellesmere_fan_ctrl_reset_fan_speed_to_default,
--	.get_fan_speed_rpm = ellesmere_fan_ctrl_get_fan_speed_rpm,
--	.set_fan_speed_rpm = ellesmere_fan_ctrl_set_fan_speed_rpm,
--	.uninitialize_thermal_controller = ellesmere_thermal_ctrl_uninitialize_thermal_controller,
--	.register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt,
--	.check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration,
--	.check_states_equal = ellesmere_check_states_equal,
--	.get_pp_table = ellesmere_get_pp_table,
--	.set_pp_table = ellesmere_set_pp_table,
--	.force_clock_level = ellesmere_force_clock_level,
--	.print_clock_levels = ellesmere_print_clock_levels,
--	.enable_per_cu_power_gating = ellesmere_phm_enable_per_cu_power_gating,
--};
--
--int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr  *data;
--
--	data = kzalloc (sizeof(struct ellesmere_hwmgr), GFP_KERNEL);
--	if (data == NULL)
--		return -ENOMEM;
--
--	hwmgr->backend = data;
--	hwmgr->hwmgr_func = &ellesmere_hwmgr_funcs;
--	hwmgr->pptable_func = &tonga_pptable_funcs;
--	pp_ellesmere_thermal_initialize(hwmgr);
--
--	return 0;
--}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-deleted file mode 100644
-index dd6c60b..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h
-+++ /dev/null
-@@ -1,354 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef ELLESMERE_HWMGR_H
--#define ELLESMERE_HWMGR_H
--
--#include "hwmgr.h"
--#include "smu74.h"
--#include "smu74_discrete.h"
--#include "ppatomctrl.h"
--#include "ellesmere_ppsmc.h"
--#include "ellesmere_powertune.h"
--
--#define ELLESMERE_MAX_HARDWARE_POWERLEVELS	2
--
--#define ELLESMERE_VOLTAGE_CONTROL_NONE                   0x0
--#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO                0x1
--#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2               0x2
--#define ELLESMERE_VOLTAGE_CONTROL_MERGED                 0x3
--
--#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
--#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
--#define DPMTABLE_UPDATE_SCLK        0x00000004
--#define DPMTABLE_UPDATE_MCLK        0x00000008
--
--struct ellesmere_performance_level {
--	uint32_t  memory_clock;
--	uint32_t  engine_clock;
--	uint16_t  pcie_gen;
--	uint16_t  pcie_lane;
--};
--
--struct ellesmere_uvd_clocks {
--	uint32_t  vclk;
--	uint32_t  dclk;
--};
--
--struct ellesmere_vce_clocks {
--	uint32_t  evclk;
--	uint32_t  ecclk;
--};
--
--struct ellesmere_power_state {
--	uint32_t                  magic;
--	struct ellesmere_uvd_clocks    uvd_clks;
--	struct ellesmere_vce_clocks    vce_clks;
--	uint32_t                  sam_clk;
--	uint16_t                  performance_level_count;
--	bool                      dc_compatible;
--	uint32_t                  sclk_threshold;
--	struct ellesmere_performance_level  performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS];
--};
--
--struct ellesmere_dpm_level {
--	bool	enabled;
--	uint32_t	value;
--	uint32_t	param1;
--};
--
--#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5
--#define MAX_REGULAR_DPM_NUMBER 8
--#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500
--
--struct ellesmere_single_dpm_table {
--	uint32_t		count;
--	struct ellesmere_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
--};
--
--struct ellesmere_dpm_table {
--	struct ellesmere_single_dpm_table  sclk_table;
--	struct ellesmere_single_dpm_table  mclk_table;
--	struct ellesmere_single_dpm_table  pcie_speed_table;
--	struct ellesmere_single_dpm_table  vddc_table;
--	struct ellesmere_single_dpm_table  vddci_table;
--	struct ellesmere_single_dpm_table  mvdd_table;
--};
--
--struct ellesmere_clock_registers {
--	uint32_t  vCG_SPLL_FUNC_CNTL;
--	uint32_t  vCG_SPLL_FUNC_CNTL_2;
--	uint32_t  vCG_SPLL_FUNC_CNTL_3;
--	uint32_t  vCG_SPLL_FUNC_CNTL_4;
--	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
--	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
--	uint32_t  vDLL_CNTL;
--	uint32_t  vMCLK_PWRMGT_CNTL;
--	uint32_t  vMPLL_AD_FUNC_CNTL;
--	uint32_t  vMPLL_DQ_FUNC_CNTL;
--	uint32_t  vMPLL_FUNC_CNTL;
--	uint32_t  vMPLL_FUNC_CNTL_1;
--	uint32_t  vMPLL_FUNC_CNTL_2;
--	uint32_t  vMPLL_SS1;
--	uint32_t  vMPLL_SS2;
--};
--
--#define DISABLE_MC_LOADMICROCODE   1
--#define DISABLE_MC_CFGPROGRAMMING  2
--
--struct ellesmere_voltage_smio_registers {
--	uint32_t vS0_VID_LOWER_SMIO_CNTL;
--};
--
--#define ELLESMERE_MAX_LEAKAGE_COUNT  8
--
--struct ellesmere_leakage_voltage {
--	uint16_t  count;
--	uint16_t  leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT];
--	uint16_t  actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT];
--};
--
--struct ellesmere_vbios_boot_state {
--	uint16_t    mvdd_bootup_value;
--	uint16_t    vddc_bootup_value;
--	uint16_t    vddci_bootup_value;
--	uint32_t    sclk_bootup_value;
--	uint32_t    mclk_bootup_value;
--	uint16_t    pcie_gen_bootup_value;
--	uint16_t    pcie_lane_bootup_value;
--};
--
--/* Ultra Low Voltage parameter structure */
--struct ellesmere_ulv_parm {
--	bool                           ulv_supported;
--	uint32_t                       cg_ulv_parameter;
--	uint32_t                       ulv_volt_change_delay;
--	struct ellesmere_performance_level  ulv_power_level;
--};
--
--struct ellesmere_display_timing {
--	uint32_t  min_clock_in_sr;
--	uint32_t  num_existing_displays;
--};
--
--struct ellesmere_dpmlevel_enable_mask {
--	uint32_t  uvd_dpm_enable_mask;
--	uint32_t  vce_dpm_enable_mask;
--	uint32_t  acp_dpm_enable_mask;
--	uint32_t  samu_dpm_enable_mask;
--	uint32_t  sclk_dpm_enable_mask;
--	uint32_t  mclk_dpm_enable_mask;
--	uint32_t  pcie_dpm_enable_mask;
--};
--
--struct ellesmere_pcie_perf_range {
--	uint16_t  max;
--	uint16_t  min;
--};
--struct ellesmere_range_table {
--	uint32_t trans_lower_frequency; /* in 10khz */
--	uint32_t trans_upper_frequency;
--};
--
--struct ellesmere_hwmgr {
--	struct ellesmere_dpm_table			dpm_table;
--	struct ellesmere_dpm_table			golden_dpm_table;
--	SMU74_Discrete_DpmTable				smc_state_table;
--	struct SMU74_Discrete_Ulv            ulv_setting;
--
--	struct ellesmere_range_table                range_table[NUM_SCLK_RANGE];
--	uint32_t						voting_rights_clients0;
--	uint32_t						voting_rights_clients1;
--	uint32_t						voting_rights_clients2;
--	uint32_t						voting_rights_clients3;
--	uint32_t						voting_rights_clients4;
--	uint32_t						voting_rights_clients5;
--	uint32_t						voting_rights_clients6;
--	uint32_t						voting_rights_clients7;
--	uint32_t						static_screen_threshold_unit;
--	uint32_t						static_screen_threshold;
--	uint32_t						voltage_control;
--	uint32_t						vddc_vddci_delta;
--
--	uint32_t						active_auto_throttle_sources;
--
--	struct ellesmere_clock_registers            clock_registers;
--	struct ellesmere_voltage_smio_registers      voltage_smio_registers;
--
--	bool                           is_memory_gddr5;
--	uint16_t                       acpi_vddc;
--	bool                           pspp_notify_required;
--	uint16_t                       force_pcie_gen;
--	uint16_t                       acpi_pcie_gen;
--	uint32_t                       pcie_gen_cap;
--	uint32_t                       pcie_lane_cap;
--	uint32_t                       pcie_spc_cap;
--	struct ellesmere_leakage_voltage          vddc_leakage;
--	struct ellesmere_leakage_voltage          Vddci_leakage;
--
--	uint32_t                             mvdd_control;
--	uint32_t                             vddc_mask_low;
--	uint32_t                             mvdd_mask_low;
--	uint16_t                            max_vddc_in_pptable;
--	uint16_t                            min_vddc_in_pptable;
--	uint16_t                            max_vddci_in_pptable;
--	uint16_t                            min_vddci_in_pptable;
--	uint32_t                             mclk_strobe_mode_threshold;
--	uint32_t                             mclk_stutter_mode_threshold;
--	uint32_t                             mclk_edc_enable_threshold;
--	uint32_t                             mclk_edcwr_enable_threshold;
--	bool                                is_uvd_enabled;
--	struct ellesmere_vbios_boot_state        vbios_boot_state;
--
--	bool                           pcie_performance_request;
--	bool                           battery_state;
--	bool                           is_tlu_enabled;
--
--	/* ---- SMC SRAM Address of firmware header tables ---- */
--	uint32_t                             sram_end;
--	uint32_t                             dpm_table_start;
--	uint32_t                             soft_regs_start;
--	uint32_t                             mc_reg_table_start;
--	uint32_t                             fan_table_start;
--	uint32_t                             arb_table_start;
--
--	/* ---- Stuff originally coming from Evergreen ---- */
--	uint32_t                             vddci_control;
--	struct pp_atomctrl_voltage_table     vddc_voltage_table;
--	struct pp_atomctrl_voltage_table     vddci_voltage_table;
--	struct pp_atomctrl_voltage_table     mvdd_voltage_table;
--
--	uint32_t                             mgcg_cgtt_local2;
--	uint32_t                             mgcg_cgtt_local3;
--	uint32_t                             gpio_debug;
--	uint32_t                             mc_micro_code_feature;
--	uint32_t                             highest_mclk;
--	uint16_t                             acpi_vddci;
--	uint8_t                              mvdd_high_index;
--	uint8_t                              mvdd_low_index;
--	bool                                 dll_default_on;
--	bool                                 performance_request_registered;
--
--	/* ---- Low Power Features ---- */
--	struct ellesmere_ulv_parm                 ulv;
--
--	/* ---- CAC Stuff ---- */
--	uint32_t                       cac_table_start;
--	bool                           cac_configuration_required;
--	bool                           driver_calculate_cac_leakage;
--	bool                           cac_enabled;
--
--	/* ---- DPM2 Parameters ---- */
--	uint32_t                       power_containment_features;
--	bool                           enable_dte_feature;
--	bool                           enable_tdc_limit_feature;
--	bool                           enable_pkg_pwr_tracking_feature;
--	bool                           disable_uvd_power_tune_feature;
--	struct ellesmere_pt_defaults       *power_tune_defaults;
--	struct SMU74_Discrete_PmFuses  power_tune_table;
--	uint32_t                       dte_tj_offset;
--	uint32_t                       fast_watermark_threshold;
--
--	/* ---- Phase Shedding ---- */
--	bool                           vddc_phase_shed_control;
--
--	/* ---- DI/DT ---- */
--	struct ellesmere_display_timing        display_timing;
--	uint32_t                      bif_sclk_table[SMU74_MAX_LEVELS_LINK];
--
--	/* ---- Thermal Temperature Setting ---- */
--	struct ellesmere_dpmlevel_enable_mask     dpm_level_enable_mask;
--	uint32_t                                  need_update_smu7_dpm_table;
--	uint32_t                                  sclk_dpm_key_disabled;
--	uint32_t                                  mclk_dpm_key_disabled;
--	uint32_t                                  pcie_dpm_key_disabled;
--	uint32_t                                  min_engine_clocks;
--	struct ellesmere_pcie_perf_range          pcie_gen_performance;
--	struct ellesmere_pcie_perf_range          pcie_lane_performance;
--	struct ellesmere_pcie_perf_range          pcie_gen_power_saving;
--	struct ellesmere_pcie_perf_range          pcie_lane_power_saving;
--	bool                                      use_pcie_performance_levels;
--	bool                                      use_pcie_power_saving_levels;
--	uint32_t                                  activity_target[SMU74_MAX_LEVELS_GRAPHICS];
--	uint32_t                                  mclk_activity_target;
--	uint32_t                                  mclk_dpm0_activity_target;
--	uint32_t                                  low_sclk_interrupt_threshold;
--	uint32_t                                  last_mclk_dpm_enable_mask;
--	bool                                      uvd_enabled;
--
--	/* ---- Power Gating States ---- */
--	bool                           uvd_power_gated;
--	bool                           vce_power_gated;
--	bool                           samu_power_gated;
--	bool                           need_long_memory_training;
--
--	/* Application power optimization parameters */
--	bool                               update_up_hyst;
--	bool                               update_down_hyst;
--	uint32_t                           down_hyst;
--	uint32_t                           up_hyst;
--	uint32_t disable_dpm_mask;
--	bool apply_optimized_settings;
--};
--
--/* To convert to Q8.8 format for firmware */
--#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT             256
--
--enum Ellesmere_I2CLineID {
--	Ellesmere_I2CLineID_DDC1 = 0x90,
--	Ellesmere_I2CLineID_DDC2 = 0x91,
--	Ellesmere_I2CLineID_DDC3 = 0x92,
--	Ellesmere_I2CLineID_DDC4 = 0x93,
--	Ellesmere_I2CLineID_DDC5 = 0x94,
--	Ellesmere_I2CLineID_DDC6 = 0x95,
--	Ellesmere_I2CLineID_SCLSDA = 0x96,
--	Ellesmere_I2CLineID_DDCVGA = 0x97
--};
--
--#define ELLESMERE_I2C_DDC1DATA          0
--#define ELLESMERE_I2C_DDC1CLK           1
--#define ELLESMERE_I2C_DDC2DATA          2
--#define ELLESMERE_I2C_DDC2CLK           3
--#define ELLESMERE_I2C_DDC3DATA          4
--#define ELLESMERE_I2C_DDC3CLK           5
--#define ELLESMERE_I2C_SDA               40
--#define ELLESMERE_I2C_SCL               41
--#define ELLESMERE_I2C_DDC4DATA          65
--#define ELLESMERE_I2C_DDC4CLK           66
--#define ELLESMERE_I2C_DDC5DATA          0x48
--#define ELLESMERE_I2C_DDC5CLK           0x49
--#define ELLESMERE_I2C_DDC6DATA          0x4a
--#define ELLESMERE_I2C_DDC6CLK           0x4b
--#define ELLESMERE_I2C_DDCVGADATA        0x4c
--#define ELLESMERE_I2C_DDCVGACLK         0x4d
--
--#define ELLESMERE_UNUSED_GPIO_PIN       0x7F
--
--int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
--
--int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
--int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
--int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
-deleted file mode 100644
-index ff41c41..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c
-+++ /dev/null
-@@ -1,396 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#include "hwmgr.h"
--#include "smumgr.h"
--#include "ellesmere_hwmgr.h"
--#include "ellesmere_powertune.h"
--#include "ellesmere_smumgr.h"
--#include "smu74_discrete.h"
--#include "pp_debug.h"
--
--#define VOLTAGE_SCALE  4
--#define POWERTUNE_DEFAULT_SET_MAX    1
--
--struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
--	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
--	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
--	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
--	{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
--	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
--};
--
--void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *ellesmere_hwmgr = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct  phm_ppt_v1_information *table_info =
--			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
--
--	if (table_info &&
--			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
--			table_info->cac_dtp_table->usPowerTuneDataSetID)
--		ellesmere_hwmgr->power_tune_defaults =
--				&ellesmere_power_tune_data_set_array
--				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
--	else
--		ellesmere_hwmgr->power_tune_defaults = &ellesmere_power_tune_data_set_array[0];
--
--}
--
--int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
--	SMU74_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
--	int i, j, k;
--	uint16_t *pdef1;
--	uint16_t *pdef2;
--
--	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
--	dpm_table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
--
--	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
--				"Target Operating Temp is out of Range!",
--				);
--/*  This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */
--	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
--
--/*  HW request to hard code this value to 8 which is 0.5C */
--	dpm_table->GpuTjHyst = 8;
--
--	dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
--	dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset);
--	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT);
--	pdef1 = defaults->BAPMTI_R;
--	pdef2 = defaults->BAPMTI_RC;
--
--	for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
--		for (j = 0; j < SMU74_DTE_SOURCES; j++) {
--			for (k = 0; k < SMU74_DTE_SINKS; k++) {
--				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
--				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
--				pdef1++;
--				pdef2++;
--			}
--		}
--	}
--
--	return 0;
--}
--
--static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
--
--	data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
--	data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
--	data->power_tune_table.SviLoadLineTrimVddC = 3;
--	data->power_tune_table.SviLoadLineOffsetVddC = 0;
--
--	return 0;
--}
--
--static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr)
--{
--	uint16_t tdc_limit;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct  ellesmere_pt_defaults *defaults = data->power_tune_defaults;
--
--	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
--	data->power_tune_table.TDC_VDDC_PkgLimit =
--			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
--	data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
--			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
--	data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
--
--	return 0;
--}
--
--static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
--	uint32_t temp;
--
--	if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--			fuse_table_offset +
--			offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
--			(uint32_t *)&temp, data->sram_end))
--		PP_ASSERT_WITH_CODE(false,
--				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
--				return -EINVAL);
--	else {
--		data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
--		data->power_tune_table.LPMLTemperatureMin =
--				(uint8_t)((temp >> 16) & 0xff);
--		data->power_tune_table.LPMLTemperatureMax =
--				(uint8_t)((temp >> 8) & 0xff);
--		data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
--	}
--	return 0;
--}
--
--static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
--{
--	int i;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	/* Currently not used. Set all to zero. */
--	for (i = 0; i < 16; i++)
--		data->power_tune_table.LPMLTemperatureScaler[i] = 0;
--
--	return 0;
--}
--
--static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
--		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
--		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
--			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
--
--	data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
--				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
--	return 0;
--}
--
--static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
--{
--	int i;
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	/* Currently not used. Set all to zero. */
--	for (i = 0; i < 16; i++)
--		data->power_tune_table.GnbLPML[i] = 0;
--
--	return 0;
--}
--
--static int ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
--{
--	return 0;
--}
--
--static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
--	uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd;
--	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
--
--	hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
--	lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
--
--	data->power_tune_table.BapmVddCBaseLeakageHiSidd =
--			CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
--	data->power_tune_table.BapmVddCBaseLeakageLoSidd =
--			CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
--
--	return 0;
--}
--
--int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	uint32_t pm_fuse_table_offset;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
--		if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
--				SMU7_FIRMWARE_HEADER_LOCATION +
--				offsetof(SMU74_Firmware_Header, PmFuseTable),
--				&pm_fuse_table_offset, data->sram_end))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to get pm_fuse_table_offset Failed!",
--					return -EINVAL);
--
--		if (ellesmere_populate_svi_load_line(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate SviLoadLine Failed!",
--					return -EINVAL);
--
--		if (ellesmere_populate_tdc_limit(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate TDCLimit Failed!", return -EINVAL);
--
--		if (ellesmere_populate_dw8(hwmgr, pm_fuse_table_offset))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate TdcWaterfallCtl, "
--					"LPMLTemperature Min and Max Failed!",
--					return -EINVAL);
--
--		if (0 != ellesmere_populate_temperature_scaler(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate LPMLTemperatureScaler Failed!",
--					return -EINVAL);
--
--		if (ellesmere_populate_fuzzy_fan(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate Fuzzy Fan Control parameters Failed!",
--					return -EINVAL);
--
--		if (ellesmere_populate_gnb_lpml(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate GnbLPML Failed!",
--					return -EINVAL);
--
--		if (ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate GnbLPML Min and Max Vid Failed!",
--					return -EINVAL);
--
--		if (ellesmere_populate_bapm_vddc_base_leakage_sidd(hwmgr))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
--					"Sidd Failed!", return -EINVAL);
--
--		if (ellesmere_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
--				(uint8_t *)&data->power_tune_table,
--				sizeof(struct SMU74_Discrete_PmFuses), data->sram_end))
--			PP_ASSERT_WITH_CODE(false,
--					"Attempt to download PmFuseTable Failed!",
--					return -EINVAL);
--	}
--	return 0;
--}
--
--int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	int result = 0;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_CAC)) {
--		int smc_result;
--		smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
--				(uint16_t)(PPSMC_MSG_EnableCac));
--		PP_ASSERT_WITH_CODE((0 == smc_result),
--				"Failed to enable CAC in SMC.", result = -1);
--
--		data->cac_enabled = (0 == smc_result) ? true : false;
--	}
--	return result;
--}
--
--int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--
--	if (data->power_containment_features &
--			POWERCONTAINMENT_FEATURE_PkgPwrLimit)
--		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_PkgPwrSetLimit, n);
--	return 0;
--}
--
--static int ellesmere_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
--{
--	return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
--			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
--}
--
--int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	int smc_result;
--	int result = 0;
--
--	data->power_containment_features = 0;
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
--		if (data->enable_dte_feature) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
--					(uint16_t)(PPSMC_MSG_EnableDTE));
--			PP_ASSERT_WITH_CODE((0 == smc_result),
--					"Failed to enable DTE in SMC.", result = -1;);
--			if (0 == smc_result)
--				data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
--		}
--
--		if (data->enable_tdc_limit_feature) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
--					(uint16_t)(PPSMC_MSG_TDCLimitEnable));
--			PP_ASSERT_WITH_CODE((0 == smc_result),
--					"Failed to enable TDCLimit in SMC.", result = -1;);
--			if (0 == smc_result)
--				data->power_containment_features |=
--						POWERCONTAINMENT_FEATURE_TDCLimit;
--		}
--
--		if (data->enable_pkg_pwr_tracking_feature) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
--					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
--			PP_ASSERT_WITH_CODE((0 == smc_result),
--					"Failed to enable PkgPwrTracking in SMC.", result = -1;);
--			if (0 == smc_result) {
--				struct phm_cac_tdp_table *cac_table =
--						table_info->cac_dtp_table;
--				uint32_t default_limit =
--					(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
--
--				data->power_containment_features |=
--						POWERCONTAINMENT_FEATURE_PkgPwrLimit;
--
--				if (ellesmere_set_power_limit(hwmgr, default_limit))
--					printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
--			}
--		}
--	}
--	return result;
--}
--
--int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr)
--{
--	struct phm_ppt_v1_information *table_info =
--			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
--	int adjust_percent, target_tdp;
--	int result = 0;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
--		/* adjustment percentage has already been validated */
--		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
--				hwmgr->platform_descriptor.TDPAdjustment :
--				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
--		/* SMC requested that target_tdp to be 7 bit fraction in DPM table
--		 * but message to be 8 bit fraction for messages
--		 */
--		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
--		result = ellesmere_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
--	}
--
--	return result;
--}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h
-deleted file mode 100644
-index 5772bf9..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h
-+++ /dev/null
-@@ -1,70 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--#ifndef ELLESMERE_POWERTUNE_H
--#define ELLESMERE_POWERTUNE_H
--
--enum ellesmere_pt_config_reg_type {
--	ELLESMERE_CONFIGREG_MMR = 0,
--	ELLESMERE_CONFIGREG_SMC_IND,
--	ELLESMERE_CONFIGREG_DIDT_IND,
--	ELLESMERE_CONFIGREG_CACHE,
--	ELLESMERE_CONFIGREG_MAX
--};
--
--/* PowerContainment Features */
--#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
--#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
--#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
--
--struct ellesmere_pt_config_reg {
--	uint32_t                           offset;
--	uint32_t                           mask;
--	uint32_t                           shift;
--	uint32_t                           value;
--	enum ellesmere_pt_config_reg_type       type;
--};
--
--struct ellesmere_pt_defaults {
--	uint8_t   SviLoadLineEn;
--	uint8_t   SviLoadLineVddC;
--	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
--	uint8_t   TDC_MAWt;
--	uint8_t   TdcWaterfallCtl;
--	uint8_t   DTEAmbientTempBase;
--
--	uint32_t  DisplayCac;
--	uint32_t  BAPM_TEMP_GRADIENT;
--	uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
--	uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
--};
--
--void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
--int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
--int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr);
--int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr);
--int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr);
--int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
--int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr);
--
--#endif  /* ELLESMERE_POWERTUNE_H */
--
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
-deleted file mode 100644
-index 08be400..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c
-+++ /dev/null
-@@ -1,711 +0,0 @@
--/*
-- * Copyright 2016 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#include "ellesmere_thermal.h"
--#include "ellesmere_hwmgr.h"
--#include "ellesmere_smumgr.h"
--#include "ellesmere_ppsmc.h"
--#include "smu/smu_7_1_3_d.h"
--#include "smu/smu_7_1_3_sh_mask.h"
--
--int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
--		struct phm_fan_speed_info *fan_speed_info)
--{
--	if (hwmgr->thermal_controller.fanInfo.bNoFan)
--		return 0;
--
--	fan_speed_info->supports_percent_read = true;
--	fan_speed_info->supports_percent_write = true;
--	fan_speed_info->min_percent = 0;
--	fan_speed_info->max_percent = 100;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
--		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
--		fan_speed_info->supports_rpm_read = true;
--		fan_speed_info->supports_rpm_write = true;
--		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
--		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
--	} else {
--		fan_speed_info->min_rpm = 0;
--		fan_speed_info->max_rpm = 0;
--	}
--
--	return 0;
--}
--
--int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
--		uint32_t *speed)
--{
--	uint32_t duty100;
--	uint32_t duty;
--	uint64_t tmp64;
--
--	if (hwmgr->thermal_controller.fanInfo.bNoFan)
--		return 0;
--
--	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL1, FMAX_DUTY100);
--	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_STATUS, FDO_PWM_DUTY);
--
--	if (duty100 == 0)
--		return -EINVAL;
--
--
--	tmp64 = (uint64_t)duty * 100;
--	do_div(tmp64, duty100);
--	*speed = (uint32_t)tmp64;
--
--	if (*speed > 100)
--		*speed = 100;
--
--	return 0;
--}
--
--int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
--{
--	uint32_t tach_period;
--	uint32_t crystal_clock_freq;
--
--	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
--			(hwmgr->thermal_controller.fanInfo.
--				ucTachometerPulsesPerRevolution == 0))
--		return 0;
--
--	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_TACH_STATUS, TACH_PERIOD);
--
--	if (tach_period == 0)
--		return -EINVAL;
--
--	crystal_clock_freq = tonga_get_xclk(hwmgr);
--
--	*speed = 60 * crystal_clock_freq * 10000 / tach_period;
--
--	return 0;
--}
--
--/**
--* Set Fan Speed Control to static mode, so that the user can decide what speed to use.
--* @param    hwmgr  the address of the powerplay hardware manager.
--*           mode    the fan control mode, 0 default, 1 by percent, 5, by RPM
--* @exception Should always succeed.
--*/
--int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
--{
--
--	if (hwmgr->fan_ctrl_is_in_default_mode) {
--		hwmgr->fan_ctrl_default_mode =
--				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,	CGS_IND_REG__SMC,
--						CG_FDO_CTRL2, FDO_PWM_MODE);
--		hwmgr->tmin =
--				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--						CG_FDO_CTRL2, TMIN);
--		hwmgr->fan_ctrl_is_in_default_mode = false;
--	}
--
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL2, TMIN, 0);
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL2, FDO_PWM_MODE, mode);
--
--	return 0;
--}
--
--/**
--* Reset Fan Speed Control to default mode.
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @exception Should always succeed.
--*/
--int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
--{
--	if (!hwmgr->fan_ctrl_is_in_default_mode) {
--		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
--		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--				CG_FDO_CTRL2, TMIN, hwmgr->tmin);
--		hwmgr->fan_ctrl_is_in_default_mode = true;
--	}
--
--	return 0;
--}
--
--int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
--{
--	int result;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
--		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
--		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
--
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_FanSpeedInTableIsRPM))
--			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
--					hwmgr->thermal_controller.
--					advanceFanControlParameters.usMaxFanRPM);
--		else
--			hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
--					hwmgr->thermal_controller.
--					advanceFanControlParameters.usMaxFanPWM);
--
--	} else {
--		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
--		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
--	}
--
--	if (!result && hwmgr->thermal_controller.
--			advanceFanControlParameters.ucTargetTemperature)
--		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_SetFanTemperatureTarget,
--				hwmgr->thermal_controller.
--				advanceFanControlParameters.ucTargetTemperature);
--
--	return result;
--}
--
--
--int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
--{
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
--}
--
--/**
--* Set Fan Speed in percent.
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    speed is the percentage value (0% - 100%) to be set.
--* @exception Fails is the 100% setting appears to be 0.
--*/
--int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
--		uint32_t speed)
--{
--	uint32_t duty100;
--	uint32_t duty;
--	uint64_t tmp64;
--
--	if (hwmgr->thermal_controller.fanInfo.bNoFan)
--		return 0;
--
--	if (speed > 100)
--		speed = 100;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
--		ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr);
--
--	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL1, FMAX_DUTY100);
--
--	if (duty100 == 0)
--		return -EINVAL;
--
--	tmp64 = (uint64_t)speed * 100;
--	do_div(tmp64, duty100);
--	duty = (uint32_t)tmp64;
--
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
--
--	return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
--}
--
--/**
--* Reset Fan Speed to default.
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @exception Always succeeds.
--*/
--int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
--{
--	int result;
--
--	if (hwmgr->thermal_controller.fanInfo.bNoFan)
--		return 0;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl)) {
--		result = ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
--		if (!result)
--			result = ellesmere_fan_ctrl_start_smc_fan_control(hwmgr);
--	} else
--		result = ellesmere_fan_ctrl_set_default_mode(hwmgr);
--
--	return result;
--}
--
--/**
--* Set Fan Speed in RPM.
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    speed is the percentage value (min - max) to be set.
--* @exception Fails is the speed not lie between min and max.
--*/
--int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
--{
--	uint32_t tach_period;
--	uint32_t crystal_clock_freq;
--
--	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
--			(hwmgr->thermal_controller.fanInfo.
--			ucTachometerPulsesPerRevolution == 0) ||
--			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
--			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
--		return 0;
--
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
--		ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr);
--
--	crystal_clock_freq = tonga_get_xclk(hwmgr);
--
--	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
--
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--				CG_TACH_STATUS, TACH_PERIOD, tach_period);
--
--	return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
--}
--
--/**
--* Reads the remote temperature from the SIslands thermal controller.
--*
--* @param    hwmgr The address of the hardware manager.
--*/
--int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr)
--{
--	int temp;
--
--	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_MULT_THERMAL_STATUS, CTF_TEMP);
--
--	/* Bit 9 means the reading is lower than the lowest usable value. */
--	if (temp & 0x200)
--		temp = ELLESMERE_THERMAL_MAXIMUM_TEMP_READING;
--	else
--		temp = temp & 0x1ff;
--
--	temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
--
--	return temp;
--}
--
--/**
--* Set the requested temperature range for high and low alert signals
--*
--* @param    hwmgr The address of the hardware manager.
--* @param    range Temperature range to be programmed for high and low alert signals
--* @exception PP_Result_BadInput if the input data is not valid.
--*/
--static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
--		uint32_t low_temp, uint32_t high_temp)
--{
--	uint32_t low = ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP *
--			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
--	uint32_t high = ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP *
--			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
--
--	if (low < low_temp)
--		low = low_temp;
--	if (high > high_temp)
--		high = high_temp;
--
--	if (low > high)
--		return -EINVAL;
--
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_INT, DIG_THERM_INTH,
--			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_INT, DIG_THERM_INTL,
--			(low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_CTRL, DIG_THERM_DPM,
--			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
--
--	return 0;
--}
--
--/**
--* Programs thermal controller one-time setting registers
--*
--* @param    hwmgr The address of the hardware manager.
--*/
--static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
--{
--	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
--		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--				CG_TACH_CTRL, EDGE_PER_REV,
--				hwmgr->thermal_controller.fanInfo.
--				ucTachometerPulsesPerRevolution - 1);
--
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
--
--	return 0;
--}
--
--/**
--* Enable thermal alerts on the RV770 thermal controller.
--*
--* @param    hwmgr The address of the hardware manager.
--*/
--static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr)
--{
--	uint32_t alert;
--
--	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_INT, THERM_INT_MASK);
--	alert &= ~(ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK);
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_INT, THERM_INT_MASK, alert);
--
--	/* send message to SMU to enable internal thermal interrupts */
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
--}
--
--/**
--* Disable thermal alerts on the RV770 thermal controller.
--* @param    hwmgr The address of the hardware manager.
--*/
--static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr)
--{
--	uint32_t alert;
--
--	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_INT, THERM_INT_MASK);
--	alert |= (ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK);
--	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_THERMAL_INT, THERM_INT_MASK, alert);
--
--	/* send message to SMU to disable internal thermal interrupts */
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
--}
--
--/**
--* Uninitialize the thermal controller.
--* Currently just disables alerts.
--* @param    hwmgr The address of the hardware manager.
--*/
--int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
--{
--	int result = ellesmere_thermal_disable_alert(hwmgr);
--
--	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
--		ellesmere_fan_ctrl_set_default_mode(hwmgr);
--
--	return result;
--}
--
--/**
--* Set up the fan table to control the fan using the SMC.
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from set temperature range routine
--*/
--int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
--	SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
--	uint32_t duty100;
--	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
--	uint16_t fdo_min, slope1, slope2;
--	uint32_t reference_clock;
--	int res;
--	uint64_t tmp64;
--
--	if (data->fan_table_start == 0) {
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_MicrocodeFanControl);
--		return 0;
--	}
--
--	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--			CG_FDO_CTRL1, FMAX_DUTY100);
--
--	if (duty100 == 0) {
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_MicrocodeFanControl);
--		return 0;
--	}
--
--	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
--			usPWMMin * duty100;
--	do_div(tmp64, 10000);
--	fdo_min = (uint16_t)tmp64;
--
--	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
--			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
--	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
--			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
--
--	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
--			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
--	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
--			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
--
--	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
--	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
--
--	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
--			thermal_controller.advanceFanControlParameters.usTMin) / 100);
--	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
--			thermal_controller.advanceFanControlParameters.usTMed) / 100);
--	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
--			thermal_controller.advanceFanControlParameters.usTMax) / 100);
--
--	fan_table.Slope1 = cpu_to_be16(slope1);
--	fan_table.Slope2 = cpu_to_be16(slope2);
--
--	fan_table.FdoMin = cpu_to_be16(fdo_min);
--
--	fan_table.HystDown = cpu_to_be16(hwmgr->
--			thermal_controller.advanceFanControlParameters.ucTHyst);
--
--	fan_table.HystUp = cpu_to_be16(1);
--
--	fan_table.HystSlope = cpu_to_be16(1);
--
--	fan_table.TempRespLim = cpu_to_be16(5);
--
--	reference_clock = tonga_get_xclk(hwmgr);
--
--	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
--			thermal_controller.advanceFanControlParameters.ulCycleDelay *
--			reference_clock) / 1600);
--
--	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
--
--	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
--			hwmgr->device, CGS_IND_REG__SMC,
--			CG_MULT_THERMAL_CTRL, TEMP_SEL);
--
--	res = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start,
--			(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
--			data->sram_end);
--
--	if (!res && hwmgr->thermal_controller.
--			advanceFanControlParameters.ucMinimumPWMLimit)
--		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_SetFanMinPwm,
--				hwmgr->thermal_controller.
--				advanceFanControlParameters.ucMinimumPWMLimit);
--
--	if (!res && hwmgr->thermal_controller.
--			advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
--		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_SetFanSclkTarget,
--				hwmgr->thermal_controller.
--				advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
--
--	if (res)
--		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_MicrocodeFanControl);
--
--	return 0;
--}
--
--/**
--* Start the fan control on the SMC.
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from set temperature range routine
--*/
--int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--/* If the fantable setup has failed we could have disabled
-- * PHM_PlatformCaps_MicrocodeFanControl even after
-- * this function was included in the table.
-- * Make sure that we still think controlling the fan is OK.
--*/
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl)) {
--		ellesmere_fan_ctrl_start_smc_fan_control(hwmgr);
--		ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
--	}
--
--	return 0;
--}
--
--/**
--* Set temperature range for high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from set temperature range routine
--*/
--int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
--
--	if (range == NULL)
--		return -EINVAL;
--
--	return ellesmere_thermal_set_temperature_range(hwmgr, range->min, range->max);
--}
--
--/**
--* Programs one-time setting registers
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from initialize thermal controller routine
--*/
--int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--    return ellesmere_thermal_initialize(hwmgr);
--}
--
--/**
--* Enable high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from enable alert routine
--*/
--int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return ellesmere_thermal_enable_alert(hwmgr);
--}
--
--/**
--* Disable high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from disable alert routine
--*/
--static int tf_ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return ellesmere_thermal_disable_alert(hwmgr);
--}
--
--static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	int ret;
--	struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--
--	if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
--		return 0;
--
--	ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
--			0 : -1;
--
--	if (!ret)
--		/* If this param is not changed, this function could fire unnecessarily */
--		smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
--
--	return ret;
--}
--
--static struct phm_master_table_item
--ellesmere_thermal_start_thermal_controller_master_list[] = {
--	{NULL, tf_ellesmere_thermal_initialize},
--	{NULL, tf_ellesmere_thermal_set_temperature_range},
--	{NULL, tf_ellesmere_thermal_enable_alert},
--	{NULL, tf_ellesmere_thermal_avfs_enable},
--/* We should restrict performance levels to low before we halt the SMC.
-- * On the other hand we are still in boot state when we do this
-- * so it would be pointless.
-- * If this assumption changes we have to revisit this table.
-- */
--	{NULL, tf_ellesmere_thermal_setup_fan_table},
--	{NULL, tf_ellesmere_thermal_start_smc_fan_control},
--	{NULL, NULL}
--};
--
--static struct phm_master_table_header
--ellesmere_thermal_start_thermal_controller_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	ellesmere_thermal_start_thermal_controller_master_list
--};
--
--static struct phm_master_table_item
--ellesmere_thermal_set_temperature_range_master_list[] = {
--	{NULL, tf_ellesmere_thermal_disable_alert},
--	{NULL, tf_ellesmere_thermal_set_temperature_range},
--	{NULL, tf_ellesmere_thermal_enable_alert},
--	{NULL, NULL}
--};
--
--struct phm_master_table_header
--ellesmere_thermal_set_temperature_range_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	ellesmere_thermal_set_temperature_range_master_list
--};
--
--int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
--{
--	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
--		ellesmere_fan_ctrl_set_default_mode(hwmgr);
--	return 0;
--}
--
--/**
--* Initializes the thermal controller related functions in the Hardware Manager structure.
--* @param    hwmgr The address of the hardware manager.
--* @exception Any error code from the low-level communication.
--*/
--int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
--{
--	int result;
--
--	result = phm_construct_table(hwmgr,
--			&ellesmere_thermal_set_temperature_range_master,
--			&(hwmgr->set_temperature_range));
--
--	if (!result) {
--		result = phm_construct_table(hwmgr,
--				&ellesmere_thermal_start_thermal_controller_master,
--				&(hwmgr->start_thermal_controller));
--		if (result)
--			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
--	}
--
--	if (!result)
--		hwmgr->fan_ctrl_is_in_default_mode = true;
--	return result;
--}
--
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h
-deleted file mode 100644
-index 4263e9b..0000000
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h
-+++ /dev/null
-@@ -1,62 +0,0 @@
--/*
-- * Copyright 2016 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef _ELLESMERE_THERMAL_H_
--#define _ELLESMERE_THERMAL_H_
--
--#include "hwmgr.h"
--
--#define ELLESMERE_THERMAL_HIGH_ALERT_MASK         0x1
--#define ELLESMERE_THERMAL_LOW_ALERT_MASK          0x2
--
--#define ELLESMERE_THERMAL_MINIMUM_TEMP_READING    -256
--#define ELLESMERE_THERMAL_MAXIMUM_TEMP_READING    255
--
--#define ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP      0
--#define ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP      255
--
--#define FDO_PWM_MODE_STATIC  1
--#define FDO_PWM_MODE_STATIC_RPM 5
--
--
--extern int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
--extern int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
--extern int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
--
--extern int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr);
--extern int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
--extern int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
--extern int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
--extern int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
--extern int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
--extern int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
--extern int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
--extern int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr);
--extern int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
--extern int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
--extern int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
--extern int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
--extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-index 2c68199..7d69ed6 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
-@@ -34,7 +34,7 @@
- extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
- extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
- extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
--extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
-+extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
- 
- int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -68,9 +68,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		case CHIP_FIJI:
- 			fiji_hwmgr_init(hwmgr);
- 			break;
--		case CHIP_BAFFIN:
--		case CHIP_ELLESMERE:
--			ellesemere_hwmgr_init(hwmgr);
-+		case CHIP_POLARIS11:
-+		case CHIP_POLARIS10:
-+			polaris10_hwmgr_init(hwmgr);
- 			break;
- 		default:
- 			return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
-new file mode 100644
-index 0000000..e362ddb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
-@@ -0,0 +1,428 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "polaris10_clockpowergating.h"
-+
-+int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_uvd_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_UVDPowerOFF);
-+	return 0;
-+}
-+
-+int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_uvd_power_gating(hwmgr)) {
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDPowerON, 1);
-+		} else {
-+			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDPowerON, 0);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_vce_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_VCEPowerOFF);
-+	return 0;
-+}
-+
-+int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cf_want_vce_power_gating(hwmgr))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_VCEPowerON);
-+	return 0;
-+}
-+
-+int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SamuPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SAMPowerOFF);
-+	return 0;
-+}
-+
-+int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SamuPowerGating))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SAMPowerON);
-+	return 0;
-+}
-+
-+int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+	data->samu_power_gated = false;
-+
-+	polaris10_phm_powerup_uvd(hwmgr);
-+	polaris10_phm_powerup_vce(hwmgr);
-+	polaris10_phm_powerup_samu(hwmgr);
-+
-+	return 0;
-+}
-+
-+int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (data->uvd_power_gated == bgate)
-+		return 0;
-+
-+	data->uvd_power_gated = bgate;
-+
-+	if (bgate) {
-+		polaris10_update_uvd_dpm(hwmgr, true);
-+		polaris10_phm_powerdown_uvd(hwmgr);
-+	} else {
-+		polaris10_phm_powerup_uvd(hwmgr);
-+		polaris10_update_uvd_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (data->vce_power_gated == bgate)
-+		return 0;
-+
-+	if (bgate)
-+		polaris10_phm_powerdown_vce(hwmgr);
-+	else
-+		polaris10_phm_powerup_vce(hwmgr);
-+
-+	return 0;
-+}
-+
-+int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (data->samu_power_gated == bgate)
-+		return 0;
-+
-+	data->samu_power_gated = bgate;
-+
-+	if (bgate) {
-+		polaris10_update_samu_dpm(hwmgr, true);
-+		polaris10_phm_powerdown_samu(hwmgr);
-+	} else {
-+		polaris10_phm_powerup_samu(hwmgr);
-+		polaris10_update_samu_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
-+					const uint32_t *msg_id)
-+{
-+	PPSMC_Msg msg;
-+	uint32_t value;
-+
-+	switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
-+	case PP_GROUP_GFX:
-+		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
-+		case PP_BLOCK_GFX_CG:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
-+					? PPSMC_MSG_EnableClockGatingFeature
-+					: PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_3D:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_3DCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if  (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_3DLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_RLC:
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_RLC_LS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_CP:
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_GFX_CP_LS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_GFX_MG:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = (CG_CPF_MGCG_MASK | CG_RLC_MGCG_MASK |
-+						CG_GFX_OTHERS_MGCG_MASK);
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		default:
-+			return -1;
-+		}
-+		break;
-+
-+	case PP_GROUP_SYS:
-+		switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
-+		case PP_BLOCK_SYS_BIF:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_BIF_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if  (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_BIF_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_MC:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_MC_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_MC_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_DRM:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_CG ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_DRM_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_DRM_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_HDP:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_HDP_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_HDP_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_SDMA:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)	?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_SDMA_MGCG_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+
-+			if (PP_STATE_SUPPORT_LS & *msg_id) {
-+				msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_SDMA_MGLS_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		case PP_BLOCK_SYS_ROM:
-+			if (PP_STATE_SUPPORT_CG & *msg_id) {
-+				msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ?
-+						PPSMC_MSG_EnableClockGatingFeature :
-+						PPSMC_MSG_DisableClockGatingFeature;
-+				value = CG_SYS_ROM_MASK;
-+
-+				if (smum_send_msg_to_smc_with_parameter(
-+						hwmgr->smumgr, msg, value))
-+					return -1;
-+			}
-+			break;
-+
-+		default:
-+			return -1;
-+
-+		}
-+		break;
-+
-+	default:
-+		return -1;
-+
-+	}
-+
-+	return 0;
-+}
-+
-+/* This function is for Polaris11 only for now,
-+ * Powerplay will only control the static per CU Power Gating.
-+ * Dynamic per CU Power Gating will be done in gfx.
-+ */
-+int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	struct cgs_system_info sys_info = {0};
-+	uint32_t active_cus;
-+	int result;
-+
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
-+
-+	result = cgs_query_system_info(hwmgr->device, &sys_info);
-+
-+	if (result)
-+		return -EINVAL;
-+	else
-+		active_cus = sys_info.value;
-+
-+	if (enable)
-+		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
-+	else
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_GFX_CU_PG_DISABLE);
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h
-new file mode 100644
-index 0000000..88d68cb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _POLARIS10_CLOCK_POWER_GATING_H_
-+#define _POLARIS10_CLOCK_POWER_GATING_H_
-+
-+#include "polaris10_hwmgr.h"
-+#include "pp_asicblocks.h"
-+
-+int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
-+int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
-+int polaris10_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
-+int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
-+int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
-+					const uint32_t *msg_id);
-+int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
-+
-+#endif /* _POLARIS10_CLOCK_POWER_GATING_H_ */
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h
-new file mode 100644
-index 0000000..f78ffd9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef POLARIS10_DYN_DEFAULTS_H
-+#define POLARIS10_DYN_DEFAULTS_H
-+
-+
-+enum Polaris10dpm_TrendDetection {
-+	Polaris10Adpm_TrendDetection_AUTO,
-+	Polaris10Adpm_TrendDetection_UP,
-+	Polaris10Adpm_TrendDetection_DOWN
-+};
-+typedef enum Polaris10dpm_TrendDetection Polaris10dpm_TrendDetection;
-+
-+/*  We need to fill in the default values */
-+
-+
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1              0x000400
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033
-+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000
-+
-+
-+#define PPPOLARIS10_THERMALPROTECTCOUNTER_DFLT            0x200
-+#define PPPOLARIS10_STATICSCREENTHRESHOLDUNIT_DFLT        0
-+#define PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT            0x00C8
-+#define PPPOLARIS10_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200
-+#define PPPOLARIS10_REFERENCEDIVIDER_DFLT                  4
-+
-+#define PPPOLARIS10_ULVVOLTAGECHANGEDELAY_DFLT             1687
-+
-+#define PPPOLARIS10_CGULVPARAMETER_DFLT                    0x00040035
-+#define PPPOLARIS10_CGULVCONTROL_DFLT                      0x00007450
-+#define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
-+#define PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT                10
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-new file mode 100644
-index 0000000..5080d67
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -0,0 +1,4844 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+#include "linux/delay.h"
-+#include "pp_acpi.h"
-+#include "hwmgr.h"
-+#include "polaris10_hwmgr.h"
-+#include "polaris10_powertune.h"
-+#include "polaris10_dyn_defaults.h"
-+#include "polaris10_smumgr.h"
-+#include "pp_debug.h"
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "tonga_pptable.h"
-+#include "pppcielanes.h"
-+#include "amd_pcie_helpers.h"
-+#include "hardwaremanager.h"
-+#include "tonga_processpptables.h"
-+#include "cgs_common.h"
-+#include "smu74.h"
-+#include "smu_ucode_xfer_vi.h"
-+#include "smu74_discrete.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "oss/oss_3_0_d.h"
-+#include "gca/gfx_8_0_d.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+#include "polaris10_thermal.h"
-+#include "polaris10_clockpowergating.h"
-+
-+#define MC_CG_ARB_FREQ_F0           0x0a
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define MC_CG_ARB_FREQ_F2           0x0c
-+#define MC_CG_ARB_FREQ_F3           0x0d
-+
-+#define MC_CG_SEQ_DRAMCONF_S0       0x05
-+#define MC_CG_SEQ_DRAMCONF_S1       0x06
-+#define MC_CG_SEQ_YCLK_SUSPEND      0x04
-+#define MC_CG_SEQ_YCLK_RESUME       0x0a
-+
-+
-+#define SMC_RAM_END 0x40000
-+
-+#define SMC_CG_IND_START            0xc0030000
-+#define SMC_CG_IND_END              0xc0040000
-+
-+#define VOLTAGE_SCALE               4
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+
-+#define VDDC_VDDCI_DELTA            200
-+
-+#define MEM_FREQ_LOW_LATENCY        25000
-+#define MEM_FREQ_HIGH_LATENCY       80000
-+
-+#define MEM_LATENCY_HIGH            45
-+#define MEM_LATENCY_LOW             35
-+#define MEM_LATENCY_ERR             0xFFFF
-+
-+#define MC_SEQ_MISC0_GDDR5_SHIFT 28
-+#define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
-+#define MC_SEQ_MISC0_GDDR5_VALUE 5
-+
-+
-+#define PCIE_BUS_CLK                10000
-+#define TCLK                        (PCIE_BUS_CLK / 10)
-+
-+
-+uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
-+							  {600, 1050, 6, 1} };
-+
-+/*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
-+uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+							{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-+
-+/*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
-+uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
-+							    {0, 2, 4, 5, 6, 5} };
-+
-+/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
-+enum DPM_EVENT_SRC {
-+	DPM_EVENT_SRC_ANALOG = 0,
-+	DPM_EVENT_SRC_EXTERNAL = 1,
-+	DPM_EVENT_SRC_DIGITAL = 2,
-+	DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
-+	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
-+};
-+
-+const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
-+
-+struct polaris10_power_state *cast_phw_polaris10_power_state(
-+				  struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL);
-+
-+	return (struct polaris10_power_state *)hw_ps;
-+}
-+
-+const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
-+				 const struct pp_hw_power_state *hw_ps)
-+{
-+	PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
-+				"Invalid Powerstate Type!",
-+				 return NULL);
-+
-+	return (const struct polaris10_power_state *)hw_ps;
-+}
-+
-+static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
-+/**
-+ * Find the MC microcode version and store it in the HwMgr struct
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
-+{
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
-+
-+	hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
-+
-+	return 0;
-+}
-+
-+uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t speedCntl = 0;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
-+			ixPCIE_LC_SPEED_CNTL);
-+	return((uint16_t)PHM_GET_FIELD(speedCntl,
-+			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
-+}
-+
-+int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t link_width;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
-+			PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
-+
-+	PP_ASSERT_WITH_CODE((7 >= link_width),
-+			"Invalid PCIe lane width!", return 0);
-+
-+	return decode_pcie_lane_width(link_width);
-+}
-+
-+void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_clock_voltage_dependency_table *table =
-+				table_info->vddc_dep_on_dal_pwrl;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-+	enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-+	uint32_t req_vddc = 0, req_volt, i;
-+
-+	if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
-+			dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
-+		return;
-+
-+	for (i = 0; i < table->count; i++) {
-+		if (dal_power_level == table->entries[i].clk) {
-+			req_vddc = table->entries[i].v;
-+			break;
-+		}
-+	}
-+
-+	vddc_table = table_info->vdd_dep_on_sclk;
-+	for (i = 0; i < vddc_table->count; i++) {
-+		if (req_vddc <= vddc_table->entries[i].vddc) {
-+			req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-+					<< VDDC_SHIFT;
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VddC_Request, req_volt);
-+			return;
-+		}
-+	}
-+	printk(KERN_ERR "DAL requested level can not"
-+			" found a available voltage in VDDC DPM Table \n");
-+}
-+
-+/**
-+* Enable voltage control
-+*
-+* @param    pHwMgr  the address of the powerplay hardware manager.
-+* @return   always PP_Result_OK
-+*/
-+int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
-+{
-+	PP_ASSERT_WITH_CODE(
-+		(hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
-+		"Failed to enable voltage DPM during DPM Start Function!",
-+		return 1;
-+	);
-+
-+	return 0;
-+}
-+
-+/**
-+* Checks if we want to support voltage control
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*/
-+static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
-+{
-+	const struct polaris10_hwmgr *data =
-+			(const struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
-+}
-+
-+/**
-+* Enable voltage control
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
-+{
-+	/* enable voltage control */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Create Voltage Tables.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	int result;
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
-+				&(data->mvdd_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve MVDD table.",
-+				return result);
-+	} else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
-+				table_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 MVDD table from dependancy table.",
-+				return result;);
-+	}
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		result = atomctrl_get_voltage_table_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
-+				&(data->vddci_voltage_table));
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve VDDCI table.",
-+				return result);
-+	} else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
-+				table_info->vdd_dep_on_mclk);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 VDDCI table from dependancy table.",
-+				return result);
-+	}
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
-+				table_info->vddc_lookup_table);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to retrieve SVI2 VDDC table from lookup table.",
-+				return result);
-+	}
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
-+			"Too many voltage values for VDDC. Trimming to fit state table.",
-+			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
-+								&(data->vddc_voltage_table)));
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
-+			"Too many voltage values for VDDCI. Trimming to fit state table.",
-+			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
-+					&(data->vddci_voltage_table)));
-+
-+	PP_ASSERT_WITH_CODE(
-+			(data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
-+			"Too many voltage values for MVDD. Trimming to fit state table.",
-+			phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
-+							   &(data->mvdd_voltage_table)));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs static screed detection parameters
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int polaris10_program_static_screen_threshold_parameters(
-+							struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	/* Set static screen threshold unit */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
-+			data->static_screen_threshold_unit);
-+	/* Set static screen threshold */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
-+			data->static_screen_threshold);
-+
-+	return 0;
-+}
-+
-+/**
-+* Setup display gap for glitch free memory clock switching.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t display_gap =
-+			cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixCG_DISPLAY_GAP_CNTL);
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP, DISPLAY_GAP_IGNORE);
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
-+			DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs activity state transition voting clients
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	/* Clear reset for voting clients before enabling DPM */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
-+
-+	return 0;
-+}
-+
-+/**
-+* Get the location of various tables inside the FW image.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always  0
-+*/
-+static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, DpmTable),
-+			&tmp, data->sram_end);
-+
-+	if (0 == result)
-+		data->dpm_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, SoftRegisters),
-+			&tmp, data->sram_end);
-+
-+	if (!result) {
-+		data->soft_regs_start = tmp;
-+		smu_data->soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, mcRegisterTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->mc_reg_table_start = tmp;
-+
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, FanTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->fan_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		data->arb_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, Version),
-+			&tmp, data->sram_end);
-+
-+	if (!result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (0 != result);
-+
-+	return error ? -1 : 0;
-+}
-+
-+/* Copy one arb setting to another and then switch the active set.
-+ * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
-+ */
-+static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
-+		uint32_t arb_src, uint32_t arb_dest)
-+{
-+	uint32_t mc_arb_dram_timing;
-+	uint32_t mc_arb_dram_timing2;
-+	uint32_t burst_time;
-+	uint32_t mc_cg_config;
-+
-+	switch (arb_src) {
-+	case MC_CG_ARB_FREQ_F0:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+		break;
-+	case MC_CG_ARB_FREQ_F1:
-+		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
-+		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
-+		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (arb_dest) {
-+	case MC_CG_ARB_FREQ_F0:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
-+		break;
-+	case MC_CG_ARB_FREQ_F1:
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
-+		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
-+		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
-+	mc_cg_config |= 0x0000000F;
-+	cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
-+	PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
-+
-+	return 0;
-+}
-+
-+/**
-+* Initial switch from ARB F0->F1
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+* This function is to be called from the SetPowerState table.
-+*/
-+static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
-+{
-+	return polaris10_copy_and_switch_arb_sets(hwmgr,
-+			MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
-+}
-+
-+static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint32_t i, max_entry;
-+
-+	PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
-+			data->use_pcie_power_saving_levels), "No pcie performance levels!",
-+			return -EINVAL);
-+
-+	if (data->use_pcie_performance_levels &&
-+			!data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_power_saving = data->pcie_gen_performance;
-+		data->pcie_lane_power_saving = data->pcie_lane_performance;
-+	} else if (!data->use_pcie_performance_levels &&
-+			data->use_pcie_power_saving_levels) {
-+		data->pcie_gen_performance = data->pcie_gen_power_saving;
-+		data->pcie_lane_performance = data->pcie_lane_power_saving;
-+	}
-+
-+	phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
-+					SMU74_MAX_LEVELS_LINK,
-+					MAX_REGULAR_DPM_NUMBER);
-+
-+	if (pcie_table != NULL) {
-+		/* max_entry is used to make sure we reserve one PCIE level
-+		 * for boot level (fix for A+A PSPP issue).
-+		 * If PCIE table from PPTable have ULV entry + 8 entries,
-+		 * then ignore the last entry.*/
-+		max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
-+				SMU74_MAX_LEVELS_LINK : pcie_table->count;
-+		for (i = 1; i < max_entry; i++) {
-+			phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
-+					get_pcie_gen_support(data->pcie_gen_cap,
-+							pcie_table->entries[i].gen_speed),
-+					get_pcie_lane_support(data->pcie_lane_cap,
-+							pcie_table->entries[i].lane_width));
-+		}
-+		data->dpm_table.pcie_speed_table.count = max_entry - 1;
-+
-+		/* Setup BIF_SCLK levels */
-+		for (i = 0; i < max_entry; i++)
-+			data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
-+	} else {
-+		/* Hardcode Pcie Table */
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Min_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Min_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				get_pcie_lane_support(data->pcie_lane_cap,
-+						PP_Max_PCIELane));
-+
-+		data->dpm_table.pcie_speed_table.count = 6;
-+	}
-+	/* Populate last level for boot PCIE level, but do not increment count. */
-+	phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
-+			data->dpm_table.pcie_speed_table.count,
-+			get_pcie_gen_support(data->pcie_gen_cap,
-+					PP_Min_PCIEGen),
-+			get_pcie_lane_support(data->pcie_lane_cap,
-+					PP_Max_PCIELane));
-+
-+	return 0;
-+}
-+
-+/*
-+ * This function is to initalize all DPM state tables
-+ * for SMU7 based on the dependency table.
-+ * Dynamic state patching function will then trim these
-+ * state tables to the allowed range based
-+ * on the power policy or external client requests,
-+ * such as UVD request, etc.
-+ */
-+int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i;
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
-+			"SCLK dependency table is missing. This table is mandatory",
-+			return -EINVAL);
-+	PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
-+			"SCLK dependency table has to have is missing."
-+			"This table is mandatory",
-+			return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
-+			"MCLK dependency table is missing. This table is mandatory",
-+			return -EINVAL);
-+	PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
-+			"MCLK dependency table has to have is missing."
-+			"This table is mandatory",
-+			return -EINVAL);
-+
-+	/* clear the state table to reset everything to default */
-+	phm_reset_single_dpm_table(
-+			&data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
-+	phm_reset_single_dpm_table(
-+			&data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
-+
-+
-+	/* Initialize Sclk DPM table based on allow Sclk values */
-+	data->dpm_table.sclk_table.count = 0;
-+	for (i = 0; i < dep_sclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
-+						dep_sclk_table->entries[i].clk) {
-+
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
-+					dep_sclk_table->entries[i].clk;
-+
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
-+					(i == 0) ? true : false;
-+			data->dpm_table.sclk_table.count++;
-+		}
-+	}
-+
-+	/* Initialize Mclk DPM table based on allow Mclk values */
-+	data->dpm_table.mclk_table.count = 0;
-+	for (i = 0; i < dep_mclk_table->count; i++) {
-+		if (i == 0 || data->dpm_table.mclk_table.dpm_levels
-+				[data->dpm_table.mclk_table.count - 1].value !=
-+						dep_mclk_table->entries[i].clk) {
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
-+							dep_mclk_table->entries[i].clk;
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
-+							(i == 0) ? true : false;
-+			data->dpm_table.mclk_table.count++;
-+		}
-+	}
-+
-+	/* setup PCIE gen speed levels */
-+	polaris10_setup_default_pcie_table(hwmgr);
-+
-+	/* save a copy of the default DPM table */
-+	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
-+			sizeof(struct polaris10_dpm_table));
-+
-+	return 0;
-+}
-+
-+uint8_t convert_to_vid(uint16_t vddc)
-+{
-+	return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-+}
-+
-+/**
-+ * Mvdd table preparation for SMC.
-+ *
-+ * @param    *hwmgr The address of the hardware manager.
-+ * @param    *table The SMC DPM table structure to be populated.
-+ * @return   0
-+ */
-+static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU74_Discrete_DpmTable *table)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t count, level;
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		count = data->mvdd_voltage_table.count;
-+		if (count > SMU_MAX_SMIO_LEVELS)
-+			count = SMU_MAX_SMIO_LEVELS;
-+		for (level = 0; level < count; level++) {
-+			table->SmioTable2.Pattern[level].Voltage =
-+				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
-+			table->SmioTable2.Pattern[level].Smio =
-+				(uint8_t) level;
-+			table->Smio[level] |=
-+				data->mvdd_voltage_table.entries[level].smio_low;
-+		}
-+		table->SmioMask2 = data->vddci_voltage_table.mask_low;
-+
-+		table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
-+					struct SMU74_Discrete_DpmTable *table)
-+{
-+	uint32_t count, level;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	count = data->vddci_voltage_table.count;
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		if (count > SMU_MAX_SMIO_LEVELS)
-+			count = SMU_MAX_SMIO_LEVELS;
-+		for (level = 0; level < count; ++level) {
-+			table->SmioTable1.Pattern[level].Voltage =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
-+			table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
-+
-+			table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
-+		}
-+	}
-+
-+	table->SmioMask1 = data->vddci_voltage_table.mask_low;
-+
-+	return 0;
-+}
-+
-+/**
-+* Preparation of vddc and vddgfx CAC tables for SMC.
-+*
-+* @param    hwmgr  the address of the hardware manager
-+* @param    table  the SMC DPM table structure to be populated
-+* @return   always 0
-+*/
-+static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
-+			table_info->vddc_lookup_table;
-+	/* tables is already swapped, so in order to use the value from it,
-+	 * we need to swap it back.
-+	 * We are populating vddc CAC data to BapmVddc table
-+	 * in split and merged mode
-+	 */
-+	for (count = 0; count < lookup_table->count; count++) {
-+		index = phm_get_voltage_index(lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
-+		table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
-+		table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Preparation of voltage tables for SMC.
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    table   the SMC DPM table structure to be populated
-+* @return   always  0
-+*/
-+
-+int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	polaris10_populate_smc_vddci_table(hwmgr, table);
-+	polaris10_populate_smc_mvdd_table(hwmgr, table);
-+	polaris10_populate_cac_table(hwmgr, table);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_Ulv *state)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
-+	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
-+			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-+
-+	state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
-+}
-+
-+static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_dpm_table *dpm_table = &data->dpm_table;
-+	int i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count)
-+	 * is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
-+				dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity = 1;
-+		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	data->smc_state_table.LinkLevelCount =
-+			(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t reference_clock, tmp;
-+	struct cgs_display_info info = {0};
-+	struct cgs_mode_info mode_info;
-+
-+	info.mode_info = &mode_info;
-+
-+	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
-+
-+	if (tmp)
-+		return TCLK;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	reference_clock = mode_info.ref_clock;
-+
-+	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
-+
-+	if (0 != tmp)
-+		return reference_clock / 4;
-+
-+	return reference_clock;
-+}
-+
-+/**
-+* Calculates the SCLK dividers using the provided engine clock
-+*
-+* @param    hwmgr  the address of the hardware manager
-+* @param    clock  the engine clock to use to populate the structure
-+* @param    sclk   the SMC SCLK structure to be populated
-+*/
-+static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, SMU_SclkSetting *sclk_setting)
-+{
-+	const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
-+	struct pp_atomctrl_clock_dividers_ai dividers;
-+
-+	uint32_t ref_clock;
-+	uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
-+	uint8_t i;
-+	int result;
-+	uint64_t temp;
-+
-+	sclk_setting->SclkFrequency = clock;
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
-+	if (result == 0) {
-+		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
-+		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
-+		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
-+		sclk_setting->PllRange = dividers.ucSclkPllRange;
-+		sclk_setting->Sclk_slew_rate = 0x400;
-+		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
-+		sclk_setting->Pcc_down_slew_rate = 0xffff;
-+		sclk_setting->SSc_En = dividers.ucSscEnable;
-+		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
-+		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
-+		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
-+		return result;
-+	}
-+
-+	ref_clock = polaris10_get_xclk(hwmgr);
-+
-+	for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+		if (clock > data->range_table[i].trans_lower_frequency
-+		&& clock <= data->range_table[i].trans_upper_frequency) {
-+			sclk_setting->PllRange = i;
-+			break;
-+		}
-+	}
-+
-+	sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
-+	temp <<= 0x10;
-+	sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
-+
-+	pcc_target_percent = 10; /*  Hardcode 10% for now. */
-+	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
-+	sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+
-+	ss_target_percent = 2; /*  Hardcode 2% for now. */
-+	sclk_setting->SSc_En = 0;
-+	if (ss_target_percent) {
-+		sclk_setting->SSc_En = 1;
-+		ss_target_freq = clock - (clock * ss_target_percent / 100);
-+		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
-+		temp <<= 0x10;
-+		sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
-+		uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i;
-+	uint16_t vddci;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	*voltage = *mvdd = 0;
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (dep_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (dep_table->entries[i].clk >= clock) {
-+			*voltage |= (dep_table->entries[i].vddc *
-+					VOLTAGE_SCALE) << VDDC_SHIFT;
-+			if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else if (dep_table->entries[i].vddci)
-+				*voltage |= (dep_table->entries[i].vddci *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else {
-+				vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						(dep_table->entries[i].vddc -
-+								(uint16_t)data->vddc_vddci_delta));
-+				*voltage |= (vddci * VOLTAGE_SCALE) <<	VDDCI_SHIFT;
-+			}
-+
-+			if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
-+					VOLTAGE_SCALE;
-+			else if (dep_table->entries[i].mvdd)
-+				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
-+					VOLTAGE_SCALE;
-+
-+			*voltage |= 1 << PHASES_SHIFT;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+				VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	else if (dep_table->entries[i-1].vddci) {
-+		vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+				(dep_table->entries[i].vddc -
-+						(uint16_t)data->vddc_vddci_delta));
-+		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	}
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
-+	else if (dep_table->entries[i].mvdd)
-+		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-+
-+	return 0;
-+}
-+
-+sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
-+						{VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
-+						{VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
-+						{VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
-+						{VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
-+						{VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
-+						{VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
-+						{VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
-+
-+static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t i, ref_clk;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
-+	struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
-+
-+	ref_clk = polaris10_get_xclk(hwmgr);
-+
-+	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
-+		for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+			table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
-+			table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
-+			table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
-+
-+			table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
-+			table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
-+
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
-+		}
-+		return;
-+	}
-+
-+	for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+
-+		data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
-+		data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
-+
-+		table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
-+		table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
-+		table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
-+
-+		table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
-+		table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
-+
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
-+	}
-+}
-+
-+/**
-+* Populates single SMC SCLK structure using the provided engine clock
-+*
-+* @param    hwmgr      the address of the hardware manager
-+* @param    clock the engine clock to use to populate the structure
-+* @param    sclk        the SMC SCLK structure to be populated
-+*/
-+
-+static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, uint16_t sclk_al_threshold,
-+		struct SMU74_Discrete_GraphicsLevel *level)
-+{
-+	int result, i, temp;
-+	/* PP_Clocks minClocks; */
-+	uint32_t mvdd;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMU_SclkSetting curr_sclk_setting = { 0 };
-+
-+	result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
-+
-+	/* populate graphics levels */
-+	result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_sclk, clock,
-+			&level->MinVoltage, &mvdd);
-+
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find VDDC voltage value for "
-+			"VDDC engine clock dependency table",
-+			return result);
-+	level->ActivityLevel = sclk_al_threshold;
-+
-+	level->CcPwrDynRm = 0;
-+	level->CcPwrDynRm1 = 0;
-+	level->EnabledForActivity = 0;
-+	level->EnabledForThrottle = 1;
-+	level->UpHyst = 10;
-+	level->DownHyst = 0;
-+	level->VoltageDownHyst = 0;
-+	level->PowerThrottle = 0;
-+
-+	/*
-+	* TODO: get minimum clocks from dal configaration
-+	* PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
-+	*/
-+	/* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
-+
-+	/* get level->DeepSleepDivId
-+	if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+		level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
-+	*/
-+	PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
-+	for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
-+		temp = clock / (1UL << i);
-+
-+		if (temp >= 2500 || i == 0)
-+			break;
-+	}
-+
-+	level->DeepSleepDivId = i;
-+
-+	/* Default to slow, highest DPM level will be
-+	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-+	 */
-+	if (data->update_up_hyst)
-+		level->UpHyst = (uint8_t)data->up_hyst;
-+	if (data->update_down_hyst)
-+		level->DownHyst = (uint8_t)data->down_hyst;
-+
-+	level->SclkSetting = curr_sclk_setting;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
-+	return 0;
-+}
-+
-+/**
-+* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
-+*
-+* @param    hwmgr      the address of the hardware manager
-+*/
-+static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_dpm_table *dpm_table = &data->dpm_table;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
-+	int result = 0;
-+	uint32_t array = data->dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
-+			SMU74_MAX_LEVELS_GRAPHICS;
-+	struct SMU74_Discrete_GraphicsLevel *levels =
-+			data->smc_state_table.GraphicsLevel;
-+	uint32_t i, max_entry;
-+	uint8_t hightest_pcie_level_enabled = 0,
-+		lowest_pcie_level_enabled = 0,
-+		mid_pcie_level_enabled = 0,
-+		count = 0;
-+
-+	polaris10_get_sclk_range_table(hwmgr);
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+
-+		result = polaris10_populate_single_graphic_level(hwmgr,
-+				dpm_table->sclk_table.dpm_levels[i].value,
-+				(uint16_t)data->activity_target[i],
-+				&(data->smc_state_table.GraphicsLevel[i]));
-+		if (result)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			levels[i].DeepSleepDivId = 0;
-+	}
-+
-+	data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+	data->smc_state_table.GraphicsDpmLevelCount =
-+			(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
-+				"There must be 1 or more PCIE levels defined in PPTable.",
-+				return -EINVAL);
-+		max_entry = pcie_entry_cnt - 1;
-+		for (i = 0; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel =
-+					(uint8_t) ((i < max_entry) ? i : max_entry);
-+	} else {
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-+			hightest_pcie_level_enabled++;
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << lowest_pcie_level_enabled)) == 0))
-+			lowest_pcie_level_enabled++;
-+
-+		while ((count < hightest_pcie_level_enabled) &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
-+			count++;
-+
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-+				hightest_pcie_level_enabled ?
-+						(lowest_pcie_level_enabled + 1 + count) :
-+						hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to hightest_pcie_level_enabled */
-+		for (i = 2; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled */
-+		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled */
-+		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change */
-+	result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, data->sram_end);
-+
-+	return result;
-+}
-+
-+static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+	struct cgs_display_info info = {0, 0, NULL};
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (table_info->vdd_dep_on_mclk) {
-+		result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk, clock,
-+				&mem_level->MinVoltage, &mem_level->MinMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find MinVddc voltage value from memory "
-+				"VDDC voltage dependency table", return result);
-+	}
-+
-+	mem_level->MclkFrequency = clock;
-+	mem_level->StutterEnable = 0;
-+	mem_level->EnabledForThrottle = 1;
-+	mem_level->EnabledForActivity = 0;
-+	mem_level->UpHyst = 0;
-+	mem_level->DownHyst = 100;
-+	mem_level->VoltageDownHyst = 0;
-+	mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	mem_level->StutterEnable = false;
-+
-+	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	if ((data->mclk_stutter_mode_threshold) &&
-+		(clock <= data->mclk_stutter_mode_threshold) &&
-+		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
-+				STUTTER_ENABLE) & 0x1))
-+		mem_level->StutterEnable = true;
-+
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
-+	}
-+	return result;
-+}
-+
-+/**
-+* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
-+*
-+* @param    hwmgr      the address of the hardware manager
-+*/
-+static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t array = data->dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
-+	uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
-+			SMU74_MAX_LEVELS_MEMORY;
-+	struct SMU74_Discrete_MemoryLevel *levels =
-+			data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+				"can not populate memory level as memory clock is zero",
-+				return -EINVAL);
-+		result = polaris10_populate_single_memory_level(hwmgr,
-+				dpm_table->mclk_table.dpm_levels[i].value,
-+				&levels[i]);
-+		if (result)
-+			return result;
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	levels[0].EnabledForActivity = 1;
-+
-+	/* in order to prevent MC activity from stutter mode to push DPM up.
-+	 * the UVD change complements this by putting the MCLK in
-+	 * a higher state by default such that we are not effected by
-+	 * up threshold or and MCLK DPM latency.
-+	 */
-+	levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
-+	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-+
-+	data->smc_state_table.MemoryDpmLevelCount =
-+			(uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high */
-+	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change */
-+	result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, data->sram_end);
-+
-+	return result;
-+}
-+
-+/**
-+* Populates the SMC MVDD structure using the provided memory clock.
-+*
-+* @param    hwmgr      the address of the hardware manager
-+* @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
-+* @param    voltage     the SMC VOLTAGE structure to be populated
-+*/
-+int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
-+		uint32_t mclk, SMIO_Pattern *smio_pat)
-+{
-+	const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
-+				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
-+				"MVDD Voltage is outside the supported range.",
-+				return -EINVAL);
-+	} else
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint32_t sclk_frequency;
-+	const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMIO_Pattern vol_level;
-+	uint32_t mvdd;
-+	uint16_t us_mvdd;
-+
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0,
-+		 * already converted to SMC_UL */
-+		sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
-+		result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_sclk,
-+				table->ACPILevel.SclkFrequency,
-+				&table->ACPILevel.MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDC voltage value "
-+				"in Clock Dependency Table", );
-+	} else {
-+		sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
-+		table->ACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
-+	PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	table->ACPILevel.DeepSleepDivId = 0;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->dpm_table.mclk_table.dpm_levels[0].value;
-+		result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk,
-+				table->MemoryACPILevel.MclkFrequency,
-+				&table->MemoryACPILevel.MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDCI voltage value "
-+				"in Clock Dependency Table",
-+				);
-+	} else {
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->vbios_boot_state.mclk_bootup_value;
-+		table->MemoryACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	us_mvdd = 0;
-+	if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
-+			(data->mclk_dpm_key_disabled))
-+		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	else {
-+		if (!polaris10_populate_mvdd_value(hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[0].value,
-+				&vol_level))
-+			us_mvdd = vol_level.Voltage;
-+	}
-+
-+	if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
-+		table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	table->MemoryACPILevel.StutterEnable = false;
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	table->MemoryACPILevel.ActivityLevel =
-+			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-+
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	table->VceLevelCount = (uint8_t)(mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage |=
-+				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->VceLevel[count].MinVoltage |=
-+				((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/*retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t)(mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
-+		int32_t eng_clock, int32_t mem_clock,
-+		SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
-+{
-+	uint32_t dram_timing;
-+	uint32_t dram_timing2;
-+	uint32_t burst_time;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+			eng_clock, mem_clock);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
-+	arb_regs->McArbBurstTime   = (uint8_t)burst_time;
-+
-+	return 0;
-+}
-+
-+static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
-+	uint32_t i, j;
-+	int result = 0;
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = polaris10_populate_memory_timing_parameters(hwmgr,
-+					data->dpm_table.sclk_table.dpm_levels[i].value,
-+					data->dpm_table.mclk_table.dpm_levels[j].value,
-+					&arb_regs.entries[i][j]);
-+			if (result == 0)
-+				result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
-+			if (result != 0)
-+				return result;
-+		}
-+	}
-+
-+	result = polaris10_copy_bytes_to_smc(
-+			hwmgr->smumgr,
-+			data->arb_table_start,
-+			(uint8_t *)&arb_regs,
-+			sizeof(SMU74_Discrete_MCArbDramTimingTable),
-+			data->sram_end);
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	table->UvdLevelCount = (uint8_t)(mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
-+
-+	}
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table */
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(table->GraphicsBootLevel));
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+			data->vbios_boot_state.mclk_bootup_value,
-+			(uint32_t *)&(table->MemoryBootLevel));
-+
-+	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
-+			VOLTAGE_SCALE;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return 0;
-+}
-+
-+
-+static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_sclk->entries[level].clk >=
-+				data->vbios_boot_state.sclk_bootup_value) {
-+			data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
-+				data->vbios_boot_state.mclk_bootup_value) {
-+			data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-+			volt_with_cks, value;
-+	uint16_t clock_freq_u16;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-+			volt_offset = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+
-+	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-+
-+	/* Read SMU_Eefuse to read and calculate RO and determine
-+	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
-+	 */
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (146 * 4));
-+	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (148 * 4));
-+	efuse &= 0xFF000000;
-+	efuse = efuse >> 24;
-+	efuse2 &= 0xF;
-+
-+	if (efuse2 == 1)
-+		ro = (2300 - 1350) * efuse / 255 + 1350;
-+	else
-+		ro = (2500 - 1000) * efuse / 255 + 1000;
-+
-+	if (ro >= 1660)
-+		type = 0;
-+	else
-+		type = 1;
-+
-+	/* Populate Stretch amount */
-+	data->smc_state_table.ClockStretcherAmount = stretch_amount;
-+
-+	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
-+	for (i = 0; i < sclk_table->count; i++) {
-+		data->smc_state_table.Sclk_CKS_masterEn0_7 |=
-+				sclk_table->entries[i].cks_enable << i;
-+		volt_without_cks = (uint32_t)((14041 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-+			(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-+		volt_with_cks = (uint32_t)((13946 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-+			(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
-+		if (volt_without_cks >= volt_with_cks)
-+			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
-+					sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
-+		data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
-+	}
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			STRETCH_ENABLE, 0x0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x1);
-+	/* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x0);
-+
-+	/* Populate CKS Lookup Table */
-+	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
-+		stretch_amount2 = 0;
-+	else if (stretch_amount == 3 || stretch_amount == 4)
-+		stretch_amount2 = 1;
-+	else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+		PP_ASSERT_WITH_CODE(false,
-+				"Stretch Amount in PPTable not supported\n",
-+				return -EINVAL);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL);
-+	value &= 0xFFC2FF87;
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-+			polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-+			polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
-+	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
-+			GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
-+	if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
-+	&& polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
-+		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-+		value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-+		/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-+		value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-+		/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-+		value |= (polaris10_clock_stretch_amount_conversion
-+				[polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
-+				 [stretch_amount]) << 3;
-+	}
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
-+	CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-+			polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-+	data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-+			(polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL, value);
-+
-+	/* Populate DDT Lookup Table */
-+	for (i = 0; i < 4; i++) {
-+		/* Assign the minimum and maximum VID stored
-+		 * in the last row of Clock Stretcher Voltage Table.
-+		 */
-+		data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
-+				(uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
-+		data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
-+				(uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
-+		/* Loop through each SCLK and check the frequency
-+		 * to see if it lies within the frequency for clock stretcher.
-+		 */
-+		for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
-+			cks_setting = 0;
-+			clock_freq = PP_SMC_TO_HOST_UL(
-+					data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
-+			/* Check the allowed frequency against the sclk level[j].
-+			 *  Sclk's endianness has already been converted,
-+			 *  and it's in 10Khz unit,
-+			 *  as opposed to Data table, which is in Mhz unit.
-+			 */
-+			if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
-+				cks_setting |= 0x2;
-+				if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
-+					cks_setting |= 0x1;
-+			}
-+			data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
-+							|= cks_setting << (j * 2);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_US(
-+			data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
-+	value &= 0xFFFFFFFE;
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-+
-+	return 0;
-+}
-+
-+/**
-+* Populates the SMC VRConfig field in DPM table.
-+*
-+* @param    hwmgr   the address of the hardware manager
-+* @param    table   the SMC DPM table structure to be populated
-+* @return   always 0
-+*/
-+static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint16_t config;
-+
-+	config = VR_MERGED_WITH_VDDC;
-+	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-+
-+	/* Set Vddc Voltage Controller */
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= config;
-+	} else {
-+		PP_ASSERT_WITH_CODE(false,
-+				"VDDC should be on SVI2 control in merged mode!",
-+				);
-+	}
-+	/* Set Vddci Voltage Controller */
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	}
-+	/* Set Mvdd Voltage Controller */
-+	if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		config = VR_SVI2_PLANE_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		config = VR_SMIO_PATTERN_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Initializes the SMC table and uploads it
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
-+	const struct polaris10_ulv_parm *ulv = &(data->ulv);
-+	uint8_t i;
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+
-+	result = polaris10_setup_default_dpm_tables(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to setup default DPM tables!", return result);
-+
-+	if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
-+		polaris10_populate_smc_voltage_tables(hwmgr, table);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
-+		result = polaris10_populate_ulv_state(hwmgr, table);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to initialize ULV state!", return result);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
-+	}
-+
-+	result = polaris10_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Link Level!", return result);
-+
-+	result = polaris10_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Graphics Level!", return result);
-+
-+	result = polaris10_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Memory Level!", return result);
-+
-+	result = polaris10_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACPI Level!", return result);
-+
-+	result = polaris10_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize VCE Level!", return result);
-+
-+	result = polaris10_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize SAMU Level!", return result);
-+
-+	/* Since only the initial state is completely set up at this point
-+	 * (the other states are just copies of the boot state) we only
-+	 * need to populate the  ARB settings for the initial state.
-+	 */
-+	result = polaris10_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to Write ARB settings for the initial state.", return result);
-+
-+	result = polaris10_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize UVD Level!", return result);
-+
-+	result = polaris10_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot Level!", return result);
-+
-+	result = polaris10_populate_smc_initailial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot State!", return result);
-+
-+	result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate BAPM Parameters!", return result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = polaris10_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to populate Clock Stretcher Data Table!",
-+				return result);
-+	}
-+
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+			table_info->cac_dtp_table->usTargetOperatingTemp *
-+			POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow  =
-+			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+			POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable = 1;
-+	table->MemoryInterval = 1;
-+	table->VoltageResponseTime = 0;
-+	table->PhaseResponseTime = 0;
-+	table->MemoryThermThrottleEnable = 1;
-+	table->PCIeBootLinkLevel = 0;
-+	table->PCIeGenInterval = 1;
-+
-+	result = polaris10_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate VRConfig setting!", return result);
-+
-+	table->ThermGpio = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
-+		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+	} else {
-+		table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
-+			&gpio_pin)) {
-+		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	/* Thermal Output GPIO */
-+	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
-+			&gpio_pin)) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+
-+		/* For porlarity read GPIOPAD_A with assigned Gpio pin
-+		 * since VBIOS will program this register to set 'inactive state',
-+		 * driver can then determine 'active state' from this and
-+		 * program SMU with correct polarity
-+		 */
-+		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
-+					& (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
-+		&& phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+	} else {
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	/* Populate BIF_SCLK levels into SMC DPM table */
-+	for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
-+		PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
-+
-+		if (i == 0)
-+			table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
-+		else
-+			table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
-+	}
-+
-+	for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
-+			data->dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, SystemFlags),
-+			(uint8_t *)&(table->SystemFlags),
-+			sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
-+			data->sram_end);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload dpm data to SMC memory!", return result);
-+
-+	return 0;
-+}
-+
-+/**
-+* Initialize the ARB DRAM timing table's index field.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/* This is a read-modify-write on the first byte of the ARB table.
-+	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
-+	 * is the field 'current'.
-+	 * This solution is ugly, but we never write the whole table only
-+	 * individual fields in it.
-+	 * In reality this field should not be in that structure
-+	 * but in a soft register.
-+	 */
-+	result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start, &tmp, data->sram_end);
-+
-+	if (result)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return polaris10_write_smc_sram_dword(hwmgr->smumgr,
-+			data->arb_table_start, tmp, data->sram_end);
-+}
-+
-+static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot))
-+		return smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_EnableVRHotGPIOInterrupt);
-+
-+	return 0;
-+}
-+
-+static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-+			SCLK_PWRMGT_OFF, 0);
-+	return 0;
-+}
-+
-+static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_ulv_parm *ulv = &(data->ulv);
-+
-+	if (ulv->ulv_supported)
-+		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
-+
-+	return 0;
-+}
-+
-+static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
-+{
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep)) {
-+		if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to enable Master Deep Sleep switch failed!",
-+					return -1);
-+	} else {
-+		if (smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to disable Master Deep Sleep switch failed!",
-+					return -1);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	/* enable SCLK dpm */
-+	if (!data->sclk_dpm_key_disabled)
-+		PP_ASSERT_WITH_CODE(
-+		(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
-+		"Failed to enable SCLK DPM during DPM Start Function!",
-+		return -1);
-+
-+	/* enable MCLK dpm */
-+	if (0 == data->mclk_dpm_key_disabled) {
-+
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_MCLKDPM_Enable)),
-+				"Failed to enable MCLK DPM during DPM Start Function!",
-+				return -1);
-+
-+
-+		PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
-+		udelay(10);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	/*enable general power management */
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+			GLOBAL_PWRMGT_EN, 1);
-+
-+	/* enable sclk deep sleep */
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
-+			DYNAMIC_PM_EN, 1);
-+
-+	/* prepare for PCIE DPM */
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			data->soft_regs_start + offsetof(SMU74_SoftRegisters,
-+					VoltageChangeTimeout), 0x1000);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
-+			SWRST_COMMAND_1, RESETLC, 0x0);
-+/*
-+	PP_ASSERT_WITH_CODE(
-+			(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_Voltage_Cntl_Enable)),
-+			"Failed to enable voltage DPM during DPM Start Function!",
-+			return -1);
-+*/
-+
-+	if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
-+		printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
-+		return -1;
-+	}
-+
-+	/* enable PCIE dpm */
-+	if (0 == data->pcie_dpm_key_disabled) {
-+		PP_ASSERT_WITH_CODE(
-+				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_Enable)),
-+				"Failed to enable pcie DPM during DPM Start Function!",
-+				return -1);
-+	}
-+
-+	PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+					PPSMC_MSG_EnableACDCGPIOInterrupt)),
-+					"Failed to enable AC DC GPIO Interrupt!",
-+			);
-+
-+	return 0;
-+}
-+
-+static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
-+{
-+	bool protection;
-+	enum DPM_EVENT_SRC src;
-+
-+	switch (sources) {
-+	default:
-+		printk(KERN_ERR "Unknown throttling event sources.");
-+		/* fall through */
-+	case 0:
-+		protection = false;
-+		/* src is unused */
-+		break;
-+	case (1 << PHM_AutoThrottleSource_Thermal):
-+		protection = true;
-+		src = DPM_EVENT_SRC_DIGITAL;
-+		break;
-+	case (1 << PHM_AutoThrottleSource_External):
-+		protection = true;
-+		src = DPM_EVENT_SRC_EXTERNAL;
-+		break;
-+	case (1 << PHM_AutoThrottleSource_External) |
-+			(1 << PHM_AutoThrottleSource_Thermal):
-+		protection = true;
-+		src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
-+		break;
-+	}
-+	/* Order matters - don't enable thermal protection for the wrong source. */
-+	if (protection) {
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
-+				DPM_EVENT_SRC, src);
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+				THERMAL_PROTECTION_DIS,
-+				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_ThermalController));
-+	} else
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-+				THERMAL_PROTECTION_DIS, 1);
-+}
-+
-+static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
-+		PHM_AutoThrottleSource source)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (!(data->active_auto_throttle_sources & (1 << source))) {
-+		data->active_auto_throttle_sources |= 1 << source;
-+		polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
-+	}
-+	return 0;
-+}
-+
-+static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
-+{
-+	return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
-+}
-+
-+int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	data->pcie_performance_request = true;
-+
-+	return 0;
-+}
-+
-+int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+	tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"DPM is already running right now, no need to enable DPM!",
-+			return 0);
-+
-+	if (polaris10_voltage_control(hwmgr)) {
-+		tmp_result = polaris10_enable_voltage_control(hwmgr);
-+		PP_ASSERT_WITH_CODE(tmp_result == 0,
-+				"Failed to enable voltage control!",
-+				result = tmp_result);
-+
-+		tmp_result = polaris10_construct_voltage_tables(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to contruct voltage tables!",
-+				result = tmp_result);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport))
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalController))
-+		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
-+
-+	tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program static screen threshold parameters!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_enable_display_gap(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable display gap!", result = tmp_result);
-+
-+	tmp_result = polaris10_program_voting_clients(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program voting clients!", result = tmp_result);
-+
-+	tmp_result = polaris10_process_firmware_header(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to process firmware header!", result = tmp_result);
-+
-+	tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize switch from ArbF0 to F1!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_init_smc_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize SMC table!", result = tmp_result);
-+
-+	tmp_result = polaris10_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to initialize ARB table index!", result = tmp_result);
-+
-+	tmp_result = polaris10_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to populate PM fuses!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_sclk_control(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable SCLK control!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable voltage control!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_ulv(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable ULV!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable deep sleep master switch!", result = tmp_result);
-+
-+	tmp_result = polaris10_start_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to start DPM!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_smc_cac(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable SMC CAC!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_power_containment(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable power containment!", result = tmp_result);
-+
-+	tmp_result = polaris10_power_control_set_level(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to power control set level!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable thermal auto throttle!", result = tmp_result);
-+
-+	tmp_result = polaris10_pcie_performance_request(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable thermal auto throttle!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+
-+	return 0;
-+}
-+
-+int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
-+{
-+
-+	return 0;
-+}
-+
-+int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
-+{
-+	return phm_hwmgr_backend_fini(hwmgr);
-+}
-+
-+int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep);
-+
-+	if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EnableMVDDControl);
-+
-+	if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ControlVDDCI);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			 PHM_PlatformCaps_TablelessHardwareInterface);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableSMU7ThermalManagement);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DynamicPowerManagement);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TablelessHardwareInterface);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_SMC);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_NonABMSupportInPPLib);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_DynamicUVDState);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_SclkThrottleLowNotification);
-+
-+	/* power tune caps Assume disabled */
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_PowerContainment);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+							PHM_PlatformCaps_CAC);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_SQRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_DBRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_TDRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_TCPRamping);
-+
-+	return 0;
-+}
-+
-+static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	polaris10_initialize_power_tune_defaults(hwmgr);
-+
-+	data->pcie_gen_performance.max = PP_PCIEGen1;
-+	data->pcie_gen_performance.min = PP_PCIEGen3;
-+	data->pcie_gen_power_saving.max = PP_PCIEGen1;
-+	data->pcie_gen_power_saving.min = PP_PCIEGen3;
-+	data->pcie_lane_performance.max = 0;
-+	data->pcie_lane_performance.min = 16;
-+	data->pcie_lane_power_saving.max = 0;
-+	data->pcie_lane_power_saving.min = 16;
-+}
-+
-+/**
-+* Get Leakage VDDC based on leakage ID.
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always 0
-+*/
-+static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint16_t vv_id;
-+	uint16_t vddc = 0;
-+	uint16_t i, j;
-+	uint32_t sclk = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	int result;
-+
-+	for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
-+		vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-+		if (!phm_get_sclk_for_voltage_evv(hwmgr,
-+				table_info->vddc_lookup_table, vv_id, &sclk)) {
-+			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_ClockStretcher)) {
-+				for (j = 1; j < sclk_table->count; j++) {
-+					if (sclk_table->entries[j].clk == sclk &&
-+							sclk_table->entries[j].cks_enable == 0) {
-+						sclk += 5000;
-+						break;
-+					}
-+				}
-+			}
-+
-+
-+			PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
-+							VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
-+						"Error retrieving EVV voltage value!",
-+						continue);
-+
-+
-+			/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
-+			PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
-+					"Invalid VDDC value", result = -EINVAL;);
-+
-+			/* the voltage should not be zero nor equal to leakage ID */
-+			if (vddc != 0 && vddc != vv_id) {
-+				data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
-+				data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
-+				data->vddc_leakage.count++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Change virtual leakage voltage to actual value.
-+ *
-+ * @param     hwmgr  the address of the powerplay hardware manager.
-+ * @param     pointer to changing voltage
-+ * @param     pointer to leakage table
-+ */
-+static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
-+		uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
-+{
-+	uint32_t index;
-+
-+	/* search for leakage voltage ID 0xff01 ~ 0xff08 */
-+	for (index = 0; index < leakage_table->count; index++) {
-+		/* if this voltage matches a leakage voltage ID */
-+		/* patch with actual leakage voltage */
-+		if (leakage_table->leakage_id[index] == *voltage) {
-+			*voltage = leakage_table->actual_voltage[index];
-+			break;
-+		}
-+	}
-+
-+	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
-+		printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
-+}
-+
-+/**
-+* Patch voltage lookup table by EVV leakages.
-+*
-+* @param     hwmgr  the address of the powerplay hardware manager.
-+* @param     pointer to voltage lookup table
-+* @param     pointer to leakage table
-+* @return     always 0
-+*/
-+static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
-+		phm_ppt_v1_voltage_lookup_table *lookup_table,
-+		struct polaris10_leakage_voltage *leakage_table)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < lookup_table->count; i++)
-+		polaris10_patch_with_vdd_leakage(hwmgr,
-+				&lookup_table->entries[i].us_vdd, leakage_table);
-+
-+	return 0;
-+}
-+
-+static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
-+		struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
-+		uint16_t *vddc)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
-+	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
-+			table_info->max_clock_voltage_on_dc.vddc;
-+	return 0;
-+}
-+
-+static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
-+		struct pp_hwmgr *hwmgr)
-+{
-+	uint8_t entryId;
-+	uint8_t voltageId;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	for (entryId = 0; entryId < sclk_table->count; ++entryId) {
-+		voltageId = sclk_table->entries[entryId].vddInd;
-+		sclk_table->entries[entryId].vddc =
-+				table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mclk_table->count; ++entryId) {
-+		voltageId = mclk_table->entries[entryId].vddInd;
-+		mclk_table->entries[entryId].vddc =
-+			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	for (entryId = 0; entryId < mm_table->count; ++entryId) {
-+		voltageId = mm_table->entries[entryId].vddcInd;
-+		mm_table->entries[entryId].vddc =
-+			table_info->vddc_lookup_table->entries[voltageId].us_vdd;
-+	}
-+
-+	return 0;
-+
-+}
-+
-+static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	/* Need to determine if we need calculated voltage. */
-+	return 0;
-+}
-+
-+static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
-+{
-+	/* Need to determine if we need calculated voltage from mm table. */
-+	return 0;
-+}
-+
-+static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
-+{
-+	uint32_t table_size, i, j;
-+	struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
-+	table_size = lookup_table->count;
-+
-+	PP_ASSERT_WITH_CODE(0 != lookup_table->count,
-+		"Lookup table is empty", return -EINVAL);
-+
-+	/* Sorting voltages */
-+	for (i = 0; i < table_size - 1; i++) {
-+		for (j = i + 1; j > 0; j--) {
-+			if (lookup_table->entries[j].us_vdd <
-+					lookup_table->entries[j - 1].us_vdd) {
-+				tmp_voltage_lookup_record = lookup_table->entries[j - 1];
-+				lookup_table->entries[j - 1] = lookup_table->entries[j];
-+				lookup_table->entries[j] = tmp_voltage_lookup_record;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
-+{
-+	int result = 0;
-+	int tmp_result;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
-+			table_info->vddc_lookup_table, &(data->vddc_leakage));
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
-+			&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
-+	if (tmp_result)
-+		result = tmp_result;
-+
-+	return result;
-+}
-+
-+static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
-+						table_info->vdd_dep_on_sclk;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
-+						table_info->vdd_dep_on_mclk;
-+
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-+		"VDD dependency on SCLK table is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-+		"VDD dependency on SCLK table has to have is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-+		"VDD dependency on MCLK table is missing. 	\
-+		This table is mandatory", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
-+		"VDD dependency on MCLK table has to have is missing.	 \
-+		This table is mandatory", return -EINVAL);
-+
-+	table_info->max_clock_voltage_on_ac.sclk =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
-+	table_info->max_clock_voltage_on_ac.mclk =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
-+	table_info->max_clock_voltage_on_ac.vddc =
-+		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
-+	table_info->max_clock_voltage_on_ac.vddci =
-+		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
-+
-+	return 0;
-+}
-+
-+int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
-+	uint32_t temp_reg;
-+	int result;
-+
-+	data->dll_default_on = false;
-+	data->sram_end = SMC_RAM_END;
-+
-+	data->disable_dpm_mask = 0xFF;
-+	data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
-+	data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
-+	data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+	data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
-+
-+	data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
-+	data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
-+	data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
-+	data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
-+	data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
-+	data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
-+	data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
-+	data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
-+
-+	data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
-+
-+	data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
-+
-+	/* need to set voltage control types before EVV patching */
-+	data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
-+	data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
-+	data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
-+
-+	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
-+		data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_DynamicPatchPowerState);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EnableMVDDControl)) {
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
-+			data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
-+		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
-+			data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ControlVDDCI)) {
-+		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
-+			data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
-+		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
-+			data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
-+	}
-+
-+	polaris10_set_features_platform_caps(hwmgr);
-+
-+	polaris10_init_dpm_defaults(hwmgr);
-+
-+	/* Get leakage voltage based on leakage ID. */
-+	result = polaris10_get_evv_voltages(hwmgr);
-+
-+	if (result) {
-+		printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
-+		return -1;
-+	}
-+
-+	polaris10_complete_dependency_tables(hwmgr);
-+	polaris10_set_private_data_based_on_pptable(hwmgr);
-+
-+	/* Initalize Dynamic State Adjustment Rule Settings */
-+	result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
-+
-+	if (0 == result) {
-+		struct cgs_system_info sys_info = {0};
-+
-+		data->is_tlu_enabled = 0;
-+
-+		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
-+							POLARIS10_MAX_HARDWARE_POWERLEVELS;
-+		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
-+		hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
-+		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
-+/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
-+		hwmgr->platform_descriptor.clockStep.engineClock = 500;
-+		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
-+
-+		if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
-+			temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
-+			switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
-+			case 0:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
-+				break;
-+			case 1:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
-+				break;
-+			case 2:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
-+				break;
-+			case 3:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
-+				break;
-+			case 4:
-+				temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
-+				break;
-+			default:
-+				PP_ASSERT_WITH_CODE(0,
-+				"Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
-+				);
-+				break;
-+			}
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
-+		}
-+
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_gen_cap = 0x30007;
-+		else
-+			data->pcie_gen_cap = (uint32_t)sys_info.value;
-+		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-+			data->pcie_spc_cap = 20;
-+		sys_info.size = sizeof(struct cgs_system_info);
-+		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
-+		result = cgs_query_system_info(hwmgr->device, &sys_info);
-+		if (result)
-+			data->pcie_lane_cap = 0x2f0000;
-+		else
-+			data->pcie_lane_cap = (uint32_t)sys_info.value;
-+	} else {
-+		/* Ignore return value in here, we are cleaning up a mess. */
-+		polaris10_hwmgr_backend_fini(hwmgr);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t level, tmp;
-+
-+	if (!data->pcie_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_PCIeDPM_ForceLevel, level);
-+		}
-+	}
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+						(1 << level));
-+		}
-+	}
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			level = 0;
-+			tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
-+			while (tmp >>= 1)
-+				level++;
-+
-+			if (level)
-+				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+						PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+						(1 << level));
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	phm_apply_dal_min_voltage_request(hwmgr);
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+	}
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+					data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (!polaris10_is_dpm_running(hwmgr))
-+		return -EINVAL;
-+
-+	if (!data->pcie_dpm_key_disabled) {
-+		smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_PCIeDPM_UnForceLevel);
-+	}
-+
-+	return polaris10_upload_dpm_level_enable_mask(hwmgr);
-+}
-+
-+static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data =
-+			(struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t level;
-+
-+	if (!data->sclk_dpm_key_disabled)
-+		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-+			level = phm_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+							    (1 << level));
-+
-+	}
-+/* uvd is enabled, can't set mclk low right now
-+	if (!data->mclk_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-+			level = phm_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+							    (1 << level));
-+		}
-+	}
-+*/
-+	if (!data->pcie_dpm_key_disabled) {
-+		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-+			level = phm_get_lowest_enabled_level(hwmgr,
-+							      data->dpm_level_enable_mask.pcie_dpm_enable_mask);
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+							    PPSMC_MSG_PCIeDPM_ForceLevel,
-+							    (level));
-+		}
-+	}
-+
-+	return 0;
-+
-+}
-+static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
-+				enum amd_dpm_forced_level level)
-+{
-+	int ret = 0;
-+
-+	switch (level) {
-+	case AMD_DPM_FORCED_LEVEL_HIGH:
-+		ret = polaris10_force_dpm_highest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_LOW:
-+		ret = polaris10_force_dpm_lowest(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	case AMD_DPM_FORCED_LEVEL_AUTO:
-+		ret = polaris10_unforce_dpm_levels(hwmgr);
-+		if (ret)
-+			return ret;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	hwmgr->dpm_level = level;
-+
-+	return ret;
-+}
-+
-+static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
-+{
-+	return sizeof(struct polaris10_power_state);
-+}
-+
-+
-+static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-+				struct pp_power_state *request_ps,
-+			const struct pp_power_state *current_ps)
-+{
-+
-+	struct polaris10_power_state *polaris10_ps =
-+				cast_phw_polaris10_power_state(&request_ps->hardware);
-+	uint32_t sclk;
-+	uint32_t mclk;
-+	struct PP_Clocks minimum_clocks = {0};
-+	bool disable_mclk_switching;
-+	bool disable_mclk_switching_for_frame_lock;
-+	struct cgs_display_info info = {0};
-+	const struct phm_clock_and_voltage_limits *max_limits;
-+	uint32_t i;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int32_t count;
-+	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
-+
-+	data->battery_state = (PP_StateUILabel_Battery ==
-+			request_ps->classification.ui_label);
-+
-+	PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
-+				 "VI should always have 2 performance levels",
-+				);
-+
-+	max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
-+			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
-+			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
-+
-+	/* Cap clock DPM tables at DC MAX if it is in DC. */
-+	if (PP_PowerSource_DC == hwmgr->power_source) {
-+		for (i = 0; i < polaris10_ps->performance_level_count; i++) {
-+			if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
-+				polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
-+			if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
-+				polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
-+		}
-+	}
-+
-+	polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
-+	polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-+
-+	/* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState)) {
-+		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
-+		stable_pstate_sclk = (max_limits->sclk * 75) / 100;
-+
-+		for (count = table_info->vdd_dep_on_sclk->count - 1;
-+				count >= 0; count--) {
-+			if (stable_pstate_sclk >=
-+					table_info->vdd_dep_on_sclk->entries[count].clk) {
-+				stable_pstate_sclk =
-+						table_info->vdd_dep_on_sclk->entries[count].clk;
-+				break;
-+			}
-+		}
-+
-+		if (count < 0)
-+			stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
-+
-+		stable_pstate_mclk = max_limits->mclk;
-+
-+		minimum_clocks.engineClock = stable_pstate_sclk;
-+		minimum_clocks.memoryClock = stable_pstate_mclk;
-+	}
-+
-+	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
-+		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
-+
-+	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
-+		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
-+
-+	polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
-+
-+	if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
-+				hwmgr->platform_descriptor.overdriveLimit.engineClock),
-+				"Overdrive sclk exceeds limit",
-+				hwmgr->gfx_arbiter.sclk_over_drive =
-+						hwmgr->platform_descriptor.overdriveLimit.engineClock);
-+
-+		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
-+			polaris10_ps->performance_levels[1].engine_clock =
-+					hwmgr->gfx_arbiter.sclk_over_drive;
-+	}
-+
-+	if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
-+		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
-+				hwmgr->platform_descriptor.overdriveLimit.memoryClock),
-+				"Overdrive mclk exceeds limit",
-+				hwmgr->gfx_arbiter.mclk_over_drive =
-+						hwmgr->platform_descriptor.overdriveLimit.memoryClock);
-+
-+		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
-+			polaris10_ps->performance_levels[1].memory_clock =
-+					hwmgr->gfx_arbiter.mclk_over_drive;
-+	}
-+
-+	disable_mclk_switching_for_frame_lock = phm_cap_enabled(
-+				    hwmgr->platform_descriptor.platformCaps,
-+				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
-+
-+	disable_mclk_switching = (1 < info.display_count) ||
-+				    disable_mclk_switching_for_frame_lock;
-+
-+	sclk = polaris10_ps->performance_levels[0].engine_clock;
-+	mclk = polaris10_ps->performance_levels[0].memory_clock;
-+
-+	if (disable_mclk_switching)
-+		mclk = polaris10_ps->performance_levels
-+		[polaris10_ps->performance_level_count - 1].memory_clock;
-+
-+	if (sclk < minimum_clocks.engineClock)
-+		sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
-+				max_limits->sclk : minimum_clocks.engineClock;
-+
-+	if (mclk < minimum_clocks.memoryClock)
-+		mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
-+				max_limits->mclk : minimum_clocks.memoryClock;
-+
-+	polaris10_ps->performance_levels[0].engine_clock = sclk;
-+	polaris10_ps->performance_levels[0].memory_clock = mclk;
-+
-+	polaris10_ps->performance_levels[1].engine_clock =
-+		(polaris10_ps->performance_levels[1].engine_clock >=
-+				polaris10_ps->performance_levels[0].engine_clock) ?
-+						polaris10_ps->performance_levels[1].engine_clock :
-+						polaris10_ps->performance_levels[0].engine_clock;
-+
-+	if (disable_mclk_switching) {
-+		if (mclk < polaris10_ps->performance_levels[1].memory_clock)
-+			mclk = polaris10_ps->performance_levels[1].memory_clock;
-+
-+		polaris10_ps->performance_levels[0].memory_clock = mclk;
-+		polaris10_ps->performance_levels[1].memory_clock = mclk;
-+	} else {
-+		if (polaris10_ps->performance_levels[1].memory_clock <
-+				polaris10_ps->performance_levels[0].memory_clock)
-+			polaris10_ps->performance_levels[1].memory_clock =
-+					polaris10_ps->performance_levels[0].memory_clock;
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState)) {
-+		for (i = 0; i < polaris10_ps->performance_level_count; i++) {
-+			polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
-+			polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
-+			polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
-+			polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
-+		}
-+	}
-+	return 0;
-+}
-+
-+
-+static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct polaris10_power_state  *polaris10_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
-+
-+	if (low)
-+		return polaris10_ps->performance_levels[0].memory_clock;
-+	else
-+		return polaris10_ps->performance_levels
-+				[polaris10_ps->performance_level_count-1].memory_clock;
-+}
-+
-+static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+{
-+	struct pp_power_state  *ps;
-+	struct polaris10_power_state  *polaris10_ps;
-+
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	ps = hwmgr->request_ps;
-+
-+	if (ps == NULL)
-+		return -EINVAL;
-+
-+	polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
-+
-+	if (low)
-+		return polaris10_ps->performance_levels[0].engine_clock;
-+	else
-+		return polaris10_ps->performance_levels
-+				[polaris10_ps->performance_level_count-1].engine_clock;
-+}
-+
-+static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
-+					struct pp_hw_power_state *hw_ps)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
-+	ATOM_FIRMWARE_INFO_V2_2 *fw_info;
-+	uint16_t size;
-+	uint8_t frev, crev;
-+	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-+
-+	/* First retrieve the Boot clocks and VDDC from the firmware info table.
-+	 * We assume here that fw_info is unchanged if this call fails.
-+	 */
-+	fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
-+			hwmgr->device, index,
-+			&size, &frev, &crev);
-+	if (!fw_info)
-+		/* During a test, there is no firmware info table. */
-+		return 0;
-+
-+	/* Patch the state. */
-+	data->vbios_boot_state.sclk_bootup_value =
-+			le32_to_cpu(fw_info->ulDefaultEngineClock);
-+	data->vbios_boot_state.mclk_bootup_value =
-+			le32_to_cpu(fw_info->ulDefaultMemoryClock);
-+	data->vbios_boot_state.mvdd_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
-+	data->vbios_boot_state.vddc_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpVDDCVoltage);
-+	data->vbios_boot_state.vddci_bootup_value =
-+			le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
-+	data->vbios_boot_state.pcie_gen_bootup_value =
-+			phm_get_current_pcie_speed(hwmgr);
-+
-+	data->vbios_boot_state.pcie_lane_bootup_value =
-+			(uint16_t)phm_get_current_pcie_lane_number(hwmgr);
-+
-+	/* set boot power state */
-+	ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
-+	ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
-+	ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
-+	ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
-+
-+	return 0;
-+}
-+
-+static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
-+		void *state, struct pp_power_state *power_state,
-+		void *pp_table, uint32_t classification_flag)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_power_state  *polaris10_power_state =
-+			(struct polaris10_power_state *)(&(power_state->hardware));
-+	struct polaris10_performance_level *performance_level;
-+	ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
-+	ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
-+			(ATOM_Tonga_POWERPLAYTABLE *)pp_table;
-+	ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
-+			(ATOM_Tonga_SCLK_Dependency_Table *)
-+			(((unsigned long)powerplay_table) +
-+				le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
-+	ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
-+			(ATOM_Tonga_MCLK_Dependency_Table *)
-+			(((unsigned long)powerplay_table) +
-+				le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
-+
-+	/* The following fields are not initialized here: id orderedList allStatesList */
-+	power_state->classification.ui_label =
-+			(le16_to_cpu(state_entry->usClassification) &
-+			ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
-+			ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
-+	power_state->classification.flags = classification_flag;
-+	/* NOTE: There is a classification2 flag in BIOS that is not being used right now */
-+
-+	power_state->classification.temporary_state = false;
-+	power_state->classification.to_be_deleted = false;
-+
-+	power_state->validation.disallowOnDC =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
-+					ATOM_Tonga_DISALLOW_ON_DC));
-+
-+	power_state->pcie.lanes = 0;
-+
-+	power_state->display.disableFrameModulation = false;
-+	power_state->display.limitRefreshrate = false;
-+	power_state->display.enableVariBright =
-+			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
-+					ATOM_Tonga_ENABLE_VARIBRIGHT));
-+
-+	power_state->validation.supportedPowerLevels = 0;
-+	power_state->uvd_clocks.VCLK = 0;
-+	power_state->uvd_clocks.DCLK = 0;
-+	power_state->temperatures.min = 0;
-+	power_state->temperatures.max = 0;
-+
-+	performance_level = &(polaris10_power_state->performance_levels
-+			[polaris10_power_state->performance_level_count++]);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
-+			"Performance levels exceeds SMC limit!",
-+			return -1);
-+
-+	PP_ASSERT_WITH_CODE(
-+			(polaris10_power_state->performance_level_count <=
-+					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
-+			"Performance levels exceeds Driver limit!",
-+			return -1);
-+
-+	/* Performance levels are arranged from low to high. */
-+	performance_level->memory_clock = mclk_dep_table->entries
-+			[state_entry->ucMemoryClockIndexLow].ulMclk;
-+	performance_level->engine_clock = sclk_dep_table->entries
-+			[state_entry->ucEngineClockIndexLow].ulSclk;
-+	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
-+			state_entry->ucPCIEGenLow);
-+	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-+			state_entry->ucPCIELaneHigh);
-+
-+	performance_level = &(polaris10_power_state->performance_levels
-+			[polaris10_power_state->performance_level_count++]);
-+	performance_level->memory_clock = mclk_dep_table->entries
-+			[state_entry->ucMemoryClockIndexHigh].ulMclk;
-+	performance_level->engine_clock = sclk_dep_table->entries
-+			[state_entry->ucEngineClockIndexHigh].ulSclk;
-+	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
-+			state_entry->ucPCIEGenHigh);
-+	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-+			state_entry->ucPCIELaneHigh);
-+
-+	return 0;
-+}
-+
-+static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
-+		unsigned long entry_index, struct pp_power_state *state)
-+{
-+	int result;
-+	struct polaris10_power_state *ps;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
-+			table_info->vdd_dep_on_mclk;
-+
-+	state->hardware.magic = PHM_VIslands_Magic;
-+
-+	ps = (struct polaris10_power_state *)(&state->hardware);
-+
-+	result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
-+			polaris10_get_pp_table_entry_callback_func);
-+
-+	/* This is the earliest time we have all the dependency table and the VBIOS boot state
-+	 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
-+	 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
-+	 */
-+	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
-+		if (dep_mclk_table->entries[0].clk !=
-+				data->vbios_boot_state.mclk_bootup_value)
-+			printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot MCLK level");
-+		if (dep_mclk_table->entries[0].vddci !=
-+				data->vbios_boot_state.vddci_bootup_value)
-+			printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
-+					"does not match VBIOS boot VDDCI level");
-+	}
-+
-+	/* set DC compatible flag if this state supports DC */
-+	if (!state->validation.disallowOnDC)
-+		ps->dc_compatible = true;
-+
-+	if (state->classification.flags & PP_StateClassificationFlag_ACPI)
-+		data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
-+
-+	ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
-+	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
-+
-+	if (!result) {
-+		uint32_t i;
-+
-+		switch (state->classification.ui_label) {
-+		case PP_StateUILabel_Performance:
-+			data->use_pcie_performance_levels = true;
-+
-+			for (i = 0; i < ps->performance_level_count; i++) {
-+				if (data->pcie_gen_performance.max <
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.max =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_performance.min >
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_performance.min =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_performance.max <
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.max =
-+							ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_performance.min >
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_performance.min =
-+							ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		case PP_StateUILabel_Battery:
-+			data->use_pcie_power_saving_levels = true;
-+
-+			for (i = 0; i < ps->performance_level_count; i++) {
-+				if (data->pcie_gen_power_saving.max <
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.max =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_gen_power_saving.min >
-+						ps->performance_levels[i].pcie_gen)
-+					data->pcie_gen_power_saving.min =
-+							ps->performance_levels[i].pcie_gen;
-+
-+				if (data->pcie_lane_power_saving.max <
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.max =
-+							ps->performance_levels[i].pcie_lane;
-+
-+				if (data->pcie_lane_power_saving.min >
-+						ps->performance_levels[i].pcie_lane)
-+					data->pcie_lane_power_saving.min =
-+							ps->performance_levels[i].pcie_lane;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static void
-+polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
-+{
-+	uint32_t sclk, mclk;
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+
-+	sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+
-+	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
-+			mclk / 100, sclk / 100);
-+}
-+
-+static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	const struct polaris10_power_state *polaris10_ps =
-+			cast_const_phw_polaris10_power_state(states->pnew_state);
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
-+	uint32_t sclk = polaris10_ps->performance_levels
-+			[polaris10_ps->performance_level_count - 1].engine_clock;
-+	struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
-+	uint32_t mclk = polaris10_ps->performance_levels
-+			[polaris10_ps->performance_level_count - 1].memory_clock;
-+	struct PP_Clocks min_clocks = {0};
-+	uint32_t i;
-+	struct cgs_display_info info = {0};
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	for (i = 0; i < sclk_table->count; i++) {
-+		if (sclk == sclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= sclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-+	else {
-+	/* TODO: Check SCLK in DAL's minimum clocks
-+	 * in case DeepSleep divider update is required.
-+	 */
-+		if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
-+			(min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
-+				data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
-+			data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
-+	}
-+
-+	for (i = 0; i < mclk_table->count; i++) {
-+		if (mclk == mclk_table->dpm_levels[i].value)
-+			break;
-+	}
-+
-+	if (i >= mclk_table->count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
-+
-+	return 0;
-+}
-+
-+static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
-+		const struct polaris10_power_state *polaris10_ps)
-+{
-+	uint32_t i;
-+	uint32_t sclk, max_sclk = 0;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_dpm_table *dpm_table = &data->dpm_table;
-+
-+	for (i = 0; i < polaris10_ps->performance_level_count; i++) {
-+		sclk = polaris10_ps->performance_levels[i].engine_clock;
-+		if (max_sclk < sclk)
-+			max_sclk = sclk;
-+	}
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
-+			return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
-+					dpm_table->pcie_speed_table.dpm_levels
-+					[dpm_table->pcie_speed_table.count - 1].value :
-+					dpm_table->pcie_speed_table.dpm_levels[i].value);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_request_link_speed_change_before_state_change(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	const struct polaris10_power_state *polaris10_nps =
-+			cast_const_phw_polaris10_power_state(states->pnew_state);
-+	const struct polaris10_power_state *polaris10_cps =
-+			cast_const_phw_polaris10_power_state(states->pcurrent_state);
-+
-+	uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
-+	uint16_t current_link_speed;
-+
-+	if (data->force_pcie_gen == PP_PCIEGenInvalid)
-+		current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
-+	else
-+		current_link_speed = data->force_pcie_gen;
-+
-+	data->force_pcie_gen = PP_PCIEGenInvalid;
-+	data->pspp_notify_required = false;
-+
-+	if (target_link_speed > current_link_speed) {
-+		switch (target_link_speed) {
-+		case PP_PCIEGen3:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
-+				break;
-+			data->force_pcie_gen = PP_PCIEGen2;
-+			if (current_link_speed == PP_PCIEGen2)
-+				break;
-+		case PP_PCIEGen2:
-+			if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
-+				break;
-+		default:
-+			data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
-+			break;
-+		}
-+	} else {
-+		if (target_link_speed < current_link_speed)
-+			data->pspp_notify_required = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+		PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
-+				"Trying to freeze SCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_FreezeLevel),
-+				"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
-+				return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		 DPMTABLE_OD_UPDATE_MCLK)) {
-+		PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
-+				"Trying to freeze MCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_MCLKDPM_FreezeLevel),
-+				"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
-+				return -1);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result = 0;
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	const struct polaris10_power_state *polaris10_ps =
-+			cast_const_phw_polaris10_power_state(states->pnew_state);
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t sclk = polaris10_ps->performance_levels
-+			[polaris10_ps->performance_level_count - 1].engine_clock;
-+	uint32_t mclk = polaris10_ps->performance_levels
-+			[polaris10_ps->performance_level_count - 1].memory_clock;
-+	struct polaris10_dpm_table *dpm_table = &data->dpm_table;
-+
-+	struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
-+	uint32_t dpm_count, clock_percent;
-+	uint32_t i;
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
-+		dpm_table->sclk_table.dpm_levels
-+		[dpm_table->sclk_table.count - 1].value = sclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-+		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+		/* Need to do calculation based on the golden DPM table
-+		 * as the Heatmap GPU Clock axis is also based on the default values
-+		 */
-+			PP_ASSERT_WITH_CODE(
-+				(golden_dpm_table->sclk_table.dpm_levels
-+						[golden_dpm_table->sclk_table.count - 1].value != 0),
-+				"Divide by 0!",
-+				return -1);
-+			dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
-+
-+			for (i = dpm_count; i > 1; i--) {
-+				if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
-+					clock_percent =
-+					      ((sclk
-+						- golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
-+						) * 100)
-+						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-+
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value +
-+							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-+								clock_percent)/100;
-+
-+				} else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
-+					clock_percent =
-+						((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
-+						- sclk) * 100)
-+						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-+
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value -
-+							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+				} else
-+					dpm_table->sclk_table.dpm_levels[i].value =
-+							golden_dpm_table->sclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
-+		dpm_table->mclk_table.dpm_levels
-+			[dpm_table->mclk_table.count - 1].value = mclk;
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-+		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+
-+			PP_ASSERT_WITH_CODE(
-+					(golden_dpm_table->mclk_table.dpm_levels
-+						[golden_dpm_table->mclk_table.count-1].value != 0),
-+					"Divide by 0!",
-+					return -1);
-+			dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
-+			for (i = dpm_count; i > 1; i--) {
-+				if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
-+					clock_percent = ((mclk -
-+					golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
-+					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-+
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value +
-+							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-+							clock_percent) / 100;
-+
-+				} else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
-+					clock_percent = (
-+					 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
-+					* 100)
-+					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-+
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value -
-+							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-+									clock_percent) / 100;
-+				} else
-+					dpm_table->mclk_table.dpm_levels[i].value =
-+							golden_dpm_table->mclk_table.dpm_levels[i].value;
-+			}
-+		}
-+	}
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
-+		result = polaris10_populate_all_graphic_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
-+		/*populate MCLK dpm table to SMU7 */
-+		result = polaris10_populate_all_memory_levels(hwmgr);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
-+				return result);
-+	}
-+
-+	return result;
-+}
-+
-+static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
-+			  struct polaris10_single_dpm_table *dpm_table,
-+			uint32_t low_limit, uint32_t high_limit)
-+{
-+	uint32_t i;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	for (i = 0; i < dpm_table->count; i++) {
-+		if ((dpm_table->dpm_levels[i].value < low_limit)
-+		|| (dpm_table->dpm_levels[i].value > high_limit))
-+			dpm_table->dpm_levels[i].enabled = false;
-+		else if (((1 << i) & data->disable_dpm_mask) == 0)
-+			dpm_table->dpm_levels[i].enabled = false;
-+		else
-+			dpm_table->dpm_levels[i].enabled = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
-+		const struct polaris10_power_state *polaris10_ps)
-+{
-+	int result = 0;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t high_limit_count;
-+
-+	PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
-+			"power state did not have any performance level",
-+			return -1);
-+
-+	high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
-+
-+	polaris10_trim_single_dpm_states(hwmgr,
-+			&(data->dpm_table.sclk_table),
-+			polaris10_ps->performance_levels[0].engine_clock,
-+			polaris10_ps->performance_levels[high_limit_count].engine_clock);
-+
-+	polaris10_trim_single_dpm_states(hwmgr,
-+			&(data->dpm_table.mclk_table),
-+			polaris10_ps->performance_levels[0].memory_clock,
-+			polaris10_ps->performance_levels[high_limit_count].memory_clock);
-+
-+	return result;
-+}
-+
-+static int polaris10_generate_dpm_level_enable_mask(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int result;
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	const struct polaris10_power_state *polaris10_ps =
-+			cast_const_phw_polaris10_power_state(states->pnew_state);
-+
-+	result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
-+	if (result)
-+		return result;
-+
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+			PPSMC_MSG_UVDDPM_Enable :
-+			PPSMC_MSG_UVDDPM_Disable);
-+}
-+
-+int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+			PPSMC_MSG_VCEDPM_Enable :
-+			PPSMC_MSG_VCEDPM_Disable);
-+}
-+
-+int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, enable?
-+			PPSMC_MSG_SAMUDPM_Enable :
-+			PPSMC_MSG_SAMUDPM_Disable);
-+}
-+
-+int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.UvdBootLevel = 0;
-+		if (table_info->mm_dep_table->count > 0)
-+			data->smc_state_table.UvdBootLevel =
-+					(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0x00FFFFFF;
-+		mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_UVDDPM) ||
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_UVDDPM_SetEnabledMask,
-+					(uint32_t)(1 << data->smc_state_table.UvdBootLevel));
-+	}
-+
-+	return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
-+}
-+
-+static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	const struct polaris10_power_state *polaris10_nps =
-+			cast_const_phw_polaris10_power_state(states->pnew_state);
-+	const struct polaris10_power_state *polaris10_cps =
-+			cast_const_phw_polaris10_power_state(states->pcurrent_state);
-+
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (polaris10_nps->vce_clks.evclk > 0 &&
-+	(polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
-+
-+		data->smc_state_table.VceBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFF00FFFF;
-+		mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_VCEDPM_SetEnabledMask,
-+					(uint32_t)1 << data->smc_state_table.VceBootLevel);
-+
-+			polaris10_enable_disable_vce_dpm(hwmgr, true);
-+		} else if (polaris10_nps->vce_clks.evclk == 0 &&
-+				polaris10_cps != NULL &&
-+				polaris10_cps->vce_clks.evclk > 0)
-+			polaris10_enable_disable_vce_dpm(hwmgr, false);
-+	}
-+
-+	return 0;
-+}
-+
-+int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (!bgate) {
-+		data->smc_state_table.SamuBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+		mm_boot_level_offset = data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
-+		mm_boot_level_offset /= 4;
-+		mm_boot_level_offset *= 4;
-+		mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset);
-+		mm_boot_level_value &= 0xFFFFFF00;
-+		mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
-+		cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_StablePState))
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SAMUDPM_SetEnabledMask,
-+					(uint32_t)(1 << data->smc_state_table.SamuBootLevel));
-+	}
-+
-+	return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
-+}
-+
-+static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = polaris10_copy_bytes_to_smc(
-+				hwmgr->smumgr,
-+				data->dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				data->sram_end);
-+	}
-+
-+	return result;
-+}
-+
-+static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return polaris10_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (0 == data->need_update_smu7_dpm_table)
-+		return 0;
-+
-+	if ((0 == data->sclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
-+
-+		PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze SCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+			"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
-+			return -1);
-+	}
-+
-+	if ((0 == data->mclk_dpm_key_disabled) &&
-+		(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
-+
-+		PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
-+				"Trying to Unfreeze MCLK DPM when DPM is disabled",
-+				);
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+		    "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
-+		    return -1);
-+	}
-+
-+	data->need_update_smu7_dpm_table = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_notify_link_speed_change_after_state_change(
-+		struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	const struct phm_set_power_state_input *states =
-+			(const struct phm_set_power_state_input *)input;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	const struct polaris10_power_state *polaris10_ps =
-+			cast_const_phw_polaris10_power_state(states->pnew_state);
-+	uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
-+	uint8_t  request;
-+
-+	if (data->pspp_notify_required) {
-+		if (target_link_speed == PP_PCIEGen3)
-+			request = PCIE_PERF_REQ_GEN3;
-+		else if (target_link_speed == PP_PCIEGen2)
-+			request = PCIE_PERF_REQ_GEN2;
-+		else
-+			request = PCIE_PERF_REQ_GEN1;
-+
-+		if (request == PCIE_PERF_REQ_GEN1 &&
-+				phm_get_current_pcie_speed(hwmgr) > 0)
-+			return 0;
-+
-+		if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
-+			if (PP_PCIEGen2 == target_link_speed)
-+				printk("PSPP request to switch to Gen2 from Gen3 Failed!");
-+			else
-+				printk("PSPP request to switch to Gen1 from Gen2 Failed!");
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int tmp_result, result = 0;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to find DPM states clocks in DPM table!",
-+			result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result =
-+			polaris10_request_link_speed_change_before_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to request link speed change before state change!",
-+				result = tmp_result);
-+	}
-+
-+	tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to freeze SCLK MCLK DPM!", result = tmp_result);
-+
-+	tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to populate and upload SCLK MCLK DPM levels!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to generate DPM level enabled mask!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_update_vce_dpm(hwmgr, input);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to update VCE DPM!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_update_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to update SCLK threshold!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to program memory timing parameters!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to unfreeze SCLK MCLK DPM!",
-+			result = tmp_result);
-+
-+	tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to upload DPM level enabled mask!",
-+			result = tmp_result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PCIEPerformanceRequest)) {
-+		tmp_result =
-+			polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
-+		PP_ASSERT_WITH_CODE((0 == tmp_result),
-+				"Failed to notify link speed change after state change!",
-+				result = tmp_result);
-+	}
-+	data->apply_optimized_settings = false;
-+	return result;
-+}
-+
-+static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
-+{
-+	hwmgr->thermal_controller.
-+	advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
-+}
-+
-+int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
-+{
-+	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
-+
-+	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
-+}
-+
-+int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t num_active_displays = 0;
-+	struct cgs_display_info info = {0};
-+	info.mode_info = NULL;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	num_active_displays = info.display_count;
-+
-+	if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
-+		polaris10_notify_smc_display_change(hwmgr, false);
-+	else
-+		polaris10_notify_smc_display_change(hwmgr, true);
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs the display gap
-+*
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @return   always OK
-+*/
-+int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t num_active_displays = 0;
-+	uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
-+	uint32_t display_gap2;
-+	uint32_t pre_vbi_time_in_us;
-+	uint32_t frame_time_in_us;
-+	uint32_t ref_clock;
-+	uint32_t refresh_rate = 0;
-+	struct cgs_display_info info = {0};
-+	struct cgs_mode_info mode_info;
-+
-+	info.mode_info = &mode_info;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	num_active_displays = info.display_count;
-+
-+	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
-+
-+	ref_clock = mode_info.ref_clock;
-+	refresh_rate = mode_info.refresh_rate;
-+
-+	if (0 == refresh_rate)
-+		refresh_rate = 60;
-+
-+	frame_time_in_us = 1000000 / refresh_rate;
-+
-+	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
-+	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
-+
-+	polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
-+
-+	return 0;
-+}
-+
-+
-+int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
-+{
-+	return polaris10_program_display_gap(hwmgr);
-+}
-+
-+/**
-+*  Set maximum target operating fan output RPM
-+*
-+* @param    hwmgr:  the address of the powerplay hardware manager.
-+* @param    usMaxFanRpm:  max operating fan RPM value.
-+* @return   The response that came from the SMC.
-+*/
-+static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
-+{
-+	hwmgr->thermal_controller.
-+	advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
-+
-+	if (phm_is_hw_access_blocked(hwmgr))
-+		return 0;
-+
-+	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
-+}
-+
-+int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
-+					const void *thermal_interrupt_info)
-+{
-+	return 0;
-+}
-+
-+bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	bool is_update_required = false;
-+	struct cgs_display_info info = {0, 0, NULL};
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (data->display_timing.num_existing_displays != info.display_count)
-+		is_update_required = true;
-+/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
-+	if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+		cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
-+		if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
-+			(min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
-+				data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
-+			is_update_required = true;
-+*/
-+	return is_update_required;
-+}
-+
-+static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
-+							   const struct polaris10_performance_level *pl2)
-+{
-+	return ((pl1->memory_clock == pl2->memory_clock) &&
-+		  (pl1->engine_clock == pl2->engine_clock) &&
-+		  (pl1->pcie_gen == pl2->pcie_gen) &&
-+		  (pl1->pcie_lane == pl2->pcie_lane));
-+}
-+
-+int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
-+{
-+	const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
-+	const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
-+	int i;
-+
-+	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
-+		return -EINVAL;
-+
-+	/* If the two states don't even have the same number of performance levels they cannot be the same state. */
-+	if (psa->performance_level_count != psb->performance_level_count) {
-+		*equal = false;
-+		return 0;
-+	}
-+
-+	for (i = 0; i < psa->performance_level_count; i++) {
-+		if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
-+			/* If we have found even one performance level pair that is different the states are different. */
-+			*equal = false;
-+			return 0;
-+		}
-+	}
-+
-+	/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
-+	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
-+	*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
-+	*equal &= (psa->sclk_threshold == psb->sclk_threshold);
-+
-+	return 0;
-+}
-+
-+int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t vbios_version;
-+
-+	/*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
-+
-+	phm_get_mc_microcode_version(hwmgr);
-+	vbios_version = hwmgr->microcode_version_info.MC & 0xf;
-+	/*  Full version of MC ucode has already been loaded. */
-+	if (vbios_version == 0) {
-+		data->need_long_memory_training = false;
-+		return 0;
-+	}
-+
-+	data->need_long_memory_training = true;
-+
-+/*
-+ * 	PPMCME_FirmwareDescriptorEntry *pfd = NULL;
-+	pfd = &tonga_mcmeFirmware;
-+	if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
-+		polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
-+					pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
-+					pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
-+*/
-+	return 0;
-+}
-+
-+/**
-+ * Read clock related registers.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
-+						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
-+						& CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
-+						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
-+						& CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
-+
-+	data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
-+						CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
-+						& CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
-+
-+	return 0;
-+}
-+
-+/**
-+ * Find out if memory is GDDR5.
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t temp;
-+
-+	temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
-+
-+	data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
-+			((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
-+			 MC_SEQ_MISC0_GDDR5_SHIFT));
-+
-+	return 0;
-+}
-+
-+/**
-+ * Enables Dynamic Power Management by SMC
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
-+{
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			GENERAL_PWRMGT, STATIC_PM_EN, 1);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initialize PowerGating States for different engines
-+ *
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-+ * @return   always 0
-+ */
-+static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	data->uvd_power_gated = false;
-+	data->vce_power_gated = false;
-+	data->samu_power_gated = false;
-+
-+	return 0;
-+}
-+
-+static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	data->low_sclk_interrupt_threshold = 0;
-+
-+	return 0;
-+}
-+
-+int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
-+{
-+	int tmp_result, result = 0;
-+
-+	polaris10_upload_mc_firmware(hwmgr);
-+
-+	tmp_result = polaris10_read_clock_registers(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to read clock registers!", result = tmp_result);
-+
-+	tmp_result = polaris10_get_memory_type(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to get memory type!", result = tmp_result);
-+
-+	tmp_result = polaris10_enable_acpi_power_management(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to enable ACPI power management!", result = tmp_result);
-+
-+	tmp_result = polaris10_init_power_gate_state(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to init power gate state!", result = tmp_result);
-+
-+	tmp_result = phm_get_mc_microcode_version(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to get MC microcode version!", result = tmp_result);
-+
-+	tmp_result = polaris10_init_sclk_threshold(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == tmp_result),
-+			"Failed to init sclk threshold!", result = tmp_result);
-+
-+	return result;
-+}
-+
-+static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	*table = (char *)&data->smc_state_table;
-+
-+	return sizeof(struct SMU74_Discrete_DpmTable);
-+}
-+
-+static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	void *table = (void *)&data->smc_state_table;
-+
-+	memcpy(table, buf, size);
-+
-+	return 0;
-+}
-+
-+static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, int level)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-+		return -EINVAL;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		if (!data->sclk_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_SCLKDPM_SetEnabledMask,
-+					(1 << level));
-+		break;
-+	case PP_MCLK:
-+		if (!data->mclk_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_MCLKDPM_SetEnabledMask,
-+					(1 << level));
-+		break;
-+	case PP_PCIE:
-+		if (!data->pcie_dpm_key_disabled)
-+			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+					PPSMC_MSG_PCIeDPM_ForceLevel,
-+					(1 << level));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t speedCntl = 0;
-+
-+	/* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
-+	speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
-+			ixPCIE_LC_SPEED_CNTL);
-+	return((uint16_t)PHM_GET_FIELD(speedCntl,
-+			PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
-+}
-+
-+static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
-+		enum pp_clock_type type, char *buf)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
-+	struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
-+	struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
-+	int i, now, size = 0;
-+	uint32_t clock, pcie_speed;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+		for (i = 0; i < sclk_table->count; i++) {
-+			if (clock > sclk_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < sclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, sclk_table->dpm_levels[i].value / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	case PP_MCLK:
-+		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-+
-+		for (i = 0; i < mclk_table->count; i++) {
-+			if (clock > mclk_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < mclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i, mclk_table->dpm_levels[i].value / 100,
-+					(i == now) ? "*" : "");
-+		break;
-+	case PP_PCIE:
-+		pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
-+		for (i = 0; i < pcie_table->count; i++) {
-+			if (pcie_speed != pcie_table->dpm_levels[i].value)
-+				continue;
-+			break;
-+		}
-+		now = i;
-+
-+		for (i = 0; i < pcie_table->count; i++)
-+			size += sprintf(buf + size, "%d: %s %s\n", i,
-+					(pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
-+					(pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
-+					(pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
-+					(i == now) ? "*" : "");
-+		break;
-+	default:
-+		break;
-+	}
-+	return size;
-+}
-+
-+static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
-+	.backend_init = &polaris10_hwmgr_backend_init,
-+	.backend_fini = &polaris10_hwmgr_backend_fini,
-+	.asic_setup = &polaris10_setup_asic_task,
-+	.dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
-+	.apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
-+	.force_dpm_level = &polaris10_force_dpm_level,
-+	.power_state_set = polaris10_set_power_state_tasks,
-+	.get_power_state_size = polaris10_get_power_state_size,
-+	.get_mclk = polaris10_dpm_get_mclk,
-+	.get_sclk = polaris10_dpm_get_sclk,
-+	.patch_boot_state = polaris10_dpm_patch_boot_state,
-+	.get_pp_table_entry = polaris10_get_pp_table_entry,
-+	.get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
-+	.print_current_perforce_level = polaris10_print_current_perforce_level,
-+	.powerdown_uvd = polaris10_phm_powerdown_uvd,
-+	.powergate_uvd = polaris10_phm_powergate_uvd,
-+	.powergate_vce = polaris10_phm_powergate_vce,
-+	.disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
-+	.update_clock_gatings = polaris10_phm_update_clock_gatings,
-+	.notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
-+	.display_config_changed = polaris10_display_configuration_changed_task,
-+	.set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
-+	.set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
-+	.get_temperature = polaris10_thermal_get_temperature,
-+	.stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
-+	.get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
-+	.get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
-+	.set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
-+	.reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
-+	.get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
-+	.set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
-+	.uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
-+	.register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
-+	.check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
-+	.check_states_equal = polaris10_check_states_equal,
-+	.get_pp_table = polaris10_get_pp_table,
-+	.set_pp_table = polaris10_set_pp_table,
-+	.force_clock_level = polaris10_force_clock_level,
-+	.print_clock_levels = polaris10_print_clock_levels,
-+	.enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
-+};
-+
-+int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr  *data;
-+
-+	data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
-+	if (data == NULL)
-+		return -ENOMEM;
-+
-+	hwmgr->backend = data;
-+	hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
-+	hwmgr->pptable_func = &tonga_pptable_funcs;
-+	pp_polaris10_thermal_initialize(hwmgr);
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-new file mode 100644
-index 0000000..2507404
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-@@ -0,0 +1,354 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef POLARIS10_HWMGR_H
-+#define POLARIS10_HWMGR_H
-+
-+#include "hwmgr.h"
-+#include "smu74.h"
-+#include "smu74_discrete.h"
-+#include "ppatomctrl.h"
-+#include "polaris10_ppsmc.h"
-+#include "polaris10_powertune.h"
-+
-+#define POLARIS10_MAX_HARDWARE_POWERLEVELS	2
-+
-+#define POLARIS10_VOLTAGE_CONTROL_NONE                   0x0
-+#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO                0x1
-+#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2               0x2
-+#define POLARIS10_VOLTAGE_CONTROL_MERGED                 0x3
-+
-+#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-+#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
-+#define DPMTABLE_UPDATE_SCLK        0x00000004
-+#define DPMTABLE_UPDATE_MCLK        0x00000008
-+
-+struct polaris10_performance_level {
-+	uint32_t  memory_clock;
-+	uint32_t  engine_clock;
-+	uint16_t  pcie_gen;
-+	uint16_t  pcie_lane;
-+};
-+
-+struct polaris10_uvd_clocks {
-+	uint32_t  vclk;
-+	uint32_t  dclk;
-+};
-+
-+struct polaris10_vce_clocks {
-+	uint32_t  evclk;
-+	uint32_t  ecclk;
-+};
-+
-+struct polaris10_power_state {
-+	uint32_t                  magic;
-+	struct polaris10_uvd_clocks    uvd_clks;
-+	struct polaris10_vce_clocks    vce_clks;
-+	uint32_t                  sam_clk;
-+	uint16_t                  performance_level_count;
-+	bool                      dc_compatible;
-+	uint32_t                  sclk_threshold;
-+	struct polaris10_performance_level  performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS];
-+};
-+
-+struct polaris10_dpm_level {
-+	bool	enabled;
-+	uint32_t	value;
-+	uint32_t	param1;
-+};
-+
-+#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5
-+#define MAX_REGULAR_DPM_NUMBER 8
-+#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500
-+
-+struct polaris10_single_dpm_table {
-+	uint32_t		count;
-+	struct polaris10_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
-+};
-+
-+struct polaris10_dpm_table {
-+	struct polaris10_single_dpm_table  sclk_table;
-+	struct polaris10_single_dpm_table  mclk_table;
-+	struct polaris10_single_dpm_table  pcie_speed_table;
-+	struct polaris10_single_dpm_table  vddc_table;
-+	struct polaris10_single_dpm_table  vddci_table;
-+	struct polaris10_single_dpm_table  mvdd_table;
-+};
-+
-+struct polaris10_clock_registers {
-+	uint32_t  vCG_SPLL_FUNC_CNTL;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t  vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t  vDLL_CNTL;
-+	uint32_t  vMCLK_PWRMGT_CNTL;
-+	uint32_t  vMPLL_AD_FUNC_CNTL;
-+	uint32_t  vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL;
-+	uint32_t  vMPLL_FUNC_CNTL_1;
-+	uint32_t  vMPLL_FUNC_CNTL_2;
-+	uint32_t  vMPLL_SS1;
-+	uint32_t  vMPLL_SS2;
-+};
-+
-+#define DISABLE_MC_LOADMICROCODE   1
-+#define DISABLE_MC_CFGPROGRAMMING  2
-+
-+struct polaris10_voltage_smio_registers {
-+	uint32_t vS0_VID_LOWER_SMIO_CNTL;
-+};
-+
-+#define POLARIS10_MAX_LEAKAGE_COUNT  8
-+
-+struct polaris10_leakage_voltage {
-+	uint16_t  count;
-+	uint16_t  leakage_id[POLARIS10_MAX_LEAKAGE_COUNT];
-+	uint16_t  actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT];
-+};
-+
-+struct polaris10_vbios_boot_state {
-+	uint16_t    mvdd_bootup_value;
-+	uint16_t    vddc_bootup_value;
-+	uint16_t    vddci_bootup_value;
-+	uint32_t    sclk_bootup_value;
-+	uint32_t    mclk_bootup_value;
-+	uint16_t    pcie_gen_bootup_value;
-+	uint16_t    pcie_lane_bootup_value;
-+};
-+
-+/* Ultra Low Voltage parameter structure */
-+struct polaris10_ulv_parm {
-+	bool                           ulv_supported;
-+	uint32_t                       cg_ulv_parameter;
-+	uint32_t                       ulv_volt_change_delay;
-+	struct polaris10_performance_level  ulv_power_level;
-+};
-+
-+struct polaris10_display_timing {
-+	uint32_t  min_clock_in_sr;
-+	uint32_t  num_existing_displays;
-+};
-+
-+struct polaris10_dpmlevel_enable_mask {
-+	uint32_t  uvd_dpm_enable_mask;
-+	uint32_t  vce_dpm_enable_mask;
-+	uint32_t  acp_dpm_enable_mask;
-+	uint32_t  samu_dpm_enable_mask;
-+	uint32_t  sclk_dpm_enable_mask;
-+	uint32_t  mclk_dpm_enable_mask;
-+	uint32_t  pcie_dpm_enable_mask;
-+};
-+
-+struct polaris10_pcie_perf_range {
-+	uint16_t  max;
-+	uint16_t  min;
-+};
-+struct polaris10_range_table {
-+	uint32_t trans_lower_frequency; /* in 10khz */
-+	uint32_t trans_upper_frequency;
-+};
-+
-+struct polaris10_hwmgr {
-+	struct polaris10_dpm_table			dpm_table;
-+	struct polaris10_dpm_table			golden_dpm_table;
-+	SMU74_Discrete_DpmTable				smc_state_table;
-+	struct SMU74_Discrete_Ulv            ulv_setting;
-+
-+	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
-+	uint32_t						voting_rights_clients0;
-+	uint32_t						voting_rights_clients1;
-+	uint32_t						voting_rights_clients2;
-+	uint32_t						voting_rights_clients3;
-+	uint32_t						voting_rights_clients4;
-+	uint32_t						voting_rights_clients5;
-+	uint32_t						voting_rights_clients6;
-+	uint32_t						voting_rights_clients7;
-+	uint32_t						static_screen_threshold_unit;
-+	uint32_t						static_screen_threshold;
-+	uint32_t						voltage_control;
-+	uint32_t						vddc_vddci_delta;
-+
-+	uint32_t						active_auto_throttle_sources;
-+
-+	struct polaris10_clock_registers            clock_registers;
-+	struct polaris10_voltage_smio_registers      voltage_smio_registers;
-+
-+	bool                           is_memory_gddr5;
-+	uint16_t                       acpi_vddc;
-+	bool                           pspp_notify_required;
-+	uint16_t                       force_pcie_gen;
-+	uint16_t                       acpi_pcie_gen;
-+	uint32_t                       pcie_gen_cap;
-+	uint32_t                       pcie_lane_cap;
-+	uint32_t                       pcie_spc_cap;
-+	struct polaris10_leakage_voltage          vddc_leakage;
-+	struct polaris10_leakage_voltage          Vddci_leakage;
-+
-+	uint32_t                             mvdd_control;
-+	uint32_t                             vddc_mask_low;
-+	uint32_t                             mvdd_mask_low;
-+	uint16_t                            max_vddc_in_pptable;
-+	uint16_t                            min_vddc_in_pptable;
-+	uint16_t                            max_vddci_in_pptable;
-+	uint16_t                            min_vddci_in_pptable;
-+	uint32_t                             mclk_strobe_mode_threshold;
-+	uint32_t                             mclk_stutter_mode_threshold;
-+	uint32_t                             mclk_edc_enable_threshold;
-+	uint32_t                             mclk_edcwr_enable_threshold;
-+	bool                                is_uvd_enabled;
-+	struct polaris10_vbios_boot_state        vbios_boot_state;
-+
-+	bool                           pcie_performance_request;
-+	bool                           battery_state;
-+	bool                           is_tlu_enabled;
-+
-+	/* ---- SMC SRAM Address of firmware header tables ---- */
-+	uint32_t                             sram_end;
-+	uint32_t                             dpm_table_start;
-+	uint32_t                             soft_regs_start;
-+	uint32_t                             mc_reg_table_start;
-+	uint32_t                             fan_table_start;
-+	uint32_t                             arb_table_start;
-+
-+	/* ---- Stuff originally coming from Evergreen ---- */
-+	uint32_t                             vddci_control;
-+	struct pp_atomctrl_voltage_table     vddc_voltage_table;
-+	struct pp_atomctrl_voltage_table     vddci_voltage_table;
-+	struct pp_atomctrl_voltage_table     mvdd_voltage_table;
-+
-+	uint32_t                             mgcg_cgtt_local2;
-+	uint32_t                             mgcg_cgtt_local3;
-+	uint32_t                             gpio_debug;
-+	uint32_t                             mc_micro_code_feature;
-+	uint32_t                             highest_mclk;
-+	uint16_t                             acpi_vddci;
-+	uint8_t                              mvdd_high_index;
-+	uint8_t                              mvdd_low_index;
-+	bool                                 dll_default_on;
-+	bool                                 performance_request_registered;
-+
-+	/* ---- Low Power Features ---- */
-+	struct polaris10_ulv_parm                 ulv;
-+
-+	/* ---- CAC Stuff ---- */
-+	uint32_t                       cac_table_start;
-+	bool                           cac_configuration_required;
-+	bool                           driver_calculate_cac_leakage;
-+	bool                           cac_enabled;
-+
-+	/* ---- DPM2 Parameters ---- */
-+	uint32_t                       power_containment_features;
-+	bool                           enable_dte_feature;
-+	bool                           enable_tdc_limit_feature;
-+	bool                           enable_pkg_pwr_tracking_feature;
-+	bool                           disable_uvd_power_tune_feature;
-+	struct polaris10_pt_defaults       *power_tune_defaults;
-+	struct SMU74_Discrete_PmFuses  power_tune_table;
-+	uint32_t                       dte_tj_offset;
-+	uint32_t                       fast_watermark_threshold;
-+
-+	/* ---- Phase Shedding ---- */
-+	bool                           vddc_phase_shed_control;
-+
-+	/* ---- DI/DT ---- */
-+	struct polaris10_display_timing        display_timing;
-+	uint32_t                      bif_sclk_table[SMU74_MAX_LEVELS_LINK];
-+
-+	/* ---- Thermal Temperature Setting ---- */
-+	struct polaris10_dpmlevel_enable_mask     dpm_level_enable_mask;
-+	uint32_t                                  need_update_smu7_dpm_table;
-+	uint32_t                                  sclk_dpm_key_disabled;
-+	uint32_t                                  mclk_dpm_key_disabled;
-+	uint32_t                                  pcie_dpm_key_disabled;
-+	uint32_t                                  min_engine_clocks;
-+	struct polaris10_pcie_perf_range          pcie_gen_performance;
-+	struct polaris10_pcie_perf_range          pcie_lane_performance;
-+	struct polaris10_pcie_perf_range          pcie_gen_power_saving;
-+	struct polaris10_pcie_perf_range          pcie_lane_power_saving;
-+	bool                                      use_pcie_performance_levels;
-+	bool                                      use_pcie_power_saving_levels;
-+	uint32_t                                  activity_target[SMU74_MAX_LEVELS_GRAPHICS];
-+	uint32_t                                  mclk_activity_target;
-+	uint32_t                                  mclk_dpm0_activity_target;
-+	uint32_t                                  low_sclk_interrupt_threshold;
-+	uint32_t                                  last_mclk_dpm_enable_mask;
-+	bool                                      uvd_enabled;
-+
-+	/* ---- Power Gating States ---- */
-+	bool                           uvd_power_gated;
-+	bool                           vce_power_gated;
-+	bool                           samu_power_gated;
-+	bool                           need_long_memory_training;
-+
-+	/* Application power optimization parameters */
-+	bool                               update_up_hyst;
-+	bool                               update_down_hyst;
-+	uint32_t                           down_hyst;
-+	uint32_t                           up_hyst;
-+	uint32_t disable_dpm_mask;
-+	bool apply_optimized_settings;
-+};
-+
-+/* To convert to Q8.8 format for firmware */
-+#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT             256
-+
-+enum Polaris10_I2CLineID {
-+	Polaris10_I2CLineID_DDC1 = 0x90,
-+	Polaris10_I2CLineID_DDC2 = 0x91,
-+	Polaris10_I2CLineID_DDC3 = 0x92,
-+	Polaris10_I2CLineID_DDC4 = 0x93,
-+	Polaris10_I2CLineID_DDC5 = 0x94,
-+	Polaris10_I2CLineID_DDC6 = 0x95,
-+	Polaris10_I2CLineID_SCLSDA = 0x96,
-+	Polaris10_I2CLineID_DDCVGA = 0x97
-+};
-+
-+#define POLARIS10_I2C_DDC1DATA          0
-+#define POLARIS10_I2C_DDC1CLK           1
-+#define POLARIS10_I2C_DDC2DATA          2
-+#define POLARIS10_I2C_DDC2CLK           3
-+#define POLARIS10_I2C_DDC3DATA          4
-+#define POLARIS10_I2C_DDC3CLK           5
-+#define POLARIS10_I2C_SDA               40
-+#define POLARIS10_I2C_SCL               41
-+#define POLARIS10_I2C_DDC4DATA          65
-+#define POLARIS10_I2C_DDC4CLK           66
-+#define POLARIS10_I2C_DDC5DATA          0x48
-+#define POLARIS10_I2C_DDC5CLK           0x49
-+#define POLARIS10_I2C_DDC6DATA          0x4a
-+#define POLARIS10_I2C_DDC6CLK           0x4b
-+#define POLARIS10_I2C_DDCVGADATA        0x4c
-+#define POLARIS10_I2C_DDCVGACLK         0x4d
-+
-+#define POLARIS10_UNUSED_GPIO_PIN       0x7F
-+
-+int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
-+
-+int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-+int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-new file mode 100644
-index 0000000..4d97326
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-@@ -0,0 +1,396 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "hwmgr.h"
-+#include "smumgr.h"
-+#include "polaris10_hwmgr.h"
-+#include "polaris10_powertune.h"
-+#include "polaris10_smumgr.h"
-+#include "smu74_discrete.h"
-+#include "pp_debug.h"
-+
-+#define VOLTAGE_SCALE  4
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+
-+struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
-+	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
-+	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-+	{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
-+	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
-+};
-+
-+void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *polaris10_hwmgr = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct  phm_ppt_v1_information *table_info =
-+			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (table_info &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID)
-+		polaris10_hwmgr->power_tune_defaults =
-+				&polaris10_power_tune_data_set_array
-+				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
-+	else
-+		polaris10_hwmgr->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
-+
-+}
-+
-+int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+	SMU74_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	int i, j, k;
-+	uint16_t *pdef1;
-+	uint16_t *pdef2;
-+
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-+	dpm_table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-+
-+	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
-+				"Target Operating Temp is out of Range!",
-+				);
-+/*  This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */
-+	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
-+
-+/*  HW request to hard code this value to 8 which is 0.5C */
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
-+	dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset);
-+	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT);
-+	pdef1 = defaults->BAPMTI_R;
-+	pdef2 = defaults->BAPMTI_RC;
-+
-+	for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
-+		for (j = 0; j < SMU74_DTE_SOURCES; j++) {
-+			for (k = 0; k < SMU74_DTE_SINKS; k++) {
-+				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
-+				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
-+				pdef1++;
-+				pdef2++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+
-+	data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
-+	data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-+	data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct  polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+
-+	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
-+	data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
-+	data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+			fuse_table_offset +
-+			offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, data->sram_end))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else {
-+		data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
-+		data->power_tune_table.LPMLTemperatureMin =
-+				(uint8_t)((temp >> 16) & 0xff);
-+		data->power_tune_table.LPMLTemperatureMax =
-+				(uint8_t)((temp >> 8) & 0xff);
-+		data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
-+	}
-+	return 0;
-+}
-+
-+static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
-+		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
-+			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
-+				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
-+	return 0;
-+}
-+
-+static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-+{
-+	return 0;
-+}
-+
-+static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+
-+	hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
-+	data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
-+
-+	return 0;
-+}
-+
-+int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	uint32_t pm_fuse_table_offset;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU74_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, data->sram_end))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to get pm_fuse_table_offset Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate SviLoadLine Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed!", return -EINVAL);
-+
-+		if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TdcWaterfallCtl, "
-+					"LPMLTemperature Min and Max Failed!",
-+					return -EINVAL);
-+
-+		if (0 != polaris10_populate_temperature_scaler(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate LPMLTemperatureScaler Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_fuzzy_fan(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate Fuzzy Fan Control parameters Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Min and Max Vid Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
-+					"Sidd Failed!", return -EINVAL);
-+
-+		if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
-+				(uint8_t *)&data->power_tune_table,
-+				sizeof(struct SMU74_Discrete_PmFuses), data->sram_end))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed!",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	int result = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_CAC)) {
-+		int smc_result;
-+		smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+				(uint16_t)(PPSMC_MSG_EnableCac));
-+		PP_ASSERT_WITH_CODE((0 == smc_result),
-+				"Failed to enable CAC in SMC.", result = -1);
-+
-+		data->cac_enabled = (0 == smc_result) ? true : false;
-+	}
-+	return result;
-+}
-+
-+int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (data->power_containment_features &
-+			POWERCONTAINMENT_FEATURE_PkgPwrLimit)
-+		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_PkgPwrSetLimit, n);
-+	return 0;
-+}
-+
-+static int polaris10_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
-+{
-+	return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
-+			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
-+}
-+
-+int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int smc_result;
-+	int result = 0;
-+
-+	data->power_containment_features = 0;
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (data->enable_dte_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_EnableDTE));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable DTE in SMC.", result = -1;);
-+			if (0 == smc_result)
-+				data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
-+		}
-+
-+		if (data->enable_tdc_limit_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_TDCLimitEnable));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable TDCLimit in SMC.", result = -1;);
-+			if (0 == smc_result)
-+				data->power_containment_features |=
-+						POWERCONTAINMENT_FEATURE_TDCLimit;
-+		}
-+
-+		if (data->enable_pkg_pwr_tracking_feature) {
-+			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
-+			PP_ASSERT_WITH_CODE((0 == smc_result),
-+					"Failed to enable PkgPwrTracking in SMC.", result = -1;);
-+			if (0 == smc_result) {
-+				struct phm_cac_tdp_table *cac_table =
-+						table_info->cac_dtp_table;
-+				uint32_t default_limit =
-+					(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
-+
-+				data->power_containment_features |=
-+						POWERCONTAINMENT_FEATURE_PkgPwrLimit;
-+
-+				if (polaris10_set_power_limit(hwmgr, default_limit))
-+					printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
-+			}
-+		}
-+	}
-+	return result;
-+}
-+
-+int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+	int adjust_percent, target_tdp;
-+	int result = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		/* adjustment percentage has already been validated */
-+		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
-+				hwmgr->platform_descriptor.TDPAdjustment :
-+				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
-+		/* SMC requested that target_tdp to be 7 bit fraction in DPM table
-+		 * but message to be 8 bit fraction for messages
-+		 */
-+		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
-+		result = polaris10_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
-+	}
-+
-+	return result;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
-new file mode 100644
-index 0000000..68bc1cb
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
-@@ -0,0 +1,70 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef POLARIS10_POWERTUNE_H
-+#define POLARIS10_POWERTUNE_H
-+
-+enum polaris10_pt_config_reg_type {
-+	POLARIS10_CONFIGREG_MMR = 0,
-+	POLARIS10_CONFIGREG_SMC_IND,
-+	POLARIS10_CONFIGREG_DIDT_IND,
-+	POLARIS10_CONFIGREG_CACHE,
-+	POLARIS10_CONFIGREG_MAX
-+};
-+
-+/* PowerContainment Features */
-+#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
-+#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
-+#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
-+
-+struct polaris10_pt_config_reg {
-+	uint32_t                           offset;
-+	uint32_t                           mask;
-+	uint32_t                           shift;
-+	uint32_t                           value;
-+	enum polaris10_pt_config_reg_type       type;
-+};
-+
-+struct polaris10_pt_defaults {
-+	uint8_t   SviLoadLineEn;
-+	uint8_t   SviLoadLineVddC;
-+	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
-+	uint8_t   TDC_MAWt;
-+	uint8_t   TdcWaterfallCtl;
-+	uint8_t   DTEAmbientTempBase;
-+
-+	uint32_t  DisplayCac;
-+	uint32_t  BAPM_TEMP_GRADIENT;
-+	uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
-+	uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
-+};
-+
-+void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
-+int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
-+int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
-+int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr);
-+int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr);
-+int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
-+int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr);
-+
-+#endif  /* POLARIS10_POWERTUNE_H */
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-new file mode 100644
-index 0000000..d2f553d
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-@@ -0,0 +1,711 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "polaris10_thermal.h"
-+#include "polaris10_hwmgr.h"
-+#include "polaris10_smumgr.h"
-+#include "polaris10_ppsmc.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+
-+int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
-+		struct phm_fan_speed_info *fan_speed_info)
-+{
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	fan_speed_info->supports_percent_read = true;
-+	fan_speed_info->supports_percent_write = true;
-+	fan_speed_info->min_percent = 0;
-+	fan_speed_info->max_percent = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
-+		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
-+		fan_speed_info->supports_rpm_read = true;
-+		fan_speed_info->supports_rpm_write = true;
-+		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
-+		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
-+	} else {
-+		fan_speed_info->min_rpm = 0;
-+		fan_speed_info->max_rpm = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
-+		uint32_t *speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_STATUS, FDO_PWM_DUTY);
-+
-+	if (duty100 == 0)
-+		return -EINVAL;
-+
-+
-+	tmp64 = (uint64_t)duty * 100;
-+	do_div(tmp64, duty100);
-+	*speed = (uint32_t)tmp64;
-+
-+	if (*speed > 100)
-+		*speed = 100;
-+
-+	return 0;
-+}
-+
-+int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
-+{
-+	uint32_t tach_period;
-+	uint32_t crystal_clock_freq;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
-+			(hwmgr->thermal_controller.fanInfo.
-+				ucTachometerPulsesPerRevolution == 0))
-+		return 0;
-+
-+	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_TACH_STATUS, TACH_PERIOD);
-+
-+	if (tach_period == 0)
-+		return -EINVAL;
-+
-+	crystal_clock_freq = tonga_get_xclk(hwmgr);
-+
-+	*speed = 60 * crystal_clock_freq * 10000 / tach_period;
-+
-+	return 0;
-+}
-+
-+/**
-+* Set Fan Speed Control to static mode, so that the user can decide what speed to use.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+*           mode    the fan control mode, 0 default, 1 by percent, 5, by RPM
-+* @exception Should always succeed.
-+*/
-+int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+
-+	if (hwmgr->fan_ctrl_is_in_default_mode) {
-+		hwmgr->fan_ctrl_default_mode =
-+				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,	CGS_IND_REG__SMC,
-+						CG_FDO_CTRL2, FDO_PWM_MODE);
-+		hwmgr->tmin =
-+				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+						CG_FDO_CTRL2, TMIN);
-+		hwmgr->fan_ctrl_is_in_default_mode = false;
-+	}
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, TMIN, 0);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, FDO_PWM_MODE, mode);
-+
-+	return 0;
-+}
-+
-+/**
-+* Reset Fan Speed Control to default mode.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Should always succeed.
-+*/
-+int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (!hwmgr->fan_ctrl_is_in_default_mode) {
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, TMIN, hwmgr->tmin);
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	}
-+
-+	return 0;
-+}
-+
-+int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
-+		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_FanSpeedInTableIsRPM))
-+			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
-+					hwmgr->thermal_controller.
-+					advanceFanControlParameters.usMaxFanRPM);
-+		else
-+			hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
-+					hwmgr->thermal_controller.
-+					advanceFanControlParameters.usMaxFanPWM);
-+
-+	} else {
-+		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
-+		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+	}
-+
-+	if (!result && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucTargetTemperature)
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanTemperatureTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucTargetTemperature);
-+
-+	return result;
-+}
-+
-+
-+int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
-+{
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
-+}
-+
-+/**
-+* Set Fan Speed in percent.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (0% - 100%) to be set.
-+* @exception Fails is the 100% setting appears to be 0.
-+*/
-+int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
-+		uint32_t speed)
-+{
-+	uint32_t duty100;
-+	uint32_t duty;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (speed > 100)
-+		speed = 100;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl))
-+		polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0)
-+		return -EINVAL;
-+
-+	tmp64 = (uint64_t)speed * 100;
-+	do_div(tmp64, duty100);
-+	duty = (uint32_t)tmp64;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
-+
-+	return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reset Fan Speed to default.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @exception Always succeeds.
-+*/
-+int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan)
-+		return 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl)) {
-+		result = polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+		if (!result)
-+			result = polaris10_fan_ctrl_start_smc_fan_control(hwmgr);
-+	} else
-+		result = polaris10_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set Fan Speed in RPM.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    speed is the percentage value (min - max) to be set.
-+* @exception Fails is the speed not lie between min and max.
-+*/
-+int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
-+{
-+	uint32_t tach_period;
-+	uint32_t crystal_clock_freq;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
-+			(hwmgr->thermal_controller.fanInfo.
-+			ucTachometerPulsesPerRevolution == 0) ||
-+			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
-+			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
-+		return 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl))
-+		polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
-+
-+	crystal_clock_freq = tonga_get_xclk(hwmgr);
-+
-+	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_TACH_STATUS, TACH_PERIOD, tach_period);
-+
-+	return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+}
-+
-+/**
-+* Reads the remote temperature from the SIslands thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
-+{
-+	int temp;
-+
-+	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_STATUS, CTF_TEMP);
-+
-+	/* Bit 9 means the reading is lower than the lowest usable value. */
-+	if (temp & 0x200)
-+		temp = POLARIS10_THERMAL_MAXIMUM_TEMP_READING;
-+	else
-+		temp = temp & 0x1ff;
-+
-+	temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	return temp;
-+}
-+
-+/**
-+* Set the requested temperature range for high and low alert signals
-+*
-+* @param    hwmgr The address of the hardware manager.
-+* @param    range Temperature range to be programmed for high and low alert signals
-+* @exception PP_Result_BadInput if the input data is not valid.
-+*/
-+static int polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-+		uint32_t low_temp, uint32_t high_temp)
-+{
-+	uint32_t low = POLARIS10_THERMAL_MINIMUM_ALERT_TEMP *
-+			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+	uint32_t high = POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP *
-+			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	if (low < low_temp)
-+		low = low_temp;
-+	if (high > high_temp)
-+		high = high_temp;
-+
-+	if (low > high)
-+		return -EINVAL;
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, DIG_THERM_INTH,
-+			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, DIG_THERM_INTL,
-+			(low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_CTRL, DIG_THERM_DPM,
-+			(high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+
-+	return 0;
-+}
-+
-+/**
-+* Programs thermal controller one-time setting registers
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int polaris10_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
-+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_TACH_CTRL, EDGE_PER_REV,
-+				hwmgr->thermal_controller.fanInfo.
-+				ucTachometerPulsesPerRevolution - 1);
-+
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
-+
-+	return 0;
-+}
-+
-+/**
-+* Enable thermal alerts on the RV770 thermal controller.
-+*
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK);
-+	alert &= ~(POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to enable internal thermal interrupts */
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
-+}
-+
-+/**
-+* Disable thermal alerts on the RV770 thermal controller.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+static int polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t alert;
-+
-+	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK);
-+	alert |= (POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK);
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_THERMAL_INT, THERM_INT_MASK, alert);
-+
-+	/* send message to SMU to disable internal thermal interrupts */
-+	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
-+}
-+
-+/**
-+* Uninitialize the thermal controller.
-+* Currently just disables alerts.
-+* @param    hwmgr The address of the hardware manager.
-+*/
-+int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	int result = polaris10_thermal_disable_alert(hwmgr);
-+
-+	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
-+		polaris10_fan_ctrl_set_default_mode(hwmgr);
-+
-+	return result;
-+}
-+
-+/**
-+* Set up the fan table to control the fan using the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+	SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (data->fan_table_start == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
-+			usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->
-+			thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = tonga_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
-+			thermal_controller.advanceFanControlParameters.ulCycleDelay *
-+			reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
-+			hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	res = polaris10_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start,
-+			(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
-+			data->sram_end);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucMinimumPWMLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanMinPwm,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucMinimumPWMLimit);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				PPSMC_MSG_SetFanSclkTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-+
-+	if (res)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+
-+	return 0;
-+}
-+
-+/**
-+* Start the fan control on the SMC.
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+/* If the fantable setup has failed we could have disabled
-+ * PHM_PlatformCaps_MicrocodeFanControl even after
-+ * this function was included in the table.
-+ * Make sure that we still think controlling the fan is OK.
-+*/
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl)) {
-+		polaris10_fan_ctrl_start_smc_fan_control(hwmgr);
-+		polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Set temperature range for high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from set temperature range routine
-+*/
-+int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
-+
-+	if (range == NULL)
-+		return -EINVAL;
-+
-+	return polaris10_thermal_set_temperature_range(hwmgr, range->min, range->max);
-+}
-+
-+/**
-+* Programs one-time setting registers
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from initialize thermal controller routine
-+*/
-+int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+    return polaris10_thermal_initialize(hwmgr);
-+}
-+
-+/**
-+* Enable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from enable alert routine
-+*/
-+int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	return polaris10_thermal_enable_alert(hwmgr);
-+}
-+
-+/**
-+* Disable high and low alerts
-+* @param    hwmgr  the address of the powerplay hardware manager.
-+* @param    pInput the pointer to input data
-+* @param    pOutput the pointer to output data
-+* @param    pStorage the pointer to temporary storage
-+* @param    Result the last failure code
-+* @return   result from disable alert routine
-+*/
-+static int tf_polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	return polaris10_thermal_disable_alert(hwmgr);
-+}
-+
-+static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
-+		void *input, void *output, void *storage, int result)
-+{
-+	int ret;
-+	struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+
-+	if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
-+		return 0;
-+
-+	ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
-+			0 : -1;
-+
-+	if (!ret)
-+		/* If this param is not changed, this function could fire unnecessarily */
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
-+
-+	return ret;
-+}
-+
-+static struct phm_master_table_item
-+polaris10_thermal_start_thermal_controller_master_list[] = {
-+	{NULL, tf_polaris10_thermal_initialize},
-+	{NULL, tf_polaris10_thermal_set_temperature_range},
-+	{NULL, tf_polaris10_thermal_enable_alert},
-+	{NULL, tf_polaris10_thermal_avfs_enable},
-+/* We should restrict performance levels to low before we halt the SMC.
-+ * On the other hand we are still in boot state when we do this
-+ * so it would be pointless.
-+ * If this assumption changes we have to revisit this table.
-+ */
-+	{NULL, tf_polaris10_thermal_setup_fan_table},
-+	{NULL, tf_polaris10_thermal_start_smc_fan_control},
-+	{NULL, NULL}
-+};
-+
-+static struct phm_master_table_header
-+polaris10_thermal_start_thermal_controller_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	polaris10_thermal_start_thermal_controller_master_list
-+};
-+
-+static struct phm_master_table_item
-+polaris10_thermal_set_temperature_range_master_list[] = {
-+	{NULL, tf_polaris10_thermal_disable_alert},
-+	{NULL, tf_polaris10_thermal_set_temperature_range},
-+	{NULL, tf_polaris10_thermal_enable_alert},
-+	{NULL, NULL}
-+};
-+
-+struct phm_master_table_header
-+polaris10_thermal_set_temperature_range_master = {
-+	0,
-+	PHM_MasterTableFlag_None,
-+	polaris10_thermal_set_temperature_range_master_list
-+};
-+
-+int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
-+{
-+	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
-+		polaris10_fan_ctrl_set_default_mode(hwmgr);
-+	return 0;
-+}
-+
-+/**
-+* Initializes the thermal controller related functions in the Hardware Manager structure.
-+* @param    hwmgr The address of the hardware manager.
-+* @exception Any error code from the low-level communication.
-+*/
-+int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+
-+	result = phm_construct_table(hwmgr,
-+			&polaris10_thermal_set_temperature_range_master,
-+			&(hwmgr->set_temperature_range));
-+
-+	if (!result) {
-+		result = phm_construct_table(hwmgr,
-+				&polaris10_thermal_start_thermal_controller_master,
-+				&(hwmgr->start_thermal_controller));
-+		if (result)
-+			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
-+	}
-+
-+	if (!result)
-+		hwmgr->fan_ctrl_is_in_default_mode = true;
-+	return result;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h
-new file mode 100644
-index 0000000..62f8cbc
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _POLARIS10_THERMAL_H_
-+#define _POLARIS10_THERMAL_H_
-+
-+#include "hwmgr.h"
-+
-+#define POLARIS10_THERMAL_HIGH_ALERT_MASK         0x1
-+#define POLARIS10_THERMAL_LOW_ALERT_MASK          0x2
-+
-+#define POLARIS10_THERMAL_MINIMUM_TEMP_READING    -256
-+#define POLARIS10_THERMAL_MAXIMUM_TEMP_READING    255
-+
-+#define POLARIS10_THERMAL_MINIMUM_ALERT_TEMP      0
-+#define POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP      255
-+
-+#define FDO_PWM_MODE_STATIC  1
-+#define FDO_PWM_MODE_STATIC_RPM 5
-+
-+
-+extern int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+extern int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-+
-+extern int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
-+extern int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
-+extern int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
-+extern int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
-+extern int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-+extern int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr);
-+extern int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
-+extern int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
-+extern int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-+extern int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
-+extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-index a2c87ae..1b44f4e 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
-@@ -209,18 +209,18 @@ typedef struct _ATOM_Tonga_PCIE_Table {
- 	ATOM_Tonga_PCIE_Record entries[1];							/* Dynamically allocate entries. */
- } ATOM_Tonga_PCIE_Table;
- 
--typedef struct _ATOM_Ellesmere_PCIE_Record {
-+typedef struct _ATOM_Polaris10_PCIE_Record {
- 	UCHAR ucPCIEGenSpeed;
- 	UCHAR usPCIELaneWidth;
- 	UCHAR ucReserved[2];
- 	ULONG ulPCIE_Sclk;
--} ATOM_Ellesmere_PCIE_Record;
-+} ATOM_Polaris10_PCIE_Record;
- 
--typedef struct _ATOM_Ellesmere_PCIE_Table {
-+typedef struct _ATOM_Polaris10_PCIE_Table {
- 	UCHAR ucRevId;
- 	UCHAR ucNumEntries;                                         /* Number of entries. */
--	ATOM_Ellesmere_PCIE_Record entries[1];                      /* Dynamically allocate entries. */
--} ATOM_Ellesmere_PCIE_Table;
-+	ATOM_Polaris10_PCIE_Record entries[1];                      /* Dynamically allocate entries. */
-+} ATOM_Polaris10_PCIE_Table;
- 
- 
- typedef struct _ATOM_Tonga_MM_Dependency_Record {
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index ecbc43f..96a2787 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -493,8 +493,8 @@ static int get_pcie_table(
- 
- 		*pp_tonga_pcie_table = pcie_table;
- 	} else {
--		/* Ellesmere/Baffin and newer. */
--		const ATOM_Ellesmere_PCIE_Table *atom_pcie_table = (ATOM_Ellesmere_PCIE_Table *)pTable;
-+		/* Polaris10/Polaris11 and newer. */
-+		const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable;
- 		PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
- 			"Invalid PowerPlay Table!", return -1);
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
-deleted file mode 100644
-index 18fe230..0000000
---- a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h
-+++ /dev/null
-@@ -1,401 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef ELLESMERE_PP_SMC_H
--#define ELLESMERE_PP_SMC_H
--
--
--#pragma pack(push, 1)
--
--
--#define PPSMC_SWSTATE_FLAG_DC                           0x01
--#define PPSMC_SWSTATE_FLAG_UVD                          0x02
--#define PPSMC_SWSTATE_FLAG_VCE                          0x04
--
--#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
--#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
--#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
--
--#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
--#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
--#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
--
--#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
--
--#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
--#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
--
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
--#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
--
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
--#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
--
--
--#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
--#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
--#define PPSMC_DPM2FLAGS_OCP                             0x04
--
--
--#define PPSMC_DISPLAY_WATERMARK_LOW                     0
--#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
--
--
--#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
--#define PPSMC_STATEFLAG_POWERBOOST         0x02
--#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
--#define PPSMC_STATEFLAG_POWERSHIFT         0x08
--#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
--#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
--#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
--
--
--#define FDO_MODE_HARDWARE 0
--#define FDO_MODE_PIECE_WISE_LINEAR 1
--
--enum FAN_CONTROL {
--	FAN_CONTROL_FUZZY,
--	FAN_CONTROL_TABLE
--};
--
--
--#define PPSMC_Result_OK             ((uint16_t)0x01)
--#define PPSMC_Result_NoMore         ((uint16_t)0x02)
--
--#define PPSMC_Result_NotNow         ((uint16_t)0x03)
--#define PPSMC_Result_Failed         ((uint16_t)0xFF)
--#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
--#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
--
--typedef uint16_t PPSMC_Result;
--
--#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
--
--
--#define PPSMC_MSG_Halt                      ((uint16_t)0x10)
--#define PPSMC_MSG_Resume                    ((uint16_t)0x11)
--#define PPSMC_MSG_EnableDPMLevel            ((uint16_t)0x12)
--#define PPSMC_MSG_ZeroLevelsDisabled        ((uint16_t)0x13)
--#define PPSMC_MSG_OneLevelsDisabled         ((uint16_t)0x14)
--#define PPSMC_MSG_TwoLevelsDisabled         ((uint16_t)0x15)
--#define PPSMC_MSG_EnableThermalInterrupt    ((uint16_t)0x16)
--#define PPSMC_MSG_RunningOnAC               ((uint16_t)0x17)
--#define PPSMC_MSG_LevelUp                   ((uint16_t)0x18)
--#define PPSMC_MSG_LevelDown                 ((uint16_t)0x19)
--#define PPSMC_MSG_ResetDPMCounters          ((uint16_t)0x1a)
--#define PPSMC_MSG_SwitchToSwState           ((uint16_t)0x20)
--#define PPSMC_MSG_SwitchToSwStateLast       ((uint16_t)0x3f)
--#define PPSMC_MSG_SwitchToInitialState      ((uint16_t)0x40)
--#define PPSMC_MSG_NoForcedLevel             ((uint16_t)0x41)
--#define PPSMC_MSG_ForceHigh                 ((uint16_t)0x42)
--#define PPSMC_MSG_ForceMediumOrHigh         ((uint16_t)0x43)
--#define PPSMC_MSG_SwitchToMinimumPower      ((uint16_t)0x51)
--#define PPSMC_MSG_ResumeFromMinimumPower    ((uint16_t)0x52)
--#define PPSMC_MSG_EnableCac                 ((uint16_t)0x53)
--#define PPSMC_MSG_DisableCac                ((uint16_t)0x54)
--#define PPSMC_DPMStateHistoryStart          ((uint16_t)0x55)
--#define PPSMC_DPMStateHistoryStop           ((uint16_t)0x56)
--#define PPSMC_CACHistoryStart               ((uint16_t)0x57)
--#define PPSMC_CACHistoryStop                ((uint16_t)0x58)
--#define PPSMC_TDPClampingActive             ((uint16_t)0x59)
--#define PPSMC_TDPClampingInactive           ((uint16_t)0x5A)
--#define PPSMC_StartFanControl               ((uint16_t)0x5B)
--#define PPSMC_StopFanControl                ((uint16_t)0x5C)
--#define PPSMC_NoDisplay                     ((uint16_t)0x5D)
--#define PPSMC_HasDisplay                    ((uint16_t)0x5E)
--#define PPSMC_MSG_UVDPowerOFF               ((uint16_t)0x60)
--#define PPSMC_MSG_UVDPowerON                ((uint16_t)0x61)
--#define PPSMC_MSG_EnableULV                 ((uint16_t)0x62)
--#define PPSMC_MSG_DisableULV                ((uint16_t)0x63)
--#define PPSMC_MSG_EnterULV                  ((uint16_t)0x64)
--#define PPSMC_MSG_ExitULV                   ((uint16_t)0x65)
--#define PPSMC_PowerShiftActive              ((uint16_t)0x6A)
--#define PPSMC_PowerShiftInactive            ((uint16_t)0x6B)
--#define PPSMC_OCPActive                     ((uint16_t)0x6C)
--#define PPSMC_OCPInactive                   ((uint16_t)0x6D)
--#define PPSMC_CACLongTermAvgEnable          ((uint16_t)0x6E)
--#define PPSMC_CACLongTermAvgDisable         ((uint16_t)0x6F)
--#define PPSMC_MSG_InferredStateSweep_Start  ((uint16_t)0x70)
--#define PPSMC_MSG_InferredStateSweep_Stop   ((uint16_t)0x71)
--#define PPSMC_MSG_SwitchToLowestInfState    ((uint16_t)0x72)
--#define PPSMC_MSG_SwitchToNonInfState       ((uint16_t)0x73)
--#define PPSMC_MSG_AllStateSweep_Start       ((uint16_t)0x74)
--#define PPSMC_MSG_AllStateSweep_Stop        ((uint16_t)0x75)
--#define PPSMC_MSG_SwitchNextLowerInfState   ((uint16_t)0x76)
--#define PPSMC_MSG_SwitchNextHigherInfState  ((uint16_t)0x77)
--#define PPSMC_MSG_MclkRetrainingTest        ((uint16_t)0x78)
--#define PPSMC_MSG_ForceTDPClamping          ((uint16_t)0x79)
--#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint16_t)0x7A)
--#define PPSMC_MSG_CollectCAC_WeightCalib    ((uint16_t)0x7B)
--#define PPSMC_MSG_CollectCAC_SQonly         ((uint16_t)0x7C)
--#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
--
--#define PPSMC_MSG_ExtremitiesTest_Start     ((uint16_t)0x7E)
--#define PPSMC_MSG_ExtremitiesTest_Stop      ((uint16_t)0x7F)
--#define PPSMC_FlushDataCache                ((uint16_t)0x80)
--#define PPSMC_FlushInstrCache               ((uint16_t)0x81)
--
--#define PPSMC_MSG_SetEnabledLevels          ((uint16_t)0x82)
--#define PPSMC_MSG_SetForcedLevels           ((uint16_t)0x83)
--
--#define PPSMC_MSG_ResetToDefaults           ((uint16_t)0x84)
--
--#define PPSMC_MSG_SetForcedLevelsAndJump      ((uint16_t)0x85)
--#define PPSMC_MSG_SetCACHistoryMode           ((uint16_t)0x86)
--#define PPSMC_MSG_EnableDTE                   ((uint16_t)0x87)
--#define PPSMC_MSG_DisableDTE                  ((uint16_t)0x88)
--
--#define PPSMC_MSG_SmcSpaceSetAddress          ((uint16_t)0x89)
--#define PPSM_MSG_SmcSpaceWriteDWordInc        ((uint16_t)0x8A)
--#define PPSM_MSG_SmcSpaceWriteWordInc         ((uint16_t)0x8B)
--#define PPSM_MSG_SmcSpaceWriteByteInc         ((uint16_t)0x8C)
--
--#define PPSMC_MSG_BREAK                       ((uint16_t)0xF8)
--
--#define PPSMC_MSG_Test                        ((uint16_t) 0x100)
--#define PPSMC_MSG_DPM_Voltage_Pwrmgt          ((uint16_t) 0x101)
--#define PPSMC_MSG_DPM_Config                  ((uint16_t) 0x102)
--#define PPSMC_MSG_PM_Controller_Start         ((uint16_t) 0x103)
--#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
--#define PPSMC_MSG_PG_PowerDownSIMD            ((uint16_t) 0x105)
--#define PPSMC_MSG_PG_PowerUpSIMD              ((uint16_t) 0x106)
--#define PPSMC_MSG_PM_Controller_Stop          ((uint16_t) 0x107)
--#define PPSMC_MSG_PG_SIMD_Config              ((uint16_t) 0x108)
--#define PPSMC_MSG_Voltage_Cntl_Enable         ((uint16_t) 0x109)
--#define PPSMC_MSG_Thermal_Cntl_Enable         ((uint16_t) 0x10a)
--#define PPSMC_MSG_Reset_Service               ((uint16_t) 0x10b)
--#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x10e)
--#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0x10f)
--#define PPSMC_MSG_DPM_Disable_VCE_HS          ((uint16_t) 0x110)
--#define PPSMC_MSG_DPM_Enable_VCE_HS           ((uint16_t) 0x111)
--#define PPSMC_MSG_DPM_N_LevelsDisabled        ((uint16_t) 0x112)
--#define PPSMC_MSG_DCEPowerOFF                 ((uint16_t) 0x113)
--#define PPSMC_MSG_DCEPowerON                  ((uint16_t) 0x114)
--#define PPSMC_MSG_PCIE_DDIPowerDown           ((uint16_t) 0x117)
--#define PPSMC_MSG_PCIE_DDIPowerUp             ((uint16_t) 0x118)
--#define PPSMC_MSG_PCIE_CascadePLLPowerDown    ((uint16_t) 0x119)
--#define PPSMC_MSG_PCIE_CascadePLLPowerUp      ((uint16_t) 0x11a)
--#define PPSMC_MSG_SYSPLLPowerOff              ((uint16_t) 0x11b)
--#define PPSMC_MSG_SYSPLLPowerOn               ((uint16_t) 0x11c)
--#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
--#define PPSMC_MSG_DCE_AllowVoltageAdjustment  ((uint16_t) 0x11e)
--#define PPSMC_MSG_DISPLAYPHYStatusNotify      ((uint16_t) 0x11f)
--#define PPSMC_MSG_EnableBAPM                  ((uint16_t) 0x120)
--#define PPSMC_MSG_DisableBAPM                 ((uint16_t) 0x121)
--#define PPSMC_MSG_Spmi_Enable                 ((uint16_t) 0x122)
--#define PPSMC_MSG_Spmi_Timer                  ((uint16_t) 0x123)
--#define PPSMC_MSG_LCLK_DPM_Config             ((uint16_t) 0x124)
--#define PPSMC_MSG_VddNB_Request               ((uint16_t) 0x125)
--#define PPSMC_MSG_PCIE_DDIPhyPowerDown        ((uint32_t) 0x126)
--#define PPSMC_MSG_PCIE_DDIPhyPowerUp          ((uint32_t) 0x127)
--#define PPSMC_MSG_MCLKDPM_Config              ((uint16_t) 0x128)
--
--#define PPSMC_MSG_UVDDPM_Config               ((uint16_t) 0x129)
--#define PPSMC_MSG_VCEDPM_Config               ((uint16_t) 0x12A)
--#define PPSMC_MSG_ACPDPM_Config               ((uint16_t) 0x12B)
--#define PPSMC_MSG_SAMUDPM_Config              ((uint16_t) 0x12C)
--#define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
--#define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
--#define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
--#define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
--#define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
--#define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
--#define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
--#define PPSMC_MSG_SetTDPLimit                 ((uint16_t) 0x134)
--#define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
--#define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
--#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
--#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
--#define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
--#define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
--#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0x13b)
--#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0x13c)
--#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
--#define PPSMC_MSG_IOMMUPowerOFF               ((uint16_t) 0x13e)
--#define PPSMC_MSG_IOMMUPowerON                ((uint16_t) 0x13f)
--#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
--#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
--#define PPSMC_MSG_NBDPM_ForceNominal          ((uint16_t) 0x142)
--#define PPSMC_MSG_NBDPM_ForcePerformance      ((uint16_t) 0x143)
--#define PPSMC_MSG_NBDPM_UnForce               ((uint16_t) 0x144)
--#define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
--#define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
--#define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
--#define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
--#define PPSMC_MSG_EnableACDCGPIOInterrupt     ((uint16_t) 0x149)
--#define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
--#define PPSMC_MSG_SwitchToAC                  ((uint16_t) 0x14b)
--#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0x14c)
--#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x14d)
--
--#define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
--#define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
--#define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
--#define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
--#define PPSMC_MSG_LCLKDPM_Enable              ((uint16_t) 0x152)
--#define PPSMC_MSG_LCLKDPM_Disable             ((uint16_t) 0x153)
--#define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
--#define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
--#define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
--#define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
--#define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
--#define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
--#define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
--#define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
--#define PPSMC_MSG_LCLKDPM_SetEnabledMask      ((uint16_t) 0x15c)
--#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
--#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
--#define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
--#define PPSMC_MSG_MCLKDPM_GetEnabledMask      ((uint16_t) 0x160)
--#define PPSMC_MSG_LCLKDPM_GetEnabledMask      ((uint16_t) 0x161)
--#define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
--#define PPSMC_MSG_UVDDPM_GetEnabledMask       ((uint16_t) 0x163)
--#define PPSMC_MSG_SAMUDPM_GetEnabledMask      ((uint16_t) 0x164)
--#define PPSMC_MSG_ACPDPM_GetEnabledMask       ((uint16_t) 0x165)
--#define PPSMC_MSG_VCEDPM_GetEnabledMask       ((uint16_t) 0x166)
--#define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
--#define PPSMC_MSG_PCIeDPM_GetEnabledMask      ((uint16_t) 0x168)
--#define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
--#define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
--#define PPSMC_MSG_DPM_AutoRotate_Mode         ((uint16_t) 0x16b)
--#define PPSMC_MSG_DISPCLK_FROM_FCH            ((uint16_t) 0x16c)
--#define PPSMC_MSG_DISPCLK_FROM_DFS            ((uint16_t) 0x16d)
--#define PPSMC_MSG_DPREFCLK_FROM_FCH           ((uint16_t) 0x16e)
--#define PPSMC_MSG_DPREFCLK_FROM_DFS           ((uint16_t) 0x16f)
--#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
--#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
--#define PPSMC_MSG_SCLK_AutoDPM_ON             ((uint16_t) 0x172)
--#define PPSMC_MSG_MCLK_AutoDPM_ON             ((uint16_t) 0x173)
--#define PPSMC_MSG_LCLK_AutoDPM_ON             ((uint16_t) 0x174)
--#define PPSMC_MSG_UVD_AutoDPM_ON              ((uint16_t) 0x175)
--#define PPSMC_MSG_SAMU_AutoDPM_ON             ((uint16_t) 0x176)
--#define PPSMC_MSG_ACP_AutoDPM_ON              ((uint16_t) 0x177)
--#define PPSMC_MSG_VCE_AutoDPM_ON              ((uint16_t) 0x178)
--#define PPSMC_MSG_PCIe_AutoDPM_ON             ((uint16_t) 0x179)
--#define PPSMC_MSG_MASTER_AutoDPM_ON           ((uint16_t) 0x17a)
--#define PPSMC_MSG_MASTER_AutoDPM_OFF          ((uint16_t) 0x17b)
--#define PPSMC_MSG_DYNAMICDISPPHYPOWER         ((uint16_t) 0x17c)
--#define PPSMC_MSG_CAC_COLLECTION_ON           ((uint16_t) 0x17d)
--#define PPSMC_MSG_CAC_COLLECTION_OFF          ((uint16_t) 0x17e)
--#define PPSMC_MSG_CAC_CORRELATION_ON          ((uint16_t) 0x17f)
--#define PPSMC_MSG_CAC_CORRELATION_OFF         ((uint16_t) 0x180)
--#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON        ((uint16_t) 0x181)
--#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF       ((uint16_t) 0x182)
--#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT     ((uint16_t) 0x184)
--#define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
--#define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
--#define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
--#define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
--#define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
--#define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
--#define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
--#define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
--#define PPSMC_MSG_START_DRAM_LOGGING          ((uint16_t) 0x18D)
--#define PPSMC_MSG_STOP_DRAM_LOGGING           ((uint16_t) 0x18E)
--#define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
--#define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
--#define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
--#define PPSMC_MSG_DisableACDCGPIOInterrupt    ((uint16_t) 0x192)
--#define PPSMC_MSG_OverrideVoltageControl_SetVddc       ((uint16_t) 0x193)
--#define PPSMC_MSG_OverrideVoltageControl_SetVddci      ((uint16_t) 0x194)
--#define PPSMC_MSG_SetVidOffset_1              ((uint16_t) 0x195)
--#define PPSMC_MSG_SetVidOffset_2              ((uint16_t) 0x207)
--#define PPSMC_MSG_GetVidOffset_1              ((uint16_t) 0x196)
--#define PPSMC_MSG_GetVidOffset_2              ((uint16_t) 0x208)
--#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable    ((uint16_t) 0x197)
--#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable   ((uint16_t) 0x198)
--#define PPSMC_MSG_SetTjMax                    ((uint16_t) 0x199)
--#define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
--#define PPSMC_MSG_WaitForMclkSwitchFinish     ((uint16_t) 0x19B)
--#define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
--#define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
--
--#define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
--#define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
--#define PPSMC_MSG_API_GetSclkBusy             ((uint16_t) 0x202)
--#define PPSMC_MSG_API_GetMclkBusy             ((uint16_t) 0x203)
--#define PPSMC_MSG_API_GetAsicPower            ((uint16_t) 0x204)
--#define PPSMC_MSG_SetFanRpmMax                ((uint16_t) 0x205)
--#define PPSMC_MSG_SetFanSclkTarget            ((uint16_t) 0x206)
--#define PPSMC_MSG_SetFanMinPwm                ((uint16_t) 0x209)
--#define PPSMC_MSG_SetFanTemperatureTarget     ((uint16_t) 0x20A)
--
--#define PPSMC_MSG_BACO_StartMonitor           ((uint16_t) 0x240)
--#define PPSMC_MSG_BACO_Cancel                 ((uint16_t) 0x241)
--#define PPSMC_MSG_EnableVddGfx                ((uint16_t) 0x242)
--#define PPSMC_MSG_DisableVddGfx               ((uint16_t) 0x243)
--#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x244)
--#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x245)
--#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x246)
--
--#define PPSMC_MSG_DRV_DRAM_ADDR_HI            ((uint16_t) 0x250)
--#define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
--#define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
--#define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
--#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
--#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x255)
--#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI      ((uint16_t) 0x256)
--#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO      ((uint16_t) 0x257)
--#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI          ((uint16_t) 0x258)
--#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO          ((uint16_t) 0x259)
--#define PPSMC_MSG_LoadVBios                   ((uint16_t) 0x25A)
--#define PPSMC_MSG_GetUcodeVersion             ((uint16_t) 0x25B)
--#define DMCUSMC_MSG_PSREntry                  ((uint16_t) 0x25C)
--#define DMCUSMC_MSG_PSRExit                   ((uint16_t) 0x25D)
--#define PPSMC_MSG_EnableClockGatingFeature    ((uint16_t) 0x260)
--#define PPSMC_MSG_DisableClockGatingFeature   ((uint16_t) 0x261)
--#define PPSMC_MSG_IsDeviceRunning             ((uint16_t) 0x262)
--#define PPSMC_MSG_LoadMetaData                ((uint16_t) 0x263)
--#define PPSMC_MSG_TMON_AutoCaliberate_Enable  ((uint16_t) 0x264)
--#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
--#define PPSMC_MSG_GetTelemetry1Slope          ((uint16_t) 0x266)
--#define PPSMC_MSG_GetTelemetry1Offset         ((uint16_t) 0x267)
--#define PPSMC_MSG_GetTelemetry2Slope          ((uint16_t) 0x268)
--#define PPSMC_MSG_GetTelemetry2Offset         ((uint16_t) 0x269)
--#define PPSMC_MSG_EnableAvfs                  ((uint16_t) 0x26A)
--#define PPSMC_MSG_DisableAvfs                 ((uint16_t) 0x26B)
--
--#define PPSMC_MSG_PerformBtc                  ((uint16_t) 0x26C)
--#define PPSMC_MSG_VftTableIsValid             ((uint16_t) 0x275)
--#define PPSMC_MSG_UseNewGPIOScheme            ((uint16_t) 0x277)
--#define PPSMC_MSG_GetEnabledPsm               ((uint16_t) 0x400)
--#define PPSMC_MSG_AgmStartPsm                 ((uint16_t) 0x401)
--#define PPSMC_MSG_AgmReadPsm                  ((uint16_t) 0x402)
--#define PPSMC_MSG_AgmResetPsm                 ((uint16_t) 0x403)
--#define PPSMC_MSG_ReadVftCell                 ((uint16_t) 0x404)
--
--#define PPSMC_MSG_GFX_CU_PG_ENABLE            ((uint16_t) 0x280)
--#define PPSMC_MSG_GFX_CU_PG_DISABLE           ((uint16_t) 0x281)
--
--#define PPSMC_MSG_SetGpuPllDfsForSclk         ((uint16_t) 0x300)
--
--typedef uint16_t PPSMC_Msg;
--
--#define PPSMC_EVENT_STATUS_THERMAL          0x00000001
--#define PPSMC_EVENT_STATUS_REGULATORHOT     0x00000002
--#define PPSMC_EVENT_STATUS_DC               0x00000004
--
--#pragma pack(pop)
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
-deleted file mode 100644
-index 997811c..0000000
---- a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h
-+++ /dev/null
-@@ -1,10088 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--#ifndef _ELLESMERE_PWRVIRUS_H
--#define _ELLESMERE_PWRVIRUS_H
--
--#define mmSMC_IND_INDEX_11                              0x01AC
--#define mmSMC_IND_DATA_11                               0x01AD
--#define mmCP_HYP_MEC1_UCODE_ADDR	0xf81a
--#define mmCP_HYP_MEC1_UCODE_DATA	0xf81b
--#define mmCP_HYP_MEC2_UCODE_ADDR	0xf81c
--#define mmCP_HYP_MEC2_UCODE_DATA	0xf81d
--
--enum PWR_Command {
--	PwrCmdNull = 0,
--	PwrCmdWrite,
--	PwrCmdEnd,
--	PwrCmdMax
--};
--
--typedef enum PWR_Command PWR_Command;
--
--struct PWR_Command_Table {
--	PWR_Command        command;
--	uint32_t              data;
--	uint32_t reg;
--};
--
--typedef struct PWR_Command_Table PWR_Command_Table;
--
--
--#define PWR_VIRUS_TABLE_SIZE  10031
--
--static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
--	{ PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
--	{ PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
--	{ PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
--	{ PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL                              },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL                              },
--	{ PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL                                 },
--	{ PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE                          },
--	{ PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG                          },
--	{ PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
--	{ PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
--	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
--	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR                   },
--	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
--	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
--	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1                    },
--	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
--	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
--	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
--	{ PwrCmdEnd,   0x00000000, 0x00000000                                 },
--};
--
--
--#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
-new file mode 100644
-index 0000000..0c6a413
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
-@@ -0,0 +1,409 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef POLARIS10_PP_SMC_H
-+#define POLARIS10_PP_SMC_H
-+
-+
-+#pragma pack(push, 1)
-+
-+
-+#define PPSMC_SWSTATE_FLAG_DC                           0x01
-+#define PPSMC_SWSTATE_FLAG_UVD                          0x02
-+#define PPSMC_SWSTATE_FLAG_VCE                          0x04
-+
-+#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL             0x00
-+#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL             0x01
-+#define PPSMC_THERMAL_PROTECT_TYPE_NONE                 0xff
-+
-+#define PPSMC_SYSTEMFLAG_GPIO_DC                        0x01
-+#define PPSMC_SYSTEMFLAG_STEPVDDC                       0x02
-+#define PPSMC_SYSTEMFLAG_GDDR5                          0x04
-+
-+#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP               0x08
-+
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT                  0x10
-+#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG           0x20
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK              0x07
-+#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK     0x08
-+
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE   0x00
-+#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE  0x01
-+
-+
-+#define PPSMC_DPM2FLAGS_TDPCLMP                         0x01
-+#define PPSMC_DPM2FLAGS_PWRSHFT                         0x02
-+#define PPSMC_DPM2FLAGS_OCP                             0x04
-+
-+
-+#define PPSMC_DISPLAY_WATERMARK_LOW                     0
-+#define PPSMC_DISPLAY_WATERMARK_HIGH                    1
-+
-+
-+#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP    0x01
-+#define PPSMC_STATEFLAG_POWERBOOST         0x02
-+#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
-+#define PPSMC_STATEFLAG_POWERSHIFT         0x08
-+#define PPSMC_STATEFLAG_SLOW_READ_MARGIN   0x10
-+#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
-+#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS   0x40
-+
-+
-+#define FDO_MODE_HARDWARE 0
-+#define FDO_MODE_PIECE_WISE_LINEAR 1
-+
-+enum FAN_CONTROL {
-+	FAN_CONTROL_FUZZY,
-+	FAN_CONTROL_TABLE
-+};
-+
-+
-+#define PPSMC_Result_OK             ((uint16_t)0x01)
-+#define PPSMC_Result_NoMore         ((uint16_t)0x02)
-+
-+#define PPSMC_Result_NotNow         ((uint16_t)0x03)
-+#define PPSMC_Result_Failed         ((uint16_t)0xFF)
-+#define PPSMC_Result_UnknownCmd     ((uint16_t)0xFE)
-+#define PPSMC_Result_UnknownVT      ((uint16_t)0xFD)
-+
-+typedef uint16_t PPSMC_Result;
-+
-+#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
-+
-+
-+#define PPSMC_MSG_Halt                      ((uint16_t)0x10)
-+#define PPSMC_MSG_Resume                    ((uint16_t)0x11)
-+#define PPSMC_MSG_EnableDPMLevel            ((uint16_t)0x12)
-+#define PPSMC_MSG_ZeroLevelsDisabled        ((uint16_t)0x13)
-+#define PPSMC_MSG_OneLevelsDisabled         ((uint16_t)0x14)
-+#define PPSMC_MSG_TwoLevelsDisabled         ((uint16_t)0x15)
-+#define PPSMC_MSG_EnableThermalInterrupt    ((uint16_t)0x16)
-+#define PPSMC_MSG_RunningOnAC               ((uint16_t)0x17)
-+#define PPSMC_MSG_LevelUp                   ((uint16_t)0x18)
-+#define PPSMC_MSG_LevelDown                 ((uint16_t)0x19)
-+#define PPSMC_MSG_ResetDPMCounters          ((uint16_t)0x1a)
-+#define PPSMC_MSG_SwitchToSwState           ((uint16_t)0x20)
-+#define PPSMC_MSG_SwitchToSwStateLast       ((uint16_t)0x3f)
-+#define PPSMC_MSG_SwitchToInitialState      ((uint16_t)0x40)
-+#define PPSMC_MSG_NoForcedLevel             ((uint16_t)0x41)
-+#define PPSMC_MSG_ForceHigh                 ((uint16_t)0x42)
-+#define PPSMC_MSG_ForceMediumOrHigh         ((uint16_t)0x43)
-+#define PPSMC_MSG_SwitchToMinimumPower      ((uint16_t)0x51)
-+#define PPSMC_MSG_ResumeFromMinimumPower    ((uint16_t)0x52)
-+#define PPSMC_MSG_EnableCac                 ((uint16_t)0x53)
-+#define PPSMC_MSG_DisableCac                ((uint16_t)0x54)
-+#define PPSMC_DPMStateHistoryStart          ((uint16_t)0x55)
-+#define PPSMC_DPMStateHistoryStop           ((uint16_t)0x56)
-+#define PPSMC_CACHistoryStart               ((uint16_t)0x57)
-+#define PPSMC_CACHistoryStop                ((uint16_t)0x58)
-+#define PPSMC_TDPClampingActive             ((uint16_t)0x59)
-+#define PPSMC_TDPClampingInactive           ((uint16_t)0x5A)
-+#define PPSMC_StartFanControl               ((uint16_t)0x5B)
-+#define PPSMC_StopFanControl                ((uint16_t)0x5C)
-+#define PPSMC_NoDisplay                     ((uint16_t)0x5D)
-+#define PPSMC_HasDisplay                    ((uint16_t)0x5E)
-+#define PPSMC_MSG_UVDPowerOFF               ((uint16_t)0x60)
-+#define PPSMC_MSG_UVDPowerON                ((uint16_t)0x61)
-+#define PPSMC_MSG_EnableULV                 ((uint16_t)0x62)
-+#define PPSMC_MSG_DisableULV                ((uint16_t)0x63)
-+#define PPSMC_MSG_EnterULV                  ((uint16_t)0x64)
-+#define PPSMC_MSG_ExitULV                   ((uint16_t)0x65)
-+#define PPSMC_PowerShiftActive              ((uint16_t)0x6A)
-+#define PPSMC_PowerShiftInactive            ((uint16_t)0x6B)
-+#define PPSMC_OCPActive                     ((uint16_t)0x6C)
-+#define PPSMC_OCPInactive                   ((uint16_t)0x6D)
-+#define PPSMC_CACLongTermAvgEnable          ((uint16_t)0x6E)
-+#define PPSMC_CACLongTermAvgDisable         ((uint16_t)0x6F)
-+#define PPSMC_MSG_InferredStateSweep_Start  ((uint16_t)0x70)
-+#define PPSMC_MSG_InferredStateSweep_Stop   ((uint16_t)0x71)
-+#define PPSMC_MSG_SwitchToLowestInfState    ((uint16_t)0x72)
-+#define PPSMC_MSG_SwitchToNonInfState       ((uint16_t)0x73)
-+#define PPSMC_MSG_AllStateSweep_Start       ((uint16_t)0x74)
-+#define PPSMC_MSG_AllStateSweep_Stop        ((uint16_t)0x75)
-+#define PPSMC_MSG_SwitchNextLowerInfState   ((uint16_t)0x76)
-+#define PPSMC_MSG_SwitchNextHigherInfState  ((uint16_t)0x77)
-+#define PPSMC_MSG_MclkRetrainingTest        ((uint16_t)0x78)
-+#define PPSMC_MSG_ForceTDPClamping          ((uint16_t)0x79)
-+#define PPSMC_MSG_CollectCAC_PowerCorreln   ((uint16_t)0x7A)
-+#define PPSMC_MSG_CollectCAC_WeightCalib    ((uint16_t)0x7B)
-+#define PPSMC_MSG_CollectCAC_SQonly         ((uint16_t)0x7C)
-+#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
-+
-+#define PPSMC_MSG_ExtremitiesTest_Start     ((uint16_t)0x7E)
-+#define PPSMC_MSG_ExtremitiesTest_Stop      ((uint16_t)0x7F)
-+#define PPSMC_FlushDataCache                ((uint16_t)0x80)
-+#define PPSMC_FlushInstrCache               ((uint16_t)0x81)
-+
-+#define PPSMC_MSG_SetEnabledLevels          ((uint16_t)0x82)
-+#define PPSMC_MSG_SetForcedLevels           ((uint16_t)0x83)
-+
-+#define PPSMC_MSG_ResetToDefaults           ((uint16_t)0x84)
-+
-+#define PPSMC_MSG_SetForcedLevelsAndJump      ((uint16_t)0x85)
-+#define PPSMC_MSG_SetCACHistoryMode           ((uint16_t)0x86)
-+#define PPSMC_MSG_EnableDTE                   ((uint16_t)0x87)
-+#define PPSMC_MSG_DisableDTE                  ((uint16_t)0x88)
-+
-+#define PPSMC_MSG_SmcSpaceSetAddress          ((uint16_t)0x89)
-+#define PPSM_MSG_SmcSpaceWriteDWordInc        ((uint16_t)0x8A)
-+#define PPSM_MSG_SmcSpaceWriteWordInc         ((uint16_t)0x8B)
-+#define PPSM_MSG_SmcSpaceWriteByteInc         ((uint16_t)0x8C)
-+
-+#define PPSMC_MSG_BREAK                       ((uint16_t)0xF8)
-+
-+#define PPSMC_MSG_Test                        ((uint16_t) 0x100)
-+#define PPSMC_MSG_DPM_Voltage_Pwrmgt          ((uint16_t) 0x101)
-+#define PPSMC_MSG_DPM_Config                  ((uint16_t) 0x102)
-+#define PPSMC_MSG_PM_Controller_Start         ((uint16_t) 0x103)
-+#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)
-+#define PPSMC_MSG_PG_PowerDownSIMD            ((uint16_t) 0x105)
-+#define PPSMC_MSG_PG_PowerUpSIMD              ((uint16_t) 0x106)
-+#define PPSMC_MSG_PM_Controller_Stop          ((uint16_t) 0x107)
-+#define PPSMC_MSG_PG_SIMD_Config              ((uint16_t) 0x108)
-+#define PPSMC_MSG_Voltage_Cntl_Enable         ((uint16_t) 0x109)
-+#define PPSMC_MSG_Thermal_Cntl_Enable         ((uint16_t) 0x10a)
-+#define PPSMC_MSG_Reset_Service               ((uint16_t) 0x10b)
-+#define PPSMC_MSG_VCEPowerOFF                 ((uint16_t) 0x10e)
-+#define PPSMC_MSG_VCEPowerON                  ((uint16_t) 0x10f)
-+#define PPSMC_MSG_DPM_Disable_VCE_HS          ((uint16_t) 0x110)
-+#define PPSMC_MSG_DPM_Enable_VCE_HS           ((uint16_t) 0x111)
-+#define PPSMC_MSG_DPM_N_LevelsDisabled        ((uint16_t) 0x112)
-+#define PPSMC_MSG_DCEPowerOFF                 ((uint16_t) 0x113)
-+#define PPSMC_MSG_DCEPowerON                  ((uint16_t) 0x114)
-+#define PPSMC_MSG_PCIE_DDIPowerDown           ((uint16_t) 0x117)
-+#define PPSMC_MSG_PCIE_DDIPowerUp             ((uint16_t) 0x118)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerDown    ((uint16_t) 0x119)
-+#define PPSMC_MSG_PCIE_CascadePLLPowerUp      ((uint16_t) 0x11a)
-+#define PPSMC_MSG_SYSPLLPowerOff              ((uint16_t) 0x11b)
-+#define PPSMC_MSG_SYSPLLPowerOn               ((uint16_t) 0x11c)
-+#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
-+#define PPSMC_MSG_DCE_AllowVoltageAdjustment  ((uint16_t) 0x11e)
-+#define PPSMC_MSG_DISPLAYPHYStatusNotify      ((uint16_t) 0x11f)
-+#define PPSMC_MSG_EnableBAPM                  ((uint16_t) 0x120)
-+#define PPSMC_MSG_DisableBAPM                 ((uint16_t) 0x121)
-+#define PPSMC_MSG_Spmi_Enable                 ((uint16_t) 0x122)
-+#define PPSMC_MSG_Spmi_Timer                  ((uint16_t) 0x123)
-+#define PPSMC_MSG_LCLK_DPM_Config             ((uint16_t) 0x124)
-+#define PPSMC_MSG_VddNB_Request               ((uint16_t) 0x125)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerDown        ((uint32_t) 0x126)
-+#define PPSMC_MSG_PCIE_DDIPhyPowerUp          ((uint32_t) 0x127)
-+#define PPSMC_MSG_MCLKDPM_Config              ((uint16_t) 0x128)
-+
-+#define PPSMC_MSG_UVDDPM_Config               ((uint16_t) 0x129)
-+#define PPSMC_MSG_VCEDPM_Config               ((uint16_t) 0x12A)
-+#define PPSMC_MSG_ACPDPM_Config               ((uint16_t) 0x12B)
-+#define PPSMC_MSG_SAMUDPM_Config              ((uint16_t) 0x12C)
-+#define PPSMC_MSG_UVDDPM_SetEnabledMask       ((uint16_t) 0x12D)
-+#define PPSMC_MSG_VCEDPM_SetEnabledMask       ((uint16_t) 0x12E)
-+#define PPSMC_MSG_ACPDPM_SetEnabledMask       ((uint16_t) 0x12F)
-+#define PPSMC_MSG_SAMUDPM_SetEnabledMask      ((uint16_t) 0x130)
-+#define PPSMC_MSG_MCLKDPM_ForceState          ((uint16_t) 0x131)
-+#define PPSMC_MSG_MCLKDPM_NoForcedLevel       ((uint16_t) 0x132)
-+#define PPSMC_MSG_Thermal_Cntl_Disable        ((uint16_t) 0x133)
-+#define PPSMC_MSG_SetTDPLimit                 ((uint16_t) 0x134)
-+#define PPSMC_MSG_Voltage_Cntl_Disable        ((uint16_t) 0x135)
-+#define PPSMC_MSG_PCIeDPM_Enable              ((uint16_t) 0x136)
-+#define PPSMC_MSG_ACPPowerOFF                 ((uint16_t) 0x137)
-+#define PPSMC_MSG_ACPPowerON                  ((uint16_t) 0x138)
-+#define PPSMC_MSG_SAMPowerOFF                 ((uint16_t) 0x139)
-+#define PPSMC_MSG_SAMPowerON                  ((uint16_t) 0x13a)
-+#define PPSMC_MSG_SDMAPowerOFF                ((uint16_t) 0x13b)
-+#define PPSMC_MSG_SDMAPowerON                 ((uint16_t) 0x13c)
-+#define PPSMC_MSG_PCIeDPM_Disable             ((uint16_t) 0x13d)
-+#define PPSMC_MSG_IOMMUPowerOFF               ((uint16_t) 0x13e)
-+#define PPSMC_MSG_IOMMUPowerON                ((uint16_t) 0x13f)
-+#define PPSMC_MSG_NBDPM_Enable                ((uint16_t) 0x140)
-+#define PPSMC_MSG_NBDPM_Disable               ((uint16_t) 0x141)
-+#define PPSMC_MSG_NBDPM_ForceNominal          ((uint16_t) 0x142)
-+#define PPSMC_MSG_NBDPM_ForcePerformance      ((uint16_t) 0x143)
-+#define PPSMC_MSG_NBDPM_UnForce               ((uint16_t) 0x144)
-+#define PPSMC_MSG_SCLKDPM_SetEnabledMask      ((uint16_t) 0x145)
-+#define PPSMC_MSG_MCLKDPM_SetEnabledMask      ((uint16_t) 0x146)
-+#define PPSMC_MSG_PCIeDPM_ForceLevel          ((uint16_t) 0x147)
-+#define PPSMC_MSG_PCIeDPM_UnForceLevel        ((uint16_t) 0x148)
-+#define PPSMC_MSG_EnableACDCGPIOInterrupt     ((uint16_t) 0x149)
-+#define PPSMC_MSG_EnableVRHotGPIOInterrupt    ((uint16_t) 0x14a)
-+#define PPSMC_MSG_SwitchToAC                  ((uint16_t) 0x14b)
-+#define PPSMC_MSG_XDMAPowerOFF                ((uint16_t) 0x14c)
-+#define PPSMC_MSG_XDMAPowerON                 ((uint16_t) 0x14d)
-+
-+#define PPSMC_MSG_DPM_Enable                  ((uint16_t) 0x14e)
-+#define PPSMC_MSG_DPM_Disable                 ((uint16_t) 0x14f)
-+#define PPSMC_MSG_MCLKDPM_Enable              ((uint16_t) 0x150)
-+#define PPSMC_MSG_MCLKDPM_Disable             ((uint16_t) 0x151)
-+#define PPSMC_MSG_LCLKDPM_Enable              ((uint16_t) 0x152)
-+#define PPSMC_MSG_LCLKDPM_Disable             ((uint16_t) 0x153)
-+#define PPSMC_MSG_UVDDPM_Enable               ((uint16_t) 0x154)
-+#define PPSMC_MSG_UVDDPM_Disable              ((uint16_t) 0x155)
-+#define PPSMC_MSG_SAMUDPM_Enable              ((uint16_t) 0x156)
-+#define PPSMC_MSG_SAMUDPM_Disable             ((uint16_t) 0x157)
-+#define PPSMC_MSG_ACPDPM_Enable               ((uint16_t) 0x158)
-+#define PPSMC_MSG_ACPDPM_Disable              ((uint16_t) 0x159)
-+#define PPSMC_MSG_VCEDPM_Enable               ((uint16_t) 0x15a)
-+#define PPSMC_MSG_VCEDPM_Disable              ((uint16_t) 0x15b)
-+#define PPSMC_MSG_LCLKDPM_SetEnabledMask      ((uint16_t) 0x15c)
-+#define PPSMC_MSG_DPM_FPS_Mode                ((uint16_t) 0x15d)
-+#define PPSMC_MSG_DPM_Activity_Mode           ((uint16_t) 0x15e)
-+#define PPSMC_MSG_VddC_Request                ((uint16_t) 0x15f)
-+#define PPSMC_MSG_MCLKDPM_GetEnabledMask      ((uint16_t) 0x160)
-+#define PPSMC_MSG_LCLKDPM_GetEnabledMask      ((uint16_t) 0x161)
-+#define PPSMC_MSG_SCLKDPM_GetEnabledMask      ((uint16_t) 0x162)
-+#define PPSMC_MSG_UVDDPM_GetEnabledMask       ((uint16_t) 0x163)
-+#define PPSMC_MSG_SAMUDPM_GetEnabledMask      ((uint16_t) 0x164)
-+#define PPSMC_MSG_ACPDPM_GetEnabledMask       ((uint16_t) 0x165)
-+#define PPSMC_MSG_VCEDPM_GetEnabledMask       ((uint16_t) 0x166)
-+#define PPSMC_MSG_PCIeDPM_SetEnabledMask      ((uint16_t) 0x167)
-+#define PPSMC_MSG_PCIeDPM_GetEnabledMask      ((uint16_t) 0x168)
-+#define PPSMC_MSG_TDCLimitEnable              ((uint16_t) 0x169)
-+#define PPSMC_MSG_TDCLimitDisable             ((uint16_t) 0x16a)
-+#define PPSMC_MSG_DPM_AutoRotate_Mode         ((uint16_t) 0x16b)
-+#define PPSMC_MSG_DISPCLK_FROM_FCH            ((uint16_t) 0x16c)
-+#define PPSMC_MSG_DISPCLK_FROM_DFS            ((uint16_t) 0x16d)
-+#define PPSMC_MSG_DPREFCLK_FROM_FCH           ((uint16_t) 0x16e)
-+#define PPSMC_MSG_DPREFCLK_FROM_DFS           ((uint16_t) 0x16f)
-+#define PPSMC_MSG_PmStatusLogStart            ((uint16_t) 0x170)
-+#define PPSMC_MSG_PmStatusLogSample           ((uint16_t) 0x171)
-+#define PPSMC_MSG_SCLK_AutoDPM_ON             ((uint16_t) 0x172)
-+#define PPSMC_MSG_MCLK_AutoDPM_ON             ((uint16_t) 0x173)
-+#define PPSMC_MSG_LCLK_AutoDPM_ON             ((uint16_t) 0x174)
-+#define PPSMC_MSG_UVD_AutoDPM_ON              ((uint16_t) 0x175)
-+#define PPSMC_MSG_SAMU_AutoDPM_ON             ((uint16_t) 0x176)
-+#define PPSMC_MSG_ACP_AutoDPM_ON              ((uint16_t) 0x177)
-+#define PPSMC_MSG_VCE_AutoDPM_ON              ((uint16_t) 0x178)
-+#define PPSMC_MSG_PCIe_AutoDPM_ON             ((uint16_t) 0x179)
-+#define PPSMC_MSG_MASTER_AutoDPM_ON           ((uint16_t) 0x17a)
-+#define PPSMC_MSG_MASTER_AutoDPM_OFF          ((uint16_t) 0x17b)
-+#define PPSMC_MSG_DYNAMICDISPPHYPOWER         ((uint16_t) 0x17c)
-+#define PPSMC_MSG_CAC_COLLECTION_ON           ((uint16_t) 0x17d)
-+#define PPSMC_MSG_CAC_COLLECTION_OFF          ((uint16_t) 0x17e)
-+#define PPSMC_MSG_CAC_CORRELATION_ON          ((uint16_t) 0x17f)
-+#define PPSMC_MSG_CAC_CORRELATION_OFF         ((uint16_t) 0x180)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON        ((uint16_t) 0x181)
-+#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF       ((uint16_t) 0x182)
-+#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT     ((uint16_t) 0x184)
-+#define PPSMC_MSG_PkgPwrLimitEnable           ((uint16_t) 0x185)
-+#define PPSMC_MSG_PkgPwrLimitDisable          ((uint16_t) 0x186)
-+#define PPSMC_MSG_PkgPwrSetLimit              ((uint16_t) 0x187)
-+#define PPSMC_MSG_OverDriveSetTargetTdp       ((uint16_t) 0x188)
-+#define PPSMC_MSG_SCLKDPM_FreezeLevel         ((uint16_t) 0x189)
-+#define PPSMC_MSG_SCLKDPM_UnfreezeLevel       ((uint16_t) 0x18A)
-+#define PPSMC_MSG_MCLKDPM_FreezeLevel         ((uint16_t) 0x18B)
-+#define PPSMC_MSG_MCLKDPM_UnfreezeLevel       ((uint16_t) 0x18C)
-+#define PPSMC_MSG_START_DRAM_LOGGING          ((uint16_t) 0x18D)
-+#define PPSMC_MSG_STOP_DRAM_LOGGING           ((uint16_t) 0x18E)
-+#define PPSMC_MSG_MASTER_DeepSleep_ON         ((uint16_t) 0x18F)
-+#define PPSMC_MSG_MASTER_DeepSleep_OFF        ((uint16_t) 0x190)
-+#define PPSMC_MSG_Remove_DC_Clamp             ((uint16_t) 0x191)
-+#define PPSMC_MSG_DisableACDCGPIOInterrupt    ((uint16_t) 0x192)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddc       ((uint16_t) 0x193)
-+#define PPSMC_MSG_OverrideVoltageControl_SetVddci      ((uint16_t) 0x194)
-+#define PPSMC_MSG_SetVidOffset_1              ((uint16_t) 0x195)
-+#define PPSMC_MSG_SetVidOffset_2              ((uint16_t) 0x207)
-+#define PPSMC_MSG_GetVidOffset_1              ((uint16_t) 0x196)
-+#define PPSMC_MSG_GetVidOffset_2              ((uint16_t) 0x208)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable    ((uint16_t) 0x197)
-+#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable   ((uint16_t) 0x198)
-+#define PPSMC_MSG_SetTjMax                    ((uint16_t) 0x199)
-+#define PPSMC_MSG_SetFanPwmMax                ((uint16_t) 0x19A)
-+#define PPSMC_MSG_WaitForMclkSwitchFinish     ((uint16_t) 0x19B)
-+#define PPSMC_MSG_ENABLE_THERMAL_DPM          ((uint16_t) 0x19C)
-+#define PPSMC_MSG_DISABLE_THERMAL_DPM         ((uint16_t) 0x19D)
-+
-+#define PPSMC_MSG_API_GetSclkFrequency        ((uint16_t) 0x200)
-+#define PPSMC_MSG_API_GetMclkFrequency        ((uint16_t) 0x201)
-+#define PPSMC_MSG_API_GetSclkBusy             ((uint16_t) 0x202)
-+#define PPSMC_MSG_API_GetMclkBusy             ((uint16_t) 0x203)
-+#define PPSMC_MSG_API_GetAsicPower            ((uint16_t) 0x204)
-+#define PPSMC_MSG_SetFanRpmMax                ((uint16_t) 0x205)
-+#define PPSMC_MSG_SetFanSclkTarget            ((uint16_t) 0x206)
-+#define PPSMC_MSG_SetFanMinPwm                ((uint16_t) 0x209)
-+#define PPSMC_MSG_SetFanTemperatureTarget     ((uint16_t) 0x20A)
-+
-+#define PPSMC_MSG_BACO_StartMonitor           ((uint16_t) 0x240)
-+#define PPSMC_MSG_BACO_Cancel                 ((uint16_t) 0x241)
-+#define PPSMC_MSG_EnableVddGfx                ((uint16_t) 0x242)
-+#define PPSMC_MSG_DisableVddGfx               ((uint16_t) 0x243)
-+#define PPSMC_MSG_UcodeAddressLow             ((uint16_t) 0x244)
-+#define PPSMC_MSG_UcodeAddressHigh            ((uint16_t) 0x245)
-+#define PPSMC_MSG_UcodeLoadStatus             ((uint16_t) 0x246)
-+
-+#define PPSMC_MSG_DRV_DRAM_ADDR_HI            ((uint16_t) 0x250)
-+#define PPSMC_MSG_DRV_DRAM_ADDR_LO            ((uint16_t) 0x251)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_HI            ((uint16_t) 0x252)
-+#define PPSMC_MSG_SMU_DRAM_ADDR_LO            ((uint16_t) 0x253)
-+#define PPSMC_MSG_LoadUcodes                  ((uint16_t) 0x254)
-+#define PPSMC_MSG_PowerStateNotify            ((uint16_t) 0x255)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI      ((uint16_t) 0x256)
-+#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO      ((uint16_t) 0x257)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI          ((uint16_t) 0x258)
-+#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO          ((uint16_t) 0x259)
-+#define PPSMC_MSG_LoadVBios                   ((uint16_t) 0x25A)
-+#define PPSMC_MSG_GetUcodeVersion             ((uint16_t) 0x25B)
-+#define DMCUSMC_MSG_PSREntry                  ((uint16_t) 0x25C)
-+#define DMCUSMC_MSG_PSRExit                   ((uint16_t) 0x25D)
-+#define PPSMC_MSG_EnableClockGatingFeature    ((uint16_t) 0x260)
-+#define PPSMC_MSG_DisableClockGatingFeature   ((uint16_t) 0x261)
-+#define PPSMC_MSG_IsDeviceRunning             ((uint16_t) 0x262)
-+#define PPSMC_MSG_LoadMetaData                ((uint16_t) 0x263)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Enable  ((uint16_t) 0x264)
-+#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
-+#define PPSMC_MSG_GetTelemetry1Slope          ((uint16_t) 0x266)
-+#define PPSMC_MSG_GetTelemetry1Offset         ((uint16_t) 0x267)
-+#define PPSMC_MSG_GetTelemetry2Slope          ((uint16_t) 0x268)
-+#define PPSMC_MSG_GetTelemetry2Offset         ((uint16_t) 0x269)
-+#define PPSMC_MSG_EnableAvfs                  ((uint16_t) 0x26A)
-+#define PPSMC_MSG_DisableAvfs                 ((uint16_t) 0x26B)
-+
-+#define PPSMC_MSG_PerformBtc                  ((uint16_t) 0x26C)
-+#define PPSMC_MSG_VftTableIsValid             ((uint16_t) 0x275)
-+#define PPSMC_MSG_UseNewGPIOScheme            ((uint16_t) 0x277)
-+#define PPSMC_MSG_GetEnabledPsm               ((uint16_t) 0x400)
-+#define PPSMC_MSG_AgmStartPsm                 ((uint16_t) 0x401)
-+#define PPSMC_MSG_AgmReadPsm                  ((uint16_t) 0x402)
-+#define PPSMC_MSG_AgmResetPsm                 ((uint16_t) 0x403)
-+#define PPSMC_MSG_ReadVftCell                 ((uint16_t) 0x404)
-+
-+#define PPSMC_MSG_GFX_CU_PG_ENABLE            ((uint16_t) 0x280)
-+#define PPSMC_MSG_GFX_CU_PG_DISABLE           ((uint16_t) 0x281)
-+#define PPSMC_MSG_GetCurrPkgPwr               ((uint16_t) 0x282)
-+
-+#define PPSMC_MSG_SetGpuPllDfsForSclk         ((uint16_t) 0x300)
-+#define PPSMC_MSG_Didt_Block_Function		  ((uint16_t) 0x301)
-+
-+#define PPSMC_MSG_SecureSRBMWrite             ((uint16_t) 0x600)
-+#define PPSMC_MSG_SecureSRBMRead              ((uint16_t) 0x601)
-+#define PPSMC_MSG_SetAddress                  ((uint16_t) 0x800)
-+#define PPSMC_MSG_GetData                     ((uint16_t) 0x801)
-+#define PPSMC_MSG_SetData                     ((uint16_t) 0x802)
-+
-+typedef uint16_t PPSMC_Msg;
-+
-+#define PPSMC_EVENT_STATUS_THERMAL          0x00000001
-+#define PPSMC_EVENT_STATUS_REGULATORHOT     0x00000002
-+#define PPSMC_EVENT_STATUS_DC               0x00000004
-+
-+#pragma pack(pop)
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
-new file mode 100644
-index 0000000..933103e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
-@@ -0,0 +1,10088 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _POLARIS10_PWRVIRUS_H
-+#define _POLARIS10_PWRVIRUS_H
-+
-+#define mmSMC_IND_INDEX_11                              0x01AC
-+#define mmSMC_IND_DATA_11                               0x01AD
-+#define mmCP_HYP_MEC1_UCODE_ADDR	0xf81a
-+#define mmCP_HYP_MEC1_UCODE_DATA	0xf81b
-+#define mmCP_HYP_MEC2_UCODE_ADDR	0xf81c
-+#define mmCP_HYP_MEC2_UCODE_DATA	0xf81d
-+
-+enum PWR_Command {
-+	PwrCmdNull = 0,
-+	PwrCmdWrite,
-+	PwrCmdEnd,
-+	PwrCmdMax
-+};
-+
-+typedef enum PWR_Command PWR_Command;
-+
-+struct PWR_Command_Table {
-+	PWR_Command        command;
-+	uint32_t              data;
-+	uint32_t reg;
-+};
-+
-+typedef struct PWR_Command_Table PWR_Command_Table;
-+
-+
-+#define PWR_VIRUS_TABLE_SIZE  10031
-+
-+static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
-+	{ PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
-+	{ PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
-+	{ PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
-+	{ PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL                              },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL                              },
-+	{ PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL                                 },
-+	{ PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE                          },
-+	{ PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG                          },
-+	{ PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
-+	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR                   },
-+	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
-+	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO                           },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
-+	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR                         },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
-+	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1                    },
-+	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
-+	{ PwrCmdEnd,   0x00000000, 0x00000000                                 },
-+};
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-index f816262..f6a7591 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-@@ -705,6 +705,7 @@ struct SMU7_Discrete_Pm_Status_Table {
- 	uint16_t Sclk_dpm_residency[8];
- 	uint16_t Uvd_dpm_residency[8];
- 	uint16_t Vce_dpm_residency[8];
-+	uint16_t Mclk_dpm_residency[4];
- 
- 	uint32_t P_vddci_acc;
- 	uint32_t P_vddr1_acc;
-@@ -779,6 +780,47 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
- #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
- #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
- 
-+// DIDT Defines
-+#define SQ_Enable_MASK 0x1
-+#define SQ_IR_MASK 0x2
-+#define SQ_PCC_MASK 0x4
-+#define SQ_EDC_MASK 0x8
-+
-+#define TCP_Enable_MASK 0x100
-+#define TCP_IR_MASK 0x200
-+#define TCP_PCC_MASK 0x400
-+#define TCP_EDC_MASK 0x800
-+
-+#define TD_Enable_MASK 0x10000
-+#define TD_IR_MASK 0x20000
-+#define TD_PCC_MASK 0x40000
-+#define TD_EDC_MASK 0x80000
-+
-+#define DB_Enable_MASK 0x1000000
-+#define DB_IR_MASK 0x2000000
-+#define DB_PCC_MASK 0x4000000 
-+#define DB_EDC_MASK 0x8000000
-+
-+#define SQ_Enable_SHIFT 0
-+#define SQ_IR_SHIFT 1
-+#define SQ_PCC_SHIFT 2
-+#define SQ_EDC_SHIFT 3
-+
-+#define TCP_Enable_SHIFT 8
-+#define TCP_IR_SHIFT 9
-+#define TCP_PCC_SHIFT 10
-+#define TCP_EDC_SHIFT 11
-+
-+#define TD_Enable_SHIFT 16
-+#define TD_IR_SHIFT 17
-+#define TD_PCC_SHIFT 18
-+#define TD_EDC_SHIFT 19
-+
-+#define DB_Enable_SHIFT 24
-+#define DB_IR_SHIFT 25
-+#define DB_PCC_SHIFT 26 
-+#define DB_EDC_SHIFT 27
-+
- #pragma pack(pop)
- 
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-index 4f751e5..f10fb64 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'smu manager' sub-component of powerplay.
- # It provides the smu management services for the driver.
- 
--SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o
-+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o polaris10_smumgr.o
- 
- AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-deleted file mode 100644
-index 6395065..0000000
---- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c
-+++ /dev/null
-@@ -1,983 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#include "smumgr.h"
--#include "smu74.h"
--#include "smu_ucode_xfer_vi.h"
--#include "ellesmere_smumgr.h"
--#include "smu74_discrete.h"
--#include "smu/smu_7_1_3_d.h"
--#include "smu/smu_7_1_3_sh_mask.h"
--#include "gmc/gmc_8_1_d.h"
--#include "gmc/gmc_8_1_sh_mask.h"
--#include "oss/oss_3_0_d.h"
--#include "gca/gfx_8_0_d.h"
--#include "bif/bif_5_0_d.h"
--#include "bif/bif_5_0_sh_mask.h"
--#include "ellesmere_pwrvirus.h"
--#include "ppatomctrl.h"
--#include "pp_debug.h"
--#include "cgs_common.h"
--
--#define ELLESMERE_SMC_SIZE 0x20000
--#define VOLTAGE_SCALE 4
--
--/* Microcode file is stored in this buffer */
--#define BUFFER_SIZE                 80000
--#define MAX_STRING_SIZE             15
--#define BUFFER_SIZETWO              131072  /* 128 *1024 */
--
--#define SMC_RAM_END 0x40000
--
--SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = {
--	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
--	/* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
--	{ 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } },
--	{ 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
--};
--
--SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
--							0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
--
--/**
--* Set the address for reading/writing the SMC SRAM space.
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    smcAddress the address in the SMC RAM to access.
--*/
--static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
--{
--	PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
--	PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
--
--	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
--
--	return 0;
--}
--
--/**
--* Copy bytes from SMC RAM space into driver memory.
--*
--* @param    smumgr  the address of the powerplay SMU manager.
--* @param    smc_start_address the start address in the SMC RAM to copy bytes from
--* @param    src the byte array to copy the bytes to.
--* @param    byte_count the number of bytes to copy.
--*/
--int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
--{
--	uint32_t data;
--	uint32_t addr;
--	uint8_t *dest_byte;
--	uint8_t i, data_byte[4] = {0};
--	uint32_t *pdata = (uint32_t *)&data_byte;
--
--	PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;);
--	PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
--
--	addr = smc_start_address;
--
--	while (byte_count >= 4) {
--		ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
--
--		*dest = PP_SMC_TO_HOST_UL(data);
--
--		dest += 1;
--		byte_count -= 4;
--		addr += 4;
--	}
--
--	if (byte_count) {
--		ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
--		*pdata = PP_SMC_TO_HOST_UL(data);
--	/* Cast dest into byte type in dest_byte.  This way, we don't overflow if the allocated memory is not 4-byte aligned. */
--		dest_byte = (uint8_t *)dest;
--		for (i = 0; i < byte_count; i++)
--			dest_byte[i] = data_byte[i];
--	}
--
--	return 0;
--}
--
--/**
--* Copy bytes from an array into the SMC RAM space.
--*
--* @param    pSmuMgr  the address of the powerplay SMU manager.
--* @param    smc_start_address the start address in the SMC RAM to copy bytes to.
--* @param    src the byte array to copy the bytes from.
--* @param    byte_count the number of bytes to copy.
--*/
--int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
--				const uint8_t *src, uint32_t byte_count, uint32_t limit)
--{
--	int result;
--	uint32_t data = 0;
--	uint32_t original_data;
--	uint32_t addr = 0;
--	uint32_t extra_shift;
--
--	PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1);
--	PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
--
--	addr = smc_start_address;
--
--	while (byte_count >= 4) {
--	/* Bytes are written into the SMC addres space with the MSB first. */
--		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
--
--		result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
--
--		if (0 != result)
--			return result;
--
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
--
--		src += 4;
--		byte_count -= 4;
--		addr += 4;
--	}
--
--	if (0 != byte_count) {
--
--		data = 0;
--
--		result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
--
--		if (0 != result)
--			return result;
--
--
--		original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
--
--		extra_shift = 8 * (4 - byte_count);
--
--		while (byte_count > 0) {
--			/* Bytes are written into the SMC addres space with the MSB first. */
--			data = (0x100 * data) + *src++;
--			byte_count--;
--		}
--
--		data <<= extra_shift;
--
--		data |= (original_data & ~((~0UL) << extra_shift));
--
--		result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
--
--		if (0 != result)
--			return result;
--
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
--	}
--
--	return 0;
--}
--
--
--static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr)
--{
--	static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
--
--	ellesmere_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
--
--	return 0;
--}
--
--/**
--* Return if the SMC is currently running.
--*
--* @param    smumgr  the address of the powerplay hardware manager.
--*/
--bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr)
--{
--	return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
--	&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
--}
--
--/**
--* Send a message to the SMC, and wait for its response.
--*
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    msg the message to send.
--* @return   The response that came from the SMC.
--*/
--int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
--{
--	if (!ellesmere_is_smc_ram_running(smumgr))
--		return -1;
--
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
--
--	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
--		printk("Failed to send Previous Message.\n");
--
--
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
--
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
--
--	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
--		printk("Failed to send Message.\n");
--
--	return 0;
--}
--
--
--/**
--* Send a message to the SMC, and do not wait for its response.
--*
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    msg the message to send.
--* @return   Always return 0.
--*/
--int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
--{
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
--
--	return 0;
--}
--
--/**
--* Send a message to the SMC with parameter
--*
--* @param    smumgr:  the address of the powerplay hardware manager.
--* @param    msg: the message to send.
--* @param    parameter: the parameter to send
--* @return   The response that came from the SMC.
--*/
--int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
--{
--	if (!ellesmere_is_smc_ram_running(smumgr)) {
--		return -1;
--	}
--
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
--
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
--
--	return ellesmere_send_msg_to_smc(smumgr, msg);
--}
--
--
--/**
--* Send a message to the SMC with parameter, do not wait for response
--*
--* @param    smumgr:  the address of the powerplay hardware manager.
--* @param    msg: the message to send.
--* @param    parameter: the parameter to send
--* @return   The response that came from the SMC.
--*/
--int ellesmere_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
--{
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
--
--	return ellesmere_send_msg_to_smc_without_waiting(smumgr, msg);
--}
--
--int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
--{
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
--
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
--
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
--
--	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
--		printk("Failed to send Message.\n");
--
--	return 0;
--}
--
--/**
--* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction.
--*
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    msg the message to send.
--* @return   The response that came from the SMC.
--*/
--int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr)
--{
--	/* If the SMC is not even on it qualifies as inactive. */
--	if (!ellesmere_is_smc_ram_running(smumgr))
--		return -1;
--
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
--	return 0;
--}
--
--
--/**
--* Upload the SMC firmware to the SMC microcontroller.
--*
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    pFirmware the data structure containing the various sections of the firmware.
--*/
--static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
--{
--	uint32_t byte_count = length;
--
--	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1);
--
--	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
--
--	for (; byte_count >= 4; byte_count -= 4)
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
--
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
--
--	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1);
--
--	return 0;
--}
--
--static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
--{
--	enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
--
--	switch (fw_type) {
--	case UCODE_ID_SMU:
--		result = CGS_UCODE_ID_SMU;
--		break;
--	case UCODE_ID_SMU_SK:
--		result = CGS_UCODE_ID_SMU_SK;
--		break;
--	case UCODE_ID_SDMA0:
--		result = CGS_UCODE_ID_SDMA0;
--		break;
--	case UCODE_ID_SDMA1:
--		result = CGS_UCODE_ID_SDMA1;
--		break;
--	case UCODE_ID_CP_CE:
--		result = CGS_UCODE_ID_CP_CE;
--		break;
--	case UCODE_ID_CP_PFP:
--		result = CGS_UCODE_ID_CP_PFP;
--		break;
--	case UCODE_ID_CP_ME:
--		result = CGS_UCODE_ID_CP_ME;
--		break;
--	case UCODE_ID_CP_MEC:
--		result = CGS_UCODE_ID_CP_MEC;
--		break;
--	case UCODE_ID_CP_MEC_JT1:
--		result = CGS_UCODE_ID_CP_MEC_JT1;
--		break;
--	case UCODE_ID_CP_MEC_JT2:
--		result = CGS_UCODE_ID_CP_MEC_JT2;
--		break;
--	case UCODE_ID_RLC_G:
--		result = CGS_UCODE_ID_RLC_G;
--		break;
--	default:
--		break;
--	}
--
--	return result;
--}
--
--static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr)
--{
--	int result = 0;
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--
--	struct cgs_firmware_info info = {0};
--
--	if (smu_data->security_hard_key == 1)
--		cgs_get_firmware_info(smumgr->device,
--			ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
--	else
--		cgs_get_firmware_info(smumgr->device,
--			ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
--
--	/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
--	result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE);
--
--	return result;
--}
--
--/**
--* Read a 32bit value from the SMC SRAM space.
--* ALL PARAMETERS ARE IN HOST BYTE ORDER.
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    smcAddress the address in the SMC RAM to access.
--* @param    value and output parameter for the data read from the SMC SRAM.
--*/
--int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
--{
--	int result;
--
--	result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
--
--	if (result)
--		return result;
--
--	*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
--	return 0;
--}
--
--/**
--* Write a 32bit value to the SMC SRAM space.
--* ALL PARAMETERS ARE IN HOST BYTE ORDER.
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    smc_addr the address in the SMC RAM to access.
--* @param    value to write to the SMC SRAM.
--*/
--int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
--{
--	int result;
--
--	result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
--
--	if (result)
--		return result;
--
--	cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
--
--	return 0;
--}
--
--
--int ellesmere_smu_fini(struct pp_smumgr *smumgr)
--{
--	if (smumgr->backend) {
--		kfree(smumgr->backend);
--		smumgr->backend = NULL;
--	}
--	return 0;
--}
--
--/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
--static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type)
--{
--	uint32_t result = 0;
--
--	switch (fw_type) {
--	case UCODE_ID_SDMA0:
--		result = UCODE_ID_SDMA0_MASK;
--		break;
--	case UCODE_ID_SDMA1:
--		result = UCODE_ID_SDMA1_MASK;
--		break;
--	case UCODE_ID_CP_CE:
--		result = UCODE_ID_CP_CE_MASK;
--		break;
--	case UCODE_ID_CP_PFP:
--		result = UCODE_ID_CP_PFP_MASK;
--		break;
--	case UCODE_ID_CP_ME:
--		result = UCODE_ID_CP_ME_MASK;
--		break;
--	case UCODE_ID_CP_MEC_JT1:
--	case UCODE_ID_CP_MEC_JT2:
--		result = UCODE_ID_CP_MEC_MASK;
--		break;
--	case UCODE_ID_RLC_G:
--		result = UCODE_ID_RLC_G_MASK;
--		break;
--	default:
--		printk("UCode type is out of range! \n");
--		result = 0;
--	}
--
--	return result;
--}
--
--/* Populate one firmware image to the data structure */
--
--static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr,
--						uint32_t fw_type,
--						struct SMU_Entry *entry)
--{
--	int result = 0;
--	struct cgs_firmware_info info = {0};
--
--	result = cgs_get_firmware_info(smumgr->device,
--				ellesmere_convert_fw_type_to_cgs(fw_type),
--				&info);
--
--	if (!result) {
--		entry->version = info.version;
--		entry->id = (uint16_t)fw_type;
--		entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
--		entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
--		entry->meta_data_addr_high = 0;
--		entry->meta_data_addr_low = 0;
--		entry->data_size_byte = info.image_size;
--		entry->num_register_entries = 0;
--	}
--
--	if (fw_type == UCODE_ID_RLC_G)
--		entry->flags = 1;
--	else
--		entry->flags = 0;
--
--	return 0;
--}
--
--static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr)
--{
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--	uint32_t fw_to_load;
--
--	int result = 0;
--	struct SMU_DRAMData_TOC *toc;
--
--	if (!smumgr->reload_fw) {
--		printk(KERN_INFO "[ powerplay ] skip reloading...\n");
--		return 0;
--	}
--
--	if (smu_data->soft_regs_start)
--		cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
--					smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
--					0x0);
--
--	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
--	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
--
--	toc = (struct SMU_DRAMData_TOC *)smu_data->header;
--	toc->num_entries = 0;
--	toc->structure_version = 1;
--
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--	PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
--
--	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
--	ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
--
--	fw_to_load = UCODE_ID_RLC_G_MASK
--		   + UCODE_ID_SDMA0_MASK
--		   + UCODE_ID_SDMA1_MASK
--		   + UCODE_ID_CP_CE_MASK
--		   + UCODE_ID_CP_ME_MASK
--		   + UCODE_ID_CP_PFP_MASK
--		   + UCODE_ID_CP_MEC_MASK;
--
--	if (ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
--		printk(KERN_ERR "Fail to Request SMU Load uCode");
--
--	return result;
--}
--
--/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
--static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
--{
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--	uint32_t fw_mask = ellesmere_get_mask_for_firmware_type(fw_type);
--	uint32_t ret;
--	/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
--	ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
--					smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
--					fw_mask, fw_mask);
--
--	return ret;
--}
--
--static int ellesmere_reload_firmware(struct pp_smumgr *smumgr)
--{
--	return smumgr->smumgr_funcs->start_smu(smumgr);
--}
--
--static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr)
--{
--	int i;
--	int result = -1;
--	uint32_t reg, data;
--
--	PWR_Command_Table *pvirus = pwr_virus_table;
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--
--
--	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
--		switch (pvirus->command) {
--		case PwrCmdWrite:
--			reg  = pvirus->reg;
--			data = pvirus->data;
--			cgs_write_register(smumgr->device, reg, data);
--			break;
--
--		case PwrCmdEnd:
--			result = 0;
--			break;
--
--		default:
--			printk("Table Exit with Invalid Command!");
--			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
--			result = -1;
--			break;
--		}
--		pvirus++;
--	}
--
--	return result;
--}
--
--static int ellesmere_perform_btc(struct pp_smumgr *smumgr)
--{
--	int result = 0;
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--
--	if (0 != smu_data->avfs.avfs_btc_param) {
--		if (0 != ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
--			printk("[AVFS][SmuEllesmere_PerformBtc] PerformBTC SMU msg failed");
--			result = -1;
--		}
--	}
--	if (smu_data->avfs.avfs_btc_param > 1) {
--		/* Soft-Reset to reset the engine before loading uCode */
--		/* halt */
--		cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
--		/* reset everything */
--		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
--		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
--	}
--	return result;
--}
--
--
--int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr)
--{
--	uint32_t vr_config;
--	uint32_t dpm_table_start;
--
--	uint16_t u16_boot_mvdd;
--	uint32_t graphics_level_address, vr_config_address, graphics_level_size;
--
--	graphics_level_size = sizeof(avfs_graphics_level_ellesmere);
--	u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
--
--	PP_ASSERT_WITH_CODE(0 == ellesmere_read_smc_sram_dword(smumgr,
--				SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
--				&dpm_table_start, 0x40000),
--			"[AVFS][Ellesmere_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
--			return -1);
--
--	/*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
--	vr_config = 0x01000500; /* Real value:0x50001 */
--
--	vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
--
--	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, vr_config_address,
--				(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
--			"[AVFS][Ellesmere_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
--			return -1);
--
--	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
--
--	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
--				(uint8_t *)(&avfs_graphics_level_ellesmere),
--				graphics_level_size, 0x40000),
--			"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
--			return -1);
--
--	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
--
--	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
--				(uint8_t *)(&avfs_memory_level_ellesmere), sizeof(avfs_memory_level_ellesmere), 0x40000),
--				"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
--			return -1);
--
--	/* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
--
--	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
--
--	PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
--			(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
--			"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of DPM table failed!",
--			return -1);
--
--	return 0;
--}
--
--int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
--{
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--
--	switch (smu_data->avfs.avfs_btc_status) {
--	case AVFS_BTC_COMPLETED_PREVIOUSLY:
--		break;
--
--	case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
--
--		smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
--		PP_ASSERT_WITH_CODE(0 == ellesmere_setup_graphics_level_structure(smumgr),
--		"[AVFS][Ellesmere_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
--		return -1);
--
--		if (smu_data->avfs.avfs_btc_param > 1) {
--			printk("[AVFS][Ellesmere_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
--			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
--			PP_ASSERT_WITH_CODE(-1 == ellesmere_setup_pwr_virus(smumgr),
--			"[AVFS][Ellesmere_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
--			return -1);
--		}
--
--		smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
--		PP_ASSERT_WITH_CODE(0 == ellesmere_perform_btc(smumgr),
--					"[AVFS][Ellesmere_AVFSEventMgr] Failure at SmuEllesmere_PerformBTC. AVFS Disabled",
--				 return -1);
--
--		break;
--
--	case AVFS_BTC_DISABLED:
--	case AVFS_BTC_NOTSUPPORTED:
--		break;
--
--	default:
--		printk("[AVFS] Something is broken. See log!");
--		break;
--	}
--
--	return 0;
--}
--
--static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
--{
--	int result = 0;
--
--	/* Wait for smc boot up */
--	/* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
--
--	/* Assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
--
--	result = ellesmere_upload_smu_firmware_image(smumgr);
--	if (result != 0)
--		return result;
--
--	/* Clear status */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
--
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
--
--	/* De-assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
--
--
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
--
--
--	/* Call Test SMU message with 0x20000 offset to trigger SMU start */
--	ellesmere_send_msg_to_smc_offset(smumgr);
--
--	/* Wait done bit to be set */
--	/* Check pass/failed indicator */
--
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
--
--	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--						SMU_STATUS, SMU_PASS))
--		PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
--
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
--
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
--
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
--
--	/* Wait for firmware to initialize */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
--
--	return result;
--}
--
--static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
--{
--	int result = 0;
--
--	/* wait for smc boot up */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
--
--	/* Clear firmware interrupt enable flag */
--	/* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
--				ixFIRMWARE_FLAGS, 0);
--
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_RESET_CNTL,
--					rst_reg, 1);
--
--	result = ellesmere_upload_smu_firmware_image(smumgr);
--	if (result != 0)
--		return result;
--
--	/* Set smc instruct start point at 0x0 */
--	ellesmere_program_jump_on_start(smumgr);
--
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
--
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
--					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
--
--	/* Wait for firmware to initialize */
--
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
--					FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
--
--	return result;
--}
--
--static int ellesmere_start_smu(struct pp_smumgr *smumgr)
--{
--	int result = 0;
--	struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--	bool SMU_VFT_INTACT;
--
--	/* Only start SMC if SMC RAM is not running */
--	if (!ellesmere_is_smc_ram_running(smumgr)) {
--		SMU_VFT_INTACT = false;
--		smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
--		smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
--
--		/* Check if SMU is running in protected mode */
--		if (smu_data->protected_mode == 0) {
--			result = ellesmere_start_smu_in_non_protection_mode(smumgr);
--		} else {
--			result = ellesmere_start_smu_in_protection_mode(smumgr);
--
--			/* If failed, try with different security Key. */
--			if (result != 0) {
--				smu_data->security_hard_key ^= 1;
--				result = ellesmere_start_smu_in_protection_mode(smumgr);
--			}
--		}
--
--		if (result != 0)
--			PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
--
--		ellesmere_avfs_event_mgr(smumgr, true);
--	} else
--		SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
--
--	smu_data->post_initial_boot = true;
--	ellesmere_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
--	/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
--	ellesmere_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
--					&(smu_data->soft_regs_start), 0x40000);
--
--	result = ellesmere_request_smu_load_fw(smumgr);
--
--	return result;
--}
--
--static int ellesmere_smu_init(struct pp_smumgr *smumgr)
--{
--	struct ellesmere_smumgr *smu_data;
--	uint8_t *internal_buf;
--	uint64_t mc_addr = 0;
--	/* Allocate memory for backend private data */
--	smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
--	smu_data->header_buffer.data_size =
--		((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
--	smu_data->smu_buffer.data_size = 200*4096;
--	smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
--/* Allocate FW image data structure and header buffer and
-- * send the header buffer address to SMU */
--	smu_allocate_memory(smumgr->device,
--		smu_data->header_buffer.data_size,
--		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
--		PAGE_SIZE,
--		&mc_addr,
--		&smu_data->header_buffer.kaddr,
--		&smu_data->header_buffer.handle);
--
--	smu_data->header = smu_data->header_buffer.kaddr;
--	smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
--	smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
--
--	PP_ASSERT_WITH_CODE((NULL != smu_data->header),
--		"Out of memory.",
--		kfree(smumgr->backend);
--		cgs_free_gpu_mem(smumgr->device,
--		(cgs_handle_t)smu_data->header_buffer.handle);
--		return -1);
--
--/* Allocate buffer for SMU internal buffer and send the address to SMU.
-- * Iceland SMU does not need internal buffer.*/
--	smu_allocate_memory(smumgr->device,
--		smu_data->smu_buffer.data_size,
--		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
--		PAGE_SIZE,
--		&mc_addr,
--		&smu_data->smu_buffer.kaddr,
--		&smu_data->smu_buffer.handle);
--
--	internal_buf = smu_data->smu_buffer.kaddr;
--	smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
--	smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
--
--	PP_ASSERT_WITH_CODE((NULL != internal_buf),
--		"Out of memory.",
--		kfree(smumgr->backend);
--		cgs_free_gpu_mem(smumgr->device,
--		(cgs_handle_t)smu_data->smu_buffer.handle);
--		return -1;);
--
--	return 0;
--}
--
--static const struct pp_smumgr_func ellsemere_smu_funcs = {
--	.smu_init = ellesmere_smu_init,
--	.smu_fini = ellesmere_smu_fini,
--	.start_smu = ellesmere_start_smu,
--	.check_fw_load_finish = ellesmere_check_fw_load_finish,
--	.request_smu_load_fw = ellesmere_reload_firmware,
--	.request_smu_load_specific_fw = NULL,
--	.send_msg_to_smc = ellesmere_send_msg_to_smc,
--	.send_msg_to_smc_with_parameter = ellesmere_send_msg_to_smc_with_parameter,
--	.download_pptable_settings = NULL,
--	.upload_pptable_settings = NULL,
--};
--
--int ellesmere_smum_init(struct pp_smumgr *smumgr)
--{
--	struct ellesmere_smumgr *ellesmere_smu = NULL;
--
--	ellesmere_smu = kzalloc(sizeof(struct ellesmere_smumgr), GFP_KERNEL);
--
--	if (ellesmere_smu == NULL)
--		return -1;
--
--	smumgr->backend = ellesmere_smu;
--	smumgr->smumgr_funcs = &ellsemere_smu_funcs;
--
--	return 0;
--}
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-deleted file mode 100644
-index 05d636a..0000000
---- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h
-+++ /dev/null
-@@ -1,68 +0,0 @@
--/*
-- * Copyright 2015 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- */
--
--#ifndef _ELLESMERE_SMUMANAGER_H
--#define _ELLESMERE_SMUMANAGER_H
--
--#include <ellesmere_ppsmc.h>
--#include <pp_endian.h>
--
--struct ellesmere_avfs {
--	enum AVFS_BTC_STATUS avfs_btc_status;
--	uint32_t           avfs_btc_param;
--};
--
--struct ellesmere_buffer_entry {
--	uint32_t data_size;
--	uint32_t mc_addr_low;
--	uint32_t mc_addr_high;
--	void *kaddr;
--	unsigned long  handle;
--};
--
--struct ellesmere_smumgr {
--	uint8_t *header;
--	uint8_t *mec_image;
--	struct ellesmere_buffer_entry smu_buffer;
--	struct ellesmere_buffer_entry header_buffer;
--	uint32_t soft_regs_start;
--	uint8_t *read_rrm_straps;
--	uint32_t read_drm_straps_mc_address_high;
--	uint32_t read_drm_straps_mc_address_low;
--	uint32_t acpi_optimization;
--	bool post_initial_boot;
--	uint8_t protected_mode;
--	uint8_t security_hard_key;
--	struct ellesmere_avfs  avfs;
--};
--
--
--int ellesmere_smum_init(struct pp_smumgr *smumgr);
--
--int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
--int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
--int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
--				const uint8_t *src, uint32_t byte_count, uint32_t limit);
--
--#endif
--
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
-new file mode 100644
-index 0000000..667e055
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
-@@ -0,0 +1,983 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include "smumgr.h"
-+#include "smu74.h"
-+#include "smu_ucode_xfer_vi.h"
-+#include "polaris10_smumgr.h"
-+#include "smu74_discrete.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "oss/oss_3_0_d.h"
-+#include "gca/gfx_8_0_d.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "polaris10_pwrvirus.h"
-+#include "ppatomctrl.h"
-+#include "pp_debug.h"
-+#include "cgs_common.h"
-+
-+#define POLARIS10_SMC_SIZE 0x20000
-+#define VOLTAGE_SCALE 4
-+
-+/* Microcode file is stored in this buffer */
-+#define BUFFER_SIZE                 80000
-+#define MAX_STRING_SIZE             15
-+#define BUFFER_SIZETWO              131072  /* 128 *1024 */
-+
-+#define SMC_RAM_END 0x40000
-+
-+SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
-+	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
-+	/* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
-+	{ 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0xa00fd047, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x409c0000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x0410d047, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0, 0, 0x0e, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x50c30000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x6810d047, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x60ea0000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0xcc10d047, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xe8fd0000, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x3011d047, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x70110100, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0x9411d047, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0xf8240100, 0, 0, 0, 0, 0, 0, 0 } },
-+	{ 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
-+};
-+
-+SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
-+							0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
-+
-+/**
-+* Set the address for reading/writing the SMC SRAM space.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smcAddress the address in the SMC RAM to access.
-+*/
-+static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
-+{
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
-+
-+	return 0;
-+}
-+
-+/**
-+* Copy bytes from SMC RAM space into driver memory.
-+*
-+* @param    smumgr  the address of the powerplay SMU manager.
-+* @param    smc_start_address the start address in the SMC RAM to copy bytes from
-+* @param    src the byte array to copy the bytes to.
-+* @param    byte_count the number of bytes to copy.
-+*/
-+int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
-+{
-+	uint32_t data;
-+	uint32_t addr;
-+	uint8_t *dest_byte;
-+	uint8_t i, data_byte[4] = {0};
-+	uint32_t *pdata = (uint32_t *)&data_byte;
-+
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1;);
-+	PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
-+
-+	addr = smc_start_address;
-+
-+	while (byte_count >= 4) {
-+		polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
-+
-+		*dest = PP_SMC_TO_HOST_UL(data);
-+
-+		dest += 1;
-+		byte_count -= 4;
-+		addr += 4;
-+	}
-+
-+	if (byte_count) {
-+		polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
-+		*pdata = PP_SMC_TO_HOST_UL(data);
-+	/* Cast dest into byte type in dest_byte.  This way, we don't overflow if the allocated memory is not 4-byte aligned. */
-+		dest_byte = (uint8_t *)dest;
-+		for (i = 0; i < byte_count; i++)
-+			dest_byte[i] = data_byte[i];
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+* Copy bytes from an array into the SMC RAM space.
-+*
-+* @param    pSmuMgr  the address of the powerplay SMU manager.
-+* @param    smc_start_address the start address in the SMC RAM to copy bytes to.
-+* @param    src the byte array to copy the bytes from.
-+* @param    byte_count the number of bytes to copy.
-+*/
-+int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+				const uint8_t *src, uint32_t byte_count, uint32_t limit)
-+{
-+	int result;
-+	uint32_t data = 0;
-+	uint32_t original_data;
-+	uint32_t addr = 0;
-+	uint32_t extra_shift;
-+
-+	PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -1);
-+	PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -1);
-+
-+	addr = smc_start_address;
-+
-+	while (byte_count >= 4) {
-+	/* Bytes are written into the SMC addres space with the MSB first. */
-+		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
-+
-+		result = polaris10_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
-+
-+		src += 4;
-+		byte_count -= 4;
-+		addr += 4;
-+	}
-+
-+	if (0 != byte_count) {
-+
-+		data = 0;
-+
-+		result = polaris10_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+
-+		original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
-+
-+		extra_shift = 8 * (4 - byte_count);
-+
-+		while (byte_count > 0) {
-+			/* Bytes are written into the SMC addres space with the MSB first. */
-+			data = (0x100 * data) + *src++;
-+			byte_count--;
-+		}
-+
-+		data <<= extra_shift;
-+
-+		data |= (original_data & ~((~0UL) << extra_shift));
-+
-+		result = polaris10_set_smc_sram_address(smumgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
-+{
-+	static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
-+
-+	polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
-+
-+	return 0;
-+}
-+
-+/**
-+* Return if the SMC is currently running.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+*/
-+bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
-+{
-+	return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-+	&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
-+}
-+
-+/**
-+* Send a message to the SMC, and wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	if (!polaris10_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+		printk("Failed to send Previous Message.\n");
-+
-+
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+		printk("Failed to send Message.\n");
-+
-+	return 0;
-+}
-+
-+
-+/**
-+* Send a message to the SMC, and do not wait for its response.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   Always return 0.
-+*/
-+int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
-+{
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	return 0;
-+}
-+
-+/**
-+* Send a message to the SMC with parameter
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+{
-+	if (!polaris10_is_smc_ram_running(smumgr)) {
-+		return -1;
-+	}
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+
-+	return polaris10_send_msg_to_smc(smumgr, msg);
-+}
-+
-+
-+/**
-+* Send a message to the SMC with parameter, do not wait for response
-+*
-+* @param    smumgr:  the address of the powerplay hardware manager.
-+* @param    msg: the message to send.
-+* @param    parameter: the parameter to send
-+* @return   The response that came from the SMC.
-+*/
-+int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+{
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+
-+	return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
-+}
-+
-+int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
-+{
-+	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
-+
-+	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-+
-+	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+		printk("Failed to send Message.\n");
-+
-+	return 0;
-+}
-+
-+/**
-+* Wait until the SMC is doing nithing. Doing nothing means that the SMC is either turned off or it is sitting on the STOP instruction.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    msg the message to send.
-+* @return   The response that came from the SMC.
-+*/
-+int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr)
-+{
-+	/* If the SMC is not even on it qualifies as inactive. */
-+	if (!polaris10_is_smc_ram_running(smumgr))
-+		return -1;
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
-+	return 0;
-+}
-+
-+
-+/**
-+* Upload the SMC firmware to the SMC microcontroller.
-+*
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    pFirmware the data structure containing the various sections of the firmware.
-+*/
-+static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
-+{
-+	uint32_t byte_count = length;
-+
-+	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -1);
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
-+
-+	for (; byte_count >= 4; byte_count -= 4)
-+		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
-+
-+	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
-+
-+	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -1);
-+
-+	return 0;
-+}
-+
-+static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type)
-+{
-+	enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SMU:
-+		result = CGS_UCODE_ID_SMU;
-+		break;
-+	case UCODE_ID_SMU_SK:
-+		result = CGS_UCODE_ID_SMU_SK;
-+		break;
-+	case UCODE_ID_SDMA0:
-+		result = CGS_UCODE_ID_SDMA0;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = CGS_UCODE_ID_SDMA1;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = CGS_UCODE_ID_CP_CE;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = CGS_UCODE_ID_CP_PFP;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = CGS_UCODE_ID_CP_ME;
-+		break;
-+	case UCODE_ID_CP_MEC:
-+		result = CGS_UCODE_ID_CP_MEC;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+		result = CGS_UCODE_ID_CP_MEC_JT1;
-+		break;
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = CGS_UCODE_ID_CP_MEC_JT2;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = CGS_UCODE_ID_RLC_G;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+
-+	struct cgs_firmware_info info = {0};
-+
-+	if (smu_data->security_hard_key == 1)
-+		cgs_get_firmware_info(smumgr->device,
-+			polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
-+	else
-+		cgs_get_firmware_info(smumgr->device,
-+			polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
-+
-+	/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
-+	result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE);
-+
-+	return result;
-+}
-+
-+/**
-+* Read a 32bit value from the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smcAddress the address in the SMC RAM to access.
-+* @param    value and output parameter for the data read from the SMC SRAM.
-+*/
-+int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
-+{
-+	int result;
-+
-+	result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
-+	return 0;
-+}
-+
-+/**
-+* Write a 32bit value to the SMC SRAM space.
-+* ALL PARAMETERS ARE IN HOST BYTE ORDER.
-+* @param    smumgr  the address of the powerplay hardware manager.
-+* @param    smc_addr the address in the SMC RAM to access.
-+* @param    value to write to the SMC SRAM.
-+*/
-+int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
-+{
-+	int result;
-+
-+	result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
-+
-+	return 0;
-+}
-+
-+
-+int polaris10_smu_fini(struct pp_smumgr *smumgr)
-+{
-+	if (smumgr->backend) {
-+		kfree(smumgr->backend);
-+		smumgr->backend = NULL;
-+	}
-+	return 0;
-+}
-+
-+/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
-+static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type)
-+{
-+	uint32_t result = 0;
-+
-+	switch (fw_type) {
-+	case UCODE_ID_SDMA0:
-+		result = UCODE_ID_SDMA0_MASK;
-+		break;
-+	case UCODE_ID_SDMA1:
-+		result = UCODE_ID_SDMA1_MASK;
-+		break;
-+	case UCODE_ID_CP_CE:
-+		result = UCODE_ID_CP_CE_MASK;
-+		break;
-+	case UCODE_ID_CP_PFP:
-+		result = UCODE_ID_CP_PFP_MASK;
-+		break;
-+	case UCODE_ID_CP_ME:
-+		result = UCODE_ID_CP_ME_MASK;
-+		break;
-+	case UCODE_ID_CP_MEC_JT1:
-+	case UCODE_ID_CP_MEC_JT2:
-+		result = UCODE_ID_CP_MEC_MASK;
-+		break;
-+	case UCODE_ID_RLC_G:
-+		result = UCODE_ID_RLC_G_MASK;
-+		break;
-+	default:
-+		printk("UCode type is out of range! \n");
-+		result = 0;
-+	}
-+
-+	return result;
-+}
-+
-+/* Populate one firmware image to the data structure */
-+
-+static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr,
-+						uint32_t fw_type,
-+						struct SMU_Entry *entry)
-+{
-+	int result = 0;
-+	struct cgs_firmware_info info = {0};
-+
-+	result = cgs_get_firmware_info(smumgr->device,
-+				polaris10_convert_fw_type_to_cgs(fw_type),
-+				&info);
-+
-+	if (!result) {
-+		entry->version = info.version;
-+		entry->id = (uint16_t)fw_type;
-+		entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
-+		entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
-+		entry->meta_data_addr_high = 0;
-+		entry->meta_data_addr_low = 0;
-+		entry->data_size_byte = info.image_size;
-+		entry->num_register_entries = 0;
-+	}
-+
-+	if (fw_type == UCODE_ID_RLC_G)
-+		entry->flags = 1;
-+	else
-+		entry->flags = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+	uint32_t fw_to_load;
-+
-+	int result = 0;
-+	struct SMU_DRAMData_TOC *toc;
-+
-+	if (!smumgr->reload_fw) {
-+		printk(KERN_INFO "[ powerplay ] skip reloading...\n");
-+		return 0;
-+	}
-+
-+	if (smu_data->soft_regs_start)
-+		cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+					smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
-+					0x0);
-+
-+	polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
-+	polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
-+
-+	toc = (struct SMU_DRAMData_TOC *)smu_data->header;
-+	toc->num_entries = 0;
-+	toc->structure_version = 1;
-+
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+	PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
-+
-+	polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
-+	polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
-+
-+	fw_to_load = UCODE_ID_RLC_G_MASK
-+		   + UCODE_ID_SDMA0_MASK
-+		   + UCODE_ID_SDMA1_MASK
-+		   + UCODE_ID_CP_CE_MASK
-+		   + UCODE_ID_CP_ME_MASK
-+		   + UCODE_ID_CP_PFP_MASK
-+		   + UCODE_ID_CP_MEC_MASK;
-+
-+	if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
-+		printk(KERN_ERR "Fail to Request SMU Load uCode");
-+
-+	return result;
-+}
-+
-+/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
-+static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+	uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type);
-+	uint32_t ret;
-+	/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
-+	ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
-+					smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
-+					fw_mask, fw_mask);
-+
-+	return ret;
-+}
-+
-+static int polaris10_reload_firmware(struct pp_smumgr *smumgr)
-+{
-+	return smumgr->smumgr_funcs->start_smu(smumgr);
-+}
-+
-+static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
-+{
-+	int i;
-+	int result = -1;
-+	uint32_t reg, data;
-+
-+	PWR_Command_Table *pvirus = pwr_virus_table;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+
-+
-+	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
-+		switch (pvirus->command) {
-+		case PwrCmdWrite:
-+			reg  = pvirus->reg;
-+			data = pvirus->data;
-+			cgs_write_register(smumgr->device, reg, data);
-+			break;
-+
-+		case PwrCmdEnd:
-+			result = 0;
-+			break;
-+
-+		default:
-+			printk("Table Exit with Invalid Command!");
-+			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
-+			result = -1;
-+			break;
-+		}
-+		pvirus++;
-+	}
-+
-+	return result;
-+}
-+
-+static int polaris10_perform_btc(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+
-+	if (0 != smu_data->avfs.avfs_btc_param) {
-+		if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
-+			printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
-+			result = -1;
-+		}
-+	}
-+	if (smu_data->avfs.avfs_btc_param > 1) {
-+		/* Soft-Reset to reset the engine before loading uCode */
-+		/* halt */
-+		cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
-+		/* reset everything */
-+		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
-+		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
-+	}
-+	return result;
-+}
-+
-+
-+int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
-+{
-+	uint32_t vr_config;
-+	uint32_t dpm_table_start;
-+
-+	uint16_t u16_boot_mvdd;
-+	uint32_t graphics_level_address, vr_config_address, graphics_level_size;
-+
-+	graphics_level_size = sizeof(avfs_graphics_level_polaris10);
-+	u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
-+
-+	PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
-+				&dpm_table_start, 0x40000),
-+			"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
-+			return -1);
-+
-+	/*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
-+	vr_config = 0x01000500; /* Real value:0x50001 */
-+
-+	vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
-+
-+	PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address,
-+				(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
-+			"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
-+			return -1);
-+
-+	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
-+
-+	PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
-+				(uint8_t *)(&avfs_graphics_level_polaris10),
-+				graphics_level_size, 0x40000),
-+			"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
-+			return -1);
-+
-+	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
-+
-+	PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
-+				(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
-+				"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
-+			return -1);
-+
-+	/* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
-+
-+	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
-+
-+	PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
-+			(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
-+			"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
-+			return -1);
-+
-+	return 0;
-+}
-+
-+int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+
-+	switch (smu_data->avfs.avfs_btc_status) {
-+	case AVFS_BTC_COMPLETED_PREVIOUSLY:
-+		break;
-+
-+	case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
-+
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
-+		"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
-+		return -1);
-+
-+		if (smu_data->avfs.avfs_btc_param > 1) {
-+			printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
-+			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
-+			PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
-+			"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
-+			return -1);
-+		}
-+
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
-+		PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
-+					"[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
-+				 return -1);
-+
-+		break;
-+
-+	case AVFS_BTC_DISABLED:
-+	case AVFS_BTC_NOTSUPPORTED:
-+		break;
-+
-+	default:
-+		printk("[AVFS] Something is broken. See log!");
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* Wait for smc boot up */
-+	/* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
-+
-+	/* Assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	result = polaris10_upload_smu_firmware_image(smumgr);
-+	if (result != 0)
-+		return result;
-+
-+	/* Clear status */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	/* De-assert reset */
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
-+
-+
-+	/* Call Test SMU message with 0x20000 offset to trigger SMU start */
-+	polaris10_send_msg_to_smc_offset(smumgr);
-+
-+	/* Wait done bit to be set */
-+	/* Check pass/failed indicator */
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
-+
-+	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+						SMU_STATUS, SMU_PASS))
-+		PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
-+
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for firmware to initialize */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+
-+	/* wait for smc boot up */
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
-+
-+	/* Clear firmware interrupt enable flag */
-+	/* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
-+	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+				ixFIRMWARE_FLAGS, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL,
-+					rst_reg, 1);
-+
-+	result = polaris10_upload_smu_firmware_image(smumgr);
-+	if (result != 0)
-+		return result;
-+
-+	/* Set smc instruct start point at 0x0 */
-+	polaris10_program_jump_on_start(smumgr);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	/* Wait for firmware to initialize */
-+
-+	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+					FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+
-+	return result;
-+}
-+
-+static int polaris10_start_smu(struct pp_smumgr *smumgr)
-+{
-+	int result = 0;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+	bool SMU_VFT_INTACT;
-+
-+	/* Only start SMC if SMC RAM is not running */
-+	if (!polaris10_is_smc_ram_running(smumgr)) {
-+		SMU_VFT_INTACT = false;
-+		smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
-+		smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
-+
-+		/* Check if SMU is running in protected mode */
-+		if (smu_data->protected_mode == 0) {
-+			result = polaris10_start_smu_in_non_protection_mode(smumgr);
-+		} else {
-+			result = polaris10_start_smu_in_protection_mode(smumgr);
-+
-+			/* If failed, try with different security Key. */
-+			if (result != 0) {
-+				smu_data->security_hard_key ^= 1;
-+				result = polaris10_start_smu_in_protection_mode(smumgr);
-+			}
-+		}
-+
-+		if (result != 0)
-+			PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
-+
-+		polaris10_avfs_event_mgr(smumgr, true);
-+	} else
-+		SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
-+
-+	smu_data->post_initial_boot = true;
-+	polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
-+	/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
-+	polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
-+					&(smu_data->soft_regs_start), 0x40000);
-+
-+	result = polaris10_request_smu_load_fw(smumgr);
-+
-+	return result;
-+}
-+
-+static int polaris10_smu_init(struct pp_smumgr *smumgr)
-+{
-+	struct polaris10_smumgr *smu_data;
-+	uint8_t *internal_buf;
-+	uint64_t mc_addr = 0;
-+	/* Allocate memory for backend private data */
-+	smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+	smu_data->header_buffer.data_size =
-+		((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
-+	smu_data->smu_buffer.data_size = 200*4096;
-+	smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
-+/* Allocate FW image data structure and header buffer and
-+ * send the header buffer address to SMU */
-+	smu_allocate_memory(smumgr->device,
-+		smu_data->header_buffer.data_size,
-+		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+		PAGE_SIZE,
-+		&mc_addr,
-+		&smu_data->header_buffer.kaddr,
-+		&smu_data->header_buffer.handle);
-+
-+	smu_data->header = smu_data->header_buffer.kaddr;
-+	smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != smu_data->header),
-+		"Out of memory.",
-+		kfree(smumgr->backend);
-+		cgs_free_gpu_mem(smumgr->device,
-+		(cgs_handle_t)smu_data->header_buffer.handle);
-+		return -1);
-+
-+/* Allocate buffer for SMU internal buffer and send the address to SMU.
-+ * Iceland SMU does not need internal buffer.*/
-+	smu_allocate_memory(smumgr->device,
-+		smu_data->smu_buffer.data_size,
-+		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-+		PAGE_SIZE,
-+		&mc_addr,
-+		&smu_data->smu_buffer.kaddr,
-+		&smu_data->smu_buffer.handle);
-+
-+	internal_buf = smu_data->smu_buffer.kaddr;
-+	smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
-+	smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
-+
-+	PP_ASSERT_WITH_CODE((NULL != internal_buf),
-+		"Out of memory.",
-+		kfree(smumgr->backend);
-+		cgs_free_gpu_mem(smumgr->device,
-+		(cgs_handle_t)smu_data->smu_buffer.handle);
-+		return -1;);
-+
-+	return 0;
-+}
-+
-+static const struct pp_smumgr_func ellsemere_smu_funcs = {
-+	.smu_init = polaris10_smu_init,
-+	.smu_fini = polaris10_smu_fini,
-+	.start_smu = polaris10_start_smu,
-+	.check_fw_load_finish = polaris10_check_fw_load_finish,
-+	.request_smu_load_fw = polaris10_reload_firmware,
-+	.request_smu_load_specific_fw = NULL,
-+	.send_msg_to_smc = polaris10_send_msg_to_smc,
-+	.send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,
-+	.download_pptable_settings = NULL,
-+	.upload_pptable_settings = NULL,
-+};
-+
-+int polaris10_smum_init(struct pp_smumgr *smumgr)
-+{
-+	struct polaris10_smumgr *polaris10_smu = NULL;
-+
-+	polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
-+
-+	if (polaris10_smu == NULL)
-+		return -1;
-+
-+	smumgr->backend = polaris10_smu;
-+	smumgr->smumgr_funcs = &ellsemere_smu_funcs;
-+
-+	return 0;
-+}
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
-new file mode 100644
-index 0000000..e5377ae
---- /dev/null
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
-@@ -0,0 +1,68 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _POLARIS10_SMUMANAGER_H
-+#define _POLARIS10_SMUMANAGER_H
-+
-+#include <polaris10_ppsmc.h>
-+#include <pp_endian.h>
-+
-+struct polaris10_avfs {
-+	enum AVFS_BTC_STATUS avfs_btc_status;
-+	uint32_t           avfs_btc_param;
-+};
-+
-+struct polaris10_buffer_entry {
-+	uint32_t data_size;
-+	uint32_t mc_addr_low;
-+	uint32_t mc_addr_high;
-+	void *kaddr;
-+	unsigned long  handle;
-+};
-+
-+struct polaris10_smumgr {
-+	uint8_t *header;
-+	uint8_t *mec_image;
-+	struct polaris10_buffer_entry smu_buffer;
-+	struct polaris10_buffer_entry header_buffer;
-+	uint32_t soft_regs_start;
-+	uint8_t *read_rrm_straps;
-+	uint32_t read_drm_straps_mc_address_high;
-+	uint32_t read_drm_straps_mc_address_low;
-+	uint32_t acpi_optimization;
-+	bool post_initial_boot;
-+	uint8_t protected_mode;
-+	uint8_t security_hard_key;
-+	struct polaris10_avfs  avfs;
-+};
-+
-+
-+int polaris10_smum_init(struct pp_smumgr *smumgr);
-+
-+int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
-+int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
-+int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+				const uint8_t *src, uint32_t byte_count, uint32_t limit);
-+
-+#endif
-+
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-index 06bbe90..c483baf 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
-@@ -30,7 +30,7 @@
- #include "cz_smumgr.h"
- #include "tonga_smumgr.h"
- #include "fiji_smumgr.h"
--#include "ellesmere_smumgr.h"
-+#include "polaris10_smumgr.h"
- 
- int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- {
-@@ -63,9 +63,9 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
- 		case CHIP_FIJI:
- 			fiji_smum_init(smumgr);
- 			break;
--		case CHIP_BAFFIN:
--		case CHIP_ELLESMERE:
--			ellesmere_smum_init(smumgr);
-+		case CHIP_POLARIS11:
-+		case CHIP_POLARIS10:
-+			polaris10_smum_init(smumgr);
- 			break;
- 		default:
- 			return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0950-drm-amd-powerplay-print-gpu-loading-and-uvd-vce-powe.patch b/common/recipes-kernel/linux/files/0950-drm-amd-powerplay-print-gpu-loading-and-uvd-vce-powe.patch
deleted file mode 100644
index b3cf9a6a..00000000
--- a/common/recipes-kernel/linux/files/0950-drm-amd-powerplay-print-gpu-loading-and-uvd-vce-powe.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 7e29b00f72a005621d2f8f022d282a68c08bb370 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 1 Mar 2016 17:01:30 +0800
-Subject: [PATCH 0950/1110] drm/amd/powerplay: print gpu loading and uvd/vce
- power gate enablement for polaris10/11.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 15 ++++++++++++++-
- 1 file changed, 14 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 5080d67..ac40599 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -3646,7 +3646,9 @@ static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
- static void
- polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
- {
--	uint32_t sclk, mclk;
-+	uint32_t sclk, mclk, activity_percent;
-+	uint32_t offset;
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- 
- 	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
- 
-@@ -3657,6 +3659,17 @@ polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *
- 	mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 	seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
- 			mclk / 100, sclk / 100);
-+
-+	offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
-+	activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
-+	activity_percent += 0x80;
-+	activity_percent >>= 8;
-+
-+	seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
-+
-+	seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
-+
-+	seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
- }
- 
- static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0951-drm-amd-powerplay-fix-mclk-in-high-clock-for-baffin.patch b/common/recipes-kernel/linux/files/0951-drm-amd-powerplay-fix-mclk-in-high-clock-for-baffin.patch
deleted file mode 100644
index 80b87aa1..00000000
--- a/common/recipes-kernel/linux/files/0951-drm-amd-powerplay-fix-mclk-in-high-clock-for-baffin.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 9f3c3aa72a1f153d672aa9415778933abe30aee6 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 15 Mar 2016 14:39:12 +0800
-Subject: [PATCH 0951/1110] drm/amd/powerplay: fix mclk in high clock for
- baffin
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 10 ++++------
- 1 file changed, 4 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index ac40599..d08f739 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -1377,13 +1377,14 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
- 		result = polaris10_populate_single_memory_level(hwmgr,
- 				dpm_table->mclk_table.dpm_levels[i].value,
- 				&levels[i]);
-+		if (i == dpm_table->mclk_table.count - 1) {
-+			levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-+			levels[i].EnabledForActivity = 1;
-+		}
- 		if (result)
- 			return result;
- 	}
- 
--	/* Only enable level 0 for now. */
--	levels[0].EnabledForActivity = 1;
--
- 	/* in order to prevent MC activity from stutter mode to push DPM up.
- 	 * the UVD change complements this by putting the MCLK in
- 	 * a higher state by default such that we are not effected by
-@@ -1396,9 +1397,6 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
- 			(uint8_t)dpm_table->mclk_table.count;
- 	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
- 			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
--	/* set highest level watermark to high */
--	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
--			PPSMC_DISPLAY_WATERMARK_HIGH;
- 
- 	/* level count will send to smc once at init smc table and never change */
- 	result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0952-drm-amd-powrplay-fix-issue-that-get-wrong-enable-fla.patch b/common/recipes-kernel/linux/files/0952-drm-amd-powrplay-fix-issue-that-get-wrong-enable-fla.patch
deleted file mode 100644
index e1bc7142..00000000
--- a/common/recipes-kernel/linux/files/0952-drm-amd-powrplay-fix-issue-that-get-wrong-enable-fla.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 4a8fd3d67594a6bf43d5827e0a15be8b124ee9c2 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 15 Mar 2016 17:42:47 +0800
-Subject: [PATCH 0952/1110] drm/amd/powrplay: fix issue that get wrong enable
- flag.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index d08f739..446ed72 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -3960,14 +3960,11 @@ static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
- 			uint32_t low_limit, uint32_t high_limit)
- {
- 	uint32_t i;
--	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- 
- 	for (i = 0; i < dpm_table->count; i++) {
- 		if ((dpm_table->dpm_levels[i].value < low_limit)
- 		|| (dpm_table->dpm_levels[i].value > high_limit))
- 			dpm_table->dpm_levels[i].enabled = false;
--		else if (((1 << i) & data->disable_dpm_mask) == 0)
--			dpm_table->dpm_levels[i].enabled = false;
- 		else
- 			dpm_table->dpm_levels[i].enabled = true;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0953-drm-amd-powerplay-enable-set-lowest-mclk-clock-on-ba.patch b/common/recipes-kernel/linux/files/0953-drm-amd-powerplay-enable-set-lowest-mclk-clock-on-ba.patch
deleted file mode 100644
index 5e1c5a22..00000000
--- a/common/recipes-kernel/linux/files/0953-drm-amd-powerplay-enable-set-lowest-mclk-clock-on-ba.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 9a116c41cd3d218c77d943a4877b8beb8bab89af Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 15 Mar 2016 19:30:00 +0800
-Subject: [PATCH 0953/1110] drm/amd/powerplay: enable set lowest mclk clock on
- baffin.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 446ed72..b77d7aa 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -3136,7 +3136,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
- 							    (1 << level));
- 
- 	}
--/* uvd is enabled, can't set mclk low right now
-+
- 	if (!data->mclk_dpm_key_disabled) {
- 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
- 			level = phm_get_lowest_enabled_level(hwmgr,
-@@ -3146,7 +3146,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
- 							    (1 << level));
- 		}
- 	}
--*/
-+
- 	if (!data->pcie_dpm_key_disabled) {
- 		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
- 			level = phm_get_lowest_enabled_level(hwmgr,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0954-drm-amd-powerplay-Disable-Spread-Spectrum-on-DPM-0-o.patch b/common/recipes-kernel/linux/files/0954-drm-amd-powerplay-Disable-Spread-Spectrum-on-DPM-0-o.patch
deleted file mode 100644
index 4798109b..00000000
--- a/common/recipes-kernel/linux/files/0954-drm-amd-powerplay-Disable-Spread-Spectrum-on-DPM-0-o.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From e2cb039fb1234388e2c77ef78e353fce4a1df100 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Tue, 22 Mar 2016 14:21:18 +0800
-Subject: [PATCH 0954/1110] drm/amd/powerplay: Disable Spread Spectrum on DPM 0
- on baffin as SPLL Shut Down feature is enabled.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Acked-by: Flora Cui <Flora.Cui@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 6 ++++++
- drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 1 +
- 2 files changed, 7 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index b77d7aa..715bc3d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -1248,6 +1248,9 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
- 		if (i > 1)
- 			levels[i].DeepSleepDivId = 0;
- 	}
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_SPLLShutdownSupport))
-+		data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
- 
- 	data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
- 	data->smc_state_table.GraphicsDpmLevelCount =
-@@ -2602,6 +2605,9 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_TCPRamping);
- 
-+	if (hwmgr->chip_id == CHIP_POLARIS11)
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_SPLLShutdownSupport);
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-index 040d3f7..56f712c 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
-@@ -211,6 +211,7 @@ enum phm_platform_caps {
- 	PHM_PlatformCaps_ClockStretcher,
- 	PHM_PlatformCaps_TablelessHardwareInterface,
- 	PHM_PlatformCaps_EnableDriverEVV,
-+	PHM_PlatformCaps_SPLLShutdownSupport,
- 	PHM_PlatformCaps_Max
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0955-drm-amdgpu-add-polaris10-11-smc-fw-declaration.patch b/common/recipes-kernel/linux/files/0955-drm-amdgpu-add-polaris10-11-smc-fw-declaration.patch
deleted file mode 100644
index 324559a3..00000000
--- a/common/recipes-kernel/linux/files/0955-drm-amdgpu-add-polaris10-11-smc-fw-declaration.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From d6c335f6a5f3fdb9b5d6bb14fd88d47ea597973f Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Fri, 18 Mar 2016 19:07:55 +0800
-Subject: [PATCH 0955/1110] drm/amdgpu: add polaris10/11 smc fw declaration
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 0d61d5b..ef80cfb 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -79,6 +79,11 @@
- #include "amdgpu_dm.h"
- #include "amdgpu_powerplay.h"
- 
-+MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
-+
- /*
-  * Indirect registers accessor
-  */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0956-drm-amd-dal-add-core-support-for-Polaris-family-v2.patch b/common/recipes-kernel/linux/files/0956-drm-amd-dal-add-core-support-for-Polaris-family-v2.patch
deleted file mode 100644
index 6143ca86..00000000
--- a/common/recipes-kernel/linux/files/0956-drm-amd-dal-add-core-support-for-Polaris-family-v2.patch
+++ /dev/null
@@ -1,9820 +0,0 @@
-From bc3e400b9b554d0e8448d89c7a721f887b612dfc Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 15 Mar 2016 10:53:48 -0400
-Subject: [PATCH 0956/1110] drm/amd/dal: add core support for Polaris family
- (v2)
-
-This adds core dc support for polaris 10 and 11.
-
-v2: add missing files
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/Makefile                |    4 +
- drivers/gpu/drm/amd/dal/dc/adapter/Makefile        |    4 +
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |   12 +
- .../adapter/dce112/hw_ctx_adapter_service_dce112.c |  302 +++
- .../adapter/dce112/hw_ctx_adapter_service_dce112.h |   39 +
- .../gpu/drm/amd/dal/dc/asic_capability/Makefile    |    9 +
- .../amd/dal/dc/asic_capability/asic_capability.c   |   15 +-
- .../dc/asic_capability/polaris10_asic_capability.c |  146 ++
- .../dc/asic_capability/polaris10_asic_capability.h |   36 +
- drivers/gpu/drm/amd/dal/dc/audio/Makefile          |    8 +
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |    9 +
- .../gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c |  451 +++++
- .../gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h |   40 +
- .../amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c  | 1923 ++++++++++++++++++++
- .../amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h  |   47 +
- drivers/gpu/drm/amd/dal/dc/bios/Makefile           |    9 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |    6 +
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |    4 +
- drivers/gpu/drm/amd/dal/dc/bios/command_table.c    |   78 +-
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.c |    6 +
- .../gpu/drm/amd/dal/dc/bios/command_table_helper.h |    3 +
- .../dal/dc/bios/dce112/bios_parser_helper_dce112.c |  480 +++++
- .../dal/dc/bios/dce112/bios_parser_helper_dce112.h |   34 +
- .../dc/bios/dce112/command_table_helper_dce112.c   |  417 +++++
- .../dc/bios/dce112/command_table_helper_dce112.h   |   34 +
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c |  206 +++
- drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c  |    7 +
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |   22 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |    1 +
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |    2 +-
- drivers/gpu/drm/amd/dal/dc/dce112/Makefile         |   10 +
- .../drm/amd/dal/dc/dce112/dce112_clock_source.c    |  266 +++
- .../drm/amd/dal/dc/dce112/dce112_clock_source.h    |   52 +
- .../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c  |  883 +++++++++
- .../gpu/drm/amd/dal/dc/dce112/dce112_compressor.h  |   84 +
- .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c    |  178 ++
- .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.h    |   36 +
- .../drm/amd/dal/dc/dce112/dce112_link_encoder.c    |  116 ++
- .../drm/amd/dal/dc/dce112/dce112_link_encoder.h    |   41 +
- .../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c   |  455 +++++
- .../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h   |   38 +
- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    | 1404 ++++++++++++++
- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.h    |   42 +
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h     |    5 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c       |    3 +
- drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c     |    3 +
- drivers/gpu/drm/amd/dal/dc/gpu/Makefile            |    8 +
- .../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c |   89 +
- .../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h |   33 +
- .../amd/dal/dc/gpu/dce112/display_clock_dce112.c   |  964 ++++++++++
- .../amd/dal/dc/gpu/dce112/display_clock_dce112.h   |   54 +
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c         |    5 +-
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h   |    4 +-
- drivers/gpu/drm/amd/dal/dc/irq/irq_service.c       |    4 +
- drivers/gpu/drm/amd/dal/include/dal_asic_id.h      |   14 +
- drivers/gpu/drm/amd/dal/include/dal_types.h        |    3 +
- .../drm/amd/dal/include/display_clock_interface.h  |    6 +
- 57 files changed, 9146 insertions(+), 8 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/Makefile
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
-index 5112ec9..a718674 100644
---- a/drivers/gpu/drm/amd/dal/dc/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
-@@ -5,6 +5,10 @@
- DC_LIBS = adapter asic_capability audio basics bios calcs \
- gpio gpu i2caux irq virtual
- 
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_2
-+DC_LIBS += dce112
-+endif
-+
- ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- DC_LIBS += dce110
- endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-index db1f0e8..370323e 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
-@@ -25,6 +25,10 @@ ifdef CONFIG_DRM_AMD_DAL_DCE11_0
- AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce110/hw_ctx_adapter_service_dce110.o
- endif
- 
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_2
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce112/hw_ctx_adapter_service_dce112.o
-+endif
-+
- ###############################################################################
- # FPGA Diagnositcs
- ###############################################################################
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index f7aea01..308d456 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -49,6 +49,10 @@
- #include "dce110/hw_ctx_adapter_service_dce110.h"
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "dce112/hw_ctx_adapter_service_dce112.h"
-+#endif
-+
- #include "diagnostics/hw_ctx_adapter_service_diag.h"
- 
- /*
-@@ -664,6 +668,10 @@ static struct hw_ctx_adapter_service *create_hw_ctx(
- 	case DCE_VERSION_11_0:
- 		return dal_adapter_service_create_hw_ctx_dce110(ctx);
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		return dal_adapter_service_create_hw_ctx_dce112(ctx);
-+#endif
- 	default:
- 		ASSERT_CRITICAL(false);
- 		return NULL;
-@@ -907,6 +915,10 @@ enum dce_version dal_adapter_service_get_dce_version(
- 	case 0x110:
- 		return DCE_VERSION_11_0;
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case 0x112:
-+		return DCE_VERSION_11_2;
-+#endif
- 	default:
- 		ASSERT_CRITICAL(false);
- 		return DCE_VERSION_UNKNOWN;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.c b/drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.c
-new file mode 100644
-index 0000000..f438998
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.c
-@@ -0,0 +1,302 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "../hw_ctx_adapter_service.h"
-+
-+#include "hw_ctx_adapter_service_dce112.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/grph_object_id.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x4819
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static const struct graphics_object_id invalid_go = {
-+	0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN, 0
-+};
-+
-+/* Macro */
-+#define AUDIO_STRAPS_HDMI_ENABLE 0x2
-+
-+#define FROM_HW_CTX(ptr) \
-+	container_of((ptr), struct hw_ctx_adapter_service_dce112, base)
-+
-+static const uint32_t audio_index_reg_offset[] = {
-+	/*CZ has 3 DIGs but 4 audio endpoints*/
-+	mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+	mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
-+};
-+
-+static const uint32_t audio_data_reg_offset[] = {
-+	mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+	mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA,
-+};
-+
-+enum {
-+	MAX_NUMBER_OF_AUDIO_PINS = 4
-+};
-+
-+static void destruct(
-+	struct hw_ctx_adapter_service_dce112 *hw_ctx)
-+{
-+	/* There is nothing to destruct at the moment */
-+	dal_adapter_service_destruct_hw_ctx(&hw_ctx->base);
-+}
-+
-+static void destroy(
-+	struct hw_ctx_adapter_service *ptr)
-+{
-+	struct hw_ctx_adapter_service_dce112 *hw_ctx =
-+		FROM_HW_CTX(ptr);
-+
-+	destruct(hw_ctx);
-+
-+	dm_free(hw_ctx);
-+}
-+
-+/*
-+ * enum_audio_object
-+ *
-+ * @brief enumerate audio object
-+ *
-+ * @param
-+ * const struct hw_ctx_adapter_service *hw_ctx - [in] provides num of endpoints
-+ * uint32_t index - [in] audio index
-+ *
-+ * @return
-+ * grphic object id
-+ */
-+static struct graphics_object_id enum_audio_object(
-+	const struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t index)
-+{
-+	uint32_t number_of_connected_audio_endpoints =
-+		FROM_HW_CTX(hw_ctx)->number_of_connected_audio_endpoints;
-+
-+	if (index >= number_of_connected_audio_endpoints ||
-+			number_of_connected_audio_endpoints == 0)
-+		return invalid_go;
-+	else
-+		return dal_graphics_object_id_init(
-+			AUDIO_ID_INTERNAL_AZALIA,
-+			(enum object_enum_id)(index + 1),
-+			OBJECT_TYPE_AUDIO);
-+}
-+
-+static uint32_t get_number_of_connected_audio_endpoints_multistream(
-+		struct dc_context *ctx)
-+{
-+	uint32_t num_connected_audio_endpoints = 0;
-+	uint32_t i;
-+	uint32_t default_config =
-+	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT;
-+
-+	/* find the total number of streams available via the
-+	 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
-+	 * registers (one for each pin) starting from pin 1
-+	 * up to the max number of audio pins.
-+	 * We stop on the first pin where
-+	 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
-+	 */
-+	for (i = 0; i < MAX_NUMBER_OF_AUDIO_PINS; i++) {
-+		uint32_t value = 0;
-+
-+		set_reg_field_value(value,
-+			default_config,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dm_write_reg(ctx, audio_index_reg_offset[i], value);
-+
-+		value = 0;
-+		value = dm_read_reg(ctx, audio_data_reg_offset[i]);
-+
-+		/* 1 means not supported*/
-+		if (get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
-+		PORT_CONNECTIVITY) == 1)
-+			break;
-+
-+		num_connected_audio_endpoints++;
-+	}
-+
-+	return num_connected_audio_endpoints;
-+
-+}
-+
-+/*
-+ * get_number_of_connected_audio_endpoints
-+ */
-+static uint32_t get_number_of_connected_audio_endpoints(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	uint32_t addr = mmCC_DC_HDMI_STRAPS;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	if (hw_ctx->cached_audio_straps == AUDIO_STRAPS_NOT_ALLOWED)
-+		/* audio straps indicate no audio supported */
-+		return 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	field = get_reg_field_value(
-+			value, CC_DC_HDMI_STRAPS, AUDIO_STREAM_NUMBER);
-+	if (field == 1)
-+		/* multi streams not supported */
-+		return 1;
-+	else if (field == 0)
-+		/* multi streams supported */
-+		return get_number_of_connected_audio_endpoints_multistream(
-+				hw_ctx->ctx);
-+
-+	/* unexpected value */
-+	ASSERT_CRITICAL(false);
-+	return field;
-+}
-+
-+/*
-+ * power_up
-+ *
-+ * @brief
-+ * Determine and cache audio support from register.
-+ *
-+ * @param
-+ * struct hw_ctx_adapter_service *hw_ctx - [in] adapter service hw context
-+ *
-+ * @return
-+ * true if succeed, false otherwise
-+ */
-+static bool power_up(
-+	struct hw_ctx_adapter_service *hw_ctx)
-+{
-+	struct hw_ctx_adapter_service_dce112 *hw_ctx_dce11 =
-+			FROM_HW_CTX(hw_ctx);
-+	/* Allow DP audio all the time
-+	 * without additional pinstrap check on Fusion */
-+
-+	{
-+		uint32_t value = 0;
-+		uint32_t field = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, mmCC_DC_HDMI_STRAPS);
-+		field = get_reg_field_value(
-+				value, CC_DC_HDMI_STRAPS, HDMI_DISABLE);
-+
-+		if (field == 0) {
-+			hw_ctx->cached_audio_straps = AUDIO_STRAPS_DP_HDMI_AUDIO;
-+		} else {
-+			value = dm_read_reg(
-+					hw_ctx->ctx, mmDC_PINSTRAPS);
-+			field = get_reg_field_value(
-+						value,
-+						DC_PINSTRAPS,
-+						DC_PINSTRAPS_AUDIO);
-+
-+			if (field & AUDIO_STRAPS_HDMI_ENABLE)
-+				hw_ctx->cached_audio_straps =
-+					AUDIO_STRAPS_DP_HDMI_AUDIO_ON_DONGLE;
-+			else
-+				hw_ctx->cached_audio_straps =
-+						AUDIO_STRAPS_DP_AUDIO_ALLOWED;
-+		}
-+
-+	}
-+
-+	/* get the number of connected audio endpoints */
-+	hw_ctx_dce11->number_of_connected_audio_endpoints =
-+		get_number_of_connected_audio_endpoints(hw_ctx);
-+
-+	return true;
-+}
-+
-+static void update_audio_connectivity(
-+	struct hw_ctx_adapter_service *hw_ctx,
-+	uint32_t number_of_audio_capable_display_path,
-+	uint32_t number_of_controllers)
-+{
-+	/* this one should be empty on DCE112 */
-+}
-+
-+static const struct hw_ctx_adapter_service_funcs funcs = {
-+	.destroy = destroy,
-+	.power_up = power_up,
-+	.enum_fake_path_resource = NULL,
-+	.enum_stereo_sync_object = NULL,
-+	.enum_sync_output_object = NULL,
-+	.enum_audio_object = enum_audio_object,
-+	.update_audio_connectivity = update_audio_connectivity
-+};
-+
-+static bool construct(
-+	struct hw_ctx_adapter_service_dce112 *hw_ctx,
-+	struct dc_context *ctx)
-+{
-+	if (!dal_adapter_service_construct_hw_ctx(&hw_ctx->base, ctx)) {
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+
-+	hw_ctx->base.funcs = &funcs;
-+	hw_ctx->number_of_connected_audio_endpoints = 0;
-+
-+	return true;
-+}
-+
-+struct hw_ctx_adapter_service *
-+	dal_adapter_service_create_hw_ctx_dce112(
-+			struct dc_context *ctx)
-+{
-+	struct hw_ctx_adapter_service_dce112 *hw_ctx =
-+			dm_alloc(sizeof(struct hw_ctx_adapter_service_dce112));
-+
-+	if (!hw_ctx) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if (construct(hw_ctx, ctx))
-+		return &hw_ctx->base;
-+
-+	ASSERT_CRITICAL(false);
-+
-+	dm_free(hw_ctx);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.h b/drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.h
-new file mode 100644
-index 0000000..bc60030
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/dce112/hw_ctx_adapter_service_dce112.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_ADAPTER_SERVICE_DCE112_H__
-+#define __DAL_HW_CTX_ADAPTER_SERVICE_DCE112_H__
-+
-+struct hw_ctx_adapter_service_dce112 {
-+	struct hw_ctx_adapter_service base;
-+	uint32_t number_of_connected_audio_endpoints;
-+};
-+
-+struct hw_ctx_adapter_service *
-+	dal_adapter_service_create_hw_ctx_dce112(
-+			struct dc_context *ctx);
-+
-+#endif /* __DAL_HW_CTX_ADAPTER_SERVICE_DCE112_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-index b243542..e80de2a 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
-@@ -46,3 +46,12 @@ AMD_DAL_ASIC_CAPABILITY_DCE11 = \
- 
- AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
- endif
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_2
-+ASIC_CAPABILITY_DCE112 = polaris10_asic_capability.o
-+
-+AMD_DAL_ASIC_CAPABILITY_DCE112 = \
-+	$(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE112))
-+
-+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE112)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-index 75e0e27..aeabfc6 100644
---- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
-@@ -44,6 +44,10 @@
- #include "carrizo_asic_capability.h"
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "polaris10_asic_capability.h"
-+#endif
-+
- /*
-  * Initializes asic_capability instance.
-  */
-@@ -108,7 +112,8 @@ static bool construct(
- 		asic_supported = true;
- #endif
- 		break;
-- 	case FAMILY_VI:
-+
-+	case FAMILY_VI:
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 		if (ASIC_REV_IS_TONGA_P(init->hw_internal_rev) ||
- 				ASIC_REV_IS_FIJI_P(init->hw_internal_rev)) {
-@@ -117,7 +122,15 @@ static bool construct(
- 			break;
- 		}
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+		if (ASIC_REV_IS_POLARIS10_P(init->hw_internal_rev) ||
-+				ASIC_REV_IS_POLARIS11_M(init->hw_internal_rev)) {
-+			polaris10_asic_capability_create(cap, init);
-+			asic_supported = true;
-+		}
-+#endif
- 		break;
-+
- 	default:
- 		/* unsupported "chip_family" */
- 		break;
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
-new file mode 100644
-index 0000000..9e4fdfa
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
-@@ -0,0 +1,146 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/asic_capability_interface.h"
-+#include "include/asic_capability_types.h"
-+
-+#include "polaris10_asic_capability.h"
-+
-+#include "atom.h"
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+#include "dal_asic_id.h"
-+
-+#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
-+
-+/*
-+ * carrizo_asic_capability_create
-+ *
-+ * Create and initiate Carrizo capability.
-+ */
-+void polaris10_asic_capability_create(struct asic_capability *cap,
-+	struct hw_asic_id *init)
-+{
-+	uint32_t e_fuse_setting;
-+	/* ASIC data */
-+	if (ASIC_REV_IS_POLARIS11_M(init->hw_internal_rev)) {
-+		cap->data[ASIC_DATA_CONTROLLERS_NUM] = 5;
-+		cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 5;
-+		cap->data[ASIC_DATA_LINEBUFFER_NUM] = 5;
-+		cap->data[ASIC_DATA_DIGFE_NUM] = 5;
-+		cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 7;
-+		cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 5;
-+		cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 5;
-+	} else {
-+		cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
-+		cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
-+		cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
-+		cap->data[ASIC_DATA_DIGFE_NUM] = 6;
-+		cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 8;
-+		cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 6;
-+		cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 6;
-+	}
-+
-+	cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
-+	cap->data[ASIC_DATA_DCE_VERSION] = 0x112; /* DCE 11 */
-+	cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 5124 * 144;
-+	cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
-+
-+	cap->data[ASIC_DATA_MC_LATENCY] = 3000;
-+	cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
-+	cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-+
-+	cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
-+	cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
-+	cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
-+
-+	cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
-+
-+	/* ASIC basic capability */
-+	cap->caps.IS_FUSION = true;
-+	cap->caps.DP_MST_SUPPORTED = true;
-+	cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
-+	cap->caps.MIRABILIS_SUPPORTED = true;
-+	cap->caps.NO_VCC_OFF_HPD_POLLING = true;
-+	cap->caps.VCE_SUPPORTED = true;
-+	cap->caps.HPD_CHECK_FOR_EDID = true;
-+	cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
-+	cap->caps.SUPPORT_8BPP = false;
-+
-+	/* ASIC stereo 3d capability */
-+	cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
-+	cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
-+	cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
-+	cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
-+	cap->stereo_3d_caps.INTERLEAVE = true;
-+
-+	e_fuse_setting = dm_read_index_reg(cap->ctx,CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-+
-+	/* Bits [28:27]*/
-+	switch ((e_fuse_setting >> 27) & 0x3) {
-+	case 0:
-+		/*both VCE engine are working*/
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
-+		/*TODO:
-+		cap->caps.wirelessLowVCEPerformance = false;
-+		m_AsicCaps.vceInstance0Enabled = true;
-+		m_AsicCaps.vceInstance1Enabled = true;*/
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 1:
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+		/*TODO:
-+		m_AsicCaps.wirelessLowVCEPerformance = false;
-+		m_AsicCaps.vceInstance1Enabled = true;*/
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 2:
-+		cap->caps.VCE_SUPPORTED = true;
-+		cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
-+		/*TODO:
-+		m_AsicCaps.wirelessLowVCEPerformance = false;
-+		m_AsicCaps.vceInstance0Enabled = true;*/
-+		cap->caps.NEED_MC_TUNING = true;
-+		break;
-+
-+	case 3:
-+		/* VCE_DISABLE = 0x3  - both VCE
-+		 * instances are in harvesting,
-+		 * no VCE supported any more.
-+		 */
-+		cap->caps.VCE_SUPPORTED = false;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
-new file mode 100644
-index 0000000..c8aebe1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_POLARIS10_ASIC_CAPABILITY_H__
-+#define __DAL_POLARIS10_ASIC_CAPABILITY_H__
-+
-+/* Forward declaration */
-+struct asic_capability;
-+
-+/* Create and initialize Polaris10 data */
-+void polaris10_asic_capability_create(struct asic_capability *cap,
-+	struct hw_asic_id *init);
-+
-+#endif /* __DAL_POLARIS10_ASIC_CAPABILITY_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-index 2433d90..9a9a64c 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-@@ -32,3 +32,11 @@ AMD_DAL_AUDIO_DCE11 = $(addprefix $(AMDDALPATH)/dc/audio/dce110/,$(AUDIO_DCE11))
- 
- AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE11)
- endif
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_2
-+AUDIO_DCE112 = audio_dce112.o hw_ctx_audio_dce112.o
-+
-+AMD_DAL_AUDIO_DCE112 = $(addprefix $(AMDDALPATH)/dc/audio/dce112/,$(AUDIO_DCE112))
-+
-+AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE112)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index c297d95..a8137e0 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -40,6 +40,11 @@
- #include "dce110/hw_ctx_audio_dce110.h"
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "dce112/audio_dce112.h"
-+#include "dce112/hw_ctx_audio_dce112.h"
-+#endif
-+
- /***** static function : only used within audio.c *****/
- 
- /* stub for hook functions */
-@@ -281,6 +286,10 @@ struct audio *dal_audio_create(
- 	case DCE_VERSION_11_0:
- 		return dal_audio_create_dce110(init_data);
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		return dal_audio_create_dce112(init_data);
-+#endif
- 	default:
- 		BREAK_TO_DEBUGGER();
- 		return NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c b/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
-new file mode 100644
-index 0000000..66c32b0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
-@@ -0,0 +1,451 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "audio_dce112.h"
-+
-+/***** static functions  *****/
-+
-+static void destruct(struct audio_dce112 *audio)
-+{
-+	/*release memory allocated for hw_ctx -- allocated is initiated
-+	 *by audio_dce112 power_up
-+	 *audio->base->hw_ctx = NULL is done within hw-ctx->destroy
-+	 */
-+	if (audio->base.hw_ctx)
-+		audio->base.hw_ctx->funcs->destroy(&(audio->base.hw_ctx));
-+
-+	/* reset base_audio_block */
-+	dal_audio_destruct_base(&audio->base);
-+}
-+
-+static void destroy(struct audio **ptr)
-+{
-+	struct audio_dce112 *audio = NULL;
-+
-+	audio = container_of(*ptr, struct audio_dce112, base);
-+
-+	destruct(audio);
-+
-+	/* release memory allocated for audio_dce112*/
-+	dm_free(audio);
-+	*ptr = NULL;
-+}
-+
-+/* The inital call of hook function comes from audio object level.
-+ *The passing object handle "struct audio *audio" point to base object
-+ *already.There is not need to get base object from audio_dce112.
-+ */
-+
-+/**
-+* setup
-+*
-+* @brief
-+*  setup Audio HW block, to be called by dal_audio_setup
-+*
-+*/
-+static enum audio_result setup(
-+	struct audio *audio,
-+	struct audio_output *output,
-+	struct audio_info *info)
-+{
-+	switch (output->signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/*setup HDMI audio engine*/
-+		audio->hw_ctx->funcs->enable_afmt_clock(
-+			audio->hw_ctx,
-+			output->engine_id,
-+			true);
-+		audio->hw_ctx->funcs->setup_hdmi_audio(
-+			audio->hw_ctx, output->engine_id, &output->crtc_info);
-+
-+		audio->hw_ctx->funcs->setup_azalia(
-+			audio->hw_ctx,
-+			output->engine_id,
-+			output->signal,
-+			&output->crtc_info,
-+			&output->pll_info,
-+			info);
-+		break;
-+
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* setup Azalia block for Wireless Display - This
-+			is different than for wired
-+			displays because there is no
-+			DIG to program.*/
-+		/*TODO:
-+		audio->hw_ctx->funcs->setup_azalia_for_vce(
-+			audio->hw_ctx,
-+			audio->signal,
-+			audio->crtc_info,
-+			info);
-+		*/
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* setup DP audio engine will be done at enable output */
-+
-+		/* setup Azalia block*/
-+		audio->hw_ctx->funcs->setup_azalia(
-+			audio->hw_ctx,
-+			output->engine_id,
-+			output->signal,
-+			&output->crtc_info,
-+			&output->pll_info,
-+			info);
-+
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* enable_output
-+*
-+* @brief
-+*  enable Audio HW block, to be called by dal_audio_enable_output
-+*/
-+static enum audio_result enable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	/* enable audio output */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP: {
-+			/* enable AFMT clock before enable audio*/
-+			audio->hw_ctx->funcs->enable_afmt_clock(
-+				audio->hw_ctx, engine_id, true);
-+			/* setup DP audio engine */
-+			audio->hw_ctx->funcs->setup_dp_audio(
-+				audio->hw_ctx, engine_id);
-+			/* enabl DP audio packets will be done at unblank */
-+			audio->hw_ctx->funcs->enable_dp_audio(
-+				audio->hw_ctx, engine_id);
-+		}
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* route audio to VCE block */
-+		audio->hw_ctx->funcs->setup_vce_audio(audio->hw_ctx);
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* disable_output
-+*
-+* @brief
-+*  disable Audio HW block, to be called by dal_audio_disable_output
-+*
-+*/
-+static enum audio_result disable_output(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_WIRELESS:
-+		/* disable HDMI audio */
-+		audio->hw_ctx->
-+			funcs->disable_azalia_audio(
-+					audio->hw_ctx, engine_id);
-+		audio->hw_ctx->
-+			funcs->enable_afmt_clock(
-+					audio->hw_ctx, engine_id,
-+					false);
-+
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP: {
-+			/* disable DP audio */
-+			audio->hw_ctx->funcs->disable_dp_audio(
-+				audio->hw_ctx, engine_id);
-+			audio->hw_ctx->funcs->disable_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+			audio->hw_ctx->funcs->enable_afmt_clock(
-+				audio->hw_ctx, engine_id, false);
-+		}
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* unmute
-+*
-+* @brief
-+*  unmute audio, to be called by dal_audio_unmute
-+*
-+*/
-+static enum audio_result unmute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* unmute Azalia audio */
-+		audio->hw_ctx->funcs->unmute_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/*Do nothing for wireless display*/
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* mute
-+*
-+* @brief
-+*  mute audio, to be called  by dal_audio_nmute
-+*
-+*/
-+static enum audio_result mute(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		/* mute Azalia audio */
-+		audio->hw_ctx->funcs->mute_azalia_audio(
-+				audio->hw_ctx, engine_id);
-+		break;
-+	case SIGNAL_TYPE_WIRELESS:
-+		/*Do nothing for wireless display*/
-+		break;
-+	default:
-+		return AUDIO_RESULT_ERROR;
-+	}
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/**
-+* initialize
-+*
-+* @brief
-+*  Perform SW initialization - create audio hw context. Then do HW
-+*  initialization. this function is called at dal_audio_power_up.
-+*
-+*/
-+static enum audio_result initialize(
-+	struct audio *audio)
-+{
-+	uint8_t audio_endpoint_enum_id = 0;
-+
-+	audio_endpoint_enum_id = audio->id.enum_id;
-+
-+	/* HW CTX already create*/
-+	if (audio->hw_ctx != NULL)
-+		return AUDIO_RESULT_OK;
-+
-+	audio->hw_ctx = dal_hw_ctx_audio_dce112_create(
-+			audio->ctx,
-+			audio_endpoint_enum_id);
-+
-+	if (audio->hw_ctx == NULL)
-+		return AUDIO_RESULT_ERROR;
-+
-+	/* override HW default settings */
-+	audio->hw_ctx->funcs->hw_initialize(audio->hw_ctx);
-+
-+	return AUDIO_RESULT_OK;
-+}
-+
-+/* enable multi channel split */
-+static void enable_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	audio->hw_ctx->funcs->setup_channel_splitting_mapping(
-+		audio->hw_ctx,
-+		engine_id,
-+		signal,
-+		audio_mapping, enable);
-+}
-+
-+/* get current multi channel split. */
-+static enum audio_result get_channel_splitting_mapping(
-+	struct audio *audio,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	if (audio->hw_ctx->funcs->get_channel_splitting_mapping(
-+		audio->hw_ctx, engine_id, audio_mapping)) {
-+		return AUDIO_RESULT_OK;
-+	} else {
-+		return AUDIO_RESULT_ERROR;
-+	}
-+}
-+
-+/**
-+* set_unsolicited_response_payload
-+*
-+* @brief
-+*  Set payload value for the unsolicited response
-+*/
-+static void set_unsolicited_response_payload(
-+	struct audio *audio,
-+	enum audio_payload payload)
-+{
-+	audio->hw_ctx->funcs->set_unsolicited_response_payload(
-+			audio->hw_ctx, payload);
-+}
-+
-+/**
-+* setup_audio_wall_dto
-+*
-+* @brief
-+*  Update audio source clock from hardware context.
-+*
-+*/
-+static void setup_audio_wall_dto(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	audio->hw_ctx->funcs->setup_audio_wall_dto(
-+		audio->hw_ctx, signal, crtc_info, pll_info);
-+}
-+
-+/**
-+* get_supported_features
-+*
-+* @brief
-+*  options and features supported by Audio
-+*  returns supported engines, signals.
-+*  features are reported for HW audio/Azalia block rather then Audio object
-+*  itself the difference for DCE6.x is that MultiStream Audio is now supported
-+*
-+*/
-+static struct audio_feature_support get_supported_features(struct audio *audio)
-+{
-+	struct audio_feature_support afs = {0};
-+
-+	afs.ENGINE_DIGA = 1;
-+	afs.ENGINE_DIGB = 1;
-+	afs.ENGINE_DIGC = 1;
-+	afs.MULTISTREAM_AUDIO = 1;
-+
-+	return afs;
-+}
-+
-+static const struct audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup = setup,
-+	.enable_output = enable_output,
-+	.disable_output = disable_output,
-+	.unmute = unmute,
-+	.mute = mute,
-+	.initialize = initialize,
-+	.enable_channel_splitting_mapping =
-+		enable_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.setup_audio_wall_dto = setup_audio_wall_dto,
-+	.get_supported_features = get_supported_features,
-+};
-+
-+static bool construct(
-+	struct audio_dce112 *audio,
-+	const struct audio_init_data *init_data)
-+{
-+	struct audio *base = &audio->base;
-+
-+	/* base audio construct*/
-+	if (!dal_audio_construct_base(base, init_data))
-+		return false;
-+
-+	/*vtable methods*/
-+	base->funcs = &funcs;
-+	return true;
-+}
-+
-+/* --- audio scope functions  --- */
-+
-+struct audio *dal_audio_create_dce112(
-+	const struct audio_init_data *init_data)
-+{
-+	/*allocate memory for audio_dce112 */
-+	struct audio_dce112 *audio = dm_alloc(sizeof(*audio));
-+
-+	if (audio == NULL) {
-+		ASSERT_CRITICAL(audio);
-+		return NULL;
-+	}
-+	/*pointer to base_audio_block of audio_dce112 ==> audio base object */
-+	if (construct(audio, init_data))
-+		return &audio->base;
-+
-+	dal_logger_write(
-+		init_data->ctx->logger,
-+		LOG_MAJOR_ERROR,
-+		LOG_MINOR_COMPONENT_AUDIO,
-+		"Failed to create audio object for DCE11\n");
-+
-+	 /*release memory allocated if fail */
-+	dm_free(audio);
-+	return NULL;
-+}
-+
-+/* Do not need expose construct_dce112 and destruct_dce112 becuase there is
-+ *derived object after dce112
-+ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h b/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
-new file mode 100644
-index 0000000..7c8d71c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_AUDIO_DCE_112_H__
-+#define __DAL_AUDIO_DCE_112_H__
-+
-+#include "audio/audio.h"
-+#include "audio/hw_ctx_audio.h"
-+#include "audio/dce112/hw_ctx_audio_dce112.h"
-+
-+struct audio_dce112 {
-+	struct audio base;
-+	/* dce-specific members are following */
-+	/* none */
-+};
-+
-+struct audio *dal_audio_create_dce112(const struct audio_init_data *init_data);
-+
-+#endif   /*__DAL_AUDIO_DCE_112_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c b/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c
-new file mode 100644
-index 0000000..95cb86f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.c
-@@ -0,0 +1,1923 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+#include "../hw_ctx_audio.h"
-+#include "hw_ctx_audio_dce112.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+#define FROM_BASE(ptr) \
-+	container_of((ptr), struct hw_ctx_audio_dce112, base)
-+
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
-+#define DP_AUDIO_DTO_MODULE_WITHOUT_SS 360
-+#define DP_AUDIO_DTO_PHASE_WITHOUT_SS 24
-+
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUDIO_FRONT_END 0
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__REGISTER_PROGRAMMABLE 2
-+
-+#define FIRST_AUDIO_STREAM_ID 1
-+
-+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_AUDIO, \
-+			"Audio:%s()\n", __func__)
-+
-+static const uint32_t engine_offset[] = {
-+	0,
-+	mmDIG1_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG2_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG3_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG4_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL,
-+	mmDIG5_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
-+};
-+
-+static void destruct(
-+	struct hw_ctx_audio_dce112 *hw_ctx_dce112)
-+{
-+	dal_audio_destruct_hw_ctx_audio(&hw_ctx_dce112->base);
-+}
-+
-+static void destroy(
-+	struct hw_ctx_audio **ptr)
-+{
-+	struct hw_ctx_audio_dce112 *hw_ctx_dce112;
-+
-+	hw_ctx_dce112 = container_of(
-+		*ptr, struct hw_ctx_audio_dce112, base);
-+
-+	destruct(hw_ctx_dce112);
-+	/* release memory allocated for struct hw_ctx_audio_dce112 */
-+	dm_free(hw_ctx_dce112);
-+
-+	*ptr = NULL;
-+}
-+
-+/* ---  helpers --- */
-+static void write_indirect_azalia_reg(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t reg_index,
-+	uint32_t reg_data)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+		set_reg_field_value(value, reg_index,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+		value = 0;
-+		set_reg_field_value(value, reg_data,
-+			AZALIA_F0_CODEC_ENDPOINT_DATA,
-+			AZALIA_ENDPOINT_REG_DATA);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	dal_logger_write(
-+		hw_ctx->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_AUDIO,
-+		"AUDIO:write_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, reg_data);
-+}
-+
-+static uint32_t read_indirect_azalia_reg(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t reg_index)
-+{
-+	uint32_t ret_val = 0;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index;
-+
-+		set_reg_field_value(value, reg_index,
-+			AZALIA_F0_CODEC_ENDPOINT_INDEX,
-+			AZALIA_ENDPOINT_REG_INDEX);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	{
-+		addr =
-+			FROM_BASE(hw_ctx)->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		ret_val = value;
-+	}
-+
-+	dal_logger_write(
-+		hw_ctx->ctx->logger,
-+		LOG_MAJOR_HW_TRACE,
-+		LOG_MINOR_HW_TRACE_AUDIO,
-+		"AUDIO:read_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, ret_val);
-+
-+	return ret_val;
-+}
-+
-+/* expose/not expose HBR capability to Audio driver */
-+static void set_high_bit_rate_capable(
-+	const struct hw_ctx_audio *hw_ctx,
-+	bool capable)
-+{
-+	uint32_t value = 0;
-+
-+	/* set high bit rate audio capable*/
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
-+
-+	set_reg_field_value(value, capable,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		HBR_CAPABLE);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		value);
-+}
-+
-+/* set HBR channnel count *
-+static void set_hbr_channel_count(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t hbr_channel_count)
-+{
-+	uint32_t value = 0;
-+
-+	if (hbr_channel_count > 7)
-+		return;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+
-+	set_reg_field_value(value, hbr_channel_count,
-+		AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+		HBR_CHANNEL_COUNT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL, value);
-+
-+}
-+
-+*set compressed audio channel count *
-+static void set_compressed_audio_channel_count(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t compressed_audio_ch_count)
-+{
-+	uint32_t value = 0;
-+	if (compressed_audio_ch_count > 7)
-+		return;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL);
-+
-+	set_reg_field_value(value, compressed_audio_ch_count,
-+		AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+		COMPRESSED_CHANNEL_COUNT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL,
-+		value);
-+
-+}
-+*/
-+/* set video latency in in ms/2+1 */
-+static void set_video_latency(
-+	const struct hw_ctx_audio *hw_ctx,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if ((latency_in_ms < 0) || (latency_in_ms > 255))
-+		return;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		VIDEO_LIPSYNC);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+
-+}
-+
-+/* set audio latency in in ms/2+1 */
-+static void set_audio_latency(
-+	const struct hw_ctx_audio *hw_ctx,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if (latency_in_ms < 0)
-+		latency_in_ms = 0;
-+
-+	if (latency_in_ms > 255)
-+		latency_in_ms = 255;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		AUDIO_LIPSYNC);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+
-+}
-+
-+/* enable HW/SW Sync */
-+/*static void enable_hw_sw_sync(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+		union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+	value = dal_read_reg(mmAZALIA_CYCLIC_BUFFER_SYNC);
-+	value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 1;
-+	dal_write_reg(mmAZALIA_CYCLIC_BUFFER_SYNC, value);
-+}*/
-+
-+/* disable HW/SW Sync */
-+/*static void disable_hw_sw_sync(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	union AZALIA_CYCLIC_BUFFER_SYNC value;
-+
-+	value = dal_read_reg(
-+		mmAZALIA_CYCLIC_BUFFER_SYNC);
-+	value.bits.CYCLIC_BUFFER_SYNC_ENABLE = 0;
-+	dal_write_reg(
-+		mmAZALIA_CYCLIC_BUFFER_SYNC, value);
-+}*/
-+
-+/* update hardware with software's current position in cyclic buffer */
-+/*static void update_sw_write_ptr(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t offset)
-+{
-+		union AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER value;
-+
-+	value = dal_read_reg(
-+		mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER);
-+	value.bits.APPLICATION_POSITION_IN_CYCLIC_BUFFER = offset;
-+	dal_write_reg(
-+		mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER,
-+		value);
-+}*/
-+
-+/* update Audio/Video association */
-+/*static void update_av_association(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	uint32_t displayId)
-+{
-+
-+}*/
-+
-+/* ---  hook functions --- */
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info);
-+
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info);
-+
-+static void setup_audio_wall_dto(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	struct azalia_clock_info clock_info = { 0 };
-+
-+	uint32_t value = dm_read_reg(hw_ctx->ctx, mmDCCG_AUDIO_DTO_SOURCE);
-+
-+	/* TODO: GraphicsObject\inc\GraphicsObjectDefs.hpp(131):
-+	 *inline bool isHdmiSignal(SignalType signal)
-+	 *if (Signals::isHdmiSignal(signal))
-+	 */
-+	if (dc_is_hdmi_signal(signal)) {
-+		/*DTO0 Programming goal:
-+		-generate 24MHz, 128*Fs from 24MHz
-+		-use DTO0 when an active HDMI port is connected
-+		(optionally a DP is connected) */
-+
-+		/* calculate DTO settings */
-+		get_azalia_clock_info_hdmi(
-+			hw_ctx,
-+			crtc_info->requested_pixel_clock,
-+			crtc_info->calculated_pixel_clock,
-+			&clock_info);
-+
-+		/* On TN/SI, Program DTO source select and DTO select before
-+		programming DTO modulo and DTO phase. These bits must be
-+		programmed first, otherwise there will be no HDMI audio at boot
-+		up. This is a HW sequence change (different from old ASICs).
-+		Caution when changing this programming sequence.
-+
-+		HDMI enabled, using DTO0
-+		program master CRTC for DTO0 */
-+		{
-+			set_reg_field_value(value,
-+				pll_info->dto_source - DTO_SOURCE_ID0,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO0_SOURCE_SEL);
-+
-+			set_reg_field_value(value,
-+				0,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO_SOURCE, value);
-+		}
-+
-+		/* module */
-+		{
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_MODULE);
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_module,
-+				DCCG_AUDIO_DTO0_MODULE,
-+				DCCG_AUDIO_DTO0_MODULE);
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_MODULE, value);
-+		}
-+
-+		/* phase */
-+		{
-+			value = 0;
-+
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_PHASE);
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_phase,
-+				DCCG_AUDIO_DTO0_PHASE,
-+				DCCG_AUDIO_DTO0_PHASE);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO0_PHASE, value);
-+		}
-+
-+	} else {
-+		/*DTO1 Programming goal:
-+		-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-+		-default is to used DTO1, and switch to DTO0 when an audio
-+		master HDMI port is connected
-+		-use as default for DP
-+
-+		calculate DTO settings */
-+		get_azalia_clock_info_dp(
-+			hw_ctx,
-+			crtc_info->requested_pixel_clock,
-+			pll_info,
-+			&clock_info);
-+
-+		/* Program DTO select before programming DTO modulo and DTO
-+		phase. default to use DTO1 */
-+
-+		{
-+			set_reg_field_value(value, 1,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL);
-+			/*dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value)*/
-+
-+			/* Select 512fs for DP TODO: web register definition
-+			does not match register header file
-+			set_reg_field_value(value, 1,
-+				DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO2_USE_512FBR_DTO);
-+			*/
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO_SOURCE, value);
-+		}
-+
-+		/* module */
-+		{
-+			value = 0;
-+
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_MODULE);
-+
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_module,
-+				DCCG_AUDIO_DTO1_MODULE,
-+				DCCG_AUDIO_DTO1_MODULE);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_MODULE, value);
-+		}
-+
-+		/* phase */
-+		{
-+			value = 0;
-+
-+			value = dm_read_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_PHASE);
-+
-+			set_reg_field_value(value,
-+				clock_info.audio_dto_phase,
-+				DCCG_AUDIO_DTO1_PHASE,
-+				DCCG_AUDIO_DTO1_PHASE);
-+
-+			dm_write_reg(hw_ctx->ctx,
-+					mmDCCG_AUDIO_DTO1_PHASE, value);
-+		}
-+
-+		/* DAL2 code separate DCCG_AUDIO_DTO_SEL and
-+		DCCG_AUDIO_DTO2_USE_512FBR_DTO programming into two different
-+		location. merge together should not hurt */
-+		/*value.bits.DCCG_AUDIO_DTO2_USE_512FBR_DTO = 1;
-+		dal_write_reg(mmDCCG_AUDIO_DTO_SOURCE, value);*/
-+	}
-+}
-+
-+/* setup HDMI audio */
-+static void setup_hdmi_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	struct audio_clock_info audio_clock_info = {0};
-+	uint32_t max_packets_per_line;
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* For now still do calculation, although this field is ignored when
-+	above HDMI_PACKET_GEN_VERSION set to 1 */
-+	max_packets_per_line =
-+		dal_audio_hw_ctx_calc_max_audio_packets_per_line(
-+			hw_ctx,
-+			crtc_info);
-+
-+	/* HDMI_AUDIO_PACKET_CONTROL */
-+	{
-+		addr =
-+			mmHDMI_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, max_packets_per_line,
-+			HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_PACKETS_PER_LINE);
-+		/* still apply RS600's default setting which is 1. */
-+		set_reg_field_value(value, 1,
-+			HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_DELAY_EN);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+			AFMT_AUDIO_PACKET_CONTROL,
-+			AFMT_60958_CS_UPDATE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 0,
-+				AFMT_AUDIO_PACKET_CONTROL2,
-+				AFMT_AUDIO_LAYOUT_OVRD);
-+
-+		/*Register field changed.*/
-+		set_reg_field_value(value, 0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_60958_OSF_OVRD);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* HDMI_ACR_PACKET_CONTROL */
-+	{
-+		addr = mmHDMI_ACR_PACKET_CONTROL + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 1,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUTO_SEND);
-+
-+		/* Set HDMI_ACR_SOURCE to 0, to use hardwre
-+		 *  computed CTS values.*/
-+		set_reg_field_value(value, 0,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_SOURCE);
-+
-+		/* For now clear HDMI_ACR_AUDIO_PRIORITY =>ACR packet has
-+		higher priority over Audio Sample */
-+		set_reg_field_value(value, 0,
-+			HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUDIO_PRIORITY);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Program audio clock sample/regeneration parameters */
-+	if (dal_audio_hw_ctx_get_audio_clock_info(
-+		hw_ctx,
-+		crtc_info->color_depth,
-+		crtc_info->requested_pixel_clock,
-+		crtc_info->calculated_pixel_clock,
-+		&audio_clock_info)) {
-+
-+		/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
-+		{
-+			addr = mmHDMI_ACR_32_0 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+			set_reg_field_value(value, audio_clock_info.cts_32khz,
-+				HDMI_ACR_32_0,
-+				HDMI_ACR_CTS_32);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
-+		{
-+			addr = mmHDMI_ACR_32_1 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_32khz,
-+				HDMI_ACR_32_1,
-+				HDMI_ACR_N_32);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
-+		{
-+			addr = mmHDMI_ACR_44_0 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.cts_44khz,
-+				HDMI_ACR_44_0,
-+				HDMI_ACR_CTS_44);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
-+		{
-+			addr = mmHDMI_ACR_44_1 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_44khz,
-+				HDMI_ACR_44_1,
-+				HDMI_ACR_N_44);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
-+		{
-+			addr = mmHDMI_ACR_48_0 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.cts_48khz,
-+				HDMI_ACR_48_0,
-+				HDMI_ACR_CTS_48);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
-+		{
-+			addr = mmHDMI_ACR_48_1 + engine_offset[engine_id];
-+
-+			value = dm_read_reg(hw_ctx->ctx, addr);
-+			set_reg_field_value(value, audio_clock_info.n_48khz,
-+				HDMI_ACR_48_1,
-+				HDMI_ACR_N_48);
-+
-+			dm_write_reg(hw_ctx->ctx, addr, value);
-+		}
-+
-+		/* Video driver cannot know in advance which sample rate will
-+		be used by HD Audio driver
-+		HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
-+		programmed below in interruppt callback */
-+	} /* if */
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
-+	AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	{
-+		addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 1,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CHANNEL_NUMBER_L);
-+
-+		 /*HW default */
-+		set_reg_field_value(value, 0,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
-+	{
-+		addr = mmAFMT_60958_1 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 2,
-+			AFMT_60958_1,
-+			AFMT_60958_CS_CHANNEL_NUMBER_R);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/*AFMT_60958_2 now keep this settings until
-+	 *  Programming guide comes out*/
-+	{
-+		addr = mmAFMT_60958_2 + engine_offset[engine_id];
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value, 3,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_2);
-+
-+		set_reg_field_value(value, 4,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_3);
-+
-+		set_reg_field_value(value, 5,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_4);
-+
-+		set_reg_field_value(value, 6,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_5);
-+
-+		set_reg_field_value(value, 7,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_6);
-+
-+		set_reg_field_value(value, 8,
-+			AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_7);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+ /* setup DP audio */
-+static void setup_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	/* --- DP Audio packet configurations --- */
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* ATP Configuration */
-+	{
-+		addr = mmDP_SEC_AUD_N + engine_offset[engine_id];
-+
-+		set_reg_field_value(value,
-+			DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT,
-+			DP_SEC_AUD_N,
-+			DP_SEC_AUD_N);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Async/auto-calc timestamp mode */
-+	{
-+		addr = mmDP_SEC_TIMESTAMP +
-+			engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		set_reg_field_value(value,
-+			DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC,
-+			DP_SEC_TIMESTAMP,
-+			DP_SEC_TIMESTAMP_MODE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* --- The following are the registers
-+	 *  copied from the SetupHDMI --- */
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	{
-+		addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+			engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			1,
-+			AFMT_AUDIO_PACKET_CONTROL,
-+			AFMT_60958_CS_UPDATE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	{
-+		addr =
-+			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_LAYOUT_OVRD);
-+
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_60958_OSF_OVRD);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_INFOFRAME_CONTROL0 */
-+	{
-+		addr =
-+			mmAFMT_INFOFRAME_CONTROL0 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value,
-+			1,
-+			AFMT_INFOFRAME_CONTROL0,
-+			AFMT_AUDIO_INFO_UPDATE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	{
-+		addr = mmAFMT_60958_0 + engine_offset[engine_id];
-+
-+		value = 0;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+		set_reg_field_value(value,
-+			0,
-+			AFMT_60958_0,
-+			AFMT_60958_CS_CLOCK_ACCURACY);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+ /* setup VCE audio */
-+static void setup_vce_audio(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	struct dc_context *ctx = hw_ctx->ctx;
-+
-+	NOT_IMPLEMENTED();
-+
-+	/*TODO:
-+	const uint32_t addr = mmDOUT_DCE_VCE_CONTROL;
-+	uint32_t value = 0;
-+
-+	value = dal_read_reg(hw_ctx->ctx,
-+			addr);
-+
-+	set_reg_field_value(value,
-+		FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+		DOUT_DCE_VCE_CONTROL,
-+		DC_VCE_AUDIO_STREAM_SELECT);
-+
-+	dal_write_reg(hw_ctx->ctx,
-+			addr, value);*/
-+}
-+
-+static void enable_afmt_clock(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	bool enable_flag)
-+{
-+	uint32_t engine_offs = engine_offset[engine_id];
-+	uint32_t value;
-+	uint32_t count = 0;
-+	uint32_t enable = enable_flag ? 1:0;
-+
-+	/* Enable Audio packets*/
-+	value = dm_read_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs);
-+
-+	/*enable AFMT clock*/
-+	set_reg_field_value(value, enable,
-+		AFMT_CNTL, AFMT_AUDIO_CLOCK_EN);
-+	dm_write_reg(hw_ctx->ctx, mmAFMT_CNTL + engine_offs, value);
-+
-+	/*wait for AFMT clock to turn on,
-+	 * the expectation is that this
-+	 * should complete in 1-2 reads)
-+	 */
-+	do {
-+		/* Wait for 1us between subsequent register reads.*/
-+		udelay(1);
-+		value = dm_read_reg(hw_ctx->ctx,
-+				mmAFMT_CNTL + engine_offs);
-+	} while (get_reg_field_value(value,
-+				AFMT_CNTL, AFMT_AUDIO_CLOCK_ON) !=
-+						enable && count++ < 10);
-+}
-+
-+/* enable Azalia audio */
-+static void enable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	uint32_t value;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	if (get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED) != 1)
-+		set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		value);
-+}
-+
-+/* disable Azalia audio */
-+static void disable_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	uint32_t value;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	set_reg_field_value(value, 0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		AUDIO_ENABLED);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		value);
-+}
-+
-+/* enable DP audio */
-+static void enable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+	uint32_t value;
-+
-+	/* Enable Audio packets */
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_ASP_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+
-+	/* Program the ATP and AIP next */
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_ATP_ENABLE);
-+
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_AIP_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+
-+	/* Program STREAM_ENABLE after all the other enables. */
-+	set_reg_field_value(value, 1,
-+		DP_SEC_CNTL,
-+		DP_SEC_STREAM_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* disable DP audio */
-+static void disable_dp_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmDP_SEC_CNTL + engine_offset[engine_id];
-+
-+	uint32_t value;
-+
-+	/* Disable Audio packets */
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ASP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ATP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_AIP_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_ACM_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+		DP_SEC_CNTL,
-+		DP_SEC_STREAM_ENABLE);
-+
-+	/* This register shared with encoder info frame. Therefore we need to
-+	keep master enabled if at least on of the fields is not 0 */
-+	if (value != 0)
-+		set_reg_field_value(value, 1,
-+			DP_SEC_CNTL,
-+			DP_SEC_STREAM_ENABLE);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+static void configure_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_info *audio_info)
-+{
-+	uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
-+	uint32_t value;
-+	uint32_t field = 0;
-+	enum audio_format_code audio_format_code;
-+	uint32_t format_index;
-+	uint32_t index;
-+	bool is_ac3_supported = false;
-+	bool is_audio_format_supported = false;
-+	union audio_sample_rates sample_rate;
-+	uint32_t strlen = 0;
-+
-+	/* Speaker Allocation */
-+	/*
-+	uint32_t value;
-+	uint32_t field = 0;*/
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
-+
-+	set_reg_field_value(value,
-+		speakers,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		SPEAKER_ALLOCATION);
-+
-+	/* LFE_PLAYBACK_LEVEL = LFEPBL
-+	 * LFEPBL = 0 : Unknown or refer to other information
-+	 * LFEPBL = 1 : 0dB playback
-+	 * LFEPBL = 2 : +10dB playback
-+	 * LFE_BL = 3 : Reserved
-+	 */
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		LFE_PLAYBACK_LEVEL);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		HDMI_CONNECTION);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		DP_CONNECTION);
-+
-+	field = get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+	field &= ~0x1;
-+
-+	set_reg_field_value(value,
-+		field,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+
-+	/* set audio for output signal */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		break;
-+	case SIGNAL_TYPE_WIRELESS: {
-+		/*LSB used for "is wireless" flag */
-+		field = 0;
-+		field = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+		field |= 0x1;
-+		set_reg_field_value(value,
-+			field,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		}
-+		break;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			DP_CONNECTION);
-+
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		value);
-+
-+	/* Wireless Display identification */
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION);
-+
-+	set_reg_field_value(value,
-+		signal == SIGNAL_TYPE_WIRELESS ? 1 : 0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION,
-+		WIRELESS_DISPLAY_IDENTIFICATION);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION,
-+		value);
-+
-+	/*  Audio Descriptors   */
-+	/* pass through all formats */
-+	for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
-+			format_index++) {
-+		audio_format_code =
-+			(AUDIO_FORMAT_CODE_FIRST + format_index);
-+
-+		/* those are unsupported, skip programming */
-+		if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
-+			audio_format_code == AUDIO_FORMAT_CODE_DST)
-+			continue;
-+
-+		value = 0;
-+
-+		/* check if supported */
-+		is_audio_format_supported =
-+			dal_audio_hw_ctx_is_audio_format_supported(
-+				hw_ctx,
-+				audio_info,
-+				audio_format_code, &index);
-+
-+		if (is_audio_format_supported) {
-+			const struct audio_mode *audio_mode =
-+					&audio_info->modes[index];
-+			union audio_sample_rates sample_rates =
-+					audio_mode->sample_rates;
-+			uint8_t byte2 = audio_mode->max_bit_rate;
-+
-+			/* adjust specific properties */
-+			switch (audio_format_code) {
-+			case AUDIO_FORMAT_CODE_LINEARPCM: {
-+				dal_hw_ctx_audio_check_audio_bandwidth(
-+					hw_ctx,
-+					crtc_info,
-+					audio_mode->channel_count,
-+					signal,
-+					&sample_rates);
-+
-+				byte2 = audio_mode->sample_size;
-+
-+				set_reg_field_value(value,
-+				sample_rates.all,
-+		AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+				SUPPORTED_FREQUENCIES_STEREO);
-+
-+				}
-+				break;
-+			case AUDIO_FORMAT_CODE_AC3:
-+				is_ac3_supported = true;
-+				break;
-+			case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
-+			case AUDIO_FORMAT_CODE_DTS_HD:
-+			case AUDIO_FORMAT_CODE_MAT_MLP:
-+			case AUDIO_FORMAT_CODE_DST:
-+			case AUDIO_FORMAT_CODE_WMAPRO:
-+				byte2 = audio_mode->vendor_specific;
-+				break;
-+			default:
-+				break;
-+			}
-+
-+			/* fill audio format data */
-+			set_reg_field_value(value,
-+			audio_mode->channel_count - 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			MAX_CHANNELS);
-+
-+			set_reg_field_value(value,
-+			sample_rates.all,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			SUPPORTED_FREQUENCIES);
-+
-+			set_reg_field_value(value,
-+			byte2,
-+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+			DESCRIPTOR_BYTE_2);
-+
-+		} /* if */
-+
-+		write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +
-+		format_index,
-+		value);
-+	} /* for */
-+
-+	if (is_ac3_supported)
-+		dm_write_reg(hw_ctx->ctx,
-+		mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
-+		0x05);
-+
-+	/* check for 192khz/8-Ch support for HBR requirements */
-+	sample_rate.all = 0;
-+	sample_rate.rate.RATE_192 = 1;
-+	dal_hw_ctx_audio_check_audio_bandwidth(
-+		hw_ctx,
-+		crtc_info,
-+		8,
-+		signal,
-+		&sample_rate);
-+
-+	set_high_bit_rate_capable(hw_ctx, sample_rate.rate.RATE_192);
-+
-+	/* Audio and Video Lipsync */
-+	set_video_latency(hw_ctx, audio_info->video_latency);
-+	set_audio_latency(hw_ctx, audio_info->audio_latency);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->manufacture_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		MANUFACTURER_ID);
-+
-+	set_reg_field_value(value, audio_info->product_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		PRODUCT_ID);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		value);
-+
-+	value = 0;
-+
-+	/*get display name string length */
-+	while (audio_info->display_name[strlen++] != '\0') {
-+		if (strlen >=
-+		MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
-+			break;
-+		}
-+	set_reg_field_value(value, strlen,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		SINK_DESCRIPTION_LEN);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		value);
-+
-+	/*
-+	*write the port ID:
-+	*PORT_ID0 = display index
-+	*PORT_ID1 = 16bit BDF
-+	*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
-+	*/
-+
-+	value = 0;
-+
-+	set_reg_field_value(value, audio_info->port_id[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		PORT_ID0);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->port_id[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		PORT_ID1);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		value);
-+
-+	/*write the 18 char monitor string */
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION0);
-+
-+	set_reg_field_value(value, audio_info->display_name[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION1);
-+
-+	set_reg_field_value(value, audio_info->display_name[2],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION2);
-+
-+	set_reg_field_value(value, audio_info->display_name[3],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION3);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[4],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION4);
-+
-+	set_reg_field_value(value, audio_info->display_name[5],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION5);
-+
-+	set_reg_field_value(value, audio_info->display_name[6],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION6);
-+
-+	set_reg_field_value(value, audio_info->display_name[7],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION7);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[8],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION8);
-+
-+	set_reg_field_value(value, audio_info->display_name[9],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION9);
-+
-+	set_reg_field_value(value, audio_info->display_name[10],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION10);
-+
-+	set_reg_field_value(value, audio_info->display_name[11],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION11);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[12],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION12);
-+
-+	set_reg_field_value(value, audio_info->display_name[13],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION13);
-+
-+	set_reg_field_value(value, audio_info->display_name[14],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION14);
-+
-+	set_reg_field_value(value, audio_info->display_name[15],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION15);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[16],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION16);
-+
-+	set_reg_field_value(value, audio_info->display_name[17],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION17);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		value);
-+
-+}
-+
-+/* setup Azalia HW block */
-+static void setup_azalia(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info,
-+	const struct audio_info *audio_info)
-+{
-+	uint32_t speakers = 0;
-+	uint32_t channels = 0;
-+
-+	if (audio_info == NULL)
-+		/* This should not happen.it does so we don't get BSOD*/
-+		return;
-+
-+	speakers = audio_info->flags.info.ALLSPEAKERS;
-+	channels = dal_audio_hw_ctx_speakers_to_channels(
-+		hw_ctx,
-+		audio_info->flags.speaker_flags).all;
-+
-+	/* setup the audio stream source select (audio -> dig mapping) */
-+	{
-+		const uint32_t addr =
-+			mmAFMT_AUDIO_SRC_CONTROL + engine_offset[engine_id];
-+
-+		uint32_t value = 0;
-+		/*convert one-based index to zero-based */
-+		set_reg_field_value(value,
-+			FROM_BASE(hw_ctx)->azalia_stream_id - 1,
-+			AFMT_AUDIO_SRC_CONTROL,
-+			AFMT_AUDIO_SRC_SELECT);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/* Channel allocation */
-+	{
-+		const uint32_t addr =
-+			mmAFMT_AUDIO_PACKET_CONTROL2 + engine_offset[engine_id];
-+		uint32_t value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value,
-+			channels,
-+			AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_CHANNEL_ENABLE);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	configure_azalia(hw_ctx, signal, crtc_info, audio_info);
-+}
-+
-+/* unmute audio */
-+static void unmute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+		engine_offset[engine_id];
-+
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 1,
-+		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* mute audio */
-+static void mute_azalia_audio(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id)
-+{
-+	const uint32_t addr = mmAFMT_AUDIO_PACKET_CONTROL +
-+		engine_offset[engine_id];
-+
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+	set_reg_field_value(value, 0,
-+		AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND);
-+
-+	dm_write_reg(hw_ctx->ctx, addr, value);
-+}
-+
-+/* enable channel splitting mapping */
-+static void setup_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	enum signal_type signal,
-+	const struct audio_channel_associate_info *audio_mapping,
-+	bool enable)
-+{
-+	uint32_t value = 0;
-+
-+	if ((audio_mapping == NULL || audio_mapping->u32all == 0) && enable)
-+		return;
-+
-+	value = audio_mapping->u32all;
-+
-+	if (enable == false)
-+		/*0xFFFFFFFF;*/
-+		value = MULTI_CHANNEL_SPLIT_NO_ASSO_INFO;
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+		value);
-+}
-+
-+/* get current channel spliting */
-+static bool get_channel_splitting_mapping(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum engine_id engine_id,
-+	struct audio_channel_associate_info *audio_mapping)
-+{
-+	uint32_t value = 0;
-+
-+	if (audio_mapping == NULL)
-+		return false;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO);
-+
-+	/*0xFFFFFFFF*/
-+	if (get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO,
-+			ASSOCIATION_INFO) !=
-+			MULTI_CHANNEL_SPLIT_NO_ASSO_INFO) {
-+		uint32_t multi_channel01_enable = 0;
-+		uint32_t multi_channel23_enable = 0;
-+		uint32_t multi_channel45_enable = 0;
-+		uint32_t multi_channel67_enable = 0;
-+		/* get the one we set.*/
-+		audio_mapping->u32all = value;
-+
-+		/* check each enable status*/
-+		value = read_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE);
-+
-+		multi_channel01_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL01_ENABLE);
-+
-+		multi_channel23_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL23_ENABLE);
-+
-+		multi_channel45_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL45_ENABLE);
-+
-+		multi_channel67_enable = get_reg_field_value(value,
-+		AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE,
-+		MULTICHANNEL67_ENABLE);
-+
-+		if (multi_channel01_enable == 0 &&
-+			multi_channel23_enable == 0 &&
-+			multi_channel45_enable == 0 &&
-+			multi_channel67_enable == 0)
-+			dal_logger_write(hw_ctx->ctx->logger,
-+				LOG_MAJOR_HW_TRACE,
-+				LOG_MINOR_COMPONENT_AUDIO,
-+				"Audio driver did not enable multi-channel\n");
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+/* set the payload value for the unsolicited response */
-+static void set_unsolicited_response_payload(
-+	const struct hw_ctx_audio *hw_ctx,
-+	enum audio_payload payload)
-+{
-+	/* set the payload value for the unsolicited response
-+	 Jack presence is not required to be enabled */
-+	uint32_t value = 0;
-+
-+	value = read_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE);
-+
-+	set_reg_field_value(value, payload,
-+		AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		UNSOLICITED_RESPONSE_PAYLOAD);
-+
-+	set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		UNSOLICITED_RESPONSE_FORCE);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE,
-+		value);
-+}
-+
-+/* initialize HW state */
-+static void hw_initialize(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t stream_id = FROM_BASE(hw_ctx)->azalia_stream_id;
-+	uint32_t addr;
-+
-+	/* we only need to program the following registers once, so we only do
-+	it for the first audio stream.*/
-+	if (stream_id != FIRST_AUDIO_STREAM_ID)
-+		return;
-+
-+	/* Suport R5 - 32khz
-+	 * Suport R6 - 44.1khz
-+	 * Suport R7 - 48khz
-+	 */
-+	addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
-+	{
-+		uint32_t value;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 0x70,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
-+		AUDIO_RATE_CAPABILITIES);
-+
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+
-+	/*Keep alive bit to verify HW block in BU. */
-+	addr = mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
-+	{
-+		uint32_t value;
-+
-+		value = dm_read_reg(hw_ctx->ctx, addr);
-+
-+		set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+		CLKSTOP);
-+
-+		set_reg_field_value(value, 1,
-+		AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+		EPSS);
-+		dm_write_reg(hw_ctx->ctx, addr, value);
-+	}
-+}
-+
-+/* Assign GTC group and enable GTC value embedding */
-+static void enable_gtc_embedding_with_group(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t group_num,
-+	uint32_t audio_latency)
-+{
-+	/*need to replace the static number with variable */
-+	if (group_num <= 6) {
-+		uint32_t value = read_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+		set_reg_field_value(
-+			value,
-+			group_num,
-+			AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+		write_indirect_azalia_reg(
-+			hw_ctx,
-+			ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+			value);
-+
-+		/*update audio latency to LIPSYNC*/
-+		set_audio_latency(hw_ctx, audio_latency);
-+	} else {
-+		dal_logger_write(
-+			hw_ctx->ctx->logger,
-+			LOG_MAJOR_HW_TRACE,
-+			LOG_MINOR_COMPONENT_AUDIO,
-+			"GTC group number %d is too big",
-+			group_num);
-+	}
-+}
-+
-+ /* Disable GTC value embedding */
-+static void disable_gtc_embedding(
-+	const struct hw_ctx_audio *hw_ctx)
-+{
-+	uint32_t value = 0;
-+
-+	value = read_indirect_azalia_reg(
-+	hw_ctx,
-+	ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING);
-+
-+	set_reg_field_value(value, 0,
-+	AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+	PRESENTATION_TIME_EMBEDDING_ENABLE);
-+
-+	set_reg_field_value(value, 0,
-+	AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+	PRESENTATION_TIME_EMBEDDING_GROUP);
-+
-+	write_indirect_azalia_reg(
-+		hw_ctx,
-+		ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING,
-+		value);
-+}
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static bool get_azalia_clock_info_hdmi(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	if (azalia_clock_info == NULL)
-+		return false;
-+
-+	/* audio_dto_phase= 24 * 10,000;
-+	 *   24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase =
-+			24 * 10000;
-+
-+	/* audio_dto_module = PCLKFrequency * 10,000;
-+	 *  [khz] -> [100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+			actual_pixel_clock_in_khz * 10;
-+
-+	return true;
-+}
-+
-+/* search pixel clock value for Azalia DP Audio */
-+static bool get_azalia_clock_info_dp(
-+	const struct hw_ctx_audio *hw_ctx,
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	if (pll_info == NULL || azalia_clock_info == NULL)
-+		return false;
-+
-+	/* Reported dpDtoSourceClockInkhz value for
-+	 * DCE8 already adjusted for SS, do not need any
-+	 * adjustment here anymore
-+	 */
-+
-+	/*audio_dto_phase = 24 * 10,000;
-+	 * 24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase = 24 * 10000;
-+
-+	/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
-+	 *  [khz] ->[100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+		pll_info->dp_dto_source_clock_in_khz * 10;
-+
-+	return true;
-+}
-+
-+static const struct hw_ctx_audio_funcs funcs = {
-+	.destroy = destroy,
-+	.setup_audio_wall_dto =
-+		setup_audio_wall_dto,
-+	.setup_hdmi_audio =
-+		setup_hdmi_audio,
-+	.setup_dp_audio = setup_dp_audio,
-+	.setup_vce_audio = setup_vce_audio,
-+	.enable_azalia_audio =
-+		enable_azalia_audio,
-+	.disable_azalia_audio =
-+		disable_azalia_audio,
-+	.enable_dp_audio =
-+		enable_dp_audio,
-+	.disable_dp_audio =
-+		disable_dp_audio,
-+	.setup_azalia =
-+		setup_azalia,
-+	.disable_az_clock_gating = NULL,
-+	.unmute_azalia_audio =
-+		unmute_azalia_audio,
-+	.mute_azalia_audio =
-+		mute_azalia_audio,
-+	.setup_channel_splitting_mapping =
-+		setup_channel_splitting_mapping,
-+	.get_channel_splitting_mapping =
-+		get_channel_splitting_mapping,
-+	.set_unsolicited_response_payload =
-+		set_unsolicited_response_payload,
-+	.hw_initialize =
-+		hw_initialize,
-+	.enable_gtc_embedding_with_group =
-+		enable_gtc_embedding_with_group,
-+	.disable_gtc_embedding =
-+		disable_gtc_embedding,
-+	.get_azalia_clock_info_hdmi =
-+		get_azalia_clock_info_hdmi,
-+	.get_azalia_clock_info_dp =
-+		get_azalia_clock_info_dp,
-+	.enable_afmt_clock = enable_afmt_clock
-+};
-+
-+static bool construct(
-+	struct hw_ctx_audio_dce112 *hw_ctx,
-+	uint8_t azalia_stream_id,
-+	struct dc_context *ctx)
-+{
-+	struct hw_ctx_audio *base = &hw_ctx->base;
-+
-+	if (!dal_audio_construct_hw_ctx_audio(base))
-+		return false;
-+
-+	base->funcs = &funcs;
-+
-+	/* save audio endpoint or dig front for current dce112 audio object */
-+	hw_ctx->azalia_stream_id = azalia_stream_id;
-+	hw_ctx->base.ctx = ctx;
-+
-+	/* azalia audio endpoints register offsets. azalia is associated with
-+	DIG front. save AUDIO register offset */
-+	switch (azalia_stream_id) {
-+	case 1: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 2: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 3: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	case 4: {
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_index =
-+			mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+			hw_ctx->az_mm_reg_offsets.
-+			azf0endpointx_azalia_f0_codec_endpoint_data =
-+			mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA;
-+		}
-+		break;
-+	default:
-+		dal_logger_write(
-+			hw_ctx->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_AUDIO,
-+			"Invalid Azalia stream ID!");
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+/* audio_dce112 is derived from audio directly, not via dce80  */
-+struct hw_ctx_audio *dal_hw_ctx_audio_dce112_create(
-+	struct dc_context *ctx,
-+	uint32_t azalia_stream_id)
-+{
-+	/* allocate memory for struc hw_ctx_audio_dce112 */
-+	struct hw_ctx_audio_dce112 *hw_ctx_dce112 =
-+			dm_alloc(sizeof(struct hw_ctx_audio_dce112));
-+
-+	if (!hw_ctx_dce112) {
-+		ASSERT_CRITICAL(hw_ctx_dce112);
-+		return NULL;
-+	}
-+
-+	/*return pointer to hw_ctx_audio back to caller  -- audio object */
-+	if (construct(
-+			hw_ctx_dce112, azalia_stream_id, ctx))
-+		return &hw_ctx_dce112->base;
-+
-+	dal_logger_write(
-+		ctx->logger,
-+		LOG_MAJOR_ERROR,
-+		LOG_MINOR_COMPONENT_AUDIO,
-+		"Failed to create hw_ctx_audio for DCE11\n");
-+
-+	dm_free(hw_ctx_dce112);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h b/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
-new file mode 100644
-index 0000000..af61aad
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_CTX_AUDIO_DCE112_H__
-+#define __DAL_HW_CTX_AUDIO_DCE112_H__
-+
-+#include "audio/hw_ctx_audio.h"
-+
-+struct hw_ctx_audio_dce112 {
-+	struct hw_ctx_audio base;
-+
-+	/* azalia stream id 1 based indexing, corresponding to audio GO enumId*/
-+	uint32_t azalia_stream_id;
-+
-+	/* azalia stream endpoint register offsets */
-+	struct azalia_reg_offsets az_mm_reg_offsets;
-+
-+	/* audio encoder block MM register offset -- associate with DIG FRONT */
-+};
-+
-+struct hw_ctx_audio *dal_hw_ctx_audio_dce112_create(
-+	struct dc_context *ctx,
-+	uint32_t azalia_stream_id);
-+
-+#endif  /* __DAL_HW_CTX_AUDIO_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-index e5c8876..9c90230 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
-@@ -37,3 +37,12 @@ endif
- 
- AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
- endif
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_2
-+ccflags-y += -DLATEST_ATOM_BIOS_SUPPORT
-+ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce112/bios_parser_helper_dce112.o
-+endif
-+
-+AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index 4e2bc90..4204798 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -55,6 +55,12 @@ bool dal_bios_parser_init_bios_helper(
- 		return true;
- 
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		bp->bios_helper = dal_bios_parser_helper_dce112_get_table();
-+		return true;
-+
-+#endif
- 	default:
- 		BREAK_TO_DEBUGGER();
- 		return false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index c58b9bb..b93b046 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -34,6 +34,10 @@
- #include "dce110/bios_parser_helper_dce110.h"
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "dce112/bios_parser_helper_dce112.h"
-+#endif
-+
- struct bios_parser;
- 
- struct vbios_helper_data {
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-index ccd1c7e..22524b3 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
-@@ -104,6 +104,13 @@ static enum bp_result encoder_control_digx_v3(
- static enum bp_result encoder_control_digx_v4(
- 	struct bios_parser *bp,
- 	struct bp_encoder_control *cntl);
-+
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+static enum bp_result encoder_control_digx_v5(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+#endif
-+
- static void init_encoder_control_dig_v1(struct bios_parser *bp);
- 
- static void init_dig_encoder_control(struct bios_parser *bp)
-@@ -112,12 +119,19 @@ static void init_dig_encoder_control(struct bios_parser *bp)
- 		BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl);
- 
- 	switch (version) {
-+	case 2:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3;
-+		break;
- 	case 4:
- 		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4;
- 		break;
--	case 2:
--		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3;
-+
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+	case 5:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v5;
- 		break;
-+#endif
-+
- 	default:
- 		init_encoder_control_dig_v1(bp);
- 		break;
-@@ -302,6 +316,66 @@ static enum bp_result encoder_control_digx_v4(
- 	return result;
- }
- 
-+#ifdef LATEST_ATOM_BIOS_SUPPORT
-+static enum bp_result encoder_control_digx_v5(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENCODER_STREAM_SETUP_PARAMETERS_V5 params = {0};
-+
-+	params.ucDigId = (uint8_t)(cntl->engine_id);
-+	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+
-+	params.ulPixelClock = cntl->pixel_clock / 10;
-+	params.ucDigMode =
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio));
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+	switch (cntl->color_depth) {
-+	case COLOR_DEPTH_888:
-+		params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.ulPixelClock =
-+				(params.ulPixelClock * 30) / 24;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.ulPixelClock =
-+				(params.ulPixelClock * 36) / 24;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.ulPixelClock =
-+				(params.ulPixelClock * 48) / 24;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+#endif
-+
- /*******************************************************************************
-  ********************************************************************************
-  **
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-index 85a5924..a27db8c 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c
-@@ -55,6 +55,12 @@ bool dal_bios_parser_init_cmd_tbl_helper(
- 		return true;
- #endif
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		*h = dal_cmd_tbl_helper_dce112_get_table();
-+		return true;
-+#endif
-+
- 	default:
- 		/* Unsupported DCE */
- 		BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-index a462917..e6a0d19 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h
-@@ -32,6 +32,9 @@
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- #include "dce110/command_table_helper_dce110.h"
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "dce112/command_table_helper_dce112.h"
-+#endif
- 
- struct command_table_helper {
- 	bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
-new file mode 100644
-index 0000000..1b0f816
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
-@@ -0,0 +1,480 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+#include "include/logger_interface.h"
-+
-+#include "../bios_parser_helper.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "bif/bif_5_1_d.h"
-+
-+/**
-+ * set_scratch_acc_mode_change
-+ *
-+ * @brief
-+ *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-+ *  VGA/non-Accelerated mode is set
-+ *
-+ * @param
-+ *  struct dc_context *ctx - [in] DAL context
-+ */
-+static void set_scratch_acc_mode_change(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value |= ATOM_S6_ACC_MODE;
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+/*
-+ * set_scratch_active_and_requested
-+ *
-+ * @brief
-+ * Set VBIOS scratch pad registers about active and requested displays
-+ *
-+ * @param
-+ * struct dc_context *ctx - [in] DAL context for register accessing
-+ * struct vbios_helper_data *d - [in] values to write
-+ */
-+static void set_scratch_active_and_requested(
-+	struct dc_context *ctx,
-+	struct vbios_helper_data *d)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_3;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
-+	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_6;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S6_ACC_REQ_MASK;
-+	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
-+	addr = mmBIOS_SCRATCH_5;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
-+	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	d->active = 0;
-+	d->requested = 0;
-+}
-+
-+/**
-+ * get LCD Scale Mode from VBIOS scratch register
-+ */
-+static enum lcd_scale get_scratch_lcd_scale(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	if (value & ATOM_S6_REQ_LCD_EXPANSION_FULL)
-+		return LCD_SCALE_FULLPANEL;
-+	else if (value & ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO)
-+		return LCD_SCALE_ASPECTRATIO;
-+	else
-+		return LCD_SCALE_NONE;
-+}
-+
-+/**
-+ * prepare_scratch_active_and_requested
-+ *
-+ * @brief
-+ *  prepare and update VBIOS scratch pad registers about active and requested
-+ *  displays
-+ *
-+ * @param
-+ * data - helper's shared data
-+ * enum controller_ild - controller Id
-+ * enum signal_type - signal type used on display
-+ * const struct connector_device_tag_info* - pointer to display type and enum id
-+ */
-+static void prepare_scratch_active_and_requested(
-+	struct dc_context *ctx,
-+	struct vbios_helper_data *data,
-+	enum controller_id id,
-+	enum signal_type s,
-+	const struct connector_device_tag_info *dev_tag)
-+{
-+	switch (s) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_DFP)
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP1;
-+				data->active |= ATOM_S3_DFP1_ACTIVE;
-+				break;
-+			case 2:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP2;
-+				data->active |= ATOM_S3_DFP2_ACTIVE;
-+				break;
-+			case 3:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP3;
-+				data->active |= ATOM_S3_DFP3_ACTIVE;
-+				break;
-+			case 4:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP4;
-+				data->active |= ATOM_S3_DFP4_ACTIVE;
-+				break;
-+			case 5:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP5;
-+				data->active |= ATOM_S3_DFP5_ACTIVE;
-+				break;
-+			case 6:
-+				data->requested |= ATOM_S6_ACC_REQ_DFP6;
-+				data->active |= ATOM_S3_DFP6_ACTIVE;
-+				break;
-+			default:
-+				break;
-+			}
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_EDP:
-+		data->requested |= ATOM_S6_ACC_REQ_LCD1;
-+		data->active |= ATOM_S3_LCD1_ACTIVE;
-+		break;
-+	case SIGNAL_TYPE_RGB:
-+		if (dev_tag->dev_id.device_type == DEVICE_TYPE_CRT)
-+			switch (dev_tag->dev_id.enum_id) {
-+			case 1:
-+				data->requested |= ATOM_S6_ACC_REQ_CRT1;
-+				data->active |= ATOM_S3_CRT1_ACTIVE;
-+				break;
-+			case 2:
-+				dal_logger_write(ctx->logger,
-+					LOG_MAJOR_BIOS,
-+					LOG_MINOR_COMPONENT_BIOS,
-+					"%s: DAL does not support DAC2!\n",
-+					__func__);
-+				break;
-+			default:
-+				break;
-+			}
-+		break;
-+	default:
-+		dal_logger_write(ctx->logger,
-+				LOG_MAJOR_BIOS,
-+				LOG_MINOR_COMPONENT_BIOS,
-+				"%s: No such signal!\n",
-+				__func__);
-+		break;
-+	}
-+}
-+
-+/*
-+ * is_accelerated_mode
-+ *
-+ * @brief
-+ *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-+ *  VGA/non-Accelerated mode is set
-+ *
-+ * @param
-+ * struct dc_context *ctx
-+ *
-+ * @return
-+ * true if in acceleration mode, false otherwise.
-+ */
-+static bool is_accelerated_mode(
-+	struct dc_context *ctx)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	return (value & ATOM_S6_ACC_MODE) ? true : false;
-+}
-+
-+#define BIOS_SCRATCH0_DAC_B_SHIFT 8
-+
-+/**
-+ * detect_sink
-+ *
-+ * @brief
-+ *  read VBIOS scratch register to determine whether display for the specified
-+ *  signal is present and return the actual sink signal type
-+ *  For analog signals VBIOS load detection has to be called prior reading the
-+ *  register
-+ *
-+ * @param
-+ *  encoder - encoder id (to specify DAC)
-+ *  connector - connector id (to check CV on DIN)
-+ *  signal - signal (as display type) to check
-+ *
-+ * @return
-+ *  signal_type - actual (on the sink) signal type detected
-+ */
-+static enum signal_type detect_sink(
-+	struct dc_context *ctx,
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id connector,
-+	enum signal_type signal)
-+{
-+	uint32_t bios_scratch0;
-+	uint32_t encoder_id = encoder.id;
-+	/* after DCE 10.x does not support DAC2, so assert and return SIGNAL_TYPE_NONE */
-+	if (encoder_id == ENCODER_ID_INTERNAL_DAC2
-+		|| encoder_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2) {
-+		ASSERT(false);
-+		return SIGNAL_TYPE_NONE;
-+	}
-+
-+	bios_scratch0 = dm_read_reg(ctx,
-+		mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF);
-+
-+	/* In further processing we use DACB masks. If we want detect load on
-+	 * DACA, we need to shift the register so DACA bits will be in place of
-+	 * DACB bits
-+	 */
-+	if (encoder_id == ENCODER_ID_INTERNAL_DAC1
-+		|| encoder_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1
-+		|| encoder_id == ENCODER_ID_EXTERNAL_NUTMEG
-+		|| encoder_id == ENCODER_ID_EXTERNAL_TRAVIS) {
-+		bios_scratch0 <<= BIOS_SCRATCH0_DAC_B_SHIFT;
-+	}
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_RGB: {
-+		if (bios_scratch0 & ATOM_S0_CRT2_MASK)
-+			return SIGNAL_TYPE_RGB;
-+		break;
-+	}
-+	case SIGNAL_TYPE_LVDS: {
-+		if (bios_scratch0 & ATOM_S0_LCD1)
-+			return SIGNAL_TYPE_LVDS;
-+		break;
-+	}
-+	case SIGNAL_TYPE_EDP: {
-+		if (bios_scratch0 & ATOM_S0_LCD1)
-+			return SIGNAL_TYPE_EDP;
-+		break;
-+	}
-+	default:
-+		break;
-+	}
-+
-+	return SIGNAL_TYPE_NONE;
-+}
-+
-+/**
-+ * set_scratch_connected
-+ *
-+ * @brief
-+ *    update BIOS_SCRATCH_0 register about connected displays
-+ *
-+ * @param
-+ * bool - update scratch register or just prepare info to be updated
-+ * bool - connection state
-+ * const struct connector_device_tag_info * - pointer to device type and enum ID
-+ */
-+static void set_scratch_connected(
-+	struct dc_context *ctx,
-+	struct graphics_object_id id,
-+	bool connected,
-+	const struct connector_device_tag_info *device_tag)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t update = 0;
-+
-+	switch (device_tag->dev_id.device_type) {
-+	case DEVICE_TYPE_LCD:
-+		/* For LCD VBIOS will update LCD Panel connected bit always and
-+		 * Lid state bit based on SBIOS info do not do anything here
-+		 * for LCD
-+		 */
-+		break;
-+	case DEVICE_TYPE_CRT:
-+		/* CRT is not supported in DCE11 */
-+		break;
-+	case DEVICE_TYPE_DFP:
-+		switch (device_tag->dev_id.enum_id) {
-+		case 1:
-+			update |= ATOM_S0_DFP1;
-+			break;
-+		case 2:
-+			update |= ATOM_S0_DFP2;
-+			break;
-+		case 3:
-+			update |= ATOM_S0_DFP3;
-+			break;
-+		case 4:
-+			update |= ATOM_S0_DFP4;
-+			break;
-+		case 5:
-+			update |= ATOM_S0_DFP5;
-+			break;
-+		case 6:
-+			update |= ATOM_S0_DFP6;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CV:
-+		/* DCE 8.0 does not support CV, so don't do anything */
-+		break;
-+
-+	case DEVICE_TYPE_TV:
-+		/* For TV VBIOS will update S-Video or
-+		 * Composite scratch bits on DAL_LoadDetect
-+		 * when called by driver, do not do anything
-+		 * here for TV
-+		 */
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+	/* update scratch register */
-+	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	if (connected)
-+		value |= update;
-+	else
-+		value &= ~update;
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void set_scratch_critical_state(
-+	struct dc_context *ctx,
-+	bool state)
-+{
-+	uint32_t addr = mmBIOS_SCRATCH_6;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	if (state)
-+		value |= ATOM_S6_CRITICAL_STATE;
-+	else
-+		value &= ~ATOM_S6_CRITICAL_STATE;
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void set_scratch_lcd_scale(
-+	struct dc_context *ctx,
-+	enum lcd_scale lcd_scale_request)
-+{
-+	DAL_LOGGER_NOT_IMPL(
-+		LOG_MINOR_COMPONENT_BIOS,
-+		"Bios Parser:%s\n",
-+		__func__);
-+}
-+
-+static bool is_lid_open(struct dc_context *ctx)
-+{
-+	uint32_t bios_scratch6;
-+
-+	bios_scratch6 =
-+		dm_read_reg(
-+			ctx,
-+			mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF);
-+
-+	/* lid is open if the bit is not set */
-+	if (!(bios_scratch6 & ATOM_S6_LID_STATE))
-+		return true;
-+
-+	return false;
-+}
-+
-+/* function table */
-+static const struct bios_parser_helper bios_parser_helper_funcs = {
-+	.detect_sink = detect_sink,
-+	.fmt_bit_depth_control = NULL,
-+	.fmt_control = NULL,
-+	.get_bios_event_info = NULL,
-+	.get_embedded_display_controller_id = NULL,
-+	.get_embedded_display_refresh_rate = NULL,
-+	.get_requested_backlight_level = NULL,
-+	.get_scratch_lcd_scale = get_scratch_lcd_scale,
-+	.is_accelerated_mode = is_accelerated_mode,
-+	.is_active_display = NULL,
-+	.is_display_config_changed = NULL,
-+	.is_lid_open = is_lid_open,
-+	.is_lid_status_changed = NULL,
-+	.prepare_scratch_active_and_requested =
-+			prepare_scratch_active_and_requested,
-+	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
-+	.set_scratch_active_and_requested = set_scratch_active_and_requested,
-+	.set_scratch_connected = set_scratch_connected,
-+	.set_scratch_critical_state = set_scratch_critical_state,
-+	.set_scratch_lcd_scale = set_scratch_lcd_scale,
-+	.take_backlight_control = NULL,
-+	.update_requested_backlight_level = NULL,
-+};
-+
-+/*
-+ * dal_bios_parser_dce112_init_bios_helper
-+ *
-+ * @brief
-+ * Initialize BIOS helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+
-+const struct bios_parser_helper *dal_bios_parser_helper_dce112_get_table()
-+{
-+	return &bios_parser_helper_funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
-new file mode 100644
-index 0000000..044327e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_HELPER_DCE112_H__
-+#define __DAL_BIOS_PARSER_HELPER_DCE112_H__
-+
-+struct bios_parser_helper;
-+
-+/* Initialize BIOS helper functions */
-+const struct bios_parser_helper *dal_bios_parser_helper_dce112_get_table(void);
-+
-+#endif /* __DAL_BIOS_PARSER_HELPER_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.c b/drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.c
-new file mode 100644
-index 0000000..32ec228
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.c
-@@ -0,0 +1,417 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "include/adapter_service_types.h"
-+
-+#include "../command_table_helper.h"
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
-+		break;
-+	case ENGINE_ID_UNKNOWN:
-+		/* No DIG_FRONT is associated to DIG_BACKEND */
-+		atom_dig_encoder_sel = 0;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-+		break;
-+	}
-+
-+	return atom_dig_encoder_sel;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_COMBO_PHY_PLL0:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL0;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL1:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL1;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL2:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL2;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL3:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL3;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL4:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL4;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL5:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL5;
-+			break;
-+		case CLOCK_SOURCE_COMBO_DISPLAY_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_GCK_DFS;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			*atom_pll_id = ATOM_DP_DTO;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			*atom_pll_id = ATOM_DP_DTO;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			/* Should not happen */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_STREAM_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+bool dc_clock_type_to_atom(enum bp_dce_clock_type id, uint32_t *atom_clock_type)
-+{
-+	bool retCode = true;
-+
-+	if (atom_clock_type != NULL) {
-+		switch (id) {
-+		case DCECLOCK_TYPE_DISPLAY_CLOCK:
-+			*atom_clock_type = DCE_CLOCK_TYPE_DISPCLK;
-+			break;
-+
-+		case DCECLOCK_TYPE_DPREFCLK:
-+			*atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK;
-+			break;
-+
-+		default:
-+			ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+			break;
-+		}
-+	}
-+
-+	return retCode;
-+}
-+
-+uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
-+{
-+	uint8_t atomColorDepth = 0;
-+
-+	switch (id) {
-+	case TRANSMITTER_COLOR_DEPTH_24:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_30:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_36:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_48:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atomColorDepth;
-+}
-+
-+/* function table */
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+			clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.assign_control_parameter = NULL,
-+	.clock_source_id_to_ref_clk_src = NULL,
-+	.transmitter_bp_to_atom = NULL,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
-+	.encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
-+	.dc_clock_type_to_atom = dc_clock_type_to_atom,
-+	.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
-+};
-+
-+/*
-+ * dal_cmd_tbl_helper_dce110_get_table
-+ *
-+ * @brief
-+ * Initialize command table helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table()
-+{
-+	return &command_table_helper_funcs;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.h b/drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.h
-new file mode 100644
-index 0000000..dc36609
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce112/command_table_helper_dce112.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE112_H__
-+#define __DAL_COMMAND_TABLE_HELPER_DCE112_H__
-+
-+struct command_table_helper;
-+
-+/* Initialize command table helper functions */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table(void);
-+
-+#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index f39499a..8a19139 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3726,6 +3726,212 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
- 		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
- 		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
- 		break;
-+	case BW_CALCS_VERSION_ELLESMERE:
-+		vbios.number_of_dram_channels = 8;
-+		vbios.dram_channel_width_in_bits = 32;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(6000);
-+		vbios.mid_yclk = bw_int_to_fixed(3200);
-+		vbios.low_yclk = bw_int_to_fixed(1000);
-+		vbios.low_sclk = bw_int_to_fixed(300);
-+		vbios.mid_sclk = bw_int_to_fixed(974);
-+		vbios.high_sclk = bw_int_to_fixed(1154);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(1132);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(48);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
-+		vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
-+		vbios.nbp_state_change_latency = bw_int_to_fixed(45);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel =
-+			256;
-+		vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-+
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.de_tiling_buffer = bw_int_to_fixed(0);
-+		dceip.dcfclk_request_generation = 0;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 6;
-+		dceip.number_of_underlay_pipes = 0;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = false;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 4;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(1);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.cursor_memory_interface_buffer_pixels = bw_int_to_fixed(
-+			64);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(11, 10);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(
-+			105,
-+			100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
-+		break;
-+	case BW_CALCS_VERSION_BAFFIN:
-+		vbios.number_of_dram_channels = 4;
-+		vbios.dram_channel_width_in_bits = 32;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(6000);
-+		vbios.mid_yclk = bw_int_to_fixed(3200);
-+		vbios.low_yclk = bw_int_to_fixed(1000);
-+		vbios.low_sclk = bw_int_to_fixed(300);
-+		vbios.mid_sclk = bw_int_to_fixed(974);
-+		vbios.high_sclk = bw_int_to_fixed(1154);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(1132);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(48);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
-+		vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
-+		vbios.nbp_state_change_latency = bw_int_to_fixed(45);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel =
-+			256;
-+		vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-+
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.de_tiling_buffer = bw_int_to_fixed(0);
-+		dceip.dcfclk_request_generation = 0;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 5;
-+		dceip.number_of_underlay_pipes = 0;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = false;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 4;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(1);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.cursor_memory_interface_buffer_pixels = bw_int_to_fixed(
-+			64);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(11, 10);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(
-+			105,
-+			100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
-+		break;
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-index 61bb67a..f9dd0d8 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c
-@@ -34,6 +34,9 @@
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/dce110_hw_sequencer.h"
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "dce112/dce112_hw_sequencer.h"
-+#endif
- 
- bool dc_construct_hw_sequencer(
- 				struct adapter_service *adapter_serv,
-@@ -55,6 +58,10 @@ bool dc_construct_hw_sequencer(
- 	case DCE_VERSION_11_0:
- 		return dce110_hw_sequencer_construct(dc);
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		return dce112_hw_sequencer_construct(dc);
-+#endif
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 5f3b702..087670d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -41,11 +41,13 @@
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- #include "dce110/dce110_resource.h"
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#include "dce112/dce112_resource.h"
-+#endif
- 
- enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
-- {
-+{
- 	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
--
- 	switch (asic_id.chip_family) {
- 
- #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-@@ -68,6 +70,12 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
- 			break;
- 		}
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+		if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
-+				ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev)) {
-+			dc_version = DCE_VERSION_11_2;
-+		}
-+#endif
- 		break;
- 	default:
- 		dc_version = DCE_VERSION_UNKNOWN;
-@@ -83,6 +91,11 @@ bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- {
- 
- 	switch (dc_version) {
-+#if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-+	case DCE_VERSION_8_0:
-+		return dce80_construct_resource_pool(
-+			adapter_serv, num_virtual_links, dc, &dc->res_pool);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- 		return dce100_construct_resource_pool(
-@@ -93,6 +106,11 @@ bool dc_construct_resource_pool(struct adapter_service *adapter_serv,
- 		return dce110_construct_resource_pool(
- 			adapter_serv, num_virtual_links, dc, &dc->res_pool);
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		return dce112_construct_resource_pool(
-+			adapter_serv, num_virtual_links, dc, &dc->res_pool);
-+#endif
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 3d4f8b7..a21fcbd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -416,6 +416,7 @@ static void dce110_crtc_switch_to_clk_src(
- 	uint32_t pixel_rate_cntl_value;
- 	uint32_t addr;
- 
-+	/* These addresses are the same across DCE8 - DCE11.2 */
- 	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
- 			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index de370ee..a9ef65d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -59,7 +59,7 @@ enum black_color_format {
- 
- /* Flowing register offsets are same in files of
-  * dce/dce_11_0_d.h
-- * dce/vi_ellesmere_p/vi_ellesmere_d.h
-+ * dce/vi_polaris10_p/vi_polaris10_d.h
-  *
-  * So we can create dce110 timing generator to use it.
-  */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/Makefile b/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
-new file mode 100644
-index 0000000..c7d61d9
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE112 = dce112_link_encoder.o dce112_compressor.o dce112_hw_sequencer.o \
-+dce112_resource.o dce112_clock_source.o dce112_mem_input.o
-+
-+AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))
-+
-+AMD_DAL_FILES += $(AMD_DAL_DCE112)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
-new file mode 100644
-index 0000000..7ec9508
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
-@@ -0,0 +1,266 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce112_clock_source.h"
-+
-+/* include DCE11.2 register header files */
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "core_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+
-+/**
-+ * Calculate PLL Dividers for given Clock Value.
-+ * First will call VBIOS Adjust Exec table to check if requested Pixel clock
-+ * will be Adjusted based on usage.
-+ * Then it will calculate PLL Dividers for this Adjusted clock using preferred
-+ * method (Maximum VCO frequency).
-+ *
-+ * \return
-+ *     Calculation error in units of 0.01%
-+ */
-+static uint32_t dce112_get_pix_clk_dividers(
-+		struct clock_source *cs,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct dce112_clk_src *clk_src = TO_DCE112_CLK_SRC(cs);
-+	uint32_t actualPixelClockInKHz;
-+
-+	if (pix_clk_params == NULL || pll_settings == NULL
-+			|| pix_clk_params->requested_pix_clk == 0) {
-+		dal_logger_write(cs->ctx->logger,
-+			LOG_MAJOR_ERROR,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"%s: Invalid parameters!!\n", __func__);
-+		return 0;
-+	}
-+
-+	memset(pll_settings, 0, sizeof(*pll_settings));
-+
-+	if (clk_src->base.id == CLOCK_SOURCE_ID_DP_DTO) {
-+		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-+		pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
-+		pll_settings->actual_pix_clk =
-+					pix_clk_params->requested_pix_clk;
-+		return 0;
-+	}
-+	/* PLL only after this point */
-+
-+	actualPixelClockInKHz = pix_clk_params->requested_pix_clk;
-+
-+	/* Calculate Dividers */
-+	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		switch (pix_clk_params->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			actualPixelClockInKHz = (actualPixelClockInKHz * 5) >> 2;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			actualPixelClockInKHz = (actualPixelClockInKHz * 6) >> 2;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			actualPixelClockInKHz = actualPixelClockInKHz * 2;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	pll_settings->actual_pix_clk = actualPixelClockInKHz;
-+	pll_settings->adjusted_pix_clk = actualPixelClockInKHz;
-+	pll_settings->calculated_pix_clk = pix_clk_params->requested_pix_clk;
-+
-+	return 0;
-+}
-+
-+static void program_pixel_clk_resync(
-+		struct dce112_clk_src *clk_src,
-+		enum signal_type signal_type,
-+		enum dc_color_depth colordepth)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(clk_src->base.ctx,
-+		clk_src->offsets.pixclk_resync_cntl);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		PHYPLLA_PIXCLK_RESYNC_CNTL,
-+		PHYPLLA_DCCG_DEEP_COLOR_CNTL);
-+
-+	/*
-+	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
-+	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
-+	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
-+	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
-+	 */
-+	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return;
-+
-+	switch (colordepth) {
-+	case COLOR_DEPTH_888:
-+		set_reg_field_value(
-+			value,
-+			0,
-+			PHYPLLA_PIXCLK_RESYNC_CNTL,
-+			PHYPLLA_DCCG_DEEP_COLOR_CNTL);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		set_reg_field_value(
-+			value,
-+			1,
-+			PHYPLLA_PIXCLK_RESYNC_CNTL,
-+			PHYPLLA_DCCG_DEEP_COLOR_CNTL);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		set_reg_field_value(
-+			value,
-+			2,
-+			PHYPLLA_PIXCLK_RESYNC_CNTL,
-+			PHYPLLA_DCCG_DEEP_COLOR_CNTL);
-+		break;
-+	case COLOR_DEPTH_161616:
-+		set_reg_field_value(
-+			value,
-+			3,
-+			PHYPLLA_PIXCLK_RESYNC_CNTL,
-+			PHYPLLA_DCCG_DEEP_COLOR_CNTL);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dm_write_reg(
-+		clk_src->base.ctx,
-+		clk_src->offsets.pixclk_resync_cntl,
-+		value);
-+}
-+
-+static bool dce112_program_pix_clk(
-+		struct clock_source *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct dce112_clk_src *dce112_clk_src = TO_DCE112_CLK_SRC(clk_src);
-+	struct bp_pixel_clock_parameters bp_pc_params = {0};
-+
-+	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
-+	bp_pc_params.controller_id = pix_clk_params->controller_id;
-+	bp_pc_params.pll_id = clk_src->id;
-+	bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
-+	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_pc_params.signal_type = pix_clk_params->signal_type;
-+
-+	if (clk_src->id != CLOCK_SOURCE_ID_DP_DTO) {
-+		bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
-+						pll_settings->use_external_clk;
-+		bp_pc_params.flags.SET_XTALIN_REF_SRC =
-+						!pll_settings->use_external_clk;
-+		bp_pc_params.flags.SUPPORT_YUV_420 = 0;
-+	}
-+
-+	if (dce112_clk_src->bios->funcs->set_pixel_clock(
-+			dce112_clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+		return false;
-+
-+	/* TODO: support YCBCR420 */
-+
-+	/* Resync deep color DTO */
-+	if (clk_src->id != CLOCK_SOURCE_ID_DP_DTO)
-+		program_pixel_clk_resync(dce112_clk_src,
-+					pix_clk_params->signal_type,
-+					pix_clk_params->color_depth);
-+
-+	return true;
-+}
-+
-+static bool dce112_clock_source_power_down(
-+		struct clock_source *clk_src)
-+{
-+	struct dce112_clk_src *dce112_clk_src = TO_DCE112_CLK_SRC(clk_src);
-+	enum bp_result bp_result;
-+	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
-+
-+	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO)
-+		return true;
-+
-+	/* If Pixel Clock is 0 it means Power Down Pll*/
-+	bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
-+	bp_pixel_clock_params.pll_id = clk_src->id;
-+	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	bp_result = dce112_clk_src->bios->funcs->set_pixel_clock(
-+			dce112_clk_src->bios,
-+			&bp_pixel_clock_params);
-+
-+	return bp_result == BP_RESULT_OK;
-+}
-+
-+/*****************************************/
-+/* Constructor                           */
-+/*****************************************/
-+static struct clock_source_funcs dce112_clk_src_funcs = {
-+	.cs_power_down = dce112_clock_source_power_down,
-+	.program_pix_clk = dce112_program_pix_clk,
-+	.get_pix_clk_dividers = dce112_get_pix_clk_dividers
-+};
-+
-+bool dce112_clk_src_construct(
-+	struct dce112_clk_src *clk_src,
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce112_clk_src_reg_offsets *reg_offsets)
-+{
-+	struct firmware_info fw_info = { { 0 } };
-+
-+	clk_src->base.ctx = ctx;
-+	clk_src->bios = bios;
-+	clk_src->base.id = id;
-+	clk_src->base.funcs = &dce112_clk_src_funcs;
-+	clk_src->offsets = *reg_offsets;
-+
-+	if (clk_src->bios->funcs->get_firmware_info(
-+			clk_src->bios, &fw_info) != BP_RESULT_OK) {
-+		ASSERT_CRITICAL(false);
-+		goto unexpected_failure;
-+	}
-+
-+	clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp;
-+
-+	return true;
-+
-+unexpected_failure:
-+	return false;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.h
-new file mode 100644
-index 0000000..40ecc58
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.h
-@@ -0,0 +1,52 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_CLOCK_SOURCE_DCE110_H__
-+#define __DC_CLOCK_SOURCE_DCE110_H__
-+
-+#include "clock_source.h"
-+
-+#define TO_DCE112_CLK_SRC(clk_src)\
-+	container_of(clk_src, struct dce112_clk_src, base)
-+
-+struct dce112_clk_src_reg_offsets {
-+	uint32_t pixclk_resync_cntl;
-+};
-+
-+struct dce112_clk_src {
-+	struct clock_source base;
-+	struct dce112_clk_src_reg_offsets offsets;
-+	struct dc_bios *bios;
-+
-+	uint32_t ext_clk_khz;
-+};
-+
-+bool dce112_clk_src_construct(
-+	struct dce112_clk_src *clk_src,
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id,
-+	const struct dce112_clk_src_reg_offsets *reg_offsets);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
-new file mode 100644
-index 0000000..9526ffd
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
-@@ -0,0 +1,883 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+
-+#include "include/logger_interface.h"
-+#include "include/adapter_service_interface.h"
-+
-+#include "dce112_compressor.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + cp110->offsets.dcp_offset)
-+#define DMIF_REG(reg)\
-+	(reg + cp110->offsets.dmif_offset)
-+
-+static const struct dce112_compressor_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+}
-+};
-+
-+static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
-+
-+enum fbc_idle_force {
-+	/* Bit 0 - Display registers updated */
-+	FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
-+
-+	/* Bit 2 - FBC_GRPH_COMP_EN register updated */
-+	FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
-+	/* Bit 3 - FBC_SRC_SEL register updated */
-+	FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
-+	/* Bit 4 - FBC_MIN_COMPRESSION register updated */
-+	FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
-+	/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-+	FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
-+	/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-+	FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
-+	/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-+	FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
-+
-+	/* Bit 24 - Memory write to region 0 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
-+	/* Bit 25 - Memory write to region 1 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
-+	/* Bit 26 - Memory write to region 2 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
-+	/* Bit 27 - Memory write to region 3 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
-+
-+	/* Bit 28 - Memory write from any client other than MCIF */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
-+	/* Bit 29 - CG statics screen signal is inactive */
-+	FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
-+};
-+
-+static uint32_t lpt_size_alignment(struct dce112_compressor *cp110)
-+{
-+	/*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-+	return cp110->base.raw_size * cp110->base.banks_num *
-+		cp110->base.dram_channels_num;
-+}
-+
-+static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
-+	uint32_t lpt_control)
-+{
-+	/*LPT MC Config */
-+	if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
-+		/* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-+		 * 00 - 1 CHANNEL
-+		 * 01 - 2 CHANNELS
-+		 * 02 - 4 OR 6 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ)
-+		 * 03 - 8 OR 12 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ) */
-+		switch (cp110->base.dram_channels_num) {
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		case 1:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT NUM_PIPES!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LPT NUM_BANKS is in
-+		 * GRPH_CONTROL.GRPH_NUM_BANKS register field
-+		 * Specifies the number of memory banks for tiling
-+		 * purposes. Only applies to 2D and 3D tiling modes.
-+		 * POSSIBLE VALUES:
-+		 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-+		 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-+		 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-+		 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-+		switch (cp110->base.banks_num) {
-+		case 16:
-+			set_reg_field_value(
-+				lpt_control,
-+				3,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 8:
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 4:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT NUM_BANKS!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping is in DMIF_ADDR_CALC.
-+		 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-+		 * Carrizo specifies the memory interleave per pipe.
-+		 * It effectively specifies the location of pipe bits in
-+		 * the memory address.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
-+		 * interleave
-+		 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
-+		 * interleave
-+		 */
-+		switch (cp110->base.channel_interleave_size) {
-+		case 256: /*256B */
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		case 512: /*512B */
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT INTERLEAVE_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LOW_POWER_TILING_ROW_SIZE is in
-+		 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
-+		 * for Carrizo. Specifies the size of dram row in bytes.
-+		 * This should match up with NOOFCOLS field in
-+		 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
-+		 * This register DMIF_ADDR_CALC is not used by the
-+		 * hardware as it is only used for addrlib assertions.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
-+		 * boundary
-+		 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
-+		 * boundary
-+		 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
-+		 * boundary */
-+		switch (cp110->base.raw_size) {
-+		case 4096: /*4 KB */
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 2048:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 1024:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		default:
-+			dal_logger_write(
-+				cp110->base.ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: Invalid LPT ROW_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+	} else {
-+		dal_logger_write(
-+			cp110->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: LPT MC Configuration is not provided",
-+			__func__);
-+	}
-+
-+	return lpt_control;
-+}
-+
-+static bool is_source_bigger_than_epanel_size(
-+	struct dce112_compressor *cp110,
-+	uint32_t source_view_width,
-+	uint32_t source_view_height)
-+{
-+	if (cp110->base.embedded_panel_h_size != 0 &&
-+		cp110->base.embedded_panel_v_size != 0 &&
-+		((source_view_width * source_view_height) >
-+		(cp110->base.embedded_panel_h_size *
-+			cp110->base.embedded_panel_v_size)))
-+		return true;
-+
-+	return false;
-+}
-+
-+static uint32_t align_to_chunks_number_per_line(
-+	struct dce112_compressor *cp110,
-+	uint32_t pixels)
-+{
-+	return 256 * ((pixels + 255) / 256);
-+}
-+
-+static void wait_for_fbc_state_changed(
-+	struct dce112_compressor *cp110,
-+	bool enabled)
-+{
-+	uint8_t counter = 0;
-+	uint32_t addr = mmFBC_STATUS;
-+	uint32_t value;
-+
-+	while (counter < 10) {
-+		value = dm_read_reg(cp110->base.ctx, addr);
-+		if (get_reg_field_value(
-+			value,
-+			FBC_STATUS,
-+			FBC_ENABLE_STATUS) == enabled)
-+			break;
-+		udelay(10);
-+		counter++;
-+	}
-+
-+	if (counter == 10) {
-+		dal_logger_write(
-+			cp110->base.ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: wait counter exceeded, changes to HW not applied",
-+			__func__);
-+	}
-+}
-+
-+void dce112_compressor_power_up_fbc(struct compressor *compressor)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmFBC_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
-+	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-+	if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
-+		/* HW needs to do power measurement comparison. */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			FBC_CNTL,
-+			FBC_COMP_CLK_GATE_EN);
-+	}
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_MODE;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
-+	/*                    1 ==> 4:1 */
-+	/*                    2 ==> 8:1 */
-+	/*                  0xF ==> 1:1 */
-+	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
-+
-+	value = 0;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+
-+	value = 0xFFFFFF;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+}
-+
-+void dce112_compressor_enable_fbc(
-+	struct compressor *compressor,
-+	uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		(compressor->options.bits.DUMMY_BACKEND == 0) &&
-+		(!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
-+		(!is_source_bigger_than_epanel_size(
-+			cp110,
-+			params->source_view_width,
-+			params->source_view_height))) {
-+
-+		uint32_t addr;
-+		uint32_t value;
-+
-+		/* Before enabling FBC first need to enable LPT if applicable
-+		 * LPT state should always be changed (enable/disable) while FBC
-+		 * is disabled */
-+		if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
-+			(params->source_view_width *
-+				params->source_view_height <=
-+				dce11_one_lpt_channel_max_resolution)) {
-+			dce112_compressor_enable_lpt(compressor);
-+		}
-+
-+		addr = mmFBC_CNTL;
-+		value = dm_read_reg(compressor->ctx, addr);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		set_reg_field_value(
-+			value,
-+			params->inst,
-+			FBC_CNTL, FBC_SRC_SEL);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		/* Keep track of enum controller_id FBC is attached to */
-+		compressor->is_enabled = true;
-+		compressor->attached_inst = params->inst;
-+		cp110->offsets = reg_offsets[params->inst - 1];
-+
-+		/*Toggle it as there is bug in HW */
-+		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		wait_for_fbc_state_changed(cp110, true);
-+	}
-+}
-+
-+void dce112_compressor_disable_fbc(struct compressor *compressor)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
-+		uint32_t reg_data;
-+		/* Turn off compression */
-+		reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+
-+		/* Reset enum controller_id to undefined */
-+		compressor->attached_inst = 0;
-+		compressor->is_enabled = false;
-+
-+		/* Whenever disabling FBC make sure LPT is disabled if LPT
-+		 * supported */
-+		if (compressor->options.bits.LPT_SUPPORT)
-+			dce112_compressor_disable_lpt(compressor);
-+
-+		wait_for_fbc_state_changed(cp110, false);
-+	}
-+}
-+
-+bool dce112_compressor_is_fbc_enabled_in_hw(
-+	struct compressor *compressor,
-+	uint32_t *inst)
-+{
-+	/* Check the hardware register */
-+	uint32_t value;
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
-+	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
-+		if (inst != NULL)
-+			*inst = compressor->attached_inst;
-+		return true;
-+	}
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_MISC);
-+	if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
-+		value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+
-+		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
-+			if (inst != NULL)
-+				*inst =
-+					compressor->attached_inst;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
-+{
-+	/* Check the hardware register */
-+	uint32_t value = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	return get_reg_field_value(
-+		value,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+}
-+
-+void dce112_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t value = 0;
-+	uint32_t fbc_pitch = 0;
-+	uint32_t compressed_surf_address_low_part =
-+		compressor->compr_surface_address.addr.low_part;
-+
-+	/* Clear content first. */
-+	dm_write_reg(
-+		compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		0);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
-+
-+	if (compressor->options.bits.LPT_SUPPORT) {
-+		uint32_t lpt_alignment = lpt_size_alignment(cp110);
-+
-+		if (lpt_alignment != 0) {
-+			compressed_surf_address_low_part =
-+				((compressed_surf_address_low_part
-+					+ (lpt_alignment - 1)) / lpt_alignment)
-+					* lpt_alignment;
-+		}
-+	}
-+
-+	/* Write address, HIGH has to be first. */
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		compressor->compr_surface_address.addr.high_part);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
-+		compressed_surf_address_low_part);
-+
-+	fbc_pitch = align_to_chunks_number_per_line(
-+		cp110,
-+		params->source_view_width);
-+
-+	if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
-+		fbc_pitch = fbc_pitch / 8;
-+	else
-+		dal_logger_write(
-+			compressor->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: Unexpected DCE11 compression ratio",
-+			__func__);
-+
-+	/* Clear content first. */
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+
-+	/* Write FBC Pitch. */
-+	set_reg_field_value(
-+		value,
-+		fbc_pitch,
-+		GRPH_COMPRESS_PITCH,
-+		GRPH_COMPRESS_PITCH);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+
-+}
-+
-+void dce112_compressor_disable_lpt(struct compressor *compressor)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t inx;
-+
-+	/* Disable all pipes LPT Stutter */
-+	for (inx = 0; inx < 3; inx++) {
-+		value =
-+			dm_read_reg(
-+				compressor->ctx,
-+				DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+			STUTTER_ENABLE_NONLPTCH);
-+		dm_write_reg(
-+			compressor->ctx,
-+			DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
-+			value);
-+	}
-+	/* Disable Underlay pipe LPT Stutter */
-+	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Disable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Clear selection of Channel(s) containing Compressed Surface */
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0xFFFFFFFF,
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
-+}
-+
-+void dce112_compressor_enable_lpt(struct compressor *compressor)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t value_control;
-+	uint32_t channels;
-+
-+	/* Enable LPT Stutter from Display pipe */
-+	value = dm_read_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
-+
-+	/* Enable Underlay pipe LPT Stutter */
-+	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Selection of Channel(s) containing Compressed Surface: 0xfffffff
-+	 * will disable LPT.
-+	 * STCTRL_LPT_TARGETn corresponds to channel n. */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value_control = dm_read_reg(compressor->ctx, addr);
-+	channels = get_reg_field_value(value_control,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		channels + 1, /* not mentioned in programming guide,
-+				but follow DCE8.1 */
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Enable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce112_compressor_program_lpt_control(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t rows_per_channel;
-+	uint32_t lpt_alignment;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+	uint32_t lpt_control = 0;
-+
-+	if (!compressor->options.bits.LPT_SUPPORT)
-+		return;
-+
-+	lpt_control = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	/* POSSIBLE VALUES for Low Power Tiling Mode:
-+	 * 00 - Use channel 0
-+	 * 01 - Use Channel 0 and 1
-+	 * 02 - Use Channel 0,1,2,3
-+	 * 03 - reserved */
-+	switch (compressor->lpt_channels_num) {
-+	/* case 2:
-+	 * Use Channel 0 & 1 / Not used for DCE 11 */
-+	case 1:
-+		/*Use Channel 0 for LPT for DCE 11 */
-+		set_reg_field_value(
-+			lpt_control,
-+			0,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+		break;
-+	default:
-+		dal_logger_write(
-+			compressor->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_CONTROLLER,
-+			"%s: Invalid selected DRAM channels for LPT!!!",
-+			__func__);
-+		break;
-+	}
-+
-+	lpt_control = lpt_memory_control_config(cp110, lpt_control);
-+
-+	/* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
-+	 * FBC compressed surface pitch.
-+	 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
-+	 * Surface Pitch) / (Row Size * Number of Channels *
-+	 * Number of Banks)). */
-+	rows_per_channel = 0;
-+	lpt_alignment = lpt_size_alignment(cp110);
-+	source_view_width =
-+		align_to_chunks_number_per_line(
-+			cp110,
-+			params->source_view_width);
-+	source_view_height = (params->source_view_height + 1) & (~0x1);
-+
-+	if (lpt_alignment != 0) {
-+		rows_per_channel = source_view_width * source_view_height * 4;
-+		rows_per_channel =
-+			(rows_per_channel % lpt_alignment) ?
-+				(rows_per_channel / lpt_alignment + 1) :
-+				rows_per_channel / lpt_alignment;
-+	}
-+
-+	set_reg_field_value(
-+		lpt_control,
-+		rows_per_channel,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ROWS_PER_CHAN);
-+
-+	dm_write_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL, lpt_control);
-+}
-+
-+/*
-+ * DCE 11 Frame Buffer Compression Implementation
-+ */
-+
-+void dce112_compressor_set_fbc_invalidation_triggers(
-+	struct compressor *compressor,
-+	uint32_t fbc_trigger)
-+{
-+	/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
-+	 * for DCE 11 regions cannot be used - does not work with S/G
-+	 */
-+	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
-+	uint32_t value = dm_read_reg(compressor->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		FBC_CLIENT_REGION_MASK,
-+		FBC_MEMORY_REGION_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Setup events when to clear all CSM entries (effectively marking
-+	 * current compressed data invalid)
-+	 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
-+	 * Used as the initial value of the metadata sent to the compressor
-+	 * after invalidation, to indicate that the compressor should attempt
-+	 * to compress all chunks on the current pass.  Also used when the chunk
-+	 * is not successfully written to memory.
-+	 * When this CSM value is detected, FBC reads from the uncompressed
-+	 * buffer. Set events according to passed in value, these events are
-+	 * valid for DCE11:
-+	 *     - bit  0 - display register updated
-+	 *     - bit 28 - memory write from any client except from MCIF
-+	 *     - bit 29 - CG static screen signal is inactive
-+	 * In addition, DCE11.1 also needs to set new DCE11.1 specific events
-+	 * that are used to trigger invalidation on certain register changes,
-+	 * for example enabling of Alpha Compression may trigger invalidation of
-+	 * FBC once bit is set. These events are as follows:
-+	 *      - Bit 2 - FBC_GRPH_COMP_EN register updated
-+	 *      - Bit 3 - FBC_SRC_SEL register updated
-+	 *      - Bit 4 - FBC_MIN_COMPRESSION register updated
-+	 *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
-+	 *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
-+	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
-+	 */
-+	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		fbc_trigger |
-+		FBC_IDLE_FORCE_GRPH_COMP_EN |
-+		FBC_IDLE_FORCE_SRC_SEL_CHANGE |
-+		FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
-+		FBC_IDLE_FORCE_ALPHA_COMP_EN |
-+		FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
-+		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
-+		FBC_IDLE_FORCE_CLEAR_MASK,
-+		FBC_IDLE_FORCE_CLEAR_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+bool dce112_compressor_construct(struct dce112_compressor *compressor,
-+	struct dc_context *ctx, struct adapter_service *as)
-+{
-+	struct embedded_panel_info panel_info;
-+
-+	compressor->base.options.bits.FBC_SUPPORT = true;
-+	if (!(dal_adapter_service_is_feature_supported(
-+		FEATURE_DISABLE_LPT_SUPPORT)))
-+		compressor->base.options.bits.LPT_SUPPORT = true;
-+	 /* For DCE 11 always use one DRAM channel for LPT */
-+	compressor->base.lpt_channels_num = 1;
-+
-+	if (dal_adapter_service_is_feature_supported(FEATURE_DUMMY_FBC_BACKEND))
-+		compressor->base.options.bits.DUMMY_BACKEND = true;
-+
-+	/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
-+	 * should not be supported */
-+	if (compressor->base.memory_bus_width == 64)
-+		compressor->base.options.bits.LPT_SUPPORT = false;
-+
-+	if (dal_adapter_service_is_feature_supported(
-+		FEATURE_DISABLE_FBC_COMP_CLK_GATE))
-+		compressor->base.options.bits.CLK_GATING_DISABLED = true;
-+
-+	compressor->base.ctx = ctx;
-+	compressor->base.embedded_panel_h_size = 0;
-+	compressor->base.embedded_panel_v_size = 0;
-+	compressor->base.memory_bus_width =
-+		dal_adapter_service_get_asic_vram_bit_width(as);
-+	compressor->base.allocated_size = 0;
-+	compressor->base.preferred_requested_size = 0;
-+	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-+	compressor->base.options.raw = 0;
-+	compressor->base.banks_num = 0;
-+	compressor->base.raw_size = 0;
-+	compressor->base.channel_interleave_size = 0;
-+	compressor->base.dram_channels_num = 0;
-+	compressor->base.lpt_channels_num = 0;
-+	compressor->base.attached_inst = 0;
-+	compressor->base.is_enabled = false;
-+
-+	if (dal_adapter_service_get_embedded_panel_info(as,
-+		&panel_info)) {
-+		compressor->base.embedded_panel_h_size =
-+			panel_info.lcd_timing.horizontal_addressable;
-+		compressor->base.embedded_panel_v_size =
-+			panel_info.lcd_timing.vertical_addressable;
-+	}
-+	return true;
-+}
-+
-+struct compressor *dce112_compressor_create(struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct dce112_compressor *cp110 =
-+		dm_alloc(sizeof(struct dce112_compressor));
-+
-+	if (!cp110)
-+		return NULL;
-+
-+	if (dce112_compressor_construct(cp110, ctx, as))
-+		return &cp110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(cp110);
-+	return NULL;
-+}
-+
-+void dce112_compressor_destroy(struct compressor **compressor)
-+{
-+	dm_free(TO_DCE112_COMPRESSOR(*compressor));
-+	*compressor = NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
-new file mode 100644
-index 0000000..bcf4480
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
-@@ -0,0 +1,84 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMPRESSOR_DCE112_H__
-+#define __DC_COMPRESSOR_DCE112_H__
-+
-+#include "../inc/compressor.h"
-+
-+#define TO_DCE112_COMPRESSOR(compressor)\
-+	container_of(compressor, struct dce112_compressor, base)
-+
-+struct dce112_compressor_reg_offsets {
-+	uint32_t dcp_offset;
-+	uint32_t dmif_offset;
-+};
-+
-+struct dce112_compressor {
-+	struct compressor base;
-+	struct dce112_compressor_reg_offsets offsets;
-+};
-+
-+struct compressor *dce112_compressor_create(struct dc_context *ctx,
-+	struct adapter_service *as);
-+
-+bool dce112_compressor_construct(struct dce112_compressor *cp110,
-+	struct dc_context *ctx, struct adapter_service *as);
-+
-+void dce112_compressor_destroy(struct compressor **cp);
-+
-+/* FBC RELATED */
-+void dce112_compressor_power_up_fbc(struct compressor *cp);
-+
-+void dce112_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params);
-+
-+void dce112_compressor_disable_fbc(struct compressor *cp);
-+
-+void dce112_compressor_set_fbc_invalidation_triggers(struct compressor *cp,
-+	uint32_t fbc_trigger);
-+
-+void dce112_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce112_compressor_get_required_compressed_surface_size(
-+	struct compressor *cp,
-+	struct fbc_input_info *input_info,
-+	struct fbc_requested_compressed_size *size);
-+
-+bool dce112_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
-+	uint32_t *fbc_mapped_crtc_id);
-+
-+/* LPT RELATED */
-+void dce112_compressor_enable_lpt(struct compressor *cp);
-+
-+void dce112_compressor_disable_lpt(struct compressor *cp);
-+
-+void dce112_compressor_program_lpt_control(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-new file mode 100644
-index 0000000..b94130f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-@@ -0,0 +1,178 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_dc.h"
-+#include "core_types.h"
-+#include "dce112_hw_sequencer.h"
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+#include "gpu/dce112/dc_clock_gating_dce112.h"
-+
-+/* include DCE11.2 register header files */
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+static void dce112_crtc_switch_to_clk_src(
-+				struct clock_source *clk_src, uint8_t crtc_inst)
-+{
-+	uint32_t pixel_rate_cntl_value;
-+	uint32_t addr;
-+
-+	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
-+			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-+
-+	pixel_rate_cntl_value = dm_read_reg(clk_src->ctx, addr);
-+
-+	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO)
-+		set_reg_field_value(pixel_rate_cntl_value, 1,
-+			CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
-+	else {
-+		set_reg_field_value(pixel_rate_cntl_value,
-+				0,
-+				CRTC0_PIXEL_RATE_CNTL,
-+				DP_DTO0_ENABLE);
-+
-+		set_reg_field_value(pixel_rate_cntl_value,
-+				clk_src->id - 1,
-+				CRTC0_PIXEL_RATE_CNTL,
-+				CRTC0_PIXEL_RATE_SOURCE);
-+	}
-+	dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-+}
-+
-+static void dce112_init_pte(struct dc_context *ctx)
-+{
-+	uint32_t addr;
-+	uint32_t value = 0;
-+	uint32_t chunk_int = 0;
-+	uint32_t chunk_mul = 0;
-+
-+	addr = mmUNP_DVMM_PTE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DVMM_PTE_CONTROL,
-+		DVMM_USE_SINGLE_PTE);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DVMM_PTE_CONTROL,
-+		DVMM_PTE_BUFFER_MODE0);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DVMM_PTE_CONTROL,
-+		DVMM_PTE_BUFFER_MODE1);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmDVMM_PTE_REQ;
-+	value = dm_read_reg(ctx, addr);
-+
-+	chunk_int = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+	chunk_mul = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+	if (chunk_int != 0x4 || chunk_mul != 0x4) {
-+
-+		set_reg_field_value(
-+			value,
-+			255,
-+			DVMM_PTE_REQ,
-+			MAX_PTEREQ_TO_ISSUE);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+static bool dce112_enable_display_power_gating(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
-+		return true;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0)
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-+		dce112_init_pte(ctx);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+bool dce112_hw_sequencer_construct(struct core_dc *dc)
-+{
-+	/* All registers used by dce11.2 match those in dce11 in offset and
-+	 * structure
-+	 */
-+	dce110_hw_sequencer_construct(dc);
-+	dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
-+	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
-+	dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
-+
-+	return true;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.h
-new file mode 100644
-index 0000000..d96c582
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.h
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE112_H__
-+#define __DC_HWSS_DCE112_H__
-+
-+#include "core_types.h"
-+
-+struct core_dc;
-+
-+bool dce112_hw_sequencer_construct(struct core_dc *dc);
-+
-+#endif /* __DC_HWSS_DCE112_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
-new file mode 100644
-index 0000000..23e127c
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "core_types.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+#include "dce112_link_encoder.h"
-+#include "../dce110/dce110_link_encoder.h"
-+#include "i2caux_interface.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+/* For current ASICs pixel clock - 600MHz */
-+#define MAX_ENCODER_CLK 600000
-+
-+#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 600000
-+
-+#define DEFAULT_AUX_MAX_DATA_SIZE 16
-+#define AUX_MAX_DEFER_WRITE_RETRY 20
-+
-+/* all values are in milliseconds */
-+/* For eDP, after power-up/power/down,
-+ * 300/500 msec max. delay from LCDVCC to black video generation */
-+#define PANEL_POWER_UP_TIMEOUT 300
-+#define PANEL_POWER_DOWN_TIMEOUT 500
-+#define HPD_CHECK_INTERVAL 10
-+
-+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-+#define TMDS_MIN_PIXEL_CLOCK 25000
-+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-+#define TMDS_MAX_PIXEL_CLOCK 165000
-+/* For current ASICs pixel clock - 600MHz */
-+#define MAX_ENCODER_CLOCK 600000
-+
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
-+static void dce112_link_encoder_dp_set_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param)
-+{
-+	switch (param->dp_phy_pattern) {
-+	case DP_TEST_PATTERN_TRAINING_PATTERN4:
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
-+		break;
-+	default:
-+		dce110_link_encoder_dp_set_phy_pattern(enc, param);
-+		break;
-+	}
-+}
-+
-+static struct link_encoder_funcs dce112_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		dce110_link_encoder_validate_output_with_stream,
-+	.hw_init = dce110_link_encoder_hw_init,
-+	.setup = dce110_link_encoder_setup,
-+	.enable_tmds_output = dce110_link_encoder_enable_tmds_output,
-+	.enable_dp_output = dce110_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
-+	.disable_output = dce110_link_encoder_disable_output,
-+	.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = dce112_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		dce110_link_encoder_update_mst_stream_allocation_table,
-+	.set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
-+	.backlight_control = dce110_link_encoder_edp_backlight_control,
-+	.power_control = dce110_link_encoder_edp_power_control,
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
-+	.destroy = dce110_link_encoder_destroy
-+};
-+
-+bool dce112_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs)
-+{
-+	dce110_link_encoder_construct(
-+		enc110,
-+		init_data,
-+		link_regs,
-+		aux_regs,
-+		bl_regs);
-+
-+	enc110->base.funcs = &dce112_lnk_enc_funcs;
-+
-+	enc110->base.features.flags.bits.IS_HBR3_CAPABLE = true;
-+
-+	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
-new file mode 100644
-index 0000000..cfc9cc5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
-@@ -0,0 +1,41 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_ENCODER__DCE112_H__
-+#define __DC_LINK_ENCODER__DCE112_H__
-+
-+#include "link_encoder.h"
-+#include "../dce110/dce110_link_encoder.h"
-+
-+bool dce112_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs);
-+
-+/****************** HW programming ************************/
-+
-+#endif /* __DC_LINK_ENCODER__DCE112_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c
-new file mode 100644
-index 0000000..823849e
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c
-@@ -0,0 +1,455 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "dce112_mem_input.h"
-+
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+
-+#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
-+#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
-+#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
-+
-+static void program_urgency_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t offset,
-+	struct bw_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	/* register value */
-+	uint32_t urgency_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	uint32_t urgency_addr = offset + mmDPG_PIPE_URGENCY_CONTROL;
-+	uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			0,
-+			DPG_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		marks_low.a_mark,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			1,
-+			DPG_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(urgency_cntl,
-+		marks_low.b_mark,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set C*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			2,
-+			DPG_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(urgency_cntl,
-+		marks_low.c_mark,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set D*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			3,
-+			DPG_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(urgency_cntl,
-+		marks_low.d_mark,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPG_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+}
-+
-+static void program_stutter_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t offset,
-+	struct bw_watermarks marks)
-+{
-+	/* register value */
-+	uint32_t stutter_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	uint32_t stutter_addr = offset + mmDPG_PIPE_STUTTER_CONTROL;
-+	uint32_t wm_addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		0,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set A*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.a_mark,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		1,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set B*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.b_mark,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set C*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		2,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set C*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.c_mark,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set D*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		3,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE);
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set D*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.d_mark,
-+		DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+}
-+
-+static void program_nbp_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t offset,
-+	struct bw_watermarks marks)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+	/* Write mask to enable reading/writing of watermark set A */
-+	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write watermark set A */
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		marks.a_mark,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write mask to enable reading/writing of watermark set B */
-+	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write watermark set B */
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		marks.b_mark,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write mask to enable reading/writing of watermark set C */
-+	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write watermark set C */
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		marks.c_mark,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write mask to enable reading/writing of watermark set D */
-+	addr = offset + mmDPG_WATERMARK_MASK_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		3,
-+		DPG_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = offset + mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* Write watermark set D */
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		marks.d_mark,
-+		DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void dce112_mem_input_program_display_marks(
-+	struct mem_input *mem_input,
-+	struct bw_watermarks nbp,
-+	struct bw_watermarks stutter,
-+	struct bw_watermarks urgent,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mem_input);
-+
-+	program_urgency_watermark(
-+		mem_input->ctx,
-+		bm_dce110->offsets.dmif,
-+		urgent,
-+		total_dest_line_time_ns);
-+
-+	program_nbp_watermark(
-+		mem_input->ctx,
-+		bm_dce110->offsets.dmif,
-+		nbp);
-+
-+	program_stutter_watermark(
-+		mem_input->ctx,
-+		bm_dce110->offsets.dmif,
-+		stutter);
-+}
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce112_mem_input_construct(
-+	struct dce110_mem_input *mem_input110,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets)
-+{
-+	if (!dce110_mem_input_construct(mem_input110, ctx, inst, offsets))
-+		return false;
-+
-+	mem_input110->base.funcs->mem_input_program_display_marks =
-+					dce112_mem_input_program_display_marks;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h
-new file mode 100644
-index 0000000..de2aaf0
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h
-@@ -0,0 +1,38 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MEM_INPUT_DCE112_H__
-+#define __DC_MEM_INPUT_DCE112_H__
-+
-+#include "mem_input.h"
-+#include "dce110/dce110_mem_input.h"
-+
-+bool dce112_mem_input_construct(
-+	struct dce110_mem_input *mem_input110,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offsets);
-+
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-new file mode 100644
-index 0000000..420b8ca
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-@@ -0,0 +1,1404 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "../virtual/virtual_stream_encoder.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "dce112/dce112_mem_input.h"
-+#include "dce112/dce112_link_encoder.h"
-+#include "dce110/dce110_link_encoder.h"
-+#include "dce110/dce110_transform.h"
-+#include "dce110/dce110_stream_encoder.h"
-+#include "dce110/dce110_opp.h"
-+#include "dce110/dce110_ipp.h"
-+#include "dce112/dce112_clock_source.h"
-+
-+#include "dce/dce_11_2_d.h"
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
-+enum dce112_clk_src_array_id {
-+	DCE112_CLK_SRC_PLL0,
-+	DCE112_CLK_SRC_PLL1,
-+	DCE112_CLK_SRC_PLL2,
-+	DCE112_CLK_SRC_PLL3,
-+	DCE112_CLK_SRC_PLL4,
-+	DCE112_CLK_SRC_PLL5,
-+
-+	DCE112_CLK_SRC_TOTAL
-+};
-+
-+static const struct dce110_transform_reg_offsets dce112_xfm_offsets[] = {
-+{
-+	.scl_offset = (mmSCL0_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB0_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL1_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB1_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL2_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB2_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{
-+	.scl_offset = (mmSCL3_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB3_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL4_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB4_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+},
-+{	.scl_offset = (mmSCL5_SCL_CONTROL - mmSCL_CONTROL),
-+	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	.lb_offset = (mmLB5_LB_DATA_FORMAT - mmLB_DATA_FORMAT),
-+}
-+};
-+
-+static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	}
-+};
-+
-+static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets[] = {
-+	{
-+		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	},
-+	{
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+		.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
-+				- mmDPG_WATERMARK_MASK_CONTROL),
-+		.pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
-+				- mmPIPE0_DMIF_BUFFER_CONTROL),
-+	}
-+};
-+
-+static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
-+}
-+};
-+
-+static const struct dce110_link_enc_bl_registers link_enc_bl_regs = {
-+		.BL_PWM_CNTL = mmBL_PWM_CNTL,
-+		.BL_PWM_GRP1_REG_LOCK = mmBL_PWM_GRP1_REG_LOCK,
-+		.BL_PWM_PERIOD_CNTL = mmBL_PWM_PERIOD_CNTL,
-+		.LVTMA_PWRSEQ_CNTL = mmLVTMA_PWRSEQ_CNTL,
-+		.LVTMA_PWRSEQ_STATE = mmLVTMA_PWRSEQ_STATE
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	.AUX_CONTROL = mmDP_AUX ## id ## _AUX_CONTROL,\
-+	.AUX_DPHY_RX_CONTROL0 = mmDP_AUX ## id ## _AUX_DPHY_RX_CONTROL0\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+	aux_regs(0),
-+	aux_regs(1),
-+	aux_regs(2),
-+	aux_regs(3),
-+	aux_regs(4),
-+	aux_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	.DIG_BE_CNTL = mmDIG ## id ## _DIG_BE_CNTL,\
-+	.DIG_BE_EN_CNTL = mmDIG ## id ## _DIG_BE_EN_CNTL,\
-+	.DP_CONFIG = mmDP ## id ## _DP_CONFIG,\
-+	.DP_DPHY_CNTL = mmDP ## id ## _DP_DPHY_CNTL,\
-+	.DP_DPHY_INTERNAL_CTRL = mmDP ## id ## _DP_DPHY_INTERNAL_CTRL,\
-+	.DP_DPHY_PRBS_CNTL = mmDP ## id ## _DP_DPHY_PRBS_CNTL,\
-+	.DP_DPHY_SYM0 = mmDP ## id ## _DP_DPHY_SYM0,\
-+	.DP_DPHY_SYM1 = mmDP ## id ## _DP_DPHY_SYM1,\
-+	.DP_DPHY_SYM2 = mmDP ## id ## _DP_DPHY_SYM2,\
-+	.DP_DPHY_TRAINING_PATTERN_SEL = mmDP ## id ## _DP_DPHY_TRAINING_PATTERN_SEL,\
-+	.DP_LINK_CNTL = mmDP ## id ## _DP_LINK_CNTL,\
-+	.DP_LINK_FRAMING_CNTL = mmDP ## id ## _DP_LINK_FRAMING_CNTL,\
-+	.DP_MSE_SAT0 = mmDP ## id ## _DP_MSE_SAT0,\
-+	.DP_MSE_SAT1 = mmDP ## id ## _DP_MSE_SAT1,\
-+	.DP_MSE_SAT2 = mmDP ## id ## _DP_MSE_SAT2,\
-+	.DP_MSE_SAT_UPDATE = mmDP ## id ## _DP_MSE_SAT_UPDATE,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5)
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	.AFMT_AVI_INFO0 = mmDIG ## id ## _AFMT_AVI_INFO0,\
-+	.AFMT_AVI_INFO1 = mmDIG ## id ## _AFMT_AVI_INFO1,\
-+	.AFMT_AVI_INFO2 = mmDIG ## id ## _AFMT_AVI_INFO2,\
-+	.AFMT_AVI_INFO3 = mmDIG ## id ## _AFMT_AVI_INFO3,\
-+	.AFMT_GENERIC_0 = mmDIG ## id ## _AFMT_GENERIC_0,\
-+	.AFMT_GENERIC_7 = mmDIG ## id ## _AFMT_GENERIC_7,\
-+	.AFMT_GENERIC_HDR = mmDIG ## id ## _AFMT_GENERIC_HDR,\
-+	.AFMT_INFOFRAME_CONTROL0 = mmDIG ## id ## _AFMT_INFOFRAME_CONTROL0,\
-+	.AFMT_VBI_PACKET_CONTROL = mmDIG ## id ## _AFMT_VBI_PACKET_CONTROL,\
-+	.DIG_FE_CNTL = mmDIG ## id ## _DIG_FE_CNTL,\
-+	.DP_MSE_RATE_CNTL = mmDP ## id ## _DP_MSE_RATE_CNTL,\
-+	.DP_MSE_RATE_UPDATE = mmDP ## id ## _DP_MSE_RATE_UPDATE,\
-+	.DP_PIXEL_FORMAT = mmDP ## id ## _DP_PIXEL_FORMAT,\
-+	.DP_SEC_CNTL = mmDP ## id ## _DP_SEC_CNTL,\
-+	.DP_STEER_FIFO = mmDP ## id ## _DP_STEER_FIFO,\
-+	.DP_VID_M = mmDP ## id ## _DP_VID_M,\
-+	.DP_VID_N = mmDP ## id ## _DP_VID_N,\
-+	.DP_VID_STREAM_CNTL = mmDP ## id ## _DP_VID_STREAM_CNTL,\
-+	.DP_VID_TIMING = mmDP ## id ## _DP_VID_TIMING,\
-+	.HDMI_CONTROL = mmDIG ## id ## _HDMI_CONTROL,\
-+	.HDMI_GC = mmDIG ## id ## _HDMI_GC,\
-+	.HDMI_GENERIC_PACKET_CONTROL0 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL0,\
-+	.HDMI_GENERIC_PACKET_CONTROL1 = mmDIG ## id ## _HDMI_GENERIC_PACKET_CONTROL1,\
-+	.HDMI_INFOFRAME_CONTROL0 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL0,\
-+	.HDMI_INFOFRAME_CONTROL1 = mmDIG ## id ## _HDMI_INFOFRAME_CONTROL1,\
-+	.HDMI_VBI_PACKET_CONTROL = mmDIG ## id ## _HDMI_VBI_PACKET_CONTROL,\
-+	.TMDS_CNTL = mmDIG ## id ## _TMDS_CNTL\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5)
-+};
-+
-+static const struct dce110_opp_reg_offsets dce112_opp_reg_offsets[] = {
-+{
-+	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-+	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+static const struct dce112_clk_src_reg_offsets dce112_clk_src_reg_offsets[] = {
-+	{
-+		.pixclk_resync_cntl  = mmPHYPLLA_PIXCLK_RESYNC_CNTL
-+	},
-+	{
-+		.pixclk_resync_cntl  = mmPHYPLLB_PIXCLK_RESYNC_CNTL
-+	},
-+	{
-+		.pixclk_resync_cntl  = mmPHYPLLC_PIXCLK_RESYNC_CNTL
-+	},
-+	{
-+		.pixclk_resync_cntl  = mmPHYPLLD_PIXCLK_RESYNC_CNTL
-+	},
-+	{
-+		.pixclk_resync_cntl  = mmPHYPLLE_PIXCLK_RESYNC_CNTL
-+	},
-+	{
-+		.pixclk_resync_cntl  = mmPHYPLLF_PIXCLK_RESYNC_CNTL
-+	}
-+};
-+
-+static struct timing_generator *dce112_timing_generator_create(
-+		struct adapter_service *as,
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		dm_alloc(sizeof(struct dce110_timing_generator));
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
-+		return &tg110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(tg110);
-+	return NULL;
-+}
-+
-+static struct stream_encoder *dce112_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp,
-+	const struct dce110_stream_enc_registers *regs)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		dm_alloc(sizeof(struct dce110_stream_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce110_stream_encoder_construct(enc110, ctx, bp, eng_id, regs))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(enc110);
-+	return NULL;
-+}
-+
-+static struct mem_input *dce112_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_mem_input_reg_offsets *offset)
-+{
-+	struct dce110_mem_input *mem_input110 =
-+		dm_alloc(sizeof(struct dce110_mem_input));
-+
-+	if (!mem_input110)
-+		return NULL;
-+
-+	if (dce112_mem_input_construct(mem_input110,
-+			ctx, inst, offset))
-+		return &mem_input110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(mem_input110);
-+	return NULL;
-+}
-+
-+static void dce112_transform_destroy(struct transform **xfm)
-+{
-+	dm_free(TO_DCE110_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce112_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_transform_reg_offsets *offsets)
-+{
-+	struct dce110_transform *transform =
-+		dm_alloc(sizeof(struct dce110_transform));
-+
-+	if (!transform)
-+		return NULL;
-+
-+	if (dce110_transform_construct(transform, ctx, inst, offsets))
-+		return &transform->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(transform);
-+	return NULL;
-+}
-+struct link_encoder *dce112_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		dm_alloc(sizeof(struct dce110_link_encoder));
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	if (dce112_link_encoder_construct(
-+			enc110,
-+			enc_init_data,
-+			&link_enc_regs[enc_init_data->transmitter],
-+			&link_enc_aux_regs[enc_init_data->channel - 1],
-+			&link_enc_bl_regs))
-+		return &enc110->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(enc110);
-+	return NULL;
-+}
-+
-+struct input_pixel_processor *dce112_ipp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_ipp_reg_offsets *offset)
-+{
-+	struct dce110_ipp *ipp =
-+		dm_alloc(sizeof(struct dce110_ipp));
-+
-+	if (!ipp)
-+		return NULL;
-+
-+	if (dce110_ipp_construct(ipp, ctx, inst, offset))
-+			return &ipp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(ipp);
-+	return NULL;
-+}
-+
-+void dce112_ipp_destroy(struct input_pixel_processor **ipp)
-+{
-+	dm_free(TO_DCE110_IPP(*ipp));
-+	*ipp = NULL;
-+}
-+
-+struct output_pixel_processor *dce112_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce110_opp_reg_offsets *offset)
-+{
-+	struct dce110_opp *opp =
-+		dm_alloc(sizeof(struct dce110_opp));
-+
-+	if (!opp)
-+		return NULL;
-+
-+	if (dce110_opp_construct(opp,
-+			ctx, inst, offset))
-+		return &opp->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	dm_free(opp);
-+	return NULL;
-+}
-+
-+void dce112_opp_destroy(struct output_pixel_processor **opp)
-+{
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coeff128_dx);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coeff128_oem);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coeff128);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.axis_x_1025);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.axis_x_256);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.coordinates_x);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_regamma);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_resulted);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_oem);
-+	dm_free(FROM_DCE11_OPP(*opp)->regamma.rgb_user);
-+	dm_free(FROM_DCE11_OPP(*opp));
-+	*opp = NULL;
-+}
-+
-+struct clock_source *dce112_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce112_clk_src_reg_offsets *offsets)
-+{
-+	struct dce112_clk_src *clk_src =
-+		dm_alloc(sizeof(struct dce112_clk_src));
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce112_clk_src_construct(clk_src, ctx, bios, id, offsets))
-+		return &clk_src->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce112_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	dm_free(TO_DCE112_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+void dce112_destruct_resource_pool(struct resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce112_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce112_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce112_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL) {
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL) {
-+			dce112_clock_source_destroy(&pool->clock_sources[i]);
-+		}
-+	}
-+
-+	if (pool->dp_clock_source != NULL)
-+		dce112_clock_source_destroy(&pool->dp_clock_source);
-+
-+	for (i = 0; i < pool->audio_count; i++)	{
-+		if (pool->audios[i] != NULL) {
-+			dal_audio_destroy(&pool->audios[i]);
-+		}
-+	}
-+
-+	if (pool->display_clock != NULL) {
-+		dal_display_clock_destroy(&pool->display_clock);
-+	}
-+
-+	if (pool->scaler_filter != NULL) {
-+		dal_scaler_filter_destroy(&pool->scaler_filter);
-+	}
-+	if (pool->irqs != NULL) {
-+		dal_irq_service_destroy(&pool->irqs);
-+	}
-+
-+	if (pool->adapter_srv != NULL) {
-+		dal_adapter_service_destroy(&pool->adapter_srv);
-+	}
-+}
-+
-+static struct clock_source *find_matching_pll(struct resource_context *res_ctx,
-+		const struct core_stream *const stream)
-+{
-+	switch (stream->sink->link->link_enc->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+		return res_ctx->pool.clock_sources[DCE112_CLK_SRC_PLL0];
-+	case TRANSMITTER_UNIPHY_B:
-+		return res_ctx->pool.clock_sources[DCE112_CLK_SRC_PLL1];
-+	case TRANSMITTER_UNIPHY_C:
-+		return res_ctx->pool.clock_sources[DCE112_CLK_SRC_PLL2];
-+	case TRANSMITTER_UNIPHY_D:
-+		return res_ctx->pool.clock_sources[DCE112_CLK_SRC_PLL3];
-+	case TRANSMITTER_UNIPHY_E:
-+		return res_ctx->pool.clock_sources[DCE112_CLK_SRC_PLL4];
-+	case TRANSMITTER_UNIPHY_F:
-+		return res_ctx->pool.clock_sources[DCE112_CLK_SRC_PLL5];
-+	default:
-+		return NULL;
-+	};
-+
-+	return 0;
-+}
-+
-+static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-+{
-+	switch (crtc_id) {
-+	case CONTROLLER_ID_D0:
-+		return DTO_SOURCE_ID0;
-+	case CONTROLLER_ID_D1:
-+		return DTO_SOURCE_ID1;
-+	case CONTROLLER_ID_D2:
-+		return DTO_SOURCE_ID2;
-+	case CONTROLLER_ID_D3:
-+		return DTO_SOURCE_ID3;
-+	case CONTROLLER_ID_D4:
-+		return DTO_SOURCE_ID4;
-+	case CONTROLLER_ID_D5:
-+		return DTO_SOURCE_ID5;
-+	default:
-+		return DTO_SOURCE_UNKNOWN;
-+	}
-+}
-+
-+static void build_audio_output(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct audio_output *audio_output)
-+{
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	audio_output->engine_id = pipe_ctx->stream_enc->id;
-+
-+	audio_output->signal = pipe_ctx->signal;
-+
-+	/* audio_crtc_info  */
-+
-+	audio_output->crtc_info.h_total =
-+		stream->public.timing.h_total;
-+
-+	/* Audio packets are sent during actual CRTC blank physical signal, we
-+	 * need to specify actual active signal portion */
-+	audio_output->crtc_info.h_active =
-+			stream->public.timing.h_addressable
-+			+ stream->public.timing.h_border_left
-+			+ stream->public.timing.h_border_right;
-+
-+	audio_output->crtc_info.v_active =
-+			stream->public.timing.v_addressable
-+			+ stream->public.timing.v_border_top
-+			+ stream->public.timing.v_border_bottom;
-+
-+	audio_output->crtc_info.pixel_repetition = 1;
-+
-+	audio_output->crtc_info.interlaced =
-+			stream->public.timing.flags.INTERLACE;
-+
-+	audio_output->crtc_info.refresh_rate =
-+		(stream->public.timing.pix_clk_khz*1000)/
-+		(stream->public.timing.h_total*stream->public.timing.v_total);
-+
-+	audio_output->crtc_info.color_depth =
-+		stream->public.timing.display_color_depth;
-+
-+	audio_output->crtc_info.requested_pixel_clock =
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
-+
-+	/* TODO - Investigate why calculated pixel clk has to be
-+	 * requested pixel clk */
-+	audio_output->crtc_info.calculated_pixel_clock =
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
-+
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		audio_output->pll_info.dp_dto_source_clock_in_khz =
-+			dal_display_clock_get_dp_ref_clk_frequency(
-+				pipe_ctx->dis_clk);
-+	}
-+
-+	audio_output->pll_info.feed_back_divider =
-+			pipe_ctx->pll_settings.feedback_divider;
-+
-+	audio_output->pll_info.dto_source =
-+		translate_to_dto_source(
-+			pipe_ctx->pipe_idx + 1);
-+
-+	/* TODO hard code to enable for now. Need get from stream */
-+	audio_output->pll_info.ss_enabled = true;
-+
-+	audio_output->pll_info.ss_percentage =
-+			pipe_ctx->pll_settings.ss_percentage;
-+}
-+
-+static void get_pixel_clock_parameters(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct pixel_clk_params *pixel_clk_params)
-+{
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
-+	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
-+	pixel_clk_params->signal_type = stream->sink->public.sink_signal;
-+	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
-+	/* TODO: un-hardcode*/
-+	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+	pixel_clk_params->flags.ENABLE_SS = 0;
-+	pixel_clk_params->color_depth =
-+		stream->public.timing.display_color_depth;
-+	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-+}
-+
-+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
-+{
-+	/*TODO: unhardcode*/
-+	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
-+	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
-+	pipe_ctx->max_hdmi_pixel_clock = 600000;
-+
-+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
-+	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-+		pipe_ctx->clock_source,
-+		&pipe_ctx->pix_clk_params,
-+		&pipe_ctx->pll_settings);
-+
-+	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
-+
-+	return DC_OK;
-+}
-+
-+static enum dc_status validate_mapped_resource(
-+		const struct core_dc *dc,
-+		struct validate_context *context)
-+{
-+	enum dc_status status = DC_OK;
-+	uint8_t i, j, k;
-+
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+			struct core_link *link = stream->sink->link;
-+
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (!pipe_ctx->tg->funcs->validate_timing(
-+						pipe_ctx->tg, &stream->public.timing))
-+					return DC_FAIL_CONTROLLER_VALIDATE;
-+
-+				status = build_pipe_hw_param(pipe_ctx);
-+
-+				if (status != DC_OK)
-+					return status;
-+
-+				if (!link->link_enc->funcs->validate_output_with_stream(
-+						link->link_enc,
-+						pipe_ctx))
-+					return DC_FAIL_ENC_VALIDATE;
-+
-+				/* TODO: validate audio ASIC caps, encoder */
-+
-+				status = dc_link_validate_mode_timing(stream->sink,
-+						link,
-+						&stream->public.timing);
-+
-+				if (status != DC_OK)
-+					return status;
-+
-+				resource_build_info_frame(pipe_ctx);
-+
-+				/* do not need to validate non root pipes */
-+				break;
-+			}
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce112_validate_bandwidth(
-+	const struct core_dc *dc,
-+	struct validate_context *context)
-+{
-+	uint8_t i;
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t number_of_displays = 0;
-+	uint8_t max_htaps = 1;
-+	uint8_t max_vtaps = 1;
-+	bool all_displays_in_sync = true;
-+	struct dc_crtc_timing prev_timing;
-+
-+	memset(&context->bw_mode_data, 0, sizeof(context->bw_mode_data));
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct bw_calcs_input_single_display *disp = &context->
-+			bw_mode_data.displays_data[number_of_displays];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->scl_data.ratios.vert.value == 0) {
-+			disp->graphics_scale_ratio = bw_int_to_fixed(1);
-+			disp->graphics_h_taps = 2;
-+			disp->graphics_v_taps = 2;
-+
-+			/* TODO: remove when bw formula accepts taps per
-+			 * display
-+			 */
-+			if (max_vtaps < 2)
-+				max_vtaps = 2;
-+			if (max_htaps < 2)
-+				max_htaps = 2;
-+
-+		} else {
-+			disp->graphics_scale_ratio =
-+				fixed31_32_to_bw_fixed(
-+					pipe_ctx->scl_data.ratios.vert.value);
-+			disp->graphics_h_taps = pipe_ctx->scl_data.taps.h_taps;
-+			disp->graphics_v_taps = pipe_ctx->scl_data.taps.v_taps;
-+
-+			/* TODO: remove when bw formula accepts taps per
-+			 * display
-+			 */
-+			if (max_vtaps < pipe_ctx->scl_data.taps.v_taps)
-+				max_vtaps = pipe_ctx->scl_data.taps.v_taps;
-+			if (max_htaps < pipe_ctx->scl_data.taps.h_taps)
-+				max_htaps = pipe_ctx->scl_data.taps.h_taps;
-+		}
-+
-+		disp->graphics_src_width =
-+			pipe_ctx->stream->public.timing.h_addressable;
-+		disp->graphics_src_height =
-+			pipe_ctx->stream->public.timing.v_addressable;
-+		disp->h_total = pipe_ctx->stream->public.timing.h_total;
-+		disp->pixel_rate = bw_frc_to_fixed(
-+			pipe_ctx->stream->public.timing.pix_clk_khz, 1000);
-+
-+		/*TODO: get from surface*/
-+		disp->graphics_bytes_per_pixel = 4;
-+		disp->graphics_tiling_mode = bw_def_tiled;
-+
-+		/* DCE11 defaults*/
-+		disp->graphics_lb_bpc = 10;
-+		disp->graphics_interlace_mode = false;
-+		disp->fbc_enable = false;
-+		disp->lpt_enable = false;
-+		disp->graphics_stereo_mode = bw_def_mono;
-+		disp->underlay_mode = bw_def_none;
-+
-+		/*All displays will be synchronized if timings are all
-+		 * the same
-+		 */
-+		if (number_of_displays != 0 && all_displays_in_sync)
-+			if (memcmp(&prev_timing,
-+				&pipe_ctx->stream->public.timing,
-+				sizeof(struct dc_crtc_timing)) != 0)
-+				all_displays_in_sync = false;
-+		if (number_of_displays == 0)
-+			prev_timing = pipe_ctx->stream->public.timing;
-+
-+		number_of_displays++;
-+	}
-+
-+	/* TODO: remove when bw formula accepts taps per
-+	 * display
-+	 */
-+	context->bw_mode_data.displays_data[0].graphics_v_taps = max_vtaps;
-+	context->bw_mode_data.displays_data[0].graphics_h_taps = max_htaps;
-+
-+	context->bw_mode_data.number_of_displays = number_of_displays;
-+	context->bw_mode_data.display_synchronization_enabled =
-+							all_displays_in_sync;
-+
-+	dal_logger_write(
-+		dc->ctx->logger,
-+		LOG_MAJOR_BWM,
-+		LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-+		"%s: start",
-+		__func__);
-+
-+	if (!bw_calcs(
-+			dc->ctx,
-+			&dc->bw_dceip,
-+			&dc->bw_vbios,
-+			&context->bw_mode_data,
-+			&context->bw_results))
-+		result =  DC_FAIL_BANDWIDTH_VALIDATE;
-+	else
-+		result =  DC_OK;
-+
-+	if (result == DC_FAIL_BANDWIDTH_VALIDATE)
-+		dal_logger_write(dc->ctx->logger,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_MODE_VALIDATION,
-+			"%s: Bandwidth validation failed!",
-+			__func__);
-+
-+	if (memcmp(&dc->current_context.bw_results,
-+			&context->bw_results, sizeof(context->bw_results))) {
-+		struct log_entry log_entry;
-+		dal_logger_open(
-+			dc->ctx->logger,
-+			&log_entry,
-+			LOG_MAJOR_BWM,
-+			LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
-+		dal_logger_append(&log_entry, "%s: finish, numDisplays: %d\n"
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			__func__, number_of_displays,
-+			context->bw_results.nbp_state_change_wm_ns[0].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[0].a_mark,
-+			context->bw_results.urgent_wm_ns[0].b_mark,
-+			context->bw_results.urgent_wm_ns[0].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[0].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[1].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[1].a_mark,
-+			context->bw_results.urgent_wm_ns[1].b_mark,
-+			context->bw_results.urgent_wm_ns[1].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[1].a_mark);
-+		dal_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
-+			context->bw_results.nbp_state_change_wm_ns[2].b_mark,
-+			context->bw_results.nbp_state_change_wm_ns[2].a_mark,
-+			context->bw_results.urgent_wm_ns[2].b_mark,
-+			context->bw_results.urgent_wm_ns[2].a_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].b_mark,
-+			context->bw_results.stutter_exit_wm_ns[2].a_mark,
-+			context->bw_results.stutter_mode_enable);
-+		dal_logger_append(&log_entry,
-+			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
-+			"sclk: %d sclk_sleep: %d yclk: %d blackout_duration: %d\n",
-+			context->bw_results.cpuc_state_change_enable,
-+			context->bw_results.cpup_state_change_enable,
-+			context->bw_results.nbp_state_change_enable,
-+			context->bw_results.all_displays_in_sync,
-+			context->bw_results.dispclk_khz,
-+			context->bw_results.required_sclk,
-+			context->bw_results.required_sclk_deep_sleep,
-+			context->bw_results.required_yclk,
-+			context->bw_results.required_blackout_duration_us);
-+		dal_logger_close(&log_entry);
-+	}
-+	return result;
-+}
-+
-+static void set_target_unchanged(
-+		struct validate_context *context,
-+		uint8_t target_idx)
-+{
-+	uint8_t i, j;
-+	struct core_target *target = context->targets[target_idx];
-+	context->target_flags[target_idx].unchanged = true;
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		struct core_stream *stream =
-+			DC_STREAM_TO_CORE(target->public.streams[i]);
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (context->res_ctx.pipe_ctx[j].stream == stream)
-+				context->res_ctx.pipe_ctx[j].flags.unchanged =
-+									true;
-+		}
-+	}
-+}
-+
-+static enum dc_status map_clock_resources(
-+		const struct core_dc *dc,
-+		struct validate_context *context)
-+{
-+	uint8_t i, j, k;
-+
-+	/* acquire new resources */
-+	for (i = 0; i < context->target_count; i++) {
-+		struct core_target *target = context->targets[i];
-+
-+		if (context->target_flags[i].unchanged)
-+			continue;
-+
-+		for (j = 0; j < target->public.stream_count; j++) {
-+			struct core_stream *stream =
-+				DC_STREAM_TO_CORE(target->public.streams[j]);
-+
-+			for (k = 0; k < MAX_PIPES; k++) {
-+				struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[k];
-+
-+				if (context->res_ctx.pipe_ctx[k].stream != stream)
-+					continue;
-+
-+				if (dc_is_dp_signal(pipe_ctx->signal)
-+					|| pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
-+					pipe_ctx->clock_source =
-+						context->res_ctx.pool.dp_clock_source;
-+				else
-+					pipe_ctx->clock_source =
-+							find_matching_pll(&context->res_ctx,
-+									stream);
-+
-+				if (pipe_ctx->clock_source == NULL)
-+					return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+				resource_reference_clock_source(
-+						&context->res_ctx,
-+						pipe_ctx->clock_source);
-+
-+				/* only one cs per stream regardless of mpo */
-+				break;
-+			}
-+		}
-+	}
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce112_validate_with_context(
-+		const struct core_dc *dc,
-+		const struct dc_validation_set set[],
-+		uint8_t set_count,
-+		struct validate_context *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	uint8_t i, j;
-+	struct dc_context *dc_ctx = dc->ctx;
-+
-+	for (i = 0; i < set_count; i++) {
-+		bool unchanged = false;
-+
-+		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
-+		dc_target_retain(&context->targets[i]->public);
-+		context->target_count++;
-+
-+		for (j = 0; j < dc->current_context.target_count; j++)
-+			if (dc->current_context.targets[j]
-+						== context->targets[i]) {
-+				unchanged = true;
-+				set_target_unchanged(context, i);
-+				resource_attach_surfaces_to_context(
-+					(struct dc_surface **)dc->current_context.
-+						target_status[j].surfaces,
-+					dc->current_context.target_status[j].surface_count,
-+					&context->targets[i]->public,
-+					context);
-+				context->target_status[i] =
-+					dc->current_context.target_status[j];
-+			}
-+		if (!unchanged || set[i].surface_count != 0)
-+			if (!resource_attach_surfaces_to_context(
-+					(struct dc_surface **)set[i].surfaces,
-+					set[i].surface_count,
-+					&context->targets[i]->public,
-+					context)) {
-+				DC_ERROR("Failed to attach surface to target!\n");
-+				return DC_FAIL_ATTACH_SURFACES;
-+			}
-+	}
-+
-+	context->res_ctx.pool = dc->res_pool;
-+
-+	result = resource_map_pool_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = map_clock_resources(dc, context);
-+
-+	if (result == DC_OK)
-+		result = validate_mapped_resource(dc, context);
-+
-+	if (result == DC_OK)
-+		resource_build_scaling_params_for_context(dc, context);
-+
-+	if (result == DC_OK)
-+		result = dce112_validate_bandwidth(dc, context);
-+
-+	return result;
-+}
-+
-+static struct resource_funcs dce112_res_pool_funcs = {
-+	.destruct = dce112_destruct_resource_pool,
-+	.link_enc_create = dce112_link_encoder_create,
-+	.validate_with_context = dce112_validate_with_context,
-+	.validate_bandwidth = dce112_validate_bandwidth
-+};
-+
-+static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
-+{
-+	struct dm_pp_clock_levels clks = {0};
-+
-+	/*do system clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_ENGINE_CLK,
-+			&clks);
-+	/* convert all the clock fro kHz to fix point mHz */
-+	dc->bw_vbios.high_sclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.mid_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do display clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_DISPLAY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios.mid_voltage_max_dispclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios.low_voltage_max_dispclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do memory clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios.low_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
-+	dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+	dc->bw_vbios.high_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+}
-+
-+
-+bool dce112_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
-+	struct core_dc *dc,
-+	struct resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct audio_init_data audio_init_data = { 0 };
-+	struct dc_context *ctx = dc->ctx;
-+
-+	pool->adapter_srv = adapter_serv;
-+	pool->funcs = &dce112_res_pool_funcs;
-+
-+	pool->stream_engines.engine.ENGINE_ID_DIGA = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGB = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGC = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGD = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGE = 1;
-+	pool->stream_engines.engine.ENGINE_ID_DIGF = 1;
-+
-+	pool->clock_sources[DCE112_CLK_SRC_PLL0] = dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_COMBO_PHY_PLL0, &dce112_clk_src_reg_offsets[0]);
-+	pool->clock_sources[DCE112_CLK_SRC_PLL1] = dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_COMBO_PHY_PLL1, &dce112_clk_src_reg_offsets[1]);
-+	pool->clock_sources[DCE112_CLK_SRC_PLL2] = dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_COMBO_PHY_PLL2, &dce112_clk_src_reg_offsets[2]);
-+	pool->clock_sources[DCE112_CLK_SRC_PLL3] = dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_COMBO_PHY_PLL3, &dce112_clk_src_reg_offsets[3]);
-+	pool->clock_sources[DCE112_CLK_SRC_PLL4] = dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_COMBO_PHY_PLL4, &dce112_clk_src_reg_offsets[4]);
-+	pool->clock_sources[DCE112_CLK_SRC_PLL5] = dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_COMBO_PHY_PLL5, &dce112_clk_src_reg_offsets[5]);
-+	pool->clk_src_count = DCE112_CLK_SRC_TOTAL;
-+
-+	pool->dp_clock_source =  dce112_clock_source_create(
-+		ctx, dal_adapter_service_get_bios_parser(adapter_serv),
-+		CLOCK_SOURCE_ID_DP_DTO, &dce112_clk_src_reg_offsets[0]);
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->display_clock = dal_display_clock_dce112_create(ctx, adapter_serv);
-+	if (pool->display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->irqs = dal_irq_service_create(
-+				dal_adapter_service_get_dce_version(
-+					dc->res_pool.adapter_srv),
-+				&init_data);
-+		if (!pool->irqs)
-+			goto irqs_create_fail;
-+
-+	}
-+
-+	pool->pipe_count =
-+		dal_adapter_service_get_func_controllers_num(adapter_serv);
-+	pool->stream_enc_count = 6;
-+	pool->scaler_filter = dal_scaler_filter_create(ctx);
-+	if (pool->scaler_filter == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dm_error("DC: failed to create filter!\n");
-+		goto filter_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		pool->timing_generators[i] = dce112_timing_generator_create(
-+				adapter_serv,
-+				ctx,
-+				i,
-+				&dce112_tg_offsets[i]);
-+		if (pool->timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->mis[i] = dce112_mem_input_create(
-+			ctx,
-+			i,
-+			&dce112_mi_reg_offsets[i]);
-+		if (pool->mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->ipps[i] = dce112_ipp_create(
-+			ctx,
-+			i,
-+			&ipp_reg_offsets[i]);
-+		if (pool->ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->transforms[i] = dce112_transform_create(
-+				ctx,
-+				i,
-+				&dce112_xfm_offsets[i]);
-+		if (pool->transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create transform!\n");
-+			goto controller_create_fail;
-+		}
-+		pool->transforms[i]->funcs->transform_set_scaler_filter(
-+				pool->transforms[i],
-+				pool->scaler_filter);
-+
-+		pool->opps[i] = dce112_opp_create(
-+			ctx,
-+			i,
-+			&dce112_opp_reg_offsets[i]);
-+		if (pool->opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+	}
-+
-+	audio_init_data.as = adapter_serv;
-+	audio_init_data.ctx = ctx;
-+	pool->audio_count = 0;
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		struct graphics_object_id obj_id;
-+
-+		obj_id = dal_adapter_service_enum_audio_object(adapter_serv, i);
-+		if (false == dal_graphics_object_id_is_valid(obj_id)) {
-+			/* no more valid audio objects */
-+			break;
-+		}
-+
-+		audio_init_data.audio_stream_id = obj_id;
-+		pool->audios[i] = dal_audio_create(&audio_init_data);
-+		if (pool->audios[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create DPPs!\n");
-+			goto audio_create_fail;
-+		}
-+		pool->audio_count++;
-+	}
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		/* TODO: rework fragile code*/
-+		if (pool->stream_engines.u_all & 1 << i) {
-+			pool->stream_enc[i] = dce112_stream_encoder_create(
-+				i, dc->ctx,
-+				dal_adapter_service_get_bios_parser(
-+					adapter_serv),
-+				&stream_enc_regs[i]);
-+			if (pool->stream_enc[i] == NULL) {
-+				BREAK_TO_DEBUGGER();
-+				dm_error("DC: failed to create stream_encoder!\n");
-+				goto stream_enc_create_fail;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < num_virtual_links; i++) {
-+		pool->stream_enc[pool->stream_enc_count] =
-+			virtual_stream_encoder_create(
-+				dc->ctx, dal_adapter_service_get_bios_parser(
-+								adapter_serv));
-+		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create stream_encoder!\n");
-+			goto stream_enc_create_fail;
-+		}
-+		pool->stream_enc_count++;
-+	}
-+
-+	/* Create hardware sequencer */
-+	if (!dc_construct_hw_sequencer(adapter_serv, dc))
-+		goto stream_enc_create_fail;
-+
-+	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_BAFFIN);
-+
-+	bw_calcs_data_update_from_pplib(dc);
-+
-+	return true;
-+
-+stream_enc_create_fail:
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] != NULL)
-+			dm_free(DCE110STRENC_FROM_STRENC(pool->stream_enc[i]));
-+	}
-+
-+audio_create_fail:
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (pool->audios[i] != NULL)
-+			dal_audio_destroy(&pool->audios[i]);
-+	}
-+
-+controller_create_fail:
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (pool->opps[i] != NULL)
-+			dce112_opp_destroy(&pool->opps[i]);
-+
-+		if (pool->transforms[i] != NULL)
-+			dce112_transform_destroy(&pool->transforms[i]);
-+
-+		if (pool->ipps[i] != NULL)
-+			dce112_ipp_destroy(&pool->ipps[i]);
-+
-+		if (pool->mis[i] != NULL) {
-+			dm_free(TO_DCE110_MEM_INPUT(pool->mis[i]));
-+			pool->mis[i] = NULL;
-+		}
-+
-+		if (pool->timing_generators[i] != NULL) {
-+			dm_free(DCE110TG_FROM_TG(pool->timing_generators[i]));
-+			pool->timing_generators[i] = NULL;
-+		}
-+	}
-+
-+filter_create_fail:
-+	dal_irq_service_destroy(&pool->irqs);
-+
-+irqs_create_fail:
-+	dal_display_clock_destroy(&pool->display_clock);
-+
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != NULL)
-+			dce112_clock_source_destroy(&pool->clock_sources[i]);
-+	}
-+
-+	return false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
-new file mode 100644
-index 0000000..eed1faf
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
-@@ -0,0 +1,42 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE112_H__
-+#define __DC_RESOURCE_DCE112_H__
-+
-+#include "core_types.h"
-+
-+struct adapter_service;
-+struct core_dc;
-+struct resource_pool;
-+
-+bool dce112_construct_resource_pool(
-+	struct adapter_service *adapter_serv,
-+	uint8_t num_virtual_links,
-+	struct core_dc *dc,
-+	struct resource_pool *pool);
-+
-+#endif /* __DC_RESOURCE_DCE112_H__ */
-+
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index 1e87624..982e968 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -212,6 +212,11 @@ enum dm_pp_clock_type {
- struct dm_pp_clock_levels {
- 	uint32_t num_levels;
- 	uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
-+
-+	/* TODO: add latency for polaris11
-+	 * do we need to know invalid (unsustainable boost) level for watermark
-+	 * programming? if not we can just report less elements in array
-+	 */
- };
- 
- struct dm_pp_single_disp_config {
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-index 63d6b54..5037a2d 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c
-@@ -78,6 +78,9 @@ bool dal_hw_factory_init(
- #endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+#endif
- 		dal_hw_factory_dce110_init(factory);
- 		return true;
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-index d3c6bc8..da56db7 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c
-@@ -75,6 +75,9 @@ bool dal_hw_translate_init(
- 	case DCE_VERSION_10_0:
- #endif
- 	case DCE_VERSION_11_0:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+#endif
- 		dal_hw_translate_dce110_init(translate);
- 		return true;
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-index cb23508..3095006 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
-@@ -32,3 +32,11 @@ AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
- 
- AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110)
- endif
-+
-+ifdef CONFIG_DRM_AMD_DAL_DCE11_2
-+GPU_DCE112 = display_clock_dce112.o dc_clock_gating_dce112.o
-+
-+AMD_DAL_GPU_DCE112 = $(addprefix $(AMDDALPATH)/dc/gpu/dce112/,$(GPU_DCE112))
-+
-+AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110) $(AMD_DAL_GPU_DCE112)
-+endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
-new file mode 100644
-index 0000000..bf24457
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
-@@ -0,0 +1,89 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+#include "dc_clock_gating_dce112.h"
-+
-+/******************************************************************************
-+ * Macro definitions
-+ *****************************************************************************/
-+
-+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_GPU, \
-+		"%s:%s()\n", __FILE__, __func__)
-+
-+/******************************************************************************
-+ * static functions
-+ *****************************************************************************/
-+static void force_hw_base_light_sleep(struct dc_context *ctx)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
-+	/* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
-+	 * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+			value,
-+			1,
-+			DC_MEM_GLOBAL_PWR_REQ_CNTL,
-+			DC_MEM_GLOBAL_PWR_REQ_DIS);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+}
-+
-+static void enable_hw_base_light_sleep(struct dc_context *ctx)
-+{
-+	NOT_IMPLEMENTED();
-+}
-+
-+static void disable_sw_manual_control_light_sleep(
-+		struct dc_context *ctx)
-+{
-+	NOT_IMPLEMENTED();
-+}
-+
-+/******************************************************************************
-+ * public functions
-+ *****************************************************************************/
-+
-+void dal_dc_clock_gating_dce112_power_up(
-+		struct dc_context *ctx,
-+		bool enable)
-+{
-+	if (enable) {
-+		enable_hw_base_light_sleep(ctx);
-+		disable_sw_manual_control_light_sleep(ctx);
-+	} else {
-+		force_hw_base_light_sleep(ctx);
-+	}
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
-new file mode 100644
-index 0000000..118da64
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DC_CLOCK_GATING_DCE112_H__
-+#define __DAL_DC_CLOCK_GATING_DCE112_H__
-+
-+void dal_dc_clock_gating_dce112_power_up(
-+		struct dc_context *ctx,
-+		bool enable);
-+
-+#endif /* __DAL_DC_CLOCK_GATING_DCE110_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-new file mode 100644
-index 0000000..e559f95
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-@@ -0,0 +1,964 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+#include "include/adapter_service_interface.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/fixed32_32.h"
-+#include "include/logger_interface.h"
-+
-+#include "../divider_range.h"
-+
-+#include "display_clock_dce112.h"
-+
-+#define FROM_DISPLAY_CLOCK(base) \
-+	container_of(base, struct display_clock_dce112, disp_clk_base)
-+
-+static struct state_dependent_clocks max_clks_by_state[] = {
-+/*ClocksStateInvalid - should not be used*/
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-+/*ClocksStateLow*/
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-+/*ClocksStateNominal*/
-+{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
-+/*ClocksStatePerformance*/
-+{ .display_clk_khz = 643000, .pixel_clk_khz = 4000000 } };
-+
-+/* Starting point for each divider range.*/
-+enum divider_range_start {
-+	DIVIDER_RANGE_01_START = 200, /* 2.00*/
-+	DIVIDER_RANGE_02_START = 1600, /* 16.00*/
-+	DIVIDER_RANGE_03_START = 3200, /* 32.00*/
-+	DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
-+};
-+
-+/* Array identifiers and count for the divider ranges.*/
-+enum divider_range_count {
-+	DIVIDER_RANGE_01 = 0,
-+	DIVIDER_RANGE_02,
-+	DIVIDER_RANGE_03,
-+	DIVIDER_RANGE_MAX /* == 3*/
-+};
-+
-+/* Ranges for divider identifiers (Divider ID or DID)
-+ mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
-+enum divider_id_register_setting {
-+	DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
-+	DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
-+	DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
-+	DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
-+};
-+
-+/* Step size between each divider within a range.
-+ Incrementing the DENTIST_DISPCLK_WDIVIDER by one
-+ will increment the divider by this much.*/
-+enum divider_range_step_size {
-+	DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
-+	DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
-+	DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
-+};
-+
-+static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
-+
-+#define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000
-+/*****************************************************************************
-+ * static functions
-+ *****************************************************************************/
-+
-+/*
-+ * store_max_clocks_state
-+ *
-+ * @brief
-+ * Cache the clock state
-+ *
-+ * @param
-+ * struct display_clock *base - [out] cach the state in this structure
-+ * enum clocks_state max_clocks_state - [in] state to be stored
-+ */
-+static void store_max_clocks_state(
-+	struct display_clock *base,
-+	enum clocks_state max_clocks_state)
-+{
-+	struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-+
-+	switch (max_clocks_state) {
-+	case CLOCKS_STATE_LOW:
-+	case CLOCKS_STATE_NOMINAL:
-+	case CLOCKS_STATE_PERFORMANCE:
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		dc->max_clks_state = max_clocks_state;
-+		break;
-+
-+	case CLOCKS_STATE_INVALID:
-+	default:
-+		/*Invalid Clocks State!*/
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+}
-+
-+static enum clocks_state get_min_clocks_state(struct display_clock *base)
-+{
-+	return base->cur_min_clks_state;
-+}
-+
-+static bool set_min_clocks_state(
-+	struct display_clock *base,
-+	enum clocks_state clocks_state)
-+{
-+	struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-+
-+	if (clocks_state > dc->max_clks_state) {
-+		/*Requested state exceeds max supported state.*/
-+		dal_logger_write(base->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Requested state exceeds max supported state");
-+		return false;
-+	} else if (clocks_state == base->cur_min_clks_state) {
-+		/*if we're trying to set the same state, we can just return
-+		 * since nothing needs to be done*/
-+		return true;
-+	}
-+
-+	base->cur_min_clks_state = clocks_state;
-+
-+	return true;
-+}
-+
-+static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
-+{
-+	uint32_t dispclk_cntl_value;
-+	uint32_t dp_ref_clk_cntl_value;
-+	uint32_t dp_ref_clk_cntl_src_sel_value;
-+	uint32_t dp_ref_clk_khz = 600000;
-+	uint32_t target_div = INVALID_DIVIDER;
-+	struct display_clock_dce112 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-+
-+	/* ASSERT DP Reference Clock source is from DFS*/
-+	dp_ref_clk_cntl_value = dm_read_reg(dc->ctx,
-+			mmDPREFCLK_CNTL);
-+
-+	dp_ref_clk_cntl_src_sel_value =
-+			get_reg_field_value(
-+				dp_ref_clk_cntl_value,
-+				DPREFCLK_CNTL, DPREFCLK_SRC_SEL);
-+
-+	ASSERT(dp_ref_clk_cntl_src_sel_value == 0);
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
-+	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
-+	dispclk_cntl_value = dm_read_reg(dc->ctx,
-+			mmDENTIST_DISPCLK_CNTL);
-+
-+	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
-+	target_div = dal_divider_range_get_divider(
-+		divider_ranges,
-+		DIVIDER_RANGE_MAX,
-+		get_reg_field_value(dispclk_cntl_value,
-+			DENTIST_DISPCLK_CNTL,
-+			DENTIST_DPREFCLK_WDIVIDER));
-+
-+	if (target_div != INVALID_DIVIDER) {
-+		/* Calculate the current DFS clock, in kHz.*/
-+		dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
-+			* disp_clk->dentist_vco_freq_khz) / target_div;
-+	}
-+
-+	/* SW will adjust DP REF Clock average value for all purposes
-+	 * (DP DTO / DP Audio DTO and DP GTC)
-+	 if clock is spread for all cases:
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
-+	 calculations for DS_INCR/DS_MODULO (this is planned to be default case)
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
-+	 calculations (not planned to be used, but average clock should still
-+	 be valid)
-+	 -if SS enabled on DP Ref clock and HW de-spreading disabled
-+	 (should not be case with CIK) then SW should program all rates
-+	 generated according to average value (case as with previous ASICs)
-+	  */
-+	if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) {
-+		struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+					disp_clk->gpu_pll_ss_percentage,
-+					disp_clk->gpu_pll_ss_divider), 200);
-+		struct fixed32_32 adj_dp_ref_clk_khz;
-+
-+		ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
-+								ss_percentage);
-+		adj_dp_ref_clk_khz =
-+			dal_fixed32_32_mul_int(
-+				ss_percentage,
-+				dp_ref_clk_khz);
-+		dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
-+	}
-+
-+	return dp_ref_clk_khz;
-+}
-+
-+static void destroy(struct display_clock **base)
-+{
-+	struct display_clock_dce112 *dc112;
-+
-+	dc112 = DCLCK112_FROM_BASE(*base);
-+
-+	dm_free(dc112);
-+
-+	*base = NULL;
-+}
-+
-+static uint32_t get_validation_clock(struct display_clock *dc)
-+{
-+	uint32_t clk = 0;
-+	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-+
-+	switch (disp_clk->max_clks_state) {
-+	case CLOCKS_STATE_ULTRA_LOW:
-+		/*Currently not supported, it has 0 in table entry*/
-+	case CLOCKS_STATE_LOW:
-+		clk = max_clks_by_state[CLOCKS_STATE_LOW].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_NOMINAL:
-+		clk = max_clks_by_state[CLOCKS_STATE_NOMINAL].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_PERFORMANCE:
-+		clk = max_clks_by_state[CLOCKS_STATE_PERFORMANCE].
-+						display_clk_khz;
-+		break;
-+
-+	case CLOCKS_STATE_INVALID:
-+	default:
-+		/*Invalid Clocks State*/
-+		dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Invalid clock state");
-+		/* just return the display engine clock for
-+		 * lowest supported state*/
-+		clk = max_clks_by_state[CLOCKS_STATE_LOW].
-+						display_clk_khz;
-+		break;
-+	}
-+	return clk;
-+}
-+
-+static struct fixed32_32 get_deep_color_factor(struct min_clock_params *params)
-+{
-+	/* DeepColorFactor = IF (HDMI = True, bpp / 24, 1)*/
-+	struct fixed32_32 deep_color_factor = dal_fixed32_32_from_int(1);
-+
-+	if (params->signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return deep_color_factor;
-+
-+	switch (params->deep_color_depth) {
-+	case COLOR_DEPTH_101010:
-+		/*deep color ratio for 30bpp is 30/24 = 1.25*/
-+		deep_color_factor = dal_fixed32_32_from_fraction(30, 24);
-+		break;
-+
-+	case COLOR_DEPTH_121212:
-+		/* deep color ratio for 36bpp is 36/24 = 1.5*/
-+		deep_color_factor = dal_fixed32_32_from_fraction(36, 24);
-+		break;
-+
-+	case COLOR_DEPTH_161616:
-+		/* deep color ratio for 48bpp is 48/24 = 2.0 */
-+		deep_color_factor = dal_fixed32_32_from_fraction(48, 24);
-+		break;
-+	default:
-+		break;
-+	}
-+	return deep_color_factor;
-+}
-+
-+static struct fixed32_32 get_scaler_efficiency(
-+	struct dc_context *ctx,
-+	struct min_clock_params *params)
-+{
-+	struct fixed32_32 scaler_efficiency = dal_fixed32_32_from_int(3);
-+
-+	if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB18BPP) {
-+		scaler_efficiency =
-+			dal_fixed32_32_add(
-+				dal_fixed32_32_from_fraction(35555, 10000),
-+				dal_fixed32_32_from_fraction(
-+					55556,
-+					100000 * 10000));
-+	} else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB24BPP) {
-+		scaler_efficiency =
-+			dal_fixed32_32_add(
-+				dal_fixed32_32_from_fraction(34285, 10000),
-+				dal_fixed32_32_from_fraction(
-+					71429,
-+					100000 * 10000));
-+	} else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB30BPP)
-+		scaler_efficiency = dal_fixed32_32_from_fraction(32, 10);
-+
-+	return scaler_efficiency;
-+}
-+
-+static struct fixed32_32 get_lb_lines_in_per_line_out(
-+		struct min_clock_params *params,
-+		struct fixed32_32 v_scale_ratio)
-+{
-+	struct fixed32_32 two = dal_fixed32_32_from_int(2);
-+	struct fixed32_32 four = dal_fixed32_32_from_int(4);
-+	struct fixed32_32 f4_to_3 = dal_fixed32_32_from_fraction(4, 3);
-+	struct fixed32_32 f6_to_4 = dal_fixed32_32_from_fraction(6, 4);
-+
-+	if (params->line_buffer_prefetch_enabled)
-+		return dal_fixed32_32_max(v_scale_ratio, dal_fixed32_32_one);
-+	else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_one))
-+		return dal_fixed32_32_one;
-+	else if (dal_fixed32_32_le(v_scale_ratio, f4_to_3))
-+		return f4_to_3;
-+	else if (dal_fixed32_32_le(v_scale_ratio, f6_to_4))
-+		return f6_to_4;
-+	else if (dal_fixed32_32_le(v_scale_ratio, two))
-+		return two;
-+	else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_from_int(3)))
-+		return four;
-+	else
-+		return dal_fixed32_32_zero;
-+}
-+
-+static uint32_t get_actual_required_display_clk(
-+	struct display_clock_dce112 *disp_clk,
-+	uint32_t target_clk_khz)
-+{
-+	uint32_t disp_clk_khz = target_clk_khz;
-+	uint32_t div = INVALID_DIVIDER;
-+	uint32_t did = INVALID_DID;
-+	uint32_t scaled_vco =
-+		disp_clk->dentist_vco_freq_khz * DIVIDER_RANGE_SCALE_FACTOR;
-+
-+	ASSERT_CRITICAL(!!disp_clk_khz);
-+
-+	if (disp_clk_khz)
-+		div = scaled_vco / disp_clk_khz;
-+
-+	did = dal_divider_range_get_did(divider_ranges, DIVIDER_RANGE_MAX, div);
-+
-+	if (did != INVALID_DID) {
-+		div = dal_divider_range_get_divider(
-+			divider_ranges, DIVIDER_RANGE_MAX, did);
-+
-+		if ((div != INVALID_DIVIDER) &&
-+			(did > DIVIDER_RANGE_01_BASE_DIVIDER_ID))
-+			if (disp_clk_khz > (scaled_vco / div))
-+				div = dal_divider_range_get_divider(
-+					divider_ranges, DIVIDER_RANGE_MAX,
-+					did - 1);
-+
-+		if (div != INVALID_DIVIDER)
-+			disp_clk_khz = scaled_vco / div;
-+
-+	}
-+	/* We need to add 10KHz to this value because the accuracy in VBIOS is
-+	 in 10KHz units. So we need to always round the last digit up in order
-+	 to reach the next div level.*/
-+	return disp_clk_khz + 10;
-+}
-+
-+static uint32_t calc_single_display_min_clks(
-+	struct display_clock *base,
-+	struct min_clock_params *params,
-+	bool set_clk)
-+{
-+	struct fixed32_32 h_scale_ratio = dal_fixed32_32_one;
-+	struct fixed32_32 v_scale_ratio = dal_fixed32_32_one;
-+	uint32_t pix_clk_khz = 0;
-+	uint32_t lb_source_width = 0;
-+	struct fixed32_32 deep_color_factor;
-+	struct fixed32_32 scaler_efficiency;
-+	struct fixed32_32 v_filter_init;
-+	uint32_t v_filter_init_trunc;
-+	uint32_t num_lines_at_frame_start = 3;
-+	struct fixed32_32 v_filter_init_ceil;
-+	struct fixed32_32 lines_per_lines_out_at_frame_start;
-+	struct fixed32_32 lb_lines_in_per_line_out; /* in middle of the frame*/
-+	uint32_t src_wdth_rnd_to_chunks;
-+	struct fixed32_32 scaling_coeff;
-+	struct fixed32_32 h_blank_granularity_factor =
-+			dal_fixed32_32_one;
-+	struct fixed32_32 fx_disp_clk_mhz;
-+	struct fixed32_32 line_time;
-+	struct fixed32_32 disp_pipe_pix_throughput;
-+	struct fixed32_32 fx_alt_disp_clk_mhz;
-+	uint32_t disp_clk_khz;
-+	uint32_t alt_disp_clk_khz;
-+	struct display_clock_dce112 *disp_clk_110 = DCLCK112_FROM_BASE(base);
-+	uint32_t max_clk_khz = get_validation_clock(base);
-+	bool panning_allowed = false; /* TODO: receive this value from AS */
-+
-+	if (params == NULL) {
-+		dal_logger_write(base->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Invalid input parameter in %s",
-+				__func__);
-+		return 0;
-+	}
-+
-+	deep_color_factor = get_deep_color_factor(params);
-+	scaler_efficiency = get_scaler_efficiency(base->ctx, params);
-+	pix_clk_khz = params->requested_pixel_clock;
-+	lb_source_width = params->source_view.width;
-+
-+	if (0 != params->dest_view.height && 0 != params->dest_view.width) {
-+
-+		h_scale_ratio = dal_fixed32_32_from_fraction(
-+			params->source_view.width,
-+			params->dest_view.width);
-+		v_scale_ratio = dal_fixed32_32_from_fraction(
-+			params->source_view.height,
-+			params->dest_view.height);
-+	} else {
-+		dal_logger_write(base->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"Destination height or width is 0!\n");
-+	}
-+
-+	v_filter_init =
-+		dal_fixed32_32_add(
-+			v_scale_ratio,
-+			dal_fixed32_32_add_int(
-+				dal_fixed32_32_div_int(
-+					dal_fixed32_32_mul_int(
-+						v_scale_ratio,
-+						params->timing_info.INTERLACED),
-+					2),
-+				params->scaling_info.v_taps + 1));
-+	v_filter_init = dal_fixed32_32_div_int(v_filter_init, 2);
-+
-+	v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
-+
-+	v_filter_init_ceil = dal_fixed32_32_from_fraction(
-+						v_filter_init_trunc, 2);
-+	v_filter_init_ceil = dal_fixed32_32_from_int(
-+		dal_fixed32_32_ceil(v_filter_init_ceil));
-+	v_filter_init_ceil = dal_fixed32_32_mul_int(v_filter_init_ceil, 2);
-+
-+	lines_per_lines_out_at_frame_start =
-+			dal_fixed32_32_div_int(v_filter_init_ceil,
-+					num_lines_at_frame_start);
-+	lb_lines_in_per_line_out =
-+			get_lb_lines_in_per_line_out(params, v_scale_ratio);
-+
-+	if (panning_allowed)
-+		src_wdth_rnd_to_chunks =
-+			((lb_source_width - 1) / 128) * 128 + 256;
-+	else
-+		src_wdth_rnd_to_chunks =
-+			((lb_source_width + 127) / 128) * 128;
-+
-+	scaling_coeff =
-+		dal_fixed32_32_div(
-+			dal_fixed32_32_from_int(params->scaling_info.v_taps),
-+			scaler_efficiency);
-+
-+	if (dal_fixed32_32_le(h_scale_ratio, dal_fixed32_32_one))
-+		scaling_coeff = dal_fixed32_32_max(
-+			dal_fixed32_32_from_int(
-+				dal_fixed32_32_ceil(
-+					dal_fixed32_32_from_fraction(
-+						params->scaling_info.h_taps,
-+						4))),
-+			dal_fixed32_32_max(
-+				dal_fixed32_32_mul(
-+					scaling_coeff,
-+					h_scale_ratio),
-+				dal_fixed32_32_one));
-+
-+	if (!params->line_buffer_prefetch_enabled &&
-+		dal_fixed32_32_floor(lb_lines_in_per_line_out) != 2 &&
-+		dal_fixed32_32_floor(lb_lines_in_per_line_out) != 4) {
-+		uint32_t line_total_pixel =
-+			params->timing_info.h_total + lb_source_width - 256;
-+		h_blank_granularity_factor = dal_fixed32_32_div(
-+			dal_fixed32_32_from_int(params->timing_info.h_total),
-+			dal_fixed32_32_div(
-+			dal_fixed32_32_from_fraction(
-+				line_total_pixel, 2),
-+				h_scale_ratio));
-+	}
-+
-+	/* Calculate display clock with ramping. Ramping factor is 1.1*/
-+	fx_disp_clk_mhz =
-+		dal_fixed32_32_div_int(
-+			dal_fixed32_32_mul_int(scaling_coeff, 11),
-+			10);
-+	line_time = dal_fixed32_32_from_fraction(
-+			params->timing_info.h_total * 1000, pix_clk_khz);
-+
-+	disp_pipe_pix_throughput = dal_fixed32_32_mul(
-+			lb_lines_in_per_line_out, h_blank_granularity_factor);
-+	disp_pipe_pix_throughput = dal_fixed32_32_max(
-+			disp_pipe_pix_throughput,
-+			lines_per_lines_out_at_frame_start);
-+	disp_pipe_pix_throughput = dal_fixed32_32_div(dal_fixed32_32_mul_int(
-+			disp_pipe_pix_throughput, src_wdth_rnd_to_chunks),
-+			line_time);
-+
-+	if (0 != params->timing_info.h_total) {
-+		fx_disp_clk_mhz =
-+			dal_fixed32_32_max(
-+				dal_fixed32_32_div_int(
-+					dal_fixed32_32_mul_int(
-+						scaling_coeff, pix_clk_khz),
-+						1000),
-+				disp_pipe_pix_throughput);
-+		fx_disp_clk_mhz =
-+			dal_fixed32_32_mul(
-+				fx_disp_clk_mhz,
-+				dal_fixed32_32_from_fraction(11, 10));
-+	}
-+
-+	fx_disp_clk_mhz = dal_fixed32_32_max(fx_disp_clk_mhz,
-+		dal_fixed32_32_mul(deep_color_factor,
-+		dal_fixed32_32_from_fraction(11, 10)));
-+
-+	/* Calculate display clock without ramping */
-+	fx_alt_disp_clk_mhz = scaling_coeff;
-+
-+	if (0 != params->timing_info.h_total) {
-+		fx_alt_disp_clk_mhz = dal_fixed32_32_max(
-+				dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
-+						scaling_coeff, pix_clk_khz),
-+						1000),
-+				dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
-+						disp_pipe_pix_throughput, 105),
-+						100));
-+	}
-+
-+	if (set_clk && disp_clk_110->ss_on_gpu_pll &&
-+			disp_clk_110->gpu_pll_ss_divider)
-+		fx_alt_disp_clk_mhz = dal_fixed32_32_mul(fx_alt_disp_clk_mhz,
-+				dal_fixed32_32_add_int(
-+				dal_fixed32_32_div_int(
-+				dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+				disp_clk_110->gpu_pll_ss_percentage,
-+				disp_clk_110->gpu_pll_ss_divider), 100),
-+				2),
-+				1));
-+
-+	/* convert to integer */
-+	disp_clk_khz = dal_fixed32_32_round(
-+			dal_fixed32_32_mul_int(fx_disp_clk_mhz, 1000));
-+	alt_disp_clk_khz = dal_fixed32_32_round(
-+			dal_fixed32_32_mul_int(fx_alt_disp_clk_mhz, 1000));
-+
-+	if ((disp_clk_khz > max_clk_khz) && (alt_disp_clk_khz <= max_clk_khz))
-+		disp_clk_khz = alt_disp_clk_khz;
-+
-+	if (set_clk) { /* only compensate clock if we are going to set it.*/
-+		disp_clk_khz = get_actual_required_display_clk(
-+			disp_clk_110, disp_clk_khz);
-+	}
-+
-+	disp_clk_khz = disp_clk_khz > max_clk_khz ? max_clk_khz : disp_clk_khz;
-+
-+	return disp_clk_khz;
-+}
-+
-+static uint32_t calculate_min_clock(
-+	struct display_clock *base,
-+	uint32_t path_num,
-+	struct min_clock_params *params)
-+{
-+	uint32_t i;
-+	uint32_t validation_clk_khz =
-+			get_validation_clock(base);
-+	uint32_t min_clk_khz = validation_clk_khz;
-+	uint32_t max_clk_khz = 0;
-+	struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-+
-+	if (dc->use_max_disp_clk)
-+		return min_clk_khz;
-+
-+	if (params != NULL) {
-+		uint32_t disp_clk_khz = 0;
-+
-+		for (i = 0; i < path_num; ++i) {
-+
-+			disp_clk_khz = calc_single_display_min_clks(
-+							base, params, true);
-+
-+			/* update the max required clock found*/
-+			if (disp_clk_khz > max_clk_khz)
-+				max_clk_khz = disp_clk_khz;
-+
-+			params++;
-+		}
-+	}
-+
-+	min_clk_khz = max_clk_khz;
-+
-+	if (min_clk_khz > validation_clk_khz)
-+		min_clk_khz = validation_clk_khz;
-+	else if (min_clk_khz < base->min_display_clk_threshold_khz)
-+		min_clk_khz = base->min_display_clk_threshold_khz;
-+
-+	if (dc->use_max_disp_clk)
-+		min_clk_khz = get_validation_clock(base);
-+
-+	return min_clk_khz;
-+}
-+
-+static bool display_clock_integrated_info_construct(
-+	struct display_clock_dce112 *disp_clk,
-+	struct adapter_service *as)
-+{
-+	struct integrated_info info;
-+	uint32_t i;
-+	struct display_clock *base = &disp_clk->disp_clk_base;
-+
-+	memset(&info, 0, sizeof(struct integrated_info));
-+
-+	disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
-+	if (disp_clk->dentist_vco_freq_khz == 0)
-+		disp_clk->dentist_vco_freq_khz = 3600000;
-+
-+	disp_clk->crystal_freq_khz = 100000;
-+
-+	base->min_display_clk_threshold_khz =
-+		disp_clk->dentist_vco_freq_khz / 64;
-+
-+	/*update the maximum display clock for each power state*/
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
-+
-+		switch (i) {
-+		case 0:
-+			clk_state = CLOCKS_STATE_ULTRA_LOW;
-+			break;
-+
-+		case 1:
-+			clk_state = CLOCKS_STATE_LOW;
-+			break;
-+
-+		case 2:
-+			clk_state = CLOCKS_STATE_NOMINAL;
-+			break;
-+
-+		case 3:
-+			clk_state = CLOCKS_STATE_PERFORMANCE;
-+			break;
-+
-+		default:
-+			clk_state = CLOCKS_STATE_INVALID;
-+			break;
-+		}
-+
-+		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
-+		 * check for > 100MHz*/
-+		if (info.disp_clk_voltage[i].max_supported_clk >= 100000) {
-+			max_clks_by_state[clk_state].display_clk_khz =
-+				info.disp_clk_voltage[i].max_supported_clk;
-+		}
-+	}
-+	disp_clk->dfs_bypass_enabled =
-+		dal_adapter_service_is_dfs_bypass_enabled(as);
-+	disp_clk->use_max_disp_clk =
-+		dal_adapter_service_is_feature_supported(
-+			FEATURE_USE_MAX_DISPLAY_CLK);
-+
-+	return true;
-+}
-+
-+static uint32_t get_clock(struct display_clock *dc)
-+{
-+	uint32_t disp_clock = get_validation_clock(dc);
-+	uint32_t target_div = INVALID_DIVIDER;
-+	uint32_t addr = mmDENTIST_DISPCLK_CNTL;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
-+	 DID DENTIST_DISPCLK_WDIVIDER.*/
-+	value = dm_read_reg(dc->ctx, addr);
-+	field = get_reg_field_value(
-+			value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
-+
-+	/* Convert DENTIST_DISPCLK_WDIVIDER to actual divider*/
-+	target_div = dal_divider_range_get_divider(
-+		divider_ranges,
-+		DIVIDER_RANGE_MAX,
-+		field);
-+
-+	if (target_div != INVALID_DIVIDER)
-+		/* Calculate the current DFS clock in KHz.
-+		 Should be okay up to 42.9 THz before overflowing.*/
-+		disp_clock = (DIVIDER_RANGE_SCALE_FACTOR
-+			* disp_clk->dentist_vco_freq_khz) / target_div;
-+	return disp_clock;
-+}
-+
-+static enum clocks_state get_required_clocks_state(
-+		struct display_clock *dc,
-+		struct state_dependent_clocks *req_clocks)
-+{
-+	int32_t i;
-+	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-+	enum clocks_state low_req_clk = disp_clk->max_clks_state;
-+
-+	if (!req_clocks) {
-+		/* NULL pointer*/
-+		dal_logger_write(dc->ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_GPU,
-+				"%s: Invalid parameter",
-+				__func__);
-+		return CLOCKS_STATE_INVALID;
-+	}
-+
-+	/* Iterate from highest supported to lowest valid state, and update
-+	 * lowest RequiredState with the lowest state that satisfies
-+	 * all required clocks
-+	 */
-+	for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
-+		if ((req_clocks->display_clk_khz <=
-+			max_clks_by_state[i].display_clk_khz) &&
-+			(req_clocks->pixel_clk_khz <=
-+				max_clks_by_state[i].pixel_clk_khz))
-+			low_req_clk = i;
-+	}
-+	return low_req_clk;
-+}
-+
-+static void set_clock(
-+	struct display_clock *base,
-+	uint32_t requested_clk_khz)
-+{
-+	struct bp_set_dce_clock_parameters dce_clk_params;
-+	struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-+	struct dc_bios *bp = dal_adapter_service_get_bios_parser(base->as);
-+
-+	/* Prepare to program display clock*/
-+	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
-+
-+	dce_clk_params.target_clock_frequency = requested_clk_khz;
-+	dce_clk_params.pll_id = dc->disp_clk_base.id;
-+	dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
-+
-+	bp->funcs->set_dce_clock(bp, &dce_clk_params);
-+
-+	/* from power down, we need mark the clock state as ClocksStateNominal
-+	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-+	if (requested_clk_khz == 0)
-+		base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
-+
-+	/*Program DP ref Clock*/
-+	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
-+	dce_clk_params.target_clock_frequency = 0;
-+	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-+	dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
-+			(dce_clk_params.pll_id == CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
-+
-+	bp->funcs->set_dce_clock(bp, &dce_clk_params);
-+}
-+
-+static void set_clock_state(
-+	struct display_clock *dc,
-+	struct display_clock_state clk_state)
-+{
-+	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-+
-+	disp_clk->clock_state = clk_state;
-+}
-+
-+static struct display_clock_state get_clock_state(
-+	struct display_clock *dc)
-+{
-+	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-+
-+	return disp_clk->clock_state;
-+}
-+
-+static uint32_t get_dfs_bypass_threshold(struct display_clock *dc)
-+{
-+	return dce112_DFS_BYPASS_THRESHOLD_KHZ;
-+}
-+
-+static const struct display_clock_funcs funcs = {
-+	.destroy = destroy,
-+	.calculate_min_clock = calculate_min_clock,
-+	.get_clock = get_clock,
-+	.get_clock_state = get_clock_state,
-+	.get_dfs_bypass_threshold = get_dfs_bypass_threshold,
-+	.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
-+	.get_min_clocks_state = get_min_clocks_state,
-+	.get_required_clocks_state = get_required_clocks_state,
-+	.get_validation_clock = get_validation_clock,
-+	.set_clock = set_clock,
-+	.set_clock_state = set_clock_state,
-+	.set_dp_ref_clock_source = NULL,
-+	.set_min_clocks_state = set_min_clocks_state,
-+	.store_max_clocks_state = store_max_clocks_state,
-+	.validate = NULL,
-+};
-+
-+static bool dal_display_clock_dce112_construct(
-+	struct display_clock_dce112 *dc112,
-+	struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct display_clock *dc_base = &dc112->disp_clk_base;
-+
-+	if (NULL == as)
-+		return false;
-+
-+	if (!dal_display_clock_construct_base(dc_base, ctx, as))
-+		return false;
-+
-+	dc_base->funcs = &funcs;
-+
-+	dc112->dfs_bypass_disp_clk = 0;
-+
-+	if (!display_clock_integrated_info_construct(dc112, as))
-+		dal_logger_write(dc_base->ctx->logger,
-+			LOG_MAJOR_WARNING,
-+			LOG_MINOR_COMPONENT_GPU,
-+			"Cannot obtain VBIOS integrated info\n");
-+
-+	dc112->gpu_pll_ss_percentage = 0;
-+	dc112->gpu_pll_ss_divider = 1000;
-+	dc112->ss_on_gpu_pll = false;
-+
-+	dc_base->id = CLOCK_SOURCE_ID_DFS;
-+/* Initially set max clocks state to nominal.  This should be updated by
-+ * via a pplib call to DAL IRI eventually calling a
-+ * DisplayEngineClock_dce112::StoreMaxClocksState().  This call will come in
-+ * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-+	dc112->max_clks_state = CLOCKS_STATE_NOMINAL;
-+
-+	dc112->disp_clk_base.min_display_clk_threshold_khz =
-+			dc112->crystal_freq_khz;
-+
-+	if (dc112->disp_clk_base.min_display_clk_threshold_khz <
-+			(dc112->dentist_vco_freq_khz / 62))
-+		dc112->disp_clk_base.min_display_clk_threshold_khz =
-+				(dc112->dentist_vco_freq_khz / 62);
-+
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_01],
-+		DIVIDER_RANGE_01_START,
-+		DIVIDER_RANGE_01_STEP_SIZE,
-+		DIVIDER_RANGE_01_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID);
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_02],
-+		DIVIDER_RANGE_02_START,
-+		DIVIDER_RANGE_02_STEP_SIZE,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID);
-+	dal_divider_range_construct(
-+		&divider_ranges[DIVIDER_RANGE_03],
-+		DIVIDER_RANGE_03_START,
-+		DIVIDER_RANGE_03_STEP_SIZE,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_MAX_DIVIDER_ID);
-+
-+	{
-+		uint32_t ss_info_num =
-+			dal_adapter_service_get_ss_info_num(
-+				as,
-+				AS_SIGNAL_TYPE_GPU_PLL);
-+
-+		if (ss_info_num) {
-+			struct spread_spectrum_info info;
-+			bool result;
-+
-+			memset(&info, 0, sizeof(info));
-+
-+			result =
-+				dal_adapter_service_get_ss_info(
-+					as,
-+					AS_SIGNAL_TYPE_GPU_PLL,
-+					0,
-+					&info);
-+
-+			/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
-+			 * even if SS not enabled and in that case
-+			 * SSInfo.spreadSpectrumPercentage !=0 would be sign
-+			 * that SS is enabled
-+			 */
-+			if (result && info.spread_spectrum_percentage != 0) {
-+				dc112->ss_on_gpu_pll = true;
-+				dc112->gpu_pll_ss_divider =
-+					info.spread_percentage_divider;
-+
-+				if (info.type.CENTER_MODE == 0) {
-+					/* Currently for DP Reference clock we
-+					 * need only SS percentage for
-+					 * downspread */
-+					dc112->gpu_pll_ss_percentage =
-+						info.spread_spectrum_percentage;
-+				}
-+			}
-+
-+		}
-+	}
-+
-+	dc112->use_max_disp_clk = true;
-+
-+	return true;
-+}
-+
-+/*****************************************************************************
-+ * public functions
-+ *****************************************************************************/
-+
-+struct display_clock *dal_display_clock_dce112_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as)
-+{
-+	struct display_clock_dce112 *dc112;
-+
-+	dc112 = dm_alloc(sizeof(struct display_clock_dce112));
-+
-+	if (dc112 == NULL)
-+		return NULL;
-+
-+	if (dal_display_clock_dce112_construct(dc112, ctx, as))
-+		return &dc112->disp_clk_base;
-+
-+	dm_free(dc112);
-+
-+	return NULL;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h
-new file mode 100644
-index 0000000..02fc67a
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h
-@@ -0,0 +1,54 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DISPLAY_CLOCK_DCE112_H__
-+#define __DAL_DISPLAY_CLOCK_DCE112_H__
-+
-+#include "gpu/display_clock.h"
-+
-+struct display_clock_dce112 {
-+	struct display_clock disp_clk_base;
-+	/* Max display block clocks state*/
-+	enum clocks_state max_clks_state;
-+	bool use_max_disp_clk;
-+	uint32_t crystal_freq_khz;
-+	uint32_t dentist_vco_freq_khz;
-+	/* Cache the status of DFS-bypass feature*/
-+	bool dfs_bypass_enabled;
-+	/* GPU PLL SS percentage (if down-spread enabled) */
-+	uint32_t gpu_pll_ss_percentage;
-+	/* GPU PLL SS percentage Divider (100 or 1000) */
-+	uint32_t gpu_pll_ss_divider;
-+	/* Flag for Enabled SS on GPU PLL */
-+	bool ss_on_gpu_pll;
-+	/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
-+	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
-+	uint32_t dfs_bypass_disp_clk;
-+	struct display_clock_state clock_state;
-+};
-+
-+#define DCLCK112_FROM_BASE(dc_base) \
-+	container_of(dc_base, struct display_clock_dce112, disp_clk_base)
-+
-+#endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 47e7922..2d394cf 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -88,10 +88,13 @@ struct i2caux *dal_i2caux_create(
- 		return dal_i2caux_dce80_create(as, ctx);
- #endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+	case DCE_VERSION_11_0:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
- 	case DCE_VERSION_10_0:
- #endif
--	case DCE_VERSION_11_0:
- 		return dal_i2caux_dce110_create(as, ctx);
- #endif
- 	default:
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index d6a599c..da00b2e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -505,7 +505,9 @@ struct bw_calcs_output {
- 
- enum bw_calcs_version {
- 	BW_CALCS_VERSION_INVALID,
--	BW_CALCS_VERSION_CARRIZO
-+	BW_CALCS_VERSION_CARRIZO,
-+	BW_CALCS_VERSION_ELLESMERE,
-+	BW_CALCS_VERSION_BAFFIN
- };
- 
- /**
-diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-index cde34ce..bfffa8e 100644
---- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
-@@ -65,6 +65,10 @@ struct irq_service *dal_irq_service_create(
- 	case DCE_VERSION_10_0:
- 		return dal_irq_service_dce110_create(init_data);
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case DCE_VERSION_11_2:
-+		return dal_irq_service_dce110_create(init_data);
-+#endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	case DCE_VERSION_11_0:
- 		return dal_irq_service_dce110_create(init_data);
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-index d8c4cd1..4cb6a9f 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
-@@ -83,11 +83,25 @@
- #define VI_TONGA_P_A1 21
- #define VI_FIJI_P_A0 60
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+/* DCE112 */
-+#define VI_POLARIS10_P_A0 80
-+#define VI_POLARIS11_M_A0 90
-+#endif
-+
-+#define VI_UNKNOWN 0xFF
-+
- #define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
- 		(eChipRev < 40))
- #define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
- 		(eChipRev < 80))
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
-+		(eChipRev < VI_POLARIS11_M_A0))
-+#define ASIC_REV_IS_POLARIS11_M(eChipRev) (eChipRev >= VI_POLARIS11_M_A0)
-+#endif
-+
- /* DCE11 */
- #define CZ_CARRIZO_A0 0x01
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index bcf83e9..21ee669 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -43,6 +43,9 @@ enum dce_version {
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- 	DCE_VERSION_11_0,
- #endif
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	DCE_VERSION_11_2,
-+#endif
- 	DCE_VERSION_MAX,
- };
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index a625e24..317ce3b 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -131,6 +131,12 @@ struct display_clock_state {
- 
- struct display_clock;
- 
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+struct display_clock *dal_display_clock_dce112_create(
-+	struct dc_context *ctx,
-+	struct adapter_service *as);
-+#endif
-+
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
- struct display_clock *dal_display_clock_dce110_create(
- 	struct dc_context *ctx,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0957-drm-amd-dal-dm-add-polaris-support.patch b/common/recipes-kernel/linux/files/0957-drm-amd-dal-dm-add-polaris-support.patch
deleted file mode 100644
index 2e54a47f..00000000
--- a/common/recipes-kernel/linux/files/0957-drm-amd-dal-dm-add-polaris-support.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 2faf384d2f6f937b90266775e72feffeb4053c5c Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 15 Mar 2016 11:18:46 -0400
-Subject: [PATCH 0957/1110] drm/amd/dal/dm: add polaris support
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 1564485..5b3edb8 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1007,6 +1007,10 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
- 	case CHIP_FIJI:
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
-+#endif
- 		if (dce110_register_irq_handlers(dm->adev)) {
- 			DRM_ERROR("DM: Failed to initialize IRQ\n");
- 			return -1;
-@@ -1308,6 +1312,22 @@ static int dm_early_init(void *handle)
- 		if (adev->mode_info.funcs == NULL)
- 			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
- 		break;
-+#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
-+	case CHIP_POLARIS11:
-+		adev->mode_info.num_crtc = 5;
-+		adev->mode_info.num_hpd = 5;
-+		adev->mode_info.num_dig = 5;
-+		if (adev->mode_info.funcs == NULL)
-+			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
-+		break;
-+	case CHIP_POLARIS10:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		if (adev->mode_info.funcs == NULL)
-+			adev->mode_info.funcs = &dm_dce_v11_0_display_funcs;
-+		break;
-+#endif
- 	default:
- 		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
- 		return -EINVAL;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0958-drm-amdgpu-add-dal-support-for-polaris.patch b/common/recipes-kernel/linux/files/0958-drm-amdgpu-add-dal-support-for-polaris.patch
deleted file mode 100644
index aa26bac7..00000000
--- a/common/recipes-kernel/linux/files/0958-drm-amdgpu-add-dal-support-for-polaris.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From b301cf00dd28222426a3f14f20cf833a521c5dd1 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 15 Mar 2016 12:30:09 -0400
-Subject: [PATCH 0958/1110] drm/amdgpu: add dal support for polaris
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +-
- drivers/gpu/drm/amd/amdgpu/vi.c            | 79 ++++++++++++++++++++++++++++++
- 2 files changed, 82 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index b73533d..8885e9e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1407,9 +1407,11 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev)
- 	case CHIP_HAWAII:
- 		return amdgpu_dal != 0;
- #endif
--#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0)
-+#if defined(CONFIG_DRM_AMD_DAL) && (defined(CONFIG_DRM_AMD_DAL_DCE11_0) || defined(CONFIG_DRM_AMD_DAL_DCE11_2))
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
- 		return amdgpu_dal != 0;
- #endif
- #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE10_0)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index ef80cfb..8d876a7 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1144,6 +1144,75 @@ static const struct amdgpu_ip_block_version cz_ip_blocks_dal[] =
- #endif
- };
- 
-+static const struct amdgpu_ip_block_version polaris11_ip_blocks_dal[] =
-+{
-+	/* ORDER MATTERS! */
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_COMMON,
-+		.major = 2,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &vi_common_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GMC,
-+		.major = 8,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &gmc_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_IH,
-+		.major = 3,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &tonga_ih_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SMC,
-+		.major = 7,
-+		.minor = 2,
-+		.rev = 0,
-+		/* To Do */
-+		.funcs = &amdgpu_pp_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_DCE,
-+		.major = 11,
-+		.minor = 2,
-+		.rev = 0,
-+		.funcs = &amdgpu_dm_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_GFX,
-+		.major = 8,
-+		.minor = 0,
-+		.rev = 0,
-+		.funcs = &gfx_v8_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_SDMA,
-+		.major = 3,
-+		.minor = 1,
-+		.rev = 0,
-+		.funcs = &sdma_v3_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_UVD,
-+		.major = 6,
-+		.minor = 3,
-+		.rev = 0,
-+		.funcs = &uvd_v6_0_ip_funcs,
-+	},
-+	{
-+		.type = AMD_IP_BLOCK_TYPE_VCE,
-+		.major = 3,
-+		.minor = 4,
-+		.rev = 0,
-+		.funcs = &vce_v3_0_ip_funcs,
-+	},
-+};
-+
- static const struct amdgpu_ip_block_version tonga_ip_blocks_dal[] =
- {
- 	/* ORDER MATTERS! */
-@@ -1318,8 +1387,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		break;
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS10:
-+#if defined(CONFIG_DRM_AMD_DAL)
-+		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+			adev->ip_blocks = polaris11_ip_blocks_dal;
-+			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_dal);
-+		} else {
-+			adev->ip_blocks = polaris11_ip_blocks;
-+			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
-+		}
-+#else
- 		adev->ip_blocks = polaris11_ip_blocks;
- 		adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
-+#endif
- 		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0959-drm-amd-dal-Enable-Polaris-support-in-the-Kconfig.patch b/common/recipes-kernel/linux/files/0959-drm-amd-dal-Enable-Polaris-support-in-the-Kconfig.patch
deleted file mode 100644
index 87f56ce4..00000000
--- a/common/recipes-kernel/linux/files/0959-drm-amd-dal-Enable-Polaris-support-in-the-Kconfig.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 96737bab5e7a23e79f5fdeeff2bbae5eaa28a58b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 15 Mar 2016 11:20:21 -0400
-Subject: [PATCH 0959/1110] drm/amd/dal: Enable Polaris support in the Kconfig
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/Kconfig | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
-index b108756..939d5c6 100644
---- a/drivers/gpu/drm/amd/dal/Kconfig
-+++ b/drivers/gpu/drm/amd/dal/Kconfig
-@@ -46,6 +46,16 @@ config DRM_AMD_DAL_DCE11_0
- 	 CZ family
- 	 for display engine
- 
-+config DRM_AMD_DAL_DCE11_2
-+        bool "Polaris11 family"
-+        depends on DRM_AMD_DAL
-+	select DRM_AMD_DAL_DCE11_0
-+        help
-+         Choose this option
-+	 if you want to have
-+	 BF family
-+	 for display engine.
-+
- config DEBUG_KERNEL_DAL
-         bool "Enable kgdb break in DAL"
-         depends on DRM_AMD_DAL
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0960-drm-amd-amdgpu-fix-64-bit-division.patch b/common/recipes-kernel/linux/files/0960-drm-amd-amdgpu-fix-64-bit-division.patch
deleted file mode 100644
index 934863d7..00000000
--- a/common/recipes-kernel/linux/files/0960-drm-amd-amdgpu-fix-64-bit-division.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 331e94f82101f319170bedc5f4b79f73227cfa2d Mon Sep 17 00:00:00 2001
-From: Slava Grigorev <slava.grigorev@amd.com>
-Date: Tue, 22 Mar 2016 23:34:29 -0400
-Subject: [PATCH 0960/1110] drm/amd/amdgpu: fix 64-bit division
-
-Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c                 | 4 ++--
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 7 +++++--
- 2 files changed, 7 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index b043dd6..d0ec83f 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -942,14 +942,14 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
- 		goto out;
- 	}
- 
--	tmp = (unsigned int *)((uint64_t)rlc_hdr +
-+	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
- 			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
- 	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
- 		adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
- 
- 	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
- 
--	tmp = (unsigned int *)((uint64_t)rlc_hdr +
-+	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
- 			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
- 	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
- 		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 715bc3d..a5172d1 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -23,6 +23,7 @@
- #include <linux/module.h>
- #include <linux/slab.h>
- #include <linux/fb.h>
-+#include <asm/div64.h>
- #include "linux/delay.h"
- #include "pp_acpi.h"
- #include "hwmgr.h"
-@@ -981,7 +982,8 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- 	sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
- 	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
- 	temp <<= 0x10;
--	sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
-+	do_div(temp, ref_clock);
-+	sclk_setting->Fcw_frac = temp & 0xffff;
- 
- 	pcc_target_percent = 10; /*  Hardcode 10% for now. */
- 	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
-@@ -995,7 +997,8 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- 		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
- 		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
- 		temp <<= 0x10;
--		sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
-+		do_div(temp, ref_clock);
-+		sclk_setting->Fcw1_frac = temp & 0xffff;
- 	}
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0961-drm-amd-powerplay-fix-copy-paste-error-in-error-mess.patch b/common/recipes-kernel/linux/files/0961-drm-amd-powerplay-fix-copy-paste-error-in-error-mess.patch
deleted file mode 100644
index a4365180..00000000
--- a/common/recipes-kernel/linux/files/0961-drm-amd-powerplay-fix-copy-paste-error-in-error-mess.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From e192788c8b5897f02cb3ac08ab7aba0e124ba1b0 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 25 Mar 2016 12:23:49 -0400
-Subject: [PATCH 0961/1110] drm/amd/powerplay: fix copy paste error in error
- message
-
-Noticed-by: Vasily Anonimov <vasily.anonimov@googlemail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index a5172d1..8a90a56 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -2533,7 +2533,7 @@ int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
- 
- 	tmp_result = polaris10_pcie_performance_request(hwmgr);
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
--			"Failed to enable thermal auto throttle!", result = tmp_result);
-+			"pcie performance request failed!", result = tmp_result);
- 
- 	return result;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0962-drm-amdgpu-code-style-refine.patch b/common/recipes-kernel/linux/files/0962-drm-amdgpu-code-style-refine.patch
deleted file mode 100644
index e6e6062b..00000000
--- a/common/recipes-kernel/linux/files/0962-drm-amdgpu-code-style-refine.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 9a7bbef9a806eb993df27dd8a433c1a011318475 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Mar 2016 14:48:03 +0800
-Subject: [PATCH 0962/1110] drm/amdgpu: code style refine.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index b5b5ff3..7327a20 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -55,7 +55,7 @@
- #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
- #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
- #define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
--#define FIRMWARE_POLARIS11         "amdgpu/polaris11_uvd.bin"
-+#define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"
- 
- /**
-  * amdgpu_uvd_cs_ctx - Command submission parser context
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0963-drm-amd-powerplay-enable-some-feature-for-baffin-ell.patch b/common/recipes-kernel/linux/files/0963-drm-amd-powerplay-enable-some-feature-for-baffin-ell.patch
deleted file mode 100644
index a67b2549..00000000
--- a/common/recipes-kernel/linux/files/0963-drm-amd-powerplay-enable-some-feature-for-baffin-ell.patch
+++ /dev/null
@@ -1,210 +0,0 @@
-From d13b24996ec4869457d5259c42c8d0ecc814281a Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Mar 2016 14:50:22 +0800
-Subject: [PATCH 0963/1110] drm/amd/powerplay: enable some feature for
- baffin/ellesmere. (v2)
-
-Sync up with internal updates.
-
-v2: squash in:
-drm/amd/powerplay: set revert flag for enable thermal protect.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  2 +-
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 94 +++++++++++++++++++---
- 2 files changed, 83 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 55a006d..dc836d3 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -3377,7 +3377,7 @@ static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
- 				DPM_EVENT_SRC, src);
- 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
- 				THERMAL_PROTECTION_DIS,
--				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_ThermalController));
- 	} else
- 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 8a90a56..85a3341 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -2395,7 +2395,7 @@ static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sou
- 				DPM_EVENT_SRC, src);
- 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
- 				THERMAL_PROTECTION_DIS,
--				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_ThermalController));
- 	} else
- 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
-@@ -2562,6 +2562,9 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SclkDeepSleep);
- 
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_DynamicPatchPowerState);
-+
- 	if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
- 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 				PHM_PlatformCaps_EnableMVDDControl);
-@@ -2580,6 +2583,9 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
- 			PHM_PlatformCaps_DynamicPowerManagement);
- 
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_UnTabledHardwareInterface);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_TablelessHardwareInterface);
- 
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-@@ -2596,10 +2602,6 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
- 
- 	/* power tune caps Assume disabled */
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_PowerContainment);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--							PHM_PlatformCaps_CAC);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_SQRamping);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_DBRamping);
-@@ -2608,6 +2610,22 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_TCPRamping);
- 
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_PowerContainment);
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+							PHM_PlatformCaps_CAC);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_RegulatorHot);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_AutomaticDCTransition);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_ODFuzzyFanControlSupport);
-+
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_FanSpeedInTableIsRPM);
- 	if (hwmgr->chip_id == CHIP_POLARIS11)
- 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_SPLLShutdownSupport);
-@@ -2890,6 +2908,11 @@ static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
- 	table_info->max_clock_voltage_on_ac.vddci =
- 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
- 
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
-+	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
-+
- 	return 0;
- }
- 
-@@ -2899,6 +2922,8 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 	struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
- 	uint32_t temp_reg;
- 	int result;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
- 
- 	data->dll_default_on = false;
- 	data->sram_end = SMC_RAM_END;
-@@ -2937,9 +2962,6 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
- 		data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
- 
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_DynamicPatchPowerState);
--
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_EnableMVDDControl)) {
- 		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-@@ -2987,10 +3009,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 							POLARIS10_MAX_HARDWARE_POWERLEVELS;
- 		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
- 		hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
--		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
--/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
--		hwmgr->platform_descriptor.clockStep.engineClock = 500;
--		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
-+
- 
- 		if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
- 			temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
-@@ -3019,6 +3038,52 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
- 		}
- 
-+		if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
-+			hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
-+			hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
-+				(uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
-+				(uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
-+				(uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
-+
-+			table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
-+									(table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
-+
-+			table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
-+			table_info->cac_dtp_table->usOperatingTempStep = 1;
-+			table_info->cac_dtp_table->usOperatingTempHyst = 1;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
-+				       hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
-+
-+			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
-+				       hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
-+
-+			hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
-+				       table_info->cac_dtp_table->usOperatingTempMinLimit;
-+
-+			hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
-+				       table_info->cac_dtp_table->usOperatingTempMaxLimit;
-+
-+			hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
-+				       table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
-+
-+			hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
-+				       table_info->cac_dtp_table->usOperatingTempStep;
-+
-+			hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
-+				       table_info->cac_dtp_table->usTargetOperatingTemp;
-+		}
-+
- 		sys_info.size = sizeof(struct cgs_system_info);
- 		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
- 		result = cgs_query_system_info(hwmgr->device, &sys_info);
-@@ -3035,6 +3100,11 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 			data->pcie_lane_cap = 0x2f0000;
- 		else
- 			data->pcie_lane_cap = (uint32_t)sys_info.value;
-+
-+		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
-+/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
-+		hwmgr->platform_descriptor.clockStep.engineClock = 500;
-+		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
- 	} else {
- 		/* Ignore return value in here, we are cleaning up a mess. */
- 		polaris10_hwmgr_backend_fini(hwmgr);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0964-drm-amd-powerplay-add-fan-control-mode-interface-for.patch b/common/recipes-kernel/linux/files/0964-drm-amd-powerplay-add-fan-control-mode-interface-for.patch
deleted file mode 100644
index 86de40f6..00000000
--- a/common/recipes-kernel/linux/files/0964-drm-amd-powerplay-add-fan-control-mode-interface-for.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 586629aacef111672337209e76cb12265b21293b Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Mar 2016 18:47:29 +0800
-Subject: [PATCH 0964/1110] drm/amd/powerplay: add fan control mode interface
- for baffin
-
-Add interface for manual fan control.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 26 ++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 85a3341..fd29c56 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -4871,6 +4871,30 @@ static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	return size;
- }
- 
-+static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+{
-+	if (mode) {
-+		/* stop auto-manage */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl))
-+			polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
-+		polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
-+	} else
-+		/* restart auto-manage */
-+		polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr->fan_ctrl_is_in_default_mode)
-+		return hwmgr->fan_ctrl_default_mode;
-+	else
-+		return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+				CG_FDO_CTRL2, FDO_PWM_MODE);
-+}
-+
- static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
- 	.backend_init = &polaris10_hwmgr_backend_init,
- 	.backend_fini = &polaris10_hwmgr_backend_fini,
-@@ -4907,6 +4931,8 @@ static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
- 	.register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
- 	.check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
- 	.check_states_equal = polaris10_check_states_equal,
-+	.set_fan_control_mode = polaris10_set_fan_control_mode,
-+	.get_fan_control_mode = polaris10_get_fan_control_mode,
- 	.get_pp_table = polaris10_get_pp_table,
- 	.set_pp_table = polaris10_set_pp_table,
- 	.force_clock_level = polaris10_force_clock_level,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0965-drm-amd-powerplay-parameter-updates-according-to-SMC.patch b/common/recipes-kernel/linux/files/0965-drm-amd-powerplay-parameter-updates-according-to-SMC.patch
deleted file mode 100644
index d677a764..00000000
--- a/common/recipes-kernel/linux/files/0965-drm-amd-powerplay-parameter-updates-according-to-SMC.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-From 37ad363096ab99bee1b6013e012036c283867049 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Mar 2016 15:04:23 +0800
-Subject: [PATCH 0965/1110] drm/amd/powerplay: parameter updates according to
- SMC.
-
-Update to latest changes for SMC team.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/powerplay/hwmgr/polaris10_powertune.c  | 32 ++++++++++++----------
- drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h | 10 +++----
- 2 files changed, 22 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-index 4d97326..02bcedc 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-@@ -57,6 +57,13 @@ void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
- 
- }
- 
-+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
-+{
-+	uint32_t tmp;
-+	tmp = raw_setting * 4096 / 100;
-+	return (uint16_t)tmp;
-+}
-+
- int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-@@ -65,6 +72,8 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- 	struct phm_ppt_v1_information *table_info =
- 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
- 	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	struct pp_advance_fan_control_parameters *fan_table=
-+			&hwmgr->thermal_controller.advanceFanControlParameters;
- 	int i, j, k;
- 	uint16_t *pdef1;
- 	uint16_t *pdef2;
-@@ -75,15 +84,16 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- 	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
- 				"Target Operating Temp is out of Range!",
- 				);
--/*  This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */
--	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
- 
--/*  HW request to hard code this value to 8 which is 0.5C */
--	dpm_table->GpuTjHyst = 8;
-+	dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTargetOperatingTemp * 256);
-+	dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitHotspot * 256);
-+	dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainEdge));
-+	dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainHotspot));
- 
--	dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
--	dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset);
--	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT);
- 	pdef1 = defaults->BAPMTI_R;
- 	pdef2 = defaults->BAPMTI_RC;
- 
-@@ -330,14 +340,6 @@ int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr)
- 	data->power_containment_features = 0;
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_PowerContainment)) {
--		if (data->enable_dte_feature) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
--					(uint16_t)(PPSMC_MSG_EnableDTE));
--			PP_ASSERT_WITH_CODE((0 == smc_result),
--					"Failed to enable DTE in SMC.", result = -1;);
--			if (0 == smc_result)
--				data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
--		}
- 
- 		if (data->enable_tdc_limit_feature) {
- 			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-index f6a7591..0dfe823 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
-@@ -323,14 +323,14 @@ struct SMU74_Discrete_DpmTable {
- 	uint16_t                            BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
- 	uint16_t                            BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
- 
--	uint8_t                             DTEAmbientTempBase;
--	uint8_t                             DTETjOffset;
--	uint8_t                             GpuTjMax;
--	uint8_t                             GpuTjHyst;
-+	uint16_t                            TemperatureLimitEdge;
-+	uint16_t                            TemperatureLimitHotspot;
-+
- 	uint16_t                            BootVddc;
- 	uint16_t                            BootVddci;
- 
--	uint32_t                            BAPM_TEMP_GRADIENT;
-+	uint16_t                            FanGainEdge;
-+	uint16_t                            FanGainHotspot;
- 
- 	uint32_t                            LowSclkInterruptThreshold;
- 	uint32_t                            VddGfxReChkWait;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0966-drm-amd-powerplay-fix-issue-that-get-wrong-reference.patch b/common/recipes-kernel/linux/files/0966-drm-amd-powerplay-fix-issue-that-get-wrong-reference.patch
deleted file mode 100644
index 66ba8cc9..00000000
--- a/common/recipes-kernel/linux/files/0966-drm-amd-powerplay-fix-issue-that-get-wrong-reference.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From e455425f6300802cb181a566b648a2bdb6caf0d6 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 23 Mar 2016 15:12:48 +0800
-Subject: [PATCH 0966/1110] drm/amd/powerplay: fix issue that get wrong
- reference clock value.
-
-use wrong parameter to computer the reference clock.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 3bed991..0242e34 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -5893,7 +5893,7 @@ uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
- 	if (!fw_info)
- 		return 0;
- 
--	reference_clock = le16_to_cpu(fw_info->usMinPixelClockPLL_Output);
-+	reference_clock = le16_to_cpu(fw_info->usReferenceClock);
- 
- 	divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0967-drm-amd-powerplay-Fix-a-bug-for-enabling-ACDC-gpio-i.patch b/common/recipes-kernel/linux/files/0967-drm-amd-powerplay-Fix-a-bug-for-enabling-ACDC-gpio-i.patch
deleted file mode 100644
index 6dcde134..00000000
--- a/common/recipes-kernel/linux/files/0967-drm-amd-powerplay-Fix-a-bug-for-enabling-ACDC-gpio-i.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 95fa0c598c1537adc77733c2723db3f55f68149a Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Thu, 24 Mar 2016 16:44:18 -0400
-Subject: [PATCH 0967/1110] drm/amd/powerplay: Fix a bug for enabling ACDC gpio
- interrupt
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 11 +++++++----
- 1 file changed, 7 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index fd29c56..045c7ef 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -2354,10 +2354,13 @@ static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
- 				return -1);
- 	}
- 
--	PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
--					PPSMC_MSG_EnableACDCGPIOInterrupt)),
--					"Failed to enable AC DC GPIO Interrupt!",
--			);
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_Falcon_QuickTransition)) {
-+		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				PPSMC_MSG_EnableACDCGPIOInterrupt)),
-+				"Failed to enable AC DC GPIO Interrupt!",
-+				);
-+	}
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0968-drm-amd-powerplay-update-vce-power-gate-state-for-ba.patch b/common/recipes-kernel/linux/files/0968-drm-amd-powerplay-update-vce-power-gate-state-for-ba.patch
deleted file mode 100644
index 33072b07..00000000
--- a/common/recipes-kernel/linux/files/0968-drm-amd-powerplay-update-vce-power-gate-state-for-ba.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 49453f65c55e4ca8e52105a5ad7c534a109146e5 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 25 Mar 2016 13:08:46 +0800
-Subject: [PATCH 0968/1110] drm/amd/powerplay: update vce power gate state for
- baffin.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
-index e362ddb..8f142a7 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
-@@ -123,6 +123,8 @@ int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- 	if (data->vce_power_gated == bgate)
- 		return 0;
- 
-+	data->vce_power_gated = bgate;
-+
- 	if (bgate)
- 		polaris10_phm_powerdown_vce(hwmgr);
- 	else
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0969-drm-amdgpu-clean-up-dal-checks-in-set_ip_blocks-func.patch b/common/recipes-kernel/linux/files/0969-drm-amdgpu-clean-up-dal-checks-in-set_ip_blocks-func.patch
deleted file mode 100644
index f2cfc44f..00000000
--- a/common/recipes-kernel/linux/files/0969-drm-amdgpu-clean-up-dal-checks-in-set_ip_blocks-func.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 9da59a738d9fc80ebd4799ed67f1e258cf54a2f6 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 30 Mar 2016 11:43:16 -0400
-Subject: [PATCH 0969/1110] drm/amdgpu: clean up dal checks in set_ip_blocks
- functions
-
-There's no need to check amdgpu_dal.  It's already checked
-in amdgpu_device_has_dal_support.
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/vi.c  | 8 ++++----
- 2 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 7efe693..14a1411 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -2112,7 +2112,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
- 	switch (adev->asic_type) {
- 	case CHIP_BONAIRE:
- #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
--		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+		if (amdgpu_device_has_dal_support(adev)) {
- 			adev->ip_blocks = bonaire_ip_blocks_dal;
- 			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_dal);
- 		} else {
-@@ -2126,7 +2126,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
- 		break;
- 	case CHIP_HAWAII:
- #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
--		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+		if (amdgpu_device_has_dal_support(adev)) {
- 			adev->ip_blocks = hawaii_ip_blocks_dal;
- 			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_dal);
- 		} else {
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 8d876a7..b5602ac 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1359,7 +1359,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		break;
- 	case CHIP_FIJI:
- #if defined(CONFIG_DRM_AMD_DAL)
--		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+		if (amdgpu_device_has_dal_support(adev)) {
- 			adev->ip_blocks = fiji_ip_blocks_dal;
- 			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_dal);
- 		} else {
-@@ -1373,7 +1373,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 		break;
- 	case CHIP_TONGA:
- #if defined(CONFIG_DRM_AMD_DAL)
--		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+		if (amdgpu_device_has_dal_support(adev)) {
- 			adev->ip_blocks = tonga_ip_blocks_dal;
- 			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_dal);
- 		} else {
-@@ -1388,7 +1388,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS10:
- #if defined(CONFIG_DRM_AMD_DAL)
--		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+		if (amdgpu_device_has_dal_support(adev)) {
- 			adev->ip_blocks = polaris11_ip_blocks_dal;
- 			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_dal);
- 		} else {
-@@ -1403,7 +1403,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
- #if defined(CONFIG_DRM_AMD_DAL)
--		if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) {
-+		if (amdgpu_device_has_dal_support(adev)) {
- 			adev->ip_blocks = cz_ip_blocks_dal;
- 			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_dal);
- 		} else {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0970-drm-amdgpu-fix-memory-leak-in-CGS-FW-info.patch b/common/recipes-kernel/linux/files/0970-drm-amdgpu-fix-memory-leak-in-CGS-FW-info.patch
deleted file mode 100644
index 39621012..00000000
--- a/common/recipes-kernel/linux/files/0970-drm-amdgpu-fix-memory-leak-in-CGS-FW-info.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 7de9db94df0fbd976cc2e69efde4bef2506802d4 Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Wed, 30 Mar 2016 05:50:11 -0400
-Subject: [PATCH 0970/1110] drm/amdgpu: fix memory leak in CGS (FW info)
-
-Previously requested FW pointer should not be
-overwrite
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 70 +++++++++++++++++----------------
- 1 file changed, 36 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-index 837cdd2..490464e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
-@@ -735,42 +735,44 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
- 		const uint8_t *src;
- 		const struct smc_firmware_header_v1_0 *hdr;
- 
--		switch (adev->asic_type) {
--		case CHIP_TONGA:
--			strcpy(fw_name, "amdgpu/tonga_smc.bin");
--			break;
--		case CHIP_FIJI:
--			strcpy(fw_name, "amdgpu/fiji_smc.bin");
--			break;
--		case CHIP_POLARIS11:
--			if (type == CGS_UCODE_ID_SMU)
--				strcpy(fw_name, "amdgpu/polaris11_smc.bin");
--			else if (type == CGS_UCODE_ID_SMU_SK)
--				strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
--			break;
--		case CHIP_POLARIS10:
--			if (type == CGS_UCODE_ID_SMU)
--				strcpy(fw_name, "amdgpu/polaris10_smc.bin");
--			else if (type == CGS_UCODE_ID_SMU_SK)
--				strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
--			break;
--		default:
--			DRM_ERROR("SMC firmware not supported\n");
--			return -EINVAL;
--		}
-+		if (!adev->pm.fw) {
-+			switch (adev->asic_type) {
-+			case CHIP_TONGA:
-+				strcpy(fw_name, "amdgpu/tonga_smc.bin");
-+				break;
-+			case CHIP_FIJI:
-+				strcpy(fw_name, "amdgpu/fiji_smc.bin");
-+				break;
-+			case CHIP_POLARIS11:
-+				if (type == CGS_UCODE_ID_SMU)
-+					strcpy(fw_name, "amdgpu/polaris11_smc.bin");
-+				else if (type == CGS_UCODE_ID_SMU_SK)
-+					strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
-+				break;
-+			case CHIP_POLARIS10:
-+				if (type == CGS_UCODE_ID_SMU)
-+					strcpy(fw_name, "amdgpu/polaris10_smc.bin");
-+				else if (type == CGS_UCODE_ID_SMU_SK)
-+					strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
-+				break;
-+			default:
-+				DRM_ERROR("SMC firmware not supported\n");
-+				return -EINVAL;
-+			}
- 
--		err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
--		if (err) {
--			DRM_ERROR("Failed to request firmware\n");
--			return err;
--		}
-+			err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
-+			if (err) {
-+				DRM_ERROR("Failed to request firmware\n");
-+				return err;
-+			}
- 
--		err = amdgpu_ucode_validate(adev->pm.fw);
--		if (err) {
--			DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
--			release_firmware(adev->pm.fw);
--			adev->pm.fw = NULL;
--			return err;
-+			err = amdgpu_ucode_validate(adev->pm.fw);
-+			if (err) {
-+				DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
-+				release_firmware(adev->pm.fw);
-+				adev->pm.fw = NULL;
-+				return err;
-+			}
- 		}
- 
- 		hdr = (const struct smc_firmware_header_v1_0 *)	adev->pm.fw->data;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0971-drm-amd-powerplay-return-0-when-interface-not-implem.patch b/common/recipes-kernel/linux/files/0971-drm-amd-powerplay-return-0-when-interface-not-implem.patch
deleted file mode 100644
index 458c3c97..00000000
--- a/common/recipes-kernel/linux/files/0971-drm-amd-powerplay-return-0-when-interface-not-implem.patch
+++ /dev/null
@@ -1,341 +0,0 @@
-From 6d51b09d6afbf635aa6a9aaa2c6760e214ccf67b Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 30 Mar 2016 11:35:50 +0800
-Subject: [PATCH 0971/1110] drm/amd/powerplay: return 0 when interface not
- implement on some asic.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 169 +++++++++++++++++---------
- 1 file changed, 113 insertions(+), 56 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 32a6a6f..ce8d9bf 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -37,6 +37,12 @@
- 			return -EINVAL;					\
- 	} while (0)
- 
-+#define PP_CHECK_HW(hwmgr)						\
-+	do {								\
-+		if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL)	\
-+			return -EINVAL;					\
-+	} while (0)
-+
- static int pp_early_init(void *handle)
- {
- 	return 0;
-@@ -54,8 +60,9 @@ static int pp_sw_init(void *handle)
- 	pp_handle = (struct pp_instance *)handle;
- 	hwmgr = pp_handle->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->pptable_func == NULL ||
--	    hwmgr->hwmgr_func == NULL ||
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->pptable_func == NULL ||
- 	    hwmgr->pptable_func->pptable_init == NULL ||
- 	    hwmgr->hwmgr_func->backend_init == NULL)
- 		return -EINVAL;
-@@ -66,9 +73,9 @@ static int pp_sw_init(void *handle)
- 		ret = hwmgr->hwmgr_func->backend_init(hwmgr);
- 
- 	if (ret)
--		printk("amdgpu: powerplay initialization failed\n");
-+		printk(KERN_ERR "amdgpu: powerplay initialization failed\n");
- 	else
--		printk("amdgpu: powerplay initialized\n");
-+		printk(KERN_INFO "amdgpu: powerplay initialized\n");
- 
- 	return ret;
- }
-@@ -85,8 +92,9 @@ static int pp_sw_fini(void *handle)
- 	pp_handle = (struct pp_instance *)handle;
- 	hwmgr = pp_handle->hwmgr;
- 
--	if (hwmgr != NULL || hwmgr->hwmgr_func != NULL ||
--	    hwmgr->hwmgr_func->backend_fini != NULL)
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->backend_fini != NULL)
- 		ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
- 
- 	return ret;
-@@ -188,11 +196,12 @@ static int pp_set_clockgating_state(void *handle,
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
--			return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
- 
--	if (hwmgr->hwmgr_func->update_clock_gatings == NULL)
-+	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
- 		return 0;
-+	}
- 
- 	if (state == AMD_CG_STATE_UNGATE)
- 		pp_state = 0;
-@@ -276,9 +285,12 @@ static int pp_set_powergating_state(void *handle,
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--			hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL)
--				return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	/* Enable/disable GFX per cu powergating through SMU */
- 	return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
-@@ -371,9 +383,12 @@ static int pp_dpm_force_performance_level(void *handle,
- 
- 	hwmgr = pp_handle->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	    hwmgr->hwmgr_func->force_dpm_level == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
- 
-@@ -405,9 +420,12 @@ static int pp_dpm_get_sclk(void *handle, bool low)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	    hwmgr->hwmgr_func->get_sclk == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_sclk == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
- }
-@@ -421,9 +439,12 @@ static int pp_dpm_get_mclk(void *handle, bool low)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	    hwmgr->hwmgr_func->get_mclk == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_mclk == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
- }
-@@ -437,9 +458,12 @@ static int pp_dpm_powergate_vce(void *handle, bool gate)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	    hwmgr->hwmgr_func->powergate_vce == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- }
-@@ -453,9 +477,12 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	    hwmgr->hwmgr_func->powergate_uvd == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- }
-@@ -551,9 +578,13 @@ pp_debugfs_print_current_performance_level(void *handle,
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	  hwmgr->hwmgr_func->print_current_perforce_level == NULL)
-+	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
-+		return;
-+
-+	if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
- 		return;
-+	}
- 
- 	hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
- }
-@@ -567,9 +598,12 @@ static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	  hwmgr->hwmgr_func->set_fan_control_mode == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
- }
-@@ -583,9 +617,12 @@ static int pp_dpm_get_fan_control_mode(void *handle)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	  hwmgr->hwmgr_func->get_fan_control_mode == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
- }
-@@ -599,9 +636,12 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	  hwmgr->hwmgr_func->set_fan_speed_percent == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
- }
-@@ -615,9 +655,12 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	  hwmgr->hwmgr_func->get_fan_speed_percent == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
- }
-@@ -631,9 +674,12 @@ static int pp_dpm_get_temperature(void *handle)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--	  hwmgr->hwmgr_func->get_temperature == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_temperature == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->get_temperature(hwmgr);
- }
-@@ -687,9 +733,12 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--		hwmgr->hwmgr_func->get_pp_table == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->get_pp_table == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->get_pp_table(hwmgr, table);
- }
-@@ -703,9 +752,12 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--		hwmgr->hwmgr_func->set_pp_table == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->set_pp_table == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
- }
-@@ -720,9 +772,12 @@ static int pp_dpm_force_clock_level(void *handle,
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--			hwmgr->hwmgr_func->force_clock_level == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
-+
-+	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 
- 	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
- }
-@@ -737,10 +792,12 @@ static int pp_dpm_print_clock_levels(void *handle,
- 
- 	hwmgr = ((struct pp_instance *)handle)->hwmgr;
- 
--	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
--			hwmgr->hwmgr_func->print_clock_levels == NULL)
--		return -EINVAL;
-+	PP_CHECK_HW(hwmgr);
- 
-+	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
-+		printk(KERN_INFO "%s was not implemented.\n", __func__);
-+		return 0;
-+	}
- 	return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0972-drm-amd-powerplay-fix-some-initialize-error-on-polar.patch b/common/recipes-kernel/linux/files/0972-drm-amd-powerplay-fix-some-initialize-error-on-polar.patch
deleted file mode 100644
index c654c86a..00000000
--- a/common/recipes-kernel/linux/files/0972-drm-amd-powerplay-fix-some-initialize-error-on-polar.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 2229280e2d2582a34a57663fc024384d3a25c78e Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Fri, 1 Apr 2016 19:56:07 +0800
-Subject: [PATCH 0972/1110] drm/amd/powerplay: fix some initialize error on
- polaris10.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 045c7ef..c3e9aca 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -2600,9 +2600,6 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_DynamicUVDState);
- 
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_SclkThrottleLowNotification);
--
- 	/* power tune caps Assume disabled */
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_SQRamping);
-@@ -2930,7 +2927,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 
- 	data->dll_default_on = false;
- 	data->sram_end = SMC_RAM_END;
--
-+	data->mclk_dpm0_activity_target = 0xa;
- 	data->disable_dpm_mask = 0xFF;
- 	data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
- 	data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0973-drm-amd-powerplay-fix-bug-dpm-can-t-work-when-resume.patch b/common/recipes-kernel/linux/files/0973-drm-amd-powerplay-fix-bug-dpm-can-t-work-when-resume.patch
deleted file mode 100644
index 6a2a15f3..00000000
--- a/common/recipes-kernel/linux/files/0973-drm-amd-powerplay-fix-bug-dpm-can-t-work-when-resume.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 7611c95cb9ab9f180ee166cfc1124bc59f787ea1 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 4 Apr 2016 11:52:56 -0400
-Subject: [PATCH 0973/1110] drm/amd/powerplay: fix bug dpm can't work when
- resume back on Polaris
-
-Fixes dpm on resume.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index c3e9aca..2ab3bb2 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -1565,6 +1565,7 @@ static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
- 
- 	for (count = 0; count < table->VceLevelCount; count++) {
- 		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage = 0;
- 		table->VceLevel[count].MinVoltage |=
- 				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
- 		table->VceLevel[count].MinVoltage |=
-@@ -1604,6 +1605,7 @@ static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
- 
- 	for (count = 0; count < table->SamuLevelCount; count++) {
- 		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].MinVoltage = 0;
- 		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
- 		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
- 				VOLTAGE_SCALE) << VDDC_SHIFT;
-@@ -1696,6 +1698,7 @@ static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
- 	table->UvdBootLevel = 0;
- 
- 	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].MinVoltage = 0;
- 		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
- 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
- 		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-@@ -2011,6 +2014,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
- 	if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
- 		polaris10_populate_smc_voltage_tables(hwmgr, table);
- 
-+	table->SystemFlags = 0;
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_AutomaticDCTransition))
- 		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-@@ -2104,6 +2108,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
- 	table->MemoryThermThrottleEnable = 1;
- 	table->PCIeBootLinkLevel = 0;
- 	table->PCIeGenInterval = 1;
-+	table->VRConfig = 0;
- 
- 	result = polaris10_populate_vr_config(hwmgr, table);
- 	PP_ASSERT_WITH_CODE(0 == result,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0974-drm-amd-dal-Filter-HDMI-4k60-for-dce10.patch b/common/recipes-kernel/linux/files/0974-drm-amd-dal-Filter-HDMI-4k60-for-dce10.patch
deleted file mode 100644
index bf066ca4..00000000
--- a/common/recipes-kernel/linux/files/0974-drm-amd-dal-Filter-HDMI-4k60-for-dce10.patch
+++ /dev/null
@@ -1,400 +0,0 @@
-From 0e2f792c9b2feea587fd068e98c6204efc20619e Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Wed, 16 Mar 2016 13:44:46 -0400
-Subject: [PATCH 0974/1110] drm/amd/dal: Filter HDMI@4k60 for dce10
-
-Refactor code to use hdmi pixel clock maximums per dce
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce100/Makefile         |  2 +-
- .../drm/amd/dal/dc/dce100/dce100_link_encoder.c    | 89 ++++++++++++++++++++++
- .../drm/amd/dal/dc/dce100/dce100_link_encoder.h    | 42 ++++++++++
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  9 +--
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    | 32 +++-----
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  5 --
- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    |  5 --
- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c  |  5 ++
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  5 --
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  7 --
- drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h   |  4 +-
- 11 files changed, 153 insertions(+), 52 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
- create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-index 656c38e..5fb7e7b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
-@@ -2,7 +2,7 @@
- # Makefile for the 'controller' sub-component of DAL.
- # It provides the control and status of HW CRTC block.
- 
--DCE100 = dce100_resource.o dce100_hw_sequencer.o
-+DCE100 = dce100_resource.o dce100_hw_sequencer.o dce100_link_encoder.o
- 
- AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
-new file mode 100644
-index 0000000..5f294ee
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
-@@ -0,0 +1,89 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "core_types.h"
-+#include "dce100_link_encoder.h"
-+#include "stream_encoder.h"
-+#include "../dce110/dce110_link_encoder.h"
-+#include "i2caux_interface.h"
-+
-+/* TODO: change to dce80 header file */
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+#include "dce/dce_10_0_enum.h"
-+
-+#define LINK_REG(reg)\
-+	(enc110->link_regs->reg)
-+
-+#define DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 300000
-+
-+
-+static struct link_encoder_funcs dce100_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		dce110_link_encoder_validate_output_with_stream,
-+	.hw_init = dce110_link_encoder_hw_init,
-+	.setup = dce110_link_encoder_setup,
-+	.enable_tmds_output = dce110_link_encoder_enable_tmds_output,
-+	.enable_dp_output = dce110_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
-+	.disable_output = dce110_link_encoder_disable_output,
-+	.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		dce110_link_encoder_update_mst_stream_allocation_table,
-+	.set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
-+	.backlight_control = dce110_link_encoder_edp_backlight_control,
-+	.power_control = dce110_link_encoder_edp_power_control,
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
-+	.destroy = dce110_link_encoder_destroy
-+};
-+
-+bool dce100_link_encoder_construct(
-+		struct dce110_link_encoder *enc110,
-+		const struct encoder_init_data *init_data,
-+		const struct dce110_link_enc_registers *link_regs,
-+		const struct dce110_link_enc_aux_registers *aux_regs,
-+		const struct dce110_link_enc_bl_registers *bl_regs)
-+{
-+	dce110_link_encoder_construct(
-+			enc110,
-+			init_data,
-+			link_regs,
-+			aux_regs,
-+			bl_regs);
-+
-+	enc110->base.funcs = &dce100_lnk_enc_funcs;
-+
-+	enc110->base.features.flags.bits.IS_HBR3_CAPABLE = false;
-+	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = false;
-+
-+	enc110->base.features.max_hdmi_pixel_clock =
-+			DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-+	enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-+
-+	return true;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
-new file mode 100644
-index 0000000..ae0712f
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
-@@ -0,0 +1,42 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_ENCODER__DCE100_H__
-+#define __DC_LINK_ENCODER__DCE100_H__
-+
-+#include "link_encoder.h"
-+#include "../dce110/dce110_link_encoder.h"
-+
-+#define TO_DCE100_LINK_ENC(link_encoder)\
-+	container_of(link_encoder, struct dce100_link_encoder, base)
-+
-+bool dce100_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_bl_registers *bl_regs);
-+
-+#endif /* __DC_LINK_ENCODER__DCE100_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index a4dba58..5185e91 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -39,6 +39,7 @@
- #include "dce110/dce110_mem_input_v.h"
- #include "dce110/dce110_ipp.h"
- #include "dce110/dce110_transform.h"
-+#include "dce100/dce100_link_encoder.h"
- #include "dce110/dce110_stream_encoder.h"
- #include "dce110/dce110_opp.h"
- #include "dce110/dce110_clock_source.h"
-@@ -442,7 +443,7 @@ struct link_encoder *dce100_link_encoder_create(
- 	if (!enc110)
- 		return NULL;
- 
--	if (dce110_link_encoder_construct(
-+	if (dce100_link_encoder_construct(
- 			enc110,
- 			enc_init_data,
- 			&link_enc_regs[enc_init_data->transmitter],
-@@ -683,11 +684,6 @@ static void get_pixel_clock_parameters(
- 
- static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- {
--	/*TODO: unhardcode*/
--	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
--	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
--	pipe_ctx->max_hdmi_pixel_clock = 600000;
--
- 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
- 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
- 		pipe_ctx->clock_source,
-@@ -741,7 +737,6 @@ static enum dc_status validate_mapped_resource(
- 					return DC_FAIL_ENC_VALIDATE;
- 
- 				/* TODO: validate audio ASIC caps, encoder */
--
- 				status = dc_link_validate_mode_timing(stream->sink,
- 						link,
- 						&stream->public.timing);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 0e5588a..8da3e4d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -929,20 +929,13 @@ static bool validate_dvi_output(
- 
- static bool validate_hdmi_output(
- 	const struct dce110_link_encoder *enc110,
--	const struct dc_crtc_timing *crtc_timing,
--	uint32_t max_tmds_clk_from_edid_in_mhz,
--	enum dc_color_depth max_hdmi_deep_color,
--	uint32_t max_hdmi_pixel_clock)
-+	const struct dc_crtc_timing *crtc_timing)
- {
--	enum dc_color_depth max_deep_color = max_hdmi_deep_color;
-+	enum dc_color_depth max_deep_color =
-+			enc110->base.features.max_hdmi_deep_color;
- 	/* expressed in KHz */
- 	uint32_t pixel_clock = 0;
- 
--	/*TODO: unhardcode*/
--	max_tmds_clk_from_edid_in_mhz = 0;
--	max_hdmi_deep_color = COLOR_DEPTH_121212;
--	max_hdmi_pixel_clock = 600000;
--
- 	if (max_deep_color > enc110->base.features.max_deep_color)
- 		max_deep_color = enc110->base.features.max_deep_color;
- 
-@@ -972,12 +965,8 @@ static bool validate_hdmi_output(
- 	break;
- 	}
- 
--	if (max_tmds_clk_from_edid_in_mhz > 0)
--		if (pixel_clock > max_tmds_clk_from_edid_in_mhz * 1000)
--			return false;
--
- 	if ((pixel_clock == 0) ||
--		(pixel_clock > max_hdmi_pixel_clock) ||
-+		(pixel_clock > enc110->base.features.max_hdmi_pixel_clock) ||
- 		(pixel_clock > enc110->base.features.max_pixel_clock))
- 		return false;
- 
-@@ -1081,7 +1070,12 @@ bool dce110_link_encoder_construct(
- 	enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
- 
- 	enc110->base.features.max_pixel_clock =
--		DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+			MAX_ENCODER_CLK;
-+
-+	enc110->base.features.max_hdmi_pixel_clock =
-+			DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-+	enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
- 
- 	/* set the flag to indicate whether driver poll the I2C data pin
- 	 * while doing the DP sink detect
-@@ -1156,7 +1150,6 @@ bool dce110_link_encoder_construct(
- 
- 	/* test pattern 3 support */
- 	enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
--	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
- 
- 	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
- 		dal_adapter_service_is_feature_supported(
-@@ -1188,10 +1181,7 @@ bool dce110_link_encoder_validate_output_with_stream(
- 	case SIGNAL_TYPE_HDMI_TYPE_A:
- 		is_valid = validate_hdmi_output(
- 				enc110,
--				&stream->public.timing,
--				pipe_ctx->max_tmds_clk_from_edid_in_mhz,
--				pipe_ctx->max_hdmi_deep_color,
--				pipe_ctx->max_hdmi_pixel_clock);
-+				&stream->public.timing);
- 	break;
- 	case SIGNAL_TYPE_RGB:
- 		is_valid = validate_rgb_output(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index b8fc445..ccf6bd8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -630,11 +630,6 @@ static void get_pixel_clock_parameters(
- 
- static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- {
--	/*TODO: unhardcode*/
--	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
--	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
--	pipe_ctx->max_hdmi_pixel_clock = 600000;
--
- 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
- 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
- 		pipe_ctx->clock_source,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-index 420b8ca..7b3dee1 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-@@ -723,11 +723,6 @@ static void get_pixel_clock_parameters(
- 
- static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- {
--	/*TODO: unhardcode*/
--	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
--	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
--	pipe_ctx->max_hdmi_pixel_clock = 600000;
--
- 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
- 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
- 		pipe_ctx->clock_source,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-index e25fca2..4615c34 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-@@ -239,6 +239,11 @@ bool dce80_link_encoder_construct(
- 
- 	enc110->base.features.max_pixel_clock = DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
- 
-+	enc110->base.features.max_hdmi_pixel_clock =
-+			DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
-+	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-+	enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-+
- 	/* set the flag to indicate whether driver poll the I2C data pin
- 	 * while doing the DP sink detect
- 	 */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 311f5fa..56487fd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -641,11 +641,6 @@ static void get_pixel_clock_parameters(
- 
- static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- {
--	/*TODO: unhardcode*/
--	pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0;
--	pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212;
--	pipe_ctx->max_hdmi_pixel_clock = 600000;
--
- 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
- 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
- 		pipe_ctx->clock_source,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 4ec6192..14b62ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -303,13 +303,6 @@ struct pipe_ctx {
- 
- 	enum signal_type signal;
- 
--	/* timing validation (HDMI only) */
--	uint32_t max_tmds_clk_from_edid_in_mhz;
--	/* maximum supported deep color depth for HDMI */
--	enum dc_color_depth max_hdmi_deep_color;
--	/* maximum supported pixel clock for HDMI */
--	uint32_t max_hdmi_pixel_clock;
--
- 	struct pixel_clk_params pix_clk_params;
- 	struct pll_settings pll_settings;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-index 24d318d..115ef54 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-@@ -60,8 +60,10 @@ struct encoder_feature_support {
- 	} flags;
- 	/* maximum supported deep color depth */
- 	enum dc_color_depth max_deep_color;
-+	enum dc_color_depth max_hdmi_deep_color;
- 	/* maximum supported clock */
--	uint32_t max_pixel_clock;
-+	unsigned int max_pixel_clock;
-+	unsigned int max_hdmi_pixel_clock;
- };
- 
- struct link_enc_status {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0975-drm-amd-dal-Add-retry-mechanism-for-link-training.patch b/common/recipes-kernel/linux/files/0975-drm-amd-dal-Add-retry-mechanism-for-link-training.patch
deleted file mode 100644
index aa1fea72..00000000
--- a/common/recipes-kernel/linux/files/0975-drm-amd-dal-Add-retry-mechanism-for-link-training.patch
+++ /dev/null
@@ -1,131 +0,0 @@
-From fa0758869eb00cfbe31058880581bbcdfd0b6195 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 16 Mar 2016 15:29:35 -0400
-Subject: [PATCH 0975/1110] drm/amd/dal: Add retry mechanism for link training.
-
-On some displays the training sequence succeedes only
-after several consecutive tries.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c    |  6 +++-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 51 +++++++++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h  |  5 +--
- 3 files changed, 40 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index fd406f9..97d6f93 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1178,7 +1178,11 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
- 	if (link_settings.link_rate == LINK_RATE_LOW)
- 			skip_video_pattern = false;
- 
--	if (perform_link_training(link, &link_settings, skip_video_pattern)) {
-+	if (perform_link_training_with_retries(
-+			link,
-+			&link_settings,
-+			skip_video_pattern,
-+			3)) {
- 		link->public.cur_link_settings = link_settings;
- 		status = DC_OK;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 282a56b..8fe0314 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1040,6 +1040,31 @@ bool perform_link_training(
- 	return status;
- }
- 
-+
-+bool perform_link_training_with_retries(
-+	struct core_link *link,
-+	const struct dc_link_settings *link_setting,
-+	bool skip_video_pattern,
-+	unsigned int retires)
-+{
-+	uint8_t j;
-+	uint8_t delay_between_retries = 10;
-+
-+	for (j = 0; j < retires; ++j) {
-+
-+		if (perform_link_training(
-+				link,
-+				link_setting,
-+				skip_video_pattern))
-+			return true;
-+
-+		msleep(delay_between_retries);
-+		delay_between_retries += 10;
-+	}
-+
-+	return false;
-+}
-+
- /*TODO add more check to see if link support request link configuration */
- static bool is_link_setting_supported(
- 	const struct dc_link_settings *link_setting,
-@@ -1150,23 +1175,11 @@ bool dp_hbr_verify_link_cap(
- 		if (skip_link_training)
- 			success = true;
- 		else {
--			uint8_t num_retries = 3;
--			uint8_t j;
--			uint8_t delay_between_retries = 10;
--
--			for (j = 0; j < num_retries; ++j) {
--				success = perform_link_training(
--					link,
--					cur,
--					skip_video_pattern);
--
--				if (success)
--					break;
--
--				msleep(delay_between_retries);
--
--				delay_between_retries += 10;
--			}
-+			success = perform_link_training_with_retries(
-+								link,
-+								cur,
-+								skip_video_pattern,
-+								3);
- 		}
- 
- 		if (success)
-@@ -1527,8 +1540,8 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 	if (hpd_rx_irq_check_link_loss_status(
- 		link,
- 		&hpd_irq_dpcd_data)) {
--		perform_link_training(link,
--			&link->public.cur_link_settings, true);
-+		perform_link_training_with_retries(link,
-+			&link->public.cur_link_settings, true, 3);
- 		status = false;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-index a0ab6b3..b9fb8b9 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-@@ -42,10 +42,11 @@ void decide_link_settings(
- 	struct core_stream *stream,
- 	struct dc_link_settings *link_setting);
- 
--bool perform_link_training(
-+bool perform_link_training_with_retries(
- 	struct core_link *link,
- 	const struct dc_link_settings *link_setting,
--	bool skip_video_pattern);
-+	bool skip_video_pattern,
-+	unsigned int  retires);
- 
- bool is_mst_supported(struct core_link *link);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0976-drm-amd-dal-adjust-flip-clean-up-sequence-to-the-new.patch b/common/recipes-kernel/linux/files/0976-drm-amd-dal-adjust-flip-clean-up-sequence-to-the-new.patch
deleted file mode 100644
index 6221db4d..00000000
--- a/common/recipes-kernel/linux/files/0976-drm-amd-dal-adjust-flip-clean-up-sequence-to-the-new.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From 3100e9cd025b2fc77dde2b6cd0cd8a7f6faf33ad Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 15 Mar 2016 06:04:01 -0400
-Subject: [PATCH 0976/1110] drm/amd/dal: adjust flip clean-up sequence to the
- new code
-
-- This change fixes possible intermittent kernel exceptions
-during hotplug
-- It also fixes a segfault while changing modes with a
-DP-DVI active dongle on CZ
-- It also resolves an issue when resuming from S3 with MST
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 42 ----------------------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h      |  4 ---
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 22 ++++--------
- 3 files changed, 6 insertions(+), 62 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 5b3edb8..5626402 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1072,48 +1072,6 @@ static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
-  * Page Flip functions
-  ******************************************************************************/
- 
--void amdgpu_dm_flip_cleanup(
--	struct amdgpu_device *adev,
--	struct amdgpu_crtc *acrtc)
--{
--	int r;
--	unsigned long flags;
--	struct amdgpu_flip_work *works = NULL;
--
--	spin_lock_irqsave(&adev->ddev->event_lock, flags);
--	if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
--		works = acrtc->pflip_works;
--		acrtc->pflip_works = NULL;
--		acrtc->pflip_status = AMDGPU_FLIP_NONE;
--
--		if (works && works->event) {
--			drm_send_vblank_event(
--				adev->ddev,
--				acrtc->crtc_id,
--				works->event);
--		}
--		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
--
--		if (works) {
--			r = amdgpu_bo_reserve(works->old_rbo, false);
--			if (likely(r == 0)) {
--				r = amdgpu_bo_unpin(works->old_rbo);
--				if (unlikely(r != 0)) {
--					DRM_ERROR("failed to unpin buffer after flip\n");
--				}
--				amdgpu_bo_unreserve(works->old_rbo);
--			} else
--				DRM_ERROR("failed to reserve buffer after flip\n");
--
--			amdgpu_bo_unref(&works->old_rbo);
--			kfree(works->shared);
--			kfree(works);
--		}
--	} else {
--		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
--	}
--}
--
- /**
-  * dm_page_flip - called by amdgpu_flip_work_func(), which is triggered
-  * 			via DRM IOCTL, by user mode.
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 5674a82..34f1f9f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -156,10 +156,6 @@ bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm);
- /* Register "Backlight device" accessible by user-mode. */
- void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm);
- 
--void amdgpu_dm_flip_cleanup(
--	struct amdgpu_device *adev,
--	struct amdgpu_crtc *acrtc);
--
- extern const struct amd_ip_funcs amdgpu_dm_funcs;
- 
- void amdgpu_dm_update_connector_after_detect(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 8e7c491..80bf0f2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2071,27 +2071,17 @@ static void manage_dm_interrupts(
- 			&adev->pageflip_irq,
- 			irq_type);
- 	} else {
-+		while (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
-+			/* Spin Wait*/
-+
-+			/* Todo: Use periodic polling rather than busy wait */
-+		}
-+
- 		amdgpu_irq_put(
- 			adev,
- 			&adev->pageflip_irq,
- 			irq_type);
- 		drm_crtc_vblank_off(&acrtc->base);
--
--		/*
--		 * should be called here, to guarantee no works left in queue.
--		 * As this function sleeps it was bug to call it inside the
--		 * amdgpu_dm_flip_cleanup function under locked event_lock
--		 */
--		if (acrtc->pflip_works) {
--			flush_work(&acrtc->pflip_works->flip_work);
--			flush_work(&acrtc->pflip_works->unpin_work);
--		}
--
--		/*
--		 * this is the case when on reset, last pending pflip
--		 * interrupt did not not occur. Clean-up
--		 */
--		amdgpu_dm_flip_cleanup(adev, acrtc);
- 	}
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0977-drm-amd-dal-unhardcode-refresh-rate-for-pplib.patch b/common/recipes-kernel/linux/files/0977-drm-amd-dal-unhardcode-refresh-rate-for-pplib.patch
deleted file mode 100644
index c028653e..00000000
--- a/common/recipes-kernel/linux/files/0977-drm-amd-dal-unhardcode-refresh-rate-for-pplib.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 442eebcea42c660b5339c9856e34bde1d2e9a4cf Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 17 Mar 2016 11:18:42 -0400
-Subject: [PATCH 0977/1110] drm/amd/dal: unhardcode refresh rate for pplib
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c                         | 7 +++++--
- drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c | 2 +-
- 2 files changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 3f28446..011dbaf 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -599,8 +599,11 @@ static void fill_display_configs(
- 			default:
- 				break;
- 			}
--			/* TODO: unhardcode*/
--			cfg->v_refresh = 60;
-+			/* Round v_refresh*/
-+			cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
-+			cfg->v_refresh /= stream->public.timing.h_total;
-+			cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
-+						/ stream->public.timing.v_total;
- 		}
- 	}
- 	pp_display_cfg->display_count = num_cfgs;
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-index e559f95..875bf22 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-@@ -50,7 +50,7 @@ static struct state_dependent_clocks max_clks_by_state[] = {
- /*ClocksStateNominal*/
- { .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
- /*ClocksStatePerformance*/
--{ .display_clk_khz = 643000, .pixel_clk_khz = 4000000 } };
-+{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
- 
- /* Starting point for each divider range.*/
- enum divider_range_start {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0978-drm-amd-dal-fix-polaris-4-display-support.patch b/common/recipes-kernel/linux/files/0978-drm-amd-dal-fix-polaris-4-display-support.patch
deleted file mode 100644
index f606527d..00000000
--- a/common/recipes-kernel/linux/files/0978-drm-amd-dal-fix-polaris-4-display-support.patch
+++ /dev/null
@@ -1,353 +0,0 @@
-From f6e568e127c9fe58ae997c922116b9d3d6a57397 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 21 Mar 2016 18:18:07 -0400
-Subject: [PATCH 0978/1110] drm/amd/dal: fix polaris 4+ display support
-
-Add proper instancing of additional registers.
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   3 +
- .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c    | 303 +++++++++++++++++++++
- 2 files changed, 306 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 011dbaf..f3a59aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -785,6 +785,9 @@ bool dc_commit_surfaces_to_target(
- 	int new_enabled_surface_count = 0;
- 	bool is_mpo_turning_on = false;
- 
-+	if (core_dc->current_context.target_count == 0)
-+		return false;
-+
- 	context = dm_alloc(sizeof(struct validate_context));
- 
- 	resource_validate_ctx_copy_construct(&core_dc->current_context, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-index b94130f..0a7e82b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-@@ -36,6 +36,306 @@
- #include "dce/dce_11_2_d.h"
- #include "dce/dce_11_2_sh_mask.h"
- 
-+struct dce112_hw_seq_reg_offsets {
-+	uint32_t dcfe;
-+	uint32_t blnd;
-+	uint32_t crtc;
-+};
-+
-+enum pipe_lock_control {
-+	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
-+	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
-+	PIPE_LOCK_CONTROL_SCL = 1 << 2,
-+	PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
-+	PIPE_LOCK_CONTROL_MODE = 1 << 4
-+};
-+
-+enum blender_mode {
-+	BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
-+	BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
-+	BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
-+	BLENDER_MODE_STEREO
-+};
-+
-+static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.dcfe = (mmDCFE0_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
-+	.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.dcfe = (mmDCFE1_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
-+	.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.dcfe = (mmDCFE2_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
-+	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.dcfe = (mmDCFE3_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
-+	.blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.dcfe = (mmDCFE4_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
-+	.blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.dcfe = (mmDCFE5_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
-+	.blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_DCFE(reg, id)\
-+	(reg + reg_offsets[id].dcfe)
-+
-+#define HW_REG_BLND(reg, id)\
-+	(reg + reg_offsets[id].blnd)
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+/***************************PIPE_CONTROL***********************************/
-+static void dce112_enable_fe_clock(
-+	struct dc_context *ctx, uint8_t controller_id, bool enable)
-+{
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	addr = HW_REG_DCFE(mmDCFE_CLOCK_CONTROL, controller_id);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		enable,
-+		DCFE_CLOCK_CONTROL,
-+		DCFE_CLOCK_ENABLE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+/* this is a workaround for hw bug - it is a trigger on r/w */
-+static void trigger_write_crtc_h_blank_start_end(
-+	struct dc_context *ctx,
-+	uint8_t controller_id)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr =  HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id);
-+	value = dm_read_reg(ctx, addr);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static bool dce112_pipe_control_lock(
-+	struct dc_context *ctx,
-+	uint8_t controller_idx,
-+	uint32_t control_mask,
-+	bool lock)
-+{
-+	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+	bool need_to_wait = false;
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SCL)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_SCL_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_BLND_V_UPDATE_LOCK);
-+		need_to_wait = true;
-+	}
-+
-+	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-+		set_reg_field_value(
-+			value,
-+			lock,
-+			BLND_V_UPDATE_LOCK,
-+			BLND_V_UPDATE_LOCK_MODE);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	need_to_wait = false;/*todo: mpo optimization remove*/
-+	if (!lock && need_to_wait) {
-+		uint8_t counter = 0;
-+		const uint8_t counter_limit = 100;
-+		const uint16_t delay_us = 1000;
-+
-+		uint8_t pipe_pending;
-+
-+		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
-+				controller_idx);
-+
-+		while (counter < counter_limit) {
-+			value = dm_read_reg(ctx, addr);
-+
-+			pipe_pending = 0;
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						BLND_BLNDC_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					BLND_BLNDO_UPDATE_PENDING);
-+			}
-+
-+			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDC_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						SCL_BLNDO_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDC_GRPH_UPDATE_PENDING);
-+				pipe_pending |=
-+					get_reg_field_value(
-+						value,
-+						BLND_REG_UPDATE_STATUS,
-+						DCP_BLNDO_GRPH_UPDATE_PENDING);
-+			}
-+			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDC_GRPH_SURF_UPDATE_PENDING);
-+				pipe_pending |= get_reg_field_value(
-+					value,
-+					BLND_REG_UPDATE_STATUS,
-+					DCP_BLNDO_GRPH_SURF_UPDATE_PENDING);
-+			}
-+
-+			if (pipe_pending == 0)
-+				break;
-+
-+			counter++;
-+			udelay(delay_us);
-+		}
-+
-+		if (counter == counter_limit) {
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: wait for update exceeded (wait %d us)\n",
-+				__func__,
-+				counter * delay_us);
-+			dal_logger_write(
-+				ctx->logger,
-+				LOG_MAJOR_WARNING,
-+				LOG_MINOR_COMPONENT_CONTROLLER,
-+				"%s: control %d, remain value %x\n",
-+				__func__,
-+				control_mask,
-+				value);
-+		} else {
-+			/* OK. */
-+		}
-+	}
-+
-+	if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER))
-+		trigger_write_crtc_h_blank_start_end(ctx, controller_idx);
-+
-+	return true;
-+}
-+
-+static void dce112_set_blender_mode(
-+	struct dc_context *ctx,
-+	uint8_t controller_id,
-+	uint32_t mode)
-+{
-+	uint32_t value;
-+	uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
-+	uint32_t alpha_mode = 2;
-+	uint32_t blnd_mode = 0;
-+	uint32_t feedthrough = 1;
-+	uint32_t multiplied_mode = 0;
-+
-+	switch (mode) {
-+	case BLENDER_MODE_OTHER_PIPE:
-+		feedthrough = 0;
-+		alpha_mode = 0;
-+		blnd_mode = 1;
-+		break;
-+	case BLENDER_MODE_BLENDING:
-+		feedthrough = 0;
-+		alpha_mode = 0;
-+		blnd_mode = 2;
-+		multiplied_mode = 1;
-+		break;
-+	case BLENDER_MODE_CURRENT_PIPE:
-+	default:
-+		break;
-+	}
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		feedthrough,
-+		BLND_CONTROL,
-+		BLND_FEEDTHROUGH_EN);
-+	set_reg_field_value(
-+		value,
-+		alpha_mode,
-+		BLND_CONTROL,
-+		BLND_ALPHA_MODE);
-+	set_reg_field_value(
-+		value,
-+		blnd_mode,
-+		BLND_CONTROL,
-+		BLND_MODE);
-+	set_reg_field_value(
-+		value,
-+		multiplied_mode,
-+		BLND_CONTROL,
-+		BLND_MULTIPLIED_MODE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
- static void dce112_crtc_switch_to_clk_src(
- 				struct clock_source *clk_src, uint8_t crtc_inst)
- {
-@@ -172,6 +472,9 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
- 	dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
- 	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
- 	dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
-+	dc->hwss.pipe_control_lock = dce112_pipe_control_lock;
-+	dc->hwss.set_blender_mode = dce112_set_blender_mode;
-+	dc->hwss.enable_fe_clock = dce112_enable_fe_clock;
- 
- 	return true;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0979-drm-amd-dal-Fix-connector-set-property-for-DP-1.2-di.patch b/common/recipes-kernel/linux/files/0979-drm-amd-dal-Fix-connector-set-property-for-DP-1.2-di.patch
deleted file mode 100644
index 6ee2d775..00000000
--- a/common/recipes-kernel/linux/files/0979-drm-amd-dal-Fix-connector-set-property-for-DP-1.2-di.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 61014587118a10022315711c106dc69778ad995b Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 22 Mar 2016 14:57:33 -0400
-Subject: [PATCH 0979/1110] drm/amd/dal: Fix connector set property for DP 1.2
- displays
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index b0a82a2..7f3f8f2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -161,6 +161,7 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
- 	.fill_modes = drm_helper_probe_single_connector_modes,
- 	.destroy = dm_dp_mst_connector_destroy,
- 	.reset = amdgpu_dm_connector_funcs_reset,
-+	.set_property = drm_atomic_helper_connector_set_property,
- 	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
- 	.atomic_destroy_state = amdgpu_dm_connector_atomic_destroy_state,
- 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0980-drm-amd-dal-Implement-retreiving-crtc-scanoutpos-for.patch b/common/recipes-kernel/linux/files/0980-drm-amd-dal-Implement-retreiving-crtc-scanoutpos-for.patch
deleted file mode 100644
index e7e9f99b..00000000
--- a/common/recipes-kernel/linux/files/0980-drm-amd-dal-Implement-retreiving-crtc-scanoutpos-for.patch
+++ /dev/null
@@ -1,172 +0,0 @@
-From a0e3903311121fd5cd9e37ffe67bdf22ae77764d Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 22 Mar 2016 16:22:20 -0400
-Subject: [PATCH 0980/1110] drm/amd/dal: Implement retreiving crtc scanoutpos
- for drm
-
-This got missed in the DAL3 rewrite.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 13 ++++++++---
- drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 26 ++++++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/dc.h                    | 10 +++++++++
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |  5 +++--
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |  4 ++--
- .../drm/amd/dal/dc/dce80/dce80_timing_generator.c  |  1 +
- .../gpu/drm/amd/dal/dc/inc/hw/timing_generator.h   |  4 ++++
- 7 files changed, 56 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 5626402..5b92771 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -98,10 +98,17 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
- {
- 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
- 		return -EINVAL;
-+	else {
-+		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
-+
-+		if (NULL == acrtc->target) {
-+			DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc);
-+			return 0;
-+		}
-+
-+		return dc_target_get_scanoutpos(acrtc->target, vbl, position);
-+	}
- 
--/* TODO: #DAL3 Implement scanoutpos
--	dal_get_crtc_scanoutpos(adev->dm.dal, crtc, vbl, position);
--*/
- 	return 0;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-index 53bb64b..4b5504c 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
-@@ -257,6 +257,32 @@ uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
- 	return 0;
- }
- 
-+uint32_t dc_target_get_scanoutpos(
-+		const struct dc_target *dc_target,
-+		uint32_t *vbl,
-+		uint32_t *position)
-+{
-+	uint8_t i, j;
-+	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
-+	struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc);
-+	struct resource_context *res_ctx =
-+		&core_dc->current_context.res_ctx;
-+
-+	for (i = 0; i < target->public.stream_count; i++) {
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			struct timing_generator *tg = res_ctx->pipe_ctx[j].tg;
-+
-+			if (res_ctx->pipe_ctx[j].stream !=
-+				DC_STREAM_TO_CORE(target->public.streams[i]))
-+				continue;
-+
-+			return tg->funcs->get_scanoutpos(tg, vbl, position);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
- enum dc_irq_source dc_target_get_irq_src(
- 	const struct dc *dc,
- 	const struct dc_target *dc_target,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 348bb0d..5c2fe6d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -242,6 +242,16 @@ bool dc_target_is_connected_to_sink(
- uint8_t dc_target_get_controller_id(const struct dc_target *dc_target);
- 
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
-+
-+/* TODO: Return parsed values rather than direct register read
-+ * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
-+ * being refactored properly to be dce-specific
-+ */
-+uint32_t dc_target_get_scanoutpos(
-+		const struct dc_target *dc_target,
-+		uint32_t *vbl,
-+		uint32_t *position);
-+
- enum dc_irq_source dc_target_get_irq_src(
- 	const struct dc *dc,
- 	const struct dc_target *dc_target,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index a9ef65d..e4fe49a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -130,6 +130,7 @@ static struct timing_generator_funcs dce110_tg_funcs = {
- 		.is_counter_moving = dce110_timing_generator_is_counter_moving,
- 		.get_position = dce110_timing_generator_get_crtc_positions,
- 		.get_frame_count = dce110_timing_generator_get_vblank_counter,
-+		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
- 		.set_early_control = dce110_timing_generator_set_early_control,
- 		.wait_for_state = dce110_tg_wait_for_state,
- 		.set_blank = dce110_tg_set_blank,
-@@ -819,8 +820,8 @@ void dce110_timing_generator_get_crtc_positions(
-  */
- uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	struct timing_generator *tg,
--	int32_t *vbl,
--	int32_t *position)
-+	uint32_t *vbl,
-+	uint32_t *position)
- {
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 	/* TODO 1: Update the implementation once caller is updated
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 005f22b..7e01bde 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -193,8 +193,8 @@ void dce110_timing_generator_program_drr(
- 
- uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	struct timing_generator *tg,
--	int32_t *vbl,
--	int32_t *position);
-+	uint32_t *vbl,
-+	uint32_t *position);
- 
- void dce110_timing_generator_enable_advanced_request(
- 	struct timing_generator *tg,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-index 24c1832..e44e131 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
-@@ -124,6 +124,7 @@ static struct timing_generator_funcs dce80_tg_funcs = {
- 		.is_counter_moving = dce110_timing_generator_is_counter_moving,
- 		.get_position = dce110_timing_generator_get_crtc_positions,
- 		.get_frame_count = dce110_timing_generator_get_vblank_counter,
-+		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
- 		.set_early_control = dce110_timing_generator_set_early_control,
- 		.wait_for_state = dce110_tg_wait_for_state,
- 		.set_blank = dce110_tg_set_blank,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-index 25f2417..9347310 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-@@ -124,6 +124,10 @@ struct timing_generator_funcs {
- 								int32_t *h_position,
- 								int32_t *v_position);
- 	uint32_t (*get_frame_count)(struct timing_generator *tg);
-+	uint32_t (*get_scanoutpos)(
-+		struct timing_generator *tg,
-+		uint32_t *vbl,
-+		uint32_t *position);
- 	void (*set_early_control)(struct timing_generator *tg,
- 							   uint32_t early_cntl);
- 	void (*wait_for_state)(struct timing_generator *tg,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0981-drm-amd-dal-surface-is-shifted-to-the-left-with-DP-V.patch b/common/recipes-kernel/linux/files/0981-drm-amd-dal-surface-is-shifted-to-the-left-with-DP-V.patch
deleted file mode 100644
index 7c974d96..00000000
--- a/common/recipes-kernel/linux/files/0981-drm-amd-dal-surface-is-shifted-to-the-left-with-DP-V.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 6ffa3e3155d34fce1a5f71774c72f9ab259ff0ce Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Tue, 22 Mar 2016 13:14:19 -0400
-Subject: [PATCH 0981/1110] drm/amd/dal: surface is shifted to the left with
- DP->VGA
-
-Translate timing hor. and vert. sync polarity using flags from drm mode
-
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 80bf0f2..2f59c55 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -757,6 +757,11 @@ static void dc_timing_from_drm_display_mode(
- 		mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
- 	timing_out->pix_clk_khz = mode_in->crtc_clock;
- 	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
-+	if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
-+		timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
-+	if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
-+		timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
-+
- }
- 
- static void fill_audio_info(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0982-drm-amd-dal-Add-missing-BLND_CONTROL-and-CRTC_GSL-in.patch b/common/recipes-kernel/linux/files/0982-drm-amd-dal-Add-missing-BLND_CONTROL-and-CRTC_GSL-in.patch
deleted file mode 100644
index 80788f2b..00000000
--- a/common/recipes-kernel/linux/files/0982-drm-amd-dal-Add-missing-BLND_CONTROL-and-CRTC_GSL-in.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 9a351e72244629a059bbb74586e0a98163c41ec3 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 23 Mar 2016 11:29:28 -0400
-Subject: [PATCH 0982/1110] drm/amd/dal: Add missing BLND_CONTROL and CRTC_GSL
- instances.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index 0c17aa1..467f322 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -66,6 +66,18 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
- {
- 	.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
- 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
- }
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0983-drm-amd-dal-Implement-connectivity-log-output.patch b/common/recipes-kernel/linux/files/0983-drm-amd-dal-Implement-connectivity-log-output.patch
deleted file mode 100644
index 0edfde37..00000000
--- a/common/recipes-kernel/linux/files/0983-drm-amd-dal-Implement-connectivity-log-output.patch
+++ /dev/null
@@ -1,459 +0,0 @@
-From 4f6313afbf2678adc26831f856b68bbf6dfc3546 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 16 Mar 2016 11:11:52 -0400
-Subject: [PATCH 0983/1110] drm/amd/dal: Implement connectivity log output.
-
-message format:
-[time stamp]   [drm] [Major_minor] [connector name] message......
-eg:
-[   26.590965] [drm] [Conn_LKTN]  [DP-1] HBRx4 pass VS=0, PE=0^
-[   26.881060] [drm] [Conn_Mode]  [DP-1] {2560x1080, 2784x1111@185580Khz}^
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  | 51 ++++++++++++++++++
- drivers/gpu/drm/amd/dal/dc/basics/logger.c         | 11 +++-
- drivers/gpu/drm/amd/dal/dc/basics/logger.h         |  6 ++-
- drivers/gpu/drm/amd/dal/dc/core/dc.c               | 10 ++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  6 +++
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      | 61 +++++++++++-----------
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 35 ++++++++-----
- drivers/gpu/drm/amd/dal/dc/dm_helpers.h            | 39 ++++++++++++++
- drivers/gpu/drm/amd/dal/include/logger_types.h     | 13 +++++
- 9 files changed, 186 insertions(+), 46 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index 8688ca2..c6d6267 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -42,6 +42,12 @@
- 
- #include "dm_helpers.h"
- 
-+/* Maximum line char number for connectivity log,
-+ * in case of output EDID, needs at least 256x3 bytes plus some other
-+ * message, so set line size to 896.
-+ */
-+#define CONN_MAX_LINE_SIZE 896
-+
- /* dm_helpers_parse_edid_caps
-  *
-  * Parse edid caps
-@@ -513,3 +519,48 @@ bool dm_helpers_submit_i2c(
- 	return result;
- }
- 
-+void dm_helper_conn_log(struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint8_t *hex_data,
-+		int hex_data_count,
-+		enum conn_event event,
-+		const char *msg,
-+		...)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	struct drm_device *dev = adev->ddev;
-+	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-+	char buffer[CONN_MAX_LINE_SIZE] = { 0 };
-+	va_list args;
-+	int size;
-+	enum log_minor minor = event;
-+
-+	va_start(args, msg);
-+
-+	sprintf(buffer, "[%s] ", aconnector->base.name);
-+
-+	size = strlen(buffer);
-+
-+	size += dm_log_to_buffer(
-+		&buffer[size], CONN_MAX_LINE_SIZE, msg, args);
-+
-+	if (buffer[strlen(buffer) - 1] == '\n') {
-+		buffer[strlen(buffer) - 1] = '\0';
-+		size--;
-+	}
-+
-+	if (hex_data) {
-+		int i;
-+
-+		for (i = 0; i < hex_data_count; i++)
-+			sprintf(&buffer[size + i * 3], "%2.2X ", hex_data[i]);
-+	}
-+
-+	strcat(buffer, "^\n");
-+
-+	dal_logger_write(ctx->logger,
-+					LOG_MAJOR_CONNECTIVITY,
-+					minor,
-+					buffer);
-+	va_end(args);
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-index f637c3f..93d4185 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
-@@ -207,6 +207,14 @@ static const struct log_minor_info ds_minor_info_tbl[] = {
- 	{LOG_MINOR_DS_MODE_SETTING, "Mode_Setting"},
- };
- 
-+static const struct log_minor_info connectivity_minor_info_tbl[] = {
-+	{LOG_MINOR_CONNECTIVITY_MODE_SET,  "Mode"},
-+	{LOG_MINOR_CONNECTIVITY_DETECTION, "Detect"},
-+	{LOG_MINOR_CONNECTIVITY_LINK_TRAINING, "LKTN"},
-+	{LOG_MINOR_CONNECTIVITY_LINK_LOSS, "LinkLoss"},
-+	{LOG_MINOR_CONNECTIVITY_UNDERFLOW, "Underflow"},
-+};
-+
- struct log_major_mask_info {
- 	struct log_major_info major_info;
- 	uint32_t default_mask;
-@@ -270,6 +278,7 @@ static const struct log_major_mask_info log_major_mask_info_tbl[] = {
- 	{{LOG_MAJOR_DISPLAY_SERVICE, "DS"          }, LG_ALL_MSK, ds_minor_info_tbl,           NUM_ELEMENTS(ds_minor_info_tbl)},
- 	{{LOG_MAJOR_FEATURE_OVERRIDE, "FeatureOverride" }, LG_ALL_MSK, override_feature_minor_info_tbl, NUM_ELEMENTS(override_feature_minor_info_tbl)},
- 	{{LOG_MAJOR_DETECTION,       "Detection"   }, LG_ALL_MSK,  detection_minor_info_tbl,    NUM_ELEMENTS(detection_minor_info_tbl)},
-+	{{LOG_MAJOR_CONNECTIVITY,    "Conn"		   }, LG_ALL_MSK,  connectivity_minor_info_tbl, NUM_ELEMENTS(connectivity_minor_info_tbl)},
- };
- 
- /* ----------- Object init and destruction ----------- */
-@@ -511,7 +520,7 @@ static void log_to_internal_buffer(struct log_entry *entry)
- 
- static void log_timestamp(struct log_entry *entry)
- {
--	dal_logger_append(entry, "00:00:00 ");
-+/*	dal_logger_append(entry, "00:00:00 ");*/
- }
- 
- static void log_major_minor(struct log_entry *entry)
-diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.h b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-index c2aea53..12d8ae6 100644
---- a/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
-@@ -29,7 +29,11 @@
- /* Structure for keeping track of offsets, buffer, etc */
- 
- #define DAL_LOGGER_BUFFER_MAX_SIZE 2048
--#define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 256
-+
-+/*Connectivity log needs to output EDID, which needs at lease 256x3 bytes,
-+ * change log line size to 896 to meet the request.
-+ */
-+#define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 896
- 
- #include "include/logger_types.h"
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index f3a59aa..da50d25 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -46,6 +46,7 @@
- #include "link_encoder.h"
- 
- #include "dc_link_ddc.h"
-+#include "dm_helpers.h"
- 
- /*******************************************************************************
-  * Private structures
-@@ -747,8 +748,17 @@ bool dc_commit_targets(
- 
- 	for (i = 0; i < context->target_count; i++) {
- 		struct dc_target *dc_target = &context->targets[i]->public;
-+		struct core_sink *sink = DC_SINK_TO_CORE(dc_target->streams[0]->sink);
-+
- 		if (context->target_status[i].surface_count > 0)
- 			target_enable_memory_requests(dc_target, &core_dc->current_context.res_ctx);
-+
-+		CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
-+				dc_target->streams[0]->timing.h_addressable,
-+				dc_target->streams[0]->timing.v_addressable,
-+				dc_target->streams[0]->timing.h_total,
-+				dc_target->streams[0]->timing.v_total,
-+				dc_target->streams[0]->timing.pix_clk_khz);
- 	}
- 
- 	program_timing_sync(core_dc, context);
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 97d6f93..06c8fa6 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -679,6 +679,12 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 			break;
- 		}
- 
-+		/* Connectivity log: detection */
-+		CONN_DATA_DETECT(link, sink->public.dc_edid.raw_edid,
-+				sink->public.dc_edid.length,
-+				"%s: ",
-+				sink->public.edid_caps.display_name);
-+
- 		dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_DETECTION,
- 			LOG_MINOR_DETECTION_EDID_PARSER,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index 698a34e..c38e60e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -768,12 +768,12 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
- 		DP_HDMI_DONGLE_ADDRESS,
- 		type2_dongle_buf,
- 		sizeof(type2_dongle_buf))) {
--		dal_logger_write(ddc->ctx->logger,
--			LOG_MAJOR_DCS,
--			LOG_MINOR_DCS_DONGLE_DETECTION,
--			"Detected DP-DVI dongle.\n");
- 		*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
- 		sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
-+
-+		CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
-+				"DP-DVI passive dongle %dMhz: ",
-+				DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
- 		return;
- 	}
- 
-@@ -815,29 +815,28 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
- 		if (0 == max_tmds_clk ||
- 				max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
- 				max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
--			dal_logger_write(ddc->ctx->logger,
--				LOG_MAJOR_DCS,
--				LOG_MINOR_DCS_DONGLE_DETECTION,
--				"Invalid Maximum TMDS clock");
- 			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+
-+			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+					sizeof(type2_dongle_buf),
-+					"DP-DVI passive dongle %dMhz: ",
-+					DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
- 		} else {
- 			if (is_valid_hdmi_signature == true) {
- 				*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
--				dal_logger_write(ddc->ctx->logger,
--					LOG_MAJOR_DCS,
--					LOG_MINOR_DCS_DONGLE_DETECTION,
--					"Detected Type 2 DP-HDMI Maximum TMDS "
--					"clock, max TMDS clock: %d MHz",
--					max_tmds_clk);
-+
-+				CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+						sizeof(type2_dongle_buf),
-+						"Type 2 DP-HDMI passive dongle %dMhz: ",
-+						max_tmds_clk);
- 			} else {
- 				*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
--				dal_logger_write(ddc->ctx->logger,
--					LOG_MAJOR_DCS,
--					LOG_MINOR_DCS_DONGLE_DETECTION,
--					"Detected Type 2 DP-HDMI (no valid HDMI"
--					" signature) Maximum TMDS clock, max "
--					"TMDS clock: %d MHz",
--					max_tmds_clk);
-+
-+				CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+						sizeof(type2_dongle_buf),
-+						"Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
-+						max_tmds_clk);
-+
- 			}
- 
- 			/* Multiply by 1000 to convert to kHz. */
-@@ -847,19 +846,19 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
- 
- 	} else {
- 		if (is_valid_hdmi_signature == true) {
--			dal_logger_write(ddc->ctx->logger,
--				LOG_MAJOR_DCS,
--				LOG_MINOR_DCS_DONGLE_DETECTION,
--				"Detected Type 1 DP-HDMI dongle.\n");
- 			*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
--		} else {
--			dal_logger_write(ddc->ctx->logger,
--				LOG_MAJOR_DCS,
--				LOG_MINOR_DCS_DONGLE_DETECTION,
--				"Detected Type 1 DP-HDMI dongle (no valid HDMI "
--				"signature).\n");
- 
-+			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+					sizeof(type2_dongle_buf),
-+					"Type 1 DP-HDMI passive dongle %dMhz: ",
-+					sink_cap->max_hdmi_pixel_clock / 1000);
-+		} else {
- 			*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+
-+			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+					sizeof(type2_dongle_buf),
-+					"Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
-+					sink_cap->max_hdmi_pixel_clock / 1000);
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index 8fe0314..c83a754 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1009,33 +1009,31 @@ bool perform_link_training(
- 	switch (lt_settings.link_settings.link_rate) {
- 
- 	case LINK_RATE_LOW:
--		link_rate = "Low";
-+		link_rate = "RBR";
- 		break;
- 	case LINK_RATE_HIGH:
--		link_rate = "High";
-+		link_rate = "HBR";
- 		break;
- 	case LINK_RATE_HIGH2:
--		link_rate = "High2";
-+		link_rate = "HBR2";
- 		break;
- 	case LINK_RATE_RBR2:
- 		link_rate = "RBR2";
- 		break;
- 	case LINK_RATE_HIGH3:
--		link_rate = "High3";
-+		link_rate = "HBR3";
- 		break;
- 	default:
- 		break;
- 	}
- 
--	dal_logger_write(link->ctx->logger,
--		LOG_MAJOR_MST,
--		LOG_MINOR_MST_PROGRAMMING,
--		"Link training for %d lanes at %s rate %s with PE %d, VS %d\n",
--		lt_settings.link_settings.lane_count,
--		link_rate,
--		status ? "succeeded" : "failed",
--		lt_settings.lane_settings[0].PRE_EMPHASIS,
--		lt_settings.lane_settings[0].VOLTAGE_SWING);
-+	/* Connectivity log: link training */
-+	CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
-+			link_rate,
-+			lt_settings.link_settings.lane_count,
-+			status ? "pass" : "fail",
-+			lt_settings.lane_settings[0].VOLTAGE_SWING,
-+			lt_settings.lane_settings[0].PRE_EMPHASIS);
- 
- 	return status;
- }
-@@ -1540,8 +1538,15 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 	if (hpd_rx_irq_check_link_loss_status(
- 		link,
- 		&hpd_irq_dpcd_data)) {
-+		/* Connectivity log: link loss */
-+		CONN_DATA_LINK_LOSS(link,
-+							hpd_irq_dpcd_data.raw,
-+							sizeof(hpd_irq_dpcd_data),
-+							"Status: ");
-+
- 		perform_link_training_with_retries(link,
- 			&link->public.cur_link_settings, true, 3);
-+
- 		status = false;
- 	}
- 
-@@ -1794,6 +1799,10 @@ static void retrieve_link_cap(struct core_link *link)
- 			(uint8_t *)(&link->edp_revision),
- 			sizeof(link->edp_revision));
- 	}
-+
-+	/* Connectivity log: detection */
-+	CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
-+
- 	/* TODO: Confirm if need retrieve_psr_link_cap */
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-index 350dd11..151c1ef 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
-@@ -35,11 +35,42 @@
- 
- struct dp_mst_stream_allocation_table;
- 
-+enum conn_event {
-+	CONN_EVENT_MODE_SET,
-+	CONN_EVENT_DETECTION,
-+	CONN_EVENT_LINK_TRAINING,
-+	CONN_EVENT_LINK_LOSS,
-+	CONN_EVENT_UNDERFLOW,
-+};
-+
- enum dc_edid_status dm_helpers_parse_edid_caps(
- 	struct dc_context *ctx,
- 	const struct dc_edid *edid,
- 	struct dc_edid_caps *edid_caps);
- 
-+
-+/* Connectivity log format:
-+ * [time stamp]   [drm] [Major_minor] [connector name] message.....
-+ * eg:
-+ * [   26.590965] [drm] [Conn_LKTN]	  [DP-1] HBRx4 pass VS=0, PE=0^
-+ * [   26.881060] [drm] [Conn_Mode]	  [DP-1] {2560x1080, 2784x1111@185580Khz}^
-+ */
-+
-+#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \
-+		dm_helper_conn_log(link->ctx, &link->public, hex_data, hex_len, \
-+				CONN_EVENT_DETECTION, ##__VA_ARGS__)
-+
-+#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \
-+		dm_helper_conn_log(link->ctx, &link->public, hex_data, hex_len, \
-+				CONN_EVENT_LINK_LOSS, ##__VA_ARGS__)
-+
-+#define CONN_MSG_LT(link, ...) \
-+		dm_helper_conn_log(link->ctx, &link->public, NULL, 0, \
-+				CONN_EVENT_LINK_TRAINING, ##__VA_ARGS__)
-+
-+#define CONN_MSG_MODE(link, ...) \
-+		dm_helper_conn_log(link->ctx, &link->public, NULL, 0, \
-+				CONN_EVENT_MODE_SET, ##__VA_ARGS__)
- /*
-  * Writes payload allocation table in immediate downstream device.
-  */
-@@ -100,4 +131,12 @@ bool dm_helpers_submit_i2c(
- 		const struct dc_link *link,
- 		struct i2c_command *cmd);
- 
-+void dm_helper_conn_log(struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint8_t *hex_data,
-+		int hex_data_count,
-+		enum conn_event event,
-+		const char *msg,
-+		...);
-+
- #endif /* __DM_HELPERS__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
-index 759542a..26960e8 100644
---- a/drivers/gpu/drm/amd/dal/include/logger_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
-@@ -65,6 +65,7 @@ enum log_major {
- /*23*/  LOG_MAJOR_DISPLAY_SERVICE, /*< related to Display Service*/
- /*24*/	LOG_MAJOR_FEATURE_OVERRIDE,	/*< related to features*/
- /*25*/	LOG_MAJOR_DETECTION,	/*< related to detection*/
-+/*26*/	LOG_MAJOR_CONNECTIVITY,	/*< related to connectivity*/
- 	LOG_MAJOR_COUNT,	/*< count of the Major categories*/
- };
- 
-@@ -311,6 +312,18 @@ enum log_minor {
- */
- 	LOG_MINOR_DETECTION_EDID_PARSER = 0,
- 	LOG_MINOR_DETECTION_DP_CAPS,
-+
-+/**
-+* @brief defines minor category for LOG_MAJOR_CONNECTIVITY
-+*
-+* @note define sub functionality related to connectivity
-+*/
-+	LOG_MINOR_CONNECTIVITY_MODE_SET = 0,
-+	LOG_MINOR_CONNECTIVITY_DETECTION,
-+	LOG_MINOR_CONNECTIVITY_LINK_TRAINING,
-+	LOG_MINOR_CONNECTIVITY_LINK_LOSS,
-+	LOG_MINOR_CONNECTIVITY_UNDERFLOW,
-+
- };
- 
- union logger_flags {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0984-drm-amd-dal-fix-headless-hotplug-for-MST.patch b/common/recipes-kernel/linux/files/0984-drm-amd-dal-fix-headless-hotplug-for-MST.patch
deleted file mode 100644
index d32658ba..00000000
--- a/common/recipes-kernel/linux/files/0984-drm-amd-dal-fix-headless-hotplug-for-MST.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From c53d5370b35d53f5fdf05830e507d5365657fa9c Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 22 Mar 2016 18:27:11 -0400
-Subject: [PATCH 0984/1110] drm/amd/dal: fix headless hotplug for MST
-
-This mirrors the fix to handle the non-MST case for xinit
-when there's no desktop manager calling mode set for us.
-
-This will allow MST to work in the case of going to headless
-state then plug back in the same configuration (be it one MST
-capable display or a daisy chain), which was broken by the
-xinit fix before. This will also allow MST displays to light
-up from hotplug in xinit environment, which was not supported
-before.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    | 74 ++++++++++++----------
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 11 +++-
- 2 files changed, 47 insertions(+), 38 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 7f3f8f2..c00c4d1 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -225,43 +225,8 @@ fail_add_sink:
- static int dm_dp_mst_get_modes(struct drm_connector *connector)
- {
- 	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
--	struct amdgpu_connector *master = aconnector->mst_port;
--	struct edid *edid;
--	const struct dc_sink *sink;
- 	int ret = 0;
- 
--	if (!aconnector->edid) {
--		edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, aconnector->port);
--
--		if (!edid) {
--			drm_mode_connector_update_edid_property(
--				&aconnector->base,
--				NULL);
--
--			return ret;
--		}
--
--		aconnector->edid = edid;
--
--		if (aconnector->dc_sink)
--			dc_link_remove_remote_sink(
--				aconnector->dc_link,
--				aconnector->dc_sink);
--
--		sink = dm_dp_mst_add_mst_sink(
--			aconnector->dc_link,
--			(uint8_t *)edid,
--			(edid->extensions + 1) * EDID_LENGTH);
--		aconnector->dc_sink = sink;
--	} else
--		edid = aconnector->edid;
--
--	DRM_DEBUG_KMS("edid retrieved %p\n", edid);
--
--	drm_mode_connector_update_edid_property(
--		&aconnector->base,
--		aconnector->edid);
--
- 	ret = drm_add_edid_modes(&aconnector->base, aconnector->edid);
- 
- 	drm_edid_to_eld(&aconnector->base, aconnector->edid);
-@@ -417,6 +382,45 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
- 	struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr);
- 	struct drm_device *dev = master->base.dev;
- 	struct amdgpu_device *adev = dev->dev_private;
-+	struct drm_connector *connector;
-+	struct amdgpu_connector *aconnector;
-+	struct edid *edid;
-+	const struct dc_sink *sink;
-+
-+	drm_modeset_lock_all(dev);
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_connector(connector);
-+		if (aconnector->mst_port && !aconnector->dc_sink) {
-+			if (!aconnector->edid) {
-+				edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
-+
-+				if (!edid) {
-+					drm_mode_connector_update_edid_property(
-+						&aconnector->base,
-+						NULL);
-+					continue;
-+				}
-+
-+				aconnector->edid = edid;
-+
-+				sink = dm_dp_mst_add_mst_sink(
-+					aconnector->dc_link,
-+					(uint8_t *)edid,
-+					(edid->extensions + 1) * EDID_LENGTH);
-+				aconnector->dc_sink = sink;
-+
-+				dm_restore_drm_connector_state(connector->dev, connector);
-+			} else
-+				edid = aconnector->edid;
-+
-+			DRM_DEBUG_KMS("edid retrieved %p\n", edid);
-+
-+			drm_mode_connector_update_edid_property(
-+				&aconnector->base,
-+				aconnector->edid);
-+		}
-+	}
-+	drm_modeset_unlock_all(dev);
- 
- 	schedule_work(&adev->dm.mst_hotplug_work);
- }
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 2f59c55..e418422 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2347,15 +2347,18 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 	struct amdgpu_device *adev = dev->dev_private;
- 	struct dc *dc = adev->dm.dc;
- 	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
--	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->state->crtc);
-+	struct amdgpu_crtc *disconnected_acrtc;
- 	const struct dc_sink *sink;
- 	struct dc_target *commit_targets[6];
- 	uint32_t commit_targets_count = 0;
- 
--	if (!aconnector->dc_sink || !connector->state || !connector->state->crtc)
-+
-+	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
- 		return;
- 
--	if (!disconnected_acrtc->target)
-+	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
-+
-+	if (!disconnected_acrtc || !disconnected_acrtc->target)
- 		return;
- 
- 	sink = disconnected_acrtc->target->streams[0]->sink;
-@@ -2370,6 +2373,8 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 			create_target_for_sink(
- 				aconnector,
- 				&disconnected_acrtc->base.state->mode);
-+
-+		DRM_INFO("Headless hotplug, restoring connector state\n");
- 		/*
- 		 * we evade vblanks and pflips on crtc that
- 		 * should be changed
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0985-drm-amd-dal-fix-DP-active-dongle-downstream-hotplug.patch b/common/recipes-kernel/linux/files/0985-drm-amd-dal-fix-DP-active-dongle-downstream-hotplug.patch
deleted file mode 100644
index 98cd472a..00000000
--- a/common/recipes-kernel/linux/files/0985-drm-amd-dal-fix-DP-active-dongle-downstream-hotplug.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 2a11ba7d7d21b80cd1d7a362ca2ca401fc3b34dd Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Wed, 23 Mar 2016 18:49:12 -0400
-Subject: [PATCH 0985/1110] drm/amd/dal: fix DP active dongle downstream
- hotplug
-
-handle_hpd_rx_irq need the same headless fix as handle_hpd_irq
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 5b92771..038dea4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -730,6 +730,11 @@ static void handle_hpd_rx_irq(void *param)
- 		/* Downstream Port status changed. */
- 		if (dc_link_detect(aconnector->dc_link, false)) {
- 			amdgpu_dm_update_connector_after_detect(aconnector);
-+
-+			drm_modeset_lock_all(dev);
-+			dm_restore_drm_connector_state(dev, connector);
-+			drm_modeset_unlock_all(dev);
-+
- 			drm_kms_helper_hotplug_event(dev);
- 		}
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0986-drm-amd-dal-Switch-from-busy-wait-to-sleep-when-wait.patch b/common/recipes-kernel/linux/files/0986-drm-amd-dal-Switch-from-busy-wait-to-sleep-when-wait.patch
deleted file mode 100644
index ffe639f0..00000000
--- a/common/recipes-kernel/linux/files/0986-drm-amd-dal-Switch-from-busy-wait-to-sleep-when-wait.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 70ca0bbe4defb86434f0f5d1173ba9ef57cbf8b9 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Tue, 29 Mar 2016 11:17:58 -0400
-Subject: [PATCH 0986/1110] drm/amd/dal: Switch from busy wait to sleep when
- waiting for pflip comletion.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index e418422..f79cbee 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2077,9 +2077,7 @@ static void manage_dm_interrupts(
- 			irq_type);
- 	} else {
- 		while (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
--			/* Spin Wait*/
--
--			/* Todo: Use periodic polling rather than busy wait */
-+			msleep(1);
- 		}
- 
- 		amdgpu_irq_put(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0987-drm-amd-dal-Pattern-for-freesync-module-implementati.patch b/common/recipes-kernel/linux/files/0987-drm-amd-dal-Pattern-for-freesync-module-implementati.patch
deleted file mode 100644
index 5ad67ce5..00000000
--- a/common/recipes-kernel/linux/files/0987-drm-amd-dal-Pattern-for-freesync-module-implementati.patch
+++ /dev/null
@@ -1,294 +0,0 @@
-From b41e2d348c8fb3df94d5d358c27c008a63f979e7 Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Wed, 23 Mar 2016 11:26:03 -0400
-Subject: [PATCH 0987/1110] drm/amd/dal: Pattern for freesync module
- implementation in DC/DM
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc.h                    |  18 +++-
- .../gpu/drm/amd/dal/modules/freesync/freesync.c    | 106 +++++++++++++++++++++
- .../gpu/drm/amd/dal/modules/freesync/freesync.h    |  41 ++++++++
- drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h |  64 +++++++++++++
- 4 files changed, 225 insertions(+), 4 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
- create mode 100644 drivers/gpu/drm/amd/dal/modules/freesync/freesync.h
- create mode 100644 drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 5c2fe6d..13fa582 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -40,13 +40,22 @@
-  ******************************************************************************/
- 
- struct dc_caps {
--    uint32_t max_targets;
--    uint32_t max_links;
--    uint32_t max_audios;
-+	uint32_t max_targets;
-+	uint32_t max_links;
-+	uint32_t max_audios;
-+};
-+
-+struct dc;
-+struct dc_surface;
-+
-+struct dc_stream_funcs {
-+	bool (*dc_stream_adjust_vmin_vmax)(struct dc *dc,
-+			struct dc_stream *stream, int vmin, int vmax);
- };
- 
- struct dc {
- 	struct dc_caps caps;
-+	struct dc_stream_funcs stream_funcs;
- };
- 
- struct dc_init_data {
-@@ -302,10 +311,11 @@ struct dc_stream {
- 
- 	struct audio_info audio_info;
- 
-+	bool enable_freesync;
-+
- 	/* TODO: dithering */
- 	/* TODO: transfer function (CSC/regamma/gamut remap) */
- 	/* TODO: custom INFO packets */
--	/* TODO: DRR/Freesync parameters */
- 	/* TODO: ABM info (DMCU) */
- 	/* TODO: PSR info */
- 	/* TODO: CEA VIC */
-diff --git a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-new file mode 100644
-index 0000000..d0113d5
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-@@ -0,0 +1,106 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "freesync.h"
-+#include "dm_services.h"
-+#include "dc.h"
-+
-+static bool check_dc_support(const struct dc *dc)
-+{
-+	if (dc->stream_funcs.dc_stream_adjust_vmin_vmax == NULL)
-+		return false;
-+
-+	return true;
-+}
-+
-+struct mod_freesync *mod_freesync_create(struct dc *dc)
-+{
-+	struct core_freesync *core_freesync = dm_alloc(sizeof(struct core_freesync));
-+
-+	if (core_freesync == NULL)
-+		goto fail_alloc_context;
-+
-+	if (dc == NULL)
-+		goto fail_construct;
-+
-+	core_freesync->dc = dc;
-+
-+	if (!check_dc_support(dc))
-+		goto fail_construct;
-+
-+	return &core_freesync->public;
-+
-+fail_construct:
-+	dm_free(core_freesync);
-+
-+fail_alloc_context:
-+	return NULL;
-+}
-+
-+void mod_freesync_destroy(struct mod_freesync *mod_freesync)
-+{
-+	if (mod_freesync != NULL) {
-+		struct core_freesync *core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+		dm_free(core_freesync);
-+	}
-+}
-+
-+bool mod_freesync_set_freesync_on_streams(struct mod_freesync *mod_freesync,
-+		struct dc_stream **streams,	int num_streams,
-+		struct mod_freesync_params *params)
-+{
-+	int v_total_nominal = 0;
-+	int i = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (num_streams == 0 || streams == NULL || mod_freesync == NULL
-+			|| params == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	if (params->mode == FREESYNC_MODE_DISABLED)	{
-+		/* Disable freesync */
-+		for (i = 0; i < num_streams; i++) {
-+			v_total_nominal = streams[i]->timing.v_total;
-+
-+			core_freesync->dc->stream_funcs.dc_stream_adjust_vmin_vmax(core_freesync->dc,
-+					streams[i], v_total_nominal, v_total_nominal);
-+		}
-+
-+		return true;
-+	} else if (params->mode == FREESYNC_MODE_VARIABLE) {
-+		/* Enable freesync */
-+	}
-+
-+	return false;
-+}
-+
-+void mod_freesync_vupdate_callback(struct mod_freesync *mod_freesync,
-+		struct dc_stream *stream)
-+{
-+
-+}
-diff --git a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.h b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.h
-new file mode 100644
-index 0000000..65a4194
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.h
-@@ -0,0 +1,41 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef FREESYNC_H_
-+#define FREESYNC_H_
-+
-+#include "mod_freesync.h"
-+
-+struct dc;
-+
-+struct core_freesync {
-+	struct mod_freesync public;
-+	struct dc *dc;
-+};
-+
-+#define MOD_FREESYNC_TO_CORE(mod_freesync)\
-+	container_of(mod_freesync, struct core_freesync, public)
-+
-+#endif /* FREESYNC_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h
-new file mode 100644
-index 0000000..e12d844
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef MOD_FREESYNC_H_
-+#define MOD_FREESYNC_H_
-+
-+#include "dm_services.h"
-+
-+struct mod_freesync {
-+	int dummy;
-+};
-+
-+enum mod_freesync_mode {
-+	FREESYNC_MODE_DISABLED,
-+	FREESYNC_MODE_FIXED,
-+	FREESYNC_MODE_VARIABLE,
-+};
-+
-+struct mod_freesync_params {
-+	enum mod_freesync_mode mode;
-+};
-+
-+struct mod_freesync *mod_freesync_create(struct dc *dc);
-+void mod_freesync_destroy(struct mod_freesync *mod_freesync);
-+
-+/*
-+ * This interface sets the freesync mode on a stream.  Mode and associated
-+ * parameters required to set it are defined in mod_freesync_params.
-+ */
-+bool mod_freesync_set_freesync_on_streams(struct mod_freesync *mod_freesync,
-+		struct dc_stream **streams, int num_streams,
-+		struct mod_freesync_params *params);
-+
-+/*
-+ * This interface must be called for on every VUPDATE event for every stream
-+ * which is not FREESYNC_MODE_DISABLED.  Calling this for a stream that is in
-+ * FREESYNC_MODE_DISABLED has no effect.
-+ */
-+void mod_freesync_vupdate_callback(struct mod_freesync *mod_freesync,
-+	struct dc_stream *stream);
-+
-+#endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0988-drm-amd-dal-Fix-clock-source-remapping-issue-when-DR.patch b/common/recipes-kernel/linux/files/0988-drm-amd-dal-Fix-clock-source-remapping-issue-when-DR.patch
deleted file mode 100644
index adc167be..00000000
--- a/common/recipes-kernel/linux/files/0988-drm-amd-dal-Fix-clock-source-remapping-issue-when-DR.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From 21ae403b786fa9b0d156f58ba2a058d72364a537 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Tue, 29 Mar 2016 15:33:52 -0400
-Subject: [PATCH 0988/1110] drm/amd/dal: Fix clock source remapping issue when
- DRM swaps crtcs
-
-When disabling and enabling monitors in a specific order, eventually we'll get
-to a point where the clock sources will be swapped.
-
-BIOS appears to have an optimization where the updated phy on enable_output
-doesn't take affect if it hasn't been disabled.
-
-To fix this, reset the pipe if the clock sources change.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   5 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 114 +++++++++++----------
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   2 -
- 3 files changed, 61 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index da50d25..7d234cf 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -740,10 +740,7 @@ bool dc_commit_targets(
- 	}
- 
- 	if (result == DC_OK) {
--		core_dc->hwss.reset_hw_ctx(core_dc, context);
--
--		if (context->target_count > 0)
--			result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
-+		result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
- 	}
- 
- 	for (i = 0; i < context->target_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index a21fcbd..fa282c0 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1224,6 +1224,43 @@ static void switch_dp_clock_sources(
-  * Public functions
-  ******************************************************************************/
- 
-+
-+static void reset_single_pipe_hw_ctx(
-+		const struct core_dc *dc,
-+		struct pipe_ctx *pipe_ctx,
-+		struct validate_context *context)
-+{
-+	struct dc_bios *dcb;
-+
-+	if (pipe_ctx->pipe_idx == DCE110_UNDERLAY_IDX)
-+		return;
-+
-+	dcb = dal_adapter_service_get_bios_parser(
-+			context->res_ctx.pool.adapter_srv);
-+	if (pipe_ctx->audio) {
-+		dal_audio_disable_output(pipe_ctx->audio,
-+				pipe_ctx->stream_enc->id,
-+				pipe_ctx->signal);
-+		pipe_ctx->audio = NULL;
-+	}
-+
-+	core_link_disable_stream(pipe_ctx);
-+	if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
-+		dm_error("DC: failed to blank crtc!\n");
-+		BREAK_TO_DEBUGGER();
-+	}
-+	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
-+	pipe_ctx->mi->funcs->free_mem_input(
-+				pipe_ctx->mi, context->target_count);
-+	pipe_ctx->xfm->funcs->transform_set_scaler_bypass(pipe_ctx->xfm);
-+	resource_unreference_clock_source(&context->res_ctx, pipe_ctx->clock_source);
-+	dc->hwss.enable_display_power_gating(
-+		pipe_ctx->stream->ctx, pipe_ctx->pipe_idx, dcb,
-+			PIPE_GATING_CONTROL_ENABLE);
-+
-+	pipe_ctx->stream = NULL;
-+}
-+
- /*TODO: const validate_context*/
- static enum dc_status apply_ctx_to_hw(
- 		struct core_dc *dc,
-@@ -1232,6 +1269,29 @@ static enum dc_status apply_ctx_to_hw(
- 	enum dc_status status;
- 	uint8_t i;
- 
-+	/* Reset old context */
-+	/* look up the targets that have been removed since last commit */
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+			&dc->current_context.res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		/* Note: We need to disable output if clock sources change,
-+		 * since bios does optimization and doesn't apply if changing
-+		 * PHY when not already disabled.
-+		 */
-+		if (pipe_ctx_old->stream && pipe_ctx_old->stream != pipe_ctx->stream)
-+			reset_single_pipe_hw_ctx(
-+				dc, pipe_ctx_old, &dc->current_context);
-+		else if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
-+			core_link_disable_stream(pipe_ctx);
-+	}
-+
-+	/* Skip applying if no targets */
-+	if (context->target_count <= 0)
-+		return DC_OK;
-+
-+	/* Apply new context */
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
- 			true);
- 
-@@ -1438,59 +1498,6 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_
- 	}
- }
- 
--static void reset_single_pipe_hw_ctx(
--		const struct core_dc *dc,
--		struct pipe_ctx *pipe_ctx,
--		struct validate_context *context)
--{
--	struct dc_bios *dcb;
--
--	if (pipe_ctx->pipe_idx == DCE110_UNDERLAY_IDX)
--		return;
--
--	dcb = dal_adapter_service_get_bios_parser(
--			context->res_ctx.pool.adapter_srv);
--	if (pipe_ctx->audio) {
--		dal_audio_disable_output(pipe_ctx->audio,
--				pipe_ctx->stream_enc->id,
--				pipe_ctx->signal);
--		pipe_ctx->audio = NULL;
--	}
--
--	core_link_disable_stream(pipe_ctx);
--	if (!pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true)) {
--		dm_error("DC: failed to blank crtc!\n");
--		BREAK_TO_DEBUGGER();
--	}
--	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
--	pipe_ctx->mi->funcs->free_mem_input(
--				pipe_ctx->mi, context->target_count);
--	pipe_ctx->xfm->funcs->transform_set_scaler_bypass(pipe_ctx->xfm);
--	resource_unreference_clock_source(&context->res_ctx, pipe_ctx->clock_source);
--	dc->hwss.enable_display_power_gating(
--		pipe_ctx->stream->ctx, pipe_ctx->pipe_idx, dcb,
--			PIPE_GATING_CONTROL_ENABLE);
--
--	pipe_ctx->stream = NULL;
--}
--
--static void reset_hw_ctx(
--		struct core_dc *dc,
--		struct validate_context *new_context)
--{
--	uint8_t i;
--
--	/* look up the targets that have been removed since last commit */
--	for (i = 0; i < MAX_PIPES; i++) {
--		struct pipe_ctx *pipe_ctx_old =
--			&dc->current_context.res_ctx.pipe_ctx[i];
--		struct pipe_ctx *pipe_ctx = &new_context->res_ctx.pipe_ctx[i];
--
--		if (pipe_ctx_old->stream && !pipe_ctx->stream)
--			reset_single_pipe_hw_ctx(
--				dc, pipe_ctx_old, &dc->current_context);
--	}
--}
- 
- static void power_down(struct core_dc *dc)
- {
-@@ -1643,7 +1650,6 @@ static void init_hw(struct core_dc *dc)
- static const struct hw_sequencer_funcs dce110_funcs = {
- 	.init_hw = init_hw,
- 	.apply_ctx_to_hw = apply_ctx_to_hw,
--	.reset_hw_ctx = reset_hw_ctx,
- 	.set_plane_config = set_plane_config,
- 	.update_plane_addrs = update_plane_addrs,
- 	.set_gamma_correction = set_gamma_ramp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index d801a60..a38c6f5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -42,8 +42,6 @@ struct hw_sequencer_funcs {
- 	enum dc_status (*apply_ctx_to_hw)(
- 			struct core_dc *dc, struct validate_context *context);
- 
--	void (*reset_hw_ctx)(struct core_dc *dc, struct validate_context *context);
--
- 	void (*set_plane_config)(
- 			const struct core_dc *dc,
- 			struct pipe_ctx *pipe_ctx,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0989-drm-amd-dal-don-t-get-edid-on-mst-disconnect.patch b/common/recipes-kernel/linux/files/0989-drm-amd-dal-don-t-get-edid-on-mst-disconnect.patch
deleted file mode 100644
index f3700b33..00000000
--- a/common/recipes-kernel/linux/files/0989-drm-amd-dal-don-t-get-edid-on-mst-disconnect.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 304ee59a3a95dfaa7a50208c372fadc91e756fd3 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Tue, 29 Mar 2016 17:38:15 -0400
-Subject: [PATCH 0989/1110] drm/amd/dal: don't get edid on mst disconnect
-
-Change check condition in dm_dp_mst_hotplug such that only
-on plug in case we get edid from the port for the connector.
-Also, following the previous change that moved sink creation
-out of fill_mode ioctl, this change moves freeing the edid
-block from fill_mode ioctl to dm_dp_destroy_mst_connector.
-
-No visible change in behaviour usecase wise.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c   | 19 +++++++++++++------
- 1 file changed, 13 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index c00c4d1..d73b246 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -127,11 +127,6 @@ dm_dp_mst_detect(struct drm_connector *connector, bool force)
- 			&master->mst_mgr,
- 			aconnector->port);
- 
--	if (status == connector_status_disconnected && aconnector->edid) {
--		kfree(aconnector->edid);
--		aconnector->edid = NULL;
--	}
--
- 	/*
- 	 * we do not want to make this connector connected until we have edid on
- 	 * it
-@@ -375,6 +370,14 @@ static void dm_dp_destroy_mst_connector(
- 		dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
- 		aconnector->dc_sink = NULL;
- 	}
-+	if (aconnector->edid) {
-+		kfree(aconnector->edid);
-+		aconnector->edid = NULL;
-+	}
-+
-+	drm_mode_connector_update_edid_property(
-+			&aconnector->base,
-+			NULL);
- }
- 
- static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-@@ -390,7 +393,11 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
- 	drm_modeset_lock_all(dev);
- 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
- 		aconnector = to_amdgpu_connector(connector);
--		if (aconnector->mst_port && !aconnector->dc_sink) {
-+		if (aconnector->port && !aconnector->dc_sink) {
-+			/*
-+			 * This is plug in case, where port has been created but
-+			 * sink hasn't been created yet
-+			 */
- 			if (!aconnector->edid) {
- 				edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0990-drm-amd-dal-Enable-drr-programming-in-DC.patch b/common/recipes-kernel/linux/files/0990-drm-amd-dal-Enable-drr-programming-in-DC.patch
deleted file mode 100644
index 9433de39..00000000
--- a/common/recipes-kernel/linux/files/0990-drm-amd-dal-Enable-drr-programming-in-DC.patch
+++ /dev/null
@@ -1,722 +0,0 @@
-From d0c2b064afa27b4a261d54961aa4eac4b436f678 Mon Sep 17 00:00:00 2001
-From: Jun Lei <Jun.Lei@amd.com>
-Date: Wed, 30 Mar 2016 11:20:27 -0400
-Subject: [PATCH 0990/1110] drm/amd/dal: Enable drr programming in DC.
-
-1.) To support freesync, crtc drr registers must be programmed.
-Since DRR use cases are driven by DM, DC must expose stream
-interfaces to directly program vmin and vmax.
-2.) Check ignore msa stream flag and program accordingly when
-enabling DP output.
-3.) Add interfaces for freesync module to track sink.  When sinks
-are added freesync module will remember.  Removing sinks stop
-tracking.  Tracking is necessary since freesync module must modify
-freesync relevant params in dc_stream, and to manage freesync mode
-(BTR, Flicker, etc.)
-4.) Fill out implementation of module
-
-Signed-off-by: Jun Lei <Jun.Lei@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  30 +++++
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  18 +++
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   4 +-
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  20 ++-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    | 118 +++++++----------
- .../amd/dal/dc/dce110/dce110_timing_generator.h    |   4 +-
- .../gpu/drm/amd/dal/dc/inc/hw/timing_generator.h   |   3 +
- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   2 +
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |   6 +-
- .../gpu/drm/amd/dal/modules/freesync/freesync.c    | 139 +++++++++++++++++++--
- .../gpu/drm/amd/dal/modules/freesync/freesync.h    |  41 ------
- drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h |  29 ++++-
- 12 files changed, 274 insertions(+), 140 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/modules/freesync/freesync.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index 7d234cf..c5aa460 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -201,6 +201,34 @@ static struct adapter_service *create_as(
- 	return as;
- }
- 
-+static bool dc_stream_adjust_vmin_vmax(struct dc *dc, const struct dc_stream **stream, int num_streams, int vmin, int vmax)
-+{
-+	/* TODO: Support multiple streams */
-+	struct core_dc *core_dc = DC_TO_CORE(dc);
-+	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
-+	int i = 0;
-+	bool ret = false;
-+	struct pipe_ctx *pipes;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (core_dc->current_context.res_ctx.pipe_ctx[i].stream == core_stream) {
-+			pipes = &core_dc->current_context.res_ctx.pipe_ctx[i];
-+			core_dc->hwss.set_drr(&pipes, 1, vmin, vmax);
-+
-+			ret = true;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static void allocate_dc_stream_funcs(struct core_dc *core_dc)
-+{
-+	if (core_dc->hwss.set_drr != NULL) {
-+		core_dc->public.stream_funcs.dc_stream_adjust_vmin_vmax = dc_stream_adjust_vmin_vmax;
-+	}
-+}
-+
- static bool construct(struct core_dc *dc, const struct dc_init_data *init_params)
- {
- 	struct dal_logger *logger;
-@@ -275,6 +303,8 @@ static bool construct(struct core_dc *dc, const struct dc_init_data *init_params
- 			goto create_links_fail;
- 	}
- 
-+	allocate_dc_stream_funcs(dc);
-+
- 	return true;
- 
- 	/**** error handling here ****/
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 06c8fa6..73dbf4f 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1159,6 +1159,22 @@ static void dpcd_configure_panel_mode(
- 			panel_mode_edp);
- }
- 
-+static void enable_stream_features(struct pipe_ctx *pipe_ctx)
-+{
-+	struct core_stream *stream = pipe_ctx->stream;
-+	struct core_link *link = stream->sink->link;
-+	union down_spread_ctrl downspread;
-+
-+	core_link_read_dpcd(link, DPCD_ADDRESS_DOWNSPREAD_CNTL,
-+			&downspread.raw, sizeof(downspread));
-+
-+	downspread.bits.IGNORE_MSA_TIMING_PARAM =
-+			(stream->public.ignore_msa_timing_param) ? 1 : 0;
-+
-+	core_link_write_dpcd(link, DPCD_ADDRESS_DOWNSPREAD_CNTL,
-+			&downspread.raw, sizeof(downspread));
-+}
-+
- static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
- {
- 	struct core_stream *stream = pipe_ctx->stream;
-@@ -1195,6 +1211,8 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
- 	else
- 		status = DC_ERROR_UNEXPECTED;
- 
-+	enable_stream_features(pipe_ctx);
-+
- 	return status;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index 13fa582..e394dd2 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -50,7 +50,7 @@ struct dc_surface;
- 
- struct dc_stream_funcs {
- 	bool (*dc_stream_adjust_vmin_vmax)(struct dc *dc,
--			struct dc_stream *stream, int vmin, int vmax);
-+			const struct dc_stream **stream, int num_streams, int vmin, int vmax);
- };
- 
- struct dc {
-@@ -311,7 +311,7 @@ struct dc_stream {
- 
- 	struct audio_info audio_info;
- 
--	bool enable_freesync;
-+	bool ignore_msa_timing_param;
- 
- 	/* TODO: dithering */
- 	/* TODO: transfer function (CSC/regamma/gamut remap) */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index fa282c0..0673a1b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1224,7 +1224,6 @@ static void switch_dp_clock_sources(
-  * Public functions
-  ******************************************************************************/
- 
--
- static void reset_single_pipe_hw_ctx(
- 		const struct core_dc *dc,
- 		struct pipe_ctx *pipe_ctx,
-@@ -1261,6 +1260,22 @@ static void reset_single_pipe_hw_ctx(
- 	pipe_ctx->stream = NULL;
- }
- 
-+static void set_drr(struct pipe_ctx **pipe_ctx,
-+		int num_pipes, int vmin, int vmax)
-+{
-+	int i = 0;
-+	struct drr_params params = {0};
-+
-+	params.vertical_total_max = vmax;
-+	params.vertical_total_min = vmin;
-+
-+	/* TODO: If multiple pipes are to be supported, you need some GSL stuff */
-+
-+	for (i = 0; i < num_pipes; i++) {
-+		pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
-+	}
-+}
-+
- /*TODO: const validate_context*/
- static enum dc_status apply_ctx_to_hw(
- 		struct core_dc *dc,
-@@ -1667,7 +1682,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
- 	.set_blender_mode = dce110_set_blender_mode,
- 	.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,/*todo*/
- 	.set_display_clock = set_display_clock,
--	.set_displaymarks = set_displaymarks
-+	.set_displaymarks = set_displaymarks,
-+	.set_drr = set_drr
- };
- 
- bool dce110_hw_sequencer_construct(struct core_dc *dc)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index e4fe49a..b17fb79 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -148,7 +148,10 @@ static struct timing_generator_funcs dce110_tg_funcs = {
- 		.tear_down_global_swap_lock =
- 				dce110_timing_generator_tear_down_global_swap_lock,
- 		.enable_advanced_request =
--				dce110_timing_generator_enable_advanced_request
-+				dce110_timing_generator_enable_advanced_request,
-+		.set_drr =
-+				dce110_timing_generator_set_drr
-+
- };
- 
- static const struct crtc_black_color black_color_format[] = {
-@@ -585,7 +588,7 @@ bool dce110_timing_generator_program_timing_generator(
- 
- /**
-  *****************************************************************************
-- *  Function: program_drr
-+ *  Function: set_drr
-  *
-  *  @brief
-  *     Program dynamic refresh rate registers m_DxCRTC_V_TOTAL_*.
-@@ -594,9 +597,9 @@ bool dce110_timing_generator_program_timing_generator(
-  *  wCrtcTiming struct
-  *****************************************************************************
-  */
--void dce110_timing_generator_program_drr(
-+void dce110_timing_generator_set_drr(
- 	struct timing_generator *tg,
--	const struct hw_ranged_timing *timing)
-+	const struct drr_params *params)
- {
- 	/* register values */
- 	uint32_t v_total_min = 0;
-@@ -619,90 +622,53 @@ void dce110_timing_generator_program_drr(
- 	addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL);
- 	static_screen_cntl = dm_read_reg(tg->ctx, addr);
- 
--	if (timing != NULL) {
--		/* Set Static Screen trigger events
--		 * If CRTC_SET_V_TOTAL_MIN_MASK_EN is set, use legacy event mask
--		 * register
--		 */
--		if (get_reg_field_value(
--			v_total_cntl,
--			CRTC_V_TOTAL_CONTROL,
--			CRTC_SET_V_TOTAL_MIN_MASK_EN)) {
--			set_reg_field_value(v_total_cntl,
--				/* TODO: add implementation
--				translate_to_dce_static_screen_events(
--					timing->control.event_mask.u_all),
--					*/ 0,
--				CRTC_V_TOTAL_CONTROL,
--				CRTC_SET_V_TOTAL_MIN_MASK);
--		} else {
--			set_reg_field_value(static_screen_cntl,
--				/* TODO: add implementation
--				translate_to_dce_static_screen_events(
--					timing->control.event_mask.u_all),
--					*/ 0,
--				CRTC_STATIC_SCREEN_CONTROL,
--				CRTC_STATIC_SCREEN_EVENT_MASK);
--		}
-+	if (params != NULL &&
-+		params->vertical_total_max > 0 &&
-+		params->vertical_total_min > 0) {
- 
--		/* Number of consecutive static screen frames before interrupt
--		 * is triggered. 0 is an invalid setting, which means we should
--		 * leaving HW setting unchanged. */
--		if (timing->control.static_frame_count != 0) {
--			set_reg_field_value(
--				static_screen_cntl,
--				timing->control.static_frame_count,
--				CRTC_STATIC_SCREEN_CONTROL,
--				CRTC_STATIC_SCREEN_FRAME_COUNT);
--		}
-+		set_reg_field_value(v_total_max,
-+				params->vertical_total_max - 1,
-+				CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX);
- 
--		/* This value is reduced by 1 based on the register definition
--		 * of the VTOTAL value:
--		 * CRTC_V_TOTAL should be set to Vertical total minus one. (E.g.
--		 * for 525 lines, set to 524 = 0x20C)
--		 */
- 		set_reg_field_value(v_total_min,
--				timing->vertical_total_min,
-+				params->vertical_total_min - 1,
- 				CRTC_V_TOTAL_MIN,
- 				CRTC_V_TOTAL_MIN);
--		set_reg_field_value(v_total_max,
--				timing->vertical_total_max,
--				CRTC_V_TOTAL_MAX,
--				CRTC_V_TOTAL_MAX);
- 
--		/* set VTotalControl value according to ranged timing control.
--		 */
--
--		if (timing->vertical_total_min != 0) {
--			set_reg_field_value(v_total_cntl,
--					1,
--					CRTC_V_TOTAL_CONTROL,
--					CRTC_V_TOTAL_MIN_SEL);
--		} else {
--			set_reg_field_value(v_total_cntl,
--					0,
--					CRTC_V_TOTAL_CONTROL,
--					CRTC_V_TOTAL_MIN_SEL);
--		}
--		if (timing->vertical_total_max != 0) {
--			set_reg_field_value(v_total_cntl,
--					1,
--					CRTC_V_TOTAL_CONTROL,
--					CRTC_V_TOTAL_MAX_SEL);
--		} else {
--			set_reg_field_value(v_total_cntl,
--					0,
--					CRTC_V_TOTAL_CONTROL,
--					CRTC_V_TOTAL_MAX_SEL);
--		}
- 		set_reg_field_value(v_total_cntl,
--				timing->control.force_lock_on_event,
-+				1,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MIN_SEL);
-+
-+		set_reg_field_value(v_total_cntl,
-+				1,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MAX_SEL);
-+
-+		set_reg_field_value(v_total_cntl,
-+				0,
- 				CRTC_V_TOTAL_CONTROL,
- 				CRTC_FORCE_LOCK_ON_EVENT);
- 		set_reg_field_value(v_total_cntl,
--				timing->control.lock_to_master_vsync,
-+				0,
- 				CRTC_V_TOTAL_CONTROL,
- 				CRTC_FORCE_LOCK_TO_MASTER_VSYNC);
-+
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_SET_V_TOTAL_MIN_MASK_EN);
-+
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_SET_V_TOTAL_MIN_MASK);
-+
-+		set_reg_field_value(static_screen_cntl,
-+				0x180,
-+			CRTC_STATIC_SCREEN_CONTROL,
-+			CRTC_STATIC_SCREEN_EVENT_MASK);
- 	} else {
- 		set_reg_field_value(v_total_cntl,
- 			0,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-index 7e01bde..fadff7f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
-@@ -187,9 +187,9 @@ void dce110_timing_generator_set_test_pattern(
- 	enum controller_dp_test_pattern test_pattern,
- 	enum dc_color_depth color_depth);
- 
--void dce110_timing_generator_program_drr(
-+void dce110_timing_generator_set_drr(
- 	struct timing_generator *tg,
--	const struct hw_ranged_timing *timing);
-+	const struct drr_params *params);
- 
- uint32_t dce110_timing_generator_get_crtc_scanoutpos(
- 	struct timing_generator *tg,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-index 9347310..770e3d3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/timing_generator.h
-@@ -111,6 +111,8 @@ struct timing_generator {
- 
- struct dc_crtc_timing;
- 
-+struct drr_params;
-+
- struct timing_generator_funcs {
- 	bool (*validate_timing)(struct timing_generator *tg,
- 							const struct dc_crtc_timing *timing);
-@@ -150,6 +152,7 @@ struct timing_generator_funcs {
- 	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
- 	void (*enable_advanced_request)(struct timing_generator *tg,
- 					bool enable, const struct dc_crtc_timing *timing);
-+	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
- };
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-index a38c6f5..e36a9a9 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
-@@ -110,6 +110,8 @@ struct hw_sequencer_funcs {
- 				struct validate_context *context);
- 
- 	void (*set_display_clock)(struct validate_context *context);
-+
-+	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, int vmin, int vmax);
- };
- 
- bool dc_construct_hw_sequencer(
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index 76c551c..60dcf81 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -103,15 +103,13 @@ struct hw_ranged_timing_control {
- };
- 
- /* define the structure of Dynamic Refresh Mode */
--struct hw_ranged_timing {
-+struct drr_params {
- 	/* defines the minimum possible vertical dimension of display timing
- 	 * for CRTC as supported by the panel */
- 	uint32_t vertical_total_min;
- 	/* defines the maximum possible vertical dimension of display timing
- 	 * for CRTC as supported by the panel */
- 	uint32_t vertical_total_max;
--
--	struct hw_ranged_timing_control control;
- };
- 
- /* CRTC timing structure */
-@@ -130,8 +128,6 @@ struct hw_crtc_timing {
- 	uint32_t v_sync_start;
- 	uint32_t v_sync_width;
- 
--	struct hw_ranged_timing ranged_timing;
--
- 	/* in KHz */
- 	uint32_t pixel_clock;
- 
-diff --git a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-index d0113d5..01cfeb0 100644
---- a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-+++ b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-@@ -23,9 +23,26 @@
-  *
-  */
- 
--#include "freesync.h"
- #include "dm_services.h"
- #include "dc.h"
-+#include "mod_freesync.h"
-+
-+static const MOD_FREESYNC_MAX_CONCURRENT_SINKS = 32;
-+
-+struct sink_caps {
-+    const struct dc_sink *sink;
-+    struct mod_freesync_caps caps;
-+};
-+
-+struct core_freesync {
-+    struct mod_freesync public;
-+    struct dc *dc;
-+    struct sink_caps *caps;
-+    int num_sinks;
-+};
-+
-+#define MOD_FREESYNC_TO_CORE(mod_freesync)\
-+    container_of(mod_freesync, struct core_freesync, public)
- 
- static bool check_dc_support(const struct dc *dc)
- {
-@@ -38,10 +55,21 @@ static bool check_dc_support(const struct dc *dc)
- struct mod_freesync *mod_freesync_create(struct dc *dc)
- {
- 	struct core_freesync *core_freesync = dm_alloc(sizeof(struct core_freesync));
-+	int i = 0;
- 
- 	if (core_freesync == NULL)
- 		goto fail_alloc_context;
- 
-+	core_freesync->caps = dm_alloc(sizeof(struct sink_caps) * MOD_FREESYNC_MAX_CONCURRENT_SINKS);
-+
-+	if (core_freesync->caps == NULL)
-+		goto fail_alloc_caps;
-+
-+	for (i = 0; i < MOD_FREESYNC_MAX_CONCURRENT_SINKS; i++)
-+		core_freesync->caps[i].sink = NULL;
-+
-+	core_freesync->num_sinks = 0;
-+
- 	if (dc == NULL)
- 		goto fail_construct;
- 
-@@ -53,6 +81,9 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
- 	return &core_freesync->public;
- 
- fail_construct:
-+	dm_free(core_freesync->caps);
-+
-+fail_alloc_caps:
- 	dm_free(core_freesync);
- 
- fail_alloc_context:
-@@ -68,32 +99,120 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync)
- 	}
- }
- 
-+bool mod_freesync_add_sink(struct mod_freesync *mod_freesync,
-+		const struct dc_sink *sink, struct mod_freesync_caps *caps)
-+{
-+	int i = 0;
-+	struct core_freesync *core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	if (core_freesync->num_sinks < MOD_FREESYNC_MAX_CONCURRENT_SINKS) {
-+		dc_sink_retain(sink);
-+
-+		core_freesync->caps[core_freesync->num_sinks].sink = sink;
-+		core_freesync->caps[core_freesync->num_sinks].caps = *caps;
-+		core_freesync->num_sinks++;
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool mod_freesync_remove_sink(struct mod_freesync *mod_freesync,
-+		const struct dc_sink *sink)
-+{
-+	int i = 0, j = 0;
-+	struct core_freesync *core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	for (i = 0; i < core_freesync->num_sinks; i++) {
-+		if (core_freesync->caps[i].sink == sink) {
-+			/* To remove this sink, shift everything after it down */
-+			for (j = i; j < core_freesync->num_sinks - 1; j++) {
-+				core_freesync->caps[j].sink = core_freesync->caps[j + 1].sink;
-+				core_freesync->caps[j].caps = core_freesync->caps[j + 1].caps;
-+			}
-+
-+			core_freesync->num_sinks--;
-+
-+			dc_sink_release(sink);
-+
-+			return true;
-+		}
-+	}
-+
-+	return false;
-+}
-+
-+void mod_freesync_update_stream(struct mod_freesync *mod_freesync,
-+		struct dc_stream *stream)
-+{
-+	int i = 0;
-+	struct core_freesync *core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	for (i = 0; i < core_freesync->num_sinks; i++) {
-+		if (core_freesync->caps[i].sink == stream->sink &&
-+			core_freesync->caps[i].caps.supported) {
-+			stream->ignore_msa_timing_param = 1;
-+		}
-+	}
-+}
-+
-+static void calc_vmin_vmax (const struct dc_stream *stream,
-+		struct mod_freesync_caps *caps, int *vmin, int *vmax)
-+{
-+	/* TODO: This calculation is probably wrong... */
-+
-+	unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0;
-+
-+	min_frame_duration_in_ns = (unsigned int)((1000000000ULL * 1000000) / caps->maxRefreshInMicroHz);
-+	max_frame_duration_in_ns = (unsigned int)((1000000000ULL * 1000000) / caps->minRefreshInMicroHz);
-+
-+	*vmax = (unsigned long long)(max_frame_duration_in_ns) * stream->timing.pix_clk_khz / stream->timing.h_total / 1000000;
-+	*vmin = (unsigned long long)(min_frame_duration_in_ns) * stream->timing.pix_clk_khz / stream->timing.h_total / 1000000;
-+
-+	if (*vmin < stream->timing.v_total) {
-+	    *vmin = stream->timing.v_total;
-+	}
-+}
-+
- bool mod_freesync_set_freesync_on_streams(struct mod_freesync *mod_freesync,
--		struct dc_stream **streams,	int num_streams,
--		struct mod_freesync_params *params)
-+		const struct dc_stream **streams,	int num_streams,
-+		const struct mod_freesync_params *params)
- {
--	int v_total_nominal = 0;
-+	int v_total_nominal = 0, v_total_min = 0, v_total_max = 0;
- 	int i = 0;
- 	struct core_freesync *core_freesync = NULL;
- 
- 	if (num_streams == 0 || streams == NULL || mod_freesync == NULL
--			|| params == NULL)
-+			|| params == NULL || num_streams > 1)
- 		return false;
- 
-+	/* TODO: Multi-stream support */
-+
- 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- 
- 	if (params->mode == FREESYNC_MODE_DISABLED)	{
- 		/* Disable freesync */
--		for (i = 0; i < num_streams; i++) {
--			v_total_nominal = streams[i]->timing.v_total;
-+		v_total_nominal = streams[0]->timing.v_total;
- 
--			core_freesync->dc->stream_funcs.dc_stream_adjust_vmin_vmax(core_freesync->dc,
--					streams[i], v_total_nominal, v_total_nominal);
--		}
-+		core_freesync->dc->stream_funcs.dc_stream_adjust_vmin_vmax(core_freesync->dc,
-+				streams, num_streams, v_total_nominal, v_total_nominal);
- 
- 		return true;
- 	} else if (params->mode == FREESYNC_MODE_VARIABLE) {
- 		/* Enable freesync */
-+		for (i = 0; i < core_freesync->num_sinks; i++) {
-+			if (core_freesync->caps[i].sink == streams[0]->sink &&
-+				core_freesync->caps[i].caps.supported) {
-+
-+				calc_vmin_vmax(streams[0], &core_freesync->caps[i].caps, &v_total_min, &v_total_max);
-+
-+				core_freesync->dc->stream_funcs.dc_stream_adjust_vmin_vmax(core_freesync->dc,
-+									streams, num_streams, v_total_min, v_total_max);
-+
-+				return true;
-+			}
-+		}
- 	}
- 
- 	return false;
-diff --git a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.h b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.h
-deleted file mode 100644
-index 65a4194..0000000
---- a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.h
-+++ /dev/null
-@@ -1,41 +0,0 @@
--/*
-- * Copyright 2016 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef FREESYNC_H_
--#define FREESYNC_H_
--
--#include "mod_freesync.h"
--
--struct dc;
--
--struct core_freesync {
--	struct mod_freesync public;
--	struct dc *dc;
--};
--
--#define MOD_FREESYNC_TO_CORE(mod_freesync)\
--	container_of(mod_freesync, struct core_freesync, public)
--
--#endif /* FREESYNC_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h
-index e12d844..8df086a 100644
---- a/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h
-+++ b/drivers/gpu/drm/amd/dal/modules/inc/mod_freesync.h
-@@ -42,16 +42,41 @@ struct mod_freesync_params {
- 	enum mod_freesync_mode mode;
- };
- 
-+struct mod_freesync_caps {
-+	bool supported;
-+	int minRefreshInMicroHz;
-+	int maxRefreshInMicroHz;
-+};
-+
- struct mod_freesync *mod_freesync_create(struct dc *dc);
- void mod_freesync_destroy(struct mod_freesync *mod_freesync);
- 
- /*
-+ * Add sink to be tracked by module
-+ */
-+bool mod_freesync_add_sink(struct mod_freesync *mod_freesync,
-+		const struct dc_sink *sink, struct mod_freesync_caps *caps);
-+
-+/*
-+ * Remove sink to be tracked by module
-+ */
-+bool mod_freesync_remove_sink(struct mod_freesync *mod_freesync,
-+		const struct dc_sink *sink);
-+
-+/*
-+ * Build additional parameters for dc_stream when creating stream for
-+ * sink to support freesync
-+ */
-+void mod_freesync_update_stream(struct mod_freesync *mod_freesync,
-+		struct dc_stream *stream);
-+
-+/*
-  * This interface sets the freesync mode on a stream.  Mode and associated
-  * parameters required to set it are defined in mod_freesync_params.
-  */
- bool mod_freesync_set_freesync_on_streams(struct mod_freesync *mod_freesync,
--		struct dc_stream **streams, int num_streams,
--		struct mod_freesync_params *params);
-+		const struct dc_stream **streams, int num_streams,
-+		const struct mod_freesync_params *params);
- 
- /*
-  * This interface must be called for on every VUPDATE event for every stream
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0991-drm-amd-dal-Fix-underscan-when-enabling-before-setti.patch b/common/recipes-kernel/linux/files/0991-drm-amd-dal-Fix-underscan-when-enabling-before-setti.patch
deleted file mode 100644
index 8dfc7ea8..00000000
--- a/common/recipes-kernel/linux/files/0991-drm-amd-dal-Fix-underscan-when-enabling-before-setti.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From 0d1247fd5e2d37e0db495608cf0d4fd1b51e27fe Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Wed, 30 Mar 2016 18:35:32 -0400
-Subject: [PATCH 0991/1110] drm/amd/dal: Fix underscan when enabling before
- setting
-
-In order for plane properties to be updated (including underscan),
-it is necessary to trigger an atomic_update by calling
-drm_atomic_get_plane_state, which will also create or duplicate
-a new state if one currently does not exist.
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 94 +++++++---------------
- 1 file changed, 31 insertions(+), 63 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index f79cbee..010705d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1019,10 +1019,12 @@ int amdgpu_dm_connector_atomic_set_property(
- 	struct dm_connector_state *dm_new_state =
- 		to_dm_connector_state(connector_state);
- 
-+	struct drm_crtc_state *new_crtc_state;
-+	struct drm_crtc *crtc;
-+	int i;
-+	int ret = -EINVAL;
-+
- 	if (property == dev->mode_config.scaling_mode_property) {
--		struct drm_crtc_state *new_crtc_state;
--		struct drm_crtc *crtc;
--		int i;
- 		enum amdgpu_rmx_type rmx_type;
- 
- 		switch (val) {
-@@ -1045,79 +1047,45 @@ int amdgpu_dm_connector_atomic_set_property(
- 			return 0;
- 
- 		dm_new_state->scaling = rmx_type;
--
--		for_each_crtc_in_state(
--			connector_state->state,
--			crtc,
--			new_crtc_state,
--			i) {
--
--			if (crtc == connector_state->crtc) {
--				struct drm_plane_state *plane_state;
--
--				new_crtc_state->mode_changed = true;
--
--				/*
--				 * Bit of magic done here. We need to ensure
--				 * that planes get update after mode is set.
--				 * So, we need to add primary plane to state,
--				 * and this way atomic_update would be called
--				 * for it
--				 */
--				plane_state =
--					drm_atomic_get_plane_state(
--						connector_state->state,
--						crtc->primary);
--
--				if (!plane_state)
--					return -EINVAL;
--			}
--		}
--
--		return 0;
-+		ret = 0;
- 	} else if (property == adev->mode_info.underscan_hborder_property) {
- 		dm_new_state->underscan_hborder = val;
--		return 0;
-+		ret = 0;
- 	} else if (property == adev->mode_info.underscan_vborder_property) {
- 		dm_new_state->underscan_vborder = val;
--		return 0;
-+		ret = 0;
- 	} else if (property == adev->mode_info.underscan_property) {
--		struct drm_crtc_state *new_crtc_state;
--		struct drm_crtc *crtc;
--		int i;
--
- 		dm_new_state->underscan_enable = val;
-+		ret = 0;
-+	}
- 
--		for_each_crtc_in_state(
--			connector_state->state,
--			crtc,
--			new_crtc_state,
--			i) {
-+	for_each_crtc_in_state(
-+		connector_state->state,
-+		crtc,
-+		new_crtc_state,
-+		i) {
- 
--			if (crtc == connector_state->crtc) {
--				struct drm_plane_state *plane_state;
-+		if (crtc == connector_state->crtc) {
-+			struct drm_plane_state *plane_state;
- 
--				/*
--				 * Bit of magic done here. We need to ensure
--				 * that planes get update after mode is set.
--				 * So, we need to add primary plane to state,
--				 * and this way atomic_update would be called
--				 * for it
--				 */
--				plane_state =
--					drm_atomic_get_plane_state(
--						connector_state->state,
--						crtc->primary);
-+			/*
-+			 * Bit of magic done here. We need to ensure
-+			 * that planes get update after mode is set.
-+			 * So, we need to add primary plane to state,
-+			 * and this way atomic_update would be called
-+			 * for it
-+			 */
-+			plane_state =
-+				drm_atomic_get_plane_state(
-+					connector_state->state,
-+					crtc->primary);
- 
--				if (!plane_state)
--					return -EINVAL;
--			}
-+			if (!plane_state)
-+				return -EINVAL;
- 		}
--
--		return 0;
- 	}
- 
--	return -EINVAL;
-+	return ret;
- }
- 
- void amdgpu_dm_connector_destroy(struct drm_connector *connector)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0992-drm-amd-dal-fix-cursor-width-and-height-in-interface.patch b/common/recipes-kernel/linux/files/0992-drm-amd-dal-fix-cursor-width-and-height-in-interface.patch
deleted file mode 100644
index 0a580423..00000000
--- a/common/recipes-kernel/linux/files/0992-drm-amd-dal-fix-cursor-width-and-height-in-interface.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 44029293d12f538a95824ecdd40b8c228933bebc Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Thu, 24 Mar 2016 11:18:12 -0400
-Subject: [PATCH 0992/1110] drm/amd/dal: fix cursor width and height in
- interface
-
-Cursor size in interface should be equal to the requested values
-Do adjustment in dce's specific code.
-
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c   | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 010705d..9f02d3e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -82,8 +82,8 @@ static void dm_set_cursor(
- 
- 	attributes.address.high_part = upper_32_bits(gpu_addr);
- 	attributes.address.low_part  = lower_32_bits(gpu_addr);
--	attributes.width             = width-1;
--	attributes.height            = height-1;
-+	attributes.width             = width;
-+	attributes.height            = height;
- 	attributes.x_hot             = 0;
- 	attributes.y_hot             = 0;
- 	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-index 2dabaed..95f6ca3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
-@@ -117,7 +117,7 @@ bool dce110_ipp_cursor_set_attributes(
- 	 * Program cursor size -- NOTE: HW spec specifies that HW register
- 	 * stores size as (height - 1, width - 1)
- 	 */
--	program_size(ipp110, attributes->width, attributes->height);
-+	program_size(ipp110, attributes->width-1, attributes->height-1);
- 
- 	/* Program cursor surface address */
- 	program_address(ipp110, attributes->address);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0993-drm-amd-dal-Fix-Fiji-audio-lag-issue.patch b/common/recipes-kernel/linux/files/0993-drm-amd-dal-Fix-Fiji-audio-lag-issue.patch
deleted file mode 100644
index 5d89c722..00000000
--- a/common/recipes-kernel/linux/files/0993-drm-amd-dal-Fix-Fiji-audio-lag-issue.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From bfc9ee223b7426fa3fd81da89f445aa35a13069f Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 30 Mar 2016 11:53:00 -0400
-Subject: [PATCH 0993/1110] drm/amd/dal: Fix Fiji audio lag issue.
-
-Issue:
-Play audio when DP and HDMI connected, if unplug HDMI, audio lag happened
-on DP monitor.
-
-Root cause:
-In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
-is set to either dto0 or dto1, audio should work fine.
-In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1.
-When HDMI unplugged, due to mode set optimization,
-setup audio wall dto is bypassed, and DCCG_AUDIO_DTO_SEL is dto0,
-audio lag happened.
-
-Solution:
-Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
-find first available pipe with audio, setup audio wall DTO per topology
-instead of per pipe.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 35 +++++++++++++++++-----
- 1 file changed, 27 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 0673a1b..9ca604d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -867,14 +867,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		}
- 	}
- 
--	/* Setup audio rate clock source */
--	if (pipe_ctx->audio != NULL)
--		dal_audio_setup_audio_wall_dto(
--				pipe_ctx->audio,
--				pipe_ctx->signal,
--				&pipe_ctx->audio_output.crtc_info,
--				&pipe_ctx->audio_output.pll_info);
--
- 	/* program blank color */
- 	color_space = get_output_color_space(&stream->public.timing);
- 	pipe_ctx->tg->funcs->set_blank_color(
-@@ -1347,6 +1339,33 @@ static enum dc_status apply_ctx_to_hw(
- 		if (DC_OK != status)
- 			return status;
- 	}
-+
-+	/* Setup audio rate clock source */
-+	/* Issue:
-+	 * Audio lag happened on DP monitor when unplug a HDMI monitor
-+	 *
-+	 * Cause:
-+	 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
-+	 * is set to either dto0 or dto1, audio should work fine.
-+	 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
-+	 * set to dto0 will cause audio lag.
-+	 *
-+	 * Solution:
-+	 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
-+	 * find first available pipe with audio, setup audio wall DTO per topology
-+	 * instead of per pipe.
-+	 */
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (context->res_ctx.pipe_ctx[i].audio != NULL) {
-+			dal_audio_setup_audio_wall_dto(
-+					context->res_ctx.pipe_ctx[i].audio,
-+					context->res_ctx.pipe_ctx[i].signal,
-+					&context->res_ctx.pipe_ctx[i].audio_output.crtc_info,
-+					&context->res_ctx.pipe_ctx[i].audio_output.pll_info);
-+			break;
-+		}
-+	}
-+
- 	dc->hwss.set_displaymarks(dc, context);
- 
- 	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0994-drm-amd-dal-Don-t-wait-in-software-for-double-buffer.patch b/common/recipes-kernel/linux/files/0994-drm-amd-dal-Don-t-wait-in-software-for-double-buffer.patch
deleted file mode 100644
index dc435a6a..00000000
--- a/common/recipes-kernel/linux/files/0994-drm-amd-dal-Don-t-wait-in-software-for-double-buffer.patch
+++ /dev/null
@@ -1,510 +0,0 @@
-From dd89e7c818be7eb788e95c9ceeaf44daf2a5e45b Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 30 Mar 2016 18:30:16 -0400
-Subject: [PATCH 0994/1110] drm/amd/dal: Don't wait in software for double
- buffered registers update.
-
-It's not necessary.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |  91 -----------------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  96 +-----------------
- .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c    | 109 ---------------------
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |  79 ---------------
- 4 files changed, 1 insertion(+), 374 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index 467f322..a2a4f2a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -118,7 +118,6 @@ static bool dce100_pipe_control_lock(
- {
- 	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- 	uint32_t value = dm_read_reg(ctx, addr);
--	bool need_to_wait = false;
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- 		set_reg_field_value(
-@@ -147,7 +146,6 @@ static bool dce100_pipe_control_lock(
- 			lock,
- 			BLND_V_UPDATE_LOCK,
- 			BLND_BLND_V_UPDATE_LOCK);
--		need_to_wait = true;
- 	}
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-@@ -159,95 +157,6 @@ static bool dce100_pipe_control_lock(
- 
- 	dm_write_reg(ctx, addr, value);
- 
--	if (!lock && need_to_wait) {
--		uint8_t counter = 0;
--		const uint8_t counter_limit = 100;
--		const uint16_t delay_us = 1000;
--
--		uint8_t pipe_pending;
--
--		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
--				controller_idx);
--
--		while (counter < counter_limit) {
--			value = dm_read_reg(ctx, addr);
--
--			pipe_pending = 0;
--
--			if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						BLND_BLNDC_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					BLND_BLNDO_UPDATE_PENDING);
--			}
--
--			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDC_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDO_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDC_GRPH_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDO_GRPH_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDC_GRPH_SURF_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDO_GRPH_SURF_UPDATE_PENDING);
--			}
--
--			if (pipe_pending == 0)
--				break;
--
--			counter++;
--			udelay(delay_us);
--		}
--
--		if (counter == counter_limit) {
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: wait for update exceeded (wait %d us)\n",
--				__func__,
--				counter * delay_us);
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: control %d, remain value %x\n",
--				__func__,
--				control_mask,
--				value);
--		} else {
--			/* OK. */
--		}
--	}
- 
- 	return true;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 9ca604d..e5cb1aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -215,7 +215,6 @@ static bool dce110_pipe_control_lock(
- {
- 	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- 	uint32_t value = dm_read_reg(ctx, addr);
--	bool need_to_wait = false;
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- 		set_reg_field_value(
-@@ -244,7 +243,6 @@ static bool dce110_pipe_control_lock(
- 			lock,
- 			BLND_V_UPDATE_LOCK,
- 			BLND_BLND_V_UPDATE_LOCK);
--		need_to_wait = true;
- 	}
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-@@ -256,97 +254,6 @@ static bool dce110_pipe_control_lock(
- 
- 	dm_write_reg(ctx, addr, value);
- 
--	need_to_wait = false;/*todo: mpo optimization remove*/
--	if (!lock && need_to_wait) {
--		uint8_t counter = 0;
--		const uint8_t counter_limit = 100;
--		const uint16_t delay_us = 1000;
--
--		uint8_t pipe_pending;
--
--		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
--				controller_idx);
--
--		while (counter < counter_limit) {
--			value = dm_read_reg(ctx, addr);
--
--			pipe_pending = 0;
--
--			if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						BLND_BLNDC_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					BLND_BLNDO_UPDATE_PENDING);
--			}
--
--			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDC_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDO_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDC_GRPH_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDO_GRPH_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDC_GRPH_SURF_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDO_GRPH_SURF_UPDATE_PENDING);
--			}
--
--			if (pipe_pending == 0)
--				break;
--
--			counter++;
--			udelay(delay_us);
--		}
--
--		if (counter == counter_limit) {
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: wait for update exceeded (wait %d us)\n",
--				__func__,
--				counter * delay_us);
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: control %d, remain value %x\n",
--				__func__,
--				control_mask,
--				value);
--		} else {
--			/* OK. */
--		}
--	}
--
- 	if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER))
- 		trigger_write_crtc_h_blank_start_end(ctx, controller_idx);
- 
-@@ -1505,7 +1412,7 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_
- 			PIPE_LOCK_CONTROL_SURFACE,
- 			true);
- 
--		pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
-+			pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
- 			pipe_ctx->mi,
- 			&surface->public.address,
- 			surface->public.flip_immediate);
-@@ -1521,7 +1428,6 @@ static void update_plane_addrs(struct core_dc *dc, struct resource_context *res_
- 					PIPE_LOCK_CONTROL_SURFACE,
- 					false);
- 
--
- 		if (surface->public.flip_immediate)
- 			pipe_ctx->mi->funcs->wait_for_no_surface_update_pending(pipe_ctx->mi);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-index 0a7e82b..b887764 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-@@ -122,19 +122,6 @@ static void dce112_enable_fe_clock(
- 	dm_write_reg(ctx, addr, value);
- }
- 
--/* this is a workaround for hw bug - it is a trigger on r/w */
--static void trigger_write_crtc_h_blank_start_end(
--	struct dc_context *ctx,
--	uint8_t controller_id)
--{
--	uint32_t value;
--	uint32_t addr;
--
--	addr =  HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id);
--	value = dm_read_reg(ctx, addr);
--	dm_write_reg(ctx, addr, value);
--}
--
- static bool dce112_pipe_control_lock(
- 	struct dc_context *ctx,
- 	uint8_t controller_idx,
-@@ -143,7 +130,6 @@ static bool dce112_pipe_control_lock(
- {
- 	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- 	uint32_t value = dm_read_reg(ctx, addr);
--	bool need_to_wait = false;
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- 		set_reg_field_value(
-@@ -172,7 +158,6 @@ static bool dce112_pipe_control_lock(
- 			lock,
- 			BLND_V_UPDATE_LOCK,
- 			BLND_BLND_V_UPDATE_LOCK);
--		need_to_wait = true;
- 	}
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-@@ -184,100 +169,6 @@ static bool dce112_pipe_control_lock(
- 
- 	dm_write_reg(ctx, addr, value);
- 
--	need_to_wait = false;/*todo: mpo optimization remove*/
--	if (!lock && need_to_wait) {
--		uint8_t counter = 0;
--		const uint8_t counter_limit = 100;
--		const uint16_t delay_us = 1000;
--
--		uint8_t pipe_pending;
--
--		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
--				controller_idx);
--
--		while (counter < counter_limit) {
--			value = dm_read_reg(ctx, addr);
--
--			pipe_pending = 0;
--
--			if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						BLND_BLNDC_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					BLND_BLNDO_UPDATE_PENDING);
--			}
--
--			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDC_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDO_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDC_GRPH_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDO_GRPH_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDC_GRPH_SURF_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDO_GRPH_SURF_UPDATE_PENDING);
--			}
--
--			if (pipe_pending == 0)
--				break;
--
--			counter++;
--			udelay(delay_us);
--		}
--
--		if (counter == counter_limit) {
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: wait for update exceeded (wait %d us)\n",
--				__func__,
--				counter * delay_us);
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: control %d, remain value %x\n",
--				__func__,
--				control_mask,
--				value);
--		} else {
--			/* OK. */
--		}
--	}
--
--	if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER))
--		trigger_write_crtc_h_blank_start_end(ctx, controller_idx);
--
- 	return true;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-index 02d7508..68cf84d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -122,7 +122,6 @@ static bool dce80_pipe_control_lock(
- {
- 	uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- 	uint32_t value = dm_read_reg(ctx, addr);
--	bool need_to_wait = false;
- 
- 	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- 		set_reg_field_value(
-@@ -147,84 +146,6 @@ static bool dce80_pipe_control_lock(
- 
- 	dm_write_reg(ctx, addr, value);
- 
--	if (!lock && need_to_wait) {
--		uint8_t counter = 0;
--		const uint8_t counter_limit = 100;
--		const uint16_t delay_us = 1000;
--
--		uint8_t pipe_pending;
--
--		addr = HW_REG_BLND(mmBLND_REG_UPDATE_STATUS,
--				controller_idx);
--
--		while (counter < counter_limit) {
--			value = dm_read_reg(ctx, addr);
--
--			pipe_pending = 0;
--
--			if (control_mask & PIPE_LOCK_CONTROL_SCL) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDc_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						SCL_BLNDo_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) {
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDc_GRPH_UPDATE_PENDING);
--				pipe_pending |=
--					get_reg_field_value(
--						value,
--						BLND_REG_UPDATE_STATUS,
--						DCP_BLNDo_GRPH_UPDATE_PENDING);
--			}
--			if (control_mask & PIPE_LOCK_CONTROL_SURFACE) {
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDc_GRPH_SURF_UPDATE_PENDING);
--				pipe_pending |= get_reg_field_value(
--					value,
--					BLND_REG_UPDATE_STATUS,
--					DCP_BLNDo_GRPH_SURF_UPDATE_PENDING);
--			}
--
--			if (pipe_pending == 0)
--				break;
--
--			counter++;
--			udelay(delay_us);
--		}
--
--		if (counter == counter_limit) {
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: wait for update exceeded (wait %d us)\n",
--				__func__,
--				counter * delay_us);
--			dal_logger_write(
--				ctx->logger,
--				LOG_MAJOR_WARNING,
--				LOG_MINOR_COMPONENT_CONTROLLER,
--				"%s: control %d, remain value %x\n",
--				__func__,
--				control_mask,
--				value);
--		} else {
--			/* OK. */
--		}
--	}
--
- 	return true;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0995-drm-amd-dal-Fix-hanging-in-disable_output-test-issue.patch b/common/recipes-kernel/linux/files/0995-drm-amd-dal-Fix-hanging-in-disable_output-test-issue.patch
deleted file mode 100644
index 1996beca..00000000
--- a/common/recipes-kernel/linux/files/0995-drm-amd-dal-Fix-hanging-in-disable_output-test-issue.patch
+++ /dev/null
@@ -1,258 +0,0 @@
-From 52852a1a03bb3a608af9a56a88c250915ea7b37a Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 30 Mar 2016 18:05:49 -0400
-Subject: [PATCH 0995/1110] drm/amd/dal: Fix hanging in disable_output test
- issue.
-
-Add waiting for pflip submission done before commiting surface.
-Add debug prints on pflip status and surface address.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 30 ++++++++---
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 60 +++++++++++++++++++---
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |  8 ++-
- 3 files changed, 85 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 038dea4..4defc70 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -149,8 +149,10 @@ static struct amdgpu_crtc *get_crtc_by_target(
- 	 * following if is check inherited from both functions where this one is
- 	 * used now. Need to be checked why it could happen.
- 	 */
--	if (dc_target == NULL)
-+	if (dc_target == NULL) {
-+		WARN_ON(1);
- 		return adev->mode_info.crtcs[0];
-+	}
- 
- 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- 		amdgpu_crtc = to_amdgpu_crtc(crtc);
-@@ -176,16 +178,21 @@ static void dm_pflip_high_irq(void *interrupt_params)
- 	amdgpu_crtc = get_crtc_by_target(adev, dc_target);
- 
- 	/* IRQ could occur when in initial stage */
--	if(amdgpu_crtc == NULL)
-+	/*TODO work and BO cleanup */
-+	if (amdgpu_crtc == NULL) {
-+		DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
- 		return;
-+	}
- 
- 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
- 	works = amdgpu_crtc->pflip_works;
-+
- 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
--		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
--						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
-+		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
- 						 amdgpu_crtc->pflip_status,
--						 AMDGPU_FLIP_SUBMITTED);
-+						 AMDGPU_FLIP_SUBMITTED,
-+						 amdgpu_crtc->crtc_id,
-+						 amdgpu_crtc);
- 		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 		return;
- 	}
-@@ -203,6 +210,9 @@ static void dm_pflip_high_irq(void *interrupt_params)
- 
- 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- 
-+	DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE, work: %p,\n",
-+					__func__, amdgpu_crtc->crtc_id, amdgpu_crtc, works);
-+
- 	drm_crtc_vblank_put(&amdgpu_crtc->base);
- 	schedule_work(&works->unpin_work);
- }
-@@ -1131,12 +1141,20 @@ static void dm_page_flip(struct amdgpu_device *adev,
- 	 * Received a page flip call after the display has been reset.
- 	 * Just return in this case. Everything should be clean-up on reset.
- 	 */
--	if (!target)
-+
-+	if (!target) {
-+		WARN_ON(1);
- 		return;
-+	}
- 
- 	addr.address.grph.addr.low_part = lower_32_bits(crtc_base);
- 	addr.address.grph.addr.high_part = upper_32_bits(crtc_base);
- 
-+	DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
-+			 __func__,
-+			 addr.address.grph.addr.high_part,
-+			 addr.address.grph.addr.low_part);
-+
- 	dc_flip_surface_addrs(
- 			adev->dm.dc,
- 			dc_target_get_status(target)->surfaces,
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 9f02d3e..d2548b6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -624,7 +624,8 @@ static void calculate_stream_scaling_settings(
- static void dm_dc_surface_commit(
- 		struct dc *dc,
- 		struct drm_crtc *crtc,
--		struct dm_connector_state *dm_state)
-+		struct dm_connector_state *dm_state
-+		)
- {
- 	struct dc_surface *dc_surface;
- 	const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-@@ -2023,6 +2024,38 @@ static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
- 	}
- }
- 
-+
-+typedef bool (*predicate)(struct amdgpu_crtc *acrtc);
-+
-+static void wait_while_pflip_status(struct amdgpu_device *adev,
-+		struct amdgpu_crtc *acrtc, predicate f) {
-+	int count = 0;
-+	while (f(acrtc)) {
-+		/* Spin Wait*/
-+		msleep(1);
-+		count++;
-+		if (count == 1000) {
-+			DRM_ERROR("%s - crtc:%d[%p], pflip_stat:%d, probable hang!\n",
-+										__func__, acrtc->crtc_id,
-+										acrtc,
-+										acrtc->pflip_status);
-+			BUG_ON(1);
-+		}
-+	}
-+
-+	DRM_DEBUG_DRIVER("%s - Finished waiting for:%d msec, crtc:%d[%p], pflip_stat:%d \n",
-+											__func__,
-+											count,
-+											acrtc->crtc_id,
-+											acrtc,
-+											acrtc->pflip_status);
-+}
-+
-+static bool pflip_in_progress_predicate(struct amdgpu_crtc *acrtc)
-+{
-+	return acrtc->pflip_status != AMDGPU_FLIP_NONE;
-+}
-+
- static void manage_dm_interrupts(
- 	struct amdgpu_device *adev,
- 	struct amdgpu_crtc *acrtc,
-@@ -2044,9 +2077,8 @@ static void manage_dm_interrupts(
- 			&adev->pageflip_irq,
- 			irq_type);
- 	} else {
--		while (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
--			msleep(1);
--		}
-+		wait_while_pflip_status(adev, acrtc,
-+				pflip_in_progress_predicate);
- 
- 		amdgpu_irq_put(
- 			adev,
-@@ -2056,6 +2088,12 @@ static void manage_dm_interrupts(
- 	}
- }
- 
-+
-+static bool pflip_pending_predicate(struct amdgpu_crtc *acrtc)
-+{
-+	return acrtc->pflip_status == AMDGPU_FLIP_PENDING;
-+}
-+
- int amdgpu_dm_atomic_commit(
- 	struct drm_device *dev,
- 	struct drm_atomic_state *state,
-@@ -2130,7 +2168,7 @@ int amdgpu_dm_atomic_commit(
- 					aconnector,
- 					&crtc->state->mode);
- 
--			DRM_INFO("Atomic commit: SET.\n");
-+			DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
- 
- 			if (!new_target) {
- 				/*
-@@ -2182,7 +2220,7 @@ int amdgpu_dm_atomic_commit(
- 
- 		case DM_COMMIT_ACTION_DPMS_OFF:
- 		case DM_COMMIT_ACTION_RESET:
--			DRM_INFO("Atomic commit: RESET.\n");
-+			DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
- 			/* i.e. reset mode */
- 			if (acrtc->target) {
- 				manage_dm_interrupts(adev, acrtc, false);
-@@ -2214,6 +2252,7 @@ int amdgpu_dm_atomic_commit(
- 	for_each_plane_in_state(state, plane, old_plane_state, i) {
- 		struct drm_plane_state *plane_state = plane->state;
- 		struct drm_crtc *crtc = plane_state->crtc;
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- 		struct drm_framebuffer *fb = plane_state->fb;
- 		struct drm_connector *connector;
- 		struct dm_connector_state *dm_state = NULL;
-@@ -2258,6 +2297,14 @@ int amdgpu_dm_atomic_commit(
- 			if (!dm_state)
- 				continue;
- 
-+			/*
-+			 * if flip is pending (ie, still waiting for fence to return
-+			 * before address is submitted) here, we cannot commit_surface
-+			 * as commit_surface will pre-maturely write out the future
-+			 * address. wait until flip is submitted before proceeding.
-+			 */
-+			wait_while_pflip_status(adev, acrtc, pflip_pending_predicate);
-+
- 			dm_dc_surface_commit(
- 				dm->dc,
- 				crtc,
-@@ -2367,6 +2414,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 		/* DC is optimized not to do anything if 'targets' didn't change. */
- 		dc_commit_targets(dc, commit_targets, commit_targets_count);
- 
-+
- 		dm_dc_surface_commit(dc, &disconnected_acrtc->base,
- 				to_dm_connector_state(
- 				connector->state));
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index c5aa460..e71088d 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -825,6 +825,7 @@ bool dc_commit_surfaces_to_target(
- 	if (core_dc->current_context.target_count == 0)
- 		return false;
- 
-+
- 	context = dm_alloc(sizeof(struct validate_context));
- 
- 	resource_validate_ctx_copy_construct(&core_dc->current_context, context);
-@@ -916,10 +917,14 @@ bool dc_commit_surfaces_to_target(
- 			dal_logger_write(core_dc->ctx->logger,
- 						LOG_MAJOR_INTERFACE_TRACE,
- 						LOG_MINOR_COMPONENT_DC,
--						"Pipe:%d 0x%x: src: %d, %d, %d,"
-+					   "Pipe:%d 0x%x: addr hi:0x%x, "
-+					   "addr low:0x%x, "
-+					   "src: %d, %d, %d,"
- 						" %d; dst: %d, %d, %d, %d;\n",
- 						pipe_ctx->pipe_idx,
- 						dc_surface,
-+					    dc_surface->address.grph.addr.high_part,
-+					    dc_surface->address.grph.addr.low_part,
- 						dc_surface->src_rect.x,
- 						dc_surface->src_rect.y,
- 						dc_surface->src_rect.width,
-@@ -951,6 +956,7 @@ bool dc_commit_surfaces_to_target(
- 						&context->pp_display_cfg);
- 	}
- 
-+
- 	resource_validate_ctx_destruct(&(core_dc->current_context));
- 	core_dc->current_context = *context;
- 	dm_free(context);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0996-drm-amd-dal-Fix-the-typo-in-apply_ctx_to_hw-reset-lo.patch b/common/recipes-kernel/linux/files/0996-drm-amd-dal-Fix-the-typo-in-apply_ctx_to_hw-reset-lo.patch
deleted file mode 100644
index a1d330e4..00000000
--- a/common/recipes-kernel/linux/files/0996-drm-amd-dal-Fix-the-typo-in-apply_ctx_to_hw-reset-lo.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From f0bad617ba038e6d8aae9a474728920e46ed9ded Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 31 Mar 2016 16:02:38 -0400
-Subject: [PATCH 0996/1110] drm/amd/dal: Fix the typo in apply_ctx_to_hw reset
- logic
-
-This fixes intermittent black screen on hotpluging second
-display on linux
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index e5cb1aa..df52740 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1194,7 +1194,7 @@ static enum dc_status apply_ctx_to_hw(
- 		 * since bios does optimization and doesn't apply if changing
- 		 * PHY when not already disabled.
- 		 */
--		if (pipe_ctx_old->stream && pipe_ctx_old->stream != pipe_ctx->stream)
-+		if (pipe_ctx_old->stream && !pipe_ctx->stream)
- 			reset_single_pipe_hw_ctx(
- 				dc, pipe_ctx_old, &dc->current_context);
- 		else if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0997-drm-amd-dal-Dump-EDID-data-one-block-per-line.patch b/common/recipes-kernel/linux/files/0997-drm-amd-dal-Dump-EDID-data-one-block-per-line.patch
deleted file mode 100644
index 2034aee6..00000000
--- a/common/recipes-kernel/linux/files/0997-drm-amd-dal-Dump-EDID-data-one-block-per-line.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 6cfd0ad4e3148a3480a90d38697a909cc8f048cf Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Fri, 1 Apr 2016 09:43:39 -0400
-Subject: [PATCH 0997/1110] drm/amd/dal: Dump EDID data one block per line.
-
-In case of EDID length is 384 bytes or more, it
-exceeds maximum line number limit for printk.
-Dump EDID data one block per line will solve the
-issue.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c |  3 +++
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c             | 10 ++++++----
- drivers/gpu/drm/amd/dal/dc/dc_types.h                 |  1 +
- 3 files changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index c6d6267..434fc5c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -549,6 +549,9 @@ void dm_helper_conn_log(struct dc_context *ctx,
- 		size--;
- 	}
- 
-+	if (hex_data_count > (CONN_MAX_LINE_SIZE - size))
-+		return;
-+
- 	if (hex_data) {
- 		int i;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 73dbf4f..4e57ed9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -680,10 +680,12 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
- 		}
- 
- 		/* Connectivity log: detection */
--		CONN_DATA_DETECT(link, sink->public.dc_edid.raw_edid,
--				sink->public.dc_edid.length,
--				"%s: ",
--				sink->public.edid_caps.display_name);
-+		for (i = 0; i < sink->public.dc_edid.length / EDID_BLOCK_SIZE; i++) {
-+			CONN_DATA_DETECT(link,
-+					&sink->public.dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
-+					EDID_BLOCK_SIZE,
-+					"%s: [Block %d] ", sink->public.edid_caps.display_name, i);
-+		}
- 
- 		dal_logger_write(link->ctx->logger,
- 			LOG_MAJOR_DETECTION,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 99da485..a375b00 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -165,6 +165,7 @@ enum bool_param_shift {
- };
- 
- #define MAX_EDID_BUFFER_SIZE 512
-+#define EDID_BLOCK_SIZE 128
- #define MAX_SURFACE_NUM 2
- #define NUM_PIXEL_FORMATS 10
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch b/common/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch
deleted file mode 100644
index 87c102fb..00000000
--- a/common/recipes-kernel/linux/files/0998-drm-amd-dal-fix-dce112-dp-clock-switching.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From a4e0f90b01fe5c4d25a62da00692da898477deac Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 31 Mar 2016 17:56:46 -0400
-Subject: [PATCH 0998/1110] drm/amd/dal: fix dce112 dp clock switching
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c |  2 +-
- drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 17 +++++++++++------
- 2 files changed, 12 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index df52740..47f75ef 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -339,7 +339,7 @@ static void dce110_crtc_switch_to_clk_src(
- 				DP_DTO0_ENABLE);
- 
- 		set_reg_field_value(pixel_rate_cntl_value,
--				clk_src->id - 1,
-+				clk_src->id - CLOCK_SOURCE_ID_PLL0,
- 				CRTC0_PIXEL_RATE_CNTL,
- 				CRTC0_PIXEL_RATE_SOURCE);
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-index b887764..931e47e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-@@ -231,8 +231,11 @@ static void dce112_crtc_switch_to_clk_src(
- 				struct clock_source *clk_src, uint8_t crtc_inst)
- {
- 	uint32_t pixel_rate_cntl_value;
--	uint32_t addr;
-+	uint32_t phypll_pixel_rate_cntl_value = 0;
-+	uint32_t addr, phypll_addr;
- 
-+	phypll_addr = mmCRTC0_PHYPLL_PIXEL_RATE_CNTL + crtc_inst *
-+		(mmCRTC1_PHYPLL_PIXEL_RATE_CNTL - mmCRTC0_PHYPLL_PIXEL_RATE_CNTL);
- 	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
- 			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
- 
-@@ -242,15 +245,17 @@ static void dce112_crtc_switch_to_clk_src(
- 		set_reg_field_value(pixel_rate_cntl_value, 1,
- 			CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
- 	else {
--		set_reg_field_value(pixel_rate_cntl_value,
--				0,
--				CRTC0_PIXEL_RATE_CNTL,
--				DP_DTO0_ENABLE);
- 
- 		set_reg_field_value(pixel_rate_cntl_value,
--				clk_src->id - 1,
-+				clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0,
- 				CRTC0_PIXEL_RATE_CNTL,
- 				CRTC0_PIXEL_RATE_SOURCE);
-+
-+		set_reg_field_value(phypll_pixel_rate_cntl_value,
-+				clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0,
-+				CRTC0_PHYPLL_PIXEL_RATE_CNTL,
-+				CRTC0_PHYPLL_PIXEL_RATE_SOURCE);
-+		dm_write_reg(clk_src->ctx, phypll_addr, phypll_pixel_rate_cntl_value);
- 	}
- 	dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0999-drm-amd-dal-Revert-disabling-stream-when-clock-sourc.patch b/common/recipes-kernel/linux/files/0999-drm-amd-dal-Revert-disabling-stream-when-clock-sourc.patch
deleted file mode 100644
index 72ae5c39..00000000
--- a/common/recipes-kernel/linux/files/0999-drm-amd-dal-Revert-disabling-stream-when-clock-sourc.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From b6e48541c1aa4b07a0f5610bd4ed26d2d7ad78f6 Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Fri, 1 Apr 2016 12:44:04 -0400
-Subject: [PATCH 0999/1110] drm/amd/dal: Revert disabling stream when clock
- source changes
-
-It causes other issues when timing doesn't change where the pipe is never re-enabled
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 47f75ef..c2adf6b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1197,8 +1197,6 @@ static enum dc_status apply_ctx_to_hw(
- 		if (pipe_ctx_old->stream && !pipe_ctx->stream)
- 			reset_single_pipe_hw_ctx(
- 				dc, pipe_ctx_old, &dc->current_context);
--		else if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
--			core_link_disable_stream(pipe_ctx);
- 	}
- 
- 	/* Skip applying if no targets */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1000-drm-amd-dal-handle-the-case-we-cannot-restore-connec.patch b/common/recipes-kernel/linux/files/1000-drm-amd-dal-handle-the-case-we-cannot-restore-connec.patch
deleted file mode 100644
index 8b44d5cb..00000000
--- a/common/recipes-kernel/linux/files/1000-drm-amd-dal-handle-the-case-we-cannot-restore-connec.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 0e45b09c8a813c15d96701c3daa5436cc358111f Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 1 Apr 2016 18:38:34 -0400
-Subject: [PATCH 1000/1110] drm/amd/dal: handle the case we cannot restore
- connector state
-
-If we unplug the last display and plug in a different one that does not
-support the timing set on the previous display, we can fail in
-dc_commit_targets, this was not properly handled and was causing a
-crash
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index d2548b6..0e19f8d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2412,7 +2412,14 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 		}
- 
- 		/* DC is optimized not to do anything if 'targets' didn't change. */
--		dc_commit_targets(dc, commit_targets, commit_targets_count);
-+		if (!dc_commit_targets(dc, commit_targets,
-+				commit_targets_count)) {
-+			DRM_INFO("Failed to restore connector state!\n");
-+			dc_target_release(disconnected_acrtc->target);
-+			disconnected_acrtc->target = NULL;
-+			disconnected_acrtc->enabled = false;
-+			return;
-+		}
- 
- 
- 		dm_dc_surface_commit(dc, &disconnected_acrtc->base,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1001-drm-amd-dal-set-timing_changed-flag-on-clk_src-chang.patch b/common/recipes-kernel/linux/files/1001-drm-amd-dal-set-timing_changed-flag-on-clk_src-chang.patch
deleted file mode 100644
index eececa74..00000000
--- a/common/recipes-kernel/linux/files/1001-drm-amd-dal-set-timing_changed-flag-on-clk_src-chang.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From c0f9ac327ed7caf044ce0b128fd571231f22e37c Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Fri, 1 Apr 2016 12:13:31 -0400
-Subject: [PATCH 1001/1110] drm/amd/dal: set timing_changed flag on clk_src
- change
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  3 +++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 23 ++++++++++++----------
- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    |  3 +++
- 3 files changed, 19 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 087670d..c2f16a9 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -1282,6 +1282,9 @@ enum dc_status resource_map_clock_resources(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
-+				if (dc->current_context.res_ctx.pipe_ctx[k].clock_source
-+					!= pipe_ctx->clock_source)
-+					pipe_ctx->flags.timing_changed = true;
- 				/* only one cs per stream regardless of mpo */
- 				break;
- 			}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index c2adf6b..53da396 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -673,27 +673,30 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		struct validate_context *context,
- 		struct core_dc *dc)
- {
-+	int i;
- 	struct core_stream *stream = pipe_ctx->stream;
--	struct pipe_ctx *old_pipe_ctx =
--		&dc->current_context.res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
- 	bool timing_changed = context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]
- 							.flags.timing_changed;
- 	enum dc_color_space color_space;
- 
-+	struct pipe_ctx *pipe_ctx_old = NULL;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (dc->current_context.res_ctx.pipe_ctx[i].stream == pipe_ctx->stream)
-+			pipe_ctx_old = &dc->current_context.res_ctx.pipe_ctx[i];
-+	}
-+
- 	if (timing_changed) {
- 		/* Must blank CRTC after disabling power gating and before any
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
- 		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
- 
--		/*
--		 * only disable stream in case it was ever enabled
--		 */
--		if (old_pipe_ctx->stream) {
--			core_link_disable_stream(old_pipe_ctx);
--
--			ASSERT(old_pipe_ctx->clock_source);
--			resource_unreference_clock_source(&dc->current_context.res_ctx, old_pipe_ctx->clock_source);
-+		if (pipe_ctx_old) {
-+			core_link_disable_stream(pipe_ctx);
-+			resource_unreference_clock_source(
-+						&dc->current_context.res_ctx,
-+						pipe_ctx_old->clock_source);
- 		}
- 
- 		/*TODO: AUTO check if timing changed*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-index 7b3dee1..c1fb291 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-@@ -1022,6 +1022,9 @@ static enum dc_status map_clock_resources(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
-+				if (pipe_ctx->clock_source
-+					!= dc->current_context.res_ctx.pipe_ctx[k].clock_source)
-+					pipe_ctx->flags.timing_changed = true;
- 				/* only one cs per stream regardless of mpo */
- 				break;
- 			}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1002-drm-amd-dal-fix-target-duplication-during-target-res.patch b/common/recipes-kernel/linux/files/1002-drm-amd-dal-fix-target-duplication-during-target-res.patch
deleted file mode 100644
index db63a075..00000000
--- a/common/recipes-kernel/linux/files/1002-drm-amd-dal-fix-target-duplication-during-target-res.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 498fe7891c7983dee32ccfc3ba6c8d0720717636 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Mon, 4 Apr 2016 17:05:54 -0400
-Subject: [PATCH 1002/1110] drm/amd/dal: fix target duplication during target
- reset
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 17 ++++++++---------
- drivers/gpu/drm/amd/dal/dc/core/dc_surface.c        |  1 +
- 2 files changed, 9 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 0e19f8d..a21d634 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2481,25 +2481,24 @@ static uint32_t remove_from_val_sets(
- 	uint32_t set_count,
- 	const struct dc_target *target)
- {
--	uint32_t i = 0;
-+	int i;
- 
--	while (i < set_count) {
-+	for (i = 0; i < set_count; i++)
- 		if (val_sets[i].target == target)
- 			break;
--		++i;
--	}
- 
- 	if (i == set_count) {
- 		/* nothing found */
- 		return set_count;
- 	}
- 
--	memmove(
--		&val_sets[i],
--		&val_sets[i + 1],
--		sizeof(struct dc_validation_set *) * (set_count - i - 1));
-+	set_count--;
-+
-+	for (; i < set_count; i++) {
-+		val_sets[i] = val_sets[i + 1];
-+	}
- 
--	return set_count - 1;
-+	return set_count;
- }
- 
- int amdgpu_dm_atomic_check(struct drm_device *dev,
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-index 5c586ba..d688bc2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_surface.c
-@@ -112,6 +112,7 @@ void dc_surface_retain(const struct dc_surface *dc_surface)
- void dc_surface_release(const struct dc_surface *dc_surface)
- {
- 	struct surface *surface = DC_SURFACE_TO_SURFACE(dc_surface);
-+
- 	--surface->ref_count;
- 
- 	if (surface->ref_count == 0) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1003-drm-amd-dal-keep-the-old-target-if-commit-fail-for-h.patch b/common/recipes-kernel/linux/files/1003-drm-amd-dal-keep-the-old-target-if-commit-fail-for-h.patch
deleted file mode 100644
index 43d50bab..00000000
--- a/common/recipes-kernel/linux/files/1003-drm-amd-dal-keep-the-old-target-if-commit-fail-for-h.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 241c93fd927bc959a80bddf085147356ff4f4ceb Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Mon, 4 Apr 2016 10:57:43 -0400
-Subject: [PATCH 1003/1110] drm/amd/dal: keep the old target if commit fail for
- headless
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 9 ++++++---
- 1 file changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a21d634..a091d97 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2363,6 +2363,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 	struct amdgpu_crtc *disconnected_acrtc;
- 	const struct dc_sink *sink;
- 	struct dc_target *commit_targets[6];
-+	struct dc_target *current_target;
- 	uint32_t commit_targets_count = 0;
- 
- 
-@@ -2394,7 +2395,8 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 		 */
- 		manage_dm_interrupts(adev, disconnected_acrtc, false);
- 		/* this is the update mode case */
--		dc_target_release(disconnected_acrtc->target);
-+
-+		current_target = disconnected_acrtc->target;
- 
- 		disconnected_acrtc->target = new_target;
- 		disconnected_acrtc->enabled = true;
-@@ -2416,11 +2418,12 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 				commit_targets_count)) {
- 			DRM_INFO("Failed to restore connector state!\n");
- 			dc_target_release(disconnected_acrtc->target);
--			disconnected_acrtc->target = NULL;
--			disconnected_acrtc->enabled = false;
-+			disconnected_acrtc->target = current_target;
-+			manage_dm_interrupts(adev, disconnected_acrtc, true);
- 			return;
- 		}
- 
-+		dc_target_release(current_target);
- 
- 		dm_dc_surface_commit(dc, &disconnected_acrtc->base,
- 				to_dm_connector_state(
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1004-drm-amd-dal-Fix-incorrect-max-size-of-validation-arr.patch b/common/recipes-kernel/linux/files/1004-drm-amd-dal-Fix-incorrect-max-size-of-validation-arr.patch
deleted file mode 100644
index e8ae8725..00000000
--- a/common/recipes-kernel/linux/files/1004-drm-amd-dal-Fix-incorrect-max-size-of-validation-arr.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-From dc3a2c4818810b2dc5be400943da7dbf802482da Mon Sep 17 00:00:00 2001
-From: Jordan Lazare <Jordan.Lazare@amd.com>
-Date: Mon, 4 Apr 2016 19:43:13 -0400
-Subject: [PATCH 1004/1110] drm/amd/dal: Fix incorrect max size of validation
- array
-
-Was leading to stack corruption with >4 displays
-
-Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 12 ++++--------
- drivers/gpu/drm/amd/dal/dc/core/dc.c                |  2 +-
- drivers/gpu/drm/amd/dal/dc/dc.h                     |  4 +++-
- 3 files changed, 8 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index a091d97..8ad78f5 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -58,7 +58,6 @@ struct dm_connector_state {
- 	container_of((x), struct dm_connector_state, base)
- 
- #define AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET 1
--#define MAX_TARGET_NUM 6
- 
- void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
- {
-@@ -813,9 +812,6 @@ static void fill_audio_info(
- 
- }
- 
--/*TODO: move these defines elsewhere*/
--#define DAL_MAX_CONTROLLERS 4
--
- static void copy_crtc_timing_for_drm_display_mode(
- 		const struct drm_display_mode *src_mode,
- 		struct drm_display_mode *dst_mode)
-@@ -2110,8 +2106,8 @@ int amdgpu_dm_atomic_commit(
- 	struct drm_crtc *crtc;
- 	struct drm_crtc_state *old_crtc_state;
- 
--	struct dc_target *commit_targets[DAL_MAX_CONTROLLERS];
--	struct amdgpu_crtc *new_crtcs[DAL_MAX_CONTROLLERS];
-+	struct dc_target *commit_targets[MAX_TARGETS];
-+	struct amdgpu_crtc *new_crtcs[MAX_TARGETS];
- 
- 	/* In this step all new fb would be pinned */
- 
-@@ -2516,8 +2512,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
- 	int ret;
- 	int set_count;
- 	int new_target_count;
--	struct dc_validation_set set[MAX_TARGET_NUM] = {{ 0 }};
--	struct dc_target *new_targets[MAX_TARGET_NUM] = { 0 };
-+	struct dc_validation_set set[MAX_TARGETS] = {{ 0 }};
-+	struct dc_target *new_targets[MAX_TARGETS] = { 0 };
- 	struct amdgpu_device *adev = dev->dev_private;
- 	struct dc *dc = adev->dm.dc;
- 	bool need_to_validate = false;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e71088d..d49ab5e 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -720,7 +720,7 @@ bool dc_commit_targets(
- 	struct dc_bios *dcb = core_dc->ctx->dc_bios;
- 	enum dc_status result = DC_ERROR_UNEXPECTED;
- 	struct validate_context *context;
--	struct dc_validation_set set[4];
-+	struct dc_validation_set set[MAX_TARGETS];
- 	uint8_t i;
- 
- 	if (false == targets_changed(core_dc, targets, target_count))
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index e394dd2..dbc972f 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -33,6 +33,8 @@
- #include "gpio_types.h"
- #include "link_service_types.h"
- 
-+#define MAX_TARGETS 6
-+#define MAX_SURFACES 6
- #define MAX_SINKS_PER_LINK 4
- 
- /*******************************************************************************
-@@ -271,7 +273,7 @@ enum dc_irq_source dc_target_get_irq_src(
-  */
- struct dc_validation_set {
- 	const struct dc_target *target;
--	const struct dc_surface *surfaces[4];
-+	const struct dc_surface *surfaces[MAX_SURFACES];
- 	uint8_t surface_count;
- };
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1005-drm-amd-dal-remove-dead-functions-prototype.patch b/common/recipes-kernel/linux/files/1005-drm-amd-dal-remove-dead-functions-prototype.patch
deleted file mode 100644
index 0f0963f9..00000000
--- a/common/recipes-kernel/linux/files/1005-drm-amd-dal-remove-dead-functions-prototype.patch
+++ /dev/null
@@ -1,1112 +0,0 @@
-From 64dd77f7a0886fdc805c8fcbe63d45e4e964aed4 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>
-Date: Thu, 24 Mar 2016 13:49:45 +0100
-Subject: [PATCH 1005/1110] drm/amd/dal: remove dead functions prototype.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Seriously ...
-
-Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h    |   5 -
- drivers/gpu/drm/amd/dal/dal_services.h             |  12 -
- drivers/gpu/drm/amd/dal/dc/audio/audio.h           |   4 -
- drivers/gpu/drm/amd/dal/dc/dc.h                    |   2 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h  |   5 -
- .../gpu/drm/amd/dal/dc/dce110/dce110_transform.h   |   5 -
- .../amd/dal/dc/dce110/dce110_transform_bit_depth.h |   4 -
- .../gpu/drm/amd/dal/dc/dce112/dce112_compressor.h  |   5 -
- .../gpu/drm/amd/dal/dc/dce80/dce80_compressor.h    |   5 -
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h |   5 -
- drivers/gpu/drm/amd/dal/dc/dm_services.h           |  10 -
- .../drm/amd/dal/include/bios_parser_interface.h    |  19 --
- .../drm/amd/dal/include/display_path_interface.h   | 249 ---------------------
- drivers/gpu/drm/amd/dal/include/dmcu_interface.h   |  38 ----
- .../gpu/drm/amd/dal/include/encoder_interface.h    |  16 --
- .../drm/amd/dal/include/hw_sequencer_interface.h   | 146 ------------
- .../drm/amd/dal/include/link_service_interface.h   | 144 ------------
- 17 files changed, 674 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-index 8f65194..7b400d1 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
-@@ -50,11 +50,6 @@ void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc);
- void amdgpu_dm_connector_destroy(struct drm_connector *connector);
- void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);
- 
--void dm_add_display_info(
--	struct drm_display_info *disp_info,
--	struct amdgpu_display_manager *dm,
--	uint32_t display_index);
--
- int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
- 
- int amdgpu_dm_atomic_commit(
-diff --git a/drivers/gpu/drm/amd/dal/dal_services.h b/drivers/gpu/drm/amd/dal/dal_services.h
-index 398e4e5..fbd1fb2 100644
---- a/drivers/gpu/drm/amd/dal/dal_services.h
-+++ b/drivers/gpu/drm/amd/dal/dal_services.h
-@@ -61,14 +61,8 @@ void dal_register_timer_interrupt(
- /* Reallocate memory. The contents will remain unchanged.*/
- void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size);
- 
--void dc_service_memmove(void *dst, const void *src, uint32_t size);
--
- void dc_service_memset(void *p, int32_t c, uint32_t count);
- 
--int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count);
--
--int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count);
--
- /*
-  *
-  * GPU registers access
-@@ -178,11 +172,6 @@ struct platform_info_ext_brightness_caps {
- 	uint8_t	max_input_signal;
- };
- 
--bool dal_get_platform_info(
--	struct dc_context *ctx,
--	struct platform_info_params *params);
--
--
- static inline uint32_t dal_bios_cmd_table_para_revision(
- 	struct dc_context *ctx,
- 	uint32_t index)
-@@ -255,7 +244,6 @@ bool dal_exec_bios_cmd_table(
- 	vsnprintf(buffer, size, fmt, args)
- 
- long dal_get_pid(void);
--long dal_get_tgid(void);
- 
- /*
-  *
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio.h b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-index 7ca71eb..bf09a13 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
-@@ -186,8 +186,4 @@ bool dal_audio_construct_base(
- void dal_audio_destruct_base(
- 	struct audio *audio);
- 
--void dal_audio_release_hw_base(
--	struct audio *audio);
--
- #endif  /* __DAL_AUDIO__ */
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index dbc972f..d5bb183 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -250,8 +250,6 @@ bool dc_target_is_connected_to_sink(
- 		const struct dc_target *dc_target,
- 		const struct dc_sink *dc_sink);
- 
--uint8_t dc_target_get_controller_id(const struct dc_target *dc_target);
--
- uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target);
- 
- /* TODO: Return parsed values rather than direct register read
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
-index 0beef22..86c30d4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
-@@ -63,11 +63,6 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
- 	struct compressor *cp,
- 	struct compr_addr_and_pitch_params *params);
- 
--bool dce110_compressor_get_required_compressed_surface_size(
--	struct compressor *cp,
--	struct fbc_input_info *input_info,
--	struct fbc_requested_compressed_size *size);
--
- bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
- 	uint32_t *fbc_mapped_crtc_id);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index e906fbf..f97d7ab 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -58,11 +58,6 @@ bool dce110_transform_set_scaler(
- 
- void dce110_transform_set_scaler_bypass(struct transform *xfm);
- 
--bool dce110_transform_update_viewport(
--	struct transform *xfm,
--	const struct rect *view_port,
--	bool is_fbc_attached);
--
- void dce110_transform_set_scaler_filter(
- 	struct transform *xfm,
- 	struct scaler_filter *filter);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
-index ff100cc..71f1c3a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
-@@ -35,10 +35,6 @@ bool dce110_transform_get_max_num_of_supported_lines(
- 	uint32_t pixel_width,
- 	uint32_t *lines);
- 
--void dce110_transform_enable_alpha(
--	struct dce110_transform *xfm110,
--	bool enable);
--
- bool dce110_transform_get_next_lower_pixel_storage_depth(
- 	struct dce110_transform *xfm110,
- 	uint32_t display_bpp,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
-index bcf4480..6a0efe8 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
-@@ -63,11 +63,6 @@ void dce112_compressor_program_compressed_surface_address_and_pitch(
- 	struct compressor *cp,
- 	struct compr_addr_and_pitch_params *params);
- 
--bool dce112_compressor_get_required_compressed_surface_size(
--	struct compressor *cp,
--	struct fbc_input_info *input_info,
--	struct fbc_requested_compressed_size *size);
--
- bool dce112_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
- 	uint32_t *fbc_mapped_crtc_id);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
-index 8254118..f5f357c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
-@@ -63,11 +63,6 @@ void dce80_compressor_program_compressed_surface_address_and_pitch(
- 	struct compressor *cp,
- 	struct compr_addr_and_pitch_params *params);
- 
--bool dce80_compressor_get_required_compressed_surface_size(
--	struct compressor *cp,
--	struct fbc_input_info *input_info,
--	struct fbc_requested_compressed_size *size);
--
- bool dce80_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
- 	uint32_t *fbc_mapped_crtc_id);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-index b719546..58b3ee4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -58,11 +58,6 @@ bool dce80_transform_set_scaler(
- 
- void dce80_transform_set_scaler_bypass(struct transform *xfm);
- 
--bool dce80_transform_update_viewport(
--	struct transform *xfm,
--	const struct rect *view_port,
--	bool is_fbc_attached);
--
- void dce80_transform_set_scaler_filter(
- 	struct transform *xfm,
- 	struct scaler_filter *filter);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-index 4c45a66..5347371 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
-@@ -48,10 +48,6 @@ irq_handler_idx dm_register_interrupt(
- 	interrupt_handler ih,
- 	void *handler_args);
- 
--void dm_unregister_interrupt(
--	struct dc_context *ctx,
--	enum dc_irq_source irq_source,
--	irq_handler_idx handler_idx);
- 
- /*
-  *
-@@ -156,12 +152,6 @@ bool dm_exec_bios_cmd_table(
- uint32_t dm_bios_cmd_table_para_revision(
- struct dc_context *ctx,
- 	uint32_t index);
--
--bool dm_bios_cmd_table_revision(
--	struct dc_context *ctx,
--	uint32_t index,
--	uint8_t *frev,
--	uint8_t *crev);
- #endif
- 
- #ifndef BUILD_DAL_TEST
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-index e4291b9..d589e8d 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -51,8 +51,6 @@ bool dal_bios_parser_is_lid_status_changed(
- 	struct bios_parser *bp);
- bool dal_bios_parser_is_display_config_changed(
- 	struct bios_parser *bp);
--bool dal_bios_parser_is_accelerated_mode(
--	struct bios_parser *bp);
- void dal_bios_parser_set_scratch_lcd_scale(
- 	struct bios_parser *bp,
- 	enum lcd_scale scale);
-@@ -77,22 +75,5 @@ enum controller_id dal_bios_parser_get_embedded_display_controller_id(
- 	struct bios_parser *bp);
- uint32_t dal_bios_parser_get_embedded_display_refresh_rate(
- 	struct bios_parser *bp);
--void dal_bios_parser_set_scratch_connected(
--	struct bios_parser *bp,
--	struct graphics_object_id connector_id,
--	bool connected,
--	const struct connector_device_tag_info *device_tag);
--void dal_bios_parser_prepare_scratch_active_and_requested(
--	struct bios_parser *bp,
--	enum controller_id controller_id,
--	enum signal_type signal,
--	const struct connector_device_tag_info *device_tag);
--void dal_bios_parser_set_scratch_active_and_requested(
--	struct bios_parser *bp);
--void dal_bios_parser_set_scratch_critical_state(
--	struct bios_parser *bp,
--	bool state);
--void dal_bios_parser_set_scratch_acc_mode_change(
--	struct bios_parser *bp);
- 
- #endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/display_path_interface.h b/drivers/gpu/drm/amd/dal/include/display_path_interface.h
-index 7bf2ef2..73831be 100644
---- a/drivers/gpu/drm/amd/dal/include/display_path_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_path_interface.h
-@@ -49,186 +49,37 @@ struct display_path *dal_display_path_clone(
- 	const struct display_path *self,
- 	bool copy_active_state);
- 
--void dal_display_path_destroy(
--	struct display_path **to_destroy);
--
--bool dal_display_path_validate(
--	struct display_path *path,
--	enum signal_type sink_signal);
--
--bool dal_display_path_add_link(
--	struct display_path *path,
--	struct encoder *encoder);
--
--bool dal_display_path_add_connector(
--	struct display_path *path,
--	struct connector *connector);
--
- struct connector *dal_display_path_get_connector(
- 	struct display_path *path);
- 
--int32_t dal_display_path_acquire(
--	struct display_path *path);
--
--bool dal_display_path_is_acquired(
--	const struct display_path *path);
--
--int32_t dal_display_path_get_ref_counter(
--	const struct display_path *path);
--
--int32_t dal_display_path_release(
--	struct display_path *path);
--
--void dal_display_path_release_resources(
--	struct display_path *path);
--
--void dal_display_path_acquire_links(
--	struct display_path *path);
--
--bool dal_display_path_is_source_blanked(
--	const struct display_path *path);
--
--bool dal_display_path_is_source_unblanked(
--	const struct display_path *path);
--
--void dal_display_path_set_source_blanked(
--	struct display_path *path,
--	enum display_tri_state state);
--
--bool dal_display_path_is_target_blanked(
--	const struct display_path *path);
--
--bool dal_display_path_is_target_unblanked(
--	const struct display_path *path);
--
--void dal_display_path_set_target_blanked(
--	struct display_path *path,
--	enum display_tri_state state);
--
--bool dal_display_path_is_target_powered_on(
--	const struct display_path *path);
--
--bool dal_display_path_is_target_powered_off(
--	const struct display_path *path);
--
--void dal_display_path_set_target_powered_on(
--	struct display_path *path,
--	enum display_tri_state state);
--
--bool dal_display_path_is_target_connected(
--	const struct display_path *path);
--
--void dal_display_path_set_target_connected(
--	struct display_path *path,
--	bool c);
--
--uint32_t dal_display_path_get_display_index(
--	const struct display_path *path);
--
--void dal_display_path_set_display_index(
--	struct display_path *path,
--	uint32_t index);
--
- struct connector_device_tag_info *dal_display_path_get_device_tag(
- 	struct display_path *path);
- 
--void dal_display_path_set_device_tag(
--	struct display_path *path,
--	struct connector_device_tag_info tag);
--
- enum clock_sharing_group dal_display_path_get_clock_sharing_group(
- 	const struct display_path *path);
- 
--void dal_display_path_set_clock_sharing_group(
--	struct display_path *path,
--	enum clock_sharing_group clock);
--
- union display_path_properties dal_display_path_get_properties(
- 	const struct display_path *path);
- 
--void dal_display_path_set_properties(
--	struct display_path *path,
--	union display_path_properties p);
--
- struct dcs *dal_display_path_get_dcs(
- 	const struct display_path *path);
- 
--void dal_display_path_set_dcs(
--	struct display_path *path,
--	struct dcs *dcs);
--
--uint32_t dal_display_path_get_number_of_links(
--	const struct display_path *path);
--
--void dal_display_path_set_controller(
--	struct display_path *path,
--	struct controller *controller);
--
- struct controller *dal_display_path_get_controller(
- 	const struct display_path *path);
- 
--void dal_display_path_set_clock_source(
--	struct display_path *path,
--	struct clock_source *clock);
--
- struct clock_source *dal_display_path_get_clock_source(
- 	const struct display_path *path);
- 
--void dal_display_path_set_alt_clock_source(
--	struct display_path *path,
--	struct clock_source *clock);
--
- struct clock_source *dal_display_path_get_alt_clock_source(
- 	const struct display_path *path);
- 
--void dal_display_path_set_fbc_info(
--	struct display_path *path,
--	struct fbc_info *clock);
--
- struct fbc_info *dal_display_path_get_fbc_info(
- 	struct display_path *path);
- 
--void dal_display_path_set_drr_config(
--	struct display_path *path,
--	struct drr_config *clock);
--
--void dal_display_path_get_drr_config(
--	const struct display_path *path,
--	struct drr_config *clock);
--
--void dal_display_path_set_static_screen_triggers(
--	struct display_path *path,
--	const struct static_screen_events *events);
--
--void dal_display_path_get_static_screen_triggers(
--	const struct display_path *path,
--	struct static_screen_events *events);
--
--bool dal_display_path_is_psr_supported(
--	const struct display_path *path);
--
--bool dal_display_path_is_drr_supported(
--	const struct display_path *path);
--
--void dal_display_path_set_link_service_data(
--	struct display_path *path,
--	uint32_t idx,
--	const struct goc_link_service_data *data);
--
--bool dal_display_path_get_link_service_data(
--	const struct display_path *path,
--	uint32_t idx,
--	struct goc_link_service_data *data);
--
- struct link_service *dal_display_path_get_link_query_interface(
- 	const struct display_path *path,
- 	uint32_t idx);
- 
--void dal_display_path_set_link_query_interface(
--	struct display_path *path,
--	uint32_t idx,
--	struct link_service *link);
--
- struct link_service *dal_display_path_get_link_config_interface(
- 	const struct display_path *path,
- 	uint32_t idx);
-@@ -257,38 +108,14 @@ struct audio *dal_display_path_get_audio(
- 	const struct display_path *path,
- 	uint32_t idx);
- 
--void dal_display_path_set_audio(
--	struct display_path *path,
--	uint32_t idx,
--	struct audio *a);
--
- struct audio *dal_display_path_get_audio_object(
- 	const struct display_path *path,
- 	uint32_t idx);
- 
--void dal_display_path_set_audio_active_state(
--	struct display_path *path,
--	uint32_t idx,
--	bool state);
--
- enum engine_id dal_display_path_get_stream_engine(
- 	const struct display_path *path,
- 	uint32_t idx);
- 
--void dal_display_path_set_stream_engine(
--	struct display_path *path,
--	uint32_t idx,
--	enum engine_id id);
--
--bool dal_display_path_is_link_active(
--	const struct display_path *path,
--	uint32_t idx);
--
--void dal_display_path_set_link_active_state(
--	struct display_path *path,
--	uint32_t idx,
--	bool state);
--
- enum signal_type dal_display_path_get_config_signal(
- 	const struct display_path *path,
- 	uint32_t idx);
-@@ -300,50 +127,18 @@ enum signal_type dal_display_path_get_query_signal(
- struct link_service *dal_display_path_get_mst_link_service(
- 	const struct display_path *path);
- 
--void dal_display_path_set_sync_output_object(
--	struct display_path *path,
--	enum sync_source o_source,
--	struct encoder *o_object);
--
- struct encoder *dal_display_path_get_sync_output_object(
- 	const struct display_path *path);
- 
--void dal_display_path_set_stereo_sync_object(
--	struct display_path *path,
--	struct encoder *stereo_sync);
--
- struct encoder *dal_display_path_get_stereo_sync_object(
- 	const struct display_path *path);
- 
--void dal_display_path_set_sync_input_source(
--	struct display_path *path,
--	enum sync_source s);
--
- enum sync_source dal_display_path_get_sync_input_source(
- 	const struct display_path *path);
- 
--void dal_display_path_set_sync_output_source(
--	struct display_path *path,
--	enum sync_source s);
--
- enum sync_source dal_display_path_get_sync_output_source(
- 	const struct display_path *path);
- 
--bool dal_display_path_set_pixel_clock_safe_range(
--	struct display_path *path,
--	struct pixel_clock_safe_range *range);
--
--bool dal_display_path_get_pixel_clock_safe_range(
--	const struct display_path *path,
--	struct pixel_clock_safe_range *range);
--
--void dal_display_path_set_ddi_channel_mapping(
--	struct display_path *path,
--	union ddi_channel_mapping mapping);
--
--bool dal_display_path_set_sink_signal(
--	struct display_path *path,
--	enum signal_type sink_signal);
- 
- enum signal_type dal_display_path_sink_signal_to_asic_signal(
- 	struct display_path *path,
-@@ -359,44 +154,13 @@ enum signal_type dal_display_path_downstream_to_upstream_signal(
- 	enum signal_type signal,
- 	uint32_t idx);
- 
--bool dal_display_path_is_audio_present(
--	const struct display_path *path,
--	uint32_t *audio_pin);
--
--bool dal_display_path_is_dp_auth_supported(
--	struct display_path *path);
--
--bool dal_display_path_is_vce_supported(
--	const struct display_path *path);
--
--bool dal_display_path_is_sls_capable(
--	const struct display_path *path);
--
--bool dal_display_path_is_gen_lock_capable(
--	const struct display_path *path);
--
--struct transmitter_configuration dal_display_path_get_transmitter_configuration(
--	const struct display_path *path,
--	bool physical);
--
- bool dal_display_path_is_ss_supported(
- 	const struct display_path *path);
- 
--bool dal_display_path_is_ss_configurable(
--	const struct display_path *path);
--
--void dal_display_path_set_ss_support(
--	struct display_path *path,
--	bool s);
--
- enum signal_type dal_display_path_get_active_signal(
- 	struct display_path *path,
- 	uint32_t idx);
- 
--bool dal_display_path_contains_object(
--	struct display_path *path,
--	struct graphics_object_id id);
--
- /* Multi-plane declarations.
-  * This structure should also be used for Stereo. */
- struct display_path_plane {
-@@ -412,13 +176,6 @@ struct display_path_plane {
- 	bool disabled;
- };
- 
--bool dal_display_path_add_plane(
--	struct display_path *path,
--	struct display_path_plane *plane);
--
--uint8_t dal_display_path_get_number_of_planes(
--	const struct display_path *path);
--
- struct display_path_plane *dal_display_path_get_plane_at_index(
- 	const struct display_path *path,
- 	uint8_t index);
-@@ -427,10 +184,4 @@ struct controller *dal_display_path_get_controller_for_layer_index(
- 	const struct display_path *path,
- 	uint8_t layer_index);
- 
--void dal_display_path_release_planes(
--	struct display_path *path);
--
--void dal_display_path_release_non_root_planes(
--	struct display_path *path);
--
- #endif /* __DISPLAY_PATH_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_interface.h b/drivers/gpu/drm/amd/dal/include/dmcu_interface.h
-index c712cc2..78709a7 100644
---- a/drivers/gpu/drm/amd/dal/include/dmcu_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/dmcu_interface.h
-@@ -34,54 +34,16 @@
- /* DMCU setup related interface functions */
- struct dmcu *dal_dmcu_create(
- 	struct dmcu_init_data *init_data);
--void dal_dmcu_destroy(struct dmcu **dmcu);
--void dal_dmcu_release_hw(struct dmcu *dmcu);
--
--void dal_dmcu_power_up(struct dmcu *dmcu);
--void dal_dmcu_power_down(struct dmcu *dmcu);
--
--void dal_dmcu_configure_wait_loop(
--		struct dmcu *dmcu,
--		uint32_t display_clock);
- 
- /* PSR feature related interface functions */
- void dal_dmcu_psr_setup(
- 		struct dmcu *dmcu,
- 		struct dmcu_context *dmcu_context);
--void dal_dmcu_psr_enable(struct dmcu *dmcu);
--void dal_dmcu_psr_disable(struct dmcu *dmcu);
--void dal_dmcu_psr_block(struct dmcu *dmcu, bool block_psr);
--bool dal_dmcu_psr_is_blocked(struct dmcu *dmcu);
--void dal_dmcu_psr_set_level(
--		struct dmcu *dmcu,
--		union dmcu_psr_level psr_level);
--void dal_dmcu_psr_allow_power_down_crtc(
--		struct dmcu *dmcu,
--		bool should_allow_crtc_power_down);
--bool dal_dmcu_psr_submit_command(
--		struct dmcu *dmcu,
--		struct dmcu_context *dmcu_context,
--		struct dmcu_config_data *config_data);
--void dal_dmcu_psr_get_config_data(
--		struct dmcu *dmcu,
--		uint32_t v_total,
--		struct dmcu_config_data *config_data);
- 
- /* ABM feature related interface functions */
- void dal_dmcu_abm_enable(
- 		struct dmcu *dmcu,
- 		enum controller_id controller_id,
- 		uint32_t vsync_rate_hz);
--void dal_dmcu_abm_disable(struct dmcu *dmcu);
--bool dal_dmcu_abm_enable_smooth_brightness(struct dmcu *dmcu);
--bool dal_dmcu_abm_disable_smooth_brightness(struct dmcu *dmcu);
--void dal_dmcu_abm_varibright_control(
--		struct dmcu *dmcu,
--		const struct varibright_control *varibright_control);
--bool dal_dmcu_abm_set_backlight_level(
--		struct dmcu *dmcu,
--		uint8_t backlight_8_bit);
--uint8_t dal_dmcu_abm_get_user_backlight_level(struct dmcu *dmcu);
--uint8_t dal_dmcu_abm_get_current_backlight_level(struct dmcu *dmcu);
- 
- #endif /* __DAL_DMCU_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/encoder_interface.h b/drivers/gpu/drm/amd/dal/include/encoder_interface.h
-index 5fbf816..311ccf8 100644
---- a/drivers/gpu/drm/amd/dal/include/encoder_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/encoder_interface.h
-@@ -62,20 +62,6 @@ const struct graphics_object_id dal_encoder_get_graphics_object_id(
-  */
- uint32_t dal_encoder_enumerate_input_signals(
- 	const struct encoder *enc);
--uint32_t dal_encoder_enumerate_output_signals(
--	const struct encoder *enc);
--bool dal_encoder_is_input_signal_supported(
--	const struct encoder *enc,
--	enum signal_type signal);
--bool dal_encoder_is_output_signal_supported(
--	const struct encoder *enc,
--	enum signal_type signal);
--void dal_encoder_set_input_signals(
--	struct encoder *enc,
--	uint32_t signals);
--void dal_encoder_set_output_signals(
--	struct encoder *enc,
--	uint32_t signals);
- 
- /*
-  * Programming interface
-@@ -143,7 +129,6 @@ enum encoder_result dal_encoder_set_dp_phy_pattern(
- 	struct encoder *enc,
- 	const struct encoder_set_dp_phy_pattern_param *param);
- 
--void dal_encoder_release_hw(struct encoder *enc);
- /*
-  * Information interface
-  */
-@@ -238,7 +223,6 @@ enum encoder_result dal_encoder_enable_stream(
- enum encoder_result dal_encoder_disable_stream(
- 	struct encoder *enc,
- 	enum engine_id engine);
--void dal_encoder_set_multi_path(struct encoder *enc, bool is_multi_path);
- /*
-  * Test harness
-  */
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-index ddd78d6..4238eb0 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-@@ -99,16 +99,6 @@ struct hw_path_mode;
- struct hwss_build_params;
- struct controller;
- 
--void dal_hw_sequencer_mute_audio_endpoint(
--	struct hw_sequencer *hws,
--	struct display_path *display_path,
--	bool mute);
--
--void dal_hw_sequencer_enable_audio_endpoint(
--	struct hw_sequencer *hws,
--	struct link_settings *ls,
--	struct display_path *display_path,
--	bool enable);
- 
- enum hwss_result dal_hw_sequencer_reset_audio_device(
- 	struct hw_sequencer *hws,
-@@ -118,11 +108,6 @@ enum hwss_result dal_hw_sequencer_validate_link(
- 	struct hw_sequencer *hws,
- 	const struct validate_link_param *param);
- 
--bool dal_hw_sequencer_is_supported_dp_training_pattern3(
--	struct hw_sequencer *hws,
--	struct display_path *display_path,
--	uint32_t link_idx);
--
- enum hwss_result dal_hw_sequencer_set_dp_phy_pattern(
- 	struct hw_sequencer *hws,
- 	const struct set_dp_phy_pattern_param *param);
-@@ -132,35 +117,6 @@ enum hwss_result dal_hw_sequencer_set_lane_settings(
- 	struct display_path *display_path,
- 	const struct link_training_settings *link_settings);
- 
--void dal_hw_sequencer_set_test_pattern(
--	struct hw_sequencer *hws,
--	struct hw_path_mode *path_mode,
--	enum dp_test_pattern test_pattern,
--	const struct link_training_settings *link_settings,
--	const uint8_t *custom_pattern,
--	uint8_t cust_pattern_size);
--
--bool dal_hw_sequencer_has_audio_bandwidth_changed(
--	struct hw_sequencer *hws,
--	const struct hw_path_mode *old,
--	const struct hw_path_mode *new);
--
--void dal_hw_sequencer_enable_azalia_audio_jack_presence(
--	struct hw_sequencer *hws,
--	struct display_path *display_path);
--
--void dal_hw_sequencer_disable_azalia_audio_jack_presence(
--	struct hw_sequencer *hws,
--	struct display_path *display_path);
--
--void dal_hw_sequencer_enable_memory_requests(
--	struct hw_sequencer *hws,
--	struct hw_path_mode *path_mode);
--
--void dal_hw_sequencer_update_info_packets(
--	struct hw_sequencer *hws,
--	struct hw_path_mode *path_mode);
--
- /* Static validation for a SINGLE path mode.
-  * Already "active" paths (if any) are NOT taken into account. */
- enum hwss_result dal_hw_sequencer_validate_display_path_mode(
-@@ -213,34 +169,10 @@ enum hwss_result dal_hw_sequencer_set_backlight_adjustment(
- 	struct display_path *display_path,
- 	struct hw_adjustment_value *adjustment);
- 
--void dal_hw_sequencer_disable_memory_requests(
--	struct hw_sequencer *hws,
--	const struct hw_path_mode *path_mode);
--
- enum hwss_result dal_hw_sequencer_enable_link(
- 	struct hw_sequencer *hws,
- 	const struct enable_link_param *in);
- 
--void dal_hw_sequencer_disable_link(
--	struct hw_sequencer *hws,
--	const struct enable_link_param *in);
--
--void dal_hw_sequencer_enable_stream(
--	struct hw_sequencer *hws,
--	const struct enable_stream_param *in);
--
--void dal_hw_sequencer_disable_stream(
--	struct hw_sequencer *hws,
--	const struct enable_stream_param *in);
--
--void dal_hw_sequencer_blank_stream(
--	struct hw_sequencer *hws,
--	const struct blank_stream_param *in);
--
--void dal_hw_sequencer_unblank_stream(
--	struct hw_sequencer *hws,
--	const struct blank_stream_param *in);
--
- enum hwss_result dal_hw_sequencer_set_clocks_and_clock_state(
- 		struct hw_sequencer *hws,
- 		struct hw_global_objects *g_obj,
-@@ -259,27 +191,6 @@ enum signal_type dal_hw_sequencer_detect_load(
- 	struct hw_sequencer *hws,
- 	struct display_path *display_path);
- 
--bool dal_hw_sequencer_is_sink_present(
--	struct hw_sequencer *hws,
--	struct display_path *display_path);
--
--void dal_hw_sequencer_psr_setup(
--	struct hw_sequencer *hws,
--	const struct hw_path_mode *path_mode,
--	const struct psr_caps *psr_caps);
--
--void dal_hw_sequencer_psr_enable(
--	struct hw_sequencer *hws,
--	struct display_path *display_path);
--
--void dal_hw_sequencer_psr_disable(
--	struct hw_sequencer *hws,
--	struct display_path *display_path);
--
--void dal_hw_sequencer_program_drr(
--		struct hw_sequencer *hws,
--		const struct hw_path_mode *path_mode);
--
- enum hwss_result dal_hw_sequencer_set_safe_displaymark(
- 		struct hw_sequencer *hws,
- 		struct hw_path_mode_set *path_set);
-@@ -288,8 +199,6 @@ enum hwss_result dal_hw_sequencer_set_displaymark(
- 		struct hw_sequencer *hws,
- 		struct hw_path_mode_set *path_set);
- 
--void dal_hw_sequencer_destroy(struct hw_sequencer **hws);
--
- struct hw_sequencer *dal_hw_sequencer_create(
- 		struct hws_init_data *hws_init_data);
- 
-@@ -298,65 +207,21 @@ enum hwss_result dal_hw_sequencer_set_overscan_adj(
- 	struct hw_path_mode_set *set,
- 	struct hw_underscan_adjustment_data *hw_underscan);
- 
--bool dal_hw_sequencer_enable_line_buffer_power_gating(
--	struct line_buffer *lb,
--	enum controller_id id,
--	enum pixel_type pixel_type,
--	uint32_t src_pixel_width,
--	uint32_t dst_pixel_width,
--	struct scaling_taps *taps,
--	enum lb_pixel_depth lb_depth,
--	uint32_t src_height,
--	uint32_t dst_height,
--	bool interlaced);
--
--void dal_hw_sequencer_build_scaler_parameter(
--	const struct hw_path_mode *path_mode,
--	const struct scaling_taps *taps,
--	bool build_timing_required,
--	struct scaler_data *scaler_data);
--
--void dal_hw_sequencer_update_info_frame(
--	const struct hw_path_mode *hw_path_mode);
--
- enum hwss_result dal_hw_sequencer_set_bit_depth_reduction_adj(
- 	struct hw_sequencer *hws,
- 	struct display_path *disp_path,
- 	union hw_adjustment_bit_depth_reduction *bit_depth);
- 
--bool dal_hw_sequencer_is_support_custom_gamut_adj(
--	struct hw_sequencer *hws,
--	struct display_path *disp_path,
--	enum hw_surface_type surface_type);
--
- enum hwss_result dal_hw_sequencer_get_hw_color_adj_range(
- 	struct hw_sequencer *hws,
- 	struct display_path *disp_path,
- 	struct hw_color_control_range *hw_color_range);
- 
--bool dal_hw_sequencer_is_support_custom_gamma_coefficients(
--	struct hw_sequencer *hws,
--	struct display_path *disp_path,
--	enum hw_surface_type surface_type);
--
- enum hwss_result dal_hw_sequencer_build_csc_adjust(
- 	struct hw_sequencer *hws,
- 	struct hw_adjustment_color_control *color_control,
- 	struct grph_csc_adjustment *adjust);
- 
--void dal_hw_sequencer_build_gamma_ramp_adj_params(
--		const struct hw_adjustment_gamma_ramp *adjusment,
--		struct gamma_parameters *gamma_param,
--		struct gamma_ramp *ramp);
--
--void translate_from_hw_to_controller_regamma(
--		const struct hw_regamma_lut *hw_regamma,
--		struct regamma_lut *regamma);
--
--void dal_hw_sequencer_enable_wireless_idle_detection(
--		struct hw_sequencer *hws,
--		bool enable);
--
- /* Cursor interface */
- enum hwss_result dal_hw_sequencer_set_cursor_position(
- 		struct hw_sequencer *hws,
-@@ -374,15 +239,4 @@ enum hwss_result dal_hw_sequencer_set_plane_config(
- 	struct hw_path_mode_set *path_set,
- 	uint32_t display_index);
- 
--bool dal_hw_sequencer_update_plane_address(
--	struct hw_sequencer *hws,
--	struct display_path *dp,
--	uint32_t num_planes,
--	struct plane_addr_flip_info *info);
--
--void dal_hw_sequencer_prepare_to_release_planes(
--	struct hw_sequencer *hws,
--	struct hw_path_mode_set *path_set,
--	uint32_t display_index);
--
- #endif /* __DAL_HW_SEQUENCER_INTERFACE_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_interface.h b/drivers/gpu/drm/amd/dal/include/link_service_interface.h
-index 2ac9311..29233ae 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_interface.h
-@@ -40,141 +40,9 @@ enum ddc_result;
- struct link_service *dal_link_service_create(
- 	struct link_service_init_data *init_data);
- 
--void dal_link_service_destroy(
--	struct link_service **ls);
--
- enum link_service_type dal_ls_get_link_service_type(
- 	struct link_service *link_service);
- 
--bool dal_ls_validate_mode_timing(
--	struct link_service *ls,
--	uint32_t display_index,
--	const struct hw_crtc_timing *timing,
--	struct link_validation_flags flags);
--
--bool dal_ls_get_mst_sink_info(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct mst_sink_info *sink_info);
--
--bool dal_ls_get_gtc_sync_status(
--	struct link_service *ls);
--
--bool dal_ls_enable_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--bool dal_ls_disable_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *poath_mode);
--
--bool dal_ls_optimized_enable_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct display_path *display_path);
--
--void dal_ls_update_stream_features(
--	struct link_service *ls,
--	const struct hw_path_mode *path_mode);
--
--bool dal_ls_blank_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--bool dal_ls_unblank_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--bool dal_ls_pre_mode_change(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--bool dal_ls_post_mode_change(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--bool dal_ls_power_on_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--bool dal_ls_power_off_stream(
--	struct link_service *ls,
--	uint32_t display_index,
--	struct hw_path_mode *path_mode);
--
--void dal_ls_retrain_link(
--	struct link_service *ls,
--	struct hw_path_mode_set *path_set);
--
--bool dal_ls_get_current_link_setting(
--	struct link_service *ls,
--	struct link_settings *link_settings);
--
--void dal_ls_connect_link(
--	struct link_service *ls,
--	const struct display_path *display_path,
--	bool initial_detection);
--
--void dal_ls_disconnect_link(
--	struct link_service *ls);
--
--bool dal_ls_is_mst_network_present(
--	struct link_service *ls);
--
--void dal_ls_invalidate_down_stream_devices(
--	struct link_service *ls);
--
--bool dal_ls_are_mst_displays_cofunctional(
--	struct link_service *ls,
--	const uint32_t *array_display_index,
--	uint32_t len);
--
--bool dal_ls_is_sink_present_at_display_index(
--	struct link_service *ls,
--	uint32_t display_index);
--
--struct ddc_service *dal_ls_obtain_mst_ddc_service(
--	struct link_service *ls,
--	uint32_t display_index);
--
--void dal_ls_release_mst_ddc_service(
--	struct link_service *ls,
--	struct ddc_service *ddc_service);
--
--void dal_ls_release_hw(
--	struct link_service *ls);
--
--bool dal_ls_associate_link(
--	struct link_service *ls,
--	uint32_t display_index,
--	uint32_t link_index,
--	bool is_internal_link);
--
--bool dal_dpsst_ls_set_overridden_trained_link_settings(
--	struct link_service *ls,
--	const struct link_settings *link_settings);
--
--void dal_dpsst_ls_set_link_training_preference(
--	struct link_service *ls,
--	const struct link_training_preference *ltp);
--
--struct link_training_preference
--	dal_dpsst_ls_get_link_training_preference(
--	struct link_service *ls);
--
--bool dal_ls_should_send_notification(
--	struct link_service *ls);
--
--uint32_t dal_ls_get_notification_display_index(
--	struct link_service *ls);
--
- enum ddc_result dal_dpsst_ls_read_dpcd_data(
- 	struct link_service *ls,
- 	uint32_t address,
-@@ -187,16 +55,4 @@ enum ddc_result dal_dpsst_ls_write_dpcd_data(
- 	const uint8_t *data,
- 	uint32_t size);
- 
--bool dal_ls_is_link_psr_supported(struct link_service *ls);
--
--bool dal_ls_is_stream_drr_supported(struct link_service *ls);
--
--void dal_ls_set_link_psr_capabilities(
--		struct link_service *ls,
--		struct psr_caps *psr_caps);
--
--void dal_ls_get_link_psr_capabilities(
--		struct link_service *ls,
--		struct psr_caps *psr_caps);
--
- #endif /* __DAL_LINK_SERVICE_INTERFACE_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch b/common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch
deleted file mode 100644
index 0c07856f..00000000
--- a/common/recipes-kernel/linux/files/1006-drm-amd-dal-remove-dead-code.patch
+++ /dev/null
@@ -1,1233 +0,0 @@
-From bbda780aa778a436e8310692181f620f52a60ca2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>
-Date: Thu, 24 Mar 2016 14:17:14 +0100
-Subject: [PATCH 1006/1110] drm/amd/dal: remove dead code.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-More seriously ...
-
-Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  24 --
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h   |  28 ---
- drivers/gpu/drm/amd/dal/dc/dm_services_types.h     |   8 -
- drivers/gpu/drm/amd/dal/dc/inc/compressor.h        |  48 ----
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  10 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h            |   5 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h   |   3 -
- drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h            |   7 -
- drivers/gpu/drm/amd/dal/include/dal_types.h        | 126 ----------
- drivers/gpu/drm/amd/dal/include/dcs_types.h        | 269 ---------------------
- .../drm/amd/dal/include/display_clock_interface.h  |  23 --
- drivers/gpu/drm/amd/dal/include/dmcu_types.h       |  45 ----
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h        |   9 -
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    |  63 -----
- drivers/gpu/drm/amd/dal/include/grph_object_defs.h |  65 -----
- .../drm/amd/dal/include/hw_sequencer_interface.h   |  15 --
- .../gpu/drm/amd/dal/include/hw_sequencer_types.h   |  37 ---
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  |  40 ---
- .../gpu/drm/amd/dal/include/video_gamma_types.h    |  16 --
- 19 files changed, 841 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index a375b00..8bc0413 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -187,15 +187,6 @@ enum view_3d_format {
- 	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
- };
- 
--struct view_stereo_3d_support {
--	enum view_3d_format format;
--	struct {
--		uint32_t CLONE_MODE :1;
--		uint32_t SCALING :1;
--		uint32_t SINGLE_FRAME_SW_PACKED :1;
--	} features;
--};
--
- enum plane_stereo_format {
- 	PLANE_STEREO_FORMAT_NONE = 0,
- 	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
-@@ -280,11 +271,6 @@ struct view {
- 	uint32_t height;
- };
- 
--struct dc_resolution {
--	uint32_t width;
--	uint32_t height;
--};
--
- struct dc_mode_flags {
- 	/* note: part of refresh rate flag*/
- 	uint32_t INTERLACE :1;
-@@ -441,16 +427,6 @@ enum scaling_transformation {
- 		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
- };
- 
--struct view_position {
--	uint32_t x;
--	uint32_t y;
--};
--
--struct render_mode {
--	struct view view;
--	enum pixel_format pixel_format;
--};
--
- /* audio*/
- 
- union audio_sample_rates {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-index e61a494..f68d51c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_types.h
-@@ -26,33 +26,5 @@
- #define __DCE110_TYPES_H_
- 
- #define GAMMA_SEGMENTS_NUM 16
--struct end_point {
--	uint32_t x_value;
--	uint32_t y_value;
--	uint32_t slope;
--};
--
--struct pwl_segment {
--	uint32_t r_value;
--	uint32_t g_value;
--	uint32_t b_value;
--	uint32_t r_delta;
--	uint32_t g_delta;
--	uint32_t b_delta;
--};
--
--struct dce110_opp_regamma_params {
--	struct {
--		uint8_t num_segments[GAMMA_SEGMENTS_NUM];
--		uint16_t offsets[GAMMA_SEGMENTS_NUM];
--		struct end_point first;
--		struct end_point last;
--	} region_config;
--
--	struct {
--		struct pwl_segment *segments;
--		int num_pwl_segments;
--	} pwl_config;
--};
- 
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_DCE110_DCE110_TYPES_H_ */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-index 982e968..62ff098 100644
---- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
-@@ -260,12 +260,4 @@ struct dm_pp_display_configuration {
- 	uint32_t line_time_in_us;
- };
- 
--struct dm_pp_static_clock_info {
--	uint32_t max_sclk_khz;
--	uint32_t max_mclk_khz;
--
--	 /* max possible display block clocks state */
--	enum dm_pp_clocks_state max_clocks_state;
--};
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-index 4992ffd..a2e44b5 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
-@@ -49,59 +49,11 @@ struct compr_addr_and_pitch_params {
- 	uint32_t source_view_height;
- };
- 
--struct fbc_lpt_config {
--	uint32_t mem_channels_num;
--	uint32_t banks_num;
--	uint32_t chan_interleave_size;
--	uint32_t row_size;
--};
--
--struct fbc_input_info {
--	bool dynamic_fbc_buffer_alloc;
--	uint32_t source_view_width;
--	uint32_t source_view_height;
--	uint32_t active_targets_num;
--	struct fbc_lpt_config lpt_config;
--};
--
--struct fbc_requested_compressed_size {
--	uint32_t preferred_size;
--	uint32_t preferred_size_alignment;
--	uint32_t min_size;
--	uint32_t min_size_alignment;
--	union {
--		struct {
--			/*Above preferred_size must be allocated in FB pool */
--			uint32_t PREFERRED_MUST_BE_FRAME_BUFFER_POOL:1;
--			/*Above min_size must be allocated in FB pool */
--			uint32_t MIN_MUST_BE_FRAME_BUFFER_POOL:1;
--		} flags;
--		uint32_t bits;
--	};
--};
--
--struct fbc_compressed_surface_info {
--	union fbc_physical_address compressed_surface_address;
--	uint32_t allocated_size;
--	union {
--		struct {
--			uint32_t FB_POOL:1; /*Allocated in FB Pool */
--			uint32_t DYNAMIC_ALLOC:1; /*Dynamic allocation */
--		} allocation_flags;
--		uint32_t bits;
--	};
--};
--
- enum fbc_hw_max_resolution_supported {
- 	FBC_MAX_X = 3840,
- 	FBC_MAX_Y = 2400
- };
- 
--struct fbc_max_resolution_supported {
--	uint32_t source_view_width;
--	uint32_t source_view_height;
--};
--
- struct compressor {
- 	struct dc_context *ctx;
- 	uint32_t attached_inst;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 14b62ab..9093e97 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -128,16 +128,6 @@ struct link_init_data {
- 	struct adapter_service *adapter_srv;
- };
- 
--struct link_caps {
--	/* support for Spread Spectrum(SS) */
--	bool ss_supported;
--	/* DP link settings (laneCount, linkRate, Spread) */
--	uint32_t lane_count;
--	uint32_t rate;
--	uint32_t spread;
--	enum dpcd_revision dpcd_revision;
--};
--
- struct dpcd_caps {
- 	union dpcd_rev dpcd_rev;
- 	union max_lane_count max_ln_count;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-index f419331..9063308 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/ipp.h
-@@ -67,11 +67,6 @@ enum ovl_color_space {
- 	OVL_COLOR_SPACE_YUV709
- };
- 
--struct dcp_video_matrix {
--	enum ovl_color_space color_space;
--	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
--};
--
- enum expansion_mode {
- 	EXPANSION_MODE_ZERO,
- 	EXPANSION_MODE_DYNAMIC
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-index 115ef54..94dd422 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
-@@ -66,9 +66,6 @@ struct encoder_feature_support {
- 	unsigned int max_hdmi_pixel_clock;
- };
- 
--struct link_enc_status {
--	int dummy; /*TODO*/
--};
- struct link_encoder {
- 	struct link_encoder_funcs *funcs;
- 	struct adapter_service *adapter_service;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-index 1c6bab3..3410357 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/opp.h
-@@ -188,13 +188,6 @@ struct gamma_coefficients {
- 	struct fixed31_32 user_brightness;
- };
- 
--struct csc_adjustments {
--	struct fixed31_32 contrast;
--	struct fixed31_32 saturation;
--	struct fixed31_32 brightness;
--	struct fixed31_32 hue;
--};
--
- struct pwl_float_data {
- 	struct fixed31_32 r;
- 	struct fixed31_32 g;
-diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
-index 21ee669..0e4c9a2 100644
---- a/drivers/gpu/drm/amd/dal/include/dal_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
-@@ -49,130 +49,4 @@ enum dce_version {
- 	DCE_VERSION_MAX,
- };
- 
--/* Wireless display structs */
--
--union dal_remote_display_cea_mode_bitmap {
--	struct {
--		uint32_t CEA_640X480_60P:1;/*0*/
--		uint32_t CEA_720X480_60P:1;/*1*/
--		uint32_t CEA_720X480_60I:1;/*2*/
--		uint32_t CEA_720X576_50P:1;/*3*/
--		uint32_t CEA_720X576_50I:1;/*4*/
--		uint32_t CEA_1280X720_30P:1;/*5*/
--		uint32_t CEA_1280X720_60P:1;/*6*/
--		uint32_t CEA_1920X1080_30P:1;/*7*/
--		uint32_t CEA_1920X1080_60P:1;/*8*/
--		uint32_t CEA_1920X1080_60I:1;/*9*/
--		uint32_t CEA_1280X720_25P:1;/*10*/
--		uint32_t CEA_1280X728_50P:1;/*11*/
--		uint32_t CEA_1920X1080_25P:1;/*12*/
--		uint32_t CEA_1920X1080_50P:1;/*13*/
--		uint32_t CEA_1920X1080_50I:1;/*14*/
--		uint32_t CEA_1280X1024_24P:1;/*15*/
--		uint32_t CEA_1920X1080_24P:1;/*16*/
--		uint32_t RESERVED:15;/*[17-31]*/
--	} flags;
--	uint32_t raw;
--};
--
--union dal_remote_display_vesa_mode_bitmap {
--	struct {
--		uint32_t VESA_800X600_30P:1;/*0*/
--		uint32_t VESA_800X600_60P:1;/*1*/
--		uint32_t VESA_1024X768_30P:1;/*2*/
--		uint32_t VESA_1024X768_60P:1;/*3*/
--		uint32_t VESA_1152X864_30P:1;/*4*/
--		uint32_t VESA_1152X864_60P:1;/*5*/
--		uint32_t VESA_1280X768_30P:1;/*6*/
--		uint32_t VESA_1280X768_60P:1;/*7*/
--		uint32_t VESA_1280X800_30P:1;/*8*/
--		uint32_t VESA_1280X800_60P:1;/*9*/
--		uint32_t VESA_1360X768_30P:1;/*10*/
--		uint32_t VESA_1360X768_60P:1;/*11*/
--		uint32_t VESA_1366X768_30P:1;/*12*/
--		uint32_t VESA_1366X768_60P:1;/*13*/
--		uint32_t VESA_1280X1024_30P:1;/*14*/
--		uint32_t VESA_1280X1024_60P:1;/*15*/
--		uint32_t VESA_1400X1050_30P:1;/*16*/
--		uint32_t VESA_1400X1050_60P:1;/*17*/
--		uint32_t VESA_1440X900_30P:1;/*18*/
--		uint32_t VESA_1440X900_60P:1;/*19*/
--		uint32_t VESA_1600X900_30P:1;/*20*/
--		uint32_t VESA_1600X900_60P:1;/*21*/
--		uint32_t VESA_1600X1200_30P:1;/*22*/
--		uint32_t VESA_1600X1200_60P:1;/*23*/
--		uint32_t VESA_1680X1024_30P:1;/*24*/
--		uint32_t VESA_1680X1024_60P:1;/*25*/
--		uint32_t VESA_1680X1050_30P:1;/*26*/
--		uint32_t VESA_1680X1050_60P:1;/*27*/
--		uint32_t VESA_1920X1200_30P:1;/*28*/
--		uint32_t VESA_1920X1200_60P:1;/*29*/
--		uint32_t RESERVED:2;/*[30-31]*/
--	} flags;
--	uint32_t raw;
--};
--
--union dal_remote_display_hh_mode_bitmap {
--	struct {
--		uint32_t HH_800X480_30P:1;/*0*/
--		uint32_t HH_800X480_60P:1;/*1*/
--		uint32_t HH_854X480_30P:1;/*2*/
--		uint32_t HH_854X480_60P:1;/*3*/
--		uint32_t HH_864X480_30P:1;/*4*/
--		uint32_t HH_864X480_60P:1;/*5*/
--		uint32_t HH_640X360_30P:1;/*6*/
--		uint32_t HH_640X360_60P:1;/*7*/
--		uint32_t HH_960X540_30P:1;/*8*/
--		uint32_t HH_960X540_60P:1;/*9*/
--		uint32_t HH_848X480_30P:1;/*10*/
--		uint32_t HH_848X480_60P:1;/*11*/
--		uint32_t RESERVED:20;/*[12-31]*/
--	} flags;
--	uint32_t raw;
--};
--
--union dal_remote_display_stereo_3d_mode_bitmap {
--	struct {
--		uint32_t STEREO_1920X1080_24P_TOP_AND_BOTTOM:1;/*0*/
--		uint32_t STEREO_1280X720_60P_TOP_AND_BOTTOM:1;/*1*/
--		uint32_t STEREO_1280X720_50P_TOP_AND_BOTTOM:1;/*2*/
--		uint32_t STEREO_1920X1080_24X2P_FRAME_ALTERNATE:1;/*3*/
--		uint32_t STEREO_1280X720_60X2P_FRAME_ALTERNATE:1;/*4*/
--		uint32_t STEREO_1280X720_30X2P_FRAME_ALTERNATE:1;/*5*/
--		uint32_t STEREO_1280X720_50X2P_FRAME_ALTERNATE:1;/*6*/
--		uint32_t STEREO_1280X720_25X2P_FRAME_ALTERNATE:1;/*7*/
--		uint32_t STEREO_1920X1080_24P_FRAME_PACKING:1;/* 8*/
--		uint32_t STEREO_1280X720_60P_FRAME_PACKING:1;/* 9*/
--		uint32_t STEREO_1280X720_30P_FRAME_PACKING:1;/*10*/
--		uint32_t STEREO_1280X720_50P_FRAME_PACKING:1;/*11*/
--		uint32_t STEREO_1280X720_25P_FRAME_PACKING:1;/*12*/
--		uint32_t RESERVED:19; /*[13-31]*/
--	} flags;
--	uint32_t raw;
--};
--
--union dal_remote_display_audio_bitmap {
--	struct {
--		uint32_t LPCM_44100HZ_16BITS_2_CHANNELS:1;/*0*/
--		uint32_t LPCM_48000HZ_16BITS_2_CHANNELS:1;/*1*/
--		uint32_t AAC_48000HZ_16BITS_2_CHANNELS:1;/*2*/
--		uint32_t AAC_48000HZ_16BITS_4_CHANNELS:1;/*3*/
--		uint32_t AAC_48000HZ_16BITS_6_CHANNELS:1;/*4*/
--		uint32_t AAC_48000HZ_16BITS_8_CHANNELS:1;/*5*/
--		uint32_t AC3_48000HZ_16BITS_2_CHANNELS:1;/*6*/
--		uint32_t AC3_48000HZ_16BITS_4_CHANNELS:1;/*7*/
--		uint32_t AC3_48000HZ_16BITS_6_CHANNELS:1;/*8*/
--		uint32_t RESERVED:23;/*[9-31]*/
--	} flags;
--	uint32_t raw;
--};
--
--struct dal_remote_display_receiver_capability {
--	union dal_remote_display_cea_mode_bitmap cea_mode;
--	union dal_remote_display_vesa_mode_bitmap vesa_mode;
--	union dal_remote_display_hh_mode_bitmap hh_mode;
--	union dal_remote_display_stereo_3d_mode_bitmap stereo_3d_mode;
--	union dal_remote_display_audio_bitmap audio;
--};
--
- #endif /* __DAL_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dcs_types.h b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-index 8c65057..bccfd99 100644
---- a/drivers/gpu/drm/amd/dal/include/dcs_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-@@ -48,35 +48,6 @@ struct drr_config {
- 	} support_method;
- };
- 
--struct timing_limits {
--	uint32_t min_pixel_clock_in_khz;
--	uint32_t max_pixel_clock_in_khz;
--};
--
--struct vendor_product_id_info {
--	uint32_t manufacturer_id;
--	uint32_t product_id;
--	uint32_t serial_id;
--	uint32_t manufacture_week;
--	uint32_t manufacture_year;
--};
--
--struct display_range_limits {
--	uint32_t min_v_rate_hz;
--	uint32_t max_v_rate_hz;
--	uint32_t min_h_rate_khz;
--	uint32_t max_h_rateIn_khz;
--	uint32_t max_pix_clk_khz;
--	bool use_override;
--};
--
--struct monitor_user_select_limits {
--	bool use_ati_override;
--	uint32_t max_h_res;
--	uint32_t max_v_res;
--	uint32_t max_refresh_rate;
--};
--
- enum edid_screen_aspect_ratio {
- 	EDID_SCREEN_AR_UNKNOWN = 0,
- 	EDID_SCREEN_AR_PROJECTOR,
-@@ -90,17 +61,6 @@ enum edid_screen_aspect_ratio {
- 	EDID_SCREEN_AR_4X5
- };
- 
--struct edid_screen_info {
--	enum edid_screen_aspect_ratio aspect_ratio;
--	uint32_t width;
--	uint32_t height;
--};
--
--struct display_characteristics {
--	uint8_t gamma;
--	uint8_t color_characteristics[NUM_OF_BYTE_EDID_COLOR_CHARACTERISTICS];
--};
--
- union cv_smart_dongle_modes {
- 	uint8_t all;
- 	struct cv_smart_dongle_switches {
-@@ -113,18 +73,6 @@ union cv_smart_dongle_modes {
- 	} switches;
- };
- 
--struct cea_audio_mode {
--	uint8_t format_code; /* ucData[0] [6:3]*/
--	uint8_t channel_count; /* ucData[0] [2:0]*/
--	uint8_t sample_rate; /* ucData[1]*/
--	union {
--		uint8_t sample_size; /* for LPCM*/
--		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
--		uint8_t max_bit_rate;
--		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
--	};
--};
--
- union cea_speaker_allocation_data_block {
- 	struct {
- 		uint32_t FL_FR:1;
-@@ -138,23 +86,6 @@ union cea_speaker_allocation_data_block {
- 	uint32_t raw;
- };
- 
--struct cea_colorimetry_data_block {
--	struct {
--		uint32_t XV_YCC601:1;
--		uint32_t XV_YCC709:1;
--		uint32_t S_YCC601:1;
--		uint32_t ADOBE_YCC601:1;
--		uint32_t ADOBE_RGB:1;
--
--	} flag;
--	struct {
--		uint32_t MD0:1;
--		uint32_t MD1:1;
--		uint32_t MD2:1;
--		uint32_t MD3:1;
--	} metadata_flag;
--};
--
- union cea_video_capability_data_block {
- 	struct {
- 		uint8_t S_CE0:1;
-@@ -184,121 +115,6 @@ enum cea_hdmi_vic {
- 	CEA_HDMI_VIC_4KX2K_24_SMPTE
- };
- 
--struct cea_hdmi_vsdb_extended_caps {
--	uint32_t reserved;
--	uint32_t image_size;
--	enum stereo_3d_multi_presence stereo_3d_multi_present;
--	bool stereo_3d_present;
--	uint32_t hdmi_3d_len;
--	uint32_t hdmi_vic_len;
--};
--
--struct cea_vendor_specific_data_block {
--
--	uint32_t ieee_id;
--
--	struct commonent_phy {
--		uint32_t PHY_ADDR_A:4;
--		uint32_t PHY_ADDR_B:4;
--		uint32_t PHY_ADDR_C:4;
--		uint32_t PHY_ADDR_D:4;
--	} commonent_phy_addr;
--
--	struct byte6 {
--		uint32_t SUPPORTS_AI:1;
--		uint32_t DC_48BIT:1;
--		uint32_t DC_36BIT:1;
--		uint32_t DC_30BIT:1;
--		uint32_t DC_Y444:1;
--		uint32_t DVI_DUAL:1;
--		uint32_t RESERVED:2;
--	} byte6;/* link capabilities*/
--	bool byte6_valid;
--
--	uint32_t max_tmds_clk_mhz;
--
--	struct byte8 {
--		uint32_t LATENCY_FIELDS_PRESENT:1;
--		uint32_t ILATENCY_FIELDS_PRESENT:1;
--		uint32_t HDMI_VIDEO_PRESENT:1;
--		uint32_t RESERVED:1;
--		uint32_t CNC3_GAME:1;
--		uint32_t CNC2_CINEMA:1;
--		uint32_t CNC1_PHOTO:1;
--		uint32_t CNC0_GRAPHICS:1;
--	} byte8;
--	/*bit 6-7: latency flags to indicate valid latency fields*/
--	/*bit 5: support of additional video format capabilities*/
--	/* bit 0-3: flags indicating which content type is supported*/
--	uint32_t video_latency;
--	uint32_t audio_latency;
--	uint32_t i_video_latency;
--	uint32_t i_audio_latency;
--
--	struct cea_hdmi_vsdb_extended_caps hdmi_vsdb_extended_caps;
--
--	enum stereo_3d_multi_presence stereo_3d_multi_present;
--
--	struct {
--		bool FRAME_PACKING:1;
--		bool SIDE_BY_SIDE_HALF:1;
--		bool TOP_AND_BOTTOM:1;
--	} stereo_3d_all_support;
--	uint16_t stereo_3d_mask;
--
--	enum cea_hdmi_vic hdmi_vic[MAX_NUMBER_OF_HDMI_VSDB_VICS];
--	struct stereo_3d_extended_support {
--		struct {
--			bool FRAME_PACKING:1;
--			bool SIDE_BY_SIDE_HALF:1;
--			bool TOP_AND_BOTTOM:1;
--		} format;
--		uint32_t vic_index;
--		uint32_t value;
--		uint32_t size;
--	} stereo_3d_extended_support[MAX_NUMBER_OF_HDMI_VSDB_3D_EXTENDED_SUPPORT];
--};
--
--struct cea861_support {
--
--	uint32_t revision;
--	union {
--		struct {
--			uint32_t NATIVE_COUNT:4;
--			uint32_t BASE_AUDIO:1;
--			uint32_t YCRCB444:1;
--			uint32_t YCRCB422:1;
--			uint32_t UNDER_SCAN:1;
--		} features;
--		uint8_t raw_features;
--	};
--};
--
--struct dcs_customized_mode {
--	struct {
--		uint32_t READ_ONLY:1;
--		uint32_t ADD_BY_DRIVER:1;
--		uint32_t INTERLACED:1;
--		uint32_t BASE_MODE:1;
--	} flags;
--	struct dc_mode_info base_mode_info;
--	struct dc_mode_info customized_mode_info;
--};
--
--struct dcs_override_mode_timing {
--	/* possible timing standards, bit vector of TimingStandard*/
--	uint32_t possible_timing_standards;
--	/* indicate driver default timing is used , no override*/
--	bool use_driver_default_timing;
--	struct dc_mode_timing mode_timing;
--};
--
--struct dcs_override_mode_timing_list {
--	uint32_t max_num_overrides;
--	uint32_t num_overrides;
--	struct dcs_override_mode_timing mode_timings[1];
--};
--
- /* "interface type" is different from Signal Type because
-  * an "interface type" can be driven by more than one Signal Type.
-  * For example, INTERFACE_TYPE_DVI can be driven by
-@@ -397,10 +213,6 @@ enum pixel_encoding_mask {
- 	PIXEL_ENCODING_MASK_RGB = 0x04,
- };
- 
--struct display_pixel_encoding_support {
--	uint32_t mask;
--};
--
- enum color_depth_index {
- 	COLOR_DEPTH_INDEX_UNKNOWN,
- 	COLOR_DEPTH_INDEX_666 = 0x01,
-@@ -412,17 +224,6 @@ enum color_depth_index {
- 	COLOR_DEPTH_INDEX_LAST = 0x40,
- };
- 
--struct display_color_depth_support {
--	uint32_t mask;
--	bool deep_color_native_res_only;
--};
--
--struct display_color_and_pixel_support {
--	struct display_color_depth_support color_depth_support;
--	struct display_pixel_encoding_support pixel_encoding_support;
--	bool deep_color_y444_support;
--};
--
- enum dcs_packed_pixel_format {
- 	DCS_PACKED_PIXEL_FORMAT_NOT_PACKED = 0,
- 	DCS_PACKED_PIXEL_FORMAT_SPLIT_G70_B54_R70_B10 = 1,
-@@ -623,14 +424,6 @@ enum monitor_patch_type {
- 	MONITOR_PATCH_TYPE_SINGLE_MODE_PACKED_PIXEL
- };
- 
--/* Single entry in the monitor table */
--struct monitor_patch_info {
--	enum monitor_manufacturer_id manufacturer_id;
--	enum monitor_product_id product_id;
--	enum monitor_patch_type type;
--	uint32_t param;
--};
--
- union dcs_monitor_patch_flags {
-         struct {
-                 bool ERROR_CHECKSUM:1;
-@@ -676,67 +469,5 @@ union dcs_monitor_patch_flags {
-         uint64_t raw;
- };
- 
--struct dcs_edid_supported_max_bw {
--	uint32_t pix_clock_khz;
--	uint32_t bits_per_pixel;
--};
--
--struct dcs_stereo_3d_features {
--	struct {
--/* 3D Format supported by monitor (implies supported by driver)*/
--		uint32_t SUPPORTED:1;
--/* 3D Format supported on all timings
--(no need to check every timing for 3D support)*/
--		uint32_t ALL_TIMINGS:1;
--/* 3D Format supported in clone mode*/
--		uint32_t CLONE_MODE:1;
--/* Scaling allowed when driving 3D Format*/
--		uint32_t SCALING:1;
--/* Left and right images packed by SW within single frame*/
--		uint32_t SINGLE_FRAME_SW_PACKED:1;
--	} flags;
--};
--
--struct dcs_container_id {
--	/*128bit GUID in binary form*/
--	uint8_t guid[16];
--	/* 8 byte port ID -> ELD.PortID*/
--	uint32_t port_id[2];
--	/* 2 byte manufacturer name -> ELD.ManufacturerName*/
--	uint16_t manufacturer_name;
--	/* 2 byte product code -> ELD.ProductCode*/
--	uint16_t product_code;
--};
--
--struct dcs_display_tile {
--/*unique Id of Tiled Display. 0 - means display is not part in Tiled Display*/
--	uint64_t id;
--	uint32_t rows;/* size of Tiled Display in tiles*/
--	uint32_t cols;/* size of Tiled Display in tiles*/
--	uint32_t width;/* size of current Tile in pixels*/
--	uint32_t height;/* size of current Tile in pixels*/
--	uint32_t row;/* location of current Tile*/
--	uint32_t col;/* location of current Tile*/
--	struct {
--		/*in pixels*/
--		uint32_t left;
--		uint32_t right;
--		uint32_t top;
--		uint32_t bottom;
--	} bezel;/* bezel information of current tile*/
--
--	struct {
--		uint32_t SEPARATE_ENCLOSURE:1;
--		uint32_t BEZEL_INFO_PRESENT:1;
--		uint32_t CAN_SCALE:1;
--	} flags;
--
--	struct {
--		uint32_t manufacturer_id;
--		uint32_t product_id;
--		uint32_t serial_id;
--	} topology_id;
--};
--
- #endif /* __DAL_DCS_TYPES_H__ */
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-index 317ce3b..55648ea 100644
---- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
-@@ -51,22 +51,6 @@ struct dc_scaling_params {
- 	uint32_t v_taps;
- };
- 
--/*Display Request Mode (1 and 2 valid when scaler is OFF)*/
--enum display_request_mode {
--	REQUEST_ONLY_AT_EVERY_READ_POINTER_INCREMENT = 0,
--	REQUEST_WAITING_FOR_THE_FIRST_READ_POINTER_ONLY,
--	REQUEST_WITHOUT_WAITING_FOR_READ_POINTER
--};
--
--/* FBC minimum CompressionRatio*/
--enum fbc_compression_ratio {
--	FBC_COMPRESSION_NOT_USED = 0,
--	FBC_MINIMUM_COMPRESSION_RATIO_1 = 1,
--	FBC_MINIMUM_COMPRESSION_RATIO_2 = 2,
--	FBC_MINIMUM_COMPRESSION_RATIO_4 = 4,
--	FBC_MINIMUM_COMPRESSION_RATIO_8 = 8
--};
--
- /* VScalerEfficiency */
- enum v_scaler_efficiency {
- 	V_SCALER_EFFICIENCY_LB36BPP = 0,
-@@ -92,13 +76,6 @@ struct min_clock_params {
- 	bool line_buffer_prefetch_enabled;
- };
- 
--/* Enumerations for Source selection of the Display clock */
--enum display_clock_source_select {
--	USE_PIXEL_CLOCK_PLL = 0,
--	USE_EXTERNAL_CLOCK,
--	USE_ENGINE_CLOCK
--};
--
- /* Result of Minimum System and Display clock calculations.
-  * Minimum System clock and Display clock, source and path to be used
-  * for Display clock*/
-diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_types.h b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-index 1f3107d..00f9fa4 100644
---- a/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-@@ -144,44 +144,6 @@ union dmcu_psr_level {
- 	uint32_t u32all;
- };
- 
--struct dmcu_config_data {
--	/* Command sent to DMCU. */
--	enum dmcu_action action;
--	/* PSR Level controls which HW blocks to power down during PSR active,
--	 * and also other sequence modifications. */
--	union dmcu_psr_level psr_level;
--	/* To indicate that first changed frame from active state should not
--	 * result in exit to inactive state, but instead perform an automatic
--	 * single frame RFB update. */
--	bool rfb_update_auto_en;
--	/* Number of consecutive static frames to detect before entering PSR
--	 * active state. */
--	uint32_t hyst_frames;
--	/* Partial frames before entering PSR active. Note this parameter is in
--	 * units of 100 lines. i.e. Wait a value of 5 means wait 500 additional
--	 * lines. */
--	uint32_t hyst_lines;
--	/* Number of repeated AUX retries before indicating failure to driver.
--	 * In a working case, first attempt to write/read AUX should pass. */
--	uint32_t aux_repeat;
--	/* Additional delay after remote frame capture before continuing to
--	 * power down. This is mainly for debug purposes to identify timing
--	 * issues. */
--	uint32_t frame_delay;
--	/* Controls how long the delay of a wait loop is. It should be tuned
--	 * to 1 us, and needs to be reconfigured every time DISPCLK changes. */
--	uint32_t wait_loop_num;
--};
--
--struct dmcu_output_data {
--	/* DMCU reply */
--	enum dmcu_output output;
--	/* The current PSR state. */
--	uint32_t psr_state;
--	/* The number of frames during PSR active state. */
--	uint32_t psr_count;
--};
--
- enum varibright_command {
- 	VARIBRIGHT_CMD_SET_VB_LEVEL = 0,
- 	VARIBRIGHT_CMD_USER_ENABLE,
-@@ -189,11 +151,4 @@ enum varibright_command {
- 	VARIBRIGHT_CMD_UNKNOWN
- };
- 
--struct varibright_control {
--	enum varibright_command command;
--	uint8_t level;
--	bool enable;
--	bool activate;
--};
--
- #endif /* __DAL_DMCU_TYPES_H__ */
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index 59677ed..e251cff 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -608,10 +608,6 @@ union audio_test_pattern_period {
- 	uint8_t raw;
- };
- 
--struct audio_test_pattern_type {
--	uint8_t value;
--};
--
- union dpcd_training_pattern {
- 	struct {
- 		uint8_t TRAINING_PATTERN_SET:4;
-@@ -854,11 +850,6 @@ struct dp_device_vendor_id {
- 	uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
- };
- 
--struct dp_sink_hw_fw_revision {
--	uint8_t ieee_hw_rev;
--	uint8_t ieee_fw_rev[2];
--};
--
- /*DPCD register of DP receiver capability field bits-*/
- union edp_configuration_cap {
- 	struct {
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index 7df01ff..11b1b99 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -39,53 +39,6 @@
-  * #####################################################
-  */
- 
--enum tv_standard {
--	TV_STANDARD_UNKNOWN = 0, /* direct HW (mmBIOS_SCRATCH_2) translation! */
--	TV_STANDARD_NTSC,
--	TV_STANDARD_NTSCJ,
--	TV_STANDARD_PAL,
--	TV_STANDARD_PALM,
--	TV_STANDARD_PALCN,
--	TV_STANDARD_PALN,
--	TV_STANDARD_PAL60,
--	TV_STANDARD_SECAM
--};
--
--enum cv_standard {
--	CV_STANDARD_UNKNOWN = 0x0000,
--	CV_STANDARD_HD_MASK = 0x0800,		/* Flag mask HDTV output */
--	CV_STANDARD_SD_NTSC_MASK = 0x1000,	/* Flag mask NTSC output */
--	CV_STANDARD_SD_NTSC_M,		/* NTSC (North America) output 1001 */
--	CV_STANDARD_SD_NTSC_J,		/* NTSC (Japan) output 1002 */
--	CV_STANDARD_SD_480I,		/* SDTV 480i output 1003 */
--	CV_STANDARD_SD_480P,		/* SDTV 480p output 1004 */
--	CV_STANDARD_HD_720_60P = 0x1800,/* HDTV 720/60p output 1800 */
--	CV_STANDARD_HD_1080_60I,	/* HDTV 1080/60i output 1801 */
--	CV_STANDARD_SD_PAL_MASK = 0x2000,/* Flag mask PAL output */
--	CV_STANDARD_SD_PAL_B,			/* PAL B output 2001 */
--	CV_STANDARD_SD_PAL_D,			/* PAL D output 2002 */
--	CV_STANDARD_SD_PAL_G,			/* PAL G output 2003 */
--	CV_STANDARD_SD_PAL_H,			/* PAL H output 2004 */
--	CV_STANDARD_SD_PAL_I,			/* PAL I output 2005 */
--	CV_STANDARD_SD_PAL_M,			/* PAL M output 2006 */
--	CV_STANDARD_SD_PAL_N,			/* PAL N output 2007 */
--	CV_STANDARD_SD_PAL_N_COMB,	/* PAL Combination N output 2008 */
--	CV_STANDARD_SD_PAL_60,		/* PAL 60 output (test mode) 2009 */
--	CV_STANDARD_SD_576I,		/* SDTV 576i output 2010 */
--	CV_STANDARD_SD_576P,		/* SDTV 576p output 2011 */
--	CV_STANDARD_HD_720_50P = 0x2800,/* HDTV 720/50p output 2800 */
--	CV_STANDARD_HD_1080_50I,	/* HDTV 1080/50i output 2801 */
--	CV_STANDARD_SD_SECAM_MASK = 0x4000, /* Flag mask SECAM output */
--	CV_STANDARD_SD_SECAM_B,		/* SECAM B output 4001 */
--	CV_STANDARD_SD_SECAM_D,		/* SECAM D output 4002 */
--	CV_STANDARD_SD_SECAM_G,		/* SECAM G output 4003 */
--	CV_STANDARD_SD_SECAM_H,		/* SECAM H output 4004 */
--	CV_STANDARD_SD_SECAM_K,		/* SECAM K output 4005 */
--	CV_STANDARD_SD_SECAM_K1,	/* SECAM K1 output 4006 */
--	CV_STANDARD_SD_SECAM_L,		/* SECAM L output 4007 */
--	CV_STANDARD_SD_SECAM_L1		/* SECAM L1 output 4009 */
--};
--
- enum display_output_bit_depth {
- 	PANEL_UNDEFINE = 0,
- 	PANEL_6BIT_COLOR = 1,
-@@ -253,11 +206,6 @@ union tv_standard_support {
- 	} bits;
- };
- 
--struct analog_tv_info {
--	union tv_standard_support tv_suppported;
--	union tv_standard_support tv_boot_up_default;
--};
--
- struct step_and_delay_info {
-     uint32_t step;
-     uint32_t delay;
-@@ -533,13 +481,6 @@ union optimization_flags {
- 
- /* Bitvector and bitfields of performance measurements
-  #IMPORTANT# Keep bitfields match bitvector! */
--enum perf_measure {
--	PERF_MEASURE_ADAPTER_POWER_STATE = 0x1,
--	PERF_MEASURE_DISPLAY_POWER_STATE = 0x2,
--	PERF_MEASURE_SET_MODE_SEQ = 0x4,
--	PERF_MEASURE_DETECT_AT_RESUME = 0x8,
--	PERF_MEASURE_MEMORY_READ_CONTROL = 0x10,
--};
- 
- union perf_measure_flags {
- 	struct {
-@@ -586,9 +527,5 @@ struct panel_backlight_boundaries {
- 	uint32_t max_signal_level;
- };
- 
--struct panel_backlight_default_levels {
--	uint32_t ac_level_percentage;
--	uint32_t dc_level_percentage;
--};
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-index a7c42f0..371b22b 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
-@@ -221,28 +221,6 @@ struct static_screen_events {
-  * ***************************************************************
-  */
- 
--/* GPIO/Register access sequences */
--enum io_register_sequence {
--	/* GLSync sequences to access SwapReady & SwapRequest
--	GPIOs - GLSync Connector parameter */
--	IO_REG_SEQUENCE_SWAPREADY_SET = 0,
--	IO_REG_SEQUENCE_SWAPREADY_RESET,
--	IO_REG_SEQUENCE_SWAPREADY_READ,
--	IO_REG_SEQUENCE_SWAPREQUEST_SET,
--	IO_REG_SEQUENCE_SWAPREQUEST_RESET,
--	IO_REG_SEQUENCE_SWAPREQUEST_READ,
--
--	/* Frame synchronization start/stop - display index parameter */
--	IO_REG_SEQUENCE_FRAMELOCK_STOP,
--	IO_REG_SEQUENCE_FRAMELOCK_START,
--
--	/* Flip lock/unlock - GLSync Connector parameter */
--	IO_REG_SEQUENCE_GLOBALSWAP_LOCK,
--	IO_REG_SEQUENCE_GLOBALSWAP_UNLOCK,
--
--	IO_REG_SEQUENCEENUM_MAX
--};
--
- #define IO_REGISTER_SEQUENCE_MAX_LENGTH 5
- 
- /*
-@@ -274,54 +252,11 @@ enum io_register_sequence {
-  *	security consideration.
-  */
- 
--/*
-- * The generic sequence to program/access registers or GPIOs.
-- * There could be 2 types of sequences - read and write.
-- * Read sequence may have 0 or more writes and in the end one read
-- * Write sequence may have 1 or more writes.
-- */
--struct io_reg_sequence {
--	/* Ordered array of register to program */
--	struct {
--		/* Offset of memory mapped register or GPIO */
--		uint32_t register_offset;
--		/* Mask to use at AND operation (Mandatory, comes
--		before OR operation) */
--		uint32_t and_mask;
--		union {
--			/* Mask to use at OR operation (For write
--			sequence only, comes after AND operation) */
--			uint32_t or_mask;
--			/* Number of bits to shift to get the actual value
--			(For read  sequence only, comes after AND operation) */
--			uint32_t bit_shift;
--		};
--	} io_registers[IO_REGISTER_SEQUENCE_MAX_LENGTH];
--
--	uint32_t steps_num; /* Total number of r/w steps in the sequence */
--};
--
- /* Sequence ID - uniqly defines sequence on single adapter */
--struct io_reg_sequence_id {
--	enum io_register_sequence sequence; /* Sequence enumeration Index/ID */
--	union {
--		/* Refers to object to which the sequence applies.*/
--		uint32_t index;
--		uint32_t display_index;
--		uint32_t controller_index;
--		uint32_t glsync_connector_index;
--	};
--};
- 
- struct fbc_info {
- 	bool fbc_enable;
- 	bool lpt_enable;
- };
- 
--/* Event to request TM change IRQ registration state */
--struct hotplug_irq_data {
--	bool disable;
--	struct graphics_object_id connector;
--};
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-index 4238eb0..81b4b93 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h
-@@ -51,21 +51,6 @@ struct hws_init_data {
- 
- /* TODO: below is three almost equal structures.
-  * We should decide what to do with them */
--struct blank_stream_param {
--	struct display_path *display_path;
--	uint32_t link_idx;
--	struct hw_crtc_timing timing;
--	struct link_settings link_settings;
--};
--
--struct enable_stream_param {
--	struct display_path *display_path;
--	uint32_t link_idx;
--	struct hw_crtc_timing timing;
--	struct link_settings link_settings;
--
--	const struct hw_path_mode *path_mode;
--};
- 
- struct enable_link_param {
- 	struct display_path *display_path;
-diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-index 60dcf81..511caf4 100644
---- a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h
-@@ -41,18 +41,6 @@ enum {
- 	HW_OTHER_PIPE_INDEX = 1
- };
- 
--struct hw_view_port_adjustment {
--	int32_t start_adjustment;
--	int32_t width;
--
--	enum controller_id controller_id;
--};
--
--struct hw_view_port_adjustments {
--	uint32_t view_ports_num;
--	struct hw_view_port_adjustment adjustments[HW_MAX_NUM_VIEWPORTS];
--};
--
- /* Timing standard */
- enum hw_timing_standard {
- 	HW_TIMING_STANDARD_UNDEFINED,
-@@ -156,12 +144,6 @@ struct hw_crtc_timing {
- 	} flags;
- };
- 
--struct hw_scaling_info {
--	struct view src;
--	struct view dst;
--	enum signal_type signal;
--};
--
- enum hw_color_space {
- 	HW_COLOR_SPACE_UNKNOWN = 0,
- 	HW_COLOR_SPACE_SRGB_FULL_RANGE,
-@@ -223,19 +205,6 @@ enum hw_dithering_options {
- 	HW_DITHERING_OPTION_DISABLE
- };
- 
--struct hw_stereo_mixer_params {
--	bool sub_sampling;
--	bool single_pipe;
--};
--
--struct hw_action_flags {
--	uint32_t RESYNC_PATH:1;
--	uint32_t TIMING_CHANGED:1;
--	uint32_t PIXEL_ENCODING_CHANGED:1;
--	uint32_t GAMUT_CHANGED:1;
--	uint32_t TURN_OFF_VCC:1;
--};
--
- enum hw_sync_request {
- 	HW_SYNC_REQUEST_NONE = 0,
- 	HW_SYNC_REQUEST_SET_INTERPATH,
-@@ -247,12 +216,6 @@ enum hw_sync_request {
- 	HW_SYNC_REQUEST_SET_STEREO3D
- };
- 
--struct hw_sync_info {
--	enum hw_sync_request sync_request;
--	uint32_t target_pixel_clock; /* in KHz */
--	enum sync_source sync_source;
--};
--
- /* TODO hw_info_frame and hw_info_packet structures are same as in encoder
-  * merge it*/
- struct hw_info_packet {
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index 85619fc..96b4ac9 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -28,46 +28,6 @@
- 
- #include "video_gamma_types.h"
- 
--enum ovl_alpha_blending_mode {
--	OVL_ALPHA_PER_PIXEL_GRPH_ALPHA_MODE = 0,
--	OVL_ALPHA_PER_PIXEL_OVL_ALPHA_MODE
--};
--
--enum ovl_surface_format {
--	OVL_SURFACE_FORMAT_UNKNOWN = 0,
--	OVL_SURFACE_FORMAT_YUY2,
--	OVL_SURFACE_FORMAT_UYVY,
--	OVL_SURFACE_FORMAT_RGB565,
--	OVL_SURFACE_FORMAT_RGB555,
--	OVL_SURFACE_FORMAT_RGB32,
--	OVL_SURFACE_FORMAT_YUV444,
--	OVL_SURFACE_FORMAT_RGB32_2101010
--};
--
--struct ovl_color_adjust_option {
--	uint32_t ALLOW_OVL_RGB_ADJUST:1;
--	uint32_t ALLOW_OVL_TEMPERATURE:1;
--	uint32_t FULL_RANGE:1; /* 0 for limited range it'is default for YUV */
--	uint32_t OVL_MATRIX:1;
--	uint32_t RESERVED:28;
--};
--
--struct overlay_adjust_item {
--	int32_t adjust; /* InInteger */
--	int32_t adjust_divider;
--};
--
--enum overlay_csc_adjust_type {
--	OVERLAY_CSC_ADJUST_TYPE_BYPASS = 0,
--	OVERLAY_CSC_ADJUST_TYPE_HW, /* without adjustments */
--	OVERLAY_CSC_ADJUST_TYPE_SW  /* use adjustments */
--};
--
--enum overlay_gamut_adjust_type {
--	OVERLAY_GAMUT_ADJUST_TYPE_BYPASS = 0,
--	OVERLAY_GAMUT_ADJUST_TYPE_SW /* use adjustments */
--};
--
- #define TEMPERATURE_MATRIX_SIZE 9
- #define MAXTRIX_SIZE TEMPERATURE_MAXTRIX_SIZE
- #define MAXTRIX_SIZE_WITH_OFFSET 12
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-index e910711..1e249ac 100644
---- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -29,13 +29,6 @@
- #include "set_mode_types.h"
- #include "gamma_types.h"
- 
--enum overlay_gamma_adjust {
--	OVERLAY_GAMMA_ADJUST_BYPASS,
--	OVERLAY_GAMMA_ADJUST_HW, /* without adjustments */
--	OVERLAY_GAMMA_ADJUST_SW /* use adjustments */
--
--};
--
- union video_gamma_flag {
- 	struct {
- 		uint32_t CONFIG_IS_CHANGED:1;
-@@ -44,13 +37,4 @@ union video_gamma_flag {
- 	uint32_t u_all;
- };
- 
--struct overlay_gamma_parameters {
--	union video_gamma_flag flag;
--	int32_t ovl_gamma_cont;
--	enum overlay_gamma_adjust adjust_type;
--	enum pixel_format desktop_surface;
--
--	/* here we grow with parameters if necessary */
--};
--
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch b/common/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch
deleted file mode 100644
index 37cd6b17..00000000
--- a/common/recipes-kernel/linux/files/1007-drm-amd-dal-remove-dead-code.patch
+++ /dev/null
@@ -1,719 +0,0 @@
-From 31cf95fbd0163fa4a00f497d8bf40996701d8806 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>
-Date: Thu, 24 Mar 2016 14:23:37 +0100
-Subject: [PATCH 1007/1110] drm/amd/dal: remove dead code.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Even more seriously ...
-
-Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  10 -
- drivers/gpu/drm/amd/dal/include/dcs_types.h        | 126 -------------
- drivers/gpu/drm/amd/dal/include/dmcu_types.h       |  15 --
- drivers/gpu/drm/amd/dal/include/dpcd_defs.h        | 209 ---------------------
- .../drm/amd/dal/include/grph_object_ctrl_defs.h    |  86 ---------
- .../gpu/drm/amd/dal/include/link_service_types.h   |  65 -------
- drivers/gpu/drm/amd/dal/include/video_csc_types.h  |  10 -
- .../gpu/drm/amd/dal/include/video_gamma_types.h    |   8 -
- 8 files changed, 529 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 9093e97..5994ad1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -148,16 +148,6 @@ struct dpcd_caps {
- 	int8_t branch_dev_name[6];
- };
- 
--union dp_wa {
--	struct {
--		/* keep DP receiver powered up on DisplayOutput */
--		uint32_t KEEP_RECEIVER_POWERED:1;
--
--		/* TODO: may add other member in.*/
--	} bits;
--	uint32_t raw;
--};
--
- /* DP MST stream allocation (payload bandwidth number) */
- struct link_mst_stream_allocation {
- 	/* DIG front */
-diff --git a/drivers/gpu/drm/amd/dal/include/dcs_types.h b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-index bccfd99..912310e 100644
---- a/drivers/gpu/drm/amd/dal/include/dcs_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dcs_types.h
-@@ -61,45 +61,6 @@ enum edid_screen_aspect_ratio {
- 	EDID_SCREEN_AR_4X5
- };
- 
--union cv_smart_dongle_modes {
--	uint8_t all;
--	struct cv_smart_dongle_switches {
--		uint8_t MODE_1080I:1;
--		uint8_t MODE_720P:1;
--		uint8_t MODE_540P:1;
--		uint8_t MODE_480P:1;
--		uint8_t MODE_480I:1;
--		uint8_t MODE_16_9:1;
--	} switches;
--};
--
--union cea_speaker_allocation_data_block {
--	struct {
--		uint32_t FL_FR:1;
--		uint32_t LFE:1;
--		uint32_t FC:1;
--		uint32_t RL_RR:1;
--		uint32_t RC:1;
--		uint32_t FLC_FRC:1;
--		uint32_t RLC_RRC:1;
--	} bits;
--	uint32_t raw;
--};
--
--union cea_video_capability_data_block {
--	struct {
--		uint8_t S_CE0:1;
--		uint8_t S_CE1:1;
--		uint8_t S_IT0:1;
--		uint8_t S_IT1:1;
--		uint8_t S_PT0:1;
--		uint8_t S_PT1:1;
--		uint8_t QS:1;
--		uint8_t QY:1;
--	} bits;
--	uint8_t raw;
--};
--
- enum stereo_3d_multi_presence {
- 	STEREO_3D_MULTI_NOT_PRESENT = 0,
- 	STEREO_3D_MULTI_ALL_FORMATS,
-@@ -131,47 +92,6 @@ enum dcs_interface_type {
- 	INTERFACE_TYPE_EDP
- };
- 
--
--union panel_misc_info {
--	struct {
--		uint32_t H_CUT_OFF:1;
--		uint32_t H_SYNC_POLARITY:1;/*0=Active High, 1=Active Low*/
--		uint32_t V_SYNC_POLARITY:1; /*0=Active High, 1=Active Low*/
--		uint32_t V_CUT_OFF:1;
--		uint32_t H_REPLICATION_BY_2:1;
--		uint32_t V_REPLICATION_BY_2:1;
--		uint32_t COMPOSITE_SYNC:1;
--		uint32_t INTERLACE:1;
--		uint32_t DOUBLE_CLOCK:1;
--		uint32_t RGB888:1;
--		uint32_t GREY_LEVEL:2;
--		uint32_t SPATIAL:1;
--		uint32_t TEMPORAL:1;
--		uint32_t API_ENABLED:1;
--	} bits;
--	uint32_t raw;
--};
--
--union hdtv_mode_support {
--	struct {
--		uint32_t HDTV_SUPPORT_480I:1;
--		uint32_t HDTV_SUPPORT_480P:1;
--		uint32_t HDTV_SUPPORT_576I25:1;
--		uint32_t HDTV_SUPPORT_576P50:1;
--		uint32_t HDTV_SUPPORT_720P:1;
--		uint32_t HDTV_SUPPORT_720P50:1;
--		uint32_t HDTV_SUPPORT_1080I:1;
--		uint32_t HDTV_SUPPORT_1080I25:1;
--		uint32_t HDTV_SUPPORT_1080P:1;
--		uint32_t HDTV_SUPPORT_1080P50:1;
--		uint32_t HDTV_SUPPORT_1080P24:1;
--		uint32_t HDTV_SUPPORT_1080P25:1;
--		uint32_t HDTV_SUPPORT_1080P30:1;
--		uint32_t HDTV_SUPPORT_16X9:1;
--	} bits;
--	uint32_t raw;
--};
--
- enum edid_retrieve_status {
- 	EDID_RETRIEVE_SUCCESS = 0,
- 	EDID_RETRIEVE_FAIL,
-@@ -424,50 +344,4 @@ enum monitor_patch_type {
- 	MONITOR_PATCH_TYPE_SINGLE_MODE_PACKED_PIXEL
- };
- 
--union dcs_monitor_patch_flags {
--        struct {
--                bool ERROR_CHECKSUM:1;
--                bool HDTV_WITH_PURE_DFP_EDID:1;
--                bool DO_NOT_USE_DETAILED_TIMING:1;
--                bool DO_NOT_USE_RANGE_LIMITATION:1;
--                bool EDID_EXTENTION_ERROR_CHECKSUM:1;
--                bool TURN_OFF_DISPLAY_BEFORE_MODE_CHANGE:1;
--                bool RESTRICT_VESA_MODE_TIMING:1;
--                bool DO_NOT_USE_EDID_MAX_PIX_CLK:1;
--                bool VENDOR_0:1;
--                bool RANDOM_CRT:1;/* 10 bits used including this one-*/
--                bool VENDOR_1:1;
--                bool LIMIT_PANEL_SUPPORT_RGB_ONLY:1;
--                bool PACKED_PIXEL_FORMAT:1;
--                bool LARGE_PANEL:1;
--                bool STEREO_SUPPORT:1;
--                bool DUAL_EDID_PANEL:1;
--                bool IGNORE_19X12_STD_TIMING:1;
--                bool MULTIPLE_PACKED_TYPE:1;
--                bool RESET_TX_ON_DISPLAY_POWER_ON:1;
--                bool ALLOW_ONLY_CE_MODE:1;/* 20 bits used including this one*/
--                bool RESTRICT_PROT_DUAL_LINK_DVI:1;
--                bool FORCE_LINK_RATE:1;
--                bool DELAY_AFTER_DP_RECEIVER_POWER_UP:1;
--                bool KEEP_DP_RECEIVER_POWERED:1;
--                bool DELAY_BEFORE_READ_EDID:1;
--                bool DELAY_AFTER_PIXEL_FORMAT_CHANGE:1;
--                bool INCREASE_DEFER_WRITE_RETRY_I2C_OVER_AUX:1;
--                bool NO_DEFAULT_TIMINGS:1;
--                bool ADD_CEA861_DETAILED_TIMING_VIC16:1;
--                bool ADD_CEA861_DETAILED_TIMING_VIC31:1; /* 30 bits*/
--                bool DELAY_BEFORE_UNMUTE:1;
--                bool RETRY_LINK_TRAINING_ON_FAILURE:1;
--                bool ALLOW_AUX_WHEN_HPD_LOW:1;
--                bool TILED_DISPLAY:1;
--                bool DISABLE_PSR_ENTRY_ABORT:1;
--                bool INTERMITTENT_EDID_ERROR:1;/* 36 bits total*/
--                bool VID_STREAM_DIFFER_TO_SYNC:1;/* 37 bits total*/
--                bool EXTRA_DELAY_ON_DISCONNECT:1;/* 38 bits total*/
--                bool DELAY_AFTER_DISABLE_BACKLIGHT_DFS_BYPASS:1;/* 39 bits total*/
--        } flags;
--        uint64_t raw;
--};
--
- #endif /* __DAL_DCS_TYPES_H__ */
--
-diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_types.h b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-index 00f9fa4..b74bb5b 100644
---- a/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/dmcu_types.h
-@@ -129,21 +129,6 @@ struct dmcu_context {
- 	uint32_t vsync_rate_hz;
- };
- 
--union dmcu_psr_level {
--	struct {
--		bool SKIP_CRC:1;
--		bool SKIP_DP_VID_STREAM_DISABLE:1;
--		bool SKIP_PHY_POWER_DOWN:1;
--		bool SKIP_AUX_ACK_CHECK:1;
--		bool SKIP_CRTC_DISABLE:1;
--		bool SKIP_AUX_RFB_CAPTURE_CHECK:1;
--		bool SKIP_SMU_NOTIFICATION:1;
--		bool SKIP_AUTO_STATE_ADVANCE:1;
--		bool DISABLE_PSR_ENTRY_ABORT:1;
--	} bits;
--	uint32_t u32all;
--};
--
- enum varibright_command {
- 	VARIBRIGHT_CMD_SET_VB_LEVEL = 0,
- 	VARIBRIGHT_CMD_USER_ENABLE,
-diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-index e251cff..27b7aee 100644
---- a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h
-@@ -414,16 +414,6 @@ union mstm_cap {
- 	uint8_t raw;
- };
- 
--union mstm_cntl {
--	struct {
--		uint8_t MST_EN:1;
--		uint8_t UP_REQ_EN:1;
--		uint8_t UPSTREAM_IS_SRC:1;
--		uint8_t RESERVED:5;
--	} bits;
--	uint8_t raw;
--};
--
- union lane_count_set {
- 	struct {
- 		uint8_t LANE_COUNT_SET:5;
-@@ -434,44 +424,6 @@ union lane_count_set {
- 	uint8_t raw;
- };
- 
--/* for DPCD_ADDRESS_I2C_SPEED_CNTL_CAP
-- * and DPCD_ADDRESS_I2C_SPEED_CNTL
-- */
--union i2c_speed {
--	struct {
--		uint8_t _1KBPS:1;
--		uint8_t _5KBPS:1;
--		uint8_t _10KBPS:1;
--		uint8_t _100KBPS:1;
--		uint8_t _400KBPS:1;
--		uint8_t _1MBPS:1;
--		uint8_t reserved:2;
--	} bits;
--	uint8_t raw;
--};
--
--union payload_table_update_status {
--	struct {
--		uint8_t VC_PAYLOAD_TABLE_UPDATED:1;
--		uint8_t ACT_HANDLED:1;
--	} bits;
--	uint8_t raw;
--};
--
--union device_irq_esi_0 {
--	struct {
--		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
--		uint8_t AUTOMATED_TEST_REQUEST:1;
--		uint8_t CP_IRQ:1;
--		uint8_t MCCS_IRQ:1;
--		uint8_t DOWN_REP_MSG_RDY:1;
--		uint8_t UP_REQ_MSG_RDY:1;
--		uint8_t SINK_SPECIFIC_IRQ:1;
--		uint8_t RESERVED:1;
--	} bits;
--	uint8_t raw;
--};
--
- union lane_status {
- 	struct {
- 		uint8_t CR_DONE_0:1;
-@@ -500,17 +452,6 @@ union device_service_irq {
- 	uint8_t raw;
- };
- 
--union downstream_port {
--	struct {
--		uint8_t PRESENT:1;
--		uint8_t TYPE:2;
--		uint8_t FORMAT_CONV:1;
--		uint8_t DETAILED_CAPS:1;
--		uint8_t RESERVED:3;
--	} bits;
--	uint8_t raw;
--};
--
- union sink_count {
- 	struct {
- 		uint8_t SINK_COUNT:6;
-@@ -540,74 +481,6 @@ union lane_adjust {
- 	uint8_t raw;
- };
- 
--/* Automated test structures */
--union test_request {
--	struct {
--		uint8_t LINK_TRAINING:1;
--		uint8_t LINK_TEST_PATTERN:1;
--		uint8_t EDID_READ:1;
--		uint8_t PHY_TEST_PATTERN:1;
--		uint8_t AUDIO_TEST_PATTERN:1;
--		uint8_t AUDIO_TEST_NO_VIDEO:1;
--		uint8_t RESERVED:1;
--		uint8_t TEST_STEREO_3D:1;
--	} bits;
--	uint8_t raw;
--};
--
--union test_response {
--	struct {
--		uint8_t ACK:1;
--		uint8_t NO_ACK:1;
--		uint8_t RESERVED:6;
--	} bits;
--	uint8_t raw;
--};
--
--union link_test_pattern {
--	struct {
--		uint8_t PATTERN:2;/*DpcdLinkTestPatterns*/
--		uint8_t RESERVED:6;
--	} bits;
--	uint8_t raw;
--};
--
--union test_misc {
--	struct dpcd_test_misc_bits {
--		uint8_t SYNC_CLOCK:1;
--		uint8_t CLR_FORMAT:2;/*DpcdTestColorFormat*/
--		uint8_t DYN_RANGE:1;/*DpcdTestDynRange*/
--		uint8_t YCBCR:1;/*DpcdTestYCbCrStandard*/
--		uint8_t BPC:3;/*DpcdTestBitDepth*/
--	} bits;
--	uint8_t raw;
--};
--
--union phy_test_pattern {
--	struct {
--		/* This field is 2 bits for DP1.1 and 3 bits for DP1.2.*/
--		uint8_t PATTERN:3;
--		uint8_t RESERVED:5;/* BY spec, bit7:2 is 0 for DP1.1.*/
--	} bits;
--	uint8_t raw;
--};
--
--union audio_test_mode {
--	struct {
--		uint8_t SAMPLING_RATE:4;
--		uint8_t CHANNEL_COUNT:4;
--	} bits;
--	uint8_t raw;
--};
--
--union audio_test_pattern_period {
--	struct {
--		uint8_t PATTERN_PERIOD:4;
--		uint8_t RESERVED:4;
--	} bits;
--	uint8_t raw;
--};
--
- union dpcd_training_pattern {
- 	struct {
- 		uint8_t TRAINING_PATTERN_SET:4;
-@@ -641,68 +514,8 @@ union dpcd_training_lane {
- post cursor 2 level of Training Pattern 2 or 3*/
- /* The DPCD addresses are 0x10F (TRAINING_LANE0_1_SET2)
- and 0x110 (TRAINING_LANE2_3_SET2)*/
--union dpcd_training_lane_set2 {
--	struct {
--		uint8_t POST_CURSOR2_SET:2;
--		uint8_t MAX_POST_CURSOR2_REACHED:1;
--		uint8_t RESERVED:1;
--	} bits;
--	uint8_t raw;
--};
--
--union dpcd_psr_configuration {
--	struct {
--		uint8_t ENABLE:1;
--		uint8_t TRANSMITTER_ACTIVE_IN_PSR:1;
--		uint8_t CRC_VERIFICATION:1;
--		uint8_t FRAME_CAPTURE_INDICATION:1;
--		uint8_t LINE_CAPTURE_INDICATION:1;
--		uint8_t IRQ_HPD_WITH_CRC_ERROR:1;
--		uint8_t RESERVED:2;
--	} bits;
--	uint8_t raw;
--};
--
--union psr_error_status {
--	struct {
--		uint8_t LINK_CRC_ERROR:1;
--		uint8_t RFB_STORAGE_ERROR:1;
--		uint8_t RESERVED:6;
--	} bits;
--	uint8_t raw;
--};
--
--union psr_event_status_ind {
--	struct {
--		uint8_t SINK_PSR_CAP_CHANGE:1;
--		uint8_t RESERVED:7;
--	} bits;
--	uint8_t raw;
--};
--
--union psr_sink_psr_status {
--	struct {
--		uint8_t SINK_SELF_REFRESH_STATUS:3;
--		uint8_t RESERVED:5;
--	} bits;
--	uint8_t raw;
--};
- 
- /* EDP related 0x701 */
--union edp_generial_cap1 {
--	struct {
--		uint8_t TCON_BACKLIGHT_ADJUSTMENT_CAPABLE:1;
--		uint8_t BACKLIGHT_PIN_ENABLE_CAPABLE:1;
--		uint8_t BACKLIGHT_AUX_ENABLE_CAPABLE:1;
--		uint8_t PANEL_SELFTEST_PIN_ENABLE_CAPABLE:1;
--		uint8_t BACKLIGHT_SELFTEST_AUX_ENABLE_CAPABLE:1;
--		uint8_t FRC_ENABLE_CAPABLE:1;
--		uint8_t COLOR_ENGINE_CAPABLE:1;
--		/*bit 7, pane can be controlled by 0x600*/
--		uint8_t SET_POWER_CAPABLE:1;
--	} bits;
--	uint8_t raw;
--};
- 
- /* TMDS-converter related */
- union dwnstream_port_caps_byte0 {
-@@ -763,19 +576,6 @@ union dwnstream_port_caps_byte3_hdmi {
- 
- /*4-byte structure for detailed capabilities of a down-stream port
- (DP-to-TMDS converter).*/
--union dwnstream_portx_caps {
--	struct {
--		union dwnstream_port_caps_byte0 byte0;
--		uint8_t max_tmds_clk;/* byte1 */
--		union dwnstream_port_caps_byte2 byte2;
--
--		union {
--			union dwnstream_port_caps_byte3_dvi byte_dvi;
--			union dwnstream_port_caps_byte3_hdmi byte_hdmi;
--		} byte3;
--	} bytes;
--	uint8_t raw[4];
--};
- 
- union sink_status {
- 	struct {
-@@ -862,15 +662,6 @@ union edp_configuration_cap {
- 	uint8_t raw;
- };
- 
--union psr_capabilities {
--	struct {
--		uint8_t EXIT_LT_NOT_REQ:1;
--		uint8_t RFB_SETUP_TIME:3;
--		uint8_t RESERVED:4;
--	} bits;
--	uint8_t raw;
--};
--
- union training_aux_rd_interval {
- 	struct {
- 		uint8_t TRAINIG_AUX_RD_INTERVAL:7;
-diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-index 11b1b99..50e3f0a 100644
---- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
-@@ -189,23 +189,6 @@ struct firmware_info {
- 	uint8_t remote_display_config;
- };
- 
--/* direct HW (mmBIOS_SCRATCH_2) translation! */
--union tv_standard_support {
--	uint8_t u_all;
--	struct {
--		bool TV_SUPPORT_NTSC:1;
--		bool TV_SUPPORT_NTSCJ:1;
--
--		bool TV_SUPPORT_PAL:1;
--		bool TV_SUPPORT_PALM:1;
--		bool TV_SUPPORT_PALCN:1;
--		bool TV_SUPPORT_PALN:1;
--		bool TV_SUPPORT_PAL60:1;
--
--		bool TV_SUPPORT_SECAM:1;
--	} bits;
--};
--
- struct step_and_delay_info {
-     uint32_t step;
-     uint32_t delay;
-@@ -406,47 +389,6 @@ struct bios_event_info {
- 	bool backlight_changed;
- };
- 
--union stereo_3d_support {
--	struct {
--		/* HW can alter left and right image sequentially */
--		uint32_t FRAME_ALTERNATE:1;
--		/* Frame Alternate + HW can integrate stereosync
--		signal into TMDS stream */
--		uint32_t DVI_FRAME_ALT:1;
--		/* Frame Alternate + HW can integrate stereosync
--		signal into DP stream */
--		uint32_t DISPLAY_PORT_FRAME_ALT:1;
--		/* Frame Alternate + HW can drive stereosync signal
--		on separate line */
--		uint32_t SIDEBAND_FRAME_ALT:1;
--		/* SW allowed to pack left and right image into single frame.
--		Used for HDMI only, DP has it's own flags. */
--		uint32_t SW_FRAME_PACK:1;
--		/* HW can pack left and right image into single HDMI frame */
--		uint32_t PROGRESSIVE_FRAME_PACK:1;
--		/* HW can pack left and right interlaced images into
--		single HDMI frame */
--		uint32_t INTERLACE_FRAME_PACK:1;
--		/* HW can pack left and right images into single DP frame */
--		uint32_t DISPLAY_PORT_FRAME_PACK:1;
--		/* SW can pack left and right images into single DP frame */
--		uint32_t DISPLAY_PORT_SW_FRAME_PACK:1;
--		/* HW can mix left and right images into single image */
--		uint32_t INTERLEAVE:1;
--		/* HW can mix left and right interlaced images
--		into single image */
--		uint32_t INTERLACE_INTERLEAVE:1;
--		/* Allow display-based formats (whatever supported)
--		in WS stereo mode */
--		uint32_t DISPLAY_3DIN_WS_MODE:1;
--		/* Side-by-side, packed by application/driver into 2D frame */
--		uint32_t SIDE_BY_SIDE_SW_PACKED:1;
--		/* Top-and-bottom, packed by application/driver into 2D frame */
--		uint32_t TOP_AND_BOTTOM_SW_PACKED:1;
--	} bits;
--	uint32_t u_all;
--};
--
- /* Bitvector and bitfields of possible optimizations
-  #IMPORTANT# Keep bitfields match bitvector! */
- enum optimization_feature {
-@@ -463,37 +405,9 @@ enum optimization_feature {
- 	OF_SKIP_POWER_DOWN_INACTIVE_ENCODER = 0x80
- };
- 
--union optimization_flags {
--	struct {
--		/* Don't do HW programming if panels were enabled by VBIOS */
--		uint32_t SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:1;
--		uint32_t SKIP_RESET_OF_ALL_HW_ON_S3RESUME:1;
--		uint32_t SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME:1;
--		uint32_t SKIP_POWER_UP_VBIOS_ENABLED_ENCODER:1;
--		/* Do not turn off VCC while powering down on boot or resume */
--		uint32_t KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME:1;
--		/* Do not turn off VCC while performing SetMode */
--		uint32_t KEEP_VCC_DURING_SET_MODE:1;
--		uint32_t DO_NOT_WAIT_FOR_HPD_LOW:1;
--	} bits;
--	uint32_t u_all;
--};
--
- /* Bitvector and bitfields of performance measurements
-  #IMPORTANT# Keep bitfields match bitvector! */
- 
--union perf_measure_flags {
--	struct {
--		uint32_t ADAPTER_POWER_STATE:1;
--		uint32_t DISPLAY_POWER_STATE:1;
--		uint32_t SET_MODE_SEQ:1;
--		uint32_t DETECT_AT_RESUME:1;
--		uint32_t MEMORY_READ_CONTROL:1;
--
--	} bits;
--	uint32_t u_all;
--};
--
- enum {
- 	PERF_MEASURE_POWERCODE_OFFSET = 0x0,
- 	PERF_MEASURE_POWER_CODE_MASK = 0xFF,
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index a14c4af..5dd75a3 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -82,46 +82,6 @@ enum edp_revision {
- 	EDP_REVISION_13 = 0x02
- };
- 
--/* DPCD_ADDR_DOWNSTREAM_PORT_PRESENT register value */
--union dpcd_downstream_port {
--	struct {
--#if defined(LITTLEENDIAN_CPU)
--		uint8_t PRESENT:1;
--		uint8_t TYPE:2;
--		uint8_t FORMAT_CONV:1;
--		uint8_t RESERVED:4;
--#elif defined(BIGENDIAN_CPU)
--		uint8_t RESERVED:4;
--		uint8_t FORMAT_CONV:1;
--		uint8_t TYPE:2;
--		uint8_t PRESENT:1;
--#else
--	#error ARCH not defined!
--#endif
--	} bits;
--
--	uint8_t raw;
--};
--
--/* DPCD_ADDR_SINK_COUNT register value */
--union dpcd_sink_count {
--	struct {
--#if defined(LITTLEENDIAN_CPU)
--		uint8_t SINK_COUNT:6;
--		uint8_t CP_READY:1;
--		uint8_t RESERVED:1;
--#elif defined(BIGENDIAN_CPU)
--		uint8_t RESERVED:1;
--		uint8_t CP_READY:1;
--		uint8_t SINK_COUNT:6;
--#else
--	#error ARCH not defined!
--#endif
--	} bits;
--
--	uint8_t raw;
--};
--
- enum {
- 	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
- };
-@@ -244,31 +204,6 @@ union dpcd_training_lane_set {
- 	uint8_t raw;
- };
- 
--/* DPCD_ADDR_TRAINING_LANEx_SET2 registers value - since DP 1.2 */
--union dpcd_training_lanes_set2 {
--	struct {
--#if defined(LITTLEENDIAN_CPU)
--		uint8_t LANE0_POST_CURSOR2_SET:2;
--		uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1;
--		uint8_t LANE0_RESERVED:1;
--		uint8_t LANE1_POST_CURSOR2_SET:2;
--		uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1;
--		uint8_t LANE1_RESERVED:1;
--#elif defined(BIGENDIAN_CPU)
--		uint8_t LANE1_RESERVED:1;
--		uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1;
--		uint8_t LANE1_POST_CURSOR2_SET:2;
--		uint8_t LANE0_RESERVED:1;
--		uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1;
--		uint8_t LANE0_POST_CURSOR2_SET:2;
--#else
--	#error ARCH not defined!
--#endif
--	} bits;
--
--	uint8_t raw;
--};
--
- /**
-  * @brief represent the 16 byte
-  *  global unique identifier
-diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-index 96b4ac9..258e5ad 100644
---- a/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h
-@@ -32,14 +32,4 @@
- #define MAXTRIX_SIZE TEMPERATURE_MAXTRIX_SIZE
- #define MAXTRIX_SIZE_WITH_OFFSET 12
- 
--/* overlay adjustment input */
--union ovl_csc_flag {
--	uint32_t u_all;
--	struct {
--		uint32_t CONFIG_IS_CHANGED:1;
--		uint32_t RESERVED:31;
--	} bits;
--};
--
--
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-index 1e249ac..5c70a75 100644
---- a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h
-@@ -29,12 +29,4 @@
- #include "set_mode_types.h"
- #include "gamma_types.h"
- 
--union video_gamma_flag {
--	struct {
--		uint32_t CONFIG_IS_CHANGED:1;
--		uint32_t RESERVED:31;
--	} bits;
--	uint32_t u_all;
--};
--
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1008-drm-amd-dal-remove-dead-code.patch b/common/recipes-kernel/linux/files/1008-drm-amd-dal-remove-dead-code.patch
deleted file mode 100644
index 4b1db4bb..00000000
--- a/common/recipes-kernel/linux/files/1008-drm-amd-dal-remove-dead-code.patch
+++ /dev/null
@@ -1,127 +0,0 @@
-From 7337cf1a1fc34ed24112079627d60b762f604c38 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>
-Date: Thu, 24 Mar 2016 14:26:18 +0100
-Subject: [PATCH 1008/1110] drm/amd/dal: remove dead code.
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Dead seriously ...
-
-Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dc_types.h              |  5 --
- .../gpu/drm/amd/dal/include/link_service_types.h   | 61 ----------------------
- 2 files changed, 66 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-index 8bc0413..4d9b24a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
-@@ -358,11 +358,6 @@ struct dc_mode_info {
- 	struct dc_mode_flags flags;
- };
- 
--struct dc_mode_timing {
--	struct dc_mode_info mode_info;
--	struct dc_crtc_timing crtc_timing;
--};
--
- enum dc_power_state {
- 	DC_POWER_STATE_ON = 1,
- 	DC_POWER_STATE_STANDBY,
-diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-index 5dd75a3..96e6b38 100644
---- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
-+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
-@@ -46,12 +46,6 @@ enum link_service_type {
- 	LINK_SERVICE_TYPE_MAX
- };
- 
--struct link_validation_flags {
--	uint32_t DYNAMIC_VALIDATION:1;
--	uint32_t CANDIDATE_TIMING:1;
--	uint32_t START_OF_VALIDATION:1;
--};
--
- enum dpcd_value_mask {
- 	DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F,
- 	DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40,
-@@ -173,13 +167,6 @@ struct link_service_init_data {
- 	struct topology_mgr *tm;
- };
- 
--/**
-- * @brief LinkServiceInitOptions to set certain bits
-- */
--struct LinkServiceInitOptions {
--	uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1;
--};
--
- /* DPCD_ADDR_TRAINING_LANEx_SET registers value */
- union dpcd_training_lane_set {
- 	struct {
-@@ -227,33 +214,6 @@ struct mst_rad {
- 	int8_t rad_str[25];
- };
- 
--/**
-- * @brief this structure is used to report
-- * properties associated to a sink device
-- */
--struct mst_sink_info {
--	/* global unique identifier */
--	struct mst_guid guid;
--	/* relative address */
--	struct mst_rad  rad;
--	/* total bandwidth available on the DP connector */
--	uint32_t total_available_bandwidth_in_mbps;
--	/* bandwidth allocated to the sink device. */
--	uint32_t allocated_bandwidth_in_mbps;
--	/* bandwidth consumed to support for the current mode. */
--	uint32_t consumed_bandwidth_in_mbps;
--};
--
--/**
-- * @brief represent device information in MST topology
-- */
--struct mst_device_info {
--	/* global unique identifier*/
--	struct mst_guid guid;
--	/* relative address*/
--	struct mst_rad  rad;
--};
--
- /* DP MST stream allocation (payload bandwidth number) */
- struct dp_mst_stream_allocation {
- 	uint8_t vcp_id;
-@@ -270,25 +230,4 @@ struct dp_mst_stream_allocation_table {
- 	struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
- };
- 
--struct dp_test_event_data {
--	/*size of parameters (starting from params) in bytes*/
--	uint32_t size;
--	/*parameters block*/
--	uint32_t params[1];
--};
--
--struct psr_caps {
--	/* These parameters are from PSR capabilities reported by Sink DPCD. */
--	uint8_t psr_version;
--	uint32_t psr_rfb_setup_time;
--	bool psr_exit_link_training_req;
--
--	/* These parameters are calculated in Driver, based on display timing
--	 * and Sink capabilities.
--	 * If VBLANK region is too small and Sink takes a long time to power up
--	 * Remote Frame Buffer, it may take an extra frame to enter PSR */
--	bool psr_frame_capture_indication_req;
--	uint32_t psr_sdp_transmit_line_num_deadline;
--};
--
- #endif /*__DAL_LINK_SERVICE_TYPES_H__*/
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1009-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch b/common/recipes-kernel/linux/files/1009-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch
deleted file mode 100644
index e689f9a2..00000000
--- a/common/recipes-kernel/linux/files/1009-drm-amd-powerplay-fix-fan-speed-percent-setting-erro.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 2e57cc484375d4fe38179dc38c6e7fa2c3cc4684 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Mon, 11 Apr 2016 14:26:12 -0400
-Subject: [PATCH 1009/1110] drm/amd/powerplay: fix fan speed percent setting
- error on Polaris10
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-index d2f553d..d39c89b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-@@ -220,8 +220,8 @@ int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
- 	if (duty100 == 0)
- 		return -EINVAL;
- 
--	tmp64 = (uint64_t)speed * 100;
--	do_div(tmp64, duty100);
-+	tmp64 = (uint64_t)speed * duty100;
-+	do_div(tmp64, 100);
- 	duty = (uint32_t)tmp64;
- 
- 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1010-drm-amd-dal-fix-the-array-size-for-displays_data-of-.patch b/common/recipes-kernel/linux/files/1010-drm-amd-dal-fix-the-array-size-for-displays_data-of-.patch
deleted file mode 100644
index 57a8dbc6..00000000
--- a/common/recipes-kernel/linux/files/1010-drm-amd-dal-fix-the-array-size-for-displays_data-of-.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 73edf66bd65a38dcf1d941eb8a2cad01ae999116 Mon Sep 17 00:00:00 2001
-From: Junwei Zhang <Jerry.Zhang@amd.com>
-Date: Thu, 7 Apr 2016 13:31:43 +0800
-Subject: [PATCH 1010/1110] drm/amd/dal: fix the array size for displays_data
- of bw_calcs_mode_data
-
-Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-index da00b2e..6961c82 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
-@@ -278,7 +278,7 @@ struct bw_calcs_input_single_display {
- 	enum bw_defines underlay_mode;
- };
- 
--#define BW_CALCS_MAX_NUM_DISPLAYS 3
-+#define BW_CALCS_MAX_NUM_DISPLAYS 6
- 
- struct bw_calcs_mode_data {
- 	/* data for all displays */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1011-drm-amd-dal-make-a-type-safe-cgs_device-struct.patch b/common/recipes-kernel/linux/files/1011-drm-amd-dal-make-a-type-safe-cgs_device-struct.patch
deleted file mode 100644
index f7654f2d..00000000
--- a/common/recipes-kernel/linux/files/1011-drm-amd-dal-make-a-type-safe-cgs_device-struct.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From a9c68ab977d0245a72ef467395c1dcb32e4928a3 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Tue, 12 Apr 2016 12:30:24 -0400
-Subject: [PATCH 1011/1110] drm/amd/dal: make a type-safe cgs_device struct.
-
-This is just a type-safety things to avoid everyone taking void *,
-it doesn't change anything.
-
-agd5f: split out from Dave's original patch that included
-base amdgpu and dal.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h | 2 +-
- drivers/gpu/drm/amd/dal/dc/dc.h               | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-index 34f1f9f..d497b6d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
-@@ -75,7 +75,7 @@ struct irq_list_head {
- struct amdgpu_display_manager {
- 	struct dal *dal;
- 	struct dc *dc;
--	void *cgs_device;
-+	struct cgs_device *cgs_device;
- 	/* lock to be used when DAL is called from SYNC IRQ context */
- 	spinlock_t dal_lock;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
-index d5bb183..b8d0786 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
-@@ -64,7 +64,7 @@ struct dc_init_data {
- 	struct hw_asic_id asic_id;
- 	struct dal_override_parameters display_param;
- 	void *driver; /* ctx */
--	void *cgs_device;
-+	struct cgs_device *cgs_device;
- 
- 	uint8_t num_virtual_links;
- 	/*
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1012-drm-amd-dal-remove-bios-parser-function-table.patch b/common/recipes-kernel/linux/files/1012-drm-amd-dal-remove-bios-parser-function-table.patch
deleted file mode 100644
index 468f6197..00000000
--- a/common/recipes-kernel/linux/files/1012-drm-amd-dal-remove-bios-parser-function-table.patch
+++ /dev/null
@@ -1,2301 +0,0 @@
-From 1c9dcbf65903c09af8c5b0df8ae1450375280445 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 16:56:03 +1000
-Subject: [PATCH 1012/1110] drm/amd/dal: remove bios parser function table.
-
-This table serves no great purpose, direct calling the APIs
-in the code works just as well.
-
-before:
-1096306	 141169	   1532	1239007	 12e7df	drivers/gpu/drm/amd/amdgpu/amdgpu.ko
-after:
-1094986	 141169	   1532	1237687	 12e2b7	drivers/gpu/drm/amd/amdgpu/amdgpu.ko
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  63 ++-
- .../drm/amd/dal/dc/adapter/wireless_data_source.c  |   2 +-
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 423 ++++++---------------
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h      |   3 +-
- .../dal/dc/bios/dce112/bios_parser_helper_dce112.c | 178 +--------
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   6 +-
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         | 412 +++++++++-----------
- .../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c    |   3 +-
- .../drm/amd/dal/dc/dce110/dce110_clock_source.c    |  49 +--
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  11 +-
- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c    |   2 +-
- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c  |   6 +-
- .../amd/dal/dc/dce110/dce110_timing_generator.c    |   6 +-
- .../drm/amd/dal/dc/dce112/dce112_clock_source.c    |   6 +-
- .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c    |   2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c  |   2 +-
- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c  |   2 +-
- .../drm/amd/dal/dc/dce80/dce80_stream_encoder.c    |   6 +-
- .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |   2 +-
- .../amd/dal/dc/gpu/dce112/display_clock_dce112.c   |   4 +-
- .../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c |   2 +-
- 21 files changed, 386 insertions(+), 804 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 308d456..810776b 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -234,8 +234,8 @@ static void initialize_backlight_caps(
- 			return;
- 	}
- 
--	if (dcb->funcs->get_firmware_info(dcb, &fw_info) != BP_RESULT_OK ||
--		dcb->funcs->get_embedded_panel_info(dcb, &panel_info) != BP_RESULT_OK)
-+	if (dc_bios_get_firmware_info(dcb, &fw_info) != BP_RESULT_OK ||
-+		dc_bios_get_embedded_panel_info(dcb, &panel_info) != BP_RESULT_OK)
- 		return;
- 
- 	params.data = &caps;
-@@ -540,7 +540,7 @@ static bool get_hpd_info(struct adapter_service *as,
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	return BP_RESULT_OK == dcb->funcs->get_hpd_info(dcb, id, info);
-+	return BP_RESULT_OK == dc_bios_get_hpd_info(dcb, id, info);
- }
- 
- /*
-@@ -693,7 +693,7 @@ static void adapter_service_destruct(
- 	dal_gpio_service_destroy(&as->gpio_service);
- 	dal_asic_capability_destroy(&as->asic_cap);
- 
--	dcb->funcs->destroy_integrated_info(dcb, &as->integrated_info);
-+	dc_bios_destroy_integrated_info(dcb, &as->integrated_info);
- 
- 	if (as->dcb_internal) {
- 		/* We are responsible only for destruction of Internal BIOS.
-@@ -802,9 +802,9 @@ static bool adapter_service_construct(
- 	/* Avoid wireless encoder creation in upstream branch. */
- 
- 	/* Integrated info is not provided on discrete ASIC. NULL is allowed */
--	as->integrated_info = dcb->funcs->create_integrated_info(dcb);
-+	as->integrated_info = dc_bios_create_integrated_info(dcb);
- 
--	dcb->funcs->post_init(dcb);
-+	dc_bios_post_init(dcb);
- 
- 	/* Generate backlight translation table and initializes
- 			  other brightness properties */
-@@ -965,7 +965,7 @@ uint8_t dal_adapter_service_get_connectors_num(
- 
- 	dcb = dal_adapter_service_get_bios_parser(as);
- 
--	vbios_connectors_num = dcb->funcs->get_connectors_number(dcb);
-+	vbios_connectors_num = dc_bios_get_connectors_number(dcb);
- 
- 	wireless_connectors_num = wireless_get_connectors_num(as);
- 
-@@ -1002,7 +1002,7 @@ uint32_t dal_adapter_service_get_src_num(
- 	if (is_wireless_object(id))
- 		return wireless_get_srcs_num(as, id);
- 	else
--		return dcb->funcs->get_src_number(dcb, id);
-+		return dc_bios_get_src_number(dcb, id);
- }
- 
- /**
-@@ -1027,7 +1027,7 @@ struct graphics_object_id dal_adapter_service_get_src_obj(
- 	if (is_wireless_object(id))
- 		src_object_id = wireless_get_src_obj_id(as, id, index);
- 	else {
--		if (BP_RESULT_OK != dcb->funcs->get_src_obj(dcb, id, index,
-+		if (BP_RESULT_OK != dc_bios_get_src_obj(dcb, id, index,
- 				&src_object_id)) {
- 			src_object_id =
- 				dal_graphics_object_id_init(
-@@ -1058,12 +1058,12 @@ struct graphics_object_id dal_adapter_service_get_connector_obj_id(
- 
- 	dcb = dal_adapter_service_get_bios_parser(as);
- 
--	bios_connectors_num = dcb->funcs->get_connectors_number(dcb);
-+	bios_connectors_num = dc_bios_get_connectors_number(dcb);
- 
- 	if (connector_index >= bios_connectors_num)
- 		return wireless_get_connector_id(as, connector_index);
- 	else
--		return dcb->funcs->get_connector_id(dcb, connector_index);
-+		return dc_bios_get_connector_id(dcb, connector_index);
- }
- 
- bool dal_adapter_service_get_device_tag(
-@@ -1074,8 +1074,8 @@ bool dal_adapter_service_get_device_tag(
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	if (BP_RESULT_OK == dcb->funcs->get_device_tag(dcb,
--			connector_object_id, device_tag_index, info))
-+	if (BP_RESULT_OK == dc_bios_get_device_tag(dcb,
-+						   connector_object_id, device_tag_index, info))
- 		return true;
- 	else
- 		return false;
-@@ -1087,7 +1087,7 @@ bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	return dcb->funcs->is_device_id_supported(dcb, id);
-+	return dc_bios_is_device_id_supported(dcb, id);
- }
- 
- bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as)
-@@ -1130,7 +1130,7 @@ uint8_t dal_adapter_service_get_clock_sources_num(
- 	 * Check is system supports the use of the External clock source
- 	 * as a clock source for DP
- 	 */
--	enum bp_result bp_result = dcb->funcs->get_firmware_info(dcb, &fw_info);
-+	enum bp_result bp_result = dc_bios_get_firmware_info(dcb, &fw_info);
- 
- 	if (BP_RESULT_OK == bp_result &&
- 			fw_info.external_clock_source_frequency_for_dp != 0)
-@@ -1249,7 +1249,7 @@ bool dal_adapter_service_get_i2c_info(
- 		return false;
- 	}
- 
--	return BP_RESULT_OK == dcb->funcs->get_i2c_info(dcb, id, i2c_info);
-+	return BP_RESULT_OK == dc_bios_get_i2c_info(dcb, id, i2c_info);
- }
- 
- /*
-@@ -1306,7 +1306,7 @@ struct irq *dal_adapter_service_obtain_hpd_irq(
- 	if (!get_hpd_info(as, id, &hpd_info))
- 		return NULL;
- 
--	bp_result = dcb->funcs->get_gpio_pin_info(dcb,
-+	bp_result = dc_bios_get_gpio_pin_info(dcb,
- 		hpd_info.hpd_int_gpio_uid, &pin_info);
- 
- 	if (bp_result != BP_RESULT_OK) {
-@@ -1343,7 +1343,7 @@ uint32_t dal_adapter_service_get_ss_info_num(
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	return dcb->funcs->get_ss_entry_number(dcb, signal);
-+	return dc_bios_get_ss_entry_number(dcb, signal);
- }
- 
- /*
-@@ -1359,8 +1359,8 @@ bool dal_adapter_service_get_ss_info(
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	enum bp_result bp_result = dcb->funcs->get_spread_spectrum_info(dcb,
--			signal, idx, info);
-+	enum bp_result bp_result = dc_bios_get_spread_spectrum_info(dcb,
-+								   signal, idx, info);
- 
- 	return BP_RESULT_OK == bp_result;
- }
-@@ -1571,12 +1571,11 @@ struct gpio *dal_adapter_service_obtain_stereo_gpio(
- 		/* Get GPIO record for this object.
- 		 * Stereo GPIO record should have exactly one entry
- 		 * where active state defines stereosync polarity */
--		if (1 != dcb->funcs->get_gpio_record(
--						dcb, id, &cntl_info,
--						1)) {
-+		if (1 != dc_bios_get_gpio_record(dcb, id, &cntl_info,
-+						 1)) {
- 			return NULL;
- 		} else if (BP_RESULT_OK
--				!= dcb->funcs->get_gpio_pin_info(
-+				!= dc_bios_get_gpio_pin_info(
- 						dcb, cntl_info.id,
- 						&pin_info)) {
- 			/*ASSERT_CRITICAL(false);*/
-@@ -1612,7 +1611,7 @@ bool dal_adapter_service_get_firmware_info(
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	return dcb->funcs->get_firmware_info(dcb, info) == BP_RESULT_OK;
-+	return dc_bios_get_firmware_info(dcb, info) == BP_RESULT_OK;
- }
- 
- /*
-@@ -1803,7 +1802,7 @@ bool dal_adapter_service_get_embedded_panel_info(
- 		/*TODO: add DALASSERT_MSG here*/
- 		return false;
- 
--	result = dcb->funcs->get_embedded_panel_info(dcb, info);
-+	result = dc_bios_get_embedded_panel_info(dcb, info);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1820,7 +1819,7 @@ bool dal_adapter_service_enum_embedded_panel_patch_mode(
- 		/*TODO: add DALASSERT_MSG here*/
- 		return false;
- 
--	result = dcb->funcs->enum_embedded_panel_patch_mode(dcb, index, mode);
-+	result = dc_bios_enum_embedded_panel_patch_mode(dcb, index, mode);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1832,7 +1831,7 @@ bool dal_adapter_service_get_faked_edid_len(
- 	enum bp_result result;
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	result = dcb->funcs->get_faked_edid_len(dcb, len);
-+	result = dc_bios_get_faked_edid_len(dcb, len);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -1845,7 +1844,7 @@ bool dal_adapter_service_get_faked_edid_buf(
- 	enum bp_result result;
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	result = dcb->funcs->get_faked_edid_buf(dcb, buf, len);
-+	result = dc_bios_get_faked_edid_buf(dcb, buf, len);
- 
- 	return result == BP_RESULT_OK;
- 
-@@ -1935,7 +1934,7 @@ bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as)
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	return dcb->funcs->is_accelerated_mode(dcb);
-+	return dc_bios_is_accelerated_mode(dcb);
- }
- 
- struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info(
-@@ -1981,7 +1980,7 @@ bool dal_adapter_service_is_lid_open(struct adapter_service *as)
- 		return is_lid_open;
- 
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
--	return dcb->funcs->is_lid_open(dcb);
-+	return dc_bios_is_lid_open(dcb);
- #else
- 	return false;
- #endif
-@@ -2068,7 +2067,7 @@ bool dal_adapter_service_get_encoder_cap_info(
- 	 * - dpHbr2Cap: indicates supported/not supported by HW Encoder
- 	 * - dpHbr2En : indicates DP spec compliant/not compliant
- 	 */
--	result = dcb->funcs->get_encoder_cap_info(dcb, id, &bp_cap_info);
-+	result = dc_bios_get_encoder_cap_info(dcb, id, &bp_cap_info);
- 
- 	/* Set dp_hbr2_validated flag (it's equal to Enable) */
- 	info->dp_hbr2_validated = bp_cap_info.DP_HBR2_EN;
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-index 0b1151e..1b6deb9 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
-@@ -66,7 +66,7 @@ bool wireless_data_init(struct wireless_data *data,
- 		 * Check if SBIOS sets remote display enable, exposed
- 		 * through VBIOS. This is only valid for APU, not dGPU
- 		 */
--		dcb->funcs->get_firmware_info(dcb, &info);
-+		dc_bios_get_firmware_info(dcb, &info);
- 
- 		if ((REMOTE_DISPLAY_ENABLE == info.remote_display_config) &&
- 				init_data->fusion) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index a43da0c..8bb5454 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -105,12 +105,8 @@ static bool bios_parser_construct(
- 	struct bp_init_data *init,
- 	struct adapter_service *as);
- 
--static uint8_t bios_parser_get_connectors_number(
--	struct dc_bios *dcb);
--
--static enum bp_result bios_parser_get_embedded_panel_info(
--	struct dc_bios *dcb,
--	struct embedded_panel_info *info);
-+enum bp_result dc_bios_get_embedded_panel_info(struct dc_bios *dcb,
-+					       struct embedded_panel_info *info);
- 
- /*****************************************************************************/
- 
-@@ -124,7 +120,7 @@ struct dc_bios *dal_bios_parser_create(
- 		return NULL;
- 
- 	if (bios_parser_construct(bp, init, as))
--		return &bp->base;
-+		return (struct dc_bios *)bp;
- 
- 	dm_free(bp);
- 	BREAK_TO_DEBUGGER();
-@@ -152,7 +148,7 @@ void dal_bios_parser_destroy(struct dc_bios **dcb)
- 	*dcb = NULL;
- }
- 
--static void bios_parser_power_down(struct dc_bios *dcb)
-+void dc_bios_power_down(struct dc_bios *dcb)
- {
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-@@ -161,7 +157,7 @@ static void bios_parser_power_down(struct dc_bios *dcb)
- #endif
- }
- 
--static void bios_parser_power_up(struct dc_bios *dcb)
-+void dc_bios_power_up(struct dc_bios *dcb)
- {
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-@@ -185,7 +181,7 @@ static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)
- 		return table->ucNumberOfObjects;
- }
- 
--static uint8_t bios_parser_get_encoders_number(struct dc_bios *dcb)
-+uint8_t dc_bios_get_encoders_number(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -193,7 +189,7 @@ static uint8_t bios_parser_get_encoders_number(struct dc_bios *dcb)
- 		le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset));
- }
- 
--static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
-+uint8_t dc_bios_get_connectors_number(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -201,7 +197,7 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
- 		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset));
- }
- 
--static uint32_t bios_parser_get_oem_ddc_lines_number(struct dc_bios *dcb)
-+uint32_t dc_bios_get_oem_ddc_lines_number(struct dc_bios *dcb)
- {
- 	uint32_t number = 0;
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-@@ -225,9 +221,8 @@ static uint32_t bios_parser_get_oem_ddc_lines_number(struct dc_bios *dcb)
- 	return number;
- }
- 
--static struct graphics_object_id bios_parser_get_encoder_id(
--	struct dc_bios *dcb,
--	uint32_t i)
-+struct graphics_object_id dc_bios_get_encoder_id(struct dc_bios *dcb,
-+						 uint32_t i)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct graphics_object_id object_id = dal_graphics_object_id_init(
-@@ -248,9 +243,8 @@ static struct graphics_object_id bios_parser_get_encoder_id(
- 	return object_id;
- }
- 
--static struct graphics_object_id bios_parser_get_connector_id(
--	struct dc_bios *dcb,
--	uint8_t i)
-+struct graphics_object_id dc_bios_get_connector_id(struct dc_bios *dcb,
-+						   uint8_t i)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct graphics_object_id object_id = dal_graphics_object_id_init(
-@@ -271,8 +265,8 @@ static struct graphics_object_id bios_parser_get_connector_id(
- 	return object_id;
- }
- 
--static uint32_t bios_parser_get_src_number(struct dc_bios *dcb,
--	struct graphics_object_id id)
-+uint32_t dc_bios_get_src_number(struct dc_bios *dcb,
-+				struct graphics_object_id id)
- {
- 	uint32_t offset;
- 	uint8_t *number;
-@@ -296,8 +290,8 @@ static uint32_t bios_parser_get_src_number(struct dc_bios *dcb,
- 	return *number;
- }
- 
--static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb,
--	struct graphics_object_id id)
-+uint32_t dc_bios_get_dst_number(struct dc_bios *dcb,
-+				struct graphics_object_id id)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object = get_bios_object(bp, id);
-@@ -305,9 +299,10 @@ static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb,
- 	return get_dst_number_from_object(bp, object);
- }
- 
--static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
--	struct graphics_object_id object_id, uint32_t index,
--	struct graphics_object_id *src_object_id)
-+enum bp_result dc_bios_get_src_obj(struct dc_bios *dcb,
-+				   struct graphics_object_id object_id,
-+				   uint32_t index,
-+				   struct graphics_object_id *src_object_id)
- {
- 	uint32_t number;
- 	uint16_t *id;
-@@ -334,9 +329,10 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
- 	return BP_RESULT_OK;
- }
- 
--static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
--	struct graphics_object_id object_id, uint32_t index,
--	struct graphics_object_id *dest_object_id)
-+enum bp_result dc_bios_get_dst_obj(struct dc_bios *dcb,
-+				   struct graphics_object_id object_id,
-+				   uint32_t index,
-+				   struct graphics_object_id *dest_object_id)
- {
- 	uint32_t number;
- 	uint16_t *id;
-@@ -358,9 +354,9 @@ static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
- 	return BP_RESULT_OK;
- }
- 
--static enum bp_result bios_parser_get_oem_ddc_info(struct dc_bios *dcb,
--	uint32_t index,
--	struct graphics_object_i2c_info *info)
-+enum bp_result dc_bios_get_oem_ddc_info(struct dc_bios *dcb,
-+					uint32_t index,
-+					struct graphics_object_i2c_info *info)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -395,9 +391,9 @@ static enum bp_result bios_parser_get_oem_ddc_info(struct dc_bios *dcb,
- 	return BP_RESULT_NORECORD;
- }
- 
--static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
--	struct graphics_object_id id,
--	struct graphics_object_i2c_info *info)
-+enum bp_result dc_bios_get_i2c_info(struct dc_bios *dcb,
-+				    struct graphics_object_id id,
-+				    struct graphics_object_i2c_info *info)
- {
- 	uint32_t offset;
- 	ATOM_OBJECT *object;
-@@ -501,10 +497,9 @@ static enum bp_result get_voltage_ddc_info_v3(uint8_t *i2c_line,
- 	return result;
- }
- 
--static enum bp_result bios_parser_get_thermal_ddc_info(
--	struct dc_bios *dcb,
--	uint32_t i2c_channel_id,
--	struct graphics_object_i2c_info *info)
-+enum bp_result dc_bios_get_thermal_ddc_info(struct dc_bios *dcb,
-+					    uint32_t i2c_channel_id,
-+					    struct graphics_object_i2c_info *info)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_I2C_ID_CONFIG_ACCESS *config;
-@@ -522,9 +517,9 @@ static enum bp_result bios_parser_get_thermal_ddc_info(
- 	return get_gpio_i2c_info(bp, &record, info);
- }
- 
--static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
--	uint32_t index,
--	struct graphics_object_i2c_info *info)
-+enum bp_result dc_bios_get_voltage_ddc_info(struct dc_bios *dcb,
-+					    uint32_t index,
-+					    struct graphics_object_i2c_info *info)
- {
- 	uint8_t i2c_line = 0;
- 	enum bp_result result = BP_RESULT_NORECORD;
-@@ -559,8 +554,8 @@ static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
- 	}
- 
- 	if (result == BP_RESULT_OK)
--		result = bios_parser_get_thermal_ddc_info(dcb,
--			i2c_line, info);
-+		result = dc_bios_get_thermal_ddc_info(dcb,
-+						      i2c_line, info);
- 
- 	return result;
- }
-@@ -629,9 +624,9 @@ enum bp_result bios_parser_get_ddc_info_for_i2c_line(struct bios_parser *bp,
- 	return BP_RESULT_NORECORD;
- }
- 
--static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb,
--	struct graphics_object_id id,
--	struct graphics_object_hpd_info *info)
-+enum bp_result dc_bios_get_hpd_info(struct dc_bios *dcb,
-+				    struct graphics_object_id id,
-+				    struct graphics_object_hpd_info *info)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object;
-@@ -656,11 +651,10 @@ static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb,
- 	return BP_RESULT_NORECORD;
- }
- 
--static uint32_t bios_parser_get_gpio_record(
--	struct dc_bios *dcb,
--	struct graphics_object_id id,
--	struct bp_gpio_cntl_info *gpio_record,
--	uint32_t record_size)
-+uint32_t dc_bios_get_gpio_record(struct dc_bios *dcb,
-+				 struct graphics_object_id id,
-+				 struct bp_gpio_cntl_info *gpio_record,
-+				 uint32_t record_size)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_COMMON_RECORD_HEADER *header = NULL;
-@@ -767,11 +761,10 @@ enum bp_result bios_parser_get_device_tag_record(
- 	return BP_RESULT_NORECORD;
- }
- 
--static enum bp_result bios_parser_get_device_tag(
--	struct dc_bios *dcb,
--	struct graphics_object_id connector_object_id,
--	uint32_t device_tag_index,
--	struct connector_device_tag_info *info)
-+enum bp_result dc_bios_get_device_tag(struct dc_bios *dcb,
-+				      struct graphics_object_id connector_object_id,
-+				      uint32_t device_tag_index,
-+				      struct connector_device_tag_info *info)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object;
-@@ -815,7 +808,7 @@ static enum bp_result get_firmware_info_v2_2(
- 	struct bios_parser *bp,
- 	struct firmware_info *info);
- 
--static enum bp_result bios_parser_get_firmware_info(
-+enum bp_result dc_bios_get_firmware_info(
- 	struct dc_bios *dcb,
- 	struct firmware_info *info)
- {
-@@ -1166,9 +1159,8 @@ static enum bp_result get_ss_info_v3_1(
- 	return BP_RESULT_NORECORD;
- }
- 
--static enum bp_result bios_parser_transmitter_control(
--	struct dc_bios *dcb,
--	struct bp_transmitter_control *cntl)
-+enum bp_result dc_bios_transmitter_control(struct dc_bios *dcb,
-+					   struct bp_transmitter_control *cntl)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1178,9 +1170,8 @@ static enum bp_result bios_parser_transmitter_control(
- 	return bp->cmd_tbl.transmitter_control(bp, cntl);
- }
- 
--static enum bp_result bios_parser_encoder_control(
--	struct dc_bios *dcb,
--	struct bp_encoder_control *cntl)
-+enum bp_result dc_bios_encoder_control(struct dc_bios *dcb,
-+					   struct bp_encoder_control *cntl)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1190,9 +1181,8 @@ static enum bp_result bios_parser_encoder_control(
- 	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
- }
- 
--static enum bp_result bios_parser_adjust_pixel_clock(
--	struct dc_bios *dcb,
--	struct bp_adjust_pixel_clock_parameters *bp_params)
-+enum bp_result dc_bios_adjust_pixel_clock(struct dc_bios *dcb,
-+					  struct bp_adjust_pixel_clock_parameters *bp_params)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1202,9 +1192,8 @@ static enum bp_result bios_parser_adjust_pixel_clock(
- 	return bp->cmd_tbl.adjust_display_pll(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_set_pixel_clock(
--	struct dc_bios *dcb,
--	struct bp_pixel_clock_parameters *bp_params)
-+enum bp_result dc_bios_set_pixel_clock(struct dc_bios *dcb,
-+				       struct bp_pixel_clock_parameters *bp_params)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1214,9 +1203,8 @@ static enum bp_result bios_parser_set_pixel_clock(
- 	return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_set_dce_clock(
--	struct dc_bios *dcb,
--	struct bp_set_dce_clock_parameters *bp_params)
-+enum bp_result dc_bios_set_dce_clock(struct dc_bios *dcb,
-+					 struct bp_set_dce_clock_parameters *bp_params)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1226,7 +1214,7 @@ static enum bp_result bios_parser_set_dce_clock(
- 	return bp->cmd_tbl.set_dce_clock(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_enable_spread_spectrum_on_ppll(
-+enum bp_result dc_bios_enable_spread_spectrum_on_ppll(
- 	struct dc_bios *dcb,
- 	struct bp_spread_spectrum_parameters *bp_params,
- 	bool enable)
-@@ -1241,7 +1229,7 @@ static enum bp_result bios_parser_enable_spread_spectrum_on_ppll(
- 
- }
- 
--static enum bp_result bios_parser_program_crtc_timing(
-+enum bp_result dc_bios_program_crtc_timing(
- 	struct dc_bios *dcb,
- 	struct bp_hw_crtc_timing_parameters *bp_params)
- {
-@@ -1253,7 +1241,7 @@ static enum bp_result bios_parser_program_crtc_timing(
- 	return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_program_display_engine_pll(
-+enum bp_result dc_bios_program_display_engine_pll(
- 	struct dc_bios *dcb,
- 	struct bp_pixel_clock_parameters *bp_params)
- {
-@@ -1266,11 +1254,10 @@ static enum bp_result bios_parser_program_display_engine_pll(
- 
- }
- 
--static enum signal_type bios_parser_dac_load_detect(
--	struct dc_bios *dcb,
--	struct graphics_object_id encoder,
--	struct graphics_object_id connector,
--	enum signal_type display_signal)
-+enum signal_type dc_bios_dac_load_detect(struct dc_bios *dcb,
-+					 struct graphics_object_id encoder,
-+					 struct graphics_object_id connector,
-+					 enum signal_type display_signal)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1281,7 +1268,7 @@ static enum signal_type bios_parser_dac_load_detect(
- 		display_signal);
- }
- 
--static enum bp_result bios_parser_get_divider_for_target_display_clock(
-+enum bp_result dc_bios_get_divider_for_target_display_clock(
- 	struct dc_bios *dcb,
- 	struct bp_display_clock_parameters *bp_params)
- {
-@@ -1293,7 +1280,7 @@ static enum bp_result bios_parser_get_divider_for_target_display_clock(
- 	return bp->cmd_tbl.compute_memore_engine_pll(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_enable_crtc(
-+enum bp_result dc_bios_enable_crtc(
- 	struct dc_bios *dcb,
- 	enum controller_id id,
- 	bool enable)
-@@ -1306,7 +1293,7 @@ static enum bp_result bios_parser_enable_crtc(
- 	return bp->cmd_tbl.enable_crtc(bp, id, enable);
- }
- 
--static enum bp_result bios_parser_blank_crtc(
-+enum bp_result dc_bios_blank_crtc(
- 	struct dc_bios *dcb,
- 	struct bp_blank_crtc_parameters *bp_params,
- 	bool blank)
-@@ -1319,7 +1306,7 @@ static enum bp_result bios_parser_blank_crtc(
- 	return bp->cmd_tbl.blank_crtc(bp, bp_params, blank);
- }
- 
--static enum bp_result bios_parser_crtc_source_select(
-+enum bp_result dc_bios_crtc_source_select(
- 	struct dc_bios *dcb,
- 	struct bp_crtc_source_select *bp_params)
- {
-@@ -1331,7 +1318,7 @@ static enum bp_result bios_parser_crtc_source_select(
- 	return bp->cmd_tbl.select_crtc_source(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_set_overscan(
-+enum bp_result dc_bios_set_overscan(
- 	struct dc_bios *dcb,
- 	struct bp_hw_crtc_overscan_parameters *bp_params)
- {
-@@ -1343,7 +1330,7 @@ static enum bp_result bios_parser_set_overscan(
- 	return bp->cmd_tbl.set_crtc_overscan(bp, bp_params);
- }
- 
--static enum bp_result bios_parser_enable_memory_requests(
-+enum bp_result dc_bios_enable_memory_requests(
- 	struct dc_bios *dcb,
- 	enum controller_id controller_id,
- 	bool enable)
-@@ -1356,7 +1343,7 @@ static enum bp_result bios_parser_enable_memory_requests(
- 	return bp->cmd_tbl.enable_crtc_mem_req(bp, controller_id, enable);
- }
- 
--static enum bp_result bios_parser_external_encoder_control(
-+enum bp_result dc_bios_external_encoder_control(
- 	struct dc_bios *dcb,
- 	struct bp_external_encoder_control *cntl)
- {
-@@ -1368,7 +1355,7 @@ static enum bp_result bios_parser_external_encoder_control(
- 	return bp->cmd_tbl.external_encoder_control(bp, cntl);
- }
- 
--static enum bp_result bios_parser_enable_disp_power_gating(
-+enum bp_result dc_bios_enable_disp_power_gating(
- 	struct dc_bios *dcb,
- 	enum controller_id controller_id,
- 	enum bp_pipe_control_action action)
-@@ -1382,9 +1369,8 @@ static enum bp_result bios_parser_enable_disp_power_gating(
- 		action);
- }
- 
--static bool bios_parser_is_device_id_supported(
--	struct dc_bios *dcb,
--	struct device_id id)
-+bool dc_bios_is_device_id_supported(struct dc_bios *dcb,
-+				    struct device_id id)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -1393,7 +1379,7 @@ static bool bios_parser_is_device_id_supported(
- 	return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0;
- }
- 
--static enum bp_result bios_parser_crt_control(
-+enum bp_result dc_bios_crt_control(
- 	struct dc_bios *dcb,
- 	enum engine_id engine_id,
- 	bool enable,
-@@ -1535,7 +1521,7 @@ static enum bp_result get_ss_info_from_tbl(
- 	uint32_t id,
- 	struct spread_spectrum_info *ss_info);
- /**
-- * bios_parser_get_spread_spectrum_info
-+ * dc_bios_get_spread_spectrum_info
-  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
-  * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
-  * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1,
-@@ -1547,7 +1533,7 @@ static enum bp_result get_ss_info_from_tbl(
-  * @param [out] ss_info, sprectrum information structure,
-  * @return Bios parser result code
-  */
--static enum bp_result bios_parser_get_spread_spectrum_info(
-+enum bp_result dc_bios_get_spread_spectrum_info(
- 	struct dc_bios *dcb,
- 	enum as_signal_type signal,
- 	uint32_t index,
-@@ -1745,7 +1731,7 @@ static enum bp_result get_ss_info_from_ss_info_table(
- 	{
- 		struct embedded_panel_info panel_info;
- 
--		if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info)
-+		if (dc_bios_get_embedded_panel_info((struct dc_bios *)bp, &panel_info)
- 				== BP_RESULT_OK)
- 			id_local = panel_info.ss_id;
- 		break;
-@@ -1801,7 +1787,7 @@ static enum bp_result get_embedded_panel_info_v1_3(
- 	struct bios_parser *bp,
- 	struct embedded_panel_info *info);
- 
--static enum bp_result bios_parser_get_embedded_panel_info(
-+enum bp_result dc_bios_get_embedded_panel_info(
- 	struct dc_bios *dcb,
- 	struct embedded_panel_info *info)
- {
-@@ -2080,7 +2066,7 @@ static enum bp_result get_embedded_panel_info_v1_3(
- }
- 
- /**
-- * bios_parser_get_encoder_cap_info
-+ * dc_bios_get_encoder_cap_info
-  *
-  * @brief
-  *  Get encoder capability information of input object id
-@@ -2091,10 +2077,9 @@ static enum bp_result get_embedded_panel_info_v1_3(
-  * @return Bios parser result code
-  *
-  */
--static enum bp_result bios_parser_get_encoder_cap_info(
--	struct dc_bios *dcb,
--	struct graphics_object_id object_id,
--	struct bp_encoder_cap_info *info)
-+enum bp_result dc_bios_get_encoder_cap_info(struct dc_bios *dcb,
-+					    struct graphics_object_id object_id,
-+					    struct bp_encoder_cap_info *info)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_OBJECT *object;
-@@ -2168,7 +2153,7 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- }
- 
- /**
-- * bios_parser_get_din_connector_info
-+ * dc_bios_get_din_connector_info
-  * @brief
-  *   Get GPIO record for the DIN connector, this GPIO tells whether there is a
-  *    CV dumb dongle
-@@ -2179,10 +2164,9 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
-  * @param info             - GPIO record infor
-  * @return Bios parser result code
-  */
--static enum bp_result bios_parser_get_din_connector_info(
--	struct dc_bios *dcb,
--	struct graphics_object_id id,
--	struct din_connector_info *info)
-+enum bp_result dc_bios_get_din_connector_info(struct dc_bios *dcb,
-+					      struct graphics_object_id id,
-+					      struct din_connector_info *info)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_COMMON_RECORD_HEADER *header;
-@@ -2265,9 +2249,8 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
-  * @param[in] signal, ASSignalType to be converted to SSid
-  * @return number of SS Entry that match the signal
-  */
--static uint32_t bios_parser_get_ss_entry_number(
--	struct dc_bios *dcb,
--	enum as_signal_type signal)
-+uint32_t dc_bios_get_ss_entry_number(struct dc_bios *dcb,
-+				     enum as_signal_type signal)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	uint32_t ss_id = 0;
-@@ -2352,7 +2335,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
- 	case ASIC_INTERNAL_SS_ON_LVDS: {
- 		struct embedded_panel_info panel_info;
- 
--		if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info)
-+		if (dc_bios_get_embedded_panel_info((struct dc_bios *)bp, &panel_info)
- 				== BP_RESULT_OK)
- 			id_local = panel_info.ss_id;
- 		break;
-@@ -2514,9 +2497,8 @@ static ATOM_FAKE_EDID_PATCH_RECORD *get_faked_edid_record(
- 	return (ATOM_FAKE_EDID_PATCH_RECORD *)record;
- }
- 
--static enum bp_result bios_parser_get_faked_edid_len(
--	struct dc_bios *dcb,
--	uint32_t *len)
-+enum bp_result dc_bios_get_faked_edid_len(struct dc_bios *dcb,
-+					  uint32_t *len)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
-@@ -2529,10 +2511,9 @@ static enum bp_result bios_parser_get_faked_edid_len(
- 	return BP_RESULT_OK;
- }
- 
--static enum bp_result bios_parser_get_faked_edid_buf(
--	struct dc_bios *dcb,
--	uint8_t *buff,
--	uint32_t len)
-+enum bp_result dc_bios_get_faked_edid_buf(struct dc_bios *dcb,
-+					  uint8_t *buff,
-+					  uint32_t len)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	ATOM_FAKE_EDID_PATCH_RECORD *edid_record = get_faked_edid_record(bp);
-@@ -2564,7 +2545,7 @@ static enum bp_result bios_parser_get_faked_edid_buf(
-  *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA
-  *  offset/mask
-  */
--static enum bp_result bios_parser_get_gpio_pin_info(
-+enum bp_result dc_bios_get_gpio_pin_info(
- 	struct dc_bios *dcb,
- 	uint32_t gpio_id,
- 	struct gpio_pin_info *info)
-@@ -2621,10 +2602,9 @@ static enum bp_result bios_parser_get_gpio_pin_info(
-  * @param info, embedded panel patch mode structure
-  * @return Bios parser result code
-  */
--static enum bp_result bios_parser_enum_embedded_panel_patch_mode(
--	struct dc_bios *dcb,
--	uint32_t index,
--	struct embedded_panel_patch_mode *mode)
-+enum bp_result dc_bios_enum_embedded_panel_patch_mode(struct dc_bios *dcb,
-+						      uint32_t index,
-+						      struct embedded_panel_patch_mode *mode)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	uint32_t record_size;
-@@ -4134,15 +4114,14 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 	}
- }
- 
--static void bios_parser_post_init(struct dc_bios *dcb)
-+void dc_bios_post_init(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
- 	process_ext_display_connection_info(bp);
- }
- 
--static bool bios_parser_is_accelerated_mode(
--	struct dc_bios *dcb)
-+bool dc_bios_is_accelerated_mode(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -4169,7 +4148,7 @@ static bool bios_parser_is_accelerated_mode(
-  *  bool - connection state
-  *  const ConnectorDeviceTagInfo* - pointer to device type and enum ID
-  */
--static void bios_parser_set_scratch_connected(
-+void dc_bios_set_scratch_connected(
- 	struct dc_bios *dcb,
- 	struct graphics_object_id connector_id,
- 	bool connected,
-@@ -4198,7 +4177,7 @@ static void bios_parser_set_scratch_connected(
-  * @param
-  *  bool - to set or reset state
-  */
--static void bios_parser_set_scratch_critical_state(
-+void dc_bios_set_scratch_critical_state(
- 	struct dc_bios *dcb,
- 	bool state)
- {
-@@ -4215,8 +4194,7 @@ static void bios_parser_set_scratch_critical_state(
- #endif
- }
- 
--static void bios_parser_set_scratch_acc_mode_change(
--	struct dc_bios *dcb)
-+void dc_bios_set_scratch_acc_mode_change(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -4243,11 +4221,10 @@ static void bios_parser_set_scratch_acc_mode_change(
-  *  const struct connector_device_tag_info * - pointer to display type and
-  *  enum Id
-  */
--static void bios_parser_prepare_scratch_active_and_requested(
--	struct dc_bios *dcb,
--	enum controller_id controller_id,
--	enum signal_type signal,
--	const struct connector_device_tag_info *device_tag)
-+void dc_bios_prepare_scratch_active_and_requested(struct dc_bios *dcb,
-+						  enum controller_id controller_id,
-+						  enum signal_type signal,
-+						  const struct connector_device_tag_info *device_tag)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -4266,8 +4243,7 @@ static void bios_parser_prepare_scratch_active_and_requested(
- #endif
- }
- 
--static void bios_parser_set_scratch_active_and_requested(
--	struct dc_bios *dcb)
-+void dc_bios_set_scratch_active_and_requested(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
-@@ -4662,8 +4638,7 @@ static enum bp_result construct_integrated_info(
- 	return result;
- }
- 
--static struct integrated_info *bios_parser_create_integrated_info(
--	struct dc_bios *dcb)
-+struct integrated_info *dc_bios_create_integrated_info(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 	struct integrated_info *info = NULL;
-@@ -4683,9 +4658,8 @@ static struct integrated_info *bios_parser_create_integrated_info(
- 	return NULL;
- }
- 
--static void bios_parser_destroy_integrated_info(
--	struct dc_bios *dcb,
--	struct integrated_info **info)
-+void dc_bios_destroy_integrated_info(struct dc_bios *dcb,
-+				     struct integrated_info **info)
- {
- 	if (info == NULL) {
- 		ASSERT_CRITICAL(0);
-@@ -4699,13 +4673,15 @@ static void bios_parser_destroy_integrated_info(
- }
- 
- /******************************************************************************
-+
-  * Stub-functions */
--static bool is_lid_open(
-+bool dc_bios_is_lid_open(
- 	struct dc_bios *bios)
- {
- 	BREAK_TO_DEBUGGER();
- 	return false;
- }
-+#if 0
- 
- static bool is_lid_status_changed(
- 	struct dc_bios *bios)
-@@ -4735,38 +4711,37 @@ static enum lcd_scale get_scratch_lcd_scale(
- 	return LCD_SCALE_NONE;
- }
- 
--static void get_bios_event_info(
-+void dc_bios_get_bios_event_info(
- 	struct dc_bios *bios,
- 	struct bios_event_info *info)
- {
- 	BREAK_TO_DEBUGGER();
- }
- 
--static void update_requested_backlight_level(
-+void dc_bios_update_requested_backlight_level(
- 	struct dc_bios *bios,
- 	uint32_t backlight_8bit)
- {
- 	BREAK_TO_DEBUGGER();
- }
- 
--static uint32_t get_requested_backlight_level(
-+uint32_t dc_bios_get_requested_backlight_level(
- 	struct dc_bios *bios)
- {
- 	BREAK_TO_DEBUGGER();
- 	return 0;
- }
- 
--static void take_backlight_control(
-+void dc_bios_take_backlight_control(
- 	struct dc_bios *bios,
- 	bool cntl)
- {
- 	BREAK_TO_DEBUGGER();
- }
- 
--static bool is_active_display(
--	struct dc_bios *bios,
--	enum signal_type signal,
--	const struct connector_device_tag_info *device_tag)
-+bool dc_bios_is_active_display(struct dc_bios *bios,
-+			       enum signal_type signal,
-+			       const struct connector_device_tag_info *device_tag)
- {
- 	BREAK_TO_DEBUGGER();
- 	return false;
-@@ -4785,151 +4760,7 @@ static uint32_t get_embedded_display_refresh_rate(
- 	BREAK_TO_DEBUGGER();
- 	return 0;
- }
--
--/******************************************************************************/
--
--static const struct dc_vbios_funcs vbios_funcs = {
--	.get_connectors_number = bios_parser_get_connectors_number,
--
--	.power_down = bios_parser_power_down,
--
--	.power_up = bios_parser_power_up,
--
--	.get_encoders_number = bios_parser_get_encoders_number,
--
--	.get_oem_ddc_lines_number = bios_parser_get_oem_ddc_lines_number,
--
--	.get_encoder_id = bios_parser_get_encoder_id,
--
--	.get_connector_id = bios_parser_get_connector_id,
--
--	.get_src_number = bios_parser_get_src_number,
--
--	.get_dst_number = bios_parser_get_dst_number,
--
--	.get_gpio_record = bios_parser_get_gpio_record,
--
--	.get_src_obj = bios_parser_get_src_obj,
--
--	.get_dst_obj = bios_parser_get_dst_obj,
--
--	.get_i2c_info = bios_parser_get_i2c_info,
--
--	.get_oem_ddc_info = bios_parser_get_oem_ddc_info,
--
--	.get_voltage_ddc_info = bios_parser_get_voltage_ddc_info,
--
--	.get_thermal_ddc_info = bios_parser_get_thermal_ddc_info,
--
--	.get_hpd_info = bios_parser_get_hpd_info,
--
--	.get_device_tag = bios_parser_get_device_tag,
--
--	.get_firmware_info = bios_parser_get_firmware_info,
--
--	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
--
--	.get_ss_entry_number = bios_parser_get_ss_entry_number,
--
--	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
--
--	.enum_embedded_panel_patch_mode = bios_parser_enum_embedded_panel_patch_mode,
--
--	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
--
--	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
--
--	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
--
--	.get_faked_edid_len = bios_parser_get_faked_edid_len,
--
--	.get_faked_edid_buf = bios_parser_get_faked_edid_buf,
--
--	.get_encoder_cap_info = bios_parser_get_encoder_cap_info,
--
--	.get_din_connector_info = bios_parser_get_din_connector_info,
--
--	.is_lid_open = is_lid_open,
--
--	.is_lid_status_changed = is_lid_status_changed,
--
--	.is_display_config_changed = is_display_config_changed,
--
--	.is_accelerated_mode = bios_parser_is_accelerated_mode,
--
--	.set_scratch_lcd_scale = set_scratch_lcd_scale,
--
--	.get_scratch_lcd_scale = get_scratch_lcd_scale,
--
--	.get_bios_event_info = get_bios_event_info,
--
--	.update_requested_backlight_level = update_requested_backlight_level,
--
--	.get_requested_backlight_level = get_requested_backlight_level,
--
--	.take_backlight_control = take_backlight_control,
--
--	.is_active_display = is_active_display,
--
--	.get_embedded_display_controller_id = get_embedded_display_controller_id,
--
--	.get_embedded_display_refresh_rate = get_embedded_display_refresh_rate,
--
--	.set_scratch_connected = bios_parser_set_scratch_connected,
--
--	.prepare_scratch_active_and_requested = bios_parser_prepare_scratch_active_and_requested,
--
--	.set_scratch_active_and_requested = bios_parser_set_scratch_active_and_requested,
--
--	.set_scratch_critical_state = bios_parser_set_scratch_critical_state,
--
--	.set_scratch_acc_mode_change = bios_parser_set_scratch_acc_mode_change,
--
--	.is_device_id_supported = bios_parser_is_device_id_supported,
--
--	/* COMMANDS */
--	.encoder_control = bios_parser_encoder_control,
--
--	.transmitter_control = bios_parser_transmitter_control,
--
--	.crt_control = bios_parser_crt_control,
--
--	.enable_crtc = bios_parser_enable_crtc,
--
--	.adjust_pixel_clock = bios_parser_adjust_pixel_clock,
--
--	.set_pixel_clock = bios_parser_set_pixel_clock,
--
--	.set_dce_clock = bios_parser_set_dce_clock,
--
--	.enable_spread_spectrum_on_ppll = bios_parser_enable_spread_spectrum_on_ppll,
--
--	.program_crtc_timing = bios_parser_program_crtc_timing,
--
--	.blank_crtc = bios_parser_blank_crtc,
--
--	.set_overscan = bios_parser_set_overscan,
--
--	.crtc_source_select = bios_parser_crtc_source_select,
--
--	.program_display_engine_pll = bios_parser_program_display_engine_pll,
--
--	.get_divider_for_target_display_clock = bios_parser_get_divider_for_target_display_clock,
--
--	.dac_load_detect = bios_parser_dac_load_detect,
--
--	.enable_memory_requests = bios_parser_enable_memory_requests,
--
--	.external_encoder_control = bios_parser_external_encoder_control,
--
--	.enable_disp_power_gating = bios_parser_enable_disp_power_gating,
--
--	.post_init = bios_parser_post_init,
--
--	.create_integrated_info = bios_parser_create_integrated_info,
--
--	.destroy_integrated_info = bios_parser_destroy_integrated_info,
--};
-+#endif
- 
- static bool bios_parser_construct(
- 	struct bios_parser *bp,
-@@ -4950,8 +4781,6 @@ static bool bios_parser_construct(
- 	if (!init->bios)
- 		return false;
- 
--	bp->base.funcs = &vbios_funcs;
--
- 	dce_version = dal_adapter_service_get_dce_version(as);
- 	bp->ctx = init->ctx;
- 	bp->as = as;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-index f8fa108..2133a59 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-@@ -51,7 +51,6 @@ enum spread_spectrum_id {
- };
- 
- struct bios_parser {
--	struct dc_bios base;
- 	struct dc_context *ctx;
- 	struct adapter_service *as;
- 
-@@ -79,6 +78,6 @@ struct bios_parser {
- 
- /* Bios Parser from DC Bios */
- #define BP_FROM_DCB(dc_bios) \
--	container_of(dc_bios, struct bios_parser, base)
-+	(struct bios_parser *)(dc_bios)
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
-index 1b0f816..46cc3aa 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
-@@ -59,57 +59,6 @@ static void set_scratch_acc_mode_change(
- 	dm_write_reg(ctx, addr, value);
- }
- 
--/*
-- * set_scratch_active_and_requested
-- *
-- * @brief
-- * Set VBIOS scratch pad registers about active and requested displays
-- *
-- * @param
-- * struct dc_context *ctx - [in] DAL context for register accessing
-- * struct vbios_helper_data *d - [in] values to write
-- */
--static void set_scratch_active_and_requested(
--	struct dc_context *ctx,
--	struct vbios_helper_data *d)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--
--	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
--	addr = mmBIOS_SCRATCH_3;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
--	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
--
--	dm_write_reg(ctx, addr, value);
--
--	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
--	addr = mmBIOS_SCRATCH_6;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S6_ACC_REQ_MASK;
--	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
--
--	dm_write_reg(ctx, addr, value);
--
--	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
--	addr = mmBIOS_SCRATCH_5;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
--	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
--
--	dm_write_reg(ctx, addr, value);
--
--	d->active = 0;
--	d->requested = 0;
--}
--
- /**
-  * get LCD Scale Mode from VBIOS scratch register
-  */
-@@ -311,116 +260,6 @@ static enum signal_type detect_sink(
- 	return SIGNAL_TYPE_NONE;
- }
- 
--/**
-- * set_scratch_connected
-- *
-- * @brief
-- *    update BIOS_SCRATCH_0 register about connected displays
-- *
-- * @param
-- * bool - update scratch register or just prepare info to be updated
-- * bool - connection state
-- * const struct connector_device_tag_info * - pointer to device type and enum ID
-- */
--static void set_scratch_connected(
--	struct dc_context *ctx,
--	struct graphics_object_id id,
--	bool connected,
--	const struct connector_device_tag_info *device_tag)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--	uint32_t update = 0;
--
--	switch (device_tag->dev_id.device_type) {
--	case DEVICE_TYPE_LCD:
--		/* For LCD VBIOS will update LCD Panel connected bit always and
--		 * Lid state bit based on SBIOS info do not do anything here
--		 * for LCD
--		 */
--		break;
--	case DEVICE_TYPE_CRT:
--		/* CRT is not supported in DCE11 */
--		break;
--	case DEVICE_TYPE_DFP:
--		switch (device_tag->dev_id.enum_id) {
--		case 1:
--			update |= ATOM_S0_DFP1;
--			break;
--		case 2:
--			update |= ATOM_S0_DFP2;
--			break;
--		case 3:
--			update |= ATOM_S0_DFP3;
--			break;
--		case 4:
--			update |= ATOM_S0_DFP4;
--			break;
--		case 5:
--			update |= ATOM_S0_DFP5;
--			break;
--		case 6:
--			update |= ATOM_S0_DFP6;
--			break;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_CV:
--		/* DCE 8.0 does not support CV, so don't do anything */
--		break;
--
--	case DEVICE_TYPE_TV:
--		/* For TV VBIOS will update S-Video or
--		 * Composite scratch bits on DAL_LoadDetect
--		 * when called by driver, do not do anything
--		 * here for TV
--		 */
--		break;
--
--	default:
--		break;
--
--	}
--
--	/* update scratch register */
--	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
--
--	value = dm_read_reg(ctx, addr);
--
--	if (connected)
--		value |= update;
--	else
--		value &= ~update;
--
--	dm_write_reg(ctx, addr, value);
--}
--
--static void set_scratch_critical_state(
--	struct dc_context *ctx,
--	bool state)
--{
--	uint32_t addr = mmBIOS_SCRATCH_6;
--	uint32_t value = dm_read_reg(ctx, addr);
--
--	if (state)
--		value |= ATOM_S6_CRITICAL_STATE;
--	else
--		value &= ~ATOM_S6_CRITICAL_STATE;
--
--	dm_write_reg(ctx, addr, value);
--}
--
--static void set_scratch_lcd_scale(
--	struct dc_context *ctx,
--	enum lcd_scale lcd_scale_request)
--{
--	DAL_LOGGER_NOT_IMPL(
--		LOG_MINOR_COMPONENT_BIOS,
--		"Bios Parser:%s\n",
--		__func__);
--}
--
- static bool is_lid_open(struct dc_context *ctx)
- {
- 	uint32_t bios_scratch6;
-@@ -440,27 +279,12 @@ static bool is_lid_open(struct dc_context *ctx)
- /* function table */
- static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.detect_sink = detect_sink,
--	.fmt_bit_depth_control = NULL,
--	.fmt_control = NULL,
--	.get_bios_event_info = NULL,
--	.get_embedded_display_controller_id = NULL,
--	.get_embedded_display_refresh_rate = NULL,
--	.get_requested_backlight_level = NULL,
- 	.get_scratch_lcd_scale = get_scratch_lcd_scale,
- 	.is_accelerated_mode = is_accelerated_mode,
--	.is_active_display = NULL,
--	.is_display_config_changed = NULL,
- 	.is_lid_open = is_lid_open,
--	.is_lid_status_changed = NULL,
- 	.prepare_scratch_active_and_requested =
- 			prepare_scratch_active_and_requested,
--	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
--	.set_scratch_active_and_requested = set_scratch_active_and_requested,
--	.set_scratch_connected = set_scratch_connected,
--	.set_scratch_critical_state = set_scratch_critical_state,
--	.set_scratch_lcd_scale = set_scratch_lcd_scale,
--	.take_backlight_control = NULL,
--	.update_requested_backlight_level = NULL,
-+	.set_scratch_acc_mode_change = set_scratch_acc_mode_change
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index d49ab5e..a5f33d4 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -83,7 +83,7 @@ static bool create_links(
- 
- 	dcb = dc->ctx->dc_bios;
- 
--	connectors_num = dcb->funcs->get_connectors_number(dcb);
-+	connectors_num = dc_bios_get_connectors_number(dcb);
- 
- 	if (connectors_num > ENUM_ID_COUNT) {
- 		dm_error(
-@@ -759,7 +759,7 @@ bool dc_commit_targets(
- 
- 	pplib_apply_safe_state(core_dc);
- 
--	if (!dcb->funcs->is_accelerated_mode(dcb)) {
-+	if (!dc_bios_is_accelerated_mode(dcb)) {
- 		core_dc->hwss.enable_accelerated_mode(core_dc);
- 	}
- 
-@@ -837,7 +837,7 @@ bool dc_commit_surfaces_to_target(
- 
- 	target_status = &context->target_status[i];
- 
--	if (!dcb->funcs->is_accelerated_mode(dcb)
-+	if (!dc_bios_is_accelerated_mode(dcb)
- 			|| i == context->target_count) {
- 		BREAK_TO_DEBUGGER();
- 		goto unexpected_fail;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index 7def8dd..f17702d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -38,239 +38,183 @@
- 
- #include "include/bios_parser_types.h"
- 
--struct dc_vbios_funcs {
--	uint8_t (*get_connectors_number)(struct dc_bios *bios);
--
--	void (*power_down)(struct dc_bios *bios);
--	void (*power_up)(struct dc_bios *bios);
--
--	uint8_t (*get_encoders_number)(struct dc_bios *bios);
--	uint32_t (*get_oem_ddc_lines_number)(struct dc_bios *bios);
--
--	struct graphics_object_id (*get_encoder_id)(
--		struct dc_bios *bios,
--		uint32_t i);
--	struct graphics_object_id (*get_connector_id)(
--		struct dc_bios *bios,
--		uint8_t connector_index);
--	uint32_t (*get_src_number)(
--		struct dc_bios *bios,
--		struct graphics_object_id id);
--	uint32_t (*get_dst_number)(
--		struct dc_bios *bios,
--		struct graphics_object_id id);
--
--	uint32_t (*get_gpio_record)(
--		struct dc_bios *dcb,
--		struct graphics_object_id id,
--		struct bp_gpio_cntl_info *gpio_record,
--		uint32_t record_size);
--
--	enum bp_result (*get_src_obj)(
--		struct dc_bios *bios,
--		struct graphics_object_id object_id, uint32_t index,
--		struct graphics_object_id *src_object_id);
--	enum bp_result (*get_dst_obj)(
--		struct dc_bios *bios,
--		struct graphics_object_id object_id, uint32_t index,
--		struct graphics_object_id *dest_object_id);
--	enum bp_result (*get_oem_ddc_info)(
--		struct dc_bios *bios,
--		uint32_t index,
--		struct graphics_object_i2c_info *info);
--
--	enum bp_result (*get_i2c_info)(
--		struct dc_bios *dcb,
--		struct graphics_object_id id,
--		struct graphics_object_i2c_info *info);
--
--	enum bp_result (*get_voltage_ddc_info)(
--		struct dc_bios *bios,
--		uint32_t index,
--		struct graphics_object_i2c_info *info);
--	enum bp_result (*get_thermal_ddc_info)(
--		struct dc_bios *bios,
--		uint32_t i2c_channel_id,
--		struct graphics_object_i2c_info *info);
--	enum bp_result (*get_hpd_info)(
--		struct dc_bios *bios,
--		struct graphics_object_id id,
--		struct graphics_object_hpd_info *info);
--	enum bp_result (*get_device_tag)(
--		struct dc_bios *bios,
--		struct graphics_object_id connector_object_id,
--		uint32_t device_tag_index,
--		struct connector_device_tag_info *info);
--	enum bp_result (*get_firmware_info)(
--		struct dc_bios *bios,
--		struct firmware_info *info);
--	enum bp_result (*get_spread_spectrum_info)(
--		struct dc_bios *bios,
--		enum as_signal_type signal,
--		uint32_t index,
--		struct spread_spectrum_info *ss_info);
--	uint32_t (*get_ss_entry_number)(
--		struct dc_bios *bios,
--		enum as_signal_type signal);
--	enum bp_result (*get_embedded_panel_info)(
--		struct dc_bios *bios,
--		struct embedded_panel_info *info);
--	enum bp_result (*enum_embedded_panel_patch_mode)(
--		struct dc_bios *bios,
--		uint32_t index,
--		struct embedded_panel_patch_mode *mode);
--	enum bp_result (*get_gpio_pin_info)(
--		struct dc_bios *bios,
--		uint32_t gpio_id,
--		struct gpio_pin_info *info);
--	enum bp_result (*get_faked_edid_len)(
--		struct dc_bios *bios,
--		uint32_t *len);
--	enum bp_result (*get_faked_edid_buf)(
--		struct dc_bios *bios,
--		uint8_t *buff,
--		uint32_t len);
--	enum bp_result (*get_encoder_cap_info)(
--		struct dc_bios *bios,
--		struct graphics_object_id object_id,
--		struct bp_encoder_cap_info *info);
--	enum bp_result (*get_din_connector_info)(
--		struct dc_bios *bios,
--		struct graphics_object_id id,
--		struct din_connector_info *info);
--
--	bool (*is_lid_open)(
--		struct dc_bios *bios);
--	bool (*is_lid_status_changed)(
--		struct dc_bios *bios);
--	bool (*is_display_config_changed)(
--		struct dc_bios *bios);
--	bool (*is_accelerated_mode)(
--		struct dc_bios *bios);
--	void (*set_scratch_lcd_scale)(
--		struct dc_bios *bios,
--		enum lcd_scale scale);
--	enum lcd_scale  (*get_scratch_lcd_scale)(
--		struct dc_bios *bios);
--	void (*get_bios_event_info)(
--		struct dc_bios *bios,
--		struct bios_event_info *info);
--	void (*update_requested_backlight_level)(
--		struct dc_bios *bios,
--		uint32_t backlight_8bit);
--	uint32_t (*get_requested_backlight_level)(
--		struct dc_bios *bios);
--	void (*take_backlight_control)(
--		struct dc_bios *bios,
--		bool cntl);
--	bool (*is_active_display)(
--		struct dc_bios *bios,
--		enum signal_type signal,
--		const struct connector_device_tag_info *device_tag);
--	enum controller_id (*get_embedded_display_controller_id)(
--		struct dc_bios *bios);
--	uint32_t (*get_embedded_display_refresh_rate)(
--		struct dc_bios *bios);
--	void (*set_scratch_connected)(
--		struct dc_bios *bios,
--		struct graphics_object_id connector_id,
--		bool connected,
--		const struct connector_device_tag_info *device_tag);
--	void (*prepare_scratch_active_and_requested)(
--		struct dc_bios *bios,
--		enum controller_id controller_id,
--		enum signal_type signal,
--		const struct connector_device_tag_info *device_tag);
--	void (*set_scratch_active_and_requested)(
--		struct dc_bios *bios);
--	void (*set_scratch_critical_state)(
--		struct dc_bios *bios,
--		bool state);
--	void (*set_scratch_acc_mode_change)(
--		struct dc_bios *bios);
--
--	bool (*is_device_id_supported)(
--		struct dc_bios *bios,
--		struct device_id id);
--
--	/* COMMANDS */
--
--	enum bp_result (*encoder_control)(
--		struct dc_bios *bios,
--		struct bp_encoder_control *cntl);
--	enum bp_result (*transmitter_control)(
--		struct dc_bios *bios,
--		struct bp_transmitter_control *cntl);
--	enum bp_result (*crt_control)(
--		struct dc_bios *bios,
--		enum engine_id engine_id,
--		bool enable,
--		uint32_t pixel_clock);
--	enum bp_result (*enable_crtc)(
--		struct dc_bios *bios,
--		enum controller_id id,
--		bool enable);
--	enum bp_result (*adjust_pixel_clock)(
--		struct dc_bios *bios,
--		struct bp_adjust_pixel_clock_parameters *bp_params);
--	enum bp_result (*set_pixel_clock)(
--		struct dc_bios *bios,
--		struct bp_pixel_clock_parameters *bp_params);
--	enum bp_result (*set_dce_clock)(
--		struct dc_bios *bios,
--		struct bp_set_dce_clock_parameters *bp_params);
--	enum bp_result (*enable_spread_spectrum_on_ppll)(
--		struct dc_bios *bios,
--		struct bp_spread_spectrum_parameters *bp_params,
--		bool enable);
--	enum bp_result (*program_crtc_timing)(
--		struct dc_bios *bios,
--		struct bp_hw_crtc_timing_parameters *bp_params);
--	enum bp_result (*blank_crtc)(
--		struct dc_bios *bios,
--		struct bp_blank_crtc_parameters *bp_params,
--		bool blank);
--	enum bp_result (*set_overscan)(
--		struct dc_bios *bios,
--		struct bp_hw_crtc_overscan_parameters *bp_params);
--	enum bp_result (*crtc_source_select)(
--		struct dc_bios *bios,
--		struct bp_crtc_source_select *bp_params);
--	enum bp_result (*program_display_engine_pll)(
--		struct dc_bios *bios,
--		struct bp_pixel_clock_parameters *bp_params);
--	enum bp_result (*get_divider_for_target_display_clock)(
--		struct dc_bios *bios,
--		struct bp_display_clock_parameters *bp_params);
--	enum signal_type (*dac_load_detect)(
--		struct dc_bios *bios,
--		struct graphics_object_id encoder,
--		struct graphics_object_id connector,
--		enum signal_type display_signal);
--	enum bp_result (*enable_memory_requests)(
--		struct dc_bios *bios,
--		enum controller_id controller_id,
--		bool enable);
--	enum bp_result (*external_encoder_control)(
--		struct dc_bios *bios,
--		struct bp_external_encoder_control *cntl);
--	enum bp_result (*enable_disp_power_gating)(
--		struct dc_bios *bios,
--		enum controller_id controller_id,
--		enum bp_pipe_control_action action);
--
--	void (*post_init)(struct dc_bios *bios);
--
--	struct integrated_info *(*create_integrated_info)(
--		struct dc_bios *bios);
--
--	void (*destroy_integrated_info)(
--		struct dc_bios *dcb,
--		struct integrated_info **info);
--};
--
--struct dc_bios {
--	const struct dc_vbios_funcs *funcs;
--};
-+uint8_t dc_bios_get_connectors_number(struct dc_bios *bios);
-+
-+void dc_bios_power_down(struct dc_bios *bios);
-+void dc_bios_power_up(struct dc_bios *bios);
-+
-+uint8_t dc_bios_get_encoders_number(struct dc_bios *bios);
-+uint32_t dc_bios_get_oem_ddc_lines_number(struct dc_bios *bios);
-+
-+struct graphics_object_id dc_bios_get_encoder_id(struct dc_bios *bios,
-+						 uint32_t i);
-+struct graphics_object_id dc_bios_get_connector_id(struct dc_bios *bios,
-+						   uint8_t connector_index);
-+uint32_t dc_bios_get_src_number(struct dc_bios *bios,
-+				struct graphics_object_id id);
-+uint32_t dc_bios_get_dst_number(struct dc_bios *bios,
-+				struct graphics_object_id id);
-+
-+uint32_t dc_bios_get_gpio_record(struct dc_bios *dcb,
-+				 struct graphics_object_id id,
-+				 struct bp_gpio_cntl_info *gpio_record,
-+				 uint32_t record_size);
-+enum bp_result dc_bios_get_src_obj(struct dc_bios *bios,
-+				    struct graphics_object_id object_id,
-+				    uint32_t index,
-+				    struct graphics_object_id *src_object_id);
-+enum bp_result dc_bios_get_dst_obj(struct dc_bios *bios,
-+				   struct graphics_object_id object_id,
-+				   uint32_t index,
-+				   struct graphics_object_id *dest_object_id);
-+enum bp_result dc_bios_get_oem_ddc_info(struct dc_bios *bios,
-+					uint32_t index,
-+					struct graphics_object_i2c_info *info);
-+enum bp_result dc_bios_get_i2c_info(struct dc_bios *dcb,
-+				    struct graphics_object_id id,
-+				    struct graphics_object_i2c_info *info);
-+
-+enum bp_result dc_bios_get_voltage_ddc_info(struct dc_bios *bios,
-+					    uint32_t index,
-+					    struct graphics_object_i2c_info *info);
-+
-+enum bp_result dc_bios_get_thermal_ddc_info(struct dc_bios *bios,
-+					    uint32_t i2c_channel_id,
-+					    struct graphics_object_i2c_info *info);
-+enum bp_result dc_bios_get_hpd_info(struct dc_bios *bios,
-+				    struct graphics_object_id id,
-+				    struct graphics_object_hpd_info *info);
-+enum bp_result dc_bios_get_device_tag(struct dc_bios *bios,
-+				      struct graphics_object_id connector_object_id,
-+				      uint32_t device_tag_index,
-+				      struct connector_device_tag_info *info);
-+
-+enum bp_result dc_bios_get_firmware_info(struct dc_bios *bios,
-+					 struct firmware_info *info);
-+
-+enum bp_result dc_bios_get_spread_spectrum_info(struct dc_bios *bios,
-+						enum as_signal_type signal,
-+						uint32_t index,
-+						struct spread_spectrum_info *ss_info);
-+uint32_t dc_bios_get_ss_entry_number(struct dc_bios *bios,
-+				     enum as_signal_type signal);
-+enum bp_result dc_bios_get_embedded_panel_info(struct dc_bios *bios,
-+					       struct embedded_panel_info *info);
-+enum bp_result dc_bios_enum_embedded_panel_patch_mode(struct dc_bios *bios,
-+						      uint32_t index,
-+						      struct embedded_panel_patch_mode *mode);
-+
-+enum bp_result dc_bios_get_gpio_pin_info(struct dc_bios *bios,
-+					 uint32_t gpio_id,
-+					 struct gpio_pin_info *info);
-+
-+enum bp_result dc_bios_get_faked_edid_len(struct dc_bios *bios,
-+					  uint32_t *len);
-+
-+enum bp_result dc_bios_get_faked_edid_buf(struct dc_bios *bios,
-+					  uint8_t *buff,
-+					  uint32_t len);
-+
-+enum bp_result dc_bios_get_encoder_cap_info(struct dc_bios *bios,
-+					    struct graphics_object_id object_id,
-+					    struct bp_encoder_cap_info *info);
-+enum bp_result dc_bios_get_din_connector_info(struct dc_bios *bios,
-+					      struct graphics_object_id id,
-+					      struct din_connector_info *info);
-+bool dc_bios_is_device_id_supported(struct dc_bios *bios,
-+				    struct device_id id);
-+bool dc_bios_is_accelerated_mode(struct dc_bios *bios);
-+bool dc_bios_is_lid_open(struct dc_bios *bios);
-+#if 0 /* unused trap to debugger functions */
-+
-+bool dc_bios_is_lid_status_changed(struct dc_bios *bios);
-+bool dc_bios_is_display_config_changed(struct dc_bios *bios);
-+
-+void dc_bios_set_scratch_lcd_scale(struct dc_bios *bios,
-+				   enum lcd_scale scale);
-+enum lcd_scale  dc_bios_get_scratch_lcd_scale(struct dc_bios *bios);
-+void dc_bios_get_bios_event_info(struct dc_bios *bios,
-+				 struct bios_event_info *info);
-+void dc_bios_update_requested_backlight_level(struct dc_bios *bios,
-+					      uint32_t backlight_8bit);
-+uint32_t dc_bios_get_requested_backlight_level(struct dc_bios *bios);
-+void dc_bios_take_backlight_control(struct dc_bios *bios,
-+				    bool cntl);
-+bool dc_bios_is_active_display(struct dc_bios *bios,
-+			       enum signal_type signal,
-+			       const struct connector_device_tag_info *device_tag);
-+enum controller_id dc_bios_get_embedded_display_controller_id(struct dc_bios *bios);
-+uint32_t dc_bios_get_embedded_display_refresh_rate(struct dc_bios *bios);
-+#endif
-+
-+void dc_bios_set_scratch_connected(struct dc_bios *bios,
-+				   struct graphics_object_id connector_id,
-+				   bool connected,
-+				   const struct connector_device_tag_info *device_tag);
-+void dc_bios_prepare_scratch_active_and_requested(struct dc_bios *bios,
-+						  enum controller_id controller_id,
-+						  enum signal_type signal,
-+						  const struct connector_device_tag_info *device_tag);
-+void dc_bios_set_scratch_active_and_requested(struct dc_bios *bios);
-+void dc_bios_set_scratch_critical_state(struct dc_bios *bios,
-+					bool state);
-+void dc_bios_set_scratch_acc_mode_change(struct dc_bios *bios);
-+
-+/* COMMANDS */
-+enum bp_result dc_bios_encoder_control(struct dc_bios *bios,
-+				       struct bp_encoder_control *cntl);
-+enum bp_result dc_bios_transmitter_control(struct dc_bios *bios,
-+					   struct bp_transmitter_control *cntl);
-+enum bp_result dc_bios_crt_control(struct dc_bios *bios,
-+				   enum engine_id engine_id,
-+				   bool enable,
-+				   uint32_t pixel_clock);
-+enum bp_result dc_bios_enable_crtc(struct dc_bios *bios,
-+				   enum controller_id id,
-+				   bool enable);
-+enum bp_result dc_bios_adjust_pixel_clock(struct dc_bios *bios,
-+					  struct bp_adjust_pixel_clock_parameters *bp_params);
-+enum bp_result dc_bios_set_pixel_clock(struct dc_bios *bios,
-+				       struct bp_pixel_clock_parameters *bp_params);
-+enum bp_result dc_bios_set_dce_clock(struct dc_bios *bios,
-+				     struct bp_set_dce_clock_parameters *bp_params);
-+enum bp_result dc_bios_enable_spread_spectrum_on_ppll(struct dc_bios *bios,
-+						      struct bp_spread_spectrum_parameters *bp_params,
-+						      bool enable);
-+enum bp_result dc_bios_program_crtc_timing(struct dc_bios *bios,
-+					   struct bp_hw_crtc_timing_parameters *bp_params);
-+enum bp_result dc_bios_blank_crtc(struct dc_bios *bios,
-+				  struct bp_blank_crtc_parameters *bp_params,
-+				  bool blank);
-+enum bp_result dc_bios_set_overscan(struct dc_bios *bios,
-+				    struct bp_hw_crtc_overscan_parameters *bp_params);
-+enum bp_result dc_bios_crtc_source_select(struct dc_bios *bios,
-+					  struct bp_crtc_source_select *bp_params);
-+enum bp_result dc_bios_program_display_engine_pll(struct dc_bios *bios,
-+						  struct bp_pixel_clock_parameters *bp_params);
-+enum bp_result dc_bios_get_divider_for_target_display_clock(struct dc_bios *bios,
-+							    struct bp_display_clock_parameters *bp_params);
-+enum signal_type dc_bios_dac_load_detect(struct dc_bios *bios,
-+					 struct graphics_object_id encoder,
-+					 struct graphics_object_id connector,
-+					 enum signal_type display_signal);
-+enum bp_result dc_bios_enable_memory_requests(struct dc_bios *bios,
-+					      enum controller_id controller_id,
-+					      bool enable);
-+enum bp_result dc_bios_external_encoder_control(struct dc_bios *bios,
-+						struct bp_external_encoder_control *cntl);
-+enum bp_result dc_bios_enable_disp_power_gating(struct dc_bios *bios,
-+						enum controller_id controller_id,
-+						enum bp_pipe_control_action action);
-+
-+
-+void dc_bios_post_init(struct dc_bios *bios);
-+
-+struct integrated_info *dc_bios_create_integrated_info(struct dc_bios *bios);
-+
-+void dc_bios_destroy_integrated_info(struct dc_bios *dcb,
-+				     struct integrated_info **info);
-+
-+struct dc_bios;
- 
- #endif /* DC_BIOS_TYPES_H */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-index a2a4f2a..ef1afd3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
-@@ -221,8 +221,7 @@ static bool dce100_enable_display_power_gating(
- 		cntl = ASIC_PIPE_DISABLE;
- 
- 	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0))
--		bp_result = dcb->funcs->enable_disp_power_gating(
--						dcb, controller_id + 1, cntl);
-+		bp_result = dc_bios_enable_disp_power_gating(dcb, controller_id + 1, cntl);
- 
- 	if (bp_result == BP_RESULT_OK)
- 		return true;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index d9c1d86..d48e3df 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -428,8 +428,8 @@ static bool pll_adjust_pix_clk(
- 	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
- 	bp_adjust_pixel_clock_params.
- 		ss_enable = pix_clk_params->flags.ENABLE_SS;
--	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
--			clk_src->bios, &bp_adjust_pixel_clock_params);
-+	bp_result = dc_bios_adjust_pixel_clock(clk_src->bios,
-+					       &bp_adjust_pixel_clock_params);
- 	if (bp_result == BP_RESULT_OK) {
- 		pll_settings->actual_pix_clk = actual_pix_clk_khz;
- 		pll_settings->adjusted_pix_clk =
-@@ -552,10 +552,9 @@ static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
- 	bp_ss_params.pll_id = clk_src->base.id;
- 
- 	/*Call ASICControl to process ATOMBIOS Exec table*/
--	result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
--			clk_src->bios,
--			&bp_ss_params,
--			false);
-+	result = dc_bios_enable_spread_spectrum_on_ppll(clk_src->bios,
-+							&bp_ss_params,
-+							false);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -659,11 +658,9 @@ static bool enable_spread_spectrum(
- 				bp_params.flags.EXTERNAL_SS = 1;
- 
- 			if (BP_RESULT_OK !=
--				clk_src->bios->funcs->
--					enable_spread_spectrum_on_ppll(
--							clk_src->bios,
--							&bp_params,
--							true))
-+			    dc_bios_enable_spread_spectrum_on_ppll(clk_src->bios,
-+								   &bp_params,
-+								   true))
- 				return false;
- 		} else
- 			return false;
-@@ -766,8 +763,8 @@ static bool dce110_program_pix_clk(
- 	bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
- 					pll_settings->use_external_clk;
- 
--	if (dce110_clk_src->bios->funcs->set_pixel_clock(
--			dce110_clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+	if (dc_bios_set_pixel_clock(dce110_clk_src->bios,
-+				    &bp_pc_params) != BP_RESULT_OK)
- 		return false;
- 
- /* Enable SS
-@@ -808,7 +805,7 @@ static bool dce110_clock_source_power_down(
- 	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
- 
- 	/*Call ASICControl to process ATOMBIOS Exec table*/
--	bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
-+	bp_result = dc_bios_set_pixel_clock(
- 			dce110_clk_src->bios,
- 			&bp_pixel_clock_params);
- 
-@@ -855,9 +852,8 @@ static void get_ss_info_from_atombios(
- 	spread_spectrum_data[0] = NULL;
- 	*ss_entries_num = 0;
- 
--	*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
--			clk_src->bios,
--			as_signal);
-+	*ss_entries_num = dc_bios_get_ss_entry_number(clk_src->bios,
-+						      as_signal);
- 
- 	if (*ss_entries_num == 0)
- 		return;
-@@ -875,12 +871,11 @@ static void get_ss_info_from_atombios(
- 		i < (*ss_entries_num);
- 		++i, ++ss_info_cur) {
- 
--		bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
--				clk_src->bios,
--				as_signal,
--				i,
--				ss_info_cur);
--
-+		bp_result = dc_bios_get_spread_spectrum_info(clk_src->bios,
-+							     as_signal,
-+							     i,
-+							     ss_info_cur);
-+		
- 		if (bp_result != BP_RESULT_OK)
- 			goto out_free_data;
- 	}
-@@ -982,9 +977,8 @@ static bool calc_pll_max_vco_construct(
- 			init_data->bp == NULL)
- 		return false;
- 
--	if (init_data->bp->funcs->get_firmware_info(
--				init_data->bp,
--				&fw_info) != BP_RESULT_OK)
-+	if (dc_bios_get_firmware_info(init_data->bp,
-+				      &fw_info) != BP_RESULT_OK)
- 		return false;
- 
- 	calc_pll_cs->ctx = init_data->ctx;
-@@ -1103,8 +1097,7 @@ bool dce110_clk_src_construct(
- 	clk_src->base.id = id;
- 	clk_src->base.funcs = &dce110_clk_src_funcs;
- 
--	if (clk_src->bios->funcs->get_firmware_info(
--			clk_src->bios, &fw_info) != BP_RESULT_OK) {
-+	if (dc_bios_get_firmware_info(clk_src->bios, &fw_info) != BP_RESULT_OK) {
- 		ASSERT_CRITICAL(false);
- 		goto unexpected_failure;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 53da396..73c576e 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -377,8 +377,7 @@ static bool dce110_enable_display_power_gating(
- 		controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
- 
- 	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0)
--		bp_result = dcb->funcs->enable_disp_power_gating(
--						dcb, controller_id + 1, cntl);
-+		bp_result = dc_bios_enable_disp_power_gating(dcb, controller_id + 1, cntl);
- 
- 	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
- 		dce110_init_pte(ctx);
-@@ -486,7 +485,7 @@ static enum dc_status bios_parser_crtc_source_select(
- 
- 	dcb = dal_adapter_service_get_bios_parser(sink->link->adapter_srv);
- 
--	if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
-+	if (BP_RESULT_OK != dc_bios_crtc_source_select(
- 		dcb,
- 		&crtc_source_select)) {
- 		return DC_ERROR_UNEXPECTED;
-@@ -520,7 +519,7 @@ static void update_bios_scratch_critical_state(struct adapter_service *as,
- {
- 	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
- 
--	dcb->funcs->set_scratch_critical_state(dcb, state);
-+	dc_bios_set_scratch_critical_state(dcb, state);
- }
- 
- static void update_info_frame(struct pipe_ctx *pipe_ctx)
-@@ -882,7 +881,7 @@ static void enable_accelerated_mode(struct core_dc *dc)
- 
- 	disable_vga_and_power_gate_all_controllers(dc);
- 
--	dcb->funcs->set_scratch_acc_mode_change(dcb);
-+	dc_bios_set_scratch_acc_mode_change(dcb);
- }
- 
- #if 0
-@@ -1558,7 +1557,7 @@ static void init_hw(struct core_dc *dc)
- 	}
- 
- 	dc->hwss.clock_gating_power_up(dc->ctx, false);
--	bp->funcs->power_up(bp);
-+	dc_bios_power_up(bp);
- 	/***************************************/
- 
- 	for (i = 0; i < dc->link_count; i++) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-index 8da3e4d..4487638 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
-@@ -118,7 +118,7 @@ static enum bp_result link_transmitter_control(
- 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(
- 					enc110->base.adapter_service);
- 
--	result = bp->funcs->transmitter_control(bp, cntl);
-+	result = dc_bios_transmitter_control(bp, cntl);
- 
- 	return result;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-index dcca860..0ff37da 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
-@@ -410,8 +410,7 @@ void dce110_stream_encoder_hdmi_set_stream_attribute(
- 	cntl.lanes_number = LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
--	if (enc110->base.bp->funcs->encoder_control(
--			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+	if (dc_bios_encoder_control(enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
- 	addr = LINK_REG(DIG_FE_CNTL);
-@@ -591,8 +590,7 @@ void dce110_stream_encoder_dvi_set_stream_attribute(
- 				LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
--	if (enc110->base.bp->funcs->encoder_control(
--			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+	if (dc_bios_encoder_control(enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
- 	switch (crtc_timing->pixel_encoding) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-index b17fb79..5572995 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
-@@ -291,7 +291,7 @@ bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
- 	value = 0;
- 	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value);
- 
--	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
-+	result = dc_bios_enable_crtc(tg->bp, tg110->controller_id, true);
- 
- 	return result == BP_RESULT_OK;
- }
-@@ -469,7 +469,7 @@ bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
- 
- 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- 
--	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);
-+	result = dc_bios_enable_crtc(tg->bp, tg110->controller_id, false);
- 
- 	/* Need to make sure stereo is disabled according to the DCE5.0 spec */
- 
-@@ -574,7 +574,7 @@ bool dce110_timing_generator_program_timing_generator(
- 	if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1)
- 		bp_params.flags.HORZ_COUNT_BY_TWO = 1;
- 
--	result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params);
-+	result = dc_bios_program_crtc_timing(tg->bp, &bp_params);
- 
- 	program_horz_count_by_2(tg, &patched_crtc_timing);
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
-index 7ec9508..65ddb80 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
-@@ -188,7 +188,7 @@ static bool dce112_program_pix_clk(
- 		bp_pc_params.flags.SUPPORT_YUV_420 = 0;
- 	}
- 
--	if (dce112_clk_src->bios->funcs->set_pixel_clock(
-+	if (dc_bios_set_pixel_clock(
- 			dce112_clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
- 		return false;
- 
-@@ -219,7 +219,7 @@ static bool dce112_clock_source_power_down(
- 	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
- 
- 	/*Call ASICControl to process ATOMBIOS Exec table*/
--	bp_result = dce112_clk_src->bios->funcs->set_pixel_clock(
-+	bp_result = dc_bios_set_pixel_clock(
- 			dce112_clk_src->bios,
- 			&bp_pixel_clock_params);
- 
-@@ -250,7 +250,7 @@ bool dce112_clk_src_construct(
- 	clk_src->base.funcs = &dce112_clk_src_funcs;
- 	clk_src->offsets = *reg_offsets;
- 
--	if (clk_src->bios->funcs->get_firmware_info(
-+	if (dc_bios_get_firmware_info(
- 			clk_src->bios, &fw_info) != BP_RESULT_OK) {
- 		ASSERT_CRITICAL(false);
- 		goto unexpected_failure;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-index 931e47e..437b4c3 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
-@@ -347,7 +347,7 @@ static bool dce112_enable_display_power_gating(
- 		cntl = ASIC_PIPE_DISABLE;
- 
- 	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0)
--		bp_result = dcb->funcs->enable_disp_power_gating(
-+		bp_result = dc_bios_enable_disp_power_gating(
- 						dcb, controller_id + 1, cntl);
- 
- 	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-index 68cf84d..e99d694 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
-@@ -203,7 +203,7 @@ static bool dce80_enable_display_power_gating(
- 		cntl = ASIC_PIPE_DISABLE;
- 
- 	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0))
--		bp_result = dcb->funcs->enable_disp_power_gating(
-+		bp_result = dc_bios_enable_disp_power_gating(
- 						dcb, controller_id + 1, cntl);
- 
- 	if (bp_result == BP_RESULT_OK)
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-index 4615c34..653983d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
-@@ -79,7 +79,7 @@ static enum bp_result link_transmitter_control(
- 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(
- 					enc110->base.adapter_service);
- 
--	result = bp->funcs->transmitter_control(bp, cntl);
-+	result = dc_bios_transmitter_control(bp, cntl);
- 
- 	return result;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-index f0a7ee1..7f62b0d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_stream_encoder.c
-@@ -426,8 +426,7 @@ void dce80_stream_encoder_hdmi_set_stream_attribute(
- 	cntl.lanes_number = LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
--	if (enc110->base.bp->funcs->encoder_control(
--			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+	if (dc_bios_encoder_control(enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
- 	switch (crtc_timing->pixel_encoding) {
-@@ -567,8 +566,7 @@ void dce80_stream_encoder_dvi_set_stream_attribute(
- 				LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
- 	cntl.color_depth = crtc_timing->display_color_depth;
- 
--	if (enc110->base.bp->funcs->encoder_control(
--			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+	if (dc_bios_encoder_control(enc110->base.bp, &cntl) != BP_RESULT_OK)
- 		return;
- 
- 	switch (crtc_timing->pixel_encoding) {
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index ba9a1fa..3d0f8e1 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -789,7 +789,7 @@ static void set_clock(
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = base->id;
- 
--	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-+	dc_bios_program_display_engine_pll(bp, &pxl_clk_params);
- 
- 	if (dc->dfs_bypass_enabled) {
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-index 875bf22..08a70db 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-@@ -776,7 +776,7 @@ static void set_clock(
- 	dce_clk_params.pll_id = dc->disp_clk_base.id;
- 	dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
- 
--	bp->funcs->set_dce_clock(bp, &dce_clk_params);
-+	dc_bios_set_dce_clock(bp, &dce_clk_params);
- 
- 	/* from power down, we need mark the clock state as ClocksStateNominal
- 	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-@@ -790,7 +790,7 @@ static void set_clock(
- 	dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
- 			(dce_clk_params.pll_id == CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
- 
--	bp->funcs->set_dce_clock(bp, &dce_clk_params);
-+	dc_bios_set_dce_clock(bp, &dce_clk_params);
- }
- 
- static void set_clock_state(
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-index 74d5b2e..313651c 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
-@@ -478,7 +478,7 @@ static void set_clock(
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = dc->id;
- 
--	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-+	dc_bios_program_display_engine_pll(bp, &pxl_clk_params);
- 
- 	if (disp_clk->dfs_bypass_enabled) {
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1013-drm-amd-dal-properly-abstract-bios-parser-from-adapt.patch b/common/recipes-kernel/linux/files/1013-drm-amd-dal-properly-abstract-bios-parser-from-adapt.patch
deleted file mode 100644
index d7dc1c79..00000000
--- a/common/recipes-kernel/linux/files/1013-drm-amd-dal-properly-abstract-bios-parser-from-adapt.patch
+++ /dev/null
@@ -1,290 +0,0 @@
-From 7c6ae82ece0599ff9cb5f06ba6d4c265ac500544 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:16:19 +1000
-Subject: [PATCH 1013/1110] drm/amd/dal: properly abstract bios parser from
- adapter service.
-
-The adapter service is only used in one place in this code, so
-pass it into the API rather than storing it for ever.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  6 +--
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 56 ++++++++++------------
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h      |  1 -
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |  3 +-
- .../drm/amd/dal/include/bios_parser_interface.h    |  2 +-
- 5 files changed, 32 insertions(+), 36 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-index 810776b..b4f9750 100644
---- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
-@@ -749,6 +749,7 @@ static bool adapter_service_construct(
- 	}
- 
- 	as->dce_environment = init_data->dce_environment;
-+	dce_version = dal_adapter_service_get_dce_version(as);
- 
- 	if (init_data->vbios_override)
- 		as->dcb_override = init_data->vbios_override;
-@@ -757,7 +758,7 @@ static bool adapter_service_construct(
- 		init_data->bp_init_data.ctx = init_data->ctx;
- 
- 		as->dcb_internal = dal_bios_parser_create(
--				&init_data->bp_init_data, as);
-+				&init_data->bp_init_data, dce_version);
- 
- 		if (!as->dcb_internal) {
- 			ASSERT_CRITICAL(false);
-@@ -767,7 +768,6 @@ static bool adapter_service_construct(
- 
- 	dcb = dal_adapter_service_get_bios_parser(as);
- 
--	dce_version = dal_adapter_service_get_dce_version(as);
- 
- 	/* Create GPIO service */
- 	as->gpio_service = dal_gpio_service_create(
-@@ -804,7 +804,7 @@ static bool adapter_service_construct(
- 	/* Integrated info is not provided on discrete ASIC. NULL is allowed */
- 	as->integrated_info = dc_bios_create_integrated_info(dcb);
- 
--	dc_bios_post_init(dcb);
-+	dc_bios_post_init(dcb, as);
- 
- 	/* Generate backlight translation table and initializes
- 			  other brightness properties */
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 8bb5454..cdf674d 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -94,7 +94,6 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id);
- static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
- 	struct bios_parser *bp,
- 	ATOM_OBJECT *object);
--static void process_ext_display_connection_info(struct bios_parser *bp);
- 
- #define BIOS_IMAGE_SIZE_OFFSET 2
- #define BIOS_IMAGE_SIZE_UNIT 512
-@@ -103,7 +102,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp);
- static bool bios_parser_construct(
- 	struct bios_parser *bp,
- 	struct bp_init_data *init,
--	struct adapter_service *as);
-+	enum dce_version dce_version);
- 
- enum bp_result dc_bios_get_embedded_panel_info(struct dc_bios *dcb,
- 					       struct embedded_panel_info *info);
-@@ -111,7 +110,8 @@ enum bp_result dc_bios_get_embedded_panel_info(struct dc_bios *dcb,
- /*****************************************************************************/
- 
- struct dc_bios *dal_bios_parser_create(
--	struct bp_init_data *init, struct adapter_service *as)
-+	struct bp_init_data *init,
-+	enum dce_version dce_version)
- {
- 	struct bios_parser *bp = NULL;
- 
-@@ -119,7 +119,7 @@ struct dc_bios *dal_bios_parser_create(
- 	if (!bp)
- 		return NULL;
- 
--	if (bios_parser_construct(bp, init, as))
-+	if (bios_parser_construct(bp, init, dce_version))
- 		return (struct dc_bios *)bp;
- 
- 	dm_free(bp);
-@@ -3369,7 +3369,7 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
-  */
- 
- static bool i2c_read(
--	struct bios_parser *bp,
-+	struct adapter_service *as,
- 	struct graphics_object_i2c_info *i2c_info,
- 	uint8_t *buffer,
- 	uint32_t length)
-@@ -3379,14 +3379,14 @@ static bool i2c_read(
- 	bool result = false;
- 	struct i2c_command cmd;
- 
--	ddc = dal_adapter_service_obtain_ddc_from_i2c_info(bp->as, i2c_info);
-+	ddc = dal_adapter_service_obtain_ddc_from_i2c_info(as, i2c_info);
- 
- 	if (!ddc)
- 		return result;
- 
- 	/*Using SW engine */
- 	cmd.engine = I2C_COMMAND_ENGINE_SW;
--	cmd.speed = dal_adapter_service_get_sw_i2c_speed(bp->as);
-+	cmd.speed = dal_adapter_service_get_sw_i2c_speed(as);
- 
- 	{
- 		struct i2c_payload payloads[] = {
-@@ -3409,12 +3409,12 @@ static bool i2c_read(
- 
- 		/* TODO route this through drm i2c_adapter */
- 		result = dal_i2caux_submit_i2c_command(
--				dal_adapter_service_get_i2caux(bp->as),
-+				dal_adapter_service_get_i2caux(as),
- 				ddc,
- 				&cmd);
- 	}
- 
--	dal_adapter_service_release_ddc(bp->as, ddc);
-+	dal_adapter_service_release_ddc(as, ddc);
- 
- 	return result;
- }
-@@ -3427,6 +3427,7 @@ static bool i2c_read(
-  */
- static enum bp_result get_ext_display_connection_info(
- 	struct bios_parser *bp,
-+	struct adapter_service *as,
- 	ATOM_OBJECT *opm_object,
- 	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *ext_display_connection_info_tbl)
- {
-@@ -3453,11 +3454,10 @@ static enum bp_result get_ext_display_connection_info(
- 				BP_RESULT_OK)
- 			return BP_RESULT_BADBIOSTABLE;
- 
--		if (i2c_read(
--				bp,
--				&i2c_info,
--				(uint8_t *)ext_display_connection_info_tbl,
--				sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
-+		if (i2c_read(as,
-+			     &i2c_info,
-+			     (uint8_t *)ext_display_connection_info_tbl,
-+			     sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
- 			config_tbl_present = true;
- 		}
- 	}
-@@ -3774,7 +3774,8 @@ static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
-  *
-  */
- static enum bp_result patch_bios_image_from_ext_display_connection_info(
--	struct bios_parser *bp)
-+	struct bios_parser *bp,
-+	struct adapter_service *as)
- {
- 	ATOM_OBJECT_TABLE *connector_tbl;
- 	uint32_t connector_tbl_offset;
-@@ -3814,10 +3815,9 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
- 	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
- 
- 	/* Read Connector info table from EEPROM through i2c */
--	if (get_ext_display_connection_info(
--			bp,
--			opm_object,
--			&ext_display_connection_info_tbl) != BP_RESULT_OK) {
-+	if (get_ext_display_connection_info(bp, as,
-+					    opm_object,
-+					    &ext_display_connection_info_tbl) != BP_RESULT_OK) {
- 		if (bp->headless_no_opm) {
- 			/* Failed to read OPM, remove all non-CF connectors. */
- 			for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
-@@ -4025,7 +4025,8 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
-  *
-  */
- 
--static void process_ext_display_connection_info(struct bios_parser *bp)
-+static void process_ext_display_connection_info(struct bios_parser *bp,
-+						struct adapter_service *as)
- {
- 	ATOM_OBJECT_TABLE *connector_tbl;
- 	uint32_t connector_tbl_offset;
-@@ -4080,7 +4081,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 		/* Step 2: (only if MXM connector found) Patch BIOS image with
- 		 * info from external module */
- 		if (mxm_connector_found &&
--				patch_bios_image_from_ext_display_connection_info(bp) !=
-+		    patch_bios_image_from_ext_display_connection_info(bp, as) !=
- 						BP_RESULT_OK) {
- 			/* Patching the bios image has failed. We will copy
- 			 * again original image provided and afterwards
-@@ -4114,11 +4115,12 @@ static void process_ext_display_connection_info(struct bios_parser *bp)
- 	}
- }
- 
--void dc_bios_post_init(struct dc_bios *dcb)
-+void dc_bios_post_init(struct dc_bios *dcb,
-+		       struct adapter_service *as)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
- 
--	process_ext_display_connection_info(bp);
-+	process_ext_display_connection_info(bp, as);
- }
- 
- bool dc_bios_is_accelerated_mode(struct dc_bios *dcb)
-@@ -4765,15 +4767,11 @@ static uint32_t get_embedded_display_refresh_rate(
- static bool bios_parser_construct(
- 	struct bios_parser *bp,
- 	struct bp_init_data *init,
--	struct adapter_service *as)
-+	enum dce_version dce_version)
- {
- 	uint16_t *rom_header_offset = NULL;
- 	ATOM_ROM_HEADER *rom_header = NULL;
- 	ATOM_OBJECT_HEADER *object_info_tbl;
--	enum dce_version dce_version;
--
--	if (!as)
--		return false;
- 
- 	if (!init)
- 		return false;
-@@ -4781,9 +4779,7 @@ static bool bios_parser_construct(
- 	if (!init->bios)
- 		return false;
- 
--	dce_version = dal_adapter_service_get_dce_version(as);
- 	bp->ctx = init->ctx;
--	bp->as = as;
- 	bp->bios = init->bios;
- 	bp->bios_size = bp->bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT;
- 	bp->bios_local_image = NULL;
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-index 2133a59..1db3eee 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h
-@@ -52,7 +52,6 @@ enum spread_spectrum_id {
- 
- struct bios_parser {
- 	struct dc_context *ctx;
--	struct adapter_service *as;
- 
- 	struct object_info_table object_info_tbl;
- 	uint32_t object_info_tbl_offset;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index f17702d..fa7b1fe 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -208,7 +208,8 @@ enum bp_result dc_bios_enable_disp_power_gating(struct dc_bios *bios,
- 						enum bp_pipe_control_action action);
- 
- 
--void dc_bios_post_init(struct dc_bios *bios);
-+void dc_bios_post_init(struct dc_bios *bios,
-+		       struct adapter_service *as);
- 
- struct integrated_info *dc_bios_create_integrated_info(struct dc_bios *bios);
- 
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-index d589e8d..a8f313a 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -38,7 +38,7 @@ struct bp_init_data {
- 
- struct dc_bios *dal_bios_parser_create(
- 	struct bp_init_data *init,
--	struct adapter_service *as);
-+	enum dce_version dce_version);
- 
- void dal_bios_parser_destroy(
- 	struct dc_bios **dcb);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1014-drm-amd-dal-drop-set_scratch_connected.patch b/common/recipes-kernel/linux/files/1014-drm-amd-dal-drop-set_scratch_connected.patch
deleted file mode 100644
index 4af7c0c4..00000000
--- a/common/recipes-kernel/linux/files/1014-drm-amd-dal-drop-set_scratch_connected.patch
+++ /dev/null
@@ -1,315 +0,0 @@
-From f7b93015ff2b31e5104a1c75f1b76d2ff414841e Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:30:36 +1000
-Subject: [PATCH 1014/1110] drm/amd/dal: drop set_scratch_connected
-
-this isn't used anywhere
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 31 -------
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |  5 --
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 89 --------------------
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   | 96 ----------------------
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |  4 -
- 5 files changed, 225 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index cdf674d..ddb5fc8 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -4140,37 +4140,6 @@ bool dc_bios_is_accelerated_mode(struct dc_bios *dcb)
- }
- 
- /**
-- * bios_parser_set_scratch_connected
-- *
-- * @brief
-- *  update VBIOS scratch register about connected displays
-- *
-- * @param
-- *  bool - update scratch register or just prepare info to be updated
-- *  bool - connection state
-- *  const ConnectorDeviceTagInfo* - pointer to device type and enum ID
-- */
--void dc_bios_set_scratch_connected(
--	struct dc_bios *dcb,
--	struct graphics_object_id connector_id,
--	bool connected,
--	const struct connector_device_tag_info *device_tag)
--{
--	struct bios_parser *bp = BP_FROM_DCB(dcb);
--
--#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
--	bp->bios_helper->set_scratch_connected(
--			bp->ctx,
--			connector_id, connected, device_tag);
--#else
--	dal_logger_write(bp->ctx->logger,
--			LOG_MAJOR_BIOS,
--			LOG_MINOR_BIOS_CMD_TABLE,
--			"%s: VBIOS is not supported", __func__);
--#endif
--}
--
--/**
-  * bios_parser_set_scratch_critical_state
-  *
-  * @brief
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index b93b046..124a11e 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -72,11 +72,6 @@ struct bios_parser_helper {
- 	void (*set_scratch_active_and_requested)(
- 		struct dc_context *ctx,
- 		struct vbios_helper_data *d);
--	void (*set_scratch_connected)(
--		struct dc_context *ctx,
--		struct graphics_object_id id,
--		bool connected,
--		const struct connector_device_tag_info *device_tag);
- 	void (*set_scratch_lcd_scale)(
- 		struct dc_context *ctx,
- 		enum lcd_scale lcd_scale_request);
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 85d3103..924957e 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -312,94 +312,6 @@ static enum signal_type detect_sink(
- 	return SIGNAL_TYPE_NONE;
- }
- 
--/**
-- * set_scratch_connected
-- *
-- * @brief
-- *    update BIOS_SCRATCH_0 register about connected displays
-- *
-- * @param
-- * bool - update scratch register or just prepare info to be updated
-- * bool - connection state
-- * const struct connector_device_tag_info * - pointer to device type and enum ID
-- */
--static void set_scratch_connected(
--	struct dc_context *ctx,
--	struct graphics_object_id id,
--	bool connected,
--	const struct connector_device_tag_info *device_tag)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--	uint32_t update = 0;
--
--	switch (device_tag->dev_id.device_type) {
--	case DEVICE_TYPE_LCD:
--		/* For LCD VBIOS will update LCD Panel connected bit always and
--		 * Lid state bit based on SBIOS info do not do anything here
--		 * for LCD
--		 */
--		break;
--	case DEVICE_TYPE_CRT:
--		/*
--		 * CRT is not supported in DCE11
--		 */
--		break;
--	case DEVICE_TYPE_DFP:
--		switch (device_tag->dev_id.enum_id) {
--		case 1:
--			update |= ATOM_S0_DFP1;
--			break;
--		case 2:
--			update |= ATOM_S0_DFP2;
--			break;
--		case 3:
--			update |= ATOM_S0_DFP3;
--			break;
--		case 4:
--			update |= ATOM_S0_DFP4;
--			break;
--		case 5:
--			update |= ATOM_S0_DFP5;
--			break;
--		case 6:
--			update |= ATOM_S0_DFP6;
--			break;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_CV:
--		/* DCE 8.0 does not support CV,
--		 * so don't do anything */
--		break;
--
--	case DEVICE_TYPE_TV:
--		/* For TV VBIOS will update S-Video or
--		 * Composite scratch bits on DAL_LoadDetect
--		 * when called by driver, do not do anything
--		 * here for TV
--		 */
--		break;
--
--	default:
--		break;
--
--	}
--
--	/* update scratch register */
--	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
--
--	value = dm_read_reg(ctx, addr);
--
--	if (connected)
--		value |= update;
--	else
--		value &= ~update;
--
--	dm_write_reg(ctx, addr, value);
--}
--
- static void set_scratch_critical_state(
- 	struct dc_context *ctx,
- 	bool state)
-@@ -460,7 +372,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 			prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.set_scratch_active_and_requested = set_scratch_active_and_requested,
--	.set_scratch_connected = set_scratch_connected,
- 	.set_scratch_critical_state = set_scratch_critical_state,
- 	.set_scratch_lcd_scale = set_scratch_lcd_scale,
- 	.take_backlight_control = NULL,
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index 4973132..3963129 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -352,101 +352,6 @@ static void set_scratch_active_and_requested(
- 	d->requested = 0;
- }
- 
--/**
-- * set_scratch_connected
-- *
-- * @brief
-- *    update BIOS_SCRATCH_0 register about connected displays
-- *
-- * @param
-- * bool - update scratch register or just prepare info to be updated
-- * bool - connection state
-- * const struct connector_device_tag_info * - pointer to device type and enum ID
-- */
--static void set_scratch_connected(
--	struct dc_context *ctx,
--	struct graphics_object_id id,
--	bool connected,
--	const struct connector_device_tag_info *device_tag)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--	uint32_t update = 0;
--
--	switch (device_tag->dev_id.device_type) {
--	case DEVICE_TYPE_LCD:
--		/* For LCD VBIOS will update LCD Panel connected bit always and
--		 * Lid state bit based on SBIOS info do not do anything here
--		 * for LCD
--		 */
--		break;
--	case DEVICE_TYPE_CRT:
--		switch (device_tag->dev_id.enum_id) {
--		case 1:
--			update |= ATOM_S0_CRT1_COLOR;
--			break;
--		case 2:
--			update |= ATOM_S0_CRT2_COLOR;
--			break;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_DFP:
--		switch (device_tag->dev_id.enum_id) {
--		case 1:
--			update |= ATOM_S0_DFP1;
--			break;
--		case 2:
--			update |= ATOM_S0_DFP2;
--			break;
--		case 3:
--			update |= ATOM_S0_DFP3;
--			break;
--		case 4:
--			update |= ATOM_S0_DFP4;
--			break;
--		case 5:
--			update |= ATOM_S0_DFP5;
--			break;
--		case 6:
--			update |= ATOM_S0_DFP6;
--			break;
--		default:
--			break;
--		}
--		break;
--	case DEVICE_TYPE_CV:
--		/* DCE 8.0 does not support CV,
--		 * so don't do anything */
--		break;
--
--	case DEVICE_TYPE_TV:
--		/* For TV VBIOS will update S-Video or
--		 * Composite scratch bits on DAL_LoadDetect
--		 * when called by driver, do not do anything
--		 * here for TV
--		 */
--		break;
--
--	default:
--		break;
--
--	}
--
--	/* update scratch register */
--	addr = mmBIOS_SCRATCH_0 + ATOM_DEVICE_CONNECT_INFO_DEF;
--
--	value = dm_read_reg(ctx, addr);
--
--	if (connected)
--		value |= update;
--	else
--		value &= ~update;
--
--	dm_write_reg(ctx, addr, value);
--}
--
- static void set_scratch_lcd_scale(
- 	struct dc_context *ctx,
- 	enum lcd_scale lcd_scale_request)
-@@ -759,7 +664,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 		prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.set_scratch_active_and_requested = set_scratch_active_and_requested,
--	.set_scratch_connected = set_scratch_connected,
- 	.set_scratch_critical_state = set_scratch_critical_state,
- 	.set_scratch_lcd_scale = set_scratch_lcd_scale,
- 	.take_backlight_control = take_backlight_control,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index fa7b1fe..458dcac 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -147,10 +147,6 @@ enum controller_id dc_bios_get_embedded_display_controller_id(struct dc_bios *bi
- uint32_t dc_bios_get_embedded_display_refresh_rate(struct dc_bios *bios);
- #endif
- 
--void dc_bios_set_scratch_connected(struct dc_bios *bios,
--				   struct graphics_object_id connector_id,
--				   bool connected,
--				   const struct connector_device_tag_info *device_tag);
- void dc_bios_prepare_scratch_active_and_requested(struct dc_bios *bios,
- 						  enum controller_id controller_id,
- 						  enum signal_type signal,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1015-drm-amd-dal-avoid-extra-interfaces-for-scratch_criti.patch b/common/recipes-kernel/linux/files/1015-drm-amd-dal-avoid-extra-interfaces-for-scratch_criti.patch
deleted file mode 100644
index 3683fdfe..00000000
--- a/common/recipes-kernel/linux/files/1015-drm-amd-dal-avoid-extra-interfaces-for-scratch_criti.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From 17345dc54501820d82995be29b161a8f69564129 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:37:17 +1000
-Subject: [PATCH 1015/1110] drm/amd/dal: avoid extra interfaces for
- scratch_critical_state.
-
-This is just an example of an over abstracted interface.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 26 ----------------------
- .../gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h   |  6 +++++
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c |  6 ++---
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |  2 --
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 17 +++++++-------
- 5 files changed, 16 insertions(+), 41 deletions(-)
- create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index ddb5fc8..fe3cc60 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -4139,32 +4139,6 @@ bool dc_bios_is_accelerated_mode(struct dc_bios *dcb)
- #endif
- }
- 
--/**
-- * bios_parser_set_scratch_critical_state
-- *
-- * @brief
-- *  update critical state bit in VBIOS scratch register
-- *
-- * @param
-- *  bool - to set or reset state
-- */
--void dc_bios_set_scratch_critical_state(
--	struct dc_bios *dcb,
--	bool state)
--{
--	struct bios_parser *bp = BP_FROM_DCB(dcb);
--
--#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
--	bp->bios_helper->set_scratch_critical_state(
--			bp->ctx, state);
--#else
--	dal_logger_write(bp->ctx->logger,
--			LOG_MAJOR_BIOS,
--			LOG_MINOR_BIOS_CMD_TABLE,
--			"%s: VBIOS is not supported", __func__);
--#endif
--}
--
- void dc_bios_set_scratch_acc_mode_change(struct dc_bios *dcb)
- {
- 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
-new file mode 100644
-index 0000000..a994d81
---- /dev/null
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
-@@ -0,0 +1,6 @@
-+#ifndef BIOS_DCE110_H
-+#define BIOS_DCE110_H
-+void dce110_set_scratch_critical_state(struct dc_context *ctx,
-+				       bool state);
-+
-+#endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 924957e..442e2a3 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -312,9 +312,8 @@ static enum signal_type detect_sink(
- 	return SIGNAL_TYPE_NONE;
- }
- 
--static void set_scratch_critical_state(
--	struct dc_context *ctx,
--	bool state)
-+void dce110_set_scratch_critical_state(struct dc_context *ctx,
-+				       bool state)
- {
- 	uint32_t addr = mmBIOS_SCRATCH_6;
- 	uint32_t value = dm_read_reg(ctx, addr);
-@@ -372,7 +371,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 			prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.set_scratch_active_and_requested = set_scratch_active_and_requested,
--	.set_scratch_critical_state = set_scratch_critical_state,
- 	.set_scratch_lcd_scale = set_scratch_lcd_scale,
- 	.take_backlight_control = NULL,
- 	.update_requested_backlight_level = NULL,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index 458dcac..7e37a72 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -152,8 +152,6 @@ void dc_bios_prepare_scratch_active_and_requested(struct dc_bios *bios,
- 						  enum signal_type signal,
- 						  const struct connector_device_tag_info *device_tag);
- void dc_bios_set_scratch_active_and_requested(struct dc_bios *bios);
--void dc_bios_set_scratch_critical_state(struct dc_bios *bios,
--					bool state);
- void dc_bios_set_scratch_acc_mode_change(struct dc_bios *bios);
- 
- /* COMMANDS */
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 73c576e..fbb9f63 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -34,6 +34,7 @@
- 
- #include "gpu/dce110/dc_clock_gating_dce110.h"
- 
-+#include "bios/dce110/bios_dce110.h"
- #include "timing_generator.h"
- #include "mem_input.h"
- #include "opp.h"
-@@ -514,12 +515,12 @@ static void program_fmt(
- 	return;
- }
- 
--static void update_bios_scratch_critical_state(struct adapter_service *as,
--		bool state)
-+static void update_bios_scratch_critical_state(struct core_dc *dc,
-+					       bool state)
- {
--	struct dc_bios *dcb = dal_adapter_service_get_bios_parser(as);
--
--	dc_bios_set_scratch_critical_state(dcb, state);
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
-+	dce110_set_scratch_critical_state(dc->ctx, state);
-+#endif
- }
- 
- static void update_info_frame(struct pipe_ctx *pipe_ctx)
-@@ -1206,8 +1207,7 @@ static enum dc_status apply_ctx_to_hw(
- 		return DC_OK;
- 
- 	/* Apply new context */
--	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
--			true);
-+	update_bios_scratch_critical_state(dc, true);
- 
- 	for (i = 0; i < MAX_PIPES; i++) {
- 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-@@ -1275,8 +1275,7 @@ static enum dc_status apply_ctx_to_hw(
- 
- 	dc->hwss.set_displaymarks(dc, context);
- 
--	update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
--			false);
-+	update_bios_scratch_critical_state(dc, false);
- 
- 	switch_dp_clock_sources(dc, &context->res_ctx);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1016-drm-amd-dal-drop-bios_power_down-and-unused-set_scra.patch b/common/recipes-kernel/linux/files/1016-drm-amd-dal-drop-bios_power_down-and-unused-set_scra.patch
deleted file mode 100644
index 2e038255..00000000
--- a/common/recipes-kernel/linux/files/1016-drm-amd-dal-drop-bios_power_down-and-unused-set_scra.patch
+++ /dev/null
@@ -1,196 +0,0 @@
-From 0fbccffaa6cc447843e521ce04cd48b3eb4045da Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:42:31 +1000
-Subject: [PATCH 1016/1110] drm/amd/dal: drop bios_power_down and unused
- set_scratch_lcd_scale API
-
-Drop dead code.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 16 ------------
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   | 17 -------------
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |  3 ---
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 11 --------
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   | 29 ----------------------
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |  3 ---
- 6 files changed, 79 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index fe3cc60..91b7d2b 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -148,15 +148,6 @@ void dal_bios_parser_destroy(struct dc_bios **dcb)
- 	*dcb = NULL;
- }
- 
--void dc_bios_power_down(struct dc_bios *dcb)
--{
--#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
--	struct bios_parser *bp = BP_FROM_DCB(dcb);
--
--	dal_bios_parser_set_scratch_lcd_scale(bp, bp->lcd_scale);
--#endif
--}
--
- void dc_bios_power_up(struct dc_bios *dcb)
- {
- #if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT)
-@@ -4642,13 +4633,6 @@ static bool is_display_config_changed(
- 	return false;
- }
- 
--static void set_scratch_lcd_scale(
--	struct dc_bios *bios,
--	enum lcd_scale scale)
--{
--	BREAK_TO_DEBUGGER();
--}
--
- static enum lcd_scale get_scratch_lcd_scale(
- 	struct dc_bios *bios)
- {
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index 4204798..af7a3b8 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -106,23 +106,6 @@ bool dal_bios_parser_is_display_config_changed(
- }
- 
- /**
--* dal_bios_parser_set_scratch_lcd_scale
--*
--* @brief
--*  update VBIOS scratch pad registers about LCD scale
--*
--* @param
--*  bool - to set to full panel mode or aspect-ratio mode
--*/
--void dal_bios_parser_set_scratch_lcd_scale(
--	struct bios_parser *bp,
--	enum lcd_scale scale)
--{
--	bp->bios_helper->set_scratch_lcd_scale(
--		bp->ctx, scale);
--}
--
--/**
- * dal_bios_parser_get_scratch_lcd_scale
- *
- * @brief
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index 124a11e..a8e10c9 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -72,9 +72,6 @@ struct bios_parser_helper {
- 	void (*set_scratch_active_and_requested)(
- 		struct dc_context *ctx,
- 		struct vbios_helper_data *d);
--	void (*set_scratch_lcd_scale)(
--		struct dc_context *ctx,
--		enum lcd_scale lcd_scale_request);
- 	enum lcd_scale (*get_scratch_lcd_scale)(
- 		struct dc_context *ctx);
- 	uint32_t (*fmt_control)(
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 442e2a3..16a63ea 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -326,16 +326,6 @@ void dce110_set_scratch_critical_state(struct dc_context *ctx,
- 	dm_write_reg(ctx, addr, value);
- }
- 
--static void set_scratch_lcd_scale(
--	struct dc_context *ctx,
--	enum lcd_scale lcd_scale_request)
--{
--	DAL_LOGGER_NOT_IMPL(
--		LOG_MINOR_COMPONENT_BIOS,
--		"Bios Parser:%s\n",
--		__func__);
--}
--
- static bool is_lid_open(struct dc_context *ctx)
- {
- 	uint32_t bios_scratch6;
-@@ -371,7 +361,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 			prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.set_scratch_active_and_requested = set_scratch_active_and_requested,
--	.set_scratch_lcd_scale = set_scratch_lcd_scale,
- 	.take_backlight_control = NULL,
- 	.update_requested_backlight_level = NULL,
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index 3963129..a7e42b5 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -352,34 +352,6 @@ static void set_scratch_active_and_requested(
- 	d->requested = 0;
- }
- 
--static void set_scratch_lcd_scale(
--	struct dc_context *ctx,
--	enum lcd_scale lcd_scale_request)
--{
--	uint32_t reg;
--
--	reg = dm_read_reg(ctx, mmBIOS_SCRATCH_6);
--
--	reg &= ~ATOM_S6_REQ_LCD_EXPANSION_FULL;
--	reg &= ~ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO;
--
--	switch (lcd_scale_request) {
--	case LCD_SCALE_FULLPANEL:
--		/* set Lcd Scale to Full Panel Mode */
--		reg |= ATOM_S6_REQ_LCD_EXPANSION_FULL;
--		break;
--	case LCD_SCALE_ASPECTRATIO:
--		/* set Lcd Scale to Aspect-Ratio Mode */
--		reg |= ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO;
--		break;
--	case LCD_SCALE_NONE:
--	default:
--		break;
--	}
--
--	dm_write_reg(ctx, mmBIOS_SCRATCH_6, reg);
--}
--
- static enum lcd_scale get_scratch_lcd_scale(
- 	struct dc_context *ctx)
- {
-@@ -665,7 +637,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.set_scratch_active_and_requested = set_scratch_active_and_requested,
- 	.set_scratch_critical_state = set_scratch_critical_state,
--	.set_scratch_lcd_scale = set_scratch_lcd_scale,
- 	.take_backlight_control = take_backlight_control,
- 	.update_requested_backlight_level = update_requested_backlight_level,
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index 7e37a72..a6fd93a 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -40,7 +40,6 @@
- 
- uint8_t dc_bios_get_connectors_number(struct dc_bios *bios);
- 
--void dc_bios_power_down(struct dc_bios *bios);
- void dc_bios_power_up(struct dc_bios *bios);
- 
- uint8_t dc_bios_get_encoders_number(struct dc_bios *bios);
-@@ -130,8 +129,6 @@ bool dc_bios_is_lid_open(struct dc_bios *bios);
- bool dc_bios_is_lid_status_changed(struct dc_bios *bios);
- bool dc_bios_is_display_config_changed(struct dc_bios *bios);
- 
--void dc_bios_set_scratch_lcd_scale(struct dc_bios *bios,
--				   enum lcd_scale scale);
- enum lcd_scale  dc_bios_get_scratch_lcd_scale(struct dc_bios *bios);
- void dc_bios_get_bios_event_info(struct dc_bios *bios,
- 				 struct bios_event_info *info);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1017-drm-amd-dal-drop-dead-set_critical_scratch-code.patch b/common/recipes-kernel/linux/files/1017-drm-amd-dal-drop-dead-set_critical_scratch-code.patch
deleted file mode 100644
index 3bdb0be6..00000000
--- a/common/recipes-kernel/linux/files/1017-drm-amd-dal-drop-dead-set_critical_scratch-code.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 977b21367fdb17c5f1188163a21d5ebafcbb6575 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:43:49 +1000
-Subject: [PATCH 1017/1110] drm/amd/dal: drop dead set_critical_scratch code.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h     |  3 ---
- .../drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c | 16 ----------------
- 2 files changed, 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index a8e10c9..6545f65 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -61,9 +61,6 @@ struct bios_parser_helper {
- 		struct dc_context *ctx);
- 	bool (*is_accelerated_mode)(
- 		struct dc_context *ctx);
--	void (*set_scratch_critical_state)(
--		struct dc_context *ctx,
--		bool state);
- 	void (*prepare_scratch_active_and_requested)(
- 		struct dc_context *ctx,
- 		struct vbios_helper_data *data,
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index a7e42b5..650a1ac 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -214,21 +214,6 @@ static bool is_accelerated_mode(
- 	return (value & ATOM_S6_ACC_MODE) ? true : false;
- }
- 
--static void set_scratch_critical_state(
--	struct dc_context *ctx,
--	bool state)
--{
--	uint32_t addr = mmBIOS_SCRATCH_6;
--	uint32_t value = dm_read_reg(ctx, addr);
--
--	if (state)
--		value |= ATOM_S6_CRITICAL_STATE;
--	else
--		value &= ~ATOM_S6_CRITICAL_STATE;
--
--	dm_write_reg(ctx, addr, value);
--}
--
- /**
-  * prepare_scratch_active_and_requested
-  *
-@@ -636,7 +621,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 		prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.set_scratch_active_and_requested = set_scratch_active_and_requested,
--	.set_scratch_critical_state = set_scratch_critical_state,
- 	.take_backlight_control = take_backlight_control,
- 	.update_requested_backlight_level = update_requested_backlight_level,
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1018-drm-amd-dal-more-dead-code.patch b/common/recipes-kernel/linux/files/1018-drm-amd-dal-more-dead-code.patch
deleted file mode 100644
index 1c842d9b..00000000
--- a/common/recipes-kernel/linux/files/1018-drm-amd-dal-more-dead-code.patch
+++ /dev/null
@@ -1,200 +0,0 @@
-From f42a3b1aa1514af93a8e775bff1c02a10bd82211 Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:45:55 +1000
-Subject: [PATCH 1018/1110] drm/amd/dal: more dead code
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 15 -------
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |  3 --
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 52 ----------------------
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   | 41 -----------------
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |  1 -
- 5 files changed, 112 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-index 91b7d2b..cecb30e 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
-@@ -4179,21 +4179,6 @@ void dc_bios_prepare_scratch_active_and_requested(struct dc_bios *dcb,
- #endif
- }
- 
--void dc_bios_set_scratch_active_and_requested(struct dc_bios *dcb)
--{
--	struct bios_parser *bp = BP_FROM_DCB(dcb);
--
--#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
--	bp->bios_helper->set_scratch_active_and_requested(
--			bp->ctx,
--			&bp->vbios_helper_data);
--#else
--	dal_logger_write(bp->ctx->logger,
--			LOG_MAJOR_BIOS,
--			LOG_MINOR_BIOS_CMD_TABLE,
--			"%s: VBIOS is not supported", __func__);
--#endif
--}
- 
- /*
-  * get_integrated_info_v8
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index 6545f65..1e17e74 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -66,9 +66,6 @@ struct bios_parser_helper {
- 		struct vbios_helper_data *data,
- 		enum controller_id id, enum signal_type s,
- 		const struct connector_device_tag_info *dev_tag);
--	void (*set_scratch_active_and_requested)(
--		struct dc_context *ctx,
--		struct vbios_helper_data *d);
- 	enum lcd_scale (*get_scratch_lcd_scale)(
- 		struct dc_context *ctx);
- 	uint32_t (*fmt_control)(
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 16a63ea..30cb2ee 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -59,57 +59,6 @@ static void set_scratch_acc_mode_change(
- 	dm_write_reg(ctx, addr, value);
- }
- 
--/*
-- * set_scratch_active_and_requested
-- *
-- * @brief
-- * Set VBIOS scratch pad registers about active and requested displays
-- *
-- * @param
-- * struct dc_context *ctx - [in] DAL context for register accessing
-- * struct vbios_helper_data *d - [in] values to write
-- */
--static void set_scratch_active_and_requested(
--	struct dc_context *ctx,
--	struct vbios_helper_data *d)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--
--	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
--	addr = mmBIOS_SCRATCH_3;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
--	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
--
--	dm_write_reg(ctx, addr, value);
--
--	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
--	addr = mmBIOS_SCRATCH_6;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S6_ACC_REQ_MASK;
--	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
--
--	dm_write_reg(ctx, addr, value);
--
--	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
--	addr = mmBIOS_SCRATCH_5;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
--	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
--
--	dm_write_reg(ctx, addr, value);
--
--	d->active = 0;
--	d->requested = 0;
--}
--
- /**
-  * get LCD Scale Mode from VBIOS scratch register
-  */
-@@ -360,7 +309,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.prepare_scratch_active_and_requested =
- 			prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
--	.set_scratch_active_and_requested = set_scratch_active_and_requested,
- 	.take_backlight_control = NULL,
- 	.update_requested_backlight_level = NULL,
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index 650a1ac..b9d01f3 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -296,46 +296,6 @@ static void prepare_scratch_active_and_requested(
- 	}
- }
- 
--static void set_scratch_active_and_requested(
--	struct dc_context *ctx,
--	struct vbios_helper_data *d)
--{
--	uint32_t addr = 0;
--	uint32_t value = 0;
--
--	/* mmBIOS_SCRATCH_3 = mmBIOS_SCRATCH_0 + ATOM_ACTIVE_INFO_DEF */
--	addr = mmBIOS_SCRATCH_3;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S3_DEVICE_ACTIVE_MASK;
--	value |= (d->active & ATOM_S3_DEVICE_ACTIVE_MASK);
--
--	dm_write_reg(ctx, addr, value);
--
--	/* mmBIOS_SCRATCH_6 =  mmBIOS_SCRATCH_0 + ATOM_ACC_CHANGE_INFO_DEF */
--	addr = mmBIOS_SCRATCH_6;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S6_ACC_REQ_MASK;
--	value |= (d->requested & ATOM_S6_ACC_REQ_MASK);
--
--	dm_write_reg(ctx, addr, value);
--
--	/* mmBIOS_SCRATCH_5 =  mmBIOS_SCRATCH_0 + ATOM_DOS_REQ_INFO_DEF */
--	addr = mmBIOS_SCRATCH_5;
--
--	value = dm_read_reg(ctx, addr);
--
--	value &= ~ATOM_S5_DOS_REQ_DEVICEw0;
--	value |= (d->active & ATOM_S5_DOS_REQ_DEVICEw0);
--
--	dm_write_reg(ctx, addr, value);
--
--	d->active = 0;
--	d->requested = 0;
--}
- 
- static enum lcd_scale get_scratch_lcd_scale(
- 	struct dc_context *ctx)
-@@ -620,7 +580,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.prepare_scratch_active_and_requested =
- 		prepare_scratch_active_and_requested,
- 	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
--	.set_scratch_active_and_requested = set_scratch_active_and_requested,
- 	.take_backlight_control = take_backlight_control,
- 	.update_requested_backlight_level = update_requested_backlight_level,
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index a6fd93a..73127c4 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -148,7 +148,6 @@ void dc_bios_prepare_scratch_active_and_requested(struct dc_bios *bios,
- 						  enum controller_id controller_id,
- 						  enum signal_type signal,
- 						  const struct connector_device_tag_info *device_tag);
--void dc_bios_set_scratch_active_and_requested(struct dc_bios *bios);
- void dc_bios_set_scratch_acc_mode_change(struct dc_bios *bios);
- 
- /* COMMANDS */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1019-drm-amd-dal-drop-call-dce110-set-scratch-acc-mode-di.patch b/common/recipes-kernel/linux/files/1019-drm-amd-dal-drop-call-dce110-set-scratch-acc-mode-di.patch
deleted file mode 100644
index 7c7c03fb..00000000
--- a/common/recipes-kernel/linux/files/1019-drm-amd-dal-drop-call-dce110-set-scratch-acc-mode-di.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 2f9d707a626f16107e9f06f4c2ccdb52c461418f Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:48:57 +1000
-Subject: [PATCH 1019/1110] drm/amd/dal: drop call dce110 set scratch acc mode
- directly
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h   |  2 +-
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c |  6 +++---
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   | 24 ----------------------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  6 +-----
- 4 files changed, 5 insertions(+), 33 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
-index a994d81..fd86296 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
-@@ -2,5 +2,5 @@
- #define BIOS_DCE110_H
- void dce110_set_scratch_critical_state(struct dc_context *ctx,
- 				       bool state);
--
-+void dce110_set_scratch_acc_mode_change(struct dc_context *ctx);
- #endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 30cb2ee..2a275b1 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -46,9 +46,9 @@
-  * @param
-  *  struct dc_context *ctx - [in] DAL context
-  */
--static void set_scratch_acc_mode_change(
--	struct dc_context *ctx)
-+void dce110_set_scratch_acc_mode_change(struct dc_context *ctx)
- {
-+#ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT
- 	uint32_t addr = mmBIOS_SCRATCH_6;
- 	uint32_t value = 0;
- 
-@@ -57,6 +57,7 @@ static void set_scratch_acc_mode_change(
- 	value |= ATOM_S6_ACC_MODE;
- 
- 	dm_write_reg(ctx, addr, value);
-+#endif
- }
- 
- /**
-@@ -308,7 +309,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.is_lid_status_changed = NULL,
- 	.prepare_scratch_active_and_requested =
- 			prepare_scratch_active_and_requested,
--	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.take_backlight_control = NULL,
- 	.update_requested_backlight_level = NULL,
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index b9d01f3..bff8fd4 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -173,29 +173,6 @@ static bool is_display_config_changed(
- }
- 
- /**
-- * set_scratch_acc_mode_change
-- *
-- * @brief
-- *  set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
-- *  VGA/non-Accelerated mode is set
-- *
-- * @param
-- *  NONE
-- */
--static void set_scratch_acc_mode_change(
--	struct dc_context *ctx)
--{
--	uint32_t addr = mmBIOS_SCRATCH_6;
--	uint32_t value = 0;
--
--	value = dm_read_reg(ctx, addr);
--
--	value |= ATOM_S6_ACC_MODE;
--
--	dm_write_reg(ctx, addr, value);
--}
--
--/**
-  * is_accelerated_mode
-  *
-  * @brief
-@@ -579,7 +556,6 @@ static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.is_lid_status_changed = is_lid_status_changed,
- 	.prepare_scratch_active_and_requested =
- 		prepare_scratch_active_and_requested,
--	.set_scratch_acc_mode_change = set_scratch_acc_mode_change,
- 	.take_backlight_control = take_backlight_control,
- 	.update_requested_backlight_level = update_requested_backlight_level,
- };
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index fbb9f63..6778c75 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -874,15 +874,11 @@ static void disable_vga_and_power_gate_all_controllers(
-  */
- static void enable_accelerated_mode(struct core_dc *dc)
- {
--	struct dc_bios *dcb;
--
--	dcb = dal_adapter_service_get_bios_parser(dc->res_pool.adapter_srv);
--
- 	power_down_all_hw_blocks(dc);
- 
- 	disable_vga_and_power_gate_all_controllers(dc);
- 
--	dc_bios_set_scratch_acc_mode_change(dcb);
-+	dce110_set_scratch_acc_mode_change(dc->ctx);
- }
- 
- #if 0
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1020-drm-amd-dal-kill-bunch-of-unused-code.patch b/common/recipes-kernel/linux/files/1020-drm-amd-dal-kill-bunch-of-unused-code.patch
deleted file mode 100644
index 6a32a82f..00000000
--- a/common/recipes-kernel/linux/files/1020-drm-amd-dal-kill-bunch-of-unused-code.patch
+++ /dev/null
@@ -1,539 +0,0 @@
-From c4a39fe28428791a7ed8ec4b179d6fd72bcbe86a Mon Sep 17 00:00:00 2001
-From: Dave Airlie <airlied@redhat.com>
-Date: Mon, 11 Apr 2016 17:54:21 +1000
-Subject: [PATCH 1020/1110] drm/amd/dal: kill bunch of unused code.
-
-Signed-off-by: Dave Airlie <airlied@redhat.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c   |  75 ------
- .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h   |  27 --
- .../dal/dc/bios/dce110/bios_parser_helper_dce110.c |  11 -
- .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   | 283 ---------------------
- drivers/gpu/drm/amd/dal/dc/dc_bios_types.h         |   1 -
- .../drm/amd/dal/include/bios_parser_interface.h    |  24 --
- 6 files changed, 421 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-index af7a3b8..e96314d 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
-@@ -98,13 +98,6 @@ bool dal_bios_parser_is_lid_status_changed(
- 			bp->ctx);
- }
- 
--bool dal_bios_parser_is_display_config_changed(
--	struct bios_parser *bp)
--{
--	return bp->bios_helper->is_display_config_changed(
--			bp->ctx);
--}
--
- /**
- * dal_bios_parser_get_scratch_lcd_scale
- *
-@@ -121,71 +114,3 @@ enum lcd_scale  dal_bios_parser_get_scratch_lcd_scale(
- 			bp->ctx);
- }
- 
--void dal_bios_parser_get_bios_event_info(
--	struct bios_parser *bp,
--	struct bios_event_info *info)
--{
--	bp->bios_helper->get_bios_event_info(
--		bp->ctx, info);
--}
--
--/* ABM related */
--
--void dal_bios_parser_update_requested_backlight_level(
--	struct bios_parser *bp,
--	uint32_t backlight_8bit)
--{
--	bp->bios_helper->update_requested_backlight_level(
--		bp->ctx,
--		backlight_8bit);
--}
--
--uint32_t dal_bios_parser_get_requested_backlight_level(
--	struct bios_parser *bp)
--{
--	return bp->bios_helper->get_requested_backlight_level(
--			bp->ctx);
--}
--
--void dal_bios_parser_take_backlight_control(
--	struct bios_parser *bp,
--	bool cntl)
--{
--	bp->bios_helper->take_backlight_control(
--		bp->ctx, cntl);
--}
--
--/**
-- * dal_bios_parser_is_active_display
-- *  Check video bios active display.
-- */
--bool dal_bios_parser_is_active_display(
--	struct bios_parser *bp,
--	enum signal_type signal,
--	const struct connector_device_tag_info *device_tag)
--{
--	return bp->bios_helper->is_active_display(
--			bp->ctx, signal, device_tag);
--}
--
--/**
-- * dal_bios_parser_get_embedded_display_controller_id
-- * Get controller ID for embedded display from scratch registers
-- */
--enum controller_id dal_bios_parser_get_embedded_display_controller_id(
--	struct bios_parser *bp)
--{
--	return bp->bios_helper->get_embedded_display_controller_id(
--			bp->ctx);
--}
--
--/**
-- * dal_bios_parser_get_embedded_display_refresh_rate
-- * Get refresh rate for embedded display from scratch registers
-- */
--uint32_t dal_bios_parser_get_embedded_display_refresh_rate(
--	struct bios_parser *bp)
--{
--	return bp->bios_helper->get_embedded_display_refresh_rate(
--			bp->ctx);
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-index 1e17e74..556c57c 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
-@@ -55,8 +55,6 @@ struct bios_parser_helper {
- 		struct dc_context *ctx);
- 	bool (*is_lid_status_changed)(
- 		struct dc_context *ctx);
--	bool (*is_display_config_changed)(
--		struct dc_context *ctx);
- 	void (*set_scratch_acc_mode_change)(
- 		struct dc_context *ctx);
- 	bool (*is_accelerated_mode)(
-@@ -68,31 +66,6 @@ struct bios_parser_helper {
- 		const struct connector_device_tag_info *dev_tag);
- 	enum lcd_scale (*get_scratch_lcd_scale)(
- 		struct dc_context *ctx);
--	uint32_t (*fmt_control)(
--		struct dc_context *ctx,
--		enum controller_id id, uint32_t *value);
--	uint32_t (*fmt_bit_depth_control)(
--		struct dc_context *ctx,
--		enum controller_id id,
--		uint32_t *value);
--	void (*get_bios_event_info)(
--		struct dc_context *ctx,
--		struct bios_event_info *info);
--	void (*take_backlight_control)(
--		struct dc_context *ctx, bool control);
--	uint32_t (*get_requested_backlight_level)(
--		struct dc_context *ctx);
--	void (*update_requested_backlight_level)(
--		struct dc_context *ctx,
--		uint32_t backlight_8bit);
--	bool (*is_active_display)(
--		struct dc_context *ctx,
--		enum signal_type signal,
--		const struct connector_device_tag_info *dev_tag);
--	enum controller_id (*get_embedded_display_controller_id)(
--		struct dc_context *ctx);
--	uint32_t (*get_embedded_display_refresh_rate)(
--		struct dc_context *ctx);
- };
- 
- bool dal_bios_parser_init_bios_helper(
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-index 2a275b1..88c3470 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
-@@ -295,22 +295,11 @@ static bool is_lid_open(struct dc_context *ctx)
- /* function table */
- static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.detect_sink = detect_sink,
--	.fmt_bit_depth_control = NULL,
--	.fmt_control = NULL,
--	.get_bios_event_info = NULL,
--	.get_embedded_display_controller_id = NULL,
--	.get_embedded_display_refresh_rate = NULL,
--	.get_requested_backlight_level = NULL,
- 	.get_scratch_lcd_scale = get_scratch_lcd_scale,
- 	.is_accelerated_mode = is_accelerated_mode,
--	.is_active_display = NULL,
--	.is_display_config_changed = NULL,
- 	.is_lid_open = is_lid_open,
--	.is_lid_status_changed = NULL,
- 	.prepare_scratch_active_and_requested =
- 			prepare_scratch_active_and_requested,
--	.take_backlight_control = NULL,
--	.update_requested_backlight_level = NULL,
- };
- 
- /*
-diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-index bff8fd4..ea0cfcb 100644
---- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
-@@ -149,29 +149,6 @@ static bool is_lid_status_changed(
- 	return result;
- }
- 
--static bool is_display_config_changed(
--	struct dc_context *ctx)
--{
--	bool result = false;
--
--	/* VBIOS does not provide bitfield definitions */
--	uint32_t reg;
--
--	reg = dm_read_reg(ctx,
--		mmBIOS_SCRATCH_6);
--
--	/* lid is open if the bit is not set */
--	if (reg & ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK) {
--		reg &= ~ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK;
--		dm_write_reg(ctx,
--				mmBIOS_SCRATCH_6, reg);
--
--		result = true;
--	}
--
--	return result;
--}
--
- /**
-  * is_accelerated_mode
-  *
-@@ -290,274 +267,14 @@ static enum lcd_scale get_scratch_lcd_scale(
- 		return LCD_SCALE_NONE;
- }
- 
--static uint32_t fmt_control(
--	struct dc_context *ctx,
--	enum controller_id id,
--	uint32_t *value)
--{
--	uint32_t result = 0;
--	uint32_t reg;
--
--	switch (id) {
--	case CONTROLLER_ID_D0:
--		reg = mmFMT0_FMT_CONTROL;
--		break;
--	case CONTROLLER_ID_D1:
--		reg = mmFMT1_FMT_CONTROL;
--		break;
--	case CONTROLLER_ID_D2:
--		reg = mmFMT2_FMT_CONTROL;
--		break;
--	case CONTROLLER_ID_D3:
--		reg = mmFMT3_FMT_CONTROL;
--		break;
--	case CONTROLLER_ID_D4:
--		reg = mmFMT4_FMT_CONTROL;
--		break;
--	case CONTROLLER_ID_D5:
--		reg = mmFMT5_FMT_CONTROL;
--		break;
--	default:
--		return result;
--	}
--
--	if (value != NULL)
--		dm_write_reg(ctx, reg, *value);
--	else
--		result = dm_read_reg(ctx, reg);
--
--	return result;
--}
--
--static uint32_t fmt_bit_depth_control(
--	struct dc_context *ctx,
--	enum controller_id id,
--	uint32_t *value)
--{
--	uint32_t addr;
--
--	switch (id) {
--	case CONTROLLER_ID_D0:
--		addr = mmFMT0_FMT_BIT_DEPTH_CONTROL;
--		break;
--	case CONTROLLER_ID_D1:
--		addr = mmFMT1_FMT_BIT_DEPTH_CONTROL;
--		break;
--	case CONTROLLER_ID_D2:
--		addr = mmFMT2_FMT_BIT_DEPTH_CONTROL;
--		break;
--	case CONTROLLER_ID_D3:
--		addr = mmFMT3_FMT_BIT_DEPTH_CONTROL;
--		break;
--	case CONTROLLER_ID_D4:
--		addr = mmFMT4_FMT_BIT_DEPTH_CONTROL;
--		break;
--	case CONTROLLER_ID_D5:
--		addr = mmFMT5_FMT_BIT_DEPTH_CONTROL;
--		break;
--	default:
--		BREAK_TO_DEBUGGER();
--		return 0;
--	}
--
--	if (value != NULL) {
--		dm_write_reg(ctx, addr, *value);
--		return 0;
--	} else {
--		return dm_read_reg(ctx, addr);
--	}
--}
--
--/**
-- * Read various BIOS Scratch registers and put the resulting information into a
-- * PowerPlay internal structure (which is not dependent on register bit layout).
-- */
--static void get_bios_event_info(
--	struct dc_context *ctx,
--	struct bios_event_info *info)
--{
--	uint32_t s2, s6;
--	uint32_t clear_mask;
--
--	memset(info, 0, sizeof(struct bios_event_info));
--
--	/* Handle backlight event ONLY. PPLib still handling other events */
--	s6 = dm_read_reg(ctx, mmBIOS_SCRATCH_6);
--
--	clear_mask = s6 & (ATOM_S6_VRI_BRIGHTNESS_CHANGE);
--
--	dm_write_reg(ctx,
--			mmBIOS_SCRATCH_6, s6 & ~clear_mask);
--
--	s2 = dm_read_reg(ctx, mmBIOS_SCRATCH_2);
--
--	info->backlight_level = (s2 & ATOM_S2_CURRENT_BL_LEVEL_MASK)
--		>> ATOM_S2_CURRENT_BL_LEVEL_SHIFT;
--	info->backlight_changed = (0 != (s6 & ATOM_S6_VRI_BRIGHTNESS_CHANGE));
--}
--
--static void take_backlight_control(
--	struct dc_context *ctx,
--	bool control)
--{
--	const uint32_t addr = mmBIOS_SCRATCH_2;
--
--	uint32_t s2;
--
--	s2 = dm_read_reg(ctx, addr);
--
--	if (control)
--		s2 |= ATOM_S2_VRI_BRIGHT_ENABLE;
--	else
--		s2 &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
--
--	dm_write_reg(ctx, addr, s2);
--}
--
--static uint32_t get_requested_backlight_level(
--	struct dc_context *ctx)
--{
--	uint32_t s2;
--
--	s2 = dm_read_reg(ctx, mmBIOS_SCRATCH_2);
--
--	return (s2 & ATOM_S2_CURRENT_BL_LEVEL_MASK)
--			>> ATOM_S2_CURRENT_BL_LEVEL_SHIFT;
--}
--
--static void update_requested_backlight_level(
--	struct dc_context *ctx,
--	uint32_t backlight_8bit)
--{
--	const uint32_t addr = mmBIOS_SCRATCH_2;
--
--	uint32_t s2;
--
--	s2 = dm_read_reg(ctx, addr);
--
--	s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
--	backlight_8bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK
--			>> ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
--	s2 |= (backlight_8bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
--
--	dm_write_reg(ctx, addr, s2);
--}
--
--static bool is_active_display(
--	struct dc_context *ctx,
--	enum signal_type signal,
--	const struct connector_device_tag_info *dev_tag)
--{
--	uint32_t active = 0;
--
--	uint32_t reg;
--
--	switch (signal) {
--	case SIGNAL_TYPE_DVI_SINGLE_LINK:
--	case SIGNAL_TYPE_DVI_DUAL_LINK:
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--		if (dev_tag->dev_id.device_type == DEVICE_TYPE_DFP) {
--			switch (dev_tag->dev_id.enum_id) {
--			case 1:
--				active = ATOM_S3_DFP1_ACTIVE;
--				break;
--			case 2:
--				active = ATOM_S3_DFP2_ACTIVE;
--				break;
--			case 3:
--				active = ATOM_S3_DFP3_ACTIVE;
--				break;
--			case 4:
--				active = ATOM_S3_DFP4_ACTIVE;
--				break;
--			case 5:
--				active = ATOM_S3_DFP5_ACTIVE;
--				break;
--
--			case 6:
--				active = ATOM_S3_DFP6_ACTIVE;
--				break;
--			default:
--				break;
--			}
--		}
--		break;
--	case SIGNAL_TYPE_LVDS:
--	case SIGNAL_TYPE_EDP:
--		active = ATOM_S3_LCD1_ACTIVE;
--		break;
--	case SIGNAL_TYPE_RGB:
--		if (dev_tag->dev_id.device_type == DEVICE_TYPE_CRT)
--			active = ATOM_S3_CRT1_ACTIVE;
--		break;
--	default:
--		break;
--	}
--
--	reg = dm_read_reg(ctx, mmBIOS_SCRATCH_3);
--	reg &= ATOM_S3_DEVICE_ACTIVE_MASK;
--
--	return 0 != (active & reg);
--}
--
--static enum controller_id get_embedded_display_controller_id(
--	struct dc_context *ctx)
--{
--	uint32_t reg;
--
--	reg = dm_read_reg(ctx, mmBIOS_SCRATCH_3);
--
--	if (ATOM_S3_LCD1_ACTIVE & reg)
--		return (reg & ATOM_S3_LCD1_CRTC_ACTIVE) ?
--			CONTROLLER_ID_D1 : CONTROLLER_ID_D0;
--
--	return CONTROLLER_ID_UNDEFINED;
--}
--
--static uint32_t get_embedded_display_refresh_rate(
--	struct dc_context *ctx)
--{
--	uint32_t result = 0;
--
--	uint32_t reg_3;
--
--	reg_3 = dm_read_reg(ctx, mmBIOS_SCRATCH_3);
--
--	if (ATOM_S3_LCD1_ACTIVE & reg_3) {
--		uint32_t reg_4;
--
--		reg_4 = dm_read_reg(ctx,
--				mmBIOS_SCRATCH_4);
--
--		result = (reg_4 & ATOM_S4_LCD1_REFRESH_MASK)
--				>> ATOM_S4_LCD1_REFRESH_SHIFT;
--	}
--
--	return result;
--}
--
- static const struct bios_parser_helper bios_parser_helper_funcs = {
- 	.detect_sink = detect_sink,
--	.fmt_bit_depth_control = fmt_bit_depth_control,
--	.fmt_control = fmt_control,
--	.get_bios_event_info = get_bios_event_info,
--	.get_embedded_display_controller_id =
--		get_embedded_display_controller_id,
--	.get_embedded_display_refresh_rate =
--		get_embedded_display_refresh_rate,
--	.get_requested_backlight_level = get_requested_backlight_level,
- 	.get_scratch_lcd_scale = get_scratch_lcd_scale,
- 	.is_accelerated_mode = is_accelerated_mode,
--	.is_active_display = is_active_display,
--	.is_display_config_changed = is_display_config_changed,
- 	.is_lid_open = is_lid_open,
- 	.is_lid_status_changed = is_lid_status_changed,
- 	.prepare_scratch_active_and_requested =
- 		prepare_scratch_active_and_requested,
--	.take_backlight_control = take_backlight_control,
--	.update_requested_backlight_level = update_requested_backlight_level,
- };
- 
- const struct bios_parser_helper *dal_bios_parser_helper_dce80_get_table()
-diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-index 73127c4..bd94ecd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
-@@ -127,7 +127,6 @@ bool dc_bios_is_lid_open(struct dc_bios *bios);
- #if 0 /* unused trap to debugger functions */
- 
- bool dc_bios_is_lid_status_changed(struct dc_bios *bios);
--bool dc_bios_is_display_config_changed(struct dc_bios *bios);
- 
- enum lcd_scale  dc_bios_get_scratch_lcd_scale(struct dc_bios *bios);
- void dc_bios_get_bios_event_info(struct dc_bios *bios,
-diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-index a8f313a..a177e15 100644
---- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
-@@ -49,31 +49,7 @@ bool dal_bios_parser_is_lid_open(
- 	struct bios_parser *bp);
- bool dal_bios_parser_is_lid_status_changed(
- 	struct bios_parser *bp);
--bool dal_bios_parser_is_display_config_changed(
--	struct bios_parser *bp);
--void dal_bios_parser_set_scratch_lcd_scale(
--	struct bios_parser *bp,
--	enum lcd_scale scale);
- enum lcd_scale  dal_bios_parser_get_scratch_lcd_scale(
- 	struct bios_parser *bp);
--void dal_bios_parser_get_bios_event_info(
--	struct bios_parser *bp,
--	struct bios_event_info *info);
--void dal_bios_parser_update_requested_backlight_level(
--	struct bios_parser *bp,
--	uint32_t backlight_8bit);
--uint32_t dal_bios_parser_get_requested_backlight_level(
--	struct bios_parser *bp);
--void dal_bios_parser_take_backlight_control(
--	struct bios_parser *bp,
--	bool cntl);
--bool dal_bios_parser_is_active_display(
--	struct bios_parser *bp,
--	enum signal_type signal,
--	const struct connector_device_tag_info *device_tag);
--enum controller_id dal_bios_parser_get_embedded_display_controller_id(
--	struct bios_parser *bp);
--uint32_t dal_bios_parser_get_embedded_display_refresh_rate(
--	struct bios_parser *bp);
- 
- #endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1021-drm-amd-powerplay-add-dpm-force-multiple-levels-on-c.patch b/common/recipes-kernel/linux/files/1021-drm-amd-powerplay-add-dpm-force-multiple-levels-on-c.patch
deleted file mode 100644
index dc389d4e..00000000
--- a/common/recipes-kernel/linux/files/1021-drm-amd-powerplay-add-dpm-force-multiple-levels-on-c.patch
+++ /dev/null
@@ -1,296 +0,0 @@
-From 5eaa9dcb8242c90858a71d144e8c7669e4b38a8b Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Tue, 12 Apr 2016 14:57:23 -0400
-Subject: [PATCH 1021/1110] drm/amd/powerplay: add dpm force multiple levels on
- cz/tonga/fiji/polaris
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c             | 51 +++++++++++++++-------
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  4 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     |  6 +--
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  8 ++--
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  8 ++--
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  8 ++--
- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |  2 +-
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  2 +-
- 8 files changed, 55 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-index 6d44d4a..589b36e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
-@@ -362,16 +362,23 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	int ret;
- 	long level;
-+	uint32_t i, mask = 0;
-+	char sub_str[2];
- 
--	ret = kstrtol(buf, 0, &level);
-+	for (i = 0; i < strlen(buf) - 1; i++) {
-+		sub_str[0] = *(buf + i);
-+		sub_str[1] = '\0';
-+		ret = kstrtol(sub_str, 0, &level);
- 
--	if (ret) {
--		count = -EINVAL;
--		goto fail;
-+		if (ret) {
-+			count = -EINVAL;
-+			goto fail;
-+		}
-+		mask |= 1 << level;
- 	}
- 
- 	if (adev->pp_enabled)
--		amdgpu_dpm_force_clock_level(adev, PP_SCLK, level);
-+		amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
- fail:
- 	return count;
- }
-@@ -399,16 +406,23 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	int ret;
- 	long level;
-+	uint32_t i, mask = 0;
-+	char sub_str[2];
- 
--	ret = kstrtol(buf, 0, &level);
-+	for (i = 0; i < strlen(buf) - 1; i++) {
-+		sub_str[0] = *(buf + i);
-+		sub_str[1] = '\0';
-+		ret = kstrtol(sub_str, 0, &level);
- 
--	if (ret) {
--		count = -EINVAL;
--		goto fail;
-+		if (ret) {
-+			count = -EINVAL;
-+			goto fail;
-+		}
-+		mask |= 1 << level;
- 	}
- 
- 	if (adev->pp_enabled)
--		amdgpu_dpm_force_clock_level(adev, PP_MCLK, level);
-+		amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
- fail:
- 	return count;
- }
-@@ -436,16 +450,23 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	int ret;
- 	long level;
-+	uint32_t i, mask = 0;
-+	char sub_str[2];
- 
--	ret = kstrtol(buf, 0, &level);
-+	for (i = 0; i < strlen(buf) - 1; i++) {
-+		sub_str[0] = *(buf + i);
-+		sub_str[1] = '\0';
-+		ret = kstrtol(sub_str, 0, &level);
- 
--	if (ret) {
--		count = -EINVAL;
--		goto fail;
-+		if (ret) {
-+			count = -EINVAL;
-+			goto fail;
-+		}
-+		mask |= 1 << level;
- 	}
- 
- 	if (adev->pp_enabled)
--		amdgpu_dpm_force_clock_level(adev, PP_PCIE, level);
-+		amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
- fail:
- 	return count;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index ce8d9bf..0527ae3 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -763,7 +763,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
- }
- 
- static int pp_dpm_force_clock_level(void *handle,
--		enum pp_clock_type type, int level)
-+		enum pp_clock_type type, uint32_t mask)
- {
- 	struct pp_hwmgr *hwmgr;
- 
-@@ -779,7 +779,7 @@ static int pp_dpm_force_clock_level(void *handle,
- 		return 0;
- 	}
- 
--	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
-+	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
- }
- 
- static int pp_dpm_print_clock_levels(void *handle,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 648394f..1f14c47 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1729,7 +1729,7 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
- }
- 
- static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
--		enum pp_clock_type type, int level)
-+		enum pp_clock_type type, uint32_t mask)
- {
- 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
- 		return -EINVAL;
-@@ -1738,10 +1738,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
- 	case PP_SCLK:
- 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 				PPSMC_MSG_SetSclkSoftMin,
--				(1 << level));
-+				mask);
- 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 				PPSMC_MSG_SetSclkSoftMax,
--				(1 << level));
-+				mask);
- 		break;
- 	default:
- 		break;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index dc836d3..623ec80 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -5113,7 +5113,7 @@ static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t siz
- }
- 
- static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
--		enum pp_clock_type type, int level)
-+		enum pp_clock_type type, uint32_t mask)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- 
-@@ -5125,19 +5125,19 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
- 		if (!data->sclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					(1 << level));
-+					mask);
- 		break;
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					(1 << level));
-+					mask);
- 		break;
- 	case PP_PCIE:
- 		if (!data->pcie_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
--					(1 << level));
-+					mask);
- 		break;
- 	default:
- 		break;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 2ab3bb2..3e59a87 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -4767,7 +4767,7 @@ static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_
- }
- 
- static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
--		enum pp_clock_type type, int level)
-+		enum pp_clock_type type, uint32_t mask)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- 
-@@ -4779,19 +4779,19 @@ static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
- 		if (!data->sclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					(1 << level));
-+					mask);
- 		break;
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					(1 << level));
-+					mask);
- 		break;
- 	case PP_PCIE:
- 		if (!data->pcie_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
--					(1 << level));
-+					mask);
- 		break;
- 	default:
- 		break;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 0242e34..0d9cf4d 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -6075,7 +6075,7 @@ static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t si
- }
- 
- static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
--		enum pp_clock_type type, int level)
-+		enum pp_clock_type type, uint32_t mask)
- {
- 	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 
-@@ -6087,19 +6087,19 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
- 		if (!data->sclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					(1 << level));
-+					mask);
- 		break;
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					(1 << level));
-+					mask);
- 		break;
- 	case PP_PCIE:
- 		if (!data->pcie_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
--					(1 << level));
-+					mask);
- 		break;
- 	default:
- 		break;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-index e5356cf..546bc0c 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
-@@ -339,7 +339,7 @@ struct amd_powerplay_funcs {
- 	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
- 	int (*get_pp_table)(void *handle, char **table);
- 	int (*set_pp_table)(void *handle, const char *buf, size_t size);
--	int (*force_clock_level)(void *handle, enum pp_clock_type type, int level);
-+	int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
- 	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
- };
- 
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index 12285a9..b1a9ae5 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -335,7 +335,7 @@ struct pp_hwmgr_func {
- 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
- 	int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table);
- 	int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
--	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level);
-+	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
- 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
- 	int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch b/common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch
deleted file mode 100644
index 9f20c469..00000000
--- a/common/recipes-kernel/linux/files/1022-drm-amd-amdgpu-Drop-print_status-callbacks.patch
+++ /dev/null
@@ -1,2641 +0,0 @@
-From c30a6205fb4acb98c44d6529c58c160f77dead49 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Fri, 15 Apr 2016 10:50:50 -0400
-Subject: [PATCH 1022/1110] drm/amd/amdgpu: Drop print_status callbacks.
-
-First patch in series to move to user mode
-debug tools we're removing the print_status callbacks.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c       |   8 -
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  42 -----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  10 -
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c           | 210 ---------------------
- drivers/gpu/drm/amd/amdgpu/cik.c              |   6 -
- drivers/gpu/drm/amd/amdgpu/cik_ih.c           |  34 ----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c         |  56 ------
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c           |   1 -
- drivers/gpu/drm/amd/amdgpu/cz_ih.c            |  34 ----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c        |  12 --
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c        |  12 --
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c         |  12 --
- drivers/gpu/drm/amd/amdgpu/fiji_dpm.c         |   1 -
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         | 253 --------------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 182 ------------------
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c         | 113 ------------
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c         | 110 -----------
- drivers/gpu/drm/amd/amdgpu/iceland_dpm.c      |   1 -
- drivers/gpu/drm/amd/amdgpu/iceland_ih.c       |  34 ----
- drivers/gpu/drm/amd/amdgpu/kv_dpm.c           |  57 ------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c        |  54 ------
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c        |  56 ------
- drivers/gpu/drm/amd/amdgpu/tonga_dpm.c        |   1 -
- drivers/gpu/drm/amd/amdgpu/tonga_ih.c         |  34 ----
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c         | 112 ------------
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c         | 115 ------------
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c         | 107 -----------
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c         |  70 -------
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c         |  68 -------
- drivers/gpu/drm/amd/amdgpu/vi.c               |   6 -
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c |   8 -
- drivers/gpu/drm/amd/include/amd_shared.h      |   2 -
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   5 -
- 33 files changed, 1826 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-index b7b583c..49838df 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -467,13 +467,6 @@ static int acp_soft_reset(void *handle)
- 	return 0;
- }
- 
--static void acp_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "ACP STATUS\n");
--}
--
- static int acp_set_clockgating_state(void *handle,
- 				     enum amd_clockgating_state state)
- {
-@@ -498,7 +491,6 @@ const struct amd_ip_funcs acp_ip_funcs = {
- 	.is_idle = acp_is_idle,
- 	.wait_for_idle = acp_wait_for_idle,
- 	.soft_reset = acp_soft_reset,
--	.print_status = acp_print_status,
- 	.set_clockgating_state = acp_set_clockgating_state,
- 	.set_powergating_state = acp_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 8885e9e..8a5e3f7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -47,8 +47,6 @@
- 
- static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
--static int amdgpu_debugfs_status_init(struct amdgpu_device *adev);
--
- 
- static const char *amdgpu_asic_name[] = {
- 	"BONAIRE",
-@@ -1110,15 +1108,6 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
- 	return NULL;
- }
- 
--void amdgpu_print_status(struct amdgpu_device *adev)
--{
--	int i;
--
--	for (i = 0; i < adev->num_ip_blocks; i++)
--		if (adev->ip_blocks[i].funcs->print_status)
--			adev->ip_blocks[i].funcs->print_status(adev);
--}
--
- /**
-  * amdgpu_ip_block_version_cmp
-  *
-@@ -1269,8 +1258,6 @@ static int amdgpu_init(struct amdgpu_device *adev)
- 		adev->ip_block_status[i].hw = true;
- 	}
- 
--	amdgpu_debugfs_status_init(adev);
--
- 	return 0;
- }
- 
-@@ -2242,32 +2229,3 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
- }
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
- #endif
--
--/*
-- * Status debugfs
-- */
--#if defined(CONFIG_DEBUG_FS)
--static int amdgpu_debugfs_print_status(struct seq_file *m, void *data)
--{
--	struct drm_info_node *node = (struct drm_info_node *)m->private;
--	struct drm_device *dev = node->minor->dev;
--	struct amdgpu_device *adev = dev->dev_private;
--
--	amdgpu_print_status(adev);
--
--	return 0;
--}
--
--static const struct drm_info_list amdgpu_debugfs_status_list[] = {
--	{"amdgpu_print_status", &amdgpu_debugfs_print_status, 0, NULL},
--};
--#endif
--
--static int amdgpu_debugfs_status_init(struct amdgpu_device *adev)
--{
--#if defined(CONFIG_DEBUG_FS)
--	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_status_list, 1);
--#else
--	return 0;
--#endif
--}
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index f315995..be56595 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -303,15 +303,6 @@ static int amdgpu_pp_soft_reset(void *handle)
- 	return ret;
- }
- 
--static void amdgpu_pp_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	if (adev->powerplay.ip_funcs->print_status)
--		adev->powerplay.ip_funcs->print_status(
--					adev->powerplay.pp_handle);
--}
--
- const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
- 	.early_init = amdgpu_pp_early_init,
- 	.late_init = amdgpu_pp_late_init,
-@@ -324,7 +315,6 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
- 	.is_idle = amdgpu_pp_is_idle,
- 	.wait_for_idle = amdgpu_pp_wait_for_idle,
- 	.soft_reset = amdgpu_pp_soft_reset,
--	.print_status = amdgpu_pp_print_status,
- 	.set_clockgating_state = amdgpu_pp_set_clockgating_state,
- 	.set_powergating_state = amdgpu_pp_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 1f9109d..90f83b2 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -6309,215 +6309,6 @@ static int ci_dpm_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void ci_dpm_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "CIK DPM registers\n");
--	dev_info(adev->dev, "  BIOS_SCRATCH_4=0x%08X\n",
--		 RREG32(mmBIOS_SCRATCH_4));
--	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING=0x%08X\n",
--		 RREG32(mmMC_ARB_DRAM_TIMING));
--	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2=0x%08X\n",
--		 RREG32(mmMC_ARB_DRAM_TIMING2));
--	dev_info(adev->dev, "  MC_ARB_BURST_TIME=0x%08X\n",
--		 RREG32(mmMC_ARB_BURST_TIME));
--	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING_1=0x%08X\n",
--		 RREG32(mmMC_ARB_DRAM_TIMING_1));
--	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2_1=0x%08X\n",
--		 RREG32(mmMC_ARB_DRAM_TIMING2_1));
--	dev_info(adev->dev, "  MC_CG_CONFIG=0x%08X\n",
--		 RREG32(mmMC_CG_CONFIG));
--	dev_info(adev->dev, "  MC_ARB_CG=0x%08X\n",
--		 RREG32(mmMC_ARB_CG));
--	dev_info(adev->dev, "  DIDT_SQ_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_SQ_CTRL0));
--	dev_info(adev->dev, "  DIDT_DB_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_DB_CTRL0));
--	dev_info(adev->dev, "  DIDT_TD_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_TD_CTRL0));
--	dev_info(adev->dev, "  DIDT_TCP_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_TCP_CTRL0));
--	dev_info(adev->dev, "  CG_THERMAL_INT=0x%08X\n",
--		 RREG32_SMC(ixCG_THERMAL_INT));
--	dev_info(adev->dev, "  CG_THERMAL_CTRL=0x%08X\n",
--		 RREG32_SMC(ixCG_THERMAL_CTRL));
--	dev_info(adev->dev, "  GENERAL_PWRMGT=0x%08X\n",
--		 RREG32_SMC(ixGENERAL_PWRMGT));
--	dev_info(adev->dev, "  MC_SEQ_CNTL_3=0x%08X\n",
--		 RREG32(mmMC_SEQ_CNTL_3));
--	dev_info(adev->dev, "  LCAC_MC0_CNTL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC0_CNTL));
--	dev_info(adev->dev, "  LCAC_MC1_CNTL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC1_CNTL));
--	dev_info(adev->dev, "  LCAC_CPL_CNTL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_CPL_CNTL));
--	dev_info(adev->dev, "  SCLK_PWRMGT_CNTL=0x%08X\n",
--		 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
--	dev_info(adev->dev, "  BIF_LNCNT_RESET=0x%08X\n",
--		 RREG32(mmBIF_LNCNT_RESET));
--	dev_info(adev->dev, "  FIRMWARE_FLAGS=0x%08X\n",
--		 RREG32_SMC(ixFIRMWARE_FLAGS));
--	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL=0x%08X\n",
--		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
--	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_2=0x%08X\n",
--		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
--	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_3=0x%08X\n",
--		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
--	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_4=0x%08X\n",
--		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
--	dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
--		 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
--	dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
--		 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
--	dev_info(adev->dev, "  DLL_CNTL=0x%08X\n",
--		 RREG32(mmDLL_CNTL));
--	dev_info(adev->dev, "  MCLK_PWRMGT_CNTL=0x%08X\n",
--		 RREG32(mmMCLK_PWRMGT_CNTL));
--	dev_info(adev->dev, "  MPLL_AD_FUNC_CNTL=0x%08X\n",
--		 RREG32(mmMPLL_AD_FUNC_CNTL));
--	dev_info(adev->dev, "  MPLL_DQ_FUNC_CNTL=0x%08X\n",
--		 RREG32(mmMPLL_DQ_FUNC_CNTL));
--	dev_info(adev->dev, "  MPLL_FUNC_CNTL=0x%08X\n",
--		 RREG32(mmMPLL_FUNC_CNTL));
--	dev_info(adev->dev, "  MPLL_FUNC_CNTL_1=0x%08X\n",
--		 RREG32(mmMPLL_FUNC_CNTL_1));
--	dev_info(adev->dev, "  MPLL_FUNC_CNTL_2=0x%08X\n",
--		 RREG32(mmMPLL_FUNC_CNTL_2));
--	dev_info(adev->dev, "  MPLL_SS1=0x%08X\n",
--		 RREG32(mmMPLL_SS1));
--	dev_info(adev->dev, "  MPLL_SS2=0x%08X\n",
--		 RREG32(mmMPLL_SS2));
--	dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL=0x%08X\n",
--		 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
--	dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL2=0x%08X\n",
--		 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
--	dev_info(adev->dev, "  CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
--		 RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_0=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_1=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_2=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_3=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_4=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_5=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_6=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_7=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
--	dev_info(adev->dev, "  RCU_UC_EVENTS=0x%08X\n",
--		 RREG32_SMC(ixRCU_UC_EVENTS));
--	dev_info(adev->dev, "  DPM_TABLE_475=0x%08X\n",
--		 RREG32_SMC(ixDPM_TABLE_475));
--	dev_info(adev->dev, "  MC_SEQ_RAS_TIMING_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_RAS_TIMING_LP));
--	dev_info(adev->dev, "  MC_SEQ_RAS_TIMING=0x%08X\n",
--		 RREG32(mmMC_SEQ_RAS_TIMING));
--	dev_info(adev->dev, "  MC_SEQ_CAS_TIMING_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_CAS_TIMING_LP));
--	dev_info(adev->dev, "  MC_SEQ_CAS_TIMING=0x%08X\n",
--		 RREG32(mmMC_SEQ_CAS_TIMING));
--	dev_info(adev->dev, "  MC_SEQ_DLL_STBY_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_DLL_STBY_LP));
--	dev_info(adev->dev, "  MC_SEQ_DLL_STBY=0x%08X\n",
--		 RREG32(mmMC_SEQ_DLL_STBY));
--	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
--	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0=0x%08X\n",
--		 RREG32(mmMC_SEQ_G5PDX_CMD0));
--	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
--	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1=0x%08X\n",
--		 RREG32(mmMC_SEQ_G5PDX_CMD1));
--	dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
--	dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL=0x%08X\n",
--		 RREG32(mmMC_SEQ_G5PDX_CTRL));
--	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
--	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_DVS_CMD));
--	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
--	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_DVS_CTL));
--	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_MISC_TIMING_LP));
--	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING=0x%08X\n",
--		 RREG32(mmMC_SEQ_MISC_TIMING));
--	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_MISC_TIMING2_LP));
--	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2=0x%08X\n",
--		 RREG32(mmMC_SEQ_MISC_TIMING2));
--	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
--	dev_info(adev->dev, "  MC_PMG_CMD_EMRS=0x%08X\n",
--		 RREG32(mmMC_PMG_CMD_EMRS));
--	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
--	dev_info(adev->dev, "  MC_PMG_CMD_MRS=0x%08X\n",
--		 RREG32(mmMC_PMG_CMD_MRS));
--	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
--	dev_info(adev->dev, "  MC_PMG_CMD_MRS1=0x%08X\n",
--		 RREG32(mmMC_PMG_CMD_MRS1));
--	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_WR_CTL_D0_LP));
--	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0=0x%08X\n",
--		 RREG32(mmMC_SEQ_WR_CTL_D0));
--	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_WR_CTL_D1_LP));
--	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1=0x%08X\n",
--		 RREG32(mmMC_SEQ_WR_CTL_D1));
--	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_RD_CTL_D0_LP));
--	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0=0x%08X\n",
--		 RREG32(mmMC_SEQ_RD_CTL_D0));
--	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_RD_CTL_D1_LP));
--	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1=0x%08X\n",
--		 RREG32(mmMC_SEQ_RD_CTL_D1));
--	dev_info(adev->dev, "  MC_SEQ_PMG_TIMING_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_TIMING_LP));
--	dev_info(adev->dev, "  MC_SEQ_PMG_TIMING=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_TIMING));
--	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
--	dev_info(adev->dev, "  MC_PMG_CMD_MRS2=0x%08X\n",
--		 RREG32(mmMC_PMG_CMD_MRS2));
--	dev_info(adev->dev, "  MC_SEQ_WR_CTL_2_LP=0x%08X\n",
--		 RREG32(mmMC_SEQ_WR_CTL_2_LP));
--	dev_info(adev->dev, "  MC_SEQ_WR_CTL_2=0x%08X\n",
--		 RREG32(mmMC_SEQ_WR_CTL_2));
--	dev_info(adev->dev, "  PCIE_LC_SPEED_CNTL=0x%08X\n",
--		 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
--	dev_info(adev->dev, "  PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
--		 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
--	dev_info(adev->dev, "  SMC_IND_INDEX_0=0x%08X\n",
--		 RREG32(mmSMC_IND_INDEX_0));
--	dev_info(adev->dev, "  SMC_IND_DATA_0=0x%08X\n",
--		 RREG32(mmSMC_IND_DATA_0));
--	dev_info(adev->dev, "  SMC_IND_ACCESS_CNTL=0x%08X\n",
--		 RREG32(mmSMC_IND_ACCESS_CNTL));
--	dev_info(adev->dev, "  SMC_RESP_0=0x%08X\n",
--		 RREG32(mmSMC_RESP_0));
--	dev_info(adev->dev, "  SMC_MESSAGE_0=0x%08X\n",
--		 RREG32(mmSMC_MESSAGE_0));
--	dev_info(adev->dev, "  SMC_SYSCON_RESET_CNTL=0x%08X\n",
--		 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
--	dev_info(adev->dev, "  SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
--		 RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
--	dev_info(adev->dev, "  SMC_SYSCON_MISC_CNTL=0x%08X\n",
--		 RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
--	dev_info(adev->dev, "  SMC_PC_C=0x%08X\n",
--		 RREG32_SMC(ixSMC_PC_C));
--}
--
- static int ci_dpm_soft_reset(void *handle)
- {
- 	return 0;
-@@ -6625,7 +6416,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = {
- 	.is_idle = ci_dpm_is_idle,
- 	.wait_for_idle = ci_dpm_wait_for_idle,
- 	.soft_reset = ci_dpm_soft_reset,
--	.print_status = ci_dpm_print_status,
- 	.set_clockgating_state = ci_dpm_set_clockgating_state,
- 	.set_powergating_state = ci_dpm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 14a1411..e86afec 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -2375,11 +2375,6 @@ static int cik_common_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void cik_common_print_status(void *handle)
--{
--
--}
--
- static int cik_common_soft_reset(void *handle)
- {
- 	/* XXX hard reset?? */
-@@ -2410,7 +2405,6 @@ const struct amd_ip_funcs cik_common_ip_funcs = {
- 	.is_idle = cik_common_is_idle,
- 	.wait_for_idle = cik_common_wait_for_idle,
- 	.soft_reset = cik_common_soft_reset,
--	.print_status = cik_common_print_status,
- 	.set_clockgating_state = cik_common_set_clockgating_state,
- 	.set_powergating_state = cik_common_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-index 30c9b3b..f2f14fe 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-@@ -372,35 +372,6 @@ static int cik_ih_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void cik_ih_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "CIK IH registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL));
--	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL2));
--	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
--		 RREG32(mmIH_CNTL));
--	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
--		 RREG32(mmIH_RB_CNTL));
--	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
--		 RREG32(mmIH_RB_BASE));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_LO));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_HI));
--	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
--		 RREG32(mmIH_RB_RPTR));
--	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR));
--}
--
- static int cik_ih_soft_reset(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -412,8 +383,6 @@ static int cik_ih_soft_reset(void *handle)
- 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
- 
- 	if (srbm_soft_reset) {
--		cik_ih_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -428,8 +397,6 @@ static int cik_ih_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		cik_ih_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -459,7 +426,6 @@ const struct amd_ip_funcs cik_ih_ip_funcs = {
- 	.is_idle = cik_ih_is_idle,
- 	.wait_for_idle = cik_ih_wait_for_idle,
- 	.soft_reset = cik_ih_soft_reset,
--	.print_status = cik_ih_print_status,
- 	.set_clockgating_state = cik_ih_set_clockgating_state,
- 	.set_powergating_state = cik_ih_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 7e28b1c..1ae79fc 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -1064,57 +1064,6 @@ static int cik_sdma_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void cik_sdma_print_status(void *handle)
--{
--	int i, j;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "CIK SDMA registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		 RREG32(mmSRBM_STATUS2));
--	for (i = 0; i < adev->sdma.num_instances; i++) {
--		dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
--			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
--			 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
--		mutex_lock(&adev->srbm_mutex);
--		for (j = 0; j < 16; j++) {
--			cik_srbm_select(adev, 0, 0, 0, j);
--			dev_info(adev->dev, "  VM %d:\n", j);
--			dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
--				 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
--			dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
--				 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
--		}
--		cik_srbm_select(adev, 0, 0, 0, 0);
--		mutex_unlock(&adev->srbm_mutex);
--	}
--}
--
- static int cik_sdma_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0;
-@@ -1137,8 +1086,6 @@ static int cik_sdma_soft_reset(void *handle)
- 	}
- 
- 	if (srbm_soft_reset) {
--		cik_sdma_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -1153,8 +1100,6 @@ static int cik_sdma_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		cik_sdma_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -1289,7 +1234,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = {
- 	.is_idle = cik_sdma_is_idle,
- 	.wait_for_idle = cik_sdma_wait_for_idle,
- 	.soft_reset = cik_sdma_soft_reset,
--	.print_status = cik_sdma_print_status,
- 	.set_clockgating_state = cik_sdma_set_clockgating_state,
- 	.set_powergating_state = cik_sdma_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index e7ef226..bf1847b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -2241,7 +2241,6 @@ const struct amd_ip_funcs cz_dpm_ip_funcs = {
- 	.is_idle = NULL,
- 	.wait_for_idle = NULL,
- 	.soft_reset = NULL,
--	.print_status = NULL,
- 	.set_clockgating_state = cz_dpm_set_clockgating_state,
- 	.set_powergating_state = cz_dpm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-index c79638f..23bd912 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-@@ -351,35 +351,6 @@ static int cz_ih_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void cz_ih_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "CZ IH registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL));
--	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL2));
--	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
--		 RREG32(mmIH_CNTL));
--	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
--		 RREG32(mmIH_RB_CNTL));
--	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
--		 RREG32(mmIH_RB_BASE));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_LO));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_HI));
--	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
--		 RREG32(mmIH_RB_RPTR));
--	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR));
--}
--
- static int cz_ih_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0;
-@@ -391,8 +362,6 @@ static int cz_ih_soft_reset(void *handle)
- 						SOFT_RESET_IH, 1);
- 
- 	if (srbm_soft_reset) {
--		cz_ih_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -407,8 +376,6 @@ static int cz_ih_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		cz_ih_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -440,7 +407,6 @@ const struct amd_ip_funcs cz_ih_ip_funcs = {
- 	.is_idle = cz_ih_is_idle,
- 	.wait_for_idle = cz_ih_wait_for_idle,
- 	.soft_reset = cz_ih_soft_reset,
--	.print_status = cz_ih_print_status,
- 	.set_clockgating_state = cz_ih_set_clockgating_state,
- 	.set_powergating_state = cz_ih_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 2445c01..609aa36 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -3130,14 +3130,6 @@ static int dce_v10_0_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void dce_v10_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "DCE 10.x registers\n");
--	/* XXX todo */
--}
--
- static int dce_v10_0_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0, tmp;
-@@ -3147,8 +3139,6 @@ static int dce_v10_0_soft_reset(void *handle)
- 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
- 
- 	if (srbm_soft_reset) {
--		dce_v10_0_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -3163,7 +3153,6 @@ static int dce_v10_0_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--		dce_v10_0_print_status((void *)adev);
- 	}
- 	return 0;
- }
-@@ -3512,7 +3501,6 @@ const struct amd_ip_funcs dce_v10_0_ip_funcs = {
- 	.is_idle = dce_v10_0_is_idle,
- 	.wait_for_idle = dce_v10_0_wait_for_idle,
- 	.soft_reset = dce_v10_0_soft_reset,
--	.print_status = dce_v10_0_print_status,
- 	.set_clockgating_state = dce_v10_0_set_clockgating_state,
- 	.set_powergating_state = dce_v10_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index e47b252..22c6250 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -3166,14 +3166,6 @@ static int dce_v11_0_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void dce_v11_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "DCE 10.x registers\n");
--	/* XXX todo */
--}
--
- static int dce_v11_0_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0, tmp;
-@@ -3183,8 +3175,6 @@ static int dce_v11_0_soft_reset(void *handle)
- 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
- 
- 	if (srbm_soft_reset) {
--		dce_v11_0_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -3199,7 +3189,6 @@ static int dce_v11_0_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--		dce_v11_0_print_status((void *)adev);
- 	}
- 	return 0;
- }
-@@ -3548,7 +3537,6 @@ const struct amd_ip_funcs dce_v11_0_ip_funcs = {
- 	.is_idle = dce_v11_0_is_idle,
- 	.wait_for_idle = dce_v11_0_wait_for_idle,
- 	.soft_reset = dce_v11_0_soft_reset,
--	.print_status = dce_v11_0_print_status,
- 	.set_clockgating_state = dce_v11_0_set_clockgating_state,
- 	.set_powergating_state = dce_v11_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index a42148f..2626c7e 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -3038,14 +3038,6 @@ static int dce_v8_0_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void dce_v8_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "DCE 8.x registers\n");
--	/* XXX todo */
--}
--
- static int dce_v8_0_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0, tmp;
-@@ -3055,8 +3047,6 @@ static int dce_v8_0_soft_reset(void *handle)
- 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
- 
- 	if (srbm_soft_reset) {
--		dce_v8_0_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -3071,7 +3061,6 @@ static int dce_v8_0_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--		dce_v8_0_print_status((void *)adev);
- 	}
- 	return 0;
- }
-@@ -3442,7 +3431,6 @@ const struct amd_ip_funcs dce_v8_0_ip_funcs = {
- 	.is_idle = dce_v8_0_is_idle,
- 	.wait_for_idle = dce_v8_0_wait_for_idle,
- 	.soft_reset = dce_v8_0_soft_reset,
--	.print_status = dce_v8_0_print_status,
- 	.set_clockgating_state = dce_v8_0_set_clockgating_state,
- 	.set_powergating_state = dce_v8_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-index 4b0e45a..6d13345 100644
---- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-@@ -154,7 +154,6 @@ const struct amd_ip_funcs fiji_dpm_ip_funcs = {
- 	.is_idle = NULL,
- 	.wait_for_idle = NULL,
- 	.soft_reset = NULL,
--	.print_status = NULL,
- 	.set_clockgating_state = fiji_dpm_set_clockgating_state,
- 	.set_powergating_state = fiji_dpm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 19b07a8..f1842f9 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4572,256 +4572,6 @@ static int gfx_v7_0_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void gfx_v7_0_print_status(void *handle)
--{
--	int i;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "GFX 7.x registers\n");
--	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
--		RREG32(mmGRBM_STATUS));
--	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
--		RREG32(mmGRBM_STATUS2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE0));
--	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE1));
--	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
--		RREG32(mmGRBM_STATUS_SE3));
--	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
--	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT2));
--	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT3));
--	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
--		 RREG32(mmCP_CPF_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPF_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
--	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPC_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
--
--	for (i = 0; i < 32; i++) {
--		dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
--			 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
--	}
--	for (i = 0; i < 16; i++) {
--		dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
--			 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
--	}
--	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
--		dev_info(adev->dev, "  se: %d\n", i);
--		gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
--		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
--			 RREG32(mmPA_SC_RASTER_CONFIG));
--		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
--			 RREG32(mmPA_SC_RASTER_CONFIG_1));
--	}
--	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
--
--	dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmGB_ADDR_CONFIG));
--	dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmHDP_ADDR_CONFIG));
--	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
--		 RREG32(mmDMIF_ADDR_CALC));
--
--	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
--		 RREG32(mmCP_MEQ_THRESHOLDS));
--	dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
--		 RREG32(mmSX_DEBUG_1));
--	dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
--		 RREG32(mmTA_CNTL_AUX));
--	dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
--		 RREG32(mmSPI_CONFIG_CNTL));
--	dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
--		 RREG32(mmSQ_CONFIG));
--	dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
--		 RREG32(mmDB_DEBUG));
--	dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
--		 RREG32(mmDB_DEBUG2));
--	dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
--		 RREG32(mmDB_DEBUG3));
--	dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
--		 RREG32(mmCB_HW_CONTROL));
--	dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
--		 RREG32(mmSPI_CONFIG_CNTL_1));
--	dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
--		 RREG32(mmPA_SC_FIFO_SIZE));
--	dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
--		 RREG32(mmVGT_NUM_INSTANCES));
--	dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
--		 RREG32(mmCP_PERFMON_CNTL));
--	dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
--		 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
--	dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
--		 RREG32(mmVGT_CACHE_INVALIDATION));
--	dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
--		 RREG32(mmVGT_GS_VERTEX_REUSE));
--	dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
--		 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
--	dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
--		 RREG32(mmPA_CL_ENHANCE));
--	dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
--		 RREG32(mmPA_SC_ENHANCE));
--
--	dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
--		 RREG32(mmCP_ME_CNTL));
--	dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
--		 RREG32(mmCP_MAX_CONTEXT));
--	dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
--		 RREG32(mmCP_ENDIAN_SWAP));
--	dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
--		 RREG32(mmCP_DEVICE_ID));
--
--	dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
--		 RREG32(mmCP_SEM_WAIT_TIMER));
--	if (adev->asic_type != CHIP_HAWAII)
--		dev_info(adev->dev, "  CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
--			 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
--
--	dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
--		 RREG32(mmCP_RB_WPTR_DELAY));
--	dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
--		 RREG32(mmCP_RB_VMID));
--	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
--		 RREG32(mmCP_RB0_CNTL));
--	dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
--		 RREG32(mmCP_RB0_WPTR));
--	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
--		 RREG32(mmCP_RB0_RPTR_ADDR));
--	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
--		 RREG32(mmCP_RB0_RPTR_ADDR_HI));
--	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
--		 RREG32(mmCP_RB0_CNTL));
--	dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
--		 RREG32(mmCP_RB0_BASE));
--	dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
--		 RREG32(mmCP_RB0_BASE_HI));
--	dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
--		 RREG32(mmCP_MEC_CNTL));
--	dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
--		 RREG32(mmCP_CPF_DEBUG));
--
--	dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
--		 RREG32(mmSCRATCH_ADDR));
--	dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
--		 RREG32(mmSCRATCH_UMSK));
--
--	/* init the pipes */
--	mutex_lock(&adev->srbm_mutex);
--	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
--		int me = (i < 4) ? 1 : 2;
--		int pipe = (i < 4) ? i : (i - 4);
--		int queue;
--
--		dev_info(adev->dev, "  me: %d, pipe: %d\n", me, pipe);
--		cik_srbm_select(adev, me, pipe, 0, 0);
--		dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR=0x%08X\n",
--			 RREG32(mmCP_HPD_EOP_BASE_ADDR));
--		dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
--			 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
--		dev_info(adev->dev, "  CP_HPD_EOP_VMID=0x%08X\n",
--			 RREG32(mmCP_HPD_EOP_VMID));
--		dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",
--			 RREG32(mmCP_HPD_EOP_CONTROL));
--
--		for (queue = 0; queue < 8; queue++) {
--			cik_srbm_select(adev, me, pipe, queue, 0);
--			dev_info(adev->dev, "  queue: %d\n", queue);
--			dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
--				 RREG32(mmCP_PQ_WPTR_POLL_CNTL));
--			dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
--			dev_info(adev->dev, "  CP_HQD_ACTIVE=0x%08X\n",
--				 RREG32(mmCP_HQD_ACTIVE));
--			dev_info(adev->dev, "  CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
--				 RREG32(mmCP_HQD_DEQUEUE_REQUEST));
--			dev_info(adev->dev, "  CP_HQD_PQ_RPTR=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_RPTR));
--			dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_WPTR));
--			dev_info(adev->dev, "  CP_HQD_PQ_BASE=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_BASE));
--			dev_info(adev->dev, "  CP_HQD_PQ_BASE_HI=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_BASE_HI));
--			dev_info(adev->dev, "  CP_HQD_PQ_CONTROL=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_CONTROL));
--			dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
--			dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
--			dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
--			dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
--			dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
--			dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
--				 RREG32(mmCP_HQD_PQ_WPTR));
--			dev_info(adev->dev, "  CP_HQD_VMID=0x%08X\n",
--				 RREG32(mmCP_HQD_VMID));
--			dev_info(adev->dev, "  CP_MQD_BASE_ADDR=0x%08X\n",
--				 RREG32(mmCP_MQD_BASE_ADDR));
--			dev_info(adev->dev, "  CP_MQD_BASE_ADDR_HI=0x%08X\n",
--				 RREG32(mmCP_MQD_BASE_ADDR_HI));
--			dev_info(adev->dev, "  CP_MQD_CONTROL=0x%08X\n",
--				 RREG32(mmCP_MQD_CONTROL));
--		}
--	}
--	cik_srbm_select(adev, 0, 0, 0, 0);
--	mutex_unlock(&adev->srbm_mutex);
--
--	dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
--		 RREG32(mmCP_INT_CNTL_RING0));
--	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTL));
--	dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
--		 RREG32(mmRLC_CNTL));
--	dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
--		 RREG32(mmRLC_CGCG_CGLS_CTRL));
--	dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTR_INIT));
--	dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTR_MAX));
--	dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
--		 RREG32(mmRLC_LB_INIT_CU_MASK));
--	dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
--		 RREG32(mmRLC_LB_PARAMS));
--	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTL));
--	dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
--		 RREG32(mmRLC_MC_CNTL));
--	dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
--		 RREG32(mmRLC_UCODE_CNTL));
--
--	if (adev->asic_type == CHIP_BONAIRE)
--		dev_info(adev->dev, "  RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
--			 RREG32(mmRLC_DRIVER_CPDMA_STATUS));
--
--	mutex_lock(&adev->srbm_mutex);
--	for (i = 0; i < 16; i++) {
--		cik_srbm_select(adev, 0, 0, 0, i);
--		dev_info(adev->dev, "  VM %d:\n", i);
--		dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
--			 RREG32(mmSH_MEM_CONFIG));
--		dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
--			 RREG32(mmSH_MEM_APE1_BASE));
--		dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
--			 RREG32(mmSH_MEM_APE1_LIMIT));
--		dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
--			 RREG32(mmSH_MEM_BASES));
--	}
--	cik_srbm_select(adev, 0, 0, 0, 0);
--	mutex_unlock(&adev->srbm_mutex);
--}
--
- static int gfx_v7_0_soft_reset(void *handle)
- {
- 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
-@@ -4855,7 +4605,6 @@ static int gfx_v7_0_soft_reset(void *handle)
- 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
- 
- 	if (grbm_soft_reset || srbm_soft_reset) {
--		gfx_v7_0_print_status((void *)adev);
- 		/* disable CG/PG */
- 		gfx_v7_0_fini_pg(adev);
- 		gfx_v7_0_update_cg(adev, false);
-@@ -4898,7 +4647,6 @@ static int gfx_v7_0_soft_reset(void *handle)
- 		}
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--		gfx_v7_0_print_status((void *)adev);
- 	}
- 	return 0;
- }
-@@ -5161,7 +4909,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
- 	.is_idle = gfx_v7_0_is_idle,
- 	.wait_for_idle = gfx_v7_0_wait_for_idle,
- 	.soft_reset = gfx_v7_0_soft_reset,
--	.print_status = gfx_v7_0_print_status,
- 	.set_clockgating_state = gfx_v7_0_set_clockgating_state,
- 	.set_powergating_state = gfx_v7_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d0ec83f..dffa413 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -4826,185 +4826,6 @@ static int gfx_v8_0_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void gfx_v8_0_print_status(void *handle)
--{
--	int i;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "GFX 8.x registers\n");
--	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
--		 RREG32(mmGRBM_STATUS));
--	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
--		 RREG32(mmGRBM_STATUS2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
--		 RREG32(mmGRBM_STATUS_SE0));
--	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
--		 RREG32(mmGRBM_STATUS_SE1));
--	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
--		 RREG32(mmGRBM_STATUS_SE2));
--	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
--		 RREG32(mmGRBM_STATUS_SE3));
--	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
--	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT2));
--	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
--		 RREG32(mmCP_STALLED_STAT3));
--	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
--		 RREG32(mmCP_CPF_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPF_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
--	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
--	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
--		 RREG32(mmCP_CPC_STALLED_STAT1));
--	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
--
--	for (i = 0; i < 32; i++) {
--		dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
--			 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
--	}
--	for (i = 0; i < 16; i++) {
--		dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
--			 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
--	}
--	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
--		dev_info(adev->dev, "  se: %d\n", i);
--		gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
--		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
--			 RREG32(mmPA_SC_RASTER_CONFIG));
--		dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
--			 RREG32(mmPA_SC_RASTER_CONFIG_1));
--	}
--	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
--
--	dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmGB_ADDR_CONFIG));
--	dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmHDP_ADDR_CONFIG));
--	dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
--		 RREG32(mmDMIF_ADDR_CALC));
--
--	dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
--		 RREG32(mmCP_MEQ_THRESHOLDS));
--	dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
--		 RREG32(mmSX_DEBUG_1));
--	dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
--		 RREG32(mmTA_CNTL_AUX));
--	dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
--		 RREG32(mmSPI_CONFIG_CNTL));
--	dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
--		 RREG32(mmSQ_CONFIG));
--	dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
--		 RREG32(mmDB_DEBUG));
--	dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
--		 RREG32(mmDB_DEBUG2));
--	dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
--		 RREG32(mmDB_DEBUG3));
--	dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
--		 RREG32(mmCB_HW_CONTROL));
--	dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
--		 RREG32(mmSPI_CONFIG_CNTL_1));
--	dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
--		 RREG32(mmPA_SC_FIFO_SIZE));
--	dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
--		 RREG32(mmVGT_NUM_INSTANCES));
--	dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
--		 RREG32(mmCP_PERFMON_CNTL));
--	dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
--		 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
--	dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
--		 RREG32(mmVGT_CACHE_INVALIDATION));
--	dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
--		 RREG32(mmVGT_GS_VERTEX_REUSE));
--	dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
--		 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
--	dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
--		 RREG32(mmPA_CL_ENHANCE));
--	dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
--		 RREG32(mmPA_SC_ENHANCE));
--
--	dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
--		 RREG32(mmCP_ME_CNTL));
--	dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
--		 RREG32(mmCP_MAX_CONTEXT));
--	dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
--		 RREG32(mmCP_ENDIAN_SWAP));
--	dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
--		 RREG32(mmCP_DEVICE_ID));
--
--	dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
--		 RREG32(mmCP_SEM_WAIT_TIMER));
--
--	dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
--		 RREG32(mmCP_RB_WPTR_DELAY));
--	dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
--		 RREG32(mmCP_RB_VMID));
--	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
--		 RREG32(mmCP_RB0_CNTL));
--	dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
--		 RREG32(mmCP_RB0_WPTR));
--	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
--		 RREG32(mmCP_RB0_RPTR_ADDR));
--	dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
--		 RREG32(mmCP_RB0_RPTR_ADDR_HI));
--	dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
--		 RREG32(mmCP_RB0_CNTL));
--	dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
--		 RREG32(mmCP_RB0_BASE));
--	dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
--		 RREG32(mmCP_RB0_BASE_HI));
--	dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
--		 RREG32(mmCP_MEC_CNTL));
--	dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
--		 RREG32(mmCP_CPF_DEBUG));
--
--	dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
--		 RREG32(mmSCRATCH_ADDR));
--	dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
--		 RREG32(mmSCRATCH_UMSK));
--
--	dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
--		 RREG32(mmCP_INT_CNTL_RING0));
--	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTL));
--	dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
--		 RREG32(mmRLC_CNTL));
--	dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
--		 RREG32(mmRLC_CGCG_CGLS_CTRL));
--	dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTR_INIT));
--	dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTR_MAX));
--	dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
--		 RREG32(mmRLC_LB_INIT_CU_MASK));
--	dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
--		 RREG32(mmRLC_LB_PARAMS));
--	dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
--		 RREG32(mmRLC_LB_CNTL));
--	dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
--		 RREG32(mmRLC_MC_CNTL));
--	dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
--		 RREG32(mmRLC_UCODE_CNTL));
--
--	mutex_lock(&adev->srbm_mutex);
--	for (i = 0; i < 16; i++) {
--		vi_srbm_select(adev, 0, 0, 0, i);
--		dev_info(adev->dev, "  VM %d:\n", i);
--		dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
--			 RREG32(mmSH_MEM_CONFIG));
--		dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
--			 RREG32(mmSH_MEM_APE1_BASE));
--		dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
--			 RREG32(mmSH_MEM_APE1_LIMIT));
--		dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
--			 RREG32(mmSH_MEM_BASES));
--	}
--	vi_srbm_select(adev, 0, 0, 0, 0);
--	mutex_unlock(&adev->srbm_mutex);
--}
--
- static int gfx_v8_0_soft_reset(void *handle)
- {
- 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
-@@ -5045,7 +4866,6 @@ static int gfx_v8_0_soft_reset(void *handle)
- 						SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
- 
- 	if (grbm_soft_reset || srbm_soft_reset) {
--		gfx_v8_0_print_status((void *)adev);
- 		/* stop the rlc */
- 		gfx_v8_0_rlc_stop(adev);
- 
-@@ -5105,7 +4925,6 @@ static int gfx_v8_0_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--		gfx_v8_0_print_status((void *)adev);
- 	}
- 	return 0;
- }
-@@ -6256,7 +6075,6 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
- 	.is_idle = gfx_v8_0_is_idle,
- 	.wait_for_idle = gfx_v8_0_wait_for_idle,
- 	.soft_reset = gfx_v8_0_soft_reset,
--	.print_status = gfx_v8_0_print_status,
- 	.set_clockgating_state = gfx_v8_0_set_clockgating_state,
- 	.set_powergating_state = gfx_v8_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index 09829f1..2037218 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -1114,114 +1114,6 @@ static int gmc_v7_0_wait_for_idle(void *handle)
- 
- }
- 
--static void gmc_v7_0_print_status(void *handle)
--{
--	int i, j;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "GMC 8.x registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
--	dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
--		 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
--	dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL));
--	dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL2));
--	dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL3));
--	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_CNTL2));
--	dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_CNTL));
--	dev_info(adev->dev, "  0x15D4=0x%08X\n",
--		 RREG32(0x575));
--	dev_info(adev->dev, "  0x15D8=0x%08X\n",
--		 RREG32(0x576));
--	dev_info(adev->dev, "  0x15DC=0x%08X\n",
--		 RREG32(0x577));
--	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_CNTL2));
--	dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_CNTL));
--	for (i = 0; i < 16; i++) {
--		if (i < 8)
--			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
--				 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
--		else
--			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
--				 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
--	}
--	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
--		 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
--	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
--		 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
--	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
--		 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
--	dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
--		 RREG32(mmMC_VM_FB_LOCATION));
--	dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
--		 RREG32(mmMC_VM_AGP_BASE));
--	dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
--		 RREG32(mmMC_VM_AGP_TOP));
--	dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
--		 RREG32(mmMC_VM_AGP_BOT));
--
--	if (adev->asic_type == CHIP_KAVERI) {
--		dev_info(adev->dev, "  CHUB_CONTROL=0x%08X\n",
--			 RREG32(mmCHUB_CONTROL));
--	}
--
--	dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
--		 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
--	dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
--		 RREG32(mmHDP_NONSURFACE_BASE));
--	dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
--		 RREG32(mmHDP_NONSURFACE_INFO));
--	dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
--		 RREG32(mmHDP_NONSURFACE_SIZE));
--	dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
--		 RREG32(mmHDP_MISC_CNTL));
--	dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
--		 RREG32(mmHDP_HOST_PATH_CNTL));
--
--	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
--		dev_info(adev->dev, "  %d:\n", i);
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb05 + j, RREG32(0xb05 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb06 + j, RREG32(0xb06 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb07 + j, RREG32(0xb07 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb08 + j, RREG32(0xb08 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb09 + j, RREG32(0xb09 + j));
--	}
--
--	dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
--		 RREG32(mmBIF_FB_EN));
--}
--
- static int gmc_v7_0_soft_reset(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -1241,8 +1133,6 @@ static int gmc_v7_0_soft_reset(void *handle)
- 	}
- 
- 	if (srbm_soft_reset) {
--		gmc_v7_0_print_status((void *)adev);
--
- 		gmc_v7_0_mc_stop(adev, &save);
- 		if (gmc_v7_0_wait_for_idle(adev)) {
- 			dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
-@@ -1266,8 +1156,6 @@ static int gmc_v7_0_soft_reset(void *handle)
- 
- 		gmc_v7_0_mc_resume(adev, &save);
- 		udelay(50);
--
--		gmc_v7_0_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -1381,7 +1269,6 @@ const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
- 	.is_idle = gmc_v7_0_is_idle,
- 	.wait_for_idle = gmc_v7_0_wait_for_idle,
- 	.soft_reset = gmc_v7_0_soft_reset,
--	.print_status = gmc_v7_0_print_status,
- 	.set_clockgating_state = gmc_v7_0_set_clockgating_state,
- 	.set_powergating_state = gmc_v7_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index f5efc67..aeb753e 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -1117,111 +1117,6 @@ static int gmc_v8_0_wait_for_idle(void *handle)
- 
- }
- 
--static void gmc_v8_0_print_status(void *handle)
--{
--	int i, j;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "GMC 8.x registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
--	dev_info(adev->dev, "  MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
--		 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
--	dev_info(adev->dev, "  VM_L2_CNTL=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL));
--	dev_info(adev->dev, "  VM_L2_CNTL2=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL2));
--	dev_info(adev->dev, "  VM_L2_CNTL3=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL3));
--	dev_info(adev->dev, "  VM_L2_CNTL4=0x%08X\n",
--		 RREG32(mmVM_L2_CNTL4));
--	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT0_CNTL2=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_CNTL2));
--	dev_info(adev->dev, "  VM_CONTEXT0_CNTL=0x%08X\n",
--		 RREG32(mmVM_CONTEXT0_CNTL));
--	dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
--		 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
--	dev_info(adev->dev, "  VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
--		 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
--	dev_info(adev->dev, "  mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
--		 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
--	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
--	dev_info(adev->dev, "  VM_CONTEXT1_CNTL2=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_CNTL2));
--	dev_info(adev->dev, "  VM_CONTEXT1_CNTL=0x%08X\n",
--		 RREG32(mmVM_CONTEXT1_CNTL));
--	for (i = 0; i < 16; i++) {
--		if (i < 8)
--			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
--				 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
--		else
--			dev_info(adev->dev, "  VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
--				 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
--	}
--	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
--		 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
--	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
--		 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
--	dev_info(adev->dev, "  MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
--		 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
--	dev_info(adev->dev, "  MC_VM_FB_LOCATION=0x%08X\n",
--		 RREG32(mmMC_VM_FB_LOCATION));
--	dev_info(adev->dev, "  MC_VM_AGP_BASE=0x%08X\n",
--		 RREG32(mmMC_VM_AGP_BASE));
--	dev_info(adev->dev, "  MC_VM_AGP_TOP=0x%08X\n",
--		 RREG32(mmMC_VM_AGP_TOP));
--	dev_info(adev->dev, "  MC_VM_AGP_BOT=0x%08X\n",
--		 RREG32(mmMC_VM_AGP_BOT));
--
--	dev_info(adev->dev, "  HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
--		 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
--	dev_info(adev->dev, "  HDP_NONSURFACE_BASE=0x%08X\n",
--		 RREG32(mmHDP_NONSURFACE_BASE));
--	dev_info(adev->dev, "  HDP_NONSURFACE_INFO=0x%08X\n",
--		 RREG32(mmHDP_NONSURFACE_INFO));
--	dev_info(adev->dev, "  HDP_NONSURFACE_SIZE=0x%08X\n",
--		 RREG32(mmHDP_NONSURFACE_SIZE));
--	dev_info(adev->dev, "  HDP_MISC_CNTL=0x%08X\n",
--		 RREG32(mmHDP_MISC_CNTL));
--	dev_info(adev->dev, "  HDP_HOST_PATH_CNTL=0x%08X\n",
--		 RREG32(mmHDP_HOST_PATH_CNTL));
--
--	for (i = 0, j = 0; i < 32; i++, j += 0x6) {
--		dev_info(adev->dev, "  %d:\n", i);
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb05 + j, RREG32(0xb05 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb06 + j, RREG32(0xb06 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb07 + j, RREG32(0xb07 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb08 + j, RREG32(0xb08 + j));
--		dev_info(adev->dev, "  0x%04X=0x%08X\n",
--			 0xb09 + j, RREG32(0xb09 + j));
--	}
--
--	dev_info(adev->dev, "  BIF_FB_EN=0x%08X\n",
--		 RREG32(mmBIF_FB_EN));
--}
--
- static int gmc_v8_0_soft_reset(void *handle)
- {
- 	struct amdgpu_mode_mc_save save;
-@@ -1241,8 +1136,6 @@ static int gmc_v8_0_soft_reset(void *handle)
- 	}
- 
- 	if (srbm_soft_reset) {
--		gmc_v8_0_print_status((void *)adev);
--
- 		gmc_v8_0_mc_stop(adev, &save);
- 		if (gmc_v8_0_wait_for_idle(adev)) {
- 			dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
-@@ -1266,8 +1159,6 @@ static int gmc_v8_0_soft_reset(void *handle)
- 
- 		gmc_v8_0_mc_resume(adev, &save);
- 		udelay(50);
--
--		gmc_v8_0_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -1540,7 +1431,6 @@ const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
- 	.is_idle = gmc_v8_0_is_idle,
- 	.wait_for_idle = gmc_v8_0_wait_for_idle,
- 	.soft_reset = gmc_v8_0_soft_reset,
--	.print_status = gmc_v8_0_print_status,
- 	.set_clockgating_state = gmc_v8_0_set_clockgating_state,
- 	.set_powergating_state = gmc_v8_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
-index 208d55f..57a9613 100644
---- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
-@@ -168,7 +168,6 @@ const struct amd_ip_funcs iceland_dpm_ip_funcs = {
- 	.is_idle = NULL,
- 	.wait_for_idle = NULL,
- 	.soft_reset = NULL,
--	.print_status = NULL,
- 	.set_clockgating_state = iceland_dpm_set_clockgating_state,
- 	.set_powergating_state = iceland_dpm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-index 679e739..5c4001e 100644
---- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-@@ -351,35 +351,6 @@ static int iceland_ih_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void iceland_ih_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "ICELAND IH registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL));
--	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL2));
--	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
--		 RREG32(mmIH_CNTL));
--	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
--		 RREG32(mmIH_RB_CNTL));
--	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
--		 RREG32(mmIH_RB_BASE));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_LO));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_HI));
--	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
--		 RREG32(mmIH_RB_RPTR));
--	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR));
--}
--
- static int iceland_ih_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0;
-@@ -391,8 +362,6 @@ static int iceland_ih_soft_reset(void *handle)
- 						SOFT_RESET_IH, 1);
- 
- 	if (srbm_soft_reset) {
--		iceland_ih_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -407,8 +376,6 @@ static int iceland_ih_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		iceland_ih_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -438,7 +405,6 @@ const struct amd_ip_funcs iceland_ih_ip_funcs = {
- 	.is_idle = iceland_ih_is_idle,
- 	.wait_for_idle = iceland_ih_wait_for_idle,
- 	.soft_reset = iceland_ih_soft_reset,
--	.print_status = iceland_ih_print_status,
- 	.set_clockgating_state = iceland_ih_set_clockgating_state,
- 	.set_powergating_state = iceland_ih_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-index 654d767..4bd1e55 100644
---- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-@@ -3147,62 +3147,6 @@ static int kv_dpm_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void kv_dpm_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "KV/KB DPM registers\n");
--	dev_info(adev->dev, "  DIDT_SQ_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_SQ_CTRL0));
--	dev_info(adev->dev, "  DIDT_DB_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_DB_CTRL0));
--	dev_info(adev->dev, "  DIDT_TD_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_TD_CTRL0));
--	dev_info(adev->dev, "  DIDT_TCP_CTRL0=0x%08X\n",
--		 RREG32_DIDT(ixDIDT_TCP_CTRL0));
--	dev_info(adev->dev, "  LCAC_SX0_OVR_SEL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_SX0_OVR_SEL));
--	dev_info(adev->dev, "  LCAC_SX0_OVR_VAL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_SX0_OVR_VAL));
--	dev_info(adev->dev, "  LCAC_MC0_OVR_SEL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC0_OVR_SEL));
--	dev_info(adev->dev, "  LCAC_MC0_OVR_VAL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC0_OVR_VAL));
--	dev_info(adev->dev, "  LCAC_MC1_OVR_SEL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC1_OVR_SEL));
--	dev_info(adev->dev, "  LCAC_MC1_OVR_VAL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC1_OVR_VAL));
--	dev_info(adev->dev, "  LCAC_MC2_OVR_SEL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC2_OVR_SEL));
--	dev_info(adev->dev, "  LCAC_MC2_OVR_VAL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC2_OVR_VAL));
--	dev_info(adev->dev, "  LCAC_MC3_OVR_SEL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC3_OVR_SEL));
--	dev_info(adev->dev, "  LCAC_MC3_OVR_VAL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_MC3_OVR_VAL));
--	dev_info(adev->dev, "  LCAC_CPL_OVR_SEL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_CPL_OVR_SEL));
--	dev_info(adev->dev, "  LCAC_CPL_OVR_VAL=0x%08X\n",
--		 RREG32_SMC(ixLCAC_CPL_OVR_VAL));
--	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_0=0x%08X\n",
--		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
--	dev_info(adev->dev, "  GENERAL_PWRMGT=0x%08X\n",
--		 RREG32_SMC(ixGENERAL_PWRMGT));
--	dev_info(adev->dev, "  SCLK_PWRMGT_CNTL=0x%08X\n",
--		 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
--	dev_info(adev->dev, "  SMC_MESSAGE_0=0x%08X\n",
--		 RREG32(mmSMC_MESSAGE_0));
--	dev_info(adev->dev, "  SMC_RESP_0=0x%08X\n",
--		 RREG32(mmSMC_RESP_0));
--	dev_info(adev->dev, "  SMC_MSG_ARG_0=0x%08X\n",
--		 RREG32(mmSMC_MSG_ARG_0));
--	dev_info(adev->dev, "  SMC_IND_INDEX_0=0x%08X\n",
--		 RREG32(mmSMC_IND_INDEX_0));
--	dev_info(adev->dev, "  SMC_IND_DATA_0=0x%08X\n",
--		 RREG32(mmSMC_IND_DATA_0));
--	dev_info(adev->dev, "  SMC_IND_ACCESS_CNTL=0x%08X\n",
--		 RREG32(mmSMC_IND_ACCESS_CNTL));
--}
- 
- static int kv_dpm_soft_reset(void *handle)
- {
-@@ -3311,7 +3255,6 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = {
- 	.is_idle = kv_dpm_is_idle,
- 	.wait_for_idle = kv_dpm_wait_for_idle,
- 	.soft_reset = kv_dpm_soft_reset,
--	.print_status = kv_dpm_print_status,
- 	.set_clockgating_state = kv_dpm_set_clockgating_state,
- 	.set_powergating_state = kv_dpm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 9d8d3ef..037a425 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -1080,55 +1080,6 @@ static int sdma_v2_4_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void sdma_v2_4_print_status(void *handle)
--{
--	int i, j;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "VI SDMA registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		 RREG32(mmSRBM_STATUS2));
--	for (i = 0; i < adev->sdma.num_instances; i++) {
--		dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
--			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
--			 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
--		mutex_lock(&adev->srbm_mutex);
--		for (j = 0; j < 16; j++) {
--			vi_srbm_select(adev, 0, 0, 0, j);
--			dev_info(adev->dev, "  VM %d:\n", j);
--			dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
--				 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
--			dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
--				 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
--		}
--		vi_srbm_select(adev, 0, 0, 0, 0);
--		mutex_unlock(&adev->srbm_mutex);
--	}
--}
--
- static int sdma_v2_4_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0;
-@@ -1151,8 +1102,6 @@ static int sdma_v2_4_soft_reset(void *handle)
- 	}
- 
- 	if (srbm_soft_reset) {
--		sdma_v2_4_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -1167,8 +1116,6 @@ static int sdma_v2_4_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		sdma_v2_4_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -1294,7 +1241,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
- 	.is_idle = sdma_v2_4_is_idle,
- 	.wait_for_idle = sdma_v2_4_wait_for_idle,
- 	.soft_reset = sdma_v2_4_soft_reset,
--	.print_status = sdma_v2_4_print_status,
- 	.set_clockgating_state = sdma_v2_4_set_clockgating_state,
- 	.set_powergating_state = sdma_v2_4_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 72cae36..c94c266 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1314,57 +1314,6 @@ static int sdma_v3_0_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void sdma_v3_0_print_status(void *handle)
--{
--	int i, j;
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "VI SDMA registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		 RREG32(mmSRBM_STATUS2));
--	for (i = 0; i < adev->sdma.num_instances; i++) {
--		dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
--			 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_GFX_DOORBELL=0x%08X\n",
--			 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
--		dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
--			 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
--		mutex_lock(&adev->srbm_mutex);
--		for (j = 0; j < 16; j++) {
--			vi_srbm_select(adev, 0, 0, 0, j);
--			dev_info(adev->dev, "  VM %d:\n", j);
--			dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
--				 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
--			dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
--				 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
--		}
--		vi_srbm_select(adev, 0, 0, 0, 0);
--		mutex_unlock(&adev->srbm_mutex);
--	}
--}
--
- static int sdma_v3_0_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0;
-@@ -1387,8 +1336,6 @@ static int sdma_v3_0_soft_reset(void *handle)
- 	}
- 
- 	if (srbm_soft_reset) {
--		sdma_v3_0_print_status((void *)adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -1403,8 +1350,6 @@ static int sdma_v3_0_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		sdma_v3_0_print_status((void *)adev);
- 	}
- 
- 	return 0;
-@@ -1608,7 +1553,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
- 	.is_idle = sdma_v3_0_is_idle,
- 	.wait_for_idle = sdma_v3_0_wait_for_idle,
- 	.soft_reset = sdma_v3_0_soft_reset,
--	.print_status = sdma_v3_0_print_status,
- 	.set_clockgating_state = sdma_v3_0_set_clockgating_state,
- 	.set_powergating_state = sdma_v3_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-index 0497784..552f0f4 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-@@ -154,7 +154,6 @@ const struct amd_ip_funcs tonga_dpm_ip_funcs = {
- 	.is_idle = NULL,
- 	.wait_for_idle = NULL,
- 	.soft_reset = NULL,
--	.print_status = NULL,
- 	.set_clockgating_state = tonga_dpm_set_clockgating_state,
- 	.set_powergating_state = tonga_dpm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-index 0f14199..55cdab8 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-@@ -374,35 +374,6 @@ static int tonga_ih_wait_for_idle(void *handle)
- 	return -ETIMEDOUT;
- }
- 
--static void tonga_ih_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "TONGA IH registers\n");
--	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
--		RREG32(mmSRBM_STATUS));
--	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
--		RREG32(mmSRBM_STATUS2));
--	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL));
--	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
--		 RREG32(mmINTERRUPT_CNTL2));
--	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
--		 RREG32(mmIH_CNTL));
--	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
--		 RREG32(mmIH_RB_CNTL));
--	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
--		 RREG32(mmIH_RB_BASE));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_LO));
--	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR_ADDR_HI));
--	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
--		 RREG32(mmIH_RB_RPTR));
--	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
--		 RREG32(mmIH_RB_WPTR));
--}
--
- static int tonga_ih_soft_reset(void *handle)
- {
- 	u32 srbm_soft_reset = 0;
-@@ -414,8 +385,6 @@ static int tonga_ih_soft_reset(void *handle)
- 						SOFT_RESET_IH, 1);
- 
- 	if (srbm_soft_reset) {
--		tonga_ih_print_status(adev);
--
- 		tmp = RREG32(mmSRBM_SOFT_RESET);
- 		tmp |= srbm_soft_reset;
- 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
-@@ -430,8 +399,6 @@ static int tonga_ih_soft_reset(void *handle)
- 
- 		/* Wait a little for things to settle down */
- 		udelay(50);
--
--		tonga_ih_print_status(adev);
- 	}
- 
- 	return 0;
-@@ -461,7 +428,6 @@ const struct amd_ip_funcs tonga_ih_ip_funcs = {
- 	.is_idle = tonga_ih_is_idle,
- 	.wait_for_idle = tonga_ih_wait_for_idle,
- 	.soft_reset = tonga_ih_soft_reset,
--	.print_status = tonga_ih_print_status,
- 	.set_clockgating_state = tonga_ih_set_clockgating_state,
- 	.set_powergating_state = tonga_ih_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index c257cfa..abd37a7 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -680,117 +680,6 @@ static int uvd_v4_2_soft_reset(void *handle)
- 	return uvd_v4_2_start(adev);
- }
- 
--static void uvd_v4_2_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	dev_info(adev->dev, "UVD 4.2 registers\n");
--	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
--		 RREG32(mmUVD_SEMA_ADDR_LOW));
--	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
--		 RREG32(mmUVD_SEMA_ADDR_HIGH));
--	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
--		 RREG32(mmUVD_SEMA_CMD));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_CMD));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_DATA0));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_DATA1));
--	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
--		 RREG32(mmUVD_ENGINE_CNTL));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_CNTL));
--	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
--		 RREG32(mmUVD_LMI_EXT40_ADDR));
--	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
--		 RREG32(mmUVD_CTX_INDEX));
--	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
--		 RREG32(mmUVD_CTX_DATA));
--	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
--		 RREG32(mmUVD_CGC_GATE));
--	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
--		 RREG32(mmUVD_CGC_CTRL));
--	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
--		 RREG32(mmUVD_LMI_CTRL2));
--	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
--		 RREG32(mmUVD_MASTINT_EN));
--	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
--		 RREG32(mmUVD_LMI_ADDR_EXT));
--	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
--		 RREG32(mmUVD_LMI_CTRL));
--	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmUVD_LMI_SWAP_CNTL));
--	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmUVD_MP_SWAP_CNTL));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXA0));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXA1));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXB0));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXB1));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUX));
--	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_ALU));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE0));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE1));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE2));
--	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CNTL));
--	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
--		 RREG32(mmUVD_SOFT_RESET));
--	dev_info(adev->dev, "  UVD_RBC_IB_BASE=0x%08X\n",
--		 RREG32(mmUVD_RBC_IB_BASE));
--	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
--		 RREG32(mmUVD_RBC_IB_SIZE));
--	dev_info(adev->dev, "  UVD_RBC_RB_BASE=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_BASE));
--	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_RPTR));
--	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_WPTR));
--	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
--	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_CNTL));
--	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
--		 RREG32(mmUVD_STATUS));
--	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
--		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
--	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
--		 RREG32(mmUVD_CONTEXT_ID));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
--
--}
--
- static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
- 					struct amdgpu_irq_src *source,
- 					unsigned type,
-@@ -861,7 +750,6 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
- 	.is_idle = uvd_v4_2_is_idle,
- 	.wait_for_idle = uvd_v4_2_wait_for_idle,
- 	.soft_reset = uvd_v4_2_soft_reset,
--	.print_status = uvd_v4_2_print_status,
- 	.set_clockgating_state = uvd_v4_2_set_clockgating_state,
- 	.set_powergating_state = uvd_v4_2_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 5f0d4f7..1c1a0e2 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -624,120 +624,6 @@ static int uvd_v5_0_soft_reset(void *handle)
- 	return uvd_v5_0_start(adev);
- }
- 
--static void uvd_v5_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	dev_info(adev->dev, "UVD 5.0 registers\n");
--	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
--		 RREG32(mmUVD_SEMA_ADDR_LOW));
--	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
--		 RREG32(mmUVD_SEMA_ADDR_HIGH));
--	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
--		 RREG32(mmUVD_SEMA_CMD));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_CMD));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_DATA0));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_DATA1));
--	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
--		 RREG32(mmUVD_ENGINE_CNTL));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_CNTL));
--	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
--		 RREG32(mmUVD_LMI_EXT40_ADDR));
--	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
--		 RREG32(mmUVD_CTX_INDEX));
--	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
--		 RREG32(mmUVD_CTX_DATA));
--	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
--		 RREG32(mmUVD_CGC_GATE));
--	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
--		 RREG32(mmUVD_CGC_CTRL));
--	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
--		 RREG32(mmUVD_LMI_CTRL2));
--	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
--		 RREG32(mmUVD_MASTINT_EN));
--	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
--		 RREG32(mmUVD_LMI_ADDR_EXT));
--	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
--		 RREG32(mmUVD_LMI_CTRL));
--	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmUVD_LMI_SWAP_CNTL));
--	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmUVD_MP_SWAP_CNTL));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXA0));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXA1));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXB0));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXB1));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUX));
--	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_ALU));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE0));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE1));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE2));
--	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CNTL));
--	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
--		 RREG32(mmUVD_SOFT_RESET));
--	dev_info(adev->dev, "  UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n",
--		 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW));
--	dev_info(adev->dev, "  UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n",
--		 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH));
--	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
--		 RREG32(mmUVD_RBC_IB_SIZE));
--	dev_info(adev->dev, "  UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n",
--		 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW));
--	dev_info(adev->dev, "  UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n",
--		 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH));
--	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_RPTR));
--	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_WPTR));
--	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
--	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_CNTL));
--	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
--		 RREG32(mmUVD_STATUS));
--	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
--		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
--	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
--		 RREG32(mmUVD_CONTEXT_ID));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
--}
--
- static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
- 					struct amdgpu_irq_src *source,
- 					unsigned type,
-@@ -916,7 +802,6 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
- 	.is_idle = uvd_v5_0_is_idle,
- 	.wait_for_idle = uvd_v5_0_wait_for_idle,
- 	.soft_reset = uvd_v5_0_soft_reset,
--	.print_status = uvd_v5_0_print_status,
- 	.set_clockgating_state = uvd_v5_0_set_clockgating_state,
- 	.set_powergating_state = uvd_v5_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 7e7c3da..5665a4f 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -706,112 +706,6 @@ static int uvd_v6_0_soft_reset(void *handle)
- 	return uvd_v6_0_start(adev);
- }
- 
--static void uvd_v6_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	dev_info(adev->dev, "UVD 6.0 registers\n");
--	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
--		 RREG32(mmUVD_SEMA_ADDR_LOW));
--	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",
--		 RREG32(mmUVD_SEMA_ADDR_HIGH));
--	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",
--		 RREG32(mmUVD_SEMA_CMD));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_CMD));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_DATA0));
--	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",
--		 RREG32(mmUVD_GPCOM_VCPU_DATA1));
--	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",
--		 RREG32(mmUVD_ENGINE_CNTL));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_CNTL));
--	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",
--		 RREG32(mmUVD_LMI_EXT40_ADDR));
--	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",
--		 RREG32(mmUVD_CTX_INDEX));
--	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",
--		 RREG32(mmUVD_CTX_DATA));
--	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",
--		 RREG32(mmUVD_CGC_GATE));
--	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",
--		 RREG32(mmUVD_CGC_CTRL));
--	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",
--		 RREG32(mmUVD_LMI_CTRL2));
--	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",
--		 RREG32(mmUVD_MASTINT_EN));
--	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",
--		 RREG32(mmUVD_LMI_ADDR_EXT));
--	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",
--		 RREG32(mmUVD_LMI_CTRL));
--	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmUVD_LMI_SWAP_CNTL));
--	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmUVD_MP_SWAP_CNTL));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXA0));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXA1));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXB0));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUXB1));
--	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_MUX));
--	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",
--		 RREG32(mmUVD_MPC_SET_ALU));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE0));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE1));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
--	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CACHE_SIZE2));
--	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",
--		 RREG32(mmUVD_VCPU_CNTL));
--	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",
--		 RREG32(mmUVD_SOFT_RESET));
--	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",
--		 RREG32(mmUVD_RBC_IB_SIZE));
--	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_RPTR));
--	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_WPTR));
--	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
--	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",
--		 RREG32(mmUVD_RBC_RB_CNTL));
--	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",
--		 RREG32(mmUVD_STATUS));
--	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
--		 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
--	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
--		 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
--	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
--		 RREG32(mmUVD_CONTEXT_ID));
--	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
--	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
--		 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
--}
--
- static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
- 					struct amdgpu_irq_src *source,
- 					unsigned type,
-@@ -993,7 +887,6 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
- 	.is_idle = uvd_v6_0_is_idle,
- 	.wait_for_idle = uvd_v6_0_wait_for_idle,
- 	.soft_reset = uvd_v6_0_soft_reset,
--	.print_status = uvd_v6_0_print_status,
- 	.set_clockgating_state = uvd_v6_0_set_clockgating_state,
- 	.set_powergating_state = uvd_v6_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index ab9ee2a..95f6e57 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -495,75 +495,6 @@ static int vce_v2_0_soft_reset(void *handle)
- 	return vce_v2_0_start(adev);
- }
- 
--static void vce_v2_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "VCE 2.0 registers\n");
--	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",
--		 RREG32(mmVCE_STATUS));
--	dev_info(adev->dev, "  VCE_VCPU_CNTL=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CNTL));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE0=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_SIZE0));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE1=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_SIZE1));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE2=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_SIZE2));
--	dev_info(adev->dev, "  VCE_SOFT_RESET=0x%08X\n",
--		 RREG32(mmVCE_SOFT_RESET));
--	dev_info(adev->dev, "  VCE_RB_BASE_LO2=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_LO2));
--	dev_info(adev->dev, "  VCE_RB_BASE_HI2=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_HI2));
--	dev_info(adev->dev, "  VCE_RB_SIZE2=0x%08X\n",
--		 RREG32(mmVCE_RB_SIZE2));
--	dev_info(adev->dev, "  VCE_RB_RPTR2=0x%08X\n",
--		 RREG32(mmVCE_RB_RPTR2));
--	dev_info(adev->dev, "  VCE_RB_WPTR2=0x%08X\n",
--		 RREG32(mmVCE_RB_WPTR2));
--	dev_info(adev->dev, "  VCE_RB_BASE_LO=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_LO));
--	dev_info(adev->dev, "  VCE_RB_BASE_HI=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_HI));
--	dev_info(adev->dev, "  VCE_RB_SIZE=0x%08X\n",
--		 RREG32(mmVCE_RB_SIZE));
--	dev_info(adev->dev, "  VCE_RB_RPTR=0x%08X\n",
--		 RREG32(mmVCE_RB_RPTR));
--	dev_info(adev->dev, "  VCE_RB_WPTR=0x%08X\n",
--		 RREG32(mmVCE_RB_WPTR));
--	dev_info(adev->dev, "  VCE_CLOCK_GATING_A=0x%08X\n",
--		 RREG32(mmVCE_CLOCK_GATING_A));
--	dev_info(adev->dev, "  VCE_CLOCK_GATING_B=0x%08X\n",
--		 RREG32(mmVCE_CLOCK_GATING_B));
--	dev_info(adev->dev, "  VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
--		 RREG32(mmVCE_CGTT_CLK_OVERRIDE));
--	dev_info(adev->dev, "  VCE_UENC_CLOCK_GATING=0x%08X\n",
--		 RREG32(mmVCE_UENC_CLOCK_GATING));
--	dev_info(adev->dev, "  VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
--		 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
--	dev_info(adev->dev, "  VCE_SYS_INT_EN=0x%08X\n",
--		 RREG32(mmVCE_SYS_INT_EN));
--	dev_info(adev->dev, "  VCE_LMI_CTRL2=0x%08X\n",
--		 RREG32(mmVCE_LMI_CTRL2));
--	dev_info(adev->dev, "  VCE_LMI_CTRL=0x%08X\n",
--		 RREG32(mmVCE_LMI_CTRL));
--	dev_info(adev->dev, "  VCE_LMI_VM_CTRL=0x%08X\n",
--		 RREG32(mmVCE_LMI_VM_CTRL));
--	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmVCE_LMI_SWAP_CNTL));
--	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL1=0x%08X\n",
--		 RREG32(mmVCE_LMI_SWAP_CNTL1));
--	dev_info(adev->dev, "  VCE_LMI_CACHE_CTRL=0x%08X\n",
--		 RREG32(mmVCE_LMI_CACHE_CTRL));
--}
--
- static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
- 					struct amdgpu_irq_src *source,
- 					unsigned type,
-@@ -647,7 +578,6 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = {
- 	.is_idle = vce_v2_0_is_idle,
- 	.wait_for_idle = vce_v2_0_wait_for_idle,
- 	.soft_reset = vce_v2_0_soft_reset,
--	.print_status = vce_v2_0_print_status,
- 	.set_clockgating_state = vce_v2_0_set_clockgating_state,
- 	.set_powergating_state = vce_v2_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index 5834285..e1d6ae7 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -566,73 +566,6 @@ static int vce_v3_0_soft_reset(void *handle)
- 	return vce_v3_0_start(adev);
- }
- 
--static void vce_v3_0_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	dev_info(adev->dev, "VCE 3.0 registers\n");
--	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",
--		 RREG32(mmVCE_STATUS));
--	dev_info(adev->dev, "  VCE_VCPU_CNTL=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CNTL));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE0=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_SIZE0));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE1=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_SIZE1));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
--	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE2=0x%08X\n",
--		 RREG32(mmVCE_VCPU_CACHE_SIZE2));
--	dev_info(adev->dev, "  VCE_SOFT_RESET=0x%08X\n",
--		 RREG32(mmVCE_SOFT_RESET));
--	dev_info(adev->dev, "  VCE_RB_BASE_LO2=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_LO2));
--	dev_info(adev->dev, "  VCE_RB_BASE_HI2=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_HI2));
--	dev_info(adev->dev, "  VCE_RB_SIZE2=0x%08X\n",
--		 RREG32(mmVCE_RB_SIZE2));
--	dev_info(adev->dev, "  VCE_RB_RPTR2=0x%08X\n",
--		 RREG32(mmVCE_RB_RPTR2));
--	dev_info(adev->dev, "  VCE_RB_WPTR2=0x%08X\n",
--		 RREG32(mmVCE_RB_WPTR2));
--	dev_info(adev->dev, "  VCE_RB_BASE_LO=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_LO));
--	dev_info(adev->dev, "  VCE_RB_BASE_HI=0x%08X\n",
--		 RREG32(mmVCE_RB_BASE_HI));
--	dev_info(adev->dev, "  VCE_RB_SIZE=0x%08X\n",
--		 RREG32(mmVCE_RB_SIZE));
--	dev_info(adev->dev, "  VCE_RB_RPTR=0x%08X\n",
--		 RREG32(mmVCE_RB_RPTR));
--	dev_info(adev->dev, "  VCE_RB_WPTR=0x%08X\n",
--		 RREG32(mmVCE_RB_WPTR));
--	dev_info(adev->dev, "  VCE_CLOCK_GATING_A=0x%08X\n",
--		 RREG32(mmVCE_CLOCK_GATING_A));
--	dev_info(adev->dev, "  VCE_CLOCK_GATING_B=0x%08X\n",
--		 RREG32(mmVCE_CLOCK_GATING_B));
--	dev_info(adev->dev, "  VCE_UENC_CLOCK_GATING=0x%08X\n",
--		 RREG32(mmVCE_UENC_CLOCK_GATING));
--	dev_info(adev->dev, "  VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
--		 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
--	dev_info(adev->dev, "  VCE_SYS_INT_EN=0x%08X\n",
--		 RREG32(mmVCE_SYS_INT_EN));
--	dev_info(adev->dev, "  VCE_LMI_CTRL2=0x%08X\n",
--		 RREG32(mmVCE_LMI_CTRL2));
--	dev_info(adev->dev, "  VCE_LMI_CTRL=0x%08X\n",
--		 RREG32(mmVCE_LMI_CTRL));
--	dev_info(adev->dev, "  VCE_LMI_VM_CTRL=0x%08X\n",
--		 RREG32(mmVCE_LMI_VM_CTRL));
--	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL=0x%08X\n",
--		 RREG32(mmVCE_LMI_SWAP_CNTL));
--	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL1=0x%08X\n",
--		 RREG32(mmVCE_LMI_SWAP_CNTL1));
--	dev_info(adev->dev, "  VCE_LMI_CACHE_CTRL=0x%08X\n",
--		 RREG32(mmVCE_LMI_CACHE_CTRL));
--}
--
- static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
- 					struct amdgpu_irq_src *source,
- 					unsigned type,
-@@ -752,7 +685,6 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = {
- 	.is_idle = vce_v3_0_is_idle,
- 	.wait_for_idle = vce_v3_0_wait_for_idle,
- 	.soft_reset = vce_v3_0_soft_reset,
--	.print_status = vce_v3_0_print_status,
- 	.set_clockgating_state = vce_v3_0_set_clockgating_state,
- 	.set_powergating_state = vce_v3_0_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index b5602ac..61f5555 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1624,11 +1624,6 @@ static int vi_common_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void vi_common_print_status(void *handle)
--{
--	return;
--}
--
- static int vi_common_soft_reset(void *handle)
- {
- 	return 0;
-@@ -1753,7 +1748,6 @@ const struct amd_ip_funcs vi_common_ip_funcs = {
- 	.is_idle = vi_common_is_idle,
- 	.wait_for_idle = vi_common_wait_for_idle,
- 	.soft_reset = vi_common_soft_reset,
--	.print_status = vi_common_print_status,
- 	.set_clockgating_state = vi_common_set_clockgating_state,
- 	.set_powergating_state = vi_common_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 4defc70..468c4ba 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -124,13 +124,6 @@ static int dm_wait_for_idle(void *handle)
- 	return 0;
- }
- 
--static void dm_print_status(void *handle)
--{
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	dev_info(adev->dev, "DCE registers\n");
--	/* XXX todo */
--}
--
- static int dm_soft_reset(void *handle)
- {
- 	/* XXX todo */
-@@ -639,7 +632,6 @@ const struct amd_ip_funcs amdgpu_dm_funcs = {
- 	.is_idle = dm_is_idle,
- 	.wait_for_idle = dm_wait_for_idle,
- 	.soft_reset = dm_soft_reset,
--	.print_status = dm_print_status,
- 	.set_clockgating_state = dm_set_clockgating_state,
- 	.set_powergating_state = dm_set_powergating_state,
- };
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index e56d8a3..ea9ee46 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -165,8 +165,6 @@ struct amd_ip_funcs {
- 	int (*wait_for_idle)(void *handle);
- 	/* soft reset the IP block */
- 	int (*soft_reset)(void *handle);
--	/* dump the IP block status registers */
--	void (*print_status)(void *handle);
- 	/* enable/disable cg for the IP block */
- 	int (*set_clockgating_state)(void *handle,
- 				     enum amd_clockgating_state state);
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index 0527ae3..aba587c 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -180,10 +180,6 @@ static int pp_sw_reset(void *handle)
- 	return 0;
- }
- 
--static void pp_print_status(void *handle)
--{
--
--}
- 
- static int pp_set_clockgating_state(void *handle,
- 				    enum amd_clockgating_state state)
-@@ -355,7 +351,6 @@ const struct amd_ip_funcs pp_ip_funcs = {
- 	.is_idle = pp_is_idle,
- 	.wait_for_idle = pp_wait_for_idle,
- 	.soft_reset = pp_sw_reset,
--	.print_status = pp_print_status,
- 	.set_clockgating_state = pp_set_clockgating_state,
- 	.set_powergating_state = pp_set_powergating_state,
- };
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1023-drm-amd-amdgpu-Add-debugfs-entries-for-smc-didt-pcie.patch b/common/recipes-kernel/linux/files/1023-drm-amd-amdgpu-Add-debugfs-entries-for-smc-didt-pcie.patch
deleted file mode 100644
index 41acf703..00000000
--- a/common/recipes-kernel/linux/files/1023-drm-amd-amdgpu-Add-debugfs-entries-for-smc-didt-pcie.patch
+++ /dev/null
@@ -1,291 +0,0 @@
-From c08b2057b33808ae9fc3942cb892f78b071379ba Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Fri, 15 Apr 2016 13:08:44 -0400
-Subject: [PATCH 1023/1110] drm/amd/amdgpu: Add debugfs entries for
- smc/didt/pcie
-
-This adds 3 new files that can be read/written to access
-GPU registers.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 230 ++++++++++++++++++++++++++++-
- 2 files changed, 223 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index a8c59be..6079a39 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1959,7 +1959,7 @@ struct amdgpu_device {
- 	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
- 	unsigned 			debugfs_count;
- #if defined(CONFIG_DEBUG_FS)
--	struct dentry			*debugfs_regs;
-+	struct dentry			*debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
- #endif
- 	struct amdgpu_atif		atif;
- 	struct amdgpu_atcs		atcs;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 8a5e3f7..56e4627 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -2186,32 +2186,246 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
- 	return result;
- }
- 
-+static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
-+					size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = f->f_inode->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	while (size) {
-+		uint32_t value;
-+
-+		value = RREG32_PCIE(*pos >> 2);
-+		r = put_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
-+static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
-+					 size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = f->f_inode->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	while (size) {
-+		uint32_t value;
-+
-+		r = get_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		WREG32_PCIE(*pos >> 2, value);
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
-+static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
-+					size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = f->f_inode->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	while (size) {
-+		uint32_t value;
-+
-+		value = RREG32_DIDT(*pos >> 2);
-+		r = put_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
-+static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
-+					 size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = f->f_inode->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	while (size) {
-+		uint32_t value;
-+
-+		r = get_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		WREG32_DIDT(*pos >> 2, value);
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
-+static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
-+					size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = f->f_inode->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	while (size) {
-+		uint32_t value;
-+
-+		value = RREG32_SMC(*pos >> 2);
-+		r = put_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
-+static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
-+					 size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = f->f_inode->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	while (size) {
-+		uint32_t value;
-+
-+		r = get_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		WREG32_SMC(*pos >> 2, value);
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
- static const struct file_operations amdgpu_debugfs_regs_fops = {
- 	.owner = THIS_MODULE,
- 	.read = amdgpu_debugfs_regs_read,
- 	.write = amdgpu_debugfs_regs_write,
- 	.llseek = default_llseek
- };
-+static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
-+	.owner = THIS_MODULE,
-+	.read = amdgpu_debugfs_regs_didt_read,
-+	.write = amdgpu_debugfs_regs_didt_write,
-+	.llseek = default_llseek
-+};
-+static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
-+	.owner = THIS_MODULE,
-+	.read = amdgpu_debugfs_regs_pcie_read,
-+	.write = amdgpu_debugfs_regs_pcie_write,
-+	.llseek = default_llseek
-+};
-+static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
-+	.owner = THIS_MODULE,
-+	.read = amdgpu_debugfs_regs_smc_read,
-+	.write = amdgpu_debugfs_regs_smc_write,
-+	.llseek = default_llseek
-+};
-+
-+static const struct file_operations *debugfs_regs[] = {
-+	&amdgpu_debugfs_regs_fops,
-+	&amdgpu_debugfs_regs_didt_fops,
-+	&amdgpu_debugfs_regs_pcie_fops,
-+	&amdgpu_debugfs_regs_smc_fops,
-+};
-+
-+static const char *debugfs_regs_names[] = {
-+	"amdgpu_regs",
-+	"amdgpu_regs_didt",
-+	"amdgpu_regs_pcie",
-+	"amdgpu_regs_smc",
-+};
- 
- static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
- {
- 	struct drm_minor *minor = adev->ddev->primary;
- 	struct dentry *ent, *root = minor->debugfs_root;
-+	unsigned i, j;
-+
-+	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
-+		ent = debugfs_create_file(debugfs_regs_names[i],
-+					  S_IFREG | S_IRUGO, root,
-+					  adev, debugfs_regs[i]);
-+		if (IS_ERR(ent)) {
-+			for (j = 0; j < i; j++) {
-+				debugfs_remove(adev->debugfs_regs[i]);
-+				adev->debugfs_regs[i] = NULL;
-+			}
-+			return PTR_ERR(ent);
-+		}
- 
--	ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
--				  adev, &amdgpu_debugfs_regs_fops);
--	if (IS_ERR(ent))
--		return PTR_ERR(ent);
--	i_size_write(ent->d_inode, adev->rmmio_size);
--	adev->debugfs_regs = ent;
-+		if (!i)
-+			i_size_write(ent->d_inode, adev->rmmio_size);
-+		adev->debugfs_regs[i] = ent;
-+	}
- 
- 	return 0;
- }
- 
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
- {
--	debugfs_remove(adev->debugfs_regs);
--	adev->debugfs_regs = NULL;
-+	unsigned i;
-+
-+	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
-+		if (adev->debugfs_regs[i]) {
-+			debugfs_remove(adev->debugfs_regs[i]);
-+			adev->debugfs_regs[i] = NULL;
-+		}
-+	}
- }
- 
- int amdgpu_debugfs_init(struct drm_minor *minor)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1024-drm-amdgpu-dce11.2-pick-pll-based-on-transmitter.patch b/common/recipes-kernel/linux/files/1024-drm-amdgpu-dce11.2-pick-pll-based-on-transmitter.patch
deleted file mode 100644
index 6a79c195..00000000
--- a/common/recipes-kernel/linux/files/1024-drm-amdgpu-dce11.2-pick-pll-based-on-transmitter.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 50efa1d0792c189c154143fc9a26192881b660ac Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 18 Apr 2016 17:40:52 -0400
-Subject: [PATCH 1024/1110] drm/amdgpu/dce11.2: pick pll based on transmitter
-
-The plls are part of the phys.
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 28 +++++++++++++++++++++++++++-
- 1 file changed, 27 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 22c6250..6a2c77d 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -2412,6 +2412,10 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
- 
- 	if ((adev->asic_type == CHIP_POLARIS10) ||
- 	    (adev->asic_type == CHIP_POLARIS11)) {
-+		struct amdgpu_encoder *amdgpu_encoder =
-+			to_amdgpu_encoder(amdgpu_crtc->encoder);
-+		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
-+
- 		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
- 			return ATOM_DP_DTO;
- 		/* use the same PPLL for all monitors with the same clock */
-@@ -2419,7 +2423,29 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
- 		if (pll != ATOM_PPLL_INVALID)
- 			return pll;
- 
--		return ATOM_COMBOPHY_PLL0 + amdgpu_crtc->crtc_id;
-+		switch (amdgpu_encoder->encoder_id) {
-+		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-+			if (dig->linkb)
-+				return ATOM_COMBOPHY_PLL1;
-+			else
-+				return ATOM_COMBOPHY_PLL0;
-+			break;
-+		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-+			if (dig->linkb)
-+				return ATOM_COMBOPHY_PLL3;
-+			else
-+				return ATOM_COMBOPHY_PLL2;
-+			break;
-+		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-+			if (dig->linkb)
-+				return ATOM_COMBOPHY_PLL5;
-+			else
-+				return ATOM_COMBOPHY_PLL4;
-+			break;
-+		default:
-+			DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
-+			return ATOM_PPLL_INVALID;
-+		}
- 	}
- 
- 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1025-drm-amdgpu-add-missing-case-for-ST-in-audio-init.patch b/common/recipes-kernel/linux/files/1025-drm-amdgpu-add-missing-case-for-ST-in-audio-init.patch
deleted file mode 100644
index d6d616e4..00000000
--- a/common/recipes-kernel/linux/files/1025-drm-amdgpu-add-missing-case-for-ST-in-audio-init.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 1c44710310c2b1346df22f092902f06ae37187a7 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 18 Apr 2016 18:14:43 -0400
-Subject: [PATCH 1025/1110] drm/amdgpu: add missing case for ST in audio init
-
-Otherwise, we fail to init modesetting.
-
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 6a2c77d..9c7ea3c 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -1608,6 +1608,7 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
- 
- 	switch (adev->asic_type) {
- 	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
- 		adev->mode_info.audio.num_pins = 7;
- 		break;
- 	case CHIP_POLARIS10:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1026-drm-amdgpu-forbid-mapping-of-userptr-bo-through-rade.patch b/common/recipes-kernel/linux/files/1026-drm-amdgpu-forbid-mapping-of-userptr-bo-through-rade.patch
deleted file mode 100644
index 920b174f..00000000
--- a/common/recipes-kernel/linux/files/1026-drm-amdgpu-forbid-mapping-of-userptr-bo-through-rade.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 8343ac3454dfd121bee9bbc686d36b5365966c8c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Glisse?= <jglisse@redhat.com>
-Date: Tue, 19 Apr 2016 09:07:51 -0400
-Subject: [PATCH 1026/1110] drm/amdgpu: forbid mapping of userptr bo through
- radeon device file
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Allowing userptr bo which are basicly a list of page from some vma
-(so either anonymous page or file backed page) would lead to serious
-corruption of kernel structures and counters (because we overwrite
-the page->mapping field when mapping buffer).
-
-This will already block if the buffer was populated before anyone does
-try to mmap it because then TTM_PAGE_FLAG_SG would be set in in the
-ttm_tt flags. But that flag is check before ttm_tt_populate in the ttm
-vm fault handler.
-
-So to be safe just add a check to verify_access() callback.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
-Cc: <stable@vger.kernel.org>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 70f005d..e296415 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
- {
- 	struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
- 
-+	if (amdgpu_ttm_tt_get_usermm(bo->ttm))
-+		return -EPERM;
- 	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1027-drm-amd-powerplay-revise-caching-the-soft-pptable-an.patch b/common/recipes-kernel/linux/files/1027-drm-amd-powerplay-revise-caching-the-soft-pptable-an.patch
deleted file mode 100644
index 9402b620..00000000
--- a/common/recipes-kernel/linux/files/1027-drm-amd-powerplay-revise-caching-the-soft-pptable-an.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 1e2ced05d13ff0c0e7c00406d155b24283d3f0c5 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 15 Apr 2016 15:02:54 -0400
-Subject: [PATCH 1027/1110] drm/amd/powerplay: revise caching the soft pptable
- and add it's size
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c   | 15 +++++++++------
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h                 |  1 +
- 2 files changed, 10 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-index 96a2787..10e3630 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
-@@ -138,12 +138,15 @@ const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
- 
- 	u16 size;
- 	u8 frev, crev;
--	void *table_address;
--
--	table_address = (ATOM_Tonga_POWERPLAYTABLE *)
--		cgs_atom_get_data_table(hwmgr->device, index, &size, &frev, &crev);
--
--	hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
-+	void *table_address = (void *)hwmgr->soft_pp_table;
-+
-+	if (!table_address) {
-+		table_address = (ATOM_Tonga_POWERPLAYTABLE *)
-+				cgs_atom_get_data_table(hwmgr->device,
-+						index, &size, &frev, &crev);
-+		hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
-+		hwmgr->soft_pp_table_size = size;
-+	}
- 
- 	return table_address;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index b1a9ae5..c96e5b1 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -577,6 +577,7 @@ struct pp_hwmgr {
- 	void *device;
- 	struct pp_smumgr *smumgr;
- 	const void *soft_pp_table;
-+	uint32_t soft_pp_table_size;
- 	bool need_pp_table_upload;
- 	enum amd_dpm_forced_level dpm_level;
- 	bool block_hw_access;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1028-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch b/common/recipes-kernel/linux/files/1028-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch
deleted file mode 100644
index 721fc7f9..00000000
--- a/common/recipes-kernel/linux/files/1028-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch
+++ /dev/null
@@ -1,119 +0,0 @@
-From 594b416da693a34ae9e024bb49c3e148121d87d9 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 15 Apr 2016 16:33:20 -0400
-Subject: [PATCH 1028/1110] drm/amd/powerplay: revise reading/writing pptable
- on Fiji
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 40 ++++++++++++++++++++----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h |  4 ++-
- 2 files changed, 37 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 623ec80..3334a89 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -579,6 +579,18 @@ static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
-+static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-+
-+	if (data->soft_pp_table) {
-+		kfree(data->soft_pp_table);
-+		data->soft_pp_table = NULL;
-+	}
-+
-+	return phm_hwmgr_backend_fini(hwmgr);
-+}
-+
- static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
-@@ -734,7 +746,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- 			data->pcie_lane_cap = (uint32_t)sys_info.value;
- 	} else {
- 		/* Ignore return value in here, we are cleaning up a mess. */
--		tonga_hwmgr_backend_fini(hwmgr);
-+		fiji_hwmgr_backend_fini(hwmgr);
- 	}
- 
- 	return 0;
-@@ -5096,18 +5108,34 @@ static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- 
--	*table = (char *)&data->smc_state_table;
-+	if (!data->soft_pp_table) {
-+		data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
-+		if (!data->soft_pp_table)
-+			return -ENOMEM;
-+		memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
-+				hwmgr->soft_pp_table_size);
-+	}
-+
-+	*table = (char *)&data->soft_pp_table;
- 
--	return sizeof(struct SMU73_Discrete_DpmTable);
-+	return hwmgr->soft_pp_table_size;
- }
- 
- static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
- {
- 	struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- 
--	void *table = (void *)&data->smc_state_table;
-+	if (!data->soft_pp_table) {
-+		data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
-+		if (!data->soft_pp_table)
-+			return -ENOMEM;
-+	}
-+
-+	memcpy(data->soft_pp_table, buf, size);
-+
-+	hwmgr->soft_pp_table = data->soft_pp_table;
- 
--	memcpy(table, buf, size);
-+	/* TODO: re-init powerplay to implement modified pptable */
- 
- 	return 0;
- }
-@@ -5274,7 +5302,7 @@ bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h
- 
- static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
- 	.backend_init = &fiji_hwmgr_backend_init,
--	.backend_fini = &tonga_hwmgr_backend_fini,
-+	.backend_fini = &fiji_hwmgr_backend_fini,
- 	.asic_setup = &fiji_setup_asic_task,
- 	.dynamic_state_management_enable = &fiji_enable_dpm_tasks,
- 	.force_dpm_level = &fiji_dpm_force_dpm_level,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-index 4b29d9e..170edf5 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
-@@ -302,6 +302,9 @@ struct fiji_hwmgr {
- 	bool                           pg_acp_init;
- 	bool                           frtc_enabled;
- 	bool                           frtc_status_changed;
-+
-+	/* soft pptable for re-uploading into smu */
-+	void *soft_pp_table;
- };
- 
- /* To convert to Q8.8 format for firmware */
-@@ -338,7 +341,6 @@ enum Fiji_I2CLineID {
- #define FIJI_UNUSED_GPIO_PIN       0x7F
- 
- extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
--extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
- extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
- extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
- extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1029-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch b/common/recipes-kernel/linux/files/1029-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch
deleted file mode 100644
index 435b3581..00000000
--- a/common/recipes-kernel/linux/files/1029-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From dc08bc87736f8aa882c78d2de63371984ce0e9bf Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 15 Apr 2016 17:14:53 -0400
-Subject: [PATCH 1029/1110] drm/amd/powerplay: revise reading/writing pptable
- on Tonga
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 37 +++++++++++++++--------
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h |  2 ++
- 2 files changed, 27 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 0d9cf4d..bc61c07 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -4443,17 +4443,14 @@ int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
- 
- int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
--		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
--		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
--	}
-+	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 
--	if (NULL != hwmgr->backend) {
--		kfree(hwmgr->backend);
--		hwmgr->backend = NULL;
-+	if (data->soft_pp_table) {
-+		kfree(data->soft_pp_table);
-+		data->soft_pp_table = NULL;
- 	}
- 
--	return 0;
-+	return phm_hwmgr_backend_fini(hwmgr);
- }
- 
- /**
-@@ -6058,18 +6055,34 @@ static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
- {
- 	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 
--	*table = (char *)&data->smc_state_table;
-+	if (!data->soft_pp_table) {
-+		data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
-+		if (!data->soft_pp_table)
-+			return -ENOMEM;
-+		memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
-+				hwmgr->soft_pp_table_size);
-+	}
-+
-+	*table = (char *)&data->soft_pp_table;
- 
--	return sizeof(struct SMU72_Discrete_DpmTable);
-+	return hwmgr->soft_pp_table_size;
- }
- 
- static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
- {
- 	struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- 
--	void *table = (void *)&data->smc_state_table;
-+	if (!data->soft_pp_table) {
-+		data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
-+		if (!data->soft_pp_table)
-+			return -ENOMEM;
-+	}
-+
-+	memcpy(data->soft_pp_table, buf, size);
-+
-+	hwmgr->soft_pp_table = data->soft_pp_table;
- 
--	memcpy(table, buf, size);
-+	/* TODO: re-init powerplay to implement modified pptable */
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index f88d3bb..c6a6b40 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -353,6 +353,8 @@ struct tonga_hwmgr {
- 	bool                           acp_power_gated;  /* 1: gated, 0:not gated */
- 	bool                           pg_acp_init;
- 
-+	/* soft pptable for re-uploading into smu */
-+	void *soft_pp_table;
- };
- 
- typedef struct tonga_hwmgr tonga_hwmgr;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1030-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch b/common/recipes-kernel/linux/files/1030-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch
deleted file mode 100644
index 1eb1785b..00000000
--- a/common/recipes-kernel/linux/files/1030-drm-amd-powerplay-revise-reading-writing-pptable-on-.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From dc3a9282aa5b0953823710628c71160653dbcb44 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Fri, 15 Apr 2016 17:23:14 -0400
-Subject: [PATCH 1030/1110] drm/amd/powerplay: revise reading/writing pptable
- on Polaris10
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 31 +++++++++++++++++++---
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h  |  3 +++
- 2 files changed, 30 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 3e59a87..d9948c0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -2560,6 +2560,13 @@ int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
- 
- int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
- {
-+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
-+
-+	if (data->soft_pp_table) {
-+		kfree(data->soft_pp_table);
-+		data->soft_pp_table = NULL;
-+	}
-+
- 	return phm_hwmgr_backend_fini(hwmgr);
- }
- 
-@@ -4750,18 +4757,34 @@ static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- 
--	*table = (char *)&data->smc_state_table;
-+	if (!data->soft_pp_table) {
-+		data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
-+		if (!data->soft_pp_table)
-+			return -ENOMEM;
-+		memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
-+				hwmgr->soft_pp_table_size);
-+	}
- 
--	return sizeof(struct SMU74_Discrete_DpmTable);
-+	*table = (char *)&data->soft_pp_table;
-+
-+	return hwmgr->soft_pp_table_size;
- }
- 
- static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- 
--	void *table = (void *)&data->smc_state_table;
-+	if (!data->soft_pp_table) {
-+		data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
-+		if (!data->soft_pp_table)
-+			return -ENOMEM;
-+	}
-+
-+	memcpy(data->soft_pp_table, buf, size);
-+
-+	hwmgr->soft_pp_table = data->soft_pp_table;
- 
--	memcpy(table, buf, size);
-+	/* TODO: re-init powerplay to implement modified pptable */
- 
- 	return 0;
- }
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-index 2507404..b022964 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-@@ -309,6 +309,9 @@ struct polaris10_hwmgr {
- 	uint32_t                           up_hyst;
- 	uint32_t disable_dpm_mask;
- 	bool apply_optimized_settings;
-+
-+	/* soft pptable for re-uploading into smu */
-+	void *soft_pp_table;
- };
- 
- /* To convert to Q8.8 format for firmware */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1031-drm-amd-dal-fix-4th-pipe-disable.patch b/common/recipes-kernel/linux/files/1031-drm-amd-dal-fix-4th-pipe-disable.patch
deleted file mode 100644
index 9d1794f4..00000000
--- a/common/recipes-kernel/linux/files/1031-drm-amd-dal-fix-4th-pipe-disable.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 8e1a35537072e4d892e324944486cc11ced043cc Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Fri, 8 Apr 2016 17:39:26 -0400
-Subject: [PATCH 1031/1110] drm/amd/dal: fix 4th pipe disable
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 6778c75..52d9094 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1129,9 +1129,6 @@ static void reset_single_pipe_hw_ctx(
- {
- 	struct dc_bios *dcb;
- 
--	if (pipe_ctx->pipe_idx == DCE110_UNDERLAY_IDX)
--		return;
--
- 	dcb = dal_adapter_service_get_bios_parser(
- 			context->res_ctx.pool.adapter_srv);
- 	if (pipe_ctx->audio) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1032-drm-amd-dal-Pass-size-into-scaler-and-mpc-bypass.patch b/common/recipes-kernel/linux/files/1032-drm-amd-dal-Pass-size-into-scaler-and-mpc-bypass.patch
deleted file mode 100644
index 994a11d8..00000000
--- a/common/recipes-kernel/linux/files/1032-drm-amd-dal-Pass-size-into-scaler-and-mpc-bypass.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From 6ed2e9a119f383c2bb812540982e1722d0805af3 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 30 Mar 2016 10:06:19 -0400
-Subject: [PATCH 1032/1110] drm/amd/dal: Pass size into scaler and mpc bypass
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c  | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h     | 4 +++-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c | 6 ++++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c   | 4 +++-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h       | 4 +++-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c   | 6 ++++--
- drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h            | 3 ++-
- 7 files changed, 20 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 52d9094..b7c6a51 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1146,7 +1146,7 @@ static void reset_single_pipe_hw_ctx(
- 	pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
- 	pipe_ctx->mi->funcs->free_mem_input(
- 				pipe_ctx->mi, context->target_count);
--	pipe_ctx->xfm->funcs->transform_set_scaler_bypass(pipe_ctx->xfm);
-+	pipe_ctx->xfm->funcs->transform_set_scaler_bypass(pipe_ctx->xfm, NULL);
- 	resource_unreference_clock_source(&context->res_ctx, pipe_ctx->clock_source);
- 	dc->hwss.enable_display_power_gating(
- 		pipe_ctx->stream->ctx, pipe_ctx->pipe_idx, dcb,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index f97d7ab..fdde463 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -56,7 +56,9 @@ bool dce110_transform_set_scaler(
- 	struct transform *xfm,
- 	const struct scaler_data *data);
- 
--void dce110_transform_set_scaler_bypass(struct transform *xfm);
-+void dce110_transform_set_scaler_bypass(
-+		struct transform *xfm,
-+		struct rect *size);
- 
- void dce110_transform_set_scaler_filter(
- 	struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index 65f9e01..67dd983 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -90,7 +90,7 @@ static bool setup_scaling_configuration(
- 	dm_write_reg(ctx, addr, value);
- 
- 	if (data->taps.h_taps + data->taps.v_taps <= 2) {
--		dce110_transform_set_scaler_bypass(&xfm110->base);
-+		dce110_transform_set_scaler_bypass(&xfm110->base, NULL);
- 		return false;
- 	}
- 
-@@ -684,7 +684,9 @@ bool dce110_transform_set_scaler(
- 	return true;
- }
- 
--void dce110_transform_set_scaler_bypass(struct transform *xfm)
-+void dce110_transform_set_scaler_bypass(
-+		struct transform *xfm,
-+		struct rect *size)
- {
- 	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- 	uint32_t sclv_mode;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index 17b72e7..a3b9b20 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -453,7 +453,9 @@ static void program_scl_ratios_inits(
- 	dm_write_reg(ctx, addr, value);
- }
- 
--static void dce110_transform_v_set_scalerv_bypass(struct transform *xfm)
-+static void dce110_transform_v_set_scalerv_bypass(
-+		struct transform *xfm,
-+		struct rect *size)
- {
- 	uint32_t addr = mmSCLV_MODE;
- 	uint32_t value = dm_read_reg(xfm->ctx, addr);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-index 58b3ee4..6c151ae 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -56,7 +56,9 @@ bool dce80_transform_set_scaler(
- 	struct transform *xfm,
- 	const struct scaler_data *data);
- 
--void dce80_transform_set_scaler_bypass(struct transform *xfm);
-+void dce80_transform_set_scaler_bypass(
-+		struct transform *xfm,
-+		struct rect *size);
- 
- void dce80_transform_set_scaler_filter(
- 	struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-index 0025e05..0248b77 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-@@ -83,7 +83,7 @@ static bool setup_scaling_configuration(
- 	uint32_t value;
- 
- 	if (data->taps.h_taps + data->taps.v_taps <= 2) {
--		dce80_transform_set_scaler_bypass(&xfm80->base);
-+		dce80_transform_set_scaler_bypass(&xfm80->base, NULL);
- 		return false;
- 	}
- 
-@@ -685,7 +685,9 @@ bool dce80_transform_set_scaler(
- 	return true;
- }
- 
--void dce80_transform_set_scaler_bypass(struct transform *xfm)
-+void dce80_transform_set_scaler_bypass(
-+		struct transform *xfm,
-+		struct rect *size)
- {
- 	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- 	uint32_t sclv_mode;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-index c0fd26b..bc4e1a1 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-@@ -166,7 +166,8 @@ struct transform_funcs {
- 		const struct scaler_data *data);
- 
- 	void (*transform_set_scaler_bypass)(
--		struct transform *xfm);
-+		struct transform *xfm,
-+		struct rect *size);
- 
- 	void (*transform_set_scaler_filter)(
- 		struct transform *xfm,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1033-drm-amd-dal-Pass-viewport-into-scaler_bypass-program.patch b/common/recipes-kernel/linux/files/1033-drm-amd-dal-Pass-viewport-into-scaler_bypass-program.patch
deleted file mode 100644
index 716e5dbc..00000000
--- a/common/recipes-kernel/linux/files/1033-drm-amd-dal-Pass-viewport-into-scaler_bypass-program.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 331aaf46b7534e635428b17e1e458236e72dfa8e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 5 Apr 2016 15:19:36 -0400
-Subject: [PATCH 1033/1110] drm/amd/dal: Pass viewport into scaler_bypass
- programming code
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h     | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c   | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h       | 2 +-
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c   | 4 ++--
- drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h            | 2 +-
- 6 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-index fdde463..6fa273c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
-@@ -58,7 +58,7 @@ bool dce110_transform_set_scaler(
- 
- void dce110_transform_set_scaler_bypass(
- 		struct transform *xfm,
--		struct rect *size);
-+		const struct rect *size);
- 
- void dce110_transform_set_scaler_filter(
- 	struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-index 67dd983..3bc450c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
-@@ -90,7 +90,7 @@ static bool setup_scaling_configuration(
- 	dm_write_reg(ctx, addr, value);
- 
- 	if (data->taps.h_taps + data->taps.v_taps <= 2) {
--		dce110_transform_set_scaler_bypass(&xfm110->base, NULL);
-+		dce110_transform_set_scaler_bypass(&xfm110->base, &data->viewport);
- 		return false;
- 	}
- 
-@@ -686,7 +686,7 @@ bool dce110_transform_set_scaler(
- 
- void dce110_transform_set_scaler_bypass(
- 		struct transform *xfm,
--		struct rect *size)
-+		const struct rect *size)
- {
- 	struct dce110_transform *xfm110 = TO_DCE110_TRANSFORM(xfm);
- 	uint32_t sclv_mode;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-index a3b9b20..5312037 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
-@@ -455,7 +455,7 @@ static void program_scl_ratios_inits(
- 
- static void dce110_transform_v_set_scalerv_bypass(
- 		struct transform *xfm,
--		struct rect *size)
-+		const struct rect *size)
- {
- 	uint32_t addr = mmSCLV_MODE;
- 	uint32_t value = dm_read_reg(xfm->ctx, addr);
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-index 6c151ae..fc6eb4b 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.h
-@@ -58,7 +58,7 @@ bool dce80_transform_set_scaler(
- 
- void dce80_transform_set_scaler_bypass(
- 		struct transform *xfm,
--		struct rect *size);
-+		const struct rect *size);
- 
- void dce80_transform_set_scaler_filter(
- 	struct transform *xfm,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-index 0248b77..3134446 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
-@@ -83,7 +83,7 @@ static bool setup_scaling_configuration(
- 	uint32_t value;
- 
- 	if (data->taps.h_taps + data->taps.v_taps <= 2) {
--		dce80_transform_set_scaler_bypass(&xfm80->base, NULL);
-+		dce80_transform_set_scaler_bypass(&xfm80->base, &data->viewport);
- 		return false;
- 	}
- 
-@@ -687,7 +687,7 @@ bool dce80_transform_set_scaler(
- 
- void dce80_transform_set_scaler_bypass(
- 		struct transform *xfm,
--		struct rect *size)
-+		const struct rect *size)
- {
- 	struct dce80_transform *xfm80 = TO_DCE80_TRANSFORM(xfm);
- 	uint32_t sclv_mode;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-index bc4e1a1..02c05f3 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
-@@ -167,7 +167,7 @@ struct transform_funcs {
- 
- 	void (*transform_set_scaler_bypass)(
- 		struct transform *xfm,
--		struct rect *size);
-+		const struct rect *size);
- 
- 	void (*transform_set_scaler_filter)(
- 		struct transform *xfm,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1034-drm-amd-dal-fix-corruption-before-first-flip-upon-S3.patch b/common/recipes-kernel/linux/files/1034-drm-amd-dal-fix-corruption-before-first-flip-upon-S3.patch
deleted file mode 100644
index a8f11370..00000000
--- a/common/recipes-kernel/linux/files/1034-drm-amd-dal-fix-corruption-before-first-flip-upon-S3.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From 074d0648329a4318ae292b6f78ee28aae15b801f Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Fri, 8 Apr 2016 16:14:46 -0400
-Subject: [PATCH 1034/1110] drm/amd/dal: fix corruption before first flip upon
- S3 resume
-
-Previously we erroneously double pin every fb at each flip because
-the pageflip run through same code path as mode set (atomic commit).
-This causes the pin count to remain above 0 when we try to unpin
-the front buffer during suspend, since the buffer remains pinned
-it was not evicted and once vram lose power during S3 all the data
-was lost. On resume we will show this fb that was destroyed by
-losing power until the next flip since it is still pinned.
-
-The new behaviour after this change is we do not double pin on flip,
-allowing the front buffer to be evicted on suspend. Then on resume
-we do an extra pin in dm_display_resume to bring the pin count from
-0 back to 1, this causes the framebuffer to be restored into vram,
-allowing us to show the correct surface.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c      | 46 +++++++++++++++++++++-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 18 +++++++--
- 2 files changed, 59 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 468c4ba..35cecbc 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -546,11 +546,55 @@ static int dm_display_resume(struct drm_device *ddev)
- 
- 	/* Attach planes to drm_atomic_state */
- 	list_for_each_entry(plane, &ddev->mode_config.plane_list, head) {
--		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, plane));
-+
-+		struct drm_crtc *crtc;
-+		struct drm_gem_object *obj;
-+		struct drm_framebuffer *fb;
-+		struct amdgpu_framebuffer *afb;
-+		struct amdgpu_bo *rbo;
-+		int r;
-+		struct drm_plane_state *plane_state = drm_atomic_get_plane_state(state, plane);
-+
-+		ret = PTR_ERR_OR_ZERO(plane_state);
- 		if (ret)
- 			goto err;
-+
-+		crtc = plane_state->crtc;
-+		fb = plane_state->fb;
-+
-+		if (!crtc || !crtc->state || !crtc->state->active)
-+			continue;
-+
-+		if (!fb) {
-+			DRM_DEBUG_KMS("No FB bound\n");
-+			return 0;
-+		}
-+
-+		/*
-+		 * Pin back the front buffers, cursor buffer was already pinned
-+		 * back in amdgpu_resume_kms
-+		 */
-+
-+		afb = to_amdgpu_framebuffer(fb);
-+
-+		obj = afb->obj;
-+		rbo = gem_to_amdgpu_bo(obj);
-+		r = amdgpu_bo_reserve(rbo, false);
-+		if (unlikely(r != 0))
-+		       return r;
-+
-+		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
-+
-+		amdgpu_bo_unreserve(rbo);
-+
-+		if (unlikely(r != 0)) {
-+			DRM_ERROR("Failed to pin framebuffer\n");
-+			return r;
-+		}
-+
- 	}
- 
-+
- 	/* Call commit internally with the state we just constructed */
- 	ret = drm_atomic_commit(state);
- 	if (!ret)
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 8ad78f5..3e5c85d 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2111,9 +2111,17 @@ int amdgpu_dm_atomic_commit(
- 
- 	/* In this step all new fb would be pinned */
- 
--	ret = drm_atomic_helper_prepare_planes(dev, state);
--	if (ret)
--		return ret;
-+	/*
-+	 * TODO: Revisit when we support true asynchronous commit.
-+	 * Right now we receive async commit only from pageflip, in which case
-+	 * we should not pin/unpin the fb here, it should be done in
-+	 * amdgpu_crtc_flip and from the vblank irq handler.
-+	 */
-+	if (!async) {
-+		ret = drm_atomic_helper_prepare_planes(dev, state);
-+		if (ret)
-+			return ret;
-+	}
- 
- 	/*
- 	 * This is the point of no return - everything below never fails except
-@@ -2339,7 +2347,9 @@ int amdgpu_dm_atomic_commit(
- 
- 	/* In this state all old framebuffers would be unpinned */
- 
--	drm_atomic_helper_cleanup_planes(dev, state);
-+	/* TODO: Revisit when we support true asynchronous commit.*/
-+	if (!async)
-+		drm_atomic_helper_cleanup_planes(dev, state);
- 
- 	drm_atomic_state_free(state);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1035-drm-amd-dal-fix-S3-wake-up-to-headless-state.patch b/common/recipes-kernel/linux/files/1035-drm-amd-dal-fix-S3-wake-up-to-headless-state.patch
deleted file mode 100644
index c54aa23c..00000000
--- a/common/recipes-kernel/linux/files/1035-drm-amd-dal-fix-S3-wake-up-to-headless-state.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 7809a270928e40a4dd06bc0036cf6a6b210f194d Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 14 Apr 2016 17:54:08 -0400
-Subject: [PATCH 1035/1110] drm/amd/dal: fix S3 wake up to headless state
-
-Previously only the following headless case was tested:
-1 display->headless->suspend->1 display->resume
-
-The following case was not working:
-1 display->Suspend->headless->resume->1 display
-
-This change fixes the second headless scenario.
-
-This change also fixes an intermittent black screen on
-resume without topology change which was caused
-by detection detecting a false HPD low at resume, turning
-it into the same use case as second case above
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c       | 17 -----------------
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c |  6 ++++--
- 2 files changed, 4 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 35cecbc..a989fc2 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -512,9 +512,6 @@ static int dm_display_resume(struct drm_device *ddev)
- 		ret = PTR_ERR_OR_ZERO(conn_state);
- 		if (ret)
- 			goto err;
--
--		if (!aconnector->dc_sink)
--			conn_state->crtc = NULL;
- 	}
- 
- 	/* Attach crtcs to drm_atomic_state*/
-@@ -526,20 +523,6 @@ static int dm_display_resume(struct drm_device *ddev)
- 		if (ret)
- 			goto err;
- 
--		aconnector =
--			amdgpu_dm_find_first_crct_matching_connector(
--				state,
--				crtc,
--				true);
--
--		/*
--		 * this is the case when display disappear during sleep
--		 */
--		if (!aconnector) {
--			crtc_state->active = false;
--			crtc_state->enable = false;
--		}
--
- 		/* force a restore */
- 		crtc_state->mode_changed = true;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 3e5c85d..205d4a4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2185,8 +2185,11 @@ int amdgpu_dm_atomic_commit(
- 				 *
- 				 * This can also happen when unplug is done
- 				 * during resume sequence ended
-+				 *
-+				 * In this case, we want to pretend we still
-+				 * have a sink to keep the pipe running so that
-+				 * hw state is consistent with the sw state
- 				 */
--				new_state->planes_changed = false;
- 				DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n",
- 						__func__, acrtc->base.base.id);
- 				break;
-@@ -2372,7 +2375,6 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
- 	struct dc_target *current_target;
- 	uint32_t commit_targets_count = 0;
- 
--
- 	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
- 		return;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1036-drm-amd-dal-Obtain-stream-encoders-number-in-proper-.patch b/common/recipes-kernel/linux/files/1036-drm-amd-dal-Obtain-stream-encoders-number-in-proper-.patch
deleted file mode 100644
index 758a4d59..00000000
--- a/common/recipes-kernel/linux/files/1036-drm-amd-dal-Obtain-stream-encoders-number-in-proper-.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 97cb83179f200937642d749f3ce7be9421437bd5 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 13 Apr 2016 16:54:02 -0400
-Subject: [PATCH 1036/1110] drm/amd/dal: Obtain stream encoders number in
- proper way.
-
-Stream encoders number was hard coded to 6 while Baffin has 5.
-This would lead to using the 6th invalid encoder for daisy chained
-second display.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-index c1fb291..5cf61bd 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-@@ -1222,7 +1222,7 @@ bool dce112_construct_resource_pool(
- 
- 	pool->pipe_count =
- 		dal_adapter_service_get_func_controllers_num(adapter_serv);
--	pool->stream_enc_count = 6;
-+	pool->stream_enc_count = dal_adapter_service_get_stream_engines_num(adapter_serv);
- 	pool->scaler_filter = dal_scaler_filter_create(ctx);
- 	if (pool->scaler_filter == NULL) {
- 		BREAK_TO_DEBUGGER();
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch b/common/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch
deleted file mode 100644
index fb9cdf84..00000000
--- a/common/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From 7c2dd404575e941111d71b7b340c8e635e01f256 Mon Sep 17 00:00:00 2001
-From: Rex Zhu <Rex.Zhu@amd.com>
-Date: Wed, 20 Apr 2016 15:59:49 +0800
-Subject: [PATCH 1037/1110] drm/amd/powerplay: ensure clock level set by user
- is valid.
-
-Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c      | 16 +++++++++++++---
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 14 +++++++++++---
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c     | 14 +++++++++++---
- 3 files changed, 35 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 3334a89..55e877c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -5153,20 +5153,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
- 		if (!data->sclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					mask);
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
- 		break;
-+
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					mask);
-+					data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
- 		break;
-+
- 	case PP_PCIE:
-+	{
-+		uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+		uint32_t level = 0;
-+
-+		while (tmp >>= 1)
-+			level++;
-+
- 		if (!data->pcie_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
--					mask);
-+					level);
- 		break;
-+	}
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index d9948c0..b146ec8 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -4802,20 +4802,28 @@ static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
- 		if (!data->sclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					mask);
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
- 		break;
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					mask);
-+					data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
- 		break;
- 	case PP_PCIE:
-+	{
-+		uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+		uint32_t level = 0;
-+
-+		while (tmp >>= 1)
-+			level++;
-+
- 		if (!data->pcie_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
--					mask);
-+					level);
- 		break;
-+	}
- 	default:
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index bc61c07..28f5c65 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -6100,20 +6100,28 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
- 		if (!data->sclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
--					mask);
-+					data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
- 		break;
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
--					mask);
-+					data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
- 		break;
- 	case PP_PCIE:
-+	{
-+		uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
-+		uint32_t level = 0;
-+
-+		while (tmp >>= 1)
-+			level++;
-+
- 		if (!data->pcie_dpm_key_disabled)
- 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
--					mask);
-+					level);
- 		break;
-+	}
- 	default:
- 		break;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1038-drm-amd-powerplay-enable-powerplay-as-default-on-CZ-.patch b/common/recipes-kernel/linux/files/1038-drm-amd-powerplay-enable-powerplay-as-default-on-CZ-.patch
deleted file mode 100644
index 4b8f13e3..00000000
--- a/common/recipes-kernel/linux/files/1038-drm-amd-powerplay-enable-powerplay-as-default-on-CZ-.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 405d4590c38312c75d64fa60189905f90f156222 Mon Sep 17 00:00:00 2001
-From: Huang Rui <ray.huang@amd.com>
-Date: Mon, 18 Apr 2016 23:29:32 +0800
-Subject: [PATCH 1038/1110] drm/amd/powerplay: enable powerplay as default on
- CZ/ST
-
-Enable powerplay as default on Carrizo and Stoney. And it can be
-disabled with amdgpu.powerplay=0.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Huang Rui <ray.huang@amd.com>
-Cc: Rex Zhu <Rex.Zhu@amd.com>
-Cc: Flora Cui <Flora.Cui@amd.com>
-Cc: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index be56595..86cdede 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -105,11 +105,9 @@ static int amdgpu_pp_early_init(void *handle)
- 		break;
- 	case CHIP_TONGA:
- 	case CHIP_FIJI:
--		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
--		break;
- 	case CHIP_CARRIZO:
- 	case CHIP_STONEY:
--		adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
-+		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
- 		break;
- 	/* These chips don't have powerplay implemenations */
- 	case CHIP_BONAIRE:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1039-drm-amdgpu-print-a-message-if-ATPX-dGPU-power-contro.patch b/common/recipes-kernel/linux/files/1039-drm-amdgpu-print-a-message-if-ATPX-dGPU-power-contro.patch
deleted file mode 100644
index 28a4fd8f..00000000
--- a/common/recipes-kernel/linux/files/1039-drm-amdgpu-print-a-message-if-ATPX-dGPU-power-contro.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From b6a77ba390852ca3da5c1d76a8290d068d04349e Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 25 Apr 2016 13:14:47 -0400
-Subject: [PATCH 1039/1110] drm/amdgpu: print a message if ATPX dGPU power
- control is missing
-
-It will help identify problematic boards.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-index 3c89586..4e38622 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-@@ -144,7 +144,10 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
- {
- 	/* make sure required functions are enabled */
- 	/* dGPU power control is required */
--	atpx->functions.power_cntl = true;
-+	if (atpx->functions.power_cntl == false) {
-+		printk("ATPX dGPU power cntl not present, forcing\n");
-+		atpx->functions.power_cntl = true;
-+	}
- 
- 	if (atpx->functions.px_params) {
- 		union acpi_object *info;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1040-drm-amdgpu-disable-vm-interrupts-with-vm_fault_stop-.patch b/common/recipes-kernel/linux/files/1040-drm-amdgpu-disable-vm-interrupts-with-vm_fault_stop-.patch
deleted file mode 100644
index d6a10321..00000000
--- a/common/recipes-kernel/linux/files/1040-drm-amdgpu-disable-vm-interrupts-with-vm_fault_stop-.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 6010c8df31c8c7ca652359811a3acc6766ab7a7b Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Mon, 25 Apr 2016 16:06:17 +0800
-Subject: [PATCH 1040/1110] drm/amdgpu: disable vm interrupts with
- vm_fault_stop=2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-V2: disable all vm interrupts in late_init()
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 ++++-
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 ++++-
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index 2037218..cae8f26 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -910,7 +910,10 @@ static int gmc_v7_0_late_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
-+	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
-+		return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
-+	else
-+		return 0;
- }
- 
- static int gmc_v7_0_sw_init(void *handle)
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index aeb753e..4abcf0d 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -905,7 +905,10 @@ static int gmc_v8_0_late_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
-+	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
-+		return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
-+	else
-+		return 0;
- }
- 
- #define mmMC_SEQ_MISC0_FIJI 0xA71
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1041-drm-amd-powerplay-hwmgr-prevent-VDDC-from-exceeding-.patch b/common/recipes-kernel/linux/files/1041-drm-amd-powerplay-hwmgr-prevent-VDDC-from-exceeding-.patch
deleted file mode 100644
index e30ff922..00000000
--- a/common/recipes-kernel/linux/files/1041-drm-amd-powerplay-hwmgr-prevent-VDDC-from-exceeding-.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 3a81868dcafd1b133fe5136440da80eac463a3b7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Moritz=20K=C3=BChner?= <kuehner.moritz@gmail.com>
-Date: Sun, 17 Apr 2016 16:15:23 +0200
-Subject: [PATCH 1041/1110] drm/amd/powerplay/hwmgr: prevent VDDC from
- exceeding 2V
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If the tonga gpu is controlled by SVID2 tonga_get_evv_voltage will only print
-an error if the voltage exceeds 2V although a comment clearly states that it
-needs be less than 2V.
-
-v2: added signed of by
-
-Signed-off-by: Moritz Kühner <kuehner.moritz@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 28f5c65..59dd78c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -458,8 +458,7 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
- 						"Error retrieving EVV voltage value!", continue);
- 
- 				/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
--				if (vddc > 2000)
--					printk(KERN_ERR "[ powerplay ] Invalid VDDC value! \n");
-+				PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
- 
- 				/* the voltage should not be zero nor equal to leakage ID */
- 				if (vddc != 0 && vddc != virtual_voltage_id) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1042-drm-amd-powerplay-hwmgr-don-t-add-invalid-voltage.patch b/common/recipes-kernel/linux/files/1042-drm-amd-powerplay-hwmgr-don-t-add-invalid-voltage.patch
deleted file mode 100644
index 1fe6b6e0..00000000
--- a/common/recipes-kernel/linux/files/1042-drm-amd-powerplay-hwmgr-don-t-add-invalid-voltage.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 636cb506132bcc77950d73d0e0aa7e2694e4d373 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Moritz=20K=C3=BChner?= <kuehner.moritz@gmail.com>
-Date: Sun, 17 Apr 2016 16:15:24 +0200
-Subject: [PATCH 1042/1110] drm/amd/powerplay/hwmgr: don't add invalid voltage
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-if atomctrl_get_voltage_evv_on_sclk returns non zero (fail) in the expansion
-of the PP_ASSERT_WITH_CODE macro the continue will actually do nothing
-(The macro uses a do ... while(0) as scope, which eats the continue).
-Based on the code I don't think this was the intent.
-Unfortunately fixing this requires rewriting the control flow and
-removing the macros.
-
-v2: added signed of by
-fixed error message print
-
-v3: agd: drop DRM_ERROR
-
-Signed-off-by: Moritz Kühner <kuehner.moritz@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 54 ++++++++++++-----------
- 1 file changed, 28 insertions(+), 26 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 59dd78c..9aaf194 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -432,19 +432,20 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
- 						}
- 					}
- 				}
--				PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
--						(hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
--						 virtual_voltage_id, &vddgfx),
--						"Error retrieving EVV voltage value!", continue);
--
--				/* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
--				PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
--
--				/* the voltage should not be zero nor equal to leakage ID */
--				if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
--					data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
--					data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
--					data->vddcgfx_leakage.count++;
-+				if (0 == atomctrl_get_voltage_evv_on_sclk
-+				    (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
-+				     virtual_voltage_id, &vddgfx)) {
-+					/* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
-+					PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
-+
-+					/* the voltage should not be zero nor equal to leakage ID */
-+					if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
-+						data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
-+						data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
-+						data->vddcgfx_leakage.count++;
-+					}
-+				} else {
-+					printk("Error retrieving EVV voltage value!\n");
- 				}
- 			}
- 		} else {
-@@ -452,19 +453,20 @@ int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
- 			if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
- 						pptable_info->vddc_lookup_table,
- 						virtual_voltage_id, &sclk)) {
--				PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
--						(hwmgr, VOLTAGE_TYPE_VDDC, sclk,
--						 virtual_voltage_id, &vddc),
--						"Error retrieving EVV voltage value!", continue);
--
--				/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
--				PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
--
--				/* the voltage should not be zero nor equal to leakage ID */
--				if (vddc != 0 && vddc != virtual_voltage_id) {
--					data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
--					data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
--					data->vddc_leakage.count++;
-+				if (0 == atomctrl_get_voltage_evv_on_sclk
-+				    (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
-+				     virtual_voltage_id, &vddc)) {
-+					/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
-+					PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
-+
-+					/* the voltage should not be zero nor equal to leakage ID */
-+					if (vddc != 0 && vddc != virtual_voltage_id) {
-+						data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
-+						data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
-+						data->vddc_leakage.count++;
-+					}
-+				} else {
-+					printk("Error retrieving EVV voltage value!\n");
- 				}
- 			}
- 		}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1043-drm-amd-powerplay-Delete-dead-struct-declaration.patch b/common/recipes-kernel/linux/files/1043-drm-amd-powerplay-Delete-dead-struct-declaration.patch
deleted file mode 100644
index e4625426..00000000
--- a/common/recipes-kernel/linux/files/1043-drm-amd-powerplay-Delete-dead-struct-declaration.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 4da6ca36bd1cac36ed12ace94a3274ec06bd52a6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Sun, 24 Apr 2016 13:21:27 +0200
-Subject: [PATCH 1043/1110] drm/amd/powerplay: Delete dead struct declaration
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-index 35e1b36..1954cea 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h
-@@ -29,7 +29,6 @@
- 
- extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
- extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
--extern struct phm_master_table_header cz_phm_disable_clock_power_gatings_master;
- extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
- extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
- extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1044-drm-amdgpu-Constify-some-tables.patch b/common/recipes-kernel/linux/files/1044-drm-amdgpu-Constify-some-tables.patch
deleted file mode 100644
index ea64cd44..00000000
--- a/common/recipes-kernel/linux/files/1044-drm-amdgpu-Constify-some-tables.patch
+++ /dev/null
@@ -1,255 +0,0 @@
-From 264aae9e6b02b5ae5a051f518abd01eb489dfa6b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
-Date: Mon, 25 Apr 2016 21:31:34 +0200
-Subject: [PATCH 1044/1110] drm/amdgpu: Constify some tables
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some more tables with constant data were added with the polaris support
-
-v2: missed a few
-
-Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 32 ++++++++++++----------
- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h  |  2 +-
- .../drm/amd/powerplay/hwmgr/polaris10_powertune.c  | 14 +++++-----
- .../drm/amd/powerplay/hwmgr/polaris10_thermal.c    |  8 +++---
- .../gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h |  2 +-
- .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    | 11 ++++----
- 6 files changed, 36 insertions(+), 33 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index b146ec8..010199f 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -99,16 +99,17 @@
- #define TCLK                        (PCIE_BUS_CLK / 10)
- 
- 
--uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
--							  {600, 1050, 6, 1} };
-+static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
-+{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
- 
- /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
--uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
--							{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-+static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
-+{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+  { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
- 
- /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
--uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
--							    {0, 2, 4, 5, 6, 5} };
-+static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
-+{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
- 
- /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
- enum DPM_EVENT_SRC {
-@@ -119,7 +120,7 @@ enum DPM_EVENT_SRC {
- 	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
- };
- 
--const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
-+static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
- 
- struct polaris10_power_state *cast_phw_polaris10_power_state(
- 				  struct pp_hw_power_state *hw_ps)
-@@ -1069,14 +1070,15 @@ static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
- 	return 0;
- }
- 
--sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
--						{VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
--						{VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
--						{VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
--						{VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
--						{VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
--						{VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
--						{VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
-+static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
-+{ {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
-+  {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
-+  {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
-+  {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
-+  {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
-+  {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
-+  {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
-+  {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
- 
- static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
- {
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-index b022964..beedf35 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
-@@ -264,7 +264,7 @@ struct polaris10_hwmgr {
- 	bool                           enable_tdc_limit_feature;
- 	bool                           enable_pkg_pwr_tracking_feature;
- 	bool                           disable_uvd_power_tune_feature;
--	struct polaris10_pt_defaults       *power_tune_defaults;
-+	const struct polaris10_pt_defaults       *power_tune_defaults;
- 	struct SMU74_Discrete_PmFuses  power_tune_table;
- 	uint32_t                       dte_tj_offset;
- 	uint32_t                       fast_watermark_threshold;
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-index 02bcedc..0b99ab3 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
-@@ -32,7 +32,7 @@
- #define VOLTAGE_SCALE  4
- #define POWERTUNE_DEFAULT_SET_MAX    1
- 
--struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
- 	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
- 	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
- 	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-@@ -67,7 +67,7 @@ static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
- int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
--	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
- 	SMU74_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
- 	struct phm_ppt_v1_information *table_info =
- 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-@@ -75,8 +75,8 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- 	struct pp_advance_fan_control_parameters *fan_table=
- 			&hwmgr->thermal_controller.advanceFanControlParameters;
- 	int i, j, k;
--	uint16_t *pdef1;
--	uint16_t *pdef2;
-+	const uint16_t *pdef1;
-+	const uint16_t *pdef2;
- 
- 	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
- 	dpm_table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-@@ -114,7 +114,7 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
- static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
--	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
- 
- 	data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
- 	data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-@@ -130,7 +130,7 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- 	struct phm_ppt_v1_information *table_info =
- 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
--	struct  polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
- 
- 	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
- 	data->power_tune_table.TDC_VDDC_PkgLimit =
-@@ -145,7 +145,7 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
- static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
- {
- 	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
--	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
-+	const struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
- 	uint32_t temp;
- 
- 	if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-index d39c89b..956e00c 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
-@@ -638,7 +638,7 @@ static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
- 	return ret;
- }
- 
--static struct phm_master_table_item
-+static const struct phm_master_table_item
- polaris10_thermal_start_thermal_controller_master_list[] = {
- 	{NULL, tf_polaris10_thermal_initialize},
- 	{NULL, tf_polaris10_thermal_set_temperature_range},
-@@ -654,14 +654,14 @@ polaris10_thermal_start_thermal_controller_master_list[] = {
- 	{NULL, NULL}
- };
- 
--static struct phm_master_table_header
-+static const struct phm_master_table_header
- polaris10_thermal_start_thermal_controller_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
- 	polaris10_thermal_start_thermal_controller_master_list
- };
- 
--static struct phm_master_table_item
-+static const struct phm_master_table_item
- polaris10_thermal_set_temperature_range_master_list[] = {
- 	{NULL, tf_polaris10_thermal_disable_alert},
- 	{NULL, tf_polaris10_thermal_set_temperature_range},
-@@ -669,7 +669,7 @@ polaris10_thermal_set_temperature_range_master_list[] = {
- 	{NULL, NULL}
- };
- 
--struct phm_master_table_header
-+static const struct phm_master_table_header
- polaris10_thermal_set_temperature_range_master = {
- 	0,
- 	PHM_MasterTableFlag_None,
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
-index 933103e..f497e7d 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
-@@ -50,7 +50,7 @@ typedef struct PWR_Command_Table PWR_Command_Table;
- 
- #define PWR_VIRUS_TABLE_SIZE  10031
- 
--static PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
-+static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
- 	{ PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
- 	{ PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
- 	{ PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
-diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
-index 667e055..de618ea 100644
---- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
-@@ -49,7 +49,7 @@
- 
- #define SMC_RAM_END 0x40000
- 
--SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
-+static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
- 	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
- 	/* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
- 	{ 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
-@@ -62,8 +62,9 @@ SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
- 	{ 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
- };
- 
--SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
--							0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
-+static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 =
-+	{0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
-+	 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
- 
- /**
- * Set the address for reading/writing the SMC SRAM space.
-@@ -200,7 +201,7 @@ int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
- 
- static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
- {
--	static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
-+	static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
- 
- 	polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
- 
-@@ -616,7 +617,7 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
- 	int result = -1;
- 	uint32_t reg, data;
- 
--	PWR_Command_Table *pvirus = pwr_virus_table;
-+	const PWR_Command_Table *pvirus = pwr_virus_table;
- 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
- 
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1045-drm-amd-amdgpu-Re-fix-debugfs-for-ring-entries.patch b/common/recipes-kernel/linux/files/1045-drm-amd-amdgpu-Re-fix-debugfs-for-ring-entries.patch
deleted file mode 100644
index fe02c865..00000000
--- a/common/recipes-kernel/linux/files/1045-drm-amd-amdgpu-Re-fix-debugfs-for-ring-entries.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 5d0daa21b8cf4858c366af8e91a50a1509fc790b Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 26 Apr 2016 14:23:02 -0400
-Subject: [PATCH 1045/1110] drm/amd/amdgpu: Re-fix debugfs for ring entries
-
-Based on Alex's rebase patch but also cleans up the
-debugfs ring init function.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 37 +++++++++++++++++---------------
- 1 file changed, 20 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index bb4ec76..3b02272 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -369,9 +369,8 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- 	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 	struct drm_device *dev = node->minor->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
--	int roffset = *(int*)node->info_ent->data;
-+	int roffset = (unsigned long)node->info_ent->data;
- 	struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset);
--
- 	uint32_t rptr, wptr, rptr_next;
- 	unsigned i;
- 
-@@ -415,7 +414,7 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
- }
- 
- static struct drm_info_list amdgpu_debugfs_ring_info_list[AMDGPU_MAX_RINGS];
--static char amdgpu_debugs_ring_names[AMDGPU_MAX_RINGS][32];
-+static char amdgpu_debugfs_ring_names[AMDGPU_MAX_RINGS][32];
- 
- #endif
- 
-@@ -425,22 +424,26 @@ static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
- #if defined(CONFIG_DEBUG_FS)
- 	unsigned offset = (uint8_t*)ring - (uint8_t*)adev;
- 	unsigned i;
-+	struct drm_info_list *info;
-+	char *name;
- 
- 	for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
--		struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
--		char *name = amdgpu_debugs_ring_names[i];
--
--		if (!info->data) {
--			sprintf(name, "amdgpu_ring_%s", ring->name);
--			info->name = name;
--			info->show = amdgpu_debugfs_ring_info;
--			info->driver_features = 0;
--			info->data = (void*)(uintptr_t)offset;
--		} else if (info->data != (void*)(uintptr_t)offset)
--			continue;
--
--		return amdgpu_debugfs_add_files(adev, info, 1);
-+		info = &amdgpu_debugfs_ring_info_list[i];
-+		if (!info->data)
-+			break;
- 	}
-+
-+	if (i == ARRAY_SIZE(amdgpu_debugfs_ring_info_list))
-+		return -ENOSPC;
-+
-+	name = &amdgpu_debugfs_ring_names[i][0];
-+	sprintf(name, "amdgpu_ring_%s", ring->name);
-+	info->name = name;
-+	info->show = amdgpu_debugfs_ring_info;
-+	info->driver_features = 0;
-+	info->data = (void*)(uintptr_t)offset;
-+
-+	return amdgpu_debugfs_add_files(adev, info, 1);
- #endif
--	return -ENOSPC;
-+	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1046-drm-amdgpu-fix-wrong-release-of-vmid-owner.patch b/common/recipes-kernel/linux/files/1046-drm-amdgpu-fix-wrong-release-of-vmid-owner.patch
deleted file mode 100644
index 8f2e4173..00000000
--- a/common/recipes-kernel/linux/files/1046-drm-amdgpu-fix-wrong-release-of-vmid-owner.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 6bd1654dc4398ecfc3798b43eb265b7d06c9c903 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Mon, 25 Apr 2016 10:28:24 +0800
-Subject: [PATCH 1046/1110] drm/amdgpu: fix wrong release of vmid owner
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +++++++++-----
- 1 file changed, 9 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 4f16688..8650d61 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -1458,6 +1458,7 @@ error_free_sched_entity:
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
- 	struct amdgpu_bo_va_mapping *mapping, *tmp;
-+        struct amdgpu_vm_id *id, *id_tmp;
- 	int i;
- 
-         amd_sched_entity_fini(vm->entity.sched, &vm->entity);
-@@ -1482,14 +1483,17 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	amdgpu_bo_unref(&vm->page_directory);
- 	fence_put(vm->page_directory_fence);
- 
--	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--		struct amdgpu_vm_id *id = vm->ids[i];
--
-+        mutex_lock(&adev->vm_manager.lock);
-+        list_for_each_entry_safe(id, id_tmp, &adev->vm_manager.ids_lru,
-+                                 list) {
- 		if (!id)
- 			continue;
--
--		atomic_long_cmpxchg(&id->owner, (long)vm, 0);
-+                if (atomic_long_read(&id->owner) == (long)vm) {
-+                        atomic_long_set(&id->owner, 0);
-+                        id->pd_gpu_addr = 0;
-+                }
- 	}
-+        mutex_unlock(&adev->vm_manager.lock);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1047-drm-amdgpu-add-client-id-for-every-vm.patch b/common/recipes-kernel/linux/files/1047-drm-amdgpu-add-client-id-for-every-vm.patch
deleted file mode 100644
index ee3bd53f..00000000
--- a/common/recipes-kernel/linux/files/1047-drm-amdgpu-add-client-id-for-every-vm.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From aa211128f8afccb9a9a5f7ca3c63a9dd64a86c97 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Mon, 25 Apr 2016 10:19:13 +0800
-Subject: [PATCH 1047/1110] drm/amdgpu: add client id for every vm
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 9 +++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
- 2 files changed, 11 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 6079a39..01aab7e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -365,6 +365,7 @@ struct amdgpu_fence_driver {
- /* some special values for the owner field */
- #define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
- #define AMDGPU_FENCE_OWNER_VM		((void*)1ul)
-+#define AMDGPU_CLIENT_ID_RESERVED       2
- 
- #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
- #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
-@@ -886,6 +887,9 @@ struct amdgpu_vm {
- 
-         /* Scheduler entity for page table updates */
-         struct amd_sched_entity entity;
-+ 
-+        /* client id */
-+        u64                     client_id;
- };
- 
- struct amdgpu_vm_id {
-@@ -925,6 +929,8 @@ struct amdgpu_vm_manager {
-         struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
-         unsigned                                vm_pte_num_rings;
-         atomic_t                                vm_pte_next_ring;
-+        /* client id counter */
-+        atomic64_t                              client_counter;
- };
- 
- void amdgpu_vm_manager_init(struct amdgpu_device *adev);
-@@ -988,6 +994,9 @@ struct amdgpu_ctx_ring {
- 	uint64_t		sequence;
- 	struct fence		**fences;
- 	struct amd_sched_entity	entity;
-+
-+	/* client id */
-+	u64                     client_id;
- };
- 
- struct amdgpu_ctx {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8650d61..458d3dd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -1393,6 +1393,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
-         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-                vm->ids[i] = NULL;
- 	vm->va = RB_ROOT;
-+        vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
- 	spin_lock_init(&vm->status_lock);
- 	INIT_LIST_HEAD(&vm->invalidated);
- 	INIT_LIST_HEAD(&vm->cleared);
-@@ -1516,8 +1517,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 			      &adev->vm_manager.ids_lru);
-         }
- 
--        atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
--
-+        atomic64_set(&adev->vm_manager.client_counter, AMDGPU_CLIENT_ID_RESERVED);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1048-drm-amdgpu-make-vmid-owner-be-client_id.patch b/common/recipes-kernel/linux/files/1048-drm-amdgpu-make-vmid-owner-be-client_id.patch
deleted file mode 100644
index 66efe60a..00000000
--- a/common/recipes-kernel/linux/files/1048-drm-amdgpu-make-vmid-owner-be-client_id.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From da97f6cf375731e48b94ef4f497e0d14a60150e1 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Mon, 25 Apr 2016 10:23:34 +0800
-Subject: [PATCH 1048/1110] drm/amdgpu: make vmid owner be client_id
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 458d3dd..3a12305 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -192,7 +192,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		if (!id)
- 			continue;
- 
--		if (atomic_long_read(&id->owner) != (long)vm)
-+		if (atomic_long_read(&id->owner) != vm->client_id)
- 			continue;
- 
- 		if (pd_addr != id->pd_gpu_addr)
-@@ -268,7 +268,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 
- 	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
- 	id->last_user = ring;
--	atomic_long_set(&id->owner, (long)vm);
-+	atomic_long_set(&id->owner, vm->client_id);
- 	vm->ids[ring->idx] = id;
- 
- 	*vm_id = id - adev->vm_manager.ids;
-@@ -1489,7 +1489,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
-                                  list) {
- 		if (!id)
- 			continue;
--                if (atomic_long_read(&id->owner) == (long)vm) {
-+                if (atomic_long_read(&id->owner) == vm->client_id) {
-                         atomic_long_set(&id->owner, 0);
-                         id->pd_gpu_addr = 0;
-                 }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1049-drm-amdgpu-keep-vm-in-job-instead-of-ib.patch b/common/recipes-kernel/linux/files/1049-drm-amdgpu-keep-vm-in-job-instead-of-ib.patch
deleted file mode 100644
index 37409985..00000000
--- a/common/recipes-kernel/linux/files/1049-drm-amdgpu-keep-vm-in-job-instead-of-ib.patch
+++ /dev/null
@@ -1,303 +0,0 @@
-From 442066909f2cae3d323fb3de4f1645f62988e0f9 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Tue, 19 Apr 2016 20:11:32 +0800
-Subject: [PATCH 1049/1110] drm/amdgpu: keep vm in job instead of ib
-
-ib.vm is a legacy way to get vm, after scheduler
-implemented vm should be get from job, and all ibs
-from one job share the same vm, no need to keep ib.vm
-just move vm field to job.
-
-this patch as well add job as paramter to ib_schedule
-so it can get vm from job->vm.
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  3 ++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 15 ++++-----------
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 10 +++++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  4 ++--
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  4 ++--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  |  2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |  2 +-
- 11 files changed, 23 insertions(+), 29 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 01aab7e..35de174 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -743,7 +743,6 @@ struct amdgpu_ib {
- 	uint64_t			gpu_addr;
- 	uint32_t			*ptr;
- 	struct amdgpu_user_fence        *user;
--	struct amdgpu_vm		*vm;
-         unsigned                        vm_id;
-         uint64_t                        vm_pd_addr;
- 	struct amdgpu_ctx		*ctx;
-@@ -765,8 +764,7 @@ enum amdgpu_ring_type {
- 
- extern const struct amd_sched_backend_ops amdgpu_sched_ops;
- int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
--                             struct amdgpu_job **job);
--
-+                      struct amdgpu_job **job, struct amdgpu_vm *vm);
- void amdgpu_job_free(struct amdgpu_job *job);
- void amdgpu_job_free_func(struct kref *refcount);
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-@@ -1200,6 +1198,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
-                        struct amdgpu_ib *ib, struct fence *last_vm_update,
-+                       struct amdgpu_job *job, struct fence **f);
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
- void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
- int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
-@@ -1255,6 +1254,7 @@ struct amdgpu_cs_parser {
- struct amdgpu_job {
- 	struct amd_sched_job    base;
- 	struct amdgpu_device	*adev;
-+        struct amdgpu_vm        *vm;
-         struct amdgpu_ring      *ring;
-         struct amdgpu_sync      sync;
- 	struct amdgpu_ib	*ibs;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 55a5814..7e8b6bb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -161,6 +161,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- {
-         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-+        struct amdgpu_vm *vm = &fpriv->vm;
- 	union drm_amdgpu_cs *cs = data;
- 	uint64_t *chunk_array_user;
- 	uint64_t *chunk_array;
-@@ -259,7 +260,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		}
- 	}
- 
--        ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job);
-+        ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
-         if (ret)
-                 goto free_all_kdata;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 146b55e..1d15ac6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -74,7 +74,6 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 			ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
- 	}
- 
--	ib->vm = vm;
- 	ib->vm_id = 0;
- 
- 	return 0;
-@@ -116,13 +115,13 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fen
-  */
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
-                        struct amdgpu_ib *ibs, struct fence *last_vm_update,
--		       struct fence **f)
-+                       struct amdgpu_job *job, struct fence **f)
- {
-         struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_ib *ib = &ibs[0];
- 	struct amdgpu_ctx *ctx, *old_ctx;
--	struct amdgpu_vm *vm;
- 	struct fence *hwf;
-+        struct amdgpu_vm *vm = NULL;
-         unsigned i, patch_offset = ~0;
- 
- 	int r = 0;
-@@ -131,7 +130,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		return -EINVAL;
- 
- 	ctx = ibs->ctx;
--	vm = ibs->vm;
-+	if (job) /* for domain0 job like ring test, ibs->job is not assigned */
-+		vm = job->vm;
- 
- 	if (!ring->ready) {
- 		dev_err(adev->dev, "couldn't schedule ib\n");
-@@ -171,13 +171,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 	for (i = 0; i < num_ibs; ++i) {
- 		ib = &ibs[i];
- 
--                if (ib->ctx != ctx || ib->vm != vm) {
--			ring->current_ctx = old_ctx;
--			if (ib->vm_id)
--				amdgpu_vm_reset_id(adev, ib->vm_id);
--			amdgpu_ring_undo(ring);
--			return -EINVAL;
--		}
- 		amdgpu_ring_emit_ib(ring, ib);
- 		ring->current_ctx = ctx;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index f9e7336..50257ad 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -46,7 +46,7 @@ void amdgpu_job_timeout_func(struct work_struct *work)
- }
- 
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--                    struct amdgpu_job **job)
-+                    struct amdgpu_job **job, struct amdgpu_vm *vm)
- {
-        size_t size = sizeof(struct amdgpu_job);
- 
-@@ -60,6 +60,7 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-                return -ENOMEM;
- 
-        (*job)->adev = adev;
-+       (*job)->vm = vm;
-        (*job)->ibs = (void *)&(*job)[1];
-        (*job)->num_ibs = num_ibs;
-        INIT_WORK(&(*job)->base.work_free_job, amdgpu_job_free_handler);
-@@ -74,7 +75,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
- {
-        int r;
- 
--       r = amdgpu_job_alloc(adev, 1, job);
-+       r = amdgpu_job_alloc(adev, 1, job, NULL);
-        if (r)
-                return r;
- 
-@@ -137,8 +138,7 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
- static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
- {
-        struct amdgpu_job *job = to_amdgpu_job(sched_job);
--       struct amdgpu_vm *vm = job->ibs->vm;
--
-+       struct amdgpu_vm *vm = job->vm;
-        struct fence *fence = amdgpu_sync_get_fence(&job->sync);
- 
-        if (fence == NULL && vm && !job->ibs->vm_id) {
-@@ -185,7 +185,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
- 
-        trace_amdgpu_sched_run_job(job);
-        r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
--                              job->sync.last_vm_update, &fence);
-+                              job->sync.last_vm_update, job, &fence);
-        if (r) {
-                DRM_ERROR("Error scheduling IBs (%d)\n", r);
-                goto err;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 7327a20..7c44f74 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -924,7 +924,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
-         if (direct) {
--                r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+                r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-                 job->fence = f;
-                 if (r)
-                         goto err_free;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 199f5cb..97c3268 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -452,7 +452,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &amdgpu_vce_free_job,
- 						 AMDGPU_FENCE_OWNER_UNDEFINED,
- 						 &f);
--        r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-                  job->fence = f;
- 	if (r)
- 		goto err;
-@@ -524,7 +524,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 						 &f);
- 
-        if (direct) {
--                r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+                r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-                 if (r)
-                         goto err;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 1ae79fc..48505c9 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -643,7 +643,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[3] = 1;
- 	ib.ptr[4] = 0xDEADBEEF;
- 	ib.length_dw = 5;
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index f1842f9..ef1a800 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2136,7 +2136,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err2;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index dffa413..c2941ba 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -800,7 +800,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err2;
- 
-@@ -1551,7 +1551,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
- 
- 	/* shedule the ib on the ring */
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
- 		goto fail;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 037a425..6bfdb3f 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -701,7 +701,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index c94c266..798d39b 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -925,7 +925,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
-+        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err1;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1050-drm-amdgpu-use-fence_context-to-judge-ctx-switch.patch b/common/recipes-kernel/linux/files/1050-drm-amdgpu-use-fence_context-to-judge-ctx-switch.patch
deleted file mode 100644
index e0f4f541..00000000
--- a/common/recipes-kernel/linux/files/1050-drm-amdgpu-use-fence_context-to-judge-ctx-switch.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 9bdfa3ac3efa9e42c24cd9263a18ab7639bd4fc1 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Fri, 22 Apr 2016 18:15:44 +0800
-Subject: [PATCH 1050/1110] drm/amdgpu: use fence_context to judge ctx switch
-
-use ctx pointer is not safe, cuz they are likely already
-be assigned to another ctx when doing comparing.
-
-fence_context is always increasing and have rare chance
-to overback to used number for jobs that scheduled to
-ring continueonsly
-
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 1d15ac6..f879ffb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -119,7 +119,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- {
-         struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_ib *ib = &ibs[0];
--	struct amdgpu_ctx *ctx, *old_ctx;
-+        uint64_t fence_context = 0, old = ring->last_fence_context;
- 	struct fence *hwf;
-         struct amdgpu_vm *vm = NULL;
-         unsigned i, patch_offset = ~0;
-@@ -129,9 +129,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 	if (num_ibs == 0)
- 		return -EINVAL;
- 
--	ctx = ibs->ctx;
--	if (job) /* for domain0 job like ring test, ibs->job is not assigned */
-+	if (job) {/* for domain0 job like ring test, ibs->job is not assigned */
- 		vm = job->vm;
-+		fence_context = job->fence_context;
-+	}
- 
- 	if (!ring->ready) {
- 		dev_err(adev->dev, "couldn't schedule ib\n");
-@@ -171,19 +172,19 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 	for (i = 0; i < num_ibs; ++i) {
- 		ib = &ibs[i];
- 
--		amdgpu_ring_emit_ib(ring, ib);
--		ring->current_ctx = ctx;
-+                amdgpu_ring_emit_ib(ring, ib, (i == 0 && old != fence_context));
- 	}
- 
- 	if (vm) {
- 		if (ring->funcs->emit_hdp_invalidate)
- 			amdgpu_ring_emit_hdp_invalidate(ring);
- 	}
-+        ring->last_fence_context = fence_context;
- 
- 	r = amdgpu_fence_emit(ring, &hwf);
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
--		ring->current_ctx = old_ctx;
-+		ring->last_fence_context = old;
- 		if (ib->vm_id)
- 			amdgpu_vm_reset_id(adev, ib->vm_id);
- 		amdgpu_ring_undo(ring);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1051-drm-amd-dal-fixed-one-issue-found-by-static-analyzer.patch b/common/recipes-kernel/linux/files/1051-drm-amd-dal-fixed-one-issue-found-by-static-analyzer.patch
deleted file mode 100644
index 23c6bc25..00000000
--- a/common/recipes-kernel/linux/files/1051-drm-amd-dal-fixed-one-issue-found-by-static-analyzer.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From efb96666e1ff86e4eabc135648505d93de35019c Mon Sep 17 00:00:00 2001
-From: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Date: Tue, 19 Apr 2016 17:36:27 +0800
-Subject: [PATCH 1051/1110] drm/amd/dal: fixed one issue found by static
- analyzer
-
-Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index c2f16a9..edf0aab 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -775,10 +775,10 @@ static enum ds_color_space build_default_color_space(
- 	{
- 		uint32_t pix_clk_khz;
- 
--		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 &&
--			timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
-+		if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422 &&
-+			timing->pixel_encoding != PIXEL_ENCODING_YCBCR444) {
- 			if (timing->timing_standard ==
--					TIMING_STANDARD_CEA770 &&
-+					TIMING_STANDARD_CEA770 ||
- 				timing->timing_standard ==
- 						TIMING_STANDARD_CEA861)
- 				color_space = DS_COLOR_SPACE_SRGB_FULLRANGE;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1052-drm-amd-dal-Fix-audio-endpoints-incorrect-during-unp.patch b/common/recipes-kernel/linux/files/1052-drm-amd-dal-Fix-audio-endpoints-incorrect-during-unp.patch
deleted file mode 100644
index 0195bf7e..00000000
--- a/common/recipes-kernel/linux/files/1052-drm-amd-dal-Fix-audio-endpoints-incorrect-during-unp.patch
+++ /dev/null
@@ -1,420 +0,0 @@
-From 09f20b864f331a3e75034a5be09b4dad70fe4b6a Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 6 Apr 2016 17:15:27 -0400
-Subject: [PATCH 1052/1110] drm/amd/dal: Fix audio endpoints incorrect during
- unplug.
-
-Issue:
-Audio endpoints isn't disappears in sound setting after
-unplug a HDMI/DP monitor on Baffin.
-
-Root cause:
-During unplug, sometime pipe_ctx isn't reset at all due
-to check condition isn't enough.
-
-Solution:
-Remove unchanged and timing changed flag in pipe_ctx,
-change check condition for reset pipe_ctx.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 24 ------
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    | 20 +----
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 97 ++++++++++++++++------
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 25 +-----
- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    | 14 ----
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  | 20 +----
- 6 files changed, 74 insertions(+), 126 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index edf0aab..12e4515 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -604,23 +604,6 @@ static struct audio *find_first_free_audio(struct resource_context *res_ctx)
- 	return 0;
- }
- 
--static bool check_timing_change(struct core_stream *cur_stream,
--		struct core_stream *new_stream)
--{
--	if (cur_stream == NULL)
--		return true;
--
--	/* If sink pointer changed, it means this is a hotplug, we should do
--	 * full hw setting.
--	 */
--	if (cur_stream->sink != new_stream->sink)
--		return true;
--
--	return !resource_is_same_timing(
--					&cur_stream->public.timing,
--					&new_stream->public.timing);
--}
--
- static void set_stream_signal(struct pipe_ctx *pipe_ctx)
- {
- 	struct dc_sink *dc_sink =
-@@ -680,8 +663,6 @@ enum dc_status resource_map_pool_resources(
- 
- 				*pipe_ctx =
- 					dc->current_context.res_ctx.pipe_ctx[k];
--				pipe_ctx->flags.timing_changed = false;
--				pipe_ctx->flags.unchanged = true;
- 
- 				set_stream_engine_in_use(
- 					&context->res_ctx,
-@@ -720,8 +701,6 @@ enum dc_status resource_map_pool_resources(
- 
- 			curr_stream =
- 				dc->current_context.res_ctx.pipe_ctx[pipe_idx].stream;
--			context->res_ctx.pipe_ctx[pipe_idx].flags.timing_changed =
--				check_timing_change(curr_stream, stream);
- 
- 			pipe_ctx->stream_enc =
- 				find_first_free_match_stream_enc_for_link(
-@@ -1282,9 +1261,6 @@ enum dc_status resource_map_clock_resources(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
--				if (dc->current_context.res_ctx.pipe_ctx[k].clock_source
--					!= pipe_ctx->clock_source)
--					pipe_ctx->flags.timing_changed = true;
- 				/* only one cs per stream regardless of mpo */
- 				break;
- 			}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 5185e91..4820af7 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -765,24 +765,6 @@ enum dc_status dce100_validate_bandwidth(
- 	return DC_OK;
- }
- 
--static void set_target_unchanged(
--		struct validate_context *context,
--		uint8_t target_idx)
--{
--	uint8_t i, j;
--	struct core_target *target = context->targets[target_idx];
--	context->target_flags[target_idx].unchanged = true;
--	for (i = 0; i < target->public.stream_count; i++) {
--		struct core_stream *stream =
--			DC_STREAM_TO_CORE(target->public.streams[i]);
--		for (j = 0; j < MAX_PIPES; j++) {
--			if (context->res_ctx.pipe_ctx[j].stream == stream)
--				context->res_ctx.pipe_ctx[j].flags.unchanged =
--									true;
--		}
--	}
--}
--
- enum dc_status dce100_validate_with_context(
- 		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
-@@ -804,7 +786,7 @@ enum dc_status dce100_validate_with_context(
- 			if (dc->current_context.targets[j]
- 						== context->targets[i]) {
- 				unchanged = true;
--				set_target_unchanged(context, i);
-+				context->target_flags[i].unchanged = true;
- 				resource_attach_surfaces_to_context(
- 					(struct dc_surface **)dc->current_context.
- 						target_status[j].surfaces,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index b7c6a51..62363ef 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -673,33 +673,17 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 		struct validate_context *context,
- 		struct core_dc *dc)
- {
--	int i;
- 	struct core_stream *stream = pipe_ctx->stream;
--	bool timing_changed = context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]
--							.flags.timing_changed;
- 	enum dc_color_space color_space;
-+	struct pipe_ctx *pipe_ctx_old = &dc->current_context.res_ctx.
-+			pipe_ctx[pipe_ctx->pipe_idx];
- 
--	struct pipe_ctx *pipe_ctx_old = NULL;
--
--	for (i = 0; i < MAX_PIPES; i++) {
--		if (dc->current_context.res_ctx.pipe_ctx[i].stream == pipe_ctx->stream)
--			pipe_ctx_old = &dc->current_context.res_ctx.pipe_ctx[i];
--	}
--
--	if (timing_changed) {
-+	if (!pipe_ctx_old->stream) {
- 		/* Must blank CRTC after disabling power gating and before any
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
- 		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
- 
--		if (pipe_ctx_old) {
--			core_link_disable_stream(pipe_ctx);
--			resource_unreference_clock_source(
--						&dc->current_context.res_ctx,
--						pipe_ctx_old->clock_source);
--		}
--
--		/*TODO: AUTO check if timing changed*/
- 		if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
- 				pipe_ctx->clock_source,
- 				&pipe_ctx->pix_clk_params,
-@@ -722,7 +706,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 					stream->public.timing.pix_clk_khz,
- 					context->target_count);
- 
--	if (timing_changed) {
-+	if (!pipe_ctx_old->stream) {
- 		if (false == pipe_ctx->tg->funcs->enable_crtc(
- 				pipe_ctx->tg)) {
- 			BREAK_TO_DEBUGGER();
-@@ -783,12 +767,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 			pipe_ctx->tg,
- 			color_space);
- 
--	if (timing_changed)
-+	if (!pipe_ctx_old->stream) {
- 		core_link_enable_stream(pipe_ctx);
- 
--	if (dc_is_dp_signal(pipe_ctx->signal))
--		unblank_stream(pipe_ctx,
--			&stream->sink->link->public.cur_link_settings);
-+		if (dc_is_dp_signal(pipe_ctx->signal))
-+			unblank_stream(pipe_ctx,
-+				&stream->sink->link->public.cur_link_settings);
-+	}
- 
- 	return DC_OK;
- }
-@@ -1171,6 +1156,49 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
- 	}
- }
- 
-+static bool check_timing_change(struct core_stream *cur_stream,
-+		struct core_stream *new_stream)
-+{
-+	if (cur_stream == NULL)
-+		return true;
-+
-+	/* If sink pointer changed, it means this is a hotplug, we should do
-+	 * full hw setting.
-+	 */
-+	if (cur_stream->sink != new_stream->sink)
-+		return true;
-+
-+	return !resource_is_same_timing(
-+					&cur_stream->public.timing,
-+					&new_stream->public.timing);
-+}
-+
-+static bool pipe_need_reprogram(
-+		struct pipe_ctx *pipe_ctx_old,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
-+		return true;
-+
-+	if (pipe_ctx_old->signal != pipe_ctx->signal)
-+		return true;
-+
-+	if (pipe_ctx_old->audio != pipe_ctx->audio)
-+		return true;
-+
-+	if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
-+		return true;
-+
-+	if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
-+		return true;
-+
-+	if (check_timing_change(pipe_ctx_old->stream, pipe_ctx->stream))
-+		return true;
-+
-+
-+	return false;
-+}
-+
- /*TODO: const validate_context*/
- static enum dc_status apply_ctx_to_hw(
- 		struct core_dc *dc,
-@@ -1190,7 +1218,12 @@ static enum dc_status apply_ctx_to_hw(
- 		 * since bios does optimization and doesn't apply if changing
- 		 * PHY when not already disabled.
- 		 */
--		if (pipe_ctx_old->stream && !pipe_ctx->stream)
-+
-+		if (!pipe_ctx_old->stream)
-+			continue;
-+
-+		if (!pipe_ctx->stream ||
-+			pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
- 			reset_single_pipe_hw_ctx(
- 				dc, pipe_ctx_old, &dc->current_context);
- 	}
-@@ -1203,10 +1236,15 @@ static enum dc_status apply_ctx_to_hw(
- 	update_bios_scratch_critical_state(dc, true);
- 
- 	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+					&dc->current_context.res_ctx.pipe_ctx[i];
- 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- 		struct dc_bios *dcb;
- 
--		if (pipe_ctx->stream == NULL || pipe_ctx->flags.unchanged)
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->stream == pipe_ctx_old->stream)
- 			continue;
- 
- 		dcb = dal_adapter_service_get_bios_parser(
-@@ -1226,9 +1264,14 @@ static enum dc_status apply_ctx_to_hw(
- 		set_display_clock(context);
- 
- 	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+					&dc->current_context.res_ctx.pipe_ctx[i];
- 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- 
--		if (pipe_ctx->stream == NULL || pipe_ctx->flags.unchanged)
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->stream == pipe_ctx_old->stream)
- 			continue;
- 
- 		status = apply_single_controller_ctx_to_hw(
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index ccf6bd8..cf3a6ed 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -886,24 +886,6 @@ enum dc_status dce110_validate_bandwidth(
- 	return result;
- }
- 
--static void set_target_unchanged(
--		struct validate_context *context,
--		uint8_t target_idx)
--{
--	uint8_t i, j;
--	struct core_target *target = context->targets[target_idx];
--	context->target_flags[target_idx].unchanged = true;
--	for (i = 0; i < target->public.stream_count; i++) {
--		struct core_stream *stream =
--			DC_STREAM_TO_CORE(target->public.streams[i]);
--		for (j = 0; j < MAX_PIPES; j++) {
--			if (context->res_ctx.pipe_ctx[j].stream == stream)
--				context->res_ctx.pipe_ctx[j].flags.unchanged =
--									true;
--		}
--	}
--}
--
- enum dc_status dce110_validate_with_context(
- 		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
-@@ -915,8 +897,6 @@ enum dc_status dce110_validate_with_context(
- 	struct dc_context *dc_ctx = dc->ctx;
- 
- 	for (i = 0; i < set_count; i++) {
--		bool unchanged = false;
--
- 		context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
- 		dc_target_retain(&context->targets[i]->public);
- 		context->target_count++;
-@@ -924,8 +904,7 @@ enum dc_status dce110_validate_with_context(
- 		for (j = 0; j < dc->current_context.target_count; j++)
- 			if (dc->current_context.targets[j]
- 						== context->targets[i]) {
--				unchanged = true;
--				set_target_unchanged(context, i);
-+				context->target_flags[i].unchanged = true;
- 				resource_attach_surfaces_to_context(
- 					(struct dc_surface **)dc->current_context.
- 						target_status[j].surfaces,
-@@ -935,7 +914,7 @@ enum dc_status dce110_validate_with_context(
- 				context->target_status[i] =
- 					dc->current_context.target_status[j];
- 			}
--		if (!unchanged || set[i].surface_count != 0)
-+		if (set[i].surface_count != 0)
- 			if (!resource_attach_surfaces_to_context(
- 					(struct dc_surface **)set[i].surfaces,
- 					set[i].surface_count,
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-index 5cf61bd..4759a41 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-@@ -968,18 +968,7 @@ static void set_target_unchanged(
- 		struct validate_context *context,
- 		uint8_t target_idx)
- {
--	uint8_t i, j;
--	struct core_target *target = context->targets[target_idx];
- 	context->target_flags[target_idx].unchanged = true;
--	for (i = 0; i < target->public.stream_count; i++) {
--		struct core_stream *stream =
--			DC_STREAM_TO_CORE(target->public.streams[i]);
--		for (j = 0; j < MAX_PIPES; j++) {
--			if (context->res_ctx.pipe_ctx[j].stream == stream)
--				context->res_ctx.pipe_ctx[j].flags.unchanged =
--									true;
--		}
--	}
- }
- 
- static enum dc_status map_clock_resources(
-@@ -1022,9 +1011,6 @@ static enum dc_status map_clock_resources(
- 						&context->res_ctx,
- 						pipe_ctx->clock_source);
- 
--				if (pipe_ctx->clock_source
--					!= dc->current_context.res_ctx.pipe_ctx[k].clock_source)
--					pipe_ctx->flags.timing_changed = true;
- 				/* only one cs per stream regardless of mpo */
- 				break;
- 			}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index 56487fd..b2aa2cc 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -719,24 +719,6 @@ enum dc_status dce80_validate_bandwidth(
- 	return DC_OK;
- }
- 
--static void set_target_unchanged(
--		struct validate_context *context,
--		uint8_t target_idx)
--{
--	uint8_t i, j;
--	struct core_target *target = context->targets[target_idx];
--	context->target_flags[target_idx].unchanged = true;
--	for (i = 0; i < target->public.stream_count; i++) {
--		struct core_stream *stream =
--			DC_STREAM_TO_CORE(target->public.streams[i]);
--		for (j = 0; j < MAX_PIPES; j++) {
--			if (context->res_ctx.pipe_ctx[j].stream == stream)
--				context->res_ctx.pipe_ctx[j].flags.unchanged =
--									true;
--		}
--	}
--}
--
- enum dc_status dce80_validate_with_context(
- 		const struct core_dc *dc,
- 		const struct dc_validation_set set[],
-@@ -758,7 +740,7 @@ enum dc_status dce80_validate_with_context(
- 			if (dc->current_context.targets[j]
- 						== context->targets[i]) {
- 				unchanged = true;
--				set_target_unchanged(context, i);
-+				context->target_flags[i].unchanged = true;
- 				resource_attach_surfaces_to_context(
- 					(struct dc_surface **)dc->current_context.
- 						target_status[j].surfaces,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1053-drm-amd-dal-Change-reset-pipe_ctx-check-conditon.patch b/common/recipes-kernel/linux/files/1053-drm-amd-dal-Change-reset-pipe_ctx-check-conditon.patch
deleted file mode 100644
index 50a0f8fb..00000000
--- a/common/recipes-kernel/linux/files/1053-drm-amd-dal-Change-reset-pipe_ctx-check-conditon.patch
+++ /dev/null
@@ -1,153 +0,0 @@
-From 2f548663a8e1b073634cafd3bdad7f9c57b1a6f4 Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Thu, 7 Apr 2016 10:47:08 -0400
-Subject: [PATCH 1053/1110] drm/amd/dal: Change reset pipe_ctx check conditon
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 43 ++++++++++++++++++++++
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 43 ----------------------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  5 ---
- drivers/gpu/drm/amd/dal/dc/inc/resource.h          |  4 ++
- 4 files changed, 47 insertions(+), 48 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 12e4515..3f62986 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -1269,3 +1269,46 @@ enum dc_status resource_map_clock_resources(
- 
- 	return DC_OK;
- }
-+
-+static bool check_timing_change(struct core_stream *cur_stream,
-+		struct core_stream *new_stream)
-+{
-+	if (cur_stream == NULL)
-+		return true;
-+
-+	/* If sink pointer changed, it means this is a hotplug, we should do
-+	 * full hw setting.
-+	 */
-+	if (cur_stream->sink != new_stream->sink)
-+		return true;
-+
-+	return !resource_is_same_timing(
-+					&cur_stream->public.timing,
-+					&new_stream->public.timing);
-+}
-+
-+bool pipe_need_reprogram(
-+		struct pipe_ctx *pipe_ctx_old,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
-+		return true;
-+
-+	if (pipe_ctx_old->signal != pipe_ctx->signal)
-+		return true;
-+
-+	if (pipe_ctx_old->audio != pipe_ctx->audio)
-+		return true;
-+
-+	if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
-+		return true;
-+
-+	if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
-+		return true;
-+
-+	if (check_timing_change(pipe_ctx_old->stream, pipe_ctx->stream))
-+		return true;
-+
-+
-+	return false;
-+}
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index 62363ef..d1dd0d5 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -1156,49 +1156,6 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
- 	}
- }
- 
--static bool check_timing_change(struct core_stream *cur_stream,
--		struct core_stream *new_stream)
--{
--	if (cur_stream == NULL)
--		return true;
--
--	/* If sink pointer changed, it means this is a hotplug, we should do
--	 * full hw setting.
--	 */
--	if (cur_stream->sink != new_stream->sink)
--		return true;
--
--	return !resource_is_same_timing(
--					&cur_stream->public.timing,
--					&new_stream->public.timing);
--}
--
--static bool pipe_need_reprogram(
--		struct pipe_ctx *pipe_ctx_old,
--		struct pipe_ctx *pipe_ctx)
--{
--	if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
--		return true;
--
--	if (pipe_ctx_old->signal != pipe_ctx->signal)
--		return true;
--
--	if (pipe_ctx_old->audio != pipe_ctx->audio)
--		return true;
--
--	if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
--		return true;
--
--	if (pipe_ctx_old->stream_enc != pipe_ctx->stream_enc)
--		return true;
--
--	if (check_timing_change(pipe_ctx_old->stream, pipe_ctx->stream))
--		return true;
--
--
--	return false;
--}
--
- /*TODO: const validate_context*/
- static enum dc_status apply_ctx_to_hw(
- 		struct core_dc *dc,
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 5994ad1..94e0adf 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -290,11 +290,6 @@ struct pipe_ctx {
- 	struct encoder_info_frame encoder_info_frame;
- 
- 	uint8_t pipe_idx;
--
--	struct flags {
--		bool unchanged;
--		bool timing_changed;
--	} flags;
- };
- 
- struct resource_context {
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-index 00843a4..e66f73e 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
-@@ -92,5 +92,9 @@ enum dc_status resource_map_clock_resources(
- 		const struct core_dc *dc,
- 		struct validate_context *context);
- 
-+bool pipe_need_reprogram(
-+		struct pipe_ctx *pipe_ctx_old,
-+		struct pipe_ctx *pipe_ctx);
-+
- 
- #endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1054-drm-amd-dal-increase-link-training-retry-delay-to-fi.patch b/common/recipes-kernel/linux/files/1054-drm-amd-dal-increase-link-training-retry-delay-to-fi.patch
deleted file mode 100644
index cc452b26..00000000
--- a/common/recipes-kernel/linux/files/1054-drm-amd-dal-increase-link-training-retry-delay-to-fi.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 5e3610e566597064f6fa5856b5a5a400ccf8a565 Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Tue, 5 Apr 2016 14:29:56 -0400
-Subject: [PATCH 1054/1110] drm/amd/dal: increase link training retry delay to
- fix LT failures
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c    |  2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 14 +++++++-------
- drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h  |  5 ++++-
- 3 files changed, 12 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 4e57ed9..6d715c2 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -1206,7 +1206,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
- 			link,
- 			&link_settings,
- 			skip_video_pattern,
--			3)) {
-+			LINK_TRAINING_ATTEMPTS)) {
- 		link->public.cur_link_settings = link_settings;
- 		status = DC_OK;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-index c83a754..15e8f61 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
-@@ -1043,12 +1043,12 @@ bool perform_link_training_with_retries(
- 	struct core_link *link,
- 	const struct dc_link_settings *link_setting,
- 	bool skip_video_pattern,
--	unsigned int retires)
-+	int attempts)
- {
- 	uint8_t j;
--	uint8_t delay_between_retries = 10;
-+	uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
- 
--	for (j = 0; j < retires; ++j) {
-+	for (j = 0; j < attempts; ++j) {
- 
- 		if (perform_link_training(
- 				link,
-@@ -1056,8 +1056,8 @@ bool perform_link_training_with_retries(
- 				skip_video_pattern))
- 			return true;
- 
--		msleep(delay_between_retries);
--		delay_between_retries += 10;
-+		msleep(delay_between_attempts);
-+		delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
- 	}
- 
- 	return false;
-@@ -1177,7 +1177,7 @@ bool dp_hbr_verify_link_cap(
- 								link,
- 								cur,
- 								skip_video_pattern,
--								3);
-+								LINK_TRAINING_ATTEMPTS);
- 		}
- 
- 		if (success)
-@@ -1545,7 +1545,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
- 							"Status: ");
- 
- 		perform_link_training_with_retries(link,
--			&link->public.cur_link_settings, true, 3);
-+			&link->public.cur_link_settings, true, LINK_TRAINING_ATTEMPTS);
- 
- 		status = false;
- 	}
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-index b9fb8b9..b0cf8e0 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h
-@@ -26,6 +26,9 @@
- #ifndef __DC_LINK_DP_H__
- #define __DC_LINK_DP_H__
- 
-+#define LINK_TRAINING_ATTEMPTS 4
-+#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
-+
- struct core_link;
- struct core_stream;
- struct dc_link_settings;
-@@ -46,7 +49,7 @@ bool perform_link_training_with_retries(
- 	struct core_link *link,
- 	const struct dc_link_settings *link_setting,
- 	bool skip_video_pattern,
--	unsigned int  retires);
-+	int attempts);
- 
- bool is_mst_supported(struct core_link *link);
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1055-drm-amd-dal-Move-gamma-program-DPP-after-DCHUB-follo.patch b/common/recipes-kernel/linux/files/1055-drm-amd-dal-Move-gamma-program-DPP-after-DCHUB-follo.patch
deleted file mode 100644
index 9592984c..00000000
--- a/common/recipes-kernel/linux/files/1055-drm-amd-dal-Move-gamma-program-DPP-after-DCHUB-follo.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From adcfaf6fd00ac35002ff955f6929d3b5129542f7 Mon Sep 17 00:00:00 2001
-From: Hersen Wu <hersenxs.wu@amd.com>
-Date: Wed, 6 Apr 2016 14:24:16 -0400
-Subject: [PATCH 1055/1110] drm/amd/dal: Move gamma program DPP after DCHUB
- following program guide
-
-Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/core/dc.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index a5f33d4..e26a099 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -934,6 +934,9 @@ bool dc_commit_surfaces_to_target(
- 						dc_surface->dst_rect.width,
- 						dc_surface->dst_rect.height);
- 
-+			core_dc->hwss.set_plane_config(
-+				core_dc, pipe_ctx, &context->res_ctx);
-+
- 			if (surface->public.gamma_correction)
- 				gamma = DC_GAMMA_TO_CORE(
- 					surface->public.gamma_correction);
-@@ -942,9 +945,6 @@ bool dc_commit_surfaces_to_target(
- 					pipe_ctx->ipp,
- 					pipe_ctx->opp,
- 					gamma, surface);
--
--			core_dc->hwss.set_plane_config(
--				core_dc, pipe_ctx, &context->res_ctx);
- 		}
- 
- 	core_dc->hwss.update_plane_addrs(core_dc, &context->res_ctx);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1056-drm-amd-dal-On-resume-rewrite-the-MSTM-control-bits-.patch b/common/recipes-kernel/linux/files/1056-drm-amd-dal-On-resume-rewrite-the-MSTM-control-bits-.patch
deleted file mode 100644
index 46d114a1..00000000
--- a/common/recipes-kernel/linux/files/1056-drm-amd-dal-On-resume-rewrite-the-MSTM-control-bits-.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 525a61bf411ffb31d73165b2bb81e7775294e287 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 8 Apr 2016 11:36:15 -0400
-Subject: [PATCH 1056/1110] drm/amd/dal: On resume rewrite the MSTM control
- bits to enamble MST
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 28 +++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index a989fc2..71b2808 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -410,6 +410,28 @@ static void detect_link_for_all_connectors(struct drm_device *dev)
- 	drm_modeset_unlock(&dev->mode_config.connection_mutex);
- }
- 
-+static void s3_handle_mst(struct drm_device *dev, bool suspend)
-+{
-+	struct amdgpu_connector *aconnector;
-+	struct drm_connector *connector;
-+
-+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		   aconnector = to_amdgpu_connector(connector);
-+		   if (aconnector->dc_link->type == dc_connection_mst_branch &&
-+				   !aconnector->mst_port) {
-+
-+			   if (suspend)
-+				   drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
-+			   else
-+				   drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
-+		   }
-+	}
-+
-+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
-+}
-+
- static int dm_hw_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -440,6 +462,8 @@ static int dm_suspend(void *handle)
- 	struct amdgpu_display_manager *dm = &adev->dm;
- 	int ret = 0;
- 
-+	s3_handle_mst(adev->ddev, true);
-+
- 	dc_set_power_state(
- 		dm->dc,
- 		DC_ACPI_CM_POWER_STATE_D3,
-@@ -527,6 +551,7 @@ static int dm_display_resume(struct drm_device *ddev)
- 		crtc_state->mode_changed = true;
- 	}
- 
-+
- 	/* Attach planes to drm_atomic_state */
- 	list_for_each_entry(plane, &ddev->mode_config.plane_list, head) {
- 
-@@ -615,6 +640,9 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	/* program HPD filter */
- 	dc_resume(dm->dc);
- 
-+	/* On resume we need to  rewrite the MSTM control bits to enamble MST*/
-+	s3_handle_mst(ddev, false);
-+
- 	/*
- 	 * early enable HPD Rx IRQ, should be done before set mode as short
- 	 * pulse interrupts are used for MST
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1057-drm-amd-dal-Fix-wrong-audio-clock-after-resume.patch b/common/recipes-kernel/linux/files/1057-drm-amd-dal-Fix-wrong-audio-clock-after-resume.patch
deleted file mode 100644
index df4f3f1f..00000000
--- a/common/recipes-kernel/linux/files/1057-drm-amd-dal-Fix-wrong-audio-clock-after-resume.patch
+++ /dev/null
@@ -1,638 +0,0 @@
-From 0f34627fec7c6c6f955ed9719e9f2edf30ad87e5 Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 20 Apr 2016 12:08:03 -0400
-Subject: [PATCH 1057/1110] drm/amd/dal: Fix wrong audio clock after resume
-
-Don't call build_audio_output during validation since it
-reads clock registers to determine the audio dto values.
-
-Move build_audio_output to end of set_mode to make sure pixel
-clock has been programmed.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  93 ---------------
- .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 130 ++++++++++++++++++---
- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  88 --------------
- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    |  89 --------------
- drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  89 --------------
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   1 -
- 6 files changed, 113 insertions(+), 377 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index 4820af7..e2b71ba 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -573,97 +573,6 @@ void dce100_destruct_resource_pool(struct resource_pool *pool)
- 		dal_adapter_service_destroy(&pool->adapter_srv);
- }
- 
--static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
--{
--	switch (crtc_id) {
--	case CONTROLLER_ID_D0:
--		return DTO_SOURCE_ID0;
--	case CONTROLLER_ID_D1:
--		return DTO_SOURCE_ID1;
--	case CONTROLLER_ID_D2:
--		return DTO_SOURCE_ID2;
--	case CONTROLLER_ID_D3:
--		return DTO_SOURCE_ID3;
--	case CONTROLLER_ID_D4:
--		return DTO_SOURCE_ID4;
--	case CONTROLLER_ID_D5:
--		return DTO_SOURCE_ID5;
--	default:
--		return DTO_SOURCE_UNKNOWN;
--	}
--}
--
--static void build_audio_output(
--	const struct pipe_ctx *pipe_ctx,
--	struct audio_output *audio_output)
--{
--	const struct core_stream *stream = pipe_ctx->stream;
--	audio_output->engine_id = pipe_ctx->stream_enc->id;
--
--	audio_output->signal = pipe_ctx->signal;
--
--	/* audio_crtc_info  */
--
--	audio_output->crtc_info.h_total =
--		stream->public.timing.h_total;
--
--	/*
--	 * Audio packets are sent during actual CRTC blank physical signal, we
--	 * need to specify actual active signal portion
--	 */
--	audio_output->crtc_info.h_active =
--			stream->public.timing.h_addressable
--			+ stream->public.timing.h_border_left
--			+ stream->public.timing.h_border_right;
--
--	audio_output->crtc_info.v_active =
--			stream->public.timing.v_addressable
--			+ stream->public.timing.v_border_top
--			+ stream->public.timing.v_border_bottom;
--
--	audio_output->crtc_info.pixel_repetition = 1;
--
--	audio_output->crtc_info.interlaced =
--			stream->public.timing.flags.INTERLACE;
--
--	audio_output->crtc_info.refresh_rate =
--		(stream->public.timing.pix_clk_khz*1000)/
--		(stream->public.timing.h_total*stream->public.timing.v_total);
--
--	audio_output->crtc_info.color_depth =
--		stream->public.timing.display_color_depth;
--
--	audio_output->crtc_info.requested_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	/*
--	 * TODO - Investigate why calculated pixel clk has to be
--	 * requested pixel clk
--	 */
--	audio_output->crtc_info.calculated_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
--			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
--		audio_output->pll_info.dp_dto_source_clock_in_khz =
--			dal_display_clock_get_dp_ref_clk_frequency(
--				pipe_ctx->dis_clk);
--	}
--
--	audio_output->pll_info.feed_back_divider =
--			pipe_ctx->pll_settings.feedback_divider;
--
--	audio_output->pll_info.dto_source =
--		translate_to_dto_source(
--			pipe_ctx->pipe_idx + 1);
--
--	/* TODO hard code to enable for now. Need get from stream */
--	audio_output->pll_info.ss_enabled = true;
--
--	audio_output->pll_info.ss_percentage =
--			pipe_ctx->pll_settings.ss_percentage;
--}
--
- static void get_pixel_clock_parameters(
- 	const struct pipe_ctx *pipe_ctx,
- 	struct pixel_clk_params *pixel_clk_params)
-@@ -690,8 +599,6 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- 		&pipe_ctx->pix_clk_params,
- 		&pipe_ctx->pll_settings);
- 
--	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
--
- 	return DC_OK;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-index d1dd0d5..265617d 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
-@@ -668,6 +668,97 @@ static enum dc_color_space get_output_color_space(
- 	return color_space;
- }
- 
-+static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-+{
-+	switch (crtc_id) {
-+	case CONTROLLER_ID_D0:
-+		return DTO_SOURCE_ID0;
-+	case CONTROLLER_ID_D1:
-+		return DTO_SOURCE_ID1;
-+	case CONTROLLER_ID_D2:
-+		return DTO_SOURCE_ID2;
-+	case CONTROLLER_ID_D3:
-+		return DTO_SOURCE_ID3;
-+	case CONTROLLER_ID_D4:
-+		return DTO_SOURCE_ID4;
-+	case CONTROLLER_ID_D5:
-+		return DTO_SOURCE_ID5;
-+	default:
-+		return DTO_SOURCE_UNKNOWN;
-+	}
-+}
-+
-+static void build_audio_output(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct audio_output *audio_output)
-+{
-+	const struct core_stream *stream = pipe_ctx->stream;
-+	audio_output->engine_id = pipe_ctx->stream_enc->id;
-+
-+	audio_output->signal = pipe_ctx->signal;
-+
-+	/* audio_crtc_info  */
-+
-+	audio_output->crtc_info.h_total =
-+		stream->public.timing.h_total;
-+
-+	/*
-+	 * Audio packets are sent during actual CRTC blank physical signal, we
-+	 * need to specify actual active signal portion
-+	 */
-+	audio_output->crtc_info.h_active =
-+			stream->public.timing.h_addressable
-+			+ stream->public.timing.h_border_left
-+			+ stream->public.timing.h_border_right;
-+
-+	audio_output->crtc_info.v_active =
-+			stream->public.timing.v_addressable
-+			+ stream->public.timing.v_border_top
-+			+ stream->public.timing.v_border_bottom;
-+
-+	audio_output->crtc_info.pixel_repetition = 1;
-+
-+	audio_output->crtc_info.interlaced =
-+			stream->public.timing.flags.INTERLACE;
-+
-+	audio_output->crtc_info.refresh_rate =
-+		(stream->public.timing.pix_clk_khz*1000)/
-+		(stream->public.timing.h_total*stream->public.timing.v_total);
-+
-+	audio_output->crtc_info.color_depth =
-+		stream->public.timing.display_color_depth;
-+
-+	audio_output->crtc_info.requested_pixel_clock =
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
-+
-+	/*
-+	 * TODO - Investigate why calculated pixel clk has to be
-+	 * requested pixel clk
-+	 */
-+	audio_output->crtc_info.calculated_pixel_clock =
-+			pipe_ctx->pix_clk_params.requested_pix_clk;
-+
-+	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		audio_output->pll_info.dp_dto_source_clock_in_khz =
-+			dal_display_clock_get_dp_ref_clk_frequency(
-+				pipe_ctx->dis_clk);
-+	}
-+
-+	audio_output->pll_info.feed_back_divider =
-+			pipe_ctx->pll_settings.feedback_divider;
-+
-+	audio_output->pll_info.dto_source =
-+		translate_to_dto_source(
-+			pipe_ctx->pipe_idx + 1);
-+
-+	/* TODO hard code to enable for now. Need get from stream */
-+	audio_output->pll_info.ss_enabled = true;
-+
-+	audio_output->pll_info.ss_percentage =
-+			pipe_ctx->pll_settings.ss_percentage;
-+}
-+
- static enum dc_status apply_single_controller_ctx_to_hw(
- 		struct pipe_ctx *pipe_ctx,
- 		struct validate_context *context,
-@@ -679,7 +770,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 			pipe_ctx[pipe_ctx->pipe_idx];
- 
- 	if (!pipe_ctx_old->stream) {
--		/* Must blank CRTC after disabling power gating and before any
-+		/*
-+		 * Must blank CRTC after disabling power gating and before any
- 		 * programming, otherwise CRTC will be hung in bad state
- 		 */
- 		pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
-@@ -751,16 +843,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- 			(pipe_ctx->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
- 			true : false);
- 
--	if (pipe_ctx->audio != NULL) {
--		if (AUDIO_RESULT_OK != dal_audio_setup(
--				pipe_ctx->audio,
--				&pipe_ctx->audio_output,
--				&stream->public.audio_info)) {
--			BREAK_TO_DEBUGGER();
--			return DC_ERROR_UNEXPECTED;
--		}
--	}
--
- 	/* program blank color */
- 	color_space = get_output_color_space(&stream->public.timing);
- 	pipe_ctx->tg->funcs->set_blank_color(
-@@ -1163,6 +1245,7 @@ static enum dc_status apply_ctx_to_hw(
- {
- 	enum dc_status status;
- 	uint8_t i;
-+	bool programmed_audio_dto = false;
- 
- 	/* Reset old context */
- 	/* look up the targets that have been removed since last commit */
-@@ -1257,12 +1340,25 @@ static enum dc_status apply_ctx_to_hw(
- 	 */
- 	for (i = 0; i < MAX_PIPES; i++) {
- 		if (context->res_ctx.pipe_ctx[i].audio != NULL) {
--			dal_audio_setup_audio_wall_dto(
--					context->res_ctx.pipe_ctx[i].audio,
--					context->res_ctx.pipe_ctx[i].signal,
--					&context->res_ctx.pipe_ctx[i].audio_output.crtc_info,
--					&context->res_ctx.pipe_ctx[i].audio_output.pll_info);
--			break;
-+			struct audio_output audio_output;
-+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+			build_audio_output(pipe_ctx, &audio_output);
-+			if (AUDIO_RESULT_OK != dal_audio_setup(
-+					pipe_ctx->audio,
-+					&audio_output,
-+					&pipe_ctx->stream->public.audio_info)) {
-+				BREAK_TO_DEBUGGER();
-+				return DC_ERROR_UNEXPECTED;
-+			}
-+			if (!programmed_audio_dto) {
-+				dal_audio_setup_audio_wall_dto(
-+					pipe_ctx->audio,
-+					pipe_ctx->signal,
-+					&audio_output.crtc_info,
-+					&audio_output.pll_info);
-+				programmed_audio_dto = true;
-+			}
- 		}
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-index cf3a6ed..903d020 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
-@@ -523,92 +523,6 @@ void dce110_destruct_resource_pool(struct resource_pool *pool)
- 	}
- }
- 
--static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
--{
--	switch (crtc_id) {
--	case CONTROLLER_ID_D0:
--		return DTO_SOURCE_ID0;
--	case CONTROLLER_ID_D1:
--		return DTO_SOURCE_ID1;
--	case CONTROLLER_ID_D2:
--		return DTO_SOURCE_ID2;
--	case CONTROLLER_ID_D3:
--		return DTO_SOURCE_ID3;
--	case CONTROLLER_ID_D4:
--		return DTO_SOURCE_ID4;
--	case CONTROLLER_ID_D5:
--		return DTO_SOURCE_ID5;
--	default:
--		return DTO_SOURCE_UNKNOWN;
--	}
--}
--
--static void build_audio_output(
--	const struct pipe_ctx *pipe_ctx,
--	struct audio_output *audio_output)
--{
--	const struct core_stream *stream = pipe_ctx->stream;
--	audio_output->engine_id = pipe_ctx->stream_enc->id;
--
--	audio_output->signal = pipe_ctx->signal;
--
--	/* audio_crtc_info  */
--
--	audio_output->crtc_info.h_total =
--		stream->public.timing.h_total;
--
--	/* Audio packets are sent during actual CRTC blank physical signal, we
--	 * need to specify actual active signal portion */
--	audio_output->crtc_info.h_active =
--			stream->public.timing.h_addressable
--			+ stream->public.timing.h_border_left
--			+ stream->public.timing.h_border_right;
--
--	audio_output->crtc_info.v_active =
--			stream->public.timing.v_addressable
--			+ stream->public.timing.v_border_top
--			+ stream->public.timing.v_border_bottom;
--
--	audio_output->crtc_info.pixel_repetition = 1;
--
--	audio_output->crtc_info.interlaced =
--			stream->public.timing.flags.INTERLACE;
--
--	audio_output->crtc_info.refresh_rate =
--		(stream->public.timing.pix_clk_khz*1000)/
--		(stream->public.timing.h_total*stream->public.timing.v_total);
--
--	audio_output->crtc_info.color_depth =
--		stream->public.timing.display_color_depth;
--
--	audio_output->crtc_info.requested_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	/* TODO - Investigate why calculated pixel clk has to be
--	 * requested pixel clk */
--	audio_output->crtc_info.calculated_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
--			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
--		audio_output->pll_info.dp_dto_source_clock_in_khz =
--			dal_display_clock_get_dp_ref_clk_frequency(
--				pipe_ctx->dis_clk);
--	}
--
--	audio_output->pll_info.feed_back_divider =
--			pipe_ctx->pll_settings.feedback_divider;
--
--	audio_output->pll_info.dto_source =
--		translate_to_dto_source(
--			pipe_ctx->pipe_idx + 1);
--
--	/* TODO hard code to enable for now. Need get from stream */
--	audio_output->pll_info.ss_enabled = true;
--
--	audio_output->pll_info.ss_percentage =
--			pipe_ctx->pll_settings.ss_percentage;
--}
- 
- static void get_pixel_clock_parameters(
- 	const struct pipe_ctx *pipe_ctx,
-@@ -636,8 +550,6 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- 		&pipe_ctx->pix_clk_params,
- 		&pipe_ctx->pll_settings);
- 
--	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
--
- 	return DC_OK;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-index 4759a41..dd185af 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
-@@ -616,93 +616,6 @@ static struct clock_source *find_matching_pll(struct resource_context *res_ctx,
- 	return 0;
- }
- 
--static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
--{
--	switch (crtc_id) {
--	case CONTROLLER_ID_D0:
--		return DTO_SOURCE_ID0;
--	case CONTROLLER_ID_D1:
--		return DTO_SOURCE_ID1;
--	case CONTROLLER_ID_D2:
--		return DTO_SOURCE_ID2;
--	case CONTROLLER_ID_D3:
--		return DTO_SOURCE_ID3;
--	case CONTROLLER_ID_D4:
--		return DTO_SOURCE_ID4;
--	case CONTROLLER_ID_D5:
--		return DTO_SOURCE_ID5;
--	default:
--		return DTO_SOURCE_UNKNOWN;
--	}
--}
--
--static void build_audio_output(
--	const struct pipe_ctx *pipe_ctx,
--	struct audio_output *audio_output)
--{
--	const struct core_stream *stream = pipe_ctx->stream;
--	audio_output->engine_id = pipe_ctx->stream_enc->id;
--
--	audio_output->signal = pipe_ctx->signal;
--
--	/* audio_crtc_info  */
--
--	audio_output->crtc_info.h_total =
--		stream->public.timing.h_total;
--
--	/* Audio packets are sent during actual CRTC blank physical signal, we
--	 * need to specify actual active signal portion */
--	audio_output->crtc_info.h_active =
--			stream->public.timing.h_addressable
--			+ stream->public.timing.h_border_left
--			+ stream->public.timing.h_border_right;
--
--	audio_output->crtc_info.v_active =
--			stream->public.timing.v_addressable
--			+ stream->public.timing.v_border_top
--			+ stream->public.timing.v_border_bottom;
--
--	audio_output->crtc_info.pixel_repetition = 1;
--
--	audio_output->crtc_info.interlaced =
--			stream->public.timing.flags.INTERLACE;
--
--	audio_output->crtc_info.refresh_rate =
--		(stream->public.timing.pix_clk_khz*1000)/
--		(stream->public.timing.h_total*stream->public.timing.v_total);
--
--	audio_output->crtc_info.color_depth =
--		stream->public.timing.display_color_depth;
--
--	audio_output->crtc_info.requested_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	/* TODO - Investigate why calculated pixel clk has to be
--	 * requested pixel clk */
--	audio_output->crtc_info.calculated_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
--			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
--		audio_output->pll_info.dp_dto_source_clock_in_khz =
--			dal_display_clock_get_dp_ref_clk_frequency(
--				pipe_ctx->dis_clk);
--	}
--
--	audio_output->pll_info.feed_back_divider =
--			pipe_ctx->pll_settings.feedback_divider;
--
--	audio_output->pll_info.dto_source =
--		translate_to_dto_source(
--			pipe_ctx->pipe_idx + 1);
--
--	/* TODO hard code to enable for now. Need get from stream */
--	audio_output->pll_info.ss_enabled = true;
--
--	audio_output->pll_info.ss_percentage =
--			pipe_ctx->pll_settings.ss_percentage;
--}
--
- static void get_pixel_clock_parameters(
- 	const struct pipe_ctx *pipe_ctx,
- 	struct pixel_clk_params *pixel_clk_params)
-@@ -729,8 +642,6 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- 		&pipe_ctx->pix_clk_params,
- 		&pipe_ctx->pll_settings);
- 
--	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
--
- 	return DC_OK;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-index b2aa2cc..c52739c 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
-@@ -534,93 +534,6 @@ void dce80_destruct_resource_pool(struct resource_pool *pool)
- 	}
- }
- 
--static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
--{
--	switch (crtc_id) {
--	case CONTROLLER_ID_D0:
--		return DTO_SOURCE_ID0;
--	case CONTROLLER_ID_D1:
--		return DTO_SOURCE_ID1;
--	case CONTROLLER_ID_D2:
--		return DTO_SOURCE_ID2;
--	case CONTROLLER_ID_D3:
--		return DTO_SOURCE_ID3;
--	case CONTROLLER_ID_D4:
--		return DTO_SOURCE_ID4;
--	case CONTROLLER_ID_D5:
--		return DTO_SOURCE_ID5;
--	default:
--		return DTO_SOURCE_UNKNOWN;
--	}
--}
--
--static void build_audio_output(
--	const struct pipe_ctx *pipe_ctx,
--	struct audio_output *audio_output)
--{
--	const struct core_stream *stream = pipe_ctx->stream;
--	audio_output->engine_id = pipe_ctx->stream_enc->id;
--
--	audio_output->signal = pipe_ctx->signal;
--
--	/* audio_crtc_info  */
--
--	audio_output->crtc_info.h_total =
--		stream->public.timing.h_total;
--
--	/* Audio packets are sent during actual CRTC blank physical signal, we
--	 * need to specify actual active signal portion */
--	audio_output->crtc_info.h_active =
--			stream->public.timing.h_addressable
--			+ stream->public.timing.h_border_left
--			+ stream->public.timing.h_border_right;
--
--	audio_output->crtc_info.v_active =
--			stream->public.timing.v_addressable
--			+ stream->public.timing.v_border_top
--			+ stream->public.timing.v_border_bottom;
--
--	audio_output->crtc_info.pixel_repetition = 1;
--
--	audio_output->crtc_info.interlaced =
--			stream->public.timing.flags.INTERLACE;
--
--	audio_output->crtc_info.refresh_rate =
--		(stream->public.timing.pix_clk_khz*1000)/
--		(stream->public.timing.h_total*stream->public.timing.v_total);
--
--	audio_output->crtc_info.color_depth =
--		stream->public.timing.display_color_depth;
--
--	audio_output->crtc_info.requested_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	/* TODO - Investigate why calculated pixel clk has to be
--	 * requested pixel clk */
--	audio_output->crtc_info.calculated_pixel_clock =
--			pipe_ctx->pix_clk_params.requested_pix_clk;
--
--	if (pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT ||
--			pipe_ctx->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
--		audio_output->pll_info.dp_dto_source_clock_in_khz =
--			dal_display_clock_get_dp_ref_clk_frequency(
--				pipe_ctx->dis_clk);
--	}
--
--	audio_output->pll_info.feed_back_divider =
--			pipe_ctx->pll_settings.feedback_divider;
--
--	audio_output->pll_info.dto_source =
--		translate_to_dto_source(
--			pipe_ctx->pipe_idx + 1);
--
--	/* TODO hard code to enable for now. Need get from stream */
--	audio_output->pll_info.ss_enabled = true;
--
--	audio_output->pll_info.ss_percentage =
--			pipe_ctx->pll_settings.ss_percentage;
--}
--
- static void get_pixel_clock_parameters(
- 	const struct pipe_ctx *pipe_ctx,
- 	struct pixel_clk_params *pixel_clk_params)
-@@ -647,8 +560,6 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
- 		&pipe_ctx->pix_clk_params,
- 		&pipe_ctx->pll_settings);
- 
--	build_audio_output(pipe_ctx, &pipe_ctx->audio_output);
--
- 	return DC_OK;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index 94e0adf..ef6ce30 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -279,7 +279,6 @@ struct pipe_ctx {
- 	struct clock_source *clock_source;
- 
- 	struct audio *audio;
--	struct audio_output audio_output;
- 
- 	enum signal_type signal;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1058-drm-amd-dal-Run-full-validate-for-virtual-connector.patch b/common/recipes-kernel/linux/files/1058-drm-amd-dal-Run-full-validate-for-virtual-connector.patch
deleted file mode 100644
index 91dc7d12..00000000
--- a/common/recipes-kernel/linux/files/1058-drm-amd-dal-Run-full-validate-for-virtual-connector.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 056436ea2e7a39f1ef79efa5cf965d0e17a6a388 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 20 Apr 2016 16:47:10 -0400
-Subject: [PATCH 1058/1110] drm/amd/dal: Run full validate for virtual
- connector
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-index e2b71ba..74c7eea 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
-@@ -630,9 +630,6 @@ static enum dc_status validate_mapped_resource(
- 						pipe_ctx->tg, &stream->public.timing))
- 					return DC_FAIL_CONTROLLER_VALIDATE;
- 
--				if (pipe_ctx->signal == SIGNAL_TYPE_VIRTUAL)
--					return status;
--
- 				status = build_pipe_hw_param(pipe_ctx);
- 
- 				if (status != DC_OK)
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1059-drm-amd-dal-Use-dce110-audio-for-dce112.patch b/common/recipes-kernel/linux/files/1059-drm-amd-dal-Use-dce110-audio-for-dce112.patch
deleted file mode 100644
index 3b29a25f..00000000
--- a/common/recipes-kernel/linux/files/1059-drm-amd-dal-Use-dce110-audio-for-dce112.patch
+++ /dev/null
@@ -1,620 +0,0 @@
-From bd1f37712022f6ca489104cf356f760314f0b1bd Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 20 Apr 2016 16:42:09 -0400
-Subject: [PATCH 1059/1110] drm/amd/dal: Use dce110 audio for dce112
-
-The code and registers are the same for both. No need
-to duplicate code.
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/audio/Makefile          |   7 -
- drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |   6 +-
- .../gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c | 451 ---------------------
- .../gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h |  40 --
- .../amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h  |  47 ---
- 5 files changed, 1 insertion(+), 550 deletions(-)
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
- delete mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-index 9a9a64c..90bdaa6 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
-@@ -33,10 +33,3 @@ AMD_DAL_AUDIO_DCE11 = $(addprefix $(AMDDALPATH)/dc/audio/dce110/,$(AUDIO_DCE11))
- AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE11)
- endif
- 
--ifdef CONFIG_DRM_AMD_DAL_DCE11_2
--AUDIO_DCE112 = audio_dce112.o hw_ctx_audio_dce112.o
--
--AMD_DAL_AUDIO_DCE112 = $(addprefix $(AMDDALPATH)/dc/audio/dce112/,$(AUDIO_DCE112))
--
--AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE112)
--endif
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-index a8137e0..31c600c 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
-@@ -40,10 +40,6 @@
- #include "dce110/hw_ctx_audio_dce110.h"
- #endif
- 
--#if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
--#include "dce112/audio_dce112.h"
--#include "dce112/hw_ctx_audio_dce112.h"
--#endif
- 
- /***** static function : only used within audio.c *****/
- 
-@@ -288,7 +284,7 @@ struct audio *dal_audio_create(
- #endif
- #if defined(CONFIG_DRM_AMD_DAL_DCE11_2)
- 	case DCE_VERSION_11_2:
--		return dal_audio_create_dce112(init_data);
-+		return dal_audio_create_dce110(init_data);
- #endif
- 	default:
- 		BREAK_TO_DEBUGGER();
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c b/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
-deleted file mode 100644
-index 66c32b0..0000000
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.c
-+++ /dev/null
-@@ -1,451 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#include "dm_services.h"
--
--#include "include/logger_interface.h"
--
--#include "audio_dce112.h"
--
--/***** static functions  *****/
--
--static void destruct(struct audio_dce112 *audio)
--{
--	/*release memory allocated for hw_ctx -- allocated is initiated
--	 *by audio_dce112 power_up
--	 *audio->base->hw_ctx = NULL is done within hw-ctx->destroy
--	 */
--	if (audio->base.hw_ctx)
--		audio->base.hw_ctx->funcs->destroy(&(audio->base.hw_ctx));
--
--	/* reset base_audio_block */
--	dal_audio_destruct_base(&audio->base);
--}
--
--static void destroy(struct audio **ptr)
--{
--	struct audio_dce112 *audio = NULL;
--
--	audio = container_of(*ptr, struct audio_dce112, base);
--
--	destruct(audio);
--
--	/* release memory allocated for audio_dce112*/
--	dm_free(audio);
--	*ptr = NULL;
--}
--
--/* The inital call of hook function comes from audio object level.
-- *The passing object handle "struct audio *audio" point to base object
-- *already.There is not need to get base object from audio_dce112.
-- */
--
--/**
--* setup
--*
--* @brief
--*  setup Audio HW block, to be called by dal_audio_setup
--*
--*/
--static enum audio_result setup(
--	struct audio *audio,
--	struct audio_output *output,
--	struct audio_info *info)
--{
--	switch (output->signal) {
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--		/*setup HDMI audio engine*/
--		audio->hw_ctx->funcs->enable_afmt_clock(
--			audio->hw_ctx,
--			output->engine_id,
--			true);
--		audio->hw_ctx->funcs->setup_hdmi_audio(
--			audio->hw_ctx, output->engine_id, &output->crtc_info);
--
--		audio->hw_ctx->funcs->setup_azalia(
--			audio->hw_ctx,
--			output->engine_id,
--			output->signal,
--			&output->crtc_info,
--			&output->pll_info,
--			info);
--		break;
--
--	case SIGNAL_TYPE_WIRELESS:
--		/* setup Azalia block for Wireless Display - This
--			is different than for wired
--			displays because there is no
--			DIG to program.*/
--		/*TODO:
--		audio->hw_ctx->funcs->setup_azalia_for_vce(
--			audio->hw_ctx,
--			audio->signal,
--			audio->crtc_info,
--			info);
--		*/
--		break;
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		/* setup DP audio engine will be done at enable output */
--
--		/* setup Azalia block*/
--		audio->hw_ctx->funcs->setup_azalia(
--			audio->hw_ctx,
--			output->engine_id,
--			output->signal,
--			&output->crtc_info,
--			&output->pll_info,
--			info);
--
--		break;
--	default:
--		return AUDIO_RESULT_ERROR;
--	}
--
--	return AUDIO_RESULT_OK;
--}
--
--/**
--* enable_output
--*
--* @brief
--*  enable Audio HW block, to be called by dal_audio_enable_output
--*/
--static enum audio_result enable_output(
--	struct audio *audio,
--	enum engine_id engine_id,
--	enum signal_type signal)
--{
--	/* enable audio output */
--	switch (signal) {
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--		break;
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP: {
--			/* enable AFMT clock before enable audio*/
--			audio->hw_ctx->funcs->enable_afmt_clock(
--				audio->hw_ctx, engine_id, true);
--			/* setup DP audio engine */
--			audio->hw_ctx->funcs->setup_dp_audio(
--				audio->hw_ctx, engine_id);
--			/* enabl DP audio packets will be done at unblank */
--			audio->hw_ctx->funcs->enable_dp_audio(
--				audio->hw_ctx, engine_id);
--		}
--		break;
--	case SIGNAL_TYPE_WIRELESS:
--		/* route audio to VCE block */
--		audio->hw_ctx->funcs->setup_vce_audio(audio->hw_ctx);
--		break;
--	default:
--		return AUDIO_RESULT_ERROR;
--	}
--	return AUDIO_RESULT_OK;
--}
--
--/**
--* disable_output
--*
--* @brief
--*  disable Audio HW block, to be called by dal_audio_disable_output
--*
--*/
--static enum audio_result disable_output(
--	struct audio *audio,
--	enum engine_id engine_id,
--	enum signal_type signal)
--{
--	switch (signal) {
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--	case SIGNAL_TYPE_WIRELESS:
--		/* disable HDMI audio */
--		audio->hw_ctx->
--			funcs->disable_azalia_audio(
--					audio->hw_ctx, engine_id);
--		audio->hw_ctx->
--			funcs->enable_afmt_clock(
--					audio->hw_ctx, engine_id,
--					false);
--
--		break;
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP: {
--			/* disable DP audio */
--			audio->hw_ctx->funcs->disable_dp_audio(
--				audio->hw_ctx, engine_id);
--			audio->hw_ctx->funcs->disable_azalia_audio(
--				audio->hw_ctx, engine_id);
--			audio->hw_ctx->funcs->enable_afmt_clock(
--				audio->hw_ctx, engine_id, false);
--		}
--		break;
--	default:
--		return AUDIO_RESULT_ERROR;
--	}
--
--	return AUDIO_RESULT_OK;
--}
--
--/**
--* unmute
--*
--* @brief
--*  unmute audio, to be called by dal_audio_unmute
--*
--*/
--static enum audio_result unmute(
--	struct audio *audio,
--	enum engine_id engine_id,
--	enum signal_type signal)
--{
--	switch (signal) {
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		/* unmute Azalia audio */
--		audio->hw_ctx->funcs->unmute_azalia_audio(
--				audio->hw_ctx, engine_id);
--		break;
--	case SIGNAL_TYPE_WIRELESS:
--		/*Do nothing for wireless display*/
--		break;
--	default:
--		return AUDIO_RESULT_ERROR;
--	}
--	return AUDIO_RESULT_OK;
--}
--
--/**
--* mute
--*
--* @brief
--*  mute audio, to be called  by dal_audio_nmute
--*
--*/
--static enum audio_result mute(
--	struct audio *audio,
--	enum engine_id engine_id,
--	enum signal_type signal)
--{
--	switch (signal) {
--	case SIGNAL_TYPE_HDMI_TYPE_A:
--	case SIGNAL_TYPE_DISPLAY_PORT:
--	case SIGNAL_TYPE_DISPLAY_PORT_MST:
--	case SIGNAL_TYPE_EDP:
--		/* mute Azalia audio */
--		audio->hw_ctx->funcs->mute_azalia_audio(
--				audio->hw_ctx, engine_id);
--		break;
--	case SIGNAL_TYPE_WIRELESS:
--		/*Do nothing for wireless display*/
--		break;
--	default:
--		return AUDIO_RESULT_ERROR;
--	}
--	return AUDIO_RESULT_OK;
--}
--
--/**
--* initialize
--*
--* @brief
--*  Perform SW initialization - create audio hw context. Then do HW
--*  initialization. this function is called at dal_audio_power_up.
--*
--*/
--static enum audio_result initialize(
--	struct audio *audio)
--{
--	uint8_t audio_endpoint_enum_id = 0;
--
--	audio_endpoint_enum_id = audio->id.enum_id;
--
--	/* HW CTX already create*/
--	if (audio->hw_ctx != NULL)
--		return AUDIO_RESULT_OK;
--
--	audio->hw_ctx = dal_hw_ctx_audio_dce112_create(
--			audio->ctx,
--			audio_endpoint_enum_id);
--
--	if (audio->hw_ctx == NULL)
--		return AUDIO_RESULT_ERROR;
--
--	/* override HW default settings */
--	audio->hw_ctx->funcs->hw_initialize(audio->hw_ctx);
--
--	return AUDIO_RESULT_OK;
--}
--
--/* enable multi channel split */
--static void enable_channel_splitting_mapping(
--	struct audio *audio,
--	enum engine_id engine_id,
--	enum signal_type signal,
--	const struct audio_channel_associate_info *audio_mapping,
--	bool enable)
--{
--	audio->hw_ctx->funcs->setup_channel_splitting_mapping(
--		audio->hw_ctx,
--		engine_id,
--		signal,
--		audio_mapping, enable);
--}
--
--/* get current multi channel split. */
--static enum audio_result get_channel_splitting_mapping(
--	struct audio *audio,
--	enum engine_id engine_id,
--	struct audio_channel_associate_info *audio_mapping)
--{
--	if (audio->hw_ctx->funcs->get_channel_splitting_mapping(
--		audio->hw_ctx, engine_id, audio_mapping)) {
--		return AUDIO_RESULT_OK;
--	} else {
--		return AUDIO_RESULT_ERROR;
--	}
--}
--
--/**
--* set_unsolicited_response_payload
--*
--* @brief
--*  Set payload value for the unsolicited response
--*/
--static void set_unsolicited_response_payload(
--	struct audio *audio,
--	enum audio_payload payload)
--{
--	audio->hw_ctx->funcs->set_unsolicited_response_payload(
--			audio->hw_ctx, payload);
--}
--
--/**
--* setup_audio_wall_dto
--*
--* @brief
--*  Update audio source clock from hardware context.
--*
--*/
--static void setup_audio_wall_dto(
--	struct audio *audio,
--	enum signal_type signal,
--	const struct audio_crtc_info *crtc_info,
--	const struct audio_pll_info *pll_info)
--{
--	audio->hw_ctx->funcs->setup_audio_wall_dto(
--		audio->hw_ctx, signal, crtc_info, pll_info);
--}
--
--/**
--* get_supported_features
--*
--* @brief
--*  options and features supported by Audio
--*  returns supported engines, signals.
--*  features are reported for HW audio/Azalia block rather then Audio object
--*  itself the difference for DCE6.x is that MultiStream Audio is now supported
--*
--*/
--static struct audio_feature_support get_supported_features(struct audio *audio)
--{
--	struct audio_feature_support afs = {0};
--
--	afs.ENGINE_DIGA = 1;
--	afs.ENGINE_DIGB = 1;
--	afs.ENGINE_DIGC = 1;
--	afs.MULTISTREAM_AUDIO = 1;
--
--	return afs;
--}
--
--static const struct audio_funcs funcs = {
--	.destroy = destroy,
--	.setup = setup,
--	.enable_output = enable_output,
--	.disable_output = disable_output,
--	.unmute = unmute,
--	.mute = mute,
--	.initialize = initialize,
--	.enable_channel_splitting_mapping =
--		enable_channel_splitting_mapping,
--	.get_channel_splitting_mapping =
--		get_channel_splitting_mapping,
--	.set_unsolicited_response_payload =
--		set_unsolicited_response_payload,
--	.setup_audio_wall_dto = setup_audio_wall_dto,
--	.get_supported_features = get_supported_features,
--};
--
--static bool construct(
--	struct audio_dce112 *audio,
--	const struct audio_init_data *init_data)
--{
--	struct audio *base = &audio->base;
--
--	/* base audio construct*/
--	if (!dal_audio_construct_base(base, init_data))
--		return false;
--
--	/*vtable methods*/
--	base->funcs = &funcs;
--	return true;
--}
--
--/* --- audio scope functions  --- */
--
--struct audio *dal_audio_create_dce112(
--	const struct audio_init_data *init_data)
--{
--	/*allocate memory for audio_dce112 */
--	struct audio_dce112 *audio = dm_alloc(sizeof(*audio));
--
--	if (audio == NULL) {
--		ASSERT_CRITICAL(audio);
--		return NULL;
--	}
--	/*pointer to base_audio_block of audio_dce112 ==> audio base object */
--	if (construct(audio, init_data))
--		return &audio->base;
--
--	dal_logger_write(
--		init_data->ctx->logger,
--		LOG_MAJOR_ERROR,
--		LOG_MINOR_COMPONENT_AUDIO,
--		"Failed to create audio object for DCE11\n");
--
--	 /*release memory allocated if fail */
--	dm_free(audio);
--	return NULL;
--}
--
--/* Do not need expose construct_dce112 and destruct_dce112 becuase there is
-- *derived object after dce112
-- */
--
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h b/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
-deleted file mode 100644
-index 7c8d71c..0000000
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce112/audio_dce112.h
-+++ /dev/null
-@@ -1,40 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--#ifndef __DAL_AUDIO_DCE_112_H__
--#define __DAL_AUDIO_DCE_112_H__
--
--#include "audio/audio.h"
--#include "audio/hw_ctx_audio.h"
--#include "audio/dce112/hw_ctx_audio_dce112.h"
--
--struct audio_dce112 {
--	struct audio base;
--	/* dce-specific members are following */
--	/* none */
--};
--
--struct audio *dal_audio_create_dce112(const struct audio_init_data *init_data);
--
--#endif   /*__DAL_AUDIO_DCE_112_H__*/
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h b/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
-deleted file mode 100644
-index af61aad..0000000
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce112/hw_ctx_audio_dce112.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/*
-- * Copyright 2012-15 Advanced Micro Devices, Inc.
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a
-- * copy of this software and associated documentation files (the "Software"),
-- * to deal in the Software without restriction, including without limitation
-- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- * and/or sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
-- *
-- * Authors: AMD
-- *
-- */
--
--#ifndef __DAL_HW_CTX_AUDIO_DCE112_H__
--#define __DAL_HW_CTX_AUDIO_DCE112_H__
--
--#include "audio/hw_ctx_audio.h"
--
--struct hw_ctx_audio_dce112 {
--	struct hw_ctx_audio base;
--
--	/* azalia stream id 1 based indexing, corresponding to audio GO enumId*/
--	uint32_t azalia_stream_id;
--
--	/* azalia stream endpoint register offsets */
--	struct azalia_reg_offsets az_mm_reg_offsets;
--
--	/* audio encoder block MM register offset -- associate with DIG FRONT */
--};
--
--struct hw_ctx_audio *dal_hw_ctx_audio_dce112_create(
--	struct dc_context *ctx,
--	uint32_t azalia_stream_id);
--
--#endif  /* __DAL_HW_CTX_AUDIO_DCE110_H__ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1060-drm-amd-dal-Add-mininum-display-clock-check-fixed-80.patch b/common/recipes-kernel/linux/files/1060-drm-amd-dal-Add-mininum-display-clock-check-fixed-80.patch
deleted file mode 100644
index 3fefc84e..00000000
--- a/common/recipes-kernel/linux/files/1060-drm-amd-dal-Add-mininum-display-clock-check-fixed-80.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 5baf168389ff51aaa7966a375347ccdde640215a Mon Sep 17 00:00:00 2001
-From: Yongqiang Sun <yongqiang.sun@amd.com>
-Date: Wed, 20 Apr 2016 09:48:08 -0400
-Subject: [PATCH 1060/1110] drm/amd/dal: Add mininum display clock check, fixed
- 800x600 issue.
-
-Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c | 5 +++++
- drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c | 5 +++++
- 2 files changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-index 3d0f8e1..e498098 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
-@@ -786,6 +786,11 @@ static void set_clock(
- 	/* Prepare to program display clock*/
- 	memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
- 
-+	/* Make sure requested clock isn't lower than minimum threshold*/
-+	if (requested_clk_khz > 0)
-+		requested_clk_khz = dm_max(requested_clk_khz,
-+				base->min_display_clk_threshold_khz);
-+
- 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
- 	pxl_clk_params.pll_id = base->id;
- 
-diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-index 08a70db..34d1e72 100644
---- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
-@@ -772,6 +772,11 @@ static void set_clock(
- 	/* Prepare to program display clock*/
- 	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
- 
-+	/* Make sure requested clock isn't lower than minimum threshold*/
-+	if (requested_clk_khz > 0)
-+		requested_clk_khz = dm_max(requested_clk_khz,
-+				base->min_display_clk_threshold_khz);
-+
- 	dce_clk_params.target_clock_frequency = requested_clk_khz;
- 	dce_clk_params.pll_id = dc->disp_clk_base.id;
- 	dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1061-drm-amd-dal-Remove-empty-audio-base-class-functions.patch b/common/recipes-kernel/linux/files/1061-drm-amd-dal-Remove-empty-audio-base-class-functions.patch
deleted file mode 100644
index c9f3b784..00000000
--- a/common/recipes-kernel/linux/files/1061-drm-amd-dal-Remove-empty-audio-base-class-functions.patch
+++ /dev/null
@@ -1,387 +0,0 @@
-From 14fac719f849ec900a007a8c5a0fa99fde57debd Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Wed, 20 Apr 2016 17:05:19 -0400
-Subject: [PATCH 1061/1110] drm/amd/dal: Remove empty audio base class
- functions
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Acked-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c  |  10 -
- .../amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c    |  12 -
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c    | 267 ---------------------
- drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h    |   3 -
- 4 files changed, 292 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-index d8a674d..d2769c7 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
-@@ -57,12 +57,6 @@ static const uint32_t engine_offset[] = {
- 	mmDIG5_DIG_FE_CNTL - mmDIG0_DIG_FE_CNTL
- };
- 
--static void destruct(
--	struct hw_ctx_audio_dce110 *hw_ctx_dce110)
--{
--	dal_audio_destruct_hw_ctx_audio(&hw_ctx_dce110->base);
--}
--
- static void destroy(
- 	struct hw_ctx_audio **ptr)
- {
-@@ -71,7 +65,6 @@ static void destroy(
- 	hw_ctx_dce110 = container_of(
- 		*ptr, struct hw_ctx_audio_dce110, base);
- 
--	destruct(hw_ctx_dce110);
- 	/* release memory allocated for struct hw_ctx_audio_dce110 */
- 	dm_free(hw_ctx_dce110);
- 
-@@ -1832,9 +1825,6 @@ static bool construct(
- {
- 	struct hw_ctx_audio *base = &hw_ctx->base;
- 
--	if (!dal_audio_construct_hw_ctx_audio(base))
--		return false;
--
- 	base->funcs = &funcs;
- 
- 	/* save audio endpoint or dig front for current dce110 audio object */
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-index 5f6a433..3b2fb52 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/dce80/hw_ctx_audio_dce80.c
-@@ -66,7 +66,6 @@ static void destroy(
- 	hw_ctx_dce80 = container_of(
- 		*ptr, struct hw_ctx_audio_dce80, base);
- 
--	dal_audio_destruct_hw_ctx_audio_dce80(hw_ctx_dce80);
- 	/* release memory allocated for struct hw_ctx_audio_dce80 */
- 	dm_free(hw_ctx_dce80);
- 
-@@ -1773,9 +1772,6 @@ bool dal_audio_construct_hw_ctx_audio_dce80(
- {
- 	struct hw_ctx_audio *base = &hw_ctx->base;
- 
--	if (!dal_audio_construct_hw_ctx_audio(base))
--		return false;
--
- 	base->funcs = &funcs;
- 
- 	/* save audio endpoint or dig front for current dce80 audio object */
-@@ -1857,14 +1853,6 @@ bool dal_audio_construct_hw_ctx_audio_dce80(
- 	return true;
- }
- 
--/* audio_dce80 is derived from audio directly, not via dce80  */
--
--void dal_audio_destruct_hw_ctx_audio_dce80(
--	struct hw_ctx_audio_dce80 *hw_ctx_dce80)
--{
--	dal_audio_destruct_hw_ctx_audio(&hw_ctx_dce80->base);
--}
--
- struct hw_ctx_audio *dal_audio_create_hw_ctx_audio_dce80(
- 	struct dc_context *ctx,
- 	uint32_t azalia_stream_id)
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-index 6d88771..606e98b 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
-@@ -87,215 +87,6 @@ static const struct audio_clock_info audio_clock_info_table_48bpc[12] = {
- 
- /***** static function *****/
- 
--/*
-- * except of HW context create function, caller will access other functions of
-- * hw ctx via handle hw_ctx. Memory allocation for struct hw_ctx_audio_dce8x
-- * will happen in hw_ctx_audio_dce8x. Memory allocation is done with
-- * dal_audio_create_hw_ctx_audio_dce8x. Memory release is done by caller
-- * via hw_ctx->functions.destroy(). It will finally use destroy() of
-- * hw_ctx_audio_dce8x. Therefore, no memory allocate and release happen
-- * physically at hw ctx base object.
-- */
--static void destroy(
--	struct hw_ctx_audio **ptr)
--{
--	/* Attention!
--	 * You must override this method in derived class */
--}
--
--static void setup_audio_wall_dto(
--	const struct hw_ctx_audio *hw_ctx,
--	enum signal_type signal,
--	const struct audio_crtc_info *crtc_info,
--	const struct audio_pll_info *pll_info)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* setup HDMI audio */
--static void setup_hdmi_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id,
--	const struct audio_crtc_info *crtc_info)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
-- /* setup DP audio */
--static void setup_dp_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
-- /* setup VCE audio */
--static void setup_vce_audio(
--	const struct hw_ctx_audio *hw_ctx)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* enable Azalia audio */
--static void enable_azalia_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* disable Azalia audio */
--static void disable_azalia_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* enable DP audio */
--static void enable_dp_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* disable DP audio */
--static void disable_dp_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* setup Azalia HW block */
--static void setup_azalia(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id,
--	enum signal_type signal,
--	const struct audio_crtc_info *crtc_info,
--	const struct audio_pll_info *pll_info,
--	const struct audio_info *audio_info)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* unmute audio */
--static void unmute_azalia_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* mute audio */
--static void mute_azalia_audio(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* enable channel splitting mapping */
--static void setup_channel_splitting_mapping(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id,
--	enum signal_type signal,
--	const struct audio_channel_associate_info *audio_mapping,
--	bool enable)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* get current channel spliting */
--static bool get_channel_splitting_mapping(
--	const struct hw_ctx_audio *hw_ctx,
--	enum engine_id engine_id,
--	struct audio_channel_associate_info *audio_mapping)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--	return false;
--}
--
--/* set the payload value for the unsolicited response */
--static void set_unsolicited_response_payload(
--	const struct hw_ctx_audio *hw_ctx,
--	enum audio_payload payload)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* initialize HW state */
--static void hw_initialize(
--	const struct hw_ctx_audio *hw_ctx)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* Assign GTC group and enable GTC value embedding */
--static void enable_gtc_embedding_with_group(
--	const struct hw_ctx_audio *hw_ctx,
--	uint32_t groupNum,
--	uint32_t audioLatency)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* Disable GTC value embedding */
--static void disable_gtc_embedding(
--	const struct hw_ctx_audio *hw_ctx)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* Disable Azalia Clock Gating Feature */
--static void disable_az_clock_gating(
--	const struct hw_ctx_audio *hw_ctx)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--}
--
--/* search pixel clock value for Azalia HDMI Audio */
--static bool get_azalia_clock_info_hdmi(
--	const struct hw_ctx_audio *hw_ctx,
--	uint32_t crtc_pixel_clock_in_khz,
--	uint32_t actual_pixel_clock_in_khz,
--	struct azalia_clock_info *azalia_clock_info)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--	return false;
--}
--
--/* search pixel clock value for Azalia DP Audio */
--static bool get_azalia_clock_info_dp(
--	const struct hw_ctx_audio *hw_ctx,
--	uint32_t requested_pixel_clock_in_khz,
--	const struct audio_pll_info *pll_info,
--	struct azalia_clock_info *azalia_clock_info)
--{
--	/*DCE specific, must be implemented in derived*/
--	BREAK_TO_DEBUGGER();
--	return false;
--}
- 
- /*****SCOPE : within audio hw context dal-audio-hw-ctx *****/
- 
-@@ -700,61 +491,3 @@ bool dal_audio_hw_ctx_get_audio_clock_info(
- 	return true;
- }
- 
--static const struct hw_ctx_audio_funcs funcs = {
--	.destroy = destroy,
--	.setup_audio_wall_dto =
--		setup_audio_wall_dto,
--	.setup_hdmi_audio =
--		setup_hdmi_audio,
--	.setup_dp_audio = setup_dp_audio,
--	.setup_vce_audio = setup_vce_audio,
--	.enable_azalia_audio =
--		enable_azalia_audio,
--	.disable_azalia_audio =
--		disable_azalia_audio,
--	.enable_dp_audio =
--		enable_dp_audio,
--	.disable_dp_audio =
--		disable_dp_audio,
--	.setup_azalia =
--		setup_azalia,
--	.disable_az_clock_gating =
--		disable_az_clock_gating,
--	.unmute_azalia_audio =
--		unmute_azalia_audio,
--	.mute_azalia_audio =
--		mute_azalia_audio,
--	.setup_channel_splitting_mapping =
--		setup_channel_splitting_mapping,
--	.get_channel_splitting_mapping =
--		get_channel_splitting_mapping,
--	.set_unsolicited_response_payload =
--		set_unsolicited_response_payload,
--	.hw_initialize =
--		hw_initialize,
--	.enable_gtc_embedding_with_group =
--		enable_gtc_embedding_with_group,
--	.disable_gtc_embedding =
--		disable_gtc_embedding,
--	.get_azalia_clock_info_hdmi =
--		get_azalia_clock_info_hdmi,
--	.get_azalia_clock_info_dp =
--		get_azalia_clock_info_dp,
--};
--/* --- object creator, destroy, construct, destruct --- */
--
--bool dal_audio_construct_hw_ctx_audio(
--	struct hw_ctx_audio *ctx)
--{
--	ctx->funcs = &funcs;
--
--	/* internal variables */
--
--	return true;
--}
--
--void dal_audio_destruct_hw_ctx_audio(
--	struct hw_ctx_audio *ctx)
--{
--	/* nothing to do */
--}
-diff --git a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-index 52865c8..8143cd5 100644
---- a/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-+++ b/drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
-@@ -206,9 +206,6 @@ struct hw_ctx_audio {
- bool dal_audio_construct_hw_ctx_audio(
- 	struct hw_ctx_audio *hw_ctx);
- 
--void dal_audio_destruct_hw_ctx_audio(
--	struct hw_ctx_audio *hw_ctx);
--
- /*
-  *creator of audio HW context will be implemented by specific ASIC object only.
-  *Top base or interface object does not have implementation of creator.
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1062-Revert-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-chec.patch b/common/recipes-kernel/linux/files/1062-Revert-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-chec.patch
deleted file mode 100644
index 444199e0..00000000
--- a/common/recipes-kernel/linux/files/1062-Revert-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-chec.patch
+++ /dev/null
@@ -1,204 +0,0 @@
-From af51b260432f89486b5e5a1179122ae74c08b55f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 28 Apr 2016 15:37:12 -0400
-Subject: [PATCH 1062/1110] Revert "drm/amd/dal/dm: remove LINUX_VERSION_CODE
- checks"
-
-This reverts commit ed7a3875d5c335511580da9e4be9896f9210d244.
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c  | 26 ++++++++++++++++++++++
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  4 ++++
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  3 +++
- 3 files changed, 33 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-index 434fc5c..f85f55f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
-@@ -136,6 +136,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
- 	return result;
- }
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static struct amdgpu_connector *get_connector_for_sink(
- 	struct drm_device *dev,
- 	const struct dc_sink *sink)
-@@ -151,6 +152,7 @@ static struct amdgpu_connector *get_connector_for_sink(
- 
- 	return aconnector;
- }
-+#endif
- 
- static struct amdgpu_connector *get_connector_for_link(
- 	struct drm_device *dev,
-@@ -168,6 +170,7 @@ static struct amdgpu_connector *get_connector_for_link(
- 	return aconnector;
- }
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static void get_payload_table(
- 		struct amdgpu_connector *aconnector,
- 		struct dp_mst_stream_allocation_table *proposed_table)
-@@ -204,6 +207,7 @@ static void get_payload_table(
- 
- 	mutex_unlock(&mst_mgr->payload_lock);
- }
-+#endif
- 
- /*
-  * Writes payload allocation table in immediate downstream device.
-@@ -214,6 +218,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
- 		struct dp_mst_stream_allocation_table *proposed_table,
- 		bool enable)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -293,6 +298,9 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
- 		return false;
- 
- 	return true;
-+#else
-+	return false;
-+#endif
- }
- 
- /*
-@@ -303,6 +311,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		struct dc_context *ctx,
- 		const struct dc_stream *stream)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -325,6 +334,9 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
- 		return false;
- 
- 	return true;
-+#else
-+	return false;
-+#endif
- }
- 
- bool dm_helpers_dp_mst_send_payload_allocation(
-@@ -332,6 +344,7 @@ bool dm_helpers_dp_mst_send_payload_allocation(
- 		const struct dc_stream *stream,
- 		bool enable)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector;
-@@ -360,10 +373,14 @@ bool dm_helpers_dp_mst_send_payload_allocation(
- 		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
- 
- 	return true;
-+#else
-+	return false;
-+#endif
- }
- 
- void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	uint8_t esi[8] = { 0 };
- 	uint8_t dret;
- 	bool new_irq_handled = true;
-@@ -402,6 +419,9 @@ void dm_helpers_dp_mst_handle_mst_hpd_rx_irq(void *param)
- 				DP_SINK_COUNT_ESI, esi, 8);
- 		}
- 	}
-+#else
-+	return false;
-+#endif
- }
- 
- bool dm_helpers_dp_mst_start_top_mgr(
-@@ -409,6 +429,7 @@ bool dm_helpers_dp_mst_start_top_mgr(
- 		const struct dc_link *link,
- 		bool boot)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-@@ -423,12 +444,16 @@ bool dm_helpers_dp_mst_start_top_mgr(
- 			aconnector, aconnector->base.base.id);
- 
- 	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
-+#else
-+	return false;
-+#endif
- }
- 
- void dm_helpers_dp_mst_stop_top_mgr(
- 		struct dc_context *ctx,
- 		const struct dc_link *link)
- {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	struct amdgpu_device *adev = ctx->driver_context;
- 	struct drm_device *dev = adev->ddev;
- 	struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
-@@ -438,6 +463,7 @@ void dm_helpers_dp_mst_stop_top_mgr(
- 
- 	if (aconnector->mst_mgr.mst_state == true)
- 		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+#endif
- }
- 
- bool dm_helpers_dp_read_dpcd(
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index d73b246..9468c52 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -115,6 +115,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg
- 	return msg->size;
- }
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- static enum drm_connector_status
- dm_dp_mst_detect(struct drm_connector *connector, bool force)
- {
-@@ -466,6 +467,7 @@ struct drm_dp_mst_topology_cbs dm_mst_cbs = {
- 	.hotplug = dm_dp_mst_hotplug,
- 	.register_connector = dm_dp_mst_register_connector
- };
-+#endif
- 
- void amdgpu_dm_initialize_mst_connector(
- 	struct amdgpu_display_manager *dm,
-@@ -477,6 +479,7 @@ void amdgpu_dm_initialize_mst_connector(
- 	aconnector->dm_dp_aux.link_index = aconnector->connector_id;
- 
- 	drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
- 	aconnector->mst_mgr.cbs = &dm_mst_cbs;
- 	drm_dp_mst_topology_mgr_init(
- 		&aconnector->mst_mgr,
-@@ -485,5 +488,6 @@ void amdgpu_dm_initialize_mst_connector(
- 		16,
- 		4,
- 		aconnector->connector_id);
-+#endif
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 205d4a4..669b1ff 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1514,7 +1514,10 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 	if (!primary_plane)
- 		goto fail_plane;
- 
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
-+	/* this flag doesn't exist in older kernels */
- 	primary_plane->format_default = true;
-+#endif
- 
- 	res = drm_universal_plane_init(
- 		dm->adev->ddev,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1063-drm-amdgpu-add-pipeline-sync-for-compute-job.patch b/common/recipes-kernel/linux/files/1063-drm-amdgpu-add-pipeline-sync-for-compute-job.patch
deleted file mode 100644
index 63d5ea35..00000000
--- a/common/recipes-kernel/linux/files/1063-drm-amdgpu-add-pipeline-sync-for-compute-job.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 1ae41fd261b58aee381d59e7fbf0d5743bbc8b21 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Wed, 27 Apr 2016 18:07:41 +0800
-Subject: [PATCH 1063/1110] drm/amdgpu: add pipeline sync for compute job
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-hardware ring is async processed, the job is executed in parelell.
-In some case, this will result vm fault, like jobs with different vmids.
-
-Change-Id: Ia5446eba1eaf25a337cb14e857a7fc00862b718b
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 3a12305..6399429 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -307,7 +307,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
-         int r;
- 
-         if (ring->funcs->emit_pipeline_sync && (
--           pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed))
-+           pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
-+                    ring->type == AMDGPU_RING_TYPE_COMPUTE))
-                amdgpu_ring_emit_pipeline_sync(ring);
- 
- 	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1064-drm-amdgpu-fiji-set-UVD-CG-state-when-enabling-UVD-D.patch b/common/recipes-kernel/linux/files/1064-drm-amdgpu-fiji-set-UVD-CG-state-when-enabling-UVD-D.patch
deleted file mode 100644
index 3d5e6c53..00000000
--- a/common/recipes-kernel/linux/files/1064-drm-amdgpu-fiji-set-UVD-CG-state-when-enabling-UVD-D.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 31c74605adbf8b60f69dbba18acfec08da39d09b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 29 Apr 2016 11:20:32 -0400
-Subject: [PATCH 1064/1110] drm/amdgpu/fiji: set UVD CG state when enabling UVD
- DPM (v2)
-
-Need to call the IP cg callbacks.
-
-v2: fix gate logic
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c | 11 +++++++++--
- 1 file changed, 9 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
-index e68edf0..e1b649b 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
-@@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
- 
- 	data->uvd_power_gated = bgate;
- 
--	if (bgate)
-+	if (bgate) {
-+		cgs_set_clockgating_state(hwmgr->device,
-+					  AMD_IP_BLOCK_TYPE_UVD,
-+					  AMD_CG_STATE_GATE);
- 		fiji_update_uvd_dpm(hwmgr, true);
--	else
-+	} else {
- 		fiji_update_uvd_dpm(hwmgr, false);
-+		cgs_set_clockgating_state(hwmgr->device,
-+					  AMD_IP_BLOCK_TYPE_UVD,
-+					  AMD_PG_STATE_UNGATE);
-+	}
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch b/common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch
deleted file mode 100644
index 953a2687..00000000
--- a/common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From c97288faffbb08ce5ae43bcbe32f06c8ba7be0f6 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 29 Apr 2016 11:44:32 -0400
-Subject: [PATCH 1065/1110] drm/amdgpu/uvd6: add bypass support for fiji (v2)
-
-Handle uvd clock bypass settings as part of clockgating
-setup.
-
-v2: fix gate logic
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 5665a4f..d015cb0 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -31,6 +31,8 @@
- #include "uvd/uvd_6_0_sh_mask.h"
- #include "oss/oss_2_0_d.h"
- #include "oss/oss_2_0_sh_mask.h"
-+#include "smu/smu_7_1_3_d.h"
-+#include "smu/smu_7_1_3_sh_mask.h"
- #include "vi.h"
- 
- static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
-@@ -823,6 +825,20 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
- }
- #endif
- 
-+static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-+{
-+	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-+
-+	if (enable)
-+		tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
-+			GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-+	else
-+		tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
-+			 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-+
-+	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-+}
-+
- static int uvd_v6_0_set_clockgating_state(void *handle,
- 					  enum amd_clockgating_state state)
- {
-@@ -830,6 +846,9 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
- 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
- 	static int curstate = -1;
- 
-+	if (adev->asic_type == CHIP_FIJI)
-+		uvd_v6_set_bypass_mode(adev, enable);
-+
- 	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
- 		return 0;
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1066-drm-amdgpu-check-if-ring-emit_vm_flush-exists-in-vm-.patch b/common/recipes-kernel/linux/files/1066-drm-amdgpu-check-if-ring-emit_vm_flush-exists-in-vm-.patch
deleted file mode 100644
index 24fdb903..00000000
--- a/common/recipes-kernel/linux/files/1066-drm-amdgpu-check-if-ring-emit_vm_flush-exists-in-vm-.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From e167a00f9ab0c0fbbc2e9434f58a3407ee860f3f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 28 Apr 2016 17:03:19 -0400
-Subject: [PATCH 1066/1110] drm/amdgpu: check if ring emit_vm_flush exists in
- vm flush
-
-No vm flush on engines that don't support VM.
-
-bug:
-https://bugs.freedesktop.org/show_bug.cgi?id=95195
-
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 6399429..fd691d0 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -311,7 +311,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
-                     ring->type == AMDGPU_RING_TYPE_COMPUTE))
-                amdgpu_ring_emit_pipeline_sync(ring);
- 
--	if (pd_addr != AMDGPU_VM_NO_FLUSH) {
-+        if (ring->funcs->emit_vm_flush &&
-+            pd_addr != AMDGPU_VM_NO_FLUSH) {
-                 struct fence *fence;
- 
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1067-drm-powerplay-add-missing-clockgating-callback-for-t.patch b/common/recipes-kernel/linux/files/1067-drm-powerplay-add-missing-clockgating-callback-for-t.patch
deleted file mode 100644
index b9dc98d9..00000000
--- a/common/recipes-kernel/linux/files/1067-drm-powerplay-add-missing-clockgating-callback-for-t.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 941e3156b08177555082890c31d6964aef1b8b60 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 28 Apr 2016 17:19:41 -0400
-Subject: [PATCH 1067/1110] drm/powerplay: add missing clockgating callback for
- tonga
-
-Without this clockgating is not enabled.
-
-Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 9aaf194..670b628 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -6214,6 +6214,7 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
- 	.powergate_uvd = tonga_phm_powergate_uvd,
- 	.powergate_vce = tonga_phm_powergate_vce,
- 	.disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
-+	.update_clock_gatings = tonga_phm_update_clock_gatings,
- 	.notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
- 	.display_config_changed = tonga_display_configuration_changed_task,
- 	.set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1068-drm-amd-amdgpu-Convert-ring-debugfs-entries-to-binar.patch b/common/recipes-kernel/linux/files/1068-drm-amd-amdgpu-Convert-ring-debugfs-entries-to-binar.patch
deleted file mode 100644
index 43af72e2..00000000
--- a/common/recipes-kernel/linux/files/1068-drm-amd-amdgpu-Convert-ring-debugfs-entries-to-binar.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From bf28c7fc27b7d737c407843e08fa1848d4e33499 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 27 Apr 2016 12:41:16 -0400
-Subject: [PATCH 1068/1110] drm/amd/amdgpu: Convert ring debugfs entries to
- binary
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-They now emit ring data in binary which will be read/written by
-the userspace tool umr shortly.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 127 +++++++++++++++----------------
- 1 file changed, 62 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 3b02272..7e1bc73 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -28,6 +28,7 @@
-  */
- #include <linux/seq_file.h>
- #include <linux/slab.h>
-+#include <linux/debugfs.h>
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
- #include "amdgpu.h"
-@@ -364,57 +365,62 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
-  */
- #if defined(CONFIG_DEBUG_FS)
- 
--static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
-+/* Layout of file is 12 bytes consisting of
-+ * - rptr
-+ * - wptr
-+ * - driver's copy of wptr
-+ *
-+ * followed by n-words of ring data
-+ */
-+static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
-+					size_t size, loff_t *pos)
- {
--	struct drm_info_node *node = (struct drm_info_node *) m->private;
--	struct drm_device *dev = node->minor->dev;
--	struct amdgpu_device *adev = dev->dev_private;
--	int roffset = (unsigned long)node->info_ent->data;
--	struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset);
--	uint32_t rptr, wptr, rptr_next;
--	unsigned i;
--
--	wptr = amdgpu_ring_get_wptr(ring);
--	seq_printf(m, "wptr: 0x%08x [%5d]\n", wptr, wptr);
--
--	rptr = amdgpu_ring_get_rptr(ring);
--	rptr_next = le32_to_cpu(*ring->next_rptr_cpu_addr);
--
--	seq_printf(m, "rptr: 0x%08x [%5d]\n", rptr, rptr);
--
--	seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
--		   ring->wptr, ring->wptr);
--
--	if (!ring->ready)
--		return 0;
--
--	/* print 8 dw before current rptr as often it's the last executed
--	 * packet that is the root issue
--	 */
--	i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
--	while (i != rptr) {
--		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
--		if (i == rptr)
--			seq_puts(m, " *");
--		if (i == rptr_next)
--			seq_puts(m, " #");
--		seq_puts(m, "\n");
--		i = (i + 1) & ring->ptr_mask;
-+	struct amdgpu_ring *ring = (struct amdgpu_ring*)f->f_inode->i_private;
-+	int r, i;
-+	uint32_t value, result, early[3];
-+
-+	if (*pos & 3)
-+		return -EINVAL;
-+
-+	result = 0;
-+
-+	if (*pos < 12) {
-+		early[0] = amdgpu_ring_get_rptr(ring);
-+		early[1] = amdgpu_ring_get_wptr(ring);
-+		early[2] = ring->wptr;
-+		for (i = *pos / 4; i < 3 && size; i++) {
-+			r = put_user(early[i], (uint32_t *)buf);
-+			if (r)
-+				return r;
-+			buf += 4;
-+			result += 4;
-+			size -= 4;
-+			*pos += 4;
-+		}
- 	}
--	while (i != wptr) {
--		seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
--		if (i == rptr)
--			seq_puts(m, " *");
--		if (i == rptr_next)
--			seq_puts(m, " #");
--		seq_puts(m, "\n");
--		i = (i + 1) & ring->ptr_mask;
-+
-+	while (size) {
-+		if (*pos >= (ring->ring_size + 12))
-+			return result;
-+			
-+		value = ring->ring[(*pos - 12)/4];
-+		r = put_user(value, (uint32_t*)buf);
-+		if (r)
-+			return r;
-+		buf += 4;
-+		result += 4;
-+		size -= 4;
-+		*pos += 4;
- 	}
--	return 0;
-+
-+	return result;
- }
- 
--static struct drm_info_list amdgpu_debugfs_ring_info_list[AMDGPU_MAX_RINGS];
--static char amdgpu_debugfs_ring_names[AMDGPU_MAX_RINGS][32];
-+static const struct file_operations amdgpu_debugfs_ring_fops = {
-+	.owner = THIS_MODULE,
-+	.read = amdgpu_debugfs_ring_read,
-+	.llseek = default_llseek
-+};
- 
- #endif
- 
-@@ -422,28 +428,19 @@ static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
- 				    struct amdgpu_ring *ring)
- {
- #if defined(CONFIG_DEBUG_FS)
--	unsigned offset = (uint8_t*)ring - (uint8_t*)adev;
--	unsigned i;
--	struct drm_info_list *info;
--	char *name;
--
--	for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
--		info = &amdgpu_debugfs_ring_info_list[i];
--		if (!info->data)
--			break;
--	}
-+	struct drm_minor *minor = adev->ddev->primary;
-+	struct dentry *ent, *root = minor->debugfs_root;
-+	char name[32];
- 
--	if (i == ARRAY_SIZE(amdgpu_debugfs_ring_info_list))
--		return -ENOSPC;
--
--	name = &amdgpu_debugfs_ring_names[i][0];
- 	sprintf(name, "amdgpu_ring_%s", ring->name);
--	info->name = name;
--	info->show = amdgpu_debugfs_ring_info;
--	info->driver_features = 0;
--	info->data = (void*)(uintptr_t)offset;
- 
--	return amdgpu_debugfs_add_files(adev, info, 1);
-+	ent = debugfs_create_file(name,
-+				  S_IFREG | S_IRUGO, root,
-+				  ring, &amdgpu_debugfs_ring_fops);
-+	if (IS_ERR(ent))
-+		return PTR_ERR(ent);
-+
-+	i_size_write(ent->d_inode, ring->ring_size + 12);
- #endif
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1069-drm-amd-amdgpu-ring-debugfs-is-read-in-increments-of.patch b/common/recipes-kernel/linux/files/1069-drm-amd-amdgpu-ring-debugfs-is-read-in-increments-of.patch
deleted file mode 100644
index ca6ed9b1..00000000
--- a/common/recipes-kernel/linux/files/1069-drm-amd-amdgpu-ring-debugfs-is-read-in-increments-of.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 8e2a49bedf717ddbd2df377cdea674509b594b63 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 2 May 2016 08:35:35 -0400
-Subject: [PATCH 1069/1110] drm/amd/amdgpu: ring debugfs is read in increments
- of 4 bytes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If a user tries to read a non-multiple of 4 bytes it would have
-read until the end of the ring potentially crashing the user
-task.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 7e1bc73..1b0b7ae 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -379,7 +379,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
- 	int r, i;
- 	uint32_t value, result, early[3];
- 
--	if (*pos & 3)
-+	if (*pos & 3 || size & 3)
- 		return -EINVAL;
- 
- 	result = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1070-drm-amd-amdgpu-Enable-CG-for-UVD6-on-Carrizo.patch b/common/recipes-kernel/linux/files/1070-drm-amd-amdgpu-Enable-CG-for-UVD6-on-Carrizo.patch
deleted file mode 100644
index f4c5fdf9..00000000
--- a/common/recipes-kernel/linux/files/1070-drm-amd-amdgpu-Enable-CG-for-UVD6-on-Carrizo.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 61e2bd5d0bc53e83de7b591e6a9ab848ba84e1ef Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 3 May 2016 10:36:28 -0400
-Subject: [PATCH 1070/1110] drm/amd/amdgpu: Enable CG for UVD6 on Carrizo
-
-Tested via vdpau/mpv.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 61f5555..cc5ebd3 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1522,7 +1522,8 @@ static int vi_common_early_init(void *handle)
- 		adev->external_rev_id = adev->rev_id + 0x50;
- 		break;
- 	case CHIP_CARRIZO:
--		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
-+		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
-+			AMD_CG_SUPPORT_GFX_MGCG |
- 			AMD_CG_SUPPORT_GFX_MGLS |
- 			AMD_CG_SUPPORT_GFX_RLC_LS |
- 			AMD_CG_SUPPORT_GFX_CP_LS |
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1071-drm-amd-dal-change-default-to-use-SW-i2c.patch b/common/recipes-kernel/linux/files/1071-drm-amd-dal-change-default-to-use-SW-i2c.patch
deleted file mode 100644
index 04202d6b..00000000
--- a/common/recipes-kernel/linux/files/1071-drm-amd-dal-change-default-to-use-SW-i2c.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 53638aa2435972cf5beaa818b623f02de111bd97 Mon Sep 17 00:00:00 2001
-From: Eric Yang <eric.yang2@amd.com>
-Date: Thu, 17 Mar 2016 16:05:47 -0400
-Subject: [PATCH 1071/1110] drm/amd/dal: change default to use SW i2c
-
-Make SW i2c engine the default. However, since all dces except
-dce80 do not create sw i2c engine, they will still use hw i2c.
-This allow enabling/disabling of sw i2c through the feature flag
-FEATURE_RESTORE_USAGE_I2C_SW_ENGINE. DCE80 is the only dce that
-has sw i2c engine enabled right now due to bug in hw i2c. This
-fixes EDID read failure on bonaire. No behaviour change on other
-dces.
-
-Signed-off-by: Eric Yang <eric.yang2@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
----
- drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-index 2d394cf..a84901e 100644
---- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
-@@ -122,7 +122,15 @@ bool dal_i2caux_submit_i2c_command(
- 		return false;
- 	}
- 
-+	/*
-+	 * default will be SW, however there is a feature flag in adapter
-+	 * service that determines whether SW i2c_engine will be available or
-+	 * not, if sw i2c is not available we will fallback to hw. This feature
-+	 * flag is set to not creating sw i2c engine for every dce except dce80
-+	 * currently
-+	 */
- 	switch (cmd->engine) {
-+	case I2C_COMMAND_ENGINE_DEFAULT:
- 	case I2C_COMMAND_ENGINE_SW:
- 		/* try to acquire SW engine first,
- 		 * acquire HW engine if SW engine not available */
-@@ -133,7 +141,6 @@ bool dal_i2caux_submit_i2c_command(
- 				i2caux, ddc);
- 	break;
- 	case I2C_COMMAND_ENGINE_HW:
--	case I2C_COMMAND_ENGINE_DEFAULT:
- 	default:
- 		/* try to acquire HW engine first,
- 		 * acquire SW engine if HW engine not available */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1072-drm-amdgpu-hdp-flush-inval-should-always-do.patch b/common/recipes-kernel/linux/files/1072-drm-amdgpu-hdp-flush-inval-should-always-do.patch
deleted file mode 100644
index 534c8981..00000000
--- a/common/recipes-kernel/linux/files/1072-drm-amdgpu-hdp-flush-inval-should-always-do.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 339c80958dc2ab9e6cfc3b1c4744500f4099be81 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Wed, 4 May 2016 16:27:41 +0800
-Subject: [PATCH 1072/1110] drm/amdgpu:hdp flush&inval should always do
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This fixes Tonga vm-fault issue when running disaster
-(a multiple context GL heavy tests),
-We should always flush & invalidate hdp no matter vm
-used or not.
-
-Change-Id: Idc18cf413bfe21ec02d92c92598693c27060502a
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <David1.Zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index f879ffb..21f717a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -175,10 +175,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
-                 amdgpu_ring_emit_ib(ring, ib, (i == 0 && old != fence_context));
- 	}
- 
--	if (vm) {
--		if (ring->funcs->emit_hdp_invalidate)
--			amdgpu_ring_emit_hdp_invalidate(ring);
--	}
-+        if (ring->funcs->emit_hdp_invalidate)
-+                amdgpu_ring_emit_hdp_invalidate(ring);
-+
-         ring->last_fence_context = fence_context;
- 
- 	r = amdgpu_fence_emit(ring, &hwf);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1073-drm-amdgpu-two-minor-80-char-fixes.patch b/common/recipes-kernel/linux/files/1073-drm-amdgpu-two-minor-80-char-fixes.patch
deleted file mode 100644
index b295caab..00000000
--- a/common/recipes-kernel/linux/files/1073-drm-amdgpu-two-minor-80-char-fixes.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From d3b7d736483beaa9bc75f35f5e7ef01105196bfb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 3 May 2016 18:46:19 +0200
-Subject: [PATCH 1073/1110] drm/amdgpu: two minor 80 char fixes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 10 ++++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c    |  3 ++-
- drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c |  7 ++++---
- 3 files changed, 12 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 35de174..98bb206 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -511,9 +511,10 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
- 				struct drm_file *file_priv);
- unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
- struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
--struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
--							struct dma_buf_attachment *attach,
--							struct sg_table *sg);
-+struct drm_gem_object *
-+amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
-+				 struct dma_buf_attachment *attach,
-+				 struct sg_table *sg);
- struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
- 					struct drm_gem_object *gobj,
- 					int flags);
-@@ -1195,7 +1196,8 @@ struct amdgpu_gfx {
- 
- int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 		  unsigned size, struct amdgpu_ib *ib);
--void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
-+void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
-+                    struct fence *f);
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
-                        struct amdgpu_ib *ib, struct fence *last_vm_update,
-                        struct amdgpu_job *job, struct fence **f);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 21f717a..8d1387d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -88,7 +88,8 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-  *
-  * Free an IB (all asics).
-  */
--void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f)
-+void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
-+		    struct fence *f)
- {
- 	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-index 32b0247..b4fe303 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-@@ -57,9 +57,10 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
- 	ttm_bo_kunmap(&bo->dma_buf_vmap);
- }
- 
--struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
--							struct dma_buf_attachment *attach,
--							struct sg_table *sg)
-+struct drm_gem_object *
-+amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
-+				 struct dma_buf_attachment *attach,
-+				 struct sg_table *sg)
- {
- 	struct reservation_object *resv = attach->dmabuf->resv;
- 	struct amdgpu_device *adev = dev->dev_private;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1074-drm-amdgpu-make-the-VMID-owner-always-64bit.patch b/common/recipes-kernel/linux/files/1074-drm-amdgpu-make-the-VMID-owner-always-64bit.patch
deleted file mode 100644
index 5004c7f6..00000000
--- a/common/recipes-kernel/linux/files/1074-drm-amdgpu-make-the-VMID-owner-always-64bit.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 6660641e1b3c7161aba6e1b63407f9333746db6e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 4 May 2016 10:20:01 +0200
-Subject: [PATCH 1074/1110] drm/amdgpu: make the VMID owner always 64bit
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Otherwise we could (in theory) run into problems on 32bit systems.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 98bb206..0b6ef3d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -897,7 +897,7 @@ struct amdgpu_vm_id {
-         struct amdgpu_sync      active;
-         struct fence            *last_flush;
-         struct amdgpu_ring      *last_user;
--	atomic_long_t		owner;
-+        atomic64_t              owner;
- 
-         uint64_t                pd_gpu_addr;
-         /* last flushed PD/PT update */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index fd691d0..b6df43d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -192,7 +192,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 		if (!id)
- 			continue;
- 
--		if (atomic_long_read(&id->owner) != vm->client_id)
-+		if (atomic64_read(&id->owner) != vm->client_id)
- 			continue;
- 
- 		if (pd_addr != id->pd_gpu_addr)
-@@ -268,7 +268,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- 
- 	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
- 	id->last_user = ring;
--	atomic_long_set(&id->owner, vm->client_id);
-+	atomic64_set(&id->owner, vm->client_id);
- 	vm->ids[ring->idx] = id;
- 
- 	*vm_id = id - adev->vm_manager.ids;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1075-drm-amdgpu-remove-owner-cleanup-v2.patch b/common/recipes-kernel/linux/files/1075-drm-amdgpu-remove-owner-cleanup-v2.patch
deleted file mode 100644
index 8dedd4f8..00000000
--- a/common/recipes-kernel/linux/files/1075-drm-amdgpu-remove-owner-cleanup-v2.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 7a2f6b5c821fb681186d162676b1a3241285e464 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 4 May 2016 10:33:11 +0200
-Subject: [PATCH 1075/1110] drm/amdgpu: remove owner cleanup v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The client ID is now unique, so no need to resert the owner fields any more.
-
-v2: remove unused variables as well
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ------------
- 1 file changed, 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index b6df43d..ab0df1a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -1461,7 +1461,6 @@ error_free_sched_entity:
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
- 	struct amdgpu_bo_va_mapping *mapping, *tmp;
--        struct amdgpu_vm_id *id, *id_tmp;
- 	int i;
- 
-         amd_sched_entity_fini(vm->entity.sched, &vm->entity);
-@@ -1486,17 +1485,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	amdgpu_bo_unref(&vm->page_directory);
- 	fence_put(vm->page_directory_fence);
- 
--        mutex_lock(&adev->vm_manager.lock);
--        list_for_each_entry_safe(id, id_tmp, &adev->vm_manager.ids_lru,
--                                 list) {
--		if (!id)
--			continue;
--                if (atomic_long_read(&id->owner) == vm->client_id) {
--                        atomic_long_set(&id->owner, 0);
--                        id->pd_gpu_addr = 0;
--                }
--	}
--        mutex_unlock(&adev->vm_manager.lock);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1076-drm-amdgpu-remove-define-for-reserved-client-ID.patch b/common/recipes-kernel/linux/files/1076-drm-amdgpu-remove-define-for-reserved-client-ID.patch
deleted file mode 100644
index 37bccf03..00000000
--- a/common/recipes-kernel/linux/files/1076-drm-amdgpu-remove-define-for-reserved-client-ID.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 62705b399af17e982f2d8a10ea6d74653cb5fd15 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 4 May 2016 10:34:03 +0200
-Subject: [PATCH 1076/1110] drm/amdgpu: remove define for reserved client ID
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Just set it to zero instead.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index ab0df1a..d5c079f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -1507,7 +1507,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 			      &adev->vm_manager.ids_lru);
-         }
- 
--        atomic64_set(&adev->vm_manager.client_counter, AMDGPU_CLIENT_ID_RESERVED);
-+        atomic64_set(&adev->vm_manager.client_counter, 0);
- }
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1077-drm-amd-cleanup-DAL-spaces-and-tabs-v2.patch b/common/recipes-kernel/linux/files/1077-drm-amd-cleanup-DAL-spaces-and-tabs-v2.patch
deleted file mode 100644
index 2b1f4930..00000000
--- a/common/recipes-kernel/linux/files/1077-drm-amd-cleanup-DAL-spaces-and-tabs-v2.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 9d38f3abd4239254f3f4fb7bc0da6314e3bc934d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 4 May 2016 09:50:07 +0200
-Subject: [PATCH 1077/1110] drm/amd: cleanup DAL spaces and tabs v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is the result of running the following commands:
-find drivers/gpu/drm/amd/dal/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \;
-find drivers/gpu/drm/amd/dal/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \;
-find drivers/gpu/drm/amd/dal/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \;
-find drivers/gpu/drm/amd/dal/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \;
-
-v2: separate DAL changes
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c           | 2 +-
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h       | 4 ++--
- drivers/gpu/drm/amd/dal/dc/core/dc_link.c               | 4 ++--
- drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c | 2 +-
- 4 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 71b2808..6e812b6 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -1143,7 +1143,7 @@ static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
- 
- /**
-  * dm_page_flip - called by amdgpu_flip_work_func(), which is triggered
-- * 			via DRM IOCTL, by user mode.
-+ *			via DRM IOCTL, by user mode.
-  *
-  * @adev: amdgpu_device pointer
-  * @crtc_id: crtc to cleanup pageflip on
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-index 9339861..7f6d9ea 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
-@@ -60,8 +60,8 @@ void amdgpu_dm_irq_fini(
-  * @handler_args: arguments which will be passed to ih
-  *
-  * Returns:
-- * 	IRQ Handler Index on success.
-- * 	NULL on failure.
-+ *	IRQ Handler Index on success.
-+ *	NULL on failure.
-  *
-  * Cannot be called from an interrupt handler.
-  */
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-index 6d715c2..141bbba 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
-@@ -100,10 +100,10 @@ static bool program_hpd_filter(
- 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
- 		/* Program hpd filter to allow DP signal to settle */
- 		/* 500:	not able to detect MST <-> SST switch as HPD is low for
--		 * 	only 100ms on DELL U2413
-+		 *	only 100ms on DELL U2413
- 		 * 0:	some passive dongle still show aux mode instead of i2c
- 		 * 20-50:not enough to hide bouncing HPD with passive dongle.
--		 * 	also see intermittent i2c read issues.
-+		 *	also see intermittent i2c read issues.
- 		 */
- 		delay_on_connect_in_ms = 80;
- 		delay_on_disconnect_in_ms = 0;
-diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-index d48e3df..1690319 100644
---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
-@@ -875,7 +875,7 @@ static void get_ss_info_from_atombios(
- 							     as_signal,
- 							     i,
- 							     ss_info_cur);
--		
-+
- 		if (bp_result != BP_RESULT_OK)
- 			goto out_free_data;
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1078-drm-amd-cleanup-remaining-spaces-and-tabs-v2.patch b/common/recipes-kernel/linux/files/1078-drm-amd-cleanup-remaining-spaces-and-tabs-v2.patch
deleted file mode 100644
index bccd71a2..00000000
--- a/common/recipes-kernel/linux/files/1078-drm-amd-cleanup-remaining-spaces-and-tabs-v2.patch
+++ /dev/null
@@ -1,462 +0,0 @@
-From e60ad8ac6cce639f277ea57ec141f75f927c0d6e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Tue, 3 May 2016 15:54:54 +0200
-Subject: [PATCH 1078/1110] drm/amd: cleanup remaining spaces and tabs v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is the result of running the following commands:
-find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \;
-find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \;
-find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \;
-find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \;
-
-v2: drop changes to DAL and internal headers
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c           |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c            |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h               |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h              |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c               |  6 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c               |  6 +++---
- drivers/gpu/drm/amd/amdgpu/atom.h                     |  2 +-
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c                   |  2 +-
- drivers/gpu/drm/amd/amdgpu/cik_ih.c                   |  2 +-
- drivers/gpu/drm/amd/amdgpu/cikd.h                     |  4 ++--
- drivers/gpu/drm/amd/amdgpu/cz_ih.c                    |  2 +-
- drivers/gpu/drm/amd/amdgpu/cz_smumgr.h                |  2 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c                 |  2 +-
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c                 |  6 +++---
- drivers/gpu/drm/amd/amdgpu/vid.h                      |  2 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c      |  6 +++---
- drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c |  8 ++++----
- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c      |  4 ++--
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c     |  8 ++++----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h     | 18 +++++++++---------
- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h             |  2 +-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h         |  2 +-
- 22 files changed, 50 insertions(+), 50 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index 17a2f83..d2b03e1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -264,7 +264,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
- 		for (i = 0; i < args->in.bo_number; ++i) {
- 			if (copy_from_user(&info[i], uptr, bytes))
- 				goto error_free;
--			
-+
- 			uptr += args->in.bo_info_size;
- 		}
- 	}
-@@ -272,7 +272,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
- 	switch (args->in.operation) {
- 	case AMDGPU_BO_LIST_OP_CREATE:
- 		r = amdgpu_bo_list_create(fpriv, &list, &handle);
--		if (r) 
-+		if (r)
- 			goto error_free;
- 
- 		r = amdgpu_bo_list_set(adev, filp, list, info,
-@@ -282,7 +282,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
- 			goto error_free;
- 
- 		break;
--		
-+
- 	case AMDGPU_BO_LIST_OP_DESTROY:
- 		amdgpu_bo_list_destroy(fpriv, handle);
- 		handle = 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 56e4627..4dbab46 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -348,7 +348,7 @@ static int amdgpu_doorbell_init(struct amdgpu_device *adev)
- 	adev->doorbell.base = pci_resource_start(adev->pdev, 2);
- 	adev->doorbell.size = pci_resource_len(adev->pdev, 2);
- 
--	adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), 
-+	adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
- 					     AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
- 	if (adev->doorbell.num_doorbells == 0)
- 		return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
-index c3f4e85..503d540 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
-@@ -43,7 +43,7 @@ struct amdgpu_ring;
- struct amdgpu_bo;
- 
- struct amdgpu_gds_asic_info {
--	uint32_t 	total_size;
-+	uint32_t	total_size;
- 	uint32_t	gfx_partition_size;
- 	uint32_t	cs_partition_size;
- };
-@@ -52,8 +52,8 @@ struct amdgpu_gds {
- 	struct amdgpu_gds_asic_info	mem;
- 	struct amdgpu_gds_asic_info	gws;
- 	struct amdgpu_gds_asic_info	oa;
--	/* At present, GDS, GWS and OA resources for gfx (graphics) 
--	 * is always pre-allocated and available for graphics operation. 
-+	/* At present, GDS, GWS and OA resources for gfx (graphics)
-+	 * is always pre-allocated and available for graphics operation.
- 	 * Such resource is shared between all gfx clients.
- 	 * TODO: move this operation to user space
- 	 * */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 3d8c7c5..a8173b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -585,7 +585,7 @@ struct amdgpu_mst_connector {
- 				((em) == ATOM_ENCODER_MODE_DP_MST))
- 
- /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
--#define USE_REAL_VBLANKSTART 		(1 << 30)
-+#define USE_REAL_VBLANKSTART		(1 << 30)
- #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
- 
- void amdgpu_link_encoder_connector(struct drm_device *dev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 7c44f74..f58dd0a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -45,9 +45,9 @@
- /* Firmware Names */
- #ifdef CONFIG_DRM_AMDGPU_CIK
- #define FIRMWARE_BONAIRE	"radeon/bonaire_uvd.bin"
--#define FIRMWARE_KABINI 	"radeon/kabini_uvd.bin"
--#define FIRMWARE_KAVERI 	"radeon/kaveri_uvd.bin"
--#define FIRMWARE_HAWAII 	"radeon/hawaii_uvd.bin"
-+#define FIRMWARE_KABINI	"radeon/kabini_uvd.bin"
-+#define FIRMWARE_KAVERI	"radeon/kaveri_uvd.bin"
-+#define FIRMWARE_HAWAII	"radeon/hawaii_uvd.bin"
- #define FIRMWARE_MULLINS	"radeon/mullins_uvd.bin"
- #endif
- #define FIRMWARE_TONGA		"amdgpu/tonga_uvd.bin"
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 97c3268..db7509c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -41,9 +41,9 @@
- /* Firmware Names */
- #ifdef CONFIG_DRM_AMDGPU_CIK
- #define FIRMWARE_BONAIRE	"radeon/bonaire_vce.bin"
--#define FIRMWARE_KABINI 	"radeon/kabini_vce.bin"
--#define FIRMWARE_KAVERI 	"radeon/kaveri_vce.bin"
--#define FIRMWARE_HAWAII 	"radeon/hawaii_vce.bin"
-+#define FIRMWARE_KABINI	"radeon/kabini_vce.bin"
-+#define FIRMWARE_KAVERI	"radeon/kaveri_vce.bin"
-+#define FIRMWARE_HAWAII	"radeon/hawaii_vce.bin"
- #define FIRMWARE_MULLINS	"radeon/mullins_vce.bin"
- #endif
- #define FIRMWARE_TONGA		"amdgpu/tonga_vce.bin"
-diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h
-index fece8f4..49daf6d 100644
---- a/drivers/gpu/drm/amd/amdgpu/atom.h
-+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
-@@ -92,7 +92,7 @@
- #define ATOM_WS_AND_MASK	0x45
- #define ATOM_WS_FB_WINDOW	0x46
- #define ATOM_WS_ATTRIBUTES	0x47
--#define ATOM_WS_REGPTR  	0x48
-+#define ATOM_WS_REGPTR		0x48
- 
- #define ATOM_IIO_NOP		0
- #define ATOM_IIO_START		1
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 90f83b2..2f24797 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -6363,7 +6363,7 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
- }
- 
- static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
--				    struct amdgpu_irq_src *source, 
-+				    struct amdgpu_irq_src *source,
- 				    struct amdgpu_iv_entry *entry)
- {
- 	bool queue_thermal = false;
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-index f2f14fe..7e750a4 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-@@ -243,7 +243,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
- 	/* wptr/rptr are in bytes! */
- 	u32 ring_index = adev->irq.ih.rptr >> 2;
- 	uint32_t dw[4];
--	
-+
- 	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
- 	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
- 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
-index 60d4493..c4f6f00 100644
---- a/drivers/gpu/drm/amd/amdgpu/cikd.h
-+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
-@@ -190,8 +190,8 @@
- #       define MACRO_TILE_ASPECT(x)				((x) << 4)
- #       define NUM_BANKS(x)					((x) << 6)
- 
--#define		MSG_ENTER_RLC_SAFE_MODE      			1
--#define		MSG_EXIT_RLC_SAFE_MODE      			0
-+#define		MSG_ENTER_RLC_SAFE_MODE			1
-+#define		MSG_EXIT_RLC_SAFE_MODE			0
- 
- /*
-  * PM4
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-index 23bd912..874b928 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-@@ -222,7 +222,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
- 	/* wptr/rptr are in bytes! */
- 	u32 ring_index = adev->irq.ih.rptr >> 2;
- 	uint32_t dw[4];
--	
-+
- 	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
- 	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
- 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
-index 924d355..026342f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
-@@ -77,7 +77,7 @@ struct cz_smu_private_data {
- 	uint8_t		driver_buffer_length;
- 	uint8_t		scratch_buffer_length;
- 	uint16_t	toc_entry_used_count;
--	uint16_t 	toc_entry_initialize_index;
-+	uint16_t	toc_entry_initialize_index;
- 	uint16_t	toc_entry_power_profiling_index;
- 	uint16_t	toc_entry_aram;
- 	uint16_t	toc_entry_ih_register_restore_task_index;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index c2941ba..ba8d786 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -603,7 +603,7 @@ static const u32 stoney_golden_settings_a11[] =
- 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
- 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
- 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
--  	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
-+	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
- 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
- 	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
- 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index e1d6ae7..55b35da 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -40,9 +40,9 @@
- 
- #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT	0x04
- #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK	0x10
--#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 	0x8616
--#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 	0x8617
--#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 	0x8618
-+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0	0x8616
-+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1	0x8617
-+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2	0x8618
- 
- #define VCE_V3_0_FW_SIZE	(384 * 1024)
- #define VCE_V3_0_STACK_SIZE	(64 * 1024)
-diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
-index ace4997..3bf7172 100644
---- a/drivers/gpu/drm/amd/amdgpu/vid.h
-+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
-@@ -365,7 +365,7 @@
- #define VCE_CMD_IB		0x00000002
- #define VCE_CMD_FENCE		0x00000003
- #define VCE_CMD_TRAP		0x00000004
--#define VCE_CMD_IB_AUTO 	0x00000005
-+#define VCE_CMD_IB_AUTO	0x00000005
- #define VCE_CMD_SEMAPHORE	0x00000006
- 
- #endif
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-index 55e877c..d05a5e0 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
-@@ -465,14 +465,14 @@ static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
- 			table_info->vdd_dep_on_mclk;
- 
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
--		"VDD dependency on SCLK table is missing. 	\
-+		"VDD dependency on SCLK table is missing.	\
- 		This table is mandatory", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
--		"VDD dependency on SCLK table has to have is missing. 	\
-+		"VDD dependency on SCLK table has to have is missing.	\
- 		This table is mandatory", return -EINVAL);
- 
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
--		"VDD dependency on MCLK table is missing. 	\
-+		"VDD dependency on MCLK table is missing.	\
- 		This table is mandatory", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
- 		"VDD dependency on MCLK table has to have is missing.	 \
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-index 010199f..dbdcc68 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
-@@ -2900,14 +2900,14 @@ static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
- 						table_info->vdd_dep_on_mclk;
- 
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
--		"VDD dependency on SCLK table is missing. 	\
-+		"VDD dependency on SCLK table is missing.	\
- 		This table is mandatory", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
--		"VDD dependency on SCLK table has to have is missing. 	\
-+		"VDD dependency on SCLK table has to have is missing.	\
- 		This table is mandatory", return -EINVAL);
- 
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
--		"VDD dependency on MCLK table is missing. 	\
-+		"VDD dependency on MCLK table is missing.	\
- 		This table is mandatory", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
- 		"VDD dependency on MCLK table has to have is missing.	 \
-@@ -4628,7 +4628,7 @@ int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
- 	data->need_long_memory_training = true;
- 
- /*
-- * 	PPMCME_FirmwareDescriptorEntry *pfd = NULL;
-+ *	PPMCME_FirmwareDescriptorEntry *pfd = NULL;
- 	pfd = &tonga_mcmeFirmware;
- 	if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
- 		polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-index 8ba3ad5..da9f5f1 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
-@@ -1041,10 +1041,10 @@ int atomctrl_calculate_voltage_evv_on_sclk(
- }
- 
- /** atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table.
-- * @param hwmgr               	input: pointer to hwManager
-+ * @param hwmgr	input: pointer to hwManager
-  * @param voltage_type            input: type of EVV voltage VDDC or VDDGFX
-  * @param sclk                        input: in 10Khz unit. DPM state SCLK frequency
-- *                                   		which is define in PPTable SCLK/VDDC dependence
-+ *		which is define in PPTable SCLK/VDDC dependence
-  *				table associated with this virtual_voltage_Id
-  * @param virtual_voltage_Id      input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
-  * @param voltage		       output: real voltage level in unit of mv
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 670b628..d79af48 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -2683,7 +2683,7 @@ static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
- struct TONGA_DLL_SPEED_SETTING {
- 	uint16_t            Min;                          /* Minimum Data Rate*/
- 	uint16_t            Max;                          /* Maximum Data Rate*/
--	uint32_t 			dll_speed;                     /* The desired DLL_SPEED setting*/
-+	uint32_t			dll_speed;                     /* The desired DLL_SPEED setting*/
- };
- 
- static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-@@ -3316,14 +3316,14 @@ static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
- 		pptable_info->vdd_dep_on_mclk;
- 
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
--		"VDD dependency on SCLK table is missing. 	\
-+		"VDD dependency on SCLK table is missing.	\
- 		This table is mandatory", return -1);
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
--		"VDD dependency on SCLK table has to have is missing. 	\
-+		"VDD dependency on SCLK table has to have is missing.	\
- 		This table is mandatory", return -1);
- 
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
--		"VDD dependency on MCLK table is missing. 	\
-+		"VDD dependency on MCLK table is missing.	\
- 		This table is mandatory", return -1);
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
- 		"VDD dependency on MCLK table has to have is missing.	 \
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-index c6a6b40..573cd39 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
-@@ -74,7 +74,7 @@ struct tonga_power_state {
- };
- 
- struct _phw_tonga_dpm_level {
--	bool  		enabled;
-+	bool		enabled;
- 	uint32_t    value;
- 	uint32_t    param1;
- };
-@@ -237,20 +237,20 @@ struct tonga_hwmgr {
- 	irq_handler_func_t             ctf_callback;
- 	void                             *ctf_context;
- 
--	phw_tonga_clock_registers      	  clock_registers;
-+	phw_tonga_clock_registers	  clock_registers;
- 	phw_tonga_voltage_smio_registers  voltage_smio_registers;
- 
--	bool                         	is_memory_GDDR5;
-+	bool	is_memory_GDDR5;
- 	uint16_t                          acpi_vddc;
--	bool                         	pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
-+	bool	pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
- 	uint16_t                          force_pcie_gen;            /* The forced PCI-E speed if not 0xffff */
- 	uint16_t                          acpi_pcie_gen;             /* The PCI-E speed at ACPI time */
- 	uint32_t                           pcie_gen_cap;             /* The PCI-E speed capabilities bitmap from CAIL */
- 	uint32_t                           pcie_lane_cap;            /* The PCI-E lane capabilities bitmap from CAIL */
- 	uint32_t                           pcie_spc_cap;             /* Symbol Per Clock Capabilities from registry */
--	phw_tonga_leakage_voltage       	vddc_leakage;            /* The Leakage VDDC supported (based on leakage ID).*/
--	phw_tonga_leakage_voltage       	vddcgfx_leakage;         /* The Leakage VDDC supported (based on leakage ID). */
--	phw_tonga_leakage_voltage       	vddci_leakage;           /* The Leakage VDDCI supported (based on leakage ID). */
-+	phw_tonga_leakage_voltage	vddc_leakage;            /* The Leakage VDDC supported (based on leakage ID).*/
-+	phw_tonga_leakage_voltage	vddcgfx_leakage;         /* The Leakage VDDC supported (based on leakage ID). */
-+	phw_tonga_leakage_voltage	vddci_leakage;           /* The Leakage VDDCI supported (based on leakage ID). */
- 
- 	uint32_t                           mvdd_control;
- 	uint32_t                           vddc_mask_low;
-@@ -263,8 +263,8 @@ struct tonga_hwmgr {
- 	uint32_t                           mclk_stutter_mode_threshold;
- 	uint32_t                           mclk_edc_enable_threshold;
- 	uint32_t                           mclk_edc_wr_enable_threshold;
--	bool                         	is_uvd_enabled;
--	bool                         	is_xdma_enabled;
-+	bool	is_uvd_enabled;
-+	bool	is_xdma_enabled;
- 	phw_tonga_vbios_boot_state      vbios_boot_state;
- 
- 	bool                         battery_state;
-diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-index c96e5b1..fd4ce7a 100644
---- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
-@@ -500,7 +500,7 @@ struct phm_dynamic_state_info {
- 	struct phm_ppm_table                          *ppm_parameter_table;
- 	struct phm_cac_tdp_table                      *cac_dtp_table;
- 	struct phm_clock_voltage_dependency_table	  *vdd_gfx_dependency_on_sclk;
--	struct phm_vq_budgeting_table		  		  *vq_budgeting_table;
-+	struct phm_vq_budgeting_table				  *vq_budgeting_table;
- };
- 
- struct pp_fan_info {
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index 169f70f..070095a 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -74,7 +74,7 @@ struct amd_sched_fence {
- 	struct amd_gpu_scheduler	*sched;
- 	spinlock_t			lock;
- 	void                            *owner;
--	struct amd_sched_job 	*s_job;
-+	struct amd_sched_job	*s_job;
- };
- 
- struct amd_sched_job {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1079-drm-amdgpu-fix-compilation-errors-during-backport.patch b/common/recipes-kernel/linux/files/1079-drm-amdgpu-fix-compilation-errors-during-backport.patch
deleted file mode 100644
index e75ac6ac..00000000
--- a/common/recipes-kernel/linux/files/1079-drm-amdgpu-fix-compilation-errors-during-backport.patch
+++ /dev/null
@@ -1,1247 +0,0 @@
-From eff368e9d9685a68e0ca6a58523e0d391fc559f0 Mon Sep 17 00:00:00 2001
-From: kalle <kalle@amd.com>
-Date: Sat, 11 Jun 2016 22:53:41 +0530
-Subject: [PATCH 1079/1110] drm/amdgpu: fix compilation errors during backport
-
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile                |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu.h                | 19 ++++----
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c        |  3 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c             | 28 +++++------
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c         |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c             | 15 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h         |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c            | 33 ++++---------
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c            | 31 +++---------
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c            | 56 ++++++----------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h            |  2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c             | 21 +++-----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c             | 14 +++---
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c             | 14 +++---
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c              |  9 ++--
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              | 11 ++---
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c              |  1 -
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c             |  2 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c             |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c              |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c              |  2 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c              |  2 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |  3 +-
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    |  7 ++-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c      | 41 ++++++++--------
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h      |  1 +
- drivers/gpu/drm/drm_crtc_helper.c                  |  2 +-
- drivers/gpu/drm/drm_pci.c                          | 20 ++++++++
- drivers/gpu/drm/ttm/ttm_bo.c                       | 12 +++++
- include/drm/drmP.h                                 |  1 +
- include/drm/drm_crtc.h                             |  2 +-
- include/drm/drm_crtc_helper.h                      |  2 +-
- include/drm/ttm/ttm_bo_api.h                       | 10 ++++
- include/drm/ttm/ttm_bo_driver.h                    | 12 +++++
- 34 files changed, 183 insertions(+), 203 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index 948d8a6..215f8fc 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -99,7 +99,7 @@ amdgpu-y += amdgpu_cgs.o
- amdgpu-y += \
- 	../scheduler/gpu_scheduler.o \
- 	../scheduler/sched_fence.o \
--	amdgpu_sched.o
-+	amdgpu_job.o
- 
- # ACP componet
- ifneq ($(CONFIG_DRM_AMD_ACP),)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0b6ef3d..0f7de1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -285,7 +285,7 @@ struct amdgpu_ring_funcs {
- 	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
- 	/* command emit functions */
- 	void (*emit_ib)(struct amdgpu_ring *ring,
--			struct amdgpu_ib *ib);
-+			struct amdgpu_ib *ib, bool ctx_switch);
- 	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
- 			   uint64_t seq, unsigned flags);
- 	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
-@@ -475,7 +475,6 @@ struct amdgpu_bo {
- 	/* Protected by gem.mutex */
- 	struct list_head		list;
- 	/* Protected by tbo.reserved */
--	u32				initial_domain;
-         u32                             prefered_domains;
-         u32                             allowed_domains;
- 	struct ttm_place		placements[AMDGPU_GEM_DOMAIN_MAX + 1];
-@@ -746,7 +745,6 @@ struct amdgpu_ib {
- 	struct amdgpu_user_fence        *user;
-         unsigned                        vm_id;
-         uint64_t                        vm_pd_addr;
--	struct amdgpu_ctx		*ctx;
- 	uint32_t			gds_base, gds_size;
- 	uint32_t			gws_base, gws_size;
- 	uint32_t			oa_base, oa_size;
-@@ -764,8 +762,11 @@ enum amdgpu_ring_type {
- };
- 
- extern const struct amd_sched_backend_ops amdgpu_sched_ops;
--int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
-+int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-                       struct amdgpu_job **job, struct amdgpu_vm *vm);
-+int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
-+                      struct amdgpu_job **job);
-+
- void amdgpu_job_free(struct amdgpu_job *job);
- void amdgpu_job_free_func(struct kref *refcount);
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
-@@ -805,7 +806,7 @@ struct amdgpu_ring {
- 	unsigned		wptr_offs;
- 	unsigned		next_rptr_offs;
- 	unsigned		fence_offs;
--	struct amdgpu_ctx	*current_ctx;
-+	uint64_t last_fence_context;
- 	enum amdgpu_ring_type	type;
- 	char			name[16];
- 	unsigned		cond_exe_offs;
-@@ -937,9 +938,6 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
--					       struct amdgpu_vm *vm,
--					       struct list_head *head);
--struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
-                                                struct amdgpu_vm *vm,
-                                                struct list_head *validated,
-                                                struct list_head *duplicates);
-@@ -1048,7 +1046,7 @@ struct amdgpu_bo_list {
- 	struct amdgpu_bo *gds_obj;
- 	struct amdgpu_bo *gws_obj;
- 	struct amdgpu_bo *oa_obj;
--	bool has_userptr;
-+        unsigned first_userptr;
- 	unsigned num_entries;
- 	struct amdgpu_bo_list_entry *array;
- };
-@@ -1263,6 +1261,7 @@ struct amdgpu_job {
-         struct fence            *fence; /* the hw fence */
- 	uint32_t		num_ibs;
- 	void			*owner;
-+        uint64_t                        fence_context;
- 	struct amdgpu_user_fence uf;
- };
- #define to_amdgpu_job(sched_job)		\
-@@ -2235,7 +2234,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
- #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
- #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
--#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
-+#define amdgpu_ring_emit_ib(r, ib, f) (r)->funcs->emit_ib((r), (ib), (f))
- #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
- #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
- #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index d2b03e1..db36de6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -93,6 +93,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 
-         unsigned last_entry = 0, first_userptr = num_entries;
- 	unsigned i;
-+	int r;
- 
- 	array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry));
- 	if (!array)
-@@ -106,7 +107,6 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
-                 struct mm_struct *usermm;
- 
- 		gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
--		if (!gobj)
-                 if (!gobj) {
-                         r = -ENOENT;
- 			goto error_free;
-@@ -122,7 +122,6 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
-                                 r = -EPERM;
-                                 goto error_free;
-                         }
--                        has_userptr = true;
-                         entry = &array[--first_userptr];
-                 } else {
-                         entry = &array[last_entry++];
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 7e8b6bb..bff83e6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -166,8 +166,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 	uint64_t *chunk_array_user;
- 	uint64_t *chunk_array;
-         struct amdgpu_user_fence uf = {};
--	unsigned size;
--        unsigned size, num_ibs = 0;
-+	unsigned size, num_ibs = 0;
- 	int i;
- 	int ret;
- 
-@@ -235,7 +234,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 
- 		switch (p->chunks[i].chunk_id) {
- 		case AMDGPU_CHUNK_ID_IB:
--			p->num_ibs++;
-+			++num_ibs;
- 			break;
- 
- 		case AMDGPU_CHUNK_ID_FENCE:
-@@ -405,16 +404,17 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 
- static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- {
-+	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-         struct amdgpu_cs_buckets buckets;
-         struct amdgpu_bo_list_entry *e;
- 	struct list_head duplicates;
- 	bool need_mmap_lock = false;
-         unsigned i, tries = 10;
--
--	int i, r;
-+        int  r;
- 	
- 	if (p->bo_list) {
--		need_mmap_lock = p->bo_list->has_userptr;
-+                need_mmap_lock = p->bo_list->first_userptr !=
-+                        p->bo_list->num_entries;
-                 amdgpu_cs_buckets_init(&buckets);
-                 for (i = 0; i < p->bo_list->num_entries; i++)
-                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
-@@ -533,8 +533,10 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
-         }
- 
- error_validate:
--	if (r)
-+	if (r) {
-+		amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
- 		ttm_eu_backoff_reservation(&p->ticket, &p->validated);
-+	}		
- 
- error_free_pages:
- 
-@@ -584,6 +586,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
-  **/
- static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
- {
-+	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
- 	unsigned i;
- 
- 	if (!error) {
-@@ -623,7 +626,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- 	if (r)
- 		return r;
- 
--        r = amdgpu_sync_fence(adev, &p->job->ibs[0].sync, vm->page_directory_fence);
-+        r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
- 	if (r)
- 		return r;
- 
-@@ -788,7 +791,6 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 
- 		ib->length_dw = chunk_ib->ib_bytes / 4;
- 		ib->flags = chunk_ib->flags;
--		ib->ctx = parser->ctx;
- 		j++;
- 	}
- 
-@@ -884,12 +886,6 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 	return 0;
- }
- 
--static int amdgpu_cs_free_job(struct amdgpu_job *job)
--{
--        amdgpu_job_free(job);
--	return 0;
--}
--
- static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 			    union drm_amdgpu_cs *cs)
- {
-@@ -908,7 +904,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
-                                                 p->filp, &fence);
-         if (r) {
- 	
-- 	         amdgpu_cs_free_job(job);
-+ 	         amdgpu_job_free(job);
- 		return r;
- 	}
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 4dbab46..58a4faa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1445,8 +1445,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	adev->num_rings = 0;
- 	adev->mman.buffer_funcs = NULL;
- 	adev->mman.buffer_funcs_ring = NULL;
-+	adev->vm_manager.vm_pte_funcs = NULL;
-         adev->vm_manager.vm_pte_num_rings = 0;
--	adev->vm_manager.vm_pte_funcs_ring = NULL;
- 	adev->gart.gart_funcs = NULL;
- 	adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index 8d1387d..b987f47 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -151,6 +151,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		return r;
- 	}
- 
-+	if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec)
-+		patch_offset = amdgpu_ring_init_cond_exec(ring);
-+
- 	if (vm) {
- 		/* do context switch */
-                 r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
-@@ -160,27 +163,24 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
-                 if (r) {
-                         amdgpu_ring_undo(ring);
-                         return r;
--                }
--
-+                    }
-+		}
- 		if (ring->funcs->emit_hdp_flush)
- 			amdgpu_ring_emit_hdp_flush(ring);
--	}
- 
- 	/* always set cond_exec_polling to CONTINUE */
- 	*ring->cond_exe_cpu_addr = 1;
- 
--	old_ctx = ring->current_ctx;
- 	for (i = 0; i < num_ibs; ++i) {
- 		ib = &ibs[i];
- 
--                amdgpu_ring_emit_ib(ring, ib, (i == 0 && old != fence_context));
-+		amdgpu_ring_emit_ib(ring, ib, (i == 0 && old != fence_context));
- 	}
-+        ring->last_fence_context = fence_context;
- 
-         if (ring->funcs->emit_hdp_invalidate)
-                 amdgpu_ring_emit_hdp_invalidate(ring);
- 
--        ring->last_fence_context = fence_context;
--
- 	r = amdgpu_fence_emit(ring, &hwf);
- 	if (r) {
- 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
-@@ -198,7 +198,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		amdgpu_ring_emit_fence(ring, addr, ib->sequence,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
--	
- 	if(f)
-         *f = fence_get(hwf);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-index bdb01d9..b769de4 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-@@ -71,7 +71,7 @@ static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
- {
- 	int r;
- 
--	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
-+	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, NULL);
- 	if (unlikely(r != 0)) {
- 		if (r != -ERESTARTSYS)
- 			dev_err(bo->adev->dev, "%p reserve failed\n", bo);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index e296415..b602052 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -973,7 +973,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
- 	.io_mem_free = &amdgpu_ttm_io_mem_free,
- 	.lru_removal = &amdgpu_ttm_lru_removal,
- 	.lru_tail = &amdgpu_ttm_lru_tail,
--	.swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
-+        .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
- };
- 
- int amdgpu_ttm_init(struct amdgpu_device *adev)
-@@ -1148,9 +1148,9 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 		       struct fence **fence)
- {
- 	struct amdgpu_device *adev = ring->adev;
-+	struct amdgpu_job *job;
- 	uint32_t max_bytes;
- 	unsigned num_loops, num_dw;
--	struct amdgpu_ib *ib;
- 	unsigned i;
- 	int r;
- 
-@@ -1161,18 +1161,9 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	/* for IB padding */
- 	while (num_dw & 0x7)
- 		num_dw++;
--
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib)
--		return -ENOMEM;
--
--        r = amdgpu_ib_get(adev, NULL, num_dw * 4, ib);
--	if (r) {
--		kfree(ib);
-+	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
-+	if (r) 
- 		return r;
--	}
--
--	ib->length_dw = 0;
- 
- 	if (resv) {
-                 r = amdgpu_sync_resv(adev, &job->sync, resv,
-@@ -1186,27 +1177,23 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	for (i = 0; i < num_loops; i++) {
- 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
- 
--		amdgpu_emit_copy_buffer(adev, ib, src_offset, dst_offset,
-+		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, dst_offset,
- 					cur_size_in_bytes);
- 
- 		src_offset += cur_size_in_bytes;
- 		dst_offset += cur_size_in_bytes;
- 		byte_count -= cur_size_in_bytes;
- 	}
--
--	amdgpu_ring_pad_ib(ring, ib);
--	WARN_ON(ib->length_dw > num_dw);
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--						 &amdgpu_vm_free_job,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 fence);
-+	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
-+	WARN_ON(job->ibs[0].length_dw > num_dw);
-+	r = amdgpu_job_submit(job, ring, &adev->mman.entity,
-+                              AMDGPU_FENCE_OWNER_UNDEFINED, fence);
- 	if (r)
- 		goto error_free;
- 
- 	return 0;
- error_free:
--	amdgpu_ib_free(adev, ib);
--	kfree(ib);
-+        amdgpu_job_free(job);
- 	return r;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index f58dd0a..88a7942 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -860,14 +860,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
- 	return 0;
- }
- 
--static int amdgpu_uvd_free_job(
--	struct amdgpu_job *job)
--{
--	amdgpu_ib_free(job->adev, job->ibs);
--	kfree(job->ibs);
--	return 0;
--}
--
- static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
-                               bool direct, struct fence **fence)
- 
-@@ -875,7 +867,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 	struct ttm_validate_buffer tv;
- 	struct ww_acquire_ctx ticket;
- 	struct list_head head;
--	struct amdgpu_ib *ib = NULL;
-+	struct amdgpu_job *job;
-+	struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
- 	struct amdgpu_device *adev = ring->adev;
- 	uint64_t addr;
-@@ -899,15 +892,11 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
- 	if (r)
- 		goto err;
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib) {
--		r = -ENOMEM;
--		goto err;
--	}
--        r = amdgpu_ib_get(adev, NULL, 64, ib);
-+	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
- 	if (r)
--		goto err1;
-+		goto err;
- 
-+	ib = &job->ibs[0];
- 	addr = amdgpu_bo_gpu_offset(bo);
- 	ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
- 	ib->ptr[1] = addr;
-@@ -919,10 +908,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 		ib->ptr[i] = PACKET2(0);
- 	ib->length_dw = 16;
- 
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--						 &amdgpu_uvd_free_job,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-         if (direct) {
-                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-                 job->fence = f;
-@@ -945,10 +930,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 	fence_put(f);
- 
- 	return 0;
--err2:
--	amdgpu_ib_free(ring->adev, ib);
--err1:
--	kfree(ib);
-+err_free:
-+	amdgpu_job_free(job);
- err:
- 	ttm_eu_backoff_reservation(&ticket, &head);
- 	return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index db7509c..7aa7342 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -371,14 +371,6 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
- 	}
- }
- 
--static int amdgpu_vce_free_job(
--	struct amdgpu_job *job)
--{
--	amdgpu_ib_free(job->adev, job->ibs);
--	kfree(job->ibs);
--	return 0;
--}
--
- /**
-  * amdgpu_vce_get_create_msg - generate a VCE create msg
-  *
-@@ -393,22 +385,17 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 			      struct fence **fence)
- {
- 	const unsigned ib_size_dw = 1024;
-+	struct amdgpu_job *job;
- 	struct amdgpu_ib *ib = NULL;
- 	struct fence *f = NULL;
--	struct amdgpu_device *adev = ring->adev;
- 	uint64_t dummy;
- 	int i, r;
- 
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib)
--		return -ENOMEM;
--        r = amdgpu_ib_get(adev, NULL, ib_size_dw * 4, ib);
--	if (r) {
--		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
--		kfree(ib);
-+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
-+	if (r) 
- 		return r;
--	}
- 
-+	ib = &job->ibs[0];	
- 	dummy = ib->gpu_addr + 1024;
- 
- 	/* stitch together an VCE create msg */
-@@ -448,10 +435,6 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	for (i = ib->length_dw; i < ib_size_dw; ++i)
- 		ib->ptr[i] = 0x0;
- 
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--						 &amdgpu_vce_free_job,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
-         r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-                  job->fence = f;
- 	if (r)
-@@ -463,8 +446,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	fence_put(f);
- 	return 0;
- err:
--	amdgpu_ib_free(adev, ib);
--	kfree(ib);
-+	amdgpu_job_free(job);
- 	return r;
- }
- 
-@@ -482,23 +464,17 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
-                                bool direct, struct fence **fence)
- {
- 	const unsigned ib_size_dw = 1024;
--	struct amdgpu_ib *ib = NULL;
-+	struct amdgpu_job *job;
-+        struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
--	struct amdgpu_device *adev = ring->adev;
- 	uint64_t dummy;
- 	int i, r;
- 
--	ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
--	if (!ib)
--		return -ENOMEM;
--
--        r = amdgpu_ib_get(adev, NULL, ib_size_dw * 4, ib);
--	if (r) {
--		kfree(ib);
--		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
-+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);	
-+	if (r) 
- 		return r;
--	}
--
-+	
-+	ib = &job->ibs[0];
- 	dummy = ib->gpu_addr + 1024;
- 
- 	/* stitch together an VCE destroy msg */
-@@ -518,13 +494,10 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 
- 	for (i = ib->length_dw; i < ib_size_dw; ++i)
- 		ib->ptr[i] = 0x0;
--	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
--						 &amdgpu_vce_free_job,
--						 AMDGPU_FENCE_OWNER_UNDEFINED,
--						 &f);
- 
-        if (direct) {
-                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-+		job->fence = f;
-                 if (r)
-                         goto err;
- 
-@@ -541,8 +514,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	fence_put(f);
- 	return 0;
- err:
--	amdgpu_ib_free(adev, ib);
--	kfree(ib);
-+	amdgpu_job_free(job);
- 	return r;
- }
- 
-@@ -787,7 +759,7 @@ out:
-  * @ib: the IB to execute
-  *
-  */
--void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
-+void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	amdgpu_ring_write(ring, VCE_CMD_IB);
- 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-index ef99d23..40d0650 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
-@@ -34,7 +34,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 			       bool direct, struct fence **fence);
- void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
- int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
--void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
-+void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, bool ctx_switch);
- void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
- 				unsigned flags);
- int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index d5c079f..7eee8ae 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -113,14 +113,6 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
-         unsigned i;
- 
- 	/* add the vm page table to the list */
--	list[0].robj = vm->page_directory;
--	list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
--	list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
--	list[0].priority = 0;
--	list[0].tv.bo = &vm->page_directory->tbo;
--	list[0].tv.shared = true;
--        list_add(&list[0].tv.head, validated);
--
-         for (i = 0; i <= vm->max_pde_used; ++i) {
-                 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-  
-@@ -481,7 +473,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	if (r)
- 		goto error_free;
- 
--        amdgpu_bo_fence(bo, fence, true)
-+        amdgpu_bo_fence(bo, fence, true);
- 	fence_put(fence);
- 	return 0;
- 
-@@ -611,6 +603,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 		fence_put(fence);
-         } else {
-                 amdgpu_job_free(job);
-+	}
- 
- 	return 0;
- 
-@@ -727,9 +720,6 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-                                   uint64_t start, uint64_t end,
-                                   uint64_t dst, uint32_t flags)
- {
--	uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
--	uint64_t last_pte = ~0, last_dst = ~0;
--	unsigned count = 0;
-         const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
-  
-         uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0;
-@@ -1382,7 +1372,6 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
-  */
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
--        struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
- 	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
- 		AMDGPU_VM_PTE_COUNT * 8);
- 	unsigned pd_size, pd_entries;
-@@ -1432,7 +1421,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
-                 goto error_free_sched_entity;
- 
- 	r = amdgpu_bo_reserve(vm->page_directory, false);
--	r = amdgpu_vm_clear_bo(adev, vm->page_directory);
-+	if (r)
-+                goto error_free_page_directory;
-+
-+	r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
- 	amdgpu_bo_unreserve(vm->page_directory);
-         if (r)
-                 goto error_free_page_directory;
-@@ -1502,6 +1494,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 
- 	/* skip over VMID 0, since it is the system VM */
-         for (i = 1; i < adev->vm_manager.num_ids; ++i) {
-+		 amdgpu_vm_reset_id(adev, i);
-                  amdgpu_sync_create(&adev->vm_manager.ids[i].active);
- 		list_add_tail(&adev->vm_manager.ids[i].list,
- 			      &adev->vm_manager.ids_lru);
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 609aa36..8f27dd5 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -3726,7 +3726,7 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- 		drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--				 DRM_MODE_ENCODER_DAC, NULL);
-+				 DRM_MODE_ENCODER_DAC);
- 		drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3737,15 +3737,15 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- 			amdgpu_encoder->rmx_type = RMX_FULL;
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS, NULL);
-+					 DRM_MODE_ENCODER_LVDS);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC, NULL);
-+					 DRM_MODE_ENCODER_DAC);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		} else {
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS, NULL);
-+					 DRM_MODE_ENCODER_TMDS);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		}
- 		drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
-@@ -3763,13 +3763,13 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- 		amdgpu_encoder->is_ext_encoder = true;
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS, NULL);
-+					 DRM_MODE_ENCODER_LVDS);
- 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC, NULL);
-+					 DRM_MODE_ENCODER_DAC);
- 		else
- 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS, NULL);
-+					 DRM_MODE_ENCODER_TMDS);
- 		drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 9c7ea3c..b95abde 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -3789,7 +3789,7 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- 		drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--				 DRM_MODE_ENCODER_DAC, NULL);
-+				 DRM_MODE_ENCODER_DAC);
- 		drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
- 		break;
- 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3800,15 +3800,15 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- 			amdgpu_encoder->rmx_type = RMX_FULL;
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS, NULL);
-+					 DRM_MODE_ENCODER_LVDS);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC, NULL);
-+					 DRM_MODE_ENCODER_DAC);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		} else {
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS, NULL);
-+					 DRM_MODE_ENCODER_TMDS);
- 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- 		}
- 		drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
-@@ -3826,13 +3826,13 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- 		amdgpu_encoder->is_ext_encoder = true;
- 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_LVDS, NULL);
-+					 DRM_MODE_ENCODER_LVDS);
- 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_DAC, NULL);
-+					 DRM_MODE_ENCODER_DAC);
- 		else
- 			drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
--					 DRM_MODE_ENCODER_TMDS, NULL);
-+					 DRM_MODE_ENCODER_TMDS);
- 		drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
- 		break;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index ef1a800..ea19760 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2029,9 +2029,8 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
-  * on the gfx ring for execution by the GPU.
-  */
- static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
--	bool need_ctx_switch = ring->current_ctx != ib->ctx;
- 	u32 header, control = 0;
- 	u32 next_rptr = ring->wptr + 5;
- 
-@@ -2039,7 +2038,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- 	if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
- 		return;
- 
--	if (need_ctx_switch)
-+	if (ctx_switch)
- 		next_rptr += 2;
- 
- 	next_rptr += 4;
-@@ -2050,7 +2049,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, next_rptr);
- 
- 	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
--	if (need_ctx_switch) {
-+	if (ctx_switch) {
- 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
- 		amdgpu_ring_write(ring, 0);
- 	}
-@@ -2073,7 +2072,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- }
- 
- static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	u32 header, control = 0;
- 	u32 next_rptr = ring->wptr + 5;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index ba8d786..d35fa43 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -5644,17 +5644,16 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
- }
- 
- static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
--	bool need_ctx_switch = ring->current_ctx != ib->ctx;
- 	u32 header, control = 0;
- 	u32 next_rptr = ring->wptr + 5;
- 
- 	/* drop the CE preamble IB for the same context */
--	if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
-+	if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !ctx_switch)
- 		return;
- 
--	if (need_ctx_switch)
-+	if (ctx_switch)
- 		next_rptr += 2;
- 
- 	next_rptr += 4;
-@@ -5665,7 +5664,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- 	amdgpu_ring_write(ring, next_rptr);
- 
- 	/* insert SWITCH_BUFFER packet before first IB in the ring frame */
--	if (need_ctx_switch) {
-+	if (ctx_switch) {
- 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
- 		amdgpu_ring_write(ring, 0);
- 	}
-@@ -5688,7 +5687,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- }
- 
- static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	u32 header, control = 0;
- 	u32 next_rptr = ring->wptr + 5;
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index cae8f26..b7a96db 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -1054,7 +1054,6 @@ static int gmc_v7_0_suspend(void *handle)
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev->vm_manager.enabled) {
--		amdgpu_vm_manager_fini(adev);
- 		gmc_v7_0_vm_fini(adev);
- 		adev->vm_manager.enabled = false;
- 	}
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 6bfdb3f..474d6f1 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -242,7 +242,7 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
-  * Schedule an IB in the DMA ring (VI).
-  */
- static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
--				   struct amdgpu_ib *ib)
-+				   struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	u32 vmid = ib->vm_id & 0xf;
- 	u32 next_rptr = ring->wptr + 5;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 798d39b..77186f5 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -400,7 +400,7 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
-  * Schedule an IB in the DMA ring (VI).
-  */
- static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
--				   struct amdgpu_ib *ib)
-+				   struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	u32 vmid = ib->vm_id & 0xf;
- 	u32 next_rptr = ring->wptr + 5;
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index abd37a7..b9c2a49 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -489,7 +489,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
-  * Write ring commands to execute the indirect buffer
-  */
- static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
- 	amdgpu_ring_write(ring, ib->gpu_addr);
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 1c1a0e2..465b77c 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -539,7 +539,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
-  * Write ring commands to execute the indirect buffer
-  */
- static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
- 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index d015cb0..c2f790b 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -631,7 +631,7 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
-  * Write ring commands to execute the indirect buffer
-  */
- static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib)
-+				  struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
- 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index 9468c52..eed16c4 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -267,8 +267,7 @@ dm_dp_create_fake_mst_encoder(struct amdgpu_connector *connector)
- 		dev,
- 		&amdgpu_encoder->base,
- 		NULL,
--		DRM_MODE_ENCODER_DPMST,
--		NULL);
-+		DRM_MODE_ENCODER_DPMST);
- 
- 	drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 669b1ff..12fbb0b 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1526,7 +1526,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 		&dm_plane_funcs,
- 		rgb_formats,
- 		ARRAY_SIZE(rgb_formats),
--		DRM_PLANE_TYPE_PRIMARY, NULL);
-+		DRM_PLANE_TYPE_PRIMARY);
- 
- 	primary_plane->crtc = &acrtc->base;
- 
-@@ -1537,7 +1537,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
- 			&acrtc->base,
- 			primary_plane,
- 			NULL,
--			&amdgpu_dm_crtc_funcs, NULL);
-+			&amdgpu_dm_crtc_funcs);
- 
- 	if (res)
- 		goto fail;
-@@ -1955,8 +1955,7 @@ int amdgpu_dm_encoder_init(
- 	int res = drm_encoder_init(dev,
- 				   &aencoder->base,
- 				   &amdgpu_dm_encoder_funcs,
--				   DRM_MODE_ENCODER_TMDS,
--				   NULL);
-+				   DRM_MODE_ENCODER_TMDS);
- 
- 	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
- 
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index c16248c..3e21bfc 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -382,27 +382,28 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
- 
- /* init a sched_job with basic field */
- int amd_sched_job_init(struct amd_sched_job *job,
--						struct amd_gpu_scheduler *sched,
--						struct amd_sched_entity *entity,
--						void (*timeout_cb)(struct work_struct *work),
--						void (*free_cb)(struct kref *refcount),
--						void *owner, struct fence **fence)
-+                                                struct amd_gpu_scheduler *sched,
-+                                                struct amd_sched_entity *entity,
-+                                                void (*timeout_cb)(struct work_struct *work),
-+                                                void (*free_cb)(struct kref *refcount),
-+                                                void *owner, struct fence **fence)
- {
--	INIT_LIST_HEAD(&job->node);
--	kref_init(&job->refcount);
--	job->sched = sched;
--	job->s_entity = entity;
--	job->s_fence = amd_sched_fence_create(entity, owner);
--	if (!job->s_fence)
--		return -ENOMEM;
--
--	job->s_fence->s_job = job;
--	job->timeout_callback = timeout_cb;
--	job->free_callback = free_cb;
--
--	if (fence)
--		*fence = &job->s_fence->base;
--	return 0;
-+        INIT_LIST_HEAD(&job->node);
-+        kref_init(&job->refcount);
-+        job->sched = sched;
-+        job->s_entity = entity;
-+        job->fence_context = entity->fence_context;
-+        job->s_fence = amd_sched_fence_create(entity, owner);
-+        if (!job->s_fence)
-+                return -ENOMEM;
-+
-+        job->s_fence->s_job = job;
-+        job->timeout_callback = timeout_cb;
-+        job->free_callback = free_cb;
-+
-+        if (fence)
-+                *fence = &job->s_fence->base;
-+        return 0;
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index 070095a..c237e8d 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -87,6 +87,7 @@ struct amd_sched_job {
- 	struct work_struct             work_free_job;
- 	struct list_head			   node;
- 	struct delayed_work work_tdr;
-+	uint64_t                fence_context;
- 	void (*timeout_callback) (struct work_struct *work);
- 	void (*free_callback)(struct kref *refcount);
- };
-diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
-index ef53475..6b4cf25 100644
---- a/drivers/gpu/drm/drm_crtc_helper.c
-+++ b/drivers/gpu/drm/drm_crtc_helper.c
-@@ -818,7 +818,7 @@ EXPORT_SYMBOL(drm_helper_connector_dpms);
-  * metadata fields.
-  */
- void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
--				    struct drm_mode_fb_cmd2 *mode_cmd)
-+				    const struct drm_mode_fb_cmd2 *mode_cmd)
- {
- 	int i;
- 
-diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
-index fcd2a86..528d3a7 100644
---- a/drivers/gpu/drm/drm_pci.c
-+++ b/drivers/gpu/drm/drm_pci.c
-@@ -321,6 +321,26 @@ err_free:
- }
- EXPORT_SYMBOL(drm_get_pci_dev);
- 
-+int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw)
-+{
-+        struct pci_dev *root;
-+        u32 lnkcap;
-+
-+        *mlw = 0;
-+        if (!dev->pdev)
-+                return -EINVAL;
-+
-+        root = dev->pdev->bus->self;
-+
-+        pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
-+
-+        *mlw = (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
-+
-+        DRM_INFO("probing mlw for device %x:%x = %x\n", root->vendor, root->device, lnkcap);
-+        return 0;
-+}
-+EXPORT_SYMBOL(drm_pcie_get_max_link_width);
-+
- /**
-  * drm_pci_init - Register matching PCI devices with the DRM subsystem
-  * @driver: DRM device driver
-diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
-index 745e996..8d65957 100644
---- a/drivers/gpu/drm/ttm/ttm_bo.c
-+++ b/drivers/gpu/drm/ttm/ttm_bo.c
-@@ -228,6 +228,18 @@ void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo)
- }
- EXPORT_SYMBOL(ttm_bo_del_sub_from_lru);
- 
-+void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo)
-+{
-+        int put_count = 0;
-+
-+        lockdep_assert_held(&bo->resv->lock.base);
-+
-+        put_count = ttm_bo_del_from_lru(bo);
-+        ttm_bo_list_ref_sub(bo, put_count, true);
-+        ttm_bo_add_to_lru(bo);
-+}
-+EXPORT_SYMBOL(ttm_bo_move_to_lru_tail);
-+
- /*
-  * Call bo->mutex locked.
-  */
-diff --git a/include/drm/drmP.h b/include/drm/drmP.h
-index 0a271ca..1664f2b 100644
---- a/include/drm/drmP.h
-+++ b/include/drm/drmP.h
-@@ -1108,6 +1108,7 @@ static inline int drm_pci_set_busid(struct drm_device *dev,
- #define DRM_PCIE_SPEED_80 4
- 
- extern int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
-+extern int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw);
- 
- /* platform section */
- extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
-diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
-index 3f0c690..bd27364 100644
---- a/include/drm/drm_crtc.h
-+++ b/include/drm/drm_crtc.h
-@@ -992,7 +992,7 @@ struct drm_mode_set {
- struct drm_mode_config_funcs {
- 	struct drm_framebuffer *(*fb_create)(struct drm_device *dev,
- 					     struct drm_file *file_priv,
--					     struct drm_mode_fb_cmd2 *mode_cmd);
-+					     const struct drm_mode_fb_cmd2 *mode_cmd);
- 	void (*output_poll_changed)(struct drm_device *dev);
- 
- 	int (*atomic_check)(struct drm_device *dev,
-diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
-index 3febb4b..e22ab29 100644
---- a/include/drm/drm_crtc_helper.h
-+++ b/include/drm/drm_crtc_helper.h
-@@ -197,7 +197,7 @@ extern int drm_helper_connector_dpms(struct drm_connector *connector, int mode);
- extern void drm_helper_move_panel_connectors_to_head(struct drm_device *);
- 
- extern void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
--					   struct drm_mode_fb_cmd2 *mode_cmd);
-+					   const struct drm_mode_fb_cmd2 *mode_cmd);
- 
- static inline void drm_crtc_helper_add(struct drm_crtc *crtc,
- 				       const struct drm_crtc_helper_funcs *funcs)
-diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
-index c768ddf..afae231 100644
---- a/include/drm/ttm/ttm_bo_api.h
-+++ b/include/drm/ttm/ttm_bo_api.h
-@@ -383,6 +383,16 @@ extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
-  */
- extern int ttm_bo_del_from_lru(struct ttm_buffer_object *bo);
- 
-+/**
-+ * ttm_bo_move_to_lru_tail
-+ *
-+ * @bo: The buffer object.
-+ *
-+ * Move this BO to the tail of all lru lists used to lookup and reserve an
-+ * object. This function must be called with struct ttm_bo_global::lru_lock
-+ * held, and is used to make a BO less likely to be considered for eviction.
-+ */
-+extern void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_lock_delayed_workqueue
-diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
-index 813042c..d5f692c 100644
---- a/include/drm/ttm/ttm_bo_driver.h
-+++ b/include/drm/ttm/ttm_bo_driver.h
-@@ -434,6 +434,18 @@ struct ttm_bo_driver {
- 	 */
- 	int (*io_mem_reserve)(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem);
- 	void (*io_mem_free)(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem);
-+
-+	 /**
-+         * Optional driver callback for when BO is removed from the LRU.
-+         * Called with LRU lock held immediately before the removal.
-+         */
-+        void (*lru_removal)(struct ttm_buffer_object *bo);
-+
-+        /**
-+         * Return the list_head after which a BO should be inserted in the LRU.
-+         */
-+        struct list_head *(*lru_tail)(struct ttm_buffer_object *bo);
-+        struct list_head *(*swap_lru_tail)(struct ttm_buffer_object *bo);
- };
- 
- /**
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1080-drm-amdgpu-fix-num_rbs-exposed-to-userspace.patch b/common/recipes-kernel/linux/files/1080-drm-amdgpu-fix-num_rbs-exposed-to-userspace.patch
deleted file mode 100644
index 0cf9183d..00000000
--- a/common/recipes-kernel/linux/files/1080-drm-amdgpu-fix-num_rbs-exposed-to-userspace.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From a164a184ca5d1a626f97706520a6eaed8c4a9cea Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 20 Jun 2016 15:25:05 +0530
-Subject: [PATCH 1080/1110] drm/amdgpu: fix num_rbs exposed to userspace
-
-This was accidently broken for harvest cards when the
-code was refactored for Polaris support.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index 7db2712..2e82537 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -448,7 +448,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- 			dev_info.max_memory_clock = adev->pm.default_mclk * 10;
- 		}
- 		dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
--		dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
-+                dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se;
- 		dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
- 		dev_info._pad = 0;
- 		dev_info.ids_flags = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1081-drm-amd-amdgpu-make-sure-VCE-is-disabled-by-default.patch b/common/recipes-kernel/linux/files/1081-drm-amd-amdgpu-make-sure-VCE-is-disabled-by-default.patch
deleted file mode 100644
index b01d3dbc..00000000
--- a/common/recipes-kernel/linux/files/1081-drm-amd-amdgpu-make-sure-VCE-is-disabled-by-default.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From c9b3aef7b291b7f2a475c4094ac8432986512e80 Mon Sep 17 00:00:00 2001
-From: Arindam Nath <arindam.nath@amd.com>
-Date: Mon, 20 Jun 2016 14:17:49 +0530
-Subject: [PATCH 1081/1110] drm/amd/amdgpu: make sure VCE is disabled by
- default
-
-With the current code, when we boot with the amdgpu
-driver enabled and loaded, the VCE also automatically
-remains enabled since bootup. This can be verified from
-the output of amdgpu_pm_info. It does not matter whether
-we boot into command line directly or into X, the VCE
-stays enabled the entire time.
-
-This patch addresses the issue and makes sure that
-VCE is turned on only during playback, and remains
-disaled otherwise.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Arindam Nath <arindam.nath@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index bf1847b..b115810 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -2224,6 +2224,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
- 			}
- 		}
- 	} else { /*pi->caps_vce_pg*/
-+		pi->vce_power_gated = gate;
- 		cz_update_vce_dpm(adev);
- 		cz_enable_vce_dpm(adev, !gate);
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1082-drm-amd-powerplay-make-sure-VCE-is-disabled-by-defau.patch b/common/recipes-kernel/linux/files/1082-drm-amd-powerplay-make-sure-VCE-is-disabled-by-defau.patch
deleted file mode 100644
index c59e3228..00000000
--- a/common/recipes-kernel/linux/files/1082-drm-amd-powerplay-make-sure-VCE-is-disabled-by-defau.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 298fb4f5972829efa5f352a6e85a77b13d045d34 Mon Sep 17 00:00:00 2001
-From: Arindam Nath <arindam.nath@amd.com>
-Date: Mon, 20 Jun 2016 16:05:01 +0530
-Subject: [PATCH 1082/1110] drm/amd/powerplay: make sure VCE is disabled by
- default
-
-This patch is a port of similar patch for amdgpu
-when PP is disabled. Since the code flow is little
-different when PP is enabled, we need to make sure
-the patch is applied for PP enabled path as well.
-
-With the current code, when we boot with the amdgpu
-driver enabled and loaded, the VCE also automatically
-remains enabled since bootup. This can be verified from
-the output of amdgpu_pm_info. It does not matter whether
-we boot into command line directly or into X, the VCE
-stays enabled the entire time.
-
-This patch addresses the issue and makes sure that
-VCE is turned on only during playback, and remains
-disaled otherwise.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Arindam Nath <arindam.nath@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-index 436fc16..17b94bc 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
-@@ -225,6 +225,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- 			}
- 		}
- 	} else {
-+		cz_hwmgr->vce_power_gated = bgate;
- 		cz_dpm_update_vce_dpm(hwmgr);
- 		cz_enable_disable_vce_dpm(hwmgr, !bgate);
- 		return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1083-1083-drm-amd-dal-remove-common-modes.patch.patch b/common/recipes-kernel/linux/files/1083-1083-drm-amd-dal-remove-common-modes.patch.patch
deleted file mode 100644
index d960bee2..00000000
--- a/common/recipes-kernel/linux/files/1083-1083-drm-amd-dal-remove-common-modes.patch.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From ded02745a454a75a08b5cbede401ea7f03d1722f Mon Sep 17 00:00:00 2001
-From: "Ramin.Ranjbar" <Ramin.Ranjbar@amd.com>
-Date: Thu, 7 Jul 2016 17:26:22 +0530
-Subject: [PATCH 1083/1110] 1083-drm-amd-dal-remove-common-modes.patch
-
-Signed-off-by: Ramin Ranjbar <Ramin.Ranjbar@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c    | 84 +---------------------
- 1 file changed, 1 insertion(+), 83 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 12fbb0b..390c9b0 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -1614,88 +1614,6 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
- 	}
- }
- 
--static struct drm_display_mode *amdgpu_dm_create_common_mode(
--		struct drm_encoder *encoder, char *name,
--		int hdisplay, int vdisplay)
--{
--	struct drm_device *dev = encoder->dev;
--	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
--	struct drm_display_mode *mode = NULL;
--	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
--
--	mode = drm_mode_duplicate(dev, native_mode);
--
--	if(mode == NULL)
--		return NULL;
--
--	mode->hdisplay = hdisplay;
--	mode->vdisplay = vdisplay;
--	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
--	strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
--
--	return mode;
--
--}
--
--static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
--					struct drm_connector *connector)
--{
--	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
--	struct drm_display_mode *mode = NULL;
--	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
--	struct amdgpu_connector *amdgpu_connector =
--				to_amdgpu_connector(connector);
--	int i;
--	int n;
--	struct mode_size {
--		char name[DRM_DISPLAY_MODE_LEN];
--		int w;
--		int h;
--	}common_modes[] = {
--		{  "640x480",  640,  480},
--		{  "800x600",  800,  600},
--		{ "1024x768", 1024,  768},
--		{ "1280x720", 1280,  720},
--		{ "1280x800", 1280,  800},
--		{"1280x1024", 1280, 1024},
--		{ "1440x900", 1440,  900},
--		{"1680x1050", 1680, 1050},
--		{"1600x1200", 1600, 1200},
--		{"1920x1080", 1920, 1080},
--		{"1920x1200", 1920, 1200}
--	};
--
--	n = sizeof(common_modes) / sizeof(common_modes[0]);
--
--	for (i = 0; i < n; i++) {
--		struct drm_display_mode *curmode = NULL;
--		bool mode_existed = false;
--
--		if (common_modes[i].w > native_mode->hdisplay ||
--			common_modes[i].h > native_mode->vdisplay ||
--			(common_modes[i].w == native_mode->hdisplay &&
--			common_modes[i].h == native_mode->vdisplay))
--				continue;
--
--		list_for_each_entry(curmode, &connector->probed_modes, head) {
--			if (common_modes[i].w == curmode->hdisplay &&
--				common_modes[i].h == curmode->vdisplay) {
--				mode_existed = true;
--				break;
--			}
--		}
--
--		if (mode_existed)
--			continue;
--
--		mode = amdgpu_dm_create_common_mode(encoder,
--				common_modes[i].name, common_modes[i].w,
--				common_modes[i].h);
--		drm_mode_probed_add(connector, mode);
--		amdgpu_connector->num_modes++;
--	}
--}
--
- static void amdgpu_dm_connector_ddc_get_modes(
- 	struct drm_connector *connector,
- 	struct edid *edid)
-@@ -1728,7 +1646,7 @@ int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
- 	encoder = helper->best_encoder(connector);
- 
- 	amdgpu_dm_connector_ddc_get_modes(connector, edid);
--	amdgpu_dm_connector_add_common_modes(encoder, connector);
-+	//amdgpu_dm_connector_add_common_modes(encoder, connector);
- 	return amdgpu_connector->num_modes;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch b/common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch
deleted file mode 100644
index f937fa7e..00000000
--- a/common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From ec6230410b55c2f2aae42b8c7e693653b71af6c2 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 1 Jul 2016 15:49:29 +0530
-Subject: [PATCH 1084/1110] drm/amdgpu/gfx8: add state setup for CZ/ST GFX
- power gating
-
-This sets up the CP jump table and GDS buffer and sets the
-PG state registers.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   4 +
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 159 ++++++++++++++++++++++++++++++++++
- 2 files changed, 163 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 0f7de1b..8127e81 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -131,6 +131,10 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define AMDGPU_RESET_VCE			(1 << 13)
- #define AMDGPU_RESET_VCE1			(1 << 14)
- 
-+#define AMDGPU_PG_SUPPORT_GFX_PG                (1 << 0)
-+#define AMDGPU_PG_SUPPORT_GFX_SMG               (1 << 1)
-+#define AMDGPU_PG_SUPPORT_GFX_DMG               (1 << 2)
-+
- /* GFX current status */
- #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
- #define AMDGPU_GFX_SAFE_MODE			0x00000001L
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d35fa43..951381c 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -29,6 +29,7 @@
- #include "amdgpu_ucode.h"
- #include "amdgpu_atombios.h"
- #include "clearstate_vi.h"
-+#include "gfx_v8_0.h"
- 
- #include "gmc/gmc_8_2_d.h"
- #include "gmc/gmc_8_2_sh_mask.h"
-@@ -1126,6 +1127,71 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
- 	buffer[count++] = cpu_to_le32(0);
- }
- 
-+static void cz_init_cp_jump_table(struct amdgpu_device *adev)
-+{
-+	const __le32 *fw_data;
-+	volatile u32 *dst_ptr;
-+	int me, i, max_me = 4;
-+	u32 bo_offset = 0;
-+	u32 table_offset, table_size;
-+
-+	if (adev->asic_type == CHIP_CARRIZO)
-+		max_me = 5;
-+
-+	/* write the cp table buffer */
-+	dst_ptr = adev->gfx.rlc.cp_table_ptr;
-+	for (me = 0; me < max_me; me++) {
-+		if (me == 0) {
-+			const struct gfx_firmware_header_v1_0 *hdr =
-+				(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
-+			fw_data = (const __le32 *)
-+				(adev->gfx.ce_fw->data +
-+				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-+			table_offset = le32_to_cpu(hdr->jt_offset);
-+			table_size = le32_to_cpu(hdr->jt_size);
-+		} else if (me == 1) {
-+			const struct gfx_firmware_header_v1_0 *hdr =
-+				(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
-+			fw_data = (const __le32 *)
-+				(adev->gfx.pfp_fw->data +
-+				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-+			table_offset = le32_to_cpu(hdr->jt_offset);
-+			table_size = le32_to_cpu(hdr->jt_size);
-+		} else if (me == 2) {
-+			const struct gfx_firmware_header_v1_0 *hdr =
-+				(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
-+			fw_data = (const __le32 *)
-+				(adev->gfx.me_fw->data +
-+				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-+			table_offset = le32_to_cpu(hdr->jt_offset);
-+			table_size = le32_to_cpu(hdr->jt_size);
-+		} else if (me == 3) {
-+			const struct gfx_firmware_header_v1_0 *hdr =
-+				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
-+			fw_data = (const __le32 *)
-+				(adev->gfx.mec_fw->data +
-+				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-+			table_offset = le32_to_cpu(hdr->jt_offset);
-+			table_size = le32_to_cpu(hdr->jt_size);
-+		} else  if (me == 4) {
-+			const struct gfx_firmware_header_v1_0 *hdr =
-+				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
-+			fw_data = (const __le32 *)
-+				(adev->gfx.mec2_fw->data +
-+				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-+			table_offset = le32_to_cpu(hdr->jt_offset);
-+			table_size = le32_to_cpu(hdr->jt_size);
-+		}
-+
-+		for (i = 0; i < table_size; i ++) {
-+			dst_ptr[bo_offset + i] =
-+				cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
-+		}
-+
-+		bo_offset += table_size;
-+	}
-+}
-+
- static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
- {
- 	int r;
-@@ -1141,6 +1207,18 @@ static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
- 		amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
- 		adev->gfx.rlc.clear_state_obj = NULL;
- 	}
-+
-+	/* jump table block */
-+	if (adev->gfx.rlc.cp_table_obj) {
-+		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
-+		if (unlikely(r != 0))
-+			dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
-+		amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
-+		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
-+
-+		amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
-+		adev->gfx.rlc.cp_table_obj = NULL;
-+	}
- }
- 
- static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
-@@ -1197,6 +1275,45 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
- 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
- 	}
- 
-+	if ((adev->asic_type == CHIP_CARRIZO) ||
-+	    (adev->asic_type == CHIP_STONEY)) {
-+		adev->gfx.rlc.cp_table_size = (96 * 5 * 4) + (64 * 1024); /* JT + GDS */
-+		if (adev->gfx.rlc.cp_table_obj == NULL) {
-+			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
-+					     AMDGPU_GEM_DOMAIN_VRAM,
-+					     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
-+					     NULL, NULL,
-+					     &adev->gfx.rlc.cp_table_obj);
-+			if (r) {
-+				dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
-+				return r;
-+			}
-+		}
-+
-+		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
-+		if (unlikely(r != 0)) {
-+			dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
-+			return r;
-+		}
-+		r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
-+				  &adev->gfx.rlc.cp_table_gpu_addr);
-+		if (r) {
-+			amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
-+			dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
-+			return r;
-+		}
-+		r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
-+		if (r) {
-+			dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
-+			return r;
-+		}
-+
-+		cz_init_cp_jump_table(adev);
-+
-+		amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
-+		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
-+	}
-+
- 	return 0;
- }
- 
-@@ -3658,6 +3775,37 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
- 	WREG32(mmRLC_SRM_CNTL, data);
- }
- 
-+static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
-+{
-+        uint32_t data;
-+ 
-+        if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
-+                              AMDGPU_PG_SUPPORT_GFX_SMG |
-+                              AMDGPU_PG_SUPPORT_GFX_DMG)) {
-+                data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
-+                data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
-+                data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
-+                WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
-+ 
-+                data = 0;
-+                data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
-+                data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
-+                data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
-+                data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
-+                WREG32(mmRLC_PG_DELAY, data);
-+ 
-+                data = RREG32(mmRLC_PG_DELAY_2);
-+                data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
-+                data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
-+                WREG32(mmRLC_PG_DELAY_2, data);
-+ 
-+                data = RREG32(mmRLC_AUTO_PG_CTRL);
-+                data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
-+                data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
-+                WREG32(mmRLC_AUTO_PG_CTRL, data);
-+        }
-+ }
-+
- static void polaris11_init_power_gating(struct amdgpu_device *adev)
- {
- 	uint32_t data;
-@@ -3700,6 +3848,17 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
- 		gfx_v8_0_init_csb(adev);
- 		gfx_v8_0_init_save_restore_list(adev);
- 		gfx_v8_0_enable_save_restore_machine(adev);
-+ 
-+                if ((adev->asic_type == CHIP_CARRIZO) ||
-+                    (adev->asic_type == CHIP_STONEY)) {
-+                        struct amdgpu_cu_info cu_info;
-+ 
-+                        gfx_v8_0_get_cu_info(adev, &cu_info);
-+ 
-+                        WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-+                        gfx_v8_0_init_power_gating(adev);
-+                        WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask);
-+                }
- 
- 		if (adev->asic_type == CHIP_POLARIS11)
- 			polaris11_init_power_gating(adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1085-drm-amdgpu-gfx8-add-powergating-support-for-CZ-ST.patch b/common/recipes-kernel/linux/files/1085-drm-amdgpu-gfx8-add-powergating-support-for-CZ-ST.patch
deleted file mode 100644
index 8f02ee83..00000000
--- a/common/recipes-kernel/linux/files/1085-drm-amdgpu-gfx8-add-powergating-support-for-CZ-ST.patch
+++ /dev/null
@@ -1,357 +0,0 @@
-From de44dc45fda1f3399c6b20646221fe6fdab5b672 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Fri, 8 Jul 2016 12:49:13 +0530
-Subject: [PATCH 1085/1110] drm/amdgpu/gfx8: add powergating support for CZ/ST
-
-This implements powergating support for CZ/ST asics.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Acked-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 266 +++++++++++++++++++++++-----------
- 2 files changed, 190 insertions(+), 81 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 8127e81..3a3815c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -131,9 +131,14 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define AMDGPU_RESET_VCE			(1 << 13)
- #define AMDGPU_RESET_VCE1			(1 << 14)
- 
-+#define AMDGPU_PG_SUPPORT_GFX_QUICK_MG         (1 << 11)
-+#define AMDGPU_PG_SUPPORT_GFX_PIPELINE         (1 << 12)
-+
- #define AMDGPU_PG_SUPPORT_GFX_PG                (1 << 0)
- #define AMDGPU_PG_SUPPORT_GFX_SMG               (1 << 1)
- #define AMDGPU_PG_SUPPORT_GFX_DMG               (1 << 2)
-+#define AMDGPU_PG_SUPPORT_CP                    (1 << 5)
-+#define AMDGPU_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
- 
- /* GFX current status */
- #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 951381c..5705436 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -834,6 +834,25 @@ err1:
- 	return r;
- }
- 
-+static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) {
-+	release_firmware(adev->gfx.pfp_fw);
-+	adev->gfx.pfp_fw = NULL;
-+	release_firmware(adev->gfx.me_fw);
-+	adev->gfx.me_fw = NULL;
-+	release_firmware(adev->gfx.ce_fw);
-+	adev->gfx.ce_fw = NULL;
-+	release_firmware(adev->gfx.rlc_fw);
-+	adev->gfx.rlc_fw = NULL;
-+	release_firmware(adev->gfx.mec_fw);
-+	adev->gfx.mec_fw = NULL;
-+	if ((adev->asic_type != CHIP_STONEY) &&
-+	    (adev->asic_type != CHIP_TOPAZ))
-+		release_firmware(adev->gfx.mec2_fw);
-+	adev->gfx.mec2_fw = NULL;
-+
-+	kfree(adev->gfx.rlc.register_list_format);
-+}
-+
- static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
- {
- 	const char *chip_name;
-@@ -2097,7 +2116,7 @@ static int gfx_v8_0_sw_fini(void *handle)
- 
- 	gfx_v8_0_rlc_fini(adev);
- 
--	kfree(adev->gfx.rlc.register_list_format);
-+	gfx_v8_0_free_microcode(adev);
- 
- 	return 0;
- }
-@@ -3806,6 +3825,53 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
-         }
-  }
- 
-+static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
-+                                               bool enable)
-+{
-+        u32 data, orig;
-+ 
-+        orig = data = RREG32(mmRLC_PG_CNTL);
-+ 
-+        if (enable)
-+                data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
-+        else
-+                data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
-+ 
-+        if (orig != data)
-+                WREG32(mmRLC_PG_CNTL, data);
-+}
-+
-+static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
-+                                                 bool enable)
-+{
-+        u32 data, orig;
-+ 
-+        orig = data = RREG32(mmRLC_PG_CNTL);
-+ 
-+        if (enable)
-+                data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-+        else
-+                data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-+ 
-+        if (orig != data)
-+                WREG32(mmRLC_PG_CNTL, data);
-+}
-+
-+static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
-+{
-+        u32 data, orig;
-+ 
-+        orig = data = RREG32(mmRLC_PG_CNTL);
-+ 
-+        if (enable)
-+                data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
-+        else
-+                data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
-+ 
-+        if (orig != data)
-+                WREG32(mmRLC_PG_CNTL, data);
-+ }
-+
- static void polaris11_init_power_gating(struct amdgpu_device *adev)
- {
- 	uint32_t data;
-@@ -3858,10 +3924,20 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
-                         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-                         gfx_v8_0_init_power_gating(adev);
-                         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask);
--                }
--
--		if (adev->asic_type == CHIP_POLARIS11)
-+ 			if (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS) {
-+                                cz_enable_sck_slow_down_on_power_up(adev, true);
-+                                cz_enable_sck_slow_down_on_power_down(adev, true);
-+                        } else {
-+                                cz_enable_sck_slow_down_on_power_up(adev, false);
-+                                cz_enable_sck_slow_down_on_power_down(adev, false);
-+                        }
-+                        if (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)
-+                                cz_enable_cp_power_gating(adev, true);
-+                        else
-+                                cz_enable_cp_power_gating(adev, false);
-+                } else if (adev->asic_type == CHIP_POLARIS11) {
- 			polaris11_init_power_gating(adev);
-+		}
- 	}
- }
- 
-@@ -5194,97 +5270,125 @@ static int gfx_v8_0_late_init(void *handle)
- 	return 0;
- }
- 
--static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
--		bool enable)
-+static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
-+                                                       bool enable)
- {
--	uint32_t data, temp;
--
--	/* Send msg to SMU via Powerplay */
--	amdgpu_set_powergating_state(adev,
--			AMD_IP_BLOCK_TYPE_SMC,
--			enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
--
--	if (enable) {
--		/* Enable static MGPG */
--		temp = data = RREG32(mmRLC_PG_CNTL);
--		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
--
--		if (temp != data)
--			WREG32(mmRLC_PG_CNTL, data);
--	} else {
--		temp = data = RREG32(mmRLC_PG_CNTL);
--		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
--
--		if (temp != data)
--			WREG32(mmRLC_PG_CNTL, data);
--	}
-+         uint32_t data, temp;
-+ 
-+         if (enable) {
-+                 /* Enable static MGPG */
-+                 temp = data = RREG32(mmRLC_PG_CNTL);
-+                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+ 
-+                 if (temp != data)
-+                         WREG32(mmRLC_PG_CNTL, data);
-+         } else {
-+                 temp = data = RREG32(mmRLC_PG_CNTL);
-+                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+ 
-+                 if (temp != data)
-+                         WREG32(mmRLC_PG_CNTL, data);
-+         }
- }
- 
--static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
--		bool enable)
-+static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
-+                                                        bool enable)
- {
--	uint32_t data, temp;
--
--	if (enable) {
--		/* Enable dynamic MGPG */
--		temp = data = RREG32(mmRLC_PG_CNTL);
--		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
--
--		if (temp != data)
--			WREG32(mmRLC_PG_CNTL, data);
--	} else {
--		temp = data = RREG32(mmRLC_PG_CNTL);
--		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
--
--		if (temp != data)
--			WREG32(mmRLC_PG_CNTL, data);
--	}
-+         uint32_t data, temp;
-+ 
-+         if (enable) {
-+                 /* Enable dynamic MGPG */
-+                 temp = data = RREG32(mmRLC_PG_CNTL);
-+                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+ 
-+                 if (temp != data)
-+                         WREG32(mmRLC_PG_CNTL, data);
-+         } else {
-+                 temp = data = RREG32(mmRLC_PG_CNTL);
-+                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+ 
-+                 if (temp != data)
-+                         WREG32(mmRLC_PG_CNTL, data);
-+         }
- }
- 
--static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
--		bool enable)
-+static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
-+                                         bool enable)
- {
--	uint32_t data, temp;
--
--	if (enable) {
--		/* Enable quick PG */
--		temp = data = RREG32(mmRLC_PG_CNTL);
--		data |= 0x100000;
-+       u32 data, orig;
-+ 
-+        orig = data = RREG32(mmRLC_PG_CNTL);
-+ 
-+        if (enable)
-+                data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
-+        else
-+                data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
-+ 
-+        if (orig != data)
-+                WREG32(mmRLC_PG_CNTL, data);
-+}
- 
--		if (temp != data)
--			WREG32(mmRLC_PG_CNTL, data);
--	} else {
--		temp = data = RREG32(mmRLC_PG_CNTL);
--		data &= ~0x100000;
-+static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
-+                                               bool enable)
-+{
-+       u32 data, orig;
-+ 
-+        orig = data = RREG32(mmRLC_PG_CNTL);
-+ 
-+        if (enable)
-+                data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-+        else
-+                data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-+ 
-+        if (orig != data)
-+                WREG32(mmRLC_PG_CNTL, data);
-+ 
-+        /* Read any GFX register to wake up GFX. */
-+        if (!enable)
-+                data = RREG32(mmDB_RENDER_CONTROL);
-+}
- 
--		if (temp != data)
--			WREG32(mmRLC_PG_CNTL, data);
--	}
-+static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
-+                                         bool enable)
-+{
-+       if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) && enable) {
-+                cz_enable_gfx_cg_power_gating(adev, true);
-+                if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PIPELINE)
-+                        cz_enable_gfx_pipeline_power_gating(adev, true);
-+        } else {
-+                cz_enable_gfx_cg_power_gating(adev, false);
-+                cz_enable_gfx_pipeline_power_gating(adev, false);
-+        }
- }
- 
- static int gfx_v8_0_set_powergating_state(void *handle,
- 					  enum amd_powergating_state state)
- {
--	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
--	if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
--		return 0;
--
--	switch (adev->asic_type) {
--	case CHIP_POLARIS11:
--		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)
--			polaris11_enable_gfx_static_mg_power_gating(adev,
--					state == AMD_PG_STATE_GATE ? true : false);
--		else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)
--			polaris11_enable_gfx_dynamic_mg_power_gating(adev,
--					state == AMD_PG_STATE_GATE ? true : false);
--		else
--			polaris11_enable_gfx_quick_mg_power_gating(adev,
--					state == AMD_PG_STATE_GATE ? true : false);
--		break;
--	default:
--		break;
--	}
-+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+        bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
-+ 
-+        if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG))
-+                return 0;
-+ 
-+        switch (adev->asic_type) {
-+        case CHIP_CARRIZO:
-+        case CHIP_STONEY:
-+                if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)
-+                        cz_update_gfx_cg_power_gating(adev, enable);
-+ 
-+                if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) && enable)
-+                        gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
-+                else
-+                        gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
-+ 
-+                if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG) && enable)
-+                       gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
-+                else
-+                       gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
-+                break;
-+        default:
-+                break;
-+        }
- 
- 	return 0;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1086-drm-amdgpu-gfx8-Add-serdes-wait-for-idle-in-CGCG-en-.patch b/common/recipes-kernel/linux/files/1086-drm-amdgpu-gfx8-Add-serdes-wait-for-idle-in-CGCG-en-.patch
deleted file mode 100644
index d63d01b5..00000000
--- a/common/recipes-kernel/linux/files/1086-drm-amdgpu-gfx8-Add-serdes-wait-for-idle-in-CGCG-en-.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 31094e633b777b26e3c09c2a313ea22c331c6d3d Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Sat, 2 Jul 2016 00:38:29 +0530
-Subject: [PATCH 1086/1110] drm/amdgpu/gfx8: Add serdes wait for idle in CGCG
- en/disable
-
-Must wait for SERDES idle before exiting RLC SAFEMODE
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 5705436..258bb1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -5697,6 +5697,8 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
- 		gfx_v8_0_wait_for_rlc_serdes(adev);
- 	}
- 
-+	gfx_v8_0_wait_for_rlc_serdes(adev);
-+
- 	adev->gfx.rlc.funcs->exit_safe_mode(adev);
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1087-drm-amdgpu-gfx8-fix-CP-jump-table-size.patch b/common/recipes-kernel/linux/files/1087-drm-amdgpu-gfx8-fix-CP-jump-table-size.patch
deleted file mode 100644
index edf8f3c4..00000000
--- a/common/recipes-kernel/linux/files/1087-drm-amdgpu-gfx8-fix-CP-jump-table-size.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From c326bd3f43db83dce3503fa6d80e502a56071151 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Sat, 2 Jul 2016 00:46:04 +0530
-Subject: [PATCH 1087/1110] drm/amdgpu/gfx8: fix CP jump table size
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Align to the jump table offset. Fixes hangs on some
-systems with GFX PG enabled.
-
-Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
-Tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
-Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 258bb1b..91e98fa 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1296,7 +1296,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
- 
- 	if ((adev->asic_type == CHIP_CARRIZO) ||
- 	    (adev->asic_type == CHIP_STONEY)) {
--		adev->gfx.rlc.cp_table_size = (96 * 5 * 4) + (64 * 1024); /* JT + GDS */
-+                adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
- 		if (adev->gfx.rlc.cp_table_obj == NULL) {
- 			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
- 					     AMDGPU_GEM_DOMAIN_VRAM,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1088-drm-amdgpu-gfx8-Enable-GFX-PG-on-CZ.patch b/common/recipes-kernel/linux/files/1088-drm-amdgpu-gfx8-Enable-GFX-PG-on-CZ.patch
deleted file mode 100644
index c69b74ec..00000000
--- a/common/recipes-kernel/linux/files/1088-drm-amdgpu-gfx8-Enable-GFX-PG-on-CZ.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From a5fc2102ff5429bbd01200e5e27c59233e8171d4 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Sat, 2 Jul 2016 00:52:32 +0530
-Subject: [PATCH 1088/1110] drm/amdgpu/gfx8: Enable GFX PG on CZ
-
-Based on Alex's patches this enables GFX PG on CZ.
-
-Tested with xonotic-glx/glxgears/supertuxkart and idle desktop.
-Also read-back registers via umr for verificiation that the bits
-are truly enabled.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index cc5ebd3..16070de 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1537,7 +1537,15 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_HDP_LS |
- 			AMD_CG_SUPPORT_SDMA_MGCG |
- 			AMD_CG_SUPPORT_SDMA_LS;
--		adev->pg_flags = 0;
-+               /* rev0 hardware doesn't support PG */
-+               if (adev->rev_id != 0x00)
-+                       adev->pg_flags |= AMDGPU_PG_SUPPORT_GFX_PG |
-+                                         AMDGPU_PG_SUPPORT_GFX_SMG |
-+                                         AMDGPU_PG_SUPPORT_GFX_DMG |
-+                                         AMDGPU_PG_SUPPORT_CP |
-+                                         AMDGPU_PG_SUPPORT_RLC_SMU_HS |
-+                                         AMDGPU_PG_SUPPORT_GFX_PIPELINE;
-+
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
- 	case CHIP_STONEY:
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1089-drm-amd-amdgpu-Add-name-field-to-amd_ip_funcs.patch b/common/recipes-kernel/linux/files/1089-drm-amd-amdgpu-Add-name-field-to-amd_ip_funcs.patch
deleted file mode 100644
index bb629f36..00000000
--- a/common/recipes-kernel/linux/files/1089-drm-amd-amdgpu-Add-name-field-to-amd_ip_funcs.patch
+++ /dev/null
@@ -1,448 +0,0 @@
-From 96f8a4bc347648bb22819b9d2d0340c8354c5eb4 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Wed, 4 May 2016 14:28:35 -0400
-Subject: [PATCH 1089/1110] drm/amd/amdgpu: Add name field to amd_ip_funcs
-
-Add name that we can print out in kernel messages
-to aid in debugging.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c       | 1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
- drivers/gpu/drm/amd/amdgpu/ci_dpm.c           | 1 +
- drivers/gpu/drm/amd/amdgpu/cik.c              | 1 +
- drivers/gpu/drm/amd/amdgpu/cik_ih.c           | 1 +
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/cz_dpm.c           | 1 +
- drivers/gpu/drm/amd/amdgpu/cz_ih.c            | 1 +
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c        | 1 +
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c        | 1 +
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/fiji_dpm.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/iceland_dpm.c      | 1 +
- drivers/gpu/drm/amd/amdgpu/iceland_ih.c       | 1 +
- drivers/gpu/drm/amd/amdgpu/kv_dpm.c           | 1 +
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c        | 1 +
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c        | 1 +
- drivers/gpu/drm/amd/amdgpu/tonga_dpm.c        | 1 +
- drivers/gpu/drm/amd/amdgpu/tonga_ih.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c         | 1 +
- drivers/gpu/drm/amd/amdgpu/vi.c               | 1 +
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 1 +
- drivers/gpu/drm/amd/include/amd_shared.h      | 2 ++
- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 1 +
- 33 files changed, 34 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-index 49838df..252edba 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -480,6 +480,7 @@ static int acp_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs acp_ip_funcs = {
-+	.name = "acp_ip",
- 	.early_init = acp_early_init,
- 	.late_init = NULL,
- 	.sw_init = acp_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 58a4faa..f63fe24 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1196,7 +1196,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
- 				if (r == -ENOENT) {
- 					adev->ip_block_status[i].valid = false;
- 				} else if (r) {
--					DRM_ERROR("early_init %d failed %d\n", i, r);
-+					DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 					return r;
- 				} else {
- 					adev->ip_block_status[i].valid = true;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 86cdede..1540359 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -302,6 +302,7 @@ static int amdgpu_pp_soft_reset(void *handle)
- }
- 
- const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
-+	.name = "amdgpu_powerplay",
- 	.early_init = amdgpu_pp_early_init,
- 	.late_init = amdgpu_pp_late_init,
- 	.sw_init = amdgpu_pp_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-index 2f24797..ca8e278 100644
---- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
-@@ -6405,6 +6405,7 @@ static int ci_dpm_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs ci_dpm_ip_funcs = {
-+	.name = "ci_dpm",
- 	.early_init = ci_dpm_early_init,
- 	.late_init = ci_dpm_late_init,
- 	.sw_init = ci_dpm_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index e86afec..cc5b943 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -2394,6 +2394,7 @@ static int cik_common_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs cik_common_ip_funcs = {
-+	.name = "cik_common",
- 	.early_init = cik_common_early_init,
- 	.late_init = NULL,
- 	.sw_init = cik_common_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-index 7e750a4..845c21b 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
-@@ -415,6 +415,7 @@ static int cik_ih_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs cik_ih_ip_funcs = {
-+	.name = "cik_ih",
- 	.early_init = cik_ih_early_init,
- 	.late_init = NULL,
- 	.sw_init = cik_ih_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 48505c9..223212f 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -1223,6 +1223,7 @@ static int cik_sdma_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs cik_sdma_ip_funcs = {
-+	.name = "cik_sdma",
- 	.early_init = cik_sdma_early_init,
- 	.late_init = NULL,
- 	.sw_init = cik_sdma_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-index b115810..f3f2922 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
-@@ -2231,6 +2231,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
- }
- 
- const struct amd_ip_funcs cz_dpm_ip_funcs = {
-+	.name = "cz_dpm",
- 	.early_init = cz_dpm_early_init,
- 	.late_init = cz_dpm_late_init,
- 	.sw_init = cz_dpm_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-index 874b928..863cb16 100644
---- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
-@@ -396,6 +396,7 @@ static int cz_ih_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs cz_ih_ip_funcs = {
-+	.name = "cz_ih",
- 	.early_init = cz_ih_early_init,
- 	.late_init = NULL,
- 	.sw_init = cz_ih_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 8f27dd5..9454381 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -3490,6 +3490,7 @@ static int dce_v10_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs dce_v10_0_ip_funcs = {
-+	.name = "dce_v10_0",
- 	.early_init = dce_v10_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = dce_v10_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index b95abde..c3117c4 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -3553,6 +3553,7 @@ static int dce_v11_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs dce_v11_0_ip_funcs = {
-+	.name = "dce_v11_0",
- 	.early_init = dce_v11_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = dce_v11_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 2626c7e..6c496ab 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -3420,6 +3420,7 @@ static int dce_v8_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs dce_v8_0_ip_funcs = {
-+	.name = "dce_v8_0",
- 	.early_init = dce_v8_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = dce_v8_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-index 6d13345..245cabf 100644
---- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
-@@ -143,6 +143,7 @@ static int fiji_dpm_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs fiji_dpm_ip_funcs = {
-+	.name = "fiji_dpm",
- 	.early_init = fiji_dpm_early_init,
- 	.late_init = NULL,
- 	.sw_init = fiji_dpm_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index ea19760..b449a40 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -4897,6 +4897,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
-+	.name = "gfx_v7_0",
- 	.early_init = gfx_v7_0_early_init,
- 	.late_init = gfx_v7_0_late_init,
- 	.sw_init = gfx_v7_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 91e98fa..3d1a5ee 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -6328,6 +6328,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
- }
- 
- const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
-+	.name = "gfx_v8_0",
- 	.early_init = gfx_v8_0_early_init,
- 	.late_init = gfx_v8_0_late_init,
- 	.sw_init = gfx_v8_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index b7a96db..52e1b06 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -1260,6 +1260,7 @@ static int gmc_v7_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
-+	.name = "gmc_v7_0",
- 	.early_init = gmc_v7_0_early_init,
- 	.late_init = gmc_v7_0_late_init,
- 	.sw_init = gmc_v7_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 4abcf0d..a4b01fb 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -1423,6 +1423,7 @@ static int gmc_v8_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
-+	.name = "gmc_v8_0",
- 	.early_init = gmc_v8_0_early_init,
- 	.late_init = gmc_v8_0_late_init,
- 	.sw_init = gmc_v8_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
-index 57a9613..460bc8a 100644
---- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
-@@ -157,6 +157,7 @@ static int iceland_dpm_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs iceland_dpm_ip_funcs = {
-+	.name = "iceland_dpm",
- 	.early_init = iceland_dpm_early_init,
- 	.late_init = NULL,
- 	.sw_init = iceland_dpm_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-index 5c4001e..39bfc52 100644
---- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
-@@ -394,6 +394,7 @@ static int iceland_ih_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs iceland_ih_ip_funcs = {
-+	.name = "iceland_ih",
- 	.early_init = iceland_ih_early_init,
- 	.late_init = NULL,
- 	.sw_init = iceland_ih_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-index 4bd1e55..25b33d9 100644
---- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
-@@ -3244,6 +3244,7 @@ static int kv_dpm_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs kv_dpm_ip_funcs = {
-+	.name = "kv_dpm",
- 	.early_init = kv_dpm_early_init,
- 	.late_init = kv_dpm_late_init,
- 	.sw_init = kv_dpm_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 474d6f1..a25df59 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -1230,6 +1230,7 @@ static int sdma_v2_4_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
-+	.name = "sdma_v2_4",
- 	.early_init = sdma_v2_4_early_init,
- 	.late_init = NULL,
- 	.sw_init = sdma_v2_4_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 77186f5..313d90a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -1542,6 +1542,7 @@ static int sdma_v3_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
-+	.name = "sdma_v3_0",
- 	.early_init = sdma_v3_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = sdma_v3_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-index 552f0f4..b7615ce 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
-@@ -143,6 +143,7 @@ static int tonga_dpm_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs tonga_dpm_ip_funcs = {
-+	.name = "tonga_dpm",
- 	.early_init = tonga_dpm_early_init,
- 	.late_init = NULL,
- 	.sw_init = tonga_dpm_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-index 55cdab8..f036af9 100644
---- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
-@@ -417,6 +417,7 @@ static int tonga_ih_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs tonga_ih_ip_funcs = {
-+	.name = "tonga_ih",
- 	.early_init = tonga_ih_early_init,
- 	.late_init = NULL,
- 	.sw_init = tonga_ih_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-index b9c2a49..a75ffb5 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
-@@ -739,6 +739,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
-+	.name = "uvd_v4_2",
- 	.early_init = uvd_v4_2_early_init,
- 	.late_init = NULL,
- 	.sw_init = uvd_v4_2_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-index 465b77c..ecb8101 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
-@@ -791,6 +791,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
-+	.name = "uvd_v5_0",
- 	.early_init = uvd_v5_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = uvd_v5_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index c2f790b..a43f1a7 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -895,6 +895,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
-+	.name = "uvd_v6_0",
- 	.early_init = uvd_v6_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = uvd_v6_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-index 95f6e57..45d92ac 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
-@@ -567,6 +567,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs vce_v2_0_ip_funcs = {
-+	.name = "vce_v2_0",
- 	.early_init = vce_v2_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = vce_v2_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-index 55b35da..30e8099 100644
---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
-@@ -674,6 +674,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs vce_v3_0_ip_funcs = {
-+	.name = "vce_v3_0",
- 	.early_init = vce_v3_0_early_init,
- 	.late_init = NULL,
- 	.sw_init = vce_v3_0_sw_init,
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 16070de..7f15c1a 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1746,6 +1746,7 @@ static int vi_common_set_powergating_state(void *handle,
- }
- 
- const struct amd_ip_funcs vi_common_ip_funcs = {
-+	.name = "vi_common",
- 	.early_init = vi_common_early_init,
- 	.late_init = NULL,
- 	.sw_init = vi_common_sw_init,
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 6e812b6..839ec13 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -676,6 +676,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- }
- 
- const struct amd_ip_funcs amdgpu_dm_funcs = {
-+	.name = "dm",
- 	.early_init = dm_early_init,
- 	.late_init = NULL,
- 	.sw_init = dm_sw_init,
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index ea9ee46..6080951 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -143,6 +143,8 @@ enum amd_pm_state_type {
- };
- 
- struct amd_ip_funcs {
-+	/* Name of IP block */
-+	char *name;
- 	/* sets up early driver state (pre sw_init), does not configure hw - Optional */
- 	int (*early_init)(void *handle);
- 	/* sets up late driver/hw state (post hw_init) - Optional */
-diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-index aba587c..9f2d406 100644
---- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
-@@ -340,6 +340,7 @@ static int pp_resume(void *handle)
- }
- 
- const struct amd_ip_funcs pp_ip_funcs = {
-+	.name = "powerplay",
- 	.early_init = pp_early_init,
- 	.late_init = NULL,
- 	.sw_init = pp_sw_init,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1090-drm-amd-amdgpu-Added-more-named-DRM-info-messages-fo.patch b/common/recipes-kernel/linux/files/1090-drm-amd-amdgpu-Added-more-named-DRM-info-messages-fo.patch
deleted file mode 100644
index fb776c80..00000000
--- a/common/recipes-kernel/linux/files/1090-drm-amd-amdgpu-Added-more-named-DRM-info-messages-fo.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 8e963faf12a24671249d976ae0604a6fd0bcd2bb Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 5 May 2016 10:23:40 -0400
-Subject: [PATCH 1090/1110] drm/amd/amdgpu: Added more named DRM info messages
- for debugging
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 ++++++++++----------
- 1 file changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index f63fe24..699ea3f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1219,7 +1219,7 @@ static int amdgpu_init(struct amdgpu_device *adev)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
- 		if (r) {
--			DRM_ERROR("sw_init %d failed %d\n", i, r);
-+			DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 			return r;
- 		}
- 		adev->ip_block_status[i].sw = true;
-@@ -1252,7 +1252,7 @@ static int amdgpu_init(struct amdgpu_device *adev)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
- 		if (r) {
--			DRM_ERROR("hw_init %d failed %d\n", i, r);
-+			DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 			return r;
- 		}
- 		adev->ip_block_status[i].hw = true;
-@@ -1272,13 +1272,13 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
- 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- 								    AMD_CG_STATE_GATE);
- 		if (r) {
--			DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
-+			DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 			return r;
- 		}
- 		if (adev->ip_blocks[i].funcs->late_init) {
- 			r = adev->ip_blocks[i].funcs->late_init((void *)adev);
- 			if (r) {
--				DRM_ERROR("late_init %d failed %d\n", i, r);
-+				DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 				return r;
- 			}
- 		}
-@@ -1302,13 +1302,13 @@ static int amdgpu_fini(struct amdgpu_device *adev)
- 		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- 								    AMD_CG_STATE_UNGATE);
- 		if (r) {
--			DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
-+			DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 			return r;
- 		}
- 		r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
- 		/* XXX handle errors */
- 		if (r) {
--			DRM_DEBUG("hw_fini %d failed %d\n", i, r);
-+			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 		}
- 		adev->ip_block_status[i].hw = false;
- 	}
-@@ -1319,7 +1319,7 @@ static int amdgpu_fini(struct amdgpu_device *adev)
- 		r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
- 		/* XXX handle errors */
- 		if (r) {
--			DRM_DEBUG("sw_fini %d failed %d\n", i, r);
-+			DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 		}
- 		adev->ip_block_status[i].sw = false;
- 		adev->ip_block_status[i].valid = false;
-@@ -1347,14 +1347,14 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
- 			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- 									    AMD_CG_STATE_UNGATE);
- 			if (r) {
--				DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
-+				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 			}
- 		}
- 		/* XXX handle errors */
- 		r = adev->ip_blocks[i].funcs->suspend(adev);
- 		/* XXX handle errors */
- 		if (r) {
--			DRM_ERROR("suspend %d failed %d\n", i, r);
-+			DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 		}
- 	}
- 
-@@ -1370,7 +1370,7 @@ static int amdgpu_resume(struct amdgpu_device *adev)
- 			continue;
- 		r = adev->ip_blocks[i].funcs->resume(adev);
- 		if (r) {
--			DRM_ERROR("resume %d failed %d\n", i, r);
-+			DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
- 			return r;
- 		}
- 	}
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1091-drm-amdgpu-fix-staging-4.5-merge-error-for-pipeline-.patch b/common/recipes-kernel/linux/files/1091-drm-amdgpu-fix-staging-4.5-merge-error-for-pipeline-.patch
deleted file mode 100644
index 948eb4ce..00000000
--- a/common/recipes-kernel/linux/files/1091-drm-amdgpu-fix-staging-4.5-merge-error-for-pipeline-.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 66212c639e2fdff02ffdbade2de52602bb8e2be7 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Mon, 9 May 2016 17:29:39 +0800
-Subject: [PATCH 1091/1110] drm/amdgpu: fix staging-4.5 merge error for
- pipeline sync
-
-Change-Id: I5b30a455a2c0b03cb16dcfc6ae03e6430a97745c
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 +++++++++++++------------
- 1 file changed, 13 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index b449a40..356a389 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -3052,6 +3052,19 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
- static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
- {
- 	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
-+	uint32_t seq = ring->fence_drv.sync_seq;
-+	uint64_t addr = ring->fence_drv.gpu_addr;
-+
-+	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
-+	amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
-+				 WAIT_REG_MEM_FUNCTION(3) | /* equal */
-+				 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
-+	amdgpu_ring_write(ring, addr & 0xfffffffc);
-+	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
-+	amdgpu_ring_write(ring, seq);
-+	amdgpu_ring_write(ring, 0xffffffff);
-+	amdgpu_ring_write(ring, 4); /* poll interval */
-+
- 	if (usepfp) {
- 		/* synce CE with ME to prevent CE fetch CEIB before context switch done */
- 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
-@@ -3079,18 +3092,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 					unsigned vm_id, uint64_t pd_addr)
- {
- 	int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
--	uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
--	uint64_t addr = ring->fence_drv.gpu_addr;
--
--	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
--	amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
--				 WAIT_REG_MEM_FUNCTION(3) | /* equal */
--				 WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
--	amdgpu_ring_write(ring, addr & 0xfffffffc);
--	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
--	amdgpu_ring_write(ring, seq);
--	amdgpu_ring_write(ring, 0xffffffff);
--	amdgpu_ring_write(ring, 4); /* poll interval */
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
- 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1092-drm-amd-dal-Properly-handle-vblank-on-S3-suspend-and.patch b/common/recipes-kernel/linux/files/1092-drm-amd-dal-Properly-handle-vblank-on-S3-suspend-and.patch
deleted file mode 100644
index 0fed1bb9..00000000
--- a/common/recipes-kernel/linux/files/1092-drm-amd-dal-Properly-handle-vblank-on-S3-suspend-and.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From f78f572d16aa121f45fa73e87154d238b928a134 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Fri, 6 May 2016 18:53:46 -0400
-Subject: [PATCH 1092/1110] drm/amd/dal: Properly handle vblank on S3 suspend
- and resume.
-
-The vblank event list should be cleaned and all pending events sent when
-going to sleep so that on resume the vblank counter can be properly
-restored.
-
-Change-Id: I5592b47bbe6af778f961d8c03f5f2a6448644c93
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index f6d7920..b0ad20e 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -499,6 +499,7 @@ int amdgpu_dm_irq_suspend(
- 	struct list_head *hnd_list_h;
- 	struct list_head *hnd_list_l;
- 	unsigned long irq_table_flags;
-+	struct drm_crtc *crtc;
- 
- 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
- 
-@@ -519,6 +520,12 @@ int amdgpu_dm_irq_suspend(
- 
- 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
- 
-+
-+	drm_modeset_lock_all(adev->ddev);
-+		drm_for_each_crtc(crtc, adev->ddev)
-+			drm_crtc_vblank_off(crtc);
-+	drm_modeset_unlock_all(adev->ddev);
-+
- 	return 0;
- }
- 
-@@ -550,6 +557,7 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
- 	int src;
- 	struct list_head *hnd_list_h, *hnd_list_l;
- 	unsigned long irq_table_flags;
-+	struct drm_crtc *crtc;
- 
- 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
- 
-@@ -565,6 +573,11 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
- 
- 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
- 
-+	drm_modeset_lock_all(adev->ddev);
-+		drm_for_each_crtc(crtc, adev->ddev)
-+			drm_crtc_vblank_on(crtc);
-+	drm_modeset_unlock_all(adev->ddev);
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1093-drm-amd-dal-S3-Move-vblank_off-to-before-CRTCs-are-d.patch b/common/recipes-kernel/linux/files/1093-drm-amd-dal-S3-Move-vblank_off-to-before-CRTCs-are-d.patch
deleted file mode 100644
index bea8b8df..00000000
--- a/common/recipes-kernel/linux/files/1093-drm-amd-dal-S3-Move-vblank_off-to-before-CRTCs-are-d.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From d4c8e1052e2944e63bb3855165fbbc1645a2433a Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Wed, 11 May 2016 16:13:06 -0400
-Subject: [PATCH 1093/1110] drm/amd/dal: S3 Move vblank_off to before CRTCs are
- disabled.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c     | 20 ++++++++++++++++++--
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 15 ---------------
- 2 files changed, 18 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 839ec13..6a002df 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -461,16 +461,32 @@ static int dm_suspend(void *handle)
- 	struct amdgpu_device *adev = handle;
- 	struct amdgpu_display_manager *dm = &adev->dm;
- 	int ret = 0;
-+	struct drm_crtc *crtc;
- 
- 	s3_handle_mst(adev->ddev, true);
- 
-+	/* flash all pending vblank events and turn interrupt off
-+	 * before disabling CRTCs. They will be enabled back in
-+	 * dm_display_resume
-+	 */
-+	drm_modeset_lock_all(adev->ddev);
-+	drm_for_each_crtc(crtc, adev->ddev) {
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+		if (acrtc->target) {
-+				drm_crtc_vblank_off(crtc);
-+				dc_target_release(acrtc->target);
-+				acrtc->target = NULL;
-+			}
-+	}
-+	drm_modeset_unlock_all(adev->ddev);
-+
-+	amdgpu_dm_irq_suspend(adev);
-+
- 	dc_set_power_state(
- 		dm->dc,
- 		DC_ACPI_CM_POWER_STATE_D3,
- 		DC_VIDEO_POWER_SUSPEND);
- 
--	amdgpu_dm_irq_suspend(adev);
--
- 	return ret;
- }
- 
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-index b0ad20e..78ffe88 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
-@@ -499,7 +499,6 @@ int amdgpu_dm_irq_suspend(
- 	struct list_head *hnd_list_h;
- 	struct list_head *hnd_list_l;
- 	unsigned long irq_table_flags;
--	struct drm_crtc *crtc;
- 
- 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
- 
-@@ -519,13 +518,6 @@ int amdgpu_dm_irq_suspend(
- 	}
- 
- 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
--
--
--	drm_modeset_lock_all(adev->ddev);
--		drm_for_each_crtc(crtc, adev->ddev)
--			drm_crtc_vblank_off(crtc);
--	drm_modeset_unlock_all(adev->ddev);
--
- 	return 0;
- }
- 
-@@ -557,7 +549,6 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
- 	int src;
- 	struct list_head *hnd_list_h, *hnd_list_l;
- 	unsigned long irq_table_flags;
--	struct drm_crtc *crtc;
- 
- 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
- 
-@@ -572,12 +563,6 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev)
- 	}
- 
- 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
--
--	drm_modeset_lock_all(adev->ddev);
--		drm_for_each_crtc(crtc, adev->ddev)
--			drm_crtc_vblank_on(crtc);
--	drm_modeset_unlock_all(adev->ddev);
--
- 	return 0;
- }
- 
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1094-drm-amd-dal-Not-releasing-target-during-suspend.patch b/common/recipes-kernel/linux/files/1094-drm-amd-dal-Not-releasing-target-during-suspend.patch
deleted file mode 100644
index 41f42ce3..00000000
--- a/common/recipes-kernel/linux/files/1094-drm-amd-dal-Not-releasing-target-during-suspend.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 2b7af35e80372411f727915b0fc9964119628ce1 Mon Sep 17 00:00:00 2001
-From: Zeyu Fan <Zeyu.Fan@amd.com>
-Date: Thu, 19 May 2016 14:59:04 -0400
-Subject: [PATCH 1094/1110] drm/amd/dal: Not releasing target during suspend.
-
-Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index 6a002df..bfa9e75 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -472,11 +472,8 @@ static int dm_suspend(void *handle)
- 	drm_modeset_lock_all(adev->ddev);
- 	drm_for_each_crtc(crtc, adev->ddev) {
- 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
--		if (acrtc->target) {
-+		if (acrtc->target)
- 				drm_crtc_vblank_off(crtc);
--				dc_target_release(acrtc->target);
--				acrtc->target = NULL;
--			}
- 	}
- 	drm_modeset_unlock_all(adev->ddev);
- 
-@@ -652,6 +649,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	struct amdgpu_connector *aconnector;
- 	struct drm_connector *connector;
- 	int ret = 0;
-+	struct drm_crtc *crtc;
- 
- 	/* program HPD filter */
- 	dc_resume(dm->dc);
-@@ -665,6 +663,14 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	 */
- 	amdgpu_dm_irq_resume_early(adev);
- 
-+	drm_modeset_lock_all(ddev);
-+	drm_for_each_crtc(crtc, ddev) {
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+		if (acrtc->target)
-+				drm_crtc_vblank_on(crtc);
-+	}
-+	drm_modeset_unlock_all(ddev);
-+
- 	/* Do detection*/
- 	list_for_each_entry(connector,
- 			&ddev->mode_config.connector_list, head) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1095-drm-amdgpu-add-late_fini-for-ip_funcs.patch b/common/recipes-kernel/linux/files/1095-drm-amdgpu-add-late_fini-for-ip_funcs.patch
deleted file mode 100644
index d5e3e6de..00000000
--- a/common/recipes-kernel/linux/files/1095-drm-amdgpu-add-late_fini-for-ip_funcs.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From c5143a30c8e8ac348d15c13b073b37dd520268be Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 19 May 2016 14:35:17 +0800
-Subject: [PATCH 1095/1110] drm/amdgpu:add late_fini for ip_funcs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Change-Id: Ibfcf42c8546dbfc07cf2370d7eed671dffe2eed5
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/include/amd_shared.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
-index 6080951..afce1ed 100644
---- a/drivers/gpu/drm/amd/include/amd_shared.h
-+++ b/drivers/gpu/drm/amd/include/amd_shared.h
-@@ -157,6 +157,7 @@ struct amd_ip_funcs {
- 	int (*hw_init)(void *handle);
- 	/* tears down the hw state */
- 	int (*hw_fini)(void *handle);
-+	void (*late_fini)(void *handle);
- 	/* handles IP specific hw/sw changes for suspend */
- 	int (*suspend)(void *handle);
- 	/* handles IP specific hw/sw changes for resume */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1096-drm-amdgpu-impl-late_fini-for-amdgpu_pp_ip.patch b/common/recipes-kernel/linux/files/1096-drm-amdgpu-impl-late_fini-for-amdgpu_pp_ip.patch
deleted file mode 100644
index 30e0865f..00000000
--- a/common/recipes-kernel/linux/files/1096-drm-amdgpu-impl-late_fini-for-amdgpu_pp_ip.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 12a4ce95a63bd92f3a1a72035cc0b8958fc85427 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Thu, 19 May 2016 14:36:01 +0800
-Subject: [PATCH 1096/1110] drm/amdgpu:impl late_fini for amdgpu_pp_ip
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Change-Id: Ifddae2313f27fabc7863d2a428ad0e692c51cd22
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-index 1540359..630ed7a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
-@@ -221,6 +221,22 @@ static int amdgpu_pp_hw_fini(void *handle)
- 	return ret;
- }
- 
-+static void amdgpu_pp_late_fini(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+#ifdef CONFIG_DRM_AMD_POWERPLAY
-+	if (adev->pp_enabled) {
-+		amdgpu_pm_sysfs_fini(adev);
-+		amd_powerplay_fini(adev->powerplay.pp_handle);
-+	}
-+
-+	if (adev->powerplay.ip_funcs->late_fini)
-+		adev->powerplay.ip_funcs->late_fini(
-+			  adev->powerplay.pp_handle);
-+#endif
-+}
-+
- static int amdgpu_pp_suspend(void *handle)
- {
- 	int ret = 0;
-@@ -309,6 +325,7 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
- 	.sw_fini = amdgpu_pp_sw_fini,
- 	.hw_init = amdgpu_pp_hw_init,
- 	.hw_fini = amdgpu_pp_hw_fini,
-+	.late_fini = amdgpu_pp_late_fini,
- 	.suspend = amdgpu_pp_suspend,
- 	.resume = amdgpu_pp_resume,
- 	.is_idle = amdgpu_pp_is_idle,
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1097-drm-amdgpu-modify-sdma-start-sequence.patch b/common/recipes-kernel/linux/files/1097-drm-amdgpu-modify-sdma-start-sequence.patch
deleted file mode 100644
index 8f574d81..00000000
--- a/common/recipes-kernel/linux/files/1097-drm-amdgpu-modify-sdma-start-sequence.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From ba897ff2f4fa5c0123a4a38623f155838affeed5 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Wed, 25 May 2016 16:57:14 +0800
-Subject: [PATCH 1097/1110] drm/amdgpu:modify sdma start sequence
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-should fist halt engine, and then doing the register
-programing, and later unhalt engine, and finally run
-ring_test.
-
-this help fix reloading driver hang issue of SDMA
-ring
-
-original sequence is wrong for it programing engine
-after unhalt, which will lead to fault behavior when
-doing driver reloading after unloaded.
-
-Change-Id: Iaccc65f6783dc40cc55714508ac907c0c70ccc2b
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  9 +++++++--
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  8 ++++++--
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 15 +++++++++++----
- 3 files changed, 24 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 223212f..03e89d2 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -445,7 +445,12 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
- 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
- 
- 		ring->ready = true;
-+	}
-+
-+	cik_sdma_enable(adev, true);
- 
-+	for (i = 0; i < adev->sdma.num_instances; i++) {
-+		ring = &adev->sdma.instance[i].ring;
- 		r = amdgpu_ring_test_ring(ring);
- 		if (r) {
- 			ring->ready = false;
-@@ -528,8 +533,8 @@ static int cik_sdma_start(struct amdgpu_device *adev)
- 	if (r)
- 		return r;
- 
--	/* unhalt the MEs */
--	cik_sdma_enable(adev, true);
-+	/* halt the engine before programing */
-+	cik_sdma_enable(adev, false);
- 
- 	/* start the gfx rings and rlc compute queues */
- 	r = cik_sdma_gfx_resume(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index a25df59..f462549 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -488,7 +488,11 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
- 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
- 
- 		ring->ready = true;
-+	}
- 
-+	sdma_v2_4_enable(adev, true);
-+	for (i = 0; i < adev->sdma.num_instances; i++) {
-+		ring = &adev->sdma.instance[i].ring;
- 		r = amdgpu_ring_test_ring(ring);
- 		if (r) {
- 			ring->ready = false;
-@@ -579,8 +583,8 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
- 			return -EINVAL;
- 	}
- 
--	/* unhalt the MEs */
--	sdma_v2_4_enable(adev, true);
-+	/* halt the engine before programing */
-+	sdma_v2_4_enable(adev, false);
- 
- 	/* start the gfx rings and rlc compute queues */
- 	r = sdma_v2_4_gfx_resume(adev);
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 313d90a..9c30f9a 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -708,7 +708,15 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
- 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
- 
- 		ring->ready = true;
-+	}
- 
-+	/* unhalt the MEs */
-+	sdma_v3_0_enable(adev, true);
-+	/* enable sdma ring preemption */
-+	sdma_v3_0_ctx_switch_enable(adev, true);
-+
-+	for (i = 0; i < adev->sdma.num_instances; i++) {
-+		ring = &adev->sdma.instance[i].ring;
- 		r = amdgpu_ring_test_ring(ring);
- 		if (r) {
- 			ring->ready = false;
-@@ -801,10 +809,9 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
- 		}
- 	}
- 
--	/* unhalt the MEs */
--	sdma_v3_0_enable(adev, true);
--	/* enable sdma ring preemption */
--	sdma_v3_0_ctx_switch_enable(adev, true);
-+	/* disble sdma engine before programing it */
-+	sdma_v3_0_ctx_switch_enable(adev, false);
-+	sdma_v3_0_enable(adev, false);
- 
- 	/* start the gfx rings and rlc compute queues */
- 	r = sdma_v3_0_gfx_resume(adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1098-drm-amd-dal-Revert-to-generic-list-iteration.patch b/common/recipes-kernel/linux/files/1098-drm-amd-dal-Revert-to-generic-list-iteration.patch
deleted file mode 100644
index dbad7999..00000000
--- a/common/recipes-kernel/linux/files/1098-drm-amd-dal-Revert-to-generic-list-iteration.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From a6b0c97b89a33748c29f933457d572310f321e18 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Date: Thu, 2 Jun 2016 15:51:50 -0400
-Subject: [PATCH 1098/1110] drm/amd/dal: Revert to generic list iteration.
-
-Do not break code under 4.1 kernel.
-
-Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
-Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-index bfa9e75..9a87f0f 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
-@@ -470,7 +470,7 @@ static int dm_suspend(void *handle)
- 	 * dm_display_resume
- 	 */
- 	drm_modeset_lock_all(adev->ddev);
--	drm_for_each_crtc(crtc, adev->ddev) {
-+	list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) {
- 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- 		if (acrtc->target)
- 				drm_crtc_vblank_off(crtc);
-@@ -664,7 +664,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
- 	amdgpu_dm_irq_resume_early(adev);
- 
- 	drm_modeset_lock_all(ddev);
--	drm_for_each_crtc(crtc, ddev) {
-+	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
- 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
- 		if (acrtc->target)
- 				drm_crtc_vblank_on(crtc);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1099-drm-amdgpu-free-sync-ioctl-declaration.patch b/common/recipes-kernel/linux/files/1099-drm-amdgpu-free-sync-ioctl-declaration.patch
deleted file mode 100644
index b1eeaafd..00000000
--- a/common/recipes-kernel/linux/files/1099-drm-amdgpu-free-sync-ioctl-declaration.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From 598f6022cf8423acc5f256767f7e14c94fc02f9c Mon Sep 17 00:00:00 2001
-From: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Date: Wed, 1 Jun 2016 11:37:37 -0400
-Subject: [PATCH 1099/1110] drm/amdgpu: free sync ioctl declaration
-
-declared enter and exit free sync mode signal
-for kernel
-
-Change-Id: Ib06a21fde9d732036cf7fcf800a7a2c82e529d7a
-Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h         |  3 +++
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 15 +++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c     |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h    | 10 ++++++++++
- include/uapi/drm/amdgpu_drm.h               |  8 ++++++++
- 5 files changed, 37 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 3a3815c..1c50f29 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1867,6 +1867,9 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi
- int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
- 				struct drm_file *filp);
- 
-+int amdgpu_freesync_ioctl(struct drm_device *dev, void *data,
-+			    struct drm_file *filp);
-+
- /* VRAM scratch page for HDP bug, default vram page */
- struct amdgpu_vram_scratch {
- 	struct amdgpu_bo		*robj;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index 58fd8aa..bd8fabc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -909,3 +909,18 @@ int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
- 		return AMDGPU_CRTC_IRQ_NONE;
- 	}
- }
-+
-+int amdgpu_freesync_ioctl(struct drm_device *dev, void *data,
-+			    struct drm_file *filp)
-+{
-+	int ret = -EPERM;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	if (adev->mode_info.funcs->notify_freesync)
-+		ret = adev->mode_info.funcs->notify_freesync(dev,data,filp);
-+	else
-+		DRM_DEBUG("amdgpu no notify_freesync ioctl\n");
-+
-+	return ret;
-+}
-+
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index 2e82537..b6e9d81 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -754,5 +754,6 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER)
- };
- const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index a8173b1..d889530 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -306,6 +306,10 @@ struct amdgpu_display_funcs {
- 			       struct amdgpu_mode_mc_save *save);
- 	void (*resume_mc_access)(struct amdgpu_device *adev,
- 				 struct amdgpu_mode_mc_save *save);
-+	/* it is used to enter or exit into free sync mode */
-+	int (*notify_freesync)(struct drm_device *dev, void *data,
-+			struct drm_file *filp);
-+
- };
- 
- struct amdgpu_framebuffer {
-@@ -567,6 +571,12 @@ struct amdgpu_connector {
- 
- 	/* TODO see if we can merge with ddc_bus or make a dm_connector */
- 	struct amdgpu_i2c_adapter *i2c;
-+
-+	/* Monitor range limits */
-+	int min_vfreq ;
-+	int max_vfreq ;
-+	int pixel_clock_mhz;
-+
- };
- 
- /* TODO: start to use this struct and remove same field from base one */
-diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
-index e52933a..7039d22 100644
---- a/include/uapi/drm/amdgpu_drm.h
-+++ b/include/uapi/drm/amdgpu_drm.h
-@@ -46,6 +46,7 @@
- #define DRM_AMDGPU_WAIT_CS		0x09
- #define DRM_AMDGPU_GEM_OP		0x10
- #define DRM_AMDGPU_GEM_USERPTR		0x11
-+#define DRM_AMDGPU_FREESYNC             0x14
- 
- #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
- #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
-@@ -59,6 +60,7 @@
- #define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
- #define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
- #define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
-+#define DRM_IOCTL_AMDGPU_FREESYNC       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
- 
- #define AMDGPU_GEM_DOMAIN_CPU		0x1
- #define AMDGPU_GEM_DOMAIN_GTT		0x2
-@@ -642,4 +644,10 @@ struct drm_amdgpu_info_hw_ip {
- #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
- #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
- 
-+struct drm_amdgpu_freesync {
-+         __u32 op;                       /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
-+                                         /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
-+         __u32 spare[7];
-+};
-+
- #endif
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1100-drm-amdgpu-drm_helper_resume_force_mode-is-only-work.patch b/common/recipes-kernel/linux/files/1100-drm-amdgpu-drm_helper_resume_force_mode-is-only-work.patch
deleted file mode 100644
index f82334c5..00000000
--- a/common/recipes-kernel/linux/files/1100-drm-amdgpu-drm_helper_resume_force_mode-is-only-work.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From af57c34afa0ab1c35877e8a3f0ab96e58b28b4af Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Mon, 6 Jun 2016 14:19:02 +0800
-Subject: [PATCH 1100/1110] drm/amdgpu: drm_helper_resume_force_mode is only
- working for non-DAL driver
-
-Change-Id: I6c9210a37a43585065d5f8de7814f89717f87bc9
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 699ea3f..a92189a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1964,7 +1964,11 @@ retry:
- 		}
- 	}
- 
--	drm_helper_resume_force_mode(adev->ddev);
-+	if (amdgpu_device_has_dal_support(adev))
-+		/* TODO needed from DAL, otherwise the mode cannot be back */
-+		;
-+	else
-+		drm_helper_resume_force_mode(adev->ddev);
- 
- 	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
- 	if (r) {
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1101-drm-amdgpu-mode-restore-for-atomic-modesetting.patch b/common/recipes-kernel/linux/files/1101-drm-amdgpu-mode-restore-for-atomic-modesetting.patch
deleted file mode 100644
index 77b82b4e..00000000
--- a/common/recipes-kernel/linux/files/1101-drm-amdgpu-mode-restore-for-atomic-modesetting.patch
+++ /dev/null
@@ -1,310 +0,0 @@
-From 46e8daa3ae37d593134460c2a31f8e080cf89b34 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Wed, 8 Jun 2016 14:01:24 +0800
-Subject: [PATCH 1101/1110] drm/amdgpu: mode restore for atomic modesetting
-
-Change-Id: If6eade28208053e549af0e839124f1bc46c1a81b
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   8 +-
- drivers/gpu/drm/drm_atomic.c               |   2 +-
- drivers/gpu/drm/drm_atomic_helper.c        | 156 +++++++++++++++++++++++++++++
- drivers/gpu/drm/drm_modeset_lock.c         |  10 +-
- include/drm/drm_atomic_helper.h            |   6 +-
- include/drm/drm_modeset_lock.h             |   2 +-
- 6 files changed, 176 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index a92189a..9c892b9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -30,6 +30,7 @@
- #include <linux/debugfs.h>
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_atomic_helper.h>
- #include <drm/amdgpu_drm.h>
- #include <linux/vgaarb.h>
- #include <linux/vga_switcheroo.h>
-@@ -1898,6 +1899,7 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
-  */
- int amdgpu_gpu_reset(struct amdgpu_device *adev)
- {
-+	struct drm_atomic_state *state = NULL;
- 	unsigned ring_sizes[AMDGPU_MAX_RINGS];
- 	uint32_t *ring_data[AMDGPU_MAX_RINGS];
- 
-@@ -1910,6 +1912,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
- 
- 	/* block TTM */
- 	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
-+	/* store modesetting */
-+	if (amdgpu_device_has_dal_support(adev))
-+		state = drm_atomic_helper_suspend(adev->ddev);
- 
- 	r = amdgpu_suspend(adev);
- 
-@@ -1965,8 +1970,7 @@ retry:
- 	}
- 
- 	if (amdgpu_device_has_dal_support(adev))
--		/* TODO needed from DAL, otherwise the mode cannot be back */
--		;
-+		r = drm_atomic_helper_resume(adev->ddev, state);
- 	else
- 		drm_helper_resume_force_mode(adev->ddev);
- 
-diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
-index aeee083..993a25f 100644
---- a/drivers/gpu/drm/drm_atomic.c
-+++ b/drivers/gpu/drm/drm_atomic.c
-@@ -1195,7 +1195,7 @@ retry:
- 			       state->acquire_ctx);
- 	if (ret)
- 		goto retry;
--	ret = drm_modeset_lock_all_crtcs(state->dev,
-+	ret = drm_modeset_lock_all_ctx(state->dev,
- 					 state->acquire_ctx);
- 	if (ret)
- 		goto retry;
-diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
-index e5aec45..6691755 100644
---- a/drivers/gpu/drm/drm_atomic_helper.c
-+++ b/drivers/gpu/drm/drm_atomic_helper.c
-@@ -1817,6 +1817,162 @@ commit:
- 	return 0;
- }
- 
-+/*
-+ * drm_atomic_helper_disable_all - disable all currently active outputs
-+ * @dev: DRM device
-+ * @ctx: lock acquisition context
-+ *
-+ * Loops through all connectors, finding those that aren't turned off and then
-+ * turns them off by setting their DPMS mode to OFF and deactivating the CRTC
-+ * that they are connected to.
-+ *
-+ * This is used for example in suspend/resume to disable all currently active
-+ * functions when suspending.
-+ *
-+ * Note that if callers haven't already acquired all modeset locks this might
-+ * return -EDEADLK, which must be handled by calling drm_modeset_backoff().
-+ *
-+ * Returns:
-+ * 0 on success or a negative error code on failure.
-+ *
-+ * See also:
-+ * drm_atomic_helper_suspend(), drm_atomic_helper_resume()
-+ */
-+int drm_atomic_helper_disable_all(struct drm_device *dev,
-+                                  struct drm_modeset_acquire_ctx *ctx)
-+{
-+         struct drm_atomic_state *state;
-+         struct drm_connector *conn;
-+         int err;
-+ 
-+         state = drm_atomic_state_alloc(dev);
-+         if (!state)
-+                 return -ENOMEM;
-+ 
-+         state->acquire_ctx = ctx;
-+ 
-+         drm_for_each_connector(conn, dev) {
-+                 struct drm_crtc *crtc = conn->state->crtc;
-+                 struct drm_crtc_state *crtc_state;
-+ 
-+                 if (!crtc || conn->dpms != DRM_MODE_DPMS_ON)
-+                         continue;
-+ 
-+                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
-+                 if (IS_ERR(crtc_state)) {
-+                         err = PTR_ERR(crtc_state);
-+                         goto free;
-+                 }
-+ 
-+                 crtc_state->active = false;
-+         }
-+ 
-+         err = drm_atomic_commit(state);
-+
-+free:
-+         if (err < 0)
-+                 drm_atomic_state_free(state);
-+ 
-+         return err;
-+}
-+EXPORT_SYMBOL(drm_atomic_helper_disable_all);
-+
-+
-+/**
-+ * drm_atomic_helper_suspend - subsystem-level suspend helper
-+ * @dev: DRM device
-+ *
-+ * Duplicates the current atomic state, disables all active outputs and then
-+ * returns a pointer to the original atomic state to the caller. Drivers can
-+ * pass this pointer to the drm_atomic_helper_resume() helper upon resume to
-+ * restore the output configuration that was active at the time the system
-+ * entered suspend.
-+ *
-+ * Note that it is potentially unsafe to use this. The atomic state object
-+ * returned by this function is assumed to be persistent. Drivers must ensure
-+ * that this holds true. Before calling this function, drivers must make sure
-+ * to suspend fbdev emulation so that nothing can be using the device.
-+ *
-+ * Returns:
-+ * A pointer to a copy of the state before suspend on success or an ERR_PTR()-
-+ * encoded error code on failure. Drivers should store the returned atomic
-+ * state object and pass it to the drm_atomic_helper_resume() helper upon
-+ * resume.
-+ *
-+ * See also:
-+ * drm_atomic_helper_duplicate_state(), drm_atomic_helper_disable_all(),
-+ * drm_atomic_helper_resume()
-+ */
-+struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev)
-+{
-+         struct drm_modeset_acquire_ctx ctx;
-+         struct drm_atomic_state *state;
-+         int err;
-+ 
-+         drm_modeset_acquire_init(&ctx, 0);
-+ 
-+retry:
-+         err = drm_modeset_lock_all_ctx(dev, &ctx);
-+         if (err < 0) {
-+                 state = ERR_PTR(err);
-+                 goto unlock;
-+         }
-+ 
-+         state = drm_atomic_helper_duplicate_state(dev, &ctx);
-+         if (IS_ERR(state))
-+                 goto unlock;
-+ 
-+         err = drm_atomic_helper_disable_all(dev, &ctx);
-+         if (err < 0) {
-+                 drm_atomic_state_free(state);
-+                 state = ERR_PTR(err);
-+                 goto unlock;
-+         }
-+ 
-+unlock:
-+         if (PTR_ERR(state) == -EDEADLK) {
-+                 drm_modeset_backoff(&ctx);
-+                 goto retry;
-+         }
-+ 
-+         drm_modeset_drop_locks(&ctx);
-+         drm_modeset_acquire_fini(&ctx);
-+         return state;
-+}
-+EXPORT_SYMBOL(drm_atomic_helper_suspend);
-+
-+/**
-+ * drm_atomic_helper_resume - subsystem-level resume helper
-+ * @dev: DRM device
-+ * @state: atomic state to resume to
-+ *
-+ * Calls drm_mode_config_reset() to synchronize hardware and software states,
-+ * grabs all modeset locks and commits the atomic state object. This can be
-+ * used in conjunction with the drm_atomic_helper_suspend() helper to
-+ * implement suspend/resume for drivers that support atomic mode-setting.
-+ *
-+ * Returns:
-+ * 0 on success or a negative error code on failure.
-+ *
-+ * See also:
-+ * drm_atomic_helper_suspend()
-+ */
-+int drm_atomic_helper_resume(struct drm_device *dev,
-+                             struct drm_atomic_state *state)
-+{
-+         struct drm_mode_config *config = &dev->mode_config;
-+         int err;
-+ 
-+         drm_mode_config_reset(dev);
-+         drm_modeset_lock_all(dev);
-+         state->acquire_ctx = config->acquire_ctx;
-+         err = drm_atomic_commit(state);
-+         drm_modeset_unlock_all(dev);
-+ 
-+         return err;
-+}
-+EXPORT_SYMBOL(drm_atomic_helper_resume);
-+
- /**
-  * drm_atomic_helper_crtc_set_property - helper for crtc properties
-  * @crtc: DRM crtc
-diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c
-index 6675b14..8c09b92 100644
---- a/drivers/gpu/drm/drm_modeset_lock.c
-+++ b/drivers/gpu/drm/drm_modeset_lock.c
-@@ -81,7 +81,7 @@ retry:
- 	ret = drm_modeset_lock(&config->connection_mutex, ctx);
- 	if (ret)
- 		goto fail;
--	ret = drm_modeset_lock_all_crtcs(dev, ctx);
-+	ret = drm_modeset_lock_all_ctx(dev, ctx);
- 	if (ret)
- 		goto fail;
- 
-@@ -433,13 +433,17 @@ EXPORT_SYMBOL(drm_modeset_unlock);
- 
- /* In some legacy codepaths it's convenient to just grab all the crtc and plane
-  * related locks. */
--int drm_modeset_lock_all_crtcs(struct drm_device *dev,
-+int drm_modeset_lock_all_ctx(struct drm_device *dev,
- 		struct drm_modeset_acquire_ctx *ctx)
- {
- 	struct drm_crtc *crtc;
- 	struct drm_plane *plane;
- 	int ret = 0;
- 
-+	ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx);
-+	if (ret)
-+		return ret;
-+
- 	drm_for_each_crtc(crtc, dev) {
- 		ret = drm_modeset_lock(&crtc->mutex, ctx);
- 		if (ret)
-@@ -454,4 +458,4 @@ int drm_modeset_lock_all_crtcs(struct drm_device *dev,
- 
- 	return 0;
- }
--EXPORT_SYMBOL(drm_modeset_lock_all_crtcs);
-+EXPORT_SYMBOL(drm_modeset_lock_all_ctx);
-diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
-index 8cba54a..d70b295 100644
---- a/include/drm/drm_atomic_helper.h
-+++ b/include/drm/drm_atomic_helper.h
-@@ -80,7 +80,11 @@ int __drm_atomic_helper_disable_plane(struct drm_plane *plane,
- int drm_atomic_helper_set_config(struct drm_mode_set *set);
- int __drm_atomic_helper_set_config(struct drm_mode_set *set,
- 		struct drm_atomic_state *state);
--
-+int drm_atomic_helper_disable_all(struct drm_device *dev,
-+                                  struct drm_modeset_acquire_ctx *ctx);
-+struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev);
-+int drm_atomic_helper_resume(struct drm_device *dev,
-+                             struct drm_atomic_state *state);
- int drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc,
- 					struct drm_property *property,
- 					uint64_t val);
-diff --git a/include/drm/drm_modeset_lock.h b/include/drm/drm_modeset_lock.h
-index 94938d8..1e70a67 100644
---- a/include/drm/drm_modeset_lock.h
-+++ b/include/drm/drm_modeset_lock.h
-@@ -138,7 +138,7 @@ void drm_warn_on_modeset_not_all_locked(struct drm_device *dev);
- struct drm_modeset_acquire_ctx *
- drm_modeset_legacy_acquire_ctx(struct drm_crtc *crtc);
- 
--int drm_modeset_lock_all_crtcs(struct drm_device *dev,
-+int drm_modeset_lock_all_ctx(struct drm_device *dev,
- 		struct drm_modeset_acquire_ctx *ctx);
- 
- #endif /* DRM_MODESET_LOCK_H_ */
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1103-drm-amdgpu-use-PCI_D3hot-for-PX-systems-without-dGPU.patch b/common/recipes-kernel/linux/files/1103-drm-amdgpu-use-PCI_D3hot-for-PX-systems-without-dGPU.patch
deleted file mode 100644
index 887d60f4..00000000
--- a/common/recipes-kernel/linux/files/1103-drm-amdgpu-use-PCI_D3hot-for-PX-systems-without-dGPU.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 7e67920e683191c2ef8b5f52da2573a721a11bbc Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 1 Jun 2016 13:12:25 -0400
-Subject: [PATCH 1103/1110] drm/amdgpu: use PCI_D3hot for PX systems without
- dGPU power control
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-On PX systems without dGPU power control, use PCI_D3hot.
-
-Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
-Acked-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h              | 4 ++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 8 ++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c          | 5 ++++-
- 3 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1c50f29..c105e68 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -2402,9 +2402,13 @@ bool amdgpu_device_is_px(struct drm_device *dev);
- #if defined(CONFIG_VGA_SWITCHEROO)
- void amdgpu_register_atpx_handler(void);
- void amdgpu_unregister_atpx_handler(void);
-+bool amdgpu_has_atpx_dgpu_power_cntl(void);
-+bool amdgpu_is_atpx_hybrid(void);
- #else
- static inline void amdgpu_register_atpx_handler(void) {}
- static inline void amdgpu_unregister_atpx_handler(void) {}
-+static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
-+static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
- #endif
- 
- /*
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-index b5531b2..45d93bb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-@@ -28,6 +28,7 @@ struct amdgpu_atpx_functions {
- struct amdgpu_atpx {
- 	acpi_handle handle;
- 	struct amdgpu_atpx_functions functions;
-+        bool is_hybrid;
- };
- 
- static struct amdgpu_atpx_priv {
-@@ -63,6 +64,13 @@ struct atpx_mux {
- bool amdgpu_has_atpx(void) {
- 	return amdgpu_atpx_priv.atpx_detected;
- }
-+bool amdgpu_has_atpx_dgpu_power_cntl(void) {
-+         return amdgpu_atpx_priv.atpx.functions.power_cntl;
-+}
-+
-+bool amdgpu_is_atpx_hybrid(void) {
-+         return amdgpu_atpx_priv.atpx.is_hybrid;
-+}
- 
- /**
-  * amdgpu_atpx_call - call an ATPX method
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 30e8c46..af014c3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -395,7 +395,10 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
- 	pci_save_state(pdev);
- 	pci_disable_device(pdev);
- 	pci_ignore_hotplug(pdev);
--	pci_set_power_state(pdev, PCI_D3cold);
-+	if (amdgpu_has_atpx_dgpu_power_cntl())
-+		pci_set_power_state(pdev, PCI_D3cold);
-+	else
-+		pci_set_power_state(pdev, PCI_D3hot);
- 	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
- 
- 	return 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1104-drm-amdgpu-add-amdgpu_irq_gpu_reset_resume_helper.patch b/common/recipes-kernel/linux/files/1104-drm-amdgpu-add-amdgpu_irq_gpu_reset_resume_helper.patch
deleted file mode 100644
index 038f1208..00000000
--- a/common/recipes-kernel/linux/files/1104-drm-amdgpu-add-amdgpu_irq_gpu_reset_resume_helper.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 3982ce2f077ad959cebf595c37761a04a39d6da0 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 16 Jun 2016 16:54:53 +0800
-Subject: [PATCH 1104/1110] drm/amdgpu: add amdgpu_irq_gpu_reset_resume_helper
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-irq need to update when gpu reset happens.
-
-Change-Id: I73e20b25b937c6028007bac808f5fca3942e2480
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c    | 12 ++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h    |  1 +
- 3 files changed, 14 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 9c892b9..e03d215 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1979,6 +1979,7 @@ retry:
- 		/* bad news, how to tell it to userspace ? */
- 		dev_info(adev->dev, "GPU reset failed\n");
- 	}
-+	amdgpu_irq_gpu_reset_resume_helper(adev);
- 
- 	return r;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-index 8d34ccd..832dfbb 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
-@@ -393,6 +393,18 @@ int amdgpu_irq_update(struct amdgpu_device *adev,
- 	return r;
- }
- 
-+void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
-+{
-+	int i, j;
-+	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; i++) {
-+		struct amdgpu_irq_src *src = adev->irq.sources[i];
-+		if (!src)
-+			continue;
-+		for (j = 0; j < src->num_types; j++)
-+			amdgpu_irq_update(adev, src, j);
-+	}
-+}
-+
- /**
-  * amdgpu_irq_get - enable interrupt
-  *
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
-index e124b59..7ef0935 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
-@@ -94,6 +94,7 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- 		   unsigned type);
- bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- 			unsigned type);
-+void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
- 
- int amdgpu_irq_add_domain(struct amdgpu_device *adev);
- void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1105-drm-amdgpu-add-dm_display_resume-to-balance-dm_suspe.patch b/common/recipes-kernel/linux/files/1105-drm-amdgpu-add-dm_display_resume-to-balance-dm_suspe.patch
deleted file mode 100644
index 71e7ab6e..00000000
--- a/common/recipes-kernel/linux/files/1105-drm-amdgpu-add-dm_display_resume-to-balance-dm_suspe.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 7b3e0b129a4a2fcfef573063ecf6c70d642d3b5f Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 17 Jun 2016 11:00:15 +0800
-Subject: [PATCH 1105/1110] drm/amdgpu: add dm_display_resume to balance
- dm_suspend
-
-Change-Id: I5ed30c7c8294c3a78a250160f06e21cf0f1d9004
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index e03d215..5f43c3e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1969,9 +1969,10 @@ retry:
- 		}
- 	}
- 
--	if (amdgpu_device_has_dal_support(adev))
-+	if (amdgpu_device_has_dal_support(adev)) {
- 		r = drm_atomic_helper_resume(adev->ddev, state);
--	else
-+		amdgpu_dm_display_resume(adev);
-+	} else
- 		drm_helper_resume_force_mode(adev->ddev);
- 
- 	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1106-drm-amdgpu-dce8-fix-flash-with-white-screen-on-monit.patch b/common/recipes-kernel/linux/files/1106-drm-amdgpu-dce8-fix-flash-with-white-screen-on-monit.patch
deleted file mode 100644
index a2f61df6..00000000
--- a/common/recipes-kernel/linux/files/1106-drm-amdgpu-dce8-fix-flash-with-white-screen-on-monit.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From 175904f5bcada8c546b878bd0373853bcc0ee862 Mon Sep 17 00:00:00 2001
-From: Junwei Zhang <Jerry.Zhang@amd.com>
-Date: Fri, 17 Jun 2016 17:07:56 +0800
-Subject: [PATCH 1106/1110] drm/amdgpu/dce8: fix flash with white screen on
- monitor
-
-Fixed mc stop and resume hardware programming sequence.
-
-Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 67 ++++-------------------------------
- 1 file changed, 7 insertions(+), 60 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 6c496ab..6fa21aa 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -523,36 +523,16 @@ void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
- 		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
- 					     CRTC_CONTROL, CRTC_MASTER_EN);
- 		if (crtc_enabled) {
--#if 0
--			u32 frame_count;
--			int j;
--
-+#if 1
- 			save->crtc_enabled[i] = true;
- 			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
- 			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
--				amdgpu_display_vblank_wait(adev, i);
--				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
-+				/*it is correct only for RGB ; black is 0*/
-+				WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
- 				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
- 				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
--				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			}
--			/* wait for the next frame */
--			frame_count = amdgpu_display_vblank_get_counter(adev, i);
--			for (j = 0; j < adev->usec_timeout; j++) {
--				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
--					break;
--				udelay(1);
--			}
--			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
--				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
--				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
--				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
--				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- 			}
-+			mdelay(20);
- #else
- 			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
- 			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
-@@ -572,55 +552,22 @@ void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
- void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
- 			       struct amdgpu_mode_mc_save *save)
- {
--	u32 tmp, frame_count;
--	int i, j;
-+	u32 tmp;
-+	int i;
- 
- 	/* update crtc base addresses */
- 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
- 		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
- 		       upper_32_bits(adev->mc.vram_start));
--		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
--		       upper_32_bits(adev->mc.vram_start));
- 		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
- 		       (u32)adev->mc.vram_start);
--		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
--		       (u32)adev->mc.vram_start);
- 
- 		if (save->crtc_enabled[i]) {
--			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
--				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
--				WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
--				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
--				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
--			}
--			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
--			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
--				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
--				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
--			}
--			for (j = 0; j < adev->usec_timeout; j++) {
--				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
--				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
--					break;
--				udelay(1);
--			}
- 			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
- 			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
- 			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
--			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
--			/* wait for the next frame */
--			frame_count = amdgpu_display_vblank_get_counter(adev, i);
--			for (j = 0; j < adev->usec_timeout; j++) {
--				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
--					break;
--				udelay(1);
--			}
- 		}
-+		mdelay(20);
- 	}
- 
- 	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1107-drm-amdgpu-fix-UVD-enabled-display-after-system-resu.patch b/common/recipes-kernel/linux/files/1107-drm-amdgpu-fix-UVD-enabled-display-after-system-resu.patch
deleted file mode 100644
index 6df693cc..00000000
--- a/common/recipes-kernel/linux/files/1107-drm-amdgpu-fix-UVD-enabled-display-after-system-resu.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 7bfda3a4c5a894c4f91ff0acd600e551664d8105 Mon Sep 17 00:00:00 2001
-From: Raveendra Talabattula <raveendra.talabattula@amd.com>
-Date: Tue, 19 Jul 2016 14:05:50 +0530
-Subject: [PATCH 1107/1110] drm/amdgpu: fix UVD enabled display after system
- resume
-
-During a playback using hardware decode (vdpau/vaapi), if the
-system enters suspend and resumes back, the output of sysfs
-entry amdgpu_pm_info displays UVD as being disabled. It is
-confirmed from the output of ps and top commands that UVD is
-actually engaged even after system resume.
-
-This patch fixes the issue and the amdgpu_pm_info correctly
-reports UVD being enabled after system resume.
-
-Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index a43f1a7..9b27c69 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -34,6 +34,7 @@
- #include "smu/smu_7_1_3_d.h"
- #include "smu/smu_7_1_3_sh_mask.h"
- #include "vi.h"
-+#include "amdgpu_pm.h"
- 
- static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
- static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
-@@ -246,6 +247,8 @@ static int uvd_v6_0_resume(void *handle)
- 	r = uvd_v6_0_hw_init(adev);
- 	if (r)
- 		return r;
-+	
-+	amdgpu_dpm_enable_uvd(adev, true);
- 
- 	return r;
- }
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1108-drm-amdgpu-fix-uvd-fini-mem-leak.patch b/common/recipes-kernel/linux/files/1108-drm-amdgpu-fix-uvd-fini-mem-leak.patch
deleted file mode 100644
index 7f7afa9b..00000000
--- a/common/recipes-kernel/linux/files/1108-drm-amdgpu-fix-uvd-fini-mem-leak.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 8d08dbb0b24d54b199c0fa1b39232ae8b73155d4 Mon Sep 17 00:00:00 2001
-From: Monk Liu <Monk.Liu@amd.com>
-Date: Mon, 30 May 2016 15:13:59 +0800
-Subject: [PATCH 1108/1110] drm/amdgpu:fix uvd fini mem leak
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Change-Id: I970ff5639fd22464a494750956646296b932ba3c
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 20 ++++++++++----------
- 1 file changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 88a7942..efb07fe 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -244,11 +244,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- {
- 	int r;
--
--	if (adev->uvd.vcpu_bo == NULL)
--		return 0;
-+	
-+	kfree(adev->uvd.saved_bo);
-         amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
--
-+	
-+	if (adev->uvd.vcpu_bo) {
- 	r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
- 	if (!r) {
- 		amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
-@@ -257,7 +257,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- 	}
- 
- 	amdgpu_bo_unref(&adev->uvd.vcpu_bo);
--
-+    }
- 	amdgpu_ring_fini(&adev->uvd.ring);
- 
- 	release_firmware(adev->uvd.fw);
-@@ -280,8 +280,10 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
-  
-         if (i == AMDGPU_MAX_UVD_HANDLES)
-                 return 0;
--
--        size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-+	
-+	cancel_delayed_work_sync(&adev->uvd.idle_work);
-+        
-+	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-         ptr = adev->uvd.cpu_addr;
-         
- 	adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
-@@ -301,8 +303,6 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
- 	if (adev->uvd.vcpu_bo == NULL)
- 		return -EINVAL;
- 
--	cancel_delayed_work_sync(&adev->uvd.idle_work);
--
- 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
- 	ptr = adev->uvd.cpu_addr;
- 
-@@ -916,7 +916,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 
-                 amdgpu_job_free(job);
-         } else {
--                r = amdgpu_job_submit(job, ring, NULL,
-+                r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
-                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-                 if (r)
-                         goto err_free;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1109-drm-amdgpu-fix-system-randomly-reboots-after-login.patch b/common/recipes-kernel/linux/files/1109-drm-amdgpu-fix-system-randomly-reboots-after-login.patch
deleted file mode 100644
index 1ed8a0b7..00000000
--- a/common/recipes-kernel/linux/files/1109-drm-amdgpu-fix-system-randomly-reboots-after-login.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 3eecb0fe3cdece4ea4f3a5dedd523b25af8adf45 Mon Sep 17 00:00:00 2001
-From: Arindam Nath <arindam.nath@amd.com>
-Date: Mon, 25 Jul 2016 17:56:19 +0530
-Subject: [PATCH 1109/1110] drm/amdgpu: fix system randomly reboots after login
-
-Signed-off-by: Arindam Nath <arindam.nath@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 7f15c1a..f4027d6 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1543,7 +1543,6 @@ static int vi_common_early_init(void *handle)
-                                          AMDGPU_PG_SUPPORT_GFX_SMG |
-                                          AMDGPU_PG_SUPPORT_GFX_DMG |
-                                          AMDGPU_PG_SUPPORT_CP |
--                                         AMDGPU_PG_SUPPORT_RLC_SMU_HS |
-                                          AMDGPU_PG_SUPPORT_GFX_PIPELINE;
- 
- 		adev->external_rev_id = adev->rev_id + 0x1;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1110-drm-amdgpu-free-handles-after-fini-the-context.patch b/common/recipes-kernel/linux/files/1110-drm-amdgpu-free-handles-after-fini-the-context.patch
deleted file mode 100644
index bde05ee1..00000000
--- a/common/recipes-kernel/linux/files/1110-drm-amdgpu-free-handles-after-fini-the-context.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 43fe0c664e7de0663b8d8845e90887965f82df4f Mon Sep 17 00:00:00 2001
-From: Leo Liu <leo.liu@amd.com>
-Date: Fri, 22 Jul 2016 14:13:11 -0400
-Subject: [PATCH 1110/1110] drm/amdgpu: free handles after fini the context
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This will make sure all the submissions from different contexts gets
-finished, and then we close the session and free up the handles.
-
-This will fix the issue that session clean-up is not get done properly,
-when with the command `kill -9'
-
-Signed-off-by: Leo Liu <leo.liu@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index b6e9d81..d4e1e86 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -566,6 +566,9 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
- 
- 	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
- 
-+        amdgpu_uvd_free_handles(adev, file_priv);
-+        amdgpu_vce_free_handles(adev, file_priv);
-+
- 	amdgpu_vm_fini(adev, &fpriv->vm);
- 
- 	idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
-@@ -590,10 +593,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
- void amdgpu_driver_preclose_kms(struct drm_device *dev,
- 				struct drm_file *file_priv)
- {
--	struct amdgpu_device *adev = dev->dev_private;
--
--	amdgpu_uvd_free_handles(adev, file_priv);
--	amdgpu_vce_free_handles(adev, file_priv);
- }
- 
- /*
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1111-drm-amd-dal-return-page-flip-status-to-userspace.patch b/common/recipes-kernel/linux/files/1111-drm-amd-dal-return-page-flip-status-to-userspace.patch
deleted file mode 100644
index 3142c157..00000000
--- a/common/recipes-kernel/linux/files/1111-drm-amd-dal-return-page-flip-status-to-userspace.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 6e02d6ce89cdf62f20e71cc769b34687b722fc62 Mon Sep 17 00:00:00 2001
-From: Arindam Nath <arindam.nath@amd.com>
-Date: Thu, 18 Aug 2016 11:59:45 +0530
-Subject: [PATCH 01/12] drm/amd/dal: return page flip status to userspace
-
-We need to return the status of page flip operation back
-to userspace. This enables userspace to take corrective
-action when say, a pflip operation returns -EBUSY.
-
-This resolves the issue when mpv randomly hangs during
-playback at the very beginning itself.
-
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Harry Wentland <harry.wentland@amd.com>
-Signed-off-by: Arindam Nath <arindam.nath@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 20 ++++++++++++--------
- 1 file changed, 12 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-index 390c9b0..ab8bc4c 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
-@@ -2020,7 +2020,7 @@ int amdgpu_dm_atomic_commit(
- 	struct drm_plane *plane;
- 	struct drm_plane_state *old_plane_state;
- 	uint32_t i;
--	int32_t ret;
-+	int32_t ret = 0;
- 	uint32_t commit_targets_count = 0;
- 	uint32_t new_crtcs_count = 0;
- 	struct drm_crtc *crtc;
-@@ -2260,12 +2260,16 @@ int amdgpu_dm_atomic_commit(
- 			!crtc->state->active)
- 			continue;
- 
--		if (page_flip_needed(plane_state, old_plane_state))
--			amdgpu_crtc_page_flip(
--				crtc,
--				fb,
--				crtc->state->event,
--				0);
-+                if (page_flip_needed(plane_state, old_plane_state)) {
-+                        ret = amdgpu_crtc_page_flip(
-+                                                    crtc,
-+                                                    fb,
-+                                                    crtc->state->event,
-+                                                    0);
-+                        if (ret)
-+                                return ret;
-+                }
-+
- 	}
- 
- 	/* In this state all old framebuffers would be unpinned */
-@@ -2276,7 +2280,7 @@ int amdgpu_dm_atomic_commit(
- 
- 	drm_atomic_state_free(state);
- 
--	return 0;
-+	return ret;
- }
- /*
-  * This functions handle all cases when set mode does not come upon hotplug.
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1112-drm-amd-Indentation-of-the-code.patch b/common/recipes-kernel/linux/files/1112-drm-amd-Indentation-of-the-code.patch
deleted file mode 100644
index 96925ce7..00000000
--- a/common/recipes-kernel/linux/files/1112-drm-amd-Indentation-of-the-code.patch
+++ /dev/null
@@ -1,4870 +0,0 @@
-From 0389ba9b0eaa14b5f0e753e4208bc272072835ea Mon Sep 17 00:00:00 2001
-From: Kalyan Alle <kalyan.alle@amd.com>
-Date: Thu, 25 Aug 2016 11:59:45 +0530
-Subject: [PATCH 02/12] drm/amd: Indentation of the code
-
-Spaces are converted to tabs whereever necessary.
-
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h                | 361 ++++++++-------
- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c            |  18 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c   |   6 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c           |   4 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c        |  58 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c             | 506 ++++++++++-----------
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c         |  14 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c        |   3 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h            |   4 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c          |   2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c            |  34 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c             |  56 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c            | 231 +++++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c            |  10 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c         |  20 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c          |   2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c           |   6 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c            |  61 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c            | 140 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c            |  65 +--
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c             | 394 ++++++++--------
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c              |  14 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c              |  12 +-
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              | 406 ++++++++---------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c             |  14 +-
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c             |  14 +-
- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c              |  12 +-
- drivers/gpu/drm/amd/amdgpu/vi.c                    |  24 +-
- .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c    |   2 +
- drivers/gpu/drm/amd/dal/dc/core/dc.c               |   2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  11 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |   3 +-
- drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |   2 +-
- .../gpu/drm/amd/dal/modules/freesync/freesync.c    |  14 +-
- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     |   2 +-
- 35 files changed, 1270 insertions(+), 1257 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index c105e68..551f763 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -22,8 +22,8 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-  */
- #ifndef __AMDGPU_H__
- #define __AMDGPU_H__
-@@ -90,7 +90,7 @@ extern int amdgpu_powerplay;
- extern unsigned amdgpu_pcie_gen_cap;
- extern unsigned amdgpu_pcie_lane_cap;
- 
--#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
-+#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS		3000
- #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
- #define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
- /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
-@@ -112,7 +112,7 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define AMDGPU_VA_RESERVED_SIZE			(8 << 20)
- 
- /* hard reset data */
--#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
-+#define AMDGPU_ASIC_RESET_DATA			0x39d5e86b
- 
- /* reset flags */
- #define AMDGPU_RESET_GFX			(1 << 0)
-@@ -131,14 +131,14 @@ extern unsigned amdgpu_pcie_lane_cap;
- #define AMDGPU_RESET_VCE			(1 << 13)
- #define AMDGPU_RESET_VCE1			(1 << 14)
- 
--#define AMDGPU_PG_SUPPORT_GFX_QUICK_MG         (1 << 11)
--#define AMDGPU_PG_SUPPORT_GFX_PIPELINE         (1 << 12)
-+#define AMDGPU_PG_SUPPORT_GFX_QUICK_MG		(1 << 11)
-+#define AMDGPU_PG_SUPPORT_GFX_PIPELINE		(1 << 12)
- 
--#define AMDGPU_PG_SUPPORT_GFX_PG                (1 << 0)
--#define AMDGPU_PG_SUPPORT_GFX_SMG               (1 << 1)
--#define AMDGPU_PG_SUPPORT_GFX_DMG               (1 << 2)
--#define AMDGPU_PG_SUPPORT_CP                    (1 << 5)
--#define AMDGPU_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
-+#define AMDGPU_PG_SUPPORT_GFX_PG		(1 << 0)
-+#define AMDGPU_PG_SUPPORT_GFX_SMG		(1 << 1)
-+#define AMDGPU_PG_SUPPORT_GFX_DMG		(1 << 2)
-+#define AMDGPU_PG_SUPPORT_CP			(1 << 5)
-+#define AMDGPU_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
- 
- /* GFX current status */
- #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
-@@ -374,16 +374,16 @@ struct amdgpu_fence_driver {
- /* some special values for the owner field */
- #define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
- #define AMDGPU_FENCE_OWNER_VM		((void*)1ul)
--#define AMDGPU_CLIENT_ID_RESERVED       2
-+#define AMDGPU_CLIENT_ID_RESERVED	2
- 
--#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
--#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
-+#define AMDGPU_FENCE_FLAG_64BIT		(1 << 0)
-+#define AMDGPU_FENCE_FLAG_INT		(1 << 1)
- 
- struct amdgpu_user_fence {
- 	/* write-back bo */
--	struct amdgpu_bo 	*bo;
-+	struct amdgpu_bo	*bo;
- 	/* write-back address offset to bo start */
--	uint32_t                offset;
-+	uint32_t		offset;
- };
- 
- int amdgpu_fence_driver_init(struct amdgpu_device *adev);
-@@ -414,7 +414,7 @@ struct amdgpu_mman_lru {
- };
- 
- struct amdgpu_mman {
--	struct ttm_bo_global_ref        bo_global_ref;
-+	struct ttm_bo_global_ref	bo_global_ref;
- 	struct drm_global_reference	mem_global_ref;
- 	struct ttm_bo_device		bdev;
- 	bool				mem_global_referenced;
-@@ -428,11 +428,11 @@ struct amdgpu_mman {
- 	/* buffer handling */
- 	const struct amdgpu_buffer_funcs	*buffer_funcs;
- 	struct amdgpu_ring			*buffer_funcs_ring;
--        /* Scheduler entity for buffer moves */
--        struct amd_sched_entity                 entity;
-+	/* Scheduler entity for buffer moves */
-+	struct amd_sched_entity			entity;
- 
--        /* custom LRU management */
--        struct amdgpu_mman_lru                  log2_size[AMDGPU_TTM_LRU_SIZE];
-+	/* custom LRU management */
-+	struct amdgpu_mman_lru			log2_size[AMDGPU_TTM_LRU_SIZE];
- };
- 
- int amdgpu_copy_buffer(struct amdgpu_ring *ring,
-@@ -463,7 +463,7 @@ struct amdgpu_bo_va_mapping {
- struct amdgpu_bo_va {
- 	/* protected by bo being reserved */
- 	struct list_head		bo_list;
--	struct fence		        *last_pt_update;
-+	struct fence			*last_pt_update;
- 	unsigned			ref_count;
- 
- 	/* protected by vm mutex and spinlock */
-@@ -484,8 +484,8 @@ struct amdgpu_bo {
- 	/* Protected by gem.mutex */
- 	struct list_head		list;
- 	/* Protected by tbo.reserved */
--        u32                             prefered_domains;
--        u32                             allowed_domains;
-+	u32				prefered_domains;
-+	u32				allowed_domains;
- 	struct ttm_place		placements[AMDGPU_GEM_DOMAIN_MAX + 1];
- 	struct ttm_placement		placement;
- 	struct ttm_buffer_object	tbo;
-@@ -519,8 +519,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
- 				struct drm_file *file_priv);
- unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
- struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
--struct drm_gem_object *
--amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
-+struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
- 				 struct dma_buf_attachment *attach,
- 				 struct sg_table *sg);
- struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
-@@ -579,7 +578,7 @@ struct amdgpu_sa_bo {
- 	struct amdgpu_sa_manager	*manager;
- 	unsigned			soffset;
- 	unsigned			eoffset;
--	struct fence		        *fence;
-+	struct fence			*fence;
- };
- 
- /*
-@@ -602,7 +601,7 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp,
-  */
- struct amdgpu_sync {
- 	DECLARE_HASHTABLE(fences, 4);
--	struct fence	        *last_vm_update;
-+	struct fence		*last_vm_update;
- };
- 
- void amdgpu_sync_create(struct amdgpu_sync *sync);
-@@ -614,7 +613,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     void *owner);
- bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);
- int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
--                            struct fence *fence);
-+			     struct fence *fence);
- struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
- int amdgpu_sync_wait(struct amdgpu_sync *sync);
- void amdgpu_sync_free(struct amdgpu_sync *sync);
-@@ -678,10 +677,10 @@ struct amdgpu_mc {
- 	unsigned		vram_width;
- 	u64			real_vram_size;
- 	int			vram_mtrr;
--	u64                     gtt_base_align;
--	u64                     mc_mask;
--	const struct firmware   *fw;	/* MC firmware */
--	uint32_t                fw_version;
-+	u64			gtt_base_align;
-+	u64			mc_mask;
-+	const struct firmware	*fw;	/* MC firmware */
-+	uint32_t		fw_version;
- 	struct amdgpu_irq_src	vm_fault;
- 	uint32_t		vram_type;
- };
-@@ -691,23 +690,23 @@ struct amdgpu_mc {
-  */
- typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
- {
--	AMDGPU_DOORBELL_KIQ                     = 0x000,
--	AMDGPU_DOORBELL_HIQ                     = 0x001,
--	AMDGPU_DOORBELL_DIQ                     = 0x002,
--	AMDGPU_DOORBELL_MEC_RING0               = 0x010,
--	AMDGPU_DOORBELL_MEC_RING1               = 0x011,
--	AMDGPU_DOORBELL_MEC_RING2               = 0x012,
--	AMDGPU_DOORBELL_MEC_RING3               = 0x013,
--	AMDGPU_DOORBELL_MEC_RING4               = 0x014,
--	AMDGPU_DOORBELL_MEC_RING5               = 0x015,
--	AMDGPU_DOORBELL_MEC_RING6               = 0x016,
--	AMDGPU_DOORBELL_MEC_RING7               = 0x017,
--	AMDGPU_DOORBELL_GFX_RING0               = 0x020,
--	AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
--	AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
--	AMDGPU_DOORBELL_IH                      = 0x1E8,
--	AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
--	AMDGPU_DOORBELL_INVALID                 = 0xFFFF
-+	AMDGPU_DOORBELL_KIQ			= 0x000,
-+	AMDGPU_DOORBELL_HIQ			= 0x001,
-+	AMDGPU_DOORBELL_DIQ			= 0x002,
-+	AMDGPU_DOORBELL_MEC_RING0		= 0x010,
-+	AMDGPU_DOORBELL_MEC_RING1		= 0x011,
-+	AMDGPU_DOORBELL_MEC_RING2		= 0x012,
-+	AMDGPU_DOORBELL_MEC_RING3		= 0x013,
-+	AMDGPU_DOORBELL_MEC_RING4		= 0x014,
-+	AMDGPU_DOORBELL_MEC_RING5		= 0x015,
-+	AMDGPU_DOORBELL_MEC_RING6		= 0x016,
-+	AMDGPU_DOORBELL_MEC_RING7		= 0x017,
-+	AMDGPU_DOORBELL_GFX_RING0		= 0x020,
-+	AMDGPU_DOORBELL_sDMA_ENGINE0		= 0x1E0,
-+	AMDGPU_DOORBELL_sDMA_ENGINE1		= 0x1E1,
-+	AMDGPU_DOORBELL_IH			= 0x1E8,
-+	AMDGPU_DOORBELL_MAX_ASSIGNMENT		= 0x3FF,
-+	AMDGPU_DOORBELL_INVALID			= 0xFFFF
- } AMDGPU_DOORBELL_ASSIGNMENT;
- 
- struct amdgpu_doorbell {
-@@ -751,9 +750,9 @@ struct amdgpu_ib {
- 	uint32_t			length_dw;
- 	uint64_t			gpu_addr;
- 	uint32_t			*ptr;
--	struct amdgpu_user_fence        *user;
--        unsigned                        vm_id;
--        uint64_t                        vm_pd_addr;
-+	struct amdgpu_user_fence	*user;
-+	unsigned			vm_id;
-+	uint64_t			vm_pd_addr;
- 	uint32_t			gds_base, gds_size;
- 	uint32_t			gws_base, gws_size;
- 	uint32_t			oa_base, oa_size;
-@@ -772,24 +771,24 @@ enum amdgpu_ring_type {
- 
- extern const struct amd_sched_backend_ops amdgpu_sched_ops;
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--                      struct amdgpu_job **job, struct amdgpu_vm *vm);
-+		     struct amdgpu_job **job, struct amdgpu_vm *vm);
- int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
--                      struct amdgpu_job **job);
-+			     struct amdgpu_job **job);
- 
- void amdgpu_job_free(struct amdgpu_job *job);
- void amdgpu_job_free_func(struct kref *refcount);
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
--                      struct amd_sched_entity *entity, void *owner,
--                      struct fence **f);
-+		      struct amd_sched_entity *entity, void *owner,
-+		      struct fence **f);
- void amdgpu_job_timeout_func(struct work_struct *work);
- 
- struct amdgpu_ring {
- 	struct amdgpu_device		*adev;
- 	const struct amdgpu_ring_funcs	*funcs;
- 	struct amdgpu_fence_driver	fence_drv;
--	struct amd_gpu_scheduler 	sched;
-+	struct amd_gpu_scheduler	sched;
- 
--	spinlock_t              fence_lock;
-+	spinlock_t		fence_lock;
- 	struct amdgpu_bo	*ring_obj;
- 	volatile uint32_t	*ring;
- 	unsigned		rptr_offs;
-@@ -815,7 +814,7 @@ struct amdgpu_ring {
- 	unsigned		wptr_offs;
- 	unsigned		next_rptr_offs;
- 	unsigned		fence_offs;
--	uint64_t last_fence_context;
-+	uint64_t 		last_fence_context;
- 	enum amdgpu_ring_type	type;
- 	char			name[16];
- 	unsigned		cond_exe_offs;
-@@ -859,9 +858,8 @@ struct amdgpu_ring {
- #define AMDGPU_VM_FAULT_STOP_ALWAYS	2
- 
- struct amdgpu_vm_pt {
--        struct amdgpu_bo_list_entry     entry;
--        uint64_t                        addr;
--
-+	struct amdgpu_bo_list_entry	entry;
-+	uint64_t			addr;
- };
- 
- struct amdgpu_vm {
-@@ -889,36 +887,36 @@ struct amdgpu_vm {
- 	struct amdgpu_vm_pt	*page_tables;
- 
- 	/* for id and flush management per ring */
--        struct amdgpu_vm_id     *ids[AMDGPU_MAX_RINGS];
-+	struct amdgpu_vm_id	*ids[AMDGPU_MAX_RINGS];
- 
- 	/* protecting freed */
- 	spinlock_t		freed_lock;
- 
--        /* Scheduler entity for page table updates */
--        struct amd_sched_entity entity;
-+	/* Scheduler entity for page table updates */
-+	struct amd_sched_entity entity;
-  
--        /* client id */
--        u64                     client_id;
-+	/* client id */
-+	u64			client_id;
- };
- 
- struct amdgpu_vm_id {
- 	struct list_head	list;
--        struct fence            *first;
--        struct amdgpu_sync      active;
--        struct fence            *last_flush;
--        struct amdgpu_ring      *last_user;
--        atomic64_t              owner;
-+	struct fence		*first;
-+	struct amdgpu_sync	active;
-+	struct fence		*last_flush;
-+	struct amdgpu_ring	*last_user;
-+	atomic64_t		owner;
- 
--        uint64_t                pd_gpu_addr;
--        /* last flushed PD/PT update */
--        struct fence            *flushed_updates;
-+	uint64_t		pd_gpu_addr;
-+	/* last flushed PD/PT update */
-+	struct fence		*flushed_updates;
- 
--        uint32_t                gds_base;
--        uint32_t                gds_size;
--        uint32_t                gws_base;
--        uint32_t                gws_size;
--        uint32_t                oa_base;
--        uint32_t                oa_size;
-+	uint32_t		gds_base;
-+	uint32_t		gds_size;
-+	uint32_t		gws_base;
-+	uint32_t		gws_size;
-+	uint32_t		oa_base;
-+	uint32_t		oa_size;
- };
- 
- struct amdgpu_vm_manager {
-@@ -926,7 +924,7 @@ struct amdgpu_vm_manager {
- 	struct mutex				lock;
- 	unsigned				num_ids;
- 	struct list_head			ids_lru;
--        struct amdgpu_vm_id                     ids[AMDGPU_NUM_VM];
-+	struct amdgpu_vm_id			ids[AMDGPU_NUM_VM];
- 
- 	uint32_t				max_pfn;
- 	/* vram base address for page table entry  */
-@@ -934,12 +932,12 @@ struct amdgpu_vm_manager {
- 	/* is vm enabled? */
- 	bool					enabled;
- 	/* vm pte handling */
--	const struct amdgpu_vm_pte_funcs        *vm_pte_funcs;
--        struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];
--        unsigned                                vm_pte_num_rings;
--        atomic_t                                vm_pte_next_ring;
--        /* client id counter */
--        atomic64_t                              client_counter;
-+	const struct amdgpu_vm_pte_funcs	*vm_pte_funcs;
-+	struct amdgpu_ring			*vm_pte_rings[AMDGPU_MAX_RINGS];
-+	unsigned				vm_pte_num_rings;
-+	atomic_t				vm_pte_next_ring;
-+	/* client id counter */
-+	atomic64_t				client_counter;
- };
- 
- void amdgpu_vm_manager_init(struct amdgpu_device *adev);
-@@ -947,23 +945,23 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
--                                               struct amdgpu_vm *vm,
--                                               struct list_head *validated,
--                                               struct list_head *duplicates);
-+					       struct amdgpu_vm *vm,
-+					       struct list_head *validated,
-+					       struct list_head *duplicates);
- void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
--                         struct list_head *validated,
--                         struct amdgpu_bo_list_entry *entry);
-+			 struct list_head *validated,
-+			 struct amdgpu_bo_list_entry *entry);
- void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
- void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
--                                  struct amdgpu_vm *vm);
-+				  struct amdgpu_vm *vm);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
--                      struct amdgpu_sync *sync, struct fence *fence,
--                      unsigned *vm_id, uint64_t *vm_pd_addr);
-+		      struct amdgpu_sync *sync, struct fence *fence,
-+		      unsigned *vm_id, uint64_t *vm_pd_addr);
- int amdgpu_vm_flush(struct amdgpu_ring *ring,
--                    unsigned vm_id, uint64_t pd_addr,
--                    uint32_t gds_base, uint32_t gds_size,
--                    uint32_t gws_base, uint32_t gws_size,
--                    uint32_t oa_base, uint32_t oa_size);
-+		    unsigned vm_id, uint64_t pd_addr,
-+		    uint32_t gds_base, uint32_t gds_size,
-+		    uint32_t gws_base, uint32_t gws_size,
-+		    uint32_t oa_base, uint32_t oa_size);
- void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
- uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-@@ -1000,17 +998,16 @@ struct amdgpu_ctx_ring {
- 	uint64_t		sequence;
- 	struct fence		**fences;
- 	struct amd_sched_entity	entity;
--
- 	/* client id */
--	u64                     client_id;
-+	u64			client_id;
- };
- 
- struct amdgpu_ctx {
- 	struct kref		refcount;
--	struct amdgpu_device    *adev;
-+	struct amdgpu_device	*adev;
- 	unsigned		reset_counter;
- 	spinlock_t		ring_lock;
--	struct fence            **fences;
-+	struct fence		**fences;
- 	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];
- };
- 
-@@ -1055,7 +1052,7 @@ struct amdgpu_bo_list {
- 	struct amdgpu_bo *gds_obj;
- 	struct amdgpu_bo *gws_obj;
- 	struct amdgpu_bo *oa_obj;
--        unsigned first_userptr;
-+	unsigned first_userptr;
- 	unsigned num_entries;
- 	struct amdgpu_bo_list_entry *array;
- };
-@@ -1080,19 +1077,19 @@ struct amdgpu_rlc {
- 	struct amdgpu_bo	*save_restore_obj;
- 	uint64_t		save_restore_gpu_addr;
- 	volatile uint32_t	*sr_ptr;
--	const u32               *reg_list;
--	u32                     reg_list_size;
-+	const u32		*reg_list;
-+	u32			reg_list_size;
- 	/* for clear state */
- 	struct amdgpu_bo	*clear_state_obj;
- 	uint64_t		clear_state_gpu_addr;
- 	volatile uint32_t	*cs_ptr;
- 	const struct cs_section_def   *cs_data;
--	u32                     clear_state_size;
-+	u32			clear_state_size;
- 	/* for cp tables */
- 	struct amdgpu_bo	*cp_table_obj;
- 	uint64_t		cp_table_gpu_addr;
- 	volatile uint32_t	*cp_table_ptr;
--	u32                     cp_table_size;
-+	u32			cp_table_size;
- 
- 	/* safe mode for updating CG/PG state */
- 	bool in_safe_mode;
-@@ -1126,7 +1123,7 @@ struct amdgpu_mec {
-  */
- struct amdgpu_scratch {
- 	unsigned		num_reg;
--	uint32_t                reg_base;
-+	uint32_t		reg_base;
- 	bool			free[32];
- 	uint32_t		reg[32];
- };
-@@ -1196,18 +1193,18 @@ struct amdgpu_gfx {
- 	struct amdgpu_irq_src		priv_reg_irq;
- 	struct amdgpu_irq_src		priv_inst_irq;
- 	/* gfx status */
--	uint32_t gfx_current_status;
-+	uint32_t			gfx_current_status;
- 	/* ce ram size*/
--	unsigned ce_ram_size;
-+	unsigned			ce_ram_size;
- };
- 
- int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 		  unsigned size, struct amdgpu_ib *ib);
- void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
--                    struct fence *f);
-+		    struct fence *f);
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
--                       struct amdgpu_ib *ib, struct fence *last_vm_update,
--                       struct amdgpu_job *job, struct fence **f);
-+		       struct amdgpu_ib *ib, struct fence *last_vm_update,
-+		       struct amdgpu_job *job, struct fence **f);
- int amdgpu_ib_pool_init(struct amdgpu_device *adev);
- void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
- int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
-@@ -1244,34 +1241,34 @@ struct amdgpu_cs_parser {
- 	unsigned		nchunks;
- 	struct amdgpu_cs_chunk	*chunks;
- 
--       /* scheduler job object */
--        struct amdgpu_job       *job;
-+	/* scheduler job object */
-+	struct amdgpu_job	*job;
-  
--       /* buffer objects */
--         struct ww_acquire_ctx           ticket;
--         struct amdgpu_bo_list           *bo_list;
--         struct amdgpu_bo_list_entry     vm_pd;
--         struct list_head                validated;
--         struct fence                    *fence;
--         uint64_t                        bytes_moved_threshold;
--         uint64_t                        bytes_moved;
-+	/* buffer objects */
-+	struct ww_acquire_ctx		ticket;
-+	struct amdgpu_bo_list		*bo_list;
-+	struct amdgpu_bo_list_entry	vm_pd;
-+	struct list_head		validated;
-+	struct fence			*fence;
-+	uint64_t			bytes_moved_threshold;
-+	uint64_t			bytes_moved;
- 
- 	/* user fence */
- 	struct amdgpu_bo_list_entry	uf_entry;
- };
- 
- struct amdgpu_job {
--	struct amd_sched_job    base;
-+	struct amd_sched_job	base;
- 	struct amdgpu_device	*adev;
--        struct amdgpu_vm        *vm;
--        struct amdgpu_ring      *ring;
--        struct amdgpu_sync      sync;
-+	struct amdgpu_vm	*vm;
-+	struct amdgpu_ring	*ring;
-+	struct amdgpu_sync	sync;
- 	struct amdgpu_ib	*ibs;
--        struct fence            *fence; /* the hw fence */
-+	struct fence		*fence; /* the hw fence */
- 	uint32_t		num_ibs;
- 	void			*owner;
--        uint64_t                        fence_context;
--	struct amdgpu_user_fence uf;
-+	uint64_t		fence_context;
-+	struct amdgpu_user_fence	 uf;
- };
- #define to_amdgpu_job(sched_job)		\
- 		container_of((sched_job), struct amdgpu_job, base)
-@@ -1279,14 +1276,14 @@ struct amdgpu_job {
- static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
- 				      uint32_t ib_idx, int idx)
- {
--        return p->job->ibs[ib_idx].ptr[idx];
-+	return p->job->ibs[ib_idx].ptr[idx];
- }
- 
- static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
- 				       uint32_t ib_idx, int idx,
- 				       uint32_t value)
- {
--        p->job->ibs[ib_idx].ptr[idx] = value;
-+	p->job->ibs[ib_idx].ptr[idx] = value;
- }
- 
- /*
-@@ -1339,8 +1336,8 @@ enum amdgpu_dpm_event_src {
- #define AMDGPU_MAX_VCE_LEVELS 6
- 
- enum amdgpu_vce_level {
--	AMDGPU_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
--	AMDGPU_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
-+	AMDGPU_VCE_LEVEL_AC_ALL = 0,	 /* AC, All cases */
-+	AMDGPU_VCE_LEVEL_DC_EE = 1,	 /* DC, entropy encoding */
- 	AMDGPU_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
- 	AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
- 	AMDGPU_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
-@@ -1367,11 +1364,11 @@ struct amdgpu_dpm_thermal {
- 	/* thermal interrupt work */
- 	struct work_struct work;
- 	/* low temperature threshold */
--	int                min_temp;
-+	int		   min_temp;
- 	/* high temperature threshold */
--	int                max_temp;
-+	int		   max_temp;
- 	/* was last interrupt low to high or high to low */
--	bool               high_to_low;
-+	bool		   high_to_low;
- 	/* interrupt source */
- 	struct amdgpu_irq_src	irq;
- };
-@@ -1574,26 +1571,26 @@ struct amdgpu_dpm_funcs {
- };
- 
- struct amdgpu_dpm {
--	struct amdgpu_ps        *ps;
-+	struct amdgpu_ps	*ps;
- 	/* number of valid power states */
--	int                     num_ps;
-+	int			num_ps;
- 	/* current power state that is active */
--	struct amdgpu_ps        *current_ps;
-+	struct amdgpu_ps	*current_ps;
- 	/* requested power state */
--	struct amdgpu_ps        *requested_ps;
-+	struct amdgpu_ps	*requested_ps;
- 	/* boot up power state */
--	struct amdgpu_ps        *boot_ps;
-+	struct amdgpu_ps	*boot_ps;
- 	/* default uvd power state */
--	struct amdgpu_ps        *uvd_ps;
-+	struct amdgpu_ps	*uvd_ps;
- 	/* vce requirements */
- 	struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
- 	enum amdgpu_vce_level vce_level;
- 	enum amd_pm_state_type state;
- 	enum amd_pm_state_type user_state;
--	u32                     platform_caps;
--	u32                     voltage_response_time;
--	u32                     backbias_response_time;
--	void                    *priv;
-+	u32			platform_caps;
-+	u32			voltage_response_time;
-+	u32			backbias_response_time;
-+	void			*priv;
- 	u32			new_active_crtcs;
- 	int			new_active_crtc_count;
- 	u32			current_active_crtcs;
-@@ -1611,9 +1608,9 @@ struct amdgpu_dpm {
- 	bool power_control;
- 	bool ac_power;
- 	/* special states active */
--	bool                    thermal_active;
--	bool                    uvd_active;
--	bool                    vce_active;
-+	bool			thermal_active;
-+	bool			uvd_active;
-+	bool			vce_active;
- 	/* thermal handling */
- 	struct amdgpu_dpm_thermal thermal;
- 	/* forced levels */
-@@ -1622,28 +1619,28 @@ struct amdgpu_dpm {
- 
- struct amdgpu_pm {
- 	struct mutex		mutex;
--	u32                     current_sclk;
--	u32                     current_mclk;
--	u32                     default_sclk;
--	u32                     default_mclk;
-+	u32			current_sclk;
-+	u32			current_mclk;
-+	u32			default_sclk;
-+	u32			default_mclk;
- 	struct amdgpu_i2c_chan *i2c_bus;
- 	/* internal thermal controller on rv6xx+ */
- 	enum amdgpu_int_thermal_type int_thermal_type;
--	struct device	        *int_hwmon_dev;
-+	struct device		*int_hwmon_dev;
- 	/* fan control parameters */
--	bool                    no_fan;
--	u8                      fan_pulses_per_revolution;
--	u8                      fan_min_rpm;
--	u8                      fan_max_rpm;
-+	bool			no_fan;
-+	u8			fan_pulses_per_revolution;
-+	u8			fan_min_rpm;
-+	u8			fan_max_rpm;
- 	/* dpm */
--	bool                    dpm_enabled;
--	bool                    sysfs_initialized;
--	struct amdgpu_dpm       dpm;
-+	bool			dpm_enabled;
-+	bool			sysfs_initialized;
-+	struct amdgpu_dpm	dpm;
- 	const struct firmware	*fw;	/* SMC firmware */
--	uint32_t                fw_version;
-+	uint32_t		fw_version;
- 	const struct amdgpu_dpm_funcs *funcs;
--	uint32_t                pcie_gen_mask;
--	uint32_t                pcie_mlw_mask;
-+	uint32_t		pcie_gen_mask;
-+	uint32_t		pcie_mlw_mask;
- 	struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
- };
- 
-@@ -1653,19 +1650,19 @@ void amdgpu_get_pcie_info(struct amdgpu_device *adev);
-  * UVD
-  */
- #define AMDGPU_DEFAULT_UVD_HANDLES     10
--#define AMDGPU_MAX_UVD_HANDLES         40
--#define AMDGPU_UVD_STACK_SIZE          (200*1024)
--#define AMDGPU_UVD_HEAP_SIZE           (256*1024)
--#define AMDGPU_UVD_SESSION_SIZE                (50*1024)
-+#define AMDGPU_MAX_UVD_HANDLES	       40
-+#define AMDGPU_UVD_STACK_SIZE	       (200*1024)
-+#define AMDGPU_UVD_HEAP_SIZE	       (256*1024)
-+#define AMDGPU_UVD_SESSION_SIZE		       (50*1024)
- #define AMDGPU_UVD_FIRMWARE_OFFSET     256
- 
- struct amdgpu_uvd {
- 	struct amdgpu_bo	*vcpu_bo;
- 	void			*cpu_addr;
- 	uint64_t		gpu_addr;
--        void                    *saved_bo;
--        unsigned                max_handles;
- 	unsigned		fw_version;
-+	void			*saved_bo;
-+	unsigned		max_handles;
- 	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
- 	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
- 	struct delayed_work	idle_work;
-@@ -1673,7 +1670,7 @@ struct amdgpu_uvd {
- 	struct amdgpu_ring	ring;
- 	struct amdgpu_irq_src	irq;
- 	bool			address_64_bit;
--        struct amd_sched_entity entity;
-+	struct amd_sched_entity entity;
- };
- 
- /*
-@@ -1718,7 +1715,7 @@ struct amdgpu_sdma {
- 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
- 	struct amdgpu_irq_src	trap_irq;
- 	struct amdgpu_irq_src	illegal_inst_irq;
--	int 			num_instances;
-+	int			num_instances;
- };
- 
- /*
-@@ -1975,11 +1972,11 @@ struct amdgpu_device {
- 	bool				shutdown;
- 	bool				need_dma32;
- 	bool				accel_working;
--	struct work_struct 		reset_work;
-+	struct work_struct		reset_work;
- 	struct notifier_block		acpi_nb;
- 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
- 	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
--	unsigned 			debugfs_count;
-+	unsigned			debugfs_count;
- #if defined(CONFIG_DEBUG_FS)
- 	struct dentry			*debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
- #endif
-@@ -1987,7 +1984,7 @@ struct amdgpu_device {
- 	struct amdgpu_atcs		atcs;
- 	struct mutex			srbm_mutex;
- 	/* GRBM index mutex. Protects concurrent access to GRBM index */
--	struct mutex                    grbm_idx_mutex;
-+	struct mutex			grbm_idx_mutex;
- 	struct dev_pm_domain		vga_pm_domain;
- 	bool				have_disp_power_ref;
- 
-@@ -2023,12 +2020,12 @@ struct amdgpu_device {
- 	spinlock_t audio_endpt_idx_lock;
- 	amdgpu_block_rreg_t		audio_endpt_rreg;
- 	amdgpu_block_wreg_t		audio_endpt_wreg;
--	void __iomem                    *rio_mem;
-+	void __iomem			*rio_mem;
- 	resource_size_t			rio_mem_size;
- 	struct amdgpu_doorbell		doorbell;
- 
- 	/* clock/pll info */
--	struct amdgpu_clock            clock;
-+	struct amdgpu_clock	       clock;
- 
- 	/* MC */
- 	struct amdgpu_mc		mc;
-@@ -2110,7 +2107,7 @@ struct amdgpu_device {
- 	u64 gart_pin_size;
- 
- 	/* amdkfd interface */
--	struct kfd_dev          *kfd;
-+	struct kfd_dev		*kfd;
- 
- 	struct amdgpu_virtualization virtualization;
- };
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-index 252edba..043ba60 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
-@@ -35,17 +35,17 @@
- 
- #include "acp_gfx_if.h"
- 
--#define ACP_TILE_ON_MASK                0x03
--#define ACP_TILE_OFF_MASK               0x02
--#define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
--#define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
-+#define ACP_TILE_ON_MASK		0x03
-+#define ACP_TILE_OFF_MASK		0x02
-+#define ACP_TILE_ON_RETAIN_REG_MASK	0x1f
-+#define ACP_TILE_OFF_RETAIN_REG_MASK	0x20
- 
--#define ACP_TILE_P1_MASK                0x3e
--#define ACP_TILE_P2_MASK                0x3d
--#define ACP_TILE_DSP0_MASK              0x3b
--#define ACP_TILE_DSP1_MASK              0x37
-+#define ACP_TILE_P1_MASK		0x3e
-+#define ACP_TILE_P2_MASK		0x3d
-+#define ACP_TILE_DSP0_MASK		0x3b
-+#define ACP_TILE_DSP1_MASK		0x37
- 
--#define ACP_TILE_DSP2_MASK              0x2f
-+#define ACP_TILE_DSP2_MASK		0x2f
- 
- #define ACP_DMA_REGS_END		0x146c0
- #define ACP_I2S_PLAY_REGS_START		0x14840
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-index 45d93bb..8162152 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
-@@ -28,7 +28,7 @@ struct amdgpu_atpx_functions {
- struct amdgpu_atpx {
- 	acpi_handle handle;
- 	struct amdgpu_atpx_functions functions;
--        bool is_hybrid;
-+	bool is_hybrid;
- };
- 
- static struct amdgpu_atpx_priv {
-@@ -65,11 +65,11 @@ bool amdgpu_has_atpx(void) {
- 	return amdgpu_atpx_priv.atpx_detected;
- }
- bool amdgpu_has_atpx_dgpu_power_cntl(void) {
--         return amdgpu_atpx_priv.atpx.functions.power_cntl;
-+	return amdgpu_atpx_priv.atpx.functions.power_cntl;
- }
- 
- bool amdgpu_is_atpx_hybrid(void) {
--         return amdgpu_atpx_priv.atpx.is_hybrid;
-+	return amdgpu_atpx_priv.atpx.is_hybrid;
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-index 99ca75b..4c803ed 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-@@ -22,8 +22,8 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-  */
- #include <drm/drmP.h>
- #include "amdgpu.h"
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-index db36de6..35d0856 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
-@@ -91,7 +91,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo;
- 	struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo;
- 
--        unsigned last_entry = 0, first_userptr = num_entries;
-+	unsigned last_entry = 0, first_userptr = num_entries;
- 	unsigned i;
- 	int r;
- 
-@@ -101,43 +101,43 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));
- 
- 	for (i = 0; i < num_entries; ++i) {
--                struct amdgpu_bo_list_entry *entry;
-+		struct amdgpu_bo_list_entry *entry;
- 		struct drm_gem_object *gobj;
--                struct amdgpu_bo *bo;
--                struct mm_struct *usermm;
-+		struct amdgpu_bo *bo;
-+		struct mm_struct *usermm;
- 
- 		gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
--                if (!gobj) {
--                        r = -ENOENT;
-+		if (!gobj) {
-+			r = -ENOENT;
- 			goto error_free;
--                }
-+		}
- 
--                bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
-+		bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
- 		drm_gem_object_unreference_unlocked(gobj);
- 
--                usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
--                if (usermm) {
--                        if (usermm != current->mm) {
--                                amdgpu_bo_unref(&bo);
--                                r = -EPERM;
--                                goto error_free;
--                        }
--                        entry = &array[--first_userptr];
--                } else {
--                        entry = &array[last_entry++];
--                }
--                
-+		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
-+		if (usermm) {
-+			if (usermm != current->mm) {
-+				amdgpu_bo_unref(&bo);
-+				r = -EPERM;
-+				goto error_free;
-+			}
-+			entry = &array[--first_userptr];
-+		} else {
-+			entry = &array[last_entry++];
-+		}
-+
- 		entry->robj = bo;
--                entry->priority = min(info[i].bo_priority,
--                                      AMDGPU_BO_LIST_MAX_PRIORITY);
-+		entry->priority = min(info[i].bo_priority,
-+				      AMDGPU_BO_LIST_MAX_PRIORITY);
- 		entry->tv.bo = &entry->robj->tbo;
- 		entry->tv.shared = true;
- 
--                if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
-+		if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
- 			gds_obj = entry->robj;
--                if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GWS)
-+		if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GWS)
- 			gws_obj = entry->robj;
--                if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_OA)
-+		if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_OA)
- 			oa_obj = entry->robj;
- 
- 		trace_amdgpu_bo_list_set(list, entry->robj);
-@@ -151,17 +151,17 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
- 	list->gds_obj = gds_obj;
- 	list->gws_obj = gws_obj;
- 	list->oa_obj = oa_obj;
--        list->first_userptr = first_userptr;
-+	list->first_userptr = first_userptr;
- 	list->array = array;
- 	list->num_entries = num_entries;
- 
- 	return 0;
- 
- error_free:
--        while (i--)
--                amdgpu_bo_unref(&array[i].robj);
-+	while (i--)
-+		amdgpu_bo_unref(&array[i].robj);
- 	drm_free_large(array);
--        return r;
-+	return r;
- }
- 
- struct amdgpu_bo_list *
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index bff83e6..f983846 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -30,45 +30,45 @@
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
--#define AMDGPU_CS_MAX_PRIORITY         32u
--#define AMDGPU_CS_NUM_BUCKETS          (AMDGPU_CS_MAX_PRIORITY + 1)
-+#define AMDGPU_CS_MAX_PRIORITY		32u
-+#define AMDGPU_CS_NUM_BUCKETS		(AMDGPU_CS_MAX_PRIORITY + 1)
- 
- /* This is based on the bucket sort with O(n) time complexity.
-  * An item with priority "i" is added to bucket[i]. The lists are then
-  * concatenated in descending order.
-  */
- struct amdgpu_cs_buckets {
--       struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
-+	struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
- };
- 
- static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
- {
--       unsigned i;
-+	unsigned i;
- 
--       for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
--               INIT_LIST_HEAD(&b->bucket[i]);
-+	for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
-+		INIT_LIST_HEAD(&b->bucket[i]);
- }
- 
- static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
--                                 struct list_head *item, unsigned priority)
-+				  struct list_head *item, unsigned priority)
- {
--       /* Since buffers which appear sooner in the relocation list are
--        * likely to be used more often than buffers which appear later
--        * in the list, the sort mustn't change the ordering of buffers
--        * with the same priority, i.e. it must be stable.
--        */
--       list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
-+	/* Since buffers which appear sooner in the relocation list are
-+	 * likely to be used more often than buffers which appear later
-+	 * in the list, the sort mustn't change the ordering of buffers
-+	 * with the same priority, i.e. it must be stable.
-+	 */
-+	list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
- }
- 
- static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
--                                      struct list_head *out_list)
-+				       struct list_head *out_list)
- {
--       unsigned i;
-+	unsigned i;
- 
--       /* Connect the sorted buckets in the output list. */
--       for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
--               list_splice(&b->bucket[i], out_list);
--       }
-+	/* Connect the sorted buckets in the output list. */
-+	for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
-+		list_splice(&b->bucket[i], out_list);
-+	}
- }
- 
- int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
-@@ -128,7 +128,7 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
- }
- 
- static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
--                                      struct amdgpu_user_fence *uf,
-+				      struct amdgpu_user_fence *uf,
- 				      struct drm_amdgpu_cs_chunk_fence *fence_data)
- {
- 	struct drm_gem_object *gobj;
-@@ -140,19 +140,19 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 	if (gobj == NULL)
- 		return -EINVAL;
- 
--        uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
--        uf->offset = fence_data->offset;
-+	uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
-+	uf->offset = fence_data->offset;
- 
--        if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) {
-+	if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) {
- 		drm_gem_object_unreference_unlocked(gobj);
- 		return -EINVAL;
- 	}
- 
--        p->uf_entry.robj = amdgpu_bo_ref(uf->bo);
-+	p->uf_entry.robj = amdgpu_bo_ref(uf->bo);
- 	p->uf_entry.priority = 0;
- 	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
- 	p->uf_entry.tv.shared = true;
--        p->uf_entry.user_pages = NULL;
-+	p->uf_entry.user_pages = NULL;
- 
- 	drm_gem_object_unreference_unlocked(gobj);
- 	return 0;
-@@ -160,12 +160,12 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
- 
- int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- {
--        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
--        struct amdgpu_vm *vm = &fpriv->vm;
-+	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-+	struct amdgpu_vm *vm = &fpriv->vm;
- 	union drm_amdgpu_cs *cs = data;
- 	uint64_t *chunk_array_user;
- 	uint64_t *chunk_array;
--        struct amdgpu_user_fence uf = {};
-+	struct amdgpu_user_fence uf = {};
- 	unsigned size, num_ibs = 0;
- 	int i;
- 	int ret;
-@@ -183,15 +183,15 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		goto free_chunk;
- 	}
-  
--        p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
-+	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
- 
- 	/* get chunks */
--        INIT_LIST_HEAD(&p->validated);
-+	INIT_LIST_HEAD(&p->validated);
- 	chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
- 	if (copy_from_user(chunk_array, chunk_array_user,
- 			   sizeof(uint64_t)*cs->in.num_chunks)) {
- 		ret = -EFAULT;
--                goto put_bo_list;
-+		goto put_bo_list;
- 	}
- 
- 	p->nchunks = cs->in.num_chunks;
-@@ -199,7 +199,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 			    GFP_KERNEL);
- 	if (!p->chunks) {
- 		ret = -ENOMEM;
--                goto put_bo_list;
-+		goto put_bo_list;
- 	}
- 
- 	for (i = 0; i < p->nchunks; i++) {
-@@ -244,7 +244,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 				goto free_partial_kdata;
- 			}
- 
--                        ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata);
-+			ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata);
- 			if (ret)
- 				goto free_partial_kdata;
- 
-@@ -259,11 +259,11 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
- 		}
- 	}
- 
--        ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
--        if (ret)
--                goto free_all_kdata;
-+	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
-+	if (ret)
-+		goto free_all_kdata;
- 
--        p->job->uf = uf;
-+	p->job->uf = uf;
- 
- 	kfree(chunk_array);
- 	return 0;
-@@ -276,7 +276,7 @@ free_partial_kdata:
- 	kfree(p->chunks);
- put_bo_list:
-        if (p->bo_list)
--               amdgpu_bo_list_put(p->bo_list);
-+	       amdgpu_bo_list_put(p->bo_list);
- 	amdgpu_ctx_put(p->ctx);
- free_chunk:
- 	kfree(chunk_array);
-@@ -301,18 +301,18 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
- 	 *
- 	 * - From 0 to one half of used VRAM, the threshold decreases
- 	 *   linearly.
--	 *         __________________
--	 * 1/4 of -|\               |
--	 * VRAM    | \              |
--	 *         |  \             |
--	 *         |   \            |
--	 *         |    \           |
--	 *         |     \          |
--	 *         |      \         |
--	 *         |       \________|1 MB
--	 *         |----------------|
--	 *    VRAM 0 %             100 %
--	 *         used            used
-+	 *	   __________________
-+	 * 1/4 of -|\		    |
-+	 * VRAM    | \		    |
-+	 *	   |  \		    |
-+	 *	   |   \	    |
-+	 *	   |	\	    |
-+	 *	   |	 \	    |
-+	 *	   |	  \	    |
-+	 *	   |	   \________|1 MB
-+	 *	   |----------------|
-+	 *    VRAM 0 %		   100 %
-+	 *	   used		   used
- 	 *
- 	 * Note: It's a threshold, not a limit. The threshold must be crossed
- 	 * for buffer relocations to stop, so any buffer of an arbitrary size
-@@ -340,64 +340,64 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- 			    struct list_head *validated)
- {
- 	struct amdgpu_bo_list_entry *lobj;
--        u64 initial_bytes_moved;
-+	u64 initial_bytes_moved;
- 	int r;
- 
- 	list_for_each_entry(lobj, validated, tv.head) {
--                struct amdgpu_bo *bo = lobj->robj;
--                bool binding_userptr = false;
--                struct mm_struct *usermm;
--                uint32_t domain;
--
--                usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
--                if (usermm && usermm != current->mm)
--                        return -EPERM;
--
--               /* Check if we have user pages and nobody bound the BO already */
--                if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
--                       size_t size = sizeof(struct page *);
--
--                       size *= bo->tbo.ttm->num_pages;
--                       memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
--                       binding_userptr = true;
--               }
--
--                if (bo->pin_count)
--                        continue;
--
--               /* Avoid moving this one if we have moved too many buffers
--                * for this IB already.
--                *
--                * Note that this allows moving at least one buffer of
--                * any size, because it doesn't take the current "bo"
--                * into account. We don't want to disallow buffer moves
--                * completely.
--                */
--                if (p->bytes_moved <= p->bytes_moved_threshold)
--                        domain = bo->prefered_domains;
--                else
--                        domain = bo->allowed_domains;
-+		struct amdgpu_bo *bo = lobj->robj;
-+		bool binding_userptr = false;
-+		struct mm_struct *usermm;
-+		uint32_t domain;
-+
-+		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
-+		if (usermm && usermm != current->mm)
-+			return -EPERM;
-+
-+		/* Check if we have user pages and nobody bound the BO already */
-+		if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
-+			size_t size = sizeof(struct page *);
-+
-+			size *= bo->tbo.ttm->num_pages;
-+			memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
-+			binding_userptr = true;
-+		}
-+
-+		if (bo->pin_count)
-+			continue;
-+
-+		/* Avoid moving this one if we have moved too many buffers
-+		 * for this IB already.
-+		 *
-+		 * Note that this allows moving at least one buffer of
-+		 * any size, because it doesn't take the current "bo"
-+		 * into account. We don't want to disallow buffer moves
-+		 * completely.
-+		 */
-+		if (p->bytes_moved <= p->bytes_moved_threshold)
-+			domain = bo->prefered_domains;
-+		else
-+			domain = bo->allowed_domains;
-  
--        retry:
--                amdgpu_ttm_placement_from_domain(bo, domain);
--                initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
--                r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
--                p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
--                               initial_bytes_moved;
-+	retry:
-+		amdgpu_ttm_placement_from_domain(bo, domain);
-+		initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
-+		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
-+		p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
-+			       initial_bytes_moved;
-  
--                if (unlikely(r)) {
--                        if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
--                                domain = bo->allowed_domains;
-+		if (unlikely(r)) {
-+			if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
-+				domain = bo->allowed_domains;
- 
--                                goto retry;
-+				goto retry;
- 			}
- 			return r;
- 		}
- 
--               if (binding_userptr) {
--                       drm_free_large(lobj->user_pages);
--                       lobj->user_pages = NULL;
--                }
-+		if (binding_userptr) {
-+			drm_free_large(lobj->user_pages);
-+			lobj->user_pages = NULL;
-+		}
- 	}
- 	return 0;
- }
-@@ -405,132 +405,132 @@ int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
- static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- {
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
--        struct amdgpu_cs_buckets buckets;
--        struct amdgpu_bo_list_entry *e;
-+	struct amdgpu_cs_buckets buckets;
-+	struct amdgpu_bo_list_entry *e;
- 	struct list_head duplicates;
- 	bool need_mmap_lock = false;
--        unsigned i, tries = 10;
--        int  r;
-+	unsigned i, tries = 10;
-+	int  r;
- 	
- 	if (p->bo_list) {
--                need_mmap_lock = p->bo_list->first_userptr !=
--                        p->bo_list->num_entries;
--                amdgpu_cs_buckets_init(&buckets);
--                for (i = 0; i < p->bo_list->num_entries; i++)
--                        amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
--                                                                 p->bo_list->array[i].priority);
--
--               amdgpu_cs_buckets_get_list(&buckets, &p->validated);
-+		need_mmap_lock = p->bo_list->first_userptr !=
-+			p->bo_list->num_entries;
-+		amdgpu_cs_buckets_init(&buckets);
-+		for (i = 0; i < p->bo_list->num_entries; i++)
-+			amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
-+								 p->bo_list->array[i].priority);
-+
-+	       amdgpu_cs_buckets_get_list(&buckets, &p->validated);
- 	}
- 
--        INIT_LIST_HEAD(&duplicates);
--        amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
-+	INIT_LIST_HEAD(&duplicates);
-+	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
- 
--        if (p->job->uf.bo)
-+	if (p->job->uf.bo)
- 		list_add(&p->uf_entry.tv.head, &p->validated);
- 
- 	if (need_mmap_lock)
- 		down_read(&current->mm->mmap_sem);
- 
--        while (1) {
--                struct list_head need_pages;
--                unsigned i;
-+	while (1) {
-+		struct list_head need_pages;
-+		unsigned i;
- 
--                r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
--                                           &duplicates);
--                if (unlikely(r != 0))
--                        goto error_free_pages;
-+		r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
-+					   &duplicates);
-+		if (unlikely(r != 0))
-+			goto error_free_pages;
-  
--                /* Without a BO list we don't have userptr BOs */
--                if (!p->bo_list)
--                        break;
-+		/* Without a BO list we don't have userptr BOs */
-+		if (!p->bo_list)
-+			break;
-  
--                INIT_LIST_HEAD(&need_pages);
--                for (i = p->bo_list->first_userptr;
--                     i < p->bo_list->num_entries; ++i) {
-+		INIT_LIST_HEAD(&need_pages);
-+		for (i = p->bo_list->first_userptr;
-+		     i < p->bo_list->num_entries; ++i) {
-  
--                        e = &p->bo_list->array[i];
-+			e = &p->bo_list->array[i];
-  
--                        if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
--                                 &e->user_invalidated) && e->user_pages) {
-+			if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
-+				 &e->user_invalidated) && e->user_pages) {
-  
--                                /* We acquired a page array, but somebody
--                                * invalidated it. Free it an try again
--                                */
--                                release_pages(e->user_pages,
--                                             e->robj->tbo.ttm->num_pages,
--                                             false);
--                               drm_free_large(e->user_pages);
--                               e->user_pages = NULL;
--                       }
--
--                       if (e->robj->tbo.ttm->state != tt_bound &&
--                           !e->user_pages) {
--                               list_del(&e->tv.head);
--                               list_add(&e->tv.head, &need_pages);
--
--                               amdgpu_bo_unreserve(e->robj);
--                       }
--               }
--
--                if (list_empty(&need_pages))
--                       break;
-+				/* We acquired a page array, but somebody
-+				 * invalidated it. Free it an try again
-+				 */
-+				release_pages(e->user_pages,
-+					      e->robj->tbo.ttm->num_pages,
-+					      false);
-+				drm_free_large(e->user_pages);
-+				e->user_pages = NULL;
-+			}
-+
-+			if (e->robj->tbo.ttm->state != tt_bound &&
-+			    !e->user_pages) {
-+				list_del(&e->tv.head);
-+				list_add(&e->tv.head, &need_pages);
-+
-+				amdgpu_bo_unreserve(e->robj);
-+			}
-+		}
-+
-+		if (list_empty(&need_pages))
-+			break;
-  
--               /* Unreserve everything again. */
--                ttm_eu_backoff_reservation(&p->ticket, &p->validated);
--
--               /* We tried to often, just abort */
--                if (!--tries) {
--                       r = -EDEADLK;
--                        goto error_free_pages;
--                }
-+		/* Unreserve everything again. */
-+		ttm_eu_backoff_reservation(&p->ticket, &p->validated);
-+
-+		/* We tried to often, just abort */
-+		if (!--tries) {
-+			r = -EDEADLK;
-+			goto error_free_pages;
-+		}
-  
--                /* Fill the page arrays for all useptrs. */
--                list_for_each_entry(e, &need_pages, tv.head) {
--                        struct ttm_tt *ttm = e->robj->tbo.ttm;
-+		/* Fill the page arrays for all useptrs. */
-+		list_for_each_entry(e, &need_pages, tv.head) {
-+			struct ttm_tt *ttm = e->robj->tbo.ttm;
-  
--                        e->user_pages = drm_calloc_large(ttm->num_pages,
--                                                         sizeof(struct page*));
--                        if (!e->user_pages) {
--                                r = -ENOMEM;
--                                goto error_free_pages;
--                        }
-+			e->user_pages = drm_calloc_large(ttm->num_pages,
-+							 sizeof(struct page*));
-+			if (!e->user_pages) {
-+				r = -ENOMEM;
-+				goto error_free_pages;
-+			}
-  
--                        r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
--                        if (r) {
--                                drm_free_large(e->user_pages);
--                                e->user_pages = NULL;
--                                goto error_free_pages;
--                        }
--                }
-+			r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
-+			if (r) {
-+				drm_free_large(e->user_pages);
-+				e->user_pages = NULL;
-+				goto error_free_pages;
-+			}
-+		}
-  
--                /* And try again. */
--                list_splice(&need_pages, &p->validated);
--        }
-+		/* And try again. */
-+		list_splice(&need_pages, &p->validated);
-+	}
- 
--        amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
-+	amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
- 
--        p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
--        p->bytes_moved = 0;
-+	p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
-+	p->bytes_moved = 0;
-  
--        r = amdgpu_cs_list_validate(p, &duplicates);
-+	r = amdgpu_cs_list_validate(p, &duplicates);
- 	if (r)
- 		goto error_validate;
- 
--        r = amdgpu_cs_list_validate(p, &p->validated);
--        if (r)
--                goto error_validate;
-+	r = amdgpu_cs_list_validate(p, &p->validated);
-+	if (r)
-+		goto error_validate;
- 
--        if (p->bo_list) {
--                struct amdgpu_vm *vm = &fpriv->vm;
--                unsigned i;
-+	if (p->bo_list) {
-+		struct amdgpu_vm *vm = &fpriv->vm;
-+		unsigned i;
-  
--                for (i = 0; i < p->bo_list->num_entries; i++) {
--                        struct amdgpu_bo *bo = p->bo_list->array[i].robj;
-+		for (i = 0; i < p->bo_list->num_entries; i++) {
-+			struct amdgpu_bo *bo = p->bo_list->array[i].robj;
-  
--                        p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
--                }
--        }
-+			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
-+		}
-+	}
- 
- error_validate:
- 	if (r) {
-@@ -540,23 +540,23 @@ error_validate:
- 
- error_free_pages:
- 
--        if (need_mmap_lock)
--                up_read(&current->mm->mmap_sem);
-+	if (need_mmap_lock)
-+		up_read(&current->mm->mmap_sem);
- 
--       if (p->bo_list) {
--                for (i = p->bo_list->first_userptr;
--                     i < p->bo_list->num_entries; ++i) {
--                        e = &p->bo_list->array[i];
-+	if (p->bo_list) {
-+		for (i = p->bo_list->first_userptr;
-+		     i < p->bo_list->num_entries; ++i) {
-+			e = &p->bo_list->array[i];
-  
--                        if (!e->user_pages)
--                                continue;
-+			if (!e->user_pages)
-+				continue;
-  
--                        release_pages(e->user_pages,
--                                      e->robj->tbo.ttm->num_pages,
--                                      false);
--                        drm_free_large(e->user_pages);
--                }
--        }
-+			release_pages(e->user_pages,
-+				      e->robj->tbo.ttm->num_pages,
-+				      false);
-+			drm_free_large(e->user_pages);
-+		}
-+	}
- 
- 	return r;
- }
-@@ -568,7 +568,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
- 
- 	list_for_each_entry(e, &p->validated, tv.head) {
- 		struct reservation_object *resv = e->robj->tbo.resv;
--                r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
-+		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
- 
- 		if (r)
- 			return r;
-@@ -609,8 +609,8 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
- 	for (i = 0; i < parser->nchunks; i++)
- 		drm_free_large(parser->chunks[i].kdata);
- 	kfree(parser->chunks);
--        if (parser->job)
--                amdgpu_job_free(parser->job);
-+	if (parser->job)
-+		amdgpu_job_free(parser->job);
- 	amdgpu_bo_unref(&parser->uf_entry.robj);
- }
- 
-@@ -626,7 +626,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- 	if (r)
- 		return r;
- 
--        r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
-+	r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
- 	if (r)
- 		return r;
- 
-@@ -652,14 +652,14 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- 				return r;
- 
- 			f = bo_va->last_pt_update;
--                        r = amdgpu_sync_fence(adev, &p->job->sync, f);
-+			r = amdgpu_sync_fence(adev, &p->job->sync, f);
- 			if (r)
- 				return r;
- 		}
- 
- 	}
- 
--        r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
-+	r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
- 
- 	if (amdgpu_vm_debug && p->bo_list) {
- 		/* Invalidate all BOs to test for userspace bugs */
-@@ -677,26 +677,25 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
- }
- 
- static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
--                                 struct amdgpu_cs_parser *p)
-+				 struct amdgpu_cs_parser *p)
- {
--        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-+	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	struct amdgpu_vm *vm = &fpriv->vm;
--        struct amdgpu_ring *ring = p->job->ring;
-+	struct amdgpu_ring *ring = p->job->ring;
- 	int i, r;
- 
- 	/* Only for UVD/VCE VM emulation */
--        if (ring->funcs->parse_cs) {
--                for (i = 0; i < p->job->num_ibs; i++) {
--                        r = amdgpu_ring_parse_cs(ring, p, i);
--
-+	if (ring->funcs->parse_cs) {
-+		for (i = 0; i < p->job->num_ibs; i++) {
-+			r = amdgpu_ring_parse_cs(ring, p, i);
- 			if (r)
- 				return r;
- 		}
- 	}
- 
--        r = amdgpu_bo_vm_update_pte(p, vm);
-+	r = amdgpu_bo_vm_update_pte(p, vm);
- 	if (!r)
--                amdgpu_cs_sync_rings(p);
-+		amdgpu_cs_sync_rings(p);
- 
- 	return r;
- }
-@@ -719,14 +718,14 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 	int i, j;
- 	int r;
- 
--        for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
-+	for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
- 		struct amdgpu_cs_chunk *chunk;
- 		struct amdgpu_ib *ib;
- 		struct drm_amdgpu_cs_chunk_ib *chunk_ib;
- 		struct amdgpu_ring *ring;
- 
- 		chunk = &parser->chunks[i];
--                ib = &parser->job->ibs[j];
-+		ib = &parser->job->ibs[j];
- 		chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
- 
- 		if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
-@@ -738,10 +737,10 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		if (r)
- 			return r;
- 
--                if (parser->job->ring && parser->job->ring != ring)
--                        return -EINVAL;
-+		if (parser->job->ring && parser->job->ring != ring)
-+			return -EINVAL;
-  
--                parser->job->ring = ring;
-+		parser->job->ring = ring;
- 
- 		if (ring->funcs->parse_cs) {
- 			struct amdgpu_bo_va_mapping *m;
-@@ -771,7 +770,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 			offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
- 			kptr += chunk_ib->va_start - offset;
- 
--                        r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
-+			r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
- 			if (r) {
- 				DRM_ERROR("Failed to get ib !\n");
- 				return r;
-@@ -780,7 +779,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
- 			amdgpu_bo_kunmap(aobj);
- 		} else {
--                        r =  amdgpu_ib_get(adev, vm, 0, ib);
-+			r =  amdgpu_ib_get(adev, vm, 0, ib);
- 			if (r) {
- 				DRM_ERROR("Failed to get ib !\n");
- 				return r;
-@@ -799,7 +798,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		struct amdgpu_bo *gds = parser->bo_list->gds_obj;
- 		struct amdgpu_bo *gws = parser->bo_list->gws_obj;
- 		struct amdgpu_bo *oa = parser->bo_list->oa_obj;
--                struct amdgpu_ib *ib = &parser->job->ibs[0];
-+		struct amdgpu_ib *ib = &parser->job->ibs[0];
- 
- 		if (gds) {
- 			ib->gds_base = amdgpu_bo_gpu_offset(gds);
-@@ -815,16 +814,16 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
- 		}
- 	}
- 	/* wrap the last IB with user fence */
--        if (parser->job->uf.bo) {
--                struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
-+	if (parser->job->uf.bo) {
-+		struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
- 
- 		/* UVD & VCE fw doesn't support user fences */
--                if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
--                    parser->job->ring->type == AMDGPU_RING_TYPE_VCE)
-+		if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
-+		    parser->job->ring->type == AMDGPU_RING_TYPE_VCE)
- 
- 			return -EINVAL;
- 
--                ib->user = &parser->job->uf;
-+		ib->user = &parser->job->uf;
- 	}
- 
- 	return 0;
-@@ -873,8 +872,8 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- 				return r;
- 
- 			} else if (fence) {
--                                r = amdgpu_sync_fence(adev, &p->job->sync,
--                                                      fence);
-+				r = amdgpu_sync_fence(adev, &p->job->sync,
-+						      fence);
- 				fence_put(fence);
- 				amdgpu_ctx_put(ctx);
- 				if (r)
-@@ -889,28 +888,27 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
- 			    union drm_amdgpu_cs *cs)
- {
--        struct amdgpu_ring *ring = p->job->ring;
--        struct fence *fence;
-+	struct amdgpu_ring *ring = p->job->ring;
-+	struct fence *fence;
- 	struct amdgpu_job *job;
- 	int r;
- 
--        job = p->job;
--        p->job = NULL;
-+	job = p->job;
-+	p->job = NULL;
- 
--        r = amd_sched_job_init(&job->base, &ring->sched,
--                                                &p->ctx->rings[ring->idx].entity,
--                                                amdgpu_job_timeout_func,
--                                                amdgpu_job_free_func,
--                                                p->filp, &fence);
--        if (r) {
--	
-- 	         amdgpu_job_free(job);
-+	r = amd_sched_job_init(&job->base, &ring->sched,
-+						&p->ctx->rings[ring->idx].entity,
-+						amdgpu_job_timeout_func,
-+						amdgpu_job_free_func,
-+						p->filp, &fence);
-+	if (r) {
-+		amdgpu_job_free(job);
- 		return r;
- 	}
- 
--        job->owner = p->filp;
--        p->fence = fence_get(fence);
--        cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence);
-+	job->owner = p->filp;
-+	p->fence = fence_get(fence);
-+	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence);
- 	job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
- 	
- 	trace_amdgpu_cs_ioctl(job);
-@@ -940,7 +938,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 		r = amdgpu_cs_handle_lockup(adev, r);
- 		return r;
- 	}
--        r = amdgpu_cs_parser_relocs(&parser);
-+	r = amdgpu_cs_parser_relocs(&parser);
- 	if (r == -ENOMEM)
- 		DRM_ERROR("Not enough memory for command submission!\n");
- 	else if (r && r != -ERESTARTSYS)
-@@ -959,14 +957,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- 	if (r)
- 		goto out;
- 
--        for (i = 0; i < parser.job->num_ibs; i++)
-+	for (i = 0; i < parser.job->num_ibs; i++)
- 		trace_amdgpu_cs(&parser, i);
- 
- 	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
- 	if (r)
- 		goto out;
- 
--        r = amdgpu_cs_submit(&parser, cs);
-+	r = amdgpu_cs_submit(&parser, cs);
- 
- out:
- 	amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 5f43c3e..6077ec6 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -22,8 +22,8 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-  */
- #include <linux/console.h>
- #include <linux/slab.h>
-@@ -379,7 +379,7 @@ static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
- 
- /**
-  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
-- *                                setup amdkfd
-+ *				  setup amdkfd
-  *
-  * @adev: amdgpu_device pointer
-  * @aperture_base: output returning doorbell aperture base physical address
-@@ -454,7 +454,7 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
- 
- 	if (adev->wb.wb_obj == NULL) {
- 		r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
--				     AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
-+				     AMDGPU_GEM_DOMAIN_GTT, 0,	NULL, NULL,
- 				     &adev->wb.wb_obj);
- 		if (r) {
- 			dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
-@@ -1003,7 +1003,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
-  * @pdev: pci dev pointer
-  * @state: vga_switcheroo state
-  *
-- * Callback for the switcheroo driver.  Suspends or resumes the
-+ * Callback for the switcheroo driver.	Suspends or resumes the
-  * the asics before or after it is powered up using ACPI methods.
-  */
- static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
-@@ -1040,7 +1040,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
-  *
-  * @pdev: pci dev pointer
-  *
-- * Callback for the switcheroo driver.  Check of the switcheroo
-+ * Callback for the switcheroo driver.	Check of the switcheroo
-  * state can be changed.
-  * Returns true if the state can be changed, false if not.
-  */
-@@ -1447,7 +1447,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- 	adev->mman.buffer_funcs = NULL;
- 	adev->mman.buffer_funcs_ring = NULL;
- 	adev->vm_manager.vm_pte_funcs = NULL;
--        adev->vm_manager.vm_pte_num_rings = 0;
-+	adev->vm_manager.vm_pte_num_rings = 0;
- 	adev->gart.gart_funcs = NULL;
- 	adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index bd8fabc..61eebc5 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -131,8 +131,9 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
- 				 vblank->framedur_ns / 1000,
- 				 vblank->linedur_ns / 1000, stat, vpos, hpos);
- 
--	/* do the flip (mmio) */
-+	/* Do the flip (mmio) */
- 	adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
-+
- 	/* set the flip status */
- 	amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
-index 3738a96..caa38dd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
-@@ -23,8 +23,8 @@
- #ifndef __AMDGPU_DPM_H__
- #define __AMDGPU_DPM_H__
- 
--#define R600_SSTU_DFLT                               0
--#define R600_SST_DFLT                                0x00C8
-+#define R600_SSTU_DFLT				     0
-+#define R600_SST_DFLT				     0x00C8
- 
- /* XXX are these ok? */
- #define R600_TEMP_RANGE_MIN (90 * 1000)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-index 50e95ab..c9fdc86 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
-@@ -616,7 +616,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
- 		seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
- 		seq_printf(m, "Last signaled fence 0x%08x\n",
- 			   atomic_read(&ring->fence_drv.last_seq));
--		seq_printf(m, "Last emitted        0x%08x\n",
-+		seq_printf(m, "Last emitted	   0x%08x\n",
- 			   ring->fence_drv.sync_seq);
- 	}
- 	return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 75edc9d..155bad9 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -22,8 +22,8 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-  */
- #include <linux/ktime.h>
- #include <linux/pagemap.h>
-@@ -274,8 +274,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
- 		goto handle_lockup;
- 
- 	bo = gem_to_amdgpu_bo(gobj);
--        bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
--        bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
-+	bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
-+	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
- 	r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
- 	if (r)
- 		goto release_object;
-@@ -343,7 +343,7 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp,
- 		return -ENOENT;
- 	}
- 	robj = gem_to_amdgpu_bo(gobj);
--        if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
-+	if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
- 	    (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
- 		drm_gem_object_unreference_unlocked(gobj);
- 		return -EPERM;
-@@ -483,7 +483,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 				    struct amdgpu_bo_va *bo_va, uint32_t operation)
- {
- 	struct ttm_validate_buffer tv, *entry;
--        struct amdgpu_bo_list_entry vm_pd;
-+	struct amdgpu_bo_list_entry vm_pd;
- 	struct ww_acquire_ctx ticket;
- 	struct list_head list, duplicates;
- 	unsigned domain;
-@@ -496,14 +496,14 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- 	tv.shared = true;
- 	list_add(&tv.head, &list);
- 
--        amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
-+	amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
- 
- 	/* Provide duplicates to avoid -EALREADY */
- 	r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
- 	if (r)
--                goto error_print;
-+		goto error_print;
-  
--        amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
-+	amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
- 	list_for_each_entry(entry, &list, head) {
- 		domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
- 		/* if anything is swapped out don't swap it in here,
-@@ -663,7 +663,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 
- 		info.bo_size = robj->gem_base.size;
- 		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
--                info.domains = robj->prefered_domains;
-+		info.domains = robj->prefered_domains;
- 		info.domain_flags = robj->flags;
- 		amdgpu_bo_unreserve(robj);
- 		if (copy_to_user(out, &info, sizeof(info)))
-@@ -671,17 +671,17 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 		break;
- 	}
- 	case AMDGPU_GEM_OP_SET_PLACEMENT:
--                if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
-+		if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
- 			r = -EPERM;
- 			amdgpu_bo_unreserve(robj);
- 			break;
- 		}
--                robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
--                                                        AMDGPU_GEM_DOMAIN_GTT |
--                                                        AMDGPU_GEM_DOMAIN_CPU);
--                robj->allowed_domains = robj->prefered_domains;
--                if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
--                        robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
-+		robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
-+							AMDGPU_GEM_DOMAIN_GTT |
-+							AMDGPU_GEM_DOMAIN_CPU);
-+		robj->allowed_domains = robj->prefered_domains;
-+		if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
-+			robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
-  
- 		amdgpu_bo_unreserve(robj);
- 		break;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-index b987f47..58f2ec1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
-@@ -22,9 +22,9 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-- *          Christian König
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-+ *	    Christian König
-  */
- #include <linux/seq_file.h>
- #include <linux/slab.h>
-@@ -111,19 +111,19 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
-  * the resource descriptors will be already in cache when the draw is
-  * processed.  To accomplish this, the userspace driver submits two
-  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
-- * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
-+ * a CONST_IB), it will be put on the ring prior to the DE IB.	Prior
-  * to SI there was just a DE IB.
-  */
- int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
--                       struct amdgpu_ib *ibs, struct fence *last_vm_update,
--                       struct amdgpu_job *job, struct fence **f)
-+		       struct amdgpu_ib *ibs, struct fence *last_vm_update,
-+		       struct amdgpu_job *job, struct fence **f)
- {
--        struct amdgpu_device *adev = ring->adev;
-+	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_ib *ib = &ibs[0];
--        uint64_t fence_context = 0, old = ring->last_fence_context;
-+	uint64_t fence_context = 0, old = ring->last_fence_context;
- 	struct fence *hwf;
--        struct amdgpu_vm *vm = NULL;
--        unsigned i, patch_offset = ~0;
-+	struct amdgpu_vm *vm = NULL;
-+	unsigned i, patch_offset = ~0;
- 
- 	int r = 0;
- 
-@@ -156,17 +156,18 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 
- 	if (vm) {
- 		/* do context switch */
--                r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
--                                    ib->gds_base, ib->gds_size,
--                                    ib->gws_base, ib->gws_size,
--                                    ib->oa_base, ib->oa_size);
--                if (r) {
--                        amdgpu_ring_undo(ring);
--                        return r;
--                    }
-+		r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
-+				    ib->gds_base, ib->gds_size,
-+				    ib->gws_base, ib->gws_size,
-+				    ib->oa_base, ib->oa_size);
-+		if (r) {
-+			amdgpu_ring_undo(ring);
-+			return r;
-+		    }
- 		}
--		if (ring->funcs->emit_hdp_flush)
--			amdgpu_ring_emit_hdp_flush(ring);
-+
-+	if (ring->funcs->emit_hdp_flush)
-+		amdgpu_ring_emit_hdp_flush(ring);
- 
- 	/* always set cond_exec_polling to CONTINUE */
- 	*ring->cond_exe_cpu_addr = 1;
-@@ -176,10 +177,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 
- 		amdgpu_ring_emit_ib(ring, ib, (i == 0 && old != fence_context));
- 	}
--        ring->last_fence_context = fence_context;
-+	ring->last_fence_context = fence_context;
- 
--        if (ring->funcs->emit_hdp_invalidate)
--                amdgpu_ring_emit_hdp_invalidate(ring);
-+	if (ring->funcs->emit_hdp_invalidate)
-+		amdgpu_ring_emit_hdp_invalidate(ring);
- 
- 	r = amdgpu_fence_emit(ring, &hwf);
- 	if (r) {
-@@ -198,11 +199,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- 		amdgpu_ring_emit_fence(ring, addr, ib->sequence,
- 				       AMDGPU_FENCE_FLAG_64BIT);
- 	}
--	if(f)
--        *f = fence_get(hwf);
- 
--        if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
--                amdgpu_ring_patch_cond_exec(ring, patch_offset);
-+	if (f)
-+		*f = fence_get(hwf);
-+
-+	if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
-+		amdgpu_ring_patch_cond_exec(ring, patch_offset);
- 
- 	amdgpu_ring_commit(ring);
- 	return 0;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-index 50257ad..de521d8 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
-@@ -37,71 +37,72 @@ static void amdgpu_job_free_handler(struct work_struct *ws)
- void amdgpu_job_timeout_func(struct work_struct *work)
- {
- 	struct amdgpu_job *job = container_of(work, struct amdgpu_job, base.work_tdr.work);
-+
- 	DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
--				job->base.sched->name,
--				(uint32_t)atomic_read(&job->ring->fence_drv.last_seq),
--				job->ring->fence_drv.sync_seq);
-+		  job->base.sched->name,
-+		  (uint32_t)atomic_read(&job->ring->fence_drv.last_seq),
-+		  job->ring->fence_drv.sync_seq);
- 
- 	amd_sched_job_put(&job->base);
- }
- 
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--                    struct amdgpu_job **job, struct amdgpu_vm *vm)
-+		     struct amdgpu_job **job, struct amdgpu_vm *vm)
- {
--       size_t size = sizeof(struct amdgpu_job);
-+	size_t size = sizeof(struct amdgpu_job);
- 
--       if (num_ibs == 0)
--               return -EINVAL;
-+	if (num_ibs == 0)
-+		return -EINVAL;
- 
--       size += sizeof(struct amdgpu_ib) * num_ibs;
-+	size += sizeof(struct amdgpu_ib) * num_ibs;
- 
--       *job = kzalloc(size, GFP_KERNEL);
--       if (!*job)
--               return -ENOMEM;
-+	*job = kzalloc(size, GFP_KERNEL);
-+	if (!*job)
-+		return -ENOMEM;
- 
--       (*job)->adev = adev;
--       (*job)->vm = vm;
--       (*job)->ibs = (void *)&(*job)[1];
--       (*job)->num_ibs = num_ibs;
--       INIT_WORK(&(*job)->base.work_free_job, amdgpu_job_free_handler);
-+	(*job)->adev = adev;
-+	(*job)->vm = vm;
-+	(*job)->ibs = (void *)&(*job)[1];
-+	(*job)->num_ibs = num_ibs;
-+	INIT_WORK(&(*job)->base.work_free_job, amdgpu_job_free_handler);
- 
--       amdgpu_sync_create(&(*job)->sync);
-+	amdgpu_sync_create(&(*job)->sync);
- 
--       return 0;
-+	return 0;
- }
- 
- int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
--                            struct amdgpu_job **job)
-+			     struct amdgpu_job **job)
- {
--       int r;
-+	int r;
- 
--       r = amdgpu_job_alloc(adev, 1, job, NULL);
--       if (r)
--               return r;
-+	r = amdgpu_job_alloc(adev, 1, job, NULL);
-+	if (r)
-+		return r;
- 
--       r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
--       if (r)
--               kfree(*job);
-+	r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
-+	if (r)
-+		kfree(*job);
- 
--       return r;
-+	return r;
- }
- 
- void amdgpu_job_free(struct amdgpu_job *job)
- {
--       unsigned i;
--       struct fence *f;
--       /* use sched fence if available */
--       f = (job->base.s_fence)? &job->base.s_fence->base : job->fence;
-+	unsigned i;
-+	struct fence *f;
-+	/* use sched fence if available */
-+	f = (job->base.s_fence)? &job->base.s_fence->base : job->fence;
- 
--       for (i = 0; i < job->num_ibs; ++i)
--               amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, f);
--       fence_put(job->fence);
-+	for (i = 0; i < job->num_ibs; ++i)
-+		amdgpu_sa_bo_free(job->adev, &job->ibs[i].sa_bo, f);
-+	fence_put(job->fence);
- 
--       amdgpu_bo_unref(&job->uf.bo);
--       amdgpu_sync_free(&job->sync);
-+	amdgpu_bo_unref(&job->uf.bo);
-+	amdgpu_sync_free(&job->sync);
- 
--       if (!job->base.use_sched)
--                kfree(job);
-+	if (!job->base.use_sched)
-+		 kfree(job);
- }
- 
- void amdgpu_job_free_func(struct kref *refcount)
-@@ -111,97 +112,97 @@ void amdgpu_job_free_func(struct kref *refcount)
- }
- 
- int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
--                      struct amd_sched_entity *entity, void *owner,
--                      struct fence **f)
-+		      struct amd_sched_entity *entity, void *owner,
-+		      struct fence **f)
- {
--       struct fence *fence;
--       int r;
--       job->ring = ring;
--       if (!f)
--               return -EINVAL;
--
--       r = amd_sched_job_init(&job->base, &ring->sched,
--                                                       entity,
--                                                       amdgpu_job_timeout_func,
--                                                       amdgpu_job_free_func,
--                                                       owner, &fence);
--       if (r)
--               return r;
--
--       job->owner = owner;
--       *f = fence_get(fence);
--       amd_sched_entity_push_job(&job->base);
--
--       return 0;
-+	struct fence *fence;
-+	int r;
-+	job->ring = ring;
-+	if (!f)
-+		return -EINVAL;
-+
-+	r = amd_sched_job_init(&job->base, &ring->sched,
-+						       entity,
-+						       amdgpu_job_timeout_func,
-+						       amdgpu_job_free_func,
-+						       owner, &fence);
-+	if (r)
-+		return r;
-+
-+	job->owner = owner;
-+	*f = fence_get(fence);
-+	amd_sched_entity_push_job(&job->base);
-+
-+	return 0;
- }
- 
- static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
- {
--       struct amdgpu_job *job = to_amdgpu_job(sched_job);
--       struct amdgpu_vm *vm = job->vm;
--       struct fence *fence = amdgpu_sync_get_fence(&job->sync);
--
--       if (fence == NULL && vm && !job->ibs->vm_id) {
--               struct amdgpu_ring *ring = job->ring;
--               unsigned i, vm_id;
--               uint64_t vm_pd_addr;
--               int r;
--
--               r = amdgpu_vm_grab_id(vm, ring, &job->sync,
--                                      &job->base.s_fence->base,
--                                      &vm_id, &vm_pd_addr);
--               if (r)
--                       DRM_ERROR("Error getting VM ID (%d)\n", r);
--               else {
--                       for (i = 0; i < job->num_ibs; ++i) {
--                               job->ibs[i].vm_id = vm_id;
--                               job->ibs[i].vm_pd_addr = vm_pd_addr;
--                       }
--               }
--
--               fence = amdgpu_sync_get_fence(&job->sync);
--       }
--
--       return fence;
-+	struct amdgpu_job *job = to_amdgpu_job(sched_job);
-+	struct amdgpu_vm *vm = job->vm;
-+	struct fence *fence = amdgpu_sync_get_fence(&job->sync);
-+
-+	if (fence == NULL && vm && !job->ibs->vm_id) {
-+		struct amdgpu_ring *ring = job->ring;
-+		unsigned i, vm_id;
-+		uint64_t vm_pd_addr;
-+		int r;
-+
-+		r = amdgpu_vm_grab_id(vm, ring, &job->sync,
-+				      &job->base.s_fence->base,
-+				      &vm_id, &vm_pd_addr);
-+		if (r)
-+			DRM_ERROR("Error getting VM ID (%d)\n", r);
-+		else {
-+			for (i = 0; i < job->num_ibs; ++i) {
-+				job->ibs[i].vm_id = vm_id;
-+				job->ibs[i].vm_pd_addr = vm_pd_addr;
-+			}
-+		}
-+
-+		fence = amdgpu_sync_get_fence(&job->sync);
-+	}
-+
-+	return fence;
- }
- 
- static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
- {
--       struct fence *fence = NULL;
--       struct amdgpu_job *job;
--       int r;
--
--       if (!sched_job) {
--               DRM_ERROR("job is null\n");
--               return NULL;
--       }
--       job = to_amdgpu_job(sched_job);
--
--       r = amdgpu_sync_wait(&job->sync);
--       if (r) {
--               DRM_ERROR("failed to sync wait (%d)\n", r);
--               return NULL;
--       }
--
--       trace_amdgpu_sched_run_job(job);
--       r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
--                              job->sync.last_vm_update, job, &fence);
--       if (r) {
--               DRM_ERROR("Error scheduling IBs (%d)\n", r);
--               goto err;
--       }
-+	struct fence *fence = NULL;
-+	struct amdgpu_job *job;
-+	int r;
-+
-+	if (!sched_job) {
-+		DRM_ERROR("job is null\n");
-+		return NULL;
-+	}
-+	job = to_amdgpu_job(sched_job);
-+
-+	r = amdgpu_sync_wait(&job->sync);
-+	if (r) {
-+		DRM_ERROR("failed to sync wait (%d)\n", r);
-+		return NULL;
-+	}
-+
-+	trace_amdgpu_sched_run_job(job);
-+	r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
-+			       job->sync.last_vm_update, job, &fence);
-+	if (r) {
-+		DRM_ERROR("Error scheduling IBs (%d)\n", r);
-+		goto err;
-+	}
- 
- err:
--       job->fence = fence;
--       amdgpu_job_free(job);
--       return fence;
-+	job->fence = fence;
-+	amdgpu_job_free(job);
-+	return fence;
- }
- 
- const struct amd_sched_backend_ops amdgpu_sched_ops = {
--       .dependency = amdgpu_job_dependency,
--       .run_job = amdgpu_job_run,
--       .begin_job = amd_sched_job_begin,
--       .finish_job = amd_sched_job_finish,
-+	.dependency = amdgpu_job_dependency,
-+	.run_job = amdgpu_job_run,
-+	.begin_job = amd_sched_job_begin,
-+	.finish_job = amd_sched_job_finish,
- };
- 
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index d4e1e86..78bd8b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -22,8 +22,8 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-  */
- #include <drm/drmP.h>
- #include "amdgpu.h"
-@@ -448,7 +448,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- 			dev_info.max_memory_clock = adev->pm.default_mclk * 10;
- 		}
- 		dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
--                dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se;
-+		dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se;
- 		dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
- 		dev_info._pad = 0;
- 		dev_info.ids_flags = 0;
-@@ -566,8 +566,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
- 
- 	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
- 
--        amdgpu_uvd_free_handles(adev, file_priv);
--        amdgpu_vce_free_handles(adev, file_priv);
-+	amdgpu_uvd_free_handles(adev, file_priv);
-+	amdgpu_vce_free_handles(adev, file_priv);
- 
- 	amdgpu_vm_fini(adev, &fpriv->vm);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index b91ff33..7ecea83 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -251,15 +251,15 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- 	bo->adev = adev;
- 	INIT_LIST_HEAD(&bo->list);
- 	INIT_LIST_HEAD(&bo->va);
--        bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
--                                         AMDGPU_GEM_DOMAIN_GTT |
--                                         AMDGPU_GEM_DOMAIN_CPU |
--                                         AMDGPU_GEM_DOMAIN_GDS |
--                                         AMDGPU_GEM_DOMAIN_GWS |
--                                         AMDGPU_GEM_DOMAIN_OA);
--        bo->allowed_domains = bo->prefered_domains;
--        if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
--                bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
-+	bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
-+					 AMDGPU_GEM_DOMAIN_GTT |
-+					 AMDGPU_GEM_DOMAIN_CPU |
-+					 AMDGPU_GEM_DOMAIN_GDS |
-+					 AMDGPU_GEM_DOMAIN_GWS |
-+					 AMDGPU_GEM_DOMAIN_OA);
-+	bo->allowed_domains = bo->prefered_domains;
-+	if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
-+		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
- 
- 	bo->flags = flags;
- 
-@@ -373,7 +373,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
- 	int r, i;
- 	unsigned fpfn, lpfn;
- 
--        if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
-+	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
- 		return -EPERM;
- 
- 	if (WARN_ON_ONCE(min_offset > max_offset))
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-index b4fe303..7700dc2 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
-@@ -118,7 +118,7 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
- {
- 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
- 
--        if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
-+	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
- 		return ERR_PTR(-EPERM);
- 
- 	return drm_gem_prime_export(dev, gobj, flags);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-index 1b0b7ae..7e79370 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
-@@ -22,9 +22,9 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-- *          Christian König
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-+ *	    Christian König
-  */
- #include <linux/seq_file.h>
- #include <linux/slab.h>
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index b602052..5994dfc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -77,8 +77,8 @@ static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
- static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
- {
- 	struct drm_global_reference *global_ref;
--        struct amdgpu_ring *ring;
--        struct amd_sched_rq *rq;
-+	struct amdgpu_ring *ring;
-+	struct amd_sched_rq *rq;
- 	int r;
- 
- 	adev->mman.mem_global_referenced = false;
-@@ -108,16 +108,16 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
- 		return r;
- 	}
- 
--        ring = adev->mman.buffer_funcs_ring;
--        rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
--        r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
--                                  rq, amdgpu_sched_jobs);
--        if (r != 0) {
--                DRM_ERROR("Failed setting up TTM BO move run queue.\n");
--                drm_global_item_unref(&adev->mman.mem_global_ref);
--                drm_global_item_unref(&adev->mman.bo_global_ref.ref);
--                return r;
--        }
-+	ring = adev->mman.buffer_funcs_ring;
-+	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
-+	r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
-+				  rq, amdgpu_sched_jobs);
-+	if (r != 0) {
-+		DRM_ERROR("Failed setting up TTM BO move run queue.\n");
-+		drm_global_item_unref(&adev->mman.mem_global_ref);
-+		drm_global_item_unref(&adev->mman.bo_global_ref.ref);
-+		return r;
-+	}
- 
- 	adev->mman.mem_global_referenced = true;
- 
-@@ -127,8 +127,8 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
- static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
- {
- 	if (adev->mman.mem_global_referenced) {
--                amd_sched_entity_fini(adev->mman.entity.sched,
--                                      &adev->mman.entity);
-+		amd_sched_entity_fini(adev->mman.entity.sched,
-+				      &adev->mman.entity);
- 		drm_global_item_unref(&adev->mman.bo_global_ref.ref);
- 		drm_global_item_unref(&adev->mman.mem_global_ref);
- 		adev->mman.mem_global_referenced = false;
-@@ -514,8 +514,8 @@ struct amdgpu_ttm_tt {
- 	uint64_t		userptr;
- 	struct mm_struct	*usermm;
- 	uint32_t		userflags;
--	spinlock_t              guptasklock;
--	struct list_head        guptasks;
-+	spinlock_t		guptasklock;
-+	struct list_head	guptasks;
- 	atomic_t		mmu_invalidations;
- };
- 
-@@ -638,13 +638,13 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
- 	uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
- 	int r;
- 
--        if (gtt->userptr) {
--                r = amdgpu_ttm_tt_pin_userptr(ttm);
--                if (r) {
--                        DRM_ERROR("failed to pin userptr\n");
--                        return r;
--                }
--        }
-+	if (gtt->userptr) {
-+		r = amdgpu_ttm_tt_pin_userptr(ttm);
-+		if (r) {
-+			DRM_ERROR("failed to pin userptr\n");
-+			return r;
-+		}
-+	}
- 	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
- 	if (!ttm->num_pages) {
- 		WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
-@@ -833,9 +833,9 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
- 
- 	if (gtt == NULL)
--                return NULL;
-+		return NULL;
- 
--        return gtt->usermm;
-+	return gtt->usermm;
- }
- 
- bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
-@@ -973,7 +973,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
- 	.io_mem_free = &amdgpu_ttm_io_mem_free,
- 	.lru_removal = &amdgpu_ttm_lru_removal,
- 	.lru_tail = &amdgpu_ttm_lru_tail,
--        .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
-+	.swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
- };
- 
- int amdgpu_ttm_init(struct amdgpu_device *adev)
-@@ -1149,6 +1149,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- {
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_job *job;
-+
- 	uint32_t max_bytes;
- 	unsigned num_loops, num_dw;
- 	unsigned i;
-@@ -1161,12 +1162,13 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	/* for IB padding */
- 	while (num_dw & 0x7)
- 		num_dw++;
-+
- 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
- 	if (r) 
- 		return r;
- 
- 	if (resv) {
--                r = amdgpu_sync_resv(adev, &job->sync, resv,
-+		r = amdgpu_sync_resv(adev, &job->sync, resv,
- 				     AMDGPU_FENCE_OWNER_UNDEFINED);
- 		if (r) {
- 			DRM_ERROR("sync failed (%d).\n", r);
-@@ -1187,13 +1189,14 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
- 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
- 	WARN_ON(job->ibs[0].length_dw > num_dw);
- 	r = amdgpu_job_submit(job, ring, &adev->mman.entity,
--                              AMDGPU_FENCE_OWNER_UNDEFINED, fence);
-+			      AMDGPU_FENCE_OWNER_UNDEFINED, fence);
- 	if (r)
- 		goto error_free;
- 
- 	return 0;
-+
- error_free:
--        amdgpu_job_free(job);
-+	amdgpu_job_free(job);
- 	return r;
- }
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index efb07fe..74f0019 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -95,8 +95,8 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
- 
- int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- {
--        struct amdgpu_ring *ring;
--        struct amd_sched_rq *rq;
-+	struct amdgpu_ring *ring;
-+	struct amd_sched_rq *rq;
- 	unsigned long bo_size;
- 	const char *fw_name;
- 	const struct common_firmware_header *hdr;
-@@ -220,14 +220,14 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
- 
- 	amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
-  
--        ring = &adev->uvd.ring;
--        rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
--        r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
--                                  rq, amdgpu_sched_jobs);
--        if (r != 0) {
--                DRM_ERROR("Failed setting up UVD run queue.\n");
--                return r;
--        }
-+	ring = &adev->uvd.ring;
-+	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+	r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
-+				  rq, amdgpu_sched_jobs);
-+	if (r != 0) {
-+		DRM_ERROR("Failed setting up UVD run queue.\n");
-+		return r;
-+	}
- 
- 	for (i = 0; i < adev->uvd.max_handles; ++i) {
- 		atomic_set(&adev->uvd.handles[i], 0);
-@@ -246,18 +246,20 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- 	int r;
- 	
- 	kfree(adev->uvd.saved_bo);
--        amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
-+
-+	amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
- 	
- 	if (adev->uvd.vcpu_bo) {
--	r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
--	if (!r) {
--		amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
--		amdgpu_bo_unpin(adev->uvd.vcpu_bo);
--		amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
-+		r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
-+		if (!r) {
-+			amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
-+			amdgpu_bo_unpin(adev->uvd.vcpu_bo);
-+			amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
-+		}
-+
-+		amdgpu_bo_unref(&adev->uvd.vcpu_bo);
- 	}
- 
--	amdgpu_bo_unref(&adev->uvd.vcpu_bo);
--    }
- 	amdgpu_ring_fini(&adev->uvd.ring);
- 
- 	release_firmware(adev->uvd.fw);
-@@ -267,30 +269,30 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- 
- int amdgpu_uvd_suspend(struct amdgpu_device *adev)
- {
--        unsigned size;
--        void *ptr;
--        int i;
-+	unsigned size;
-+	void *ptr;
-+	int i;
- 
- 	if (adev->uvd.vcpu_bo == NULL)
- 		return 0;
- 
--        for (i = 0; i < adev->uvd.max_handles; ++i)
--                if (atomic_read(&adev->uvd.handles[i]))
--                        break;
-+	for (i = 0; i < adev->uvd.max_handles; ++i)
-+		if (atomic_read(&adev->uvd.handles[i]))
-+			break;
-  
--        if (i == AMDGPU_MAX_UVD_HANDLES)
--                return 0;
-+	if (i == AMDGPU_MAX_UVD_HANDLES)
-+		return 0;
- 	
- 	cancel_delayed_work_sync(&adev->uvd.idle_work);
--        
-+
- 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
--        ptr = adev->uvd.cpu_addr;
--        
-+	ptr = adev->uvd.cpu_addr;
-+
- 	adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
--        if (!adev->uvd.saved_bo)
--                return -ENOMEM;
-+	if (!adev->uvd.saved_bo)
-+		return -ENOMEM;
-  
--        memcpy(adev->uvd.saved_bo, ptr, size);
-+	memcpy(adev->uvd.saved_bo, ptr, size);
- 
- 	return 0;
- }
-@@ -310,18 +312,18 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
- 		memcpy(ptr, adev->uvd.saved_bo, size);
- 		kfree(adev->uvd.saved_bo);
- 		adev->uvd.saved_bo = NULL;
--        } else {
--                const struct common_firmware_header *hdr;
--                unsigned offset;
-+	} else {
-+		const struct common_firmware_header *hdr;
-+		unsigned offset;
-  
--                hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
--                offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
--                memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
--                        (adev->uvd.fw->size) - offset);
--                size -= le32_to_cpu(hdr->ucode_size_bytes);
--                ptr += le32_to_cpu(hdr->ucode_size_bytes);
-+		hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
-+		offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-+		memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
-+			(adev->uvd.fw->size) - offset);
-+		size -= le32_to_cpu(hdr->ucode_size_bytes);
-+		ptr += le32_to_cpu(hdr->ucode_size_bytes);
- 		memset(ptr, 0, size);
--        }
-+	}
- 
- 	return 0;
- }
-@@ -331,15 +333,15 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
- 	struct amdgpu_ring *ring = &adev->uvd.ring;
- 	int i, r;
- 
--        for (i = 0; i < adev->uvd.max_handles; ++i) {
-+	for (i = 0; i < adev->uvd.max_handles; ++i) {
- 		uint32_t handle = atomic_read(&adev->uvd.handles[i]);
- 		if (handle != 0 && adev->uvd.filp[i] == filp) {
- 			struct fence *fence;
- 
- 			amdgpu_uvd_note_usage(adev);
- 
--                        r = amdgpu_uvd_get_destroy_msg(ring, handle,
--                                                      false, &fence);
-+			r = amdgpu_uvd_get_destroy_msg(ring, handle,
-+						       false, &fence);
- 			if (r) {
- 				DRM_ERROR("Error destroying UVD (%d)!\n", r);
- 				continue;
-@@ -591,7 +593,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 		amdgpu_bo_kunmap(bo);
- 
- 		/* try to alloc a new handle */
--                for (i = 0; i < adev->uvd.max_handles; ++i) {
-+		for (i = 0; i < adev->uvd.max_handles; ++i) {
- 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
- 				DRM_ERROR("Handle 0x%x already in use!\n", handle);
- 				return -EINVAL;
-@@ -614,7 +616,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 			return r;
- 
- 		/* validate the handle */
--                for (i = 0; i < adev->uvd.max_handles; ++i) {
-+		for (i = 0; i < adev->uvd.max_handles; ++i) {
- 			if (atomic_read(&adev->uvd.handles[i]) == handle) {
- 				if (adev->uvd.filp[i] != ctx->parser->filp) {
- 					DRM_ERROR("UVD handle collision detected!\n");
-@@ -629,7 +631,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
- 
- 	case 2:
- 		/* it's a destroy msg, free the handle */
--                for (i = 0; i < adev->uvd.max_handles; ++i)
-+		for (i = 0; i < adev->uvd.max_handles; ++i)
- 			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
- 		amdgpu_bo_kunmap(bo);
- 		return 0;
-@@ -739,7 +741,7 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
- static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
- 			     int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
- {
--        struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
-+	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
- 	int i, r;
- 
- 	ctx->idx++;
-@@ -785,7 +787,7 @@ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
- static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
- 				 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
- {
--        struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
-+	struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
- 	int r;
- 
- 	for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
-@@ -827,7 +829,7 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
- 		[0x00000003]	=	2048,
- 		[0x00000004]	=	0xFFFFFFFF,
- 	};
--        struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
-+	struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
- 	int r;
- 
- 	if (ib->length_dw % 16) {
-@@ -861,8 +863,7 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
- }
- 
- static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
--                              bool direct, struct fence **fence)
--
-+			       bool direct, struct fence **fence)
- {
- 	struct ttm_validate_buffer tv;
- 	struct ww_acquire_ctx ticket;
-@@ -892,6 +893,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
- 	if (r)
- 		goto err;
-+
- 	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
- 	if (r)
- 		goto err;
-@@ -908,19 +910,19 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 		ib->ptr[i] = PACKET2(0);
- 	ib->length_dw = 16;
- 
--        if (direct) {
--                r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
--                job->fence = f;
--                if (r)
--                        goto err_free;
-+	if (direct) {
-+		r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-+		job->fence = f;
-+		if (r)
-+			goto err_free;
- 
--                amdgpu_job_free(job);
--        } else {
--                r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
--                                      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
--                if (r)
--                        goto err_free;
--        }
-+		amdgpu_job_free(job);
-+	} else {
-+		r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
-+				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+		if (r)
-+			goto err_free;
-+	}
- 
- 	ttm_eu_fence_buffer_objects(&ticket, &head, f);
- 
-@@ -930,8 +932,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- 	fence_put(f);
- 
- 	return 0;
-+
- err_free:
- 	amdgpu_job_free(job);
-+
- err:
- 	ttm_eu_backoff_reservation(&ticket, &head);
- 	return r;
-@@ -986,11 +990,11 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	amdgpu_bo_kunmap(bo);
- 	amdgpu_bo_unreserve(bo);
- 
--        return amdgpu_uvd_send_msg(ring, bo, true, fence);
-+	return amdgpu_uvd_send_msg(ring, bo, true, fence);
- }
- 
- int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
--                              bool direct, struct fence **fence)
-+			       bool direct, struct fence **fence)
- {
- 	struct amdgpu_device *adev = ring->adev;
- 	struct amdgpu_bo *bo;
-@@ -1028,7 +1032,7 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	amdgpu_bo_kunmap(bo);
- 	amdgpu_bo_unreserve(bo);
- 
--        return amdgpu_uvd_send_msg(ring, bo, direct, fence);
-+	return amdgpu_uvd_send_msg(ring, bo, direct, fence);
- }
- 
- static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-index 7aa7342..e03b454 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
-@@ -51,7 +51,7 @@
- #define FIRMWARE_FIJI		"amdgpu/fiji_vce.bin"
- #define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"
- #define FIRMWARE_POLARIS10	"amdgpu/polaris10_vce.bin"
--#define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
-+#define FIRMWARE_POLARIS11	   "amdgpu/polaris11_vce.bin"
- 
- #ifdef CONFIG_DRM_AMDGPU_CIK
- MODULE_FIRMWARE(FIRMWARE_BONAIRE);
-@@ -78,8 +78,8 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work);
-  */
- int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
- {
--        struct amdgpu_ring *ring;
--        struct amd_sched_rq *rq;
-+	struct amdgpu_ring *ring;
-+	struct amd_sched_rq *rq;
- 	const char *fw_name;
- 	const struct common_firmware_header *hdr;
- 	unsigned ucode_version, version_major, version_minor, binary_id;
-@@ -183,14 +183,14 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
- 	}
- 
- 
--       ring = &adev->vce.ring[0];
--       rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
--       r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
--                                 rq, amdgpu_sched_jobs);
--       if (r != 0) {
--               DRM_ERROR("Failed setting up VCE run queue.\n");
--               return r;
--       }
-+	ring = &adev->vce.ring[0];
-+	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+	r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
-+				  rq, amdgpu_sched_jobs);
-+	if (r != 0) {
-+		DRM_ERROR("Failed setting up VCE run queue.\n");
-+		return r;
-+	}
- 
- 	for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
- 		atomic_set(&adev->vce.handles[i], 0);
-@@ -212,7 +212,7 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
- 	if (adev->vce.vcpu_bo == NULL)
- 		return 0;
- 
--        amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
-+	amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
- 
- 	amdgpu_bo_unref(&adev->vce.vcpu_bo);
- 
-@@ -362,7 +362,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
- 
- 		amdgpu_vce_note_usage(adev);
- 
--                r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
-+		r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
- 		if (r)
- 			DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
- 
-@@ -396,6 +396,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 		return r;
- 
- 	ib = &job->ibs[0];	
-+
- 	dummy = ib->gpu_addr + 1024;
- 
- 	/* stitch together an VCE create msg */
-@@ -435,16 +436,17 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	for (i = ib->length_dw; i < ib_size_dw; ++i)
- 		ib->ptr[i] = 0x0;
- 
--        r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
--                 job->fence = f;
-+	r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-+	job->fence = f;
- 	if (r)
- 		goto err;
-        
--	 amdgpu_job_free(job);
-+	amdgpu_job_free(job);
- 	if (fence)
- 		*fence = fence_get(f);
- 	fence_put(f);
- 	return 0;
-+
- err:
- 	amdgpu_job_free(job);
- 	return r;
-@@ -461,11 +463,11 @@ err:
-  * Close up a stream for HW test or if userspace failed to do so
-  */
- int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
--                               bool direct, struct fence **fence)
-+			       bool direct, struct fence **fence)
- {
- 	const unsigned ib_size_dw = 1024;
- 	struct amdgpu_job *job;
--        struct amdgpu_ib *ib;
-+	struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
- 	uint64_t dummy;
- 	int i, r;
-@@ -495,24 +497,25 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- 	for (i = ib->length_dw; i < ib_size_dw; ++i)
- 		ib->ptr[i] = 0x0;
- 
--       if (direct) {
--                r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
-+	if (direct) {
-+		r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
- 		job->fence = f;
--                if (r)
--                        goto err;
-+		if (r)
-+			goto err;
- 
--                amdgpu_job_free(job);
--        } else {
--                r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
--                                      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
--                if (r)
--                        goto err;
--        }
-+		amdgpu_job_free(job);
-+	} else {
-+		r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
-+				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+		if (r)
-+			goto err;
-+	}
- 
- 	if (fence)
- 		*fence = fence_get(f);
- 	fence_put(f);
- 	return 0;
-+
- err:
- 	amdgpu_job_free(job);
- 	return r;
-@@ -616,7 +619,7 @@ static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
-  */
- int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
- {
--        struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
-+	struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
- 	unsigned fb_idx = 0, bs_idx = 0;
- 	int session_idx = -1;
- 	bool destroyed = false;
-@@ -848,7 +851,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
- 		goto error;
- 	}
- 
--        r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
-+	r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
- 		goto error;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 7eee8ae..a583f36 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -22,8 +22,8 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  * Authors: Dave Airlie
-- *          Alex Deucher
-- *          Jerome Glisse
-+ *	    Alex Deucher
-+ *	    Jerome Glisse
-  */
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
-@@ -87,15 +87,15 @@ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
-  * validate for command submission.
-  */
- void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
--                        struct list_head *validated,
--                        struct amdgpu_bo_list_entry *entry)
-+			 struct list_head *validated,
-+			 struct amdgpu_bo_list_entry *entry)
- {
--        entry->robj = vm->page_directory;
--        entry->priority = 0;
--        entry->tv.bo = &vm->page_directory->tbo;
--        entry->tv.shared = true;
--        entry->user_pages = NULL;
--        list_add(&entry->tv.head, validated);
-+	entry->robj = vm->page_directory;
-+	entry->priority = 0;
-+	entry->tv.bo = &vm->page_directory->tbo;
-+	entry->tv.shared = true;
-+	entry->user_pages = NULL;
-+	list_add(&entry->tv.head, validated);
- }
- 
- /**
-@@ -110,16 +110,16 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-  */
- void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
- {
--        unsigned i;
-+	unsigned i;
- 
- 	/* add the vm page table to the list */
--        for (i = 0; i <= vm->max_pde_used; ++i) {
--                struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-+	for (i = 0; i <= vm->max_pde_used; ++i) {
-+		struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-  
--                if (!entry->robj)
-+		if (!entry->robj)
- 			continue;
- 
--                list_add(&entry->tv.head, duplicates);
-+		list_add(&entry->tv.head, duplicates);
- 	}
- }
- 
-@@ -132,21 +132,21 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
-  * Move the PT BOs to the tail of the LRU.
-  */
- void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
--                                  struct amdgpu_vm *vm)
-+				  struct amdgpu_vm *vm)
- {
--        struct ttm_bo_global *glob = adev->mman.bdev.glob;
--        unsigned i;
-+	struct ttm_bo_global *glob = adev->mman.bdev.glob;
-+	unsigned i;
-  
--        spin_lock(&glob->lru_lock);
--        for (i = 0; i <= vm->max_pde_used; ++i) {
--                struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-+	spin_lock(&glob->lru_lock);
-+	for (i = 0; i <= vm->max_pde_used; ++i) {
-+		struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-  
--                if (!entry->robj)
--                        continue;
-+		if (!entry->robj)
-+			continue;
-  
--                ttm_bo_move_to_lru_tail(&entry->robj->tbo);
--        }
--        spin_unlock(&glob->lru_lock);
-+		ttm_bo_move_to_lru_tail(&entry->robj->tbo);
-+	}
-+	spin_unlock(&glob->lru_lock);
- }
- 
- /**
-@@ -282,55 +282,55 @@ error:
-  * Emit a VM flush when it is necessary.
-  */
- int amdgpu_vm_flush(struct amdgpu_ring *ring,
--                    unsigned vm_id, uint64_t pd_addr,
--                    uint32_t gds_base, uint32_t gds_size,
--                    uint32_t gws_base, uint32_t gws_size,
--                    uint32_t oa_base, uint32_t oa_size)
-+		    unsigned vm_id, uint64_t pd_addr,
-+		    uint32_t gds_base, uint32_t gds_size,
-+		    uint32_t gws_base, uint32_t gws_size,
-+		    uint32_t oa_base, uint32_t oa_size)
- {
--        struct amdgpu_device *adev = ring->adev;
--        struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
--        bool gds_switch_needed = ring->funcs->emit_gds_switch && (
--                id->gds_base != gds_base ||
--                id->gds_size != gds_size ||
--                id->gws_base != gws_base ||
--                id->gws_size != gws_size ||
--                id->oa_base != oa_base ||
--                id->oa_size != oa_size);
--        int r;
--
--        if (ring->funcs->emit_pipeline_sync && (
--           pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
--                    ring->type == AMDGPU_RING_TYPE_COMPUTE))
--               amdgpu_ring_emit_pipeline_sync(ring);
--
--        if (ring->funcs->emit_vm_flush &&
--            pd_addr != AMDGPU_VM_NO_FLUSH) {
--                struct fence *fence;
-+	struct amdgpu_device *adev = ring->adev;
-+	struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
-+	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
-+		id->gds_base != gds_base ||
-+		id->gds_size != gds_size ||
-+		id->gws_base != gws_base ||
-+		id->gws_size != gws_size ||
-+		id->oa_base != oa_base ||
-+		id->oa_size != oa_size);
-+	int r;
-+
-+	if (ring->funcs->emit_pipeline_sync && (
-+	    pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
-+	    ring->type == AMDGPU_RING_TYPE_COMPUTE))
-+	       amdgpu_ring_emit_pipeline_sync(ring);
-+
-+	if (ring->funcs->emit_vm_flush &&
-+	    pd_addr != AMDGPU_VM_NO_FLUSH) {
-+		struct fence *fence;
- 
- 		trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
- 		amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
-  
--                mutex_lock(&adev->vm_manager.lock);
--                if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) {
--                        r = amdgpu_fence_emit(ring, &fence);
--                        if (r) {
--                                mutex_unlock(&adev->vm_manager.lock);
--                                return r;
--                        }
--                        fence_put(id->last_flush);
--                        id->last_flush = fence;
--                }
--                mutex_unlock(&adev->vm_manager.lock);
-+		mutex_lock(&adev->vm_manager.lock);
-+		if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) {
-+			r = amdgpu_fence_emit(ring, &fence);
-+			if (r) {
-+				mutex_unlock(&adev->vm_manager.lock);
-+				return r;
-+			}
-+			fence_put(id->last_flush);
-+			id->last_flush = fence;
-+		}
-+		mutex_unlock(&adev->vm_manager.lock);
- 	}
- 
--        if (gds_switch_needed) {
--                id->gds_base = gds_base;
--                id->gds_size = gds_size;
--                id->gws_base = gws_base;
--                id->gws_size = gws_size;
--                id->oa_base = oa_base;
--                id->oa_size = oa_size;
--	       amdgpu_ring_emit_gds_switch(ring, vm_id,
-+	if (gds_switch_needed) {
-+		id->gds_base = gds_base;
-+		id->gds_size = gds_size;
-+		id->gws_base = gws_base;
-+		id->gws_size = gws_size;
-+		id->oa_base = oa_base;
-+		id->oa_size = oa_size;
-+		amdgpu_ring_emit_gds_switch(ring, vm_id,
- 					    gds_base, gds_size,
- 					    gws_base, gws_size,
- 					    oa_base, oa_size);
-@@ -349,14 +349,14 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
-  */
- void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
- {
--       struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
--
--       id->gds_base = 0;
--       id->gds_size = 0;
--       id->gws_base = 0;
--       id->gws_size = 0;
--       id->oa_base = 0;
--       id->oa_size = 0;
-+	struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
-+
-+	id->gds_base = 0;
-+	id->gds_size = 0;
-+	id->gws_base = 0;
-+	id->gws_size = 0;
-+	id->oa_base = 0;
-+	id->oa_size = 0;
- }
- 
- /**
-@@ -437,17 +437,17 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
-  * need to reserve bo first before calling it.
-  */
- static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
--                              struct amdgpu_vm *vm,
-+			      struct amdgpu_vm *vm,
- 			      struct amdgpu_bo *bo)
- {
--        struct amdgpu_ring *ring;
-+	struct amdgpu_ring *ring;
- 	struct fence *fence = NULL;
--        struct amdgpu_job *job;
-+	struct amdgpu_job *job;
- 	unsigned entries;
- 	uint64_t addr;
- 	int r;
- 
--        ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-+	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
- 
- 	r = reservation_object_reserve_shared(bo->tbo.resv);
- 	if (r)
-@@ -460,25 +460,25 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- 	addr = amdgpu_bo_gpu_offset(bo);
- 	entries = amdgpu_bo_size(bo) / 8;
- 
--        r = amdgpu_job_alloc_with_ib(adev, 64, &job);
--        if (r)
-+	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
-+	if (r)
- 		goto error;
--        amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries,
--                                0, 0);
--        amdgpu_ring_pad_ib(ring, &job->ibs[0]);
-+	amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries,
-+			       0, 0);
-+	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
- 
--        WARN_ON(job->ibs[0].length_dw > 64);
--        r = amdgpu_job_submit(job, ring, &vm->entity,
--                              AMDGPU_FENCE_OWNER_VM, &fence);
-+	WARN_ON(job->ibs[0].length_dw > 64);
-+	r = amdgpu_job_submit(job, ring, &vm->entity,
-+			      AMDGPU_FENCE_OWNER_VM, &fence);
- 	if (r)
- 		goto error_free;
- 
--        amdgpu_bo_fence(bo, fence, true);
-+	amdgpu_bo_fence(bo, fence, true);
- 	fence_put(fence);
- 	return 0;
- 
- error_free:
--        amdgpu_job_free(job);
-+	amdgpu_job_free(job);
- error:
- 	return r;
- }
-@@ -528,32 +528,32 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
- int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				    struct amdgpu_vm *vm)
- {
--        struct amdgpu_ring *ring;
-+	struct amdgpu_ring *ring;
- 	struct amdgpu_bo *pd = vm->page_directory;
- 	uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
- 	uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
- 	uint64_t last_pde = ~0, last_pt = ~0;
- 	unsigned count = 0, pt_idx, ndw;
--        struct amdgpu_job *job;
-+	struct amdgpu_job *job;
- 	struct amdgpu_ib *ib;
- 	struct fence *fence = NULL;
- 
- 	int r;
--        ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-+	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
- 
- 	/* padding, etc. */
- 	ndw = 64;
- 
- 	/* assume the worst case */
- 	ndw += vm->max_pde_used * 6;
--        r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
--        if (r)
-+	r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
-+	if (r)
- 		return r;
- 
--        ib = &job->ibs[0];
-+	ib = &job->ibs[0];
- 	/* walk over the address space and update the page directory */
- 	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
--                struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
-+		struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
- 		uint64_t pde, pt;
- 
- 		if (bo == NULL)
-@@ -588,12 +588,12 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 				       count, incr, AMDGPU_PTE_VALID);
- 
- 	if (ib->length_dw != 0) {
--                amdgpu_ring_pad_ib(ring, ib);
--                amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
--                                 AMDGPU_FENCE_OWNER_VM);
-+		amdgpu_ring_pad_ib(ring, ib);
-+		amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
-+				 AMDGPU_FENCE_OWNER_VM);
- 		WARN_ON(ib->length_dw > ndw);
--                r = amdgpu_job_submit(job, ring, &vm->entity,
--                                      AMDGPU_FENCE_OWNER_VM, &fence);
-+		r = amdgpu_job_submit(job, ring, &vm->entity,
-+				      AMDGPU_FENCE_OWNER_VM, &fence);
- 		if (r)
- 			goto error_free;
- 
-@@ -601,14 +601,14 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
- 		fence_put(vm->page_directory_fence);
- 		vm->page_directory_fence = fence_get(fence);
- 		fence_put(fence);
--        } else {
--                amdgpu_job_free(job);
-+	} else {
-+		amdgpu_job_free(job);
- 	}
- 
- 	return 0;
- 
- error_free:
--        amdgpu_job_free(job);
-+	amdgpu_job_free(job);
- 	return r;
- }
- 
-@@ -627,8 +627,8 @@ error_free:
-  * Global and local mutex must be locked!
-  */
- static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
--                                uint64_t src,
--                                dma_addr_t *pages_addr,
-+				uint64_t src,
-+				dma_addr_t *pages_addr,
- 				struct amdgpu_ib *ib,
- 				uint64_t pe_start, uint64_t pe_end,
- 				uint64_t addr, uint32_t flags)
-@@ -661,16 +661,16 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
- 
- 	unsigned count;
- 
--        /* Abort early if there isn't anything to do */
--        if (pe_start == pe_end)
--                return;
-+	/* Abort early if there isn't anything to do */
-+	if (pe_start == pe_end)
-+		return;
- 
- 	/* system pages are non continuously */
--        if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) ||
--            (frag_start >= frag_end)) {
-+	if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) ||
-+	    (frag_start >= frag_end)) {
- 
- 		count = (pe_end - pe_start) / 8;
--                amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start,
-+		amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start,
- 				       addr, count, AMDGPU_GPU_PAGE_SIZE,
- 				       flags);
- 		return;
-@@ -713,52 +713,52 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-  * Update the page tables in the range @start - @end.
-  */
- static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
--                                  uint64_t src,
--                                  dma_addr_t *pages_addr,
--                                  struct amdgpu_vm *vm,
--                                  struct amdgpu_ib *ib,
--                                  uint64_t start, uint64_t end,
--                                  uint64_t dst, uint32_t flags)
-+				  uint64_t src,
-+				  dma_addr_t *pages_addr,
-+				  struct amdgpu_vm *vm,
-+				  struct amdgpu_ib *ib,
-+				  uint64_t start, uint64_t end,
-+				  uint64_t dst, uint32_t flags)
- {
--        const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
-+	const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
-  
--        uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0;
-+	uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0;
- 	uint64_t addr;
- 
- 	/* walk over the address space and update the page tables */
- 	for (addr = start; addr < end; ) {
- 		uint64_t pt_idx = addr >> amdgpu_vm_block_size;
--                struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
-+		struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
- 		unsigned nptes;
--                uint64_t pe_start;
-+		uint64_t pe_start;
- 
- 		if ((addr & ~mask) == (end & ~mask))
- 			nptes = end - addr;
- 		else
- 			nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
- 
--                pe_start = amdgpu_bo_gpu_offset(pt);
--                pe_start += (addr & mask) * 8;
-+		pe_start = amdgpu_bo_gpu_offset(pt);
-+		pe_start += (addr & mask) * 8;
- 
--                if (last_pe_end != pe_start) {
-+		if (last_pe_end != pe_start) {
- 
--                        amdgpu_vm_frag_ptes(adev, src, pages_addr, ib,
--                                            last_pe_start, last_pe_end,
--                                            last_dst, flags);
-+			amdgpu_vm_frag_ptes(adev, src, pages_addr, ib,
-+					    last_pe_start, last_pe_end,
-+					    last_dst, flags);
-  
--                        last_pe_start = pe_start;
--                        last_pe_end = pe_start + 8 * nptes;
-+			last_pe_start = pe_start;
-+			last_pe_end = pe_start + 8 * nptes;
- 			last_dst = dst;
- 		} else {
--                        last_pe_end += 8 * nptes;
-+			last_pe_end += 8 * nptes;
- 		}
- 
- 		addr += nptes;
- 		dst += nptes * AMDGPU_GPU_PAGE_SIZE;
- 	}
- 
--        amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start,
--                           last_pe_end, last_dst, flags);
-+	amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start,
-+			   last_pe_end, last_dst, flags);
- }
- 
- /**
-@@ -785,19 +785,19 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 				       uint32_t flags, uint64_t addr,
- 				       struct fence **fence)
- {
--        struct amdgpu_ring *ring;
--        void *owner = AMDGPU_FENCE_OWNER_VM;
-+	struct amdgpu_ring *ring;
-+	void *owner = AMDGPU_FENCE_OWNER_VM;
- 	unsigned nptes, ncmds, ndw;
--        struct amdgpu_job *job;
-+	struct amdgpu_job *job;
- 	struct amdgpu_ib *ib;
- 	struct fence *f = NULL;
- 	int r;
- 
--        ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-+	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
- 
--        /* sync to everything on unmapping */
--        if (!(flags & AMDGPU_PTE_VALID))
--                owner = AMDGPU_FENCE_OWNER_UNDEFINED;
-+	/* sync to everything on unmapping */
-+	if (!(flags & AMDGPU_PTE_VALID))
-+		owner = AMDGPU_FENCE_OWNER_UNDEFINED;
-  
- 	nptes = last - start + 1;
- 
-@@ -828,29 +828,29 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 		/* two extra commands for begin/end of fragment */
- 		ndw += 2 * 10;
- 	}
--        r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
--        if (r)
-+	r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
-+	if (r)
- 
- 		return r;
- 
--        ib = &job->ibs[0];
-+	ib = &job->ibs[0];
- 
--        r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
--                             owner);
--        if (r)
--                goto error_free;
-+	r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
-+			     owner);
-+	if (r)
-+		goto error_free;
- 
--        r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
--        if (r)
--                goto error_free;
-+	r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
-+	if (r)
-+		goto error_free;
-  
--        amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start,
--                              last + 1, addr, flags);
-+	amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start,
-+			      last + 1, addr, flags);
- 
--        amdgpu_ring_pad_ib(ring, ib);
-+	amdgpu_ring_pad_ib(ring, ib);
- 	WARN_ON(ib->length_dw > ndw);
--        r = amdgpu_job_submit(job, ring, &vm->entity,
--                              AMDGPU_FENCE_OWNER_VM, &f);
-+	r = amdgpu_job_submit(job, ring, &vm->entity,
-+			      AMDGPU_FENCE_OWNER_VM, &f);
- 	if (r)
- 		goto error_free;
- 
-@@ -863,7 +863,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 	return 0;
- 
- error_free:
--        amdgpu_job_free(job);
-+	amdgpu_job_free(job);
- 	return r;
- }
- 
-@@ -1205,11 +1205,11 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 	/* walk over the address space and allocate the page tables */
- 	for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
- 		struct reservation_object *resv = vm->page_directory->tbo.resv;
--                struct amdgpu_bo_list_entry *entry;
-+		struct amdgpu_bo_list_entry *entry;
- 		struct amdgpu_bo *pt;
- 
--                entry = &vm->page_tables[pt_idx].entry;
--                if (entry->robj)
-+		entry = &vm->page_tables[pt_idx].entry;
-+		if (entry->robj)
- 			continue;
- 
- 		r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
-@@ -1225,17 +1225,17 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
- 		 */
- 		pt->parent = amdgpu_bo_ref(vm->page_directory);
- 
--                r = amdgpu_vm_clear_bo(adev, vm, pt);
-+		r = amdgpu_vm_clear_bo(adev, vm, pt);
- 		if (r) {
- 			amdgpu_bo_unref(&pt);
- 			goto error_free;
- 		}
- 
--                entry->robj = pt;
--                entry->priority = 0;
--                entry->tv.bo = &entry->robj->tbo;
--                entry->tv.shared = true;
--                entry->user_pages = NULL;
-+		entry->robj = pt;
-+		entry->priority = 0;
-+		entry->tv.bo = &entry->robj->tbo;
-+		entry->tv.shared = true;
-+		entry->user_pages = NULL;
- 		vm->page_tables[pt_idx].addr = 0;
- 	}
- 
-@@ -1375,16 +1375,15 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
- 		AMDGPU_VM_PTE_COUNT * 8);
- 	unsigned pd_size, pd_entries;
--        unsigned ring_instance;
--        struct amdgpu_ring *ring;
--
--        struct amd_sched_rq *rq;
-+	unsigned ring_instance;
-+	struct amdgpu_ring *ring;
-+	struct amd_sched_rq *rq;
- 	int i, r;
- 
--        for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
--               vm->ids[i] = NULL;
-+	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-+		vm->ids[i] = NULL;
- 	vm->va = RB_ROOT;
--        vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
-+	vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
- 	spin_lock_init(&vm->status_lock);
- 	INIT_LIST_HEAD(&vm->invalidated);
- 	INIT_LIST_HEAD(&vm->cleared);
-@@ -1400,16 +1399,16 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 		return -ENOMEM;
- 	}
- 
--        /* create scheduler entity for page table updates */
-+	/* create scheduler entity for page table updates */
- 
--        ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
--        ring_instance %= adev->vm_manager.vm_pte_num_rings;
--        ring = adev->vm_manager.vm_pte_rings[ring_instance];
--        rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
--        r = amd_sched_entity_init(&ring->sched, &vm->entity,
--                                  rq, amdgpu_sched_jobs);
--        if (r)
--                return r;
-+	ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
-+	ring_instance %= adev->vm_manager.vm_pte_num_rings;
-+	ring = adev->vm_manager.vm_pte_rings[ring_instance];
-+	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
-+	r = amd_sched_entity_init(&ring->sched, &vm->entity,
-+				  rq, amdgpu_sched_jobs);
-+	if (r)
-+		return r;
- 
- 	vm->page_directory_fence = NULL;
- 
-@@ -1418,27 +1417,27 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 			     AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
- 			     NULL, NULL, &vm->page_directory);
- 	if (r)
--                goto error_free_sched_entity;
-+		goto error_free_sched_entity;
- 
- 	r = amdgpu_bo_reserve(vm->page_directory, false);
- 	if (r)
--                goto error_free_page_directory;
-+		goto error_free_page_directory;
- 
- 	r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
- 	amdgpu_bo_unreserve(vm->page_directory);
--        if (r)
--                goto error_free_page_directory;
-+	if (r)
-+		goto error_free_page_directory;
- 
- 	return 0;
- 
- error_free_page_directory:
--        amdgpu_bo_unref(&vm->page_directory);
--        vm->page_directory = NULL;
-+	amdgpu_bo_unref(&vm->page_directory);
-+	vm->page_directory = NULL;
- 
- error_free_sched_entity:
--        amd_sched_entity_fini(&ring->sched, &vm->entity);
-+	amd_sched_entity_fini(&ring->sched, &vm->entity);
- 
--       return r;
-+	return r;
- }
- 
- /**
-@@ -1455,7 +1454,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	struct amdgpu_bo_va_mapping *mapping, *tmp;
- 	int i;
- 
--        amd_sched_entity_fini(vm->entity.sched, &vm->entity);
-+	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
- 
- 	if (!RB_EMPTY_ROOT(&vm->va)) {
- 		dev_err(adev->dev, "still active bo inside vm\n");
-@@ -1471,12 +1470,11 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- 	}
- 
- 	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
--                amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
-+		amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
- 	drm_free_large(vm->page_tables);
- 
- 	amdgpu_bo_unref(&vm->page_directory);
- 	fence_put(vm->page_directory_fence);
--
- }
- 
- /**
-@@ -1493,14 +1491,14 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
- 	INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
- 
- 	/* skip over VMID 0, since it is the system VM */
--        for (i = 1; i < adev->vm_manager.num_ids; ++i) {
--		 amdgpu_vm_reset_id(adev, i);
--                 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
-+	for (i = 1; i < adev->vm_manager.num_ids; ++i) {
-+		amdgpu_vm_reset_id(adev, i);
-+		amdgpu_sync_create(&adev->vm_manager.ids[i].active);
- 		list_add_tail(&adev->vm_manager.ids[i].list,
- 			      &adev->vm_manager.ids_lru);
--        }
-+	}
- 
--        atomic64_set(&adev->vm_manager.client_counter, 0);
-+	atomic64_set(&adev->vm_manager.client_counter, 0);
- }
- 
- /**
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 03e89d2..85e78b8 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -636,7 +636,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 	memset(&ib, 0, sizeof(ib));
--        r = amdgpu_ib_get(adev, NULL, 256, &ib);
-+	r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err0;
-@@ -648,7 +648,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[3] = 1;
- 	ib.ptr[4] = 0xDEADBEEF;
- 	ib.length_dw = 5;
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-@@ -1359,14 +1359,14 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
- 
- static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
- {
--        unsigned i;
-+	unsigned i;
- 
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
--                for (i = 0; i < adev->sdma.num_instances; i++)
--                        adev->vm_manager.vm_pte_rings[i] =
--                                &adev->sdma.instance[i].ring;
-+		for (i = 0; i < adev->sdma.num_instances; i++)
-+			adev->vm_manager.vm_pte_rings[i] =
-+				&adev->sdma.instance[i].ring;
-  
--                adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
-+		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 356a389..0d01c0b 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -1675,9 +1675,9 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
- 
- 	/*
- 	 * Configure apertures:
--	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
--	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
--	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
-+	 * LDS:		0x60000000'00000000 - 0x60000001'00000000 (4GB)
-+	 * Scratch:	0x60000001'00000000 - 0x60000002'00000000 (4GB)
-+	 * GPUVM:	0x60010000'00000000 - 0x60020000'00000000 (1TB)
- 	*/
- 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
- 	sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
-@@ -2125,7 +2125,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	}
- 	WREG32(scratch, 0xCAFEDEAD);
- 	memset(&ib, 0, sizeof(ib));
--        r = amdgpu_ib_get(adev, NULL, 256, &ib);
-+	r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err1;
-@@ -2135,7 +2135,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err2;
- 
-@@ -2626,7 +2626,7 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
- 	u32 *hpd;
- 
- 	/*
--	 * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
-+	 * KV:	  2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
- 	 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
- 	 * Nonetheless, we assign only 1 pipe because all other pipes will
- 	 * be handled by KFD
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 3d1a5ee..92f3ee6 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -66,12 +66,12 @@
- #define MACRO_TILE_ASPECT(x)				((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
- #define NUM_BANKS(x)					((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
- 
--#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
--#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
--#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
--#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
--#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
--#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
-+#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK	    0x00000001L
-+#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK	    0x00000002L
-+#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK	    0x00000004L
-+#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK	    0x00000008L
-+#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK	    0x00000010L
-+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK	    0x00000020L
- 
- /* BPM SERDES CMD */
- #define SET_BPM_SERDES_CMD    1
-@@ -79,15 +79,15 @@
- 
- /* BPM Register Address*/
- enum {
--	BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
--	BPM_REG_CGLS_ON,            /* ON/OFF CGLS: shall be controlled by RLC FW */
--	BPM_REG_CGCG_OVERRIDE,      /* Set/Clear CGCG Override */
--	BPM_REG_MGCG_OVERRIDE,      /* Set/Clear MGCG Override */
--	BPM_REG_FGCG_OVERRIDE,      /* Set/Clear FGCG Override */
-+	BPM_REG_CGLS_EN = 0,	    /* Enable/Disable CGLS */
-+	BPM_REG_CGLS_ON,	    /* ON/OFF CGLS: shall be controlled by RLC FW */
-+	BPM_REG_CGCG_OVERRIDE,	    /* Set/Clear CGCG Override */
-+	BPM_REG_MGCG_OVERRIDE,	    /* Set/Clear MGCG Override */
-+	BPM_REG_FGCG_OVERRIDE,	    /* Set/Clear FGCG Override */
- 	BPM_REG_FGCG_MAX
- };
- 
--#define RLC_FormatDirectRegListLength        14
-+#define RLC_FormatDirectRegListLength	     14
- 
- MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
- MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
-@@ -791,7 +791,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	}
- 	WREG32(scratch, 0xCAFEDEAD);
- 	memset(&ib, 0, sizeof(ib));
--        r = amdgpu_ib_get(adev, NULL, 256, &ib);
-+	r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err1;
-@@ -801,7 +801,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[2] = 0xDEADBEEF;
- 	ib.length_dw = 3;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err2;
- 
-@@ -1192,7 +1192,7 @@ static void cz_init_cp_jump_table(struct amdgpu_device *adev)
- 				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
- 			table_offset = le32_to_cpu(hdr->jt_offset);
- 			table_size = le32_to_cpu(hdr->jt_size);
--		} else  if (me == 4) {
-+		} else	if (me == 4) {
- 			const struct gfx_firmware_header_v1_0 *hdr =
- 				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
- 			fw_data = (const __le32 *)
-@@ -1296,7 +1296,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
- 
- 	if ((adev->asic_type == CHIP_CARRIZO) ||
- 	    (adev->asic_type == CHIP_STONEY)) {
--                adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
-+		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
- 		if (adev->gfx.rlc.cp_table_obj == NULL) {
- 			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
- 					     AMDGPU_GEM_DOMAIN_VRAM,
-@@ -1592,7 +1592,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 
- 	/* allocate an indirect buffer to put the commands in */
- 	memset(&ib, 0, sizeof(ib));
--        r = amdgpu_ib_get(adev, NULL, total_size, &ib);
-+	r = amdgpu_ib_get(adev, NULL, total_size, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		return r;
-@@ -1687,7 +1687,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
- 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
- 
- 	/* shedule the ib on the ring */
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r) {
- 		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
- 		goto fail;
-@@ -3525,9 +3525,9 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
- 
- 	/*
- 	 * Configure apertures:
--	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
--	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
--	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
-+	 * LDS:		0x60000000'00000000 - 0x60000001'00000000 (4GB)
-+	 * Scratch:	0x60000001'00000000 - 0x60000002'00000000 (4GB)
-+	 * GPUVM:	0x60010000'00000000 - 0x60020000'00000000 (1TB)
- 	 */
- 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
- 
-@@ -3796,80 +3796,80 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
- 
- static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
- {
--        uint32_t data;
-+	uint32_t data;
-  
--        if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
--                              AMDGPU_PG_SUPPORT_GFX_SMG |
--                              AMDGPU_PG_SUPPORT_GFX_DMG)) {
--                data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
--                data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
--                data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
--                WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
-+	if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
-+			      AMDGPU_PG_SUPPORT_GFX_SMG |
-+			      AMDGPU_PG_SUPPORT_GFX_DMG)) {
-+		data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
-+		data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
-+		data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
-+		WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
-  
--                data = 0;
--                data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
--                data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
--                data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
--                data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
--                WREG32(mmRLC_PG_DELAY, data);
-+		data = 0;
-+		data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
-+		data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
-+		data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
-+		data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
-+		WREG32(mmRLC_PG_DELAY, data);
-  
--                data = RREG32(mmRLC_PG_DELAY_2);
--                data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
--                data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
--                WREG32(mmRLC_PG_DELAY_2, data);
-+		data = RREG32(mmRLC_PG_DELAY_2);
-+		data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
-+		data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
-+		WREG32(mmRLC_PG_DELAY_2, data);
-  
--                data = RREG32(mmRLC_AUTO_PG_CTRL);
--                data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
--                data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
--                WREG32(mmRLC_AUTO_PG_CTRL, data);
--        }
-+		data = RREG32(mmRLC_AUTO_PG_CTRL);
-+		data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
-+		data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
-+		WREG32(mmRLC_AUTO_PG_CTRL, data);
-+	}
-  }
- 
- static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
--                                               bool enable)
-+					       bool enable)
- {
--        u32 data, orig;
-+	u32 data, orig;
-  
--        orig = data = RREG32(mmRLC_PG_CNTL);
-+	orig = data = RREG32(mmRLC_PG_CNTL);
-  
--        if (enable)
--                data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
--        else
--                data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
-+	if (enable)
-+		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
-+	else
-+		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
-  
--        if (orig != data)
--                WREG32(mmRLC_PG_CNTL, data);
-+	if (orig != data)
-+		WREG32(mmRLC_PG_CNTL, data);
- }
- 
- static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
--                                                 bool enable)
-+						 bool enable)
- {
--        u32 data, orig;
-+	u32 data, orig;
-  
--        orig = data = RREG32(mmRLC_PG_CNTL);
-+	orig = data = RREG32(mmRLC_PG_CNTL);
-  
--        if (enable)
--                data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
--        else
--                data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-+	if (enable)
-+		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-+	else
-+		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-  
--        if (orig != data)
--                WREG32(mmRLC_PG_CNTL, data);
-+	if (orig != data)
-+		WREG32(mmRLC_PG_CNTL, data);
- }
- 
- static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
- {
--        u32 data, orig;
-+	u32 data, orig;
-  
--        orig = data = RREG32(mmRLC_PG_CNTL);
-+	orig = data = RREG32(mmRLC_PG_CNTL);
-  
--        if (enable)
--                data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
--        else
--                data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
-+	if (enable)
-+		data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
-+	else
-+		data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
-  
--        if (orig != data)
--                WREG32(mmRLC_PG_CNTL, data);
-+	if (orig != data)
-+		WREG32(mmRLC_PG_CNTL, data);
-  }
- 
- static void polaris11_init_power_gating(struct amdgpu_device *adev)
-@@ -3877,8 +3877,8 @@ static void polaris11_init_power_gating(struct amdgpu_device *adev)
- 	uint32_t data;
- 
- 	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
--			AMD_PG_SUPPORT_GFX_SMG |
--			AMD_PG_SUPPORT_GFX_DMG)) {
-+			      AMD_PG_SUPPORT_GFX_SMG |
-+			      AMD_PG_SUPPORT_GFX_DMG)) {
- 		data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
- 		data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
- 		data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
-@@ -3915,27 +3915,27 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
- 		gfx_v8_0_init_save_restore_list(adev);
- 		gfx_v8_0_enable_save_restore_machine(adev);
-  
--                if ((adev->asic_type == CHIP_CARRIZO) ||
--                    (adev->asic_type == CHIP_STONEY)) {
--                        struct amdgpu_cu_info cu_info;
-+		if ((adev->asic_type == CHIP_CARRIZO) ||
-+		    (adev->asic_type == CHIP_STONEY)) {
-+			struct amdgpu_cu_info cu_info;
-  
--                        gfx_v8_0_get_cu_info(adev, &cu_info);
-+			gfx_v8_0_get_cu_info(adev, &cu_info);
-  
--                        WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
--                        gfx_v8_0_init_power_gating(adev);
--                        WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask);
-- 			if (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS) {
--                                cz_enable_sck_slow_down_on_power_up(adev, true);
--                                cz_enable_sck_slow_down_on_power_down(adev, true);
--                        } else {
--                                cz_enable_sck_slow_down_on_power_up(adev, false);
--                                cz_enable_sck_slow_down_on_power_down(adev, false);
--                        }
--                        if (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)
--                                cz_enable_cp_power_gating(adev, true);
--                        else
--                                cz_enable_cp_power_gating(adev, false);
--                } else if (adev->asic_type == CHIP_POLARIS11) {
-+			WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-+			gfx_v8_0_init_power_gating(adev);
-+			WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, cu_info.ao_cu_mask);
-+			if (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS) {
-+				cz_enable_sck_slow_down_on_power_up(adev, true);
-+				cz_enable_sck_slow_down_on_power_down(adev, true);
-+			} else {
-+				cz_enable_sck_slow_down_on_power_up(adev, false);
-+				cz_enable_sck_slow_down_on_power_down(adev, false);
-+			}
-+			if (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)
-+				cz_enable_cp_power_gating(adev, true);
-+			else
-+				cz_enable_cp_power_gating(adev, false);
-+		} else if (adev->asic_type == CHIP_POLARIS11) {
- 			polaris11_init_power_gating(adev);
- 		}
- 	}
-@@ -4387,9 +4387,9 @@ struct vi_mqd {
- 	uint32_t compute_start_x;  /* ordinal5 */
- 	uint32_t compute_start_y;  /* ordinal6 */
- 	uint32_t compute_start_z;  /* ordinal7 */
--	uint32_t compute_num_thread_x;  /* ordinal8 */
--	uint32_t compute_num_thread_y;  /* ordinal9 */
--	uint32_t compute_num_thread_z;  /* ordinal10 */
-+	uint32_t compute_num_thread_x;	/* ordinal8 */
-+	uint32_t compute_num_thread_y;	/* ordinal9 */
-+	uint32_t compute_num_thread_z;	/* ordinal10 */
- 	uint32_t compute_pipelinestat_enable;  /* ordinal11 */
- 	uint32_t compute_perfcount_enable;  /* ordinal12 */
- 	uint32_t compute_pgm_lo;  /* ordinal13 */
-@@ -4400,11 +4400,11 @@ struct vi_mqd {
- 	uint32_t compute_tma_hi;  /* ordinal18 */
- 	uint32_t compute_pgm_rsrc1;  /* ordinal19 */
- 	uint32_t compute_pgm_rsrc2;  /* ordinal20 */
--	uint32_t compute_vmid;  /* ordinal21 */
-+	uint32_t compute_vmid;	/* ordinal21 */
- 	uint32_t compute_resource_limits;  /* ordinal22 */
- 	uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
- 	uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
--	uint32_t compute_tmpring_size;  /* ordinal25 */
-+	uint32_t compute_tmpring_size;	/* ordinal25 */
- 	uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
- 	uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
- 	uint32_t compute_restart_x;  /* ordinal28 */
-@@ -4415,9 +4415,9 @@ struct vi_mqd {
- 	uint32_t compute_dispatch_id;  /* ordinal33 */
- 	uint32_t compute_threadgroup_id;  /* ordinal34 */
- 	uint32_t compute_relaunch;  /* ordinal35 */
--	uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
--	uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
--	uint32_t compute_wave_restore_control;  /* ordinal38 */
-+	uint32_t compute_wave_restore_addr_lo;	/* ordinal36 */
-+	uint32_t compute_wave_restore_addr_hi;	/* ordinal37 */
-+	uint32_t compute_wave_restore_control;	/* ordinal38 */
- 	uint32_t reserved9;  /* ordinal39 */
- 	uint32_t reserved10;  /* ordinal40 */
- 	uint32_t reserved11;  /* ordinal41 */
-@@ -4454,21 +4454,21 @@ struct vi_mqd {
- 	uint32_t compute_user_data_7;  /* ordinal72 */
- 	uint32_t compute_user_data_8;  /* ordinal73 */
- 	uint32_t compute_user_data_9;  /* ordinal74 */
--	uint32_t compute_user_data_10;  /* ordinal75 */
--	uint32_t compute_user_data_11;  /* ordinal76 */
--	uint32_t compute_user_data_12;  /* ordinal77 */
--	uint32_t compute_user_data_13;  /* ordinal78 */
--	uint32_t compute_user_data_14;  /* ordinal79 */
--	uint32_t compute_user_data_15;  /* ordinal80 */
-+	uint32_t compute_user_data_10;	/* ordinal75 */
-+	uint32_t compute_user_data_11;	/* ordinal76 */
-+	uint32_t compute_user_data_12;	/* ordinal77 */
-+	uint32_t compute_user_data_13;	/* ordinal78 */
-+	uint32_t compute_user_data_14;	/* ordinal79 */
-+	uint32_t compute_user_data_15;	/* ordinal80 */
- 	uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
- 	uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
- 	uint32_t reserved35;  /* ordinal83 */
- 	uint32_t reserved36;  /* ordinal84 */
- 	uint32_t reserved37;  /* ordinal85 */
--	uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
--	uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
--	uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
--	uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
-+	uint32_t cp_mqd_query_time_lo;	/* ordinal86 */
-+	uint32_t cp_mqd_query_time_hi;	/* ordinal87 */
-+	uint32_t cp_mqd_connect_start_time_lo;	/* ordinal88 */
-+	uint32_t cp_mqd_connect_start_time_hi;	/* ordinal89 */
- 	uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
- 	uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
- 	uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
-@@ -4481,8 +4481,8 @@ struct vi_mqd {
- 	uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
- 	uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
- 	uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
--	uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
--	uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
-+	uint32_t cp_mqd_restore_start_time_lo;	/* ordinal102 */
-+	uint32_t cp_mqd_restore_start_time_hi;	/* ordinal103 */
- 	uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
- 	uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
- 	uint32_t reserved40;  /* ordinal106 */
-@@ -4512,7 +4512,7 @@ struct vi_mqd {
- 	uint32_t cp_hqd_active;  /* ordinal130 */
- 	uint32_t cp_hqd_vmid;  /* ordinal131 */
- 	uint32_t cp_hqd_persistent_state;  /* ordinal132 */
--	uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
-+	uint32_t cp_hqd_pipe_priority;	/* ordinal133 */
- 	uint32_t cp_hqd_queue_priority;  /* ordinal134 */
- 	uint32_t cp_hqd_quantum;  /* ordinal135 */
- 	uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
-@@ -4550,15 +4550,15 @@ struct vi_mqd {
- 	uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
- 	uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
- 	uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
--	uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
--	uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
-+	uint32_t cp_hqd_ctx_save_base_addr_lo;	/* ordinal171 */
-+	uint32_t cp_hqd_ctx_save_base_addr_hi;	/* ordinal172 */
- 	uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
- 	uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
- 	uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
- 	uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
--	uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
-+	uint32_t cp_hqd_ctx_save_size;	/* ordinal177 */
- 	uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
--	uint32_t cp_hqd_error;  /* ordinal179 */
-+	uint32_t cp_hqd_error;	/* ordinal179 */
- 	uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
- 	uint32_t cp_hqd_eop_dones;  /* ordinal181 */
- 	uint32_t reserved46;  /* ordinal182 */
-@@ -4607,7 +4607,7 @@ struct vi_mqd {
- 	uint32_t reserved56;  /* ordinal225 */
- 	uint32_t reserved57;  /* ordinal226 */
- 	uint32_t reserved58;  /* ordinal227 */
--	uint32_t set_resources_header;  /* ordinal228 */
-+	uint32_t set_resources_header;	/* ordinal228 */
- 	uint32_t set_resources_dw1;  /* ordinal229 */
- 	uint32_t set_resources_dw2;  /* ordinal230 */
- 	uint32_t set_resources_dw3;  /* ordinal231 */
-@@ -5271,124 +5271,124 @@ static int gfx_v8_0_late_init(void *handle)
- }
- 
- static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
--                                                       bool enable)
-+						       bool enable)
- {
--         uint32_t data, temp;
-+	 uint32_t data, temp;
-  
--         if (enable) {
--                 /* Enable static MGPG */
--                 temp = data = RREG32(mmRLC_PG_CNTL);
--                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+	 if (enable) {
-+		 /* Enable static MGPG */
-+		 temp = data = RREG32(mmRLC_PG_CNTL);
-+		 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-  
--                 if (temp != data)
--                         WREG32(mmRLC_PG_CNTL, data);
--         } else {
--                 temp = data = RREG32(mmRLC_PG_CNTL);
--                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+		 if (temp != data)
-+			 WREG32(mmRLC_PG_CNTL, data);
-+	 } else {
-+		 temp = data = RREG32(mmRLC_PG_CNTL);
-+		 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-  
--                 if (temp != data)
--                         WREG32(mmRLC_PG_CNTL, data);
--         }
-+		 if (temp != data)
-+			 WREG32(mmRLC_PG_CNTL, data);
-+	 }
- }
- 
- static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
--                                                        bool enable)
-+							bool enable)
- {
--         uint32_t data, temp;
-+	 uint32_t data, temp;
-  
--         if (enable) {
--                 /* Enable dynamic MGPG */
--                 temp = data = RREG32(mmRLC_PG_CNTL);
--                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+	 if (enable) {
-+		 /* Enable dynamic MGPG */
-+		 temp = data = RREG32(mmRLC_PG_CNTL);
-+		 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-  
--                 if (temp != data)
--                         WREG32(mmRLC_PG_CNTL, data);
--         } else {
--                 temp = data = RREG32(mmRLC_PG_CNTL);
--                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+		 if (temp != data)
-+			 WREG32(mmRLC_PG_CNTL, data);
-+	 } else {
-+		 temp = data = RREG32(mmRLC_PG_CNTL);
-+		 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-  
--                 if (temp != data)
--                         WREG32(mmRLC_PG_CNTL, data);
--         }
-+		 if (temp != data)
-+			 WREG32(mmRLC_PG_CNTL, data);
-+	 }
- }
- 
- static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
--                                         bool enable)
-+					  bool enable)
- {
--       u32 data, orig;
-+	u32 data, orig;
-  
--        orig = data = RREG32(mmRLC_PG_CNTL);
-+	orig = data = RREG32(mmRLC_PG_CNTL);
-  
--        if (enable)
--                data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
--        else
--                data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
-+	if (enable)
-+		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
-+	else
-+		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
-  
--        if (orig != data)
--                WREG32(mmRLC_PG_CNTL, data);
-+	if (orig != data)
-+		WREG32(mmRLC_PG_CNTL, data);
- }
- 
- static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
--                                               bool enable)
-+						bool enable)
- {
--       u32 data, orig;
-+	u32 data, orig;
-  
--        orig = data = RREG32(mmRLC_PG_CNTL);
-+	orig = data = RREG32(mmRLC_PG_CNTL);
-  
--        if (enable)
--                data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
--        else
--                data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-+	if (enable)
-+		data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-+	else
-+		data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-  
--        if (orig != data)
--                WREG32(mmRLC_PG_CNTL, data);
-+	if (orig != data)
-+		WREG32(mmRLC_PG_CNTL, data);
-  
--        /* Read any GFX register to wake up GFX. */
--        if (!enable)
--                data = RREG32(mmDB_RENDER_CONTROL);
-+	/* Read any GFX register to wake up GFX. */
-+	if (!enable)
-+		data = RREG32(mmDB_RENDER_CONTROL);
- }
- 
- static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
--                                         bool enable)
-+					  bool enable)
- {
-        if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) && enable) {
--                cz_enable_gfx_cg_power_gating(adev, true);
--                if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PIPELINE)
--                        cz_enable_gfx_pipeline_power_gating(adev, true);
--        } else {
--                cz_enable_gfx_cg_power_gating(adev, false);
--                cz_enable_gfx_pipeline_power_gating(adev, false);
--        }
-+		cz_enable_gfx_cg_power_gating(adev, true);
-+		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PIPELINE)
-+			cz_enable_gfx_pipeline_power_gating(adev, true);
-+	} else {
-+		cz_enable_gfx_cg_power_gating(adev, false);
-+		cz_enable_gfx_pipeline_power_gating(adev, false);
-+	}
- }
- 
- static int gfx_v8_0_set_powergating_state(void *handle,
- 					  enum amd_powergating_state state)
- {
--        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--        bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
-  
--        if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG))
--                return 0;
-+	if (!(adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG))
-+		return 0;
-  
--        switch (adev->asic_type) {
--        case CHIP_CARRIZO:
--        case CHIP_STONEY:
--                if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)
--                        cz_update_gfx_cg_power_gating(adev, enable);
-+	switch (adev->asic_type) {
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)
-+			cz_update_gfx_cg_power_gating(adev, enable);
-  
--                if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) && enable)
--                        gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
--                else
--                        gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
-+		if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) && enable)
-+			gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
-+		else
-+			gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
-  
--                if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG) && enable)
--                       gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
--                else
--                       gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
--                break;
--        default:
--                break;
--        }
-+		if ((adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG) && enable)
-+		       gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
-+		else
-+		       gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
-+		break;
-+	default:
-+		break;
-+	}
- 
- 	return 0;
- }
-@@ -5435,11 +5435,11 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
- }
- 
- #define MSG_ENTER_RLC_SAFE_MODE     1
--#define MSG_EXIT_RLC_SAFE_MODE      0
-+#define MSG_EXIT_RLC_SAFE_MODE	    0
- 
--#define RLC_GPR_REG2__REQ_MASK           0x00000001
--#define RLC_GPR_REG2__MESSAGE__SHIFT     0x00000001
--#define RLC_GPR_REG2__MESSAGE_MASK       0x0000001e
-+#define RLC_GPR_REG2__REQ_MASK		 0x00000001
-+#define RLC_GPR_REG2__MESSAGE__SHIFT	 0x00000001
-+#define RLC_GPR_REG2__MESSAGE_MASK	 0x0000001e
- 
- static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
- {
-@@ -5795,13 +5795,13 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
- {
- 	if (enable) {
- 		/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
--		 * ===  MGCG + MGLS + TS(CG/LS) ===
-+		 * ===	MGCG + MGLS + TS(CG/LS) ===
- 		 */
- 		gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
- 		gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
- 	} else {
- 		/* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
--		 * ===  CGCG + CGLS ===
-+		 * ===	CGCG + CGLS ===
- 		 */
- 		gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
- 		gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
-@@ -5909,7 +5909,7 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
- }
- 
- static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib, bool ctx_switch)
-+				      struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	u32 header, control = 0;
- 	u32 next_rptr = ring->wptr + 5;
-@@ -5952,7 +5952,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- }
- 
- static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
--				  struct amdgpu_ib *ib, bool ctx_switch)
-+					  struct amdgpu_ib *ib, bool ctx_switch)
- {
- 	u32 header, control = 0;
- 	u32 next_rptr = ring->wptr + 5;
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index f462549..0b88711 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -688,7 +688,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 	memset(&ib, 0, sizeof(ib));
--        r = amdgpu_ib_get(adev, NULL, 256, &ib);
-+	r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err0;
-@@ -705,7 +705,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-@@ -1366,14 +1366,14 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
- 
- static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
- {
--        unsigned i;
-+	unsigned i;
- 
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
--               for (i = 0; i < adev->sdma.num_instances; i++)
--                       adev->vm_manager.vm_pte_rings[i] =
--                               &adev->sdma.instance[i].ring;
-+	        for (i = 0; i < adev->sdma.num_instances; i++)
-+		        adev->vm_manager.vm_pte_rings[i] =
-+			        &adev->sdma.instance[i].ring;
-  
--                adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
-+		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index 9c30f9a..5efac1e 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -915,7 +915,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	tmp = 0xCAFEDEAD;
- 	adev->wb.wb[index] = cpu_to_le32(tmp);
- 	memset(&ib, 0, sizeof(ib));
--        r = amdgpu_ib_get(adev, NULL, 256, &ib);
-+	r = amdgpu_ib_get(adev, NULL, 256, &ib);
- 	if (r) {
- 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
- 		goto err0;
-@@ -932,7 +932,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
- 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- 	ib.length_dw = 8;
- 
--        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
-+	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
- 	if (r)
- 		goto err1;
- 
-@@ -1681,14 +1681,14 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
- 
- static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
- {
--        unsigned i;
-+	unsigned i;
- 
- 	if (adev->vm_manager.vm_pte_funcs == NULL) {
- 		adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
--                for (i = 0; i < adev->sdma.num_instances; i++)
--                        adev->vm_manager.vm_pte_rings[i] =
--                                &adev->sdma.instance[i].ring;
-+		for (i = 0; i < adev->sdma.num_instances; i++)
-+			adev->vm_manager.vm_pte_rings[i] =
-+				&adev->sdma.instance[i].ring;
- 
--                adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
-+		adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
- 	}
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-index 9b27c69..0887ea9 100644
---- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
-@@ -415,10 +415,14 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
- 	mdelay(1);
- 
- 	/* put LMI, VCPU, RBC etc... into reset */
--	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
--		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
--		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
--		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
-+	WREG32(mmUVD_SOFT_RESET,
-+		UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
-+		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
-+		UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
-+		UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
-+		UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
-+		UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
-+		UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
- 		UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
- 	mdelay(5);
- 
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index f4027d6..02ba429 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -135,8 +135,8 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
- }
- 
- /* smu_8_0_d.h */
--#define mmMP0PUB_IND_INDEX                                                      0x180
--#define mmMP0PUB_IND_DATA                                                       0x181
-+#define mmMP0PUB_IND_INDEX							0x180
-+#define mmMP0PUB_IND_DATA							0x181
- 
- static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
- {
-@@ -1423,9 +1423,9 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
- 	return 0;
- }
- 
--#define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
--#define ATI_REV_ID_FUSE_MACRO__SHIFT        9
--#define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
-+#define ATI_REV_ID_FUSE_MACRO__ADDRESS	    0xC0014044
-+#define ATI_REV_ID_FUSE_MACRO__SHIFT	    9
-+#define ATI_REV_ID_FUSE_MACRO__MASK	    0x00001E00
- 
- static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
- {
-@@ -1537,13 +1537,13 @@ static int vi_common_early_init(void *handle)
- 			AMD_CG_SUPPORT_HDP_LS |
- 			AMD_CG_SUPPORT_SDMA_MGCG |
- 			AMD_CG_SUPPORT_SDMA_LS;
--               /* rev0 hardware doesn't support PG */
--               if (adev->rev_id != 0x00)
--                       adev->pg_flags |= AMDGPU_PG_SUPPORT_GFX_PG |
--                                         AMDGPU_PG_SUPPORT_GFX_SMG |
--                                         AMDGPU_PG_SUPPORT_GFX_DMG |
--                                         AMDGPU_PG_SUPPORT_CP |
--                                         AMDGPU_PG_SUPPORT_GFX_PIPELINE;
-+	        /* rev0 hardware doesn't support PG */
-+	        if (adev->rev_id != 0x00)
-+		        adev->pg_flags |= AMDGPU_PG_SUPPORT_GFX_PG |
-+				 AMDGPU_PG_SUPPORT_GFX_SMG |
-+				 AMDGPU_PG_SUPPORT_GFX_DMG |
-+				 AMDGPU_PG_SUPPORT_CP |
-+				 AMDGPU_PG_SUPPORT_GFX_PIPELINE;
- 
- 		adev->external_rev_id = adev->rev_id + 0x1;
- 		break;
-diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-index eed16c4..7bbf6fc 100644
---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
-@@ -212,8 +212,10 @@ static struct dc_sink *dm_dp_mst_add_mst_sink(
- 	/* dc_sink_retain(&core_sink->public); */
- 
- 	return dc_sink;
-+
- fail:
- 	dc_link_remove_remote_sink(dc_link, dc_sink);
-+
- fail_add_sink:
- 	return NULL;
- }
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-index e26a099..863a1bd 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
-@@ -399,7 +399,7 @@ static int8_t acquire_first_free_underlay(
-  ******************************************************************************/
- 
- struct dc *dc_create(const struct dc_init_data *init_params)
-- {
-+{
- 	struct dc_context ctx = {
- 		.driver_context = init_params->driver,
- 		.cgs_device = init_params->cgs_device
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-index 3f62986..84ddabc 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
-@@ -347,14 +347,13 @@ static void calculate_scaling_ratios(
- 
- 	if (surface->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE)
- 		pipe_ctx->scl_data.ratios.horz.value *= 2;
--	else if (surface->stereo_format
--					== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
-+	else if (surface->stereo_format	== PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
- 		pipe_ctx->scl_data.ratios.vert.value *= 2;
- 
--	pipe_ctx->scl_data.ratios.vert.value = div64_s64(pipe_ctx->scl_data.ratios.vert.value * in_h,
--			out_h);
--	pipe_ctx->scl_data.ratios.horz.value = div64_s64(pipe_ctx->scl_data.ratios.horz.value * in_w,
--			out_w);
-+	pipe_ctx->scl_data.ratios.vert.value = div64_s64(
-+		pipe_ctx->scl_data.ratios.vert.value * in_h, out_h);
-+	pipe_ctx->scl_data.ratios.horz.value = div64_s64(
-+		pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
- 
- 	pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
- 	pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-index b696401..9a97574 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
-@@ -148,7 +148,8 @@ void dc_stream_release(struct dc_stream *public)
- 	}
- }
- 
--struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink)
-+struct dc_stream *dc_create_stream_for_sink(
-+		const struct dc_sink *dc_sink)
- {
- 	struct core_sink *sink = DC_SINK_TO_CORE(dc_sink);
- 	struct stream *stream;
-diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-index ef6ce30..91041e8 100644
---- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
-@@ -299,7 +299,7 @@ struct resource_context {
- 	bool is_audio_acquired[MAX_PIPES];
- 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
- 	uint8_t dp_clock_source_ref_count;
-- };
-+};
- 
- struct target_flags {
- 	bool unchanged;
-diff --git a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-index 01cfeb0..002dbad 100644
---- a/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-+++ b/drivers/gpu/drm/amd/dal/modules/freesync/freesync.c
-@@ -30,19 +30,19 @@
- static const MOD_FREESYNC_MAX_CONCURRENT_SINKS = 32;
- 
- struct sink_caps {
--    const struct dc_sink *sink;
--    struct mod_freesync_caps caps;
-+	const struct dc_sink *sink;
-+	struct mod_freesync_caps caps;
- };
- 
- struct core_freesync {
--    struct mod_freesync public;
--    struct dc *dc;
--    struct sink_caps *caps;
--    int num_sinks;
-+	struct mod_freesync public;
-+	struct dc *dc;
-+	struct sink_caps *caps;
-+	int num_sinks;
- };
- 
- #define MOD_FREESYNC_TO_CORE(mod_freesync)\
--    container_of(mod_freesync, struct core_freesync, public)
-+		container_of(mod_freesync, struct core_freesync, public)
- 
- static bool check_dc_support(const struct dc *dc)
- {
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-index 1f14c47..019356a 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
-@@ -1644,7 +1644,7 @@ static void cz_hw_print_display_cfg(
- 			cc6_settings->cpu_pstate_separation_time);
- }
- 
-- static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
-+static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 	uint32_t data = 0;
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/1141-Fix-a-deadlock-affecting-ww_mutexes.patch b/common/recipes-kernel/linux/files/1141-Fix-a-deadlock-affecting-ww_mutexes.patch
deleted file mode 100644
index 25312ef1..00000000
--- a/common/recipes-kernel/linux/files/1141-Fix-a-deadlock-affecting-ww_mutexes.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From 5f3c992c00f95a483cf01d55b8ff0fa1fe6df216 Mon Sep 17 00:00:00 2001
-From: Sanjay R Mehta <sanju.mehta@amd.com>
-Date: Wed, 23 Nov 2016 14:54:46 +0530
-Subject: [PATCH 03/10] Fix a deadlock affecting ww_mutexes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-his patch fixes a race condition involving 4 threads and 2 ww_mutexes
-as indicated in the following example. Acquire context stamps are ordered
-like the thread numbers, i.e. thread #1 should back off when it encounters
-a mutex locked by thread #0 etc.
-
-Thread #0    Thread #1    Thread #2    Thread #3
----------    ---------    ---------    ---------
-                                        lock(ww)
-              lock(ww')
-                           lock(ww)
-              lock(ww)
-                                        unlock(ww) part 1
-lock(ww)
-                                        unlock(ww) part 2
-                           back off
-lock(ww')
-
-Here, unlock(ww) part 1 is the part that sets lock->base.count to 1
-(without being protected by lock->base.wait_lock), meaning that thread #0
-can acquire ww in the fast path. Since lock->base.count == 0, thread #0
-won't wake up any of the waiters.
-
-Then, unlock(ww) part 2 wakes up _only_the_first_ waiter of ww. This is
-thread #2, since waiters are added at the tail. Thread #2 wakes up and
-backs off since it sees ww owned by a context with a lower stamp.
-
-Meanwhile, thread #1 is never woken up, and so it won't back off its lock
-on ww'. So thread #0 gets stuck waiting for ww' to be released.
-
-This patch fixes the deadlock by waking up all waiters in the slow path
-of ww_mutex_unlock.
-
-We have an internal test case for amdgpu which continuously submits
-command streams from tens of threads, where all command stream reference
-hundreds of GPU buffer objects with a lot of overlap in the buffer lists
-between command streams. This test reliably caused a deadlock, and while I
-haven't completely confirmed that it is exactly the scenario outlined
-above, this patch does fix the test case.
-
-Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
-Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
----
- kernel/locking/mutex.c | 26 ++++++++++++++++++++++----
- 1 file changed, 22 insertions(+), 4 deletions(-)
-
-diff --git a/kernel/locking/mutex.c b/kernel/locking/mutex.c
-index 0551c21..39fa58a 100644
---- a/kernel/locking/mutex.c
-+++ b/kernel/locking/mutex.c
-@@ -409,6 +409,10 @@ static bool mutex_optimistic_spin(struct mutex *lock,
- __visible __used noinline
- void __sched __mutex_unlock_slowpath(atomic_t *lock_count);
- 
-+static __used noinline
-+void __sched __mutex_unlock_slowpath_wakeall(atomic_t *lock_count);
-+
-+
- /**
-  * mutex_unlock - release the mutex
-  * @lock: the mutex to be released
-@@ -473,7 +477,7 @@ void __sched ww_mutex_unlock(struct ww_mutex *lock)
- 	 */
- 	mutex_clear_owner(&lock->base);
- #endif
--	__mutex_fastpath_unlock(&lock->base.count, __mutex_unlock_slowpath);
-+	__mutex_fastpath_unlock(&lock->base.count, __mutex_unlock_slowpath_wakeall);
- }
- EXPORT_SYMBOL(ww_mutex_unlock);
- 
-@@ -713,7 +717,7 @@ EXPORT_SYMBOL_GPL(__ww_mutex_lock_interruptible);
-  * Release the lock, slowpath:
-  */
- static inline void
--__mutex_unlock_common_slowpath(struct mutex *lock, int nested)
-+__mutex_unlock_common_slowpath(struct mutex *lock, int nested, int wake_all)
- {
- 	unsigned long flags;
- 
-@@ -736,7 +740,13 @@ __mutex_unlock_common_slowpath(struct mutex *lock, int nested)
- 	mutex_release(&lock->dep_map, nested, _RET_IP_);
- 	debug_mutex_unlock(lock);
- 
--	if (!list_empty(&lock->wait_list)) {
-+	if (wake_all) {
-+		struct mutex_waiter *waiter;
-+		list_for_each_entry(waiter, &lock->wait_list, list) {
-+			debug_mutex_wake_waiter(lock, waiter);
-+			wake_up_process(waiter->task);
-+		}
-+	} else if (!list_empty(&lock->wait_list)) {
- 		/* get the first entry from the wait-list: */
- 		struct mutex_waiter *waiter =
- 				list_entry(lock->wait_list.next,
-@@ -758,7 +768,15 @@ __mutex_unlock_slowpath(atomic_t *lock_count)
- {
- 	struct mutex *lock = container_of(lock_count, struct mutex, count);
- 
--	__mutex_unlock_common_slowpath(lock, 1);
-+	__mutex_unlock_common_slowpath(lock, 1, 0);
-+}
-+
-+static void
-+__mutex_unlock_slowpath_wakeall(atomic_t *lock_count)
-+{
-+	struct mutex *lock = container_of(lock_count, struct mutex, count);
-+
-+	__mutex_unlock_common_slowpath(lock, 1, 1);
- }
- 
- #ifndef CONFIG_DEBUG_LOCK_ALLOC
--- 
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/CVE-2016-5195.patch b/common/recipes-kernel/linux/files/CVE-2016-5195.patch
deleted file mode 100644
index 6b9fa694..00000000
--- a/common/recipes-kernel/linux/files/CVE-2016-5195.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From 1294d355881cc5c3421d24fee512f16974addb6c Mon Sep 17 00:00:00 2001
-From: Linus Torvalds <torvalds@linux-foundation.org>
-Date: Thu, 13 Oct 2016 13:07:36 -0700
-Subject: mm: remove gup_flags FOLL_WRITE games from __get_user_pages()
-
-commit 19be0eaffa3ac7d8eb6784ad9bdbc7d67ed8e619 upstream.
-
-This is an ancient bug that was actually attempted to be fixed once
-(badly) by me eleven years ago in commit 4ceb5db9757a ("Fix
-get_user_pages() race for write access") but that was then undone due to
-problems on s390 by commit f33ea7f404e5 ("fix get_user_pages bug").
-
-In the meantime, the s390 situation has long been fixed, and we can now
-fix it by checking the pte_dirty() bit properly (and do it better).  The
-s390 dirty bit was implemented in abf09bed3cce ("s390/mm: implement
-software dirty bits") which made it into v3.9.  Earlier kernels will
-have to look at the page state itself.
-
-Also, the VM has become more scalable, and what used a purely
-theoretical race back then has become easier to trigger.
-
-To fix it, we introduce a new internal FOLL_COW flag to mark the "yes,
-we already did a COW" rather than play racy games with FOLL_WRITE that
-is very fundamental, and then use the pte dirty flag to validate that
-the FOLL_COW flag is still valid.
-
-Reported-and-tested-by: Phil "not Paul" Oester <kernel@linuxace.com>
-Acked-by: Hugh Dickins <hughd@google.com>
-Reviewed-by: Michal Hocko <mhocko@suse.com>
-Cc: Andy Lutomirski <luto@kernel.org>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Oleg Nesterov <oleg@redhat.com>
-Cc: Willy Tarreau <w@1wt.eu>
-Cc: Nick Piggin <npiggin@gmail.com>
-Cc: Greg Thelen <gthelen@google.com>
-Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
-diff --git a/include/linux/mm.h b/include/linux/mm.h
-index cfebb74..f0ffa01 100644
---- a/include/linux/mm.h
-+++ b/include/linux/mm.h
-@@ -2112,6 +2112,7 @@ static inline struct page *follow_page(struct vm_area_struct *vma,
- #define FOLL_MIGRATION	0x400	/* wait for page to replace migration entry */
- #define FOLL_TRIED	0x800	/* a retry, previous pass started an IO */
- #define FOLL_MLOCK	0x1000	/* lock present pages */
-+#define FOLL_COW	0x4000	/* internal GUP flag */
- 
- typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr,
- 			void *data);
-diff --git a/mm/gup.c b/mm/gup.c
-index deafa2c..4b0b7e7 100644
---- a/mm/gup.c
-+++ b/mm/gup.c
-@@ -58,6 +58,16 @@ static int follow_pfn_pte(struct vm_area_struct *vma, unsigned long address,
- 	return -EEXIST;
- }
- 
-+/*
-+ * FOLL_FORCE can write to even unwritable pte's, but only
-+ * after we've gone through a COW cycle and they are dirty.
-+ */
-+static inline bool can_follow_write_pte(pte_t pte, unsigned int flags)
-+{
-+	return pte_write(pte) ||
-+		((flags & FOLL_FORCE) && (flags & FOLL_COW) && pte_dirty(pte));
-+}
-+
- static struct page *follow_page_pte(struct vm_area_struct *vma,
- 		unsigned long address, pmd_t *pmd, unsigned int flags)
- {
-@@ -92,7 +102,7 @@ retry:
- 	}
- 	if ((flags & FOLL_NUMA) && pte_protnone(pte))
- 		goto no_page;
--	if ((flags & FOLL_WRITE) && !pte_write(pte)) {
-+	if ((flags & FOLL_WRITE) && !can_follow_write_pte(pte, flags)) {
- 		pte_unmap_unlock(ptep, ptl);
- 		return NULL;
- 	}
-@@ -352,7 +362,7 @@ static int faultin_page(struct task_struct *tsk, struct vm_area_struct *vma,
- 	 * reCOWed by userspace write).
- 	 */
- 	if ((ret & VM_FAULT_WRITE) && !(vma->vm_flags & VM_WRITE))
--		*flags &= ~FOLL_WRITE;
-+	        *flags |= FOLL_COW;
- 	return 0;
- }
- 
--- 
-cgit v0.10.2
diff --git a/common/recipes-kernel/linux/files/console.cfg b/common/recipes-kernel/linux/files/console.cfg
deleted file mode 100644
index 9e30450e..00000000
--- a/common/recipes-kernel/linux/files/console.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_EFI=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FB_VESA=y
-CONFIG_FB_SIMPLE=y
diff --git a/common/recipes-kernel/linux/files/disable-bluetooth.cfg b/common/recipes-kernel/linux/files/disable-bluetooth.cfg
deleted file mode 100644
index ce6ddb43..00000000
--- a/common/recipes-kernel/linux/files/disable-bluetooth.cfg
+++ /dev/null
@@ -1 +0,0 @@
-# CONFIG_BT is not set
diff --git a/common/recipes-kernel/linux/files/disable-intel-graphics.cfg b/common/recipes-kernel/linux/files/disable-intel-graphics.cfg
deleted file mode 100644
index 06a5238d..00000000
--- a/common/recipes-kernel/linux/files/disable-intel-graphics.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-# CONFIG_DRM_I915 is not set
-# CONFIG_DRM_I915_KMS is not set
diff --git a/common/recipes-kernel/linux/files/disable-kgdb.cfg b/common/recipes-kernel/linux/files/disable-kgdb.cfg
deleted file mode 100644
index b8a2218b..00000000
--- a/common/recipes-kernel/linux/files/disable-kgdb.cfg
+++ /dev/null
@@ -1 +0,0 @@
-# CONFIG_KGDB is not set
diff --git a/common/recipes-kernel/linux/files/drm.cfg b/common/recipes-kernel/linux/files/drm.cfg
deleted file mode 100644
index b6a52201..00000000
--- a/common/recipes-kernel/linux/files/drm.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_DRM=m
-CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-CONFIG_DRM_KMS_HELPER=m
-CONFIG_DRM_KMS_FB_HELPER=y
-CONFIG_DRM_TTM=m
-# CONFIG_DRM_CIRRUS_QEMU is not set
diff --git a/common/recipes-kernel/linux/files/efi-partition.cfg b/common/recipes-kernel/linux/files/efi-partition.cfg
deleted file mode 100644
index a7a89935..00000000
--- a/common/recipes-kernel/linux/files/efi-partition.cfg
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_EFI_PARTITION=y
diff --git a/common/recipes-kernel/linux/files/enable-bluetooth.cfg b/common/recipes-kernel/linux/files/enable-bluetooth.cfg
deleted file mode 100644
index 581830f0..00000000
--- a/common/recipes-kernel/linux/files/enable-bluetooth.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_BNEP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_ATH3K=m
diff --git a/common/recipes-kernel/linux/files/enable-imc.cfg b/common/recipes-kernel/linux/files/enable-imc.cfg
deleted file mode 100644
index 205b2388..00000000
--- a/common/recipes-kernel/linux/files/enable-imc.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_STAGING=y
-CONFIG_AMD_IMC=y
diff --git a/common/recipes-kernel/linux/files/enable-kgdb.cfg b/common/recipes-kernel/linux/files/enable-kgdb.cfg
deleted file mode 100644
index 55f296b2..00000000
--- a/common/recipes-kernel/linux/files/enable-kgdb.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_KGDB=y
-CONFIG_KGDB_LOW_LEVEL_TRAP=y
-CONFIG_KGDB_KDB=y
diff --git a/common/recipes-kernel/linux/files/hid.cfg b/common/recipes-kernel/linux/files/hid.cfg
deleted file mode 100644
index cbab0fa7..00000000
--- a/common/recipes-kernel/linux/files/hid.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_HID_A4TECH=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MULTITOUCH=m
diff --git a/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc b/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc
deleted file mode 100644
index 5bcd947c..00000000
--- a/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc
+++ /dev/null
@@ -1,1116 +0,0 @@
-patch 0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch
-patch 0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch
-patch 0001-drm-Remove-unused-fbdev_list-members.patch
-patch 0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch
-patch 0003-drm-amdgpu-use-src-in-Makefile-v2.patch
-patch 0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch
-patch 0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch
-patch 0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch
-patch 0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch
-patch 0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch
-patch 0009-drm-amdgpu-add-err-check-for-pin-userptr.patch
-patch 0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch
-patch 0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch
-patch 0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch
-patch 0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch
-patch 0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
-patch 0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch
-patch 0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch
-patch 0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch
-patch 0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch
-patch 0019-drm-Pass-name-to-drm_encoder_init.patch
-patch 0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch
-patch 0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch
-patch 0022-drm-amdgpu-update-rev-id-register-for-VI.patch
-patch 0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch
-patch 0024-drm-amdgpu-add-entity-only-when-first-job-come.patch
-patch 0025-drm-amdgpu-handle-error-case-for-ctx.patch
-patch 0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch
-patch 0027-drm-amdgpu-change-default-sched-jobs-to-32.patch
-patch 0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch
-patch 0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch
-patch 0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch
-patch 0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch
-patch 0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch
-patch 0033-drm-amdgpu-fix-dp-link-rate-selection-v2.patch
-patch 0034-drm-amdgpu-share-struct-amdgpu_pm_state_type-with-po.patch
-patch 0035-drm-amdgpu-mv-some-definition-from-amdgpu_acpi.c-to-.patch
-patch 0036-drm-amdgpu-mv-amdgpu_acpi.h-to-amd-include-amd_acpi..patch
-patch 0037-drm-amdgpu-implement-new-cgs-interface-for-acpi-func.patch
-patch 0038-drm-amdgpu-implement-cgs-interface-to-query-system-i.patch
-patch 0039-drm-amdgpu-add-new-cgs-interface-to-get-display-info.patch
-patch 0040-drm-amd-powerplay-add-basic-powerplay-framework.patch
-patch 0041-drm-amdgpu-disable-legacy-path-of-firmware-check-if-.patch
-patch 0042-drm-amdgpu-export-amd_powerplay_func-to-amdgpu-and-o.patch
-patch 0043-drm-amd-powerplay-add-SMU-manager-sub-component.patch
-patch 0044-drm-amd-powerplay-add-hardware-manager-sub-component.patch
-patch 0045-drm-amd-powerplay-add-Carrizo-smu-support.patch
-patch 0046-drm-amd-powerplay-add-Carrizo-dpm-support.patch
-patch 0047-drm-amd-powerplay-add-CG-and-PG-support-for-carrizo.patch
-patch 0048-drm-amd-powerplay-add-event-manager-sub-component.patch
-patch 0049-drm-amd-powerplay-implement-functions-of-amd_powerpl.patch
-patch 0050-drm-amd-powerplay-Add-ixSWRST_COMMAND_1-in-bif_5_0_d.patch
-patch 0051-drm-amd-powerplay-Move-smu7-.h-from-amdgpu-to-powerp.patch
-patch 0052-drm-amd-powerplay-add-header-file-for-tonga-smu-and-.patch
-patch 0053-drm-amd-powerplay-Add-Tonga-SMU-support.patch
-patch 0054-drm-amd-powerplay-add-Tonga-dpm-support-v3.patch
-patch 0055-drm-amd-powerplay-add-update-headers-for-Fiji-SMU-an.patch
-patch 0056-drm-amd-powerplay-update-atomctrl-for-fiji.patch
-patch 0057-drm-amd-powerplay-add-Fiji-SMU-support.patch
-patch 0058-drm-amd-powerplay-add-Fiji-DPM-support.patch
-patch 0059-drm-amdgpu-add-amdgpu.powerplay-module-option.patch
-patch 0060-drm-amd-amdgpu-enable-powerplay-and-smc-firmware-loa.patch
-patch 0061-drm-amdgpu-powerplay-add-function-point-in-hwmgr_fun.patch
-patch 0062-drm-amdgpu-poweprlay-export-program-display-gap-func.patch
-patch 0063-drm-amdgpu-powerplay-implement-pem_task-for-display_.patch
-patch 0064-drm-amdgpu-powerplay-program-display-gap-for-tonga.patch
-patch 0065-drm-amdgpu-enable-powerplay-module-by-default-for-to.patch
-patch 0066-drm-amdgpu-enable-powerplay-module-by-default-for-fi.patch
-patch 0067-drm-amdgpu-powerplay-add-some-definition-for-other-i.patch
-patch 0068-drm-amd-powerplay-add-new-function-point-in-hwmgr_fu.patch
-patch 0069-drm-amd-powerplay-Add-CG-and-PG-support-for-tonga.patch
-patch 0070-drm-amdgpu-powerplay-add-new-function-point-in-hwmgr.patch
-patch 0071-drm-amdgpu-powerplay-mv-ppinterrupt.h-to-inc-folder-.patch
-patch 0072-drm-amdgpu-powerplay-add-thermal-control-interface-i.patch
-patch 0073-drm-amdgpu-powerplay-enable-thermal-interrupt-task-i.patch
-patch 0074-drm-amdgpu-powerplay-implement-thermal-control-for-t.patch
-patch 0075-drm-amdgpu-powerplay-implement-fan-control-interface.patch
-patch 0076-drm-amdgpu-export-fan-control-functions-to-amdgpu.patch
-patch 0077-drm-amdgpu-enable-sysfs-interface-for-powerplay.patch
-patch 0078-drm-amdgpu-support-per-device-powerplay-enablement-v.patch
-patch 0079-drm-amd-powerplay-add-and-export-hwmgr-interface-to-.patch
-patch 0080-drm-amd-powerplay-implement-new-funcs-to-check-curre.patch
-patch 0081-drm-amd-powerplay-refine-the-logic-of-whether-need-t.patch
-patch 0082-drm-amd-powerplay-tonga-enable-pcie-and-mclk-forcing.patch
-patch 0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch
-patch 0084-drm-amdgpu-extract-pcie-helpers-to-common-header.patch
-patch 0085-drm-amdgpu-store-pcie-gen-mask-and-link-width.patch
-patch 0086-drm-amdgpu-cgs-add-sys-info-query-for-pcie-gen-and-l.patch
-patch 0087-drm-amdgpu-powerplay-tonga-query-supported-pcie-info.patch
-patch 0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch
-patch 0089-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch
-patch 0090-drm-amd-powerplay-tonga-Add-UVD-DPM-init.patch
-patch 0091-drm-amd-amdgpu-add-gfx-clock-gating-support-for-Fiji.patch
-patch 0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch
-patch 0093-drm-amdgpu-add-sdma-clock-gating-support-for-Fiji.patch
-patch 0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch
-patch 0095-drm-amd-powerplay-enable-clock-gating-for-Fiji.patch
-patch 0096-drm-amd-powerplay-add-atomctrl-function-to-calculate.patch
-patch 0097-drm-amd-powerplay-implement-smc-state-upload-for-CZ.patch
-patch 0098-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch
-patch 0099-drm-amd-powerplay-fix-warning-of-cast-to-pointer-fro.patch
-patch 0100-amdgpu-powerplay-Add-Stoney-to-list-of-early-init-ca.patch
-patch 0101-drm-amd-powerplay-add-new-function-point-in-hwmgr.patch
-patch 0102-drm-amd-powerplay-add-smc-msg-for-NB-P-State-switch.patch
-patch 0103-drm-amd-powerplay-export-interface-to-DAL-to-init-ch.patch
-patch 0104-drm-amd-powerplay-enable-set_cpu_power_state-task.-v.patch
-patch 0105-drm-amd-powerplay-enable-disable-NB-pstate-feature-f.patch
-patch 0106-drm-amd-powerplay-Add-PPLib-debug-print-macro.patch
-patch 0107-drm-amdgpu-rename-tonga_smumgr.h-to-tonga_smum.h.patch
-patch 0108-drm-amdgpu-rename-fiji_smumgr.h-to-fiji_smum.h.patch
-patch 0109-drm-amd-powerplay-add-multimedia-power-gating-suppor.patch
-patch 0110-drm-amd-amdgpu-add-uvd6.0-clock-gating-support.-v2.patch
-patch 0111-drm-amd-amdgpu-add-vce3.0-clock-gating-support.-v2.patch
-patch 0112-drm-amd-amdgpu-enable-uvd-vce-clock-gating-for-Fiji.patch
-patch 0113-drm-amdgpu-Prepare-DKMS-build-for-powerplay-module.patch
-patch 0114-drm-amd-powerplay-add-display-configeration-changed-.patch
-patch 0115-drm-amd-powerplay-Add-thermal-protection-support-for.patch
-patch 0116-drm-amd-powerplay-Fix-a-bug-in-fan-control-setting-d.patch
-patch 0117-drm-amd-powerplay-add-functions-set-get_fan_control_.patch
-patch 0118-drm-amd-powerplay-add-functions-set-get_fan_control_.patch
-patch 0119-drm-amd-powerplay-fix-boolreturn.cocci-warnings.patch
-patch 0120-drm-amd-powerplay-fix-bug-that-dpm-funcs-in-debugfs-.patch
-patch 0121-drm-amd-powerplay-check-whether-enable-dpm-in-powerp.patch
-patch 0122-drm-amd-powerplay-move-shared-function-of-vi-to-hwmg.patch
-patch 0123-drm-amdgpu-powerplay-enable-sysfs-and-debugfs-interf.patch
-patch 0124-drm-amd-powerplay-display-gpu-load-when-print-perfor.patch
-patch 0125-amd-powerplay-Implement-get-dal-power-level.patch
-patch 0126-amd-powerplay-Fix-get-dal-power-level.patch
-patch 0127-amd-powerplay-Add-structures-required-to-report-conf.patch
-patch 0128-drm-powerplay-add-debugging-output-to-tonga_processp.patch
-patch 0129-drm-powerplay-add-debugging-output-to-processpptable.patch
-patch 0130-drm-powerplay-hwmgr-log-errors-in-tonga_hwmgr_backen.patch
-patch 0131-drm-amd-powerplay-Don-t-return-an-error-if-fan-table.patch
-patch 0132-drm-amdgpu-powerplay-Program-a-calculated-value-as-D.patch
-patch 0133-drm-amd-powerplay-add-point-check-to-avoid-NULL-poin.patch
-patch 0134-drm-amd-powerplay-check-whether-need-to-enable-therm.patch
-patch 0135-drm-amd-powerplay-show-gpu-load-when-print-gpu-perfo.patch
-patch 0136-amd-powerplay-don-t-enable-ucode-fan-control-if-vbio.patch
-patch 0137-amd-powerplay-disable-powerplay-by-default-initially.patch
-patch 0138-amd-powerplay-fix-copy-paste-typo-in-hardwaremanager.patch
-patch 0139-drm-powerplay-use-div64_s64-instead-of-do_div.patch
-patch 0140-drm-amd-powerplay-fix-a-reversed-condition.patch
-patch 0141-drm-amdgpu-cgs-cleanup-some-indenting.patch
-patch 0142-drm-amd-powerplay-precedence-bug-in-init_non_clock_f.patch
-patch 0143-drm-amdgpu-fix-NULL-in-vm_grab_id-while-S3-back.patch
-patch 0144-amdgpu-vce3-Cleanup-harvest-config-function.patch
-patch 0145-amdgpu-vce3-Simplify-idle-and-wait-for-idle-code.patch
-patch 0146-amdgpu-vce3-Simplify-vce_v3_0_soft_reset.patch
-patch 0147-amdgpu-vce3-Simplify-vce_v3_0_process_interrupt.patch
-patch 0148-amdgpu-vce3-Remove-magic-constants-from-harvest-regi.patch
-patch 0149-amdgpu-vce3-Simplify-vce_v3_0_hw_init-and-ensure-bot.patch
-patch 0150-amdgpu-dce11-Remove-division-from-dce_v11_0_vblank_w.patch
-patch 0151-amdgpu-dce11-Add-test-for-crtc-0-to-various-DCEv11-f.patch
-patch 0152-drm-amd-powerplay-fix-bug-that-NULL-checks-are-rever.patch
-patch 0153-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch
-patch 0154-drm-amd-powerplay-fix-Smatch-static-checker-warnings.patch
-patch 0155-drm-amd-powerplay-add-powerplay-valid-check-to-avoid.patch
-patch 0156-drm-amd-powerplay-Reload-and-initialize-the-smc-firm.patch
-patch 0157-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch
-patch 0158-drm-amdgpu-Show-gpu-load-when-display-gpu-performanc.patch
-patch 0159-drm-amdgpu-fix-hex-decimal-bug-when-show-gpu-load.patch
-patch 0160-drm-amd-powerplay-add-thermal-control-task-when-resu.patch
-patch 0161-drm-amd-powerplay-enable-set-boot-state-task.patch
-patch 0162-drm-amd-powerplay-enable-power-down-asic-task.-v2.patch
-patch 0163-drm-amd-powerplay-implement-power-down-asic-task-for.patch
-patch 0164-drm-amdgpu-add-warning-to-amdgpu_bo_gpu_offset-v2.patch
-patch 0165-drm-amdgpu-cgs-add-an-interface-to-access-PCI-resour.patch
-patch 0166-drm-amdgpu-add-irq-domain-support.patch
-patch 0167-drm-amdgpu-powerplay-include-asm-div64.h-for-do_div.patch
-patch 0168-drm-amd-powerplay-fix-static-checker-warning-for-ret.patch
-patch 0169-drm-amdgpu-cz-add-code-to-enable-forcing-UVD-clocks.patch
-patch 0170-drm-amdgpu-cz-add-code-to-enable-forcing-VCE-clocks.patch
-patch 0171-drm-amdgpu-cz-force-uvd-clocks-when-sclks-are-forced.patch
-patch 0172-drm-amdgpu-cz-force-vce-clocks-when-sclks-are-forced.patch
-patch 0173-drm-amdgpu-use-kobj_to_dev.patch
-patch 0174-drm-amdgpu-move-VM-page-tables-to-the-LRU-end-on-CS-.patch
-patch 0175-drm-amdgpu-validate-duplicates-first.patch
-patch 0176-drm-amdgpu-add-missing-irq.h-include.patch
-patch 0177-drm-amdgpu-Add-some-tweaks-to-gfx-8-soft-reset.patch
-patch 0178-drm-amdgpu-Allow-the-driver-to-load-if-amdgpu.powerp.patch
-patch 0179-drm-amd-amdgpu-Improve-amdgpu_dpm-macros-to-avoid-un.patch
-patch 0180-drm-amdgpu-add-a-message-to-indicate-when-powerplay-.patch
-patch 0181-drm-amdgpu-fix-next_rptr-handling-for-debugfs.patch
-patch 0182-drm-amdgpu-don-t-init-fbdev-if-we-don-t-have-any-con.patch
-patch 0183-drm-amd-powerplay-Update-SMU-firmware-loading-for-St.patch
-patch 0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch
-patch 0185-drm-amdgpu-gfx7-enable-cp-inst-reg-error-interrupts.patch
-patch 0186-drm-amdgpu-load-MEC-ucode-manually-on-iceland.patch
-patch 0187-drm-amdgpu-disable-uvd-and-vce-clockgating-on-Fiji.patch
-patch 0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch
-patch 0189-drm-amdgpu-cik-don-t-mess-with-aspm-if-gpu-is-root-b.patch
-patch 0190-drm-amdgpu-dpm-ci-switch-over-to-the-common-pcie-cap.patch
-patch 0191-drm-amdgpu-handle-uvd-pg-flags-properly.patch
-patch 0192-drm-amdgpu-handle-vce-pg-flags-properly.patch
-patch 0193-drm-amdgpu-clean-up-vce-pg-flags-for-cz-st.patch
-patch 0194-drm-amdgpu-be-consistent-with-uvd-cg-flags.patch
-patch 0195-drm-amd-powerplay-cz-disable-uvd-pg.patch
-patch 0196-drm-amd-powerplay-cz-disable-vce-pg.patch
-patch 0197-drm-amd-powerplay-tonga-disable-uvd-pg.patch
-patch 0198-drm-amd-powerplay-tonga-disable-vce-pg.patch
-patch 0199-drm-amdgpu-add-a-cgs-interface-to-fetch-cg-and-pg-fl.patch
-patch 0200-drm-amdgpu-remove-unused-cg-defines.patch
-patch 0201-drma-dmgpu-move-cg-and-pg-flags-into-shared-headers.patch
-patch 0202-drm-amdgpu-tonga-plumb-pg-flags-through-to-powerplay.patch
-patch 0203-drm-amdgpu-cz-plumb-pg-flags-through-to-powerplay.patch
-patch 0204-drm-amdgpu-gfx8-fix-priv-reg-interrupt-enable.patch
-patch 0205-drm-amdgpu-fix-locking-in-force-performance-level.patch
-patch 0206-drm-amdgpu-pm-add-some-checks-for-PX.patch
-patch 0207-amdgpu-fix-NULL-pointer-dereference-at-tonga_check_s.patch
-patch 0208-drm-amdgpu-disable-direct-VM-updates-when-vm_debug-i.patch
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-patch 1063-drm-amdgpu-add-pipeline-sync-for-compute-job.patch
-patch 1064-drm-amdgpu-fiji-set-UVD-CG-state-when-enabling-UVD-D.patch
-patch 1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch
-patch 1066-drm-amdgpu-check-if-ring-emit_vm_flush-exists-in-vm-.patch
-patch 1067-drm-powerplay-add-missing-clockgating-callback-for-t.patch
-patch 1068-drm-amd-amdgpu-Convert-ring-debugfs-entries-to-binar.patch
-patch 1069-drm-amd-amdgpu-ring-debugfs-is-read-in-increments-of.patch
-patch 1070-drm-amd-amdgpu-Enable-CG-for-UVD6-on-Carrizo.patch
-patch 1071-drm-amd-dal-change-default-to-use-SW-i2c.patch
-patch 1072-drm-amdgpu-hdp-flush-inval-should-always-do.patch
-patch 1073-drm-amdgpu-two-minor-80-char-fixes.patch
-patch 1074-drm-amdgpu-make-the-VMID-owner-always-64bit.patch
-patch 1075-drm-amdgpu-remove-owner-cleanup-v2.patch
-patch 1076-drm-amdgpu-remove-define-for-reserved-client-ID.patch
-patch 1077-drm-amd-cleanup-DAL-spaces-and-tabs-v2.patch
-patch 1078-drm-amd-cleanup-remaining-spaces-and-tabs-v2.patch
-patch 1079-drm-amdgpu-fix-compilation-errors-during-backport.patch
-patch 1080-drm-amdgpu-fix-num_rbs-exposed-to-userspace.patch
-patch 1081-drm-amd-amdgpu-make-sure-VCE-is-disabled-by-default.patch
-patch 1082-drm-amd-powerplay-make-sure-VCE-is-disabled-by-defau.patch
-patch 1083-1083-drm-amd-dal-remove-common-modes.patch.patch
-patch 1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch
-patch 1085-drm-amdgpu-gfx8-add-powergating-support-for-CZ-ST.patch
-patch 1086-drm-amdgpu-gfx8-Add-serdes-wait-for-idle-in-CGCG-en-.patch
-patch 1087-drm-amdgpu-gfx8-fix-CP-jump-table-size.patch
-patch 1088-drm-amdgpu-gfx8-Enable-GFX-PG-on-CZ.patch
-patch 1089-drm-amd-amdgpu-Add-name-field-to-amd_ip_funcs.patch
-patch 1090-drm-amd-amdgpu-Added-more-named-DRM-info-messages-fo.patch
-patch 1091-drm-amdgpu-fix-staging-4.5-merge-error-for-pipeline-.patch
-patch 1092-drm-amd-dal-Properly-handle-vblank-on-S3-suspend-and.patch
-patch 1093-drm-amd-dal-S3-Move-vblank_off-to-before-CRTCs-are-d.patch
-patch 1094-drm-amd-dal-Not-releasing-target-during-suspend.patch
-patch 1095-drm-amdgpu-add-late_fini-for-ip_funcs.patch
-patch 1096-drm-amdgpu-impl-late_fini-for-amdgpu_pp_ip.patch
-patch 1097-drm-amdgpu-modify-sdma-start-sequence.patch
-patch 1098-drm-amd-dal-Revert-to-generic-list-iteration.patch
-patch 1099-drm-amdgpu-free-sync-ioctl-declaration.patch
-patch 1100-drm-amdgpu-drm_helper_resume_force_mode-is-only-work.patch
-patch 1101-drm-amdgpu-mode-restore-for-atomic-modesetting.patch
-patch 1103-drm-amdgpu-use-PCI_D3hot-for-PX-systems-without-dGPU.patch
-patch 1104-drm-amdgpu-add-amdgpu_irq_gpu_reset_resume_helper.patch
-patch 1105-drm-amdgpu-add-dm_display_resume-to-balance-dm_suspe.patch
-patch 1106-drm-amdgpu-dce8-fix-flash-with-white-screen-on-monit.patch
-patch 1107-drm-amdgpu-fix-UVD-enabled-display-after-system-resu.patch
-patch 1108-drm-amdgpu-fix-uvd-fini-mem-leak.patch
-patch 1109-drm-amdgpu-fix-system-randomly-reboots-after-login.patch
-patch 1110-drm-amdgpu-free-handles-after-fini-the-context.patch
-patch 1111-drm-amd-dal-return-page-flip-status-to-userspace.patch
-patch 1112-drm-amd-Indentation-of-the-code.patch
-patch CVE-2016-5195.patch
-patch 0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch
-patch 1141-Fix-a-deadlock-affecting-ww_mutexes.patch
diff --git a/common/recipes-kernel/linux/files/logo.cfg b/common/recipes-kernel/linux/files/logo.cfg
deleted file mode 100644
index 9772c12e..00000000
--- a/common/recipes-kernel/linux/files/logo.cfg
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_LOGO=y
diff --git a/common/recipes-kernel/linux/files/radeon-console.cfg b/common/recipes-kernel/linux/files/radeon-console.cfg
deleted file mode 100644
index 301172ad..00000000
--- a/common/recipes-kernel/linux/files/radeon-console.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_FB_VGA16=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_FB_RADEON=y
diff --git a/common/recipes-kernel/linux/files/radeon-gpu-config.cfg b/common/recipes-kernel/linux/files/radeon-gpu-config.cfg
deleted file mode 100644
index 728e2436..00000000
--- a/common/recipes-kernel/linux/files/radeon-gpu-config.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_DRM_RADEON=m
-CONFIG_DRM_RADEON_UMS=y
diff --git a/common/recipes-kernel/linux/files/radeon-microcode.cfg b/common/recipes-kernel/linux/files/radeon-microcode.cfg
deleted file mode 100644
index fadbe9a9..00000000
--- a/common/recipes-kernel/linux/files/radeon-microcode.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-# CONFIG_MICROCODE_EARLY is not set
-# CONFIG_MICROCODE_INTEL_EARLY is not set
diff --git a/common/recipes-kernel/linux/files/sound.cfg b/common/recipes-kernel/linux/files/sound.cfg
deleted file mode 100644
index a4d0fcb1..00000000
--- a/common/recipes-kernel/linux/files/sound.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_SEQ_DUMMY=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_HRTIMER=y
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_PCSP=y
-CONFIG_SND_HDA_GENERIC=y
-CONFIG_SND_HDA_INTEL=y
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_JACK=y
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_CODEC_REALTEK=y
-CONFIG_SND_HDA_CODEC_ANALOG=y
-CONFIG_SND_HDA_CODEC_SIGMATEL=y
-CONFIG_SND_HDA_CODEC_VIA=y
-CONFIG_SND_HDA_CODEC_HDMI=y
-CONFIG_SND_HDA_CODEC_CIRRUS=y
-CONFIG_SND_HDA_CODEC_CONEXANT=y
-CONFIG_SND_HDA_CODEC_CA0110=y
-CONFIG_SND_HDA_CODEC_CA0132=y
-CONFIG_SND_HDA_CODEC_CMEDIA=y
-CONFIG_SND_HDA_CODEC_SI3054=y
-CONFIG_SND_USB_AUDIO=y
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_SOC=m
diff --git a/common/recipes-kernel/linux/files/usb-serial.cfg b/common/recipes-kernel/linux/files/usb-serial.cfg
deleted file mode 100644
index 11402439..00000000
--- a/common/recipes-kernel/linux/files/usb-serial.cfg
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_USB_SERIAL_MOS7840=y
diff --git a/common/recipes-kernel/linux/files/wifi-drivers.cfg b/common/recipes-kernel/linux/files/wifi-drivers.cfg
deleted file mode 100644
index 8b407303..00000000
--- a/common/recipes-kernel/linux/files/wifi-drivers.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_CFG80211_WEXT=y
-CONFIG_WEXT_CORE=y
-CONFIG_WEXT_PROC=y
-CONFIG_IWLWIFI=m
-CONFIG_IWLDVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
diff --git a/common/recipes-kernel/linux/linux-yocto-common_4.4.inc b/common/recipes-kernel/linux/linux-yocto-common_4.4.inc
deleted file mode 100644
index 91d5023a..00000000
--- a/common/recipes-kernel/linux/linux-yocto-common_4.4.inc
+++ /dev/null
@@ -1,30 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
-
-PR := "${INC_PR}.1"
-
-KMACHINE_amdx86 ?= "common-pc-64"
-SRCREV_meta_amdx86 ?= "e66032e2d93da24c6b9137dbbe66008c77f6d4aa"
-LINUX_VERSION_amdx86 ?= "4.4.20"
-
-SRC_URI_append_amdx86 += " \
-	file://linux-yocto-amd-patches.scc \
-	file://logo.cfg \
-	file://console.cfg \
-	file://drm.cfg \
-	file://sound.cfg \
-	file://hid.cfg \
-	file://enable-imc.cfg \
-	file://efi-partition.cfg \
-	file://usb-serial.cfg \
-	file://wifi-drivers.cfg \
-	file://disable-intel-graphics.cfg \
-	${@bb.utils.contains('DISTRO_FEATURES', 'bluetooth', 'file://enable-bluetooth.cfg', 'file://disable-bluetooth.cfg', d)} \
-	${@bb.utils.contains('DISTRO', 'mel', 'file://enable-kgdb.cfg', 'file://disable-kgdb.cfg', d)} \
-"
-
-KERNEL_FEATURES_append_amdx86 = " cfg/smp.scc cfg/sound.scc"
-
-do_validate_branches_append() {
-    # Drop a config generating spurious warnings
-    sed -i '/CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT/d' ${WORKDIR}/${KMETA}/features/i915/i915.cfg
-}
diff --git a/common/recipes-kernel/linux/linux-yocto-rt_4.4.bb b/common/recipes-kernel/linux/linux-yocto-rt_4.4.bb
deleted file mode 100644
index 5fd13f13..00000000
--- a/common/recipes-kernel/linux/linux-yocto-rt_4.4.bb
+++ /dev/null
@@ -1,36 +0,0 @@
-KBRANCH ?= "standard/preempt-rt/base"
-
-require recipes-kernel/linux/linux-yocto.inc
-
-# Skip processing of this recipe if it is not explicitly specified as the
-# PREFERRED_PROVIDER for virtual/kernel. This avoids errors when trying
-# to build multiple virtual/kernel providers, e.g. as dependency of
-# core-image-rt-sdk, core-image-rt.
-python () {
-    if d.getVar("KERNEL_PACKAGE_NAME") == "kernel" and d.getVar("PREFERRED_PROVIDER_virtual/kernel") != "linux-yocto-rt":
-        raise bb.parse.SkipRecipe("Set PREFERRED_PROVIDER_virtual/kernel to linux-yocto-rt to enable it")
-}
-
-SRCREV_machine ?= "d5efeeeb928a0111fc187fd1e8d03d2e4e35d4a0"
-SRCREV_meta ?= "b149d14ccae8349ab33e101f6af233a12f4b17ba"
-
-SRC_URI = "git://git.yoctoproject.org/linux-yocto-4.4.git;branch=${KBRANCH};name=machine \
-           git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-4.4;destsuffix=${KMETA}"
-
-LINUX_VERSION ?= "4.4.113"
-
-PV = "${LINUX_VERSION}+git${SRCPV}"
-
-KMETA = "kernel-meta"
-KCONF_BSP_AUDIT_LEVEL = "2"
-
-LINUX_KERNEL_TYPE = "preempt-rt"
-
-COMPATIBLE_MACHINE = "(qemux86|qemux86-64|qemuarm|qemuppc|qemumips)"
-
-# Functionality flags
-KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc features/taskstats/taskstats.scc"
-KERNEL_FEATURES_append = " ${KERNEL_EXTRA_FEATURES}"
-KERNEL_FEATURES_append_qemuall=" cfg/virtio.scc"
-KERNEL_FEATURES_append_qemux86=" cfg/sound.scc cfg/paravirt_kvm.scc"
-KERNEL_FEATURES_append_qemux86-64=" cfg/sound.scc"
diff --git a/common/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend b/common/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend
deleted file mode 100644
index 63333b20..00000000
--- a/common/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend
+++ /dev/null
@@ -1,4 +0,0 @@
-require linux-yocto-common_4.4.inc
-
-KBRANCH_amdx86 ?= "standard/preempt-rt/base"
-SRCREV_machine_amdx86 ?= "76a02384d86df7b7499755f1650b5299740f5473"
diff --git a/common/recipes-kernel/linux/linux-yocto_4.4.bb b/common/recipes-kernel/linux/linux-yocto_4.4.bb
deleted file mode 100644
index 97c16d59..00000000
--- a/common/recipes-kernel/linux/linux-yocto_4.4.bb
+++ /dev/null
@@ -1,42 +0,0 @@
-KBRANCH ?= "standard/base"
-
-require recipes-kernel/linux/linux-yocto.inc
-
-# board specific branches
-KBRANCH_qemuarm  ?= "standard/arm-versatile-926ejs"
-KBRANCH_qemuarm64 ?= "standard/qemuarm64"
-KBRANCH_qemumips ?= "standard/mti-malta32"
-KBRANCH_qemuppc  ?= "standard/qemuppc"
-KBRANCH_qemux86  ?= "standard/base"
-KBRANCH_qemux86-64 ?= "standard/base"
-KBRANCH_qemumips64 ?= "standard/mti-malta64"
-
-SRCREV_machine_qemuarm ?= "400c0f39b954cd8fffdf53e6ec97852b73fea7af"
-SRCREV_machine_qemuarm64 ?= "4d31a8b7661509ff1044abcf9050750cc2478e20"
-SRCREV_machine_qemumips ?= "fb03a9472367b6c177729ac631326aafd5d17c92"
-SRCREV_machine_qemuppc ?= "4d31a8b7661509ff1044abcf9050750cc2478e20"
-SRCREV_machine_qemux86 ?= "4d31a8b7661509ff1044abcf9050750cc2478e20"
-SRCREV_machine_qemux86-64 ?= "4d31a8b7661509ff1044abcf9050750cc2478e20"
-SRCREV_machine_qemumips64 ?= "26b8ba186a6d39728fc1510bd2264110c75842f5"
-SRCREV_machine ?= "4d31a8b7661509ff1044abcf9050750cc2478e20"
-SRCREV_meta ?= "b149d14ccae8349ab33e101f6af233a12f4b17ba"
-
-SRC_URI = "git://git.yoctoproject.org/linux-yocto-4.4.git;name=machine;branch=${KBRANCH}; \
-           git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-4.4;destsuffix=${KMETA}"
-
-LINUX_VERSION ?= "4.4.113"
-
-PV = "${LINUX_VERSION}+git${SRCPV}"
-
-KMETA = "kernel-meta"
-KCONF_BSP_AUDIT_LEVEL = "2"
-
-COMPATIBLE_MACHINE = "qemuarm|qemuarm64|qemux86|qemuppc|qemumips|qemumips64|qemux86-64"
-
-# Functionality flags
-KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc"
-KERNEL_FEATURES_append = " ${KERNEL_EXTRA_FEATURES}"
-KERNEL_FEATURES_append_qemuall=" cfg/virtio.scc"
-KERNEL_FEATURES_append_qemux86=" cfg/sound.scc cfg/paravirt_kvm.scc"
-KERNEL_FEATURES_append_qemux86-64=" cfg/sound.scc cfg/paravirt_kvm.scc"
-KERNEL_FEATURES_append = " ${@bb.utils.contains("TUNE_FEATURES", "mx32", " cfg/x32.scc", "" ,d)}"
diff --git a/common/recipes-kernel/linux/linux-yocto_4.4.bbappend b/common/recipes-kernel/linux/linux-yocto_4.4.bbappend
deleted file mode 100644
index 7d5f09a8..00000000
--- a/common/recipes-kernel/linux/linux-yocto_4.4.bbappend
+++ /dev/null
@@ -1,11 +0,0 @@
-require linux-yocto-common_4.4.inc
-
-KBRANCH_amdx86 ?= "standard/base"
-SRCREV_machine_amdx86 ?= "7d1401a0dd9bebfe49937ca7d9785972e0cc76d0"
-
-SRC_URI_append_radeon += " \
-	file://radeon-microcode.cfg \
-	file://radeon-console.cfg \
-	file://radeon-gpu-config.cfg \
-"
-